diff --git a/coverage/cgfs_fext/RV32Zcd/fld.cgf b/coverage/cgfs_fext/RV32Zcd/fld.cgf new file mode 100644 index 000000000..4c42779df --- /dev/null +++ b/coverage/cgfs_fext/RV32Zcd/fld.cgf @@ -0,0 +1,67 @@ +c.fld: + config: + - check ISA:=regex(.*I.*F.*D.*C.*) + mnemonics: + c.fld: 0 + rs1: + <<: *c_regs + rd: + <<: *c_fregs + op_comb: + 'rs1 != rd': 0 + val_comb: + 'imm_val > 0 and fcsr == 0': 0 + 'imm_val == 0 and fcsr == 0': 0 + abstract_comb: + 'walking_ones("imm_val",5,False, scale_func = lambda x: x*8)': 0 + 'walking_zeros("imm_val",5,False, scale_func = lambda x: x*8)': 0 + 'alternate("imm_val",5, False,scale_func = lambda x: x*8)': 0 + +c.fsd: + config: + - check ISA:=regex(.*I.*F.*D.*C.*) + opcode: + c.fsd: 0 + rs1: + <<: *c_regs + rs2: + <<: *c_fregs + op_comb: + 'rs1 != rs2': 0 + val_comb: + 'imm_val > 0': 0 + 'imm_val == 0': 0 + abstract_comb: + 'walking_ones("imm_val",5,False, scale_func = lambda x: x*8)': 0 + 'walking_zeros("imm_val",5,False, scale_func = lambda x: x*8)': 0 + 'alternate("imm_val",5, False,scale_func = lambda x: x*8)': 0 + +c.fldsp: + config: + - check ISA:=regex(.*I.*F.*D.*C.*) + opcode: + c.fldsp: 0 + rd: + <<: *all_fregs + val_comb: + 'imm_val > 0': 0 + 'imm_val == 0': 0 + abstract_comb: + 'walking_ones("imm_val",6,False, scale_func = lambda x: x*8)': 0 + 'walking_zeros("imm_val",6,False, scale_func = lambda x: x*8)': 0 + 'alternate("imm_val",6, False,scale_func = lambda x: x*8)': 0 + +c.fsdsp: + config: + - check ISA:=regex(.*I.*F.*D.*C.*) + opcode: + c.fsdsp: 0 + rs2: + <<: *all_fregs + val_comb: + 'imm_val > 0': 0 + 'imm_val == 0': 0 + abstract_comb: + 'walking_ones("imm_val",6,False, scale_func = lambda x: x*8)': 0 + 'walking_zeros("imm_val",6,False, scale_func = lambda x: x*8)': 0 + 'alternate("imm_val",6, False,scale_func = lambda x: x*8)': 0 diff --git a/coverage/cgfs_fext/RV32Zcf/flw.cgf b/coverage/cgfs_fext/RV32Zcf/flw.cgf new file mode 100644 index 000000000..3442d59f0 --- /dev/null +++ b/coverage/cgfs_fext/RV32Zcf/flw.cgf @@ -0,0 +1,65 @@ +c.flw: + config: + - check ISA:=regex(.*I.*F.*C.*) + mnemonics: + c.flw: 0 + rs1: + <<: *c_regs + rd: + <<: *c_fregs + val_comb: + 'imm_val > 0 and fcsr == 0': 0 + 'imm_val == 0 and fcsr == 0': 0 + abstract_comb: + 'walking_ones("imm_val",5,False, scale_func = lambda x: x*4)': 0 + 'walking_zeros("imm_val",5,False, scale_func = lambda x: x*4)': 0 + 'alternate("imm_val",5, False,scale_func = lambda x: x*4)': 0 + +c.flwsp: + config: + - check ISA:=regex(.*I.*F.*C.*) + opcode: + c.flwsp: 0 + rd: + <<: *c_fregs + val_comb: + 'imm_val > 0 and fcsr == 0': 0 + 'imm_val == 0 and fcsr == 0': 0 + abstract_comb: + 'walking_ones("imm_val",6,False, scale_func = lambda x: x*4)': 0 + 'walking_zeros("imm_val",6,False, scale_func = lambda x: x*4)': 0 + 'alternate("imm_val",6, False,scale_func = lambda x: x*4)': 0 + +c.fsw: + config: + - check ISA:=regex(.*I.*F.*C.*) + opcode: + c.fsw: 0 + rs1: + <<: *c_regs + rs2: + <<: *c_fregs + op_comb: + 'rs1 != rs2': 0 + val_comb: + 'imm_val > 0': 0 + 'imm_val == 0': 0 + abstract_comb: + 'walking_ones("imm_val",5,False, scale_func = lambda x: x*4)': 0 + 'walking_zeros("imm_val",5,False, scale_func = lambda x: x*4)': 0 + 'alternate("imm_val",5, False,scale_func = lambda x: x*4)': 0 + +c.fswsp: + config: + - check ISA:=regex(.*I.*F.*C.*) + opcode: + c.fswsp: 0 + rs2: + <<: *c_fregs + val_comb: + 'imm_val > 0': 0 + 'imm_val == 0': 0 + abstract_comb: + 'walking_ones("imm_val",6,False, scale_func = lambda x: x*4)': 0 + 'walking_zeros("imm_val",6,False, scale_func = lambda x: x*4)': 0 + 'alternate("imm_val",6, False,scale_func = lambda x: x*4)': 0 diff --git a/coverage/cgfs_fext/RV32Zhinx/rv32h_fadd.cgf b/coverage/cgfs_fext/RV32Zhinx/rv32h_fadd.cgf new file mode 100644 index 000000000..3caa84fed --- /dev/null +++ b/coverage/cgfs_fext/RV32Zhinx/rv32h_fadd.cgf @@ -0,0 +1,188 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fadd_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fadd.h", 2,True)': 0 + +fadd_b2: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b2(flen,16, "fadd.h", 2,True)': 0 + +fadd_b3: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b3(flen,16, "fadd.h", 2,True)': 0 + +fadd_b4: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b4(flen,16, "fadd.h", 2,True)': 0 + +fadd_b5: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b5(flen,16, "fadd.h", 2,True)': 0 + +fadd_b7: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b7(flen,16, "fadd.h", 2,True)': 0 + +fadd_b8: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b8(flen,16, "fadd.h", 2,True)': 0 + +fadd_b10: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b10(flen,16, "fadd.h", 2,True)': 0 + +fadd_b11: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b11(flen,16, "fadd.h", 2,True)': 0 + +fadd_b12: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b12(flen,16, "fadd.h", 2,True)': 0 + +fadd_b13: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b13(flen,16, "fadd.h", 2,True)': 0 diff --git a/coverage/cgfs_fext/RV32Zhinx/rv32h_fclass.cgf b/coverage/cgfs_fext/RV32Zhinx/rv32h_fclass.cgf new file mode 100644 index 000000000..07bca6f11 --- /dev/null +++ b/coverage/cgfs_fext/RV32Zhinx/rv32h_fclass.cgf @@ -0,0 +1,15 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fclass_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fclass.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fclass.h", 1,True)': 0 + diff --git a/coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.d.h.cgf b/coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.d.h.cgf new file mode 100644 index 000000000..1d47c5cfe --- /dev/null +++ b/coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.d.h.cgf @@ -0,0 +1,106 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.d.h_b1: + config: + - check ISA:=regex(.*I.*F.*D.*Zfh.*) + mnemonics: + fcvt.d.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fcvt.d.h", 1)': 0 + +fcvt.d.h_b22: + config: + - check ISA:=regex(.*I.*F.*D.*Zfh.*) + mnemonics: + fcvt.d.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b22(flen,16, "fcvt.d.h", 1)': 0 + +fcvt.d.h_b23: + config: + - check ISA:=regex(.*I.*F.*D.*Zfh.*) + mnemonics: + fcvt.d.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b23(flen,16, "fcvt.d.h", 1)': 0 + +fcvt.d.h_b24: + config: + - check ISA:=regex(.*I.*F.*D.*Zfh.*) + mnemonics: + fcvt.d.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b24(flen,16, "fcvt.d.h", 1)': 0 + +fcvt.d.h_b27: + config: + - check ISA:=regex(.*I.*F.*D.*Zfh.*) + mnemonics: + fcvt.d.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b27(flen,16, "fcvt.d.h", 1)': 0 + +fcvt.d.h_b28: + config: + - check ISA:=regex(.*I.*F.*D.*Zfh.*) + mnemonics: + fcvt.d.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b28(flen,16, "fcvt.d.h", 1)': 0 + +fcvt.d.h_b29: + config: + - check ISA:=regex(.*I.*F.*D.*Zfh.*) + mnemonics: + fcvt.d.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b29(flen,16, "fcvt.d.h", 1)': 0 diff --git a/coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.h.d.cgf b/coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.h.d.cgf new file mode 100644 index 000000000..07af2333d --- /dev/null +++ b/coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.h.d.cgf @@ -0,0 +1,106 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.h.d_b1: + config: + - check ISA:=regex(.*I.*F.*D.*Zfh.*) + mnemonics: + fcvt.h.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,64, "fcvt.h.d", 1)': 0 + +fcvt.h.d_b22: + config: + - check ISA:=regex(.*I.*F.*D.*Zfh.*) + mnemonics: + fcvt.h.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b22(flen,64, "fcvt.h.d", 1)': 0 + +fcvt.h.d_b23: + config: + - check ISA:=regex(.*I.*F.*D.*Zfh.*) + mnemonics: + fcvt.h.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b23(flen,64, "fcvt.h.d", 1)': 0 + +fcvt.h.d_b24: + config: + - check ISA:=regex(.*I.*F.*D.*Zfh.*) + mnemonics: + fcvt.h.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b24(flen,64, "fcvt.h.d", 1)': 0 + +fcvt.h.d_b27: + config: + - check ISA:=regex(.*I.*F.*D.*Zfh.*) + mnemonics: + fcvt.h.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b27(flen,64, "fcvt.h.d", 1)': 0 + +fcvt.h.d_b28: + config: + - check ISA:=regex(.*I.*F.*D.*Zfh.*) + mnemonics: + fcvt.h.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b28(flen,64, "fcvt.h.d", 1)': 0 + +fcvt.h.d_b29: + config: + - check ISA:=regex(.*I.*F.*D.*Zfh.*) + mnemonics: + fcvt.h.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b29(flen,64, "fcvt.h.d", 1)': 0 diff --git a/coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.h.l.cgf b/coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.h.l.cgf new file mode 100644 index 000000000..45e9c45fe --- /dev/null +++ b/coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.h.l.cgf @@ -0,0 +1,27 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.h.l_b25: + config: + - check ISA:=regex(.*I.*F.*D.*Zfh.*) + opcode: + fcvt.h.l: 0 + rs1: + <<: *all_regs + rd: + <<: *all_fregs + val_comb: + abstract_comb: + 'ibm_b25(flen,16, "fcvt.h.l", 1)': 0 + +fcvt.h.l_b26: + config: + - check ISA:=regex(.*I.*F.*D.*Zfh.*) + opcode: + fcvt.h.l: 0 + rs1: + <<: *all_regs + rd: + <<: *all_fregs + val_comb: + abstract_comb: + 'ibm_b26(16, "fcvt.h.l", 1)': 0 diff --git a/coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.h.lu.cgf b/coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.h.lu.cgf new file mode 100644 index 000000000..886da1506 --- /dev/null +++ b/coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.h.lu.cgf @@ -0,0 +1,27 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.h.lu_b25: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fcvt.h.lu: 0 + rs1: + <<: *all_regs + rd: + <<: *all_fregs + val_comb: + abstract_comb: + 'ibm_b25(flen,16, "fcvt.h.lu", 1)': 0 + +fcvt.h.lu_b26: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fcvt.h.lu: 0 + rs1: + <<: *all_regs + rd: + <<: *all_fregs + val_comb: + abstract_comb: + 'ibm_b26(16, "fcvt.h.lu", 1)': 0 diff --git a/coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.h.s.cgf b/coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.h.s.cgf new file mode 100644 index 000000000..5ddc2fa50 --- /dev/null +++ b/coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.h.s.cgf @@ -0,0 +1,106 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.h.s_b1: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fcvt.h.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,32, "fcvt.h.s", 1)': 0 + +fcvt.h.s_b22: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fcvt.h.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b22(flen,32, "fcvt.h.s", 1)': 0 + +fcvt.h.s_b23: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fcvt.h.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b23(flen,32, "fcvt.h.s", 1)': 0 + +fcvt.h.s_b24: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fcvt.h.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b24(flen,32, "fcvt.h.s", 1)': 0 + +fcvt.h.s_b27: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fcvt.h.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b27(flen,32, "fcvt.h.s", 1)': 0 + +fcvt.h.s_b28: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fcvt.h.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b28(flen,32, "fcvt.h.s", 1)': 0 + +fcvt.h.s_b29: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fcvt.h.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b29(flen,32, "fcvt.h.s", 1)': 0 diff --git a/coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.h.w.cgf b/coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.h.w.cgf new file mode 100644 index 000000000..e6ef94a8a --- /dev/null +++ b/coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.h.w.cgf @@ -0,0 +1,14 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.h.w_b25: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fcvt.h.w: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b25(flen,32, "fcvt.h.w", 1,True)': 0 diff --git a/coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.h.wu.cgf b/coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.h.wu.cgf new file mode 100644 index 000000000..c34ffa553 --- /dev/null +++ b/coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.h.wu.cgf @@ -0,0 +1,15 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.h.wu_b25: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fcvt.h.wu: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b25(flen,32, "fcvt.h.wu", 1,True)': 0 + diff --git a/coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.s.h.cgf b/coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.s.h.cgf new file mode 100644 index 000000000..ba74626b1 --- /dev/null +++ b/coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.s.h.cgf @@ -0,0 +1,106 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.s.h_b1: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + mnemonics: + fcvt.s.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fcvt.s.h", 1)': 0 + +fcvt.s.h_b22: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + mnemonics: + fcvt.s.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b22(flen,16, "fcvt.s.h", 1)': 0 + +fcvt.s.h_b23: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + mnemonics: + fcvt.s.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b23(flen,16, "fcvt.s.h", 1)': 0 + +fcvt.s.h_b24: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + mnemonics: + fcvt.s.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b24(flen,16, "fcvt.s.h", 1)': 0 + +fcvt.s.h_b27: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + mnemonics: + fcvt.s.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b27(flen,16, "fcvt.s.h", 1)': 0 + +fcvt.s.h_b28: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + mnemonics: + fcvt.s.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b28(flen,16, "fcvt.s.h", 1)': 0 + +fcvt.s.h_b29: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + mnemonics: + fcvt.s.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b29(flen,16, "fcvt.s.h", 1)': 0 diff --git a/coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.w.h.cgf b/coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.w.h.cgf new file mode 100644 index 000000000..f419ba9fd --- /dev/null +++ b/coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.w.h.cgf @@ -0,0 +1,92 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.w.h_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fcvt.w.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fcvt.w.h", 1,True)': 0 + +fcvt.w.h_b22: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fcvt.w.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b22(flen,16, "fcvt.w.h", 1,True)': 0 + +fcvt.w.h_b23: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fcvt.w.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b23(flen,16, "fcvt.w.h", 1,True)': 0 + +fcvt.w.h_b24: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fcvt.w.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b24(flen,16, "fcvt.w.h", 1,True)': 0 + +fcvt.w.h_b27: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fcvt.w.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b27(flen,16, "fcvt.w.h", 1,True)': 0 + +fcvt.w.h_b28: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fcvt.w.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b28(flen,16, "fcvt.w.h", 1,True)': 0 + +fcvt.w.h_b29: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fcvt.w.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b29(flen,16, "fcvt.w.h", 1,True)': 0 diff --git a/coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.wu.h.cgf b/coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.wu.h.cgf new file mode 100644 index 000000000..99c988d3f --- /dev/null +++ b/coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.wu.h.cgf @@ -0,0 +1,92 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.wu.h_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fcvt.wu.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fcvt.wu.h", 1,True)': 0 + +fcvt.wu.h_b22: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fcvt.wu.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b22(flen,16, "fcvt.wu.h", 1,True)': 0 + +fcvt.wu.h_b23: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fcvt.wu.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b23(flen,16, "fcvt.wu.h", 1,True)': 0 + +fcvt.wu.h_b24: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fcvt.wu.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b24(flen,16, "fcvt.wu.h", 1,True)': 0 + +fcvt.wu.h_b27: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fcvt.wu.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b27(flen,16, "fcvt.wu.h", 1,True)': 0 + +fcvt.wu.h_b28: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fcvt.wu.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b28(flen,16, "fcvt.wu.h", 1,True)': 0 + +fcvt.wu.h_b29: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fcvt.wu.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b29(flen,16, "fcvt.wu.h", 1,True)': 0 diff --git a/coverage/cgfs_fext/RV32Zhinx/rv32h_fdiv.cgf b/coverage/cgfs_fext/RV32Zhinx/rv32h_fdiv.cgf new file mode 100644 index 000000000..ab470aa72 --- /dev/null +++ b/coverage/cgfs_fext/RV32Zhinx/rv32h_fdiv.cgf @@ -0,0 +1,188 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fdiv_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fdiv.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fdiv.h", 2,True)': 0 + +fdiv_b2: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fdiv.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b2(flen,16, "fdiv.h", 2,True)': 0 + +fdiv_b3: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fdiv.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b3(flen,16, "fdiv.h", 2,True)': 0 + +fdiv_b4: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fdiv.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b4(flen,16, "fdiv.h", 2,True)': 0 + +fdiv_b5: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fdiv.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b5(flen,16, "fdiv.h", 2,True)': 0 + +fdiv_b6: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fdiv.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b6(flen,16, "fdiv.h", 2,True)': 0 + +fdiv_b7: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fdiv.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b7(flen,16, "fdiv.h", 2,True)': 0 + +fdiv_b8: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fdiv.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b8(flen,16, "fdiv.h", 2,True)': 0 + +fdiv_b9: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fdiv.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b9(flen,16, "fdiv.h", 2,True)': 0 + +fdiv_b20: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fdiv.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b20(flen,16, "fdiv.h", 2,True)': 0 + +fdiv_b21: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fdiv.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b21(flen,16, "fdiv.h", 2,True)': 0 diff --git a/coverage/cgfs_fext/RV32Zhinx/rv32h_feq.cgf b/coverage/cgfs_fext/RV32Zhinx/rv32h_feq.cgf new file mode 100644 index 000000000..3b173a2f5 --- /dev/null +++ b/coverage/cgfs_fext/RV32Zhinx/rv32h_feq.cgf @@ -0,0 +1,35 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +feq_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + feq.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "feq.h", 2,True)': 0 + +feq_b19: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + feq.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b19(flen,16, "feq.h", 2,True)': 0 diff --git a/coverage/cgfs_fext/RV32Zhinx/rv32h_fle.cgf b/coverage/cgfs_fext/RV32Zhinx/rv32h_fle.cgf new file mode 100644 index 000000000..ad31c31f6 --- /dev/null +++ b/coverage/cgfs_fext/RV32Zhinx/rv32h_fle.cgf @@ -0,0 +1,35 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fle_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fle.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fle.h", 2,True)': 0 + +fle_b19: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fle.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b19(flen,16, "fle.h", 2,True)': 0 diff --git a/coverage/cgfs_fext/RV32Zhinx/rv32h_flt.cgf b/coverage/cgfs_fext/RV32Zhinx/rv32h_flt.cgf new file mode 100644 index 000000000..8ec408fb1 --- /dev/null +++ b/coverage/cgfs_fext/RV32Zhinx/rv32h_flt.cgf @@ -0,0 +1,35 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +flt_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + flt.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen, 16, "flt.h", 2,True)': 0 + +flt_b19: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + flt.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b19(flen,16, "flt.h", 2,True)': 0 diff --git a/coverage/cgfs_fext/RV32Zhinx/rv32h_fmadd.cgf b/coverage/cgfs_fext/RV32Zhinx/rv32h_fmadd.cgf new file mode 100644 index 000000000..c80e44013 --- /dev/null +++ b/coverage/cgfs_fext/RV32Zhinx/rv32h_fmadd.cgf @@ -0,0 +1,229 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fmadd_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fmadd.h", 3,True)': 0 + +fmadd_b2: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b2(flen,16, "fmadd.h", 3,True)': 0 + +fmadd_b3: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b3(flen,16, "fmadd.h", 3,True)': 0 + +fmadd_b4: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b4(flen,16, "fmadd.h", 3,True)': 0 + +fmadd_b5: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b5(flen,16, "fmadd.h", 3,True)': 0 + +fmadd_b6: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b6(flen,16, "fmadd.h", 3,True)': 0 + +fmadd_b7: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b7(flen,16, "fmadd.h", 3,True)': 0 + +fmadd_b8: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b8(flen,16, "fmadd.h", 3,True)': 0 + +fmadd_b14: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b14(flen,16, "fmadd.h", 3,True)': 0 + +fmadd_b16: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b16(flen,16, "fmadd.h", 3,True)': 0 + +fmadd_b17: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b17(flen,16, "fmadd.h", 3,True)': 0 + +fmadd_b18: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b18(flen,16, "fmadd.h", 3,True)': 0 diff --git a/coverage/cgfs_fext/RV32Zhinx/rv32h_fmax.cgf b/coverage/cgfs_fext/RV32Zhinx/rv32h_fmax.cgf new file mode 100644 index 000000000..3cf803847 --- /dev/null +++ b/coverage/cgfs_fext/RV32Zhinx/rv32h_fmax.cgf @@ -0,0 +1,35 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fmax_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmax.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fmax.h", 2,True)': 0 + +fmax_b19: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmax.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b19(flen,16, "fmax.h", 2,True)': 0 diff --git a/coverage/cgfs_fext/RV32Zhinx/rv32h_fmin.cgf b/coverage/cgfs_fext/RV32Zhinx/rv32h_fmin.cgf new file mode 100644 index 000000000..77db040ca --- /dev/null +++ b/coverage/cgfs_fext/RV32Zhinx/rv32h_fmin.cgf @@ -0,0 +1,35 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fmin_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmin.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fmin.h", 2,True)': 0 + +fmin_b19: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmin.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b19(flen,16, "fmin.h", 2,True)': 0 diff --git a/coverage/cgfs_fext/RV32Zhinx/rv32h_fmsub.cgf b/coverage/cgfs_fext/RV32Zhinx/rv32h_fmsub.cgf new file mode 100644 index 000000000..de52f5045 --- /dev/null +++ b/coverage/cgfs_fext/RV32Zhinx/rv32h_fmsub.cgf @@ -0,0 +1,229 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fmsub_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fmsub.h", 3,True)': 0 + +fmsub_b2: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b2(flen,16, "fmsub.h", 3,True)': 0 + +fmsub_b3: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b3(flen,16, "fmsub.h", 3,True)': 0 + +fmsub_b4: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b4(flen,16, "fmsub.h", 3,True)': 0 + +fmsub_b5: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b5(flen,16, "fmsub.h", 3,True)': 0 + +fmsub_b6: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b6(flen,16, "fmsub.h", 3,True)': 0 + +fmsub_b7: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b7(flen,16, "fmsub.h", 3,True)': 0 + +fmsub_b8: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b8(flen,16, "fmsub.h", 3,True)': 0 + +fmsub_b14: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b14(flen,16, "fmsub.h", 3,True)': 0 + +fmsub_b16: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b16(flen,16, "fmsub.h", 3,True)': 0 + +fmsub_b17: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b17(flen,16, "fmsub.h", 3,True)': 0 + +fmsub_b18: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b18(flen,16, "fmsub.h", 3,True)': 0 diff --git a/coverage/cgfs_fext/RV32Zhinx/rv32h_fmul.cgf b/coverage/cgfs_fext/RV32Zhinx/rv32h_fmul.cgf new file mode 100644 index 000000000..626248b13 --- /dev/null +++ b/coverage/cgfs_fext/RV32Zhinx/rv32h_fmul.cgf @@ -0,0 +1,155 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fmul_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmul.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fmul.h", 2,True)': 0 + +fmul_b2: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmul.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b2(flen,16, "fmul.h", 2,True)': 0 + +fmul_b3: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmul.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b3(flen,16, "fmul.h", 2,True)': 0 + +fmul_b4: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmul.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b4(flen,16, "fmul.h", 2,True)': 0 + +fmul_b5: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmul.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b5(flen,16, "fmul.h", 2,True)': 0 + +fmul_b6: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmul.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b6(flen,16, "fmul.h", 2,True)': 0 + +fmul_b7: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmul.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b7(flen,16, "fmul.h", 2,True)': 0 + +fmul_b8: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmul.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b8(flen,16, "fmul.h", 2,True)': 0 + +fmul_b9: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmul.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b9(flen,16, "fmul.h", 2,True)': 0 + diff --git a/coverage/cgfs_fext/RV32Zhinx/rv32h_fnmadd.cgf b/coverage/cgfs_fext/RV32Zhinx/rv32h_fnmadd.cgf new file mode 100644 index 000000000..3c435167c --- /dev/null +++ b/coverage/cgfs_fext/RV32Zhinx/rv32h_fnmadd.cgf @@ -0,0 +1,229 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fnmadd_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fnmadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fnmadd.h", 3,True)': 0 + +fnmadd_b2: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fnmadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b2(flen,16, "fnmadd.h", 3,True)': 0 + +fnmadd_b3: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fnmadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b3(flen,16, "fnmadd.h", 3,True)': 0 + +fnmadd_b4: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fnmadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b4(flen,16, "fnmadd.h", 3,True)': 0 + +fnmadd_b5: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fnmadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b5(flen,16, "fnmadd.h", 3,True)': 0 + +fnmadd_b6: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fnmadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b6(flen,16, "fnmadd.h", 3,True)': 0 + +fnmadd_b7: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fnmadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b7(flen,16, "fnmadd.h", 3,True)': 0 + +fnmadd_b8: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fnmadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b8(flen,16, "fnmadd.h", 3,True)': 0 + +fnmadd_b14: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fnmadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b14(flen,16, "fnmadd.h", 3,True)': 0 + +fnmadd_b16: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fnmadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b16(flen,16, "fnmadd.h", 3,True)': 0 + +fnmadd_b17: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fnmadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b17(flen,16, "fnmadd.h", 3,True)': 0 + +fnmadd_b18: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fnmadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b18(flen,16, "fnmadd.h", 3,True)': 0 diff --git a/coverage/cgfs_fext/RV32Zhinx/rv32h_fnmsub.cgf b/coverage/cgfs_fext/RV32Zhinx/rv32h_fnmsub.cgf new file mode 100644 index 000000000..c7005ecd2 --- /dev/null +++ b/coverage/cgfs_fext/RV32Zhinx/rv32h_fnmsub.cgf @@ -0,0 +1,229 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fnmsub_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fnmsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fnmsub.h", 3,True)': 0 + +fnmsub_b2: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fnmsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b2(flen,16, "fnmsub.h", 3,True)': 0 + +fnmsub_b3: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fnmsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b3(flen,16, "fnmsub.h", 3,True)': 0 + +fnmsub_b4: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fnmsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b4(flen,16, "fnmsub.h", 3,True)': 0 + +fnmsub_b5: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fnmsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b5(flen,16, "fnmsub.h", 3,True)': 0 + +fnmsub_b6: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fnmsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b6(flen,16, "fnmsub.h", 3,True)': 0 + +fnmsub_b7: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fnmsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b7(flen,16, "fnmsub.h", 3,True)': 0 + +fnmsub_b8: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fnmsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b8(flen,16, "fnmsub.h", 3,True)': 0 + +fnmsub_b14: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fnmsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b14(flen,16, "fnmsub.h", 3,True)': 0 + +fnmsub_b16: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fnmsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b16(flen,16, "fnmsub.h", 3,True)': 0 + +fnmsub_b17: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fnmsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b17(flen,16, "fnmsub.h", 3,True)': 0 + +fnmsub_b18: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fnmsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b18(flen,16, "fnmsub.h", 3,True)': 0 diff --git a/coverage/cgfs_fext/RV32Zhinx/rv32h_fsgnj.cgf b/coverage/cgfs_fext/RV32Zhinx/rv32h_fsgnj.cgf new file mode 100644 index 000000000..21c89be37 --- /dev/null +++ b/coverage/cgfs_fext/RV32Zhinx/rv32h_fsgnj.cgf @@ -0,0 +1,19 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fsgnj_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fsgnj.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fsgnj.h", 2,True)': 0 + diff --git a/coverage/cgfs_fext/RV32Zhinx/rv32h_fsgnjn.cgf b/coverage/cgfs_fext/RV32Zhinx/rv32h_fsgnjn.cgf new file mode 100644 index 000000000..cc281a311 --- /dev/null +++ b/coverage/cgfs_fext/RV32Zhinx/rv32h_fsgnjn.cgf @@ -0,0 +1,19 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fsgnjn_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fsgnjn.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fsgnjn.h", 2,True)': 0 + diff --git a/coverage/cgfs_fext/RV32Zhinx/rv32h_fsgnjx.cgf b/coverage/cgfs_fext/RV32Zhinx/rv32h_fsgnjx.cgf new file mode 100644 index 000000000..07f17b4a2 --- /dev/null +++ b/coverage/cgfs_fext/RV32Zhinx/rv32h_fsgnjx.cgf @@ -0,0 +1,19 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fsgnjx_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fsgnjx.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fsgnjx.h", 2,True)': 0 + diff --git a/coverage/cgfs_fext/RV32Zhinx/rv32h_fsqrt.cgf b/coverage/cgfs_fext/RV32Zhinx/rv32h_fsqrt.cgf new file mode 100644 index 000000000..3112744d3 --- /dev/null +++ b/coverage/cgfs_fext/RV32Zhinx/rv32h_fsqrt.cgf @@ -0,0 +1,136 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fsqrt_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fsqrt.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fsqrt.h", 1,True)': 0 + +fsqrt_b2: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fsqrt.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b2(flen,16, "fsqrt.h", 1,True)': 0 + +fsqrt_b3: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fsqrt.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b3(flen,16, "fsqrt.h", 1,True)': 0 + +fsqrt_b4: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fsqrt.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b4(flen,16, "fsqrt.h", 1,True)': 0 + +fsqrt_b5: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fsqrt.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b5(flen,16, "fsqrt.h", 1,True)': 0 + +fsqrt_b7: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fsqrt.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b7(flen,16, "fsqrt.h", 1,True)': 0 + +fsqrt_b8: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fsqrt.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b8(flen,16, "fsqrt.h", 1,True)': 0 + +fsqrt_b9: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fsqrt.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b9(flen,16, "fsqrt.h", 1,True)': 0 + +fsqrt_b20: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fsqrt.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b20(flen,16, "fsqrt.h", 1,True)': 0 diff --git a/coverage/cgfs_fext/RV32Zhinx/rv32h_fsub.cgf b/coverage/cgfs_fext/RV32Zhinx/rv32h_fsub.cgf new file mode 100644 index 000000000..1a3a8ecaa --- /dev/null +++ b/coverage/cgfs_fext/RV32Zhinx/rv32h_fsub.cgf @@ -0,0 +1,188 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fsub_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fsub.h", 2,True)': 0 + +fsub_b2: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b2(flen,16, "fsub.h", 2,True)': 0 + +fsub_b3: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b3(flen,16, "fsub.h", 2,True)': 0 + +fsub_b4: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b4(flen,16, "fsub.h", 2,True)': 0 + +fsub_b5: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b5(flen,16, "fsub.h", 2,True)': 0 + +fsub_b7: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b7(flen,16, "fsub.h", 2,True)': 0 + +fsub_b8: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b8(flen,16, "fsub.h", 2,True)': 0 + +fsub_b10: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b10(flen,16, "fsub.h", 2,True)': 0 + +fsub_b11: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b11(flen,16, "fsub.h", 2,True)': 0 + +fsub_b12: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b12(flen,16, "fsub.h", 2,True)': 0 + +fsub_b13: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b13(flen,16, "fsub.h", 2,True)': 0 diff --git a/coverage/cgfs_fext/RV64Zcd/fld.cgf b/coverage/cgfs_fext/RV64Zcd/fld.cgf new file mode 100644 index 000000000..4c42779df --- /dev/null +++ b/coverage/cgfs_fext/RV64Zcd/fld.cgf @@ -0,0 +1,67 @@ +c.fld: + config: + - check ISA:=regex(.*I.*F.*D.*C.*) + mnemonics: + c.fld: 0 + rs1: + <<: *c_regs + rd: + <<: *c_fregs + op_comb: + 'rs1 != rd': 0 + val_comb: + 'imm_val > 0 and fcsr == 0': 0 + 'imm_val == 0 and fcsr == 0': 0 + abstract_comb: + 'walking_ones("imm_val",5,False, scale_func = lambda x: x*8)': 0 + 'walking_zeros("imm_val",5,False, scale_func = lambda x: x*8)': 0 + 'alternate("imm_val",5, False,scale_func = lambda x: x*8)': 0 + +c.fsd: + config: + - check ISA:=regex(.*I.*F.*D.*C.*) + opcode: + c.fsd: 0 + rs1: + <<: *c_regs + rs2: + <<: *c_fregs + op_comb: + 'rs1 != rs2': 0 + val_comb: + 'imm_val > 0': 0 + 'imm_val == 0': 0 + abstract_comb: + 'walking_ones("imm_val",5,False, scale_func = lambda x: x*8)': 0 + 'walking_zeros("imm_val",5,False, scale_func = lambda x: x*8)': 0 + 'alternate("imm_val",5, False,scale_func = lambda x: x*8)': 0 + +c.fldsp: + config: + - check ISA:=regex(.*I.*F.*D.*C.*) + opcode: + c.fldsp: 0 + rd: + <<: *all_fregs + val_comb: + 'imm_val > 0': 0 + 'imm_val == 0': 0 + abstract_comb: + 'walking_ones("imm_val",6,False, scale_func = lambda x: x*8)': 0 + 'walking_zeros("imm_val",6,False, scale_func = lambda x: x*8)': 0 + 'alternate("imm_val",6, False,scale_func = lambda x: x*8)': 0 + +c.fsdsp: + config: + - check ISA:=regex(.*I.*F.*D.*C.*) + opcode: + c.fsdsp: 0 + rs2: + <<: *all_fregs + val_comb: + 'imm_val > 0': 0 + 'imm_val == 0': 0 + abstract_comb: + 'walking_ones("imm_val",6,False, scale_func = lambda x: x*8)': 0 + 'walking_zeros("imm_val",6,False, scale_func = lambda x: x*8)': 0 + 'alternate("imm_val",6, False,scale_func = lambda x: x*8)': 0 diff --git a/coverage/cgfs_fext/RV64Zhinx/rv64h_fcvt.h.l.cgf b/coverage/cgfs_fext/RV64Zhinx/rv64h_fcvt.h.l.cgf new file mode 100644 index 000000000..13dcae37c --- /dev/null +++ b/coverage/cgfs_fext/RV64Zhinx/rv64h_fcvt.h.l.cgf @@ -0,0 +1,14 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.h.l_b25: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fcvt.h.l: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b25(flen,64, "fcvt.h.l", 1,True)': 0 diff --git a/coverage/cgfs_fext/RV64Zhinx/rv64h_fcvt.h.lu.cgf b/coverage/cgfs_fext/RV64Zhinx/rv64h_fcvt.h.lu.cgf new file mode 100644 index 000000000..b7fbe149f --- /dev/null +++ b/coverage/cgfs_fext/RV64Zhinx/rv64h_fcvt.h.lu.cgf @@ -0,0 +1,14 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.h.lu_b25: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fcvt.h.lu: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b25(flen,64, "fcvt.h.lu", 1,True)': 0 diff --git a/coverage/cgfs_fext/RV64Zhinx/rv64h_fcvt.l.h.cgf b/coverage/cgfs_fext/RV64Zhinx/rv64h_fcvt.l.h.cgf new file mode 100644 index 000000000..54fd6dbc9 --- /dev/null +++ b/coverage/cgfs_fext/RV64Zhinx/rv64h_fcvt.l.h.cgf @@ -0,0 +1,104 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.l.h_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + mnemonics: + fcvt.l.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fcvt.l.h", 1,True)': 0 + +fcvt.l.h_b22: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + mnemonics: + fcvt.l.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b22(flen,16, "fcvt.l.h", 1, True)': 0 + +fcvt.l.h_b23: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + mnemonics: + fcvt.l.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b23(flen,16, "fcvt.l.h", 1, True)': 0 + +fcvt.l.h_b24: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + mnemonics: + fcvt.l.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b24(flen,16, "fcvt.l.h", 1, True)': 0 + +fcvt.l.h_b27: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + mnemonics: + fcvt.l.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b27(flen,16, "fcvt.l.h", 1, True)': 0 + +fcvt.l.h_b28: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + mnemonics: + fcvt.l.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b28(flen,16, "fcvt.l.h", 1, True)': 0 + +fcvt.l.h_b29: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + mnemonics: + fcvt.l.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b29(flen,16, "fcvt.l.h", 1, True)': 0 diff --git a/coverage/cgfs_fext/RV64Zhinx/rv64h_fcvt.lu.h.cgf b/coverage/cgfs_fext/RV64Zhinx/rv64h_fcvt.lu.h.cgf new file mode 100644 index 000000000..ab3cd99b2 --- /dev/null +++ b/coverage/cgfs_fext/RV64Zhinx/rv64h_fcvt.lu.h.cgf @@ -0,0 +1,104 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.lu.h_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + mnemonics: + fcvt.lu.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fcvt.lu.h", 1,True)': 0 + +fcvt.lu.h_b22: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + mnemonics: + fcvt.lu.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b22(flen,16, "fcvt.lu.h", 1, True)': 0 + +fcvt.lu.h_b23: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + mnemonics: + fcvt.lu.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b23(flen,16, "fcvt.lu.h", 1, True)': 0 + +fcvt.lu.h_b24: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + mnemonics: + fcvt.lu.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b24(flen,16, "fcvt.lu.h", 1, True)': 0 + +fcvt.lu.h_b27: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + mnemonics: + fcvt.lu.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b27(flen,16, "fcvt.lu.h", 1, True)': 0 + +fcvt.lu.h_b28: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + mnemonics: + fcvt.lu.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b28(flen,16, "fcvt.lu.h", 1, True)': 0 + +fcvt.lu.h_b29: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + mnemonics: + fcvt.lu.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b29(flen,16, "fcvt.lu.h", 1, True)': 0 diff --git a/coverage/dataset.cgf b/coverage/dataset.cgf index a1a1a01f4..b84b69dd8 100644 --- a/coverage/dataset.cgf +++ b/coverage/dataset.cgf @@ -180,6 +180,16 @@ datasets: x13: 0 x14: 0 x15: 0 + + c_fregs: &c_fregs + f8: 0 + f9: 0 + f10: 0 + f11: 0 + f12: 0 + f13: 0 + f14: 0 + f15: 0 all_regs_mx2: &all_regs_mx2 x1: 0 diff --git a/requirements.txt b/requirements.txt index 40b8fe2b0..7565af294 100755 --- a/requirements.txt +++ b/requirements.txt @@ -17,6 +17,7 @@ Jinja2 m2r2>=0.2.7 MarkupSafe>=1.1.1 mistune>=0.8.4 +ordered-set>=4.1.0 oyaml>=0.9 packaging>=19.0 pbr>=5.3.1 @@ -26,7 +27,7 @@ Pygments>=2.4.2 pyparsing>=2.4.0 pytablewriter pytest -python-constraint +python-constraint>=1.4.0 python-dateutil>=2.8.0 pytz>=2019.1 pyyaml diff --git a/riscv-ctg/riscv_ctg/constants.py b/riscv-ctg/riscv_ctg/constants.py index ccf8e4713..5cff5e542 100644 --- a/riscv-ctg/riscv_ctg/constants.py +++ b/riscv-ctg/riscv_ctg/constants.py @@ -3,6 +3,8 @@ import os from math import * from string import Template + +from ordered_set import OrderedSet from riscv_isac.fp_dataset import * root = os.path.abspath(os.path.dirname(__file__)) @@ -120,7 +122,7 @@ def gen_sign_dataset(bit_width): t1 =( '' if bit_width%2 == 0 else '1') + ''.join(['01']*int(bit_width/2)) t2 =( '' if bit_width%2 == 0 else '0') + ''.join(['10']*int(bit_width/2)) data += [twos(t1,bit_width),twos(t2,bit_width)] - return list(set(data)) + return list(OrderedSet(data)) def gen_usign_dataset(bit_width): ''' diff --git a/riscv-ctg/riscv_ctg/cross_comb.py b/riscv-ctg/riscv_ctg/cross_comb.py index e5a69ae77..23336aad3 100644 --- a/riscv-ctg/riscv_ctg/cross_comb.py +++ b/riscv-ctg/riscv_ctg/cross_comb.py @@ -122,7 +122,7 @@ def cross_comb(self, cgf_node): full_solution = [] if 'cross_comb' in cgf_node: - cross_comb = set(cgf_node['cross_comb']) + cross_comb = OrderedSet(cgf_node['cross_comb']) else: return @@ -210,7 +210,7 @@ def eval_conds(*oprs_lst): opr_lst += get_oprs(assgn) # Remove redundant operands - opr_lst = list(set(opr_lst)) + opr_lst = list(OrderedSet(opr_lst)) # Get possible instructions problem.reset() @@ -293,7 +293,7 @@ def exc_rd_zero(*oprs_lst): opr_lst = get_oprs(cond) opr_lst += get_oprs(assgn) - opr_lst = list(set(opr_lst)) + opr_lst = list(OrderedSet(opr_lst)) if data[i] in self.OP_TEMPLATE: # If single instruction instr = data[i] @@ -363,7 +363,7 @@ def exc_rd_zero(*oprs_lst): full_solution += [solution] - self.isa = list(set(isa_set)) + self.isa = list(OrderedSet(isa_set)) return full_solution def swreg(cross_comb_instrs): @@ -381,10 +381,10 @@ def swreg(cross_comb_instrs): if key != 'instr' and key != 'imm_val': op_vals.add(val) - swreg_sol = set(['x'+str(x) for x in range(0,32 if 'e' not in base_isa else 16)]) - op_vals + swreg_sol = OrderedSet(['x'+str(x) for x in range(0,32 if 'e' not in base_isa else 16)]) - op_vals sreg = random.choice(list(swreg_sol)) - freg_Sol = swreg_sol - set(sreg) + freg_Sol = swreg_sol - OrderedSet(sreg) freg = random.choice(list(freg_Sol)) return (sreg, freg) @@ -401,7 +401,7 @@ def get_reginit_str(cross_comb_instrs, freg): - List of initialization strings ''' - reg_init_lst = set() + reg_init_lst = OrderedSet() for instr_dict in cross_comb_instrs: if 'rd' in instr_dict: @@ -455,7 +455,7 @@ def write_test(self, fprefix, cgf_node, usage_str, cov_label, full_solution): sig_label = "signature_" + sreg + "_" + str(sreg_dict[sreg]) code = code + "\nRVTEST_SIGBASE(" + sreg + ", "+ sig_label + ")\n\n" - rd_lst = set() + rd_lst = OrderedSet() # Generate instruction corresponding to each instruction dictionary # Append signature update statements to store rd value after each instruction code += '// Cross-combination test sequence\n' diff --git a/riscv-ctg/riscv_ctg/csr_comb.py b/riscv-ctg/riscv_ctg/csr_comb.py index ef75d388c..0a6f6c486 100644 --- a/riscv-ctg/riscv_ctg/csr_comb.py +++ b/riscv-ctg/riscv_ctg/csr_comb.py @@ -267,7 +267,7 @@ def __init__(self, base_isa, xlen, randomize): def csr_comb(self, cgf_node): logger.debug('Generating tests for csr_comb') if 'csr_comb' in cgf_node: - csr_comb = set(cgf_node['csr_comb']) + csr_comb = OrderedSet(cgf_node['csr_comb']) else: return diff --git a/riscv-ctg/riscv_ctg/ctg.py b/riscv-ctg/riscv_ctg/ctg.py index 421562579..2828639b0 100644 --- a/riscv-ctg/riscv_ctg/ctg.py +++ b/riscv-ctg/riscv_ctg/ctg.py @@ -100,7 +100,7 @@ def gen_test(op_node, opcode): logger.info('Writing tests for csr_comb') csr_comb_gen.write_test(fprefix, node, usage_str, label, csr_comb_instr_dict) -def ctg(verbose, out, random ,xlen_arg,flen_arg, cgf_file,num_procs,base_isa, max_inst,inxFlag): +def ctg(verbose, out, random ,xlen_arg,flen_arg, cgf_file,num_procs,base_isa, max_inst,inxFlag,filter): logger.level(verbose) logger.info('****** RISC-V Compliance Test Generator {0} *******'.format(__version__ )) logger.info('Copyright (c) 2020, InCore Semiconductors Pvt. Ltd.') @@ -135,6 +135,12 @@ def ctg(verbose, out, random ,xlen_arg,flen_arg, cgf_file,num_procs,base_isa, ma op_template = utils.load_yaml(const.template_files) cgf = expand_cgf(cgf_file,xlen,flen) pool = mp.Pool(num_procs) - results = pool.starmap(create_test, [(usage_str, node,label,base_isa,max_inst, op_template, - randomize, out_dir, xlen, flen, inxFlag) for label,node in cgf.items()]) + + args_list = [] + for label,node in cgf.items(): + if filter is not None and re.search(filter, label) is None: + continue + args_list.append((usage_str, node,label,base_isa,max_inst, op_template, + randomize, out_dir, xlen, flen, inxFlag)) + results = pool.starmap(create_test, args_list) pool.close() diff --git a/riscv-ctg/riscv_ctg/data/imc.yaml b/riscv-ctg/riscv_ctg/data/imc.yaml index d77570efc..14fc7d9a1 100644 --- a/riscv-ctg/riscv_ctg/data/imc.yaml +++ b/riscv-ctg/riscv_ctg/data/imc.yaml @@ -1890,3 +1890,178 @@ c.jalr: // opcode: c.jalr; op1:$rs1 TEST_CJALR_OP($testreg, $rs1, $swreg, $offset) +c.flw: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *c_regs + rd_op_data: *c_fregs + xlen: [32] + std_op: + isa: + - IF_Zcf + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + formattype: 'clformat' + ea_align_data: '[0,1,2,3]' + rs1_val_data: '[0]' + imm_val_data: '[x*4 for x in gen_usign_dataset(5)]' + template: |- + // $comment + // opcode: $inst; op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align; flagreg:$flagreg; fcsr: $fcsr + TEST_LOAD_F($swreg,$testreg,$fcsr,$rs1,$rd,$imm_val,$inst,$ea_align,$flagreg) + +c.flwsp: + sig: + stride: 1 + sz: 'XLEN/8' + rd_op_data: *c_fregs + xlen: [32] + std_op: + isa: + - IF_Zcf + formattype: 'ciformat' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + ea_align_data: '[0,1,2,3]' + imm_val_data: '[x*4 for x in gen_usign_dataset(6)]' + template: |- + // $comment + // opcode: $inst op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align; flagreg:$flagreg; fcsr: $fcsr + TEST_LOAD_F($swreg,$testreg,$fcsr,$rs1,$rd,$imm_val,$inst,$ea_align,$flagreg) + +c.fsw: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32] + rs1_op_data: *c_regs + rs2_op_data: *c_fregs + std_op: + isa: + - IF_Zcf + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + formattype: 'csformat' + ea_align_data: '[0,1,2,3]' + rs1_val_data: '[0]' + rs2_val_data: 'gen_sign_dataset(xlen)' + imm_val_data: '[x*4 for x in gen_usign_dataset(5)]' + template: |- + // $comment + /* opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val; align:$ea_align; flagreg:$flagreg; + valreg: $valaddr_reg; valoffset: $val_offset + */ + TEST_STORE_F($swreg,$testreg,$fcsr,$rs1,$rs2,$imm_val,$offset,$inst,$ea_align,$flagreg,$valaddr_reg, $val_offset) + +c.fswsp: + sig: + stride: 1 + sz: 'XLEN/8' + rs2_op_data: *c_fregs + xlen: [32] + std_op: + isa: + - IF_Zcf + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + formattype: 'cssformat' + ea_align_data: '[0,1,2,3]' + rs2_val_data: 'gen_sign_dataset(xlen)' + imm_val_data: '[x*4 for x in gen_usign_dataset(6)]' + template: |- + // $comment + /* opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val; align:$ea_align; flagreg:$flagreg; + valreg: $valaddr_reg; valoffset: $val_offset + */ + TEST_STORE_F($swreg,$testreg,$fcsr,$rs1,$rs2,$imm_val,$offset,$inst,$ea_align,$flagreg,$valaddr_reg, $val_offset) + +c.fld: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: '8' + val_template: "''" + load_instr: "fld" + rs1_op_data: *c_regs + rd_op_data: *c_fregs + xlen: [32,64] + std_op: + isa: + - IFD_Zcd + formattype: 'clformat' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + ea_align_data: '[0,1,2,3]' + imm_val_data: '[x*8 for x in gen_usign_dataset(5)]' + template: |- + // $comment + // opcode: $inst; op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align; flagreg:$flagreg + TEST_LOAD_F($swreg,$testreg,$fcsr,$rs1,$rd,$imm_val,$inst,$ea_align,$flagreg) + +c.fldsp: + sig: + stride: 2 + sz: 'SIGALIGN' + rd_op_data: *c_fregs + xlen: [32,64] + std_op: + isa: + - IFD_Zcd + formattype: 'ciformat' + imm_val_data: '[x*8 for x in gen_usign_dataset(6)]' + template: |- + // $comment + // opcode: $inst; op1:x2; dest:$rd; immval:$imm_val; align:$ea_align; flagreg:x4 + TEST_LOAD_F($swreg,$testreg,$fcsr,x2,$rd,$imm_val,$inst,$ea_align,x4) + + +c.fsd: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "''" + load_instr: "FLREG" + rs1_op_data: *c_regs + rs2_op_data: *c_fregs + xlen: [32,64] + std_op: + isa: + - IFD_Zcd + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + formattype: 'csformat' + ea_align_data: '[0,1,2,3]' + rs2_val_data: 'gen_sign_dataset(xlen)' + imm_val_data: '[x*8 for x in gen_usign_dataset(5)]' + template: |- + // $comment + /* opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val; align:$ea_align; flagreg:$flagreg; + valreg: $valaddr_reg; valoffset: $val_offset + */ + TEST_STORE_F($swreg,$testreg,$fcsr,$rs1,$rs2,$imm_val,$offset,$inst,$ea_align,$flagreg,$valaddr_reg, $val_offset) + +c.fsdsp: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "''" + load_instr: "FLREG" + rs2_op_data: *c_fregs + xlen: [32,64] + std_op: + isa: + - IFD_Zcd + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + formattype: 'cssformat' + ea_align_data: '[0,1,2,3]' + rs2_val_data: 'gen_sign_dataset(xlen)' + imm_val_data: '[x*8 for x in gen_usign_dataset(6)]' + template: |- + // $comment + /* opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val; align:$ea_align; flagreg:$flagreg; + valreg: $valaddr_reg; valoffset: $val_offset + */ + TEST_STORE_F($swreg,$testreg,$fcsr,$rs1,$rs2,$imm_val,$offset,$inst,$ea_align,$flagreg,$valaddr_reg, $val_offset) diff --git a/riscv-ctg/riscv_ctg/data/inx.yaml b/riscv-ctg/riscv_ctg/data/inx.yaml index 867e6a914..20d5e3059 100644 --- a/riscv-ctg/riscv_ctg/data/inx.yaml +++ b/riscv-ctg/riscv_ctg/data/inx.yaml @@ -1527,4 +1527,725 @@ fcvt.s.lu: // $comment /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg; - fcsr_val: $fcsr*/ \ No newline at end of file + fcsr_val: $fcsr*/ + +fadd.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - I_Zfinx_Zhinx + flen: [16,32] + std_op: + formattype: 'rformat' + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; fcsr: $fcsr; + correctval:??; testreg:$testreg + */ + TEST_FPRR_OP($inst, $rd, $rs1, $rs2, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fclass.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - I_Zfinx_Zhinx + flen: [16,32,64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; correctval:??; testreg:$testreg; + fcsr_val:$fcsr*/ + TEST_FPID_OP_NRM($inst, $rd, $rs1, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fmax.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - I_Zfinx_Zhinx + flen: [16,32,64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr; + correctval:??; testreg:$testreg + */ + TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fmin.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - I_Zfinx_Zhinx + flen: [16,32,64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr; + correctval:??; testreg:$testreg + */ + TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +feq.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - I_Zfinx_Zhinx + flen: [16,32,64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; correctval:??; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FCMP_OP($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fle.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - I_Zfinx_Zhinx + flen: [16,32,64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; correctval:??; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FCMP_OP($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +flt.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - I_Zfinx_Zhinx + flen: [16,32,64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; correctval:??; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FCMP_OP($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fsgnj.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - I_Zfinx_Zhinx + flen: [16,32,64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr; + correctval:??; testreg:$testreg + */ + TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fsgnjn.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - I_Zfinx_Zhinx + flen: [16,32,64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr; + correctval:??; testreg:$testreg + */ + TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fsgnjx.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - I_Zfinx_Zhinx + flen: [16,32,64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr; + correctval:??; testreg:$testreg + */ + TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fsqrt.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - I_Zfinx_Zhinx + flen: [16,32] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; + fcsr_val: $fcsr */ + TEST_FPSR_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fdiv.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - I_Zfinx_Zhinx + flen: [16,32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; fcsr: $fcsr; + correctval:??; testreg:$testreg + */ + TEST_FPRR_OP($inst, $rd, $rs1, $rs2, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fmul.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - I_Zfinx_Zhinx + flen: [16,32] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; fcsr: $fcsr; + correctval:??; testreg:$testreg + */ + TEST_FPRR_OP($inst, $rd, $rs1, $rs2, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fsub.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - I_Zfinx_Zhinx + flen: [16,32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; fcsr: $fcsr; + correctval:??; testreg:$testreg*/ + TEST_FPRR_OP($inst, $rd, $rs1, $rs2, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fcvt.h.w: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: '4' + val_template: "'.word $val;'" + load_instr: "lw" + xlen: [32,64] + isa: + - I_Zfinx_Zhinx + flen: [16,32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FPIO_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + +fcvt.h.wu: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: '4' + val_template: "'.word $val;'" + load_instr: "LREGWU" + xlen: [32,64] + isa: + - I_Zfinx_Zhinx + flen: [16,32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FPIO_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + +fcvt.w.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - I_Zfinx_Zhinx + flen: [16,32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; + fcsr_val:$fcsr*/ + TEST_FPID_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + +fcvt.wu.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - I_Zfinx_Zhinx + flen: [16,32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; + fcsr_val:$fcsr*/ + TEST_FPID_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + +fcvt.s.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - I_Zfinx_Zhinx + flen: [16,32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; + fcsr_val: $fcsr */ + TEST_FPSR_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fcvt.h.l: + sig: + stride: 1 + sz: 'SIGALIGN' + val: + stride: 1 + sz: '8' + val_template: "'.dword $val;'" + load_instr: "ld" + xlen: [64] + isa: + - I_Zfinx_Zhinx + std_op: + flen: [16,32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + formattype: 'fsrformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FPIO_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + +fcvt.l.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [64] + std_op: + isa: + - I_Zfinx_Zhinx + flen: [16,32,64] + rm_val_data: '[0,1,2,3,4,7]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + formattype: 'fsrformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; + fcsr_val:$fcsr*/ + TEST_FPID_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + +fcvt.lu.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [64] + isa: + - I_Zfinx_Zhinx + flen: [16,32,64] + rm_val_data: '[0,1,2,3,4,7]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; + fcsr_val:$fcsr*/ + TEST_FPID_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + +fcvt.h.lu: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: '8' + val_template: "'.dword $val;'" + load_instr: "ld" + xlen: [32,64] + isa: + - I_Zfinx_Zhinx + flen: [16,32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FPIO_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + +fmadd.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 3 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - I_Zfinx_Zhinx + flen: [16,32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'r4format' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rs3_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; op3:$rs3; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + op3val:$rs3_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; + testreg:$testreg; fcsr_val:$fcsr */ + TEST_FPR4_OP($inst, $rd, $rs1, $rs2, $rs3, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fmsub.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 3 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - I_Zfinx_Zhinx + flen: [16,32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'r4format' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rs3_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; op3:$rs3; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + op3val:$rs3_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; + testreg:$testreg; fcsr_val:$fcsr */ + TEST_FPR4_OP($inst, $rd, $rs1, $rs2, $rs3, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fnmadd.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 3 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - I_Zfinx_Zhinx + flen: [16,32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'r4format' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rs3_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; op3:$rs3; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + op3val:$rs3_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; + testreg:$testreg; fcsr_val:$fcsr */ + TEST_FPR4_OP($inst, $rd, $rs1, $rs2, $rs3, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fnmsub.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 3 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - I_Zfinx_Zhinx + flen: [16,32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'r4format' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rs3_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; op3:$rs3; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + op3val:$rs3_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; + testreg:$testreg; fcsr_val:$fcsr */ + TEST_FPR4_OP($inst, $rd, $rs1, $rs2, $rs3, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) \ No newline at end of file diff --git a/riscv-ctg/riscv_ctg/data/template.yaml b/riscv-ctg/riscv_ctg/data/template.yaml index d1f87c8df..40d23c717 100644 --- a/riscv-ctg/riscv_ctg/data/template.yaml +++ b/riscv-ctg/riscv_ctg/data/template.yaml @@ -4,6 +4,7 @@ metadata: all_fregs: &all_fregs "['f'+str(x) for x in range(0,32 if 'e' not in base_isa else 16)]" all_regs_mx0: &all_regs_mx0 "['x'+str(x) for x in range(1,32 if 'e' not in base_isa else 16)]" c_regs: &c_regs "['x'+str(x) for x in range(8,16)]" + c_fregs: &c_fregs "['x'+str(x) for x in range(8,16)]" pair_regs: &pair_regs "['x'+str(x) for x in range(2,32 if 'e' not in base_isa else 16, 2 if xlen == 32 else 1)]" rv32rv64pair_regs: &rv32rv64pair_regs "['x'+str(x) for x in range(2,30 if 'e' not in base_isa else 16, 2)]" diff --git a/riscv-ctg/riscv_ctg/generator.py b/riscv-ctg/riscv_ctg/generator.py index 5e25cf17e..c150785e9 100644 --- a/riscv-ctg/riscv_ctg/generator.py +++ b/riscv-ctg/riscv_ctg/generator.py @@ -260,7 +260,8 @@ def __init__(self,fmt,opnode,opcode,randomization, xl, fl, ifl ,base_isa_str,inx is_nan_box = False - is_fext = any(['F' in x or 'D' in x or 'Zfh' in x or 'Zfinx' in x for x in opnode['isa']]) + + is_fext = any(['F' in x or 'D' in x or 'Zfh' in x or 'Zfinx' in x or 'Zcf' in x or 'Zcd' in x or 'Zhinx' in x for x in opnode['isa']]) is_sgn_extd = True if (inxFlag and iflen = 1: if self.rd[1] == 'x': arch_state.x_rf[int(commitvalue[1])] = str(commitvalue[2][2:]) elif self.rd[1] == 'f': @@ -689,7 +690,13 @@ def evaluate_reg_sem_f_ext(self, reg_val, flen, iflen, postfix, f_ext_vars, inxF if flen > iflen: - if inxFlag: + if inxFlag and iflen == 16: + if bin_val[16] == '1' : + sgnd_bin_val = bin(reg_val &((1<> 26 funct7 = (instr >> 25) rd = ((instr & self.RD_MASK) >> 7, 'x') + + if funct3 == 0b110: + if rd[0] == 0: + return self.prefetch_ops(instrObj) + rs1 = ((instr & self.RS1_MASK) >> 15, 'x') rs2 = ((instr & self.RS2_MASK) >> 20, 'x') rs3 = ((instr & self.RS3_MASK) >> 27, 'x') @@ -1305,6 +1311,14 @@ def arith_ops(self, instrObj): return instrObj + def mem_ops(self, instrObj): + instr = instrObj.instr + func3 = (instr & self.FUNCT3_MASK) >> 12 + if func3 == 0b000 or func3 == 0b001: + return self.fence_ops(instrObj) + elif func3 == 0b010 : + return self.cbo_ops(instrObj) + def fence_ops(self, instrObj): instr = instrObj.instr funct3 = (instr & self.FUNCT3_MASK) >> 12 @@ -1321,6 +1335,37 @@ def fence_ops(self, instrObj): return instrObj + def cbo_ops(self, instrObj): + instr = instrObj.instr + func = (instr) >> 20 + instrObj.rs1 = ((instr & self.RS1_MASK) >> 15, 'x') + instrObj.imm = 0 + if func == 0b1: + instrObj.instr_name = "cbo.clean" + elif func == 0b10: + instrObj.instr_name = "cbo.flush" + elif func == 0b0: + instrObj.instr_name = "cbo.inval" + elif func == 0b100: + instrObj.instr_name = "cbo.zero" + return instrObj + + def prefetch_ops(self, instrObj): + instr = instrObj.instr + func = (instr & self.RS2_MASK) >> 20 + instrObj.rs1 = ((instr & self.RS1_MASK) >> 15, 'x') + + imm_11_5 = (instr & 0xfe000000) >> 20 + instrObj.imm = self.twos_comp(imm_11_5, 12) + + if func == 0b0: + instrObj.instr_name = "prefetch.i" + elif func == 0b1: + instrObj.instr_name = "prefetch.r" + elif func == 0b11: + instrObj.instr_name = "prefetch.w" + return instrObj + def priviledged_ops(self, instrObj): instr = instrObj.instr funct3 = (instr & self.FUNCT3_MASK) >> 12 @@ -1562,6 +1607,12 @@ def rv64i_arith_ops(self, instrObj): 0b11100: 'amomaxu.d' } + zacas_instr_names = { + 0b010: 'zacas.w', + 0b011: 'zacas.d', + 0b100: 'zacas.q', + } + def rv64_rv32_atomic_ops(self, instrObj): instr = instrObj.instr @@ -1580,25 +1631,28 @@ def rv64_rv32_atomic_ops(self, instrObj): instrObj.rl = rl instrObj.aq = aq - #RV32A instructions - if funct3 == 0b010: - if funct5 == 0b00010: - instrObj.rs2 = None - instrObj.instr_name = self.rv32a_instr_names[funct5] - else: - instrObj.instr_name = self.rv32a_instr_names[funct5] + if funct5 == 0b00101: + instrObj.instr_name = self.zacas_instr_names[funct3] + else: + #RV32A instructions + if funct3 == 0b010: + if funct5 == 0b00010: + instrObj.rs2 = None + instrObj.instr_name = self.rv32a_instr_names[funct5] + else: + instrObj.instr_name = self.rv32a_instr_names[funct5] - return instrObj + return instrObj - #RV64A instructions - if funct3 == 0b011: - if funct5 == 0b00010: - instrObj.rs2 = None - instrObj.instr_name = self.rv64a_instr_names[funct5] - else: - instrObj.instr_name = self.rv64a_instr_names[funct5] + #RV64A instructions + if funct3 == 0b011: + if funct5 == 0b00010: + instrObj.rs2 = None + instrObj.instr_name = self.rv64a_instr_names[funct5] + else: + instrObj.instr_name = self.rv64a_instr_names[funct5] - return instrObj + return instrObj def flw_fld(self, instrObj): instr = instrObj.instr diff --git a/riscv-test-suite/env/arch_test.h b/riscv-test-suite/env/arch_test.h index 80a150505..18ef0e801 100644 --- a/riscv-test-suite/env/arch_test.h +++ b/riscv-test-suite/env/arch_test.h @@ -292,8 +292,14 @@ #define FSREG SREG #define FREGWIDTH 8 #define FLEN 64 +#elif ZHINX==1 + #define FLREG lw + #define FSREG sw + #define FREGWIDTH 4 + #define FLEN 32 #endif + #if SIGALIGN==8 #define CANARY \ .dword 0x6F5CA309E7D4B281 diff --git a/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b1-01.S b/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b1-01.S index cab307857..1e1fee401 100644 --- a/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b1-01.S +++ b/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b1-01.S @@ -279,39 +279,39 @@ rvtest_data: .word 0xbecafeba .word 0xecafebab test_dataset_0: -NAN_BOXED(0,64,FLEN) -NAN_BOXED(1,64,FLEN) -NAN_BOXED(2,64,FLEN) -NAN_BOXED(8388607,64,FLEN) -NAN_BOXED(4503599627370496,64,FLEN) -NAN_BOXED(4503599627370497,64,FLEN) -NAN_BOXED(571957152676052992,64,FLEN) -NAN_BOXED(1143914305360494591,64,FLEN) -NAN_BOXED(1148417904979476480,64,FLEN) -NAN_BOXED(1148417904979476481,64,FLEN) -NAN_BOXED(1148417904983670784,64,FLEN) -NAN_BOXED(1148417904983670785,64,FLEN) -NAN_BOXED(9223372036854775808,64,FLEN) -NAN_BOXED(9223372036854775809,64,FLEN) -NAN_BOXED(9223372036863164414,64,FLEN) -NAN_BOXED(9223372036863164415,64,FLEN) -NAN_BOXED(9227875636482146304,64,FLEN) -NAN_BOXED(9227875636482495829,64,FLEN) -NAN_BOXED(9795329189530828800,64,FLEN) -NAN_BOXED(10367286342215270399,64,FLEN) -NAN_BOXED(10371789941834252288,64,FLEN) -NAN_BOXED(10371789941837048490,64,FLEN) -NAN_BOXED(10371789941838446592,64,FLEN) -NAN_BOXED(10371789941838796117,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(2147483648,32,FLEN) +NAN_BOXED(1,32,FLEN) +NAN_BOXED(2147483649,32,FLEN) +NAN_BOXED(2,32,FLEN) +NAN_BOXED(2155872254,32,FLEN) +NAN_BOXED(8388607,32,FLEN) +NAN_BOXED(2155872255,32,FLEN) +NAN_BOXED(8388608,32,FLEN) +NAN_BOXED(2155872256,32,FLEN) +NAN_BOXED(8388609,32,FLEN) +NAN_BOXED(2156221781,32,FLEN) +NAN_BOXED(2139095039,32,FLEN) +NAN_BOXED(4286578687,32,FLEN) +NAN_BOXED(2139095040,32,FLEN) +NAN_BOXED(4286578688,32,FLEN) +NAN_BOXED(2143289344,32,FLEN) +NAN_BOXED(4290772992,32,FLEN) +NAN_BOXED(2143289345,32,FLEN) +NAN_BOXED(4291122517,32,FLEN) +NAN_BOXED(2139095041,32,FLEN) +NAN_BOXED(4289374890,32,FLEN) +NAN_BOXED(1065353216,32,FLEN) +NAN_BOXED(3212836864,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) RVTEST_DATA_END RVMODEL_DATA_BEGIN diff --git a/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b22-01.S b/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b22-01.S index c1ae197ee..df5f88761 100644 --- a/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b22-01.S +++ b/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b22-01.S @@ -279,39 +279,39 @@ rvtest_data: .word 0xbecafeba .word 0xecafebab test_dataset_0: -NAN_BOXED(463870761624642812,64,FLEN) -NAN_BOXED(558446353798734776,64,FLEN) -NAN_BOXED(562949953424909782,64,FLEN) -NAN_BOXED(567453553053531877,64,FLEN) -NAN_BOXED(571957152677781869,64,FLEN) -NAN_BOXED(576460752310246121,64,FLEN) -NAN_BOXED(580964351937702748,64,FLEN) -NAN_BOXED(882705526964905814,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(463870761624642812,64,FLEN) +NAN_BOXED(1044980664,32,FLEN) +NAN_BOXED(1052173782,32,FLEN) +NAN_BOXED(1061813989,32,FLEN) +NAN_BOXED(1067082093,32,FLEN) +NAN_BOXED(1080564457,32,FLEN) +NAN_BOXED(1089039196,32,FLEN) +NAN_BOXED(869508348,32,FLEN) +NAN_BOXED(1644455766,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) RVTEST_DATA_END RVMODEL_DATA_BEGIN diff --git a/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b23-01.S b/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b23-01.S index 0cb29ad08..c4c413462 100644 --- a/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b23-01.S +++ b/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b23-01.S @@ -279,39 +279,51 @@ rvtest_data: .word 0xbecafeba .word 0xecafebab test_dataset_0: -NAN_BOXED(707065141505556476,64,FLEN) -NAN_BOXED(707065141505556477,64,FLEN) -NAN_BOXED(707065141505556478,64,FLEN) -NAN_BOXED(707065141505556479,64,FLEN) -NAN_BOXED(711568741124538368,64,FLEN) -NAN_BOXED(711568741124538369,64,FLEN) -NAN_BOXED(711568741124538370,64,FLEN) -NAN_BOXED(711568741124538371,64,FLEN) -NAN_BOXED(711568741124538372,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(707065141505556476,64,FLEN) +NAN_BOXED(1325400060,32,FLEN) +NAN_BOXED(1325400060,32,FLEN) +NAN_BOXED(1325400060,32,FLEN) +NAN_BOXED(1325400060,32,FLEN) +NAN_BOXED(1325400060,32,FLEN) +NAN_BOXED(1325400061,32,FLEN) +NAN_BOXED(1325400061,32,FLEN) +NAN_BOXED(1325400061,32,FLEN) +NAN_BOXED(1325400061,32,FLEN) +NAN_BOXED(1325400061,32,FLEN) +NAN_BOXED(1325400062,32,FLEN) +NAN_BOXED(1325400062,32,FLEN) +NAN_BOXED(1325400062,32,FLEN) +NAN_BOXED(1325400062,32,FLEN) +NAN_BOXED(1325400062,32,FLEN) +NAN_BOXED(1325400063,32,FLEN) +NAN_BOXED(1325400063,32,FLEN) +NAN_BOXED(1325400063,32,FLEN) +NAN_BOXED(1325400063,32,FLEN) +NAN_BOXED(1325400063,32,FLEN) +NAN_BOXED(1325400064,32,FLEN) +NAN_BOXED(1325400064,32,FLEN) +NAN_BOXED(1325400064,32,FLEN) +NAN_BOXED(1325400064,32,FLEN) +NAN_BOXED(1325400064,32,FLEN) +NAN_BOXED(1325400065,32,FLEN) +NAN_BOXED(1325400065,32,FLEN) +NAN_BOXED(1325400065,32,FLEN) +NAN_BOXED(1325400065,32,FLEN) +NAN_BOXED(1325400065,32,FLEN) +NAN_BOXED(1325400066,32,FLEN) +NAN_BOXED(1325400066,32,FLEN) +NAN_BOXED(1325400066,32,FLEN) +NAN_BOXED(1325400066,32,FLEN) +NAN_BOXED(1325400066,32,FLEN) +NAN_BOXED(1325400067,32,FLEN) +NAN_BOXED(1325400067,32,FLEN) +NAN_BOXED(1325400067,32,FLEN) +NAN_BOXED(1325400067,32,FLEN) +NAN_BOXED(1325400067,32,FLEN) +NAN_BOXED(1325400068,32,FLEN) +NAN_BOXED(1325400068,32,FLEN) +NAN_BOXED(1325400068,32,FLEN) +NAN_BOXED(1325400068,32,FLEN) +NAN_BOXED(1325400068,32,FLEN) RVTEST_DATA_END RVMODEL_DATA_BEGIN diff --git a/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b24-01.S b/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b24-01.S index b7cea7321..69116e5b6 100644 --- a/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b24-01.S +++ b/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b24-01.S @@ -279,39 +279,111 @@ rvtest_data: .word 0xbecafeba .word 0xecafebab test_dataset_0: -NAN_BOXED(2032,64,FLEN) -NAN_BOXED(540431955286808330,64,FLEN) -NAN_BOXED(553942754171604172,64,FLEN) -NAN_BOXED(553942754172946350,64,FLEN) -NAN_BOXED(567453553055225610,64,FLEN) -NAN_BOXED(567453553055393382,64,FLEN) -NAN_BOXED(567453553056903331,64,FLEN) -NAN_BOXED(571957152676052992,64,FLEN) -NAN_BOXED(571957152676136878,64,FLEN) -NAN_BOXED(571957152676891852,64,FLEN) -NAN_BOXED(571957152676975738,64,FLEN) -NAN_BOXED(9763803992141584138,64,FLEN) -NAN_BOXED(9777314791026379980,64,FLEN) -NAN_BOXED(9777314791027722158,64,FLEN) -NAN_BOXED(9790825589910001418,64,FLEN) -NAN_BOXED(9790825589910169190,64,FLEN) -NAN_BOXED(9790825589911679139,64,FLEN) -NAN_BOXED(9795329189530828800,64,FLEN) -NAN_BOXED(9795329189530912686,64,FLEN) -NAN_BOXED(9795329189531667660,64,FLEN) -NAN_BOXED(9795329189531751546,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(2032,64,FLEN) +NAN_BOXED(2032,32,FLEN) +NAN_BOXED(2032,32,FLEN) +NAN_BOXED(2032,32,FLEN) +NAN_BOXED(2032,32,FLEN) +NAN_BOXED(2032,32,FLEN) +NAN_BOXED(3212669091,32,FLEN) +NAN_BOXED(3212669091,32,FLEN) +NAN_BOXED(3212669091,32,FLEN) +NAN_BOXED(3212669091,32,FLEN) +NAN_BOXED(3212669091,32,FLEN) +NAN_BOXED(1036831948,32,FLEN) +NAN_BOXED(1036831948,32,FLEN) +NAN_BOXED(1036831948,32,FLEN) +NAN_BOXED(1036831948,32,FLEN) +NAN_BOXED(1036831948,32,FLEN) +NAN_BOXED(3213675724,32,FLEN) +NAN_BOXED(3213675724,32,FLEN) +NAN_BOXED(3213675724,32,FLEN) +NAN_BOXED(3213675724,32,FLEN) +NAN_BOXED(3213675724,32,FLEN) +NAN_BOXED(1038174126,32,FLEN) +NAN_BOXED(1038174126,32,FLEN) +NAN_BOXED(1038174126,32,FLEN) +NAN_BOXED(1038174126,32,FLEN) +NAN_BOXED(1038174126,32,FLEN) +NAN_BOXED(1066275962,32,FLEN) +NAN_BOXED(1066275962,32,FLEN) +NAN_BOXED(1066275962,32,FLEN) +NAN_BOXED(1066275962,32,FLEN) +NAN_BOXED(1066275962,32,FLEN) +NAN_BOXED(3212920750,32,FLEN) +NAN_BOXED(3212920750,32,FLEN) +NAN_BOXED(3212920750,32,FLEN) +NAN_BOXED(3212920750,32,FLEN) +NAN_BOXED(3212920750,32,FLEN) +NAN_BOXED(3210991370,32,FLEN) +NAN_BOXED(3210991370,32,FLEN) +NAN_BOXED(3210991370,32,FLEN) +NAN_BOXED(3210991370,32,FLEN) +NAN_BOXED(3210991370,32,FLEN) +NAN_BOXED(3184315596,32,FLEN) +NAN_BOXED(3184315596,32,FLEN) +NAN_BOXED(3184315596,32,FLEN) +NAN_BOXED(3184315596,32,FLEN) +NAN_BOXED(3184315596,32,FLEN) +NAN_BOXED(1065353216,32,FLEN) +NAN_BOXED(1065353216,32,FLEN) +NAN_BOXED(1065353216,32,FLEN) +NAN_BOXED(1065353216,32,FLEN) +NAN_BOXED(1065353216,32,FLEN) +NAN_BOXED(3212836864,32,FLEN) +NAN_BOXED(3212836864,32,FLEN) +NAN_BOXED(3212836864,32,FLEN) +NAN_BOXED(3212836864,32,FLEN) +NAN_BOXED(3212836864,32,FLEN) +NAN_BOXED(1066192076,32,FLEN) +NAN_BOXED(1066192076,32,FLEN) +NAN_BOXED(1066192076,32,FLEN) +NAN_BOXED(1066192076,32,FLEN) +NAN_BOXED(1066192076,32,FLEN) +NAN_BOXED(1063675494,32,FLEN) +NAN_BOXED(1063675494,32,FLEN) +NAN_BOXED(1063675494,32,FLEN) +NAN_BOXED(1063675494,32,FLEN) +NAN_BOXED(1063675494,32,FLEN) +NAN_BOXED(3156465418,32,FLEN) +NAN_BOXED(3156465418,32,FLEN) +NAN_BOXED(3156465418,32,FLEN) +NAN_BOXED(3156465418,32,FLEN) +NAN_BOXED(3156465418,32,FLEN) +NAN_BOXED(1065437102,32,FLEN) +NAN_BOXED(1065437102,32,FLEN) +NAN_BOXED(1065437102,32,FLEN) +NAN_BOXED(1065437102,32,FLEN) +NAN_BOXED(1065437102,32,FLEN) +NAN_BOXED(1063507722,32,FLEN) +NAN_BOXED(1063507722,32,FLEN) +NAN_BOXED(1063507722,32,FLEN) +NAN_BOXED(1063507722,32,FLEN) +NAN_BOXED(1063507722,32,FLEN) +NAN_BOXED(3185657774,32,FLEN) +NAN_BOXED(3185657774,32,FLEN) +NAN_BOXED(3185657774,32,FLEN) +NAN_BOXED(3185657774,32,FLEN) +NAN_BOXED(3185657774,32,FLEN) +NAN_BOXED(1008981770,32,FLEN) +NAN_BOXED(1008981770,32,FLEN) +NAN_BOXED(1008981770,32,FLEN) +NAN_BOXED(1008981770,32,FLEN) +NAN_BOXED(1008981770,32,FLEN) +NAN_BOXED(3211159142,32,FLEN) +NAN_BOXED(3211159142,32,FLEN) +NAN_BOXED(3211159142,32,FLEN) +NAN_BOXED(3211159142,32,FLEN) +NAN_BOXED(3211159142,32,FLEN) +NAN_BOXED(3213759610,32,FLEN) +NAN_BOXED(3213759610,32,FLEN) +NAN_BOXED(3213759610,32,FLEN) +NAN_BOXED(3213759610,32,FLEN) +NAN_BOXED(3213759610,32,FLEN) +NAN_BOXED(1065185443,32,FLEN) +NAN_BOXED(1065185443,32,FLEN) +NAN_BOXED(1065185443,32,FLEN) +NAN_BOXED(1065185443,32,FLEN) +NAN_BOXED(1065185443,32,FLEN) RVTEST_DATA_END RVMODEL_DATA_BEGIN diff --git a/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b27-01.S b/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b27-01.S index d7fee7fdb..1b866af06 100644 --- a/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b27-01.S +++ b/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b27-01.S @@ -279,39 +279,39 @@ rvtest_data: .word 0xbecafeba .word 0xecafebab test_dataset_0: -NAN_BOXED(1148417904979476481,64,FLEN) -NAN_BOXED(1148417904982272682,64,FLEN) -NAN_BOXED(1148417904983670785,64,FLEN) -NAN_BOXED(1148417904984020309,64,FLEN) -NAN_BOXED(10371789941834252289,64,FLEN) -NAN_BOXED(10371789941837048490,64,FLEN) -NAN_BOXED(10371789941838446593,64,FLEN) -NAN_BOXED(10371789941838796117,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(1148417904979476481,64,FLEN) +NAN_BOXED(2139095041,32,FLEN) +NAN_BOXED(4286578689,32,FLEN) +NAN_BOXED(2141891242,32,FLEN) +NAN_BOXED(4289374890,32,FLEN) +NAN_BOXED(2143289345,32,FLEN) +NAN_BOXED(4290772993,32,FLEN) +NAN_BOXED(2143638869,32,FLEN) +NAN_BOXED(4291122517,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) RVTEST_DATA_END RVMODEL_DATA_BEGIN diff --git a/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b28-01.S b/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b28-01.S index 43840720f..852662595 100644 --- a/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b28-01.S +++ b/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b28-01.S @@ -279,39 +279,39 @@ rvtest_data: .word 0xbecafeba .word 0xecafebab test_dataset_0: -NAN_BOXED(0,64,FLEN) -NAN_BOXED(567453553049880432,64,FLEN) -NAN_BOXED(571957152676052992,64,FLEN) -NAN_BOXED(571957152678150144,64,FLEN) -NAN_BOXED(571957152680247296,64,FLEN) -NAN_BOXED(571957152682344448,64,FLEN) -NAN_BOXED(576460752303423488,64,FLEN) -NAN_BOXED(576460752304472064,64,FLEN) -NAN_BOXED(576460752305520640,64,FLEN) -NAN_BOXED(576460752306569216,64,FLEN) -NAN_BOXED(702561541875799896,64,FLEN) -NAN_BOXED(707065141505556479,64,FLEN) -NAN_BOXED(1148417904979476480,64,FLEN) -NAN_BOXED(1148417904979476481,64,FLEN) -NAN_BOXED(1148417904983670785,64,FLEN) -NAN_BOXED(9223372036854775808,64,FLEN) -NAN_BOXED(9786321990281856106,64,FLEN) -NAN_BOXED(9795329189530828800,64,FLEN) -NAN_BOXED(9795329189532925952,64,FLEN) -NAN_BOXED(9795329189535023104,64,FLEN) -NAN_BOXED(9795329189537120256,64,FLEN) -NAN_BOXED(9799832789158199296,64,FLEN) -NAN_BOXED(9799832789159247872,64,FLEN) -NAN_BOXED(9799832789160296448,64,FLEN) -NAN_BOXED(9799832789161345024,64,FLEN) -NAN_BOXED(9930437178356874533,64,FLEN) -NAN_BOXED(9934940777979314176,64,FLEN) -NAN_BOXED(10371789941834252288,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(1058162544,32,FLEN) +NAN_BOXED(1065353216,32,FLEN) +NAN_BOXED(1067450368,32,FLEN) +NAN_BOXED(1069547520,32,FLEN) +NAN_BOXED(1071644672,32,FLEN) +NAN_BOXED(1073741824,32,FLEN) +NAN_BOXED(1074790400,32,FLEN) +NAN_BOXED(1075838976,32,FLEN) +NAN_BOXED(1076887552,32,FLEN) +NAN_BOXED(1314625368,32,FLEN) +NAN_BOXED(1325400063,32,FLEN) +NAN_BOXED(2139095040,32,FLEN) +NAN_BOXED(2139095041,32,FLEN) +NAN_BOXED(2143289345,32,FLEN) +NAN_BOXED(2147483648,32,FLEN) +NAN_BOXED(3201827946,32,FLEN) +NAN_BOXED(3212836864,32,FLEN) +NAN_BOXED(3224371200,32,FLEN) +NAN_BOXED(3223322624,32,FLEN) +NAN_BOXED(3222274048,32,FLEN) +NAN_BOXED(3221225472,32,FLEN) +NAN_BOXED(3219128320,32,FLEN) +NAN_BOXED(3217031168,32,FLEN) +NAN_BOXED(3214934016,32,FLEN) +NAN_BOXED(3469425957,32,FLEN) +NAN_BOXED(3472883712,32,FLEN) +NAN_BOXED(4286578688,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) RVTEST_DATA_END RVMODEL_DATA_BEGIN diff --git a/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b29-01.S b/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b29-01.S index 0033b9c5c..dbb13ac32 100644 --- a/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b29-01.S +++ b/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b29-01.S @@ -279,39 +279,86 @@ rvtest_data: .word 0xbecafeba .word 0xecafebab test_dataset_0: -NAN_BOXED(558446353798734776,64,FLEN) -NAN_BOXED(558446353798734777,64,FLEN) -NAN_BOXED(558446353798734778,64,FLEN) -NAN_BOXED(558446353798734779,64,FLEN) -NAN_BOXED(558446353798734780,64,FLEN) -NAN_BOXED(558446353798734781,64,FLEN) -NAN_BOXED(558446353798734782,64,FLEN) -NAN_BOXED(558446353798734783,64,FLEN) -NAN_BOXED(9781818390653510584,64,FLEN) -NAN_BOXED(9781818390653510585,64,FLEN) -NAN_BOXED(9781818390653510586,64,FLEN) -NAN_BOXED(9781818390653510587,64,FLEN) -NAN_BOXED(9781818390653510588,64,FLEN) -NAN_BOXED(9781818390653510589,64,FLEN) -NAN_BOXED(9781818390653510590,64,FLEN) -NAN_BOXED(9781818390653510591,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(558446353798734776,64,FLEN) +NAN_BOXED(1044980664,32,FLEN) +NAN_BOXED(1044980664,32,FLEN) +NAN_BOXED(1044980664,32,FLEN) +NAN_BOXED(1044980664,32,FLEN) +NAN_BOXED(1044980664,32,FLEN) +NAN_BOXED(1044980665,32,FLEN) +NAN_BOXED(1044980665,32,FLEN) +NAN_BOXED(1044980665,32,FLEN) +NAN_BOXED(1044980665,32,FLEN) +NAN_BOXED(1044980665,32,FLEN) +NAN_BOXED(1044980666,32,FLEN) +NAN_BOXED(1044980666,32,FLEN) +NAN_BOXED(1044980666,32,FLEN) +NAN_BOXED(1044980666,32,FLEN) +NAN_BOXED(1044980666,32,FLEN) +NAN_BOXED(1044980667,32,FLEN) +NAN_BOXED(1044980667,32,FLEN) +NAN_BOXED(1044980667,32,FLEN) +NAN_BOXED(1044980667,32,FLEN) +NAN_BOXED(1044980667,32,FLEN) +NAN_BOXED(1044980668,32,FLEN) +NAN_BOXED(1044980668,32,FLEN) +NAN_BOXED(1044980668,32,FLEN) +NAN_BOXED(1044980668,32,FLEN) +NAN_BOXED(1044980668,32,FLEN) +NAN_BOXED(1044980669,32,FLEN) +NAN_BOXED(1044980669,32,FLEN) +NAN_BOXED(1044980669,32,FLEN) +NAN_BOXED(1044980669,32,FLEN) +NAN_BOXED(1044980669,32,FLEN) +NAN_BOXED(1044980670,32,FLEN) +NAN_BOXED(1044980670,32,FLEN) +NAN_BOXED(1044980670,32,FLEN) +NAN_BOXED(1044980670,32,FLEN) +NAN_BOXED(1044980670,32,FLEN) +NAN_BOXED(1044980671,32,FLEN) +NAN_BOXED(1044980671,32,FLEN) +NAN_BOXED(1044980671,32,FLEN) +NAN_BOXED(1044980671,32,FLEN) +NAN_BOXED(1044980671,32,FLEN) +NAN_BOXED(3192464312,32,FLEN) +NAN_BOXED(3192464312,32,FLEN) +NAN_BOXED(3192464312,32,FLEN) +NAN_BOXED(3192464312,32,FLEN) +NAN_BOXED(3192464312,32,FLEN) +NAN_BOXED(3192464313,32,FLEN) +NAN_BOXED(3192464313,32,FLEN) +NAN_BOXED(3192464313,32,FLEN) +NAN_BOXED(3192464313,32,FLEN) +NAN_BOXED(3192464313,32,FLEN) +NAN_BOXED(3192464314,32,FLEN) +NAN_BOXED(3192464314,32,FLEN) +NAN_BOXED(3192464314,32,FLEN) +NAN_BOXED(3192464314,32,FLEN) +NAN_BOXED(3192464314,32,FLEN) +NAN_BOXED(3192464315,32,FLEN) +NAN_BOXED(3192464315,32,FLEN) +NAN_BOXED(3192464315,32,FLEN) +NAN_BOXED(3192464315,32,FLEN) +NAN_BOXED(3192464315,32,FLEN) +NAN_BOXED(3192464316,32,FLEN) +NAN_BOXED(3192464316,32,FLEN) +NAN_BOXED(3192464316,32,FLEN) +NAN_BOXED(3192464316,32,FLEN) +NAN_BOXED(3192464316,32,FLEN) +NAN_BOXED(3192464317,32,FLEN) +NAN_BOXED(3192464317,32,FLEN) +NAN_BOXED(3192464317,32,FLEN) +NAN_BOXED(3192464317,32,FLEN) +NAN_BOXED(3192464317,32,FLEN) +NAN_BOXED(3192464318,32,FLEN) +NAN_BOXED(3192464318,32,FLEN) +NAN_BOXED(3192464318,32,FLEN) +NAN_BOXED(3192464318,32,FLEN) +NAN_BOXED(3192464318,32,FLEN) +NAN_BOXED(3192464319,32,FLEN) +NAN_BOXED(3192464319,32,FLEN) +NAN_BOXED(3192464319,32,FLEN) +NAN_BOXED(3192464319,32,FLEN) +NAN_BOXED(3192464319,32,FLEN) RVTEST_DATA_END RVMODEL_DATA_BEGIN diff --git a/riscv-test-suite/rv32i_m/D_Zcd/src/c.fld-01.S b/riscv-test-suite/rv32i_m/D_Zcd/src/c.fld-01.S new file mode 100644 index 000000000..f5b609c00 --- /dev/null +++ b/riscv-test-suite/rv32i_m/D_Zcd/src/c.fld-01.S @@ -0,0 +1,173 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.0 +// timestamp : Fri Aug 4 07:31:35 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/riscv-ctg/sample_cgfs/RV32C/fld.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.fld instruction of the RISC-V RV32FDC_Zcd,RV64FDC_Zcd extension for the c.fld covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IFDC") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*C.*);def TEST_CASE_1=True;",c.fld) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 != rd, rs1==x15, rd==f15,imm_val == 0 and fcsr == 0, +// opcode:c.fld; op1:x15; dest:f15; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,0,x15,f15,0x0,c.fld,0,x4) + +inst_1: +// rs1==x14, rd==f14,imm_val > 0 and fcsr == 0, +// opcode:c.fld; op1:x14; dest:f14; immval:0xf8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,0,x14,f14,0xf8,c.fld,0,x4) + +inst_2: +// rs1==x13, rd==f13,imm_val == 168, +// opcode:c.fld; op1:x13; dest:f13; immval:0xa8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x13,f13,0xa8,c.fld,0,x4) + +inst_3: +// rs1==x12, rd==f12,imm_val == 80, +// opcode:c.fld; op1:x12; dest:f12; immval:0x50; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x12,f12,0x50,c.fld,0,x4) + +inst_4: +// rs1==x11, rd==f11,imm_val == 8, +// opcode:c.fld; op1:x11; dest:f11; immval:0x8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x11,f11,0x8,c.fld,0,x4) + +inst_5: +// rs1==x10, rd==f10,imm_val == 16, +// opcode:c.fld; op1:x10; dest:f10; immval:0x10; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x10,f10,0x10,c.fld,0,x4) + +inst_6: +// rs1==x9, rd==f9,imm_val == 240, +// opcode:c.fld; op1:x9; dest:f9; immval:0xf0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x9,f9,0xf0,c.fld,0,x4) + +inst_7: +// rs1==x8, rd==f8,imm_val == 232, +// opcode:c.fld; op1:x8; dest:f8; immval:0xe8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x8,f8,0xe8,c.fld,0,x4) + +inst_8: +// imm_val == 216, +// opcode:c.fld; op1:x15; dest:f15; immval:0xd8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x15,f15,0xd8,c.fld,0,x4) + +inst_9: +// imm_val == 184, +// opcode:c.fld; op1:x15; dest:f15; immval:0xb8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x15,f15,0xb8,c.fld,0,x4) + +inst_10: +// imm_val == 120, +// opcode:c.fld; op1:x15; dest:f15; immval:0x78; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x15,f15,0x78,c.fld,0,x4) + +inst_11: +// imm_val == 32, +// opcode:c.fld; op1:x15; dest:f15; immval:0x20; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x15,f15,0x20,c.fld,0,x4) + +inst_12: +// imm_val == 64, +// opcode:c.fld; op1:x15; dest:f15; immval:0x40; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x15,f15,0x40,c.fld,0,x4) + +inst_13: +// imm_val == 128, +// opcode:c.fld; op1:x15; dest:f15; immval:0x80; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x15,f15,0x80,c.fld,0,x4) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: + + + + + + + + + + + + + + +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/D_Zcd/src/c.fldsp-01.S b/riscv-test-suite/rv32i_m/D_Zcd/src/c.fldsp-01.S new file mode 100644 index 000000000..579e37234 --- /dev/null +++ b/riscv-test-suite/rv32i_m/D_Zcd/src/c.fldsp-01.S @@ -0,0 +1,247 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.0 +// timestamp : Wed Aug 16 04:57:10 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/riscv-ctg/sample_cgfs/RV32C/fldsp.cgf \ + \ +// -- xlen 64 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.fldsp instruction of the RISC-V RV64FDC extension for the c.fldsp covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64IFDC") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*C.*);def TEST_CASE_1=True;",c.fldsp) + +RVTEST_FP_ENABLE() +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rd==f31, imm_val == 0, +// opcode:c.fldsp; op1:x2; dest:f31; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f31,0x0,c.fldsp,0,x4) + +inst_1: +// rd==f30, imm_val > 0, +// opcode:c.fldsp; op1:x2; dest:f30; immval:0x1f8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f30,0x1f8,c.fldsp,0,x4) + +inst_2: +// rd==f29, imm_val == 168, +// opcode:c.fldsp; op1:x2; dest:f29; immval:0xa8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f29,0xa8,c.fldsp,0,x4) + +inst_3: +// rd==f28, imm_val == 336, +// opcode:c.fldsp; op1:x2; dest:f28; immval:0x150; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f28,0x150,c.fldsp,0,x4) + +inst_4: +// rd==f27, imm_val == 496, +// opcode:c.fldsp; op1:x2; dest:f27; immval:0x1f0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f27,0x1f0,c.fldsp,0,x4) + +inst_5: +// rd==f26, imm_val == 488, +// opcode:c.fldsp; op1:x2; dest:f26; immval:0x1e8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f26,0x1e8,c.fldsp,0,x4) + +inst_6: +// rd==f25, imm_val == 472, +// opcode:c.fldsp; op1:x2; dest:f25; immval:0x1d8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f25,0x1d8,c.fldsp,0,x4) + +inst_7: +// rd==f24, imm_val == 440, +// opcode:c.fldsp; op1:x2; dest:f24; immval:0x1b8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f24,0x1b8,c.fldsp,0,x4) + +inst_8: +// rd==f23, imm_val == 376, +// opcode:c.fldsp; op1:x2; dest:f23; immval:0x178; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f23,0x178,c.fldsp,0,x4) + +inst_9: +// rd==f22, imm_val == 248, +// opcode:c.fldsp; op1:x2; dest:f22; immval:0xf8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f22,0xf8,c.fldsp,0,x4) + +inst_10: +// rd==f21, imm_val == 8, +// opcode:c.fldsp; op1:x2; dest:f21; immval:0x8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f21,0x8,c.fldsp,0,x4) + +inst_11: +// rd==f20, imm_val == 16, +// opcode:c.fldsp; op1:x2; dest:f20; immval:0x10; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f20,0x10,c.fldsp,0,x4) + +inst_12: +// rd==f19, imm_val == 32, +// opcode:c.fldsp; op1:x2; dest:f19; immval:0x20; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f19,0x20,c.fldsp,0,x4) + +inst_13: +// rd==f18, imm_val == 64, +// opcode:c.fldsp; op1:x2; dest:f18; immval:0x40; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f18,0x40,c.fldsp,0,x4) + +inst_14: +// rd==f17, imm_val == 128, +// opcode:c.fldsp; op1:x2; dest:f17; immval:0x80; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f17,0x80,c.fldsp,0,x4) + +inst_15: +// rd==f16, imm_val == 256, +// opcode:c.fldsp; op1:x2; dest:f16; immval:0x100; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f16,0x100,c.fldsp,0,x4) + +inst_16: +// rd==f15, +// opcode:c.fldsp; op1:x2; dest:f15; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f15,0x0,c.fldsp,0,x4) + +inst_17: +// rd==f14, +// opcode:c.fldsp; op1:x2; dest:f14; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f14,0x0,c.fldsp,0,x4) + +inst_18: +// rd==f13, +// opcode:c.fldsp; op1:x2; dest:f13; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f13,0x0,c.fldsp,0,x4) + +inst_19: +// rd==f12, +// opcode:c.fldsp; op1:x2; dest:f12; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f12,0x0,c.fldsp,0,x4) + +inst_20: +// rd==f11, +// opcode:c.fldsp; op1:x2; dest:f11; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f11,0x0,c.fldsp,0,x4) + +inst_21: +// rd==f10, +// opcode:c.fldsp; op1:x2; dest:f10; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f10,0x0,c.fldsp,0,x4) + +inst_22: +// rd==f9, +// opcode:c.fldsp; op1:x2; dest:f9; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f9,0x0,c.fldsp,0,x4) + +inst_23: +// rd==f8, +// opcode:c.fldsp; op1:x2; dest:f8; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f8,0x0,c.fldsp,0,x4) + +inst_24: +// rd==f7, +// opcode:c.fldsp; op1:x2; dest:f7; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f7,0x0,c.fldsp,0,x4) + +inst_25: +// rd==f6, +// opcode:c.fldsp; op1:x2; dest:f6; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f6,0x0,c.fldsp,0,x4) + +inst_26: +// rd==f5, +// opcode:c.fldsp; op1:x2; dest:f5; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f5,0x0,c.fldsp,0,x4) + +inst_27: +// rd==f4, +// opcode:c.fldsp; op1:x2; dest:f4; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f4,0x0,c.fldsp,0,x4) + +inst_28: +// rd==f3, +// opcode:c.fldsp; op1:x2; dest:f3; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f3,0x0,c.fldsp,0,x4) + +inst_29: +// rd==f2, +// opcode:c.fldsp; op1:x2; dest:f2; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f2,0x0,c.fldsp,0,x4) + +inst_30: +// rd==f1, +// opcode:c.fldsp; op1:x2; dest:f1; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f1,0x0,c.fldsp,0,x4) + +inst_31: +// rd==f0, +// opcode:c.fldsp; op1:x2; dest:f0; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f0,0x0,c.fldsp,0,x4) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 64*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/D_Zcd/src/c.fsd-01.S b/riscv-test-suite/rv32i_m/D_Zcd/src/c.fsd-01.S new file mode 100644 index 000000000..967a60248 --- /dev/null +++ b/riscv-test-suite/rv32i_m/D_Zcd/src/c.fsd-01.S @@ -0,0 +1,213 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.0 +// timestamp : Fri Aug 4 07:31:35 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/riscv-ctg/sample_cgfs/RV32C/fld.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.fsd instruction of the RISC-V RV32FDC_Zcd,RV64FDC_Zcd extension for the c.fsd covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IFDC") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*C.*);def TEST_CASE_1=True;",c.fsd) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0:// rs1 != rs2, rs1==x15, rs2==f15,imm_val == 0, +// opcode: c.fsd; op1:x15; op2:f15; op2val:-0x1000001; immval:0x0; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 0*FLEN/8; +TEST_STORE_F(x1,x2,0,x15,f15,0x0,0*SIGALIGN,c.fsd,0,x4,x3, 0*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_1) + +inst_1:// rs1==x14, rs2==f14,imm_val > 0, +// opcode: c.fsd; op1:x14; op2:f14; op2val:-0x1000001; immval:0xf8; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 1*FLEN/8; +TEST_STORE_F(x1,x2,0,x14,f14,0xf8,2*SIGALIGN,c.fsd,0,x4,x3, 1*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_2) + +inst_2:// rs1==x13, rs2==f13,imm_val == 168, +// opcode: c.fsd; op1:x13; op2:f13; op2val:-0x1000001; immval:0xa8; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 2*FLEN/8; +TEST_STORE_F(x1,x2,0,x13,f13,0xa8,4*SIGALIGN,c.fsd,0,x4,x3, 2*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_3) + +inst_3:// rs1==x12, rs2==f12,imm_val == 80, +// opcode: c.fsd; op1:x12; op2:f12; op2val:-0x1000001; immval:0x50; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 3*FLEN/8; +TEST_STORE_F(x1,x2,0,x12,f12,0x50,6*SIGALIGN,c.fsd,0,x4,x3, 3*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_4) + +inst_4:// rs1==x11, rs2==f11,imm_val == 8, +// opcode: c.fsd; op1:x11; op2:f11; op2val:-0x1000001; immval:0x8; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 4*FLEN/8; +TEST_STORE_F(x1,x2,0,x11,f11,0x8,8*SIGALIGN,c.fsd,0,x4,x3, 4*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_5) + +inst_5:// rs1==x10, rs2==f10,imm_val == 16, +// opcode: c.fsd; op1:x10; op2:f10; op2val:-0x1000001; immval:0x10; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 5*FLEN/8; +TEST_STORE_F(x1,x2,0,x10,f10,0x10,10*SIGALIGN,c.fsd,0,x4,x3, 5*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_6) + +inst_6:// rs1==x9, rs2==f9,imm_val == 240, +// opcode: c.fsd; op1:x9; op2:f9; op2val:-0x1000001; immval:0xf0; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 6*FLEN/8; +TEST_STORE_F(x1,x2,0,x9,f9,0xf0,12*SIGALIGN,c.fsd,0,x4,x3, 6*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_7) + +inst_7:// rs1==x8, rs2==f8,imm_val == 232, +// opcode: c.fsd; op1:x8; op2:f8; op2val:-0x1000001; immval:0xe8; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 7*FLEN/8; +TEST_STORE_F(x1,x2,0,x8,f8,0xe8,14*SIGALIGN,c.fsd,0,x4,x3, 7*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_8) + +inst_8:// imm_val == 216, +// opcode: c.fsd; op1:x15; op2:f15; op2val:-0x1000001; immval:0xd8; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 8*FLEN/8; +TEST_STORE_F(x1,x2,0,x15,f15,0xd8,16*SIGALIGN,c.fsd,0,x4,x3, 8*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_9) + +inst_9:// imm_val == 184, +// opcode: c.fsd; op1:x15; op2:f15; op2val:-0x1000001; immval:0xb8; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 9*FLEN/8; +TEST_STORE_F(x1,x2,0,x15,f15,0xb8,18*SIGALIGN,c.fsd,0,x4,x3, 9*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_10) + +inst_10:// imm_val == 120, +// opcode: c.fsd; op1:x15; op2:f15; op2val:-0x1000001; immval:0x78; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 10*FLEN/8; +TEST_STORE_F(x1,x2,0,x15,f15,0x78,20*SIGALIGN,c.fsd,0,x4,x3, 10*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_11) + +inst_11:// imm_val == 32, +// opcode: c.fsd; op1:x15; op2:f15; op2val:-0x1000001; immval:0x20; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 11*FLEN/8; +TEST_STORE_F(x1,x2,0,x15,f15,0x20,22*SIGALIGN,c.fsd,0,x4,x3, 11*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_12) + +inst_12:// imm_val == 64, +// opcode: c.fsd; op1:x15; op2:f15; op2val:-0x1000001; immval:0x40; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 12*FLEN/8; +TEST_STORE_F(x1,x2,0,x15,f15,0x40,24*SIGALIGN,c.fsd,0,x4,x3, 12*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_13) + +inst_13:// imm_val == 128, +// opcode: c.fsd; op1:x15; op2:f15; op2val:-0x1000001; immval:0x80; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 13*FLEN/8; +TEST_STORE_F(x1,x2,0,x15,f15,0x80,26*SIGALIGN,c.fsd,0,x4,x3, 13*FLEN/8) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: + + +test_dataset_1: + + +test_dataset_2: + + +test_dataset_3: + + +test_dataset_4: + + +test_dataset_5: + + +test_dataset_6: + + +test_dataset_7: + + +test_dataset_8: + + +test_dataset_9: + + +test_dataset_10: + + +test_dataset_11: + + +test_dataset_12: + + +test_dataset_13: + + +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/D_Zcd/src/c.fsdsp-01.S b/riscv-test-suite/rv32i_m/D_Zcd/src/c.fsdsp-01.S new file mode 100644 index 000000000..5a044aa7a --- /dev/null +++ b/riscv-test-suite/rv32i_m/D_Zcd/src/c.fsdsp-01.S @@ -0,0 +1,343 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.0 +// timestamp : Wed Aug 16 04:41:22 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/riscv-ctg/sample_cgfs/RV32C/fsdsp.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.fsdsp instruction of the RISC-V RV32FDC,RV64FDC extension for the c.fsdsp covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IFDC,RV64IFDC") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*C.*);def TEST_CASE_1=True;",c.fsdsp) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x4,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0:// rs2==f31, imm_val == 0, +// opcode: c.fsdsp; op1:x2; op2:f31; op2val:-0x1000001; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 0*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f31,0x0,0*SIGALIGN,c.fsdsp,0,x5,x4,0*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_1) + +inst_1:// rs2==f30, imm_val > 0, +// opcode: c.fsdsp; op1:x2; op2:f30; op2val:-0x1000001; immval:0x1f8; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 1*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f30,0x1f8,2*SIGALIGN,c.fsdsp,0,x5,x4,1*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_2) + +inst_2:// rs2==f29, imm_val == 168, +// opcode: c.fsdsp; op1:x2; op2:f29; op2val:-0x1000001; immval:0xa8; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 2*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f29,0xa8,4*SIGALIGN,c.fsdsp,0,x5,x4,2*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_3) + +inst_3:// rs2==f28, imm_val == 336, +// opcode: c.fsdsp; op1:x2; op2:f28; op2val:-0x1000001; immval:0x150; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 3*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f28,0x150,6*SIGALIGN,c.fsdsp,0,x5,x4,3*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_4) + +inst_4:// rs2==f27, imm_val == 496, +// opcode: c.fsdsp; op1:x2; op2:f27; op2val:-0x1000001; immval:0x1f0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 4*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f27,0x1f0,8*SIGALIGN,c.fsdsp,0,x5,x4,4*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_5) + +inst_5:// rs2==f26, imm_val == 488, +// opcode: c.fsdsp; op1:x2; op2:f26; op2val:-0x1000001; immval:0x1e8; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 5*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f26,0x1e8,10*SIGALIGN,c.fsdsp,0,x5,x4,5*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_6) + +inst_6:// rs2==f25, imm_val == 472, +// opcode: c.fsdsp; op1:x2; op2:f25; op2val:-0x1000001; immval:0x1d8; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 6*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f25,0x1d8,12*SIGALIGN,c.fsdsp,0,x5,x4,6*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_7) + +inst_7:// rs2==f24, imm_val == 440, +// opcode: c.fsdsp; op1:x2; op2:f24; op2val:-0x1000001; immval:0x1b8; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 7*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f24,0x1b8,14*SIGALIGN,c.fsdsp,0,x5,x4,7*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_8) + +inst_8:// rs2==f23, imm_val == 376, +// opcode: c.fsdsp; op1:x2; op2:f23; op2val:-0x1000001; immval:0x178; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 8*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f23,0x178,16*SIGALIGN,c.fsdsp,0,x5,x4,8*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_9) + +inst_9:// rs2==f22, imm_val == 248, +// opcode: c.fsdsp; op1:x2; op2:f22; op2val:-0x1000001; immval:0xf8; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 9*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f22,0xf8,18*SIGALIGN,c.fsdsp,0,x5,x4,9*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_10) + +inst_10:// rs2==f21, imm_val == 8, +// opcode: c.fsdsp; op1:x2; op2:f21; op2val:-0x1000001; immval:0x8; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 10*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f21,0x8,20*SIGALIGN,c.fsdsp,0,x5,x4,10*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_11) + +inst_11:// rs2==f20, imm_val == 16, +// opcode: c.fsdsp; op1:x2; op2:f20; op2val:-0x1000001; immval:0x10; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 11*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f20,0x10,22*SIGALIGN,c.fsdsp,0,x5,x4,11*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_12) + +inst_12:// rs2==f19, imm_val == 32, +// opcode: c.fsdsp; op1:x2; op2:f19; op2val:-0x1000001; immval:0x20; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 12*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f19,0x20,24*SIGALIGN,c.fsdsp,0,x5,x4,12*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_13) + +inst_13:// rs2==f18, imm_val == 64, +// opcode: c.fsdsp; op1:x2; op2:f18; op2val:-0x1000001; immval:0x40; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 13*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f18,0x40,26*SIGALIGN,c.fsdsp,0,x5,x4,13*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_14) + +inst_14:// rs2==f17, imm_val == 128, +// opcode: c.fsdsp; op1:x2; op2:f17; op2val:-0x1000001; immval:0x80; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 14*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f17,0x80,28*SIGALIGN,c.fsdsp,0,x5,x4,14*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_15) + +inst_15:// rs2==f16, imm_val == 256, +// opcode: c.fsdsp; op1:x2; op2:f16; op2val:-0x1000001; immval:0x100; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 15*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f16,0x100,30*SIGALIGN,c.fsdsp,0,x5,x4,15*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_16) + +inst_16:// rs2==f15, +// opcode: c.fsdsp; op1:x2; op2:f15; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 16*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f15,0x0,32*SIGALIGN,c.fsdsp,0,x5,x4,16*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_17) + +inst_17:// rs2==f14, +// opcode: c.fsdsp; op1:x2; op2:f14; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 17*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f14,0x0,34*SIGALIGN,c.fsdsp,0,x5,x4,17*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_18) + +inst_18:// rs2==f13, +// opcode: c.fsdsp; op1:x2; op2:f13; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 18*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f13,0x0,36*SIGALIGN,c.fsdsp,0,x5,x4,18*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_19) + +inst_19:// rs2==f12, +// opcode: c.fsdsp; op1:x2; op2:f12; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 19*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f12,0x0,38*SIGALIGN,c.fsdsp,0,x5,x4,19*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_20) + +inst_20:// rs2==f11, +// opcode: c.fsdsp; op1:x2; op2:f11; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 20*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f11,0x0,40*SIGALIGN,c.fsdsp,0,x5,x4,20*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_21) + +inst_21:// rs2==f10, +// opcode: c.fsdsp; op1:x2; op2:f10; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 21*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f10,0x0,42*SIGALIGN,c.fsdsp,0,x5,x4,21*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_22) + +inst_22:// rs2==f9, +// opcode: c.fsdsp; op1:x2; op2:f9; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 22*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f9,0x0,44*SIGALIGN,c.fsdsp,0,x5,x4,22*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_23) + +inst_23:// rs2==f8, +// opcode: c.fsdsp; op1:x2; op2:f8; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 23*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f8,0x0,46*SIGALIGN,c.fsdsp,0,x5,x4,23*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_24) + +inst_24:// rs2==f7, +// opcode: c.fsdsp; op1:x2; op2:f7; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 24*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f7,0x0,48*SIGALIGN,c.fsdsp,0,x5,x4,24*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_25) + +inst_25:// rs2==f6, +// opcode: c.fsdsp; op1:x2; op2:f6; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 25*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f6,0x0,50*SIGALIGN,c.fsdsp,0,x5,x4,25*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_26) + +inst_26:// rs2==f5, +// opcode: c.fsdsp; op1:x2; op2:f5; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 26*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f5,0x0,52*SIGALIGN,c.fsdsp,0,x5,x4,26*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_27) + +inst_27:// rs2==f4, +// opcode: c.fsdsp; op1:x2; op2:f4; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 27*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f4,0x0,54*SIGALIGN,c.fsdsp,0,x5,x4,27*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_28) + +inst_28:// rs2==f3, +// opcode: c.fsdsp; op1:x2; op2:f3; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 28*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f3,0x0,56*SIGALIGN,c.fsdsp,0,x5,x4,28*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_29) + +inst_29:// rs2==f2, +// opcode: c.fsdsp; op1:x2; op2:f2; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 29*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f2,0x0,58*SIGALIGN,c.fsdsp,0,x5,x4,29*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_30) + +inst_30:// rs2==f1, +// opcode: c.fsdsp; op1:x2; op2:f1; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 30*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f1,0x0,60*SIGALIGN,c.fsdsp,0,x5,x4,30*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_31) + +inst_31:// rs2==f0, +// opcode: c.fsdsp; op1:x2; op2:f0; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 31*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f0,0x0,62*SIGALIGN,c.fsdsp,0,x5,x4,31*FLEN/8) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: + +test_dataset_1: + +test_dataset_2: + +test_dataset_3: + +test_dataset_4: + +test_dataset_5: + +test_dataset_6: + +test_dataset_7: + +test_dataset_8: + +test_dataset_9: + +test_dataset_10: + +test_dataset_11: + +test_dataset_12: + +test_dataset_13: + +test_dataset_14: + +test_dataset_15: + +test_dataset_16: + +test_dataset_17: + +test_dataset_18: + +test_dataset_19: + +test_dataset_20: + +test_dataset_21: + +test_dataset_22: + +test_dataset_23: + +test_dataset_24: + +test_dataset_25: + +test_dataset_26: + +test_dataset_27: + +test_dataset_28: + +test_dataset_29: + +test_dataset_30: + +test_dataset_31: + +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 64*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/F_Zcf/src/c.flw-01.S b/riscv-test-suite/rv32i_m/F_Zcf/src/c.flw-01.S new file mode 100644 index 000000000..043e33306 --- /dev/null +++ b/riscv-test-suite/rv32i_m/F_Zcf/src/c.flw-01.S @@ -0,0 +1,173 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.0 +// timestamp : Thu Aug 3 07:43:25 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/riscv-ctg/sample_cgfs/RV32C/FLW.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.flw instruction of the RISC-V RV32F_Zcf extension for the c.flw covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IF_Zcf") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zcf.*);def TEST_CASE_1=True;",c.flw) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1==x15, rd==f15,imm_val == 0 and fcsr == 0, +// opcode:c.flw; op1:x15; dest:f15; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,0,x15,f15,0x0,c.flw,0,x4) + +inst_1: +// rs1==x14, rd==f14,imm_val > 0 and fcsr == 0, +// opcode:c.flw; op1:x14; dest:f14; immval:0x7c; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,0,x14,f14,0x7c,c.flw,0,x4) + +inst_2: +// rs1==x13, rd==f13,imm_val == 84, +// opcode:c.flw; op1:x13; dest:f13; immval:0x54; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x13,f13,0x54,c.flw,0,x4) + +inst_3: +// rs1==x12, rd==f12,imm_val == 40, +// opcode:c.flw; op1:x12; dest:f12; immval:0x28; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x12,f12,0x28,c.flw,0,x4) + +inst_4: +// rs1==x11, rd==f11,imm_val == 4, +// opcode:c.flw; op1:x11; dest:f11; immval:0x4; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x11,f11,0x4,c.flw,0,x4) + +inst_5: +// rs1==x10, rd==f10,imm_val == 120, +// opcode:c.flw; op1:x10; dest:f10; immval:0x78; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x10,f10,0x78,c.flw,0,x4) + +inst_6: +// rs1==x9, rd==f9,imm_val == 116, +// opcode:c.flw; op1:x9; dest:f9; immval:0x74; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x9,f9,0x74,c.flw,0,x4) + +inst_7: +// rs1==x8, rd==f8,imm_val == 108, +// opcode:c.flw; op1:x8; dest:f8; immval:0x6c; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x8,f8,0x6c,c.flw,0,x4) + +inst_8: +// imm_val == 92, +// opcode:c.flw; op1:x15; dest:f15; immval:0x5c; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x15,f15,0x5c,c.flw,0,x4) + +inst_9: +// imm_val == 60, +// opcode:c.flw; op1:x15; dest:f15; immval:0x3c; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x15,f15,0x3c,c.flw,0,x4) + +inst_10: +// imm_val == 8, +// opcode:c.flw; op1:x15; dest:f15; immval:0x8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x15,f15,0x8,c.flw,0,x4) + +inst_11: +// imm_val == 16, +// opcode:c.flw; op1:x15; dest:f15; immval:0x10; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x15,f15,0x10,c.flw,0,x4) + +inst_12: +// imm_val == 32, +// opcode:c.flw; op1:x15; dest:f15; immval:0x20; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x15,f15,0x20,c.flw,0,x4) + +inst_13: +// imm_val == 64, +// opcode:c.flw; op1:x15; dest:f15; immval:0x40; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x15,f15,0x40,c.flw,0,x4) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: + + + + + + + + + + + + + + +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/F_Zcf/src/c.flwsp-01.S b/riscv-test-suite/rv32i_m/F_Zcf/src/c.flwsp-01.S new file mode 100644 index 000000000..33806012a --- /dev/null +++ b/riscv-test-suite/rv32i_m/F_Zcf/src/c.flwsp-01.S @@ -0,0 +1,249 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.0 +// timestamp : Thu Aug 10 08:04:09 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/riscv-ctg/sample_cgfs/RV32C/flwsp.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.flwsp instruction of the RISC-V RV32F_Zcf extension for the c.flwsp covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IF_Zcf") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zcf.*);def TEST_CASE_1=True;",c.flwsp) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x4,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rd==f31, imm_val == 0 and fcsr == 0, +// opcode:c.flwsp; op1:x2; dest:f31; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f31,0x0,c.flwsp,0,x4) + +inst_1: +// rd==f30, imm_val > 0 and fcsr == 0, +// opcode:c.flwsp; op1:x2; dest:f30; immval:0xfc; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f30,0xfc,c.flwsp,0,x4) + +inst_2: +// rd==f29, imm_val == 84, +// opcode:c.flwsp; op1:x2; dest:f29; immval:0x54; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,159,x2,f29,0x54,c.flwsp,0,x4) + +inst_3: +// rd==f28, imm_val == 168, +// opcode:c.flwsp; op1:x2; dest:f28; immval:0xa8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,159,x2,f28,0xa8,c.flwsp,0,x4) + +inst_4: +// rd==f27, imm_val == 248, +// opcode:c.flwsp; op1:x2; dest:f27; immval:0xf8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,159,x2,f27,0xf8,c.flwsp,0,x4) + +inst_5: +// rd==f26, imm_val == 244, +// opcode:c.flwsp; op1:x2; dest:f26; immval:0xf4; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,159,x2,f26,0xf4,c.flwsp,0,x4) + +inst_6: +// rd==f25, imm_val == 236, +// opcode:c.flwsp; op1:x2; dest:f25; immval:0xec; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,159,x2,f25,0xec,c.flwsp,0,x4) + +inst_7: +// rd==f24, imm_val == 220, +// opcode:c.flwsp; op1:x2; dest:f24; immval:0xdc; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,159,x2,f24,0xdc,c.flwsp,0,x4) + +inst_8: +// rd==f23, imm_val == 188, +// opcode:c.flwsp; op1:x2; dest:f23; immval:0xbc; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,159,x2,f23,0xbc,c.flwsp,0,x4) + +inst_9: +// rd==f22, imm_val == 124, +// opcode:c.flwsp; op1:x2; dest:f22; immval:0x7c; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,159,x2,f22,0x7c,c.flwsp,0,x4) + +inst_10: +// rd==f21, imm_val == 4, +// opcode:c.flwsp; op1:x2; dest:f21; immval:0x4; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,159,x2,f21,0x4,c.flwsp,0,x4) + +inst_11: +// rd==f20, imm_val == 8, +// opcode:c.flwsp; op1:x2; dest:f20; immval:0x8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,159,x2,f20,0x8,c.flwsp,0,x4) + +inst_12: +// rd==f19, imm_val == 16, +// opcode:c.flwsp; op1:x2; dest:f19; immval:0x10; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,159,x2,f19,0x10,c.flwsp,0,x4) + +inst_13: +// rd==f18, imm_val == 32, +// opcode:c.flwsp; op1:x2; dest:f18; immval:0x20; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,159,x2,f18,0x20,c.flwsp,0,x4) + +inst_14: +// rd==f17, imm_val == 64, +// opcode:c.flwsp; op1:x2; dest:f17; immval:0x40; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,159,x2,f17,0x40,c.flwsp,0,x4) + +inst_15: +// rd==f16, imm_val == 128, +// opcode:c.flwsp; op1:x2; dest:f16; immval:0x80; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,159,x2,f16,0x80,c.flwsp,0,x4) + +inst_16: +// rd==f15, +// opcode:c.flwsp; op1:x2; dest:f15; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f15,0x0,c.flwsp,0,x4) + +inst_17: +// rd==f14, +// opcode:c.flwsp; op1:x2; dest:f14; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f14,0x0,c.flwsp,0,x4) + +inst_18: +// rd==f13, +// opcode:c.flwsp; op1:x2; dest:f13; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f13,0x0,c.flwsp,0,x4) + +inst_19: +// rd==f12, +// opcode:c.flwsp; op1:x2; dest:f12; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f12,0x0,c.flwsp,0,x4) + +inst_20: +// rd==f11, +// opcode:c.flwsp; op1:x2; dest:f11; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f11,0x0,c.flwsp,0,x4) + +inst_21: +// rd==f10, +// opcode:c.flwsp; op1:x2; dest:f10; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f10,0x0,c.flwsp,0,x4) + +inst_22: +// rd==f9, +// opcode:c.flwsp; op1:x2; dest:f9; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f9,0x0,c.flwsp,0,x4) + +inst_23: +// rd==f8, +// opcode:c.flwsp; op1:x2; dest:f8; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f8,0x0,c.flwsp,0,x4) + +inst_24: +// rd==f7, +// opcode:c.flwsp; op1:x2; dest:f7; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f7,0x0,c.flwsp,0,x4) + +inst_25: +// rd==f6, +// opcode:c.flwsp; op1:x2; dest:f6; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f6,0x0,c.flwsp,0,x4) + +inst_26: +// rd==f5, +// opcode:c.flwsp; op1:x2; dest:f5; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f5,0x0,c.flwsp,0,x4) + +inst_27: +// rd==f4, +// opcode:c.flwsp; op1:x2; dest:f4; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f4,0x0,c.flwsp,0,x4) + +inst_28: +// rd==f3, +// opcode:c.flwsp; op1:x2; dest:f3; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f3,0x0,c.flwsp,0,x4) + +inst_29: +// rd==f2, +// opcode:c.flwsp; op1:x2; dest:f2; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f2,0x0,c.flwsp,0,x4) + +inst_30: +// rd==f1, +// opcode:c.flwsp; op1:x2; dest:f1; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f1,0x0,c.flwsp,0,x4) + +inst_31: +// rd==f0, +// opcode:c.flwsp; op1:x2; dest:f0; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f0,0x0,c.flwsp,0,x4) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 64*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/F_Zcf/src/c.fsw-01.S b/riscv-test-suite/rv32i_m/F_Zcf/src/c.fsw-01.S new file mode 100644 index 000000000..7b95fadd6 --- /dev/null +++ b/riscv-test-suite/rv32i_m/F_Zcf/src/c.fsw-01.S @@ -0,0 +1,213 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.0 +// timestamp : Thu Aug 3 07:43:25 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/riscv-ctg/sample_cgfs/RV32C/FLW.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.fsw instruction of the RISC-V RV32F_Zcf extension for the c.fsw covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IF_Zcf") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zcf.*);def TEST_CASE_1=True;",c.fsw) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0:// rs1 != rs2, rs1==x15, rs2==f15,imm_val == 0, +// opcode: c.fsw; op1:x15; op2:f15; op2val:-0x1000001; immval:0x0; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 0*FLEN/8 +TEST_STORE_F(x1,x2,$fcsr,x15,f15,0x0,0*SIGALIGN,c.fsw,0,x4,x3, 0*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_1) + +inst_1:// rs1==x14, rs2==f14,imm_val > 0, +// opcode: c.fsw; op1:x14; op2:f14; op2val:-0x1000001; immval:0x7c; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 1*FLEN/8 +TEST_STORE_F(x1,x2,$fcsr,x14,f14,0x7c,1*SIGALIGN,c.fsw,0,x4,x3, 1*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_2) + +inst_2:// rs1==x13, rs2==f13,imm_val == 84, +// opcode: c.fsw; op1:x13; op2:f13; op2val:-0x1000001; immval:0x54; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 2*FLEN/8 +TEST_STORE_F(x1,x2,$fcsr,x13,f13,0x54,2*SIGALIGN,c.fsw,0,x4,x3, 2*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_3) + +inst_3:// rs1==x12, rs2==f12,imm_val == 40, +// opcode: c.fsw; op1:x12; op2:f12; op2val:-0x1000001; immval:0x28; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 3*FLEN/8 +TEST_STORE_F(x1,x2,$fcsr,x12,f12,0x28,3*SIGALIGN,c.fsw,0,x4,x3, 3*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_4) + +inst_4:// rs1==x11, rs2==f11,imm_val == 4, +// opcode: c.fsw; op1:x11; op2:f11; op2val:-0x1000001; immval:0x4; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 4*FLEN/8 +TEST_STORE_F(x1,x2,$fcsr,x11,f11,0x4,4*SIGALIGN,c.fsw,0,x4,x3, 4*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_5) + +inst_5:// rs1==x10, rs2==f10,imm_val == 8, +// opcode: c.fsw; op1:x10; op2:f10; op2val:-0x1000001; immval:0x8; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 5*FLEN/8 +TEST_STORE_F(x1,x2,$fcsr,x10,f10,0x8,5*SIGALIGN,c.fsw,0,x4,x3, 5*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_6) + +inst_6:// rs1==x9, rs2==f9,imm_val == 120, +// opcode: c.fsw; op1:x9; op2:f9; op2val:-0x1000001; immval:0x78; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 6*FLEN/8 +TEST_STORE_F(x1,x2,$fcsr,x9,f9,0x78,6*SIGALIGN,c.fsw,0,x4,x3, 6*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_7) + +inst_7:// rs1==x8, rs2==f8,imm_val == 116, +// opcode: c.fsw; op1:x8; op2:f8; op2val:-0x1000001; immval:0x74; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 7*FLEN/8 +TEST_STORE_F(x1,x2,$fcsr,x8,f8,0x74,7*SIGALIGN,c.fsw,0,x4,x3, 7*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_8) + +inst_8:// imm_val == 108, +// opcode: c.fsw; op1:x15; op2:f15; op2val:-0x1000001; immval:0x6c; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 8*FLEN/8 +TEST_STORE_F(x1,x2,$fcsr,x15,f15,0x6c,8*SIGALIGN,c.fsw,0,x4,x3, 8*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_9) + +inst_9:// imm_val == 92, +// opcode: c.fsw; op1:x15; op2:f15; op2val:-0x1000001; immval:0x5c; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 9*FLEN/8 +TEST_STORE_F(x1,x2,$fcsr,x15,f15,0x5c,9*SIGALIGN,c.fsw,0,x4,x3, 9*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_10) + +inst_10:// imm_val == 60, +// opcode: c.fsw; op1:x15; op2:f15; op2val:-0x1000001; immval:0x3c; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 10*FLEN/8 +TEST_STORE_F(x1,x2,$fcsr,x15,f15,0x3c,10*SIGALIGN,c.fsw,0,x4,x3, 10*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_11) + +inst_11:// imm_val == 16, +// opcode: c.fsw; op1:x15; op2:f15; op2val:-0x1000001; immval:0x10; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 11*FLEN/8 +TEST_STORE_F(x1,x2,$fcsr,x15,f15,0x10,11*SIGALIGN,c.fsw,0,x4,x3, 11*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_12) + +inst_12:// imm_val == 32, +// opcode: c.fsw; op1:x15; op2:f15; op2val:-0x1000001; immval:0x20; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 12*FLEN/8 +TEST_STORE_F(x1,x2,$fcsr,x15,f15,0x20,12*SIGALIGN,c.fsw,0,x4,x3, 12*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_13) + +inst_13:// imm_val == 64, +// opcode: c.fsw; op1:x15; op2:f15; op2val:-0x1000001; immval:0x40; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 13*FLEN/8 +TEST_STORE_F(x1,x2,$fcsr,x15,f15,0x40,13*SIGALIGN,c.fsw,0,x4,x3, 13*FLEN/8) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: + + +test_dataset_1: + + +test_dataset_2: + + +test_dataset_3: + + +test_dataset_4: + + +test_dataset_5: + + +test_dataset_6: + + +test_dataset_7: + + +test_dataset_8: + + +test_dataset_9: + + +test_dataset_10: + + +test_dataset_11: + + +test_dataset_12: + + +test_dataset_13: + + +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 14*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/F_Zcf/src/c.fswsp-01.S b/riscv-test-suite/rv32i_m/F_Zcf/src/c.fswsp-01.S new file mode 100644 index 000000000..7908a2bb8 --- /dev/null +++ b/riscv-test-suite/rv32i_m/F_Zcf/src/c.fswsp-01.S @@ -0,0 +1,343 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.0 +// timestamp : Wed Aug 16 04:45:36 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/riscv-ctg/sample_cgfs/RV32C/fswsp.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.fswsp instruction of the RISC-V RV32FC extension for the c.fswsp covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IFC") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*C.*);def TEST_CASE_1=True;",c.fswsp) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x4,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0:// rs2==f31, imm_val == 0, +// opcode: c.fswsp; op1:x2; op2:f31; op2val:-0x1000001; immval:0x0; align:0; flagreg:x5; +// valreg: x4; valoffset: 0*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f31,0x0,0*SIGALIGN,c.fswsp,0,x5,x4,0*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_1) + +inst_1:// rs2==f30, imm_val > 0, +// opcode: c.fswsp; op1:x2; op2:f30; op2val:-0x1000001; immval:0xfc; align:0; flagreg:x5; +// valreg: x4; valoffset: 1*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f30,0xfc,1*SIGALIGN,c.fswsp,0,x5,x4,1*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_2) + +inst_2:// rs2==f29, imm_val == 84, +// opcode: c.fswsp; op1:x2; op2:f29; op2val:-0x1000001; immval:0x54; align:0; flagreg:x5; +// valreg: x4; valoffset: 2*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f29,0x54,2*SIGALIGN,c.fswsp,0,x5,x4,2*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_3) + +inst_3:// rs2==f28, imm_val == 168, +// opcode: c.fswsp; op1:x2; op2:f28; op2val:-0x1000001; immval:0xa8; align:0; flagreg:x5; +// valreg: x4; valoffset: 3*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f28,0xa8,3*SIGALIGN,c.fswsp,0,x5,x4,3*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_4) + +inst_4:// rs2==f27, imm_val == 248, +// opcode: c.fswsp; op1:x2; op2:f27; op2val:-0x1000001; immval:0xf8; align:0; flagreg:x5; +// valreg: x4; valoffset: 4*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f27,0xf8,4*SIGALIGN,c.fswsp,0,x5,x4,4*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_5) + +inst_5:// rs2==f26, imm_val == 244, +// opcode: c.fswsp; op1:x2; op2:f26; op2val:-0x1000001; immval:0xf4; align:0; flagreg:x5; +// valreg: x4; valoffset: 5*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f26,0xf4,5*SIGALIGN,c.fswsp,0,x5,x4,5*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_6) + +inst_6:// rs2==f25, imm_val == 236, +// opcode: c.fswsp; op1:x2; op2:f25; op2val:-0x1000001; immval:0xec; align:0; flagreg:x5; +// valreg: x4; valoffset: 6*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f25,0xec,6*SIGALIGN,c.fswsp,0,x5,x4,6*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_7) + +inst_7:// rs2==f24, imm_val == 220, +// opcode: c.fswsp; op1:x2; op2:f24; op2val:-0x1000001; immval:0xdc; align:0; flagreg:x5; +// valreg: x4; valoffset: 7*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f24,0xdc,7*SIGALIGN,c.fswsp,0,x5,x4,7*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_8) + +inst_8:// rs2==f23, imm_val == 188, +// opcode: c.fswsp; op1:x2; op2:f23; op2val:-0x1000001; immval:0xbc; align:0; flagreg:x5; +// valreg: x4; valoffset: 8*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f23,0xbc,8*SIGALIGN,c.fswsp,0,x5,x4,8*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_9) + +inst_9:// rs2==f22, imm_val == 124, +// opcode: c.fswsp; op1:x2; op2:f22; op2val:-0x1000001; immval:0x7c; align:0; flagreg:x5; +// valreg: x4; valoffset: 9*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f22,0x7c,9*SIGALIGN,c.fswsp,0,x5,x4,9*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_10) + +inst_10:// rs2==f21, imm_val == 4, +// opcode: c.fswsp; op1:x2; op2:f21; op2val:-0x1000001; immval:0x4; align:0; flagreg:x5; +// valreg: x4; valoffset: 10*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f21,0x4,10*SIGALIGN,c.fswsp,0,x5,x4,10*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_11) + +inst_11:// rs2==f20, imm_val == 8, +// opcode: c.fswsp; op1:x2; op2:f20; op2val:-0x1000001; immval:0x8; align:0; flagreg:x5; +// valreg: x4; valoffset: 11*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f20,0x8,11*SIGALIGN,c.fswsp,0,x5,x4,11*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_12) + +inst_12:// rs2==f19, imm_val == 16, +// opcode: c.fswsp; op1:x2; op2:f19; op2val:-0x1000001; immval:0x10; align:0; flagreg:x5; +// valreg: x4; valoffset: 12*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f19,0x10,12*SIGALIGN,c.fswsp,0,x5,x4,12*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_13) + +inst_13:// rs2==f18, imm_val == 32, +// opcode: c.fswsp; op1:x2; op2:f18; op2val:-0x1000001; immval:0x20; align:0; flagreg:x5; +// valreg: x4; valoffset: 13*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f18,0x20,13*SIGALIGN,c.fswsp,0,x5,x4,13*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_14) + +inst_14:// rs2==f17, imm_val == 64, +// opcode: c.fswsp; op1:x2; op2:f17; op2val:-0x1000001; immval:0x40; align:0; flagreg:x5; +// valreg: x4; valoffset: 14*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f17,0x40,14*SIGALIGN,c.fswsp,0,x5,x4,14*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_15) + +inst_15:// rs2==f16, imm_val == 128, +// opcode: c.fswsp; op1:x2; op2:f16; op2val:-0x1000001; immval:0x80; align:0; flagreg:x5; +// valreg: x4; valoffset: 15*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f16,0x80,15*SIGALIGN,c.fswsp,0,x5,x4,15*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_16) + +inst_16:// rs2==f15, +// opcode: c.fswsp; op1:x2; op2:f15; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4; valoffset: 16*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f15,0x0,16*SIGALIGN,c.fswsp,0,x5,x4,16*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_17) + +inst_17:// rs2==f14, +// opcode: c.fswsp; op1:x2; op2:f14; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4; valoffset: 17*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f14,0x0,17*SIGALIGN,c.fswsp,0,x5,x4,17*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_18) + +inst_18:// rs2==f13, +// opcode: c.fswsp; op1:x2; op2:f13; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4; valoffset: 18*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f13,0x0,18*SIGALIGN,c.fswsp,0,x5,x4,18*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_19) + +inst_19:// rs2==f12, +// opcode: c.fswsp; op1:x2; op2:f12; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4; valoffset: 19*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f12,0x0,19*SIGALIGN,c.fswsp,0,x5,x4,19*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_20) + +inst_20:// rs2==f11, +// opcode: c.fswsp; op1:x2; op2:f11; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4; valoffset: 20*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f11,0x0,20*SIGALIGN,c.fswsp,0,x5,x4,20*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_21) + +inst_21:// rs2==f10, +// opcode: c.fswsp; op1:x2; op2:f10; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4; valoffset: 21*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f10,0x0,21*SIGALIGN,c.fswsp,0,x5,x4,21*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_22) + +inst_22:// rs2==f9, +// opcode: c.fswsp; op1:x2; op2:f9; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4; valoffset: 22*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f9,0x0,22*SIGALIGN,c.fswsp,0,x5,x4,22*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_23) + +inst_23:// rs2==f8, +// opcode: c.fswsp; op1:x2; op2:f8; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4; valoffset: 23*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f8,0x0,23*SIGALIGN,c.fswsp,0,x5,x4,23*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_24) + +inst_24:// rs2==f7, +// opcode: c.fswsp; op1:x2; op2:f7; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4; valoffset: 24*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f7,0x0,24*SIGALIGN,c.fswsp,0,x5,x4,24*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_25) + +inst_25:// rs2==f6, +// opcode: c.fswsp; op1:x2; op2:f6; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4; valoffset: 25*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f6,0x0,25*SIGALIGN,c.fswsp,0,x5,x4,25*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_26) + +inst_26:// rs2==f5, +// opcode: c.fswsp; op1:x2; op2:f5; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4; valoffset: 26*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f5,0x0,26*SIGALIGN,c.fswsp,0,x5,x4,26*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_27) + +inst_27:// rs2==f4, +// opcode: c.fswsp; op1:x2; op2:f4; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4; valoffset: 27*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f4,0x0,27*SIGALIGN,c.fswsp,0,x5,x4,27*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_28) + +inst_28:// rs2==f3, +// opcode: c.fswsp; op1:x2; op2:f3; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4; valoffset: 28*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f3,0x0,28*SIGALIGN,c.fswsp,0,x5,x4,28*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_29) + +inst_29:// rs2==f2, +// opcode: c.fswsp; op1:x2; op2:f2; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4; valoffset: 29*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f2,0x0,29*SIGALIGN,c.fswsp,0,x5,x4,29*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_30) + +inst_30:// rs2==f1, +// opcode: c.fswsp; op1:x2; op2:f1; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4; valoffset: 30*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f1,0x0,30*SIGALIGN,c.fswsp,0,x5,x4,30*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_31) + +inst_31:// rs2==f0, +// opcode: c.fswsp; op1:x2; op2:f0; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4; valoffset: 31*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f0,0x0,31*SIGALIGN,c.fswsp,0,x5,x4,31*FLEN/8) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: + +test_dataset_1: + +test_dataset_2: + +test_dataset_3: + +test_dataset_4: + +test_dataset_5: + +test_dataset_6: + +test_dataset_7: + +test_dataset_8: + +test_dataset_9: + +test_dataset_10: + +test_dataset_11: + +test_dataset_12: + +test_dataset_13: + +test_dataset_14: + +test_dataset_15: + +test_dataset_16: + +test_dataset_17: + +test_dataset_18: + +test_dataset_19: + +test_dataset_20: + +test_dataset_21: + +test_dataset_22: + +test_dataset_23: + +test_dataset_24: + +test_dataset_25: + +test_dataset_26: + +test_dataset_27: + +test_dataset_28: + +test_dataset_29: + +test_dataset_30: + +test_dataset_31: + +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 32*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b1-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b1-01.S new file mode 100644 index 000000000..713b9aa20 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b1-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Fri Sep 13 19:12:48 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.d.h.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.d.h instruction of the RISC-V RV32FD_Zicsr_Zfh,RV64FD_Zicsr_Zfh extension for the fcvt.d.h_b1 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IFD_Zicsr_Zfh,RV64IFD_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.d.h_b1) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f31; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 != rd, rs1==f29, rd==f30,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f29; dest:f30; op1val:0x8000; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f30, f29, 0, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f29; op1val:0x1; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f29, f30, 0, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f27; dest:f28; op1val:0x8001; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f28, f27, 0, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f28; dest:f27; op1val:0x2; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f27, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f25; dest:f26; op1val:0x83fe; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f26; dest:f25; op1val:0x3ff; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f25, f26, 0, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f23; dest:f24; op1val:0x83ff; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f24, f23, 0, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f24; dest:f23; op1val:0x400; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f23, f24, 0, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f21; dest:f22; op1val:0x8400; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f22, f21, 0, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f22; dest:f21; op1val:0x401; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f19; dest:f20; op1val:0x8455; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f20, f19, 0, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f20; dest:f19; op1val:0x7bff; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f19, f20, 0, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f17; dest:f18; op1val:0xfbff; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f18, f17, 0, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f18; dest:f17; op1val:0x7c00; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f17, f18, 0, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f15; dest:f16; op1val:0xfc00; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f16; dest:f15; op1val:0x7e00; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f15, f16, 0, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f13; dest:f14; op1val:0xfe00; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f14, f13, 0, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f14; dest:f13; op1val:0x7e01; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f13, f14, 0, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f11; dest:f12; op1val:0xfe55; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f12, f11, 0, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f12; dest:f11; op1val:0x7c01; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10,fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f9; dest:f10; op1val:0xfd55; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f10, f9, 0, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f10; dest:f9; op1val:0x3c00; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f9, f10, 0, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8,fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f7; dest:f8; op1val:0xbc00; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f8, f7, 0, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7, +/* opcode: fcvt.d.h ; op1:f8; dest:f7; op1val:0x0; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f7, f8, 0, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6, +/* opcode: fcvt.d.h ; op1:f5; dest:f6; op1val:0x0; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5, +/* opcode: fcvt.d.h ; op1:f6; dest:f5; op1val:0x0; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f5, f6, 0, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4, +/* opcode: fcvt.d.h ; op1:f3; dest:f4; op1val:0x0; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f4, f3, 0, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3, +/* opcode: fcvt.d.h ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f3, f4, 0, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2, +/* opcode: fcvt.d.h ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f2, f1, 0, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1, +/* opcode: fcvt.d.h ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0, +/* opcode: fcvt.d.h ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f0, 0, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0, +/* opcode: fcvt.d.h ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f0, f31, 0, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b22-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b22-01.S new file mode 100644 index 000000000..5b5acfff5 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b22-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Fri Sep 13 19:12:48 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.d.h.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.d.h instruction of the RISC-V RV32FD_Zicsr_Zfh,RV64FD_Zicsr_Zfh extension for the fcvt.d.h_b22 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IFD_Zicsr_Zfh,RV64IFD_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.d.h_b22) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f31; dest:f31; op1val:0x3249; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 != rd, rs1==f29, rd==f30,fs1 == 0 and fe1 == 0x0d and fm1 == 0x1b7 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f29; dest:f30; op1val:0x35b7; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f30, f29, 0, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x0e and fm1 == 0x24f and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f29; op1val:0x3a4f; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f29, f30, 0, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x0f and fm1 == 0x0d3 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f27; dest:f28; op1val:0x3cd3; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f28, f27, 0, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x10 and fm1 == 0x340 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f28; dest:f27; op1val:0x4340; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f27, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 0 and fe1 == 0x11 and fm1 == 0x34b and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f25; dest:f26; op1val:0x474b; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 1 and fe1 == 0x07 and fm1 == 0x29d and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f26; dest:f25; op1val:0x9e9d; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f25, f26, 0, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 0 and fe1 == 0x04 and fm1 == 0x023 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f23; dest:f24; op1val:0x1023; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f24, f23, 0, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23, +/* opcode: fcvt.d.h ; op1:f24; dest:f23; op1val:0x0; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f23, f24, 0, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22, +/* opcode: fcvt.d.h ; op1:f21; dest:f22; op1val:0x0; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f22, f21, 0, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21, +/* opcode: fcvt.d.h ; op1:f22; dest:f21; op1val:0x0; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20, +/* opcode: fcvt.d.h ; op1:f19; dest:f20; op1val:0x0; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f20, f19, 0, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19, +/* opcode: fcvt.d.h ; op1:f20; dest:f19; op1val:0x0; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f19, f20, 0, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18, +/* opcode: fcvt.d.h ; op1:f17; dest:f18; op1val:0x0; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f18, f17, 0, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17, +/* opcode: fcvt.d.h ; op1:f18; dest:f17; op1val:0x0; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f17, f18, 0, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16, +/* opcode: fcvt.d.h ; op1:f15; dest:f16; op1val:0x0; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15, +/* opcode: fcvt.d.h ; op1:f16; dest:f15; op1val:0x0; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f15, f16, 0, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14, +/* opcode: fcvt.d.h ; op1:f13; dest:f14; op1val:0x0; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f14, f13, 0, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13, +/* opcode: fcvt.d.h ; op1:f14; dest:f13; op1val:0x0; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f13, f14, 0, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12, +/* opcode: fcvt.d.h ; op1:f11; dest:f12; op1val:0x0; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f12, f11, 0, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11, +/* opcode: fcvt.d.h ; op1:f12; dest:f11; op1val:0x0; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10, +/* opcode: fcvt.d.h ; op1:f9; dest:f10; op1val:0x0; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f10, f9, 0, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9, +/* opcode: fcvt.d.h ; op1:f10; dest:f9; op1val:0x0; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f9, f10, 0, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8, +/* opcode: fcvt.d.h ; op1:f7; dest:f8; op1val:0x0; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f8, f7, 0, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7, +/* opcode: fcvt.d.h ; op1:f8; dest:f7; op1val:0x0; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f7, f8, 0, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6, +/* opcode: fcvt.d.h ; op1:f5; dest:f6; op1val:0x0; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5, +/* opcode: fcvt.d.h ; op1:f6; dest:f5; op1val:0x0; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f5, f6, 0, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4, +/* opcode: fcvt.d.h ; op1:f3; dest:f4; op1val:0x0; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f4, f3, 0, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3, +/* opcode: fcvt.d.h ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f3, f4, 0, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2, +/* opcode: fcvt.d.h ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f2, f1, 0, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1, +/* opcode: fcvt.d.h ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0, +/* opcode: fcvt.d.h ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f0, 0, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0, +/* opcode: fcvt.d.h ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f0, f31, 0, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(12873,16,FLEN) +NAN_BOXED(13751,16,FLEN) +NAN_BOXED(14927,16,FLEN) +NAN_BOXED(15571,16,FLEN) +NAN_BOXED(17216,16,FLEN) +NAN_BOXED(18251,16,FLEN) +NAN_BOXED(40605,16,FLEN) +NAN_BOXED(4131,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b23-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b23-01.S new file mode 100644 index 000000000..452d29d44 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b23-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Fri Sep 13 19:12:48 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.d.h.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.d.h instruction of the RISC-V RV32FD_Zicsr_Zfh,RV64FD_Zicsr_Zfh extension for the fcvt.d.h_b23 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IFD_Zicsr_Zfh,RV64IFD_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.d.h_b23) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f31; dest:f31; op1val:0x77fc; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 != rd, rs1==f29, rd==f30,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fd and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f29; dest:f30; op1val:0x77fd; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f30, f29, 0, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f29; op1val:0x77fe; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f29, f30, 0, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f27; dest:f28; op1val:0x77ff; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f28, f27, 0, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f28; dest:f27; op1val:0x7800; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f27, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f25; dest:f26; op1val:0x7801; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f26; dest:f25; op1val:0x7802; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f25, f26, 0, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 0 and fe1 == 0x1e and fm1 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f23; dest:f24; op1val:0x7803; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f24, f23, 0, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f24; dest:f23; op1val:0x7804; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f23, f24, 0, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22, +/* opcode: fcvt.d.h ; op1:f21; dest:f22; op1val:0x0; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f22, f21, 0, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21, +/* opcode: fcvt.d.h ; op1:f22; dest:f21; op1val:0x0; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20, +/* opcode: fcvt.d.h ; op1:f19; dest:f20; op1val:0x0; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f20, f19, 0, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19, +/* opcode: fcvt.d.h ; op1:f20; dest:f19; op1val:0x0; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f19, f20, 0, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18, +/* opcode: fcvt.d.h ; op1:f17; dest:f18; op1val:0x0; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f18, f17, 0, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17, +/* opcode: fcvt.d.h ; op1:f18; dest:f17; op1val:0x0; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f17, f18, 0, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16, +/* opcode: fcvt.d.h ; op1:f15; dest:f16; op1val:0x0; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15, +/* opcode: fcvt.d.h ; op1:f16; dest:f15; op1val:0x0; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f15, f16, 0, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14, +/* opcode: fcvt.d.h ; op1:f13; dest:f14; op1val:0x0; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f14, f13, 0, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13, +/* opcode: fcvt.d.h ; op1:f14; dest:f13; op1val:0x0; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f13, f14, 0, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12, +/* opcode: fcvt.d.h ; op1:f11; dest:f12; op1val:0x0; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f12, f11, 0, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11, +/* opcode: fcvt.d.h ; op1:f12; dest:f11; op1val:0x0; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10, +/* opcode: fcvt.d.h ; op1:f9; dest:f10; op1val:0x0; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f10, f9, 0, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9, +/* opcode: fcvt.d.h ; op1:f10; dest:f9; op1val:0x0; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f9, f10, 0, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8, +/* opcode: fcvt.d.h ; op1:f7; dest:f8; op1val:0x0; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f8, f7, 0, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7, +/* opcode: fcvt.d.h ; op1:f8; dest:f7; op1val:0x0; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f7, f8, 0, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6, +/* opcode: fcvt.d.h ; op1:f5; dest:f6; op1val:0x0; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5, +/* opcode: fcvt.d.h ; op1:f6; dest:f5; op1val:0x0; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f5, f6, 0, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4, +/* opcode: fcvt.d.h ; op1:f3; dest:f4; op1val:0x0; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f4, f3, 0, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3, +/* opcode: fcvt.d.h ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f3, f4, 0, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2, +/* opcode: fcvt.d.h ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f2, f1, 0, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1, +/* opcode: fcvt.d.h ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0, +/* opcode: fcvt.d.h ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f0, 0, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0, +/* opcode: fcvt.d.h ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f0, f31, 0, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(30716,16,FLEN) +NAN_BOXED(30717,16,FLEN) +NAN_BOXED(30718,16,FLEN) +NAN_BOXED(30719,16,FLEN) +NAN_BOXED(30720,16,FLEN) +NAN_BOXED(30721,16,FLEN) +NAN_BOXED(30722,16,FLEN) +NAN_BOXED(30723,16,FLEN) +NAN_BOXED(30724,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b24-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b24-01.S new file mode 100644 index 000000000..255b71662 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b24-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Fri Sep 13 19:12:48 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.d.h.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.d.h instruction of the RISC-V RV32FD_Zicsr_Zfh,RV64FD_Zicsr_Zfh extension for the fcvt.d.h_b24 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IFD_Zicsr_Zfh,RV64IFD_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.d.h_b24) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==f31, rd==f31,fs1 == 1 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f31; dest:f31; op1val:0xbc0a; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 != rd, rs1==f29, rd==f30,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f29; dest:f30; op1val:0x3c00; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f30, f29, 0, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f30, rd==f29,fs1 == 1 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f29; op1val:0xa11e; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f29, f30, 0, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 1 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f27; dest:f28; op1val:0xbb33; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f28, f27, 0, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f28; dest:f27; op1val:0xf0; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f27, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 0 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f25; dest:f26; op1val:0x2f0a; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f26; dest:f25; op1val:0x3c70; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f25, f26, 0, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f23; dest:f24; op1val:0xbc66; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f24, f23, 0, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 1 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f24; dest:f23; op1val:0xae66; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f23, f24, 0, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 0 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f21; dest:f22; op1val:0x3b1e; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f22, f21, 0, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f22; dest:f21; op1val:0x3beb; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 0 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f19; dest:f20; op1val:0x3b33; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f20, f19, 0, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f20; dest:f19; op1val:0xbc00; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f19, f20, 0, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 1 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f17; dest:f18; op1val:0xbc70; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f18, f17, 0, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f18; dest:f17; op1val:0x211e; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f17, f18, 0, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f15; dest:f16; op1val:0x2e66; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f16; dest:f15; op1val:0xaf0a; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f15, f16, 0, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f13; dest:f14; op1val:0x3c66; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f14, f13, 0, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f14; dest:f13; op1val:0xbbeb; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f13, f14, 0, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 0 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f11; dest:f12; op1val:0x3c0a; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f12, f11, 0, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 1 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f12; dest:f11; op1val:0xbb1e; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10, +/* opcode: fcvt.d.h ; op1:f9; dest:f10; op1val:0x0; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f10, f9, 0, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9, +/* opcode: fcvt.d.h ; op1:f10; dest:f9; op1val:0x0; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f9, f10, 0, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8, +/* opcode: fcvt.d.h ; op1:f7; dest:f8; op1val:0x0; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f8, f7, 0, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7, +/* opcode: fcvt.d.h ; op1:f8; dest:f7; op1val:0x0; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f7, f8, 0, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6, +/* opcode: fcvt.d.h ; op1:f5; dest:f6; op1val:0x0; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5, +/* opcode: fcvt.d.h ; op1:f6; dest:f5; op1val:0x0; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f5, f6, 0, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4, +/* opcode: fcvt.d.h ; op1:f3; dest:f4; op1val:0x0; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f4, f3, 0, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3, +/* opcode: fcvt.d.h ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f3, f4, 0, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2, +/* opcode: fcvt.d.h ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f2, f1, 0, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1, +/* opcode: fcvt.d.h ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0, +/* opcode: fcvt.d.h ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f0, 0, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0, +/* opcode: fcvt.d.h ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f0, f31, 0, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(48138,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(41246,16,FLEN) +NAN_BOXED(47923,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(12042,16,FLEN) +NAN_BOXED(15472,16,FLEN) +NAN_BOXED(48230,16,FLEN) +NAN_BOXED(44646,16,FLEN) +NAN_BOXED(15134,16,FLEN) +NAN_BOXED(15339,16,FLEN) +NAN_BOXED(15155,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48240,16,FLEN) +NAN_BOXED(8478,16,FLEN) +NAN_BOXED(11878,16,FLEN) +NAN_BOXED(44810,16,FLEN) +NAN_BOXED(15462,16,FLEN) +NAN_BOXED(48107,16,FLEN) +NAN_BOXED(15370,16,FLEN) +NAN_BOXED(47902,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b27-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b27-01.S new file mode 100644 index 000000000..46a91fefb --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b27-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Fri Sep 13 19:12:48 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.d.h.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.d.h instruction of the RISC-V RV32FD_Zicsr_Zfh,RV64FD_Zicsr_Zfh extension for the fcvt.d.h_b27 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IFD_Zicsr_Zfh,RV64IFD_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.d.h_b27) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f31; dest:f31; op1val:0x7c01; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 != rd, rs1==f29, rd==f30,fs1 == 1 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f29; dest:f30; op1val:0xfc01; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f30, f29, 0, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x1f and fm1 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f29; op1val:0x7d55; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f29, f30, 0, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f27; dest:f28; op1val:0xfd55; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f28, f27, 0, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f28; dest:f27; op1val:0x7e01; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f27, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 1 and fe1 == 0x1f and fm1 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f25; dest:f26; op1val:0xfe01; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x1f and fm1 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f26; dest:f25; op1val:0x7e55; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f25, f26, 0, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f23; dest:f24; op1val:0xfe55; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f24, f23, 0, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23, +/* opcode: fcvt.d.h ; op1:f24; dest:f23; op1val:0x0; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f23, f24, 0, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22, +/* opcode: fcvt.d.h ; op1:f21; dest:f22; op1val:0x0; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f22, f21, 0, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21, +/* opcode: fcvt.d.h ; op1:f22; dest:f21; op1val:0x0; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20, +/* opcode: fcvt.d.h ; op1:f19; dest:f20; op1val:0x0; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f20, f19, 0, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19, +/* opcode: fcvt.d.h ; op1:f20; dest:f19; op1val:0x0; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f19, f20, 0, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18, +/* opcode: fcvt.d.h ; op1:f17; dest:f18; op1val:0x0; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f18, f17, 0, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17, +/* opcode: fcvt.d.h ; op1:f18; dest:f17; op1val:0x0; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f17, f18, 0, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16, +/* opcode: fcvt.d.h ; op1:f15; dest:f16; op1val:0x0; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15, +/* opcode: fcvt.d.h ; op1:f16; dest:f15; op1val:0x0; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f15, f16, 0, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14, +/* opcode: fcvt.d.h ; op1:f13; dest:f14; op1val:0x0; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f14, f13, 0, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13, +/* opcode: fcvt.d.h ; op1:f14; dest:f13; op1val:0x0; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f13, f14, 0, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12, +/* opcode: fcvt.d.h ; op1:f11; dest:f12; op1val:0x0; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f12, f11, 0, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11, +/* opcode: fcvt.d.h ; op1:f12; dest:f11; op1val:0x0; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10, +/* opcode: fcvt.d.h ; op1:f9; dest:f10; op1val:0x0; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f10, f9, 0, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9, +/* opcode: fcvt.d.h ; op1:f10; dest:f9; op1val:0x0; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f9, f10, 0, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8, +/* opcode: fcvt.d.h ; op1:f7; dest:f8; op1val:0x0; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f8, f7, 0, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7, +/* opcode: fcvt.d.h ; op1:f8; dest:f7; op1val:0x0; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f7, f8, 0, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6, +/* opcode: fcvt.d.h ; op1:f5; dest:f6; op1val:0x0; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5, +/* opcode: fcvt.d.h ; op1:f6; dest:f5; op1val:0x0; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f5, f6, 0, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4, +/* opcode: fcvt.d.h ; op1:f3; dest:f4; op1val:0x0; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f4, f3, 0, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3, +/* opcode: fcvt.d.h ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f3, f4, 0, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2, +/* opcode: fcvt.d.h ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f2, f1, 0, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1, +/* opcode: fcvt.d.h ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0, +/* opcode: fcvt.d.h ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f0, 0, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0, +/* opcode: fcvt.d.h ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f0, f31, 0, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(64513,16,FLEN) +NAN_BOXED(32085,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(65025,16,FLEN) +NAN_BOXED(32341,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b28-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b28-01.S new file mode 100644 index 000000000..a59b503d8 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b28-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Fri Sep 13 19:12:48 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.d.h.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.d.h instruction of the RISC-V RV32FD_Zicsr_Zfh,RV64FD_Zicsr_Zfh extension for the fcvt.d.h_b28 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IFD_Zicsr_Zfh,RV64IFD_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.d.h_b28) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f31; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 != rd, rs1==f29, rd==f30,fs1 == 0 and fe1 == 0x0e and fm1 == 0x092 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f29; dest:f30; op1val:0x3892; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f30, f29, 0, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f29; op1val:0x3c00; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f29, f30, 0, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x0f and fm1 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f27; dest:f28; op1val:0x3d00; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f28, f27, 0, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x0f and fm1 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f28; dest:f27; op1val:0x3e00; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f27, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 0 and fe1 == 0x0f and fm1 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f25; dest:f26; op1val:0x3f00; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x10 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f26; dest:f25; op1val:0x4000; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f25, f26, 0, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 0 and fe1 == 0x10 and fm1 == 0x080 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f23; dest:f24; op1val:0x4080; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f24, f23, 0, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x10 and fm1 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f24; dest:f23; op1val:0x4100; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f23, f24, 0, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 0 and fe1 == 0x10 and fm1 == 0x180 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f21; dest:f22; op1val:0x4180; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f22, f21, 0, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x1c and fm1 == 0x2dc and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f22; dest:f21; op1val:0x72dc; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f19; dest:f20; op1val:0x77ff; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f20, f19, 0, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f20; dest:f19; op1val:0x7c00; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f19, f20, 0, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f17; dest:f18; op1val:0x7c01; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f18, f17, 0, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f18; dest:f17; op1val:0x7e01; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f17, f18, 0, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f15; dest:f16; op1val:0x8000; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 1 and fe1 == 0x0d and fm1 == 0x2c0 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f16; dest:f15; op1val:0xb6c0; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f15, f16, 0, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f13; dest:f14; op1val:0xbc00; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f14, f13, 0, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 1 and fe1 == 0x10 and fm1 == 0x180 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f14; dest:f13; op1val:0xc180; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f13, f14, 0, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 1 and fe1 == 0x10 and fm1 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f11; dest:f12; op1val:0xc100; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f12, f11, 0, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 1 and fe1 == 0x10 and fm1 == 0x080 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f12; dest:f11; op1val:0xc080; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10,fs1 == 1 and fe1 == 0x10 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f9; dest:f10; op1val:0xc000; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f10, f9, 0, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9,fs1 == 1 and fe1 == 0x0f and fm1 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f10; dest:f9; op1val:0xbf00; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f9, f10, 0, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8,fs1 == 1 and fe1 == 0x0f and fm1 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f7; dest:f8; op1val:0xbe00; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f8, f7, 0, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7,fs1 == 1 and fe1 == 0x0f and fm1 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f8; dest:f7; op1val:0xbd00; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f7, f8, 0, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6,fs1 == 1 and fe1 == 0x1d and fm1 == 0x259 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f5; dest:f6; op1val:0xf659; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5,fs1 == 1 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f6; dest:f5; op1val:0xf800; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f5, f6, 0, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4,fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f3; dest:f4; op1val:0xfc00; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f4, f3, 0, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3, +/* opcode: fcvt.d.h ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f3, f4, 0, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2, +/* opcode: fcvt.d.h ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f2, f1, 0, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1, +/* opcode: fcvt.d.h ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0, +/* opcode: fcvt.d.h ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f0, 0, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0, +/* opcode: fcvt.d.h ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f0, f31, 0, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,16,FLEN) +NAN_BOXED(14482,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15616,16,FLEN) +NAN_BOXED(15872,16,FLEN) +NAN_BOXED(16128,16,FLEN) +NAN_BOXED(16384,16,FLEN) +NAN_BOXED(16512,16,FLEN) +NAN_BOXED(16640,16,FLEN) +NAN_BOXED(16768,16,FLEN) +NAN_BOXED(29404,16,FLEN) +NAN_BOXED(30719,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(46784,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(49536,16,FLEN) +NAN_BOXED(49408,16,FLEN) +NAN_BOXED(49280,16,FLEN) +NAN_BOXED(49152,16,FLEN) +NAN_BOXED(48896,16,FLEN) +NAN_BOXED(48640,16,FLEN) +NAN_BOXED(48384,16,FLEN) +NAN_BOXED(63065,16,FLEN) +NAN_BOXED(63488,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b29-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b29-01.S new file mode 100644 index 000000000..ed6f6e448 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b29-01.S @@ -0,0 +1,729 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Fri Sep 13 19:12:48 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.d.h.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.d.h instruction of the RISC-V RV32FD_Zicsr_Zfh,RV64FD_Zicsr_Zfh extension for the fcvt.d.h_b29 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IFD_Zicsr_Zfh,RV64IFD_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.d.h_b29) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f31; dest:f31; op1val:0x3248; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 != rd, rs1==f29, rd==f30,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f29; dest:f30; op1val:0x3248; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f30, f29, 32, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f29; op1val:0x3248; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f29, f30, 64, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f27; dest:f28; op1val:0x3248; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f28, f27, 96, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f28; dest:f27; op1val:0x3248; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f27, f28, 128, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f25; dest:f26; op1val:0x3249; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f26; dest:f25; op1val:0x3249; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f25, f26, 32, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f23; dest:f24; op1val:0x3249; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f24, f23, 64, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f24; dest:f23; op1val:0x3249; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f23, f24, 96, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f21; dest:f22; op1val:0x3249; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f22, f21, 128, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f22; dest:f21; op1val:0x324a; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f19; dest:f20; op1val:0x324a; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f20, f19, 32, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f20; dest:f19; op1val:0x324a; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f19, f20, 64, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f17; dest:f18; op1val:0x324a; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f18, f17, 96, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f18; dest:f17; op1val:0x324a; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f17, f18, 128, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f15; dest:f16; op1val:0x324b; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f16; dest:f15; op1val:0x324b; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f15, f16, 32, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f13; dest:f14; op1val:0x324b; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f14, f13, 64, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f14; dest:f13; op1val:0x324b; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f13, f14, 96, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f11; dest:f12; op1val:0x324b; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f12, f11, 128, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f12; dest:f11; op1val:0x324c; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f9; dest:f10; op1val:0x324c; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f10, f9, 32, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f10; dest:f9; op1val:0x324c; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f9, f10, 64, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f7; dest:f8; op1val:0x324c; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f8, f7, 96, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f8; dest:f7; op1val:0x324c; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f7, f8, 128, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f5; dest:f6; op1val:0x324d; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f6; dest:f5; op1val:0x324d; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f5, f6, 32, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f3; dest:f4; op1val:0x324d; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f4, f3, 64, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f4; dest:f3; op1val:0x324d; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f3, f4, 96, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f1; dest:f2; op1val:0x324d; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f2, f1, 128, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f2; dest:f1; op1val:0x324e; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f0; dest:f31; op1val:0x324e; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f0, 32, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f31; dest:f0; op1val:0x324e; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f0, f31, 64, 0, x3, 32*FLEN/8, x4, x1, x2) + +inst_33: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0x324e; valaddr_reg:x3; +val_offset:33*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 96, 0, x3, 33*FLEN/8, x4, x1, x2) + +inst_34: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0x324e; valaddr_reg:x3; +val_offset:34*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 128, 0, x3, 34*FLEN/8, x4, x1, x2) + +inst_35: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0x324f; valaddr_reg:x3; +val_offset:35*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 0, 0, x3, 35*FLEN/8, x4, x1, x2) + +inst_36: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0x324f; valaddr_reg:x3; +val_offset:36*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 32, 0, x3, 36*FLEN/8, x4, x1, x2) + +inst_37: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0x324f; valaddr_reg:x3; +val_offset:37*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 64, 0, x3, 37*FLEN/8, x4, x1, x2) + +inst_38: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0x324f; valaddr_reg:x3; +val_offset:38*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 96, 0, x3, 38*FLEN/8, x4, x1, x2) + +inst_39: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0x324f; valaddr_reg:x3; +val_offset:39*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 128, 0, x3, 39*FLEN/8, x4, x1, x2) + +inst_40: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb248; valaddr_reg:x3; +val_offset:40*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 0, 0, x3, 40*FLEN/8, x4, x1, x2) + +inst_41: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb248; valaddr_reg:x3; +val_offset:41*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 32, 0, x3, 41*FLEN/8, x4, x1, x2) + +inst_42: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb248; valaddr_reg:x3; +val_offset:42*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 64, 0, x3, 42*FLEN/8, x4, x1, x2) + +inst_43: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb248; valaddr_reg:x3; +val_offset:43*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 96, 0, x3, 43*FLEN/8, x4, x1, x2) + +inst_44: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb248; valaddr_reg:x3; +val_offset:44*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 128, 0, x3, 44*FLEN/8, x4, x1, x2) + +inst_45: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb249; valaddr_reg:x3; +val_offset:45*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 0, 0, x3, 45*FLEN/8, x4, x1, x2) + +inst_46: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb249; valaddr_reg:x3; +val_offset:46*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 32, 0, x3, 46*FLEN/8, x4, x1, x2) + +inst_47: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb249; valaddr_reg:x3; +val_offset:47*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 64, 0, x3, 47*FLEN/8, x4, x1, x2) + +inst_48: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb249; valaddr_reg:x3; +val_offset:48*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 96, 0, x3, 48*FLEN/8, x4, x1, x2) + +inst_49: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb249; valaddr_reg:x3; +val_offset:49*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 128, 0, x3, 49*FLEN/8, x4, x1, x2) + +inst_50: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24a; valaddr_reg:x3; +val_offset:50*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 0, 0, x3, 50*FLEN/8, x4, x1, x2) + +inst_51: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24a; valaddr_reg:x3; +val_offset:51*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 32, 0, x3, 51*FLEN/8, x4, x1, x2) + +inst_52: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24a; valaddr_reg:x3; +val_offset:52*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 64, 0, x3, 52*FLEN/8, x4, x1, x2) + +inst_53: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24a; valaddr_reg:x3; +val_offset:53*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 96, 0, x3, 53*FLEN/8, x4, x1, x2) + +inst_54: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24a; valaddr_reg:x3; +val_offset:54*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 128, 0, x3, 54*FLEN/8, x4, x1, x2) + +inst_55: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24b; valaddr_reg:x3; +val_offset:55*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 0, 0, x3, 55*FLEN/8, x4, x1, x2) + +inst_56: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24b; valaddr_reg:x3; +val_offset:56*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 32, 0, x3, 56*FLEN/8, x4, x1, x2) + +inst_57: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24b; valaddr_reg:x3; +val_offset:57*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 64, 0, x3, 57*FLEN/8, x4, x1, x2) + +inst_58: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24b; valaddr_reg:x3; +val_offset:58*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 96, 0, x3, 58*FLEN/8, x4, x1, x2) + +inst_59: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24b; valaddr_reg:x3; +val_offset:59*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 128, 0, x3, 59*FLEN/8, x4, x1, x2) + +inst_60: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24c; valaddr_reg:x3; +val_offset:60*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 0, 0, x3, 60*FLEN/8, x4, x1, x2) + +inst_61: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24c; valaddr_reg:x3; +val_offset:61*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 32, 0, x3, 61*FLEN/8, x4, x1, x2) + +inst_62: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24c; valaddr_reg:x3; +val_offset:62*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 64, 0, x3, 62*FLEN/8, x4, x1, x2) + +inst_63: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24c; valaddr_reg:x3; +val_offset:63*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 96, 0, x3, 63*FLEN/8, x4, x1, x2) + +inst_64: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24c; valaddr_reg:x3; +val_offset:64*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 128, 0, x3, 64*FLEN/8, x4, x1, x2) + +inst_65: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24d; valaddr_reg:x3; +val_offset:65*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 0, 0, x3, 65*FLEN/8, x4, x1, x2) + +inst_66: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24d; valaddr_reg:x3; +val_offset:66*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 32, 0, x3, 66*FLEN/8, x4, x1, x2) + +inst_67: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24d; valaddr_reg:x3; +val_offset:67*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 64, 0, x3, 67*FLEN/8, x4, x1, x2) + +inst_68: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24d; valaddr_reg:x3; +val_offset:68*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 96, 0, x3, 68*FLEN/8, x4, x1, x2) + +inst_69: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24d; valaddr_reg:x3; +val_offset:69*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 128, 0, x3, 69*FLEN/8, x4, x1, x2) + +inst_70: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24e; valaddr_reg:x3; +val_offset:70*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 0, 0, x3, 70*FLEN/8, x4, x1, x2) + +inst_71: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24e; valaddr_reg:x3; +val_offset:71*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 32, 0, x3, 71*FLEN/8, x4, x1, x2) + +inst_72: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24e; valaddr_reg:x3; +val_offset:72*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 64, 0, x3, 72*FLEN/8, x4, x1, x2) + +inst_73: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24e; valaddr_reg:x3; +val_offset:73*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 96, 0, x3, 73*FLEN/8, x4, x1, x2) + +inst_74: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24e; valaddr_reg:x3; +val_offset:74*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 128, 0, x3, 74*FLEN/8, x4, x1, x2) + +inst_75: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24f; valaddr_reg:x3; +val_offset:75*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 0, 0, x3, 75*FLEN/8, x4, x1, x2) + +inst_76: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24f; valaddr_reg:x3; +val_offset:76*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 32, 0, x3, 76*FLEN/8, x4, x1, x2) + +inst_77: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24f; valaddr_reg:x3; +val_offset:77*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 64, 0, x3, 77*FLEN/8, x4, x1, x2) + +inst_78: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24f; valaddr_reg:x3; +val_offset:78*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 96, 0, x3, 78*FLEN/8, x4, x1, x2) + +inst_79: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24f; valaddr_reg:x3; +val_offset:79*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 128, 0, x3, 79*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(12872,16,FLEN) +NAN_BOXED(12872,16,FLEN) +NAN_BOXED(12872,16,FLEN) +NAN_BOXED(12872,16,FLEN) +NAN_BOXED(12872,16,FLEN) +NAN_BOXED(12873,16,FLEN) +NAN_BOXED(12873,16,FLEN) +NAN_BOXED(12873,16,FLEN) +NAN_BOXED(12873,16,FLEN) +NAN_BOXED(12873,16,FLEN) +NAN_BOXED(12874,16,FLEN) +NAN_BOXED(12874,16,FLEN) +NAN_BOXED(12874,16,FLEN) +NAN_BOXED(12874,16,FLEN) +NAN_BOXED(12874,16,FLEN) +NAN_BOXED(12875,16,FLEN) +NAN_BOXED(12875,16,FLEN) +NAN_BOXED(12875,16,FLEN) +NAN_BOXED(12875,16,FLEN) +NAN_BOXED(12875,16,FLEN) +NAN_BOXED(12876,16,FLEN) +NAN_BOXED(12876,16,FLEN) +NAN_BOXED(12876,16,FLEN) +NAN_BOXED(12876,16,FLEN) +NAN_BOXED(12876,16,FLEN) +NAN_BOXED(12877,16,FLEN) +NAN_BOXED(12877,16,FLEN) +NAN_BOXED(12877,16,FLEN) +NAN_BOXED(12877,16,FLEN) +NAN_BOXED(12877,16,FLEN) +NAN_BOXED(12878,16,FLEN) +NAN_BOXED(12878,16,FLEN) +NAN_BOXED(12878,16,FLEN) +NAN_BOXED(12878,16,FLEN) +NAN_BOXED(12878,16,FLEN) +NAN_BOXED(12879,16,FLEN) +NAN_BOXED(12879,16,FLEN) +NAN_BOXED(12879,16,FLEN) +NAN_BOXED(12879,16,FLEN) +NAN_BOXED(12879,16,FLEN) +NAN_BOXED(45640,16,FLEN) +NAN_BOXED(45640,16,FLEN) +NAN_BOXED(45640,16,FLEN) +NAN_BOXED(45640,16,FLEN) +NAN_BOXED(45640,16,FLEN) +NAN_BOXED(45641,16,FLEN) +NAN_BOXED(45641,16,FLEN) +NAN_BOXED(45641,16,FLEN) +NAN_BOXED(45641,16,FLEN) +NAN_BOXED(45641,16,FLEN) +NAN_BOXED(45642,16,FLEN) +NAN_BOXED(45642,16,FLEN) +NAN_BOXED(45642,16,FLEN) +NAN_BOXED(45642,16,FLEN) +NAN_BOXED(45642,16,FLEN) +NAN_BOXED(45643,16,FLEN) +NAN_BOXED(45643,16,FLEN) +NAN_BOXED(45643,16,FLEN) +NAN_BOXED(45643,16,FLEN) +NAN_BOXED(45643,16,FLEN) +NAN_BOXED(45644,16,FLEN) +NAN_BOXED(45644,16,FLEN) +NAN_BOXED(45644,16,FLEN) +NAN_BOXED(45644,16,FLEN) +NAN_BOXED(45644,16,FLEN) +NAN_BOXED(45645,16,FLEN) +NAN_BOXED(45645,16,FLEN) +NAN_BOXED(45645,16,FLEN) +NAN_BOXED(45645,16,FLEN) +NAN_BOXED(45645,16,FLEN) +NAN_BOXED(45646,16,FLEN) +NAN_BOXED(45646,16,FLEN) +NAN_BOXED(45646,16,FLEN) +NAN_BOXED(45646,16,FLEN) +NAN_BOXED(45646,16,FLEN) +NAN_BOXED(45647,16,FLEN) +NAN_BOXED(45647,16,FLEN) +NAN_BOXED(45647,16,FLEN) +NAN_BOXED(45647,16,FLEN) +NAN_BOXED(45647,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 160*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b1-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b1-01.S new file mode 100644 index 000000000..68dba6c97 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b1-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Thu Sep 19 19:19:34 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.d.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.h.d instruction of the RISC-V RV32FD_Zicsr_Zfh,RV64FD_Zicsr_Zfh extension for the fcvt.h.d_b1 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IFD_Zicsr_Zfh,RV64IFD_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.d_b1) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 != rd, rs1==f30, rd==f31,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f30; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 == rd, rs1==f29, rd==f29,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f29; dest:f29; op1val:0x80000000; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f29, f29, 0, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f31, rd==f30,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f31; dest:f30; op1val:0x1; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f30, f31, 0, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f27; dest:f28; op1val:0x80000001; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f28, f27, 0, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f28; dest:f27; op1val:0x2; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f27, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f25; dest:f26; op1val:0x80000002; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f26; dest:f25; op1val:0xfffffffffffff; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f25, f26, 0, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f23; dest:f24; op1val:0x100fffffffffffff; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f24, f23, 0, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f24; dest:f23; op1val:0x800000; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f23, f24, 0, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f21; dest:f22; op1val:0x80800000; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f22, f21, 0, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f22; dest:f21; op1val:0x800002; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f19; dest:f20; op1val:0x80800002; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f20, f19, 0, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f20; dest:f19; op1val:0x7fefffffffffffff; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f19, f20, 0, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f17; dest:f18; op1val:0xffefffffffffffff; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f18, f17, 0, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f18; dest:f17; op1val:0x3ff800000; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f17, f18, 0, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f15; dest:f16; op1val:0x7ff800000; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f16; dest:f15; op1val:0x7ff8000000000000; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f15, f16, 0, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f13; dest:f14; op1val:0xfff8000000000000; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f14, f13, 0, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f14; dest:f13; op1val:0x7ff8000000000001; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f13, f14, 0, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f11; dest:f12; op1val:0xfff8000000000001; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f12, f11, 0, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f12; dest:f11; op1val:0x3ff800001; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f9; dest:f10; op1val:0x7ff800001; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f10, f9, 0, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f10; dest:f9; op1val:0x1ff800000; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f9, f10, 0, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8,fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f7; dest:f8; op1val:0x3fc000000; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f8, f7, 0, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7, +/* opcode: fcvt.h.d ; op1:f8; dest:f7; op1val:0x0; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f7, f8, 0, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6, +/* opcode: fcvt.h.d ; op1:f5; dest:f6; op1val:0x0; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5, +/* opcode: fcvt.h.d ; op1:f6; dest:f5; op1val:0x0; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f5, f6, 0, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4, +/* opcode: fcvt.h.d ; op1:f3; dest:f4; op1val:0x0; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f4, f3, 0, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3, +/* opcode: fcvt.h.d ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f3, f4, 0, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2, +/* opcode: fcvt.h.d ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f2, f1, 0, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1, +/* opcode: fcvt.h.d ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0, +/* opcode: fcvt.h.d ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f31, f0, 0, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0, +/* opcode: fcvt.h.d ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f0, f31, 0, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +.dword 0; +.dword 2147483648; +.dword 1; +.dword 2147483649; +.dword 2; +.dword 2147483650; +.dword 4503599627370495; +.dword 1157425104234217471; +.dword 8388608; +.dword 2155872256; +.dword 8388610; +.dword 2155872258; +.dword 9218868437227405311; +.dword 18442240474082181119; +.dword 17171480576; +.dword 34351349760; +.dword 9221120237041090560; +.dword 18444492273895866368; +.dword 9221120237041090561; +.dword 18444492273895866369; +.dword 17171480577; +.dword 34351349761; +.dword 8581545984; +.dword 17112760320; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b22-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b22-01.S new file mode 100644 index 000000000..d93c18ef6 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b22-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Thu Sep 19 19:19:34 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.d.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.h.d instruction of the RISC-V RV32FD_Zicsr_Zfh,RV64FD_Zicsr_Zfh extension for the fcvt.h.d_b22 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IFD_Zicsr_Zfh,RV64IFD_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.d_b22) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 != rd, rs1==f30, rd==f31,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08577924770d3 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f30; dest:f31; op1val:0x3fc8577924770d3; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 == rd, rs1==f29, rd==f29,fs1 == 0 and fe1 == 0x3fd and fm1 == 0x93fdc7b89296c and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f29; dest:f29; op1val:0x3fd93fdc7b89296c; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f29, f29, 0, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f31, rd==f30,fs1 == 1 and fe1 == 0x3fe and fm1 == 0x766ba34c2da80 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f31; dest:f30; op1val:0x3ff766ba34c2da80; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f30, f31, 0, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x3ff and fm1 == 0xd2d6b7dc59a3a and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f27; dest:f28; op1val:0x3ffd2d6b7dc59a3a; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f28, f27, 0, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x400 and fm1 == 0xcf84ba749f9c5 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f28; dest:f27; op1val:0x400cf84ba749f9c5; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f27, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 0 and fe1 == 0x401 and fm1 == 0x854a908ceac39 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f25; dest:f26; op1val:0x401854a908ceac39; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 1 and fe1 == 0x0ff and fm1 == 0x137a953e8eb43 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f26; dest:f25; op1val:0x3ff37a953e8eb43; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f25, f26, 0, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xbedc2f3ebcf12 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f23; dest:f24; op1val:0x7febedc2f3ebcf12; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f24, f23, 0, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23, +/* opcode: fcvt.h.d ; op1:f24; dest:f23; op1val:0x0; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f23, f24, 0, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22, +/* opcode: fcvt.h.d ; op1:f21; dest:f22; op1val:0x0; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f22, f21, 0, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21, +/* opcode: fcvt.h.d ; op1:f22; dest:f21; op1val:0x0; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20, +/* opcode: fcvt.h.d ; op1:f19; dest:f20; op1val:0x0; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f20, f19, 0, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19, +/* opcode: fcvt.h.d ; op1:f20; dest:f19; op1val:0x0; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f19, f20, 0, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18, +/* opcode: fcvt.h.d ; op1:f17; dest:f18; op1val:0x0; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f18, f17, 0, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17, +/* opcode: fcvt.h.d ; op1:f18; dest:f17; op1val:0x0; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f17, f18, 0, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16, +/* opcode: fcvt.h.d ; op1:f15; dest:f16; op1val:0x0; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15, +/* opcode: fcvt.h.d ; op1:f16; dest:f15; op1val:0x0; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f15, f16, 0, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14, +/* opcode: fcvt.h.d ; op1:f13; dest:f14; op1val:0x0; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f14, f13, 0, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13, +/* opcode: fcvt.h.d ; op1:f14; dest:f13; op1val:0x0; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f13, f14, 0, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12, +/* opcode: fcvt.h.d ; op1:f11; dest:f12; op1val:0x0; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f12, f11, 0, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11, +/* opcode: fcvt.h.d ; op1:f12; dest:f11; op1val:0x0; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10, +/* opcode: fcvt.h.d ; op1:f9; dest:f10; op1val:0x0; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f10, f9, 0, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9, +/* opcode: fcvt.h.d ; op1:f10; dest:f9; op1val:0x0; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f9, f10, 0, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8, +/* opcode: fcvt.h.d ; op1:f7; dest:f8; op1val:0x0; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f8, f7, 0, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7, +/* opcode: fcvt.h.d ; op1:f8; dest:f7; op1val:0x0; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f7, f8, 0, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6, +/* opcode: fcvt.h.d ; op1:f5; dest:f6; op1val:0x0; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5, +/* opcode: fcvt.h.d ; op1:f6; dest:f5; op1val:0x0; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f5, f6, 0, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4, +/* opcode: fcvt.h.d ; op1:f3; dest:f4; op1val:0x0; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f4, f3, 0, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3, +/* opcode: fcvt.h.d ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f3, f4, 0, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2, +/* opcode: fcvt.h.d ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f2, f1, 0, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1, +/* opcode: fcvt.h.d ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0, +/* opcode: fcvt.h.d ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f31, f0, 0, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0, +/* opcode: fcvt.h.d ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f0, f31, 0, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +.dword 287251224846627027; +.dword 4600778710533613932; +.dword 4609265693572127360; +.dword 4610891533192108602; +.dword 4615336721960794565; +.dword 4618534502842412089; +.dword 288010101571775299; +.dword 9217722483915607826; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b23-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b23-01.S new file mode 100644 index 000000000..5fc00bbce --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b23-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Thu Sep 19 19:19:34 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.d.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.h.d instruction of the RISC-V RV32FD_Zicsr_Zfh,RV64FD_Zicsr_Zfh extension for the fcvt.h.d_b23 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IFD_Zicsr_Zfh,RV64IFD_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.d_b23) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 != rd, rs1==f30, rd==f31,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffc and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f30; dest:f31; op1val:0x43dffffffffffffc; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 == rd, rs1==f29, rd==f29,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffc and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f29; dest:f29; op1val:0x43dffffffffffffc; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f29, f29, 32, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f31, rd==f30,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffc and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f31; dest:f30; op1val:0x43dffffffffffffc; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f30, f31, 64, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffc and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f27; dest:f28; op1val:0x43dffffffffffffc; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f28, f27, 96, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffc and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f28; dest:f27; op1val:0x43dffffffffffffc; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f27, f28, 128, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffd and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f25; dest:f26; op1val:0x43dffffffffffffd; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffd and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f26; dest:f25; op1val:0x43dffffffffffffd; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f25, f26, 32, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffd and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f23; dest:f24; op1val:0x43dffffffffffffd; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f24, f23, 64, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffd and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f24; dest:f23; op1val:0x43dffffffffffffd; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f23, f24, 96, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffd and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f21; dest:f22; op1val:0x43dffffffffffffd; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f22, f21, 128, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffe and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f22; dest:f21; op1val:0x43dffffffffffffe; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffe and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f19; dest:f20; op1val:0x43dffffffffffffe; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f20, f19, 32, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffe and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f20; dest:f19; op1val:0x43dffffffffffffe; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f19, f20, 64, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffe and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f17; dest:f18; op1val:0x43dffffffffffffe; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f18, f17, 96, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffe and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f18; dest:f17; op1val:0x43dffffffffffffe; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f17, f18, 128, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 0 and fe1 == 0x43d and fm1 == 0xfffffffffffff and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f15; dest:f16; op1val:0x43dfffffffffffff; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 0 and fe1 == 0x43d and fm1 == 0xfffffffffffff and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f16; dest:f15; op1val:0x43dfffffffffffff; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f15, f16, 32, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 0 and fe1 == 0x43d and fm1 == 0xfffffffffffff and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f13; dest:f14; op1val:0x43dfffffffffffff; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f14, f13, 64, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 0 and fe1 == 0x43d and fm1 == 0xfffffffffffff and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f14; dest:f13; op1val:0x43dfffffffffffff; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f13, f14, 96, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 0 and fe1 == 0x43d and fm1 == 0xfffffffffffff and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f11; dest:f12; op1val:0x43dfffffffffffff; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f12, f11, 128, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f12; dest:f11; op1val:0x21f000000; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f9; dest:f10; op1val:0x21f000000; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f10, f9, 32, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f10; dest:f9; op1val:0x21f000000; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f9, f10, 64, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f7; dest:f8; op1val:0x21f000000; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f8, f7, 96, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f8; dest:f7; op1val:0x21f000000; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f7, f8, 128, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f5; dest:f6; op1val:0x21f000001; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000001 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f6; dest:f5; op1val:0x21f000001; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f5, f6, 32, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000001 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f3; dest:f4; op1val:0x21f000001; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f4, f3, 64, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000001 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f4; dest:f3; op1val:0x21f000001; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f3, f4, 96, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000001 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f1; dest:f2; op1val:0x21f000001; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f2, f1, 128, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000002 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f2; dest:f1; op1val:0x21f000002; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000002 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f0; dest:f31; op1val:0x21f000002; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f31, f0, 32, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000002 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f31; dest:f0; op1val:0x21f000002; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f0, f31, 64, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +.dword 4890909195324358652; +.dword 4890909195324358652; +.dword 4890909195324358652; +.dword 4890909195324358652; +.dword 4890909195324358652; +.dword 4890909195324358653; +.dword 4890909195324358653; +.dword 4890909195324358653; +.dword 4890909195324358653; +.dword 4890909195324358653; +.dword 4890909195324358654; +.dword 4890909195324358654; +.dword 4890909195324358654; +.dword 4890909195324358654; +.dword 4890909195324358654; +.dword 4890909195324358655; +.dword 4890909195324358655; +.dword 4890909195324358655; +.dword 4890909195324358655; +.dword 4890909195324358655; +.dword 9110028288; +.dword 9110028288; +.dword 9110028288; +.dword 9110028288; +.dword 9110028288; +.dword 9110028289; +.dword 9110028289; +.dword 9110028289; +.dword 9110028289; +.dword 9110028289; +.dword 9110028290; +.dword 9110028290; +.dword 9110028290; +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b24-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b24-01.S new file mode 100644 index 000000000..586d5b71a --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b24-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Thu Sep 19 19:19:34 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.d.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.h.d instruction of the RISC-V RV32FD_Zicsr_Zfh,RV64FD_Zicsr_Zfh extension for the fcvt.h.d_b24 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IFD_Zicsr_Zfh,RV64IFD_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.d_b24) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 != rd, rs1==f30, rd==f31,fs1 == 1 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f30; dest:f31; op1val:0x7fec7ae147ae147b; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 == rd, rs1==f29, rd==f29,fs1 == 1 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f29; dest:f29; op1val:0x7fec7ae147ae147b; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f29, f29, 32, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f31, rd==f30,fs1 == 1 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f31; dest:f30; op1val:0x7fec7ae147ae147b; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f30, f31, 64, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 1 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f27; dest:f28; op1val:0x7fec7ae147ae147b; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f28, f27, 96, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 1 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f28; dest:f27; op1val:0x7fec7ae147ae147b; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f27, f28, 128, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 1 and fe1 == 0x3fb and fm1 == 0x999999999999a and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f25; dest:f26; op1val:0x7fb999999999999a; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 1 and fe1 == 0x3fb and fm1 == 0x999999999999a and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f26; dest:f25; op1val:0x7fb999999999999a; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f25, f26, 32, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 1 and fe1 == 0x3fb and fm1 == 0x999999999999a and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f23; dest:f24; op1val:0x7fb999999999999a; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f24, f23, 64, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 1 and fe1 == 0x3fb and fm1 == 0x999999999999a and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f24; dest:f23; op1val:0x7fb999999999999a; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f23, f24, 96, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 1 and fe1 == 0x3fb and fm1 == 0x999999999999a and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f21; dest:f22; op1val:0x7fb999999999999a; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f22, f21, 128, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f22; dest:f21; op1val:0xffe8f5c28f5c29; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f19; dest:f20; op1val:0xffe8f5c28f5c29; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f20, f19, 32, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f20; dest:f19; op1val:0xffe8f5c28f5c29; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f19, f20, 64, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f17; dest:f18; op1val:0xffe8f5c28f5c29; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f18, f17, 96, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f18; dest:f17; op1val:0xffe8f5c28f5c29; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f17, f18, 128, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 0 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f15; dest:f16; op1val:0x1fc47ae147ae147b; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 0 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f16; dest:f15; op1val:0x1fc47ae147ae147b; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f15, f16, 32, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 0 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f13; dest:f14; op1val:0x1fc47ae147ae147b; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f14, f13, 64, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 0 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f14; dest:f13; op1val:0x1fc47ae147ae147b; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f13, f14, 96, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 0 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f11; dest:f12; op1val:0x1fc47ae147ae147b; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f12, f11, 128, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f12; dest:f11; op1val:0x0; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f9; dest:f10; op1val:0x0; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f10, f9, 32, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f10; dest:f9; op1val:0x0; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f9, f10, 64, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f7; dest:f8; op1val:0x0; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f8, f7, 96, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f8; dest:f7; op1val:0x0; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f7, f8, 128, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6,fs1 == 1 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f5; dest:f6; op1val:0x3ff800000; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5,fs1 == 1 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f6; dest:f5; op1val:0x3ff800000; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f5, f6, 32, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4,fs1 == 1 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f3; dest:f4; op1val:0x3ff800000; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f4, f3, 64, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3,fs1 == 1 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f4; dest:f3; op1val:0x3ff800000; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f3, f4, 96, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2,fs1 == 1 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f1; dest:f2; op1val:0x3ff800000; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f2, f1, 128, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f2; dest:f1; op1val:0x1ff800000; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f0; dest:f31; op1val:0x1ff800000; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f31, f0, 32, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f31; dest:f0; op1val:0x1ff800000; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f0, f31, 64, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +.dword 9217877645309383803; +.dword 9217877645309383803; +.dword 9217877645309383803; +.dword 9217877645309383803; +.dword 9217877645309383803; +.dword 9203556198494345626; +.dword 9203556198494345626; +.dword 9203556198494345626; +.dword 9203556198494345626; +.dword 9203556198494345626; +.dword 72032261290023977; +.dword 72032261290023977; +.dword 72032261290023977; +.dword 72032261290023977; +.dword 72032261290023977; +.dword 2289089618599875707; +.dword 2289089618599875707; +.dword 2289089618599875707; +.dword 2289089618599875707; +.dword 2289089618599875707; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 17171480576; +.dword 17171480576; +.dword 17171480576; +.dword 17171480576; +.dword 17171480576; +.dword 8581545984; +.dword 8581545984; +.dword 8581545984; +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b27-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b27-01.S new file mode 100644 index 000000000..6fb9ee31c --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b27-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Thu Sep 19 19:19:34 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.d.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.h.d instruction of the RISC-V RV32FD_Zicsr_Zfh,RV64FD_Zicsr_Zfh extension for the fcvt.h.d_b27 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IFD_Zicsr_Zfh,RV64IFD_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.d_b27) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 != rd, rs1==f30, rd==f31,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f30; dest:f31; op1val:0x3ff800001; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 == rd, rs1==f29, rd==f29,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f29; dest:f29; op1val:0x7ff800001; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f29, f29, 0, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f31, rd==f30,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x4aaaaaaaaaaaa and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f31; dest:f30; op1val:0x3ffcaaaaaaaaaaaa; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f30, f31, 0, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x4aaaaaaaaaaaa and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f27; dest:f28; op1val:0x7ffcaaaaaaaaaaaa; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f28, f27, 0, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f28; dest:f27; op1val:0x7ff8000000000001; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f27, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f25; dest:f26; op1val:0xfff8000000000001; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x7ff and fm1 == 0xc000000000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f26; dest:f25; op1val:0x7ffc000000000001; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f25, f26, 0, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 1 and fe1 == 0x7ff and fm1 == 0xc000000000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f23; dest:f24; op1val:0xfffc000000000001; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f24, f23, 0, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23, +/* opcode: fcvt.h.d ; op1:f24; dest:f23; op1val:0x0; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f23, f24, 0, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22, +/* opcode: fcvt.h.d ; op1:f21; dest:f22; op1val:0x0; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f22, f21, 0, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21, +/* opcode: fcvt.h.d ; op1:f22; dest:f21; op1val:0x0; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20, +/* opcode: fcvt.h.d ; op1:f19; dest:f20; op1val:0x0; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f20, f19, 0, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19, +/* opcode: fcvt.h.d ; op1:f20; dest:f19; op1val:0x0; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f19, f20, 0, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18, +/* opcode: fcvt.h.d ; op1:f17; dest:f18; op1val:0x0; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f18, f17, 0, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17, +/* opcode: fcvt.h.d ; op1:f18; dest:f17; op1val:0x0; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f17, f18, 0, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16, +/* opcode: fcvt.h.d ; op1:f15; dest:f16; op1val:0x0; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15, +/* opcode: fcvt.h.d ; op1:f16; dest:f15; op1val:0x0; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f15, f16, 0, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14, +/* opcode: fcvt.h.d ; op1:f13; dest:f14; op1val:0x0; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f14, f13, 0, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13, +/* opcode: fcvt.h.d ; op1:f14; dest:f13; op1val:0x0; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f13, f14, 0, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12, +/* opcode: fcvt.h.d ; op1:f11; dest:f12; op1val:0x0; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f12, f11, 0, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11, +/* opcode: fcvt.h.d ; op1:f12; dest:f11; op1val:0x0; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10, +/* opcode: fcvt.h.d ; op1:f9; dest:f10; op1val:0x0; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f10, f9, 0, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9, +/* opcode: fcvt.h.d ; op1:f10; dest:f9; op1val:0x0; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f9, f10, 0, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8, +/* opcode: fcvt.h.d ; op1:f7; dest:f8; op1val:0x0; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f8, f7, 0, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7, +/* opcode: fcvt.h.d ; op1:f8; dest:f7; op1val:0x0; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f7, f8, 0, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6, +/* opcode: fcvt.h.d ; op1:f5; dest:f6; op1val:0x0; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5, +/* opcode: fcvt.h.d ; op1:f6; dest:f5; op1val:0x0; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f5, f6, 0, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4, +/* opcode: fcvt.h.d ; op1:f3; dest:f4; op1val:0x0; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f4, f3, 0, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3, +/* opcode: fcvt.h.d ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f3, f4, 0, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2, +/* opcode: fcvt.h.d ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f2, f1, 0, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1, +/* opcode: fcvt.h.d ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0, +/* opcode: fcvt.h.d ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f31, f0, 0, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0, +/* opcode: fcvt.h.d ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f0, f31, 0, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +.dword 17171480577; +.dword 34351349761; +.dword 4610747768505019050; +.dword 9222433786932406954; +.dword 9221120237041090561; +.dword 18444492273895866369; +.dword 9222246136947933185; +.dword 18445618173802708993; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b28-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b28-01.S new file mode 100644 index 000000000..b79caf4c1 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b28-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Thu Sep 19 19:19:34 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.d.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.h.d instruction of the RISC-V RV32FD_Zicsr_Zfh,RV64FD_Zicsr_Zfh extension for the fcvt.h.d_b28 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IFD_Zicsr_Zfh,RV64IFD_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.d_b28) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 != rd, rs1==f30, rd==f31,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f30; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 == rd, rs1==f29, rd==f29,fs1 == 0 and fe1 == 0x3fe and fm1 == 0x248ee18215dfa and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f29; dest:f29; op1val:0xffa48ee18215dfa; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f29, f29, 0, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f31, rd==f30,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f31; dest:f30; op1val:0x1ff800000; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f30, f31, 0, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x4000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f27; dest:f28; op1val:0x1ffc000000000000; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f28, f27, 0, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x8000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f28; dest:f27; op1val:0x3ff8000000000000; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f27, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 0 and fe1 == 0x3ff and fm1 == 0xc000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f25; dest:f26; op1val:0x3ffc000000000000; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x400 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f26; dest:f25; op1val:0x200000000; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f25, f26, 0, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 0 and fe1 == 0x400 and fm1 == 0x2000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f23; dest:f24; op1val:0x1002000000000000; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f24, f23, 0, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x400 and fm1 == 0x4000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f24; dest:f23; op1val:0x2004000000000000; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f23, f24, 0, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 0 and fe1 == 0x400 and fm1 == 0x6000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f21; dest:f22; op1val:0x2006000000000000; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f22, f21, 0, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x43c and fm1 == 0xb72eb13dc494a and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f22; dest:f21; op1val:0x43cb72eb13dc494a; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f19; dest:f20; op1val:0x21f000000; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f20, f19, 0, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f20; dest:f19; op1val:0x3ff800000; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f19, f20, 0, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f17; dest:f18; op1val:0x3ff800001; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f18, f17, 0, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f18; dest:f17; op1val:0x7ff8000000000001; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f17, f18, 0, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f15; dest:f16; op1val:0x80000000; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 1 and fe1 == 0x3fd and fm1 == 0xb008d57e19f88 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f16; dest:f15; op1val:0x7fdb008d57e19f88; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f15, f16, 0, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f13; dest:f14; op1val:0x3fc000000; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f14, f13, 0, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 1 and fe1 == 0x400 and fm1 == 0x6000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f14; dest:f13; op1val:0x6006000000000000; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f13, f14, 0, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 1 and fe1 == 0x400 and fm1 == 0x4000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f11; dest:f12; op1val:0x6004000000000000; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f12, f11, 0, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 1 and fe1 == 0x400 and fm1 == 0x2000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f12; dest:f11; op1val:0x3002000000000000; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10,fs1 == 1 and fe1 == 0x400 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f9; dest:f10; op1val:0x600000000; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f10, f9, 0, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9,fs1 == 1 and fe1 == 0x3ff and fm1 == 0xc000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f10; dest:f9; op1val:0x7ffc000000000000; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f9, f10, 0, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8,fs1 == 1 and fe1 == 0x3ff and fm1 == 0x8000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f7; dest:f8; op1val:0x7ff8000000000000; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f8, f7, 0, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7,fs1 == 1 and fe1 == 0x3ff and fm1 == 0x4000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f8; dest:f7; op1val:0x3ffc000000000000; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f7, f8, 0, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6,fs1 == 1 and fe1 == 0x43d and fm1 == 0x967a4ae26514c and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f5; dest:f6; op1val:0xc3d967a4ae26514c; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5,fs1 == 1 and fe1 == 0x43e and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f6; dest:f5; op1val:0x61f000000; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f5, f6, 0, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f3; dest:f4; op1val:0x7ff800000; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f4, f3, 0, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3, +/* opcode: fcvt.h.d ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f3, f4, 0, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2, +/* opcode: fcvt.h.d ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f2, f1, 0, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1, +/* opcode: fcvt.h.d ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0, +/* opcode: fcvt.h.d ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f31, f0, 0, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0, +/* opcode: fcvt.h.d ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f0, f31, 0, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +.dword 0; +.dword 1151312842190839290; +.dword 8581545984; +.dword 2304717109306851328; +.dword 4609434218613702656; +.dword 4610560118520545280; +.dword 8589934592; +.dword 1153484454560268288; +.dword 2306968909120536576; +.dword 2307531859073957888; +.dword 4885124574789519690; +.dword 9110028288; +.dword 17171480576; +.dword 17171480577; +.dword 9221120237041090561; +.dword 2147483648; +.dword 9212958069781274504; +.dword 17112760320; +.dword 6919217877501345792; +.dword 6918654927547924480; +.dword 3459327463773962240; +.dword 25769803776; +.dword 9222246136947933184; +.dword 9221120237041090560; +.dword 4610560118520545280; +.dword 14112424864336204108; +.dword 26289897472; +.dword 34351349760; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b29-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b29-01.S new file mode 100644 index 000000000..9063584b5 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b29-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Thu Sep 19 19:19:34 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.d.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.h.d instruction of the RISC-V RV32FD_Zicsr_Zfh,RV64FD_Zicsr_Zfh extension for the fcvt.h.d_b29 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IFD_Zicsr_Zfh,RV64IFD_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.d_b29) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 != rd, rs1==f30, rd==f31,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f30; dest:f31; op1val:0x3fc8574923b8698; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 == rd, rs1==f29, rd==f29,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f29; dest:f29; op1val:0x3fc8574923b8698; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f29, f29, 32, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f31, rd==f30,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f31; dest:f30; op1val:0x3fc8574923b8698; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f30, f31, 64, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f27; dest:f28; op1val:0x3fc8574923b8698; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f28, f27, 96, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f28; dest:f27; op1val:0x3fc8574923b8698; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f27, f28, 128, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f25; dest:f26; op1val:0x3fc8574923b8699; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f26; dest:f25; op1val:0x3fc8574923b8699; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f25, f26, 32, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f23; dest:f24; op1val:0x3fc8574923b8699; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f24, f23, 64, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f24; dest:f23; op1val:0x3fc8574923b8699; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f23, f24, 96, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f21; dest:f22; op1val:0x3fc8574923b8699; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f22, f21, 128, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869a and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f22; dest:f21; op1val:0x3fc8574923b869a; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869a and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f19; dest:f20; op1val:0x3fc8574923b869a; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f20, f19, 32, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869a and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f20; dest:f19; op1val:0x3fc8574923b869a; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f19, f20, 64, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869a and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f17; dest:f18; op1val:0x3fc8574923b869a; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f18, f17, 96, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869a and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f18; dest:f17; op1val:0x3fc8574923b869a; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f17, f18, 128, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869b and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f15; dest:f16; op1val:0x3fc8574923b869b; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869b and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f16; dest:f15; op1val:0x3fc8574923b869b; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f15, f16, 32, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869b and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f13; dest:f14; op1val:0x3fc8574923b869b; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f14, f13, 64, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869b and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f14; dest:f13; op1val:0x3fc8574923b869b; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f13, f14, 96, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869b and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f11; dest:f12; op1val:0x3fc8574923b869b; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f12, f11, 128, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869c and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f12; dest:f11; op1val:0x3fc8574923b869c; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869c and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f9; dest:f10; op1val:0x3fc8574923b869c; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f10, f9, 32, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869c and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f10; dest:f9; op1val:0x3fc8574923b869c; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f9, f10, 64, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869c and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f7; dest:f8; op1val:0x3fc8574923b869c; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f8, f7, 96, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869c and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f8; dest:f7; op1val:0x3fc8574923b869c; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f7, f8, 128, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869d and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f5; dest:f6; op1val:0x3fc8574923b869d; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869d and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f6; dest:f5; op1val:0x3fc8574923b869d; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f5, f6, 32, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869d and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f3; dest:f4; op1val:0x3fc8574923b869d; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f4, f3, 64, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869d and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f4; dest:f3; op1val:0x3fc8574923b869d; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f3, f4, 96, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869d and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f1; dest:f2; op1val:0x3fc8574923b869d; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f2, f1, 128, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869e and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f2; dest:f1; op1val:0x3fc8574923b869e; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869e and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f0; dest:f31; op1val:0x3fc8574923b869e; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f31, f0, 32, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869e and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f31; dest:f0; op1val:0x3fc8574923b869e; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f0, f31, 64, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +.dword 287251211960944280; +.dword 287251211960944280; +.dword 287251211960944280; +.dword 287251211960944280; +.dword 287251211960944280; +.dword 287251211960944281; +.dword 287251211960944281; +.dword 287251211960944281; +.dword 287251211960944281; +.dword 287251211960944281; +.dword 287251211960944282; +.dword 287251211960944282; +.dword 287251211960944282; +.dword 287251211960944282; +.dword 287251211960944282; +.dword 287251211960944283; +.dword 287251211960944283; +.dword 287251211960944283; +.dword 287251211960944283; +.dword 287251211960944283; +.dword 287251211960944284; +.dword 287251211960944284; +.dword 287251211960944284; +.dword 287251211960944284; +.dword 287251211960944284; +.dword 287251211960944285; +.dword 287251211960944285; +.dword 287251211960944285; +.dword 287251211960944285; +.dword 287251211960944285; +.dword 287251211960944286; +.dword 287251211960944286; +.dword 287251211960944286; +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b1-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b1-01.S new file mode 100644 index 000000000..49363d961 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b1-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Sat Sep 14 02:42:23 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.s.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.h.s instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.h.s_b1 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.s_b1) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f31; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 != rd, rs1==f29, rd==f30,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f29; dest:f30; op1val:0x80000000; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f30, f29, 0, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f29; op1val:0x1; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f29, f30, 0, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f27; dest:f28; op1val:0x80000001; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f28, f27, 0, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f28; dest:f27; op1val:0x2; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f27, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f25; dest:f26; op1val:0x807ffffe; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f26; dest:f25; op1val:0x7fffff; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f25, f26, 0, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f23; dest:f24; op1val:0x807fffff; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f24, f23, 0, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f24; dest:f23; op1val:0x800000; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f23, f24, 0, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f21; dest:f22; op1val:0x80800000; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f22, f21, 0, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f22; dest:f21; op1val:0x800001; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f19; dest:f20; op1val:0x80855555; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f20, f19, 0, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f20; dest:f19; op1val:0x7f7fffff; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f19, f20, 0, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f17; dest:f18; op1val:0xff7fffff; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f18, f17, 0, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f18; dest:f17; op1val:0x7f800000; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f17, f18, 0, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f15; dest:f16; op1val:0xff800000; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f16; dest:f15; op1val:0x7fc00000; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f15, f16, 0, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f13; dest:f14; op1val:0xffc00000; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f14, f13, 0, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f14; dest:f13; op1val:0x7fc00001; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f13, f14, 0, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f11; dest:f12; op1val:0xffc55555; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f12, f11, 0, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f12; dest:f11; op1val:0x7f800001; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10,fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f9; dest:f10; op1val:0xffaaaaaa; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f10, f9, 0, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9,fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f10; dest:f9; op1val:0x3f800000; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f9, f10, 0, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8,fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f7; dest:f8; op1val:0xbf800000; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f8, f7, 0, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7, +/* opcode: fcvt.h.s ; op1:f8; dest:f7; op1val:0x0; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f7, f8, 0, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6, +/* opcode: fcvt.h.s ; op1:f5; dest:f6; op1val:0x0; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5, +/* opcode: fcvt.h.s ; op1:f6; dest:f5; op1val:0x0; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f5, f6, 0, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4, +/* opcode: fcvt.h.s ; op1:f3; dest:f4; op1val:0x0; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f4, f3, 0, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3, +/* opcode: fcvt.h.s ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f3, f4, 0, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2, +/* opcode: fcvt.h.s ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f2, f1, 0, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1, +/* opcode: fcvt.h.s ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0, +/* opcode: fcvt.h.s ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f0, 0, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0, +/* opcode: fcvt.h.s ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f0, f31, 0, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(2147483648,32,FLEN) +NAN_BOXED(1,32,FLEN) +NAN_BOXED(2147483649,32,FLEN) +NAN_BOXED(2,32,FLEN) +NAN_BOXED(2155872254,32,FLEN) +NAN_BOXED(8388607,32,FLEN) +NAN_BOXED(2155872255,32,FLEN) +NAN_BOXED(8388608,32,FLEN) +NAN_BOXED(2155872256,32,FLEN) +NAN_BOXED(8388609,32,FLEN) +NAN_BOXED(2156221781,32,FLEN) +NAN_BOXED(2139095039,32,FLEN) +NAN_BOXED(4286578687,32,FLEN) +NAN_BOXED(2139095040,32,FLEN) +NAN_BOXED(4286578688,32,FLEN) +NAN_BOXED(2143289344,32,FLEN) +NAN_BOXED(4290772992,32,FLEN) +NAN_BOXED(2143289345,32,FLEN) +NAN_BOXED(4291122517,32,FLEN) +NAN_BOXED(2139095041,32,FLEN) +NAN_BOXED(4289374890,32,FLEN) +NAN_BOXED(1065353216,32,FLEN) +NAN_BOXED(3212836864,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b22-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b22-01.S new file mode 100644 index 000000000..6d37c239d --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b22-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Sat Sep 14 02:42:23 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.s.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.h.s instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.h.s_b22 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.s_b22) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923b8 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f31; dest:f31; op1val:0x3e4923b8; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 != rd, rs1==f29, rd==f30,fs1 == 0 and fe1 == 0x7d and fm1 == 0x36e5d6 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f29; dest:f30; op1val:0x3eb6e5d6; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f30, f29, 0, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x7e and fm1 == 0x49fee5 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f29; op1val:0x3f49fee5; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f29, f30, 0, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x7f and fm1 == 0x1a616d and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f27; dest:f28; op1val:0x3f9a616d; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f28, f27, 0, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x80 and fm1 == 0x681ae9 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f28; dest:f27; op1val:0x40681ae9; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f27, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 0 and fe1 == 0x81 and fm1 == 0x696b5c and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f25; dest:f26; op1val:0x40e96b5c; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x67 and fm1 == 0x53a4fc and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f26; dest:f25; op1val:0x33d3a4fc; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f25, f26, 0, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 0 and fe1 == 0xc4 and fm1 == 0x046756 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f23; dest:f24; op1val:0x62046756; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f24, f23, 0, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23, +/* opcode: fcvt.h.s ; op1:f24; dest:f23; op1val:0x0; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f23, f24, 0, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22, +/* opcode: fcvt.h.s ; op1:f21; dest:f22; op1val:0x0; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f22, f21, 0, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21, +/* opcode: fcvt.h.s ; op1:f22; dest:f21; op1val:0x0; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20, +/* opcode: fcvt.h.s ; op1:f19; dest:f20; op1val:0x0; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f20, f19, 0, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19, +/* opcode: fcvt.h.s ; op1:f20; dest:f19; op1val:0x0; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f19, f20, 0, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18, +/* opcode: fcvt.h.s ; op1:f17; dest:f18; op1val:0x0; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f18, f17, 0, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17, +/* opcode: fcvt.h.s ; op1:f18; dest:f17; op1val:0x0; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f17, f18, 0, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16, +/* opcode: fcvt.h.s ; op1:f15; dest:f16; op1val:0x0; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15, +/* opcode: fcvt.h.s ; op1:f16; dest:f15; op1val:0x0; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f15, f16, 0, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14, +/* opcode: fcvt.h.s ; op1:f13; dest:f14; op1val:0x0; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f14, f13, 0, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13, +/* opcode: fcvt.h.s ; op1:f14; dest:f13; op1val:0x0; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f13, f14, 0, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12, +/* opcode: fcvt.h.s ; op1:f11; dest:f12; op1val:0x0; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f12, f11, 0, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11, +/* opcode: fcvt.h.s ; op1:f12; dest:f11; op1val:0x0; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10, +/* opcode: fcvt.h.s ; op1:f9; dest:f10; op1val:0x0; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f10, f9, 0, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9, +/* opcode: fcvt.h.s ; op1:f10; dest:f9; op1val:0x0; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f9, f10, 0, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8, +/* opcode: fcvt.h.s ; op1:f7; dest:f8; op1val:0x0; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f8, f7, 0, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7, +/* opcode: fcvt.h.s ; op1:f8; dest:f7; op1val:0x0; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f7, f8, 0, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6, +/* opcode: fcvt.h.s ; op1:f5; dest:f6; op1val:0x0; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5, +/* opcode: fcvt.h.s ; op1:f6; dest:f5; op1val:0x0; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f5, f6, 0, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4, +/* opcode: fcvt.h.s ; op1:f3; dest:f4; op1val:0x0; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f4, f3, 0, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3, +/* opcode: fcvt.h.s ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f3, f4, 0, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2, +/* opcode: fcvt.h.s ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f2, f1, 0, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1, +/* opcode: fcvt.h.s ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0, +/* opcode: fcvt.h.s ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f0, 0, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0, +/* opcode: fcvt.h.s ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f0, f31, 0, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(1044980664,32,FLEN) +NAN_BOXED(1052173782,32,FLEN) +NAN_BOXED(1061813989,32,FLEN) +NAN_BOXED(1067082093,32,FLEN) +NAN_BOXED(1080564457,32,FLEN) +NAN_BOXED(1089039196,32,FLEN) +NAN_BOXED(869508348,32,FLEN) +NAN_BOXED(1644455766,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b23-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b23-01.S new file mode 100644 index 000000000..f68582b2a --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b23-01.S @@ -0,0 +1,449 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Sat Sep 14 02:42:23 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.s.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.h.s instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.h.s_b23 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.s_b23) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffc and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f31; dest:f31; op1val:0x4efffffc; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 != rd, rs1==f29, rd==f30,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffc and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f29; dest:f30; op1val:0x4efffffc; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f30, f29, 32, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffc and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f29; op1val:0x4efffffc; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f29, f30, 64, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffc and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f27; dest:f28; op1val:0x4efffffc; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f28, f27, 96, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffc and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f28; dest:f27; op1val:0x4efffffc; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f27, f28, 128, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffd and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f25; dest:f26; op1val:0x4efffffd; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffd and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f26; dest:f25; op1val:0x4efffffd; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f25, f26, 32, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffd and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f23; dest:f24; op1val:0x4efffffd; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f24, f23, 64, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffd and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f24; dest:f23; op1val:0x4efffffd; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f23, f24, 96, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffd and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f21; dest:f22; op1val:0x4efffffd; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f22, f21, 128, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffe and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f22; dest:f21; op1val:0x4efffffe; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffe and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f19; dest:f20; op1val:0x4efffffe; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f20, f19, 32, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffe and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f20; dest:f19; op1val:0x4efffffe; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f19, f20, 64, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffe and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f17; dest:f18; op1val:0x4efffffe; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f18, f17, 96, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffe and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f18; dest:f17; op1val:0x4efffffe; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f17, f18, 128, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7fffff and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f15; dest:f16; op1val:0x4effffff; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7fffff and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f16; dest:f15; op1val:0x4effffff; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f15, f16, 32, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7fffff and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f13; dest:f14; op1val:0x4effffff; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f14, f13, 64, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7fffff and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f14; dest:f13; op1val:0x4effffff; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f13, f14, 96, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7fffff and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f11; dest:f12; op1val:0x4effffff; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f12, f11, 128, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f12; dest:f11; op1val:0x4f000000; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000000 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f9; dest:f10; op1val:0x4f000000; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f10, f9, 32, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000000 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f10; dest:f9; op1val:0x4f000000; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f9, f10, 64, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000000 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f7; dest:f8; op1val:0x4f000000; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f8, f7, 96, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000000 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f8; dest:f7; op1val:0x4f000000; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f7, f8, 128, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f5; dest:f6; op1val:0x4f000001; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000001 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f6; dest:f5; op1val:0x4f000001; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f5, f6, 32, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000001 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f3; dest:f4; op1val:0x4f000001; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f4, f3, 64, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000001 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f4; dest:f3; op1val:0x4f000001; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f3, f4, 96, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000001 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f1; dest:f2; op1val:0x4f000001; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f2, f1, 128, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000002 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f2; dest:f1; op1val:0x4f000002; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000002 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f0; dest:f31; op1val:0x4f000002; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f0, 32, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000002 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f31; dest:f0; op1val:0x4f000002; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f0, f31, 64, 0, x3, 32*FLEN/8, x4, x1, x2) + +inst_33: +// fs1 == 0 and fe1 == 0x9e and fm1 == 0x000002 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x4f000002; valaddr_reg:x3; +val_offset:33*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 33*FLEN/8, x4, x1, x2) + +inst_34: +// fs1 == 0 and fe1 == 0x9e and fm1 == 0x000002 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x4f000002; valaddr_reg:x3; +val_offset:34*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 34*FLEN/8, x4, x1, x2) + +inst_35: +// fs1 == 0 and fe1 == 0x9e and fm1 == 0x000003 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x4f000003; valaddr_reg:x3; +val_offset:35*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 35*FLEN/8, x4, x1, x2) + +inst_36: +// fs1 == 0 and fe1 == 0x9e and fm1 == 0x000003 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x4f000003; valaddr_reg:x3; +val_offset:36*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 36*FLEN/8, x4, x1, x2) + +inst_37: +// fs1 == 0 and fe1 == 0x9e and fm1 == 0x000003 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x4f000003; valaddr_reg:x3; +val_offset:37*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 37*FLEN/8, x4, x1, x2) + +inst_38: +// fs1 == 0 and fe1 == 0x9e and fm1 == 0x000003 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x4f000003; valaddr_reg:x3; +val_offset:38*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 38*FLEN/8, x4, x1, x2) + +inst_39: +// fs1 == 0 and fe1 == 0x9e and fm1 == 0x000003 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x4f000003; valaddr_reg:x3; +val_offset:39*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 39*FLEN/8, x4, x1, x2) + +inst_40: +// fs1 == 0 and fe1 == 0x9e and fm1 == 0x000004 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x4f000004; valaddr_reg:x3; +val_offset:40*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 40*FLEN/8, x4, x1, x2) + +inst_41: +// fs1 == 0 and fe1 == 0x9e and fm1 == 0x000004 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x4f000004; valaddr_reg:x3; +val_offset:41*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 41*FLEN/8, x4, x1, x2) + +inst_42: +// fs1 == 0 and fe1 == 0x9e and fm1 == 0x000004 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x4f000004; valaddr_reg:x3; +val_offset:42*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 42*FLEN/8, x4, x1, x2) + +inst_43: +// fs1 == 0 and fe1 == 0x9e and fm1 == 0x000004 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x4f000004; valaddr_reg:x3; +val_offset:43*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 43*FLEN/8, x4, x1, x2) + +inst_44: +// fs1 == 0 and fe1 == 0x9e and fm1 == 0x000004 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x4f000004; valaddr_reg:x3; +val_offset:44*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 44*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(1325400060,32,FLEN) +NAN_BOXED(1325400060,32,FLEN) +NAN_BOXED(1325400060,32,FLEN) +NAN_BOXED(1325400060,32,FLEN) +NAN_BOXED(1325400060,32,FLEN) +NAN_BOXED(1325400061,32,FLEN) +NAN_BOXED(1325400061,32,FLEN) +NAN_BOXED(1325400061,32,FLEN) +NAN_BOXED(1325400061,32,FLEN) +NAN_BOXED(1325400061,32,FLEN) +NAN_BOXED(1325400062,32,FLEN) +NAN_BOXED(1325400062,32,FLEN) +NAN_BOXED(1325400062,32,FLEN) +NAN_BOXED(1325400062,32,FLEN) +NAN_BOXED(1325400062,32,FLEN) +NAN_BOXED(1325400063,32,FLEN) +NAN_BOXED(1325400063,32,FLEN) +NAN_BOXED(1325400063,32,FLEN) +NAN_BOXED(1325400063,32,FLEN) +NAN_BOXED(1325400063,32,FLEN) +NAN_BOXED(1325400064,32,FLEN) +NAN_BOXED(1325400064,32,FLEN) +NAN_BOXED(1325400064,32,FLEN) +NAN_BOXED(1325400064,32,FLEN) +NAN_BOXED(1325400064,32,FLEN) +NAN_BOXED(1325400065,32,FLEN) +NAN_BOXED(1325400065,32,FLEN) +NAN_BOXED(1325400065,32,FLEN) +NAN_BOXED(1325400065,32,FLEN) +NAN_BOXED(1325400065,32,FLEN) +NAN_BOXED(1325400066,32,FLEN) +NAN_BOXED(1325400066,32,FLEN) +NAN_BOXED(1325400066,32,FLEN) +NAN_BOXED(1325400066,32,FLEN) +NAN_BOXED(1325400066,32,FLEN) +NAN_BOXED(1325400067,32,FLEN) +NAN_BOXED(1325400067,32,FLEN) +NAN_BOXED(1325400067,32,FLEN) +NAN_BOXED(1325400067,32,FLEN) +NAN_BOXED(1325400067,32,FLEN) +NAN_BOXED(1325400068,32,FLEN) +NAN_BOXED(1325400068,32,FLEN) +NAN_BOXED(1325400068,32,FLEN) +NAN_BOXED(1325400068,32,FLEN) +NAN_BOXED(1325400068,32,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 90*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b24-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b24-01.S new file mode 100644 index 000000000..e7da9dea1 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b24-01.S @@ -0,0 +1,929 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Sat Sep 14 02:42:23 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.s.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.h.s instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.h.s_b24 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.s_b24) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f31; dest:f31; op1val:0x7f0; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 != rd, rs1==f29, rd==f30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f29; dest:f30; op1val:0x7f0; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f30, f29, 32, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f29; op1val:0x7f0; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f29, f30, 64, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f27; dest:f28; op1val:0x7f0; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f28, f27, 96, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f28; dest:f27; op1val:0x7f0; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f27, f28, 128, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 1 and fe1 == 0x7e and fm1 == 0x7d70a3 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f25; dest:f26; op1val:0xbf7d70a3; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 1 and fe1 == 0x7e and fm1 == 0x7d70a3 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f26; dest:f25; op1val:0xbf7d70a3; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f25, f26, 32, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 1 and fe1 == 0x7e and fm1 == 0x7d70a3 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f23; dest:f24; op1val:0xbf7d70a3; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f24, f23, 64, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 1 and fe1 == 0x7e and fm1 == 0x7d70a3 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f24; dest:f23; op1val:0xbf7d70a3; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f23, f24, 96, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 1 and fe1 == 0x7e and fm1 == 0x7d70a3 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f21; dest:f22; op1val:0xbf7d70a3; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f22, f21, 128, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x7b and fm1 == 0x4ccccc and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f22; dest:f21; op1val:0x3dcccccc; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 0 and fe1 == 0x7b and fm1 == 0x4ccccc and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f19; dest:f20; op1val:0x3dcccccc; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f20, f19, 32, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0x7b and fm1 == 0x4ccccc and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f20; dest:f19; op1val:0x3dcccccc; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f19, f20, 64, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 0 and fe1 == 0x7b and fm1 == 0x4ccccc and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f17; dest:f18; op1val:0x3dcccccc; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f18, f17, 96, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0x7b and fm1 == 0x4ccccc and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f18; dest:f17; op1val:0x3dcccccc; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f17, f18, 128, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 1 and fe1 == 0x7f and fm1 == 0x0ccccc and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f15; dest:f16; op1val:0xbf8ccccc; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 1 and fe1 == 0x7f and fm1 == 0x0ccccc and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f16; dest:f15; op1val:0xbf8ccccc; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f15, f16, 32, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 1 and fe1 == 0x7f and fm1 == 0x0ccccc and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f13; dest:f14; op1val:0xbf8ccccc; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f14, f13, 64, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 1 and fe1 == 0x7f and fm1 == 0x0ccccc and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f14; dest:f13; op1val:0xbf8ccccc; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f13, f14, 96, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 1 and fe1 == 0x7f and fm1 == 0x0ccccc and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f11; dest:f12; op1val:0xbf8ccccc; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f12, f11, 128, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 0 and fe1 == 0x7b and fm1 == 0x6147ae and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f12; dest:f11; op1val:0x3de147ae; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10,fs1 == 0 and fe1 == 0x7b and fm1 == 0x6147ae and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f9; dest:f10; op1val:0x3de147ae; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f10, f9, 32, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9,fs1 == 0 and fe1 == 0x7b and fm1 == 0x6147ae and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f10; dest:f9; op1val:0x3de147ae; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f9, f10, 64, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8,fs1 == 0 and fe1 == 0x7b and fm1 == 0x6147ae and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f7; dest:f8; op1val:0x3de147ae; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f8, f7, 96, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7,fs1 == 0 and fe1 == 0x7b and fm1 == 0x6147ae and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f8; dest:f7; op1val:0x3de147ae; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f7, f8, 128, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6,fs1 == 0 and fe1 == 0x7f and fm1 == 0x0e147a and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f5; dest:f6; op1val:0x3f8e147a; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5,fs1 == 0 and fe1 == 0x7f and fm1 == 0x0e147a and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f6; dest:f5; op1val:0x3f8e147a; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f5, f6, 32, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4,fs1 == 0 and fe1 == 0x7f and fm1 == 0x0e147a and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f3; dest:f4; op1val:0x3f8e147a; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f4, f3, 64, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3,fs1 == 0 and fe1 == 0x7f and fm1 == 0x0e147a and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f4; dest:f3; op1val:0x3f8e147a; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f3, f4, 96, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2,fs1 == 0 and fe1 == 0x7f and fm1 == 0x0e147a and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f1; dest:f2; op1val:0x3f8e147a; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f2, f1, 128, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1,fs1 == 1 and fe1 == 0x7f and fm1 == 0x0147ae and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f2; dest:f1; op1val:0xbf8147ae; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0,fs1 == 1 and fe1 == 0x7f and fm1 == 0x0147ae and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f0; dest:f31; op1val:0xbf8147ae; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f0, 32, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0,fs1 == 1 and fe1 == 0x7f and fm1 == 0x0147ae and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f31; dest:f0; op1val:0xbf8147ae; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f0, f31, 64, 0, x3, 32*FLEN/8, x4, x1, x2) + +inst_33: +// fs1 == 1 and fe1 == 0x7f and fm1 == 0x0147ae and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbf8147ae; valaddr_reg:x3; +val_offset:33*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 33*FLEN/8, x4, x1, x2) + +inst_34: +// fs1 == 1 and fe1 == 0x7f and fm1 == 0x0147ae and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbf8147ae; valaddr_reg:x3; +val_offset:34*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 34*FLEN/8, x4, x1, x2) + +inst_35: +// fs1 == 1 and fe1 == 0x7e and fm1 == 0x63d70a and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbf63d70a; valaddr_reg:x3; +val_offset:35*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 35*FLEN/8, x4, x1, x2) + +inst_36: +// fs1 == 1 and fe1 == 0x7e and fm1 == 0x63d70a and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbf63d70a; valaddr_reg:x3; +val_offset:36*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 36*FLEN/8, x4, x1, x2) + +inst_37: +// fs1 == 1 and fe1 == 0x7e and fm1 == 0x63d70a and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbf63d70a; valaddr_reg:x3; +val_offset:37*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 37*FLEN/8, x4, x1, x2) + +inst_38: +// fs1 == 1 and fe1 == 0x7e and fm1 == 0x63d70a and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbf63d70a; valaddr_reg:x3; +val_offset:38*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 38*FLEN/8, x4, x1, x2) + +inst_39: +// fs1 == 1 and fe1 == 0x7e and fm1 == 0x63d70a and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbf63d70a; valaddr_reg:x3; +val_offset:39*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 39*FLEN/8, x4, x1, x2) + +inst_40: +// fs1 == 1 and fe1 == 0x7b and fm1 == 0x4ccccc and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbdcccccc; valaddr_reg:x3; +val_offset:40*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 40*FLEN/8, x4, x1, x2) + +inst_41: +// fs1 == 1 and fe1 == 0x7b and fm1 == 0x4ccccc and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbdcccccc; valaddr_reg:x3; +val_offset:41*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 41*FLEN/8, x4, x1, x2) + +inst_42: +// fs1 == 1 and fe1 == 0x7b and fm1 == 0x4ccccc and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbdcccccc; valaddr_reg:x3; +val_offset:42*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 42*FLEN/8, x4, x1, x2) + +inst_43: +// fs1 == 1 and fe1 == 0x7b and fm1 == 0x4ccccc and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbdcccccc; valaddr_reg:x3; +val_offset:43*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 43*FLEN/8, x4, x1, x2) + +inst_44: +// fs1 == 1 and fe1 == 0x7b and fm1 == 0x4ccccc and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbdcccccc; valaddr_reg:x3; +val_offset:44*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 44*FLEN/8, x4, x1, x2) + +inst_45: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f800000; valaddr_reg:x3; +val_offset:45*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 45*FLEN/8, x4, x1, x2) + +inst_46: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f800000; valaddr_reg:x3; +val_offset:46*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 46*FLEN/8, x4, x1, x2) + +inst_47: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f800000; valaddr_reg:x3; +val_offset:47*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 47*FLEN/8, x4, x1, x2) + +inst_48: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f800000; valaddr_reg:x3; +val_offset:48*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 48*FLEN/8, x4, x1, x2) + +inst_49: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f800000; valaddr_reg:x3; +val_offset:49*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 49*FLEN/8, x4, x1, x2) + +inst_50: +// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbf800000; valaddr_reg:x3; +val_offset:50*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 50*FLEN/8, x4, x1, x2) + +inst_51: +// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbf800000; valaddr_reg:x3; +val_offset:51*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 51*FLEN/8, x4, x1, x2) + +inst_52: +// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbf800000; valaddr_reg:x3; +val_offset:52*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 52*FLEN/8, x4, x1, x2) + +inst_53: +// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbf800000; valaddr_reg:x3; +val_offset:53*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 53*FLEN/8, x4, x1, x2) + +inst_54: +// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbf800000; valaddr_reg:x3; +val_offset:54*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 54*FLEN/8, x4, x1, x2) + +inst_55: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x0ccccc and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f8ccccc; valaddr_reg:x3; +val_offset:55*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 55*FLEN/8, x4, x1, x2) + +inst_56: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x0ccccc and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f8ccccc; valaddr_reg:x3; +val_offset:56*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 56*FLEN/8, x4, x1, x2) + +inst_57: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x0ccccc and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f8ccccc; valaddr_reg:x3; +val_offset:57*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 57*FLEN/8, x4, x1, x2) + +inst_58: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x0ccccc and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f8ccccc; valaddr_reg:x3; +val_offset:58*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 58*FLEN/8, x4, x1, x2) + +inst_59: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x0ccccc and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f8ccccc; valaddr_reg:x3; +val_offset:59*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 59*FLEN/8, x4, x1, x2) + +inst_60: +// fs1 == 0 and fe1 == 0x7e and fm1 == 0x666666 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f666666; valaddr_reg:x3; +val_offset:60*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 60*FLEN/8, x4, x1, x2) + +inst_61: +// fs1 == 0 and fe1 == 0x7e and fm1 == 0x666666 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f666666; valaddr_reg:x3; +val_offset:61*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 61*FLEN/8, x4, x1, x2) + +inst_62: +// fs1 == 0 and fe1 == 0x7e and fm1 == 0x666666 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f666666; valaddr_reg:x3; +val_offset:62*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 62*FLEN/8, x4, x1, x2) + +inst_63: +// fs1 == 0 and fe1 == 0x7e and fm1 == 0x666666 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f666666; valaddr_reg:x3; +val_offset:63*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 63*FLEN/8, x4, x1, x2) + +inst_64: +// fs1 == 0 and fe1 == 0x7e and fm1 == 0x666666 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f666666; valaddr_reg:x3; +val_offset:64*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 64*FLEN/8, x4, x1, x2) + +inst_65: +// fs1 == 1 and fe1 == 0x78 and fm1 == 0x23d70a and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbc23d70a; valaddr_reg:x3; +val_offset:65*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 65*FLEN/8, x4, x1, x2) + +inst_66: +// fs1 == 1 and fe1 == 0x78 and fm1 == 0x23d70a and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbc23d70a; valaddr_reg:x3; +val_offset:66*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 66*FLEN/8, x4, x1, x2) + +inst_67: +// fs1 == 1 and fe1 == 0x78 and fm1 == 0x23d70a and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbc23d70a; valaddr_reg:x3; +val_offset:67*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 67*FLEN/8, x4, x1, x2) + +inst_68: +// fs1 == 1 and fe1 == 0x78 and fm1 == 0x23d70a and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbc23d70a; valaddr_reg:x3; +val_offset:68*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 68*FLEN/8, x4, x1, x2) + +inst_69: +// fs1 == 1 and fe1 == 0x78 and fm1 == 0x23d70a and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbc23d70a; valaddr_reg:x3; +val_offset:69*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 69*FLEN/8, x4, x1, x2) + +inst_70: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x0147ae and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f8147ae; valaddr_reg:x3; +val_offset:70*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 70*FLEN/8, x4, x1, x2) + +inst_71: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x0147ae and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f8147ae; valaddr_reg:x3; +val_offset:71*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 71*FLEN/8, x4, x1, x2) + +inst_72: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x0147ae and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f8147ae; valaddr_reg:x3; +val_offset:72*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 72*FLEN/8, x4, x1, x2) + +inst_73: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x0147ae and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f8147ae; valaddr_reg:x3; +val_offset:73*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 73*FLEN/8, x4, x1, x2) + +inst_74: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x0147ae and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f8147ae; valaddr_reg:x3; +val_offset:74*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 74*FLEN/8, x4, x1, x2) + +inst_75: +// fs1 == 0 and fe1 == 0x7e and fm1 == 0x63d70a and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f63d70a; valaddr_reg:x3; +val_offset:75*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 75*FLEN/8, x4, x1, x2) + +inst_76: +// fs1 == 0 and fe1 == 0x7e and fm1 == 0x63d70a and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f63d70a; valaddr_reg:x3; +val_offset:76*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 76*FLEN/8, x4, x1, x2) + +inst_77: +// fs1 == 0 and fe1 == 0x7e and fm1 == 0x63d70a and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f63d70a; valaddr_reg:x3; +val_offset:77*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 77*FLEN/8, x4, x1, x2) + +inst_78: +// fs1 == 0 and fe1 == 0x7e and fm1 == 0x63d70a and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f63d70a; valaddr_reg:x3; +val_offset:78*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 78*FLEN/8, x4, x1, x2) + +inst_79: +// fs1 == 0 and fe1 == 0x7e and fm1 == 0x63d70a and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f63d70a; valaddr_reg:x3; +val_offset:79*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 79*FLEN/8, x4, x1, x2) + +inst_80: +// fs1 == 1 and fe1 == 0x7b and fm1 == 0x6147ae and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbde147ae; valaddr_reg:x3; +val_offset:80*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 80*FLEN/8, x4, x1, x2) + +inst_81: +// fs1 == 1 and fe1 == 0x7b and fm1 == 0x6147ae and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbde147ae; valaddr_reg:x3; +val_offset:81*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 81*FLEN/8, x4, x1, x2) + +inst_82: +// fs1 == 1 and fe1 == 0x7b and fm1 == 0x6147ae and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbde147ae; valaddr_reg:x3; +val_offset:82*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 82*FLEN/8, x4, x1, x2) + +inst_83: +// fs1 == 1 and fe1 == 0x7b and fm1 == 0x6147ae and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbde147ae; valaddr_reg:x3; +val_offset:83*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 83*FLEN/8, x4, x1, x2) + +inst_84: +// fs1 == 1 and fe1 == 0x7b and fm1 == 0x6147ae and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbde147ae; valaddr_reg:x3; +val_offset:84*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 84*FLEN/8, x4, x1, x2) + +inst_85: +// fs1 == 0 and fe1 == 0x78 and fm1 == 0x23d70a and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3c23d70a; valaddr_reg:x3; +val_offset:85*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 85*FLEN/8, x4, x1, x2) + +inst_86: +// fs1 == 0 and fe1 == 0x78 and fm1 == 0x23d70a and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3c23d70a; valaddr_reg:x3; +val_offset:86*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 86*FLEN/8, x4, x1, x2) + +inst_87: +// fs1 == 0 and fe1 == 0x78 and fm1 == 0x23d70a and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3c23d70a; valaddr_reg:x3; +val_offset:87*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 87*FLEN/8, x4, x1, x2) + +inst_88: +// fs1 == 0 and fe1 == 0x78 and fm1 == 0x23d70a and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3c23d70a; valaddr_reg:x3; +val_offset:88*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 88*FLEN/8, x4, x1, x2) + +inst_89: +// fs1 == 0 and fe1 == 0x78 and fm1 == 0x23d70a and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3c23d70a; valaddr_reg:x3; +val_offset:89*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 89*FLEN/8, x4, x1, x2) + +inst_90: +// fs1 == 1 and fe1 == 0x7e and fm1 == 0x666666 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbf666666; valaddr_reg:x3; +val_offset:90*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 90*FLEN/8, x4, x1, x2) + +inst_91: +// fs1 == 1 and fe1 == 0x7e and fm1 == 0x666666 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbf666666; valaddr_reg:x3; +val_offset:91*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 91*FLEN/8, x4, x1, x2) + +inst_92: +// fs1 == 1 and fe1 == 0x7e and fm1 == 0x666666 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbf666666; valaddr_reg:x3; +val_offset:92*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 92*FLEN/8, x4, x1, x2) + +inst_93: +// fs1 == 1 and fe1 == 0x7e and fm1 == 0x666666 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbf666666; valaddr_reg:x3; +val_offset:93*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 93*FLEN/8, x4, x1, x2) + +inst_94: +// fs1 == 1 and fe1 == 0x7e and fm1 == 0x666666 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbf666666; valaddr_reg:x3; +val_offset:94*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 94*FLEN/8, x4, x1, x2) + +inst_95: +// fs1 == 1 and fe1 == 0x7f and fm1 == 0x0e147a and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbf8e147a; valaddr_reg:x3; +val_offset:95*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 95*FLEN/8, x4, x1, x2) + +inst_96: +// fs1 == 1 and fe1 == 0x7f and fm1 == 0x0e147a and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbf8e147a; valaddr_reg:x3; +val_offset:96*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 96*FLEN/8, x4, x1, x2) + +inst_97: +// fs1 == 1 and fe1 == 0x7f and fm1 == 0x0e147a and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbf8e147a; valaddr_reg:x3; +val_offset:97*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 97*FLEN/8, x4, x1, x2) + +inst_98: +// fs1 == 1 and fe1 == 0x7f and fm1 == 0x0e147a and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbf8e147a; valaddr_reg:x3; +val_offset:98*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 98*FLEN/8, x4, x1, x2) + +inst_99: +// fs1 == 1 and fe1 == 0x7f and fm1 == 0x0e147a and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbf8e147a; valaddr_reg:x3; +val_offset:99*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 99*FLEN/8, x4, x1, x2) + +inst_100: +// fs1 == 0 and fe1 == 0x7e and fm1 == 0x7d70a3 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f7d70a3; valaddr_reg:x3; +val_offset:100*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 100*FLEN/8, x4, x1, x2) + +inst_101: +// fs1 == 0 and fe1 == 0x7e and fm1 == 0x7d70a3 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f7d70a3; valaddr_reg:x3; +val_offset:101*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 101*FLEN/8, x4, x1, x2) + +inst_102: +// fs1 == 0 and fe1 == 0x7e and fm1 == 0x7d70a3 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f7d70a3; valaddr_reg:x3; +val_offset:102*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 102*FLEN/8, x4, x1, x2) + +inst_103: +// fs1 == 0 and fe1 == 0x7e and fm1 == 0x7d70a3 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f7d70a3; valaddr_reg:x3; +val_offset:103*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 103*FLEN/8, x4, x1, x2) + +inst_104: +// fs1 == 0 and fe1 == 0x7e and fm1 == 0x7d70a3 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f7d70a3; valaddr_reg:x3; +val_offset:104*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 104*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(2032,32,FLEN) +NAN_BOXED(2032,32,FLEN) +NAN_BOXED(2032,32,FLEN) +NAN_BOXED(2032,32,FLEN) +NAN_BOXED(2032,32,FLEN) +NAN_BOXED(3212669091,32,FLEN) +NAN_BOXED(3212669091,32,FLEN) +NAN_BOXED(3212669091,32,FLEN) +NAN_BOXED(3212669091,32,FLEN) +NAN_BOXED(3212669091,32,FLEN) +NAN_BOXED(1036831948,32,FLEN) +NAN_BOXED(1036831948,32,FLEN) +NAN_BOXED(1036831948,32,FLEN) +NAN_BOXED(1036831948,32,FLEN) +NAN_BOXED(1036831948,32,FLEN) +NAN_BOXED(3213675724,32,FLEN) +NAN_BOXED(3213675724,32,FLEN) +NAN_BOXED(3213675724,32,FLEN) +NAN_BOXED(3213675724,32,FLEN) +NAN_BOXED(3213675724,32,FLEN) +NAN_BOXED(1038174126,32,FLEN) +NAN_BOXED(1038174126,32,FLEN) +NAN_BOXED(1038174126,32,FLEN) +NAN_BOXED(1038174126,32,FLEN) +NAN_BOXED(1038174126,32,FLEN) +NAN_BOXED(1066275962,32,FLEN) +NAN_BOXED(1066275962,32,FLEN) +NAN_BOXED(1066275962,32,FLEN) +NAN_BOXED(1066275962,32,FLEN) +NAN_BOXED(1066275962,32,FLEN) +NAN_BOXED(3212920750,32,FLEN) +NAN_BOXED(3212920750,32,FLEN) +NAN_BOXED(3212920750,32,FLEN) +NAN_BOXED(3212920750,32,FLEN) +NAN_BOXED(3212920750,32,FLEN) +NAN_BOXED(3210991370,32,FLEN) +NAN_BOXED(3210991370,32,FLEN) +NAN_BOXED(3210991370,32,FLEN) +NAN_BOXED(3210991370,32,FLEN) +NAN_BOXED(3210991370,32,FLEN) +NAN_BOXED(3184315596,32,FLEN) +NAN_BOXED(3184315596,32,FLEN) +NAN_BOXED(3184315596,32,FLEN) +NAN_BOXED(3184315596,32,FLEN) +NAN_BOXED(3184315596,32,FLEN) +NAN_BOXED(1065353216,32,FLEN) +NAN_BOXED(1065353216,32,FLEN) +NAN_BOXED(1065353216,32,FLEN) +NAN_BOXED(1065353216,32,FLEN) +NAN_BOXED(1065353216,32,FLEN) +NAN_BOXED(3212836864,32,FLEN) +NAN_BOXED(3212836864,32,FLEN) +NAN_BOXED(3212836864,32,FLEN) +NAN_BOXED(3212836864,32,FLEN) +NAN_BOXED(3212836864,32,FLEN) +NAN_BOXED(1066192076,32,FLEN) +NAN_BOXED(1066192076,32,FLEN) +NAN_BOXED(1066192076,32,FLEN) +NAN_BOXED(1066192076,32,FLEN) +NAN_BOXED(1066192076,32,FLEN) +NAN_BOXED(1063675494,32,FLEN) +NAN_BOXED(1063675494,32,FLEN) +NAN_BOXED(1063675494,32,FLEN) +NAN_BOXED(1063675494,32,FLEN) +NAN_BOXED(1063675494,32,FLEN) +NAN_BOXED(3156465418,32,FLEN) +NAN_BOXED(3156465418,32,FLEN) +NAN_BOXED(3156465418,32,FLEN) +NAN_BOXED(3156465418,32,FLEN) +NAN_BOXED(3156465418,32,FLEN) +NAN_BOXED(1065437102,32,FLEN) +NAN_BOXED(1065437102,32,FLEN) +NAN_BOXED(1065437102,32,FLEN) +NAN_BOXED(1065437102,32,FLEN) +NAN_BOXED(1065437102,32,FLEN) +NAN_BOXED(1063507722,32,FLEN) +NAN_BOXED(1063507722,32,FLEN) +NAN_BOXED(1063507722,32,FLEN) +NAN_BOXED(1063507722,32,FLEN) +NAN_BOXED(1063507722,32,FLEN) +NAN_BOXED(3185657774,32,FLEN) +NAN_BOXED(3185657774,32,FLEN) +NAN_BOXED(3185657774,32,FLEN) +NAN_BOXED(3185657774,32,FLEN) +NAN_BOXED(3185657774,32,FLEN) +NAN_BOXED(1008981770,32,FLEN) +NAN_BOXED(1008981770,32,FLEN) +NAN_BOXED(1008981770,32,FLEN) +NAN_BOXED(1008981770,32,FLEN) +NAN_BOXED(1008981770,32,FLEN) +NAN_BOXED(3211159142,32,FLEN) +NAN_BOXED(3211159142,32,FLEN) +NAN_BOXED(3211159142,32,FLEN) +NAN_BOXED(3211159142,32,FLEN) +NAN_BOXED(3211159142,32,FLEN) +NAN_BOXED(3213759610,32,FLEN) +NAN_BOXED(3213759610,32,FLEN) +NAN_BOXED(3213759610,32,FLEN) +NAN_BOXED(3213759610,32,FLEN) +NAN_BOXED(3213759610,32,FLEN) +NAN_BOXED(1065185443,32,FLEN) +NAN_BOXED(1065185443,32,FLEN) +NAN_BOXED(1065185443,32,FLEN) +NAN_BOXED(1065185443,32,FLEN) +NAN_BOXED(1065185443,32,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 210*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b27-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b27-01.S new file mode 100644 index 000000000..7f6174289 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b27-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Sat Sep 14 02:42:23 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.s.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.h.s instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.h.s_b27 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.s_b27) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f31; dest:f31; op1val:0x7f800001; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 != rd, rs1==f29, rd==f30,fs1 == 1 and fe1 == 0xff and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f29; dest:f30; op1val:0xff800001; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f30, f29, 0, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0xff and fm1 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f29; op1val:0x7faaaaaa; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f29, f30, 0, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f27; dest:f28; op1val:0xffaaaaaa; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f28, f27, 0, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f28; dest:f27; op1val:0x7fc00001; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f27, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 1 and fe1 == 0xff and fm1 == 0x400001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f25; dest:f26; op1val:0xffc00001; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0xff and fm1 == 0x455555 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f26; dest:f25; op1val:0x7fc55555; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f25, f26, 0, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f23; dest:f24; op1val:0xffc55555; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f24, f23, 0, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23, +/* opcode: fcvt.h.s ; op1:f24; dest:f23; op1val:0x0; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f23, f24, 0, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22, +/* opcode: fcvt.h.s ; op1:f21; dest:f22; op1val:0x0; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f22, f21, 0, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21, +/* opcode: fcvt.h.s ; op1:f22; dest:f21; op1val:0x0; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20, +/* opcode: fcvt.h.s ; op1:f19; dest:f20; op1val:0x0; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f20, f19, 0, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19, +/* opcode: fcvt.h.s ; op1:f20; dest:f19; op1val:0x0; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f19, f20, 0, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18, +/* opcode: fcvt.h.s ; op1:f17; dest:f18; op1val:0x0; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f18, f17, 0, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17, +/* opcode: fcvt.h.s ; op1:f18; dest:f17; op1val:0x0; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f17, f18, 0, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16, +/* opcode: fcvt.h.s ; op1:f15; dest:f16; op1val:0x0; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15, +/* opcode: fcvt.h.s ; op1:f16; dest:f15; op1val:0x0; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f15, f16, 0, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14, +/* opcode: fcvt.h.s ; op1:f13; dest:f14; op1val:0x0; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f14, f13, 0, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13, +/* opcode: fcvt.h.s ; op1:f14; dest:f13; op1val:0x0; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f13, f14, 0, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12, +/* opcode: fcvt.h.s ; op1:f11; dest:f12; op1val:0x0; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f12, f11, 0, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11, +/* opcode: fcvt.h.s ; op1:f12; dest:f11; op1val:0x0; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10, +/* opcode: fcvt.h.s ; op1:f9; dest:f10; op1val:0x0; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f10, f9, 0, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9, +/* opcode: fcvt.h.s ; op1:f10; dest:f9; op1val:0x0; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f9, f10, 0, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8, +/* opcode: fcvt.h.s ; op1:f7; dest:f8; op1val:0x0; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f8, f7, 0, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7, +/* opcode: fcvt.h.s ; op1:f8; dest:f7; op1val:0x0; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f7, f8, 0, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6, +/* opcode: fcvt.h.s ; op1:f5; dest:f6; op1val:0x0; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5, +/* opcode: fcvt.h.s ; op1:f6; dest:f5; op1val:0x0; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f5, f6, 0, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4, +/* opcode: fcvt.h.s ; op1:f3; dest:f4; op1val:0x0; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f4, f3, 0, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3, +/* opcode: fcvt.h.s ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f3, f4, 0, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2, +/* opcode: fcvt.h.s ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f2, f1, 0, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1, +/* opcode: fcvt.h.s ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0, +/* opcode: fcvt.h.s ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f0, 0, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0, +/* opcode: fcvt.h.s ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f0, f31, 0, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(2139095041,32,FLEN) +NAN_BOXED(4286578689,32,FLEN) +NAN_BOXED(2141891242,32,FLEN) +NAN_BOXED(4289374890,32,FLEN) +NAN_BOXED(2143289345,32,FLEN) +NAN_BOXED(4290772993,32,FLEN) +NAN_BOXED(2143638869,32,FLEN) +NAN_BOXED(4291122517,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b28-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b28-01.S new file mode 100644 index 000000000..4c5592ee2 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b28-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Sat Sep 14 02:42:23 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.s.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.h.s instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.h.s_b28 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.s_b28) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f31; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 != rd, rs1==f29, rd==f30,fs1 == 0 and fe1 == 0x7e and fm1 == 0x124770 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f29; dest:f30; op1val:0x3f124770; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f30, f29, 0, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f29; op1val:0x3f800000; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f29, f30, 0, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x7f and fm1 == 0x200000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f27; dest:f28; op1val:0x3fa00000; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f28, f27, 0, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x7f and fm1 == 0x400000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f28; dest:f27; op1val:0x3fc00000; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f27, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 0 and fe1 == 0x7f and fm1 == 0x600000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f25; dest:f26; op1val:0x3fe00000; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x80 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f26; dest:f25; op1val:0x40000000; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f25, f26, 0, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 0 and fe1 == 0x80 and fm1 == 0x100000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f23; dest:f24; op1val:0x40100000; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f24, f23, 0, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x80 and fm1 == 0x200000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f24; dest:f23; op1val:0x40200000; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f23, f24, 0, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 0 and fe1 == 0x80 and fm1 == 0x300000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f21; dest:f22; op1val:0x40300000; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f22, f21, 0, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x9c and fm1 == 0x5b9758 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f22; dest:f21; op1val:0x4e5b9758; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7fffff and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f19; dest:f20; op1val:0x4effffff; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f20, f19, 0, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f20; dest:f19; op1val:0x7f800000; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f19, f20, 0, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f17; dest:f18; op1val:0x7f800001; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f18, f17, 0, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f18; dest:f17; op1val:0x7fc00001; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f17, f18, 0, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f15; dest:f16; op1val:0x80000000; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 1 and fe1 == 0x7d and fm1 == 0x58046a and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f16; dest:f15; op1val:0xbed8046a; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f15, f16, 0, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f13; dest:f14; op1val:0xbf800000; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f14, f13, 0, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 1 and fe1 == 0x80 and fm1 == 0x300000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f14; dest:f13; op1val:0xc0300000; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f13, f14, 0, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 1 and fe1 == 0x80 and fm1 == 0x200000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f11; dest:f12; op1val:0xc0200000; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f12, f11, 0, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 1 and fe1 == 0x80 and fm1 == 0x100000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f12; dest:f11; op1val:0xc0100000; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10,fs1 == 1 and fe1 == 0x80 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f9; dest:f10; op1val:0xc0000000; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f10, f9, 0, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9,fs1 == 1 and fe1 == 0x7f and fm1 == 0x600000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f10; dest:f9; op1val:0xbfe00000; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f9, f10, 0, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8,fs1 == 1 and fe1 == 0x7f and fm1 == 0x400000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f7; dest:f8; op1val:0xbfc00000; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f8, f7, 0, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7,fs1 == 1 and fe1 == 0x7f and fm1 == 0x200000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f8; dest:f7; op1val:0xbfa00000; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f7, f8, 0, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6,fs1 == 1 and fe1 == 0x9d and fm1 == 0x4b3d25 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f5; dest:f6; op1val:0xcecb3d25; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5,fs1 == 1 and fe1 == 0x9e and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f6; dest:f5; op1val:0xcf000000; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f5, f6, 0, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4,fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f3; dest:f4; op1val:0xff800000; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f4, f3, 0, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3, +/* opcode: fcvt.h.s ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f3, f4, 0, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2, +/* opcode: fcvt.h.s ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f2, f1, 0, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1, +/* opcode: fcvt.h.s ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0, +/* opcode: fcvt.h.s ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f0, 0, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0, +/* opcode: fcvt.h.s ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f0, f31, 0, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(1058162544,32,FLEN) +NAN_BOXED(1065353216,32,FLEN) +NAN_BOXED(1067450368,32,FLEN) +NAN_BOXED(1069547520,32,FLEN) +NAN_BOXED(1071644672,32,FLEN) +NAN_BOXED(1073741824,32,FLEN) +NAN_BOXED(1074790400,32,FLEN) +NAN_BOXED(1075838976,32,FLEN) +NAN_BOXED(1076887552,32,FLEN) +NAN_BOXED(1314625368,32,FLEN) +NAN_BOXED(1325400063,32,FLEN) +NAN_BOXED(2139095040,32,FLEN) +NAN_BOXED(2139095041,32,FLEN) +NAN_BOXED(2143289345,32,FLEN) +NAN_BOXED(2147483648,32,FLEN) +NAN_BOXED(3201827946,32,FLEN) +NAN_BOXED(3212836864,32,FLEN) +NAN_BOXED(3224371200,32,FLEN) +NAN_BOXED(3223322624,32,FLEN) +NAN_BOXED(3222274048,32,FLEN) +NAN_BOXED(3221225472,32,FLEN) +NAN_BOXED(3219128320,32,FLEN) +NAN_BOXED(3217031168,32,FLEN) +NAN_BOXED(3214934016,32,FLEN) +NAN_BOXED(3469425957,32,FLEN) +NAN_BOXED(3472883712,32,FLEN) +NAN_BOXED(4286578688,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b29-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b29-01.S new file mode 100644 index 000000000..adfa2f8b2 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b29-01.S @@ -0,0 +1,729 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Sat Sep 14 02:42:23 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.s.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.h.s instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.h.s_b29 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.s_b29) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923b8 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f31; dest:f31; op1val:0x3e4923b8; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 != rd, rs1==f29, rd==f30,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923b8 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f29; dest:f30; op1val:0x3e4923b8; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f30, f29, 32, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923b8 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f29; op1val:0x3e4923b8; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f29, f30, 64, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923b8 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f27; dest:f28; op1val:0x3e4923b8; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f28, f27, 96, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923b8 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f28; dest:f27; op1val:0x3e4923b8; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f27, f28, 128, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923b9 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f25; dest:f26; op1val:0x3e4923b9; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923b9 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f26; dest:f25; op1val:0x3e4923b9; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f25, f26, 32, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923b9 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f23; dest:f24; op1val:0x3e4923b9; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f24, f23, 64, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923b9 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f24; dest:f23; op1val:0x3e4923b9; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f23, f24, 96, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923b9 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f21; dest:f22; op1val:0x3e4923b9; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f22, f21, 128, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923ba and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f22; dest:f21; op1val:0x3e4923ba; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923ba and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f19; dest:f20; op1val:0x3e4923ba; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f20, f19, 32, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923ba and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f20; dest:f19; op1val:0x3e4923ba; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f19, f20, 64, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923ba and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f17; dest:f18; op1val:0x3e4923ba; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f18, f17, 96, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923ba and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f18; dest:f17; op1val:0x3e4923ba; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f17, f18, 128, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bb and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f15; dest:f16; op1val:0x3e4923bb; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bb and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f16; dest:f15; op1val:0x3e4923bb; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f15, f16, 32, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bb and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f13; dest:f14; op1val:0x3e4923bb; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f14, f13, 64, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bb and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f14; dest:f13; op1val:0x3e4923bb; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f13, f14, 96, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bb and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f11; dest:f12; op1val:0x3e4923bb; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f12, f11, 128, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bc and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f12; dest:f11; op1val:0x3e4923bc; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bc and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f9; dest:f10; op1val:0x3e4923bc; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f10, f9, 32, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bc and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f10; dest:f9; op1val:0x3e4923bc; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f9, f10, 64, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bc and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f7; dest:f8; op1val:0x3e4923bc; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f8, f7, 96, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bc and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f8; dest:f7; op1val:0x3e4923bc; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f7, f8, 128, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bd and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f5; dest:f6; op1val:0x3e4923bd; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bd and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f6; dest:f5; op1val:0x3e4923bd; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f5, f6, 32, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bd and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f3; dest:f4; op1val:0x3e4923bd; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f4, f3, 64, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bd and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f4; dest:f3; op1val:0x3e4923bd; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f3, f4, 96, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bd and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f1; dest:f2; op1val:0x3e4923bd; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f2, f1, 128, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923be and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f2; dest:f1; op1val:0x3e4923be; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923be and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f0; dest:f31; op1val:0x3e4923be; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f0, 32, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923be and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f31; dest:f0; op1val:0x3e4923be; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f0, f31, 64, 0, x3, 32*FLEN/8, x4, x1, x2) + +inst_33: +// fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923be and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3e4923be; valaddr_reg:x3; +val_offset:33*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 33*FLEN/8, x4, x1, x2) + +inst_34: +// fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923be and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3e4923be; valaddr_reg:x3; +val_offset:34*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 34*FLEN/8, x4, x1, x2) + +inst_35: +// fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bf and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3e4923bf; valaddr_reg:x3; +val_offset:35*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 35*FLEN/8, x4, x1, x2) + +inst_36: +// fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bf and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3e4923bf; valaddr_reg:x3; +val_offset:36*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 36*FLEN/8, x4, x1, x2) + +inst_37: +// fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bf and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3e4923bf; valaddr_reg:x3; +val_offset:37*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 37*FLEN/8, x4, x1, x2) + +inst_38: +// fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bf and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3e4923bf; valaddr_reg:x3; +val_offset:38*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 38*FLEN/8, x4, x1, x2) + +inst_39: +// fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bf and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3e4923bf; valaddr_reg:x3; +val_offset:39*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 39*FLEN/8, x4, x1, x2) + +inst_40: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923b8 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923b8; valaddr_reg:x3; +val_offset:40*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 40*FLEN/8, x4, x1, x2) + +inst_41: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923b8 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923b8; valaddr_reg:x3; +val_offset:41*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 41*FLEN/8, x4, x1, x2) + +inst_42: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923b8 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923b8; valaddr_reg:x3; +val_offset:42*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 42*FLEN/8, x4, x1, x2) + +inst_43: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923b8 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923b8; valaddr_reg:x3; +val_offset:43*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 43*FLEN/8, x4, x1, x2) + +inst_44: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923b8 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923b8; valaddr_reg:x3; +val_offset:44*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 44*FLEN/8, x4, x1, x2) + +inst_45: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923b9 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923b9; valaddr_reg:x3; +val_offset:45*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 45*FLEN/8, x4, x1, x2) + +inst_46: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923b9 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923b9; valaddr_reg:x3; +val_offset:46*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 46*FLEN/8, x4, x1, x2) + +inst_47: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923b9 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923b9; valaddr_reg:x3; +val_offset:47*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 47*FLEN/8, x4, x1, x2) + +inst_48: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923b9 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923b9; valaddr_reg:x3; +val_offset:48*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 48*FLEN/8, x4, x1, x2) + +inst_49: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923b9 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923b9; valaddr_reg:x3; +val_offset:49*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 49*FLEN/8, x4, x1, x2) + +inst_50: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923ba and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923ba; valaddr_reg:x3; +val_offset:50*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 50*FLEN/8, x4, x1, x2) + +inst_51: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923ba and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923ba; valaddr_reg:x3; +val_offset:51*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 51*FLEN/8, x4, x1, x2) + +inst_52: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923ba and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923ba; valaddr_reg:x3; +val_offset:52*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 52*FLEN/8, x4, x1, x2) + +inst_53: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923ba and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923ba; valaddr_reg:x3; +val_offset:53*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 53*FLEN/8, x4, x1, x2) + +inst_54: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923ba and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923ba; valaddr_reg:x3; +val_offset:54*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 54*FLEN/8, x4, x1, x2) + +inst_55: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bb and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923bb; valaddr_reg:x3; +val_offset:55*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 55*FLEN/8, x4, x1, x2) + +inst_56: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bb and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923bb; valaddr_reg:x3; +val_offset:56*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 56*FLEN/8, x4, x1, x2) + +inst_57: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bb and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923bb; valaddr_reg:x3; +val_offset:57*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 57*FLEN/8, x4, x1, x2) + +inst_58: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bb and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923bb; valaddr_reg:x3; +val_offset:58*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 58*FLEN/8, x4, x1, x2) + +inst_59: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bb and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923bb; valaddr_reg:x3; +val_offset:59*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 59*FLEN/8, x4, x1, x2) + +inst_60: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bc and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923bc; valaddr_reg:x3; +val_offset:60*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 60*FLEN/8, x4, x1, x2) + +inst_61: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bc and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923bc; valaddr_reg:x3; +val_offset:61*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 61*FLEN/8, x4, x1, x2) + +inst_62: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bc and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923bc; valaddr_reg:x3; +val_offset:62*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 62*FLEN/8, x4, x1, x2) + +inst_63: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bc and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923bc; valaddr_reg:x3; +val_offset:63*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 63*FLEN/8, x4, x1, x2) + +inst_64: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bc and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923bc; valaddr_reg:x3; +val_offset:64*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 64*FLEN/8, x4, x1, x2) + +inst_65: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bd and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923bd; valaddr_reg:x3; +val_offset:65*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 65*FLEN/8, x4, x1, x2) + +inst_66: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bd and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923bd; valaddr_reg:x3; +val_offset:66*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 66*FLEN/8, x4, x1, x2) + +inst_67: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bd and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923bd; valaddr_reg:x3; +val_offset:67*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 67*FLEN/8, x4, x1, x2) + +inst_68: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bd and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923bd; valaddr_reg:x3; +val_offset:68*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 68*FLEN/8, x4, x1, x2) + +inst_69: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bd and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923bd; valaddr_reg:x3; +val_offset:69*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 69*FLEN/8, x4, x1, x2) + +inst_70: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923be and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923be; valaddr_reg:x3; +val_offset:70*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 70*FLEN/8, x4, x1, x2) + +inst_71: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923be and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923be; valaddr_reg:x3; +val_offset:71*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 71*FLEN/8, x4, x1, x2) + +inst_72: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923be and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923be; valaddr_reg:x3; +val_offset:72*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 72*FLEN/8, x4, x1, x2) + +inst_73: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923be and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923be; valaddr_reg:x3; +val_offset:73*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 73*FLEN/8, x4, x1, x2) + +inst_74: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923be and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923be; valaddr_reg:x3; +val_offset:74*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 74*FLEN/8, x4, x1, x2) + +inst_75: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bf and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923bf; valaddr_reg:x3; +val_offset:75*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 75*FLEN/8, x4, x1, x2) + +inst_76: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bf and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923bf; valaddr_reg:x3; +val_offset:76*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 76*FLEN/8, x4, x1, x2) + +inst_77: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bf and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923bf; valaddr_reg:x3; +val_offset:77*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 77*FLEN/8, x4, x1, x2) + +inst_78: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bf and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923bf; valaddr_reg:x3; +val_offset:78*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 78*FLEN/8, x4, x1, x2) + +inst_79: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bf and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923bf; valaddr_reg:x3; +val_offset:79*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 79*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(1044980664,32,FLEN) +NAN_BOXED(1044980664,32,FLEN) +NAN_BOXED(1044980664,32,FLEN) +NAN_BOXED(1044980664,32,FLEN) +NAN_BOXED(1044980664,32,FLEN) +NAN_BOXED(1044980665,32,FLEN) +NAN_BOXED(1044980665,32,FLEN) +NAN_BOXED(1044980665,32,FLEN) +NAN_BOXED(1044980665,32,FLEN) +NAN_BOXED(1044980665,32,FLEN) +NAN_BOXED(1044980666,32,FLEN) +NAN_BOXED(1044980666,32,FLEN) +NAN_BOXED(1044980666,32,FLEN) +NAN_BOXED(1044980666,32,FLEN) +NAN_BOXED(1044980666,32,FLEN) +NAN_BOXED(1044980667,32,FLEN) +NAN_BOXED(1044980667,32,FLEN) +NAN_BOXED(1044980667,32,FLEN) +NAN_BOXED(1044980667,32,FLEN) +NAN_BOXED(1044980667,32,FLEN) +NAN_BOXED(1044980668,32,FLEN) +NAN_BOXED(1044980668,32,FLEN) +NAN_BOXED(1044980668,32,FLEN) +NAN_BOXED(1044980668,32,FLEN) +NAN_BOXED(1044980668,32,FLEN) +NAN_BOXED(1044980669,32,FLEN) +NAN_BOXED(1044980669,32,FLEN) +NAN_BOXED(1044980669,32,FLEN) +NAN_BOXED(1044980669,32,FLEN) +NAN_BOXED(1044980669,32,FLEN) +NAN_BOXED(1044980670,32,FLEN) +NAN_BOXED(1044980670,32,FLEN) +NAN_BOXED(1044980670,32,FLEN) +NAN_BOXED(1044980670,32,FLEN) +NAN_BOXED(1044980670,32,FLEN) +NAN_BOXED(1044980671,32,FLEN) +NAN_BOXED(1044980671,32,FLEN) +NAN_BOXED(1044980671,32,FLEN) +NAN_BOXED(1044980671,32,FLEN) +NAN_BOXED(1044980671,32,FLEN) +NAN_BOXED(3192464312,32,FLEN) +NAN_BOXED(3192464312,32,FLEN) +NAN_BOXED(3192464312,32,FLEN) +NAN_BOXED(3192464312,32,FLEN) +NAN_BOXED(3192464312,32,FLEN) +NAN_BOXED(3192464313,32,FLEN) +NAN_BOXED(3192464313,32,FLEN) +NAN_BOXED(3192464313,32,FLEN) +NAN_BOXED(3192464313,32,FLEN) +NAN_BOXED(3192464313,32,FLEN) +NAN_BOXED(3192464314,32,FLEN) +NAN_BOXED(3192464314,32,FLEN) +NAN_BOXED(3192464314,32,FLEN) +NAN_BOXED(3192464314,32,FLEN) +NAN_BOXED(3192464314,32,FLEN) +NAN_BOXED(3192464315,32,FLEN) +NAN_BOXED(3192464315,32,FLEN) +NAN_BOXED(3192464315,32,FLEN) +NAN_BOXED(3192464315,32,FLEN) +NAN_BOXED(3192464315,32,FLEN) +NAN_BOXED(3192464316,32,FLEN) +NAN_BOXED(3192464316,32,FLEN) +NAN_BOXED(3192464316,32,FLEN) +NAN_BOXED(3192464316,32,FLEN) +NAN_BOXED(3192464316,32,FLEN) +NAN_BOXED(3192464317,32,FLEN) +NAN_BOXED(3192464317,32,FLEN) +NAN_BOXED(3192464317,32,FLEN) +NAN_BOXED(3192464317,32,FLEN) +NAN_BOXED(3192464317,32,FLEN) +NAN_BOXED(3192464318,32,FLEN) +NAN_BOXED(3192464318,32,FLEN) +NAN_BOXED(3192464318,32,FLEN) +NAN_BOXED(3192464318,32,FLEN) +NAN_BOXED(3192464318,32,FLEN) +NAN_BOXED(3192464319,32,FLEN) +NAN_BOXED(3192464319,32,FLEN) +NAN_BOXED(3192464319,32,FLEN) +NAN_BOXED(3192464319,32,FLEN) +NAN_BOXED(3192464319,32,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 160*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.s.h_b22-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.s.h_b22-01.S new file mode 100644 index 000000000..8dfc6a638 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.s.h_b22-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Fri Sep 20 02:26:03 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.s.h.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.s.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.s.h_b22 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.s.h_b22) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f31; dest:f31; op1val:0x3249; valaddr_reg:x3; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 != rd, rs1==f29, rd==f30,fs1 == 0 and fe1 == 0x0d and fm1 == 0x1b7 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f29; dest:f30; op1val:0x35b7; valaddr_reg:x3; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f30, f29, 0, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x0e and fm1 == 0x24f and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f30; dest:f29; op1val:0x3a4f; valaddr_reg:x3; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f29, f30, 0, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x0f and fm1 == 0x0d3 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f27; dest:f28; op1val:0x3cd3; valaddr_reg:x3; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f28, f27, 0, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x10 and fm1 == 0x340 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f28; dest:f27; op1val:0x4340; valaddr_reg:x3; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f27, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 0 and fe1 == 0x11 and fm1 == 0x34b and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f25; dest:f26; op1val:0x474b; valaddr_reg:x3; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 1 and fe1 == 0x07 and fm1 == 0x29d and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f26; dest:f25; op1val:0x9e9d; valaddr_reg:x3; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f25, f26, 0, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 0 and fe1 == 0x04 and fm1 == 0x023 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f23; dest:f24; op1val:0x1023; valaddr_reg:x3; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f24, f23, 0, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23, +/* opcode: fcvt.s.h ; op1:f24; dest:f23; op1val:0x0; valaddr_reg:x3; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f23, f24, 0, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22, +/* opcode: fcvt.s.h ; op1:f21; dest:f22; op1val:0x0; valaddr_reg:x3; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f22, f21, 0, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21, +/* opcode: fcvt.s.h ; op1:f22; dest:f21; op1val:0x0; valaddr_reg:x3; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20, +/* opcode: fcvt.s.h ; op1:f19; dest:f20; op1val:0x0; valaddr_reg:x3; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f20, f19, 0, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19, +/* opcode: fcvt.s.h ; op1:f20; dest:f19; op1val:0x0; valaddr_reg:x3; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f19, f20, 0, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18, +/* opcode: fcvt.s.h ; op1:f17; dest:f18; op1val:0x0; valaddr_reg:x3; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f18, f17, 0, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17, +/* opcode: fcvt.s.h ; op1:f18; dest:f17; op1val:0x0; valaddr_reg:x3; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f17, f18, 0, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16, +/* opcode: fcvt.s.h ; op1:f15; dest:f16; op1val:0x0; valaddr_reg:x3; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15, +/* opcode: fcvt.s.h ; op1:f16; dest:f15; op1val:0x0; valaddr_reg:x3; +val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f15, f16, 0, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14, +/* opcode: fcvt.s.h ; op1:f13; dest:f14; op1val:0x0; valaddr_reg:x3; +val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f14, f13, 0, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13, +/* opcode: fcvt.s.h ; op1:f14; dest:f13; op1val:0x0; valaddr_reg:x3; +val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f13, f14, 0, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12, +/* opcode: fcvt.s.h ; op1:f11; dest:f12; op1val:0x0; valaddr_reg:x3; +val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f12, f11, 0, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11, +/* opcode: fcvt.s.h ; op1:f12; dest:f11; op1val:0x0; valaddr_reg:x3; +val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10, +/* opcode: fcvt.s.h ; op1:f9; dest:f10; op1val:0x0; valaddr_reg:x3; +val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f10, f9, 0, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9, +/* opcode: fcvt.s.h ; op1:f10; dest:f9; op1val:0x0; valaddr_reg:x3; +val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f9, f10, 0, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8, +/* opcode: fcvt.s.h ; op1:f7; dest:f8; op1val:0x0; valaddr_reg:x3; +val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f8, f7, 0, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7, +/* opcode: fcvt.s.h ; op1:f8; dest:f7; op1val:0x0; valaddr_reg:x3; +val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f7, f8, 0, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6, +/* opcode: fcvt.s.h ; op1:f5; dest:f6; op1val:0x0; valaddr_reg:x3; +val_offset:25*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5, +/* opcode: fcvt.s.h ; op1:f6; dest:f5; op1val:0x0; valaddr_reg:x3; +val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f5, f6, 0, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4, +/* opcode: fcvt.s.h ; op1:f3; dest:f4; op1val:0x0; valaddr_reg:x3; +val_offset:27*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f4, f3, 0, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3, +/* opcode: fcvt.s.h ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3; +val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f3, f4, 0, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2, +/* opcode: fcvt.s.h ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3; +val_offset:29*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f2, f1, 0, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1, +/* opcode: fcvt.s.h ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3; +val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0, +/* opcode: fcvt.s.h ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:31*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f31, f0, 0, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0, +/* opcode: fcvt.s.h ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3; +val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f0, f31, 0, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(12873,16,FLEN) +NAN_BOXED(13751,16,FLEN) +NAN_BOXED(14927,16,FLEN) +NAN_BOXED(15571,16,FLEN) +NAN_BOXED(17216,16,FLEN) +NAN_BOXED(18251,16,FLEN) +NAN_BOXED(40605,16,FLEN) +NAN_BOXED(4131,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.s.h_b23-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.s.h_b23-01.S new file mode 100644 index 000000000..50b7de7b4 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.s.h_b23-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Fri Sep 20 02:26:03 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.s.h.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.s.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.s.h_b23 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.s.h_b23) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f31; dest:f31; op1val:0x77fc; valaddr_reg:x3; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 != rd, rs1==f29, rd==f30,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f29; dest:f30; op1val:0x77fc; valaddr_reg:x3; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f30, f29, 32, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f30; dest:f29; op1val:0x77fc; valaddr_reg:x3; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f29, f30, 64, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f27; dest:f28; op1val:0x77fc; valaddr_reg:x3; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f28, f27, 96, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f28; dest:f27; op1val:0x77fc; valaddr_reg:x3; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f27, f28, 128, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fd and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f25; dest:f26; op1val:0x77fd; valaddr_reg:x3; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fd and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f26; dest:f25; op1val:0x77fd; valaddr_reg:x3; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f25, f26, 32, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fd and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f23; dest:f24; op1val:0x77fd; valaddr_reg:x3; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f24, f23, 64, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fd and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f24; dest:f23; op1val:0x77fd; valaddr_reg:x3; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f23, f24, 96, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fd and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f21; dest:f22; op1val:0x77fd; valaddr_reg:x3; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f22, f21, 128, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f22; dest:f21; op1val:0x77fe; valaddr_reg:x3; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f19; dest:f20; op1val:0x77fe; valaddr_reg:x3; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f20, f19, 32, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f20; dest:f19; op1val:0x77fe; valaddr_reg:x3; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f19, f20, 64, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f17; dest:f18; op1val:0x77fe; valaddr_reg:x3; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f18, f17, 96, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f18; dest:f17; op1val:0x77fe; valaddr_reg:x3; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f17, f18, 128, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f15; dest:f16; op1val:0x77ff; valaddr_reg:x3; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f16; dest:f15; op1val:0x77ff; valaddr_reg:x3; +val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f15, f16, 32, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f13; dest:f14; op1val:0x77ff; valaddr_reg:x3; +val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f14, f13, 64, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f14; dest:f13; op1val:0x77ff; valaddr_reg:x3; +val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f13, f14, 96, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f11; dest:f12; op1val:0x77ff; valaddr_reg:x3; +val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f12, f11, 128, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 0 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f12; dest:f11; op1val:0x7800; valaddr_reg:x3; +val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10,fs1 == 0 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f9; dest:f10; op1val:0x7800; valaddr_reg:x3; +val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f10, f9, 32, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9,fs1 == 0 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f10; dest:f9; op1val:0x7800; valaddr_reg:x3; +val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f9, f10, 64, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8,fs1 == 0 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f7; dest:f8; op1val:0x7800; valaddr_reg:x3; +val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f8, f7, 96, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7,fs1 == 0 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f8; dest:f7; op1val:0x7800; valaddr_reg:x3; +val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f7, f8, 128, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f5; dest:f6; op1val:0x7801; valaddr_reg:x3; +val_offset:25*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f6; dest:f5; op1val:0x7801; valaddr_reg:x3; +val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f5, f6, 32, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f3; dest:f4; op1val:0x7801; valaddr_reg:x3; +val_offset:27*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f4, f3, 64, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f4; dest:f3; op1val:0x7801; valaddr_reg:x3; +val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f3, f4, 96, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f1; dest:f2; op1val:0x7801; valaddr_reg:x3; +val_offset:29*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f2, f1, 128, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f2; dest:f1; op1val:0x7802; valaddr_reg:x3; +val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0,fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f0; dest:f31; op1val:0x7802; valaddr_reg:x3; +val_offset:31*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f31, f0, 32, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0,fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f31; dest:f0; op1val:0x7802; valaddr_reg:x3; +val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f0, f31, 64, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(30716,16,FLEN) +NAN_BOXED(30716,16,FLEN) +NAN_BOXED(30716,16,FLEN) +NAN_BOXED(30716,16,FLEN) +NAN_BOXED(30716,16,FLEN) +NAN_BOXED(30717,16,FLEN) +NAN_BOXED(30717,16,FLEN) +NAN_BOXED(30717,16,FLEN) +NAN_BOXED(30717,16,FLEN) +NAN_BOXED(30717,16,FLEN) +NAN_BOXED(30718,16,FLEN) +NAN_BOXED(30718,16,FLEN) +NAN_BOXED(30718,16,FLEN) +NAN_BOXED(30718,16,FLEN) +NAN_BOXED(30718,16,FLEN) +NAN_BOXED(30719,16,FLEN) +NAN_BOXED(30719,16,FLEN) +NAN_BOXED(30719,16,FLEN) +NAN_BOXED(30719,16,FLEN) +NAN_BOXED(30719,16,FLEN) +NAN_BOXED(30720,16,FLEN) +NAN_BOXED(30720,16,FLEN) +NAN_BOXED(30720,16,FLEN) +NAN_BOXED(30720,16,FLEN) +NAN_BOXED(30720,16,FLEN) +NAN_BOXED(30721,16,FLEN) +NAN_BOXED(30721,16,FLEN) +NAN_BOXED(30721,16,FLEN) +NAN_BOXED(30721,16,FLEN) +NAN_BOXED(30721,16,FLEN) +NAN_BOXED(30722,16,FLEN) +NAN_BOXED(30722,16,FLEN) +NAN_BOXED(30722,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.s.h_b24-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.s.h_b24-01.S new file mode 100644 index 000000000..d11e5d2cf --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.s.h_b24-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Fri Sep 20 02:26:03 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.s.h.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.s.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.s.h_b24 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.s.h_b24) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f31; dest:f31; op1val:0x2e66; valaddr_reg:x3; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 != rd, rs1==f29, rd==f30,fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f29; dest:f30; op1val:0x2e66; valaddr_reg:x3; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f30, f29, 32, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f30; dest:f29; op1val:0x2e66; valaddr_reg:x3; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f29, f30, 64, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f27; dest:f28; op1val:0x2e66; valaddr_reg:x3; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f28, f27, 96, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f28; dest:f27; op1val:0x2e66; valaddr_reg:x3; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f27, f28, 128, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f25; dest:f26; op1val:0xbc66; valaddr_reg:x3; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f26; dest:f25; op1val:0xbc66; valaddr_reg:x3; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f25, f26, 32, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f23; dest:f24; op1val:0xbc66; valaddr_reg:x3; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f24, f23, 64, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f24; dest:f23; op1val:0xbc66; valaddr_reg:x3; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f23, f24, 96, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f21; dest:f22; op1val:0xbc66; valaddr_reg:x3; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f22, f21, 128, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f22; dest:f21; op1val:0x3c66; valaddr_reg:x3; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f19; dest:f20; op1val:0x3c66; valaddr_reg:x3; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f20, f19, 32, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f20; dest:f19; op1val:0x3c66; valaddr_reg:x3; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f19, f20, 64, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f17; dest:f18; op1val:0x3c66; valaddr_reg:x3; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f18, f17, 96, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f18; dest:f17; op1val:0x3c66; valaddr_reg:x3; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f17, f18, 128, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f15; dest:f16; op1val:0xbbeb; valaddr_reg:x3; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f16; dest:f15; op1val:0xbbeb; valaddr_reg:x3; +val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f15, f16, 32, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f13; dest:f14; op1val:0xbbeb; valaddr_reg:x3; +val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f14, f13, 64, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f14; dest:f13; op1val:0xbbeb; valaddr_reg:x3; +val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f13, f14, 96, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f11; dest:f12; op1val:0xbbeb; valaddr_reg:x3; +val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f12, f11, 128, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f12; dest:f11; op1val:0xaf0a; valaddr_reg:x3; +val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10,fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f9; dest:f10; op1val:0xaf0a; valaddr_reg:x3; +val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f10, f9, 32, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9,fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f10; dest:f9; op1val:0xaf0a; valaddr_reg:x3; +val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f9, f10, 64, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8,fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f7; dest:f8; op1val:0xaf0a; valaddr_reg:x3; +val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f8, f7, 96, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7,fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f8; dest:f7; op1val:0xaf0a; valaddr_reg:x3; +val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f7, f8, 128, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f5; dest:f6; op1val:0xf0; valaddr_reg:x3; +val_offset:25*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f6; dest:f5; op1val:0xf0; valaddr_reg:x3; +val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f5, f6, 32, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f3; dest:f4; op1val:0xf0; valaddr_reg:x3; +val_offset:27*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f4, f3, 64, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f4; dest:f3; op1val:0xf0; valaddr_reg:x3; +val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f3, f4, 96, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f1; dest:f2; op1val:0xf0; valaddr_reg:x3; +val_offset:29*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f2, f1, 128, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1,fs1 == 1 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f2; dest:f1; op1val:0xa11e; valaddr_reg:x3; +val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0,fs1 == 1 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f0; dest:f31; op1val:0xa11e; valaddr_reg:x3; +val_offset:31*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f31, f0, 32, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0,fs1 == 1 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f31; dest:f0; op1val:0xa11e; valaddr_reg:x3; +val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f0, f31, 64, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(11878,16,FLEN) +NAN_BOXED(11878,16,FLEN) +NAN_BOXED(11878,16,FLEN) +NAN_BOXED(11878,16,FLEN) +NAN_BOXED(11878,16,FLEN) +NAN_BOXED(48230,16,FLEN) +NAN_BOXED(48230,16,FLEN) +NAN_BOXED(48230,16,FLEN) +NAN_BOXED(48230,16,FLEN) +NAN_BOXED(48230,16,FLEN) +NAN_BOXED(15462,16,FLEN) +NAN_BOXED(15462,16,FLEN) +NAN_BOXED(15462,16,FLEN) +NAN_BOXED(15462,16,FLEN) +NAN_BOXED(15462,16,FLEN) +NAN_BOXED(48107,16,FLEN) +NAN_BOXED(48107,16,FLEN) +NAN_BOXED(48107,16,FLEN) +NAN_BOXED(48107,16,FLEN) +NAN_BOXED(48107,16,FLEN) +NAN_BOXED(44810,16,FLEN) +NAN_BOXED(44810,16,FLEN) +NAN_BOXED(44810,16,FLEN) +NAN_BOXED(44810,16,FLEN) +NAN_BOXED(44810,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(41246,16,FLEN) +NAN_BOXED(41246,16,FLEN) +NAN_BOXED(41246,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.s.h_b27-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.s.h_b27-01.S new file mode 100644 index 000000000..55fd97f01 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.s.h_b27-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Fri Sep 20 02:26:03 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.s.h.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.s.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.s.h_b27 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.s.h_b27) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f31; dest:f31; op1val:0x7c01; valaddr_reg:x3; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 != rd, rs1==f29, rd==f30,fs1 == 1 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f29; dest:f30; op1val:0xfc01; valaddr_reg:x3; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f30, f29, 0, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x1f and fm1 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f30; dest:f29; op1val:0x7d55; valaddr_reg:x3; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f29, f30, 0, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f27; dest:f28; op1val:0xfd55; valaddr_reg:x3; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f28, f27, 0, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f28; dest:f27; op1val:0x7e01; valaddr_reg:x3; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f27, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 1 and fe1 == 0x1f and fm1 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f25; dest:f26; op1val:0xfe01; valaddr_reg:x3; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x1f and fm1 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f26; dest:f25; op1val:0x7e55; valaddr_reg:x3; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f25, f26, 0, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f23; dest:f24; op1val:0xfe55; valaddr_reg:x3; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f24, f23, 0, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23, +/* opcode: fcvt.s.h ; op1:f24; dest:f23; op1val:0x0; valaddr_reg:x3; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f23, f24, 0, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22, +/* opcode: fcvt.s.h ; op1:f21; dest:f22; op1val:0x0; valaddr_reg:x3; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f22, f21, 0, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21, +/* opcode: fcvt.s.h ; op1:f22; dest:f21; op1val:0x0; valaddr_reg:x3; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20, +/* opcode: fcvt.s.h ; op1:f19; dest:f20; op1val:0x0; valaddr_reg:x3; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f20, f19, 0, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19, +/* opcode: fcvt.s.h ; op1:f20; dest:f19; op1val:0x0; valaddr_reg:x3; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f19, f20, 0, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18, +/* opcode: fcvt.s.h ; op1:f17; dest:f18; op1val:0x0; valaddr_reg:x3; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f18, f17, 0, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17, +/* opcode: fcvt.s.h ; op1:f18; dest:f17; op1val:0x0; valaddr_reg:x3; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f17, f18, 0, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16, +/* opcode: fcvt.s.h ; op1:f15; dest:f16; op1val:0x0; valaddr_reg:x3; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15, +/* opcode: fcvt.s.h ; op1:f16; dest:f15; op1val:0x0; valaddr_reg:x3; +val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f15, f16, 0, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14, +/* opcode: fcvt.s.h ; op1:f13; dest:f14; op1val:0x0; valaddr_reg:x3; +val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f14, f13, 0, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13, +/* opcode: fcvt.s.h ; op1:f14; dest:f13; op1val:0x0; valaddr_reg:x3; +val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f13, f14, 0, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12, +/* opcode: fcvt.s.h ; op1:f11; dest:f12; op1val:0x0; valaddr_reg:x3; +val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f12, f11, 0, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11, +/* opcode: fcvt.s.h ; op1:f12; dest:f11; op1val:0x0; valaddr_reg:x3; +val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10, +/* opcode: fcvt.s.h ; op1:f9; dest:f10; op1val:0x0; valaddr_reg:x3; +val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f10, f9, 0, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9, +/* opcode: fcvt.s.h ; op1:f10; dest:f9; op1val:0x0; valaddr_reg:x3; +val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f9, f10, 0, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8, +/* opcode: fcvt.s.h ; op1:f7; dest:f8; op1val:0x0; valaddr_reg:x3; +val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f8, f7, 0, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7, +/* opcode: fcvt.s.h ; op1:f8; dest:f7; op1val:0x0; valaddr_reg:x3; +val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f7, f8, 0, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6, +/* opcode: fcvt.s.h ; op1:f5; dest:f6; op1val:0x0; valaddr_reg:x3; +val_offset:25*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5, +/* opcode: fcvt.s.h ; op1:f6; dest:f5; op1val:0x0; valaddr_reg:x3; +val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f5, f6, 0, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4, +/* opcode: fcvt.s.h ; op1:f3; dest:f4; op1val:0x0; valaddr_reg:x3; +val_offset:27*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f4, f3, 0, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3, +/* opcode: fcvt.s.h ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3; +val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f3, f4, 0, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2, +/* opcode: fcvt.s.h ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3; +val_offset:29*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f2, f1, 0, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1, +/* opcode: fcvt.s.h ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3; +val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0, +/* opcode: fcvt.s.h ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:31*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f31, f0, 0, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0, +/* opcode: fcvt.s.h ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3; +val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f0, f31, 0, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(64513,16,FLEN) +NAN_BOXED(32085,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(65025,16,FLEN) +NAN_BOXED(32341,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.s.h_b28-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.s.h_b28-01.S new file mode 100644 index 000000000..a22413aaf --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.s.h_b28-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Fri Sep 20 02:26:03 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.s.h.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.s.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.s.h_b28 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.s.h_b28) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f31; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 != rd, rs1==f29, rd==f30,fs1 == 0 and fe1 == 0x0e and fm1 == 0x092 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f29; dest:f30; op1val:0x3892; valaddr_reg:x3; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f30, f29, 0, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f30; dest:f29; op1val:0x3c00; valaddr_reg:x3; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f29, f30, 0, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x0f and fm1 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f27; dest:f28; op1val:0x3d00; valaddr_reg:x3; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f28, f27, 0, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x0f and fm1 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f28; dest:f27; op1val:0x3e00; valaddr_reg:x3; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f27, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 0 and fe1 == 0x0f and fm1 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f25; dest:f26; op1val:0x3f00; valaddr_reg:x3; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x10 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f26; dest:f25; op1val:0x4000; valaddr_reg:x3; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f25, f26, 0, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 0 and fe1 == 0x10 and fm1 == 0x080 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f23; dest:f24; op1val:0x4080; valaddr_reg:x3; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f24, f23, 0, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x10 and fm1 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f24; dest:f23; op1val:0x4100; valaddr_reg:x3; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f23, f24, 0, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 0 and fe1 == 0x10 and fm1 == 0x180 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f21; dest:f22; op1val:0x4180; valaddr_reg:x3; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f22, f21, 0, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x1c and fm1 == 0x2dc and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f22; dest:f21; op1val:0x72dc; valaddr_reg:x3; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f19; dest:f20; op1val:0x77ff; valaddr_reg:x3; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f20, f19, 0, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f20; dest:f19; op1val:0x7c00; valaddr_reg:x3; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f19, f20, 0, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f17; dest:f18; op1val:0x7c01; valaddr_reg:x3; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f18, f17, 0, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f18; dest:f17; op1val:0x7e01; valaddr_reg:x3; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f17, f18, 0, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f15; dest:f16; op1val:0x8000; valaddr_reg:x3; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 1 and fe1 == 0x0d and fm1 == 0x2c0 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f16; dest:f15; op1val:0xb6c0; valaddr_reg:x3; +val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f15, f16, 0, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f13; dest:f14; op1val:0xbc00; valaddr_reg:x3; +val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f14, f13, 0, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 1 and fe1 == 0x10 and fm1 == 0x180 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f14; dest:f13; op1val:0xc180; valaddr_reg:x3; +val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f13, f14, 0, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 1 and fe1 == 0x10 and fm1 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f11; dest:f12; op1val:0xc100; valaddr_reg:x3; +val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f12, f11, 0, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 1 and fe1 == 0x10 and fm1 == 0x080 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f12; dest:f11; op1val:0xc080; valaddr_reg:x3; +val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10,fs1 == 1 and fe1 == 0x10 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f9; dest:f10; op1val:0xc000; valaddr_reg:x3; +val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f10, f9, 0, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9,fs1 == 1 and fe1 == 0x0f and fm1 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f10; dest:f9; op1val:0xbf00; valaddr_reg:x3; +val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f9, f10, 0, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8,fs1 == 1 and fe1 == 0x0f and fm1 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f7; dest:f8; op1val:0xbe00; valaddr_reg:x3; +val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f8, f7, 0, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7,fs1 == 1 and fe1 == 0x0f and fm1 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f8; dest:f7; op1val:0xbd00; valaddr_reg:x3; +val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f7, f8, 0, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6,fs1 == 1 and fe1 == 0x1d and fm1 == 0x259 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f5; dest:f6; op1val:0xf659; valaddr_reg:x3; +val_offset:25*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5,fs1 == 1 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f6; dest:f5; op1val:0xf800; valaddr_reg:x3; +val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f5, f6, 0, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4,fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f3; dest:f4; op1val:0xfc00; valaddr_reg:x3; +val_offset:27*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f4, f3, 0, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3, +/* opcode: fcvt.s.h ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3; +val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f3, f4, 0, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2, +/* opcode: fcvt.s.h ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3; +val_offset:29*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f2, f1, 0, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1, +/* opcode: fcvt.s.h ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3; +val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0, +/* opcode: fcvt.s.h ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:31*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f31, f0, 0, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0, +/* opcode: fcvt.s.h ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3; +val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f0, f31, 0, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,16,FLEN) +NAN_BOXED(14482,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15616,16,FLEN) +NAN_BOXED(15872,16,FLEN) +NAN_BOXED(16128,16,FLEN) +NAN_BOXED(16384,16,FLEN) +NAN_BOXED(16512,16,FLEN) +NAN_BOXED(16640,16,FLEN) +NAN_BOXED(16768,16,FLEN) +NAN_BOXED(29404,16,FLEN) +NAN_BOXED(30719,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(46784,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(49536,16,FLEN) +NAN_BOXED(49408,16,FLEN) +NAN_BOXED(49280,16,FLEN) +NAN_BOXED(49152,16,FLEN) +NAN_BOXED(48896,16,FLEN) +NAN_BOXED(48640,16,FLEN) +NAN_BOXED(48384,16,FLEN) +NAN_BOXED(63065,16,FLEN) +NAN_BOXED(63488,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.s.h_b29-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.s.h_b29-01.S new file mode 100644 index 000000000..18444165b --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.s.h_b29-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Fri Sep 20 02:26:03 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.s.h.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.s.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.s.h_b29 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.s.h_b29) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f31; dest:f31; op1val:0x3248; valaddr_reg:x3; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 != rd, rs1==f29, rd==f30,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f29; dest:f30; op1val:0x3248; valaddr_reg:x3; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f30, f29, 32, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f30; dest:f29; op1val:0x3248; valaddr_reg:x3; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f29, f30, 64, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f27; dest:f28; op1val:0x3248; valaddr_reg:x3; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f28, f27, 96, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f28; dest:f27; op1val:0x3248; valaddr_reg:x3; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f27, f28, 128, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f25; dest:f26; op1val:0x3249; valaddr_reg:x3; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f26; dest:f25; op1val:0x3249; valaddr_reg:x3; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f25, f26, 32, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f23; dest:f24; op1val:0x3249; valaddr_reg:x3; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f24, f23, 64, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f24; dest:f23; op1val:0x3249; valaddr_reg:x3; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f23, f24, 96, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f21; dest:f22; op1val:0x3249; valaddr_reg:x3; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f22, f21, 128, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f22; dest:f21; op1val:0x324a; valaddr_reg:x3; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f19; dest:f20; op1val:0x324a; valaddr_reg:x3; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f20, f19, 32, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f20; dest:f19; op1val:0x324a; valaddr_reg:x3; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f19, f20, 64, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f17; dest:f18; op1val:0x324a; valaddr_reg:x3; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f18, f17, 96, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f18; dest:f17; op1val:0x324a; valaddr_reg:x3; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f17, f18, 128, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f15; dest:f16; op1val:0x324b; valaddr_reg:x3; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f16; dest:f15; op1val:0x324b; valaddr_reg:x3; +val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f15, f16, 32, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f13; dest:f14; op1val:0x324b; valaddr_reg:x3; +val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f14, f13, 64, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f14; dest:f13; op1val:0x324b; valaddr_reg:x3; +val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f13, f14, 96, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f11; dest:f12; op1val:0x324b; valaddr_reg:x3; +val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f12, f11, 128, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f12; dest:f11; op1val:0x324c; valaddr_reg:x3; +val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f9; dest:f10; op1val:0x324c; valaddr_reg:x3; +val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f10, f9, 32, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f10; dest:f9; op1val:0x324c; valaddr_reg:x3; +val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f9, f10, 64, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f7; dest:f8; op1val:0x324c; valaddr_reg:x3; +val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f8, f7, 96, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f8; dest:f7; op1val:0x324c; valaddr_reg:x3; +val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f7, f8, 128, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f5; dest:f6; op1val:0x324d; valaddr_reg:x3; +val_offset:25*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f6; dest:f5; op1val:0x324d; valaddr_reg:x3; +val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f5, f6, 32, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f3; dest:f4; op1val:0x324d; valaddr_reg:x3; +val_offset:27*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f4, f3, 64, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f4; dest:f3; op1val:0x324d; valaddr_reg:x3; +val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f3, f4, 96, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f1; dest:f2; op1val:0x324d; valaddr_reg:x3; +val_offset:29*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f2, f1, 128, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f2; dest:f1; op1val:0x324e; valaddr_reg:x3; +val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f0; dest:f31; op1val:0x324e; valaddr_reg:x3; +val_offset:31*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f31, f0, 32, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f31; dest:f0; op1val:0x324e; valaddr_reg:x3; +val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f0, f31, 64, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(12872,16,FLEN) +NAN_BOXED(12872,16,FLEN) +NAN_BOXED(12872,16,FLEN) +NAN_BOXED(12872,16,FLEN) +NAN_BOXED(12872,16,FLEN) +NAN_BOXED(12873,16,FLEN) +NAN_BOXED(12873,16,FLEN) +NAN_BOXED(12873,16,FLEN) +NAN_BOXED(12873,16,FLEN) +NAN_BOXED(12873,16,FLEN) +NAN_BOXED(12874,16,FLEN) +NAN_BOXED(12874,16,FLEN) +NAN_BOXED(12874,16,FLEN) +NAN_BOXED(12874,16,FLEN) +NAN_BOXED(12874,16,FLEN) +NAN_BOXED(12875,16,FLEN) +NAN_BOXED(12875,16,FLEN) +NAN_BOXED(12875,16,FLEN) +NAN_BOXED(12875,16,FLEN) +NAN_BOXED(12875,16,FLEN) +NAN_BOXED(12876,16,FLEN) +NAN_BOXED(12876,16,FLEN) +NAN_BOXED(12876,16,FLEN) +NAN_BOXED(12876,16,FLEN) +NAN_BOXED(12876,16,FLEN) +NAN_BOXED(12877,16,FLEN) +NAN_BOXED(12877,16,FLEN) +NAN_BOXED(12877,16,FLEN) +NAN_BOXED(12877,16,FLEN) +NAN_BOXED(12877,16,FLEN) +NAN_BOXED(12878,16,FLEN) +NAN_BOXED(12878,16,FLEN) +NAN_BOXED(12878,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fadd_b1-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fadd_b1-01.S new file mode 100644 index 000000000..d0228d284 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fadd_b1-01.S @@ -0,0 +1,5934 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 05:45:15 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fadd.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fadd.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fadd_b1 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fadd_b1) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x11,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rs2 != rd, rs1==x26, rs2==x26, rd==x6,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x26; op2:x26; dest:x6; op1val:0x0; op2val:0x0; + valaddr_reg:x11; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fadd.h, x6, x26, x26, dyn, 0, 0, x11, 0*FLEN/8, x17, x1, x9) + +inst_1: +// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==x0, rs2==x12, rd==x26,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x0; op2:x12; dest:x26; op1val:0x0; op2val:0x8000; + valaddr_reg:x11; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fadd.h, x26, x0, x12, dyn, 0, 0, x11, 2*FLEN/8, x17, x1, x9) + +inst_2: +// rs1 == rs2 == rd, rs1==x19, rs2==x19, rd==x19,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x19; op2:x19; dest:x19; op1val:0x0; op2val:0x0; + valaddr_reg:x11; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fadd.h, x19, x19, x19, dyn, 0, 0, x11, 4*FLEN/8, x17, x1, x9) + +inst_3: +// rs2 == rd != rs1, rs1==x3, rs2==x23, rd==x23,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x3; op2:x23; dest:x23; op1val:0x0; op2val:0x8001; + valaddr_reg:x11; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fadd.h, x23, x3, x23, dyn, 0, 0, x11, 6*FLEN/8, x17, x1, x9) + +inst_4: +// rs1 == rd != rs2, rs1==x5, rs2==x30, rd==x5,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x5; op2:x30; dest:x5; op1val:0x0; op2val:0x2; + valaddr_reg:x11; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fadd.h, x5, x5, x30, dyn, 0, 0, x11, 8*FLEN/8, x17, x1, x9) + +inst_5: +// rs1==x31, rs2==x5, rd==x12,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x31; op2:x5; dest:x12; op1val:0x0; op2val:0x83fe; + valaddr_reg:x11; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fadd.h, x12, x31, x5, dyn, 0, 0, x11, 10*FLEN/8, x17, x1, x9) + +inst_6: +// rs1==x10, rs2==x6, rd==x13,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x10; op2:x6; dest:x13; op1val:0x0; op2val:0x3ff; + valaddr_reg:x11; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fadd.h, x13, x10, x6, dyn, 0, 0, x11, 12*FLEN/8, x17, x1, x9) + +inst_7: +// rs1==x8, rs2==x31, rd==x25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x8; op2:x31; dest:x25; op1val:0x0; op2val:0x83ff; + valaddr_reg:x11; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fadd.h, x25, x8, x31, dyn, 0, 0, x11, 14*FLEN/8, x17, x1, x9) + +inst_8: +// rs1==x16, rs2==x29, rd==x10,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x16; op2:x29; dest:x10; op1val:0x0; op2val:0x400; + valaddr_reg:x11; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fadd.h, x10, x16, x29, dyn, 0, 0, x11, 16*FLEN/8, x17, x1, x9) + +inst_9: +// rs1==x30, rs2==x4, rd==x14,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x4; dest:x14; op1val:0x0; op2val:0x8400; + valaddr_reg:x11; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fadd.h, x14, x30, x4, dyn, 0, 0, x11, 18*FLEN/8, x17, x1, x9) + +inst_10: +// rs1==x6, rs2==x7, rd==x3,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x6; op2:x7; dest:x3; op1val:0x0; op2val:0x401; + valaddr_reg:x11; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fadd.h, x3, x6, x7, dyn, 0, 0, x11, 20*FLEN/8, x17, x1, x9) + +inst_11: +// rs1==x29, rs2==x22, rd==x20,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x29; op2:x22; dest:x20; op1val:0x0; op2val:0x8455; + valaddr_reg:x11; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fadd.h, x20, x29, x22, dyn, 0, 0, x11, 22*FLEN/8, x17, x1, x9) + +inst_12: +// rs1==x15, rs2==x3, rd==x21,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x15; op2:x3; dest:x21; op1val:0x0; op2val:0x7bff; + valaddr_reg:x11; val_offset:24*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fadd.h, x21, x15, x3, dyn, 0, 0, x11, 24*FLEN/8, x17, x1, x9) + +inst_13: +// rs1==x20, rs2==x0, rd==x2,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x20; op2:x0; dest:x2; op1val:0x0; op2val:0x0; + valaddr_reg:x11; val_offset:26*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fadd.h, x2, x20, x0, dyn, 0, 0, x11, 26*FLEN/8, x17, x1, x9) +RVTEST_VALBASEUPD(x6,test_dataset_1) + +inst_14: +// rs1==x7, rs2==x24, rd==x28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x7; op2:x24; dest:x28; op1val:0x0; op2val:0x7c00; + valaddr_reg:x6; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fadd.h, x28, x7, x24, dyn, 0, 0, x6, 0*FLEN/8, x19, x1, x9) + +inst_15: +// rs1==x27, rs2==x15, rd==x17,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x27; op2:x15; dest:x17; op1val:0x0; op2val:0xfc00; + valaddr_reg:x6; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x17, x27, x15, dyn, 0, 0, x6, 2*FLEN/8, x19, x1, x5) +RVTEST_SIGBASE(x3,signature_x3_0) + +inst_16: +// rs1==x9, rs2==x16, rd==x7,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x9; op2:x16; dest:x7; op1val:0x0; op2val:0x7e00; + valaddr_reg:x6; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x7, x9, x16, dyn, 0, 0, x6, 4*FLEN/8, x19, x3, x5) + +inst_17: +// rs1==x12, rs2==x10, rd==x29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x12; op2:x10; dest:x29; op1val:0x0; op2val:0xfe00; + valaddr_reg:x6; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x29, x12, x10, dyn, 0, 0, x6, 6*FLEN/8, x19, x3, x5) + +inst_18: +// rs1==x1, rs2==x2, rd==x15,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x1; op2:x2; dest:x15; op1val:0x0; op2val:0x7e01; + valaddr_reg:x6; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x15, x1, x2, dyn, 0, 0, x6, 8*FLEN/8, x19, x3, x5) + +inst_19: +// rs1==x2, rs2==x13, rd==x9,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x2; op2:x13; dest:x9; op1val:0x0; op2val:0xfe55; + valaddr_reg:x6; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x9, x2, x13, dyn, 0, 0, x6, 10*FLEN/8, x19, x3, x5) + +inst_20: +// rs1==x28, rs2==x20, rd==x18,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x28; op2:x20; dest:x18; op1val:0x0; op2val:0x7c01; + valaddr_reg:x6; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x18, x28, x20, dyn, 0, 0, x6, 12*FLEN/8, x19, x3, x5) + +inst_21: +// rs1==x4, rs2==x18, rd==x22,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x4; op2:x18; dest:x22; op1val:0x0; op2val:0xfd55; + valaddr_reg:x6; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x22, x4, x18, dyn, 0, 0, x6, 14*FLEN/8, x19, x3, x5) + +inst_22: +// rs1==x23, rs2==x8, rd==x11,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x23; op2:x8; dest:x11; op1val:0x0; op2val:0x3c00; + valaddr_reg:x6; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x11, x23, x8, dyn, 0, 0, x6, 16*FLEN/8, x19, x3, x5) + +inst_23: +// rs1==x11, rs2==x28, rd==x16,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x11; op2:x28; dest:x16; op1val:0x0; op2val:0xbc00; + valaddr_reg:x6; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x16, x11, x28, dyn, 0, 0, x6, 18*FLEN/8, x19, x3, x5) + +inst_24: +// rs1==x17, rs2==x27, rd==x31,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x17; op2:x27; dest:x31; op1val:0x8000; op2val:0x0; + valaddr_reg:x6; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x17, x27, dyn, 0, 0, x6, 20*FLEN/8, x19, x3, x5) + +inst_25: +// rs1==x14, rs2==x1, rd==x0,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x14; op2:x1; dest:x0; op1val:0x8000; op2val:0x8000; + valaddr_reg:x6; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x0, x14, x1, dyn, 0, 0, x6, 22*FLEN/8, x19, x3, x5) +RVTEST_VALBASEUPD(x7,test_dataset_2) + +inst_26: +// rs1==x24, rs2==x17, rd==x4,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x24; op2:x17; dest:x4; op1val:0x8000; op2val:0x1; + valaddr_reg:x7; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x4, x24, x17, dyn, 0, 0, x7, 0*FLEN/8, x10, x3, x5) + +inst_27: +// rs1==x25, rs2==x9, rd==x1,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x25; op2:x9; dest:x1; op1val:0x8000; op2val:0x8001; + valaddr_reg:x7; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x1, x25, x9, dyn, 0, 0, x7, 2*FLEN/8, x10, x3, x5) + +inst_28: +// rs1==x13, rs2==x11, rd==x24,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x13; op2:x11; dest:x24; op1val:0x8000; op2val:0x2; + valaddr_reg:x7; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x24, x13, x11, dyn, 0, 0, x7, 4*FLEN/8, x10, x3, x5) + +inst_29: +// rs1==x18, rs2==x25, rd==x8,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x18; op2:x25; dest:x8; op1val:0x8000; op2val:0x83fe; + valaddr_reg:x7; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x8, x18, x25, dyn, 0, 0, x7, 6*FLEN/8, x10, x3, x5) + +inst_30: +// rs1==x22, rs2==x14, rd==x27,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x22; op2:x14; dest:x27; op1val:0x8000; op2val:0x3ff; + valaddr_reg:x7; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x27, x22, x14, dyn, 0, 0, x7, 8*FLEN/8, x10, x3, x5) + +inst_31: +// rs1==x21,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x21; op2:x14; dest:x6; op1val:0x8000; op2val:0x83ff; + valaddr_reg:x7; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x6, x21, x14, dyn, 0, 0, x7, 10*FLEN/8, x10, x3, x5) +RVTEST_SIGBASE(x1,signature_x1_2) + +inst_32: +// rs2==x21,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x16; op2:x21; dest:x20; op1val:0x8000; op2val:0x400; + valaddr_reg:x7; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x20, x16, x21, dyn, 0, 0, x7, 12*FLEN/8, x10, x1, x2) + +inst_33: +// rd==x30,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x26; op2:x13; dest:x30; op1val:0x8000; op2val:0x8400; + valaddr_reg:x7; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x30, x26, x13, dyn, 0, 0, x7, 14*FLEN/8, x10, x1, x2) + +inst_34: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x401; + valaddr_reg:x7; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 16*FLEN/8, x10, x1, x2) + +inst_35: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8455; + valaddr_reg:x7; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 18*FLEN/8, x10, x1, x2) + +inst_36: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x7bff; + valaddr_reg:x7; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 20*FLEN/8, x10, x1, x2) + +inst_37: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xfbff; + valaddr_reg:x7; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 22*FLEN/8, x10, x1, x2) + +inst_38: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x7c00; + valaddr_reg:x7; val_offset:24*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 24*FLEN/8, x10, x1, x2) + +inst_39: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xfc00; + valaddr_reg:x7; val_offset:26*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 26*FLEN/8, x10, x1, x2) + +inst_40: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x7e00; + valaddr_reg:x7; val_offset:28*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 28*FLEN/8, x10, x1, x2) + +inst_41: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xfe00; + valaddr_reg:x7; val_offset:30*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 30*FLEN/8, x10, x1, x2) + +inst_42: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x7e01; + valaddr_reg:x7; val_offset:32*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 32*FLEN/8, x10, x1, x2) + +inst_43: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xfe55; + valaddr_reg:x7; val_offset:34*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 34*FLEN/8, x10, x1, x2) + +inst_44: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x7c01; + valaddr_reg:x7; val_offset:36*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 36*FLEN/8, x10, x1, x2) + +inst_45: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xfd55; + valaddr_reg:x7; val_offset:38*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 38*FLEN/8, x10, x1, x2) + +inst_46: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x3c00; + valaddr_reg:x7; val_offset:40*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 40*FLEN/8, x10, x1, x2) + +inst_47: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xbc00; + valaddr_reg:x7; val_offset:42*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 42*FLEN/8, x10, x1, x2) + +inst_48: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x0; + valaddr_reg:x7; val_offset:44*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 44*FLEN/8, x10, x1, x2) + +inst_49: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x8000; + valaddr_reg:x7; val_offset:46*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 46*FLEN/8, x10, x1, x2) + +inst_50: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x1; + valaddr_reg:x7; val_offset:48*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 48*FLEN/8, x10, x1, x2) + +inst_51: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x8001; + valaddr_reg:x7; val_offset:50*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 50*FLEN/8, x10, x1, x2) + +inst_52: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x2; + valaddr_reg:x7; val_offset:52*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 52*FLEN/8, x10, x1, x2) + +inst_53: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x83fe; + valaddr_reg:x7; val_offset:54*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 54*FLEN/8, x10, x1, x2) + +inst_54: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x3ff; + valaddr_reg:x7; val_offset:56*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 56*FLEN/8, x10, x1, x2) + +inst_55: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x83ff; + valaddr_reg:x7; val_offset:58*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 58*FLEN/8, x10, x1, x2) + +inst_56: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x400; + valaddr_reg:x7; val_offset:60*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 60*FLEN/8, x10, x1, x2) + +inst_57: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x8400; + valaddr_reg:x7; val_offset:62*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 62*FLEN/8, x10, x1, x2) + +inst_58: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x401; + valaddr_reg:x7; val_offset:64*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 64*FLEN/8, x10, x1, x2) + +inst_59: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x8455; + valaddr_reg:x7; val_offset:66*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 66*FLEN/8, x10, x1, x2) + +inst_60: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7bff; + valaddr_reg:x7; val_offset:68*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 68*FLEN/8, x10, x1, x2) + +inst_61: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xfbff; + valaddr_reg:x7; val_offset:70*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 70*FLEN/8, x10, x1, x2) + +inst_62: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7c00; + valaddr_reg:x7; val_offset:72*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 72*FLEN/8, x10, x1, x2) + +inst_63: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xfc00; + valaddr_reg:x7; val_offset:74*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 74*FLEN/8, x10, x1, x2) + +inst_64: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7e00; + valaddr_reg:x7; val_offset:76*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 76*FLEN/8, x10, x1, x2) + +inst_65: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xfe00; + valaddr_reg:x7; val_offset:78*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 78*FLEN/8, x10, x1, x2) + +inst_66: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7e01; + valaddr_reg:x7; val_offset:80*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 80*FLEN/8, x10, x1, x2) + +inst_67: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xfe55; + valaddr_reg:x7; val_offset:82*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 82*FLEN/8, x10, x1, x2) + +inst_68: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7c01; + valaddr_reg:x7; val_offset:84*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 84*FLEN/8, x10, x1, x2) + +inst_69: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xfd55; + valaddr_reg:x7; val_offset:86*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 86*FLEN/8, x10, x1, x2) + +inst_70: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x3c00; + valaddr_reg:x7; val_offset:88*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 88*FLEN/8, x10, x1, x2) + +inst_71: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xbc00; + valaddr_reg:x7; val_offset:90*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 90*FLEN/8, x10, x1, x2) + +inst_72: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x0; + valaddr_reg:x7; val_offset:92*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 92*FLEN/8, x10, x1, x2) + +inst_73: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8000; + valaddr_reg:x7; val_offset:94*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 94*FLEN/8, x10, x1, x2) + +inst_74: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x1; + valaddr_reg:x7; val_offset:96*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 96*FLEN/8, x10, x1, x2) + +inst_75: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8001; + valaddr_reg:x7; val_offset:98*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 98*FLEN/8, x10, x1, x2) + +inst_76: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x2; + valaddr_reg:x7; val_offset:100*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 100*FLEN/8, x10, x1, x2) + +inst_77: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x83fe; + valaddr_reg:x7; val_offset:102*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 102*FLEN/8, x10, x1, x2) + +inst_78: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x3ff; + valaddr_reg:x7; val_offset:104*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 104*FLEN/8, x10, x1, x2) + +inst_79: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x83ff; + valaddr_reg:x7; val_offset:106*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 106*FLEN/8, x10, x1, x2) + +inst_80: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x400; + valaddr_reg:x7; val_offset:108*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 108*FLEN/8, x10, x1, x2) + +inst_81: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8400; + valaddr_reg:x7; val_offset:110*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 110*FLEN/8, x10, x1, x2) + +inst_82: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x401; + valaddr_reg:x7; val_offset:112*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 112*FLEN/8, x10, x1, x2) + +inst_83: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8455; + valaddr_reg:x7; val_offset:114*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 114*FLEN/8, x10, x1, x2) + +inst_84: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x7bff; + valaddr_reg:x7; val_offset:116*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 116*FLEN/8, x10, x1, x2) + +inst_85: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xfbff; + valaddr_reg:x7; val_offset:118*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 118*FLEN/8, x10, x1, x2) + +inst_86: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x7c00; + valaddr_reg:x7; val_offset:120*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 120*FLEN/8, x10, x1, x2) + +inst_87: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xfc00; + valaddr_reg:x7; val_offset:122*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 122*FLEN/8, x10, x1, x2) + +inst_88: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x7e00; + valaddr_reg:x7; val_offset:124*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 124*FLEN/8, x10, x1, x2) + +inst_89: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xfe00; + valaddr_reg:x7; val_offset:126*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 126*FLEN/8, x10, x1, x2) + +inst_90: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x7e01; + valaddr_reg:x7; val_offset:128*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 128*FLEN/8, x10, x1, x2) + +inst_91: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xfe55; + valaddr_reg:x7; val_offset:130*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 130*FLEN/8, x10, x1, x2) + +inst_92: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x7c01; + valaddr_reg:x7; val_offset:132*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 132*FLEN/8, x10, x1, x2) + +inst_93: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xfd55; + valaddr_reg:x7; val_offset:134*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 134*FLEN/8, x10, x1, x2) + +inst_94: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x3c00; + valaddr_reg:x7; val_offset:136*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 136*FLEN/8, x10, x1, x2) + +inst_95: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xbc00; + valaddr_reg:x7; val_offset:138*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 138*FLEN/8, x10, x1, x2) + +inst_96: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x0; + valaddr_reg:x7; val_offset:140*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 140*FLEN/8, x10, x1, x2) + +inst_97: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x8000; + valaddr_reg:x7; val_offset:142*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 142*FLEN/8, x10, x1, x2) + +inst_98: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x1; + valaddr_reg:x7; val_offset:144*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 144*FLEN/8, x10, x1, x2) + +inst_99: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x8001; + valaddr_reg:x7; val_offset:146*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 146*FLEN/8, x10, x1, x2) + +inst_100: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x2; + valaddr_reg:x7; val_offset:148*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 148*FLEN/8, x10, x1, x2) + +inst_101: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x83fe; + valaddr_reg:x7; val_offset:150*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 150*FLEN/8, x10, x1, x2) + +inst_102: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x3ff; + valaddr_reg:x7; val_offset:152*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 152*FLEN/8, x10, x1, x2) + +inst_103: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x83ff; + valaddr_reg:x7; val_offset:154*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 154*FLEN/8, x10, x1, x2) + +inst_104: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x400; + valaddr_reg:x7; val_offset:156*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 156*FLEN/8, x10, x1, x2) + +inst_105: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x8400; + valaddr_reg:x7; val_offset:158*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 158*FLEN/8, x10, x1, x2) + +inst_106: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x401; + valaddr_reg:x7; val_offset:160*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 160*FLEN/8, x10, x1, x2) + +inst_107: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x8455; + valaddr_reg:x7; val_offset:162*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 162*FLEN/8, x10, x1, x2) + +inst_108: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x7bff; + valaddr_reg:x7; val_offset:164*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 164*FLEN/8, x10, x1, x2) + +inst_109: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xfbff; + valaddr_reg:x7; val_offset:166*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 166*FLEN/8, x10, x1, x2) + +inst_110: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x7c00; + valaddr_reg:x7; val_offset:168*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 168*FLEN/8, x10, x1, x2) + +inst_111: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xfc00; + valaddr_reg:x7; val_offset:170*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 170*FLEN/8, x10, x1, x2) + +inst_112: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x7e00; + valaddr_reg:x7; val_offset:172*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 172*FLEN/8, x10, x1, x2) + +inst_113: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xfe00; + valaddr_reg:x7; val_offset:174*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 174*FLEN/8, x10, x1, x2) + +inst_114: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x7e01; + valaddr_reg:x7; val_offset:176*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 176*FLEN/8, x10, x1, x2) + +inst_115: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xfe55; + valaddr_reg:x7; val_offset:178*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 178*FLEN/8, x10, x1, x2) + +inst_116: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x7c01; + valaddr_reg:x7; val_offset:180*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 180*FLEN/8, x10, x1, x2) + +inst_117: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xfd55; + valaddr_reg:x7; val_offset:182*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 182*FLEN/8, x10, x1, x2) + +inst_118: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x3c00; + valaddr_reg:x7; val_offset:184*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 184*FLEN/8, x10, x1, x2) + +inst_119: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xbc00; + valaddr_reg:x7; val_offset:186*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 186*FLEN/8, x10, x1, x2) + +inst_120: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x0; + valaddr_reg:x7; val_offset:188*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 188*FLEN/8, x10, x1, x2) + +inst_121: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x8000; + valaddr_reg:x7; val_offset:190*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 190*FLEN/8, x10, x1, x2) + +inst_122: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x1; + valaddr_reg:x7; val_offset:192*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 192*FLEN/8, x10, x1, x2) + +inst_123: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x8001; + valaddr_reg:x7; val_offset:194*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 194*FLEN/8, x10, x1, x2) + +inst_124: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x2; + valaddr_reg:x7; val_offset:196*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 196*FLEN/8, x10, x1, x2) + +inst_125: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x83fe; + valaddr_reg:x7; val_offset:198*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 198*FLEN/8, x10, x1, x2) + +inst_126: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x3ff; + valaddr_reg:x7; val_offset:200*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 200*FLEN/8, x10, x1, x2) + +inst_127: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x83ff; + valaddr_reg:x7; val_offset:202*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 202*FLEN/8, x10, x1, x2) + +inst_128: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x400; + valaddr_reg:x7; val_offset:204*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 204*FLEN/8, x10, x1, x2) + +inst_129: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x8400; + valaddr_reg:x7; val_offset:206*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 206*FLEN/8, x10, x1, x2) + +inst_130: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x401; + valaddr_reg:x7; val_offset:208*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 208*FLEN/8, x10, x1, x2) + +inst_131: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x8455; + valaddr_reg:x7; val_offset:210*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 210*FLEN/8, x10, x1, x2) + +inst_132: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x7bff; + valaddr_reg:x7; val_offset:212*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 212*FLEN/8, x10, x1, x2) + +inst_133: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xfbff; + valaddr_reg:x7; val_offset:214*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 214*FLEN/8, x10, x1, x2) + +inst_134: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x7c00; + valaddr_reg:x7; val_offset:216*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 216*FLEN/8, x10, x1, x2) + +inst_135: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xfc00; + valaddr_reg:x7; val_offset:218*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 218*FLEN/8, x10, x1, x2) + +inst_136: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x7e00; + valaddr_reg:x7; val_offset:220*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 220*FLEN/8, x10, x1, x2) + +inst_137: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xfe00; + valaddr_reg:x7; val_offset:222*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 222*FLEN/8, x10, x1, x2) + +inst_138: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x7e01; + valaddr_reg:x7; val_offset:224*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 224*FLEN/8, x10, x1, x2) + +inst_139: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xfe55; + valaddr_reg:x7; val_offset:226*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 226*FLEN/8, x10, x1, x2) + +inst_140: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x7c01; + valaddr_reg:x7; val_offset:228*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 228*FLEN/8, x10, x1, x2) + +inst_141: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xfd55; + valaddr_reg:x7; val_offset:230*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 230*FLEN/8, x10, x1, x2) + +inst_142: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x3c00; + valaddr_reg:x7; val_offset:232*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 232*FLEN/8, x10, x1, x2) + +inst_143: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xbc00; + valaddr_reg:x7; val_offset:234*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 234*FLEN/8, x10, x1, x2) + +inst_144: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x0; + valaddr_reg:x7; val_offset:236*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 236*FLEN/8, x10, x1, x2) + +inst_145: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x8000; + valaddr_reg:x7; val_offset:238*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 238*FLEN/8, x10, x1, x2) + +inst_146: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x1; + valaddr_reg:x7; val_offset:240*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 240*FLEN/8, x10, x1, x2) + +inst_147: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x8001; + valaddr_reg:x7; val_offset:242*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 242*FLEN/8, x10, x1, x2) + +inst_148: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x2; + valaddr_reg:x7; val_offset:244*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 244*FLEN/8, x10, x1, x2) + +inst_149: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x83fe; + valaddr_reg:x7; val_offset:246*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 246*FLEN/8, x10, x1, x2) + +inst_150: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x3ff; + valaddr_reg:x7; val_offset:248*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 248*FLEN/8, x10, x1, x2) + +inst_151: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x83ff; + valaddr_reg:x7; val_offset:250*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 250*FLEN/8, x10, x1, x2) + +inst_152: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x400; + valaddr_reg:x7; val_offset:252*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 252*FLEN/8, x10, x1, x2) + +inst_153: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x8400; + valaddr_reg:x7; val_offset:254*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 254*FLEN/8, x10, x1, x2) + +inst_154: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x401; + valaddr_reg:x7; val_offset:256*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 256*FLEN/8, x10, x1, x2) + +inst_155: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x8455; + valaddr_reg:x7; val_offset:258*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 258*FLEN/8, x10, x1, x2) + +inst_156: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7bff; + valaddr_reg:x7; val_offset:260*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 260*FLEN/8, x10, x1, x2) + +inst_157: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xfbff; + valaddr_reg:x7; val_offset:262*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 262*FLEN/8, x10, x1, x2) + +inst_158: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7c00; + valaddr_reg:x7; val_offset:264*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 264*FLEN/8, x10, x1, x2) + +inst_159: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xfc00; + valaddr_reg:x7; val_offset:266*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 266*FLEN/8, x10, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_3) + +inst_160: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7e00; + valaddr_reg:x7; val_offset:268*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 268*FLEN/8, x10, x1, x2) + +inst_161: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xfe00; + valaddr_reg:x7; val_offset:270*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 270*FLEN/8, x10, x1, x2) + +inst_162: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7e01; + valaddr_reg:x7; val_offset:272*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 272*FLEN/8, x10, x1, x2) + +inst_163: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xfe55; + valaddr_reg:x7; val_offset:274*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 274*FLEN/8, x10, x1, x2) + +inst_164: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7c01; + valaddr_reg:x7; val_offset:276*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 276*FLEN/8, x10, x1, x2) + +inst_165: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xfd55; + valaddr_reg:x7; val_offset:278*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 278*FLEN/8, x10, x1, x2) + +inst_166: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x3c00; + valaddr_reg:x7; val_offset:280*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 280*FLEN/8, x10, x1, x2) + +inst_167: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xbc00; + valaddr_reg:x7; val_offset:282*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 282*FLEN/8, x10, x1, x2) + +inst_168: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x0; + valaddr_reg:x7; val_offset:284*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 284*FLEN/8, x10, x1, x2) + +inst_169: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8000; + valaddr_reg:x7; val_offset:286*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 286*FLEN/8, x10, x1, x2) + +inst_170: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x1; + valaddr_reg:x7; val_offset:288*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 288*FLEN/8, x10, x1, x2) + +inst_171: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8001; + valaddr_reg:x7; val_offset:290*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 290*FLEN/8, x10, x1, x2) + +inst_172: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x2; + valaddr_reg:x7; val_offset:292*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 292*FLEN/8, x10, x1, x2) + +inst_173: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x83fe; + valaddr_reg:x7; val_offset:294*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 294*FLEN/8, x10, x1, x2) + +inst_174: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x3ff; + valaddr_reg:x7; val_offset:296*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 296*FLEN/8, x10, x1, x2) + +inst_175: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x83ff; + valaddr_reg:x7; val_offset:298*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 298*FLEN/8, x10, x1, x2) + +inst_176: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x400; + valaddr_reg:x7; val_offset:300*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 300*FLEN/8, x10, x1, x2) + +inst_177: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8400; + valaddr_reg:x7; val_offset:302*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 302*FLEN/8, x10, x1, x2) + +inst_178: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x401; + valaddr_reg:x7; val_offset:304*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 304*FLEN/8, x10, x1, x2) + +inst_179: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8455; + valaddr_reg:x7; val_offset:306*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 306*FLEN/8, x10, x1, x2) + +inst_180: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x7bff; + valaddr_reg:x7; val_offset:308*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 308*FLEN/8, x10, x1, x2) + +inst_181: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xfbff; + valaddr_reg:x7; val_offset:310*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 310*FLEN/8, x10, x1, x2) + +inst_182: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x7c00; + valaddr_reg:x7; val_offset:312*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 312*FLEN/8, x10, x1, x2) + +inst_183: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xfc00; + valaddr_reg:x7; val_offset:314*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 314*FLEN/8, x10, x1, x2) + +inst_184: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x7e00; + valaddr_reg:x7; val_offset:316*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 316*FLEN/8, x10, x1, x2) + +inst_185: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xfe00; + valaddr_reg:x7; val_offset:318*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 318*FLEN/8, x10, x1, x2) + +inst_186: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x7e01; + valaddr_reg:x7; val_offset:320*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 320*FLEN/8, x10, x1, x2) + +inst_187: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xfe55; + valaddr_reg:x7; val_offset:322*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 322*FLEN/8, x10, x1, x2) + +inst_188: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x7c01; + valaddr_reg:x7; val_offset:324*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 324*FLEN/8, x10, x1, x2) + +inst_189: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xfd55; + valaddr_reg:x7; val_offset:326*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 326*FLEN/8, x10, x1, x2) + +inst_190: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x3c00; + valaddr_reg:x7; val_offset:328*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 328*FLEN/8, x10, x1, x2) + +inst_191: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xbc00; + valaddr_reg:x7; val_offset:330*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 330*FLEN/8, x10, x1, x2) + +inst_192: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x0; + valaddr_reg:x7; val_offset:332*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 332*FLEN/8, x10, x1, x2) + +inst_193: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x8000; + valaddr_reg:x7; val_offset:334*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 334*FLEN/8, x10, x1, x2) + +inst_194: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x1; + valaddr_reg:x7; val_offset:336*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 336*FLEN/8, x10, x1, x2) + +inst_195: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x8001; + valaddr_reg:x7; val_offset:338*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 338*FLEN/8, x10, x1, x2) + +inst_196: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x2; + valaddr_reg:x7; val_offset:340*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 340*FLEN/8, x10, x1, x2) + +inst_197: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x83fe; + valaddr_reg:x7; val_offset:342*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 342*FLEN/8, x10, x1, x2) + +inst_198: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x3ff; + valaddr_reg:x7; val_offset:344*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 344*FLEN/8, x10, x1, x2) + +inst_199: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x83ff; + valaddr_reg:x7; val_offset:346*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 346*FLEN/8, x10, x1, x2) + +inst_200: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x400; + valaddr_reg:x7; val_offset:348*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 348*FLEN/8, x10, x1, x2) + +inst_201: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x8400; + valaddr_reg:x7; val_offset:350*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 350*FLEN/8, x10, x1, x2) + +inst_202: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x401; + valaddr_reg:x7; val_offset:352*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 352*FLEN/8, x10, x1, x2) + +inst_203: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x8455; + valaddr_reg:x7; val_offset:354*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 354*FLEN/8, x10, x1, x2) + +inst_204: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7bff; + valaddr_reg:x7; val_offset:356*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 356*FLEN/8, x10, x1, x2) + +inst_205: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xfbff; + valaddr_reg:x7; val_offset:358*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 358*FLEN/8, x10, x1, x2) + +inst_206: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7c00; + valaddr_reg:x7; val_offset:360*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 360*FLEN/8, x10, x1, x2) + +inst_207: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xfc00; + valaddr_reg:x7; val_offset:362*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 362*FLEN/8, x10, x1, x2) + +inst_208: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7e00; + valaddr_reg:x7; val_offset:364*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 364*FLEN/8, x10, x1, x2) + +inst_209: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xfe00; + valaddr_reg:x7; val_offset:366*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 366*FLEN/8, x10, x1, x2) + +inst_210: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7e01; + valaddr_reg:x7; val_offset:368*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 368*FLEN/8, x10, x1, x2) + +inst_211: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xfe55; + valaddr_reg:x7; val_offset:370*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 370*FLEN/8, x10, x1, x2) + +inst_212: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7c01; + valaddr_reg:x7; val_offset:372*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 372*FLEN/8, x10, x1, x2) + +inst_213: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xfd55; + valaddr_reg:x7; val_offset:374*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 374*FLEN/8, x10, x1, x2) + +inst_214: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x3c00; + valaddr_reg:x7; val_offset:376*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 376*FLEN/8, x10, x1, x2) + +inst_215: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xbc00; + valaddr_reg:x7; val_offset:378*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 378*FLEN/8, x10, x1, x2) + +inst_216: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x0; + valaddr_reg:x7; val_offset:380*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 380*FLEN/8, x10, x1, x2) + +inst_217: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8000; + valaddr_reg:x7; val_offset:382*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 382*FLEN/8, x10, x1, x2) + +inst_218: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x1; + valaddr_reg:x7; val_offset:384*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 384*FLEN/8, x10, x1, x2) + +inst_219: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8001; + valaddr_reg:x7; val_offset:386*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 386*FLEN/8, x10, x1, x2) + +inst_220: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x2; + valaddr_reg:x7; val_offset:388*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 388*FLEN/8, x10, x1, x2) + +inst_221: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x83fe; + valaddr_reg:x7; val_offset:390*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 390*FLEN/8, x10, x1, x2) + +inst_222: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x3ff; + valaddr_reg:x7; val_offset:392*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 392*FLEN/8, x10, x1, x2) + +inst_223: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x83ff; + valaddr_reg:x7; val_offset:394*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 394*FLEN/8, x10, x1, x2) + +inst_224: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x400; + valaddr_reg:x7; val_offset:396*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 396*FLEN/8, x10, x1, x2) + +inst_225: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8400; + valaddr_reg:x7; val_offset:398*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 398*FLEN/8, x10, x1, x2) + +inst_226: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x401; + valaddr_reg:x7; val_offset:400*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 400*FLEN/8, x10, x1, x2) + +inst_227: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8455; + valaddr_reg:x7; val_offset:402*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 402*FLEN/8, x10, x1, x2) + +inst_228: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x7bff; + valaddr_reg:x7; val_offset:404*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 404*FLEN/8, x10, x1, x2) + +inst_229: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xfbff; + valaddr_reg:x7; val_offset:406*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 406*FLEN/8, x10, x1, x2) + +inst_230: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x7c00; + valaddr_reg:x7; val_offset:408*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 408*FLEN/8, x10, x1, x2) + +inst_231: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xfc00; + valaddr_reg:x7; val_offset:410*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 410*FLEN/8, x10, x1, x2) + +inst_232: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x7e00; + valaddr_reg:x7; val_offset:412*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 412*FLEN/8, x10, x1, x2) + +inst_233: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xfe00; + valaddr_reg:x7; val_offset:414*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 414*FLEN/8, x10, x1, x2) + +inst_234: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x7e01; + valaddr_reg:x7; val_offset:416*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 416*FLEN/8, x10, x1, x2) + +inst_235: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xfe55; + valaddr_reg:x7; val_offset:418*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 418*FLEN/8, x10, x1, x2) + +inst_236: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x7c01; + valaddr_reg:x7; val_offset:420*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 420*FLEN/8, x10, x1, x2) + +inst_237: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xfd55; + valaddr_reg:x7; val_offset:422*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 422*FLEN/8, x10, x1, x2) + +inst_238: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x3c00; + valaddr_reg:x7; val_offset:424*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 424*FLEN/8, x10, x1, x2) + +inst_239: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xbc00; + valaddr_reg:x7; val_offset:426*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 426*FLEN/8, x10, x1, x2) + +inst_240: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x0; + valaddr_reg:x7; val_offset:428*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 428*FLEN/8, x10, x1, x2) + +inst_241: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x8000; + valaddr_reg:x7; val_offset:430*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 430*FLEN/8, x10, x1, x2) + +inst_242: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x1; + valaddr_reg:x7; val_offset:432*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 432*FLEN/8, x10, x1, x2) + +inst_243: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x8001; + valaddr_reg:x7; val_offset:434*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 434*FLEN/8, x10, x1, x2) + +inst_244: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x2; + valaddr_reg:x7; val_offset:436*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 436*FLEN/8, x10, x1, x2) + +inst_245: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x83fe; + valaddr_reg:x7; val_offset:438*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 438*FLEN/8, x10, x1, x2) + +inst_246: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x3ff; + valaddr_reg:x7; val_offset:440*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 440*FLEN/8, x10, x1, x2) + +inst_247: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x83ff; + valaddr_reg:x7; val_offset:442*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 442*FLEN/8, x10, x1, x2) + +inst_248: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x400; + valaddr_reg:x7; val_offset:444*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 444*FLEN/8, x10, x1, x2) + +inst_249: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x8400; + valaddr_reg:x7; val_offset:446*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 446*FLEN/8, x10, x1, x2) + +inst_250: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x401; + valaddr_reg:x7; val_offset:448*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 448*FLEN/8, x10, x1, x2) + +inst_251: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x8455; + valaddr_reg:x7; val_offset:450*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 450*FLEN/8, x10, x1, x2) + +inst_252: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x7bff; + valaddr_reg:x7; val_offset:452*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 452*FLEN/8, x10, x1, x2) + +inst_253: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xfbff; + valaddr_reg:x7; val_offset:454*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 454*FLEN/8, x10, x1, x2) + +inst_254: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x7c00; + valaddr_reg:x7; val_offset:456*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 456*FLEN/8, x10, x1, x2) + +inst_255: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xfc00; + valaddr_reg:x7; val_offset:458*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 458*FLEN/8, x10, x1, x2) + +inst_256: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x7e00; + valaddr_reg:x7; val_offset:460*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 460*FLEN/8, x10, x1, x2) + +inst_257: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xfe00; + valaddr_reg:x7; val_offset:462*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 462*FLEN/8, x10, x1, x2) + +inst_258: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x7e01; + valaddr_reg:x7; val_offset:464*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 464*FLEN/8, x10, x1, x2) + +inst_259: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xfe55; + valaddr_reg:x7; val_offset:466*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 466*FLEN/8, x10, x1, x2) + +inst_260: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x7c01; + valaddr_reg:x7; val_offset:468*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 468*FLEN/8, x10, x1, x2) + +inst_261: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xfd55; + valaddr_reg:x7; val_offset:470*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 470*FLEN/8, x10, x1, x2) + +inst_262: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x3c00; + valaddr_reg:x7; val_offset:472*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 472*FLEN/8, x10, x1, x2) + +inst_263: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xbc00; + valaddr_reg:x7; val_offset:474*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 474*FLEN/8, x10, x1, x2) + +inst_264: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x0; + valaddr_reg:x7; val_offset:476*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 476*FLEN/8, x10, x1, x2) + +inst_265: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x8000; + valaddr_reg:x7; val_offset:478*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 478*FLEN/8, x10, x1, x2) + +inst_266: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x1; + valaddr_reg:x7; val_offset:480*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 480*FLEN/8, x10, x1, x2) + +inst_267: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x8001; + valaddr_reg:x7; val_offset:482*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 482*FLEN/8, x10, x1, x2) + +inst_268: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x2; + valaddr_reg:x7; val_offset:484*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 484*FLEN/8, x10, x1, x2) + +inst_269: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x83fe; + valaddr_reg:x7; val_offset:486*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 486*FLEN/8, x10, x1, x2) + +inst_270: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x3ff; + valaddr_reg:x7; val_offset:488*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 488*FLEN/8, x10, x1, x2) + +inst_271: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x83ff; + valaddr_reg:x7; val_offset:490*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 490*FLEN/8, x10, x1, x2) + +inst_272: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x400; + valaddr_reg:x7; val_offset:492*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 492*FLEN/8, x10, x1, x2) + +inst_273: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x8400; + valaddr_reg:x7; val_offset:494*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 494*FLEN/8, x10, x1, x2) + +inst_274: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x401; + valaddr_reg:x7; val_offset:496*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 496*FLEN/8, x10, x1, x2) + +inst_275: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x8455; + valaddr_reg:x7; val_offset:498*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 498*FLEN/8, x10, x1, x2) + +inst_276: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x7bff; + valaddr_reg:x7; val_offset:500*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 500*FLEN/8, x10, x1, x2) + +inst_277: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xfbff; + valaddr_reg:x7; val_offset:502*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 502*FLEN/8, x10, x1, x2) + +inst_278: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x7c00; + valaddr_reg:x7; val_offset:504*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 504*FLEN/8, x10, x1, x2) + +inst_279: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xfc00; + valaddr_reg:x7; val_offset:506*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 506*FLEN/8, x10, x1, x2) + +inst_280: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x7e00; + valaddr_reg:x7; val_offset:508*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 508*FLEN/8, x10, x1, x2) + +inst_281: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xfe00; + valaddr_reg:x7; val_offset:510*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 510*FLEN/8, x10, x1, x2) + +inst_282: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x7e01; + valaddr_reg:x7; val_offset:512*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 512*FLEN/8, x10, x1, x2) + +inst_283: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xfe55; + valaddr_reg:x7; val_offset:514*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 514*FLEN/8, x10, x1, x2) + +inst_284: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x7c01; + valaddr_reg:x7; val_offset:516*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 516*FLEN/8, x10, x1, x2) + +inst_285: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xfd55; + valaddr_reg:x7; val_offset:518*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 518*FLEN/8, x10, x1, x2) + +inst_286: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x3c00; + valaddr_reg:x7; val_offset:520*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 520*FLEN/8, x10, x1, x2) + +inst_287: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xbc00; + valaddr_reg:x7; val_offset:522*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 522*FLEN/8, x10, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_4) + +inst_288: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x0; + valaddr_reg:x7; val_offset:524*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 524*FLEN/8, x10, x1, x2) + +inst_289: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8000; + valaddr_reg:x7; val_offset:526*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 526*FLEN/8, x10, x1, x2) + +inst_290: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x1; + valaddr_reg:x7; val_offset:528*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 528*FLEN/8, x10, x1, x2) + +inst_291: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8001; + valaddr_reg:x7; val_offset:530*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 530*FLEN/8, x10, x1, x2) + +inst_292: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x2; + valaddr_reg:x7; val_offset:532*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 532*FLEN/8, x10, x1, x2) + +inst_293: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x83fe; + valaddr_reg:x7; val_offset:534*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 534*FLEN/8, x10, x1, x2) + +inst_294: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x3ff; + valaddr_reg:x7; val_offset:536*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 536*FLEN/8, x10, x1, x2) + +inst_295: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x83ff; + valaddr_reg:x7; val_offset:538*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 538*FLEN/8, x10, x1, x2) + +inst_296: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x400; + valaddr_reg:x7; val_offset:540*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 540*FLEN/8, x10, x1, x2) + +inst_297: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8400; + valaddr_reg:x7; val_offset:542*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 542*FLEN/8, x10, x1, x2) + +inst_298: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x401; + valaddr_reg:x7; val_offset:544*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 544*FLEN/8, x10, x1, x2) + +inst_299: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8455; + valaddr_reg:x7; val_offset:546*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 546*FLEN/8, x10, x1, x2) + +inst_300: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7bff; + valaddr_reg:x7; val_offset:548*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 548*FLEN/8, x10, x1, x2) + +inst_301: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xfbff; + valaddr_reg:x7; val_offset:550*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 550*FLEN/8, x10, x1, x2) + +inst_302: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7c00; + valaddr_reg:x7; val_offset:552*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 552*FLEN/8, x10, x1, x2) + +inst_303: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xfc00; + valaddr_reg:x7; val_offset:554*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 554*FLEN/8, x10, x1, x2) + +inst_304: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7e00; + valaddr_reg:x7; val_offset:556*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 556*FLEN/8, x10, x1, x2) + +inst_305: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xfe00; + valaddr_reg:x7; val_offset:558*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 558*FLEN/8, x10, x1, x2) + +inst_306: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7e01; + valaddr_reg:x7; val_offset:560*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 560*FLEN/8, x10, x1, x2) + +inst_307: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xfe55; + valaddr_reg:x7; val_offset:562*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 562*FLEN/8, x10, x1, x2) + +inst_308: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7c01; + valaddr_reg:x7; val_offset:564*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 564*FLEN/8, x10, x1, x2) + +inst_309: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xfd55; + valaddr_reg:x7; val_offset:566*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 566*FLEN/8, x10, x1, x2) + +inst_310: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x3c00; + valaddr_reg:x7; val_offset:568*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 568*FLEN/8, x10, x1, x2) + +inst_311: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xbc00; + valaddr_reg:x7; val_offset:570*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 570*FLEN/8, x10, x1, x2) + +inst_312: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x0; + valaddr_reg:x7; val_offset:572*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 572*FLEN/8, x10, x1, x2) + +inst_313: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8000; + valaddr_reg:x7; val_offset:574*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 574*FLEN/8, x10, x1, x2) + +inst_314: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x1; + valaddr_reg:x7; val_offset:576*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 576*FLEN/8, x10, x1, x2) + +inst_315: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8001; + valaddr_reg:x7; val_offset:578*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 578*FLEN/8, x10, x1, x2) + +inst_316: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x2; + valaddr_reg:x7; val_offset:580*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 580*FLEN/8, x10, x1, x2) + +inst_317: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x83fe; + valaddr_reg:x7; val_offset:582*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 582*FLEN/8, x10, x1, x2) + +inst_318: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x3ff; + valaddr_reg:x7; val_offset:584*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 584*FLEN/8, x10, x1, x2) + +inst_319: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x83ff; + valaddr_reg:x7; val_offset:586*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 586*FLEN/8, x10, x1, x2) + +inst_320: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x400; + valaddr_reg:x7; val_offset:588*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 588*FLEN/8, x10, x1, x2) + +inst_321: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8400; + valaddr_reg:x7; val_offset:590*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 590*FLEN/8, x10, x1, x2) + +inst_322: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x401; + valaddr_reg:x7; val_offset:592*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 592*FLEN/8, x10, x1, x2) + +inst_323: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8455; + valaddr_reg:x7; val_offset:594*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 594*FLEN/8, x10, x1, x2) + +inst_324: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7bff; + valaddr_reg:x7; val_offset:596*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 596*FLEN/8, x10, x1, x2) + +inst_325: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfbff; + valaddr_reg:x7; val_offset:598*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 598*FLEN/8, x10, x1, x2) + +inst_326: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7c00; + valaddr_reg:x7; val_offset:600*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 600*FLEN/8, x10, x1, x2) + +inst_327: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfc00; + valaddr_reg:x7; val_offset:602*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 602*FLEN/8, x10, x1, x2) + +inst_328: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7e00; + valaddr_reg:x7; val_offset:604*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 604*FLEN/8, x10, x1, x2) + +inst_329: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfe00; + valaddr_reg:x7; val_offset:606*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 606*FLEN/8, x10, x1, x2) + +inst_330: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7e01; + valaddr_reg:x7; val_offset:608*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 608*FLEN/8, x10, x1, x2) + +inst_331: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfe55; + valaddr_reg:x7; val_offset:610*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 610*FLEN/8, x10, x1, x2) + +inst_332: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7c01; + valaddr_reg:x7; val_offset:612*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 612*FLEN/8, x10, x1, x2) + +inst_333: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfd55; + valaddr_reg:x7; val_offset:614*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 614*FLEN/8, x10, x1, x2) + +inst_334: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x3c00; + valaddr_reg:x7; val_offset:616*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 616*FLEN/8, x10, x1, x2) + +inst_335: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xbc00; + valaddr_reg:x7; val_offset:618*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 618*FLEN/8, x10, x1, x2) + +inst_336: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x0; + valaddr_reg:x7; val_offset:620*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 620*FLEN/8, x10, x1, x2) + +inst_337: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x8000; + valaddr_reg:x7; val_offset:622*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 622*FLEN/8, x10, x1, x2) + +inst_338: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x1; + valaddr_reg:x7; val_offset:624*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 624*FLEN/8, x10, x1, x2) + +inst_339: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x8001; + valaddr_reg:x7; val_offset:626*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 626*FLEN/8, x10, x1, x2) + +inst_340: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x2; + valaddr_reg:x7; val_offset:628*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 628*FLEN/8, x10, x1, x2) + +inst_341: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x83fe; + valaddr_reg:x7; val_offset:630*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 630*FLEN/8, x10, x1, x2) + +inst_342: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x3ff; + valaddr_reg:x7; val_offset:632*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 632*FLEN/8, x10, x1, x2) + +inst_343: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x83ff; + valaddr_reg:x7; val_offset:634*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 634*FLEN/8, x10, x1, x2) + +inst_344: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x400; + valaddr_reg:x7; val_offset:636*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 636*FLEN/8, x10, x1, x2) + +inst_345: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x8400; + valaddr_reg:x7; val_offset:638*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 638*FLEN/8, x10, x1, x2) + +inst_346: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x401; + valaddr_reg:x7; val_offset:640*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 640*FLEN/8, x10, x1, x2) + +inst_347: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x8455; + valaddr_reg:x7; val_offset:642*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 642*FLEN/8, x10, x1, x2) + +inst_348: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x7bff; + valaddr_reg:x7; val_offset:644*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 644*FLEN/8, x10, x1, x2) + +inst_349: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xfbff; + valaddr_reg:x7; val_offset:646*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 646*FLEN/8, x10, x1, x2) + +inst_350: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x7c00; + valaddr_reg:x7; val_offset:648*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 648*FLEN/8, x10, x1, x2) + +inst_351: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xfc00; + valaddr_reg:x7; val_offset:650*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 650*FLEN/8, x10, x1, x2) + +inst_352: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x7e00; + valaddr_reg:x7; val_offset:652*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 652*FLEN/8, x10, x1, x2) + +inst_353: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xfe00; + valaddr_reg:x7; val_offset:654*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 654*FLEN/8, x10, x1, x2) + +inst_354: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x7e01; + valaddr_reg:x7; val_offset:656*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 656*FLEN/8, x10, x1, x2) + +inst_355: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xfe55; + valaddr_reg:x7; val_offset:658*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 658*FLEN/8, x10, x1, x2) + +inst_356: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x7c01; + valaddr_reg:x7; val_offset:660*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 660*FLEN/8, x10, x1, x2) + +inst_357: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xfd55; + valaddr_reg:x7; val_offset:662*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 662*FLEN/8, x10, x1, x2) + +inst_358: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x3c00; + valaddr_reg:x7; val_offset:664*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 664*FLEN/8, x10, x1, x2) + +inst_359: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xbc00; + valaddr_reg:x7; val_offset:666*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 666*FLEN/8, x10, x1, x2) + +inst_360: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x0; + valaddr_reg:x7; val_offset:668*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 668*FLEN/8, x10, x1, x2) + +inst_361: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x8000; + valaddr_reg:x7; val_offset:670*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 670*FLEN/8, x10, x1, x2) + +inst_362: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x1; + valaddr_reg:x7; val_offset:672*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 672*FLEN/8, x10, x1, x2) + +inst_363: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x8001; + valaddr_reg:x7; val_offset:674*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 674*FLEN/8, x10, x1, x2) + +inst_364: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x2; + valaddr_reg:x7; val_offset:676*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 676*FLEN/8, x10, x1, x2) + +inst_365: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x83fe; + valaddr_reg:x7; val_offset:678*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 678*FLEN/8, x10, x1, x2) + +inst_366: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x3ff; + valaddr_reg:x7; val_offset:680*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 680*FLEN/8, x10, x1, x2) + +inst_367: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x83ff; + valaddr_reg:x7; val_offset:682*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 682*FLEN/8, x10, x1, x2) + +inst_368: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x400; + valaddr_reg:x7; val_offset:684*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 684*FLEN/8, x10, x1, x2) + +inst_369: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x8400; + valaddr_reg:x7; val_offset:686*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 686*FLEN/8, x10, x1, x2) + +inst_370: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x401; + valaddr_reg:x7; val_offset:688*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 688*FLEN/8, x10, x1, x2) + +inst_371: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x8455; + valaddr_reg:x7; val_offset:690*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 690*FLEN/8, x10, x1, x2) + +inst_372: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x7bff; + valaddr_reg:x7; val_offset:692*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 692*FLEN/8, x10, x1, x2) + +inst_373: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xfbff; + valaddr_reg:x7; val_offset:694*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 694*FLEN/8, x10, x1, x2) + +inst_374: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x7c00; + valaddr_reg:x7; val_offset:696*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 696*FLEN/8, x10, x1, x2) + +inst_375: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xfc00; + valaddr_reg:x7; val_offset:698*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 698*FLEN/8, x10, x1, x2) + +inst_376: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x7e00; + valaddr_reg:x7; val_offset:700*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 700*FLEN/8, x10, x1, x2) + +inst_377: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xfe00; + valaddr_reg:x7; val_offset:702*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 702*FLEN/8, x10, x1, x2) + +inst_378: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x7e01; + valaddr_reg:x7; val_offset:704*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 704*FLEN/8, x10, x1, x2) + +inst_379: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xfe55; + valaddr_reg:x7; val_offset:706*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 706*FLEN/8, x10, x1, x2) + +inst_380: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x7c01; + valaddr_reg:x7; val_offset:708*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 708*FLEN/8, x10, x1, x2) + +inst_381: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xfd55; + valaddr_reg:x7; val_offset:710*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 710*FLEN/8, x10, x1, x2) + +inst_382: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x3c00; + valaddr_reg:x7; val_offset:712*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 712*FLEN/8, x10, x1, x2) + +inst_383: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xbc00; + valaddr_reg:x7; val_offset:714*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 714*FLEN/8, x10, x1, x2) + +inst_384: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x0; + valaddr_reg:x7; val_offset:716*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 716*FLEN/8, x10, x1, x2) + +inst_385: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x8000; + valaddr_reg:x7; val_offset:718*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 718*FLEN/8, x10, x1, x2) + +inst_386: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x1; + valaddr_reg:x7; val_offset:720*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 720*FLEN/8, x10, x1, x2) + +inst_387: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x8001; + valaddr_reg:x7; val_offset:722*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 722*FLEN/8, x10, x1, x2) + +inst_388: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x2; + valaddr_reg:x7; val_offset:724*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 724*FLEN/8, x10, x1, x2) + +inst_389: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x83fe; + valaddr_reg:x7; val_offset:726*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 726*FLEN/8, x10, x1, x2) + +inst_390: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x3ff; + valaddr_reg:x7; val_offset:728*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 728*FLEN/8, x10, x1, x2) + +inst_391: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x83ff; + valaddr_reg:x7; val_offset:730*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 730*FLEN/8, x10, x1, x2) + +inst_392: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x400; + valaddr_reg:x7; val_offset:732*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 732*FLEN/8, x10, x1, x2) + +inst_393: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x8400; + valaddr_reg:x7; val_offset:734*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 734*FLEN/8, x10, x1, x2) + +inst_394: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x401; + valaddr_reg:x7; val_offset:736*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 736*FLEN/8, x10, x1, x2) + +inst_395: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x8455; + valaddr_reg:x7; val_offset:738*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 738*FLEN/8, x10, x1, x2) + +inst_396: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x7bff; + valaddr_reg:x7; val_offset:740*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 740*FLEN/8, x10, x1, x2) + +inst_397: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xfbff; + valaddr_reg:x7; val_offset:742*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 742*FLEN/8, x10, x1, x2) + +inst_398: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x7c00; + valaddr_reg:x7; val_offset:744*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 744*FLEN/8, x10, x1, x2) + +inst_399: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xfc00; + valaddr_reg:x7; val_offset:746*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 746*FLEN/8, x10, x1, x2) + +inst_400: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x7e00; + valaddr_reg:x7; val_offset:748*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 748*FLEN/8, x10, x1, x2) + +inst_401: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xfe00; + valaddr_reg:x7; val_offset:750*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 750*FLEN/8, x10, x1, x2) + +inst_402: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x7e01; + valaddr_reg:x7; val_offset:752*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 752*FLEN/8, x10, x1, x2) + +inst_403: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xfe55; + valaddr_reg:x7; val_offset:754*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 754*FLEN/8, x10, x1, x2) + +inst_404: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x7c01; + valaddr_reg:x7; val_offset:756*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 756*FLEN/8, x10, x1, x2) + +inst_405: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xfd55; + valaddr_reg:x7; val_offset:758*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 758*FLEN/8, x10, x1, x2) + +inst_406: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x3c00; + valaddr_reg:x7; val_offset:760*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 760*FLEN/8, x10, x1, x2) + +inst_407: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xbc00; + valaddr_reg:x7; val_offset:762*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 762*FLEN/8, x10, x1, x2) + +inst_408: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x0; + valaddr_reg:x7; val_offset:764*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 764*FLEN/8, x10, x1, x2) + +inst_409: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x8000; + valaddr_reg:x7; val_offset:766*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 766*FLEN/8, x10, x1, x2) + +inst_410: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x1; + valaddr_reg:x7; val_offset:768*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 768*FLEN/8, x10, x1, x2) + +inst_411: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x8001; + valaddr_reg:x7; val_offset:770*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 770*FLEN/8, x10, x1, x2) + +inst_412: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x2; + valaddr_reg:x7; val_offset:772*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 772*FLEN/8, x10, x1, x2) + +inst_413: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x83fe; + valaddr_reg:x7; val_offset:774*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 774*FLEN/8, x10, x1, x2) + +inst_414: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x3ff; + valaddr_reg:x7; val_offset:776*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 776*FLEN/8, x10, x1, x2) + +inst_415: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x83ff; + valaddr_reg:x7; val_offset:778*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 778*FLEN/8, x10, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_5) + +inst_416: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x400; + valaddr_reg:x7; val_offset:780*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 780*FLEN/8, x10, x1, x2) + +inst_417: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x8400; + valaddr_reg:x7; val_offset:782*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 782*FLEN/8, x10, x1, x2) + +inst_418: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x401; + valaddr_reg:x7; val_offset:784*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 784*FLEN/8, x10, x1, x2) + +inst_419: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x8455; + valaddr_reg:x7; val_offset:786*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 786*FLEN/8, x10, x1, x2) + +inst_420: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x7bff; + valaddr_reg:x7; val_offset:788*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 788*FLEN/8, x10, x1, x2) + +inst_421: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xfbff; + valaddr_reg:x7; val_offset:790*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 790*FLEN/8, x10, x1, x2) + +inst_422: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x7c00; + valaddr_reg:x7; val_offset:792*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 792*FLEN/8, x10, x1, x2) + +inst_423: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xfc00; + valaddr_reg:x7; val_offset:794*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 794*FLEN/8, x10, x1, x2) + +inst_424: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x7e00; + valaddr_reg:x7; val_offset:796*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 796*FLEN/8, x10, x1, x2) + +inst_425: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xfe00; + valaddr_reg:x7; val_offset:798*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 798*FLEN/8, x10, x1, x2) + +inst_426: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x7e01; + valaddr_reg:x7; val_offset:800*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 800*FLEN/8, x10, x1, x2) + +inst_427: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xfe55; + valaddr_reg:x7; val_offset:802*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 802*FLEN/8, x10, x1, x2) + +inst_428: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x7c01; + valaddr_reg:x7; val_offset:804*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 804*FLEN/8, x10, x1, x2) + +inst_429: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xfd55; + valaddr_reg:x7; val_offset:806*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 806*FLEN/8, x10, x1, x2) + +inst_430: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x3c00; + valaddr_reg:x7; val_offset:808*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 808*FLEN/8, x10, x1, x2) + +inst_431: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xbc00; + valaddr_reg:x7; val_offset:810*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 810*FLEN/8, x10, x1, x2) + +inst_432: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x0; + valaddr_reg:x7; val_offset:812*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 812*FLEN/8, x10, x1, x2) + +inst_433: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x8000; + valaddr_reg:x7; val_offset:814*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 814*FLEN/8, x10, x1, x2) + +inst_434: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x1; + valaddr_reg:x7; val_offset:816*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 816*FLEN/8, x10, x1, x2) + +inst_435: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x8001; + valaddr_reg:x7; val_offset:818*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 818*FLEN/8, x10, x1, x2) + +inst_436: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x2; + valaddr_reg:x7; val_offset:820*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 820*FLEN/8, x10, x1, x2) + +inst_437: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x83fe; + valaddr_reg:x7; val_offset:822*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 822*FLEN/8, x10, x1, x2) + +inst_438: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x3ff; + valaddr_reg:x7; val_offset:824*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 824*FLEN/8, x10, x1, x2) + +inst_439: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x83ff; + valaddr_reg:x7; val_offset:826*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 826*FLEN/8, x10, x1, x2) + +inst_440: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x400; + valaddr_reg:x7; val_offset:828*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 828*FLEN/8, x10, x1, x2) + +inst_441: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x8400; + valaddr_reg:x7; val_offset:830*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 830*FLEN/8, x10, x1, x2) + +inst_442: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x401; + valaddr_reg:x7; val_offset:832*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 832*FLEN/8, x10, x1, x2) + +inst_443: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x8455; + valaddr_reg:x7; val_offset:834*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 834*FLEN/8, x10, x1, x2) + +inst_444: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x7bff; + valaddr_reg:x7; val_offset:836*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 836*FLEN/8, x10, x1, x2) + +inst_445: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xfbff; + valaddr_reg:x7; val_offset:838*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 838*FLEN/8, x10, x1, x2) + +inst_446: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x7c00; + valaddr_reg:x7; val_offset:840*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 840*FLEN/8, x10, x1, x2) + +inst_447: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xfc00; + valaddr_reg:x7; val_offset:842*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 842*FLEN/8, x10, x1, x2) + +inst_448: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x7e00; + valaddr_reg:x7; val_offset:844*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 844*FLEN/8, x10, x1, x2) + +inst_449: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xfe00; + valaddr_reg:x7; val_offset:846*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 846*FLEN/8, x10, x1, x2) + +inst_450: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x7e01; + valaddr_reg:x7; val_offset:848*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 848*FLEN/8, x10, x1, x2) + +inst_451: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xfe55; + valaddr_reg:x7; val_offset:850*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 850*FLEN/8, x10, x1, x2) + +inst_452: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x7c01; + valaddr_reg:x7; val_offset:852*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 852*FLEN/8, x10, x1, x2) + +inst_453: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xfd55; + valaddr_reg:x7; val_offset:854*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 854*FLEN/8, x10, x1, x2) + +inst_454: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x3c00; + valaddr_reg:x7; val_offset:856*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 856*FLEN/8, x10, x1, x2) + +inst_455: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xbc00; + valaddr_reg:x7; val_offset:858*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 858*FLEN/8, x10, x1, x2) + +inst_456: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x0; + valaddr_reg:x7; val_offset:860*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 860*FLEN/8, x10, x1, x2) + +inst_457: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x8000; + valaddr_reg:x7; val_offset:862*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 862*FLEN/8, x10, x1, x2) + +inst_458: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x1; + valaddr_reg:x7; val_offset:864*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 864*FLEN/8, x10, x1, x2) + +inst_459: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x8001; + valaddr_reg:x7; val_offset:866*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 866*FLEN/8, x10, x1, x2) + +inst_460: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x2; + valaddr_reg:x7; val_offset:868*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 868*FLEN/8, x10, x1, x2) + +inst_461: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x83fe; + valaddr_reg:x7; val_offset:870*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 870*FLEN/8, x10, x1, x2) + +inst_462: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x3ff; + valaddr_reg:x7; val_offset:872*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 872*FLEN/8, x10, x1, x2) + +inst_463: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x83ff; + valaddr_reg:x7; val_offset:874*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 874*FLEN/8, x10, x1, x2) + +inst_464: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x400; + valaddr_reg:x7; val_offset:876*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 876*FLEN/8, x10, x1, x2) + +inst_465: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x8400; + valaddr_reg:x7; val_offset:878*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 878*FLEN/8, x10, x1, x2) + +inst_466: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x401; + valaddr_reg:x7; val_offset:880*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 880*FLEN/8, x10, x1, x2) + +inst_467: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x8455; + valaddr_reg:x7; val_offset:882*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 882*FLEN/8, x10, x1, x2) + +inst_468: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x7bff; + valaddr_reg:x7; val_offset:884*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 884*FLEN/8, x10, x1, x2) + +inst_469: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xfbff; + valaddr_reg:x7; val_offset:886*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 886*FLEN/8, x10, x1, x2) + +inst_470: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x7c00; + valaddr_reg:x7; val_offset:888*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 888*FLEN/8, x10, x1, x2) + +inst_471: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xfc00; + valaddr_reg:x7; val_offset:890*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 890*FLEN/8, x10, x1, x2) + +inst_472: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x7e00; + valaddr_reg:x7; val_offset:892*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 892*FLEN/8, x10, x1, x2) + +inst_473: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xfe00; + valaddr_reg:x7; val_offset:894*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 894*FLEN/8, x10, x1, x2) + +inst_474: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x7e01; + valaddr_reg:x7; val_offset:896*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 896*FLEN/8, x10, x1, x2) + +inst_475: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xfe55; + valaddr_reg:x7; val_offset:898*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 898*FLEN/8, x10, x1, x2) + +inst_476: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x7c01; + valaddr_reg:x7; val_offset:900*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 900*FLEN/8, x10, x1, x2) + +inst_477: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xfd55; + valaddr_reg:x7; val_offset:902*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 902*FLEN/8, x10, x1, x2) + +inst_478: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x3c00; + valaddr_reg:x7; val_offset:904*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 904*FLEN/8, x10, x1, x2) + +inst_479: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xbc00; + valaddr_reg:x7; val_offset:906*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 906*FLEN/8, x10, x1, x2) + +inst_480: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x0; + valaddr_reg:x7; val_offset:908*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 908*FLEN/8, x10, x1, x2) + +inst_481: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x8000; + valaddr_reg:x7; val_offset:910*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 910*FLEN/8, x10, x1, x2) + +inst_482: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x1; + valaddr_reg:x7; val_offset:912*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 912*FLEN/8, x10, x1, x2) + +inst_483: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x8001; + valaddr_reg:x7; val_offset:914*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 914*FLEN/8, x10, x1, x2) + +inst_484: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x2; + valaddr_reg:x7; val_offset:916*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 916*FLEN/8, x10, x1, x2) + +inst_485: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x83fe; + valaddr_reg:x7; val_offset:918*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 918*FLEN/8, x10, x1, x2) + +inst_486: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x3ff; + valaddr_reg:x7; val_offset:920*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 920*FLEN/8, x10, x1, x2) + +inst_487: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x83ff; + valaddr_reg:x7; val_offset:922*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 922*FLEN/8, x10, x1, x2) + +inst_488: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x400; + valaddr_reg:x7; val_offset:924*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 924*FLEN/8, x10, x1, x2) + +inst_489: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x8400; + valaddr_reg:x7; val_offset:926*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 926*FLEN/8, x10, x1, x2) + +inst_490: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x401; + valaddr_reg:x7; val_offset:928*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 928*FLEN/8, x10, x1, x2) + +inst_491: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x8455; + valaddr_reg:x7; val_offset:930*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 930*FLEN/8, x10, x1, x2) + +inst_492: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x7bff; + valaddr_reg:x7; val_offset:932*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 932*FLEN/8, x10, x1, x2) + +inst_493: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xfbff; + valaddr_reg:x7; val_offset:934*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 934*FLEN/8, x10, x1, x2) + +inst_494: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x7c00; + valaddr_reg:x7; val_offset:936*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 936*FLEN/8, x10, x1, x2) + +inst_495: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xfc00; + valaddr_reg:x7; val_offset:938*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 938*FLEN/8, x10, x1, x2) + +inst_496: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x7e00; + valaddr_reg:x7; val_offset:940*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 940*FLEN/8, x10, x1, x2) + +inst_497: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xfe00; + valaddr_reg:x7; val_offset:942*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 942*FLEN/8, x10, x1, x2) + +inst_498: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x7e01; + valaddr_reg:x7; val_offset:944*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 944*FLEN/8, x10, x1, x2) + +inst_499: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xfe55; + valaddr_reg:x7; val_offset:946*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 946*FLEN/8, x10, x1, x2) + +inst_500: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x7c01; + valaddr_reg:x7; val_offset:948*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 948*FLEN/8, x10, x1, x2) + +inst_501: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xfd55; + valaddr_reg:x7; val_offset:950*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 950*FLEN/8, x10, x1, x2) + +inst_502: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x3c00; + valaddr_reg:x7; val_offset:952*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 952*FLEN/8, x10, x1, x2) + +inst_503: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xbc00; + valaddr_reg:x7; val_offset:954*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 954*FLEN/8, x10, x1, x2) + +inst_504: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x0; + valaddr_reg:x7; val_offset:956*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 956*FLEN/8, x10, x1, x2) + +inst_505: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x8000; + valaddr_reg:x7; val_offset:958*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 958*FLEN/8, x10, x1, x2) + +inst_506: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x1; + valaddr_reg:x7; val_offset:960*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 960*FLEN/8, x10, x1, x2) + +inst_507: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x8001; + valaddr_reg:x7; val_offset:962*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 962*FLEN/8, x10, x1, x2) + +inst_508: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x2; + valaddr_reg:x7; val_offset:964*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 964*FLEN/8, x10, x1, x2) + +inst_509: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x83fe; + valaddr_reg:x7; val_offset:966*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 966*FLEN/8, x10, x1, x2) + +inst_510: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x3ff; + valaddr_reg:x7; val_offset:968*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 968*FLEN/8, x10, x1, x2) + +inst_511: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x83ff; + valaddr_reg:x7; val_offset:970*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 970*FLEN/8, x10, x1, x2) + +inst_512: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x400; + valaddr_reg:x7; val_offset:972*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 972*FLEN/8, x10, x1, x2) + +inst_513: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x8400; + valaddr_reg:x7; val_offset:974*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 974*FLEN/8, x10, x1, x2) + +inst_514: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x401; + valaddr_reg:x7; val_offset:976*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 976*FLEN/8, x10, x1, x2) + +inst_515: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x8455; + valaddr_reg:x7; val_offset:978*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 978*FLEN/8, x10, x1, x2) + +inst_516: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x7bff; + valaddr_reg:x7; val_offset:980*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 980*FLEN/8, x10, x1, x2) + +inst_517: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xfbff; + valaddr_reg:x7; val_offset:982*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 982*FLEN/8, x10, x1, x2) + +inst_518: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x7c00; + valaddr_reg:x7; val_offset:984*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 984*FLEN/8, x10, x1, x2) + +inst_519: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xfc00; + valaddr_reg:x7; val_offset:986*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 986*FLEN/8, x10, x1, x2) + +inst_520: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x7e00; + valaddr_reg:x7; val_offset:988*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 988*FLEN/8, x10, x1, x2) + +inst_521: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xfe00; + valaddr_reg:x7; val_offset:990*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 990*FLEN/8, x10, x1, x2) + +inst_522: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x7e01; + valaddr_reg:x7; val_offset:992*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 992*FLEN/8, x10, x1, x2) + +inst_523: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xfe55; + valaddr_reg:x7; val_offset:994*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 994*FLEN/8, x10, x1, x2) + +inst_524: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x7c01; + valaddr_reg:x7; val_offset:996*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 996*FLEN/8, x10, x1, x2) + +inst_525: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xfd55; + valaddr_reg:x7; val_offset:998*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 998*FLEN/8, x10, x1, x2) + +inst_526: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x3c00; + valaddr_reg:x7; val_offset:1000*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 1000*FLEN/8, x10, x1, x2) + +inst_527: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xbc00; + valaddr_reg:x7; val_offset:1002*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 1002*FLEN/8, x10, x1, x2) + +inst_528: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x0; + valaddr_reg:x7; val_offset:1004*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 1004*FLEN/8, x10, x1, x2) + +inst_529: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x8000; + valaddr_reg:x7; val_offset:1006*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 1006*FLEN/8, x10, x1, x2) + +inst_530: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x1; + valaddr_reg:x7; val_offset:1008*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 1008*FLEN/8, x10, x1, x2) + +inst_531: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x8001; + valaddr_reg:x7; val_offset:1010*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 1010*FLEN/8, x10, x1, x2) + +inst_532: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2; + valaddr_reg:x7; val_offset:1012*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 1012*FLEN/8, x10, x1, x2) + +inst_533: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x83fe; + valaddr_reg:x7; val_offset:1014*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 1014*FLEN/8, x10, x1, x2) + +inst_534: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3ff; + valaddr_reg:x7; val_offset:1016*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 1016*FLEN/8, x10, x1, x2) + +inst_535: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x83ff; + valaddr_reg:x7; val_offset:1018*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 1018*FLEN/8, x10, x1, x2) + +inst_536: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x400; + valaddr_reg:x7; val_offset:1020*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 1020*FLEN/8, x10, x1, x2) + +inst_537: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x8400; + valaddr_reg:x7; val_offset:1022*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 1022*FLEN/8, x10, x1, x2) + +inst_538: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x401; + valaddr_reg:x7; val_offset:1024*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 1024*FLEN/8, x10, x1, x2) + +inst_539: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x8455; + valaddr_reg:x7; val_offset:1026*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 1026*FLEN/8, x10, x1, x2) + +inst_540: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7bff; + valaddr_reg:x7; val_offset:1028*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 1028*FLEN/8, x10, x1, x2) + +inst_541: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xfbff; + valaddr_reg:x7; val_offset:1030*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 1030*FLEN/8, x10, x1, x2) + +inst_542: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7c00; + valaddr_reg:x7; val_offset:1032*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 1032*FLEN/8, x10, x1, x2) + +inst_543: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xfc00; + valaddr_reg:x7; val_offset:1034*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 1034*FLEN/8, x10, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_6) + +inst_544: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7e00; + valaddr_reg:x7; val_offset:1036*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 1036*FLEN/8, x10, x1, x2) + +inst_545: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xfe00; + valaddr_reg:x7; val_offset:1038*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 1038*FLEN/8, x10, x1, x2) + +inst_546: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7e01; + valaddr_reg:x7; val_offset:1040*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 1040*FLEN/8, x10, x1, x2) + +inst_547: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xfe55; + valaddr_reg:x7; val_offset:1042*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 1042*FLEN/8, x10, x1, x2) + +inst_548: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7c01; + valaddr_reg:x7; val_offset:1044*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 1044*FLEN/8, x10, x1, x2) + +inst_549: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xfd55; + valaddr_reg:x7; val_offset:1046*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 1046*FLEN/8, x10, x1, x2) + +inst_550: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3c00; + valaddr_reg:x7; val_offset:1048*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 1048*FLEN/8, x10, x1, x2) + +inst_551: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xbc00; + valaddr_reg:x7; val_offset:1050*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 1050*FLEN/8, x10, x1, x2) + +inst_552: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x0; + valaddr_reg:x7; val_offset:1052*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 1052*FLEN/8, x10, x1, x2) + +inst_553: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x8000; + valaddr_reg:x7; val_offset:1054*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 1054*FLEN/8, x10, x1, x2) + +inst_554: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x1; + valaddr_reg:x7; val_offset:1056*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 1056*FLEN/8, x10, x1, x2) + +inst_555: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x8001; + valaddr_reg:x7; val_offset:1058*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 1058*FLEN/8, x10, x1, x2) + +inst_556: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x2; + valaddr_reg:x7; val_offset:1060*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 1060*FLEN/8, x10, x1, x2) + +inst_557: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x83fe; + valaddr_reg:x7; val_offset:1062*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 1062*FLEN/8, x10, x1, x2) + +inst_558: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x3ff; + valaddr_reg:x7; val_offset:1064*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 1064*FLEN/8, x10, x1, x2) + +inst_559: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x83ff; + valaddr_reg:x7; val_offset:1066*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 1066*FLEN/8, x10, x1, x2) + +inst_560: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x400; + valaddr_reg:x7; val_offset:1068*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 1068*FLEN/8, x10, x1, x2) + +inst_561: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x8400; + valaddr_reg:x7; val_offset:1070*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 1070*FLEN/8, x10, x1, x2) + +inst_562: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x401; + valaddr_reg:x7; val_offset:1072*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 1072*FLEN/8, x10, x1, x2) + +inst_563: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x8455; + valaddr_reg:x7; val_offset:1074*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 1074*FLEN/8, x10, x1, x2) + +inst_564: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x7bff; + valaddr_reg:x7; val_offset:1076*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 1076*FLEN/8, x10, x1, x2) + +inst_565: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xfbff; + valaddr_reg:x7; val_offset:1078*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 1078*FLEN/8, x10, x1, x2) + +inst_566: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x7c00; + valaddr_reg:x7; val_offset:1080*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 1080*FLEN/8, x10, x1, x2) + +inst_567: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xfc00; + valaddr_reg:x7; val_offset:1082*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 1082*FLEN/8, x10, x1, x2) + +inst_568: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x7e00; + valaddr_reg:x7; val_offset:1084*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 1084*FLEN/8, x10, x1, x2) + +inst_569: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xfe00; + valaddr_reg:x7; val_offset:1086*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 1086*FLEN/8, x10, x1, x2) + +inst_570: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x7e01; + valaddr_reg:x7; val_offset:1088*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 1088*FLEN/8, x10, x1, x2) + +inst_571: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xfe55; + valaddr_reg:x7; val_offset:1090*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 1090*FLEN/8, x10, x1, x2) + +inst_572: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x7c01; + valaddr_reg:x7; val_offset:1092*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 1092*FLEN/8, x10, x1, x2) + +inst_573: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xfd55; + valaddr_reg:x7; val_offset:1094*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 1094*FLEN/8, x10, x1, x2) + +inst_574: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x3c00; + valaddr_reg:x7; val_offset:1096*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 1096*FLEN/8, x10, x1, x2) + +inst_575: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbc00; + valaddr_reg:x7; val_offset:1098*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 1098*FLEN/8, x10, x1, x2) + +inst_576: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x0; + valaddr_reg:x7; val_offset:1100*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 1100*FLEN/8, x10, x1, x2) + +inst_577: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x8000; + valaddr_reg:x7; val_offset:1102*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 1102*FLEN/8, x10, x1, x2) + +inst_578: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x1; + valaddr_reg:x7; val_offset:1104*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 1104*FLEN/8, x10, x1, x2) + +inst_579: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xfbff; + valaddr_reg:x7; val_offset:1106*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 1106*FLEN/8, x10, x1, x2) + +inst_580: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8000; + valaddr_reg:x7; val_offset:1108*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 1108*FLEN/8, x10, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(2,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(1023,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(1024,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(1025,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,16,FLEN) +test_dataset_1: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31744,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32256,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32257,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31745,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(15360,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32768,16,FLEN) +test_dataset_2: +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(2,16,FLEN) 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32*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_2: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_3: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_4: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_5: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_6: + .fill 74*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fadd_b10-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fadd_b10-01.S new file mode 100644 index 000000000..f05b19fd8 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fadd_b10-01.S @@ -0,0 +1,464 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 05:45:15 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fadd.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fadd.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fadd_b10 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fadd_b10) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x7,test_dataset_0) +RVTEST_SIGBASE(x11,signature_x11_1) + +inst_0: +// rs1 == rs2 != rd, rs1==x25, rs2==x25, rd==x23,fs1 == 0 and fe1 == 0x14 and fm1 == 0x2ee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x053 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x25; op2:x25; dest:x23; op1val:0x52ee; op2val:0x52ee; + valaddr_reg:x7; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x15 +*/ +TEST_FPRR_OP(fadd.h, x23, x25, x25, dyn, 0, 0, x7, 0*FLEN/8, x18, x11, x15) + +inst_1: +// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==x4, rs2==x3, rd==x28,fs1 == 0 and fe1 == 0x14 and fm1 == 0x2ee and fs2 == 0 and fe2 == 0x0a and fm2 == 0x262 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x4; op2:x3; dest:x28; op1val:0x52ee; op2val:0x2a62; + valaddr_reg:x7; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x15 +*/ +TEST_FPRR_OP(fadd.h, x28, x4, x3, dyn, 0, 0, x7, 2*FLEN/8, x18, x11, x15) + +inst_2: +// rs1 == rs2 == rd, rs1==x19, rs2==x19, rd==x19,fs1 == 0 and fe1 == 0x14 and fm1 == 0x2ee and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3fb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x19; op2:x19; dest:x19; op1val:0x52ee; op2val:0x52ee; + valaddr_reg:x7; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x15 +*/ +TEST_FPRR_OP(fadd.h, x19, x19, x19, dyn, 0, 0, x7, 4*FLEN/8, x18, x11, x15) + +inst_3: +// rs2 == rd != rs1, rs1==x1, rs2==x27, rd==x27,fs1 == 0 and fe1 == 0x14 and fm1 == 0x2ee and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0fd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x1; op2:x27; dest:x27; op1val:0x52ee; op2val:0x44fd; + valaddr_reg:x7; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x15 +*/ +TEST_FPRR_OP(fadd.h, x27, x1, x27, dyn, 0, 0, x7, 6*FLEN/8, x18, x11, x15) + +inst_4: +// rs1 == rd != rs2, rs1==x8, rs2==x26, rd==x8,fs1 == 0 and fe1 == 0x14 and fm1 == 0x2ee and fs2 == 0 and fe2 == 0x14 and fm2 == 0x23c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x8; op2:x26; dest:x8; op1val:0x52ee; op2val:0x523c; + valaddr_reg:x7; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x15 +*/ +TEST_FPRR_OP(fadd.h, x8, x8, x26, dyn, 0, 0, x7, 8*FLEN/8, x18, x11, x15) + +inst_5: +// rs1==x6, rs2==x22, rd==x3,fs1 == 0 and fe1 == 0x14 and fm1 == 0x2ee and fs2 == 0 and fe2 == 0x17 and fm2 == 0x3cb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x6; op2:x22; dest:x3; op1val:0x52ee; op2val:0x5fcb; + valaddr_reg:x7; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x15 +*/ +TEST_FPRR_OP(fadd.h, x3, x6, x22, dyn, 0, 0, x7, 10*FLEN/8, x18, x11, x15) + +inst_6: +// rs1==x17, rs2==x2, rd==x9, +/* opcode: fadd.h ; op1:x17; op2:x2; dest:x9; op1val:0x0; op2val:0x0; + valaddr_reg:x7; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x15 +*/ +TEST_FPRR_OP(fadd.h, x9, x17, x2, dyn, 0, 0, x7, 12*FLEN/8, x18, x11, x15) + +inst_7: +// rs1==x29, rs2==x5, rd==x17, +/* opcode: fadd.h ; op1:x29; op2:x5; dest:x17; op1val:0x0; op2val:0x0; + valaddr_reg:x7; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x15 +*/ +TEST_FPRR_OP(fadd.h, x17, x29, x5, dyn, 0, 0, x7, 14*FLEN/8, x18, x11, x15) + +inst_8: +// rs1==x3, rs2==x14, rd==x22, +/* opcode: fadd.h ; op1:x3; op2:x14; dest:x22; op1val:0x0; op2val:0x0; + valaddr_reg:x7; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x15 +*/ +TEST_FPRR_OP(fadd.h, x22, x3, x14, dyn, 0, 0, x7, 16*FLEN/8, x18, x11, x15) + +inst_9: +// rs1==x14, rs2==x12, rd==x4, +/* opcode: fadd.h ; op1:x14; op2:x12; dest:x4; op1val:0x0; op2val:0x0; + valaddr_reg:x7; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x15 +*/ +TEST_FPRR_OP(fadd.h, x4, x14, x12, dyn, 0, 0, x7, 18*FLEN/8, x18, x11, x15) + +inst_10: +// rs1==x30, rs2==x0, rd==x16, +/* opcode: fadd.h ; op1:x30; op2:x0; dest:x16; op1val:0x0; op2val:0x0; + valaddr_reg:x7; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x15 +*/ +TEST_FPRR_OP(fadd.h, x16, x30, x0, dyn, 0, 0, x7, 20*FLEN/8, x18, x11, x15) + +inst_11: +// rs1==x16, rs2==x13, rd==x10, +/* opcode: fadd.h ; op1:x16; op2:x13; dest:x10; op1val:0x0; op2val:0x0; + valaddr_reg:x7; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x15 +*/ +TEST_FPRR_OP(fadd.h, x10, x16, x13, dyn, 0, 0, x7, 22*FLEN/8, x18, x11, x15) +RVTEST_VALBASEUPD(x17,test_dataset_1) + +inst_12: +// rs1==x31, rs2==x8, rd==x29, +/* opcode: fadd.h ; op1:x31; op2:x8; dest:x29; op1val:0x0; op2val:0x0; + valaddr_reg:x17; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x15 +*/ +TEST_FPRR_OP(fadd.h, x29, x31, x8, dyn, 0, 0, x17, 0*FLEN/8, x19, x11, x15) + +inst_13: +// rs1==x2, rs2==x7, rd==x26, +/* opcode: fadd.h ; op1:x2; op2:x7; dest:x26; op1val:0x0; op2val:0x0; + valaddr_reg:x17; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x15 +*/ +TEST_FPRR_OP(fadd.h, x26, x2, x7, dyn, 0, 0, x17, 2*FLEN/8, x19, x11, x15) + +inst_14: +// rs1==x7, rs2==x29, rd==x0, +/* opcode: fadd.h ; op1:x7; op2:x29; dest:x0; op1val:0x0; op2val:0x0; + valaddr_reg:x17; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fadd.h, x0, x7, x29, dyn, 0, 0, x17, 4*FLEN/8, x19, x11, x8) + +inst_15: +// rs1==x15, rs2==x23, rd==x7, +/* opcode: fadd.h ; op1:x15; op2:x23; dest:x7; op1val:0x0; op2val:0x0; + valaddr_reg:x17; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fadd.h, x7, x15, x23, dyn, 0, 0, x17, 6*FLEN/8, x19, x11, x8) +RVTEST_SIGBASE(x3,signature_x3_0) + +inst_16: +// rs1==x13, rs2==x11, rd==x14, +/* opcode: fadd.h ; op1:x13; op2:x11; dest:x14; op1val:0x0; op2val:0x0; + valaddr_reg:x17; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fadd.h, x14, x13, x11, dyn, 0, 0, x17, 8*FLEN/8, x19, x3, x8) + +inst_17: +// rs1==x24, rs2==x15, rd==x13, +/* opcode: fadd.h ; op1:x24; op2:x15; dest:x13; op1val:0x0; op2val:0x0; + valaddr_reg:x17; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fadd.h, x13, x24, x15, dyn, 0, 0, x17, 10*FLEN/8, x19, x3, x8) + +inst_18: +// rs1==x10, rs2==x28, rd==x24, +/* opcode: fadd.h ; op1:x10; op2:x28; dest:x24; op1val:0x0; op2val:0x0; + valaddr_reg:x17; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fadd.h, x24, x10, x28, dyn, 0, 0, x17, 12*FLEN/8, x19, x3, x8) + +inst_19: +// rs1==x18, rs2==x4, rd==x11, +/* opcode: fadd.h ; op1:x18; op2:x4; dest:x11; op1val:0x0; op2val:0x0; + valaddr_reg:x17; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fadd.h, x11, x18, x4, dyn, 0, 0, x17, 14*FLEN/8, x19, x3, x8) + +inst_20: +// rs1==x28, rs2==x31, rd==x21, +/* opcode: fadd.h ; op1:x28; op2:x31; dest:x21; op1val:0x0; op2val:0x0; + valaddr_reg:x17; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fadd.h, x21, x28, x31, dyn, 0, 0, x17, 16*FLEN/8, x19, x3, x8) + +inst_21: +// rs1==x22, rs2==x21, rd==x18, +/* opcode: fadd.h ; op1:x22; op2:x21; dest:x18; op1val:0x0; op2val:0x0; + valaddr_reg:x17; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fadd.h, x18, x22, x21, dyn, 0, 0, x17, 18*FLEN/8, x19, x3, x8) + +inst_22: +// rs1==x12, rs2==x16, rd==x2, +/* opcode: fadd.h ; op1:x12; op2:x16; dest:x2; op1val:0x0; op2val:0x0; + valaddr_reg:x17; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fadd.h, x2, x12, x16, dyn, 0, 0, x17, 20*FLEN/8, x19, x3, x8) + +inst_23: +// rs1==x9, rs2==x1, rd==x6, +/* opcode: fadd.h ; op1:x9; op2:x1; dest:x6; op1val:0x0; op2val:0x0; + valaddr_reg:x17; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fadd.h, x6, x9, x1, dyn, 0, 0, x17, 22*FLEN/8, x19, x3, x8) + +inst_24: +// rs1==x5, rs2==x24, rd==x15, +/* opcode: fadd.h ; op1:x5; op2:x24; dest:x15; op1val:0x0; op2val:0x0; + valaddr_reg:x17; val_offset:24*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fadd.h, x15, x5, x24, dyn, 0, 0, x17, 24*FLEN/8, x19, x3, x8) +RVTEST_VALBASEUPD(x7,test_dataset_2) + +inst_25: +// rs1==x27, rs2==x6, rd==x1, +/* opcode: fadd.h ; op1:x27; op2:x6; dest:x1; op1val:0x0; op2val:0x0; + valaddr_reg:x7; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fadd.h, x1, x27, x6, dyn, 0, 0, x7, 0*FLEN/8, x13, x3, x8) + +inst_26: +// rs1==x21, rs2==x30, rd==x25, +/* opcode: fadd.h ; op1:x21; op2:x30; dest:x25; op1val:0x0; op2val:0x0; + valaddr_reg:x7; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fadd.h, x25, x21, x30, dyn, 0, 0, x7, 2*FLEN/8, x13, x3, x8) + +inst_27: +// rs1==x23, rs2==x10, rd==x5, +/* opcode: fadd.h ; op1:x23; op2:x10; dest:x5; op1val:0x0; op2val:0x0; + valaddr_reg:x7; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x5, x23, x10, dyn, 0, 0, x7, 4*FLEN/8, x13, x3, x4) + +inst_28: +// rs1==x26, rs2==x18, rd==x30, +/* opcode: fadd.h ; op1:x26; op2:x18; dest:x30; op1val:0x0; op2val:0x0; + valaddr_reg:x7; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x30, x26, x18, dyn, 0, 0, x7, 6*FLEN/8, x13, x3, x4) + +inst_29: +// rs1==x11, rs2==x9, rd==x12, +/* opcode: fadd.h ; op1:x11; op2:x9; dest:x12; op1val:0x0; op2val:0x0; + valaddr_reg:x7; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x12, x11, x9, dyn, 0, 0, x7, 8*FLEN/8, x13, x3, x4) + +inst_30: +// rs1==x0, rs2==x17, rd==x31, +/* opcode: fadd.h ; op1:x0; op2:x17; dest:x31; op1val:0x0; op2val:0x0; + valaddr_reg:x7; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x0, x17, dyn, 0, 0, x7, 10*FLEN/8, x13, x3, x4) + +inst_31: +// rs1==x20, +/* opcode: fadd.h ; op1:x20; op2:x16; dest:x6; op1val:0x0; op2val:0x0; + valaddr_reg:x7; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x6, x20, x16, dyn, 0, 0, x7, 12*FLEN/8, x13, x3, x4) +RVTEST_SIGBASE(x2,signature_x2_0) + +inst_32: +// rs2==x20, +/* opcode: fadd.h ; op1:x1; op2:x20; dest:x10; op1val:0x0; op2val:0x0; + valaddr_reg:x7; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x10, x1, x20, dyn, 0, 0, x7, 14*FLEN/8, x13, x2, x4) + +inst_33: +// rd==x20, +/* opcode: fadd.h ; op1:x28; op2:x17; dest:x20; op1val:0x0; op2val:0x0; + valaddr_reg:x7; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x20, x28, x17, dyn, 0, 0, x7, 16*FLEN/8, x13, x2, x4) + +inst_34: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2ee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x053 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x52ee; op2val:0x53; + valaddr_reg:x7; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 18*FLEN/8, x13, x2, x4) + +inst_35: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2ee and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3fb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x52ee; op2val:0x37fb; + valaddr_reg:x7; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x7, 20*FLEN/8, x13, x2, x4) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(21230,32,FLEN) +NAN_BOXED(21230,32,FLEN) +NAN_BOXED(21230,32,FLEN) +NAN_BOXED(10850,32,FLEN) +NAN_BOXED(21230,32,FLEN) +NAN_BOXED(21230,32,FLEN) +NAN_BOXED(21230,32,FLEN) +NAN_BOXED(17661,32,FLEN) +NAN_BOXED(21230,32,FLEN) +NAN_BOXED(21052,32,FLEN) +NAN_BOXED(21230,32,FLEN) +NAN_BOXED(24523,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +test_dataset_1: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +test_dataset_2: +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(21230,16,FLEN) +NAN_BOXED(83,16,FLEN) +NAN_BOXED(21230,16,FLEN) +NAN_BOXED(14331,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x11_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x11_1: + .fill 32*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x3_0: + .fill 32*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_0: + .fill 8*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fadd_b11-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fadd_b11-01.S new file mode 100644 index 000000000..f0e0fb30b --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fadd_b11-01.S @@ -0,0 +1,33864 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 05:45:15 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fadd.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fadd.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fadd_b11 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fadd_b11) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x1,test_dataset_0) +RVTEST_SIGBASE(x2,signature_x2_1) + +inst_0: +// rs1 == rs2 != rd, rs1==x10, rs2==x10, rd==x7,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x10; op2:x10; dest:x7; op1val:0x0; op2val:0x0; + valaddr_reg:x1; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x7, x10, x10, dyn, 0, 0, x1, 0*FLEN/8, x4, x2, x5) + +inst_1: +// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==x30, rs2==x23, rd==x9,fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x23; dest:x9; op1val:0x1; op2val:0x0; + valaddr_reg:x1; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x9, x30, x23, dyn, 0, 0, x1, 2*FLEN/8, x4, x2, x5) + +inst_2: +// rs1 == rs2 == rd, rs1==x11, rs2==x11, rd==x11,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x11; op2:x11; dest:x11; op1val:0x0; op2val:0x0; + valaddr_reg:x1; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x11, x11, x11, dyn, 0, 0, x1, 4*FLEN/8, x4, x2, x5) + +inst_3: +// rs2 == rd != rs1, rs1==x23, rs2==x15, rd==x15,fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x23; op2:x15; dest:x15; op1val:0x3ff; op2val:0x0; + valaddr_reg:x1; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x15, x23, x15, dyn, 0, 0, x1, 6*FLEN/8, x4, x2, x5) + +inst_4: +// rs1 == rd != rs2, rs1==x27, rs2==x29, rd==x27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x27; op2:x29; dest:x27; op1val:0x0; op2val:0x200; + valaddr_reg:x1; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x27, x27, x29, dyn, 0, 0, x1, 8*FLEN/8, x4, x2, x5) + +inst_5: +// rs1==x12, rs2==x25, rd==x21,fs1 == 0 and fe1 == 0x00 and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x12; op2:x25; dest:x21; op1val:0x200; op2val:0x0; + valaddr_reg:x1; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x21, x12, x25, dyn, 0, 0, x1, 10*FLEN/8, x4, x2, x5) + +inst_6: +// rs1==x26, rs2==x31, rd==x0,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x26; op2:x31; dest:x0; op1val:0x0; op2val:0x1ff; + valaddr_reg:x1; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x0, x26, x31, dyn, 0, 0, x1, 12*FLEN/8, x4, x2, x5) + +inst_7: +// rs1==x18, rs2==x26, rd==x17,fs1 == 0 and fe1 == 0x00 and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x18; op2:x26; dest:x17; op1val:0x1ff; op2val:0x0; + valaddr_reg:x1; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x17, x18, x26, dyn, 0, 0, x1, 14*FLEN/8, x4, x2, x5) + +inst_8: +// rs1==x24, rs2==x6, rd==x31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x24; op2:x6; dest:x31; op1val:0x0; op2val:0x300; + valaddr_reg:x1; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x24, x6, dyn, 0, 0, x1, 16*FLEN/8, x4, x2, x5) + +inst_9: +// rs1==x21, rs2==x12, rd==x13,fs1 == 0 and fe1 == 0x00 and fm1 == 0x300 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x21; op2:x12; dest:x13; op1val:0x300; op2val:0x0; + valaddr_reg:x1; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x13, x21, x12, dyn, 0, 0, x1, 18*FLEN/8, x4, x2, x5) + +inst_10: +// rs1==x3, rs2==x22, rd==x19,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x3; op2:x22; dest:x19; op1val:0x0; op2val:0xff; + valaddr_reg:x1; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x19, x3, x22, dyn, 0, 0, x1, 20*FLEN/8, x4, x2, x5) + +inst_11: +// rs1==x13, rs2==x8, rd==x25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x13; op2:x8; dest:x25; op1val:0xff; op2val:0x0; + valaddr_reg:x1; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x25, x13, x8, dyn, 0, 0, x1, 22*FLEN/8, x4, x2, x5) +RVTEST_VALBASEUPD(x11,test_dataset_1) + +inst_12: +// rs1==x7, rs2==x30, rd==x18,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x7; op2:x30; dest:x18; op1val:0x0; op2val:0x380; + valaddr_reg:x11; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x18, x7, x30, dyn, 0, 0, x11, 0*FLEN/8, x12, x2, x5) + +inst_13: +// rs1==x0, rs2==x18, rd==x4,fs1 == 0 and fe1 == 0x00 and fm1 == 0x380 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x0; op2:x18; dest:x4; op1val:0x0; op2val:0x0; + valaddr_reg:x11; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x4, x0, x18, dyn, 0, 0, x11, 2*FLEN/8, x12, x2, x5) + +inst_14: +// rs1==x1, rs2==x0, rd==x10,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x1; op2:x0; dest:x10; op1val:0x0; op2val:0x0; + valaddr_reg:x11; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x10, x1, x0, dyn, 0, 0, x11, 4*FLEN/8, x12, x2, x5) + +inst_15: +// rs1==x5, rs2==x3, rd==x22,fs1 == 0 and fe1 == 0x00 and fm1 == 0x07f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x5; op2:x3; dest:x22; op1val:0x7f; op2val:0x0; + valaddr_reg:x11; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP(fadd.h, x22, x5, x3, dyn, 0, 0, x11, 6*FLEN/8, x12, x2, x10) +RVTEST_SIGBASE(x3,signature_x3_0) + +inst_16: +// rs1==x20, rs2==x7, rd==x2,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x20; op2:x7; dest:x2; op1val:0x0; op2val:0x3c0; + valaddr_reg:x11; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP(fadd.h, x2, x20, x7, dyn, 0, 0, x11, 8*FLEN/8, x12, x3, x10) + +inst_17: +// rs1==x9, rs2==x27, rd==x24,fs1 == 0 and fe1 == 0x00 and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x9; op2:x27; dest:x24; op1val:0x3c0; op2val:0x0; + valaddr_reg:x11; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP(fadd.h, x24, x9, x27, dyn, 0, 0, x11, 10*FLEN/8, x12, x3, x10) + +inst_18: +// rs1==x28, rs2==x5, rd==x6,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x28; op2:x5; dest:x6; op1val:0x0; op2val:0x3f; + valaddr_reg:x11; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP(fadd.h, x6, x28, x5, dyn, 0, 0, x11, 12*FLEN/8, x12, x3, x10) + +inst_19: +// rs1==x14, rs2==x17, rd==x30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x14; op2:x17; dest:x30; op1val:0x3f; op2val:0x0; + valaddr_reg:x11; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP(fadd.h, x30, x14, x17, dyn, 0, 0, x11, 14*FLEN/8, x12, x3, x10) + +inst_20: +// rs1==x15, rs2==x16, rd==x28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x15; op2:x16; dest:x28; op1val:0x0; op2val:0x3e0; + valaddr_reg:x11; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP(fadd.h, x28, x15, x16, dyn, 0, 0, x11, 16*FLEN/8, x12, x3, x10) + +inst_21: +// rs1==x22, rs2==x13, rd==x20,fs1 == 0 and fe1 == 0x00 and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x22; op2:x13; dest:x20; op1val:0x3e0; op2val:0x0; + valaddr_reg:x11; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP(fadd.h, x20, x22, x13, dyn, 0, 0, x11, 18*FLEN/8, x12, x3, x10) + +inst_22: +// rs1==x8, rs2==x21, rd==x29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x8; op2:x21; dest:x29; op1val:0x0; op2val:0x1f; + valaddr_reg:x11; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP(fadd.h, x29, x8, x21, dyn, 0, 0, x11, 20*FLEN/8, x12, x3, x10) + +inst_23: +// rs1==x4, rs2==x2, rd==x14,fs1 == 0 and fe1 == 0x00 and fm1 == 0x01f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x4; op2:x2; dest:x14; op1val:0x1f; op2val:0x0; + valaddr_reg:x11; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP(fadd.h, x14, x4, x2, dyn, 0, 0, x11, 22*FLEN/8, x12, x3, x10) + +inst_24: +// rs1==x6, rs2==x4, rd==x23,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x6; op2:x4; dest:x23; op1val:0x0; op2val:0x3f0; + valaddr_reg:x11; val_offset:24*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP(fadd.h, x23, x6, x4, dyn, 0, 0, x11, 24*FLEN/8, x12, x3, x10) +RVTEST_VALBASEUPD(x6,test_dataset_2) + +inst_25: +// rs1==x25, rs2==x9, rd==x1,fs1 == 0 and fe1 == 0x00 and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x25; op2:x9; dest:x1; op1val:0x3f0; op2val:0x0; + valaddr_reg:x6; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP(fadd.h, x1, x25, x9, dyn, 0, 0, x6, 0*FLEN/8, x7, x3, x10) + +inst_26: +// rs1==x19, rs2==x20, rd==x16,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x19; op2:x20; dest:x16; op1val:0x0; op2val:0xf; + valaddr_reg:x6; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP(fadd.h, x16, x19, x20, dyn, 0, 0, x6, 2*FLEN/8, x7, x3, x10) + +inst_27: +// rs1==x17, rs2==x19, rd==x26,fs1 == 0 and fe1 == 0x00 and fm1 == 0x00f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x17; op2:x19; dest:x26; op1val:0xf; op2val:0x0; + valaddr_reg:x6; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP(fadd.h, x26, x17, x19, dyn, 0, 0, x6, 4*FLEN/8, x7, x3, x10) + +inst_28: +// rs1==x2, rs2==x24, rd==x12,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x2; op2:x24; dest:x12; op1val:0x0; op2val:0x3f8; + valaddr_reg:x6; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x12, x2, x24, dyn, 0, 0, x6, 6*FLEN/8, x7, x3, x4) +RVTEST_SIGBASE(x2,signature_x2_2) + +inst_29: +// rs1==x31, rs2==x1, rd==x5,fs1 == 0 and fe1 == 0x00 and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x31; op2:x1; dest:x5; op1val:0x3f8; op2val:0x0; + valaddr_reg:x6; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x5, x31, x1, dyn, 0, 0, x6, 8*FLEN/8, x7, x2, x4) + +inst_30: +// rs1==x16, rs2==x28, rd==x8,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x16; op2:x28; dest:x8; op1val:0x0; op2val:0x7; + valaddr_reg:x6; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x8, x16, x28, dyn, 0, 0, x6, 10*FLEN/8, x7, x2, x4) + +inst_31: +// rs1==x29, rs2==x14, rd==x3,fs1 == 0 and fe1 == 0x00 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x29; op2:x14; dest:x3; op1val:0x7; op2val:0x0; + valaddr_reg:x6; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x3, x29, x14, dyn, 0, 0, x6, 12*FLEN/8, x7, x2, x4) + +inst_32: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x3fc; + valaddr_reg:x6; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 14*FLEN/8, x7, x2, x4) + +inst_33: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fc; op2val:0x0; + valaddr_reg:x6; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 16*FLEN/8, x7, x2, x4) + +inst_34: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x3; + valaddr_reg:x6; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 18*FLEN/8, x7, x2, x4) + +inst_35: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x003 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3; op2val:0x0; + valaddr_reg:x6; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 20*FLEN/8, x7, x2, x4) + +inst_36: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x3fe; + valaddr_reg:x6; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 22*FLEN/8, x7, x2, x4) + +inst_37: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fe; op2val:0x0; + valaddr_reg:x6; val_offset:24*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 24*FLEN/8, x7, x2, x4) + +inst_38: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1b6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x1b6; + valaddr_reg:x6; val_offset:26*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 26*FLEN/8, x7, x2, x4) + +inst_39: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1b6; op2val:0x0; + valaddr_reg:x6; val_offset:28*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 28*FLEN/8, x7, x2, x4) + +inst_40: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x36d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x36d; + valaddr_reg:x6; val_offset:30*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 30*FLEN/8, x7, x2, x4) + +inst_41: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x36d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x36d; op2val:0x0; + valaddr_reg:x6; val_offset:32*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 32*FLEN/8, x7, x2, x4) + +inst_42: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0cc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xcc; + valaddr_reg:x6; val_offset:34*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 34*FLEN/8, x7, x2, x4) + +inst_43: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0cc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xcc; op2val:0x0; + valaddr_reg:x6; val_offset:36*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 36*FLEN/8, x7, x2, x4) + +inst_44: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x333 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x333; + valaddr_reg:x6; val_offset:38*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 38*FLEN/8, x7, x2, x4) + +inst_45: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x333 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x333; op2val:0x0; + valaddr_reg:x6; val_offset:40*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 40*FLEN/8, x7, x2, x4) + +inst_46: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1dd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x1dd; + valaddr_reg:x6; val_offset:42*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 42*FLEN/8, x7, x2, x4) + +inst_47: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1dd; op2val:0x0; + valaddr_reg:x6; val_offset:44*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 44*FLEN/8, x7, x2, x4) + +inst_48: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x222 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x222; + valaddr_reg:x6; val_offset:46*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 46*FLEN/8, x7, x2, x4) + +inst_49: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x222 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x222; op2val:0x0; + valaddr_reg:x6; val_offset:48*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 48*FLEN/8, x7, x2, x4) + +inst_50: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x124 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x124; + valaddr_reg:x6; val_offset:50*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 50*FLEN/8, x7, x2, x4) + +inst_51: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x124 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x124; op2val:0x0; + valaddr_reg:x6; val_offset:52*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 52*FLEN/8, x7, x2, x4) + +inst_52: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2db and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x2db; + valaddr_reg:x6; val_offset:54*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 54*FLEN/8, x7, x2, x4) + +inst_53: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2db; op2val:0x0; + valaddr_reg:x6; val_offset:56*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 56*FLEN/8, x7, x2, x4) + +inst_54: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x199 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x199; + valaddr_reg:x6; val_offset:58*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 58*FLEN/8, x7, x2, x4) + +inst_55: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x199 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x199; op2val:0x0; + valaddr_reg:x6; val_offset:60*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 60*FLEN/8, x7, x2, x4) + +inst_56: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x266 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x266; + valaddr_reg:x6; val_offset:62*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 62*FLEN/8, x7, x2, x4) + +inst_57: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x266 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x266; op2val:0x0; + valaddr_reg:x6; val_offset:64*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 64*FLEN/8, x7, x2, x4) + +inst_58: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x7000; + valaddr_reg:x6; val_offset:66*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 66*FLEN/8, x7, x2, x4) + +inst_59: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7000; op2val:0x0; + valaddr_reg:x6; val_offset:68*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 68*FLEN/8, x7, x2, x4) + +inst_60: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x73ff; + valaddr_reg:x6; val_offset:70*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 70*FLEN/8, x7, x2, x4) + +inst_61: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x73ff; op2val:0x0; + valaddr_reg:x6; val_offset:72*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 72*FLEN/8, x7, x2, x4) + +inst_62: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x7200; + valaddr_reg:x6; val_offset:74*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 74*FLEN/8, x7, x2, x4) + +inst_63: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7200; op2val:0x0; + valaddr_reg:x6; val_offset:76*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 76*FLEN/8, x7, x2, x4) + +inst_64: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x71ff; + valaddr_reg:x6; val_offset:78*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 78*FLEN/8, x7, x2, x4) + +inst_65: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x71ff; op2val:0x0; + valaddr_reg:x6; val_offset:80*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 80*FLEN/8, x7, x2, x4) + +inst_66: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x7300; + valaddr_reg:x6; val_offset:82*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 82*FLEN/8, x7, x2, x4) + +inst_67: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x300 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7300; op2val:0x0; + valaddr_reg:x6; val_offset:84*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 84*FLEN/8, x7, x2, x4) + +inst_68: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x70ff; + valaddr_reg:x6; val_offset:86*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 86*FLEN/8, x7, x2, x4) + +inst_69: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x70ff; op2val:0x0; + valaddr_reg:x6; val_offset:88*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 88*FLEN/8, x7, x2, x4) + +inst_70: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x7380; + valaddr_reg:x6; val_offset:90*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 90*FLEN/8, x7, x2, x4) + +inst_71: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x380 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7380; op2val:0x0; + valaddr_reg:x6; val_offset:92*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 92*FLEN/8, x7, x2, x4) + +inst_72: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x707f; + valaddr_reg:x6; val_offset:94*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 94*FLEN/8, x7, x2, x4) + +inst_73: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x07f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x707f; op2val:0x0; + valaddr_reg:x6; val_offset:96*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 96*FLEN/8, x7, x2, x4) + +inst_74: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x73c0; + valaddr_reg:x6; val_offset:98*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 98*FLEN/8, x7, x2, x4) + +inst_75: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x73c0; op2val:0x0; + valaddr_reg:x6; val_offset:100*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 100*FLEN/8, x7, x2, x4) + +inst_76: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x703f; + valaddr_reg:x6; val_offset:102*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 102*FLEN/8, x7, x2, x4) + +inst_77: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x03f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x703f; op2val:0x0; + valaddr_reg:x6; val_offset:104*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 104*FLEN/8, x7, x2, x4) + +inst_78: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x73e0; + valaddr_reg:x6; val_offset:106*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 106*FLEN/8, x7, x2, x4) + +inst_79: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x73e0; op2val:0x0; + valaddr_reg:x6; val_offset:108*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 108*FLEN/8, x7, x2, x4) + +inst_80: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x701f; + valaddr_reg:x6; val_offset:110*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 110*FLEN/8, x7, x2, x4) + +inst_81: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x01f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x701f; op2val:0x0; + valaddr_reg:x6; val_offset:112*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 112*FLEN/8, x7, x2, x4) + +inst_82: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x73f0; + valaddr_reg:x6; val_offset:114*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 114*FLEN/8, x7, x2, x4) + +inst_83: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x73f0; op2val:0x0; + valaddr_reg:x6; val_offset:116*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 116*FLEN/8, x7, x2, x4) + +inst_84: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x700f; + valaddr_reg:x6; val_offset:118*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 118*FLEN/8, x7, x2, x4) + +inst_85: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x00f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x700f; op2val:0x0; + valaddr_reg:x6; val_offset:120*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 120*FLEN/8, x7, x2, x4) + +inst_86: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x73f8; + valaddr_reg:x6; val_offset:122*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 122*FLEN/8, x7, x2, x4) + +inst_87: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x73f8; op2val:0x0; + valaddr_reg:x6; val_offset:124*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 124*FLEN/8, x7, x2, x4) + +inst_88: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x7007; + valaddr_reg:x6; val_offset:126*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 126*FLEN/8, x7, x2, x4) + +inst_89: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x007 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7007; op2val:0x0; + valaddr_reg:x6; val_offset:128*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 128*FLEN/8, x7, x2, x4) + +inst_90: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x73fc; + valaddr_reg:x6; val_offset:130*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 130*FLEN/8, x7, x2, x4) + +inst_91: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x73fc; op2val:0x0; + valaddr_reg:x6; val_offset:132*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 132*FLEN/8, x7, x2, x4) + +inst_92: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x7003; + valaddr_reg:x6; val_offset:134*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 134*FLEN/8, x7, x2, x4) + +inst_93: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x003 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7003; op2val:0x0; + valaddr_reg:x6; val_offset:136*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 136*FLEN/8, x7, x2, x4) + +inst_94: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x73fe; + valaddr_reg:x6; val_offset:138*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 138*FLEN/8, x7, x2, x4) + +inst_95: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x73fe; op2val:0x0; + valaddr_reg:x6; val_offset:140*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 140*FLEN/8, x7, x2, x4) + +inst_96: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x7001; + valaddr_reg:x6; val_offset:142*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 142*FLEN/8, x7, x2, x4) + +inst_97: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7001; op2val:0x0; + valaddr_reg:x6; val_offset:144*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 144*FLEN/8, x7, x2, x4) + +inst_98: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x400; + valaddr_reg:x6; val_offset:146*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 146*FLEN/8, x7, x2, x4) + +inst_99: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x0; + valaddr_reg:x6; val_offset:148*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 148*FLEN/8, x7, x2, x4) + +inst_100: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x7ff; + valaddr_reg:x6; val_offset:150*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 150*FLEN/8, x7, x2, x4) + +inst_101: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ff; op2val:0x0; + valaddr_reg:x6; val_offset:152*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 152*FLEN/8, x7, x2, x4) + +inst_102: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x600; + valaddr_reg:x6; val_offset:154*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 154*FLEN/8, x7, x2, x4) + +inst_103: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x600; op2val:0x0; + valaddr_reg:x6; val_offset:156*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 156*FLEN/8, x7, x2, x4) + +inst_104: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x5ff; + valaddr_reg:x6; val_offset:158*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 158*FLEN/8, x7, x2, x4) + +inst_105: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5ff; op2val:0x0; + valaddr_reg:x6; val_offset:160*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 160*FLEN/8, x7, x2, x4) + +inst_106: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x700; + valaddr_reg:x6; val_offset:162*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 162*FLEN/8, x7, x2, x4) + +inst_107: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x300 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x700; op2val:0x0; + valaddr_reg:x6; val_offset:164*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 164*FLEN/8, x7, x2, x4) + +inst_108: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x4ff; + valaddr_reg:x6; val_offset:166*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 166*FLEN/8, x7, x2, x4) + +inst_109: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4ff; op2val:0x0; + valaddr_reg:x6; val_offset:168*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 168*FLEN/8, x7, x2, x4) + +inst_110: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x780; + valaddr_reg:x6; val_offset:170*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 170*FLEN/8, x7, x2, x4) + +inst_111: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x380 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x780; op2val:0x0; + valaddr_reg:x6; val_offset:172*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 172*FLEN/8, x7, x2, x4) + +inst_112: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x47f; + valaddr_reg:x6; val_offset:174*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 174*FLEN/8, x7, x2, x4) + +inst_113: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x07f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x47f; op2val:0x0; + valaddr_reg:x6; val_offset:176*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 176*FLEN/8, x7, x2, x4) + +inst_114: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x7c0; + valaddr_reg:x6; val_offset:178*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 178*FLEN/8, x7, x2, x4) + +inst_115: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c0; op2val:0x0; + valaddr_reg:x6; val_offset:180*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 180*FLEN/8, x7, x2, x4) + +inst_116: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x43f; + valaddr_reg:x6; val_offset:182*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 182*FLEN/8, x7, x2, x4) + +inst_117: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x43f; op2val:0x0; + valaddr_reg:x6; val_offset:184*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 184*FLEN/8, x7, x2, x4) + +inst_118: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x7e0; + valaddr_reg:x6; val_offset:186*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 186*FLEN/8, x7, x2, x4) + +inst_119: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e0; op2val:0x0; + valaddr_reg:x6; val_offset:188*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 188*FLEN/8, x7, x2, x4) + +inst_120: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x41f; + valaddr_reg:x6; val_offset:190*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 190*FLEN/8, x7, x2, x4) + +inst_121: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x01f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x41f; op2val:0x0; + valaddr_reg:x6; val_offset:192*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 192*FLEN/8, x7, x2, x4) + +inst_122: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x7f0; + valaddr_reg:x6; val_offset:194*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 194*FLEN/8, x7, x2, x4) + +inst_123: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7f0; op2val:0x0; + valaddr_reg:x6; val_offset:196*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 196*FLEN/8, x7, x2, x4) + +inst_124: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x40f; + valaddr_reg:x6; val_offset:198*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 198*FLEN/8, x7, x2, x4) + +inst_125: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x00f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x40f; op2val:0x0; + valaddr_reg:x6; val_offset:200*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 200*FLEN/8, x7, x2, x4) + +inst_126: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x7f8; + valaddr_reg:x6; val_offset:202*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 202*FLEN/8, x7, x2, x4) + +inst_127: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7f8; op2val:0x0; + valaddr_reg:x6; val_offset:204*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 204*FLEN/8, x7, x2, x4) + +inst_128: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x407; + valaddr_reg:x6; val_offset:206*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 206*FLEN/8, x7, x2, x4) + +inst_129: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x407; op2val:0x0; + valaddr_reg:x6; val_offset:208*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 208*FLEN/8, x7, x2, x4) + +inst_130: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x7fc; + valaddr_reg:x6; val_offset:210*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 210*FLEN/8, x7, x2, x4) + +inst_131: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7fc; op2val:0x0; + valaddr_reg:x6; val_offset:212*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 212*FLEN/8, x7, x2, x4) + +inst_132: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x403; + valaddr_reg:x6; val_offset:214*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 214*FLEN/8, x7, x2, x4) + +inst_133: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x003 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x403; op2val:0x0; + valaddr_reg:x6; val_offset:216*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 216*FLEN/8, x7, x2, x4) + +inst_134: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x7fe; + valaddr_reg:x6; val_offset:218*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 218*FLEN/8, x7, x2, x4) + +inst_135: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7fe; op2val:0x0; + valaddr_reg:x6; val_offset:220*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 220*FLEN/8, x7, x2, x4) + +inst_136: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x401; + valaddr_reg:x6; val_offset:222*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 222*FLEN/8, x7, x2, x4) + +inst_137: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x0; + valaddr_reg:x6; val_offset:224*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 224*FLEN/8, x7, x2, x4) + +inst_138: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x800; + valaddr_reg:x6; val_offset:226*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 226*FLEN/8, x7, x2, x4) + +inst_139: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x800; op2val:0x0; + valaddr_reg:x6; val_offset:228*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 228*FLEN/8, x7, x2, x4) + +inst_140: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xbff; + valaddr_reg:x6; val_offset:230*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 230*FLEN/8, x7, x2, x4) + +inst_141: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbff; op2val:0x0; + valaddr_reg:x6; val_offset:232*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 232*FLEN/8, x7, x2, x4) + +inst_142: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xa00; + valaddr_reg:x6; val_offset:234*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 234*FLEN/8, x7, x2, x4) + +inst_143: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xa00; op2val:0x0; + valaddr_reg:x6; val_offset:236*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 236*FLEN/8, x7, x2, x4) + +inst_144: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x9ff; + valaddr_reg:x6; val_offset:238*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 238*FLEN/8, x7, x2, x4) + +inst_145: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x9ff; op2val:0x0; + valaddr_reg:x6; val_offset:240*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 240*FLEN/8, x7, x2, x4) + +inst_146: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xb00; + valaddr_reg:x6; val_offset:242*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 242*FLEN/8, x7, x2, x4) + +inst_147: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x300 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xb00; op2val:0x0; + valaddr_reg:x6; val_offset:244*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 244*FLEN/8, x7, x2, x4) + +inst_148: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x8ff; + valaddr_reg:x6; val_offset:246*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 246*FLEN/8, x7, x2, x4) + +inst_149: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8ff; op2val:0x0; + valaddr_reg:x6; val_offset:248*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 248*FLEN/8, x7, x2, x4) + +inst_150: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xb80; + valaddr_reg:x6; val_offset:250*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 250*FLEN/8, x7, x2, x4) + +inst_151: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x380 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xb80; op2val:0x0; + valaddr_reg:x6; val_offset:252*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 252*FLEN/8, x7, x2, x4) + +inst_152: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x87f; + valaddr_reg:x6; val_offset:254*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 254*FLEN/8, x7, x2, x4) + +inst_153: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x07f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x87f; op2val:0x0; + valaddr_reg:x6; val_offset:256*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 256*FLEN/8, x7, x2, x4) + +inst_154: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xbc0; + valaddr_reg:x6; val_offset:258*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 258*FLEN/8, x7, x2, x4) + +inst_155: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc0; op2val:0x0; + valaddr_reg:x6; val_offset:260*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 260*FLEN/8, x7, x2, x4) + +inst_156: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x83f; + valaddr_reg:x6; val_offset:262*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 262*FLEN/8, x7, x2, x4) +RVTEST_SIGBASE(x2,signature_x2_3) + +inst_157: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83f; op2val:0x0; + valaddr_reg:x6; val_offset:264*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 264*FLEN/8, x7, x2, x4) + +inst_158: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xbe0; + valaddr_reg:x6; val_offset:266*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 266*FLEN/8, x7, x2, x4) + +inst_159: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbe0; op2val:0x0; + valaddr_reg:x6; val_offset:268*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 268*FLEN/8, x7, x2, x4) + +inst_160: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x81f; + valaddr_reg:x6; val_offset:270*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 270*FLEN/8, x7, x2, x4) + +inst_161: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x01f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x81f; op2val:0x0; + valaddr_reg:x6; val_offset:272*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 272*FLEN/8, x7, x2, x4) + +inst_162: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xbf0; + valaddr_reg:x6; val_offset:274*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 274*FLEN/8, x7, x2, x4) + +inst_163: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbf0; op2val:0x0; + valaddr_reg:x6; val_offset:276*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 276*FLEN/8, x7, x2, x4) + +inst_164: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x80f; + valaddr_reg:x6; val_offset:278*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 278*FLEN/8, x7, x2, x4) + +inst_165: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x00f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x80f; op2val:0x0; + valaddr_reg:x6; val_offset:280*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 280*FLEN/8, x7, x2, x4) + +inst_166: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xbf8; + valaddr_reg:x6; val_offset:282*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 282*FLEN/8, x7, x2, x4) + +inst_167: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbf8; op2val:0x0; + valaddr_reg:x6; val_offset:284*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 284*FLEN/8, x7, x2, x4) + +inst_168: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x807; + valaddr_reg:x6; val_offset:286*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 286*FLEN/8, x7, x2, x4) + +inst_169: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x807; op2val:0x0; + valaddr_reg:x6; val_offset:288*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 288*FLEN/8, x7, x2, x4) + +inst_170: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xbfc; + valaddr_reg:x6; val_offset:290*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 290*FLEN/8, x7, x2, x4) + +inst_171: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbfc; op2val:0x0; + valaddr_reg:x6; val_offset:292*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 292*FLEN/8, x7, x2, x4) + +inst_172: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x803; + valaddr_reg:x6; val_offset:294*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 294*FLEN/8, x7, x2, x4) + +inst_173: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x003 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x803; op2val:0x0; + valaddr_reg:x6; val_offset:296*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 296*FLEN/8, x7, x2, x4) + +inst_174: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xbfe; + valaddr_reg:x6; val_offset:298*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 298*FLEN/8, x7, x2, x4) + +inst_175: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbfe; op2val:0x0; + valaddr_reg:x6; val_offset:300*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 300*FLEN/8, x7, x2, x4) + +inst_176: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x801; + valaddr_reg:x6; val_offset:302*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 302*FLEN/8, x7, x2, x4) + +inst_177: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x801; op2val:0x0; + valaddr_reg:x6; val_offset:304*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 304*FLEN/8, x7, x2, x4) + +inst_178: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xc00; + valaddr_reg:x6; val_offset:306*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 306*FLEN/8, x7, x2, x4) + +inst_179: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc00; op2val:0x0; + valaddr_reg:x6; val_offset:308*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 308*FLEN/8, x7, x2, x4) + +inst_180: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xfff; + valaddr_reg:x6; val_offset:310*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 310*FLEN/8, x7, x2, x4) + +inst_181: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfff; op2val:0x0; + valaddr_reg:x6; val_offset:312*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 312*FLEN/8, x7, x2, x4) + +inst_182: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xe00; + valaddr_reg:x6; val_offset:314*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 314*FLEN/8, x7, x2, x4) + +inst_183: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xe00; op2val:0x0; + valaddr_reg:x6; val_offset:316*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 316*FLEN/8, x7, x2, x4) + +inst_184: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xdff; + valaddr_reg:x6; val_offset:318*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 318*FLEN/8, x7, x2, x4) + +inst_185: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xdff; op2val:0x0; + valaddr_reg:x6; val_offset:320*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 320*FLEN/8, x7, x2, x4) + +inst_186: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xf00; + valaddr_reg:x6; val_offset:322*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 322*FLEN/8, x7, x2, x4) + +inst_187: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x300 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf00; op2val:0x0; + valaddr_reg:x6; val_offset:324*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 324*FLEN/8, x7, x2, x4) + +inst_188: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xcff; + valaddr_reg:x6; val_offset:326*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 326*FLEN/8, x7, x2, x4) + +inst_189: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xcff; op2val:0x0; + valaddr_reg:x6; val_offset:328*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 328*FLEN/8, x7, x2, x4) + +inst_190: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xf80; + valaddr_reg:x6; val_offset:330*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 330*FLEN/8, x7, x2, x4) + +inst_191: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x380 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf80; op2val:0x0; + valaddr_reg:x6; val_offset:332*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 332*FLEN/8, x7, x2, x4) + +inst_192: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xc7f; + valaddr_reg:x6; val_offset:334*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 334*FLEN/8, x7, x2, x4) + +inst_193: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x07f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc7f; op2val:0x0; + valaddr_reg:x6; val_offset:336*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 336*FLEN/8, x7, x2, x4) + +inst_194: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xfc0; + valaddr_reg:x6; val_offset:338*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 338*FLEN/8, x7, x2, x4) + +inst_195: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc0; op2val:0x0; + valaddr_reg:x6; val_offset:340*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 340*FLEN/8, x7, x2, x4) + +inst_196: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xc3f; + valaddr_reg:x6; val_offset:342*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 342*FLEN/8, x7, x2, x4) + +inst_197: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc3f; op2val:0x0; + valaddr_reg:x6; val_offset:344*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 344*FLEN/8, x7, x2, x4) + +inst_198: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xfe0; + valaddr_reg:x6; val_offset:346*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 346*FLEN/8, x7, x2, x4) + +inst_199: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe0; op2val:0x0; + valaddr_reg:x6; val_offset:348*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 348*FLEN/8, x7, x2, x4) + +inst_200: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xc1f; + valaddr_reg:x6; val_offset:350*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 350*FLEN/8, x7, x2, x4) + +inst_201: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x01f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc1f; op2val:0x0; + valaddr_reg:x6; val_offset:352*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 352*FLEN/8, x7, x2, x4) + +inst_202: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xff0; + valaddr_reg:x6; val_offset:354*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 354*FLEN/8, x7, x2, x4) + +inst_203: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xff0; op2val:0x0; + valaddr_reg:x6; val_offset:356*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 356*FLEN/8, x7, x2, x4) + +inst_204: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xc0f; + valaddr_reg:x6; val_offset:358*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 358*FLEN/8, x7, x2, x4) + +inst_205: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x00f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc0f; op2val:0x0; + valaddr_reg:x6; val_offset:360*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 360*FLEN/8, x7, x2, x4) + +inst_206: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xff8; + valaddr_reg:x6; val_offset:362*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 362*FLEN/8, x7, x2, x4) + +inst_207: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xff8; op2val:0x0; + valaddr_reg:x6; val_offset:364*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 364*FLEN/8, x7, x2, x4) + +inst_208: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xc07; + valaddr_reg:x6; val_offset:366*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 366*FLEN/8, x7, x2, x4) + +inst_209: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc07; op2val:0x0; + valaddr_reg:x6; val_offset:368*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 368*FLEN/8, x7, x2, x4) + +inst_210: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xffc; + valaddr_reg:x6; val_offset:370*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 370*FLEN/8, x7, x2, x4) + +inst_211: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xffc; op2val:0x0; + valaddr_reg:x6; val_offset:372*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 372*FLEN/8, x7, x2, x4) + +inst_212: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xc03; + valaddr_reg:x6; val_offset:374*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 374*FLEN/8, x7, x2, x4) + +inst_213: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x003 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc03; op2val:0x0; + valaddr_reg:x6; val_offset:376*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 376*FLEN/8, x7, x2, x4) + +inst_214: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xffe; + valaddr_reg:x6; val_offset:378*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 378*FLEN/8, x7, x2, x4) + +inst_215: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xffe; op2val:0x0; + valaddr_reg:x6; val_offset:380*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 380*FLEN/8, x7, x2, x4) + +inst_216: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xc01; + valaddr_reg:x6; val_offset:382*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 382*FLEN/8, x7, x2, x4) + +inst_217: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc01; op2val:0x0; + valaddr_reg:x6; val_offset:384*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 384*FLEN/8, x7, x2, x4) + +inst_218: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8001; + valaddr_reg:x6; val_offset:386*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 386*FLEN/8, x7, x2, x4) + +inst_219: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8000; + valaddr_reg:x6; val_offset:388*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 388*FLEN/8, x7, x2, x4) + +inst_220: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x83ff; + valaddr_reg:x6; val_offset:390*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 390*FLEN/8, x7, x2, x4) + +inst_221: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8000; + valaddr_reg:x6; val_offset:392*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 392*FLEN/8, x7, x2, x4) + +inst_222: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8200; + valaddr_reg:x6; val_offset:394*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 394*FLEN/8, x7, x2, x4) + +inst_223: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8200; op2val:0x8000; + valaddr_reg:x6; val_offset:396*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 396*FLEN/8, x7, x2, x4) + +inst_224: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x81ff; + valaddr_reg:x6; val_offset:398*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 398*FLEN/8, x7, x2, x4) + +inst_225: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x81ff; op2val:0x8000; + valaddr_reg:x6; val_offset:400*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 400*FLEN/8, x7, x2, x4) + +inst_226: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8300; + valaddr_reg:x6; val_offset:402*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 402*FLEN/8, x7, x2, x4) + +inst_227: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x300 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8300; op2val:0x8000; + valaddr_reg:x6; val_offset:404*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 404*FLEN/8, x7, x2, x4) + +inst_228: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x80ff; + valaddr_reg:x6; val_offset:406*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 406*FLEN/8, x7, x2, x4) + +inst_229: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x80ff; op2val:0x8000; + valaddr_reg:x6; val_offset:408*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 408*FLEN/8, x7, x2, x4) + +inst_230: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8380; + valaddr_reg:x6; val_offset:410*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 410*FLEN/8, x7, x2, x4) + +inst_231: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x380 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8380; op2val:0x8000; + valaddr_reg:x6; val_offset:412*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 412*FLEN/8, x7, x2, x4) + +inst_232: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x807f; + valaddr_reg:x6; val_offset:414*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 414*FLEN/8, x7, x2, x4) + +inst_233: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x07f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x807f; op2val:0x8000; + valaddr_reg:x6; val_offset:416*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 416*FLEN/8, x7, x2, x4) + +inst_234: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x83c0; + valaddr_reg:x6; val_offset:418*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 418*FLEN/8, x7, x2, x4) + +inst_235: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83c0; op2val:0x8000; + valaddr_reg:x6; val_offset:420*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 420*FLEN/8, x7, x2, x4) + +inst_236: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x803f; + valaddr_reg:x6; val_offset:422*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 422*FLEN/8, x7, x2, x4) + +inst_237: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x803f; op2val:0x8000; + valaddr_reg:x6; val_offset:424*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 424*FLEN/8, x7, x2, x4) + +inst_238: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x83e0; + valaddr_reg:x6; val_offset:426*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 426*FLEN/8, x7, x2, x4) + +inst_239: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83e0; op2val:0x8000; + valaddr_reg:x6; val_offset:428*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 428*FLEN/8, x7, x2, x4) + +inst_240: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x801f; + valaddr_reg:x6; val_offset:430*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 430*FLEN/8, x7, x2, x4) + +inst_241: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x01f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x801f; op2val:0x8000; + valaddr_reg:x6; val_offset:432*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 432*FLEN/8, x7, x2, x4) + +inst_242: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x83f0; + valaddr_reg:x6; val_offset:434*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 434*FLEN/8, x7, x2, x4) + +inst_243: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83f0; op2val:0x8000; + valaddr_reg:x6; val_offset:436*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 436*FLEN/8, x7, x2, x4) + +inst_244: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x800f; + valaddr_reg:x6; val_offset:438*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 438*FLEN/8, x7, x2, x4) + +inst_245: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x00f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x800f; op2val:0x8000; + valaddr_reg:x6; val_offset:440*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 440*FLEN/8, x7, x2, x4) + +inst_246: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x83f8; + valaddr_reg:x6; val_offset:442*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 442*FLEN/8, x7, x2, x4) + +inst_247: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83f8; op2val:0x8000; + valaddr_reg:x6; val_offset:444*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 444*FLEN/8, x7, x2, x4) + +inst_248: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8007; + valaddr_reg:x6; val_offset:446*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 446*FLEN/8, x7, x2, x4) + +inst_249: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8007; op2val:0x8000; + valaddr_reg:x6; val_offset:448*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 448*FLEN/8, x7, x2, x4) + +inst_250: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x83fc; + valaddr_reg:x6; val_offset:450*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 450*FLEN/8, x7, x2, x4) + +inst_251: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fc; op2val:0x8000; + valaddr_reg:x6; val_offset:452*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 452*FLEN/8, x7, x2, x4) + +inst_252: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8003; + valaddr_reg:x6; val_offset:454*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 454*FLEN/8, x7, x2, x4) + +inst_253: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8003; op2val:0x8000; + valaddr_reg:x6; val_offset:456*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 456*FLEN/8, x7, x2, x4) + +inst_254: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x83fe; + valaddr_reg:x6; val_offset:458*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 458*FLEN/8, x7, x2, x4) + +inst_255: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x8000; + valaddr_reg:x6; val_offset:460*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 460*FLEN/8, x7, x2, x4) + +inst_256: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1b6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x81b6; + valaddr_reg:x6; val_offset:462*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 462*FLEN/8, x7, x2, x4) + +inst_257: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x81b6; op2val:0x8000; + valaddr_reg:x6; val_offset:464*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 464*FLEN/8, x7, x2, x4) + +inst_258: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x36d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x836d; + valaddr_reg:x6; val_offset:466*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 466*FLEN/8, x7, x2, x4) + +inst_259: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x36d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x836d; op2val:0x8000; + valaddr_reg:x6; val_offset:468*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 468*FLEN/8, x7, x2, x4) + +inst_260: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0cc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x80cc; + valaddr_reg:x6; val_offset:470*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 470*FLEN/8, x7, x2, x4) + +inst_261: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0cc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x80cc; op2val:0x8000; + valaddr_reg:x6; val_offset:472*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 472*FLEN/8, x7, x2, x4) + +inst_262: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x333 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8333; + valaddr_reg:x6; val_offset:474*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 474*FLEN/8, x7, x2, x4) + +inst_263: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x333 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8333; op2val:0x8000; + valaddr_reg:x6; val_offset:476*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 476*FLEN/8, x7, x2, x4) + +inst_264: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1dd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x81dd; + valaddr_reg:x6; val_offset:478*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 478*FLEN/8, x7, x2, x4) + +inst_265: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1dd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x81dd; op2val:0x8000; + valaddr_reg:x6; val_offset:480*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 480*FLEN/8, x7, x2, x4) + +inst_266: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x222 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8222; + valaddr_reg:x6; val_offset:482*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 482*FLEN/8, x7, x2, x4) + +inst_267: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x222 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8222; op2val:0x8000; + valaddr_reg:x6; val_offset:484*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 484*FLEN/8, x7, x2, x4) + +inst_268: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x124 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8124; + valaddr_reg:x6; val_offset:486*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 486*FLEN/8, x7, x2, x4) + +inst_269: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x124 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8124; op2val:0x8000; + valaddr_reg:x6; val_offset:488*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 488*FLEN/8, x7, x2, x4) + +inst_270: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2db and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x82db; + valaddr_reg:x6; val_offset:490*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 490*FLEN/8, x7, x2, x4) + +inst_271: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x82db; op2val:0x8000; + valaddr_reg:x6; val_offset:492*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 492*FLEN/8, x7, x2, x4) + +inst_272: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x199 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8199; + valaddr_reg:x6; val_offset:494*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 494*FLEN/8, x7, x2, x4) + +inst_273: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x199 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8199; op2val:0x8000; + valaddr_reg:x6; val_offset:496*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 496*FLEN/8, x7, x2, x4) + +inst_274: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x266 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8266; + valaddr_reg:x6; val_offset:498*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 498*FLEN/8, x7, x2, x4) + +inst_275: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x266 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8266; op2val:0x8000; + valaddr_reg:x6; val_offset:500*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 500*FLEN/8, x7, x2, x4) + +inst_276: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x9800; + valaddr_reg:x6; val_offset:502*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 502*FLEN/8, x7, x2, x4) + +inst_277: +// fs1 == 1 and fe1 == 0x06 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x9800; op2val:0x8000; + valaddr_reg:x6; val_offset:504*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 504*FLEN/8, x7, x2, x4) + +inst_278: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x9bff; + valaddr_reg:x6; val_offset:506*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 506*FLEN/8, x7, x2, x4) + +inst_279: +// fs1 == 1 and fe1 == 0x06 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x9bff; op2val:0x8000; + valaddr_reg:x6; val_offset:508*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 508*FLEN/8, x7, x2, x4) + +inst_280: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x9a00; + valaddr_reg:x6; val_offset:510*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 510*FLEN/8, x7, x2, x4) + +inst_281: +// fs1 == 1 and fe1 == 0x06 and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x9a00; op2val:0x8000; + valaddr_reg:x6; val_offset:512*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 512*FLEN/8, x7, x2, x4) + +inst_282: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x99ff; + valaddr_reg:x6; val_offset:514*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 514*FLEN/8, x7, x2, x4) + +inst_283: +// fs1 == 1 and fe1 == 0x06 and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x99ff; op2val:0x8000; + valaddr_reg:x6; val_offset:516*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 516*FLEN/8, x7, x2, x4) + +inst_284: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x9b00; + valaddr_reg:x6; val_offset:518*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 518*FLEN/8, x7, x2, x4) +RVTEST_SIGBASE(x2,signature_x2_4) + +inst_285: +// fs1 == 1 and fe1 == 0x06 and fm1 == 0x300 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x9b00; op2val:0x8000; + valaddr_reg:x6; val_offset:520*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 520*FLEN/8, x7, x2, x4) + +inst_286: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x98ff; + valaddr_reg:x6; val_offset:522*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 522*FLEN/8, x7, x2, x4) + +inst_287: +// fs1 == 1 and fe1 == 0x06 and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x98ff; op2val:0x8000; + valaddr_reg:x6; val_offset:524*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 524*FLEN/8, x7, x2, x4) + +inst_288: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x9b80; + valaddr_reg:x6; val_offset:526*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 526*FLEN/8, x7, x2, x4) + +inst_289: +// fs1 == 1 and fe1 == 0x06 and fm1 == 0x380 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x9b80; op2val:0x8000; + valaddr_reg:x6; val_offset:528*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 528*FLEN/8, x7, x2, x4) + +inst_290: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x987f; + valaddr_reg:x6; val_offset:530*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 530*FLEN/8, x7, x2, x4) + +inst_291: +// fs1 == 1 and fe1 == 0x06 and fm1 == 0x07f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x987f; op2val:0x8000; + valaddr_reg:x6; val_offset:532*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 532*FLEN/8, x7, x2, x4) + +inst_292: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x9bc0; + valaddr_reg:x6; val_offset:534*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 534*FLEN/8, x7, x2, x4) + +inst_293: +// fs1 == 1 and fe1 == 0x06 and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x9bc0; op2val:0x8000; + valaddr_reg:x6; val_offset:536*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 536*FLEN/8, x7, x2, x4) + +inst_294: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x983f; + valaddr_reg:x6; val_offset:538*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 538*FLEN/8, x7, x2, x4) + +inst_295: +// fs1 == 1 and fe1 == 0x06 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x983f; op2val:0x8000; + valaddr_reg:x6; val_offset:540*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 540*FLEN/8, x7, x2, x4) + +inst_296: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x9be0; + valaddr_reg:x6; val_offset:542*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 542*FLEN/8, x7, x2, x4) + +inst_297: +// fs1 == 1 and fe1 == 0x06 and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x9be0; op2val:0x8000; + valaddr_reg:x6; val_offset:544*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 544*FLEN/8, x7, x2, x4) + +inst_298: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x981f; + valaddr_reg:x6; val_offset:546*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 546*FLEN/8, x7, x2, x4) + +inst_299: +// fs1 == 1 and fe1 == 0x06 and fm1 == 0x01f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x981f; op2val:0x8000; + valaddr_reg:x6; val_offset:548*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 548*FLEN/8, x7, x2, x4) + +inst_300: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x9bf0; + valaddr_reg:x6; val_offset:550*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 550*FLEN/8, x7, x2, x4) + +inst_301: +// fs1 == 1 and fe1 == 0x06 and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x9bf0; op2val:0x8000; + valaddr_reg:x6; val_offset:552*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 552*FLEN/8, x7, x2, x4) + +inst_302: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x980f; + valaddr_reg:x6; val_offset:554*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 554*FLEN/8, x7, x2, x4) + +inst_303: +// fs1 == 1 and fe1 == 0x06 and fm1 == 0x00f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x980f; op2val:0x8000; + valaddr_reg:x6; val_offset:556*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 556*FLEN/8, x7, x2, x4) + +inst_304: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x9bf8; + valaddr_reg:x6; val_offset:558*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 558*FLEN/8, x7, x2, x4) + +inst_305: +// fs1 == 1 and fe1 == 0x06 and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x9bf8; op2val:0x8000; + valaddr_reg:x6; val_offset:560*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 560*FLEN/8, x7, x2, x4) + +inst_306: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x9807; + valaddr_reg:x6; val_offset:562*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 562*FLEN/8, x7, x2, x4) + +inst_307: +// fs1 == 1 and fe1 == 0x06 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x9807; op2val:0x8000; + valaddr_reg:x6; val_offset:564*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 564*FLEN/8, x7, x2, x4) + +inst_308: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x9bfc; + valaddr_reg:x6; val_offset:566*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 566*FLEN/8, x7, x2, x4) + +inst_309: +// fs1 == 1 and fe1 == 0x06 and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x9bfc; op2val:0x8000; + valaddr_reg:x6; val_offset:568*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 568*FLEN/8, x7, x2, x4) + +inst_310: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x9803; + valaddr_reg:x6; val_offset:570*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 570*FLEN/8, x7, x2, x4) + +inst_311: +// fs1 == 1 and fe1 == 0x06 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x9803; op2val:0x8000; + valaddr_reg:x6; val_offset:572*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 572*FLEN/8, x7, x2, x4) + +inst_312: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x9bfe; + valaddr_reg:x6; val_offset:574*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 574*FLEN/8, x7, x2, x4) + +inst_313: +// fs1 == 1 and fe1 == 0x06 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x9bfe; op2val:0x8000; + valaddr_reg:x6; val_offset:576*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 576*FLEN/8, x7, x2, x4) + +inst_314: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x9801; + valaddr_reg:x6; val_offset:578*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 578*FLEN/8, x7, x2, x4) + +inst_315: +// fs1 == 1 and fe1 == 0x06 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x9801; op2val:0x8000; + valaddr_reg:x6; val_offset:580*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 580*FLEN/8, x7, x2, x4) + +inst_316: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8400; + valaddr_reg:x6; val_offset:582*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 582*FLEN/8, x7, x2, x4) + +inst_317: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8000; + valaddr_reg:x6; val_offset:584*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 584*FLEN/8, x7, x2, x4) + +inst_318: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x87ff; + valaddr_reg:x6; val_offset:586*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 586*FLEN/8, x7, x2, x4) + +inst_319: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x87ff; op2val:0x8000; + valaddr_reg:x6; val_offset:588*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 588*FLEN/8, x7, x2, x4) + +inst_320: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8600; + valaddr_reg:x6; val_offset:590*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 590*FLEN/8, x7, x2, x4) + +inst_321: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8600; op2val:0x8000; + valaddr_reg:x6; val_offset:592*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 592*FLEN/8, x7, x2, x4) + +inst_322: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x85ff; + valaddr_reg:x6; val_offset:594*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 594*FLEN/8, x7, x2, x4) + +inst_323: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x85ff; op2val:0x8000; + valaddr_reg:x6; val_offset:596*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 596*FLEN/8, x7, x2, x4) + +inst_324: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8700; + valaddr_reg:x6; val_offset:598*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 598*FLEN/8, x7, x2, x4) + +inst_325: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x300 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8700; op2val:0x8000; + valaddr_reg:x6; val_offset:600*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 600*FLEN/8, x7, x2, x4) + +inst_326: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x84ff; + valaddr_reg:x6; val_offset:602*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 602*FLEN/8, x7, x2, x4) + +inst_327: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x84ff; op2val:0x8000; + valaddr_reg:x6; val_offset:604*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 604*FLEN/8, x7, x2, x4) + +inst_328: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8780; + valaddr_reg:x6; val_offset:606*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 606*FLEN/8, x7, x2, x4) + +inst_329: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x380 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8780; op2val:0x8000; + valaddr_reg:x6; val_offset:608*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 608*FLEN/8, x7, x2, x4) + +inst_330: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x847f; + valaddr_reg:x6; val_offset:610*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 610*FLEN/8, x7, x2, x4) + +inst_331: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x07f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x847f; op2val:0x8000; + valaddr_reg:x6; val_offset:612*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 612*FLEN/8, x7, x2, x4) + +inst_332: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x87c0; + valaddr_reg:x6; val_offset:614*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 614*FLEN/8, x7, x2, x4) + +inst_333: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x87c0; op2val:0x8000; + valaddr_reg:x6; val_offset:616*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 616*FLEN/8, x7, x2, x4) + +inst_334: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x843f; + valaddr_reg:x6; val_offset:618*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 618*FLEN/8, x7, x2, x4) + +inst_335: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x843f; op2val:0x8000; + valaddr_reg:x6; val_offset:620*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 620*FLEN/8, x7, x2, x4) + +inst_336: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x87e0; + valaddr_reg:x6; val_offset:622*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 622*FLEN/8, x7, x2, x4) + +inst_337: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x87e0; op2val:0x8000; + valaddr_reg:x6; val_offset:624*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 624*FLEN/8, x7, x2, x4) + +inst_338: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x841f; + valaddr_reg:x6; val_offset:626*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 626*FLEN/8, x7, x2, x4) + +inst_339: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x01f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x841f; op2val:0x8000; + valaddr_reg:x6; val_offset:628*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 628*FLEN/8, x7, x2, x4) + +inst_340: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x87f0; + valaddr_reg:x6; val_offset:630*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 630*FLEN/8, x7, x2, x4) + +inst_341: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x87f0; op2val:0x8000; + valaddr_reg:x6; val_offset:632*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 632*FLEN/8, x7, x2, x4) + +inst_342: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x840f; + valaddr_reg:x6; val_offset:634*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 634*FLEN/8, x7, x2, x4) + +inst_343: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x00f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x840f; op2val:0x8000; + valaddr_reg:x6; val_offset:636*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 636*FLEN/8, x7, x2, x4) + +inst_344: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x87f8; + valaddr_reg:x6; val_offset:638*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 638*FLEN/8, x7, x2, x4) + +inst_345: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x87f8; op2val:0x8000; + valaddr_reg:x6; val_offset:640*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 640*FLEN/8, x7, x2, x4) + +inst_346: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8407; + valaddr_reg:x6; val_offset:642*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 642*FLEN/8, x7, x2, x4) + +inst_347: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8407; op2val:0x8000; + valaddr_reg:x6; val_offset:644*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 644*FLEN/8, x7, x2, x4) + +inst_348: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x87fc; + valaddr_reg:x6; val_offset:646*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 646*FLEN/8, x7, x2, x4) + +inst_349: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x87fc; op2val:0x8000; + valaddr_reg:x6; val_offset:648*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 648*FLEN/8, x7, x2, x4) + +inst_350: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8403; + valaddr_reg:x6; val_offset:650*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 650*FLEN/8, x7, x2, x4) + +inst_351: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8403; op2val:0x8000; + valaddr_reg:x6; val_offset:652*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 652*FLEN/8, x7, x2, x4) + +inst_352: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x87fe; + valaddr_reg:x6; val_offset:654*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 654*FLEN/8, x7, x2, x4) + +inst_353: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x87fe; op2val:0x8000; + valaddr_reg:x6; val_offset:656*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 656*FLEN/8, x7, x2, x4) + +inst_354: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8401; + valaddr_reg:x6; val_offset:658*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 658*FLEN/8, x7, x2, x4) + +inst_355: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8401; op2val:0x8000; + valaddr_reg:x6; val_offset:660*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 660*FLEN/8, x7, x2, x4) + +inst_356: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8800; + valaddr_reg:x6; val_offset:662*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 662*FLEN/8, x7, x2, x4) + +inst_357: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8800; op2val:0x8000; + valaddr_reg:x6; val_offset:664*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 664*FLEN/8, x7, x2, x4) + +inst_358: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8bff; + valaddr_reg:x6; val_offset:666*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 666*FLEN/8, x7, x2, x4) + +inst_359: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8bff; op2val:0x8000; + valaddr_reg:x6; val_offset:668*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 668*FLEN/8, x7, x2, x4) + +inst_360: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8a00; + valaddr_reg:x6; val_offset:670*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 670*FLEN/8, x7, x2, x4) + +inst_361: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8a00; op2val:0x8000; + valaddr_reg:x6; val_offset:672*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 672*FLEN/8, x7, x2, x4) + +inst_362: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x89ff; + valaddr_reg:x6; val_offset:674*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 674*FLEN/8, x7, x2, x4) + +inst_363: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x89ff; op2val:0x8000; + valaddr_reg:x6; val_offset:676*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 676*FLEN/8, x7, x2, x4) + +inst_364: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8b00; + valaddr_reg:x6; val_offset:678*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 678*FLEN/8, x7, x2, x4) + +inst_365: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x300 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8b00; op2val:0x8000; + valaddr_reg:x6; val_offset:680*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 680*FLEN/8, x7, x2, x4) + +inst_366: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x88ff; + valaddr_reg:x6; val_offset:682*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 682*FLEN/8, x7, x2, x4) + +inst_367: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x88ff; op2val:0x8000; + valaddr_reg:x6; val_offset:684*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 684*FLEN/8, x7, x2, x4) + +inst_368: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8b80; + valaddr_reg:x6; val_offset:686*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 686*FLEN/8, x7, x2, x4) + +inst_369: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x380 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8b80; op2val:0x8000; + valaddr_reg:x6; val_offset:688*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 688*FLEN/8, x7, x2, x4) + +inst_370: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x887f; + valaddr_reg:x6; val_offset:690*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 690*FLEN/8, x7, x2, x4) + +inst_371: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x07f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x887f; op2val:0x8000; + valaddr_reg:x6; val_offset:692*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 692*FLEN/8, x7, x2, x4) + +inst_372: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8bc0; + valaddr_reg:x6; val_offset:694*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 694*FLEN/8, x7, x2, x4) + +inst_373: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8bc0; op2val:0x8000; + valaddr_reg:x6; val_offset:696*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 696*FLEN/8, x7, x2, x4) + +inst_374: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x883f; + valaddr_reg:x6; val_offset:698*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 698*FLEN/8, x7, x2, x4) + +inst_375: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x883f; op2val:0x8000; + valaddr_reg:x6; val_offset:700*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 700*FLEN/8, x7, x2, x4) + +inst_376: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8be0; + valaddr_reg:x6; val_offset:702*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 702*FLEN/8, x7, x2, x4) + +inst_377: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8be0; op2val:0x8000; + valaddr_reg:x6; val_offset:704*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 704*FLEN/8, x7, x2, x4) + +inst_378: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x881f; + valaddr_reg:x6; val_offset:706*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 706*FLEN/8, x7, x2, x4) + +inst_379: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x01f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x881f; op2val:0x8000; + valaddr_reg:x6; val_offset:708*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 708*FLEN/8, x7, x2, x4) + +inst_380: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8bf0; + valaddr_reg:x6; val_offset:710*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 710*FLEN/8, x7, x2, x4) + +inst_381: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8bf0; op2val:0x8000; + valaddr_reg:x6; val_offset:712*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 712*FLEN/8, x7, x2, x4) + +inst_382: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x880f; + valaddr_reg:x6; val_offset:714*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 714*FLEN/8, x7, x2, x4) + +inst_383: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x00f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x880f; op2val:0x8000; + valaddr_reg:x6; val_offset:716*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 716*FLEN/8, x7, x2, x4) + +inst_384: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8bf8; + valaddr_reg:x6; val_offset:718*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 718*FLEN/8, x7, x2, x4) + +inst_385: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8bf8; op2val:0x8000; + valaddr_reg:x6; val_offset:720*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 720*FLEN/8, x7, x2, x4) + +inst_386: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8807; + valaddr_reg:x6; val_offset:722*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 722*FLEN/8, x7, x2, x4) + +inst_387: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8807; op2val:0x8000; + valaddr_reg:x6; val_offset:724*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 724*FLEN/8, x7, x2, x4) + +inst_388: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8bfc; + valaddr_reg:x6; val_offset:726*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 726*FLEN/8, x7, x2, x4) + +inst_389: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8bfc; op2val:0x8000; + valaddr_reg:x6; val_offset:728*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 728*FLEN/8, x7, x2, x4) + +inst_390: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8803; + valaddr_reg:x6; val_offset:730*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 730*FLEN/8, x7, x2, x4) + +inst_391: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8803; op2val:0x8000; + valaddr_reg:x6; val_offset:732*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 732*FLEN/8, x7, x2, x4) + +inst_392: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8bfe; + valaddr_reg:x6; val_offset:734*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 734*FLEN/8, x7, x2, x4) + +inst_393: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8bfe; op2val:0x8000; + valaddr_reg:x6; val_offset:736*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 736*FLEN/8, x7, x2, x4) + +inst_394: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8801; + valaddr_reg:x6; val_offset:738*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 738*FLEN/8, x7, x2, x4) + +inst_395: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8801; op2val:0x8000; + valaddr_reg:x6; val_offset:740*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 740*FLEN/8, x7, x2, x4) + +inst_396: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8c00; + valaddr_reg:x6; val_offset:742*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 742*FLEN/8, x7, x2, x4) + +inst_397: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8c00; op2val:0x8000; + valaddr_reg:x6; val_offset:744*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 744*FLEN/8, x7, x2, x4) + +inst_398: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8fff; + valaddr_reg:x6; val_offset:746*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 746*FLEN/8, x7, x2, x4) + +inst_399: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8fff; op2val:0x8000; + valaddr_reg:x6; val_offset:748*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 748*FLEN/8, x7, x2, x4) + +inst_400: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8e00; + valaddr_reg:x6; val_offset:750*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 750*FLEN/8, x7, x2, x4) + +inst_401: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8e00; op2val:0x8000; + valaddr_reg:x6; val_offset:752*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 752*FLEN/8, x7, x2, x4) + +inst_402: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8dff; + valaddr_reg:x6; val_offset:754*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 754*FLEN/8, x7, x2, x4) + +inst_403: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8dff; op2val:0x8000; + valaddr_reg:x6; val_offset:756*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 756*FLEN/8, x7, x2, x4) + +inst_404: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8f00; + valaddr_reg:x6; val_offset:758*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 758*FLEN/8, x7, x2, x4) + +inst_405: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x300 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8f00; op2val:0x8000; + valaddr_reg:x6; val_offset:760*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 760*FLEN/8, x7, x2, x4) + +inst_406: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8cff; + valaddr_reg:x6; val_offset:762*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 762*FLEN/8, x7, x2, x4) + +inst_407: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8cff; op2val:0x8000; + valaddr_reg:x6; val_offset:764*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 764*FLEN/8, x7, x2, x4) + +inst_408: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8f80; + valaddr_reg:x6; val_offset:766*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 766*FLEN/8, x7, x2, x4) + +inst_409: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x380 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8f80; op2val:0x8000; + valaddr_reg:x6; val_offset:768*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 768*FLEN/8, x7, x2, x4) + +inst_410: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8c7f; + valaddr_reg:x6; val_offset:770*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 770*FLEN/8, x7, x2, x4) + +inst_411: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x07f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8c7f; op2val:0x8000; + valaddr_reg:x6; val_offset:772*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 772*FLEN/8, x7, x2, x4) + +inst_412: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8fc0; + valaddr_reg:x6; val_offset:774*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 774*FLEN/8, x7, x2, x4) +RVTEST_SIGBASE(x2,signature_x2_5) + +inst_413: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8fc0; op2val:0x8000; + valaddr_reg:x6; val_offset:776*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 776*FLEN/8, x7, x2, x4) + +inst_414: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8c3f; + valaddr_reg:x6; val_offset:778*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 778*FLEN/8, x7, x2, x4) + +inst_415: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8c3f; op2val:0x8000; + valaddr_reg:x6; val_offset:780*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 780*FLEN/8, x7, x2, x4) + +inst_416: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8fe0; + valaddr_reg:x6; val_offset:782*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 782*FLEN/8, x7, x2, x4) + +inst_417: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8fe0; op2val:0x8000; + valaddr_reg:x6; val_offset:784*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 784*FLEN/8, x7, x2, x4) + +inst_418: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8c1f; + valaddr_reg:x6; val_offset:786*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 786*FLEN/8, x7, x2, x4) + +inst_419: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x01f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8c1f; op2val:0x8000; + valaddr_reg:x6; val_offset:788*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 788*FLEN/8, x7, x2, x4) + +inst_420: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8ff0; + valaddr_reg:x6; val_offset:790*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 790*FLEN/8, x7, x2, x4) + +inst_421: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8ff0; op2val:0x8000; + valaddr_reg:x6; val_offset:792*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 792*FLEN/8, x7, x2, x4) + +inst_422: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8c0f; + valaddr_reg:x6; val_offset:794*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 794*FLEN/8, x7, x2, x4) + +inst_423: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x00f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8c0f; op2val:0x8000; + valaddr_reg:x6; val_offset:796*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 796*FLEN/8, x7, x2, x4) + +inst_424: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8ff8; + valaddr_reg:x6; val_offset:798*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 798*FLEN/8, x7, x2, x4) + +inst_425: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8ff8; op2val:0x8000; + valaddr_reg:x6; val_offset:800*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 800*FLEN/8, x7, x2, x4) + +inst_426: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8c07; + valaddr_reg:x6; val_offset:802*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 802*FLEN/8, x7, x2, x4) + +inst_427: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8c07; op2val:0x8000; + valaddr_reg:x6; val_offset:804*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 804*FLEN/8, x7, x2, x4) + +inst_428: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8ffc; + valaddr_reg:x6; val_offset:806*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 806*FLEN/8, x7, x2, x4) + +inst_429: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8ffc; op2val:0x8000; + valaddr_reg:x6; val_offset:808*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 808*FLEN/8, x7, x2, x4) + +inst_430: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8c03; + valaddr_reg:x6; val_offset:810*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 810*FLEN/8, x7, x2, x4) + +inst_431: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8c03; op2val:0x8000; + valaddr_reg:x6; val_offset:812*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 812*FLEN/8, x7, x2, x4) + +inst_432: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8ffe; + valaddr_reg:x6; val_offset:814*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 814*FLEN/8, x7, x2, x4) + +inst_433: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8ffe; op2val:0x8000; + valaddr_reg:x6; val_offset:816*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 816*FLEN/8, x7, x2, x4) + +inst_434: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8c01; + valaddr_reg:x6; val_offset:818*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 818*FLEN/8, x7, x2, x4) + +inst_435: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8c01; op2val:0x8000; + valaddr_reg:x6; val_offset:820*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 820*FLEN/8, x7, x2, x4) + +inst_436: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x1800; + valaddr_reg:x6; val_offset:822*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 822*FLEN/8, x7, x2, x4) + +inst_437: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1800; op2val:0x3c00; + valaddr_reg:x6; val_offset:824*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 824*FLEN/8, x7, x2, x4) + +inst_438: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x1bff; + valaddr_reg:x6; val_offset:826*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 826*FLEN/8, x7, x2, x4) + +inst_439: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1bff; op2val:0x3c00; + valaddr_reg:x6; val_offset:828*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 828*FLEN/8, x7, x2, x4) + +inst_440: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x1a00; + valaddr_reg:x6; val_offset:830*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 830*FLEN/8, x7, x2, x4) + +inst_441: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1a00; op2val:0x3c00; + valaddr_reg:x6; val_offset:832*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 832*FLEN/8, x7, x2, x4) + +inst_442: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x19ff; + valaddr_reg:x6; val_offset:834*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 834*FLEN/8, x7, x2, x4) + +inst_443: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x19ff; op2val:0x3c00; + valaddr_reg:x6; val_offset:836*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 836*FLEN/8, x7, x2, x4) + +inst_444: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x1b00; + valaddr_reg:x6; val_offset:838*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 838*FLEN/8, x7, x2, x4) + +inst_445: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x300 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1b00; op2val:0x3c00; + valaddr_reg:x6; val_offset:840*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 840*FLEN/8, x7, x2, x4) + +inst_446: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x18ff; + valaddr_reg:x6; val_offset:842*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 842*FLEN/8, x7, x2, x4) + +inst_447: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x18ff; op2val:0x3c00; + valaddr_reg:x6; val_offset:844*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 844*FLEN/8, x7, x2, x4) + +inst_448: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x1b80; + valaddr_reg:x6; val_offset:846*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 846*FLEN/8, x7, x2, x4) + +inst_449: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x380 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1b80; op2val:0x3c00; + valaddr_reg:x6; val_offset:848*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 848*FLEN/8, x7, x2, x4) + +inst_450: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x187f; + valaddr_reg:x6; val_offset:850*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 850*FLEN/8, x7, x2, x4) + +inst_451: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x07f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x187f; op2val:0x3c00; + valaddr_reg:x6; val_offset:852*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 852*FLEN/8, x7, x2, x4) + +inst_452: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x1bc0; + valaddr_reg:x6; val_offset:854*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 854*FLEN/8, x7, x2, x4) + +inst_453: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1bc0; op2val:0x3c00; + valaddr_reg:x6; val_offset:856*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 856*FLEN/8, x7, x2, x4) + +inst_454: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x183f; + valaddr_reg:x6; val_offset:858*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 858*FLEN/8, x7, x2, x4) + +inst_455: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x183f; op2val:0x3c00; + valaddr_reg:x6; val_offset:860*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 860*FLEN/8, x7, x2, x4) + +inst_456: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x1be0; + valaddr_reg:x6; val_offset:862*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 862*FLEN/8, x7, x2, x4) + +inst_457: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1be0; op2val:0x3c00; + valaddr_reg:x6; val_offset:864*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 864*FLEN/8, x7, x2, x4) + +inst_458: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x181f; + valaddr_reg:x6; val_offset:866*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 866*FLEN/8, x7, x2, x4) + +inst_459: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x01f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x181f; op2val:0x3c00; + valaddr_reg:x6; val_offset:868*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 868*FLEN/8, x7, x2, x4) + +inst_460: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x1bf0; + valaddr_reg:x6; val_offset:870*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 870*FLEN/8, x7, x2, x4) + +inst_461: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1bf0; op2val:0x3c00; + valaddr_reg:x6; val_offset:872*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 872*FLEN/8, x7, x2, x4) + +inst_462: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x180f; + valaddr_reg:x6; val_offset:874*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 874*FLEN/8, x7, x2, x4) + +inst_463: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x00f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x180f; op2val:0x3c00; + valaddr_reg:x6; val_offset:876*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 876*FLEN/8, x7, x2, x4) + +inst_464: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x1bf8; + valaddr_reg:x6; val_offset:878*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 878*FLEN/8, x7, x2, x4) + +inst_465: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1bf8; op2val:0x3c00; + valaddr_reg:x6; val_offset:880*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 880*FLEN/8, x7, x2, x4) + +inst_466: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x1807; + valaddr_reg:x6; val_offset:882*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 882*FLEN/8, x7, x2, x4) + +inst_467: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1807; op2val:0x3c00; + valaddr_reg:x6; val_offset:884*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 884*FLEN/8, x7, x2, x4) + +inst_468: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x1bfc; + valaddr_reg:x6; val_offset:886*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 886*FLEN/8, x7, x2, x4) + +inst_469: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1bfc; op2val:0x3c00; + valaddr_reg:x6; val_offset:888*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 888*FLEN/8, x7, x2, x4) + +inst_470: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x1803; + valaddr_reg:x6; val_offset:890*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 890*FLEN/8, x7, x2, x4) + +inst_471: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x003 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1803; op2val:0x3c00; + valaddr_reg:x6; val_offset:892*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 892*FLEN/8, x7, x2, x4) + +inst_472: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x1bfe; + valaddr_reg:x6; val_offset:894*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 894*FLEN/8, x7, x2, x4) + +inst_473: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1bfe; op2val:0x3c00; + valaddr_reg:x6; val_offset:896*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 896*FLEN/8, x7, x2, x4) + +inst_474: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x1801; + valaddr_reg:x6; val_offset:898*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 898*FLEN/8, x7, x2, x4) + +inst_475: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1801; op2val:0x3c00; + valaddr_reg:x6; val_offset:900*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 900*FLEN/8, x7, x2, x4) + +inst_476: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3ffe; + valaddr_reg:x6; val_offset:902*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 902*FLEN/8, x7, x2, x4) + +inst_477: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ffe; op2val:0x3c00; + valaddr_reg:x6; val_offset:904*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 904*FLEN/8, x7, x2, x4) + +inst_478: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3c01; + valaddr_reg:x6; val_offset:906*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 906*FLEN/8, x7, x2, x4) + +inst_479: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c01; op2val:0x3c00; + valaddr_reg:x6; val_offset:908*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 908*FLEN/8, x7, x2, x4) + +inst_480: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1b6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3db6; + valaddr_reg:x6; val_offset:910*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 910*FLEN/8, x7, x2, x4) + +inst_481: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x1b6 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3db6; op2val:0x3c00; + valaddr_reg:x6; val_offset:912*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 912*FLEN/8, x7, x2, x4) + +inst_482: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x36d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3f6d; + valaddr_reg:x6; val_offset:914*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 914*FLEN/8, x7, x2, x4) + +inst_483: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x36d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3f6d; op2val:0x3c00; + valaddr_reg:x6; val_offset:916*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 916*FLEN/8, x7, x2, x4) + +inst_484: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0cc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3ccc; + valaddr_reg:x6; val_offset:918*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 918*FLEN/8, x7, x2, x4) + +inst_485: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x0cc and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ccc; op2val:0x3c00; + valaddr_reg:x6; val_offset:920*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 920*FLEN/8, x7, x2, x4) + +inst_486: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x333 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3f33; + valaddr_reg:x6; val_offset:922*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 922*FLEN/8, x7, x2, x4) + +inst_487: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x333 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3f33; op2val:0x3c00; + valaddr_reg:x6; val_offset:924*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 924*FLEN/8, x7, x2, x4) + +inst_488: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1dd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3ddd; + valaddr_reg:x6; val_offset:926*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 926*FLEN/8, x7, x2, x4) + +inst_489: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x1dd and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ddd; op2val:0x3c00; + valaddr_reg:x6; val_offset:928*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 928*FLEN/8, x7, x2, x4) + +inst_490: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x222 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3e22; + valaddr_reg:x6; val_offset:930*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 930*FLEN/8, x7, x2, x4) + +inst_491: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x222 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3e22; op2val:0x3c00; + valaddr_reg:x6; val_offset:932*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 932*FLEN/8, x7, x2, x4) + +inst_492: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x124 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3d24; + valaddr_reg:x6; val_offset:934*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 934*FLEN/8, x7, x2, x4) + +inst_493: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x124 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3d24; op2val:0x3c00; + valaddr_reg:x6; val_offset:936*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 936*FLEN/8, x7, x2, x4) + +inst_494: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2db and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3edb; + valaddr_reg:x6; val_offset:938*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 938*FLEN/8, x7, x2, x4) + +inst_495: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x2db and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3edb; op2val:0x3c00; + valaddr_reg:x6; val_offset:940*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 940*FLEN/8, x7, x2, x4) + +inst_496: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x199 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3d99; + valaddr_reg:x6; val_offset:942*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 942*FLEN/8, x7, x2, x4) + +inst_497: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x199 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3d99; op2val:0x3c00; + valaddr_reg:x6; val_offset:944*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 944*FLEN/8, x7, x2, x4) + +inst_498: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x266 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3e66; + valaddr_reg:x6; val_offset:946*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 946*FLEN/8, x7, x2, x4) + +inst_499: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x266 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3e66; op2val:0x3c00; + valaddr_reg:x6; val_offset:948*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 948*FLEN/8, x7, x2, x4) + +inst_500: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7400; + valaddr_reg:x6; val_offset:950*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 950*FLEN/8, x7, x2, x4) + +inst_501: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7400; op2val:0x3c00; + valaddr_reg:x6; val_offset:952*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 952*FLEN/8, x7, x2, x4) + +inst_502: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x77ff; + valaddr_reg:x6; val_offset:954*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 954*FLEN/8, x7, x2, x4) + +inst_503: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77ff; op2val:0x3c00; + valaddr_reg:x6; val_offset:956*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 956*FLEN/8, x7, x2, x4) + +inst_504: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7600; + valaddr_reg:x6; val_offset:958*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 958*FLEN/8, x7, x2, x4) + +inst_505: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7600; op2val:0x3c00; + valaddr_reg:x6; val_offset:960*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 960*FLEN/8, x7, x2, x4) + +inst_506: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x75ff; + valaddr_reg:x6; val_offset:962*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 962*FLEN/8, x7, x2, x4) + +inst_507: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x75ff; op2val:0x3c00; + valaddr_reg:x6; val_offset:964*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 964*FLEN/8, x7, x2, x4) + +inst_508: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7700; + valaddr_reg:x6; val_offset:966*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 966*FLEN/8, x7, x2, x4) + +inst_509: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x300 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7700; op2val:0x3c00; + valaddr_reg:x6; val_offset:968*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 968*FLEN/8, x7, x2, x4) + +inst_510: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x74ff; + valaddr_reg:x6; val_offset:970*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 970*FLEN/8, x7, x2, x4) + +inst_511: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x74ff; op2val:0x3c00; + valaddr_reg:x6; val_offset:972*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 972*FLEN/8, x7, x2, x4) + +inst_512: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7780; + valaddr_reg:x6; val_offset:974*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 974*FLEN/8, x7, x2, x4) + +inst_513: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x380 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7780; op2val:0x3c00; + valaddr_reg:x6; val_offset:976*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 976*FLEN/8, x7, x2, x4) + +inst_514: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x747f; + valaddr_reg:x6; val_offset:978*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 978*FLEN/8, x7, x2, x4) + +inst_515: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x07f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x747f; op2val:0x3c00; + valaddr_reg:x6; val_offset:980*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 980*FLEN/8, x7, x2, x4) + +inst_516: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x77c0; + valaddr_reg:x6; val_offset:982*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 982*FLEN/8, x7, x2, x4) + +inst_517: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77c0; op2val:0x3c00; + valaddr_reg:x6; val_offset:984*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 984*FLEN/8, x7, x2, x4) + +inst_518: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x743f; + valaddr_reg:x6; val_offset:986*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 986*FLEN/8, x7, x2, x4) + +inst_519: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x03f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x743f; op2val:0x3c00; + valaddr_reg:x6; val_offset:988*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 988*FLEN/8, x7, x2, x4) + +inst_520: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x77e0; + valaddr_reg:x6; val_offset:990*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 990*FLEN/8, x7, x2, x4) + +inst_521: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77e0; op2val:0x3c00; + valaddr_reg:x6; val_offset:992*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 992*FLEN/8, x7, x2, x4) + +inst_522: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x741f; + valaddr_reg:x6; val_offset:994*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 994*FLEN/8, x7, x2, x4) + +inst_523: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x01f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x741f; op2val:0x3c00; + valaddr_reg:x6; val_offset:996*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 996*FLEN/8, x7, x2, x4) + +inst_524: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x77f0; + valaddr_reg:x6; val_offset:998*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 998*FLEN/8, x7, x2, x4) + +inst_525: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77f0; op2val:0x3c00; + valaddr_reg:x6; val_offset:1000*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1000*FLEN/8, x7, x2, x4) + +inst_526: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x740f; + valaddr_reg:x6; val_offset:1002*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1002*FLEN/8, x7, x2, x4) + +inst_527: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x00f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x740f; op2val:0x3c00; + valaddr_reg:x6; val_offset:1004*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1004*FLEN/8, x7, x2, x4) + +inst_528: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x77f8; + valaddr_reg:x6; val_offset:1006*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1006*FLEN/8, x7, x2, x4) + +inst_529: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77f8; op2val:0x3c00; + valaddr_reg:x6; val_offset:1008*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1008*FLEN/8, x7, x2, x4) + +inst_530: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7407; + valaddr_reg:x6; val_offset:1010*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1010*FLEN/8, x7, x2, x4) + +inst_531: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x007 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7407; op2val:0x3c00; + valaddr_reg:x6; val_offset:1012*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1012*FLEN/8, x7, x2, x4) + +inst_532: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x77fc; + valaddr_reg:x6; val_offset:1014*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1014*FLEN/8, x7, x2, x4) + +inst_533: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77fc; op2val:0x3c00; + valaddr_reg:x6; val_offset:1016*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1016*FLEN/8, x7, x2, x4) + +inst_534: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7403; + valaddr_reg:x6; val_offset:1018*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1018*FLEN/8, x7, x2, x4) + +inst_535: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x003 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7403; op2val:0x3c00; + valaddr_reg:x6; val_offset:1020*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1020*FLEN/8, x7, x2, x4) + +inst_536: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x77fe; + valaddr_reg:x6; val_offset:1022*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1022*FLEN/8, x7, x2, x4) + +inst_537: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77fe; op2val:0x3c00; + valaddr_reg:x6; val_offset:1024*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1024*FLEN/8, x7, x2, x4) + +inst_538: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7401; + valaddr_reg:x6; val_offset:1026*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1026*FLEN/8, x7, x2, x4) + +inst_539: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7401; op2val:0x3c00; + valaddr_reg:x6; val_offset:1028*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1028*FLEN/8, x7, x2, x4) + +inst_540: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2c00; + valaddr_reg:x6; val_offset:1030*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1030*FLEN/8, x7, x2, x4) +RVTEST_SIGBASE(x2,signature_x2_6) + +inst_541: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2c00; op2val:0x3c00; + valaddr_reg:x6; val_offset:1032*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1032*FLEN/8, x7, x2, x4) + +inst_542: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2fff; + valaddr_reg:x6; val_offset:1034*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1034*FLEN/8, x7, x2, x4) + +inst_543: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2fff; op2val:0x3c00; + valaddr_reg:x6; val_offset:1036*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1036*FLEN/8, x7, x2, x4) + +inst_544: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2e00; + valaddr_reg:x6; val_offset:1038*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1038*FLEN/8, x7, x2, x4) + +inst_545: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e00; op2val:0x3c00; + valaddr_reg:x6; val_offset:1040*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1040*FLEN/8, x7, x2, x4) + +inst_546: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2dff; + valaddr_reg:x6; val_offset:1042*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1042*FLEN/8, x7, x2, x4) + +inst_547: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2dff; op2val:0x3c00; + valaddr_reg:x6; val_offset:1044*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1044*FLEN/8, x7, x2, x4) + +inst_548: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2f00; + valaddr_reg:x6; val_offset:1046*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1046*FLEN/8, x7, x2, x4) + +inst_549: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x300 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2f00; op2val:0x3c00; + valaddr_reg:x6; val_offset:1048*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1048*FLEN/8, x7, x2, x4) + +inst_550: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2cff; + valaddr_reg:x6; val_offset:1050*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1050*FLEN/8, x7, x2, x4) + +inst_551: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2cff; op2val:0x3c00; + valaddr_reg:x6; val_offset:1052*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1052*FLEN/8, x7, x2, x4) + +inst_552: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2f80; + valaddr_reg:x6; val_offset:1054*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1054*FLEN/8, x7, x2, x4) + +inst_553: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x380 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2f80; op2val:0x3c00; + valaddr_reg:x6; val_offset:1056*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1056*FLEN/8, x7, x2, x4) + +inst_554: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2c7f; + valaddr_reg:x6; val_offset:1058*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1058*FLEN/8, x7, x2, x4) + +inst_555: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x07f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2c7f; op2val:0x3c00; + valaddr_reg:x6; val_offset:1060*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1060*FLEN/8, x7, x2, x4) + +inst_556: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2fc0; + valaddr_reg:x6; val_offset:1062*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1062*FLEN/8, x7, x2, x4) + +inst_557: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2fc0; op2val:0x3c00; + valaddr_reg:x6; val_offset:1064*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1064*FLEN/8, x7, x2, x4) + +inst_558: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2c3f; + valaddr_reg:x6; val_offset:1066*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1066*FLEN/8, x7, x2, x4) + +inst_559: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x03f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2c3f; op2val:0x3c00; + valaddr_reg:x6; val_offset:1068*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1068*FLEN/8, x7, x2, x4) + +inst_560: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2fe0; + valaddr_reg:x6; val_offset:1070*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1070*FLEN/8, x7, x2, x4) + +inst_561: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2fe0; op2val:0x3c00; + valaddr_reg:x6; val_offset:1072*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1072*FLEN/8, x7, x2, x4) + +inst_562: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2c1f; + valaddr_reg:x6; val_offset:1074*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1074*FLEN/8, x7, x2, x4) + +inst_563: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x01f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2c1f; op2val:0x3c00; + valaddr_reg:x6; val_offset:1076*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1076*FLEN/8, x7, x2, x4) + +inst_564: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2ff0; + valaddr_reg:x6; val_offset:1078*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1078*FLEN/8, x7, x2, x4) + +inst_565: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ff0; op2val:0x3c00; + valaddr_reg:x6; val_offset:1080*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1080*FLEN/8, x7, x2, x4) + +inst_566: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2c0f; + valaddr_reg:x6; val_offset:1082*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1082*FLEN/8, x7, x2, x4) + +inst_567: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x00f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2c0f; op2val:0x3c00; + valaddr_reg:x6; val_offset:1084*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1084*FLEN/8, x7, x2, x4) + +inst_568: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2ff8; + valaddr_reg:x6; val_offset:1086*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1086*FLEN/8, x7, x2, x4) + +inst_569: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ff8; op2val:0x3c00; + valaddr_reg:x6; val_offset:1088*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1088*FLEN/8, x7, x2, x4) + +inst_570: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2c07; + valaddr_reg:x6; val_offset:1090*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1090*FLEN/8, x7, x2, x4) + +inst_571: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x007 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2c07; op2val:0x3c00; + valaddr_reg:x6; val_offset:1092*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1092*FLEN/8, x7, x2, x4) + +inst_572: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2ffc; + valaddr_reg:x6; val_offset:1094*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1094*FLEN/8, x7, x2, x4) + +inst_573: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ffc; op2val:0x3c00; + valaddr_reg:x6; val_offset:1096*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1096*FLEN/8, x7, x2, x4) + +inst_574: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2c03; + valaddr_reg:x6; val_offset:1098*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1098*FLEN/8, x7, x2, x4) + +inst_575: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x003 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2c03; op2val:0x3c00; + valaddr_reg:x6; val_offset:1100*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1100*FLEN/8, x7, x2, x4) + +inst_576: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2ffe; + valaddr_reg:x6; val_offset:1102*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1102*FLEN/8, x7, x2, x4) + +inst_577: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ffe; op2val:0x3c00; + valaddr_reg:x6; val_offset:1104*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1104*FLEN/8, x7, x2, x4) + +inst_578: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2c01; + valaddr_reg:x6; val_offset:1106*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1106*FLEN/8, x7, x2, x4) + +inst_579: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2c01; op2val:0x3c00; + valaddr_reg:x6; val_offset:1108*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1108*FLEN/8, x7, x2, x4) + +inst_580: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3000; + valaddr_reg:x6; val_offset:1110*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1110*FLEN/8, x7, x2, x4) + +inst_581: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3000; op2val:0x3c00; + valaddr_reg:x6; val_offset:1112*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1112*FLEN/8, x7, x2, x4) + +inst_582: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x33ff; + valaddr_reg:x6; val_offset:1114*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1114*FLEN/8, x7, x2, x4) + +inst_583: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x33ff; op2val:0x3c00; + valaddr_reg:x6; val_offset:1116*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1116*FLEN/8, x7, x2, x4) + +inst_584: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3200; + valaddr_reg:x6; val_offset:1118*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1118*FLEN/8, x7, x2, x4) + +inst_585: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3200; op2val:0x3c00; + valaddr_reg:x6; val_offset:1120*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1120*FLEN/8, x7, x2, x4) + +inst_586: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x31ff; + valaddr_reg:x6; val_offset:1122*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1122*FLEN/8, x7, x2, x4) + +inst_587: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x31ff; op2val:0x3c00; + valaddr_reg:x6; val_offset:1124*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1124*FLEN/8, x7, x2, x4) + +inst_588: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3300; + valaddr_reg:x6; val_offset:1126*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1126*FLEN/8, x7, x2, x4) + +inst_589: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x300 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3300; op2val:0x3c00; + valaddr_reg:x6; val_offset:1128*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1128*FLEN/8, x7, x2, x4) + +inst_590: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x30ff; + valaddr_reg:x6; val_offset:1130*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1130*FLEN/8, x7, x2, x4) + +inst_591: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x30ff; op2val:0x3c00; + valaddr_reg:x6; val_offset:1132*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1132*FLEN/8, x7, x2, x4) + +inst_592: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3380; + valaddr_reg:x6; val_offset:1134*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1134*FLEN/8, x7, x2, x4) + +inst_593: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x380 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3380; op2val:0x3c00; + valaddr_reg:x6; val_offset:1136*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1136*FLEN/8, x7, x2, x4) + +inst_594: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x307f; + valaddr_reg:x6; val_offset:1138*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1138*FLEN/8, x7, x2, x4) + +inst_595: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x07f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x307f; op2val:0x3c00; + valaddr_reg:x6; val_offset:1140*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1140*FLEN/8, x7, x2, x4) + +inst_596: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x33c0; + valaddr_reg:x6; val_offset:1142*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1142*FLEN/8, x7, x2, x4) + +inst_597: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x33c0; op2val:0x3c00; + valaddr_reg:x6; val_offset:1144*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1144*FLEN/8, x7, x2, x4) + +inst_598: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x303f; + valaddr_reg:x6; val_offset:1146*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1146*FLEN/8, x7, x2, x4) + +inst_599: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x03f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x303f; op2val:0x3c00; + valaddr_reg:x6; val_offset:1148*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1148*FLEN/8, x7, x2, x4) + +inst_600: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x33e0; + valaddr_reg:x6; val_offset:1150*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1150*FLEN/8, x7, x2, x4) + +inst_601: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x33e0; op2val:0x3c00; + valaddr_reg:x6; val_offset:1152*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1152*FLEN/8, x7, x2, x4) + +inst_602: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x301f; + valaddr_reg:x6; val_offset:1154*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1154*FLEN/8, x7, x2, x4) + +inst_603: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x01f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x301f; op2val:0x3c00; + valaddr_reg:x6; val_offset:1156*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1156*FLEN/8, x7, x2, x4) + +inst_604: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x33f0; + valaddr_reg:x6; val_offset:1158*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1158*FLEN/8, x7, x2, x4) + +inst_605: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x33f0; op2val:0x3c00; + valaddr_reg:x6; val_offset:1160*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1160*FLEN/8, x7, x2, x4) + +inst_606: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x300f; + valaddr_reg:x6; val_offset:1162*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1162*FLEN/8, x7, x2, x4) + +inst_607: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x00f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x300f; op2val:0x3c00; + valaddr_reg:x6; val_offset:1164*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1164*FLEN/8, x7, x2, x4) + +inst_608: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x33f8; + valaddr_reg:x6; val_offset:1166*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1166*FLEN/8, x7, x2, x4) + +inst_609: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x33f8; op2val:0x3c00; + valaddr_reg:x6; val_offset:1168*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1168*FLEN/8, x7, x2, x4) + +inst_610: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3007; + valaddr_reg:x6; val_offset:1170*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1170*FLEN/8, x7, x2, x4) + +inst_611: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x007 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3007; op2val:0x3c00; + valaddr_reg:x6; val_offset:1172*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1172*FLEN/8, x7, x2, x4) + +inst_612: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x33fc; + valaddr_reg:x6; val_offset:1174*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1174*FLEN/8, x7, x2, x4) + +inst_613: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x33fc; op2val:0x3c00; + valaddr_reg:x6; val_offset:1176*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1176*FLEN/8, x7, x2, x4) + +inst_614: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3003; + valaddr_reg:x6; val_offset:1178*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1178*FLEN/8, x7, x2, x4) + +inst_615: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x003 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3003; op2val:0x3c00; + valaddr_reg:x6; val_offset:1180*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1180*FLEN/8, x7, x2, x4) + +inst_616: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x33fe; + valaddr_reg:x6; val_offset:1182*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1182*FLEN/8, x7, x2, x4) + +inst_617: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x33fe; op2val:0x3c00; + valaddr_reg:x6; val_offset:1184*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1184*FLEN/8, x7, x2, x4) + +inst_618: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3001; + valaddr_reg:x6; val_offset:1186*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1186*FLEN/8, x7, x2, x4) + +inst_619: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3001; op2val:0x3c00; + valaddr_reg:x6; val_offset:1188*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1188*FLEN/8, x7, x2, x4) + +inst_620: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3400; + valaddr_reg:x6; val_offset:1190*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1190*FLEN/8, x7, x2, x4) + +inst_621: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3400; op2val:0x3c00; + valaddr_reg:x6; val_offset:1192*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1192*FLEN/8, x7, x2, x4) + +inst_622: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x37ff; + valaddr_reg:x6; val_offset:1194*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1194*FLEN/8, x7, x2, x4) + +inst_623: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x37ff; op2val:0x3c00; + valaddr_reg:x6; val_offset:1196*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1196*FLEN/8, x7, x2, x4) + +inst_624: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3600; + valaddr_reg:x6; val_offset:1198*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1198*FLEN/8, x7, x2, x4) + +inst_625: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3600; op2val:0x3c00; + valaddr_reg:x6; val_offset:1200*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1200*FLEN/8, x7, x2, x4) + +inst_626: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x35ff; + valaddr_reg:x6; val_offset:1202*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1202*FLEN/8, x7, x2, x4) + +inst_627: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x35ff; op2val:0x3c00; + valaddr_reg:x6; val_offset:1204*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1204*FLEN/8, x7, x2, x4) + +inst_628: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3700; + valaddr_reg:x6; val_offset:1206*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1206*FLEN/8, x7, x2, x4) + +inst_629: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x300 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3700; op2val:0x3c00; + valaddr_reg:x6; val_offset:1208*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1208*FLEN/8, x7, x2, x4) + +inst_630: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x34ff; + valaddr_reg:x6; val_offset:1210*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1210*FLEN/8, x7, x2, x4) + +inst_631: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x34ff; op2val:0x3c00; + valaddr_reg:x6; val_offset:1212*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1212*FLEN/8, x7, x2, x4) + +inst_632: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3780; + valaddr_reg:x6; val_offset:1214*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1214*FLEN/8, x7, x2, x4) + +inst_633: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x380 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3780; op2val:0x3c00; + valaddr_reg:x6; val_offset:1216*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1216*FLEN/8, x7, x2, x4) + +inst_634: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x347f; + valaddr_reg:x6; val_offset:1218*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1218*FLEN/8, x7, x2, x4) + +inst_635: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x07f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x347f; op2val:0x3c00; + valaddr_reg:x6; val_offset:1220*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1220*FLEN/8, x7, x2, x4) + +inst_636: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x37c0; + valaddr_reg:x6; val_offset:1222*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1222*FLEN/8, x7, x2, x4) + +inst_637: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x37c0; op2val:0x3c00; + valaddr_reg:x6; val_offset:1224*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1224*FLEN/8, x7, x2, x4) + +inst_638: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x343f; + valaddr_reg:x6; val_offset:1226*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1226*FLEN/8, x7, x2, x4) + +inst_639: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x03f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x343f; op2val:0x3c00; + valaddr_reg:x6; val_offset:1228*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1228*FLEN/8, x7, x2, x4) + +inst_640: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x37e0; + valaddr_reg:x6; val_offset:1230*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1230*FLEN/8, x7, x2, x4) + +inst_641: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x37e0; op2val:0x3c00; + valaddr_reg:x6; val_offset:1232*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1232*FLEN/8, x7, x2, x4) + +inst_642: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x341f; + valaddr_reg:x6; val_offset:1234*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1234*FLEN/8, x7, x2, x4) + +inst_643: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x01f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x341f; op2val:0x3c00; + valaddr_reg:x6; val_offset:1236*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1236*FLEN/8, x7, x2, x4) + +inst_644: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x37f0; + valaddr_reg:x6; val_offset:1238*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1238*FLEN/8, x7, x2, x4) + +inst_645: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x37f0; op2val:0x3c00; + valaddr_reg:x6; val_offset:1240*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1240*FLEN/8, x7, x2, x4) + +inst_646: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x340f; + valaddr_reg:x6; val_offset:1242*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1242*FLEN/8, x7, x2, x4) + +inst_647: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x00f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x340f; op2val:0x3c00; + valaddr_reg:x6; val_offset:1244*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1244*FLEN/8, x7, x2, x4) + +inst_648: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x37f8; + valaddr_reg:x6; val_offset:1246*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1246*FLEN/8, x7, x2, x4) + +inst_649: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x37f8; op2val:0x3c00; + valaddr_reg:x6; val_offset:1248*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1248*FLEN/8, x7, x2, x4) + +inst_650: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3407; + valaddr_reg:x6; val_offset:1250*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1250*FLEN/8, x7, x2, x4) + +inst_651: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x007 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3407; op2val:0x3c00; + valaddr_reg:x6; val_offset:1252*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1252*FLEN/8, x7, x2, x4) + +inst_652: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x37fc; + valaddr_reg:x6; val_offset:1254*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1254*FLEN/8, x7, x2, x4) + +inst_653: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x37fc; op2val:0x3c00; + valaddr_reg:x6; val_offset:1256*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1256*FLEN/8, x7, x2, x4) + +inst_654: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3403; + valaddr_reg:x6; val_offset:1258*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1258*FLEN/8, x7, x2, x4) + +inst_655: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x003 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3403; op2val:0x3c00; + valaddr_reg:x6; val_offset:1260*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1260*FLEN/8, x7, x2, x4) + +inst_656: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x37fe; + valaddr_reg:x6; val_offset:1262*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1262*FLEN/8, x7, x2, x4) + +inst_657: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x37fe; op2val:0x3c00; + valaddr_reg:x6; val_offset:1264*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1264*FLEN/8, x7, x2, x4) + +inst_658: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3401; + valaddr_reg:x6; val_offset:1266*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1266*FLEN/8, x7, x2, x4) + +inst_659: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3401; op2val:0x3c00; + valaddr_reg:x6; val_offset:1268*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1268*FLEN/8, x7, x2, x4) + +inst_660: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3800; + valaddr_reg:x6; val_offset:1270*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1270*FLEN/8, x7, x2, x4) + +inst_661: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3800; op2val:0x3c00; + valaddr_reg:x6; val_offset:1272*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1272*FLEN/8, x7, x2, x4) + +inst_662: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3bff; + valaddr_reg:x6; val_offset:1274*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1274*FLEN/8, x7, x2, x4) + +inst_663: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bff; op2val:0x3c00; + valaddr_reg:x6; val_offset:1276*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1276*FLEN/8, x7, x2, x4) + +inst_664: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3a00; + valaddr_reg:x6; val_offset:1278*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1278*FLEN/8, x7, x2, x4) + +inst_665: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a00; op2val:0x3c00; + valaddr_reg:x6; val_offset:1280*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1280*FLEN/8, x7, x2, x4) + +inst_666: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x39ff; + valaddr_reg:x6; val_offset:1282*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1282*FLEN/8, x7, x2, x4) + +inst_667: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x39ff; op2val:0x3c00; + valaddr_reg:x6; val_offset:1284*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1284*FLEN/8, x7, x2, x4) + +inst_668: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3b00; + valaddr_reg:x6; val_offset:1286*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1286*FLEN/8, x7, x2, x4) +RVTEST_SIGBASE(x2,signature_x2_7) + +inst_669: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x300 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b00; op2val:0x3c00; + valaddr_reg:x6; val_offset:1288*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1288*FLEN/8, x7, x2, x4) + +inst_670: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x38ff; + valaddr_reg:x6; val_offset:1290*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1290*FLEN/8, x7, x2, x4) + +inst_671: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x38ff; op2val:0x3c00; + valaddr_reg:x6; val_offset:1292*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1292*FLEN/8, x7, x2, x4) + +inst_672: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3b80; + valaddr_reg:x6; val_offset:1294*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1294*FLEN/8, x7, x2, x4) + +inst_673: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x380 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b80; op2val:0x3c00; + valaddr_reg:x6; val_offset:1296*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1296*FLEN/8, x7, x2, x4) + +inst_674: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x387f; + valaddr_reg:x6; val_offset:1298*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1298*FLEN/8, x7, x2, x4) + +inst_675: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x07f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x387f; op2val:0x3c00; + valaddr_reg:x6; val_offset:1300*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1300*FLEN/8, x7, x2, x4) + +inst_676: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3bc0; + valaddr_reg:x6; val_offset:1302*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1302*FLEN/8, x7, x2, x4) + +inst_677: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bc0; op2val:0x3c00; + valaddr_reg:x6; val_offset:1304*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1304*FLEN/8, x7, x2, x4) + +inst_678: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x383f; + valaddr_reg:x6; val_offset:1306*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1306*FLEN/8, x7, x2, x4) + +inst_679: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x03f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x383f; op2val:0x3c00; + valaddr_reg:x6; val_offset:1308*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1308*FLEN/8, x7, x2, x4) + +inst_680: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3be0; + valaddr_reg:x6; val_offset:1310*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1310*FLEN/8, x7, x2, x4) + +inst_681: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3be0; op2val:0x3c00; + valaddr_reg:x6; val_offset:1312*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1312*FLEN/8, x7, x2, x4) + +inst_682: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x381f; + valaddr_reg:x6; val_offset:1314*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1314*FLEN/8, x7, x2, x4) + +inst_683: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x01f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x381f; op2val:0x3c00; + valaddr_reg:x6; val_offset:1316*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1316*FLEN/8, x7, x2, x4) + +inst_684: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3bf0; + valaddr_reg:x6; val_offset:1318*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1318*FLEN/8, x7, x2, x4) + +inst_685: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bf0; op2val:0x3c00; + valaddr_reg:x6; val_offset:1320*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1320*FLEN/8, x7, x2, x4) + +inst_686: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x380f; + valaddr_reg:x6; val_offset:1322*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1322*FLEN/8, x7, x2, x4) + +inst_687: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x00f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x380f; op2val:0x3c00; + valaddr_reg:x6; val_offset:1324*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1324*FLEN/8, x7, x2, x4) + +inst_688: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3bf8; + valaddr_reg:x6; val_offset:1326*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1326*FLEN/8, x7, x2, x4) + +inst_689: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bf8; op2val:0x3c00; + valaddr_reg:x6; val_offset:1328*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1328*FLEN/8, x7, x2, x4) + +inst_690: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3807; + valaddr_reg:x6; val_offset:1330*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1330*FLEN/8, x7, x2, x4) + +inst_691: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x007 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3807; op2val:0x3c00; + valaddr_reg:x6; val_offset:1332*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1332*FLEN/8, x7, x2, x4) + +inst_692: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3bfc; + valaddr_reg:x6; val_offset:1334*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1334*FLEN/8, x7, x2, x4) + +inst_693: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bfc; op2val:0x3c00; + valaddr_reg:x6; val_offset:1336*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1336*FLEN/8, x7, x2, x4) + +inst_694: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3803; + valaddr_reg:x6; val_offset:1338*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1338*FLEN/8, x7, x2, x4) + +inst_695: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x003 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3803; op2val:0x3c00; + valaddr_reg:x6; val_offset:1340*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1340*FLEN/8, x7, x2, x4) + +inst_696: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3bfe; + valaddr_reg:x6; val_offset:1342*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1342*FLEN/8, x7, x2, x4) + +inst_697: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bfe; op2val:0x3c00; + valaddr_reg:x6; val_offset:1344*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1344*FLEN/8, x7, x2, x4) + +inst_698: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3801; + valaddr_reg:x6; val_offset:1346*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1346*FLEN/8, x7, x2, x4) + +inst_699: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3801; op2val:0x3c00; + valaddr_reg:x6; val_offset:1348*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1348*FLEN/8, x7, x2, x4) + +inst_700: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3c00; + valaddr_reg:x6; val_offset:1350*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1350*FLEN/8, x7, x2, x4) + +inst_701: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3fff; + valaddr_reg:x6; val_offset:1352*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1352*FLEN/8, x7, x2, x4) + +inst_702: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fff; op2val:0x3c00; + valaddr_reg:x6; val_offset:1354*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1354*FLEN/8, x7, x2, x4) + +inst_703: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3e00; + valaddr_reg:x6; val_offset:1356*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1356*FLEN/8, x7, x2, x4) + +inst_704: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3e00; op2val:0x3c00; + valaddr_reg:x6; val_offset:1358*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1358*FLEN/8, x7, x2, x4) + +inst_705: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3dff; + valaddr_reg:x6; val_offset:1360*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1360*FLEN/8, x7, x2, x4) + +inst_706: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3dff; op2val:0x3c00; + valaddr_reg:x6; val_offset:1362*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1362*FLEN/8, x7, x2, x4) + +inst_707: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3f00; + valaddr_reg:x6; val_offset:1364*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1364*FLEN/8, x7, x2, x4) + +inst_708: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x300 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3f00; op2val:0x3c00; + valaddr_reg:x6; val_offset:1366*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1366*FLEN/8, x7, x2, x4) + +inst_709: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3cff; + valaddr_reg:x6; val_offset:1368*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1368*FLEN/8, x7, x2, x4) + +inst_710: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3cff; op2val:0x3c00; + valaddr_reg:x6; val_offset:1370*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1370*FLEN/8, x7, x2, x4) + +inst_711: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3f80; + valaddr_reg:x6; val_offset:1372*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1372*FLEN/8, x7, x2, x4) + +inst_712: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x380 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3f80; op2val:0x3c00; + valaddr_reg:x6; val_offset:1374*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1374*FLEN/8, x7, x2, x4) + +inst_713: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3c7f; + valaddr_reg:x6; val_offset:1376*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1376*FLEN/8, x7, x2, x4) + +inst_714: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x07f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c7f; op2val:0x3c00; + valaddr_reg:x6; val_offset:1378*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1378*FLEN/8, x7, x2, x4) + +inst_715: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3fc0; + valaddr_reg:x6; val_offset:1380*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1380*FLEN/8, x7, x2, x4) + +inst_716: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fc0; op2val:0x3c00; + valaddr_reg:x6; val_offset:1382*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1382*FLEN/8, x7, x2, x4) + +inst_717: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3c3f; + valaddr_reg:x6; val_offset:1384*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1384*FLEN/8, x7, x2, x4) + +inst_718: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x03f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c3f; op2val:0x3c00; + valaddr_reg:x6; val_offset:1386*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1386*FLEN/8, x7, x2, x4) + +inst_719: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3fe0; + valaddr_reg:x6; val_offset:1388*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1388*FLEN/8, x7, x2, x4) + +inst_720: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fe0; op2val:0x3c00; + valaddr_reg:x6; val_offset:1390*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1390*FLEN/8, x7, x2, x4) + +inst_721: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3c1f; + valaddr_reg:x6; val_offset:1392*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1392*FLEN/8, x7, x2, x4) + +inst_722: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x01f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c1f; op2val:0x3c00; + valaddr_reg:x6; val_offset:1394*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1394*FLEN/8, x7, x2, x4) + +inst_723: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3ff0; + valaddr_reg:x6; val_offset:1396*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1396*FLEN/8, x7, x2, x4) + +inst_724: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff0; op2val:0x3c00; + valaddr_reg:x6; val_offset:1398*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1398*FLEN/8, x7, x2, x4) + +inst_725: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3c0f; + valaddr_reg:x6; val_offset:1400*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1400*FLEN/8, x7, x2, x4) + +inst_726: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x00f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c0f; op2val:0x3c00; + valaddr_reg:x6; val_offset:1402*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1402*FLEN/8, x7, x2, x4) + +inst_727: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3ff8; + valaddr_reg:x6; val_offset:1404*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1404*FLEN/8, x7, x2, x4) + +inst_728: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff8; op2val:0x3c00; + valaddr_reg:x6; val_offset:1406*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1406*FLEN/8, x7, x2, x4) + +inst_729: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3c07; + valaddr_reg:x6; val_offset:1408*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1408*FLEN/8, x7, x2, x4) + +inst_730: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x007 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c07; op2val:0x3c00; + valaddr_reg:x6; val_offset:1410*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1410*FLEN/8, x7, x2, x4) + +inst_731: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3ffc; + valaddr_reg:x6; val_offset:1412*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1412*FLEN/8, x7, x2, x4) + +inst_732: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ffc; op2val:0x3c00; + valaddr_reg:x6; val_offset:1414*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1414*FLEN/8, x7, x2, x4) + +inst_733: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3c03; + valaddr_reg:x6; val_offset:1416*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1416*FLEN/8, x7, x2, x4) + +inst_734: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x003 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c03; op2val:0x3c00; + valaddr_reg:x6; val_offset:1418*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1418*FLEN/8, x7, x2, x4) + +inst_735: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x4000; + valaddr_reg:x6; val_offset:1420*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1420*FLEN/8, x7, x2, x4) + +inst_736: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4000; op2val:0x3c00; + valaddr_reg:x6; val_offset:1422*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1422*FLEN/8, x7, x2, x4) + +inst_737: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x43ff; + valaddr_reg:x6; val_offset:1424*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1424*FLEN/8, x7, x2, x4) + +inst_738: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x43ff; op2val:0x3c00; + valaddr_reg:x6; val_offset:1426*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1426*FLEN/8, x7, x2, x4) + +inst_739: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x4200; + valaddr_reg:x6; val_offset:1428*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1428*FLEN/8, x7, x2, x4) + +inst_740: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4200; op2val:0x3c00; + valaddr_reg:x6; val_offset:1430*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1430*FLEN/8, x7, x2, x4) + +inst_741: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x41ff; + valaddr_reg:x6; val_offset:1432*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1432*FLEN/8, x7, x2, x4) + +inst_742: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x41ff; op2val:0x3c00; + valaddr_reg:x6; val_offset:1434*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1434*FLEN/8, x7, x2, x4) + +inst_743: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x4300; + valaddr_reg:x6; val_offset:1436*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1436*FLEN/8, x7, x2, x4) + +inst_744: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x300 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4300; op2val:0x3c00; + valaddr_reg:x6; val_offset:1438*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1438*FLEN/8, x7, x2, x4) + +inst_745: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x40ff; + valaddr_reg:x6; val_offset:1440*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1440*FLEN/8, x7, x2, x4) + +inst_746: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x40ff; op2val:0x3c00; + valaddr_reg:x6; val_offset:1442*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1442*FLEN/8, x7, x2, x4) + +inst_747: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x4380; + valaddr_reg:x6; val_offset:1444*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1444*FLEN/8, x7, x2, x4) + +inst_748: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x380 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4380; op2val:0x3c00; + valaddr_reg:x6; val_offset:1446*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1446*FLEN/8, x7, x2, x4) + +inst_749: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x407f; + valaddr_reg:x6; val_offset:1448*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1448*FLEN/8, x7, x2, x4) + +inst_750: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x07f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x407f; op2val:0x3c00; + valaddr_reg:x6; val_offset:1450*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1450*FLEN/8, x7, x2, x4) + +inst_751: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x43c0; + valaddr_reg:x6; val_offset:1452*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1452*FLEN/8, x7, x2, x4) + +inst_752: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x43c0; op2val:0x3c00; + valaddr_reg:x6; val_offset:1454*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1454*FLEN/8, x7, x2, x4) + +inst_753: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x403f; + valaddr_reg:x6; val_offset:1456*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1456*FLEN/8, x7, x2, x4) + +inst_754: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x403f; op2val:0x3c00; + valaddr_reg:x6; val_offset:1458*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1458*FLEN/8, x7, x2, x4) + +inst_755: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x43e0; + valaddr_reg:x6; val_offset:1460*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1460*FLEN/8, x7, x2, x4) + +inst_756: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x43e0; op2val:0x3c00; + valaddr_reg:x6; val_offset:1462*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1462*FLEN/8, x7, x2, x4) + +inst_757: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x401f; + valaddr_reg:x6; val_offset:1464*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1464*FLEN/8, x7, x2, x4) + +inst_758: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x01f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x401f; op2val:0x3c00; + valaddr_reg:x6; val_offset:1466*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1466*FLEN/8, x7, x2, x4) + +inst_759: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x43f0; + valaddr_reg:x6; val_offset:1468*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1468*FLEN/8, x7, x2, x4) + +inst_760: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x43f0; op2val:0x3c00; + valaddr_reg:x6; val_offset:1470*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1470*FLEN/8, x7, x2, x4) + +inst_761: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x400f; + valaddr_reg:x6; val_offset:1472*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1472*FLEN/8, x7, x2, x4) + +inst_762: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x00f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400f; op2val:0x3c00; + valaddr_reg:x6; val_offset:1474*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1474*FLEN/8, x7, x2, x4) + +inst_763: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x43f8; + valaddr_reg:x6; val_offset:1476*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1476*FLEN/8, x7, x2, x4) + +inst_764: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x43f8; op2val:0x3c00; + valaddr_reg:x6; val_offset:1478*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1478*FLEN/8, x7, x2, x4) + +inst_765: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x4007; + valaddr_reg:x6; val_offset:1480*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1480*FLEN/8, x7, x2, x4) + +inst_766: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4007; op2val:0x3c00; + valaddr_reg:x6; val_offset:1482*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1482*FLEN/8, x7, x2, x4) + +inst_767: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x43fc; + valaddr_reg:x6; val_offset:1484*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1484*FLEN/8, x7, x2, x4) + +inst_768: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x43fc; op2val:0x3c00; + valaddr_reg:x6; val_offset:1486*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1486*FLEN/8, x7, x2, x4) + +inst_769: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x4003; + valaddr_reg:x6; val_offset:1488*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1488*FLEN/8, x7, x2, x4) + +inst_770: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x003 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4003; op2val:0x3c00; + valaddr_reg:x6; val_offset:1490*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1490*FLEN/8, x7, x2, x4) + +inst_771: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x43fe; + valaddr_reg:x6; val_offset:1492*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1492*FLEN/8, x7, x2, x4) + +inst_772: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x43fe; op2val:0x3c00; + valaddr_reg:x6; val_offset:1494*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1494*FLEN/8, x7, x2, x4) + +inst_773: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x4001; + valaddr_reg:x6; val_offset:1496*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1496*FLEN/8, x7, x2, x4) + +inst_774: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4001; op2val:0x3c00; + valaddr_reg:x6; val_offset:1498*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1498*FLEN/8, x7, x2, x4) + +inst_775: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x4400; + valaddr_reg:x6; val_offset:1500*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1500*FLEN/8, x7, x2, x4) + +inst_776: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4400; op2val:0x3c00; + valaddr_reg:x6; val_offset:1502*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1502*FLEN/8, x7, x2, x4) + +inst_777: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x47ff; + valaddr_reg:x6; val_offset:1504*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1504*FLEN/8, x7, x2, x4) + +inst_778: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x47ff; op2val:0x3c00; + valaddr_reg:x6; val_offset:1506*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1506*FLEN/8, x7, x2, x4) + +inst_779: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x4600; + valaddr_reg:x6; val_offset:1508*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1508*FLEN/8, x7, x2, x4) + +inst_780: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4600; op2val:0x3c00; + valaddr_reg:x6; val_offset:1510*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1510*FLEN/8, x7, x2, x4) + +inst_781: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x45ff; + valaddr_reg:x6; val_offset:1512*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1512*FLEN/8, x7, x2, x4) + +inst_782: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x45ff; op2val:0x3c00; + valaddr_reg:x6; val_offset:1514*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1514*FLEN/8, x7, x2, x4) + +inst_783: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x4700; + valaddr_reg:x6; val_offset:1516*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1516*FLEN/8, x7, x2, x4) + +inst_784: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x300 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4700; op2val:0x3c00; + valaddr_reg:x6; val_offset:1518*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1518*FLEN/8, x7, x2, x4) + +inst_785: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x44ff; + valaddr_reg:x6; val_offset:1520*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1520*FLEN/8, x7, x2, x4) + +inst_786: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x44ff; op2val:0x3c00; + valaddr_reg:x6; val_offset:1522*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1522*FLEN/8, x7, x2, x4) + +inst_787: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x4780; + valaddr_reg:x6; val_offset:1524*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1524*FLEN/8, x7, x2, x4) + +inst_788: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x380 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4780; op2val:0x3c00; + valaddr_reg:x6; val_offset:1526*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1526*FLEN/8, x7, x2, x4) + +inst_789: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x447f; + valaddr_reg:x6; val_offset:1528*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1528*FLEN/8, x7, x2, x4) + +inst_790: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x07f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x447f; op2val:0x3c00; + valaddr_reg:x6; val_offset:1530*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1530*FLEN/8, x7, x2, x4) + +inst_791: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x47c0; + valaddr_reg:x6; val_offset:1532*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1532*FLEN/8, x7, x2, x4) + +inst_792: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x47c0; op2val:0x3c00; + valaddr_reg:x6; val_offset:1534*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1534*FLEN/8, x7, x2, x4) + +inst_793: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x443f; + valaddr_reg:x6; val_offset:1536*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1536*FLEN/8, x7, x2, x4) + +inst_794: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x443f; op2val:0x3c00; + valaddr_reg:x6; val_offset:1538*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1538*FLEN/8, x7, x2, x4) + +inst_795: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x47e0; + valaddr_reg:x6; val_offset:1540*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1540*FLEN/8, x7, x2, x4) + +inst_796: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x47e0; op2val:0x3c00; + valaddr_reg:x6; val_offset:1542*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1542*FLEN/8, x7, x2, x4) +RVTEST_SIGBASE(x2,signature_x2_8) + +inst_797: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x441f; + valaddr_reg:x6; val_offset:1544*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1544*FLEN/8, x7, x2, x4) + +inst_798: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x01f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x441f; op2val:0x3c00; + valaddr_reg:x6; val_offset:1546*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1546*FLEN/8, x7, x2, x4) + +inst_799: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x47f0; + valaddr_reg:x6; val_offset:1548*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1548*FLEN/8, x7, x2, x4) + +inst_800: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x47f0; op2val:0x3c00; + valaddr_reg:x6; val_offset:1550*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1550*FLEN/8, x7, x2, x4) + +inst_801: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x440f; + valaddr_reg:x6; val_offset:1552*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1552*FLEN/8, x7, x2, x4) + +inst_802: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x00f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x440f; op2val:0x3c00; + valaddr_reg:x6; val_offset:1554*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1554*FLEN/8, x7, x2, x4) + +inst_803: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x47f8; + valaddr_reg:x6; val_offset:1556*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1556*FLEN/8, x7, x2, x4) + +inst_804: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x47f8; op2val:0x3c00; + valaddr_reg:x6; val_offset:1558*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1558*FLEN/8, x7, x2, x4) + +inst_805: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x4407; + valaddr_reg:x6; val_offset:1560*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1560*FLEN/8, x7, x2, x4) + +inst_806: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4407; op2val:0x3c00; + valaddr_reg:x6; val_offset:1562*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1562*FLEN/8, x7, x2, x4) + +inst_807: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x47fc; + valaddr_reg:x6; val_offset:1564*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1564*FLEN/8, x7, x2, x4) + +inst_808: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x47fc; op2val:0x3c00; + valaddr_reg:x6; val_offset:1566*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1566*FLEN/8, x7, x2, x4) + +inst_809: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x4403; + valaddr_reg:x6; val_offset:1568*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1568*FLEN/8, x7, x2, x4) + +inst_810: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x003 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4403; op2val:0x3c00; + valaddr_reg:x6; val_offset:1570*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1570*FLEN/8, x7, x2, x4) + +inst_811: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x47fe; + valaddr_reg:x6; val_offset:1572*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1572*FLEN/8, x7, x2, x4) + +inst_812: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x47fe; op2val:0x3c00; + valaddr_reg:x6; val_offset:1574*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1574*FLEN/8, x7, x2, x4) + +inst_813: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x4401; + valaddr_reg:x6; val_offset:1576*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1576*FLEN/8, x7, x2, x4) + +inst_814: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4401; op2val:0x3c00; + valaddr_reg:x6; val_offset:1578*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1578*FLEN/8, x7, x2, x4) + +inst_815: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x4800; + valaddr_reg:x6; val_offset:1580*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1580*FLEN/8, x7, x2, x4) + +inst_816: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4800; op2val:0x3c00; + valaddr_reg:x6; val_offset:1582*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1582*FLEN/8, x7, x2, x4) + +inst_817: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x4bff; + valaddr_reg:x6; val_offset:1584*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1584*FLEN/8, x7, x2, x4) + +inst_818: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4bff; op2val:0x3c00; + valaddr_reg:x6; val_offset:1586*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1586*FLEN/8, x7, x2, x4) + +inst_819: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x4a00; + valaddr_reg:x6; val_offset:1588*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1588*FLEN/8, x7, x2, x4) + +inst_820: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4a00; op2val:0x3c00; + valaddr_reg:x6; val_offset:1590*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1590*FLEN/8, x7, x2, x4) + +inst_821: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x49ff; + valaddr_reg:x6; val_offset:1592*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1592*FLEN/8, x7, x2, x4) + +inst_822: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x49ff; op2val:0x3c00; + valaddr_reg:x6; val_offset:1594*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1594*FLEN/8, x7, x2, x4) + +inst_823: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x4b00; + valaddr_reg:x6; val_offset:1596*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1596*FLEN/8, x7, x2, x4) + +inst_824: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x300 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4b00; op2val:0x3c00; + valaddr_reg:x6; val_offset:1598*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1598*FLEN/8, x7, x2, x4) + +inst_825: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x48ff; + valaddr_reg:x6; val_offset:1600*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1600*FLEN/8, x7, x2, x4) + +inst_826: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x48ff; op2val:0x3c00; + valaddr_reg:x6; val_offset:1602*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1602*FLEN/8, x7, x2, x4) + +inst_827: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x4b80; + valaddr_reg:x6; val_offset:1604*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1604*FLEN/8, x7, x2, x4) + +inst_828: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x380 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4b80; op2val:0x3c00; + valaddr_reg:x6; val_offset:1606*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1606*FLEN/8, x7, x2, x4) + +inst_829: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x487f; + valaddr_reg:x6; val_offset:1608*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1608*FLEN/8, x7, x2, x4) + +inst_830: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x07f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x487f; op2val:0x3c00; + valaddr_reg:x6; val_offset:1610*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1610*FLEN/8, x7, x2, x4) + +inst_831: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x4bc0; + valaddr_reg:x6; val_offset:1612*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1612*FLEN/8, x7, x2, x4) + +inst_832: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4bc0; op2val:0x3c00; + valaddr_reg:x6; val_offset:1614*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1614*FLEN/8, x7, x2, x4) + +inst_833: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x483f; + valaddr_reg:x6; val_offset:1616*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1616*FLEN/8, x7, x2, x4) + +inst_834: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x483f; op2val:0x3c00; + valaddr_reg:x6; val_offset:1618*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1618*FLEN/8, x7, x2, x4) + +inst_835: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x4be0; + valaddr_reg:x6; val_offset:1620*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1620*FLEN/8, x7, x2, x4) + +inst_836: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4be0; op2val:0x3c00; + valaddr_reg:x6; val_offset:1622*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1622*FLEN/8, x7, x2, x4) + +inst_837: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x481f; + valaddr_reg:x6; val_offset:1624*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1624*FLEN/8, x7, x2, x4) + +inst_838: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x01f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x481f; op2val:0x3c00; + valaddr_reg:x6; val_offset:1626*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1626*FLEN/8, x7, x2, x4) + +inst_839: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x4bf0; + valaddr_reg:x6; val_offset:1628*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1628*FLEN/8, x7, x2, x4) + +inst_840: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4bf0; op2val:0x3c00; + valaddr_reg:x6; val_offset:1630*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1630*FLEN/8, x7, x2, x4) + +inst_841: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x480f; + valaddr_reg:x6; val_offset:1632*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1632*FLEN/8, x7, x2, x4) + +inst_842: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x00f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x480f; op2val:0x3c00; + valaddr_reg:x6; val_offset:1634*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1634*FLEN/8, x7, x2, x4) + +inst_843: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x4bf8; + valaddr_reg:x6; val_offset:1636*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1636*FLEN/8, x7, x2, x4) + +inst_844: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4bf8; op2val:0x3c00; + valaddr_reg:x6; val_offset:1638*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1638*FLEN/8, x7, x2, x4) + +inst_845: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x4807; + valaddr_reg:x6; val_offset:1640*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1640*FLEN/8, x7, x2, x4) + +inst_846: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4807; op2val:0x3c00; + valaddr_reg:x6; val_offset:1642*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1642*FLEN/8, x7, x2, x4) + +inst_847: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x4bfc; + valaddr_reg:x6; val_offset:1644*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1644*FLEN/8, x7, x2, x4) + +inst_848: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4bfc; op2val:0x3c00; + valaddr_reg:x6; val_offset:1646*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1646*FLEN/8, x7, x2, x4) + +inst_849: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x4803; + valaddr_reg:x6; val_offset:1648*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1648*FLEN/8, x7, x2, x4) + +inst_850: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x003 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4803; op2val:0x3c00; + valaddr_reg:x6; val_offset:1650*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1650*FLEN/8, x7, x2, x4) + +inst_851: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x4bfe; + valaddr_reg:x6; val_offset:1652*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1652*FLEN/8, x7, x2, x4) + +inst_852: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4bfe; op2val:0x3c00; + valaddr_reg:x6; val_offset:1654*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1654*FLEN/8, x7, x2, x4) + +inst_853: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x4801; + valaddr_reg:x6; val_offset:1656*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1656*FLEN/8, x7, x2, x4) + +inst_854: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4801; op2val:0x3c00; + valaddr_reg:x6; val_offset:1658*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1658*FLEN/8, x7, x2, x4) + +inst_855: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x9000; + valaddr_reg:x6; val_offset:1660*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1660*FLEN/8, x7, x2, x4) + +inst_856: +// fs1 == 1 and fe1 == 0x04 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x9000; op2val:0xbc00; + valaddr_reg:x6; val_offset:1662*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1662*FLEN/8, x7, x2, x4) + +inst_857: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x93ff; + valaddr_reg:x6; val_offset:1664*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1664*FLEN/8, x7, x2, x4) + +inst_858: +// fs1 == 1 and fe1 == 0x04 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x93ff; op2val:0xbc00; + valaddr_reg:x6; val_offset:1666*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1666*FLEN/8, x7, x2, x4) + +inst_859: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x9200; + valaddr_reg:x6; val_offset:1668*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1668*FLEN/8, x7, x2, x4) + +inst_860: +// fs1 == 1 and fe1 == 0x04 and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x9200; op2val:0xbc00; + valaddr_reg:x6; val_offset:1670*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1670*FLEN/8, x7, x2, x4) + +inst_861: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x91ff; + valaddr_reg:x6; val_offset:1672*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1672*FLEN/8, x7, x2, x4) + +inst_862: +// fs1 == 1 and fe1 == 0x04 and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x91ff; op2val:0xbc00; + valaddr_reg:x6; val_offset:1674*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1674*FLEN/8, x7, x2, x4) + +inst_863: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x9300; + valaddr_reg:x6; val_offset:1676*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1676*FLEN/8, x7, x2, x4) + +inst_864: +// fs1 == 1 and fe1 == 0x04 and fm1 == 0x300 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x9300; op2val:0xbc00; + valaddr_reg:x6; val_offset:1678*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1678*FLEN/8, x7, x2, x4) + +inst_865: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x90ff; + valaddr_reg:x6; val_offset:1680*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1680*FLEN/8, x7, x2, x4) + +inst_866: +// fs1 == 1 and fe1 == 0x04 and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x90ff; op2val:0xbc00; + valaddr_reg:x6; val_offset:1682*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1682*FLEN/8, x7, x2, x4) + +inst_867: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x9380; + valaddr_reg:x6; val_offset:1684*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1684*FLEN/8, x7, x2, x4) + +inst_868: +// fs1 == 1 and fe1 == 0x04 and fm1 == 0x380 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x9380; op2val:0xbc00; + valaddr_reg:x6; val_offset:1686*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1686*FLEN/8, x7, x2, x4) + +inst_869: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x907f; + valaddr_reg:x6; val_offset:1688*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1688*FLEN/8, x7, x2, x4) + +inst_870: +// fs1 == 1 and fe1 == 0x04 and fm1 == 0x07f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x907f; op2val:0xbc00; + valaddr_reg:x6; val_offset:1690*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1690*FLEN/8, x7, x2, x4) + +inst_871: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x93c0; + valaddr_reg:x6; val_offset:1692*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1692*FLEN/8, x7, x2, x4) + +inst_872: +// fs1 == 1 and fe1 == 0x04 and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x93c0; op2val:0xbc00; + valaddr_reg:x6; val_offset:1694*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1694*FLEN/8, x7, x2, x4) + +inst_873: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x903f; + valaddr_reg:x6; val_offset:1696*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1696*FLEN/8, x7, x2, x4) + +inst_874: +// fs1 == 1 and fe1 == 0x04 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x903f; op2val:0xbc00; + valaddr_reg:x6; val_offset:1698*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1698*FLEN/8, x7, x2, x4) + +inst_875: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x93e0; + valaddr_reg:x6; val_offset:1700*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1700*FLEN/8, x7, x2, x4) + +inst_876: +// fs1 == 1 and fe1 == 0x04 and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x93e0; op2val:0xbc00; + valaddr_reg:x6; val_offset:1702*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1702*FLEN/8, x7, x2, x4) + +inst_877: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x901f; + valaddr_reg:x6; val_offset:1704*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1704*FLEN/8, x7, x2, x4) + +inst_878: +// fs1 == 1 and fe1 == 0x04 and fm1 == 0x01f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x901f; op2val:0xbc00; + valaddr_reg:x6; val_offset:1706*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1706*FLEN/8, x7, x2, x4) + +inst_879: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x93f0; + valaddr_reg:x6; val_offset:1708*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1708*FLEN/8, x7, x2, x4) + +inst_880: +// fs1 == 1 and fe1 == 0x04 and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x93f0; op2val:0xbc00; + valaddr_reg:x6; val_offset:1710*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1710*FLEN/8, x7, x2, x4) + +inst_881: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x900f; + valaddr_reg:x6; val_offset:1712*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1712*FLEN/8, x7, x2, x4) + +inst_882: +// fs1 == 1 and fe1 == 0x04 and fm1 == 0x00f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x900f; op2val:0xbc00; + valaddr_reg:x6; val_offset:1714*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1714*FLEN/8, x7, x2, x4) + +inst_883: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x93f8; + valaddr_reg:x6; val_offset:1716*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1716*FLEN/8, x7, x2, x4) + +inst_884: +// fs1 == 1 and fe1 == 0x04 and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x93f8; op2val:0xbc00; + valaddr_reg:x6; val_offset:1718*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1718*FLEN/8, x7, x2, x4) + +inst_885: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x9007; + valaddr_reg:x6; val_offset:1720*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1720*FLEN/8, x7, x2, x4) + +inst_886: +// fs1 == 1 and fe1 == 0x04 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x9007; op2val:0xbc00; + valaddr_reg:x6; val_offset:1722*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1722*FLEN/8, x7, x2, x4) + +inst_887: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x93fc; + valaddr_reg:x6; val_offset:1724*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1724*FLEN/8, x7, x2, x4) + +inst_888: +// fs1 == 1 and fe1 == 0x04 and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x93fc; op2val:0xbc00; + valaddr_reg:x6; val_offset:1726*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1726*FLEN/8, x7, x2, x4) + +inst_889: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x9003; + valaddr_reg:x6; val_offset:1728*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1728*FLEN/8, x7, x2, x4) + +inst_890: +// fs1 == 1 and fe1 == 0x04 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x9003; op2val:0xbc00; + valaddr_reg:x6; val_offset:1730*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1730*FLEN/8, x7, x2, x4) + +inst_891: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x93fe; + valaddr_reg:x6; val_offset:1732*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1732*FLEN/8, x7, x2, x4) + +inst_892: +// fs1 == 1 and fe1 == 0x04 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x93fe; op2val:0xbc00; + valaddr_reg:x6; val_offset:1734*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1734*FLEN/8, x7, x2, x4) + +inst_893: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x9001; + valaddr_reg:x6; val_offset:1736*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1736*FLEN/8, x7, x2, x4) + +inst_894: +// fs1 == 1 and fe1 == 0x04 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x9001; op2val:0xbc00; + valaddr_reg:x6; val_offset:1738*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1738*FLEN/8, x7, x2, x4) + +inst_895: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbffe; + valaddr_reg:x6; val_offset:1740*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1740*FLEN/8, x7, x2, x4) + +inst_896: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbffe; op2val:0xbc00; + valaddr_reg:x6; val_offset:1742*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1742*FLEN/8, x7, x2, x4) + +inst_897: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbc01; + valaddr_reg:x6; val_offset:1744*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1744*FLEN/8, x7, x2, x4) + +inst_898: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc01; op2val:0xbc00; + valaddr_reg:x6; val_offset:1746*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1746*FLEN/8, x7, x2, x4) + +inst_899: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1b6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbdb6; + valaddr_reg:x6; val_offset:1748*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1748*FLEN/8, x7, x2, x4) + +inst_900: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x1b6 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbdb6; op2val:0xbc00; + valaddr_reg:x6; val_offset:1750*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1750*FLEN/8, x7, x2, x4) + +inst_901: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x36d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbf6d; + valaddr_reg:x6; val_offset:1752*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1752*FLEN/8, x7, x2, x4) + +inst_902: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x36d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbf6d; op2val:0xbc00; + valaddr_reg:x6; val_offset:1754*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1754*FLEN/8, x7, x2, x4) + +inst_903: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0cc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbccc; + valaddr_reg:x6; val_offset:1756*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1756*FLEN/8, x7, x2, x4) + +inst_904: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x0cc and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbccc; op2val:0xbc00; + valaddr_reg:x6; val_offset:1758*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1758*FLEN/8, x7, x2, x4) + +inst_905: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x333 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbf33; + valaddr_reg:x6; val_offset:1760*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1760*FLEN/8, x7, x2, x4) + +inst_906: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x333 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbf33; op2val:0xbc00; + valaddr_reg:x6; val_offset:1762*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1762*FLEN/8, x7, x2, x4) + +inst_907: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1dd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbddd; + valaddr_reg:x6; val_offset:1764*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1764*FLEN/8, x7, x2, x4) + +inst_908: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x1dd and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbddd; op2val:0xbc00; + valaddr_reg:x6; val_offset:1766*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1766*FLEN/8, x7, x2, x4) + +inst_909: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x222 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbe22; + valaddr_reg:x6; val_offset:1768*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1768*FLEN/8, x7, x2, x4) + +inst_910: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x222 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbe22; op2val:0xbc00; + valaddr_reg:x6; val_offset:1770*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1770*FLEN/8, x7, x2, x4) + +inst_911: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x124 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbd24; + valaddr_reg:x6; val_offset:1772*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1772*FLEN/8, x7, x2, x4) + +inst_912: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x124 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbd24; op2val:0xbc00; + valaddr_reg:x6; val_offset:1774*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1774*FLEN/8, x7, x2, x4) + +inst_913: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2db and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbedb; + valaddr_reg:x6; val_offset:1776*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1776*FLEN/8, x7, x2, x4) + +inst_914: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x2db and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbedb; op2val:0xbc00; + valaddr_reg:x6; val_offset:1778*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1778*FLEN/8, x7, x2, x4) + +inst_915: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x199 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbd99; + valaddr_reg:x6; val_offset:1780*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1780*FLEN/8, x7, x2, x4) + +inst_916: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x199 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbd99; op2val:0xbc00; + valaddr_reg:x6; val_offset:1782*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1782*FLEN/8, x7, x2, x4) + +inst_917: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x266 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbe66; + valaddr_reg:x6; val_offset:1784*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1784*FLEN/8, x7, x2, x4) + +inst_918: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x266 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbe66; op2val:0xbc00; + valaddr_reg:x6; val_offset:1786*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1786*FLEN/8, x7, x2, x4) + +inst_919: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x5400; + valaddr_reg:x6; val_offset:1788*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1788*FLEN/8, x7, x2, x4) + +inst_920: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5400; op2val:0xbc00; + valaddr_reg:x6; val_offset:1790*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1790*FLEN/8, x7, x2, x4) + +inst_921: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x57ff; + valaddr_reg:x6; val_offset:1792*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1792*FLEN/8, x7, x2, x4) + +inst_922: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x57ff; op2val:0xbc00; + valaddr_reg:x6; val_offset:1794*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1794*FLEN/8, x7, x2, x4) + +inst_923: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x5600; + valaddr_reg:x6; val_offset:1796*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1796*FLEN/8, x7, x2, x4) + +inst_924: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5600; op2val:0xbc00; + valaddr_reg:x6; val_offset:1798*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1798*FLEN/8, x7, x2, x4) +RVTEST_SIGBASE(x2,signature_x2_9) + +inst_925: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x55ff; + valaddr_reg:x6; val_offset:1800*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1800*FLEN/8, x7, x2, x4) + +inst_926: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x55ff; op2val:0xbc00; + valaddr_reg:x6; val_offset:1802*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1802*FLEN/8, x7, x2, x4) + +inst_927: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x5700; + valaddr_reg:x6; val_offset:1804*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1804*FLEN/8, x7, x2, x4) + +inst_928: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x300 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5700; op2val:0xbc00; + valaddr_reg:x6; val_offset:1806*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1806*FLEN/8, x7, x2, x4) + +inst_929: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x54ff; + valaddr_reg:x6; val_offset:1808*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1808*FLEN/8, x7, x2, x4) + +inst_930: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x54ff; op2val:0xbc00; + valaddr_reg:x6; val_offset:1810*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1810*FLEN/8, x7, x2, x4) + +inst_931: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x5780; + valaddr_reg:x6; val_offset:1812*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1812*FLEN/8, x7, x2, x4) + +inst_932: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x380 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5780; op2val:0xbc00; + valaddr_reg:x6; val_offset:1814*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1814*FLEN/8, x7, x2, x4) + +inst_933: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x547f; + valaddr_reg:x6; val_offset:1816*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1816*FLEN/8, x7, x2, x4) + +inst_934: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x07f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x547f; op2val:0xbc00; + valaddr_reg:x6; val_offset:1818*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1818*FLEN/8, x7, x2, x4) + +inst_935: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x57c0; + valaddr_reg:x6; val_offset:1820*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1820*FLEN/8, x7, x2, x4) + +inst_936: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x57c0; op2val:0xbc00; + valaddr_reg:x6; val_offset:1822*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1822*FLEN/8, x7, x2, x4) + +inst_937: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x543f; + valaddr_reg:x6; val_offset:1824*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1824*FLEN/8, x7, x2, x4) + +inst_938: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x543f; op2val:0xbc00; + valaddr_reg:x6; val_offset:1826*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1826*FLEN/8, x7, x2, x4) + +inst_939: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x57e0; + valaddr_reg:x6; val_offset:1828*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1828*FLEN/8, x7, x2, x4) + +inst_940: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x57e0; op2val:0xbc00; + valaddr_reg:x6; val_offset:1830*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1830*FLEN/8, x7, x2, x4) + +inst_941: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x541f; + valaddr_reg:x6; val_offset:1832*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1832*FLEN/8, x7, x2, x4) + +inst_942: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x01f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x541f; op2val:0xbc00; + valaddr_reg:x6; val_offset:1834*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1834*FLEN/8, x7, x2, x4) + +inst_943: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x57f0; + valaddr_reg:x6; val_offset:1836*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1836*FLEN/8, x7, x2, x4) + +inst_944: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x57f0; op2val:0xbc00; + valaddr_reg:x6; val_offset:1838*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1838*FLEN/8, x7, x2, x4) + +inst_945: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x540f; + valaddr_reg:x6; val_offset:1840*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1840*FLEN/8, x7, x2, x4) + +inst_946: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x00f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x540f; op2val:0xbc00; + valaddr_reg:x6; val_offset:1842*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1842*FLEN/8, x7, x2, x4) + +inst_947: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x57f8; + valaddr_reg:x6; val_offset:1844*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1844*FLEN/8, x7, x2, x4) + +inst_948: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x57f8; op2val:0xbc00; + valaddr_reg:x6; val_offset:1846*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1846*FLEN/8, x7, x2, x4) + +inst_949: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x5407; + valaddr_reg:x6; val_offset:1848*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1848*FLEN/8, x7, x2, x4) + +inst_950: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5407; op2val:0xbc00; + valaddr_reg:x6; val_offset:1850*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1850*FLEN/8, x7, x2, x4) + +inst_951: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x57fc; + valaddr_reg:x6; val_offset:1852*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1852*FLEN/8, x7, x2, x4) + +inst_952: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x57fc; op2val:0xbc00; + valaddr_reg:x6; val_offset:1854*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1854*FLEN/8, x7, x2, x4) + +inst_953: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x5403; + valaddr_reg:x6; val_offset:1856*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1856*FLEN/8, x7, x2, x4) + +inst_954: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5403; op2val:0xbc00; + valaddr_reg:x6; val_offset:1858*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1858*FLEN/8, x7, x2, x4) + +inst_955: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x57fe; + valaddr_reg:x6; val_offset:1860*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1860*FLEN/8, x7, x2, x4) + +inst_956: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x57fe; op2val:0xbc00; + valaddr_reg:x6; val_offset:1862*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1862*FLEN/8, x7, x2, x4) + +inst_957: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x5401; + valaddr_reg:x6; val_offset:1864*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1864*FLEN/8, x7, x2, x4) + +inst_958: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5401; op2val:0xbc00; + valaddr_reg:x6; val_offset:1866*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1866*FLEN/8, x7, x2, x4) + +inst_959: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xac00; + valaddr_reg:x6; val_offset:1868*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1868*FLEN/8, x7, x2, x4) + +inst_960: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xac00; op2val:0xbc00; + valaddr_reg:x6; val_offset:1870*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1870*FLEN/8, x7, x2, x4) + +inst_961: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xafff; + valaddr_reg:x6; val_offset:1872*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1872*FLEN/8, x7, x2, x4) + +inst_962: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xafff; op2val:0xbc00; + valaddr_reg:x6; val_offset:1874*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1874*FLEN/8, x7, x2, x4) + +inst_963: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xae00; + valaddr_reg:x6; val_offset:1876*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1876*FLEN/8, x7, x2, x4) + +inst_964: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xae00; op2val:0xbc00; + valaddr_reg:x6; val_offset:1878*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1878*FLEN/8, x7, x2, x4) + +inst_965: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xadff; + valaddr_reg:x6; val_offset:1880*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1880*FLEN/8, x7, x2, x4) + +inst_966: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xadff; op2val:0xbc00; + valaddr_reg:x6; val_offset:1882*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1882*FLEN/8, x7, x2, x4) + +inst_967: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xaf00; + valaddr_reg:x6; val_offset:1884*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1884*FLEN/8, x7, x2, x4) + +inst_968: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x300 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xaf00; op2val:0xbc00; + valaddr_reg:x6; val_offset:1886*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1886*FLEN/8, x7, x2, x4) + +inst_969: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xacff; + valaddr_reg:x6; val_offset:1888*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1888*FLEN/8, x7, x2, x4) + +inst_970: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xacff; op2val:0xbc00; + valaddr_reg:x6; val_offset:1890*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1890*FLEN/8, x7, x2, x4) + +inst_971: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xaf80; + valaddr_reg:x6; val_offset:1892*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1892*FLEN/8, x7, x2, x4) + +inst_972: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x380 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xaf80; op2val:0xbc00; + valaddr_reg:x6; val_offset:1894*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1894*FLEN/8, x7, x2, x4) + +inst_973: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xac7f; + valaddr_reg:x6; val_offset:1896*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1896*FLEN/8, x7, x2, x4) + +inst_974: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x07f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xac7f; op2val:0xbc00; + valaddr_reg:x6; val_offset:1898*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1898*FLEN/8, x7, x2, x4) + +inst_975: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xafc0; + valaddr_reg:x6; val_offset:1900*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1900*FLEN/8, x7, x2, x4) + +inst_976: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xafc0; op2val:0xbc00; + valaddr_reg:x6; val_offset:1902*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1902*FLEN/8, x7, x2, x4) + +inst_977: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xac3f; + valaddr_reg:x6; val_offset:1904*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1904*FLEN/8, x7, x2, x4) + +inst_978: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x03f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xac3f; op2val:0xbc00; + valaddr_reg:x6; val_offset:1906*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1906*FLEN/8, x7, x2, x4) + +inst_979: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xafe0; + valaddr_reg:x6; val_offset:1908*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1908*FLEN/8, x7, x2, x4) + +inst_980: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xafe0; op2val:0xbc00; + valaddr_reg:x6; val_offset:1910*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1910*FLEN/8, x7, x2, x4) + +inst_981: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xac1f; + valaddr_reg:x6; val_offset:1912*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1912*FLEN/8, x7, x2, x4) + +inst_982: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x01f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xac1f; op2val:0xbc00; + valaddr_reg:x6; val_offset:1914*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1914*FLEN/8, x7, x2, x4) + +inst_983: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xaff0; + valaddr_reg:x6; val_offset:1916*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1916*FLEN/8, x7, x2, x4) + +inst_984: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xaff0; op2val:0xbc00; + valaddr_reg:x6; val_offset:1918*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1918*FLEN/8, x7, x2, x4) + +inst_985: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xac0f; + valaddr_reg:x6; val_offset:1920*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1920*FLEN/8, x7, x2, x4) + +inst_986: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x00f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xac0f; op2val:0xbc00; + valaddr_reg:x6; val_offset:1922*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1922*FLEN/8, x7, x2, x4) + +inst_987: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xaff8; + valaddr_reg:x6; val_offset:1924*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1924*FLEN/8, x7, x2, x4) + +inst_988: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xaff8; op2val:0xbc00; + valaddr_reg:x6; val_offset:1926*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1926*FLEN/8, x7, x2, x4) + +inst_989: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xac07; + valaddr_reg:x6; val_offset:1928*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1928*FLEN/8, x7, x2, x4) + +inst_990: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x007 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xac07; op2val:0xbc00; + valaddr_reg:x6; val_offset:1930*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1930*FLEN/8, x7, x2, x4) + +inst_991: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xaffc; + valaddr_reg:x6; val_offset:1932*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1932*FLEN/8, x7, x2, x4) + +inst_992: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xaffc; op2val:0xbc00; + valaddr_reg:x6; val_offset:1934*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1934*FLEN/8, x7, x2, x4) + +inst_993: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xac03; + valaddr_reg:x6; val_offset:1936*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1936*FLEN/8, x7, x2, x4) + +inst_994: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x003 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xac03; op2val:0xbc00; + valaddr_reg:x6; val_offset:1938*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1938*FLEN/8, x7, x2, x4) + +inst_995: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xaffe; + valaddr_reg:x6; val_offset:1940*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1940*FLEN/8, x7, x2, x4) + +inst_996: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xaffe; op2val:0xbc00; + valaddr_reg:x6; val_offset:1942*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1942*FLEN/8, x7, x2, x4) + +inst_997: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xac01; + valaddr_reg:x6; val_offset:1944*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1944*FLEN/8, x7, x2, x4) + +inst_998: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xac01; op2val:0xbc00; + valaddr_reg:x6; val_offset:1946*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1946*FLEN/8, x7, x2, x4) + +inst_999: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb000; + valaddr_reg:x6; val_offset:1948*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1948*FLEN/8, x7, x2, x4) + +inst_1000: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xb000; op2val:0xbc00; + valaddr_reg:x6; val_offset:1950*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1950*FLEN/8, x7, x2, x4) + +inst_1001: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb3ff; + valaddr_reg:x6; val_offset:1952*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1952*FLEN/8, x7, x2, x4) + +inst_1002: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xb3ff; op2val:0xbc00; + valaddr_reg:x6; val_offset:1954*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1954*FLEN/8, x7, x2, x4) + +inst_1003: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb200; + valaddr_reg:x6; val_offset:1956*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1956*FLEN/8, x7, x2, x4) + +inst_1004: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xb200; op2val:0xbc00; + valaddr_reg:x6; val_offset:1958*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1958*FLEN/8, x7, x2, x4) + +inst_1005: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb1ff; + valaddr_reg:x6; val_offset:1960*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1960*FLEN/8, x7, x2, x4) + +inst_1006: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xb1ff; op2val:0xbc00; + valaddr_reg:x6; val_offset:1962*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1962*FLEN/8, x7, x2, x4) + +inst_1007: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb300; + valaddr_reg:x6; val_offset:1964*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1964*FLEN/8, x7, x2, x4) + +inst_1008: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x300 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xb300; op2val:0xbc00; + valaddr_reg:x6; val_offset:1966*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1966*FLEN/8, x7, x2, x4) + +inst_1009: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb0ff; + valaddr_reg:x6; val_offset:1968*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1968*FLEN/8, x7, x2, x4) + +inst_1010: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xb0ff; op2val:0xbc00; + valaddr_reg:x6; val_offset:1970*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1970*FLEN/8, x7, x2, x4) + +inst_1011: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb380; + valaddr_reg:x6; val_offset:1972*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1972*FLEN/8, x7, x2, x4) + +inst_1012: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x380 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xb380; op2val:0xbc00; + valaddr_reg:x6; val_offset:1974*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1974*FLEN/8, x7, x2, x4) + +inst_1013: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb07f; + valaddr_reg:x6; val_offset:1976*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1976*FLEN/8, x7, x2, x4) + +inst_1014: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x07f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xb07f; op2val:0xbc00; + valaddr_reg:x6; val_offset:1978*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1978*FLEN/8, x7, x2, x4) + +inst_1015: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb3c0; + valaddr_reg:x6; val_offset:1980*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1980*FLEN/8, x7, x2, x4) + +inst_1016: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xb3c0; op2val:0xbc00; + valaddr_reg:x6; val_offset:1982*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1982*FLEN/8, x7, x2, x4) + +inst_1017: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb03f; + valaddr_reg:x6; val_offset:1984*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1984*FLEN/8, x7, x2, x4) + +inst_1018: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x03f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xb03f; op2val:0xbc00; + valaddr_reg:x6; val_offset:1986*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1986*FLEN/8, x7, x2, x4) + +inst_1019: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb3e0; + valaddr_reg:x6; val_offset:1988*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1988*FLEN/8, x7, x2, x4) + +inst_1020: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xb3e0; op2val:0xbc00; + valaddr_reg:x6; val_offset:1990*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1990*FLEN/8, x7, x2, x4) + +inst_1021: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb01f; + valaddr_reg:x6; val_offset:1992*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1992*FLEN/8, x7, x2, x4) + +inst_1022: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x01f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xb01f; op2val:0xbc00; + valaddr_reg:x6; val_offset:1994*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1994*FLEN/8, x7, x2, x4) + +inst_1023: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb3f0; + valaddr_reg:x6; val_offset:1996*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1996*FLEN/8, x7, x2, x4) + +inst_1024: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xb3f0; op2val:0xbc00; + valaddr_reg:x6; val_offset:1998*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 1998*FLEN/8, x7, x2, x4) + +inst_1025: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb00f; + valaddr_reg:x6; val_offset:2000*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2000*FLEN/8, x7, x2, x4) + +inst_1026: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x00f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xb00f; op2val:0xbc00; + valaddr_reg:x6; val_offset:2002*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2002*FLEN/8, x7, x2, x4) + +inst_1027: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb3f8; + valaddr_reg:x6; val_offset:2004*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2004*FLEN/8, x7, x2, x4) + +inst_1028: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xb3f8; op2val:0xbc00; + valaddr_reg:x6; val_offset:2006*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2006*FLEN/8, x7, x2, x4) + +inst_1029: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb007; + valaddr_reg:x6; val_offset:2008*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2008*FLEN/8, x7, x2, x4) + +inst_1030: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x007 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xb007; op2val:0xbc00; + valaddr_reg:x6; val_offset:2010*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2010*FLEN/8, x7, x2, x4) + +inst_1031: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb3fc; + valaddr_reg:x6; val_offset:2012*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2012*FLEN/8, x7, x2, x4) + +inst_1032: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xb3fc; op2val:0xbc00; + valaddr_reg:x6; val_offset:2014*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2014*FLEN/8, x7, x2, x4) + +inst_1033: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb003; + valaddr_reg:x6; val_offset:2016*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2016*FLEN/8, x7, x2, x4) + +inst_1034: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x003 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xb003; op2val:0xbc00; + valaddr_reg:x6; val_offset:2018*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2018*FLEN/8, x7, x2, x4) + +inst_1035: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb3fe; + valaddr_reg:x6; val_offset:2020*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2020*FLEN/8, x7, x2, x4) + +inst_1036: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xb3fe; op2val:0xbc00; + valaddr_reg:x6; val_offset:2022*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2022*FLEN/8, x7, x2, x4) + +inst_1037: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb001; + valaddr_reg:x6; val_offset:2024*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2024*FLEN/8, x7, x2, x4) + +inst_1038: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xb001; op2val:0xbc00; + valaddr_reg:x6; val_offset:2026*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2026*FLEN/8, x7, x2, x4) + +inst_1039: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb400; + valaddr_reg:x6; val_offset:2028*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2028*FLEN/8, x7, x2, x4) + +inst_1040: +// fs1 == 1 and fe1 == 0x0d and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xb400; op2val:0xbc00; + valaddr_reg:x6; val_offset:2030*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2030*FLEN/8, x7, x2, x4) + +inst_1041: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb7ff; + valaddr_reg:x6; val_offset:2032*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2032*FLEN/8, x7, x2, x4) + +inst_1042: +// fs1 == 1 and fe1 == 0x0d and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xb7ff; op2val:0xbc00; + valaddr_reg:x6; val_offset:2034*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2034*FLEN/8, x7, x2, x4) + +inst_1043: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb600; + valaddr_reg:x6; val_offset:2036*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2036*FLEN/8, x7, x2, x4) + +inst_1044: +// fs1 == 1 and fe1 == 0x0d and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xb600; op2val:0xbc00; + valaddr_reg:x6; val_offset:2038*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2038*FLEN/8, x7, x2, x4) + +inst_1045: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb5ff; + valaddr_reg:x6; val_offset:2040*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2040*FLEN/8, x7, x2, x4) + +inst_1046: +// fs1 == 1 and fe1 == 0x0d and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xb5ff; op2val:0xbc00; + valaddr_reg:x6; val_offset:2042*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2042*FLEN/8, x7, x2, x4) + +inst_1047: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb700; + valaddr_reg:x6; val_offset:2044*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2044*FLEN/8, x7, x2, x4) + +inst_1048: +// fs1 == 1 and fe1 == 0x0d and fm1 == 0x300 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xb700; op2val:0xbc00; + valaddr_reg:x6; val_offset:2046*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2046*FLEN/8, x7, x2, x4) + +inst_1049: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb4ff; + valaddr_reg:x6; val_offset:2048*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2048*FLEN/8, x7, x2, x4) + +inst_1050: +// fs1 == 1 and fe1 == 0x0d and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xb4ff; op2val:0xbc00; + valaddr_reg:x6; val_offset:2050*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2050*FLEN/8, x7, x2, x4) + +inst_1051: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb780; + valaddr_reg:x6; val_offset:2052*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2052*FLEN/8, x7, x2, x4) + +inst_1052: +// fs1 == 1 and fe1 == 0x0d and fm1 == 0x380 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xb780; op2val:0xbc00; + valaddr_reg:x6; val_offset:2054*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2054*FLEN/8, x7, x2, x4) +RVTEST_SIGBASE(x2,signature_x2_10) + +inst_1053: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb47f; + valaddr_reg:x6; val_offset:2056*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2056*FLEN/8, x7, x2, x4) + +inst_1054: +// fs1 == 1 and fe1 == 0x0d and fm1 == 0x07f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xb47f; op2val:0xbc00; + valaddr_reg:x6; val_offset:2058*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2058*FLEN/8, x7, x2, x4) + +inst_1055: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb7c0; + valaddr_reg:x6; val_offset:2060*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2060*FLEN/8, x7, x2, x4) + +inst_1056: +// fs1 == 1 and fe1 == 0x0d and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xb7c0; op2val:0xbc00; + valaddr_reg:x6; val_offset:2062*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2062*FLEN/8, x7, x2, x4) + +inst_1057: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb43f; + valaddr_reg:x6; val_offset:2064*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2064*FLEN/8, x7, x2, x4) + +inst_1058: +// fs1 == 1 and fe1 == 0x0d and fm1 == 0x03f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xb43f; op2val:0xbc00; + valaddr_reg:x6; val_offset:2066*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2066*FLEN/8, x7, x2, x4) + +inst_1059: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb7e0; + valaddr_reg:x6; val_offset:2068*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2068*FLEN/8, x7, x2, x4) + +inst_1060: +// fs1 == 1 and fe1 == 0x0d and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xb7e0; op2val:0xbc00; + valaddr_reg:x6; val_offset:2070*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2070*FLEN/8, x7, x2, x4) + +inst_1061: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb41f; + valaddr_reg:x6; val_offset:2072*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2072*FLEN/8, x7, x2, x4) + +inst_1062: +// fs1 == 1 and fe1 == 0x0d and fm1 == 0x01f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xb41f; op2val:0xbc00; + valaddr_reg:x6; val_offset:2074*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2074*FLEN/8, x7, x2, x4) + +inst_1063: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb7f0; + valaddr_reg:x6; val_offset:2076*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2076*FLEN/8, x7, x2, x4) + +inst_1064: +// fs1 == 1 and fe1 == 0x0d and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xb7f0; op2val:0xbc00; + valaddr_reg:x6; val_offset:2078*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2078*FLEN/8, x7, x2, x4) + +inst_1065: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb40f; + valaddr_reg:x6; val_offset:2080*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2080*FLEN/8, x7, x2, x4) + +inst_1066: +// fs1 == 1 and fe1 == 0x0d and fm1 == 0x00f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xb40f; op2val:0xbc00; + valaddr_reg:x6; val_offset:2082*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2082*FLEN/8, x7, x2, x4) + +inst_1067: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb7f8; + valaddr_reg:x6; val_offset:2084*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2084*FLEN/8, x7, x2, x4) + +inst_1068: +// fs1 == 1 and fe1 == 0x0d and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xb7f8; op2val:0xbc00; + valaddr_reg:x6; val_offset:2086*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2086*FLEN/8, x7, x2, x4) + +inst_1069: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb407; + valaddr_reg:x6; val_offset:2088*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2088*FLEN/8, x7, x2, x4) + +inst_1070: +// fs1 == 1 and fe1 == 0x0d and fm1 == 0x007 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xb407; op2val:0xbc00; + valaddr_reg:x6; val_offset:2090*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2090*FLEN/8, x7, x2, x4) + +inst_1071: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb7fc; + valaddr_reg:x6; val_offset:2092*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2092*FLEN/8, x7, x2, x4) + +inst_1072: +// fs1 == 1 and fe1 == 0x0d and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xb7fc; op2val:0xbc00; + valaddr_reg:x6; val_offset:2094*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2094*FLEN/8, x7, x2, x4) + +inst_1073: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb403; + valaddr_reg:x6; val_offset:2096*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2096*FLEN/8, x7, x2, x4) + +inst_1074: +// fs1 == 1 and fe1 == 0x0d and fm1 == 0x003 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xb403; op2val:0xbc00; + valaddr_reg:x6; val_offset:2098*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2098*FLEN/8, x7, x2, x4) + +inst_1075: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb7fe; + valaddr_reg:x6; val_offset:2100*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2100*FLEN/8, x7, x2, x4) + +inst_1076: +// fs1 == 1 and fe1 == 0x0d and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xb7fe; op2val:0xbc00; + valaddr_reg:x6; val_offset:2102*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2102*FLEN/8, x7, x2, x4) + +inst_1077: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb401; + valaddr_reg:x6; val_offset:2104*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2104*FLEN/8, x7, x2, x4) + +inst_1078: +// fs1 == 1 and fe1 == 0x0d and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xb401; op2val:0xbc00; + valaddr_reg:x6; val_offset:2106*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2106*FLEN/8, x7, x2, x4) + +inst_1079: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb800; + valaddr_reg:x6; val_offset:2108*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2108*FLEN/8, x7, x2, x4) + +inst_1080: +// fs1 == 1 and fe1 == 0x0e and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xb800; op2val:0xbc00; + valaddr_reg:x6; val_offset:2110*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2110*FLEN/8, x7, x2, x4) + +inst_1081: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbbff; + valaddr_reg:x6; val_offset:2112*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2112*FLEN/8, x7, x2, x4) + +inst_1082: +// fs1 == 1 and fe1 == 0x0e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbbff; op2val:0xbc00; + valaddr_reg:x6; val_offset:2114*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2114*FLEN/8, x7, x2, x4) + +inst_1083: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xba00; + valaddr_reg:x6; val_offset:2116*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2116*FLEN/8, x7, x2, x4) + +inst_1084: +// fs1 == 1 and fe1 == 0x0e and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xba00; op2val:0xbc00; + valaddr_reg:x6; val_offset:2118*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2118*FLEN/8, x7, x2, x4) + +inst_1085: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb9ff; + valaddr_reg:x6; val_offset:2120*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2120*FLEN/8, x7, x2, x4) + +inst_1086: +// fs1 == 1 and fe1 == 0x0e and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xb9ff; op2val:0xbc00; + valaddr_reg:x6; val_offset:2122*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2122*FLEN/8, x7, x2, x4) + +inst_1087: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbb00; + valaddr_reg:x6; val_offset:2124*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2124*FLEN/8, x7, x2, x4) + +inst_1088: +// fs1 == 1 and fe1 == 0x0e and fm1 == 0x300 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbb00; op2val:0xbc00; + valaddr_reg:x6; val_offset:2126*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2126*FLEN/8, x7, x2, x4) + +inst_1089: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb8ff; + valaddr_reg:x6; val_offset:2128*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2128*FLEN/8, x7, x2, x4) + +inst_1090: +// fs1 == 1 and fe1 == 0x0e and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xb8ff; op2val:0xbc00; + valaddr_reg:x6; val_offset:2130*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2130*FLEN/8, x7, x2, x4) + +inst_1091: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbb80; + valaddr_reg:x6; val_offset:2132*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2132*FLEN/8, x7, x2, x4) + +inst_1092: +// fs1 == 1 and fe1 == 0x0e and fm1 == 0x380 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbb80; op2val:0xbc00; + valaddr_reg:x6; val_offset:2134*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2134*FLEN/8, x7, x2, x4) + +inst_1093: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb87f; + valaddr_reg:x6; val_offset:2136*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2136*FLEN/8, x7, x2, x4) + +inst_1094: +// fs1 == 1 and fe1 == 0x0e and fm1 == 0x07f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xb87f; op2val:0xbc00; + valaddr_reg:x6; val_offset:2138*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2138*FLEN/8, x7, x2, x4) + +inst_1095: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbbc0; + valaddr_reg:x6; val_offset:2140*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2140*FLEN/8, x7, x2, x4) + +inst_1096: +// fs1 == 1 and fe1 == 0x0e and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbbc0; op2val:0xbc00; + valaddr_reg:x6; val_offset:2142*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2142*FLEN/8, x7, x2, x4) + +inst_1097: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb83f; + valaddr_reg:x6; val_offset:2144*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2144*FLEN/8, x7, x2, x4) + +inst_1098: +// fs1 == 1 and fe1 == 0x0e and fm1 == 0x03f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xb83f; op2val:0xbc00; + valaddr_reg:x6; val_offset:2146*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2146*FLEN/8, x7, x2, x4) + +inst_1099: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbbe0; + valaddr_reg:x6; val_offset:2148*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2148*FLEN/8, x7, x2, x4) + +inst_1100: +// fs1 == 1 and fe1 == 0x0e and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbbe0; op2val:0xbc00; + valaddr_reg:x6; val_offset:2150*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2150*FLEN/8, x7, x2, x4) + +inst_1101: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb81f; + valaddr_reg:x6; val_offset:2152*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2152*FLEN/8, x7, x2, x4) + +inst_1102: +// fs1 == 1 and fe1 == 0x0e and fm1 == 0x01f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xb81f; op2val:0xbc00; + valaddr_reg:x6; val_offset:2154*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2154*FLEN/8, x7, x2, x4) + +inst_1103: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbbf0; + valaddr_reg:x6; val_offset:2156*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2156*FLEN/8, x7, x2, x4) + +inst_1104: +// fs1 == 1 and fe1 == 0x0e and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbbf0; op2val:0xbc00; + valaddr_reg:x6; val_offset:2158*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2158*FLEN/8, x7, x2, x4) + +inst_1105: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb80f; + valaddr_reg:x6; val_offset:2160*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2160*FLEN/8, x7, x2, x4) + +inst_1106: +// fs1 == 1 and fe1 == 0x0e and fm1 == 0x00f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xb80f; op2val:0xbc00; + valaddr_reg:x6; val_offset:2162*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2162*FLEN/8, x7, x2, x4) + +inst_1107: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbbf8; + valaddr_reg:x6; val_offset:2164*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2164*FLEN/8, x7, x2, x4) + +inst_1108: +// fs1 == 1 and fe1 == 0x0e and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbbf8; op2val:0xbc00; + valaddr_reg:x6; val_offset:2166*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2166*FLEN/8, x7, x2, x4) + +inst_1109: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb807; + valaddr_reg:x6; val_offset:2168*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2168*FLEN/8, x7, x2, x4) + +inst_1110: +// fs1 == 1 and fe1 == 0x0e and fm1 == 0x007 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xb807; op2val:0xbc00; + valaddr_reg:x6; val_offset:2170*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2170*FLEN/8, x7, x2, x4) + +inst_1111: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbbfc; + valaddr_reg:x6; val_offset:2172*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2172*FLEN/8, x7, x2, x4) + +inst_1112: +// fs1 == 1 and fe1 == 0x0e and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbbfc; op2val:0xbc00; + valaddr_reg:x6; val_offset:2174*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2174*FLEN/8, x7, x2, x4) + +inst_1113: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb803; + valaddr_reg:x6; val_offset:2176*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2176*FLEN/8, x7, x2, x4) + +inst_1114: +// fs1 == 1 and fe1 == 0x0e and fm1 == 0x003 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xb803; op2val:0xbc00; + valaddr_reg:x6; val_offset:2178*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2178*FLEN/8, x7, x2, x4) + +inst_1115: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbbfe; + valaddr_reg:x6; val_offset:2180*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2180*FLEN/8, x7, x2, x4) + +inst_1116: +// fs1 == 1 and fe1 == 0x0e and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbbfe; op2val:0xbc00; + valaddr_reg:x6; val_offset:2182*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2182*FLEN/8, x7, x2, x4) + +inst_1117: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb801; + valaddr_reg:x6; val_offset:2184*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2184*FLEN/8, x7, x2, x4) + +inst_1118: +// fs1 == 1 and fe1 == 0x0e and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xb801; op2val:0xbc00; + valaddr_reg:x6; val_offset:2186*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2186*FLEN/8, x7, x2, x4) + +inst_1119: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbc00; + valaddr_reg:x6; val_offset:2188*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2188*FLEN/8, x7, x2, x4) + +inst_1120: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbfff; + valaddr_reg:x6; val_offset:2190*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2190*FLEN/8, x7, x2, x4) + +inst_1121: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbfff; op2val:0xbc00; + valaddr_reg:x6; val_offset:2192*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2192*FLEN/8, x7, x2, x4) + +inst_1122: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbe00; + valaddr_reg:x6; val_offset:2194*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2194*FLEN/8, x7, x2, x4) + +inst_1123: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbe00; op2val:0xbc00; + valaddr_reg:x6; val_offset:2196*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2196*FLEN/8, x7, x2, x4) + +inst_1124: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbdff; + valaddr_reg:x6; val_offset:2198*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2198*FLEN/8, x7, x2, x4) + +inst_1125: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbdff; op2val:0xbc00; + valaddr_reg:x6; val_offset:2200*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2200*FLEN/8, x7, x2, x4) + +inst_1126: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbf00; + valaddr_reg:x6; val_offset:2202*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2202*FLEN/8, x7, x2, x4) + +inst_1127: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x300 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbf00; op2val:0xbc00; + valaddr_reg:x6; val_offset:2204*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2204*FLEN/8, x7, x2, x4) + +inst_1128: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbcff; + valaddr_reg:x6; val_offset:2206*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2206*FLEN/8, x7, x2, x4) + +inst_1129: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbcff; op2val:0xbc00; + valaddr_reg:x6; val_offset:2208*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2208*FLEN/8, x7, x2, x4) + +inst_1130: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbf80; + valaddr_reg:x6; val_offset:2210*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2210*FLEN/8, x7, x2, x4) + +inst_1131: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x380 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbf80; op2val:0xbc00; + valaddr_reg:x6; val_offset:2212*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2212*FLEN/8, x7, x2, x4) + +inst_1132: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbc7f; + valaddr_reg:x6; val_offset:2214*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2214*FLEN/8, x7, x2, x4) + +inst_1133: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x07f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc7f; op2val:0xbc00; + valaddr_reg:x6; val_offset:2216*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2216*FLEN/8, x7, x2, x4) + +inst_1134: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbfc0; + valaddr_reg:x6; val_offset:2218*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2218*FLEN/8, x7, x2, x4) + +inst_1135: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbfc0; op2val:0xbc00; + valaddr_reg:x6; val_offset:2220*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2220*FLEN/8, x7, x2, x4) + +inst_1136: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbc3f; + valaddr_reg:x6; val_offset:2222*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2222*FLEN/8, x7, x2, x4) + +inst_1137: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x03f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc3f; op2val:0xbc00; + valaddr_reg:x6; val_offset:2224*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2224*FLEN/8, x7, x2, x4) + +inst_1138: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbfe0; + valaddr_reg:x6; val_offset:2226*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2226*FLEN/8, x7, x2, x4) + +inst_1139: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbfe0; op2val:0xbc00; + valaddr_reg:x6; val_offset:2228*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2228*FLEN/8, x7, x2, x4) + +inst_1140: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbc1f; + valaddr_reg:x6; val_offset:2230*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2230*FLEN/8, x7, x2, x4) + +inst_1141: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x01f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc1f; op2val:0xbc00; + valaddr_reg:x6; val_offset:2232*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2232*FLEN/8, x7, x2, x4) + +inst_1142: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbff0; + valaddr_reg:x6; val_offset:2234*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2234*FLEN/8, x7, x2, x4) + +inst_1143: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbff0; op2val:0xbc00; + valaddr_reg:x6; val_offset:2236*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2236*FLEN/8, x7, x2, x4) + +inst_1144: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbc0f; + valaddr_reg:x6; val_offset:2238*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2238*FLEN/8, x7, x2, x4) + +inst_1145: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x00f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc0f; op2val:0xbc00; + valaddr_reg:x6; val_offset:2240*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2240*FLEN/8, x7, x2, x4) + +inst_1146: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbff8; + valaddr_reg:x6; val_offset:2242*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2242*FLEN/8, x7, x2, x4) + +inst_1147: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbff8; op2val:0xbc00; + valaddr_reg:x6; val_offset:2244*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2244*FLEN/8, x7, x2, x4) + +inst_1148: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbc07; + valaddr_reg:x6; val_offset:2246*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2246*FLEN/8, x7, x2, x4) + +inst_1149: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x007 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc07; op2val:0xbc00; + valaddr_reg:x6; val_offset:2248*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2248*FLEN/8, x7, x2, x4) + +inst_1150: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbffc; + valaddr_reg:x6; val_offset:2250*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2250*FLEN/8, x7, x2, x4) + +inst_1151: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbffc; op2val:0xbc00; + valaddr_reg:x6; val_offset:2252*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2252*FLEN/8, x7, x2, x4) + +inst_1152: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbc03; + valaddr_reg:x6; val_offset:2254*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2254*FLEN/8, x7, x2, x4) + +inst_1153: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x003 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc03; op2val:0xbc00; + valaddr_reg:x6; val_offset:2256*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2256*FLEN/8, x7, x2, x4) + +inst_1154: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc000; + valaddr_reg:x6; val_offset:2258*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2258*FLEN/8, x7, x2, x4) + +inst_1155: +// fs1 == 1 and fe1 == 0x10 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc000; op2val:0xbc00; + valaddr_reg:x6; val_offset:2260*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2260*FLEN/8, x7, x2, x4) + +inst_1156: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc3ff; + valaddr_reg:x6; val_offset:2262*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2262*FLEN/8, x7, x2, x4) + +inst_1157: +// fs1 == 1 and fe1 == 0x10 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc3ff; op2val:0xbc00; + valaddr_reg:x6; val_offset:2264*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2264*FLEN/8, x7, x2, x4) + +inst_1158: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc200; + valaddr_reg:x6; val_offset:2266*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2266*FLEN/8, x7, x2, x4) + +inst_1159: +// fs1 == 1 and fe1 == 0x10 and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc200; op2val:0xbc00; + valaddr_reg:x6; val_offset:2268*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2268*FLEN/8, x7, x2, x4) + +inst_1160: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc1ff; + valaddr_reg:x6; val_offset:2270*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2270*FLEN/8, x7, x2, x4) + +inst_1161: +// fs1 == 1 and fe1 == 0x10 and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc1ff; op2val:0xbc00; + valaddr_reg:x6; val_offset:2272*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2272*FLEN/8, x7, x2, x4) + +inst_1162: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc300; + valaddr_reg:x6; val_offset:2274*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2274*FLEN/8, x7, x2, x4) + +inst_1163: +// fs1 == 1 and fe1 == 0x10 and fm1 == 0x300 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc300; op2val:0xbc00; + valaddr_reg:x6; val_offset:2276*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2276*FLEN/8, x7, x2, x4) + +inst_1164: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc0ff; + valaddr_reg:x6; val_offset:2278*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2278*FLEN/8, x7, x2, x4) + +inst_1165: +// fs1 == 1 and fe1 == 0x10 and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc0ff; op2val:0xbc00; + valaddr_reg:x6; val_offset:2280*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2280*FLEN/8, x7, x2, x4) + +inst_1166: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc380; + valaddr_reg:x6; val_offset:2282*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2282*FLEN/8, x7, x2, x4) + +inst_1167: +// fs1 == 1 and fe1 == 0x10 and fm1 == 0x380 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc380; op2val:0xbc00; + valaddr_reg:x6; val_offset:2284*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2284*FLEN/8, x7, x2, x4) + +inst_1168: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc07f; + valaddr_reg:x6; val_offset:2286*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2286*FLEN/8, x7, x2, x4) + +inst_1169: +// fs1 == 1 and fe1 == 0x10 and fm1 == 0x07f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc07f; op2val:0xbc00; + valaddr_reg:x6; val_offset:2288*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2288*FLEN/8, x7, x2, x4) + +inst_1170: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc3c0; + valaddr_reg:x6; val_offset:2290*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2290*FLEN/8, x7, x2, x4) + +inst_1171: +// fs1 == 1 and fe1 == 0x10 and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc3c0; op2val:0xbc00; + valaddr_reg:x6; val_offset:2292*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2292*FLEN/8, x7, x2, x4) + +inst_1172: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc03f; + valaddr_reg:x6; val_offset:2294*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2294*FLEN/8, x7, x2, x4) + +inst_1173: +// fs1 == 1 and fe1 == 0x10 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc03f; op2val:0xbc00; + valaddr_reg:x6; val_offset:2296*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2296*FLEN/8, x7, x2, x4) + +inst_1174: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc3e0; + valaddr_reg:x6; val_offset:2298*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2298*FLEN/8, x7, x2, x4) + +inst_1175: +// fs1 == 1 and fe1 == 0x10 and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc3e0; op2val:0xbc00; + valaddr_reg:x6; val_offset:2300*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2300*FLEN/8, x7, x2, x4) + +inst_1176: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc01f; + valaddr_reg:x6; val_offset:2302*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2302*FLEN/8, x7, x2, x4) + +inst_1177: +// fs1 == 1 and fe1 == 0x10 and fm1 == 0x01f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc01f; op2val:0xbc00; + valaddr_reg:x6; val_offset:2304*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2304*FLEN/8, x7, x2, x4) + +inst_1178: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc3f0; + valaddr_reg:x6; val_offset:2306*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2306*FLEN/8, x7, x2, x4) + +inst_1179: +// fs1 == 1 and fe1 == 0x10 and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc3f0; op2val:0xbc00; + valaddr_reg:x6; val_offset:2308*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2308*FLEN/8, x7, x2, x4) + +inst_1180: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc00f; + valaddr_reg:x6; val_offset:2310*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2310*FLEN/8, x7, x2, x4) +RVTEST_SIGBASE(x2,signature_x2_11) + +inst_1181: +// fs1 == 1 and fe1 == 0x10 and fm1 == 0x00f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc00f; op2val:0xbc00; + valaddr_reg:x6; val_offset:2312*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2312*FLEN/8, x7, x2, x4) + +inst_1182: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc3f8; + valaddr_reg:x6; val_offset:2314*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2314*FLEN/8, x7, x2, x4) + +inst_1183: +// fs1 == 1 and fe1 == 0x10 and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc3f8; op2val:0xbc00; + valaddr_reg:x6; val_offset:2316*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2316*FLEN/8, x7, x2, x4) + +inst_1184: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc007; + valaddr_reg:x6; val_offset:2318*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2318*FLEN/8, x7, x2, x4) + +inst_1185: +// fs1 == 1 and fe1 == 0x10 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc007; op2val:0xbc00; + valaddr_reg:x6; val_offset:2320*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2320*FLEN/8, x7, x2, x4) + +inst_1186: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc3fc; + valaddr_reg:x6; val_offset:2322*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2322*FLEN/8, x7, x2, x4) + +inst_1187: +// fs1 == 1 and fe1 == 0x10 and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc3fc; op2val:0xbc00; + valaddr_reg:x6; val_offset:2324*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2324*FLEN/8, x7, x2, x4) + +inst_1188: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc003; + valaddr_reg:x6; val_offset:2326*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2326*FLEN/8, x7, x2, x4) + +inst_1189: +// fs1 == 1 and fe1 == 0x10 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc003; op2val:0xbc00; + valaddr_reg:x6; val_offset:2328*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2328*FLEN/8, x7, x2, x4) + +inst_1190: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc3fe; + valaddr_reg:x6; val_offset:2330*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2330*FLEN/8, x7, x2, x4) + +inst_1191: +// fs1 == 1 and fe1 == 0x10 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc3fe; op2val:0xbc00; + valaddr_reg:x6; val_offset:2332*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2332*FLEN/8, x7, x2, x4) + +inst_1192: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc001; + valaddr_reg:x6; val_offset:2334*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2334*FLEN/8, x7, x2, x4) + +inst_1193: +// fs1 == 1 and fe1 == 0x10 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc001; op2val:0xbc00; + valaddr_reg:x6; val_offset:2336*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2336*FLEN/8, x7, x2, x4) + +inst_1194: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc400; + valaddr_reg:x6; val_offset:2338*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2338*FLEN/8, x7, x2, x4) + +inst_1195: +// fs1 == 1 and fe1 == 0x11 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc400; op2val:0xbc00; + valaddr_reg:x6; val_offset:2340*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2340*FLEN/8, x7, x2, x4) + +inst_1196: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc7ff; + valaddr_reg:x6; val_offset:2342*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2342*FLEN/8, x7, x2, x4) + +inst_1197: +// fs1 == 1 and fe1 == 0x11 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc7ff; op2val:0xbc00; + valaddr_reg:x6; val_offset:2344*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2344*FLEN/8, x7, x2, x4) + +inst_1198: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc600; + valaddr_reg:x6; val_offset:2346*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2346*FLEN/8, x7, x2, x4) + +inst_1199: +// fs1 == 1 and fe1 == 0x11 and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc600; op2val:0xbc00; + valaddr_reg:x6; val_offset:2348*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2348*FLEN/8, x7, x2, x4) + +inst_1200: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc5ff; + valaddr_reg:x6; val_offset:2350*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2350*FLEN/8, x7, x2, x4) + +inst_1201: +// fs1 == 1 and fe1 == 0x11 and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc5ff; op2val:0xbc00; + valaddr_reg:x6; val_offset:2352*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2352*FLEN/8, x7, x2, x4) + +inst_1202: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc700; + valaddr_reg:x6; val_offset:2354*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2354*FLEN/8, x7, x2, x4) + +inst_1203: +// fs1 == 1 and fe1 == 0x11 and fm1 == 0x300 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc700; op2val:0xbc00; + valaddr_reg:x6; val_offset:2356*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2356*FLEN/8, x7, x2, x4) + +inst_1204: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc4ff; + valaddr_reg:x6; val_offset:2358*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2358*FLEN/8, x7, x2, x4) + +inst_1205: +// fs1 == 1 and fe1 == 0x11 and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc4ff; op2val:0xbc00; + valaddr_reg:x6; val_offset:2360*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2360*FLEN/8, x7, x2, x4) + +inst_1206: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc780; + valaddr_reg:x6; val_offset:2362*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2362*FLEN/8, x7, x2, x4) + +inst_1207: +// fs1 == 1 and fe1 == 0x11 and fm1 == 0x380 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc780; op2val:0xbc00; + valaddr_reg:x6; val_offset:2364*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2364*FLEN/8, x7, x2, x4) + +inst_1208: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc47f; + valaddr_reg:x6; val_offset:2366*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2366*FLEN/8, x7, x2, x4) + +inst_1209: +// fs1 == 1 and fe1 == 0x11 and fm1 == 0x07f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc47f; op2val:0xbc00; + valaddr_reg:x6; val_offset:2368*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2368*FLEN/8, x7, x2, x4) + +inst_1210: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc7c0; + valaddr_reg:x6; val_offset:2370*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2370*FLEN/8, x7, x2, x4) + +inst_1211: +// fs1 == 1 and fe1 == 0x11 and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc7c0; op2val:0xbc00; + valaddr_reg:x6; val_offset:2372*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2372*FLEN/8, x7, x2, x4) + +inst_1212: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc43f; + valaddr_reg:x6; val_offset:2374*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2374*FLEN/8, x7, x2, x4) + +inst_1213: +// fs1 == 1 and fe1 == 0x11 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc43f; op2val:0xbc00; + valaddr_reg:x6; val_offset:2376*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2376*FLEN/8, x7, x2, x4) + +inst_1214: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc7e0; + valaddr_reg:x6; val_offset:2378*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2378*FLEN/8, x7, x2, x4) + +inst_1215: +// fs1 == 1 and fe1 == 0x11 and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc7e0; op2val:0xbc00; + valaddr_reg:x6; val_offset:2380*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2380*FLEN/8, x7, x2, x4) + +inst_1216: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc41f; + valaddr_reg:x6; val_offset:2382*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2382*FLEN/8, x7, x2, x4) + +inst_1217: +// fs1 == 1 and fe1 == 0x11 and fm1 == 0x01f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc41f; op2val:0xbc00; + valaddr_reg:x6; val_offset:2384*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2384*FLEN/8, x7, x2, x4) + +inst_1218: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc7f0; + valaddr_reg:x6; val_offset:2386*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2386*FLEN/8, x7, x2, x4) + +inst_1219: +// fs1 == 1 and fe1 == 0x11 and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc7f0; op2val:0xbc00; + valaddr_reg:x6; val_offset:2388*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2388*FLEN/8, x7, x2, x4) + +inst_1220: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc40f; + valaddr_reg:x6; val_offset:2390*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2390*FLEN/8, x7, x2, x4) + +inst_1221: +// fs1 == 1 and fe1 == 0x11 and fm1 == 0x00f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc40f; op2val:0xbc00; + valaddr_reg:x6; val_offset:2392*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2392*FLEN/8, x7, x2, x4) + +inst_1222: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc7f8; + valaddr_reg:x6; val_offset:2394*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2394*FLEN/8, x7, x2, x4) + +inst_1223: +// fs1 == 1 and fe1 == 0x11 and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc7f8; op2val:0xbc00; + valaddr_reg:x6; val_offset:2396*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2396*FLEN/8, x7, x2, x4) + +inst_1224: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc407; + valaddr_reg:x6; val_offset:2398*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2398*FLEN/8, x7, x2, x4) + +inst_1225: +// fs1 == 1 and fe1 == 0x11 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc407; op2val:0xbc00; + valaddr_reg:x6; val_offset:2400*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2400*FLEN/8, x7, x2, x4) + +inst_1226: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc7fc; + valaddr_reg:x6; val_offset:2402*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2402*FLEN/8, x7, x2, x4) + +inst_1227: +// fs1 == 1 and fe1 == 0x11 and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc7fc; op2val:0xbc00; + valaddr_reg:x6; val_offset:2404*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2404*FLEN/8, x7, x2, x4) + +inst_1228: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc403; + valaddr_reg:x6; val_offset:2406*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2406*FLEN/8, x7, x2, x4) + +inst_1229: +// fs1 == 1 and fe1 == 0x11 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc403; op2val:0xbc00; + valaddr_reg:x6; val_offset:2408*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2408*FLEN/8, x7, x2, x4) + +inst_1230: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc7fe; + valaddr_reg:x6; val_offset:2410*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2410*FLEN/8, x7, x2, x4) + +inst_1231: +// fs1 == 1 and fe1 == 0x11 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc7fe; op2val:0xbc00; + valaddr_reg:x6; val_offset:2412*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2412*FLEN/8, x7, x2, x4) + +inst_1232: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc401; + valaddr_reg:x6; val_offset:2414*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2414*FLEN/8, x7, x2, x4) + +inst_1233: +// fs1 == 1 and fe1 == 0x11 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc401; op2val:0xbc00; + valaddr_reg:x6; val_offset:2416*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2416*FLEN/8, x7, x2, x4) + +inst_1234: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc800; + valaddr_reg:x6; val_offset:2418*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2418*FLEN/8, x7, x2, x4) + +inst_1235: +// fs1 == 1 and fe1 == 0x12 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc800; op2val:0xbc00; + valaddr_reg:x6; val_offset:2420*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2420*FLEN/8, x7, x2, x4) + +inst_1236: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xcbff; + valaddr_reg:x6; val_offset:2422*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2422*FLEN/8, x7, x2, x4) + +inst_1237: +// fs1 == 1 and fe1 == 0x12 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xcbff; op2val:0xbc00; + valaddr_reg:x6; val_offset:2424*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2424*FLEN/8, x7, x2, x4) + +inst_1238: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xca00; + valaddr_reg:x6; val_offset:2426*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2426*FLEN/8, x7, x2, x4) + +inst_1239: +// fs1 == 1 and fe1 == 0x12 and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xca00; op2val:0xbc00; + valaddr_reg:x6; val_offset:2428*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2428*FLEN/8, x7, x2, x4) + +inst_1240: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc9ff; + valaddr_reg:x6; val_offset:2430*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2430*FLEN/8, x7, x2, x4) + +inst_1241: +// fs1 == 1 and fe1 == 0x12 and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc9ff; op2val:0xbc00; + valaddr_reg:x6; val_offset:2432*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2432*FLEN/8, x7, x2, x4) + +inst_1242: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xcb00; + valaddr_reg:x6; val_offset:2434*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2434*FLEN/8, x7, x2, x4) + +inst_1243: +// fs1 == 1 and fe1 == 0x12 and fm1 == 0x300 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xcb00; op2val:0xbc00; + valaddr_reg:x6; val_offset:2436*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2436*FLEN/8, x7, x2, x4) + +inst_1244: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc8ff; + valaddr_reg:x6; val_offset:2438*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2438*FLEN/8, x7, x2, x4) + +inst_1245: +// fs1 == 1 and fe1 == 0x12 and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc8ff; op2val:0xbc00; + valaddr_reg:x6; val_offset:2440*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2440*FLEN/8, x7, x2, x4) + +inst_1246: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xcb80; + valaddr_reg:x6; val_offset:2442*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2442*FLEN/8, x7, x2, x4) + +inst_1247: +// fs1 == 1 and fe1 == 0x12 and fm1 == 0x380 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xcb80; op2val:0xbc00; + valaddr_reg:x6; val_offset:2444*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2444*FLEN/8, x7, x2, x4) + +inst_1248: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc87f; + valaddr_reg:x6; val_offset:2446*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2446*FLEN/8, x7, x2, x4) + +inst_1249: +// fs1 == 1 and fe1 == 0x12 and fm1 == 0x07f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc87f; op2val:0xbc00; + valaddr_reg:x6; val_offset:2448*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2448*FLEN/8, x7, x2, x4) + +inst_1250: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xcbc0; + valaddr_reg:x6; val_offset:2450*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2450*FLEN/8, x7, x2, x4) + +inst_1251: +// fs1 == 1 and fe1 == 0x12 and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xcbc0; op2val:0xbc00; + valaddr_reg:x6; val_offset:2452*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2452*FLEN/8, x7, x2, x4) + +inst_1252: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc83f; + valaddr_reg:x6; val_offset:2454*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2454*FLEN/8, x7, x2, x4) + +inst_1253: +// fs1 == 1 and fe1 == 0x12 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc83f; op2val:0xbc00; + valaddr_reg:x6; val_offset:2456*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2456*FLEN/8, x7, x2, x4) + +inst_1254: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xcbe0; + valaddr_reg:x6; val_offset:2458*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2458*FLEN/8, x7, x2, x4) + +inst_1255: +// fs1 == 1 and fe1 == 0x12 and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xcbe0; op2val:0xbc00; + valaddr_reg:x6; val_offset:2460*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2460*FLEN/8, x7, x2, x4) + +inst_1256: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc81f; + valaddr_reg:x6; val_offset:2462*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2462*FLEN/8, x7, x2, x4) + +inst_1257: +// fs1 == 1 and fe1 == 0x12 and fm1 == 0x01f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc81f; op2val:0xbc00; + valaddr_reg:x6; val_offset:2464*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2464*FLEN/8, x7, x2, x4) + +inst_1258: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xcbf0; + valaddr_reg:x6; val_offset:2466*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2466*FLEN/8, x7, x2, x4) + +inst_1259: +// fs1 == 1 and fe1 == 0x12 and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xcbf0; op2val:0xbc00; + valaddr_reg:x6; val_offset:2468*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2468*FLEN/8, x7, x2, x4) + +inst_1260: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc80f; + valaddr_reg:x6; val_offset:2470*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2470*FLEN/8, x7, x2, x4) + +inst_1261: +// fs1 == 1 and fe1 == 0x12 and fm1 == 0x00f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc80f; op2val:0xbc00; + valaddr_reg:x6; val_offset:2472*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2472*FLEN/8, x7, x2, x4) + +inst_1262: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xcbf8; + valaddr_reg:x6; val_offset:2474*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2474*FLEN/8, x7, x2, x4) + +inst_1263: +// fs1 == 1 and fe1 == 0x12 and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xcbf8; op2val:0xbc00; + valaddr_reg:x6; val_offset:2476*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2476*FLEN/8, x7, x2, x4) + +inst_1264: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc807; + valaddr_reg:x6; val_offset:2478*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2478*FLEN/8, x7, x2, x4) + +inst_1265: +// fs1 == 1 and fe1 == 0x12 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc807; op2val:0xbc00; + valaddr_reg:x6; val_offset:2480*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2480*FLEN/8, x7, x2, x4) + +inst_1266: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xcbfc; + valaddr_reg:x6; val_offset:2482*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2482*FLEN/8, x7, x2, x4) + +inst_1267: +// fs1 == 1 and fe1 == 0x12 and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xcbfc; op2val:0xbc00; + valaddr_reg:x6; val_offset:2484*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2484*FLEN/8, x7, x2, x4) + +inst_1268: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc803; + valaddr_reg:x6; val_offset:2486*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2486*FLEN/8, x7, x2, x4) + +inst_1269: +// fs1 == 1 and fe1 == 0x12 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc803; op2val:0xbc00; + valaddr_reg:x6; val_offset:2488*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2488*FLEN/8, x7, x2, x4) + +inst_1270: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xcbfe; + valaddr_reg:x6; val_offset:2490*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2490*FLEN/8, x7, x2, x4) + +inst_1271: +// fs1 == 1 and fe1 == 0x12 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xcbfe; op2val:0xbc00; + valaddr_reg:x6; val_offset:2492*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2492*FLEN/8, x7, x2, x4) + +inst_1272: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc801; + valaddr_reg:x6; val_offset:2494*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2494*FLEN/8, x7, x2, x4) + +inst_1273: +// fs1 == 1 and fe1 == 0x12 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc801; op2val:0xbc00; + valaddr_reg:x6; val_offset:2496*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2496*FLEN/8, x7, x2, x4) + +inst_1274: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x1; + valaddr_reg:x6; val_offset:2498*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2498*FLEN/8, x7, x2, x4) + +inst_1275: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x3ff; + valaddr_reg:x6; val_offset:2500*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2500*FLEN/8, x7, x2, x4) + +inst_1276: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x1; + valaddr_reg:x6; val_offset:2502*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2502*FLEN/8, x7, x2, x4) + +inst_1277: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x200; + valaddr_reg:x6; val_offset:2504*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2504*FLEN/8, x7, x2, x4) + +inst_1278: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x200; op2val:0x1; + valaddr_reg:x6; val_offset:2506*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2506*FLEN/8, x7, x2, x4) + +inst_1279: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x1ff; + valaddr_reg:x6; val_offset:2508*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2508*FLEN/8, x7, x2, x4) + +inst_1280: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1ff; op2val:0x1; + valaddr_reg:x6; val_offset:2510*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2510*FLEN/8, x7, x2, x4) + +inst_1281: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x300; + valaddr_reg:x6; val_offset:2512*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2512*FLEN/8, x7, x2, x4) + +inst_1282: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x300 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x300; op2val:0x1; + valaddr_reg:x6; val_offset:2514*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2514*FLEN/8, x7, x2, x4) + +inst_1283: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xff; + valaddr_reg:x6; val_offset:2516*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2516*FLEN/8, x7, x2, x4) + +inst_1284: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xff; op2val:0x1; + valaddr_reg:x6; val_offset:2518*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2518*FLEN/8, x7, x2, x4) + +inst_1285: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x380; + valaddr_reg:x6; val_offset:2520*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2520*FLEN/8, x7, x2, x4) + +inst_1286: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x380 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x380; op2val:0x1; + valaddr_reg:x6; val_offset:2522*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2522*FLEN/8, x7, x2, x4) + +inst_1287: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7f; + valaddr_reg:x6; val_offset:2524*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2524*FLEN/8, x7, x2, x4) + +inst_1288: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x07f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7f; op2val:0x1; + valaddr_reg:x6; val_offset:2526*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2526*FLEN/8, x7, x2, x4) + +inst_1289: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x3c0; + valaddr_reg:x6; val_offset:2528*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2528*FLEN/8, x7, x2, x4) + +inst_1290: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c0; op2val:0x1; + valaddr_reg:x6; val_offset:2530*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2530*FLEN/8, x7, x2, x4) + +inst_1291: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x3f; + valaddr_reg:x6; val_offset:2532*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2532*FLEN/8, x7, x2, x4) + +inst_1292: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3f; op2val:0x1; + valaddr_reg:x6; val_offset:2534*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2534*FLEN/8, x7, x2, x4) + +inst_1293: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x3e0; + valaddr_reg:x6; val_offset:2536*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2536*FLEN/8, x7, x2, x4) + +inst_1294: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3e0; op2val:0x1; + valaddr_reg:x6; val_offset:2538*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2538*FLEN/8, x7, x2, x4) + +inst_1295: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x1f; + valaddr_reg:x6; val_offset:2540*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2540*FLEN/8, x7, x2, x4) + +inst_1296: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x01f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1f; op2val:0x1; + valaddr_reg:x6; val_offset:2542*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2542*FLEN/8, x7, x2, x4) + +inst_1297: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x3f0; + valaddr_reg:x6; val_offset:2544*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2544*FLEN/8, x7, x2, x4) + +inst_1298: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3f0; op2val:0x1; + valaddr_reg:x6; val_offset:2546*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2546*FLEN/8, x7, x2, x4) + +inst_1299: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xf; + valaddr_reg:x6; val_offset:2548*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2548*FLEN/8, x7, x2, x4) + +inst_1300: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf; op2val:0x1; + valaddr_reg:x6; val_offset:2550*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2550*FLEN/8, x7, x2, x4) + +inst_1301: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x3f8; + valaddr_reg:x6; val_offset:2552*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2552*FLEN/8, x7, x2, x4) + +inst_1302: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3f8; op2val:0x1; + valaddr_reg:x6; val_offset:2554*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2554*FLEN/8, x7, x2, x4) + +inst_1303: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7; + valaddr_reg:x6; val_offset:2556*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2556*FLEN/8, x7, x2, x4) + +inst_1304: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7; op2val:0x1; + valaddr_reg:x6; val_offset:2558*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2558*FLEN/8, x7, x2, x4) + +inst_1305: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x3fc; + valaddr_reg:x6; val_offset:2560*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2560*FLEN/8, x7, x2, x4) + +inst_1306: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fc; op2val:0x1; + valaddr_reg:x6; val_offset:2562*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2562*FLEN/8, x7, x2, x4) + +inst_1307: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x3; + valaddr_reg:x6; val_offset:2564*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2564*FLEN/8, x7, x2, x4) + +inst_1308: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x003 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3; op2val:0x1; + valaddr_reg:x6; val_offset:2566*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2566*FLEN/8, x7, x2, x4) +RVTEST_SIGBASE(x2,signature_x2_12) + +inst_1309: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x3fe; + valaddr_reg:x6; val_offset:2568*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2568*FLEN/8, x7, x2, x4) + +inst_1310: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fe; op2val:0x1; + valaddr_reg:x6; val_offset:2570*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2570*FLEN/8, x7, x2, x4) + +inst_1311: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1b6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x1b6; + valaddr_reg:x6; val_offset:2572*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2572*FLEN/8, x7, x2, x4) + +inst_1312: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1b6; op2val:0x1; + valaddr_reg:x6; val_offset:2574*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2574*FLEN/8, x7, x2, x4) + +inst_1313: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x36d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x36d; + valaddr_reg:x6; val_offset:2576*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2576*FLEN/8, x7, x2, x4) + +inst_1314: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x36d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x36d; op2val:0x1; + valaddr_reg:x6; val_offset:2578*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2578*FLEN/8, x7, x2, x4) + +inst_1315: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0cc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xcc; + valaddr_reg:x6; val_offset:2580*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2580*FLEN/8, x7, x2, x4) + +inst_1316: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0cc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xcc; op2val:0x1; + valaddr_reg:x6; val_offset:2582*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2582*FLEN/8, x7, x2, x4) + +inst_1317: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x333 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x333; + valaddr_reg:x6; val_offset:2584*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2584*FLEN/8, x7, x2, x4) + +inst_1318: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x333 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x333; op2val:0x1; + valaddr_reg:x6; val_offset:2586*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2586*FLEN/8, x7, x2, x4) + +inst_1319: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1dd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x1dd; + valaddr_reg:x6; val_offset:2588*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2588*FLEN/8, x7, x2, x4) + +inst_1320: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1dd; op2val:0x1; + valaddr_reg:x6; val_offset:2590*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2590*FLEN/8, x7, x2, x4) + +inst_1321: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x222 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x222; + valaddr_reg:x6; val_offset:2592*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2592*FLEN/8, x7, x2, x4) + +inst_1322: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x222 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x222; op2val:0x1; + valaddr_reg:x6; val_offset:2594*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2594*FLEN/8, x7, x2, x4) + +inst_1323: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x124 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x124; + valaddr_reg:x6; val_offset:2596*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2596*FLEN/8, x7, x2, x4) + +inst_1324: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x124 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x124; op2val:0x1; + valaddr_reg:x6; val_offset:2598*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2598*FLEN/8, x7, x2, x4) + +inst_1325: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2db and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x2db; + valaddr_reg:x6; val_offset:2600*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2600*FLEN/8, x7, x2, x4) + +inst_1326: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2db; op2val:0x1; + valaddr_reg:x6; val_offset:2602*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2602*FLEN/8, x7, x2, x4) + +inst_1327: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x199 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x199; + valaddr_reg:x6; val_offset:2604*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2604*FLEN/8, x7, x2, x4) + +inst_1328: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x199 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x199; op2val:0x1; + valaddr_reg:x6; val_offset:2606*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2606*FLEN/8, x7, x2, x4) + +inst_1329: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x266 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x266; + valaddr_reg:x6; val_offset:2608*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2608*FLEN/8, x7, x2, x4) + +inst_1330: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x266 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x266; op2val:0x1; + valaddr_reg:x6; val_offset:2610*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2610*FLEN/8, x7, x2, x4) + +inst_1331: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x401; + valaddr_reg:x6; val_offset:2612*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2612*FLEN/8, x7, x2, x4) + +inst_1332: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x1; + valaddr_reg:x6; val_offset:2614*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2614*FLEN/8, x7, x2, x4) + +inst_1333: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x400; + valaddr_reg:x6; val_offset:2616*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2616*FLEN/8, x7, x2, x4) + +inst_1334: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x1; + valaddr_reg:x6; val_offset:2618*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2618*FLEN/8, x7, x2, x4) + +inst_1335: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7ff; + valaddr_reg:x6; val_offset:2620*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2620*FLEN/8, x7, x2, x4) + +inst_1336: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ff; op2val:0x1; + valaddr_reg:x6; val_offset:2622*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2622*FLEN/8, x7, x2, x4) + +inst_1337: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x600; + valaddr_reg:x6; val_offset:2624*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2624*FLEN/8, x7, x2, x4) + +inst_1338: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x600; op2val:0x1; + valaddr_reg:x6; val_offset:2626*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2626*FLEN/8, x7, x2, x4) + +inst_1339: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x5ff; + valaddr_reg:x6; val_offset:2628*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2628*FLEN/8, x7, x2, x4) + +inst_1340: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5ff; op2val:0x1; + valaddr_reg:x6; val_offset:2630*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2630*FLEN/8, x7, x2, x4) + +inst_1341: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x700; + valaddr_reg:x6; val_offset:2632*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2632*FLEN/8, x7, x2, x4) + +inst_1342: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x300 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x700; op2val:0x1; + valaddr_reg:x6; val_offset:2634*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2634*FLEN/8, x7, x2, x4) + +inst_1343: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x4ff; + valaddr_reg:x6; val_offset:2636*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2636*FLEN/8, x7, x2, x4) + +inst_1344: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4ff; op2val:0x1; + valaddr_reg:x6; val_offset:2638*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2638*FLEN/8, x7, x2, x4) + +inst_1345: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x780; + valaddr_reg:x6; val_offset:2640*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2640*FLEN/8, x7, x2, x4) + +inst_1346: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x380 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x780; op2val:0x1; + valaddr_reg:x6; val_offset:2642*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2642*FLEN/8, x7, x2, x4) + +inst_1347: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x47f; + valaddr_reg:x6; val_offset:2644*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2644*FLEN/8, x7, x2, x4) + +inst_1348: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x07f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x47f; op2val:0x1; + valaddr_reg:x6; val_offset:2646*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2646*FLEN/8, x7, x2, x4) + +inst_1349: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7c0; + valaddr_reg:x6; val_offset:2648*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2648*FLEN/8, x7, x2, x4) + +inst_1350: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c0; op2val:0x1; + valaddr_reg:x6; val_offset:2650*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2650*FLEN/8, x7, x2, x4) + +inst_1351: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x43f; + valaddr_reg:x6; val_offset:2652*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2652*FLEN/8, x7, x2, x4) + +inst_1352: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x43f; op2val:0x1; + valaddr_reg:x6; val_offset:2654*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2654*FLEN/8, x7, x2, x4) + +inst_1353: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7e0; + valaddr_reg:x6; val_offset:2656*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2656*FLEN/8, x7, x2, x4) + +inst_1354: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e0; op2val:0x1; + valaddr_reg:x6; val_offset:2658*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2658*FLEN/8, x7, x2, x4) + +inst_1355: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x41f; + valaddr_reg:x6; val_offset:2660*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2660*FLEN/8, x7, x2, x4) + +inst_1356: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x01f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x41f; op2val:0x1; + valaddr_reg:x6; val_offset:2662*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2662*FLEN/8, x7, x2, x4) + +inst_1357: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7f0; + valaddr_reg:x6; val_offset:2664*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2664*FLEN/8, x7, x2, x4) + +inst_1358: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7f0; op2val:0x1; + valaddr_reg:x6; val_offset:2666*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2666*FLEN/8, x7, x2, x4) + +inst_1359: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x40f; + valaddr_reg:x6; val_offset:2668*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2668*FLEN/8, x7, x2, x4) + +inst_1360: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x00f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x40f; op2val:0x1; + valaddr_reg:x6; val_offset:2670*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2670*FLEN/8, x7, x2, x4) + +inst_1361: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7f8; + valaddr_reg:x6; val_offset:2672*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2672*FLEN/8, x7, x2, x4) + +inst_1362: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7f8; op2val:0x1; + valaddr_reg:x6; val_offset:2674*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2674*FLEN/8, x7, x2, x4) + +inst_1363: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x407; + valaddr_reg:x6; val_offset:2676*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2676*FLEN/8, x7, x2, x4) + +inst_1364: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x407; op2val:0x1; + valaddr_reg:x6; val_offset:2678*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2678*FLEN/8, x7, x2, x4) + +inst_1365: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7fc; + valaddr_reg:x6; val_offset:2680*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2680*FLEN/8, x7, x2, x4) + +inst_1366: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7fc; op2val:0x1; + valaddr_reg:x6; val_offset:2682*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2682*FLEN/8, x7, x2, x4) + +inst_1367: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x403; + valaddr_reg:x6; val_offset:2684*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2684*FLEN/8, x7, x2, x4) + +inst_1368: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x003 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x403; op2val:0x1; + valaddr_reg:x6; val_offset:2686*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2686*FLEN/8, x7, x2, x4) + +inst_1369: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7fe; + valaddr_reg:x6; val_offset:2688*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2688*FLEN/8, x7, x2, x4) + +inst_1370: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7fe; op2val:0x1; + valaddr_reg:x6; val_offset:2690*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2690*FLEN/8, x7, x2, x4) + +inst_1371: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x801; + valaddr_reg:x6; val_offset:2692*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2692*FLEN/8, x7, x2, x4) + +inst_1372: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x801; op2val:0x1; + valaddr_reg:x6; val_offset:2694*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2694*FLEN/8, x7, x2, x4) + +inst_1373: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x800; + valaddr_reg:x6; val_offset:2696*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2696*FLEN/8, x7, x2, x4) + +inst_1374: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x800; op2val:0x1; + valaddr_reg:x6; val_offset:2698*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2698*FLEN/8, x7, x2, x4) + +inst_1375: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xbff; + valaddr_reg:x6; val_offset:2700*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2700*FLEN/8, x7, x2, x4) + +inst_1376: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbff; op2val:0x1; + valaddr_reg:x6; val_offset:2702*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2702*FLEN/8, x7, x2, x4) + +inst_1377: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xa00; + valaddr_reg:x6; val_offset:2704*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2704*FLEN/8, x7, x2, x4) + +inst_1378: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xa00; op2val:0x1; + valaddr_reg:x6; val_offset:2706*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2706*FLEN/8, x7, x2, x4) + +inst_1379: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x9ff; + valaddr_reg:x6; val_offset:2708*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2708*FLEN/8, x7, x2, x4) + +inst_1380: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x9ff; op2val:0x1; + valaddr_reg:x6; val_offset:2710*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2710*FLEN/8, x7, x2, x4) + +inst_1381: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xb00; + valaddr_reg:x6; val_offset:2712*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2712*FLEN/8, x7, x2, x4) + +inst_1382: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x300 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xb00; op2val:0x1; + valaddr_reg:x6; val_offset:2714*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2714*FLEN/8, x7, x2, x4) + +inst_1383: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x8ff; + valaddr_reg:x6; val_offset:2716*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2716*FLEN/8, x7, x2, x4) + +inst_1384: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8ff; op2val:0x1; + valaddr_reg:x6; val_offset:2718*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2718*FLEN/8, x7, x2, x4) + +inst_1385: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xb80; + valaddr_reg:x6; val_offset:2720*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2720*FLEN/8, x7, x2, x4) + +inst_1386: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x380 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xb80; op2val:0x1; + valaddr_reg:x6; val_offset:2722*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2722*FLEN/8, x7, x2, x4) + +inst_1387: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x87f; + valaddr_reg:x6; val_offset:2724*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2724*FLEN/8, x7, x2, x4) + +inst_1388: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x07f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x87f; op2val:0x1; + valaddr_reg:x6; val_offset:2726*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2726*FLEN/8, x7, x2, x4) + +inst_1389: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xbc0; + valaddr_reg:x6; val_offset:2728*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2728*FLEN/8, x7, x2, x4) + +inst_1390: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc0; op2val:0x1; + valaddr_reg:x6; val_offset:2730*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2730*FLEN/8, x7, x2, x4) + +inst_1391: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x83f; + valaddr_reg:x6; val_offset:2732*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2732*FLEN/8, x7, x2, x4) + +inst_1392: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83f; op2val:0x1; + valaddr_reg:x6; val_offset:2734*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2734*FLEN/8, x7, x2, x4) + +inst_1393: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xbe0; + valaddr_reg:x6; val_offset:2736*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2736*FLEN/8, x7, x2, x4) + +inst_1394: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbe0; op2val:0x1; + valaddr_reg:x6; val_offset:2738*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2738*FLEN/8, x7, x2, x4) + +inst_1395: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x81f; + valaddr_reg:x6; val_offset:2740*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2740*FLEN/8, x7, x2, x4) + +inst_1396: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x01f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x81f; op2val:0x1; + valaddr_reg:x6; val_offset:2742*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2742*FLEN/8, x7, x2, x4) + +inst_1397: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xbf0; + valaddr_reg:x6; val_offset:2744*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2744*FLEN/8, x7, x2, x4) + +inst_1398: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbf0; op2val:0x1; + valaddr_reg:x6; val_offset:2746*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2746*FLEN/8, x7, x2, x4) + +inst_1399: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x80f; + valaddr_reg:x6; val_offset:2748*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2748*FLEN/8, x7, x2, x4) + +inst_1400: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x00f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x80f; op2val:0x1; + valaddr_reg:x6; val_offset:2750*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2750*FLEN/8, x7, x2, x4) + +inst_1401: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xbf8; + valaddr_reg:x6; val_offset:2752*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2752*FLEN/8, x7, x2, x4) + +inst_1402: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbf8; op2val:0x1; + valaddr_reg:x6; val_offset:2754*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2754*FLEN/8, x7, x2, x4) + +inst_1403: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x807; + valaddr_reg:x6; val_offset:2756*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2756*FLEN/8, x7, x2, x4) + +inst_1404: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x807; op2val:0x1; + valaddr_reg:x6; val_offset:2758*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2758*FLEN/8, x7, x2, x4) + +inst_1405: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xbfc; + valaddr_reg:x6; val_offset:2760*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2760*FLEN/8, x7, x2, x4) + +inst_1406: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbfc; op2val:0x1; + valaddr_reg:x6; val_offset:2762*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2762*FLEN/8, x7, x2, x4) + +inst_1407: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x803; + valaddr_reg:x6; val_offset:2764*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2764*FLEN/8, x7, x2, x4) + +inst_1408: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x003 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x803; op2val:0x1; + valaddr_reg:x6; val_offset:2766*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2766*FLEN/8, x7, x2, x4) + +inst_1409: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xbfe; + valaddr_reg:x6; val_offset:2768*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2768*FLEN/8, x7, x2, x4) + +inst_1410: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbfe; op2val:0x1; + valaddr_reg:x6; val_offset:2770*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2770*FLEN/8, x7, x2, x4) + +inst_1411: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xc01; + valaddr_reg:x6; val_offset:2772*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2772*FLEN/8, x7, x2, x4) + +inst_1412: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc01; op2val:0x1; + valaddr_reg:x6; val_offset:2774*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2774*FLEN/8, x7, x2, x4) + +inst_1413: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xc00; + valaddr_reg:x6; val_offset:2776*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2776*FLEN/8, x7, x2, x4) + +inst_1414: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc00; op2val:0x1; + valaddr_reg:x6; val_offset:2778*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2778*FLEN/8, x7, x2, x4) + +inst_1415: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xfff; + valaddr_reg:x6; val_offset:2780*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2780*FLEN/8, x7, x2, x4) + +inst_1416: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfff; op2val:0x1; + valaddr_reg:x6; val_offset:2782*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2782*FLEN/8, x7, x2, x4) + +inst_1417: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xe00; + valaddr_reg:x6; val_offset:2784*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2784*FLEN/8, x7, x2, x4) + +inst_1418: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xe00; op2val:0x1; + valaddr_reg:x6; val_offset:2786*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2786*FLEN/8, x7, x2, x4) + +inst_1419: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xdff; + valaddr_reg:x6; val_offset:2788*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2788*FLEN/8, x7, x2, x4) + +inst_1420: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xdff; op2val:0x1; + valaddr_reg:x6; val_offset:2790*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2790*FLEN/8, x7, x2, x4) + +inst_1421: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xf00; + valaddr_reg:x6; val_offset:2792*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2792*FLEN/8, x7, x2, x4) + +inst_1422: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x300 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf00; op2val:0x1; + valaddr_reg:x6; val_offset:2794*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2794*FLEN/8, x7, x2, x4) + +inst_1423: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xcff; + valaddr_reg:x6; val_offset:2796*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2796*FLEN/8, x7, x2, x4) + +inst_1424: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xcff; op2val:0x1; + valaddr_reg:x6; val_offset:2798*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2798*FLEN/8, x7, x2, x4) + +inst_1425: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xf80; + valaddr_reg:x6; val_offset:2800*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2800*FLEN/8, x7, x2, x4) + +inst_1426: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x380 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf80; op2val:0x1; + valaddr_reg:x6; val_offset:2802*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2802*FLEN/8, x7, x2, x4) + +inst_1427: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xc7f; + valaddr_reg:x6; val_offset:2804*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2804*FLEN/8, x7, x2, x4) + +inst_1428: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x07f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc7f; op2val:0x1; + valaddr_reg:x6; val_offset:2806*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2806*FLEN/8, x7, x2, x4) + +inst_1429: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xfc0; + valaddr_reg:x6; val_offset:2808*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2808*FLEN/8, x7, x2, x4) + +inst_1430: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc0; op2val:0x1; + valaddr_reg:x6; val_offset:2810*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2810*FLEN/8, x7, x2, x4) + +inst_1431: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xc3f; + valaddr_reg:x6; val_offset:2812*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2812*FLEN/8, x7, x2, x4) + +inst_1432: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc3f; op2val:0x1; + valaddr_reg:x6; val_offset:2814*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2814*FLEN/8, x7, x2, x4) + +inst_1433: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xfe0; + valaddr_reg:x6; val_offset:2816*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2816*FLEN/8, x7, x2, x4) + +inst_1434: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe0; op2val:0x1; + valaddr_reg:x6; val_offset:2818*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2818*FLEN/8, x7, x2, x4) + +inst_1435: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xc1f; + valaddr_reg:x6; val_offset:2820*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2820*FLEN/8, x7, x2, x4) + +inst_1436: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x01f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc1f; op2val:0x1; + valaddr_reg:x6; val_offset:2822*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2822*FLEN/8, x7, x2, x4) +RVTEST_SIGBASE(x2,signature_x2_13) + +inst_1437: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xff0; + valaddr_reg:x6; val_offset:2824*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2824*FLEN/8, x7, x2, x4) + +inst_1438: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xff0; op2val:0x1; + valaddr_reg:x6; val_offset:2826*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2826*FLEN/8, x7, x2, x4) + +inst_1439: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xc0f; + valaddr_reg:x6; val_offset:2828*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2828*FLEN/8, x7, x2, x4) + +inst_1440: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x00f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc0f; op2val:0x1; + valaddr_reg:x6; val_offset:2830*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2830*FLEN/8, x7, x2, x4) + +inst_1441: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xff8; + valaddr_reg:x6; val_offset:2832*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2832*FLEN/8, x7, x2, x4) + +inst_1442: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xff8; op2val:0x1; + valaddr_reg:x6; val_offset:2834*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2834*FLEN/8, x7, x2, x4) + +inst_1443: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xc07; + valaddr_reg:x6; val_offset:2836*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2836*FLEN/8, x7, x2, x4) + +inst_1444: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc07; op2val:0x1; + valaddr_reg:x6; val_offset:2838*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2838*FLEN/8, x7, x2, x4) + +inst_1445: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xffc; + valaddr_reg:x6; val_offset:2840*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2840*FLEN/8, x7, x2, x4) + +inst_1446: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xffc; op2val:0x1; + valaddr_reg:x6; val_offset:2842*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2842*FLEN/8, x7, x2, x4) + +inst_1447: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xc03; + valaddr_reg:x6; val_offset:2844*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2844*FLEN/8, x7, x2, x4) + +inst_1448: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x003 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc03; op2val:0x1; + valaddr_reg:x6; val_offset:2846*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2846*FLEN/8, x7, x2, x4) + +inst_1449: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xffe; + valaddr_reg:x6; val_offset:2848*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2848*FLEN/8, x7, x2, x4) + +inst_1450: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xffe; op2val:0x1; + valaddr_reg:x6; val_offset:2850*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2850*FLEN/8, x7, x2, x4) + +inst_1451: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8001; + valaddr_reg:x6; val_offset:2852*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2852*FLEN/8, x7, x2, x4) + +inst_1452: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x83ff; + valaddr_reg:x6; val_offset:2854*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2854*FLEN/8, x7, x2, x4) + +inst_1453: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8001; + valaddr_reg:x6; val_offset:2856*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2856*FLEN/8, x7, x2, x4) + +inst_1454: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8200; + valaddr_reg:x6; val_offset:2858*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2858*FLEN/8, x7, x2, x4) + +inst_1455: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8200; op2val:0x8001; + valaddr_reg:x6; val_offset:2860*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2860*FLEN/8, x7, x2, x4) + +inst_1456: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x81ff; + valaddr_reg:x6; val_offset:2862*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2862*FLEN/8, x7, x2, x4) + +inst_1457: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x81ff; op2val:0x8001; + valaddr_reg:x6; val_offset:2864*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2864*FLEN/8, x7, x2, x4) + +inst_1458: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8300; + valaddr_reg:x6; val_offset:2866*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2866*FLEN/8, x7, x2, x4) + +inst_1459: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x300 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8300; op2val:0x8001; + valaddr_reg:x6; val_offset:2868*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2868*FLEN/8, x7, x2, x4) + +inst_1460: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x80ff; + valaddr_reg:x6; val_offset:2870*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2870*FLEN/8, x7, x2, x4) + +inst_1461: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x80ff; op2val:0x8001; + valaddr_reg:x6; val_offset:2872*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2872*FLEN/8, x7, x2, x4) + +inst_1462: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8380; + valaddr_reg:x6; val_offset:2874*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2874*FLEN/8, x7, x2, x4) + +inst_1463: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x380 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8380; op2val:0x8001; + valaddr_reg:x6; val_offset:2876*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2876*FLEN/8, x7, x2, x4) + +inst_1464: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x807f; + valaddr_reg:x6; val_offset:2878*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2878*FLEN/8, x7, x2, x4) + +inst_1465: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x07f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x807f; op2val:0x8001; + valaddr_reg:x6; val_offset:2880*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2880*FLEN/8, x7, x2, x4) + +inst_1466: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x83c0; + valaddr_reg:x6; val_offset:2882*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2882*FLEN/8, x7, x2, x4) + +inst_1467: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83c0; op2val:0x8001; + valaddr_reg:x6; val_offset:2884*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2884*FLEN/8, x7, x2, x4) + +inst_1468: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x803f; + valaddr_reg:x6; val_offset:2886*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2886*FLEN/8, x7, x2, x4) + +inst_1469: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x803f; op2val:0x8001; + valaddr_reg:x6; val_offset:2888*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2888*FLEN/8, x7, x2, x4) + +inst_1470: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x83e0; + valaddr_reg:x6; val_offset:2890*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2890*FLEN/8, x7, x2, x4) + +inst_1471: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83e0; op2val:0x8001; + valaddr_reg:x6; val_offset:2892*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2892*FLEN/8, x7, x2, x4) + +inst_1472: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x801f; + valaddr_reg:x6; val_offset:2894*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2894*FLEN/8, x7, x2, x4) + +inst_1473: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x01f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x801f; op2val:0x8001; + valaddr_reg:x6; val_offset:2896*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2896*FLEN/8, x7, x2, x4) + +inst_1474: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x83f0; + valaddr_reg:x6; val_offset:2898*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2898*FLEN/8, x7, x2, x4) + +inst_1475: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83f0; op2val:0x8001; + valaddr_reg:x6; val_offset:2900*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2900*FLEN/8, x7, x2, x4) + +inst_1476: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x800f; + valaddr_reg:x6; val_offset:2902*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2902*FLEN/8, x7, x2, x4) + +inst_1477: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x00f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x800f; op2val:0x8001; + valaddr_reg:x6; val_offset:2904*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2904*FLEN/8, x7, x2, x4) + +inst_1478: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x83f8; + valaddr_reg:x6; val_offset:2906*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2906*FLEN/8, x7, x2, x4) + +inst_1479: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83f8; op2val:0x8001; + valaddr_reg:x6; val_offset:2908*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2908*FLEN/8, x7, x2, x4) + +inst_1480: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8007; + valaddr_reg:x6; val_offset:2910*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2910*FLEN/8, x7, x2, x4) + +inst_1481: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8007; op2val:0x8001; + valaddr_reg:x6; val_offset:2912*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2912*FLEN/8, x7, x2, x4) + +inst_1482: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x83fc; + valaddr_reg:x6; val_offset:2914*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2914*FLEN/8, x7, x2, x4) + +inst_1483: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fc; op2val:0x8001; + valaddr_reg:x6; val_offset:2916*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2916*FLEN/8, x7, x2, x4) + +inst_1484: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8003; + valaddr_reg:x6; val_offset:2918*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2918*FLEN/8, x7, x2, x4) + +inst_1485: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8003; op2val:0x8001; + valaddr_reg:x6; val_offset:2920*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2920*FLEN/8, x7, x2, x4) + +inst_1486: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x83fe; + valaddr_reg:x6; val_offset:2922*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2922*FLEN/8, x7, x2, x4) + +inst_1487: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x8001; + valaddr_reg:x6; val_offset:2924*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2924*FLEN/8, x7, x2, x4) + +inst_1488: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1b6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x81b6; + valaddr_reg:x6; val_offset:2926*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2926*FLEN/8, x7, x2, x4) + +inst_1489: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x81b6; op2val:0x8001; + valaddr_reg:x6; val_offset:2928*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2928*FLEN/8, x7, x2, x4) + +inst_1490: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x36d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x836d; + valaddr_reg:x6; val_offset:2930*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2930*FLEN/8, x7, x2, x4) + +inst_1491: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x36d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x836d; op2val:0x8001; + valaddr_reg:x6; val_offset:2932*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2932*FLEN/8, x7, x2, x4) + +inst_1492: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0cc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x80cc; + valaddr_reg:x6; val_offset:2934*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2934*FLEN/8, x7, x2, x4) + +inst_1493: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0cc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x80cc; op2val:0x8001; + valaddr_reg:x6; val_offset:2936*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2936*FLEN/8, x7, x2, x4) + +inst_1494: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x333 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8333; + valaddr_reg:x6; val_offset:2938*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2938*FLEN/8, x7, x2, x4) + +inst_1495: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x333 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8333; op2val:0x8001; + valaddr_reg:x6; val_offset:2940*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2940*FLEN/8, x7, x2, x4) + +inst_1496: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1dd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x81dd; + valaddr_reg:x6; val_offset:2942*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2942*FLEN/8, x7, x2, x4) + +inst_1497: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1dd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x81dd; op2val:0x8001; + valaddr_reg:x6; val_offset:2944*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2944*FLEN/8, x7, x2, x4) + +inst_1498: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x222 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8222; + valaddr_reg:x6; val_offset:2946*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2946*FLEN/8, x7, x2, x4) + +inst_1499: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x222 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8222; op2val:0x8001; + valaddr_reg:x6; val_offset:2948*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2948*FLEN/8, x7, x2, x4) + +inst_1500: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x124 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8124; + valaddr_reg:x6; val_offset:2950*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2950*FLEN/8, x7, x2, x4) + +inst_1501: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x124 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8124; op2val:0x8001; + valaddr_reg:x6; val_offset:2952*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2952*FLEN/8, x7, x2, x4) + +inst_1502: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2db and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x82db; + valaddr_reg:x6; val_offset:2954*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2954*FLEN/8, x7, x2, x4) + +inst_1503: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x82db; op2val:0x8001; + valaddr_reg:x6; val_offset:2956*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2956*FLEN/8, x7, x2, x4) + +inst_1504: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x199 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8199; + valaddr_reg:x6; val_offset:2958*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2958*FLEN/8, x7, x2, x4) + +inst_1505: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x199 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8199; op2val:0x8001; + valaddr_reg:x6; val_offset:2960*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2960*FLEN/8, x7, x2, x4) + +inst_1506: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x266 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8266; + valaddr_reg:x6; val_offset:2962*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2962*FLEN/8, x7, x2, x4) + +inst_1507: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x266 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8266; op2val:0x8001; + valaddr_reg:x6; val_offset:2964*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2964*FLEN/8, x7, x2, x4) + +inst_1508: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xac01; + valaddr_reg:x6; val_offset:2966*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2966*FLEN/8, x7, x2, x4) + +inst_1509: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xac01; op2val:0x8001; + valaddr_reg:x6; val_offset:2968*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2968*FLEN/8, x7, x2, x4) + +inst_1510: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xac00; + valaddr_reg:x6; val_offset:2970*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2970*FLEN/8, x7, x2, x4) + +inst_1511: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xac00; op2val:0x8001; + valaddr_reg:x6; val_offset:2972*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2972*FLEN/8, x7, x2, x4) + +inst_1512: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xafff; + valaddr_reg:x6; val_offset:2974*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2974*FLEN/8, x7, x2, x4) + +inst_1513: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xafff; op2val:0x8001; + valaddr_reg:x6; val_offset:2976*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2976*FLEN/8, x7, x2, x4) + +inst_1514: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xae00; + valaddr_reg:x6; val_offset:2978*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2978*FLEN/8, x7, x2, x4) + +inst_1515: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xae00; op2val:0x8001; + valaddr_reg:x6; val_offset:2980*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2980*FLEN/8, x7, x2, x4) + +inst_1516: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xadff; + valaddr_reg:x6; val_offset:2982*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2982*FLEN/8, x7, x2, x4) + +inst_1517: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xadff; op2val:0x8001; + valaddr_reg:x6; val_offset:2984*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2984*FLEN/8, x7, x2, x4) + +inst_1518: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xaf00; + valaddr_reg:x6; val_offset:2986*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2986*FLEN/8, x7, x2, x4) + +inst_1519: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x300 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xaf00; op2val:0x8001; + valaddr_reg:x6; val_offset:2988*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2988*FLEN/8, x7, x2, x4) + +inst_1520: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xacff; + valaddr_reg:x6; val_offset:2990*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2990*FLEN/8, x7, x2, x4) + +inst_1521: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xacff; op2val:0x8001; + valaddr_reg:x6; val_offset:2992*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2992*FLEN/8, x7, x2, x4) + +inst_1522: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xaf80; + valaddr_reg:x6; val_offset:2994*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2994*FLEN/8, x7, x2, x4) + +inst_1523: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x380 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xaf80; op2val:0x8001; + valaddr_reg:x6; val_offset:2996*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2996*FLEN/8, x7, x2, x4) + +inst_1524: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xac7f; + valaddr_reg:x6; val_offset:2998*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 2998*FLEN/8, x7, x2, x4) + +inst_1525: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x07f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xac7f; op2val:0x8001; + valaddr_reg:x6; val_offset:3000*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3000*FLEN/8, x7, x2, x4) + +inst_1526: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xafc0; + valaddr_reg:x6; val_offset:3002*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3002*FLEN/8, x7, x2, x4) + +inst_1527: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xafc0; op2val:0x8001; + valaddr_reg:x6; val_offset:3004*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3004*FLEN/8, x7, x2, x4) + +inst_1528: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xac3f; + valaddr_reg:x6; val_offset:3006*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3006*FLEN/8, x7, x2, x4) + +inst_1529: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x03f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xac3f; op2val:0x8001; + valaddr_reg:x6; val_offset:3008*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3008*FLEN/8, x7, x2, x4) + +inst_1530: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xafe0; + valaddr_reg:x6; val_offset:3010*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3010*FLEN/8, x7, x2, x4) + +inst_1531: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xafe0; op2val:0x8001; + valaddr_reg:x6; val_offset:3012*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3012*FLEN/8, x7, x2, x4) + +inst_1532: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xac1f; + valaddr_reg:x6; val_offset:3014*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3014*FLEN/8, x7, x2, x4) + +inst_1533: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x01f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xac1f; op2val:0x8001; + valaddr_reg:x6; val_offset:3016*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3016*FLEN/8, x7, x2, x4) + +inst_1534: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xaff0; + valaddr_reg:x6; val_offset:3018*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3018*FLEN/8, x7, x2, x4) + +inst_1535: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xaff0; op2val:0x8001; + valaddr_reg:x6; val_offset:3020*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3020*FLEN/8, x7, x2, x4) + +inst_1536: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xac0f; + valaddr_reg:x6; val_offset:3022*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3022*FLEN/8, x7, x2, x4) + +inst_1537: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x00f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xac0f; op2val:0x8001; + valaddr_reg:x6; val_offset:3024*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3024*FLEN/8, x7, x2, x4) + +inst_1538: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xaff8; + valaddr_reg:x6; val_offset:3026*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3026*FLEN/8, x7, x2, x4) + +inst_1539: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xaff8; op2val:0x8001; + valaddr_reg:x6; val_offset:3028*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3028*FLEN/8, x7, x2, x4) + +inst_1540: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xac07; + valaddr_reg:x6; val_offset:3030*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3030*FLEN/8, x7, x2, x4) + +inst_1541: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x007 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xac07; op2val:0x8001; + valaddr_reg:x6; val_offset:3032*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3032*FLEN/8, x7, x2, x4) + +inst_1542: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xaffc; + valaddr_reg:x6; val_offset:3034*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3034*FLEN/8, x7, x2, x4) + +inst_1543: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xaffc; op2val:0x8001; + valaddr_reg:x6; val_offset:3036*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3036*FLEN/8, x7, x2, x4) + +inst_1544: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xac03; + valaddr_reg:x6; val_offset:3038*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3038*FLEN/8, x7, x2, x4) + +inst_1545: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x003 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xac03; op2val:0x8001; + valaddr_reg:x6; val_offset:3040*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3040*FLEN/8, x7, x2, x4) + +inst_1546: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xaffe; + valaddr_reg:x6; val_offset:3042*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3042*FLEN/8, x7, x2, x4) + +inst_1547: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xaffe; op2val:0x8001; + valaddr_reg:x6; val_offset:3044*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3044*FLEN/8, x7, x2, x4) + +inst_1548: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8401; + valaddr_reg:x6; val_offset:3046*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3046*FLEN/8, x7, x2, x4) + +inst_1549: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8401; op2val:0x8001; + valaddr_reg:x6; val_offset:3048*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3048*FLEN/8, x7, x2, x4) + +inst_1550: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8400; + valaddr_reg:x6; val_offset:3050*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3050*FLEN/8, x7, x2, x4) + +inst_1551: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8001; + valaddr_reg:x6; val_offset:3052*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3052*FLEN/8, x7, x2, x4) + +inst_1552: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x87ff; + valaddr_reg:x6; val_offset:3054*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3054*FLEN/8, x7, x2, x4) + +inst_1553: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x87ff; op2val:0x8001; + valaddr_reg:x6; val_offset:3056*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3056*FLEN/8, x7, x2, x4) + +inst_1554: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8600; + valaddr_reg:x6; val_offset:3058*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3058*FLEN/8, x7, x2, x4) + +inst_1555: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8600; op2val:0x8001; + valaddr_reg:x6; val_offset:3060*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3060*FLEN/8, x7, x2, x4) + +inst_1556: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x85ff; + valaddr_reg:x6; val_offset:3062*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3062*FLEN/8, x7, x2, x4) + +inst_1557: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x85ff; op2val:0x8001; + valaddr_reg:x6; val_offset:3064*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3064*FLEN/8, x7, x2, x4) + +inst_1558: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8700; + valaddr_reg:x6; val_offset:3066*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3066*FLEN/8, x7, x2, x4) + +inst_1559: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x300 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8700; op2val:0x8001; + valaddr_reg:x6; val_offset:3068*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3068*FLEN/8, x7, x2, x4) + +inst_1560: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x84ff; + valaddr_reg:x6; val_offset:3070*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3070*FLEN/8, x7, x2, x4) + +inst_1561: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x84ff; op2val:0x8001; + valaddr_reg:x6; val_offset:3072*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3072*FLEN/8, x7, x2, x4) + +inst_1562: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8780; + valaddr_reg:x6; val_offset:3074*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3074*FLEN/8, x7, x2, x4) + +inst_1563: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x380 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8780; op2val:0x8001; + valaddr_reg:x6; val_offset:3076*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3076*FLEN/8, x7, x2, x4) + +inst_1564: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x847f; + valaddr_reg:x6; val_offset:3078*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3078*FLEN/8, x7, x2, x4) +RVTEST_SIGBASE(x2,signature_x2_14) + +inst_1565: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x07f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x847f; op2val:0x8001; + valaddr_reg:x6; val_offset:3080*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3080*FLEN/8, x7, x2, x4) + +inst_1566: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x87c0; + valaddr_reg:x6; val_offset:3082*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3082*FLEN/8, x7, x2, x4) + +inst_1567: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x87c0; op2val:0x8001; + valaddr_reg:x6; val_offset:3084*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3084*FLEN/8, x7, x2, x4) + +inst_1568: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x843f; + valaddr_reg:x6; val_offset:3086*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3086*FLEN/8, x7, x2, x4) + +inst_1569: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x843f; op2val:0x8001; + valaddr_reg:x6; val_offset:3088*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3088*FLEN/8, x7, x2, x4) + +inst_1570: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x87e0; + valaddr_reg:x6; val_offset:3090*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3090*FLEN/8, x7, x2, x4) + +inst_1571: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x87e0; op2val:0x8001; + valaddr_reg:x6; val_offset:3092*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3092*FLEN/8, x7, x2, x4) + +inst_1572: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x841f; + valaddr_reg:x6; val_offset:3094*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3094*FLEN/8, x7, x2, x4) + +inst_1573: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x01f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x841f; op2val:0x8001; + valaddr_reg:x6; val_offset:3096*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3096*FLEN/8, x7, x2, x4) + +inst_1574: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x87f0; + valaddr_reg:x6; val_offset:3098*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3098*FLEN/8, x7, x2, x4) + +inst_1575: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x87f0; op2val:0x8001; + valaddr_reg:x6; val_offset:3100*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3100*FLEN/8, x7, x2, x4) + +inst_1576: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x840f; + valaddr_reg:x6; val_offset:3102*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3102*FLEN/8, x7, x2, x4) + +inst_1577: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x00f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x840f; op2val:0x8001; + valaddr_reg:x6; val_offset:3104*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3104*FLEN/8, x7, x2, x4) + +inst_1578: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x87f8; + valaddr_reg:x6; val_offset:3106*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3106*FLEN/8, x7, x2, x4) + +inst_1579: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x87f8; op2val:0x8001; + valaddr_reg:x6; val_offset:3108*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3108*FLEN/8, x7, x2, x4) + +inst_1580: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8407; + valaddr_reg:x6; val_offset:3110*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3110*FLEN/8, x7, x2, x4) + +inst_1581: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8407; op2val:0x8001; + valaddr_reg:x6; val_offset:3112*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3112*FLEN/8, x7, x2, x4) + +inst_1582: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x87fc; + valaddr_reg:x6; val_offset:3114*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3114*FLEN/8, x7, x2, x4) + +inst_1583: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x87fc; op2val:0x8001; + valaddr_reg:x6; val_offset:3116*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3116*FLEN/8, x7, x2, x4) + +inst_1584: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8403; + valaddr_reg:x6; val_offset:3118*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3118*FLEN/8, x7, x2, x4) + +inst_1585: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8403; op2val:0x8001; + valaddr_reg:x6; val_offset:3120*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3120*FLEN/8, x7, x2, x4) + +inst_1586: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x87fe; + valaddr_reg:x6; val_offset:3122*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3122*FLEN/8, x7, x2, x4) + +inst_1587: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x87fe; op2val:0x8001; + valaddr_reg:x6; val_offset:3124*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3124*FLEN/8, x7, x2, x4) + +inst_1588: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8801; + valaddr_reg:x6; val_offset:3126*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3126*FLEN/8, x7, x2, x4) + +inst_1589: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8801; op2val:0x8001; + valaddr_reg:x6; val_offset:3128*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3128*FLEN/8, x7, x2, x4) + +inst_1590: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8800; + valaddr_reg:x6; val_offset:3130*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3130*FLEN/8, x7, x2, x4) + +inst_1591: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8800; op2val:0x8001; + valaddr_reg:x6; val_offset:3132*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3132*FLEN/8, x7, x2, x4) + +inst_1592: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8bff; + valaddr_reg:x6; val_offset:3134*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3134*FLEN/8, x7, x2, x4) + +inst_1593: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8bff; op2val:0x8001; + valaddr_reg:x6; val_offset:3136*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3136*FLEN/8, x7, x2, x4) + +inst_1594: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8a00; + valaddr_reg:x6; val_offset:3138*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3138*FLEN/8, x7, x2, x4) + +inst_1595: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8a00; op2val:0x8001; + valaddr_reg:x6; val_offset:3140*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3140*FLEN/8, x7, x2, x4) + +inst_1596: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x89ff; + valaddr_reg:x6; val_offset:3142*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3142*FLEN/8, x7, x2, x4) + +inst_1597: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x89ff; op2val:0x8001; + valaddr_reg:x6; val_offset:3144*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3144*FLEN/8, x7, x2, x4) + +inst_1598: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8b00; + valaddr_reg:x6; val_offset:3146*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3146*FLEN/8, x7, x2, x4) + +inst_1599: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x300 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8b00; op2val:0x8001; + valaddr_reg:x6; val_offset:3148*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3148*FLEN/8, x7, x2, x4) + +inst_1600: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x88ff; + valaddr_reg:x6; val_offset:3150*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3150*FLEN/8, x7, x2, x4) + +inst_1601: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x88ff; op2val:0x8001; + valaddr_reg:x6; val_offset:3152*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3152*FLEN/8, x7, x2, x4) + +inst_1602: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8b80; + valaddr_reg:x6; val_offset:3154*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3154*FLEN/8, x7, x2, x4) + +inst_1603: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x380 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8b80; op2val:0x8001; + valaddr_reg:x6; val_offset:3156*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3156*FLEN/8, x7, x2, x4) + +inst_1604: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x887f; + valaddr_reg:x6; val_offset:3158*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3158*FLEN/8, x7, x2, x4) + +inst_1605: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x07f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x887f; op2val:0x8001; + valaddr_reg:x6; val_offset:3160*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3160*FLEN/8, x7, x2, x4) + +inst_1606: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8bc0; + valaddr_reg:x6; val_offset:3162*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3162*FLEN/8, x7, x2, x4) + +inst_1607: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8bc0; op2val:0x8001; + valaddr_reg:x6; val_offset:3164*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3164*FLEN/8, x7, x2, x4) + +inst_1608: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x883f; + valaddr_reg:x6; val_offset:3166*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3166*FLEN/8, x7, x2, x4) + +inst_1609: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x883f; op2val:0x8001; + valaddr_reg:x6; val_offset:3168*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3168*FLEN/8, x7, x2, x4) + +inst_1610: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8be0; + valaddr_reg:x6; val_offset:3170*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3170*FLEN/8, x7, x2, x4) + +inst_1611: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8be0; op2val:0x8001; + valaddr_reg:x6; val_offset:3172*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3172*FLEN/8, x7, x2, x4) + +inst_1612: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x881f; + valaddr_reg:x6; val_offset:3174*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3174*FLEN/8, x7, x2, x4) + +inst_1613: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x01f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x881f; op2val:0x8001; + valaddr_reg:x6; val_offset:3176*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3176*FLEN/8, x7, x2, x4) + +inst_1614: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8bf0; + valaddr_reg:x6; val_offset:3178*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3178*FLEN/8, x7, x2, x4) + +inst_1615: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8bf0; op2val:0x8001; + valaddr_reg:x6; val_offset:3180*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3180*FLEN/8, x7, x2, x4) + +inst_1616: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x880f; + valaddr_reg:x6; val_offset:3182*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3182*FLEN/8, x7, x2, x4) + +inst_1617: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x00f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x880f; op2val:0x8001; + valaddr_reg:x6; val_offset:3184*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3184*FLEN/8, x7, x2, x4) + +inst_1618: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8bf8; + valaddr_reg:x6; val_offset:3186*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3186*FLEN/8, x7, x2, x4) + +inst_1619: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8bf8; op2val:0x8001; + valaddr_reg:x6; val_offset:3188*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3188*FLEN/8, x7, x2, x4) + +inst_1620: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8807; + valaddr_reg:x6; val_offset:3190*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3190*FLEN/8, x7, x2, x4) + +inst_1621: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8807; op2val:0x8001; + valaddr_reg:x6; val_offset:3192*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3192*FLEN/8, x7, x2, x4) + +inst_1622: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8bfc; + valaddr_reg:x6; val_offset:3194*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3194*FLEN/8, x7, x2, x4) + +inst_1623: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8bfc; op2val:0x8001; + valaddr_reg:x6; val_offset:3196*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3196*FLEN/8, x7, x2, x4) + +inst_1624: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8803; + valaddr_reg:x6; val_offset:3198*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3198*FLEN/8, x7, x2, x4) + +inst_1625: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8803; op2val:0x8001; + valaddr_reg:x6; val_offset:3200*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3200*FLEN/8, x7, x2, x4) + +inst_1626: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8bfe; + valaddr_reg:x6; val_offset:3202*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3202*FLEN/8, x7, x2, x4) + +inst_1627: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8bfe; op2val:0x8001; + valaddr_reg:x6; val_offset:3204*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3204*FLEN/8, x7, x2, x4) + +inst_1628: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8c01; + valaddr_reg:x6; val_offset:3206*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3206*FLEN/8, x7, x2, x4) + +inst_1629: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8c01; op2val:0x8001; + valaddr_reg:x6; val_offset:3208*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3208*FLEN/8, x7, x2, x4) + +inst_1630: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8c00; + valaddr_reg:x6; val_offset:3210*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3210*FLEN/8, x7, x2, x4) + +inst_1631: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8c00; op2val:0x8001; + valaddr_reg:x6; val_offset:3212*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3212*FLEN/8, x7, x2, x4) + +inst_1632: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8fff; + valaddr_reg:x6; val_offset:3214*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3214*FLEN/8, x7, x2, x4) + +inst_1633: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8fff; op2val:0x8001; + valaddr_reg:x6; val_offset:3216*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3216*FLEN/8, x7, x2, x4) + +inst_1634: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8e00; + valaddr_reg:x6; val_offset:3218*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3218*FLEN/8, x7, x2, x4) + +inst_1635: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8e00; op2val:0x8001; + valaddr_reg:x6; val_offset:3220*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3220*FLEN/8, x7, x2, x4) + +inst_1636: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8dff; + valaddr_reg:x6; val_offset:3222*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3222*FLEN/8, x7, x2, x4) + +inst_1637: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8dff; op2val:0x8001; + valaddr_reg:x6; val_offset:3224*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3224*FLEN/8, x7, x2, x4) + +inst_1638: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8f00; + valaddr_reg:x6; val_offset:3226*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3226*FLEN/8, x7, x2, x4) + +inst_1639: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x300 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8f00; op2val:0x8001; + valaddr_reg:x6; val_offset:3228*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3228*FLEN/8, x7, x2, x4) + +inst_1640: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8cff; + valaddr_reg:x6; val_offset:3230*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3230*FLEN/8, x7, x2, x4) + +inst_1641: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8cff; op2val:0x8001; + valaddr_reg:x6; val_offset:3232*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3232*FLEN/8, x7, x2, x4) + +inst_1642: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8f80; + valaddr_reg:x6; val_offset:3234*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3234*FLEN/8, x7, x2, x4) + +inst_1643: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x380 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8f80; op2val:0x8001; + valaddr_reg:x6; val_offset:3236*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3236*FLEN/8, x7, x2, x4) + +inst_1644: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8c7f; + valaddr_reg:x6; val_offset:3238*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3238*FLEN/8, x7, x2, x4) + +inst_1645: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x07f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8c7f; op2val:0x8001; + valaddr_reg:x6; val_offset:3240*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3240*FLEN/8, x7, x2, x4) + +inst_1646: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8fc0; + valaddr_reg:x6; val_offset:3242*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3242*FLEN/8, x7, x2, x4) + +inst_1647: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8fc0; op2val:0x8001; + valaddr_reg:x6; val_offset:3244*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3244*FLEN/8, x7, x2, x4) + +inst_1648: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8c3f; + valaddr_reg:x6; val_offset:3246*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3246*FLEN/8, x7, x2, x4) + +inst_1649: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8c3f; op2val:0x8001; + valaddr_reg:x6; val_offset:3248*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3248*FLEN/8, x7, x2, x4) + +inst_1650: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8fe0; + valaddr_reg:x6; val_offset:3250*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3250*FLEN/8, x7, x2, x4) + +inst_1651: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8fe0; op2val:0x8001; + valaddr_reg:x6; val_offset:3252*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3252*FLEN/8, x7, x2, x4) + +inst_1652: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8c1f; + valaddr_reg:x6; val_offset:3254*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3254*FLEN/8, x7, x2, x4) + +inst_1653: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x01f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8c1f; op2val:0x8001; + valaddr_reg:x6; val_offset:3256*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3256*FLEN/8, x7, x2, x4) + +inst_1654: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8ff0; + valaddr_reg:x6; val_offset:3258*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3258*FLEN/8, x7, x2, x4) + +inst_1655: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8ff0; op2val:0x8001; + valaddr_reg:x6; val_offset:3260*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3260*FLEN/8, x7, x2, x4) + +inst_1656: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8c0f; + valaddr_reg:x6; val_offset:3262*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3262*FLEN/8, x7, x2, x4) + +inst_1657: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x00f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8c0f; op2val:0x8001; + valaddr_reg:x6; val_offset:3264*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3264*FLEN/8, x7, x2, x4) + +inst_1658: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8ff8; + valaddr_reg:x6; val_offset:3266*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3266*FLEN/8, x7, x2, x4) + +inst_1659: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8ff8; op2val:0x8001; + valaddr_reg:x6; val_offset:3268*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3268*FLEN/8, x7, x2, x4) + +inst_1660: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8c07; + valaddr_reg:x6; val_offset:3270*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3270*FLEN/8, x7, x2, x4) + +inst_1661: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8c07; op2val:0x8001; + valaddr_reg:x6; val_offset:3272*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3272*FLEN/8, x7, x2, x4) + +inst_1662: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8ffc; + valaddr_reg:x6; val_offset:3274*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3274*FLEN/8, x7, x2, x4) + +inst_1663: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8ffc; op2val:0x8001; + valaddr_reg:x6; val_offset:3276*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3276*FLEN/8, x7, x2, x4) + +inst_1664: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8c03; + valaddr_reg:x6; val_offset:3278*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3278*FLEN/8, x7, x2, x4) + +inst_1665: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8c03; op2val:0x8001; + valaddr_reg:x6; val_offset:3280*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3280*FLEN/8, x7, x2, x4) + +inst_1666: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8ffe; + valaddr_reg:x6; val_offset:3282*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3282*FLEN/8, x7, x2, x4) + +inst_1667: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8ffe; op2val:0x8001; + valaddr_reg:x6; val_offset:3284*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3284*FLEN/8, x7, x2, x4) + +inst_1668: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x3ff; + valaddr_reg:x6; val_offset:3286*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3286*FLEN/8, x7, x2, x4) + +inst_1669: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x1ff; + valaddr_reg:x6; val_offset:3288*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3288*FLEN/8, x7, x2, x4) + +inst_1670: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1ff; op2val:0x3ff; + valaddr_reg:x6; val_offset:3290*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3290*FLEN/8, x7, x2, x4) + +inst_1671: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x200; + valaddr_reg:x6; val_offset:3292*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3292*FLEN/8, x7, x2, x4) + +inst_1672: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x200; op2val:0x3ff; + valaddr_reg:x6; val_offset:3294*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3294*FLEN/8, x7, x2, x4) + +inst_1673: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xff; + valaddr_reg:x6; val_offset:3296*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3296*FLEN/8, x7, x2, x4) + +inst_1674: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xff; op2val:0x3ff; + valaddr_reg:x6; val_offset:3298*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3298*FLEN/8, x7, x2, x4) + +inst_1675: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x300; + valaddr_reg:x6; val_offset:3300*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3300*FLEN/8, x7, x2, x4) + +inst_1676: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x300 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x300; op2val:0x3ff; + valaddr_reg:x6; val_offset:3302*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3302*FLEN/8, x7, x2, x4) + +inst_1677: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7f; + valaddr_reg:x6; val_offset:3304*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3304*FLEN/8, x7, x2, x4) + +inst_1678: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x07f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7f; op2val:0x3ff; + valaddr_reg:x6; val_offset:3306*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3306*FLEN/8, x7, x2, x4) + +inst_1679: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x380; + valaddr_reg:x6; val_offset:3308*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3308*FLEN/8, x7, x2, x4) + +inst_1680: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x380 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x380; op2val:0x3ff; + valaddr_reg:x6; val_offset:3310*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3310*FLEN/8, x7, x2, x4) + +inst_1681: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x3f; + valaddr_reg:x6; val_offset:3312*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3312*FLEN/8, x7, x2, x4) + +inst_1682: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3f; op2val:0x3ff; + valaddr_reg:x6; val_offset:3314*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3314*FLEN/8, x7, x2, x4) + +inst_1683: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x3c0; + valaddr_reg:x6; val_offset:3316*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3316*FLEN/8, x7, x2, x4) + +inst_1684: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c0; op2val:0x3ff; + valaddr_reg:x6; val_offset:3318*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3318*FLEN/8, x7, x2, x4) + +inst_1685: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x1f; + valaddr_reg:x6; val_offset:3320*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3320*FLEN/8, x7, x2, x4) + +inst_1686: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x01f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1f; op2val:0x3ff; + valaddr_reg:x6; val_offset:3322*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3322*FLEN/8, x7, x2, x4) + +inst_1687: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x3e0; + valaddr_reg:x6; val_offset:3324*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3324*FLEN/8, x7, x2, x4) + +inst_1688: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3e0; op2val:0x3ff; + valaddr_reg:x6; val_offset:3326*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3326*FLEN/8, x7, x2, x4) + +inst_1689: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xf; + valaddr_reg:x6; val_offset:3328*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3328*FLEN/8, x7, x2, x4) + +inst_1690: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf; op2val:0x3ff; + valaddr_reg:x6; val_offset:3330*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3330*FLEN/8, x7, x2, x4) + +inst_1691: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x3f0; + valaddr_reg:x6; val_offset:3332*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3332*FLEN/8, x7, x2, x4) + +inst_1692: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3f0; op2val:0x3ff; + valaddr_reg:x6; val_offset:3334*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3334*FLEN/8, x7, x2, x4) +RVTEST_SIGBASE(x2,signature_x2_15) + +inst_1693: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7; + valaddr_reg:x6; val_offset:3336*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3336*FLEN/8, x7, x2, x4) + +inst_1694: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7; op2val:0x3ff; + valaddr_reg:x6; val_offset:3338*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3338*FLEN/8, x7, x2, x4) + +inst_1695: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x3f8; + valaddr_reg:x6; val_offset:3340*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3340*FLEN/8, x7, x2, x4) + +inst_1696: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3f8; op2val:0x3ff; + valaddr_reg:x6; val_offset:3342*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3342*FLEN/8, x7, x2, x4) + +inst_1697: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x3; + valaddr_reg:x6; val_offset:3344*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3344*FLEN/8, x7, x2, x4) + +inst_1698: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x003 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3; op2val:0x3ff; + valaddr_reg:x6; val_offset:3346*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3346*FLEN/8, x7, x2, x4) + +inst_1699: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x3fc; + valaddr_reg:x6; val_offset:3348*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3348*FLEN/8, x7, x2, x4) + +inst_1700: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fc; op2val:0x3ff; + valaddr_reg:x6; val_offset:3350*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3350*FLEN/8, x7, x2, x4) + +inst_1701: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x3fe; + valaddr_reg:x6; val_offset:3352*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3352*FLEN/8, x7, x2, x4) + +inst_1702: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fe; op2val:0x3ff; + valaddr_reg:x6; val_offset:3354*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3354*FLEN/8, x7, x2, x4) + +inst_1703: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1b6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x1b6; + valaddr_reg:x6; val_offset:3356*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3356*FLEN/8, x7, x2, x4) + +inst_1704: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1b6; op2val:0x3ff; + valaddr_reg:x6; val_offset:3358*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3358*FLEN/8, x7, x2, x4) + +inst_1705: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x36d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x36d; + valaddr_reg:x6; val_offset:3360*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3360*FLEN/8, x7, x2, x4) + +inst_1706: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x36d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x36d; op2val:0x3ff; + valaddr_reg:x6; val_offset:3362*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3362*FLEN/8, x7, x2, x4) + +inst_1707: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0cc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xcc; + valaddr_reg:x6; val_offset:3364*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3364*FLEN/8, x7, x2, x4) + +inst_1708: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0cc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xcc; op2val:0x3ff; + valaddr_reg:x6; val_offset:3366*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3366*FLEN/8, x7, x2, x4) + +inst_1709: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x333 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x333; + valaddr_reg:x6; val_offset:3368*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3368*FLEN/8, x7, x2, x4) + +inst_1710: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x333 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x333; op2val:0x3ff; + valaddr_reg:x6; val_offset:3370*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3370*FLEN/8, x7, x2, x4) + +inst_1711: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1dd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x1dd; + valaddr_reg:x6; val_offset:3372*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3372*FLEN/8, x7, x2, x4) + +inst_1712: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1dd; op2val:0x3ff; + valaddr_reg:x6; val_offset:3374*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3374*FLEN/8, x7, x2, x4) + +inst_1713: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x222 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x222; + valaddr_reg:x6; val_offset:3376*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3376*FLEN/8, x7, x2, x4) + +inst_1714: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x222 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x222; op2val:0x3ff; + valaddr_reg:x6; val_offset:3378*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3378*FLEN/8, x7, x2, x4) + +inst_1715: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x124 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x124; + valaddr_reg:x6; val_offset:3380*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3380*FLEN/8, x7, x2, x4) + +inst_1716: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x124 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x124; op2val:0x3ff; + valaddr_reg:x6; val_offset:3382*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3382*FLEN/8, x7, x2, x4) + +inst_1717: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2db and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x2db; + valaddr_reg:x6; val_offset:3384*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3384*FLEN/8, x7, x2, x4) + +inst_1718: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2db; op2val:0x3ff; + valaddr_reg:x6; val_offset:3386*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3386*FLEN/8, x7, x2, x4) + +inst_1719: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x199 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x199; + valaddr_reg:x6; val_offset:3388*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3388*FLEN/8, x7, x2, x4) + +inst_1720: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x199 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x199; op2val:0x3ff; + valaddr_reg:x6; val_offset:3390*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3390*FLEN/8, x7, x2, x4) + +inst_1721: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x266 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x266; + valaddr_reg:x6; val_offset:3392*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3392*FLEN/8, x7, x2, x4) + +inst_1722: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x266 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x266; op2val:0x3ff; + valaddr_reg:x6; val_offset:3394*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3394*FLEN/8, x7, x2, x4) + +inst_1723: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xbfff; + valaddr_reg:x6; val_offset:3396*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3396*FLEN/8, x7, x2, x4) + +inst_1724: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbfff; op2val:0x3ff; + valaddr_reg:x6; val_offset:3398*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3398*FLEN/8, x7, x2, x4) + +inst_1725: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xbc00; + valaddr_reg:x6; val_offset:3400*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3400*FLEN/8, x7, x2, x4) + +inst_1726: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x3ff; + valaddr_reg:x6; val_offset:3402*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3402*FLEN/8, x7, x2, x4) + +inst_1727: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xbdff; + valaddr_reg:x6; val_offset:3404*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3404*FLEN/8, x7, x2, x4) + +inst_1728: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbdff; op2val:0x3ff; + valaddr_reg:x6; val_offset:3406*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3406*FLEN/8, x7, x2, x4) + +inst_1729: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xbe00; + valaddr_reg:x6; val_offset:3408*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3408*FLEN/8, x7, x2, x4) + +inst_1730: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbe00; op2val:0x3ff; + valaddr_reg:x6; val_offset:3410*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3410*FLEN/8, x7, x2, x4) + +inst_1731: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xbcff; + valaddr_reg:x6; val_offset:3412*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3412*FLEN/8, x7, x2, x4) + +inst_1732: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbcff; op2val:0x3ff; + valaddr_reg:x6; val_offset:3414*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3414*FLEN/8, x7, x2, x4) + +inst_1733: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xbf00; + valaddr_reg:x6; val_offset:3416*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3416*FLEN/8, x7, x2, x4) + +inst_1734: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x300 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbf00; op2val:0x3ff; + valaddr_reg:x6; val_offset:3418*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3418*FLEN/8, x7, x2, x4) + +inst_1735: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xbc7f; + valaddr_reg:x6; val_offset:3420*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3420*FLEN/8, x7, x2, x4) + +inst_1736: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x07f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc7f; op2val:0x3ff; + valaddr_reg:x6; val_offset:3422*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3422*FLEN/8, x7, x2, x4) + +inst_1737: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xbf80; + valaddr_reg:x6; val_offset:3424*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3424*FLEN/8, x7, x2, x4) + +inst_1738: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x380 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbf80; op2val:0x3ff; + valaddr_reg:x6; val_offset:3426*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3426*FLEN/8, x7, x2, x4) + +inst_1739: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xbc3f; + valaddr_reg:x6; val_offset:3428*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3428*FLEN/8, x7, x2, x4) + +inst_1740: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x03f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc3f; op2val:0x3ff; + valaddr_reg:x6; val_offset:3430*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3430*FLEN/8, x7, x2, x4) + +inst_1741: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xbfc0; + valaddr_reg:x6; val_offset:3432*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3432*FLEN/8, x7, x2, x4) + +inst_1742: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbfc0; op2val:0x3ff; + valaddr_reg:x6; val_offset:3434*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3434*FLEN/8, x7, x2, x4) + +inst_1743: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xbc1f; + valaddr_reg:x6; val_offset:3436*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3436*FLEN/8, x7, x2, x4) + +inst_1744: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x01f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc1f; op2val:0x3ff; + valaddr_reg:x6; val_offset:3438*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3438*FLEN/8, x7, x2, x4) + +inst_1745: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xbfe0; + valaddr_reg:x6; val_offset:3440*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3440*FLEN/8, x7, x2, x4) + +inst_1746: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbfe0; op2val:0x3ff; + valaddr_reg:x6; val_offset:3442*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3442*FLEN/8, x7, x2, x4) + +inst_1747: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xbc0f; + valaddr_reg:x6; val_offset:3444*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3444*FLEN/8, x7, x2, x4) + +inst_1748: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x00f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc0f; op2val:0x3ff; + valaddr_reg:x6; val_offset:3446*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3446*FLEN/8, x7, x2, x4) + +inst_1749: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xbff0; + valaddr_reg:x6; val_offset:3448*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3448*FLEN/8, x7, x2, x4) + +inst_1750: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbff0; op2val:0x3ff; + valaddr_reg:x6; val_offset:3450*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3450*FLEN/8, x7, x2, x4) + +inst_1751: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xbc07; + valaddr_reg:x6; val_offset:3452*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3452*FLEN/8, x7, x2, x4) + +inst_1752: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x007 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc07; op2val:0x3ff; + valaddr_reg:x6; val_offset:3454*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3454*FLEN/8, x7, x2, x4) + +inst_1753: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xbff8; + valaddr_reg:x6; val_offset:3456*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3456*FLEN/8, x7, x2, x4) + +inst_1754: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbff8; op2val:0x3ff; + valaddr_reg:x6; val_offset:3458*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3458*FLEN/8, x7, x2, x4) + +inst_1755: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xbc03; + valaddr_reg:x6; val_offset:3460*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3460*FLEN/8, x7, x2, x4) + +inst_1756: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x003 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc03; op2val:0x3ff; + valaddr_reg:x6; val_offset:3462*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3462*FLEN/8, x7, x2, x4) + +inst_1757: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xbffc; + valaddr_reg:x6; val_offset:3464*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3464*FLEN/8, x7, x2, x4) + +inst_1758: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbffc; op2val:0x3ff; + valaddr_reg:x6; val_offset:3466*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3466*FLEN/8, x7, x2, x4) + +inst_1759: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xbc01; + valaddr_reg:x6; val_offset:3468*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3468*FLEN/8, x7, x2, x4) + +inst_1760: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc01; op2val:0x3ff; + valaddr_reg:x6; val_offset:3470*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3470*FLEN/8, x7, x2, x4) + +inst_1761: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xbffe; + valaddr_reg:x6; val_offset:3472*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3472*FLEN/8, x7, x2, x4) + +inst_1762: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbffe; op2val:0x3ff; + valaddr_reg:x6; val_offset:3474*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3474*FLEN/8, x7, x2, x4) + +inst_1763: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7ff; + valaddr_reg:x6; val_offset:3476*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3476*FLEN/8, x7, x2, x4) + +inst_1764: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ff; op2val:0x3ff; + valaddr_reg:x6; val_offset:3478*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3478*FLEN/8, x7, x2, x4) + +inst_1765: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x400; + valaddr_reg:x6; val_offset:3480*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3480*FLEN/8, x7, x2, x4) + +inst_1766: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x3ff; + valaddr_reg:x6; val_offset:3482*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3482*FLEN/8, x7, x2, x4) + +inst_1767: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x5ff; + valaddr_reg:x6; val_offset:3484*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3484*FLEN/8, x7, x2, x4) + +inst_1768: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5ff; op2val:0x3ff; + valaddr_reg:x6; val_offset:3486*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3486*FLEN/8, x7, x2, x4) + +inst_1769: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x600; + valaddr_reg:x6; val_offset:3488*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3488*FLEN/8, x7, x2, x4) + +inst_1770: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x600; op2val:0x3ff; + valaddr_reg:x6; val_offset:3490*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3490*FLEN/8, x7, x2, x4) + +inst_1771: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x4ff; + valaddr_reg:x6; val_offset:3492*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3492*FLEN/8, x7, x2, x4) + +inst_1772: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4ff; op2val:0x3ff; + valaddr_reg:x6; val_offset:3494*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3494*FLEN/8, x7, x2, x4) + +inst_1773: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x700; + valaddr_reg:x6; val_offset:3496*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3496*FLEN/8, x7, x2, x4) + +inst_1774: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x300 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x700; op2val:0x3ff; + valaddr_reg:x6; val_offset:3498*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3498*FLEN/8, x7, x2, x4) + +inst_1775: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x47f; + valaddr_reg:x6; val_offset:3500*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3500*FLEN/8, x7, x2, x4) + +inst_1776: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x07f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x47f; op2val:0x3ff; + valaddr_reg:x6; val_offset:3502*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3502*FLEN/8, x7, x2, x4) + +inst_1777: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x780; + valaddr_reg:x6; val_offset:3504*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3504*FLEN/8, x7, x2, x4) + +inst_1778: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x380 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x780; op2val:0x3ff; + valaddr_reg:x6; val_offset:3506*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3506*FLEN/8, x7, x2, x4) + +inst_1779: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x43f; + valaddr_reg:x6; val_offset:3508*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3508*FLEN/8, x7, x2, x4) + +inst_1780: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x43f; op2val:0x3ff; + valaddr_reg:x6; val_offset:3510*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3510*FLEN/8, x7, x2, x4) + +inst_1781: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7c0; + valaddr_reg:x6; val_offset:3512*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3512*FLEN/8, x7, x2, x4) + +inst_1782: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c0; op2val:0x3ff; + valaddr_reg:x6; val_offset:3514*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3514*FLEN/8, x7, x2, x4) + +inst_1783: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x41f; + valaddr_reg:x6; val_offset:3516*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3516*FLEN/8, x7, x2, x4) + +inst_1784: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x01f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x41f; op2val:0x3ff; + valaddr_reg:x6; val_offset:3518*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3518*FLEN/8, x7, x2, x4) + +inst_1785: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7e0; + valaddr_reg:x6; val_offset:3520*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3520*FLEN/8, x7, x2, x4) + +inst_1786: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e0; op2val:0x3ff; + valaddr_reg:x6; val_offset:3522*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3522*FLEN/8, x7, x2, x4) + +inst_1787: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x40f; + valaddr_reg:x6; val_offset:3524*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3524*FLEN/8, x7, x2, x4) + +inst_1788: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x00f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x40f; op2val:0x3ff; + valaddr_reg:x6; val_offset:3526*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3526*FLEN/8, x7, x2, x4) + +inst_1789: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7f0; + valaddr_reg:x6; val_offset:3528*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3528*FLEN/8, x7, x2, x4) + +inst_1790: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7f0; op2val:0x3ff; + valaddr_reg:x6; val_offset:3530*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3530*FLEN/8, x7, x2, x4) + +inst_1791: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x407; + valaddr_reg:x6; val_offset:3532*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3532*FLEN/8, x7, x2, x4) + +inst_1792: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x407; op2val:0x3ff; + valaddr_reg:x6; val_offset:3534*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3534*FLEN/8, x7, x2, x4) + +inst_1793: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7f8; + valaddr_reg:x6; val_offset:3536*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3536*FLEN/8, x7, x2, x4) + +inst_1794: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7f8; op2val:0x3ff; + valaddr_reg:x6; val_offset:3538*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3538*FLEN/8, x7, x2, x4) + +inst_1795: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x403; + valaddr_reg:x6; val_offset:3540*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3540*FLEN/8, x7, x2, x4) + +inst_1796: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x003 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x403; op2val:0x3ff; + valaddr_reg:x6; val_offset:3542*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3542*FLEN/8, x7, x2, x4) + +inst_1797: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7fc; + valaddr_reg:x6; val_offset:3544*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3544*FLEN/8, x7, x2, x4) + +inst_1798: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7fc; op2val:0x3ff; + valaddr_reg:x6; val_offset:3546*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3546*FLEN/8, x7, x2, x4) + +inst_1799: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x401; + valaddr_reg:x6; val_offset:3548*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3548*FLEN/8, x7, x2, x4) + +inst_1800: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x3ff; + valaddr_reg:x6; val_offset:3550*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3550*FLEN/8, x7, x2, x4) + +inst_1801: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7fe; + valaddr_reg:x6; val_offset:3552*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3552*FLEN/8, x7, x2, x4) + +inst_1802: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7fe; op2val:0x3ff; + valaddr_reg:x6; val_offset:3554*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3554*FLEN/8, x7, x2, x4) + +inst_1803: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xbff; + valaddr_reg:x6; val_offset:3556*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3556*FLEN/8, x7, x2, x4) + +inst_1804: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbff; op2val:0x3ff; + valaddr_reg:x6; val_offset:3558*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3558*FLEN/8, x7, x2, x4) + +inst_1805: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x02 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x800; + valaddr_reg:x6; val_offset:3560*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3560*FLEN/8, x7, x2, x4) + +inst_1806: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x800; op2val:0x3ff; + valaddr_reg:x6; val_offset:3562*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3562*FLEN/8, x7, x2, x4) + +inst_1807: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x02 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x9ff; + valaddr_reg:x6; val_offset:3564*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3564*FLEN/8, x7, x2, x4) + +inst_1808: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x9ff; op2val:0x3ff; + valaddr_reg:x6; val_offset:3566*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3566*FLEN/8, x7, x2, x4) + +inst_1809: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x02 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xa00; + valaddr_reg:x6; val_offset:3568*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3568*FLEN/8, x7, x2, x4) + +inst_1810: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xa00; op2val:0x3ff; + valaddr_reg:x6; val_offset:3570*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3570*FLEN/8, x7, x2, x4) + +inst_1811: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x02 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x8ff; + valaddr_reg:x6; val_offset:3572*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3572*FLEN/8, x7, x2, x4) + +inst_1812: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8ff; op2val:0x3ff; + valaddr_reg:x6; val_offset:3574*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3574*FLEN/8, x7, x2, x4) + +inst_1813: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x02 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xb00; + valaddr_reg:x6; val_offset:3576*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3576*FLEN/8, x7, x2, x4) + +inst_1814: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x300 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xb00; op2val:0x3ff; + valaddr_reg:x6; val_offset:3578*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3578*FLEN/8, x7, x2, x4) + +inst_1815: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x02 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x87f; + valaddr_reg:x6; val_offset:3580*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3580*FLEN/8, x7, x2, x4) + +inst_1816: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x07f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x87f; op2val:0x3ff; + valaddr_reg:x6; val_offset:3582*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3582*FLEN/8, x7, x2, x4) + +inst_1817: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x02 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xb80; + valaddr_reg:x6; val_offset:3584*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3584*FLEN/8, x7, x2, x4) + +inst_1818: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x380 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xb80; op2val:0x3ff; + valaddr_reg:x6; val_offset:3586*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3586*FLEN/8, x7, x2, x4) + +inst_1819: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x02 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x83f; + valaddr_reg:x6; val_offset:3588*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3588*FLEN/8, x7, x2, x4) + +inst_1820: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83f; op2val:0x3ff; + valaddr_reg:x6; val_offset:3590*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3590*FLEN/8, x7, x2, x4) +RVTEST_SIGBASE(x2,signature_x2_16) + +inst_1821: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xbc0; + valaddr_reg:x6; val_offset:3592*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3592*FLEN/8, x7, x2, x4) + +inst_1822: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc0; op2val:0x3ff; + valaddr_reg:x6; val_offset:3594*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3594*FLEN/8, x7, x2, x4) + +inst_1823: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x02 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x81f; + valaddr_reg:x6; val_offset:3596*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3596*FLEN/8, x7, x2, x4) + +inst_1824: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x01f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x81f; op2val:0x3ff; + valaddr_reg:x6; val_offset:3598*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3598*FLEN/8, x7, x2, x4) + +inst_1825: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xbe0; + valaddr_reg:x6; val_offset:3600*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3600*FLEN/8, x7, x2, x4) + +inst_1826: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbe0; op2val:0x3ff; + valaddr_reg:x6; val_offset:3602*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3602*FLEN/8, x7, x2, x4) + +inst_1827: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x02 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x80f; + valaddr_reg:x6; val_offset:3604*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3604*FLEN/8, x7, x2, x4) + +inst_1828: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x00f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x80f; op2val:0x3ff; + valaddr_reg:x6; val_offset:3606*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3606*FLEN/8, x7, x2, x4) + +inst_1829: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xbf0; + valaddr_reg:x6; val_offset:3608*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3608*FLEN/8, x7, x2, x4) + +inst_1830: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbf0; op2val:0x3ff; + valaddr_reg:x6; val_offset:3610*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3610*FLEN/8, x7, x2, x4) + +inst_1831: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x02 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x807; + valaddr_reg:x6; val_offset:3612*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3612*FLEN/8, x7, x2, x4) + +inst_1832: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x807; op2val:0x3ff; + valaddr_reg:x6; val_offset:3614*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3614*FLEN/8, x7, x2, x4) + +inst_1833: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xbf8; + valaddr_reg:x6; val_offset:3616*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3616*FLEN/8, x7, x2, x4) + +inst_1834: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbf8; op2val:0x3ff; + valaddr_reg:x6; val_offset:3618*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3618*FLEN/8, x7, x2, x4) + +inst_1835: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x02 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x803; + valaddr_reg:x6; val_offset:3620*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3620*FLEN/8, x7, x2, x4) + +inst_1836: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x003 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x803; op2val:0x3ff; + valaddr_reg:x6; val_offset:3622*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3622*FLEN/8, x7, x2, x4) + +inst_1837: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xbfc; + valaddr_reg:x6; val_offset:3624*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3624*FLEN/8, x7, x2, x4) + +inst_1838: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbfc; op2val:0x3ff; + valaddr_reg:x6; val_offset:3626*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3626*FLEN/8, x7, x2, x4) + +inst_1839: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x02 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x801; + valaddr_reg:x6; val_offset:3628*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3628*FLEN/8, x7, x2, x4) + +inst_1840: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x801; op2val:0x3ff; + valaddr_reg:x6; val_offset:3630*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3630*FLEN/8, x7, x2, x4) + +inst_1841: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xbfe; + valaddr_reg:x6; val_offset:3632*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3632*FLEN/8, x7, x2, x4) + +inst_1842: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbfe; op2val:0x3ff; + valaddr_reg:x6; val_offset:3634*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3634*FLEN/8, x7, x2, x4) + +inst_1843: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xfff; + valaddr_reg:x6; val_offset:3636*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3636*FLEN/8, x7, x2, x4) + +inst_1844: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfff; op2val:0x3ff; + valaddr_reg:x6; val_offset:3638*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3638*FLEN/8, x7, x2, x4) + +inst_1845: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x03 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xc00; + valaddr_reg:x6; val_offset:3640*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3640*FLEN/8, x7, x2, x4) + +inst_1846: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc00; op2val:0x3ff; + valaddr_reg:x6; val_offset:3642*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3642*FLEN/8, x7, x2, x4) + +inst_1847: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x03 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xdff; + valaddr_reg:x6; val_offset:3644*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3644*FLEN/8, x7, x2, x4) + +inst_1848: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xdff; op2val:0x3ff; + valaddr_reg:x6; val_offset:3646*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3646*FLEN/8, x7, x2, x4) + +inst_1849: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x03 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xe00; + valaddr_reg:x6; val_offset:3648*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3648*FLEN/8, x7, x2, x4) + +inst_1850: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xe00; op2val:0x3ff; + valaddr_reg:x6; val_offset:3650*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3650*FLEN/8, x7, x2, x4) + +inst_1851: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x03 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xcff; + valaddr_reg:x6; val_offset:3652*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3652*FLEN/8, x7, x2, x4) + +inst_1852: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xcff; op2val:0x3ff; + valaddr_reg:x6; val_offset:3654*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3654*FLEN/8, x7, x2, x4) + +inst_1853: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x03 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xf00; + valaddr_reg:x6; val_offset:3656*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3656*FLEN/8, x7, x2, x4) + +inst_1854: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x300 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf00; op2val:0x3ff; + valaddr_reg:x6; val_offset:3658*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3658*FLEN/8, x7, x2, x4) + +inst_1855: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x03 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xc7f; + valaddr_reg:x6; val_offset:3660*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3660*FLEN/8, x7, x2, x4) + +inst_1856: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x07f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc7f; op2val:0x3ff; + valaddr_reg:x6; val_offset:3662*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3662*FLEN/8, x7, x2, x4) + +inst_1857: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x03 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xf80; + valaddr_reg:x6; val_offset:3664*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3664*FLEN/8, x7, x2, x4) + +inst_1858: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x380 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf80; op2val:0x3ff; + valaddr_reg:x6; val_offset:3666*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3666*FLEN/8, x7, x2, x4) + +inst_1859: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x03 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xc3f; + valaddr_reg:x6; val_offset:3668*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3668*FLEN/8, x7, x2, x4) + +inst_1860: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc3f; op2val:0x3ff; + valaddr_reg:x6; val_offset:3670*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3670*FLEN/8, x7, x2, x4) + +inst_1861: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xfc0; + valaddr_reg:x6; val_offset:3672*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3672*FLEN/8, x7, x2, x4) + +inst_1862: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc0; op2val:0x3ff; + valaddr_reg:x6; val_offset:3674*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3674*FLEN/8, x7, x2, x4) + +inst_1863: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x03 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xc1f; + valaddr_reg:x6; val_offset:3676*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3676*FLEN/8, x7, x2, x4) + +inst_1864: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x01f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc1f; op2val:0x3ff; + valaddr_reg:x6; val_offset:3678*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3678*FLEN/8, x7, x2, x4) + +inst_1865: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xfe0; + valaddr_reg:x6; val_offset:3680*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3680*FLEN/8, x7, x2, x4) + +inst_1866: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe0; op2val:0x3ff; + valaddr_reg:x6; val_offset:3682*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3682*FLEN/8, x7, x2, x4) + +inst_1867: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x03 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xc0f; + valaddr_reg:x6; val_offset:3684*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3684*FLEN/8, x7, x2, x4) + +inst_1868: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x00f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc0f; op2val:0x3ff; + valaddr_reg:x6; val_offset:3686*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3686*FLEN/8, x7, x2, x4) + +inst_1869: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xff0; + valaddr_reg:x6; val_offset:3688*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3688*FLEN/8, x7, x2, x4) + +inst_1870: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xff0; op2val:0x3ff; + valaddr_reg:x6; val_offset:3690*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3690*FLEN/8, x7, x2, x4) + +inst_1871: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x03 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xc07; + valaddr_reg:x6; val_offset:3692*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3692*FLEN/8, x7, x2, x4) + +inst_1872: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc07; op2val:0x3ff; + valaddr_reg:x6; val_offset:3694*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3694*FLEN/8, x7, x2, x4) + +inst_1873: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xff8; + valaddr_reg:x6; val_offset:3696*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3696*FLEN/8, x7, x2, x4) + +inst_1874: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xff8; op2val:0x3ff; + valaddr_reg:x6; val_offset:3698*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3698*FLEN/8, x7, x2, x4) + +inst_1875: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x03 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xc03; + valaddr_reg:x6; val_offset:3700*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3700*FLEN/8, x7, x2, x4) + +inst_1876: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x003 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc03; op2val:0x3ff; + valaddr_reg:x6; val_offset:3702*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3702*FLEN/8, x7, x2, x4) + +inst_1877: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xffc; + valaddr_reg:x6; val_offset:3704*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3704*FLEN/8, x7, x2, x4) + +inst_1878: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xffc; op2val:0x3ff; + valaddr_reg:x6; val_offset:3706*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3706*FLEN/8, x7, x2, x4) + +inst_1879: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x03 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xc01; + valaddr_reg:x6; val_offset:3708*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3708*FLEN/8, x7, x2, x4) + +inst_1880: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc01; op2val:0x3ff; + valaddr_reg:x6; val_offset:3710*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3710*FLEN/8, x7, x2, x4) + +inst_1881: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xffe; + valaddr_reg:x6; val_offset:3712*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3712*FLEN/8, x7, x2, x4) + +inst_1882: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xffe; op2val:0x3ff; + valaddr_reg:x6; val_offset:3714*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3714*FLEN/8, x7, x2, x4) + +inst_1883: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x83ff; + valaddr_reg:x6; val_offset:3716*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3716*FLEN/8, x7, x2, x4) + +inst_1884: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x81ff; + valaddr_reg:x6; val_offset:3718*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3718*FLEN/8, x7, x2, x4) + +inst_1885: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x81ff; op2val:0x83ff; + valaddr_reg:x6; val_offset:3720*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3720*FLEN/8, x7, x2, x4) + +inst_1886: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8200; + valaddr_reg:x6; val_offset:3722*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3722*FLEN/8, x7, x2, x4) + +inst_1887: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8200; op2val:0x83ff; + valaddr_reg:x6; val_offset:3724*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3724*FLEN/8, x7, x2, x4) + +inst_1888: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x80ff; + valaddr_reg:x6; val_offset:3726*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3726*FLEN/8, x7, x2, x4) + +inst_1889: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x80ff; op2val:0x83ff; + valaddr_reg:x6; val_offset:3728*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3728*FLEN/8, x7, x2, x4) + +inst_1890: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8300; + valaddr_reg:x6; val_offset:3730*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3730*FLEN/8, x7, x2, x4) + +inst_1891: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x300 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8300; op2val:0x83ff; + valaddr_reg:x6; val_offset:3732*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3732*FLEN/8, x7, x2, x4) + +inst_1892: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x807f; + valaddr_reg:x6; val_offset:3734*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3734*FLEN/8, x7, x2, x4) + +inst_1893: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x07f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x807f; op2val:0x83ff; + valaddr_reg:x6; val_offset:3736*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3736*FLEN/8, x7, x2, x4) + +inst_1894: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8380; + valaddr_reg:x6; val_offset:3738*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3738*FLEN/8, x7, x2, x4) + +inst_1895: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x380 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8380; op2val:0x83ff; + valaddr_reg:x6; val_offset:3740*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3740*FLEN/8, x7, x2, x4) + +inst_1896: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x803f; + valaddr_reg:x6; val_offset:3742*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3742*FLEN/8, x7, x2, x4) + +inst_1897: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x803f; op2val:0x83ff; + valaddr_reg:x6; val_offset:3744*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3744*FLEN/8, x7, x2, x4) + +inst_1898: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x83c0; + valaddr_reg:x6; val_offset:3746*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3746*FLEN/8, x7, x2, x4) + +inst_1899: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83c0; op2val:0x83ff; + valaddr_reg:x6; val_offset:3748*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3748*FLEN/8, x7, x2, x4) + +inst_1900: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x801f; + valaddr_reg:x6; val_offset:3750*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3750*FLEN/8, x7, x2, x4) + +inst_1901: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x01f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x801f; op2val:0x83ff; + valaddr_reg:x6; val_offset:3752*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3752*FLEN/8, x7, x2, x4) + +inst_1902: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x83e0; + valaddr_reg:x6; val_offset:3754*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3754*FLEN/8, x7, x2, x4) + +inst_1903: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83e0; op2val:0x83ff; + valaddr_reg:x6; val_offset:3756*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3756*FLEN/8, x7, x2, x4) + +inst_1904: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x800f; + valaddr_reg:x6; val_offset:3758*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3758*FLEN/8, x7, x2, x4) + +inst_1905: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x00f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x800f; op2val:0x83ff; + valaddr_reg:x6; val_offset:3760*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3760*FLEN/8, x7, x2, x4) + +inst_1906: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x83f0; + valaddr_reg:x6; val_offset:3762*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3762*FLEN/8, x7, x2, x4) + +inst_1907: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83f0; op2val:0x83ff; + valaddr_reg:x6; val_offset:3764*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3764*FLEN/8, x7, x2, x4) + +inst_1908: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8007; + valaddr_reg:x6; val_offset:3766*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3766*FLEN/8, x7, x2, x4) + +inst_1909: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8007; op2val:0x83ff; + valaddr_reg:x6; val_offset:3768*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3768*FLEN/8, x7, x2, x4) + +inst_1910: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x83f8; + valaddr_reg:x6; val_offset:3770*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3770*FLEN/8, x7, x2, x4) + +inst_1911: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83f8; op2val:0x83ff; + valaddr_reg:x6; val_offset:3772*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3772*FLEN/8, x7, x2, x4) + +inst_1912: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8003; + valaddr_reg:x6; val_offset:3774*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3774*FLEN/8, x7, x2, x4) + +inst_1913: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8003; op2val:0x83ff; + valaddr_reg:x6; val_offset:3776*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3776*FLEN/8, x7, x2, x4) + +inst_1914: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x83fc; + valaddr_reg:x6; val_offset:3778*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3778*FLEN/8, x7, x2, x4) + +inst_1915: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fc; op2val:0x83ff; + valaddr_reg:x6; val_offset:3780*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3780*FLEN/8, x7, x2, x4) + +inst_1916: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x83fe; + valaddr_reg:x6; val_offset:3782*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3782*FLEN/8, x7, x2, x4) + +inst_1917: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x83ff; + valaddr_reg:x6; val_offset:3784*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3784*FLEN/8, x7, x2, x4) + +inst_1918: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1b6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x81b6; + valaddr_reg:x6; val_offset:3786*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3786*FLEN/8, x7, x2, x4) + +inst_1919: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x81b6; op2val:0x83ff; + valaddr_reg:x6; val_offset:3788*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3788*FLEN/8, x7, x2, x4) + +inst_1920: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x36d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x836d; + valaddr_reg:x6; val_offset:3790*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3790*FLEN/8, x7, x2, x4) + +inst_1921: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x36d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x836d; op2val:0x83ff; + valaddr_reg:x6; val_offset:3792*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3792*FLEN/8, x7, x2, x4) + +inst_1922: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0cc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x80cc; + valaddr_reg:x6; val_offset:3794*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3794*FLEN/8, x7, x2, x4) + +inst_1923: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0cc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x80cc; op2val:0x83ff; + valaddr_reg:x6; val_offset:3796*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3796*FLEN/8, x7, x2, x4) + +inst_1924: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x333 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8333; + valaddr_reg:x6; val_offset:3798*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3798*FLEN/8, x7, x2, x4) + +inst_1925: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x333 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8333; op2val:0x83ff; + valaddr_reg:x6; val_offset:3800*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3800*FLEN/8, x7, x2, x4) + +inst_1926: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1dd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x81dd; + valaddr_reg:x6; val_offset:3802*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3802*FLEN/8, x7, x2, x4) + +inst_1927: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1dd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x81dd; op2val:0x83ff; + valaddr_reg:x6; val_offset:3804*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3804*FLEN/8, x7, x2, x4) + +inst_1928: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x222 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8222; + valaddr_reg:x6; val_offset:3806*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3806*FLEN/8, x7, x2, x4) + +inst_1929: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x222 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8222; op2val:0x83ff; + valaddr_reg:x6; val_offset:3808*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3808*FLEN/8, x7, x2, x4) + +inst_1930: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x124 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8124; + valaddr_reg:x6; val_offset:3810*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3810*FLEN/8, x7, x2, x4) + +inst_1931: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x124 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8124; op2val:0x83ff; + valaddr_reg:x6; val_offset:3812*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3812*FLEN/8, x7, x2, x4) + +inst_1932: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2db and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x82db; + valaddr_reg:x6; val_offset:3814*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3814*FLEN/8, x7, x2, x4) + +inst_1933: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x82db; op2val:0x83ff; + valaddr_reg:x6; val_offset:3816*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3816*FLEN/8, x7, x2, x4) + +inst_1934: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x199 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8199; + valaddr_reg:x6; val_offset:3818*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3818*FLEN/8, x7, x2, x4) + +inst_1935: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x199 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8199; op2val:0x83ff; + valaddr_reg:x6; val_offset:3820*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3820*FLEN/8, x7, x2, x4) + +inst_1936: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x266 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8266; + valaddr_reg:x6; val_offset:3822*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3822*FLEN/8, x7, x2, x4) + +inst_1937: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x266 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8266; op2val:0x83ff; + valaddr_reg:x6; val_offset:3824*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3824*FLEN/8, x7, x2, x4) + +inst_1938: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x33ff; + valaddr_reg:x6; val_offset:3826*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3826*FLEN/8, x7, x2, x4) + +inst_1939: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x33ff; op2val:0x83ff; + valaddr_reg:x6; val_offset:3828*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3828*FLEN/8, x7, x2, x4) + +inst_1940: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0c and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x3000; + valaddr_reg:x6; val_offset:3830*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3830*FLEN/8, x7, x2, x4) + +inst_1941: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3000; op2val:0x83ff; + valaddr_reg:x6; val_offset:3832*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3832*FLEN/8, x7, x2, x4) + +inst_1942: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x31ff; + valaddr_reg:x6; val_offset:3834*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3834*FLEN/8, x7, x2, x4) + +inst_1943: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x31ff; op2val:0x83ff; + valaddr_reg:x6; val_offset:3836*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3836*FLEN/8, x7, x2, x4) + +inst_1944: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0c and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x3200; + valaddr_reg:x6; val_offset:3838*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3838*FLEN/8, x7, x2, x4) + +inst_1945: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3200; op2val:0x83ff; + valaddr_reg:x6; val_offset:3840*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3840*FLEN/8, x7, x2, x4) + +inst_1946: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x30ff; + valaddr_reg:x6; val_offset:3842*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3842*FLEN/8, x7, x2, x4) + +inst_1947: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x30ff; op2val:0x83ff; + valaddr_reg:x6; val_offset:3844*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3844*FLEN/8, x7, x2, x4) + +inst_1948: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0c and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x3300; + valaddr_reg:x6; val_offset:3846*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3846*FLEN/8, x7, x2, x4) +RVTEST_SIGBASE(x2,signature_x2_17) + +inst_1949: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x300 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3300; op2val:0x83ff; + valaddr_reg:x6; val_offset:3848*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3848*FLEN/8, x7, x2, x4) + +inst_1950: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0c and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x307f; + valaddr_reg:x6; val_offset:3850*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3850*FLEN/8, x7, x2, x4) + +inst_1951: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x07f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x307f; op2val:0x83ff; + valaddr_reg:x6; val_offset:3852*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3852*FLEN/8, x7, x2, x4) + +inst_1952: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0c and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x3380; + valaddr_reg:x6; val_offset:3854*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3854*FLEN/8, x7, x2, x4) + +inst_1953: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x380 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3380; op2val:0x83ff; + valaddr_reg:x6; val_offset:3856*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3856*FLEN/8, x7, x2, x4) + +inst_1954: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0c and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x303f; + valaddr_reg:x6; val_offset:3858*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3858*FLEN/8, x7, x2, x4) + +inst_1955: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x03f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x303f; op2val:0x83ff; + valaddr_reg:x6; val_offset:3860*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3860*FLEN/8, x7, x2, x4) + +inst_1956: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x33c0; + valaddr_reg:x6; val_offset:3862*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3862*FLEN/8, x7, x2, x4) + +inst_1957: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x33c0; op2val:0x83ff; + valaddr_reg:x6; val_offset:3864*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3864*FLEN/8, x7, x2, x4) + +inst_1958: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0c and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x301f; + valaddr_reg:x6; val_offset:3866*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3866*FLEN/8, x7, x2, x4) + +inst_1959: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x01f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x301f; op2val:0x83ff; + valaddr_reg:x6; val_offset:3868*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3868*FLEN/8, x7, x2, x4) + +inst_1960: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x33e0; + valaddr_reg:x6; val_offset:3870*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3870*FLEN/8, x7, x2, x4) + +inst_1961: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x33e0; op2val:0x83ff; + valaddr_reg:x6; val_offset:3872*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3872*FLEN/8, x7, x2, x4) + +inst_1962: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0c and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x300f; + valaddr_reg:x6; val_offset:3874*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3874*FLEN/8, x7, x2, x4) + +inst_1963: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x00f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x300f; op2val:0x83ff; + valaddr_reg:x6; val_offset:3876*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3876*FLEN/8, x7, x2, x4) + +inst_1964: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x33f0; + valaddr_reg:x6; val_offset:3878*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3878*FLEN/8, x7, x2, x4) + +inst_1965: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x33f0; op2val:0x83ff; + valaddr_reg:x6; val_offset:3880*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3880*FLEN/8, x7, x2, x4) + +inst_1966: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0c and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x3007; + valaddr_reg:x6; val_offset:3882*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3882*FLEN/8, x7, x2, x4) + +inst_1967: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x007 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3007; op2val:0x83ff; + valaddr_reg:x6; val_offset:3884*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3884*FLEN/8, x7, x2, x4) + +inst_1968: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x33f8; + valaddr_reg:x6; val_offset:3886*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3886*FLEN/8, x7, x2, x4) + +inst_1969: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x33f8; op2val:0x83ff; + valaddr_reg:x6; val_offset:3888*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3888*FLEN/8, x7, x2, x4) + +inst_1970: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0c and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x3003; + valaddr_reg:x6; val_offset:3890*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3890*FLEN/8, x7, x2, x4) + +inst_1971: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x003 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3003; op2val:0x83ff; + valaddr_reg:x6; val_offset:3892*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3892*FLEN/8, x7, x2, x4) + +inst_1972: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x33fc; + valaddr_reg:x6; val_offset:3894*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3894*FLEN/8, x7, x2, x4) + +inst_1973: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x33fc; op2val:0x83ff; + valaddr_reg:x6; val_offset:3896*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3896*FLEN/8, x7, x2, x4) + +inst_1974: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0c and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x3001; + valaddr_reg:x6; val_offset:3898*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3898*FLEN/8, x7, x2, x4) + +inst_1975: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3001; op2val:0x83ff; + valaddr_reg:x6; val_offset:3900*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3900*FLEN/8, x7, x2, x4) + +inst_1976: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x33fe; + valaddr_reg:x6; val_offset:3902*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3902*FLEN/8, x7, x2, x4) + +inst_1977: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x33fe; op2val:0x83ff; + valaddr_reg:x6; val_offset:3904*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3904*FLEN/8, x7, x2, x4) + +inst_1978: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x87ff; + valaddr_reg:x6; val_offset:3906*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3906*FLEN/8, x7, x2, x4) + +inst_1979: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x87ff; op2val:0x83ff; + valaddr_reg:x6; val_offset:3908*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3908*FLEN/8, x7, x2, x4) + +inst_1980: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8400; + valaddr_reg:x6; val_offset:3910*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3910*FLEN/8, x7, x2, x4) + +inst_1981: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x83ff; + valaddr_reg:x6; val_offset:3912*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3912*FLEN/8, x7, x2, x4) + +inst_1982: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x85ff; + valaddr_reg:x6; val_offset:3914*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3914*FLEN/8, x7, x2, x4) + +inst_1983: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x85ff; op2val:0x83ff; + valaddr_reg:x6; val_offset:3916*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3916*FLEN/8, x7, x2, x4) + +inst_1984: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8600; + valaddr_reg:x6; val_offset:3918*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3918*FLEN/8, x7, x2, x4) + +inst_1985: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8600; op2val:0x83ff; + valaddr_reg:x6; val_offset:3920*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3920*FLEN/8, x7, x2, x4) + +inst_1986: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x84ff; + valaddr_reg:x6; val_offset:3922*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3922*FLEN/8, x7, x2, x4) + +inst_1987: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x84ff; op2val:0x83ff; + valaddr_reg:x6; val_offset:3924*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3924*FLEN/8, x7, x2, x4) + +inst_1988: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8700; + valaddr_reg:x6; val_offset:3926*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3926*FLEN/8, x7, x2, x4) + +inst_1989: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x300 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8700; op2val:0x83ff; + valaddr_reg:x6; val_offset:3928*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3928*FLEN/8, x7, x2, x4) + +inst_1990: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x847f; + valaddr_reg:x6; val_offset:3930*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3930*FLEN/8, x7, x2, x4) + +inst_1991: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x07f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x847f; op2val:0x83ff; + valaddr_reg:x6; val_offset:3932*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3932*FLEN/8, x7, x2, x4) + +inst_1992: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8780; + valaddr_reg:x6; val_offset:3934*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3934*FLEN/8, x7, x2, x4) + +inst_1993: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x380 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8780; op2val:0x83ff; + valaddr_reg:x6; val_offset:3936*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3936*FLEN/8, x7, x2, x4) + +inst_1994: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x843f; + valaddr_reg:x6; val_offset:3938*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3938*FLEN/8, x7, x2, x4) + +inst_1995: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x843f; op2val:0x83ff; + valaddr_reg:x6; val_offset:3940*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3940*FLEN/8, x7, x2, x4) + +inst_1996: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x87c0; + valaddr_reg:x6; val_offset:3942*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3942*FLEN/8, x7, x2, x4) + +inst_1997: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x87c0; op2val:0x83ff; + valaddr_reg:x6; val_offset:3944*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3944*FLEN/8, x7, x2, x4) + +inst_1998: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x841f; + valaddr_reg:x6; val_offset:3946*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3946*FLEN/8, x7, x2, x4) + +inst_1999: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x01f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x841f; op2val:0x83ff; + valaddr_reg:x6; val_offset:3948*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3948*FLEN/8, x7, x2, x4) + +inst_2000: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x87e0; + valaddr_reg:x6; val_offset:3950*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3950*FLEN/8, x7, x2, x4) + +inst_2001: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x87e0; op2val:0x83ff; + valaddr_reg:x6; val_offset:3952*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3952*FLEN/8, x7, x2, x4) + +inst_2002: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x840f; + valaddr_reg:x6; val_offset:3954*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3954*FLEN/8, x7, x2, x4) + +inst_2003: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x00f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x840f; op2val:0x83ff; + valaddr_reg:x6; val_offset:3956*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3956*FLEN/8, x7, x2, x4) + +inst_2004: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x87f0; + valaddr_reg:x6; val_offset:3958*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3958*FLEN/8, x7, x2, x4) + +inst_2005: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x87f0; op2val:0x83ff; + valaddr_reg:x6; val_offset:3960*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3960*FLEN/8, x7, x2, x4) + +inst_2006: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8407; + valaddr_reg:x6; val_offset:3962*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3962*FLEN/8, x7, x2, x4) + +inst_2007: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8407; op2val:0x83ff; + valaddr_reg:x6; val_offset:3964*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3964*FLEN/8, x7, x2, x4) + +inst_2008: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x87f8; + valaddr_reg:x6; val_offset:3966*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3966*FLEN/8, x7, x2, x4) + +inst_2009: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x87f8; op2val:0x83ff; + valaddr_reg:x6; val_offset:3968*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3968*FLEN/8, x7, x2, x4) + +inst_2010: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8403; + valaddr_reg:x6; val_offset:3970*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3970*FLEN/8, x7, x2, x4) + +inst_2011: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8403; op2val:0x83ff; + valaddr_reg:x6; val_offset:3972*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3972*FLEN/8, x7, x2, x4) + +inst_2012: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x87fc; + valaddr_reg:x6; val_offset:3974*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3974*FLEN/8, x7, x2, x4) + +inst_2013: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x87fc; op2val:0x83ff; + valaddr_reg:x6; val_offset:3976*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3976*FLEN/8, x7, x2, x4) + +inst_2014: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8401; + valaddr_reg:x6; val_offset:3978*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3978*FLEN/8, x7, x2, x4) + +inst_2015: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8401; op2val:0x83ff; + valaddr_reg:x6; val_offset:3980*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3980*FLEN/8, x7, x2, x4) + +inst_2016: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x87fe; + valaddr_reg:x6; val_offset:3982*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3982*FLEN/8, x7, x2, x4) + +inst_2017: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x87fe; op2val:0x83ff; + valaddr_reg:x6; val_offset:3984*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3984*FLEN/8, x7, x2, x4) + +inst_2018: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x02 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8bff; + valaddr_reg:x6; val_offset:3986*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3986*FLEN/8, x7, x2, x4) + +inst_2019: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8bff; op2val:0x83ff; + valaddr_reg:x6; val_offset:3988*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3988*FLEN/8, x7, x2, x4) + +inst_2020: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x02 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8800; + valaddr_reg:x6; val_offset:3990*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3990*FLEN/8, x7, x2, x4) + +inst_2021: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8800; op2val:0x83ff; + valaddr_reg:x6; val_offset:3992*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3992*FLEN/8, x7, x2, x4) + +inst_2022: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x89ff; + valaddr_reg:x6; val_offset:3994*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3994*FLEN/8, x7, x2, x4) + +inst_2023: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x89ff; op2val:0x83ff; + valaddr_reg:x6; val_offset:3996*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3996*FLEN/8, x7, x2, x4) + +inst_2024: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x02 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8a00; + valaddr_reg:x6; val_offset:3998*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 3998*FLEN/8, x7, x2, x4) + +inst_2025: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8a00; op2val:0x83ff; + valaddr_reg:x6; val_offset:4000*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4000*FLEN/8, x7, x2, x4) + +inst_2026: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x02 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x88ff; + valaddr_reg:x6; val_offset:4002*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4002*FLEN/8, x7, x2, x4) + +inst_2027: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x88ff; op2val:0x83ff; + valaddr_reg:x6; val_offset:4004*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4004*FLEN/8, x7, x2, x4) + +inst_2028: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x02 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8b00; + valaddr_reg:x6; val_offset:4006*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4006*FLEN/8, x7, x2, x4) + +inst_2029: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x300 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8b00; op2val:0x83ff; + valaddr_reg:x6; val_offset:4008*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4008*FLEN/8, x7, x2, x4) + +inst_2030: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x02 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x887f; + valaddr_reg:x6; val_offset:4010*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4010*FLEN/8, x7, x2, x4) + +inst_2031: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x07f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x887f; op2val:0x83ff; + valaddr_reg:x6; val_offset:4012*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4012*FLEN/8, x7, x2, x4) + +inst_2032: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x02 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8b80; + valaddr_reg:x6; val_offset:4014*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4014*FLEN/8, x7, x2, x4) + +inst_2033: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x380 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8b80; op2val:0x83ff; + valaddr_reg:x6; val_offset:4016*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4016*FLEN/8, x7, x2, x4) + +inst_2034: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x02 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x883f; + valaddr_reg:x6; val_offset:4018*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4018*FLEN/8, x7, x2, x4) + +inst_2035: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x883f; op2val:0x83ff; + valaddr_reg:x6; val_offset:4020*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4020*FLEN/8, x7, x2, x4) + +inst_2036: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x02 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8bc0; + valaddr_reg:x6; val_offset:4022*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4022*FLEN/8, x7, x2, x4) + +inst_2037: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8bc0; op2val:0x83ff; + valaddr_reg:x6; val_offset:4024*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4024*FLEN/8, x7, x2, x4) + +inst_2038: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x02 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x881f; + valaddr_reg:x6; val_offset:4026*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4026*FLEN/8, x7, x2, x4) + +inst_2039: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x01f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x881f; op2val:0x83ff; + valaddr_reg:x6; val_offset:4028*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4028*FLEN/8, x7, x2, x4) + +inst_2040: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x02 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8be0; + valaddr_reg:x6; val_offset:4030*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4030*FLEN/8, x7, x2, x4) + +inst_2041: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8be0; op2val:0x83ff; + valaddr_reg:x6; val_offset:4032*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4032*FLEN/8, x7, x2, x4) + +inst_2042: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x02 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x880f; + valaddr_reg:x6; val_offset:4034*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4034*FLEN/8, x7, x2, x4) + +inst_2043: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x00f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x880f; op2val:0x83ff; + valaddr_reg:x6; val_offset:4036*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4036*FLEN/8, x7, x2, x4) + +inst_2044: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x02 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8bf0; + valaddr_reg:x6; val_offset:4038*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4038*FLEN/8, x7, x2, x4) + +inst_2045: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8bf0; op2val:0x83ff; + valaddr_reg:x6; val_offset:4040*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4040*FLEN/8, x7, x2, x4) + +inst_2046: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x02 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8807; + valaddr_reg:x6; val_offset:4042*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4042*FLEN/8, x7, x2, x4) + +inst_2047: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8807; op2val:0x83ff; + valaddr_reg:x6; val_offset:4044*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4044*FLEN/8, x7, x2, x4) + +inst_2048: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x02 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8bf8; + valaddr_reg:x6; val_offset:4046*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4046*FLEN/8, x7, x2, x4) + +inst_2049: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8bf8; op2val:0x83ff; + valaddr_reg:x6; val_offset:4048*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4048*FLEN/8, x7, x2, x4) + +inst_2050: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x02 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8803; + valaddr_reg:x6; val_offset:4050*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4050*FLEN/8, x7, x2, x4) + +inst_2051: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8803; op2val:0x83ff; + valaddr_reg:x6; val_offset:4052*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4052*FLEN/8, x7, x2, x4) + +inst_2052: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x02 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8bfc; + valaddr_reg:x6; val_offset:4054*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4054*FLEN/8, x7, x2, x4) + +inst_2053: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8bfc; op2val:0x83ff; + valaddr_reg:x6; val_offset:4056*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4056*FLEN/8, x7, x2, x4) + +inst_2054: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x02 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8801; + valaddr_reg:x6; val_offset:4058*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4058*FLEN/8, x7, x2, x4) + +inst_2055: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8801; op2val:0x83ff; + valaddr_reg:x6; val_offset:4060*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4060*FLEN/8, x7, x2, x4) + +inst_2056: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x02 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8bfe; + valaddr_reg:x6; val_offset:4062*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4062*FLEN/8, x7, x2, x4) + +inst_2057: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8bfe; op2val:0x83ff; + valaddr_reg:x6; val_offset:4064*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4064*FLEN/8, x7, x2, x4) + +inst_2058: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x03 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8fff; + valaddr_reg:x6; val_offset:4066*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4066*FLEN/8, x7, x2, x4) + +inst_2059: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8fff; op2val:0x83ff; + valaddr_reg:x6; val_offset:4068*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4068*FLEN/8, x7, x2, x4) + +inst_2060: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x03 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8c00; + valaddr_reg:x6; val_offset:4070*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4070*FLEN/8, x7, x2, x4) + +inst_2061: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8c00; op2val:0x83ff; + valaddr_reg:x6; val_offset:4072*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4072*FLEN/8, x7, x2, x4) + +inst_2062: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x03 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8dff; + valaddr_reg:x6; val_offset:4074*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4074*FLEN/8, x7, x2, x4) + +inst_2063: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8dff; op2val:0x83ff; + valaddr_reg:x6; val_offset:4076*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4076*FLEN/8, x7, x2, x4) + +inst_2064: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x03 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8e00; + valaddr_reg:x6; val_offset:4078*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4078*FLEN/8, x7, x2, x4) + +inst_2065: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8e00; op2val:0x83ff; + valaddr_reg:x6; val_offset:4080*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4080*FLEN/8, x7, x2, x4) + +inst_2066: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x03 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8cff; + valaddr_reg:x6; val_offset:4082*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4082*FLEN/8, x7, x2, x4) + +inst_2067: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8cff; op2val:0x83ff; + valaddr_reg:x6; val_offset:4084*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4084*FLEN/8, x7, x2, x4) + +inst_2068: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x03 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8f00; + valaddr_reg:x6; val_offset:4086*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4086*FLEN/8, x7, x2, x4) + +inst_2069: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x300 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8f00; op2val:0x83ff; + valaddr_reg:x6; val_offset:4088*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4088*FLEN/8, x7, x2, x4) + +inst_2070: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x03 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8c7f; + valaddr_reg:x6; val_offset:4090*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4090*FLEN/8, x7, x2, x4) + +inst_2071: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x07f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8c7f; op2val:0x83ff; + valaddr_reg:x6; val_offset:4092*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4092*FLEN/8, x7, x2, x4) + +inst_2072: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x03 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8f80; + valaddr_reg:x6; val_offset:4094*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4094*FLEN/8, x7, x2, x4) + +inst_2073: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x380 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8f80; op2val:0x83ff; + valaddr_reg:x6; val_offset:4096*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4096*FLEN/8, x7, x2, x4) + +inst_2074: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x03 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8c3f; + valaddr_reg:x6; val_offset:4098*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4098*FLEN/8, x7, x2, x4) + +inst_2075: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8c3f; op2val:0x83ff; + valaddr_reg:x6; val_offset:4100*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4100*FLEN/8, x7, x2, x4) + +inst_2076: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x03 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8fc0; + valaddr_reg:x6; val_offset:4102*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4102*FLEN/8, x7, x2, x4) +RVTEST_SIGBASE(x2,signature_x2_18) + +inst_2077: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8fc0; op2val:0x83ff; + valaddr_reg:x6; val_offset:4104*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4104*FLEN/8, x7, x2, x4) + +inst_2078: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x03 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8c1f; + valaddr_reg:x6; val_offset:4106*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4106*FLEN/8, x7, x2, x4) + +inst_2079: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x01f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8c1f; op2val:0x83ff; + valaddr_reg:x6; val_offset:4108*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4108*FLEN/8, x7, x2, x4) + +inst_2080: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x03 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8fe0; + valaddr_reg:x6; val_offset:4110*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4110*FLEN/8, x7, x2, x4) + +inst_2081: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8fe0; op2val:0x83ff; + valaddr_reg:x6; val_offset:4112*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4112*FLEN/8, x7, x2, x4) + +inst_2082: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x03 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8c0f; + valaddr_reg:x6; val_offset:4114*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4114*FLEN/8, x7, x2, x4) + +inst_2083: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x00f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8c0f; op2val:0x83ff; + valaddr_reg:x6; val_offset:4116*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4116*FLEN/8, x7, x2, x4) + +inst_2084: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x03 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8ff0; + valaddr_reg:x6; val_offset:4118*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4118*FLEN/8, x7, x2, x4) + +inst_2085: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8ff0; op2val:0x83ff; + valaddr_reg:x6; val_offset:4120*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4120*FLEN/8, x7, x2, x4) + +inst_2086: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x03 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8c07; + valaddr_reg:x6; val_offset:4122*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4122*FLEN/8, x7, x2, x4) + +inst_2087: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8c07; op2val:0x83ff; + valaddr_reg:x6; val_offset:4124*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4124*FLEN/8, x7, x2, x4) + +inst_2088: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x03 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8ff8; + valaddr_reg:x6; val_offset:4126*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4126*FLEN/8, x7, x2, x4) + +inst_2089: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8ff8; op2val:0x83ff; + valaddr_reg:x6; val_offset:4128*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4128*FLEN/8, x7, x2, x4) + +inst_2090: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x03 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8c03; + valaddr_reg:x6; val_offset:4130*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4130*FLEN/8, x7, x2, x4) + +inst_2091: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8c03; op2val:0x83ff; + valaddr_reg:x6; val_offset:4132*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4132*FLEN/8, x7, x2, x4) + +inst_2092: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x03 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8ffc; + valaddr_reg:x6; val_offset:4134*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4134*FLEN/8, x7, x2, x4) + +inst_2093: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8ffc; op2val:0x83ff; + valaddr_reg:x6; val_offset:4136*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4136*FLEN/8, x7, x2, x4) + +inst_2094: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x03 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8c01; + valaddr_reg:x6; val_offset:4138*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4138*FLEN/8, x7, x2, x4) + +inst_2095: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8c01; op2val:0x83ff; + valaddr_reg:x6; val_offset:4140*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4140*FLEN/8, x7, x2, x4) + +inst_2096: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x03 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8ffe; + valaddr_reg:x6; val_offset:4142*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4142*FLEN/8, x7, x2, x4) + +inst_2097: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8ffe; op2val:0x83ff; + valaddr_reg:x6; val_offset:4144*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4144*FLEN/8, x7, x2, x4) + +inst_2098: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x200; + valaddr_reg:x6; val_offset:4146*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4146*FLEN/8, x7, x2, x4) + +inst_2099: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x200; op2val:0x400; + valaddr_reg:x6; val_offset:4148*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4148*FLEN/8, x7, x2, x4) + +inst_2100: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x1ff; + valaddr_reg:x6; val_offset:4150*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4150*FLEN/8, x7, x2, x4) + +inst_2101: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1ff; op2val:0x400; + valaddr_reg:x6; val_offset:4152*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4152*FLEN/8, x7, x2, x4) + +inst_2102: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x300; + valaddr_reg:x6; val_offset:4154*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4154*FLEN/8, x7, x2, x4) + +inst_2103: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x300 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x300; op2val:0x400; + valaddr_reg:x6; val_offset:4156*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4156*FLEN/8, x7, x2, x4) + +inst_2104: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xff; + valaddr_reg:x6; val_offset:4158*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4158*FLEN/8, x7, x2, x4) + +inst_2105: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xff; op2val:0x400; + valaddr_reg:x6; val_offset:4160*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4160*FLEN/8, x7, x2, x4) + +inst_2106: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x380; + valaddr_reg:x6; val_offset:4162*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4162*FLEN/8, x7, x2, x4) + +inst_2107: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x380 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x380; op2val:0x400; + valaddr_reg:x6; val_offset:4164*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4164*FLEN/8, x7, x2, x4) + +inst_2108: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7f; + valaddr_reg:x6; val_offset:4166*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4166*FLEN/8, x7, x2, x4) + +inst_2109: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x07f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7f; op2val:0x400; + valaddr_reg:x6; val_offset:4168*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4168*FLEN/8, x7, x2, x4) + +inst_2110: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x3c0; + valaddr_reg:x6; val_offset:4170*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4170*FLEN/8, x7, x2, x4) + +inst_2111: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c0; op2val:0x400; + valaddr_reg:x6; val_offset:4172*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4172*FLEN/8, x7, x2, x4) + +inst_2112: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x3f; + valaddr_reg:x6; val_offset:4174*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4174*FLEN/8, x7, x2, x4) + +inst_2113: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3f; op2val:0x400; + valaddr_reg:x6; val_offset:4176*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4176*FLEN/8, x7, x2, x4) + +inst_2114: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x3e0; + valaddr_reg:x6; val_offset:4178*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4178*FLEN/8, x7, x2, x4) + +inst_2115: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3e0; op2val:0x400; + valaddr_reg:x6; val_offset:4180*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4180*FLEN/8, x7, x2, x4) + +inst_2116: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x1f; + valaddr_reg:x6; val_offset:4182*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4182*FLEN/8, x7, x2, x4) + +inst_2117: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x01f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1f; op2val:0x400; + valaddr_reg:x6; val_offset:4184*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4184*FLEN/8, x7, x2, x4) + +inst_2118: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x3f0; + valaddr_reg:x6; val_offset:4186*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4186*FLEN/8, x7, x2, x4) + +inst_2119: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3f0; op2val:0x400; + valaddr_reg:x6; val_offset:4188*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4188*FLEN/8, x7, x2, x4) + +inst_2120: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xf; + valaddr_reg:x6; val_offset:4190*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4190*FLEN/8, x7, x2, x4) + +inst_2121: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf; op2val:0x400; + valaddr_reg:x6; val_offset:4192*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4192*FLEN/8, x7, x2, x4) + +inst_2122: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x3f8; + valaddr_reg:x6; val_offset:4194*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4194*FLEN/8, x7, x2, x4) + +inst_2123: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3f8; op2val:0x400; + valaddr_reg:x6; val_offset:4196*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4196*FLEN/8, x7, x2, x4) + +inst_2124: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7; + valaddr_reg:x6; val_offset:4198*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4198*FLEN/8, x7, x2, x4) + +inst_2125: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7; op2val:0x400; + valaddr_reg:x6; val_offset:4200*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4200*FLEN/8, x7, x2, x4) + +inst_2126: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x3fc; + valaddr_reg:x6; val_offset:4202*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4202*FLEN/8, x7, x2, x4) + +inst_2127: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fc; op2val:0x400; + valaddr_reg:x6; val_offset:4204*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4204*FLEN/8, x7, x2, x4) + +inst_2128: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x3; + valaddr_reg:x6; val_offset:4206*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4206*FLEN/8, x7, x2, x4) + +inst_2129: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x003 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3; op2val:0x400; + valaddr_reg:x6; val_offset:4208*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4208*FLEN/8, x7, x2, x4) + +inst_2130: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x3fe; + valaddr_reg:x6; val_offset:4210*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4210*FLEN/8, x7, x2, x4) + +inst_2131: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fe; op2val:0x400; + valaddr_reg:x6; val_offset:4212*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4212*FLEN/8, x7, x2, x4) + +inst_2132: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7fe; + valaddr_reg:x6; val_offset:4214*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4214*FLEN/8, x7, x2, x4) + +inst_2133: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7fe; op2val:0x400; + valaddr_reg:x6; val_offset:4216*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4216*FLEN/8, x7, x2, x4) + +inst_2134: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x401; + valaddr_reg:x6; val_offset:4218*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4218*FLEN/8, x7, x2, x4) + +inst_2135: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x400; + valaddr_reg:x6; val_offset:4220*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4220*FLEN/8, x7, x2, x4) + +inst_2136: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1b6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x5b6; + valaddr_reg:x6; val_offset:4222*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4222*FLEN/8, x7, x2, x4) + +inst_2137: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x1b6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5b6; op2val:0x400; + valaddr_reg:x6; val_offset:4224*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4224*FLEN/8, x7, x2, x4) + +inst_2138: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x36d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x76d; + valaddr_reg:x6; val_offset:4226*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4226*FLEN/8, x7, x2, x4) + +inst_2139: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x36d and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x76d; op2val:0x400; + valaddr_reg:x6; val_offset:4228*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4228*FLEN/8, x7, x2, x4) + +inst_2140: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0cc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x4cc; + valaddr_reg:x6; val_offset:4230*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4230*FLEN/8, x7, x2, x4) + +inst_2141: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x0cc and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4cc; op2val:0x400; + valaddr_reg:x6; val_offset:4232*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4232*FLEN/8, x7, x2, x4) + +inst_2142: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x333 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x733; + valaddr_reg:x6; val_offset:4234*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4234*FLEN/8, x7, x2, x4) + +inst_2143: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x333 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x733; op2val:0x400; + valaddr_reg:x6; val_offset:4236*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4236*FLEN/8, x7, x2, x4) + +inst_2144: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1dd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x5dd; + valaddr_reg:x6; val_offset:4238*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4238*FLEN/8, x7, x2, x4) + +inst_2145: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x1dd and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5dd; op2val:0x400; + valaddr_reg:x6; val_offset:4240*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4240*FLEN/8, x7, x2, x4) + +inst_2146: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x222 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x622; + valaddr_reg:x6; val_offset:4242*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4242*FLEN/8, x7, x2, x4) + +inst_2147: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x222 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x622; op2val:0x400; + valaddr_reg:x6; val_offset:4244*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4244*FLEN/8, x7, x2, x4) + +inst_2148: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x124 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x524; + valaddr_reg:x6; val_offset:4246*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4246*FLEN/8, x7, x2, x4) + +inst_2149: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x124 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x524; op2val:0x400; + valaddr_reg:x6; val_offset:4248*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4248*FLEN/8, x7, x2, x4) + +inst_2150: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x2db and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x6db; + valaddr_reg:x6; val_offset:4250*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4250*FLEN/8, x7, x2, x4) + +inst_2151: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x2db and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6db; op2val:0x400; + valaddr_reg:x6; val_offset:4252*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4252*FLEN/8, x7, x2, x4) + +inst_2152: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x199 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x599; + valaddr_reg:x6; val_offset:4254*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4254*FLEN/8, x7, x2, x4) + +inst_2153: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x199 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x599; op2val:0x400; + valaddr_reg:x6; val_offset:4256*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4256*FLEN/8, x7, x2, x4) + +inst_2154: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x266 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x666; + valaddr_reg:x6; val_offset:4258*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4258*FLEN/8, x7, x2, x4) + +inst_2155: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x266 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x666; op2val:0x400; + valaddr_reg:x6; val_offset:4260*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4260*FLEN/8, x7, x2, x4) + +inst_2156: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x6400; + valaddr_reg:x6; val_offset:4262*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4262*FLEN/8, x7, x2, x4) + +inst_2157: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6400; op2val:0x400; + valaddr_reg:x6; val_offset:4264*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4264*FLEN/8, x7, x2, x4) + +inst_2158: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x67ff; + valaddr_reg:x6; val_offset:4266*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4266*FLEN/8, x7, x2, x4) + +inst_2159: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x67ff; op2val:0x400; + valaddr_reg:x6; val_offset:4268*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4268*FLEN/8, x7, x2, x4) + +inst_2160: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x6600; + valaddr_reg:x6; val_offset:4270*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4270*FLEN/8, x7, x2, x4) + +inst_2161: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6600; op2val:0x400; + valaddr_reg:x6; val_offset:4272*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4272*FLEN/8, x7, x2, x4) + +inst_2162: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x65ff; + valaddr_reg:x6; val_offset:4274*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4274*FLEN/8, x7, x2, x4) + +inst_2163: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x65ff; op2val:0x400; + valaddr_reg:x6; val_offset:4276*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4276*FLEN/8, x7, x2, x4) + +inst_2164: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x6700; + valaddr_reg:x6; val_offset:4278*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4278*FLEN/8, x7, x2, x4) + +inst_2165: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x300 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6700; op2val:0x400; + valaddr_reg:x6; val_offset:4280*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4280*FLEN/8, x7, x2, x4) + +inst_2166: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x64ff; + valaddr_reg:x6; val_offset:4282*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4282*FLEN/8, x7, x2, x4) + +inst_2167: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x64ff; op2val:0x400; + valaddr_reg:x6; val_offset:4284*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4284*FLEN/8, x7, x2, x4) + +inst_2168: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x6780; + valaddr_reg:x6; val_offset:4286*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4286*FLEN/8, x7, x2, x4) + +inst_2169: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x380 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6780; op2val:0x400; + valaddr_reg:x6; val_offset:4288*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4288*FLEN/8, x7, x2, x4) + +inst_2170: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x647f; + valaddr_reg:x6; val_offset:4290*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4290*FLEN/8, x7, x2, x4) + +inst_2171: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x07f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x647f; op2val:0x400; + valaddr_reg:x6; val_offset:4292*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4292*FLEN/8, x7, x2, x4) + +inst_2172: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x67c0; + valaddr_reg:x6; val_offset:4294*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4294*FLEN/8, x7, x2, x4) + +inst_2173: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x67c0; op2val:0x400; + valaddr_reg:x6; val_offset:4296*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4296*FLEN/8, x7, x2, x4) + +inst_2174: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x643f; + valaddr_reg:x6; val_offset:4298*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4298*FLEN/8, x7, x2, x4) + +inst_2175: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x643f; op2val:0x400; + valaddr_reg:x6; val_offset:4300*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4300*FLEN/8, x7, x2, x4) + +inst_2176: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x67e0; + valaddr_reg:x6; val_offset:4302*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4302*FLEN/8, x7, x2, x4) + +inst_2177: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x67e0; op2val:0x400; + valaddr_reg:x6; val_offset:4304*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4304*FLEN/8, x7, x2, x4) + +inst_2178: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x641f; + valaddr_reg:x6; val_offset:4306*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4306*FLEN/8, x7, x2, x4) + +inst_2179: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x01f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x641f; op2val:0x400; + valaddr_reg:x6; val_offset:4308*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4308*FLEN/8, x7, x2, x4) + +inst_2180: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x67f0; + valaddr_reg:x6; val_offset:4310*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4310*FLEN/8, x7, x2, x4) + +inst_2181: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x67f0; op2val:0x400; + valaddr_reg:x6; val_offset:4312*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4312*FLEN/8, x7, x2, x4) + +inst_2182: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x640f; + valaddr_reg:x6; val_offset:4314*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4314*FLEN/8, x7, x2, x4) + +inst_2183: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x00f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x640f; op2val:0x400; + valaddr_reg:x6; val_offset:4316*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4316*FLEN/8, x7, x2, x4) + +inst_2184: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x67f8; + valaddr_reg:x6; val_offset:4318*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4318*FLEN/8, x7, x2, x4) + +inst_2185: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x67f8; op2val:0x400; + valaddr_reg:x6; val_offset:4320*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4320*FLEN/8, x7, x2, x4) + +inst_2186: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x6407; + valaddr_reg:x6; val_offset:4322*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4322*FLEN/8, x7, x2, x4) + +inst_2187: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6407; op2val:0x400; + valaddr_reg:x6; val_offset:4324*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4324*FLEN/8, x7, x2, x4) + +inst_2188: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x67fc; + valaddr_reg:x6; val_offset:4326*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4326*FLEN/8, x7, x2, x4) + +inst_2189: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x67fc; op2val:0x400; + valaddr_reg:x6; val_offset:4328*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4328*FLEN/8, x7, x2, x4) + +inst_2190: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x6403; + valaddr_reg:x6; val_offset:4330*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4330*FLEN/8, x7, x2, x4) + +inst_2191: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x003 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6403; op2val:0x400; + valaddr_reg:x6; val_offset:4332*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4332*FLEN/8, x7, x2, x4) + +inst_2192: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x67fe; + valaddr_reg:x6; val_offset:4334*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4334*FLEN/8, x7, x2, x4) + +inst_2193: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x67fe; op2val:0x400; + valaddr_reg:x6; val_offset:4336*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4336*FLEN/8, x7, x2, x4) + +inst_2194: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x6401; + valaddr_reg:x6; val_offset:4338*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4338*FLEN/8, x7, x2, x4) + +inst_2195: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6401; op2val:0x400; + valaddr_reg:x6; val_offset:4340*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4340*FLEN/8, x7, x2, x4) + +inst_2196: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x400; + valaddr_reg:x6; val_offset:4342*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4342*FLEN/8, x7, x2, x4) + +inst_2197: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7ff; + valaddr_reg:x6; val_offset:4344*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4344*FLEN/8, x7, x2, x4) + +inst_2198: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ff; op2val:0x400; + valaddr_reg:x6; val_offset:4346*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4346*FLEN/8, x7, x2, x4) + +inst_2199: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x600; + valaddr_reg:x6; val_offset:4348*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4348*FLEN/8, x7, x2, x4) + +inst_2200: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x600; op2val:0x400; + valaddr_reg:x6; val_offset:4350*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4350*FLEN/8, x7, x2, x4) + +inst_2201: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x5ff; + valaddr_reg:x6; val_offset:4352*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4352*FLEN/8, x7, x2, x4) + +inst_2202: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5ff; op2val:0x400; + valaddr_reg:x6; val_offset:4354*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4354*FLEN/8, x7, x2, x4) + +inst_2203: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x700; + valaddr_reg:x6; val_offset:4356*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4356*FLEN/8, x7, x2, x4) + +inst_2204: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x300 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x700; op2val:0x400; + valaddr_reg:x6; val_offset:4358*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4358*FLEN/8, x7, x2, x4) +RVTEST_SIGBASE(x2,signature_x2_19) + +inst_2205: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x4ff; + valaddr_reg:x6; val_offset:4360*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4360*FLEN/8, x7, x2, x4) + +inst_2206: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4ff; op2val:0x400; + valaddr_reg:x6; val_offset:4362*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4362*FLEN/8, x7, x2, x4) + +inst_2207: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x780; + valaddr_reg:x6; val_offset:4364*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4364*FLEN/8, x7, x2, x4) + +inst_2208: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x380 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x780; op2val:0x400; + valaddr_reg:x6; val_offset:4366*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4366*FLEN/8, x7, x2, x4) + +inst_2209: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x47f; + valaddr_reg:x6; val_offset:4368*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4368*FLEN/8, x7, x2, x4) + +inst_2210: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x07f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x47f; op2val:0x400; + valaddr_reg:x6; val_offset:4370*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4370*FLEN/8, x7, x2, x4) + +inst_2211: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7c0; + valaddr_reg:x6; val_offset:4372*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4372*FLEN/8, x7, x2, x4) + +inst_2212: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c0; op2val:0x400; + valaddr_reg:x6; val_offset:4374*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4374*FLEN/8, x7, x2, x4) + +inst_2213: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x43f; + valaddr_reg:x6; val_offset:4376*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4376*FLEN/8, x7, x2, x4) + +inst_2214: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x43f; op2val:0x400; + valaddr_reg:x6; val_offset:4378*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4378*FLEN/8, x7, x2, x4) + +inst_2215: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7e0; + valaddr_reg:x6; val_offset:4380*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4380*FLEN/8, x7, x2, x4) + +inst_2216: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e0; op2val:0x400; + valaddr_reg:x6; val_offset:4382*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4382*FLEN/8, x7, x2, x4) + +inst_2217: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x41f; + valaddr_reg:x6; val_offset:4384*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4384*FLEN/8, x7, x2, x4) + +inst_2218: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x01f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x41f; op2val:0x400; + valaddr_reg:x6; val_offset:4386*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4386*FLEN/8, x7, x2, x4) + +inst_2219: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7f0; + valaddr_reg:x6; val_offset:4388*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4388*FLEN/8, x7, x2, x4) + +inst_2220: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7f0; op2val:0x400; + valaddr_reg:x6; val_offset:4390*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4390*FLEN/8, x7, x2, x4) + +inst_2221: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x40f; + valaddr_reg:x6; val_offset:4392*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4392*FLEN/8, x7, x2, x4) + +inst_2222: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x00f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x40f; op2val:0x400; + valaddr_reg:x6; val_offset:4394*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4394*FLEN/8, x7, x2, x4) + +inst_2223: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7f8; + valaddr_reg:x6; val_offset:4396*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4396*FLEN/8, x7, x2, x4) + +inst_2224: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7f8; op2val:0x400; + valaddr_reg:x6; val_offset:4398*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4398*FLEN/8, x7, x2, x4) + +inst_2225: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x407; + valaddr_reg:x6; val_offset:4400*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4400*FLEN/8, x7, x2, x4) + +inst_2226: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x407; op2val:0x400; + valaddr_reg:x6; val_offset:4402*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4402*FLEN/8, x7, x2, x4) + +inst_2227: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7fc; + valaddr_reg:x6; val_offset:4404*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4404*FLEN/8, x7, x2, x4) + +inst_2228: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7fc; op2val:0x400; + valaddr_reg:x6; val_offset:4406*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4406*FLEN/8, x7, x2, x4) + +inst_2229: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x403; + valaddr_reg:x6; val_offset:4408*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4408*FLEN/8, x7, x2, x4) + +inst_2230: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x003 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x403; op2val:0x400; + valaddr_reg:x6; val_offset:4410*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4410*FLEN/8, x7, x2, x4) + +inst_2231: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x800; + valaddr_reg:x6; val_offset:4412*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4412*FLEN/8, x7, x2, x4) + +inst_2232: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x800; op2val:0x400; + valaddr_reg:x6; val_offset:4414*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4414*FLEN/8, x7, x2, x4) + +inst_2233: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xbff; + valaddr_reg:x6; val_offset:4416*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4416*FLEN/8, x7, x2, x4) + +inst_2234: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbff; op2val:0x400; + valaddr_reg:x6; val_offset:4418*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4418*FLEN/8, x7, x2, x4) + +inst_2235: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xa00; + valaddr_reg:x6; val_offset:4420*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4420*FLEN/8, x7, x2, x4) + +inst_2236: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xa00; op2val:0x400; + valaddr_reg:x6; val_offset:4422*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4422*FLEN/8, x7, x2, x4) + +inst_2237: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x9ff; + valaddr_reg:x6; val_offset:4424*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4424*FLEN/8, x7, x2, x4) + +inst_2238: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x9ff; op2val:0x400; + valaddr_reg:x6; val_offset:4426*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4426*FLEN/8, x7, x2, x4) + +inst_2239: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xb00; + valaddr_reg:x6; val_offset:4428*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4428*FLEN/8, x7, x2, x4) + +inst_2240: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x300 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xb00; op2val:0x400; + valaddr_reg:x6; val_offset:4430*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4430*FLEN/8, x7, x2, x4) + +inst_2241: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x8ff; + valaddr_reg:x6; val_offset:4432*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4432*FLEN/8, x7, x2, x4) + +inst_2242: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8ff; op2val:0x400; + valaddr_reg:x6; val_offset:4434*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4434*FLEN/8, x7, x2, x4) + +inst_2243: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xb80; + valaddr_reg:x6; val_offset:4436*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4436*FLEN/8, x7, x2, x4) + +inst_2244: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x380 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xb80; op2val:0x400; + valaddr_reg:x6; val_offset:4438*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4438*FLEN/8, x7, x2, x4) + +inst_2245: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x87f; + valaddr_reg:x6; val_offset:4440*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4440*FLEN/8, x7, x2, x4) + +inst_2246: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x07f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x87f; op2val:0x400; + valaddr_reg:x6; val_offset:4442*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4442*FLEN/8, x7, x2, x4) + +inst_2247: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xbc0; + valaddr_reg:x6; val_offset:4444*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4444*FLEN/8, x7, x2, x4) + +inst_2248: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc0; op2val:0x400; + valaddr_reg:x6; val_offset:4446*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4446*FLEN/8, x7, x2, x4) + +inst_2249: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x83f; + valaddr_reg:x6; val_offset:4448*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4448*FLEN/8, x7, x2, x4) + +inst_2250: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83f; op2val:0x400; + valaddr_reg:x6; val_offset:4450*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4450*FLEN/8, x7, x2, x4) + +inst_2251: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xbe0; + valaddr_reg:x6; val_offset:4452*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4452*FLEN/8, x7, x2, x4) + +inst_2252: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbe0; op2val:0x400; + valaddr_reg:x6; val_offset:4454*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4454*FLEN/8, x7, x2, x4) + +inst_2253: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x81f; + valaddr_reg:x6; val_offset:4456*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4456*FLEN/8, x7, x2, x4) + +inst_2254: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x01f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x81f; op2val:0x400; + valaddr_reg:x6; val_offset:4458*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4458*FLEN/8, x7, x2, x4) + +inst_2255: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xbf0; + valaddr_reg:x6; val_offset:4460*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4460*FLEN/8, x7, x2, x4) + +inst_2256: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbf0; op2val:0x400; + valaddr_reg:x6; val_offset:4462*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4462*FLEN/8, x7, x2, x4) + +inst_2257: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x80f; + valaddr_reg:x6; val_offset:4464*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4464*FLEN/8, x7, x2, x4) + +inst_2258: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x00f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x80f; op2val:0x400; + valaddr_reg:x6; val_offset:4466*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4466*FLEN/8, x7, x2, x4) + +inst_2259: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xbf8; + valaddr_reg:x6; val_offset:4468*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4468*FLEN/8, x7, x2, x4) + +inst_2260: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbf8; op2val:0x400; + valaddr_reg:x6; val_offset:4470*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4470*FLEN/8, x7, x2, x4) + +inst_2261: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x807; + valaddr_reg:x6; val_offset:4472*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4472*FLEN/8, x7, x2, x4) + +inst_2262: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x807; op2val:0x400; + valaddr_reg:x6; val_offset:4474*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4474*FLEN/8, x7, x2, x4) + +inst_2263: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xbfc; + valaddr_reg:x6; val_offset:4476*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4476*FLEN/8, x7, x2, x4) + +inst_2264: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbfc; op2val:0x400; + valaddr_reg:x6; val_offset:4478*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4478*FLEN/8, x7, x2, x4) + +inst_2265: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x803; + valaddr_reg:x6; val_offset:4480*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4480*FLEN/8, x7, x2, x4) + +inst_2266: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x003 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x803; op2val:0x400; + valaddr_reg:x6; val_offset:4482*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4482*FLEN/8, x7, x2, x4) + +inst_2267: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xbfe; + valaddr_reg:x6; val_offset:4484*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4484*FLEN/8, x7, x2, x4) + +inst_2268: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xbfe; op2val:0x400; + valaddr_reg:x6; val_offset:4486*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4486*FLEN/8, x7, x2, x4) + +inst_2269: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x801; + valaddr_reg:x6; val_offset:4488*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4488*FLEN/8, x7, x2, x4) + +inst_2270: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x801; op2val:0x400; + valaddr_reg:x6; val_offset:4490*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4490*FLEN/8, x7, x2, x4) + +inst_2271: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xc00; + valaddr_reg:x6; val_offset:4492*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4492*FLEN/8, x7, x2, x4) + +inst_2272: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc00; op2val:0x400; + valaddr_reg:x6; val_offset:4494*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4494*FLEN/8, x7, x2, x4) + +inst_2273: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xfff; + valaddr_reg:x6; val_offset:4496*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4496*FLEN/8, x7, x2, x4) + +inst_2274: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfff; op2val:0x400; + valaddr_reg:x6; val_offset:4498*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4498*FLEN/8, x7, x2, x4) + +inst_2275: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xe00; + valaddr_reg:x6; val_offset:4500*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4500*FLEN/8, x7, x2, x4) + +inst_2276: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xe00; op2val:0x400; + valaddr_reg:x6; val_offset:4502*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4502*FLEN/8, x7, x2, x4) + +inst_2277: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xdff; + valaddr_reg:x6; val_offset:4504*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4504*FLEN/8, x7, x2, x4) + +inst_2278: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xdff; op2val:0x400; + valaddr_reg:x6; val_offset:4506*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4506*FLEN/8, x7, x2, x4) + +inst_2279: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xf00; + valaddr_reg:x6; val_offset:4508*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4508*FLEN/8, x7, x2, x4) + +inst_2280: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x300 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf00; op2val:0x400; + valaddr_reg:x6; val_offset:4510*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4510*FLEN/8, x7, x2, x4) + +inst_2281: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xcff; + valaddr_reg:x6; val_offset:4512*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4512*FLEN/8, x7, x2, x4) + +inst_2282: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xcff; op2val:0x400; + valaddr_reg:x6; val_offset:4514*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4514*FLEN/8, x7, x2, x4) + +inst_2283: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xf80; + valaddr_reg:x6; val_offset:4516*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4516*FLEN/8, x7, x2, x4) + +inst_2284: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x380 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf80; op2val:0x400; + valaddr_reg:x6; val_offset:4518*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4518*FLEN/8, x7, x2, x4) + +inst_2285: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xc7f; + valaddr_reg:x6; val_offset:4520*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4520*FLEN/8, x7, x2, x4) + +inst_2286: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x07f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc7f; op2val:0x400; + valaddr_reg:x6; val_offset:4522*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4522*FLEN/8, x7, x2, x4) + +inst_2287: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xfc0; + valaddr_reg:x6; val_offset:4524*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4524*FLEN/8, x7, x2, x4) + +inst_2288: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc0; op2val:0x400; + valaddr_reg:x6; val_offset:4526*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4526*FLEN/8, x7, x2, x4) + +inst_2289: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xc3f; + valaddr_reg:x6; val_offset:4528*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4528*FLEN/8, x7, x2, x4) + +inst_2290: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc3f; op2val:0x400; + valaddr_reg:x6; val_offset:4530*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4530*FLEN/8, x7, x2, x4) + +inst_2291: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xfe0; + valaddr_reg:x6; val_offset:4532*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4532*FLEN/8, x7, x2, x4) + +inst_2292: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe0; op2val:0x400; + valaddr_reg:x6; val_offset:4534*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4534*FLEN/8, x7, x2, x4) + +inst_2293: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xc1f; + valaddr_reg:x6; val_offset:4536*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4536*FLEN/8, x7, x2, x4) + +inst_2294: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x01f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc1f; op2val:0x400; + valaddr_reg:x6; val_offset:4538*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4538*FLEN/8, x7, x2, x4) + +inst_2295: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xff0; + valaddr_reg:x6; val_offset:4540*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4540*FLEN/8, x7, x2, x4) + +inst_2296: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xff0; op2val:0x400; + valaddr_reg:x6; val_offset:4542*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4542*FLEN/8, x7, x2, x4) + +inst_2297: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xc0f; + valaddr_reg:x6; val_offset:4544*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4544*FLEN/8, x7, x2, x4) + +inst_2298: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x00f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc0f; op2val:0x400; + valaddr_reg:x6; val_offset:4546*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4546*FLEN/8, x7, x2, x4) + +inst_2299: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xff8; + valaddr_reg:x6; val_offset:4548*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4548*FLEN/8, x7, x2, x4) + +inst_2300: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xff8; op2val:0x400; + valaddr_reg:x6; val_offset:4550*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4550*FLEN/8, x7, x2, x4) + +inst_2301: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xc07; + valaddr_reg:x6; val_offset:4552*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4552*FLEN/8, x7, x2, x4) + +inst_2302: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc07; op2val:0x400; + valaddr_reg:x6; val_offset:4554*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4554*FLEN/8, x7, x2, x4) + +inst_2303: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xffc; + valaddr_reg:x6; val_offset:4556*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4556*FLEN/8, x7, x2, x4) + +inst_2304: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xffc; op2val:0x400; + valaddr_reg:x6; val_offset:4558*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4558*FLEN/8, x7, x2, x4) + +inst_2305: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xc03; + valaddr_reg:x6; val_offset:4560*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4560*FLEN/8, x7, x2, x4) + +inst_2306: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x003 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc03; op2val:0x400; + valaddr_reg:x6; val_offset:4562*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4562*FLEN/8, x7, x2, x4) + +inst_2307: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xffe; + valaddr_reg:x6; val_offset:4564*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4564*FLEN/8, x7, x2, x4) + +inst_2308: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xffe; op2val:0x400; + valaddr_reg:x6; val_offset:4566*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4566*FLEN/8, x7, x2, x4) + +inst_2309: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xc01; + valaddr_reg:x6; val_offset:4568*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4568*FLEN/8, x7, x2, x4) + +inst_2310: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc01; op2val:0x400; + valaddr_reg:x6; val_offset:4570*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4570*FLEN/8, x7, x2, x4) + +inst_2311: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x1000; + valaddr_reg:x6; val_offset:4572*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4572*FLEN/8, x7, x2, x4) + +inst_2312: +// fs1 == 0 and fe1 == 0x04 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1000; op2val:0x400; + valaddr_reg:x6; val_offset:4574*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4574*FLEN/8, x7, x2, x4) + +inst_2313: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x13ff; + valaddr_reg:x6; val_offset:4576*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4576*FLEN/8, x7, x2, x4) + +inst_2314: +// fs1 == 0 and fe1 == 0x04 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x13ff; op2val:0x400; + valaddr_reg:x6; val_offset:4578*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4578*FLEN/8, x7, x2, x4) + +inst_2315: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x1200; + valaddr_reg:x6; val_offset:4580*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4580*FLEN/8, x7, x2, x4) + +inst_2316: +// fs1 == 0 and fe1 == 0x04 and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1200; op2val:0x400; + valaddr_reg:x6; val_offset:4582*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4582*FLEN/8, x7, x2, x4) + +inst_2317: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x11ff; + valaddr_reg:x6; val_offset:4584*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4584*FLEN/8, x7, x2, x4) + +inst_2318: +// fs1 == 0 and fe1 == 0x04 and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x11ff; op2val:0x400; + valaddr_reg:x6; val_offset:4586*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4586*FLEN/8, x7, x2, x4) + +inst_2319: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x1300; + valaddr_reg:x6; val_offset:4588*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4588*FLEN/8, x7, x2, x4) + +inst_2320: +// fs1 == 0 and fe1 == 0x04 and fm1 == 0x300 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1300; op2val:0x400; + valaddr_reg:x6; val_offset:4590*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4590*FLEN/8, x7, x2, x4) + +inst_2321: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x10ff; + valaddr_reg:x6; val_offset:4592*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4592*FLEN/8, x7, x2, x4) + +inst_2322: +// fs1 == 0 and fe1 == 0x04 and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x10ff; op2val:0x400; + valaddr_reg:x6; val_offset:4594*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4594*FLEN/8, x7, x2, x4) + +inst_2323: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x1380; + valaddr_reg:x6; val_offset:4596*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4596*FLEN/8, x7, x2, x4) + +inst_2324: +// fs1 == 0 and fe1 == 0x04 and fm1 == 0x380 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1380; op2val:0x400; + valaddr_reg:x6; val_offset:4598*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4598*FLEN/8, x7, x2, x4) + +inst_2325: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x107f; + valaddr_reg:x6; val_offset:4600*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4600*FLEN/8, x7, x2, x4) + +inst_2326: +// fs1 == 0 and fe1 == 0x04 and fm1 == 0x07f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x107f; op2val:0x400; + valaddr_reg:x6; val_offset:4602*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4602*FLEN/8, x7, x2, x4) + +inst_2327: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x13c0; + valaddr_reg:x6; val_offset:4604*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4604*FLEN/8, x7, x2, x4) + +inst_2328: +// fs1 == 0 and fe1 == 0x04 and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x13c0; op2val:0x400; + valaddr_reg:x6; val_offset:4606*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4606*FLEN/8, x7, x2, x4) + +inst_2329: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x103f; + valaddr_reg:x6; val_offset:4608*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4608*FLEN/8, x7, x2, x4) + +inst_2330: +// fs1 == 0 and fe1 == 0x04 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x103f; op2val:0x400; + valaddr_reg:x6; val_offset:4610*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4610*FLEN/8, x7, x2, x4) + +inst_2331: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x13e0; + valaddr_reg:x6; val_offset:4612*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4612*FLEN/8, x7, x2, x4) + +inst_2332: +// fs1 == 0 and fe1 == 0x04 and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x13e0; op2val:0x400; + valaddr_reg:x6; val_offset:4614*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4614*FLEN/8, x7, x2, x4) +RVTEST_SIGBASE(x2,signature_x2_20) + +inst_2333: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x101f; + valaddr_reg:x6; val_offset:4616*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4616*FLEN/8, x7, x2, x4) + +inst_2334: +// fs1 == 0 and fe1 == 0x04 and fm1 == 0x01f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x101f; op2val:0x400; + valaddr_reg:x6; val_offset:4618*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4618*FLEN/8, x7, x2, x4) + +inst_2335: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x13f0; + valaddr_reg:x6; val_offset:4620*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4620*FLEN/8, x7, x2, x4) + +inst_2336: +// fs1 == 0 and fe1 == 0x04 and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x13f0; op2val:0x400; + valaddr_reg:x6; val_offset:4622*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4622*FLEN/8, x7, x2, x4) + +inst_2337: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x100f; + valaddr_reg:x6; val_offset:4624*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4624*FLEN/8, x7, x2, x4) + +inst_2338: +// fs1 == 0 and fe1 == 0x04 and fm1 == 0x00f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x100f; op2val:0x400; + valaddr_reg:x6; val_offset:4626*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4626*FLEN/8, x7, x2, x4) + +inst_2339: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x13f8; + valaddr_reg:x6; val_offset:4628*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4628*FLEN/8, x7, x2, x4) + +inst_2340: +// fs1 == 0 and fe1 == 0x04 and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x13f8; op2val:0x400; + valaddr_reg:x6; val_offset:4630*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4630*FLEN/8, x7, x2, x4) + +inst_2341: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x1007; + valaddr_reg:x6; val_offset:4632*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4632*FLEN/8, x7, x2, x4) + +inst_2342: +// fs1 == 0 and fe1 == 0x04 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1007; op2val:0x400; + valaddr_reg:x6; val_offset:4634*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4634*FLEN/8, x7, x2, x4) + +inst_2343: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x13fc; + valaddr_reg:x6; val_offset:4636*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4636*FLEN/8, x7, x2, x4) + +inst_2344: +// fs1 == 0 and fe1 == 0x04 and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x13fc; op2val:0x400; + valaddr_reg:x6; val_offset:4638*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4638*FLEN/8, x7, x2, x4) + +inst_2345: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x1003; + valaddr_reg:x6; val_offset:4640*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4640*FLEN/8, x7, x2, x4) + +inst_2346: +// fs1 == 0 and fe1 == 0x04 and fm1 == 0x003 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1003; op2val:0x400; + valaddr_reg:x6; val_offset:4642*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4642*FLEN/8, x7, x2, x4) + +inst_2347: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x13fe; + valaddr_reg:x6; val_offset:4644*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4644*FLEN/8, x7, x2, x4) + +inst_2348: +// fs1 == 0 and fe1 == 0x04 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x13fe; op2val:0x400; + valaddr_reg:x6; val_offset:4646*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4646*FLEN/8, x7, x2, x4) + +inst_2349: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x1001; + valaddr_reg:x6; val_offset:4648*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4648*FLEN/8, x7, x2, x4) + +inst_2350: +// fs1 == 0 and fe1 == 0x04 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1001; op2val:0x400; + valaddr_reg:x6; val_offset:4650*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4650*FLEN/8, x7, x2, x4) + +inst_2351: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8200; + valaddr_reg:x6; val_offset:4652*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4652*FLEN/8, x7, x2, x4) + +inst_2352: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8200; op2val:0x8400; + valaddr_reg:x6; val_offset:4654*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4654*FLEN/8, x7, x2, x4) + +inst_2353: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x81ff; + valaddr_reg:x6; val_offset:4656*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4656*FLEN/8, x7, x2, x4) + +inst_2354: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x81ff; op2val:0x8400; + valaddr_reg:x6; val_offset:4658*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4658*FLEN/8, x7, x2, x4) + +inst_2355: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8300; + valaddr_reg:x6; val_offset:4660*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4660*FLEN/8, x7, x2, x4) + +inst_2356: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x300 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8300; op2val:0x8400; + valaddr_reg:x6; val_offset:4662*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4662*FLEN/8, x7, x2, x4) + +inst_2357: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x80ff; + valaddr_reg:x6; val_offset:4664*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4664*FLEN/8, x7, x2, x4) + +inst_2358: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x80ff; op2val:0x8400; + valaddr_reg:x6; val_offset:4666*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4666*FLEN/8, x7, x2, x4) + +inst_2359: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8380; + valaddr_reg:x6; val_offset:4668*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4668*FLEN/8, x7, x2, x4) + +inst_2360: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x380 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8380; op2val:0x8400; + valaddr_reg:x6; val_offset:4670*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4670*FLEN/8, x7, x2, x4) + +inst_2361: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x807f; + valaddr_reg:x6; val_offset:4672*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4672*FLEN/8, x7, x2, x4) + +inst_2362: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x07f and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x807f; op2val:0x8400; + valaddr_reg:x6; val_offset:4674*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4674*FLEN/8, x7, x2, x4) + +inst_2363: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x83c0; + valaddr_reg:x6; val_offset:4676*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4676*FLEN/8, x7, x2, x4) + +inst_2364: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83c0; op2val:0x8400; + valaddr_reg:x6; val_offset:4678*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4678*FLEN/8, x7, x2, x4) + +inst_2365: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x803f; + valaddr_reg:x6; val_offset:4680*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4680*FLEN/8, x7, x2, x4) + +inst_2366: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x803f; op2val:0x8400; + valaddr_reg:x6; val_offset:4682*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4682*FLEN/8, x7, x2, x4) + +inst_2367: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x83e0; + valaddr_reg:x6; val_offset:4684*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4684*FLEN/8, x7, x2, x4) + +inst_2368: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83e0; op2val:0x8400; + valaddr_reg:x6; val_offset:4686*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4686*FLEN/8, x7, x2, x4) + +inst_2369: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x801f; + valaddr_reg:x6; val_offset:4688*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4688*FLEN/8, x7, x2, x4) + +inst_2370: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x01f and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x801f; op2val:0x8400; + valaddr_reg:x6; val_offset:4690*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4690*FLEN/8, x7, x2, x4) + +inst_2371: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x83f0; + valaddr_reg:x6; val_offset:4692*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4692*FLEN/8, x7, x2, x4) + +inst_2372: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83f0; op2val:0x8400; + valaddr_reg:x6; val_offset:4694*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4694*FLEN/8, x7, x2, x4) + +inst_2373: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x800f; + valaddr_reg:x6; val_offset:4696*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4696*FLEN/8, x7, x2, x4) + +inst_2374: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x00f and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x800f; op2val:0x8400; + valaddr_reg:x6; val_offset:4698*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4698*FLEN/8, x7, x2, x4) + +inst_2375: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x83f8; + valaddr_reg:x6; val_offset:4700*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4700*FLEN/8, x7, x2, x4) + +inst_2376: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83f8; op2val:0x8400; + valaddr_reg:x6; val_offset:4702*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4702*FLEN/8, x7, x2, x4) + +inst_2377: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8007; + valaddr_reg:x6; val_offset:4704*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4704*FLEN/8, x7, x2, x4) + +inst_2378: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8007; op2val:0x8400; + valaddr_reg:x6; val_offset:4706*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4706*FLEN/8, x7, x2, x4) + +inst_2379: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x83fc; + valaddr_reg:x6; val_offset:4708*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4708*FLEN/8, x7, x2, x4) + +inst_2380: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fc; op2val:0x8400; + valaddr_reg:x6; val_offset:4710*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4710*FLEN/8, x7, x2, x4) + +inst_2381: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8003; + valaddr_reg:x6; val_offset:4712*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4712*FLEN/8, x7, x2, x4) + +inst_2382: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8003; op2val:0x8400; + valaddr_reg:x6; val_offset:4714*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4714*FLEN/8, x7, x2, x4) + +inst_2383: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x83fe; + valaddr_reg:x6; val_offset:4716*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4716*FLEN/8, x7, x2, x4) + +inst_2384: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x8400; + valaddr_reg:x6; val_offset:4718*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4718*FLEN/8, x7, x2, x4) + +inst_2385: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x87fe; + valaddr_reg:x6; val_offset:4720*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4720*FLEN/8, x7, x2, x4) + +inst_2386: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x87fe; op2val:0x8400; + valaddr_reg:x6; val_offset:4722*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4722*FLEN/8, x7, x2, x4) + +inst_2387: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8401; + valaddr_reg:x6; val_offset:4724*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4724*FLEN/8, x7, x2, x4) + +inst_2388: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8401; op2val:0x8400; + valaddr_reg:x6; val_offset:4726*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4726*FLEN/8, x7, x2, x4) + +inst_2389: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x1b6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x85b6; + valaddr_reg:x6; val_offset:4728*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4728*FLEN/8, x7, x2, x4) + +inst_2390: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x1b6 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x85b6; op2val:0x8400; + valaddr_reg:x6; val_offset:4730*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4730*FLEN/8, x7, x2, x4) + +inst_2391: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x36d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x876d; + valaddr_reg:x6; val_offset:4732*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4732*FLEN/8, x7, x2, x4) + +inst_2392: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x36d and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x876d; op2val:0x8400; + valaddr_reg:x6; val_offset:4734*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4734*FLEN/8, x7, x2, x4) + +inst_2393: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0cc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x84cc; + valaddr_reg:x6; val_offset:4736*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4736*FLEN/8, x7, x2, x4) + +inst_2394: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x0cc and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x84cc; op2val:0x8400; + valaddr_reg:x6; val_offset:4738*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4738*FLEN/8, x7, x2, x4) + +inst_2395: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x333 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8733; + valaddr_reg:x6; val_offset:4740*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4740*FLEN/8, x7, x2, x4) + +inst_2396: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x333 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8733; op2val:0x8400; + valaddr_reg:x6; val_offset:4742*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4742*FLEN/8, x7, x2, x4) + +inst_2397: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x1dd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x85dd; + valaddr_reg:x6; val_offset:4744*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4744*FLEN/8, x7, x2, x4) + +inst_2398: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x1dd and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x85dd; op2val:0x8400; + valaddr_reg:x6; val_offset:4746*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4746*FLEN/8, x7, x2, x4) + +inst_2399: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x222 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8622; + valaddr_reg:x6; val_offset:4748*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4748*FLEN/8, x7, x2, x4) + +inst_2400: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x222 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8622; op2val:0x8400; + valaddr_reg:x6; val_offset:4750*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4750*FLEN/8, x7, x2, x4) + +inst_2401: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x124 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8524; + valaddr_reg:x6; val_offset:4752*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4752*FLEN/8, x7, x2, x4) + +inst_2402: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x124 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8524; op2val:0x8400; + valaddr_reg:x6; val_offset:4754*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4754*FLEN/8, x7, x2, x4) + +inst_2403: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x2db and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x86db; + valaddr_reg:x6; val_offset:4756*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4756*FLEN/8, x7, x2, x4) + +inst_2404: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x2db and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x86db; op2val:0x8400; + valaddr_reg:x6; val_offset:4758*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4758*FLEN/8, x7, x2, x4) + +inst_2405: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x199 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8599; + valaddr_reg:x6; val_offset:4760*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4760*FLEN/8, x7, x2, x4) + +inst_2406: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x199 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8599; op2val:0x8400; + valaddr_reg:x6; val_offset:4762*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4762*FLEN/8, x7, x2, x4) + +inst_2407: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x266 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8666; + valaddr_reg:x6; val_offset:4764*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4764*FLEN/8, x7, x2, x4) + +inst_2408: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x266 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8666; op2val:0x8400; + valaddr_reg:x6; val_offset:4766*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4766*FLEN/8, x7, x2, x4) + +inst_2409: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x4800; + valaddr_reg:x6; val_offset:4768*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4768*FLEN/8, x7, x2, x4) + +inst_2410: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4800; op2val:0x8400; + valaddr_reg:x6; val_offset:4770*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4770*FLEN/8, x7, x2, x4) + +inst_2411: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x4bff; + valaddr_reg:x6; val_offset:4772*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4772*FLEN/8, x7, x2, x4) + +inst_2412: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4bff; op2val:0x8400; + valaddr_reg:x6; val_offset:4774*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4774*FLEN/8, x7, x2, x4) + +inst_2413: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x4a00; + valaddr_reg:x6; val_offset:4776*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4776*FLEN/8, x7, x2, x4) + +inst_2414: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4a00; op2val:0x8400; + valaddr_reg:x6; val_offset:4778*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4778*FLEN/8, x7, x2, x4) + +inst_2415: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x49ff; + valaddr_reg:x6; val_offset:4780*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4780*FLEN/8, x7, x2, x4) + +inst_2416: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x49ff; op2val:0x8400; + valaddr_reg:x6; val_offset:4782*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4782*FLEN/8, x7, x2, x4) + +inst_2417: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x4b00; + valaddr_reg:x6; val_offset:4784*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4784*FLEN/8, x7, x2, x4) + +inst_2418: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x300 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4b00; op2val:0x8400; + valaddr_reg:x6; val_offset:4786*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4786*FLEN/8, x7, x2, x4) + +inst_2419: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x48ff; + valaddr_reg:x6; val_offset:4788*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4788*FLEN/8, x7, x2, x4) + +inst_2420: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x48ff; op2val:0x8400; + valaddr_reg:x6; val_offset:4790*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4790*FLEN/8, x7, x2, x4) + +inst_2421: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x4b80; + valaddr_reg:x6; val_offset:4792*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4792*FLEN/8, x7, x2, x4) + +inst_2422: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x380 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4b80; op2val:0x8400; + valaddr_reg:x6; val_offset:4794*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4794*FLEN/8, x7, x2, x4) + +inst_2423: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x487f; + valaddr_reg:x6; val_offset:4796*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4796*FLEN/8, x7, x2, x4) + +inst_2424: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x07f and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x487f; op2val:0x8400; + valaddr_reg:x6; val_offset:4798*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4798*FLEN/8, x7, x2, x4) + +inst_2425: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x4bc0; + valaddr_reg:x6; val_offset:4800*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4800*FLEN/8, x7, x2, x4) + +inst_2426: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4bc0; op2val:0x8400; + valaddr_reg:x6; val_offset:4802*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4802*FLEN/8, x7, x2, x4) + +inst_2427: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x483f; + valaddr_reg:x6; val_offset:4804*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4804*FLEN/8, x7, x2, x4) + +inst_2428: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x483f; op2val:0x8400; + valaddr_reg:x6; val_offset:4806*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4806*FLEN/8, x7, x2, x4) + +inst_2429: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x4be0; + valaddr_reg:x6; val_offset:4808*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4808*FLEN/8, x7, x2, x4) + +inst_2430: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4be0; op2val:0x8400; + valaddr_reg:x6; val_offset:4810*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4810*FLEN/8, x7, x2, x4) + +inst_2431: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x481f; + valaddr_reg:x6; val_offset:4812*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4812*FLEN/8, x7, x2, x4) + +inst_2432: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x01f and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x481f; op2val:0x8400; + valaddr_reg:x6; val_offset:4814*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4814*FLEN/8, x7, x2, x4) + +inst_2433: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x4bf0; + valaddr_reg:x6; val_offset:4816*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4816*FLEN/8, x7, x2, x4) + +inst_2434: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4bf0; op2val:0x8400; + valaddr_reg:x6; val_offset:4818*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4818*FLEN/8, x7, x2, x4) + +inst_2435: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x480f; + valaddr_reg:x6; val_offset:4820*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4820*FLEN/8, x7, x2, x4) + +inst_2436: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x00f and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x480f; op2val:0x8400; + valaddr_reg:x6; val_offset:4822*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4822*FLEN/8, x7, x2, x4) + +inst_2437: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x4bf8; + valaddr_reg:x6; val_offset:4824*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4824*FLEN/8, x7, x2, x4) + +inst_2438: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4bf8; op2val:0x8400; + valaddr_reg:x6; val_offset:4826*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4826*FLEN/8, x7, x2, x4) + +inst_2439: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x4807; + valaddr_reg:x6; val_offset:4828*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4828*FLEN/8, x7, x2, x4) + +inst_2440: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4807; op2val:0x8400; + valaddr_reg:x6; val_offset:4830*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4830*FLEN/8, x7, x2, x4) + +inst_2441: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x4bfc; + valaddr_reg:x6; val_offset:4832*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4832*FLEN/8, x7, x2, x4) + +inst_2442: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4bfc; op2val:0x8400; + valaddr_reg:x6; val_offset:4834*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4834*FLEN/8, x7, x2, x4) + +inst_2443: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x4803; + valaddr_reg:x6; val_offset:4836*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4836*FLEN/8, x7, x2, x4) + +inst_2444: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4803; op2val:0x8400; + valaddr_reg:x6; val_offset:4838*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4838*FLEN/8, x7, x2, x4) + +inst_2445: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x4bfe; + valaddr_reg:x6; val_offset:4840*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4840*FLEN/8, x7, x2, x4) + +inst_2446: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4bfe; op2val:0x8400; + valaddr_reg:x6; val_offset:4842*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4842*FLEN/8, x7, x2, x4) + +inst_2447: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x4801; + valaddr_reg:x6; val_offset:4844*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4844*FLEN/8, x7, x2, x4) + +inst_2448: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4801; op2val:0x8400; + valaddr_reg:x6; val_offset:4846*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4846*FLEN/8, x7, x2, x4) + +inst_2449: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8400; + valaddr_reg:x6; val_offset:4848*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4848*FLEN/8, x7, x2, x4) + +inst_2450: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x87ff; + valaddr_reg:x6; val_offset:4850*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4850*FLEN/8, x7, x2, x4) + +inst_2451: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x87ff; op2val:0x8400; + valaddr_reg:x6; val_offset:4852*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4852*FLEN/8, x7, x2, x4) + +inst_2452: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8600; + valaddr_reg:x6; val_offset:4854*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4854*FLEN/8, x7, x2, x4) + +inst_2453: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8600; op2val:0x8400; + valaddr_reg:x6; val_offset:4856*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4856*FLEN/8, x7, x2, x4) + +inst_2454: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x85ff; + valaddr_reg:x6; val_offset:4858*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4858*FLEN/8, x7, x2, x4) + +inst_2455: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x85ff; op2val:0x8400; + valaddr_reg:x6; val_offset:4860*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4860*FLEN/8, x7, x2, x4) + +inst_2456: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8700; + valaddr_reg:x6; val_offset:4862*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4862*FLEN/8, x7, x2, x4) + +inst_2457: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x300 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8700; op2val:0x8400; + valaddr_reg:x6; val_offset:4864*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4864*FLEN/8, x7, x2, x4) + +inst_2458: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x84ff; + valaddr_reg:x6; val_offset:4866*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4866*FLEN/8, x7, x2, x4) + +inst_2459: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x84ff; op2val:0x8400; + valaddr_reg:x6; val_offset:4868*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4868*FLEN/8, x7, x2, x4) + +inst_2460: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8780; + valaddr_reg:x6; val_offset:4870*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4870*FLEN/8, x7, x2, x4) +RVTEST_SIGBASE(x2,signature_x2_21) + +inst_2461: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x380 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8780; op2val:0x8400; + valaddr_reg:x6; val_offset:4872*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4872*FLEN/8, x7, x2, x4) + +inst_2462: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x847f; + valaddr_reg:x6; val_offset:4874*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4874*FLEN/8, x7, x2, x4) + +inst_2463: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x07f and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x847f; op2val:0x8400; + valaddr_reg:x6; val_offset:4876*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4876*FLEN/8, x7, x2, x4) + +inst_2464: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x87c0; + valaddr_reg:x6; val_offset:4878*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4878*FLEN/8, x7, x2, x4) + +inst_2465: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x87c0; op2val:0x8400; + valaddr_reg:x6; val_offset:4880*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4880*FLEN/8, x7, x2, x4) + +inst_2466: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x843f; + valaddr_reg:x6; val_offset:4882*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4882*FLEN/8, x7, x2, x4) + +inst_2467: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x843f; op2val:0x8400; + valaddr_reg:x6; val_offset:4884*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4884*FLEN/8, x7, x2, x4) + +inst_2468: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x87e0; + valaddr_reg:x6; val_offset:4886*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4886*FLEN/8, x7, x2, x4) + +inst_2469: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x87e0; op2val:0x8400; + valaddr_reg:x6; val_offset:4888*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4888*FLEN/8, x7, x2, x4) + +inst_2470: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x841f; + valaddr_reg:x6; val_offset:4890*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4890*FLEN/8, x7, x2, x4) + +inst_2471: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x01f and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x841f; op2val:0x8400; + valaddr_reg:x6; val_offset:4892*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4892*FLEN/8, x7, x2, x4) + +inst_2472: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x87f0; + valaddr_reg:x6; val_offset:4894*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4894*FLEN/8, x7, x2, x4) + +inst_2473: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x87f0; op2val:0x8400; + valaddr_reg:x6; val_offset:4896*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4896*FLEN/8, x7, x2, x4) + +inst_2474: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x840f; + valaddr_reg:x6; val_offset:4898*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4898*FLEN/8, x7, x2, x4) + +inst_2475: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x00f and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x840f; op2val:0x8400; + valaddr_reg:x6; val_offset:4900*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4900*FLEN/8, x7, x2, x4) + +inst_2476: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x87f8; + valaddr_reg:x6; val_offset:4902*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4902*FLEN/8, x7, x2, x4) + +inst_2477: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x87f8; op2val:0x8400; + valaddr_reg:x6; val_offset:4904*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4904*FLEN/8, x7, x2, x4) + +inst_2478: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8407; + valaddr_reg:x6; val_offset:4906*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4906*FLEN/8, x7, x2, x4) + +inst_2479: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8407; op2val:0x8400; + valaddr_reg:x6; val_offset:4908*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4908*FLEN/8, x7, x2, x4) + +inst_2480: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x87fc; + valaddr_reg:x6; val_offset:4910*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4910*FLEN/8, x7, x2, x4) + +inst_2481: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x87fc; op2val:0x8400; + valaddr_reg:x6; val_offset:4912*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4912*FLEN/8, x7, x2, x4) + +inst_2482: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8403; + valaddr_reg:x6; val_offset:4914*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4914*FLEN/8, x7, x2, x4) + +inst_2483: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8403; op2val:0x8400; + valaddr_reg:x6; val_offset:4916*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4916*FLEN/8, x7, x2, x4) + +inst_2484: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8800; + valaddr_reg:x6; val_offset:4918*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4918*FLEN/8, x7, x2, x4) + +inst_2485: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8800; op2val:0x8400; + valaddr_reg:x6; val_offset:4920*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4920*FLEN/8, x7, x2, x4) + +inst_2486: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8bff; + valaddr_reg:x6; val_offset:4922*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4922*FLEN/8, x7, x2, x4) + +inst_2487: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8bff; op2val:0x8400; + valaddr_reg:x6; val_offset:4924*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4924*FLEN/8, x7, x2, x4) + +inst_2488: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8a00; + valaddr_reg:x6; val_offset:4926*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4926*FLEN/8, x7, x2, x4) + +inst_2489: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8a00; op2val:0x8400; + valaddr_reg:x6; val_offset:4928*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4928*FLEN/8, x7, x2, x4) + +inst_2490: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x89ff; + valaddr_reg:x6; val_offset:4930*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4930*FLEN/8, x7, x2, x4) + +inst_2491: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x89ff; op2val:0x8400; + valaddr_reg:x6; val_offset:4932*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4932*FLEN/8, x7, x2, x4) + +inst_2492: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8b00; + valaddr_reg:x6; val_offset:4934*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4934*FLEN/8, x7, x2, x4) + +inst_2493: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x300 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8b00; op2val:0x8400; + valaddr_reg:x6; val_offset:4936*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4936*FLEN/8, x7, x2, x4) + +inst_2494: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x88ff; + valaddr_reg:x6; val_offset:4938*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4938*FLEN/8, x7, x2, x4) + +inst_2495: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x88ff; op2val:0x8400; + valaddr_reg:x6; val_offset:4940*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4940*FLEN/8, x7, x2, x4) + +inst_2496: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8b80; + valaddr_reg:x6; val_offset:4942*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4942*FLEN/8, x7, x2, x4) + +inst_2497: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x380 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8b80; op2val:0x8400; + valaddr_reg:x6; val_offset:4944*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4944*FLEN/8, x7, x2, x4) + +inst_2498: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x887f; + valaddr_reg:x6; val_offset:4946*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4946*FLEN/8, x7, x2, x4) + +inst_2499: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x07f and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x887f; op2val:0x8400; + valaddr_reg:x6; val_offset:4948*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4948*FLEN/8, x7, x2, x4) + +inst_2500: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8bc0; + valaddr_reg:x6; val_offset:4950*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4950*FLEN/8, x7, x2, x4) + +inst_2501: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8bc0; op2val:0x8400; + valaddr_reg:x6; val_offset:4952*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4952*FLEN/8, x7, x2, x4) + +inst_2502: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x883f; + valaddr_reg:x6; val_offset:4954*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4954*FLEN/8, x7, x2, x4) + +inst_2503: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x883f; op2val:0x8400; + valaddr_reg:x6; val_offset:4956*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4956*FLEN/8, x7, x2, x4) + +inst_2504: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8be0; + valaddr_reg:x6; val_offset:4958*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4958*FLEN/8, x7, x2, x4) + +inst_2505: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8be0; op2val:0x8400; + valaddr_reg:x6; val_offset:4960*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4960*FLEN/8, x7, x2, x4) + +inst_2506: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x881f; + valaddr_reg:x6; val_offset:4962*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4962*FLEN/8, x7, x2, x4) + +inst_2507: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x01f and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x881f; op2val:0x8400; + valaddr_reg:x6; val_offset:4964*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4964*FLEN/8, x7, x2, x4) + +inst_2508: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8bf0; + valaddr_reg:x6; val_offset:4966*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4966*FLEN/8, x7, x2, x4) + +inst_2509: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8bf0; op2val:0x8400; + valaddr_reg:x6; val_offset:4968*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4968*FLEN/8, x7, x2, x4) + +inst_2510: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x880f; + valaddr_reg:x6; val_offset:4970*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4970*FLEN/8, x7, x2, x4) + +inst_2511: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x00f and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x880f; op2val:0x8400; + valaddr_reg:x6; val_offset:4972*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4972*FLEN/8, x7, x2, x4) + +inst_2512: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8bf8; + valaddr_reg:x6; val_offset:4974*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4974*FLEN/8, x7, x2, x4) + +inst_2513: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8bf8; op2val:0x8400; + valaddr_reg:x6; val_offset:4976*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4976*FLEN/8, x7, x2, x4) + +inst_2514: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8807; + valaddr_reg:x6; val_offset:4978*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4978*FLEN/8, x7, x2, x4) + +inst_2515: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8807; op2val:0x8400; + valaddr_reg:x6; val_offset:4980*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4980*FLEN/8, x7, x2, x4) + +inst_2516: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8bfc; + valaddr_reg:x6; val_offset:4982*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4982*FLEN/8, x7, x2, x4) + +inst_2517: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8bfc; op2val:0x8400; + valaddr_reg:x6; val_offset:4984*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4984*FLEN/8, x7, x2, x4) + +inst_2518: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8803; + valaddr_reg:x6; val_offset:4986*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4986*FLEN/8, x7, x2, x4) + +inst_2519: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8803; op2val:0x8400; + valaddr_reg:x6; val_offset:4988*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4988*FLEN/8, x7, x2, x4) + +inst_2520: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8bfe; + valaddr_reg:x6; val_offset:4990*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4990*FLEN/8, x7, x2, x4) + +inst_2521: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8bfe; op2val:0x8400; + valaddr_reg:x6; val_offset:4992*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4992*FLEN/8, x7, x2, x4) + +inst_2522: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8801; + valaddr_reg:x6; val_offset:4994*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4994*FLEN/8, x7, x2, x4) + +inst_2523: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8801; op2val:0x8400; + valaddr_reg:x6; val_offset:4996*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4996*FLEN/8, x7, x2, x4) + +inst_2524: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8c00; + valaddr_reg:x6; val_offset:4998*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 4998*FLEN/8, x7, x2, x4) + +inst_2525: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8c00; op2val:0x8400; + valaddr_reg:x6; val_offset:5000*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5000*FLEN/8, x7, x2, x4) + +inst_2526: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8fff; + valaddr_reg:x6; val_offset:5002*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5002*FLEN/8, x7, x2, x4) + +inst_2527: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8fff; op2val:0x8400; + valaddr_reg:x6; val_offset:5004*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5004*FLEN/8, x7, x2, x4) + +inst_2528: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8e00; + valaddr_reg:x6; val_offset:5006*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5006*FLEN/8, x7, x2, x4) + +inst_2529: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8e00; op2val:0x8400; + valaddr_reg:x6; val_offset:5008*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5008*FLEN/8, x7, x2, x4) + +inst_2530: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8dff; + valaddr_reg:x6; val_offset:5010*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5010*FLEN/8, x7, x2, x4) + +inst_2531: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8dff; op2val:0x8400; + valaddr_reg:x6; val_offset:5012*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5012*FLEN/8, x7, x2, x4) + +inst_2532: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8f00; + valaddr_reg:x6; val_offset:5014*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5014*FLEN/8, x7, x2, x4) + +inst_2533: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x300 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8f00; op2val:0x8400; + valaddr_reg:x6; val_offset:5016*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5016*FLEN/8, x7, x2, x4) + +inst_2534: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8cff; + valaddr_reg:x6; val_offset:5018*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5018*FLEN/8, x7, x2, x4) + +inst_2535: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8cff; op2val:0x8400; + valaddr_reg:x6; val_offset:5020*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5020*FLEN/8, x7, x2, x4) + +inst_2536: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8f80; + valaddr_reg:x6; val_offset:5022*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5022*FLEN/8, x7, x2, x4) + +inst_2537: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x380 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8f80; op2val:0x8400; + valaddr_reg:x6; val_offset:5024*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5024*FLEN/8, x7, x2, x4) + +inst_2538: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8c7f; + valaddr_reg:x6; val_offset:5026*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5026*FLEN/8, x7, x2, x4) + +inst_2539: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x07f and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8c7f; op2val:0x8400; + valaddr_reg:x6; val_offset:5028*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5028*FLEN/8, x7, x2, x4) + +inst_2540: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8fc0; + valaddr_reg:x6; val_offset:5030*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5030*FLEN/8, x7, x2, x4) + +inst_2541: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8fc0; op2val:0x8400; + valaddr_reg:x6; val_offset:5032*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5032*FLEN/8, x7, x2, x4) + +inst_2542: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8c3f; + valaddr_reg:x6; val_offset:5034*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5034*FLEN/8, x7, x2, x4) + +inst_2543: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8c3f; op2val:0x8400; + valaddr_reg:x6; val_offset:5036*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5036*FLEN/8, x7, x2, x4) + +inst_2544: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8fe0; + valaddr_reg:x6; val_offset:5038*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5038*FLEN/8, x7, x2, x4) + +inst_2545: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8fe0; op2val:0x8400; + valaddr_reg:x6; val_offset:5040*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5040*FLEN/8, x7, x2, x4) + +inst_2546: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8c1f; + valaddr_reg:x6; val_offset:5042*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5042*FLEN/8, x7, x2, x4) + +inst_2547: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x01f and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8c1f; op2val:0x8400; + valaddr_reg:x6; val_offset:5044*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5044*FLEN/8, x7, x2, x4) + +inst_2548: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8ff0; + valaddr_reg:x6; val_offset:5046*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5046*FLEN/8, x7, x2, x4) + +inst_2549: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8ff0; op2val:0x8400; + valaddr_reg:x6; val_offset:5048*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5048*FLEN/8, x7, x2, x4) + +inst_2550: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8c0f; + valaddr_reg:x6; val_offset:5050*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5050*FLEN/8, x7, x2, x4) + +inst_2551: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x00f and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8c0f; op2val:0x8400; + valaddr_reg:x6; val_offset:5052*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5052*FLEN/8, x7, x2, x4) + +inst_2552: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8ff8; + valaddr_reg:x6; val_offset:5054*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5054*FLEN/8, x7, x2, x4) + +inst_2553: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8ff8; op2val:0x8400; + valaddr_reg:x6; val_offset:5056*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5056*FLEN/8, x7, x2, x4) + +inst_2554: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8c07; + valaddr_reg:x6; val_offset:5058*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5058*FLEN/8, x7, x2, x4) + +inst_2555: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8c07; op2val:0x8400; + valaddr_reg:x6; val_offset:5060*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5060*FLEN/8, x7, x2, x4) + +inst_2556: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8ffc; + valaddr_reg:x6; val_offset:5062*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5062*FLEN/8, x7, x2, x4) + +inst_2557: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8ffc; op2val:0x8400; + valaddr_reg:x6; val_offset:5064*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5064*FLEN/8, x7, x2, x4) + +inst_2558: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8c03; + valaddr_reg:x6; val_offset:5066*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5066*FLEN/8, x7, x2, x4) + +inst_2559: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8c03; op2val:0x8400; + valaddr_reg:x6; val_offset:5068*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5068*FLEN/8, x7, x2, x4) + +inst_2560: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8ffe; + valaddr_reg:x6; val_offset:5070*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5070*FLEN/8, x7, x2, x4) + +inst_2561: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8ffe; op2val:0x8400; + valaddr_reg:x6; val_offset:5072*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5072*FLEN/8, x7, x2, x4) + +inst_2562: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8c01; + valaddr_reg:x6; val_offset:5074*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5074*FLEN/8, x7, x2, x4) + +inst_2563: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8c01; op2val:0x8400; + valaddr_reg:x6; val_offset:5076*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5076*FLEN/8, x7, x2, x4) + +inst_2564: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x9000; + valaddr_reg:x6; val_offset:5078*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5078*FLEN/8, x7, x2, x4) + +inst_2565: +// fs1 == 1 and fe1 == 0x04 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x9000; op2val:0x8400; + valaddr_reg:x6; val_offset:5080*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5080*FLEN/8, x7, x2, x4) + +inst_2566: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x93ff; + valaddr_reg:x6; val_offset:5082*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5082*FLEN/8, x7, x2, x4) + +inst_2567: +// fs1 == 1 and fe1 == 0x04 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x93ff; op2val:0x8400; + valaddr_reg:x6; val_offset:5084*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5084*FLEN/8, x7, x2, x4) + +inst_2568: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x9200; + valaddr_reg:x6; val_offset:5086*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5086*FLEN/8, x7, x2, x4) + +inst_2569: +// fs1 == 1 and fe1 == 0x04 and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x9200; op2val:0x8400; + valaddr_reg:x6; val_offset:5088*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5088*FLEN/8, x7, x2, x4) + +inst_2570: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x91ff; + valaddr_reg:x6; val_offset:5090*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5090*FLEN/8, x7, x2, x4) + +inst_2571: +// fs1 == 1 and fe1 == 0x04 and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x91ff; op2val:0x8400; + valaddr_reg:x6; val_offset:5092*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5092*FLEN/8, x7, x2, x4) + +inst_2572: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x9300; + valaddr_reg:x6; val_offset:5094*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5094*FLEN/8, x7, x2, x4) + +inst_2573: +// fs1 == 1 and fe1 == 0x04 and fm1 == 0x300 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x9300; op2val:0x8400; + valaddr_reg:x6; val_offset:5096*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5096*FLEN/8, x7, x2, x4) + +inst_2574: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x90ff; + valaddr_reg:x6; val_offset:5098*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5098*FLEN/8, x7, x2, x4) + +inst_2575: +// fs1 == 1 and fe1 == 0x04 and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x90ff; op2val:0x8400; + valaddr_reg:x6; val_offset:5100*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5100*FLEN/8, x7, x2, x4) + +inst_2576: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x9380; + valaddr_reg:x6; val_offset:5102*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5102*FLEN/8, x7, x2, x4) + +inst_2577: +// fs1 == 1 and fe1 == 0x04 and fm1 == 0x380 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x9380; op2val:0x8400; + valaddr_reg:x6; val_offset:5104*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5104*FLEN/8, x7, x2, x4) + +inst_2578: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x907f; + valaddr_reg:x6; val_offset:5106*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5106*FLEN/8, x7, x2, x4) + +inst_2579: +// fs1 == 1 and fe1 == 0x04 and fm1 == 0x07f and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x907f; op2val:0x8400; + valaddr_reg:x6; val_offset:5108*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5108*FLEN/8, x7, x2, x4) + +inst_2580: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x93c0; + valaddr_reg:x6; val_offset:5110*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5110*FLEN/8, x7, x2, x4) + +inst_2581: +// fs1 == 1 and fe1 == 0x04 and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x93c0; op2val:0x8400; + valaddr_reg:x6; val_offset:5112*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5112*FLEN/8, x7, x2, x4) + +inst_2582: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x903f; + valaddr_reg:x6; val_offset:5114*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5114*FLEN/8, x7, x2, x4) + +inst_2583: +// fs1 == 1 and fe1 == 0x04 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x903f; op2val:0x8400; + valaddr_reg:x6; val_offset:5116*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5116*FLEN/8, x7, x2, x4) + +inst_2584: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x93e0; + valaddr_reg:x6; val_offset:5118*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5118*FLEN/8, x7, x2, x4) + +inst_2585: +// fs1 == 1 and fe1 == 0x04 and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x93e0; op2val:0x8400; + valaddr_reg:x6; val_offset:5120*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5120*FLEN/8, x7, x2, x4) + +inst_2586: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x901f; + valaddr_reg:x6; val_offset:5122*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5122*FLEN/8, x7, x2, x4) + +inst_2587: +// fs1 == 1 and fe1 == 0x04 and fm1 == 0x01f and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x901f; op2val:0x8400; + valaddr_reg:x6; val_offset:5124*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5124*FLEN/8, x7, x2, x4) + +inst_2588: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x93f0; + valaddr_reg:x6; val_offset:5126*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5126*FLEN/8, x7, x2, x4) +RVTEST_SIGBASE(x2,signature_x2_22) + +inst_2589: +// fs1 == 1 and fe1 == 0x04 and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x93f0; op2val:0x8400; + valaddr_reg:x6; val_offset:5128*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5128*FLEN/8, x7, x2, x4) + +inst_2590: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x900f; + valaddr_reg:x6; val_offset:5130*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5130*FLEN/8, x7, x2, x4) + +inst_2591: +// fs1 == 1 and fe1 == 0x04 and fm1 == 0x00f and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x900f; op2val:0x8400; + valaddr_reg:x6; val_offset:5132*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5132*FLEN/8, x7, x2, x4) + +inst_2592: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x93f8; + valaddr_reg:x6; val_offset:5134*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5134*FLEN/8, x7, x2, x4) + +inst_2593: +// fs1 == 1 and fe1 == 0x04 and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x93f8; op2val:0x8400; + valaddr_reg:x6; val_offset:5136*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5136*FLEN/8, x7, x2, x4) + +inst_2594: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x9007; + valaddr_reg:x6; val_offset:5138*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5138*FLEN/8, x7, x2, x4) + +inst_2595: +// fs1 == 1 and fe1 == 0x04 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x9007; op2val:0x8400; + valaddr_reg:x6; val_offset:5140*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5140*FLEN/8, x7, x2, x4) + +inst_2596: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x93fc; + valaddr_reg:x6; val_offset:5142*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5142*FLEN/8, x7, x2, x4) + +inst_2597: +// fs1 == 1 and fe1 == 0x04 and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x93fc; op2val:0x8400; + valaddr_reg:x6; val_offset:5144*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5144*FLEN/8, x7, x2, x4) + +inst_2598: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x9003; + valaddr_reg:x6; val_offset:5146*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5146*FLEN/8, x7, x2, x4) + +inst_2599: +// fs1 == 1 and fe1 == 0x04 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x9003; op2val:0x8400; + valaddr_reg:x6; val_offset:5148*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5148*FLEN/8, x7, x2, x4) + +inst_2600: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x93fe; + valaddr_reg:x6; val_offset:5150*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5150*FLEN/8, x7, x2, x4) + +inst_2601: +// fs1 == 1 and fe1 == 0x04 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x93fe; op2val:0x8400; + valaddr_reg:x6; val_offset:5152*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5152*FLEN/8, x7, x2, x4) + +inst_2602: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x9001; + valaddr_reg:x6; val_offset:5154*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5154*FLEN/8, x7, x2, x4) + +inst_2603: +// fs1 == 1 and fe1 == 0x04 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x9001; op2val:0x8400; + valaddr_reg:x6; val_offset:5156*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5156*FLEN/8, x7, x2, x4) + +inst_2604: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x3fff; + valaddr_reg:x6; val_offset:5158*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5158*FLEN/8, x7, x2, x4) + +inst_2605: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fff; op2val:0x7bff; + valaddr_reg:x6; val_offset:5160*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5160*FLEN/8, x7, x2, x4) + +inst_2606: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x3c00; + valaddr_reg:x6; val_offset:5162*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5162*FLEN/8, x7, x2, x4) + +inst_2607: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7bff; + valaddr_reg:x6; val_offset:5164*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5164*FLEN/8, x7, x2, x4) + +inst_2608: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x3dff; + valaddr_reg:x6; val_offset:5166*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5166*FLEN/8, x7, x2, x4) + +inst_2609: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3dff; op2val:0x7bff; + valaddr_reg:x6; val_offset:5168*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5168*FLEN/8, x7, x2, x4) + +inst_2610: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x3e00; + valaddr_reg:x6; val_offset:5170*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5170*FLEN/8, x7, x2, x4) + +inst_2611: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3e00; op2val:0x7bff; + valaddr_reg:x6; val_offset:5172*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5172*FLEN/8, x7, x2, x4) + +inst_2612: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x3cff; + valaddr_reg:x6; val_offset:5174*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5174*FLEN/8, x7, x2, x4) + +inst_2613: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3cff; op2val:0x7bff; + valaddr_reg:x6; val_offset:5176*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5176*FLEN/8, x7, x2, x4) + +inst_2614: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x3f00; + valaddr_reg:x6; val_offset:5178*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5178*FLEN/8, x7, x2, x4) + +inst_2615: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x300 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3f00; op2val:0x7bff; + valaddr_reg:x6; val_offset:5180*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5180*FLEN/8, x7, x2, x4) + +inst_2616: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x3c7f; + valaddr_reg:x6; val_offset:5182*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5182*FLEN/8, x7, x2, x4) + +inst_2617: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x07f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c7f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5184*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5184*FLEN/8, x7, x2, x4) + +inst_2618: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x3f80; + valaddr_reg:x6; val_offset:5186*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5186*FLEN/8, x7, x2, x4) + +inst_2619: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x380 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3f80; op2val:0x7bff; + valaddr_reg:x6; val_offset:5188*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5188*FLEN/8, x7, x2, x4) + +inst_2620: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x3c3f; + valaddr_reg:x6; val_offset:5190*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5190*FLEN/8, x7, x2, x4) + +inst_2621: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x03f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c3f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5192*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5192*FLEN/8, x7, x2, x4) + +inst_2622: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x3fc0; + valaddr_reg:x6; val_offset:5194*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5194*FLEN/8, x7, x2, x4) + +inst_2623: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fc0; op2val:0x7bff; + valaddr_reg:x6; val_offset:5196*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5196*FLEN/8, x7, x2, x4) + +inst_2624: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x3c1f; + valaddr_reg:x6; val_offset:5198*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5198*FLEN/8, x7, x2, x4) + +inst_2625: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x01f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c1f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5200*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5200*FLEN/8, x7, x2, x4) + +inst_2626: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x3fe0; + valaddr_reg:x6; val_offset:5202*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5202*FLEN/8, x7, x2, x4) + +inst_2627: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fe0; op2val:0x7bff; + valaddr_reg:x6; val_offset:5204*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5204*FLEN/8, x7, x2, x4) + +inst_2628: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x3c0f; + valaddr_reg:x6; val_offset:5206*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5206*FLEN/8, x7, x2, x4) + +inst_2629: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x00f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c0f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5208*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5208*FLEN/8, x7, x2, x4) + +inst_2630: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x3ff0; + valaddr_reg:x6; val_offset:5210*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5210*FLEN/8, x7, x2, x4) + +inst_2631: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff0; op2val:0x7bff; + valaddr_reg:x6; val_offset:5212*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5212*FLEN/8, x7, x2, x4) + +inst_2632: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x3c07; + valaddr_reg:x6; val_offset:5214*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5214*FLEN/8, x7, x2, x4) + +inst_2633: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x007 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c07; op2val:0x7bff; + valaddr_reg:x6; val_offset:5216*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5216*FLEN/8, x7, x2, x4) + +inst_2634: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x3ff8; + valaddr_reg:x6; val_offset:5218*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5218*FLEN/8, x7, x2, x4) + +inst_2635: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff8; op2val:0x7bff; + valaddr_reg:x6; val_offset:5220*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5220*FLEN/8, x7, x2, x4) + +inst_2636: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x3c03; + valaddr_reg:x6; val_offset:5222*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5222*FLEN/8, x7, x2, x4) + +inst_2637: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x003 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c03; op2val:0x7bff; + valaddr_reg:x6; val_offset:5224*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5224*FLEN/8, x7, x2, x4) + +inst_2638: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x3ffc; + valaddr_reg:x6; val_offset:5226*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5226*FLEN/8, x7, x2, x4) + +inst_2639: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ffc; op2val:0x7bff; + valaddr_reg:x6; val_offset:5228*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5228*FLEN/8, x7, x2, x4) + +inst_2640: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x3c01; + valaddr_reg:x6; val_offset:5230*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5230*FLEN/8, x7, x2, x4) + +inst_2641: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c01; op2val:0x7bff; + valaddr_reg:x6; val_offset:5232*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5232*FLEN/8, x7, x2, x4) + +inst_2642: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x3ffe; + valaddr_reg:x6; val_offset:5234*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5234*FLEN/8, x7, x2, x4) + +inst_2643: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ffe; op2val:0x7bff; + valaddr_reg:x6; val_offset:5236*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5236*FLEN/8, x7, x2, x4) + +inst_2644: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7bfe; + valaddr_reg:x6; val_offset:5238*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5238*FLEN/8, x7, x2, x4) + +inst_2645: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bfe; op2val:0x7bff; + valaddr_reg:x6; val_offset:5240*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5240*FLEN/8, x7, x2, x4) + +inst_2646: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7801; + valaddr_reg:x6; val_offset:5242*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5242*FLEN/8, x7, x2, x4) + +inst_2647: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7801; op2val:0x7bff; + valaddr_reg:x6; val_offset:5244*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5244*FLEN/8, x7, x2, x4) + +inst_2648: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1b6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x79b6; + valaddr_reg:x6; val_offset:5246*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5246*FLEN/8, x7, x2, x4) + +inst_2649: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b6; op2val:0x7bff; + valaddr_reg:x6; val_offset:5248*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5248*FLEN/8, x7, x2, x4) + +inst_2650: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x36d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7b6d; + valaddr_reg:x6; val_offset:5250*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5250*FLEN/8, x7, x2, x4) + +inst_2651: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x36d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b6d; op2val:0x7bff; + valaddr_reg:x6; val_offset:5252*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5252*FLEN/8, x7, x2, x4) + +inst_2652: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0cc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x78cc; + valaddr_reg:x6; val_offset:5254*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5254*FLEN/8, x7, x2, x4) + +inst_2653: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0cc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78cc; op2val:0x7bff; + valaddr_reg:x6; val_offset:5256*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5256*FLEN/8, x7, x2, x4) + +inst_2654: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x333 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7b33; + valaddr_reg:x6; val_offset:5258*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5258*FLEN/8, x7, x2, x4) + +inst_2655: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x333 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b33; op2val:0x7bff; + valaddr_reg:x6; val_offset:5260*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5260*FLEN/8, x7, x2, x4) + +inst_2656: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1dd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x79dd; + valaddr_reg:x6; val_offset:5262*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5262*FLEN/8, x7, x2, x4) + +inst_2657: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1dd and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79dd; op2val:0x7bff; + valaddr_reg:x6; val_offset:5264*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5264*FLEN/8, x7, x2, x4) + +inst_2658: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x222 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7a22; + valaddr_reg:x6; val_offset:5266*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5266*FLEN/8, x7, x2, x4) + +inst_2659: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x222 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a22; op2val:0x7bff; + valaddr_reg:x6; val_offset:5268*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5268*FLEN/8, x7, x2, x4) + +inst_2660: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x124 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7924; + valaddr_reg:x6; val_offset:5270*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5270*FLEN/8, x7, x2, x4) + +inst_2661: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x124 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7924; op2val:0x7bff; + valaddr_reg:x6; val_offset:5272*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5272*FLEN/8, x7, x2, x4) + +inst_2662: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2db and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7adb; + valaddr_reg:x6; val_offset:5274*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5274*FLEN/8, x7, x2, x4) + +inst_2663: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2db and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7adb; op2val:0x7bff; + valaddr_reg:x6; val_offset:5276*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5276*FLEN/8, x7, x2, x4) + +inst_2664: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x199 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7999; + valaddr_reg:x6; val_offset:5278*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5278*FLEN/8, x7, x2, x4) + +inst_2665: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x199 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7999; op2val:0x7bff; + valaddr_reg:x6; val_offset:5280*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5280*FLEN/8, x7, x2, x4) + +inst_2666: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x266 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7a66; + valaddr_reg:x6; val_offset:5282*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5282*FLEN/8, x7, x2, x4) + +inst_2667: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x266 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a66; op2val:0x7bff; + valaddr_reg:x6; val_offset:5284*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5284*FLEN/8, x7, x2, x4) + +inst_2668: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xf7ff; + valaddr_reg:x6; val_offset:5286*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5286*FLEN/8, x7, x2, x4) + +inst_2669: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf7ff; op2val:0x7bff; + valaddr_reg:x6; val_offset:5288*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5288*FLEN/8, x7, x2, x4) + +inst_2670: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1d and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xf400; + valaddr_reg:x6; val_offset:5290*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5290*FLEN/8, x7, x2, x4) + +inst_2671: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf400; op2val:0x7bff; + valaddr_reg:x6; val_offset:5292*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5292*FLEN/8, x7, x2, x4) + +inst_2672: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1d and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xf5ff; + valaddr_reg:x6; val_offset:5294*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5294*FLEN/8, x7, x2, x4) + +inst_2673: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf5ff; op2val:0x7bff; + valaddr_reg:x6; val_offset:5296*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5296*FLEN/8, x7, x2, x4) + +inst_2674: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1d and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xf600; + valaddr_reg:x6; val_offset:5298*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5298*FLEN/8, x7, x2, x4) + +inst_2675: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf600; op2val:0x7bff; + valaddr_reg:x6; val_offset:5300*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5300*FLEN/8, x7, x2, x4) + +inst_2676: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1d and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xf4ff; + valaddr_reg:x6; val_offset:5302*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5302*FLEN/8, x7, x2, x4) + +inst_2677: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf4ff; op2val:0x7bff; + valaddr_reg:x6; val_offset:5304*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5304*FLEN/8, x7, x2, x4) + +inst_2678: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1d and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xf700; + valaddr_reg:x6; val_offset:5306*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5306*FLEN/8, x7, x2, x4) + +inst_2679: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x300 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf700; op2val:0x7bff; + valaddr_reg:x6; val_offset:5308*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5308*FLEN/8, x7, x2, x4) + +inst_2680: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1d and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xf47f; + valaddr_reg:x6; val_offset:5310*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5310*FLEN/8, x7, x2, x4) + +inst_2681: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x07f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf47f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5312*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5312*FLEN/8, x7, x2, x4) + +inst_2682: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1d and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xf780; + valaddr_reg:x6; val_offset:5314*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5314*FLEN/8, x7, x2, x4) + +inst_2683: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x380 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf780; op2val:0x7bff; + valaddr_reg:x6; val_offset:5316*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5316*FLEN/8, x7, x2, x4) + +inst_2684: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1d and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xf43f; + valaddr_reg:x6; val_offset:5318*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5318*FLEN/8, x7, x2, x4) + +inst_2685: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x03f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf43f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5320*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5320*FLEN/8, x7, x2, x4) + +inst_2686: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xf7c0; + valaddr_reg:x6; val_offset:5322*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5322*FLEN/8, x7, x2, x4) + +inst_2687: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf7c0; op2val:0x7bff; + valaddr_reg:x6; val_offset:5324*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5324*FLEN/8, x7, x2, x4) + +inst_2688: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1d and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xf41f; + valaddr_reg:x6; val_offset:5326*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5326*FLEN/8, x7, x2, x4) + +inst_2689: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x01f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf41f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5328*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5328*FLEN/8, x7, x2, x4) + +inst_2690: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xf7e0; + valaddr_reg:x6; val_offset:5330*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5330*FLEN/8, x7, x2, x4) + +inst_2691: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf7e0; op2val:0x7bff; + valaddr_reg:x6; val_offset:5332*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5332*FLEN/8, x7, x2, x4) + +inst_2692: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1d and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xf40f; + valaddr_reg:x6; val_offset:5334*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5334*FLEN/8, x7, x2, x4) + +inst_2693: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x00f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf40f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5336*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5336*FLEN/8, x7, x2, x4) + +inst_2694: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xf7f0; + valaddr_reg:x6; val_offset:5338*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5338*FLEN/8, x7, x2, x4) + +inst_2695: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf7f0; op2val:0x7bff; + valaddr_reg:x6; val_offset:5340*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5340*FLEN/8, x7, x2, x4) + +inst_2696: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1d and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xf407; + valaddr_reg:x6; val_offset:5342*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5342*FLEN/8, x7, x2, x4) + +inst_2697: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x007 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf407; op2val:0x7bff; + valaddr_reg:x6; val_offset:5344*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5344*FLEN/8, x7, x2, x4) + +inst_2698: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xf7f8; + valaddr_reg:x6; val_offset:5346*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5346*FLEN/8, x7, x2, x4) + +inst_2699: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf7f8; op2val:0x7bff; + valaddr_reg:x6; val_offset:5348*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5348*FLEN/8, x7, x2, x4) + +inst_2700: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1d and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xf403; + valaddr_reg:x6; val_offset:5350*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5350*FLEN/8, x7, x2, x4) + +inst_2701: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x003 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf403; op2val:0x7bff; + valaddr_reg:x6; val_offset:5352*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5352*FLEN/8, x7, x2, x4) + +inst_2702: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xf7fc; + valaddr_reg:x6; val_offset:5354*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5354*FLEN/8, x7, x2, x4) + +inst_2703: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf7fc; op2val:0x7bff; + valaddr_reg:x6; val_offset:5356*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5356*FLEN/8, x7, x2, x4) + +inst_2704: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1d and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xf401; + valaddr_reg:x6; val_offset:5358*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5358*FLEN/8, x7, x2, x4) + +inst_2705: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf401; op2val:0x7bff; + valaddr_reg:x6; val_offset:5360*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5360*FLEN/8, x7, x2, x4) + +inst_2706: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xf7fe; + valaddr_reg:x6; val_offset:5362*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5362*FLEN/8, x7, x2, x4) + +inst_2707: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf7fe; op2val:0x7bff; + valaddr_reg:x6; val_offset:5364*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5364*FLEN/8, x7, x2, x4) + +inst_2708: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1a and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6bff; + valaddr_reg:x6; val_offset:5366*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5366*FLEN/8, x7, x2, x4) + +inst_2709: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6bff; op2val:0x7bff; + valaddr_reg:x6; val_offset:5368*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5368*FLEN/8, x7, x2, x4) + +inst_2710: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1a and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6800; + valaddr_reg:x6; val_offset:5370*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5370*FLEN/8, x7, x2, x4) + +inst_2711: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6800; op2val:0x7bff; + valaddr_reg:x6; val_offset:5372*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5372*FLEN/8, x7, x2, x4) + +inst_2712: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1a and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x69ff; + valaddr_reg:x6; val_offset:5374*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5374*FLEN/8, x7, x2, x4) + +inst_2713: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x69ff; op2val:0x7bff; + valaddr_reg:x6; val_offset:5376*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5376*FLEN/8, x7, x2, x4) + +inst_2714: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1a and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6a00; + valaddr_reg:x6; val_offset:5378*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5378*FLEN/8, x7, x2, x4) + +inst_2715: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6a00; op2val:0x7bff; + valaddr_reg:x6; val_offset:5380*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5380*FLEN/8, x7, x2, x4) + +inst_2716: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1a and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x68ff; + valaddr_reg:x6; val_offset:5382*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5382*FLEN/8, x7, x2, x4) +RVTEST_SIGBASE(x2,signature_x2_23) + +inst_2717: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x68ff; op2val:0x7bff; + valaddr_reg:x6; val_offset:5384*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5384*FLEN/8, x7, x2, x4) + +inst_2718: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1a and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6b00; + valaddr_reg:x6; val_offset:5386*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5386*FLEN/8, x7, x2, x4) + +inst_2719: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x300 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6b00; op2val:0x7bff; + valaddr_reg:x6; val_offset:5388*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5388*FLEN/8, x7, x2, x4) + +inst_2720: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1a and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x687f; + valaddr_reg:x6; val_offset:5390*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5390*FLEN/8, x7, x2, x4) + +inst_2721: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x07f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x687f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5392*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5392*FLEN/8, x7, x2, x4) + +inst_2722: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1a and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6b80; + valaddr_reg:x6; val_offset:5394*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5394*FLEN/8, x7, x2, x4) + +inst_2723: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x380 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6b80; op2val:0x7bff; + valaddr_reg:x6; val_offset:5396*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5396*FLEN/8, x7, x2, x4) + +inst_2724: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1a and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x683f; + valaddr_reg:x6; val_offset:5398*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5398*FLEN/8, x7, x2, x4) + +inst_2725: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x03f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x683f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5400*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5400*FLEN/8, x7, x2, x4) + +inst_2726: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1a and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6bc0; + valaddr_reg:x6; val_offset:5402*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5402*FLEN/8, x7, x2, x4) + +inst_2727: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6bc0; op2val:0x7bff; + valaddr_reg:x6; val_offset:5404*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5404*FLEN/8, x7, x2, x4) + +inst_2728: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1a and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x681f; + valaddr_reg:x6; val_offset:5406*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5406*FLEN/8, x7, x2, x4) + +inst_2729: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x01f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x681f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5408*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5408*FLEN/8, x7, x2, x4) + +inst_2730: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1a and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6be0; + valaddr_reg:x6; val_offset:5410*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5410*FLEN/8, x7, x2, x4) + +inst_2731: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6be0; op2val:0x7bff; + valaddr_reg:x6; val_offset:5412*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5412*FLEN/8, x7, x2, x4) + +inst_2732: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1a and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x680f; + valaddr_reg:x6; val_offset:5414*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5414*FLEN/8, x7, x2, x4) + +inst_2733: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x00f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x680f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5416*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5416*FLEN/8, x7, x2, x4) + +inst_2734: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1a and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6bf0; + valaddr_reg:x6; val_offset:5418*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5418*FLEN/8, x7, x2, x4) + +inst_2735: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6bf0; op2val:0x7bff; + valaddr_reg:x6; val_offset:5420*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5420*FLEN/8, x7, x2, x4) + +inst_2736: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1a and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6807; + valaddr_reg:x6; val_offset:5422*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5422*FLEN/8, x7, x2, x4) + +inst_2737: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x007 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6807; op2val:0x7bff; + valaddr_reg:x6; val_offset:5424*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5424*FLEN/8, x7, x2, x4) + +inst_2738: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1a and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6bf8; + valaddr_reg:x6; val_offset:5426*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5426*FLEN/8, x7, x2, x4) + +inst_2739: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6bf8; op2val:0x7bff; + valaddr_reg:x6; val_offset:5428*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5428*FLEN/8, x7, x2, x4) + +inst_2740: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1a and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6803; + valaddr_reg:x6; val_offset:5430*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5430*FLEN/8, x7, x2, x4) + +inst_2741: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x003 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6803; op2val:0x7bff; + valaddr_reg:x6; val_offset:5432*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5432*FLEN/8, x7, x2, x4) + +inst_2742: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1a and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6bfc; + valaddr_reg:x6; val_offset:5434*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5434*FLEN/8, x7, x2, x4) + +inst_2743: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6bfc; op2val:0x7bff; + valaddr_reg:x6; val_offset:5436*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5436*FLEN/8, x7, x2, x4) + +inst_2744: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1a and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6801; + valaddr_reg:x6; val_offset:5438*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5438*FLEN/8, x7, x2, x4) + +inst_2745: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6801; op2val:0x7bff; + valaddr_reg:x6; val_offset:5440*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5440*FLEN/8, x7, x2, x4) + +inst_2746: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1a and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6bfe; + valaddr_reg:x6; val_offset:5442*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5442*FLEN/8, x7, x2, x4) + +inst_2747: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6bfe; op2val:0x7bff; + valaddr_reg:x6; val_offset:5444*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5444*FLEN/8, x7, x2, x4) + +inst_2748: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6fff; + valaddr_reg:x6; val_offset:5446*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5446*FLEN/8, x7, x2, x4) + +inst_2749: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6fff; op2val:0x7bff; + valaddr_reg:x6; val_offset:5448*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5448*FLEN/8, x7, x2, x4) + +inst_2750: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1b and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6c00; + valaddr_reg:x6; val_offset:5450*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5450*FLEN/8, x7, x2, x4) + +inst_2751: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c00; op2val:0x7bff; + valaddr_reg:x6; val_offset:5452*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5452*FLEN/8, x7, x2, x4) + +inst_2752: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1b and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6dff; + valaddr_reg:x6; val_offset:5454*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5454*FLEN/8, x7, x2, x4) + +inst_2753: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6dff; op2val:0x7bff; + valaddr_reg:x6; val_offset:5456*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5456*FLEN/8, x7, x2, x4) + +inst_2754: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1b and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6e00; + valaddr_reg:x6; val_offset:5458*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5458*FLEN/8, x7, x2, x4) + +inst_2755: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e00; op2val:0x7bff; + valaddr_reg:x6; val_offset:5460*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5460*FLEN/8, x7, x2, x4) + +inst_2756: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6cff; + valaddr_reg:x6; val_offset:5462*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5462*FLEN/8, x7, x2, x4) + +inst_2757: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6cff; op2val:0x7bff; + valaddr_reg:x6; val_offset:5464*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5464*FLEN/8, x7, x2, x4) + +inst_2758: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1b and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6f00; + valaddr_reg:x6; val_offset:5466*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5466*FLEN/8, x7, x2, x4) + +inst_2759: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x300 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f00; op2val:0x7bff; + valaddr_reg:x6; val_offset:5468*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5468*FLEN/8, x7, x2, x4) + +inst_2760: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1b and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6c7f; + valaddr_reg:x6; val_offset:5470*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5470*FLEN/8, x7, x2, x4) + +inst_2761: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x07f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c7f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5472*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5472*FLEN/8, x7, x2, x4) + +inst_2762: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1b and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6f80; + valaddr_reg:x6; val_offset:5474*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5474*FLEN/8, x7, x2, x4) + +inst_2763: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x380 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f80; op2val:0x7bff; + valaddr_reg:x6; val_offset:5476*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5476*FLEN/8, x7, x2, x4) + +inst_2764: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1b and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6c3f; + valaddr_reg:x6; val_offset:5478*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5478*FLEN/8, x7, x2, x4) + +inst_2765: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x03f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c3f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5480*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5480*FLEN/8, x7, x2, x4) + +inst_2766: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6fc0; + valaddr_reg:x6; val_offset:5482*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5482*FLEN/8, x7, x2, x4) + +inst_2767: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6fc0; op2val:0x7bff; + valaddr_reg:x6; val_offset:5484*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5484*FLEN/8, x7, x2, x4) + +inst_2768: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1b and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6c1f; + valaddr_reg:x6; val_offset:5486*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5486*FLEN/8, x7, x2, x4) + +inst_2769: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x01f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c1f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5488*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5488*FLEN/8, x7, x2, x4) + +inst_2770: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6fe0; + valaddr_reg:x6; val_offset:5490*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5490*FLEN/8, x7, x2, x4) + +inst_2771: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6fe0; op2val:0x7bff; + valaddr_reg:x6; val_offset:5492*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5492*FLEN/8, x7, x2, x4) + +inst_2772: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1b and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6c0f; + valaddr_reg:x6; val_offset:5494*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5494*FLEN/8, x7, x2, x4) + +inst_2773: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x00f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c0f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5496*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5496*FLEN/8, x7, x2, x4) + +inst_2774: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6ff0; + valaddr_reg:x6; val_offset:5498*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5498*FLEN/8, x7, x2, x4) + +inst_2775: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ff0; op2val:0x7bff; + valaddr_reg:x6; val_offset:5500*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5500*FLEN/8, x7, x2, x4) + +inst_2776: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1b and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6c07; + valaddr_reg:x6; val_offset:5502*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5502*FLEN/8, x7, x2, x4) + +inst_2777: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x007 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c07; op2val:0x7bff; + valaddr_reg:x6; val_offset:5504*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5504*FLEN/8, x7, x2, x4) + +inst_2778: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6ff8; + valaddr_reg:x6; val_offset:5506*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5506*FLEN/8, x7, x2, x4) + +inst_2779: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ff8; op2val:0x7bff; + valaddr_reg:x6; val_offset:5508*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5508*FLEN/8, x7, x2, x4) + +inst_2780: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1b and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6c03; + valaddr_reg:x6; val_offset:5510*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5510*FLEN/8, x7, x2, x4) + +inst_2781: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x003 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c03; op2val:0x7bff; + valaddr_reg:x6; val_offset:5512*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5512*FLEN/8, x7, x2, x4) + +inst_2782: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6ffc; + valaddr_reg:x6; val_offset:5514*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5514*FLEN/8, x7, x2, x4) + +inst_2783: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ffc; op2val:0x7bff; + valaddr_reg:x6; val_offset:5516*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5516*FLEN/8, x7, x2, x4) + +inst_2784: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1b and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6c01; + valaddr_reg:x6; val_offset:5518*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5518*FLEN/8, x7, x2, x4) + +inst_2785: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c01; op2val:0x7bff; + valaddr_reg:x6; val_offset:5520*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5520*FLEN/8, x7, x2, x4) + +inst_2786: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6ffe; + valaddr_reg:x6; val_offset:5522*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5522*FLEN/8, x7, x2, x4) + +inst_2787: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ffe; op2val:0x7bff; + valaddr_reg:x6; val_offset:5524*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5524*FLEN/8, x7, x2, x4) + +inst_2788: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x73ff; + valaddr_reg:x6; val_offset:5526*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5526*FLEN/8, x7, x2, x4) + +inst_2789: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x73ff; op2val:0x7bff; + valaddr_reg:x6; val_offset:5528*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5528*FLEN/8, x7, x2, x4) + +inst_2790: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1c and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7000; + valaddr_reg:x6; val_offset:5530*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5530*FLEN/8, x7, x2, x4) + +inst_2791: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7000; op2val:0x7bff; + valaddr_reg:x6; val_offset:5532*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5532*FLEN/8, x7, x2, x4) + +inst_2792: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x71ff; + valaddr_reg:x6; val_offset:5534*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5534*FLEN/8, x7, x2, x4) + +inst_2793: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x71ff; op2val:0x7bff; + valaddr_reg:x6; val_offset:5536*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5536*FLEN/8, x7, x2, x4) + +inst_2794: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1c and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7200; + valaddr_reg:x6; val_offset:5538*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5538*FLEN/8, x7, x2, x4) + +inst_2795: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7200; op2val:0x7bff; + valaddr_reg:x6; val_offset:5540*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5540*FLEN/8, x7, x2, x4) + +inst_2796: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x70ff; + valaddr_reg:x6; val_offset:5542*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5542*FLEN/8, x7, x2, x4) + +inst_2797: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x70ff; op2val:0x7bff; + valaddr_reg:x6; val_offset:5544*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5544*FLEN/8, x7, x2, x4) + +inst_2798: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1c and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7300; + valaddr_reg:x6; val_offset:5546*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5546*FLEN/8, x7, x2, x4) + +inst_2799: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x300 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7300; op2val:0x7bff; + valaddr_reg:x6; val_offset:5548*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5548*FLEN/8, x7, x2, x4) + +inst_2800: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1c and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x707f; + valaddr_reg:x6; val_offset:5550*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5550*FLEN/8, x7, x2, x4) + +inst_2801: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x07f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x707f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5552*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5552*FLEN/8, x7, x2, x4) + +inst_2802: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1c and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7380; + valaddr_reg:x6; val_offset:5554*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5554*FLEN/8, x7, x2, x4) + +inst_2803: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x380 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7380; op2val:0x7bff; + valaddr_reg:x6; val_offset:5556*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5556*FLEN/8, x7, x2, x4) + +inst_2804: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1c and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x703f; + valaddr_reg:x6; val_offset:5558*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5558*FLEN/8, x7, x2, x4) + +inst_2805: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x03f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x703f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5560*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5560*FLEN/8, x7, x2, x4) + +inst_2806: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x73c0; + valaddr_reg:x6; val_offset:5562*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5562*FLEN/8, x7, x2, x4) + +inst_2807: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x73c0; op2val:0x7bff; + valaddr_reg:x6; val_offset:5564*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5564*FLEN/8, x7, x2, x4) + +inst_2808: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1c and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x701f; + valaddr_reg:x6; val_offset:5566*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5566*FLEN/8, x7, x2, x4) + +inst_2809: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x01f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x701f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5568*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5568*FLEN/8, x7, x2, x4) + +inst_2810: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x73e0; + valaddr_reg:x6; val_offset:5570*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5570*FLEN/8, x7, x2, x4) + +inst_2811: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x73e0; op2val:0x7bff; + valaddr_reg:x6; val_offset:5572*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5572*FLEN/8, x7, x2, x4) + +inst_2812: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1c and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x700f; + valaddr_reg:x6; val_offset:5574*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5574*FLEN/8, x7, x2, x4) + +inst_2813: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x00f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x700f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5576*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5576*FLEN/8, x7, x2, x4) + +inst_2814: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x73f0; + valaddr_reg:x6; val_offset:5578*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5578*FLEN/8, x7, x2, x4) + +inst_2815: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x73f0; op2val:0x7bff; + valaddr_reg:x6; val_offset:5580*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5580*FLEN/8, x7, x2, x4) + +inst_2816: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1c and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7007; + valaddr_reg:x6; val_offset:5582*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5582*FLEN/8, x7, x2, x4) + +inst_2817: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x007 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7007; op2val:0x7bff; + valaddr_reg:x6; val_offset:5584*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5584*FLEN/8, x7, x2, x4) + +inst_2818: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x73f8; + valaddr_reg:x6; val_offset:5586*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5586*FLEN/8, x7, x2, x4) + +inst_2819: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x73f8; op2val:0x7bff; + valaddr_reg:x6; val_offset:5588*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5588*FLEN/8, x7, x2, x4) + +inst_2820: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1c and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7003; + valaddr_reg:x6; val_offset:5590*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5590*FLEN/8, x7, x2, x4) + +inst_2821: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x003 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7003; op2val:0x7bff; + valaddr_reg:x6; val_offset:5592*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5592*FLEN/8, x7, x2, x4) + +inst_2822: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x73fc; + valaddr_reg:x6; val_offset:5594*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5594*FLEN/8, x7, x2, x4) + +inst_2823: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x73fc; op2val:0x7bff; + valaddr_reg:x6; val_offset:5596*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5596*FLEN/8, x7, x2, x4) + +inst_2824: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1c and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7001; + valaddr_reg:x6; val_offset:5598*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5598*FLEN/8, x7, x2, x4) + +inst_2825: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7001; op2val:0x7bff; + valaddr_reg:x6; val_offset:5600*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5600*FLEN/8, x7, x2, x4) + +inst_2826: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x73fe; + valaddr_reg:x6; val_offset:5602*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5602*FLEN/8, x7, x2, x4) + +inst_2827: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x73fe; op2val:0x7bff; + valaddr_reg:x6; val_offset:5604*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5604*FLEN/8, x7, x2, x4) + +inst_2828: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x77ff; + valaddr_reg:x6; val_offset:5606*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5606*FLEN/8, x7, x2, x4) + +inst_2829: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77ff; op2val:0x7bff; + valaddr_reg:x6; val_offset:5608*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5608*FLEN/8, x7, x2, x4) + +inst_2830: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1d and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7400; + valaddr_reg:x6; val_offset:5610*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5610*FLEN/8, x7, x2, x4) + +inst_2831: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7400; op2val:0x7bff; + valaddr_reg:x6; val_offset:5612*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5612*FLEN/8, x7, x2, x4) + +inst_2832: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x75ff; + valaddr_reg:x6; val_offset:5614*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5614*FLEN/8, x7, x2, x4) + +inst_2833: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x75ff; op2val:0x7bff; + valaddr_reg:x6; val_offset:5616*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5616*FLEN/8, x7, x2, x4) + +inst_2834: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1d and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7600; + valaddr_reg:x6; val_offset:5618*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5618*FLEN/8, x7, x2, x4) + +inst_2835: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7600; op2val:0x7bff; + valaddr_reg:x6; val_offset:5620*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5620*FLEN/8, x7, x2, x4) + +inst_2836: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x74ff; + valaddr_reg:x6; val_offset:5622*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5622*FLEN/8, x7, x2, x4) + +inst_2837: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x74ff; op2val:0x7bff; + valaddr_reg:x6; val_offset:5624*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5624*FLEN/8, x7, x2, x4) + +inst_2838: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1d and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7700; + valaddr_reg:x6; val_offset:5626*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5626*FLEN/8, x7, x2, x4) + +inst_2839: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x300 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7700; op2val:0x7bff; + valaddr_reg:x6; val_offset:5628*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5628*FLEN/8, x7, x2, x4) + +inst_2840: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1d and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x747f; + valaddr_reg:x6; val_offset:5630*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5630*FLEN/8, x7, x2, x4) + +inst_2841: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x07f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x747f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5632*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5632*FLEN/8, x7, x2, x4) + +inst_2842: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1d and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7780; + valaddr_reg:x6; val_offset:5634*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5634*FLEN/8, x7, x2, x4) + +inst_2843: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x380 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7780; op2val:0x7bff; + valaddr_reg:x6; val_offset:5636*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5636*FLEN/8, x7, x2, x4) + +inst_2844: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1d and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x743f; + valaddr_reg:x6; val_offset:5638*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5638*FLEN/8, x7, x2, x4) +RVTEST_SIGBASE(x2,signature_x2_24) + +inst_2845: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x03f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x743f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5640*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5640*FLEN/8, x7, x2, x4) + +inst_2846: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x77c0; + valaddr_reg:x6; val_offset:5642*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5642*FLEN/8, x7, x2, x4) + +inst_2847: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77c0; op2val:0x7bff; + valaddr_reg:x6; val_offset:5644*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5644*FLEN/8, x7, x2, x4) + +inst_2848: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1d and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x741f; + valaddr_reg:x6; val_offset:5646*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5646*FLEN/8, x7, x2, x4) + +inst_2849: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x01f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x741f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5648*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5648*FLEN/8, x7, x2, x4) + +inst_2850: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x77e0; + valaddr_reg:x6; val_offset:5650*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5650*FLEN/8, x7, x2, x4) + +inst_2851: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77e0; op2val:0x7bff; + valaddr_reg:x6; val_offset:5652*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5652*FLEN/8, x7, x2, x4) + +inst_2852: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1d and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x740f; + valaddr_reg:x6; val_offset:5654*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5654*FLEN/8, x7, x2, x4) + +inst_2853: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x00f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x740f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5656*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5656*FLEN/8, x7, x2, x4) + +inst_2854: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x77f0; + valaddr_reg:x6; val_offset:5658*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5658*FLEN/8, x7, x2, x4) + +inst_2855: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77f0; op2val:0x7bff; + valaddr_reg:x6; val_offset:5660*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5660*FLEN/8, x7, x2, x4) + +inst_2856: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1d and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7407; + valaddr_reg:x6; val_offset:5662*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5662*FLEN/8, x7, x2, x4) + +inst_2857: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x007 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7407; op2val:0x7bff; + valaddr_reg:x6; val_offset:5664*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5664*FLEN/8, x7, x2, x4) + +inst_2858: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x77f8; + valaddr_reg:x6; val_offset:5666*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5666*FLEN/8, x7, x2, x4) + +inst_2859: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77f8; op2val:0x7bff; + valaddr_reg:x6; val_offset:5668*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5668*FLEN/8, x7, x2, x4) + +inst_2860: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1d and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7403; + valaddr_reg:x6; val_offset:5670*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5670*FLEN/8, x7, x2, x4) + +inst_2861: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x003 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7403; op2val:0x7bff; + valaddr_reg:x6; val_offset:5672*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5672*FLEN/8, x7, x2, x4) + +inst_2862: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x77fc; + valaddr_reg:x6; val_offset:5674*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5674*FLEN/8, x7, x2, x4) + +inst_2863: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77fc; op2val:0x7bff; + valaddr_reg:x6; val_offset:5676*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5676*FLEN/8, x7, x2, x4) + +inst_2864: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1d and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7401; + valaddr_reg:x6; val_offset:5678*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5678*FLEN/8, x7, x2, x4) + +inst_2865: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7401; op2val:0x7bff; + valaddr_reg:x6; val_offset:5680*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5680*FLEN/8, x7, x2, x4) + +inst_2866: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x77fe; + valaddr_reg:x6; val_offset:5682*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5682*FLEN/8, x7, x2, x4) + +inst_2867: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77fe; op2val:0x7bff; + valaddr_reg:x6; val_offset:5684*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5684*FLEN/8, x7, x2, x4) + +inst_2868: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7bff; + valaddr_reg:x6; val_offset:5686*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5686*FLEN/8, x7, x2, x4) + +inst_2869: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7800; + valaddr_reg:x6; val_offset:5688*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5688*FLEN/8, x7, x2, x4) + +inst_2870: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7800; op2val:0x7bff; + valaddr_reg:x6; val_offset:5690*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5690*FLEN/8, x7, x2, x4) + +inst_2871: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x79ff; + valaddr_reg:x6; val_offset:5692*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5692*FLEN/8, x7, x2, x4) + +inst_2872: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79ff; op2val:0x7bff; + valaddr_reg:x6; val_offset:5694*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5694*FLEN/8, x7, x2, x4) + +inst_2873: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7a00; + valaddr_reg:x6; val_offset:5696*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5696*FLEN/8, x7, x2, x4) + +inst_2874: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a00; op2val:0x7bff; + valaddr_reg:x6; val_offset:5698*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5698*FLEN/8, x7, x2, x4) + +inst_2875: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x78ff; + valaddr_reg:x6; val_offset:5700*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5700*FLEN/8, x7, x2, x4) + +inst_2876: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78ff; op2val:0x7bff; + valaddr_reg:x6; val_offset:5702*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5702*FLEN/8, x7, x2, x4) + +inst_2877: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7b00; + valaddr_reg:x6; val_offset:5704*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5704*FLEN/8, x7, x2, x4) + +inst_2878: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x300 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b00; op2val:0x7bff; + valaddr_reg:x6; val_offset:5706*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5706*FLEN/8, x7, x2, x4) + +inst_2879: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x787f; + valaddr_reg:x6; val_offset:5708*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5708*FLEN/8, x7, x2, x4) + +inst_2880: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x07f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x787f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5710*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5710*FLEN/8, x7, x2, x4) + +inst_2881: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7b80; + valaddr_reg:x6; val_offset:5712*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5712*FLEN/8, x7, x2, x4) + +inst_2882: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x380 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b80; op2val:0x7bff; + valaddr_reg:x6; val_offset:5714*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5714*FLEN/8, x7, x2, x4) + +inst_2883: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x783f; + valaddr_reg:x6; val_offset:5716*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5716*FLEN/8, x7, x2, x4) + +inst_2884: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x03f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x783f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5718*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5718*FLEN/8, x7, x2, x4) + +inst_2885: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7bc0; + valaddr_reg:x6; val_offset:5720*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5720*FLEN/8, x7, x2, x4) + +inst_2886: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bc0; op2val:0x7bff; + valaddr_reg:x6; val_offset:5722*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5722*FLEN/8, x7, x2, x4) + +inst_2887: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x781f; + valaddr_reg:x6; val_offset:5724*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5724*FLEN/8, x7, x2, x4) + +inst_2888: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x01f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x781f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5726*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5726*FLEN/8, x7, x2, x4) + +inst_2889: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7be0; + valaddr_reg:x6; val_offset:5728*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5728*FLEN/8, x7, x2, x4) + +inst_2890: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7be0; op2val:0x7bff; + valaddr_reg:x6; val_offset:5730*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5730*FLEN/8, x7, x2, x4) + +inst_2891: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x780f; + valaddr_reg:x6; val_offset:5732*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5732*FLEN/8, x7, x2, x4) + +inst_2892: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x780f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5734*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5734*FLEN/8, x7, x2, x4) + +inst_2893: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7bf0; + valaddr_reg:x6; val_offset:5736*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5736*FLEN/8, x7, x2, x4) + +inst_2894: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bf0; op2val:0x7bff; + valaddr_reg:x6; val_offset:5738*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5738*FLEN/8, x7, x2, x4) + +inst_2895: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7807; + valaddr_reg:x6; val_offset:5740*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5740*FLEN/8, x7, x2, x4) + +inst_2896: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x007 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7807; op2val:0x7bff; + valaddr_reg:x6; val_offset:5742*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5742*FLEN/8, x7, x2, x4) + +inst_2897: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7bf8; + valaddr_reg:x6; val_offset:5744*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5744*FLEN/8, x7, x2, x4) + +inst_2898: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bf8; op2val:0x7bff; + valaddr_reg:x6; val_offset:5746*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5746*FLEN/8, x7, x2, x4) + +inst_2899: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7803; + valaddr_reg:x6; val_offset:5748*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5748*FLEN/8, x7, x2, x4) + +inst_2900: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x003 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7803; op2val:0x7bff; + valaddr_reg:x6; val_offset:5750*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5750*FLEN/8, x7, x2, x4) + +inst_2901: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7bfc; + valaddr_reg:x6; val_offset:5752*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5752*FLEN/8, x7, x2, x4) + +inst_2902: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bfc; op2val:0x7bff; + valaddr_reg:x6; val_offset:5754*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5754*FLEN/8, x7, x2, x4) + +inst_2903: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x83ff; + valaddr_reg:x6; val_offset:5756*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5756*FLEN/8, x7, x2, x4) + +inst_2904: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x7bff; + valaddr_reg:x6; val_offset:5758*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5758*FLEN/8, x7, x2, x4) + +inst_2905: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8001; + valaddr_reg:x6; val_offset:5760*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5760*FLEN/8, x7, x2, x4) + +inst_2906: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x7bff; + valaddr_reg:x6; val_offset:5762*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5762*FLEN/8, x7, x2, x4) + +inst_2907: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x81ff; + valaddr_reg:x6; val_offset:5764*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5764*FLEN/8, x7, x2, x4) + +inst_2908: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x81ff; op2val:0x7bff; + valaddr_reg:x6; val_offset:5766*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5766*FLEN/8, x7, x2, x4) + +inst_2909: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8200; + valaddr_reg:x6; val_offset:5768*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5768*FLEN/8, x7, x2, x4) + +inst_2910: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8200; op2val:0x7bff; + valaddr_reg:x6; val_offset:5770*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5770*FLEN/8, x7, x2, x4) + +inst_2911: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x80ff; + valaddr_reg:x6; val_offset:5772*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5772*FLEN/8, x7, x2, x4) + +inst_2912: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x80ff; op2val:0x7bff; + valaddr_reg:x6; val_offset:5774*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5774*FLEN/8, x7, x2, x4) + +inst_2913: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8300; + valaddr_reg:x6; val_offset:5776*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5776*FLEN/8, x7, x2, x4) + +inst_2914: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x300 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8300; op2val:0x7bff; + valaddr_reg:x6; val_offset:5778*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5778*FLEN/8, x7, x2, x4) + +inst_2915: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x807f; + valaddr_reg:x6; val_offset:5780*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5780*FLEN/8, x7, x2, x4) + +inst_2916: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x07f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x807f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5782*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5782*FLEN/8, x7, x2, x4) + +inst_2917: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8380; + valaddr_reg:x6; val_offset:5784*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5784*FLEN/8, x7, x2, x4) + +inst_2918: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x380 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8380; op2val:0x7bff; + valaddr_reg:x6; val_offset:5786*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5786*FLEN/8, x7, x2, x4) + +inst_2919: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x803f; + valaddr_reg:x6; val_offset:5788*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5788*FLEN/8, x7, x2, x4) + +inst_2920: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x803f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5790*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5790*FLEN/8, x7, x2, x4) + +inst_2921: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x83c0; + valaddr_reg:x6; val_offset:5792*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5792*FLEN/8, x7, x2, x4) + +inst_2922: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83c0; op2val:0x7bff; + valaddr_reg:x6; val_offset:5794*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5794*FLEN/8, x7, x2, x4) + +inst_2923: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x801f; + valaddr_reg:x6; val_offset:5796*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5796*FLEN/8, x7, x2, x4) + +inst_2924: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x01f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x801f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5798*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5798*FLEN/8, x7, x2, x4) + +inst_2925: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x83e0; + valaddr_reg:x6; val_offset:5800*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5800*FLEN/8, x7, x2, x4) + +inst_2926: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83e0; op2val:0x7bff; + valaddr_reg:x6; val_offset:5802*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5802*FLEN/8, x7, x2, x4) + +inst_2927: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x800f; + valaddr_reg:x6; val_offset:5804*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5804*FLEN/8, x7, x2, x4) + +inst_2928: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x00f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x800f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5806*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5806*FLEN/8, x7, x2, x4) + +inst_2929: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x83f0; + valaddr_reg:x6; val_offset:5808*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5808*FLEN/8, x7, x2, x4) + +inst_2930: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83f0; op2val:0x7bff; + valaddr_reg:x6; val_offset:5810*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5810*FLEN/8, x7, x2, x4) + +inst_2931: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8007; + valaddr_reg:x6; val_offset:5812*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5812*FLEN/8, x7, x2, x4) + +inst_2932: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8007; op2val:0x7bff; + valaddr_reg:x6; val_offset:5814*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5814*FLEN/8, x7, x2, x4) + +inst_2933: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x83f8; + valaddr_reg:x6; val_offset:5816*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5816*FLEN/8, x7, x2, x4) + +inst_2934: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83f8; op2val:0x7bff; + valaddr_reg:x6; val_offset:5818*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5818*FLEN/8, x7, x2, x4) + +inst_2935: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8003; + valaddr_reg:x6; val_offset:5820*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5820*FLEN/8, x7, x2, x4) + +inst_2936: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x003 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8003; op2val:0x7bff; + valaddr_reg:x6; val_offset:5822*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5822*FLEN/8, x7, x2, x4) + +inst_2937: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x83fc; + valaddr_reg:x6; val_offset:5824*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5824*FLEN/8, x7, x2, x4) + +inst_2938: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fc; op2val:0x7bff; + valaddr_reg:x6; val_offset:5826*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5826*FLEN/8, x7, x2, x4) + +inst_2939: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x83fe; + valaddr_reg:x6; val_offset:5828*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5828*FLEN/8, x7, x2, x4) + +inst_2940: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x7bff; + valaddr_reg:x6; val_offset:5830*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5830*FLEN/8, x7, x2, x4) + +inst_2941: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x87ff; + valaddr_reg:x6; val_offset:5832*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5832*FLEN/8, x7, x2, x4) + +inst_2942: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x87ff; op2val:0x7bff; + valaddr_reg:x6; val_offset:5834*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5834*FLEN/8, x7, x2, x4) + +inst_2943: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8400; + valaddr_reg:x6; val_offset:5836*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5836*FLEN/8, x7, x2, x4) + +inst_2944: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x7bff; + valaddr_reg:x6; val_offset:5838*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5838*FLEN/8, x7, x2, x4) + +inst_2945: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x85ff; + valaddr_reg:x6; val_offset:5840*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5840*FLEN/8, x7, x2, x4) + +inst_2946: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x85ff; op2val:0x7bff; + valaddr_reg:x6; val_offset:5842*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5842*FLEN/8, x7, x2, x4) + +inst_2947: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8600; + valaddr_reg:x6; val_offset:5844*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5844*FLEN/8, x7, x2, x4) + +inst_2948: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8600; op2val:0x7bff; + valaddr_reg:x6; val_offset:5846*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5846*FLEN/8, x7, x2, x4) + +inst_2949: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x84ff; + valaddr_reg:x6; val_offset:5848*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5848*FLEN/8, x7, x2, x4) + +inst_2950: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x84ff; op2val:0x7bff; + valaddr_reg:x6; val_offset:5850*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5850*FLEN/8, x7, x2, x4) + +inst_2951: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8700; + valaddr_reg:x6; val_offset:5852*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5852*FLEN/8, x7, x2, x4) + +inst_2952: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x300 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8700; op2val:0x7bff; + valaddr_reg:x6; val_offset:5854*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5854*FLEN/8, x7, x2, x4) + +inst_2953: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x847f; + valaddr_reg:x6; val_offset:5856*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5856*FLEN/8, x7, x2, x4) + +inst_2954: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x07f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x847f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5858*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5858*FLEN/8, x7, x2, x4) + +inst_2955: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8780; + valaddr_reg:x6; val_offset:5860*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5860*FLEN/8, x7, x2, x4) + +inst_2956: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x380 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8780; op2val:0x7bff; + valaddr_reg:x6; val_offset:5862*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5862*FLEN/8, x7, x2, x4) + +inst_2957: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x843f; + valaddr_reg:x6; val_offset:5864*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5864*FLEN/8, x7, x2, x4) + +inst_2958: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x843f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5866*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5866*FLEN/8, x7, x2, x4) + +inst_2959: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x87c0; + valaddr_reg:x6; val_offset:5868*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5868*FLEN/8, x7, x2, x4) + +inst_2960: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x87c0; op2val:0x7bff; + valaddr_reg:x6; val_offset:5870*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5870*FLEN/8, x7, x2, x4) + +inst_2961: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x841f; + valaddr_reg:x6; val_offset:5872*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5872*FLEN/8, x7, x2, x4) + +inst_2962: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x01f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x841f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5874*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5874*FLEN/8, x7, x2, x4) + +inst_2963: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x87e0; + valaddr_reg:x6; val_offset:5876*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5876*FLEN/8, x7, x2, x4) + +inst_2964: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x87e0; op2val:0x7bff; + valaddr_reg:x6; val_offset:5878*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5878*FLEN/8, x7, x2, x4) + +inst_2965: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x840f; + valaddr_reg:x6; val_offset:5880*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5880*FLEN/8, x7, x2, x4) + +inst_2966: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x00f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x840f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5882*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5882*FLEN/8, x7, x2, x4) + +inst_2967: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x87f0; + valaddr_reg:x6; val_offset:5884*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5884*FLEN/8, x7, x2, x4) + +inst_2968: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x87f0; op2val:0x7bff; + valaddr_reg:x6; val_offset:5886*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5886*FLEN/8, x7, x2, x4) + +inst_2969: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8407; + valaddr_reg:x6; val_offset:5888*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5888*FLEN/8, x7, x2, x4) + +inst_2970: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8407; op2val:0x7bff; + valaddr_reg:x6; val_offset:5890*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5890*FLEN/8, x7, x2, x4) + +inst_2971: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x87f8; + valaddr_reg:x6; val_offset:5892*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5892*FLEN/8, x7, x2, x4) + +inst_2972: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x87f8; op2val:0x7bff; + valaddr_reg:x6; val_offset:5894*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5894*FLEN/8, x7, x2, x4) +RVTEST_SIGBASE(x2,signature_x2_25) + +inst_2973: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8403; + valaddr_reg:x6; val_offset:5896*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5896*FLEN/8, x7, x2, x4) + +inst_2974: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x003 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8403; op2val:0x7bff; + valaddr_reg:x6; val_offset:5898*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5898*FLEN/8, x7, x2, x4) + +inst_2975: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x87fc; + valaddr_reg:x6; val_offset:5900*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5900*FLEN/8, x7, x2, x4) + +inst_2976: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x87fc; op2val:0x7bff; + valaddr_reg:x6; val_offset:5902*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5902*FLEN/8, x7, x2, x4) + +inst_2977: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8401; + valaddr_reg:x6; val_offset:5904*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5904*FLEN/8, x7, x2, x4) + +inst_2978: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8401; op2val:0x7bff; + valaddr_reg:x6; val_offset:5906*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5906*FLEN/8, x7, x2, x4) + +inst_2979: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x87fe; + valaddr_reg:x6; val_offset:5908*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5908*FLEN/8, x7, x2, x4) + +inst_2980: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x87fe; op2val:0x7bff; + valaddr_reg:x6; val_offset:5910*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5910*FLEN/8, x7, x2, x4) + +inst_2981: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x12 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xcbff; + valaddr_reg:x6; val_offset:5912*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5912*FLEN/8, x7, x2, x4) + +inst_2982: +// fs1 == 1 and fe1 == 0x12 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xcbff; op2val:0xfbff; + valaddr_reg:x6; val_offset:5914*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5914*FLEN/8, x7, x2, x4) + +inst_2983: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x12 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xc800; + valaddr_reg:x6; val_offset:5916*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5916*FLEN/8, x7, x2, x4) + +inst_2984: +// fs1 == 1 and fe1 == 0x12 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc800; op2val:0xfbff; + valaddr_reg:x6; val_offset:5918*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5918*FLEN/8, x7, x2, x4) + +inst_2985: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x12 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xc9ff; + valaddr_reg:x6; val_offset:5920*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5920*FLEN/8, x7, x2, x4) + +inst_2986: +// fs1 == 1 and fe1 == 0x12 and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc9ff; op2val:0xfbff; + valaddr_reg:x6; val_offset:5922*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5922*FLEN/8, x7, x2, x4) + +inst_2987: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x12 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xca00; + valaddr_reg:x6; val_offset:5924*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5924*FLEN/8, x7, x2, x4) + +inst_2988: +// fs1 == 1 and fe1 == 0x12 and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xca00; op2val:0xfbff; + valaddr_reg:x6; val_offset:5926*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5926*FLEN/8, x7, x2, x4) + +inst_2989: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xc8ff; + valaddr_reg:x6; val_offset:5928*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5928*FLEN/8, x7, x2, x4) + +inst_2990: +// fs1 == 1 and fe1 == 0x12 and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc8ff; op2val:0xfbff; + valaddr_reg:x6; val_offset:5930*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5930*FLEN/8, x7, x2, x4) + +inst_2991: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x12 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xcb00; + valaddr_reg:x6; val_offset:5932*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5932*FLEN/8, x7, x2, x4) + +inst_2992: +// fs1 == 1 and fe1 == 0x12 and fm1 == 0x300 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xcb00; op2val:0xfbff; + valaddr_reg:x6; val_offset:5934*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5934*FLEN/8, x7, x2, x4) + +inst_2993: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x12 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xc87f; + valaddr_reg:x6; val_offset:5936*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5936*FLEN/8, x7, x2, x4) + +inst_2994: +// fs1 == 1 and fe1 == 0x12 and fm1 == 0x07f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc87f; op2val:0xfbff; + valaddr_reg:x6; val_offset:5938*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5938*FLEN/8, x7, x2, x4) + +inst_2995: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x12 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xcb80; + valaddr_reg:x6; val_offset:5940*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5940*FLEN/8, x7, x2, x4) + +inst_2996: +// fs1 == 1 and fe1 == 0x12 and fm1 == 0x380 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xcb80; op2val:0xfbff; + valaddr_reg:x6; val_offset:5942*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5942*FLEN/8, x7, x2, x4) + +inst_2997: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x12 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xc83f; + valaddr_reg:x6; val_offset:5944*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5944*FLEN/8, x7, x2, x4) + +inst_2998: +// fs1 == 1 and fe1 == 0x12 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc83f; op2val:0xfbff; + valaddr_reg:x6; val_offset:5946*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5946*FLEN/8, x7, x2, x4) + +inst_2999: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x12 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xcbc0; + valaddr_reg:x6; val_offset:5948*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5948*FLEN/8, x7, x2, x4) + +inst_3000: +// fs1 == 1 and fe1 == 0x12 and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xcbc0; op2val:0xfbff; + valaddr_reg:x6; val_offset:5950*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5950*FLEN/8, x7, x2, x4) + +inst_3001: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x12 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xc81f; + valaddr_reg:x6; val_offset:5952*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5952*FLEN/8, x7, x2, x4) + +inst_3002: +// fs1 == 1 and fe1 == 0x12 and fm1 == 0x01f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc81f; op2val:0xfbff; + valaddr_reg:x6; val_offset:5954*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5954*FLEN/8, x7, x2, x4) + +inst_3003: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x12 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xcbe0; + valaddr_reg:x6; val_offset:5956*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5956*FLEN/8, x7, x2, x4) + +inst_3004: +// fs1 == 1 and fe1 == 0x12 and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xcbe0; op2val:0xfbff; + valaddr_reg:x6; val_offset:5958*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5958*FLEN/8, x7, x2, x4) + +inst_3005: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x12 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xc80f; + valaddr_reg:x6; val_offset:5960*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5960*FLEN/8, x7, x2, x4) + +inst_3006: +// fs1 == 1 and fe1 == 0x12 and fm1 == 0x00f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc80f; op2val:0xfbff; + valaddr_reg:x6; val_offset:5962*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5962*FLEN/8, x7, x2, x4) + +inst_3007: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x12 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xcbf0; + valaddr_reg:x6; val_offset:5964*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5964*FLEN/8, x7, x2, x4) + +inst_3008: +// fs1 == 1 and fe1 == 0x12 and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xcbf0; op2val:0xfbff; + valaddr_reg:x6; val_offset:5966*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5966*FLEN/8, x7, x2, x4) + +inst_3009: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x12 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xc807; + valaddr_reg:x6; val_offset:5968*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5968*FLEN/8, x7, x2, x4) + +inst_3010: +// fs1 == 1 and fe1 == 0x12 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc807; op2val:0xfbff; + valaddr_reg:x6; val_offset:5970*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5970*FLEN/8, x7, x2, x4) + +inst_3011: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x12 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xcbf8; + valaddr_reg:x6; val_offset:5972*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5972*FLEN/8, x7, x2, x4) + +inst_3012: +// fs1 == 1 and fe1 == 0x12 and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xcbf8; op2val:0xfbff; + valaddr_reg:x6; val_offset:5974*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5974*FLEN/8, x7, x2, x4) + +inst_3013: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x12 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xc803; + valaddr_reg:x6; val_offset:5976*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5976*FLEN/8, x7, x2, x4) + +inst_3014: +// fs1 == 1 and fe1 == 0x12 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc803; op2val:0xfbff; + valaddr_reg:x6; val_offset:5978*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5978*FLEN/8, x7, x2, x4) + +inst_3015: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x12 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xcbfc; + valaddr_reg:x6; val_offset:5980*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5980*FLEN/8, x7, x2, x4) + +inst_3016: +// fs1 == 1 and fe1 == 0x12 and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xcbfc; op2val:0xfbff; + valaddr_reg:x6; val_offset:5982*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5982*FLEN/8, x7, x2, x4) + +inst_3017: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x12 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xc801; + valaddr_reg:x6; val_offset:5984*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5984*FLEN/8, x7, x2, x4) + +inst_3018: +// fs1 == 1 and fe1 == 0x12 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc801; op2val:0xfbff; + valaddr_reg:x6; val_offset:5986*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5986*FLEN/8, x7, x2, x4) + +inst_3019: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x12 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xcbfe; + valaddr_reg:x6; val_offset:5988*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5988*FLEN/8, x7, x2, x4) + +inst_3020: +// fs1 == 1 and fe1 == 0x12 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xcbfe; op2val:0xfbff; + valaddr_reg:x6; val_offset:5990*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5990*FLEN/8, x7, x2, x4) + +inst_3021: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfbfe; + valaddr_reg:x6; val_offset:5992*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5992*FLEN/8, x7, x2, x4) + +inst_3022: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbfe; op2val:0xfbff; + valaddr_reg:x6; val_offset:5994*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5994*FLEN/8, x7, x2, x4) + +inst_3023: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf801; + valaddr_reg:x6; val_offset:5996*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5996*FLEN/8, x7, x2, x4) + +inst_3024: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf801; op2val:0xfbff; + valaddr_reg:x6; val_offset:5998*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 5998*FLEN/8, x7, x2, x4) + +inst_3025: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1b6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf9b6; + valaddr_reg:x6; val_offset:6000*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6000*FLEN/8, x7, x2, x4) + +inst_3026: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x1b6 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf9b6; op2val:0xfbff; + valaddr_reg:x6; val_offset:6002*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6002*FLEN/8, x7, x2, x4) + +inst_3027: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x36d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfb6d; + valaddr_reg:x6; val_offset:6004*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6004*FLEN/8, x7, x2, x4) + +inst_3028: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x36d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb6d; op2val:0xfbff; + valaddr_reg:x6; val_offset:6006*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6006*FLEN/8, x7, x2, x4) + +inst_3029: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0cc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf8cc; + valaddr_reg:x6; val_offset:6008*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6008*FLEN/8, x7, x2, x4) + +inst_3030: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x0cc and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf8cc; op2val:0xfbff; + valaddr_reg:x6; val_offset:6010*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6010*FLEN/8, x7, x2, x4) + +inst_3031: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x333 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfb33; + valaddr_reg:x6; val_offset:6012*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6012*FLEN/8, x7, x2, x4) + +inst_3032: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x333 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb33; op2val:0xfbff; + valaddr_reg:x6; val_offset:6014*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6014*FLEN/8, x7, x2, x4) + +inst_3033: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1dd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf9dd; + valaddr_reg:x6; val_offset:6016*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6016*FLEN/8, x7, x2, x4) + +inst_3034: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x1dd and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf9dd; op2val:0xfbff; + valaddr_reg:x6; val_offset:6018*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6018*FLEN/8, x7, x2, x4) + +inst_3035: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x222 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfa22; + valaddr_reg:x6; val_offset:6020*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6020*FLEN/8, x7, x2, x4) + +inst_3036: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x222 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa22; op2val:0xfbff; + valaddr_reg:x6; val_offset:6022*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6022*FLEN/8, x7, x2, x4) + +inst_3037: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x124 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf924; + valaddr_reg:x6; val_offset:6024*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6024*FLEN/8, x7, x2, x4) + +inst_3038: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x124 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf924; op2val:0xfbff; + valaddr_reg:x6; val_offset:6026*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6026*FLEN/8, x7, x2, x4) + +inst_3039: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2db and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfadb; + valaddr_reg:x6; val_offset:6028*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6028*FLEN/8, x7, x2, x4) + +inst_3040: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x2db and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfadb; op2val:0xfbff; + valaddr_reg:x6; val_offset:6030*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6030*FLEN/8, x7, x2, x4) + +inst_3041: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x199 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf999; + valaddr_reg:x6; val_offset:6032*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6032*FLEN/8, x7, x2, x4) + +inst_3042: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x199 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf999; op2val:0xfbff; + valaddr_reg:x6; val_offset:6034*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6034*FLEN/8, x7, x2, x4) + +inst_3043: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x266 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfa66; + valaddr_reg:x6; val_offset:6036*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6036*FLEN/8, x7, x2, x4) + +inst_3044: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x266 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa66; op2val:0xfbff; + valaddr_reg:x6; val_offset:6038*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6038*FLEN/8, x7, x2, x4) + +inst_3045: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x19 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x67ff; + valaddr_reg:x6; val_offset:6040*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6040*FLEN/8, x7, x2, x4) + +inst_3046: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x67ff; op2val:0xfbff; + valaddr_reg:x6; val_offset:6042*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6042*FLEN/8, x7, x2, x4) + +inst_3047: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x19 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x6400; + valaddr_reg:x6; val_offset:6044*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6044*FLEN/8, x7, x2, x4) + +inst_3048: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6400; op2val:0xfbff; + valaddr_reg:x6; val_offset:6046*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6046*FLEN/8, x7, x2, x4) + +inst_3049: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x19 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x65ff; + valaddr_reg:x6; val_offset:6048*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6048*FLEN/8, x7, x2, x4) + +inst_3050: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x65ff; op2val:0xfbff; + valaddr_reg:x6; val_offset:6050*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6050*FLEN/8, x7, x2, x4) + +inst_3051: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x19 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x6600; + valaddr_reg:x6; val_offset:6052*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6052*FLEN/8, x7, x2, x4) + +inst_3052: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6600; op2val:0xfbff; + valaddr_reg:x6; val_offset:6054*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6054*FLEN/8, x7, x2, x4) + +inst_3053: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x19 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x64ff; + valaddr_reg:x6; val_offset:6056*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6056*FLEN/8, x7, x2, x4) + +inst_3054: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x64ff; op2val:0xfbff; + valaddr_reg:x6; val_offset:6058*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6058*FLEN/8, x7, x2, x4) + +inst_3055: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x19 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x6700; + valaddr_reg:x6; val_offset:6060*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6060*FLEN/8, x7, x2, x4) + +inst_3056: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x300 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6700; op2val:0xfbff; + valaddr_reg:x6; val_offset:6062*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6062*FLEN/8, x7, x2, x4) + +inst_3057: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x19 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x647f; + valaddr_reg:x6; val_offset:6064*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6064*FLEN/8, x7, x2, x4) + +inst_3058: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x07f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x647f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6066*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6066*FLEN/8, x7, x2, x4) + +inst_3059: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x19 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x6780; + valaddr_reg:x6; val_offset:6068*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6068*FLEN/8, x7, x2, x4) + +inst_3060: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x380 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6780; op2val:0xfbff; + valaddr_reg:x6; val_offset:6070*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6070*FLEN/8, x7, x2, x4) + +inst_3061: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x19 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x643f; + valaddr_reg:x6; val_offset:6072*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6072*FLEN/8, x7, x2, x4) + +inst_3062: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x643f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6074*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6074*FLEN/8, x7, x2, x4) + +inst_3063: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x19 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x67c0; + valaddr_reg:x6; val_offset:6076*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6076*FLEN/8, x7, x2, x4) + +inst_3064: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x67c0; op2val:0xfbff; + valaddr_reg:x6; val_offset:6078*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6078*FLEN/8, x7, x2, x4) + +inst_3065: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x19 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x641f; + valaddr_reg:x6; val_offset:6080*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6080*FLEN/8, x7, x2, x4) + +inst_3066: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x01f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x641f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6082*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6082*FLEN/8, x7, x2, x4) + +inst_3067: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x19 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x67e0; + valaddr_reg:x6; val_offset:6084*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6084*FLEN/8, x7, x2, x4) + +inst_3068: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x67e0; op2val:0xfbff; + valaddr_reg:x6; val_offset:6086*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6086*FLEN/8, x7, x2, x4) + +inst_3069: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x19 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x640f; + valaddr_reg:x6; val_offset:6088*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6088*FLEN/8, x7, x2, x4) + +inst_3070: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x00f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x640f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6090*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6090*FLEN/8, x7, x2, x4) + +inst_3071: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x19 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x67f0; + valaddr_reg:x6; val_offset:6092*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6092*FLEN/8, x7, x2, x4) + +inst_3072: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x67f0; op2val:0xfbff; + valaddr_reg:x6; val_offset:6094*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6094*FLEN/8, x7, x2, x4) + +inst_3073: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x19 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x6407; + valaddr_reg:x6; val_offset:6096*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6096*FLEN/8, x7, x2, x4) + +inst_3074: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6407; op2val:0xfbff; + valaddr_reg:x6; val_offset:6098*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6098*FLEN/8, x7, x2, x4) + +inst_3075: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x19 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x67f8; + valaddr_reg:x6; val_offset:6100*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6100*FLEN/8, x7, x2, x4) + +inst_3076: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x67f8; op2val:0xfbff; + valaddr_reg:x6; val_offset:6102*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6102*FLEN/8, x7, x2, x4) + +inst_3077: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x19 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x6403; + valaddr_reg:x6; val_offset:6104*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6104*FLEN/8, x7, x2, x4) + +inst_3078: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6403; op2val:0xfbff; + valaddr_reg:x6; val_offset:6106*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6106*FLEN/8, x7, x2, x4) + +inst_3079: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x19 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x67fc; + valaddr_reg:x6; val_offset:6108*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6108*FLEN/8, x7, x2, x4) + +inst_3080: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x67fc; op2val:0xfbff; + valaddr_reg:x6; val_offset:6110*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6110*FLEN/8, x7, x2, x4) + +inst_3081: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x19 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x6401; + valaddr_reg:x6; val_offset:6112*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6112*FLEN/8, x7, x2, x4) + +inst_3082: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6401; op2val:0xfbff; + valaddr_reg:x6; val_offset:6114*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6114*FLEN/8, x7, x2, x4) + +inst_3083: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x19 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x67fe; + valaddr_reg:x6; val_offset:6116*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6116*FLEN/8, x7, x2, x4) + +inst_3084: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x67fe; op2val:0xfbff; + valaddr_reg:x6; val_offset:6118*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6118*FLEN/8, x7, x2, x4) + +inst_3085: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1a and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xebff; + valaddr_reg:x6; val_offset:6120*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6120*FLEN/8, x7, x2, x4) + +inst_3086: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xebff; op2val:0xfbff; + valaddr_reg:x6; val_offset:6122*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6122*FLEN/8, x7, x2, x4) + +inst_3087: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1a and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xe800; + valaddr_reg:x6; val_offset:6124*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6124*FLEN/8, x7, x2, x4) + +inst_3088: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xe800; op2val:0xfbff; + valaddr_reg:x6; val_offset:6126*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6126*FLEN/8, x7, x2, x4) + +inst_3089: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1a and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xe9ff; + valaddr_reg:x6; val_offset:6128*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6128*FLEN/8, x7, x2, x4) + +inst_3090: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xe9ff; op2val:0xfbff; + valaddr_reg:x6; val_offset:6130*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6130*FLEN/8, x7, x2, x4) + +inst_3091: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1a and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xea00; + valaddr_reg:x6; val_offset:6132*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6132*FLEN/8, x7, x2, x4) + +inst_3092: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xea00; op2val:0xfbff; + valaddr_reg:x6; val_offset:6134*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6134*FLEN/8, x7, x2, x4) + +inst_3093: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1a and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xe8ff; + valaddr_reg:x6; val_offset:6136*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6136*FLEN/8, x7, x2, x4) + +inst_3094: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xe8ff; op2val:0xfbff; + valaddr_reg:x6; val_offset:6138*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6138*FLEN/8, x7, x2, x4) + +inst_3095: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1a and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xeb00; + valaddr_reg:x6; val_offset:6140*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6140*FLEN/8, x7, x2, x4) + +inst_3096: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x300 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xeb00; op2val:0xfbff; + valaddr_reg:x6; val_offset:6142*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6142*FLEN/8, x7, x2, x4) + +inst_3097: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1a and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xe87f; + valaddr_reg:x6; val_offset:6144*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6144*FLEN/8, x7, x2, x4) + +inst_3098: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x07f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xe87f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6146*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6146*FLEN/8, x7, x2, x4) + +inst_3099: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1a and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xeb80; + valaddr_reg:x6; val_offset:6148*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6148*FLEN/8, x7, x2, x4) + +inst_3100: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x380 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xeb80; op2val:0xfbff; + valaddr_reg:x6; val_offset:6150*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6150*FLEN/8, x7, x2, x4) +RVTEST_SIGBASE(x2,signature_x2_26) + +inst_3101: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1a and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xe83f; + valaddr_reg:x6; val_offset:6152*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6152*FLEN/8, x7, x2, x4) + +inst_3102: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x03f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xe83f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6154*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6154*FLEN/8, x7, x2, x4) + +inst_3103: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1a and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xebc0; + valaddr_reg:x6; val_offset:6156*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6156*FLEN/8, x7, x2, x4) + +inst_3104: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xebc0; op2val:0xfbff; + valaddr_reg:x6; val_offset:6158*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6158*FLEN/8, x7, x2, x4) + +inst_3105: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1a and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xe81f; + valaddr_reg:x6; val_offset:6160*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6160*FLEN/8, x7, x2, x4) + +inst_3106: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x01f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xe81f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6162*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6162*FLEN/8, x7, x2, x4) + +inst_3107: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1a and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xebe0; + valaddr_reg:x6; val_offset:6164*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6164*FLEN/8, x7, x2, x4) + +inst_3108: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xebe0; op2val:0xfbff; + valaddr_reg:x6; val_offset:6166*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6166*FLEN/8, x7, x2, x4) + +inst_3109: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1a and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xe80f; + valaddr_reg:x6; val_offset:6168*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6168*FLEN/8, x7, x2, x4) + +inst_3110: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x00f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xe80f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6170*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6170*FLEN/8, x7, x2, x4) + +inst_3111: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1a and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xebf0; + valaddr_reg:x6; val_offset:6172*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6172*FLEN/8, x7, x2, x4) + +inst_3112: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xebf0; op2val:0xfbff; + valaddr_reg:x6; val_offset:6174*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6174*FLEN/8, x7, x2, x4) + +inst_3113: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1a and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xe807; + valaddr_reg:x6; val_offset:6176*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6176*FLEN/8, x7, x2, x4) + +inst_3114: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x007 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xe807; op2val:0xfbff; + valaddr_reg:x6; val_offset:6178*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6178*FLEN/8, x7, x2, x4) + +inst_3115: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1a and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xebf8; + valaddr_reg:x6; val_offset:6180*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6180*FLEN/8, x7, x2, x4) + +inst_3116: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xebf8; op2val:0xfbff; + valaddr_reg:x6; val_offset:6182*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6182*FLEN/8, x7, x2, x4) + +inst_3117: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1a and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xe803; + valaddr_reg:x6; val_offset:6184*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6184*FLEN/8, x7, x2, x4) + +inst_3118: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x003 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xe803; op2val:0xfbff; + valaddr_reg:x6; val_offset:6186*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6186*FLEN/8, x7, x2, x4) + +inst_3119: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1a and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xebfc; + valaddr_reg:x6; val_offset:6188*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6188*FLEN/8, x7, x2, x4) + +inst_3120: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xebfc; op2val:0xfbff; + valaddr_reg:x6; val_offset:6190*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6190*FLEN/8, x7, x2, x4) + +inst_3121: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1a and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xe801; + valaddr_reg:x6; val_offset:6192*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6192*FLEN/8, x7, x2, x4) + +inst_3122: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xe801; op2val:0xfbff; + valaddr_reg:x6; val_offset:6194*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6194*FLEN/8, x7, x2, x4) + +inst_3123: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1a and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xebfe; + valaddr_reg:x6; val_offset:6196*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6196*FLEN/8, x7, x2, x4) + +inst_3124: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xebfe; op2val:0xfbff; + valaddr_reg:x6; val_offset:6198*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6198*FLEN/8, x7, x2, x4) + +inst_3125: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1b and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xefff; + valaddr_reg:x6; val_offset:6200*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6200*FLEN/8, x7, x2, x4) + +inst_3126: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xefff; op2val:0xfbff; + valaddr_reg:x6; val_offset:6202*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6202*FLEN/8, x7, x2, x4) + +inst_3127: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1b and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xec00; + valaddr_reg:x6; val_offset:6204*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6204*FLEN/8, x7, x2, x4) + +inst_3128: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xec00; op2val:0xfbff; + valaddr_reg:x6; val_offset:6206*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6206*FLEN/8, x7, x2, x4) + +inst_3129: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1b and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xedff; + valaddr_reg:x6; val_offset:6208*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6208*FLEN/8, x7, x2, x4) + +inst_3130: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xedff; op2val:0xfbff; + valaddr_reg:x6; val_offset:6210*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6210*FLEN/8, x7, x2, x4) + +inst_3131: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1b and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xee00; + valaddr_reg:x6; val_offset:6212*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6212*FLEN/8, x7, x2, x4) + +inst_3132: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xee00; op2val:0xfbff; + valaddr_reg:x6; val_offset:6214*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6214*FLEN/8, x7, x2, x4) + +inst_3133: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1b and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xecff; + valaddr_reg:x6; val_offset:6216*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6216*FLEN/8, x7, x2, x4) + +inst_3134: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xecff; op2val:0xfbff; + valaddr_reg:x6; val_offset:6218*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6218*FLEN/8, x7, x2, x4) + +inst_3135: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1b and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xef00; + valaddr_reg:x6; val_offset:6220*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6220*FLEN/8, x7, x2, x4) + +inst_3136: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x300 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xef00; op2val:0xfbff; + valaddr_reg:x6; val_offset:6222*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6222*FLEN/8, x7, x2, x4) + +inst_3137: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1b and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xec7f; + valaddr_reg:x6; val_offset:6224*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6224*FLEN/8, x7, x2, x4) + +inst_3138: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x07f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xec7f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6226*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6226*FLEN/8, x7, x2, x4) + +inst_3139: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1b and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xef80; + valaddr_reg:x6; val_offset:6228*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6228*FLEN/8, x7, x2, x4) + +inst_3140: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x380 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xef80; op2val:0xfbff; + valaddr_reg:x6; val_offset:6230*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6230*FLEN/8, x7, x2, x4) + +inst_3141: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1b and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xec3f; + valaddr_reg:x6; val_offset:6232*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6232*FLEN/8, x7, x2, x4) + +inst_3142: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x03f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xec3f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6234*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6234*FLEN/8, x7, x2, x4) + +inst_3143: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1b and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xefc0; + valaddr_reg:x6; val_offset:6236*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6236*FLEN/8, x7, x2, x4) + +inst_3144: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xefc0; op2val:0xfbff; + valaddr_reg:x6; val_offset:6238*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6238*FLEN/8, x7, x2, x4) + +inst_3145: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1b and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xec1f; + valaddr_reg:x6; val_offset:6240*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6240*FLEN/8, x7, x2, x4) + +inst_3146: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x01f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xec1f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6242*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6242*FLEN/8, x7, x2, x4) + +inst_3147: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1b and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xefe0; + valaddr_reg:x6; val_offset:6244*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6244*FLEN/8, x7, x2, x4) + +inst_3148: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xefe0; op2val:0xfbff; + valaddr_reg:x6; val_offset:6246*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6246*FLEN/8, x7, x2, x4) + +inst_3149: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1b and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xec0f; + valaddr_reg:x6; val_offset:6248*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6248*FLEN/8, x7, x2, x4) + +inst_3150: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x00f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xec0f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6250*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6250*FLEN/8, x7, x2, x4) + +inst_3151: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1b and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xeff0; + valaddr_reg:x6; val_offset:6252*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6252*FLEN/8, x7, x2, x4) + +inst_3152: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xeff0; op2val:0xfbff; + valaddr_reg:x6; val_offset:6254*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6254*FLEN/8, x7, x2, x4) + +inst_3153: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1b and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xec07; + valaddr_reg:x6; val_offset:6256*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6256*FLEN/8, x7, x2, x4) + +inst_3154: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x007 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xec07; op2val:0xfbff; + valaddr_reg:x6; val_offset:6258*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6258*FLEN/8, x7, x2, x4) + +inst_3155: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1b and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xeff8; + valaddr_reg:x6; val_offset:6260*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6260*FLEN/8, x7, x2, x4) + +inst_3156: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xeff8; op2val:0xfbff; + valaddr_reg:x6; val_offset:6262*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6262*FLEN/8, x7, x2, x4) + +inst_3157: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1b and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xec03; + valaddr_reg:x6; val_offset:6264*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6264*FLEN/8, x7, x2, x4) + +inst_3158: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x003 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xec03; op2val:0xfbff; + valaddr_reg:x6; val_offset:6266*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6266*FLEN/8, x7, x2, x4) + +inst_3159: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1b and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xeffc; + valaddr_reg:x6; val_offset:6268*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6268*FLEN/8, x7, x2, x4) + +inst_3160: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xeffc; op2val:0xfbff; + valaddr_reg:x6; val_offset:6270*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6270*FLEN/8, x7, x2, x4) + +inst_3161: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1b and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xec01; + valaddr_reg:x6; val_offset:6272*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6272*FLEN/8, x7, x2, x4) + +inst_3162: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xec01; op2val:0xfbff; + valaddr_reg:x6; val_offset:6274*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6274*FLEN/8, x7, x2, x4) + +inst_3163: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1b and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xeffe; + valaddr_reg:x6; val_offset:6276*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6276*FLEN/8, x7, x2, x4) + +inst_3164: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xeffe; op2val:0xfbff; + valaddr_reg:x6; val_offset:6278*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6278*FLEN/8, x7, x2, x4) + +inst_3165: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf3ff; + valaddr_reg:x6; val_offset:6280*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6280*FLEN/8, x7, x2, x4) + +inst_3166: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3ff; op2val:0xfbff; + valaddr_reg:x6; val_offset:6282*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6282*FLEN/8, x7, x2, x4) + +inst_3167: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1c and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf000; + valaddr_reg:x6; val_offset:6284*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6284*FLEN/8, x7, x2, x4) + +inst_3168: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf000; op2val:0xfbff; + valaddr_reg:x6; val_offset:6286*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6286*FLEN/8, x7, x2, x4) + +inst_3169: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1c and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf1ff; + valaddr_reg:x6; val_offset:6288*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6288*FLEN/8, x7, x2, x4) + +inst_3170: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf1ff; op2val:0xfbff; + valaddr_reg:x6; val_offset:6290*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6290*FLEN/8, x7, x2, x4) + +inst_3171: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1c and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf200; + valaddr_reg:x6; val_offset:6292*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6292*FLEN/8, x7, x2, x4) + +inst_3172: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf200; op2val:0xfbff; + valaddr_reg:x6; val_offset:6294*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6294*FLEN/8, x7, x2, x4) + +inst_3173: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf0ff; + valaddr_reg:x6; val_offset:6296*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6296*FLEN/8, x7, x2, x4) + +inst_3174: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0ff; op2val:0xfbff; + valaddr_reg:x6; val_offset:6298*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6298*FLEN/8, x7, x2, x4) + +inst_3175: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1c and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf300; + valaddr_reg:x6; val_offset:6300*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6300*FLEN/8, x7, x2, x4) + +inst_3176: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x300 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf300; op2val:0xfbff; + valaddr_reg:x6; val_offset:6302*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6302*FLEN/8, x7, x2, x4) + +inst_3177: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1c and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf07f; + valaddr_reg:x6; val_offset:6304*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6304*FLEN/8, x7, x2, x4) + +inst_3178: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x07f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf07f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6306*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6306*FLEN/8, x7, x2, x4) + +inst_3179: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1c and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf380; + valaddr_reg:x6; val_offset:6308*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6308*FLEN/8, x7, x2, x4) + +inst_3180: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x380 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf380; op2val:0xfbff; + valaddr_reg:x6; val_offset:6310*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6310*FLEN/8, x7, x2, x4) + +inst_3181: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1c and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf03f; + valaddr_reg:x6; val_offset:6312*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6312*FLEN/8, x7, x2, x4) + +inst_3182: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x03f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf03f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6314*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6314*FLEN/8, x7, x2, x4) + +inst_3183: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf3c0; + valaddr_reg:x6; val_offset:6316*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6316*FLEN/8, x7, x2, x4) + +inst_3184: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3c0; op2val:0xfbff; + valaddr_reg:x6; val_offset:6318*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6318*FLEN/8, x7, x2, x4) + +inst_3185: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1c and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf01f; + valaddr_reg:x6; val_offset:6320*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6320*FLEN/8, x7, x2, x4) + +inst_3186: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x01f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf01f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6322*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6322*FLEN/8, x7, x2, x4) + +inst_3187: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf3e0; + valaddr_reg:x6; val_offset:6324*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6324*FLEN/8, x7, x2, x4) + +inst_3188: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3e0; op2val:0xfbff; + valaddr_reg:x6; val_offset:6326*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6326*FLEN/8, x7, x2, x4) + +inst_3189: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1c and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf00f; + valaddr_reg:x6; val_offset:6328*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6328*FLEN/8, x7, x2, x4) + +inst_3190: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x00f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf00f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6330*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6330*FLEN/8, x7, x2, x4) + +inst_3191: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf3f0; + valaddr_reg:x6; val_offset:6332*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6332*FLEN/8, x7, x2, x4) + +inst_3192: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3f0; op2val:0xfbff; + valaddr_reg:x6; val_offset:6334*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6334*FLEN/8, x7, x2, x4) + +inst_3193: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1c and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf007; + valaddr_reg:x6; val_offset:6336*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6336*FLEN/8, x7, x2, x4) + +inst_3194: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x007 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf007; op2val:0xfbff; + valaddr_reg:x6; val_offset:6338*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6338*FLEN/8, x7, x2, x4) + +inst_3195: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf3f8; + valaddr_reg:x6; val_offset:6340*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6340*FLEN/8, x7, x2, x4) + +inst_3196: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3f8; op2val:0xfbff; + valaddr_reg:x6; val_offset:6342*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6342*FLEN/8, x7, x2, x4) + +inst_3197: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1c and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf003; + valaddr_reg:x6; val_offset:6344*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6344*FLEN/8, x7, x2, x4) + +inst_3198: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x003 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf003; op2val:0xfbff; + valaddr_reg:x6; val_offset:6346*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6346*FLEN/8, x7, x2, x4) + +inst_3199: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf3fc; + valaddr_reg:x6; val_offset:6348*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6348*FLEN/8, x7, x2, x4) + +inst_3200: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3fc; op2val:0xfbff; + valaddr_reg:x6; val_offset:6350*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6350*FLEN/8, x7, x2, x4) + +inst_3201: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1c and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf001; + valaddr_reg:x6; val_offset:6352*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6352*FLEN/8, x7, x2, x4) + +inst_3202: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf001; op2val:0xfbff; + valaddr_reg:x6; val_offset:6354*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6354*FLEN/8, x7, x2, x4) + +inst_3203: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf3fe; + valaddr_reg:x6; val_offset:6356*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6356*FLEN/8, x7, x2, x4) + +inst_3204: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3fe; op2val:0xfbff; + valaddr_reg:x6; val_offset:6358*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6358*FLEN/8, x7, x2, x4) + +inst_3205: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf7ff; + valaddr_reg:x6; val_offset:6360*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6360*FLEN/8, x7, x2, x4) + +inst_3206: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf7ff; op2val:0xfbff; + valaddr_reg:x6; val_offset:6362*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6362*FLEN/8, x7, x2, x4) + +inst_3207: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1d and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf400; + valaddr_reg:x6; val_offset:6364*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6364*FLEN/8, x7, x2, x4) + +inst_3208: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf400; op2val:0xfbff; + valaddr_reg:x6; val_offset:6366*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6366*FLEN/8, x7, x2, x4) + +inst_3209: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1d and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf5ff; + valaddr_reg:x6; val_offset:6368*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6368*FLEN/8, x7, x2, x4) + +inst_3210: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf5ff; op2val:0xfbff; + valaddr_reg:x6; val_offset:6370*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6370*FLEN/8, x7, x2, x4) + +inst_3211: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1d and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf600; + valaddr_reg:x6; val_offset:6372*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6372*FLEN/8, x7, x2, x4) + +inst_3212: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf600; op2val:0xfbff; + valaddr_reg:x6; val_offset:6374*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6374*FLEN/8, x7, x2, x4) + +inst_3213: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1d and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf4ff; + valaddr_reg:x6; val_offset:6376*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6376*FLEN/8, x7, x2, x4) + +inst_3214: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf4ff; op2val:0xfbff; + valaddr_reg:x6; val_offset:6378*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6378*FLEN/8, x7, x2, x4) + +inst_3215: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1d and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf700; + valaddr_reg:x6; val_offset:6380*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6380*FLEN/8, x7, x2, x4) + +inst_3216: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x300 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf700; op2val:0xfbff; + valaddr_reg:x6; val_offset:6382*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6382*FLEN/8, x7, x2, x4) + +inst_3217: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1d and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf47f; + valaddr_reg:x6; val_offset:6384*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6384*FLEN/8, x7, x2, x4) + +inst_3218: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x07f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf47f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6386*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6386*FLEN/8, x7, x2, x4) + +inst_3219: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1d and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf780; + valaddr_reg:x6; val_offset:6388*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6388*FLEN/8, x7, x2, x4) + +inst_3220: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x380 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf780; op2val:0xfbff; + valaddr_reg:x6; val_offset:6390*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6390*FLEN/8, x7, x2, x4) + +inst_3221: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1d and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf43f; + valaddr_reg:x6; val_offset:6392*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6392*FLEN/8, x7, x2, x4) + +inst_3222: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x03f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf43f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6394*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6394*FLEN/8, x7, x2, x4) + +inst_3223: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf7c0; + valaddr_reg:x6; val_offset:6396*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6396*FLEN/8, x7, x2, x4) + +inst_3224: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf7c0; op2val:0xfbff; + valaddr_reg:x6; val_offset:6398*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6398*FLEN/8, x7, x2, x4) + +inst_3225: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1d and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf41f; + valaddr_reg:x6; val_offset:6400*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6400*FLEN/8, x7, x2, x4) + +inst_3226: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x01f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf41f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6402*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6402*FLEN/8, x7, x2, x4) + +inst_3227: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf7e0; + valaddr_reg:x6; val_offset:6404*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6404*FLEN/8, x7, x2, x4) + +inst_3228: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf7e0; op2val:0xfbff; + valaddr_reg:x6; val_offset:6406*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6406*FLEN/8, x7, x2, x4) +RVTEST_SIGBASE(x2,signature_x2_27) + +inst_3229: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1d and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf40f; + valaddr_reg:x6; val_offset:6408*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6408*FLEN/8, x7, x2, x4) + +inst_3230: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x00f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf40f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6410*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6410*FLEN/8, x7, x2, x4) + +inst_3231: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf7f0; + valaddr_reg:x6; val_offset:6412*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6412*FLEN/8, x7, x2, x4) + +inst_3232: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf7f0; op2val:0xfbff; + valaddr_reg:x6; val_offset:6414*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6414*FLEN/8, x7, x2, x4) + +inst_3233: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1d and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf407; + valaddr_reg:x6; val_offset:6416*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6416*FLEN/8, x7, x2, x4) + +inst_3234: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x007 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf407; op2val:0xfbff; + valaddr_reg:x6; val_offset:6418*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6418*FLEN/8, x7, x2, x4) + +inst_3235: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf7f8; + valaddr_reg:x6; val_offset:6420*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6420*FLEN/8, x7, x2, x4) + +inst_3236: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf7f8; op2val:0xfbff; + valaddr_reg:x6; val_offset:6422*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6422*FLEN/8, x7, x2, x4) + +inst_3237: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1d and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf403; + valaddr_reg:x6; val_offset:6424*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6424*FLEN/8, x7, x2, x4) + +inst_3238: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x003 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf403; op2val:0xfbff; + valaddr_reg:x6; val_offset:6426*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6426*FLEN/8, x7, x2, x4) + +inst_3239: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf7fc; + valaddr_reg:x6; val_offset:6428*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6428*FLEN/8, x7, x2, x4) + +inst_3240: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf7fc; op2val:0xfbff; + valaddr_reg:x6; val_offset:6430*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6430*FLEN/8, x7, x2, x4) + +inst_3241: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1d and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf401; + valaddr_reg:x6; val_offset:6432*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6432*FLEN/8, x7, x2, x4) + +inst_3242: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf401; op2val:0xfbff; + valaddr_reg:x6; val_offset:6434*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6434*FLEN/8, x7, x2, x4) + +inst_3243: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf7fe; + valaddr_reg:x6; val_offset:6436*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6436*FLEN/8, x7, x2, x4) + +inst_3244: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf7fe; op2val:0xfbff; + valaddr_reg:x6; val_offset:6438*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6438*FLEN/8, x7, x2, x4) + +inst_3245: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfbff; + valaddr_reg:x6; val_offset:6440*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6440*FLEN/8, x7, x2, x4) + +inst_3246: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf800; + valaddr_reg:x6; val_offset:6442*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6442*FLEN/8, x7, x2, x4) + +inst_3247: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf800; op2val:0xfbff; + valaddr_reg:x6; val_offset:6444*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6444*FLEN/8, x7, x2, x4) + +inst_3248: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf9ff; + valaddr_reg:x6; val_offset:6446*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6446*FLEN/8, x7, x2, x4) + +inst_3249: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf9ff; op2val:0xfbff; + valaddr_reg:x6; val_offset:6448*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6448*FLEN/8, x7, x2, x4) + +inst_3250: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfa00; + valaddr_reg:x6; val_offset:6450*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6450*FLEN/8, x7, x2, x4) + +inst_3251: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa00; op2val:0xfbff; + valaddr_reg:x6; val_offset:6452*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6452*FLEN/8, x7, x2, x4) + +inst_3252: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf8ff; + valaddr_reg:x6; val_offset:6454*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6454*FLEN/8, x7, x2, x4) + +inst_3253: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf8ff; op2val:0xfbff; + valaddr_reg:x6; val_offset:6456*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6456*FLEN/8, x7, x2, x4) + +inst_3254: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfb00; + valaddr_reg:x6; val_offset:6458*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6458*FLEN/8, x7, x2, x4) + +inst_3255: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x300 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb00; op2val:0xfbff; + valaddr_reg:x6; val_offset:6460*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6460*FLEN/8, x7, x2, x4) + +inst_3256: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf87f; + valaddr_reg:x6; val_offset:6462*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6462*FLEN/8, x7, x2, x4) + +inst_3257: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x07f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf87f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6464*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6464*FLEN/8, x7, x2, x4) + +inst_3258: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfb80; + valaddr_reg:x6; val_offset:6466*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6466*FLEN/8, x7, x2, x4) + +inst_3259: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x380 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb80; op2val:0xfbff; + valaddr_reg:x6; val_offset:6468*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6468*FLEN/8, x7, x2, x4) + +inst_3260: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf83f; + valaddr_reg:x6; val_offset:6470*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6470*FLEN/8, x7, x2, x4) + +inst_3261: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x03f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf83f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6472*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6472*FLEN/8, x7, x2, x4) + +inst_3262: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfbc0; + valaddr_reg:x6; val_offset:6474*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6474*FLEN/8, x7, x2, x4) + +inst_3263: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbc0; op2val:0xfbff; + valaddr_reg:x6; val_offset:6476*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6476*FLEN/8, x7, x2, x4) + +inst_3264: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf81f; + valaddr_reg:x6; val_offset:6478*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6478*FLEN/8, x7, x2, x4) + +inst_3265: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x01f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf81f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6480*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6480*FLEN/8, x7, x2, x4) + +inst_3266: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfbe0; + valaddr_reg:x6; val_offset:6482*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6482*FLEN/8, x7, x2, x4) + +inst_3267: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbe0; op2val:0xfbff; + valaddr_reg:x6; val_offset:6484*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6484*FLEN/8, x7, x2, x4) + +inst_3268: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf80f; + valaddr_reg:x6; val_offset:6486*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6486*FLEN/8, x7, x2, x4) + +inst_3269: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x00f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf80f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6488*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6488*FLEN/8, x7, x2, x4) + +inst_3270: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfbf0; + valaddr_reg:x6; val_offset:6490*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6490*FLEN/8, x7, x2, x4) + +inst_3271: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbf0; op2val:0xfbff; + valaddr_reg:x6; val_offset:6492*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6492*FLEN/8, x7, x2, x4) + +inst_3272: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf807; + valaddr_reg:x6; val_offset:6494*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6494*FLEN/8, x7, x2, x4) + +inst_3273: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x007 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf807; op2val:0xfbff; + valaddr_reg:x6; val_offset:6496*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6496*FLEN/8, x7, x2, x4) + +inst_3274: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfbf8; + valaddr_reg:x6; val_offset:6498*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6498*FLEN/8, x7, x2, x4) + +inst_3275: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbf8; op2val:0xfbff; + valaddr_reg:x6; val_offset:6500*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6500*FLEN/8, x7, x2, x4) + +inst_3276: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf803; + valaddr_reg:x6; val_offset:6502*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6502*FLEN/8, x7, x2, x4) + +inst_3277: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x003 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf803; op2val:0xfbff; + valaddr_reg:x6; val_offset:6504*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6504*FLEN/8, x7, x2, x4) + +inst_3278: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfbfc; + valaddr_reg:x6; val_offset:6506*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6506*FLEN/8, x7, x2, x4) + +inst_3279: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbfc; op2val:0xfbff; + valaddr_reg:x6; val_offset:6508*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6508*FLEN/8, x7, x2, x4) + +inst_3280: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x83ff; + valaddr_reg:x6; val_offset:6510*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6510*FLEN/8, x7, x2, x4) + +inst_3281: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xfbff; + valaddr_reg:x6; val_offset:6512*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6512*FLEN/8, x7, x2, x4) + +inst_3282: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8001; + valaddr_reg:x6; val_offset:6514*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6514*FLEN/8, x7, x2, x4) + +inst_3283: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xfbff; + valaddr_reg:x6; val_offset:6516*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6516*FLEN/8, x7, x2, x4) + +inst_3284: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x81ff; + valaddr_reg:x6; val_offset:6518*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6518*FLEN/8, x7, x2, x4) + +inst_3285: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x81ff; op2val:0xfbff; + valaddr_reg:x6; val_offset:6520*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6520*FLEN/8, x7, x2, x4) + +inst_3286: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8200; + valaddr_reg:x6; val_offset:6522*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6522*FLEN/8, x7, x2, x4) + +inst_3287: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8200; op2val:0xfbff; + valaddr_reg:x6; val_offset:6524*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6524*FLEN/8, x7, x2, x4) + +inst_3288: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x80ff; + valaddr_reg:x6; val_offset:6526*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6526*FLEN/8, x7, x2, x4) + +inst_3289: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x80ff; op2val:0xfbff; + valaddr_reg:x6; val_offset:6528*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6528*FLEN/8, x7, x2, x4) + +inst_3290: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8300; + valaddr_reg:x6; val_offset:6530*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6530*FLEN/8, x7, x2, x4) + +inst_3291: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x300 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8300; op2val:0xfbff; + valaddr_reg:x6; val_offset:6532*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6532*FLEN/8, x7, x2, x4) + +inst_3292: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x807f; + valaddr_reg:x6; val_offset:6534*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6534*FLEN/8, x7, x2, x4) + +inst_3293: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x07f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x807f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6536*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6536*FLEN/8, x7, x2, x4) + +inst_3294: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8380; + valaddr_reg:x6; val_offset:6538*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6538*FLEN/8, x7, x2, x4) + +inst_3295: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x380 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8380; op2val:0xfbff; + valaddr_reg:x6; val_offset:6540*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6540*FLEN/8, x7, x2, x4) + +inst_3296: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x803f; + valaddr_reg:x6; val_offset:6542*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6542*FLEN/8, x7, x2, x4) + +inst_3297: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x803f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6544*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6544*FLEN/8, x7, x2, x4) + +inst_3298: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x83c0; + valaddr_reg:x6; val_offset:6546*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6546*FLEN/8, x7, x2, x4) + +inst_3299: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83c0; op2val:0xfbff; + valaddr_reg:x6; val_offset:6548*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6548*FLEN/8, x7, x2, x4) + +inst_3300: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x801f; + valaddr_reg:x6; val_offset:6550*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6550*FLEN/8, x7, x2, x4) + +inst_3301: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x01f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x801f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6552*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6552*FLEN/8, x7, x2, x4) + +inst_3302: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x83e0; + valaddr_reg:x6; val_offset:6554*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6554*FLEN/8, x7, x2, x4) + +inst_3303: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83e0; op2val:0xfbff; + valaddr_reg:x6; val_offset:6556*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6556*FLEN/8, x7, x2, x4) + +inst_3304: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x800f; + valaddr_reg:x6; val_offset:6558*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6558*FLEN/8, x7, x2, x4) + +inst_3305: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x00f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x800f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6560*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6560*FLEN/8, x7, x2, x4) + +inst_3306: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x83f0; + valaddr_reg:x6; val_offset:6562*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6562*FLEN/8, x7, x2, x4) + +inst_3307: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83f0; op2val:0xfbff; + valaddr_reg:x6; val_offset:6564*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6564*FLEN/8, x7, x2, x4) + +inst_3308: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8007; + valaddr_reg:x6; val_offset:6566*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6566*FLEN/8, x7, x2, x4) + +inst_3309: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8007; op2val:0xfbff; + valaddr_reg:x6; val_offset:6568*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6568*FLEN/8, x7, x2, x4) + +inst_3310: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x83f8; + valaddr_reg:x6; val_offset:6570*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6570*FLEN/8, x7, x2, x4) + +inst_3311: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83f8; op2val:0xfbff; + valaddr_reg:x6; val_offset:6572*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6572*FLEN/8, x7, x2, x4) + +inst_3312: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8003; + valaddr_reg:x6; val_offset:6574*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6574*FLEN/8, x7, x2, x4) + +inst_3313: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8003; op2val:0xfbff; + valaddr_reg:x6; val_offset:6576*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6576*FLEN/8, x7, x2, x4) + +inst_3314: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x83fc; + valaddr_reg:x6; val_offset:6578*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6578*FLEN/8, x7, x2, x4) + +inst_3315: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fc; op2val:0xfbff; + valaddr_reg:x6; val_offset:6580*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6580*FLEN/8, x7, x2, x4) + +inst_3316: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x83fe; + valaddr_reg:x6; val_offset:6582*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6582*FLEN/8, x7, x2, x4) + +inst_3317: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xfbff; + valaddr_reg:x6; val_offset:6584*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6584*FLEN/8, x7, x2, x4) + +inst_3318: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x87ff; + valaddr_reg:x6; val_offset:6586*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6586*FLEN/8, x7, x2, x4) + +inst_3319: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x87ff; op2val:0xfbff; + valaddr_reg:x6; val_offset:6588*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6588*FLEN/8, x7, x2, x4) + +inst_3320: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8400; + valaddr_reg:x6; val_offset:6590*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6590*FLEN/8, x7, x2, x4) + +inst_3321: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xfbff; + valaddr_reg:x6; val_offset:6592*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6592*FLEN/8, x7, x2, x4) + +inst_3322: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x85ff; + valaddr_reg:x6; val_offset:6594*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6594*FLEN/8, x7, x2, x4) + +inst_3323: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x85ff; op2val:0xfbff; + valaddr_reg:x6; val_offset:6596*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6596*FLEN/8, x7, x2, x4) + +inst_3324: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8600; + valaddr_reg:x6; val_offset:6598*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6598*FLEN/8, x7, x2, x4) + +inst_3325: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8600; op2val:0xfbff; + valaddr_reg:x6; val_offset:6600*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6600*FLEN/8, x7, x2, x4) + +inst_3326: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x84ff; + valaddr_reg:x6; val_offset:6602*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6602*FLEN/8, x7, x2, x4) + +inst_3327: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x84ff; op2val:0xfbff; + valaddr_reg:x6; val_offset:6604*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6604*FLEN/8, x7, x2, x4) + +inst_3328: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8700; + valaddr_reg:x6; val_offset:6606*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6606*FLEN/8, x7, x2, x4) + +inst_3329: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x300 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8700; op2val:0xfbff; + valaddr_reg:x6; val_offset:6608*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6608*FLEN/8, x7, x2, x4) + +inst_3330: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x847f; + valaddr_reg:x6; val_offset:6610*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6610*FLEN/8, x7, x2, x4) + +inst_3331: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x07f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x847f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6612*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6612*FLEN/8, x7, x2, x4) + +inst_3332: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8780; + valaddr_reg:x6; val_offset:6614*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6614*FLEN/8, x7, x2, x4) + +inst_3333: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x380 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8780; op2val:0xfbff; + valaddr_reg:x6; val_offset:6616*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6616*FLEN/8, x7, x2, x4) + +inst_3334: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x843f; + valaddr_reg:x6; val_offset:6618*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6618*FLEN/8, x7, x2, x4) + +inst_3335: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x843f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6620*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6620*FLEN/8, x7, x2, x4) + +inst_3336: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x87c0; + valaddr_reg:x6; val_offset:6622*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6622*FLEN/8, x7, x2, x4) + +inst_3337: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x87c0; op2val:0xfbff; + valaddr_reg:x6; val_offset:6624*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6624*FLEN/8, x7, x2, x4) + +inst_3338: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x841f; + valaddr_reg:x6; val_offset:6626*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6626*FLEN/8, x7, x2, x4) + +inst_3339: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x01f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x841f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6628*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6628*FLEN/8, x7, x2, x4) + +inst_3340: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x87e0; + valaddr_reg:x6; val_offset:6630*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6630*FLEN/8, x7, x2, x4) + +inst_3341: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x87e0; op2val:0xfbff; + valaddr_reg:x6; val_offset:6632*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6632*FLEN/8, x7, x2, x4) + +inst_3342: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x840f; + valaddr_reg:x6; val_offset:6634*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6634*FLEN/8, x7, x2, x4) + +inst_3343: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x00f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x840f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6636*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6636*FLEN/8, x7, x2, x4) + +inst_3344: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x87f0; + valaddr_reg:x6; val_offset:6638*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6638*FLEN/8, x7, x2, x4) + +inst_3345: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x87f0; op2val:0xfbff; + valaddr_reg:x6; val_offset:6640*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6640*FLEN/8, x7, x2, x4) + +inst_3346: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8407; + valaddr_reg:x6; val_offset:6642*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6642*FLEN/8, x7, x2, x4) + +inst_3347: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8407; op2val:0xfbff; + valaddr_reg:x6; val_offset:6644*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6644*FLEN/8, x7, x2, x4) + +inst_3348: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x87f8; + valaddr_reg:x6; val_offset:6646*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6646*FLEN/8, x7, x2, x4) + +inst_3349: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x87f8; op2val:0xfbff; + valaddr_reg:x6; val_offset:6648*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6648*FLEN/8, x7, x2, x4) + +inst_3350: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8403; + valaddr_reg:x6; val_offset:6650*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6650*FLEN/8, x7, x2, x4) + +inst_3351: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8403; op2val:0xfbff; + valaddr_reg:x6; val_offset:6652*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6652*FLEN/8, x7, x2, x4) + +inst_3352: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x87fc; + valaddr_reg:x6; val_offset:6654*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6654*FLEN/8, x7, x2, x4) + +inst_3353: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x87fc; op2val:0xfbff; + valaddr_reg:x6; val_offset:6656*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6656*FLEN/8, x7, x2, x4) + +inst_3354: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8401; + valaddr_reg:x6; val_offset:6658*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6658*FLEN/8, x7, x2, x4) + +inst_3355: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8401; op2val:0xfbff; + valaddr_reg:x6; val_offset:6660*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6660*FLEN/8, x7, x2, x4) + +inst_3356: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x87fe; + valaddr_reg:x6; val_offset:6662*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6662*FLEN/8, x7, x2, x4) +RVTEST_SIGBASE(x2,signature_x2_28) + +inst_3357: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x87fe; op2val:0xfbff; + valaddr_reg:x6; val_offset:6664*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6664*FLEN/8, x7, x2, x4) + +inst_3358: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x1; + valaddr_reg:x6; val_offset:6666*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6666*FLEN/8, x7, x2, x4) + +inst_3359: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x3ff; + valaddr_reg:x6; val_offset:6668*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6668*FLEN/8, x7, x2, x4) + +inst_3360: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x1ff; + valaddr_reg:x6; val_offset:6670*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6670*FLEN/8, x7, x2, x4) + +inst_3361: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x380 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x380; op2val:0x0; + valaddr_reg:x6; val_offset:6672*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6672*FLEN/8, x7, x2, x4) + +inst_3362: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x7f; + valaddr_reg:x6; val_offset:6674*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 6674*FLEN/8, x7, x2, x4) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(1,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(1023,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(512,32,FLEN) +NAN_BOXED(512,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(511,32,FLEN) +NAN_BOXED(511,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(768,32,FLEN) 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+NAN_BOXED(34814,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(511,16,FLEN) +NAN_BOXED(896,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(127,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x2_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_1: + .fill 32*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x3_0: + .fill 26*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_2: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_3: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_4: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_5: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_6: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_7: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_8: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_9: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_10: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_11: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_12: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_13: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_14: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_15: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_16: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_17: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_18: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_19: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_20: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_21: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_22: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_23: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_24: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_25: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_26: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_27: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_28: + .fill 12*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fadd_b12-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fadd_b12-01.S new file mode 100644 index 000000000..8a614decd --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fadd_b12-01.S @@ -0,0 +1,644 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 05:45:15 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fadd.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fadd.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fadd_b12 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fadd_b12) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x5,test_dataset_0) +RVTEST_SIGBASE(x3,signature_x3_1) + +inst_0: +// rs1 == rs2 != rd, rs1==x17, rs2==x17, rd==x22,fs1 == 1 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x17; op2:x17; dest:x22; op1val:0xfac0; op2val:0xfac0; + valaddr_reg:x5; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x22, x17, x17, dyn, 0, 0, x5, 0*FLEN/8, x6, x3, x2) + +inst_1: +// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==x16, rs2==x29, rd==x27,fs1 == 1 and fe1 == 0x1d and fm1 == 0x2b9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x16e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x16; op2:x29; dest:x27; op1val:0xf6b9; op2val:0x796e; + valaddr_reg:x5; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x27, x16, x29, dyn, 0, 0, x5, 2*FLEN/8, x6, x3, x2) + +inst_2: +// rs1 == rs2 == rd, rs1==x24, rs2==x24, rd==x24,fs1 == 1 and fe1 == 0x1e and fm1 == 0x016 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x353 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x24; op2:x24; dest:x24; op1val:0xf816; op2val:0xf816; + valaddr_reg:x5; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x24, x24, x24, dyn, 0, 0, x5, 4*FLEN/8, x6, x3, x2) + +inst_3: +// rs2 == rd != rs1, rs1==x14, rs2==x9, rd==x9,fs1 == 1 and fe1 == 0x1e and fm1 == 0x244 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x14; op2:x9; dest:x9; op1val:0xfa44; op2val:0x7bff; + valaddr_reg:x5; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x9, x14, x9, dyn, 0, 0, x5, 6*FLEN/8, x6, x3, x2) + +inst_4: +// rs1 == rd != rs2, rs1==x1, rs2==x16, rd==x1,fs1 == 1 and fe1 == 0x1d and fm1 == 0x39f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x1; op2:x16; dest:x1; op1val:0xf79f; op2val:0x7bff; + valaddr_reg:x5; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x1, x1, x16, dyn, 0, 0, x5, 8*FLEN/8, x6, x3, x2) + +inst_5: +// rs1==x30, rs2==x4, rd==x31,fs1 == 1 and fe1 == 0x1e and fm1 == 0x342 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x4; dest:x31; op1val:0xfb42; op2val:0x7bff; + valaddr_reg:x5; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x4, dyn, 0, 0, x5, 10*FLEN/8, x6, x3, x2) + +inst_6: +// rs1==x27, rs2==x30, rd==x13,fs1 == 1 and fe1 == 0x1d and fm1 == 0x081 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x27; op2:x30; dest:x13; op1val:0xf481; op2val:0x7bff; + valaddr_reg:x5; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x13, x27, x30, dyn, 0, 0, x5, 12*FLEN/8, x6, x3, x2) + +inst_7: +// rs1==x18, rs2==x20, rd==x15,fs1 == 1 and fe1 == 0x1e and fm1 == 0x0f1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2f2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x18; op2:x20; dest:x15; op1val:0xf8f1; op2val:0x7af2; + valaddr_reg:x5; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x15, x18, x20, dyn, 0, 0, x5, 14*FLEN/8, x6, x3, x2) + +inst_8: +// rs1==x21, rs2==x22, rd==x26,fs1 == 1 and fe1 == 0x1e and fm1 == 0x346 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x21; op2:x22; dest:x26; op1val:0xfb46; op2val:0x7bff; + valaddr_reg:x5; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x26, x21, x22, dyn, 0, 0, x5, 16*FLEN/8, x6, x3, x2) + +inst_9: +// rs1==x29, rs2==x13, rd==x8,fs1 == 1 and fe1 == 0x1e and fm1 == 0x27a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x29; op2:x13; dest:x8; op1val:0xfa7a; op2val:0x7bff; + valaddr_reg:x5; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x8, x29, x13, dyn, 0, 0, x5, 18*FLEN/8, x6, x3, x2) + +inst_10: +// rs1==x26, rs2==x14, rd==x25,fs1 == 1 and fe1 == 0x1d and fm1 == 0x0f5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x26; op2:x14; dest:x25; op1val:0xf4f5; op2val:0x7bff; + valaddr_reg:x5; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x25, x26, x14, dyn, 0, 0, x5, 20*FLEN/8, x6, x3, x2) + +inst_11: +// rs1==x9, rs2==x27, rd==x12,fs1 == 1 and fe1 == 0x1e and fm1 == 0x32f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x9; op2:x27; dest:x12; op1val:0xfb2f; op2val:0x7bff; + valaddr_reg:x5; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x12, x9, x27, dyn, 0, 0, x5, 22*FLEN/8, x6, x3, x2) + +inst_12: +// rs1==x7, rs2==x26, rd==x19,fs1 == 1 and fe1 == 0x1d and fm1 == 0x38c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x094 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x7; op2:x26; dest:x19; op1val:0xf78c; op2val:0x7894; + valaddr_reg:x5; val_offset:24*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x19, x7, x26, dyn, 0, 0, x5, 24*FLEN/8, x6, x3, x2) +RVTEST_VALBASEUPD(x13,test_dataset_1) + +inst_13: +// rs1==x4, rs2==x8, rd==x17,fs1 == 1 and fe1 == 0x1d and fm1 == 0x2f1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x4; op2:x8; dest:x17; op1val:0xf6f1; op2val:0x7bff; + valaddr_reg:x13; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x17, x4, x8, dyn, 0, 0, x13, 0*FLEN/8, x15, x3, x2) + +inst_14: +// rs1==x6, rs2==x12, rd==x18,fs1 == 1 and fe1 == 0x1e and fm1 == 0x34c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x6; op2:x12; dest:x18; op1val:0xfb4c; op2val:0x7bff; + valaddr_reg:x13; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x18, x6, x12, dyn, 0, 0, x13, 2*FLEN/8, x15, x3, x2) + +inst_15: +// rs1==x19, rs2==x31, rd==x5,fs1 == 1 and fe1 == 0x1d and fm1 == 0x3a0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x19; op2:x31; dest:x5; op1val:0xf7a0; op2val:0x7bff; + valaddr_reg:x13; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x5, x19, x31, dyn, 0, 0, x13, 4*FLEN/8, x15, x3, x2) + +inst_16: +// rs1==x28, rs2==x2, rd==x7,fs1 == 1 and fe1 == 0x1d and fm1 == 0x02a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x28; op2:x2; dest:x7; op1val:0xf42a; op2val:0x7bff; + valaddr_reg:x13; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x11 +*/ +TEST_FPRR_OP(fadd.h, x7, x28, x2, dyn, 0, 0, x13, 6*FLEN/8, x15, x3, x11) +RVTEST_SIGBASE(x9,signature_x9_0) + +inst_17: +// rs1==x0, rs2==x5, rd==x30,fs1 == 1 and fe1 == 0x1e and fm1 == 0x063 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x0; op2:x5; dest:x30; op1val:0x0; op2val:0x787f; + valaddr_reg:x13; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x11 +*/ +TEST_FPRR_OP(fadd.h, x30, x0, x5, dyn, 0, 0, x13, 8*FLEN/8, x15, x9, x11) + +inst_18: +// rs1==x31, rs2==x21, rd==x20,fs1 == 1 and fe1 == 0x1e and fm1 == 0x1c1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x31; op2:x21; dest:x20; op1val:0xf9c1; op2val:0x7bff; + valaddr_reg:x13; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x11 +*/ +TEST_FPRR_OP(fadd.h, x20, x31, x21, dyn, 0, 0, x13, 10*FLEN/8, x15, x9, x11) + +inst_19: +// rs1==x8, rs2==x1, rd==x4,fs1 == 1 and fe1 == 0x1e and fm1 == 0x298 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x8; op2:x1; dest:x4; op1val:0xfa98; op2val:0x7bff; + valaddr_reg:x13; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x11 +*/ +TEST_FPRR_OP(fadd.h, x4, x8, x1, dyn, 0, 0, x13, 12*FLEN/8, x15, x9, x11) + +inst_20: +// rs1==x5, rs2==x6, rd==x0,fs1 == 1 and fe1 == 0x15 and fm1 == 0x0ad and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3e9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x5; op2:x6; dest:x0; op1val:0xd4ad; op2val:0x77e9; + valaddr_reg:x13; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x11 +*/ +TEST_FPRR_OP(fadd.h, x0, x5, x6, dyn, 0, 0, x13, 14*FLEN/8, x15, x9, x11) + +inst_21: +// rs1==x3, rs2==x19, rd==x29,fs1 == 1 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x3; op2:x19; dest:x29; op1val:0xfaef; op2val:0x7bff; + valaddr_reg:x13; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x11 +*/ +TEST_FPRR_OP(fadd.h, x29, x3, x19, dyn, 0, 0, x13, 16*FLEN/8, x15, x9, x11) + +inst_22: +// rs1==x22, rs2==x0, rd==x14,fs1 == 1 and fe1 == 0x1d and fm1 == 0x133 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x22; op2:x0; dest:x14; op1val:0xf533; op2val:0x0; + valaddr_reg:x13; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x11 +*/ +TEST_FPRR_OP(fadd.h, x14, x22, x0, dyn, 0, 0, x13, 18*FLEN/8, x15, x9, x11) + +inst_23: +// rs1==x20, rs2==x25, rd==x16,fs1 == 1 and fe1 == 0x1c and fm1 == 0x21c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x210 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x20; op2:x25; dest:x16; op1val:0xf21c; op2val:0x7a10; + valaddr_reg:x13; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x11 +*/ +TEST_FPRR_OP(fadd.h, x16, x20, x25, dyn, 0, 0, x13, 20*FLEN/8, x15, x9, x11) + +inst_24: +// rs1==x23, rs2==x10, rd==x28,fs1 == 1 and fe1 == 0x1c and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x23; op2:x10; dest:x28; op1val:0xf3a1; op2val:0x7bff; + valaddr_reg:x13; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x11 +*/ +TEST_FPRR_OP(fadd.h, x28, x23, x10, dyn, 0, 0, x13, 22*FLEN/8, x15, x9, x11) +RVTEST_VALBASEUPD(x5,test_dataset_2) + +inst_25: +// rs1==x13, rs2==x7, rd==x21,fs1 == 1 and fe1 == 0x1e and fm1 == 0x26c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x13; op2:x7; dest:x21; op1val:0xfa6c; op2val:0x7bff; + valaddr_reg:x5; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x11 +*/ +TEST_FPRR_OP(fadd.h, x21, x13, x7, dyn, 0, 0, x5, 0*FLEN/8, x8, x9, x11) + +inst_26: +// rs1==x15, rs2==x18, rd==x10,fs1 == 1 and fe1 == 0x1b and fm1 == 0x125 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x267 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x15; op2:x18; dest:x10; op1val:0xed25; op2val:0x7667; + valaddr_reg:x5; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x11 +*/ +TEST_FPRR_OP(fadd.h, x10, x15, x18, dyn, 0, 0, x5, 2*FLEN/8, x8, x9, x11) + +inst_27: +// rs1==x12, rs2==x3, rd==x2,fs1 == 1 and fe1 == 0x1e and fm1 == 0x00f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x12; op2:x3; dest:x2; op1val:0xf80f; op2val:0x7bff; + valaddr_reg:x5; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x11 +*/ +TEST_FPRR_OP(fadd.h, x2, x12, x3, dyn, 0, 0, x5, 4*FLEN/8, x8, x9, x11) + +inst_28: +// rs1==x25, rs2==x11, rd==x3,fs1 == 1 and fe1 == 0x1b and fm1 == 0x2f9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x147 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x25; op2:x11; dest:x3; op1val:0xeef9; op2val:0x7947; + valaddr_reg:x5; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x3, x25, x11, dyn, 0, 0, x5, 6*FLEN/8, x8, x9, x4) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_29: +// rs1==x10, rs2==x23, rd==x6,fs1 == 1 and fe1 == 0x1e and fm1 == 0x1a6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x10; op2:x23; dest:x6; op1val:0xf9a6; op2val:0x7bff; + valaddr_reg:x5; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x6, x10, x23, dyn, 0, 0, x5, 8*FLEN/8, x8, x1, x4) + +inst_30: +// rs1==x2, rs2==x28, rd==x11,fs1 == 1 and fe1 == 0x1e and fm1 == 0x283 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x2; op2:x28; dest:x11; op1val:0xfa83; op2val:0x7bff; + valaddr_reg:x5; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x11, x2, x28, dyn, 0, 0, x5, 10*FLEN/8, x8, x1, x4) + +inst_31: +// rs1==x11, rs2==x15, rd==x23,fs1 == 1 and fe1 == 0x1e and fm1 == 0x3b4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x11; op2:x15; dest:x23; op1val:0xfbb4; op2val:0x7bff; + valaddr_reg:x5; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x23, x11, x15, dyn, 0, 0, x5, 12*FLEN/8, x8, x1, x4) + +inst_32: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x0b2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf8b2; op2val:0x7bff; + valaddr_reg:x5; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x5, 14*FLEN/8, x8, x1, x4) + +inst_33: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x0c4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3d8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf8c4; op2val:0x7bd8; + valaddr_reg:x5; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x5, 16*FLEN/8, x8, x1, x4) + +inst_34: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x09a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ec and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf89a; op2val:0x7aec; + valaddr_reg:x5; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x5, 18*FLEN/8, x8, x1, x4) + +inst_35: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x20e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x203 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf20e; op2val:0x7603; + valaddr_reg:x5; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x5, 20*FLEN/8, x8, x1, x4) + +inst_36: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x0e6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf8e6; op2val:0x7bff; + valaddr_reg:x5; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x5, 22*FLEN/8, x8, x1, x4) + +inst_37: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x39e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x087 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf79e; op2val:0x7887; + valaddr_reg:x5; val_offset:24*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x5, 24*FLEN/8, x8, x1, x4) + +inst_38: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x20e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa0e; op2val:0x7bff; + valaddr_reg:x5; val_offset:26*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x5, 26*FLEN/8, x8, x1, x4) + +inst_39: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x362 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb62; op2val:0x7bff; + valaddr_reg:x5; val_offset:28*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x5, 28*FLEN/8, x8, x1, x4) + +inst_40: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x32e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb2e; op2val:0x7bff; + valaddr_reg:x5; val_offset:30*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x5, 30*FLEN/8, x8, x1, x4) + +inst_41: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x052 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x373 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf852; op2val:0x7b73; + valaddr_reg:x5; val_offset:32*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x5, 32*FLEN/8, x8, x1, x4) + +inst_42: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x1a3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3d7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf9a3; op2val:0x7bd7; + valaddr_reg:x5; val_offset:34*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x5, 34*FLEN/8, x8, x1, x4) + +inst_43: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x27d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa7d; op2val:0x7bff; + valaddr_reg:x5; val_offset:36*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x5, 36*FLEN/8, x8, x1, x4) + +inst_44: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x328 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb28; op2val:0x7bff; + valaddr_reg:x5; val_offset:38*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x5, 38*FLEN/8, x8, x1, x4) + +inst_45: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x398 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb98; op2val:0x7bff; + valaddr_reg:x5; val_offset:40*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x5, 40*FLEN/8, x8, x1, x4) + +inst_46: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x334 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf734; op2val:0x7bff; + valaddr_reg:x5; val_offset:42*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x5, 42*FLEN/8, x8, x1, x4) + +inst_47: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3f7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbf7; op2val:0x7bff; + valaddr_reg:x5; val_offset:44*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x5, 44*FLEN/8, x8, x1, x4) + +inst_48: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x257 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa57; op2val:0x7b00; + valaddr_reg:x5; val_offset:46*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x5, 46*FLEN/8, x8, x1, x4) + +inst_49: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xfac0; op2val:0x7bff; + valaddr_reg:x5; val_offset:48*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x5, 48*FLEN/8, x8, x1, x4) + +inst_50: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x016 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x353 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf816; op2val:0x7b53; + valaddr_reg:x5; val_offset:50*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x5, 50*FLEN/8, x8, x1, x4) + +inst_51: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x063 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf863; op2val:0x787f; + valaddr_reg:x5; val_offset:52*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x5, 52*FLEN/8, x8, x1, x4) + +inst_52: +// fs1 == 1 and fe1 == 0x15 and fm1 == 0x0ad and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3e9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xd4ad; op2val:0x77e9; + valaddr_reg:x5; val_offset:54*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x5, 54*FLEN/8, x8, x1, x4) + +inst_53: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x133 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xf533; op2val:0x7bff; + valaddr_reg:x5; val_offset:56*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x5, 56*FLEN/8, x8, x1, x4) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(64192,16,FLEN) +NAN_BOXED(64192,32,FLEN) +NAN_BOXED(63161,16,FLEN) +NAN_BOXED(31086,32,FLEN) +NAN_BOXED(63510,16,FLEN) +NAN_BOXED(63510,32,FLEN) +NAN_BOXED(64068,16,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(63391,16,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(64322,16,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(62593,16,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(63729,16,FLEN) +NAN_BOXED(31474,32,FLEN) +NAN_BOXED(64326,16,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(64122,16,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(62709,16,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(64303,16,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(63372,16,FLEN) +NAN_BOXED(30868,32,FLEN) +test_dataset_1: +NAN_BOXED(63217,16,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(64332,16,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(63392,16,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(62506,16,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(30847,32,FLEN) +NAN_BOXED(63937,16,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(64152,16,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(54445,16,FLEN) +NAN_BOXED(30697,32,FLEN) +NAN_BOXED(64239,16,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(62771,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(61980,16,FLEN) +NAN_BOXED(31248,32,FLEN) +NAN_BOXED(62369,16,FLEN) +NAN_BOXED(31743,32,FLEN) +test_dataset_2: +NAN_BOXED(64108,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(60709,16,FLEN) +NAN_BOXED(30311,16,FLEN) +NAN_BOXED(63503,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(61177,16,FLEN) +NAN_BOXED(31047,16,FLEN) +NAN_BOXED(63910,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(64131,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(64436,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(63666,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(63684,16,FLEN) +NAN_BOXED(31704,16,FLEN) +NAN_BOXED(63642,16,FLEN) +NAN_BOXED(31468,16,FLEN) +NAN_BOXED(61966,16,FLEN) +NAN_BOXED(30211,16,FLEN) +NAN_BOXED(63718,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(63390,16,FLEN) +NAN_BOXED(30855,16,FLEN) +NAN_BOXED(64014,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(64354,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(64302,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(63570,16,FLEN) +NAN_BOXED(31603,16,FLEN) +NAN_BOXED(63907,16,FLEN) +NAN_BOXED(31703,16,FLEN) +NAN_BOXED(64125,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(64296,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(64408,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(63284,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(64503,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(64087,16,FLEN) +NAN_BOXED(31488,16,FLEN) +NAN_BOXED(64192,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(63510,16,FLEN) +NAN_BOXED(31571,16,FLEN) +NAN_BOXED(63587,16,FLEN) +NAN_BOXED(30847,16,FLEN) +NAN_BOXED(54445,16,FLEN) +NAN_BOXED(30697,16,FLEN) +NAN_BOXED(62771,16,FLEN) +NAN_BOXED(31743,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x3_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x3_1: + .fill 34*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x9_0: + .fill 24*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_0: + .fill 50*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fadd_b13-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fadd_b13-01.S new file mode 100644 index 000000000..832ad9b21 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fadd_b13-01.S @@ -0,0 +1,2079 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 05:45:15 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fadd.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fadd.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fadd_b13 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fadd_b13) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x15,signature_x15_1) + +inst_0: +// rs1 == rs2 != rd, rs1==x18, rs2==x18, rd==x14,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x18; op2:x18; dest:x14; op1val:0x7ac0; op2val:0x7ac0; + valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x17 +*/ +TEST_FPRR_OP(fadd.h, x14, x18, x18, dyn, 0, 0, x3, 0*FLEN/8, x9, x15, x17) + +inst_1: +// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==x27, rs2==x14, rd==x16,fs1 == 0 and fe1 == 0x1d and fm1 == 0x2b9 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2b9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x27; op2:x14; dest:x16; op1val:0x76b9; op2val:0xf6b9; + valaddr_reg:x3; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x17 +*/ +TEST_FPRR_OP(fadd.h, x16, x27, x14, dyn, 0, 0, x3, 2*FLEN/8, x9, x15, x17) + +inst_2: +// rs1 == rs2 == rd, rs1==x4, rs2==x4, rd==x4,fs1 == 0 and fe1 == 0x1e and fm1 == 0x016 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x016 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x4; op2:x4; dest:x4; op1val:0x7816; op2val:0x7816; + valaddr_reg:x3; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x17 +*/ +TEST_FPRR_OP(fadd.h, x4, x4, x4, dyn, 0, 0, x3, 4*FLEN/8, x9, x15, x17) + +inst_3: +// rs2 == rd != rs1, rs1==x20, rs2==x22, rd==x22,fs1 == 0 and fe1 == 0x1e and fm1 == 0x244 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x244 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x20; op2:x22; dest:x22; op1val:0x7a44; op2val:0xfa44; + valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x17 +*/ +TEST_FPRR_OP(fadd.h, x22, x20, x22, dyn, 0, 0, x3, 6*FLEN/8, x9, x15, x17) + +inst_4: +// rs1 == rd != rs2, rs1==x19, rs2==x10, rd==x19,fs1 == 0 and fe1 == 0x1d and fm1 == 0x39f and fs2 == 1 and fe2 == 0x1d and fm2 == 0x39f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x19; op2:x10; dest:x19; op1val:0x779f; op2val:0xf79f; + valaddr_reg:x3; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x17 +*/ +TEST_FPRR_OP(fadd.h, x19, x19, x10, dyn, 0, 0, x3, 8*FLEN/8, x9, x15, x17) + +inst_5: +// rs1==x29, rs2==x21, rd==x28,fs1 == 0 and fe1 == 0x1e and fm1 == 0x342 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x342 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x29; op2:x21; dest:x28; op1val:0x7b42; op2val:0xfb42; + valaddr_reg:x3; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x17 +*/ +TEST_FPRR_OP(fadd.h, x28, x29, x21, dyn, 0, 0, x3, 10*FLEN/8, x9, x15, x17) + +inst_6: +// rs1==x6, rs2==x28, rd==x21,fs1 == 0 and fe1 == 0x1d and fm1 == 0x081 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x081 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x6; op2:x28; dest:x21; op1val:0x7481; op2val:0xf481; + valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x17 +*/ +TEST_FPRR_OP(fadd.h, x21, x6, x28, dyn, 0, 0, x3, 12*FLEN/8, x9, x15, x17) + +inst_7: +// rs1==x31, rs2==x6, rd==x7,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0f1 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0f1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x31; op2:x6; dest:x7; op1val:0x78f1; op2val:0xf8f1; + valaddr_reg:x3; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x17 +*/ +TEST_FPRR_OP(fadd.h, x7, x31, x6, dyn, 0, 0, x3, 14*FLEN/8, x9, x15, x17) + +inst_8: +// rs1==x1, rs2==x13, rd==x8,fs1 == 0 and fe1 == 0x1e and fm1 == 0x346 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x346 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x1; op2:x13; dest:x8; op1val:0x7b46; op2val:0xfb46; + valaddr_reg:x3; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x17 +*/ +TEST_FPRR_OP(fadd.h, x8, x1, x13, dyn, 0, 0, x3, 16*FLEN/8, x9, x15, x17) + +inst_9: +// rs1==x14, rs2==x25, rd==x12,fs1 == 0 and fe1 == 0x1e and fm1 == 0x27a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x27a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x14; op2:x25; dest:x12; op1val:0x7a7a; op2val:0xfa7a; + valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x17 +*/ +TEST_FPRR_OP(fadd.h, x12, x14, x25, dyn, 0, 0, x3, 18*FLEN/8, x9, x15, x17) + +inst_10: +// rs1==x12, rs2==x2, rd==x11,fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f5 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x0f5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x12; op2:x2; dest:x11; op1val:0x74f5; op2val:0xf4f5; + valaddr_reg:x3; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x17 +*/ +TEST_FPRR_OP(fadd.h, x11, x12, x2, dyn, 0, 0, x3, 20*FLEN/8, x9, x15, x17) + +inst_11: +// rs1==x21, rs2==x27, rd==x2,fs1 == 0 and fe1 == 0x1e and fm1 == 0x32f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x32f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x21; op2:x27; dest:x2; op1val:0x7b2f; op2val:0xfb2f; + valaddr_reg:x3; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x17 +*/ +TEST_FPRR_OP(fadd.h, x2, x21, x27, dyn, 0, 0, x3, 22*FLEN/8, x9, x15, x17) + +inst_12: +// rs1==x11, rs2==x5, rd==x24,fs1 == 0 and fe1 == 0x1d and fm1 == 0x38c and fs2 == 1 and fe2 == 0x1d and fm2 == 0x38c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x11; op2:x5; dest:x24; op1val:0x778c; op2val:0xf78c; + valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x17 +*/ +TEST_FPRR_OP(fadd.h, x24, x11, x5, dyn, 0, 0, x3, 24*FLEN/8, x9, x15, x17) +RVTEST_VALBASEUPD(x14,test_dataset_1) + +inst_13: +// rs1==x3, rs2==x9, rd==x23,fs1 == 0 and fe1 == 0x1d and fm1 == 0x2f1 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2f1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x3; op2:x9; dest:x23; op1val:0x76f1; op2val:0xf6f1; + valaddr_reg:x14; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x17 +*/ +TEST_FPRR_OP(fadd.h, x23, x3, x9, dyn, 0, 0, x14, 0*FLEN/8, x16, x15, x17) +RVTEST_SIGBASE(x4,signature_x4_0) + +inst_14: +// rs1==x22, rs2==x3, rd==x9,fs1 == 0 and fe1 == 0x1e and fm1 == 0x34c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x34c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x22; op2:x3; dest:x9; op1val:0x7b4c; op2val:0xfb4c; + valaddr_reg:x14; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP(fadd.h, x9, x22, x3, dyn, 0, 0, x14, 2*FLEN/8, x16, x4, x13) + +inst_15: +// rs1==x24, rs2==x12, rd==x27,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a0 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3a0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x24; op2:x12; dest:x27; op1val:0x77a0; op2val:0xf7a0; + valaddr_reg:x14; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP(fadd.h, x27, x24, x12, dyn, 0, 0, x14, 4*FLEN/8, x16, x4, x13) + +inst_16: +// rs1==x2, rs2==x11, rd==x15,fs1 == 0 and fe1 == 0x1d and fm1 == 0x02a and fs2 == 1 and fe2 == 0x1d and fm2 == 0x02a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x2; op2:x11; dest:x15; op1val:0x742a; op2val:0xf42a; + valaddr_reg:x14; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP(fadd.h, x15, x2, x11, dyn, 0, 0, x14, 6*FLEN/8, x16, x4, x13) + +inst_17: +// rs1==x10, rs2==x24, rd==x17,fs1 == 0 and fe1 == 0x1e and fm1 == 0x063 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x063 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x10; op2:x24; dest:x17; op1val:0x7863; op2val:0xf863; + valaddr_reg:x14; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP(fadd.h, x17, x10, x24, dyn, 0, 0, x14, 8*FLEN/8, x16, x4, x13) + +inst_18: +// rs1==x5, rs2==x8, rd==x31,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c1 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1c1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x5; op2:x8; dest:x31; op1val:0x79c1; op2val:0xf9c1; + valaddr_reg:x14; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP(fadd.h, x31, x5, x8, dyn, 0, 0, x14, 10*FLEN/8, x16, x4, x13) + +inst_19: +// rs1==x28, rs2==x31, rd==x18,fs1 == 0 and fe1 == 0x1e and fm1 == 0x298 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x298 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x28; op2:x31; dest:x18; op1val:0x7a98; op2val:0xfa98; + valaddr_reg:x14; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP(fadd.h, x18, x28, x31, dyn, 0, 0, x14, 12*FLEN/8, x16, x4, x13) + +inst_20: +// rs1==x8, rs2==x17, rd==x30,fs1 == 0 and fe1 == 0x15 and fm1 == 0x0ad and fs2 == 1 and fe2 == 0x15 and fm2 == 0x0ad and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x8; op2:x17; dest:x30; op1val:0x54ad; op2val:0xd4ad; + valaddr_reg:x14; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP(fadd.h, x30, x8, x17, dyn, 0, 0, x14, 14*FLEN/8, x16, x4, x13) + +inst_21: +// rs1==x9, rs2==x23, rd==x1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2ef and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x9; op2:x23; dest:x1; op1val:0x7aef; op2val:0xfaef; + valaddr_reg:x14; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP(fadd.h, x1, x9, x23, dyn, 0, 0, x14, 16*FLEN/8, x16, x4, x13) + +inst_22: +// rs1==x23, rs2==x19, rd==x25,fs1 == 0 and fe1 == 0x1d and fm1 == 0x133 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x133 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x23; op2:x19; dest:x25; op1val:0x7533; op2val:0xf533; + valaddr_reg:x14; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP(fadd.h, x25, x23, x19, dyn, 0, 0, x14, 18*FLEN/8, x16, x4, x13) + +inst_23: +// rs1==x30, rs2==x20, rd==x5,fs1 == 0 and fe1 == 0x1c and fm1 == 0x21c and fs2 == 1 and fe2 == 0x1c and fm2 == 0x21c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x20; dest:x5; op1val:0x721c; op2val:0xf21c; + valaddr_reg:x14; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP(fadd.h, x5, x30, x20, dyn, 0, 0, x14, 20*FLEN/8, x16, x4, x13) + +inst_24: +// rs1==x25, rs2==x15, rd==x20,fs1 == 0 and fe1 == 0x1c and fm1 == 0x3a1 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3a1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x25; op2:x15; dest:x20; op1val:0x73a1; op2val:0xf3a1; + valaddr_reg:x14; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP(fadd.h, x20, x25, x15, dyn, 0, 0, x14, 22*FLEN/8, x16, x4, x13) + +inst_25: +// rs1==x7, rs2==x29, rd==x6,fs1 == 0 and fe1 == 0x1e and fm1 == 0x26c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x26c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x7; op2:x29; dest:x6; op1val:0x7a6c; op2val:0xfa6c; + valaddr_reg:x14; val_offset:24*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP(fadd.h, x6, x7, x29, dyn, 0, 0, x14, 24*FLEN/8, x16, x4, x13) +RVTEST_VALBASEUPD(x6,test_dataset_2) + +inst_26: +// rs1==x26, rs2==x0, rd==x13,fs1 == 0 and fe1 == 0x1b and fm1 == 0x125 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x125 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x26; op2:x0; dest:x13; op1val:0x6d25; op2val:0x0; + valaddr_reg:x6; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x13, x26, x0, dyn, 0, 0, x6, 0*FLEN/8, x8, x4, x5) +RVTEST_SIGBASE(x2,signature_x2_0) + +inst_27: +// rs1==x15, rs2==x7, rd==x3,fs1 == 0 and fe1 == 0x1e and fm1 == 0x00f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x15; op2:x7; dest:x3; op1val:0x780f; op2val:0xf80f; + valaddr_reg:x6; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x3, x15, x7, dyn, 0, 0, x6, 2*FLEN/8, x8, x2, x5) + +inst_28: +// rs1==x16, rs2==x26, rd==x0,fs1 == 0 and fe1 == 0x1b and fm1 == 0x2f9 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x2f9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x16; op2:x26; dest:x0; op1val:0x6ef9; op2val:0xeef9; + valaddr_reg:x6; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x0, x16, x26, dyn, 0, 0, x6, 4*FLEN/8, x8, x2, x5) + +inst_29: +// rs1==x0, rs2==x16, rd==x29,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a6 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1a6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x0; op2:x16; dest:x29; op1val:0x0; op2val:0xf9a6; + valaddr_reg:x6; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x29, x0, x16, dyn, 0, 0, x6, 6*FLEN/8, x8, x2, x5) + +inst_30: +// rs1==x13, rs2==x1, rd==x26,fs1 == 0 and fe1 == 0x1e and fm1 == 0x283 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x283 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x13; op2:x1; dest:x26; op1val:0x7a83; op2val:0xfa83; + valaddr_reg:x6; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x26, x13, x1, dyn, 0, 0, x6, 8*FLEN/8, x8, x2, x5) + +inst_31: +// rs1==x17, rs2==x30, rd==x10,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3b4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x17; op2:x30; dest:x10; op1val:0x7bb4; op2val:0xfbb4; + valaddr_reg:x6; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x10, x17, x30, dyn, 0, 0, x6, 10*FLEN/8, x8, x2, x5) + +inst_32: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b2 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0b2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78b2; op2val:0xf8b2; + valaddr_reg:x6; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 12*FLEN/8, x8, x2, x5) + +inst_33: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0c4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78c4; op2val:0xf8c4; + valaddr_reg:x6; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 14*FLEN/8, x8, x2, x5) + +inst_34: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x09a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x789a; op2val:0xf89a; + valaddr_reg:x6; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 16*FLEN/8, x8, x2, x5) + +inst_35: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x20e and fs2 == 1 and fe2 == 0x1c and fm2 == 0x20e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x720e; op2val:0xf20e; + valaddr_reg:x6; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 18*FLEN/8, x8, x2, x5) + +inst_36: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e6 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0e6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78e6; op2val:0xf8e6; + valaddr_reg:x6; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 20*FLEN/8, x8, x2, x5) + +inst_37: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x39e and fs2 == 1 and fe2 == 0x1d and fm2 == 0x39e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x779e; op2val:0xf79e; + valaddr_reg:x6; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 22*FLEN/8, x8, x2, x5) + +inst_38: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x20e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a0e; op2val:0xfa0e; + valaddr_reg:x6; val_offset:24*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 24*FLEN/8, x8, x2, x5) + +inst_39: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x362 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x362 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b62; op2val:0xfb62; + valaddr_reg:x6; val_offset:26*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 26*FLEN/8, x8, x2, x5) + +inst_40: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x32e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b2e; op2val:0xfb2e; + valaddr_reg:x6; val_offset:28*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 28*FLEN/8, x8, x2, x5) + +inst_41: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x052 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x052 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7852; op2val:0xf852; + valaddr_reg:x6; val_offset:30*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 30*FLEN/8, x8, x2, x5) + +inst_42: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1a3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79a3; op2val:0xf9a3; + valaddr_reg:x6; val_offset:32*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 32*FLEN/8, x8, x2, x5) + +inst_43: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x27d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x27d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a7d; op2val:0xfa7d; + valaddr_reg:x6; val_offset:34*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 34*FLEN/8, x8, x2, x5) + +inst_44: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x328 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x328 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b28; op2val:0xfb28; + valaddr_reg:x6; val_offset:36*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 36*FLEN/8, x8, x2, x5) + +inst_45: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x398 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x398 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b98; op2val:0xfb98; + valaddr_reg:x6; val_offset:38*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 38*FLEN/8, x8, x2, x5) + +inst_46: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x334 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x334 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7734; op2val:0xf734; + valaddr_reg:x6; val_offset:40*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 40*FLEN/8, x8, x2, x5) + +inst_47: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f7 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3f7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bf7; op2val:0xfbf7; + valaddr_reg:x6; val_offset:42*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 42*FLEN/8, x8, x2, x5) + +inst_48: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x257 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x257 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a57; op2val:0xfa57; + valaddr_reg:x6; val_offset:44*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 44*FLEN/8, x8, x2, x5) + +inst_49: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x109 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x109 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7909; op2val:0xf909; + valaddr_reg:x6; val_offset:46*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 46*FLEN/8, x8, x2, x5) + +inst_50: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3c5 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3c5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x73c5; op2val:0xf3c5; + valaddr_reg:x6; val_offset:48*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 48*FLEN/8, x8, x2, x5) + +inst_51: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x37e and fs2 == 1 and fe2 == 0x1b and fm2 == 0x37e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f7e; op2val:0xef7e; + valaddr_reg:x6; val_offset:50*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 50*FLEN/8, x8, x2, x5) + +inst_52: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x25a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a5a; op2val:0xfa5a; + valaddr_reg:x6; val_offset:52*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 52*FLEN/8, x8, x2, x5) + +inst_53: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x286 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x286 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a86; op2val:0xfa86; + valaddr_reg:x6; val_offset:54*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 54*FLEN/8, x8, x2, x5) + +inst_54: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0ae and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0ae and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x70ae; op2val:0xf0ae; + valaddr_reg:x6; val_offset:56*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 56*FLEN/8, x8, x2, x5) + +inst_55: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x1c9 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x1c9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x69c9; op2val:0xe9c9; + valaddr_reg:x6; val_offset:58*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 58*FLEN/8, x8, x2, x5) + +inst_56: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x171 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x171 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7971; op2val:0xf971; + valaddr_reg:x6; val_offset:60*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 60*FLEN/8, x8, x2, x5) + +inst_57: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0xf913; + valaddr_reg:x6; val_offset:62*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 62*FLEN/8, x8, x2, x5) + +inst_58: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1eb and fs2 == 1 and fe2 == 0x1d and fm2 == 0x1eb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x75eb; op2val:0xf5eb; + valaddr_reg:x6; val_offset:64*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 64*FLEN/8, x8, x2, x5) + +inst_59: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x0a7 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x0a7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x68a7; op2val:0xe8a7; + valaddr_reg:x6; val_offset:66*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 66*FLEN/8, x8, x2, x5) + +inst_60: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3af and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3af and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7baf; op2val:0xfbaf; + valaddr_reg:x6; val_offset:68*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 68*FLEN/8, x8, x2, x5) + +inst_61: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3ec and fs2 == 1 and fe2 == 0x1b and fm2 == 0x3ec and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6fec; op2val:0xefec; + valaddr_reg:x6; val_offset:70*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 70*FLEN/8, x8, x2, x5) + +inst_62: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x267 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x267 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a67; op2val:0xfa67; + valaddr_reg:x6; val_offset:72*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 72*FLEN/8, x8, x2, x5) + +inst_63: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x1d4 and fs2 == 1 and fe2 == 0x19 and fm2 == 0x1d4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x65d4; op2val:0xe5d4; + valaddr_reg:x6; val_offset:74*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 74*FLEN/8, x8, x2, x5) + +inst_64: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x27e and fs2 == 1 and fe2 == 0x1b and fm2 == 0x27e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e7e; op2val:0xee7e; + valaddr_reg:x6; val_offset:76*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 76*FLEN/8, x8, x2, x5) + +inst_65: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x310 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x310 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7310; op2val:0xf310; + valaddr_reg:x6; val_offset:78*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 78*FLEN/8, x8, x2, x5) + +inst_66: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x19a and fs2 == 1 and fe2 == 0x1d and fm2 == 0x19a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x759a; op2val:0xf59a; + valaddr_reg:x6; val_offset:80*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 80*FLEN/8, x8, x2, x5) + +inst_67: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x006 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x006 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7806; op2val:0xf806; + valaddr_reg:x6; val_offset:82*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 82*FLEN/8, x8, x2, x5) + +inst_68: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x274 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x274 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e74; op2val:0xee74; + valaddr_reg:x6; val_offset:84*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 84*FLEN/8, x8, x2, x5) + +inst_69: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x260 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x260 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7260; op2val:0xf260; + valaddr_reg:x6; val_offset:86*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 86*FLEN/8, x8, x2, x5) + +inst_70: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1d9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79d9; op2val:0xf9d9; + valaddr_reg:x6; val_offset:88*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 88*FLEN/8, x8, x2, x5) + +inst_71: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x358 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x358 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b58; op2val:0xfb58; + valaddr_reg:x6; val_offset:90*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 90*FLEN/8, x8, x2, x5) + +inst_72: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x160 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x160 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7960; op2val:0xf960; + valaddr_reg:x6; val_offset:92*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 92*FLEN/8, x8, x2, x5) + +inst_73: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x36d and fs2 == 1 and fe2 == 0x1a and fm2 == 0x36d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6b6d; op2val:0xeb6d; + valaddr_reg:x6; val_offset:94*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 94*FLEN/8, x8, x2, x5) + +inst_74: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c2 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2c2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ac2; op2val:0xfac2; + valaddr_reg:x6; val_offset:96*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 96*FLEN/8, x8, x2, x5) + +inst_75: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7402; op2val:0xf402; + valaddr_reg:x6; val_offset:98*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 98*FLEN/8, x8, x2, x5) + +inst_76: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x312 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x312 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7712; op2val:0xf712; + valaddr_reg:x6; val_offset:100*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 100*FLEN/8, x8, x2, x5) + +inst_77: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x38a and fs2 == 1 and fe2 == 0x1d and fm2 == 0x38a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x778a; op2val:0xf78a; + valaddr_reg:x6; val_offset:102*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 102*FLEN/8, x8, x2, x5) + +inst_78: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x08c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x08c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x788c; op2val:0xf88c; + valaddr_reg:x6; val_offset:104*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 104*FLEN/8, x8, x2, x5) + +inst_79: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x1d and fm2 == 0x0fb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x74fb; op2val:0xf4fb; + valaddr_reg:x6; val_offset:106*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 106*FLEN/8, x8, x2, x5) + +inst_80: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b2 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2b2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab2; op2val:0xfab2; + valaddr_reg:x6; val_offset:108*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 108*FLEN/8, x8, x2, x5) + +inst_81: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x07b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x07b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x787b; op2val:0xf87b; + valaddr_reg:x6; val_offset:110*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 110*FLEN/8, x8, x2, x5) + +inst_82: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ee and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1ee and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79ee; op2val:0xf9ee; + valaddr_reg:x6; val_offset:112*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 112*FLEN/8, x8, x2, x5) + +inst_83: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x1d8 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x1d8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x69d8; op2val:0xe9d8; + valaddr_reg:x6; val_offset:114*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 114*FLEN/8, x8, x2, x5) + +inst_84: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3ae and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3ae and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x73ae; op2val:0xf3ae; + valaddr_reg:x6; val_offset:116*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 116*FLEN/8, x8, x2, x5) + +inst_85: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a2 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x1a2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x75a2; op2val:0xf5a2; + valaddr_reg:x6; val_offset:118*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 118*FLEN/8, x8, x2, x5) + +inst_86: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1be and fs2 == 1 and fe2 == 0x1d and fm2 == 0x1be and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x75be; op2val:0xf5be; + valaddr_reg:x6; val_offset:120*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 120*FLEN/8, x8, x2, x5) + +inst_87: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x111 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x111 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7911; op2val:0xf911; + valaddr_reg:x6; val_offset:122*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 122*FLEN/8, x8, x2, x5) + +inst_88: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b8 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1b8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b8; op2val:0xf9b8; + valaddr_reg:x6; val_offset:124*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 124*FLEN/8, x8, x2, x5) + +inst_89: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a0 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2a0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x76a0; op2val:0xf6a0; + valaddr_reg:x6; val_offset:126*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 126*FLEN/8, x8, x2, x5) + +inst_90: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x23d and fs2 == 1 and fe2 == 0x15 and fm2 == 0x23d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x563d; op2val:0xd63d; + valaddr_reg:x6; val_offset:128*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 128*FLEN/8, x8, x2, x5) + +inst_91: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x159 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x159 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7559; op2val:0xf559; + valaddr_reg:x6; val_offset:130*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 130*FLEN/8, x8, x2, x5) + +inst_92: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x118 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x118 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7918; op2val:0xf918; + valaddr_reg:x6; val_offset:132*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 132*FLEN/8, x8, x2, x5) + +inst_93: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aff; op2val:0xfaff; + valaddr_reg:x6; val_offset:134*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 134*FLEN/8, x8, x2, x5) + +inst_94: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x19c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x799c; op2val:0xf99c; + valaddr_reg:x6; val_offset:136*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 136*FLEN/8, x8, x2, x5) + +inst_95: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x14b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x14b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x794b; op2val:0xf94b; + valaddr_reg:x6; val_offset:138*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 138*FLEN/8, x8, x2, x5) + +inst_96: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31f and fs2 == 1 and fe2 == 0x1d and fm2 == 0x31f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x771f; op2val:0xf71f; + valaddr_reg:x6; val_offset:140*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 140*FLEN/8, x8, x2, x5) + +inst_97: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x10b and fs2 == 1 and fe2 == 0x1c and fm2 == 0x10b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x710b; op2val:0xf10b; + valaddr_reg:x6; val_offset:142*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 142*FLEN/8, x8, x2, x5) + +inst_98: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ca and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3ca and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77ca; op2val:0xf7ca; + valaddr_reg:x6; val_offset:144*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 144*FLEN/8, x8, x2, x5) + +inst_99: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x20a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a0a; op2val:0xfa0a; + valaddr_reg:x6; val_offset:146*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 146*FLEN/8, x8, x2, x5) + +inst_100: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3e8 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3e8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77e8; op2val:0xf7e8; + valaddr_reg:x6; val_offset:148*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 148*FLEN/8, x8, x2, x5) + +inst_101: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x377 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x377 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7777; op2val:0xf777; + valaddr_reg:x6; val_offset:150*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 150*FLEN/8, x8, x2, x5) + +inst_102: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x203 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x203 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7203; op2val:0xf203; + valaddr_reg:x6; val_offset:152*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 152*FLEN/8, x8, x2, x5) + +inst_103: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x10f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x10f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x790f; op2val:0xf90f; + valaddr_reg:x6; val_offset:154*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 154*FLEN/8, x8, x2, x5) + +inst_104: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1cd and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1cd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79cd; op2val:0xf9cd; + valaddr_reg:x6; val_offset:156*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 156*FLEN/8, x8, x2, x5) + +inst_105: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26d and fs2 == 1 and fe2 == 0x1d and fm2 == 0x26d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x766d; op2val:0xf66d; + valaddr_reg:x6; val_offset:158*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 158*FLEN/8, x8, x2, x5) + +inst_106: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x10e and fs2 == 1 and fe2 == 0x1d and fm2 == 0x10e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x750e; op2val:0xf50e; + valaddr_reg:x6; val_offset:160*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 160*FLEN/8, x8, x2, x5) + +inst_107: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1bc and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1bc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79bc; op2val:0xf9bc; + valaddr_reg:x6; val_offset:162*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 162*FLEN/8, x8, x2, x5) + +inst_108: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x294 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x294 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a94; op2val:0xfa94; + valaddr_reg:x6; val_offset:164*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 164*FLEN/8, x8, x2, x5) + +inst_109: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x241 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x241 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e41; op2val:0xee41; + valaddr_reg:x6; val_offset:166*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 166*FLEN/8, x8, x2, x5) + +inst_110: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x131 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x131 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7931; op2val:0xf931; + valaddr_reg:x6; val_offset:168*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 168*FLEN/8, x8, x2, x5) + +inst_111: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x07a and fs2 == 1 and fe2 == 0x1d and fm2 == 0x07a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x747a; op2val:0xf47a; + valaddr_reg:x6; val_offset:170*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 170*FLEN/8, x8, x2, x5) + +inst_112: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x268 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x268 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e68; op2val:0xee68; + valaddr_reg:x6; val_offset:172*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 172*FLEN/8, x8, x2, x5) + +inst_113: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x258 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x258 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7658; op2val:0xf658; + valaddr_reg:x6; val_offset:174*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 174*FLEN/8, x8, x2, x5) + +inst_114: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x064 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x064 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7464; op2val:0xf464; + valaddr_reg:x6; val_offset:176*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 176*FLEN/8, x8, x2, x5) + +inst_115: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a55; op2val:0xfa55; + valaddr_reg:x6; val_offset:178*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 178*FLEN/8, x8, x2, x5) + +inst_116: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x044 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x044 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7044; op2val:0xf044; + valaddr_reg:x6; val_offset:180*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 180*FLEN/8, x8, x2, x5) + +inst_117: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x134 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x134 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7934; op2val:0xf934; + valaddr_reg:x6; val_offset:182*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 182*FLEN/8, x8, x2, x5) + +inst_118: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f8 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7af8; op2val:0xfaf8; + valaddr_reg:x6; val_offset:184*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 184*FLEN/8, x8, x2, x5) + +inst_119: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x0c0 and fs2 == 1 and fe2 == 0x19 and fm2 == 0x0c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x64c0; op2val:0xe4c0; + valaddr_reg:x6; val_offset:186*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 186*FLEN/8, x8, x2, x5) + +inst_120: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x172 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x172 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7972; op2val:0xf972; + valaddr_reg:x6; val_offset:188*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 188*FLEN/8, x8, x2, x5) + +inst_121: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x391 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x391 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b91; op2val:0xfb91; + valaddr_reg:x6; val_offset:190*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 190*FLEN/8, x8, x2, x5) + +inst_122: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1fd and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1fd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79fd; op2val:0xf9fd; + valaddr_reg:x6; val_offset:192*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 192*FLEN/8, x8, x2, x5) + +inst_123: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x13d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x13d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x793d; op2val:0xf93d; + valaddr_reg:x6; val_offset:194*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 194*FLEN/8, x8, x2, x5) + +inst_124: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x337 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x337 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b37; op2val:0xfb37; + valaddr_reg:x6; val_offset:196*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 196*FLEN/8, x8, x2, x5) + +inst_125: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1f4 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x1f4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x75f4; op2val:0xf5f4; + valaddr_reg:x6; val_offset:198*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 198*FLEN/8, x8, x2, x5) + +inst_126: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2a5 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x2a5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x72a5; op2val:0xf2a5; + valaddr_reg:x6; val_offset:200*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 200*FLEN/8, x8, x2, x5) + +inst_127: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x08d and fs2 == 1 and fe2 == 0x18 and fm2 == 0x08d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x608d; op2val:0xe08d; + valaddr_reg:x6; val_offset:202*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 202*FLEN/8, x8, x2, x5) + +inst_128: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x154 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x154 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7554; op2val:0xf554; + valaddr_reg:x6; val_offset:204*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 204*FLEN/8, x8, x2, x5) + +inst_129: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1be and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1be and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79be; op2val:0xf9be; + valaddr_reg:x6; val_offset:206*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 206*FLEN/8, x8, x2, x5) + +inst_130: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0f6 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0f6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78f6; op2val:0xf8f6; + valaddr_reg:x6; val_offset:208*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 208*FLEN/8, x8, x2, x5) + +inst_131: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x13d and fs2 == 1 and fe2 == 0x1c and fm2 == 0x13d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x713d; op2val:0xf13d; + valaddr_reg:x6; val_offset:210*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 210*FLEN/8, x8, x2, x5) + +inst_132: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a1 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x0a1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x74a1; op2val:0xf4a1; + valaddr_reg:x6; val_offset:212*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 212*FLEN/8, x8, x2, x5) + +inst_133: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x062 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x062 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7862; op2val:0xf862; + valaddr_reg:x6; val_offset:214*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 214*FLEN/8, x8, x2, x5) + +inst_134: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a5 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3a5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77a5; op2val:0xf7a5; + valaddr_reg:x6; val_offset:216*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 216*FLEN/8, x8, x2, x5) + +inst_135: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x22c and fs2 == 1 and fe2 == 0x1a and fm2 == 0x22c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6a2c; op2val:0xea2c; + valaddr_reg:x6; val_offset:218*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 218*FLEN/8, x8, x2, x5) + +inst_136: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x782e; op2val:0xf82e; + valaddr_reg:x6; val_offset:220*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 220*FLEN/8, x8, x2, x5) + +inst_137: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x272 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x272 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7672; op2val:0xf672; + valaddr_reg:x6; val_offset:222*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 222*FLEN/8, x8, x2, x5) + +inst_138: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a1 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2a1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x76a1; op2val:0xf6a1; + valaddr_reg:x6; val_offset:224*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 224*FLEN/8, x8, x2, x5) + +inst_139: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x344 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x344 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b44; op2val:0xfb44; + valaddr_reg:x6; val_offset:226*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 226*FLEN/8, x8, x2, x5) + +inst_140: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2b9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab9; op2val:0xfab9; + valaddr_reg:x6; val_offset:228*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 228*FLEN/8, x8, x2, x5) + +inst_141: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x17e and fs2 == 1 and fe2 == 0x1d and fm2 == 0x17e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x757e; op2val:0xf57e; + valaddr_reg:x6; val_offset:230*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 230*FLEN/8, x8, x2, x5) + +inst_142: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x198 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x198 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7998; op2val:0xf998; + valaddr_reg:x6; val_offset:232*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 232*FLEN/8, x8, x2, x5) + +inst_143: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d3 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x0d3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x74d3; op2val:0xf4d3; + valaddr_reg:x6; val_offset:234*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 234*FLEN/8, x8, x2, x5) + +inst_144: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x326 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x326 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b26; op2val:0xfb26; + valaddr_reg:x6; val_offset:236*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 236*FLEN/8, x8, x2, x5) + +inst_145: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x102 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x102 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7902; op2val:0xf902; + valaddr_reg:x6; val_offset:238*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 238*FLEN/8, x8, x2, x5) + +inst_146: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ca and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ca and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bca; op2val:0xfbca; + valaddr_reg:x6; val_offset:240*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 240*FLEN/8, x8, x2, x5) + +inst_147: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x036 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x036 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c36; op2val:0xec36; + valaddr_reg:x6; val_offset:242*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 242*FLEN/8, x8, x2, x5) + +inst_148: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79fe; op2val:0xf9fe; + valaddr_reg:x6; val_offset:244*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 244*FLEN/8, x8, x2, x5) + +inst_149: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x004 and fs2 == 1 and fe2 == 0x18 and fm2 == 0x004 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6004; op2val:0xe004; + valaddr_reg:x6; val_offset:246*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 246*FLEN/8, x8, x2, x5) + +inst_150: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x026 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x026 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7826; op2val:0xf826; + valaddr_reg:x6; val_offset:248*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 248*FLEN/8, x8, x2, x5) + +inst_151: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d0 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3d0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77d0; op2val:0xf7d0; + valaddr_reg:x6; val_offset:250*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 250*FLEN/8, x8, x2, x5) + +inst_152: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x16e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x16e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x796e; op2val:0xf96e; + valaddr_reg:x6; val_offset:252*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 252*FLEN/8, x8, x2, x5) + +inst_153: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1e3 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x1e3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x75e3; op2val:0xf5e3; + valaddr_reg:x6; val_offset:254*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 254*FLEN/8, x8, x2, x5) + +inst_154: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x02c and fs2 == 1 and fe2 == 0x1d and fm2 == 0x02c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x742c; op2val:0xf42c; + valaddr_reg:x6; val_offset:256*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 256*FLEN/8, x8, x2, x5) +RVTEST_SIGBASE(x2,signature_x2_1) + +inst_155: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e5 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2e5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x76e5; op2val:0xf6e5; + valaddr_reg:x6; val_offset:258*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 258*FLEN/8, x8, x2, x5) + +inst_156: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x015 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x015 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c15; op2val:0xec15; + valaddr_reg:x6; val_offset:260*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 260*FLEN/8, x8, x2, x5) + +inst_157: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x19d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x799d; op2val:0xf99d; + valaddr_reg:x6; val_offset:262*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 262*FLEN/8, x8, x2, x5) + +inst_158: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x338 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x338 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7738; op2val:0xf738; + valaddr_reg:x6; val_offset:264*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 264*FLEN/8, x8, x2, x5) + +inst_159: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x39b and fs2 == 1 and fe2 == 0x1b and fm2 == 0x39b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f9b; op2val:0xef9b; + valaddr_reg:x6; val_offset:266*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 266*FLEN/8, x8, x2, x5) + +inst_160: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2a0 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x2a0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x72a0; op2val:0xf2a0; + valaddr_reg:x6; val_offset:268*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 268*FLEN/8, x8, x2, x5) + +inst_161: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x394 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x394 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b94; op2val:0xfb94; + valaddr_reg:x6; val_offset:270*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 270*FLEN/8, x8, x2, x5) + +inst_162: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x20b and fs2 == 1 and fe2 == 0x1d and fm2 == 0x20b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x760b; op2val:0xf60b; + valaddr_reg:x6; val_offset:272*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 272*FLEN/8, x8, x2, x5) + +inst_163: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0d7 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0d7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x70d7; op2val:0xf0d7; + valaddr_reg:x6; val_offset:274*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 274*FLEN/8, x8, x2, x5) + +inst_164: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3dc and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3dc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bdc; op2val:0xfbdc; + valaddr_reg:x6; val_offset:276*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 276*FLEN/8, x8, x2, x5) + +inst_165: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x27d and fs2 == 1 and fe2 == 0x1d and fm2 == 0x27d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x767d; op2val:0xf67d; + valaddr_reg:x6; val_offset:278*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 278*FLEN/8, x8, x2, x5) + +inst_166: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x304 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x304 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b04; op2val:0xfb04; + valaddr_reg:x6; val_offset:280*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 280*FLEN/8, x8, x2, x5) + +inst_167: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x355 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x355 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b55; op2val:0xfb55; + valaddr_reg:x6; val_offset:282*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 282*FLEN/8, x8, x2, x5) + +inst_168: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77f8; op2val:0xf7f8; + valaddr_reg:x6; val_offset:284*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 284*FLEN/8, x8, x2, x5) + +inst_169: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x15b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x795b; op2val:0xf95b; + valaddr_reg:x6; val_offset:286*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 286*FLEN/8, x8, x2, x5) + +inst_170: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78e0; op2val:0xf8e0; + valaddr_reg:x6; val_offset:288*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 288*FLEN/8, x8, x2, x5) + +inst_171: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x170 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x170 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7570; op2val:0xf570; + valaddr_reg:x6; val_offset:290*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 290*FLEN/8, x8, x2, x5) + +inst_172: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x330 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x330 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b30; op2val:0xfb30; + valaddr_reg:x6; val_offset:292*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 292*FLEN/8, x8, x2, x5) + +inst_173: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x089 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x089 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6889; op2val:0xe889; + valaddr_reg:x6; val_offset:294*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 294*FLEN/8, x8, x2, x5) + +inst_174: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x01b and fs2 == 1 and fe2 == 0x1d and fm2 == 0x01b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x741b; op2val:0xf41b; + valaddr_reg:x6; val_offset:296*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 296*FLEN/8, x8, x2, x5) + +inst_175: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2bc and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2bc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7abc; op2val:0xfabc; + valaddr_reg:x6; val_offset:298*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 298*FLEN/8, x8, x2, x5) + +inst_176: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x03e and fs2 == 1 and fe2 == 0x1b and fm2 == 0x03e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c3e; op2val:0xec3e; + valaddr_reg:x6; val_offset:300*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 300*FLEN/8, x8, x2, x5) + +inst_177: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f2 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2f2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7af2; op2val:0xfaf2; + valaddr_reg:x6; val_offset:302*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 302*FLEN/8, x8, x2, x5) + +inst_178: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x333 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x333 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7333; op2val:0xf333; + valaddr_reg:x6; val_offset:304*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 304*FLEN/8, x8, x2, x5) + +inst_179: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x3d2 and fs2 == 1 and fe2 == 0x18 and fm2 == 0x3d2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x63d2; op2val:0xe3d2; + valaddr_reg:x6; val_offset:306*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 306*FLEN/8, x8, x2, x5) + +inst_180: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x149 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x149 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7549; op2val:0xf549; + valaddr_reg:x6; val_offset:308*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 308*FLEN/8, x8, x2, x5) + +inst_181: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0c2 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0c2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x70c2; op2val:0xf0c2; + valaddr_reg:x6; val_offset:310*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 310*FLEN/8, x8, x2, x5) + +inst_182: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3be and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3be and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bbe; op2val:0xfbbe; + valaddr_reg:x6; val_offset:312*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 312*FLEN/8, x8, x2, x5) + +inst_183: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x334 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x334 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b34; op2val:0xfb34; + valaddr_reg:x6; val_offset:314*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 314*FLEN/8, x8, x2, x5) + +inst_184: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x096 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x096 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7896; op2val:0xf896; + valaddr_reg:x6; val_offset:316*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 316*FLEN/8, x8, x2, x5) + +inst_185: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x270 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x270 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a70; op2val:0xfa70; + valaddr_reg:x6; val_offset:318*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 318*FLEN/8, x8, x2, x5) + +inst_186: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3eb and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3eb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7beb; op2val:0xfbeb; + valaddr_reg:x6; val_offset:320*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 320*FLEN/8, x8, x2, x5) + +inst_187: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x33e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x33e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b3e; op2val:0xfb3e; + valaddr_reg:x6; val_offset:322*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 322*FLEN/8, x8, x2, x5) + +inst_188: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x047 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x047 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7847; op2val:0xf847; + valaddr_reg:x6; val_offset:324*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 324*FLEN/8, x8, x2, x5) + +inst_189: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x29a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x29a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a9a; op2val:0xfa9a; + valaddr_reg:x6; val_offset:326*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 326*FLEN/8, x8, x2, x5) + +inst_190: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x253 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x253 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a53; op2val:0xfa53; + valaddr_reg:x6; val_offset:328*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 328*FLEN/8, x8, x2, x5) + +inst_191: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0b0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78b0; op2val:0xf8b0; + valaddr_reg:x6; val_offset:330*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 330*FLEN/8, x8, x2, x5) + +inst_192: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ac0; op2val:0xfac0; + valaddr_reg:x6; val_offset:332*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 332*FLEN/8, x8, x2, x5) + +inst_193: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x016 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x016 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7816; op2val:0xf816; + valaddr_reg:x6; val_offset:334*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 334*FLEN/8, x8, x2, x5) + +inst_194: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x125 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x125 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d25; op2val:0xed25; + valaddr_reg:x6; val_offset:336*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 336*FLEN/8, x8, x2, x5) + +inst_195: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2f9 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x2f9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ef9; op2val:0xeef9; + valaddr_reg:x6; val_offset:338*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 338*FLEN/8, x8, x2, x5) + +inst_196: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a6 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1a6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79a6; op2val:0xf9a6; + valaddr_reg:x6; val_offset:340*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x6, 340*FLEN/8, x8, x2, x5) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(31424,32,FLEN) +NAN_BOXED(31424,16,FLEN) +NAN_BOXED(30393,32,FLEN) +NAN_BOXED(63161,16,FLEN) +NAN_BOXED(30742,32,FLEN) +NAN_BOXED(30742,16,FLEN) +NAN_BOXED(31300,32,FLEN) +NAN_BOXED(64068,16,FLEN) +NAN_BOXED(30623,32,FLEN) +NAN_BOXED(63391,16,FLEN) +NAN_BOXED(31554,32,FLEN) +NAN_BOXED(64322,16,FLEN) +NAN_BOXED(29825,32,FLEN) +NAN_BOXED(62593,16,FLEN) +NAN_BOXED(30961,32,FLEN) +NAN_BOXED(63729,16,FLEN) +NAN_BOXED(31558,32,FLEN) +NAN_BOXED(64326,16,FLEN) +NAN_BOXED(31354,32,FLEN) +NAN_BOXED(64122,16,FLEN) +NAN_BOXED(29941,32,FLEN) +NAN_BOXED(62709,16,FLEN) +NAN_BOXED(31535,32,FLEN) +NAN_BOXED(64303,16,FLEN) +NAN_BOXED(30604,32,FLEN) +NAN_BOXED(63372,16,FLEN) +test_dataset_1: +NAN_BOXED(30449,32,FLEN) +NAN_BOXED(63217,16,FLEN) +NAN_BOXED(31564,32,FLEN) +NAN_BOXED(64332,16,FLEN) +NAN_BOXED(30624,32,FLEN) +NAN_BOXED(63392,16,FLEN) +NAN_BOXED(29738,32,FLEN) +NAN_BOXED(62506,16,FLEN) +NAN_BOXED(30819,32,FLEN) +NAN_BOXED(63587,16,FLEN) +NAN_BOXED(31169,32,FLEN) +NAN_BOXED(63937,16,FLEN) +NAN_BOXED(31384,32,FLEN) +NAN_BOXED(64152,16,FLEN) +NAN_BOXED(21677,32,FLEN) +NAN_BOXED(54445,16,FLEN) +NAN_BOXED(31471,32,FLEN) +NAN_BOXED(64239,16,FLEN) +NAN_BOXED(30003,32,FLEN) +NAN_BOXED(62771,16,FLEN) +NAN_BOXED(29212,32,FLEN) +NAN_BOXED(61980,16,FLEN) +NAN_BOXED(29601,32,FLEN) +NAN_BOXED(62369,16,FLEN) +NAN_BOXED(31340,32,FLEN) +NAN_BOXED(64108,16,FLEN) +test_dataset_2: +NAN_BOXED(27941,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(30735,16,FLEN) +NAN_BOXED(63503,16,FLEN) +NAN_BOXED(28409,16,FLEN) +NAN_BOXED(61177,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(63910,16,FLEN) +NAN_BOXED(31363,16,FLEN) +NAN_BOXED(64131,16,FLEN) +NAN_BOXED(31668,16,FLEN) +NAN_BOXED(64436,16,FLEN) +NAN_BOXED(30898,16,FLEN) +NAN_BOXED(63666,16,FLEN) +NAN_BOXED(30916,16,FLEN) +NAN_BOXED(63684,16,FLEN) +NAN_BOXED(30874,16,FLEN) +NAN_BOXED(63642,16,FLEN) +NAN_BOXED(29198,16,FLEN) +NAN_BOXED(61966,16,FLEN) +NAN_BOXED(30950,16,FLEN) +NAN_BOXED(63718,16,FLEN) +NAN_BOXED(30622,16,FLEN) +NAN_BOXED(63390,16,FLEN) +NAN_BOXED(31246,16,FLEN) +NAN_BOXED(64014,16,FLEN) +NAN_BOXED(31586,16,FLEN) +NAN_BOXED(64354,16,FLEN) +NAN_BOXED(31534,16,FLEN) +NAN_BOXED(64302,16,FLEN) +NAN_BOXED(30802,16,FLEN) +NAN_BOXED(63570,16,FLEN) +NAN_BOXED(31139,16,FLEN) +NAN_BOXED(63907,16,FLEN) +NAN_BOXED(31357,16,FLEN) +NAN_BOXED(64125,16,FLEN) +NAN_BOXED(31528,16,FLEN) +NAN_BOXED(64296,16,FLEN) +NAN_BOXED(31640,16,FLEN) +NAN_BOXED(64408,16,FLEN) +NAN_BOXED(30516,16,FLEN) +NAN_BOXED(63284,16,FLEN) +NAN_BOXED(31735,16,FLEN) +NAN_BOXED(64503,16,FLEN) +NAN_BOXED(31319,16,FLEN) +NAN_BOXED(64087,16,FLEN) +NAN_BOXED(30985,16,FLEN) +NAN_BOXED(63753,16,FLEN) +NAN_BOXED(29637,16,FLEN) +NAN_BOXED(62405,16,FLEN) +NAN_BOXED(28542,16,FLEN) +NAN_BOXED(61310,16,FLEN) +NAN_BOXED(31322,16,FLEN) +NAN_BOXED(64090,16,FLEN) +NAN_BOXED(31366,16,FLEN) +NAN_BOXED(64134,16,FLEN) +NAN_BOXED(28846,16,FLEN) +NAN_BOXED(61614,16,FLEN) +NAN_BOXED(27081,16,FLEN) +NAN_BOXED(59849,16,FLEN) +NAN_BOXED(31089,16,FLEN) +NAN_BOXED(63857,16,FLEN) +NAN_BOXED(30995,16,FLEN) +NAN_BOXED(63763,16,FLEN) +NAN_BOXED(30187,16,FLEN) +NAN_BOXED(62955,16,FLEN) +NAN_BOXED(26791,16,FLEN) +NAN_BOXED(59559,16,FLEN) +NAN_BOXED(31663,16,FLEN) +NAN_BOXED(64431,16,FLEN) +NAN_BOXED(28652,16,FLEN) +NAN_BOXED(61420,16,FLEN) +NAN_BOXED(31335,16,FLEN) +NAN_BOXED(64103,16,FLEN) +NAN_BOXED(26068,16,FLEN) +NAN_BOXED(58836,16,FLEN) +NAN_BOXED(28286,16,FLEN) +NAN_BOXED(61054,16,FLEN) +NAN_BOXED(29456,16,FLEN) +NAN_BOXED(62224,16,FLEN) +NAN_BOXED(30106,16,FLEN) +NAN_BOXED(62874,16,FLEN) +NAN_BOXED(30726,16,FLEN) +NAN_BOXED(63494,16,FLEN) +NAN_BOXED(28276,16,FLEN) +NAN_BOXED(61044,16,FLEN) +NAN_BOXED(29280,16,FLEN) +NAN_BOXED(62048,16,FLEN) +NAN_BOXED(31193,16,FLEN) +NAN_BOXED(63961,16,FLEN) +NAN_BOXED(31576,16,FLEN) +NAN_BOXED(64344,16,FLEN) +NAN_BOXED(31072,16,FLEN) +NAN_BOXED(63840,16,FLEN) +NAN_BOXED(27501,16,FLEN) +NAN_BOXED(60269,16,FLEN) +NAN_BOXED(31426,16,FLEN) +NAN_BOXED(64194,16,FLEN) +NAN_BOXED(29698,16,FLEN) +NAN_BOXED(62466,16,FLEN) +NAN_BOXED(30482,16,FLEN) +NAN_BOXED(63250,16,FLEN) +NAN_BOXED(30602,16,FLEN) +NAN_BOXED(63370,16,FLEN) +NAN_BOXED(30860,16,FLEN) +NAN_BOXED(63628,16,FLEN) +NAN_BOXED(29947,16,FLEN) +NAN_BOXED(62715,16,FLEN) +NAN_BOXED(31410,16,FLEN) +NAN_BOXED(64178,16,FLEN) +NAN_BOXED(30843,16,FLEN) +NAN_BOXED(63611,16,FLEN) +NAN_BOXED(31214,16,FLEN) +NAN_BOXED(63982,16,FLEN) +NAN_BOXED(27096,16,FLEN) +NAN_BOXED(59864,16,FLEN) +NAN_BOXED(29614,16,FLEN) +NAN_BOXED(62382,16,FLEN) +NAN_BOXED(30114,16,FLEN) +NAN_BOXED(62882,16,FLEN) +NAN_BOXED(30142,16,FLEN) +NAN_BOXED(62910,16,FLEN) +NAN_BOXED(30993,16,FLEN) +NAN_BOXED(63761,16,FLEN) +NAN_BOXED(31160,16,FLEN) +NAN_BOXED(63928,16,FLEN) +NAN_BOXED(30368,16,FLEN) +NAN_BOXED(63136,16,FLEN) +NAN_BOXED(22077,16,FLEN) +NAN_BOXED(54845,16,FLEN) +NAN_BOXED(30041,16,FLEN) +NAN_BOXED(62809,16,FLEN) +NAN_BOXED(31000,16,FLEN) +NAN_BOXED(63768,16,FLEN) +NAN_BOXED(31487,16,FLEN) +NAN_BOXED(64255,16,FLEN) +NAN_BOXED(31132,16,FLEN) +NAN_BOXED(63900,16,FLEN) +NAN_BOXED(31051,16,FLEN) +NAN_BOXED(63819,16,FLEN) +NAN_BOXED(30495,16,FLEN) +NAN_BOXED(63263,16,FLEN) +NAN_BOXED(28939,16,FLEN) +NAN_BOXED(61707,16,FLEN) +NAN_BOXED(30666,16,FLEN) +NAN_BOXED(63434,16,FLEN) +NAN_BOXED(31242,16,FLEN) +NAN_BOXED(64010,16,FLEN) +NAN_BOXED(30696,16,FLEN) +NAN_BOXED(63464,16,FLEN) +NAN_BOXED(30583,16,FLEN) +NAN_BOXED(63351,16,FLEN) +NAN_BOXED(29187,16,FLEN) +NAN_BOXED(61955,16,FLEN) +NAN_BOXED(30991,16,FLEN) +NAN_BOXED(63759,16,FLEN) +NAN_BOXED(31181,16,FLEN) +NAN_BOXED(63949,16,FLEN) +NAN_BOXED(30317,16,FLEN) +NAN_BOXED(63085,16,FLEN) +NAN_BOXED(29966,16,FLEN) +NAN_BOXED(62734,16,FLEN) +NAN_BOXED(31164,16,FLEN) +NAN_BOXED(63932,16,FLEN) +NAN_BOXED(31380,16,FLEN) +NAN_BOXED(64148,16,FLEN) +NAN_BOXED(28225,16,FLEN) +NAN_BOXED(60993,16,FLEN) +NAN_BOXED(31025,16,FLEN) +NAN_BOXED(63793,16,FLEN) +NAN_BOXED(29818,16,FLEN) +NAN_BOXED(62586,16,FLEN) +NAN_BOXED(28264,16,FLEN) +NAN_BOXED(61032,16,FLEN) +NAN_BOXED(30296,16,FLEN) +NAN_BOXED(63064,16,FLEN) +NAN_BOXED(29796,16,FLEN) +NAN_BOXED(62564,16,FLEN) +NAN_BOXED(31317,16,FLEN) +NAN_BOXED(64085,16,FLEN) +NAN_BOXED(28740,16,FLEN) +NAN_BOXED(61508,16,FLEN) +NAN_BOXED(31028,16,FLEN) +NAN_BOXED(63796,16,FLEN) +NAN_BOXED(31480,16,FLEN) +NAN_BOXED(64248,16,FLEN) +NAN_BOXED(25792,16,FLEN) +NAN_BOXED(58560,16,FLEN) +NAN_BOXED(31090,16,FLEN) +NAN_BOXED(63858,16,FLEN) +NAN_BOXED(31633,16,FLEN) +NAN_BOXED(64401,16,FLEN) +NAN_BOXED(31229,16,FLEN) +NAN_BOXED(63997,16,FLEN) +NAN_BOXED(31037,16,FLEN) +NAN_BOXED(63805,16,FLEN) +NAN_BOXED(31543,16,FLEN) +NAN_BOXED(64311,16,FLEN) +NAN_BOXED(30196,16,FLEN) +NAN_BOXED(62964,16,FLEN) +NAN_BOXED(29349,16,FLEN) +NAN_BOXED(62117,16,FLEN) +NAN_BOXED(24717,16,FLEN) +NAN_BOXED(57485,16,FLEN) +NAN_BOXED(30036,16,FLEN) +NAN_BOXED(62804,16,FLEN) +NAN_BOXED(31166,16,FLEN) +NAN_BOXED(63934,16,FLEN) +NAN_BOXED(30966,16,FLEN) +NAN_BOXED(63734,16,FLEN) +NAN_BOXED(28989,16,FLEN) +NAN_BOXED(61757,16,FLEN) +NAN_BOXED(29857,16,FLEN) +NAN_BOXED(62625,16,FLEN) +NAN_BOXED(30818,16,FLEN) +NAN_BOXED(63586,16,FLEN) +NAN_BOXED(30629,16,FLEN) +NAN_BOXED(63397,16,FLEN) +NAN_BOXED(27180,16,FLEN) +NAN_BOXED(59948,16,FLEN) +NAN_BOXED(30766,16,FLEN) +NAN_BOXED(63534,16,FLEN) +NAN_BOXED(30322,16,FLEN) +NAN_BOXED(63090,16,FLEN) +NAN_BOXED(30369,16,FLEN) +NAN_BOXED(63137,16,FLEN) +NAN_BOXED(31556,16,FLEN) +NAN_BOXED(64324,16,FLEN) +NAN_BOXED(31417,16,FLEN) +NAN_BOXED(64185,16,FLEN) +NAN_BOXED(30078,16,FLEN) +NAN_BOXED(62846,16,FLEN) +NAN_BOXED(31128,16,FLEN) +NAN_BOXED(63896,16,FLEN) +NAN_BOXED(29907,16,FLEN) +NAN_BOXED(62675,16,FLEN) +NAN_BOXED(31526,16,FLEN) +NAN_BOXED(64294,16,FLEN) +NAN_BOXED(30978,16,FLEN) +NAN_BOXED(63746,16,FLEN) +NAN_BOXED(31690,16,FLEN) +NAN_BOXED(64458,16,FLEN) +NAN_BOXED(27702,16,FLEN) +NAN_BOXED(60470,16,FLEN) +NAN_BOXED(31230,16,FLEN) +NAN_BOXED(63998,16,FLEN) +NAN_BOXED(24580,16,FLEN) +NAN_BOXED(57348,16,FLEN) +NAN_BOXED(30758,16,FLEN) +NAN_BOXED(63526,16,FLEN) +NAN_BOXED(30672,16,FLEN) +NAN_BOXED(63440,16,FLEN) +NAN_BOXED(31086,16,FLEN) +NAN_BOXED(63854,16,FLEN) +NAN_BOXED(30179,16,FLEN) +NAN_BOXED(62947,16,FLEN) +NAN_BOXED(29740,16,FLEN) +NAN_BOXED(62508,16,FLEN) +NAN_BOXED(30437,16,FLEN) +NAN_BOXED(63205,16,FLEN) +NAN_BOXED(27669,16,FLEN) +NAN_BOXED(60437,16,FLEN) +NAN_BOXED(31133,16,FLEN) +NAN_BOXED(63901,16,FLEN) +NAN_BOXED(30520,16,FLEN) +NAN_BOXED(63288,16,FLEN) +NAN_BOXED(28571,16,FLEN) +NAN_BOXED(61339,16,FLEN) +NAN_BOXED(29344,16,FLEN) +NAN_BOXED(62112,16,FLEN) +NAN_BOXED(31636,16,FLEN) +NAN_BOXED(64404,16,FLEN) +NAN_BOXED(30219,16,FLEN) +NAN_BOXED(62987,16,FLEN) +NAN_BOXED(28887,16,FLEN) +NAN_BOXED(61655,16,FLEN) +NAN_BOXED(31708,16,FLEN) +NAN_BOXED(64476,16,FLEN) +NAN_BOXED(30333,16,FLEN) +NAN_BOXED(63101,16,FLEN) +NAN_BOXED(31492,16,FLEN) +NAN_BOXED(64260,16,FLEN) +NAN_BOXED(31573,16,FLEN) +NAN_BOXED(64341,16,FLEN) +NAN_BOXED(30712,16,FLEN) +NAN_BOXED(63480,16,FLEN) +NAN_BOXED(31067,16,FLEN) +NAN_BOXED(63835,16,FLEN) +NAN_BOXED(30944,16,FLEN) +NAN_BOXED(63712,16,FLEN) +NAN_BOXED(30064,16,FLEN) +NAN_BOXED(62832,16,FLEN) +NAN_BOXED(31536,16,FLEN) +NAN_BOXED(64304,16,FLEN) +NAN_BOXED(26761,16,FLEN) +NAN_BOXED(59529,16,FLEN) +NAN_BOXED(29723,16,FLEN) +NAN_BOXED(62491,16,FLEN) +NAN_BOXED(31420,16,FLEN) +NAN_BOXED(64188,16,FLEN) +NAN_BOXED(27710,16,FLEN) +NAN_BOXED(60478,16,FLEN) +NAN_BOXED(31474,16,FLEN) +NAN_BOXED(64242,16,FLEN) +NAN_BOXED(29491,16,FLEN) +NAN_BOXED(62259,16,FLEN) +NAN_BOXED(25554,16,FLEN) +NAN_BOXED(58322,16,FLEN) +NAN_BOXED(30025,16,FLEN) +NAN_BOXED(62793,16,FLEN) +NAN_BOXED(28866,16,FLEN) +NAN_BOXED(61634,16,FLEN) +NAN_BOXED(31678,16,FLEN) +NAN_BOXED(64446,16,FLEN) +NAN_BOXED(31540,16,FLEN) +NAN_BOXED(64308,16,FLEN) +NAN_BOXED(30870,16,FLEN) +NAN_BOXED(63638,16,FLEN) +NAN_BOXED(31344,16,FLEN) +NAN_BOXED(64112,16,FLEN) +NAN_BOXED(31723,16,FLEN) +NAN_BOXED(64491,16,FLEN) +NAN_BOXED(31550,16,FLEN) +NAN_BOXED(64318,16,FLEN) +NAN_BOXED(30791,16,FLEN) +NAN_BOXED(63559,16,FLEN) +NAN_BOXED(31386,16,FLEN) +NAN_BOXED(64154,16,FLEN) +NAN_BOXED(31315,16,FLEN) +NAN_BOXED(64083,16,FLEN) +NAN_BOXED(30896,16,FLEN) +NAN_BOXED(63664,16,FLEN) +NAN_BOXED(31424,16,FLEN) +NAN_BOXED(64192,16,FLEN) +NAN_BOXED(30742,16,FLEN) +NAN_BOXED(63510,16,FLEN) +NAN_BOXED(27941,16,FLEN) +NAN_BOXED(60709,16,FLEN) +NAN_BOXED(28409,16,FLEN) +NAN_BOXED(61177,16,FLEN) +NAN_BOXED(31142,16,FLEN) +NAN_BOXED(63910,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x15_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x15_1: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x4_0: + .fill 26*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_0: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_1: + .fill 84*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fadd_b2-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fadd_b2-01.S new file mode 100644 index 000000000..15d6c9350 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fadd_b2-01.S @@ -0,0 +1,1344 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 05:45:15 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fadd.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fadd.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fadd_b2 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fadd_b2) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x18,test_dataset_0) +RVTEST_SIGBASE(x8,signature_x8_1) + +inst_0: +// rs1 == rs2 != rd, rs1==x29, rs2==x29, rd==x15,fs1 == 0 and fe1 == 0x00 and fm1 == 0x032 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x030 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x29; op2:x29; dest:x15; op1val:0x32; op2val:0x32; + valaddr_reg:x18; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fadd.h, x15, x29, x29, dyn, 0, 0, x18, 0*FLEN/8, x19, x8, x9) + +inst_1: +// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==x0, rs2==x17, rd==x5,fs1 == 0 and fe1 == 0x00 and fm1 == 0x036 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x034 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x0; op2:x17; dest:x5; op1val:0x0; op2val:0x8034; + valaddr_reg:x18; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fadd.h, x5, x0, x17, dyn, 0, 0, x18, 2*FLEN/8, x19, x8, x9) + +inst_2: +// rs1 == rs2 == rd, rs1==x13, rs2==x13, rd==x13,fs1 == 0 and fe1 == 0x00 and fm1 == 0x022 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x01e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x13; op2:x13; dest:x13; op1val:0x22; op2val:0x22; + valaddr_reg:x18; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fadd.h, x13, x13, x13, dyn, 0, 0, x18, 4*FLEN/8, x19, x8, x9) + +inst_3: +// rs2 == rd != rs1, rs1==x17, rs2==x0, rd==x0,fs1 == 0 and fe1 == 0x00 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x037 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x17; op2:x0; dest:x0; op1val:0x3f; op2val:0x0; + valaddr_reg:x18; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fadd.h, x0, x17, x0, dyn, 0, 0, x18, 6*FLEN/8, x19, x8, x9) + +inst_4: +// rs1 == rd != rs2, rs1==x2, rs2==x30, rd==x2,fs1 == 0 and fe1 == 0x00 and fm1 == 0x027 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x017 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x2; op2:x30; dest:x2; op1val:0x27; op2val:0x8017; + valaddr_reg:x18; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fadd.h, x2, x2, x30, dyn, 0, 0, x18, 8*FLEN/8, x19, x8, x9) + +inst_5: +// rs1==x1, rs2==x26, rd==x23,fs1 == 0 and fe1 == 0x00 and fm1 == 0x02e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x1; op2:x26; dest:x23; op1val:0x2e; op2val:0x800e; + valaddr_reg:x18; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fadd.h, x23, x1, x26, dyn, 0, 0, x18, 10*FLEN/8, x19, x8, x9) + +inst_6: +// rs1==x12, rs2==x24, rd==x11,fs1 == 0 and fe1 == 0x00 and fm1 == 0x01c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x024 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x12; op2:x24; dest:x11; op1val:0x1c; op2val:0x24; + valaddr_reg:x18; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fadd.h, x11, x12, x24, dyn, 0, 0, x18, 12*FLEN/8, x19, x8, x9) + +inst_7: +// rs1==x7, rs2==x28, rd==x22,fs1 == 0 and fe1 == 0x00 and fm1 == 0x012 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x06e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x7; op2:x28; dest:x22; op1val:0x12; op2val:0x6e; + valaddr_reg:x18; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fadd.h, x22, x7, x28, dyn, 0, 0, x18, 14*FLEN/8, x19, x8, x9) + +inst_8: +// rs1==x22, rs2==x4, rd==x14,fs1 == 0 and fe1 == 0x00 and fm1 == 0x012 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0ee and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x22; op2:x4; dest:x14; op1val:0x12; op2val:0xee; + valaddr_reg:x18; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fadd.h, x14, x22, x4, dyn, 0, 0, x18, 16*FLEN/8, x19, x8, x9) + +inst_9: +// rs1==x11, rs2==x7, rd==x3,fs1 == 0 and fe1 == 0x00 and fm1 == 0x00d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1f3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x11; op2:x7; dest:x3; op1val:0xd; op2val:0x1f3; + valaddr_reg:x18; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fadd.h, x3, x11, x7, dyn, 0, 0, x18, 18*FLEN/8, x19, x8, x9) + +inst_10: +// rs1==x23, rs2==x1, rd==x6,fs1 == 0 and fe1 == 0x00 and fm1 == 0x021 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x022 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x23; op2:x1; dest:x6; op1val:0x21; op2val:0x8022; + valaddr_reg:x18; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fadd.h, x6, x23, x1, dyn, 0, 0, x18, 20*FLEN/8, x19, x8, x9) + +inst_11: +// rs1==x20, rs2==x12, rd==x16,fs1 == 0 and fe1 == 0x00 and fm1 == 0x05b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x05d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x20; op2:x12; dest:x16; op1val:0x5b; op2val:0x805d; + valaddr_reg:x18; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fadd.h, x16, x20, x12, dyn, 0, 0, x18, 22*FLEN/8, x19, x8, x9) + +inst_12: +// rs1==x10, rs2==x14, rd==x20,fs1 == 0 and fe1 == 0x00 and fm1 == 0x013 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x017 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x10; op2:x14; dest:x20; op1val:0x13; op2val:0x8017; + valaddr_reg:x18; val_offset:24*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fadd.h, x20, x10, x14, dyn, 0, 0, x18, 24*FLEN/8, x19, x8, x9) +RVTEST_VALBASEUPD(x2,test_dataset_1) + +inst_13: +// rs1==x27, rs2==x23, rd==x18,fs1 == 0 and fe1 == 0x00 and fm1 == 0x00d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x015 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x27; op2:x23; dest:x18; op1val:0xd; op2val:0x8015; + valaddr_reg:x2; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fadd.h, x18, x27, x23, dyn, 0, 0, x2, 0*FLEN/8, x5, x8, x9) + +inst_14: +// rs1==x4, rs2==x22, rd==x25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x00a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x01a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x4; op2:x22; dest:x25; op1val:0xa; op2val:0x801a; + valaddr_reg:x2; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x25, x4, x22, dyn, 0, 0, x2, 2*FLEN/8, x5, x8, x1) +RVTEST_SIGBASE(x13,signature_x13_0) + +inst_15: +// rs1==x6, rs2==x21, rd==x19,fs1 == 0 and fe1 == 0x00 and fm1 == 0x02b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x04b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x6; op2:x21; dest:x19; op1val:0x2b; op2val:0x804b; + valaddr_reg:x2; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x19, x6, x21, dyn, 0, 0, x2, 4*FLEN/8, x5, x13, x1) + +inst_16: +// rs1==x21, rs2==x6, rd==x12,fs1 == 0 and fe1 == 0x00 and fm1 == 0x048 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x088 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x21; op2:x6; dest:x12; op1val:0x48; op2val:0x8088; + valaddr_reg:x2; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x12, x21, x6, dyn, 0, 0, x2, 6*FLEN/8, x5, x13, x1) + +inst_17: +// rs1==x19, rs2==x10, rd==x29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x02e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0ae and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x19; op2:x10; dest:x29; op1val:0x2e; op2val:0x80ae; + valaddr_reg:x2; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x29, x19, x10, dyn, 0, 0, x2, 8*FLEN/8, x5, x13, x1) + +inst_18: +// rs1==x18, rs2==x8, rd==x27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x029 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x129 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x18; op2:x8; dest:x27; op1val:0x29; op2val:0x8129; + valaddr_reg:x2; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x27, x18, x8, dyn, 0, 0, x2, 10*FLEN/8, x5, x13, x1) + +inst_19: +// rs1==x9, rs2==x18, rd==x4,fs1 == 0 and fe1 == 0x00 and fm1 == 0x052 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x252 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x9; op2:x18; dest:x4; op1val:0x52; op2val:0x8252; + valaddr_reg:x2; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x4, x9, x18, dyn, 0, 0, x2, 12*FLEN/8, x5, x13, x1) + +inst_20: +// rs1==x31, rs2==x11, rd==x17,fs1 == 0 and fe1 == 0x0f and fm1 == 0x047 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x060 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x31; op2:x11; dest:x17; op1val:0x3c47; op2val:0xac60; + valaddr_reg:x2; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x17, x31, x11, dyn, 0, 0, x2, 14*FLEN/8, x5, x13, x1) + +inst_21: +// rs1==x14, rs2==x9, rd==x26,fs1 == 0 and fe1 == 0x0f and fm1 == 0x039 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x2e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x14; op2:x9; dest:x26; op1val:0x3c39; op2val:0xaae0; + valaddr_reg:x2; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x26, x14, x9, dyn, 0, 0, x2, 16*FLEN/8, x5, x13, x1) + +inst_22: +// rs1==x24, rs2==x15, rd==x28,fs1 == 0 and fe1 == 0x0f and fm1 == 0x022 and fs2 == 1 and fe2 == 0x09 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x24; op2:x15; dest:x28; op1val:0x3c22; op2val:0xa780; + valaddr_reg:x2; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x28, x24, x15, dyn, 0, 0, x2, 18*FLEN/8, x5, x13, x1) + +inst_23: +// rs1==x15, rs2==x27, rd==x24,fs1 == 0 and fe1 == 0x0f and fm1 == 0x047 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x15; op2:x27; dest:x24; op1val:0x3c47; op2val:0xabe0; + valaddr_reg:x2; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x24, x15, x27, dyn, 0, 0, x2, 20*FLEN/8, x5, x13, x1) + +inst_24: +// rs1==x30, rs2==x3, rd==x10,fs1 == 0 and fe1 == 0x0f and fm1 == 0x00c and fs2 == 0 and fe2 == 0x07 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x3; dest:x10; op1val:0x3c0c; op2val:0x1c00; + valaddr_reg:x2; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x10, x30, x3, dyn, 0, 0, x2, 22*FLEN/8, x5, x13, x1) +RVTEST_VALBASEUPD(x4,test_dataset_2) + +inst_25: +// rs1==x3, rs2==x2, rd==x31,fs1 == 0 and fe1 == 0x0f and fm1 == 0x034 and fs2 == 1 and fe2 == 0x09 and fm2 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x3; op2:x2; dest:x31; op1val:0x3c34; op2val:0xa500; + valaddr_reg:x4; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x3, x2, dyn, 0, 0, x4, 0*FLEN/8, x6, x13, x1) + +inst_26: +// rs1==x26, rs2==x31, rd==x7,fs1 == 0 and fe1 == 0x0f and fm1 == 0x056 and fs2 == 1 and fe2 == 0x09 and fm2 == 0x180 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x26; op2:x31; dest:x7; op1val:0x3c56; op2val:0xa580; + valaddr_reg:x4; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x7, x26, x31, dyn, 0, 0, x4, 2*FLEN/8, x6, x13, x1) + +inst_27: +// rs1==x5, rs2==x25, rd==x21,fs1 == 0 and fe1 == 0x0f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x5; op2:x25; dest:x21; op1val:0x3c01; op2val:0x2ff0; + valaddr_reg:x4; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x21, x5, x25, dyn, 0, 0, x4, 4*FLEN/8, x6, x13, x2) + +inst_28: +// rs1==x8, rs2==x19, rd==x1,fs1 == 0 and fe1 == 0x0f and fm1 == 0x040 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x8; op2:x19; dest:x1; op1val:0x3c40; op2val:0x3200; + valaddr_reg:x4; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x1, x8, x19, dyn, 0, 0, x4, 6*FLEN/8, x6, x13, x2) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_29: +// rs1==x28, rs2==x20, rd==x30,fs1 == 0 and fe1 == 0x0f and fm1 == 0x020 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x28; op2:x20; dest:x30; op1val:0x3c20; op2val:0x3780; + valaddr_reg:x4; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x30, x28, x20, dyn, 0, 0, x4, 8*FLEN/8, x6, x1, x2) + +inst_30: +// rs1==x25, rs2==x16, rd==x9,fs1 == 0 and fe1 == 0x0f and fm1 == 0x02a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x015 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x25; op2:x16; dest:x9; op1val:0x3c2a; op2val:0xc015; + valaddr_reg:x4; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x9, x25, x16, dyn, 0, 0, x4, 10*FLEN/8, x6, x1, x2) + +inst_31: +// rs1==x16, rs2==x5, rd==x8,fs1 == 0 and fe1 == 0x0f and fm1 == 0x009 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x005 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x16; op2:x5; dest:x8; op1val:0x3c09; op2val:0xc005; + valaddr_reg:x4; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x8, x16, x5, dyn, 0, 0, x4, 12*FLEN/8, x6, x1, x2) + +inst_32: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x049 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x026 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c49; op2val:0xc026; + valaddr_reg:x4; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 14*FLEN/8, x6, x1, x2) + +inst_33: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x01f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x013 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c1f; op2val:0xc013; + valaddr_reg:x4; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 16*FLEN/8, x6, x1, x2) + +inst_34: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x046 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x02b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c46; op2val:0xc02b; + valaddr_reg:x4; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 18*FLEN/8, x6, x1, x2) + +inst_35: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x00c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x016 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c0c; op2val:0xc016; + valaddr_reg:x4; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 20*FLEN/8, x6, x1, x2) + +inst_36: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x029 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x034 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c29; op2val:0xc034; + valaddr_reg:x4; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 22*FLEN/8, x6, x1, x2) + +inst_37: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x03f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x05f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c3f; op2val:0xc05f; + valaddr_reg:x4; val_offset:24*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 24*FLEN/8, x6, x1, x2) + +inst_38: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x027 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x093 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c27; op2val:0xc093; + valaddr_reg:x4; val_offset:26*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 26*FLEN/8, x6, x1, x2) + +inst_39: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x026 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x113 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c26; op2val:0xc113; + valaddr_reg:x4; val_offset:28*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 28*FLEN/8, x6, x1, x2) + +inst_40: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x010 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x10; op2val:0x800e; + valaddr_reg:x4; val_offset:30*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 30*FLEN/8, x6, x1, x2) + +inst_41: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x02b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x028 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b; op2val:0x8028; + valaddr_reg:x4; val_offset:32*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 32*FLEN/8, x6, x1, x2) + +inst_42: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x01b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x016 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1b; op2val:0x8016; + valaddr_reg:x4; val_offset:34*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 34*FLEN/8, x6, x1, x2) + +inst_43: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x03e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x47; op2val:0x803e; + valaddr_reg:x4; val_offset:36*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 36*FLEN/8, x6, x1, x2) + +inst_44: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x025 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x014 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x25; op2val:0x8014; + valaddr_reg:x4; val_offset:38*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 38*FLEN/8, x6, x1, x2) + +inst_45: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x015 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc; op2val:0x15; + valaddr_reg:x4; val_offset:40*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 40*FLEN/8, x6, x1, x2) + +inst_46: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x032 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x32; op2val:0xf; + valaddr_reg:x4; val_offset:42*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 42*FLEN/8, x6, x1, x2) + +inst_47: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x04a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x037 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4a; op2val:0x37; + valaddr_reg:x4; val_offset:44*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 44*FLEN/8, x6, x1, x2) + +inst_48: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x026 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0db and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x26; op2val:0xdb; + valaddr_reg:x4; val_offset:46*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 46*FLEN/8, x6, x1, x2) + +inst_49: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x019 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1e8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x19; op2val:0x1e8; + valaddr_reg:x4; val_offset:48*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 48*FLEN/8, x6, x1, x2) + +inst_50: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x005 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x006 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5; op2val:0x8006; + valaddr_reg:x4; val_offset:50*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 50*FLEN/8, x6, x1, x2) + +inst_51: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x058 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x55; op2val:0x8058; + valaddr_reg:x4; val_offset:52*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 52*FLEN/8, x6, x1, x2) + +inst_52: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x042 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3d; op2val:0x8042; + valaddr_reg:x4; val_offset:54*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 54*FLEN/8, x6, x1, x2) + +inst_53: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x015 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc; op2val:0x8015; + valaddr_reg:x4; val_offset:56*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 56*FLEN/8, x6, x1, x2) + +inst_54: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x061 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x072 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x61; op2val:0x8072; + valaddr_reg:x4; val_offset:58*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 58*FLEN/8, x6, x1, x2) + +inst_55: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x014 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x035 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x14; op2val:0x8035; + valaddr_reg:x4; val_offset:60*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 60*FLEN/8, x6, x1, x2) + +inst_56: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x04c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xb; op2val:0x804c; + valaddr_reg:x4; val_offset:62*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 62*FLEN/8, x6, x1, x2) + +inst_57: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x046 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0c7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x46; op2val:0x80c7; + valaddr_reg:x4; val_offset:64*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 64*FLEN/8, x6, x1, x2) + +inst_58: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x033 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x134 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x33; op2val:0x8134; + valaddr_reg:x4; val_offset:66*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 66*FLEN/8, x6, x1, x2) + +inst_59: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x044 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x245 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x44; op2val:0x8245; + valaddr_reg:x4; val_offset:68*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 68*FLEN/8, x6, x1, x2) + +inst_60: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x043 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3bb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x43; op2val:0x3bb; + valaddr_reg:x4; val_offset:70*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 70*FLEN/8, x6, x1, x2) + +inst_61: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x01c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3e1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1c; op2val:0x3e1; + valaddr_reg:x4; val_offset:72*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 72*FLEN/8, x6, x1, x2) + +inst_62: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x04c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3af and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4c; op2val:0x3af; + valaddr_reg:x4; val_offset:74*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 74*FLEN/8, x6, x1, x2) + +inst_63: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x04b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ac and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4b; op2val:0x3ac; + valaddr_reg:x4; val_offset:76*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 76*FLEN/8, x6, x1, x2) + +inst_64: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3b5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a; op2val:0x3b5; + valaddr_reg:x4; val_offset:78*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 78*FLEN/8, x6, x1, x2) + +inst_65: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x38a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x55; op2val:0x38a; + valaddr_reg:x4; val_offset:80*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 80*FLEN/8, x6, x1, x2) + +inst_66: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x05a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5a; op2val:0x365; + valaddr_reg:x4; val_offset:82*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 82*FLEN/8, x6, x1, x2) + +inst_67: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x374 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xb; op2val:0x374; + valaddr_reg:x4; val_offset:84*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 84*FLEN/8, x6, x1, x2) + +inst_68: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x04f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2b0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4f; op2val:0x2b0; + valaddr_reg:x4; val_offset:86*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 86*FLEN/8, x6, x1, x2) + +inst_69: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3f; op2val:0x1c0; + valaddr_reg:x4; val_offset:88*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 88*FLEN/8, x6, x1, x2) + +inst_70: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x051 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x04f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x51; op2val:0x844f; + valaddr_reg:x4; val_offset:90*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 90*FLEN/8, x6, x1, x2) + +inst_71: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x019 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x016 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x19; op2val:0x8416; + valaddr_reg:x4; val_offset:92*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 92*FLEN/8, x6, x1, x2) + +inst_72: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3; op2val:0x83fe; + valaddr_reg:x4; val_offset:94*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 94*FLEN/8, x6, x1, x2) + +inst_73: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x023 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x23; op2val:0x841a; + valaddr_reg:x4; val_offset:96*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 96*FLEN/8, x6, x1, x2) + +inst_74: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x05b and fs2 == 1 and fe2 == 0x01 and fm2 == 0x04a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5b; op2val:0x844a; + valaddr_reg:x4; val_offset:98*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 98*FLEN/8, x6, x1, x2) + +inst_75: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x030 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x30; op2val:0x840f; + valaddr_reg:x4; val_offset:100*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 100*FLEN/8, x6, x1, x2) + +inst_76: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x02b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ea and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b; op2val:0x83ea; + valaddr_reg:x4; val_offset:102*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 102*FLEN/8, x6, x1, x2) + +inst_77: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x008 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x387 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8; op2val:0x8387; + valaddr_reg:x4; val_offset:104*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 104*FLEN/8, x6, x1, x2) + +inst_78: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x013 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x312 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x13; op2val:0x8312; + valaddr_reg:x4; val_offset:106*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 106*FLEN/8, x6, x1, x2) + +inst_79: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x01d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1d; op2val:0x821c; + valaddr_reg:x4; val_offset:108*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 108*FLEN/8, x6, x1, x2) + +inst_80: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x04a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x049 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x44a; op2val:0x8049; + valaddr_reg:x4; val_offset:110*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 110*FLEN/8, x6, x1, x2) + +inst_81: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x045 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x043 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x445; op2val:0x8043; + valaddr_reg:x4; val_offset:112*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 112*FLEN/8, x6, x1, x2) + +inst_82: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x058 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x054 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x458; op2val:0x8054; + valaddr_reg:x4; val_offset:114*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 114*FLEN/8, x6, x1, x2) + +inst_83: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x004 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x004 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x404; op2val:0x4; + valaddr_reg:x4; val_offset:116*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 116*FLEN/8, x6, x1, x2) + +inst_84: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x052 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x042 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x452; op2val:0x8042; + valaddr_reg:x4; val_offset:118*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 118*FLEN/8, x6, x1, x2) + +inst_85: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x04e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x02e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x44e; op2val:0x802e; + valaddr_reg:x4; val_offset:120*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 120*FLEN/8, x6, x1, x2) + +inst_86: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x010 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x030 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x410; op2val:0x30; + valaddr_reg:x4; val_offset:122*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 122*FLEN/8, x6, x1, x2) + +inst_87: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x00c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x074 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x40c; op2val:0x74; + valaddr_reg:x4; val_offset:124*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 124*FLEN/8, x6, x1, x2) + +inst_88: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x00f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x40f; op2val:0xf1; + valaddr_reg:x4; val_offset:126*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 126*FLEN/8, x6, x1, x2) + +inst_89: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x04e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1b2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x44e; op2val:0x1b2; + valaddr_reg:x4; val_offset:128*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 128*FLEN/8, x6, x1, x2) + +inst_90: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x019 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x00d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x419; op2val:0x880d; + valaddr_reg:x4; val_offset:130*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 130*FLEN/8, x6, x1, x2) + +inst_91: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x05c and fs2 == 1 and fe2 == 0x02 and fm2 == 0x02f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x45c; op2val:0x882f; + valaddr_reg:x4; val_offset:132*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 132*FLEN/8, x6, x1, x2) + +inst_92: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x03e and fs2 == 1 and fe2 == 0x02 and fm2 == 0x021 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x43e; op2val:0x8821; + valaddr_reg:x4; val_offset:134*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 134*FLEN/8, x6, x1, x2) + +inst_93: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x05e and fs2 == 1 and fe2 == 0x02 and fm2 == 0x033 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x45e; op2val:0x8833; + valaddr_reg:x4; val_offset:136*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 136*FLEN/8, x6, x1, x2) + +inst_94: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x057 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x033 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x457; op2val:0x8833; + valaddr_reg:x4; val_offset:138*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 138*FLEN/8, x6, x1, x2) + +inst_95: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x046 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x033 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x446; op2val:0x8833; + valaddr_reg:x4; val_offset:140*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 140*FLEN/8, x6, x1, x2) + +inst_96: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x050 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x048 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x450; op2val:0x8848; + valaddr_reg:x4; val_offset:142*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 142*FLEN/8, x6, x1, x2) + +inst_97: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x022 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x051 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x422; op2val:0x8851; + valaddr_reg:x4; val_offset:144*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 144*FLEN/8, x6, x1, x2) + +inst_98: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x01d and fs2 == 1 and fe2 == 0x02 and fm2 == 0x08e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x41d; op2val:0x888e; + valaddr_reg:x4; val_offset:146*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 146*FLEN/8, x6, x1, x2) + +inst_99: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x053 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x129 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x453; op2val:0x8929; + valaddr_reg:x4; val_offset:148*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 148*FLEN/8, x6, x1, x2) + +inst_100: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02d and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3a2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x782d; op2val:0x77a2; + valaddr_reg:x4; val_offset:150*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 150*FLEN/8, x6, x1, x2) + +inst_101: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x018 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3ca and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7818; op2val:0x77ca; + valaddr_reg:x4; val_offset:152*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 152*FLEN/8, x6, x1, x2) + +inst_102: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x041 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x374 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7841; op2val:0x7774; + valaddr_reg:x4; val_offset:154*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 154*FLEN/8, x6, x1, x2) + +inst_103: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x006 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3e2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7806; op2val:0x77e2; + valaddr_reg:x4; val_offset:156*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 156*FLEN/8, x6, x1, x2) + +inst_104: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00d and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3c4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x780d; op2val:0x77c4; + valaddr_reg:x4; val_offset:158*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 158*FLEN/8, x6, x1, x2) + +inst_105: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x033 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x358 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7833; op2val:0x7758; + valaddr_reg:x4; val_offset:160*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 160*FLEN/8, x6, x1, x2) + +inst_106: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x022 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x33a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7822; op2val:0x773a; + valaddr_reg:x4; val_offset:162*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 162*FLEN/8, x6, x1, x2) + +inst_107: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x05e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x242 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x785e; op2val:0x7642; + valaddr_reg:x4; val_offset:164*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 164*FLEN/8, x6, x1, x2) + +inst_108: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x049 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x16c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7849; op2val:0x756c; + valaddr_reg:x4; val_offset:166*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 166*FLEN/8, x6, x1, x2) + +inst_109: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x05a and fs2 == 0 and fe2 == 0x1c and fm2 == 0x294 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x785a; op2val:0x7294; + valaddr_reg:x4; val_offset:168*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 168*FLEN/8, x6, x1, x2) + +inst_110: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x01b and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x781b; op2val:0xfc00; + valaddr_reg:x4; val_offset:170*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 170*FLEN/8, x6, x1, x2) + +inst_111: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x008 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7808; op2val:0xfc00; + valaddr_reg:x4; val_offset:172*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 172*FLEN/8, x6, x1, x2) + +inst_112: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x015 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7815; op2val:0xfc00; + valaddr_reg:x4; val_offset:174*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 174*FLEN/8, x6, x1, x2) + +inst_113: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02c and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x782c; op2val:0xfc00; + valaddr_reg:x4; val_offset:176*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 176*FLEN/8, x6, x1, x2) + +inst_114: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x021 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7821; op2val:0xfc00; + valaddr_reg:x4; val_offset:178*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 178*FLEN/8, x6, x1, x2) + +inst_115: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04d and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x784d; op2val:0xfc00; + valaddr_reg:x4; val_offset:180*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 180*FLEN/8, x6, x1, x2) + +inst_116: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x056 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7856; op2val:0xfc00; + valaddr_reg:x4; val_offset:182*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 182*FLEN/8, x6, x1, x2) + +inst_117: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7802; op2val:0xfc00; + valaddr_reg:x4; val_offset:184*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 184*FLEN/8, x6, x1, x2) + +inst_118: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x058 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7858; op2val:0xfc00; + valaddr_reg:x4; val_offset:186*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 186*FLEN/8, x6, x1, x2) + +inst_119: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x049 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7849; op2val:0xfc00; + valaddr_reg:x4; val_offset:188*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 188*FLEN/8, x6, x1, x2) + +inst_120: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x032 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x030 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x32; op2val:0x8030; + valaddr_reg:x4; val_offset:190*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 190*FLEN/8, x6, x1, x2) + +inst_121: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x036 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x034 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x36; op2val:0x8034; + valaddr_reg:x4; val_offset:192*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 192*FLEN/8, x6, x1, x2) + +inst_122: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x022 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x01e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x22; op2val:0x801e; + valaddr_reg:x4; val_offset:194*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 194*FLEN/8, x6, x1, x2) + +inst_123: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x037 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3f; op2val:0x8037; + valaddr_reg:x4; val_offset:196*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 196*FLEN/8, x6, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(50,32,FLEN) +NAN_BOXED(50,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32820,16,FLEN) +NAN_BOXED(34,32,FLEN) +NAN_BOXED(34,16,FLEN) +NAN_BOXED(63,32,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(39,32,FLEN) +NAN_BOXED(32791,16,FLEN) +NAN_BOXED(46,32,FLEN) +NAN_BOXED(32782,16,FLEN) +NAN_BOXED(28,32,FLEN) +NAN_BOXED(36,32,FLEN) +NAN_BOXED(18,32,FLEN) +NAN_BOXED(110,32,FLEN) +NAN_BOXED(18,32,FLEN) +NAN_BOXED(238,32,FLEN) +NAN_BOXED(13,32,FLEN) +NAN_BOXED(499,32,FLEN) +NAN_BOXED(33,32,FLEN) +NAN_BOXED(32802,16,FLEN) +NAN_BOXED(91,32,FLEN) +NAN_BOXED(32861,16,FLEN) +NAN_BOXED(19,32,FLEN) +NAN_BOXED(32791,16,FLEN) +test_dataset_1: +NAN_BOXED(13,32,FLEN) +NAN_BOXED(32789,16,FLEN) +NAN_BOXED(10,32,FLEN) +NAN_BOXED(32794,16,FLEN) +NAN_BOXED(43,32,FLEN) +NAN_BOXED(32843,16,FLEN) +NAN_BOXED(72,32,FLEN) +NAN_BOXED(32904,16,FLEN) +NAN_BOXED(46,32,FLEN) +NAN_BOXED(32942,16,FLEN) +NAN_BOXED(41,32,FLEN) +NAN_BOXED(33065,16,FLEN) +NAN_BOXED(82,32,FLEN) +NAN_BOXED(33362,16,FLEN) +NAN_BOXED(15431,32,FLEN) +NAN_BOXED(44128,16,FLEN) +NAN_BOXED(15417,32,FLEN) +NAN_BOXED(43744,16,FLEN) +NAN_BOXED(15394,32,FLEN) +NAN_BOXED(42880,16,FLEN) +NAN_BOXED(15431,32,FLEN) +NAN_BOXED(44000,16,FLEN) +NAN_BOXED(15372,32,FLEN) +NAN_BOXED(7168,32,FLEN) +test_dataset_2: +NAN_BOXED(15412,16,FLEN) +NAN_BOXED(42240,16,FLEN) +NAN_BOXED(15446,16,FLEN) +NAN_BOXED(42368,16,FLEN) +NAN_BOXED(15361,16,FLEN) +NAN_BOXED(12272,16,FLEN) +NAN_BOXED(15424,16,FLEN) +NAN_BOXED(12800,16,FLEN) +NAN_BOXED(15392,16,FLEN) +NAN_BOXED(14208,16,FLEN) +NAN_BOXED(15402,16,FLEN) +NAN_BOXED(49173,16,FLEN) +NAN_BOXED(15369,16,FLEN) +NAN_BOXED(49157,16,FLEN) +NAN_BOXED(15433,16,FLEN) +NAN_BOXED(49190,16,FLEN) +NAN_BOXED(15391,16,FLEN) +NAN_BOXED(49171,16,FLEN) +NAN_BOXED(15430,16,FLEN) +NAN_BOXED(49195,16,FLEN) +NAN_BOXED(15372,16,FLEN) +NAN_BOXED(49174,16,FLEN) +NAN_BOXED(15401,16,FLEN) +NAN_BOXED(49204,16,FLEN) +NAN_BOXED(15423,16,FLEN) +NAN_BOXED(49247,16,FLEN) +NAN_BOXED(15399,16,FLEN) +NAN_BOXED(49299,16,FLEN) +NAN_BOXED(15398,16,FLEN) +NAN_BOXED(49427,16,FLEN) +NAN_BOXED(16,16,FLEN) +NAN_BOXED(32782,16,FLEN) +NAN_BOXED(43,16,FLEN) +NAN_BOXED(32808,16,FLEN) +NAN_BOXED(27,16,FLEN) +NAN_BOXED(32790,16,FLEN) +NAN_BOXED(71,16,FLEN) +NAN_BOXED(32830,16,FLEN) +NAN_BOXED(37,16,FLEN) +NAN_BOXED(32788,16,FLEN) +NAN_BOXED(12,16,FLEN) +NAN_BOXED(21,16,FLEN) +NAN_BOXED(50,16,FLEN) +NAN_BOXED(15,16,FLEN) +NAN_BOXED(74,16,FLEN) +NAN_BOXED(55,16,FLEN) +NAN_BOXED(38,16,FLEN) +NAN_BOXED(219,16,FLEN) +NAN_BOXED(25,16,FLEN) +NAN_BOXED(488,16,FLEN) +NAN_BOXED(5,16,FLEN) +NAN_BOXED(32774,16,FLEN) +NAN_BOXED(85,16,FLEN) +NAN_BOXED(32856,16,FLEN) +NAN_BOXED(61,16,FLEN) +NAN_BOXED(32834,16,FLEN) +NAN_BOXED(12,16,FLEN) +NAN_BOXED(32789,16,FLEN) +NAN_BOXED(97,16,FLEN) +NAN_BOXED(32882,16,FLEN) +NAN_BOXED(20,16,FLEN) +NAN_BOXED(32821,16,FLEN) +NAN_BOXED(11,16,FLEN) +NAN_BOXED(32844,16,FLEN) +NAN_BOXED(70,16,FLEN) +NAN_BOXED(32967,16,FLEN) +NAN_BOXED(51,16,FLEN) +NAN_BOXED(33076,16,FLEN) +NAN_BOXED(68,16,FLEN) +NAN_BOXED(33349,16,FLEN) +NAN_BOXED(67,16,FLEN) +NAN_BOXED(955,16,FLEN) +NAN_BOXED(28,16,FLEN) +NAN_BOXED(993,16,FLEN) +NAN_BOXED(76,16,FLEN) +NAN_BOXED(943,16,FLEN) +NAN_BOXED(75,16,FLEN) +NAN_BOXED(940,16,FLEN) +NAN_BOXED(58,16,FLEN) +NAN_BOXED(949,16,FLEN) +NAN_BOXED(85,16,FLEN) +NAN_BOXED(906,16,FLEN) +NAN_BOXED(90,16,FLEN) +NAN_BOXED(869,16,FLEN) +NAN_BOXED(11,16,FLEN) +NAN_BOXED(884,16,FLEN) +NAN_BOXED(79,16,FLEN) +NAN_BOXED(688,16,FLEN) +NAN_BOXED(63,16,FLEN) +NAN_BOXED(448,16,FLEN) +NAN_BOXED(81,16,FLEN) +NAN_BOXED(33871,16,FLEN) +NAN_BOXED(25,16,FLEN) +NAN_BOXED(33814,16,FLEN) +NAN_BOXED(3,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(35,16,FLEN) +NAN_BOXED(33818,16,FLEN) +NAN_BOXED(91,16,FLEN) +NAN_BOXED(33866,16,FLEN) +NAN_BOXED(48,16,FLEN) +NAN_BOXED(33807,16,FLEN) +NAN_BOXED(43,16,FLEN) +NAN_BOXED(33770,16,FLEN) +NAN_BOXED(8,16,FLEN) +NAN_BOXED(33671,16,FLEN) +NAN_BOXED(19,16,FLEN) +NAN_BOXED(33554,16,FLEN) +NAN_BOXED(29,16,FLEN) +NAN_BOXED(33308,16,FLEN) +NAN_BOXED(1098,16,FLEN) +NAN_BOXED(32841,16,FLEN) +NAN_BOXED(1093,16,FLEN) +NAN_BOXED(32835,16,FLEN) +NAN_BOXED(1112,16,FLEN) +NAN_BOXED(32852,16,FLEN) +NAN_BOXED(1028,16,FLEN) +NAN_BOXED(4,16,FLEN) +NAN_BOXED(1106,16,FLEN) +NAN_BOXED(32834,16,FLEN) +NAN_BOXED(1102,16,FLEN) +NAN_BOXED(32814,16,FLEN) +NAN_BOXED(1040,16,FLEN) +NAN_BOXED(48,16,FLEN) +NAN_BOXED(1036,16,FLEN) +NAN_BOXED(116,16,FLEN) +NAN_BOXED(1039,16,FLEN) +NAN_BOXED(241,16,FLEN) +NAN_BOXED(1102,16,FLEN) +NAN_BOXED(434,16,FLEN) +NAN_BOXED(1049,16,FLEN) +NAN_BOXED(34829,16,FLEN) +NAN_BOXED(1116,16,FLEN) +NAN_BOXED(34863,16,FLEN) +NAN_BOXED(1086,16,FLEN) +NAN_BOXED(34849,16,FLEN) +NAN_BOXED(1118,16,FLEN) +NAN_BOXED(34867,16,FLEN) +NAN_BOXED(1111,16,FLEN) +NAN_BOXED(34867,16,FLEN) +NAN_BOXED(1094,16,FLEN) +NAN_BOXED(34867,16,FLEN) +NAN_BOXED(1104,16,FLEN) +NAN_BOXED(34888,16,FLEN) +NAN_BOXED(1058,16,FLEN) +NAN_BOXED(34897,16,FLEN) +NAN_BOXED(1053,16,FLEN) +NAN_BOXED(34958,16,FLEN) +NAN_BOXED(1107,16,FLEN) +NAN_BOXED(35113,16,FLEN) +NAN_BOXED(30765,16,FLEN) +NAN_BOXED(30626,16,FLEN) +NAN_BOXED(30744,16,FLEN) +NAN_BOXED(30666,16,FLEN) +NAN_BOXED(30785,16,FLEN) +NAN_BOXED(30580,16,FLEN) +NAN_BOXED(30726,16,FLEN) +NAN_BOXED(30690,16,FLEN) +NAN_BOXED(30733,16,FLEN) +NAN_BOXED(30660,16,FLEN) +NAN_BOXED(30771,16,FLEN) +NAN_BOXED(30552,16,FLEN) +NAN_BOXED(30754,16,FLEN) +NAN_BOXED(30522,16,FLEN) +NAN_BOXED(30814,16,FLEN) +NAN_BOXED(30274,16,FLEN) +NAN_BOXED(30793,16,FLEN) +NAN_BOXED(30060,16,FLEN) +NAN_BOXED(30810,16,FLEN) +NAN_BOXED(29332,16,FLEN) +NAN_BOXED(30747,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(30728,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(30741,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(30764,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(30753,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(30797,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(30806,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(30722,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(30808,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(30793,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(50,16,FLEN) +NAN_BOXED(32816,16,FLEN) +NAN_BOXED(54,16,FLEN) +NAN_BOXED(32820,16,FLEN) +NAN_BOXED(34,16,FLEN) +NAN_BOXED(32798,16,FLEN) +NAN_BOXED(63,16,FLEN) +NAN_BOXED(32823,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x8_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x8_1: + .fill 30*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x13_0: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_0: + .fill 190*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fadd_b3-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fadd_b3-01.S new file mode 100644 index 000000000..dc78d8e08 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fadd_b3-01.S @@ -0,0 +1,10989 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 05:45:15 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fadd.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fadd.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fadd_b3 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fadd_b3) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x12,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rs2 != rd, rs1==x9, rs2==x9, rd==x14,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x9; op2:x9; dest:x14; op1val:0x7ac0; op2val:0x7ac0; + valaddr_reg:x12; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fadd.h, x14, x9, x9, dyn, 0, 0, x12, 0*FLEN/8, x13, x1, x3) + +inst_1: +// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==x8, rs2==x28, rd==x2,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2c0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x8; op2:x28; dest:x2; op1val:0x7ac0; op2val:0xfac0; + valaddr_reg:x12; val_offset:2*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fadd.h, x2, x8, x28, dyn, 32, 0, x12, 2*FLEN/8, x13, x1, x3) + +inst_2: +// rs1 == rs2 == rd, rs1==x7, rs2==x7, rd==x7,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2c0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x7; op2:x7; dest:x7; op1val:0x7ac0; op2val:0x7ac0; + valaddr_reg:x12; val_offset:4*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fadd.h, x7, x7, x7, dyn, 64, 0, x12, 4*FLEN/8, x13, x1, x3) + +inst_3: +// rs2 == rd != rs1, rs1==x22, rs2==x27, rd==x27,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2c0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x22; op2:x27; dest:x27; op1val:0x7ac0; op2val:0xfac0; + valaddr_reg:x12; val_offset:6*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fadd.h, x27, x22, x27, dyn, 96, 0, x12, 6*FLEN/8, x13, x1, x3) + +inst_4: +// rs1 == rd != rs2, rs1==x29, rs2==x21, rd==x29,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2c0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x29; op2:x21; dest:x29; op1val:0x7ac0; op2val:0xfac0; + valaddr_reg:x12; val_offset:8*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fadd.h, x29, x29, x21, dyn, 128, 0, x12, 8*FLEN/8, x13, x1, x3) + +inst_5: +// rs1==x15, rs2==x14, rd==x23,fs1 == 0 and fe1 == 0x1d and fm1 == 0x2b9 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2b9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x15; op2:x14; dest:x23; op1val:0x76b9; op2val:0xf6b9; + valaddr_reg:x12; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fadd.h, x23, x15, x14, dyn, 0, 0, x12, 10*FLEN/8, x13, x1, x3) + +inst_6: +// rs1==x24, rs2==x17, rd==x16,fs1 == 0 and fe1 == 0x1d and fm1 == 0x2b9 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2b9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x24; op2:x17; dest:x16; op1val:0x76b9; op2val:0xf6b9; + valaddr_reg:x12; val_offset:12*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fadd.h, x16, x24, x17, dyn, 32, 0, x12, 12*FLEN/8, x13, x1, x3) + +inst_7: +// rs1==x11, rs2==x6, rd==x22,fs1 == 0 and fe1 == 0x1d and fm1 == 0x2b9 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2b9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x11; op2:x6; dest:x22; op1val:0x76b9; op2val:0xf6b9; + valaddr_reg:x12; val_offset:14*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fadd.h, x22, x11, x6, dyn, 64, 0, x12, 14*FLEN/8, x13, x1, x3) + +inst_8: +// rs1==x4, rs2==x10, rd==x25,fs1 == 0 and fe1 == 0x1d and fm1 == 0x2b9 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2b9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x4; op2:x10; dest:x25; op1val:0x76b9; op2val:0xf6b9; + valaddr_reg:x12; val_offset:16*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fadd.h, x25, x4, x10, dyn, 96, 0, x12, 16*FLEN/8, x13, x1, x3) + +inst_9: +// rs1==x30, rs2==x25, rd==x24,fs1 == 0 and fe1 == 0x1d and fm1 == 0x2b9 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2b9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x25; dest:x24; op1val:0x76b9; op2val:0xf6b9; + valaddr_reg:x12; val_offset:18*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fadd.h, x24, x30, x25, dyn, 128, 0, x12, 18*FLEN/8, x13, x1, x3) + +inst_10: +// rs1==x14, rs2==x24, rd==x20,fs1 == 0 and fe1 == 0x1e and fm1 == 0x016 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x016 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x14; op2:x24; dest:x20; op1val:0x7816; op2val:0xf816; + valaddr_reg:x12; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fadd.h, x20, x14, x24, dyn, 0, 0, x12, 20*FLEN/8, x13, x1, x3) + +inst_11: +// rs1==x0, rs2==x16, rd==x30,fs1 == 0 and fe1 == 0x1e and fm1 == 0x016 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x016 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x0; op2:x16; dest:x30; op1val:0x0; op2val:0xf816; + valaddr_reg:x12; val_offset:22*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fadd.h, x30, x0, x16, dyn, 32, 0, x12, 22*FLEN/8, x13, x1, x3) + +inst_12: +// rs1==x20, rs2==x26, rd==x5,fs1 == 0 and fe1 == 0x1e and fm1 == 0x016 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x016 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x20; op2:x26; dest:x5; op1val:0x7816; op2val:0xf816; + valaddr_reg:x12; val_offset:24*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fadd.h, x5, x20, x26, dyn, 64, 0, x12, 24*FLEN/8, x13, x1, x3) +RVTEST_VALBASEUPD(x12,test_dataset_1) + +inst_13: +// rs1==x16, rs2==x23, rd==x4,fs1 == 0 and fe1 == 0x1e and fm1 == 0x016 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x016 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x16; op2:x23; dest:x4; op1val:0x7816; op2val:0xf816; + valaddr_reg:x12; val_offset:0*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fadd.h, x4, x16, x23, dyn, 96, 0, x12, 0*FLEN/8, x15, x1, x3) + +inst_14: +// rs1==x10, rs2==x20, rd==x11,fs1 == 0 and fe1 == 0x1e and fm1 == 0x016 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x016 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x10; op2:x20; dest:x11; op1val:0x7816; op2val:0xf816; + valaddr_reg:x12; val_offset:2*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fadd.h, x11, x10, x20, dyn, 128, 0, x12, 2*FLEN/8, x15, x1, x3) + +inst_15: +// rs1==x17, rs2==x19, rd==x26,fs1 == 0 and fe1 == 0x1e and fm1 == 0x244 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x244 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x17; op2:x19; dest:x26; op1val:0x7a44; op2val:0xfa44; + valaddr_reg:x12; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fadd.h, x26, x17, x19, dyn, 0, 0, x12, 4*FLEN/8, x15, x1, x3) + +inst_16: +// rs1==x23, rs2==x13, rd==x18,fs1 == 0 and fe1 == 0x1e and fm1 == 0x244 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x244 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x23; op2:x13; dest:x18; op1val:0x7a44; op2val:0xfa44; + valaddr_reg:x12; val_offset:6*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x14 +*/ +TEST_FPRR_OP(fadd.h, x18, x23, x13, dyn, 32, 0, x12, 6*FLEN/8, x15, x1, x14) +RVTEST_SIGBASE(x7,signature_x7_0) + +inst_17: +// rs1==x21, rs2==x18, rd==x6,fs1 == 0 and fe1 == 0x1e and fm1 == 0x244 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x244 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x21; op2:x18; dest:x6; op1val:0x7a44; op2val:0xfa44; + valaddr_reg:x12; val_offset:8*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x14 +*/ +TEST_FPRR_OP(fadd.h, x6, x21, x18, dyn, 64, 0, x12, 8*FLEN/8, x15, x7, x14) + +inst_18: +// rs1==x2, rs2==x31, rd==x19,fs1 == 0 and fe1 == 0x1e and fm1 == 0x244 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x244 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x2; op2:x31; dest:x19; op1val:0x7a44; op2val:0xfa44; + valaddr_reg:x12; val_offset:10*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x14 +*/ +TEST_FPRR_OP(fadd.h, x19, x2, x31, dyn, 96, 0, x12, 10*FLEN/8, x15, x7, x14) + +inst_19: +// rs1==x6, rs2==x4, rd==x9,fs1 == 0 and fe1 == 0x1e and fm1 == 0x244 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x244 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x6; op2:x4; dest:x9; op1val:0x7a44; op2val:0xfa44; + valaddr_reg:x12; val_offset:12*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x14 +*/ +TEST_FPRR_OP(fadd.h, x9, x6, x4, dyn, 128, 0, x12, 12*FLEN/8, x15, x7, x14) + +inst_20: +// rs1==x27, rs2==x5, rd==x13,fs1 == 0 and fe1 == 0x1d and fm1 == 0x39f and fs2 == 1 and fe2 == 0x1d and fm2 == 0x39f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x27; op2:x5; dest:x13; op1val:0x779f; op2val:0xf79f; + valaddr_reg:x12; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x14 +*/ +TEST_FPRR_OP(fadd.h, x13, x27, x5, dyn, 0, 0, x12, 14*FLEN/8, x15, x7, x14) + +inst_21: +// rs1==x18, rs2==x8, rd==x17,fs1 == 0 and fe1 == 0x1d and fm1 == 0x39f and fs2 == 1 and fe2 == 0x1d and fm2 == 0x39f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x18; op2:x8; dest:x17; op1val:0x779f; op2val:0xf79f; + valaddr_reg:x12; val_offset:16*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x14 +*/ +TEST_FPRR_OP(fadd.h, x17, x18, x8, dyn, 32, 0, x12, 16*FLEN/8, x15, x7, x14) + +inst_22: +// rs1==x26, rs2==x29, rd==x28,fs1 == 0 and fe1 == 0x1d and fm1 == 0x39f and fs2 == 1 and fe2 == 0x1d and fm2 == 0x39f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x26; op2:x29; dest:x28; op1val:0x779f; op2val:0xf79f; + valaddr_reg:x12; val_offset:18*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x14 +*/ +TEST_FPRR_OP(fadd.h, x28, x26, x29, dyn, 64, 0, x12, 18*FLEN/8, x15, x7, x14) +RVTEST_VALBASEUPD(x4,test_dataset_2) + +inst_23: +// rs1==x12, rs2==x22, rd==x31,fs1 == 0 and fe1 == 0x1d and fm1 == 0x39f and fs2 == 1 and fe2 == 0x1d and fm2 == 0x39f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x12; op2:x22; dest:x31; op1val:0x779f; op2val:0xf79f; + valaddr_reg:x4; val_offset:0*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x14 +*/ +TEST_FPRR_OP(fadd.h, x31, x12, x22, dyn, 96, 0, x4, 0*FLEN/8, x6, x7, x14) + +inst_24: +// rs1==x5, rs2==x3, rd==x0,fs1 == 0 and fe1 == 0x1d and fm1 == 0x39f and fs2 == 1 and fe2 == 0x1d and fm2 == 0x39f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x5; op2:x3; dest:x0; op1val:0x779f; op2val:0xf79f; + valaddr_reg:x4; val_offset:2*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x14 +*/ +TEST_FPRR_OP(fadd.h, x0, x5, x3, dyn, 128, 0, x4, 2*FLEN/8, x6, x7, x14) + +inst_25: +// rs1==x13, rs2==x1, rd==x15,fs1 == 0 and fe1 == 0x1e and fm1 == 0x342 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x342 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x13; op2:x1; dest:x15; op1val:0x7b42; op2val:0xfb42; + valaddr_reg:x4; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x14 +*/ +TEST_FPRR_OP(fadd.h, x15, x13, x1, dyn, 0, 0, x4, 4*FLEN/8, x6, x7, x14) + +inst_26: +// rs1==x31, rs2==x11, rd==x12,fs1 == 0 and fe1 == 0x1e and fm1 == 0x342 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x342 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x31; op2:x11; dest:x12; op1val:0x7b42; op2val:0xfb42; + valaddr_reg:x4; val_offset:6*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x14 +*/ +TEST_FPRR_OP(fadd.h, x12, x31, x11, dyn, 32, 0, x4, 6*FLEN/8, x6, x7, x14) + +inst_27: +// rs1==x28, rs2==x2, rd==x1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x342 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x342 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x28; op2:x2; dest:x1; op1val:0x7b42; op2val:0xfb42; + valaddr_reg:x4; val_offset:8*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x14 +*/ +TEST_FPRR_OP(fadd.h, x1, x28, x2, dyn, 64, 0, x4, 8*FLEN/8, x6, x7, x14) + +inst_28: +// rs1==x3, rs2==x0, rd==x21,fs1 == 0 and fe1 == 0x1e and fm1 == 0x342 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x342 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x3; op2:x0; dest:x21; op1val:0x7b42; op2val:0x0; + valaddr_reg:x4; val_offset:10*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x14 +*/ +TEST_FPRR_OP(fadd.h, x21, x3, x0, dyn, 96, 0, x4, 10*FLEN/8, x6, x7, x14) + +inst_29: +// rs1==x1, rs2==x15, rd==x10,fs1 == 0 and fe1 == 0x1e and fm1 == 0x342 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x342 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x1; op2:x15; dest:x10; op1val:0x7b42; op2val:0xfb42; + valaddr_reg:x4; val_offset:12*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x14 +*/ +TEST_FPRR_OP(fadd.h, x10, x1, x15, dyn, 128, 0, x4, 12*FLEN/8, x6, x7, x14) + +inst_30: +// rs1==x25, rs2==x12, rd==x8,fs1 == 0 and fe1 == 0x1d and fm1 == 0x081 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x081 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x25; op2:x12; dest:x8; op1val:0x7481; op2val:0xf481; + valaddr_reg:x4; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x14 +*/ +TEST_FPRR_OP(fadd.h, x8, x25, x12, dyn, 0, 0, x4, 14*FLEN/8, x6, x7, x14) + +inst_31: +// rs1==x19, rs2==x30, rd==x3,fs1 == 0 and fe1 == 0x1d and fm1 == 0x081 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x081 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x19; op2:x30; dest:x3; op1val:0x7481; op2val:0xf481; + valaddr_reg:x4; val_offset:16*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x3, x19, x30, dyn, 32, 0, x4, 16*FLEN/8, x6, x7, x1) + +inst_32: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x081 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x081 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7481; op2val:0xf481; + valaddr_reg:x4; val_offset:18*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 18*FLEN/8, x6, x7, x1) + +inst_33: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x081 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x081 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7481; op2val:0xf481; + valaddr_reg:x4; val_offset:20*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 20*FLEN/8, x6, x7, x1) + +inst_34: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x081 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x081 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7481; op2val:0xf481; + valaddr_reg:x4; val_offset:22*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 22*FLEN/8, x6, x7, x1) + +inst_35: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0f1 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0f1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78f1; op2val:0xf8f1; + valaddr_reg:x4; val_offset:24*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 24*FLEN/8, x6, x7, x1) + +inst_36: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0f1 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0f1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78f1; op2val:0xf8f1; + valaddr_reg:x4; val_offset:26*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 26*FLEN/8, x6, x7, x1) + +inst_37: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0f1 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0f1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78f1; op2val:0xf8f1; + valaddr_reg:x4; val_offset:28*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 28*FLEN/8, x6, x7, x1) + +inst_38: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0f1 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0f1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78f1; op2val:0xf8f1; + valaddr_reg:x4; val_offset:30*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 30*FLEN/8, x6, x7, x1) + +inst_39: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0f1 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0f1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78f1; op2val:0xf8f1; + valaddr_reg:x4; val_offset:32*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 32*FLEN/8, x6, x7, x1) + +inst_40: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x346 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x346 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b46; op2val:0xfb46; + valaddr_reg:x4; val_offset:34*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 34*FLEN/8, x6, x7, x1) + +inst_41: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x346 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x346 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b46; op2val:0xfb46; + valaddr_reg:x4; val_offset:36*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 36*FLEN/8, x6, x7, x1) + +inst_42: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x346 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x346 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b46; op2val:0xfb46; + valaddr_reg:x4; val_offset:38*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 38*FLEN/8, x6, x7, x1) + +inst_43: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x346 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x346 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b46; op2val:0xfb46; + valaddr_reg:x4; val_offset:40*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 40*FLEN/8, x6, x7, x1) + +inst_44: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x346 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x346 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b46; op2val:0xfb46; + valaddr_reg:x4; val_offset:42*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 42*FLEN/8, x6, x7, x1) + +inst_45: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x27a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x27a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a7a; op2val:0xfa7a; + valaddr_reg:x4; val_offset:44*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 44*FLEN/8, x6, x7, x1) + +inst_46: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x27a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x27a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a7a; op2val:0xfa7a; + valaddr_reg:x4; val_offset:46*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 46*FLEN/8, x6, x7, x1) + +inst_47: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x27a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x27a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a7a; op2val:0xfa7a; + valaddr_reg:x4; val_offset:48*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 48*FLEN/8, x6, x7, x1) + +inst_48: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x27a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x27a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a7a; op2val:0xfa7a; + valaddr_reg:x4; val_offset:50*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 50*FLEN/8, x6, x7, x1) + +inst_49: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x27a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x27a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a7a; op2val:0xfa7a; + valaddr_reg:x4; val_offset:52*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 52*FLEN/8, x6, x7, x1) + +inst_50: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f5 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x0f5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x74f5; op2val:0xf4f5; + valaddr_reg:x4; val_offset:54*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 54*FLEN/8, x6, x7, x1) + +inst_51: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f5 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x0f5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x74f5; op2val:0xf4f5; + valaddr_reg:x4; val_offset:56*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 56*FLEN/8, x6, x7, x1) + +inst_52: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f5 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x0f5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x74f5; op2val:0xf4f5; + valaddr_reg:x4; val_offset:58*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 58*FLEN/8, x6, x7, x1) + +inst_53: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f5 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x0f5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x74f5; op2val:0xf4f5; + valaddr_reg:x4; val_offset:60*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 60*FLEN/8, x6, x7, x1) + +inst_54: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f5 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x0f5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x74f5; op2val:0xf4f5; + valaddr_reg:x4; val_offset:62*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 62*FLEN/8, x6, x7, x1) + +inst_55: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x32f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b2f; op2val:0xfb2f; + valaddr_reg:x4; val_offset:64*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 64*FLEN/8, x6, x7, x1) + +inst_56: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x32f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b2f; op2val:0xfb2f; + valaddr_reg:x4; val_offset:66*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 66*FLEN/8, x6, x7, x1) + +inst_57: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x32f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b2f; op2val:0xfb2f; + valaddr_reg:x4; val_offset:68*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 68*FLEN/8, x6, x7, x1) + +inst_58: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x32f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b2f; op2val:0xfb2f; + valaddr_reg:x4; val_offset:70*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 70*FLEN/8, x6, x7, x1) + +inst_59: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x32f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b2f; op2val:0xfb2f; + valaddr_reg:x4; val_offset:72*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 72*FLEN/8, x6, x7, x1) + +inst_60: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x38c and fs2 == 1 and fe2 == 0x1d and fm2 == 0x38c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x778c; op2val:0xf78c; + valaddr_reg:x4; val_offset:74*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 74*FLEN/8, x6, x7, x1) + +inst_61: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x38c and fs2 == 1 and fe2 == 0x1d and fm2 == 0x38c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x778c; op2val:0xf78c; + valaddr_reg:x4; val_offset:76*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 76*FLEN/8, x6, x7, x1) + +inst_62: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x38c and fs2 == 1 and fe2 == 0x1d and fm2 == 0x38c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x778c; op2val:0xf78c; + valaddr_reg:x4; val_offset:78*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 78*FLEN/8, x6, x7, x1) + +inst_63: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x38c and fs2 == 1 and fe2 == 0x1d and fm2 == 0x38c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x778c; op2val:0xf78c; + valaddr_reg:x4; val_offset:80*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 80*FLEN/8, x6, x7, x1) + +inst_64: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x38c and fs2 == 1 and fe2 == 0x1d and fm2 == 0x38c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x778c; op2val:0xf78c; + valaddr_reg:x4; val_offset:82*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 82*FLEN/8, x6, x7, x1) + +inst_65: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2f1 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2f1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x76f1; op2val:0xf6f1; + valaddr_reg:x4; val_offset:84*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 84*FLEN/8, x6, x7, x1) + +inst_66: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2f1 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2f1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x76f1; op2val:0xf6f1; + valaddr_reg:x4; val_offset:86*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 86*FLEN/8, x6, x7, x1) + +inst_67: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2f1 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2f1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x76f1; op2val:0xf6f1; + valaddr_reg:x4; val_offset:88*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 88*FLEN/8, x6, x7, x1) + +inst_68: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2f1 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2f1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x76f1; op2val:0xf6f1; + valaddr_reg:x4; val_offset:90*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 90*FLEN/8, x6, x7, x1) + +inst_69: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2f1 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2f1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x76f1; op2val:0xf6f1; + valaddr_reg:x4; val_offset:92*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 92*FLEN/8, x6, x7, x1) + +inst_70: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x34c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x34c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b4c; op2val:0xfb4c; + valaddr_reg:x4; val_offset:94*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 94*FLEN/8, x6, x7, x1) + +inst_71: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x34c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x34c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b4c; op2val:0xfb4c; + valaddr_reg:x4; val_offset:96*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 96*FLEN/8, x6, x7, x1) + +inst_72: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x34c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x34c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b4c; op2val:0xfb4c; + valaddr_reg:x4; val_offset:98*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 98*FLEN/8, x6, x7, x1) + +inst_73: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x34c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x34c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b4c; op2val:0xfb4c; + valaddr_reg:x4; val_offset:100*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 100*FLEN/8, x6, x7, x1) + +inst_74: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x34c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x34c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b4c; op2val:0xfb4c; + valaddr_reg:x4; val_offset:102*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 102*FLEN/8, x6, x7, x1) + +inst_75: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a0 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3a0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77a0; op2val:0xf7a0; + valaddr_reg:x4; val_offset:104*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 104*FLEN/8, x6, x7, x1) + +inst_76: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a0 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3a0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77a0; op2val:0xf7a0; + valaddr_reg:x4; val_offset:106*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 106*FLEN/8, x6, x7, x1) + +inst_77: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a0 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3a0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77a0; op2val:0xf7a0; + valaddr_reg:x4; val_offset:108*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 108*FLEN/8, x6, x7, x1) + +inst_78: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a0 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3a0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77a0; op2val:0xf7a0; + valaddr_reg:x4; val_offset:110*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 110*FLEN/8, x6, x7, x1) + +inst_79: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a0 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3a0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77a0; op2val:0xf7a0; + valaddr_reg:x4; val_offset:112*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 112*FLEN/8, x6, x7, x1) + +inst_80: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x02a and fs2 == 1 and fe2 == 0x1d and fm2 == 0x02a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x742a; op2val:0xf42a; + valaddr_reg:x4; val_offset:114*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 114*FLEN/8, x6, x7, x1) + +inst_81: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x02a and fs2 == 1 and fe2 == 0x1d and fm2 == 0x02a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x742a; op2val:0xf42a; + valaddr_reg:x4; val_offset:116*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 116*FLEN/8, x6, x7, x1) + +inst_82: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x02a and fs2 == 1 and fe2 == 0x1d and fm2 == 0x02a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x742a; op2val:0xf42a; + valaddr_reg:x4; val_offset:118*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 118*FLEN/8, x6, x7, x1) + +inst_83: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x02a and fs2 == 1 and fe2 == 0x1d and fm2 == 0x02a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x742a; op2val:0xf42a; + valaddr_reg:x4; val_offset:120*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 120*FLEN/8, x6, x7, x1) + +inst_84: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x02a and fs2 == 1 and fe2 == 0x1d and fm2 == 0x02a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x742a; op2val:0xf42a; + valaddr_reg:x4; val_offset:122*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 122*FLEN/8, x6, x7, x1) + +inst_85: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x063 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x063 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7863; op2val:0xf863; + valaddr_reg:x4; val_offset:124*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 124*FLEN/8, x6, x7, x1) + +inst_86: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x063 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x063 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7863; op2val:0xf863; + valaddr_reg:x4; val_offset:126*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 126*FLEN/8, x6, x7, x1) + +inst_87: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x063 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x063 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7863; op2val:0xf863; + valaddr_reg:x4; val_offset:128*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 128*FLEN/8, x6, x7, x1) + +inst_88: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x063 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x063 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7863; op2val:0xf863; + valaddr_reg:x4; val_offset:130*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 130*FLEN/8, x6, x7, x1) + +inst_89: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x063 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x063 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7863; op2val:0xf863; + valaddr_reg:x4; val_offset:132*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 132*FLEN/8, x6, x7, x1) + +inst_90: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c1 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1c1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c1; op2val:0xf9c1; + valaddr_reg:x4; val_offset:134*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 134*FLEN/8, x6, x7, x1) + +inst_91: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c1 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1c1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c1; op2val:0xf9c1; + valaddr_reg:x4; val_offset:136*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 136*FLEN/8, x6, x7, x1) + +inst_92: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c1 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1c1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c1; op2val:0xf9c1; + valaddr_reg:x4; val_offset:138*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 138*FLEN/8, x6, x7, x1) + +inst_93: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c1 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1c1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c1; op2val:0xf9c1; + valaddr_reg:x4; val_offset:140*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 140*FLEN/8, x6, x7, x1) + +inst_94: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c1 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1c1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c1; op2val:0xf9c1; + valaddr_reg:x4; val_offset:142*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 142*FLEN/8, x6, x7, x1) + +inst_95: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x298 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x298 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a98; op2val:0xfa98; + valaddr_reg:x4; val_offset:144*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 144*FLEN/8, x6, x7, x1) + +inst_96: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x298 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x298 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a98; op2val:0xfa98; + valaddr_reg:x4; val_offset:146*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 146*FLEN/8, x6, x7, x1) + +inst_97: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x298 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x298 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a98; op2val:0xfa98; + valaddr_reg:x4; val_offset:148*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 148*FLEN/8, x6, x7, x1) + +inst_98: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x298 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x298 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a98; op2val:0xfa98; + valaddr_reg:x4; val_offset:150*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 150*FLEN/8, x6, x7, x1) + +inst_99: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x298 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x298 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a98; op2val:0xfa98; + valaddr_reg:x4; val_offset:152*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 152*FLEN/8, x6, x7, x1) + +inst_100: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x0bd and fs2 == 1 and fe2 == 0x15 and fm2 == 0x0bd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x54bd; op2val:0xd4bd; + valaddr_reg:x4; val_offset:154*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 154*FLEN/8, x6, x7, x1) + +inst_101: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x0bd and fs2 == 1 and fe2 == 0x15 and fm2 == 0x0bd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x54bd; op2val:0xd4bd; + valaddr_reg:x4; val_offset:156*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 156*FLEN/8, x6, x7, x1) + +inst_102: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x0bd and fs2 == 1 and fe2 == 0x15 and fm2 == 0x0bd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x54bd; op2val:0xd4bd; + valaddr_reg:x4; val_offset:158*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 158*FLEN/8, x6, x7, x1) + +inst_103: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x0bd and fs2 == 1 and fe2 == 0x15 and fm2 == 0x0bd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x54bd; op2val:0xd4bd; + valaddr_reg:x4; val_offset:160*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 160*FLEN/8, x6, x7, x1) + +inst_104: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x0bd and fs2 == 1 and fe2 == 0x15 and fm2 == 0x0bd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x54bd; op2val:0xd4bd; + valaddr_reg:x4; val_offset:162*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 162*FLEN/8, x6, x7, x1) + +inst_105: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2ef and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aef; op2val:0xfaef; + valaddr_reg:x4; val_offset:164*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 164*FLEN/8, x6, x7, x1) + +inst_106: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2ef and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aef; op2val:0xfaef; + valaddr_reg:x4; val_offset:166*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 166*FLEN/8, x6, x7, x1) + +inst_107: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2ef and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aef; op2val:0xfaef; + valaddr_reg:x4; val_offset:168*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 168*FLEN/8, x6, x7, x1) + +inst_108: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2ef and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aef; op2val:0xfaef; + valaddr_reg:x4; val_offset:170*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 170*FLEN/8, x6, x7, x1) + +inst_109: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2ef and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aef; op2val:0xfaef; + valaddr_reg:x4; val_offset:172*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 172*FLEN/8, x6, x7, x1) + +inst_110: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x133 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x133 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7533; op2val:0xf533; + valaddr_reg:x4; val_offset:174*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 174*FLEN/8, x6, x7, x1) + +inst_111: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x133 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x133 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7533; op2val:0xf533; + valaddr_reg:x4; val_offset:176*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 176*FLEN/8, x6, x7, x1) + +inst_112: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x133 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x133 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7533; op2val:0xf533; + valaddr_reg:x4; val_offset:178*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 178*FLEN/8, x6, x7, x1) + +inst_113: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x133 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x133 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7533; op2val:0xf533; + valaddr_reg:x4; val_offset:180*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 180*FLEN/8, x6, x7, x1) + +inst_114: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x133 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x133 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7533; op2val:0xf533; + valaddr_reg:x4; val_offset:182*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 182*FLEN/8, x6, x7, x1) + +inst_115: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x21c and fs2 == 1 and fe2 == 0x1c and fm2 == 0x21c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x721c; op2val:0xf21c; + valaddr_reg:x4; val_offset:184*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 184*FLEN/8, x6, x7, x1) + +inst_116: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x21c and fs2 == 1 and fe2 == 0x1c and fm2 == 0x21c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x721c; op2val:0xf21c; + valaddr_reg:x4; val_offset:186*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 186*FLEN/8, x6, x7, x1) + +inst_117: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x21c and fs2 == 1 and fe2 == 0x1c and fm2 == 0x21c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x721c; op2val:0xf21c; + valaddr_reg:x4; val_offset:188*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 188*FLEN/8, x6, x7, x1) + +inst_118: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x21c and fs2 == 1 and fe2 == 0x1c and fm2 == 0x21c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x721c; op2val:0xf21c; + valaddr_reg:x4; val_offset:190*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 190*FLEN/8, x6, x7, x1) + +inst_119: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x21c and fs2 == 1 and fe2 == 0x1c and fm2 == 0x21c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x721c; op2val:0xf21c; + valaddr_reg:x4; val_offset:192*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 192*FLEN/8, x6, x7, x1) + +inst_120: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3a1 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3a1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x73a1; op2val:0xf3a1; + valaddr_reg:x4; val_offset:194*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 194*FLEN/8, x6, x7, x1) + +inst_121: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3a1 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3a1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x73a1; op2val:0xf3a1; + valaddr_reg:x4; val_offset:196*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 196*FLEN/8, x6, x7, x1) + +inst_122: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3a1 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3a1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x73a1; op2val:0xf3a1; + valaddr_reg:x4; val_offset:198*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 198*FLEN/8, x6, x7, x1) + +inst_123: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3a1 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3a1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x73a1; op2val:0xf3a1; + valaddr_reg:x4; val_offset:200*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 200*FLEN/8, x6, x7, x1) + +inst_124: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3a1 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3a1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x73a1; op2val:0xf3a1; + valaddr_reg:x4; val_offset:202*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 202*FLEN/8, x6, x7, x1) + +inst_125: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x26c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a6c; op2val:0xfa6c; + valaddr_reg:x4; val_offset:204*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 204*FLEN/8, x6, x7, x1) + +inst_126: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x26c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a6c; op2val:0xfa6c; + valaddr_reg:x4; val_offset:206*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 206*FLEN/8, x6, x7, x1) + +inst_127: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x26c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a6c; op2val:0xfa6c; + valaddr_reg:x4; val_offset:208*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 208*FLEN/8, x6, x7, x1) + +inst_128: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x26c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a6c; op2val:0xfa6c; + valaddr_reg:x4; val_offset:210*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 210*FLEN/8, x6, x7, x1) + +inst_129: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x26c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a6c; op2val:0xfa6c; + valaddr_reg:x4; val_offset:212*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 212*FLEN/8, x6, x7, x1) + +inst_130: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x125 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x125 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d25; op2val:0xed25; + valaddr_reg:x4; val_offset:214*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 214*FLEN/8, x6, x7, x1) + +inst_131: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x125 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x125 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d25; op2val:0xed25; + valaddr_reg:x4; val_offset:216*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 216*FLEN/8, x6, x7, x1) + +inst_132: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x125 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x125 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d25; op2val:0xed25; + valaddr_reg:x4; val_offset:218*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 218*FLEN/8, x6, x7, x1) + +inst_133: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x125 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x125 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d25; op2val:0xed25; + valaddr_reg:x4; val_offset:220*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 220*FLEN/8, x6, x7, x1) + +inst_134: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x125 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x125 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d25; op2val:0xed25; + valaddr_reg:x4; val_offset:222*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 222*FLEN/8, x6, x7, x1) + +inst_135: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x780f; op2val:0xf80f; + valaddr_reg:x4; val_offset:224*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 224*FLEN/8, x6, x7, x1) + +inst_136: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x00f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x780f; op2val:0xf80f; + valaddr_reg:x4; val_offset:226*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 226*FLEN/8, x6, x7, x1) + +inst_137: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x00f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x780f; op2val:0xf80f; + valaddr_reg:x4; val_offset:228*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 228*FLEN/8, x6, x7, x1) + +inst_138: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x00f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x780f; op2val:0xf80f; + valaddr_reg:x4; val_offset:230*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 230*FLEN/8, x6, x7, x1) + +inst_139: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x00f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x780f; op2val:0xf80f; + valaddr_reg:x4; val_offset:232*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 232*FLEN/8, x6, x7, x1) + +inst_140: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2fa and fs2 == 1 and fe2 == 0x1b and fm2 == 0x2fa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6efa; op2val:0xeefa; + valaddr_reg:x4; val_offset:234*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 234*FLEN/8, x6, x7, x1) + +inst_141: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2fa and fs2 == 1 and fe2 == 0x1b and fm2 == 0x2fa and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6efa; op2val:0xeefa; + valaddr_reg:x4; val_offset:236*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 236*FLEN/8, x6, x7, x1) + +inst_142: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2fa and fs2 == 1 and fe2 == 0x1b and fm2 == 0x2fa and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6efa; op2val:0xeefa; + valaddr_reg:x4; val_offset:238*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 238*FLEN/8, x6, x7, x1) + +inst_143: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2fa and fs2 == 1 and fe2 == 0x1b and fm2 == 0x2fa and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6efa; op2val:0xeefa; + valaddr_reg:x4; val_offset:240*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 240*FLEN/8, x6, x7, x1) + +inst_144: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2fa and fs2 == 1 and fe2 == 0x1b and fm2 == 0x2fa and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6efa; op2val:0xeefa; + valaddr_reg:x4; val_offset:242*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 242*FLEN/8, x6, x7, x1) +RVTEST_SIGBASE(x7,signature_x7_1) + +inst_145: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a6 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1a6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79a6; op2val:0xf9a6; + valaddr_reg:x4; val_offset:244*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 244*FLEN/8, x6, x7, x1) + +inst_146: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a6 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1a6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79a6; op2val:0xf9a6; + valaddr_reg:x4; val_offset:246*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 246*FLEN/8, x6, x7, x1) + +inst_147: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a6 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1a6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79a6; op2val:0xf9a6; + valaddr_reg:x4; val_offset:248*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 248*FLEN/8, x6, x7, x1) + +inst_148: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a6 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1a6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79a6; op2val:0xf9a6; + valaddr_reg:x4; val_offset:250*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 250*FLEN/8, x6, x7, x1) + +inst_149: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a6 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1a6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79a6; op2val:0xf9a6; + valaddr_reg:x4; val_offset:252*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 252*FLEN/8, x6, x7, x1) + +inst_150: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x283 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x283 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a83; op2val:0xfa83; + valaddr_reg:x4; val_offset:254*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 254*FLEN/8, x6, x7, x1) + +inst_151: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x283 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x283 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a83; op2val:0xfa83; + valaddr_reg:x4; val_offset:256*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 256*FLEN/8, x6, x7, x1) + +inst_152: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x283 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x283 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a83; op2val:0xfa83; + valaddr_reg:x4; val_offset:258*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 258*FLEN/8, x6, x7, x1) + +inst_153: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x283 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x283 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a83; op2val:0xfa83; + valaddr_reg:x4; val_offset:260*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 260*FLEN/8, x6, x7, x1) + +inst_154: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x283 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x283 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a83; op2val:0xfa83; + valaddr_reg:x4; val_offset:262*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 262*FLEN/8, x6, x7, x1) + +inst_155: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3b4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb4; op2val:0xfbb4; + valaddr_reg:x4; val_offset:264*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 264*FLEN/8, x6, x7, x1) + +inst_156: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3b4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb4; op2val:0xfbb4; + valaddr_reg:x4; val_offset:266*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 266*FLEN/8, x6, x7, x1) + +inst_157: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3b4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb4; op2val:0xfbb4; + valaddr_reg:x4; val_offset:268*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 268*FLEN/8, x6, x7, x1) + +inst_158: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3b4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb4; op2val:0xfbb4; + valaddr_reg:x4; val_offset:270*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 270*FLEN/8, x6, x7, x1) + +inst_159: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3b4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb4; op2val:0xfbb4; + valaddr_reg:x4; val_offset:272*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 272*FLEN/8, x6, x7, x1) + +inst_160: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b2 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0b2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78b2; op2val:0xf8b2; + valaddr_reg:x4; val_offset:274*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 274*FLEN/8, x6, x7, x1) + +inst_161: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b2 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0b2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78b2; op2val:0xf8b2; + valaddr_reg:x4; val_offset:276*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 276*FLEN/8, x6, x7, x1) + +inst_162: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b2 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0b2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78b2; op2val:0xf8b2; + valaddr_reg:x4; val_offset:278*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 278*FLEN/8, x6, x7, x1) + +inst_163: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b2 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0b2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78b2; op2val:0xf8b2; + valaddr_reg:x4; val_offset:280*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 280*FLEN/8, x6, x7, x1) + +inst_164: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b2 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0b2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78b2; op2val:0xf8b2; + valaddr_reg:x4; val_offset:282*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 282*FLEN/8, x6, x7, x1) + +inst_165: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0c4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78c4; op2val:0xf8c4; + valaddr_reg:x4; val_offset:284*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 284*FLEN/8, x6, x7, x1) + +inst_166: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0c4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78c4; op2val:0xf8c4; + valaddr_reg:x4; val_offset:286*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 286*FLEN/8, x6, x7, x1) + +inst_167: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0c4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78c4; op2val:0xf8c4; + valaddr_reg:x4; val_offset:288*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 288*FLEN/8, x6, x7, x1) + +inst_168: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0c4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78c4; op2val:0xf8c4; + valaddr_reg:x4; val_offset:290*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 290*FLEN/8, x6, x7, x1) + +inst_169: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0c4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78c4; op2val:0xf8c4; + valaddr_reg:x4; val_offset:292*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 292*FLEN/8, x6, x7, x1) + +inst_170: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x09a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x789a; op2val:0xf89a; + valaddr_reg:x4; val_offset:294*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 294*FLEN/8, x6, x7, x1) + +inst_171: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x09a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x789a; op2val:0xf89a; + valaddr_reg:x4; val_offset:296*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 296*FLEN/8, x6, x7, x1) + +inst_172: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x09a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x789a; op2val:0xf89a; + valaddr_reg:x4; val_offset:298*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 298*FLEN/8, x6, x7, x1) + +inst_173: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x09a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x789a; op2val:0xf89a; + valaddr_reg:x4; val_offset:300*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 300*FLEN/8, x6, x7, x1) + +inst_174: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x09a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x789a; op2val:0xf89a; + valaddr_reg:x4; val_offset:302*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 302*FLEN/8, x6, x7, x1) + +inst_175: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x20e and fs2 == 1 and fe2 == 0x1c and fm2 == 0x20e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x720e; op2val:0xf20e; + valaddr_reg:x4; val_offset:304*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 304*FLEN/8, x6, x7, x1) + +inst_176: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x20e and fs2 == 1 and fe2 == 0x1c and fm2 == 0x20e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x720e; op2val:0xf20e; + valaddr_reg:x4; val_offset:306*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 306*FLEN/8, x6, x7, x1) + +inst_177: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x20e and fs2 == 1 and fe2 == 0x1c and fm2 == 0x20e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x720e; op2val:0xf20e; + valaddr_reg:x4; val_offset:308*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 308*FLEN/8, x6, x7, x1) + +inst_178: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x20e and fs2 == 1 and fe2 == 0x1c and fm2 == 0x20e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x720e; op2val:0xf20e; + valaddr_reg:x4; val_offset:310*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 310*FLEN/8, x6, x7, x1) + +inst_179: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x20e and fs2 == 1 and fe2 == 0x1c and fm2 == 0x20e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x720e; op2val:0xf20e; + valaddr_reg:x4; val_offset:312*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 312*FLEN/8, x6, x7, x1) + +inst_180: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e6 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0e6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78e6; op2val:0xf8e6; + valaddr_reg:x4; val_offset:314*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 314*FLEN/8, x6, x7, x1) + +inst_181: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e6 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0e6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78e6; op2val:0xf8e6; + valaddr_reg:x4; val_offset:316*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 316*FLEN/8, x6, x7, x1) + +inst_182: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e6 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0e6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78e6; op2val:0xf8e6; + valaddr_reg:x4; val_offset:318*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 318*FLEN/8, x6, x7, x1) + +inst_183: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e6 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0e6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78e6; op2val:0xf8e6; + valaddr_reg:x4; val_offset:320*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 320*FLEN/8, x6, x7, x1) + +inst_184: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e6 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0e6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78e6; op2val:0xf8e6; + valaddr_reg:x4; val_offset:322*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 322*FLEN/8, x6, x7, x1) + +inst_185: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x39e and fs2 == 1 and fe2 == 0x1d and fm2 == 0x39e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x779e; op2val:0xf79e; + valaddr_reg:x4; val_offset:324*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 324*FLEN/8, x6, x7, x1) + +inst_186: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x39e and fs2 == 1 and fe2 == 0x1d and fm2 == 0x39e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x779e; op2val:0xf79e; + valaddr_reg:x4; val_offset:326*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 326*FLEN/8, x6, x7, x1) + +inst_187: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x39e and fs2 == 1 and fe2 == 0x1d and fm2 == 0x39e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x779e; op2val:0xf79e; + valaddr_reg:x4; val_offset:328*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 328*FLEN/8, x6, x7, x1) + +inst_188: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x39e and fs2 == 1 and fe2 == 0x1d and fm2 == 0x39e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x779e; op2val:0xf79e; + valaddr_reg:x4; val_offset:330*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 330*FLEN/8, x6, x7, x1) + +inst_189: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x39e and fs2 == 1 and fe2 == 0x1d and fm2 == 0x39e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x779e; op2val:0xf79e; + valaddr_reg:x4; val_offset:332*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 332*FLEN/8, x6, x7, x1) + +inst_190: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x20e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a0e; op2val:0xfa0e; + valaddr_reg:x4; val_offset:334*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 334*FLEN/8, x6, x7, x1) + +inst_191: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x20e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a0e; op2val:0xfa0e; + valaddr_reg:x4; val_offset:336*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 336*FLEN/8, x6, x7, x1) + +inst_192: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x20e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a0e; op2val:0xfa0e; + valaddr_reg:x4; val_offset:338*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 338*FLEN/8, x6, x7, x1) + +inst_193: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x20e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a0e; op2val:0xfa0e; + valaddr_reg:x4; val_offset:340*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 340*FLEN/8, x6, x7, x1) + +inst_194: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x20e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a0e; op2val:0xfa0e; + valaddr_reg:x4; val_offset:342*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 342*FLEN/8, x6, x7, x1) + +inst_195: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x362 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x362 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b62; op2val:0xfb62; + valaddr_reg:x4; val_offset:344*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 344*FLEN/8, x6, x7, x1) + +inst_196: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x362 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x362 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b62; op2val:0xfb62; + valaddr_reg:x4; val_offset:346*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 346*FLEN/8, x6, x7, x1) + +inst_197: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x362 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x362 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b62; op2val:0xfb62; + valaddr_reg:x4; val_offset:348*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 348*FLEN/8, x6, x7, x1) + +inst_198: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x362 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x362 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b62; op2val:0xfb62; + valaddr_reg:x4; val_offset:350*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 350*FLEN/8, x6, x7, x1) + +inst_199: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x362 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x362 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b62; op2val:0xfb62; + valaddr_reg:x4; val_offset:352*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 352*FLEN/8, x6, x7, x1) + +inst_200: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x32e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b2e; op2val:0xfb2e; + valaddr_reg:x4; val_offset:354*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 354*FLEN/8, x6, x7, x1) + +inst_201: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x32e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b2e; op2val:0xfb2e; + valaddr_reg:x4; val_offset:356*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 356*FLEN/8, x6, x7, x1) + +inst_202: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x32e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b2e; op2val:0xfb2e; + valaddr_reg:x4; val_offset:358*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 358*FLEN/8, x6, x7, x1) + +inst_203: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x32e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b2e; op2val:0xfb2e; + valaddr_reg:x4; val_offset:360*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 360*FLEN/8, x6, x7, x1) + +inst_204: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x32e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b2e; op2val:0xfb2e; + valaddr_reg:x4; val_offset:362*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 362*FLEN/8, x6, x7, x1) + +inst_205: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x052 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x052 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7852; op2val:0xf852; + valaddr_reg:x4; val_offset:364*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 364*FLEN/8, x6, x7, x1) + +inst_206: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x052 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x052 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7852; op2val:0xf852; + valaddr_reg:x4; val_offset:366*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 366*FLEN/8, x6, x7, x1) + +inst_207: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x052 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x052 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7852; op2val:0xf852; + valaddr_reg:x4; val_offset:368*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 368*FLEN/8, x6, x7, x1) + +inst_208: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x052 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x052 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7852; op2val:0xf852; + valaddr_reg:x4; val_offset:370*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 370*FLEN/8, x6, x7, x1) + +inst_209: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x052 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x052 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7852; op2val:0xf852; + valaddr_reg:x4; val_offset:372*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 372*FLEN/8, x6, x7, x1) + +inst_210: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1a3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79a3; op2val:0xf9a3; + valaddr_reg:x4; val_offset:374*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 374*FLEN/8, x6, x7, x1) + +inst_211: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1a3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79a3; op2val:0xf9a3; + valaddr_reg:x4; val_offset:376*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 376*FLEN/8, x6, x7, x1) + +inst_212: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1a3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79a3; op2val:0xf9a3; + valaddr_reg:x4; val_offset:378*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 378*FLEN/8, x6, x7, x1) + +inst_213: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1a3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79a3; op2val:0xf9a3; + valaddr_reg:x4; val_offset:380*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 380*FLEN/8, x6, x7, x1) + +inst_214: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1a3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79a3; op2val:0xf9a3; + valaddr_reg:x4; val_offset:382*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 382*FLEN/8, x6, x7, x1) + +inst_215: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x27d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x27d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a7d; op2val:0xfa7d; + valaddr_reg:x4; val_offset:384*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 384*FLEN/8, x6, x7, x1) + +inst_216: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x27d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x27d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a7d; op2val:0xfa7d; + valaddr_reg:x4; val_offset:386*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 386*FLEN/8, x6, x7, x1) + +inst_217: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x27d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x27d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a7d; op2val:0xfa7d; + valaddr_reg:x4; val_offset:388*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 388*FLEN/8, x6, x7, x1) + +inst_218: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x27d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x27d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a7d; op2val:0xfa7d; + valaddr_reg:x4; val_offset:390*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 390*FLEN/8, x6, x7, x1) + +inst_219: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x27d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x27d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a7d; op2val:0xfa7d; + valaddr_reg:x4; val_offset:392*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 392*FLEN/8, x6, x7, x1) + +inst_220: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x328 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x328 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b28; op2val:0xfb28; + valaddr_reg:x4; val_offset:394*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 394*FLEN/8, x6, x7, x1) + +inst_221: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x328 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x328 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b28; op2val:0xfb28; + valaddr_reg:x4; val_offset:396*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 396*FLEN/8, x6, x7, x1) + +inst_222: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x328 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x328 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b28; op2val:0xfb28; + valaddr_reg:x4; val_offset:398*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 398*FLEN/8, x6, x7, x1) + +inst_223: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x328 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x328 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b28; op2val:0xfb28; + valaddr_reg:x4; val_offset:400*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 400*FLEN/8, x6, x7, x1) + +inst_224: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x328 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x328 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b28; op2val:0xfb28; + valaddr_reg:x4; val_offset:402*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 402*FLEN/8, x6, x7, x1) + +inst_225: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x398 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x398 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b98; op2val:0xfb98; + valaddr_reg:x4; val_offset:404*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 404*FLEN/8, x6, x7, x1) + +inst_226: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x398 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x398 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b98; op2val:0xfb98; + valaddr_reg:x4; val_offset:406*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 406*FLEN/8, x6, x7, x1) + +inst_227: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x398 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x398 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b98; op2val:0xfb98; + valaddr_reg:x4; val_offset:408*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 408*FLEN/8, x6, x7, x1) + +inst_228: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x398 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x398 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b98; op2val:0xfb98; + valaddr_reg:x4; val_offset:410*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 410*FLEN/8, x6, x7, x1) + +inst_229: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x398 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x398 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b98; op2val:0xfb98; + valaddr_reg:x4; val_offset:412*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 412*FLEN/8, x6, x7, x1) + +inst_230: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x334 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x334 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7734; op2val:0xf734; + valaddr_reg:x4; val_offset:414*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 414*FLEN/8, x6, x7, x1) + +inst_231: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x334 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x334 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7734; op2val:0xf734; + valaddr_reg:x4; val_offset:416*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 416*FLEN/8, x6, x7, x1) + +inst_232: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x334 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x334 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7734; op2val:0xf734; + valaddr_reg:x4; val_offset:418*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 418*FLEN/8, x6, x7, x1) + +inst_233: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x334 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x334 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7734; op2val:0xf734; + valaddr_reg:x4; val_offset:420*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 420*FLEN/8, x6, x7, x1) + +inst_234: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x334 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x334 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7734; op2val:0xf734; + valaddr_reg:x4; val_offset:422*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 422*FLEN/8, x6, x7, x1) + +inst_235: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f7 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3f7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bf7; op2val:0xfbf7; + valaddr_reg:x4; val_offset:424*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 424*FLEN/8, x6, x7, x1) + +inst_236: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f7 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3f7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bf7; op2val:0xfbf7; + valaddr_reg:x4; val_offset:426*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 426*FLEN/8, x6, x7, x1) + +inst_237: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f7 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3f7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bf7; op2val:0xfbf7; + valaddr_reg:x4; val_offset:428*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 428*FLEN/8, x6, x7, x1) + +inst_238: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f7 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3f7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bf7; op2val:0xfbf7; + valaddr_reg:x4; val_offset:430*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 430*FLEN/8, x6, x7, x1) + +inst_239: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f7 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3f7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bf7; op2val:0xfbf7; + valaddr_reg:x4; val_offset:432*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 432*FLEN/8, x6, x7, x1) + +inst_240: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x257 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x257 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a57; op2val:0xfa57; + valaddr_reg:x4; val_offset:434*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 434*FLEN/8, x6, x7, x1) + +inst_241: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x257 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x257 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a57; op2val:0xfa57; + valaddr_reg:x4; val_offset:436*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 436*FLEN/8, x6, x7, x1) + +inst_242: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x257 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x257 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a57; op2val:0xfa57; + valaddr_reg:x4; val_offset:438*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 438*FLEN/8, x6, x7, x1) + +inst_243: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x257 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x257 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a57; op2val:0xfa57; + valaddr_reg:x4; val_offset:440*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 440*FLEN/8, x6, x7, x1) + +inst_244: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x257 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x257 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a57; op2val:0xfa57; + valaddr_reg:x4; val_offset:442*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 442*FLEN/8, x6, x7, x1) + +inst_245: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x109 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x109 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7909; op2val:0xf909; + valaddr_reg:x4; val_offset:444*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 444*FLEN/8, x6, x7, x1) + +inst_246: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x109 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x109 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7909; op2val:0xf909; + valaddr_reg:x4; val_offset:446*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 446*FLEN/8, x6, x7, x1) + +inst_247: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x109 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x109 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7909; op2val:0xf909; + valaddr_reg:x4; val_offset:448*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 448*FLEN/8, x6, x7, x1) + +inst_248: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x109 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x109 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7909; op2val:0xf909; + valaddr_reg:x4; val_offset:450*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 450*FLEN/8, x6, x7, x1) + +inst_249: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x109 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x109 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7909; op2val:0xf909; + valaddr_reg:x4; val_offset:452*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 452*FLEN/8, x6, x7, x1) + +inst_250: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3c6 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3c6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x73c6; op2val:0xf3c6; + valaddr_reg:x4; val_offset:454*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 454*FLEN/8, x6, x7, x1) + +inst_251: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3c6 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3c6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x73c6; op2val:0xf3c6; + valaddr_reg:x4; val_offset:456*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 456*FLEN/8, x6, x7, x1) + +inst_252: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3c6 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3c6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x73c6; op2val:0xf3c6; + valaddr_reg:x4; val_offset:458*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 458*FLEN/8, x6, x7, x1) + +inst_253: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3c6 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3c6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x73c6; op2val:0xf3c6; + valaddr_reg:x4; val_offset:460*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 460*FLEN/8, x6, x7, x1) + +inst_254: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3c6 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3c6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x73c6; op2val:0xf3c6; + valaddr_reg:x4; val_offset:462*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 462*FLEN/8, x6, x7, x1) + +inst_255: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x37e and fs2 == 1 and fe2 == 0x1b and fm2 == 0x37e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f7e; op2val:0xef7e; + valaddr_reg:x4; val_offset:464*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 464*FLEN/8, x6, x7, x1) + +inst_256: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x37e and fs2 == 1 and fe2 == 0x1b and fm2 == 0x37e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f7e; op2val:0xef7e; + valaddr_reg:x4; val_offset:466*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 466*FLEN/8, x6, x7, x1) + +inst_257: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x37e and fs2 == 1 and fe2 == 0x1b and fm2 == 0x37e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f7e; op2val:0xef7e; + valaddr_reg:x4; val_offset:468*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 468*FLEN/8, x6, x7, x1) + +inst_258: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x37e and fs2 == 1 and fe2 == 0x1b and fm2 == 0x37e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f7e; op2val:0xef7e; + valaddr_reg:x4; val_offset:470*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 470*FLEN/8, x6, x7, x1) + +inst_259: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x37e and fs2 == 1 and fe2 == 0x1b and fm2 == 0x37e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f7e; op2val:0xef7e; + valaddr_reg:x4; val_offset:472*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 472*FLEN/8, x6, x7, x1) + +inst_260: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x25a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a5a; op2val:0xfa5a; + valaddr_reg:x4; val_offset:474*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 474*FLEN/8, x6, x7, x1) + +inst_261: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x25a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a5a; op2val:0xfa5a; + valaddr_reg:x4; val_offset:476*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 476*FLEN/8, x6, x7, x1) + +inst_262: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x25a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a5a; op2val:0xfa5a; + valaddr_reg:x4; val_offset:478*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 478*FLEN/8, x6, x7, x1) + +inst_263: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x25a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a5a; op2val:0xfa5a; + valaddr_reg:x4; val_offset:480*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 480*FLEN/8, x6, x7, x1) + +inst_264: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x25a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a5a; op2val:0xfa5a; + valaddr_reg:x4; val_offset:482*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 482*FLEN/8, x6, x7, x1) + +inst_265: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x286 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x286 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a86; op2val:0xfa86; + valaddr_reg:x4; val_offset:484*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 484*FLEN/8, x6, x7, x1) + +inst_266: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x286 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x286 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a86; op2val:0xfa86; + valaddr_reg:x4; val_offset:486*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 486*FLEN/8, x6, x7, x1) + +inst_267: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x286 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x286 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a86; op2val:0xfa86; + valaddr_reg:x4; val_offset:488*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 488*FLEN/8, x6, x7, x1) + +inst_268: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x286 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x286 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a86; op2val:0xfa86; + valaddr_reg:x4; val_offset:490*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 490*FLEN/8, x6, x7, x1) + +inst_269: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x286 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x286 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a86; op2val:0xfa86; + valaddr_reg:x4; val_offset:492*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 492*FLEN/8, x6, x7, x1) + +inst_270: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0ae and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0ae and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x70ae; op2val:0xf0ae; + valaddr_reg:x4; val_offset:494*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 494*FLEN/8, x6, x7, x1) + +inst_271: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0ae and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0ae and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x70ae; op2val:0xf0ae; + valaddr_reg:x4; val_offset:496*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 496*FLEN/8, x6, x7, x1) + +inst_272: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0ae and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0ae and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x70ae; op2val:0xf0ae; + valaddr_reg:x4; val_offset:498*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 498*FLEN/8, x6, x7, x1) +RVTEST_SIGBASE(x7,signature_x7_2) + +inst_273: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0ae and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0ae and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x70ae; op2val:0xf0ae; + valaddr_reg:x4; val_offset:500*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 500*FLEN/8, x6, x7, x1) + +inst_274: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0ae and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0ae and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x70ae; op2val:0xf0ae; + valaddr_reg:x4; val_offset:502*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 502*FLEN/8, x6, x7, x1) + +inst_275: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x1c9 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x1c9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x69c9; op2val:0xe9c9; + valaddr_reg:x4; val_offset:504*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 504*FLEN/8, x6, x7, x1) + +inst_276: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x1c9 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x1c9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x69c9; op2val:0xe9c9; + valaddr_reg:x4; val_offset:506*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 506*FLEN/8, x6, x7, x1) + +inst_277: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x1c9 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x1c9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x69c9; op2val:0xe9c9; + valaddr_reg:x4; val_offset:508*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 508*FLEN/8, x6, x7, x1) + +inst_278: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x1c9 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x1c9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x69c9; op2val:0xe9c9; + valaddr_reg:x4; val_offset:510*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 510*FLEN/8, x6, x7, x1) + +inst_279: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x1c9 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x1c9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x69c9; op2val:0xe9c9; + valaddr_reg:x4; val_offset:512*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 512*FLEN/8, x6, x7, x1) + +inst_280: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x171 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x171 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7971; op2val:0xf971; + valaddr_reg:x4; val_offset:514*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 514*FLEN/8, x6, x7, x1) + +inst_281: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x171 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x171 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7971; op2val:0xf971; + valaddr_reg:x4; val_offset:516*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 516*FLEN/8, x6, x7, x1) + +inst_282: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x171 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x171 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7971; op2val:0xf971; + valaddr_reg:x4; val_offset:518*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 518*FLEN/8, x6, x7, x1) + +inst_283: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x171 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x171 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7971; op2val:0xf971; + valaddr_reg:x4; val_offset:520*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 520*FLEN/8, x6, x7, x1) + +inst_284: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x171 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x171 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7971; op2val:0xf971; + valaddr_reg:x4; val_offset:522*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 522*FLEN/8, x6, x7, x1) + +inst_285: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0xf913; + valaddr_reg:x4; val_offset:524*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 524*FLEN/8, x6, x7, x1) + +inst_286: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0xf913; + valaddr_reg:x4; val_offset:526*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 526*FLEN/8, x6, x7, x1) + +inst_287: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0xf913; + valaddr_reg:x4; val_offset:528*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 528*FLEN/8, x6, x7, x1) + +inst_288: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0xf913; + valaddr_reg:x4; val_offset:530*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 530*FLEN/8, x6, x7, x1) + +inst_289: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0xf913; + valaddr_reg:x4; val_offset:532*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 532*FLEN/8, x6, x7, x1) + +inst_290: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1eb and fs2 == 1 and fe2 == 0x1d and fm2 == 0x1eb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x75eb; op2val:0xf5eb; + valaddr_reg:x4; val_offset:534*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 534*FLEN/8, x6, x7, x1) + +inst_291: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1eb and fs2 == 1 and fe2 == 0x1d and fm2 == 0x1eb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x75eb; op2val:0xf5eb; + valaddr_reg:x4; val_offset:536*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 536*FLEN/8, x6, x7, x1) + +inst_292: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1eb and fs2 == 1 and fe2 == 0x1d and fm2 == 0x1eb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x75eb; op2val:0xf5eb; + valaddr_reg:x4; val_offset:538*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 538*FLEN/8, x6, x7, x1) + +inst_293: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1eb and fs2 == 1 and fe2 == 0x1d and fm2 == 0x1eb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x75eb; op2val:0xf5eb; + valaddr_reg:x4; val_offset:540*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 540*FLEN/8, x6, x7, x1) + +inst_294: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1eb and fs2 == 1 and fe2 == 0x1d and fm2 == 0x1eb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x75eb; op2val:0xf5eb; + valaddr_reg:x4; val_offset:542*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 542*FLEN/8, x6, x7, x1) + +inst_295: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x0a8 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x0a8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x68a8; op2val:0xe8a8; + valaddr_reg:x4; val_offset:544*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 544*FLEN/8, x6, x7, x1) + +inst_296: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x0a8 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x0a8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x68a8; op2val:0xe8a8; + valaddr_reg:x4; val_offset:546*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 546*FLEN/8, x6, x7, x1) + +inst_297: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x0a8 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x0a8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x68a8; op2val:0xe8a8; + valaddr_reg:x4; val_offset:548*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 548*FLEN/8, x6, x7, x1) + +inst_298: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x0a8 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x0a8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x68a8; op2val:0xe8a8; + valaddr_reg:x4; val_offset:550*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 550*FLEN/8, x6, x7, x1) + +inst_299: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x0a8 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x0a8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x68a8; op2val:0xe8a8; + valaddr_reg:x4; val_offset:552*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 552*FLEN/8, x6, x7, x1) + +inst_300: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3af and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3af and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7baf; op2val:0xfbaf; + valaddr_reg:x4; val_offset:554*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 554*FLEN/8, x6, x7, x1) + +inst_301: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3af and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3af and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7baf; op2val:0xfbaf; + valaddr_reg:x4; val_offset:556*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 556*FLEN/8, x6, x7, x1) + +inst_302: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3af and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3af and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7baf; op2val:0xfbaf; + valaddr_reg:x4; val_offset:558*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 558*FLEN/8, x6, x7, x1) + +inst_303: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3af and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3af and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7baf; op2val:0xfbaf; + valaddr_reg:x4; val_offset:560*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 560*FLEN/8, x6, x7, x1) + +inst_304: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3af and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3af and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7baf; op2val:0xfbaf; + valaddr_reg:x4; val_offset:562*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 562*FLEN/8, x6, x7, x1) + +inst_305: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3ed and fs2 == 1 and fe2 == 0x1b and fm2 == 0x3ed and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6fed; op2val:0xefed; + valaddr_reg:x4; val_offset:564*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 564*FLEN/8, x6, x7, x1) + +inst_306: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3ed and fs2 == 1 and fe2 == 0x1b and fm2 == 0x3ed and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6fed; op2val:0xefed; + valaddr_reg:x4; val_offset:566*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 566*FLEN/8, x6, x7, x1) + +inst_307: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3ed and fs2 == 1 and fe2 == 0x1b and fm2 == 0x3ed and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6fed; op2val:0xefed; + valaddr_reg:x4; val_offset:568*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 568*FLEN/8, x6, x7, x1) + +inst_308: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3ed and fs2 == 1 and fe2 == 0x1b and fm2 == 0x3ed and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6fed; op2val:0xefed; + valaddr_reg:x4; val_offset:570*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 570*FLEN/8, x6, x7, x1) + +inst_309: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3ed and fs2 == 1 and fe2 == 0x1b and fm2 == 0x3ed and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6fed; op2val:0xefed; + valaddr_reg:x4; val_offset:572*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 572*FLEN/8, x6, x7, x1) + +inst_310: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x267 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x267 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a67; op2val:0xfa67; + valaddr_reg:x4; val_offset:574*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 574*FLEN/8, x6, x7, x1) + +inst_311: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x267 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x267 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a67; op2val:0xfa67; + valaddr_reg:x4; val_offset:576*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 576*FLEN/8, x6, x7, x1) + +inst_312: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x267 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x267 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a67; op2val:0xfa67; + valaddr_reg:x4; val_offset:578*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 578*FLEN/8, x6, x7, x1) + +inst_313: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x267 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x267 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a67; op2val:0xfa67; + valaddr_reg:x4; val_offset:580*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 580*FLEN/8, x6, x7, x1) + +inst_314: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x267 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x267 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a67; op2val:0xfa67; + valaddr_reg:x4; val_offset:582*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 582*FLEN/8, x6, x7, x1) + +inst_315: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x1d5 and fs2 == 1 and fe2 == 0x19 and fm2 == 0x1d5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x65d5; op2val:0xe5d5; + valaddr_reg:x4; val_offset:584*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 584*FLEN/8, x6, x7, x1) + +inst_316: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x1d5 and fs2 == 1 and fe2 == 0x19 and fm2 == 0x1d5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x65d5; op2val:0xe5d5; + valaddr_reg:x4; val_offset:586*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 586*FLEN/8, x6, x7, x1) + +inst_317: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x1d5 and fs2 == 1 and fe2 == 0x19 and fm2 == 0x1d5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x65d5; op2val:0xe5d5; + valaddr_reg:x4; val_offset:588*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 588*FLEN/8, x6, x7, x1) + +inst_318: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x1d5 and fs2 == 1 and fe2 == 0x19 and fm2 == 0x1d5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x65d5; op2val:0xe5d5; + valaddr_reg:x4; val_offset:590*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 590*FLEN/8, x6, x7, x1) + +inst_319: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x1d5 and fs2 == 1 and fe2 == 0x19 and fm2 == 0x1d5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x65d5; op2val:0xe5d5; + valaddr_reg:x4; val_offset:592*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 592*FLEN/8, x6, x7, x1) + +inst_320: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x27e and fs2 == 1 and fe2 == 0x1b and fm2 == 0x27e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e7e; op2val:0xee7e; + valaddr_reg:x4; val_offset:594*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 594*FLEN/8, x6, x7, x1) + +inst_321: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x27e and fs2 == 1 and fe2 == 0x1b and fm2 == 0x27e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e7e; op2val:0xee7e; + valaddr_reg:x4; val_offset:596*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 596*FLEN/8, x6, x7, x1) + +inst_322: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x27e and fs2 == 1 and fe2 == 0x1b and fm2 == 0x27e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e7e; op2val:0xee7e; + valaddr_reg:x4; val_offset:598*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 598*FLEN/8, x6, x7, x1) + +inst_323: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x27e and fs2 == 1 and fe2 == 0x1b and fm2 == 0x27e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e7e; op2val:0xee7e; + valaddr_reg:x4; val_offset:600*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 600*FLEN/8, x6, x7, x1) + +inst_324: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x27e and fs2 == 1 and fe2 == 0x1b and fm2 == 0x27e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e7e; op2val:0xee7e; + valaddr_reg:x4; val_offset:602*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 602*FLEN/8, x6, x7, x1) + +inst_325: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x310 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x310 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7310; op2val:0xf310; + valaddr_reg:x4; val_offset:604*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 604*FLEN/8, x6, x7, x1) + +inst_326: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x310 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x310 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7310; op2val:0xf310; + valaddr_reg:x4; val_offset:606*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 606*FLEN/8, x6, x7, x1) + +inst_327: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x310 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x310 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7310; op2val:0xf310; + valaddr_reg:x4; val_offset:608*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 608*FLEN/8, x6, x7, x1) + +inst_328: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x310 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x310 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7310; op2val:0xf310; + valaddr_reg:x4; val_offset:610*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 610*FLEN/8, x6, x7, x1) + +inst_329: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x310 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x310 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7310; op2val:0xf310; + valaddr_reg:x4; val_offset:612*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 612*FLEN/8, x6, x7, x1) + +inst_330: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x19a and fs2 == 1 and fe2 == 0x1d and fm2 == 0x19a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x759a; op2val:0xf59a; + valaddr_reg:x4; val_offset:614*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 614*FLEN/8, x6, x7, x1) + +inst_331: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x19a and fs2 == 1 and fe2 == 0x1d and fm2 == 0x19a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x759a; op2val:0xf59a; + valaddr_reg:x4; val_offset:616*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 616*FLEN/8, x6, x7, x1) + +inst_332: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x19a and fs2 == 1 and fe2 == 0x1d and fm2 == 0x19a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x759a; op2val:0xf59a; + valaddr_reg:x4; val_offset:618*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 618*FLEN/8, x6, x7, x1) + +inst_333: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x19a and fs2 == 1 and fe2 == 0x1d and fm2 == 0x19a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x759a; op2val:0xf59a; + valaddr_reg:x4; val_offset:620*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 620*FLEN/8, x6, x7, x1) + +inst_334: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x19a and fs2 == 1 and fe2 == 0x1d and fm2 == 0x19a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x759a; op2val:0xf59a; + valaddr_reg:x4; val_offset:622*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 622*FLEN/8, x6, x7, x1) + +inst_335: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x006 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x006 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7806; op2val:0xf806; + valaddr_reg:x4; val_offset:624*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 624*FLEN/8, x6, x7, x1) + +inst_336: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x006 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x006 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7806; op2val:0xf806; + valaddr_reg:x4; val_offset:626*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 626*FLEN/8, x6, x7, x1) + +inst_337: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x006 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x006 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7806; op2val:0xf806; + valaddr_reg:x4; val_offset:628*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 628*FLEN/8, x6, x7, x1) + +inst_338: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x006 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x006 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7806; op2val:0xf806; + valaddr_reg:x4; val_offset:630*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 630*FLEN/8, x6, x7, x1) + +inst_339: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x006 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x006 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7806; op2val:0xf806; + valaddr_reg:x4; val_offset:632*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 632*FLEN/8, x6, x7, x1) + +inst_340: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x274 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x274 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e74; op2val:0xee74; + valaddr_reg:x4; val_offset:634*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 634*FLEN/8, x6, x7, x1) + +inst_341: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x274 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x274 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e74; op2val:0xee74; + valaddr_reg:x4; val_offset:636*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 636*FLEN/8, x6, x7, x1) + +inst_342: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x274 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x274 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e74; op2val:0xee74; + valaddr_reg:x4; val_offset:638*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 638*FLEN/8, x6, x7, x1) + +inst_343: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x274 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x274 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e74; op2val:0xee74; + valaddr_reg:x4; val_offset:640*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 640*FLEN/8, x6, x7, x1) + +inst_344: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x274 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x274 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e74; op2val:0xee74; + valaddr_reg:x4; val_offset:642*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 642*FLEN/8, x6, x7, x1) + +inst_345: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x260 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x260 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7260; op2val:0xf260; + valaddr_reg:x4; val_offset:644*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 644*FLEN/8, x6, x7, x1) + +inst_346: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x260 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x260 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7260; op2val:0xf260; + valaddr_reg:x4; val_offset:646*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 646*FLEN/8, x6, x7, x1) + +inst_347: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x260 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x260 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7260; op2val:0xf260; + valaddr_reg:x4; val_offset:648*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 648*FLEN/8, x6, x7, x1) + +inst_348: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x260 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x260 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7260; op2val:0xf260; + valaddr_reg:x4; val_offset:650*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 650*FLEN/8, x6, x7, x1) + +inst_349: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x260 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x260 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7260; op2val:0xf260; + valaddr_reg:x4; val_offset:652*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 652*FLEN/8, x6, x7, x1) + +inst_350: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1d9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79d9; op2val:0xf9d9; + valaddr_reg:x4; val_offset:654*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 654*FLEN/8, x6, x7, x1) + +inst_351: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1d9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79d9; op2val:0xf9d9; + valaddr_reg:x4; val_offset:656*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 656*FLEN/8, x6, x7, x1) + +inst_352: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1d9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79d9; op2val:0xf9d9; + valaddr_reg:x4; val_offset:658*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 658*FLEN/8, x6, x7, x1) + +inst_353: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1d9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79d9; op2val:0xf9d9; + valaddr_reg:x4; val_offset:660*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 660*FLEN/8, x6, x7, x1) + +inst_354: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1d9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79d9; op2val:0xf9d9; + valaddr_reg:x4; val_offset:662*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 662*FLEN/8, x6, x7, x1) + +inst_355: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x358 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x358 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b58; op2val:0xfb58; + valaddr_reg:x4; val_offset:664*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 664*FLEN/8, x6, x7, x1) + +inst_356: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x358 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x358 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b58; op2val:0xfb58; + valaddr_reg:x4; val_offset:666*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 666*FLEN/8, x6, x7, x1) + +inst_357: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x358 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x358 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b58; op2val:0xfb58; + valaddr_reg:x4; val_offset:668*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 668*FLEN/8, x6, x7, x1) + +inst_358: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x358 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x358 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b58; op2val:0xfb58; + valaddr_reg:x4; val_offset:670*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 670*FLEN/8, x6, x7, x1) + +inst_359: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x358 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x358 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b58; op2val:0xfb58; + valaddr_reg:x4; val_offset:672*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 672*FLEN/8, x6, x7, x1) + +inst_360: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x160 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x160 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7960; op2val:0xf960; + valaddr_reg:x4; val_offset:674*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 674*FLEN/8, x6, x7, x1) + +inst_361: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x160 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x160 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7960; op2val:0xf960; + valaddr_reg:x4; val_offset:676*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 676*FLEN/8, x6, x7, x1) + +inst_362: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x160 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x160 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7960; op2val:0xf960; + valaddr_reg:x4; val_offset:678*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 678*FLEN/8, x6, x7, x1) + +inst_363: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x160 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x160 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7960; op2val:0xf960; + valaddr_reg:x4; val_offset:680*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 680*FLEN/8, x6, x7, x1) + +inst_364: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x160 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x160 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7960; op2val:0xf960; + valaddr_reg:x4; val_offset:682*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 682*FLEN/8, x6, x7, x1) + +inst_365: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x36d and fs2 == 1 and fe2 == 0x1a and fm2 == 0x36d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6b6d; op2val:0xeb6d; + valaddr_reg:x4; val_offset:684*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 684*FLEN/8, x6, x7, x1) + +inst_366: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x36d and fs2 == 1 and fe2 == 0x1a and fm2 == 0x36d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6b6d; op2val:0xeb6d; + valaddr_reg:x4; val_offset:686*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 686*FLEN/8, x6, x7, x1) + +inst_367: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x36d and fs2 == 1 and fe2 == 0x1a and fm2 == 0x36d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6b6d; op2val:0xeb6d; + valaddr_reg:x4; val_offset:688*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 688*FLEN/8, x6, x7, x1) + +inst_368: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x36d and fs2 == 1 and fe2 == 0x1a and fm2 == 0x36d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6b6d; op2val:0xeb6d; + valaddr_reg:x4; val_offset:690*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 690*FLEN/8, x6, x7, x1) + +inst_369: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x36d and fs2 == 1 and fe2 == 0x1a and fm2 == 0x36d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6b6d; op2val:0xeb6d; + valaddr_reg:x4; val_offset:692*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 692*FLEN/8, x6, x7, x1) + +inst_370: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c2 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2c2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ac2; op2val:0xfac2; + valaddr_reg:x4; val_offset:694*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 694*FLEN/8, x6, x7, x1) + +inst_371: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c2 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2c2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ac2; op2val:0xfac2; + valaddr_reg:x4; val_offset:696*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 696*FLEN/8, x6, x7, x1) + +inst_372: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c2 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2c2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ac2; op2val:0xfac2; + valaddr_reg:x4; val_offset:698*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 698*FLEN/8, x6, x7, x1) + +inst_373: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c2 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2c2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ac2; op2val:0xfac2; + valaddr_reg:x4; val_offset:700*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 700*FLEN/8, x6, x7, x1) + +inst_374: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c2 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2c2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ac2; op2val:0xfac2; + valaddr_reg:x4; val_offset:702*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 702*FLEN/8, x6, x7, x1) + +inst_375: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7402; op2val:0xf402; + valaddr_reg:x4; val_offset:704*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 704*FLEN/8, x6, x7, x1) + +inst_376: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x002 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7402; op2val:0xf402; + valaddr_reg:x4; val_offset:706*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 706*FLEN/8, x6, x7, x1) + +inst_377: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x002 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7402; op2val:0xf402; + valaddr_reg:x4; val_offset:708*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 708*FLEN/8, x6, x7, x1) + +inst_378: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x002 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7402; op2val:0xf402; + valaddr_reg:x4; val_offset:710*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 710*FLEN/8, x6, x7, x1) + +inst_379: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x002 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7402; op2val:0xf402; + valaddr_reg:x4; val_offset:712*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 712*FLEN/8, x6, x7, x1) + +inst_380: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x312 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x312 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7712; op2val:0xf712; + valaddr_reg:x4; val_offset:714*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 714*FLEN/8, x6, x7, x1) + +inst_381: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x312 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x312 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7712; op2val:0xf712; + valaddr_reg:x4; val_offset:716*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 716*FLEN/8, x6, x7, x1) + +inst_382: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x312 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x312 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7712; op2val:0xf712; + valaddr_reg:x4; val_offset:718*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 718*FLEN/8, x6, x7, x1) + +inst_383: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x312 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x312 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7712; op2val:0xf712; + valaddr_reg:x4; val_offset:720*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 720*FLEN/8, x6, x7, x1) + +inst_384: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x312 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x312 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7712; op2val:0xf712; + valaddr_reg:x4; val_offset:722*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 722*FLEN/8, x6, x7, x1) + +inst_385: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x38a and fs2 == 1 and fe2 == 0x1d and fm2 == 0x38a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x778a; op2val:0xf78a; + valaddr_reg:x4; val_offset:724*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 724*FLEN/8, x6, x7, x1) + +inst_386: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x38a and fs2 == 1 and fe2 == 0x1d and fm2 == 0x38a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x778a; op2val:0xf78a; + valaddr_reg:x4; val_offset:726*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 726*FLEN/8, x6, x7, x1) + +inst_387: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x38a and fs2 == 1 and fe2 == 0x1d and fm2 == 0x38a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x778a; op2val:0xf78a; + valaddr_reg:x4; val_offset:728*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 728*FLEN/8, x6, x7, x1) + +inst_388: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x38a and fs2 == 1 and fe2 == 0x1d and fm2 == 0x38a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x778a; op2val:0xf78a; + valaddr_reg:x4; val_offset:730*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 730*FLEN/8, x6, x7, x1) + +inst_389: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x38a and fs2 == 1 and fe2 == 0x1d and fm2 == 0x38a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x778a; op2val:0xf78a; + valaddr_reg:x4; val_offset:732*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 732*FLEN/8, x6, x7, x1) + +inst_390: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x08c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x08c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x788c; op2val:0xf88c; + valaddr_reg:x4; val_offset:734*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 734*FLEN/8, x6, x7, x1) + +inst_391: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x08c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x08c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x788c; op2val:0xf88c; + valaddr_reg:x4; val_offset:736*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 736*FLEN/8, x6, x7, x1) + +inst_392: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x08c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x08c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x788c; op2val:0xf88c; + valaddr_reg:x4; val_offset:738*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 738*FLEN/8, x6, x7, x1) + +inst_393: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x08c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x08c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x788c; op2val:0xf88c; + valaddr_reg:x4; val_offset:740*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 740*FLEN/8, x6, x7, x1) + +inst_394: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x08c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x08c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x788c; op2val:0xf88c; + valaddr_reg:x4; val_offset:742*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 742*FLEN/8, x6, x7, x1) + +inst_395: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x1d and fm2 == 0x0fb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x74fb; op2val:0xf4fb; + valaddr_reg:x4; val_offset:744*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 744*FLEN/8, x6, x7, x1) + +inst_396: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x1d and fm2 == 0x0fb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x74fb; op2val:0xf4fb; + valaddr_reg:x4; val_offset:746*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 746*FLEN/8, x6, x7, x1) + +inst_397: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x1d and fm2 == 0x0fb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x74fb; op2val:0xf4fb; + valaddr_reg:x4; val_offset:748*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 748*FLEN/8, x6, x7, x1) + +inst_398: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x1d and fm2 == 0x0fb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x74fb; op2val:0xf4fb; + valaddr_reg:x4; val_offset:750*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 750*FLEN/8, x6, x7, x1) + +inst_399: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x1d and fm2 == 0x0fb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x74fb; op2val:0xf4fb; + valaddr_reg:x4; val_offset:752*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 752*FLEN/8, x6, x7, x1) + +inst_400: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b2 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2b2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab2; op2val:0xfab2; + valaddr_reg:x4; val_offset:754*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 754*FLEN/8, x6, x7, x1) +RVTEST_SIGBASE(x7,signature_x7_3) + +inst_401: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b2 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2b2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab2; op2val:0xfab2; + valaddr_reg:x4; val_offset:756*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 756*FLEN/8, x6, x7, x1) + +inst_402: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b2 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2b2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab2; op2val:0xfab2; + valaddr_reg:x4; val_offset:758*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 758*FLEN/8, x6, x7, x1) + +inst_403: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b2 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2b2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab2; op2val:0xfab2; + valaddr_reg:x4; val_offset:760*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 760*FLEN/8, x6, x7, x1) + +inst_404: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b2 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2b2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab2; op2val:0xfab2; + valaddr_reg:x4; val_offset:762*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 762*FLEN/8, x6, x7, x1) + +inst_405: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x07b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x07b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x787b; op2val:0xf87b; + valaddr_reg:x4; val_offset:764*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 764*FLEN/8, x6, x7, x1) + +inst_406: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x07b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x07b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x787b; op2val:0xf87b; + valaddr_reg:x4; val_offset:766*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 766*FLEN/8, x6, x7, x1) + +inst_407: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x07b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x07b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x787b; op2val:0xf87b; + valaddr_reg:x4; val_offset:768*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 768*FLEN/8, x6, x7, x1) + +inst_408: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x07b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x07b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x787b; op2val:0xf87b; + valaddr_reg:x4; val_offset:770*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 770*FLEN/8, x6, x7, x1) + +inst_409: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x07b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x07b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x787b; op2val:0xf87b; + valaddr_reg:x4; val_offset:772*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 772*FLEN/8, x6, x7, x1) + +inst_410: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ee and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1ee and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79ee; op2val:0xf9ee; + valaddr_reg:x4; val_offset:774*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 774*FLEN/8, x6, x7, x1) + +inst_411: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ee and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1ee and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79ee; op2val:0xf9ee; + valaddr_reg:x4; val_offset:776*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 776*FLEN/8, x6, x7, x1) + +inst_412: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ee and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1ee and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79ee; op2val:0xf9ee; + valaddr_reg:x4; val_offset:778*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 778*FLEN/8, x6, x7, x1) + +inst_413: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ee and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1ee and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79ee; op2val:0xf9ee; + valaddr_reg:x4; val_offset:780*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 780*FLEN/8, x6, x7, x1) + +inst_414: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ee and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1ee and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79ee; op2val:0xf9ee; + valaddr_reg:x4; val_offset:782*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 782*FLEN/8, x6, x7, x1) + +inst_415: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x1d9 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x1d9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x69d9; op2val:0xe9d9; + valaddr_reg:x4; val_offset:784*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 784*FLEN/8, x6, x7, x1) + +inst_416: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x1d9 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x1d9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x69d9; op2val:0xe9d9; + valaddr_reg:x4; val_offset:786*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 786*FLEN/8, x6, x7, x1) + +inst_417: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x1d9 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x1d9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x69d9; op2val:0xe9d9; + valaddr_reg:x4; val_offset:788*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 788*FLEN/8, x6, x7, x1) + +inst_418: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x1d9 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x1d9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x69d9; op2val:0xe9d9; + valaddr_reg:x4; val_offset:790*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 790*FLEN/8, x6, x7, x1) + +inst_419: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x1d9 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x1d9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x69d9; op2val:0xe9d9; + valaddr_reg:x4; val_offset:792*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 792*FLEN/8, x6, x7, x1) + +inst_420: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3ae and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3ae and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x73ae; op2val:0xf3ae; + valaddr_reg:x4; val_offset:794*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 794*FLEN/8, x6, x7, x1) + +inst_421: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3ae and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3ae and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x73ae; op2val:0xf3ae; + valaddr_reg:x4; val_offset:796*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 796*FLEN/8, x6, x7, x1) + +inst_422: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3ae and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3ae and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x73ae; op2val:0xf3ae; + valaddr_reg:x4; val_offset:798*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 798*FLEN/8, x6, x7, x1) + +inst_423: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3ae and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3ae and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x73ae; op2val:0xf3ae; + valaddr_reg:x4; val_offset:800*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 800*FLEN/8, x6, x7, x1) + +inst_424: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3ae and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3ae and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x73ae; op2val:0xf3ae; + valaddr_reg:x4; val_offset:802*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 802*FLEN/8, x6, x7, x1) + +inst_425: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a2 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x1a2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x75a2; op2val:0xf5a2; + valaddr_reg:x4; val_offset:804*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 804*FLEN/8, x6, x7, x1) + +inst_426: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a2 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x1a2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x75a2; op2val:0xf5a2; + valaddr_reg:x4; val_offset:806*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 806*FLEN/8, x6, x7, x1) + +inst_427: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a2 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x1a2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x75a2; op2val:0xf5a2; + valaddr_reg:x4; val_offset:808*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 808*FLEN/8, x6, x7, x1) + +inst_428: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a2 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x1a2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x75a2; op2val:0xf5a2; + valaddr_reg:x4; val_offset:810*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 810*FLEN/8, x6, x7, x1) + +inst_429: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a2 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x1a2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x75a2; op2val:0xf5a2; + valaddr_reg:x4; val_offset:812*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 812*FLEN/8, x6, x7, x1) + +inst_430: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1be and fs2 == 1 and fe2 == 0x1d and fm2 == 0x1be and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x75be; op2val:0xf5be; + valaddr_reg:x4; val_offset:814*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 814*FLEN/8, x6, x7, x1) + +inst_431: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1be and fs2 == 1 and fe2 == 0x1d and fm2 == 0x1be and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x75be; op2val:0xf5be; + valaddr_reg:x4; val_offset:816*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 816*FLEN/8, x6, x7, x1) + +inst_432: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1be and fs2 == 1 and fe2 == 0x1d and fm2 == 0x1be and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x75be; op2val:0xf5be; + valaddr_reg:x4; val_offset:818*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 818*FLEN/8, x6, x7, x1) + +inst_433: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1be and fs2 == 1 and fe2 == 0x1d and fm2 == 0x1be and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x75be; op2val:0xf5be; + valaddr_reg:x4; val_offset:820*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 820*FLEN/8, x6, x7, x1) + +inst_434: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1be and fs2 == 1 and fe2 == 0x1d and fm2 == 0x1be and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x75be; op2val:0xf5be; + valaddr_reg:x4; val_offset:822*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 822*FLEN/8, x6, x7, x1) + +inst_435: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x111 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x111 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7911; op2val:0xf911; + valaddr_reg:x4; val_offset:824*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 824*FLEN/8, x6, x7, x1) + +inst_436: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x111 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x111 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7911; op2val:0xf911; + valaddr_reg:x4; val_offset:826*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 826*FLEN/8, x6, x7, x1) + +inst_437: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x111 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x111 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7911; op2val:0xf911; + valaddr_reg:x4; val_offset:828*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 828*FLEN/8, x6, x7, x1) + +inst_438: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x111 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x111 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7911; op2val:0xf911; + valaddr_reg:x4; val_offset:830*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 830*FLEN/8, x6, x7, x1) + +inst_439: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x111 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x111 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7911; op2val:0xf911; + valaddr_reg:x4; val_offset:832*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 832*FLEN/8, x6, x7, x1) + +inst_440: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b8 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1b8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b8; op2val:0xf9b8; + valaddr_reg:x4; val_offset:834*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 834*FLEN/8, x6, x7, x1) + +inst_441: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b8 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1b8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b8; op2val:0xf9b8; + valaddr_reg:x4; val_offset:836*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 836*FLEN/8, x6, x7, x1) + +inst_442: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b8 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1b8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b8; op2val:0xf9b8; + valaddr_reg:x4; val_offset:838*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 838*FLEN/8, x6, x7, x1) + +inst_443: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b8 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1b8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b8; op2val:0xf9b8; + valaddr_reg:x4; val_offset:840*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 840*FLEN/8, x6, x7, x1) + +inst_444: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b8 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1b8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b8; op2val:0xf9b8; + valaddr_reg:x4; val_offset:842*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 842*FLEN/8, x6, x7, x1) + +inst_445: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a0 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2a0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x76a0; op2val:0xf6a0; + valaddr_reg:x4; val_offset:844*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 844*FLEN/8, x6, x7, x1) + +inst_446: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a0 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2a0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x76a0; op2val:0xf6a0; + valaddr_reg:x4; val_offset:846*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 846*FLEN/8, x6, x7, x1) + +inst_447: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a0 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2a0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x76a0; op2val:0xf6a0; + valaddr_reg:x4; val_offset:848*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 848*FLEN/8, x6, x7, x1) + +inst_448: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a0 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2a0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x76a0; op2val:0xf6a0; + valaddr_reg:x4; val_offset:850*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 850*FLEN/8, x6, x7, x1) + +inst_449: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a0 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2a0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x76a0; op2val:0xf6a0; + valaddr_reg:x4; val_offset:852*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 852*FLEN/8, x6, x7, x1) + +inst_450: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x24d and fs2 == 1 and fe2 == 0x15 and fm2 == 0x24d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x564d; op2val:0xd64d; + valaddr_reg:x4; val_offset:854*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 854*FLEN/8, x6, x7, x1) + +inst_451: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x24d and fs2 == 1 and fe2 == 0x15 and fm2 == 0x24d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x564d; op2val:0xd64d; + valaddr_reg:x4; val_offset:856*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 856*FLEN/8, x6, x7, x1) + +inst_452: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x24d and fs2 == 1 and fe2 == 0x15 and fm2 == 0x24d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x564d; op2val:0xd64d; + valaddr_reg:x4; val_offset:858*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 858*FLEN/8, x6, x7, x1) + +inst_453: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x24d and fs2 == 1 and fe2 == 0x15 and fm2 == 0x24d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x564d; op2val:0xd64d; + valaddr_reg:x4; val_offset:860*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 860*FLEN/8, x6, x7, x1) + +inst_454: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x24d and fs2 == 1 and fe2 == 0x15 and fm2 == 0x24d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x564d; op2val:0xd64d; + valaddr_reg:x4; val_offset:862*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 862*FLEN/8, x6, x7, x1) + +inst_455: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x159 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x159 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7559; op2val:0xf559; + valaddr_reg:x4; val_offset:864*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 864*FLEN/8, x6, x7, x1) + +inst_456: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x159 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x159 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7559; op2val:0xf559; + valaddr_reg:x4; val_offset:866*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 866*FLEN/8, x6, x7, x1) + +inst_457: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x159 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x159 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7559; op2val:0xf559; + valaddr_reg:x4; val_offset:868*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 868*FLEN/8, x6, x7, x1) + +inst_458: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x159 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x159 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7559; op2val:0xf559; + valaddr_reg:x4; val_offset:870*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 870*FLEN/8, x6, x7, x1) + +inst_459: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x159 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x159 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7559; op2val:0xf559; + valaddr_reg:x4; val_offset:872*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 872*FLEN/8, x6, x7, x1) + +inst_460: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x118 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x118 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7918; op2val:0xf918; + valaddr_reg:x4; val_offset:874*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 874*FLEN/8, x6, x7, x1) + +inst_461: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x118 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x118 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7918; op2val:0xf918; + valaddr_reg:x4; val_offset:876*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 876*FLEN/8, x6, x7, x1) + +inst_462: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x118 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x118 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7918; op2val:0xf918; + valaddr_reg:x4; val_offset:878*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 878*FLEN/8, x6, x7, x1) + +inst_463: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x118 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x118 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7918; op2val:0xf918; + valaddr_reg:x4; val_offset:880*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 880*FLEN/8, x6, x7, x1) + +inst_464: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x118 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x118 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7918; op2val:0xf918; + valaddr_reg:x4; val_offset:882*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 882*FLEN/8, x6, x7, x1) + +inst_465: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aff; op2val:0xfaff; + valaddr_reg:x4; val_offset:884*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 884*FLEN/8, x6, x7, x1) + +inst_466: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aff; op2val:0xfaff; + valaddr_reg:x4; val_offset:886*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 886*FLEN/8, x6, x7, x1) + +inst_467: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aff; op2val:0xfaff; + valaddr_reg:x4; val_offset:888*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 888*FLEN/8, x6, x7, x1) + +inst_468: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aff; op2val:0xfaff; + valaddr_reg:x4; val_offset:890*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 890*FLEN/8, x6, x7, x1) + +inst_469: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aff; op2val:0xfaff; + valaddr_reg:x4; val_offset:892*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 892*FLEN/8, x6, x7, x1) + +inst_470: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x19c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x799c; op2val:0xf99c; + valaddr_reg:x4; val_offset:894*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 894*FLEN/8, x6, x7, x1) + +inst_471: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x19c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x799c; op2val:0xf99c; + valaddr_reg:x4; val_offset:896*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 896*FLEN/8, x6, x7, x1) + +inst_472: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x19c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x799c; op2val:0xf99c; + valaddr_reg:x4; val_offset:898*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 898*FLEN/8, x6, x7, x1) + +inst_473: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x19c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x799c; op2val:0xf99c; + valaddr_reg:x4; val_offset:900*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 900*FLEN/8, x6, x7, x1) + +inst_474: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x19c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x799c; op2val:0xf99c; + valaddr_reg:x4; val_offset:902*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 902*FLEN/8, x6, x7, x1) + +inst_475: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x14b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x14b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x794b; op2val:0xf94b; + valaddr_reg:x4; val_offset:904*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 904*FLEN/8, x6, x7, x1) + +inst_476: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x14b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x14b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x794b; op2val:0xf94b; + valaddr_reg:x4; val_offset:906*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 906*FLEN/8, x6, x7, x1) + +inst_477: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x14b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x14b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x794b; op2val:0xf94b; + valaddr_reg:x4; val_offset:908*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 908*FLEN/8, x6, x7, x1) + +inst_478: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x14b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x14b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x794b; op2val:0xf94b; + valaddr_reg:x4; val_offset:910*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 910*FLEN/8, x6, x7, x1) + +inst_479: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x14b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x14b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x794b; op2val:0xf94b; + valaddr_reg:x4; val_offset:912*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 912*FLEN/8, x6, x7, x1) + +inst_480: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31f and fs2 == 1 and fe2 == 0x1d and fm2 == 0x31f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x771f; op2val:0xf71f; + valaddr_reg:x4; val_offset:914*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 914*FLEN/8, x6, x7, x1) + +inst_481: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31f and fs2 == 1 and fe2 == 0x1d and fm2 == 0x31f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x771f; op2val:0xf71f; + valaddr_reg:x4; val_offset:916*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 916*FLEN/8, x6, x7, x1) + +inst_482: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31f and fs2 == 1 and fe2 == 0x1d and fm2 == 0x31f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x771f; op2val:0xf71f; + valaddr_reg:x4; val_offset:918*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 918*FLEN/8, x6, x7, x1) + +inst_483: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31f and fs2 == 1 and fe2 == 0x1d and fm2 == 0x31f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x771f; op2val:0xf71f; + valaddr_reg:x4; val_offset:920*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 920*FLEN/8, x6, x7, x1) + +inst_484: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31f and fs2 == 1 and fe2 == 0x1d and fm2 == 0x31f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x771f; op2val:0xf71f; + valaddr_reg:x4; val_offset:922*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 922*FLEN/8, x6, x7, x1) + +inst_485: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x10b and fs2 == 1 and fe2 == 0x1c and fm2 == 0x10b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x710b; op2val:0xf10b; + valaddr_reg:x4; val_offset:924*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 924*FLEN/8, x6, x7, x1) + +inst_486: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x10b and fs2 == 1 and fe2 == 0x1c and fm2 == 0x10b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x710b; op2val:0xf10b; + valaddr_reg:x4; val_offset:926*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 926*FLEN/8, x6, x7, x1) + +inst_487: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x10b and fs2 == 1 and fe2 == 0x1c and fm2 == 0x10b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x710b; op2val:0xf10b; + valaddr_reg:x4; val_offset:928*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 928*FLEN/8, x6, x7, x1) + +inst_488: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x10b and fs2 == 1 and fe2 == 0x1c and fm2 == 0x10b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x710b; op2val:0xf10b; + valaddr_reg:x4; val_offset:930*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 930*FLEN/8, x6, x7, x1) + +inst_489: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x10b and fs2 == 1 and fe2 == 0x1c and fm2 == 0x10b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x710b; op2val:0xf10b; + valaddr_reg:x4; val_offset:932*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 932*FLEN/8, x6, x7, x1) + +inst_490: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ca and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3ca and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77ca; op2val:0xf7ca; + valaddr_reg:x4; val_offset:934*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 934*FLEN/8, x6, x7, x1) + +inst_491: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ca and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3ca and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77ca; op2val:0xf7ca; + valaddr_reg:x4; val_offset:936*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 936*FLEN/8, x6, x7, x1) + +inst_492: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ca and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3ca and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77ca; op2val:0xf7ca; + valaddr_reg:x4; val_offset:938*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 938*FLEN/8, x6, x7, x1) + +inst_493: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ca and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3ca and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77ca; op2val:0xf7ca; + valaddr_reg:x4; val_offset:940*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 940*FLEN/8, x6, x7, x1) + +inst_494: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ca and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3ca and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77ca; op2val:0xf7ca; + valaddr_reg:x4; val_offset:942*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 942*FLEN/8, x6, x7, x1) + +inst_495: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x20a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a0a; op2val:0xfa0a; + valaddr_reg:x4; val_offset:944*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 944*FLEN/8, x6, x7, x1) + +inst_496: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x20a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a0a; op2val:0xfa0a; + valaddr_reg:x4; val_offset:946*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 946*FLEN/8, x6, x7, x1) + +inst_497: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x20a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a0a; op2val:0xfa0a; + valaddr_reg:x4; val_offset:948*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 948*FLEN/8, x6, x7, x1) + +inst_498: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x20a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a0a; op2val:0xfa0a; + valaddr_reg:x4; val_offset:950*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 950*FLEN/8, x6, x7, x1) + +inst_499: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x20a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a0a; op2val:0xfa0a; + valaddr_reg:x4; val_offset:952*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 952*FLEN/8, x6, x7, x1) + +inst_500: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3e8 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3e8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77e8; op2val:0xf7e8; + valaddr_reg:x4; val_offset:954*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 954*FLEN/8, x6, x7, x1) + +inst_501: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3e8 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3e8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77e8; op2val:0xf7e8; + valaddr_reg:x4; val_offset:956*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 956*FLEN/8, x6, x7, x1) + +inst_502: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3e8 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3e8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77e8; op2val:0xf7e8; + valaddr_reg:x4; val_offset:958*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 958*FLEN/8, x6, x7, x1) + +inst_503: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3e8 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3e8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77e8; op2val:0xf7e8; + valaddr_reg:x4; val_offset:960*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 960*FLEN/8, x6, x7, x1) + +inst_504: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3e8 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3e8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77e8; op2val:0xf7e8; + valaddr_reg:x4; val_offset:962*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 962*FLEN/8, x6, x7, x1) + +inst_505: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x377 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x377 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7777; op2val:0xf777; + valaddr_reg:x4; val_offset:964*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 964*FLEN/8, x6, x7, x1) + +inst_506: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x377 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x377 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7777; op2val:0xf777; + valaddr_reg:x4; val_offset:966*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 966*FLEN/8, x6, x7, x1) + +inst_507: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x377 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x377 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7777; op2val:0xf777; + valaddr_reg:x4; val_offset:968*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 968*FLEN/8, x6, x7, x1) + +inst_508: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x377 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x377 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7777; op2val:0xf777; + valaddr_reg:x4; val_offset:970*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 970*FLEN/8, x6, x7, x1) + +inst_509: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x377 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x377 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7777; op2val:0xf777; + valaddr_reg:x4; val_offset:972*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 972*FLEN/8, x6, x7, x1) + +inst_510: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x203 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x203 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7203; op2val:0xf203; + valaddr_reg:x4; val_offset:974*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 974*FLEN/8, x6, x7, x1) + +inst_511: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x203 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x203 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7203; op2val:0xf203; + valaddr_reg:x4; val_offset:976*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 976*FLEN/8, x6, x7, x1) + +inst_512: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x203 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x203 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7203; op2val:0xf203; + valaddr_reg:x4; val_offset:978*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 978*FLEN/8, x6, x7, x1) + +inst_513: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x203 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x203 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7203; op2val:0xf203; + valaddr_reg:x4; val_offset:980*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 980*FLEN/8, x6, x7, x1) + +inst_514: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x203 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x203 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7203; op2val:0xf203; + valaddr_reg:x4; val_offset:982*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 982*FLEN/8, x6, x7, x1) + +inst_515: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x10f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x10f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x790f; op2val:0xf90f; + valaddr_reg:x4; val_offset:984*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 984*FLEN/8, x6, x7, x1) + +inst_516: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x10f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x10f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x790f; op2val:0xf90f; + valaddr_reg:x4; val_offset:986*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 986*FLEN/8, x6, x7, x1) + +inst_517: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x10f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x10f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x790f; op2val:0xf90f; + valaddr_reg:x4; val_offset:988*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 988*FLEN/8, x6, x7, x1) + +inst_518: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x10f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x10f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x790f; op2val:0xf90f; + valaddr_reg:x4; val_offset:990*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 990*FLEN/8, x6, x7, x1) + +inst_519: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x10f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x10f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x790f; op2val:0xf90f; + valaddr_reg:x4; val_offset:992*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 992*FLEN/8, x6, x7, x1) + +inst_520: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1cd and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1cd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79cd; op2val:0xf9cd; + valaddr_reg:x4; val_offset:994*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 994*FLEN/8, x6, x7, x1) + +inst_521: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1cd and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1cd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79cd; op2val:0xf9cd; + valaddr_reg:x4; val_offset:996*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 996*FLEN/8, x6, x7, x1) + +inst_522: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1cd and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1cd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79cd; op2val:0xf9cd; + valaddr_reg:x4; val_offset:998*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 998*FLEN/8, x6, x7, x1) + +inst_523: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1cd and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1cd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79cd; op2val:0xf9cd; + valaddr_reg:x4; val_offset:1000*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1000*FLEN/8, x6, x7, x1) + +inst_524: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1cd and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1cd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79cd; op2val:0xf9cd; + valaddr_reg:x4; val_offset:1002*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1002*FLEN/8, x6, x7, x1) + +inst_525: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26d and fs2 == 1 and fe2 == 0x1d and fm2 == 0x26d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x766d; op2val:0xf66d; + valaddr_reg:x4; val_offset:1004*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1004*FLEN/8, x6, x7, x1) + +inst_526: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26d and fs2 == 1 and fe2 == 0x1d and fm2 == 0x26d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x766d; op2val:0xf66d; + valaddr_reg:x4; val_offset:1006*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1006*FLEN/8, x6, x7, x1) + +inst_527: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26d and fs2 == 1 and fe2 == 0x1d and fm2 == 0x26d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x766d; op2val:0xf66d; + valaddr_reg:x4; val_offset:1008*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1008*FLEN/8, x6, x7, x1) + +inst_528: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26d and fs2 == 1 and fe2 == 0x1d and fm2 == 0x26d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x766d; op2val:0xf66d; + valaddr_reg:x4; val_offset:1010*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1010*FLEN/8, x6, x7, x1) +RVTEST_SIGBASE(x7,signature_x7_4) + +inst_529: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26d and fs2 == 1 and fe2 == 0x1d and fm2 == 0x26d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x766d; op2val:0xf66d; + valaddr_reg:x4; val_offset:1012*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1012*FLEN/8, x6, x7, x1) + +inst_530: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x10e and fs2 == 1 and fe2 == 0x1d and fm2 == 0x10e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x750e; op2val:0xf50e; + valaddr_reg:x4; val_offset:1014*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1014*FLEN/8, x6, x7, x1) + +inst_531: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x10e and fs2 == 1 and fe2 == 0x1d and fm2 == 0x10e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x750e; op2val:0xf50e; + valaddr_reg:x4; val_offset:1016*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1016*FLEN/8, x6, x7, x1) + +inst_532: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x10e and fs2 == 1 and fe2 == 0x1d and fm2 == 0x10e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x750e; op2val:0xf50e; + valaddr_reg:x4; val_offset:1018*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1018*FLEN/8, x6, x7, x1) + +inst_533: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x10e and fs2 == 1 and fe2 == 0x1d and fm2 == 0x10e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x750e; op2val:0xf50e; + valaddr_reg:x4; val_offset:1020*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1020*FLEN/8, x6, x7, x1) + +inst_534: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x10e and fs2 == 1 and fe2 == 0x1d and fm2 == 0x10e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x750e; op2val:0xf50e; + valaddr_reg:x4; val_offset:1022*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1022*FLEN/8, x6, x7, x1) + +inst_535: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1bc and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1bc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79bc; op2val:0xf9bc; + valaddr_reg:x4; val_offset:1024*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1024*FLEN/8, x6, x7, x1) + +inst_536: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1bc and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1bc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79bc; op2val:0xf9bc; + valaddr_reg:x4; val_offset:1026*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1026*FLEN/8, x6, x7, x1) + +inst_537: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1bc and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1bc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79bc; op2val:0xf9bc; + valaddr_reg:x4; val_offset:1028*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1028*FLEN/8, x6, x7, x1) + +inst_538: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1bc and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1bc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79bc; op2val:0xf9bc; + valaddr_reg:x4; val_offset:1030*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1030*FLEN/8, x6, x7, x1) + +inst_539: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1bc and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1bc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79bc; op2val:0xf9bc; + valaddr_reg:x4; val_offset:1032*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1032*FLEN/8, x6, x7, x1) + +inst_540: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x294 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x294 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a94; op2val:0xfa94; + valaddr_reg:x4; val_offset:1034*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1034*FLEN/8, x6, x7, x1) + +inst_541: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x294 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x294 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a94; op2val:0xfa94; + valaddr_reg:x4; val_offset:1036*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1036*FLEN/8, x6, x7, x1) + +inst_542: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x294 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x294 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a94; op2val:0xfa94; + valaddr_reg:x4; val_offset:1038*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1038*FLEN/8, x6, x7, x1) + +inst_543: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x294 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x294 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a94; op2val:0xfa94; + valaddr_reg:x4; val_offset:1040*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1040*FLEN/8, x6, x7, x1) + +inst_544: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x294 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x294 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a94; op2val:0xfa94; + valaddr_reg:x4; val_offset:1042*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1042*FLEN/8, x6, x7, x1) + +inst_545: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x241 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x241 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e41; op2val:0xee41; + valaddr_reg:x4; val_offset:1044*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1044*FLEN/8, x6, x7, x1) + +inst_546: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x241 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x241 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e41; op2val:0xee41; + valaddr_reg:x4; val_offset:1046*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1046*FLEN/8, x6, x7, x1) + +inst_547: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x241 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x241 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e41; op2val:0xee41; + valaddr_reg:x4; val_offset:1048*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1048*FLEN/8, x6, x7, x1) + +inst_548: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x241 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x241 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e41; op2val:0xee41; + valaddr_reg:x4; val_offset:1050*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1050*FLEN/8, x6, x7, x1) + +inst_549: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x241 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x241 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e41; op2val:0xee41; + valaddr_reg:x4; val_offset:1052*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1052*FLEN/8, x6, x7, x1) + +inst_550: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x131 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x131 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7931; op2val:0xf931; + valaddr_reg:x4; val_offset:1054*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1054*FLEN/8, x6, x7, x1) + +inst_551: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x131 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x131 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7931; op2val:0xf931; + valaddr_reg:x4; val_offset:1056*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1056*FLEN/8, x6, x7, x1) + +inst_552: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x131 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x131 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7931; op2val:0xf931; + valaddr_reg:x4; val_offset:1058*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1058*FLEN/8, x6, x7, x1) + +inst_553: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x131 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x131 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7931; op2val:0xf931; + valaddr_reg:x4; val_offset:1060*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1060*FLEN/8, x6, x7, x1) + +inst_554: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x131 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x131 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7931; op2val:0xf931; + valaddr_reg:x4; val_offset:1062*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1062*FLEN/8, x6, x7, x1) + +inst_555: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x07a and fs2 == 1 and fe2 == 0x1d and fm2 == 0x07a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x747a; op2val:0xf47a; + valaddr_reg:x4; val_offset:1064*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1064*FLEN/8, x6, x7, x1) + +inst_556: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x07a and fs2 == 1 and fe2 == 0x1d and fm2 == 0x07a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x747a; op2val:0xf47a; + valaddr_reg:x4; val_offset:1066*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1066*FLEN/8, x6, x7, x1) + +inst_557: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x07a and fs2 == 1 and fe2 == 0x1d and fm2 == 0x07a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x747a; op2val:0xf47a; + valaddr_reg:x4; val_offset:1068*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1068*FLEN/8, x6, x7, x1) + +inst_558: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x07a and fs2 == 1 and fe2 == 0x1d and fm2 == 0x07a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x747a; op2val:0xf47a; + valaddr_reg:x4; val_offset:1070*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1070*FLEN/8, x6, x7, x1) + +inst_559: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x07a and fs2 == 1 and fe2 == 0x1d and fm2 == 0x07a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x747a; op2val:0xf47a; + valaddr_reg:x4; val_offset:1072*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1072*FLEN/8, x6, x7, x1) + +inst_560: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x268 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x268 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e68; op2val:0xee68; + valaddr_reg:x4; val_offset:1074*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1074*FLEN/8, x6, x7, x1) + +inst_561: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x268 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x268 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e68; op2val:0xee68; + valaddr_reg:x4; val_offset:1076*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1076*FLEN/8, x6, x7, x1) + +inst_562: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x268 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x268 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e68; op2val:0xee68; + valaddr_reg:x4; val_offset:1078*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1078*FLEN/8, x6, x7, x1) + +inst_563: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x268 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x268 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e68; op2val:0xee68; + valaddr_reg:x4; val_offset:1080*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1080*FLEN/8, x6, x7, x1) + +inst_564: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x268 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x268 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e68; op2val:0xee68; + valaddr_reg:x4; val_offset:1082*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1082*FLEN/8, x6, x7, x1) + +inst_565: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x258 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x258 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7658; op2val:0xf658; + valaddr_reg:x4; val_offset:1084*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1084*FLEN/8, x6, x7, x1) + +inst_566: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x258 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x258 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7658; op2val:0xf658; + valaddr_reg:x4; val_offset:1086*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1086*FLEN/8, x6, x7, x1) + +inst_567: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x258 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x258 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7658; op2val:0xf658; + valaddr_reg:x4; val_offset:1088*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1088*FLEN/8, x6, x7, x1) + +inst_568: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x258 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x258 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7658; op2val:0xf658; + valaddr_reg:x4; val_offset:1090*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1090*FLEN/8, x6, x7, x1) + +inst_569: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x258 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x258 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7658; op2val:0xf658; + valaddr_reg:x4; val_offset:1092*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1092*FLEN/8, x6, x7, x1) + +inst_570: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x064 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x064 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7464; op2val:0xf464; + valaddr_reg:x4; val_offset:1094*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1094*FLEN/8, x6, x7, x1) + +inst_571: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x064 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x064 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7464; op2val:0xf464; + valaddr_reg:x4; val_offset:1096*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1096*FLEN/8, x6, x7, x1) + +inst_572: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x064 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x064 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7464; op2val:0xf464; + valaddr_reg:x4; val_offset:1098*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1098*FLEN/8, x6, x7, x1) + +inst_573: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x064 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x064 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7464; op2val:0xf464; + valaddr_reg:x4; val_offset:1100*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1100*FLEN/8, x6, x7, x1) + +inst_574: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x064 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x064 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7464; op2val:0xf464; + valaddr_reg:x4; val_offset:1102*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1102*FLEN/8, x6, x7, x1) + +inst_575: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a55; op2val:0xfa55; + valaddr_reg:x4; val_offset:1104*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1104*FLEN/8, x6, x7, x1) + +inst_576: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x255 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a55; op2val:0xfa55; + valaddr_reg:x4; val_offset:1106*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1106*FLEN/8, x6, x7, x1) + +inst_577: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x255 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a55; op2val:0xfa55; + valaddr_reg:x4; val_offset:1108*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1108*FLEN/8, x6, x7, x1) + +inst_578: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x255 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a55; op2val:0xfa55; + valaddr_reg:x4; val_offset:1110*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1110*FLEN/8, x6, x7, x1) + +inst_579: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x255 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a55; op2val:0xfa55; + valaddr_reg:x4; val_offset:1112*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1112*FLEN/8, x6, x7, x1) + +inst_580: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x044 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x044 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7044; op2val:0xf044; + valaddr_reg:x4; val_offset:1114*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1114*FLEN/8, x6, x7, x1) + +inst_581: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x044 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x044 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7044; op2val:0xf044; + valaddr_reg:x4; val_offset:1116*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1116*FLEN/8, x6, x7, x1) + +inst_582: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x044 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x044 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7044; op2val:0xf044; + valaddr_reg:x4; val_offset:1118*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1118*FLEN/8, x6, x7, x1) + +inst_583: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x044 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x044 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7044; op2val:0xf044; + valaddr_reg:x4; val_offset:1120*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1120*FLEN/8, x6, x7, x1) + +inst_584: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x044 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x044 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7044; op2val:0xf044; + valaddr_reg:x4; val_offset:1122*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1122*FLEN/8, x6, x7, x1) + +inst_585: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x134 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x134 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7934; op2val:0xf934; + valaddr_reg:x4; val_offset:1124*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1124*FLEN/8, x6, x7, x1) + +inst_586: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x134 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x134 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7934; op2val:0xf934; + valaddr_reg:x4; val_offset:1126*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1126*FLEN/8, x6, x7, x1) + +inst_587: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x134 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x134 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7934; op2val:0xf934; + valaddr_reg:x4; val_offset:1128*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1128*FLEN/8, x6, x7, x1) + +inst_588: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x134 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x134 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7934; op2val:0xf934; + valaddr_reg:x4; val_offset:1130*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1130*FLEN/8, x6, x7, x1) + +inst_589: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x134 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x134 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7934; op2val:0xf934; + valaddr_reg:x4; val_offset:1132*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1132*FLEN/8, x6, x7, x1) + +inst_590: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f8 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7af8; op2val:0xfaf8; + valaddr_reg:x4; val_offset:1134*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1134*FLEN/8, x6, x7, x1) + +inst_591: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f8 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2f8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7af8; op2val:0xfaf8; + valaddr_reg:x4; val_offset:1136*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1136*FLEN/8, x6, x7, x1) + +inst_592: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f8 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2f8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7af8; op2val:0xfaf8; + valaddr_reg:x4; val_offset:1138*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1138*FLEN/8, x6, x7, x1) + +inst_593: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f8 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2f8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7af8; op2val:0xfaf8; + valaddr_reg:x4; val_offset:1140*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1140*FLEN/8, x6, x7, x1) + +inst_594: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f8 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2f8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7af8; op2val:0xfaf8; + valaddr_reg:x4; val_offset:1142*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1142*FLEN/8, x6, x7, x1) + +inst_595: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x0c1 and fs2 == 1 and fe2 == 0x19 and fm2 == 0x0c1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x64c1; op2val:0xe4c1; + valaddr_reg:x4; val_offset:1144*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1144*FLEN/8, x6, x7, x1) + +inst_596: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x0c1 and fs2 == 1 and fe2 == 0x19 and fm2 == 0x0c1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x64c1; op2val:0xe4c1; + valaddr_reg:x4; val_offset:1146*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1146*FLEN/8, x6, x7, x1) + +inst_597: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x0c1 and fs2 == 1 and fe2 == 0x19 and fm2 == 0x0c1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x64c1; op2val:0xe4c1; + valaddr_reg:x4; val_offset:1148*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1148*FLEN/8, x6, x7, x1) + +inst_598: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x0c1 and fs2 == 1 and fe2 == 0x19 and fm2 == 0x0c1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x64c1; op2val:0xe4c1; + valaddr_reg:x4; val_offset:1150*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1150*FLEN/8, x6, x7, x1) + +inst_599: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x0c1 and fs2 == 1 and fe2 == 0x19 and fm2 == 0x0c1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x64c1; op2val:0xe4c1; + valaddr_reg:x4; val_offset:1152*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1152*FLEN/8, x6, x7, x1) + +inst_600: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x172 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x172 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7972; op2val:0xf972; + valaddr_reg:x4; val_offset:1154*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1154*FLEN/8, x6, x7, x1) + +inst_601: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x172 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x172 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7972; op2val:0xf972; + valaddr_reg:x4; val_offset:1156*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1156*FLEN/8, x6, x7, x1) + +inst_602: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x172 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x172 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7972; op2val:0xf972; + valaddr_reg:x4; val_offset:1158*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1158*FLEN/8, x6, x7, x1) + +inst_603: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x172 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x172 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7972; op2val:0xf972; + valaddr_reg:x4; val_offset:1160*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1160*FLEN/8, x6, x7, x1) + +inst_604: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x172 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x172 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7972; op2val:0xf972; + valaddr_reg:x4; val_offset:1162*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1162*FLEN/8, x6, x7, x1) + +inst_605: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x391 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x391 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b91; op2val:0xfb91; + valaddr_reg:x4; val_offset:1164*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1164*FLEN/8, x6, x7, x1) + +inst_606: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x391 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x391 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b91; op2val:0xfb91; + valaddr_reg:x4; val_offset:1166*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1166*FLEN/8, x6, x7, x1) + +inst_607: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x391 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x391 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b91; op2val:0xfb91; + valaddr_reg:x4; val_offset:1168*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1168*FLEN/8, x6, x7, x1) + +inst_608: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x391 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x391 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b91; op2val:0xfb91; + valaddr_reg:x4; val_offset:1170*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1170*FLEN/8, x6, x7, x1) + +inst_609: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x391 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x391 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b91; op2val:0xfb91; + valaddr_reg:x4; val_offset:1172*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1172*FLEN/8, x6, x7, x1) + +inst_610: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1fd and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1fd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79fd; op2val:0xf9fd; + valaddr_reg:x4; val_offset:1174*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1174*FLEN/8, x6, x7, x1) + +inst_611: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1fd and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1fd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79fd; op2val:0xf9fd; + valaddr_reg:x4; val_offset:1176*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1176*FLEN/8, x6, x7, x1) + +inst_612: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1fd and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1fd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79fd; op2val:0xf9fd; + valaddr_reg:x4; val_offset:1178*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1178*FLEN/8, x6, x7, x1) + +inst_613: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1fd and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1fd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79fd; op2val:0xf9fd; + valaddr_reg:x4; val_offset:1180*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1180*FLEN/8, x6, x7, x1) + +inst_614: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1fd and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1fd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79fd; op2val:0xf9fd; + valaddr_reg:x4; val_offset:1182*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1182*FLEN/8, x6, x7, x1) + +inst_615: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x13d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x13d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x793d; op2val:0xf93d; + valaddr_reg:x4; val_offset:1184*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1184*FLEN/8, x6, x7, x1) + +inst_616: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x13d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x13d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x793d; op2val:0xf93d; + valaddr_reg:x4; val_offset:1186*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1186*FLEN/8, x6, x7, x1) + +inst_617: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x13d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x13d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x793d; op2val:0xf93d; + valaddr_reg:x4; val_offset:1188*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1188*FLEN/8, x6, x7, x1) + +inst_618: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x13d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x13d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x793d; op2val:0xf93d; + valaddr_reg:x4; val_offset:1190*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1190*FLEN/8, x6, x7, x1) + +inst_619: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x13d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x13d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x793d; op2val:0xf93d; + valaddr_reg:x4; val_offset:1192*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1192*FLEN/8, x6, x7, x1) + +inst_620: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x337 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x337 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b37; op2val:0xfb37; + valaddr_reg:x4; val_offset:1194*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1194*FLEN/8, x6, x7, x1) + +inst_621: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x337 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x337 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b37; op2val:0xfb37; + valaddr_reg:x4; val_offset:1196*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1196*FLEN/8, x6, x7, x1) + +inst_622: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x337 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x337 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b37; op2val:0xfb37; + valaddr_reg:x4; val_offset:1198*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1198*FLEN/8, x6, x7, x1) + +inst_623: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x337 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x337 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b37; op2val:0xfb37; + valaddr_reg:x4; val_offset:1200*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1200*FLEN/8, x6, x7, x1) + +inst_624: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x337 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x337 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b37; op2val:0xfb37; + valaddr_reg:x4; val_offset:1202*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1202*FLEN/8, x6, x7, x1) + +inst_625: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1f4 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x1f4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x75f4; op2val:0xf5f4; + valaddr_reg:x4; val_offset:1204*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1204*FLEN/8, x6, x7, x1) + +inst_626: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1f4 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x1f4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x75f4; op2val:0xf5f4; + valaddr_reg:x4; val_offset:1206*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1206*FLEN/8, x6, x7, x1) + +inst_627: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1f4 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x1f4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x75f4; op2val:0xf5f4; + valaddr_reg:x4; val_offset:1208*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1208*FLEN/8, x6, x7, x1) + +inst_628: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1f4 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x1f4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x75f4; op2val:0xf5f4; + valaddr_reg:x4; val_offset:1210*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1210*FLEN/8, x6, x7, x1) + +inst_629: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1f4 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x1f4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x75f4; op2val:0xf5f4; + valaddr_reg:x4; val_offset:1212*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1212*FLEN/8, x6, x7, x1) + +inst_630: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2a5 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x2a5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x72a5; op2val:0xf2a5; + valaddr_reg:x4; val_offset:1214*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1214*FLEN/8, x6, x7, x1) + +inst_631: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2a5 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x2a5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x72a5; op2val:0xf2a5; + valaddr_reg:x4; val_offset:1216*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1216*FLEN/8, x6, x7, x1) + +inst_632: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2a5 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x2a5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x72a5; op2val:0xf2a5; + valaddr_reg:x4; val_offset:1218*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1218*FLEN/8, x6, x7, x1) + +inst_633: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2a5 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x2a5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x72a5; op2val:0xf2a5; + valaddr_reg:x4; val_offset:1220*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1220*FLEN/8, x6, x7, x1) + +inst_634: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2a5 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x2a5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x72a5; op2val:0xf2a5; + valaddr_reg:x4; val_offset:1222*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1222*FLEN/8, x6, x7, x1) + +inst_635: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x08f and fs2 == 1 and fe2 == 0x18 and fm2 == 0x08f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x608f; op2val:0xe08f; + valaddr_reg:x4; val_offset:1224*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1224*FLEN/8, x6, x7, x1) + +inst_636: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x08f and fs2 == 1 and fe2 == 0x18 and fm2 == 0x08f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x608f; op2val:0xe08f; + valaddr_reg:x4; val_offset:1226*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1226*FLEN/8, x6, x7, x1) + +inst_637: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x08f and fs2 == 1 and fe2 == 0x18 and fm2 == 0x08f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x608f; op2val:0xe08f; + valaddr_reg:x4; val_offset:1228*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1228*FLEN/8, x6, x7, x1) + +inst_638: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x08f and fs2 == 1 and fe2 == 0x18 and fm2 == 0x08f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x608f; op2val:0xe08f; + valaddr_reg:x4; val_offset:1230*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1230*FLEN/8, x6, x7, x1) + +inst_639: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x08f and fs2 == 1 and fe2 == 0x18 and fm2 == 0x08f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x608f; op2val:0xe08f; + valaddr_reg:x4; val_offset:1232*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1232*FLEN/8, x6, x7, x1) + +inst_640: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7555; op2val:0xf555; + valaddr_reg:x4; val_offset:1234*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1234*FLEN/8, x6, x7, x1) + +inst_641: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x155 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7555; op2val:0xf555; + valaddr_reg:x4; val_offset:1236*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1236*FLEN/8, x6, x7, x1) + +inst_642: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x155 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7555; op2val:0xf555; + valaddr_reg:x4; val_offset:1238*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1238*FLEN/8, x6, x7, x1) + +inst_643: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x155 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7555; op2val:0xf555; + valaddr_reg:x4; val_offset:1240*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1240*FLEN/8, x6, x7, x1) + +inst_644: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x155 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7555; op2val:0xf555; + valaddr_reg:x4; val_offset:1242*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1242*FLEN/8, x6, x7, x1) + +inst_645: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1be and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1be and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79be; op2val:0xf9be; + valaddr_reg:x4; val_offset:1244*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1244*FLEN/8, x6, x7, x1) + +inst_646: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1be and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1be and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79be; op2val:0xf9be; + valaddr_reg:x4; val_offset:1246*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1246*FLEN/8, x6, x7, x1) + +inst_647: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1be and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1be and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79be; op2val:0xf9be; + valaddr_reg:x4; val_offset:1248*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1248*FLEN/8, x6, x7, x1) + +inst_648: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1be and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1be and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79be; op2val:0xf9be; + valaddr_reg:x4; val_offset:1250*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1250*FLEN/8, x6, x7, x1) + +inst_649: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1be and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1be and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79be; op2val:0xf9be; + valaddr_reg:x4; val_offset:1252*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1252*FLEN/8, x6, x7, x1) + +inst_650: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0f6 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0f6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78f6; op2val:0xf8f6; + valaddr_reg:x4; val_offset:1254*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1254*FLEN/8, x6, x7, x1) + +inst_651: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0f6 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0f6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78f6; op2val:0xf8f6; + valaddr_reg:x4; val_offset:1256*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1256*FLEN/8, x6, x7, x1) + +inst_652: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0f6 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0f6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78f6; op2val:0xf8f6; + valaddr_reg:x4; val_offset:1258*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1258*FLEN/8, x6, x7, x1) + +inst_653: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0f6 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0f6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78f6; op2val:0xf8f6; + valaddr_reg:x4; val_offset:1260*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1260*FLEN/8, x6, x7, x1) + +inst_654: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0f6 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0f6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78f6; op2val:0xf8f6; + valaddr_reg:x4; val_offset:1262*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1262*FLEN/8, x6, x7, x1) + +inst_655: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x13d and fs2 == 1 and fe2 == 0x1c and fm2 == 0x13d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x713d; op2val:0xf13d; + valaddr_reg:x4; val_offset:1264*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1264*FLEN/8, x6, x7, x1) + +inst_656: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x13d and fs2 == 1 and fe2 == 0x1c and fm2 == 0x13d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x713d; op2val:0xf13d; + valaddr_reg:x4; val_offset:1266*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1266*FLEN/8, x6, x7, x1) +RVTEST_SIGBASE(x7,signature_x7_5) + +inst_657: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x13d and fs2 == 1 and fe2 == 0x1c and fm2 == 0x13d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x713d; op2val:0xf13d; + valaddr_reg:x4; val_offset:1268*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1268*FLEN/8, x6, x7, x1) + +inst_658: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x13d and fs2 == 1 and fe2 == 0x1c and fm2 == 0x13d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x713d; op2val:0xf13d; + valaddr_reg:x4; val_offset:1270*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1270*FLEN/8, x6, x7, x1) + +inst_659: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x13d and fs2 == 1 and fe2 == 0x1c and fm2 == 0x13d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x713d; op2val:0xf13d; + valaddr_reg:x4; val_offset:1272*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1272*FLEN/8, x6, x7, x1) + +inst_660: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a1 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x0a1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x74a1; op2val:0xf4a1; + valaddr_reg:x4; val_offset:1274*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1274*FLEN/8, x6, x7, x1) + +inst_661: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a1 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x0a1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x74a1; op2val:0xf4a1; + valaddr_reg:x4; val_offset:1276*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1276*FLEN/8, x6, x7, x1) + +inst_662: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a1 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x0a1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x74a1; op2val:0xf4a1; + valaddr_reg:x4; val_offset:1278*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1278*FLEN/8, x6, x7, x1) + +inst_663: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a1 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x0a1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x74a1; op2val:0xf4a1; + valaddr_reg:x4; val_offset:1280*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1280*FLEN/8, x6, x7, x1) + +inst_664: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a1 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x0a1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x74a1; op2val:0xf4a1; + valaddr_reg:x4; val_offset:1282*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1282*FLEN/8, x6, x7, x1) + +inst_665: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x062 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x062 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7862; op2val:0xf862; + valaddr_reg:x4; val_offset:1284*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1284*FLEN/8, x6, x7, x1) + +inst_666: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x062 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x062 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7862; op2val:0xf862; + valaddr_reg:x4; val_offset:1286*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1286*FLEN/8, x6, x7, x1) + +inst_667: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x062 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x062 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7862; op2val:0xf862; + valaddr_reg:x4; val_offset:1288*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1288*FLEN/8, x6, x7, x1) + +inst_668: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x062 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x062 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7862; op2val:0xf862; + valaddr_reg:x4; val_offset:1290*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1290*FLEN/8, x6, x7, x1) + +inst_669: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x062 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x062 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7862; op2val:0xf862; + valaddr_reg:x4; val_offset:1292*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1292*FLEN/8, x6, x7, x1) + +inst_670: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a5 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3a5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77a5; op2val:0xf7a5; + valaddr_reg:x4; val_offset:1294*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1294*FLEN/8, x6, x7, x1) + +inst_671: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a5 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3a5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77a5; op2val:0xf7a5; + valaddr_reg:x4; val_offset:1296*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1296*FLEN/8, x6, x7, x1) + +inst_672: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a5 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3a5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77a5; op2val:0xf7a5; + valaddr_reg:x4; val_offset:1298*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1298*FLEN/8, x6, x7, x1) + +inst_673: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a5 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3a5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77a5; op2val:0xf7a5; + valaddr_reg:x4; val_offset:1300*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1300*FLEN/8, x6, x7, x1) + +inst_674: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a5 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3a5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77a5; op2val:0xf7a5; + valaddr_reg:x4; val_offset:1302*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1302*FLEN/8, x6, x7, x1) + +inst_675: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x22c and fs2 == 1 and fe2 == 0x1a and fm2 == 0x22c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6a2c; op2val:0xea2c; + valaddr_reg:x4; val_offset:1304*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1304*FLEN/8, x6, x7, x1) + +inst_676: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x22c and fs2 == 1 and fe2 == 0x1a and fm2 == 0x22c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6a2c; op2val:0xea2c; + valaddr_reg:x4; val_offset:1306*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1306*FLEN/8, x6, x7, x1) + +inst_677: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x22c and fs2 == 1 and fe2 == 0x1a and fm2 == 0x22c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6a2c; op2val:0xea2c; + valaddr_reg:x4; val_offset:1308*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1308*FLEN/8, x6, x7, x1) + +inst_678: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x22c and fs2 == 1 and fe2 == 0x1a and fm2 == 0x22c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6a2c; op2val:0xea2c; + valaddr_reg:x4; val_offset:1310*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1310*FLEN/8, x6, x7, x1) + +inst_679: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x22c and fs2 == 1 and fe2 == 0x1a and fm2 == 0x22c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6a2c; op2val:0xea2c; + valaddr_reg:x4; val_offset:1312*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1312*FLEN/8, x6, x7, x1) + +inst_680: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x782e; op2val:0xf82e; + valaddr_reg:x4; val_offset:1314*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1314*FLEN/8, x6, x7, x1) + +inst_681: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x782e; op2val:0xf82e; + valaddr_reg:x4; val_offset:1316*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1316*FLEN/8, x6, x7, x1) + +inst_682: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x782e; op2val:0xf82e; + valaddr_reg:x4; val_offset:1318*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1318*FLEN/8, x6, x7, x1) + +inst_683: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x782e; op2val:0xf82e; + valaddr_reg:x4; val_offset:1320*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1320*FLEN/8, x6, x7, x1) + +inst_684: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x782e; op2val:0xf82e; + valaddr_reg:x4; val_offset:1322*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1322*FLEN/8, x6, x7, x1) + +inst_685: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x272 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x272 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7672; op2val:0xf672; + valaddr_reg:x4; val_offset:1324*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1324*FLEN/8, x6, x7, x1) + +inst_686: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x272 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x272 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7672; op2val:0xf672; + valaddr_reg:x4; val_offset:1326*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1326*FLEN/8, x6, x7, x1) + +inst_687: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x272 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x272 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7672; op2val:0xf672; + valaddr_reg:x4; val_offset:1328*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1328*FLEN/8, x6, x7, x1) + +inst_688: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x272 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x272 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7672; op2val:0xf672; + valaddr_reg:x4; val_offset:1330*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1330*FLEN/8, x6, x7, x1) + +inst_689: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x272 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x272 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7672; op2val:0xf672; + valaddr_reg:x4; val_offset:1332*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1332*FLEN/8, x6, x7, x1) + +inst_690: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a1 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2a1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x76a1; op2val:0xf6a1; + valaddr_reg:x4; val_offset:1334*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1334*FLEN/8, x6, x7, x1) + +inst_691: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a1 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2a1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x76a1; op2val:0xf6a1; + valaddr_reg:x4; val_offset:1336*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1336*FLEN/8, x6, x7, x1) + +inst_692: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a1 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2a1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x76a1; op2val:0xf6a1; + valaddr_reg:x4; val_offset:1338*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1338*FLEN/8, x6, x7, x1) + +inst_693: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a1 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2a1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x76a1; op2val:0xf6a1; + valaddr_reg:x4; val_offset:1340*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1340*FLEN/8, x6, x7, x1) + +inst_694: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a1 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2a1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x76a1; op2val:0xf6a1; + valaddr_reg:x4; val_offset:1342*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1342*FLEN/8, x6, x7, x1) + +inst_695: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x344 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x344 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b44; op2val:0xfb44; + valaddr_reg:x4; val_offset:1344*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1344*FLEN/8, x6, x7, x1) + +inst_696: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x344 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x344 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b44; op2val:0xfb44; + valaddr_reg:x4; val_offset:1346*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1346*FLEN/8, x6, x7, x1) + +inst_697: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x344 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x344 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b44; op2val:0xfb44; + valaddr_reg:x4; val_offset:1348*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1348*FLEN/8, x6, x7, x1) + +inst_698: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x344 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x344 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b44; op2val:0xfb44; + valaddr_reg:x4; val_offset:1350*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1350*FLEN/8, x6, x7, x1) + +inst_699: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x344 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x344 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b44; op2val:0xfb44; + valaddr_reg:x4; val_offset:1352*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1352*FLEN/8, x6, x7, x1) + +inst_700: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2b9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab9; op2val:0xfab9; + valaddr_reg:x4; val_offset:1354*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1354*FLEN/8, x6, x7, x1) + +inst_701: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2b9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab9; op2val:0xfab9; + valaddr_reg:x4; val_offset:1356*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1356*FLEN/8, x6, x7, x1) + +inst_702: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2b9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab9; op2val:0xfab9; + valaddr_reg:x4; val_offset:1358*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1358*FLEN/8, x6, x7, x1) + +inst_703: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2b9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab9; op2val:0xfab9; + valaddr_reg:x4; val_offset:1360*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1360*FLEN/8, x6, x7, x1) + +inst_704: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2b9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab9; op2val:0xfab9; + valaddr_reg:x4; val_offset:1362*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1362*FLEN/8, x6, x7, x1) + +inst_705: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x17e and fs2 == 1 and fe2 == 0x1d and fm2 == 0x17e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x757e; op2val:0xf57e; + valaddr_reg:x4; val_offset:1364*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1364*FLEN/8, x6, x7, x1) + +inst_706: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x17e and fs2 == 1 and fe2 == 0x1d and fm2 == 0x17e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x757e; op2val:0xf57e; + valaddr_reg:x4; val_offset:1366*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1366*FLEN/8, x6, x7, x1) + +inst_707: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x17e and fs2 == 1 and fe2 == 0x1d and fm2 == 0x17e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x757e; op2val:0xf57e; + valaddr_reg:x4; val_offset:1368*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1368*FLEN/8, x6, x7, x1) + +inst_708: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x17e and fs2 == 1 and fe2 == 0x1d and fm2 == 0x17e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x757e; op2val:0xf57e; + valaddr_reg:x4; val_offset:1370*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1370*FLEN/8, x6, x7, x1) + +inst_709: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x17e and fs2 == 1 and fe2 == 0x1d and fm2 == 0x17e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x757e; op2val:0xf57e; + valaddr_reg:x4; val_offset:1372*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1372*FLEN/8, x6, x7, x1) + +inst_710: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x198 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x198 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7998; op2val:0xf998; + valaddr_reg:x4; val_offset:1374*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1374*FLEN/8, x6, x7, x1) + +inst_711: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x198 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x198 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7998; op2val:0xf998; + valaddr_reg:x4; val_offset:1376*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1376*FLEN/8, x6, x7, x1) + +inst_712: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x198 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x198 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7998; op2val:0xf998; + valaddr_reg:x4; val_offset:1378*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1378*FLEN/8, x6, x7, x1) + +inst_713: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x198 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x198 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7998; op2val:0xf998; + valaddr_reg:x4; val_offset:1380*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1380*FLEN/8, x6, x7, x1) + +inst_714: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x198 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x198 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7998; op2val:0xf998; + valaddr_reg:x4; val_offset:1382*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1382*FLEN/8, x6, x7, x1) + +inst_715: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d4 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x0d4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x74d4; op2val:0xf4d4; + valaddr_reg:x4; val_offset:1384*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1384*FLEN/8, x6, x7, x1) + +inst_716: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d4 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x0d4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x74d4; op2val:0xf4d4; + valaddr_reg:x4; val_offset:1386*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1386*FLEN/8, x6, x7, x1) + +inst_717: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d4 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x0d4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x74d4; op2val:0xf4d4; + valaddr_reg:x4; val_offset:1388*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1388*FLEN/8, x6, x7, x1) + +inst_718: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d4 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x0d4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x74d4; op2val:0xf4d4; + valaddr_reg:x4; val_offset:1390*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1390*FLEN/8, x6, x7, x1) + +inst_719: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d4 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x0d4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x74d4; op2val:0xf4d4; + valaddr_reg:x4; val_offset:1392*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1392*FLEN/8, x6, x7, x1) + +inst_720: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x326 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x326 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b26; op2val:0xfb26; + valaddr_reg:x4; val_offset:1394*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1394*FLEN/8, x6, x7, x1) + +inst_721: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x326 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x326 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b26; op2val:0xfb26; + valaddr_reg:x4; val_offset:1396*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1396*FLEN/8, x6, x7, x1) + +inst_722: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x326 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x326 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b26; op2val:0xfb26; + valaddr_reg:x4; val_offset:1398*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1398*FLEN/8, x6, x7, x1) + +inst_723: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x326 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x326 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b26; op2val:0xfb26; + valaddr_reg:x4; val_offset:1400*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1400*FLEN/8, x6, x7, x1) + +inst_724: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x326 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x326 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b26; op2val:0xfb26; + valaddr_reg:x4; val_offset:1402*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1402*FLEN/8, x6, x7, x1) + +inst_725: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x102 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x102 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7902; op2val:0xf902; + valaddr_reg:x4; val_offset:1404*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1404*FLEN/8, x6, x7, x1) + +inst_726: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x102 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x102 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7902; op2val:0xf902; + valaddr_reg:x4; val_offset:1406*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1406*FLEN/8, x6, x7, x1) + +inst_727: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x102 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x102 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7902; op2val:0xf902; + valaddr_reg:x4; val_offset:1408*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1408*FLEN/8, x6, x7, x1) + +inst_728: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x102 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x102 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7902; op2val:0xf902; + valaddr_reg:x4; val_offset:1410*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1410*FLEN/8, x6, x7, x1) + +inst_729: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x102 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x102 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7902; op2val:0xf902; + valaddr_reg:x4; val_offset:1412*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1412*FLEN/8, x6, x7, x1) + +inst_730: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ca and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ca and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bca; op2val:0xfbca; + valaddr_reg:x4; val_offset:1414*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1414*FLEN/8, x6, x7, x1) + +inst_731: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ca and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ca and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bca; op2val:0xfbca; + valaddr_reg:x4; val_offset:1416*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1416*FLEN/8, x6, x7, x1) + +inst_732: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ca and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ca and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bca; op2val:0xfbca; + valaddr_reg:x4; val_offset:1418*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1418*FLEN/8, x6, x7, x1) + +inst_733: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ca and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ca and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bca; op2val:0xfbca; + valaddr_reg:x4; val_offset:1420*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1420*FLEN/8, x6, x7, x1) + +inst_734: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ca and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ca and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bca; op2val:0xfbca; + valaddr_reg:x4; val_offset:1422*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1422*FLEN/8, x6, x7, x1) + +inst_735: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x036 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x036 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c36; op2val:0xec36; + valaddr_reg:x4; val_offset:1424*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1424*FLEN/8, x6, x7, x1) + +inst_736: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x036 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x036 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c36; op2val:0xec36; + valaddr_reg:x4; val_offset:1426*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1426*FLEN/8, x6, x7, x1) + +inst_737: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x036 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x036 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c36; op2val:0xec36; + valaddr_reg:x4; val_offset:1428*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1428*FLEN/8, x6, x7, x1) + +inst_738: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x036 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x036 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c36; op2val:0xec36; + valaddr_reg:x4; val_offset:1430*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1430*FLEN/8, x6, x7, x1) + +inst_739: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x036 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x036 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c36; op2val:0xec36; + valaddr_reg:x4; val_offset:1432*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1432*FLEN/8, x6, x7, x1) + +inst_740: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79fe; op2val:0xf9fe; + valaddr_reg:x4; val_offset:1434*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1434*FLEN/8, x6, x7, x1) + +inst_741: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1fe and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79fe; op2val:0xf9fe; + valaddr_reg:x4; val_offset:1436*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1436*FLEN/8, x6, x7, x1) + +inst_742: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1fe and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79fe; op2val:0xf9fe; + valaddr_reg:x4; val_offset:1438*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1438*FLEN/8, x6, x7, x1) + +inst_743: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1fe and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79fe; op2val:0xf9fe; + valaddr_reg:x4; val_offset:1440*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1440*FLEN/8, x6, x7, x1) + +inst_744: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1fe and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79fe; op2val:0xf9fe; + valaddr_reg:x4; val_offset:1442*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1442*FLEN/8, x6, x7, x1) + +inst_745: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x006 and fs2 == 1 and fe2 == 0x18 and fm2 == 0x006 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6006; op2val:0xe006; + valaddr_reg:x4; val_offset:1444*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1444*FLEN/8, x6, x7, x1) + +inst_746: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x006 and fs2 == 1 and fe2 == 0x18 and fm2 == 0x006 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6006; op2val:0xe006; + valaddr_reg:x4; val_offset:1446*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1446*FLEN/8, x6, x7, x1) + +inst_747: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x006 and fs2 == 1 and fe2 == 0x18 and fm2 == 0x006 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6006; op2val:0xe006; + valaddr_reg:x4; val_offset:1448*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1448*FLEN/8, x6, x7, x1) + +inst_748: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x006 and fs2 == 1 and fe2 == 0x18 and fm2 == 0x006 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6006; op2val:0xe006; + valaddr_reg:x4; val_offset:1450*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1450*FLEN/8, x6, x7, x1) + +inst_749: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x006 and fs2 == 1 and fe2 == 0x18 and fm2 == 0x006 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6006; op2val:0xe006; + valaddr_reg:x4; val_offset:1452*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1452*FLEN/8, x6, x7, x1) + +inst_750: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x026 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x026 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7826; op2val:0xf826; + valaddr_reg:x4; val_offset:1454*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1454*FLEN/8, x6, x7, x1) + +inst_751: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x026 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x026 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7826; op2val:0xf826; + valaddr_reg:x4; val_offset:1456*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1456*FLEN/8, x6, x7, x1) + +inst_752: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x026 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x026 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7826; op2val:0xf826; + valaddr_reg:x4; val_offset:1458*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1458*FLEN/8, x6, x7, x1) + +inst_753: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x026 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x026 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7826; op2val:0xf826; + valaddr_reg:x4; val_offset:1460*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1460*FLEN/8, x6, x7, x1) + +inst_754: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x026 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x026 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7826; op2val:0xf826; + valaddr_reg:x4; val_offset:1462*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1462*FLEN/8, x6, x7, x1) + +inst_755: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d0 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3d0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77d0; op2val:0xf7d0; + valaddr_reg:x4; val_offset:1464*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1464*FLEN/8, x6, x7, x1) + +inst_756: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d0 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3d0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77d0; op2val:0xf7d0; + valaddr_reg:x4; val_offset:1466*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1466*FLEN/8, x6, x7, x1) + +inst_757: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d0 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3d0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77d0; op2val:0xf7d0; + valaddr_reg:x4; val_offset:1468*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1468*FLEN/8, x6, x7, x1) + +inst_758: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d0 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3d0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77d0; op2val:0xf7d0; + valaddr_reg:x4; val_offset:1470*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1470*FLEN/8, x6, x7, x1) + +inst_759: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d0 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3d0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77d0; op2val:0xf7d0; + valaddr_reg:x4; val_offset:1472*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1472*FLEN/8, x6, x7, x1) + +inst_760: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x16e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x16e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x796e; op2val:0xf96e; + valaddr_reg:x4; val_offset:1474*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1474*FLEN/8, x6, x7, x1) + +inst_761: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x16e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x16e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x796e; op2val:0xf96e; + valaddr_reg:x4; val_offset:1476*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1476*FLEN/8, x6, x7, x1) + +inst_762: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x16e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x16e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x796e; op2val:0xf96e; + valaddr_reg:x4; val_offset:1478*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1478*FLEN/8, x6, x7, x1) + +inst_763: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x16e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x16e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x796e; op2val:0xf96e; + valaddr_reg:x4; val_offset:1480*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1480*FLEN/8, x6, x7, x1) + +inst_764: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x16e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x16e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x796e; op2val:0xf96e; + valaddr_reg:x4; val_offset:1482*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1482*FLEN/8, x6, x7, x1) + +inst_765: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1e3 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x1e3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x75e3; op2val:0xf5e3; + valaddr_reg:x4; val_offset:1484*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1484*FLEN/8, x6, x7, x1) + +inst_766: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1e3 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x1e3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x75e3; op2val:0xf5e3; + valaddr_reg:x4; val_offset:1486*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1486*FLEN/8, x6, x7, x1) + +inst_767: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1e3 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x1e3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x75e3; op2val:0xf5e3; + valaddr_reg:x4; val_offset:1488*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1488*FLEN/8, x6, x7, x1) + +inst_768: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1e3 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x1e3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x75e3; op2val:0xf5e3; + valaddr_reg:x4; val_offset:1490*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1490*FLEN/8, x6, x7, x1) + +inst_769: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1e3 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x1e3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x75e3; op2val:0xf5e3; + valaddr_reg:x4; val_offset:1492*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1492*FLEN/8, x6, x7, x1) + +inst_770: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x02c and fs2 == 1 and fe2 == 0x1d and fm2 == 0x02c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x742c; op2val:0xf42c; + valaddr_reg:x4; val_offset:1494*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1494*FLEN/8, x6, x7, x1) + +inst_771: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x02c and fs2 == 1 and fe2 == 0x1d and fm2 == 0x02c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x742c; op2val:0xf42c; + valaddr_reg:x4; val_offset:1496*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1496*FLEN/8, x6, x7, x1) + +inst_772: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x02c and fs2 == 1 and fe2 == 0x1d and fm2 == 0x02c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x742c; op2val:0xf42c; + valaddr_reg:x4; val_offset:1498*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1498*FLEN/8, x6, x7, x1) + +inst_773: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x02c and fs2 == 1 and fe2 == 0x1d and fm2 == 0x02c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x742c; op2val:0xf42c; + valaddr_reg:x4; val_offset:1500*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1500*FLEN/8, x6, x7, x1) + +inst_774: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x02c and fs2 == 1 and fe2 == 0x1d and fm2 == 0x02c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x742c; op2val:0xf42c; + valaddr_reg:x4; val_offset:1502*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1502*FLEN/8, x6, x7, x1) + +inst_775: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e5 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2e5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x76e5; op2val:0xf6e5; + valaddr_reg:x4; val_offset:1504*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1504*FLEN/8, x6, x7, x1) + +inst_776: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e5 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2e5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x76e5; op2val:0xf6e5; + valaddr_reg:x4; val_offset:1506*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1506*FLEN/8, x6, x7, x1) + +inst_777: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e5 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2e5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x76e5; op2val:0xf6e5; + valaddr_reg:x4; val_offset:1508*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1508*FLEN/8, x6, x7, x1) + +inst_778: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e5 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2e5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x76e5; op2val:0xf6e5; + valaddr_reg:x4; val_offset:1510*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1510*FLEN/8, x6, x7, x1) + +inst_779: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e5 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2e5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x76e5; op2val:0xf6e5; + valaddr_reg:x4; val_offset:1512*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1512*FLEN/8, x6, x7, x1) + +inst_780: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x015 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x015 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c15; op2val:0xec15; + valaddr_reg:x4; val_offset:1514*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1514*FLEN/8, x6, x7, x1) + +inst_781: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x015 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x015 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c15; op2val:0xec15; + valaddr_reg:x4; val_offset:1516*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1516*FLEN/8, x6, x7, x1) + +inst_782: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x015 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x015 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c15; op2val:0xec15; + valaddr_reg:x4; val_offset:1518*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1518*FLEN/8, x6, x7, x1) + +inst_783: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x015 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x015 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c15; op2val:0xec15; + valaddr_reg:x4; val_offset:1520*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1520*FLEN/8, x6, x7, x1) + +inst_784: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x015 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x015 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c15; op2val:0xec15; + valaddr_reg:x4; val_offset:1522*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1522*FLEN/8, x6, x7, x1) +RVTEST_SIGBASE(x7,signature_x7_6) + +inst_785: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x19d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x799d; op2val:0xf99d; + valaddr_reg:x4; val_offset:1524*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1524*FLEN/8, x6, x7, x1) + +inst_786: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x19d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x799d; op2val:0xf99d; + valaddr_reg:x4; val_offset:1526*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1526*FLEN/8, x6, x7, x1) + +inst_787: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x19d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x799d; op2val:0xf99d; + valaddr_reg:x4; val_offset:1528*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1528*FLEN/8, x6, x7, x1) + +inst_788: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x19d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x799d; op2val:0xf99d; + valaddr_reg:x4; val_offset:1530*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1530*FLEN/8, x6, x7, x1) + +inst_789: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x19d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x799d; op2val:0xf99d; + valaddr_reg:x4; val_offset:1532*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1532*FLEN/8, x6, x7, x1) + +inst_790: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x338 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x338 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7738; op2val:0xf738; + valaddr_reg:x4; val_offset:1534*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1534*FLEN/8, x6, x7, x1) + +inst_791: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x338 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x338 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7738; op2val:0xf738; + valaddr_reg:x4; val_offset:1536*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1536*FLEN/8, x6, x7, x1) + +inst_792: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x338 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x338 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7738; op2val:0xf738; + valaddr_reg:x4; val_offset:1538*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1538*FLEN/8, x6, x7, x1) + +inst_793: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x338 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x338 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7738; op2val:0xf738; + valaddr_reg:x4; val_offset:1540*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1540*FLEN/8, x6, x7, x1) + +inst_794: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x338 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x338 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7738; op2val:0xf738; + valaddr_reg:x4; val_offset:1542*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1542*FLEN/8, x6, x7, x1) + +inst_795: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x39b and fs2 == 1 and fe2 == 0x1b and fm2 == 0x39b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f9b; op2val:0xef9b; + valaddr_reg:x4; val_offset:1544*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1544*FLEN/8, x6, x7, x1) + +inst_796: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x39b and fs2 == 1 and fe2 == 0x1b and fm2 == 0x39b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f9b; op2val:0xef9b; + valaddr_reg:x4; val_offset:1546*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1546*FLEN/8, x6, x7, x1) + +inst_797: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x39b and fs2 == 1 and fe2 == 0x1b and fm2 == 0x39b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f9b; op2val:0xef9b; + valaddr_reg:x4; val_offset:1548*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1548*FLEN/8, x6, x7, x1) + +inst_798: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x39b and fs2 == 1 and fe2 == 0x1b and fm2 == 0x39b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f9b; op2val:0xef9b; + valaddr_reg:x4; val_offset:1550*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1550*FLEN/8, x6, x7, x1) + +inst_799: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x39b and fs2 == 1 and fe2 == 0x1b and fm2 == 0x39b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f9b; op2val:0xef9b; + valaddr_reg:x4; val_offset:1552*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1552*FLEN/8, x6, x7, x1) + +inst_800: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2a0 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x2a0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x72a0; op2val:0xf2a0; + valaddr_reg:x4; val_offset:1554*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1554*FLEN/8, x6, x7, x1) + +inst_801: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2a0 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x2a0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x72a0; op2val:0xf2a0; + valaddr_reg:x4; val_offset:1556*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1556*FLEN/8, x6, x7, x1) + +inst_802: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2a0 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x2a0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x72a0; op2val:0xf2a0; + valaddr_reg:x4; val_offset:1558*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1558*FLEN/8, x6, x7, x1) + +inst_803: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2a0 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x2a0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x72a0; op2val:0xf2a0; + valaddr_reg:x4; val_offset:1560*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1560*FLEN/8, x6, x7, x1) + +inst_804: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2a0 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x2a0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x72a0; op2val:0xf2a0; + valaddr_reg:x4; val_offset:1562*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1562*FLEN/8, x6, x7, x1) + +inst_805: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x394 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x394 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b94; op2val:0xfb94; + valaddr_reg:x4; val_offset:1564*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1564*FLEN/8, x6, x7, x1) + +inst_806: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x394 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x394 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b94; op2val:0xfb94; + valaddr_reg:x4; val_offset:1566*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1566*FLEN/8, x6, x7, x1) + +inst_807: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x394 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x394 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b94; op2val:0xfb94; + valaddr_reg:x4; val_offset:1568*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1568*FLEN/8, x6, x7, x1) + +inst_808: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x394 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x394 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b94; op2val:0xfb94; + valaddr_reg:x4; val_offset:1570*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1570*FLEN/8, x6, x7, x1) + +inst_809: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x394 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x394 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b94; op2val:0xfb94; + valaddr_reg:x4; val_offset:1572*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1572*FLEN/8, x6, x7, x1) + +inst_810: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0ae and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0a6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x70ae; op2val:0xf0a6; + valaddr_reg:x4; val_offset:1574*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1574*FLEN/8, x6, x7, x1) + +inst_811: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0ae and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0a6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x70ae; op2val:0xf0a6; + valaddr_reg:x4; val_offset:1576*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1576*FLEN/8, x6, x7, x1) + +inst_812: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0ae and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0a6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x70ae; op2val:0xf0a6; + valaddr_reg:x4; val_offset:1578*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1578*FLEN/8, x6, x7, x1) + +inst_813: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0ae and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0a6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x70ae; op2val:0xf0a6; + valaddr_reg:x4; val_offset:1580*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1580*FLEN/8, x6, x7, x1) + +inst_814: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0ae and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0a6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x70ae; op2val:0xf0a6; + valaddr_reg:x4; val_offset:1582*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1582*FLEN/8, x6, x7, x1) + +inst_815: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x20b and fs2 == 1 and fe2 == 0x1d and fm2 == 0x207 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x760b; op2val:0xf607; + valaddr_reg:x4; val_offset:1584*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1584*FLEN/8, x6, x7, x1) + +inst_816: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x20b and fs2 == 1 and fe2 == 0x1d and fm2 == 0x207 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x760b; op2val:0xf607; + valaddr_reg:x4; val_offset:1586*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1586*FLEN/8, x6, x7, x1) + +inst_817: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x20b and fs2 == 1 and fe2 == 0x1d and fm2 == 0x207 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x760b; op2val:0xf607; + valaddr_reg:x4; val_offset:1588*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1588*FLEN/8, x6, x7, x1) + +inst_818: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x20b and fs2 == 1 and fe2 == 0x1d and fm2 == 0x207 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x760b; op2val:0xf607; + valaddr_reg:x4; val_offset:1590*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1590*FLEN/8, x6, x7, x1) + +inst_819: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x20b and fs2 == 1 and fe2 == 0x1d and fm2 == 0x207 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x760b; op2val:0xf607; + valaddr_reg:x4; val_offset:1592*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1592*FLEN/8, x6, x7, x1) + +inst_820: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0d7 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0cf and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x70d7; op2val:0xf0cf; + valaddr_reg:x4; val_offset:1594*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1594*FLEN/8, x6, x7, x1) + +inst_821: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0d7 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0cf and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x70d7; op2val:0xf0cf; + valaddr_reg:x4; val_offset:1596*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1596*FLEN/8, x6, x7, x1) + +inst_822: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0d7 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0cf and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x70d7; op2val:0xf0cf; + valaddr_reg:x4; val_offset:1598*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1598*FLEN/8, x6, x7, x1) + +inst_823: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0d7 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0cf and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x70d7; op2val:0xf0cf; + valaddr_reg:x4; val_offset:1600*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1600*FLEN/8, x6, x7, x1) + +inst_824: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0d7 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0cf and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x70d7; op2val:0xf0cf; + valaddr_reg:x4; val_offset:1602*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1602*FLEN/8, x6, x7, x1) + +inst_825: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3dc and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3da and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bdc; op2val:0xfbda; + valaddr_reg:x4; val_offset:1604*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1604*FLEN/8, x6, x7, x1) + +inst_826: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3dc and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3da and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bdc; op2val:0xfbda; + valaddr_reg:x4; val_offset:1606*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1606*FLEN/8, x6, x7, x1) + +inst_827: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3dc and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3da and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bdc; op2val:0xfbda; + valaddr_reg:x4; val_offset:1608*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1608*FLEN/8, x6, x7, x1) + +inst_828: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3dc and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3da and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bdc; op2val:0xfbda; + valaddr_reg:x4; val_offset:1610*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1610*FLEN/8, x6, x7, x1) + +inst_829: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3dc and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3da and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bdc; op2val:0xfbda; + valaddr_reg:x4; val_offset:1612*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1612*FLEN/8, x6, x7, x1) + +inst_830: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x27d and fs2 == 1 and fe2 == 0x1d and fm2 == 0x279 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x767d; op2val:0xf679; + valaddr_reg:x4; val_offset:1614*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1614*FLEN/8, x6, x7, x1) + +inst_831: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x27d and fs2 == 1 and fe2 == 0x1d and fm2 == 0x279 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x767d; op2val:0xf679; + valaddr_reg:x4; val_offset:1616*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1616*FLEN/8, x6, x7, x1) + +inst_832: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x27d and fs2 == 1 and fe2 == 0x1d and fm2 == 0x279 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x767d; op2val:0xf679; + valaddr_reg:x4; val_offset:1618*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1618*FLEN/8, x6, x7, x1) + +inst_833: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x27d and fs2 == 1 and fe2 == 0x1d and fm2 == 0x279 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x767d; op2val:0xf679; + valaddr_reg:x4; val_offset:1620*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1620*FLEN/8, x6, x7, x1) + +inst_834: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x27d and fs2 == 1 and fe2 == 0x1d and fm2 == 0x279 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x767d; op2val:0xf679; + valaddr_reg:x4; val_offset:1622*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1622*FLEN/8, x6, x7, x1) + +inst_835: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x304 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x302 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b04; op2val:0xfb02; + valaddr_reg:x4; val_offset:1624*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1624*FLEN/8, x6, x7, x1) + +inst_836: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x304 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x302 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b04; op2val:0xfb02; + valaddr_reg:x4; val_offset:1626*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1626*FLEN/8, x6, x7, x1) + +inst_837: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x304 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x302 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b04; op2val:0xfb02; + valaddr_reg:x4; val_offset:1628*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1628*FLEN/8, x6, x7, x1) + +inst_838: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x304 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x302 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b04; op2val:0xfb02; + valaddr_reg:x4; val_offset:1630*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1630*FLEN/8, x6, x7, x1) + +inst_839: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x304 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x302 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b04; op2val:0xfb02; + valaddr_reg:x4; val_offset:1632*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1632*FLEN/8, x6, x7, x1) + +inst_840: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x355 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x353 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b55; op2val:0xfb53; + valaddr_reg:x4; val_offset:1634*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1634*FLEN/8, x6, x7, x1) + +inst_841: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x355 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x353 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b55; op2val:0xfb53; + valaddr_reg:x4; val_offset:1636*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1636*FLEN/8, x6, x7, x1) + +inst_842: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x355 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x353 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b55; op2val:0xfb53; + valaddr_reg:x4; val_offset:1638*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1638*FLEN/8, x6, x7, x1) + +inst_843: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x355 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x353 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b55; op2val:0xfb53; + valaddr_reg:x4; val_offset:1640*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1640*FLEN/8, x6, x7, x1) + +inst_844: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x355 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x353 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b55; op2val:0xfb53; + valaddr_reg:x4; val_offset:1642*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1642*FLEN/8, x6, x7, x1) + +inst_845: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77f8; op2val:0xf7fc; + valaddr_reg:x4; val_offset:1644*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1644*FLEN/8, x6, x7, x1) + +inst_846: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3fc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77f8; op2val:0xf7fc; + valaddr_reg:x4; val_offset:1646*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1646*FLEN/8, x6, x7, x1) + +inst_847: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3fc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77f8; op2val:0xf7fc; + valaddr_reg:x4; val_offset:1648*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1648*FLEN/8, x6, x7, x1) + +inst_848: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3fc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77f8; op2val:0xf7fc; + valaddr_reg:x4; val_offset:1650*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1650*FLEN/8, x6, x7, x1) + +inst_849: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3fc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77f8; op2val:0xf7fc; + valaddr_reg:x4; val_offset:1652*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1652*FLEN/8, x6, x7, x1) + +inst_850: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x15d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x795b; op2val:0xf95d; + valaddr_reg:x4; val_offset:1654*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1654*FLEN/8, x6, x7, x1) + +inst_851: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x15d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x795b; op2val:0xf95d; + valaddr_reg:x4; val_offset:1656*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1656*FLEN/8, x6, x7, x1) + +inst_852: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x15d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x795b; op2val:0xf95d; + valaddr_reg:x4; val_offset:1658*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1658*FLEN/8, x6, x7, x1) + +inst_853: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x15d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x795b; op2val:0xf95d; + valaddr_reg:x4; val_offset:1660*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1660*FLEN/8, x6, x7, x1) + +inst_854: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x15d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x795b; op2val:0xf95d; + valaddr_reg:x4; val_offset:1662*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1662*FLEN/8, x6, x7, x1) + +inst_855: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0e2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78e0; op2val:0xf8e2; + valaddr_reg:x4; val_offset:1664*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1664*FLEN/8, x6, x7, x1) + +inst_856: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0e2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78e0; op2val:0xf8e2; + valaddr_reg:x4; val_offset:1666*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1666*FLEN/8, x6, x7, x1) + +inst_857: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0e2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78e0; op2val:0xf8e2; + valaddr_reg:x4; val_offset:1668*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1668*FLEN/8, x6, x7, x1) + +inst_858: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0e2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78e0; op2val:0xf8e2; + valaddr_reg:x4; val_offset:1670*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1670*FLEN/8, x6, x7, x1) + +inst_859: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0e2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78e0; op2val:0xf8e2; + valaddr_reg:x4; val_offset:1672*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1672*FLEN/8, x6, x7, x1) + +inst_860: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x170 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x174 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7570; op2val:0xf574; + valaddr_reg:x4; val_offset:1674*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1674*FLEN/8, x6, x7, x1) + +inst_861: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x170 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x174 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7570; op2val:0xf574; + valaddr_reg:x4; val_offset:1676*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1676*FLEN/8, x6, x7, x1) + +inst_862: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x170 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x174 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7570; op2val:0xf574; + valaddr_reg:x4; val_offset:1678*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1678*FLEN/8, x6, x7, x1) + +inst_863: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x170 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x174 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7570; op2val:0xf574; + valaddr_reg:x4; val_offset:1680*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1680*FLEN/8, x6, x7, x1) + +inst_864: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x170 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x174 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7570; op2val:0xf574; + valaddr_reg:x4; val_offset:1682*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1682*FLEN/8, x6, x7, x1) + +inst_865: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x330 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x332 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b30; op2val:0xfb32; + valaddr_reg:x4; val_offset:1684*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1684*FLEN/8, x6, x7, x1) + +inst_866: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x330 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x332 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b30; op2val:0xfb32; + valaddr_reg:x4; val_offset:1686*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1686*FLEN/8, x6, x7, x1) + +inst_867: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x330 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x332 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b30; op2val:0xfb32; + valaddr_reg:x4; val_offset:1688*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1688*FLEN/8, x6, x7, x1) + +inst_868: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x330 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x332 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b30; op2val:0xfb32; + valaddr_reg:x4; val_offset:1690*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1690*FLEN/8, x6, x7, x1) + +inst_869: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x330 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x332 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b30; op2val:0xfb32; + valaddr_reg:x4; val_offset:1692*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1692*FLEN/8, x6, x7, x1) + +inst_870: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x08a and fs2 == 1 and fe2 == 0x1a and fm2 == 0x0aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x688a; op2val:0xe8aa; + valaddr_reg:x4; val_offset:1694*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1694*FLEN/8, x6, x7, x1) + +inst_871: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x08a and fs2 == 1 and fe2 == 0x1a and fm2 == 0x0aa and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x688a; op2val:0xe8aa; + valaddr_reg:x4; val_offset:1696*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1696*FLEN/8, x6, x7, x1) + +inst_872: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x08a and fs2 == 1 and fe2 == 0x1a and fm2 == 0x0aa and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x688a; op2val:0xe8aa; + valaddr_reg:x4; val_offset:1698*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1698*FLEN/8, x6, x7, x1) + +inst_873: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x08a and fs2 == 1 and fe2 == 0x1a and fm2 == 0x0aa and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x688a; op2val:0xe8aa; + valaddr_reg:x4; val_offset:1700*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1700*FLEN/8, x6, x7, x1) + +inst_874: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x08a and fs2 == 1 and fe2 == 0x1a and fm2 == 0x0aa and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x688a; op2val:0xe8aa; + valaddr_reg:x4; val_offset:1702*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1702*FLEN/8, x6, x7, x1) + +inst_875: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x01b and fs2 == 1 and fe2 == 0x1d and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x741b; op2val:0xf41f; + valaddr_reg:x4; val_offset:1704*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1704*FLEN/8, x6, x7, x1) + +inst_876: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x01b and fs2 == 1 and fe2 == 0x1d and fm2 == 0x01f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x741b; op2val:0xf41f; + valaddr_reg:x4; val_offset:1706*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1706*FLEN/8, x6, x7, x1) + +inst_877: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x01b and fs2 == 1 and fe2 == 0x1d and fm2 == 0x01f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x741b; op2val:0xf41f; + valaddr_reg:x4; val_offset:1708*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1708*FLEN/8, x6, x7, x1) + +inst_878: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x01b and fs2 == 1 and fe2 == 0x1d and fm2 == 0x01f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x741b; op2val:0xf41f; + valaddr_reg:x4; val_offset:1710*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1710*FLEN/8, x6, x7, x1) + +inst_879: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x01b and fs2 == 1 and fe2 == 0x1d and fm2 == 0x01f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x741b; op2val:0xf41f; + valaddr_reg:x4; val_offset:1712*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1712*FLEN/8, x6, x7, x1) + +inst_880: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2bc and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2be and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7abc; op2val:0xfabe; + valaddr_reg:x4; val_offset:1714*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1714*FLEN/8, x6, x7, x1) + +inst_881: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2bc and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2be and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7abc; op2val:0xfabe; + valaddr_reg:x4; val_offset:1716*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1716*FLEN/8, x6, x7, x1) + +inst_882: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2bc and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2be and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7abc; op2val:0xfabe; + valaddr_reg:x4; val_offset:1718*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1718*FLEN/8, x6, x7, x1) + +inst_883: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2bc and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2be and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7abc; op2val:0xfabe; + valaddr_reg:x4; val_offset:1720*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1720*FLEN/8, x6, x7, x1) + +inst_884: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2bc and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2be and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7abc; op2val:0xfabe; + valaddr_reg:x4; val_offset:1722*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1722*FLEN/8, x6, x7, x1) + +inst_885: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1be and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79be; op2val:0xf9c0; + valaddr_reg:x4; val_offset:1724*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1724*FLEN/8, x6, x7, x1) + +inst_886: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1be and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1c0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79be; op2val:0xf9c0; + valaddr_reg:x4; val_offset:1726*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1726*FLEN/8, x6, x7, x1) + +inst_887: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1be and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1c0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79be; op2val:0xf9c0; + valaddr_reg:x4; val_offset:1728*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1728*FLEN/8, x6, x7, x1) + +inst_888: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1be and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1c0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79be; op2val:0xf9c0; + valaddr_reg:x4; val_offset:1730*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1730*FLEN/8, x6, x7, x1) + +inst_889: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1be and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1c0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79be; op2val:0xf9c0; + valaddr_reg:x4; val_offset:1732*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1732*FLEN/8, x6, x7, x1) + +inst_890: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x03e and fs2 == 1 and fe2 == 0x1b and fm2 == 0x04e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c3e; op2val:0xec4e; + valaddr_reg:x4; val_offset:1734*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1734*FLEN/8, x6, x7, x1) + +inst_891: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x03e and fs2 == 1 and fe2 == 0x1b and fm2 == 0x04e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c3e; op2val:0xec4e; + valaddr_reg:x4; val_offset:1736*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1736*FLEN/8, x6, x7, x1) + +inst_892: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x03e and fs2 == 1 and fe2 == 0x1b and fm2 == 0x04e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c3e; op2val:0xec4e; + valaddr_reg:x4; val_offset:1738*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1738*FLEN/8, x6, x7, x1) + +inst_893: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x03e and fs2 == 1 and fe2 == 0x1b and fm2 == 0x04e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c3e; op2val:0xec4e; + valaddr_reg:x4; val_offset:1740*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1740*FLEN/8, x6, x7, x1) + +inst_894: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x03e and fs2 == 1 and fe2 == 0x1b and fm2 == 0x04e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c3e; op2val:0xec4e; + valaddr_reg:x4; val_offset:1742*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1742*FLEN/8, x6, x7, x1) + +inst_895: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f2 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2f4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7af2; op2val:0xfaf4; + valaddr_reg:x4; val_offset:1744*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1744*FLEN/8, x6, x7, x1) + +inst_896: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f2 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2f4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7af2; op2val:0xfaf4; + valaddr_reg:x4; val_offset:1746*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1746*FLEN/8, x6, x7, x1) + +inst_897: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f2 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2f4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7af2; op2val:0xfaf4; + valaddr_reg:x4; val_offset:1748*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1748*FLEN/8, x6, x7, x1) + +inst_898: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f2 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2f4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7af2; op2val:0xfaf4; + valaddr_reg:x4; val_offset:1750*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1750*FLEN/8, x6, x7, x1) + +inst_899: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f2 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2f4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7af2; op2val:0xfaf4; + valaddr_reg:x4; val_offset:1752*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1752*FLEN/8, x6, x7, x1) + +inst_900: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x333 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x33b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7333; op2val:0xf33b; + valaddr_reg:x4; val_offset:1754*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1754*FLEN/8, x6, x7, x1) + +inst_901: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x333 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x33b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7333; op2val:0xf33b; + valaddr_reg:x4; val_offset:1756*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1756*FLEN/8, x6, x7, x1) + +inst_902: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x333 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x33b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7333; op2val:0xf33b; + valaddr_reg:x4; val_offset:1758*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1758*FLEN/8, x6, x7, x1) + +inst_903: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x333 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x33b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7333; op2val:0xf33b; + valaddr_reg:x4; val_offset:1760*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1760*FLEN/8, x6, x7, x1) + +inst_904: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x333 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x33b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7333; op2val:0xf33b; + valaddr_reg:x4; val_offset:1762*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1762*FLEN/8, x6, x7, x1) + +inst_905: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x3d4 and fs2 == 1 and fe2 == 0x19 and fm2 == 0x02a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x63d4; op2val:0xe42a; + valaddr_reg:x4; val_offset:1764*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1764*FLEN/8, x6, x7, x1) + +inst_906: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x3d4 and fs2 == 1 and fe2 == 0x19 and fm2 == 0x02a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x63d4; op2val:0xe42a; + valaddr_reg:x4; val_offset:1766*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1766*FLEN/8, x6, x7, x1) + +inst_907: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x3d4 and fs2 == 1 and fe2 == 0x19 and fm2 == 0x02a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x63d4; op2val:0xe42a; + valaddr_reg:x4; val_offset:1768*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1768*FLEN/8, x6, x7, x1) + +inst_908: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x3d4 and fs2 == 1 and fe2 == 0x19 and fm2 == 0x02a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x63d4; op2val:0xe42a; + valaddr_reg:x4; val_offset:1770*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1770*FLEN/8, x6, x7, x1) + +inst_909: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x3d4 and fs2 == 1 and fe2 == 0x19 and fm2 == 0x02a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x63d4; op2val:0xe42a; + valaddr_reg:x4; val_offset:1772*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1772*FLEN/8, x6, x7, x1) + +inst_910: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x149 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x14d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7549; op2val:0xf54d; + valaddr_reg:x4; val_offset:1774*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1774*FLEN/8, x6, x7, x1) + +inst_911: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x149 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x14d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7549; op2val:0xf54d; + valaddr_reg:x4; val_offset:1776*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1776*FLEN/8, x6, x7, x1) + +inst_912: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x149 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x14d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7549; op2val:0xf54d; + valaddr_reg:x4; val_offset:1778*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1778*FLEN/8, x6, x7, x1) +RVTEST_SIGBASE(x7,signature_x7_7) + +inst_913: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x149 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x14d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7549; op2val:0xf54d; + valaddr_reg:x4; val_offset:1780*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1780*FLEN/8, x6, x7, x1) + +inst_914: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x149 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x14d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7549; op2val:0xf54d; + valaddr_reg:x4; val_offset:1782*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1782*FLEN/8, x6, x7, x1) + +inst_915: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0c2 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0ba and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x70c2; op2val:0xf0ba; + valaddr_reg:x4; val_offset:1784*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1784*FLEN/8, x6, x7, x1) + +inst_916: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0c2 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0ba and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x70c2; op2val:0xf0ba; + valaddr_reg:x4; val_offset:1786*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1786*FLEN/8, x6, x7, x1) + +inst_917: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0c2 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0ba and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x70c2; op2val:0xf0ba; + valaddr_reg:x4; val_offset:1788*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1788*FLEN/8, x6, x7, x1) + +inst_918: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0c2 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0ba and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x70c2; op2val:0xf0ba; + valaddr_reg:x4; val_offset:1790*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1790*FLEN/8, x6, x7, x1) + +inst_919: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0c2 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0ba and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x70c2; op2val:0xf0ba; + valaddr_reg:x4; val_offset:1792*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1792*FLEN/8, x6, x7, x1) + +inst_920: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3be and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3bc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bbe; op2val:0xfbbc; + valaddr_reg:x4; val_offset:1794*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1794*FLEN/8, x6, x7, x1) + +inst_921: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3be and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3bc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bbe; op2val:0xfbbc; + valaddr_reg:x4; val_offset:1796*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1796*FLEN/8, x6, x7, x1) + +inst_922: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3be and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3bc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bbe; op2val:0xfbbc; + valaddr_reg:x4; val_offset:1798*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1798*FLEN/8, x6, x7, x1) + +inst_923: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3be and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3bc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bbe; op2val:0xfbbc; + valaddr_reg:x4; val_offset:1800*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1800*FLEN/8, x6, x7, x1) + +inst_924: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3be and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3bc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bbe; op2val:0xfbbc; + valaddr_reg:x4; val_offset:1802*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1802*FLEN/8, x6, x7, x1) + +inst_925: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x334 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x332 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b34; op2val:0xfb32; + valaddr_reg:x4; val_offset:1804*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1804*FLEN/8, x6, x7, x1) + +inst_926: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x334 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x332 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b34; op2val:0xfb32; + valaddr_reg:x4; val_offset:1806*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1806*FLEN/8, x6, x7, x1) + +inst_927: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x334 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x332 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b34; op2val:0xfb32; + valaddr_reg:x4; val_offset:1808*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1808*FLEN/8, x6, x7, x1) + +inst_928: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x334 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x332 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b34; op2val:0xfb32; + valaddr_reg:x4; val_offset:1810*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1810*FLEN/8, x6, x7, x1) + +inst_929: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x334 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x332 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b34; op2val:0xfb32; + valaddr_reg:x4; val_offset:1812*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1812*FLEN/8, x6, x7, x1) + +inst_930: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x096 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x094 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7896; op2val:0xf894; + valaddr_reg:x4; val_offset:1814*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1814*FLEN/8, x6, x7, x1) + +inst_931: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x096 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x094 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7896; op2val:0xf894; + valaddr_reg:x4; val_offset:1816*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1816*FLEN/8, x6, x7, x1) + +inst_932: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x096 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x094 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7896; op2val:0xf894; + valaddr_reg:x4; val_offset:1818*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1818*FLEN/8, x6, x7, x1) + +inst_933: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x096 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x094 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7896; op2val:0xf894; + valaddr_reg:x4; val_offset:1820*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1820*FLEN/8, x6, x7, x1) + +inst_934: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x096 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x094 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7896; op2val:0xf894; + valaddr_reg:x4; val_offset:1822*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1822*FLEN/8, x6, x7, x1) + +inst_935: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x270 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x26e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a70; op2val:0xfa6e; + valaddr_reg:x4; val_offset:1824*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1824*FLEN/8, x6, x7, x1) + +inst_936: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x270 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x26e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a70; op2val:0xfa6e; + valaddr_reg:x4; val_offset:1826*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1826*FLEN/8, x6, x7, x1) + +inst_937: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x270 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x26e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a70; op2val:0xfa6e; + valaddr_reg:x4; val_offset:1828*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1828*FLEN/8, x6, x7, x1) + +inst_938: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x270 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x26e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a70; op2val:0xfa6e; + valaddr_reg:x4; val_offset:1830*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1830*FLEN/8, x6, x7, x1) + +inst_939: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x270 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x26e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a70; op2val:0xfa6e; + valaddr_reg:x4; val_offset:1832*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1832*FLEN/8, x6, x7, x1) + +inst_940: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3eb and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3e9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7beb; op2val:0xfbe9; + valaddr_reg:x4; val_offset:1834*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1834*FLEN/8, x6, x7, x1) + +inst_941: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3eb and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3e9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7beb; op2val:0xfbe9; + valaddr_reg:x4; val_offset:1836*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1836*FLEN/8, x6, x7, x1) + +inst_942: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3eb and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3e9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7beb; op2val:0xfbe9; + valaddr_reg:x4; val_offset:1838*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1838*FLEN/8, x6, x7, x1) + +inst_943: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3eb and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3e9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7beb; op2val:0xfbe9; + valaddr_reg:x4; val_offset:1840*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1840*FLEN/8, x6, x7, x1) + +inst_944: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3eb and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3e9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7beb; op2val:0xfbe9; + valaddr_reg:x4; val_offset:1842*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1842*FLEN/8, x6, x7, x1) + +inst_945: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x33e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x33c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b3e; op2val:0xfb3c; + valaddr_reg:x4; val_offset:1844*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1844*FLEN/8, x6, x7, x1) + +inst_946: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x33e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x33c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b3e; op2val:0xfb3c; + valaddr_reg:x4; val_offset:1846*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1846*FLEN/8, x6, x7, x1) + +inst_947: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x33e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x33c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b3e; op2val:0xfb3c; + valaddr_reg:x4; val_offset:1848*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1848*FLEN/8, x6, x7, x1) + +inst_948: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x33e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x33c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b3e; op2val:0xfb3c; + valaddr_reg:x4; val_offset:1850*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1850*FLEN/8, x6, x7, x1) + +inst_949: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x33e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x33c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b3e; op2val:0xfb3c; + valaddr_reg:x4; val_offset:1852*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1852*FLEN/8, x6, x7, x1) + +inst_950: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x048 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x048 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7848; op2val:0xf848; + valaddr_reg:x4; val_offset:1854*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1854*FLEN/8, x6, x7, x1) + +inst_951: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x048 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x048 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7848; op2val:0xf848; + valaddr_reg:x4; val_offset:1856*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1856*FLEN/8, x6, x7, x1) + +inst_952: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x048 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x048 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7848; op2val:0xf848; + valaddr_reg:x4; val_offset:1858*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1858*FLEN/8, x6, x7, x1) + +inst_953: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x048 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x048 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7848; op2val:0xf848; + valaddr_reg:x4; val_offset:1860*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1860*FLEN/8, x6, x7, x1) + +inst_954: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x048 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x048 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7848; op2val:0xf848; + valaddr_reg:x4; val_offset:1862*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1862*FLEN/8, x6, x7, x1) + +inst_955: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x29a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x29a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a9a; op2val:0xfa9a; + valaddr_reg:x4; val_offset:1864*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1864*FLEN/8, x6, x7, x1) + +inst_956: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x29a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x29a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a9a; op2val:0xfa9a; + valaddr_reg:x4; val_offset:1866*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1866*FLEN/8, x6, x7, x1) + +inst_957: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x29a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x29a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a9a; op2val:0xfa9a; + valaddr_reg:x4; val_offset:1868*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1868*FLEN/8, x6, x7, x1) + +inst_958: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x29a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x29a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a9a; op2val:0xfa9a; + valaddr_reg:x4; val_offset:1870*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1870*FLEN/8, x6, x7, x1) + +inst_959: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x29a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x29a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a9a; op2val:0xfa9a; + valaddr_reg:x4; val_offset:1872*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1872*FLEN/8, x6, x7, x1) + +inst_960: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x253 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x253 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a53; op2val:0xfa53; + valaddr_reg:x4; val_offset:1874*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1874*FLEN/8, x6, x7, x1) + +inst_961: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x253 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x253 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a53; op2val:0xfa53; + valaddr_reg:x4; val_offset:1876*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1876*FLEN/8, x6, x7, x1) + +inst_962: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x253 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x253 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a53; op2val:0xfa53; + valaddr_reg:x4; val_offset:1878*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1878*FLEN/8, x6, x7, x1) + +inst_963: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x253 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x253 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a53; op2val:0xfa53; + valaddr_reg:x4; val_offset:1880*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1880*FLEN/8, x6, x7, x1) + +inst_964: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x253 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x253 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a53; op2val:0xfa53; + valaddr_reg:x4; val_offset:1882*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1882*FLEN/8, x6, x7, x1) + +inst_965: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0b0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78b0; op2val:0xf8b0; + valaddr_reg:x4; val_offset:1884*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1884*FLEN/8, x6, x7, x1) + +inst_966: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0b0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78b0; op2val:0xf8b0; + valaddr_reg:x4; val_offset:1886*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1886*FLEN/8, x6, x7, x1) + +inst_967: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0b0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78b0; op2val:0xf8b0; + valaddr_reg:x4; val_offset:1888*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1888*FLEN/8, x6, x7, x1) + +inst_968: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0b0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78b0; op2val:0xf8b0; + valaddr_reg:x4; val_offset:1890*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1890*FLEN/8, x6, x7, x1) + +inst_969: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0b0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78b0; op2val:0xf8b0; + valaddr_reg:x4; val_offset:1892*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1892*FLEN/8, x6, x7, x1) + +inst_970: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x261 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x261 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a61; op2val:0xfa61; + valaddr_reg:x4; val_offset:1894*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1894*FLEN/8, x6, x7, x1) + +inst_971: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x261 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x261 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a61; op2val:0xfa61; + valaddr_reg:x4; val_offset:1896*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1896*FLEN/8, x6, x7, x1) + +inst_972: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x261 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x261 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a61; op2val:0xfa61; + valaddr_reg:x4; val_offset:1898*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1898*FLEN/8, x6, x7, x1) + +inst_973: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x261 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x261 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a61; op2val:0xfa61; + valaddr_reg:x4; val_offset:1900*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1900*FLEN/8, x6, x7, x1) + +inst_974: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x261 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x261 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a61; op2val:0xfa61; + valaddr_reg:x4; val_offset:1902*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1902*FLEN/8, x6, x7, x1) + +inst_975: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x031 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x02f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4c31; op2val:0xcc2f; + valaddr_reg:x4; val_offset:1904*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1904*FLEN/8, x6, x7, x1) + +inst_976: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x031 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x02f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4c31; op2val:0xcc2f; + valaddr_reg:x4; val_offset:1906*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1906*FLEN/8, x6, x7, x1) + +inst_977: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x031 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x02f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4c31; op2val:0xcc2f; + valaddr_reg:x4; val_offset:1908*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1908*FLEN/8, x6, x7, x1) + +inst_978: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x031 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x02f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4c31; op2val:0xcc2f; + valaddr_reg:x4; val_offset:1910*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1910*FLEN/8, x6, x7, x1) + +inst_979: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x031 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x02f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4c31; op2val:0xcc2f; + valaddr_reg:x4; val_offset:1912*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1912*FLEN/8, x6, x7, x1) + +inst_980: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x00d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x780d; op2val:0xf80d; + valaddr_reg:x4; val_offset:1914*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1914*FLEN/8, x6, x7, x1) + +inst_981: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x00d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x780d; op2val:0xf80d; + valaddr_reg:x4; val_offset:1916*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1916*FLEN/8, x6, x7, x1) + +inst_982: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x00d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x780d; op2val:0xf80d; + valaddr_reg:x4; val_offset:1918*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1918*FLEN/8, x6, x7, x1) + +inst_983: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x00d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x780d; op2val:0xf80d; + valaddr_reg:x4; val_offset:1920*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1920*FLEN/8, x6, x7, x1) + +inst_984: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x00d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x780d; op2val:0xf80d; + valaddr_reg:x4; val_offset:1922*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1922*FLEN/8, x6, x7, x1) + +inst_985: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x032 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x032 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c32; op2val:0xec32; + valaddr_reg:x4; val_offset:1924*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1924*FLEN/8, x6, x7, x1) + +inst_986: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x032 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x032 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c32; op2val:0xec32; + valaddr_reg:x4; val_offset:1926*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1926*FLEN/8, x6, x7, x1) + +inst_987: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x032 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x032 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c32; op2val:0xec32; + valaddr_reg:x4; val_offset:1928*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1928*FLEN/8, x6, x7, x1) + +inst_988: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x032 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x032 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c32; op2val:0xec32; + valaddr_reg:x4; val_offset:1930*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1930*FLEN/8, x6, x7, x1) + +inst_989: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x032 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x032 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c32; op2val:0xec32; + valaddr_reg:x4; val_offset:1932*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1932*FLEN/8, x6, x7, x1) + +inst_990: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x38a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x38a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b8a; op2val:0xfb8a; + valaddr_reg:x4; val_offset:1934*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1934*FLEN/8, x6, x7, x1) + +inst_991: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x38a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x38a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b8a; op2val:0xfb8a; + valaddr_reg:x4; val_offset:1936*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1936*FLEN/8, x6, x7, x1) + +inst_992: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x38a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x38a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b8a; op2val:0xfb8a; + valaddr_reg:x4; val_offset:1938*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1938*FLEN/8, x6, x7, x1) + +inst_993: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x38a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x38a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b8a; op2val:0xfb8a; + valaddr_reg:x4; val_offset:1940*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1940*FLEN/8, x6, x7, x1) + +inst_994: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x38a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x38a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b8a; op2val:0xfb8a; + valaddr_reg:x4; val_offset:1942*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1942*FLEN/8, x6, x7, x1) + +inst_995: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x286 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x286 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7686; op2val:0xf686; + valaddr_reg:x4; val_offset:1944*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1944*FLEN/8, x6, x7, x1) + +inst_996: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x286 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x286 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7686; op2val:0xf686; + valaddr_reg:x4; val_offset:1946*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1946*FLEN/8, x6, x7, x1) + +inst_997: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x286 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x286 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7686; op2val:0xf686; + valaddr_reg:x4; val_offset:1948*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1948*FLEN/8, x6, x7, x1) + +inst_998: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x286 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x286 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7686; op2val:0xf686; + valaddr_reg:x4; val_offset:1950*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1950*FLEN/8, x6, x7, x1) + +inst_999: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x286 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x286 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7686; op2val:0xf686; + valaddr_reg:x4; val_offset:1952*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1952*FLEN/8, x6, x7, x1) + +inst_1000: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3f7 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x3f7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6bf7; op2val:0xebf7; + valaddr_reg:x4; val_offset:1954*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1954*FLEN/8, x6, x7, x1) + +inst_1001: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3f7 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x3f7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6bf7; op2val:0xebf7; + valaddr_reg:x4; val_offset:1956*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1956*FLEN/8, x6, x7, x1) + +inst_1002: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3f7 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x3f7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6bf7; op2val:0xebf7; + valaddr_reg:x4; val_offset:1958*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1958*FLEN/8, x6, x7, x1) + +inst_1003: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3f7 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x3f7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6bf7; op2val:0xebf7; + valaddr_reg:x4; val_offset:1960*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1960*FLEN/8, x6, x7, x1) + +inst_1004: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3f7 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x3f7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6bf7; op2val:0xebf7; + valaddr_reg:x4; val_offset:1962*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1962*FLEN/8, x6, x7, x1) + +inst_1005: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x012 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x012 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7012; op2val:0xf012; + valaddr_reg:x4; val_offset:1964*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1964*FLEN/8, x6, x7, x1) + +inst_1006: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x012 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x012 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7012; op2val:0xf012; + valaddr_reg:x4; val_offset:1966*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1966*FLEN/8, x6, x7, x1) + +inst_1007: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x012 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x012 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7012; op2val:0xf012; + valaddr_reg:x4; val_offset:1968*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1968*FLEN/8, x6, x7, x1) + +inst_1008: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x012 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x012 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7012; op2val:0xf012; + valaddr_reg:x4; val_offset:1970*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1970*FLEN/8, x6, x7, x1) + +inst_1009: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x012 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x012 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7012; op2val:0xf012; + valaddr_reg:x4; val_offset:1972*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1972*FLEN/8, x6, x7, x1) + +inst_1010: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a2 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2a2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aa2; op2val:0xfaa2; + valaddr_reg:x4; val_offset:1974*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1974*FLEN/8, x6, x7, x1) + +inst_1011: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a2 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2a2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aa2; op2val:0xfaa2; + valaddr_reg:x4; val_offset:1976*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1976*FLEN/8, x6, x7, x1) + +inst_1012: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a2 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2a2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aa2; op2val:0xfaa2; + valaddr_reg:x4; val_offset:1978*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1978*FLEN/8, x6, x7, x1) + +inst_1013: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a2 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2a2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aa2; op2val:0xfaa2; + valaddr_reg:x4; val_offset:1980*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1980*FLEN/8, x6, x7, x1) + +inst_1014: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a2 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2a2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aa2; op2val:0xfaa2; + valaddr_reg:x4; val_offset:1982*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1982*FLEN/8, x6, x7, x1) + +inst_1015: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x099 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x099 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6899; op2val:0xe899; + valaddr_reg:x4; val_offset:1984*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1984*FLEN/8, x6, x7, x1) + +inst_1016: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x099 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x099 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6899; op2val:0xe899; + valaddr_reg:x4; val_offset:1986*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1986*FLEN/8, x6, x7, x1) + +inst_1017: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x099 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x099 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6899; op2val:0xe899; + valaddr_reg:x4; val_offset:1988*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1988*FLEN/8, x6, x7, x1) + +inst_1018: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x099 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x099 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6899; op2val:0xe899; + valaddr_reg:x4; val_offset:1990*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 1990*FLEN/8, x6, x7, x1) + +inst_1019: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x099 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x099 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6899; op2val:0xe899; + valaddr_reg:x4; val_offset:1992*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 1992*FLEN/8, x6, x7, x1) + +inst_1020: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3dd and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3dd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77dd; op2val:0xf7dd; + valaddr_reg:x4; val_offset:1994*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 1994*FLEN/8, x6, x7, x1) + +inst_1021: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3dd and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3dd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77dd; op2val:0xf7dd; + valaddr_reg:x4; val_offset:1996*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 1996*FLEN/8, x6, x7, x1) + +inst_1022: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3dd and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3dd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77dd; op2val:0xf7dd; + valaddr_reg:x4; val_offset:1998*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 1998*FLEN/8, x6, x7, x1) + +inst_1023: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3dd and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3dd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77dd; op2val:0xf7dd; + valaddr_reg:x4; val_offset:2000*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 2000*FLEN/8, x6, x7, x1) + +inst_1024: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3dd and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3dd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77dd; op2val:0xf7dd; + valaddr_reg:x4; val_offset:2002*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 2002*FLEN/8, x6, x7, x1) + +inst_1025: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0d7 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0d7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x70d7; op2val:0xf0d7; + valaddr_reg:x4; val_offset:2004*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 2004*FLEN/8, x6, x7, x1) + +inst_1026: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0d7 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0d7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x70d7; op2val:0xf0d7; + valaddr_reg:x4; val_offset:2006*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 2006*FLEN/8, x6, x7, x1) + +inst_1027: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0d7 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0d7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x70d7; op2val:0xf0d7; + valaddr_reg:x4; val_offset:2008*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 2008*FLEN/8, x6, x7, x1) + +inst_1028: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0d7 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0d7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x70d7; op2val:0xf0d7; + valaddr_reg:x4; val_offset:2010*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 2010*FLEN/8, x6, x7, x1) + +inst_1029: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0d7 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0d7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x70d7; op2val:0xf0d7; + valaddr_reg:x4; val_offset:2012*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 2012*FLEN/8, x6, x7, x1) + +inst_1030: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x293 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x293 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7693; op2val:0xf693; + valaddr_reg:x4; val_offset:2014*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 2014*FLEN/8, x6, x7, x1) + +inst_1031: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x293 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x293 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7693; op2val:0xf693; + valaddr_reg:x4; val_offset:2016*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 2016*FLEN/8, x6, x7, x1) + +inst_1032: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x293 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x293 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7693; op2val:0xf693; + valaddr_reg:x4; val_offset:2018*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 2018*FLEN/8, x6, x7, x1) + +inst_1033: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x293 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x293 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7693; op2val:0xf693; + valaddr_reg:x4; val_offset:2020*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 2020*FLEN/8, x6, x7, x1) + +inst_1034: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x293 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x293 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7693; op2val:0xf693; + valaddr_reg:x4; val_offset:2022*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 2022*FLEN/8, x6, x7, x1) + +inst_1035: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x22f and fs2 == 1 and fe2 == 0x1d and fm2 == 0x22f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x762f; op2val:0xf62f; + valaddr_reg:x4; val_offset:2024*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 2024*FLEN/8, x6, x7, x1) + +inst_1036: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x22f and fs2 == 1 and fe2 == 0x1d and fm2 == 0x22f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x762f; op2val:0xf62f; + valaddr_reg:x4; val_offset:2026*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 2026*FLEN/8, x6, x7, x1) + +inst_1037: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x22f and fs2 == 1 and fe2 == 0x1d and fm2 == 0x22f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x762f; op2val:0xf62f; + valaddr_reg:x4; val_offset:2028*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 2028*FLEN/8, x6, x7, x1) + +inst_1038: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x22f and fs2 == 1 and fe2 == 0x1d and fm2 == 0x22f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x762f; op2val:0xf62f; + valaddr_reg:x4; val_offset:2030*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 2030*FLEN/8, x6, x7, x1) + +inst_1039: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x22f and fs2 == 1 and fe2 == 0x1d and fm2 == 0x22f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x762f; op2val:0xf62f; + valaddr_reg:x4; val_offset:2032*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 2032*FLEN/8, x6, x7, x1) + +inst_1040: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x387 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x387 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7787; op2val:0xf787; + valaddr_reg:x4; val_offset:2034*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 2034*FLEN/8, x6, x7, x1) +RVTEST_SIGBASE(x7,signature_x7_8) + +inst_1041: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x387 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x387 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7787; op2val:0xf787; + valaddr_reg:x4; val_offset:2036*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 2036*FLEN/8, x6, x7, x1) + +inst_1042: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x387 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x387 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7787; op2val:0xf787; + valaddr_reg:x4; val_offset:2038*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 2038*FLEN/8, x6, x7, x1) + +inst_1043: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x387 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x387 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7787; op2val:0xf787; + valaddr_reg:x4; val_offset:2040*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 2040*FLEN/8, x6, x7, x1) + +inst_1044: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x387 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x387 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7787; op2val:0xf787; + valaddr_reg:x4; val_offset:2042*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 2042*FLEN/8, x6, x7, x1) + +inst_1045: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x027 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x027 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6827; op2val:0xe827; + valaddr_reg:x4; val_offset:2044*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 2044*FLEN/8, x6, x7, x1) + +inst_1046: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x027 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x027 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6827; op2val:0xe827; + valaddr_reg:x4; val_offset:2046*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 2046*FLEN/8, x6, x7, x1) + +inst_1047: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x027 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x027 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6827; op2val:0xe827; + valaddr_reg:x4; val_offset:2048*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 2048*FLEN/8, x6, x7, x1) + +inst_1048: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x027 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x027 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6827; op2val:0xe827; + valaddr_reg:x4; val_offset:2050*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 2050*FLEN/8, x6, x7, x1) + +inst_1049: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x027 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x027 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6827; op2val:0xe827; + valaddr_reg:x4; val_offset:2052*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 2052*FLEN/8, x6, x7, x1) + +inst_1050: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x064 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x064 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7864; op2val:0xf864; + valaddr_reg:x4; val_offset:2054*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 2054*FLEN/8, x6, x7, x1) + +inst_1051: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x064 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x064 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7864; op2val:0xf864; + valaddr_reg:x4; val_offset:2056*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 2056*FLEN/8, x6, x7, x1) + +inst_1052: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x064 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x064 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7864; op2val:0xf864; + valaddr_reg:x4; val_offset:2058*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 2058*FLEN/8, x6, x7, x1) + +inst_1053: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x064 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x064 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7864; op2val:0xf864; + valaddr_reg:x4; val_offset:2060*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 2060*FLEN/8, x6, x7, x1) + +inst_1054: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x064 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x064 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7864; op2val:0xf864; + valaddr_reg:x4; val_offset:2062*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 2062*FLEN/8, x6, x7, x1) + +inst_1055: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x221 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x221 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7621; op2val:0xf621; + valaddr_reg:x4; val_offset:2064*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 2064*FLEN/8, x6, x7, x1) + +inst_1056: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x221 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x221 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7621; op2val:0xf621; + valaddr_reg:x4; val_offset:2066*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 2066*FLEN/8, x6, x7, x1) + +inst_1057: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x221 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x221 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7621; op2val:0xf621; + valaddr_reg:x4; val_offset:2068*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 2068*FLEN/8, x6, x7, x1) + +inst_1058: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x221 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x221 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7621; op2val:0xf621; + valaddr_reg:x4; val_offset:2070*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 2070*FLEN/8, x6, x7, x1) + +inst_1059: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x221 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x221 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7621; op2val:0xf621; + valaddr_reg:x4; val_offset:2072*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 2072*FLEN/8, x6, x7, x1) + +inst_1060: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d7 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3d7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77d7; op2val:0xf7d7; + valaddr_reg:x4; val_offset:2074*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 2074*FLEN/8, x6, x7, x1) + +inst_1061: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d7 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3d7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77d7; op2val:0xf7d7; + valaddr_reg:x4; val_offset:2076*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 2076*FLEN/8, x6, x7, x1) + +inst_1062: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d7 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3d7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77d7; op2val:0xf7d7; + valaddr_reg:x4; val_offset:2078*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 2078*FLEN/8, x6, x7, x1) + +inst_1063: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d7 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3d7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77d7; op2val:0xf7d7; + valaddr_reg:x4; val_offset:2080*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 2080*FLEN/8, x6, x7, x1) + +inst_1064: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d7 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3d7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77d7; op2val:0xf7d7; + valaddr_reg:x4; val_offset:2082*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 2082*FLEN/8, x6, x7, x1) + +inst_1065: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78e0; op2val:0xf8e0; + valaddr_reg:x4; val_offset:2084*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 2084*FLEN/8, x6, x7, x1) + +inst_1066: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0e0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78e0; op2val:0xf8e0; + valaddr_reg:x4; val_offset:2086*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 2086*FLEN/8, x6, x7, x1) + +inst_1067: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0e0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78e0; op2val:0xf8e0; + valaddr_reg:x4; val_offset:2088*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 2088*FLEN/8, x6, x7, x1) + +inst_1068: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0e0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78e0; op2val:0xf8e0; + valaddr_reg:x4; val_offset:2090*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 2090*FLEN/8, x6, x7, x1) + +inst_1069: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0e0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78e0; op2val:0xf8e0; + valaddr_reg:x4; val_offset:2092*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 2092*FLEN/8, x6, x7, x1) + +inst_1070: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x10e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x10e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x790e; op2val:0xf90e; + valaddr_reg:x4; val_offset:2094*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 2094*FLEN/8, x6, x7, x1) + +inst_1071: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x10e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x10e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x790e; op2val:0xf90e; + valaddr_reg:x4; val_offset:2096*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 2096*FLEN/8, x6, x7, x1) + +inst_1072: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x10e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x10e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x790e; op2val:0xf90e; + valaddr_reg:x4; val_offset:2098*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 2098*FLEN/8, x6, x7, x1) + +inst_1073: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x10e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x10e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x790e; op2val:0xf90e; + valaddr_reg:x4; val_offset:2100*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 2100*FLEN/8, x6, x7, x1) + +inst_1074: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x10e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x10e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x790e; op2val:0xf90e; + valaddr_reg:x4; val_offset:2102*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 2102*FLEN/8, x6, x7, x1) + +inst_1075: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3f4 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x3f4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ff4; op2val:0xeff4; + valaddr_reg:x4; val_offset:2104*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 2104*FLEN/8, x6, x7, x1) + +inst_1076: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3f4 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x3f4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ff4; op2val:0xeff4; + valaddr_reg:x4; val_offset:2106*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 2106*FLEN/8, x6, x7, x1) + +inst_1077: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3f4 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x3f4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ff4; op2val:0xeff4; + valaddr_reg:x4; val_offset:2108*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 2108*FLEN/8, x6, x7, x1) + +inst_1078: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3f4 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x3f4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ff4; op2val:0xeff4; + valaddr_reg:x4; val_offset:2110*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 2110*FLEN/8, x6, x7, x1) + +inst_1079: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3f4 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x3f4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ff4; op2val:0xeff4; + valaddr_reg:x4; val_offset:2112*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 2112*FLEN/8, x6, x7, x1) + +inst_1080: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ac0; op2val:0xfac0; + valaddr_reg:x4; val_offset:2114*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 2114*FLEN/8, x6, x7, x1) + +inst_1081: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2c0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ac0; op2val:0xfac0; + valaddr_reg:x4; val_offset:2116*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 2116*FLEN/8, x6, x7, x1) + +inst_1082: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x016 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x016 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7816; op2val:0xf816; + valaddr_reg:x4; val_offset:2118*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 2118*FLEN/8, x6, x7, x1) + +inst_1083: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x39f and fs2 == 1 and fe2 == 0x1d and fm2 == 0x39f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x779f; op2val:0xf79f; + valaddr_reg:x4; val_offset:2120*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 2120*FLEN/8, x6, x7, x1) + +inst_1084: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x342 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x342 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b42; op2val:0xfb42; + valaddr_reg:x4; val_offset:2122*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 2122*FLEN/8, x6, x7, x1) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(31424,32,FLEN) +NAN_BOXED(31424,16,FLEN) +NAN_BOXED(31424,32,FLEN) +NAN_BOXED(64192,16,FLEN) +NAN_BOXED(31424,32,FLEN) +NAN_BOXED(31424,16,FLEN) +NAN_BOXED(31424,32,FLEN) +NAN_BOXED(64192,16,FLEN) +NAN_BOXED(31424,32,FLEN) +NAN_BOXED(64192,16,FLEN) +NAN_BOXED(30393,32,FLEN) +NAN_BOXED(63161,16,FLEN) +NAN_BOXED(30393,32,FLEN) +NAN_BOXED(63161,16,FLEN) +NAN_BOXED(30393,32,FLEN) +NAN_BOXED(63161,16,FLEN) +NAN_BOXED(30393,32,FLEN) +NAN_BOXED(63161,16,FLEN) +NAN_BOXED(30393,32,FLEN) +NAN_BOXED(63161,16,FLEN) +NAN_BOXED(30742,32,FLEN) +NAN_BOXED(63510,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(63510,16,FLEN) +NAN_BOXED(30742,32,FLEN) +NAN_BOXED(63510,16,FLEN) +test_dataset_1: +NAN_BOXED(30742,32,FLEN) +NAN_BOXED(63510,16,FLEN) +NAN_BOXED(30742,32,FLEN) +NAN_BOXED(63510,16,FLEN) +NAN_BOXED(31300,32,FLEN) +NAN_BOXED(64068,16,FLEN) +NAN_BOXED(31300,32,FLEN) +NAN_BOXED(64068,16,FLEN) +NAN_BOXED(31300,32,FLEN) +NAN_BOXED(64068,16,FLEN) +NAN_BOXED(31300,32,FLEN) +NAN_BOXED(64068,16,FLEN) +NAN_BOXED(31300,32,FLEN) +NAN_BOXED(64068,16,FLEN) +NAN_BOXED(30623,32,FLEN) +NAN_BOXED(63391,16,FLEN) +NAN_BOXED(30623,32,FLEN) +NAN_BOXED(63391,16,FLEN) +NAN_BOXED(30623,32,FLEN) +NAN_BOXED(63391,16,FLEN) +test_dataset_2: +NAN_BOXED(30623,16,FLEN) +NAN_BOXED(63391,16,FLEN) +NAN_BOXED(30623,16,FLEN) +NAN_BOXED(63391,16,FLEN) +NAN_BOXED(31554,16,FLEN) +NAN_BOXED(64322,16,FLEN) +NAN_BOXED(31554,16,FLEN) +NAN_BOXED(64322,16,FLEN) +NAN_BOXED(31554,16,FLEN) +NAN_BOXED(64322,16,FLEN) +NAN_BOXED(31554,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31554,16,FLEN) +NAN_BOXED(64322,16,FLEN) +NAN_BOXED(29825,16,FLEN) +NAN_BOXED(62593,16,FLEN) +NAN_BOXED(29825,16,FLEN) +NAN_BOXED(62593,16,FLEN) +NAN_BOXED(29825,16,FLEN) +NAN_BOXED(62593,16,FLEN) +NAN_BOXED(29825,16,FLEN) +NAN_BOXED(62593,16,FLEN) +NAN_BOXED(29825,16,FLEN) +NAN_BOXED(62593,16,FLEN) +NAN_BOXED(30961,16,FLEN) +NAN_BOXED(63729,16,FLEN) +NAN_BOXED(30961,16,FLEN) +NAN_BOXED(63729,16,FLEN) +NAN_BOXED(30961,16,FLEN) +NAN_BOXED(63729,16,FLEN) +NAN_BOXED(30961,16,FLEN) +NAN_BOXED(63729,16,FLEN) +NAN_BOXED(30961,16,FLEN) +NAN_BOXED(63729,16,FLEN) +NAN_BOXED(31558,16,FLEN) +NAN_BOXED(64326,16,FLEN) +NAN_BOXED(31558,16,FLEN) +NAN_BOXED(64326,16,FLEN) +NAN_BOXED(31558,16,FLEN) +NAN_BOXED(64326,16,FLEN) +NAN_BOXED(31558,16,FLEN) +NAN_BOXED(64326,16,FLEN) +NAN_BOXED(31558,16,FLEN) +NAN_BOXED(64326,16,FLEN) +NAN_BOXED(31354,16,FLEN) +NAN_BOXED(64122,16,FLEN) +NAN_BOXED(31354,16,FLEN) +NAN_BOXED(64122,16,FLEN) +NAN_BOXED(31354,16,FLEN) +NAN_BOXED(64122,16,FLEN) +NAN_BOXED(31354,16,FLEN) +NAN_BOXED(64122,16,FLEN) +NAN_BOXED(31354,16,FLEN) +NAN_BOXED(64122,16,FLEN) +NAN_BOXED(29941,16,FLEN) +NAN_BOXED(62709,16,FLEN) +NAN_BOXED(29941,16,FLEN) +NAN_BOXED(62709,16,FLEN) +NAN_BOXED(29941,16,FLEN) +NAN_BOXED(62709,16,FLEN) +NAN_BOXED(29941,16,FLEN) +NAN_BOXED(62709,16,FLEN) +NAN_BOXED(29941,16,FLEN) +NAN_BOXED(62709,16,FLEN) +NAN_BOXED(31535,16,FLEN) +NAN_BOXED(64303,16,FLEN) +NAN_BOXED(31535,16,FLEN) +NAN_BOXED(64303,16,FLEN) +NAN_BOXED(31535,16,FLEN) +NAN_BOXED(64303,16,FLEN) +NAN_BOXED(31535,16,FLEN) +NAN_BOXED(64303,16,FLEN) +NAN_BOXED(31535,16,FLEN) +NAN_BOXED(64303,16,FLEN) +NAN_BOXED(30604,16,FLEN) +NAN_BOXED(63372,16,FLEN) +NAN_BOXED(30604,16,FLEN) +NAN_BOXED(63372,16,FLEN) +NAN_BOXED(30604,16,FLEN) +NAN_BOXED(63372,16,FLEN) +NAN_BOXED(30604,16,FLEN) +NAN_BOXED(63372,16,FLEN) +NAN_BOXED(30604,16,FLEN) +NAN_BOXED(63372,16,FLEN) +NAN_BOXED(30449,16,FLEN) +NAN_BOXED(63217,16,FLEN) +NAN_BOXED(30449,16,FLEN) +NAN_BOXED(63217,16,FLEN) +NAN_BOXED(30449,16,FLEN) +NAN_BOXED(63217,16,FLEN) +NAN_BOXED(30449,16,FLEN) +NAN_BOXED(63217,16,FLEN) +NAN_BOXED(30449,16,FLEN) +NAN_BOXED(63217,16,FLEN) +NAN_BOXED(31564,16,FLEN) +NAN_BOXED(64332,16,FLEN) +NAN_BOXED(31564,16,FLEN) +NAN_BOXED(64332,16,FLEN) +NAN_BOXED(31564,16,FLEN) +NAN_BOXED(64332,16,FLEN) +NAN_BOXED(31564,16,FLEN) +NAN_BOXED(64332,16,FLEN) +NAN_BOXED(31564,16,FLEN) +NAN_BOXED(64332,16,FLEN) +NAN_BOXED(30624,16,FLEN) +NAN_BOXED(63392,16,FLEN) +NAN_BOXED(30624,16,FLEN) +NAN_BOXED(63392,16,FLEN) +NAN_BOXED(30624,16,FLEN) +NAN_BOXED(63392,16,FLEN) +NAN_BOXED(30624,16,FLEN) +NAN_BOXED(63392,16,FLEN) +NAN_BOXED(30624,16,FLEN) +NAN_BOXED(63392,16,FLEN) +NAN_BOXED(29738,16,FLEN) +NAN_BOXED(62506,16,FLEN) +NAN_BOXED(29738,16,FLEN) +NAN_BOXED(62506,16,FLEN) +NAN_BOXED(29738,16,FLEN) +NAN_BOXED(62506,16,FLEN) +NAN_BOXED(29738,16,FLEN) +NAN_BOXED(62506,16,FLEN) +NAN_BOXED(29738,16,FLEN) +NAN_BOXED(62506,16,FLEN) +NAN_BOXED(30819,16,FLEN) +NAN_BOXED(63587,16,FLEN) +NAN_BOXED(30819,16,FLEN) +NAN_BOXED(63587,16,FLEN) +NAN_BOXED(30819,16,FLEN) +NAN_BOXED(63587,16,FLEN) +NAN_BOXED(30819,16,FLEN) +NAN_BOXED(63587,16,FLEN) +NAN_BOXED(30819,16,FLEN) +NAN_BOXED(63587,16,FLEN) +NAN_BOXED(31169,16,FLEN) +NAN_BOXED(63937,16,FLEN) +NAN_BOXED(31169,16,FLEN) +NAN_BOXED(63937,16,FLEN) +NAN_BOXED(31169,16,FLEN) +NAN_BOXED(63937,16,FLEN) +NAN_BOXED(31169,16,FLEN) +NAN_BOXED(63937,16,FLEN) +NAN_BOXED(31169,16,FLEN) +NAN_BOXED(63937,16,FLEN) +NAN_BOXED(31384,16,FLEN) +NAN_BOXED(64152,16,FLEN) +NAN_BOXED(31384,16,FLEN) +NAN_BOXED(64152,16,FLEN) +NAN_BOXED(31384,16,FLEN) +NAN_BOXED(64152,16,FLEN) +NAN_BOXED(31384,16,FLEN) +NAN_BOXED(64152,16,FLEN) +NAN_BOXED(31384,16,FLEN) +NAN_BOXED(64152,16,FLEN) +NAN_BOXED(21693,16,FLEN) +NAN_BOXED(54461,16,FLEN) +NAN_BOXED(21693,16,FLEN) +NAN_BOXED(54461,16,FLEN) +NAN_BOXED(21693,16,FLEN) +NAN_BOXED(54461,16,FLEN) +NAN_BOXED(21693,16,FLEN) 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+NAN_BOXED(63588,16,FLEN) +NAN_BOXED(30820,16,FLEN) +NAN_BOXED(63588,16,FLEN) +NAN_BOXED(30241,16,FLEN) +NAN_BOXED(63009,16,FLEN) +NAN_BOXED(30241,16,FLEN) +NAN_BOXED(63009,16,FLEN) +NAN_BOXED(30241,16,FLEN) +NAN_BOXED(63009,16,FLEN) +NAN_BOXED(30241,16,FLEN) +NAN_BOXED(63009,16,FLEN) +NAN_BOXED(30241,16,FLEN) +NAN_BOXED(63009,16,FLEN) +NAN_BOXED(30679,16,FLEN) +NAN_BOXED(63447,16,FLEN) +NAN_BOXED(30679,16,FLEN) +NAN_BOXED(63447,16,FLEN) +NAN_BOXED(30679,16,FLEN) +NAN_BOXED(63447,16,FLEN) +NAN_BOXED(30679,16,FLEN) +NAN_BOXED(63447,16,FLEN) +NAN_BOXED(30679,16,FLEN) +NAN_BOXED(63447,16,FLEN) +NAN_BOXED(30944,16,FLEN) +NAN_BOXED(63712,16,FLEN) +NAN_BOXED(30944,16,FLEN) +NAN_BOXED(63712,16,FLEN) +NAN_BOXED(30944,16,FLEN) +NAN_BOXED(63712,16,FLEN) +NAN_BOXED(30944,16,FLEN) +NAN_BOXED(63712,16,FLEN) +NAN_BOXED(30944,16,FLEN) +NAN_BOXED(63712,16,FLEN) +NAN_BOXED(30990,16,FLEN) +NAN_BOXED(63758,16,FLEN) +NAN_BOXED(30990,16,FLEN) +NAN_BOXED(63758,16,FLEN) +NAN_BOXED(30990,16,FLEN) +NAN_BOXED(63758,16,FLEN) +NAN_BOXED(30990,16,FLEN) +NAN_BOXED(63758,16,FLEN) +NAN_BOXED(30990,16,FLEN) +NAN_BOXED(63758,16,FLEN) +NAN_BOXED(28660,16,FLEN) +NAN_BOXED(61428,16,FLEN) +NAN_BOXED(28660,16,FLEN) +NAN_BOXED(61428,16,FLEN) +NAN_BOXED(28660,16,FLEN) +NAN_BOXED(61428,16,FLEN) +NAN_BOXED(28660,16,FLEN) +NAN_BOXED(61428,16,FLEN) +NAN_BOXED(28660,16,FLEN) +NAN_BOXED(61428,16,FLEN) +NAN_BOXED(31424,16,FLEN) +NAN_BOXED(64192,16,FLEN) +NAN_BOXED(31424,16,FLEN) +NAN_BOXED(64192,16,FLEN) +NAN_BOXED(30742,16,FLEN) +NAN_BOXED(63510,16,FLEN) +NAN_BOXED(30623,16,FLEN) +NAN_BOXED(63391,16,FLEN) +NAN_BOXED(31554,16,FLEN) +NAN_BOXED(64322,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 34*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x7_0: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x7_1: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x7_2: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x7_3: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x7_4: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x7_5: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x7_6: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x7_7: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x7_8: + .fill 88*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fadd_b4-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fadd_b4-01.S new file mode 100644 index 000000000..e8aa5a0c1 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fadd_b4-01.S @@ -0,0 +1,1524 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 05:45:15 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fadd.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fadd.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fadd_b4 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fadd_b4) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x4,test_dataset_0) +RVTEST_SIGBASE(x13,signature_x13_1) + +inst_0: +// rs1 == rs2 != rd, rs1==x19, rs2==x19, rd==x5,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0f9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x19; op2:x19; dest:x5; op1val:0x7ac0; op2val:0x7ac0; + valaddr_reg:x4; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fadd.h, x5, x19, x19, dyn, 0, 0, x4, 0*FLEN/8, x15, x13, x6) + +inst_1: +// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==x3, rs2==x1, rd==x23,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0f9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x3; op2:x1; dest:x23; op1val:0x7ac0; op2val:0x70f9; + valaddr_reg:x4; val_offset:2*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fadd.h, x23, x3, x1, dyn, 32, 0, x4, 2*FLEN/8, x15, x13, x6) + +inst_2: +// rs1 == rs2 == rd, rs1==x0, rs2==x0, rd==x0,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0f9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x0; op2:x0; dest:x0; op1val:0x0; op2val:0x0; + valaddr_reg:x4; val_offset:4*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fadd.h, x0, x0, x0, dyn, 64, 0, x4, 4*FLEN/8, x15, x13, x6) + +inst_3: +// rs2 == rd != rs1, rs1==x23, rs2==x16, rd==x16,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0f9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x23; op2:x16; dest:x16; op1val:0x7ac0; op2val:0x70f9; + valaddr_reg:x4; val_offset:6*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fadd.h, x16, x23, x16, dyn, 96, 0, x4, 6*FLEN/8, x15, x13, x6) + +inst_4: +// rs1 == rd != rs2, rs1==x29, rs2==x26, rd==x29,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0f9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x29; op2:x26; dest:x29; op1val:0x7ac0; op2val:0x70f9; + valaddr_reg:x4; val_offset:8*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fadd.h, x29, x29, x26, dyn, 128, 0, x4, 8*FLEN/8, x15, x13, x6) + +inst_5: +// rs1==x28, rs2==x24, rd==x26,fs1 == 0 and fe1 == 0x1d and fm1 == 0x2b9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x28; op2:x24; dest:x26; op1val:0x76b9; op2val:0xfbff; + valaddr_reg:x4; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fadd.h, x26, x28, x24, dyn, 0, 0, x4, 10*FLEN/8, x15, x13, x6) + +inst_6: +// rs1==x16, rs2==x5, rd==x8,fs1 == 0 and fe1 == 0x1d and fm1 == 0x2b9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x16; op2:x5; dest:x8; op1val:0x76b9; op2val:0xfbff; + valaddr_reg:x4; val_offset:12*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fadd.h, x8, x16, x5, dyn, 32, 0, x4, 12*FLEN/8, x15, x13, x6) + +inst_7: +// rs1==x31, rs2==x12, rd==x2,fs1 == 0 and fe1 == 0x1d and fm1 == 0x2b9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x31; op2:x12; dest:x2; op1val:0x76b9; op2val:0xfbff; + valaddr_reg:x4; val_offset:14*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fadd.h, x2, x31, x12, dyn, 64, 0, x4, 14*FLEN/8, x15, x13, x6) + +inst_8: +// rs1==x2, rs2==x27, rd==x30,fs1 == 0 and fe1 == 0x1d and fm1 == 0x2b9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x2; op2:x27; dest:x30; op1val:0x76b9; op2val:0xfbff; + valaddr_reg:x4; val_offset:16*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fadd.h, x30, x2, x27, dyn, 96, 0, x4, 16*FLEN/8, x15, x13, x6) + +inst_9: +// rs1==x14, rs2==x18, rd==x22,fs1 == 0 and fe1 == 0x1d and fm1 == 0x2b9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x14; op2:x18; dest:x22; op1val:0x76b9; op2val:0xfbff; + valaddr_reg:x4; val_offset:18*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fadd.h, x22, x14, x18, dyn, 128, 0, x4, 18*FLEN/8, x15, x13, x6) + +inst_10: +// rs1==x11, rs2==x28, rd==x12,fs1 == 0 and fe1 == 0x1e and fm1 == 0x016 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3d0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x11; op2:x28; dest:x12; op1val:0x7816; op2val:0x77d0; + valaddr_reg:x4; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fadd.h, x12, x11, x28, dyn, 0, 0, x4, 20*FLEN/8, x15, x13, x6) + +inst_11: +// rs1==x9, rs2==x10, rd==x7,fs1 == 0 and fe1 == 0x1e and fm1 == 0x016 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3d0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x9; op2:x10; dest:x7; op1val:0x7816; op2val:0x77d0; + valaddr_reg:x4; val_offset:22*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fadd.h, x7, x9, x10, dyn, 32, 0, x4, 22*FLEN/8, x15, x13, x6) +RVTEST_VALBASEUPD(x9,test_dataset_1) + +inst_12: +// rs1==x1, rs2==x30, rd==x11,fs1 == 0 and fe1 == 0x1e and fm1 == 0x016 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3d0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x1; op2:x30; dest:x11; op1val:0x7816; op2val:0x77d0; + valaddr_reg:x9; val_offset:0*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fadd.h, x11, x1, x30, dyn, 64, 0, x9, 0*FLEN/8, x10, x13, x6) + +inst_13: +// rs1==x26, rs2==x8, rd==x24,fs1 == 0 and fe1 == 0x1e and fm1 == 0x016 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3d0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x26; op2:x8; dest:x24; op1val:0x7816; op2val:0x77d0; + valaddr_reg:x9; val_offset:2*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fadd.h, x24, x26, x8, dyn, 96, 0, x9, 2*FLEN/8, x10, x13, x6) + +inst_14: +// rs1==x7, rs2==x4, rd==x25,fs1 == 0 and fe1 == 0x1e and fm1 == 0x016 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3d0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x7; op2:x4; dest:x25; op1val:0x7816; op2val:0x77d0; + valaddr_reg:x9; val_offset:4*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fadd.h, x25, x7, x4, dyn, 128, 0, x9, 4*FLEN/8, x10, x13, x6) + +inst_15: +// rs1==x20, rs2==x6, rd==x14,fs1 == 0 and fe1 == 0x1e and fm1 == 0x244 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x20; op2:x6; dest:x14; op1val:0x7a44; op2val:0xfbff; + valaddr_reg:x9; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x16 +*/ +TEST_FPRR_OP(fadd.h, x14, x20, x6, dyn, 0, 0, x9, 6*FLEN/8, x10, x13, x16) +RVTEST_SIGBASE(x12,signature_x12_0) + +inst_16: +// rs1==x5, rs2==x21, rd==x4,fs1 == 0 and fe1 == 0x1e and fm1 == 0x244 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x5; op2:x21; dest:x4; op1val:0x7a44; op2val:0xfbff; + valaddr_reg:x9; val_offset:8*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x16 +*/ +TEST_FPRR_OP(fadd.h, x4, x5, x21, dyn, 32, 0, x9, 8*FLEN/8, x10, x12, x16) + +inst_17: +// rs1==x30, rs2==x2, rd==x20,fs1 == 0 and fe1 == 0x1e and fm1 == 0x244 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x2; dest:x20; op1val:0x7a44; op2val:0xfbff; + valaddr_reg:x9; val_offset:10*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x16 +*/ +TEST_FPRR_OP(fadd.h, x20, x30, x2, dyn, 64, 0, x9, 10*FLEN/8, x10, x12, x16) + +inst_18: +// rs1==x22, rs2==x7, rd==x31,fs1 == 0 and fe1 == 0x1e and fm1 == 0x244 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x22; op2:x7; dest:x31; op1val:0x7a44; op2val:0xfbff; + valaddr_reg:x9; val_offset:12*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x16 +*/ +TEST_FPRR_OP(fadd.h, x31, x22, x7, dyn, 96, 0, x9, 12*FLEN/8, x10, x12, x16) + +inst_19: +// rs1==x6, rs2==x3, rd==x28,fs1 == 0 and fe1 == 0x1e and fm1 == 0x244 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x6; op2:x3; dest:x28; op1val:0x7a44; op2val:0xfbff; + valaddr_reg:x9; val_offset:14*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x16 +*/ +TEST_FPRR_OP(fadd.h, x28, x6, x3, dyn, 128, 0, x9, 14*FLEN/8, x10, x12, x16) + +inst_20: +// rs1==x4, rs2==x20, rd==x15,fs1 == 0 and fe1 == 0x1d and fm1 == 0x39f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x4; op2:x20; dest:x15; op1val:0x779f; op2val:0x782f; + valaddr_reg:x9; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x16 +*/ +TEST_FPRR_OP(fadd.h, x15, x4, x20, dyn, 0, 0, x9, 16*FLEN/8, x10, x12, x16) + +inst_21: +// rs1==x13, rs2==x11, rd==x18,fs1 == 0 and fe1 == 0x1d and fm1 == 0x39f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x13; op2:x11; dest:x18; op1val:0x779f; op2val:0x782f; + valaddr_reg:x9; val_offset:18*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x16 +*/ +TEST_FPRR_OP(fadd.h, x18, x13, x11, dyn, 32, 0, x9, 18*FLEN/8, x10, x12, x16) + +inst_22: +// rs1==x8, rs2==x13, rd==x17,fs1 == 0 and fe1 == 0x1d and fm1 == 0x39f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x8; op2:x13; dest:x17; op1val:0x779f; op2val:0x782f; + valaddr_reg:x9; val_offset:20*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x16 +*/ +TEST_FPRR_OP(fadd.h, x17, x8, x13, dyn, 64, 0, x9, 20*FLEN/8, x10, x12, x16) +RVTEST_VALBASEUPD(x4,test_dataset_2) + +inst_23: +// rs1==x17, rs2==x25, rd==x3,fs1 == 0 and fe1 == 0x1d and fm1 == 0x39f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x17; op2:x25; dest:x3; op1val:0x779f; op2val:0x782f; + valaddr_reg:x4; val_offset:0*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x16 +*/ +TEST_FPRR_OP(fadd.h, x3, x17, x25, dyn, 96, 0, x4, 0*FLEN/8, x5, x12, x16) + +inst_24: +// rs1==x18, rs2==x22, rd==x13,fs1 == 0 and fe1 == 0x1d and fm1 == 0x39f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x18; op2:x22; dest:x13; op1val:0x779f; op2val:0x782f; + valaddr_reg:x4; val_offset:2*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x16 +*/ +TEST_FPRR_OP(fadd.h, x13, x18, x22, dyn, 128, 0, x4, 2*FLEN/8, x5, x12, x16) + +inst_25: +// rs1==x25, rs2==x15, rd==x1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x342 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x25; op2:x15; dest:x1; op1val:0x7b42; op2val:0xfbff; + valaddr_reg:x4; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x16 +*/ +TEST_FPRR_OP(fadd.h, x1, x25, x15, dyn, 0, 0, x4, 4*FLEN/8, x5, x12, x16) + +inst_26: +// rs1==x15, rs2==x14, rd==x6,fs1 == 0 and fe1 == 0x1e and fm1 == 0x342 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x15; op2:x14; dest:x6; op1val:0x7b42; op2val:0xfbff; + valaddr_reg:x4; val_offset:6*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x16 +*/ +TEST_FPRR_OP(fadd.h, x6, x15, x14, dyn, 32, 0, x4, 6*FLEN/8, x5, x12, x16) + +inst_27: +// rs1==x27, rs2==x17, rd==x19,fs1 == 0 and fe1 == 0x1e and fm1 == 0x342 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x27; op2:x17; dest:x19; op1val:0x7b42; op2val:0xfbff; + valaddr_reg:x4; val_offset:8*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x16 +*/ +TEST_FPRR_OP(fadd.h, x19, x27, x17, dyn, 64, 0, x4, 8*FLEN/8, x5, x12, x16) + +inst_28: +// rs1==x10, rs2==x23, rd==x9,fs1 == 0 and fe1 == 0x1e and fm1 == 0x342 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x10; op2:x23; dest:x9; op1val:0x7b42; op2val:0xfbff; + valaddr_reg:x4; val_offset:10*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x16 +*/ +TEST_FPRR_OP(fadd.h, x9, x10, x23, dyn, 96, 0, x4, 10*FLEN/8, x5, x12, x16) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_29: +// rs1==x24, rs2==x9, rd==x21,fs1 == 0 and fe1 == 0x1e and fm1 == 0x342 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x24; op2:x9; dest:x21; op1val:0x7b42; op2val:0xfbff; + valaddr_reg:x4; val_offset:12*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x21, x24, x9, dyn, 128, 0, x4, 12*FLEN/8, x5, x1, x2) + +inst_30: +// rs1==x21, rs2==x29, rd==x27,fs1 == 0 and fe1 == 0x1d and fm1 == 0x081 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1be and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x21; op2:x29; dest:x27; op1val:0x7481; op2val:0x79be; + valaddr_reg:x4; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x27, x21, x29, dyn, 0, 0, x4, 14*FLEN/8, x5, x1, x2) + +inst_31: +// rs1==x12, rs2==x31, rd==x10,fs1 == 0 and fe1 == 0x1d and fm1 == 0x081 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1be and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x12; op2:x31; dest:x10; op1val:0x7481; op2val:0x79be; + valaddr_reg:x4; val_offset:16*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x10, x12, x31, dyn, 32, 0, x4, 16*FLEN/8, x5, x1, x2) + +inst_32: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x081 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1be and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7481; op2val:0x79be; + valaddr_reg:x4; val_offset:18*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 18*FLEN/8, x5, x1, x2) + +inst_33: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x081 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1be and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7481; op2val:0x79be; + valaddr_reg:x4; val_offset:20*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 20*FLEN/8, x5, x1, x2) + +inst_34: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x081 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1be and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7481; op2val:0x79be; + valaddr_reg:x4; val_offset:22*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 22*FLEN/8, x5, x1, x2) + +inst_35: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0f1 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78f1; op2val:0xfbff; + valaddr_reg:x4; val_offset:24*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 24*FLEN/8, x5, x1, x2) + +inst_36: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0f1 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78f1; op2val:0xfbff; + valaddr_reg:x4; val_offset:26*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 26*FLEN/8, x5, x1, x2) + +inst_37: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0f1 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78f1; op2val:0xfbff; + valaddr_reg:x4; val_offset:28*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 28*FLEN/8, x5, x1, x2) + +inst_38: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0f1 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78f1; op2val:0xfbff; + valaddr_reg:x4; val_offset:30*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 30*FLEN/8, x5, x1, x2) + +inst_39: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0f1 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78f1; op2val:0xfbff; + valaddr_reg:x4; val_offset:32*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 32*FLEN/8, x5, x1, x2) + +inst_40: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x346 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x1c5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b46; op2val:0x6dc5; + valaddr_reg:x4; val_offset:34*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 34*FLEN/8, x5, x1, x2) + +inst_41: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x346 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x1c5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b46; op2val:0x6dc5; + valaddr_reg:x4; val_offset:36*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 36*FLEN/8, x5, x1, x2) + +inst_42: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x346 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x1c5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b46; op2val:0x6dc5; + valaddr_reg:x4; val_offset:38*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 38*FLEN/8, x5, x1, x2) + +inst_43: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x346 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x1c5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b46; op2val:0x6dc5; + valaddr_reg:x4; val_offset:40*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 40*FLEN/8, x5, x1, x2) + +inst_44: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x346 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x1c5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b46; op2val:0x6dc5; + valaddr_reg:x4; val_offset:42*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 42*FLEN/8, x5, x1, x2) + +inst_45: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x27a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a7a; op2val:0xfbff; + valaddr_reg:x4; val_offset:44*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 44*FLEN/8, x5, x1, x2) + +inst_46: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x27a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a7a; op2val:0xfbff; + valaddr_reg:x4; val_offset:46*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 46*FLEN/8, x5, x1, x2) + +inst_47: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x27a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a7a; op2val:0xfbff; + valaddr_reg:x4; val_offset:48*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 48*FLEN/8, x5, x1, x2) + +inst_48: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x27a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a7a; op2val:0xfbff; + valaddr_reg:x4; val_offset:50*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 50*FLEN/8, x5, x1, x2) + +inst_49: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x27a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a7a; op2val:0xfbff; + valaddr_reg:x4; val_offset:52*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 52*FLEN/8, x5, x1, x2) + +inst_50: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x184 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x74f5; op2val:0x7984; + valaddr_reg:x4; val_offset:54*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 54*FLEN/8, x5, x1, x2) + +inst_51: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x184 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x74f5; op2val:0x7984; + valaddr_reg:x4; val_offset:56*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 56*FLEN/8, x5, x1, x2) + +inst_52: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x184 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x74f5; op2val:0x7984; + valaddr_reg:x4; val_offset:58*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 58*FLEN/8, x5, x1, x2) + +inst_53: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x184 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x74f5; op2val:0x7984; + valaddr_reg:x4; val_offset:60*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 60*FLEN/8, x5, x1, x2) + +inst_54: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x184 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x74f5; op2val:0x7984; + valaddr_reg:x4; val_offset:62*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 62*FLEN/8, x5, x1, x2) + +inst_55: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b2f; op2val:0xfbff; + valaddr_reg:x4; val_offset:64*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 64*FLEN/8, x5, x1, x2) + +inst_56: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b2f; op2val:0xfbff; + valaddr_reg:x4; val_offset:66*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 66*FLEN/8, x5, x1, x2) + +inst_57: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b2f; op2val:0xfbff; + valaddr_reg:x4; val_offset:68*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 68*FLEN/8, x5, x1, x2) + +inst_58: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b2f; op2val:0xfbff; + valaddr_reg:x4; val_offset:70*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 70*FLEN/8, x5, x1, x2) + +inst_59: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b2f; op2val:0xfbff; + valaddr_reg:x4; val_offset:72*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 72*FLEN/8, x5, x1, x2) + +inst_60: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x38c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x038 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x778c; op2val:0x7838; + valaddr_reg:x4; val_offset:74*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 74*FLEN/8, x5, x1, x2) + +inst_61: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x38c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x038 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x778c; op2val:0x7838; + valaddr_reg:x4; val_offset:76*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 76*FLEN/8, x5, x1, x2) + +inst_62: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x38c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x038 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x778c; op2val:0x7838; + valaddr_reg:x4; val_offset:78*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 78*FLEN/8, x5, x1, x2) + +inst_63: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x38c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x038 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x778c; op2val:0x7838; + valaddr_reg:x4; val_offset:80*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 80*FLEN/8, x5, x1, x2) + +inst_64: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x38c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x038 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x778c; op2val:0x7838; + valaddr_reg:x4; val_offset:82*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 82*FLEN/8, x5, x1, x2) + +inst_65: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2f1 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x76f1; op2val:0xfbff; + valaddr_reg:x4; val_offset:84*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 84*FLEN/8, x5, x1, x2) + +inst_66: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2f1 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x76f1; op2val:0xfbff; + valaddr_reg:x4; val_offset:86*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 86*FLEN/8, x5, x1, x2) + +inst_67: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2f1 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x76f1; op2val:0xfbff; + valaddr_reg:x4; val_offset:88*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 88*FLEN/8, x5, x1, x2) + +inst_68: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2f1 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x76f1; op2val:0xfbff; + valaddr_reg:x4; val_offset:90*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 90*FLEN/8, x5, x1, x2) + +inst_69: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2f1 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x76f1; op2val:0xfbff; + valaddr_reg:x4; val_offset:92*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 92*FLEN/8, x5, x1, x2) + +inst_70: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x34c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x24d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b4c; op2val:0xfa4d; + valaddr_reg:x4; val_offset:94*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 94*FLEN/8, x5, x1, x2) + +inst_71: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x34c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x24d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b4c; op2val:0xfa4d; + valaddr_reg:x4; val_offset:96*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 96*FLEN/8, x5, x1, x2) + +inst_72: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x34c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x24d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b4c; op2val:0xfa4d; + valaddr_reg:x4; val_offset:98*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 98*FLEN/8, x5, x1, x2) + +inst_73: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x34c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x24d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b4c; op2val:0xfa4d; + valaddr_reg:x4; val_offset:100*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 100*FLEN/8, x5, x1, x2) + +inst_74: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x34c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x24d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b4c; op2val:0xfa4d; + valaddr_reg:x4; val_offset:102*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 102*FLEN/8, x5, x1, x2) + +inst_75: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0d0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77a0; op2val:0xf8d0; + valaddr_reg:x4; val_offset:104*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 104*FLEN/8, x5, x1, x2) + +inst_76: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0d0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77a0; op2val:0xf8d0; + valaddr_reg:x4; val_offset:106*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 106*FLEN/8, x5, x1, x2) + +inst_77: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0d0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77a0; op2val:0xf8d0; + valaddr_reg:x4; val_offset:108*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 108*FLEN/8, x5, x1, x2) + +inst_78: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0d0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77a0; op2val:0xf8d0; + valaddr_reg:x4; val_offset:110*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 110*FLEN/8, x5, x1, x2) + +inst_79: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0d0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77a0; op2val:0xf8d0; + valaddr_reg:x4; val_offset:112*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 112*FLEN/8, x5, x1, x2) + +inst_80: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x02a and fs2 == 1 and fe2 == 0x18 and fm2 == 0x160 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x742a; op2val:0xe160; + valaddr_reg:x4; val_offset:114*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 114*FLEN/8, x5, x1, x2) + +inst_81: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x02a and fs2 == 1 and fe2 == 0x18 and fm2 == 0x160 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x742a; op2val:0xe160; + valaddr_reg:x4; val_offset:116*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 116*FLEN/8, x5, x1, x2) + +inst_82: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x02a and fs2 == 1 and fe2 == 0x18 and fm2 == 0x160 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x742a; op2val:0xe160; + valaddr_reg:x4; val_offset:118*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 118*FLEN/8, x5, x1, x2) + +inst_83: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x02a and fs2 == 1 and fe2 == 0x18 and fm2 == 0x160 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x742a; op2val:0xe160; + valaddr_reg:x4; val_offset:120*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 120*FLEN/8, x5, x1, x2) + +inst_84: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x02a and fs2 == 1 and fe2 == 0x18 and fm2 == 0x160 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x742a; op2val:0xe160; + valaddr_reg:x4; val_offset:122*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 122*FLEN/8, x5, x1, x2) + +inst_85: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x063 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x262 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7863; op2val:0xfa62; + valaddr_reg:x4; val_offset:124*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 124*FLEN/8, x5, x1, x2) + +inst_86: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x063 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x262 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7863; op2val:0xfa62; + valaddr_reg:x4; val_offset:126*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 126*FLEN/8, x5, x1, x2) + +inst_87: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x063 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x262 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7863; op2val:0xfa62; + valaddr_reg:x4; val_offset:128*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 128*FLEN/8, x5, x1, x2) + +inst_88: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x063 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x262 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7863; op2val:0xfa62; + valaddr_reg:x4; val_offset:130*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 130*FLEN/8, x5, x1, x2) + +inst_89: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x063 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x262 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7863; op2val:0xfa62; + valaddr_reg:x4; val_offset:132*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 132*FLEN/8, x5, x1, x2) + +inst_90: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c1 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x306 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c1; op2val:0xf306; + valaddr_reg:x4; val_offset:134*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 134*FLEN/8, x5, x1, x2) + +inst_91: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c1 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x306 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c1; op2val:0xf306; + valaddr_reg:x4; val_offset:136*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 136*FLEN/8, x5, x1, x2) + +inst_92: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c1 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x306 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c1; op2val:0xf306; + valaddr_reg:x4; val_offset:138*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 138*FLEN/8, x5, x1, x2) + +inst_93: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c1 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x306 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c1; op2val:0xf306; + valaddr_reg:x4; val_offset:140*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 140*FLEN/8, x5, x1, x2) + +inst_94: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c1 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x306 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c1; op2val:0xf306; + valaddr_reg:x4; val_offset:142*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 142*FLEN/8, x5, x1, x2) + +inst_95: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x298 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a98; op2val:0xfbff; + valaddr_reg:x4; val_offset:144*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 144*FLEN/8, x5, x1, x2) + +inst_96: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x298 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a98; op2val:0xfbff; + valaddr_reg:x4; val_offset:146*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 146*FLEN/8, x5, x1, x2) + +inst_97: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x298 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a98; op2val:0xfbff; + valaddr_reg:x4; val_offset:148*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 148*FLEN/8, x5, x1, x2) + +inst_98: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x298 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a98; op2val:0xfbff; + valaddr_reg:x4; val_offset:150*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 150*FLEN/8, x5, x1, x2) + +inst_99: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x298 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a98; op2val:0xfbff; + valaddr_reg:x4; val_offset:152*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 152*FLEN/8, x5, x1, x2) + +inst_100: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x0bd and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x54bd; op2val:0x7bfc; + valaddr_reg:x4; val_offset:154*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 154*FLEN/8, x5, x1, x2) + +inst_101: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x0bd and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3fc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x54bd; op2val:0x7bfc; + valaddr_reg:x4; val_offset:156*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 156*FLEN/8, x5, x1, x2) + +inst_102: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x0bd and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3fc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x54bd; op2val:0x7bfc; + valaddr_reg:x4; val_offset:158*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 158*FLEN/8, x5, x1, x2) + +inst_103: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x0bd and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3fc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x54bd; op2val:0x7bfc; + valaddr_reg:x4; val_offset:160*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 160*FLEN/8, x5, x1, x2) + +inst_104: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x0bd and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3fc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x54bd; op2val:0x7bfc; + valaddr_reg:x4; val_offset:162*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 162*FLEN/8, x5, x1, x2) + +inst_105: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aef; op2val:0xfbff; + valaddr_reg:x4; val_offset:164*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 164*FLEN/8, x5, x1, x2) + +inst_106: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aef; op2val:0xfbff; + valaddr_reg:x4; val_offset:166*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 166*FLEN/8, x5, x1, x2) + +inst_107: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aef; op2val:0xfbff; + valaddr_reg:x4; val_offset:168*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 168*FLEN/8, x5, x1, x2) + +inst_108: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aef; op2val:0xfbff; + valaddr_reg:x4; val_offset:170*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 170*FLEN/8, x5, x1, x2) + +inst_109: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aef; op2val:0xfbff; + valaddr_reg:x4; val_offset:172*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 172*FLEN/8, x5, x1, x2) + +inst_110: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x133 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7533; op2val:0x7bff; + valaddr_reg:x4; val_offset:174*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 174*FLEN/8, x5, x1, x2) + +inst_111: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x133 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7533; op2val:0x7bff; + valaddr_reg:x4; val_offset:176*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 176*FLEN/8, x5, x1, x2) + +inst_112: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x133 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7533; op2val:0x7bff; + valaddr_reg:x4; val_offset:178*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 178*FLEN/8, x5, x1, x2) + +inst_113: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x133 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7533; op2val:0x7bff; + valaddr_reg:x4; val_offset:180*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 180*FLEN/8, x5, x1, x2) + +inst_114: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x133 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7533; op2val:0x7bff; + valaddr_reg:x4; val_offset:182*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 182*FLEN/8, x5, x1, x2) + +inst_115: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x21c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x721c; op2val:0xfbff; + valaddr_reg:x4; val_offset:184*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 184*FLEN/8, x5, x1, x2) + +inst_116: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x21c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x721c; op2val:0xfbff; + valaddr_reg:x4; val_offset:186*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 186*FLEN/8, x5, x1, x2) + +inst_117: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x21c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x721c; op2val:0xfbff; + valaddr_reg:x4; val_offset:188*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 188*FLEN/8, x5, x1, x2) + +inst_118: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x21c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x721c; op2val:0xfbff; + valaddr_reg:x4; val_offset:190*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 190*FLEN/8, x5, x1, x2) + +inst_119: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x21c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x721c; op2val:0xfbff; + valaddr_reg:x4; val_offset:192*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 192*FLEN/8, x5, x1, x2) + +inst_120: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x73a1; op2val:0x7bff; + valaddr_reg:x4; val_offset:194*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 194*FLEN/8, x5, x1, x2) + +inst_121: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x73a1; op2val:0x7bff; + valaddr_reg:x4; val_offset:196*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 196*FLEN/8, x5, x1, x2) + +inst_122: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x73a1; op2val:0x7bff; + valaddr_reg:x4; val_offset:198*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 198*FLEN/8, x5, x1, x2) + +inst_123: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x73a1; op2val:0x7bff; + valaddr_reg:x4; val_offset:200*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 200*FLEN/8, x5, x1, x2) + +inst_124: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x73a1; op2val:0x7bff; + valaddr_reg:x4; val_offset:202*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 202*FLEN/8, x5, x1, x2) + +inst_125: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a6c; op2val:0xfbff; + valaddr_reg:x4; val_offset:204*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 204*FLEN/8, x5, x1, x2) + +inst_126: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a6c; op2val:0xfbff; + valaddr_reg:x4; val_offset:206*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 206*FLEN/8, x5, x1, x2) + +inst_127: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a6c; op2val:0xfbff; + valaddr_reg:x4; val_offset:208*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 208*FLEN/8, x5, x1, x2) + +inst_128: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a6c; op2val:0xfbff; + valaddr_reg:x4; val_offset:210*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 210*FLEN/8, x5, x1, x2) + +inst_129: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a6c; op2val:0xfbff; + valaddr_reg:x4; val_offset:212*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 212*FLEN/8, x5, x1, x2) + +inst_130: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x125 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d25; op2val:0x7bff; + valaddr_reg:x4; val_offset:214*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 214*FLEN/8, x5, x1, x2) + +inst_131: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x125 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d25; op2val:0x7bff; + valaddr_reg:x4; val_offset:216*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 216*FLEN/8, x5, x1, x2) + +inst_132: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x125 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d25; op2val:0x7bff; + valaddr_reg:x4; val_offset:218*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 218*FLEN/8, x5, x1, x2) + +inst_133: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x125 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d25; op2val:0x7bff; + valaddr_reg:x4; val_offset:220*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 220*FLEN/8, x5, x1, x2) + +inst_134: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x125 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d25; op2val:0x7bff; + valaddr_reg:x4; val_offset:222*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 222*FLEN/8, x5, x1, x2) + +inst_135: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x780f; op2val:0xfbff; + valaddr_reg:x4; val_offset:224*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 224*FLEN/8, x5, x1, x2) + +inst_136: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x780f; op2val:0xfbff; + valaddr_reg:x4; val_offset:226*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x4, 226*FLEN/8, x5, x1, x2) + +inst_137: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x780f; op2val:0xfbff; + valaddr_reg:x4; val_offset:228*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 228*FLEN/8, x5, x1, x2) + +inst_138: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x780f; op2val:0xfbff; + valaddr_reg:x4; val_offset:230*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x4, 230*FLEN/8, x5, x1, x2) + +inst_139: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x780f; op2val:0xfbff; + valaddr_reg:x4; val_offset:232*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x4, 232*FLEN/8, x5, x1, x2) + +inst_140: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0f9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ac0; op2val:0x70f9; + valaddr_reg:x4; val_offset:234*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 234*FLEN/8, x5, x1, x2) + +inst_141: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0f9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ac0; op2val:0x70f9; + valaddr_reg:x4; val_offset:236*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x4, 236*FLEN/8, x5, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(31424,32,FLEN) +NAN_BOXED(31424,32,FLEN) +NAN_BOXED(31424,32,FLEN) +NAN_BOXED(28921,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31424,32,FLEN) +NAN_BOXED(28921,32,FLEN) +NAN_BOXED(31424,32,FLEN) +NAN_BOXED(28921,32,FLEN) +NAN_BOXED(30393,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30393,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30393,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30393,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30393,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30742,32,FLEN) +NAN_BOXED(30672,32,FLEN) +NAN_BOXED(30742,32,FLEN) +NAN_BOXED(30672,32,FLEN) +test_dataset_1: +NAN_BOXED(30742,32,FLEN) +NAN_BOXED(30672,32,FLEN) +NAN_BOXED(30742,32,FLEN) +NAN_BOXED(30672,32,FLEN) +NAN_BOXED(30742,32,FLEN) +NAN_BOXED(30672,32,FLEN) +NAN_BOXED(31300,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31300,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31300,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31300,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31300,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30623,32,FLEN) +NAN_BOXED(30767,32,FLEN) +NAN_BOXED(30623,32,FLEN) +NAN_BOXED(30767,32,FLEN) +NAN_BOXED(30623,32,FLEN) +NAN_BOXED(30767,32,FLEN) +test_dataset_2: +NAN_BOXED(30623,16,FLEN) +NAN_BOXED(30767,16,FLEN) +NAN_BOXED(30623,16,FLEN) +NAN_BOXED(30767,16,FLEN) +NAN_BOXED(31554,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31554,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31554,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31554,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31554,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29825,16,FLEN) +NAN_BOXED(31166,16,FLEN) +NAN_BOXED(29825,16,FLEN) +NAN_BOXED(31166,16,FLEN) +NAN_BOXED(29825,16,FLEN) +NAN_BOXED(31166,16,FLEN) +NAN_BOXED(29825,16,FLEN) +NAN_BOXED(31166,16,FLEN) +NAN_BOXED(29825,16,FLEN) +NAN_BOXED(31166,16,FLEN) +NAN_BOXED(30961,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30961,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30961,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30961,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30961,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31558,16,FLEN) +NAN_BOXED(28101,16,FLEN) +NAN_BOXED(31558,16,FLEN) +NAN_BOXED(28101,16,FLEN) +NAN_BOXED(31558,16,FLEN) +NAN_BOXED(28101,16,FLEN) +NAN_BOXED(31558,16,FLEN) +NAN_BOXED(28101,16,FLEN) +NAN_BOXED(31558,16,FLEN) +NAN_BOXED(28101,16,FLEN) +NAN_BOXED(31354,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31354,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31354,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31354,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31354,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29941,16,FLEN) +NAN_BOXED(31108,16,FLEN) +NAN_BOXED(29941,16,FLEN) +NAN_BOXED(31108,16,FLEN) +NAN_BOXED(29941,16,FLEN) +NAN_BOXED(31108,16,FLEN) +NAN_BOXED(29941,16,FLEN) +NAN_BOXED(31108,16,FLEN) +NAN_BOXED(29941,16,FLEN) +NAN_BOXED(31108,16,FLEN) +NAN_BOXED(31535,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31535,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31535,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31535,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31535,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30604,16,FLEN) +NAN_BOXED(30776,16,FLEN) +NAN_BOXED(30604,16,FLEN) +NAN_BOXED(30776,16,FLEN) +NAN_BOXED(30604,16,FLEN) +NAN_BOXED(30776,16,FLEN) +NAN_BOXED(30604,16,FLEN) +NAN_BOXED(30776,16,FLEN) +NAN_BOXED(30604,16,FLEN) +NAN_BOXED(30776,16,FLEN) +NAN_BOXED(30449,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30449,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30449,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30449,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30449,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31564,16,FLEN) +NAN_BOXED(64077,16,FLEN) +NAN_BOXED(31564,16,FLEN) +NAN_BOXED(64077,16,FLEN) +NAN_BOXED(31564,16,FLEN) +NAN_BOXED(64077,16,FLEN) +NAN_BOXED(31564,16,FLEN) +NAN_BOXED(64077,16,FLEN) +NAN_BOXED(31564,16,FLEN) +NAN_BOXED(64077,16,FLEN) +NAN_BOXED(30624,16,FLEN) +NAN_BOXED(63696,16,FLEN) +NAN_BOXED(30624,16,FLEN) +NAN_BOXED(63696,16,FLEN) +NAN_BOXED(30624,16,FLEN) +NAN_BOXED(63696,16,FLEN) +NAN_BOXED(30624,16,FLEN) +NAN_BOXED(63696,16,FLEN) +NAN_BOXED(30624,16,FLEN) +NAN_BOXED(63696,16,FLEN) +NAN_BOXED(29738,16,FLEN) +NAN_BOXED(57696,16,FLEN) +NAN_BOXED(29738,16,FLEN) +NAN_BOXED(57696,16,FLEN) +NAN_BOXED(29738,16,FLEN) +NAN_BOXED(57696,16,FLEN) +NAN_BOXED(29738,16,FLEN) +NAN_BOXED(57696,16,FLEN) +NAN_BOXED(29738,16,FLEN) +NAN_BOXED(57696,16,FLEN) +NAN_BOXED(30819,16,FLEN) +NAN_BOXED(64098,16,FLEN) +NAN_BOXED(30819,16,FLEN) +NAN_BOXED(64098,16,FLEN) +NAN_BOXED(30819,16,FLEN) +NAN_BOXED(64098,16,FLEN) +NAN_BOXED(30819,16,FLEN) +NAN_BOXED(64098,16,FLEN) +NAN_BOXED(30819,16,FLEN) +NAN_BOXED(64098,16,FLEN) +NAN_BOXED(31169,16,FLEN) +NAN_BOXED(62214,16,FLEN) +NAN_BOXED(31169,16,FLEN) +NAN_BOXED(62214,16,FLEN) +NAN_BOXED(31169,16,FLEN) +NAN_BOXED(62214,16,FLEN) +NAN_BOXED(31169,16,FLEN) +NAN_BOXED(62214,16,FLEN) +NAN_BOXED(31169,16,FLEN) +NAN_BOXED(62214,16,FLEN) +NAN_BOXED(31384,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31384,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31384,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31384,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31384,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(21693,16,FLEN) +NAN_BOXED(31740,16,FLEN) +NAN_BOXED(21693,16,FLEN) +NAN_BOXED(31740,16,FLEN) +NAN_BOXED(21693,16,FLEN) +NAN_BOXED(31740,16,FLEN) +NAN_BOXED(21693,16,FLEN) +NAN_BOXED(31740,16,FLEN) +NAN_BOXED(21693,16,FLEN) +NAN_BOXED(31740,16,FLEN) +NAN_BOXED(31471,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31471,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31471,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31471,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31471,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30003,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30003,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30003,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30003,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30003,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29212,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29212,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29212,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29212,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29212,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29601,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29601,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29601,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29601,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29601,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31340,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31340,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31340,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31340,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31340,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(27941,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(27941,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(27941,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(27941,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(27941,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30735,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30735,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30735,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30735,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30735,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31424,16,FLEN) +NAN_BOXED(28921,16,FLEN) +NAN_BOXED(31424,16,FLEN) +NAN_BOXED(28921,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x13_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x13_1: + .fill 32*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x12_0: + .fill 26*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_0: + .fill 226*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fadd_b5-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fadd_b5-01.S new file mode 100644 index 000000000..e239acc9f --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fadd_b5-01.S @@ -0,0 +1,2329 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 05:45:15 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fadd.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fadd.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fadd_b5 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fadd_b5) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x17,test_dataset_0) +RVTEST_SIGBASE(x10,signature_x10_1) + +inst_0: +// rs1 == rs2 != rd, rs1==x4, rs2==x4, rd==x25,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x4; op2:x4; dest:x25; op1val:0x7ac0; op2val:0x7ac0; + valaddr_reg:x17; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x25, x4, x4, dyn, 0, 0, x17, 0*FLEN/8, x19, x10, x1) + +inst_1: +// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==x15, rs2==x3, rd==x22,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2c0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x15; op2:x3; dest:x22; op1val:0x7ac0; op2val:0xfac0; + valaddr_reg:x17; val_offset:2*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x22, x15, x3, dyn, 32, 0, x17, 2*FLEN/8, x19, x10, x1) + +inst_2: +// rs1 == rs2 == rd, rs1==x0, rs2==x0, rd==x0,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2c0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x0; op2:x0; dest:x0; op1val:0x0; op2val:0x0; + valaddr_reg:x17; val_offset:4*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x0, x0, x0, dyn, 64, 0, x17, 4*FLEN/8, x19, x10, x1) + +inst_3: +// rs2 == rd != rs1, rs1==x18, rs2==x6, rd==x6,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2c0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x18; op2:x6; dest:x6; op1val:0x7ac0; op2val:0xfac0; + valaddr_reg:x17; val_offset:6*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x6, x18, x6, dyn, 96, 0, x17, 6*FLEN/8, x19, x10, x1) + +inst_4: +// rs1 == rd != rs2, rs1==x29, rs2==x14, rd==x29,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2c0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x29; op2:x14; dest:x29; op1val:0x7ac0; op2val:0xfac0; + valaddr_reg:x17; val_offset:8*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x29, x29, x14, dyn, 128, 0, x17, 8*FLEN/8, x19, x10, x1) + +inst_5: +// rs1==x5, rs2==x26, rd==x28,fs1 == 0 and fe1 == 0x1d and fm1 == 0x2b9 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2b9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x5; op2:x26; dest:x28; op1val:0x76b9; op2val:0xf6b9; + valaddr_reg:x17; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x28, x5, x26, dyn, 0, 0, x17, 10*FLEN/8, x19, x10, x1) + +inst_6: +// rs1==x21, rs2==x9, rd==x14,fs1 == 0 and fe1 == 0x1d and fm1 == 0x2b9 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2b9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x21; op2:x9; dest:x14; op1val:0x76b9; op2val:0xf6b9; + valaddr_reg:x17; val_offset:12*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x14, x21, x9, dyn, 32, 0, x17, 12*FLEN/8, x19, x10, x1) + +inst_7: +// rs1==x3, rs2==x16, rd==x9,fs1 == 0 and fe1 == 0x1d and fm1 == 0x2b9 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2b9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x3; op2:x16; dest:x9; op1val:0x76b9; op2val:0xf6b9; + valaddr_reg:x17; val_offset:14*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x9, x3, x16, dyn, 64, 0, x17, 14*FLEN/8, x19, x10, x1) + +inst_8: +// rs1==x7, rs2==x11, rd==x4,fs1 == 0 and fe1 == 0x1d and fm1 == 0x2b9 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2b9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x7; op2:x11; dest:x4; op1val:0x76b9; op2val:0xf6b9; + valaddr_reg:x17; val_offset:16*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x4, x7, x11, dyn, 96, 0, x17, 16*FLEN/8, x19, x10, x1) + +inst_9: +// rs1==x13, rs2==x15, rd==x30,fs1 == 0 and fe1 == 0x1d and fm1 == 0x2b9 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2b9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x13; op2:x15; dest:x30; op1val:0x76b9; op2val:0xf6b9; + valaddr_reg:x17; val_offset:18*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x30, x13, x15, dyn, 128, 0, x17, 18*FLEN/8, x19, x10, x1) + +inst_10: +// rs1==x26, rs2==x22, rd==x2,fs1 == 0 and fe1 == 0x1e and fm1 == 0x016 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x016 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x26; op2:x22; dest:x2; op1val:0x7816; op2val:0xf816; + valaddr_reg:x17; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x2, x26, x22, dyn, 0, 0, x17, 20*FLEN/8, x19, x10, x1) + +inst_11: +// rs1==x6, rs2==x8, rd==x16,fs1 == 0 and fe1 == 0x1e and fm1 == 0x016 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x016 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x6; op2:x8; dest:x16; op1val:0x7816; op2val:0xf816; + valaddr_reg:x17; val_offset:22*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x16, x6, x8, dyn, 32, 0, x17, 22*FLEN/8, x19, x10, x1) + +inst_12: +// rs1==x30, rs2==x20, rd==x12,fs1 == 0 and fe1 == 0x1e and fm1 == 0x016 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x016 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x20; dest:x12; op1val:0x7816; op2val:0xf816; + valaddr_reg:x17; val_offset:24*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x12, x30, x20, dyn, 64, 0, x17, 24*FLEN/8, x19, x10, x1) +RVTEST_VALBASEUPD(x2,test_dataset_1) + +inst_13: +// rs1==x17, rs2==x27, rd==x26,fs1 == 0 and fe1 == 0x1e and fm1 == 0x016 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x016 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x17; op2:x27; dest:x26; op1val:0x7816; op2val:0xf816; + valaddr_reg:x2; val_offset:0*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fadd.h, x26, x17, x27, dyn, 96, 0, x2, 0*FLEN/8, x7, x10, x1) + +inst_14: +// rs1==x1, rs2==x24, rd==x23,fs1 == 0 and fe1 == 0x1e and fm1 == 0x016 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x016 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x1; op2:x24; dest:x23; op1val:0x7816; op2val:0xf816; + valaddr_reg:x2; val_offset:2*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fadd.h, x23, x1, x24, dyn, 128, 0, x2, 2*FLEN/8, x7, x10, x6) +RVTEST_SIGBASE(x4,signature_x4_0) + +inst_15: +// rs1==x22, rs2==x17, rd==x20,fs1 == 0 and fe1 == 0x1e and fm1 == 0x244 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x244 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x22; op2:x17; dest:x20; op1val:0x7a44; op2val:0xfa44; + valaddr_reg:x2; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fadd.h, x20, x22, x17, dyn, 0, 0, x2, 4*FLEN/8, x7, x4, x6) + +inst_16: +// rs1==x14, rs2==x31, rd==x8,fs1 == 0 and fe1 == 0x1e and fm1 == 0x244 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x244 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x14; op2:x31; dest:x8; op1val:0x7a44; op2val:0xfa44; + valaddr_reg:x2; val_offset:6*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fadd.h, x8, x14, x31, dyn, 32, 0, x2, 6*FLEN/8, x7, x4, x6) + +inst_17: +// rs1==x31, rs2==x12, rd==x19,fs1 == 0 and fe1 == 0x1e and fm1 == 0x244 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x244 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x31; op2:x12; dest:x19; op1val:0x7a44; op2val:0xfa44; + valaddr_reg:x2; val_offset:8*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fadd.h, x19, x31, x12, dyn, 64, 0, x2, 8*FLEN/8, x7, x4, x6) + +inst_18: +// rs1==x23, rs2==x21, rd==x24,fs1 == 0 and fe1 == 0x1e and fm1 == 0x244 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x244 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x23; op2:x21; dest:x24; op1val:0x7a44; op2val:0xfa44; + valaddr_reg:x2; val_offset:10*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fadd.h, x24, x23, x21, dyn, 96, 0, x2, 10*FLEN/8, x7, x4, x6) + +inst_19: +// rs1==x11, rs2==x19, rd==x31,fs1 == 0 and fe1 == 0x1e and fm1 == 0x244 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x244 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x11; op2:x19; dest:x31; op1val:0x7a44; op2val:0xfa44; + valaddr_reg:x2; val_offset:12*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fadd.h, x31, x11, x19, dyn, 128, 0, x2, 12*FLEN/8, x7, x4, x6) + +inst_20: +// rs1==x24, rs2==x10, rd==x17,fs1 == 0 and fe1 == 0x1d and fm1 == 0x39f and fs2 == 1 and fe2 == 0x1d and fm2 == 0x39f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x24; op2:x10; dest:x17; op1val:0x779f; op2val:0xf79f; + valaddr_reg:x2; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fadd.h, x17, x24, x10, dyn, 0, 0, x2, 14*FLEN/8, x7, x4, x6) + +inst_21: +// rs1==x16, rs2==x1, rd==x3,fs1 == 0 and fe1 == 0x1d and fm1 == 0x39f and fs2 == 1 and fe2 == 0x1d and fm2 == 0x39f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x16; op2:x1; dest:x3; op1val:0x779f; op2val:0xf79f; + valaddr_reg:x2; val_offset:16*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fadd.h, x3, x16, x1, dyn, 32, 0, x2, 16*FLEN/8, x7, x4, x6) + +inst_22: +// rs1==x27, rs2==x30, rd==x21,fs1 == 0 and fe1 == 0x1d and fm1 == 0x39f and fs2 == 1 and fe2 == 0x1d and fm2 == 0x39f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x27; op2:x30; dest:x21; op1val:0x779f; op2val:0xf79f; + valaddr_reg:x2; val_offset:18*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fadd.h, x21, x27, x30, dyn, 64, 0, x2, 18*FLEN/8, x7, x4, x6) + +inst_23: +// rs1==x10, rs2==x29, rd==x5,fs1 == 0 and fe1 == 0x1d and fm1 == 0x39f and fs2 == 1 and fe2 == 0x1d and fm2 == 0x39f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x10; op2:x29; dest:x5; op1val:0x779f; op2val:0xf79f; + valaddr_reg:x2; val_offset:20*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fadd.h, x5, x10, x29, dyn, 96, 0, x2, 20*FLEN/8, x7, x4, x6) + +inst_24: +// rs1==x12, rs2==x28, rd==x18,fs1 == 0 and fe1 == 0x1d and fm1 == 0x39f and fs2 == 1 and fe2 == 0x1d and fm2 == 0x39f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x12; op2:x28; dest:x18; op1val:0x779f; op2val:0xf79f; + valaddr_reg:x2; val_offset:22*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fadd.h, x18, x12, x28, dyn, 128, 0, x2, 22*FLEN/8, x7, x4, x6) +RVTEST_VALBASEUPD(x3,test_dataset_2) + +inst_25: +// rs1==x19, rs2==x2, rd==x27,fs1 == 0 and fe1 == 0x1e and fm1 == 0x342 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x342 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x19; op2:x2; dest:x27; op1val:0x7b42; op2val:0xfb42; + valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fadd.h, x27, x19, x2, dyn, 0, 0, x3, 0*FLEN/8, x14, x4, x6) + +inst_26: +// rs1==x2, rs2==x13, rd==x15,fs1 == 0 and fe1 == 0x1e and fm1 == 0x342 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x342 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x2; op2:x13; dest:x15; op1val:0x7b42; op2val:0xfb42; + valaddr_reg:x3; val_offset:2*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fadd.h, x15, x2, x13, dyn, 32, 0, x3, 2*FLEN/8, x14, x4, x6) + +inst_27: +// rs1==x28, rs2==x18, rd==x1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x342 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x342 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x28; op2:x18; dest:x1; op1val:0x7b42; op2val:0xfb42; + valaddr_reg:x3; val_offset:4*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x1, x28, x18, dyn, 64, 0, x3, 4*FLEN/8, x14, x4, x2) + +inst_28: +// rs1==x25, rs2==x5, rd==x13,fs1 == 0 and fe1 == 0x1e and fm1 == 0x342 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x342 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x25; op2:x5; dest:x13; op1val:0x7b42; op2val:0xfb42; + valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x13, x25, x5, dyn, 96, 0, x3, 6*FLEN/8, x14, x4, x2) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_29: +// rs1==x9, rs2==x25, rd==x11,fs1 == 0 and fe1 == 0x1e and fm1 == 0x342 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x342 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x9; op2:x25; dest:x11; op1val:0x7b42; op2val:0xfb42; + valaddr_reg:x3; val_offset:8*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x11, x9, x25, dyn, 128, 0, x3, 8*FLEN/8, x14, x1, x2) + +inst_30: +// rs1==x20, rs2==x23, rd==x10,fs1 == 0 and fe1 == 0x1d and fm1 == 0x081 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x081 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x20; op2:x23; dest:x10; op1val:0x7481; op2val:0xf481; + valaddr_reg:x3; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x10, x20, x23, dyn, 0, 0, x3, 10*FLEN/8, x14, x1, x2) + +inst_31: +// rs1==x8,fs1 == 0 and fe1 == 0x1d and fm1 == 0x081 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x081 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x8; op2:x11; dest:x25; op1val:0x7481; op2val:0xf481; + valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x25, x8, x11, dyn, 32, 0, x3, 12*FLEN/8, x14, x1, x2) + +inst_32: +// rs2==x7,fs1 == 0 and fe1 == 0x1d and fm1 == 0x081 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x081 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x22; op2:x7; dest:x19; op1val:0x7481; op2val:0xf481; + valaddr_reg:x3; val_offset:14*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x19, x22, x7, dyn, 64, 0, x3, 14*FLEN/8, x14, x1, x2) + +inst_33: +// rd==x7,fs1 == 0 and fe1 == 0x1d and fm1 == 0x081 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x081 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x13; op2:x12; dest:x7; op1val:0x7481; op2val:0xf481; + valaddr_reg:x3; val_offset:16*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x7, x13, x12, dyn, 96, 0, x3, 16*FLEN/8, x14, x1, x2) + +inst_34: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x081 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x081 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7481; op2val:0xf481; + valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x3, 18*FLEN/8, x14, x1, x2) + +inst_35: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0f1 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0f1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78f1; op2val:0xf8f1; + valaddr_reg:x3; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x3, 20*FLEN/8, x14, x1, x2) + +inst_36: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0f1 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0f1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78f1; op2val:0xf8f1; + valaddr_reg:x3; val_offset:22*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x3, 22*FLEN/8, x14, x1, x2) + +inst_37: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0f1 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0f1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78f1; op2val:0xf8f1; + valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x3, 24*FLEN/8, x14, x1, x2) + +inst_38: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0f1 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0f1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78f1; op2val:0xf8f1; + valaddr_reg:x3; val_offset:26*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x3, 26*FLEN/8, x14, x1, x2) + +inst_39: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0f1 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0f1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78f1; op2val:0xf8f1; + valaddr_reg:x3; val_offset:28*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x3, 28*FLEN/8, x14, x1, x2) + +inst_40: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x346 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x346 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b46; op2val:0xfb46; + valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x3, 30*FLEN/8, x14, x1, x2) + +inst_41: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x346 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x346 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b46; op2val:0xfb46; + valaddr_reg:x3; val_offset:32*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x3, 32*FLEN/8, x14, x1, x2) + +inst_42: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x346 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x346 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b46; op2val:0xfb46; + valaddr_reg:x3; val_offset:34*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x3, 34*FLEN/8, x14, x1, x2) + +inst_43: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x346 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x346 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b46; op2val:0xfb46; + valaddr_reg:x3; val_offset:36*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x3, 36*FLEN/8, x14, x1, x2) + +inst_44: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x346 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x346 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b46; op2val:0xfb46; + valaddr_reg:x3; val_offset:38*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x3, 38*FLEN/8, x14, x1, x2) + +inst_45: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x27a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x27a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a7a; op2val:0xfa7a; + valaddr_reg:x3; val_offset:40*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x3, 40*FLEN/8, x14, x1, x2) + +inst_46: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x27a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x27a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a7a; op2val:0xfa7a; + valaddr_reg:x3; val_offset:42*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x3, 42*FLEN/8, x14, x1, x2) + +inst_47: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x27a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x27a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a7a; op2val:0xfa7a; + valaddr_reg:x3; val_offset:44*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x3, 44*FLEN/8, x14, x1, x2) + +inst_48: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x27a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x27a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a7a; op2val:0xfa7a; + valaddr_reg:x3; val_offset:46*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x3, 46*FLEN/8, x14, x1, x2) + +inst_49: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x27a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x27a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a7a; op2val:0xfa7a; + valaddr_reg:x3; val_offset:48*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x3, 48*FLEN/8, x14, x1, x2) + +inst_50: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f5 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x0f5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x74f5; op2val:0xf4f5; + valaddr_reg:x3; val_offset:50*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x3, 50*FLEN/8, x14, x1, x2) + +inst_51: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f5 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x0f5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x74f5; op2val:0xf4f5; + valaddr_reg:x3; val_offset:52*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x3, 52*FLEN/8, x14, x1, x2) + +inst_52: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f5 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x0f5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x74f5; op2val:0xf4f5; + valaddr_reg:x3; val_offset:54*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x3, 54*FLEN/8, x14, x1, x2) + +inst_53: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f5 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x0f5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x74f5; op2val:0xf4f5; + valaddr_reg:x3; val_offset:56*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x3, 56*FLEN/8, x14, x1, x2) + +inst_54: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f5 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x0f5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x74f5; op2val:0xf4f5; + valaddr_reg:x3; val_offset:58*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x3, 58*FLEN/8, x14, x1, x2) + +inst_55: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x32f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b2f; op2val:0xfb2f; + valaddr_reg:x3; val_offset:60*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x3, 60*FLEN/8, x14, x1, x2) + +inst_56: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x32f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b2f; op2val:0xfb2f; + valaddr_reg:x3; val_offset:62*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x3, 62*FLEN/8, x14, x1, x2) + +inst_57: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x32f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b2f; op2val:0xfb2f; + valaddr_reg:x3; val_offset:64*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x3, 64*FLEN/8, x14, x1, x2) + +inst_58: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x32f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b2f; op2val:0xfb2f; + valaddr_reg:x3; val_offset:66*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x3, 66*FLEN/8, x14, x1, x2) + +inst_59: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x32f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b2f; op2val:0xfb2f; + valaddr_reg:x3; val_offset:68*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x3, 68*FLEN/8, x14, x1, x2) + +inst_60: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x38c and fs2 == 1 and fe2 == 0x1d and fm2 == 0x38c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x778c; op2val:0xf78c; + valaddr_reg:x3; val_offset:70*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x3, 70*FLEN/8, x14, x1, x2) + +inst_61: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x38c and fs2 == 1 and fe2 == 0x1d and fm2 == 0x38c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x778c; op2val:0xf78c; + valaddr_reg:x3; val_offset:72*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x3, 72*FLEN/8, x14, x1, x2) + +inst_62: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x38c and fs2 == 1 and fe2 == 0x1d and fm2 == 0x38c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x778c; op2val:0xf78c; + valaddr_reg:x3; val_offset:74*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x3, 74*FLEN/8, x14, x1, x2) + +inst_63: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x38c and fs2 == 1 and fe2 == 0x1d and fm2 == 0x38c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x778c; op2val:0xf78c; + valaddr_reg:x3; val_offset:76*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x3, 76*FLEN/8, x14, x1, x2) + +inst_64: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x38c and fs2 == 1 and fe2 == 0x1d and fm2 == 0x38c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x778c; op2val:0xf78c; + valaddr_reg:x3; val_offset:78*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x3, 78*FLEN/8, x14, x1, x2) + +inst_65: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2f1 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2f1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x76f1; op2val:0xf6f1; + valaddr_reg:x3; val_offset:80*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x3, 80*FLEN/8, x14, x1, x2) + +inst_66: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2f1 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2f1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x76f1; op2val:0xf6f1; + valaddr_reg:x3; val_offset:82*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x3, 82*FLEN/8, x14, x1, x2) + +inst_67: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2f1 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2f1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x76f1; op2val:0xf6f1; + valaddr_reg:x3; val_offset:84*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x3, 84*FLEN/8, x14, x1, x2) + +inst_68: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2f1 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2f1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x76f1; op2val:0xf6f1; + valaddr_reg:x3; val_offset:86*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x3, 86*FLEN/8, x14, x1, x2) + +inst_69: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2f1 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2f1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x76f1; op2val:0xf6f1; + valaddr_reg:x3; val_offset:88*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x3, 88*FLEN/8, x14, x1, x2) + +inst_70: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x34c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x34c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b4c; op2val:0xfb4c; + valaddr_reg:x3; val_offset:90*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x3, 90*FLEN/8, x14, x1, x2) + +inst_71: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x34c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x34c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b4c; op2val:0xfb4c; + valaddr_reg:x3; val_offset:92*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x3, 92*FLEN/8, x14, x1, x2) + +inst_72: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x34c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x34c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b4c; op2val:0xfb4c; + valaddr_reg:x3; val_offset:94*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x3, 94*FLEN/8, x14, x1, x2) + +inst_73: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x34c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x34c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b4c; op2val:0xfb4c; + valaddr_reg:x3; val_offset:96*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x3, 96*FLEN/8, x14, x1, x2) + +inst_74: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x34c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x34c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b4c; op2val:0xfb4c; + valaddr_reg:x3; val_offset:98*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x3, 98*FLEN/8, x14, x1, x2) + +inst_75: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a0 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3a0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77a0; op2val:0xf7a0; + valaddr_reg:x3; val_offset:100*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x3, 100*FLEN/8, x14, x1, x2) + +inst_76: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a0 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3a0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77a0; op2val:0xf7a0; + valaddr_reg:x3; val_offset:102*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x3, 102*FLEN/8, x14, x1, x2) + +inst_77: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a0 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3a0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77a0; op2val:0xf7a0; + valaddr_reg:x3; val_offset:104*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x3, 104*FLEN/8, x14, x1, x2) + +inst_78: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a0 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3a0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77a0; op2val:0xf7a0; + valaddr_reg:x3; val_offset:106*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x3, 106*FLEN/8, x14, x1, x2) + +inst_79: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a0 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3a0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x77a0; op2val:0xf7a0; + valaddr_reg:x3; val_offset:108*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x3, 108*FLEN/8, x14, x1, x2) + +inst_80: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x02a and fs2 == 1 and fe2 == 0x1d and fm2 == 0x02a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x742a; op2val:0xf42a; + valaddr_reg:x3; val_offset:110*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x3, 110*FLEN/8, x14, x1, x2) + +inst_81: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x02a and fs2 == 1 and fe2 == 0x1d and fm2 == 0x02a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x742a; op2val:0xf42a; + valaddr_reg:x3; val_offset:112*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x3, 112*FLEN/8, x14, x1, x2) + +inst_82: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x02a and fs2 == 1 and fe2 == 0x1d and fm2 == 0x02a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x742a; op2val:0xf42a; + valaddr_reg:x3; val_offset:114*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x3, 114*FLEN/8, x14, x1, x2) + +inst_83: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x02a and fs2 == 1 and fe2 == 0x1d and fm2 == 0x02a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x742a; op2val:0xf42a; + valaddr_reg:x3; val_offset:116*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x3, 116*FLEN/8, x14, x1, x2) + +inst_84: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x02a and fs2 == 1 and fe2 == 0x1d and fm2 == 0x02a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x742a; op2val:0xf42a; + valaddr_reg:x3; val_offset:118*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x3, 118*FLEN/8, x14, x1, x2) + +inst_85: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x063 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x063 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7863; op2val:0xf863; + valaddr_reg:x3; val_offset:120*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x3, 120*FLEN/8, x14, x1, x2) + +inst_86: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x063 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x063 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7863; op2val:0xf863; + valaddr_reg:x3; val_offset:122*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x3, 122*FLEN/8, x14, x1, x2) + +inst_87: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x063 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x063 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7863; op2val:0xf863; + valaddr_reg:x3; val_offset:124*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x3, 124*FLEN/8, x14, x1, x2) + +inst_88: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x063 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x063 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7863; op2val:0xf863; + valaddr_reg:x3; val_offset:126*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x3, 126*FLEN/8, x14, x1, x2) + +inst_89: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x063 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x063 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7863; op2val:0xf863; + valaddr_reg:x3; val_offset:128*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x3, 128*FLEN/8, x14, x1, x2) + +inst_90: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c1 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1c1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c1; op2val:0xf9c1; + valaddr_reg:x3; val_offset:130*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x3, 130*FLEN/8, x14, x1, x2) + +inst_91: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c1 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1c1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c1; op2val:0xf9c1; + valaddr_reg:x3; val_offset:132*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x3, 132*FLEN/8, x14, x1, x2) + +inst_92: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c1 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1c1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c1; op2val:0xf9c1; + valaddr_reg:x3; val_offset:134*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x3, 134*FLEN/8, x14, x1, x2) + +inst_93: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c1 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1c1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c1; op2val:0xf9c1; + valaddr_reg:x3; val_offset:136*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x3, 136*FLEN/8, x14, x1, x2) + +inst_94: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c1 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1c1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c1; op2val:0xf9c1; + valaddr_reg:x3; val_offset:138*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x3, 138*FLEN/8, x14, x1, x2) + +inst_95: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x298 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x298 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a98; op2val:0xfa98; + valaddr_reg:x3; val_offset:140*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x3, 140*FLEN/8, x14, x1, x2) + +inst_96: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x298 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x298 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a98; op2val:0xfa98; + valaddr_reg:x3; val_offset:142*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x3, 142*FLEN/8, x14, x1, x2) + +inst_97: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x298 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x298 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a98; op2val:0xfa98; + valaddr_reg:x3; val_offset:144*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x3, 144*FLEN/8, x14, x1, x2) + +inst_98: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x298 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x298 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a98; op2val:0xfa98; + valaddr_reg:x3; val_offset:146*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x3, 146*FLEN/8, x14, x1, x2) + +inst_99: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x298 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x298 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a98; op2val:0xfa98; + valaddr_reg:x3; val_offset:148*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x3, 148*FLEN/8, x14, x1, x2) + +inst_100: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x0bd and fs2 == 1 and fe2 == 0x15 and fm2 == 0x0bd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x54bd; op2val:0xd4bd; + valaddr_reg:x3; val_offset:150*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x3, 150*FLEN/8, x14, x1, x2) + +inst_101: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x0bd and fs2 == 1 and fe2 == 0x15 and fm2 == 0x0bd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x54bd; op2val:0xd4bd; + valaddr_reg:x3; val_offset:152*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x3, 152*FLEN/8, x14, x1, x2) + +inst_102: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x0bd and fs2 == 1 and fe2 == 0x15 and fm2 == 0x0bd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x54bd; op2val:0xd4bd; + valaddr_reg:x3; val_offset:154*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x3, 154*FLEN/8, x14, x1, x2) + +inst_103: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x0bd and fs2 == 1 and fe2 == 0x15 and fm2 == 0x0bd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x54bd; op2val:0xd4bd; + valaddr_reg:x3; val_offset:156*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x3, 156*FLEN/8, x14, x1, x2) + +inst_104: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x0bd and fs2 == 1 and fe2 == 0x15 and fm2 == 0x0bd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x54bd; op2val:0xd4bd; + valaddr_reg:x3; val_offset:158*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x3, 158*FLEN/8, x14, x1, x2) + +inst_105: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2ef and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aef; op2val:0xfaef; + valaddr_reg:x3; val_offset:160*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x3, 160*FLEN/8, x14, x1, x2) + +inst_106: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2ef and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aef; op2val:0xfaef; + valaddr_reg:x3; val_offset:162*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x3, 162*FLEN/8, x14, x1, x2) + +inst_107: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2ef and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aef; op2val:0xfaef; + valaddr_reg:x3; val_offset:164*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x3, 164*FLEN/8, x14, x1, x2) + +inst_108: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2ef and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aef; op2val:0xfaef; + valaddr_reg:x3; val_offset:166*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x3, 166*FLEN/8, x14, x1, x2) + +inst_109: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2ef and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aef; op2val:0xfaef; + valaddr_reg:x3; val_offset:168*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x3, 168*FLEN/8, x14, x1, x2) + +inst_110: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x133 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x133 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7533; op2val:0xf533; + valaddr_reg:x3; val_offset:170*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x3, 170*FLEN/8, x14, x1, x2) + +inst_111: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x133 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x133 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7533; op2val:0xf533; + valaddr_reg:x3; val_offset:172*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x3, 172*FLEN/8, x14, x1, x2) + +inst_112: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x133 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x133 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7533; op2val:0xf533; + valaddr_reg:x3; val_offset:174*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x3, 174*FLEN/8, x14, x1, x2) + +inst_113: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x133 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x133 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7533; op2val:0xf533; + valaddr_reg:x3; val_offset:176*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x3, 176*FLEN/8, x14, x1, x2) + +inst_114: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x133 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x133 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7533; op2val:0xf533; + valaddr_reg:x3; val_offset:178*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x3, 178*FLEN/8, x14, x1, x2) + +inst_115: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x21c and fs2 == 1 and fe2 == 0x1c and fm2 == 0x21c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x721c; op2val:0xf21c; + valaddr_reg:x3; val_offset:180*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x3, 180*FLEN/8, x14, x1, x2) + +inst_116: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x21c and fs2 == 1 and fe2 == 0x1c and fm2 == 0x21c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x721c; op2val:0xf21c; + valaddr_reg:x3; val_offset:182*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x3, 182*FLEN/8, x14, x1, x2) + +inst_117: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x21c and fs2 == 1 and fe2 == 0x1c and fm2 == 0x21c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x721c; op2val:0xf21c; + valaddr_reg:x3; val_offset:184*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x3, 184*FLEN/8, x14, x1, x2) + +inst_118: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x21c and fs2 == 1 and fe2 == 0x1c and fm2 == 0x21c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x721c; op2val:0xf21c; + valaddr_reg:x3; val_offset:186*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x3, 186*FLEN/8, x14, x1, x2) + +inst_119: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x21c and fs2 == 1 and fe2 == 0x1c and fm2 == 0x21c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x721c; op2val:0xf21c; + valaddr_reg:x3; val_offset:188*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x3, 188*FLEN/8, x14, x1, x2) + +inst_120: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3a1 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3a1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x73a1; op2val:0xf3a1; + valaddr_reg:x3; val_offset:190*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x3, 190*FLEN/8, x14, x1, x2) + +inst_121: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3a1 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3a1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x73a1; op2val:0xf3a1; + valaddr_reg:x3; val_offset:192*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x3, 192*FLEN/8, x14, x1, x2) + +inst_122: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3a1 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3a1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x73a1; op2val:0xf3a1; + valaddr_reg:x3; val_offset:194*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x3, 194*FLEN/8, x14, x1, x2) + +inst_123: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3a1 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3a1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x73a1; op2val:0xf3a1; + valaddr_reg:x3; val_offset:196*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x3, 196*FLEN/8, x14, x1, x2) + +inst_124: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3a1 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3a1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x73a1; op2val:0xf3a1; + valaddr_reg:x3; val_offset:198*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x3, 198*FLEN/8, x14, x1, x2) + +inst_125: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x26c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a6c; op2val:0xfa6c; + valaddr_reg:x3; val_offset:200*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x3, 200*FLEN/8, x14, x1, x2) + +inst_126: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x26c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a6c; op2val:0xfa6c; + valaddr_reg:x3; val_offset:202*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x3, 202*FLEN/8, x14, x1, x2) + +inst_127: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x26c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a6c; op2val:0xfa6c; + valaddr_reg:x3; val_offset:204*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x3, 204*FLEN/8, x14, x1, x2) + +inst_128: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x26c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a6c; op2val:0xfa6c; + valaddr_reg:x3; val_offset:206*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x3, 206*FLEN/8, x14, x1, x2) + +inst_129: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x26c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a6c; op2val:0xfa6c; + valaddr_reg:x3; val_offset:208*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x3, 208*FLEN/8, x14, x1, x2) + +inst_130: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x125 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x125 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d25; op2val:0xed25; + valaddr_reg:x3; val_offset:210*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x3, 210*FLEN/8, x14, x1, x2) + +inst_131: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x125 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x125 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d25; op2val:0xed25; + valaddr_reg:x3; val_offset:212*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x3, 212*FLEN/8, x14, x1, x2) + +inst_132: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x125 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x125 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d25; op2val:0xed25; + valaddr_reg:x3; val_offset:214*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x3, 214*FLEN/8, x14, x1, x2) + +inst_133: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x125 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x125 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d25; op2val:0xed25; + valaddr_reg:x3; val_offset:216*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x3, 216*FLEN/8, x14, x1, x2) + +inst_134: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x125 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x125 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d25; op2val:0xed25; + valaddr_reg:x3; val_offset:218*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x3, 218*FLEN/8, x14, x1, x2) + +inst_135: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x780f; op2val:0xf80f; + valaddr_reg:x3; val_offset:220*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x3, 220*FLEN/8, x14, x1, x2) + +inst_136: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x00f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x780f; op2val:0xf80f; + valaddr_reg:x3; val_offset:222*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x3, 222*FLEN/8, x14, x1, x2) + +inst_137: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x00f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x780f; op2val:0xf80f; + valaddr_reg:x3; val_offset:224*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x3, 224*FLEN/8, x14, x1, x2) + +inst_138: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x00f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x780f; op2val:0xf80f; + valaddr_reg:x3; val_offset:226*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x3, 226*FLEN/8, x14, x1, x2) + +inst_139: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x00f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x780f; op2val:0xf80f; + valaddr_reg:x3; val_offset:228*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x3, 228*FLEN/8, x14, x1, x2) + +inst_140: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2fa and fs2 == 1 and fe2 == 0x1b and fm2 == 0x2fa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6efa; op2val:0xeefa; + valaddr_reg:x3; val_offset:230*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x3, 230*FLEN/8, x14, x1, x2) + +inst_141: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2fa and fs2 == 1 and fe2 == 0x1b and fm2 == 0x2fa and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6efa; op2val:0xeefa; + valaddr_reg:x3; val_offset:232*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x3, 232*FLEN/8, x14, x1, x2) + +inst_142: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2fa and fs2 == 1 and fe2 == 0x1b and fm2 == 0x2fa and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6efa; op2val:0xeefa; + valaddr_reg:x3; val_offset:234*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x3, 234*FLEN/8, x14, x1, x2) + +inst_143: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2fa and fs2 == 1 and fe2 == 0x1b and fm2 == 0x2fa and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6efa; op2val:0xeefa; + valaddr_reg:x3; val_offset:236*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x3, 236*FLEN/8, x14, x1, x2) + +inst_144: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2fa and fs2 == 1 and fe2 == 0x1b and fm2 == 0x2fa and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6efa; op2val:0xeefa; + valaddr_reg:x3; val_offset:238*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x3, 238*FLEN/8, x14, x1, x2) + +inst_145: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a6 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1a6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79a6; op2val:0xf9a6; + valaddr_reg:x3; val_offset:240*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x3, 240*FLEN/8, x14, x1, x2) + +inst_146: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a6 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1a6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79a6; op2val:0xf9a6; + valaddr_reg:x3; val_offset:242*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x3, 242*FLEN/8, x14, x1, x2) + +inst_147: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a6 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1a6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79a6; op2val:0xf9a6; + valaddr_reg:x3; val_offset:244*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x3, 244*FLEN/8, x14, x1, x2) + +inst_148: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a6 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1a6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79a6; op2val:0xf9a6; + valaddr_reg:x3; val_offset:246*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x3, 246*FLEN/8, x14, x1, x2) + +inst_149: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a6 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1a6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79a6; op2val:0xf9a6; + valaddr_reg:x3; val_offset:248*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x3, 248*FLEN/8, x14, x1, x2) + +inst_150: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x283 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x283 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a83; op2val:0xfa83; + valaddr_reg:x3; val_offset:250*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x3, 250*FLEN/8, x14, x1, x2) + +inst_151: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x283 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x283 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a83; op2val:0xfa83; + valaddr_reg:x3; val_offset:252*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x3, 252*FLEN/8, x14, x1, x2) + +inst_152: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x283 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x283 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a83; op2val:0xfa83; + valaddr_reg:x3; val_offset:254*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x3, 254*FLEN/8, x14, x1, x2) + +inst_153: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x283 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x283 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a83; op2val:0xfa83; + valaddr_reg:x3; val_offset:256*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x3, 256*FLEN/8, x14, x1, x2) + +inst_154: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x283 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x283 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a83; op2val:0xfa83; + valaddr_reg:x3; val_offset:258*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x3, 258*FLEN/8, x14, x1, x2) + +inst_155: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3b4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb4; op2val:0xfbb4; + valaddr_reg:x3; val_offset:260*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x3, 260*FLEN/8, x14, x1, x2) + +inst_156: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3b4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb4; op2val:0xfbb4; + valaddr_reg:x3; val_offset:262*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x3, 262*FLEN/8, x14, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_157: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3b4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb4; op2val:0xfbb4; + valaddr_reg:x3; val_offset:264*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x3, 264*FLEN/8, x14, x1, x2) + +inst_158: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3b4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb4; op2val:0xfbb4; + valaddr_reg:x3; val_offset:266*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x3, 266*FLEN/8, x14, x1, x2) + +inst_159: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3b4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb4; op2val:0xfbb4; + valaddr_reg:x3; val_offset:268*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x3, 268*FLEN/8, x14, x1, x2) + +inst_160: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b2 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0b2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78b2; op2val:0xf8b2; + valaddr_reg:x3; val_offset:270*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x3, 270*FLEN/8, x14, x1, x2) + +inst_161: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b2 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0b2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78b2; op2val:0xf8b2; + valaddr_reg:x3; val_offset:272*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x3, 272*FLEN/8, x14, x1, x2) + +inst_162: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b2 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0b2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78b2; op2val:0xf8b2; + valaddr_reg:x3; val_offset:274*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x3, 274*FLEN/8, x14, x1, x2) + +inst_163: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b2 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0b2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78b2; op2val:0xf8b2; + valaddr_reg:x3; val_offset:276*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x3, 276*FLEN/8, x14, x1, x2) + +inst_164: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b2 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0b2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78b2; op2val:0xf8b2; + valaddr_reg:x3; val_offset:278*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x3, 278*FLEN/8, x14, x1, x2) + +inst_165: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0c4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78c4; op2val:0xf8c4; + valaddr_reg:x3; val_offset:280*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x3, 280*FLEN/8, x14, x1, x2) + +inst_166: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0c4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78c4; op2val:0xf8c4; + valaddr_reg:x3; val_offset:282*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x3, 282*FLEN/8, x14, x1, x2) + +inst_167: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0c4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78c4; op2val:0xf8c4; + valaddr_reg:x3; val_offset:284*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x3, 284*FLEN/8, x14, x1, x2) + +inst_168: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0c4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78c4; op2val:0xf8c4; + valaddr_reg:x3; val_offset:286*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x3, 286*FLEN/8, x14, x1, x2) + +inst_169: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0c4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78c4; op2val:0xf8c4; + valaddr_reg:x3; val_offset:288*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x3, 288*FLEN/8, x14, x1, x2) + +inst_170: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x09a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x789a; op2val:0xf89a; + valaddr_reg:x3; val_offset:290*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x3, 290*FLEN/8, x14, x1, x2) + +inst_171: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x09a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x789a; op2val:0xf89a; + valaddr_reg:x3; val_offset:292*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x3, 292*FLEN/8, x14, x1, x2) + +inst_172: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x09a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x789a; op2val:0xf89a; + valaddr_reg:x3; val_offset:294*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x3, 294*FLEN/8, x14, x1, x2) + +inst_173: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x09a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x789a; op2val:0xf89a; + valaddr_reg:x3; val_offset:296*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x3, 296*FLEN/8, x14, x1, x2) + +inst_174: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x09a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x789a; op2val:0xf89a; + valaddr_reg:x3; val_offset:298*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x3, 298*FLEN/8, x14, x1, x2) + +inst_175: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x20e and fs2 == 1 and fe2 == 0x1c and fm2 == 0x20e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x720e; op2val:0xf20e; + valaddr_reg:x3; val_offset:300*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x3, 300*FLEN/8, x14, x1, x2) + +inst_176: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x20e and fs2 == 1 and fe2 == 0x1c and fm2 == 0x20e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x720e; op2val:0xf20e; + valaddr_reg:x3; val_offset:302*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x3, 302*FLEN/8, x14, x1, x2) + +inst_177: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x20e and fs2 == 1 and fe2 == 0x1c and fm2 == 0x20e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x720e; op2val:0xf20e; + valaddr_reg:x3; val_offset:304*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x3, 304*FLEN/8, x14, x1, x2) + +inst_178: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x20e and fs2 == 1 and fe2 == 0x1c and fm2 == 0x20e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x720e; op2val:0xf20e; + valaddr_reg:x3; val_offset:306*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x3, 306*FLEN/8, x14, x1, x2) + +inst_179: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x20e and fs2 == 1 and fe2 == 0x1c and fm2 == 0x20e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x720e; op2val:0xf20e; + valaddr_reg:x3; val_offset:308*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x3, 308*FLEN/8, x14, x1, x2) + +inst_180: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e6 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0e6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78e6; op2val:0xf8e6; + valaddr_reg:x3; val_offset:310*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x3, 310*FLEN/8, x14, x1, x2) + +inst_181: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e6 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0e6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78e6; op2val:0xf8e6; + valaddr_reg:x3; val_offset:312*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x3, 312*FLEN/8, x14, x1, x2) + +inst_182: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e6 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0e6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78e6; op2val:0xf8e6; + valaddr_reg:x3; val_offset:314*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x3, 314*FLEN/8, x14, x1, x2) + +inst_183: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e6 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0e6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78e6; op2val:0xf8e6; + valaddr_reg:x3; val_offset:316*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x3, 316*FLEN/8, x14, x1, x2) + +inst_184: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e6 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0e6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78e6; op2val:0xf8e6; + valaddr_reg:x3; val_offset:318*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x3, 318*FLEN/8, x14, x1, x2) + +inst_185: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x39e and fs2 == 1 and fe2 == 0x1d and fm2 == 0x39e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x779e; op2val:0xf79e; + valaddr_reg:x3; val_offset:320*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x3, 320*FLEN/8, x14, x1, x2) + +inst_186: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x39e and fs2 == 1 and fe2 == 0x1d and fm2 == 0x39e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x779e; op2val:0xf79e; + valaddr_reg:x3; val_offset:322*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x3, 322*FLEN/8, x14, x1, x2) + +inst_187: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x39e and fs2 == 1 and fe2 == 0x1d and fm2 == 0x39e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x779e; op2val:0xf79e; + valaddr_reg:x3; val_offset:324*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x3, 324*FLEN/8, x14, x1, x2) + +inst_188: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x39e and fs2 == 1 and fe2 == 0x1d and fm2 == 0x39e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x779e; op2val:0xf79e; + valaddr_reg:x3; val_offset:326*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x3, 326*FLEN/8, x14, x1, x2) + +inst_189: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x39e and fs2 == 1 and fe2 == 0x1d and fm2 == 0x39e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x779e; op2val:0xf79e; + valaddr_reg:x3; val_offset:328*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x3, 328*FLEN/8, x14, x1, x2) + +inst_190: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x20e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a0e; op2val:0xfa0e; + valaddr_reg:x3; val_offset:330*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x3, 330*FLEN/8, x14, x1, x2) + +inst_191: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x20e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a0e; op2val:0xfa0e; + valaddr_reg:x3; val_offset:332*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x3, 332*FLEN/8, x14, x1, x2) + +inst_192: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x20e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a0e; op2val:0xfa0e; + valaddr_reg:x3; val_offset:334*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x3, 334*FLEN/8, x14, x1, x2) + +inst_193: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x20e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a0e; op2val:0xfa0e; + valaddr_reg:x3; val_offset:336*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x3, 336*FLEN/8, x14, x1, x2) + +inst_194: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x20e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a0e; op2val:0xfa0e; + valaddr_reg:x3; val_offset:338*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x3, 338*FLEN/8, x14, x1, x2) + +inst_195: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x362 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x362 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b62; op2val:0xfb62; + valaddr_reg:x3; val_offset:340*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x3, 340*FLEN/8, x14, x1, x2) + +inst_196: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x362 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x362 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b62; op2val:0xfb62; + valaddr_reg:x3; val_offset:342*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x3, 342*FLEN/8, x14, x1, x2) + +inst_197: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x362 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x362 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b62; op2val:0xfb62; + valaddr_reg:x3; val_offset:344*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x3, 344*FLEN/8, x14, x1, x2) + +inst_198: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x362 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x362 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b62; op2val:0xfb62; + valaddr_reg:x3; val_offset:346*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x3, 346*FLEN/8, x14, x1, x2) + +inst_199: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x362 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x362 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b62; op2val:0xfb62; + valaddr_reg:x3; val_offset:348*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x3, 348*FLEN/8, x14, x1, x2) + +inst_200: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x32e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b2e; op2val:0xfb2e; + valaddr_reg:x3; val_offset:350*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x3, 350*FLEN/8, x14, x1, x2) + +inst_201: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x32e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b2e; op2val:0xfb2e; + valaddr_reg:x3; val_offset:352*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x3, 352*FLEN/8, x14, x1, x2) + +inst_202: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x32e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b2e; op2val:0xfb2e; + valaddr_reg:x3; val_offset:354*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x3, 354*FLEN/8, x14, x1, x2) + +inst_203: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x32e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b2e; op2val:0xfb2e; + valaddr_reg:x3; val_offset:356*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x3, 356*FLEN/8, x14, x1, x2) + +inst_204: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x32e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b2e; op2val:0xfb2e; + valaddr_reg:x3; val_offset:358*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x3, 358*FLEN/8, x14, x1, x2) + +inst_205: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x052 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x052 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7852; op2val:0xf852; + valaddr_reg:x3; val_offset:360*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x3, 360*FLEN/8, x14, x1, x2) + +inst_206: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x052 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x052 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7852; op2val:0xf852; + valaddr_reg:x3; val_offset:362*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x3, 362*FLEN/8, x14, x1, x2) + +inst_207: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x052 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x052 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7852; op2val:0xf852; + valaddr_reg:x3; val_offset:364*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x3, 364*FLEN/8, x14, x1, x2) + +inst_208: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x052 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x052 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7852; op2val:0xf852; + valaddr_reg:x3; val_offset:366*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x3, 366*FLEN/8, x14, x1, x2) + +inst_209: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x052 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x052 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7852; op2val:0xf852; + valaddr_reg:x3; val_offset:368*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x3, 368*FLEN/8, x14, x1, x2) + +inst_210: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1a3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79a3; op2val:0xf9a3; + valaddr_reg:x3; val_offset:370*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x3, 370*FLEN/8, x14, x1, x2) + +inst_211: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1a3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79a3; op2val:0xf9a3; + valaddr_reg:x3; val_offset:372*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x3, 372*FLEN/8, x14, x1, x2) + +inst_212: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1a3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79a3; op2val:0xf9a3; + valaddr_reg:x3; val_offset:374*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x3, 374*FLEN/8, x14, x1, x2) + +inst_213: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1a3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79a3; op2val:0xf9a3; + valaddr_reg:x3; val_offset:376*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x3, 376*FLEN/8, x14, x1, x2) + +inst_214: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1a3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79a3; op2val:0xf9a3; + valaddr_reg:x3; val_offset:378*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x3, 378*FLEN/8, x14, x1, x2) + +inst_215: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x27d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x27d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a7d; op2val:0xfa7d; + valaddr_reg:x3; val_offset:380*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x3, 380*FLEN/8, x14, x1, x2) + +inst_216: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x27d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x27d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a7d; op2val:0xfa7d; + valaddr_reg:x3; val_offset:382*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x3, 382*FLEN/8, x14, x1, x2) + +inst_217: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x27d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x27d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a7d; op2val:0xfa7d; + valaddr_reg:x3; val_offset:384*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x3, 384*FLEN/8, x14, x1, x2) + +inst_218: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x27d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x27d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a7d; op2val:0xfa7d; + valaddr_reg:x3; val_offset:386*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x3, 386*FLEN/8, x14, x1, x2) + +inst_219: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x27d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x27d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a7d; op2val:0xfa7d; + valaddr_reg:x3; val_offset:388*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x3, 388*FLEN/8, x14, x1, x2) + +inst_220: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ac0; op2val:0xfac0; + valaddr_reg:x3; val_offset:390*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x3, 390*FLEN/8, x14, x1, x2) + +inst_221: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2c0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ac0; op2val:0xfac0; + valaddr_reg:x3; val_offset:392*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x3, 392*FLEN/8, x14, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(31424,32,FLEN) +NAN_BOXED(31424,16,FLEN) +NAN_BOXED(31424,32,FLEN) +NAN_BOXED(64192,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31424,32,FLEN) +NAN_BOXED(64192,16,FLEN) +NAN_BOXED(31424,32,FLEN) +NAN_BOXED(64192,16,FLEN) +NAN_BOXED(30393,32,FLEN) +NAN_BOXED(63161,16,FLEN) +NAN_BOXED(30393,32,FLEN) +NAN_BOXED(63161,16,FLEN) +NAN_BOXED(30393,32,FLEN) +NAN_BOXED(63161,16,FLEN) +NAN_BOXED(30393,32,FLEN) +NAN_BOXED(63161,16,FLEN) +NAN_BOXED(30393,32,FLEN) +NAN_BOXED(63161,16,FLEN) +NAN_BOXED(30742,32,FLEN) +NAN_BOXED(63510,16,FLEN) +NAN_BOXED(30742,32,FLEN) +NAN_BOXED(63510,16,FLEN) +NAN_BOXED(30742,32,FLEN) +NAN_BOXED(63510,16,FLEN) +test_dataset_1: +NAN_BOXED(30742,32,FLEN) +NAN_BOXED(63510,16,FLEN) +NAN_BOXED(30742,32,FLEN) +NAN_BOXED(63510,16,FLEN) +NAN_BOXED(31300,32,FLEN) +NAN_BOXED(64068,16,FLEN) +NAN_BOXED(31300,32,FLEN) +NAN_BOXED(64068,16,FLEN) +NAN_BOXED(31300,32,FLEN) +NAN_BOXED(64068,16,FLEN) +NAN_BOXED(31300,32,FLEN) +NAN_BOXED(64068,16,FLEN) +NAN_BOXED(31300,32,FLEN) +NAN_BOXED(64068,16,FLEN) +NAN_BOXED(30623,32,FLEN) +NAN_BOXED(63391,16,FLEN) +NAN_BOXED(30623,32,FLEN) +NAN_BOXED(63391,16,FLEN) +NAN_BOXED(30623,32,FLEN) +NAN_BOXED(63391,16,FLEN) +NAN_BOXED(30623,32,FLEN) +NAN_BOXED(63391,16,FLEN) +NAN_BOXED(30623,32,FLEN) +NAN_BOXED(63391,16,FLEN) +test_dataset_2: +NAN_BOXED(31554,16,FLEN) +NAN_BOXED(64322,16,FLEN) +NAN_BOXED(31554,16,FLEN) +NAN_BOXED(64322,16,FLEN) +NAN_BOXED(31554,16,FLEN) +NAN_BOXED(64322,16,FLEN) +NAN_BOXED(31554,16,FLEN) +NAN_BOXED(64322,16,FLEN) +NAN_BOXED(31554,16,FLEN) +NAN_BOXED(64322,16,FLEN) +NAN_BOXED(29825,16,FLEN) +NAN_BOXED(62593,16,FLEN) +NAN_BOXED(29825,16,FLEN) +NAN_BOXED(62593,16,FLEN) +NAN_BOXED(29825,16,FLEN) +NAN_BOXED(62593,16,FLEN) +NAN_BOXED(29825,16,FLEN) +NAN_BOXED(62593,16,FLEN) +NAN_BOXED(29825,16,FLEN) +NAN_BOXED(62593,16,FLEN) +NAN_BOXED(30961,16,FLEN) +NAN_BOXED(63729,16,FLEN) +NAN_BOXED(30961,16,FLEN) +NAN_BOXED(63729,16,FLEN) +NAN_BOXED(30961,16,FLEN) +NAN_BOXED(63729,16,FLEN) +NAN_BOXED(30961,16,FLEN) +NAN_BOXED(63729,16,FLEN) +NAN_BOXED(30961,16,FLEN) +NAN_BOXED(63729,16,FLEN) +NAN_BOXED(31558,16,FLEN) +NAN_BOXED(64326,16,FLEN) +NAN_BOXED(31558,16,FLEN) +NAN_BOXED(64326,16,FLEN) +NAN_BOXED(31558,16,FLEN) +NAN_BOXED(64326,16,FLEN) +NAN_BOXED(31558,16,FLEN) +NAN_BOXED(64326,16,FLEN) +NAN_BOXED(31558,16,FLEN) +NAN_BOXED(64326,16,FLEN) +NAN_BOXED(31354,16,FLEN) +NAN_BOXED(64122,16,FLEN) +NAN_BOXED(31354,16,FLEN) +NAN_BOXED(64122,16,FLEN) +NAN_BOXED(31354,16,FLEN) +NAN_BOXED(64122,16,FLEN) +NAN_BOXED(31354,16,FLEN) +NAN_BOXED(64122,16,FLEN) +NAN_BOXED(31354,16,FLEN) +NAN_BOXED(64122,16,FLEN) +NAN_BOXED(29941,16,FLEN) +NAN_BOXED(62709,16,FLEN) +NAN_BOXED(29941,16,FLEN) +NAN_BOXED(62709,16,FLEN) +NAN_BOXED(29941,16,FLEN) +NAN_BOXED(62709,16,FLEN) +NAN_BOXED(29941,16,FLEN) +NAN_BOXED(62709,16,FLEN) +NAN_BOXED(29941,16,FLEN) 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+NAN_BOXED(63570,16,FLEN) +NAN_BOXED(30802,16,FLEN) +NAN_BOXED(63570,16,FLEN) +NAN_BOXED(30802,16,FLEN) +NAN_BOXED(63570,16,FLEN) +NAN_BOXED(30802,16,FLEN) +NAN_BOXED(63570,16,FLEN) +NAN_BOXED(31139,16,FLEN) +NAN_BOXED(63907,16,FLEN) +NAN_BOXED(31139,16,FLEN) +NAN_BOXED(63907,16,FLEN) +NAN_BOXED(31139,16,FLEN) +NAN_BOXED(63907,16,FLEN) +NAN_BOXED(31139,16,FLEN) +NAN_BOXED(63907,16,FLEN) +NAN_BOXED(31139,16,FLEN) +NAN_BOXED(63907,16,FLEN) +NAN_BOXED(31357,16,FLEN) +NAN_BOXED(64125,16,FLEN) +NAN_BOXED(31357,16,FLEN) +NAN_BOXED(64125,16,FLEN) +NAN_BOXED(31357,16,FLEN) +NAN_BOXED(64125,16,FLEN) +NAN_BOXED(31357,16,FLEN) +NAN_BOXED(64125,16,FLEN) +NAN_BOXED(31357,16,FLEN) +NAN_BOXED(64125,16,FLEN) +NAN_BOXED(31424,16,FLEN) +NAN_BOXED(64192,16,FLEN) +NAN_BOXED(31424,16,FLEN) +NAN_BOXED(64192,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x10_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x10_1: + .fill 30*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x4_0: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_0: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 130*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fadd_b7-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fadd_b7-01.S new file mode 100644 index 000000000..b65b93df1 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fadd_b7-01.S @@ -0,0 +1,706 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 05:45:15 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fadd.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fadd.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fadd_b7 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fadd_b7) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x19,test_dataset_0) +RVTEST_SIGBASE(x16,signature_x16_1) + +inst_0: +// rs1 == rs2 != rd, rs1==x21, rs2==x21, rd==x26,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2c0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x21; op2:x21; dest:x26; op1val:0x7ac0; op2val:0x7ac0; + valaddr_reg:x19; val_offset:0*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP(fadd.h, x26, x21, x21, dyn, 96, 0, x19, 0*FLEN/8, x20, x16, x13) + +inst_1: +// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==x5, rs2==x2, rd==x9,fs1 == 0 and fe1 == 0x1d and fm1 == 0x2b9 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2b9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x5; op2:x2; dest:x9; op1val:0x76b9; op2val:0xf6b9; + valaddr_reg:x19; val_offset:2*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP(fadd.h, x9, x5, x2, dyn, 96, 0, x19, 2*FLEN/8, x20, x16, x13) + +inst_2: +// rs1 == rs2 == rd, rs1==x6, rs2==x6, rd==x6,fs1 == 0 and fe1 == 0x1e and fm1 == 0x016 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x016 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x6; op2:x6; dest:x6; op1val:0x7816; op2val:0x7816; + valaddr_reg:x19; val_offset:4*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP(fadd.h, x6, x6, x6, dyn, 96, 0, x19, 4*FLEN/8, x20, x16, x13) + +inst_3: +// rs2 == rd != rs1, rs1==x27, rs2==x30, rd==x30,fs1 == 0 and fe1 == 0x1e and fm1 == 0x244 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x244 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x27; op2:x30; dest:x30; op1val:0x7a44; op2val:0xfa44; + valaddr_reg:x19; val_offset:6*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP(fadd.h, x30, x27, x30, dyn, 96, 0, x19, 6*FLEN/8, x20, x16, x13) + +inst_4: +// rs1 == rd != rs2, rs1==x17, rs2==x11, rd==x17,fs1 == 0 and fe1 == 0x1d and fm1 == 0x39f and fs2 == 1 and fe2 == 0x1d and fm2 == 0x39f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x17; op2:x11; dest:x17; op1val:0x779f; op2val:0xf79f; + valaddr_reg:x19; val_offset:8*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP(fadd.h, x17, x17, x11, dyn, 96, 0, x19, 8*FLEN/8, x20, x16, x13) + +inst_5: +// rs1==x14, rs2==x27, rd==x28,fs1 == 0 and fe1 == 0x1e and fm1 == 0x342 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x342 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x14; op2:x27; dest:x28; op1val:0x7b42; op2val:0xfb42; + valaddr_reg:x19; val_offset:10*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP(fadd.h, x28, x14, x27, dyn, 96, 0, x19, 10*FLEN/8, x20, x16, x13) + +inst_6: +// rs1==x8, rs2==x24, rd==x10,fs1 == 0 and fe1 == 0x1d and fm1 == 0x081 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x081 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x8; op2:x24; dest:x10; op1val:0x7481; op2val:0xf481; + valaddr_reg:x19; val_offset:12*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP(fadd.h, x10, x8, x24, dyn, 96, 0, x19, 12*FLEN/8, x20, x16, x13) + +inst_7: +// rs1==x3, rs2==x18, rd==x24,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0f1 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0f1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x3; op2:x18; dest:x24; op1val:0x78f1; op2val:0xf8f1; + valaddr_reg:x19; val_offset:14*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP(fadd.h, x24, x3, x18, dyn, 96, 0, x19, 14*FLEN/8, x20, x16, x13) + +inst_8: +// rs1==x28, rs2==x15, rd==x7,fs1 == 0 and fe1 == 0x1e and fm1 == 0x346 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x346 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x28; op2:x15; dest:x7; op1val:0x7b46; op2val:0xfb46; + valaddr_reg:x19; val_offset:16*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP(fadd.h, x7, x28, x15, dyn, 96, 0, x19, 16*FLEN/8, x20, x16, x13) + +inst_9: +// rs1==x23, rs2==x31, rd==x12,fs1 == 0 and fe1 == 0x1e and fm1 == 0x27a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x27a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x23; op2:x31; dest:x12; op1val:0x7a7a; op2val:0xfa7a; + valaddr_reg:x19; val_offset:18*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP(fadd.h, x12, x23, x31, dyn, 96, 0, x19, 18*FLEN/8, x20, x16, x13) + +inst_10: +// rs1==x1, rs2==x23, rd==x4,fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f5 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x0f5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x1; op2:x23; dest:x4; op1val:0x74f5; op2val:0xf4f5; + valaddr_reg:x19; val_offset:20*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP(fadd.h, x4, x1, x23, dyn, 96, 0, x19, 20*FLEN/8, x20, x16, x13) +RVTEST_VALBASEUPD(x22,test_dataset_1) + +inst_11: +// rs1==x10, rs2==x14, rd==x19,fs1 == 0 and fe1 == 0x1e and fm1 == 0x32f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x32f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x10; op2:x14; dest:x19; op1val:0x7b2f; op2val:0xfb2f; + valaddr_reg:x22; val_offset:0*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP(fadd.h, x19, x10, x14, dyn, 96, 0, x22, 0*FLEN/8, x23, x16, x13) + +inst_12: +// rs1==x11, rs2==x5, rd==x0,fs1 == 0 and fe1 == 0x1d and fm1 == 0x38c and fs2 == 1 and fe2 == 0x1d and fm2 == 0x38c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x11; op2:x5; dest:x0; op1val:0x778c; op2val:0xf78c; + valaddr_reg:x22; val_offset:2*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fadd.h, x0, x11, x5, dyn, 96, 0, x22, 2*FLEN/8, x23, x16, x6) + +inst_13: +// rs1==x13, rs2==x28, rd==x21,fs1 == 0 and fe1 == 0x1d and fm1 == 0x2f1 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2f1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x13; op2:x28; dest:x21; op1val:0x76f1; op2val:0xf6f1; + valaddr_reg:x22; val_offset:4*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fadd.h, x21, x13, x28, dyn, 96, 0, x22, 4*FLEN/8, x23, x16, x6) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_14: +// rs1==x24, rs2==x17, rd==x15,fs1 == 0 and fe1 == 0x1e and fm1 == 0x34c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x34c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x24; op2:x17; dest:x15; op1val:0x7b4c; op2val:0xfb4c; + valaddr_reg:x22; val_offset:6*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fadd.h, x15, x24, x17, dyn, 96, 0, x22, 6*FLEN/8, x23, x1, x6) + +inst_15: +// rs1==x2, rs2==x20, rd==x3,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a0 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3a0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x2; op2:x20; dest:x3; op1val:0x77a0; op2val:0xf7a0; + valaddr_reg:x22; val_offset:8*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fadd.h, x3, x2, x20, dyn, 96, 0, x22, 8*FLEN/8, x23, x1, x6) + +inst_16: +// rs1==x29, rs2==x8, rd==x18,fs1 == 0 and fe1 == 0x1d and fm1 == 0x02a and fs2 == 1 and fe2 == 0x1d and fm2 == 0x02a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x29; op2:x8; dest:x18; op1val:0x742a; op2val:0xf42a; + valaddr_reg:x22; val_offset:10*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fadd.h, x18, x29, x8, dyn, 96, 0, x22, 10*FLEN/8, x23, x1, x6) + +inst_17: +// rs1==x7, rs2==x13, rd==x31,fs1 == 0 and fe1 == 0x1e and fm1 == 0x063 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x063 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x7; op2:x13; dest:x31; op1val:0x7863; op2val:0xf863; + valaddr_reg:x22; val_offset:12*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fadd.h, x31, x7, x13, dyn, 96, 0, x22, 12*FLEN/8, x23, x1, x6) + +inst_18: +// rs1==x4, rs2==x7, rd==x2,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c1 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1c1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x4; op2:x7; dest:x2; op1val:0x79c1; op2val:0xf9c1; + valaddr_reg:x22; val_offset:14*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fadd.h, x2, x4, x7, dyn, 96, 0, x22, 14*FLEN/8, x23, x1, x6) + +inst_19: +// rs1==x31, rs2==x12, rd==x29,fs1 == 0 and fe1 == 0x1e and fm1 == 0x298 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x298 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x31; op2:x12; dest:x29; op1val:0x7a98; op2val:0xfa98; + valaddr_reg:x22; val_offset:16*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fadd.h, x29, x31, x12, dyn, 96, 0, x22, 16*FLEN/8, x23, x1, x6) + +inst_20: +// rs1==x9, rs2==x16, rd==x20,fs1 == 0 and fe1 == 0x15 and fm1 == 0x0bd and fs2 == 1 and fe2 == 0x15 and fm2 == 0x0bd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x9; op2:x16; dest:x20; op1val:0x54bd; op2val:0xd4bd; + valaddr_reg:x22; val_offset:18*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fadd.h, x20, x9, x16, dyn, 96, 0, x22, 18*FLEN/8, x23, x1, x6) +RVTEST_VALBASEUPD(x7,test_dataset_2) + +inst_21: +// rs1==x0, rs2==x25, rd==x5,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2ef and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x0; op2:x25; dest:x5; op1val:0x0; op2val:0xfaef; + valaddr_reg:x7; val_offset:0*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fadd.h, x5, x0, x25, dyn, 96, 0, x7, 0*FLEN/8, x17, x1, x6) + +inst_22: +// rs1==x12, rs2==x19, rd==x14,fs1 == 0 and fe1 == 0x1d and fm1 == 0x133 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x133 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x12; op2:x19; dest:x14; op1val:0x7533; op2val:0xf533; + valaddr_reg:x7; val_offset:2*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fadd.h, x14, x12, x19, dyn, 96, 0, x7, 2*FLEN/8, x17, x1, x6) + +inst_23: +// rs1==x25, rs2==x10, rd==x22,fs1 == 0 and fe1 == 0x1c and fm1 == 0x21c and fs2 == 1 and fe2 == 0x1c and fm2 == 0x21c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x25; op2:x10; dest:x22; op1val:0x721c; op2val:0xf21c; + valaddr_reg:x7; val_offset:4*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fadd.h, x22, x25, x10, dyn, 96, 0, x7, 4*FLEN/8, x17, x1, x6) + +inst_24: +// rs1==x19, rs2==x4, rd==x13,fs1 == 0 and fe1 == 0x1c and fm1 == 0x3a1 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3a1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x19; op2:x4; dest:x13; op1val:0x73a1; op2val:0xf3a1; + valaddr_reg:x7; val_offset:6*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x13, x19, x4, dyn, 96, 0, x7, 6*FLEN/8, x17, x1, x5) + +inst_25: +// rs1==x22, rs2==x9, rd==x23,fs1 == 0 and fe1 == 0x1e and fm1 == 0x26c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x26c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x22; op2:x9; dest:x23; op1val:0x7a6c; op2val:0xfa6c; + valaddr_reg:x7; val_offset:8*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x23, x22, x9, dyn, 96, 0, x7, 8*FLEN/8, x17, x1, x5) + +inst_26: +// rs1==x30, rs2==x22, rd==x27,fs1 == 0 and fe1 == 0x1b and fm1 == 0x125 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x125 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x22; dest:x27; op1val:0x6d25; op2val:0xed25; + valaddr_reg:x7; val_offset:10*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x27, x30, x22, dyn, 96, 0, x7, 10*FLEN/8, x17, x1, x5) + +inst_27: +// rs1==x18, rs2==x0, rd==x11,fs1 == 0 and fe1 == 0x1e and fm1 == 0x00f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x00f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x18; op2:x0; dest:x11; op1val:0x780f; op2val:0x0; + valaddr_reg:x7; val_offset:12*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x11, x18, x0, dyn, 96, 0, x7, 12*FLEN/8, x17, x1, x5) +RVTEST_SIGBASE(x2,signature_x2_0) + +inst_28: +// rs1==x15, rs2==x3, rd==x8,fs1 == 0 and fe1 == 0x1b and fm1 == 0x2fa and fs2 == 1 and fe2 == 0x1b and fm2 == 0x2fa and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x15; op2:x3; dest:x8; op1val:0x6efa; op2val:0xeefa; + valaddr_reg:x7; val_offset:14*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x8, x15, x3, dyn, 96, 0, x7, 14*FLEN/8, x17, x2, x5) + +inst_29: +// rs1==x26, rs2==x29, rd==x1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a6 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1a6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x26; op2:x29; dest:x1; op1val:0x79a6; op2val:0xf9a6; + valaddr_reg:x7; val_offset:16*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x1, x26, x29, dyn, 96, 0, x7, 16*FLEN/8, x17, x2, x5) + +inst_30: +// rs1==x20, rs2==x26, rd==x25,fs1 == 0 and fe1 == 0x1e and fm1 == 0x283 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x283 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x20; op2:x26; dest:x25; op1val:0x7a83; op2val:0xfa83; + valaddr_reg:x7; val_offset:18*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x25, x20, x26, dyn, 96, 0, x7, 18*FLEN/8, x17, x2, x5) + +inst_31: +// rs1==x16,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3b4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x16; op2:x30; dest:x19; op1val:0x7bb4; op2val:0xfbb4; + valaddr_reg:x7; val_offset:20*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x19, x16, x30, dyn, 96, 0, x7, 20*FLEN/8, x17, x2, x5) +RVTEST_VALBASEUPD(x3,test_dataset_3) + +inst_32: +// rs2==x1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b2 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0b2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x22; op2:x1; dest:x13; op1val:0x78b2; op2val:0xf8b2; + valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x13, x22, x1, dyn, 96, 0, x3, 0*FLEN/8, x4, x2, x5) + +inst_33: +// rd==x16,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0c4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x6; op2:x14; dest:x16; op1val:0x78c4; op2val:0xf8c4; + valaddr_reg:x3; val_offset:2*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x16, x6, x14, dyn, 96, 0, x3, 2*FLEN/8, x4, x2, x5) + +inst_34: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x09a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x789a; op2val:0xf89a; + valaddr_reg:x3; val_offset:4*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x3, 4*FLEN/8, x4, x2, x5) + +inst_35: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x20e and fs2 == 1 and fe2 == 0x1c and fm2 == 0x20e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x720e; op2val:0xf20e; + valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x3, 6*FLEN/8, x4, x2, x5) + +inst_36: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e6 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0e6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x78e6; op2val:0xf8e6; + valaddr_reg:x3; val_offset:8*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x3, 8*FLEN/8, x4, x2, x5) + +inst_37: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x39e and fs2 == 1 and fe2 == 0x1d and fm2 == 0x39e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x779e; op2val:0xf79e; + valaddr_reg:x3; val_offset:10*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x3, 10*FLEN/8, x4, x2, x5) + +inst_38: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x20e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a0e; op2val:0xfa0e; + valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x3, 12*FLEN/8, x4, x2, x5) + +inst_39: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x362 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x362 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b62; op2val:0xfb62; + valaddr_reg:x3; val_offset:14*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x3, 14*FLEN/8, x4, x2, x5) + +inst_40: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x32e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b2e; op2val:0xfb2e; + valaddr_reg:x3; val_offset:16*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x3, 16*FLEN/8, x4, x2, x5) + +inst_41: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x052 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x052 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7852; op2val:0xf852; + valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x3, 18*FLEN/8, x4, x2, x5) + +inst_42: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1a1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x79a3; op2val:0xf9a1; + valaddr_reg:x3; val_offset:20*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x3, 20*FLEN/8, x4, x2, x5) + +inst_43: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x27d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x27b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a7d; op2val:0xfa7b; + valaddr_reg:x3; val_offset:22*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x3, 22*FLEN/8, x4, x2, x5) + +inst_44: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x328 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x326 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b28; op2val:0xfb26; + valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x3, 24*FLEN/8, x4, x2, x5) + +inst_45: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x398 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x396 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b98; op2val:0xfb96; + valaddr_reg:x3; val_offset:26*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x3, 26*FLEN/8, x4, x2, x5) + +inst_46: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x334 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x330 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7734; op2val:0xf730; + valaddr_reg:x3; val_offset:28*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x3, 28*FLEN/8, x4, x2, x5) + +inst_47: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f7 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3f5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bf7; op2val:0xfbf5; + valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x3, 30*FLEN/8, x4, x2, x5) + +inst_48: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x257 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x255 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a57; op2val:0xfa55; + valaddr_reg:x3; val_offset:32*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x3, 32*FLEN/8, x4, x2, x5) + +inst_49: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x109 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x109 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7909; op2val:0xf909; + valaddr_reg:x3; val_offset:34*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x3, 34*FLEN/8, x4, x2, x5) + +inst_50: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3c6 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3c6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x73c6; op2val:0xf3c6; + valaddr_reg:x3; val_offset:36*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x3, 36*FLEN/8, x4, x2, x5) + +inst_51: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x37e and fs2 == 1 and fe2 == 0x1b and fm2 == 0x37e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f7e; op2val:0xef7e; + valaddr_reg:x3; val_offset:38*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x3, 38*FLEN/8, x4, x2, x5) + +inst_52: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x25a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a5a; op2val:0xfa5a; + valaddr_reg:x3; val_offset:40*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x3, 40*FLEN/8, x4, x2, x5) + +inst_53: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x286 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x286 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a86; op2val:0xfa86; + valaddr_reg:x3; val_offset:42*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x3, 42*FLEN/8, x4, x2, x5) + +inst_54: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0ae and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0ae and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x70ae; op2val:0xf0ae; + valaddr_reg:x3; val_offset:44*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x3, 44*FLEN/8, x4, x2, x5) + +inst_55: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2c0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ac0; op2val:0xfac0; + valaddr_reg:x3; val_offset:46*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x3, 46*FLEN/8, x4, x2, x5) + +inst_56: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x016 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x016 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7816; op2val:0xf816; + valaddr_reg:x3; val_offset:48*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x3, 48*FLEN/8, x4, x2, x5) + +inst_57: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x38c and fs2 == 1 and fe2 == 0x1d and fm2 == 0x38c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x778c; op2val:0xf78c; + valaddr_reg:x3; val_offset:50*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x3, 50*FLEN/8, x4, x2, x5) + +inst_58: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2ef and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aef; op2val:0xfaef; + valaddr_reg:x3; val_offset:52*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x3, 52*FLEN/8, x4, x2, x5) + +inst_59: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x00f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x780f; op2val:0xf80f; + valaddr_reg:x3; val_offset:54*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x3, 54*FLEN/8, x4, x2, x5) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(31424,32,FLEN) +NAN_BOXED(31424,16,FLEN) +NAN_BOXED(30393,32,FLEN) +NAN_BOXED(63161,16,FLEN) +NAN_BOXED(30742,32,FLEN) +NAN_BOXED(30742,16,FLEN) +NAN_BOXED(31300,32,FLEN) +NAN_BOXED(64068,16,FLEN) +NAN_BOXED(30623,32,FLEN) +NAN_BOXED(63391,16,FLEN) +NAN_BOXED(31554,32,FLEN) +NAN_BOXED(64322,16,FLEN) +NAN_BOXED(29825,32,FLEN) +NAN_BOXED(62593,16,FLEN) +NAN_BOXED(30961,32,FLEN) +NAN_BOXED(63729,16,FLEN) +NAN_BOXED(31558,32,FLEN) +NAN_BOXED(64326,16,FLEN) +NAN_BOXED(31354,32,FLEN) +NAN_BOXED(64122,16,FLEN) +NAN_BOXED(29941,32,FLEN) +NAN_BOXED(62709,16,FLEN) +test_dataset_1: +NAN_BOXED(31535,32,FLEN) +NAN_BOXED(64303,16,FLEN) +NAN_BOXED(30604,32,FLEN) +NAN_BOXED(63372,16,FLEN) +NAN_BOXED(30449,32,FLEN) +NAN_BOXED(63217,16,FLEN) +NAN_BOXED(31564,32,FLEN) +NAN_BOXED(64332,16,FLEN) +NAN_BOXED(30624,32,FLEN) +NAN_BOXED(63392,16,FLEN) +NAN_BOXED(29738,32,FLEN) +NAN_BOXED(62506,16,FLEN) +NAN_BOXED(30819,32,FLEN) +NAN_BOXED(63587,16,FLEN) +NAN_BOXED(31169,32,FLEN) +NAN_BOXED(63937,16,FLEN) +NAN_BOXED(31384,32,FLEN) +NAN_BOXED(64152,16,FLEN) +NAN_BOXED(21693,32,FLEN) +NAN_BOXED(54461,16,FLEN) +test_dataset_2: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64239,16,FLEN) +NAN_BOXED(30003,32,FLEN) +NAN_BOXED(62771,16,FLEN) +NAN_BOXED(29212,32,FLEN) +NAN_BOXED(61980,16,FLEN) +NAN_BOXED(29601,32,FLEN) +NAN_BOXED(62369,16,FLEN) +NAN_BOXED(31340,32,FLEN) +NAN_BOXED(64108,16,FLEN) +NAN_BOXED(27941,32,FLEN) +NAN_BOXED(60709,16,FLEN) +NAN_BOXED(30735,32,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(28410,32,FLEN) +NAN_BOXED(61178,16,FLEN) +NAN_BOXED(31142,32,FLEN) +NAN_BOXED(63910,16,FLEN) +NAN_BOXED(31363,32,FLEN) +NAN_BOXED(64131,16,FLEN) +NAN_BOXED(31668,32,FLEN) +NAN_BOXED(64436,16,FLEN) +test_dataset_3: +NAN_BOXED(30898,16,FLEN) +NAN_BOXED(63666,16,FLEN) +NAN_BOXED(30916,16,FLEN) +NAN_BOXED(63684,16,FLEN) +NAN_BOXED(30874,16,FLEN) +NAN_BOXED(63642,16,FLEN) +NAN_BOXED(29198,16,FLEN) +NAN_BOXED(61966,16,FLEN) +NAN_BOXED(30950,16,FLEN) +NAN_BOXED(63718,16,FLEN) +NAN_BOXED(30622,16,FLEN) +NAN_BOXED(63390,16,FLEN) +NAN_BOXED(31246,16,FLEN) +NAN_BOXED(64014,16,FLEN) +NAN_BOXED(31586,16,FLEN) +NAN_BOXED(64354,16,FLEN) +NAN_BOXED(31534,16,FLEN) +NAN_BOXED(64302,16,FLEN) +NAN_BOXED(30802,16,FLEN) +NAN_BOXED(63570,16,FLEN) +NAN_BOXED(31139,16,FLEN) +NAN_BOXED(63905,16,FLEN) +NAN_BOXED(31357,16,FLEN) +NAN_BOXED(64123,16,FLEN) +NAN_BOXED(31528,16,FLEN) +NAN_BOXED(64294,16,FLEN) +NAN_BOXED(31640,16,FLEN) +NAN_BOXED(64406,16,FLEN) +NAN_BOXED(30516,16,FLEN) +NAN_BOXED(63280,16,FLEN) +NAN_BOXED(31735,16,FLEN) +NAN_BOXED(64501,16,FLEN) +NAN_BOXED(31319,16,FLEN) +NAN_BOXED(64085,16,FLEN) +NAN_BOXED(30985,16,FLEN) +NAN_BOXED(63753,16,FLEN) +NAN_BOXED(29638,16,FLEN) +NAN_BOXED(62406,16,FLEN) +NAN_BOXED(28542,16,FLEN) +NAN_BOXED(61310,16,FLEN) +NAN_BOXED(31322,16,FLEN) +NAN_BOXED(64090,16,FLEN) +NAN_BOXED(31366,16,FLEN) +NAN_BOXED(64134,16,FLEN) +NAN_BOXED(28846,16,FLEN) +NAN_BOXED(61614,16,FLEN) +NAN_BOXED(31424,16,FLEN) +NAN_BOXED(64192,16,FLEN) +NAN_BOXED(30742,16,FLEN) +NAN_BOXED(63510,16,FLEN) +NAN_BOXED(30604,16,FLEN) +NAN_BOXED(63372,16,FLEN) +NAN_BOXED(31471,16,FLEN) +NAN_BOXED(64239,16,FLEN) +NAN_BOXED(30735,16,FLEN) +NAN_BOXED(63503,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x16_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x16_1: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_0: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_0: + .fill 64*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fadd_b8-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fadd_b8-01.S new file mode 100644 index 000000000..0d68d7498 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fadd_b8-01.S @@ -0,0 +1,16656 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 05:45:15 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fadd.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fadd.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fadd_b8 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fadd_b8) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x4,test_dataset_0) +RVTEST_SIGBASE(x3,signature_x3_1) + +inst_0: +// rs1 == rs2 != rd, rs1==x29, rs2==x29, rd==x28,fs1 == 0 and fe1 == 0x0c and fm1 == 0x0fa and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0fa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x29; op2:x29; dest:x28; op1val:0x30fa; op2val:0x30fa; + valaddr_reg:x4; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x28, x29, x29, dyn, 0, 0, x4, 0*FLEN/8, x11, x3, x2) + +inst_1: +// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==x23, rs2==x28, rd==x7,fs1 == 0 and fe1 == 0x0c and fm1 == 0x0fa and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0fa and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x23; op2:x28; dest:x7; op1val:0x30fa; op2val:0xb0fa; + valaddr_reg:x4; val_offset:2*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x7, x23, x28, dyn, 32, 0, x4, 2*FLEN/8, x11, x3, x2) + +inst_2: +// rs1 == rs2 == rd, rs1==x21, rs2==x21, rd==x21,fs1 == 0 and fe1 == 0x0c and fm1 == 0x0fa and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0fa and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x21; op2:x21; dest:x21; op1val:0x30fa; op2val:0x30fa; + valaddr_reg:x4; val_offset:4*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x21, x21, x21, dyn, 64, 0, x4, 4*FLEN/8, x11, x3, x2) + +inst_3: +// rs2 == rd != rs1, rs1==x6, rs2==x0, rd==x0,fs1 == 0 and fe1 == 0x0c and fm1 == 0x0fa and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0fa and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x6; op2:x0; dest:x0; op1val:0x30fa; op2val:0x0; + valaddr_reg:x4; val_offset:6*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x0, x6, x0, dyn, 96, 0, x4, 6*FLEN/8, x11, x3, x2) + +inst_4: +// rs1 == rd != rs2, rs1==x10, rs2==x19, rd==x10,fs1 == 0 and fe1 == 0x0c and fm1 == 0x0fa and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0fa and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x10; op2:x19; dest:x10; op1val:0x30fa; op2val:0xb0fa; + valaddr_reg:x4; val_offset:8*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x10, x10, x19, dyn, 128, 0, x4, 8*FLEN/8, x11, x3, x2) + +inst_5: +// rs1==x12, rs2==x8, rd==x27,fs1 == 0 and fe1 == 0x0e and fm1 == 0x0a2 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0a2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x12; op2:x8; dest:x27; op1val:0x38a2; op2val:0xb8a2; + valaddr_reg:x4; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x27, x12, x8, dyn, 0, 0, x4, 10*FLEN/8, x11, x3, x2) + +inst_6: +// rs1==x22, rs2==x15, rd==x18,fs1 == 0 and fe1 == 0x0e and fm1 == 0x0a2 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0a2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x22; op2:x15; dest:x18; op1val:0x38a2; op2val:0xb8a2; + valaddr_reg:x4; val_offset:12*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x18, x22, x15, dyn, 32, 0, x4, 12*FLEN/8, x11, x3, x2) + +inst_7: +// rs1==x16, rs2==x13, rd==x31,fs1 == 0 and fe1 == 0x0e and fm1 == 0x0a2 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0a2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x16; op2:x13; dest:x31; op1val:0x38a2; op2val:0xb8a2; + valaddr_reg:x4; val_offset:14*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x31, x16, x13, dyn, 64, 0, x4, 14*FLEN/8, x11, x3, x2) + +inst_8: +// rs1==x1, rs2==x12, rd==x29,fs1 == 0 and fe1 == 0x0e and fm1 == 0x0a2 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0a2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x1; op2:x12; dest:x29; op1val:0x38a2; op2val:0xb8a2; + valaddr_reg:x4; val_offset:16*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x29, x1, x12, dyn, 96, 0, x4, 16*FLEN/8, x11, x3, x2) + +inst_9: +// rs1==x26, rs2==x22, rd==x9,fs1 == 0 and fe1 == 0x0e and fm1 == 0x0a2 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0a2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x26; op2:x22; dest:x9; op1val:0x38a2; op2val:0xb8a2; + valaddr_reg:x4; val_offset:18*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x9, x26, x22, dyn, 128, 0, x4, 18*FLEN/8, x11, x3, x2) + +inst_10: +// rs1==x31, rs2==x24, rd==x25,fs1 == 0 and fe1 == 0x0d and fm1 == 0x3d1 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3d1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x31; op2:x24; dest:x25; op1val:0x37d1; op2val:0xb7d1; + valaddr_reg:x4; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x25, x31, x24, dyn, 0, 0, x4, 20*FLEN/8, x11, x3, x2) + +inst_11: +// rs1==x13, rs2==x25, rd==x5,fs1 == 0 and fe1 == 0x0d and fm1 == 0x3d1 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3d1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x13; op2:x25; dest:x5; op1val:0x37d1; op2val:0xb7d1; + valaddr_reg:x4; val_offset:22*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x5, x13, x25, dyn, 32, 0, x4, 22*FLEN/8, x11, x3, x2) +RVTEST_VALBASEUPD(x6,test_dataset_1) + +inst_12: +// rs1==x24, rs2==x27, rd==x14,fs1 == 0 and fe1 == 0x0d and fm1 == 0x3d1 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3d1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x24; op2:x27; dest:x14; op1val:0x37d1; op2val:0xb7d1; + valaddr_reg:x6; val_offset:0*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x14, x24, x27, dyn, 64, 0, x6, 0*FLEN/8, x13, x3, x2) + +inst_13: +// rs1==x4, rs2==x9, rd==x22,fs1 == 0 and fe1 == 0x0d and fm1 == 0x3d1 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3d1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x4; op2:x9; dest:x22; op1val:0x37d1; op2val:0xb7d1; + valaddr_reg:x6; val_offset:2*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.h, x22, x4, x9, dyn, 96, 0, x6, 2*FLEN/8, x13, x3, x2) + +inst_14: +// rs1==x2, rs2==x7, rd==x8,fs1 == 0 and fe1 == 0x0d and fm1 == 0x3d1 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3d1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x2; op2:x7; dest:x8; op1val:0x37d1; op2val:0xb7d1; + valaddr_reg:x6; val_offset:4*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x21 +*/ +TEST_FPRR_OP(fadd.h, x8, x2, x7, dyn, 128, 0, x6, 4*FLEN/8, x13, x3, x21) +RVTEST_SIGBASE(x10,signature_x10_0) + +inst_15: +// rs1==x0, rs2==x30, rd==x11,fs1 == 0 and fe1 == 0x0c and fm1 == 0x2eb and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2eb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x0; op2:x30; dest:x11; op1val:0x0; op2val:0xb2eb; + valaddr_reg:x6; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x21 +*/ +TEST_FPRR_OP(fadd.h, x11, x0, x30, dyn, 0, 0, x6, 6*FLEN/8, x13, x10, x21) + +inst_16: +// rs1==x15, rs2==x31, rd==x12,fs1 == 0 and fe1 == 0x0c and fm1 == 0x2eb and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2eb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x15; op2:x31; dest:x12; op1val:0x32eb; op2val:0xb2eb; + valaddr_reg:x6; val_offset:8*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x21 +*/ +TEST_FPRR_OP(fadd.h, x12, x15, x31, dyn, 32, 0, x6, 8*FLEN/8, x13, x10, x21) + +inst_17: +// rs1==x25, rs2==x5, rd==x1,fs1 == 0 and fe1 == 0x0c and fm1 == 0x2eb and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2eb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x25; op2:x5; dest:x1; op1val:0x32eb; op2val:0xb2eb; + valaddr_reg:x6; val_offset:10*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x21 +*/ +TEST_FPRR_OP(fadd.h, x1, x25, x5, dyn, 64, 0, x6, 10*FLEN/8, x13, x10, x21) + +inst_18: +// rs1==x18, rs2==x17, rd==x19,fs1 == 0 and fe1 == 0x0c and fm1 == 0x2eb and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2eb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x18; op2:x17; dest:x19; op1val:0x32eb; op2val:0xb2eb; + valaddr_reg:x6; val_offset:12*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x21 +*/ +TEST_FPRR_OP(fadd.h, x19, x18, x17, dyn, 96, 0, x6, 12*FLEN/8, x13, x10, x21) + +inst_19: +// rs1==x20, rs2==x16, rd==x30,fs1 == 0 and fe1 == 0x0c and fm1 == 0x2eb and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2eb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x20; op2:x16; dest:x30; op1val:0x32eb; op2val:0xb2eb; + valaddr_reg:x6; val_offset:14*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x21 +*/ +TEST_FPRR_OP(fadd.h, x30, x20, x16, dyn, 128, 0, x6, 14*FLEN/8, x13, x10, x21) +RVTEST_VALBASEUPD(x1,test_dataset_2) + +inst_20: +// rs1==x28, rs2==x11, rd==x6,fs1 == 0 and fe1 == 0x0e and fm1 == 0x02f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x02f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x28; op2:x11; dest:x6; op1val:0x382f; op2val:0xb82f; + valaddr_reg:x1; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x21 +*/ +TEST_FPRR_OP(fadd.h, x6, x28, x11, dyn, 0, 0, x1, 0*FLEN/8, x12, x10, x21) + +inst_21: +// rs1==x8, rs2==x18, rd==x4,fs1 == 0 and fe1 == 0x0e and fm1 == 0x02f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x02f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x8; op2:x18; dest:x4; op1val:0x382f; op2val:0xb82f; + valaddr_reg:x1; val_offset:2*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x21 +*/ +TEST_FPRR_OP(fadd.h, x4, x8, x18, dyn, 32, 0, x1, 2*FLEN/8, x12, x10, x21) + +inst_22: +// rs1==x5, rs2==x23, rd==x13,fs1 == 0 and fe1 == 0x0e and fm1 == 0x02f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x02f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x5; op2:x23; dest:x13; op1val:0x382f; op2val:0xb82f; + valaddr_reg:x1; val_offset:4*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x21 +*/ +TEST_FPRR_OP(fadd.h, x13, x5, x23, dyn, 64, 0, x1, 4*FLEN/8, x12, x10, x21) + +inst_23: +// rs1==x9, rs2==x4, rd==x2,fs1 == 0 and fe1 == 0x0e and fm1 == 0x02f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x02f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x9; op2:x4; dest:x2; op1val:0x382f; op2val:0xb82f; + valaddr_reg:x1; val_offset:6*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x21 +*/ +TEST_FPRR_OP(fadd.h, x2, x9, x4, dyn, 96, 0, x1, 6*FLEN/8, x12, x10, x21) + +inst_24: +// rs1==x7, rs2==x14, rd==x15,fs1 == 0 and fe1 == 0x0e and fm1 == 0x02f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x02f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x7; op2:x14; dest:x15; op1val:0x382f; op2val:0xb82f; + valaddr_reg:x1; val_offset:8*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x21 +*/ +TEST_FPRR_OP(fadd.h, x15, x7, x14, dyn, 128, 0, x1, 8*FLEN/8, x12, x10, x21) + +inst_25: +// rs1==x3, rs2==x26, rd==x24,fs1 == 0 and fe1 == 0x0b and fm1 == 0x1e1 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1e1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x3; op2:x26; dest:x24; op1val:0x2de1; op2val:0xade1; + valaddr_reg:x1; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x21 +*/ +TEST_FPRR_OP(fadd.h, x24, x3, x26, dyn, 0, 0, x1, 10*FLEN/8, x12, x10, x21) +RVTEST_SIGBASE(x4,signature_x4_0) + +inst_26: +// rs1==x30, rs2==x6, rd==x23,fs1 == 0 and fe1 == 0x0b and fm1 == 0x1e1 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1e1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x6; dest:x23; op1val:0x2de1; op2val:0xade1; + valaddr_reg:x1; val_offset:12*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x23, x30, x6, dyn, 32, 0, x1, 12*FLEN/8, x12, x4, x5) + +inst_27: +// rs1==x17, rs2==x20, rd==x16,fs1 == 0 and fe1 == 0x0b and fm1 == 0x1e1 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1e1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x17; op2:x20; dest:x16; op1val:0x2de1; op2val:0xade1; + valaddr_reg:x1; val_offset:14*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x16, x17, x20, dyn, 64, 0, x1, 14*FLEN/8, x12, x4, x5) + +inst_28: +// rs1==x27, rs2==x10, rd==x3,fs1 == 0 and fe1 == 0x0b and fm1 == 0x1e1 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1e1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x27; op2:x10; dest:x3; op1val:0x2de1; op2val:0xade1; + valaddr_reg:x1; val_offset:16*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x3, x27, x10, dyn, 96, 0, x1, 16*FLEN/8, x12, x4, x5) + +inst_29: +// rs1==x19, rs2==x2, rd==x20,fs1 == 0 and fe1 == 0x0b and fm1 == 0x1e1 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1e1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x19; op2:x2; dest:x20; op1val:0x2de1; op2val:0xade1; + valaddr_reg:x1; val_offset:18*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x20, x19, x2, dyn, 128, 0, x1, 18*FLEN/8, x12, x4, x5) +RVTEST_VALBASEUPD(x2,test_dataset_3) + +inst_30: +// rs1==x11, rs2==x3, rd==x26,fs1 == 0 and fe1 == 0x0e and fm1 == 0x1be and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1be and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x11; op2:x3; dest:x26; op1val:0x39be; op2val:0xb9be; + valaddr_reg:x2; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x26, x11, x3, dyn, 0, 0, x2, 0*FLEN/8, x6, x4, x5) + +inst_31: +// rs1==x14, rs2==x1, rd==x17,fs1 == 0 and fe1 == 0x0e and fm1 == 0x1be and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1be and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x14; op2:x1; dest:x17; op1val:0x39be; op2val:0xb9be; + valaddr_reg:x2; val_offset:2*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x17, x14, x1, dyn, 32, 0, x2, 2*FLEN/8, x6, x4, x5) + +inst_32: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1be and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1be and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x39be; op2val:0xb9be; + valaddr_reg:x2; val_offset:4*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 4*FLEN/8, x6, x4, x5) + +inst_33: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1be and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1be and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x39be; op2val:0xb9be; + valaddr_reg:x2; val_offset:6*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 6*FLEN/8, x6, x4, x5) + +inst_34: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1be and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1be and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x39be; op2val:0xb9be; + valaddr_reg:x2; val_offset:8*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 8*FLEN/8, x6, x4, x5) + +inst_35: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x21b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x21b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x361b; op2val:0xb61b; + valaddr_reg:x2; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 10*FLEN/8, x6, x4, x5) + +inst_36: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x21b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x21b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x361b; op2val:0xb61b; + valaddr_reg:x2; val_offset:12*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 12*FLEN/8, x6, x4, x5) + +inst_37: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x21b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x21b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x361b; op2val:0xb61b; + valaddr_reg:x2; val_offset:14*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 14*FLEN/8, x6, x4, x5) + +inst_38: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x21b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x21b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x361b; op2val:0xb61b; + valaddr_reg:x2; val_offset:16*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 16*FLEN/8, x6, x4, x5) + +inst_39: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x21b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x21b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x361b; op2val:0xb61b; + valaddr_reg:x2; val_offset:18*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 18*FLEN/8, x6, x4, x5) + +inst_40: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1c6 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1c6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2dc6; op2val:0xadc6; + valaddr_reg:x2; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 20*FLEN/8, x6, x4, x5) + +inst_41: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1c6 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1c6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2dc6; op2val:0xadc6; + valaddr_reg:x2; val_offset:22*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 22*FLEN/8, x6, x4, x5) + +inst_42: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1c6 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1c6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2dc6; op2val:0xadc6; + valaddr_reg:x2; val_offset:24*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 24*FLEN/8, x6, x4, x5) + +inst_43: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1c6 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1c6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2dc6; op2val:0xadc6; + valaddr_reg:x2; val_offset:26*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 26*FLEN/8, x6, x4, x5) + +inst_44: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1c6 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1c6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2dc6; op2val:0xadc6; + valaddr_reg:x2; val_offset:28*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 28*FLEN/8, x6, x4, x5) + +inst_45: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x212 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x212 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3212; op2val:0xb212; + valaddr_reg:x2; val_offset:30*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 30*FLEN/8, x6, x4, x5) + +inst_46: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x212 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x212 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3212; op2val:0xb212; + valaddr_reg:x2; val_offset:32*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 32*FLEN/8, x6, x4, x5) + +inst_47: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x212 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x212 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3212; op2val:0xb212; + valaddr_reg:x2; val_offset:34*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 34*FLEN/8, x6, x4, x5) + +inst_48: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x212 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x212 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3212; op2val:0xb212; + valaddr_reg:x2; val_offset:36*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 36*FLEN/8, x6, x4, x5) + +inst_49: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x212 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x212 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3212; op2val:0xb212; + valaddr_reg:x2; val_offset:38*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 38*FLEN/8, x6, x4, x5) + +inst_50: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x184 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x184 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3984; op2val:0xb984; + valaddr_reg:x2; val_offset:40*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 40*FLEN/8, x6, x4, x5) + +inst_51: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x184 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x184 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3984; op2val:0xb984; + valaddr_reg:x2; val_offset:42*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 42*FLEN/8, x6, x4, x5) + +inst_52: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x184 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x184 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3984; op2val:0xb984; + valaddr_reg:x2; val_offset:44*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 44*FLEN/8, x6, x4, x5) + +inst_53: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x184 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x184 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3984; op2val:0xb984; + valaddr_reg:x2; val_offset:46*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 46*FLEN/8, x6, x4, x5) + +inst_54: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x184 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x184 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3984; op2val:0xb984; + valaddr_reg:x2; val_offset:48*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 48*FLEN/8, x6, x4, x5) + +inst_55: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x279 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x279 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e79; op2val:0xae79; + valaddr_reg:x2; val_offset:50*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 50*FLEN/8, x6, x4, x5) + +inst_56: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x279 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x279 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e79; op2val:0xae79; + valaddr_reg:x2; val_offset:52*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 52*FLEN/8, x6, x4, x5) + +inst_57: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x279 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x279 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e79; op2val:0xae79; + valaddr_reg:x2; val_offset:54*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 54*FLEN/8, x6, x4, x5) + +inst_58: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x279 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x279 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e79; op2val:0xae79; + valaddr_reg:x2; val_offset:56*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 56*FLEN/8, x6, x4, x5) + +inst_59: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x279 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x279 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e79; op2val:0xae79; + valaddr_reg:x2; val_offset:58*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 58*FLEN/8, x6, x4, x5) + +inst_60: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x039 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x039 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3839; op2val:0xb839; + valaddr_reg:x2; val_offset:60*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 60*FLEN/8, x6, x4, x5) + +inst_61: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x039 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x039 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3839; op2val:0xb839; + valaddr_reg:x2; val_offset:62*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 62*FLEN/8, x6, x4, x5) + +inst_62: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x039 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x039 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3839; op2val:0xb839; + valaddr_reg:x2; val_offset:64*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 64*FLEN/8, x6, x4, x5) + +inst_63: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x039 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x039 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3839; op2val:0xb839; + valaddr_reg:x2; val_offset:66*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 66*FLEN/8, x6, x4, x5) + +inst_64: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x039 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x039 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3839; op2val:0xb839; + valaddr_reg:x2; val_offset:68*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 68*FLEN/8, x6, x4, x5) + +inst_65: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x086 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x086 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3886; op2val:0xb886; + valaddr_reg:x2; val_offset:70*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 70*FLEN/8, x6, x4, x5) + +inst_66: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x086 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x086 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3886; op2val:0xb886; + valaddr_reg:x2; val_offset:72*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 72*FLEN/8, x6, x4, x5) + +inst_67: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x086 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x086 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3886; op2val:0xb886; + valaddr_reg:x2; val_offset:74*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 74*FLEN/8, x6, x4, x5) + +inst_68: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x086 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x086 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3886; op2val:0xb886; + valaddr_reg:x2; val_offset:76*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 76*FLEN/8, x6, x4, x5) + +inst_69: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x086 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x086 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3886; op2val:0xb886; + valaddr_reg:x2; val_offset:78*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 78*FLEN/8, x6, x4, x5) + +inst_70: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x191 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x191 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d91; op2val:0xad91; + valaddr_reg:x2; val_offset:80*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 80*FLEN/8, x6, x4, x5) + +inst_71: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x191 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x191 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d91; op2val:0xad91; + valaddr_reg:x2; val_offset:82*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 82*FLEN/8, x6, x4, x5) + +inst_72: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x191 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x191 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d91; op2val:0xad91; + valaddr_reg:x2; val_offset:84*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 84*FLEN/8, x6, x4, x5) + +inst_73: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x191 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x191 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d91; op2val:0xad91; + valaddr_reg:x2; val_offset:86*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 86*FLEN/8, x6, x4, x5) + +inst_74: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x191 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x191 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d91; op2val:0xad91; + valaddr_reg:x2; val_offset:88*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 88*FLEN/8, x6, x4, x5) + +inst_75: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ea and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1ea and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x39ea; op2val:0xb9ea; + valaddr_reg:x2; val_offset:90*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 90*FLEN/8, x6, x4, x5) + +inst_76: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ea and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1ea and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x39ea; op2val:0xb9ea; + valaddr_reg:x2; val_offset:92*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 92*FLEN/8, x6, x4, x5) + +inst_77: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ea and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1ea and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x39ea; op2val:0xb9ea; + valaddr_reg:x2; val_offset:94*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 94*FLEN/8, x6, x4, x5) + +inst_78: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ea and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1ea and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x39ea; op2val:0xb9ea; + valaddr_reg:x2; val_offset:96*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 96*FLEN/8, x6, x4, x5) + +inst_79: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ea and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1ea and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x39ea; op2val:0xb9ea; + valaddr_reg:x2; val_offset:98*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 98*FLEN/8, x6, x4, x5) + +inst_80: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x338 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x338 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3738; op2val:0xb738; + valaddr_reg:x2; val_offset:100*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 100*FLEN/8, x6, x4, x5) + +inst_81: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x338 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x338 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3738; op2val:0xb738; + valaddr_reg:x2; val_offset:102*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 102*FLEN/8, x6, x4, x5) + +inst_82: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x338 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x338 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3738; op2val:0xb738; + valaddr_reg:x2; val_offset:104*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 104*FLEN/8, x6, x4, x5) + +inst_83: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x338 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x338 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3738; op2val:0xb738; + valaddr_reg:x2; val_offset:106*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 106*FLEN/8, x6, x4, x5) + +inst_84: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x338 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x338 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3738; op2val:0xb738; + valaddr_reg:x2; val_offset:108*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 108*FLEN/8, x6, x4, x5) + +inst_85: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x07c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x07c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x347c; op2val:0xb47c; + valaddr_reg:x2; val_offset:110*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 110*FLEN/8, x6, x4, x5) + +inst_86: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x07c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x07c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x347c; op2val:0xb47c; + valaddr_reg:x2; val_offset:112*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 112*FLEN/8, x6, x4, x5) + +inst_87: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x07c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x07c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x347c; op2val:0xb47c; + valaddr_reg:x2; val_offset:114*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 114*FLEN/8, x6, x4, x5) + +inst_88: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x07c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x07c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x347c; op2val:0xb47c; + valaddr_reg:x2; val_offset:116*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 116*FLEN/8, x6, x4, x5) + +inst_89: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x07c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x07c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x347c; op2val:0xb47c; + valaddr_reg:x2; val_offset:118*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 118*FLEN/8, x6, x4, x5) + +inst_90: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x19a and fs2 == 1 and fe2 == 0x0c and fm2 == 0x19a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x319a; op2val:0xb19a; + valaddr_reg:x2; val_offset:120*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 120*FLEN/8, x6, x4, x5) + +inst_91: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x19a and fs2 == 1 and fe2 == 0x0c and fm2 == 0x19a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x319a; op2val:0xb19a; + valaddr_reg:x2; val_offset:122*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 122*FLEN/8, x6, x4, x5) + +inst_92: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x19a and fs2 == 1 and fe2 == 0x0c and fm2 == 0x19a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x319a; op2val:0xb19a; + valaddr_reg:x2; val_offset:124*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 124*FLEN/8, x6, x4, x5) + +inst_93: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x19a and fs2 == 1 and fe2 == 0x0c and fm2 == 0x19a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x319a; op2val:0xb19a; + valaddr_reg:x2; val_offset:126*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 126*FLEN/8, x6, x4, x5) + +inst_94: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x19a and fs2 == 1 and fe2 == 0x0c and fm2 == 0x19a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x319a; op2val:0xb19a; + valaddr_reg:x2; val_offset:128*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 128*FLEN/8, x6, x4, x5) + +inst_95: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3fd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3fd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bfd; op2val:0xbbfd; + valaddr_reg:x2; val_offset:130*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 130*FLEN/8, x6, x4, x5) + +inst_96: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3fd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3fd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bfd; op2val:0xbbfd; + valaddr_reg:x2; val_offset:132*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 132*FLEN/8, x6, x4, x5) + +inst_97: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3fd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3fd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bfd; op2val:0xbbfd; + valaddr_reg:x2; val_offset:134*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 134*FLEN/8, x6, x4, x5) + +inst_98: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3fd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3fd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bfd; op2val:0xbbfd; + valaddr_reg:x2; val_offset:136*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 136*FLEN/8, x6, x4, x5) + +inst_99: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3fd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3fd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bfd; op2val:0xbbfd; + valaddr_reg:x2; val_offset:138*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 138*FLEN/8, x6, x4, x5) + +inst_100: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x03c and fs2 == 1 and fe2 == 0x0c and fm2 == 0x03c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x303c; op2val:0xb03c; + valaddr_reg:x2; val_offset:140*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 140*FLEN/8, x6, x4, x5) + +inst_101: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x03c and fs2 == 1 and fe2 == 0x0c and fm2 == 0x03c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x303c; op2val:0xb03c; + valaddr_reg:x2; val_offset:142*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 142*FLEN/8, x6, x4, x5) + +inst_102: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x03c and fs2 == 1 and fe2 == 0x0c and fm2 == 0x03c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x303c; op2val:0xb03c; + valaddr_reg:x2; val_offset:144*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 144*FLEN/8, x6, x4, x5) + +inst_103: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x03c and fs2 == 1 and fe2 == 0x0c and fm2 == 0x03c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x303c; op2val:0xb03c; + valaddr_reg:x2; val_offset:146*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 146*FLEN/8, x6, x4, x5) + +inst_104: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x03c and fs2 == 1 and fe2 == 0x0c and fm2 == 0x03c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x303c; op2val:0xb03c; + valaddr_reg:x2; val_offset:148*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 148*FLEN/8, x6, x4, x5) + +inst_105: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x165 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x165 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3965; op2val:0xb965; + valaddr_reg:x2; val_offset:150*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 150*FLEN/8, x6, x4, x5) + +inst_106: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x165 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x165 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3965; op2val:0xb965; + valaddr_reg:x2; val_offset:152*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 152*FLEN/8, x6, x4, x5) + +inst_107: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x165 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x165 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3965; op2val:0xb965; + valaddr_reg:x2; val_offset:154*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 154*FLEN/8, x6, x4, x5) + +inst_108: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x165 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x165 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3965; op2val:0xb965; + valaddr_reg:x2; val_offset:156*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 156*FLEN/8, x6, x4, x5) + +inst_109: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x165 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x165 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3965; op2val:0xb965; + valaddr_reg:x2; val_offset:158*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 158*FLEN/8, x6, x4, x5) + +inst_110: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x278 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x278 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a78; op2val:0xba78; + valaddr_reg:x2; val_offset:160*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 160*FLEN/8, x6, x4, x5) + +inst_111: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x278 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x278 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a78; op2val:0xba78; + valaddr_reg:x2; val_offset:162*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 162*FLEN/8, x6, x4, x5) + +inst_112: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x278 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x278 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a78; op2val:0xba78; + valaddr_reg:x2; val_offset:164*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 164*FLEN/8, x6, x4, x5) + +inst_113: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x278 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x278 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a78; op2val:0xba78; + valaddr_reg:x2; val_offset:166*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 166*FLEN/8, x6, x4, x5) + +inst_114: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x278 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x278 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a78; op2val:0xba78; + valaddr_reg:x2; val_offset:168*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 168*FLEN/8, x6, x4, x5) + +inst_115: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x217 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x217 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a17; op2val:0xba17; + valaddr_reg:x2; val_offset:170*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 170*FLEN/8, x6, x4, x5) + +inst_116: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x217 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x217 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a17; op2val:0xba17; + valaddr_reg:x2; val_offset:172*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 172*FLEN/8, x6, x4, x5) + +inst_117: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x217 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x217 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a17; op2val:0xba17; + valaddr_reg:x2; val_offset:174*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 174*FLEN/8, x6, x4, x5) + +inst_118: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x217 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x217 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a17; op2val:0xba17; + valaddr_reg:x2; val_offset:176*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 176*FLEN/8, x6, x4, x5) + +inst_119: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x217 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x217 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a17; op2val:0xba17; + valaddr_reg:x2; val_offset:178*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 178*FLEN/8, x6, x4, x5) + +inst_120: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fs2 == 1 and fe2 == 0x0c and fm2 == 0x24c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x324c; op2val:0xb24c; + valaddr_reg:x2; val_offset:180*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 180*FLEN/8, x6, x4, x5) + +inst_121: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fs2 == 1 and fe2 == 0x0c and fm2 == 0x24c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x324c; op2val:0xb24c; + valaddr_reg:x2; val_offset:182*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 182*FLEN/8, x6, x4, x5) + +inst_122: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fs2 == 1 and fe2 == 0x0c and fm2 == 0x24c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x324c; op2val:0xb24c; + valaddr_reg:x2; val_offset:184*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 184*FLEN/8, x6, x4, x5) + +inst_123: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fs2 == 1 and fe2 == 0x0c and fm2 == 0x24c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x324c; op2val:0xb24c; + valaddr_reg:x2; val_offset:186*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 186*FLEN/8, x6, x4, x5) + +inst_124: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fs2 == 1 and fe2 == 0x0c and fm2 == 0x24c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x324c; op2val:0xb24c; + valaddr_reg:x2; val_offset:188*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 188*FLEN/8, x6, x4, x5) + +inst_125: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x35b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x35b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b5b; op2val:0xbb5b; + valaddr_reg:x2; val_offset:190*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 190*FLEN/8, x6, x4, x5) + +inst_126: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x35b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x35b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b5b; op2val:0xbb5b; + valaddr_reg:x2; val_offset:192*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 192*FLEN/8, x6, x4, x5) + +inst_127: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x35b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x35b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b5b; op2val:0xbb5b; + valaddr_reg:x2; val_offset:194*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 194*FLEN/8, x6, x4, x5) + +inst_128: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x35b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x35b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b5b; op2val:0xbb5b; + valaddr_reg:x2; val_offset:196*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 196*FLEN/8, x6, x4, x5) + +inst_129: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x35b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x35b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b5b; op2val:0xbb5b; + valaddr_reg:x2; val_offset:198*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 198*FLEN/8, x6, x4, x5) + +inst_130: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3df and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3df and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x37df; op2val:0xb7df; + valaddr_reg:x2; val_offset:200*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 200*FLEN/8, x6, x4, x5) + +inst_131: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3df and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3df and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x37df; op2val:0xb7df; + valaddr_reg:x2; val_offset:202*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 202*FLEN/8, x6, x4, x5) + +inst_132: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3df and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3df and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x37df; op2val:0xb7df; + valaddr_reg:x2; val_offset:204*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 204*FLEN/8, x6, x4, x5) + +inst_133: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3df and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3df and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x37df; op2val:0xb7df; + valaddr_reg:x2; val_offset:206*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 206*FLEN/8, x6, x4, x5) + +inst_134: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3df and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3df and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x37df; op2val:0xb7df; + valaddr_reg:x2; val_offset:208*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 208*FLEN/8, x6, x4, x5) + +inst_135: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x320 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x320 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b20; op2val:0xbb20; + valaddr_reg:x2; val_offset:210*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 210*FLEN/8, x6, x4, x5) + +inst_136: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x320 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x320 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b20; op2val:0xbb20; + valaddr_reg:x2; val_offset:212*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 212*FLEN/8, x6, x4, x5) + +inst_137: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x320 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x320 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b20; op2val:0xbb20; + valaddr_reg:x2; val_offset:214*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 214*FLEN/8, x6, x4, x5) + +inst_138: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x320 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x320 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b20; op2val:0xbb20; + valaddr_reg:x2; val_offset:216*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 216*FLEN/8, x6, x4, x5) + +inst_139: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x320 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x320 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b20; op2val:0xbb20; + valaddr_reg:x2; val_offset:218*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 218*FLEN/8, x6, x4, x5) + +inst_140: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0b1 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0b1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x34b1; op2val:0xb4b1; + valaddr_reg:x2; val_offset:220*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 220*FLEN/8, x6, x4, x5) + +inst_141: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0b1 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0b1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x34b1; op2val:0xb4b1; + valaddr_reg:x2; val_offset:222*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 222*FLEN/8, x6, x4, x5) + +inst_142: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0b1 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0b1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x34b1; op2val:0xb4b1; + valaddr_reg:x2; val_offset:224*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 224*FLEN/8, x6, x4, x5) + +inst_143: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0b1 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0b1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x34b1; op2val:0xb4b1; + valaddr_reg:x2; val_offset:226*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 226*FLEN/8, x6, x4, x5) + +inst_144: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0b1 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0b1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x34b1; op2val:0xb4b1; + valaddr_reg:x2; val_offset:228*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 228*FLEN/8, x6, x4, x5) + +inst_145: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1ef and fs2 == 1 and fe2 == 0x0c and fm2 == 0x1ef and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x31ef; op2val:0xb1ef; + valaddr_reg:x2; val_offset:230*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 230*FLEN/8, x6, x4, x5) + +inst_146: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1ef and fs2 == 1 and fe2 == 0x0c and fm2 == 0x1ef and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x31ef; op2val:0xb1ef; + valaddr_reg:x2; val_offset:232*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 232*FLEN/8, x6, x4, x5) + +inst_147: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1ef and fs2 == 1 and fe2 == 0x0c and fm2 == 0x1ef and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x31ef; op2val:0xb1ef; + valaddr_reg:x2; val_offset:234*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 234*FLEN/8, x6, x4, x5) + +inst_148: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1ef and fs2 == 1 and fe2 == 0x0c and fm2 == 0x1ef and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x31ef; op2val:0xb1ef; + valaddr_reg:x2; val_offset:236*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 236*FLEN/8, x6, x4, x5) + +inst_149: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1ef and fs2 == 1 and fe2 == 0x0c and fm2 == 0x1ef and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x31ef; op2val:0xb1ef; + valaddr_reg:x2; val_offset:238*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 238*FLEN/8, x6, x4, x5) + +inst_150: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x0a0 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x0a0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x28a0; op2val:0xa8a0; + valaddr_reg:x2; val_offset:240*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 240*FLEN/8, x6, x4, x5) + +inst_151: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x0a0 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x0a0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x28a0; op2val:0xa8a0; + valaddr_reg:x2; val_offset:242*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 242*FLEN/8, x6, x4, x5) + +inst_152: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x0a0 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x0a0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x28a0; op2val:0xa8a0; + valaddr_reg:x2; val_offset:244*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 244*FLEN/8, x6, x4, x5) + +inst_153: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x0a0 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x0a0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x28a0; op2val:0xa8a0; + valaddr_reg:x2; val_offset:246*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 246*FLEN/8, x6, x4, x5) +RVTEST_SIGBASE(x4,signature_x4_1) + +inst_154: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x0a0 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x0a0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x28a0; op2val:0xa8a0; + valaddr_reg:x2; val_offset:248*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 248*FLEN/8, x6, x4, x5) + +inst_155: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x299 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x299 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3699; op2val:0xb699; + valaddr_reg:x2; val_offset:250*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 250*FLEN/8, x6, x4, x5) + +inst_156: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x299 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x299 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3699; op2val:0xb699; + valaddr_reg:x2; val_offset:252*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 252*FLEN/8, x6, x4, x5) + +inst_157: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x299 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x299 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3699; op2val:0xb699; + valaddr_reg:x2; val_offset:254*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 254*FLEN/8, x6, x4, x5) + +inst_158: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x299 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x299 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3699; op2val:0xb699; + valaddr_reg:x2; val_offset:256*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 256*FLEN/8, x6, x4, x5) + +inst_159: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x299 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x299 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3699; op2val:0xb699; + valaddr_reg:x2; val_offset:258*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 258*FLEN/8, x6, x4, x5) + +inst_160: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x275 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x275 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3675; op2val:0xb675; + valaddr_reg:x2; val_offset:260*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 260*FLEN/8, x6, x4, x5) + +inst_161: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x275 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x275 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3675; op2val:0xb675; + valaddr_reg:x2; val_offset:262*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 262*FLEN/8, x6, x4, x5) + +inst_162: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x275 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x275 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3675; op2val:0xb675; + valaddr_reg:x2; val_offset:264*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 264*FLEN/8, x6, x4, x5) + +inst_163: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x275 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x275 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3675; op2val:0xb675; + valaddr_reg:x2; val_offset:266*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 266*FLEN/8, x6, x4, x5) + +inst_164: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x275 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x275 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3675; op2val:0xb675; + valaddr_reg:x2; val_offset:268*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 268*FLEN/8, x6, x4, x5) + +inst_165: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2ca and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2ca and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x36ca; op2val:0xb6ca; + valaddr_reg:x2; val_offset:270*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 270*FLEN/8, x6, x4, x5) + +inst_166: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2ca and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2ca and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x36ca; op2val:0xb6ca; + valaddr_reg:x2; val_offset:272*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 272*FLEN/8, x6, x4, x5) + +inst_167: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2ca and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2ca and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x36ca; op2val:0xb6ca; + valaddr_reg:x2; val_offset:274*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 274*FLEN/8, x6, x4, x5) + +inst_168: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2ca and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2ca and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x36ca; op2val:0xb6ca; + valaddr_reg:x2; val_offset:276*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 276*FLEN/8, x6, x4, x5) + +inst_169: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2ca and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2ca and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x36ca; op2val:0xb6ca; + valaddr_reg:x2; val_offset:278*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 278*FLEN/8, x6, x4, x5) + +inst_170: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x27c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x27c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a7c; op2val:0xba7c; + valaddr_reg:x2; val_offset:280*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 280*FLEN/8, x6, x4, x5) + +inst_171: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x27c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x27c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a7c; op2val:0xba7c; + valaddr_reg:x2; val_offset:282*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 282*FLEN/8, x6, x4, x5) + +inst_172: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x27c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x27c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a7c; op2val:0xba7c; + valaddr_reg:x2; val_offset:284*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 284*FLEN/8, x6, x4, x5) + +inst_173: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x27c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x27c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a7c; op2val:0xba7c; + valaddr_reg:x2; val_offset:286*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 286*FLEN/8, x6, x4, x5) + +inst_174: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x27c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x27c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a7c; op2val:0xba7c; + valaddr_reg:x2; val_offset:288*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 288*FLEN/8, x6, x4, x5) + +inst_175: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x232 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x232 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3632; op2val:0xb632; + valaddr_reg:x2; val_offset:290*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 290*FLEN/8, x6, x4, x5) + +inst_176: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x232 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x232 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3632; op2val:0xb632; + valaddr_reg:x2; val_offset:292*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 292*FLEN/8, x6, x4, x5) + +inst_177: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x232 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x232 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3632; op2val:0xb632; + valaddr_reg:x2; val_offset:294*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 294*FLEN/8, x6, x4, x5) + +inst_178: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x232 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x232 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3632; op2val:0xb632; + valaddr_reg:x2; val_offset:296*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 296*FLEN/8, x6, x4, x5) + +inst_179: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x232 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x232 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3632; op2val:0xb632; + valaddr_reg:x2; val_offset:298*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 298*FLEN/8, x6, x4, x5) + +inst_180: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x030 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x030 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3830; op2val:0xb830; + valaddr_reg:x2; val_offset:300*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 300*FLEN/8, x6, x4, x5) + +inst_181: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x030 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x030 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3830; op2val:0xb830; + valaddr_reg:x2; val_offset:302*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 302*FLEN/8, x6, x4, x5) + +inst_182: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x030 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x030 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3830; op2val:0xb830; + valaddr_reg:x2; val_offset:304*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 304*FLEN/8, x6, x4, x5) + +inst_183: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x030 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x030 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3830; op2val:0xb830; + valaddr_reg:x2; val_offset:306*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 306*FLEN/8, x6, x4, x5) + +inst_184: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x030 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x030 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3830; op2val:0xb830; + valaddr_reg:x2; val_offset:308*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 308*FLEN/8, x6, x4, x5) + +inst_185: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3c1 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3c1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x33c1; op2val:0xb3c1; + valaddr_reg:x2; val_offset:310*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 310*FLEN/8, x6, x4, x5) + +inst_186: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3c1 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3c1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x33c1; op2val:0xb3c1; + valaddr_reg:x2; val_offset:312*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 312*FLEN/8, x6, x4, x5) + +inst_187: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3c1 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3c1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x33c1; op2val:0xb3c1; + valaddr_reg:x2; val_offset:314*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 314*FLEN/8, x6, x4, x5) + +inst_188: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3c1 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3c1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x33c1; op2val:0xb3c1; + valaddr_reg:x2; val_offset:316*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 316*FLEN/8, x6, x4, x5) + +inst_189: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3c1 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3c1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x33c1; op2val:0xb3c1; + valaddr_reg:x2; val_offset:318*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 318*FLEN/8, x6, x4, x5) + +inst_190: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0e7 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x0e7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ce7; op2val:0xace7; + valaddr_reg:x2; val_offset:320*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 320*FLEN/8, x6, x4, x5) + +inst_191: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0e7 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x0e7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ce7; op2val:0xace7; + valaddr_reg:x2; val_offset:322*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 322*FLEN/8, x6, x4, x5) + +inst_192: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0e7 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x0e7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ce7; op2val:0xace7; + valaddr_reg:x2; val_offset:324*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 324*FLEN/8, x6, x4, x5) + +inst_193: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0e7 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x0e7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ce7; op2val:0xace7; + valaddr_reg:x2; val_offset:326*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 326*FLEN/8, x6, x4, x5) + +inst_194: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0e7 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x0e7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ce7; op2val:0xace7; + valaddr_reg:x2; val_offset:328*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 328*FLEN/8, x6, x4, x5) + +inst_195: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x284 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x284 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e84; op2val:0xae84; + valaddr_reg:x2; val_offset:330*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 330*FLEN/8, x6, x4, x5) + +inst_196: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x284 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x284 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e84; op2val:0xae84; + valaddr_reg:x2; val_offset:332*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 332*FLEN/8, x6, x4, x5) + +inst_197: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x284 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x284 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e84; op2val:0xae84; + valaddr_reg:x2; val_offset:334*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 334*FLEN/8, x6, x4, x5) + +inst_198: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x284 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x284 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e84; op2val:0xae84; + valaddr_reg:x2; val_offset:336*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 336*FLEN/8, x6, x4, x5) + +inst_199: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x284 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x284 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e84; op2val:0xae84; + valaddr_reg:x2; val_offset:338*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 338*FLEN/8, x6, x4, x5) + +inst_200: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x359 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x359 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3759; op2val:0xb759; + valaddr_reg:x2; val_offset:340*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 340*FLEN/8, x6, x4, x5) + +inst_201: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x359 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x359 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3759; op2val:0xb759; + valaddr_reg:x2; val_offset:342*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 342*FLEN/8, x6, x4, x5) + +inst_202: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x359 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x359 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3759; op2val:0xb759; + valaddr_reg:x2; val_offset:344*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 344*FLEN/8, x6, x4, x5) + +inst_203: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x359 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x359 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3759; op2val:0xb759; + valaddr_reg:x2; val_offset:346*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 346*FLEN/8, x6, x4, x5) + +inst_204: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x359 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x359 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3759; op2val:0xb759; + valaddr_reg:x2; val_offset:348*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 348*FLEN/8, x6, x4, x5) + +inst_205: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0b7 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0b7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x34b7; op2val:0xb4b7; + valaddr_reg:x2; val_offset:350*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 350*FLEN/8, x6, x4, x5) + +inst_206: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0b7 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0b7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x34b7; op2val:0xb4b7; + valaddr_reg:x2; val_offset:352*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 352*FLEN/8, x6, x4, x5) + +inst_207: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0b7 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0b7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x34b7; op2val:0xb4b7; + valaddr_reg:x2; val_offset:354*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 354*FLEN/8, x6, x4, x5) + +inst_208: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0b7 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0b7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x34b7; op2val:0xb4b7; + valaddr_reg:x2; val_offset:356*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 356*FLEN/8, x6, x4, x5) + +inst_209: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0b7 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0b7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x34b7; op2val:0xb4b7; + valaddr_reg:x2; val_offset:358*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 358*FLEN/8, x6, x4, x5) + +inst_210: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x207 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x207 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3207; op2val:0xb207; + valaddr_reg:x2; val_offset:360*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 360*FLEN/8, x6, x4, x5) + +inst_211: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x207 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x207 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3207; op2val:0xb207; + valaddr_reg:x2; val_offset:362*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 362*FLEN/8, x6, x4, x5) + +inst_212: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x207 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x207 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3207; op2val:0xb207; + valaddr_reg:x2; val_offset:364*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 364*FLEN/8, x6, x4, x5) + +inst_213: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x207 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x207 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3207; op2val:0xb207; + valaddr_reg:x2; val_offset:366*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 366*FLEN/8, x6, x4, x5) + +inst_214: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x207 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x207 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3207; op2val:0xb207; + valaddr_reg:x2; val_offset:368*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 368*FLEN/8, x6, x4, x5) + +inst_215: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2b8 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x2b7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2eb8; op2val:0xaeb7; + valaddr_reg:x2; val_offset:370*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 370*FLEN/8, x6, x4, x5) + +inst_216: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2b8 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x2b7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2eb8; op2val:0xaeb7; + valaddr_reg:x2; val_offset:372*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 372*FLEN/8, x6, x4, x5) + +inst_217: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2b8 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x2b7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2eb8; op2val:0xaeb7; + valaddr_reg:x2; val_offset:374*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 374*FLEN/8, x6, x4, x5) + +inst_218: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2b8 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x2b7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2eb8; op2val:0xaeb7; + valaddr_reg:x2; val_offset:376*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 376*FLEN/8, x6, x4, x5) + +inst_219: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2b8 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x2b7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2eb8; op2val:0xaeb7; + valaddr_reg:x2; val_offset:378*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 378*FLEN/8, x6, x4, x5) + +inst_220: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x270 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x26e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2a70; op2val:0xaa6e; + valaddr_reg:x2; val_offset:380*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 380*FLEN/8, x6, x4, x5) + +inst_221: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x270 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x26e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2a70; op2val:0xaa6e; + valaddr_reg:x2; val_offset:382*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 382*FLEN/8, x6, x4, x5) + +inst_222: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x270 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x26e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2a70; op2val:0xaa6e; + valaddr_reg:x2; val_offset:384*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 384*FLEN/8, x6, x4, x5) + +inst_223: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x270 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x26e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2a70; op2val:0xaa6e; + valaddr_reg:x2; val_offset:386*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 386*FLEN/8, x6, x4, x5) + +inst_224: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x270 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x26e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2a70; op2val:0xaa6e; + valaddr_reg:x2; val_offset:388*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 388*FLEN/8, x6, x4, x5) + +inst_225: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x065 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x065 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3865; op2val:0xb865; + valaddr_reg:x2; val_offset:390*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 390*FLEN/8, x6, x4, x5) + +inst_226: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x065 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x065 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3865; op2val:0xb865; + valaddr_reg:x2; val_offset:392*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 392*FLEN/8, x6, x4, x5) + +inst_227: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x065 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x065 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3865; op2val:0xb865; + valaddr_reg:x2; val_offset:394*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 394*FLEN/8, x6, x4, x5) + +inst_228: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x065 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x065 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3865; op2val:0xb865; + valaddr_reg:x2; val_offset:396*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 396*FLEN/8, x6, x4, x5) + +inst_229: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x065 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x065 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3865; op2val:0xb865; + valaddr_reg:x2; val_offset:398*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 398*FLEN/8, x6, x4, x5) + +inst_230: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x3c9 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x3a9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1bc9; op2val:0x9ba9; + valaddr_reg:x2; val_offset:400*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 400*FLEN/8, x6, x4, x5) + +inst_231: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x3c9 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x3a9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1bc9; op2val:0x9ba9; + valaddr_reg:x2; val_offset:402*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 402*FLEN/8, x6, x4, x5) + +inst_232: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x3c9 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x3a9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1bc9; op2val:0x9ba9; + valaddr_reg:x2; val_offset:404*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 404*FLEN/8, x6, x4, x5) + +inst_233: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x3c9 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x3a9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1bc9; op2val:0x9ba9; + valaddr_reg:x2; val_offset:406*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 406*FLEN/8, x6, x4, x5) + +inst_234: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x3c9 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x3a9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1bc9; op2val:0x9ba9; + valaddr_reg:x2; val_offset:408*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 408*FLEN/8, x6, x4, x5) + +inst_235: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x29d and fs2 == 1 and fe2 == 0x0c and fm2 == 0x29c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x329d; op2val:0xb29c; + valaddr_reg:x2; val_offset:410*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 410*FLEN/8, x6, x4, x5) + +inst_236: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x29d and fs2 == 1 and fe2 == 0x0c and fm2 == 0x29c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x329d; op2val:0xb29c; + valaddr_reg:x2; val_offset:412*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 412*FLEN/8, x6, x4, x5) + +inst_237: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x29d and fs2 == 1 and fe2 == 0x0c and fm2 == 0x29c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x329d; op2val:0xb29c; + valaddr_reg:x2; val_offset:414*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 414*FLEN/8, x6, x4, x5) + +inst_238: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x29d and fs2 == 1 and fe2 == 0x0c and fm2 == 0x29c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x329d; op2val:0xb29c; + valaddr_reg:x2; val_offset:416*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 416*FLEN/8, x6, x4, x5) + +inst_239: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x29d and fs2 == 1 and fe2 == 0x0c and fm2 == 0x29c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x329d; op2val:0xb29c; + valaddr_reg:x2; val_offset:418*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 418*FLEN/8, x6, x4, x5) + +inst_240: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x232 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x231 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3632; op2val:0xb631; + valaddr_reg:x2; val_offset:420*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 420*FLEN/8, x6, x4, x5) + +inst_241: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x232 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x231 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3632; op2val:0xb631; + valaddr_reg:x2; val_offset:422*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 422*FLEN/8, x6, x4, x5) + +inst_242: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x232 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x231 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3632; op2val:0xb631; + valaddr_reg:x2; val_offset:424*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 424*FLEN/8, x6, x4, x5) + +inst_243: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x232 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x231 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3632; op2val:0xb631; + valaddr_reg:x2; val_offset:426*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 426*FLEN/8, x6, x4, x5) + +inst_244: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x232 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x231 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3632; op2val:0xb631; + valaddr_reg:x2; val_offset:428*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 428*FLEN/8, x6, x4, x5) + +inst_245: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1eb and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1ea and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x35eb; op2val:0xb5ea; + valaddr_reg:x2; val_offset:430*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 430*FLEN/8, x6, x4, x5) + +inst_246: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1eb and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1ea and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x35eb; op2val:0xb5ea; + valaddr_reg:x2; val_offset:432*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 432*FLEN/8, x6, x4, x5) + +inst_247: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1eb and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1ea and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x35eb; op2val:0xb5ea; + valaddr_reg:x2; val_offset:434*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 434*FLEN/8, x6, x4, x5) + +inst_248: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1eb and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1ea and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x35eb; op2val:0xb5ea; + valaddr_reg:x2; val_offset:436*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 436*FLEN/8, x6, x4, x5) + +inst_249: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1eb and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1ea and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x35eb; op2val:0xb5ea; + valaddr_reg:x2; val_offset:438*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 438*FLEN/8, x6, x4, x5) + +inst_250: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x20e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x20e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a0e; op2val:0xba0e; + valaddr_reg:x2; val_offset:440*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 440*FLEN/8, x6, x4, x5) + +inst_251: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x20e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x20e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a0e; op2val:0xba0e; + valaddr_reg:x2; val_offset:442*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 442*FLEN/8, x6, x4, x5) + +inst_252: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x20e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x20e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a0e; op2val:0xba0e; + valaddr_reg:x2; val_offset:444*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 444*FLEN/8, x6, x4, x5) + +inst_253: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x20e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x20e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a0e; op2val:0xba0e; + valaddr_reg:x2; val_offset:446*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 446*FLEN/8, x6, x4, x5) + +inst_254: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x20e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x20e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a0e; op2val:0xba0e; + valaddr_reg:x2; val_offset:448*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 448*FLEN/8, x6, x4, x5) + +inst_255: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x310 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x30f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b10; op2val:0xbb0f; + valaddr_reg:x2; val_offset:450*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 450*FLEN/8, x6, x4, x5) + +inst_256: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x310 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x30f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b10; op2val:0xbb0f; + valaddr_reg:x2; val_offset:452*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 452*FLEN/8, x6, x4, x5) + +inst_257: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x310 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x30f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b10; op2val:0xbb0f; + valaddr_reg:x2; val_offset:454*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 454*FLEN/8, x6, x4, x5) + +inst_258: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x310 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x30f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b10; op2val:0xbb0f; + valaddr_reg:x2; val_offset:456*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 456*FLEN/8, x6, x4, x5) + +inst_259: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x310 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x30f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b10; op2val:0xbb0f; + valaddr_reg:x2; val_offset:458*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 458*FLEN/8, x6, x4, x5) + +inst_260: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x293 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x292 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3293; op2val:0xb292; + valaddr_reg:x2; val_offset:460*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 460*FLEN/8, x6, x4, x5) + +inst_261: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x293 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x292 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3293; op2val:0xb292; + valaddr_reg:x2; val_offset:462*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 462*FLEN/8, x6, x4, x5) + +inst_262: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x293 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x292 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3293; op2val:0xb292; + valaddr_reg:x2; val_offset:464*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 464*FLEN/8, x6, x4, x5) + +inst_263: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x293 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x292 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3293; op2val:0xb292; + valaddr_reg:x2; val_offset:466*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 466*FLEN/8, x6, x4, x5) + +inst_264: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x293 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x292 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3293; op2val:0xb292; + valaddr_reg:x2; val_offset:468*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 468*FLEN/8, x6, x4, x5) + +inst_265: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1e4 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x1e3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x31e4; op2val:0xb1e3; + valaddr_reg:x2; val_offset:470*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 470*FLEN/8, x6, x4, x5) + +inst_266: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1e4 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x1e3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x31e4; op2val:0xb1e3; + valaddr_reg:x2; val_offset:472*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 472*FLEN/8, x6, x4, x5) + +inst_267: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1e4 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x1e3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x31e4; op2val:0xb1e3; + valaddr_reg:x2; val_offset:474*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 474*FLEN/8, x6, x4, x5) + +inst_268: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1e4 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x1e3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x31e4; op2val:0xb1e3; + valaddr_reg:x2; val_offset:476*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 476*FLEN/8, x6, x4, x5) + +inst_269: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1e4 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x1e3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x31e4; op2val:0xb1e3; + valaddr_reg:x2; val_offset:478*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 478*FLEN/8, x6, x4, x5) + +inst_270: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2d4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ad4; op2val:0xbad4; + valaddr_reg:x2; val_offset:480*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 480*FLEN/8, x6, x4, x5) + +inst_271: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2d4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ad4; op2val:0xbad4; + valaddr_reg:x2; val_offset:482*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 482*FLEN/8, x6, x4, x5) + +inst_272: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2d4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ad4; op2val:0xbad4; + valaddr_reg:x2; val_offset:484*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 484*FLEN/8, x6, x4, x5) + +inst_273: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2d4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ad4; op2val:0xbad4; + valaddr_reg:x2; val_offset:486*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 486*FLEN/8, x6, x4, x5) + +inst_274: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2d4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ad4; op2val:0xbad4; + valaddr_reg:x2; val_offset:488*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 488*FLEN/8, x6, x4, x5) + +inst_275: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3a3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3a3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ba3; op2val:0xbba3; + valaddr_reg:x2; val_offset:490*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 490*FLEN/8, x6, x4, x5) + +inst_276: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3a3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3a3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ba3; op2val:0xbba3; + valaddr_reg:x2; val_offset:492*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 492*FLEN/8, x6, x4, x5) + +inst_277: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3a3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3a3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ba3; op2val:0xbba3; + valaddr_reg:x2; val_offset:494*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 494*FLEN/8, x6, x4, x5) + +inst_278: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3a3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3a3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ba3; op2val:0xbba3; + valaddr_reg:x2; val_offset:496*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 496*FLEN/8, x6, x4, x5) + +inst_279: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3a3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3a3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ba3; op2val:0xbba3; + valaddr_reg:x2; val_offset:498*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 498*FLEN/8, x6, x4, x5) + +inst_280: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1c3 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1c2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2dc3; op2val:0xadc2; + valaddr_reg:x2; val_offset:500*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 500*FLEN/8, x6, x4, x5) + +inst_281: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1c3 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1c2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2dc3; op2val:0xadc2; + valaddr_reg:x2; val_offset:502*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 502*FLEN/8, x6, x4, x5) +RVTEST_SIGBASE(x4,signature_x4_2) + +inst_282: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1c3 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1c2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2dc3; op2val:0xadc2; + valaddr_reg:x2; val_offset:504*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 504*FLEN/8, x6, x4, x5) + +inst_283: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1c3 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1c2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2dc3; op2val:0xadc2; + valaddr_reg:x2; val_offset:506*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 506*FLEN/8, x6, x4, x5) + +inst_284: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1c3 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1c2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2dc3; op2val:0xadc2; + valaddr_reg:x2; val_offset:508*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 508*FLEN/8, x6, x4, x5) + +inst_285: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x11c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x11c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x351c; op2val:0xb51c; + valaddr_reg:x2; val_offset:510*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 510*FLEN/8, x6, x4, x5) + +inst_286: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x11c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x11c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x351c; op2val:0xb51c; + valaddr_reg:x2; val_offset:512*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 512*FLEN/8, x6, x4, x5) + +inst_287: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x11c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x11c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x351c; op2val:0xb51c; + valaddr_reg:x2; val_offset:514*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 514*FLEN/8, x6, x4, x5) + +inst_288: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x11c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x11c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x351c; op2val:0xb51c; + valaddr_reg:x2; val_offset:516*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 516*FLEN/8, x6, x4, x5) + +inst_289: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x11c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x11c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x351c; op2val:0xb51c; + valaddr_reg:x2; val_offset:518*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 518*FLEN/8, x6, x4, x5) + +inst_290: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1d7 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1d6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x35d7; op2val:0xb5d6; + valaddr_reg:x2; val_offset:520*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 520*FLEN/8, x6, x4, x5) + +inst_291: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1d7 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1d6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x35d7; op2val:0xb5d6; + valaddr_reg:x2; val_offset:522*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 522*FLEN/8, x6, x4, x5) + +inst_292: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1d7 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1d6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x35d7; op2val:0xb5d6; + valaddr_reg:x2; val_offset:524*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 524*FLEN/8, x6, x4, x5) + +inst_293: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1d7 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1d6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x35d7; op2val:0xb5d6; + valaddr_reg:x2; val_offset:526*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 526*FLEN/8, x6, x4, x5) + +inst_294: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1d7 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1d6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x35d7; op2val:0xb5d6; + valaddr_reg:x2; val_offset:528*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 528*FLEN/8, x6, x4, x5) + +inst_295: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2c9 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2c8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x36c9; op2val:0xb6c8; + valaddr_reg:x2; val_offset:530*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 530*FLEN/8, x6, x4, x5) + +inst_296: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2c9 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2c8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x36c9; op2val:0xb6c8; + valaddr_reg:x2; val_offset:532*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 532*FLEN/8, x6, x4, x5) + +inst_297: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2c9 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2c8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x36c9; op2val:0xb6c8; + valaddr_reg:x2; val_offset:534*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 534*FLEN/8, x6, x4, x5) + +inst_298: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2c9 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2c8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x36c9; op2val:0xb6c8; + valaddr_reg:x2; val_offset:536*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 536*FLEN/8, x6, x4, x5) + +inst_299: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2c9 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2c8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x36c9; op2val:0xb6c8; + valaddr_reg:x2; val_offset:538*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 538*FLEN/8, x6, x4, x5) + +inst_300: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x109 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x109 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3909; op2val:0xb909; + valaddr_reg:x2; val_offset:540*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 540*FLEN/8, x6, x4, x5) + +inst_301: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x109 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x109 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3909; op2val:0xb909; + valaddr_reg:x2; val_offset:542*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 542*FLEN/8, x6, x4, x5) + +inst_302: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x109 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x109 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3909; op2val:0xb909; + valaddr_reg:x2; val_offset:544*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 544*FLEN/8, x6, x4, x5) + +inst_303: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x109 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x109 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3909; op2val:0xb909; + valaddr_reg:x2; val_offset:546*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 546*FLEN/8, x6, x4, x5) + +inst_304: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x109 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x109 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3909; op2val:0xb909; + valaddr_reg:x2; val_offset:548*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 548*FLEN/8, x6, x4, x5) + +inst_305: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bb5; op2val:0xbbb5; + valaddr_reg:x2; val_offset:550*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 550*FLEN/8, x6, x4, x5) + +inst_306: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bb5; op2val:0xbbb5; + valaddr_reg:x2; val_offset:552*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 552*FLEN/8, x6, x4, x5) + +inst_307: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bb5; op2val:0xbbb5; + valaddr_reg:x2; val_offset:554*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 554*FLEN/8, x6, x4, x5) + +inst_308: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bb5; op2val:0xbbb5; + valaddr_reg:x2; val_offset:556*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 556*FLEN/8, x6, x4, x5) + +inst_309: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bb5; op2val:0xbbb5; + valaddr_reg:x2; val_offset:558*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 558*FLEN/8, x6, x4, x5) + +inst_310: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x0fe and fs2 == 1 and fe2 == 0x0a and fm2 == 0x0fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x28fe; op2val:0xa8fc; + valaddr_reg:x2; val_offset:560*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 560*FLEN/8, x6, x4, x5) + +inst_311: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x0fe and fs2 == 1 and fe2 == 0x0a and fm2 == 0x0fc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x28fe; op2val:0xa8fc; + valaddr_reg:x2; val_offset:562*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 562*FLEN/8, x6, x4, x5) + +inst_312: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x0fe and fs2 == 1 and fe2 == 0x0a and fm2 == 0x0fc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x28fe; op2val:0xa8fc; + valaddr_reg:x2; val_offset:564*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 564*FLEN/8, x6, x4, x5) + +inst_313: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x0fe and fs2 == 1 and fe2 == 0x0a and fm2 == 0x0fc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x28fe; op2val:0xa8fc; + valaddr_reg:x2; val_offset:566*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 566*FLEN/8, x6, x4, x5) + +inst_314: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x0fe and fs2 == 1 and fe2 == 0x0a and fm2 == 0x0fc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x28fe; op2val:0xa8fc; + valaddr_reg:x2; val_offset:568*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 568*FLEN/8, x6, x4, x5) + +inst_315: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x302 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x302 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b02; op2val:0xbb02; + valaddr_reg:x2; val_offset:570*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 570*FLEN/8, x6, x4, x5) + +inst_316: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x302 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x302 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b02; op2val:0xbb02; + valaddr_reg:x2; val_offset:572*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 572*FLEN/8, x6, x4, x5) + +inst_317: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x302 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x302 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b02; op2val:0xbb02; + valaddr_reg:x2; val_offset:574*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 574*FLEN/8, x6, x4, x5) + +inst_318: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x302 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x302 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b02; op2val:0xbb02; + valaddr_reg:x2; val_offset:576*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 576*FLEN/8, x6, x4, x5) + +inst_319: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x302 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x302 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b02; op2val:0xbb02; + valaddr_reg:x2; val_offset:578*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 578*FLEN/8, x6, x4, x5) + +inst_320: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x260 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x260 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3260; op2val:0xb260; + valaddr_reg:x2; val_offset:580*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 580*FLEN/8, x6, x4, x5) + +inst_321: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x260 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x260 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3260; op2val:0xb260; + valaddr_reg:x2; val_offset:582*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 582*FLEN/8, x6, x4, x5) + +inst_322: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x260 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x260 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3260; op2val:0xb260; + valaddr_reg:x2; val_offset:584*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 584*FLEN/8, x6, x4, x5) + +inst_323: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x260 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x260 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3260; op2val:0xb260; + valaddr_reg:x2; val_offset:586*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 586*FLEN/8, x6, x4, x5) + +inst_324: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x260 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x260 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3260; op2val:0xb260; + valaddr_reg:x2; val_offset:588*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 588*FLEN/8, x6, x4, x5) + +inst_325: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d1 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3d1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bd1; op2val:0xbbd1; + valaddr_reg:x2; val_offset:590*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 590*FLEN/8, x6, x4, x5) + +inst_326: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d1 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3d1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bd1; op2val:0xbbd1; + valaddr_reg:x2; val_offset:592*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 592*FLEN/8, x6, x4, x5) + +inst_327: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d1 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3d1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bd1; op2val:0xbbd1; + valaddr_reg:x2; val_offset:594*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 594*FLEN/8, x6, x4, x5) + +inst_328: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d1 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3d1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bd1; op2val:0xbbd1; + valaddr_reg:x2; val_offset:596*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 596*FLEN/8, x6, x4, x5) + +inst_329: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d1 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3d1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bd1; op2val:0xbbd1; + valaddr_reg:x2; val_offset:598*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 598*FLEN/8, x6, x4, x5) + +inst_330: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x330 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x330 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b30; op2val:0xbb30; + valaddr_reg:x2; val_offset:600*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 600*FLEN/8, x6, x4, x5) + +inst_331: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x330 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x330 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b30; op2val:0xbb30; + valaddr_reg:x2; val_offset:602*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 602*FLEN/8, x6, x4, x5) + +inst_332: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x330 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x330 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b30; op2val:0xbb30; + valaddr_reg:x2; val_offset:604*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 604*FLEN/8, x6, x4, x5) + +inst_333: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x330 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x330 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b30; op2val:0xbb30; + valaddr_reg:x2; val_offset:606*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 606*FLEN/8, x6, x4, x5) + +inst_334: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x330 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x330 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b30; op2val:0xbb30; + valaddr_reg:x2; val_offset:608*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 608*FLEN/8, x6, x4, x5) + +inst_335: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x23b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a3b; op2val:0xba3b; + valaddr_reg:x2; val_offset:610*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 610*FLEN/8, x6, x4, x5) + +inst_336: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x23b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a3b; op2val:0xba3b; + valaddr_reg:x2; val_offset:612*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 612*FLEN/8, x6, x4, x5) + +inst_337: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x23b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a3b; op2val:0xba3b; + valaddr_reg:x2; val_offset:614*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 614*FLEN/8, x6, x4, x5) + +inst_338: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x23b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a3b; op2val:0xba3b; + valaddr_reg:x2; val_offset:616*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 616*FLEN/8, x6, x4, x5) + +inst_339: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x23b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a3b; op2val:0xba3b; + valaddr_reg:x2; val_offset:618*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 618*FLEN/8, x6, x4, x5) + +inst_340: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x132 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x132 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3932; op2val:0xb932; + valaddr_reg:x2; val_offset:620*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 620*FLEN/8, x6, x4, x5) + +inst_341: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x132 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x132 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3932; op2val:0xb932; + valaddr_reg:x2; val_offset:622*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 622*FLEN/8, x6, x4, x5) + +inst_342: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x132 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x132 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3932; op2val:0xb932; + valaddr_reg:x2; val_offset:624*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 624*FLEN/8, x6, x4, x5) + +inst_343: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x132 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x132 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3932; op2val:0xb932; + valaddr_reg:x2; val_offset:626*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 626*FLEN/8, x6, x4, x5) + +inst_344: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x132 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x132 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3932; op2val:0xb932; + valaddr_reg:x2; val_offset:628*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 628*FLEN/8, x6, x4, x5) + +inst_345: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3f1 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x37f1; op2val:0xb7f0; + valaddr_reg:x2; val_offset:630*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 630*FLEN/8, x6, x4, x5) + +inst_346: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3f1 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3f0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x37f1; op2val:0xb7f0; + valaddr_reg:x2; val_offset:632*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 632*FLEN/8, x6, x4, x5) + +inst_347: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3f1 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3f0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x37f1; op2val:0xb7f0; + valaddr_reg:x2; val_offset:634*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 634*FLEN/8, x6, x4, x5) + +inst_348: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3f1 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3f0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x37f1; op2val:0xb7f0; + valaddr_reg:x2; val_offset:636*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 636*FLEN/8, x6, x4, x5) + +inst_349: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3f1 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3f0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x37f1; op2val:0xb7f0; + valaddr_reg:x2; val_offset:638*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 638*FLEN/8, x6, x4, x5) + +inst_350: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x331 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x331 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b31; op2val:0xbb31; + valaddr_reg:x2; val_offset:640*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 640*FLEN/8, x6, x4, x5) + +inst_351: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x331 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x331 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b31; op2val:0xbb31; + valaddr_reg:x2; val_offset:642*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 642*FLEN/8, x6, x4, x5) + +inst_352: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x331 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x331 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b31; op2val:0xbb31; + valaddr_reg:x2; val_offset:644*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 644*FLEN/8, x6, x4, x5) + +inst_353: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x331 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x331 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b31; op2val:0xbb31; + valaddr_reg:x2; val_offset:646*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 646*FLEN/8, x6, x4, x5) + +inst_354: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x331 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x331 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b31; op2val:0xbb31; + valaddr_reg:x2; val_offset:648*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 648*FLEN/8, x6, x4, x5) + +inst_355: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x267 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x267 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a67; op2val:0xba67; + valaddr_reg:x2; val_offset:650*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 650*FLEN/8, x6, x4, x5) + +inst_356: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x267 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x267 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a67; op2val:0xba67; + valaddr_reg:x2; val_offset:652*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 652*FLEN/8, x6, x4, x5) + +inst_357: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x267 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x267 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a67; op2val:0xba67; + valaddr_reg:x2; val_offset:654*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 654*FLEN/8, x6, x4, x5) + +inst_358: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x267 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x267 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a67; op2val:0xba67; + valaddr_reg:x2; val_offset:656*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 656*FLEN/8, x6, x4, x5) + +inst_359: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x267 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x267 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a67; op2val:0xba67; + valaddr_reg:x2; val_offset:658*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 658*FLEN/8, x6, x4, x5) + +inst_360: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x04b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x04b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x344b; op2val:0xb44b; + valaddr_reg:x2; val_offset:660*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 660*FLEN/8, x6, x4, x5) + +inst_361: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x04b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x04b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x344b; op2val:0xb44b; + valaddr_reg:x2; val_offset:662*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 662*FLEN/8, x6, x4, x5) + +inst_362: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x04b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x04b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x344b; op2val:0xb44b; + valaddr_reg:x2; val_offset:664*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 664*FLEN/8, x6, x4, x5) + +inst_363: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x04b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x04b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x344b; op2val:0xb44b; + valaddr_reg:x2; val_offset:666*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 666*FLEN/8, x6, x4, x5) + +inst_364: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x04b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x04b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x344b; op2val:0xb44b; + valaddr_reg:x2; val_offset:668*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 668*FLEN/8, x6, x4, x5) + +inst_365: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x138 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x137 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d38; op2val:0xad37; + valaddr_reg:x2; val_offset:670*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 670*FLEN/8, x6, x4, x5) + +inst_366: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x138 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x137 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d38; op2val:0xad37; + valaddr_reg:x2; val_offset:672*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 672*FLEN/8, x6, x4, x5) + +inst_367: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x138 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x137 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d38; op2val:0xad37; + valaddr_reg:x2; val_offset:674*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 674*FLEN/8, x6, x4, x5) + +inst_368: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x138 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x137 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d38; op2val:0xad37; + valaddr_reg:x2; val_offset:676*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 676*FLEN/8, x6, x4, x5) + +inst_369: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x138 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x137 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d38; op2val:0xad37; + valaddr_reg:x2; val_offset:678*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 678*FLEN/8, x6, x4, x5) + +inst_370: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x13d and fs2 == 1 and fe2 == 0x0d and fm2 == 0x13c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x353d; op2val:0xb53c; + valaddr_reg:x2; val_offset:680*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 680*FLEN/8, x6, x4, x5) + +inst_371: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x13d and fs2 == 1 and fe2 == 0x0d and fm2 == 0x13c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x353d; op2val:0xb53c; + valaddr_reg:x2; val_offset:682*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 682*FLEN/8, x6, x4, x5) + +inst_372: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x13d and fs2 == 1 and fe2 == 0x0d and fm2 == 0x13c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x353d; op2val:0xb53c; + valaddr_reg:x2; val_offset:684*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 684*FLEN/8, x6, x4, x5) + +inst_373: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x13d and fs2 == 1 and fe2 == 0x0d and fm2 == 0x13c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x353d; op2val:0xb53c; + valaddr_reg:x2; val_offset:686*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 686*FLEN/8, x6, x4, x5) + +inst_374: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x13d and fs2 == 1 and fe2 == 0x0d and fm2 == 0x13c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x353d; op2val:0xb53c; + valaddr_reg:x2; val_offset:688*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 688*FLEN/8, x6, x4, x5) + +inst_375: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x389 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x388 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b89; op2val:0xbb88; + valaddr_reg:x2; val_offset:690*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 690*FLEN/8, x6, x4, x5) + +inst_376: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x389 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x388 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b89; op2val:0xbb88; + valaddr_reg:x2; val_offset:692*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 692*FLEN/8, x6, x4, x5) + +inst_377: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x389 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x388 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b89; op2val:0xbb88; + valaddr_reg:x2; val_offset:694*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 694*FLEN/8, x6, x4, x5) + +inst_378: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x389 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x388 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b89; op2val:0xbb88; + valaddr_reg:x2; val_offset:696*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 696*FLEN/8, x6, x4, x5) + +inst_379: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x389 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x388 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b89; op2val:0xbb88; + valaddr_reg:x2; val_offset:698*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 698*FLEN/8, x6, x4, x5) + +inst_380: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0f2 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0f2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x30f2; op2val:0xb0f2; + valaddr_reg:x2; val_offset:700*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 700*FLEN/8, x6, x4, x5) + +inst_381: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0f2 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0f2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x30f2; op2val:0xb0f2; + valaddr_reg:x2; val_offset:702*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 702*FLEN/8, x6, x4, x5) + +inst_382: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0f2 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0f2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x30f2; op2val:0xb0f2; + valaddr_reg:x2; val_offset:704*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 704*FLEN/8, x6, x4, x5) + +inst_383: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0f2 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0f2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x30f2; op2val:0xb0f2; + valaddr_reg:x2; val_offset:706*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 706*FLEN/8, x6, x4, x5) + +inst_384: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0f2 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0f2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x30f2; op2val:0xb0f2; + valaddr_reg:x2; val_offset:708*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 708*FLEN/8, x6, x4, x5) + +inst_385: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fe and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x39fe; op2val:0xb9fe; + valaddr_reg:x2; val_offset:710*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 710*FLEN/8, x6, x4, x5) + +inst_386: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fe and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1fe and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x39fe; op2val:0xb9fe; + valaddr_reg:x2; val_offset:712*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 712*FLEN/8, x6, x4, x5) + +inst_387: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fe and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1fe and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x39fe; op2val:0xb9fe; + valaddr_reg:x2; val_offset:714*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 714*FLEN/8, x6, x4, x5) + +inst_388: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fe and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1fe and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x39fe; op2val:0xb9fe; + valaddr_reg:x2; val_offset:716*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 716*FLEN/8, x6, x4, x5) + +inst_389: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fe and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1fe and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x39fe; op2val:0xb9fe; + valaddr_reg:x2; val_offset:718*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 718*FLEN/8, x6, x4, x5) + +inst_390: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x076 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x076 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3876; op2val:0xb876; + valaddr_reg:x2; val_offset:720*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 720*FLEN/8, x6, x4, x5) + +inst_391: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x076 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x076 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3876; op2val:0xb876; + valaddr_reg:x2; val_offset:722*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 722*FLEN/8, x6, x4, x5) + +inst_392: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x076 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x076 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3876; op2val:0xb876; + valaddr_reg:x2; val_offset:724*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 724*FLEN/8, x6, x4, x5) + +inst_393: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x076 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x076 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3876; op2val:0xb876; + valaddr_reg:x2; val_offset:726*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 726*FLEN/8, x6, x4, x5) + +inst_394: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x076 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x076 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3876; op2val:0xb876; + valaddr_reg:x2; val_offset:728*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 728*FLEN/8, x6, x4, x5) + +inst_395: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x03a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x03a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x383a; op2val:0xb83a; + valaddr_reg:x2; val_offset:730*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 730*FLEN/8, x6, x4, x5) + +inst_396: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x03a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x03a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x383a; op2val:0xb83a; + valaddr_reg:x2; val_offset:732*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 732*FLEN/8, x6, x4, x5) + +inst_397: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x03a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x03a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x383a; op2val:0xb83a; + valaddr_reg:x2; val_offset:734*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 734*FLEN/8, x6, x4, x5) + +inst_398: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x03a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x03a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x383a; op2val:0xb83a; + valaddr_reg:x2; val_offset:736*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 736*FLEN/8, x6, x4, x5) + +inst_399: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x03a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x03a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x383a; op2val:0xb83a; + valaddr_reg:x2; val_offset:738*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 738*FLEN/8, x6, x4, x5) + +inst_400: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2e5 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2e4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x36e5; op2val:0xb6e4; + valaddr_reg:x2; val_offset:740*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 740*FLEN/8, x6, x4, x5) + +inst_401: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2e5 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2e4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x36e5; op2val:0xb6e4; + valaddr_reg:x2; val_offset:742*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 742*FLEN/8, x6, x4, x5) + +inst_402: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2e5 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2e4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x36e5; op2val:0xb6e4; + valaddr_reg:x2; val_offset:744*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 744*FLEN/8, x6, x4, x5) + +inst_403: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2e5 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2e4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x36e5; op2val:0xb6e4; + valaddr_reg:x2; val_offset:746*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 746*FLEN/8, x6, x4, x5) + +inst_404: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2e5 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2e4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x36e5; op2val:0xb6e4; + valaddr_reg:x2; val_offset:748*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 748*FLEN/8, x6, x4, x5) + +inst_405: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x182 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x182 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3982; op2val:0xb982; + valaddr_reg:x2; val_offset:750*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 750*FLEN/8, x6, x4, x5) + +inst_406: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x182 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x182 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3982; op2val:0xb982; + valaddr_reg:x2; val_offset:752*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 752*FLEN/8, x6, x4, x5) + +inst_407: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x182 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x182 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3982; op2val:0xb982; + valaddr_reg:x2; val_offset:754*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 754*FLEN/8, x6, x4, x5) + +inst_408: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x182 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x182 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3982; op2val:0xb982; + valaddr_reg:x2; val_offset:756*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 756*FLEN/8, x6, x4, x5) + +inst_409: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x182 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x182 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3982; op2val:0xb982; + valaddr_reg:x2; val_offset:758*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 758*FLEN/8, x6, x4, x5) +RVTEST_SIGBASE(x4,signature_x4_3) + +inst_410: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x132 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x131 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3132; op2val:0xb131; + valaddr_reg:x2; val_offset:760*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 760*FLEN/8, x6, x4, x5) + +inst_411: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x132 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x131 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3132; op2val:0xb131; + valaddr_reg:x2; val_offset:762*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 762*FLEN/8, x6, x4, x5) + +inst_412: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x132 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x131 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3132; op2val:0xb131; + valaddr_reg:x2; val_offset:764*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 764*FLEN/8, x6, x4, x5) + +inst_413: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x132 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x131 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3132; op2val:0xb131; + valaddr_reg:x2; val_offset:766*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 766*FLEN/8, x6, x4, x5) + +inst_414: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x132 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x131 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3132; op2val:0xb131; + valaddr_reg:x2; val_offset:768*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 768*FLEN/8, x6, x4, x5) + +inst_415: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x307 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x307 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3707; op2val:0xb707; + valaddr_reg:x2; val_offset:770*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 770*FLEN/8, x6, x4, x5) + +inst_416: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x307 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x307 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3707; op2val:0xb707; + valaddr_reg:x2; val_offset:772*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 772*FLEN/8, x6, x4, x5) + +inst_417: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x307 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x307 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3707; op2val:0xb707; + valaddr_reg:x2; val_offset:774*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 774*FLEN/8, x6, x4, x5) + +inst_418: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x307 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x307 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3707; op2val:0xb707; + valaddr_reg:x2; val_offset:776*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 776*FLEN/8, x6, x4, x5) + +inst_419: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x307 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x307 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3707; op2val:0xb707; + valaddr_reg:x2; val_offset:778*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 778*FLEN/8, x6, x4, x5) + +inst_420: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x022 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x022 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3422; op2val:0xb422; + valaddr_reg:x2; val_offset:780*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 780*FLEN/8, x6, x4, x5) + +inst_421: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x022 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x022 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3422; op2val:0xb422; + valaddr_reg:x2; val_offset:782*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 782*FLEN/8, x6, x4, x5) + +inst_422: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x022 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x022 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3422; op2val:0xb422; + valaddr_reg:x2; val_offset:784*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 784*FLEN/8, x6, x4, x5) + +inst_423: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x022 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x022 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3422; op2val:0xb422; + valaddr_reg:x2; val_offset:786*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 786*FLEN/8, x6, x4, x5) + +inst_424: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x022 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x022 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3422; op2val:0xb422; + valaddr_reg:x2; val_offset:788*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 788*FLEN/8, x6, x4, x5) + +inst_425: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3a2 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3a2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ba2; op2val:0xbba2; + valaddr_reg:x2; val_offset:790*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 790*FLEN/8, x6, x4, x5) + +inst_426: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3a2 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3a2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ba2; op2val:0xbba2; + valaddr_reg:x2; val_offset:792*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 792*FLEN/8, x6, x4, x5) + +inst_427: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3a2 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3a2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ba2; op2val:0xbba2; + valaddr_reg:x2; val_offset:794*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 794*FLEN/8, x6, x4, x5) + +inst_428: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3a2 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3a2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ba2; op2val:0xbba2; + valaddr_reg:x2; val_offset:796*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 796*FLEN/8, x6, x4, x5) + +inst_429: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3a2 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3a2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ba2; op2val:0xbba2; + valaddr_reg:x2; val_offset:798*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 798*FLEN/8, x6, x4, x5) + +inst_430: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x214 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x214 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a14; op2val:0xba14; + valaddr_reg:x2; val_offset:800*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 800*FLEN/8, x6, x4, x5) + +inst_431: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x214 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x214 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a14; op2val:0xba14; + valaddr_reg:x2; val_offset:802*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 802*FLEN/8, x6, x4, x5) + +inst_432: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x214 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x214 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a14; op2val:0xba14; + valaddr_reg:x2; val_offset:804*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 804*FLEN/8, x6, x4, x5) + +inst_433: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x214 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x214 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a14; op2val:0xba14; + valaddr_reg:x2; val_offset:806*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 806*FLEN/8, x6, x4, x5) + +inst_434: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x214 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x214 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a14; op2val:0xba14; + valaddr_reg:x2; val_offset:808*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 808*FLEN/8, x6, x4, x5) + +inst_435: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x12e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x12e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x392e; op2val:0xb92e; + valaddr_reg:x2; val_offset:810*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 810*FLEN/8, x6, x4, x5) + +inst_436: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x12e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x12e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x392e; op2val:0xb92e; + valaddr_reg:x2; val_offset:812*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 812*FLEN/8, x6, x4, x5) + +inst_437: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x12e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x12e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x392e; op2val:0xb92e; + valaddr_reg:x2; val_offset:814*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 814*FLEN/8, x6, x4, x5) + +inst_438: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x12e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x12e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x392e; op2val:0xb92e; + valaddr_reg:x2; val_offset:816*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 816*FLEN/8, x6, x4, x5) + +inst_439: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x12e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x12e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x392e; op2val:0xb92e; + valaddr_reg:x2; val_offset:818*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 818*FLEN/8, x6, x4, x5) + +inst_440: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x120 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x120 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3920; op2val:0xb920; + valaddr_reg:x2; val_offset:820*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 820*FLEN/8, x6, x4, x5) + +inst_441: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x120 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x120 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3920; op2val:0xb920; + valaddr_reg:x2; val_offset:822*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 822*FLEN/8, x6, x4, x5) + +inst_442: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x120 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x120 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3920; op2val:0xb920; + valaddr_reg:x2; val_offset:824*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 824*FLEN/8, x6, x4, x5) + +inst_443: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x120 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x120 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3920; op2val:0xb920; + valaddr_reg:x2; val_offset:826*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 826*FLEN/8, x6, x4, x5) + +inst_444: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x120 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x120 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3920; op2val:0xb920; + valaddr_reg:x2; val_offset:828*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 828*FLEN/8, x6, x4, x5) + +inst_445: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1dc and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1dc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x35dc; op2val:0xb5dc; + valaddr_reg:x2; val_offset:830*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 830*FLEN/8, x6, x4, x5) + +inst_446: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1dc and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1dc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x35dc; op2val:0xb5dc; + valaddr_reg:x2; val_offset:832*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 832*FLEN/8, x6, x4, x5) + +inst_447: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1dc and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1dc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x35dc; op2val:0xb5dc; + valaddr_reg:x2; val_offset:834*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 834*FLEN/8, x6, x4, x5) + +inst_448: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1dc and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1dc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x35dc; op2val:0xb5dc; + valaddr_reg:x2; val_offset:836*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 836*FLEN/8, x6, x4, x5) + +inst_449: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1dc and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1dc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x35dc; op2val:0xb5dc; + valaddr_reg:x2; val_offset:838*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 838*FLEN/8, x6, x4, x5) + +inst_450: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x08c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x08c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x348c; op2val:0xb48c; + valaddr_reg:x2; val_offset:840*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 840*FLEN/8, x6, x4, x5) + +inst_451: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x08c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x08c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x348c; op2val:0xb48c; + valaddr_reg:x2; val_offset:842*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 842*FLEN/8, x6, x4, x5) + +inst_452: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x08c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x08c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x348c; op2val:0xb48c; + valaddr_reg:x2; val_offset:844*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 844*FLEN/8, x6, x4, x5) + +inst_453: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x08c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x08c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x348c; op2val:0xb48c; + valaddr_reg:x2; val_offset:846*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 846*FLEN/8, x6, x4, x5) + +inst_454: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x08c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x08c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x348c; op2val:0xb48c; + valaddr_reg:x2; val_offset:848*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 848*FLEN/8, x6, x4, x5) + +inst_455: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0af and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0af and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x38af; op2val:0xb8af; + valaddr_reg:x2; val_offset:850*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 850*FLEN/8, x6, x4, x5) + +inst_456: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0af and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0af and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x38af; op2val:0xb8af; + valaddr_reg:x2; val_offset:852*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 852*FLEN/8, x6, x4, x5) + +inst_457: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0af and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0af and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x38af; op2val:0xb8af; + valaddr_reg:x2; val_offset:854*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 854*FLEN/8, x6, x4, x5) + +inst_458: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0af and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0af and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x38af; op2val:0xb8af; + valaddr_reg:x2; val_offset:856*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 856*FLEN/8, x6, x4, x5) + +inst_459: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0af and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0af and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x38af; op2val:0xb8af; + valaddr_reg:x2; val_offset:858*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 858*FLEN/8, x6, x4, x5) + +inst_460: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bfc; op2val:0xbbfc; + valaddr_reg:x2; val_offset:860*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 860*FLEN/8, x6, x4, x5) + +inst_461: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3fc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bfc; op2val:0xbbfc; + valaddr_reg:x2; val_offset:862*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 862*FLEN/8, x6, x4, x5) + +inst_462: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3fc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bfc; op2val:0xbbfc; + valaddr_reg:x2; val_offset:864*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 864*FLEN/8, x6, x4, x5) + +inst_463: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3fc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bfc; op2val:0xbbfc; + valaddr_reg:x2; val_offset:866*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 866*FLEN/8, x6, x4, x5) + +inst_464: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3fc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bfc; op2val:0xbbfc; + valaddr_reg:x2; val_offset:868*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 868*FLEN/8, x6, x4, x5) + +inst_465: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x153 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x153 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3953; op2val:0xb953; + valaddr_reg:x2; val_offset:870*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 870*FLEN/8, x6, x4, x5) + +inst_466: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x153 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x153 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3953; op2val:0xb953; + valaddr_reg:x2; val_offset:872*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 872*FLEN/8, x6, x4, x5) + +inst_467: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x153 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x153 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3953; op2val:0xb953; + valaddr_reg:x2; val_offset:874*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 874*FLEN/8, x6, x4, x5) + +inst_468: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x153 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x153 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3953; op2val:0xb953; + valaddr_reg:x2; val_offset:876*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 876*FLEN/8, x6, x4, x5) + +inst_469: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x153 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x153 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3953; op2val:0xb953; + valaddr_reg:x2; val_offset:878*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 878*FLEN/8, x6, x4, x5) + +inst_470: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1cd and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1cd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x35cd; op2val:0xb5cd; + valaddr_reg:x2; val_offset:880*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 880*FLEN/8, x6, x4, x5) + +inst_471: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1cd and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1cd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x35cd; op2val:0xb5cd; + valaddr_reg:x2; val_offset:882*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 882*FLEN/8, x6, x4, x5) + +inst_472: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1cd and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1cd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x35cd; op2val:0xb5cd; + valaddr_reg:x2; val_offset:884*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 884*FLEN/8, x6, x4, x5) + +inst_473: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1cd and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1cd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x35cd; op2val:0xb5cd; + valaddr_reg:x2; val_offset:886*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 886*FLEN/8, x6, x4, x5) + +inst_474: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1cd and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1cd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x35cd; op2val:0xb5cd; + valaddr_reg:x2; val_offset:888*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 888*FLEN/8, x6, x4, x5) + +inst_475: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3f9 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ff9; op2val:0xaff8; + valaddr_reg:x2; val_offset:890*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 890*FLEN/8, x6, x4, x5) + +inst_476: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3f9 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x3f8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ff9; op2val:0xaff8; + valaddr_reg:x2; val_offset:892*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 892*FLEN/8, x6, x4, x5) + +inst_477: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3f9 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x3f8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ff9; op2val:0xaff8; + valaddr_reg:x2; val_offset:894*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 894*FLEN/8, x6, x4, x5) + +inst_478: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3f9 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x3f8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ff9; op2val:0xaff8; + valaddr_reg:x2; val_offset:896*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 896*FLEN/8, x6, x4, x5) + +inst_479: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3f9 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x3f8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ff9; op2val:0xaff8; + valaddr_reg:x2; val_offset:898*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 898*FLEN/8, x6, x4, x5) + +inst_480: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0c5 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0c5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x34c5; op2val:0xb4c5; + valaddr_reg:x2; val_offset:900*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 900*FLEN/8, x6, x4, x5) + +inst_481: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0c5 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0c5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x34c5; op2val:0xb4c5; + valaddr_reg:x2; val_offset:902*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 902*FLEN/8, x6, x4, x5) + +inst_482: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0c5 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0c5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x34c5; op2val:0xb4c5; + valaddr_reg:x2; val_offset:904*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 904*FLEN/8, x6, x4, x5) + +inst_483: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0c5 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0c5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x34c5; op2val:0xb4c5; + valaddr_reg:x2; val_offset:906*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 906*FLEN/8, x6, x4, x5) + +inst_484: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0c5 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0c5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x34c5; op2val:0xb4c5; + valaddr_reg:x2; val_offset:908*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 908*FLEN/8, x6, x4, x5) + +inst_485: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x167 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x167 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3567; op2val:0xb567; + valaddr_reg:x2; val_offset:910*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 910*FLEN/8, x6, x4, x5) + +inst_486: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x167 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x167 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3567; op2val:0xb567; + valaddr_reg:x2; val_offset:912*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 912*FLEN/8, x6, x4, x5) + +inst_487: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x167 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x167 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3567; op2val:0xb567; + valaddr_reg:x2; val_offset:914*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 914*FLEN/8, x6, x4, x5) + +inst_488: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x167 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x167 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3567; op2val:0xb567; + valaddr_reg:x2; val_offset:916*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 916*FLEN/8, x6, x4, x5) + +inst_489: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x167 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x167 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3567; op2val:0xb567; + valaddr_reg:x2; val_offset:918*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 918*FLEN/8, x6, x4, x5) + +inst_490: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x06f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x06f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x386f; op2val:0xb86f; + valaddr_reg:x2; val_offset:920*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 920*FLEN/8, x6, x4, x5) + +inst_491: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x06f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x06f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x386f; op2val:0xb86f; + valaddr_reg:x2; val_offset:922*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 922*FLEN/8, x6, x4, x5) + +inst_492: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x06f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x06f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x386f; op2val:0xb86f; + valaddr_reg:x2; val_offset:924*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 924*FLEN/8, x6, x4, x5) + +inst_493: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x06f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x06f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x386f; op2val:0xb86f; + valaddr_reg:x2; val_offset:926*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 926*FLEN/8, x6, x4, x5) + +inst_494: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x06f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x06f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x386f; op2val:0xb86f; + valaddr_reg:x2; val_offset:928*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 928*FLEN/8, x6, x4, x5) + +inst_495: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2bd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2bc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3abd; op2val:0xbabc; + valaddr_reg:x2; val_offset:930*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 930*FLEN/8, x6, x4, x5) + +inst_496: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2bd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2bc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3abd; op2val:0xbabc; + valaddr_reg:x2; val_offset:932*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 932*FLEN/8, x6, x4, x5) + +inst_497: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2bd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2bc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3abd; op2val:0xbabc; + valaddr_reg:x2; val_offset:934*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 934*FLEN/8, x6, x4, x5) + +inst_498: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2bd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2bc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3abd; op2val:0xbabc; + valaddr_reg:x2; val_offset:936*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 936*FLEN/8, x6, x4, x5) + +inst_499: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2bd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2bc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3abd; op2val:0xbabc; + valaddr_reg:x2; val_offset:938*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 938*FLEN/8, x6, x4, x5) + +inst_500: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x01a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x01a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x381a; op2val:0xb81a; + valaddr_reg:x2; val_offset:940*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 940*FLEN/8, x6, x4, x5) + +inst_501: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x01a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x01a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x381a; op2val:0xb81a; + valaddr_reg:x2; val_offset:942*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 942*FLEN/8, x6, x4, x5) + +inst_502: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x01a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x01a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x381a; op2val:0xb81a; + valaddr_reg:x2; val_offset:944*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 944*FLEN/8, x6, x4, x5) + +inst_503: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x01a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x01a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x381a; op2val:0xb81a; + valaddr_reg:x2; val_offset:946*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 946*FLEN/8, x6, x4, x5) + +inst_504: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x01a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x01a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x381a; op2val:0xb81a; + valaddr_reg:x2; val_offset:948*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 948*FLEN/8, x6, x4, x5) + +inst_505: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3d3 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3d2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x33d3; op2val:0xb3d2; + valaddr_reg:x2; val_offset:950*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 950*FLEN/8, x6, x4, x5) + +inst_506: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3d3 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3d2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x33d3; op2val:0xb3d2; + valaddr_reg:x2; val_offset:952*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 952*FLEN/8, x6, x4, x5) + +inst_507: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3d3 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3d2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x33d3; op2val:0xb3d2; + valaddr_reg:x2; val_offset:954*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 954*FLEN/8, x6, x4, x5) + +inst_508: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3d3 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3d2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x33d3; op2val:0xb3d2; + valaddr_reg:x2; val_offset:956*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 956*FLEN/8, x6, x4, x5) + +inst_509: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3d3 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3d2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x33d3; op2val:0xb3d2; + valaddr_reg:x2; val_offset:958*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 958*FLEN/8, x6, x4, x5) + +inst_510: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x00b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x00b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x380b; op2val:0xb80b; + valaddr_reg:x2; val_offset:960*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 960*FLEN/8, x6, x4, x5) + +inst_511: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x00b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x00b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x380b; op2val:0xb80b; + valaddr_reg:x2; val_offset:962*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 962*FLEN/8, x6, x4, x5) + +inst_512: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x00b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x00b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x380b; op2val:0xb80b; + valaddr_reg:x2; val_offset:964*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 964*FLEN/8, x6, x4, x5) + +inst_513: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x00b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x00b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x380b; op2val:0xb80b; + valaddr_reg:x2; val_offset:966*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 966*FLEN/8, x6, x4, x5) + +inst_514: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x00b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x00b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x380b; op2val:0xb80b; + valaddr_reg:x2; val_offset:968*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 968*FLEN/8, x6, x4, x5) + +inst_515: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x043 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x043 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3843; op2val:0xb843; + valaddr_reg:x2; val_offset:970*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 970*FLEN/8, x6, x4, x5) + +inst_516: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x043 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x043 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3843; op2val:0xb843; + valaddr_reg:x2; val_offset:972*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 972*FLEN/8, x6, x4, x5) + +inst_517: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x043 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x043 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3843; op2val:0xb843; + valaddr_reg:x2; val_offset:974*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 974*FLEN/8, x6, x4, x5) + +inst_518: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x043 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x043 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3843; op2val:0xb843; + valaddr_reg:x2; val_offset:976*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 976*FLEN/8, x6, x4, x5) + +inst_519: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x043 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x043 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3843; op2val:0xb843; + valaddr_reg:x2; val_offset:978*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 978*FLEN/8, x6, x4, x5) + +inst_520: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3000; op2val:0xafff; + valaddr_reg:x2; val_offset:980*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 980*FLEN/8, x6, x4, x5) + +inst_521: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3000; op2val:0xafff; + valaddr_reg:x2; val_offset:982*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 982*FLEN/8, x6, x4, x5) + +inst_522: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3000; op2val:0xafff; + valaddr_reg:x2; val_offset:984*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 984*FLEN/8, x6, x4, x5) + +inst_523: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3000; op2val:0xafff; + valaddr_reg:x2; val_offset:986*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 986*FLEN/8, x6, x4, x5) + +inst_524: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3000; op2val:0xafff; + valaddr_reg:x2; val_offset:988*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 988*FLEN/8, x6, x4, x5) + +inst_525: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x27e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x27e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a7e; op2val:0xba7e; + valaddr_reg:x2; val_offset:990*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 990*FLEN/8, x6, x4, x5) + +inst_526: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x27e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x27e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a7e; op2val:0xba7e; + valaddr_reg:x2; val_offset:992*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 992*FLEN/8, x6, x4, x5) + +inst_527: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x27e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x27e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a7e; op2val:0xba7e; + valaddr_reg:x2; val_offset:994*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 994*FLEN/8, x6, x4, x5) + +inst_528: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x27e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x27e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a7e; op2val:0xba7e; + valaddr_reg:x2; val_offset:996*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 996*FLEN/8, x6, x4, x5) + +inst_529: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x27e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x27e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a7e; op2val:0xba7e; + valaddr_reg:x2; val_offset:998*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 998*FLEN/8, x6, x4, x5) + +inst_530: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1de and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1de and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x35de; op2val:0xb5de; + valaddr_reg:x2; val_offset:1000*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1000*FLEN/8, x6, x4, x5) + +inst_531: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1de and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1de and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x35de; op2val:0xb5de; + valaddr_reg:x2; val_offset:1002*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1002*FLEN/8, x6, x4, x5) + +inst_532: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1de and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1de and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x35de; op2val:0xb5de; + valaddr_reg:x2; val_offset:1004*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1004*FLEN/8, x6, x4, x5) + +inst_533: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1de and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1de and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x35de; op2val:0xb5de; + valaddr_reg:x2; val_offset:1006*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1006*FLEN/8, x6, x4, x5) + +inst_534: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1de and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1de and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x35de; op2val:0xb5de; + valaddr_reg:x2; val_offset:1008*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1008*FLEN/8, x6, x4, x5) + +inst_535: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x064 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x064 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3464; op2val:0xb464; + valaddr_reg:x2; val_offset:1010*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1010*FLEN/8, x6, x4, x5) + +inst_536: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x064 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x064 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3464; op2val:0xb464; + valaddr_reg:x2; val_offset:1012*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1012*FLEN/8, x6, x4, x5) + +inst_537: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x064 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x064 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3464; op2val:0xb464; + valaddr_reg:x2; val_offset:1014*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1014*FLEN/8, x6, x4, x5) +RVTEST_SIGBASE(x4,signature_x4_4) + +inst_538: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x064 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x064 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3464; op2val:0xb464; + valaddr_reg:x2; val_offset:1016*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1016*FLEN/8, x6, x4, x5) + +inst_539: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x064 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x064 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3464; op2val:0xb464; + valaddr_reg:x2; val_offset:1018*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1018*FLEN/8, x6, x4, x5) + +inst_540: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0c9 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0c9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x38c9; op2val:0xb8c9; + valaddr_reg:x2; val_offset:1020*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1020*FLEN/8, x6, x4, x5) + +inst_541: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0c9 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0c9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x38c9; op2val:0xb8c9; + valaddr_reg:x2; val_offset:1022*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1022*FLEN/8, x6, x4, x5) + +inst_542: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0c9 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0c9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x38c9; op2val:0xb8c9; + valaddr_reg:x2; val_offset:1024*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1024*FLEN/8, x6, x4, x5) + +inst_543: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0c9 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0c9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x38c9; op2val:0xb8c9; + valaddr_reg:x2; val_offset:1026*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1026*FLEN/8, x6, x4, x5) + +inst_544: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0c9 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0c9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x38c9; op2val:0xb8c9; + valaddr_reg:x2; val_offset:1028*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1028*FLEN/8, x6, x4, x5) + +inst_545: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x178 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x178 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3978; op2val:0xb978; + valaddr_reg:x2; val_offset:1030*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1030*FLEN/8, x6, x4, x5) + +inst_546: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x178 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x178 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3978; op2val:0xb978; + valaddr_reg:x2; val_offset:1032*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1032*FLEN/8, x6, x4, x5) + +inst_547: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x178 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x178 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3978; op2val:0xb978; + valaddr_reg:x2; val_offset:1034*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1034*FLEN/8, x6, x4, x5) + +inst_548: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x178 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x178 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3978; op2val:0xb978; + valaddr_reg:x2; val_offset:1036*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1036*FLEN/8, x6, x4, x5) + +inst_549: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x178 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x178 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3978; op2val:0xb978; + valaddr_reg:x2; val_offset:1038*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1038*FLEN/8, x6, x4, x5) + +inst_550: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x085 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x085 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3485; op2val:0xb485; + valaddr_reg:x2; val_offset:1040*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1040*FLEN/8, x6, x4, x5) + +inst_551: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x085 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x085 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3485; op2val:0xb485; + valaddr_reg:x2; val_offset:1042*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1042*FLEN/8, x6, x4, x5) + +inst_552: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x085 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x085 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3485; op2val:0xb485; + valaddr_reg:x2; val_offset:1044*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1044*FLEN/8, x6, x4, x5) + +inst_553: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x085 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x085 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3485; op2val:0xb485; + valaddr_reg:x2; val_offset:1046*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1046*FLEN/8, x6, x4, x5) + +inst_554: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x085 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x085 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3485; op2val:0xb485; + valaddr_reg:x2; val_offset:1048*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1048*FLEN/8, x6, x4, x5) + +inst_555: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1ac and fs2 == 1 and fe2 == 0x0c and fm2 == 0x1ac and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x31ac; op2val:0xb1ac; + valaddr_reg:x2; val_offset:1050*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1050*FLEN/8, x6, x4, x5) + +inst_556: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1ac and fs2 == 1 and fe2 == 0x0c and fm2 == 0x1ac and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x31ac; op2val:0xb1ac; + valaddr_reg:x2; val_offset:1052*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1052*FLEN/8, x6, x4, x5) + +inst_557: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1ac and fs2 == 1 and fe2 == 0x0c and fm2 == 0x1ac and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x31ac; op2val:0xb1ac; + valaddr_reg:x2; val_offset:1054*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1054*FLEN/8, x6, x4, x5) + +inst_558: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1ac and fs2 == 1 and fe2 == 0x0c and fm2 == 0x1ac and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x31ac; op2val:0xb1ac; + valaddr_reg:x2; val_offset:1056*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1056*FLEN/8, x6, x4, x5) + +inst_559: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1ac and fs2 == 1 and fe2 == 0x0c and fm2 == 0x1ac and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x31ac; op2val:0xb1ac; + valaddr_reg:x2; val_offset:1058*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1058*FLEN/8, x6, x4, x5) + +inst_560: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x337 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x337 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b37; op2val:0xbb37; + valaddr_reg:x2; val_offset:1060*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1060*FLEN/8, x6, x4, x5) + +inst_561: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x337 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x337 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b37; op2val:0xbb37; + valaddr_reg:x2; val_offset:1062*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1062*FLEN/8, x6, x4, x5) + +inst_562: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x337 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x337 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b37; op2val:0xbb37; + valaddr_reg:x2; val_offset:1064*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1064*FLEN/8, x6, x4, x5) + +inst_563: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x337 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x337 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b37; op2val:0xbb37; + valaddr_reg:x2; val_offset:1066*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1066*FLEN/8, x6, x4, x5) + +inst_564: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x337 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x337 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b37; op2val:0xbb37; + valaddr_reg:x2; val_offset:1068*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1068*FLEN/8, x6, x4, x5) + +inst_565: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x19c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x19c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x359c; op2val:0xb59c; + valaddr_reg:x2; val_offset:1070*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1070*FLEN/8, x6, x4, x5) + +inst_566: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x19c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x19c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x359c; op2val:0xb59c; + valaddr_reg:x2; val_offset:1072*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1072*FLEN/8, x6, x4, x5) + +inst_567: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x19c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x19c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x359c; op2val:0xb59c; + valaddr_reg:x2; val_offset:1074*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1074*FLEN/8, x6, x4, x5) + +inst_568: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x19c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x19c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x359c; op2val:0xb59c; + valaddr_reg:x2; val_offset:1076*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1076*FLEN/8, x6, x4, x5) + +inst_569: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x19c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x19c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x359c; op2val:0xb59c; + valaddr_reg:x2; val_offset:1078*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1078*FLEN/8, x6, x4, x5) + +inst_570: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1c2 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1c2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x39c2; op2val:0xb9c2; + valaddr_reg:x2; val_offset:1080*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1080*FLEN/8, x6, x4, x5) + +inst_571: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1c2 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1c2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x39c2; op2val:0xb9c2; + valaddr_reg:x2; val_offset:1082*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1082*FLEN/8, x6, x4, x5) + +inst_572: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1c2 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1c2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x39c2; op2val:0xb9c2; + valaddr_reg:x2; val_offset:1084*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1084*FLEN/8, x6, x4, x5) + +inst_573: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1c2 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1c2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x39c2; op2val:0xb9c2; + valaddr_reg:x2; val_offset:1086*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1086*FLEN/8, x6, x4, x5) + +inst_574: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1c2 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1c2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x39c2; op2val:0xb9c2; + valaddr_reg:x2; val_offset:1088*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1088*FLEN/8, x6, x4, x5) + +inst_575: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x332 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x332 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b32; op2val:0xbb32; + valaddr_reg:x2; val_offset:1090*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1090*FLEN/8, x6, x4, x5) + +inst_576: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x332 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x332 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b32; op2val:0xbb32; + valaddr_reg:x2; val_offset:1092*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1092*FLEN/8, x6, x4, x5) + +inst_577: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x332 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x332 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b32; op2val:0xbb32; + valaddr_reg:x2; val_offset:1094*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1094*FLEN/8, x6, x4, x5) + +inst_578: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x332 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x332 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b32; op2val:0xbb32; + valaddr_reg:x2; val_offset:1096*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1096*FLEN/8, x6, x4, x5) + +inst_579: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x332 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x332 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b32; op2val:0xbb32; + valaddr_reg:x2; val_offset:1098*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1098*FLEN/8, x6, x4, x5) + +inst_580: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0d3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x38d3; op2val:0xb8d3; + valaddr_reg:x2; val_offset:1100*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1100*FLEN/8, x6, x4, x5) + +inst_581: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0d3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x38d3; op2val:0xb8d3; + valaddr_reg:x2; val_offset:1102*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1102*FLEN/8, x6, x4, x5) + +inst_582: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0d3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x38d3; op2val:0xb8d3; + valaddr_reg:x2; val_offset:1104*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1104*FLEN/8, x6, x4, x5) + +inst_583: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0d3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x38d3; op2val:0xb8d3; + valaddr_reg:x2; val_offset:1106*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1106*FLEN/8, x6, x4, x5) + +inst_584: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0d3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x38d3; op2val:0xb8d3; + valaddr_reg:x2; val_offset:1108*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1108*FLEN/8, x6, x4, x5) + +inst_585: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1cd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1cd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x39cd; op2val:0xb9cd; + valaddr_reg:x2; val_offset:1110*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1110*FLEN/8, x6, x4, x5) + +inst_586: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1cd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1cd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x39cd; op2val:0xb9cd; + valaddr_reg:x2; val_offset:1112*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1112*FLEN/8, x6, x4, x5) + +inst_587: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1cd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1cd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x39cd; op2val:0xb9cd; + valaddr_reg:x2; val_offset:1114*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1114*FLEN/8, x6, x4, x5) + +inst_588: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1cd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1cd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x39cd; op2val:0xb9cd; + valaddr_reg:x2; val_offset:1116*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1116*FLEN/8, x6, x4, x5) + +inst_589: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1cd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1cd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x39cd; op2val:0xb9cd; + valaddr_reg:x2; val_offset:1118*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1118*FLEN/8, x6, x4, x5) + +inst_590: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2a5 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2a5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x32a5; op2val:0xb2a5; + valaddr_reg:x2; val_offset:1120*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1120*FLEN/8, x6, x4, x5) + +inst_591: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2a5 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2a5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x32a5; op2val:0xb2a5; + valaddr_reg:x2; val_offset:1122*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1122*FLEN/8, x6, x4, x5) + +inst_592: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2a5 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2a5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x32a5; op2val:0xb2a5; + valaddr_reg:x2; val_offset:1124*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1124*FLEN/8, x6, x4, x5) + +inst_593: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2a5 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2a5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x32a5; op2val:0xb2a5; + valaddr_reg:x2; val_offset:1126*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1126*FLEN/8, x6, x4, x5) + +inst_594: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2a5 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2a5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x32a5; op2val:0xb2a5; + valaddr_reg:x2; val_offset:1128*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1128*FLEN/8, x6, x4, x5) + +inst_595: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ee and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2ee and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aee; op2val:0xbaee; + valaddr_reg:x2; val_offset:1130*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1130*FLEN/8, x6, x4, x5) + +inst_596: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ee and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2ee and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aee; op2val:0xbaee; + valaddr_reg:x2; val_offset:1132*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1132*FLEN/8, x6, x4, x5) + +inst_597: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ee and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2ee and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aee; op2val:0xbaee; + valaddr_reg:x2; val_offset:1134*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1134*FLEN/8, x6, x4, x5) + +inst_598: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ee and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2ee and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aee; op2val:0xbaee; + valaddr_reg:x2; val_offset:1136*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1136*FLEN/8, x6, x4, x5) + +inst_599: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ee and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2ee and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aee; op2val:0xbaee; + valaddr_reg:x2; val_offset:1138*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1138*FLEN/8, x6, x4, x5) + +inst_600: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x196 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x196 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3596; op2val:0xb596; + valaddr_reg:x2; val_offset:1140*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1140*FLEN/8, x6, x4, x5) + +inst_601: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x196 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x196 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3596; op2val:0xb596; + valaddr_reg:x2; val_offset:1142*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1142*FLEN/8, x6, x4, x5) + +inst_602: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x196 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x196 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3596; op2val:0xb596; + valaddr_reg:x2; val_offset:1144*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1144*FLEN/8, x6, x4, x5) + +inst_603: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x196 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x196 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3596; op2val:0xb596; + valaddr_reg:x2; val_offset:1146*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1146*FLEN/8, x6, x4, x5) + +inst_604: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x196 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x196 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3596; op2val:0xb596; + valaddr_reg:x2; val_offset:1148*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1148*FLEN/8, x6, x4, x5) + +inst_605: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x019 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x019 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3019; op2val:0xb019; + valaddr_reg:x2; val_offset:1150*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1150*FLEN/8, x6, x4, x5) + +inst_606: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x019 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x019 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3019; op2val:0xb019; + valaddr_reg:x2; val_offset:1152*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1152*FLEN/8, x6, x4, x5) + +inst_607: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x019 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x019 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3019; op2val:0xb019; + valaddr_reg:x2; val_offset:1154*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1154*FLEN/8, x6, x4, x5) + +inst_608: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x019 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x019 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3019; op2val:0xb019; + valaddr_reg:x2; val_offset:1156*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1156*FLEN/8, x6, x4, x5) + +inst_609: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x019 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x019 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3019; op2val:0xb019; + valaddr_reg:x2; val_offset:1158*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1158*FLEN/8, x6, x4, x5) + +inst_610: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d9 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3d9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bd9; op2val:0xbbd9; + valaddr_reg:x2; val_offset:1160*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1160*FLEN/8, x6, x4, x5) + +inst_611: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d9 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3d9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bd9; op2val:0xbbd9; + valaddr_reg:x2; val_offset:1162*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1162*FLEN/8, x6, x4, x5) + +inst_612: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d9 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3d9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bd9; op2val:0xbbd9; + valaddr_reg:x2; val_offset:1164*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1164*FLEN/8, x6, x4, x5) + +inst_613: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d9 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3d9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bd9; op2val:0xbbd9; + valaddr_reg:x2; val_offset:1166*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1166*FLEN/8, x6, x4, x5) + +inst_614: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d9 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3d9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bd9; op2val:0xbbd9; + valaddr_reg:x2; val_offset:1168*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1168*FLEN/8, x6, x4, x5) + +inst_615: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x11a and fs2 == 1 and fe2 == 0x0d and fm2 == 0x11a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x351a; op2val:0xb51a; + valaddr_reg:x2; val_offset:1170*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1170*FLEN/8, x6, x4, x5) + +inst_616: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x11a and fs2 == 1 and fe2 == 0x0d and fm2 == 0x11a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x351a; op2val:0xb51a; + valaddr_reg:x2; val_offset:1172*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1172*FLEN/8, x6, x4, x5) + +inst_617: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x11a and fs2 == 1 and fe2 == 0x0d and fm2 == 0x11a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x351a; op2val:0xb51a; + valaddr_reg:x2; val_offset:1174*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1174*FLEN/8, x6, x4, x5) + +inst_618: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x11a and fs2 == 1 and fe2 == 0x0d and fm2 == 0x11a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x351a; op2val:0xb51a; + valaddr_reg:x2; val_offset:1176*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1176*FLEN/8, x6, x4, x5) + +inst_619: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x11a and fs2 == 1 and fe2 == 0x0d and fm2 == 0x11a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x351a; op2val:0xb51a; + valaddr_reg:x2; val_offset:1178*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1178*FLEN/8, x6, x4, x5) + +inst_620: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2da and fs2 == 1 and fe2 == 0x0a and fm2 == 0x2d8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ada; op2val:0xaad8; + valaddr_reg:x2; val_offset:1180*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1180*FLEN/8, x6, x4, x5) + +inst_621: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2da and fs2 == 1 and fe2 == 0x0a and fm2 == 0x2d8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ada; op2val:0xaad8; + valaddr_reg:x2; val_offset:1182*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1182*FLEN/8, x6, x4, x5) + +inst_622: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2da and fs2 == 1 and fe2 == 0x0a and fm2 == 0x2d8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ada; op2val:0xaad8; + valaddr_reg:x2; val_offset:1184*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1184*FLEN/8, x6, x4, x5) + +inst_623: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2da and fs2 == 1 and fe2 == 0x0a and fm2 == 0x2d8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ada; op2val:0xaad8; + valaddr_reg:x2; val_offset:1186*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1186*FLEN/8, x6, x4, x5) + +inst_624: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2da and fs2 == 1 and fe2 == 0x0a and fm2 == 0x2d8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ada; op2val:0xaad8; + valaddr_reg:x2; val_offset:1188*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1188*FLEN/8, x6, x4, x5) + +inst_625: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1c5 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1c4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2dc5; op2val:0xadc4; + valaddr_reg:x2; val_offset:1190*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1190*FLEN/8, x6, x4, x5) + +inst_626: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1c5 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1c4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2dc5; op2val:0xadc4; + valaddr_reg:x2; val_offset:1192*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1192*FLEN/8, x6, x4, x5) + +inst_627: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1c5 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1c4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2dc5; op2val:0xadc4; + valaddr_reg:x2; val_offset:1194*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1194*FLEN/8, x6, x4, x5) + +inst_628: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1c5 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1c4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2dc5; op2val:0xadc4; + valaddr_reg:x2; val_offset:1196*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1196*FLEN/8, x6, x4, x5) + +inst_629: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1c5 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1c4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2dc5; op2val:0xadc4; + valaddr_reg:x2; val_offset:1198*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1198*FLEN/8, x6, x4, x5) + +inst_630: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x003 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3403; op2val:0xb403; + valaddr_reg:x2; val_offset:1200*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1200*FLEN/8, x6, x4, x5) + +inst_631: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x003 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x003 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3403; op2val:0xb403; + valaddr_reg:x2; val_offset:1202*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1202*FLEN/8, x6, x4, x5) + +inst_632: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x003 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x003 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3403; op2val:0xb403; + valaddr_reg:x2; val_offset:1204*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1204*FLEN/8, x6, x4, x5) + +inst_633: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x003 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x003 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3403; op2val:0xb403; + valaddr_reg:x2; val_offset:1206*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1206*FLEN/8, x6, x4, x5) + +inst_634: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x003 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x003 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3403; op2val:0xb403; + valaddr_reg:x2; val_offset:1208*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1208*FLEN/8, x6, x4, x5) + +inst_635: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x183 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x183 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3583; op2val:0xb583; + valaddr_reg:x2; val_offset:1210*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1210*FLEN/8, x6, x4, x5) + +inst_636: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x183 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x183 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3583; op2val:0xb583; + valaddr_reg:x2; val_offset:1212*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1212*FLEN/8, x6, x4, x5) + +inst_637: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x183 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x183 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3583; op2val:0xb583; + valaddr_reg:x2; val_offset:1214*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1214*FLEN/8, x6, x4, x5) + +inst_638: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x183 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x183 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3583; op2val:0xb583; + valaddr_reg:x2; val_offset:1216*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1216*FLEN/8, x6, x4, x5) + +inst_639: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x183 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x183 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3583; op2val:0xb583; + valaddr_reg:x2; val_offset:1218*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1218*FLEN/8, x6, x4, x5) + +inst_640: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x23a and fs2 == 1 and fe2 == 0x0b and fm2 == 0x239 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e3a; op2val:0xae39; + valaddr_reg:x2; val_offset:1220*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1220*FLEN/8, x6, x4, x5) + +inst_641: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x23a and fs2 == 1 and fe2 == 0x0b and fm2 == 0x239 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e3a; op2val:0xae39; + valaddr_reg:x2; val_offset:1222*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1222*FLEN/8, x6, x4, x5) + +inst_642: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x23a and fs2 == 1 and fe2 == 0x0b and fm2 == 0x239 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e3a; op2val:0xae39; + valaddr_reg:x2; val_offset:1224*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1224*FLEN/8, x6, x4, x5) + +inst_643: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x23a and fs2 == 1 and fe2 == 0x0b and fm2 == 0x239 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e3a; op2val:0xae39; + valaddr_reg:x2; val_offset:1226*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1226*FLEN/8, x6, x4, x5) + +inst_644: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x23a and fs2 == 1 and fe2 == 0x0b and fm2 == 0x239 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e3a; op2val:0xae39; + valaddr_reg:x2; val_offset:1228*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1228*FLEN/8, x6, x4, x5) + +inst_645: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x105 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x105 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3905; op2val:0xb905; + valaddr_reg:x2; val_offset:1230*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1230*FLEN/8, x6, x4, x5) + +inst_646: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x105 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x105 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3905; op2val:0xb905; + valaddr_reg:x2; val_offset:1232*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1232*FLEN/8, x6, x4, x5) + +inst_647: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x105 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x105 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3905; op2val:0xb905; + valaddr_reg:x2; val_offset:1234*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1234*FLEN/8, x6, x4, x5) + +inst_648: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x105 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x105 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3905; op2val:0xb905; + valaddr_reg:x2; val_offset:1236*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1236*FLEN/8, x6, x4, x5) + +inst_649: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x105 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x105 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3905; op2val:0xb905; + valaddr_reg:x2; val_offset:1238*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1238*FLEN/8, x6, x4, x5) + +inst_650: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x256 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x256 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a56; op2val:0xba56; + valaddr_reg:x2; val_offset:1240*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1240*FLEN/8, x6, x4, x5) + +inst_651: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x256 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x256 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a56; op2val:0xba56; + valaddr_reg:x2; val_offset:1242*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1242*FLEN/8, x6, x4, x5) + +inst_652: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x256 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x256 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a56; op2val:0xba56; + valaddr_reg:x2; val_offset:1244*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1244*FLEN/8, x6, x4, x5) + +inst_653: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x256 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x256 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a56; op2val:0xba56; + valaddr_reg:x2; val_offset:1246*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1246*FLEN/8, x6, x4, x5) + +inst_654: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x256 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x256 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a56; op2val:0xba56; + valaddr_reg:x2; val_offset:1248*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1248*FLEN/8, x6, x4, x5) + +inst_655: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ed and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3ed and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bed; op2val:0xbbed; + valaddr_reg:x2; val_offset:1250*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1250*FLEN/8, x6, x4, x5) + +inst_656: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ed and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3ed and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bed; op2val:0xbbed; + valaddr_reg:x2; val_offset:1252*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1252*FLEN/8, x6, x4, x5) + +inst_657: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ed and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3ed and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bed; op2val:0xbbed; + valaddr_reg:x2; val_offset:1254*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1254*FLEN/8, x6, x4, x5) + +inst_658: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ed and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3ed and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bed; op2val:0xbbed; + valaddr_reg:x2; val_offset:1256*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1256*FLEN/8, x6, x4, x5) + +inst_659: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ed and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3ed and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bed; op2val:0xbbed; + valaddr_reg:x2; val_offset:1258*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1258*FLEN/8, x6, x4, x5) + +inst_660: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x155 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3955; op2val:0xb955; + valaddr_reg:x2; val_offset:1260*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1260*FLEN/8, x6, x4, x5) + +inst_661: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x155 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x155 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3955; op2val:0xb955; + valaddr_reg:x2; val_offset:1262*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1262*FLEN/8, x6, x4, x5) + +inst_662: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x155 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x155 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3955; op2val:0xb955; + valaddr_reg:x2; val_offset:1264*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1264*FLEN/8, x6, x4, x5) + +inst_663: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x155 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x155 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3955; op2val:0xb955; + valaddr_reg:x2; val_offset:1266*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1266*FLEN/8, x6, x4, x5) + +inst_664: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x155 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x155 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3955; op2val:0xb955; + valaddr_reg:x2; val_offset:1268*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1268*FLEN/8, x6, x4, x5) + +inst_665: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x081 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x080 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3481; op2val:0xb480; + valaddr_reg:x2; val_offset:1270*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1270*FLEN/8, x6, x4, x5) +RVTEST_SIGBASE(x4,signature_x4_5) + +inst_666: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x081 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x080 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3481; op2val:0xb480; + valaddr_reg:x2; val_offset:1272*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1272*FLEN/8, x6, x4, x5) + +inst_667: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x081 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x080 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3481; op2val:0xb480; + valaddr_reg:x2; val_offset:1274*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1274*FLEN/8, x6, x4, x5) + +inst_668: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x081 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x080 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3481; op2val:0xb480; + valaddr_reg:x2; val_offset:1276*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1276*FLEN/8, x6, x4, x5) + +inst_669: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x081 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x080 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3481; op2val:0xb480; + valaddr_reg:x2; val_offset:1278*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1278*FLEN/8, x6, x4, x5) + +inst_670: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x212 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x212 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3612; op2val:0xb612; + valaddr_reg:x2; val_offset:1280*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1280*FLEN/8, x6, x4, x5) + +inst_671: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x212 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x212 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3612; op2val:0xb612; + valaddr_reg:x2; val_offset:1282*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1282*FLEN/8, x6, x4, x5) + +inst_672: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x212 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x212 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3612; op2val:0xb612; + valaddr_reg:x2; val_offset:1284*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1284*FLEN/8, x6, x4, x5) + +inst_673: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x212 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x212 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3612; op2val:0xb612; + valaddr_reg:x2; val_offset:1286*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1286*FLEN/8, x6, x4, x5) + +inst_674: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x212 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x212 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3612; op2val:0xb612; + valaddr_reg:x2; val_offset:1288*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1288*FLEN/8, x6, x4, x5) + +inst_675: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b0 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2b0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ab0; op2val:0xbab0; + valaddr_reg:x2; val_offset:1290*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1290*FLEN/8, x6, x4, x5) + +inst_676: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b0 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2b0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ab0; op2val:0xbab0; + valaddr_reg:x2; val_offset:1292*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1292*FLEN/8, x6, x4, x5) + +inst_677: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b0 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2b0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ab0; op2val:0xbab0; + valaddr_reg:x2; val_offset:1294*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1294*FLEN/8, x6, x4, x5) + +inst_678: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b0 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2b0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ab0; op2val:0xbab0; + valaddr_reg:x2; val_offset:1296*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1296*FLEN/8, x6, x4, x5) + +inst_679: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b0 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2b0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ab0; op2val:0xbab0; + valaddr_reg:x2; val_offset:1298*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1298*FLEN/8, x6, x4, x5) + +inst_680: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1af and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1ae and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x39af; op2val:0xb9ae; + valaddr_reg:x2; val_offset:1300*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1300*FLEN/8, x6, x4, x5) + +inst_681: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1af and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1ae and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x39af; op2val:0xb9ae; + valaddr_reg:x2; val_offset:1302*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1302*FLEN/8, x6, x4, x5) + +inst_682: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1af and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1ae and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x39af; op2val:0xb9ae; + valaddr_reg:x2; val_offset:1304*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1304*FLEN/8, x6, x4, x5) + +inst_683: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1af and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1ae and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x39af; op2val:0xb9ae; + valaddr_reg:x2; val_offset:1306*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1306*FLEN/8, x6, x4, x5) + +inst_684: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1af and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1ae and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x39af; op2val:0xb9ae; + valaddr_reg:x2; val_offset:1308*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1308*FLEN/8, x6, x4, x5) + +inst_685: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x339 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x339 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3739; op2val:0xb739; + valaddr_reg:x2; val_offset:1310*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1310*FLEN/8, x6, x4, x5) + +inst_686: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x339 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x339 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3739; op2val:0xb739; + valaddr_reg:x2; val_offset:1312*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1312*FLEN/8, x6, x4, x5) + +inst_687: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x339 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x339 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3739; op2val:0xb739; + valaddr_reg:x2; val_offset:1314*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1314*FLEN/8, x6, x4, x5) + +inst_688: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x339 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x339 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3739; op2val:0xb739; + valaddr_reg:x2; val_offset:1316*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1316*FLEN/8, x6, x4, x5) + +inst_689: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x339 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x339 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3739; op2val:0xb739; + valaddr_reg:x2; val_offset:1318*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1318*FLEN/8, x6, x4, x5) + +inst_690: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x02c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x382c; op2val:0xb82c; + valaddr_reg:x2; val_offset:1320*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1320*FLEN/8, x6, x4, x5) + +inst_691: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x02c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x382c; op2val:0xb82c; + valaddr_reg:x2; val_offset:1322*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1322*FLEN/8, x6, x4, x5) + +inst_692: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x02c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x382c; op2val:0xb82c; + valaddr_reg:x2; val_offset:1324*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1324*FLEN/8, x6, x4, x5) + +inst_693: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x02c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x382c; op2val:0xb82c; + valaddr_reg:x2; val_offset:1326*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1326*FLEN/8, x6, x4, x5) + +inst_694: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x02c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x382c; op2val:0xb82c; + valaddr_reg:x2; val_offset:1328*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1328*FLEN/8, x6, x4, x5) + +inst_695: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x39d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x39d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b9d; op2val:0xbb9d; + valaddr_reg:x2; val_offset:1330*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1330*FLEN/8, x6, x4, x5) + +inst_696: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x39d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x39d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b9d; op2val:0xbb9d; + valaddr_reg:x2; val_offset:1332*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1332*FLEN/8, x6, x4, x5) + +inst_697: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x39d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x39d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b9d; op2val:0xbb9d; + valaddr_reg:x2; val_offset:1334*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1334*FLEN/8, x6, x4, x5) + +inst_698: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x39d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x39d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b9d; op2val:0xbb9d; + valaddr_reg:x2; val_offset:1336*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1336*FLEN/8, x6, x4, x5) + +inst_699: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x39d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x39d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b9d; op2val:0xbb9d; + valaddr_reg:x2; val_offset:1338*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1338*FLEN/8, x6, x4, x5) + +inst_700: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3a1 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3a1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x37a1; op2val:0xb7a1; + valaddr_reg:x2; val_offset:1340*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1340*FLEN/8, x6, x4, x5) + +inst_701: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3a1 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3a1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x37a1; op2val:0xb7a1; + valaddr_reg:x2; val_offset:1342*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1342*FLEN/8, x6, x4, x5) + +inst_702: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3a1 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3a1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x37a1; op2val:0xb7a1; + valaddr_reg:x2; val_offset:1344*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1344*FLEN/8, x6, x4, x5) + +inst_703: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3a1 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3a1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x37a1; op2val:0xb7a1; + valaddr_reg:x2; val_offset:1346*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1346*FLEN/8, x6, x4, x5) + +inst_704: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3a1 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3a1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x37a1; op2val:0xb7a1; + valaddr_reg:x2; val_offset:1348*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1348*FLEN/8, x6, x4, x5) + +inst_705: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0c6 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0c6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x38c6; op2val:0xb8c6; + valaddr_reg:x2; val_offset:1350*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1350*FLEN/8, x6, x4, x5) + +inst_706: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0c6 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0c6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x38c6; op2val:0xb8c6; + valaddr_reg:x2; val_offset:1352*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1352*FLEN/8, x6, x4, x5) + +inst_707: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0c6 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0c6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x38c6; op2val:0xb8c6; + valaddr_reg:x2; val_offset:1354*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1354*FLEN/8, x6, x4, x5) + +inst_708: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0c6 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0c6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x38c6; op2val:0xb8c6; + valaddr_reg:x2; val_offset:1356*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1356*FLEN/8, x6, x4, x5) + +inst_709: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0c6 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0c6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x38c6; op2val:0xb8c6; + valaddr_reg:x2; val_offset:1358*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1358*FLEN/8, x6, x4, x5) + +inst_710: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ae and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0ae and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x38ae; op2val:0xb8ae; + valaddr_reg:x2; val_offset:1360*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1360*FLEN/8, x6, x4, x5) + +inst_711: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ae and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0ae and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x38ae; op2val:0xb8ae; + valaddr_reg:x2; val_offset:1362*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1362*FLEN/8, x6, x4, x5) + +inst_712: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ae and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0ae and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x38ae; op2val:0xb8ae; + valaddr_reg:x2; val_offset:1364*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1364*FLEN/8, x6, x4, x5) + +inst_713: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ae and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0ae and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x38ae; op2val:0xb8ae; + valaddr_reg:x2; val_offset:1366*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1366*FLEN/8, x6, x4, x5) + +inst_714: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ae and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0ae and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x38ae; op2val:0xb8ae; + valaddr_reg:x2; val_offset:1368*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1368*FLEN/8, x6, x4, x5) + +inst_715: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1d9 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1d8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2dd9; op2val:0xadd8; + valaddr_reg:x2; val_offset:1370*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1370*FLEN/8, x6, x4, x5) + +inst_716: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1d9 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1d8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2dd9; op2val:0xadd8; + valaddr_reg:x2; val_offset:1372*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1372*FLEN/8, x6, x4, x5) + +inst_717: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1d9 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1d8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2dd9; op2val:0xadd8; + valaddr_reg:x2; val_offset:1374*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1374*FLEN/8, x6, x4, x5) + +inst_718: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1d9 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1d8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2dd9; op2val:0xadd8; + valaddr_reg:x2; val_offset:1376*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1376*FLEN/8, x6, x4, x5) + +inst_719: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1d9 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1d8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2dd9; op2val:0xadd8; + valaddr_reg:x2; val_offset:1378*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1378*FLEN/8, x6, x4, x5) + +inst_720: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x118 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x117 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3118; op2val:0xb117; + valaddr_reg:x2; val_offset:1380*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1380*FLEN/8, x6, x4, x5) + +inst_721: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x118 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x117 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3118; op2val:0xb117; + valaddr_reg:x2; val_offset:1382*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1382*FLEN/8, x6, x4, x5) + +inst_722: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x118 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x117 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3118; op2val:0xb117; + valaddr_reg:x2; val_offset:1384*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1384*FLEN/8, x6, x4, x5) + +inst_723: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x118 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x117 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3118; op2val:0xb117; + valaddr_reg:x2; val_offset:1386*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1386*FLEN/8, x6, x4, x5) + +inst_724: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x118 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x117 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3118; op2val:0xb117; + valaddr_reg:x2; val_offset:1388*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1388*FLEN/8, x6, x4, x5) + +inst_725: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x140 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x140 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3940; op2val:0xb940; + valaddr_reg:x2; val_offset:1390*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1390*FLEN/8, x6, x4, x5) + +inst_726: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x140 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x140 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3940; op2val:0xb940; + valaddr_reg:x2; val_offset:1392*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1392*FLEN/8, x6, x4, x5) + +inst_727: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x140 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x140 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3940; op2val:0xb940; + valaddr_reg:x2; val_offset:1394*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1394*FLEN/8, x6, x4, x5) + +inst_728: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x140 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x140 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3940; op2val:0xb940; + valaddr_reg:x2; val_offset:1396*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1396*FLEN/8, x6, x4, x5) + +inst_729: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x140 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x140 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3940; op2val:0xb940; + valaddr_reg:x2; val_offset:1398*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1398*FLEN/8, x6, x4, x5) + +inst_730: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ce and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0ce and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x34ce; op2val:0xb4ce; + valaddr_reg:x2; val_offset:1400*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1400*FLEN/8, x6, x4, x5) + +inst_731: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ce and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0ce and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x34ce; op2val:0xb4ce; + valaddr_reg:x2; val_offset:1402*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1402*FLEN/8, x6, x4, x5) + +inst_732: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ce and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0ce and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x34ce; op2val:0xb4ce; + valaddr_reg:x2; val_offset:1404*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1404*FLEN/8, x6, x4, x5) + +inst_733: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ce and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0ce and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x34ce; op2val:0xb4ce; + valaddr_reg:x2; val_offset:1406*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1406*FLEN/8, x6, x4, x5) + +inst_734: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ce and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0ce and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x34ce; op2val:0xb4ce; + valaddr_reg:x2; val_offset:1408*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1408*FLEN/8, x6, x4, x5) + +inst_735: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x195 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x195 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3995; op2val:0xb995; + valaddr_reg:x2; val_offset:1410*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1410*FLEN/8, x6, x4, x5) + +inst_736: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x195 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x195 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3995; op2val:0xb995; + valaddr_reg:x2; val_offset:1412*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1412*FLEN/8, x6, x4, x5) + +inst_737: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x195 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x195 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3995; op2val:0xb995; + valaddr_reg:x2; val_offset:1414*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1414*FLEN/8, x6, x4, x5) + +inst_738: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x195 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x195 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3995; op2val:0xb995; + valaddr_reg:x2; val_offset:1416*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1416*FLEN/8, x6, x4, x5) + +inst_739: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x195 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x195 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3995; op2val:0xb995; + valaddr_reg:x2; val_offset:1418*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1418*FLEN/8, x6, x4, x5) + +inst_740: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2c3 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x2c2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ec3; op2val:0xaec2; + valaddr_reg:x2; val_offset:1420*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1420*FLEN/8, x6, x4, x5) + +inst_741: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2c3 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x2c2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ec3; op2val:0xaec2; + valaddr_reg:x2; val_offset:1422*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1422*FLEN/8, x6, x4, x5) + +inst_742: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2c3 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x2c2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ec3; op2val:0xaec2; + valaddr_reg:x2; val_offset:1424*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1424*FLEN/8, x6, x4, x5) + +inst_743: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2c3 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x2c2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ec3; op2val:0xaec2; + valaddr_reg:x2; val_offset:1426*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1426*FLEN/8, x6, x4, x5) + +inst_744: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2c3 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x2c2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ec3; op2val:0xaec2; + valaddr_reg:x2; val_offset:1428*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1428*FLEN/8, x6, x4, x5) + +inst_745: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1f9 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x35f9; op2val:0xb5f8; + valaddr_reg:x2; val_offset:1430*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1430*FLEN/8, x6, x4, x5) + +inst_746: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1f9 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1f8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x35f9; op2val:0xb5f8; + valaddr_reg:x2; val_offset:1432*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1432*FLEN/8, x6, x4, x5) + +inst_747: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1f9 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1f8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x35f9; op2val:0xb5f8; + valaddr_reg:x2; val_offset:1434*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1434*FLEN/8, x6, x4, x5) + +inst_748: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1f9 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1f8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x35f9; op2val:0xb5f8; + valaddr_reg:x2; val_offset:1436*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1436*FLEN/8, x6, x4, x5) + +inst_749: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1f9 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1f8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x35f9; op2val:0xb5f8; + valaddr_reg:x2; val_offset:1438*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1438*FLEN/8, x6, x4, x5) + +inst_750: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x287 and fs2 == 1 and fe2 == 0x09 and fm2 == 0x283 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2687; op2val:0xa683; + valaddr_reg:x2; val_offset:1440*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1440*FLEN/8, x6, x4, x5) + +inst_751: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x287 and fs2 == 1 and fe2 == 0x09 and fm2 == 0x283 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2687; op2val:0xa683; + valaddr_reg:x2; val_offset:1442*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1442*FLEN/8, x6, x4, x5) + +inst_752: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x287 and fs2 == 1 and fe2 == 0x09 and fm2 == 0x283 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2687; op2val:0xa683; + valaddr_reg:x2; val_offset:1444*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1444*FLEN/8, x6, x4, x5) + +inst_753: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x287 and fs2 == 1 and fe2 == 0x09 and fm2 == 0x283 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2687; op2val:0xa683; + valaddr_reg:x2; val_offset:1446*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1446*FLEN/8, x6, x4, x5) + +inst_754: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x287 and fs2 == 1 and fe2 == 0x09 and fm2 == 0x283 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2687; op2val:0xa683; + valaddr_reg:x2; val_offset:1448*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1448*FLEN/8, x6, x4, x5) + +inst_755: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x379 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x379 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b79; op2val:0xbb79; + valaddr_reg:x2; val_offset:1450*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1450*FLEN/8, x6, x4, x5) + +inst_756: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x379 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x379 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b79; op2val:0xbb79; + valaddr_reg:x2; val_offset:1452*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1452*FLEN/8, x6, x4, x5) + +inst_757: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x379 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x379 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b79; op2val:0xbb79; + valaddr_reg:x2; val_offset:1454*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1454*FLEN/8, x6, x4, x5) + +inst_758: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x379 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x379 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b79; op2val:0xbb79; + valaddr_reg:x2; val_offset:1456*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1456*FLEN/8, x6, x4, x5) + +inst_759: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x379 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x379 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b79; op2val:0xbb79; + valaddr_reg:x2; val_offset:1458*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1458*FLEN/8, x6, x4, x5) + +inst_760: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3400; op2val:0xb400; + valaddr_reg:x2; val_offset:1460*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1460*FLEN/8, x6, x4, x5) + +inst_761: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3400; op2val:0xb400; + valaddr_reg:x2; val_offset:1462*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1462*FLEN/8, x6, x4, x5) + +inst_762: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3400; op2val:0xb400; + valaddr_reg:x2; val_offset:1464*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1464*FLEN/8, x6, x4, x5) + +inst_763: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3400; op2val:0xb400; + valaddr_reg:x2; val_offset:1466*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1466*FLEN/8, x6, x4, x5) + +inst_764: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3400; op2val:0xb400; + valaddr_reg:x2; val_offset:1468*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1468*FLEN/8, x6, x4, x5) + +inst_765: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ef and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3ef and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bef; op2val:0xbbef; + valaddr_reg:x2; val_offset:1470*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1470*FLEN/8, x6, x4, x5) + +inst_766: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ef and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3ef and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bef; op2val:0xbbef; + valaddr_reg:x2; val_offset:1472*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1472*FLEN/8, x6, x4, x5) + +inst_767: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ef and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3ef and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bef; op2val:0xbbef; + valaddr_reg:x2; val_offset:1474*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1474*FLEN/8, x6, x4, x5) + +inst_768: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ef and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3ef and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bef; op2val:0xbbef; + valaddr_reg:x2; val_offset:1476*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1476*FLEN/8, x6, x4, x5) + +inst_769: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ef and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3ef and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bef; op2val:0xbbef; + valaddr_reg:x2; val_offset:1478*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1478*FLEN/8, x6, x4, x5) + +inst_770: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3b2 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3b2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x37b2; op2val:0xb7b2; + valaddr_reg:x2; val_offset:1480*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1480*FLEN/8, x6, x4, x5) + +inst_771: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3b2 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3b2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x37b2; op2val:0xb7b2; + valaddr_reg:x2; val_offset:1482*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1482*FLEN/8, x6, x4, x5) + +inst_772: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3b2 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3b2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x37b2; op2val:0xb7b2; + valaddr_reg:x2; val_offset:1484*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1484*FLEN/8, x6, x4, x5) + +inst_773: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3b2 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3b2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x37b2; op2val:0xb7b2; + valaddr_reg:x2; val_offset:1486*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1486*FLEN/8, x6, x4, x5) + +inst_774: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3b2 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3b2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x37b2; op2val:0xb7b2; + valaddr_reg:x2; val_offset:1488*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1488*FLEN/8, x6, x4, x5) + +inst_775: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x017 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x017 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3817; op2val:0xb817; + valaddr_reg:x2; val_offset:1490*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1490*FLEN/8, x6, x4, x5) + +inst_776: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x017 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x017 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3817; op2val:0xb817; + valaddr_reg:x2; val_offset:1492*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1492*FLEN/8, x6, x4, x5) + +inst_777: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x017 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x017 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3817; op2val:0xb817; + valaddr_reg:x2; val_offset:1494*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1494*FLEN/8, x6, x4, x5) + +inst_778: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x017 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x017 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3817; op2val:0xb817; + valaddr_reg:x2; val_offset:1496*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1496*FLEN/8, x6, x4, x5) + +inst_779: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x017 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x017 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3817; op2val:0xb817; + valaddr_reg:x2; val_offset:1498*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1498*FLEN/8, x6, x4, x5) + +inst_780: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x121 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x121 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3521; op2val:0xb521; + valaddr_reg:x2; val_offset:1500*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1500*FLEN/8, x6, x4, x5) + +inst_781: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x121 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x121 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3521; op2val:0xb521; + valaddr_reg:x2; val_offset:1502*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1502*FLEN/8, x6, x4, x5) + +inst_782: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x121 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x121 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3521; op2val:0xb521; + valaddr_reg:x2; val_offset:1504*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1504*FLEN/8, x6, x4, x5) + +inst_783: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x121 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x121 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3521; op2val:0xb521; + valaddr_reg:x2; val_offset:1506*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1506*FLEN/8, x6, x4, x5) + +inst_784: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x121 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x121 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3521; op2val:0xb521; + valaddr_reg:x2; val_offset:1508*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1508*FLEN/8, x6, x4, x5) + +inst_785: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x10d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x10d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x390d; op2val:0xb90d; + valaddr_reg:x2; val_offset:1510*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1510*FLEN/8, x6, x4, x5) + +inst_786: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x10d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x10d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x390d; op2val:0xb90d; + valaddr_reg:x2; val_offset:1512*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1512*FLEN/8, x6, x4, x5) + +inst_787: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x10d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x10d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x390d; op2val:0xb90d; + valaddr_reg:x2; val_offset:1514*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1514*FLEN/8, x6, x4, x5) + +inst_788: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x10d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x10d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x390d; op2val:0xb90d; + valaddr_reg:x2; val_offset:1516*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1516*FLEN/8, x6, x4, x5) + +inst_789: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x10d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x10d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x390d; op2val:0xb90d; + valaddr_reg:x2; val_offset:1518*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1518*FLEN/8, x6, x4, x5) + +inst_790: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1e9 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1e9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x39e9; op2val:0xb9e9; + valaddr_reg:x2; val_offset:1520*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1520*FLEN/8, x6, x4, x5) + +inst_791: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1e9 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1e9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x39e9; op2val:0xb9e9; + valaddr_reg:x2; val_offset:1522*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1522*FLEN/8, x6, x4, x5) + +inst_792: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1e9 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1e9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x39e9; op2val:0xb9e9; + valaddr_reg:x2; val_offset:1524*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1524*FLEN/8, x6, x4, x5) + +inst_793: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1e9 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1e9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x39e9; op2val:0xb9e9; + valaddr_reg:x2; val_offset:1526*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1526*FLEN/8, x6, x4, x5) +RVTEST_SIGBASE(x4,signature_x4_6) + +inst_794: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1e9 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1e9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x39e9; op2val:0xb9e9; + valaddr_reg:x2; val_offset:1528*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1528*FLEN/8, x6, x4, x5) + +inst_795: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x08c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x08c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x388c; op2val:0xb88c; + valaddr_reg:x2; val_offset:1530*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1530*FLEN/8, x6, x4, x5) + +inst_796: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x08c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x08c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x388c; op2val:0xb88c; + valaddr_reg:x2; val_offset:1532*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1532*FLEN/8, x6, x4, x5) + +inst_797: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x08c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x08c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x388c; op2val:0xb88c; + valaddr_reg:x2; val_offset:1534*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1534*FLEN/8, x6, x4, x5) + +inst_798: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x08c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x08c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x388c; op2val:0xb88c; + valaddr_reg:x2; val_offset:1536*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1536*FLEN/8, x6, x4, x5) + +inst_799: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x08c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x08c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x388c; op2val:0xb88c; + valaddr_reg:x2; val_offset:1538*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1538*FLEN/8, x6, x4, x5) + +inst_800: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x37d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x37d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b7d; op2val:0xbb7d; + valaddr_reg:x2; val_offset:1540*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1540*FLEN/8, x6, x4, x5) + +inst_801: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x37d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x37d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b7d; op2val:0xbb7d; + valaddr_reg:x2; val_offset:1542*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1542*FLEN/8, x6, x4, x5) + +inst_802: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x37d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x37d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b7d; op2val:0xbb7d; + valaddr_reg:x2; val_offset:1544*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1544*FLEN/8, x6, x4, x5) + +inst_803: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x37d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x37d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b7d; op2val:0xbb7d; + valaddr_reg:x2; val_offset:1546*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1546*FLEN/8, x6, x4, x5) + +inst_804: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x37d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x37d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b7d; op2val:0xbb7d; + valaddr_reg:x2; val_offset:1548*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1548*FLEN/8, x6, x4, x5) + +inst_805: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0c4 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0c4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x34c4; op2val:0xb4c4; + valaddr_reg:x2; val_offset:1550*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1550*FLEN/8, x6, x4, x5) + +inst_806: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0c4 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0c4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x34c4; op2val:0xb4c4; + valaddr_reg:x2; val_offset:1552*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1552*FLEN/8, x6, x4, x5) + +inst_807: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0c4 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0c4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x34c4; op2val:0xb4c4; + valaddr_reg:x2; val_offset:1554*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1554*FLEN/8, x6, x4, x5) + +inst_808: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0c4 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0c4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x34c4; op2val:0xb4c4; + valaddr_reg:x2; val_offset:1556*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1556*FLEN/8, x6, x4, x5) + +inst_809: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0c4 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0c4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x34c4; op2val:0xb4c4; + valaddr_reg:x2; val_offset:1558*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1558*FLEN/8, x6, x4, x5) + +inst_810: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x063 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x063 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3863; op2val:0xb863; + valaddr_reg:x2; val_offset:1560*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1560*FLEN/8, x6, x4, x5) + +inst_811: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x063 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x063 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3863; op2val:0xb863; + valaddr_reg:x2; val_offset:1562*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1562*FLEN/8, x6, x4, x5) + +inst_812: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x063 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x063 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3863; op2val:0xb863; + valaddr_reg:x2; val_offset:1564*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1564*FLEN/8, x6, x4, x5) + +inst_813: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x063 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x063 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3863; op2val:0xb863; + valaddr_reg:x2; val_offset:1566*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1566*FLEN/8, x6, x4, x5) + +inst_814: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x063 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x063 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3863; op2val:0xb863; + valaddr_reg:x2; val_offset:1568*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1568*FLEN/8, x6, x4, x5) + +inst_815: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x30c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x30c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b0c; op2val:0xbb0c; + valaddr_reg:x2; val_offset:1570*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1570*FLEN/8, x6, x4, x5) + +inst_816: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x30c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x30c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b0c; op2val:0xbb0c; + valaddr_reg:x2; val_offset:1572*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1572*FLEN/8, x6, x4, x5) + +inst_817: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x30c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x30c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b0c; op2val:0xbb0c; + valaddr_reg:x2; val_offset:1574*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1574*FLEN/8, x6, x4, x5) + +inst_818: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x30c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x30c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b0c; op2val:0xbb0c; + valaddr_reg:x2; val_offset:1576*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1576*FLEN/8, x6, x4, x5) + +inst_819: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x30c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x30c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b0c; op2val:0xbb0c; + valaddr_reg:x2; val_offset:1578*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1578*FLEN/8, x6, x4, x5) + +inst_820: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x257 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x257 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a57; op2val:0xba57; + valaddr_reg:x2; val_offset:1580*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1580*FLEN/8, x6, x4, x5) + +inst_821: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x257 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x257 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a57; op2val:0xba57; + valaddr_reg:x2; val_offset:1582*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1582*FLEN/8, x6, x4, x5) + +inst_822: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x257 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x257 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a57; op2val:0xba57; + valaddr_reg:x2; val_offset:1584*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1584*FLEN/8, x6, x4, x5) + +inst_823: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x257 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x257 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a57; op2val:0xba57; + valaddr_reg:x2; val_offset:1586*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1586*FLEN/8, x6, x4, x5) + +inst_824: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x257 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x257 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a57; op2val:0xba57; + valaddr_reg:x2; val_offset:1588*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1588*FLEN/8, x6, x4, x5) + +inst_825: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2ab and fs2 == 1 and fe2 == 0x0a and fm2 == 0x2a9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2aab; op2val:0xaaa9; + valaddr_reg:x2; val_offset:1590*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1590*FLEN/8, x6, x4, x5) + +inst_826: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2ab and fs2 == 1 and fe2 == 0x0a and fm2 == 0x2a9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2aab; op2val:0xaaa9; + valaddr_reg:x2; val_offset:1592*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1592*FLEN/8, x6, x4, x5) + +inst_827: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2ab and fs2 == 1 and fe2 == 0x0a and fm2 == 0x2a9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2aab; op2val:0xaaa9; + valaddr_reg:x2; val_offset:1594*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1594*FLEN/8, x6, x4, x5) + +inst_828: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2ab and fs2 == 1 and fe2 == 0x0a and fm2 == 0x2a9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2aab; op2val:0xaaa9; + valaddr_reg:x2; val_offset:1596*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1596*FLEN/8, x6, x4, x5) + +inst_829: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2ab and fs2 == 1 and fe2 == 0x0a and fm2 == 0x2a9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2aab; op2val:0xaaa9; + valaddr_reg:x2; val_offset:1598*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1598*FLEN/8, x6, x4, x5) + +inst_830: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0f9 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0f9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x38f9; op2val:0xb8f9; + valaddr_reg:x2; val_offset:1600*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1600*FLEN/8, x6, x4, x5) + +inst_831: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0f9 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0f9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x38f9; op2val:0xb8f9; + valaddr_reg:x2; val_offset:1602*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1602*FLEN/8, x6, x4, x5) + +inst_832: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0f9 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0f9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x38f9; op2val:0xb8f9; + valaddr_reg:x2; val_offset:1604*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1604*FLEN/8, x6, x4, x5) + +inst_833: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0f9 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0f9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x38f9; op2val:0xb8f9; + valaddr_reg:x2; val_offset:1606*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1606*FLEN/8, x6, x4, x5) + +inst_834: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0f9 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0f9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x38f9; op2val:0xb8f9; + valaddr_reg:x2; val_offset:1608*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1608*FLEN/8, x6, x4, x5) + +inst_835: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ca and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2c9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aca; op2val:0xbac9; + valaddr_reg:x2; val_offset:1610*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1610*FLEN/8, x6, x4, x5) + +inst_836: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ca and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2c9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aca; op2val:0xbac9; + valaddr_reg:x2; val_offset:1612*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1612*FLEN/8, x6, x4, x5) + +inst_837: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ca and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2c9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aca; op2val:0xbac9; + valaddr_reg:x2; val_offset:1614*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1614*FLEN/8, x6, x4, x5) + +inst_838: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ca and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2c9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aca; op2val:0xbac9; + valaddr_reg:x2; val_offset:1616*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1616*FLEN/8, x6, x4, x5) + +inst_839: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ca and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2c9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aca; op2val:0xbac9; + valaddr_reg:x2; val_offset:1618*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1618*FLEN/8, x6, x4, x5) + +inst_840: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x05f and fs2 == 1 and fe2 == 0x09 and fm2 == 0x05a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x245f; op2val:0xa45a; + valaddr_reg:x2; val_offset:1620*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1620*FLEN/8, x6, x4, x5) + +inst_841: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x05f and fs2 == 1 and fe2 == 0x09 and fm2 == 0x05a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x245f; op2val:0xa45a; + valaddr_reg:x2; val_offset:1622*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1622*FLEN/8, x6, x4, x5) + +inst_842: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x05f and fs2 == 1 and fe2 == 0x09 and fm2 == 0x05a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x245f; op2val:0xa45a; + valaddr_reg:x2; val_offset:1624*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1624*FLEN/8, x6, x4, x5) + +inst_843: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x05f and fs2 == 1 and fe2 == 0x09 and fm2 == 0x05a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x245f; op2val:0xa45a; + valaddr_reg:x2; val_offset:1626*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1626*FLEN/8, x6, x4, x5) + +inst_844: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x05f and fs2 == 1 and fe2 == 0x09 and fm2 == 0x05a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x245f; op2val:0xa45a; + valaddr_reg:x2; val_offset:1628*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1628*FLEN/8, x6, x4, x5) + +inst_845: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0c0 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x38c0; op2val:0xb8c0; + valaddr_reg:x2; val_offset:1630*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1630*FLEN/8, x6, x4, x5) + +inst_846: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0c0 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0c0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x38c0; op2val:0xb8c0; + valaddr_reg:x2; val_offset:1632*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1632*FLEN/8, x6, x4, x5) + +inst_847: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0c0 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0c0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x38c0; op2val:0xb8c0; + valaddr_reg:x2; val_offset:1634*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1634*FLEN/8, x6, x4, x5) + +inst_848: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0c0 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0c0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x38c0; op2val:0xb8c0; + valaddr_reg:x2; val_offset:1636*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1636*FLEN/8, x6, x4, x5) + +inst_849: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0c0 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0c0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x38c0; op2val:0xb8c0; + valaddr_reg:x2; val_offset:1638*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1638*FLEN/8, x6, x4, x5) + +inst_850: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3d5 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x3d4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2fd5; op2val:0xafd4; + valaddr_reg:x2; val_offset:1640*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1640*FLEN/8, x6, x4, x5) + +inst_851: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3d5 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x3d4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2fd5; op2val:0xafd4; + valaddr_reg:x2; val_offset:1642*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1642*FLEN/8, x6, x4, x5) + +inst_852: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3d5 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x3d4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2fd5; op2val:0xafd4; + valaddr_reg:x2; val_offset:1644*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1644*FLEN/8, x6, x4, x5) + +inst_853: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3d5 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x3d4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2fd5; op2val:0xafd4; + valaddr_reg:x2; val_offset:1646*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1646*FLEN/8, x6, x4, x5) + +inst_854: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3d5 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x3d4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2fd5; op2val:0xafd4; + valaddr_reg:x2; val_offset:1648*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1648*FLEN/8, x6, x4, x5) + +inst_855: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x150 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x14f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d50; op2val:0xad4f; + valaddr_reg:x2; val_offset:1650*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1650*FLEN/8, x6, x4, x5) + +inst_856: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x150 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x14f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d50; op2val:0xad4f; + valaddr_reg:x2; val_offset:1652*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1652*FLEN/8, x6, x4, x5) + +inst_857: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x150 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x14f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d50; op2val:0xad4f; + valaddr_reg:x2; val_offset:1654*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1654*FLEN/8, x6, x4, x5) + +inst_858: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x150 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x14f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d50; op2val:0xad4f; + valaddr_reg:x2; val_offset:1656*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1656*FLEN/8, x6, x4, x5) + +inst_859: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x150 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x14f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d50; op2val:0xad4f; + valaddr_reg:x2; val_offset:1658*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1658*FLEN/8, x6, x4, x5) + +inst_860: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x003 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3803; op2val:0xb803; + valaddr_reg:x2; val_offset:1660*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1660*FLEN/8, x6, x4, x5) + +inst_861: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x003 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x003 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3803; op2val:0xb803; + valaddr_reg:x2; val_offset:1662*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1662*FLEN/8, x6, x4, x5) + +inst_862: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x003 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x003 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3803; op2val:0xb803; + valaddr_reg:x2; val_offset:1664*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1664*FLEN/8, x6, x4, x5) + +inst_863: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x003 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x003 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3803; op2val:0xb803; + valaddr_reg:x2; val_offset:1666*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1666*FLEN/8, x6, x4, x5) + +inst_864: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x003 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x003 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3803; op2val:0xb803; + valaddr_reg:x2; val_offset:1668*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1668*FLEN/8, x6, x4, x5) + +inst_865: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x147 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x147 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3547; op2val:0xb547; + valaddr_reg:x2; val_offset:1670*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1670*FLEN/8, x6, x4, x5) + +inst_866: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x147 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x147 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3547; op2val:0xb547; + valaddr_reg:x2; val_offset:1672*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1672*FLEN/8, x6, x4, x5) + +inst_867: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x147 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x147 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3547; op2val:0xb547; + valaddr_reg:x2; val_offset:1674*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1674*FLEN/8, x6, x4, x5) + +inst_868: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x147 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x147 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3547; op2val:0xb547; + valaddr_reg:x2; val_offset:1676*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1676*FLEN/8, x6, x4, x5) + +inst_869: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x147 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x147 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3547; op2val:0xb547; + valaddr_reg:x2; val_offset:1678*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1678*FLEN/8, x6, x4, x5) + +inst_870: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x23e and fs2 == 1 and fe2 == 0x0d and fm2 == 0x23e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x363e; op2val:0xb63e; + valaddr_reg:x2; val_offset:1680*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1680*FLEN/8, x6, x4, x5) + +inst_871: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x23e and fs2 == 1 and fe2 == 0x0d and fm2 == 0x23e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x363e; op2val:0xb63e; + valaddr_reg:x2; val_offset:1682*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1682*FLEN/8, x6, x4, x5) + +inst_872: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x23e and fs2 == 1 and fe2 == 0x0d and fm2 == 0x23e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x363e; op2val:0xb63e; + valaddr_reg:x2; val_offset:1684*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1684*FLEN/8, x6, x4, x5) + +inst_873: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x23e and fs2 == 1 and fe2 == 0x0d and fm2 == 0x23e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x363e; op2val:0xb63e; + valaddr_reg:x2; val_offset:1686*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1686*FLEN/8, x6, x4, x5) + +inst_874: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x23e and fs2 == 1 and fe2 == 0x0d and fm2 == 0x23e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x363e; op2val:0xb63e; + valaddr_reg:x2; val_offset:1688*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1688*FLEN/8, x6, x4, x5) + +inst_875: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x147 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x147 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3947; op2val:0xb947; + valaddr_reg:x2; val_offset:1690*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1690*FLEN/8, x6, x4, x5) + +inst_876: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x147 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x147 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3947; op2val:0xb947; + valaddr_reg:x2; val_offset:1692*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1692*FLEN/8, x6, x4, x5) + +inst_877: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x147 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x147 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3947; op2val:0xb947; + valaddr_reg:x2; val_offset:1694*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1694*FLEN/8, x6, x4, x5) + +inst_878: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x147 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x147 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3947; op2val:0xb947; + valaddr_reg:x2; val_offset:1696*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1696*FLEN/8, x6, x4, x5) + +inst_879: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x147 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x147 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3947; op2val:0xb947; + valaddr_reg:x2; val_offset:1698*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1698*FLEN/8, x6, x4, x5) + +inst_880: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x277 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x276 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e77; op2val:0xae76; + valaddr_reg:x2; val_offset:1700*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1700*FLEN/8, x6, x4, x5) + +inst_881: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x277 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x276 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e77; op2val:0xae76; + valaddr_reg:x2; val_offset:1702*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1702*FLEN/8, x6, x4, x5) + +inst_882: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x277 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x276 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e77; op2val:0xae76; + valaddr_reg:x2; val_offset:1704*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1704*FLEN/8, x6, x4, x5) + +inst_883: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x277 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x276 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e77; op2val:0xae76; + valaddr_reg:x2; val_offset:1706*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1706*FLEN/8, x6, x4, x5) + +inst_884: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x277 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x276 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e77; op2val:0xae76; + valaddr_reg:x2; val_offset:1708*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1708*FLEN/8, x6, x4, x5) + +inst_885: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bb7; op2val:0xbbb7; + valaddr_reg:x2; val_offset:1710*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1710*FLEN/8, x6, x4, x5) + +inst_886: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bb7; op2val:0xbbb7; + valaddr_reg:x2; val_offset:1712*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1712*FLEN/8, x6, x4, x5) + +inst_887: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bb7; op2val:0xbbb7; + valaddr_reg:x2; val_offset:1714*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1714*FLEN/8, x6, x4, x5) + +inst_888: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bb7; op2val:0xbbb7; + valaddr_reg:x2; val_offset:1716*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1716*FLEN/8, x6, x4, x5) + +inst_889: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bb7; op2val:0xbbb7; + valaddr_reg:x2; val_offset:1718*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1718*FLEN/8, x6, x4, x5) + +inst_890: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1f1 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1f1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x39f1; op2val:0xb9f1; + valaddr_reg:x2; val_offset:1720*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1720*FLEN/8, x6, x4, x5) + +inst_891: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1f1 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1f1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x39f1; op2val:0xb9f1; + valaddr_reg:x2; val_offset:1722*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1722*FLEN/8, x6, x4, x5) + +inst_892: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1f1 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1f1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x39f1; op2val:0xb9f1; + valaddr_reg:x2; val_offset:1724*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1724*FLEN/8, x6, x4, x5) + +inst_893: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1f1 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1f1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x39f1; op2val:0xb9f1; + valaddr_reg:x2; val_offset:1726*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1726*FLEN/8, x6, x4, x5) + +inst_894: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1f1 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1f1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x39f1; op2val:0xb9f1; + valaddr_reg:x2; val_offset:1728*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1728*FLEN/8, x6, x4, x5) + +inst_895: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x10c and fs2 == 1 and fe2 == 0x0c and fm2 == 0x10b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x310c; op2val:0xb10b; + valaddr_reg:x2; val_offset:1730*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1730*FLEN/8, x6, x4, x5) + +inst_896: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x10c and fs2 == 1 and fe2 == 0x0c and fm2 == 0x10b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x310c; op2val:0xb10b; + valaddr_reg:x2; val_offset:1732*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1732*FLEN/8, x6, x4, x5) + +inst_897: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x10c and fs2 == 1 and fe2 == 0x0c and fm2 == 0x10b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x310c; op2val:0xb10b; + valaddr_reg:x2; val_offset:1734*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1734*FLEN/8, x6, x4, x5) + +inst_898: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x10c and fs2 == 1 and fe2 == 0x0c and fm2 == 0x10b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x310c; op2val:0xb10b; + valaddr_reg:x2; val_offset:1736*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1736*FLEN/8, x6, x4, x5) + +inst_899: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x10c and fs2 == 1 and fe2 == 0x0c and fm2 == 0x10b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x310c; op2val:0xb10b; + valaddr_reg:x2; val_offset:1738*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1738*FLEN/8, x6, x4, x5) + +inst_900: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x082 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x082 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3482; op2val:0xb482; + valaddr_reg:x2; val_offset:1740*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1740*FLEN/8, x6, x4, x5) + +inst_901: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x082 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x082 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3482; op2val:0xb482; + valaddr_reg:x2; val_offset:1742*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1742*FLEN/8, x6, x4, x5) + +inst_902: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x082 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x082 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3482; op2val:0xb482; + valaddr_reg:x2; val_offset:1744*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1744*FLEN/8, x6, x4, x5) + +inst_903: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x082 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x082 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3482; op2val:0xb482; + valaddr_reg:x2; val_offset:1746*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1746*FLEN/8, x6, x4, x5) + +inst_904: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x082 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x082 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3482; op2val:0xb482; + valaddr_reg:x2; val_offset:1748*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1748*FLEN/8, x6, x4, x5) + +inst_905: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x378 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x377 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b78; op2val:0xbb77; + valaddr_reg:x2; val_offset:1750*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1750*FLEN/8, x6, x4, x5) + +inst_906: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x378 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x377 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b78; op2val:0xbb77; + valaddr_reg:x2; val_offset:1752*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1752*FLEN/8, x6, x4, x5) + +inst_907: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x378 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x377 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b78; op2val:0xbb77; + valaddr_reg:x2; val_offset:1754*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1754*FLEN/8, x6, x4, x5) + +inst_908: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x378 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x377 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b78; op2val:0xbb77; + valaddr_reg:x2; val_offset:1756*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1756*FLEN/8, x6, x4, x5) + +inst_909: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x378 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x377 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b78; op2val:0xbb77; + valaddr_reg:x2; val_offset:1758*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1758*FLEN/8, x6, x4, x5) + +inst_910: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x032 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x031 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3032; op2val:0xb031; + valaddr_reg:x2; val_offset:1760*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1760*FLEN/8, x6, x4, x5) + +inst_911: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x032 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x031 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3032; op2val:0xb031; + valaddr_reg:x2; val_offset:1762*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1762*FLEN/8, x6, x4, x5) + +inst_912: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x032 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x031 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3032; op2val:0xb031; + valaddr_reg:x2; val_offset:1764*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1764*FLEN/8, x6, x4, x5) + +inst_913: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x032 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x031 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3032; op2val:0xb031; + valaddr_reg:x2; val_offset:1766*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1766*FLEN/8, x6, x4, x5) + +inst_914: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x032 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x031 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3032; op2val:0xb031; + valaddr_reg:x2; val_offset:1768*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1768*FLEN/8, x6, x4, x5) + +inst_915: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x233 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x232 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a33; op2val:0xba32; + valaddr_reg:x2; val_offset:1770*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1770*FLEN/8, x6, x4, x5) + +inst_916: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x233 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x232 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a33; op2val:0xba32; + valaddr_reg:x2; val_offset:1772*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1772*FLEN/8, x6, x4, x5) + +inst_917: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x233 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x232 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a33; op2val:0xba32; + valaddr_reg:x2; val_offset:1774*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1774*FLEN/8, x6, x4, x5) + +inst_918: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x233 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x232 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a33; op2val:0xba32; + valaddr_reg:x2; val_offset:1776*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1776*FLEN/8, x6, x4, x5) + +inst_919: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x233 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x232 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a33; op2val:0xba32; + valaddr_reg:x2; val_offset:1778*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1778*FLEN/8, x6, x4, x5) + +inst_920: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3be0; op2val:0xbbe0; + valaddr_reg:x2; val_offset:1780*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1780*FLEN/8, x6, x4, x5) + +inst_921: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3e0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3be0; op2val:0xbbe0; + valaddr_reg:x2; val_offset:1782*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1782*FLEN/8, x6, x4, x5) +RVTEST_SIGBASE(x4,signature_x4_7) + +inst_922: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3e0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3be0; op2val:0xbbe0; + valaddr_reg:x2; val_offset:1784*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1784*FLEN/8, x6, x4, x5) + +inst_923: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3e0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3be0; op2val:0xbbe0; + valaddr_reg:x2; val_offset:1786*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1786*FLEN/8, x6, x4, x5) + +inst_924: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3e0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3be0; op2val:0xbbe0; + valaddr_reg:x2; val_offset:1788*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1788*FLEN/8, x6, x4, x5) + +inst_925: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x15a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x15a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x395a; op2val:0xb95a; + valaddr_reg:x2; val_offset:1790*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1790*FLEN/8, x6, x4, x5) + +inst_926: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x15a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x15a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x395a; op2val:0xb95a; + valaddr_reg:x2; val_offset:1792*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1792*FLEN/8, x6, x4, x5) + +inst_927: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x15a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x15a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x395a; op2val:0xb95a; + valaddr_reg:x2; val_offset:1794*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1794*FLEN/8, x6, x4, x5) + +inst_928: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x15a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x15a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x395a; op2val:0xb95a; + valaddr_reg:x2; val_offset:1796*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1796*FLEN/8, x6, x4, x5) + +inst_929: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x15a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x15a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x395a; op2val:0xb95a; + valaddr_reg:x2; val_offset:1798*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1798*FLEN/8, x6, x4, x5) + +inst_930: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2cf and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2cf and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3acf; op2val:0xbacf; + valaddr_reg:x2; val_offset:1800*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1800*FLEN/8, x6, x4, x5) + +inst_931: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2cf and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2cf and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3acf; op2val:0xbacf; + valaddr_reg:x2; val_offset:1802*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1802*FLEN/8, x6, x4, x5) + +inst_932: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2cf and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2cf and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3acf; op2val:0xbacf; + valaddr_reg:x2; val_offset:1804*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1804*FLEN/8, x6, x4, x5) + +inst_933: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2cf and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2cf and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3acf; op2val:0xbacf; + valaddr_reg:x2; val_offset:1806*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1806*FLEN/8, x6, x4, x5) + +inst_934: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2cf and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2cf and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3acf; op2val:0xbacf; + valaddr_reg:x2; val_offset:1808*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1808*FLEN/8, x6, x4, x5) + +inst_935: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x007 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x004 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2807; op2val:0xa804; + valaddr_reg:x2; val_offset:1810*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1810*FLEN/8, x6, x4, x5) + +inst_936: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x007 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x004 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2807; op2val:0xa804; + valaddr_reg:x2; val_offset:1812*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1812*FLEN/8, x6, x4, x5) + +inst_937: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x007 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x004 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2807; op2val:0xa804; + valaddr_reg:x2; val_offset:1814*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1814*FLEN/8, x6, x4, x5) + +inst_938: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x007 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x004 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2807; op2val:0xa804; + valaddr_reg:x2; val_offset:1816*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1816*FLEN/8, x6, x4, x5) + +inst_939: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x007 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x004 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2807; op2val:0xa804; + valaddr_reg:x2; val_offset:1818*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1818*FLEN/8, x6, x4, x5) + +inst_940: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x254 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e55; op2val:0xae54; + valaddr_reg:x2; val_offset:1820*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1820*FLEN/8, x6, x4, x5) + +inst_941: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x254 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e55; op2val:0xae54; + valaddr_reg:x2; val_offset:1822*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1822*FLEN/8, x6, x4, x5) + +inst_942: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x254 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e55; op2val:0xae54; + valaddr_reg:x2; val_offset:1824*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1824*FLEN/8, x6, x4, x5) + +inst_943: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x254 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e55; op2val:0xae54; + valaddr_reg:x2; val_offset:1826*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1826*FLEN/8, x6, x4, x5) + +inst_944: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x254 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e55; op2val:0xae54; + valaddr_reg:x2; val_offset:1828*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1828*FLEN/8, x6, x4, x5) + +inst_945: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2d1 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2d1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x36d1; op2val:0xb6d1; + valaddr_reg:x2; val_offset:1830*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1830*FLEN/8, x6, x4, x5) + +inst_946: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2d1 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2d1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x36d1; op2val:0xb6d1; + valaddr_reg:x2; val_offset:1832*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1832*FLEN/8, x6, x4, x5) + +inst_947: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2d1 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2d1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x36d1; op2val:0xb6d1; + valaddr_reg:x2; val_offset:1834*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1834*FLEN/8, x6, x4, x5) + +inst_948: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2d1 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2d1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x36d1; op2val:0xb6d1; + valaddr_reg:x2; val_offset:1836*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1836*FLEN/8, x6, x4, x5) + +inst_949: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2d1 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2d1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x36d1; op2val:0xb6d1; + valaddr_reg:x2; val_offset:1838*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1838*FLEN/8, x6, x4, x5) + +inst_950: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x23c and fs2 == 1 and fe2 == 0x0c and fm2 == 0x23c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x323c; op2val:0xb23c; + valaddr_reg:x2; val_offset:1840*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1840*FLEN/8, x6, x4, x5) + +inst_951: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x23c and fs2 == 1 and fe2 == 0x0c and fm2 == 0x23c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x323c; op2val:0xb23c; + valaddr_reg:x2; val_offset:1842*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1842*FLEN/8, x6, x4, x5) + +inst_952: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x23c and fs2 == 1 and fe2 == 0x0c and fm2 == 0x23c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x323c; op2val:0xb23c; + valaddr_reg:x2; val_offset:1844*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1844*FLEN/8, x6, x4, x5) + +inst_953: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x23c and fs2 == 1 and fe2 == 0x0c and fm2 == 0x23c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x323c; op2val:0xb23c; + valaddr_reg:x2; val_offset:1846*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1846*FLEN/8, x6, x4, x5) + +inst_954: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x23c and fs2 == 1 and fe2 == 0x0c and fm2 == 0x23c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x323c; op2val:0xb23c; + valaddr_reg:x2; val_offset:1848*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1848*FLEN/8, x6, x4, x5) + +inst_955: +// fs1 == 0 and fe1 == 0x08 and fm1 == 0x0e1 and fs2 == 1 and fe2 == 0x08 and fm2 == 0x0d8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x20e1; op2val:0xa0d8; + valaddr_reg:x2; val_offset:1850*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1850*FLEN/8, x6, x4, x5) + +inst_956: +// fs1 == 0 and fe1 == 0x08 and fm1 == 0x0e1 and fs2 == 1 and fe2 == 0x08 and fm2 == 0x0d8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x20e1; op2val:0xa0d8; + valaddr_reg:x2; val_offset:1852*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1852*FLEN/8, x6, x4, x5) + +inst_957: +// fs1 == 0 and fe1 == 0x08 and fm1 == 0x0e1 and fs2 == 1 and fe2 == 0x08 and fm2 == 0x0d8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x20e1; op2val:0xa0d8; + valaddr_reg:x2; val_offset:1854*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1854*FLEN/8, x6, x4, x5) + +inst_958: +// fs1 == 0 and fe1 == 0x08 and fm1 == 0x0e1 and fs2 == 1 and fe2 == 0x08 and fm2 == 0x0d8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x20e1; op2val:0xa0d8; + valaddr_reg:x2; val_offset:1856*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1856*FLEN/8, x6, x4, x5) + +inst_959: +// fs1 == 0 and fe1 == 0x08 and fm1 == 0x0e1 and fs2 == 1 and fe2 == 0x08 and fm2 == 0x0d8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x20e1; op2val:0xa0d8; + valaddr_reg:x2; val_offset:1858*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1858*FLEN/8, x6, x4, x5) + +inst_960: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x208 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x207 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e08; op2val:0xae07; + valaddr_reg:x2; val_offset:1860*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1860*FLEN/8, x6, x4, x5) + +inst_961: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x208 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x207 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e08; op2val:0xae07; + valaddr_reg:x2; val_offset:1862*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1862*FLEN/8, x6, x4, x5) + +inst_962: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x208 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x207 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e08; op2val:0xae07; + valaddr_reg:x2; val_offset:1864*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1864*FLEN/8, x6, x4, x5) + +inst_963: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x208 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x207 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e08; op2val:0xae07; + valaddr_reg:x2; val_offset:1866*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1866*FLEN/8, x6, x4, x5) + +inst_964: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x208 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x207 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e08; op2val:0xae07; + valaddr_reg:x2; val_offset:1868*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1868*FLEN/8, x6, x4, x5) + +inst_965: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x36f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x36e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x376f; op2val:0xb76e; + valaddr_reg:x2; val_offset:1870*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1870*FLEN/8, x6, x4, x5) + +inst_966: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x36f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x36e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x376f; op2val:0xb76e; + valaddr_reg:x2; val_offset:1872*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1872*FLEN/8, x6, x4, x5) + +inst_967: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x36f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x36e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x376f; op2val:0xb76e; + valaddr_reg:x2; val_offset:1874*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1874*FLEN/8, x6, x4, x5) + +inst_968: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x36f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x36e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x376f; op2val:0xb76e; + valaddr_reg:x2; val_offset:1876*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1876*FLEN/8, x6, x4, x5) + +inst_969: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x36f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x36e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x376f; op2val:0xb76e; + valaddr_reg:x2; val_offset:1878*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1878*FLEN/8, x6, x4, x5) + +inst_970: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x194 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x193 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3194; op2val:0xb193; + valaddr_reg:x2; val_offset:1880*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1880*FLEN/8, x6, x4, x5) + +inst_971: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x194 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x193 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3194; op2val:0xb193; + valaddr_reg:x2; val_offset:1882*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1882*FLEN/8, x6, x4, x5) + +inst_972: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x194 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x193 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3194; op2val:0xb193; + valaddr_reg:x2; val_offset:1884*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1884*FLEN/8, x6, x4, x5) + +inst_973: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x194 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x193 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3194; op2val:0xb193; + valaddr_reg:x2; val_offset:1886*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1886*FLEN/8, x6, x4, x5) + +inst_974: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x194 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x193 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3194; op2val:0xb193; + valaddr_reg:x2; val_offset:1888*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1888*FLEN/8, x6, x4, x5) + +inst_975: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2b0 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2af and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x32b0; op2val:0xb2af; + valaddr_reg:x2; val_offset:1890*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1890*FLEN/8, x6, x4, x5) + +inst_976: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2b0 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2af and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x32b0; op2val:0xb2af; + valaddr_reg:x2; val_offset:1892*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1892*FLEN/8, x6, x4, x5) + +inst_977: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2b0 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2af and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x32b0; op2val:0xb2af; + valaddr_reg:x2; val_offset:1894*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1894*FLEN/8, x6, x4, x5) + +inst_978: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2b0 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2af and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x32b0; op2val:0xb2af; + valaddr_reg:x2; val_offset:1896*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1896*FLEN/8, x6, x4, x5) + +inst_979: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2b0 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2af and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x32b0; op2val:0xb2af; + valaddr_reg:x2; val_offset:1898*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1898*FLEN/8, x6, x4, x5) + +inst_980: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x29e and fs2 == 1 and fe2 == 0x0d and fm2 == 0x29e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x369e; op2val:0xb69e; + valaddr_reg:x2; val_offset:1900*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1900*FLEN/8, x6, x4, x5) + +inst_981: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x29e and fs2 == 1 and fe2 == 0x0d and fm2 == 0x29e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x369e; op2val:0xb69e; + valaddr_reg:x2; val_offset:1902*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1902*FLEN/8, x6, x4, x5) + +inst_982: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x29e and fs2 == 1 and fe2 == 0x0d and fm2 == 0x29e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x369e; op2val:0xb69e; + valaddr_reg:x2; val_offset:1904*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1904*FLEN/8, x6, x4, x5) + +inst_983: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x29e and fs2 == 1 and fe2 == 0x0d and fm2 == 0x29e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x369e; op2val:0xb69e; + valaddr_reg:x2; val_offset:1906*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1906*FLEN/8, x6, x4, x5) + +inst_984: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x29e and fs2 == 1 and fe2 == 0x0d and fm2 == 0x29e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x369e; op2val:0xb69e; + valaddr_reg:x2; val_offset:1908*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1908*FLEN/8, x6, x4, x5) + +inst_985: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x276 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x276 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3276; op2val:0xb276; + valaddr_reg:x2; val_offset:1910*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1910*FLEN/8, x6, x4, x5) + +inst_986: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x276 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x276 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3276; op2val:0xb276; + valaddr_reg:x2; val_offset:1912*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1912*FLEN/8, x6, x4, x5) + +inst_987: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x276 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x276 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3276; op2val:0xb276; + valaddr_reg:x2; val_offset:1914*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1914*FLEN/8, x6, x4, x5) + +inst_988: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x276 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x276 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3276; op2val:0xb276; + valaddr_reg:x2; val_offset:1916*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1916*FLEN/8, x6, x4, x5) + +inst_989: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x276 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x276 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3276; op2val:0xb276; + valaddr_reg:x2; val_offset:1918*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1918*FLEN/8, x6, x4, x5) + +inst_990: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bff; op2val:0xbbff; + valaddr_reg:x2; val_offset:1920*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1920*FLEN/8, x6, x4, x5) + +inst_991: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bff; op2val:0xbbff; + valaddr_reg:x2; val_offset:1922*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1922*FLEN/8, x6, x4, x5) + +inst_992: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bff; op2val:0xbbff; + valaddr_reg:x2; val_offset:1924*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1924*FLEN/8, x6, x4, x5) + +inst_993: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bff; op2val:0xbbff; + valaddr_reg:x2; val_offset:1926*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1926*FLEN/8, x6, x4, x5) + +inst_994: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bff; op2val:0xbbff; + valaddr_reg:x2; val_offset:1928*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1928*FLEN/8, x6, x4, x5) + +inst_995: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3e4 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3e3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x37e4; op2val:0xb7e3; + valaddr_reg:x2; val_offset:1930*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1930*FLEN/8, x6, x4, x5) + +inst_996: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3e4 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3e3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x37e4; op2val:0xb7e3; + valaddr_reg:x2; val_offset:1932*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1932*FLEN/8, x6, x4, x5) + +inst_997: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3e4 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3e3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x37e4; op2val:0xb7e3; + valaddr_reg:x2; val_offset:1934*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1934*FLEN/8, x6, x4, x5) + +inst_998: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3e4 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3e3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x37e4; op2val:0xb7e3; + valaddr_reg:x2; val_offset:1936*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1936*FLEN/8, x6, x4, x5) + +inst_999: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3e4 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3e3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x37e4; op2val:0xb7e3; + valaddr_reg:x2; val_offset:1938*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1938*FLEN/8, x6, x4, x5) + +inst_1000: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x34f and fs2 == 1 and fe2 == 0x0a and fm2 == 0x34d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b4f; op2val:0xab4d; + valaddr_reg:x2; val_offset:1940*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1940*FLEN/8, x6, x4, x5) + +inst_1001: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x34f and fs2 == 1 and fe2 == 0x0a and fm2 == 0x34d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b4f; op2val:0xab4d; + valaddr_reg:x2; val_offset:1942*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1942*FLEN/8, x6, x4, x5) + +inst_1002: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x34f and fs2 == 1 and fe2 == 0x0a and fm2 == 0x34d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b4f; op2val:0xab4d; + valaddr_reg:x2; val_offset:1944*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1944*FLEN/8, x6, x4, x5) + +inst_1003: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x34f and fs2 == 1 and fe2 == 0x0a and fm2 == 0x34d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b4f; op2val:0xab4d; + valaddr_reg:x2; val_offset:1946*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1946*FLEN/8, x6, x4, x5) + +inst_1004: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x34f and fs2 == 1 and fe2 == 0x0a and fm2 == 0x34d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b4f; op2val:0xab4d; + valaddr_reg:x2; val_offset:1948*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1948*FLEN/8, x6, x4, x5) + +inst_1005: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0bc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0bc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x38bc; op2val:0xb8bc; + valaddr_reg:x2; val_offset:1950*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1950*FLEN/8, x6, x4, x5) + +inst_1006: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0bc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0bc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x38bc; op2val:0xb8bc; + valaddr_reg:x2; val_offset:1952*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1952*FLEN/8, x6, x4, x5) + +inst_1007: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0bc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0bc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x38bc; op2val:0xb8bc; + valaddr_reg:x2; val_offset:1954*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1954*FLEN/8, x6, x4, x5) + +inst_1008: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0bc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0bc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x38bc; op2val:0xb8bc; + valaddr_reg:x2; val_offset:1956*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1956*FLEN/8, x6, x4, x5) + +inst_1009: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0bc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0bc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x38bc; op2val:0xb8bc; + valaddr_reg:x2; val_offset:1958*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1958*FLEN/8, x6, x4, x5) + +inst_1010: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x380 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b80; op2val:0xbb80; + valaddr_reg:x2; val_offset:1960*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1960*FLEN/8, x6, x4, x5) + +inst_1011: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x380 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x380 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b80; op2val:0xbb80; + valaddr_reg:x2; val_offset:1962*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1962*FLEN/8, x6, x4, x5) + +inst_1012: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x380 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x380 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b80; op2val:0xbb80; + valaddr_reg:x2; val_offset:1964*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1964*FLEN/8, x6, x4, x5) + +inst_1013: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x380 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x380 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b80; op2val:0xbb80; + valaddr_reg:x2; val_offset:1966*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1966*FLEN/8, x6, x4, x5) + +inst_1014: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x380 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x380 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b80; op2val:0xbb80; + valaddr_reg:x2; val_offset:1968*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1968*FLEN/8, x6, x4, x5) + +inst_1015: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2fb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3afb; op2val:0xbafb; + valaddr_reg:x2; val_offset:1970*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1970*FLEN/8, x6, x4, x5) + +inst_1016: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2fb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3afb; op2val:0xbafb; + valaddr_reg:x2; val_offset:1972*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1972*FLEN/8, x6, x4, x5) + +inst_1017: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2fb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3afb; op2val:0xbafb; + valaddr_reg:x2; val_offset:1974*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1974*FLEN/8, x6, x4, x5) + +inst_1018: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2fb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3afb; op2val:0xbafb; + valaddr_reg:x2; val_offset:1976*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1976*FLEN/8, x6, x4, x5) + +inst_1019: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2fb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3afb; op2val:0xbafb; + valaddr_reg:x2; val_offset:1978*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1978*FLEN/8, x6, x4, x5) + +inst_1020: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x171 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x171 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3171; op2val:0xb171; + valaddr_reg:x2; val_offset:1980*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1980*FLEN/8, x6, x4, x5) + +inst_1021: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x171 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x171 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3171; op2val:0xb171; + valaddr_reg:x2; val_offset:1982*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1982*FLEN/8, x6, x4, x5) + +inst_1022: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x171 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x171 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3171; op2val:0xb171; + valaddr_reg:x2; val_offset:1984*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1984*FLEN/8, x6, x4, x5) + +inst_1023: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x171 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x171 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3171; op2val:0xb171; + valaddr_reg:x2; val_offset:1986*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1986*FLEN/8, x6, x4, x5) + +inst_1024: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x171 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x171 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3171; op2val:0xb171; + valaddr_reg:x2; val_offset:1988*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1988*FLEN/8, x6, x4, x5) + +inst_1025: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b6 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bb6; op2val:0xbbb6; + valaddr_reg:x2; val_offset:1990*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 1990*FLEN/8, x6, x4, x5) + +inst_1026: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b6 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bb6; op2val:0xbbb6; + valaddr_reg:x2; val_offset:1992*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 1992*FLEN/8, x6, x4, x5) + +inst_1027: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b6 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bb6; op2val:0xbbb6; + valaddr_reg:x2; val_offset:1994*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 1994*FLEN/8, x6, x4, x5) + +inst_1028: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b6 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bb6; op2val:0xbbb6; + valaddr_reg:x2; val_offset:1996*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 1996*FLEN/8, x6, x4, x5) + +inst_1029: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b6 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bb6; op2val:0xbbb6; + valaddr_reg:x2; val_offset:1998*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 1998*FLEN/8, x6, x4, x5) + +inst_1030: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x010 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x010 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3810; op2val:0xb810; + valaddr_reg:x2; val_offset:2000*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2000*FLEN/8, x6, x4, x5) + +inst_1031: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x010 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x010 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3810; op2val:0xb810; + valaddr_reg:x2; val_offset:2002*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2002*FLEN/8, x6, x4, x5) + +inst_1032: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x010 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x010 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3810; op2val:0xb810; + valaddr_reg:x2; val_offset:2004*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2004*FLEN/8, x6, x4, x5) + +inst_1033: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x010 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x010 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3810; op2val:0xb810; + valaddr_reg:x2; val_offset:2006*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2006*FLEN/8, x6, x4, x5) + +inst_1034: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x010 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x010 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3810; op2val:0xb810; + valaddr_reg:x2; val_offset:2008*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2008*FLEN/8, x6, x4, x5) + +inst_1035: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x086 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x086 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3486; op2val:0xb486; + valaddr_reg:x2; val_offset:2010*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2010*FLEN/8, x6, x4, x5) + +inst_1036: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x086 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x086 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3486; op2val:0xb486; + valaddr_reg:x2; val_offset:2012*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2012*FLEN/8, x6, x4, x5) + +inst_1037: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x086 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x086 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3486; op2val:0xb486; + valaddr_reg:x2; val_offset:2014*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2014*FLEN/8, x6, x4, x5) + +inst_1038: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x086 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x086 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3486; op2val:0xb486; + valaddr_reg:x2; val_offset:2016*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2016*FLEN/8, x6, x4, x5) + +inst_1039: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x086 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x086 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3486; op2val:0xb486; + valaddr_reg:x2; val_offset:2018*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2018*FLEN/8, x6, x4, x5) + +inst_1040: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0b6 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0b5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x38b6; op2val:0xb8b5; + valaddr_reg:x2; val_offset:2020*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2020*FLEN/8, x6, x4, x5) + +inst_1041: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0b6 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0b5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x38b6; op2val:0xb8b5; + valaddr_reg:x2; val_offset:2022*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2022*FLEN/8, x6, x4, x5) + +inst_1042: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0b6 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0b5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x38b6; op2val:0xb8b5; + valaddr_reg:x2; val_offset:2024*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2024*FLEN/8, x6, x4, x5) + +inst_1043: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0b6 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0b5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x38b6; op2val:0xb8b5; + valaddr_reg:x2; val_offset:2026*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2026*FLEN/8, x6, x4, x5) + +inst_1044: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0b6 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0b5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x38b6; op2val:0xb8b5; + valaddr_reg:x2; val_offset:2028*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2028*FLEN/8, x6, x4, x5) + +inst_1045: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0e7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x38e8; op2val:0xb8e7; + valaddr_reg:x2; val_offset:2030*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2030*FLEN/8, x6, x4, x5) + +inst_1046: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0e7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x38e8; op2val:0xb8e7; + valaddr_reg:x2; val_offset:2032*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2032*FLEN/8, x6, x4, x5) + +inst_1047: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0e7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x38e8; op2val:0xb8e7; + valaddr_reg:x2; val_offset:2034*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2034*FLEN/8, x6, x4, x5) + +inst_1048: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0e7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x38e8; op2val:0xb8e7; + valaddr_reg:x2; val_offset:2036*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2036*FLEN/8, x6, x4, x5) + +inst_1049: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0e7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x38e8; op2val:0xb8e7; + valaddr_reg:x2; val_offset:2038*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2038*FLEN/8, x6, x4, x5) +RVTEST_SIGBASE(x4,signature_x4_8) + +inst_1050: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x03b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x03b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x383b; op2val:0xb83b; + valaddr_reg:x2; val_offset:2040*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2040*FLEN/8, x6, x4, x5) + +inst_1051: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x03b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x03b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x383b; op2val:0xb83b; + valaddr_reg:x2; val_offset:2042*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2042*FLEN/8, x6, x4, x5) + +inst_1052: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x03b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x03b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x383b; op2val:0xb83b; + valaddr_reg:x2; val_offset:2044*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2044*FLEN/8, x6, x4, x5) + +inst_1053: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x03b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x03b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x383b; op2val:0xb83b; + valaddr_reg:x2; val_offset:2046*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2046*FLEN/8, x6, x4, x5) + +inst_1054: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x03b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x03b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x383b; op2val:0xb83b; + valaddr_reg:x2; val_offset:2048*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2048*FLEN/8, x6, x4, x5) + +inst_1055: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3bd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3bd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bbd; op2val:0xbbbd; + valaddr_reg:x2; val_offset:2050*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2050*FLEN/8, x6, x4, x5) + +inst_1056: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3bd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3bd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bbd; op2val:0xbbbd; + valaddr_reg:x2; val_offset:2052*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2052*FLEN/8, x6, x4, x5) + +inst_1057: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3bd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3bd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bbd; op2val:0xbbbd; + valaddr_reg:x2; val_offset:2054*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2054*FLEN/8, x6, x4, x5) + +inst_1058: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3bd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3bd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bbd; op2val:0xbbbd; + valaddr_reg:x2; val_offset:2056*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2056*FLEN/8, x6, x4, x5) + +inst_1059: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3bd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3bd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bbd; op2val:0xbbbd; + valaddr_reg:x2; val_offset:2058*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2058*FLEN/8, x6, x4, x5) + +inst_1060: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1eb and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1eb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x35eb; op2val:0xb5eb; + valaddr_reg:x2; val_offset:2060*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2060*FLEN/8, x6, x4, x5) + +inst_1061: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1eb and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1eb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x35eb; op2val:0xb5eb; + valaddr_reg:x2; val_offset:2062*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2062*FLEN/8, x6, x4, x5) + +inst_1062: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1eb and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1eb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x35eb; op2val:0xb5eb; + valaddr_reg:x2; val_offset:2064*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2064*FLEN/8, x6, x4, x5) + +inst_1063: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1eb and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1eb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x35eb; op2val:0xb5eb; + valaddr_reg:x2; val_offset:2066*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2066*FLEN/8, x6, x4, x5) + +inst_1064: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1eb and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1eb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x35eb; op2val:0xb5eb; + valaddr_reg:x2; val_offset:2068*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2068*FLEN/8, x6, x4, x5) + +inst_1065: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x336 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x336 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3736; op2val:0xb736; + valaddr_reg:x2; val_offset:2070*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2070*FLEN/8, x6, x4, x5) + +inst_1066: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x336 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x336 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3736; op2val:0xb736; + valaddr_reg:x2; val_offset:2072*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2072*FLEN/8, x6, x4, x5) + +inst_1067: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x336 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x336 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3736; op2val:0xb736; + valaddr_reg:x2; val_offset:2074*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2074*FLEN/8, x6, x4, x5) + +inst_1068: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x336 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x336 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3736; op2val:0xb736; + valaddr_reg:x2; val_offset:2076*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2076*FLEN/8, x6, x4, x5) + +inst_1069: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x336 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x336 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3736; op2val:0xb736; + valaddr_reg:x2; val_offset:2078*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2078*FLEN/8, x6, x4, x5) + +inst_1070: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ee and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0ee and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x38ee; op2val:0xb8ee; + valaddr_reg:x2; val_offset:2080*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2080*FLEN/8, x6, x4, x5) + +inst_1071: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ee and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0ee and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x38ee; op2val:0xb8ee; + valaddr_reg:x2; val_offset:2082*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2082*FLEN/8, x6, x4, x5) + +inst_1072: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ee and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0ee and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x38ee; op2val:0xb8ee; + valaddr_reg:x2; val_offset:2084*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2084*FLEN/8, x6, x4, x5) + +inst_1073: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ee and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0ee and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x38ee; op2val:0xb8ee; + valaddr_reg:x2; val_offset:2086*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2086*FLEN/8, x6, x4, x5) + +inst_1074: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ee and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0ee and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x38ee; op2val:0xb8ee; + valaddr_reg:x2; val_offset:2088*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2088*FLEN/8, x6, x4, x5) + +inst_1075: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x013 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x013 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3813; op2val:0xb813; + valaddr_reg:x2; val_offset:2090*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2090*FLEN/8, x6, x4, x5) + +inst_1076: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x013 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x013 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3813; op2val:0xb813; + valaddr_reg:x2; val_offset:2092*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2092*FLEN/8, x6, x4, x5) + +inst_1077: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x013 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x013 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3813; op2val:0xb813; + valaddr_reg:x2; val_offset:2094*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2094*FLEN/8, x6, x4, x5) + +inst_1078: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x013 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x013 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3813; op2val:0xb813; + valaddr_reg:x2; val_offset:2096*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2096*FLEN/8, x6, x4, x5) + +inst_1079: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x013 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x013 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3813; op2val:0xb813; + valaddr_reg:x2; val_offset:2098*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2098*FLEN/8, x6, x4, x5) + +inst_1080: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x23d and fs2 == 1 and fe2 == 0x0d and fm2 == 0x23c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x363d; op2val:0xb63c; + valaddr_reg:x2; val_offset:2100*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2100*FLEN/8, x6, x4, x5) + +inst_1081: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x23d and fs2 == 1 and fe2 == 0x0d and fm2 == 0x23c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x363d; op2val:0xb63c; + valaddr_reg:x2; val_offset:2102*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2102*FLEN/8, x6, x4, x5) + +inst_1082: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x23d and fs2 == 1 and fe2 == 0x0d and fm2 == 0x23c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x363d; op2val:0xb63c; + valaddr_reg:x2; val_offset:2104*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2104*FLEN/8, x6, x4, x5) + +inst_1083: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x23d and fs2 == 1 and fe2 == 0x0d and fm2 == 0x23c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x363d; op2val:0xb63c; + valaddr_reg:x2; val_offset:2106*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2106*FLEN/8, x6, x4, x5) + +inst_1084: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x23d and fs2 == 1 and fe2 == 0x0d and fm2 == 0x23c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x363d; op2val:0xb63c; + valaddr_reg:x2; val_offset:2108*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2108*FLEN/8, x6, x4, x5) + +inst_1085: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1e2 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1e1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x35e2; op2val:0xb5e1; + valaddr_reg:x2; val_offset:2110*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2110*FLEN/8, x6, x4, x5) + +inst_1086: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1e2 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1e1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x35e2; op2val:0xb5e1; + valaddr_reg:x2; val_offset:2112*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2112*FLEN/8, x6, x4, x5) + +inst_1087: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1e2 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1e1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x35e2; op2val:0xb5e1; + valaddr_reg:x2; val_offset:2114*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2114*FLEN/8, x6, x4, x5) + +inst_1088: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1e2 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1e1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x35e2; op2val:0xb5e1; + valaddr_reg:x2; val_offset:2116*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2116*FLEN/8, x6, x4, x5) + +inst_1089: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1e2 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1e1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x35e2; op2val:0xb5e1; + valaddr_reg:x2; val_offset:2118*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2118*FLEN/8, x6, x4, x5) + +inst_1090: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x301 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x301 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b01; op2val:0xbb01; + valaddr_reg:x2; val_offset:2120*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2120*FLEN/8, x6, x4, x5) + +inst_1091: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x301 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x301 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b01; op2val:0xbb01; + valaddr_reg:x2; val_offset:2122*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2122*FLEN/8, x6, x4, x5) + +inst_1092: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x301 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x301 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b01; op2val:0xbb01; + valaddr_reg:x2; val_offset:2124*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2124*FLEN/8, x6, x4, x5) + +inst_1093: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x301 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x301 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b01; op2val:0xbb01; + valaddr_reg:x2; val_offset:2126*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2126*FLEN/8, x6, x4, x5) + +inst_1094: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x301 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x301 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b01; op2val:0xbb01; + valaddr_reg:x2; val_offset:2128*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2128*FLEN/8, x6, x4, x5) + +inst_1095: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x20c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x20c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x360c; op2val:0xb60c; + valaddr_reg:x2; val_offset:2130*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2130*FLEN/8, x6, x4, x5) + +inst_1096: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x20c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x20c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x360c; op2val:0xb60c; + valaddr_reg:x2; val_offset:2132*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2132*FLEN/8, x6, x4, x5) + +inst_1097: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x20c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x20c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x360c; op2val:0xb60c; + valaddr_reg:x2; val_offset:2134*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2134*FLEN/8, x6, x4, x5) + +inst_1098: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x20c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x20c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x360c; op2val:0xb60c; + valaddr_reg:x2; val_offset:2136*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2136*FLEN/8, x6, x4, x5) + +inst_1099: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x20c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x20c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x360c; op2val:0xb60c; + valaddr_reg:x2; val_offset:2138*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2138*FLEN/8, x6, x4, x5) + +inst_1100: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x26c and fs2 == 1 and fe2 == 0x0c and fm2 == 0x26b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x326c; op2val:0xb26b; + valaddr_reg:x2; val_offset:2140*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2140*FLEN/8, x6, x4, x5) + +inst_1101: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x26c and fs2 == 1 and fe2 == 0x0c and fm2 == 0x26b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x326c; op2val:0xb26b; + valaddr_reg:x2; val_offset:2142*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2142*FLEN/8, x6, x4, x5) + +inst_1102: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x26c and fs2 == 1 and fe2 == 0x0c and fm2 == 0x26b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x326c; op2val:0xb26b; + valaddr_reg:x2; val_offset:2144*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2144*FLEN/8, x6, x4, x5) + +inst_1103: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x26c and fs2 == 1 and fe2 == 0x0c and fm2 == 0x26b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x326c; op2val:0xb26b; + valaddr_reg:x2; val_offset:2146*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2146*FLEN/8, x6, x4, x5) + +inst_1104: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x26c and fs2 == 1 and fe2 == 0x0c and fm2 == 0x26b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x326c; op2val:0xb26b; + valaddr_reg:x2; val_offset:2148*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2148*FLEN/8, x6, x4, x5) + +inst_1105: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x014 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x014 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3014; op2val:0xb014; + valaddr_reg:x2; val_offset:2150*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2150*FLEN/8, x6, x4, x5) + +inst_1106: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x014 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x014 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3014; op2val:0xb014; + valaddr_reg:x2; val_offset:2152*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2152*FLEN/8, x6, x4, x5) + +inst_1107: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x014 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x014 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3014; op2val:0xb014; + valaddr_reg:x2; val_offset:2154*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2154*FLEN/8, x6, x4, x5) + +inst_1108: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x014 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x014 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3014; op2val:0xb014; + valaddr_reg:x2; val_offset:2156*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2156*FLEN/8, x6, x4, x5) + +inst_1109: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x014 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x014 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3014; op2val:0xb014; + valaddr_reg:x2; val_offset:2158*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2158*FLEN/8, x6, x4, x5) + +inst_1110: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2dd and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2dd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x32dd; op2val:0xb2dd; + valaddr_reg:x2; val_offset:2160*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2160*FLEN/8, x6, x4, x5) + +inst_1111: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2dd and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2dd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x32dd; op2val:0xb2dd; + valaddr_reg:x2; val_offset:2162*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2162*FLEN/8, x6, x4, x5) + +inst_1112: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2dd and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2dd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x32dd; op2val:0xb2dd; + valaddr_reg:x2; val_offset:2164*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2164*FLEN/8, x6, x4, x5) + +inst_1113: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2dd and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2dd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x32dd; op2val:0xb2dd; + valaddr_reg:x2; val_offset:2166*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2166*FLEN/8, x6, x4, x5) + +inst_1114: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2dd and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2dd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x32dd; op2val:0xb2dd; + valaddr_reg:x2; val_offset:2168*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2168*FLEN/8, x6, x4, x5) + +inst_1115: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2f9 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x32f9; op2val:0xb2f8; + valaddr_reg:x2; val_offset:2170*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2170*FLEN/8, x6, x4, x5) + +inst_1116: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2f9 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2f8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x32f9; op2val:0xb2f8; + valaddr_reg:x2; val_offset:2172*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2172*FLEN/8, x6, x4, x5) + +inst_1117: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2f9 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2f8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x32f9; op2val:0xb2f8; + valaddr_reg:x2; val_offset:2174*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2174*FLEN/8, x6, x4, x5) + +inst_1118: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2f9 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2f8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x32f9; op2val:0xb2f8; + valaddr_reg:x2; val_offset:2176*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2176*FLEN/8, x6, x4, x5) + +inst_1119: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2f9 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2f8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x32f9; op2val:0xb2f8; + valaddr_reg:x2; val_offset:2178*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2178*FLEN/8, x6, x4, x5) + +inst_1120: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3ca and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3c9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x33ca; op2val:0xb3c9; + valaddr_reg:x2; val_offset:2180*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2180*FLEN/8, x6, x4, x5) + +inst_1121: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3ca and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3c9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x33ca; op2val:0xb3c9; + valaddr_reg:x2; val_offset:2182*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2182*FLEN/8, x6, x4, x5) + +inst_1122: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3ca and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3c9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x33ca; op2val:0xb3c9; + valaddr_reg:x2; val_offset:2184*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2184*FLEN/8, x6, x4, x5) + +inst_1123: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3ca and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3c9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x33ca; op2val:0xb3c9; + valaddr_reg:x2; val_offset:2186*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2186*FLEN/8, x6, x4, x5) + +inst_1124: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3ca and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3c9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x33ca; op2val:0xb3c9; + valaddr_reg:x2; val_offset:2188*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2188*FLEN/8, x6, x4, x5) + +inst_1125: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2bc and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2bb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x32bc; op2val:0xb2bb; + valaddr_reg:x2; val_offset:2190*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2190*FLEN/8, x6, x4, x5) + +inst_1126: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2bc and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2bb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x32bc; op2val:0xb2bb; + valaddr_reg:x2; val_offset:2192*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2192*FLEN/8, x6, x4, x5) + +inst_1127: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2bc and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2bb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x32bc; op2val:0xb2bb; + valaddr_reg:x2; val_offset:2194*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2194*FLEN/8, x6, x4, x5) + +inst_1128: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2bc and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2bb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x32bc; op2val:0xb2bb; + valaddr_reg:x2; val_offset:2196*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2196*FLEN/8, x6, x4, x5) + +inst_1129: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2bc and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2bb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x32bc; op2val:0xb2bb; + valaddr_reg:x2; val_offset:2198*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2198*FLEN/8, x6, x4, x5) + +inst_1130: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3a4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3a4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ba4; op2val:0xbba4; + valaddr_reg:x2; val_offset:2200*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2200*FLEN/8, x6, x4, x5) + +inst_1131: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3a4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3a4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ba4; op2val:0xbba4; + valaddr_reg:x2; val_offset:2202*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2202*FLEN/8, x6, x4, x5) + +inst_1132: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3a4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3a4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ba4; op2val:0xbba4; + valaddr_reg:x2; val_offset:2204*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2204*FLEN/8, x6, x4, x5) + +inst_1133: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3a4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3a4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ba4; op2val:0xbba4; + valaddr_reg:x2; val_offset:2206*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2206*FLEN/8, x6, x4, x5) + +inst_1134: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3a4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3a4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ba4; op2val:0xbba4; + valaddr_reg:x2; val_offset:2208*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2208*FLEN/8, x6, x4, x5) + +inst_1135: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x01c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x01c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x381c; op2val:0xb81c; + valaddr_reg:x2; val_offset:2210*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2210*FLEN/8, x6, x4, x5) + +inst_1136: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x01c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x01c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x381c; op2val:0xb81c; + valaddr_reg:x2; val_offset:2212*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2212*FLEN/8, x6, x4, x5) + +inst_1137: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x01c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x01c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x381c; op2val:0xb81c; + valaddr_reg:x2; val_offset:2214*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2214*FLEN/8, x6, x4, x5) + +inst_1138: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x01c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x01c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x381c; op2val:0xb81c; + valaddr_reg:x2; val_offset:2216*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2216*FLEN/8, x6, x4, x5) + +inst_1139: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x01c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x01c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x381c; op2val:0xb81c; + valaddr_reg:x2; val_offset:2218*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2218*FLEN/8, x6, x4, x5) + +inst_1140: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x313 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x311 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b13; op2val:0xab11; + valaddr_reg:x2; val_offset:2220*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2220*FLEN/8, x6, x4, x5) + +inst_1141: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x313 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x311 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b13; op2val:0xab11; + valaddr_reg:x2; val_offset:2222*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2222*FLEN/8, x6, x4, x5) + +inst_1142: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x313 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x311 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b13; op2val:0xab11; + valaddr_reg:x2; val_offset:2224*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2224*FLEN/8, x6, x4, x5) + +inst_1143: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x313 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x311 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b13; op2val:0xab11; + valaddr_reg:x2; val_offset:2226*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2226*FLEN/8, x6, x4, x5) + +inst_1144: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x313 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x311 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b13; op2val:0xab11; + valaddr_reg:x2; val_offset:2228*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2228*FLEN/8, x6, x4, x5) + +inst_1145: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2da and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2d9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x36da; op2val:0xb6d9; + valaddr_reg:x2; val_offset:2230*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2230*FLEN/8, x6, x4, x5) + +inst_1146: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2da and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2d9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x36da; op2val:0xb6d9; + valaddr_reg:x2; val_offset:2232*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2232*FLEN/8, x6, x4, x5) + +inst_1147: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2da and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2d9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x36da; op2val:0xb6d9; + valaddr_reg:x2; val_offset:2234*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2234*FLEN/8, x6, x4, x5) + +inst_1148: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2da and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2d9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x36da; op2val:0xb6d9; + valaddr_reg:x2; val_offset:2236*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2236*FLEN/8, x6, x4, x5) + +inst_1149: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2da and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2d9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x36da; op2val:0xb6d9; + valaddr_reg:x2; val_offset:2238*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2238*FLEN/8, x6, x4, x5) + +inst_1150: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x340 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x340 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b40; op2val:0xbb40; + valaddr_reg:x2; val_offset:2240*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2240*FLEN/8, x6, x4, x5) + +inst_1151: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x340 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x340 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b40; op2val:0xbb40; + valaddr_reg:x2; val_offset:2242*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2242*FLEN/8, x6, x4, x5) + +inst_1152: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x340 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x340 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b40; op2val:0xbb40; + valaddr_reg:x2; val_offset:2244*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2244*FLEN/8, x6, x4, x5) + +inst_1153: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x340 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x340 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b40; op2val:0xbb40; + valaddr_reg:x2; val_offset:2246*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2246*FLEN/8, x6, x4, x5) + +inst_1154: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x340 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x340 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b40; op2val:0xbb40; + valaddr_reg:x2; val_offset:2248*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2248*FLEN/8, x6, x4, x5) + +inst_1155: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x31f and fs2 == 1 and fe2 == 0x0b and fm2 == 0x31e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2f1f; op2val:0xaf1e; + valaddr_reg:x2; val_offset:2250*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2250*FLEN/8, x6, x4, x5) + +inst_1156: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x31f and fs2 == 1 and fe2 == 0x0b and fm2 == 0x31e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2f1f; op2val:0xaf1e; + valaddr_reg:x2; val_offset:2252*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2252*FLEN/8, x6, x4, x5) + +inst_1157: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x31f and fs2 == 1 and fe2 == 0x0b and fm2 == 0x31e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2f1f; op2val:0xaf1e; + valaddr_reg:x2; val_offset:2254*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2254*FLEN/8, x6, x4, x5) + +inst_1158: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x31f and fs2 == 1 and fe2 == 0x0b and fm2 == 0x31e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2f1f; op2val:0xaf1e; + valaddr_reg:x2; val_offset:2256*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2256*FLEN/8, x6, x4, x5) + +inst_1159: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x31f and fs2 == 1 and fe2 == 0x0b and fm2 == 0x31e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2f1f; op2val:0xaf1e; + valaddr_reg:x2; val_offset:2258*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2258*FLEN/8, x6, x4, x5) + +inst_1160: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0d3 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0d2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x34d3; op2val:0xb4d2; + valaddr_reg:x2; val_offset:2260*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2260*FLEN/8, x6, x4, x5) + +inst_1161: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0d3 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0d2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x34d3; op2val:0xb4d2; + valaddr_reg:x2; val_offset:2262*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2262*FLEN/8, x6, x4, x5) + +inst_1162: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0d3 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0d2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x34d3; op2val:0xb4d2; + valaddr_reg:x2; val_offset:2264*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2264*FLEN/8, x6, x4, x5) + +inst_1163: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0d3 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0d2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x34d3; op2val:0xb4d2; + valaddr_reg:x2; val_offset:2266*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2266*FLEN/8, x6, x4, x5) + +inst_1164: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0d3 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0d2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x34d3; op2val:0xb4d2; + valaddr_reg:x2; val_offset:2268*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2268*FLEN/8, x6, x4, x5) + +inst_1165: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x18e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x18e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x398e; op2val:0xb98e; + valaddr_reg:x2; val_offset:2270*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2270*FLEN/8, x6, x4, x5) + +inst_1166: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x18e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x18e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x398e; op2val:0xb98e; + valaddr_reg:x2; val_offset:2272*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2272*FLEN/8, x6, x4, x5) + +inst_1167: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x18e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x18e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x398e; op2val:0xb98e; + valaddr_reg:x2; val_offset:2274*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2274*FLEN/8, x6, x4, x5) + +inst_1168: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x18e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x18e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x398e; op2val:0xb98e; + valaddr_reg:x2; val_offset:2276*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2276*FLEN/8, x6, x4, x5) + +inst_1169: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x18e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x18e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x398e; op2val:0xb98e; + valaddr_reg:x2; val_offset:2278*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2278*FLEN/8, x6, x4, x5) + +inst_1170: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x097 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x097 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3897; op2val:0xb897; + valaddr_reg:x2; val_offset:2280*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2280*FLEN/8, x6, x4, x5) + +inst_1171: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x097 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x097 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3897; op2val:0xb897; + valaddr_reg:x2; val_offset:2282*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2282*FLEN/8, x6, x4, x5) + +inst_1172: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x097 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x097 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3897; op2val:0xb897; + valaddr_reg:x2; val_offset:2284*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2284*FLEN/8, x6, x4, x5) + +inst_1173: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x097 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x097 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3897; op2val:0xb897; + valaddr_reg:x2; val_offset:2286*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2286*FLEN/8, x6, x4, x5) + +inst_1174: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x097 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x097 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3897; op2val:0xb897; + valaddr_reg:x2; val_offset:2288*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2288*FLEN/8, x6, x4, x5) + +inst_1175: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x0ef and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2cf0; op2val:0xacef; + valaddr_reg:x2; val_offset:2290*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2290*FLEN/8, x6, x4, x5) + +inst_1176: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x0ef and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2cf0; op2val:0xacef; + valaddr_reg:x2; val_offset:2292*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2292*FLEN/8, x6, x4, x5) + +inst_1177: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x0ef and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2cf0; op2val:0xacef; + valaddr_reg:x2; val_offset:2294*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2294*FLEN/8, x6, x4, x5) +RVTEST_SIGBASE(x4,signature_x4_9) + +inst_1178: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x0ef and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2cf0; op2val:0xacef; + valaddr_reg:x2; val_offset:2296*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2296*FLEN/8, x6, x4, x5) + +inst_1179: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x0ef and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2cf0; op2val:0xacef; + valaddr_reg:x2; val_offset:2298*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2298*FLEN/8, x6, x4, x5) + +inst_1180: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ac and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0ac and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x38ac; op2val:0xb8ac; + valaddr_reg:x2; val_offset:2300*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2300*FLEN/8, x6, x4, x5) + +inst_1181: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ac and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0ac and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x38ac; op2val:0xb8ac; + valaddr_reg:x2; val_offset:2302*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2302*FLEN/8, x6, x4, x5) + +inst_1182: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ac and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0ac and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x38ac; op2val:0xb8ac; + valaddr_reg:x2; val_offset:2304*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2304*FLEN/8, x6, x4, x5) + +inst_1183: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ac and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0ac and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x38ac; op2val:0xb8ac; + valaddr_reg:x2; val_offset:2306*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2306*FLEN/8, x6, x4, x5) + +inst_1184: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ac and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0ac and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x38ac; op2val:0xb8ac; + valaddr_reg:x2; val_offset:2308*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2308*FLEN/8, x6, x4, x5) + +inst_1185: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x33d and fs2 == 1 and fe2 == 0x0c and fm2 == 0x33c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x333d; op2val:0xb33c; + valaddr_reg:x2; val_offset:2310*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2310*FLEN/8, x6, x4, x5) + +inst_1186: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x33d and fs2 == 1 and fe2 == 0x0c and fm2 == 0x33c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x333d; op2val:0xb33c; + valaddr_reg:x2; val_offset:2312*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2312*FLEN/8, x6, x4, x5) + +inst_1187: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x33d and fs2 == 1 and fe2 == 0x0c and fm2 == 0x33c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x333d; op2val:0xb33c; + valaddr_reg:x2; val_offset:2314*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2314*FLEN/8, x6, x4, x5) + +inst_1188: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x33d and fs2 == 1 and fe2 == 0x0c and fm2 == 0x33c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x333d; op2val:0xb33c; + valaddr_reg:x2; val_offset:2316*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2316*FLEN/8, x6, x4, x5) + +inst_1189: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x33d and fs2 == 1 and fe2 == 0x0c and fm2 == 0x33c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x333d; op2val:0xb33c; + valaddr_reg:x2; val_offset:2318*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2318*FLEN/8, x6, x4, x5) + +inst_1190: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c1 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bc1; op2val:0xbbc0; + valaddr_reg:x2; val_offset:2320*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2320*FLEN/8, x6, x4, x5) + +inst_1191: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c1 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3c0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bc1; op2val:0xbbc0; + valaddr_reg:x2; val_offset:2322*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2322*FLEN/8, x6, x4, x5) + +inst_1192: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c1 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3c0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bc1; op2val:0xbbc0; + valaddr_reg:x2; val_offset:2324*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2324*FLEN/8, x6, x4, x5) + +inst_1193: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c1 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3c0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bc1; op2val:0xbbc0; + valaddr_reg:x2; val_offset:2326*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2326*FLEN/8, x6, x4, x5) + +inst_1194: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c1 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3c0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bc1; op2val:0xbbc0; + valaddr_reg:x2; val_offset:2328*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2328*FLEN/8, x6, x4, x5) + +inst_1195: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x104 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x104 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3504; op2val:0xb504; + valaddr_reg:x2; val_offset:2330*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2330*FLEN/8, x6, x4, x5) + +inst_1196: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x104 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x104 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3504; op2val:0xb504; + valaddr_reg:x2; val_offset:2332*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2332*FLEN/8, x6, x4, x5) + +inst_1197: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x104 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x104 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3504; op2val:0xb504; + valaddr_reg:x2; val_offset:2334*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2334*FLEN/8, x6, x4, x5) + +inst_1198: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x104 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x104 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3504; op2val:0xb504; + valaddr_reg:x2; val_offset:2336*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2336*FLEN/8, x6, x4, x5) + +inst_1199: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x104 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x104 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3504; op2val:0xb504; + valaddr_reg:x2; val_offset:2338*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2338*FLEN/8, x6, x4, x5) + +inst_1200: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x12b and fs2 == 1 and fe2 == 0x0b and fm2 == 0x12a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d2b; op2val:0xad2a; + valaddr_reg:x2; val_offset:2340*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2340*FLEN/8, x6, x4, x5) + +inst_1201: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x12b and fs2 == 1 and fe2 == 0x0b and fm2 == 0x12a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d2b; op2val:0xad2a; + valaddr_reg:x2; val_offset:2342*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2342*FLEN/8, x6, x4, x5) + +inst_1202: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x12b and fs2 == 1 and fe2 == 0x0b and fm2 == 0x12a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d2b; op2val:0xad2a; + valaddr_reg:x2; val_offset:2344*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2344*FLEN/8, x6, x4, x5) + +inst_1203: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x12b and fs2 == 1 and fe2 == 0x0b and fm2 == 0x12a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d2b; op2val:0xad2a; + valaddr_reg:x2; val_offset:2346*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2346*FLEN/8, x6, x4, x5) + +inst_1204: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x12b and fs2 == 1 and fe2 == 0x0b and fm2 == 0x12a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d2b; op2val:0xad2a; + valaddr_reg:x2; val_offset:2348*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2348*FLEN/8, x6, x4, x5) + +inst_1205: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x070 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x070 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3470; op2val:0xb470; + valaddr_reg:x2; val_offset:2350*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2350*FLEN/8, x6, x4, x5) + +inst_1206: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x070 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x070 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3470; op2val:0xb470; + valaddr_reg:x2; val_offset:2352*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2352*FLEN/8, x6, x4, x5) + +inst_1207: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x070 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x070 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3470; op2val:0xb470; + valaddr_reg:x2; val_offset:2354*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2354*FLEN/8, x6, x4, x5) + +inst_1208: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x070 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x070 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3470; op2val:0xb470; + valaddr_reg:x2; val_offset:2356*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2356*FLEN/8, x6, x4, x5) + +inst_1209: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x070 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x070 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3470; op2val:0xb470; + valaddr_reg:x2; val_offset:2358*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2358*FLEN/8, x6, x4, x5) + +inst_1210: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x36f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b6f; op2val:0xbb6f; + valaddr_reg:x2; val_offset:2360*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2360*FLEN/8, x6, x4, x5) + +inst_1211: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x36f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b6f; op2val:0xbb6f; + valaddr_reg:x2; val_offset:2362*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2362*FLEN/8, x6, x4, x5) + +inst_1212: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x36f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b6f; op2val:0xbb6f; + valaddr_reg:x2; val_offset:2364*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2364*FLEN/8, x6, x4, x5) + +inst_1213: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x36f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b6f; op2val:0xbb6f; + valaddr_reg:x2; val_offset:2366*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2366*FLEN/8, x6, x4, x5) + +inst_1214: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x36f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b6f; op2val:0xbb6f; + valaddr_reg:x2; val_offset:2368*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2368*FLEN/8, x6, x4, x5) + +inst_1215: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3c3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bc3; op2val:0xbbc3; + valaddr_reg:x2; val_offset:2370*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2370*FLEN/8, x6, x4, x5) + +inst_1216: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3c3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bc3; op2val:0xbbc3; + valaddr_reg:x2; val_offset:2372*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2372*FLEN/8, x6, x4, x5) + +inst_1217: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3c3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bc3; op2val:0xbbc3; + valaddr_reg:x2; val_offset:2374*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2374*FLEN/8, x6, x4, x5) + +inst_1218: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3c3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bc3; op2val:0xbbc3; + valaddr_reg:x2; val_offset:2376*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2376*FLEN/8, x6, x4, x5) + +inst_1219: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3c3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bc3; op2val:0xbbc3; + valaddr_reg:x2; val_offset:2378*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2378*FLEN/8, x6, x4, x5) + +inst_1220: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3eb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3eb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3beb; op2val:0xbbeb; + valaddr_reg:x2; val_offset:2380*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2380*FLEN/8, x6, x4, x5) + +inst_1221: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3eb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3eb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3beb; op2val:0xbbeb; + valaddr_reg:x2; val_offset:2382*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2382*FLEN/8, x6, x4, x5) + +inst_1222: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3eb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3eb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3beb; op2val:0xbbeb; + valaddr_reg:x2; val_offset:2384*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2384*FLEN/8, x6, x4, x5) + +inst_1223: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3eb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3eb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3beb; op2val:0xbbeb; + valaddr_reg:x2; val_offset:2386*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2386*FLEN/8, x6, x4, x5) + +inst_1224: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3eb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3eb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3beb; op2val:0xbbeb; + valaddr_reg:x2; val_offset:2388*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2388*FLEN/8, x6, x4, x5) + +inst_1225: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x293 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x1b3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5293; op2val:0x49b3; + valaddr_reg:x2; val_offset:2390*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2390*FLEN/8, x6, x4, x5) + +inst_1226: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x293 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x1b3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5293; op2val:0x49b3; + valaddr_reg:x2; val_offset:2392*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2392*FLEN/8, x6, x4, x5) + +inst_1227: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x293 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x1b3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5293; op2val:0x49b3; + valaddr_reg:x2; val_offset:2394*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2394*FLEN/8, x6, x4, x5) + +inst_1228: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x293 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x1b3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5293; op2val:0x49b3; + valaddr_reg:x2; val_offset:2396*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2396*FLEN/8, x6, x4, x5) + +inst_1229: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x293 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x1b3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5293; op2val:0x49b3; + valaddr_reg:x2; val_offset:2398*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2398*FLEN/8, x6, x4, x5) + +inst_1230: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x329 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x2b6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5329; op2val:0x46b6; + valaddr_reg:x2; val_offset:2400*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2400*FLEN/8, x6, x4, x5) + +inst_1231: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x329 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x2b6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5329; op2val:0x46b6; + valaddr_reg:x2; val_offset:2402*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2402*FLEN/8, x6, x4, x5) + +inst_1232: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x329 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x2b6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5329; op2val:0x46b6; + valaddr_reg:x2; val_offset:2404*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2404*FLEN/8, x6, x4, x5) + +inst_1233: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x329 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x2b6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5329; op2val:0x46b6; + valaddr_reg:x2; val_offset:2406*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2406*FLEN/8, x6, x4, x5) + +inst_1234: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x329 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x2b6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5329; op2val:0x46b6; + valaddr_reg:x2; val_offset:2408*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2408*FLEN/8, x6, x4, x5) + +inst_1235: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x2f3 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x243 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4af3; op2val:0x5243; + valaddr_reg:x2; val_offset:2410*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2410*FLEN/8, x6, x4, x5) + +inst_1236: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x2f3 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x243 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4af3; op2val:0x5243; + valaddr_reg:x2; val_offset:2412*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2412*FLEN/8, x6, x4, x5) + +inst_1237: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x2f3 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x243 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4af3; op2val:0x5243; + valaddr_reg:x2; val_offset:2414*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2414*FLEN/8, x6, x4, x5) + +inst_1238: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x2f3 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x243 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4af3; op2val:0x5243; + valaddr_reg:x2; val_offset:2416*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2416*FLEN/8, x6, x4, x5) + +inst_1239: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x2f3 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x243 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4af3; op2val:0x5243; + valaddr_reg:x2; val_offset:2418*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2418*FLEN/8, x6, x4, x5) + +inst_1240: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x383 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3c7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5383; op2val:0x43c7; + valaddr_reg:x2; val_offset:2420*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2420*FLEN/8, x6, x4, x5) + +inst_1241: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x383 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3c7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5383; op2val:0x43c7; + valaddr_reg:x2; val_offset:2422*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2422*FLEN/8, x6, x4, x5) + +inst_1242: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x383 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3c7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5383; op2val:0x43c7; + valaddr_reg:x2; val_offset:2424*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2424*FLEN/8, x6, x4, x5) + +inst_1243: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x383 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3c7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5383; op2val:0x43c7; + valaddr_reg:x2; val_offset:2426*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2426*FLEN/8, x6, x4, x5) + +inst_1244: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x383 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3c7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5383; op2val:0x43c7; + valaddr_reg:x2; val_offset:2428*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2428*FLEN/8, x6, x4, x5) + +inst_1245: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x1cf and fs2 == 0 and fe2 == 0x14 and fm2 == 0x3d1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3dcf; op2val:0x53d1; + valaddr_reg:x2; val_offset:2430*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2430*FLEN/8, x6, x4, x5) + +inst_1246: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x1cf and fs2 == 0 and fe2 == 0x14 and fm2 == 0x3d1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3dcf; op2val:0x53d1; + valaddr_reg:x2; val_offset:2432*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2432*FLEN/8, x6, x4, x5) + +inst_1247: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x1cf and fs2 == 0 and fe2 == 0x14 and fm2 == 0x3d1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3dcf; op2val:0x53d1; + valaddr_reg:x2; val_offset:2434*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2434*FLEN/8, x6, x4, x5) + +inst_1248: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x1cf and fs2 == 0 and fe2 == 0x14 and fm2 == 0x3d1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3dcf; op2val:0x53d1; + valaddr_reg:x2; val_offset:2436*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2436*FLEN/8, x6, x4, x5) + +inst_1249: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x1cf and fs2 == 0 and fe2 == 0x14 and fm2 == 0x3d1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3dcf; op2val:0x53d1; + valaddr_reg:x2; val_offset:2438*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2438*FLEN/8, x6, x4, x5) + +inst_1250: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x11b and fs2 == 0 and fe2 == 0x14 and fm2 == 0x3ae and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x411b; op2val:0x53ae; + valaddr_reg:x2; val_offset:2440*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2440*FLEN/8, x6, x4, x5) + +inst_1251: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x11b and fs2 == 0 and fe2 == 0x14 and fm2 == 0x3ae and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x411b; op2val:0x53ae; + valaddr_reg:x2; val_offset:2442*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2442*FLEN/8, x6, x4, x5) + +inst_1252: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x11b and fs2 == 0 and fe2 == 0x14 and fm2 == 0x3ae and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x411b; op2val:0x53ae; + valaddr_reg:x2; val_offset:2444*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2444*FLEN/8, x6, x4, x5) + +inst_1253: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x11b and fs2 == 0 and fe2 == 0x14 and fm2 == 0x3ae and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x411b; op2val:0x53ae; + valaddr_reg:x2; val_offset:2446*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2446*FLEN/8, x6, x4, x5) + +inst_1254: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x11b and fs2 == 0 and fe2 == 0x14 and fm2 == 0x3ae and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x411b; op2val:0x53ae; + valaddr_reg:x2; val_offset:2448*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2448*FLEN/8, x6, x4, x5) + +inst_1255: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2e4 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x06f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x52e4; op2val:0x486f; + valaddr_reg:x2; val_offset:2450*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2450*FLEN/8, x6, x4, x5) + +inst_1256: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2e4 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x06f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x52e4; op2val:0x486f; + valaddr_reg:x2; val_offset:2452*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2452*FLEN/8, x6, x4, x5) + +inst_1257: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2e4 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x06f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x52e4; op2val:0x486f; + valaddr_reg:x2; val_offset:2454*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2454*FLEN/8, x6, x4, x5) + +inst_1258: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2e4 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x06f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x52e4; op2val:0x486f; + valaddr_reg:x2; val_offset:2456*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2456*FLEN/8, x6, x4, x5) + +inst_1259: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2e4 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x06f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x52e4; op2val:0x486f; + valaddr_reg:x2; val_offset:2458*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2458*FLEN/8, x6, x4, x5) + +inst_1260: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x00a and fs2 == 0 and fe2 == 0x14 and fm2 == 0x2fd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x480a; op2val:0x52fd; + valaddr_reg:x2; val_offset:2460*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2460*FLEN/8, x6, x4, x5) + +inst_1261: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x00a and fs2 == 0 and fe2 == 0x14 and fm2 == 0x2fd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x480a; op2val:0x52fd; + valaddr_reg:x2; val_offset:2462*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2462*FLEN/8, x6, x4, x5) + +inst_1262: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x00a and fs2 == 0 and fe2 == 0x14 and fm2 == 0x2fd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x480a; op2val:0x52fd; + valaddr_reg:x2; val_offset:2464*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2464*FLEN/8, x6, x4, x5) + +inst_1263: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x00a and fs2 == 0 and fe2 == 0x14 and fm2 == 0x2fd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x480a; op2val:0x52fd; + valaddr_reg:x2; val_offset:2466*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2466*FLEN/8, x6, x4, x5) + +inst_1264: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x00a and fs2 == 0 and fe2 == 0x14 and fm2 == 0x2fd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x480a; op2val:0x52fd; + valaddr_reg:x2; val_offset:2468*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2468*FLEN/8, x6, x4, x5) + +inst_1265: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3ad and fs2 == 0 and fe2 == 0x10 and fm2 == 0x125 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x53ad; op2val:0x4125; + valaddr_reg:x2; val_offset:2470*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2470*FLEN/8, x6, x4, x5) + +inst_1266: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3ad and fs2 == 0 and fe2 == 0x10 and fm2 == 0x125 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x53ad; op2val:0x4125; + valaddr_reg:x2; val_offset:2472*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2472*FLEN/8, x6, x4, x5) + +inst_1267: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3ad and fs2 == 0 and fe2 == 0x10 and fm2 == 0x125 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x53ad; op2val:0x4125; + valaddr_reg:x2; val_offset:2474*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2474*FLEN/8, x6, x4, x5) + +inst_1268: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3ad and fs2 == 0 and fe2 == 0x10 and fm2 == 0x125 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x53ad; op2val:0x4125; + valaddr_reg:x2; val_offset:2476*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2476*FLEN/8, x6, x4, x5) + +inst_1269: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3ad and fs2 == 0 and fe2 == 0x10 and fm2 == 0x125 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x53ad; op2val:0x4125; + valaddr_reg:x2; val_offset:2478*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2478*FLEN/8, x6, x4, x5) + +inst_1270: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3bc and fs2 == 0 and fe2 == 0x10 and fm2 == 0x038 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x53bc; op2val:0x4038; + valaddr_reg:x2; val_offset:2480*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2480*FLEN/8, x6, x4, x5) + +inst_1271: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3bc and fs2 == 0 and fe2 == 0x10 and fm2 == 0x038 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x53bc; op2val:0x4038; + valaddr_reg:x2; val_offset:2482*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2482*FLEN/8, x6, x4, x5) + +inst_1272: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3bc and fs2 == 0 and fe2 == 0x10 and fm2 == 0x038 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x53bc; op2val:0x4038; + valaddr_reg:x2; val_offset:2484*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2484*FLEN/8, x6, x4, x5) + +inst_1273: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3bc and fs2 == 0 and fe2 == 0x10 and fm2 == 0x038 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x53bc; op2val:0x4038; + valaddr_reg:x2; val_offset:2486*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2486*FLEN/8, x6, x4, x5) + +inst_1274: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3bc and fs2 == 0 and fe2 == 0x10 and fm2 == 0x038 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x53bc; op2val:0x4038; + valaddr_reg:x2; val_offset:2488*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2488*FLEN/8, x6, x4, x5) + +inst_1275: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3b4 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x025 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4fb4; op2val:0x5025; + valaddr_reg:x2; val_offset:2490*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2490*FLEN/8, x6, x4, x5) + +inst_1276: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3b4 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x025 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4fb4; op2val:0x5025; + valaddr_reg:x2; val_offset:2492*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2492*FLEN/8, x6, x4, x5) + +inst_1277: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3b4 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x025 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4fb4; op2val:0x5025; + valaddr_reg:x2; val_offset:2494*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2494*FLEN/8, x6, x4, x5) + +inst_1278: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3b4 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x025 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4fb4; op2val:0x5025; + valaddr_reg:x2; val_offset:2496*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2496*FLEN/8, x6, x4, x5) + +inst_1279: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3b4 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x025 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4fb4; op2val:0x5025; + valaddr_reg:x2; val_offset:2498*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2498*FLEN/8, x6, x4, x5) + +inst_1280: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x381 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3ec and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5381; op2val:0x43ec; + valaddr_reg:x2; val_offset:2500*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2500*FLEN/8, x6, x4, x5) + +inst_1281: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x381 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3ec and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5381; op2val:0x43ec; + valaddr_reg:x2; val_offset:2502*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2502*FLEN/8, x6, x4, x5) + +inst_1282: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x381 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3ec and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5381; op2val:0x43ec; + valaddr_reg:x2; val_offset:2504*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2504*FLEN/8, x6, x4, x5) + +inst_1283: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x381 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3ec and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5381; op2val:0x43ec; + valaddr_reg:x2; val_offset:2506*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2506*FLEN/8, x6, x4, x5) + +inst_1284: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x381 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3ec and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5381; op2val:0x43ec; + valaddr_reg:x2; val_offset:2508*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2508*FLEN/8, x6, x4, x5) + +inst_1285: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x122 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x1bc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5122; op2val:0x4dbc; + valaddr_reg:x2; val_offset:2510*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2510*FLEN/8, x6, x4, x5) + +inst_1286: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x122 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x1bc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5122; op2val:0x4dbc; + valaddr_reg:x2; val_offset:2512*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2512*FLEN/8, x6, x4, x5) + +inst_1287: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x122 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x1bc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5122; op2val:0x4dbc; + valaddr_reg:x2; val_offset:2514*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2514*FLEN/8, x6, x4, x5) + +inst_1288: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x122 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x1bc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5122; op2val:0x4dbc; + valaddr_reg:x2; val_offset:2516*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2516*FLEN/8, x6, x4, x5) + +inst_1289: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x122 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x1bc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5122; op2val:0x4dbc; + valaddr_reg:x2; val_offset:2518*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2518*FLEN/8, x6, x4, x5) + +inst_1290: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3f2 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x31b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x53f2; op2val:0x371b; + valaddr_reg:x2; val_offset:2520*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2520*FLEN/8, x6, x4, x5) + +inst_1291: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3f2 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x31b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x53f2; op2val:0x371b; + valaddr_reg:x2; val_offset:2522*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2522*FLEN/8, x6, x4, x5) + +inst_1292: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3f2 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x31b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x53f2; op2val:0x371b; + valaddr_reg:x2; val_offset:2524*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2524*FLEN/8, x6, x4, x5) + +inst_1293: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3f2 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x31b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x53f2; op2val:0x371b; + valaddr_reg:x2; val_offset:2526*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2526*FLEN/8, x6, x4, x5) + +inst_1294: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3f2 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x31b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x53f2; op2val:0x371b; + valaddr_reg:x2; val_offset:2528*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2528*FLEN/8, x6, x4, x5) + +inst_1295: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x0b3 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x29a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x50b3; op2val:0x4e9a; + valaddr_reg:x2; val_offset:2530*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2530*FLEN/8, x6, x4, x5) + +inst_1296: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x0b3 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x29a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x50b3; op2val:0x4e9a; + valaddr_reg:x2; val_offset:2532*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2532*FLEN/8, x6, x4, x5) + +inst_1297: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x0b3 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x29a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x50b3; op2val:0x4e9a; + valaddr_reg:x2; val_offset:2534*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2534*FLEN/8, x6, x4, x5) + +inst_1298: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x0b3 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x29a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x50b3; op2val:0x4e9a; + valaddr_reg:x2; val_offset:2536*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2536*FLEN/8, x6, x4, x5) + +inst_1299: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x0b3 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x29a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x50b3; op2val:0x4e9a; + valaddr_reg:x2; val_offset:2538*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2538*FLEN/8, x6, x4, x5) + +inst_1300: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x331 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x272 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5331; op2val:0x4672; + valaddr_reg:x2; val_offset:2540*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2540*FLEN/8, x6, x4, x5) + +inst_1301: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x331 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x272 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5331; op2val:0x4672; + valaddr_reg:x2; val_offset:2542*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2542*FLEN/8, x6, x4, x5) + +inst_1302: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x331 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x272 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5331; op2val:0x4672; + valaddr_reg:x2; val_offset:2544*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2544*FLEN/8, x6, x4, x5) + +inst_1303: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x331 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x272 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5331; op2val:0x4672; + valaddr_reg:x2; val_offset:2546*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2546*FLEN/8, x6, x4, x5) + +inst_1304: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x331 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x272 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5331; op2val:0x4672; + valaddr_reg:x2; val_offset:2548*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2548*FLEN/8, x6, x4, x5) + +inst_1305: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x275 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x229 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5275; op2val:0x4a29; + valaddr_reg:x2; val_offset:2550*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2550*FLEN/8, x6, x4, x5) +RVTEST_SIGBASE(x4,signature_x4_10) + +inst_1306: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x275 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x229 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5275; op2val:0x4a29; + valaddr_reg:x2; val_offset:2552*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2552*FLEN/8, x6, x4, x5) + +inst_1307: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x275 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x229 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5275; op2val:0x4a29; + valaddr_reg:x2; val_offset:2554*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2554*FLEN/8, x6, x4, x5) + +inst_1308: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x275 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x229 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5275; op2val:0x4a29; + valaddr_reg:x2; val_offset:2556*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2556*FLEN/8, x6, x4, x5) + +inst_1309: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x275 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x229 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5275; op2val:0x4a29; + valaddr_reg:x2; val_offset:2558*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2558*FLEN/8, x6, x4, x5) + +inst_1310: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x013 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x1f6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4c13; op2val:0x51f6; + valaddr_reg:x2; val_offset:2560*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2560*FLEN/8, x6, x4, x5) + +inst_1311: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x013 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x1f6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4c13; op2val:0x51f6; + valaddr_reg:x2; val_offset:2562*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2562*FLEN/8, x6, x4, x5) + +inst_1312: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x013 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x1f6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4c13; op2val:0x51f6; + valaddr_reg:x2; val_offset:2564*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2564*FLEN/8, x6, x4, x5) + +inst_1313: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x013 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x1f6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4c13; op2val:0x51f6; + valaddr_reg:x2; val_offset:2566*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2566*FLEN/8, x6, x4, x5) + +inst_1314: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x013 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x1f6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4c13; op2val:0x51f6; + valaddr_reg:x2; val_offset:2568*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2568*FLEN/8, x6, x4, x5) + +inst_1315: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x0d5 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x195 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4cd5; op2val:0x5195; + valaddr_reg:x2; val_offset:2570*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2570*FLEN/8, x6, x4, x5) + +inst_1316: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x0d5 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x195 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4cd5; op2val:0x5195; + valaddr_reg:x2; val_offset:2572*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2572*FLEN/8, x6, x4, x5) + +inst_1317: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x0d5 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x195 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4cd5; op2val:0x5195; + valaddr_reg:x2; val_offset:2574*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2574*FLEN/8, x6, x4, x5) + +inst_1318: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x0d5 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x195 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4cd5; op2val:0x5195; + valaddr_reg:x2; val_offset:2576*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2576*FLEN/8, x6, x4, x5) + +inst_1319: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x0d5 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x195 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4cd5; op2val:0x5195; + valaddr_reg:x2; val_offset:2578*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2578*FLEN/8, x6, x4, x5) + +inst_1320: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x3d4 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x382 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x43d4; op2val:0x5382; + valaddr_reg:x2; val_offset:2580*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2580*FLEN/8, x6, x4, x5) + +inst_1321: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x3d4 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x382 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x43d4; op2val:0x5382; + valaddr_reg:x2; val_offset:2582*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2582*FLEN/8, x6, x4, x5) + +inst_1322: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x3d4 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x382 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x43d4; op2val:0x5382; + valaddr_reg:x2; val_offset:2584*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2584*FLEN/8, x6, x4, x5) + +inst_1323: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x3d4 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x382 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x43d4; op2val:0x5382; + valaddr_reg:x2; val_offset:2586*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2586*FLEN/8, x6, x4, x5) + +inst_1324: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x3d4 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x382 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x43d4; op2val:0x5382; + valaddr_reg:x2; val_offset:2588*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2588*FLEN/8, x6, x4, x5) + +inst_1325: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x096 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x3b6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4096; op2val:0x53b6; + valaddr_reg:x2; val_offset:2590*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2590*FLEN/8, x6, x4, x5) + +inst_1326: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x096 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x3b6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4096; op2val:0x53b6; + valaddr_reg:x2; val_offset:2592*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2592*FLEN/8, x6, x4, x5) + +inst_1327: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x096 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x3b6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4096; op2val:0x53b6; + valaddr_reg:x2; val_offset:2594*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2594*FLEN/8, x6, x4, x5) + +inst_1328: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x096 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x3b6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4096; op2val:0x53b6; + valaddr_reg:x2; val_offset:2596*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2596*FLEN/8, x6, x4, x5) + +inst_1329: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x096 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x3b6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4096; op2val:0x53b6; + valaddr_reg:x2; val_offset:2598*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2598*FLEN/8, x6, x4, x5) + +inst_1330: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x19c and fs2 == 0 and fe2 == 0x14 and fm2 == 0x34c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x459c; op2val:0x534c; + valaddr_reg:x2; val_offset:2600*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2600*FLEN/8, x6, x4, x5) + +inst_1331: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x19c and fs2 == 0 and fe2 == 0x14 and fm2 == 0x34c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x459c; op2val:0x534c; + valaddr_reg:x2; val_offset:2602*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2602*FLEN/8, x6, x4, x5) + +inst_1332: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x19c and fs2 == 0 and fe2 == 0x14 and fm2 == 0x34c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x459c; op2val:0x534c; + valaddr_reg:x2; val_offset:2604*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2604*FLEN/8, x6, x4, x5) + +inst_1333: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x19c and fs2 == 0 and fe2 == 0x14 and fm2 == 0x34c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x459c; op2val:0x534c; + valaddr_reg:x2; val_offset:2606*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2606*FLEN/8, x6, x4, x5) + +inst_1334: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x19c and fs2 == 0 and fe2 == 0x14 and fm2 == 0x34c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x459c; op2val:0x534c; + valaddr_reg:x2; val_offset:2608*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2608*FLEN/8, x6, x4, x5) + +inst_1335: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x076 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x313 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5076; op2val:0x4f13; + valaddr_reg:x2; val_offset:2610*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2610*FLEN/8, x6, x4, x5) + +inst_1336: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x076 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x313 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5076; op2val:0x4f13; + valaddr_reg:x2; val_offset:2612*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2612*FLEN/8, x6, x4, x5) + +inst_1337: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x076 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x313 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5076; op2val:0x4f13; + valaddr_reg:x2; val_offset:2614*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2614*FLEN/8, x6, x4, x5) + +inst_1338: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x076 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x313 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5076; op2val:0x4f13; + valaddr_reg:x2; val_offset:2616*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2616*FLEN/8, x6, x4, x5) + +inst_1339: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x076 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x313 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5076; op2val:0x4f13; + valaddr_reg:x2; val_offset:2618*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2618*FLEN/8, x6, x4, x5) + +inst_1340: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x0fb and fs2 == 0 and fe2 == 0x14 and fm2 == 0x2c1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x48fb; op2val:0x52c1; + valaddr_reg:x2; val_offset:2620*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2620*FLEN/8, x6, x4, x5) + +inst_1341: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x0fb and fs2 == 0 and fe2 == 0x14 and fm2 == 0x2c1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x48fb; op2val:0x52c1; + valaddr_reg:x2; val_offset:2622*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2622*FLEN/8, x6, x4, x5) + +inst_1342: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x0fb and fs2 == 0 and fe2 == 0x14 and fm2 == 0x2c1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x48fb; op2val:0x52c1; + valaddr_reg:x2; val_offset:2624*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2624*FLEN/8, x6, x4, x5) + +inst_1343: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x0fb and fs2 == 0 and fe2 == 0x14 and fm2 == 0x2c1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x48fb; op2val:0x52c1; + valaddr_reg:x2; val_offset:2626*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2626*FLEN/8, x6, x4, x5) + +inst_1344: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x0fb and fs2 == 0 and fe2 == 0x14 and fm2 == 0x2c1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x48fb; op2val:0x52c1; + valaddr_reg:x2; val_offset:2628*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2628*FLEN/8, x6, x4, x5) + +inst_1345: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x124 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x1b8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5124; op2val:0x4db8; + valaddr_reg:x2; val_offset:2630*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2630*FLEN/8, x6, x4, x5) + +inst_1346: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x124 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x1b8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5124; op2val:0x4db8; + valaddr_reg:x2; val_offset:2632*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2632*FLEN/8, x6, x4, x5) + +inst_1347: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x124 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x1b8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5124; op2val:0x4db8; + valaddr_reg:x2; val_offset:2634*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2634*FLEN/8, x6, x4, x5) + +inst_1348: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x124 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x1b8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5124; op2val:0x4db8; + valaddr_reg:x2; val_offset:2636*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2636*FLEN/8, x6, x4, x5) + +inst_1349: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x124 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x1b8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5124; op2val:0x4db8; + valaddr_reg:x2; val_offset:2638*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2638*FLEN/8, x6, x4, x5) + +inst_1350: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x341 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x05f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4f41; op2val:0x505f; + valaddr_reg:x2; val_offset:2640*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2640*FLEN/8, x6, x4, x5) + +inst_1351: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x341 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x05f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4f41; op2val:0x505f; + valaddr_reg:x2; val_offset:2642*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2642*FLEN/8, x6, x4, x5) + +inst_1352: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x341 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x05f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4f41; op2val:0x505f; + valaddr_reg:x2; val_offset:2644*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2644*FLEN/8, x6, x4, x5) + +inst_1353: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x341 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x05f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4f41; op2val:0x505f; + valaddr_reg:x2; val_offset:2646*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2646*FLEN/8, x6, x4, x5) + +inst_1354: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x341 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x05f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4f41; op2val:0x505f; + valaddr_reg:x2; val_offset:2648*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2648*FLEN/8, x6, x4, x5) + +inst_1355: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x399 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x26f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5399; op2val:0x426f; + valaddr_reg:x2; val_offset:2650*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2650*FLEN/8, x6, x4, x5) + +inst_1356: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x399 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x26f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5399; op2val:0x426f; + valaddr_reg:x2; val_offset:2652*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2652*FLEN/8, x6, x4, x5) + +inst_1357: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x399 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x26f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5399; op2val:0x426f; + valaddr_reg:x2; val_offset:2654*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2654*FLEN/8, x6, x4, x5) + +inst_1358: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x399 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x26f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5399; op2val:0x426f; + valaddr_reg:x2; val_offset:2656*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2656*FLEN/8, x6, x4, x5) + +inst_1359: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x399 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x26f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5399; op2val:0x426f; + valaddr_reg:x2; val_offset:2658*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2658*FLEN/8, x6, x4, x5) + +inst_1360: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x2af and fs2 == 0 and fe2 == 0x14 and fm2 == 0x0a8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4eaf; op2val:0x50a8; + valaddr_reg:x2; val_offset:2660*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2660*FLEN/8, x6, x4, x5) + +inst_1361: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x2af and fs2 == 0 and fe2 == 0x14 and fm2 == 0x0a8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4eaf; op2val:0x50a8; + valaddr_reg:x2; val_offset:2662*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2662*FLEN/8, x6, x4, x5) + +inst_1362: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x2af and fs2 == 0 and fe2 == 0x14 and fm2 == 0x0a8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4eaf; op2val:0x50a8; + valaddr_reg:x2; val_offset:2664*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2664*FLEN/8, x6, x4, x5) + +inst_1363: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x2af and fs2 == 0 and fe2 == 0x14 and fm2 == 0x0a8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4eaf; op2val:0x50a8; + valaddr_reg:x2; val_offset:2666*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2666*FLEN/8, x6, x4, x5) + +inst_1364: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x2af and fs2 == 0 and fe2 == 0x14 and fm2 == 0x0a8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4eaf; op2val:0x50a8; + valaddr_reg:x2; val_offset:2668*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2668*FLEN/8, x6, x4, x5) + +inst_1365: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1dc and fs2 == 0 and fe2 == 0x13 and fm2 == 0x048 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x51dc; op2val:0x4c48; + valaddr_reg:x2; val_offset:2670*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2670*FLEN/8, x6, x4, x5) + +inst_1366: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1dc and fs2 == 0 and fe2 == 0x13 and fm2 == 0x048 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x51dc; op2val:0x4c48; + valaddr_reg:x2; val_offset:2672*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2672*FLEN/8, x6, x4, x5) + +inst_1367: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1dc and fs2 == 0 and fe2 == 0x13 and fm2 == 0x048 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x51dc; op2val:0x4c48; + valaddr_reg:x2; val_offset:2674*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2674*FLEN/8, x6, x4, x5) + +inst_1368: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1dc and fs2 == 0 and fe2 == 0x13 and fm2 == 0x048 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x51dc; op2val:0x4c48; + valaddr_reg:x2; val_offset:2676*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2676*FLEN/8, x6, x4, x5) + +inst_1369: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1dc and fs2 == 0 and fe2 == 0x13 and fm2 == 0x048 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x51dc; op2val:0x4c48; + valaddr_reg:x2; val_offset:2678*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2678*FLEN/8, x6, x4, x5) + +inst_1370: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x2ed and fs2 == 0 and fe2 == 0x14 and fm2 == 0x244 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4aed; op2val:0x5244; + valaddr_reg:x2; val_offset:2680*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2680*FLEN/8, x6, x4, x5) + +inst_1371: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x2ed and fs2 == 0 and fe2 == 0x14 and fm2 == 0x244 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4aed; op2val:0x5244; + valaddr_reg:x2; val_offset:2682*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2682*FLEN/8, x6, x4, x5) + +inst_1372: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x2ed and fs2 == 0 and fe2 == 0x14 and fm2 == 0x244 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4aed; op2val:0x5244; + valaddr_reg:x2; val_offset:2684*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2684*FLEN/8, x6, x4, x5) + +inst_1373: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x2ed and fs2 == 0 and fe2 == 0x14 and fm2 == 0x244 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4aed; op2val:0x5244; + valaddr_reg:x2; val_offset:2686*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2686*FLEN/8, x6, x4, x5) + +inst_1374: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x2ed and fs2 == 0 and fe2 == 0x14 and fm2 == 0x244 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4aed; op2val:0x5244; + valaddr_reg:x2; val_offset:2688*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2688*FLEN/8, x6, x4, x5) + +inst_1375: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3aa and fs2 == 0 and fe2 == 0x14 and fm2 == 0x02a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4faa; op2val:0x502a; + valaddr_reg:x2; val_offset:2690*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2690*FLEN/8, x6, x4, x5) + +inst_1376: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3aa and fs2 == 0 and fe2 == 0x14 and fm2 == 0x02a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4faa; op2val:0x502a; + valaddr_reg:x2; val_offset:2692*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2692*FLEN/8, x6, x4, x5) + +inst_1377: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3aa and fs2 == 0 and fe2 == 0x14 and fm2 == 0x02a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4faa; op2val:0x502a; + valaddr_reg:x2; val_offset:2694*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2694*FLEN/8, x6, x4, x5) + +inst_1378: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3aa and fs2 == 0 and fe2 == 0x14 and fm2 == 0x02a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4faa; op2val:0x502a; + valaddr_reg:x2; val_offset:2696*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2696*FLEN/8, x6, x4, x5) + +inst_1379: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3aa and fs2 == 0 and fe2 == 0x14 and fm2 == 0x02a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4faa; op2val:0x502a; + valaddr_reg:x2; val_offset:2698*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2698*FLEN/8, x6, x4, x5) + +inst_1380: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x265 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x269 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5265; op2val:0x4a69; + valaddr_reg:x2; val_offset:2700*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2700*FLEN/8, x6, x4, x5) + +inst_1381: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x265 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x269 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5265; op2val:0x4a69; + valaddr_reg:x2; val_offset:2702*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2702*FLEN/8, x6, x4, x5) + +inst_1382: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x265 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x269 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5265; op2val:0x4a69; + valaddr_reg:x2; val_offset:2704*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2704*FLEN/8, x6, x4, x5) + +inst_1383: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x265 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x269 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5265; op2val:0x4a69; + valaddr_reg:x2; val_offset:2706*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2706*FLEN/8, x6, x4, x5) + +inst_1384: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x265 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x269 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5265; op2val:0x4a69; + valaddr_reg:x2; val_offset:2708*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2708*FLEN/8, x6, x4, x5) + +inst_1385: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x085 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x2f5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5085; op2val:0x4ef5; + valaddr_reg:x2; val_offset:2710*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2710*FLEN/8, x6, x4, x5) + +inst_1386: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x085 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x2f5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5085; op2val:0x4ef5; + valaddr_reg:x2; val_offset:2712*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2712*FLEN/8, x6, x4, x5) + +inst_1387: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x085 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x2f5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5085; op2val:0x4ef5; + valaddr_reg:x2; val_offset:2714*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2714*FLEN/8, x6, x4, x5) + +inst_1388: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x085 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x2f5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5085; op2val:0x4ef5; + valaddr_reg:x2; val_offset:2716*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2716*FLEN/8, x6, x4, x5) + +inst_1389: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x085 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x2f5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5085; op2val:0x4ef5; + valaddr_reg:x2; val_offset:2718*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2718*FLEN/8, x6, x4, x5) + +inst_1390: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x264 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x270 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5264; op2val:0x4a70; + valaddr_reg:x2; val_offset:2720*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2720*FLEN/8, x6, x4, x5) + +inst_1391: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x264 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x270 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5264; op2val:0x4a70; + valaddr_reg:x2; val_offset:2722*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2722*FLEN/8, x6, x4, x5) + +inst_1392: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x264 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x270 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5264; op2val:0x4a70; + valaddr_reg:x2; val_offset:2724*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2724*FLEN/8, x6, x4, x5) + +inst_1393: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x264 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x270 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5264; op2val:0x4a70; + valaddr_reg:x2; val_offset:2726*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2726*FLEN/8, x6, x4, x5) + +inst_1394: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x264 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x270 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5264; op2val:0x4a70; + valaddr_reg:x2; val_offset:2728*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2728*FLEN/8, x6, x4, x5) + +inst_1395: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x288 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x0bc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4e88; op2val:0x50bc; + valaddr_reg:x2; val_offset:2730*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2730*FLEN/8, x6, x4, x5) + +inst_1396: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x288 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x0bc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4e88; op2val:0x50bc; + valaddr_reg:x2; val_offset:2732*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2732*FLEN/8, x6, x4, x5) + +inst_1397: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x288 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x0bc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4e88; op2val:0x50bc; + valaddr_reg:x2; val_offset:2734*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2734*FLEN/8, x6, x4, x5) + +inst_1398: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x288 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x0bc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4e88; op2val:0x50bc; + valaddr_reg:x2; val_offset:2736*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2736*FLEN/8, x6, x4, x5) + +inst_1399: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x288 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x0bc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4e88; op2val:0x50bc; + valaddr_reg:x2; val_offset:2738*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2738*FLEN/8, x6, x4, x5) + +inst_1400: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x30c and fs2 == 0 and fe2 == 0x14 and fm2 == 0x079 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4f0c; op2val:0x5079; + valaddr_reg:x2; val_offset:2740*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2740*FLEN/8, x6, x4, x5) + +inst_1401: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x30c and fs2 == 0 and fe2 == 0x14 and fm2 == 0x079 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4f0c; op2val:0x5079; + valaddr_reg:x2; val_offset:2742*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2742*FLEN/8, x6, x4, x5) + +inst_1402: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x30c and fs2 == 0 and fe2 == 0x14 and fm2 == 0x079 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4f0c; op2val:0x5079; + valaddr_reg:x2; val_offset:2744*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2744*FLEN/8, x6, x4, x5) + +inst_1403: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x30c and fs2 == 0 and fe2 == 0x14 and fm2 == 0x079 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4f0c; op2val:0x5079; + valaddr_reg:x2; val_offset:2746*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2746*FLEN/8, x6, x4, x5) + +inst_1404: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x30c and fs2 == 0 and fe2 == 0x14 and fm2 == 0x079 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4f0c; op2val:0x5079; + valaddr_reg:x2; val_offset:2748*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2748*FLEN/8, x6, x4, x5) + +inst_1405: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x364 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x04e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4f64; op2val:0x504e; + valaddr_reg:x2; val_offset:2750*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2750*FLEN/8, x6, x4, x5) + +inst_1406: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x364 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x04e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4f64; op2val:0x504e; + valaddr_reg:x2; val_offset:2752*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2752*FLEN/8, x6, x4, x5) + +inst_1407: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x364 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x04e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4f64; op2val:0x504e; + valaddr_reg:x2; val_offset:2754*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2754*FLEN/8, x6, x4, x5) + +inst_1408: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x364 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x04e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4f64; op2val:0x504e; + valaddr_reg:x2; val_offset:2756*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2756*FLEN/8, x6, x4, x5) + +inst_1409: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x364 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x04e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4f64; op2val:0x504e; + valaddr_reg:x2; val_offset:2758*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2758*FLEN/8, x6, x4, x5) + +inst_1410: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x0fd and fs2 == 0 and fe2 == 0x14 and fm2 == 0x2c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x48fd; op2val:0x52c0; + valaddr_reg:x2; val_offset:2760*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2760*FLEN/8, x6, x4, x5) + +inst_1411: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x0fd and fs2 == 0 and fe2 == 0x14 and fm2 == 0x2c0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x48fd; op2val:0x52c0; + valaddr_reg:x2; val_offset:2762*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2762*FLEN/8, x6, x4, x5) + +inst_1412: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x0fd and fs2 == 0 and fe2 == 0x14 and fm2 == 0x2c0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x48fd; op2val:0x52c0; + valaddr_reg:x2; val_offset:2764*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2764*FLEN/8, x6, x4, x5) + +inst_1413: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x0fd and fs2 == 0 and fe2 == 0x14 and fm2 == 0x2c0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x48fd; op2val:0x52c0; + valaddr_reg:x2; val_offset:2766*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2766*FLEN/8, x6, x4, x5) + +inst_1414: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x0fd and fs2 == 0 and fe2 == 0x14 and fm2 == 0x2c0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x48fd; op2val:0x52c0; + valaddr_reg:x2; val_offset:2768*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2768*FLEN/8, x6, x4, x5) + +inst_1415: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x125 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x1b6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5125; op2val:0x4db6; + valaddr_reg:x2; val_offset:2770*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2770*FLEN/8, x6, x4, x5) + +inst_1416: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x125 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x1b6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5125; op2val:0x4db6; + valaddr_reg:x2; val_offset:2772*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2772*FLEN/8, x6, x4, x5) + +inst_1417: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x125 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x1b6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5125; op2val:0x4db6; + valaddr_reg:x2; val_offset:2774*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2774*FLEN/8, x6, x4, x5) + +inst_1418: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x125 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x1b6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5125; op2val:0x4db6; + valaddr_reg:x2; val_offset:2776*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2776*FLEN/8, x6, x4, x5) + +inst_1419: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x125 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x1b6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5125; op2val:0x4db6; + valaddr_reg:x2; val_offset:2778*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2778*FLEN/8, x6, x4, x5) + +inst_1420: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x2ea and fs2 == 0 and fe2 == 0x14 and fm2 == 0x245 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4aea; op2val:0x5245; + valaddr_reg:x2; val_offset:2780*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2780*FLEN/8, x6, x4, x5) + +inst_1421: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x2ea and fs2 == 0 and fe2 == 0x14 and fm2 == 0x245 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4aea; op2val:0x5245; + valaddr_reg:x2; val_offset:2782*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2782*FLEN/8, x6, x4, x5) + +inst_1422: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x2ea and fs2 == 0 and fe2 == 0x14 and fm2 == 0x245 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4aea; op2val:0x5245; + valaddr_reg:x2; val_offset:2784*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2784*FLEN/8, x6, x4, x5) + +inst_1423: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x2ea and fs2 == 0 and fe2 == 0x14 and fm2 == 0x245 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4aea; op2val:0x5245; + valaddr_reg:x2; val_offset:2786*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2786*FLEN/8, x6, x4, x5) + +inst_1424: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x2ea and fs2 == 0 and fe2 == 0x14 and fm2 == 0x245 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4aea; op2val:0x5245; + valaddr_reg:x2; val_offset:2788*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2788*FLEN/8, x6, x4, x5) + +inst_1425: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1a1 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x0bd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x51a1; op2val:0x4cbd; + valaddr_reg:x2; val_offset:2790*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2790*FLEN/8, x6, x4, x5) + +inst_1426: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1a1 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x0bd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x51a1; op2val:0x4cbd; + valaddr_reg:x2; val_offset:2792*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2792*FLEN/8, x6, x4, x5) + +inst_1427: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1a1 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x0bd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x51a1; op2val:0x4cbd; + valaddr_reg:x2; val_offset:2794*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2794*FLEN/8, x6, x4, x5) + +inst_1428: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1a1 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x0bd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x51a1; op2val:0x4cbd; + valaddr_reg:x2; val_offset:2796*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2796*FLEN/8, x6, x4, x5) + +inst_1429: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1a1 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x0bd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x51a1; op2val:0x4cbd; + valaddr_reg:x2; val_offset:2798*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2798*FLEN/8, x6, x4, x5) + +inst_1430: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x1f5 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x3d0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3df5; op2val:0x53d0; + valaddr_reg:x2; val_offset:2800*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2800*FLEN/8, x6, x4, x5) + +inst_1431: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x1f5 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x3d0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3df5; op2val:0x53d0; + valaddr_reg:x2; val_offset:2802*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2802*FLEN/8, x6, x4, x5) + +inst_1432: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x1f5 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x3d0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3df5; op2val:0x53d0; + valaddr_reg:x2; val_offset:2804*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2804*FLEN/8, x6, x4, x5) + +inst_1433: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x1f5 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x3d0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3df5; op2val:0x53d0; + valaddr_reg:x2; val_offset:2806*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2806*FLEN/8, x6, x4, x5) +RVTEST_SIGBASE(x4,signature_x4_11) + +inst_1434: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x1f5 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x3d0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3df5; op2val:0x53d0; + valaddr_reg:x2; val_offset:2808*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2808*FLEN/8, x6, x4, x5) + +inst_1435: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x016 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x32c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3416; op2val:0xb32c; + valaddr_reg:x2; val_offset:2810*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2810*FLEN/8, x6, x4, x5) + +inst_1436: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x016 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x32c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3416; op2val:0xb32c; + valaddr_reg:x2; val_offset:2812*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2812*FLEN/8, x6, x4, x5) + +inst_1437: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x016 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x32c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3416; op2val:0xb32c; + valaddr_reg:x2; val_offset:2814*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2814*FLEN/8, x6, x4, x5) + +inst_1438: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x016 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x32c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3416; op2val:0xb32c; + valaddr_reg:x2; val_offset:2816*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2816*FLEN/8, x6, x4, x5) + +inst_1439: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x016 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x32c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3416; op2val:0xb32c; + valaddr_reg:x2; val_offset:2818*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2818*FLEN/8, x6, x4, x5) + +inst_1440: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x38c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x30c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x378c; op2val:0xb70c; + valaddr_reg:x2; val_offset:2820*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2820*FLEN/8, x6, x4, x5) + +inst_1441: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x38c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x30c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x378c; op2val:0xb70c; + valaddr_reg:x2; val_offset:2822*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2822*FLEN/8, x6, x4, x5) + +inst_1442: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x38c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x30c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x378c; op2val:0xb70c; + valaddr_reg:x2; val_offset:2824*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2824*FLEN/8, x6, x4, x5) + +inst_1443: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x38c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x30c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x378c; op2val:0xb70c; + valaddr_reg:x2; val_offset:2826*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2826*FLEN/8, x6, x4, x5) + +inst_1444: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x38c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x30c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x378c; op2val:0xb70c; + valaddr_reg:x2; val_offset:2828*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2828*FLEN/8, x6, x4, x5) + +inst_1445: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x10d and fs2 == 1 and fe2 == 0x0d and fm2 == 0x08d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x350d; op2val:0xb48d; + valaddr_reg:x2; val_offset:2830*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2830*FLEN/8, x6, x4, x5) + +inst_1446: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x10d and fs2 == 1 and fe2 == 0x0d and fm2 == 0x08d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x350d; op2val:0xb48d; + valaddr_reg:x2; val_offset:2832*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2832*FLEN/8, x6, x4, x5) + +inst_1447: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x10d and fs2 == 1 and fe2 == 0x0d and fm2 == 0x08d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x350d; op2val:0xb48d; + valaddr_reg:x2; val_offset:2834*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2834*FLEN/8, x6, x4, x5) + +inst_1448: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x10d and fs2 == 1 and fe2 == 0x0d and fm2 == 0x08d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x350d; op2val:0xb48d; + valaddr_reg:x2; val_offset:2836*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2836*FLEN/8, x6, x4, x5) + +inst_1449: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x10d and fs2 == 1 and fe2 == 0x0d and fm2 == 0x08d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x350d; op2val:0xb48d; + valaddr_reg:x2; val_offset:2838*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2838*FLEN/8, x6, x4, x5) + +inst_1450: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x17c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x357c; op2val:0xb4fc; + valaddr_reg:x2; val_offset:2840*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2840*FLEN/8, x6, x4, x5) + +inst_1451: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x17c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0fc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x357c; op2val:0xb4fc; + valaddr_reg:x2; val_offset:2842*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2842*FLEN/8, x6, x4, x5) + +inst_1452: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x17c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0fc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x357c; op2val:0xb4fc; + valaddr_reg:x2; val_offset:2844*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2844*FLEN/8, x6, x4, x5) + +inst_1453: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x17c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0fc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x357c; op2val:0xb4fc; + valaddr_reg:x2; val_offset:2846*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2846*FLEN/8, x6, x4, x5) + +inst_1454: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x17c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0fc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x357c; op2val:0xb4fc; + valaddr_reg:x2; val_offset:2848*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2848*FLEN/8, x6, x4, x5) + +inst_1455: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x232 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1f2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a32; op2val:0xb9f2; + valaddr_reg:x2; val_offset:2850*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2850*FLEN/8, x6, x4, x5) + +inst_1456: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x232 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1f2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a32; op2val:0xb9f2; + valaddr_reg:x2; val_offset:2852*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2852*FLEN/8, x6, x4, x5) + +inst_1457: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x232 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1f2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a32; op2val:0xb9f2; + valaddr_reg:x2; val_offset:2854*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2854*FLEN/8, x6, x4, x5) + +inst_1458: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x232 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1f2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a32; op2val:0xb9f2; + valaddr_reg:x2; val_offset:2856*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2856*FLEN/8, x6, x4, x5) + +inst_1459: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x232 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1f2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a32; op2val:0xb9f2; + valaddr_reg:x2; val_offset:2858*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2858*FLEN/8, x6, x4, x5) + +inst_1460: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1d4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x194 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x39d4; op2val:0xb994; + valaddr_reg:x2; val_offset:2860*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2860*FLEN/8, x6, x4, x5) + +inst_1461: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1d4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x194 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x39d4; op2val:0xb994; + valaddr_reg:x2; val_offset:2862*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2862*FLEN/8, x6, x4, x5) + +inst_1462: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1d4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x194 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x39d4; op2val:0xb994; + valaddr_reg:x2; val_offset:2864*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2864*FLEN/8, x6, x4, x5) + +inst_1463: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1d4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x194 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x39d4; op2val:0xb994; + valaddr_reg:x2; val_offset:2866*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2866*FLEN/8, x6, x4, x5) + +inst_1464: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1d4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x194 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x39d4; op2val:0xb994; + valaddr_reg:x2; val_offset:2868*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2868*FLEN/8, x6, x4, x5) + +inst_1465: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x310 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2d0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b10; op2val:0xbad0; + valaddr_reg:x2; val_offset:2870*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2870*FLEN/8, x6, x4, x5) + +inst_1466: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x310 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2d0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b10; op2val:0xbad0; + valaddr_reg:x2; val_offset:2872*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2872*FLEN/8, x6, x4, x5) + +inst_1467: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x310 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2d0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b10; op2val:0xbad0; + valaddr_reg:x2; val_offset:2874*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2874*FLEN/8, x6, x4, x5) + +inst_1468: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x310 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2d0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b10; op2val:0xbad0; + valaddr_reg:x2; val_offset:2876*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2876*FLEN/8, x6, x4, x5) + +inst_1469: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x310 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2d0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b10; op2val:0xbad0; + valaddr_reg:x2; val_offset:2878*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2878*FLEN/8, x6, x4, x5) + +inst_1470: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3af and fs2 == 1 and fe2 == 0x0e and fm2 == 0x36f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3baf; op2val:0xbb6f; + valaddr_reg:x2; val_offset:2880*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2880*FLEN/8, x6, x4, x5) + +inst_1471: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3af and fs2 == 1 and fe2 == 0x0e and fm2 == 0x36f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3baf; op2val:0xbb6f; + valaddr_reg:x2; val_offset:2882*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2882*FLEN/8, x6, x4, x5) + +inst_1472: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3af and fs2 == 1 and fe2 == 0x0e and fm2 == 0x36f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3baf; op2val:0xbb6f; + valaddr_reg:x2; val_offset:2884*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2884*FLEN/8, x6, x4, x5) + +inst_1473: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3af and fs2 == 1 and fe2 == 0x0e and fm2 == 0x36f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3baf; op2val:0xbb6f; + valaddr_reg:x2; val_offset:2886*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2886*FLEN/8, x6, x4, x5) + +inst_1474: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3af and fs2 == 1 and fe2 == 0x0e and fm2 == 0x36f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3baf; op2val:0xbb6f; + valaddr_reg:x2; val_offset:2888*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2888*FLEN/8, x6, x4, x5) + +inst_1475: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3d8 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x358 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x37d8; op2val:0xb758; + valaddr_reg:x2; val_offset:2890*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2890*FLEN/8, x6, x4, x5) + +inst_1476: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3d8 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x358 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x37d8; op2val:0xb758; + valaddr_reg:x2; val_offset:2892*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2892*FLEN/8, x6, x4, x5) + +inst_1477: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3d8 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x358 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x37d8; op2val:0xb758; + valaddr_reg:x2; val_offset:2894*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2894*FLEN/8, x6, x4, x5) + +inst_1478: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3d8 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x358 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x37d8; op2val:0xb758; + valaddr_reg:x2; val_offset:2896*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2896*FLEN/8, x6, x4, x5) + +inst_1479: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3d8 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x358 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x37d8; op2val:0xb758; + valaddr_reg:x2; val_offset:2898*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2898*FLEN/8, x6, x4, x5) + +inst_1480: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ed and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0ad and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x38ed; op2val:0xb8ad; + valaddr_reg:x2; val_offset:2900*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2900*FLEN/8, x6, x4, x5) + +inst_1481: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ed and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0ad and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x38ed; op2val:0xb8ad; + valaddr_reg:x2; val_offset:2902*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2902*FLEN/8, x6, x4, x5) + +inst_1482: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ed and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0ad and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x38ed; op2val:0xb8ad; + valaddr_reg:x2; val_offset:2904*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2904*FLEN/8, x6, x4, x5) + +inst_1483: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ed and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0ad and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x38ed; op2val:0xb8ad; + valaddr_reg:x2; val_offset:2906*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2906*FLEN/8, x6, x4, x5) + +inst_1484: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ed and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0ad and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x38ed; op2val:0xb8ad; + valaddr_reg:x2; val_offset:2908*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2908*FLEN/8, x6, x4, x5) + +inst_1485: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x20a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1ca and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a0a; op2val:0xb9ca; + valaddr_reg:x2; val_offset:2910*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2910*FLEN/8, x6, x4, x5) + +inst_1486: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x20a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1ca and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a0a; op2val:0xb9ca; + valaddr_reg:x2; val_offset:2912*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2912*FLEN/8, x6, x4, x5) + +inst_1487: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x20a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1ca and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a0a; op2val:0xb9ca; + valaddr_reg:x2; val_offset:2914*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2914*FLEN/8, x6, x4, x5) + +inst_1488: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x20a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1ca and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a0a; op2val:0xb9ca; + valaddr_reg:x2; val_offset:2916*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2916*FLEN/8, x6, x4, x5) + +inst_1489: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x20a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1ca and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a0a; op2val:0xb9ca; + valaddr_reg:x2; val_offset:2918*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2918*FLEN/8, x6, x4, x5) + +inst_1490: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x04b and fs2 == 1 and fe2 == 0x0c and fm2 == 0x396 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x344b; op2val:0xb396; + valaddr_reg:x2; val_offset:2920*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2920*FLEN/8, x6, x4, x5) + +inst_1491: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x04b and fs2 == 1 and fe2 == 0x0c and fm2 == 0x396 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x344b; op2val:0xb396; + valaddr_reg:x2; val_offset:2922*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2922*FLEN/8, x6, x4, x5) + +inst_1492: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x04b and fs2 == 1 and fe2 == 0x0c and fm2 == 0x396 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x344b; op2val:0xb396; + valaddr_reg:x2; val_offset:2924*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2924*FLEN/8, x6, x4, x5) + +inst_1493: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x04b and fs2 == 1 and fe2 == 0x0c and fm2 == 0x396 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x344b; op2val:0xb396; + valaddr_reg:x2; val_offset:2926*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2926*FLEN/8, x6, x4, x5) + +inst_1494: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x04b and fs2 == 1 and fe2 == 0x0c and fm2 == 0x396 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x344b; op2val:0xb396; + valaddr_reg:x2; val_offset:2928*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2928*FLEN/8, x6, x4, x5) + +inst_1495: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2c5 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x245 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x36c5; op2val:0xb645; + valaddr_reg:x2; val_offset:2930*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2930*FLEN/8, x6, x4, x5) + +inst_1496: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2c5 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x245 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x36c5; op2val:0xb645; + valaddr_reg:x2; val_offset:2932*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2932*FLEN/8, x6, x4, x5) + +inst_1497: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2c5 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x245 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x36c5; op2val:0xb645; + valaddr_reg:x2; val_offset:2934*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2934*FLEN/8, x6, x4, x5) + +inst_1498: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2c5 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x245 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x36c5; op2val:0xb645; + valaddr_reg:x2; val_offset:2936*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2936*FLEN/8, x6, x4, x5) + +inst_1499: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2c5 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x245 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x36c5; op2val:0xb645; + valaddr_reg:x2; val_offset:2938*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2938*FLEN/8, x6, x4, x5) + +inst_1500: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x370 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x270 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3370; op2val:0xb270; + valaddr_reg:x2; val_offset:2940*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2940*FLEN/8, x6, x4, x5) + +inst_1501: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x370 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x270 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3370; op2val:0xb270; + valaddr_reg:x2; val_offset:2942*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2942*FLEN/8, x6, x4, x5) + +inst_1502: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x370 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x270 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3370; op2val:0xb270; + valaddr_reg:x2; val_offset:2944*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2944*FLEN/8, x6, x4, x5) + +inst_1503: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x370 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x270 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3370; op2val:0xb270; + valaddr_reg:x2; val_offset:2946*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2946*FLEN/8, x6, x4, x5) + +inst_1504: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x370 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x270 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3370; op2val:0xb270; + valaddr_reg:x2; val_offset:2948*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2948*FLEN/8, x6, x4, x5) + +inst_1505: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x15d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x11d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x395d; op2val:0xb91d; + valaddr_reg:x2; val_offset:2950*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2950*FLEN/8, x6, x4, x5) + +inst_1506: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x15d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x11d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x395d; op2val:0xb91d; + valaddr_reg:x2; val_offset:2952*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2952*FLEN/8, x6, x4, x5) + +inst_1507: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x15d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x11d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x395d; op2val:0xb91d; + valaddr_reg:x2; val_offset:2954*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2954*FLEN/8, x6, x4, x5) + +inst_1508: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x15d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x11d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x395d; op2val:0xb91d; + valaddr_reg:x2; val_offset:2956*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2956*FLEN/8, x6, x4, x5) + +inst_1509: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x15d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x11d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x395d; op2val:0xb91d; + valaddr_reg:x2; val_offset:2958*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2958*FLEN/8, x6, x4, x5) + +inst_1510: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x211 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1d1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a11; op2val:0xb9d1; + valaddr_reg:x2; val_offset:2960*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2960*FLEN/8, x6, x4, x5) + +inst_1511: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x211 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1d1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a11; op2val:0xb9d1; + valaddr_reg:x2; val_offset:2962*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2962*FLEN/8, x6, x4, x5) + +inst_1512: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x211 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1d1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a11; op2val:0xb9d1; + valaddr_reg:x2; val_offset:2964*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2964*FLEN/8, x6, x4, x5) + +inst_1513: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x211 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1d1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a11; op2val:0xb9d1; + valaddr_reg:x2; val_offset:2966*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2966*FLEN/8, x6, x4, x5) + +inst_1514: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x211 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1d1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a11; op2val:0xb9d1; + valaddr_reg:x2; val_offset:2968*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2968*FLEN/8, x6, x4, x5) + +inst_1515: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2bb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x27b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3abb; op2val:0xba7b; + valaddr_reg:x2; val_offset:2970*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2970*FLEN/8, x6, x4, x5) + +inst_1516: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2bb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x27b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3abb; op2val:0xba7b; + valaddr_reg:x2; val_offset:2972*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2972*FLEN/8, x6, x4, x5) + +inst_1517: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2bb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x27b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3abb; op2val:0xba7b; + valaddr_reg:x2; val_offset:2974*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2974*FLEN/8, x6, x4, x5) + +inst_1518: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2bb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x27b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3abb; op2val:0xba7b; + valaddr_reg:x2; val_offset:2976*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2976*FLEN/8, x6, x4, x5) + +inst_1519: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2bb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x27b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3abb; op2val:0xba7b; + valaddr_reg:x2; val_offset:2978*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2978*FLEN/8, x6, x4, x5) + +inst_1520: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1c1 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x181 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x39c1; op2val:0xb981; + valaddr_reg:x2; val_offset:2980*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2980*FLEN/8, x6, x4, x5) + +inst_1521: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1c1 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x181 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x39c1; op2val:0xb981; + valaddr_reg:x2; val_offset:2982*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2982*FLEN/8, x6, x4, x5) + +inst_1522: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1c1 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x181 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x39c1; op2val:0xb981; + valaddr_reg:x2; val_offset:2984*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2984*FLEN/8, x6, x4, x5) + +inst_1523: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1c1 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x181 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x39c1; op2val:0xb981; + valaddr_reg:x2; val_offset:2986*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2986*FLEN/8, x6, x4, x5) + +inst_1524: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1c1 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x181 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x39c1; op2val:0xb981; + valaddr_reg:x2; val_offset:2988*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2988*FLEN/8, x6, x4, x5) + +inst_1525: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x31a and fs2 == 1 and fe2 == 0x0d and fm2 == 0x29a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x371a; op2val:0xb69a; + valaddr_reg:x2; val_offset:2990*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 2990*FLEN/8, x6, x4, x5) + +inst_1526: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x31a and fs2 == 1 and fe2 == 0x0d and fm2 == 0x29a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x371a; op2val:0xb69a; + valaddr_reg:x2; val_offset:2992*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 2992*FLEN/8, x6, x4, x5) + +inst_1527: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x31a and fs2 == 1 and fe2 == 0x0d and fm2 == 0x29a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x371a; op2val:0xb69a; + valaddr_reg:x2; val_offset:2994*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 2994*FLEN/8, x6, x4, x5) + +inst_1528: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x31a and fs2 == 1 and fe2 == 0x0d and fm2 == 0x29a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x371a; op2val:0xb69a; + valaddr_reg:x2; val_offset:2996*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 2996*FLEN/8, x6, x4, x5) + +inst_1529: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x31a and fs2 == 1 and fe2 == 0x0d and fm2 == 0x29a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x371a; op2val:0xb69a; + valaddr_reg:x2; val_offset:2998*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 2998*FLEN/8, x6, x4, x5) + +inst_1530: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3c3 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x343 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x37c3; op2val:0xb743; + valaddr_reg:x2; val_offset:3000*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 3000*FLEN/8, x6, x4, x5) + +inst_1531: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3c3 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x343 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x37c3; op2val:0xb743; + valaddr_reg:x2; val_offset:3002*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 3002*FLEN/8, x6, x4, x5) + +inst_1532: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3c3 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x343 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x37c3; op2val:0xb743; + valaddr_reg:x2; val_offset:3004*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 3004*FLEN/8, x6, x4, x5) + +inst_1533: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3c3 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x343 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x37c3; op2val:0xb743; + valaddr_reg:x2; val_offset:3006*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 3006*FLEN/8, x6, x4, x5) + +inst_1534: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3c3 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x343 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x37c3; op2val:0xb743; + valaddr_reg:x2; val_offset:3008*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 3008*FLEN/8, x6, x4, x5) + +inst_1535: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x229 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1a9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3629; op2val:0xb5a9; + valaddr_reg:x2; val_offset:3010*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 3010*FLEN/8, x6, x4, x5) + +inst_1536: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x229 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1a9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3629; op2val:0xb5a9; + valaddr_reg:x2; val_offset:3012*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 3012*FLEN/8, x6, x4, x5) + +inst_1537: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x229 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1a9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3629; op2val:0xb5a9; + valaddr_reg:x2; val_offset:3014*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 3014*FLEN/8, x6, x4, x5) + +inst_1538: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x229 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1a9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3629; op2val:0xb5a9; + valaddr_reg:x2; val_offset:3016*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 3016*FLEN/8, x6, x4, x5) + +inst_1539: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x229 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1a9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3629; op2val:0xb5a9; + valaddr_reg:x2; val_offset:3018*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 3018*FLEN/8, x6, x4, x5) + +inst_1540: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3dd and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2dd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x33dd; op2val:0xb2dd; + valaddr_reg:x2; val_offset:3020*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 3020*FLEN/8, x6, x4, x5) + +inst_1541: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3dd and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2dd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x33dd; op2val:0xb2dd; + valaddr_reg:x2; val_offset:3022*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 3022*FLEN/8, x6, x4, x5) + +inst_1542: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3dd and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2dd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x33dd; op2val:0xb2dd; + valaddr_reg:x2; val_offset:3024*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 3024*FLEN/8, x6, x4, x5) + +inst_1543: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3dd and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2dd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x33dd; op2val:0xb2dd; + valaddr_reg:x2; val_offset:3026*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 3026*FLEN/8, x6, x4, x5) + +inst_1544: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3dd and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2dd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x33dd; op2val:0xb2dd; + valaddr_reg:x2; val_offset:3028*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 3028*FLEN/8, x6, x4, x5) + +inst_1545: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1bc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x17c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x39bc; op2val:0xb97c; + valaddr_reg:x2; val_offset:3030*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 3030*FLEN/8, x6, x4, x5) + +inst_1546: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1bc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x17c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x39bc; op2val:0xb97c; + valaddr_reg:x2; val_offset:3032*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 3032*FLEN/8, x6, x4, x5) + +inst_1547: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1bc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x17c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x39bc; op2val:0xb97c; + valaddr_reg:x2; val_offset:3034*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 3034*FLEN/8, x6, x4, x5) + +inst_1548: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1bc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x17c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x39bc; op2val:0xb97c; + valaddr_reg:x2; val_offset:3036*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 3036*FLEN/8, x6, x4, x5) + +inst_1549: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1bc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x17c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x39bc; op2val:0xb97c; + valaddr_reg:x2; val_offset:3038*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 3038*FLEN/8, x6, x4, x5) + +inst_1550: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x240 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3640; op2val:0xb5c0; + valaddr_reg:x2; val_offset:3040*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 3040*FLEN/8, x6, x4, x5) + +inst_1551: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x240 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1c0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3640; op2val:0xb5c0; + valaddr_reg:x2; val_offset:3042*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 3042*FLEN/8, x6, x4, x5) + +inst_1552: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x240 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1c0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3640; op2val:0xb5c0; + valaddr_reg:x2; val_offset:3044*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 3044*FLEN/8, x6, x4, x5) + +inst_1553: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x240 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1c0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3640; op2val:0xb5c0; + valaddr_reg:x2; val_offset:3046*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 3046*FLEN/8, x6, x4, x5) + +inst_1554: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x240 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1c0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3640; op2val:0xb5c0; + valaddr_reg:x2; val_offset:3048*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 3048*FLEN/8, x6, x4, x5) + +inst_1555: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x132 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0b2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3532; op2val:0xb4b2; + valaddr_reg:x2; val_offset:3050*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 3050*FLEN/8, x6, x4, x5) + +inst_1556: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x132 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0b2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3532; op2val:0xb4b2; + valaddr_reg:x2; val_offset:3052*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 3052*FLEN/8, x6, x4, x5) + +inst_1557: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x132 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0b2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3532; op2val:0xb4b2; + valaddr_reg:x2; val_offset:3054*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 3054*FLEN/8, x6, x4, x5) + +inst_1558: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x132 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0b2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3532; op2val:0xb4b2; + valaddr_reg:x2; val_offset:3056*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 3056*FLEN/8, x6, x4, x5) + +inst_1559: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x132 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0b2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3532; op2val:0xb4b2; + valaddr_reg:x2; val_offset:3058*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 3058*FLEN/8, x6, x4, x5) + +inst_1560: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2d6 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x256 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x36d6; op2val:0xb656; + valaddr_reg:x2; val_offset:3060*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 3060*FLEN/8, x6, x4, x5) + +inst_1561: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2d6 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x256 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x36d6; op2val:0xb656; + valaddr_reg:x2; val_offset:3062*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 3062*FLEN/8, x6, x4, x5) +RVTEST_SIGBASE(x4,signature_x4_12) + +inst_1562: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2d6 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x256 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x36d6; op2val:0xb656; + valaddr_reg:x2; val_offset:3064*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 3064*FLEN/8, x6, x4, x5) + +inst_1563: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2d6 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x256 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x36d6; op2val:0xb656; + valaddr_reg:x2; val_offset:3066*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 3066*FLEN/8, x6, x4, x5) + +inst_1564: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2d6 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x256 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x36d6; op2val:0xb656; + valaddr_reg:x2; val_offset:3068*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 3068*FLEN/8, x6, x4, x5) + +inst_1565: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a4 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x124 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x35a4; op2val:0xb524; + valaddr_reg:x2; val_offset:3070*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 3070*FLEN/8, x6, x4, x5) + +inst_1566: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a4 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x124 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x35a4; op2val:0xb524; + valaddr_reg:x2; val_offset:3072*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 3072*FLEN/8, x6, x4, x5) + +inst_1567: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a4 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x124 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x35a4; op2val:0xb524; + valaddr_reg:x2; val_offset:3074*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 3074*FLEN/8, x6, x4, x5) + +inst_1568: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a4 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x124 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x35a4; op2val:0xb524; + valaddr_reg:x2; val_offset:3076*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 3076*FLEN/8, x6, x4, x5) + +inst_1569: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a4 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x124 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x35a4; op2val:0xb524; + valaddr_reg:x2; val_offset:3078*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 3078*FLEN/8, x6, x4, x5) + +inst_1570: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x056 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x016 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3856; op2val:0xb816; + valaddr_reg:x2; val_offset:3080*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 3080*FLEN/8, x6, x4, x5) + +inst_1571: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x056 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x016 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3856; op2val:0xb816; + valaddr_reg:x2; val_offset:3082*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 3082*FLEN/8, x6, x4, x5) + +inst_1572: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x056 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x016 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3856; op2val:0xb816; + valaddr_reg:x2; val_offset:3084*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 3084*FLEN/8, x6, x4, x5) + +inst_1573: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x056 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x016 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3856; op2val:0xb816; + valaddr_reg:x2; val_offset:3086*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 3086*FLEN/8, x6, x4, x5) + +inst_1574: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x056 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x016 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3856; op2val:0xb816; + valaddr_reg:x2; val_offset:3088*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 3088*FLEN/8, x6, x4, x5) + +inst_1575: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x04e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x00e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x384e; op2val:0xb80e; + valaddr_reg:x2; val_offset:3090*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 3090*FLEN/8, x6, x4, x5) + +inst_1576: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x04e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x00e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x384e; op2val:0xb80e; + valaddr_reg:x2; val_offset:3092*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 3092*FLEN/8, x6, x4, x5) + +inst_1577: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x04e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x00e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x384e; op2val:0xb80e; + valaddr_reg:x2; val_offset:3094*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 3094*FLEN/8, x6, x4, x5) + +inst_1578: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x04e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x00e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x384e; op2val:0xb80e; + valaddr_reg:x2; val_offset:3096*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 3096*FLEN/8, x6, x4, x5) + +inst_1579: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x04e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x00e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x384e; op2val:0xb80e; + valaddr_reg:x2; val_offset:3098*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 3098*FLEN/8, x6, x4, x5) + +inst_1580: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x188 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x148 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3988; op2val:0xb948; + valaddr_reg:x2; val_offset:3100*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 3100*FLEN/8, x6, x4, x5) + +inst_1581: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x188 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x148 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3988; op2val:0xb948; + valaddr_reg:x2; val_offset:3102*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 3102*FLEN/8, x6, x4, x5) + +inst_1582: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x188 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x148 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3988; op2val:0xb948; + valaddr_reg:x2; val_offset:3104*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 3104*FLEN/8, x6, x4, x5) + +inst_1583: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x188 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x148 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3988; op2val:0xb948; + valaddr_reg:x2; val_offset:3106*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 3106*FLEN/8, x6, x4, x5) + +inst_1584: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x188 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x148 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3988; op2val:0xb948; + valaddr_reg:x2; val_offset:3108*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 3108*FLEN/8, x6, x4, x5) + +inst_1585: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x388 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x348 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b88; op2val:0xbb48; + valaddr_reg:x2; val_offset:3110*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 3110*FLEN/8, x6, x4, x5) + +inst_1586: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x388 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x348 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b88; op2val:0xbb48; + valaddr_reg:x2; val_offset:3112*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 3112*FLEN/8, x6, x4, x5) + +inst_1587: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x388 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x348 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b88; op2val:0xbb48; + valaddr_reg:x2; val_offset:3114*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 3114*FLEN/8, x6, x4, x5) + +inst_1588: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x388 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x348 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b88; op2val:0xbb48; + valaddr_reg:x2; val_offset:3116*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 3116*FLEN/8, x6, x4, x5) + +inst_1589: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x388 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x348 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b88; op2val:0xbb48; + valaddr_reg:x2; val_offset:3118*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 3118*FLEN/8, x6, x4, x5) + +inst_1590: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x073 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3e6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3473; op2val:0xb3e6; + valaddr_reg:x2; val_offset:3120*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 3120*FLEN/8, x6, x4, x5) + +inst_1591: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x073 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3e6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3473; op2val:0xb3e6; + valaddr_reg:x2; val_offset:3122*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 3122*FLEN/8, x6, x4, x5) + +inst_1592: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x073 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3e6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3473; op2val:0xb3e6; + valaddr_reg:x2; val_offset:3124*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 3124*FLEN/8, x6, x4, x5) + +inst_1593: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x073 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3e6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3473; op2val:0xb3e6; + valaddr_reg:x2; val_offset:3126*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 3126*FLEN/8, x6, x4, x5) + +inst_1594: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x073 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3e6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3473; op2val:0xb3e6; + valaddr_reg:x2; val_offset:3128*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 3128*FLEN/8, x6, x4, x5) + +inst_1595: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x25f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1df and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x365f; op2val:0xb5df; + valaddr_reg:x2; val_offset:3130*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 3130*FLEN/8, x6, x4, x5) + +inst_1596: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x25f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1df and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x365f; op2val:0xb5df; + valaddr_reg:x2; val_offset:3132*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 3132*FLEN/8, x6, x4, x5) + +inst_1597: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x25f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1df and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x365f; op2val:0xb5df; + valaddr_reg:x2; val_offset:3134*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 3134*FLEN/8, x6, x4, x5) + +inst_1598: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x25f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1df and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x365f; op2val:0xb5df; + valaddr_reg:x2; val_offset:3136*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 3136*FLEN/8, x6, x4, x5) + +inst_1599: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x25f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1df and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x365f; op2val:0xb5df; + valaddr_reg:x2; val_offset:3138*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 3138*FLEN/8, x6, x4, x5) + +inst_1600: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x058 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x018 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3858; op2val:0xb818; + valaddr_reg:x2; val_offset:3140*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 3140*FLEN/8, x6, x4, x5) + +inst_1601: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x058 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x018 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3858; op2val:0xb818; + valaddr_reg:x2; val_offset:3142*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 3142*FLEN/8, x6, x4, x5) + +inst_1602: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x058 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x018 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3858; op2val:0xb818; + valaddr_reg:x2; val_offset:3144*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 3144*FLEN/8, x6, x4, x5) + +inst_1603: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x058 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x018 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3858; op2val:0xb818; + valaddr_reg:x2; val_offset:3146*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 3146*FLEN/8, x6, x4, x5) + +inst_1604: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x058 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x018 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3858; op2val:0xb818; + valaddr_reg:x2; val_offset:3148*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 3148*FLEN/8, x6, x4, x5) + +inst_1605: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3eb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3ab and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3beb; op2val:0xbbab; + valaddr_reg:x2; val_offset:3150*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 3150*FLEN/8, x6, x4, x5) + +inst_1606: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3eb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3ab and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3beb; op2val:0xbbab; + valaddr_reg:x2; val_offset:3152*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 3152*FLEN/8, x6, x4, x5) + +inst_1607: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3eb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3ab and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3beb; op2val:0xbbab; + valaddr_reg:x2; val_offset:3154*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 3154*FLEN/8, x6, x4, x5) + +inst_1608: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3eb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3ab and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3beb; op2val:0xbbab; + valaddr_reg:x2; val_offset:3156*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 3156*FLEN/8, x6, x4, x5) + +inst_1609: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3eb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3ab and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3beb; op2val:0xbbab; + valaddr_reg:x2; val_offset:3158*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 3158*FLEN/8, x6, x4, x5) + +inst_1610: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x37c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x33c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b7c; op2val:0xbb3c; + valaddr_reg:x2; val_offset:3160*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 3160*FLEN/8, x6, x4, x5) + +inst_1611: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x37c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x33c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b7c; op2val:0xbb3c; + valaddr_reg:x2; val_offset:3162*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 3162*FLEN/8, x6, x4, x5) + +inst_1612: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x37c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x33c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b7c; op2val:0xbb3c; + valaddr_reg:x2; val_offset:3164*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 3164*FLEN/8, x6, x4, x5) + +inst_1613: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x37c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x33c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b7c; op2val:0xbb3c; + valaddr_reg:x2; val_offset:3166*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 3166*FLEN/8, x6, x4, x5) + +inst_1614: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x37c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x33c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b7c; op2val:0xbb3c; + valaddr_reg:x2; val_offset:3168*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 3168*FLEN/8, x6, x4, x5) + +inst_1615: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x15c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0dc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x355c; op2val:0xb4dc; + valaddr_reg:x2; val_offset:3170*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 3170*FLEN/8, x6, x4, x5) + +inst_1616: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x15c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0dc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x355c; op2val:0xb4dc; + valaddr_reg:x2; val_offset:3172*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 3172*FLEN/8, x6, x4, x5) + +inst_1617: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x15c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0dc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x355c; op2val:0xb4dc; + valaddr_reg:x2; val_offset:3174*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 3174*FLEN/8, x6, x4, x5) + +inst_1618: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x15c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0dc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x355c; op2val:0xb4dc; + valaddr_reg:x2; val_offset:3176*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 3176*FLEN/8, x6, x4, x5) + +inst_1619: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x15c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0dc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x355c; op2val:0xb4dc; + valaddr_reg:x2; val_offset:3178*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 3178*FLEN/8, x6, x4, x5) + +inst_1620: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a1 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x121 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x35a1; op2val:0xb521; + valaddr_reg:x2; val_offset:3180*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 3180*FLEN/8, x6, x4, x5) + +inst_1621: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a1 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x121 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x35a1; op2val:0xb521; + valaddr_reg:x2; val_offset:3182*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 3182*FLEN/8, x6, x4, x5) + +inst_1622: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a1 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x121 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x35a1; op2val:0xb521; + valaddr_reg:x2; val_offset:3184*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 3184*FLEN/8, x6, x4, x5) + +inst_1623: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a1 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x121 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x35a1; op2val:0xb521; + valaddr_reg:x2; val_offset:3186*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 3186*FLEN/8, x6, x4, x5) + +inst_1624: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a1 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x121 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x35a1; op2val:0xb521; + valaddr_reg:x2; val_offset:3188*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 3188*FLEN/8, x6, x4, x5) + +inst_1625: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ae and fs2 == 1 and fe2 == 0x0e and fm2 == 0x36e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bae; op2val:0xbb6e; + valaddr_reg:x2; val_offset:3190*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 3190*FLEN/8, x6, x4, x5) + +inst_1626: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ae and fs2 == 1 and fe2 == 0x0e and fm2 == 0x36e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bae; op2val:0xbb6e; + valaddr_reg:x2; val_offset:3192*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 3192*FLEN/8, x6, x4, x5) + +inst_1627: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ae and fs2 == 1 and fe2 == 0x0e and fm2 == 0x36e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bae; op2val:0xbb6e; + valaddr_reg:x2; val_offset:3194*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 3194*FLEN/8, x6, x4, x5) + +inst_1628: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ae and fs2 == 1 and fe2 == 0x0e and fm2 == 0x36e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bae; op2val:0xbb6e; + valaddr_reg:x2; val_offset:3196*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 3196*FLEN/8, x6, x4, x5) + +inst_1629: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ae and fs2 == 1 and fe2 == 0x0e and fm2 == 0x36e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bae; op2val:0xbb6e; + valaddr_reg:x2; val_offset:3198*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 3198*FLEN/8, x6, x4, x5) + +inst_1630: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x00a and fs2 == 1 and fe2 == 0x03 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x280a; op2val:0x8cff; + valaddr_reg:x2; val_offset:3200*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 3200*FLEN/8, x6, x4, x5) + +inst_1631: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x00a and fs2 == 1 and fe2 == 0x03 and fm2 == 0x0ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x280a; op2val:0x8cff; + valaddr_reg:x2; val_offset:3202*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 3202*FLEN/8, x6, x4, x5) + +inst_1632: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x00a and fs2 == 1 and fe2 == 0x03 and fm2 == 0x0ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x280a; op2val:0x8cff; + valaddr_reg:x2; val_offset:3204*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 3204*FLEN/8, x6, x4, x5) + +inst_1633: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x00a and fs2 == 1 and fe2 == 0x03 and fm2 == 0x0ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x280a; op2val:0x8cff; + valaddr_reg:x2; val_offset:3206*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 3206*FLEN/8, x6, x4, x5) + +inst_1634: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x00a and fs2 == 1 and fe2 == 0x03 and fm2 == 0x0ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x280a; op2val:0x8cff; + valaddr_reg:x2; val_offset:3208*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 3208*FLEN/8, x6, x4, x5) + +inst_1635: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x127 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0a7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3527; op2val:0xb4a7; + valaddr_reg:x2; val_offset:3210*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 3210*FLEN/8, x6, x4, x5) + +inst_1636: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x127 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0a7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3527; op2val:0xb4a7; + valaddr_reg:x2; val_offset:3212*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 3212*FLEN/8, x6, x4, x5) + +inst_1637: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x127 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0a7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3527; op2val:0xb4a7; + valaddr_reg:x2; val_offset:3214*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 3214*FLEN/8, x6, x4, x5) + +inst_1638: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x127 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0a7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3527; op2val:0xb4a7; + valaddr_reg:x2; val_offset:3216*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 3216*FLEN/8, x6, x4, x5) + +inst_1639: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x127 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0a7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3527; op2val:0xb4a7; + valaddr_reg:x2; val_offset:3218*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 3218*FLEN/8, x6, x4, x5) + +inst_1640: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a3e; op2val:0xb9fe; + valaddr_reg:x2; val_offset:3220*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 3220*FLEN/8, x6, x4, x5) + +inst_1641: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1fe and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a3e; op2val:0xb9fe; + valaddr_reg:x2; val_offset:3222*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 32, 0, x2, 3222*FLEN/8, x6, x4, x5) + +inst_1642: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1fe and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a3e; op2val:0xb9fe; + valaddr_reg:x2; val_offset:3224*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 3224*FLEN/8, x6, x4, x5) + +inst_1643: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1fe and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a3e; op2val:0xb9fe; + valaddr_reg:x2; val_offset:3226*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 3226*FLEN/8, x6, x4, x5) + +inst_1644: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1fe and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a3e; op2val:0xb9fe; + valaddr_reg:x2; val_offset:3228*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 128, 0, x2, 3228*FLEN/8, x6, x4, x5) + +inst_1645: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0fa and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0fa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x30fa; op2val:0xb0fa; + valaddr_reg:x2; val_offset:3230*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 3230*FLEN/8, x6, x4, x5) + +inst_1646: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0fa and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0fa and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x30fa; op2val:0xb0fa; + valaddr_reg:x2; val_offset:3232*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 64, 0, x2, 3232*FLEN/8, x6, x4, x5) + +inst_1647: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0fa and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0fa and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x30fa; op2val:0xb0fa; + valaddr_reg:x2; val_offset:3234*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 96, 0, x2, 3234*FLEN/8, x6, x4, x5) + +inst_1648: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2eb and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2eb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x32eb; op2val:0xb2eb; + valaddr_reg:x2; val_offset:3236*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x2, 3236*FLEN/8, x6, x4, x5) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(12538,32,FLEN) +NAN_BOXED(12538,16,FLEN) +NAN_BOXED(12538,32,FLEN) +NAN_BOXED(45306,16,FLEN) +NAN_BOXED(12538,32,FLEN) +NAN_BOXED(12538,16,FLEN) +NAN_BOXED(12538,32,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(12538,32,FLEN) +NAN_BOXED(45306,16,FLEN) +NAN_BOXED(14498,32,FLEN) +NAN_BOXED(47266,16,FLEN) +NAN_BOXED(14498,32,FLEN) +NAN_BOXED(47266,16,FLEN) +NAN_BOXED(14498,32,FLEN) +NAN_BOXED(47266,16,FLEN) +NAN_BOXED(14498,32,FLEN) +NAN_BOXED(47266,16,FLEN) +NAN_BOXED(14498,32,FLEN) +NAN_BOXED(47266,16,FLEN) +NAN_BOXED(14289,32,FLEN) +NAN_BOXED(47057,16,FLEN) +NAN_BOXED(14289,32,FLEN) +NAN_BOXED(47057,16,FLEN) +test_dataset_1: +NAN_BOXED(14289,32,FLEN) +NAN_BOXED(47057,16,FLEN) +NAN_BOXED(14289,32,FLEN) +NAN_BOXED(47057,16,FLEN) +NAN_BOXED(14289,32,FLEN) +NAN_BOXED(47057,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(45803,16,FLEN) +NAN_BOXED(13035,32,FLEN) +NAN_BOXED(45803,16,FLEN) +NAN_BOXED(13035,32,FLEN) +NAN_BOXED(45803,16,FLEN) +NAN_BOXED(13035,32,FLEN) +NAN_BOXED(45803,16,FLEN) +NAN_BOXED(13035,32,FLEN) +NAN_BOXED(45803,16,FLEN) +test_dataset_2: +NAN_BOXED(14383,32,FLEN) +NAN_BOXED(47151,16,FLEN) +NAN_BOXED(14383,32,FLEN) +NAN_BOXED(47151,16,FLEN) +NAN_BOXED(14383,32,FLEN) +NAN_BOXED(47151,16,FLEN) +NAN_BOXED(14383,32,FLEN) +NAN_BOXED(47151,16,FLEN) +NAN_BOXED(14383,32,FLEN) +NAN_BOXED(47151,16,FLEN) +NAN_BOXED(11745,32,FLEN) +NAN_BOXED(44513,16,FLEN) +NAN_BOXED(11745,32,FLEN) +NAN_BOXED(44513,16,FLEN) +NAN_BOXED(11745,32,FLEN) +NAN_BOXED(44513,16,FLEN) +NAN_BOXED(11745,32,FLEN) +NAN_BOXED(44513,16,FLEN) +NAN_BOXED(11745,32,FLEN) +NAN_BOXED(44513,16,FLEN) +test_dataset_3: +NAN_BOXED(14782,16,FLEN) +NAN_BOXED(47550,16,FLEN) +NAN_BOXED(14782,16,FLEN) +NAN_BOXED(47550,16,FLEN) +NAN_BOXED(14782,16,FLEN) +NAN_BOXED(47550,16,FLEN) +NAN_BOXED(14782,16,FLEN) +NAN_BOXED(47550,16,FLEN) +NAN_BOXED(14782,16,FLEN) +NAN_BOXED(47550,16,FLEN) +NAN_BOXED(13851,16,FLEN) +NAN_BOXED(46619,16,FLEN) +NAN_BOXED(13851,16,FLEN) +NAN_BOXED(46619,16,FLEN) +NAN_BOXED(13851,16,FLEN) +NAN_BOXED(46619,16,FLEN) +NAN_BOXED(13851,16,FLEN) +NAN_BOXED(46619,16,FLEN) +NAN_BOXED(13851,16,FLEN) +NAN_BOXED(46619,16,FLEN) +NAN_BOXED(11718,16,FLEN) +NAN_BOXED(44486,16,FLEN) +NAN_BOXED(11718,16,FLEN) +NAN_BOXED(44486,16,FLEN) +NAN_BOXED(11718,16,FLEN) +NAN_BOXED(44486,16,FLEN) +NAN_BOXED(11718,16,FLEN) +NAN_BOXED(44486,16,FLEN) +NAN_BOXED(11718,16,FLEN) +NAN_BOXED(44486,16,FLEN) +NAN_BOXED(12818,16,FLEN) +NAN_BOXED(45586,16,FLEN) +NAN_BOXED(12818,16,FLEN) +NAN_BOXED(45586,16,FLEN) +NAN_BOXED(12818,16,FLEN) +NAN_BOXED(45586,16,FLEN) +NAN_BOXED(12818,16,FLEN) +NAN_BOXED(45586,16,FLEN) +NAN_BOXED(12818,16,FLEN) +NAN_BOXED(45586,16,FLEN) +NAN_BOXED(14724,16,FLEN) +NAN_BOXED(47492,16,FLEN) +NAN_BOXED(14724,16,FLEN) +NAN_BOXED(47492,16,FLEN) +NAN_BOXED(14724,16,FLEN) +NAN_BOXED(47492,16,FLEN) +NAN_BOXED(14724,16,FLEN) +NAN_BOXED(47492,16,FLEN) +NAN_BOXED(14724,16,FLEN) +NAN_BOXED(47492,16,FLEN) +NAN_BOXED(11897,16,FLEN) +NAN_BOXED(44665,16,FLEN) +NAN_BOXED(11897,16,FLEN) +NAN_BOXED(44665,16,FLEN) +NAN_BOXED(11897,16,FLEN) +NAN_BOXED(44665,16,FLEN) +NAN_BOXED(11897,16,FLEN) +NAN_BOXED(44665,16,FLEN) +NAN_BOXED(11897,16,FLEN) +NAN_BOXED(44665,16,FLEN) +NAN_BOXED(14393,16,FLEN) +NAN_BOXED(47161,16,FLEN) +NAN_BOXED(14393,16,FLEN) +NAN_BOXED(47161,16,FLEN) +NAN_BOXED(14393,16,FLEN) +NAN_BOXED(47161,16,FLEN) +NAN_BOXED(14393,16,FLEN) +NAN_BOXED(47161,16,FLEN) +NAN_BOXED(14393,16,FLEN) +NAN_BOXED(47161,16,FLEN) +NAN_BOXED(14470,16,FLEN) +NAN_BOXED(47238,16,FLEN) +NAN_BOXED(14470,16,FLEN) +NAN_BOXED(47238,16,FLEN) +NAN_BOXED(14470,16,FLEN) +NAN_BOXED(47238,16,FLEN) +NAN_BOXED(14470,16,FLEN) +NAN_BOXED(47238,16,FLEN) +NAN_BOXED(14470,16,FLEN) +NAN_BOXED(47238,16,FLEN) +NAN_BOXED(11665,16,FLEN) +NAN_BOXED(44433,16,FLEN) +NAN_BOXED(11665,16,FLEN) +NAN_BOXED(44433,16,FLEN) +NAN_BOXED(11665,16,FLEN) +NAN_BOXED(44433,16,FLEN) +NAN_BOXED(11665,16,FLEN) +NAN_BOXED(44433,16,FLEN) +NAN_BOXED(11665,16,FLEN) +NAN_BOXED(44433,16,FLEN) +NAN_BOXED(14826,16,FLEN) +NAN_BOXED(47594,16,FLEN) +NAN_BOXED(14826,16,FLEN) +NAN_BOXED(47594,16,FLEN) +NAN_BOXED(14826,16,FLEN) +NAN_BOXED(47594,16,FLEN) +NAN_BOXED(14826,16,FLEN) +NAN_BOXED(47594,16,FLEN) +NAN_BOXED(14826,16,FLEN) +NAN_BOXED(47594,16,FLEN) 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256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x4_3: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x4_4: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x4_5: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x4_6: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x4_7: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x4_8: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x4_9: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x4_10: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x4_11: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x4_12: + .fill 174*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fclass_b1-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fclass_b1-01.S new file mode 100644 index 000000000..09d7db077 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fclass_b1-01.S @@ -0,0 +1,330 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Tue Sep 24 09:03:54 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fclass.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fclass.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fclass_b1 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fclass_b1) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x16,test_dataset_0) +RVTEST_SIGBASE(x12,signature_x12_1) + +inst_0:// rs1==x23, rd==x6,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 +/* opcode: fclass.h ; op1:x23; dest:x6; op1val:0x0; valaddr_reg:x16; +val_offset:0*FLEN/8; correctval:??; testreg:x15; +fcsr_val:0*/ +TEST_FPID_OP_NRM(fclass.h, x6, x23, 0, 0, x16, 0*FLEN/8, x17, x12, x15) + +inst_1:// rs1==x11, rd==x27,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff +/* opcode: fclass.h ; op1:x11; dest:x27; op1val:0x8000; valaddr_reg:x16; +val_offset:1*FLEN/8; correctval:??; testreg:x15; +fcsr_val:0*/ +TEST_FPID_OP_NRM(fclass.h, x27, x11, 0, 0, x16, 1*FLEN/8, x17, x12, x15) + +inst_2:// rs1==x27, rd==x30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 +/* opcode: fclass.h ; op1:x27; dest:x30; op1val:0x1; valaddr_reg:x16; +val_offset:2*FLEN/8; correctval:??; testreg:x15; +fcsr_val:0*/ +TEST_FPID_OP_NRM(fclass.h, x30, x27, 0, 0, x16, 2*FLEN/8, x17, x12, x15) + +inst_3:// rs1==x2, rd==x25,fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff +/* opcode: fclass.h ; op1:x2; dest:x25; op1val:0x8001; valaddr_reg:x16; +val_offset:3*FLEN/8; correctval:??; testreg:x15; +fcsr_val:0*/ +TEST_FPID_OP_NRM(fclass.h, x25, x2, 0, 0, x16, 3*FLEN/8, x17, x12, x15) + +inst_4:// rs1==x20, rd==x3,fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 +/* opcode: fclass.h ; op1:x20; dest:x3; op1val:0x2; valaddr_reg:x16; +val_offset:4*FLEN/8; correctval:??; testreg:x15; +fcsr_val:0*/ +TEST_FPID_OP_NRM(fclass.h, x3, x20, 0, 0, x16, 4*FLEN/8, x17, x12, x15) + +inst_5:// rs1==x19, rd==x7,fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff +/* opcode: fclass.h ; op1:x19; dest:x7; op1val:0x83fe; valaddr_reg:x16; +val_offset:5*FLEN/8; correctval:??; testreg:x15; +fcsr_val:0*/ +TEST_FPID_OP_NRM(fclass.h, x7, x19, 0, 0, x16, 5*FLEN/8, x17, x12, x15) + +inst_6:// rs1==x8, rd==x21,fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 +/* opcode: fclass.h ; op1:x8; dest:x21; op1val:0x3ff; valaddr_reg:x16; +val_offset:6*FLEN/8; correctval:??; testreg:x15; +fcsr_val:0*/ +TEST_FPID_OP_NRM(fclass.h, x21, x8, 0, 0, x16, 6*FLEN/8, x17, x12, x15) + +inst_7:// rs1==x26, rd==x22,fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff +/* opcode: fclass.h ; op1:x26; dest:x22; op1val:0x83ff; valaddr_reg:x16; +val_offset:7*FLEN/8; correctval:??; testreg:x15; +fcsr_val:0*/ +TEST_FPID_OP_NRM(fclass.h, x22, x26, 0, 0, x16, 7*FLEN/8, x17, x12, x15) + +inst_8:// rs1==x25, rd==x10,fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 +/* opcode: fclass.h ; op1:x25; dest:x10; op1val:0x400; valaddr_reg:x16; +val_offset:8*FLEN/8; correctval:??; testreg:x15; +fcsr_val:0*/ +TEST_FPID_OP_NRM(fclass.h, x10, x25, 0, 0, x16, 8*FLEN/8, x17, x12, x15) + +inst_9:// rs1==x1, rd==x28,fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff +/* opcode: fclass.h ; op1:x1; dest:x28; op1val:0x8400; valaddr_reg:x16; +val_offset:9*FLEN/8; correctval:??; testreg:x15; +fcsr_val:0*/ +TEST_FPID_OP_NRM(fclass.h, x28, x1, 0, 0, x16, 9*FLEN/8, x17, x12, x15) + +inst_10:// rs1==x18, rd==x5,fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 +/* opcode: fclass.h ; op1:x18; dest:x5; op1val:0x401; valaddr_reg:x16; +val_offset:10*FLEN/8; correctval:??; testreg:x15; +fcsr_val:0*/ +TEST_FPID_OP_NRM(fclass.h, x5, x18, 0, 0, x16, 10*FLEN/8, x17, x12, x15) + +inst_11:// rs1==x7, rd==x14,fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff +/* opcode: fclass.h ; op1:x7; dest:x14; op1val:0x8455; valaddr_reg:x16; +val_offset:11*FLEN/8; correctval:??; testreg:x15; +fcsr_val:0*/ +TEST_FPID_OP_NRM(fclass.h, x14, x7, 0, 0, x16, 11*FLEN/8, x17, x12, x15) + +inst_12:// rs1==x31, rd==x2,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 +/* opcode: fclass.h ; op1:x31; dest:x2; op1val:0x7bff; valaddr_reg:x16; +val_offset:12*FLEN/8; correctval:??; testreg:x15; +fcsr_val:0*/ +TEST_FPID_OP_NRM(fclass.h, x2, x31, 0, 0, x16, 12*FLEN/8, x17, x12, x15) + +inst_13:// rs1==x9, rd==x0,fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff +/* opcode: fclass.h ; op1:x9; dest:x0; op1val:0xfbff; valaddr_reg:x16; +val_offset:13*FLEN/8; correctval:??; testreg:x15; +fcsr_val:0*/ +TEST_FPID_OP_NRM(fclass.h, x0, x9, 0, 0, x16, 13*FLEN/8, x17, x12, x15) + +inst_14:// rs1==x13, rd==x4,fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 +/* opcode: fclass.h ; op1:x13; dest:x4; op1val:0x7c00; valaddr_reg:x16; +val_offset:14*FLEN/8; correctval:??; testreg:x15; +fcsr_val:0*/ +TEST_FPID_OP_NRM(fclass.h, x4, x13, 0, 0, x16, 14*FLEN/8, x17, x12, x15) +RVTEST_VALBASEUPD(x8,test_dataset_1) + +inst_15:// rs1==x17, rd==x19,fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff +/* opcode: fclass.h ; op1:x17; dest:x19; op1val:0xfc00; valaddr_reg:x8; +val_offset:0*FLEN/8; correctval:??; testreg:x15; +fcsr_val:0*/ +TEST_FPID_OP_NRM(fclass.h, x19, x17, 0, 0, x8, 0*FLEN/8, x14, x12, x15) + +inst_16:// rs1==x16, rd==x24,fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 +/* opcode: fclass.h ; op1:x16; dest:x24; op1val:0x7e00; valaddr_reg:x8; +val_offset:1*FLEN/8; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP_NRM(fclass.h, x24, x16, 0, 0, x8, 1*FLEN/8, x14, x12, x7) +RVTEST_SIGBASE(x2,signature_x2_0) + +inst_17:// rs1==x24, rd==x26,fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff +/* opcode: fclass.h ; op1:x24; dest:x26; op1val:0xfe00; valaddr_reg:x8; +val_offset:2*FLEN/8; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP_NRM(fclass.h, x26, x24, 0, 0, x8, 2*FLEN/8, x14, x2, x7) + +inst_18:// rs1==x10, rd==x23,fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 +/* opcode: fclass.h ; op1:x10; dest:x23; op1val:0x7e01; valaddr_reg:x8; +val_offset:3*FLEN/8; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP_NRM(fclass.h, x23, x10, 0, 0, x8, 3*FLEN/8, x14, x2, x7) + +inst_19:// rs1==x12, rd==x1,fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff +/* opcode: fclass.h ; op1:x12; dest:x1; op1val:0xfe55; valaddr_reg:x8; +val_offset:4*FLEN/8; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP_NRM(fclass.h, x1, x12, 0, 0, x8, 4*FLEN/8, x14, x2, x7) + +inst_20:// rs1==x30, rd==x15,fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 +/* opcode: fclass.h ; op1:x30; dest:x15; op1val:0x7c01; valaddr_reg:x8; +val_offset:5*FLEN/8; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP_NRM(fclass.h, x15, x30, 0, 0, x8, 5*FLEN/8, x14, x2, x7) + +inst_21:// rs1==x6, rd==x31,fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff +/* opcode: fclass.h ; op1:x6; dest:x31; op1val:0xfd55; valaddr_reg:x8; +val_offset:6*FLEN/8; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP_NRM(fclass.h, x31, x6, 0, 0, x8, 6*FLEN/8, x14, x2, x7) + +inst_22:// rs1==x15, rd==x13,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 +/* opcode: fclass.h ; op1:x15; dest:x13; op1val:0x3c00; valaddr_reg:x8; +val_offset:7*FLEN/8; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP_NRM(fclass.h, x13, x15, 0, 0, x8, 7*FLEN/8, x14, x2, x7) + +inst_23:// rs1==x5, rd==x11,fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff +/* opcode: fclass.h ; op1:x5; dest:x11; op1val:0xbc00; valaddr_reg:x8; +val_offset:8*FLEN/8; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP_NRM(fclass.h, x11, x5, 0, 0, x8, 8*FLEN/8, x14, x2, x7) + +inst_24:// rs1==x21, rd==x20, +/* opcode: fclass.h ; op1:x21; dest:x20; op1val:0x0; valaddr_reg:x8; +val_offset:9*FLEN/8; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP_NRM(fclass.h, x20, x21, 0, 0, x8, 9*FLEN/8, x14, x2, x7) + +inst_25:// rs1==x3, rd==x12, +/* opcode: fclass.h ; op1:x3; dest:x12; op1val:0x0; valaddr_reg:x8; +val_offset:10*FLEN/8; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP_NRM(fclass.h, x12, x3, 0, 0, x8, 10*FLEN/8, x14, x2, x7) + +inst_26:// rs1==x29, rd==x18, +/* opcode: fclass.h ; op1:x29; dest:x18; op1val:0x0; valaddr_reg:x8; +val_offset:11*FLEN/8; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP_NRM(fclass.h, x18, x29, 0, 0, x8, 11*FLEN/8, x14, x2, x7) + +inst_27:// rs1==x28, rd==x9, +/* opcode: fclass.h ; op1:x28; dest:x9; op1val:0x0; valaddr_reg:x8; +val_offset:12*FLEN/8; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP_NRM(fclass.h, x9, x28, 0, 0, x8, 12*FLEN/8, x14, x2, x7) + +inst_28:// rs1==x4, rd==x29, +/* opcode: fclass.h ; op1:x4; dest:x29; op1val:0x0; valaddr_reg:x8; +val_offset:13*FLEN/8; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP_NRM(fclass.h, x29, x4, 0, 0, x8, 13*FLEN/8, x14, x2, x7) +RVTEST_VALBASEUPD(x3,test_dataset_2) + +inst_29:// rs1==x14, rd==x8, +/* opcode: fclass.h ; op1:x14; dest:x8; op1val:0x0; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP_NRM(fclass.h, x8, x14, 0, 0, x3, 0*FLEN/8, x4, x2, x7) + +inst_30:// rs1==x0, rd==x17, +/* opcode: fclass.h ; op1:x0; dest:x17; op1val:0x0; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP_NRM(fclass.h, x17, x0, 0, 0, x3, 1*FLEN/8, x4, x2, x7) + +inst_31:// rs1==x22, rd==x16, +/* opcode: fclass.h ; op1:x22; dest:x16; op1val:0x0; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP_NRM(fclass.h, x16, x22, 0, 0, x3, 2*FLEN/8, x4, x2, x7) + +inst_32:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff +/* opcode: fclass.h ; op1:x30; dest:x31; op1val:0xfbff; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x1; +fcsr_val:0*/ +TEST_FPID_OP_NRM(fclass.h, x31, x30, 0, 0, x3, 3*FLEN/8, x4, x2, x1) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1,32,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(2,32,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(1023,32,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(1024,32,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(1025,32,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31744,32,FLEN) +test_dataset_1: +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(32256,32,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(32257,32,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(31745,32,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(15360,32,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +test_dataset_2: +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x12_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x12_1: + .fill 34*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_0: + .fill 32*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fcvt.w.h_b1-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fcvt.w.h_b1-01.S new file mode 100644 index 000000000..6e321b2a2 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fcvt.w.h_b1-01.S @@ -0,0 +1,342 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 06:00:03 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fcvt.w.h.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.w.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fcvt.w.h_b1 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fcvt.w.h_b1) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x14,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0:// rs1==x8, rd==x22,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x8; dest:x22; op1val:0x0; valaddr_reg:x14; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x22, x8, dyn, 0, 0, x14, 0*FLEN/8, x19, x1, x3,FLREG) + +inst_1:// rs1==x9, rd==x4,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x9; dest:x4; op1val:0x8000; valaddr_reg:x14; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x4, x9, dyn, 0, 0, x14, 1*FLEN/8, x19, x1, x3,FLREG) + +inst_2:// rs1==x31, rd==x23,fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x31; dest:x23; op1val:0x1; valaddr_reg:x14; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x23, x31, dyn, 0, 0, x14, 2*FLEN/8, x19, x1, x3,FLREG) + +inst_3:// rs1==x29, rd==x21,fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x29; dest:x21; op1val:0x8001; valaddr_reg:x14; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x21, x29, dyn, 0, 0, x14, 3*FLEN/8, x19, x1, x3,FLREG) + +inst_4:// rs1==x5, rd==x13,fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x5; dest:x13; op1val:0x2; valaddr_reg:x14; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x13, x5, dyn, 0, 0, x14, 4*FLEN/8, x19, x1, x3,FLREG) + +inst_5:// rs1==x4, rd==x25,fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x4; dest:x25; op1val:0x83fe; valaddr_reg:x14; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x25, x4, dyn, 0, 0, x14, 5*FLEN/8, x19, x1, x3,FLREG) + +inst_6:// rs1==x28, rd==x26,fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x28; dest:x26; op1val:0x3ff; valaddr_reg:x14; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x26, x28, dyn, 0, 0, x14, 6*FLEN/8, x19, x1, x3,FLREG) + +inst_7:// rs1==x10, rd==x11,fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x10; dest:x11; op1val:0x83ff; valaddr_reg:x14; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x11, x10, dyn, 0, 0, x14, 7*FLEN/8, x19, x1, x3,FLREG) + +inst_8:// rs1==x18, rd==x9,fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x18; dest:x9; op1val:0x400; valaddr_reg:x14; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x9, x18, dyn, 0, 0, x14, 8*FLEN/8, x19, x1, x3,FLREG) + +inst_9:// rs1==x24, rd==x15,fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x24; dest:x15; op1val:0x8400; valaddr_reg:x14; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x15, x24, dyn, 0, 0, x14, 9*FLEN/8, x19, x1, x3,FLREG) + +inst_10:// rs1==x17, rd==x18,fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x17; dest:x18; op1val:0x401; valaddr_reg:x14; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x18, x17, dyn, 0, 0, x14, 10*FLEN/8, x19, x1, x3,FLREG) + +inst_11:// rs1==x7, rd==x0,fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x7; dest:x0; op1val:0x8455; valaddr_reg:x14; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x0, x7, dyn, 0, 0, x14, 11*FLEN/8, x19, x1, x3,FLREG) + +inst_12:// rs1==x16, rd==x6,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x16; dest:x6; op1val:0x7bff; valaddr_reg:x14; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x6, x16, dyn, 0, 0, x14, 12*FLEN/8, x19, x1, x3,FLREG) + +inst_13:// rs1==x12, rd==x2,fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x12; dest:x2; op1val:0xfbff; valaddr_reg:x14; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x2, x12, dyn, 0, 0, x14, 13*FLEN/8, x19, x1, x3,FLREG) +RVTEST_VALBASEUPD(x7,test_dataset_1) + +inst_14:// rs1==x27, rd==x20,fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x27; dest:x20; op1val:0x7c00; valaddr_reg:x7; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x20, x27, dyn, 0, 0, x7, 0*FLEN/8, x10, x1, x3,FLREG) + +inst_15:// rs1==x30, rd==x17,fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x17; op1val:0xfc00; valaddr_reg:x7; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x17, x30, dyn, 0, 0, x7, 1*FLEN/8, x10, x1, x9,FLREG) +RVTEST_SIGBASE(x4,signature_x4_0) + +inst_16:// rs1==x0, rd==x27,fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x0; dest:x27; op1val:0x0; valaddr_reg:x7; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x27, x0, dyn, 0, 0, x7, 2*FLEN/8, x10, x4, x9,FLREG) + +inst_17:// rs1==x22, rd==x28,fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x22; dest:x28; op1val:0xfe00; valaddr_reg:x7; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x28, x22, dyn, 0, 0, x7, 3*FLEN/8, x10, x4, x9,FLREG) + +inst_18:// rs1==x6, rd==x8,fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x6; dest:x8; op1val:0x7e01; valaddr_reg:x7; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x8, x6, dyn, 0, 0, x7, 4*FLEN/8, x10, x4, x9,FLREG) + +inst_19:// rs1==x3, rd==x16,fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x3; dest:x16; op1val:0xfe55; valaddr_reg:x7; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x16, x3, dyn, 0, 0, x7, 5*FLEN/8, x10, x4, x9,FLREG) + +inst_20:// rs1==x2, rd==x12,fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x2; dest:x12; op1val:0x7c01; valaddr_reg:x7; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x12, x2, dyn, 0, 0, x7, 6*FLEN/8, x10, x4, x9,FLREG) + +inst_21:// rs1==x23, rd==x19,fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x23; dest:x19; op1val:0xfd55; valaddr_reg:x7; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x19, x23, dyn, 0, 0, x7, 7*FLEN/8, x10, x4, x9,FLREG) + +inst_22:// rs1==x14, rd==x30,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x14; dest:x30; op1val:0x3c00; valaddr_reg:x7; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x30, x14, dyn, 0, 0, x7, 8*FLEN/8, x10, x4, x9,FLREG) + +inst_23:// rs1==x20, rd==x31,fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x20; dest:x31; op1val:0xbc00; valaddr_reg:x7; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x31, x20, dyn, 0, 0, x7, 9*FLEN/8, x10, x4, x9,FLREG) + +inst_24:// rs1==x26, rd==x14, +/* opcode: fcvt.w.h ; op1:x26; dest:x14; op1val:0x0; valaddr_reg:x7; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x14, x26, dyn, 0, 0, x7, 10*FLEN/8, x10, x4, x9,FLREG) + +inst_25:// rs1==x19, rd==x3, +/* opcode: fcvt.w.h ; op1:x19; dest:x3; op1val:0x0; valaddr_reg:x7; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x3, x19, dyn, 0, 0, x7, 11*FLEN/8, x10, x4, x9,FLREG) + +inst_26:// rs1==x1, rd==x24, +/* opcode: fcvt.w.h ; op1:x1; dest:x24; op1val:0x0; valaddr_reg:x7; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x24, x1, dyn, 0, 0, x7, 12*FLEN/8, x10, x4, x9,FLREG) + +inst_27:// rs1==x13, rd==x29, +/* opcode: fcvt.w.h ; op1:x13; dest:x29; op1val:0x0; valaddr_reg:x7; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x29, x13, dyn, 0, 0, x7, 13*FLEN/8, x10, x4, x9,FLREG) + +inst_28:// rs1==x25, rd==x1, +/* opcode: fcvt.w.h ; op1:x25; dest:x1; op1val:0x0; valaddr_reg:x7; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x1, x25, dyn, 0, 0, x7, 14*FLEN/8, x10, x4, x9,FLREG) + +inst_29:// rs1==x11, rd==x5, +/* opcode: fcvt.w.h ; op1:x11; dest:x5; op1val:0x0; valaddr_reg:x7; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x5, x11, dyn, 0, 0, x7, 15*FLEN/8, x10, x4, x9,FLREG) +RVTEST_VALBASEUPD(x3,test_dataset_2) + +inst_30:// rs1==x21, rd==x7, +/* opcode: fcvt.w.h ; op1:x21; dest:x7; op1val:0x0; valaddr_reg:x3; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x7, x21, dyn, 0, 0, x3, 0*FLEN/8, x5, x4, x9,FLREG) + +inst_31:// rs1==x15, rd==x10, +/* opcode: fcvt.w.h ; op1:x15; dest:x10; op1val:0x0; valaddr_reg:x3; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x10, x15, dyn, 0, 0, x3, 1*FLEN/8, x5, x4, x2,FLREG) +RVTEST_SIGBASE(x1,signature_x1_2) + +inst_32:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0x8455; valaddr_reg:x3; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 0, 0, x3, 2*FLEN/8, x5, x1, x2,FLREG) + +inst_33:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0x7e00; valaddr_reg:x3; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 0, 0, x3, 3*FLEN/8, x5, x1, x2,FLREG) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1,32,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(2,32,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(1023,32,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(1024,32,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(1025,32,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(64511,16,FLEN) +test_dataset_1: +NAN_BOXED(31744,32,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(32257,32,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(31745,32,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(15360,32,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +test_dataset_2: +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(32256,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 32*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x4_0: + .fill 32*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_2: + .fill 4*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fcvt.w.h_b22-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fcvt.w.h_b22-01.S new file mode 100644 index 000000000..318a7c857 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fcvt.w.h_b22-01.S @@ -0,0 +1,391 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 06:00:03 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fcvt.w.h.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.w.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fcvt.w.h_b22 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fcvt.w.h_b22) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x15,test_dataset_0) +RVTEST_SIGBASE(x2,signature_x2_1) + +inst_0:// rs1==x10, rd==x31,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x10; dest:x31; op1val:0x3249; valaddr_reg:x15; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x31, x10, dyn, 0, 0, x15, 0*FLEN/8, x23, x2, x13,FLREG) + +inst_1:// rs1==x6, rd==x26,fs1 == 0 and fe1 == 0x0d and fm1 == 0x1b7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x6; dest:x26; op1val:0x35b7; valaddr_reg:x15; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x26, x6, dyn, 0, 0, x15, 1*FLEN/8, x23, x2, x13,FLREG) + +inst_2:// rs1==x14, rd==x12,fs1 == 0 and fe1 == 0x0e and fm1 == 0x24f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x14; dest:x12; op1val:0x3a4f; valaddr_reg:x15; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x12, x14, dyn, 0, 0, x15, 2*FLEN/8, x23, x2, x13,FLREG) + +inst_3:// rs1==x30, rd==x10,fs1 == 0 and fe1 == 0x0f and fm1 == 0x0d3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x10; op1val:0x3cd3; valaddr_reg:x15; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x10, x30, dyn, 0, 0, x15, 3*FLEN/8, x23, x2, x13,FLREG) + +inst_4:// rs1==x21, rd==x16,fs1 == 0 and fe1 == 0x10 and fm1 == 0x340 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x21; dest:x16; op1val:0x4340; valaddr_reg:x15; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x16, x21, dyn, 0, 0, x15, 4*FLEN/8, x23, x2, x13,FLREG) + +inst_5:// rs1==x27, rd==x14,fs1 == 0 and fe1 == 0x11 and fm1 == 0x34b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x27; dest:x14; op1val:0x474b; valaddr_reg:x15; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x14, x27, dyn, 0, 0, x15, 5*FLEN/8, x23, x2, x13,FLREG) + +inst_6:// rs1==x28, rd==x20,fs1 == 1 and fe1 == 0x12 and fm1 == 0x29d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x28; dest:x20; op1val:0xca9d; valaddr_reg:x15; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x20, x28, dyn, 0, 0, x15, 6*FLEN/8, x23, x2, x13,FLREG) + +inst_7:// rs1==x18, rd==x0,fs1 == 0 and fe1 == 0x13 and fm1 == 0x0a4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x18; dest:x0; op1val:0x4ca4; valaddr_reg:x15; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x0, x18, dyn, 0, 0, x15, 7*FLEN/8, x23, x2, x13,FLREG) + +inst_8:// rs1==x11, rd==x27,fs1 == 0 and fe1 == 0x14 and fm1 == 0x215 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x11; dest:x27; op1val:0x5215; valaddr_reg:x15; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x27, x11, dyn, 0, 0, x15, 8*FLEN/8, x23, x2, x13,FLREG) + +inst_9:// rs1==x3, rd==x29,fs1 == 0 and fe1 == 0x15 and fm1 == 0x14f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x3; dest:x29; op1val:0x554f; valaddr_reg:x15; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x29, x3, dyn, 0, 0, x15, 9*FLEN/8, x23, x2, x13,FLREG) + +inst_10:// rs1==x19, rd==x8,fs1 == 1 and fe1 == 0x16 and fm1 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x19; dest:x8; op1val:0xd8ff; valaddr_reg:x15; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x8, x19, dyn, 0, 0, x15, 10*FLEN/8, x23, x2, x13,FLREG) + +inst_11:// rs1==x17, rd==x19,fs1 == 1 and fe1 == 0x17 and fm1 == 0x3cf and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x17; dest:x19; op1val:0xdfcf; valaddr_reg:x15; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x19, x17, dyn, 0, 0, x15, 11*FLEN/8, x23, x2, x13,FLREG) + +inst_12:// rs1==x5, rd==x18,fs1 == 0 and fe1 == 0x18 and fm1 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x5; dest:x18; op1val:0x63fc; valaddr_reg:x15; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x18, x5, dyn, 0, 0, x15, 12*FLEN/8, x23, x2, x13,FLREG) + +inst_13:// rs1==x8, rd==x28,fs1 == 0 and fe1 == 0x19 and fm1 == 0x02d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x8; dest:x28; op1val:0x642d; valaddr_reg:x15; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x28, x8, dyn, 0, 0, x15, 13*FLEN/8, x23, x2, x13,FLREG) + +inst_14:// rs1==x29, rd==x22,fs1 == 0 and fe1 == 0x1a and fm1 == 0x370 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x29; dest:x22; op1val:0x6b70; valaddr_reg:x15; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x22, x29, dyn, 0, 0, x15, 14*FLEN/8, x23, x2, x13,FLREG) + +inst_15:// rs1==x9, rd==x4,fs1 == 0 and fe1 == 0x1b and fm1 == 0x269 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x9; dest:x4; op1val:0x6e69; valaddr_reg:x15; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x4, x9, dyn, 0, 0, x15, 15*FLEN/8, x23, x2, x13,FLREG) + +inst_16:// rs1==x1, rd==x7,fs1 == 0 and fe1 == 0x1c and fm1 == 0x186 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x1; dest:x7; op1val:0x7186; valaddr_reg:x15; +val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x7, x1, dyn, 0, 0, x15, 16*FLEN/8, x23, x2, x13,FLREG) +RVTEST_VALBASEUPD(x14,test_dataset_1) + +inst_17:// rs1==x24, rd==x23,fs1 == 1 and fe1 == 0x1d and fm1 == 0x122 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x24; dest:x23; op1val:0xf522; valaddr_reg:x14; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x23, x24, dyn, 0, 0, x14, 0*FLEN/8, x18, x2, x13,FLREG) +RVTEST_SIGBASE(x8,signature_x8_0) + +inst_18:// rs1==x25, rd==x1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x25; dest:x1; op1val:0x7ab3; valaddr_reg:x14; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x10; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x1, x25, dyn, 0, 0, x14, 1*FLEN/8, x18, x8, x10,FLREG) + +inst_19:// rs1==x26, rd==x11,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x26; dest:x11; op1val:0x7bff; valaddr_reg:x14; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x10; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x11, x26, dyn, 0, 0, x14, 2*FLEN/8, x18, x8, x10,FLREG) + +inst_20:// rs1==x12, rd==x30,fs1 == 1 and fe1 == 0x00 and fm1 == 0x2be and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x12; dest:x30; op1val:0x82be; valaddr_reg:x14; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x10; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x30, x12, dyn, 0, 0, x14, 3*FLEN/8, x18, x8, x10,FLREG) + +inst_21:// rs1==x15, rd==x3,fs1 == 1 and fe1 == 0x01 and fm1 == 0x2a5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x15; dest:x3; op1val:0x86a5; valaddr_reg:x14; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x10; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x3, x15, dyn, 0, 0, x14, 4*FLEN/8, x18, x8, x10,FLREG) + +inst_22:// rs1==x23, rd==x9,fs1 == 1 and fe1 == 0x02 and fm1 == 0x088 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x23; dest:x9; op1val:0x8888; valaddr_reg:x14; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x10; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x9, x23, dyn, 0, 0, x14, 5*FLEN/8, x18, x8, x10,FLREG) + +inst_23:// rs1==x31, rd==x13,fs1 == 1 and fe1 == 0x03 and fm1 == 0x312 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x31; dest:x13; op1val:0x8f12; valaddr_reg:x14; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x10; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x13, x31, dyn, 0, 0, x14, 6*FLEN/8, x18, x8, x10,FLREG) + +inst_24:// rs1==x13, rd==x6,fs1 == 1 and fe1 == 0x04 and fm1 == 0x3ed and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x13; dest:x6; op1val:0x93ed; valaddr_reg:x14; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x10; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x6, x13, dyn, 0, 0, x14, 7*FLEN/8, x18, x8, x10,FLREG) + +inst_25:// rs1==x7, rd==x17,fs1 == 1 and fe1 == 0x05 and fm1 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x7; dest:x17; op1val:0x97e0; valaddr_reg:x14; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x10; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x17, x7, dyn, 0, 0, x14, 8*FLEN/8, x18, x8, x10,FLREG) + +inst_26:// rs1==x20, rd==x15,fs1 == 1 and fe1 == 0x06 and fm1 == 0x274 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x20; dest:x15; op1val:0x9a74; valaddr_reg:x14; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x10; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x15, x20, dyn, 0, 0, x14, 9*FLEN/8, x18, x8, x10,FLREG) + +inst_27:// rs1==x2, rd==x21,fs1 == 1 and fe1 == 0x07 and fm1 == 0x02d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x2; dest:x21; op1val:0x9c2d; valaddr_reg:x14; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x10; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x21, x2, dyn, 0, 0, x14, 10*FLEN/8, x18, x8, x10,FLREG) + +inst_28:// rs1==x16, rd==x24,fs1 == 1 and fe1 == 0x08 and fm1 == 0x004 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x16; dest:x24; op1val:0xa004; valaddr_reg:x14; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x10; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x24, x16, dyn, 0, 0, x14, 11*FLEN/8, x18, x8, x10,FLREG) + +inst_29:// rs1==x22, rd==x5,fs1 == 1 and fe1 == 0x09 and fm1 == 0x089 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x22; dest:x5; op1val:0xa489; valaddr_reg:x14; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x10; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x5, x22, dyn, 0, 0, x14, 12*FLEN/8, x18, x8, x10,FLREG) + +inst_30:// rs1==x0, rd==x2,fs1 == 1 and fe1 == 0x0a and fm1 == 0x3c3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x0; dest:x2; op1val:0x0; valaddr_reg:x14; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x10; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x2, x0, dyn, 0, 0, x14, 13*FLEN/8, x18, x8, x10,FLREG) + +inst_31:// rs1==x4, rd==x25,fs1 == 1 and fe1 == 0x0b and fm1 == 0x136 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x4; dest:x25; op1val:0xad36; valaddr_reg:x14; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x10; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x25, x4, dyn, 0, 0, x14, 14*FLEN/8, x18, x8, x10,FLREG) + +inst_32:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x176 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xb176; valaddr_reg:x14; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x10; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 0, 0, x14, 15*FLEN/8, x18, x8, x10,FLREG) + +inst_33:// fs1 == 1 and fe1 == 0x0d and fm1 == 0x397 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xb797; valaddr_reg:x14; +val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x10; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 0, 0, x14, 16*FLEN/8, x18, x8, x10,FLREG) + +inst_34:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x141 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xb941; valaddr_reg:x14; +val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x10; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 0, 0, x14, 17*FLEN/8, x18, x8, x10,FLREG) + +inst_35:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x232 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xbe32; valaddr_reg:x14; +val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x10; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 0, 0, x14, 18*FLEN/8, x18, x8, x10,FLREG) + +inst_36:// fs1 == 1 and fe1 == 0x10 and fm1 == 0x1be and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xc1be; valaddr_reg:x14; +val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x10; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 0, 0, x14, 19*FLEN/8, x18, x8, x10,FLREG) + +inst_37:// fs1 == 1 and fe1 == 0x11 and fm1 == 0x042 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xc442; valaddr_reg:x14; +val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x10; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 0, 0, x14, 20*FLEN/8, x18, x8, x10,FLREG) + +inst_38:// fs1 == 1 and fe1 == 0x09 and fm1 == 0x256 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xa656; valaddr_reg:x14; +val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x10; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 0, 0, x14, 21*FLEN/8, x18, x8, x10,FLREG) + +inst_39:// fs1 == 1 and fe1 == 0x16 and fm1 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xda01; valaddr_reg:x14; +val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x10; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 0, 0, x14, 22*FLEN/8, x18, x8, x10,FLREG) + +inst_40:// fs1 == 0 and fe1 == 0x13 and fm1 == 0x0a4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0x4ca4; valaddr_reg:x14; +val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x10; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 0, 0, x14, 23*FLEN/8, x18, x8, x10,FLREG) + +inst_41:// fs1 == 1 and fe1 == 0x0a and fm1 == 0x3c3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xabc3; valaddr_reg:x14; +val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x10; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 0, 0, x14, 24*FLEN/8, x18, x8, x10,FLREG) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(12873,32,FLEN) +NAN_BOXED(13751,32,FLEN) +NAN_BOXED(14927,32,FLEN) +NAN_BOXED(15571,32,FLEN) +NAN_BOXED(17216,32,FLEN) +NAN_BOXED(18251,32,FLEN) +NAN_BOXED(51869,16,FLEN) +NAN_BOXED(19620,32,FLEN) +NAN_BOXED(21013,32,FLEN) +NAN_BOXED(21839,32,FLEN) +NAN_BOXED(55551,16,FLEN) +NAN_BOXED(57295,16,FLEN) +NAN_BOXED(25596,32,FLEN) +NAN_BOXED(25645,32,FLEN) +NAN_BOXED(27504,32,FLEN) +NAN_BOXED(28265,32,FLEN) +NAN_BOXED(29062,32,FLEN) +test_dataset_1: +NAN_BOXED(62754,16,FLEN) +NAN_BOXED(31411,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(33470,16,FLEN) +NAN_BOXED(34469,16,FLEN) +NAN_BOXED(34952,16,FLEN) +NAN_BOXED(36626,16,FLEN) +NAN_BOXED(37869,16,FLEN) +NAN_BOXED(38880,16,FLEN) +NAN_BOXED(39540,16,FLEN) +NAN_BOXED(39981,16,FLEN) +NAN_BOXED(40964,16,FLEN) +NAN_BOXED(42121,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(44342,16,FLEN) +NAN_BOXED(45430,16,FLEN) +NAN_BOXED(46999,16,FLEN) +NAN_BOXED(47425,16,FLEN) +NAN_BOXED(48690,16,FLEN) +NAN_BOXED(49598,16,FLEN) +NAN_BOXED(50242,16,FLEN) +NAN_BOXED(42582,16,FLEN) +NAN_BOXED(55809,16,FLEN) +NAN_BOXED(19620,16,FLEN) +NAN_BOXED(43971,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x2_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_1: + .fill 36*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x8_0: + .fill 48*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fcvt.w.h_b23-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fcvt.w.h_b23-01.S new file mode 100644 index 000000000..1e971f5fc --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fcvt.w.h_b23-01.S @@ -0,0 +1,428 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 06:00:03 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fcvt.w.h.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.w.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fcvt.w.h_b23 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fcvt.w.h_b23) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x12,test_dataset_0) +RVTEST_SIGBASE(x17,signature_x17_1) + +inst_0:// rs1==x30, rd==x21,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x21; op1val:0x77fc; valaddr_reg:x12; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x22; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x21, x30, dyn, 0, 0, x12, 0*FLEN/8, x25, x17, x22,FLREG) + +inst_1:// rs1==x23, rd==x20,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x23; dest:x20; op1val:0x77fc; valaddr_reg:x12; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x22; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.w.h, x20, x23, dyn, 32, 0, x12, 1*FLEN/8, x25, x17, x22,FLREG) + +inst_2:// rs1==x7, rd==x26,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x7; dest:x26; op1val:0x77fc; valaddr_reg:x12; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x22; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.w.h, x26, x7, dyn, 64, 0, x12, 2*FLEN/8, x25, x17, x22,FLREG) + +inst_3:// rs1==x21, rd==x1,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x21; dest:x1; op1val:0x77fc; valaddr_reg:x12; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x22; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.w.h, x1, x21, dyn, 96, 0, x12, 3*FLEN/8, x25, x17, x22,FLREG) + +inst_4:// rs1==x13, rd==x9,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x13; dest:x9; op1val:0x77fc; valaddr_reg:x12; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x22; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.w.h, x9, x13, dyn, 128, 0, x12, 4*FLEN/8, x25, x17, x22,FLREG) + +inst_5:// rs1==x16, rd==x2,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x16; dest:x2; op1val:0x77fd; valaddr_reg:x12; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x22; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x2, x16, dyn, 0, 0, x12, 5*FLEN/8, x25, x17, x22,FLREG) + +inst_6:// rs1==x9, rd==x30,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x9; dest:x30; op1val:0x77fd; valaddr_reg:x12; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x22; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.w.h, x30, x9, dyn, 32, 0, x12, 6*FLEN/8, x25, x17, x22,FLREG) + +inst_7:// rs1==x14, rd==x15,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x14; dest:x15; op1val:0x77fd; valaddr_reg:x12; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x22; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.w.h, x15, x14, dyn, 64, 0, x12, 7*FLEN/8, x25, x17, x22,FLREG) + +inst_8:// rs1==x19, rd==x13,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x19; dest:x13; op1val:0x77fd; valaddr_reg:x12; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x22; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.w.h, x13, x19, dyn, 96, 0, x12, 8*FLEN/8, x25, x17, x22,FLREG) + +inst_9:// rs1==x4, rd==x24,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x4; dest:x24; op1val:0x77fd; valaddr_reg:x12; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x22; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.w.h, x24, x4, dyn, 128, 0, x12, 9*FLEN/8, x25, x17, x22,FLREG) + +inst_10:// rs1==x3, rd==x14,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x3; dest:x14; op1val:0x77fe; valaddr_reg:x12; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x22; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x14, x3, dyn, 0, 0, x12, 10*FLEN/8, x25, x17, x22,FLREG) + +inst_11:// rs1==x26, rd==x0,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x26; dest:x0; op1val:0x77fe; valaddr_reg:x12; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x22; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.w.h, x0, x26, dyn, 32, 0, x12, 11*FLEN/8, x25, x17, x22,FLREG) + +inst_12:// rs1==x10, rd==x18,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x10; dest:x18; op1val:0x77fe; valaddr_reg:x12; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x22; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.w.h, x18, x10, dyn, 64, 0, x12, 12*FLEN/8, x25, x17, x22,FLREG) + +inst_13:// rs1==x6, rd==x11,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x6; dest:x11; op1val:0x77fe; valaddr_reg:x12; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x22; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.w.h, x11, x6, dyn, 96, 0, x12, 13*FLEN/8, x25, x17, x22,FLREG) + +inst_14:// rs1==x5, rd==x8,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x5; dest:x8; op1val:0x77fe; valaddr_reg:x12; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x22; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.w.h, x8, x5, dyn, 128, 0, x12, 14*FLEN/8, x25, x17, x22,FLREG) + +inst_15:// rs1==x28, rd==x23,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x28; dest:x23; op1val:0x77ff; valaddr_reg:x12; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x22; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x23, x28, dyn, 0, 0, x12, 15*FLEN/8, x25, x17, x22,FLREG) +RVTEST_VALBASEUPD(x13,test_dataset_1) + +inst_16:// rs1==x1, rd==x25,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x1; dest:x25; op1val:0x77ff; valaddr_reg:x13; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x22; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.w.h, x25, x1, dyn, 32, 0, x13, 0*FLEN/8, x14, x17, x22,FLREG) + +inst_17:// rs1==x12, rd==x16,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x12; dest:x16; op1val:0x77ff; valaddr_reg:x13; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x22; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.w.h, x16, x12, dyn, 64, 0, x13, 1*FLEN/8, x14, x17, x22,FLREG) + +inst_18:// rs1==x20, rd==x5,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x20; dest:x5; op1val:0x77ff; valaddr_reg:x13; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.w.h, x5, x20, dyn, 96, 0, x13, 2*FLEN/8, x14, x17, x9,FLREG) + +inst_19:// rs1==x0, rd==x31,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x0; dest:x31; op1val:0x0; valaddr_reg:x13; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.w.h, x31, x0, dyn, 128, 0, x13, 3*FLEN/8, x14, x17, x9,FLREG) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_20:// rs1==x24, rd==x10,fs1 == 0 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x24; dest:x10; op1val:0x7800; valaddr_reg:x13; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x10, x24, dyn, 0, 0, x13, 4*FLEN/8, x14, x1, x9,FLREG) + +inst_21:// rs1==x27, rd==x19,fs1 == 0 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x27; dest:x19; op1val:0x7800; valaddr_reg:x13; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.w.h, x19, x27, dyn, 32, 0, x13, 5*FLEN/8, x14, x1, x9,FLREG) + +inst_22:// rs1==x8, rd==x12,fs1 == 0 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x8; dest:x12; op1val:0x7800; valaddr_reg:x13; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.w.h, x12, x8, dyn, 64, 0, x13, 6*FLEN/8, x14, x1, x9,FLREG) + +inst_23:// rs1==x15, rd==x29,fs1 == 0 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x15; dest:x29; op1val:0x7800; valaddr_reg:x13; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.w.h, x29, x15, dyn, 96, 0, x13, 7*FLEN/8, x14, x1, x9,FLREG) + +inst_24:// rs1==x18, rd==x27,fs1 == 0 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x18; dest:x27; op1val:0x7800; valaddr_reg:x13; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.w.h, x27, x18, dyn, 128, 0, x13, 8*FLEN/8, x14, x1, x9,FLREG) + +inst_25:// rs1==x25, rd==x17,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x25; dest:x17; op1val:0x7801; valaddr_reg:x13; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x17, x25, dyn, 0, 0, x13, 9*FLEN/8, x14, x1, x9,FLREG) + +inst_26:// rs1==x17, rd==x7,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x17; dest:x7; op1val:0x7801; valaddr_reg:x13; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.w.h, x7, x17, dyn, 32, 0, x13, 10*FLEN/8, x14, x1, x9,FLREG) + +inst_27:// rs1==x2, rd==x22,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x2; dest:x22; op1val:0x7801; valaddr_reg:x13; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.w.h, x22, x2, dyn, 64, 0, x13, 11*FLEN/8, x14, x1, x9,FLREG) + +inst_28:// rs1==x11, rd==x3,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x11; dest:x3; op1val:0x7801; valaddr_reg:x13; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.w.h, x3, x11, dyn, 96, 0, x13, 12*FLEN/8, x14, x1, x9,FLREG) + +inst_29:// rs1==x31, rd==x4,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x31; dest:x4; op1val:0x7801; valaddr_reg:x13; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.w.h, x4, x31, dyn, 128, 0, x13, 13*FLEN/8, x14, x1, x9,FLREG) + +inst_30:// rs1==x29, rd==x6,fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x29; dest:x6; op1val:0x7802; valaddr_reg:x13; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x6, x29, dyn, 0, 0, x13, 14*FLEN/8, x14, x1, x9,FLREG) + +inst_31:// rs1==x22, rd==x28,fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x22; dest:x28; op1val:0x7802; valaddr_reg:x13; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.w.h, x28, x22, dyn, 32, 0, x13, 15*FLEN/8, x14, x1, x9,FLREG) + +inst_32:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0x7802; valaddr_reg:x13; +val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 64, 0, x13, 16*FLEN/8, x14, x1, x9,FLREG) +RVTEST_VALBASEUPD(x2,test_dataset_2) + +inst_33:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0x7802; valaddr_reg:x2; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 96, 0, x2, 0*FLEN/8, x3, x1, x9,FLREG) + +inst_34:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0x7802; valaddr_reg:x2; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 128, 0, x2, 1*FLEN/8, x3, x1, x9,FLREG) + +inst_35:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0x7803; valaddr_reg:x2; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 0, 0, x2, 2*FLEN/8, x3, x1, x9,FLREG) + +inst_36:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x003 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0x7803; valaddr_reg:x2; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 32, 0, x2, 3*FLEN/8, x3, x1, x9,FLREG) + +inst_37:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x003 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0x7803; valaddr_reg:x2; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 64, 0, x2, 4*FLEN/8, x3, x1, x9,FLREG) + +inst_38:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x003 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0x7803; valaddr_reg:x2; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 96, 0, x2, 5*FLEN/8, x3, x1, x9,FLREG) + +inst_39:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x003 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0x7803; valaddr_reg:x2; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 128, 0, x2, 6*FLEN/8, x3, x1, x9,FLREG) + +inst_40:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0x7804; valaddr_reg:x2; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 0, 0, x2, 7*FLEN/8, x3, x1, x9,FLREG) + +inst_41:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0x7804; valaddr_reg:x2; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 32, 0, x2, 8*FLEN/8, x3, x1, x9,FLREG) + +inst_42:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0x7804; valaddr_reg:x2; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 64, 0, x2, 9*FLEN/8, x3, x1, x9,FLREG) + +inst_43:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0x7804; valaddr_reg:x2; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 96, 0, x2, 10*FLEN/8, x3, x1, x9,FLREG) + +inst_44:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0x7804; valaddr_reg:x2; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 128, 0, x2, 11*FLEN/8, x3, x1, x9,FLREG) + +inst_45:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0x77fe; valaddr_reg:x2; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 32, 0, x2, 12*FLEN/8, x3, x1, x9,FLREG) + +inst_46:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0x77ff; valaddr_reg:x2; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 128, 0, x2, 13*FLEN/8, x3, x1, x9,FLREG) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(30716,32,FLEN) +NAN_BOXED(30716,32,FLEN) +NAN_BOXED(30716,32,FLEN) +NAN_BOXED(30716,32,FLEN) +NAN_BOXED(30716,32,FLEN) +NAN_BOXED(30717,32,FLEN) +NAN_BOXED(30717,32,FLEN) +NAN_BOXED(30717,32,FLEN) +NAN_BOXED(30717,32,FLEN) +NAN_BOXED(30717,32,FLEN) +NAN_BOXED(30718,32,FLEN) +NAN_BOXED(30718,32,FLEN) +NAN_BOXED(30718,32,FLEN) +NAN_BOXED(30718,32,FLEN) +NAN_BOXED(30718,32,FLEN) +NAN_BOXED(30719,32,FLEN) +test_dataset_1: +NAN_BOXED(30719,32,FLEN) +NAN_BOXED(30719,32,FLEN) +NAN_BOXED(30719,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(30720,32,FLEN) +NAN_BOXED(30720,32,FLEN) +NAN_BOXED(30720,32,FLEN) +NAN_BOXED(30720,32,FLEN) +NAN_BOXED(30720,32,FLEN) +NAN_BOXED(30721,32,FLEN) +NAN_BOXED(30721,32,FLEN) +NAN_BOXED(30721,32,FLEN) +NAN_BOXED(30721,32,FLEN) +NAN_BOXED(30721,32,FLEN) +NAN_BOXED(30722,32,FLEN) +NAN_BOXED(30722,32,FLEN) +NAN_BOXED(30722,32,FLEN) +test_dataset_2: +NAN_BOXED(30722,16,FLEN) +NAN_BOXED(30722,16,FLEN) +NAN_BOXED(30723,16,FLEN) +NAN_BOXED(30723,16,FLEN) +NAN_BOXED(30723,16,FLEN) +NAN_BOXED(30723,16,FLEN) +NAN_BOXED(30723,16,FLEN) +NAN_BOXED(30724,16,FLEN) +NAN_BOXED(30724,16,FLEN) +NAN_BOXED(30724,16,FLEN) +NAN_BOXED(30724,16,FLEN) +NAN_BOXED(30724,16,FLEN) +NAN_BOXED(30718,16,FLEN) +NAN_BOXED(30719,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x17_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x17_1: + .fill 40*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_0: + .fill 54*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fcvt.w.h_b24-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fcvt.w.h_b24-01.S new file mode 100644 index 000000000..5afc43b10 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fcvt.w.h_b24-01.S @@ -0,0 +1,846 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 06:00:03 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fcvt.w.h.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.w.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fcvt.w.h_b24 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fcvt.w.h_b24) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x14,signature_x14_1) + +inst_0:// rs1==x27, rd==x23,fs1 == 0 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x27; dest:x23; op1val:0x2f0a; valaddr_reg:x3; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x15; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x23, x27, dyn, 0, 0, x3, 0*FLEN/8, x7, x14, x15,FLREG) + +inst_1:// rs1==x8, rd==x9,fs1 == 0 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x8; dest:x9; op1val:0x2f0a; valaddr_reg:x3; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x15; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.w.h, x9, x8, dyn, 32, 0, x3, 1*FLEN/8, x7, x14, x15,FLREG) + +inst_2:// rs1==x30, rd==x20,fs1 == 0 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x20; op1val:0x2f0a; valaddr_reg:x3; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x15; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.w.h, x20, x30, dyn, 64, 0, x3, 2*FLEN/8, x7, x14, x15,FLREG) + +inst_3:// rs1==x1, rd==x30,fs1 == 0 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x1; dest:x30; op1val:0x2f0a; valaddr_reg:x3; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x15; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.w.h, x30, x1, dyn, 96, 0, x3, 3*FLEN/8, x7, x14, x15,FLREG) + +inst_4:// rs1==x2, rd==x13,fs1 == 0 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x2; dest:x13; op1val:0x2f0a; valaddr_reg:x3; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x15; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.w.h, x13, x2, dyn, 128, 0, x3, 4*FLEN/8, x7, x14, x15,FLREG) + +inst_5:// rs1==x12, rd==x24,fs1 == 0 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x12; dest:x24; op1val:0x211e; valaddr_reg:x3; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x15; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x24, x12, dyn, 0, 0, x3, 5*FLEN/8, x7, x14, x15,FLREG) + +inst_6:// rs1==x16, rd==x2,fs1 == 0 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x16; dest:x2; op1val:0x211e; valaddr_reg:x3; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x15; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.w.h, x2, x16, dyn, 32, 0, x3, 6*FLEN/8, x7, x14, x15,FLREG) + +inst_7:// rs1==x11, rd==x31,fs1 == 0 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x11; dest:x31; op1val:0x211e; valaddr_reg:x3; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x15; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.w.h, x31, x11, dyn, 64, 0, x3, 7*FLEN/8, x7, x14, x15,FLREG) + +inst_8:// rs1==x6, rd==x16,fs1 == 0 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x6; dest:x16; op1val:0x211e; valaddr_reg:x3; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x15; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.w.h, x16, x6, dyn, 96, 0, x3, 8*FLEN/8, x7, x14, x15,FLREG) + +inst_9:// rs1==x23, rd==x5,fs1 == 0 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x23; dest:x5; op1val:0x211e; valaddr_reg:x3; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x15; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.w.h, x5, x23, dyn, 128, 0, x3, 9*FLEN/8, x7, x14, x15,FLREG) + +inst_10:// rs1==x10, rd==x25,fs1 == 1 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x10; dest:x25; op1val:0xa11e; valaddr_reg:x3; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x15; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x25, x10, dyn, 0, 0, x3, 10*FLEN/8, x7, x14, x15,FLREG) + +inst_11:// rs1==x22, rd==x10,fs1 == 1 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x22; dest:x10; op1val:0xa11e; valaddr_reg:x3; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x15; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.w.h, x10, x22, dyn, 32, 0, x3, 11*FLEN/8, x7, x14, x15,FLREG) + +inst_12:// rs1==x21, rd==x4,fs1 == 1 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x21; dest:x4; op1val:0xa11e; valaddr_reg:x3; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x15; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.w.h, x4, x21, dyn, 64, 0, x3, 12*FLEN/8, x7, x14, x15,FLREG) + +inst_13:// rs1==x9, rd==x28,fs1 == 1 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x9; dest:x28; op1val:0xa11e; valaddr_reg:x3; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x15; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.w.h, x28, x9, dyn, 96, 0, x3, 13*FLEN/8, x7, x14, x15,FLREG) + +inst_14:// rs1==x28, rd==x1,fs1 == 1 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x28; dest:x1; op1val:0xa11e; valaddr_reg:x3; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x15; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.w.h, x1, x28, dyn, 128, 0, x3, 14*FLEN/8, x7, x14, x15,FLREG) + +inst_15:// rs1==x31, rd==x29,fs1 == 0 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x31; dest:x29; op1val:0x3c0a; valaddr_reg:x3; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x15; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x29, x31, dyn, 0, 0, x3, 15*FLEN/8, x7, x14, x15,FLREG) + +inst_16:// rs1==x25, rd==x26,fs1 == 0 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x25; dest:x26; op1val:0x3c0a; valaddr_reg:x3; +val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x15; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.w.h, x26, x25, dyn, 32, 0, x3, 16*FLEN/8, x7, x14, x15,FLREG) +RVTEST_VALBASEUPD(x9,test_dataset_1) + +inst_17:// rs1==x0, rd==x3,fs1 == 0 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x0; dest:x3; op1val:0x0; valaddr_reg:x9; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x15; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.w.h, x3, x0, dyn, 64, 0, x9, 0*FLEN/8, x10, x14, x15,FLREG) + +inst_18:// rs1==x26, rd==x0,fs1 == 0 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x26; dest:x0; op1val:0x3c0a; valaddr_reg:x9; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x15; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.w.h, x0, x26, dyn, 96, 0, x9, 1*FLEN/8, x10, x14, x15,FLREG) + +inst_19:// rs1==x7, rd==x12,fs1 == 0 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x7; dest:x12; op1val:0x3c0a; valaddr_reg:x9; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x15; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.w.h, x12, x7, dyn, 128, 0, x9, 2*FLEN/8, x10, x14, x15,FLREG) + +inst_20:// rs1==x19, rd==x15,fs1 == 1 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x19; dest:x15; op1val:0xbb33; valaddr_reg:x9; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x15, x19, dyn, 0, 0, x9, 3*FLEN/8, x10, x14, x2,FLREG) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_21:// rs1==x14, rd==x27,fs1 == 1 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x14; dest:x27; op1val:0xbb33; valaddr_reg:x9; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.w.h, x27, x14, dyn, 32, 0, x9, 4*FLEN/8, x10, x1, x2,FLREG) + +inst_22:// rs1==x4, rd==x21,fs1 == 1 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x4; dest:x21; op1val:0xbb33; valaddr_reg:x9; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.w.h, x21, x4, dyn, 64, 0, x9, 5*FLEN/8, x10, x1, x2,FLREG) + +inst_23:// rs1==x17, rd==x8,fs1 == 1 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x17; dest:x8; op1val:0xbb33; valaddr_reg:x9; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.w.h, x8, x17, dyn, 96, 0, x9, 6*FLEN/8, x10, x1, x2,FLREG) + +inst_24:// rs1==x3, rd==x22,fs1 == 1 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x3; dest:x22; op1val:0xbb33; valaddr_reg:x9; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.w.h, x22, x3, dyn, 128, 0, x9, 7*FLEN/8, x10, x1, x2,FLREG) + +inst_25:// rs1==x20, rd==x11,fs1 == 1 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x20; dest:x11; op1val:0xbc70; valaddr_reg:x9; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x11, x20, dyn, 0, 0, x9, 8*FLEN/8, x10, x1, x2,FLREG) + +inst_26:// rs1==x18, rd==x6,fs1 == 1 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x18; dest:x6; op1val:0xbc70; valaddr_reg:x9; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.w.h, x6, x18, dyn, 32, 0, x9, 9*FLEN/8, x10, x1, x2,FLREG) + +inst_27:// rs1==x29, rd==x17,fs1 == 1 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x29; dest:x17; op1val:0xbc70; valaddr_reg:x9; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.w.h, x17, x29, dyn, 64, 0, x9, 10*FLEN/8, x10, x1, x2,FLREG) + +inst_28:// rs1==x15, rd==x18,fs1 == 1 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x15; dest:x18; op1val:0xbc70; valaddr_reg:x9; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.w.h, x18, x15, dyn, 96, 0, x9, 11*FLEN/8, x10, x1, x2,FLREG) + +inst_29:// rs1==x13, rd==x19,fs1 == 1 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x13; dest:x19; op1val:0xbc70; valaddr_reg:x9; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.w.h, x19, x13, dyn, 128, 0, x9, 12*FLEN/8, x10, x1, x2,FLREG) + +inst_30:// rs1==x24, rd==x14,fs1 == 1 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x24; dest:x14; op1val:0xbb1e; valaddr_reg:x9; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x14, x24, dyn, 0, 0, x9, 13*FLEN/8, x10, x1, x2,FLREG) + +inst_31:// rs1==x5, rd==x7,fs1 == 1 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x5; dest:x7; op1val:0xbb1e; valaddr_reg:x9; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.w.h, x7, x5, dyn, 32, 0, x9, 14*FLEN/8, x10, x1, x2,FLREG) + +inst_32:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xbb1e; valaddr_reg:x9; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 64, 0, x9, 15*FLEN/8, x10, x1, x2,FLREG) + +inst_33:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xbb1e; valaddr_reg:x9; +val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 96, 0, x9, 16*FLEN/8, x10, x1, x2,FLREG) + +inst_34:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xbb1e; valaddr_reg:x9; +val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 128, 0, x9, 17*FLEN/8, x10, x1, x2,FLREG) + +inst_35:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xbc00; valaddr_reg:x9; +val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 0, 0, x9, 18*FLEN/8, x10, x1, x2,FLREG) + +inst_36:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xbc00; valaddr_reg:x9; +val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 32, 0, x9, 19*FLEN/8, x10, x1, x2,FLREG) + +inst_37:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xbc00; valaddr_reg:x9; +val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 64, 0, x9, 20*FLEN/8, x10, x1, x2,FLREG) + +inst_38:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xbc00; valaddr_reg:x9; +val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 96, 0, x9, 21*FLEN/8, x10, x1, x2,FLREG) + +inst_39:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xbc00; valaddr_reg:x9; +val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 128, 0, x9, 22*FLEN/8, x10, x1, x2,FLREG) + +inst_40:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xbbeb; valaddr_reg:x9; +val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 0, 0, x9, 23*FLEN/8, x10, x1, x2,FLREG) + +inst_41:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xbbeb; valaddr_reg:x9; +val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 32, 0, x9, 24*FLEN/8, x10, x1, x2,FLREG) + +inst_42:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xbbeb; valaddr_reg:x9; +val_offset:25*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 64, 0, x9, 25*FLEN/8, x10, x1, x2,FLREG) + +inst_43:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xbbeb; valaddr_reg:x9; +val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 96, 0, x9, 26*FLEN/8, x10, x1, x2,FLREG) + +inst_44:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xbbeb; valaddr_reg:x9; +val_offset:27*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 128, 0, x9, 27*FLEN/8, x10, x1, x2,FLREG) + +inst_45:// fs1 == 1 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xae66; valaddr_reg:x9; +val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 0, 0, x9, 28*FLEN/8, x10, x1, x2,FLREG) + +inst_46:// fs1 == 1 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xae66; valaddr_reg:x9; +val_offset:29*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 32, 0, x9, 29*FLEN/8, x10, x1, x2,FLREG) + +inst_47:// fs1 == 1 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xae66; valaddr_reg:x9; +val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 64, 0, x9, 30*FLEN/8, x10, x1, x2,FLREG) + +inst_48:// fs1 == 1 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xae66; valaddr_reg:x9; +val_offset:31*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 96, 0, x9, 31*FLEN/8, x10, x1, x2,FLREG) + +inst_49:// fs1 == 1 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xae66; valaddr_reg:x9; +val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 128, 0, x9, 32*FLEN/8, x10, x1, x2,FLREG) + +inst_50:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xf0; valaddr_reg:x9; +val_offset:33*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 0, 0, x9, 33*FLEN/8, x10, x1, x2,FLREG) + +inst_51:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xf0; valaddr_reg:x9; +val_offset:34*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 32, 0, x9, 34*FLEN/8, x10, x1, x2,FLREG) + +inst_52:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xf0; valaddr_reg:x9; +val_offset:35*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 64, 0, x9, 35*FLEN/8, x10, x1, x2,FLREG) + +inst_53:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xf0; valaddr_reg:x9; +val_offset:36*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 96, 0, x9, 36*FLEN/8, x10, x1, x2,FLREG) + +inst_54:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xf0; valaddr_reg:x9; +val_offset:37*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 128, 0, x9, 37*FLEN/8, x10, x1, x2,FLREG) + +inst_55:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0x3c00; valaddr_reg:x9; +val_offset:38*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 0, 0, x9, 38*FLEN/8, x10, x1, x2,FLREG) + +inst_56:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0x3c00; valaddr_reg:x9; +val_offset:39*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 32, 0, x9, 39*FLEN/8, x10, x1, x2,FLREG) + +inst_57:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0x3c00; valaddr_reg:x9; +val_offset:40*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 64, 0, x9, 40*FLEN/8, x10, x1, x2,FLREG) + +inst_58:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0x3c00; valaddr_reg:x9; +val_offset:41*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 96, 0, x9, 41*FLEN/8, x10, x1, x2,FLREG) + +inst_59:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0x3c00; valaddr_reg:x9; +val_offset:42*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 128, 0, x9, 42*FLEN/8, x10, x1, x2,FLREG) + +inst_60:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xbc0a; valaddr_reg:x9; +val_offset:43*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 0, 0, x9, 43*FLEN/8, x10, x1, x2,FLREG) + +inst_61:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xbc0a; valaddr_reg:x9; +val_offset:44*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 32, 0, x9, 44*FLEN/8, x10, x1, x2,FLREG) + +inst_62:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xbc0a; valaddr_reg:x9; +val_offset:45*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 64, 0, x9, 45*FLEN/8, x10, x1, x2,FLREG) + +inst_63:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xbc0a; valaddr_reg:x9; +val_offset:46*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 96, 0, x9, 46*FLEN/8, x10, x1, x2,FLREG) + +inst_64:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xbc0a; valaddr_reg:x9; +val_offset:47*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 128, 0, x9, 47*FLEN/8, x10, x1, x2,FLREG) + +inst_65:// fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0x2e66; valaddr_reg:x9; +val_offset:48*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 0, 0, x9, 48*FLEN/8, x10, x1, x2,FLREG) + +inst_66:// fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0x2e66; valaddr_reg:x9; +val_offset:49*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 32, 0, x9, 49*FLEN/8, x10, x1, x2,FLREG) + +inst_67:// fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0x2e66; valaddr_reg:x9; +val_offset:50*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 64, 0, x9, 50*FLEN/8, x10, x1, x2,FLREG) + +inst_68:// fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0x2e66; valaddr_reg:x9; +val_offset:51*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 96, 0, x9, 51*FLEN/8, x10, x1, x2,FLREG) + +inst_69:// fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0x2e66; valaddr_reg:x9; +val_offset:52*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 128, 0, x9, 52*FLEN/8, x10, x1, x2,FLREG) + +inst_70:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0x3beb; valaddr_reg:x9; +val_offset:53*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 0, 0, x9, 53*FLEN/8, x10, x1, x2,FLREG) + +inst_71:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0x3beb; valaddr_reg:x9; +val_offset:54*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 32, 0, x9, 54*FLEN/8, x10, x1, x2,FLREG) + +inst_72:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0x3beb; valaddr_reg:x9; +val_offset:55*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 64, 0, x9, 55*FLEN/8, x10, x1, x2,FLREG) + +inst_73:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0x3beb; valaddr_reg:x9; +val_offset:56*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 96, 0, x9, 56*FLEN/8, x10, x1, x2,FLREG) + +inst_74:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0x3beb; valaddr_reg:x9; +val_offset:57*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 128, 0, x9, 57*FLEN/8, x10, x1, x2,FLREG) + +inst_75:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0x3c66; valaddr_reg:x9; +val_offset:58*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 0, 0, x9, 58*FLEN/8, x10, x1, x2,FLREG) + +inst_76:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0x3c66; valaddr_reg:x9; +val_offset:59*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 32, 0, x9, 59*FLEN/8, x10, x1, x2,FLREG) + +inst_77:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0x3c66; valaddr_reg:x9; +val_offset:60*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 64, 0, x9, 60*FLEN/8, x10, x1, x2,FLREG) + +inst_78:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0x3c66; valaddr_reg:x9; +val_offset:61*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 96, 0, x9, 61*FLEN/8, x10, x1, x2,FLREG) + +inst_79:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0x3c66; valaddr_reg:x9; +val_offset:62*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 128, 0, x9, 62*FLEN/8, x10, x1, x2,FLREG) + +inst_80:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0x3b1e; valaddr_reg:x9; +val_offset:63*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 0, 0, x9, 63*FLEN/8, x10, x1, x2,FLREG) + +inst_81:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0x3b1e; valaddr_reg:x9; +val_offset:64*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 32, 0, x9, 64*FLEN/8, x10, x1, x2,FLREG) + +inst_82:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0x3b1e; valaddr_reg:x9; +val_offset:65*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 64, 0, x9, 65*FLEN/8, x10, x1, x2,FLREG) + +inst_83:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0x3b1e; valaddr_reg:x9; +val_offset:66*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 96, 0, x9, 66*FLEN/8, x10, x1, x2,FLREG) + +inst_84:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0x3b1e; valaddr_reg:x9; +val_offset:67*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 128, 0, x9, 67*FLEN/8, x10, x1, x2,FLREG) + +inst_85:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0x3b33; valaddr_reg:x9; +val_offset:68*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 0, 0, x9, 68*FLEN/8, x10, x1, x2,FLREG) + +inst_86:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0x3b33; valaddr_reg:x9; +val_offset:69*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 32, 0, x9, 69*FLEN/8, x10, x1, x2,FLREG) + +inst_87:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0x3b33; valaddr_reg:x9; +val_offset:70*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 64, 0, x9, 70*FLEN/8, x10, x1, x2,FLREG) + +inst_88:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0x3b33; valaddr_reg:x9; +val_offset:71*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 96, 0, x9, 71*FLEN/8, x10, x1, x2,FLREG) + +inst_89:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0x3b33; valaddr_reg:x9; +val_offset:72*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 128, 0, x9, 72*FLEN/8, x10, x1, x2,FLREG) + +inst_90:// fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xaf0a; valaddr_reg:x9; +val_offset:73*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 0, 0, x9, 73*FLEN/8, x10, x1, x2,FLREG) + +inst_91:// fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xaf0a; valaddr_reg:x9; +val_offset:74*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 32, 0, x9, 74*FLEN/8, x10, x1, x2,FLREG) + +inst_92:// fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xaf0a; valaddr_reg:x9; +val_offset:75*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 64, 0, x9, 75*FLEN/8, x10, x1, x2,FLREG) + +inst_93:// fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xaf0a; valaddr_reg:x9; +val_offset:76*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 96, 0, x9, 76*FLEN/8, x10, x1, x2,FLREG) + +inst_94:// fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xaf0a; valaddr_reg:x9; +val_offset:77*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 128, 0, x9, 77*FLEN/8, x10, x1, x2,FLREG) + +inst_95:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0x3c70; valaddr_reg:x9; +val_offset:78*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 0, 0, x9, 78*FLEN/8, x10, x1, x2,FLREG) + +inst_96:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0x3c70; valaddr_reg:x9; +val_offset:79*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 32, 0, x9, 79*FLEN/8, x10, x1, x2,FLREG) + +inst_97:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0x3c70; valaddr_reg:x9; +val_offset:80*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 64, 0, x9, 80*FLEN/8, x10, x1, x2,FLREG) + +inst_98:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0x3c70; valaddr_reg:x9; +val_offset:81*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 96, 0, x9, 81*FLEN/8, x10, x1, x2,FLREG) + +inst_99:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0x3c70; valaddr_reg:x9; +val_offset:82*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 128, 0, x9, 82*FLEN/8, x10, x1, x2,FLREG) + +inst_100:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xbc66; valaddr_reg:x9; +val_offset:83*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 0, 0, x9, 83*FLEN/8, x10, x1, x2,FLREG) + +inst_101:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xbc66; valaddr_reg:x9; +val_offset:84*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 32, 0, x9, 84*FLEN/8, x10, x1, x2,FLREG) + +inst_102:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xbc66; valaddr_reg:x9; +val_offset:85*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 64, 0, x9, 85*FLEN/8, x10, x1, x2,FLREG) + +inst_103:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xbc66; valaddr_reg:x9; +val_offset:86*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 96, 0, x9, 86*FLEN/8, x10, x1, x2,FLREG) + +inst_104:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xbc66; valaddr_reg:x9; +val_offset:87*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 128, 0, x9, 87*FLEN/8, x10, x1, x2,FLREG) + +inst_105:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0x3c0a; valaddr_reg:x9; +val_offset:88*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 64, 0, x9, 88*FLEN/8, x10, x1, x2,FLREG) + +inst_106:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0x3c0a; valaddr_reg:x9; +val_offset:89*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 96, 0, x9, 89*FLEN/8, x10, x1, x2,FLREG) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(12042,32,FLEN) +NAN_BOXED(12042,32,FLEN) +NAN_BOXED(12042,32,FLEN) +NAN_BOXED(12042,32,FLEN) +NAN_BOXED(12042,32,FLEN) +NAN_BOXED(8478,32,FLEN) +NAN_BOXED(8478,32,FLEN) +NAN_BOXED(8478,32,FLEN) +NAN_BOXED(8478,32,FLEN) +NAN_BOXED(8478,32,FLEN) +NAN_BOXED(41246,16,FLEN) +NAN_BOXED(41246,16,FLEN) +NAN_BOXED(41246,16,FLEN) +NAN_BOXED(41246,16,FLEN) +NAN_BOXED(41246,16,FLEN) +NAN_BOXED(15370,32,FLEN) +NAN_BOXED(15370,32,FLEN) +test_dataset_1: +NAN_BOXED(0,16,FLEN) +NAN_BOXED(15370,16,FLEN) +NAN_BOXED(15370,16,FLEN) +NAN_BOXED(47923,16,FLEN) +NAN_BOXED(47923,16,FLEN) +NAN_BOXED(47923,16,FLEN) +NAN_BOXED(47923,16,FLEN) +NAN_BOXED(47923,16,FLEN) +NAN_BOXED(48240,16,FLEN) +NAN_BOXED(48240,16,FLEN) +NAN_BOXED(48240,16,FLEN) +NAN_BOXED(48240,16,FLEN) +NAN_BOXED(48240,16,FLEN) +NAN_BOXED(47902,16,FLEN) +NAN_BOXED(47902,16,FLEN) +NAN_BOXED(47902,16,FLEN) +NAN_BOXED(47902,16,FLEN) +NAN_BOXED(47902,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48107,16,FLEN) +NAN_BOXED(48107,16,FLEN) +NAN_BOXED(48107,16,FLEN) +NAN_BOXED(48107,16,FLEN) +NAN_BOXED(48107,16,FLEN) +NAN_BOXED(44646,16,FLEN) +NAN_BOXED(44646,16,FLEN) +NAN_BOXED(44646,16,FLEN) +NAN_BOXED(44646,16,FLEN) +NAN_BOXED(44646,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(48138,16,FLEN) +NAN_BOXED(48138,16,FLEN) +NAN_BOXED(48138,16,FLEN) +NAN_BOXED(48138,16,FLEN) +NAN_BOXED(48138,16,FLEN) +NAN_BOXED(11878,16,FLEN) +NAN_BOXED(11878,16,FLEN) +NAN_BOXED(11878,16,FLEN) +NAN_BOXED(11878,16,FLEN) +NAN_BOXED(11878,16,FLEN) +NAN_BOXED(15339,16,FLEN) +NAN_BOXED(15339,16,FLEN) +NAN_BOXED(15339,16,FLEN) +NAN_BOXED(15339,16,FLEN) +NAN_BOXED(15339,16,FLEN) +NAN_BOXED(15462,16,FLEN) +NAN_BOXED(15462,16,FLEN) +NAN_BOXED(15462,16,FLEN) +NAN_BOXED(15462,16,FLEN) +NAN_BOXED(15462,16,FLEN) +NAN_BOXED(15134,16,FLEN) +NAN_BOXED(15134,16,FLEN) +NAN_BOXED(15134,16,FLEN) +NAN_BOXED(15134,16,FLEN) +NAN_BOXED(15134,16,FLEN) +NAN_BOXED(15155,16,FLEN) +NAN_BOXED(15155,16,FLEN) +NAN_BOXED(15155,16,FLEN) +NAN_BOXED(15155,16,FLEN) +NAN_BOXED(15155,16,FLEN) +NAN_BOXED(44810,16,FLEN) +NAN_BOXED(44810,16,FLEN) +NAN_BOXED(44810,16,FLEN) +NAN_BOXED(44810,16,FLEN) +NAN_BOXED(44810,16,FLEN) +NAN_BOXED(15472,16,FLEN) +NAN_BOXED(15472,16,FLEN) +NAN_BOXED(15472,16,FLEN) +NAN_BOXED(15472,16,FLEN) +NAN_BOXED(15472,16,FLEN) +NAN_BOXED(48230,16,FLEN) +NAN_BOXED(48230,16,FLEN) +NAN_BOXED(48230,16,FLEN) +NAN_BOXED(48230,16,FLEN) +NAN_BOXED(48230,16,FLEN) +NAN_BOXED(15370,16,FLEN) +NAN_BOXED(15370,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x14_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x14_1: + .fill 42*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_0: + .fill 172*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fcvt.w.h_b27-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fcvt.w.h_b27-01.S new file mode 100644 index 000000000..1dc31ce00 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fcvt.w.h_b27-01.S @@ -0,0 +1,321 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 06:00:03 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fcvt.w.h.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.w.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fcvt.w.h_b27 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fcvt.w.h_b27) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x11,test_dataset_0) +RVTEST_SIGBASE(x2,signature_x2_1) + +inst_0:// rs1==x20, rd==x22,fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x20; dest:x22; op1val:0x7c01; valaddr_reg:x11; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x22, x20, dyn, 0, 0, x11, 0*FLEN/8, x13, x2, x3,FLREG) + +inst_1:// rs1==x14, rd==x17,fs1 == 1 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x14; dest:x17; op1val:0xfc01; valaddr_reg:x11; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x17, x14, dyn, 0, 0, x11, 1*FLEN/8, x13, x2, x3,FLREG) + +inst_2:// rs1==x23, rd==x1,fs1 == 0 and fe1 == 0x1f and fm1 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x23; dest:x1; op1val:0x7d55; valaddr_reg:x11; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x1, x23, dyn, 0, 0, x11, 2*FLEN/8, x13, x2, x3,FLREG) + +inst_3:// rs1==x27, rd==x16,fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x27; dest:x16; op1val:0xfd55; valaddr_reg:x11; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x16, x27, dyn, 0, 0, x11, 3*FLEN/8, x13, x2, x3,FLREG) + +inst_4:// rs1==x18, rd==x28,fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x18; dest:x28; op1val:0x7e01; valaddr_reg:x11; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x28, x18, dyn, 0, 0, x11, 4*FLEN/8, x13, x2, x3,FLREG) + +inst_5:// rs1==x21, rd==x15,fs1 == 1 and fe1 == 0x1f and fm1 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x21; dest:x15; op1val:0xfe01; valaddr_reg:x11; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x15, x21, dyn, 0, 0, x11, 5*FLEN/8, x13, x2, x3,FLREG) + +inst_6:// rs1==x28, rd==x21,fs1 == 0 and fe1 == 0x1f and fm1 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x28; dest:x21; op1val:0x7e55; valaddr_reg:x11; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x21, x28, dyn, 0, 0, x11, 6*FLEN/8, x13, x2, x3,FLREG) + +inst_7:// rs1==x12, rd==x8,fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x12; dest:x8; op1val:0xfe55; valaddr_reg:x11; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x8, x12, dyn, 0, 0, x11, 7*FLEN/8, x13, x2, x3,FLREG) + +inst_8:// rs1==x9, rd==x29, +/* opcode: fcvt.w.h ; op1:x9; dest:x29; op1val:0x0; valaddr_reg:x11; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x29, x9, dyn, 0, 0, x11, 8*FLEN/8, x13, x2, x3,FLREG) + +inst_9:// rs1==x4, rd==x6, +/* opcode: fcvt.w.h ; op1:x4; dest:x6; op1val:0x0; valaddr_reg:x11; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x6, x4, dyn, 0, 0, x11, 9*FLEN/8, x13, x2, x3,FLREG) + +inst_10:// rs1==x10, rd==x5, +/* opcode: fcvt.w.h ; op1:x10; dest:x5; op1val:0x0; valaddr_reg:x11; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x5, x10, dyn, 0, 0, x11, 10*FLEN/8, x13, x2, x3,FLREG) + +inst_11:// rs1==x15, rd==x12, +/* opcode: fcvt.w.h ; op1:x15; dest:x12; op1val:0x0; valaddr_reg:x11; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x12, x15, dyn, 0, 0, x11, 11*FLEN/8, x13, x2, x3,FLREG) + +inst_12:// rs1==x5, rd==x30, +/* opcode: fcvt.w.h ; op1:x5; dest:x30; op1val:0x0; valaddr_reg:x11; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x30, x5, dyn, 0, 0, x11, 12*FLEN/8, x13, x2, x3,FLREG) + +inst_13:// rs1==x26, rd==x18, +/* opcode: fcvt.w.h ; op1:x26; dest:x18; op1val:0x0; valaddr_reg:x11; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x18, x26, dyn, 0, 0, x11, 13*FLEN/8, x13, x2, x3,FLREG) + +inst_14:// rs1==x17, rd==x25, +/* opcode: fcvt.w.h ; op1:x17; dest:x25; op1val:0x0; valaddr_reg:x11; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x25, x17, dyn, 0, 0, x11, 14*FLEN/8, x13, x2, x3,FLREG) + +inst_15:// rs1==x30, rd==x7, +/* opcode: fcvt.w.h ; op1:x30; dest:x7; op1val:0x0; valaddr_reg:x11; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x7, x30, dyn, 0, 0, x11, 15*FLEN/8, x13, x2, x3,FLREG) +RVTEST_VALBASEUPD(x12,test_dataset_1) + +inst_16:// rs1==x7, rd==x11, +/* opcode: fcvt.w.h ; op1:x7; dest:x11; op1val:0x0; valaddr_reg:x12; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x11, x7, dyn, 0, 0, x12, 0*FLEN/8, x15, x2, x3,FLREG) + +inst_17:// rs1==x19, rd==x13, +/* opcode: fcvt.w.h ; op1:x19; dest:x13; op1val:0x0; valaddr_reg:x12; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x13, x19, dyn, 0, 0, x12, 1*FLEN/8, x15, x2, x3,FLREG) +RVTEST_SIGBASE(x5,signature_x5_0) + +inst_18:// rs1==x16, rd==x4, +/* opcode: fcvt.w.h ; op1:x16; dest:x4; op1val:0x0; valaddr_reg:x12; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x4, x16, dyn, 0, 0, x12, 2*FLEN/8, x15, x5, x7,FLREG) + +inst_19:// rs1==x24, rd==x27, +/* opcode: fcvt.w.h ; op1:x24; dest:x27; op1val:0x0; valaddr_reg:x12; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x27, x24, dyn, 0, 0, x12, 3*FLEN/8, x15, x5, x7,FLREG) + +inst_20:// rs1==x25, rd==x26, +/* opcode: fcvt.w.h ; op1:x25; dest:x26; op1val:0x0; valaddr_reg:x12; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x26, x25, dyn, 0, 0, x12, 4*FLEN/8, x15, x5, x7,FLREG) + +inst_21:// rs1==x13, rd==x3, +/* opcode: fcvt.w.h ; op1:x13; dest:x3; op1val:0x0; valaddr_reg:x12; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x3, x13, dyn, 0, 0, x12, 5*FLEN/8, x15, x5, x7,FLREG) + +inst_22:// rs1==x3, rd==x20, +/* opcode: fcvt.w.h ; op1:x3; dest:x20; op1val:0x0; valaddr_reg:x12; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x20, x3, dyn, 0, 0, x12, 6*FLEN/8, x15, x5, x7,FLREG) + +inst_23:// rs1==x2, rd==x10, +/* opcode: fcvt.w.h ; op1:x2; dest:x10; op1val:0x0; valaddr_reg:x12; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x10, x2, dyn, 0, 0, x12, 7*FLEN/8, x15, x5, x7,FLREG) + +inst_24:// rs1==x6, rd==x23, +/* opcode: fcvt.w.h ; op1:x6; dest:x23; op1val:0x0; valaddr_reg:x12; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x23, x6, dyn, 0, 0, x12, 8*FLEN/8, x15, x5, x7,FLREG) + +inst_25:// rs1==x11, rd==x2, +/* opcode: fcvt.w.h ; op1:x11; dest:x2; op1val:0x0; valaddr_reg:x12; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x2, x11, dyn, 0, 0, x12, 9*FLEN/8, x15, x5, x7,FLREG) + +inst_26:// rs1==x8, rd==x31, +/* opcode: fcvt.w.h ; op1:x8; dest:x31; op1val:0x0; valaddr_reg:x12; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x31, x8, dyn, 0, 0, x12, 10*FLEN/8, x15, x5, x7,FLREG) + +inst_27:// rs1==x22, rd==x19, +/* opcode: fcvt.w.h ; op1:x22; dest:x19; op1val:0x0; valaddr_reg:x12; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x19, x22, dyn, 0, 0, x12, 11*FLEN/8, x15, x5, x7,FLREG) + +inst_28:// rs1==x0, rd==x14, +/* opcode: fcvt.w.h ; op1:x0; dest:x14; op1val:0x0; valaddr_reg:x12; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x14, x0, dyn, 0, 0, x12, 12*FLEN/8, x15, x5, x7,FLREG) + +inst_29:// rs1==x29, rd==x9, +/* opcode: fcvt.w.h ; op1:x29; dest:x9; op1val:0x0; valaddr_reg:x12; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x9, x29, dyn, 0, 0, x12, 13*FLEN/8, x15, x5, x7,FLREG) + +inst_30:// rs1==x31, rd==x0, +/* opcode: fcvt.w.h ; op1:x31; dest:x0; op1val:0x0; valaddr_reg:x12; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x0, x31, dyn, 0, 0, x12, 14*FLEN/8, x15, x5, x7,FLREG) + +inst_31:// rs1==x1, rd==x24, +/* opcode: fcvt.w.h ; op1:x1; dest:x24; op1val:0x0; valaddr_reg:x12; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x24, x1, dyn, 0, 0, x12, 15*FLEN/8, x15, x5, x7,FLREG) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(31745,32,FLEN) +NAN_BOXED(64513,16,FLEN) +NAN_BOXED(32085,32,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32257,32,FLEN) +NAN_BOXED(65025,16,FLEN) +NAN_BOXED(32341,32,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +test_dataset_1: +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x2_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_1: + .fill 36*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x5_0: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fcvt.w.h_b28-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fcvt.w.h_b28-01.S new file mode 100644 index 000000000..1509b5a86 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fcvt.w.h_b28-01.S @@ -0,0 +1,330 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 06:00:03 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fcvt.w.h.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.w.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fcvt.w.h_b28 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fcvt.w.h_b28) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x8,signature_x8_1) + +inst_0:// rs1==x0, rd==x19,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x0; dest:x19; op1val:0x0; valaddr_reg:x3; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x19, x0, dyn, 0, 0, x3, 0*FLEN/8, x10, x8, x9,FLREG) + +inst_1:// rs1==x19, rd==x15,fs1 == 0 and fe1 == 0x0e and fm1 == 0x092 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x19; dest:x15; op1val:0x3892; valaddr_reg:x3; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x15, x19, dyn, 0, 0, x3, 1*FLEN/8, x10, x8, x9,FLREG) + +inst_2:// rs1==x27, rd==x5,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x27; dest:x5; op1val:0x3c00; valaddr_reg:x3; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x5, x27, dyn, 0, 0, x3, 2*FLEN/8, x10, x8, x9,FLREG) + +inst_3:// rs1==x16, rd==x1,fs1 == 0 and fe1 == 0x0f and fm1 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x16; dest:x1; op1val:0x3d00; valaddr_reg:x3; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x1, x16, dyn, 0, 0, x3, 3*FLEN/8, x10, x8, x9,FLREG) + +inst_4:// rs1==x13, rd==x27,fs1 == 0 and fe1 == 0x0f and fm1 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x13; dest:x27; op1val:0x3e00; valaddr_reg:x3; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x27, x13, dyn, 0, 0, x3, 4*FLEN/8, x10, x8, x9,FLREG) + +inst_5:// rs1==x12, rd==x6,fs1 == 0 and fe1 == 0x0f and fm1 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x12; dest:x6; op1val:0x3f00; valaddr_reg:x3; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x6, x12, dyn, 0, 0, x3, 5*FLEN/8, x10, x8, x9,FLREG) + +inst_6:// rs1==x23, rd==x31,fs1 == 0 and fe1 == 0x10 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x23; dest:x31; op1val:0x4000; valaddr_reg:x3; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x31, x23, dyn, 0, 0, x3, 6*FLEN/8, x10, x8, x9,FLREG) + +inst_7:// rs1==x21, rd==x30,fs1 == 0 and fe1 == 0x10 and fm1 == 0x080 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x21; dest:x30; op1val:0x4080; valaddr_reg:x3; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x30, x21, dyn, 0, 0, x3, 7*FLEN/8, x10, x8, x9,FLREG) + +inst_8:// rs1==x5, rd==x11,fs1 == 0 and fe1 == 0x10 and fm1 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x5; dest:x11; op1val:0x4100; valaddr_reg:x3; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x11, x5, dyn, 0, 0, x3, 8*FLEN/8, x10, x8, x9,FLREG) + +inst_9:// rs1==x11, rd==x28,fs1 == 0 and fe1 == 0x10 and fm1 == 0x180 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x11; dest:x28; op1val:0x4180; valaddr_reg:x3; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x28, x11, dyn, 0, 0, x3, 9*FLEN/8, x10, x8, x9,FLREG) + +inst_10:// rs1==x4, rd==x2,fs1 == 0 and fe1 == 0x1c and fm1 == 0x2dc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x4; dest:x2; op1val:0x72dc; valaddr_reg:x3; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x2, x4, dyn, 0, 0, x3, 10*FLEN/8, x10, x8, x9,FLREG) + +inst_11:// rs1==x20, rd==x7,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x20; dest:x7; op1val:0x77ff; valaddr_reg:x3; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x7, x20, dyn, 0, 0, x3, 11*FLEN/8, x10, x8, x9,FLREG) + +inst_12:// rs1==x29, rd==x13,fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x29; dest:x13; op1val:0x7c00; valaddr_reg:x3; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x13, x29, dyn, 0, 0, x3, 12*FLEN/8, x10, x8, x9,FLREG) + +inst_13:// rs1==x18, rd==x14,fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x18; dest:x14; op1val:0x7c01; valaddr_reg:x3; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x14, x18, dyn, 0, 0, x3, 13*FLEN/8, x10, x8, x9,FLREG) + +inst_14:// rs1==x7, rd==x17,fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x7; dest:x17; op1val:0x7e01; valaddr_reg:x3; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x17, x7, dyn, 0, 0, x3, 14*FLEN/8, x10, x8, x9,FLREG) + +inst_15:// rs1==x24, rd==x12,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x24; dest:x12; op1val:0x8000; valaddr_reg:x3; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x12, x24, dyn, 0, 0, x3, 15*FLEN/8, x10, x8, x9,FLREG) +RVTEST_VALBASEUPD(x11,test_dataset_1) + +inst_16:// rs1==x3, rd==x22,fs1 == 1 and fe1 == 0x0d and fm1 == 0x2c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x3; dest:x22; op1val:0xb6c0; valaddr_reg:x11; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x22, x3, dyn, 0, 0, x11, 0*FLEN/8, x12, x8, x9,FLREG) + +inst_17:// rs1==x17, rd==x23,fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x17; dest:x23; op1val:0xbc00; valaddr_reg:x11; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x23, x17, dyn, 0, 0, x11, 1*FLEN/8, x12, x8, x7,FLREG) + +inst_18:// rs1==x25, rd==x26,fs1 == 1 and fe1 == 0x10 and fm1 == 0x180 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x25; dest:x26; op1val:0xc180; valaddr_reg:x11; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x26, x25, dyn, 0, 0, x11, 2*FLEN/8, x12, x8, x7,FLREG) +RVTEST_SIGBASE(x5,signature_x5_0) + +inst_19:// rs1==x10, rd==x24,fs1 == 1 and fe1 == 0x10 and fm1 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x10; dest:x24; op1val:0xc100; valaddr_reg:x11; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x24, x10, dyn, 0, 0, x11, 3*FLEN/8, x12, x5, x7,FLREG) + +inst_20:// rs1==x28, rd==x9,fs1 == 1 and fe1 == 0x10 and fm1 == 0x080 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x28; dest:x9; op1val:0xc080; valaddr_reg:x11; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x9, x28, dyn, 0, 0, x11, 4*FLEN/8, x12, x5, x7,FLREG) + +inst_21:// rs1==x30, rd==x18,fs1 == 1 and fe1 == 0x10 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x18; op1val:0xc000; valaddr_reg:x11; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x18, x30, dyn, 0, 0, x11, 5*FLEN/8, x12, x5, x7,FLREG) + +inst_22:// rs1==x1, rd==x21,fs1 == 1 and fe1 == 0x0f and fm1 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x1; dest:x21; op1val:0xbf00; valaddr_reg:x11; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x21, x1, dyn, 0, 0, x11, 6*FLEN/8, x12, x5, x7,FLREG) + +inst_23:// rs1==x31, rd==x25,fs1 == 1 and fe1 == 0x0f and fm1 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x31; dest:x25; op1val:0xbe00; valaddr_reg:x11; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x25, x31, dyn, 0, 0, x11, 7*FLEN/8, x12, x5, x7,FLREG) + +inst_24:// rs1==x6, rd==x0,fs1 == 1 and fe1 == 0x0f and fm1 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x6; dest:x0; op1val:0xbd00; valaddr_reg:x11; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x0, x6, dyn, 0, 0, x11, 8*FLEN/8, x12, x5, x7,FLREG) + +inst_25:// rs1==x8, rd==x10,fs1 == 1 and fe1 == 0x1d and fm1 == 0x259 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x8; dest:x10; op1val:0xf659; valaddr_reg:x11; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x10, x8, dyn, 0, 0, x11, 9*FLEN/8, x12, x5, x7,FLREG) + +inst_26:// rs1==x9, rd==x29,fs1 == 1 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x9; dest:x29; op1val:0xf800; valaddr_reg:x11; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x29, x9, dyn, 0, 0, x11, 10*FLEN/8, x12, x5, x7,FLREG) + +inst_27:// rs1==x2, rd==x16,fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x2; dest:x16; op1val:0xfc00; valaddr_reg:x11; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x16, x2, dyn, 0, 0, x11, 11*FLEN/8, x12, x5, x7,FLREG) + +inst_28:// rs1==x14, rd==x8, +/* opcode: fcvt.w.h ; op1:x14; dest:x8; op1val:0x0; valaddr_reg:x11; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x8, x14, dyn, 0, 0, x11, 12*FLEN/8, x12, x5, x7,FLREG) + +inst_29:// rs1==x26, rd==x4, +/* opcode: fcvt.w.h ; op1:x26; dest:x4; op1val:0x0; valaddr_reg:x11; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x4, x26, dyn, 0, 0, x11, 13*FLEN/8, x12, x5, x7,FLREG) + +inst_30:// rs1==x22, rd==x20, +/* opcode: fcvt.w.h ; op1:x22; dest:x20; op1val:0x0; valaddr_reg:x11; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x20, x22, dyn, 0, 0, x11, 14*FLEN/8, x12, x5, x7,FLREG) + +inst_31:// rs1==x15, rd==x3, +/* opcode: fcvt.w.h ; op1:x15; dest:x3; op1val:0x0; valaddr_reg:x11; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x3, x15, dyn, 0, 0, x11, 15*FLEN/8, x12, x5, x7,FLREG) +RVTEST_VALBASEUPD(x1,test_dataset_2) + +inst_32:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xbd00; valaddr_reg:x1; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 0, 0, x1, 0*FLEN/8, x2, x5, x7,FLREG) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(14482,32,FLEN) +NAN_BOXED(15360,32,FLEN) +NAN_BOXED(15616,32,FLEN) +NAN_BOXED(15872,32,FLEN) +NAN_BOXED(16128,32,FLEN) +NAN_BOXED(16384,32,FLEN) +NAN_BOXED(16512,32,FLEN) +NAN_BOXED(16640,32,FLEN) +NAN_BOXED(16768,32,FLEN) +NAN_BOXED(29404,32,FLEN) +NAN_BOXED(30719,32,FLEN) +NAN_BOXED(31744,32,FLEN) +NAN_BOXED(31745,32,FLEN) +NAN_BOXED(32257,32,FLEN) +NAN_BOXED(32768,16,FLEN) +test_dataset_1: +NAN_BOXED(46784,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(49536,16,FLEN) +NAN_BOXED(49408,16,FLEN) +NAN_BOXED(49280,16,FLEN) +NAN_BOXED(49152,16,FLEN) +NAN_BOXED(48896,16,FLEN) +NAN_BOXED(48640,16,FLEN) +NAN_BOXED(48384,16,FLEN) +NAN_BOXED(63065,16,FLEN) +NAN_BOXED(63488,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +test_dataset_2: +NAN_BOXED(48384,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x8_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x8_1: + .fill 38*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x5_0: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fcvt.w.h_b29-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fcvt.w.h_b29-01.S new file mode 100644 index 000000000..920b369ae --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fcvt.w.h_b29-01.S @@ -0,0 +1,671 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 06:00:03 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fcvt.w.h.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.w.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fcvt.w.h_b29 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fcvt.w.h_b29) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x12,test_dataset_0) +RVTEST_SIGBASE(x2,signature_x2_1) + +inst_0:// rs1==x13, rd==x15,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x13; dest:x15; op1val:0x3248; valaddr_reg:x12; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x17; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x15, x13, dyn, 0, 0, x12, 0*FLEN/8, x24, x2, x17,FLREG) + +inst_1:// rs1==x18, rd==x5,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x18; dest:x5; op1val:0x3248; valaddr_reg:x12; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x17; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.w.h, x5, x18, dyn, 32, 0, x12, 1*FLEN/8, x24, x2, x17,FLREG) + +inst_2:// rs1==x27, rd==x22,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x27; dest:x22; op1val:0x3248; valaddr_reg:x12; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x17; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.w.h, x22, x27, dyn, 64, 0, x12, 2*FLEN/8, x24, x2, x17,FLREG) + +inst_3:// rs1==x19, rd==x4,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x19; dest:x4; op1val:0x3248; valaddr_reg:x12; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x17; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.w.h, x4, x19, dyn, 96, 0, x12, 3*FLEN/8, x24, x2, x17,FLREG) + +inst_4:// rs1==x6, rd==x29,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x6; dest:x29; op1val:0x3248; valaddr_reg:x12; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x17; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.w.h, x29, x6, dyn, 128, 0, x12, 4*FLEN/8, x24, x2, x17,FLREG) + +inst_5:// rs1==x16, rd==x14,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x16; dest:x14; op1val:0x3249; valaddr_reg:x12; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x17; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x14, x16, dyn, 0, 0, x12, 5*FLEN/8, x24, x2, x17,FLREG) + +inst_6:// rs1==x3, rd==x1,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x3; dest:x1; op1val:0x3249; valaddr_reg:x12; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x17; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.w.h, x1, x3, dyn, 32, 0, x12, 6*FLEN/8, x24, x2, x17,FLREG) + +inst_7:// rs1==x15, rd==x11,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x15; dest:x11; op1val:0x3249; valaddr_reg:x12; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x17; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.w.h, x11, x15, dyn, 64, 0, x12, 7*FLEN/8, x24, x2, x17,FLREG) + +inst_8:// rs1==x9, rd==x23,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x9; dest:x23; op1val:0x3249; valaddr_reg:x12; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x17; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.w.h, x23, x9, dyn, 96, 0, x12, 8*FLEN/8, x24, x2, x17,FLREG) + +inst_9:// rs1==x8, rd==x3,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x8; dest:x3; op1val:0x3249; valaddr_reg:x12; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x17; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.w.h, x3, x8, dyn, 128, 0, x12, 9*FLEN/8, x24, x2, x17,FLREG) + +inst_10:// rs1==x5, rd==x21,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x5; dest:x21; op1val:0x324a; valaddr_reg:x12; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x17; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x21, x5, dyn, 0, 0, x12, 10*FLEN/8, x24, x2, x17,FLREG) + +inst_11:// rs1==x11, rd==x27,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x11; dest:x27; op1val:0x324a; valaddr_reg:x12; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x17; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.w.h, x27, x11, dyn, 32, 0, x12, 11*FLEN/8, x24, x2, x17,FLREG) + +inst_12:// rs1==x10, rd==x9,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x10; dest:x9; op1val:0x324a; valaddr_reg:x12; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x17; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.w.h, x9, x10, dyn, 64, 0, x12, 12*FLEN/8, x24, x2, x17,FLREG) + +inst_13:// rs1==x26, rd==x16,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x26; dest:x16; op1val:0x324a; valaddr_reg:x12; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x17; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.w.h, x16, x26, dyn, 96, 0, x12, 13*FLEN/8, x24, x2, x17,FLREG) + +inst_14:// rs1==x7, rd==x28,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x7; dest:x28; op1val:0x324a; valaddr_reg:x12; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x17; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.w.h, x28, x7, dyn, 128, 0, x12, 14*FLEN/8, x24, x2, x17,FLREG) + +inst_15:// rs1==x28, rd==x20,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x28; dest:x20; op1val:0x324b; valaddr_reg:x12; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x17; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x20, x28, dyn, 0, 0, x12, 15*FLEN/8, x24, x2, x17,FLREG) +RVTEST_VALBASEUPD(x5,test_dataset_1) + +inst_16:// rs1==x0, rd==x19,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x0; dest:x19; op1val:0x0; valaddr_reg:x5; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x17; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.w.h, x19, x0, dyn, 32, 0, x5, 0*FLEN/8, x9, x2, x17,FLREG) + +inst_17:// rs1==x14, rd==x30,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x14; dest:x30; op1val:0x324b; valaddr_reg:x5; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x17; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.w.h, x30, x14, dyn, 64, 0, x5, 1*FLEN/8, x9, x2, x17,FLREG) + +inst_18:// rs1==x4, rd==x12,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x4; dest:x12; op1val:0x324b; valaddr_reg:x5; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x17; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.w.h, x12, x4, dyn, 96, 0, x5, 2*FLEN/8, x9, x2, x17,FLREG) + +inst_19:// rs1==x23, rd==x31,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x23; dest:x31; op1val:0x324b; valaddr_reg:x5; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.w.h, x31, x23, dyn, 128, 0, x5, 3*FLEN/8, x9, x2, x4,FLREG) +RVTEST_SIGBASE(x3,signature_x3_0) + +inst_20:// rs1==x31, rd==x24,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x31; dest:x24; op1val:0x324c; valaddr_reg:x5; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x24, x31, dyn, 0, 0, x5, 4*FLEN/8, x9, x3, x4,FLREG) + +inst_21:// rs1==x1, rd==x7,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x1; dest:x7; op1val:0x324c; valaddr_reg:x5; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.w.h, x7, x1, dyn, 32, 0, x5, 5*FLEN/8, x9, x3, x4,FLREG) + +inst_22:// rs1==x22, rd==x25,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x22; dest:x25; op1val:0x324c; valaddr_reg:x5; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.w.h, x25, x22, dyn, 64, 0, x5, 6*FLEN/8, x9, x3, x4,FLREG) + +inst_23:// rs1==x21, rd==x13,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x21; dest:x13; op1val:0x324c; valaddr_reg:x5; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.w.h, x13, x21, dyn, 96, 0, x5, 7*FLEN/8, x9, x3, x4,FLREG) + +inst_24:// rs1==x20, rd==x0,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x20; dest:x0; op1val:0x324c; valaddr_reg:x5; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.w.h, x0, x20, dyn, 128, 0, x5, 8*FLEN/8, x9, x3, x4,FLREG) + +inst_25:// rs1==x2, rd==x8,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x2; dest:x8; op1val:0x324d; valaddr_reg:x5; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x8, x2, dyn, 0, 0, x5, 9*FLEN/8, x9, x3, x4,FLREG) + +inst_26:// rs1==x25, rd==x17,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x25; dest:x17; op1val:0x324d; valaddr_reg:x5; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.w.h, x17, x25, dyn, 32, 0, x5, 10*FLEN/8, x9, x3, x4,FLREG) + +inst_27:// rs1==x30, rd==x26,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x26; op1val:0x324d; valaddr_reg:x5; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.w.h, x26, x30, dyn, 64, 0, x5, 11*FLEN/8, x9, x3, x4,FLREG) + +inst_28:// rs1==x24, rd==x2,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x24; dest:x2; op1val:0x324d; valaddr_reg:x5; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.w.h, x2, x24, dyn, 96, 0, x5, 12*FLEN/8, x9, x3, x4,FLREG) + +inst_29:// rs1==x12, rd==x10,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x12; dest:x10; op1val:0x324d; valaddr_reg:x5; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.w.h, x10, x12, dyn, 128, 0, x5, 13*FLEN/8, x9, x3, x4,FLREG) + +inst_30:// rs1==x29, rd==x6,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x29; dest:x6; op1val:0x324e; valaddr_reg:x5; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x6, x29, dyn, 0, 0, x5, 14*FLEN/8, x9, x3, x4,FLREG) + +inst_31:// rs1==x17, rd==x18,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x17; dest:x18; op1val:0x324e; valaddr_reg:x5; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.w.h, x18, x17, dyn, 32, 0, x5, 15*FLEN/8, x9, x3, x4,FLREG) + +inst_32:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0x324e; valaddr_reg:x5; +val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 64, 0, x5, 16*FLEN/8, x9, x3, x4,FLREG) + +inst_33:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0x324e; valaddr_reg:x5; +val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 96, 0, x5, 17*FLEN/8, x9, x3, x4,FLREG) + +inst_34:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0x324e; valaddr_reg:x5; +val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 128, 0, x5, 18*FLEN/8, x9, x3, x4,FLREG) + +inst_35:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0x324f; valaddr_reg:x5; +val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 0, 0, x5, 19*FLEN/8, x9, x3, x4,FLREG) + +inst_36:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0x324f; valaddr_reg:x5; +val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 32, 0, x5, 20*FLEN/8, x9, x3, x4,FLREG) + +inst_37:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0x324f; valaddr_reg:x5; +val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 64, 0, x5, 21*FLEN/8, x9, x3, x4,FLREG) + +inst_38:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0x324f; valaddr_reg:x5; +val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 96, 0, x5, 22*FLEN/8, x9, x3, x4,FLREG) + +inst_39:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0x324f; valaddr_reg:x5; +val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 128, 0, x5, 23*FLEN/8, x9, x3, x4,FLREG) + +inst_40:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xb248; valaddr_reg:x5; +val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 0, 0, x5, 24*FLEN/8, x9, x3, x4,FLREG) + +inst_41:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xb248; valaddr_reg:x5; +val_offset:25*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 32, 0, x5, 25*FLEN/8, x9, x3, x4,FLREG) + +inst_42:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xb248; valaddr_reg:x5; +val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 64, 0, x5, 26*FLEN/8, x9, x3, x4,FLREG) + +inst_43:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xb248; valaddr_reg:x5; +val_offset:27*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 96, 0, x5, 27*FLEN/8, x9, x3, x4,FLREG) + +inst_44:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xb248; valaddr_reg:x5; +val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 128, 0, x5, 28*FLEN/8, x9, x3, x4,FLREG) + +inst_45:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xb249; valaddr_reg:x5; +val_offset:29*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 0, 0, x5, 29*FLEN/8, x9, x3, x4,FLREG) + +inst_46:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xb249; valaddr_reg:x5; +val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 32, 0, x5, 30*FLEN/8, x9, x3, x4,FLREG) + +inst_47:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xb249; valaddr_reg:x5; +val_offset:31*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 64, 0, x5, 31*FLEN/8, x9, x3, x4,FLREG) + +inst_48:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xb249; valaddr_reg:x5; +val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 96, 0, x5, 32*FLEN/8, x9, x3, x4,FLREG) + +inst_49:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xb249; valaddr_reg:x5; +val_offset:33*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 128, 0, x5, 33*FLEN/8, x9, x3, x4,FLREG) + +inst_50:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xb24a; valaddr_reg:x5; +val_offset:34*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 0, 0, x5, 34*FLEN/8, x9, x3, x4,FLREG) + +inst_51:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xb24a; valaddr_reg:x5; +val_offset:35*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 32, 0, x5, 35*FLEN/8, x9, x3, x4,FLREG) + +inst_52:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xb24a; valaddr_reg:x5; +val_offset:36*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 64, 0, x5, 36*FLEN/8, x9, x3, x4,FLREG) + +inst_53:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xb24a; valaddr_reg:x5; +val_offset:37*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 96, 0, x5, 37*FLEN/8, x9, x3, x4,FLREG) + +inst_54:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xb24a; valaddr_reg:x5; +val_offset:38*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 128, 0, x5, 38*FLEN/8, x9, x3, x4,FLREG) + +inst_55:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xb24b; valaddr_reg:x5; +val_offset:39*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 0, 0, x5, 39*FLEN/8, x9, x3, x4,FLREG) + +inst_56:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xb24b; valaddr_reg:x5; +val_offset:40*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 32, 0, x5, 40*FLEN/8, x9, x3, x4,FLREG) + +inst_57:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xb24b; valaddr_reg:x5; +val_offset:41*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 64, 0, x5, 41*FLEN/8, x9, x3, x4,FLREG) + +inst_58:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xb24b; valaddr_reg:x5; +val_offset:42*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 96, 0, x5, 42*FLEN/8, x9, x3, x4,FLREG) + +inst_59:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xb24b; valaddr_reg:x5; +val_offset:43*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 128, 0, x5, 43*FLEN/8, x9, x3, x4,FLREG) + +inst_60:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xb24c; valaddr_reg:x5; +val_offset:44*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 0, 0, x5, 44*FLEN/8, x9, x3, x4,FLREG) + +inst_61:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xb24c; valaddr_reg:x5; +val_offset:45*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 32, 0, x5, 45*FLEN/8, x9, x3, x4,FLREG) + +inst_62:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xb24c; valaddr_reg:x5; +val_offset:46*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 64, 0, x5, 46*FLEN/8, x9, x3, x4,FLREG) + +inst_63:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xb24c; valaddr_reg:x5; +val_offset:47*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 96, 0, x5, 47*FLEN/8, x9, x3, x4,FLREG) + +inst_64:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xb24c; valaddr_reg:x5; +val_offset:48*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 128, 0, x5, 48*FLEN/8, x9, x3, x4,FLREG) + +inst_65:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xb24d; valaddr_reg:x5; +val_offset:49*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 0, 0, x5, 49*FLEN/8, x9, x3, x4,FLREG) + +inst_66:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xb24d; valaddr_reg:x5; +val_offset:50*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 32, 0, x5, 50*FLEN/8, x9, x3, x4,FLREG) + +inst_67:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xb24d; valaddr_reg:x5; +val_offset:51*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 64, 0, x5, 51*FLEN/8, x9, x3, x4,FLREG) + +inst_68:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xb24d; valaddr_reg:x5; +val_offset:52*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 96, 0, x5, 52*FLEN/8, x9, x3, x4,FLREG) + +inst_69:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xb24d; valaddr_reg:x5; +val_offset:53*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 128, 0, x5, 53*FLEN/8, x9, x3, x4,FLREG) + +inst_70:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xb24e; valaddr_reg:x5; +val_offset:54*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 0, 0, x5, 54*FLEN/8, x9, x3, x4,FLREG) + +inst_71:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xb24e; valaddr_reg:x5; +val_offset:55*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 32, 0, x5, 55*FLEN/8, x9, x3, x4,FLREG) + +inst_72:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xb24e; valaddr_reg:x5; +val_offset:56*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 64, 0, x5, 56*FLEN/8, x9, x3, x4,FLREG) + +inst_73:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xb24e; valaddr_reg:x5; +val_offset:57*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 96, 0, x5, 57*FLEN/8, x9, x3, x4,FLREG) + +inst_74:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xb24e; valaddr_reg:x5; +val_offset:58*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 128, 0, x5, 58*FLEN/8, x9, x3, x4,FLREG) + +inst_75:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xb24f; valaddr_reg:x5; +val_offset:59*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 0, 0, x5, 59*FLEN/8, x9, x3, x4,FLREG) + +inst_76:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xb24f; valaddr_reg:x5; +val_offset:60*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 32, 0, x5, 60*FLEN/8, x9, x3, x4,FLREG) + +inst_77:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xb24f; valaddr_reg:x5; +val_offset:61*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 64, 0, x5, 61*FLEN/8, x9, x3, x4,FLREG) + +inst_78:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xb24f; valaddr_reg:x5; +val_offset:62*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 96, 0, x5, 62*FLEN/8, x9, x3, x4,FLREG) + +inst_79:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0xb24f; valaddr_reg:x5; +val_offset:63*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 128, 0, x5, 63*FLEN/8, x9, x3, x4,FLREG) + +inst_80:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0x324b; valaddr_reg:x5; +val_offset:64*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 32, 0, x5, 64*FLEN/8, x9, x3, x4,FLREG) + +inst_81:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.w.h ; op1:x30; dest:x31; op1val:0x324c; valaddr_reg:x5; +val_offset:65*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.w.h, x31, x30, dyn, 128, 0, x5, 65*FLEN/8, x9, x3, x4,FLREG) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(12872,32,FLEN) +NAN_BOXED(12872,32,FLEN) +NAN_BOXED(12872,32,FLEN) +NAN_BOXED(12872,32,FLEN) +NAN_BOXED(12872,32,FLEN) +NAN_BOXED(12873,32,FLEN) +NAN_BOXED(12873,32,FLEN) +NAN_BOXED(12873,32,FLEN) +NAN_BOXED(12873,32,FLEN) +NAN_BOXED(12873,32,FLEN) +NAN_BOXED(12874,32,FLEN) +NAN_BOXED(12874,32,FLEN) +NAN_BOXED(12874,32,FLEN) +NAN_BOXED(12874,32,FLEN) +NAN_BOXED(12874,32,FLEN) +NAN_BOXED(12875,32,FLEN) +test_dataset_1: +NAN_BOXED(0,16,FLEN) +NAN_BOXED(12875,16,FLEN) +NAN_BOXED(12875,16,FLEN) +NAN_BOXED(12875,16,FLEN) +NAN_BOXED(12876,16,FLEN) +NAN_BOXED(12876,16,FLEN) +NAN_BOXED(12876,16,FLEN) +NAN_BOXED(12876,16,FLEN) +NAN_BOXED(12876,16,FLEN) +NAN_BOXED(12877,16,FLEN) +NAN_BOXED(12877,16,FLEN) +NAN_BOXED(12877,16,FLEN) +NAN_BOXED(12877,16,FLEN) +NAN_BOXED(12877,16,FLEN) +NAN_BOXED(12878,16,FLEN) +NAN_BOXED(12878,16,FLEN) +NAN_BOXED(12878,16,FLEN) +NAN_BOXED(12878,16,FLEN) +NAN_BOXED(12878,16,FLEN) +NAN_BOXED(12879,16,FLEN) +NAN_BOXED(12879,16,FLEN) +NAN_BOXED(12879,16,FLEN) +NAN_BOXED(12879,16,FLEN) +NAN_BOXED(12879,16,FLEN) +NAN_BOXED(45640,16,FLEN) +NAN_BOXED(45640,16,FLEN) +NAN_BOXED(45640,16,FLEN) +NAN_BOXED(45640,16,FLEN) +NAN_BOXED(45640,16,FLEN) +NAN_BOXED(45641,16,FLEN) +NAN_BOXED(45641,16,FLEN) +NAN_BOXED(45641,16,FLEN) +NAN_BOXED(45641,16,FLEN) +NAN_BOXED(45641,16,FLEN) +NAN_BOXED(45642,16,FLEN) +NAN_BOXED(45642,16,FLEN) +NAN_BOXED(45642,16,FLEN) +NAN_BOXED(45642,16,FLEN) +NAN_BOXED(45642,16,FLEN) +NAN_BOXED(45643,16,FLEN) +NAN_BOXED(45643,16,FLEN) +NAN_BOXED(45643,16,FLEN) +NAN_BOXED(45643,16,FLEN) +NAN_BOXED(45643,16,FLEN) +NAN_BOXED(45644,16,FLEN) +NAN_BOXED(45644,16,FLEN) +NAN_BOXED(45644,16,FLEN) +NAN_BOXED(45644,16,FLEN) +NAN_BOXED(45644,16,FLEN) +NAN_BOXED(45645,16,FLEN) +NAN_BOXED(45645,16,FLEN) +NAN_BOXED(45645,16,FLEN) +NAN_BOXED(45645,16,FLEN) +NAN_BOXED(45645,16,FLEN) +NAN_BOXED(45646,16,FLEN) +NAN_BOXED(45646,16,FLEN) +NAN_BOXED(45646,16,FLEN) +NAN_BOXED(45646,16,FLEN) +NAN_BOXED(45646,16,FLEN) +NAN_BOXED(45647,16,FLEN) +NAN_BOXED(45647,16,FLEN) +NAN_BOXED(45647,16,FLEN) +NAN_BOXED(45647,16,FLEN) +NAN_BOXED(45647,16,FLEN) +NAN_BOXED(12875,16,FLEN) +NAN_BOXED(12876,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x2_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_1: + .fill 40*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x3_0: + .fill 124*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fcvt.wu.h_b1-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fcvt.wu.h_b1-01.S new file mode 100644 index 000000000..48289195e --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fcvt.wu.h_b1-01.S @@ -0,0 +1,337 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 06:01:25 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fcvt.wu.h.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.wu.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fcvt.wu.h_b1 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fcvt.wu.h_b1) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x5,signature_x5_1) + +inst_0:// rs1==x28, rd==x6,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x28; dest:x6; op1val:0x0; valaddr_reg:x3; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x6, x28, dyn, 0, 0, x3, 0*FLEN/8, x8, x5, x7,FLREG) + +inst_1:// rs1==x20, rd==x13,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x20; dest:x13; op1val:0x8000; valaddr_reg:x3; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x13, x20, dyn, 0, 0, x3, 1*FLEN/8, x8, x5, x7,FLREG) + +inst_2:// rs1==x1, rd==x28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x1; dest:x28; op1val:0x1; valaddr_reg:x3; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x28, x1, dyn, 0, 0, x3, 2*FLEN/8, x8, x5, x7,FLREG) + +inst_3:// rs1==x9, rd==x1,fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x9; dest:x1; op1val:0x8001; valaddr_reg:x3; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x1, x9, dyn, 0, 0, x3, 3*FLEN/8, x8, x5, x7,FLREG) + +inst_4:// rs1==x2, rd==x25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x2; dest:x25; op1val:0x2; valaddr_reg:x3; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x25, x2, dyn, 0, 0, x3, 4*FLEN/8, x8, x5, x7,FLREG) + +inst_5:// rs1==x17, rd==x4,fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x17; dest:x4; op1val:0x83fe; valaddr_reg:x3; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x4, x17, dyn, 0, 0, x3, 5*FLEN/8, x8, x5, x7,FLREG) + +inst_6:// rs1==x30, rd==x0,fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x0; op1val:0x3ff; valaddr_reg:x3; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x0, x30, dyn, 0, 0, x3, 6*FLEN/8, x8, x5, x7,FLREG) + +inst_7:// rs1==x26, rd==x19,fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x26; dest:x19; op1val:0x83ff; valaddr_reg:x3; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x19, x26, dyn, 0, 0, x3, 7*FLEN/8, x8, x5, x7,FLREG) + +inst_8:// rs1==x19, rd==x26,fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x19; dest:x26; op1val:0x400; valaddr_reg:x3; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x26, x19, dyn, 0, 0, x3, 8*FLEN/8, x8, x5, x7,FLREG) + +inst_9:// rs1==x27, rd==x21,fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x27; dest:x21; op1val:0x8400; valaddr_reg:x3; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x21, x27, dyn, 0, 0, x3, 9*FLEN/8, x8, x5, x7,FLREG) + +inst_10:// rs1==x25, rd==x24,fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x25; dest:x24; op1val:0x401; valaddr_reg:x3; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x24, x25, dyn, 0, 0, x3, 10*FLEN/8, x8, x5, x7,FLREG) + +inst_11:// rs1==x18, rd==x12,fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x18; dest:x12; op1val:0x8455; valaddr_reg:x3; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x12, x18, dyn, 0, 0, x3, 11*FLEN/8, x8, x5, x7,FLREG) + +inst_12:// rs1==x10, rd==x29,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x10; dest:x29; op1val:0x7bff; valaddr_reg:x3; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x29, x10, dyn, 0, 0, x3, 12*FLEN/8, x8, x5, x7,FLREG) + +inst_13:// rs1==x13, rd==x15,fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x13; dest:x15; op1val:0xfbff; valaddr_reg:x3; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x15, x13, dyn, 0, 0, x3, 13*FLEN/8, x8, x5, x7,FLREG) + +inst_14:// rs1==x23, rd==x31,fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x23; dest:x31; op1val:0x7c00; valaddr_reg:x3; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x31, x23, dyn, 0, 0, x3, 14*FLEN/8, x8, x5, x7,FLREG) + +inst_15:// rs1==x11, rd==x22,fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x11; dest:x22; op1val:0xfc00; valaddr_reg:x3; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x22, x11, dyn, 0, 0, x3, 15*FLEN/8, x8, x5, x7,FLREG) +RVTEST_VALBASEUPD(x19,test_dataset_1) + +inst_16:// rs1==x24, rd==x30,fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x24; dest:x30; op1val:0x7e00; valaddr_reg:x19; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x30, x24, dyn, 0, 0, x19, 0*FLEN/8, x21, x5, x7,FLREG) + +inst_17:// rs1==x15, rd==x20,fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x15; dest:x20; op1val:0xfe00; valaddr_reg:x19; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x20, x15, dyn, 0, 0, x19, 1*FLEN/8, x21, x5, x7,FLREG) + +inst_18:// rs1==x29, rd==x3,fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x29; dest:x3; op1val:0x7e01; valaddr_reg:x19; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x3, x29, dyn, 0, 0, x19, 2*FLEN/8, x21, x5, x7,FLREG) + +inst_19:// rs1==x4, rd==x27,fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x4; dest:x27; op1val:0xfe55; valaddr_reg:x19; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x27, x4, dyn, 0, 0, x19, 3*FLEN/8, x21, x5, x13,FLREG) + +inst_20:// rs1==x0, rd==x2,fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x0; dest:x2; op1val:0x0; valaddr_reg:x19; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x2, x0, dyn, 0, 0, x19, 4*FLEN/8, x21, x5, x13,FLREG) + +inst_21:// rs1==x12, rd==x9,fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x12; dest:x9; op1val:0xfd55; valaddr_reg:x19; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x9, x12, dyn, 0, 0, x19, 5*FLEN/8, x21, x5, x13,FLREG) + +inst_22:// rs1==x16, rd==x14,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x16; dest:x14; op1val:0x3c00; valaddr_reg:x19; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x14, x16, dyn, 0, 0, x19, 6*FLEN/8, x21, x5, x13,FLREG) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_23:// rs1==x8, rd==x7,fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x8; dest:x7; op1val:0xbc00; valaddr_reg:x19; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x7, x8, dyn, 0, 0, x19, 7*FLEN/8, x21, x1, x13,FLREG) + +inst_24:// rs1==x22, rd==x23, +/* opcode: fcvt.wu.h ; op1:x22; dest:x23; op1val:0x0; valaddr_reg:x19; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x23, x22, dyn, 0, 0, x19, 8*FLEN/8, x21, x1, x13,FLREG) + +inst_25:// rs1==x5, rd==x16, +/* opcode: fcvt.wu.h ; op1:x5; dest:x16; op1val:0x0; valaddr_reg:x19; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x16, x5, dyn, 0, 0, x19, 9*FLEN/8, x21, x1, x13,FLREG) + +inst_26:// rs1==x6, rd==x8, +/* opcode: fcvt.wu.h ; op1:x6; dest:x8; op1val:0x0; valaddr_reg:x19; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x8, x6, dyn, 0, 0, x19, 10*FLEN/8, x21, x1, x13,FLREG) + +inst_27:// rs1==x31, rd==x11, +/* opcode: fcvt.wu.h ; op1:x31; dest:x11; op1val:0x0; valaddr_reg:x19; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x11, x31, dyn, 0, 0, x19, 11*FLEN/8, x21, x1, x13,FLREG) + +inst_28:// rs1==x7, rd==x10, +/* opcode: fcvt.wu.h ; op1:x7; dest:x10; op1val:0x0; valaddr_reg:x19; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x10, x7, dyn, 0, 0, x19, 12*FLEN/8, x21, x1, x13,FLREG) + +inst_29:// rs1==x14, rd==x18, +/* opcode: fcvt.wu.h ; op1:x14; dest:x18; op1val:0x0; valaddr_reg:x19; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x18, x14, dyn, 0, 0, x19, 13*FLEN/8, x21, x1, x13,FLREG) + +inst_30:// rs1==x3, rd==x17, +/* opcode: fcvt.wu.h ; op1:x3; dest:x17; op1val:0x0; valaddr_reg:x19; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x17, x3, dyn, 0, 0, x19, 14*FLEN/8, x21, x1, x13,FLREG) +RVTEST_VALBASEUPD(x2,test_dataset_2) + +inst_31:// rs1==x21, rd==x5, +/* opcode: fcvt.wu.h ; op1:x21; dest:x5; op1val:0x0; valaddr_reg:x2; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x5, x21, dyn, 0, 0, x2, 0*FLEN/8, x3, x1, x13,FLREG) + +inst_32:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x3ff; valaddr_reg:x2; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 0, 0, x2, 1*FLEN/8, x3, x1, x13,FLREG) + +inst_33:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x7c01; valaddr_reg:x2; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 0, 0, x2, 2*FLEN/8, x3, x1, x13,FLREG) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1,32,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(2,32,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(1023,32,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(1024,32,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(1025,32,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31744,32,FLEN) +NAN_BOXED(64512,16,FLEN) +test_dataset_1: +NAN_BOXED(32256,32,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(32257,32,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(15360,32,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +test_dataset_2: +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(31745,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x5_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x5_1: + .fill 46*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_0: + .fill 22*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fcvt.wu.h_b22-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fcvt.wu.h_b22-01.S new file mode 100644 index 000000000..4537f5d4e --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fcvt.wu.h_b22-01.S @@ -0,0 +1,393 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 06:01:25 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fcvt.wu.h.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.wu.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fcvt.wu.h_b22 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fcvt.wu.h_b22) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x11,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0:// rs1==x21, rd==x31,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x21; dest:x31; op1val:0x3249; valaddr_reg:x11; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x31, x21, dyn, 0, 0, x11, 0*FLEN/8, x14, x1, x2,FLREG) + +inst_1:// rs1==x8, rd==x3,fs1 == 0 and fe1 == 0x0d and fm1 == 0x1b7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x8; dest:x3; op1val:0x35b7; valaddr_reg:x11; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x3, x8, dyn, 0, 0, x11, 1*FLEN/8, x14, x1, x2,FLREG) + +inst_2:// rs1==x4, rd==x6,fs1 == 0 and fe1 == 0x0e and fm1 == 0x24f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x4; dest:x6; op1val:0x3a4f; valaddr_reg:x11; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x6, x4, dyn, 0, 0, x11, 2*FLEN/8, x14, x1, x2,FLREG) + +inst_3:// rs1==x5, rd==x29,fs1 == 0 and fe1 == 0x0f and fm1 == 0x0d3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x5; dest:x29; op1val:0x3cd3; valaddr_reg:x11; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x29, x5, dyn, 0, 0, x11, 3*FLEN/8, x14, x1, x2,FLREG) + +inst_4:// rs1==x23, rd==x28,fs1 == 0 and fe1 == 0x10 and fm1 == 0x340 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x23; dest:x28; op1val:0x4340; valaddr_reg:x11; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x28, x23, dyn, 0, 0, x11, 4*FLEN/8, x14, x1, x2,FLREG) + +inst_5:// rs1==x19, rd==x4,fs1 == 0 and fe1 == 0x11 and fm1 == 0x34b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x19; dest:x4; op1val:0x474b; valaddr_reg:x11; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x4, x19, dyn, 0, 0, x11, 5*FLEN/8, x14, x1, x2,FLREG) + +inst_6:// rs1==x15, rd==x9,fs1 == 1 and fe1 == 0x12 and fm1 == 0x29d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x15; dest:x9; op1val:0xca9d; valaddr_reg:x11; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x9, x15, dyn, 0, 0, x11, 6*FLEN/8, x14, x1, x2,FLREG) + +inst_7:// rs1==x0, rd==x20,fs1 == 0 and fe1 == 0x13 and fm1 == 0x0a4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x0; dest:x20; op1val:0x0; valaddr_reg:x11; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x20, x0, dyn, 0, 0, x11, 7*FLEN/8, x14, x1, x2,FLREG) + +inst_8:// rs1==x18, rd==x21,fs1 == 0 and fe1 == 0x14 and fm1 == 0x215 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x18; dest:x21; op1val:0x5215; valaddr_reg:x11; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x21, x18, dyn, 0, 0, x11, 8*FLEN/8, x14, x1, x2,FLREG) + +inst_9:// rs1==x27, rd==x12,fs1 == 0 and fe1 == 0x15 and fm1 == 0x14f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x27; dest:x12; op1val:0x554f; valaddr_reg:x11; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x12, x27, dyn, 0, 0, x11, 9*FLEN/8, x14, x1, x2,FLREG) + +inst_10:// rs1==x17, rd==x25,fs1 == 1 and fe1 == 0x16 and fm1 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x17; dest:x25; op1val:0xd8ff; valaddr_reg:x11; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x25, x17, dyn, 0, 0, x11, 10*FLEN/8, x14, x1, x2,FLREG) + +inst_11:// rs1==x7, rd==x13,fs1 == 1 and fe1 == 0x17 and fm1 == 0x3cf and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x7; dest:x13; op1val:0xdfcf; valaddr_reg:x11; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x13, x7, dyn, 0, 0, x11, 11*FLEN/8, x14, x1, x2,FLREG) + +inst_12:// rs1==x9, rd==x24,fs1 == 0 and fe1 == 0x18 and fm1 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x9; dest:x24; op1val:0x63fc; valaddr_reg:x11; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x24, x9, dyn, 0, 0, x11, 12*FLEN/8, x14, x1, x2,FLREG) + +inst_13:// rs1==x31, rd==x30,fs1 == 0 and fe1 == 0x19 and fm1 == 0x02d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x31; dest:x30; op1val:0x642d; valaddr_reg:x11; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x30, x31, dyn, 0, 0, x11, 13*FLEN/8, x14, x1, x2,FLREG) + +inst_14:// rs1==x10, rd==x16,fs1 == 0 and fe1 == 0x1a and fm1 == 0x370 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x10; dest:x16; op1val:0x6b70; valaddr_reg:x11; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x16, x10, dyn, 0, 0, x11, 14*FLEN/8, x14, x1, x2,FLREG) +RVTEST_VALBASEUPD(x19,test_dataset_1) + +inst_15:// rs1==x28, rd==x10,fs1 == 0 and fe1 == 0x1b and fm1 == 0x269 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x28; dest:x10; op1val:0x6e69; valaddr_reg:x19; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x10, x28, dyn, 0, 0, x19, 0*FLEN/8, x21, x1, x2,FLREG) + +inst_16:// rs1==x12, rd==x15,fs1 == 0 and fe1 == 0x1c and fm1 == 0x186 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x12; dest:x15; op1val:0x7186; valaddr_reg:x19; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x15, x12, dyn, 0, 0, x19, 1*FLEN/8, x21, x1, x2,FLREG) + +inst_17:// rs1==x16, rd==x26,fs1 == 1 and fe1 == 0x1d and fm1 == 0x122 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x16; dest:x26; op1val:0xf522; valaddr_reg:x19; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x26, x16, dyn, 0, 0, x19, 2*FLEN/8, x21, x1, x2,FLREG) + +inst_18:// rs1==x13, rd==x18,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x13; dest:x18; op1val:0x7ab3; valaddr_reg:x19; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x18, x13, dyn, 0, 0, x19, 3*FLEN/8, x21, x1, x9,FLREG) + +inst_19:// rs1==x14, rd==x23,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x14; dest:x23; op1val:0x7bff; valaddr_reg:x19; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x23, x14, dyn, 0, 0, x19, 4*FLEN/8, x21, x1, x9,FLREG) +RVTEST_SIGBASE(x4,signature_x4_0) + +inst_20:// rs1==x11, rd==x0,fs1 == 1 and fe1 == 0x00 and fm1 == 0x2be and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x11; dest:x0; op1val:0x82be; valaddr_reg:x19; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x0, x11, dyn, 0, 0, x19, 5*FLEN/8, x21, x4, x9,FLREG) + +inst_21:// rs1==x26, rd==x1,fs1 == 1 and fe1 == 0x01 and fm1 == 0x2a5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x26; dest:x1; op1val:0x86a5; valaddr_reg:x19; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x1, x26, dyn, 0, 0, x19, 6*FLEN/8, x21, x4, x9,FLREG) + +inst_22:// rs1==x22, rd==x11,fs1 == 1 and fe1 == 0x02 and fm1 == 0x088 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x22; dest:x11; op1val:0x8888; valaddr_reg:x19; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x11, x22, dyn, 0, 0, x19, 7*FLEN/8, x21, x4, x9,FLREG) + +inst_23:// rs1==x1, rd==x5,fs1 == 1 and fe1 == 0x03 and fm1 == 0x312 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x1; dest:x5; op1val:0x8f12; valaddr_reg:x19; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x5, x1, dyn, 0, 0, x19, 8*FLEN/8, x21, x4, x9,FLREG) + +inst_24:// rs1==x25, rd==x2,fs1 == 1 and fe1 == 0x04 and fm1 == 0x3ed and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x25; dest:x2; op1val:0x93ed; valaddr_reg:x19; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x2, x25, dyn, 0, 0, x19, 9*FLEN/8, x21, x4, x9,FLREG) + +inst_25:// rs1==x2, rd==x7,fs1 == 1 and fe1 == 0x05 and fm1 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x2; dest:x7; op1val:0x97e0; valaddr_reg:x19; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x7, x2, dyn, 0, 0, x19, 10*FLEN/8, x21, x4, x9,FLREG) + +inst_26:// rs1==x29, rd==x14,fs1 == 1 and fe1 == 0x06 and fm1 == 0x274 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x29; dest:x14; op1val:0x9a74; valaddr_reg:x19; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x14, x29, dyn, 0, 0, x19, 11*FLEN/8, x21, x4, x9,FLREG) + +inst_27:// rs1==x6, rd==x8,fs1 == 1 and fe1 == 0x07 and fm1 == 0x02d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x6; dest:x8; op1val:0x9c2d; valaddr_reg:x19; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x8, x6, dyn, 0, 0, x19, 12*FLEN/8, x21, x4, x9,FLREG) + +inst_28:// rs1==x24, rd==x22,fs1 == 1 and fe1 == 0x08 and fm1 == 0x004 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x24; dest:x22; op1val:0xa004; valaddr_reg:x19; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x22, x24, dyn, 0, 0, x19, 13*FLEN/8, x21, x4, x9,FLREG) + +inst_29:// rs1==x20, rd==x27,fs1 == 1 and fe1 == 0x09 and fm1 == 0x089 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x20; dest:x27; op1val:0xa489; valaddr_reg:x19; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x27, x20, dyn, 0, 0, x19, 14*FLEN/8, x21, x4, x9,FLREG) + +inst_30:// rs1==x3, rd==x17,fs1 == 1 and fe1 == 0x0a and fm1 == 0x3c3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x3; dest:x17; op1val:0xabc3; valaddr_reg:x19; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x17, x3, dyn, 0, 0, x19, 15*FLEN/8, x21, x4, x9,FLREG) +RVTEST_VALBASEUPD(x1,test_dataset_2) + +inst_31:// rs1==x30, rd==x19,fs1 == 1 and fe1 == 0x0b and fm1 == 0x136 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x19; op1val:0xad36; valaddr_reg:x1; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x19, x30, dyn, 0, 0, x1, 0*FLEN/8, x2, x4, x9,FLREG) + +inst_32:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x176 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xb176; valaddr_reg:x1; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 0, 0, x1, 1*FLEN/8, x2, x4, x9,FLREG) + +inst_33:// fs1 == 1 and fe1 == 0x0d and fm1 == 0x397 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xb797; valaddr_reg:x1; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 0, 0, x1, 2*FLEN/8, x2, x4, x9,FLREG) + +inst_34:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x141 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xb941; valaddr_reg:x1; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 0, 0, x1, 3*FLEN/8, x2, x4, x9,FLREG) + +inst_35:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x232 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xbe32; valaddr_reg:x1; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 0, 0, x1, 4*FLEN/8, x2, x4, x9,FLREG) + +inst_36:// fs1 == 1 and fe1 == 0x10 and fm1 == 0x1be and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xc1be; valaddr_reg:x1; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 0, 0, x1, 5*FLEN/8, x2, x4, x9,FLREG) + +inst_37:// fs1 == 1 and fe1 == 0x11 and fm1 == 0x042 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xc442; valaddr_reg:x1; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 0, 0, x1, 6*FLEN/8, x2, x4, x9,FLREG) + +inst_38:// fs1 == 1 and fe1 == 0x09 and fm1 == 0x256 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xa656; valaddr_reg:x1; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 0, 0, x1, 7*FLEN/8, x2, x4, x9,FLREG) + +inst_39:// fs1 == 1 and fe1 == 0x16 and fm1 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xda01; valaddr_reg:x1; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 0, 0, x1, 8*FLEN/8, x2, x4, x9,FLREG) + +inst_40:// fs1 == 0 and fe1 == 0x13 and fm1 == 0x0a4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x4ca4; valaddr_reg:x1; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 0, 0, x1, 9*FLEN/8, x2, x4, x9,FLREG) + +inst_41:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2be and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x82be; valaddr_reg:x1; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 0, 0, x1, 10*FLEN/8, x2, x4, x9,FLREG) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(12873,32,FLEN) +NAN_BOXED(13751,32,FLEN) +NAN_BOXED(14927,32,FLEN) +NAN_BOXED(15571,32,FLEN) +NAN_BOXED(17216,32,FLEN) +NAN_BOXED(18251,32,FLEN) +NAN_BOXED(51869,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(21013,32,FLEN) +NAN_BOXED(21839,32,FLEN) +NAN_BOXED(55551,16,FLEN) +NAN_BOXED(57295,16,FLEN) +NAN_BOXED(25596,32,FLEN) +NAN_BOXED(25645,32,FLEN) +NAN_BOXED(27504,32,FLEN) +test_dataset_1: +NAN_BOXED(28265,32,FLEN) +NAN_BOXED(29062,32,FLEN) +NAN_BOXED(62754,16,FLEN) +NAN_BOXED(31411,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(33470,16,FLEN) +NAN_BOXED(34469,16,FLEN) +NAN_BOXED(34952,16,FLEN) +NAN_BOXED(36626,16,FLEN) +NAN_BOXED(37869,16,FLEN) +NAN_BOXED(38880,16,FLEN) +NAN_BOXED(39540,16,FLEN) +NAN_BOXED(39981,16,FLEN) +NAN_BOXED(40964,16,FLEN) +NAN_BOXED(42121,16,FLEN) +NAN_BOXED(43971,16,FLEN) +test_dataset_2: +NAN_BOXED(44342,16,FLEN) +NAN_BOXED(45430,16,FLEN) +NAN_BOXED(46999,16,FLEN) +NAN_BOXED(47425,16,FLEN) +NAN_BOXED(48690,16,FLEN) +NAN_BOXED(49598,16,FLEN) +NAN_BOXED(50242,16,FLEN) +NAN_BOXED(42582,16,FLEN) +NAN_BOXED(55809,16,FLEN) +NAN_BOXED(19620,16,FLEN) +NAN_BOXED(33470,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 40*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x4_0: + .fill 44*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fcvt.wu.h_b23-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fcvt.wu.h_b23-01.S new file mode 100644 index 000000000..356916857 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fcvt.wu.h_b23-01.S @@ -0,0 +1,426 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 06:01:25 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fcvt.wu.h.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.wu.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fcvt.wu.h_b23 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fcvt.wu.h_b23) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x19,test_dataset_0) +RVTEST_SIGBASE(x16,signature_x16_1) + +inst_0:// rs1==x10, rd==x31,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x10; dest:x31; op1val:0x77fc; valaddr_reg:x19; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x31, x10, dyn, 0, 0, x19, 0*FLEN/8, x21, x16, x7,FLREG) + +inst_1:// rs1==x23, rd==x20,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x23; dest:x20; op1val:0x77fc; valaddr_reg:x19; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.wu.h, x20, x23, dyn, 32, 0, x19, 1*FLEN/8, x21, x16, x7,FLREG) + +inst_2:// rs1==x26, rd==x24,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x26; dest:x24; op1val:0x77fc; valaddr_reg:x19; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.wu.h, x24, x26, dyn, 64, 0, x19, 2*FLEN/8, x21, x16, x7,FLREG) + +inst_3:// rs1==x28, rd==x9,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x28; dest:x9; op1val:0x77fc; valaddr_reg:x19; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.wu.h, x9, x28, dyn, 96, 0, x19, 3*FLEN/8, x21, x16, x7,FLREG) + +inst_4:// rs1==x29, rd==x5,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x29; dest:x5; op1val:0x77fc; valaddr_reg:x19; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.wu.h, x5, x29, dyn, 128, 0, x19, 4*FLEN/8, x21, x16, x7,FLREG) + +inst_5:// rs1==x12, rd==x13,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x12; dest:x13; op1val:0x77fd; valaddr_reg:x19; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x13, x12, dyn, 0, 0, x19, 5*FLEN/8, x21, x16, x7,FLREG) + +inst_6:// rs1==x20, rd==x27,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x20; dest:x27; op1val:0x77fd; valaddr_reg:x19; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.wu.h, x27, x20, dyn, 32, 0, x19, 6*FLEN/8, x21, x16, x7,FLREG) + +inst_7:// rs1==x5, rd==x4,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x5; dest:x4; op1val:0x77fd; valaddr_reg:x19; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.wu.h, x4, x5, dyn, 64, 0, x19, 7*FLEN/8, x21, x16, x7,FLREG) + +inst_8:// rs1==x6, rd==x22,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x6; dest:x22; op1val:0x77fd; valaddr_reg:x19; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.wu.h, x22, x6, dyn, 96, 0, x19, 8*FLEN/8, x21, x16, x7,FLREG) + +inst_9:// rs1==x31, rd==x3,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x31; dest:x3; op1val:0x77fd; valaddr_reg:x19; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.wu.h, x3, x31, dyn, 128, 0, x19, 9*FLEN/8, x21, x16, x7,FLREG) + +inst_10:// rs1==x4, rd==x2,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x4; dest:x2; op1val:0x77fe; valaddr_reg:x19; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x2, x4, dyn, 0, 0, x19, 10*FLEN/8, x21, x16, x7,FLREG) + +inst_11:// rs1==x3, rd==x11,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x3; dest:x11; op1val:0x77fe; valaddr_reg:x19; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.wu.h, x11, x3, dyn, 32, 0, x19, 11*FLEN/8, x21, x16, x7,FLREG) + +inst_12:// rs1==x1, rd==x10,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x1; dest:x10; op1val:0x77fe; valaddr_reg:x19; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.wu.h, x10, x1, dyn, 64, 0, x19, 12*FLEN/8, x21, x16, x7,FLREG) + +inst_13:// rs1==x22, rd==x15,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x22; dest:x15; op1val:0x77fe; valaddr_reg:x19; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.wu.h, x15, x22, dyn, 96, 0, x19, 13*FLEN/8, x21, x16, x7,FLREG) + +inst_14:// rs1==x13, rd==x8,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x13; dest:x8; op1val:0x77fe; valaddr_reg:x19; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.wu.h, x8, x13, dyn, 128, 0, x19, 14*FLEN/8, x21, x16, x7,FLREG) + +inst_15:// rs1==x18, rd==x26,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x18; dest:x26; op1val:0x77ff; valaddr_reg:x19; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x26, x18, dyn, 0, 0, x19, 15*FLEN/8, x21, x16, x7,FLREG) + +inst_16:// rs1==x15, rd==x28,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x15; dest:x28; op1val:0x77ff; valaddr_reg:x19; +val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.wu.h, x28, x15, dyn, 32, 0, x19, 16*FLEN/8, x21, x16, x7,FLREG) + +inst_17:// rs1==x14, rd==x17,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x14; dest:x17; op1val:0x77ff; valaddr_reg:x19; +val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.wu.h, x17, x14, dyn, 64, 0, x19, 17*FLEN/8, x21, x16, x7,FLREG) +RVTEST_VALBASEUPD(x5,test_dataset_1) + +inst_18:// rs1==x8, rd==x21,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x8; dest:x21; op1val:0x77ff; valaddr_reg:x5; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.wu.h, x21, x8, dyn, 96, 0, x5, 0*FLEN/8, x10, x16, x7,FLREG) + +inst_19:// rs1==x7, rd==x29,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x7; dest:x29; op1val:0x77ff; valaddr_reg:x5; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.wu.h, x29, x7, dyn, 128, 0, x5, 1*FLEN/8, x10, x16, x4,FLREG) +RVTEST_SIGBASE(x3,signature_x3_0) + +inst_20:// rs1==x2, rd==x30,fs1 == 0 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x2; dest:x30; op1val:0x7800; valaddr_reg:x5; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x30, x2, dyn, 0, 0, x5, 2*FLEN/8, x10, x3, x4,FLREG) + +inst_21:// rs1==x27, rd==x6,fs1 == 0 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x27; dest:x6; op1val:0x7800; valaddr_reg:x5; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.wu.h, x6, x27, dyn, 32, 0, x5, 3*FLEN/8, x10, x3, x4,FLREG) + +inst_22:// rs1==x24, rd==x25,fs1 == 0 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x24; dest:x25; op1val:0x7800; valaddr_reg:x5; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.wu.h, x25, x24, dyn, 64, 0, x5, 4*FLEN/8, x10, x3, x4,FLREG) + +inst_23:// rs1==x16, rd==x14,fs1 == 0 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x16; dest:x14; op1val:0x7800; valaddr_reg:x5; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.wu.h, x14, x16, dyn, 96, 0, x5, 5*FLEN/8, x10, x3, x4,FLREG) + +inst_24:// rs1==x11, rd==x12,fs1 == 0 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x11; dest:x12; op1val:0x7800; valaddr_reg:x5; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.wu.h, x12, x11, dyn, 128, 0, x5, 6*FLEN/8, x10, x3, x4,FLREG) + +inst_25:// rs1==x0, rd==x7,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x0; dest:x7; op1val:0x0; valaddr_reg:x5; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x7, x0, dyn, 0, 0, x5, 7*FLEN/8, x10, x3, x4,FLREG) + +inst_26:// rs1==x9, rd==x16,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x9; dest:x16; op1val:0x7801; valaddr_reg:x5; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.wu.h, x16, x9, dyn, 32, 0, x5, 8*FLEN/8, x10, x3, x4,FLREG) + +inst_27:// rs1==x30, rd==x23,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x23; op1val:0x7801; valaddr_reg:x5; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.wu.h, x23, x30, dyn, 64, 0, x5, 9*FLEN/8, x10, x3, x4,FLREG) + +inst_28:// rs1==x17, rd==x1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x17; dest:x1; op1val:0x7801; valaddr_reg:x5; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.wu.h, x1, x17, dyn, 96, 0, x5, 10*FLEN/8, x10, x3, x4,FLREG) + +inst_29:// rs1==x21, rd==x0,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x21; dest:x0; op1val:0x7801; valaddr_reg:x5; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.wu.h, x0, x21, dyn, 128, 0, x5, 11*FLEN/8, x10, x3, x4,FLREG) + +inst_30:// rs1==x25, rd==x18,fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x25; dest:x18; op1val:0x7802; valaddr_reg:x5; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x18, x25, dyn, 0, 0, x5, 12*FLEN/8, x10, x3, x4,FLREG) + +inst_31:// rs1==x19,fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x19; dest:x28; op1val:0x7802; valaddr_reg:x5; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.wu.h, x28, x19, dyn, 32, 0, x5, 13*FLEN/8, x10, x3, x4,FLREG) + +inst_32:// rd==x19,fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x22; dest:x19; op1val:0x7802; valaddr_reg:x5; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.wu.h, x19, x22, dyn, 64, 0, x5, 14*FLEN/8, x10, x3, x4,FLREG) + +inst_33:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x7802; valaddr_reg:x5; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 96, 0, x5, 15*FLEN/8, x10, x3, x4,FLREG) + +inst_34:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x7802; valaddr_reg:x5; +val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 128, 0, x5, 16*FLEN/8, x10, x3, x4,FLREG) + +inst_35:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x7803; valaddr_reg:x5; +val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 0, 0, x5, 17*FLEN/8, x10, x3, x4,FLREG) + +inst_36:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x003 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x7803; valaddr_reg:x5; +val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 32, 0, x5, 18*FLEN/8, x10, x3, x4,FLREG) + +inst_37:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x003 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x7803; valaddr_reg:x5; +val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 64, 0, x5, 19*FLEN/8, x10, x3, x4,FLREG) + +inst_38:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x003 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x7803; valaddr_reg:x5; +val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 96, 0, x5, 20*FLEN/8, x10, x3, x4,FLREG) + +inst_39:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x003 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x7803; valaddr_reg:x5; +val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 128, 0, x5, 21*FLEN/8, x10, x3, x4,FLREG) + +inst_40:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x7804; valaddr_reg:x5; +val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 0, 0, x5, 22*FLEN/8, x10, x3, x4,FLREG) + +inst_41:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x7804; valaddr_reg:x5; +val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 32, 0, x5, 23*FLEN/8, x10, x3, x4,FLREG) + +inst_42:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x7804; valaddr_reg:x5; +val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 64, 0, x5, 24*FLEN/8, x10, x3, x4,FLREG) + +inst_43:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x7804; valaddr_reg:x5; +val_offset:25*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 96, 0, x5, 25*FLEN/8, x10, x3, x4,FLREG) + +inst_44:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x7804; valaddr_reg:x5; +val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 128, 0, x5, 26*FLEN/8, x10, x3, x4,FLREG) + +inst_45:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x7801; valaddr_reg:x5; +val_offset:27*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 0, 0, x5, 27*FLEN/8, x10, x3, x4,FLREG) + +inst_46:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x7801; valaddr_reg:x5; +val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 128, 0, x5, 28*FLEN/8, x10, x3, x4,FLREG) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(30716,32,FLEN) +NAN_BOXED(30716,32,FLEN) +NAN_BOXED(30716,32,FLEN) +NAN_BOXED(30716,32,FLEN) +NAN_BOXED(30716,32,FLEN) +NAN_BOXED(30717,32,FLEN) +NAN_BOXED(30717,32,FLEN) +NAN_BOXED(30717,32,FLEN) +NAN_BOXED(30717,32,FLEN) +NAN_BOXED(30717,32,FLEN) +NAN_BOXED(30718,32,FLEN) +NAN_BOXED(30718,32,FLEN) +NAN_BOXED(30718,32,FLEN) +NAN_BOXED(30718,32,FLEN) +NAN_BOXED(30718,32,FLEN) +NAN_BOXED(30719,32,FLEN) +NAN_BOXED(30719,32,FLEN) +NAN_BOXED(30719,32,FLEN) +test_dataset_1: +NAN_BOXED(30719,16,FLEN) +NAN_BOXED(30719,16,FLEN) +NAN_BOXED(30720,16,FLEN) +NAN_BOXED(30720,16,FLEN) +NAN_BOXED(30720,16,FLEN) +NAN_BOXED(30720,16,FLEN) +NAN_BOXED(30720,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(30721,16,FLEN) +NAN_BOXED(30721,16,FLEN) +NAN_BOXED(30721,16,FLEN) +NAN_BOXED(30721,16,FLEN) +NAN_BOXED(30722,16,FLEN) +NAN_BOXED(30722,16,FLEN) +NAN_BOXED(30722,16,FLEN) +NAN_BOXED(30722,16,FLEN) +NAN_BOXED(30722,16,FLEN) +NAN_BOXED(30723,16,FLEN) +NAN_BOXED(30723,16,FLEN) +NAN_BOXED(30723,16,FLEN) +NAN_BOXED(30723,16,FLEN) +NAN_BOXED(30723,16,FLEN) +NAN_BOXED(30724,16,FLEN) +NAN_BOXED(30724,16,FLEN) +NAN_BOXED(30724,16,FLEN) +NAN_BOXED(30724,16,FLEN) +NAN_BOXED(30724,16,FLEN) +NAN_BOXED(30721,16,FLEN) +NAN_BOXED(30721,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x16_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x16_1: + .fill 40*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x3_0: + .fill 54*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fcvt.wu.h_b24-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fcvt.wu.h_b24-01.S new file mode 100644 index 000000000..0b0cffdeb --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fcvt.wu.h_b24-01.S @@ -0,0 +1,846 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 06:01:25 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fcvt.wu.h.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.wu.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fcvt.wu.h_b24 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fcvt.wu.h_b24) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x10,test_dataset_0) +RVTEST_SIGBASE(x6,signature_x6_1) + +inst_0:// rs1==x30, rd==x2,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x2; op1val:0xf0; valaddr_reg:x10; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x8; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x2, x30, dyn, 0, 0, x10, 0*FLEN/8, x15, x6, x8,FLREG) + +inst_1:// rs1==x3, rd==x20,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x3; dest:x20; op1val:0xf0; valaddr_reg:x10; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x8; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.wu.h, x20, x3, dyn, 32, 0, x10, 1*FLEN/8, x15, x6, x8,FLREG) + +inst_2:// rs1==x21, rd==x13,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x21; dest:x13; op1val:0xf0; valaddr_reg:x10; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x8; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.wu.h, x13, x21, dyn, 64, 0, x10, 2*FLEN/8, x15, x6, x8,FLREG) + +inst_3:// rs1==x13, rd==x26,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x13; dest:x26; op1val:0xf0; valaddr_reg:x10; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x8; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.wu.h, x26, x13, dyn, 96, 0, x10, 3*FLEN/8, x15, x6, x8,FLREG) + +inst_4:// rs1==x26, rd==x31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x26; dest:x31; op1val:0xf0; valaddr_reg:x10; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x8; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.wu.h, x31, x26, dyn, 128, 0, x10, 4*FLEN/8, x15, x6, x8,FLREG) + +inst_5:// rs1==x22, rd==x3,fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x22; dest:x3; op1val:0xaf0a; valaddr_reg:x10; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x8; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x3, x22, dyn, 0, 0, x10, 5*FLEN/8, x15, x6, x8,FLREG) + +inst_6:// rs1==x24, rd==x4,fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x24; dest:x4; op1val:0xaf0a; valaddr_reg:x10; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x8; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.wu.h, x4, x24, dyn, 32, 0, x10, 6*FLEN/8, x15, x6, x8,FLREG) + +inst_7:// rs1==x28, rd==x22,fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x28; dest:x22; op1val:0xaf0a; valaddr_reg:x10; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x8; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.wu.h, x22, x28, dyn, 64, 0, x10, 7*FLEN/8, x15, x6, x8,FLREG) + +inst_8:// rs1==x27, rd==x24,fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x27; dest:x24; op1val:0xaf0a; valaddr_reg:x10; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x8; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.wu.h, x24, x27, dyn, 96, 0, x10, 8*FLEN/8, x15, x6, x8,FLREG) + +inst_9:// rs1==x29, rd==x27,fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x29; dest:x27; op1val:0xaf0a; valaddr_reg:x10; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x8; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.wu.h, x27, x29, dyn, 128, 0, x10, 9*FLEN/8, x15, x6, x8,FLREG) + +inst_10:// rs1==x12, rd==x14,fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x12; dest:x14; op1val:0xbc66; valaddr_reg:x10; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x8; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x14, x12, dyn, 0, 0, x10, 10*FLEN/8, x15, x6, x8,FLREG) + +inst_11:// rs1==x9, rd==x11,fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x9; dest:x11; op1val:0xbc66; valaddr_reg:x10; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x8; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.wu.h, x11, x9, dyn, 32, 0, x10, 11*FLEN/8, x15, x6, x8,FLREG) + +inst_12:// rs1==x31, rd==x28,fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x31; dest:x28; op1val:0xbc66; valaddr_reg:x10; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x8; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.wu.h, x28, x31, dyn, 64, 0, x10, 12*FLEN/8, x15, x6, x8,FLREG) + +inst_13:// rs1==x5, rd==x7,fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x5; dest:x7; op1val:0xbc66; valaddr_reg:x10; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x8; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.wu.h, x7, x5, dyn, 96, 0, x10, 13*FLEN/8, x15, x6, x8,FLREG) + +inst_14:// rs1==x11, rd==x19,fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x11; dest:x19; op1val:0xbc66; valaddr_reg:x10; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x8; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.wu.h, x19, x11, dyn, 128, 0, x10, 14*FLEN/8, x15, x6, x8,FLREG) + +inst_15:// rs1==x14, rd==x1,fs1 == 0 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x14; dest:x1; op1val:0x3b1e; valaddr_reg:x10; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x8; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x1, x14, dyn, 0, 0, x10, 15*FLEN/8, x15, x6, x8,FLREG) + +inst_16:// rs1==x25, rd==x23,fs1 == 0 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x25; dest:x23; op1val:0x3b1e; valaddr_reg:x10; +val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x8; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.wu.h, x23, x25, dyn, 32, 0, x10, 16*FLEN/8, x15, x6, x8,FLREG) +RVTEST_VALBASEUPD(x11,test_dataset_1) + +inst_17:// rs1==x15, rd==x12,fs1 == 0 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x15; dest:x12; op1val:0x3b1e; valaddr_reg:x11; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x8; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.wu.h, x12, x15, dyn, 64, 0, x11, 0*FLEN/8, x13, x6, x8,FLREG) + +inst_18:// rs1==x20, rd==x18,fs1 == 0 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x20; dest:x18; op1val:0x3b1e; valaddr_reg:x11; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x8; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.wu.h, x18, x20, dyn, 96, 0, x11, 1*FLEN/8, x13, x6, x8,FLREG) + +inst_19:// rs1==x2, rd==x30,fs1 == 0 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x2; dest:x30; op1val:0x3b1e; valaddr_reg:x11; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.wu.h, x30, x2, dyn, 128, 0, x11, 2*FLEN/8, x13, x6, x3,FLREG) + +inst_20:// rs1==x8, rd==x29,fs1 == 0 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x8; dest:x29; op1val:0x3b33; valaddr_reg:x11; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x29, x8, dyn, 0, 0, x11, 3*FLEN/8, x13, x6, x3,FLREG) +RVTEST_SIGBASE(x2,signature_x2_0) + +inst_21:// rs1==x4, rd==x10,fs1 == 0 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x4; dest:x10; op1val:0x3b33; valaddr_reg:x11; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.wu.h, x10, x4, dyn, 32, 0, x11, 4*FLEN/8, x13, x2, x3,FLREG) + +inst_22:// rs1==x23, rd==x25,fs1 == 0 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x23; dest:x25; op1val:0x3b33; valaddr_reg:x11; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.wu.h, x25, x23, dyn, 64, 0, x11, 5*FLEN/8, x13, x2, x3,FLREG) + +inst_23:// rs1==x16, rd==x8,fs1 == 0 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x16; dest:x8; op1val:0x3b33; valaddr_reg:x11; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.wu.h, x8, x16, dyn, 96, 0, x11, 6*FLEN/8, x13, x2, x3,FLREG) + +inst_24:// rs1==x6, rd==x5,fs1 == 0 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x6; dest:x5; op1val:0x3b33; valaddr_reg:x11; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.wu.h, x5, x6, dyn, 128, 0, x11, 7*FLEN/8, x13, x2, x3,FLREG) + +inst_25:// rs1==x7, rd==x6,fs1 == 1 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x7; dest:x6; op1val:0xa11e; valaddr_reg:x11; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x6, x7, dyn, 0, 0, x11, 8*FLEN/8, x13, x2, x3,FLREG) + +inst_26:// rs1==x10, rd==x21,fs1 == 1 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x10; dest:x21; op1val:0xa11e; valaddr_reg:x11; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.wu.h, x21, x10, dyn, 32, 0, x11, 9*FLEN/8, x13, x2, x3,FLREG) + +inst_27:// rs1==x1, rd==x16,fs1 == 1 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x1; dest:x16; op1val:0xa11e; valaddr_reg:x11; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.wu.h, x16, x1, dyn, 64, 0, x11, 10*FLEN/8, x13, x2, x3,FLREG) + +inst_28:// rs1==x0, rd==x9,fs1 == 1 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x0; dest:x9; op1val:0x0; valaddr_reg:x11; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.wu.h, x9, x0, dyn, 96, 0, x11, 11*FLEN/8, x13, x2, x3,FLREG) + +inst_29:// rs1==x17, rd==x15,fs1 == 1 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x17; dest:x15; op1val:0xa11e; valaddr_reg:x11; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.wu.h, x15, x17, dyn, 128, 0, x11, 12*FLEN/8, x13, x2, x3,FLREG) + +inst_30:// rs1==x18, rd==x17,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x18; dest:x17; op1val:0x3c00; valaddr_reg:x11; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x17, x18, dyn, 0, 0, x11, 13*FLEN/8, x13, x2, x3,FLREG) + +inst_31:// rs1==x19, rd==x0,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x19; dest:x0; op1val:0x3c00; valaddr_reg:x11; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.wu.h, x0, x19, dyn, 32, 0, x11, 14*FLEN/8, x13, x2, x3,FLREG) + +inst_32:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x3c00; valaddr_reg:x11; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 64, 0, x11, 15*FLEN/8, x13, x2, x3,FLREG) + +inst_33:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x3c00; valaddr_reg:x11; +val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 96, 0, x11, 16*FLEN/8, x13, x2, x3,FLREG) + +inst_34:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x3c00; valaddr_reg:x11; +val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 128, 0, x11, 17*FLEN/8, x13, x2, x3,FLREG) + +inst_35:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xbc0a; valaddr_reg:x11; +val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 0, 0, x11, 18*FLEN/8, x13, x2, x3,FLREG) + +inst_36:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xbc0a; valaddr_reg:x11; +val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 32, 0, x11, 19*FLEN/8, x13, x2, x3,FLREG) + +inst_37:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xbc0a; valaddr_reg:x11; +val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 64, 0, x11, 20*FLEN/8, x13, x2, x3,FLREG) + +inst_38:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xbc0a; valaddr_reg:x11; +val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 96, 0, x11, 21*FLEN/8, x13, x2, x3,FLREG) + +inst_39:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xbc0a; valaddr_reg:x11; +val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 128, 0, x11, 22*FLEN/8, x13, x2, x3,FLREG) + +inst_40:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xbbeb; valaddr_reg:x11; +val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 0, 0, x11, 23*FLEN/8, x13, x2, x3,FLREG) + +inst_41:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xbbeb; valaddr_reg:x11; +val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 32, 0, x11, 24*FLEN/8, x13, x2, x3,FLREG) + +inst_42:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xbbeb; valaddr_reg:x11; +val_offset:25*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 64, 0, x11, 25*FLEN/8, x13, x2, x3,FLREG) + +inst_43:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xbbeb; valaddr_reg:x11; +val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 96, 0, x11, 26*FLEN/8, x13, x2, x3,FLREG) + +inst_44:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xbbeb; valaddr_reg:x11; +val_offset:27*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 128, 0, x11, 27*FLEN/8, x13, x2, x3,FLREG) + +inst_45:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x3beb; valaddr_reg:x11; +val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 0, 0, x11, 28*FLEN/8, x13, x2, x3,FLREG) + +inst_46:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x3beb; valaddr_reg:x11; +val_offset:29*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 32, 0, x11, 29*FLEN/8, x13, x2, x3,FLREG) + +inst_47:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x3beb; valaddr_reg:x11; +val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 64, 0, x11, 30*FLEN/8, x13, x2, x3,FLREG) + +inst_48:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x3beb; valaddr_reg:x11; +val_offset:31*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 96, 0, x11, 31*FLEN/8, x13, x2, x3,FLREG) + +inst_49:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x3beb; valaddr_reg:x11; +val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 128, 0, x11, 32*FLEN/8, x13, x2, x3,FLREG) + +inst_50:// fs1 == 0 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x2f0a; valaddr_reg:x11; +val_offset:33*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 0, 0, x11, 33*FLEN/8, x13, x2, x3,FLREG) + +inst_51:// fs1 == 0 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x2f0a; valaddr_reg:x11; +val_offset:34*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 32, 0, x11, 34*FLEN/8, x13, x2, x3,FLREG) + +inst_52:// fs1 == 0 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x2f0a; valaddr_reg:x11; +val_offset:35*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 64, 0, x11, 35*FLEN/8, x13, x2, x3,FLREG) + +inst_53:// fs1 == 0 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x2f0a; valaddr_reg:x11; +val_offset:36*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 96, 0, x11, 36*FLEN/8, x13, x2, x3,FLREG) + +inst_54:// fs1 == 0 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x2f0a; valaddr_reg:x11; +val_offset:37*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 128, 0, x11, 37*FLEN/8, x13, x2, x3,FLREG) + +inst_55:// fs1 == 0 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x211e; valaddr_reg:x11; +val_offset:38*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 0, 0, x11, 38*FLEN/8, x13, x2, x3,FLREG) + +inst_56:// fs1 == 0 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x211e; valaddr_reg:x11; +val_offset:39*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 32, 0, x11, 39*FLEN/8, x13, x2, x3,FLREG) + +inst_57:// fs1 == 0 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x211e; valaddr_reg:x11; +val_offset:40*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 64, 0, x11, 40*FLEN/8, x13, x2, x3,FLREG) + +inst_58:// fs1 == 0 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x211e; valaddr_reg:x11; +val_offset:41*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 96, 0, x11, 41*FLEN/8, x13, x2, x3,FLREG) + +inst_59:// fs1 == 0 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x211e; valaddr_reg:x11; +val_offset:42*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 128, 0, x11, 42*FLEN/8, x13, x2, x3,FLREG) + +inst_60:// fs1 == 1 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xae66; valaddr_reg:x11; +val_offset:43*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 0, 0, x11, 43*FLEN/8, x13, x2, x3,FLREG) + +inst_61:// fs1 == 1 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xae66; valaddr_reg:x11; +val_offset:44*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 32, 0, x11, 44*FLEN/8, x13, x2, x3,FLREG) + +inst_62:// fs1 == 1 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xae66; valaddr_reg:x11; +val_offset:45*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 64, 0, x11, 45*FLEN/8, x13, x2, x3,FLREG) + +inst_63:// fs1 == 1 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xae66; valaddr_reg:x11; +val_offset:46*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 96, 0, x11, 46*FLEN/8, x13, x2, x3,FLREG) + +inst_64:// fs1 == 1 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xae66; valaddr_reg:x11; +val_offset:47*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 128, 0, x11, 47*FLEN/8, x13, x2, x3,FLREG) + +inst_65:// fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x2e66; valaddr_reg:x11; +val_offset:48*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 0, 0, x11, 48*FLEN/8, x13, x2, x3,FLREG) + +inst_66:// fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x2e66; valaddr_reg:x11; +val_offset:49*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 32, 0, x11, 49*FLEN/8, x13, x2, x3,FLREG) + +inst_67:// fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x2e66; valaddr_reg:x11; +val_offset:50*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 64, 0, x11, 50*FLEN/8, x13, x2, x3,FLREG) + +inst_68:// fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x2e66; valaddr_reg:x11; +val_offset:51*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 96, 0, x11, 51*FLEN/8, x13, x2, x3,FLREG) + +inst_69:// fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x2e66; valaddr_reg:x11; +val_offset:52*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 128, 0, x11, 52*FLEN/8, x13, x2, x3,FLREG) + +inst_70:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xbc00; valaddr_reg:x11; +val_offset:53*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 0, 0, x11, 53*FLEN/8, x13, x2, x3,FLREG) + +inst_71:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xbc00; valaddr_reg:x11; +val_offset:54*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 32, 0, x11, 54*FLEN/8, x13, x2, x3,FLREG) + +inst_72:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xbc00; valaddr_reg:x11; +val_offset:55*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 64, 0, x11, 55*FLEN/8, x13, x2, x3,FLREG) + +inst_73:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xbc00; valaddr_reg:x11; +val_offset:56*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 96, 0, x11, 56*FLEN/8, x13, x2, x3,FLREG) + +inst_74:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xbc00; valaddr_reg:x11; +val_offset:57*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 128, 0, x11, 57*FLEN/8, x13, x2, x3,FLREG) + +inst_75:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xbc70; valaddr_reg:x11; +val_offset:58*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 0, 0, x11, 58*FLEN/8, x13, x2, x3,FLREG) + +inst_76:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xbc70; valaddr_reg:x11; +val_offset:59*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 32, 0, x11, 59*FLEN/8, x13, x2, x3,FLREG) + +inst_77:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xbc70; valaddr_reg:x11; +val_offset:60*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 64, 0, x11, 60*FLEN/8, x13, x2, x3,FLREG) + +inst_78:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xbc70; valaddr_reg:x11; +val_offset:61*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 96, 0, x11, 61*FLEN/8, x13, x2, x3,FLREG) + +inst_79:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xbc70; valaddr_reg:x11; +val_offset:62*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 128, 0, x11, 62*FLEN/8, x13, x2, x3,FLREG) + +inst_80:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x3c70; valaddr_reg:x11; +val_offset:63*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 0, 0, x11, 63*FLEN/8, x13, x2, x3,FLREG) + +inst_81:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x3c70; valaddr_reg:x11; +val_offset:64*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 32, 0, x11, 64*FLEN/8, x13, x2, x3,FLREG) + +inst_82:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x3c70; valaddr_reg:x11; +val_offset:65*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 64, 0, x11, 65*FLEN/8, x13, x2, x3,FLREG) + +inst_83:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x3c70; valaddr_reg:x11; +val_offset:66*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 96, 0, x11, 66*FLEN/8, x13, x2, x3,FLREG) + +inst_84:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x3c70; valaddr_reg:x11; +val_offset:67*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 128, 0, x11, 67*FLEN/8, x13, x2, x3,FLREG) + +inst_85:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xbb33; valaddr_reg:x11; +val_offset:68*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 0, 0, x11, 68*FLEN/8, x13, x2, x3,FLREG) + +inst_86:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xbb33; valaddr_reg:x11; +val_offset:69*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 32, 0, x11, 69*FLEN/8, x13, x2, x3,FLREG) + +inst_87:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xbb33; valaddr_reg:x11; +val_offset:70*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 64, 0, x11, 70*FLEN/8, x13, x2, x3,FLREG) + +inst_88:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xbb33; valaddr_reg:x11; +val_offset:71*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 96, 0, x11, 71*FLEN/8, x13, x2, x3,FLREG) + +inst_89:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xbb33; valaddr_reg:x11; +val_offset:72*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 128, 0, x11, 72*FLEN/8, x13, x2, x3,FLREG) + +inst_90:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x3c0a; valaddr_reg:x11; +val_offset:73*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 0, 0, x11, 73*FLEN/8, x13, x2, x3,FLREG) + +inst_91:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x3c0a; valaddr_reg:x11; +val_offset:74*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 32, 0, x11, 74*FLEN/8, x13, x2, x3,FLREG) + +inst_92:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x3c0a; valaddr_reg:x11; +val_offset:75*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 64, 0, x11, 75*FLEN/8, x13, x2, x3,FLREG) + +inst_93:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x3c0a; valaddr_reg:x11; +val_offset:76*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 96, 0, x11, 76*FLEN/8, x13, x2, x3,FLREG) + +inst_94:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x3c0a; valaddr_reg:x11; +val_offset:77*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 128, 0, x11, 77*FLEN/8, x13, x2, x3,FLREG) + +inst_95:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x3c66; valaddr_reg:x11; +val_offset:78*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 0, 0, x11, 78*FLEN/8, x13, x2, x3,FLREG) + +inst_96:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x3c66; valaddr_reg:x11; +val_offset:79*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 32, 0, x11, 79*FLEN/8, x13, x2, x3,FLREG) + +inst_97:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x3c66; valaddr_reg:x11; +val_offset:80*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 64, 0, x11, 80*FLEN/8, x13, x2, x3,FLREG) + +inst_98:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x3c66; valaddr_reg:x11; +val_offset:81*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 96, 0, x11, 81*FLEN/8, x13, x2, x3,FLREG) + +inst_99:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x3c66; valaddr_reg:x11; +val_offset:82*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 128, 0, x11, 82*FLEN/8, x13, x2, x3,FLREG) + +inst_100:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xbb1e; valaddr_reg:x11; +val_offset:83*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 0, 0, x11, 83*FLEN/8, x13, x2, x3,FLREG) + +inst_101:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xbb1e; valaddr_reg:x11; +val_offset:84*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 32, 0, x11, 84*FLEN/8, x13, x2, x3,FLREG) + +inst_102:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xbb1e; valaddr_reg:x11; +val_offset:85*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 64, 0, x11, 85*FLEN/8, x13, x2, x3,FLREG) + +inst_103:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xbb1e; valaddr_reg:x11; +val_offset:86*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 96, 0, x11, 86*FLEN/8, x13, x2, x3,FLREG) + +inst_104:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xbb1e; valaddr_reg:x11; +val_offset:87*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 128, 0, x11, 87*FLEN/8, x13, x2, x3,FLREG) + +inst_105:// fs1 == 1 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xa11e; valaddr_reg:x11; +val_offset:88*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 96, 0, x11, 88*FLEN/8, x13, x2, x3,FLREG) + +inst_106:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x3c00; valaddr_reg:x11; +val_offset:89*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 32, 0, x11, 89*FLEN/8, x13, x2, x3,FLREG) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(240,32,FLEN) +NAN_BOXED(240,32,FLEN) +NAN_BOXED(240,32,FLEN) +NAN_BOXED(240,32,FLEN) +NAN_BOXED(240,32,FLEN) +NAN_BOXED(44810,16,FLEN) +NAN_BOXED(44810,16,FLEN) +NAN_BOXED(44810,16,FLEN) +NAN_BOXED(44810,16,FLEN) +NAN_BOXED(44810,16,FLEN) +NAN_BOXED(48230,16,FLEN) +NAN_BOXED(48230,16,FLEN) +NAN_BOXED(48230,16,FLEN) +NAN_BOXED(48230,16,FLEN) +NAN_BOXED(48230,16,FLEN) +NAN_BOXED(15134,32,FLEN) +NAN_BOXED(15134,32,FLEN) +test_dataset_1: +NAN_BOXED(15134,16,FLEN) +NAN_BOXED(15134,16,FLEN) +NAN_BOXED(15134,16,FLEN) +NAN_BOXED(15155,16,FLEN) +NAN_BOXED(15155,16,FLEN) +NAN_BOXED(15155,16,FLEN) +NAN_BOXED(15155,16,FLEN) +NAN_BOXED(15155,16,FLEN) +NAN_BOXED(41246,16,FLEN) +NAN_BOXED(41246,16,FLEN) +NAN_BOXED(41246,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(41246,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(48138,16,FLEN) +NAN_BOXED(48138,16,FLEN) +NAN_BOXED(48138,16,FLEN) +NAN_BOXED(48138,16,FLEN) +NAN_BOXED(48138,16,FLEN) +NAN_BOXED(48107,16,FLEN) +NAN_BOXED(48107,16,FLEN) +NAN_BOXED(48107,16,FLEN) +NAN_BOXED(48107,16,FLEN) +NAN_BOXED(48107,16,FLEN) +NAN_BOXED(15339,16,FLEN) +NAN_BOXED(15339,16,FLEN) +NAN_BOXED(15339,16,FLEN) +NAN_BOXED(15339,16,FLEN) +NAN_BOXED(15339,16,FLEN) +NAN_BOXED(12042,16,FLEN) +NAN_BOXED(12042,16,FLEN) +NAN_BOXED(12042,16,FLEN) +NAN_BOXED(12042,16,FLEN) +NAN_BOXED(12042,16,FLEN) +NAN_BOXED(8478,16,FLEN) +NAN_BOXED(8478,16,FLEN) +NAN_BOXED(8478,16,FLEN) +NAN_BOXED(8478,16,FLEN) +NAN_BOXED(8478,16,FLEN) +NAN_BOXED(44646,16,FLEN) +NAN_BOXED(44646,16,FLEN) +NAN_BOXED(44646,16,FLEN) +NAN_BOXED(44646,16,FLEN) +NAN_BOXED(44646,16,FLEN) +NAN_BOXED(11878,16,FLEN) +NAN_BOXED(11878,16,FLEN) +NAN_BOXED(11878,16,FLEN) +NAN_BOXED(11878,16,FLEN) +NAN_BOXED(11878,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48240,16,FLEN) +NAN_BOXED(48240,16,FLEN) +NAN_BOXED(48240,16,FLEN) +NAN_BOXED(48240,16,FLEN) +NAN_BOXED(48240,16,FLEN) +NAN_BOXED(15472,16,FLEN) +NAN_BOXED(15472,16,FLEN) +NAN_BOXED(15472,16,FLEN) +NAN_BOXED(15472,16,FLEN) +NAN_BOXED(15472,16,FLEN) +NAN_BOXED(47923,16,FLEN) +NAN_BOXED(47923,16,FLEN) +NAN_BOXED(47923,16,FLEN) +NAN_BOXED(47923,16,FLEN) +NAN_BOXED(47923,16,FLEN) +NAN_BOXED(15370,16,FLEN) +NAN_BOXED(15370,16,FLEN) +NAN_BOXED(15370,16,FLEN) +NAN_BOXED(15370,16,FLEN) +NAN_BOXED(15370,16,FLEN) +NAN_BOXED(15462,16,FLEN) +NAN_BOXED(15462,16,FLEN) +NAN_BOXED(15462,16,FLEN) +NAN_BOXED(15462,16,FLEN) +NAN_BOXED(15462,16,FLEN) +NAN_BOXED(47902,16,FLEN) +NAN_BOXED(47902,16,FLEN) +NAN_BOXED(47902,16,FLEN) +NAN_BOXED(47902,16,FLEN) +NAN_BOXED(47902,16,FLEN) +NAN_BOXED(41246,16,FLEN) +NAN_BOXED(15360,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x6_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x6_1: + .fill 42*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_0: + .fill 172*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fcvt.wu.h_b27-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fcvt.wu.h_b27-01.S new file mode 100644 index 000000000..ee1555040 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fcvt.wu.h_b27-01.S @@ -0,0 +1,328 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 06:01:25 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fcvt.wu.h.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.wu.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fcvt.wu.h_b27 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fcvt.wu.h_b27) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x1,test_dataset_0) +RVTEST_SIGBASE(x11,signature_x11_1) + +inst_0:// rs1==x16, rd==x12,fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x16; dest:x12; op1val:0x7c01; valaddr_reg:x1; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x12, x16, dyn, 0, 0, x1, 0*FLEN/8, x25, x11, x3,FLREG) + +inst_1:// rs1==x7, rd==x22,fs1 == 1 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x7; dest:x22; op1val:0xfc01; valaddr_reg:x1; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x22, x7, dyn, 0, 0, x1, 1*FLEN/8, x25, x11, x3,FLREG) + +inst_2:// rs1==x19, rd==x10,fs1 == 0 and fe1 == 0x1f and fm1 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x19; dest:x10; op1val:0x7d55; valaddr_reg:x1; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x10, x19, dyn, 0, 0, x1, 2*FLEN/8, x25, x11, x3,FLREG) + +inst_3:// rs1==x31, rd==x0,fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x31; dest:x0; op1val:0xfd55; valaddr_reg:x1; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x0, x31, dyn, 0, 0, x1, 3*FLEN/8, x25, x11, x3,FLREG) + +inst_4:// rs1==x5, rd==x6,fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x5; dest:x6; op1val:0x7e01; valaddr_reg:x1; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x6, x5, dyn, 0, 0, x1, 4*FLEN/8, x25, x11, x3,FLREG) + +inst_5:// rs1==x8, rd==x26,fs1 == 1 and fe1 == 0x1f and fm1 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x8; dest:x26; op1val:0xfe01; valaddr_reg:x1; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x26, x8, dyn, 0, 0, x1, 5*FLEN/8, x25, x11, x3,FLREG) + +inst_6:// rs1==x26, rd==x2,fs1 == 0 and fe1 == 0x1f and fm1 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x26; dest:x2; op1val:0x7e55; valaddr_reg:x1; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x2, x26, dyn, 0, 0, x1, 6*FLEN/8, x25, x11, x3,FLREG) + +inst_7:// rs1==x4, rd==x17,fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x4; dest:x17; op1val:0xfe55; valaddr_reg:x1; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x17, x4, dyn, 0, 0, x1, 7*FLEN/8, x25, x11, x3,FLREG) + +inst_8:// rs1==x27, rd==x21, +/* opcode: fcvt.wu.h ; op1:x27; dest:x21; op1val:0x0; valaddr_reg:x1; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x21, x27, dyn, 0, 0, x1, 8*FLEN/8, x25, x11, x3,FLREG) + +inst_9:// rs1==x17, rd==x9, +/* opcode: fcvt.wu.h ; op1:x17; dest:x9; op1val:0x0; valaddr_reg:x1; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x9, x17, dyn, 0, 0, x1, 9*FLEN/8, x25, x11, x3,FLREG) + +inst_10:// rs1==x18, rd==x20, +/* opcode: fcvt.wu.h ; op1:x18; dest:x20; op1val:0x0; valaddr_reg:x1; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x20, x18, dyn, 0, 0, x1, 10*FLEN/8, x25, x11, x3,FLREG) + +inst_11:// rs1==x21, rd==x7, +/* opcode: fcvt.wu.h ; op1:x21; dest:x7; op1val:0x0; valaddr_reg:x1; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x7, x21, dyn, 0, 0, x1, 11*FLEN/8, x25, x11, x3,FLREG) + +inst_12:// rs1==x13, rd==x27, +/* opcode: fcvt.wu.h ; op1:x13; dest:x27; op1val:0x0; valaddr_reg:x1; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x27, x13, dyn, 0, 0, x1, 12*FLEN/8, x25, x11, x3,FLREG) + +inst_13:// rs1==x23, rd==x5, +/* opcode: fcvt.wu.h ; op1:x23; dest:x5; op1val:0x0; valaddr_reg:x1; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x5, x23, dyn, 0, 0, x1, 13*FLEN/8, x25, x11, x3,FLREG) + +inst_14:// rs1==x28, rd==x13, +/* opcode: fcvt.wu.h ; op1:x28; dest:x13; op1val:0x0; valaddr_reg:x1; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x13, x28, dyn, 0, 0, x1, 14*FLEN/8, x25, x11, x3,FLREG) + +inst_15:// rs1==x15, rd==x19, +/* opcode: fcvt.wu.h ; op1:x15; dest:x19; op1val:0x0; valaddr_reg:x1; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x19, x15, dyn, 0, 0, x1, 15*FLEN/8, x25, x11, x3,FLREG) + +inst_16:// rs1==x12, rd==x18, +/* opcode: fcvt.wu.h ; op1:x12; dest:x18; op1val:0x0; valaddr_reg:x1; +val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x18, x12, dyn, 0, 0, x1, 16*FLEN/8, x25, x11, x3,FLREG) + +inst_17:// rs1==x14, rd==x24, +/* opcode: fcvt.wu.h ; op1:x14; dest:x24; op1val:0x0; valaddr_reg:x1; +val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x24, x14, dyn, 0, 0, x1, 17*FLEN/8, x25, x11, x3,FLREG) +RVTEST_VALBASEUPD(x12,test_dataset_1) + +inst_18:// rs1==x22, rd==x1, +/* opcode: fcvt.wu.h ; op1:x22; dest:x1; op1val:0x0; valaddr_reg:x12; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x1, x22, dyn, 0, 0, x12, 0*FLEN/8, x13, x11, x3,FLREG) + +inst_19:// rs1==x3, rd==x30, +/* opcode: fcvt.wu.h ; op1:x3; dest:x30; op1val:0x0; valaddr_reg:x12; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x30, x3, dyn, 0, 0, x12, 1*FLEN/8, x13, x11, x7,FLREG) +RVTEST_SIGBASE(x5,signature_x5_0) + +inst_20:// rs1==x9, rd==x23, +/* opcode: fcvt.wu.h ; op1:x9; dest:x23; op1val:0x0; valaddr_reg:x12; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x23, x9, dyn, 0, 0, x12, 2*FLEN/8, x13, x5, x7,FLREG) + +inst_21:// rs1==x0, rd==x16, +/* opcode: fcvt.wu.h ; op1:x0; dest:x16; op1val:0x0; valaddr_reg:x12; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x16, x0, dyn, 0, 0, x12, 3*FLEN/8, x13, x5, x7,FLREG) + +inst_22:// rs1==x29, rd==x28, +/* opcode: fcvt.wu.h ; op1:x29; dest:x28; op1val:0x0; valaddr_reg:x12; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x28, x29, dyn, 0, 0, x12, 4*FLEN/8, x13, x5, x7,FLREG) + +inst_23:// rs1==x2, rd==x15, +/* opcode: fcvt.wu.h ; op1:x2; dest:x15; op1val:0x0; valaddr_reg:x12; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x15, x2, dyn, 0, 0, x12, 5*FLEN/8, x13, x5, x7,FLREG) + +inst_24:// rs1==x11, rd==x8, +/* opcode: fcvt.wu.h ; op1:x11; dest:x8; op1val:0x0; valaddr_reg:x12; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x8, x11, dyn, 0, 0, x12, 6*FLEN/8, x13, x5, x7,FLREG) + +inst_25:// rs1==x20, rd==x11, +/* opcode: fcvt.wu.h ; op1:x20; dest:x11; op1val:0x0; valaddr_reg:x12; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x11, x20, dyn, 0, 0, x12, 7*FLEN/8, x13, x5, x7,FLREG) + +inst_26:// rs1==x30, rd==x31, +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x0; valaddr_reg:x12; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 0, 0, x12, 8*FLEN/8, x13, x5, x7,FLREG) + +inst_27:// rs1==x24, rd==x14, +/* opcode: fcvt.wu.h ; op1:x24; dest:x14; op1val:0x0; valaddr_reg:x12; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x14, x24, dyn, 0, 0, x12, 9*FLEN/8, x13, x5, x7,FLREG) + +inst_28:// rs1==x6, rd==x25, +/* opcode: fcvt.wu.h ; op1:x6; dest:x25; op1val:0x0; valaddr_reg:x12; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x25, x6, dyn, 0, 0, x12, 10*FLEN/8, x13, x5, x7,FLREG) + +inst_29:// rs1==x10, rd==x3, +/* opcode: fcvt.wu.h ; op1:x10; dest:x3; op1val:0x0; valaddr_reg:x12; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x3, x10, dyn, 0, 0, x12, 11*FLEN/8, x13, x5, x7,FLREG) + +inst_30:// rs1==x1, rd==x29, +/* opcode: fcvt.wu.h ; op1:x1; dest:x29; op1val:0x0; valaddr_reg:x12; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x29, x1, dyn, 0, 0, x12, 12*FLEN/8, x13, x5, x7,FLREG) + +inst_31:// rs1==x25, rd==x4, +/* opcode: fcvt.wu.h ; op1:x25; dest:x4; op1val:0x0; valaddr_reg:x12; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x4, x25, dyn, 0, 0, x12, 13*FLEN/8, x13, x5, x7,FLREG) + +inst_32:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xfd55; valaddr_reg:x12; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 0, 0, x12, 14*FLEN/8, x13, x5, x7,FLREG) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(31745,32,FLEN) +NAN_BOXED(64513,16,FLEN) +NAN_BOXED(32085,32,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32257,32,FLEN) +NAN_BOXED(65025,16,FLEN) +NAN_BOXED(32341,32,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +test_dataset_1: +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64853,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x11_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x11_1: + .fill 40*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x5_0: + .fill 26*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fcvt.wu.h_b28-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fcvt.wu.h_b28-01.S new file mode 100644 index 000000000..a2418e58c --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fcvt.wu.h_b28-01.S @@ -0,0 +1,328 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 06:01:25 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fcvt.wu.h.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.wu.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fcvt.wu.h_b28 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fcvt.wu.h_b28) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x19,test_dataset_0) +RVTEST_SIGBASE(x8,signature_x8_1) + +inst_0:// rs1==x20, rd==x11,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x20; dest:x11; op1val:0x0; valaddr_reg:x19; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x15; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x11, x20, dyn, 0, 0, x19, 0*FLEN/8, x23, x8, x15,FLREG) + +inst_1:// rs1==x2, rd==x10,fs1 == 0 and fe1 == 0x0e and fm1 == 0x092 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x2; dest:x10; op1val:0x3892; valaddr_reg:x19; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x15; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x10, x2, dyn, 0, 0, x19, 1*FLEN/8, x23, x8, x15,FLREG) + +inst_2:// rs1==x27, rd==x20,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x27; dest:x20; op1val:0x3c00; valaddr_reg:x19; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x15; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x20, x27, dyn, 0, 0, x19, 2*FLEN/8, x23, x8, x15,FLREG) + +inst_3:// rs1==x14, rd==x7,fs1 == 0 and fe1 == 0x0f and fm1 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x14; dest:x7; op1val:0x3d00; valaddr_reg:x19; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x15; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x7, x14, dyn, 0, 0, x19, 3*FLEN/8, x23, x8, x15,FLREG) + +inst_4:// rs1==x30, rd==x25,fs1 == 0 and fe1 == 0x0f and fm1 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x25; op1val:0x3e00; valaddr_reg:x19; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x15; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x25, x30, dyn, 0, 0, x19, 4*FLEN/8, x23, x8, x15,FLREG) + +inst_5:// rs1==x24, rd==x17,fs1 == 0 and fe1 == 0x0f and fm1 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x24; dest:x17; op1val:0x3f00; valaddr_reg:x19; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x15; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x17, x24, dyn, 0, 0, x19, 5*FLEN/8, x23, x8, x15,FLREG) + +inst_6:// rs1==x6, rd==x26,fs1 == 0 and fe1 == 0x10 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x6; dest:x26; op1val:0x4000; valaddr_reg:x19; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x15; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x26, x6, dyn, 0, 0, x19, 6*FLEN/8, x23, x8, x15,FLREG) + +inst_7:// rs1==x16, rd==x21,fs1 == 0 and fe1 == 0x10 and fm1 == 0x080 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x16; dest:x21; op1val:0x4080; valaddr_reg:x19; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x15; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x21, x16, dyn, 0, 0, x19, 7*FLEN/8, x23, x8, x15,FLREG) + +inst_8:// rs1==x11, rd==x5,fs1 == 0 and fe1 == 0x10 and fm1 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x11; dest:x5; op1val:0x4100; valaddr_reg:x19; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x15; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x5, x11, dyn, 0, 0, x19, 8*FLEN/8, x23, x8, x15,FLREG) + +inst_9:// rs1==x21, rd==x27,fs1 == 0 and fe1 == 0x10 and fm1 == 0x180 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x21; dest:x27; op1val:0x4180; valaddr_reg:x19; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x15; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x27, x21, dyn, 0, 0, x19, 9*FLEN/8, x23, x8, x15,FLREG) + +inst_10:// rs1==x28, rd==x4,fs1 == 0 and fe1 == 0x1c and fm1 == 0x2dc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x28; dest:x4; op1val:0x72dc; valaddr_reg:x19; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x15; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x4, x28, dyn, 0, 0, x19, 10*FLEN/8, x23, x8, x15,FLREG) + +inst_11:// rs1==x18, rd==x2,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x18; dest:x2; op1val:0x77ff; valaddr_reg:x19; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x15; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x2, x18, dyn, 0, 0, x19, 11*FLEN/8, x23, x8, x15,FLREG) + +inst_12:// rs1==x7, rd==x6,fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x7; dest:x6; op1val:0x7c00; valaddr_reg:x19; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x15; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x6, x7, dyn, 0, 0, x19, 12*FLEN/8, x23, x8, x15,FLREG) + +inst_13:// rs1==x1, rd==x22,fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x1; dest:x22; op1val:0x7c01; valaddr_reg:x19; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x15; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x22, x1, dyn, 0, 0, x19, 13*FLEN/8, x23, x8, x15,FLREG) + +inst_14:// rs1==x12, rd==x13,fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x12; dest:x13; op1val:0x7e01; valaddr_reg:x19; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x15; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x13, x12, dyn, 0, 0, x19, 14*FLEN/8, x23, x8, x15,FLREG) + +inst_15:// rs1==x10, rd==x24,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x10; dest:x24; op1val:0x8000; valaddr_reg:x19; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x15; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x24, x10, dyn, 0, 0, x19, 15*FLEN/8, x23, x8, x15,FLREG) + +inst_16:// rs1==x3, rd==x9,fs1 == 1 and fe1 == 0x0d and fm1 == 0x2c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x3; dest:x9; op1val:0xb6c0; valaddr_reg:x19; +val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x15; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x9, x3, dyn, 0, 0, x19, 16*FLEN/8, x23, x8, x15,FLREG) +RVTEST_VALBASEUPD(x6,test_dataset_1) + +inst_17:// rs1==x5, rd==x28,fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x5; dest:x28; op1val:0xbc00; valaddr_reg:x6; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x15; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x28, x5, dyn, 0, 0, x6, 0*FLEN/8, x7, x8, x15,FLREG) + +inst_18:// rs1==x26, rd==x23,fs1 == 1 and fe1 == 0x10 and fm1 == 0x180 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x26; dest:x23; op1val:0xc180; valaddr_reg:x6; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x15; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x23, x26, dyn, 0, 0, x6, 1*FLEN/8, x7, x8, x15,FLREG) + +inst_19:// rs1==x19, rd==x0,fs1 == 1 and fe1 == 0x10 and fm1 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x19; dest:x0; op1val:0xc100; valaddr_reg:x6; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x0, x19, dyn, 0, 0, x6, 2*FLEN/8, x7, x8, x5,FLREG) +RVTEST_SIGBASE(x2,signature_x2_0) + +inst_20:// rs1==x25, rd==x30,fs1 == 1 and fe1 == 0x10 and fm1 == 0x080 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x25; dest:x30; op1val:0xc080; valaddr_reg:x6; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x30, x25, dyn, 0, 0, x6, 3*FLEN/8, x7, x2, x5,FLREG) + +inst_21:// rs1==x31, rd==x16,fs1 == 1 and fe1 == 0x10 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x31; dest:x16; op1val:0xc000; valaddr_reg:x6; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x16, x31, dyn, 0, 0, x6, 4*FLEN/8, x7, x2, x5,FLREG) + +inst_22:// rs1==x23, rd==x31,fs1 == 1 and fe1 == 0x0f and fm1 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x23; dest:x31; op1val:0xbf00; valaddr_reg:x6; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x31, x23, dyn, 0, 0, x6, 5*FLEN/8, x7, x2, x5,FLREG) + +inst_23:// rs1==x13, rd==x18,fs1 == 1 and fe1 == 0x0f and fm1 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x13; dest:x18; op1val:0xbe00; valaddr_reg:x6; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x18, x13, dyn, 0, 0, x6, 6*FLEN/8, x7, x2, x5,FLREG) + +inst_24:// rs1==x9, rd==x29,fs1 == 1 and fe1 == 0x0f and fm1 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x9; dest:x29; op1val:0xbd00; valaddr_reg:x6; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x29, x9, dyn, 0, 0, x6, 7*FLEN/8, x7, x2, x5,FLREG) + +inst_25:// rs1==x4, rd==x3,fs1 == 1 and fe1 == 0x1d and fm1 == 0x259 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x4; dest:x3; op1val:0xf659; valaddr_reg:x6; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x3, x4, dyn, 0, 0, x6, 8*FLEN/8, x7, x2, x5,FLREG) + +inst_26:// rs1==x22, rd==x15,fs1 == 1 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x22; dest:x15; op1val:0xf800; valaddr_reg:x6; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x15, x22, dyn, 0, 0, x6, 9*FLEN/8, x7, x2, x5,FLREG) + +inst_27:// rs1==x29, rd==x8,fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x29; dest:x8; op1val:0xfc00; valaddr_reg:x6; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x8, x29, dyn, 0, 0, x6, 10*FLEN/8, x7, x2, x5,FLREG) + +inst_28:// rs1==x15, rd==x14, +/* opcode: fcvt.wu.h ; op1:x15; dest:x14; op1val:0x0; valaddr_reg:x6; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x14, x15, dyn, 0, 0, x6, 11*FLEN/8, x7, x2, x5,FLREG) + +inst_29:// rs1==x8, rd==x1, +/* opcode: fcvt.wu.h ; op1:x8; dest:x1; op1val:0x0; valaddr_reg:x6; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x1, x8, dyn, 0, 0, x6, 12*FLEN/8, x7, x2, x5,FLREG) + +inst_30:// rs1==x17, rd==x19, +/* opcode: fcvt.wu.h ; op1:x17; dest:x19; op1val:0x0; valaddr_reg:x6; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x19, x17, dyn, 0, 0, x6, 13*FLEN/8, x7, x2, x5,FLREG) + +inst_31:// rs1==x0, rd==x12, +/* opcode: fcvt.wu.h ; op1:x0; dest:x12; op1val:0x0; valaddr_reg:x6; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x12, x0, dyn, 0, 0, x6, 14*FLEN/8, x7, x2, x5,FLREG) + +inst_32:// fs1 == 1 and fe1 == 0x10 and fm1 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xc100; valaddr_reg:x6; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 0, 0, x6, 15*FLEN/8, x7, x2, x5,FLREG) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(14482,32,FLEN) +NAN_BOXED(15360,32,FLEN) +NAN_BOXED(15616,32,FLEN) +NAN_BOXED(15872,32,FLEN) +NAN_BOXED(16128,32,FLEN) +NAN_BOXED(16384,32,FLEN) +NAN_BOXED(16512,32,FLEN) +NAN_BOXED(16640,32,FLEN) +NAN_BOXED(16768,32,FLEN) +NAN_BOXED(29404,32,FLEN) +NAN_BOXED(30719,32,FLEN) +NAN_BOXED(31744,32,FLEN) +NAN_BOXED(31745,32,FLEN) +NAN_BOXED(32257,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(46784,16,FLEN) +test_dataset_1: +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(49536,16,FLEN) +NAN_BOXED(49408,16,FLEN) +NAN_BOXED(49280,16,FLEN) +NAN_BOXED(49152,16,FLEN) +NAN_BOXED(48896,16,FLEN) +NAN_BOXED(48640,16,FLEN) +NAN_BOXED(48384,16,FLEN) +NAN_BOXED(63065,16,FLEN) +NAN_BOXED(63488,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(49408,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x8_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x8_1: + .fill 40*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_0: + .fill 26*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fcvt.wu.h_b29-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fcvt.wu.h_b29-01.S new file mode 100644 index 000000000..081686605 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fcvt.wu.h_b29-01.S @@ -0,0 +1,673 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 06:01:25 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fcvt.wu.h.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.wu.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fcvt.wu.h_b29 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fcvt.wu.h_b29) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x1,test_dataset_0) +RVTEST_SIGBASE(x12,signature_x12_1) + +inst_0:// rs1==x21, rd==x8,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x21; dest:x8; op1val:0x3248; valaddr_reg:x1; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x11; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x8, x21, dyn, 0, 0, x1, 0*FLEN/8, x18, x12, x11,FLREG) + +inst_1:// rs1==x14, rd==x10,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x14; dest:x10; op1val:0x3248; valaddr_reg:x1; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x11; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.wu.h, x10, x14, dyn, 32, 0, x1, 1*FLEN/8, x18, x12, x11,FLREG) + +inst_2:// rs1==x9, rd==x27,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x9; dest:x27; op1val:0x3248; valaddr_reg:x1; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x11; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.wu.h, x27, x9, dyn, 64, 0, x1, 2*FLEN/8, x18, x12, x11,FLREG) + +inst_3:// rs1==x26, rd==x21,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x26; dest:x21; op1val:0x3248; valaddr_reg:x1; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x11; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.wu.h, x21, x26, dyn, 96, 0, x1, 3*FLEN/8, x18, x12, x11,FLREG) + +inst_4:// rs1==x16, rd==x0,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x16; dest:x0; op1val:0x3248; valaddr_reg:x1; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x11; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.wu.h, x0, x16, dyn, 128, 0, x1, 4*FLEN/8, x18, x12, x11,FLREG) + +inst_5:// rs1==x22, rd==x6,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x22; dest:x6; op1val:0x3249; valaddr_reg:x1; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x11; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x6, x22, dyn, 0, 0, x1, 5*FLEN/8, x18, x12, x11,FLREG) + +inst_6:// rs1==x4, rd==x15,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x4; dest:x15; op1val:0x3249; valaddr_reg:x1; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x11; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.wu.h, x15, x4, dyn, 32, 0, x1, 6*FLEN/8, x18, x12, x11,FLREG) + +inst_7:// rs1==x5, rd==x7,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x5; dest:x7; op1val:0x3249; valaddr_reg:x1; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x11; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.wu.h, x7, x5, dyn, 64, 0, x1, 7*FLEN/8, x18, x12, x11,FLREG) + +inst_8:// rs1==x3, rd==x30,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x3; dest:x30; op1val:0x3249; valaddr_reg:x1; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x11; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.wu.h, x30, x3, dyn, 96, 0, x1, 8*FLEN/8, x18, x12, x11,FLREG) + +inst_9:// rs1==x29, rd==x4,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x29; dest:x4; op1val:0x3249; valaddr_reg:x1; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x11; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.wu.h, x4, x29, dyn, 128, 0, x1, 9*FLEN/8, x18, x12, x11,FLREG) + +inst_10:// rs1==x19, rd==x3,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x19; dest:x3; op1val:0x324a; valaddr_reg:x1; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x11; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x3, x19, dyn, 0, 0, x1, 10*FLEN/8, x18, x12, x11,FLREG) + +inst_11:// rs1==x28, rd==x22,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x28; dest:x22; op1val:0x324a; valaddr_reg:x1; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x11; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.wu.h, x22, x28, dyn, 32, 0, x1, 11*FLEN/8, x18, x12, x11,FLREG) + +inst_12:// rs1==x13, rd==x19,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x13; dest:x19; op1val:0x324a; valaddr_reg:x1; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x11; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.wu.h, x19, x13, dyn, 64, 0, x1, 12*FLEN/8, x18, x12, x11,FLREG) + +inst_13:// rs1==x17, rd==x24,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x17; dest:x24; op1val:0x324a; valaddr_reg:x1; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x11; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.wu.h, x24, x17, dyn, 96, 0, x1, 13*FLEN/8, x18, x12, x11,FLREG) + +inst_14:// rs1==x24, rd==x31,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x24; dest:x31; op1val:0x324a; valaddr_reg:x1; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x11; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.wu.h, x31, x24, dyn, 128, 0, x1, 14*FLEN/8, x18, x12, x11,FLREG) + +inst_15:// rs1==x25, rd==x2,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x25; dest:x2; op1val:0x324b; valaddr_reg:x1; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x11; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x2, x25, dyn, 0, 0, x1, 15*FLEN/8, x18, x12, x11,FLREG) +RVTEST_VALBASEUPD(x9,test_dataset_1) + +inst_16:// rs1==x1, rd==x17,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x1; dest:x17; op1val:0x324b; valaddr_reg:x9; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x11; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.wu.h, x17, x1, dyn, 32, 0, x9, 0*FLEN/8, x19, x12, x11,FLREG) + +inst_17:// rs1==x11, rd==x14,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x11; dest:x14; op1val:0x324b; valaddr_reg:x9; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.wu.h, x14, x11, dyn, 64, 0, x9, 1*FLEN/8, x19, x12, x4,FLREG) +RVTEST_SIGBASE(x3,signature_x3_0) + +inst_18:// rs1==x30, rd==x28,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x28; op1val:0x324b; valaddr_reg:x9; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.wu.h, x28, x30, dyn, 96, 0, x9, 2*FLEN/8, x19, x3, x4,FLREG) + +inst_19:// rs1==x15, rd==x16,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x15; dest:x16; op1val:0x324b; valaddr_reg:x9; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.wu.h, x16, x15, dyn, 128, 0, x9, 3*FLEN/8, x19, x3, x4,FLREG) + +inst_20:// rs1==x20, rd==x23,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x20; dest:x23; op1val:0x324c; valaddr_reg:x9; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x23, x20, dyn, 0, 0, x9, 4*FLEN/8, x19, x3, x4,FLREG) + +inst_21:// rs1==x31, rd==x29,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x31; dest:x29; op1val:0x324c; valaddr_reg:x9; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.wu.h, x29, x31, dyn, 32, 0, x9, 5*FLEN/8, x19, x3, x4,FLREG) + +inst_22:// rs1==x10, rd==x1,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x10; dest:x1; op1val:0x324c; valaddr_reg:x9; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.wu.h, x1, x10, dyn, 64, 0, x9, 6*FLEN/8, x19, x3, x4,FLREG) + +inst_23:// rs1==x0, rd==x12,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x0; dest:x12; op1val:0x0; valaddr_reg:x9; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.wu.h, x12, x0, dyn, 96, 0, x9, 7*FLEN/8, x19, x3, x4,FLREG) + +inst_24:// rs1==x2, rd==x18,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x2; dest:x18; op1val:0x324c; valaddr_reg:x9; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.wu.h, x18, x2, dyn, 128, 0, x9, 8*FLEN/8, x19, x3, x4,FLREG) + +inst_25:// rs1==x6, rd==x25,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x6; dest:x25; op1val:0x324d; valaddr_reg:x9; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x25, x6, dyn, 0, 0, x9, 9*FLEN/8, x19, x3, x4,FLREG) + +inst_26:// rs1==x8, rd==x5,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x8; dest:x5; op1val:0x324d; valaddr_reg:x9; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.wu.h, x5, x8, dyn, 32, 0, x9, 10*FLEN/8, x19, x3, x4,FLREG) + +inst_27:// rs1==x12, rd==x20,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x12; dest:x20; op1val:0x324d; valaddr_reg:x9; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.wu.h, x20, x12, dyn, 64, 0, x9, 11*FLEN/8, x19, x3, x4,FLREG) + +inst_28:// rs1==x27, rd==x13,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x27; dest:x13; op1val:0x324d; valaddr_reg:x9; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.wu.h, x13, x27, dyn, 96, 0, x9, 12*FLEN/8, x19, x3, x4,FLREG) + +inst_29:// rs1==x18, rd==x11,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x18; dest:x11; op1val:0x324d; valaddr_reg:x9; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.wu.h, x11, x18, dyn, 128, 0, x9, 13*FLEN/8, x19, x3, x4,FLREG) + +inst_30:// rs1==x7, rd==x26,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x7; dest:x26; op1val:0x324e; valaddr_reg:x9; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x26, x7, dyn, 0, 0, x9, 14*FLEN/8, x19, x3, x4,FLREG) +RVTEST_VALBASEUPD(x1,test_dataset_2) + +inst_31:// rs1==x23, rd==x9,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x23; dest:x9; op1val:0x324e; valaddr_reg:x1; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.wu.h, x9, x23, dyn, 32, 0, x1, 0*FLEN/8, x2, x3, x4,FLREG) + +inst_32:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x324e; valaddr_reg:x1; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 64, 0, x1, 1*FLEN/8, x2, x3, x4,FLREG) + +inst_33:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x324e; valaddr_reg:x1; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 96, 0, x1, 2*FLEN/8, x2, x3, x4,FLREG) + +inst_34:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x324e; valaddr_reg:x1; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 128, 0, x1, 3*FLEN/8, x2, x3, x4,FLREG) + +inst_35:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x324f; valaddr_reg:x1; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 0, 0, x1, 4*FLEN/8, x2, x3, x4,FLREG) + +inst_36:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x324f; valaddr_reg:x1; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 32, 0, x1, 5*FLEN/8, x2, x3, x4,FLREG) + +inst_37:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x324f; valaddr_reg:x1; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 64, 0, x1, 6*FLEN/8, x2, x3, x4,FLREG) + +inst_38:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x324f; valaddr_reg:x1; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 96, 0, x1, 7*FLEN/8, x2, x3, x4,FLREG) + +inst_39:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x324f; valaddr_reg:x1; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 128, 0, x1, 8*FLEN/8, x2, x3, x4,FLREG) + +inst_40:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xb248; valaddr_reg:x1; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 0, 0, x1, 9*FLEN/8, x2, x3, x4,FLREG) + +inst_41:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xb248; valaddr_reg:x1; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 32, 0, x1, 10*FLEN/8, x2, x3, x4,FLREG) + +inst_42:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xb248; valaddr_reg:x1; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 64, 0, x1, 11*FLEN/8, x2, x3, x4,FLREG) + +inst_43:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xb248; valaddr_reg:x1; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 96, 0, x1, 12*FLEN/8, x2, x3, x4,FLREG) + +inst_44:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xb248; valaddr_reg:x1; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 128, 0, x1, 13*FLEN/8, x2, x3, x4,FLREG) + +inst_45:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xb249; valaddr_reg:x1; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 0, 0, x1, 14*FLEN/8, x2, x3, x4,FLREG) + +inst_46:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xb249; valaddr_reg:x1; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 32, 0, x1, 15*FLEN/8, x2, x3, x4,FLREG) + +inst_47:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xb249; valaddr_reg:x1; +val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 64, 0, x1, 16*FLEN/8, x2, x3, x4,FLREG) + +inst_48:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xb249; valaddr_reg:x1; +val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 96, 0, x1, 17*FLEN/8, x2, x3, x4,FLREG) + +inst_49:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xb249; valaddr_reg:x1; +val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 128, 0, x1, 18*FLEN/8, x2, x3, x4,FLREG) + +inst_50:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xb24a; valaddr_reg:x1; +val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 0, 0, x1, 19*FLEN/8, x2, x3, x4,FLREG) + +inst_51:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xb24a; valaddr_reg:x1; +val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 32, 0, x1, 20*FLEN/8, x2, x3, x4,FLREG) + +inst_52:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xb24a; valaddr_reg:x1; +val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 64, 0, x1, 21*FLEN/8, x2, x3, x4,FLREG) + +inst_53:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xb24a; valaddr_reg:x1; +val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 96, 0, x1, 22*FLEN/8, x2, x3, x4,FLREG) + +inst_54:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xb24a; valaddr_reg:x1; +val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 128, 0, x1, 23*FLEN/8, x2, x3, x4,FLREG) + +inst_55:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xb24b; valaddr_reg:x1; +val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 0, 0, x1, 24*FLEN/8, x2, x3, x4,FLREG) + +inst_56:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xb24b; valaddr_reg:x1; +val_offset:25*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 32, 0, x1, 25*FLEN/8, x2, x3, x4,FLREG) + +inst_57:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xb24b; valaddr_reg:x1; +val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 64, 0, x1, 26*FLEN/8, x2, x3, x4,FLREG) + +inst_58:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xb24b; valaddr_reg:x1; +val_offset:27*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 96, 0, x1, 27*FLEN/8, x2, x3, x4,FLREG) + +inst_59:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xb24b; valaddr_reg:x1; +val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 128, 0, x1, 28*FLEN/8, x2, x3, x4,FLREG) + +inst_60:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xb24c; valaddr_reg:x1; +val_offset:29*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 0, 0, x1, 29*FLEN/8, x2, x3, x4,FLREG) + +inst_61:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xb24c; valaddr_reg:x1; +val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 32, 0, x1, 30*FLEN/8, x2, x3, x4,FLREG) + +inst_62:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xb24c; valaddr_reg:x1; +val_offset:31*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 64, 0, x1, 31*FLEN/8, x2, x3, x4,FLREG) + +inst_63:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xb24c; valaddr_reg:x1; +val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 96, 0, x1, 32*FLEN/8, x2, x3, x4,FLREG) + +inst_64:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xb24c; valaddr_reg:x1; +val_offset:33*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 128, 0, x1, 33*FLEN/8, x2, x3, x4,FLREG) + +inst_65:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xb24d; valaddr_reg:x1; +val_offset:34*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 0, 0, x1, 34*FLEN/8, x2, x3, x4,FLREG) + +inst_66:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xb24d; valaddr_reg:x1; +val_offset:35*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 32, 0, x1, 35*FLEN/8, x2, x3, x4,FLREG) + +inst_67:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xb24d; valaddr_reg:x1; +val_offset:36*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 64, 0, x1, 36*FLEN/8, x2, x3, x4,FLREG) + +inst_68:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xb24d; valaddr_reg:x1; +val_offset:37*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 96, 0, x1, 37*FLEN/8, x2, x3, x4,FLREG) + +inst_69:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xb24d; valaddr_reg:x1; +val_offset:38*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 128, 0, x1, 38*FLEN/8, x2, x3, x4,FLREG) + +inst_70:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xb24e; valaddr_reg:x1; +val_offset:39*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 0, 0, x1, 39*FLEN/8, x2, x3, x4,FLREG) + +inst_71:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xb24e; valaddr_reg:x1; +val_offset:40*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 32, 0, x1, 40*FLEN/8, x2, x3, x4,FLREG) + +inst_72:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xb24e; valaddr_reg:x1; +val_offset:41*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 64, 0, x1, 41*FLEN/8, x2, x3, x4,FLREG) + +inst_73:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xb24e; valaddr_reg:x1; +val_offset:42*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 96, 0, x1, 42*FLEN/8, x2, x3, x4,FLREG) + +inst_74:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xb24e; valaddr_reg:x1; +val_offset:43*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 128, 0, x1, 43*FLEN/8, x2, x3, x4,FLREG) + +inst_75:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xb24f; valaddr_reg:x1; +val_offset:44*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 0, 0, x1, 44*FLEN/8, x2, x3, x4,FLREG) + +inst_76:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xb24f; valaddr_reg:x1; +val_offset:45*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 32, 0, x1, 45*FLEN/8, x2, x3, x4,FLREG) + +inst_77:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xb24f; valaddr_reg:x1; +val_offset:46*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 64, 0, x1, 46*FLEN/8, x2, x3, x4,FLREG) + +inst_78:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xb24f; valaddr_reg:x1; +val_offset:47*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 96, 0, x1, 47*FLEN/8, x2, x3, x4,FLREG) + +inst_79:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0xb24f; valaddr_reg:x1; +val_offset:48*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 128, 0, x1, 48*FLEN/8, x2, x3, x4,FLREG) + +inst_80:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x3248; valaddr_reg:x1; +val_offset:49*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 128, 0, x1, 49*FLEN/8, x2, x3, x4,FLREG) + +inst_81:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.wu.h ; op1:x30; dest:x31; op1val:0x324c; valaddr_reg:x1; +val_offset:50*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.wu.h, x31, x30, dyn, 96, 0, x1, 50*FLEN/8, x2, x3, x4,FLREG) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(12872,32,FLEN) +NAN_BOXED(12872,32,FLEN) +NAN_BOXED(12872,32,FLEN) +NAN_BOXED(12872,32,FLEN) +NAN_BOXED(12872,32,FLEN) +NAN_BOXED(12873,32,FLEN) +NAN_BOXED(12873,32,FLEN) +NAN_BOXED(12873,32,FLEN) +NAN_BOXED(12873,32,FLEN) +NAN_BOXED(12873,32,FLEN) +NAN_BOXED(12874,32,FLEN) +NAN_BOXED(12874,32,FLEN) +NAN_BOXED(12874,32,FLEN) +NAN_BOXED(12874,32,FLEN) +NAN_BOXED(12874,32,FLEN) +NAN_BOXED(12875,32,FLEN) +test_dataset_1: +NAN_BOXED(12875,32,FLEN) +NAN_BOXED(12875,32,FLEN) +NAN_BOXED(12875,32,FLEN) +NAN_BOXED(12875,32,FLEN) +NAN_BOXED(12876,32,FLEN) +NAN_BOXED(12876,32,FLEN) +NAN_BOXED(12876,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(12876,32,FLEN) +NAN_BOXED(12877,32,FLEN) +NAN_BOXED(12877,32,FLEN) +NAN_BOXED(12877,32,FLEN) +NAN_BOXED(12877,32,FLEN) +NAN_BOXED(12877,32,FLEN) +NAN_BOXED(12878,32,FLEN) +test_dataset_2: +NAN_BOXED(12878,16,FLEN) +NAN_BOXED(12878,16,FLEN) +NAN_BOXED(12878,16,FLEN) +NAN_BOXED(12878,16,FLEN) +NAN_BOXED(12879,16,FLEN) +NAN_BOXED(12879,16,FLEN) +NAN_BOXED(12879,16,FLEN) +NAN_BOXED(12879,16,FLEN) +NAN_BOXED(12879,16,FLEN) +NAN_BOXED(45640,16,FLEN) +NAN_BOXED(45640,16,FLEN) +NAN_BOXED(45640,16,FLEN) +NAN_BOXED(45640,16,FLEN) +NAN_BOXED(45640,16,FLEN) +NAN_BOXED(45641,16,FLEN) +NAN_BOXED(45641,16,FLEN) +NAN_BOXED(45641,16,FLEN) +NAN_BOXED(45641,16,FLEN) +NAN_BOXED(45641,16,FLEN) +NAN_BOXED(45642,16,FLEN) +NAN_BOXED(45642,16,FLEN) +NAN_BOXED(45642,16,FLEN) +NAN_BOXED(45642,16,FLEN) +NAN_BOXED(45642,16,FLEN) +NAN_BOXED(45643,16,FLEN) +NAN_BOXED(45643,16,FLEN) +NAN_BOXED(45643,16,FLEN) +NAN_BOXED(45643,16,FLEN) +NAN_BOXED(45643,16,FLEN) +NAN_BOXED(45644,16,FLEN) +NAN_BOXED(45644,16,FLEN) +NAN_BOXED(45644,16,FLEN) +NAN_BOXED(45644,16,FLEN) +NAN_BOXED(45644,16,FLEN) +NAN_BOXED(45645,16,FLEN) +NAN_BOXED(45645,16,FLEN) +NAN_BOXED(45645,16,FLEN) +NAN_BOXED(45645,16,FLEN) +NAN_BOXED(45645,16,FLEN) +NAN_BOXED(45646,16,FLEN) +NAN_BOXED(45646,16,FLEN) +NAN_BOXED(45646,16,FLEN) +NAN_BOXED(45646,16,FLEN) +NAN_BOXED(45646,16,FLEN) +NAN_BOXED(45647,16,FLEN) +NAN_BOXED(45647,16,FLEN) +NAN_BOXED(45647,16,FLEN) +NAN_BOXED(45647,16,FLEN) +NAN_BOXED(45647,16,FLEN) +NAN_BOXED(12872,16,FLEN) +NAN_BOXED(12876,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x12_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x12_1: + .fill 36*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x3_0: + .fill 128*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fdiv_b1-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fdiv_b1-01.S new file mode 100644 index 000000000..39c00f28c --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fdiv_b1-01.S @@ -0,0 +1,5936 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 05:22:24 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fdiv.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fdiv.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fdiv_b1 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fdiv_b1) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x4,signature_x4_1) + +inst_0: +// rs1 == rd != rs2, rs1==x18, rs2==x21, rd==x18,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x18; op2:x21; dest:x18; op1val:0x0; op2val:0x0; + valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fdiv.h, x18, x18, x21, dyn, 0, 0, x3, 0*FLEN/8, x15, x4, x5) + +inst_1: +// rs1 == rs2 != rd, rs1==x12, rs2==x12, rd==x27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x12; op2:x12; dest:x27; op1val:0x0; op2val:0x0; + valaddr_reg:x3; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fdiv.h, x27, x12, x12, dyn, 0, 0, x3, 2*FLEN/8, x15, x4, x5) + +inst_2: +// rs1 == rs2 == rd, rs1==x31, rs2==x31, rd==x31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x31; op2:x31; dest:x31; op1val:0x0; op2val:0x0; + valaddr_reg:x3; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fdiv.h, x31, x31, x31, dyn, 0, 0, x3, 4*FLEN/8, x15, x4, x5) + +inst_3: +// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==x8, rs2==x22, rd==x1,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x8; op2:x22; dest:x1; op1val:0x0; op2val:0x8001; + valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fdiv.h, x1, x8, x22, dyn, 0, 0, x3, 6*FLEN/8, x15, x4, x5) + +inst_4: +// rs2 == rd != rs1, rs1==x29, rs2==x30, rd==x30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x29; op2:x30; dest:x30; op1val:0x0; op2val:0x2; + valaddr_reg:x3; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fdiv.h, x30, x29, x30, dyn, 0, 0, x3, 8*FLEN/8, x15, x4, x5) + +inst_5: +// rs1==x20, rs2==x7, rd==x10,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x20; op2:x7; dest:x10; op1val:0x0; op2val:0x83fe; + valaddr_reg:x3; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fdiv.h, x10, x20, x7, dyn, 0, 0, x3, 10*FLEN/8, x15, x4, x5) + +inst_6: +// rs1==x13, rs2==x28, rd==x11,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x13; op2:x28; dest:x11; op1val:0x0; op2val:0x3ff; + valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fdiv.h, x11, x13, x28, dyn, 0, 0, x3, 12*FLEN/8, x15, x4, x5) + +inst_7: +// rs1==x16, rs2==x27, rd==x9,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x16; op2:x27; dest:x9; op1val:0x0; op2val:0x83ff; + valaddr_reg:x3; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fdiv.h, x9, x16, x27, dyn, 0, 0, x3, 14*FLEN/8, x15, x4, x5) + +inst_8: +// rs1==x0, rs2==x1, rd==x24,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x0; op2:x1; dest:x24; op1val:0x0; op2val:0x400; + valaddr_reg:x3; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fdiv.h, x24, x0, x1, dyn, 0, 0, x3, 16*FLEN/8, x15, x4, x5) + +inst_9: +// rs1==x6, rs2==x26, rd==x16,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x6; op2:x26; dest:x16; op1val:0x0; op2val:0x8400; + valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fdiv.h, x16, x6, x26, dyn, 0, 0, x3, 18*FLEN/8, x15, x4, x5) + +inst_10: +// rs1==x27, rs2==x13, rd==x17,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x27; op2:x13; dest:x17; op1val:0x0; op2val:0x401; + valaddr_reg:x3; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fdiv.h, x17, x27, x13, dyn, 0, 0, x3, 20*FLEN/8, x15, x4, x5) + +inst_11: +// rs1==x11, rs2==x2, rd==x14,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x11; op2:x2; dest:x14; op1val:0x0; op2val:0x8455; + valaddr_reg:x3; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fdiv.h, x14, x11, x2, dyn, 0, 0, x3, 22*FLEN/8, x15, x4, x5) +RVTEST_VALBASEUPD(x1,test_dataset_1) + +inst_12: +// rs1==x22, rs2==x20, rd==x3,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x22; op2:x20; dest:x3; op1val:0x0; op2val:0x7bff; + valaddr_reg:x1; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fdiv.h, x3, x22, x20, dyn, 0, 0, x1, 0*FLEN/8, x12, x4, x5) + +inst_13: +// rs1==x2, rs2==x25, rd==x6,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x2; op2:x25; dest:x6; op1val:0x0; op2val:0xfbff; + valaddr_reg:x1; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x16 +*/ +TEST_FPRR_OP(fdiv.h, x6, x2, x25, dyn, 0, 0, x1, 2*FLEN/8, x12, x4, x16) +RVTEST_SIGBASE(x11,signature_x11_0) + +inst_14: +// rs1==x4, rs2==x18, rd==x5,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x4; op2:x18; dest:x5; op1val:0x0; op2val:0x7c00; + valaddr_reg:x1; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x16 +*/ +TEST_FPRR_OP(fdiv.h, x5, x4, x18, dyn, 0, 0, x1, 4*FLEN/8, x12, x11, x16) + +inst_15: +// rs1==x10, rs2==x29, rd==x2,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x10; op2:x29; dest:x2; op1val:0x0; op2val:0xfc00; + valaddr_reg:x1; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x16 +*/ +TEST_FPRR_OP(fdiv.h, x2, x10, x29, dyn, 0, 0, x1, 6*FLEN/8, x12, x11, x16) + +inst_16: +// rs1==x26, rs2==x14, rd==x8,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x26; op2:x14; dest:x8; op1val:0x0; op2val:0x7e00; + valaddr_reg:x1; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x16 +*/ +TEST_FPRR_OP(fdiv.h, x8, x26, x14, dyn, 0, 0, x1, 8*FLEN/8, x12, x11, x16) + +inst_17: +// rs1==x19, rs2==x9, rd==x28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x19; op2:x9; dest:x28; op1val:0x0; op2val:0xfe00; + valaddr_reg:x1; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x16 +*/ +TEST_FPRR_OP(fdiv.h, x28, x19, x9, dyn, 0, 0, x1, 10*FLEN/8, x12, x11, x16) + +inst_18: +// rs1==x17, rs2==x24, rd==x29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x17; op2:x24; dest:x29; op1val:0x0; op2val:0x7e01; + valaddr_reg:x1; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x16 +*/ +TEST_FPRR_OP(fdiv.h, x29, x17, x24, dyn, 0, 0, x1, 12*FLEN/8, x12, x11, x16) + +inst_19: +// rs1==x14, rs2==x19, rd==x25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x14; op2:x19; dest:x25; op1val:0x0; op2val:0xfe55; + valaddr_reg:x1; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x16 +*/ +TEST_FPRR_OP(fdiv.h, x25, x14, x19, dyn, 0, 0, x1, 14*FLEN/8, x12, x11, x16) + +inst_20: +// rs1==x5, rs2==x15, rd==x4,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x5; op2:x15; dest:x4; op1val:0x0; op2val:0x7c01; + valaddr_reg:x1; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x16 +*/ +TEST_FPRR_OP(fdiv.h, x4, x5, x15, dyn, 0, 0, x1, 16*FLEN/8, x12, x11, x16) + +inst_21: +// rs1==x21, rs2==x23, rd==x7,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x21; op2:x23; dest:x7; op1val:0x0; op2val:0xfd55; + valaddr_reg:x1; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x16 +*/ +TEST_FPRR_OP(fdiv.h, x7, x21, x23, dyn, 0, 0, x1, 18*FLEN/8, x12, x11, x16) +RVTEST_VALBASEUPD(x14,test_dataset_2) + +inst_22: +// rs1==x3, rs2==x10, rd==x13,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x3; op2:x10; dest:x13; op1val:0x0; op2val:0x3c00; + valaddr_reg:x14; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x16 +*/ +TEST_FPRR_OP(fdiv.h, x13, x3, x10, dyn, 0, 0, x14, 0*FLEN/8, x18, x11, x16) + +inst_23: +// rs1==x25, rs2==x3, rd==x0,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x25; op2:x3; dest:x0; op1val:0x0; op2val:0xbc00; + valaddr_reg:x14; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x16 +*/ +TEST_FPRR_OP(fdiv.h, x0, x25, x3, dyn, 0, 0, x14, 2*FLEN/8, x18, x11, x16) + +inst_24: +// rs1==x1, rs2==x6, rd==x22,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x1; op2:x6; dest:x22; op1val:0x8000; op2val:0x0; + valaddr_reg:x14; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x16 +*/ +TEST_FPRR_OP(fdiv.h, x22, x1, x6, dyn, 0, 0, x14, 4*FLEN/8, x18, x11, x16) + +inst_25: +// rs1==x15, rs2==x0, rd==x21,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x15; op2:x0; dest:x21; op1val:0x8000; op2val:0x0; + valaddr_reg:x14; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x16 +*/ +TEST_FPRR_OP(fdiv.h, x21, x15, x0, dyn, 0, 0, x14, 6*FLEN/8, x18, x11, x16) + +inst_26: +// rs1==x24, rs2==x4, rd==x12,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x24; op2:x4; dest:x12; op1val:0x8000; op2val:0x1; + valaddr_reg:x14; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x16 +*/ +TEST_FPRR_OP(fdiv.h, x12, x24, x4, dyn, 0, 0, x14, 8*FLEN/8, x18, x11, x16) + +inst_27: +// rs1==x9, rs2==x17, rd==x15,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x9; op2:x17; dest:x15; op1val:0x8000; op2val:0x8001; + valaddr_reg:x14; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x15, x9, x17, dyn, 0, 0, x14, 10*FLEN/8, x18, x11, x2) + +inst_28: +// rs1==x23, rs2==x16, rd==x19,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x23; op2:x16; dest:x19; op1val:0x8000; op2val:0x2; + valaddr_reg:x14; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x19, x23, x16, dyn, 0, 0, x14, 12*FLEN/8, x18, x11, x2) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_29: +// rs1==x30, rs2==x11, rd==x26,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x11; dest:x26; op1val:0x8000; op2val:0x83fe; + valaddr_reg:x14; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x26, x30, x11, dyn, 0, 0, x14, 14*FLEN/8, x18, x1, x2) + +inst_30: +// rs1==x28, rs2==x8, rd==x20,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x28; op2:x8; dest:x20; op1val:0x8000; op2val:0x3ff; + valaddr_reg:x14; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x20, x28, x8, dyn, 0, 0, x14, 16*FLEN/8, x18, x1, x2) + +inst_31: +// rs1==x7, rs2==x5, rd==x23,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x7; op2:x5; dest:x23; op1val:0x8000; op2val:0x83ff; + valaddr_reg:x14; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x23, x7, x5, dyn, 0, 0, x14, 18*FLEN/8, x18, x1, x2) +RVTEST_VALBASEUPD(x3,test_dataset_3) + +inst_32: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x400; + valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_33: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8400; + valaddr_reg:x3; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_34: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x401; + valaddr_reg:x3; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_35: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8455; + valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_36: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x7bff; + valaddr_reg:x3; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_37: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xfbff; + valaddr_reg:x3; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_38: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x7c00; + valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_39: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xfc00; + valaddr_reg:x3; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_40: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x7e00; + valaddr_reg:x3; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_41: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xfe00; + valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_42: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x7e01; + valaddr_reg:x3; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_43: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xfe55; + valaddr_reg:x3; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_44: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x7c01; + valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_45: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xfd55; + valaddr_reg:x3; val_offset:26*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_46: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x3c00; + valaddr_reg:x3; val_offset:28*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_47: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xbc00; + valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_48: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x0; + valaddr_reg:x3; val_offset:32*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 32*FLEN/8, x4, x1, x2) + +inst_49: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x8000; + valaddr_reg:x3; val_offset:34*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 34*FLEN/8, x4, x1, x2) + +inst_50: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x1; + valaddr_reg:x3; val_offset:36*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 36*FLEN/8, x4, x1, x2) + +inst_51: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x8001; + valaddr_reg:x3; val_offset:38*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 38*FLEN/8, x4, x1, x2) + +inst_52: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x2; + valaddr_reg:x3; val_offset:40*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 40*FLEN/8, x4, x1, x2) + +inst_53: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x83fe; + valaddr_reg:x3; val_offset:42*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 42*FLEN/8, x4, x1, x2) + +inst_54: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x3ff; + valaddr_reg:x3; val_offset:44*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 44*FLEN/8, x4, x1, x2) + +inst_55: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x83ff; + valaddr_reg:x3; val_offset:46*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 46*FLEN/8, x4, x1, x2) + +inst_56: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x400; + valaddr_reg:x3; val_offset:48*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 48*FLEN/8, x4, x1, x2) + +inst_57: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x8400; + valaddr_reg:x3; val_offset:50*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 50*FLEN/8, x4, x1, x2) + +inst_58: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x401; + valaddr_reg:x3; val_offset:52*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 52*FLEN/8, x4, x1, x2) + +inst_59: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x8455; + valaddr_reg:x3; val_offset:54*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 54*FLEN/8, x4, x1, x2) + +inst_60: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7bff; + valaddr_reg:x3; val_offset:56*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 56*FLEN/8, x4, x1, x2) + +inst_61: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xfbff; + valaddr_reg:x3; val_offset:58*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 58*FLEN/8, x4, x1, x2) + +inst_62: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7c00; + valaddr_reg:x3; val_offset:60*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 60*FLEN/8, x4, x1, x2) + +inst_63: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xfc00; + valaddr_reg:x3; val_offset:62*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 62*FLEN/8, x4, x1, x2) + +inst_64: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7e00; + valaddr_reg:x3; val_offset:64*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 64*FLEN/8, x4, x1, x2) + +inst_65: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xfe00; + valaddr_reg:x3; val_offset:66*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 66*FLEN/8, x4, x1, x2) + +inst_66: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7e01; + valaddr_reg:x3; val_offset:68*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 68*FLEN/8, x4, x1, x2) + +inst_67: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xfe55; + valaddr_reg:x3; val_offset:70*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 70*FLEN/8, x4, x1, x2) + +inst_68: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7c01; + valaddr_reg:x3; val_offset:72*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 72*FLEN/8, x4, x1, x2) + +inst_69: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xfd55; + valaddr_reg:x3; val_offset:74*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 74*FLEN/8, x4, x1, x2) + +inst_70: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x3c00; + valaddr_reg:x3; val_offset:76*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 76*FLEN/8, x4, x1, x2) + +inst_71: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xbc00; + valaddr_reg:x3; val_offset:78*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 78*FLEN/8, x4, x1, x2) + +inst_72: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x0; + valaddr_reg:x3; val_offset:80*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 80*FLEN/8, x4, x1, x2) + +inst_73: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8000; + valaddr_reg:x3; val_offset:82*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 82*FLEN/8, x4, x1, x2) + +inst_74: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x1; + valaddr_reg:x3; val_offset:84*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 84*FLEN/8, x4, x1, x2) + +inst_75: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8001; + valaddr_reg:x3; val_offset:86*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 86*FLEN/8, x4, x1, x2) + +inst_76: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x2; + valaddr_reg:x3; val_offset:88*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 88*FLEN/8, x4, x1, x2) + +inst_77: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x83fe; + valaddr_reg:x3; val_offset:90*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 90*FLEN/8, x4, x1, x2) + +inst_78: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x3ff; + valaddr_reg:x3; val_offset:92*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 92*FLEN/8, x4, x1, x2) + +inst_79: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x83ff; + valaddr_reg:x3; val_offset:94*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 94*FLEN/8, x4, x1, x2) + +inst_80: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x400; + valaddr_reg:x3; val_offset:96*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 96*FLEN/8, x4, x1, x2) + +inst_81: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8400; + valaddr_reg:x3; val_offset:98*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 98*FLEN/8, x4, x1, x2) + +inst_82: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x401; + valaddr_reg:x3; val_offset:100*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 100*FLEN/8, x4, x1, x2) + +inst_83: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8455; + valaddr_reg:x3; val_offset:102*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 102*FLEN/8, x4, x1, x2) + +inst_84: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x7bff; + valaddr_reg:x3; val_offset:104*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 104*FLEN/8, x4, x1, x2) + +inst_85: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xfbff; + valaddr_reg:x3; val_offset:106*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 106*FLEN/8, x4, x1, x2) + +inst_86: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x7c00; + valaddr_reg:x3; val_offset:108*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 108*FLEN/8, x4, x1, x2) + +inst_87: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xfc00; + valaddr_reg:x3; val_offset:110*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 110*FLEN/8, x4, x1, x2) + +inst_88: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x7e00; + valaddr_reg:x3; val_offset:112*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 112*FLEN/8, x4, x1, x2) + +inst_89: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xfe00; + valaddr_reg:x3; val_offset:114*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 114*FLEN/8, x4, x1, x2) + +inst_90: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x7e01; + valaddr_reg:x3; val_offset:116*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 116*FLEN/8, x4, x1, x2) + +inst_91: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xfe55; + valaddr_reg:x3; val_offset:118*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 118*FLEN/8, x4, x1, x2) + +inst_92: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x7c01; + valaddr_reg:x3; val_offset:120*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 120*FLEN/8, x4, x1, x2) + +inst_93: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xfd55; + valaddr_reg:x3; val_offset:122*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 122*FLEN/8, x4, x1, x2) + +inst_94: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x3c00; + valaddr_reg:x3; val_offset:124*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 124*FLEN/8, x4, x1, x2) + +inst_95: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xbc00; + valaddr_reg:x3; val_offset:126*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 126*FLEN/8, x4, x1, x2) + +inst_96: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x0; + valaddr_reg:x3; val_offset:128*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 128*FLEN/8, x4, x1, x2) + +inst_97: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x8000; + valaddr_reg:x3; val_offset:130*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 130*FLEN/8, x4, x1, x2) + +inst_98: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x1; + valaddr_reg:x3; val_offset:132*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 132*FLEN/8, x4, x1, x2) + +inst_99: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x8001; + valaddr_reg:x3; val_offset:134*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 134*FLEN/8, x4, x1, x2) + +inst_100: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x2; + valaddr_reg:x3; val_offset:136*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 136*FLEN/8, x4, x1, x2) + +inst_101: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x83fe; + valaddr_reg:x3; val_offset:138*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 138*FLEN/8, x4, x1, x2) + +inst_102: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x3ff; + valaddr_reg:x3; val_offset:140*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 140*FLEN/8, x4, x1, x2) + +inst_103: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x83ff; + valaddr_reg:x3; val_offset:142*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 142*FLEN/8, x4, x1, x2) + +inst_104: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x400; + valaddr_reg:x3; val_offset:144*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 144*FLEN/8, x4, x1, x2) + +inst_105: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x8400; + valaddr_reg:x3; val_offset:146*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 146*FLEN/8, x4, x1, x2) + +inst_106: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x401; + valaddr_reg:x3; val_offset:148*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 148*FLEN/8, x4, x1, x2) + +inst_107: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x8455; + valaddr_reg:x3; val_offset:150*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 150*FLEN/8, x4, x1, x2) + +inst_108: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x7bff; + valaddr_reg:x3; val_offset:152*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 152*FLEN/8, x4, x1, x2) + +inst_109: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xfbff; + valaddr_reg:x3; val_offset:154*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 154*FLEN/8, x4, x1, x2) + +inst_110: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x7c00; + valaddr_reg:x3; val_offset:156*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 156*FLEN/8, x4, x1, x2) + +inst_111: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xfc00; + valaddr_reg:x3; val_offset:158*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 158*FLEN/8, x4, x1, x2) + +inst_112: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x7e00; + valaddr_reg:x3; val_offset:160*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 160*FLEN/8, x4, x1, x2) + +inst_113: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xfe00; + valaddr_reg:x3; val_offset:162*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 162*FLEN/8, x4, x1, x2) + +inst_114: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x7e01; + valaddr_reg:x3; val_offset:164*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 164*FLEN/8, x4, x1, x2) + +inst_115: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xfe55; + valaddr_reg:x3; val_offset:166*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 166*FLEN/8, x4, x1, x2) + +inst_116: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x7c01; + valaddr_reg:x3; val_offset:168*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 168*FLEN/8, x4, x1, x2) + +inst_117: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xfd55; + valaddr_reg:x3; val_offset:170*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 170*FLEN/8, x4, x1, x2) + +inst_118: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x3c00; + valaddr_reg:x3; val_offset:172*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 172*FLEN/8, x4, x1, x2) + +inst_119: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xbc00; + valaddr_reg:x3; val_offset:174*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 174*FLEN/8, x4, x1, x2) + +inst_120: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x0; + valaddr_reg:x3; val_offset:176*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 176*FLEN/8, x4, x1, x2) + +inst_121: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x8000; + valaddr_reg:x3; val_offset:178*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 178*FLEN/8, x4, x1, x2) + +inst_122: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x1; + valaddr_reg:x3; val_offset:180*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 180*FLEN/8, x4, x1, x2) + +inst_123: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x8001; + valaddr_reg:x3; val_offset:182*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 182*FLEN/8, x4, x1, x2) + +inst_124: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x2; + valaddr_reg:x3; val_offset:184*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 184*FLEN/8, x4, x1, x2) + +inst_125: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x83fe; + valaddr_reg:x3; val_offset:186*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 186*FLEN/8, x4, x1, x2) + +inst_126: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x3ff; + valaddr_reg:x3; val_offset:188*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 188*FLEN/8, x4, x1, x2) + +inst_127: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x83ff; + valaddr_reg:x3; val_offset:190*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 190*FLEN/8, x4, x1, x2) + +inst_128: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x400; + valaddr_reg:x3; val_offset:192*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 192*FLEN/8, x4, x1, x2) + +inst_129: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x8400; + valaddr_reg:x3; val_offset:194*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 194*FLEN/8, x4, x1, x2) + +inst_130: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x401; + valaddr_reg:x3; val_offset:196*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 196*FLEN/8, x4, x1, x2) + +inst_131: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x8455; + valaddr_reg:x3; val_offset:198*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 198*FLEN/8, x4, x1, x2) + +inst_132: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x7bff; + valaddr_reg:x3; val_offset:200*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 200*FLEN/8, x4, x1, x2) + +inst_133: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xfbff; + valaddr_reg:x3; val_offset:202*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 202*FLEN/8, x4, x1, x2) + +inst_134: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x7c00; + valaddr_reg:x3; val_offset:204*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 204*FLEN/8, x4, x1, x2) + +inst_135: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xfc00; + valaddr_reg:x3; val_offset:206*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 206*FLEN/8, x4, x1, x2) + +inst_136: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x7e00; + valaddr_reg:x3; val_offset:208*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 208*FLEN/8, x4, x1, x2) + +inst_137: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xfe00; + valaddr_reg:x3; val_offset:210*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 210*FLEN/8, x4, x1, x2) + +inst_138: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x7e01; + valaddr_reg:x3; val_offset:212*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 212*FLEN/8, x4, x1, x2) + +inst_139: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xfe55; + valaddr_reg:x3; val_offset:214*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 214*FLEN/8, x4, x1, x2) + +inst_140: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x7c01; + valaddr_reg:x3; val_offset:216*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 216*FLEN/8, x4, x1, x2) + +inst_141: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xfd55; + valaddr_reg:x3; val_offset:218*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 218*FLEN/8, x4, x1, x2) + +inst_142: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x3c00; + valaddr_reg:x3; val_offset:220*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 220*FLEN/8, x4, x1, x2) + +inst_143: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xbc00; + valaddr_reg:x3; val_offset:222*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 222*FLEN/8, x4, x1, x2) + +inst_144: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x0; + valaddr_reg:x3; val_offset:224*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 224*FLEN/8, x4, x1, x2) + +inst_145: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x8000; + valaddr_reg:x3; val_offset:226*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 226*FLEN/8, x4, x1, x2) + +inst_146: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x1; + valaddr_reg:x3; val_offset:228*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 228*FLEN/8, x4, x1, x2) + +inst_147: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x8001; + valaddr_reg:x3; val_offset:230*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 230*FLEN/8, x4, x1, x2) + +inst_148: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x2; + valaddr_reg:x3; val_offset:232*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 232*FLEN/8, x4, x1, x2) + +inst_149: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x83fe; + valaddr_reg:x3; val_offset:234*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 234*FLEN/8, x4, x1, x2) + +inst_150: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x3ff; + valaddr_reg:x3; val_offset:236*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 236*FLEN/8, x4, x1, x2) + +inst_151: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x83ff; + valaddr_reg:x3; val_offset:238*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 238*FLEN/8, x4, x1, x2) + +inst_152: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x400; + valaddr_reg:x3; val_offset:240*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 240*FLEN/8, x4, x1, x2) + +inst_153: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x8400; + valaddr_reg:x3; val_offset:242*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 242*FLEN/8, x4, x1, x2) + +inst_154: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x401; + valaddr_reg:x3; val_offset:244*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 244*FLEN/8, x4, x1, x2) + +inst_155: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x8455; + valaddr_reg:x3; val_offset:246*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 246*FLEN/8, x4, x1, x2) + +inst_156: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7bff; + valaddr_reg:x3; val_offset:248*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 248*FLEN/8, x4, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_157: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xfbff; + valaddr_reg:x3; val_offset:250*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 250*FLEN/8, x4, x1, x2) + +inst_158: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7c00; + valaddr_reg:x3; val_offset:252*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 252*FLEN/8, x4, x1, x2) + +inst_159: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xfc00; + valaddr_reg:x3; val_offset:254*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 254*FLEN/8, x4, x1, x2) + +inst_160: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7e00; + valaddr_reg:x3; val_offset:256*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 256*FLEN/8, x4, x1, x2) + +inst_161: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xfe00; + valaddr_reg:x3; val_offset:258*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 258*FLEN/8, x4, x1, x2) + +inst_162: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7e01; + valaddr_reg:x3; val_offset:260*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 260*FLEN/8, x4, x1, x2) + +inst_163: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xfe55; + valaddr_reg:x3; val_offset:262*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 262*FLEN/8, x4, x1, x2) + +inst_164: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7c01; + valaddr_reg:x3; val_offset:264*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 264*FLEN/8, x4, x1, x2) + +inst_165: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xfd55; + valaddr_reg:x3; val_offset:266*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 266*FLEN/8, x4, x1, x2) + +inst_166: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x3c00; + valaddr_reg:x3; val_offset:268*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 268*FLEN/8, x4, x1, x2) + +inst_167: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xbc00; + valaddr_reg:x3; val_offset:270*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 270*FLEN/8, x4, x1, x2) + +inst_168: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x0; + valaddr_reg:x3; val_offset:272*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 272*FLEN/8, x4, x1, x2) + +inst_169: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8000; + valaddr_reg:x3; val_offset:274*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 274*FLEN/8, x4, x1, x2) + +inst_170: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x1; + valaddr_reg:x3; val_offset:276*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 276*FLEN/8, x4, x1, x2) + +inst_171: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8001; + valaddr_reg:x3; val_offset:278*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 278*FLEN/8, x4, x1, x2) + +inst_172: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x2; + valaddr_reg:x3; val_offset:280*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 280*FLEN/8, x4, x1, x2) + +inst_173: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x83fe; + valaddr_reg:x3; val_offset:282*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 282*FLEN/8, x4, x1, x2) + +inst_174: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x3ff; + valaddr_reg:x3; val_offset:284*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 284*FLEN/8, x4, x1, x2) + +inst_175: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x83ff; + valaddr_reg:x3; val_offset:286*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 286*FLEN/8, x4, x1, x2) + +inst_176: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x400; + valaddr_reg:x3; val_offset:288*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 288*FLEN/8, x4, x1, x2) + +inst_177: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8400; + valaddr_reg:x3; val_offset:290*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 290*FLEN/8, x4, x1, x2) + +inst_178: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x401; + valaddr_reg:x3; val_offset:292*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 292*FLEN/8, x4, x1, x2) + +inst_179: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8455; + valaddr_reg:x3; val_offset:294*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 294*FLEN/8, x4, x1, x2) + +inst_180: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x7bff; + valaddr_reg:x3; val_offset:296*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 296*FLEN/8, x4, x1, x2) + +inst_181: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xfbff; + valaddr_reg:x3; val_offset:298*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 298*FLEN/8, x4, x1, x2) + +inst_182: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x7c00; + valaddr_reg:x3; val_offset:300*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 300*FLEN/8, x4, x1, x2) + +inst_183: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xfc00; + valaddr_reg:x3; val_offset:302*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 302*FLEN/8, x4, x1, x2) + +inst_184: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x7e00; + valaddr_reg:x3; val_offset:304*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 304*FLEN/8, x4, x1, x2) + +inst_185: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xfe00; + valaddr_reg:x3; val_offset:306*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 306*FLEN/8, x4, x1, x2) + +inst_186: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x7e01; + valaddr_reg:x3; val_offset:308*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 308*FLEN/8, x4, x1, x2) + +inst_187: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xfe55; + valaddr_reg:x3; val_offset:310*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 310*FLEN/8, x4, x1, x2) + +inst_188: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x7c01; + valaddr_reg:x3; val_offset:312*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 312*FLEN/8, x4, x1, x2) + +inst_189: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xfd55; + valaddr_reg:x3; val_offset:314*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 314*FLEN/8, x4, x1, x2) + +inst_190: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x3c00; + valaddr_reg:x3; val_offset:316*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 316*FLEN/8, x4, x1, x2) + +inst_191: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xbc00; + valaddr_reg:x3; val_offset:318*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 318*FLEN/8, x4, x1, x2) + +inst_192: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x0; + valaddr_reg:x3; val_offset:320*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 320*FLEN/8, x4, x1, x2) + +inst_193: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x8000; + valaddr_reg:x3; val_offset:322*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 322*FLEN/8, x4, x1, x2) + +inst_194: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x1; + valaddr_reg:x3; val_offset:324*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 324*FLEN/8, x4, x1, x2) + +inst_195: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x8001; + valaddr_reg:x3; val_offset:326*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 326*FLEN/8, x4, x1, x2) + +inst_196: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x2; + valaddr_reg:x3; val_offset:328*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 328*FLEN/8, x4, x1, x2) + +inst_197: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x83fe; + valaddr_reg:x3; val_offset:330*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 330*FLEN/8, x4, x1, x2) + +inst_198: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x3ff; + valaddr_reg:x3; val_offset:332*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 332*FLEN/8, x4, x1, x2) + +inst_199: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x83ff; + valaddr_reg:x3; val_offset:334*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 334*FLEN/8, x4, x1, x2) + +inst_200: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x400; + valaddr_reg:x3; val_offset:336*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 336*FLEN/8, x4, x1, x2) + +inst_201: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x8400; + valaddr_reg:x3; val_offset:338*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 338*FLEN/8, x4, x1, x2) + +inst_202: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x401; + valaddr_reg:x3; val_offset:340*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 340*FLEN/8, x4, x1, x2) + +inst_203: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x8455; + valaddr_reg:x3; val_offset:342*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 342*FLEN/8, x4, x1, x2) + +inst_204: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7bff; + valaddr_reg:x3; val_offset:344*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 344*FLEN/8, x4, x1, x2) + +inst_205: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xfbff; + valaddr_reg:x3; val_offset:346*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 346*FLEN/8, x4, x1, x2) + +inst_206: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7c00; + valaddr_reg:x3; val_offset:348*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 348*FLEN/8, x4, x1, x2) + +inst_207: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xfc00; + valaddr_reg:x3; val_offset:350*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 350*FLEN/8, x4, x1, x2) + +inst_208: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7e00; + valaddr_reg:x3; val_offset:352*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 352*FLEN/8, x4, x1, x2) + +inst_209: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xfe00; + valaddr_reg:x3; val_offset:354*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 354*FLEN/8, x4, x1, x2) + +inst_210: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7e01; + valaddr_reg:x3; val_offset:356*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 356*FLEN/8, x4, x1, x2) + +inst_211: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xfe55; + valaddr_reg:x3; val_offset:358*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 358*FLEN/8, x4, x1, x2) + +inst_212: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7c01; + valaddr_reg:x3; val_offset:360*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 360*FLEN/8, x4, x1, x2) + +inst_213: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xfd55; + valaddr_reg:x3; val_offset:362*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 362*FLEN/8, x4, x1, x2) + +inst_214: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x3c00; + valaddr_reg:x3; val_offset:364*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 364*FLEN/8, x4, x1, x2) + +inst_215: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xbc00; + valaddr_reg:x3; val_offset:366*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 366*FLEN/8, x4, x1, x2) + +inst_216: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x0; + valaddr_reg:x3; val_offset:368*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 368*FLEN/8, x4, x1, x2) + +inst_217: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8000; + valaddr_reg:x3; val_offset:370*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 370*FLEN/8, x4, x1, x2) + +inst_218: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x1; + valaddr_reg:x3; val_offset:372*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 372*FLEN/8, x4, x1, x2) + +inst_219: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8001; + valaddr_reg:x3; val_offset:374*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 374*FLEN/8, x4, x1, x2) + +inst_220: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x2; + valaddr_reg:x3; val_offset:376*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 376*FLEN/8, x4, x1, x2) + +inst_221: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x83fe; + valaddr_reg:x3; val_offset:378*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 378*FLEN/8, x4, x1, x2) + +inst_222: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x3ff; + valaddr_reg:x3; val_offset:380*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 380*FLEN/8, x4, x1, x2) + +inst_223: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x83ff; + valaddr_reg:x3; val_offset:382*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 382*FLEN/8, x4, x1, x2) + +inst_224: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x400; + valaddr_reg:x3; val_offset:384*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 384*FLEN/8, x4, x1, x2) + +inst_225: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8400; + valaddr_reg:x3; val_offset:386*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 386*FLEN/8, x4, x1, x2) + +inst_226: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x401; + valaddr_reg:x3; val_offset:388*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 388*FLEN/8, x4, x1, x2) + +inst_227: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8455; + valaddr_reg:x3; val_offset:390*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 390*FLEN/8, x4, x1, x2) + +inst_228: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x7bff; + valaddr_reg:x3; val_offset:392*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 392*FLEN/8, x4, x1, x2) + +inst_229: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xfbff; + valaddr_reg:x3; val_offset:394*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 394*FLEN/8, x4, x1, x2) + +inst_230: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x7c00; + valaddr_reg:x3; val_offset:396*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 396*FLEN/8, x4, x1, x2) + +inst_231: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xfc00; + valaddr_reg:x3; val_offset:398*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 398*FLEN/8, x4, x1, x2) + +inst_232: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x7e00; + valaddr_reg:x3; val_offset:400*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 400*FLEN/8, x4, x1, x2) + +inst_233: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xfe00; + valaddr_reg:x3; val_offset:402*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 402*FLEN/8, x4, x1, x2) + +inst_234: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x7e01; + valaddr_reg:x3; val_offset:404*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 404*FLEN/8, x4, x1, x2) + +inst_235: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xfe55; + valaddr_reg:x3; val_offset:406*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 406*FLEN/8, x4, x1, x2) + +inst_236: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x7c01; + valaddr_reg:x3; val_offset:408*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 408*FLEN/8, x4, x1, x2) + +inst_237: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xfd55; + valaddr_reg:x3; val_offset:410*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 410*FLEN/8, x4, x1, x2) + +inst_238: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x3c00; + valaddr_reg:x3; val_offset:412*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 412*FLEN/8, x4, x1, x2) + +inst_239: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xbc00; + valaddr_reg:x3; val_offset:414*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 414*FLEN/8, x4, x1, x2) + +inst_240: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x0; + valaddr_reg:x3; val_offset:416*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 416*FLEN/8, x4, x1, x2) + +inst_241: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x8000; + valaddr_reg:x3; val_offset:418*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 418*FLEN/8, x4, x1, x2) + +inst_242: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x1; + valaddr_reg:x3; val_offset:420*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 420*FLEN/8, x4, x1, x2) + +inst_243: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x8001; + valaddr_reg:x3; val_offset:422*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 422*FLEN/8, x4, x1, x2) + +inst_244: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x2; + valaddr_reg:x3; val_offset:424*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 424*FLEN/8, x4, x1, x2) + +inst_245: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x83fe; + valaddr_reg:x3; val_offset:426*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 426*FLEN/8, x4, x1, x2) + +inst_246: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x3ff; + valaddr_reg:x3; val_offset:428*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 428*FLEN/8, x4, x1, x2) + +inst_247: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x83ff; + valaddr_reg:x3; val_offset:430*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 430*FLEN/8, x4, x1, x2) + +inst_248: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x400; + valaddr_reg:x3; val_offset:432*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 432*FLEN/8, x4, x1, x2) + +inst_249: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x8400; + valaddr_reg:x3; val_offset:434*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 434*FLEN/8, x4, x1, x2) + +inst_250: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x401; + valaddr_reg:x3; val_offset:436*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 436*FLEN/8, x4, x1, x2) + +inst_251: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x8455; + valaddr_reg:x3; val_offset:438*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 438*FLEN/8, x4, x1, x2) + +inst_252: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x7bff; + valaddr_reg:x3; val_offset:440*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 440*FLEN/8, x4, x1, x2) + +inst_253: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xfbff; + valaddr_reg:x3; val_offset:442*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 442*FLEN/8, x4, x1, x2) + +inst_254: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x7c00; + valaddr_reg:x3; val_offset:444*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 444*FLEN/8, x4, x1, x2) + +inst_255: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xfc00; + valaddr_reg:x3; val_offset:446*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 446*FLEN/8, x4, x1, x2) + +inst_256: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x7e00; + valaddr_reg:x3; val_offset:448*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 448*FLEN/8, x4, x1, x2) + +inst_257: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xfe00; + valaddr_reg:x3; val_offset:450*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 450*FLEN/8, x4, x1, x2) + +inst_258: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x7e01; + valaddr_reg:x3; val_offset:452*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 452*FLEN/8, x4, x1, x2) + +inst_259: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xfe55; + valaddr_reg:x3; val_offset:454*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 454*FLEN/8, x4, x1, x2) + +inst_260: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x7c01; + valaddr_reg:x3; val_offset:456*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 456*FLEN/8, x4, x1, x2) + +inst_261: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xfd55; + valaddr_reg:x3; val_offset:458*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 458*FLEN/8, x4, x1, x2) + +inst_262: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x3c00; + valaddr_reg:x3; val_offset:460*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 460*FLEN/8, x4, x1, x2) + +inst_263: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xbc00; + valaddr_reg:x3; val_offset:462*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 462*FLEN/8, x4, x1, x2) + +inst_264: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x0; + valaddr_reg:x3; val_offset:464*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 464*FLEN/8, x4, x1, x2) + +inst_265: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x8000; + valaddr_reg:x3; val_offset:466*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 466*FLEN/8, x4, x1, x2) + +inst_266: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x1; + valaddr_reg:x3; val_offset:468*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 468*FLEN/8, x4, x1, x2) + +inst_267: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x8001; + valaddr_reg:x3; val_offset:470*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 470*FLEN/8, x4, x1, x2) + +inst_268: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x2; + valaddr_reg:x3; val_offset:472*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 472*FLEN/8, x4, x1, x2) + +inst_269: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x83fe; + valaddr_reg:x3; val_offset:474*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 474*FLEN/8, x4, x1, x2) + +inst_270: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x3ff; + valaddr_reg:x3; val_offset:476*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 476*FLEN/8, x4, x1, x2) + +inst_271: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x83ff; + valaddr_reg:x3; val_offset:478*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 478*FLEN/8, x4, x1, x2) + +inst_272: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x400; + valaddr_reg:x3; val_offset:480*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 480*FLEN/8, x4, x1, x2) + +inst_273: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x8400; + valaddr_reg:x3; val_offset:482*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 482*FLEN/8, x4, x1, x2) + +inst_274: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x401; + valaddr_reg:x3; val_offset:484*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 484*FLEN/8, x4, x1, x2) + +inst_275: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x8455; + valaddr_reg:x3; val_offset:486*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 486*FLEN/8, x4, x1, x2) + +inst_276: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x7bff; + valaddr_reg:x3; val_offset:488*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 488*FLEN/8, x4, x1, x2) + +inst_277: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xfbff; + valaddr_reg:x3; val_offset:490*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 490*FLEN/8, x4, x1, x2) + +inst_278: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x7c00; + valaddr_reg:x3; val_offset:492*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 492*FLEN/8, x4, x1, x2) + +inst_279: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xfc00; + valaddr_reg:x3; val_offset:494*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 494*FLEN/8, x4, x1, x2) + +inst_280: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x7e00; + valaddr_reg:x3; val_offset:496*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 496*FLEN/8, x4, x1, x2) + +inst_281: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xfe00; + valaddr_reg:x3; val_offset:498*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 498*FLEN/8, x4, x1, x2) + +inst_282: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x7e01; + valaddr_reg:x3; val_offset:500*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 500*FLEN/8, x4, x1, x2) + +inst_283: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xfe55; + valaddr_reg:x3; val_offset:502*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 502*FLEN/8, x4, x1, x2) + +inst_284: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x7c01; + valaddr_reg:x3; val_offset:504*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 504*FLEN/8, x4, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_2) + +inst_285: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xfd55; + valaddr_reg:x3; val_offset:506*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 506*FLEN/8, x4, x1, x2) + +inst_286: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x3c00; + valaddr_reg:x3; val_offset:508*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 508*FLEN/8, x4, x1, x2) + +inst_287: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xbc00; + valaddr_reg:x3; val_offset:510*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 510*FLEN/8, x4, x1, x2) + +inst_288: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x0; + valaddr_reg:x3; val_offset:512*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 512*FLEN/8, x4, x1, x2) + +inst_289: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8000; + valaddr_reg:x3; val_offset:514*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 514*FLEN/8, x4, x1, x2) + +inst_290: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x1; + valaddr_reg:x3; val_offset:516*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 516*FLEN/8, x4, x1, x2) + +inst_291: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8001; + valaddr_reg:x3; val_offset:518*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 518*FLEN/8, x4, x1, x2) + +inst_292: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x2; + valaddr_reg:x3; val_offset:520*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 520*FLEN/8, x4, x1, x2) + +inst_293: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x83fe; + valaddr_reg:x3; val_offset:522*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 522*FLEN/8, x4, x1, x2) + +inst_294: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x3ff; + valaddr_reg:x3; val_offset:524*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 524*FLEN/8, x4, x1, x2) + +inst_295: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x83ff; + valaddr_reg:x3; val_offset:526*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 526*FLEN/8, x4, x1, x2) + +inst_296: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x400; + valaddr_reg:x3; val_offset:528*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 528*FLEN/8, x4, x1, x2) + +inst_297: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8400; + valaddr_reg:x3; val_offset:530*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 530*FLEN/8, x4, x1, x2) + +inst_298: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x401; + valaddr_reg:x3; val_offset:532*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 532*FLEN/8, x4, x1, x2) + +inst_299: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8455; + valaddr_reg:x3; val_offset:534*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 534*FLEN/8, x4, x1, x2) + +inst_300: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7bff; + valaddr_reg:x3; val_offset:536*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 536*FLEN/8, x4, x1, x2) + +inst_301: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xfbff; + valaddr_reg:x3; val_offset:538*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 538*FLEN/8, x4, x1, x2) + +inst_302: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7c00; + valaddr_reg:x3; val_offset:540*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 540*FLEN/8, x4, x1, x2) + +inst_303: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xfc00; + valaddr_reg:x3; val_offset:542*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 542*FLEN/8, x4, x1, x2) + +inst_304: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7e00; + valaddr_reg:x3; val_offset:544*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 544*FLEN/8, x4, x1, x2) + +inst_305: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xfe00; + valaddr_reg:x3; val_offset:546*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 546*FLEN/8, x4, x1, x2) + +inst_306: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7e01; + valaddr_reg:x3; val_offset:548*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 548*FLEN/8, x4, x1, x2) + +inst_307: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xfe55; + valaddr_reg:x3; val_offset:550*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 550*FLEN/8, x4, x1, x2) + +inst_308: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7c01; + valaddr_reg:x3; val_offset:552*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 552*FLEN/8, x4, x1, x2) + +inst_309: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xfd55; + valaddr_reg:x3; val_offset:554*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 554*FLEN/8, x4, x1, x2) + +inst_310: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x3c00; + valaddr_reg:x3; val_offset:556*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 556*FLEN/8, x4, x1, x2) + +inst_311: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xbc00; + valaddr_reg:x3; val_offset:558*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 558*FLEN/8, x4, x1, x2) + +inst_312: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x0; + valaddr_reg:x3; val_offset:560*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 560*FLEN/8, x4, x1, x2) + +inst_313: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8000; + valaddr_reg:x3; val_offset:562*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 562*FLEN/8, x4, x1, x2) + +inst_314: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x1; + valaddr_reg:x3; val_offset:564*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 564*FLEN/8, x4, x1, x2) + +inst_315: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8001; + valaddr_reg:x3; val_offset:566*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 566*FLEN/8, x4, x1, x2) + +inst_316: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x2; + valaddr_reg:x3; val_offset:568*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 568*FLEN/8, x4, x1, x2) + +inst_317: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x83fe; + valaddr_reg:x3; val_offset:570*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 570*FLEN/8, x4, x1, x2) + +inst_318: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x3ff; + valaddr_reg:x3; val_offset:572*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 572*FLEN/8, x4, x1, x2) + +inst_319: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x83ff; + valaddr_reg:x3; val_offset:574*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 574*FLEN/8, x4, x1, x2) + +inst_320: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x400; + valaddr_reg:x3; val_offset:576*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 576*FLEN/8, x4, x1, x2) + +inst_321: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8400; + valaddr_reg:x3; val_offset:578*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 578*FLEN/8, x4, x1, x2) + +inst_322: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x401; + valaddr_reg:x3; val_offset:580*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 580*FLEN/8, x4, x1, x2) + +inst_323: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8455; + valaddr_reg:x3; val_offset:582*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 582*FLEN/8, x4, x1, x2) + +inst_324: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7bff; + valaddr_reg:x3; val_offset:584*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 584*FLEN/8, x4, x1, x2) + +inst_325: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfbff; + valaddr_reg:x3; val_offset:586*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 586*FLEN/8, x4, x1, x2) + +inst_326: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7c00; + valaddr_reg:x3; val_offset:588*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 588*FLEN/8, x4, x1, x2) + +inst_327: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfc00; + valaddr_reg:x3; val_offset:590*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 590*FLEN/8, x4, x1, x2) + +inst_328: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7e00; + valaddr_reg:x3; val_offset:592*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 592*FLEN/8, x4, x1, x2) + +inst_329: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfe00; + valaddr_reg:x3; val_offset:594*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 594*FLEN/8, x4, x1, x2) + +inst_330: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7e01; + valaddr_reg:x3; val_offset:596*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 596*FLEN/8, x4, x1, x2) + +inst_331: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfe55; + valaddr_reg:x3; val_offset:598*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 598*FLEN/8, x4, x1, x2) + +inst_332: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7c01; + valaddr_reg:x3; val_offset:600*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 600*FLEN/8, x4, x1, x2) + +inst_333: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfd55; + valaddr_reg:x3; val_offset:602*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 602*FLEN/8, x4, x1, x2) + +inst_334: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x3c00; + valaddr_reg:x3; val_offset:604*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 604*FLEN/8, x4, x1, x2) + +inst_335: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xbc00; + valaddr_reg:x3; val_offset:606*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 606*FLEN/8, x4, x1, x2) + +inst_336: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x0; + valaddr_reg:x3; val_offset:608*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 608*FLEN/8, x4, x1, x2) + +inst_337: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x8000; + valaddr_reg:x3; val_offset:610*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 610*FLEN/8, x4, x1, x2) + +inst_338: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x1; + valaddr_reg:x3; val_offset:612*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 612*FLEN/8, x4, x1, x2) + +inst_339: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x8001; + valaddr_reg:x3; val_offset:614*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 614*FLEN/8, x4, x1, x2) + +inst_340: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x2; + valaddr_reg:x3; val_offset:616*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 616*FLEN/8, x4, x1, x2) + +inst_341: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x83fe; + valaddr_reg:x3; val_offset:618*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 618*FLEN/8, x4, x1, x2) + +inst_342: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x3ff; + valaddr_reg:x3; val_offset:620*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 620*FLEN/8, x4, x1, x2) + +inst_343: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x83ff; + valaddr_reg:x3; val_offset:622*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 622*FLEN/8, x4, x1, x2) + +inst_344: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x400; + valaddr_reg:x3; val_offset:624*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 624*FLEN/8, x4, x1, x2) + +inst_345: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x8400; + valaddr_reg:x3; val_offset:626*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 626*FLEN/8, x4, x1, x2) + +inst_346: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x401; + valaddr_reg:x3; val_offset:628*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 628*FLEN/8, x4, x1, x2) + +inst_347: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x8455; + valaddr_reg:x3; val_offset:630*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 630*FLEN/8, x4, x1, x2) + +inst_348: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x7bff; + valaddr_reg:x3; val_offset:632*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 632*FLEN/8, x4, x1, x2) + +inst_349: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xfbff; + valaddr_reg:x3; val_offset:634*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 634*FLEN/8, x4, x1, x2) + +inst_350: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x7c00; + valaddr_reg:x3; val_offset:636*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 636*FLEN/8, x4, x1, x2) + +inst_351: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xfc00; + valaddr_reg:x3; val_offset:638*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 638*FLEN/8, x4, x1, x2) + +inst_352: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x7e00; + valaddr_reg:x3; val_offset:640*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 640*FLEN/8, x4, x1, x2) + +inst_353: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xfe00; + valaddr_reg:x3; val_offset:642*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 642*FLEN/8, x4, x1, x2) + +inst_354: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x7e01; + valaddr_reg:x3; val_offset:644*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 644*FLEN/8, x4, x1, x2) + +inst_355: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xfe55; + valaddr_reg:x3; val_offset:646*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 646*FLEN/8, x4, x1, x2) + +inst_356: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x7c01; + valaddr_reg:x3; val_offset:648*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 648*FLEN/8, x4, x1, x2) + +inst_357: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xfd55; + valaddr_reg:x3; val_offset:650*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 650*FLEN/8, x4, x1, x2) + +inst_358: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x3c00; + valaddr_reg:x3; val_offset:652*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 652*FLEN/8, x4, x1, x2) + +inst_359: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xbc00; + valaddr_reg:x3; val_offset:654*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 654*FLEN/8, x4, x1, x2) + +inst_360: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x0; + valaddr_reg:x3; val_offset:656*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 656*FLEN/8, x4, x1, x2) + +inst_361: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x8000; + valaddr_reg:x3; val_offset:658*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 658*FLEN/8, x4, x1, x2) + +inst_362: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x1; + valaddr_reg:x3; val_offset:660*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 660*FLEN/8, x4, x1, x2) + +inst_363: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x8001; + valaddr_reg:x3; val_offset:662*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 662*FLEN/8, x4, x1, x2) + +inst_364: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x2; + valaddr_reg:x3; val_offset:664*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 664*FLEN/8, x4, x1, x2) + +inst_365: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x83fe; + valaddr_reg:x3; val_offset:666*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 666*FLEN/8, x4, x1, x2) + +inst_366: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x3ff; + valaddr_reg:x3; val_offset:668*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 668*FLEN/8, x4, x1, x2) + +inst_367: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x83ff; + valaddr_reg:x3; val_offset:670*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 670*FLEN/8, x4, x1, x2) + +inst_368: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x400; + valaddr_reg:x3; val_offset:672*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 672*FLEN/8, x4, x1, x2) + +inst_369: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x8400; + valaddr_reg:x3; val_offset:674*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 674*FLEN/8, x4, x1, x2) + +inst_370: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x401; + valaddr_reg:x3; val_offset:676*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 676*FLEN/8, x4, x1, x2) + +inst_371: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x8455; + valaddr_reg:x3; val_offset:678*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 678*FLEN/8, x4, x1, x2) + +inst_372: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x7bff; + valaddr_reg:x3; val_offset:680*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 680*FLEN/8, x4, x1, x2) + +inst_373: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xfbff; + valaddr_reg:x3; val_offset:682*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 682*FLEN/8, x4, x1, x2) + +inst_374: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x7c00; + valaddr_reg:x3; val_offset:684*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 684*FLEN/8, x4, x1, x2) + +inst_375: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xfc00; + valaddr_reg:x3; val_offset:686*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 686*FLEN/8, x4, x1, x2) + +inst_376: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x7e00; + valaddr_reg:x3; val_offset:688*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 688*FLEN/8, x4, x1, x2) + +inst_377: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xfe00; + valaddr_reg:x3; val_offset:690*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 690*FLEN/8, x4, x1, x2) + +inst_378: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x7e01; + valaddr_reg:x3; val_offset:692*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 692*FLEN/8, x4, x1, x2) + +inst_379: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xfe55; + valaddr_reg:x3; val_offset:694*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 694*FLEN/8, x4, x1, x2) + +inst_380: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x7c01; + valaddr_reg:x3; val_offset:696*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 696*FLEN/8, x4, x1, x2) + +inst_381: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xfd55; + valaddr_reg:x3; val_offset:698*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 698*FLEN/8, x4, x1, x2) + +inst_382: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x3c00; + valaddr_reg:x3; val_offset:700*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 700*FLEN/8, x4, x1, x2) + +inst_383: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xbc00; + valaddr_reg:x3; val_offset:702*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 702*FLEN/8, x4, x1, x2) + +inst_384: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x0; + valaddr_reg:x3; val_offset:704*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 704*FLEN/8, x4, x1, x2) + +inst_385: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x8000; + valaddr_reg:x3; val_offset:706*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 706*FLEN/8, x4, x1, x2) + +inst_386: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x1; + valaddr_reg:x3; val_offset:708*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 708*FLEN/8, x4, x1, x2) + +inst_387: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x8001; + valaddr_reg:x3; val_offset:710*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 710*FLEN/8, x4, x1, x2) + +inst_388: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x2; + valaddr_reg:x3; val_offset:712*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 712*FLEN/8, x4, x1, x2) + +inst_389: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x83fe; + valaddr_reg:x3; val_offset:714*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 714*FLEN/8, x4, x1, x2) + +inst_390: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x3ff; + valaddr_reg:x3; val_offset:716*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 716*FLEN/8, x4, x1, x2) + +inst_391: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x83ff; + valaddr_reg:x3; val_offset:718*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 718*FLEN/8, x4, x1, x2) + +inst_392: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x400; + valaddr_reg:x3; val_offset:720*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 720*FLEN/8, x4, x1, x2) + +inst_393: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x8400; + valaddr_reg:x3; val_offset:722*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 722*FLEN/8, x4, x1, x2) + +inst_394: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x401; + valaddr_reg:x3; val_offset:724*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 724*FLEN/8, x4, x1, x2) + +inst_395: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x8455; + valaddr_reg:x3; val_offset:726*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 726*FLEN/8, x4, x1, x2) + +inst_396: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x7bff; + valaddr_reg:x3; val_offset:728*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 728*FLEN/8, x4, x1, x2) + +inst_397: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xfbff; + valaddr_reg:x3; val_offset:730*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 730*FLEN/8, x4, x1, x2) + +inst_398: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x7c00; + valaddr_reg:x3; val_offset:732*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 732*FLEN/8, x4, x1, x2) + +inst_399: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xfc00; + valaddr_reg:x3; val_offset:734*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 734*FLEN/8, x4, x1, x2) + +inst_400: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x7e00; + valaddr_reg:x3; val_offset:736*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 736*FLEN/8, x4, x1, x2) + +inst_401: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xfe00; + valaddr_reg:x3; val_offset:738*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 738*FLEN/8, x4, x1, x2) + +inst_402: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x7e01; + valaddr_reg:x3; val_offset:740*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 740*FLEN/8, x4, x1, x2) + +inst_403: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xfe55; + valaddr_reg:x3; val_offset:742*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 742*FLEN/8, x4, x1, x2) + +inst_404: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x7c01; + valaddr_reg:x3; val_offset:744*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 744*FLEN/8, x4, x1, x2) + +inst_405: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xfd55; + valaddr_reg:x3; val_offset:746*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 746*FLEN/8, x4, x1, x2) + +inst_406: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x3c00; + valaddr_reg:x3; val_offset:748*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 748*FLEN/8, x4, x1, x2) + +inst_407: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xbc00; + valaddr_reg:x3; val_offset:750*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 750*FLEN/8, x4, x1, x2) + +inst_408: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x0; + valaddr_reg:x3; val_offset:752*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 752*FLEN/8, x4, x1, x2) + +inst_409: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x8000; + valaddr_reg:x3; val_offset:754*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 754*FLEN/8, x4, x1, x2) + +inst_410: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x1; + valaddr_reg:x3; val_offset:756*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 756*FLEN/8, x4, x1, x2) + +inst_411: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x8001; + valaddr_reg:x3; val_offset:758*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 758*FLEN/8, x4, x1, x2) + +inst_412: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x2; + valaddr_reg:x3; val_offset:760*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 760*FLEN/8, x4, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_3) + +inst_413: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x83fe; + valaddr_reg:x3; val_offset:762*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 762*FLEN/8, x4, x1, x2) + +inst_414: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x3ff; + valaddr_reg:x3; val_offset:764*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 764*FLEN/8, x4, x1, x2) + +inst_415: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x83ff; + valaddr_reg:x3; val_offset:766*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 766*FLEN/8, x4, x1, x2) + +inst_416: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x400; + valaddr_reg:x3; val_offset:768*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 768*FLEN/8, x4, x1, x2) + +inst_417: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x8400; + valaddr_reg:x3; val_offset:770*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 770*FLEN/8, x4, x1, x2) + +inst_418: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x401; + valaddr_reg:x3; val_offset:772*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 772*FLEN/8, x4, x1, x2) + +inst_419: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x8455; + valaddr_reg:x3; val_offset:774*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 774*FLEN/8, x4, x1, x2) + +inst_420: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x7bff; + valaddr_reg:x3; val_offset:776*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 776*FLEN/8, x4, x1, x2) + +inst_421: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xfbff; + valaddr_reg:x3; val_offset:778*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 778*FLEN/8, x4, x1, x2) + +inst_422: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x7c00; + valaddr_reg:x3; val_offset:780*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 780*FLEN/8, x4, x1, x2) + +inst_423: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xfc00; + valaddr_reg:x3; val_offset:782*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 782*FLEN/8, x4, x1, x2) + +inst_424: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x7e00; + valaddr_reg:x3; val_offset:784*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 784*FLEN/8, x4, x1, x2) + +inst_425: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xfe00; + valaddr_reg:x3; val_offset:786*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 786*FLEN/8, x4, x1, x2) + +inst_426: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x7e01; + valaddr_reg:x3; val_offset:788*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 788*FLEN/8, x4, x1, x2) + +inst_427: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xfe55; + valaddr_reg:x3; val_offset:790*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 790*FLEN/8, x4, x1, x2) + +inst_428: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x7c01; + valaddr_reg:x3; val_offset:792*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 792*FLEN/8, x4, x1, x2) + +inst_429: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xfd55; + valaddr_reg:x3; val_offset:794*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 794*FLEN/8, x4, x1, x2) + +inst_430: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x3c00; + valaddr_reg:x3; val_offset:796*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 796*FLEN/8, x4, x1, x2) + +inst_431: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xbc00; + valaddr_reg:x3; val_offset:798*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 798*FLEN/8, x4, x1, x2) + +inst_432: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x0; + valaddr_reg:x3; val_offset:800*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 800*FLEN/8, x4, x1, x2) + +inst_433: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x8000; + valaddr_reg:x3; val_offset:802*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 802*FLEN/8, x4, x1, x2) + +inst_434: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x1; + valaddr_reg:x3; val_offset:804*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 804*FLEN/8, x4, x1, x2) + +inst_435: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x8001; + valaddr_reg:x3; val_offset:806*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 806*FLEN/8, x4, x1, x2) + +inst_436: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x2; + valaddr_reg:x3; val_offset:808*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 808*FLEN/8, x4, x1, x2) + +inst_437: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x83fe; + valaddr_reg:x3; val_offset:810*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 810*FLEN/8, x4, x1, x2) + +inst_438: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x3ff; + valaddr_reg:x3; val_offset:812*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 812*FLEN/8, x4, x1, x2) + +inst_439: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x83ff; + valaddr_reg:x3; val_offset:814*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 814*FLEN/8, x4, x1, x2) + +inst_440: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x400; + valaddr_reg:x3; val_offset:816*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 816*FLEN/8, x4, x1, x2) + +inst_441: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x8400; + valaddr_reg:x3; val_offset:818*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 818*FLEN/8, x4, x1, x2) + +inst_442: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x401; + valaddr_reg:x3; val_offset:820*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 820*FLEN/8, x4, x1, x2) + +inst_443: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x8455; + valaddr_reg:x3; val_offset:822*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 822*FLEN/8, x4, x1, x2) + +inst_444: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x7bff; + valaddr_reg:x3; val_offset:824*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 824*FLEN/8, x4, x1, x2) + +inst_445: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xfbff; + valaddr_reg:x3; val_offset:826*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 826*FLEN/8, x4, x1, x2) + +inst_446: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x7c00; + valaddr_reg:x3; val_offset:828*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 828*FLEN/8, x4, x1, x2) + +inst_447: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xfc00; + valaddr_reg:x3; val_offset:830*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 830*FLEN/8, x4, x1, x2) + +inst_448: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x7e00; + valaddr_reg:x3; val_offset:832*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 832*FLEN/8, x4, x1, x2) + +inst_449: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xfe00; + valaddr_reg:x3; val_offset:834*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 834*FLEN/8, x4, x1, x2) + +inst_450: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x7e01; + valaddr_reg:x3; val_offset:836*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 836*FLEN/8, x4, x1, x2) + +inst_451: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xfe55; + valaddr_reg:x3; val_offset:838*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 838*FLEN/8, x4, x1, x2) + +inst_452: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x7c01; + valaddr_reg:x3; val_offset:840*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 840*FLEN/8, x4, x1, x2) + +inst_453: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xfd55; + valaddr_reg:x3; val_offset:842*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 842*FLEN/8, x4, x1, x2) + +inst_454: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x3c00; + valaddr_reg:x3; val_offset:844*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 844*FLEN/8, x4, x1, x2) + +inst_455: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xbc00; + valaddr_reg:x3; val_offset:846*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 846*FLEN/8, x4, x1, x2) + +inst_456: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x0; + valaddr_reg:x3; val_offset:848*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 848*FLEN/8, x4, x1, x2) + +inst_457: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x8000; + valaddr_reg:x3; val_offset:850*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 850*FLEN/8, x4, x1, x2) + +inst_458: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x1; + valaddr_reg:x3; val_offset:852*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 852*FLEN/8, x4, x1, x2) + +inst_459: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x8001; + valaddr_reg:x3; val_offset:854*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 854*FLEN/8, x4, x1, x2) + +inst_460: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x2; + valaddr_reg:x3; val_offset:856*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 856*FLEN/8, x4, x1, x2) + +inst_461: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x83fe; + valaddr_reg:x3; val_offset:858*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 858*FLEN/8, x4, x1, x2) + +inst_462: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x3ff; + valaddr_reg:x3; val_offset:860*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 860*FLEN/8, x4, x1, x2) + +inst_463: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x83ff; + valaddr_reg:x3; val_offset:862*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 862*FLEN/8, x4, x1, x2) + +inst_464: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x400; + valaddr_reg:x3; val_offset:864*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 864*FLEN/8, x4, x1, x2) + +inst_465: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x8400; + valaddr_reg:x3; val_offset:866*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 866*FLEN/8, x4, x1, x2) + +inst_466: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x401; + valaddr_reg:x3; val_offset:868*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 868*FLEN/8, x4, x1, x2) + +inst_467: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x8455; + valaddr_reg:x3; val_offset:870*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 870*FLEN/8, x4, x1, x2) + +inst_468: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x7bff; + valaddr_reg:x3; val_offset:872*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 872*FLEN/8, x4, x1, x2) + +inst_469: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xfbff; + valaddr_reg:x3; val_offset:874*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 874*FLEN/8, x4, x1, x2) + +inst_470: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x7c00; + valaddr_reg:x3; val_offset:876*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 876*FLEN/8, x4, x1, x2) + +inst_471: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xfc00; + valaddr_reg:x3; val_offset:878*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 878*FLEN/8, x4, x1, x2) + +inst_472: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x7e00; + valaddr_reg:x3; val_offset:880*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 880*FLEN/8, x4, x1, x2) + +inst_473: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xfe00; + valaddr_reg:x3; val_offset:882*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 882*FLEN/8, x4, x1, x2) + +inst_474: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x7e01; + valaddr_reg:x3; val_offset:884*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 884*FLEN/8, x4, x1, x2) + +inst_475: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xfe55; + valaddr_reg:x3; val_offset:886*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 886*FLEN/8, x4, x1, x2) + +inst_476: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x7c01; + valaddr_reg:x3; val_offset:888*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 888*FLEN/8, x4, x1, x2) + +inst_477: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xfd55; + valaddr_reg:x3; val_offset:890*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 890*FLEN/8, x4, x1, x2) + +inst_478: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x3c00; + valaddr_reg:x3; val_offset:892*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 892*FLEN/8, x4, x1, x2) + +inst_479: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xbc00; + valaddr_reg:x3; val_offset:894*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 894*FLEN/8, x4, x1, x2) + +inst_480: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x0; + valaddr_reg:x3; val_offset:896*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 896*FLEN/8, x4, x1, x2) + +inst_481: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x8000; + valaddr_reg:x3; val_offset:898*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 898*FLEN/8, x4, x1, x2) + +inst_482: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x1; + valaddr_reg:x3; val_offset:900*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 900*FLEN/8, x4, x1, x2) + +inst_483: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x8001; + valaddr_reg:x3; val_offset:902*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 902*FLEN/8, x4, x1, x2) + +inst_484: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x2; + valaddr_reg:x3; val_offset:904*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 904*FLEN/8, x4, x1, x2) + +inst_485: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x83fe; + valaddr_reg:x3; val_offset:906*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 906*FLEN/8, x4, x1, x2) + +inst_486: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x3ff; + valaddr_reg:x3; val_offset:908*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 908*FLEN/8, x4, x1, x2) + +inst_487: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x83ff; + valaddr_reg:x3; val_offset:910*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 910*FLEN/8, x4, x1, x2) + +inst_488: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x400; + valaddr_reg:x3; val_offset:912*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 912*FLEN/8, x4, x1, x2) + +inst_489: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x8400; + valaddr_reg:x3; val_offset:914*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 914*FLEN/8, x4, x1, x2) + +inst_490: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x401; + valaddr_reg:x3; val_offset:916*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 916*FLEN/8, x4, x1, x2) + +inst_491: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x8455; + valaddr_reg:x3; val_offset:918*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 918*FLEN/8, x4, x1, x2) + +inst_492: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x7bff; + valaddr_reg:x3; val_offset:920*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 920*FLEN/8, x4, x1, x2) + +inst_493: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xfbff; + valaddr_reg:x3; val_offset:922*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 922*FLEN/8, x4, x1, x2) + +inst_494: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x7c00; + valaddr_reg:x3; val_offset:924*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 924*FLEN/8, x4, x1, x2) + +inst_495: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xfc00; + valaddr_reg:x3; val_offset:926*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 926*FLEN/8, x4, x1, x2) + +inst_496: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x7e00; + valaddr_reg:x3; val_offset:928*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 928*FLEN/8, x4, x1, x2) + +inst_497: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xfe00; + valaddr_reg:x3; val_offset:930*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 930*FLEN/8, x4, x1, x2) + +inst_498: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x7e01; + valaddr_reg:x3; val_offset:932*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 932*FLEN/8, x4, x1, x2) + +inst_499: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xfe55; + valaddr_reg:x3; val_offset:934*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 934*FLEN/8, x4, x1, x2) + +inst_500: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x7c01; + valaddr_reg:x3; val_offset:936*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 936*FLEN/8, x4, x1, x2) + +inst_501: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xfd55; + valaddr_reg:x3; val_offset:938*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 938*FLEN/8, x4, x1, x2) + +inst_502: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x3c00; + valaddr_reg:x3; val_offset:940*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 940*FLEN/8, x4, x1, x2) + +inst_503: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xbc00; + valaddr_reg:x3; val_offset:942*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 942*FLEN/8, x4, x1, x2) + +inst_504: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x0; + valaddr_reg:x3; val_offset:944*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 944*FLEN/8, x4, x1, x2) + +inst_505: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x8000; + valaddr_reg:x3; val_offset:946*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 946*FLEN/8, x4, x1, x2) + +inst_506: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x1; + valaddr_reg:x3; val_offset:948*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 948*FLEN/8, x4, x1, x2) + +inst_507: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x8001; + valaddr_reg:x3; val_offset:950*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 950*FLEN/8, x4, x1, x2) + +inst_508: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x2; + valaddr_reg:x3; val_offset:952*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 952*FLEN/8, x4, x1, x2) + +inst_509: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x83fe; + valaddr_reg:x3; val_offset:954*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 954*FLEN/8, x4, x1, x2) + +inst_510: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x3ff; + valaddr_reg:x3; val_offset:956*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 956*FLEN/8, x4, x1, x2) + +inst_511: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x83ff; + valaddr_reg:x3; val_offset:958*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 958*FLEN/8, x4, x1, x2) + +inst_512: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x400; + valaddr_reg:x3; val_offset:960*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 960*FLEN/8, x4, x1, x2) + +inst_513: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x8400; + valaddr_reg:x3; val_offset:962*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 962*FLEN/8, x4, x1, x2) + +inst_514: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x401; + valaddr_reg:x3; val_offset:964*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 964*FLEN/8, x4, x1, x2) + +inst_515: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x8455; + valaddr_reg:x3; val_offset:966*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 966*FLEN/8, x4, x1, x2) + +inst_516: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x7bff; + valaddr_reg:x3; val_offset:968*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 968*FLEN/8, x4, x1, x2) + +inst_517: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xfbff; + valaddr_reg:x3; val_offset:970*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 970*FLEN/8, x4, x1, x2) + +inst_518: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x7c00; + valaddr_reg:x3; val_offset:972*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 972*FLEN/8, x4, x1, x2) + +inst_519: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xfc00; + valaddr_reg:x3; val_offset:974*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 974*FLEN/8, x4, x1, x2) + +inst_520: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x7e00; + valaddr_reg:x3; val_offset:976*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 976*FLEN/8, x4, x1, x2) + +inst_521: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xfe00; + valaddr_reg:x3; val_offset:978*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 978*FLEN/8, x4, x1, x2) + +inst_522: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x7e01; + valaddr_reg:x3; val_offset:980*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 980*FLEN/8, x4, x1, x2) + +inst_523: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xfe55; + valaddr_reg:x3; val_offset:982*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 982*FLEN/8, x4, x1, x2) + +inst_524: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x7c01; + valaddr_reg:x3; val_offset:984*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 984*FLEN/8, x4, x1, x2) + +inst_525: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xfd55; + valaddr_reg:x3; val_offset:986*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 986*FLEN/8, x4, x1, x2) + +inst_526: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x3c00; + valaddr_reg:x3; val_offset:988*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 988*FLEN/8, x4, x1, x2) + +inst_527: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xbc00; + valaddr_reg:x3; val_offset:990*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 990*FLEN/8, x4, x1, x2) + +inst_528: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x0; + valaddr_reg:x3; val_offset:992*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 992*FLEN/8, x4, x1, x2) + +inst_529: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x8000; + valaddr_reg:x3; val_offset:994*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 994*FLEN/8, x4, x1, x2) + +inst_530: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x1; + valaddr_reg:x3; val_offset:996*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 996*FLEN/8, x4, x1, x2) + +inst_531: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x8001; + valaddr_reg:x3; val_offset:998*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 998*FLEN/8, x4, x1, x2) + +inst_532: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2; + valaddr_reg:x3; val_offset:1000*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1000*FLEN/8, x4, x1, x2) + +inst_533: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x83fe; + valaddr_reg:x3; val_offset:1002*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1002*FLEN/8, x4, x1, x2) + +inst_534: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3ff; + valaddr_reg:x3; val_offset:1004*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1004*FLEN/8, x4, x1, x2) + +inst_535: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x83ff; + valaddr_reg:x3; val_offset:1006*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1006*FLEN/8, x4, x1, x2) + +inst_536: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x400; + valaddr_reg:x3; val_offset:1008*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1008*FLEN/8, x4, x1, x2) + +inst_537: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x8400; + valaddr_reg:x3; val_offset:1010*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1010*FLEN/8, x4, x1, x2) + +inst_538: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x401; + valaddr_reg:x3; val_offset:1012*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1012*FLEN/8, x4, x1, x2) + +inst_539: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x8455; + valaddr_reg:x3; val_offset:1014*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1014*FLEN/8, x4, x1, x2) + +inst_540: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7bff; + valaddr_reg:x3; val_offset:1016*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1016*FLEN/8, x4, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_4) + +inst_541: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xfbff; + valaddr_reg:x3; val_offset:1018*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1018*FLEN/8, x4, x1, x2) + +inst_542: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7c00; + valaddr_reg:x3; val_offset:1020*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1020*FLEN/8, x4, x1, x2) + +inst_543: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xfc00; + valaddr_reg:x3; val_offset:1022*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1022*FLEN/8, x4, x1, x2) + +inst_544: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7e00; + valaddr_reg:x3; val_offset:1024*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1024*FLEN/8, x4, x1, x2) + +inst_545: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xfe00; + valaddr_reg:x3; val_offset:1026*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1026*FLEN/8, x4, x1, x2) + +inst_546: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7e01; + valaddr_reg:x3; val_offset:1028*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1028*FLEN/8, x4, x1, x2) + +inst_547: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xfe55; + valaddr_reg:x3; val_offset:1030*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1030*FLEN/8, x4, x1, x2) + +inst_548: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7c01; + valaddr_reg:x3; val_offset:1032*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1032*FLEN/8, x4, x1, x2) + +inst_549: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xfd55; + valaddr_reg:x3; val_offset:1034*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1034*FLEN/8, x4, x1, x2) + +inst_550: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3c00; + valaddr_reg:x3; val_offset:1036*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1036*FLEN/8, x4, x1, x2) + +inst_551: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xbc00; + valaddr_reg:x3; val_offset:1038*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1038*FLEN/8, x4, x1, x2) + +inst_552: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x0; + valaddr_reg:x3; val_offset:1040*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1040*FLEN/8, x4, x1, x2) + +inst_553: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x8000; + valaddr_reg:x3; val_offset:1042*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1042*FLEN/8, x4, x1, x2) + +inst_554: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x1; + valaddr_reg:x3; val_offset:1044*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1044*FLEN/8, x4, x1, x2) + +inst_555: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x8001; + valaddr_reg:x3; val_offset:1046*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1046*FLEN/8, x4, x1, x2) + +inst_556: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x2; + valaddr_reg:x3; val_offset:1048*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1048*FLEN/8, x4, x1, x2) + +inst_557: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x83fe; + valaddr_reg:x3; val_offset:1050*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1050*FLEN/8, x4, x1, x2) + +inst_558: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x3ff; + valaddr_reg:x3; val_offset:1052*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1052*FLEN/8, x4, x1, x2) + +inst_559: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x83ff; + valaddr_reg:x3; val_offset:1054*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1054*FLEN/8, x4, x1, x2) + +inst_560: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x400; + valaddr_reg:x3; val_offset:1056*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1056*FLEN/8, x4, x1, x2) + +inst_561: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x8400; + valaddr_reg:x3; val_offset:1058*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1058*FLEN/8, x4, x1, x2) + +inst_562: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x401; + valaddr_reg:x3; val_offset:1060*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1060*FLEN/8, x4, x1, x2) + +inst_563: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x8455; + valaddr_reg:x3; val_offset:1062*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1062*FLEN/8, x4, x1, x2) + +inst_564: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x7bff; + valaddr_reg:x3; val_offset:1064*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1064*FLEN/8, x4, x1, x2) + +inst_565: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xfbff; + valaddr_reg:x3; val_offset:1066*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1066*FLEN/8, x4, x1, x2) + +inst_566: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x7c00; + valaddr_reg:x3; val_offset:1068*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1068*FLEN/8, x4, x1, x2) + +inst_567: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xfc00; + valaddr_reg:x3; val_offset:1070*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1070*FLEN/8, x4, x1, x2) + +inst_568: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x7e00; + valaddr_reg:x3; val_offset:1072*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1072*FLEN/8, x4, x1, x2) + +inst_569: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xfe00; + valaddr_reg:x3; val_offset:1074*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1074*FLEN/8, x4, x1, x2) + +inst_570: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x7e01; + valaddr_reg:x3; val_offset:1076*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1076*FLEN/8, x4, x1, x2) + +inst_571: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xfe55; + valaddr_reg:x3; val_offset:1078*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1078*FLEN/8, x4, x1, x2) + +inst_572: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x7c01; + valaddr_reg:x3; val_offset:1080*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1080*FLEN/8, x4, x1, x2) + +inst_573: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xfd55; + valaddr_reg:x3; val_offset:1082*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1082*FLEN/8, x4, x1, x2) + +inst_574: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x3c00; + valaddr_reg:x3; val_offset:1084*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1084*FLEN/8, x4, x1, x2) + +inst_575: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbc00; + valaddr_reg:x3; val_offset:1086*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1086*FLEN/8, x4, x1, x2) + +inst_576: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x8000; + valaddr_reg:x3; val_offset:1088*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1088*FLEN/8, x4, x1, x2) + +inst_577: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x1; + valaddr_reg:x3; val_offset:1090*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1090*FLEN/8, x4, x1, x2) + +inst_578: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x400; + valaddr_reg:x3; val_offset:1092*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1092*FLEN/8, x4, x1, x2) + +inst_579: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xbc00; + valaddr_reg:x3; val_offset:1094*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1094*FLEN/8, x4, x1, x2) + +inst_580: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8000; + valaddr_reg:x3; val_offset:1096*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1096*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(2,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(1023,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(1024,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(1025,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(33877,16,FLEN) +test_dataset_1: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31744,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32256,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32257,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31745,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64853,16,FLEN) +test_dataset_2: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(15360,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(2,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1023,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33791,16,FLEN) +test_dataset_3: +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(33792,16,FLEN) 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+NAN_BOXED(65109,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32768,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x4_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x4_1: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x11_0: + .fill 30*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_0: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_2: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_3: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_4: + .fill 80*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fdiv_b2-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fdiv_b2-01.S new file mode 100644 index 000000000..42904724a --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fdiv_b2-01.S @@ -0,0 +1,1324 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 05:22:24 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fdiv.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fdiv.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fdiv_b2 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fdiv_b2) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x5,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd != rs2, rs1==x22, rs2==x29, rd==x22,fs1 == 0 and fe1 == 0x00 and fm1 == 0x01f and fs2 == 0 and fe2 == 0x13 and fm2 == 0x3b2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x22; op2:x29; dest:x22; op1val:0x1f; op2val:0x4fb2; + valaddr_reg:x5; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP(fdiv.h, x22, x22, x29, dyn, 0, 0, x5, 0*FLEN/8, x15, x1, x13) + +inst_1: +// rs1 == rs2 != rd, rs1==x16, rs2==x16, rd==x10,fs1 == 0 and fe1 == 0x00 and fm1 == 0x046 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x060 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x16; op2:x16; dest:x10; op1val:0x46; op2val:0x46; + valaddr_reg:x5; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP(fdiv.h, x10, x16, x16, dyn, 0, 0, x5, 2*FLEN/8, x15, x1, x13) + +inst_2: +// rs1 == rs2 == rd, rs1==x0, rs2==x0, rd==x0,fs1 == 0 and fe1 == 0x00 and fm1 == 0x030 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x0; op2:x0; dest:x0; op1val:0x0; op2val:0x0; + valaddr_reg:x5; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP(fdiv.h, x0, x0, x0, dyn, 0, 0, x5, 4*FLEN/8, x15, x1, x13) + +inst_3: +// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==x26, rs2==x8, rd==x11,fs1 == 0 and fe1 == 0x00 and fm1 == 0x03d and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3a0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x26; op2:x8; dest:x11; op1val:0x3d; op2val:0x47a0; + valaddr_reg:x5; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP(fdiv.h, x11, x26, x8, dyn, 0, 0, x5, 6*FLEN/8, x15, x1, x13) + +inst_4: +// rs2 == rd != rs1, rs1==x20, rs2==x23, rd==x23,fs1 == 0 and fe1 == 0x00 and fm1 == 0x04b and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0b0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x20; op2:x23; dest:x23; op1val:0x4b; op2val:0x44b0; + valaddr_reg:x5; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP(fdiv.h, x23, x20, x23, dyn, 0, 0, x5, 8*FLEN/8, x15, x1, x13) + +inst_5: +// rs1==x25, rs2==x7, rd==x12,fs1 == 0 and fe1 == 0x00 and fm1 == 0x04e and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x25; op2:x7; dest:x12; op1val:0x4e; op2val:0x40e0; + valaddr_reg:x5; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP(fdiv.h, x12, x25, x7, dyn, 0, 0, x5, 10*FLEN/8, x15, x1, x13) + +inst_6: +// rs1==x10, rs2==x14, rd==x28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x03d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3a0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x10; op2:x14; dest:x28; op1val:0x3d; op2val:0x3ba0; + valaddr_reg:x5; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP(fdiv.h, x28, x10, x14, dyn, 0, 0, x5, 12*FLEN/8, x15, x1, x13) + +inst_7: +// rs1==x28, rs2==x10, rd==x25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x047 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x070 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x28; op2:x10; dest:x25; op1val:0x47; op2val:0x3870; + valaddr_reg:x5; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP(fdiv.h, x25, x28, x10, dyn, 0, 0, x5, 14*FLEN/8, x15, x1, x13) + +inst_8: +// rs1==x3, rs2==x17, rd==x24,fs1 == 0 and fe1 == 0x00 and fm1 == 0x019 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x240 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x3; op2:x17; dest:x24; op1val:0x19; op2val:0x2e40; + valaddr_reg:x5; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP(fdiv.h, x24, x3, x17, dyn, 0, 0, x5, 16*FLEN/8, x15, x1, x13) + +inst_9: +// rs1==x30, rs2==x26, rd==x17,fs1 == 0 and fe1 == 0x00 and fm1 == 0x03d and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3a0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x26; dest:x17; op1val:0x3d; op2val:0x2fa0; + valaddr_reg:x5; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP(fdiv.h, x17, x30, x26, dyn, 0, 0, x5, 18*FLEN/8, x15, x1, x13) + +inst_10: +// rs1==x17, rs2==x28, rd==x6,fs1 == 0 and fe1 == 0x00 and fm1 == 0x047 and fs2 == 1 and fe2 == 0x15 and fm2 == 0x068 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x17; op2:x28; dest:x6; op1val:0x47; op2val:0xd468; + valaddr_reg:x5; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP(fdiv.h, x6, x17, x28, dyn, 0, 0, x5, 20*FLEN/8, x15, x1, x13) + +inst_11: +// rs1==x14, rs2==x25, rd==x2,fs1 == 0 and fe1 == 0x00 and fm1 == 0x033 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x260 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x14; op2:x25; dest:x2; op1val:0x33; op2val:0xce60; + valaddr_reg:x5; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP(fdiv.h, x2, x14, x25, dyn, 0, 0, x5, 22*FLEN/8, x15, x1, x13) + +inst_12: +// rs1==x27, rs2==x3, rd==x4,fs1 == 0 and fe1 == 0x00 and fm1 == 0x014 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x27; op2:x3; dest:x4; op1val:0x14; op2val:0xc500; + valaddr_reg:x5; val_offset:24*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP(fdiv.h, x4, x27, x3, dyn, 0, 0, x5, 24*FLEN/8, x15, x1, x13) + +inst_13: +// rs1==x9, rs2==x27, rd==x19,fs1 == 0 and fe1 == 0x00 and fm1 == 0x052 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x120 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x9; op2:x27; dest:x19; op1val:0x52; op2val:0xc920; + valaddr_reg:x5; val_offset:26*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP(fdiv.h, x19, x9, x27, dyn, 0, 0, x5, 26*FLEN/8, x15, x1, x13) +RVTEST_VALBASEUPD(x14,test_dataset_1) + +inst_14: +// rs1==x2, rs2==x4, rd==x20,fs1 == 0 and fe1 == 0x00 and fm1 == 0x043 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x030 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x2; op2:x4; dest:x20; op1val:0x43; op2val:0xc430; + valaddr_reg:x14; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP(fdiv.h, x20, x2, x4, dyn, 0, 0, x14, 0*FLEN/8, x17, x1, x13) + +inst_15: +// rs1==x5, rs2==x6, rd==x29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x05f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x5; op2:x6; dest:x29; op1val:0x5f; op2val:0xc1f0; + valaddr_reg:x14; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP(fdiv.h, x29, x5, x6, dyn, 0, 0, x14, 2*FLEN/8, x17, x1, x13) + +inst_16: +// rs1==x18, rs2==x9, rd==x31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x056 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x160 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x18; op2:x9; dest:x31; op1val:0x56; op2val:0xbd60; + valaddr_reg:x14; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x16 +*/ +TEST_FPRR_OP(fdiv.h, x31, x18, x9, dyn, 0, 0, x14, 4*FLEN/8, x17, x1, x16) +RVTEST_SIGBASE(x10,signature_x10_0) + +inst_17: +// rs1==x31, rs2==x2, rd==x27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x015 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x140 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x31; op2:x2; dest:x27; op1val:0x15; op2val:0xb140; + valaddr_reg:x14; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x16 +*/ +TEST_FPRR_OP(fdiv.h, x27, x31, x2, dyn, 0, 0, x14, 6*FLEN/8, x17, x10, x16) + +inst_18: +// rs1==x12, rs2==x13, rd==x1,fs1 == 0 and fe1 == 0x00 and fm1 == 0x04c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x12; op2:x13; dest:x1; op1val:0x4c; op2val:0xb4c0; + valaddr_reg:x14; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x16 +*/ +TEST_FPRR_OP(fdiv.h, x1, x12, x13, dyn, 0, 0, x14, 8*FLEN/8, x17, x10, x16) + +inst_19: +// rs1==x7, rs2==x22, rd==x15,fs1 == 0 and fe1 == 0x00 and fm1 == 0x027 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x0e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x7; op2:x22; dest:x15; op1val:0x27; op2val:0xace0; + valaddr_reg:x14; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x16 +*/ +TEST_FPRR_OP(fdiv.h, x15, x7, x22, dyn, 0, 0, x14, 10*FLEN/8, x17, x10, x16) + +inst_20: +// rs1==x29, rs2==x1, rd==x8,fs1 == 0 and fe1 == 0x0f and fm1 == 0x023 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x021 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x29; op2:x1; dest:x8; op1val:0x3c23; op2val:0x3c21; + valaddr_reg:x14; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x16 +*/ +TEST_FPRR_OP(fdiv.h, x8, x29, x1, dyn, 0, 0, x14, 12*FLEN/8, x17, x10, x16) + +inst_21: +// rs1==x19, rs2==x31, rd==x30,fs1 == 0 and fe1 == 0x0f and fm1 == 0x04d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x04a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x19; op2:x31; dest:x30; op1val:0x3c4d; op2val:0x3c4a; + valaddr_reg:x14; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x16 +*/ +TEST_FPRR_OP(fdiv.h, x30, x19, x31, dyn, 0, 0, x14, 14*FLEN/8, x17, x10, x16) + +inst_22: +// rs1==x21, rs2==x19, rd==x13,fs1 == 0 and fe1 == 0x0f and fm1 == 0x032 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x02d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x21; op2:x19; dest:x13; op1val:0x3c32; op2val:0x3c2d; + valaddr_reg:x14; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x16 +*/ +TEST_FPRR_OP(fdiv.h, x13, x21, x19, dyn, 0, 0, x14, 16*FLEN/8, x17, x10, x16) + +inst_23: +// rs1==x15, rs2==x12, rd==x7,fs1 == 0 and fe1 == 0x0f and fm1 == 0x037 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x02e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x15; op2:x12; dest:x7; op1val:0x3c37; op2val:0x3c2e; + valaddr_reg:x14; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x16 +*/ +TEST_FPRR_OP(fdiv.h, x7, x15, x12, dyn, 0, 0, x14, 18*FLEN/8, x17, x10, x16) + +inst_24: +// rs1==x4, rs2==x11, rd==x3,fs1 == 0 and fe1 == 0x0f and fm1 == 0x05e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x04c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x4; op2:x11; dest:x3; op1val:0x3c5e; op2val:0x3c4c; + valaddr_reg:x14; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x16 +*/ +TEST_FPRR_OP(fdiv.h, x3, x4, x11, dyn, 0, 0, x14, 20*FLEN/8, x17, x10, x16) + +inst_25: +// rs1==x11, rs2==x5, rd==x21,fs1 == 0 and fe1 == 0x0f and fm1 == 0x039 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x018 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x11; op2:x5; dest:x21; op1val:0x3c39; op2val:0x3c18; + valaddr_reg:x14; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x16 +*/ +TEST_FPRR_OP(fdiv.h, x21, x11, x5, dyn, 0, 0, x14, 22*FLEN/8, x17, x10, x16) + +inst_26: +// rs1==x23, rs2==x24, rd==x9,fs1 == 0 and fe1 == 0x0f and fm1 == 0x02f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x23; op2:x24; dest:x9; op1val:0x3c2f; op2val:0x3be0; + valaddr_reg:x14; val_offset:24*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x16 +*/ +TEST_FPRR_OP(fdiv.h, x9, x23, x24, dyn, 0, 0, x14, 24*FLEN/8, x17, x10, x16) +RVTEST_VALBASEUPD(x3,test_dataset_2) + +inst_27: +// rs1==x1, rs2==x21, rd==x18,fs1 == 0 and fe1 == 0x0f and fm1 == 0x005 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x325 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x1; op2:x21; dest:x18; op1val:0x3c05; op2val:0x3b25; + valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x16 +*/ +TEST_FPRR_OP(fdiv.h, x18, x1, x21, dyn, 0, 0, x3, 0*FLEN/8, x4, x10, x16) + +inst_28: +// rs1==x24, rs2==x15, rd==x14,fs1 == 0 and fe1 == 0x0f and fm1 == 0x040 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2cc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x24; op2:x15; dest:x14; op1val:0x3c40; op2val:0x3acc; + valaddr_reg:x3; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x16 +*/ +TEST_FPRR_OP(fdiv.h, x14, x24, x15, dyn, 0, 0, x3, 2*FLEN/8, x4, x10, x16) + +inst_29: +// rs1==x6, rs2==x30, rd==x26,fs1 == 0 and fe1 == 0x0f and fm1 == 0x022 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x182 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x6; op2:x30; dest:x26; op1val:0x3c22; op2val:0x3982; + valaddr_reg:x3; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x16 +*/ +TEST_FPRR_OP(fdiv.h, x26, x6, x30, dyn, 0, 0, x3, 4*FLEN/8, x4, x10, x16) + +inst_30: +// rs1==x13, rs2==x20, rd==x16,fs1 == 0 and fe1 == 0x0f and fm1 == 0x038 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x036 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x13; op2:x20; dest:x16; op1val:0x3c38; op2val:0xbc36; + valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x16, x13, x20, dyn, 0, 0, x3, 6*FLEN/8, x4, x10, x2) +RVTEST_SIGBASE(x1,signature_x1_2) + +inst_31: +// rs1==x8, rs2==x18, rd==x5,fs1 == 0 and fe1 == 0x0f and fm1 == 0x027 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x024 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x8; op2:x18; dest:x5; op1val:0x3c27; op2val:0xbc24; + valaddr_reg:x3; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x5, x8, x18, dyn, 0, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_32: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x041 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x03c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c41; op2val:0xbc3c; + valaddr_reg:x3; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_33: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x04a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x041 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c4a; op2val:0xbc41; + valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_34: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x045 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x034 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c45; op2val:0xbc34; + valaddr_reg:x3; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_35: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x035 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x014 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c35; op2val:0xbc14; + valaddr_reg:x3; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_36: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x01e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c1e; op2val:0xbbc0; + valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_37: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x058 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c58; op2val:0xbbb8; + valaddr_reg:x3; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_38: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x024 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2a0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c24; op2val:0xbaa0; + valaddr_reg:x3; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_39: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x056 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1c8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c56; op2val:0xb9c8; + valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_40: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x015 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x137 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x15; op2val:0x4d37; + valaddr_reg:x3; val_offset:26*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_41: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x02a and fs2 == 0 and fe2 == 0x12 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2a; op2val:0x4b00; + valaddr_reg:x3; val_offset:28*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_42: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x04a and fs2 == 0 and fe2 == 0x12 and fm2 == 0x366 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4a; op2val:0x4b66; + valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_43: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x238 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xe; op2val:0x3e38; + valaddr_reg:x3; val_offset:32*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 32*FLEN/8, x4, x1, x2) + +inst_44: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x054 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x54; op2val:0x44f0; + valaddr_reg:x3; val_offset:34*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 34*FLEN/8, x4, x1, x2) + +inst_45: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x052 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x52; op2val:0x40f8; + valaddr_reg:x3; val_offset:36*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 36*FLEN/8, x4, x1, x2) + +inst_46: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x023 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x04e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x23; op2val:0x384e; + valaddr_reg:x3; val_offset:38*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 38*FLEN/8, x4, x1, x2) + +inst_47: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x010 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x10; op2val:0x2ff0; + valaddr_reg:x3; val_offset:40*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 40*FLEN/8, x4, x1, x2) + +inst_48: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03e and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3b8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3e; op2val:0x33b8; + valaddr_reg:x3; val_offset:42*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 42*FLEN/8, x4, x1, x2) + +inst_49: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03e and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3bc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3e; op2val:0x2fbc; + valaddr_reg:x3; val_offset:44*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 44*FLEN/8, x4, x1, x2) + +inst_50: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x02d and fs2 == 1 and fe2 == 0x14 and fm2 == 0x196 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d; op2val:0xd196; + valaddr_reg:x3; val_offset:46*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 46*FLEN/8, x4, x1, x2) + +inst_51: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x035 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x06a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x35; op2val:0xcc6a; + valaddr_reg:x3; val_offset:48*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 48*FLEN/8, x4, x1, x2) + +inst_52: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0cc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3; op2val:0xb8cc; + valaddr_reg:x3; val_offset:50*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 50*FLEN/8, x4, x1, x2) + +inst_53: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x037 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x21c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x37; op2val:0xc61c; + valaddr_reg:x3; val_offset:52*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 52*FLEN/8, x4, x1, x2) + +inst_54: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x036 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x25a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x36; op2val:0xc25a; + valaddr_reg:x3; val_offset:54*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 54*FLEN/8, x4, x1, x2) + +inst_55: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x006 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x1d1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6; op2val:0xb1d1; + valaddr_reg:x3; val_offset:56*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 56*FLEN/8, x4, x1, x2) + +inst_56: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x04f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0dc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4f; op2val:0xbcdc; + valaddr_reg:x3; val_offset:58*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 58*FLEN/8, x4, x1, x2) + +inst_57: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x006 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x1f4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6; op2val:0xa9f4; + valaddr_reg:x3; val_offset:60*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 60*FLEN/8, x4, x1, x2) + +inst_58: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x05c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1ba and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5c; op2val:0xb5ba; + valaddr_reg:x3; val_offset:62*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 62*FLEN/8, x4, x1, x2) + +inst_59: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x02b and fs2 == 1 and fe2 == 0x0b and fm2 == 0x15d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b; op2val:0xad5d; + valaddr_reg:x3; val_offset:64*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 64*FLEN/8, x4, x1, x2) + +inst_60: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x024 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x082 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x24; op2val:0x2882; + valaddr_reg:x3; val_offset:66*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 66*FLEN/8, x4, x1, x2) + +inst_61: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x01f and fs2 == 0 and fe2 == 0x09 and fm2 == 0x3c5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x1f; op2val:0x27c5; + valaddr_reg:x3; val_offset:68*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 68*FLEN/8, x4, x1, x2) + +inst_62: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x028 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x106 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x28; op2val:0x2906; + valaddr_reg:x3; val_offset:70*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 70*FLEN/8, x4, x1, x2) + +inst_63: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00a and fs2 == 0 and fe2 == 0x08 and fm2 == 0x10b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xa; op2val:0x210b; + valaddr_reg:x3; val_offset:72*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 72*FLEN/8, x4, x1, x2) + +inst_64: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x04d and fs2 == 0 and fe2 == 0x0b and fm2 == 0x0e4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4d; op2val:0x2ce4; + valaddr_reg:x3; val_offset:74*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 74*FLEN/8, x4, x1, x2) + +inst_65: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x005 and fs2 == 0 and fe2 == 0x07 and fm2 == 0x12a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5; op2val:0x1d2a; + valaddr_reg:x3; val_offset:76*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 76*FLEN/8, x4, x1, x2) + +inst_66: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x035 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x312 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x35; op2val:0x2b12; + valaddr_reg:x3; val_offset:78*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 78*FLEN/8, x4, x1, x2) + +inst_67: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x04f and fs2 == 0 and fe2 == 0x0b and fm2 == 0x1a6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4f; op2val:0x2da6; + valaddr_reg:x3; val_offset:80*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 80*FLEN/8, x4, x1, x2) + +inst_68: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x014 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x2ac and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x14; op2val:0x26ac; + valaddr_reg:x3; val_offset:82*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 82*FLEN/8, x4, x1, x2) + +inst_69: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x006 and fs2 == 0 and fe2 == 0x08 and fm2 == 0x203 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6; op2val:0x2203; + valaddr_reg:x3; val_offset:84*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 84*FLEN/8, x4, x1, x2) + +inst_70: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x029 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x122 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x29; op2val:0xa922; + valaddr_reg:x3; val_offset:86*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 86*FLEN/8, x4, x1, x2) + +inst_71: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x012 and fs2 == 1 and fe2 == 0x09 and fm2 == 0x083 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x12; op2val:0xa483; + valaddr_reg:x3; val_offset:88*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 88*FLEN/8, x4, x1, x2) + +inst_72: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x031 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x227 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x31; op2val:0xaa27; + valaddr_reg:x3; val_offset:90*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 90*FLEN/8, x4, x1, x2) + +inst_73: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x043 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x039 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x43; op2val:0xac39; + valaddr_reg:x3; val_offset:92*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 92*FLEN/8, x4, x1, x2) + +inst_74: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x053 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x146 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x53; op2val:0xad46; + valaddr_reg:x3; val_offset:94*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 94*FLEN/8, x4, x1, x2) + +inst_75: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x058 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1ae and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x58; op2val:0xadae; + valaddr_reg:x3; val_offset:96*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 96*FLEN/8, x4, x1, x2) + +inst_76: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 1 and fe2 == 0x08 and fm2 == 0x379 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xe; op2val:0xa379; + valaddr_reg:x3; val_offset:98*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 98*FLEN/8, x4, x1, x2) + +inst_77: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x041 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x0a5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x41; op2val:0xaca5; + valaddr_reg:x3; val_offset:100*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 100*FLEN/8, x4, x1, x2) + +inst_78: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x038 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x0ac and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x38; op2val:0xacac; + valaddr_reg:x3; val_offset:102*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 102*FLEN/8, x4, x1, x2) + +inst_79: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x05d and fs2 == 1 and fe2 == 0x0c and fm2 == 0x1d2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5d; op2val:0xb1d2; + valaddr_reg:x3; val_offset:104*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 104*FLEN/8, x4, x1, x2) + +inst_80: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x01f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x01d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x41f; op2val:0x3c1d; + valaddr_reg:x3; val_offset:106*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 106*FLEN/8, x4, x1, x2) + +inst_81: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x038 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x035 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x438; op2val:0x3c35; + valaddr_reg:x3; val_offset:108*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 108*FLEN/8, x4, x1, x2) + +inst_82: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x043 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x03e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x443; op2val:0x3c3e; + valaddr_reg:x3; val_offset:110*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 110*FLEN/8, x4, x1, x2) + +inst_83: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x047 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x03e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x447; op2val:0x3c3e; + valaddr_reg:x3; val_offset:112*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 112*FLEN/8, x4, x1, x2) + +inst_84: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3e4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x402; op2val:0x3be4; + valaddr_reg:x3; val_offset:114*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 114*FLEN/8, x4, x1, x2) + +inst_85: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x04b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x029 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x44b; op2val:0x3c29; + valaddr_reg:x3; val_offset:116*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 116*FLEN/8, x4, x1, x2) + +inst_86: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x003 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x38d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x403; op2val:0x3b8d; + valaddr_reg:x3; val_offset:118*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 118*FLEN/8, x4, x1, x2) + +inst_87: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x04f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3a8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x44f; op2val:0x3ba8; + valaddr_reg:x3; val_offset:120*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 120*FLEN/8, x4, x1, x2) + +inst_88: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x051 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2e8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x451; op2val:0x3ae8; + valaddr_reg:x3; val_offset:122*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 122*FLEN/8, x4, x1, x2) + +inst_89: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x008 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x160 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x408; op2val:0x3960; + valaddr_reg:x3; val_offset:124*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 124*FLEN/8, x4, x1, x2) + +inst_90: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x051 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x04f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x451; op2val:0xbc4f; + valaddr_reg:x3; val_offset:126*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 126*FLEN/8, x4, x1, x2) + +inst_91: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x03c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x039 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x43c; op2val:0xbc39; + valaddr_reg:x3; val_offset:128*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 128*FLEN/8, x4, x1, x2) + +inst_92: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x057 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x052 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x457; op2val:0xbc52; + valaddr_reg:x3; val_offset:130*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 130*FLEN/8, x4, x1, x2) + +inst_93: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x04e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x045 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x44e; op2val:0xbc45; + valaddr_reg:x3; val_offset:132*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 132*FLEN/8, x4, x1, x2) + +inst_94: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x024 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x013 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x424; op2val:0xbc13; + valaddr_reg:x3; val_offset:134*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 134*FLEN/8, x4, x1, x2) + +inst_95: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x01e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x43f; op2val:0xbc1e; + valaddr_reg:x3; val_offset:136*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 136*FLEN/8, x4, x1, x2) + +inst_96: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x04c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x00b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x44c; op2val:0xbc0b; + valaddr_reg:x3; val_offset:138*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 138*FLEN/8, x4, x1, x2) + +inst_97: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x057 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x457; op2val:0xbbb7; + valaddr_reg:x3; val_offset:140*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 140*FLEN/8, x4, x1, x2) + +inst_98: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x030 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2b3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x430; op2val:0xbab3; + valaddr_reg:x3; val_offset:142*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 142*FLEN/8, x4, x1, x2) + +inst_99: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x051 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1c1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x451; op2val:0xb9c1; + valaddr_reg:x3; val_offset:144*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 144*FLEN/8, x4, x1, x2) + +inst_100: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x027 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x028 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7827; op2val:0x3828; + valaddr_reg:x3; val_offset:146*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 146*FLEN/8, x4, x1, x2) + +inst_101: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x04e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x784d; op2val:0x384e; + valaddr_reg:x3; val_offset:148*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 148*FLEN/8, x4, x1, x2) + +inst_102: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x017 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x019 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7817; op2val:0x3819; + valaddr_reg:x3; val_offset:150*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 150*FLEN/8, x4, x1, x2) + +inst_103: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x018 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x01c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7818; op2val:0x381c; + valaddr_reg:x3; val_offset:152*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 152*FLEN/8, x4, x1, x2) + +inst_104: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x062 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x06b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7862; op2val:0x386b; + valaddr_reg:x3; val_offset:154*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 154*FLEN/8, x4, x1, x2) + +inst_105: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x05f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x784d; op2val:0x385f; + valaddr_reg:x3; val_offset:156*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 156*FLEN/8, x4, x1, x2) + +inst_106: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x027 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x049 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7827; op2val:0x3849; + valaddr_reg:x3; val_offset:158*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 158*FLEN/8, x4, x1, x2) + +inst_107: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x053 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x780e; op2val:0x3853; + valaddr_reg:x3; val_offset:160*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 160*FLEN/8, x4, x1, x2) + +inst_108: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x097 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7804; op2val:0x3897; + valaddr_reg:x3; val_offset:162*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 162*FLEN/8, x4, x1, x2) + +inst_109: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x058 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1cb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7858; op2val:0x39cb; + valaddr_reg:x3; val_offset:164*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 164*FLEN/8, x4, x1, x2) + +inst_110: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x011 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x012 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7811; op2val:0xb812; + valaddr_reg:x3; val_offset:166*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 166*FLEN/8, x4, x1, x2) + +inst_111: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x041 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x042 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7841; op2val:0xb842; + valaddr_reg:x3; val_offset:168*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 168*FLEN/8, x4, x1, x2) + +inst_112: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x054 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x056 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7854; op2val:0xb856; + valaddr_reg:x3; val_offset:170*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 170*FLEN/8, x4, x1, x2) + +inst_113: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x01f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x023 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x781f; op2val:0xb823; + valaddr_reg:x3; val_offset:172*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 172*FLEN/8, x4, x1, x2) + +inst_114: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x018 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x020 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7818; op2val:0xb820; + valaddr_reg:x3; val_offset:174*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 174*FLEN/8, x4, x1, x2) + +inst_115: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x038 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x049 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7838; op2val:0xb849; + valaddr_reg:x3; val_offset:176*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 176*FLEN/8, x4, x1, x2) + +inst_116: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x05a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x07e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x785a; op2val:0xb87e; + valaddr_reg:x3; val_offset:178*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 178*FLEN/8, x4, x1, x2) + +inst_117: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x053 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x780e; op2val:0xb853; + valaddr_reg:x3; val_offset:180*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 180*FLEN/8, x4, x1, x2) + +inst_118: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0c2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x782a; op2val:0xb8c2; + valaddr_reg:x3; val_offset:182*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 182*FLEN/8, x4, x1, x2) + +inst_119: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x057 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1ca and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7857; op2val:0xb9ca; + valaddr_reg:x3; val_offset:184*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 184*FLEN/8, x4, x1, x2) + +inst_120: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x046 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x060 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x46; op2val:0x5060; + valaddr_reg:x3; val_offset:186*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 186*FLEN/8, x4, x1, x2) + +inst_121: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x030 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x30; op2val:0x4a00; + valaddr_reg:x3; val_offset:188*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 188*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(31,32,FLEN) +NAN_BOXED(20402,32,FLEN) +NAN_BOXED(70,32,FLEN) +NAN_BOXED(70,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(61,32,FLEN) +NAN_BOXED(18336,32,FLEN) +NAN_BOXED(75,32,FLEN) +NAN_BOXED(17584,32,FLEN) +NAN_BOXED(78,32,FLEN) +NAN_BOXED(16608,32,FLEN) +NAN_BOXED(61,32,FLEN) +NAN_BOXED(15264,32,FLEN) +NAN_BOXED(71,32,FLEN) +NAN_BOXED(14448,32,FLEN) +NAN_BOXED(25,32,FLEN) +NAN_BOXED(11840,32,FLEN) +NAN_BOXED(61,32,FLEN) +NAN_BOXED(12192,32,FLEN) +NAN_BOXED(71,32,FLEN) +NAN_BOXED(54376,16,FLEN) +NAN_BOXED(51,32,FLEN) +NAN_BOXED(52832,16,FLEN) +NAN_BOXED(20,32,FLEN) +NAN_BOXED(50432,16,FLEN) +NAN_BOXED(82,32,FLEN) +NAN_BOXED(51488,16,FLEN) +test_dataset_1: +NAN_BOXED(67,32,FLEN) +NAN_BOXED(50224,16,FLEN) +NAN_BOXED(95,32,FLEN) +NAN_BOXED(49648,16,FLEN) +NAN_BOXED(86,32,FLEN) +NAN_BOXED(48480,16,FLEN) +NAN_BOXED(21,32,FLEN) +NAN_BOXED(45376,16,FLEN) +NAN_BOXED(76,32,FLEN) +NAN_BOXED(46272,16,FLEN) +NAN_BOXED(39,32,FLEN) +NAN_BOXED(44256,16,FLEN) +NAN_BOXED(15395,32,FLEN) +NAN_BOXED(15393,32,FLEN) +NAN_BOXED(15437,32,FLEN) +NAN_BOXED(15434,32,FLEN) +NAN_BOXED(15410,32,FLEN) +NAN_BOXED(15405,32,FLEN) +NAN_BOXED(15415,32,FLEN) +NAN_BOXED(15406,32,FLEN) +NAN_BOXED(15454,32,FLEN) +NAN_BOXED(15436,32,FLEN) +NAN_BOXED(15417,32,FLEN) +NAN_BOXED(15384,32,FLEN) +NAN_BOXED(15407,32,FLEN) +NAN_BOXED(15328,32,FLEN) +test_dataset_2: +NAN_BOXED(15365,16,FLEN) +NAN_BOXED(15141,16,FLEN) +NAN_BOXED(15424,16,FLEN) +NAN_BOXED(15052,16,FLEN) +NAN_BOXED(15394,16,FLEN) +NAN_BOXED(14722,16,FLEN) +NAN_BOXED(15416,16,FLEN) +NAN_BOXED(48182,16,FLEN) +NAN_BOXED(15399,16,FLEN) +NAN_BOXED(48164,16,FLEN) +NAN_BOXED(15425,16,FLEN) +NAN_BOXED(48188,16,FLEN) +NAN_BOXED(15434,16,FLEN) +NAN_BOXED(48193,16,FLEN) +NAN_BOXED(15429,16,FLEN) +NAN_BOXED(48180,16,FLEN) +NAN_BOXED(15413,16,FLEN) +NAN_BOXED(48148,16,FLEN) +NAN_BOXED(15390,16,FLEN) +NAN_BOXED(48064,16,FLEN) +NAN_BOXED(15448,16,FLEN) +NAN_BOXED(48056,16,FLEN) +NAN_BOXED(15396,16,FLEN) +NAN_BOXED(47776,16,FLEN) +NAN_BOXED(15446,16,FLEN) +NAN_BOXED(47560,16,FLEN) +NAN_BOXED(21,16,FLEN) +NAN_BOXED(19767,16,FLEN) +NAN_BOXED(42,16,FLEN) +NAN_BOXED(19200,16,FLEN) +NAN_BOXED(74,16,FLEN) +NAN_BOXED(19302,16,FLEN) +NAN_BOXED(14,16,FLEN) +NAN_BOXED(15928,16,FLEN) +NAN_BOXED(84,16,FLEN) +NAN_BOXED(17648,16,FLEN) +NAN_BOXED(82,16,FLEN) +NAN_BOXED(16632,16,FLEN) +NAN_BOXED(35,16,FLEN) +NAN_BOXED(14414,16,FLEN) +NAN_BOXED(16,16,FLEN) +NAN_BOXED(12272,16,FLEN) +NAN_BOXED(62,16,FLEN) +NAN_BOXED(13240,16,FLEN) +NAN_BOXED(62,16,FLEN) +NAN_BOXED(12220,16,FLEN) +NAN_BOXED(45,16,FLEN) +NAN_BOXED(53654,16,FLEN) +NAN_BOXED(53,16,FLEN) +NAN_BOXED(52330,16,FLEN) +NAN_BOXED(3,16,FLEN) +NAN_BOXED(47308,16,FLEN) +NAN_BOXED(55,16,FLEN) +NAN_BOXED(50716,16,FLEN) +NAN_BOXED(54,16,FLEN) +NAN_BOXED(49754,16,FLEN) +NAN_BOXED(6,16,FLEN) +NAN_BOXED(45521,16,FLEN) +NAN_BOXED(79,16,FLEN) +NAN_BOXED(48348,16,FLEN) +NAN_BOXED(6,16,FLEN) +NAN_BOXED(43508,16,FLEN) +NAN_BOXED(92,16,FLEN) +NAN_BOXED(46522,16,FLEN) +NAN_BOXED(43,16,FLEN) +NAN_BOXED(44381,16,FLEN) +NAN_BOXED(36,16,FLEN) +NAN_BOXED(10370,16,FLEN) +NAN_BOXED(31,16,FLEN) +NAN_BOXED(10181,16,FLEN) +NAN_BOXED(40,16,FLEN) +NAN_BOXED(10502,16,FLEN) +NAN_BOXED(10,16,FLEN) +NAN_BOXED(8459,16,FLEN) +NAN_BOXED(77,16,FLEN) +NAN_BOXED(11492,16,FLEN) +NAN_BOXED(5,16,FLEN) +NAN_BOXED(7466,16,FLEN) +NAN_BOXED(53,16,FLEN) +NAN_BOXED(11026,16,FLEN) +NAN_BOXED(79,16,FLEN) +NAN_BOXED(11686,16,FLEN) +NAN_BOXED(20,16,FLEN) +NAN_BOXED(9900,16,FLEN) +NAN_BOXED(6,16,FLEN) +NAN_BOXED(8707,16,FLEN) +NAN_BOXED(41,16,FLEN) +NAN_BOXED(43298,16,FLEN) +NAN_BOXED(18,16,FLEN) +NAN_BOXED(42115,16,FLEN) +NAN_BOXED(49,16,FLEN) +NAN_BOXED(43559,16,FLEN) +NAN_BOXED(67,16,FLEN) +NAN_BOXED(44089,16,FLEN) +NAN_BOXED(83,16,FLEN) +NAN_BOXED(44358,16,FLEN) +NAN_BOXED(88,16,FLEN) +NAN_BOXED(44462,16,FLEN) +NAN_BOXED(14,16,FLEN) +NAN_BOXED(41849,16,FLEN) +NAN_BOXED(65,16,FLEN) +NAN_BOXED(44197,16,FLEN) +NAN_BOXED(56,16,FLEN) +NAN_BOXED(44204,16,FLEN) +NAN_BOXED(93,16,FLEN) +NAN_BOXED(45522,16,FLEN) +NAN_BOXED(1055,16,FLEN) +NAN_BOXED(15389,16,FLEN) +NAN_BOXED(1080,16,FLEN) +NAN_BOXED(15413,16,FLEN) +NAN_BOXED(1091,16,FLEN) +NAN_BOXED(15422,16,FLEN) +NAN_BOXED(1095,16,FLEN) +NAN_BOXED(15422,16,FLEN) +NAN_BOXED(1026,16,FLEN) +NAN_BOXED(15332,16,FLEN) +NAN_BOXED(1099,16,FLEN) +NAN_BOXED(15401,16,FLEN) +NAN_BOXED(1027,16,FLEN) +NAN_BOXED(15245,16,FLEN) +NAN_BOXED(1103,16,FLEN) +NAN_BOXED(15272,16,FLEN) +NAN_BOXED(1105,16,FLEN) +NAN_BOXED(15080,16,FLEN) +NAN_BOXED(1032,16,FLEN) +NAN_BOXED(14688,16,FLEN) +NAN_BOXED(1105,16,FLEN) +NAN_BOXED(48207,16,FLEN) +NAN_BOXED(1084,16,FLEN) +NAN_BOXED(48185,16,FLEN) +NAN_BOXED(1111,16,FLEN) +NAN_BOXED(48210,16,FLEN) +NAN_BOXED(1102,16,FLEN) +NAN_BOXED(48197,16,FLEN) +NAN_BOXED(1060,16,FLEN) +NAN_BOXED(48147,16,FLEN) +NAN_BOXED(1087,16,FLEN) +NAN_BOXED(48158,16,FLEN) +NAN_BOXED(1100,16,FLEN) +NAN_BOXED(48139,16,FLEN) +NAN_BOXED(1111,16,FLEN) +NAN_BOXED(48055,16,FLEN) +NAN_BOXED(1072,16,FLEN) +NAN_BOXED(47795,16,FLEN) +NAN_BOXED(1105,16,FLEN) +NAN_BOXED(47553,16,FLEN) +NAN_BOXED(30759,16,FLEN) +NAN_BOXED(14376,16,FLEN) +NAN_BOXED(30797,16,FLEN) +NAN_BOXED(14414,16,FLEN) +NAN_BOXED(30743,16,FLEN) +NAN_BOXED(14361,16,FLEN) +NAN_BOXED(30744,16,FLEN) +NAN_BOXED(14364,16,FLEN) +NAN_BOXED(30818,16,FLEN) +NAN_BOXED(14443,16,FLEN) +NAN_BOXED(30797,16,FLEN) +NAN_BOXED(14431,16,FLEN) +NAN_BOXED(30759,16,FLEN) +NAN_BOXED(14409,16,FLEN) +NAN_BOXED(30734,16,FLEN) +NAN_BOXED(14419,16,FLEN) +NAN_BOXED(30724,16,FLEN) +NAN_BOXED(14487,16,FLEN) +NAN_BOXED(30808,16,FLEN) +NAN_BOXED(14795,16,FLEN) +NAN_BOXED(30737,16,FLEN) +NAN_BOXED(47122,16,FLEN) +NAN_BOXED(30785,16,FLEN) +NAN_BOXED(47170,16,FLEN) +NAN_BOXED(30804,16,FLEN) +NAN_BOXED(47190,16,FLEN) +NAN_BOXED(30751,16,FLEN) +NAN_BOXED(47139,16,FLEN) +NAN_BOXED(30744,16,FLEN) +NAN_BOXED(47136,16,FLEN) +NAN_BOXED(30776,16,FLEN) +NAN_BOXED(47177,16,FLEN) +NAN_BOXED(30810,16,FLEN) +NAN_BOXED(47230,16,FLEN) +NAN_BOXED(30734,16,FLEN) +NAN_BOXED(47187,16,FLEN) +NAN_BOXED(30762,16,FLEN) +NAN_BOXED(47298,16,FLEN) +NAN_BOXED(30807,16,FLEN) +NAN_BOXED(47562,16,FLEN) +NAN_BOXED(70,16,FLEN) +NAN_BOXED(20576,16,FLEN) +NAN_BOXED(48,16,FLEN) +NAN_BOXED(18944,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 34*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x10_0: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_2: + .fill 182*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fdiv_b20-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fdiv_b20-01.S new file mode 100644 index 000000000..8f2fc922d --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fdiv_b20-01.S @@ -0,0 +1,519 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 05:22:24 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fdiv.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fdiv.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fdiv_b20 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fdiv_b20) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x18,test_dataset_0) +RVTEST_SIGBASE(x14,signature_x14_1) + +inst_0: +// rs1 == rd != rs2, rs1==x28, rs2==x2, rd==x28,fs1 == 0 and fe1 == 0x1d and fm1 == 0x24a and fs2 == 1 and fe2 == 0x0a and fm2 == 0x24a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x28; op2:x2; dest:x28; op1val:0x764a; op2val:0xaa4a; + valaddr_reg:x18; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x15 +*/ +TEST_FPRR_OP(fdiv.h, x28, x28, x2, dyn, 0, 0, x18, 0*FLEN/8, x24, x14, x15) + +inst_1: +// rs1 == rs2 != rd, rs1==x7, rs2==x7, rd==x11,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x7; op2:x7; dest:x11; op1val:0x7ad2; op2val:0x7ad2; + valaddr_reg:x18; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x15 +*/ +TEST_FPRR_OP(fdiv.h, x11, x7, x7, dyn, 0, 0, x18, 2*FLEN/8, x24, x14, x15) + +inst_2: +// rs1 == rs2 == rd, rs1==x17, rs2==x17, rd==x17,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ae and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x17; op2:x17; dest:x17; op1val:0x77ae; op2val:0x77ae; + valaddr_reg:x18; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x15 +*/ +TEST_FPRR_OP(fdiv.h, x17, x17, x17, dyn, 0, 0, x18, 4*FLEN/8, x24, x14, x15) + +inst_3: +// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==x5, rs2==x28, rd==x20,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x5; op2:x28; dest:x20; op1val:0x79f2; op2val:0x7bff; + valaddr_reg:x18; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x15 +*/ +TEST_FPRR_OP(fdiv.h, x20, x5, x28, dyn, 0, 0, x18, 6*FLEN/8, x24, x14, x15) + +inst_4: +// rs2 == rd != rs1, rs1==x19, rs2==x9, rd==x9,fs1 == 0 and fe1 == 0x1d and fm1 == 0x277 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x19; op2:x9; dest:x9; op1val:0x7677; op2val:0xfbff; + valaddr_reg:x18; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x15 +*/ +TEST_FPRR_OP(fdiv.h, x9, x19, x9, dyn, 0, 0, x18, 8*FLEN/8, x24, x14, x15) + +inst_5: +// rs1==x3, rs2==x27, rd==x19,fs1 == 0 and fe1 == 0x1e and fm1 == 0x150 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x3; op2:x27; dest:x19; op1val:0x7950; op2val:0x7bff; + valaddr_reg:x18; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x15 +*/ +TEST_FPRR_OP(fdiv.h, x19, x3, x27, dyn, 0, 0, x18, 10*FLEN/8, x24, x14, x15) + +inst_6: +// rs1==x31, rs2==x16, rd==x30,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1df and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x31; op2:x16; dest:x30; op1val:0x75df; op2val:0x8000; + valaddr_reg:x18; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x15 +*/ +TEST_FPRR_OP(fdiv.h, x30, x31, x16, dyn, 0, 0, x18, 12*FLEN/8, x24, x14, x15) + +inst_7: +// rs1==x22, rs2==x1, rd==x27,fs1 == 0 and fe1 == 0x1e and fm1 == 0x30e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x22; op2:x1; dest:x27; op1val:0x7b0e; op2val:0xfbff; + valaddr_reg:x18; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x15 +*/ +TEST_FPRR_OP(fdiv.h, x27, x22, x1, dyn, 0, 0, x18, 14*FLEN/8, x24, x14, x15) + +inst_8: +// rs1==x21, rs2==x20, rd==x6,fs1 == 0 and fe1 == 0x1e and fm1 == 0x234 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x21; op2:x20; dest:x6; op1val:0x7a34; op2val:0x0; + valaddr_reg:x18; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x15 +*/ +TEST_FPRR_OP(fdiv.h, x6, x21, x20, dyn, 0, 0, x18, 16*FLEN/8, x24, x14, x15) + +inst_9: +// rs1==x13, rs2==x30, rd==x8,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1e7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x13; op2:x30; dest:x8; op1val:0x79e7; op2val:0x7bff; + valaddr_reg:x18; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x15 +*/ +TEST_FPRR_OP(fdiv.h, x8, x13, x30, dyn, 0, 0, x18, 18*FLEN/8, x24, x14, x15) + +inst_10: +// rs1==x16, rs2==x11, rd==x23,fs1 == 0 and fe1 == 0x1b and fm1 == 0x188 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x16; op2:x11; dest:x23; op1val:0x6d88; op2val:0x0; + valaddr_reg:x18; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x15 +*/ +TEST_FPRR_OP(fdiv.h, x23, x16, x11, dyn, 0, 0, x18, 20*FLEN/8, x24, x14, x15) + +inst_11: +// rs1==x9, rs2==x8, rd==x5,fs1 == 0 and fe1 == 0x1e and fm1 == 0x14e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x9; op2:x8; dest:x5; op1val:0x794e; op2val:0x0; + valaddr_reg:x18; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x15 +*/ +TEST_FPRR_OP(fdiv.h, x5, x9, x8, dyn, 0, 0, x18, 22*FLEN/8, x24, x14, x15) + +inst_12: +// rs1==x1, rs2==x10, rd==x21,fs1 == 0 and fe1 == 0x1b and fm1 == 0x2e7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x1; op2:x10; dest:x21; op1val:0x6ee7; op2val:0x7bff; + valaddr_reg:x18; val_offset:24*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x15 +*/ +TEST_FPRR_OP(fdiv.h, x21, x1, x10, dyn, 0, 0, x18, 24*FLEN/8, x24, x14, x15) + +inst_13: +// rs1==x4, rs2==x12, rd==x7,fs1 == 0 and fe1 == 0x1c and fm1 == 0x13c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x4; op2:x12; dest:x7; op1val:0x713c; op2val:0xfbff; + valaddr_reg:x18; val_offset:26*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x15 +*/ +TEST_FPRR_OP(fdiv.h, x7, x4, x12, dyn, 0, 0, x18, 26*FLEN/8, x24, x14, x15) +RVTEST_VALBASEUPD(x5,test_dataset_1) + +inst_14: +// rs1==x30, rs2==x22, rd==x0,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b7 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x22; dest:x0; op1val:0x7ab7; op2val:0xfbff; + valaddr_reg:x5; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x15 +*/ +TEST_FPRR_OP(fdiv.h, x0, x30, x22, dyn, 0, 0, x5, 0*FLEN/8, x8, x14, x15) + +inst_15: +// rs1==x11, rs2==x13, rd==x31,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ec and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x11; op2:x13; dest:x31; op1val:0x75ec; op2val:0xfbff; + valaddr_reg:x5; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x15 +*/ +TEST_FPRR_OP(fdiv.h, x31, x11, x13, dyn, 0, 0, x5, 2*FLEN/8, x8, x14, x15) + +inst_16: +// rs1==x29, rs2==x19, rd==x3,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x29; op2:x19; dest:x3; op1val:0x79db; op2val:0x0; + valaddr_reg:x5; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x15 +*/ +TEST_FPRR_OP(fdiv.h, x3, x29, x19, dyn, 0, 0, x5, 4*FLEN/8, x8, x14, x15) + +inst_17: +// rs1==x12, rs2==x4, rd==x16,fs1 == 0 and fe1 == 0x1d and fm1 == 0x381 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x12; op2:x4; dest:x16; op1val:0x7781; op2val:0xfbff; + valaddr_reg:x5; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fdiv.h, x16, x12, x4, dyn, 0, 0, x5, 6*FLEN/8, x8, x14, x9) + +inst_18: +// rs1==x10, rs2==x0, rd==x13,fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x10; op2:x0; dest:x13; op1val:0x74ef; op2val:0x0; + valaddr_reg:x5; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fdiv.h, x13, x10, x0, dyn, 0, 0, x5, 8*FLEN/8, x8, x14, x9) + +inst_19: +// rs1==x15, rs2==x24, rd==x22,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c8 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x15; op2:x24; dest:x22; op1val:0x7ac8; op2val:0xf7c0; + valaddr_reg:x5; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fdiv.h, x22, x15, x24, dyn, 0, 0, x5, 10*FLEN/8, x8, x14, x9) +RVTEST_SIGBASE(x7,signature_x7_0) + +inst_20: +// rs1==x24, rs2==x6, rd==x12,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ea and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x24; op2:x6; dest:x12; op1val:0x78ea; op2val:0x7bff; + valaddr_reg:x5; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fdiv.h, x12, x24, x6, dyn, 0, 0, x5, 12*FLEN/8, x8, x7, x9) + +inst_21: +// rs1==x25, rs2==x14, rd==x10,fs1 == 0 and fe1 == 0x1e and fm1 == 0x09f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x25; op2:x14; dest:x10; op1val:0x789f; op2val:0xfbff; + valaddr_reg:x5; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fdiv.h, x10, x25, x14, dyn, 0, 0, x5, 14*FLEN/8, x8, x7, x9) + +inst_22: +// rs1==x20, rs2==x15, rd==x24,fs1 == 0 and fe1 == 0x1e and fm1 == 0x12c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x20; op2:x15; dest:x24; op1val:0x792c; op2val:0x0; + valaddr_reg:x5; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fdiv.h, x24, x20, x15, dyn, 0, 0, x5, 16*FLEN/8, x8, x7, x9) + +inst_23: +// rs1==x27, rs2==x18, rd==x29,fs1 == 0 and fe1 == 0x1c and fm1 == 0x164 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x27; op2:x18; dest:x29; op1val:0x7164; op2val:0x7bff; + valaddr_reg:x5; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fdiv.h, x29, x27, x18, dyn, 0, 0, x5, 18*FLEN/8, x8, x7, x9) + +inst_24: +// rs1==x2, rs2==x3, rd==x1,fs1 == 0 and fe1 == 0x1c and fm1 == 0x342 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x2; op2:x3; dest:x1; op1val:0x7342; op2val:0x8000; + valaddr_reg:x5; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fdiv.h, x1, x2, x3, dyn, 0, 0, x5, 20*FLEN/8, x8, x7, x9) + +inst_25: +// rs1==x14, rs2==x26, rd==x25,fs1 == 0 and fe1 == 0x18 and fm1 == 0x24d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x14; op2:x26; dest:x25; op1val:0x624d; op2val:0x0; + valaddr_reg:x5; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fdiv.h, x25, x14, x26, dyn, 0, 0, x5, 22*FLEN/8, x8, x7, x9) +RVTEST_VALBASEUPD(x3,test_dataset_2) + +inst_26: +// rs1==x18, rs2==x29, rd==x14,fs1 == 0 and fe1 == 0x1c and fm1 == 0x261 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x008 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x18; op2:x29; dest:x14; op1val:0x7261; op2val:0x8008; + valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fdiv.h, x14, x18, x29, dyn, 0, 0, x3, 0*FLEN/8, x10, x7, x9) + +inst_27: +// rs1==x6, rs2==x25, rd==x26,fs1 == 0 and fe1 == 0x1e and fm1 == 0x35b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x6; op2:x25; dest:x26; op1val:0x7b5b; op2val:0x0; + valaddr_reg:x3; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fdiv.h, x26, x6, x25, dyn, 0, 0, x3, 2*FLEN/8, x10, x7, x9) + +inst_28: +// rs1==x8, rs2==x5, rd==x4,fs1 == 0 and fe1 == 0x1e and fm1 == 0x062 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x8; op2:x5; dest:x4; op1val:0x7862; op2val:0x0; + valaddr_reg:x3; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fdiv.h, x4, x8, x5, dyn, 0, 0, x3, 4*FLEN/8, x10, x7, x9) + +inst_29: +// rs1==x0, rs2==x23, rd==x15,fs1 == 0 and fe1 == 0x1d and fm1 == 0x277 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x0; op2:x23; dest:x15; op1val:0x0; op2val:0x8000; + valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fdiv.h, x15, x0, x23, dyn, 0, 0, x3, 6*FLEN/8, x10, x7, x9) + +inst_30: +// rs1==x23, rs2==x31, rd==x2,fs1 == 0 and fe1 == 0x1d and fm1 == 0x17f and fs2 == 1 and fe2 == 0x16 and fm2 == 0x266 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x23; op2:x31; dest:x2; op1val:0x757f; op2val:0xda66; + valaddr_reg:x3; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fdiv.h, x2, x23, x31, dyn, 0, 0, x3, 8*FLEN/8, x10, x7, x9) + +inst_31: +// rs1==x26, rs2==x21, rd==x18,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c6 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x26; op2:x21; dest:x18; op1val:0x7ac6; op2val:0xfbff; + valaddr_reg:x3; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fdiv.h, x18, x26, x21, dyn, 0, 0, x3, 10*FLEN/8, x10, x7, x9) + +inst_32: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x75a6; op2val:0x8000; + valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 12*FLEN/8, x10, x7, x9) + +inst_33: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x346 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b46; op2val:0x7bff; + valaddr_reg:x3; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 14*FLEN/8, x10, x7, x1) + +inst_34: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x145 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7945; op2val:0x8000; + valaddr_reg:x3; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 16*FLEN/8, x10, x7, x1) + +inst_35: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0de and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78de; op2val:0xfbff; + valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 18*FLEN/8, x10, x7, x1) + +inst_36: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79d5; op2val:0x8000; + valaddr_reg:x3; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 20*FLEN/8, x10, x7, x1) + +inst_37: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ad2; op2val:0x0; + valaddr_reg:x3; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 22*FLEN/8, x10, x7, x1) + +inst_38: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ae and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x77ae; op2val:0x7bff; + valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 24*FLEN/8, x10, x7, x1) + +inst_39: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b7 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab7; op2val:0xfbff; + valaddr_reg:x3; val_offset:26*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 26*FLEN/8, x10, x7, x1) + +inst_40: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74ef; op2val:0x0; + valaddr_reg:x3; val_offset:28*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 28*FLEN/8, x10, x7, x1) + +inst_41: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x277 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7677; op2val:0x8000; + valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 30*FLEN/8, x10, x7, x1) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(30282,32,FLEN) +NAN_BOXED(43594,16,FLEN) +NAN_BOXED(31442,32,FLEN) +NAN_BOXED(31442,32,FLEN) +NAN_BOXED(30638,32,FLEN) +NAN_BOXED(30638,32,FLEN) +NAN_BOXED(31218,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(30327,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31056,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(30175,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31502,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31284,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31207,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(28040,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31054,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(28391,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(28988,32,FLEN) +NAN_BOXED(64511,16,FLEN) +test_dataset_1: +NAN_BOXED(31415,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30188,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31195,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(30593,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29935,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31432,32,FLEN) +NAN_BOXED(63424,16,FLEN) +NAN_BOXED(30954,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(30879,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31020,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(29028,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(29506,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(25165,32,FLEN) +NAN_BOXED(0,32,FLEN) +test_dataset_2: +NAN_BOXED(29281,16,FLEN) +NAN_BOXED(32776,16,FLEN) +NAN_BOXED(31579,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(30818,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(30079,16,FLEN) +NAN_BOXED(55910,16,FLEN) +NAN_BOXED(31430,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30118,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31558,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31045,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(30942,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31189,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31442,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(30638,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31415,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29935,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(30327,16,FLEN) +NAN_BOXED(32768,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x14_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x14_1: + .fill 40*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x7_0: + .fill 44*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fdiv_b21-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fdiv_b21-01.S new file mode 100644 index 000000000..22dd2df20 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fdiv_b21-01.S @@ -0,0 +1,6931 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 05:22:24 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fdiv.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fdiv.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fdiv_b21 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fdiv_b21) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x10,test_dataset_0) +RVTEST_SIGBASE(x15,signature_x15_1) + +inst_0: +// rs1 == rd != rs2, rs1==x11, rs2==x22, rd==x11,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x11; op2:x22; dest:x11; op1val:0x0; op2val:0x0; + valaddr_reg:x10; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fdiv.h, x11, x11, x22, dyn, 0, 0, x10, 0*FLEN/8, x19, x15, x9) + +inst_1: +// rs1 == rs2 != rd, rs1==x31, rs2==x31, rd==x0,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x31; op2:x31; dest:x0; op1val:0x0; op2val:0x0; + valaddr_reg:x10; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fdiv.h, x0, x31, x31, dyn, 0, 0, x10, 2*FLEN/8, x19, x15, x9) + +inst_2: +// rs1 == rs2 == rd, rs1==x8, rs2==x8, rd==x8,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x8; op2:x8; dest:x8; op1val:0x0; op2val:0x0; + valaddr_reg:x10; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fdiv.h, x8, x8, x8, dyn, 0, 0, x10, 4*FLEN/8, x19, x15, x9) + +inst_3: +// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==x1, rs2==x20, rd==x24,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x1; op2:x20; dest:x24; op1val:0x0; op2val:0x8002; + valaddr_reg:x10; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fdiv.h, x24, x1, x20, dyn, 0, 0, x10, 6*FLEN/8, x19, x15, x9) + +inst_4: +// rs2 == rd != rs1, rs1==x21, rs2==x12, rd==x12,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x21; op2:x12; dest:x12; op1val:0x0; op2val:0x3fe; + valaddr_reg:x10; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fdiv.h, x12, x21, x12, dyn, 0, 0, x10, 8*FLEN/8, x19, x15, x9) + +inst_5: +// rs1==x7, rs2==x18, rd==x30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x7; op2:x18; dest:x30; op1val:0x0; op2val:0x83fe; + valaddr_reg:x10; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fdiv.h, x30, x7, x18, dyn, 0, 0, x10, 10*FLEN/8, x19, x15, x9) + +inst_6: +// rs1==x16, rs2==x3, rd==x5,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x16; op2:x3; dest:x5; op1val:0x0; op2val:0x2aa; + valaddr_reg:x10; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fdiv.h, x5, x16, x3, dyn, 0, 0, x10, 12*FLEN/8, x19, x15, x9) + +inst_7: +// rs1==x14, rs2==x17, rd==x4,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x14; op2:x17; dest:x4; op1val:0x0; op2val:0x82aa; + valaddr_reg:x10; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fdiv.h, x4, x14, x17, dyn, 0, 0, x10, 14*FLEN/8, x19, x15, x9) + +inst_8: +// rs1==x28, rs2==x6, rd==x31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x28; op2:x6; dest:x31; op1val:0x0; op2val:0x401; + valaddr_reg:x10; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fdiv.h, x31, x28, x6, dyn, 0, 0, x10, 16*FLEN/8, x19, x15, x9) + +inst_9: +// rs1==x0, rs2==x23, rd==x6,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x0; op2:x23; dest:x6; op1val:0x0; op2val:0x8401; + valaddr_reg:x10; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fdiv.h, x6, x0, x23, dyn, 0, 0, x10, 18*FLEN/8, x19, x15, x9) + +inst_10: +// rs1==x13, rs2==x2, rd==x1,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x13; op2:x2; dest:x1; op1val:0x0; op2val:0x455; + valaddr_reg:x10; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fdiv.h, x1, x13, x2, dyn, 0, 0, x10, 20*FLEN/8, x19, x15, x9) +RVTEST_VALBASEUPD(x1,test_dataset_1) + +inst_11: +// rs1==x18, rs2==x21, rd==x3,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x18; op2:x21; dest:x3; op1val:0x0; op2val:0x8455; + valaddr_reg:x1; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fdiv.h, x3, x18, x21, dyn, 0, 0, x1, 0*FLEN/8, x6, x15, x9) + +inst_12: +// rs1==x10, rs2==x5, rd==x16,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x10; op2:x5; dest:x16; op1val:0x0; op2val:0x4aa; + valaddr_reg:x1; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fdiv.h, x16, x10, x5, dyn, 0, 0, x1, 2*FLEN/8, x6, x15, x9) + +inst_13: +// rs1==x22, rs2==x0, rd==x21,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x22; op2:x0; dest:x21; op1val:0x0; op2val:0x0; + valaddr_reg:x1; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fdiv.h, x21, x22, x0, dyn, 0, 0, x1, 4*FLEN/8, x6, x15, x9) + +inst_14: +// rs1==x19, rs2==x13, rd==x14,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x19; op2:x13; dest:x14; op1val:0x0; op2val:0x5400; + valaddr_reg:x1; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fdiv.h, x14, x19, x13, dyn, 0, 0, x1, 6*FLEN/8, x6, x15, x9) + +inst_15: +// rs1==x9, rs2==x7, rd==x23,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x15 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x9; op2:x7; dest:x23; op1val:0x0; op2val:0xd400; + valaddr_reg:x1; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fdiv.h, x23, x9, x7, dyn, 0, 0, x1, 8*FLEN/8, x6, x15, x8) +RVTEST_SIGBASE(x5,signature_x5_0) + +inst_16: +// rs1==x4, rs2==x25, rd==x26,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x4; op2:x25; dest:x26; op1val:0x0; op2val:0x2800; + valaddr_reg:x1; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fdiv.h, x26, x4, x25, dyn, 0, 0, x1, 10*FLEN/8, x6, x5, x8) + +inst_17: +// rs1==x29, rs2==x30, rd==x19,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x29; op2:x30; dest:x19; op1val:0x0; op2val:0xa800; + valaddr_reg:x1; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fdiv.h, x19, x29, x30, dyn, 0, 0, x1, 12*FLEN/8, x6, x5, x8) + +inst_18: +// rs1==x2, rs2==x14, rd==x13,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x2; op2:x14; dest:x13; op1val:0x0; op2val:0x7c00; + valaddr_reg:x1; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fdiv.h, x13, x2, x14, dyn, 0, 0, x1, 14*FLEN/8, x6, x5, x8) + +inst_19: +// rs1==x27, rs2==x26, rd==x2,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x27; op2:x26; dest:x2; op1val:0x0; op2val:0xfc00; + valaddr_reg:x1; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fdiv.h, x2, x27, x26, dyn, 0, 0, x1, 16*FLEN/8, x6, x5, x8) + +inst_20: +// rs1==x20, rs2==x11, rd==x28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x20; op2:x11; dest:x28; op1val:0x0; op2val:0x7e00; + valaddr_reg:x1; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fdiv.h, x28, x20, x11, dyn, 0, 0, x1, 18*FLEN/8, x6, x5, x8) +RVTEST_VALBASEUPD(x11,test_dataset_2) + +inst_21: +// rs1==x24, rs2==x1, rd==x17,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x24; op2:x1; dest:x17; op1val:0x0; op2val:0xfe00; + valaddr_reg:x11; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fdiv.h, x17, x24, x1, dyn, 0, 0, x11, 0*FLEN/8, x13, x5, x8) + +inst_22: +// rs1==x17, rs2==x24, rd==x25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x17; op2:x24; dest:x25; op1val:0x0; op2val:0x7e01; + valaddr_reg:x11; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fdiv.h, x25, x17, x24, dyn, 0, 0, x11, 2*FLEN/8, x13, x5, x8) + +inst_23: +// rs1==x25, rs2==x15, rd==x18,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x25; op2:x15; dest:x18; op1val:0x0; op2val:0xfe55; + valaddr_reg:x11; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fdiv.h, x18, x25, x15, dyn, 0, 0, x11, 4*FLEN/8, x13, x5, x8) + +inst_24: +// rs1==x6, rs2==x10, rd==x29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x6; op2:x10; dest:x29; op1val:0x0; op2val:0x7c01; + valaddr_reg:x11; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fdiv.h, x29, x6, x10, dyn, 0, 0, x11, 6*FLEN/8, x13, x5, x8) + +inst_25: +// rs1==x26, rs2==x27, rd==x9,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x26; op2:x27; dest:x9; op1val:0x0; op2val:0xfd55; + valaddr_reg:x11; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fdiv.h, x9, x26, x27, dyn, 0, 0, x11, 8*FLEN/8, x13, x5, x8) + +inst_26: +// rs1==x23, rs2==x16, rd==x7,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x23; op2:x16; dest:x7; op1val:0x8000; op2val:0x0; + valaddr_reg:x11; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fdiv.h, x7, x23, x16, dyn, 0, 0, x11, 10*FLEN/8, x13, x5, x8) + +inst_27: +// rs1==x3, rs2==x29, rd==x20,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x3; op2:x29; dest:x20; op1val:0x8000; op2val:0x8000; + valaddr_reg:x11; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fdiv.h, x20, x3, x29, dyn, 0, 0, x11, 12*FLEN/8, x13, x5, x8) + +inst_28: +// rs1==x15, rs2==x9, rd==x27,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x15; op2:x9; dest:x27; op1val:0x8000; op2val:0x2; + valaddr_reg:x11; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x27, x15, x9, dyn, 0, 0, x11, 14*FLEN/8, x13, x5, x2) + +inst_29: +// rs1==x30, rs2==x28, rd==x15,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x28; dest:x15; op1val:0x8000; op2val:0x8002; + valaddr_reg:x11; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x15, x30, x28, dyn, 0, 0, x11, 16*FLEN/8, x13, x5, x2) + +inst_30: +// rs1==x12, rs2==x19, rd==x10,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x12; op2:x19; dest:x10; op1val:0x8000; op2val:0x3fe; + valaddr_reg:x11; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x10, x12, x19, dyn, 0, 0, x11, 18*FLEN/8, x13, x5, x2) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_31: +// rs1==x5, rs2==x4, rd==x22,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x5; op2:x4; dest:x22; op1val:0x8000; op2val:0x83fe; + valaddr_reg:x11; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x22, x5, x4, dyn, 0, 0, x11, 20*FLEN/8, x13, x1, x2) +RVTEST_VALBASEUPD(x3,test_dataset_3) + +inst_32: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x2aa; + valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_33: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x82aa; + valaddr_reg:x3; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_34: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x401; + valaddr_reg:x3; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_35: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8401; + valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_36: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x455; + valaddr_reg:x3; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_37: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8455; + valaddr_reg:x3; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_38: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x4aa; + valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_39: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x84aa; + valaddr_reg:x3; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_40: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x5400; + valaddr_reg:x3; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_41: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x15 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xd400; + valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_42: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x2800; + valaddr_reg:x3; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_43: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xa800; + valaddr_reg:x3; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_44: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x7c00; + valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_45: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xfc00; + valaddr_reg:x3; val_offset:26*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_46: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x7e00; + valaddr_reg:x3; val_offset:28*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_47: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xfe00; + valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_48: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x7e01; + valaddr_reg:x3; val_offset:32*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 32*FLEN/8, x4, x1, x2) + +inst_49: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xfe55; + valaddr_reg:x3; val_offset:34*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 34*FLEN/8, x4, x1, x2) + +inst_50: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x7c01; + valaddr_reg:x3; val_offset:36*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 36*FLEN/8, x4, x1, x2) + +inst_51: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xfd55; + valaddr_reg:x3; val_offset:38*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 38*FLEN/8, x4, x1, x2) + +inst_52: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x0; + valaddr_reg:x3; val_offset:40*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 40*FLEN/8, x4, x1, x2) + +inst_53: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x8000; + valaddr_reg:x3; val_offset:42*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 42*FLEN/8, x4, x1, x2) + +inst_54: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x2; + valaddr_reg:x3; val_offset:44*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 44*FLEN/8, x4, x1, x2) + +inst_55: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x8002; + valaddr_reg:x3; val_offset:46*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 46*FLEN/8, x4, x1, x2) + +inst_56: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x3fe; + valaddr_reg:x3; val_offset:48*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 48*FLEN/8, x4, x1, x2) + +inst_57: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x83fe; + valaddr_reg:x3; val_offset:50*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 50*FLEN/8, x4, x1, x2) + +inst_58: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x2aa; + valaddr_reg:x3; val_offset:52*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 52*FLEN/8, x4, x1, x2) + +inst_59: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x82aa; + valaddr_reg:x3; val_offset:54*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 54*FLEN/8, x4, x1, x2) + +inst_60: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x401; + valaddr_reg:x3; val_offset:56*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 56*FLEN/8, x4, x1, x2) + +inst_61: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x8401; + valaddr_reg:x3; val_offset:58*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 58*FLEN/8, x4, x1, x2) + +inst_62: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x455; + valaddr_reg:x3; val_offset:60*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 60*FLEN/8, x4, x1, x2) + +inst_63: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x8455; + valaddr_reg:x3; val_offset:62*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 62*FLEN/8, x4, x1, x2) + +inst_64: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x4aa; + valaddr_reg:x3; val_offset:64*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 64*FLEN/8, x4, x1, x2) + +inst_65: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x84aa; + valaddr_reg:x3; val_offset:66*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 66*FLEN/8, x4, x1, x2) + +inst_66: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x5400; + valaddr_reg:x3; val_offset:68*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 68*FLEN/8, x4, x1, x2) + +inst_67: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x15 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xd400; + valaddr_reg:x3; val_offset:70*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 70*FLEN/8, x4, x1, x2) + +inst_68: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x2800; + valaddr_reg:x3; val_offset:72*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 72*FLEN/8, x4, x1, x2) + +inst_69: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xa800; + valaddr_reg:x3; val_offset:74*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 74*FLEN/8, x4, x1, x2) + +inst_70: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x7c00; + valaddr_reg:x3; val_offset:76*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 76*FLEN/8, x4, x1, x2) + +inst_71: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xfc00; + valaddr_reg:x3; val_offset:78*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 78*FLEN/8, x4, x1, x2) + +inst_72: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x7e00; + valaddr_reg:x3; val_offset:80*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 80*FLEN/8, x4, x1, x2) + +inst_73: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xfe00; + valaddr_reg:x3; val_offset:82*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 82*FLEN/8, x4, x1, x2) + +inst_74: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x7e01; + valaddr_reg:x3; val_offset:84*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 84*FLEN/8, x4, x1, x2) + +inst_75: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xfe55; + valaddr_reg:x3; val_offset:86*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 86*FLEN/8, x4, x1, x2) + +inst_76: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x7c01; + valaddr_reg:x3; val_offset:88*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 88*FLEN/8, x4, x1, x2) + +inst_77: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xfd55; + valaddr_reg:x3; val_offset:90*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 90*FLEN/8, x4, x1, x2) + +inst_78: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8002; op2val:0x0; + valaddr_reg:x3; val_offset:92*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 92*FLEN/8, x4, x1, x2) + +inst_79: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8002; op2val:0x8000; + valaddr_reg:x3; val_offset:94*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 94*FLEN/8, x4, x1, x2) + +inst_80: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8002; op2val:0x2; + valaddr_reg:x3; val_offset:96*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 96*FLEN/8, x4, x1, x2) + +inst_81: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8002; op2val:0x8002; + valaddr_reg:x3; val_offset:98*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 98*FLEN/8, x4, x1, x2) + +inst_82: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8002; op2val:0x3fe; + valaddr_reg:x3; val_offset:100*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 100*FLEN/8, x4, x1, x2) + +inst_83: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8002; op2val:0x83fe; + valaddr_reg:x3; val_offset:102*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 102*FLEN/8, x4, x1, x2) + +inst_84: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8002; op2val:0x2aa; + valaddr_reg:x3; val_offset:104*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 104*FLEN/8, x4, x1, x2) + +inst_85: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8002; op2val:0x82aa; + valaddr_reg:x3; val_offset:106*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 106*FLEN/8, x4, x1, x2) + +inst_86: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8002; op2val:0x401; + valaddr_reg:x3; val_offset:108*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 108*FLEN/8, x4, x1, x2) + +inst_87: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8002; op2val:0x8401; + valaddr_reg:x3; val_offset:110*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 110*FLEN/8, x4, x1, x2) + +inst_88: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8002; op2val:0x455; + valaddr_reg:x3; val_offset:112*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 112*FLEN/8, x4, x1, x2) + +inst_89: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8002; op2val:0x8455; + valaddr_reg:x3; val_offset:114*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 114*FLEN/8, x4, x1, x2) + +inst_90: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8002; op2val:0x4aa; + valaddr_reg:x3; val_offset:116*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 116*FLEN/8, x4, x1, x2) + +inst_91: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8002; op2val:0x84aa; + valaddr_reg:x3; val_offset:118*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 118*FLEN/8, x4, x1, x2) + +inst_92: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8002; op2val:0x5400; + valaddr_reg:x3; val_offset:120*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 120*FLEN/8, x4, x1, x2) + +inst_93: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x15 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8002; op2val:0xd400; + valaddr_reg:x3; val_offset:122*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 122*FLEN/8, x4, x1, x2) + +inst_94: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8002; op2val:0x2800; + valaddr_reg:x3; val_offset:124*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 124*FLEN/8, x4, x1, x2) + +inst_95: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8002; op2val:0xa800; + valaddr_reg:x3; val_offset:126*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 126*FLEN/8, x4, x1, x2) + +inst_96: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8002; op2val:0x7c00; + valaddr_reg:x3; val_offset:128*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 128*FLEN/8, x4, x1, x2) + +inst_97: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8002; op2val:0xfc00; + valaddr_reg:x3; val_offset:130*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 130*FLEN/8, x4, x1, x2) + +inst_98: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8002; op2val:0x7e00; + valaddr_reg:x3; val_offset:132*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 132*FLEN/8, x4, x1, x2) + +inst_99: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8002; op2val:0xfe00; + valaddr_reg:x3; val_offset:134*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 134*FLEN/8, x4, x1, x2) + +inst_100: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8002; op2val:0x7e01; + valaddr_reg:x3; val_offset:136*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 136*FLEN/8, x4, x1, x2) + +inst_101: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8002; op2val:0xfe55; + valaddr_reg:x3; val_offset:138*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 138*FLEN/8, x4, x1, x2) + +inst_102: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8002; op2val:0x7c01; + valaddr_reg:x3; val_offset:140*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 140*FLEN/8, x4, x1, x2) + +inst_103: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8002; op2val:0xfd55; + valaddr_reg:x3; val_offset:142*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 142*FLEN/8, x4, x1, x2) + +inst_104: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fe; op2val:0x0; + valaddr_reg:x3; val_offset:144*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 144*FLEN/8, x4, x1, x2) + +inst_105: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fe; op2val:0x8000; + valaddr_reg:x3; val_offset:146*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 146*FLEN/8, x4, x1, x2) + +inst_106: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fe; op2val:0x2; + valaddr_reg:x3; val_offset:148*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 148*FLEN/8, x4, x1, x2) + +inst_107: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fe; op2val:0x8002; + valaddr_reg:x3; val_offset:150*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 150*FLEN/8, x4, x1, x2) + +inst_108: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fe; op2val:0x3fe; + valaddr_reg:x3; val_offset:152*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 152*FLEN/8, x4, x1, x2) + +inst_109: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fe; op2val:0x83fe; + valaddr_reg:x3; val_offset:154*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 154*FLEN/8, x4, x1, x2) + +inst_110: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fe; op2val:0x2aa; + valaddr_reg:x3; val_offset:156*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 156*FLEN/8, x4, x1, x2) + +inst_111: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fe; op2val:0x82aa; + valaddr_reg:x3; val_offset:158*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 158*FLEN/8, x4, x1, x2) + +inst_112: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fe; op2val:0x401; + valaddr_reg:x3; val_offset:160*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 160*FLEN/8, x4, x1, x2) + +inst_113: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fe; op2val:0x8401; + valaddr_reg:x3; val_offset:162*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 162*FLEN/8, x4, x1, x2) + +inst_114: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fe; op2val:0x455; + valaddr_reg:x3; val_offset:164*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 164*FLEN/8, x4, x1, x2) + +inst_115: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fe; op2val:0x8455; + valaddr_reg:x3; val_offset:166*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 166*FLEN/8, x4, x1, x2) + +inst_116: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fe; op2val:0x4aa; + valaddr_reg:x3; val_offset:168*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 168*FLEN/8, x4, x1, x2) + +inst_117: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fe; op2val:0x84aa; + valaddr_reg:x3; val_offset:170*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 170*FLEN/8, x4, x1, x2) + +inst_118: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x15 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fe; op2val:0x5400; + valaddr_reg:x3; val_offset:172*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 172*FLEN/8, x4, x1, x2) + +inst_119: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x15 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fe; op2val:0xd400; + valaddr_reg:x3; val_offset:174*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 174*FLEN/8, x4, x1, x2) + +inst_120: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0a and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fe; op2val:0x2800; + valaddr_reg:x3; val_offset:176*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 176*FLEN/8, x4, x1, x2) + +inst_121: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0a and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fe; op2val:0xa800; + valaddr_reg:x3; val_offset:178*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 178*FLEN/8, x4, x1, x2) + +inst_122: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fe; op2val:0x7c00; + valaddr_reg:x3; val_offset:180*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 180*FLEN/8, x4, x1, x2) + +inst_123: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fe; op2val:0xfc00; + valaddr_reg:x3; val_offset:182*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 182*FLEN/8, x4, x1, x2) + +inst_124: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fe; op2val:0x7e00; + valaddr_reg:x3; val_offset:184*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 184*FLEN/8, x4, x1, x2) + +inst_125: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fe; op2val:0xfe00; + valaddr_reg:x3; val_offset:186*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 186*FLEN/8, x4, x1, x2) + +inst_126: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fe; op2val:0x7e01; + valaddr_reg:x3; val_offset:188*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 188*FLEN/8, x4, x1, x2) + +inst_127: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fe; op2val:0xfe55; + valaddr_reg:x3; val_offset:190*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 190*FLEN/8, x4, x1, x2) + +inst_128: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fe; op2val:0x7c01; + valaddr_reg:x3; val_offset:192*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 192*FLEN/8, x4, x1, x2) + +inst_129: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fe; op2val:0xfd55; + valaddr_reg:x3; val_offset:194*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 194*FLEN/8, x4, x1, x2) + +inst_130: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x0; + valaddr_reg:x3; val_offset:196*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 196*FLEN/8, x4, x1, x2) + +inst_131: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x8000; + valaddr_reg:x3; val_offset:198*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 198*FLEN/8, x4, x1, x2) + +inst_132: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x2; + valaddr_reg:x3; val_offset:200*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 200*FLEN/8, x4, x1, x2) + +inst_133: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x8002; + valaddr_reg:x3; val_offset:202*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 202*FLEN/8, x4, x1, x2) + +inst_134: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x3fe; + valaddr_reg:x3; val_offset:204*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 204*FLEN/8, x4, x1, x2) + +inst_135: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x83fe; + valaddr_reg:x3; val_offset:206*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 206*FLEN/8, x4, x1, x2) + +inst_136: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x2aa; + valaddr_reg:x3; val_offset:208*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 208*FLEN/8, x4, x1, x2) + +inst_137: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x82aa; + valaddr_reg:x3; val_offset:210*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 210*FLEN/8, x4, x1, x2) + +inst_138: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x401; + valaddr_reg:x3; val_offset:212*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 212*FLEN/8, x4, x1, x2) + +inst_139: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x8401; + valaddr_reg:x3; val_offset:214*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 214*FLEN/8, x4, x1, x2) + +inst_140: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x455; + valaddr_reg:x3; val_offset:216*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 216*FLEN/8, x4, x1, x2) + +inst_141: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x8455; + valaddr_reg:x3; val_offset:218*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 218*FLEN/8, x4, x1, x2) + +inst_142: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x4aa; + valaddr_reg:x3; val_offset:220*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 220*FLEN/8, x4, x1, x2) + +inst_143: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x84aa; + valaddr_reg:x3; val_offset:222*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 222*FLEN/8, x4, x1, x2) + +inst_144: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x15 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x5400; + valaddr_reg:x3; val_offset:224*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 224*FLEN/8, x4, x1, x2) + +inst_145: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x15 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xd400; + valaddr_reg:x3; val_offset:226*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 226*FLEN/8, x4, x1, x2) + +inst_146: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0a and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x2800; + valaddr_reg:x3; val_offset:228*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 228*FLEN/8, x4, x1, x2) + +inst_147: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0a and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xa800; + valaddr_reg:x3; val_offset:230*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 230*FLEN/8, x4, x1, x2) + +inst_148: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x7c00; + valaddr_reg:x3; val_offset:232*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 232*FLEN/8, x4, x1, x2) + +inst_149: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xfc00; + valaddr_reg:x3; val_offset:234*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 234*FLEN/8, x4, x1, x2) + +inst_150: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x7e00; + valaddr_reg:x3; val_offset:236*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 236*FLEN/8, x4, x1, x2) + +inst_151: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xfe00; + valaddr_reg:x3; val_offset:238*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 238*FLEN/8, x4, x1, x2) + +inst_152: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x7e01; + valaddr_reg:x3; val_offset:240*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 240*FLEN/8, x4, x1, x2) + +inst_153: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xfe55; + valaddr_reg:x3; val_offset:242*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 242*FLEN/8, x4, x1, x2) + +inst_154: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x7c01; + valaddr_reg:x3; val_offset:244*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 244*FLEN/8, x4, x1, x2) + +inst_155: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xfd55; + valaddr_reg:x3; val_offset:246*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 246*FLEN/8, x4, x1, x2) + +inst_156: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2aa; op2val:0x0; + valaddr_reg:x3; val_offset:248*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 248*FLEN/8, x4, x1, x2) + +inst_157: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2aa; op2val:0x8000; + valaddr_reg:x3; val_offset:250*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 250*FLEN/8, x4, x1, x2) + +inst_158: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2aa; op2val:0x2; + valaddr_reg:x3; val_offset:252*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 252*FLEN/8, x4, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_159: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2aa; op2val:0x8002; + valaddr_reg:x3; val_offset:254*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 254*FLEN/8, x4, x1, x2) + +inst_160: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2aa; op2val:0x3fe; + valaddr_reg:x3; val_offset:256*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 256*FLEN/8, x4, x1, x2) + +inst_161: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2aa; op2val:0x83fe; + valaddr_reg:x3; val_offset:258*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 258*FLEN/8, x4, x1, x2) + +inst_162: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2aa; op2val:0x2aa; + valaddr_reg:x3; val_offset:260*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 260*FLEN/8, x4, x1, x2) + +inst_163: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2aa; op2val:0x82aa; + valaddr_reg:x3; val_offset:262*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 262*FLEN/8, x4, x1, x2) + +inst_164: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2aa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2aa; op2val:0x401; + valaddr_reg:x3; val_offset:264*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 264*FLEN/8, x4, x1, x2) + +inst_165: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2aa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2aa; op2val:0x8401; + valaddr_reg:x3; val_offset:266*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 266*FLEN/8, x4, x1, x2) + +inst_166: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2aa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2aa; op2val:0x455; + valaddr_reg:x3; val_offset:268*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 268*FLEN/8, x4, x1, x2) + +inst_167: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2aa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2aa; op2val:0x8455; + valaddr_reg:x3; val_offset:270*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 270*FLEN/8, x4, x1, x2) + +inst_168: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2aa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2aa; op2val:0x4aa; + valaddr_reg:x3; val_offset:272*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 272*FLEN/8, x4, x1, x2) + +inst_169: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2aa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2aa; op2val:0x84aa; + valaddr_reg:x3; val_offset:274*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 274*FLEN/8, x4, x1, x2) + +inst_170: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2aa and fs2 == 0 and fe2 == 0x15 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2aa; op2val:0x5400; + valaddr_reg:x3; val_offset:276*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 276*FLEN/8, x4, x1, x2) + +inst_171: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2aa and fs2 == 1 and fe2 == 0x15 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2aa; op2val:0xd400; + valaddr_reg:x3; val_offset:278*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 278*FLEN/8, x4, x1, x2) + +inst_172: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2aa and fs2 == 0 and fe2 == 0x0a and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2aa; op2val:0x2800; + valaddr_reg:x3; val_offset:280*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 280*FLEN/8, x4, x1, x2) + +inst_173: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2aa and fs2 == 1 and fe2 == 0x0a and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2aa; op2val:0xa800; + valaddr_reg:x3; val_offset:282*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 282*FLEN/8, x4, x1, x2) + +inst_174: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2aa and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2aa; op2val:0x7c00; + valaddr_reg:x3; val_offset:284*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 284*FLEN/8, x4, x1, x2) + +inst_175: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2aa and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2aa; op2val:0xfc00; + valaddr_reg:x3; val_offset:286*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 286*FLEN/8, x4, x1, x2) + +inst_176: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2aa and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2aa; op2val:0x7e00; + valaddr_reg:x3; val_offset:288*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 288*FLEN/8, x4, x1, x2) + +inst_177: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2aa and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2aa; op2val:0xfe00; + valaddr_reg:x3; val_offset:290*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 290*FLEN/8, x4, x1, x2) + +inst_178: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2aa and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2aa; op2val:0x7e01; + valaddr_reg:x3; val_offset:292*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 292*FLEN/8, x4, x1, x2) + +inst_179: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2aa and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2aa; op2val:0xfe55; + valaddr_reg:x3; val_offset:294*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 294*FLEN/8, x4, x1, x2) + +inst_180: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2aa and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2aa; op2val:0x7c01; + valaddr_reg:x3; val_offset:296*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 296*FLEN/8, x4, x1, x2) + +inst_181: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2aa and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2aa; op2val:0xfd55; + valaddr_reg:x3; val_offset:298*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 298*FLEN/8, x4, x1, x2) + +inst_182: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x82aa; op2val:0x0; + valaddr_reg:x3; val_offset:300*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 300*FLEN/8, x4, x1, x2) + +inst_183: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x82aa; op2val:0x8000; + valaddr_reg:x3; val_offset:302*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 302*FLEN/8, x4, x1, x2) + +inst_184: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x82aa; op2val:0x2; + valaddr_reg:x3; val_offset:304*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 304*FLEN/8, x4, x1, x2) + +inst_185: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x82aa; op2val:0x8002; + valaddr_reg:x3; val_offset:306*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 306*FLEN/8, x4, x1, x2) + +inst_186: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x82aa; op2val:0x3fe; + valaddr_reg:x3; val_offset:308*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 308*FLEN/8, x4, x1, x2) + +inst_187: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x82aa; op2val:0x83fe; + valaddr_reg:x3; val_offset:310*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 310*FLEN/8, x4, x1, x2) + +inst_188: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x82aa; op2val:0x2aa; + valaddr_reg:x3; val_offset:312*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 312*FLEN/8, x4, x1, x2) + +inst_189: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x82aa; op2val:0x82aa; + valaddr_reg:x3; val_offset:314*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 314*FLEN/8, x4, x1, x2) + +inst_190: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2aa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x82aa; op2val:0x401; + valaddr_reg:x3; val_offset:316*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 316*FLEN/8, x4, x1, x2) + +inst_191: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2aa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x82aa; op2val:0x8401; + valaddr_reg:x3; val_offset:318*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 318*FLEN/8, x4, x1, x2) + +inst_192: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2aa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x82aa; op2val:0x455; + valaddr_reg:x3; val_offset:320*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 320*FLEN/8, x4, x1, x2) + +inst_193: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2aa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x82aa; op2val:0x8455; + valaddr_reg:x3; val_offset:322*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 322*FLEN/8, x4, x1, x2) + +inst_194: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2aa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x82aa; op2val:0x4aa; + valaddr_reg:x3; val_offset:324*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 324*FLEN/8, x4, x1, x2) + +inst_195: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2aa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x82aa; op2val:0x84aa; + valaddr_reg:x3; val_offset:326*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 326*FLEN/8, x4, x1, x2) + +inst_196: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2aa and fs2 == 0 and fe2 == 0x15 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x82aa; op2val:0x5400; + valaddr_reg:x3; val_offset:328*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 328*FLEN/8, x4, x1, x2) + +inst_197: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2aa and fs2 == 1 and fe2 == 0x15 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x82aa; op2val:0xd400; + valaddr_reg:x3; val_offset:330*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 330*FLEN/8, x4, x1, x2) + +inst_198: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2aa and fs2 == 0 and fe2 == 0x0a and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x82aa; op2val:0x2800; + valaddr_reg:x3; val_offset:332*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 332*FLEN/8, x4, x1, x2) + +inst_199: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2aa and fs2 == 1 and fe2 == 0x0a and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x82aa; op2val:0xa800; + valaddr_reg:x3; val_offset:334*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 334*FLEN/8, x4, x1, x2) + +inst_200: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2aa and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x82aa; op2val:0x7c00; + valaddr_reg:x3; val_offset:336*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 336*FLEN/8, x4, x1, x2) + +inst_201: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2aa and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x82aa; op2val:0xfc00; + valaddr_reg:x3; val_offset:338*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 338*FLEN/8, x4, x1, x2) + +inst_202: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2aa and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x82aa; op2val:0x7e00; + valaddr_reg:x3; val_offset:340*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 340*FLEN/8, x4, x1, x2) + +inst_203: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2aa and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x82aa; op2val:0xfe00; + valaddr_reg:x3; val_offset:342*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 342*FLEN/8, x4, x1, x2) + +inst_204: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2aa and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x82aa; op2val:0x7e01; + valaddr_reg:x3; val_offset:344*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 344*FLEN/8, x4, x1, x2) + +inst_205: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2aa and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x82aa; op2val:0xfe55; + valaddr_reg:x3; val_offset:346*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 346*FLEN/8, x4, x1, x2) + +inst_206: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2aa and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x82aa; op2val:0x7c01; + valaddr_reg:x3; val_offset:348*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 348*FLEN/8, x4, x1, x2) + +inst_207: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2aa and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x82aa; op2val:0xfd55; + valaddr_reg:x3; val_offset:350*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 350*FLEN/8, x4, x1, x2) + +inst_208: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x0; + valaddr_reg:x3; val_offset:352*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 352*FLEN/8, x4, x1, x2) + +inst_209: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x8000; + valaddr_reg:x3; val_offset:354*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 354*FLEN/8, x4, x1, x2) + +inst_210: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x2; + valaddr_reg:x3; val_offset:356*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 356*FLEN/8, x4, x1, x2) + +inst_211: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x8002; + valaddr_reg:x3; val_offset:358*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 358*FLEN/8, x4, x1, x2) + +inst_212: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x3fe; + valaddr_reg:x3; val_offset:360*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 360*FLEN/8, x4, x1, x2) + +inst_213: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x83fe; + valaddr_reg:x3; val_offset:362*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 362*FLEN/8, x4, x1, x2) + +inst_214: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x2aa; + valaddr_reg:x3; val_offset:364*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 364*FLEN/8, x4, x1, x2) + +inst_215: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x82aa; + valaddr_reg:x3; val_offset:366*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 366*FLEN/8, x4, x1, x2) + +inst_216: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x401; + valaddr_reg:x3; val_offset:368*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 368*FLEN/8, x4, x1, x2) + +inst_217: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x8401; + valaddr_reg:x3; val_offset:370*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 370*FLEN/8, x4, x1, x2) + +inst_218: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x455; + valaddr_reg:x3; val_offset:372*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 372*FLEN/8, x4, x1, x2) + +inst_219: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x8455; + valaddr_reg:x3; val_offset:374*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 374*FLEN/8, x4, x1, x2) + +inst_220: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x4aa; + valaddr_reg:x3; val_offset:376*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 376*FLEN/8, x4, x1, x2) + +inst_221: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x84aa; + valaddr_reg:x3; val_offset:378*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 378*FLEN/8, x4, x1, x2) + +inst_222: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x5400; + valaddr_reg:x3; val_offset:380*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 380*FLEN/8, x4, x1, x2) + +inst_223: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x15 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xd400; + valaddr_reg:x3; val_offset:382*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 382*FLEN/8, x4, x1, x2) + +inst_224: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x2800; + valaddr_reg:x3; val_offset:384*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 384*FLEN/8, x4, x1, x2) + +inst_225: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xa800; + valaddr_reg:x3; val_offset:386*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 386*FLEN/8, x4, x1, x2) + +inst_226: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x7c00; + valaddr_reg:x3; val_offset:388*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 388*FLEN/8, x4, x1, x2) + +inst_227: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xfc00; + valaddr_reg:x3; val_offset:390*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 390*FLEN/8, x4, x1, x2) + +inst_228: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x7e00; + valaddr_reg:x3; val_offset:392*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 392*FLEN/8, x4, x1, x2) + +inst_229: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xfe00; + valaddr_reg:x3; val_offset:394*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 394*FLEN/8, x4, x1, x2) + +inst_230: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x7e01; + valaddr_reg:x3; val_offset:396*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 396*FLEN/8, x4, x1, x2) + +inst_231: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xfe55; + valaddr_reg:x3; val_offset:398*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 398*FLEN/8, x4, x1, x2) + +inst_232: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x7c01; + valaddr_reg:x3; val_offset:400*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 400*FLEN/8, x4, x1, x2) + +inst_233: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xfd55; + valaddr_reg:x3; val_offset:402*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 402*FLEN/8, x4, x1, x2) + +inst_234: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8401; op2val:0x0; + valaddr_reg:x3; val_offset:404*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 404*FLEN/8, x4, x1, x2) + +inst_235: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8401; op2val:0x8000; + valaddr_reg:x3; val_offset:406*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 406*FLEN/8, x4, x1, x2) + +inst_236: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8401; op2val:0x2; + valaddr_reg:x3; val_offset:408*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 408*FLEN/8, x4, x1, x2) + +inst_237: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8401; op2val:0x8002; + valaddr_reg:x3; val_offset:410*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 410*FLEN/8, x4, x1, x2) + +inst_238: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8401; op2val:0x3fe; + valaddr_reg:x3; val_offset:412*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 412*FLEN/8, x4, x1, x2) + +inst_239: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8401; op2val:0x83fe; + valaddr_reg:x3; val_offset:414*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 414*FLEN/8, x4, x1, x2) + +inst_240: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8401; op2val:0x2aa; + valaddr_reg:x3; val_offset:416*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 416*FLEN/8, x4, x1, x2) + +inst_241: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8401; op2val:0x82aa; + valaddr_reg:x3; val_offset:418*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 418*FLEN/8, x4, x1, x2) + +inst_242: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8401; op2val:0x401; + valaddr_reg:x3; val_offset:420*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 420*FLEN/8, x4, x1, x2) + +inst_243: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8401; op2val:0x8401; + valaddr_reg:x3; val_offset:422*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 422*FLEN/8, x4, x1, x2) + +inst_244: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8401; op2val:0x455; + valaddr_reg:x3; val_offset:424*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 424*FLEN/8, x4, x1, x2) + +inst_245: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8401; op2val:0x8455; + valaddr_reg:x3; val_offset:426*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 426*FLEN/8, x4, x1, x2) + +inst_246: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8401; op2val:0x4aa; + valaddr_reg:x3; val_offset:428*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 428*FLEN/8, x4, x1, x2) + +inst_247: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8401; op2val:0x84aa; + valaddr_reg:x3; val_offset:430*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 430*FLEN/8, x4, x1, x2) + +inst_248: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8401; op2val:0x5400; + valaddr_reg:x3; val_offset:432*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 432*FLEN/8, x4, x1, x2) + +inst_249: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x15 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8401; op2val:0xd400; + valaddr_reg:x3; val_offset:434*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 434*FLEN/8, x4, x1, x2) + +inst_250: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8401; op2val:0x2800; + valaddr_reg:x3; val_offset:436*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 436*FLEN/8, x4, x1, x2) + +inst_251: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8401; op2val:0xa800; + valaddr_reg:x3; val_offset:438*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 438*FLEN/8, x4, x1, x2) + +inst_252: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8401; op2val:0x7c00; + valaddr_reg:x3; val_offset:440*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 440*FLEN/8, x4, x1, x2) + +inst_253: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8401; op2val:0xfc00; + valaddr_reg:x3; val_offset:442*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 442*FLEN/8, x4, x1, x2) + +inst_254: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8401; op2val:0x7e00; + valaddr_reg:x3; val_offset:444*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 444*FLEN/8, x4, x1, x2) + +inst_255: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8401; op2val:0xfe00; + valaddr_reg:x3; val_offset:446*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 446*FLEN/8, x4, x1, x2) + +inst_256: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8401; op2val:0x7e01; + valaddr_reg:x3; val_offset:448*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 448*FLEN/8, x4, x1, x2) + +inst_257: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8401; op2val:0xfe55; + valaddr_reg:x3; val_offset:450*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 450*FLEN/8, x4, x1, x2) + +inst_258: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8401; op2val:0x7c01; + valaddr_reg:x3; val_offset:452*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 452*FLEN/8, x4, x1, x2) + +inst_259: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8401; op2val:0xfd55; + valaddr_reg:x3; val_offset:454*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 454*FLEN/8, x4, x1, x2) + +inst_260: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x455; op2val:0x0; + valaddr_reg:x3; val_offset:456*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 456*FLEN/8, x4, x1, x2) + +inst_261: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x455; op2val:0x8000; + valaddr_reg:x3; val_offset:458*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 458*FLEN/8, x4, x1, x2) + +inst_262: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x455; op2val:0x2; + valaddr_reg:x3; val_offset:460*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 460*FLEN/8, x4, x1, x2) + +inst_263: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x455; op2val:0x8002; + valaddr_reg:x3; val_offset:462*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 462*FLEN/8, x4, x1, x2) + +inst_264: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x455; op2val:0x3fe; + valaddr_reg:x3; val_offset:464*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 464*FLEN/8, x4, x1, x2) + +inst_265: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x455; op2val:0x83fe; + valaddr_reg:x3; val_offset:466*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 466*FLEN/8, x4, x1, x2) + +inst_266: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x455; op2val:0x2aa; + valaddr_reg:x3; val_offset:468*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 468*FLEN/8, x4, x1, x2) + +inst_267: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x455; op2val:0x82aa; + valaddr_reg:x3; val_offset:470*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 470*FLEN/8, x4, x1, x2) + +inst_268: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x455; op2val:0x401; + valaddr_reg:x3; val_offset:472*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 472*FLEN/8, x4, x1, x2) + +inst_269: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x455; op2val:0x8401; + valaddr_reg:x3; val_offset:474*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 474*FLEN/8, x4, x1, x2) + +inst_270: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x455; op2val:0x455; + valaddr_reg:x3; val_offset:476*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 476*FLEN/8, x4, x1, x2) + +inst_271: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x455; op2val:0x8455; + valaddr_reg:x3; val_offset:478*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 478*FLEN/8, x4, x1, x2) + +inst_272: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x455; op2val:0x4aa; + valaddr_reg:x3; val_offset:480*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 480*FLEN/8, x4, x1, x2) + +inst_273: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x455; op2val:0x84aa; + valaddr_reg:x3; val_offset:482*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 482*FLEN/8, x4, x1, x2) + +inst_274: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x455; op2val:0x5400; + valaddr_reg:x3; val_offset:484*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 484*FLEN/8, x4, x1, x2) + +inst_275: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x15 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x455; op2val:0xd400; + valaddr_reg:x3; val_offset:486*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 486*FLEN/8, x4, x1, x2) + +inst_276: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x455; op2val:0x2800; + valaddr_reg:x3; val_offset:488*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 488*FLEN/8, x4, x1, x2) + +inst_277: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x455; op2val:0xa800; + valaddr_reg:x3; val_offset:490*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 490*FLEN/8, x4, x1, x2) + +inst_278: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x455; op2val:0x7c00; + valaddr_reg:x3; val_offset:492*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 492*FLEN/8, x4, x1, x2) + +inst_279: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x455; op2val:0xfc00; + valaddr_reg:x3; val_offset:494*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 494*FLEN/8, x4, x1, x2) + +inst_280: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x455; op2val:0x7e00; + valaddr_reg:x3; val_offset:496*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 496*FLEN/8, x4, x1, x2) + +inst_281: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x455; op2val:0xfe00; + valaddr_reg:x3; val_offset:498*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 498*FLEN/8, x4, x1, x2) + +inst_282: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x455; op2val:0x7e01; + valaddr_reg:x3; val_offset:500*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 500*FLEN/8, x4, x1, x2) + +inst_283: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x455; op2val:0xfe55; + valaddr_reg:x3; val_offset:502*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 502*FLEN/8, x4, x1, x2) + +inst_284: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x455; op2val:0x7c01; + valaddr_reg:x3; val_offset:504*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 504*FLEN/8, x4, x1, x2) + +inst_285: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x455; op2val:0xfd55; + valaddr_reg:x3; val_offset:506*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 506*FLEN/8, x4, x1, x2) + +inst_286: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x0; + valaddr_reg:x3; val_offset:508*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 508*FLEN/8, x4, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_2) + +inst_287: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x8000; + valaddr_reg:x3; val_offset:510*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 510*FLEN/8, x4, x1, x2) + +inst_288: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x2; + valaddr_reg:x3; val_offset:512*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 512*FLEN/8, x4, x1, x2) + +inst_289: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x8002; + valaddr_reg:x3; val_offset:514*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 514*FLEN/8, x4, x1, x2) + +inst_290: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x3fe; + valaddr_reg:x3; val_offset:516*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 516*FLEN/8, x4, x1, x2) + +inst_291: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x83fe; + valaddr_reg:x3; val_offset:518*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 518*FLEN/8, x4, x1, x2) + +inst_292: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x2aa; + valaddr_reg:x3; val_offset:520*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 520*FLEN/8, x4, x1, x2) + +inst_293: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x82aa; + valaddr_reg:x3; val_offset:522*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 522*FLEN/8, x4, x1, x2) + +inst_294: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x401; + valaddr_reg:x3; val_offset:524*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 524*FLEN/8, x4, x1, x2) + +inst_295: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x8401; + valaddr_reg:x3; val_offset:526*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 526*FLEN/8, x4, x1, x2) + +inst_296: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x455; + valaddr_reg:x3; val_offset:528*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 528*FLEN/8, x4, x1, x2) + +inst_297: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x8455; + valaddr_reg:x3; val_offset:530*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 530*FLEN/8, x4, x1, x2) + +inst_298: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x4aa; + valaddr_reg:x3; val_offset:532*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 532*FLEN/8, x4, x1, x2) + +inst_299: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x84aa; + valaddr_reg:x3; val_offset:534*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 534*FLEN/8, x4, x1, x2) + +inst_300: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x5400; + valaddr_reg:x3; val_offset:536*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 536*FLEN/8, x4, x1, x2) + +inst_301: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x15 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xd400; + valaddr_reg:x3; val_offset:538*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 538*FLEN/8, x4, x1, x2) + +inst_302: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x2800; + valaddr_reg:x3; val_offset:540*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 540*FLEN/8, x4, x1, x2) + +inst_303: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xa800; + valaddr_reg:x3; val_offset:542*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 542*FLEN/8, x4, x1, x2) + +inst_304: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x7c00; + valaddr_reg:x3; val_offset:544*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 544*FLEN/8, x4, x1, x2) + +inst_305: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xfc00; + valaddr_reg:x3; val_offset:546*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 546*FLEN/8, x4, x1, x2) + +inst_306: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x7e00; + valaddr_reg:x3; val_offset:548*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 548*FLEN/8, x4, x1, x2) + +inst_307: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xfe00; + valaddr_reg:x3; val_offset:550*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 550*FLEN/8, x4, x1, x2) + +inst_308: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x7e01; + valaddr_reg:x3; val_offset:552*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 552*FLEN/8, x4, x1, x2) + +inst_309: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xfe55; + valaddr_reg:x3; val_offset:554*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 554*FLEN/8, x4, x1, x2) + +inst_310: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x7c01; + valaddr_reg:x3; val_offset:556*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 556*FLEN/8, x4, x1, x2) + +inst_311: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xfd55; + valaddr_reg:x3; val_offset:558*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 558*FLEN/8, x4, x1, x2) + +inst_312: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x0aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4aa; op2val:0x0; + valaddr_reg:x3; val_offset:560*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 560*FLEN/8, x4, x1, x2) + +inst_313: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x0aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4aa; op2val:0x8000; + valaddr_reg:x3; val_offset:562*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 562*FLEN/8, x4, x1, x2) + +inst_314: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x0aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4aa; op2val:0x2; + valaddr_reg:x3; val_offset:564*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 564*FLEN/8, x4, x1, x2) + +inst_315: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x0aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4aa; op2val:0x8002; + valaddr_reg:x3; val_offset:566*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 566*FLEN/8, x4, x1, x2) + +inst_316: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x0aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4aa; op2val:0x3fe; + valaddr_reg:x3; val_offset:568*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 568*FLEN/8, x4, x1, x2) + +inst_317: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x0aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4aa; op2val:0x83fe; + valaddr_reg:x3; val_offset:570*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 570*FLEN/8, x4, x1, x2) + +inst_318: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x0aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4aa; op2val:0x2aa; + valaddr_reg:x3; val_offset:572*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 572*FLEN/8, x4, x1, x2) + +inst_319: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x0aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4aa; op2val:0x82aa; + valaddr_reg:x3; val_offset:574*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 574*FLEN/8, x4, x1, x2) + +inst_320: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x0aa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4aa; op2val:0x401; + valaddr_reg:x3; val_offset:576*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 576*FLEN/8, x4, x1, x2) + +inst_321: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x0aa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4aa; op2val:0x8401; + valaddr_reg:x3; val_offset:578*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 578*FLEN/8, x4, x1, x2) + +inst_322: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x0aa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4aa; op2val:0x455; + valaddr_reg:x3; val_offset:580*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 580*FLEN/8, x4, x1, x2) + +inst_323: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x0aa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4aa; op2val:0x8455; + valaddr_reg:x3; val_offset:582*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 582*FLEN/8, x4, x1, x2) + +inst_324: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x0aa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4aa; op2val:0x4aa; + valaddr_reg:x3; val_offset:584*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 584*FLEN/8, x4, x1, x2) + +inst_325: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x0aa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4aa; op2val:0x84aa; + valaddr_reg:x3; val_offset:586*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 586*FLEN/8, x4, x1, x2) + +inst_326: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x0aa and fs2 == 0 and fe2 == 0x15 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4aa; op2val:0x5400; + valaddr_reg:x3; val_offset:588*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 588*FLEN/8, x4, x1, x2) + +inst_327: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x0aa and fs2 == 1 and fe2 == 0x15 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4aa; op2val:0xd400; + valaddr_reg:x3; val_offset:590*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 590*FLEN/8, x4, x1, x2) + +inst_328: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x0aa and fs2 == 0 and fe2 == 0x0a and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4aa; op2val:0x2800; + valaddr_reg:x3; val_offset:592*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 592*FLEN/8, x4, x1, x2) + +inst_329: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x0aa and fs2 == 1 and fe2 == 0x0a and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4aa; op2val:0xa800; + valaddr_reg:x3; val_offset:594*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 594*FLEN/8, x4, x1, x2) + +inst_330: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x0aa and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4aa; op2val:0x7c00; + valaddr_reg:x3; val_offset:596*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 596*FLEN/8, x4, x1, x2) + +inst_331: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x0aa and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4aa; op2val:0xfc00; + valaddr_reg:x3; val_offset:598*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 598*FLEN/8, x4, x1, x2) + +inst_332: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x0aa and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4aa; op2val:0x7e00; + valaddr_reg:x3; val_offset:600*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 600*FLEN/8, x4, x1, x2) + +inst_333: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x0aa and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4aa; op2val:0xfe00; + valaddr_reg:x3; val_offset:602*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 602*FLEN/8, x4, x1, x2) + +inst_334: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x0aa and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4aa; op2val:0x7e01; + valaddr_reg:x3; val_offset:604*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 604*FLEN/8, x4, x1, x2) + +inst_335: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x0aa and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4aa; op2val:0xfe55; + valaddr_reg:x3; val_offset:606*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 606*FLEN/8, x4, x1, x2) + +inst_336: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x0aa and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4aa; op2val:0x7c01; + valaddr_reg:x3; val_offset:608*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 608*FLEN/8, x4, x1, x2) + +inst_337: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x0aa and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4aa; op2val:0xfd55; + valaddr_reg:x3; val_offset:610*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 610*FLEN/8, x4, x1, x2) + +inst_338: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x0aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x84aa; op2val:0x0; + valaddr_reg:x3; val_offset:612*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 612*FLEN/8, x4, x1, x2) + +inst_339: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x0aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x84aa; op2val:0x8000; + valaddr_reg:x3; val_offset:614*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 614*FLEN/8, x4, x1, x2) + +inst_340: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x0aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x84aa; op2val:0x2; + valaddr_reg:x3; val_offset:616*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 616*FLEN/8, x4, x1, x2) + +inst_341: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x0aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x84aa; op2val:0x8002; + valaddr_reg:x3; val_offset:618*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 618*FLEN/8, x4, x1, x2) + +inst_342: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x0aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x84aa; op2val:0x3fe; + valaddr_reg:x3; val_offset:620*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 620*FLEN/8, x4, x1, x2) + +inst_343: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x0aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x84aa; op2val:0x83fe; + valaddr_reg:x3; val_offset:622*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 622*FLEN/8, x4, x1, x2) + +inst_344: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x0aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x84aa; op2val:0x2aa; + valaddr_reg:x3; val_offset:624*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 624*FLEN/8, x4, x1, x2) + +inst_345: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x0aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x84aa; op2val:0x82aa; + valaddr_reg:x3; val_offset:626*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 626*FLEN/8, x4, x1, x2) + +inst_346: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x0aa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x84aa; op2val:0x401; + valaddr_reg:x3; val_offset:628*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 628*FLEN/8, x4, x1, x2) + +inst_347: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x0aa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x84aa; op2val:0x8401; + valaddr_reg:x3; val_offset:630*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 630*FLEN/8, x4, x1, x2) + +inst_348: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x0aa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x84aa; op2val:0x455; + valaddr_reg:x3; val_offset:632*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 632*FLEN/8, x4, x1, x2) + +inst_349: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x0aa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x84aa; op2val:0x8455; + valaddr_reg:x3; val_offset:634*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 634*FLEN/8, x4, x1, x2) + +inst_350: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x0aa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x84aa; op2val:0x4aa; + valaddr_reg:x3; val_offset:636*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 636*FLEN/8, x4, x1, x2) + +inst_351: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x0aa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x84aa; op2val:0x84aa; + valaddr_reg:x3; val_offset:638*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 638*FLEN/8, x4, x1, x2) + +inst_352: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x0aa and fs2 == 0 and fe2 == 0x15 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x84aa; op2val:0x5400; + valaddr_reg:x3; val_offset:640*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 640*FLEN/8, x4, x1, x2) + +inst_353: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x0aa and fs2 == 1 and fe2 == 0x15 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x84aa; op2val:0xd400; + valaddr_reg:x3; val_offset:642*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 642*FLEN/8, x4, x1, x2) + +inst_354: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x0aa and fs2 == 0 and fe2 == 0x0a and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x84aa; op2val:0x2800; + valaddr_reg:x3; val_offset:644*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 644*FLEN/8, x4, x1, x2) + +inst_355: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x0aa and fs2 == 1 and fe2 == 0x0a and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x84aa; op2val:0xa800; + valaddr_reg:x3; val_offset:646*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 646*FLEN/8, x4, x1, x2) + +inst_356: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x0aa and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x84aa; op2val:0x7c00; + valaddr_reg:x3; val_offset:648*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 648*FLEN/8, x4, x1, x2) + +inst_357: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x0aa and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x84aa; op2val:0xfc00; + valaddr_reg:x3; val_offset:650*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 650*FLEN/8, x4, x1, x2) + +inst_358: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x0aa and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x84aa; op2val:0x7e00; + valaddr_reg:x3; val_offset:652*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 652*FLEN/8, x4, x1, x2) + +inst_359: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x0aa and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x84aa; op2val:0xfe00; + valaddr_reg:x3; val_offset:654*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 654*FLEN/8, x4, x1, x2) + +inst_360: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x0aa and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x84aa; op2val:0x7e01; + valaddr_reg:x3; val_offset:656*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 656*FLEN/8, x4, x1, x2) + +inst_361: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x0aa and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x84aa; op2val:0xfe55; + valaddr_reg:x3; val_offset:658*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 658*FLEN/8, x4, x1, x2) + +inst_362: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x0aa and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x84aa; op2val:0x7c01; + valaddr_reg:x3; val_offset:660*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 660*FLEN/8, x4, x1, x2) + +inst_363: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x0aa and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x84aa; op2val:0xfd55; + valaddr_reg:x3; val_offset:662*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 662*FLEN/8, x4, x1, x2) + +inst_364: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5400; op2val:0x0; + valaddr_reg:x3; val_offset:664*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 664*FLEN/8, x4, x1, x2) + +inst_365: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5400; op2val:0x8000; + valaddr_reg:x3; val_offset:666*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 666*FLEN/8, x4, x1, x2) + +inst_366: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5400; op2val:0x2; + valaddr_reg:x3; val_offset:668*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 668*FLEN/8, x4, x1, x2) + +inst_367: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5400; op2val:0x8002; + valaddr_reg:x3; val_offset:670*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 670*FLEN/8, x4, x1, x2) + +inst_368: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5400; op2val:0x3fe; + valaddr_reg:x3; val_offset:672*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 672*FLEN/8, x4, x1, x2) + +inst_369: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5400; op2val:0x83fe; + valaddr_reg:x3; val_offset:674*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 674*FLEN/8, x4, x1, x2) + +inst_370: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5400; op2val:0x2aa; + valaddr_reg:x3; val_offset:676*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 676*FLEN/8, x4, x1, x2) + +inst_371: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5400; op2val:0x82aa; + valaddr_reg:x3; val_offset:678*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 678*FLEN/8, x4, x1, x2) + +inst_372: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5400; op2val:0x401; + valaddr_reg:x3; val_offset:680*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 680*FLEN/8, x4, x1, x2) + +inst_373: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5400; op2val:0x8401; + valaddr_reg:x3; val_offset:682*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 682*FLEN/8, x4, x1, x2) + +inst_374: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5400; op2val:0x455; + valaddr_reg:x3; val_offset:684*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 684*FLEN/8, x4, x1, x2) + +inst_375: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5400; op2val:0x8455; + valaddr_reg:x3; val_offset:686*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 686*FLEN/8, x4, x1, x2) + +inst_376: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5400; op2val:0x4aa; + valaddr_reg:x3; val_offset:688*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 688*FLEN/8, x4, x1, x2) + +inst_377: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5400; op2val:0x84aa; + valaddr_reg:x3; val_offset:690*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 690*FLEN/8, x4, x1, x2) + +inst_378: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5400; op2val:0x5400; + valaddr_reg:x3; val_offset:692*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 692*FLEN/8, x4, x1, x2) + +inst_379: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x15 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5400; op2val:0xd400; + valaddr_reg:x3; val_offset:694*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 694*FLEN/8, x4, x1, x2) + +inst_380: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5400; op2val:0x2800; + valaddr_reg:x3; val_offset:696*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 696*FLEN/8, x4, x1, x2) + +inst_381: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5400; op2val:0xa800; + valaddr_reg:x3; val_offset:698*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 698*FLEN/8, x4, x1, x2) + +inst_382: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5400; op2val:0x7c00; + valaddr_reg:x3; val_offset:700*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 700*FLEN/8, x4, x1, x2) + +inst_383: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5400; op2val:0xfc00; + valaddr_reg:x3; val_offset:702*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 702*FLEN/8, x4, x1, x2) + +inst_384: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5400; op2val:0x7e00; + valaddr_reg:x3; val_offset:704*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 704*FLEN/8, x4, x1, x2) + +inst_385: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5400; op2val:0xfe00; + valaddr_reg:x3; val_offset:706*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 706*FLEN/8, x4, x1, x2) + +inst_386: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5400; op2val:0x7e01; + valaddr_reg:x3; val_offset:708*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 708*FLEN/8, x4, x1, x2) + +inst_387: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5400; op2val:0xfe55; + valaddr_reg:x3; val_offset:710*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 710*FLEN/8, x4, x1, x2) + +inst_388: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5400; op2val:0x7c01; + valaddr_reg:x3; val_offset:712*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 712*FLEN/8, x4, x1, x2) + +inst_389: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5400; op2val:0xfd55; + valaddr_reg:x3; val_offset:714*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 714*FLEN/8, x4, x1, x2) + +inst_390: +// fs1 == 1 and fe1 == 0x15 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xd400; op2val:0x0; + valaddr_reg:x3; val_offset:716*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 716*FLEN/8, x4, x1, x2) + +inst_391: +// fs1 == 1 and fe1 == 0x15 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xd400; op2val:0x8000; + valaddr_reg:x3; val_offset:718*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 718*FLEN/8, x4, x1, x2) + +inst_392: +// fs1 == 1 and fe1 == 0x15 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xd400; op2val:0x2; + valaddr_reg:x3; val_offset:720*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 720*FLEN/8, x4, x1, x2) + +inst_393: +// fs1 == 1 and fe1 == 0x15 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xd400; op2val:0x8002; + valaddr_reg:x3; val_offset:722*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 722*FLEN/8, x4, x1, x2) + +inst_394: +// fs1 == 1 and fe1 == 0x15 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xd400; op2val:0x3fe; + valaddr_reg:x3; val_offset:724*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 724*FLEN/8, x4, x1, x2) + +inst_395: +// fs1 == 1 and fe1 == 0x15 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xd400; op2val:0x83fe; + valaddr_reg:x3; val_offset:726*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 726*FLEN/8, x4, x1, x2) + +inst_396: +// fs1 == 1 and fe1 == 0x15 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xd400; op2val:0x2aa; + valaddr_reg:x3; val_offset:728*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 728*FLEN/8, x4, x1, x2) + +inst_397: +// fs1 == 1 and fe1 == 0x15 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xd400; op2val:0x82aa; + valaddr_reg:x3; val_offset:730*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 730*FLEN/8, x4, x1, x2) + +inst_398: +// fs1 == 1 and fe1 == 0x15 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xd400; op2val:0x401; + valaddr_reg:x3; val_offset:732*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 732*FLEN/8, x4, x1, x2) + +inst_399: +// fs1 == 1 and fe1 == 0x15 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xd400; op2val:0x8401; + valaddr_reg:x3; val_offset:734*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 734*FLEN/8, x4, x1, x2) + +inst_400: +// fs1 == 1 and fe1 == 0x15 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xd400; op2val:0x455; + valaddr_reg:x3; val_offset:736*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 736*FLEN/8, x4, x1, x2) + +inst_401: +// fs1 == 1 and fe1 == 0x15 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xd400; op2val:0x8455; + valaddr_reg:x3; val_offset:738*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 738*FLEN/8, x4, x1, x2) + +inst_402: +// fs1 == 1 and fe1 == 0x15 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xd400; op2val:0x4aa; + valaddr_reg:x3; val_offset:740*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 740*FLEN/8, x4, x1, x2) + +inst_403: +// fs1 == 1 and fe1 == 0x15 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xd400; op2val:0x84aa; + valaddr_reg:x3; val_offset:742*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 742*FLEN/8, x4, x1, x2) + +inst_404: +// fs1 == 1 and fe1 == 0x15 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xd400; op2val:0x5400; + valaddr_reg:x3; val_offset:744*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 744*FLEN/8, x4, x1, x2) + +inst_405: +// fs1 == 1 and fe1 == 0x15 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x15 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xd400; op2val:0xd400; + valaddr_reg:x3; val_offset:746*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 746*FLEN/8, x4, x1, x2) + +inst_406: +// fs1 == 1 and fe1 == 0x15 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xd400; op2val:0x2800; + valaddr_reg:x3; val_offset:748*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 748*FLEN/8, x4, x1, x2) + +inst_407: +// fs1 == 1 and fe1 == 0x15 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xd400; op2val:0xa800; + valaddr_reg:x3; val_offset:750*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 750*FLEN/8, x4, x1, x2) + +inst_408: +// fs1 == 1 and fe1 == 0x15 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xd400; op2val:0x7c00; + valaddr_reg:x3; val_offset:752*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 752*FLEN/8, x4, x1, x2) + +inst_409: +// fs1 == 1 and fe1 == 0x15 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xd400; op2val:0xfc00; + valaddr_reg:x3; val_offset:754*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 754*FLEN/8, x4, x1, x2) + +inst_410: +// fs1 == 1 and fe1 == 0x15 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xd400; op2val:0x7e00; + valaddr_reg:x3; val_offset:756*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 756*FLEN/8, x4, x1, x2) + +inst_411: +// fs1 == 1 and fe1 == 0x15 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xd400; op2val:0xfe00; + valaddr_reg:x3; val_offset:758*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 758*FLEN/8, x4, x1, x2) + +inst_412: +// fs1 == 1 and fe1 == 0x15 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xd400; op2val:0x7e01; + valaddr_reg:x3; val_offset:760*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 760*FLEN/8, x4, x1, x2) + +inst_413: +// fs1 == 1 and fe1 == 0x15 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xd400; op2val:0xfe55; + valaddr_reg:x3; val_offset:762*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 762*FLEN/8, x4, x1, x2) + +inst_414: +// fs1 == 1 and fe1 == 0x15 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xd400; op2val:0x7c01; + valaddr_reg:x3; val_offset:764*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 764*FLEN/8, x4, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_3) + +inst_415: +// fs1 == 1 and fe1 == 0x15 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xd400; op2val:0xfd55; + valaddr_reg:x3; val_offset:766*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 766*FLEN/8, x4, x1, x2) + +inst_416: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2800; op2val:0x0; + valaddr_reg:x3; val_offset:768*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 768*FLEN/8, x4, x1, x2) + +inst_417: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2800; op2val:0x8000; + valaddr_reg:x3; val_offset:770*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 770*FLEN/8, x4, x1, x2) + +inst_418: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2800; op2val:0x2; + valaddr_reg:x3; val_offset:772*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 772*FLEN/8, x4, x1, x2) + +inst_419: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2800; op2val:0x8002; + valaddr_reg:x3; val_offset:774*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 774*FLEN/8, x4, x1, x2) + +inst_420: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2800; op2val:0x3fe; + valaddr_reg:x3; val_offset:776*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 776*FLEN/8, x4, x1, x2) + +inst_421: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2800; op2val:0x83fe; + valaddr_reg:x3; val_offset:778*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 778*FLEN/8, x4, x1, x2) + +inst_422: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2800; op2val:0x2aa; + valaddr_reg:x3; val_offset:780*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 780*FLEN/8, x4, x1, x2) + +inst_423: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2800; op2val:0x82aa; + valaddr_reg:x3; val_offset:782*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 782*FLEN/8, x4, x1, x2) + +inst_424: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2800; op2val:0x401; + valaddr_reg:x3; val_offset:784*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 784*FLEN/8, x4, x1, x2) + +inst_425: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2800; op2val:0x8401; + valaddr_reg:x3; val_offset:786*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 786*FLEN/8, x4, x1, x2) + +inst_426: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2800; op2val:0x455; + valaddr_reg:x3; val_offset:788*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 788*FLEN/8, x4, x1, x2) + +inst_427: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2800; op2val:0x8455; + valaddr_reg:x3; val_offset:790*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 790*FLEN/8, x4, x1, x2) + +inst_428: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2800; op2val:0x4aa; + valaddr_reg:x3; val_offset:792*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 792*FLEN/8, x4, x1, x2) + +inst_429: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2800; op2val:0x84aa; + valaddr_reg:x3; val_offset:794*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 794*FLEN/8, x4, x1, x2) + +inst_430: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x000 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2800; op2val:0x5400; + valaddr_reg:x3; val_offset:796*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 796*FLEN/8, x4, x1, x2) + +inst_431: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x000 and fs2 == 1 and fe2 == 0x15 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2800; op2val:0xd400; + valaddr_reg:x3; val_offset:798*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 798*FLEN/8, x4, x1, x2) + +inst_432: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2800; op2val:0x2800; + valaddr_reg:x3; val_offset:800*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 800*FLEN/8, x4, x1, x2) + +inst_433: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2800; op2val:0xa800; + valaddr_reg:x3; val_offset:802*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 802*FLEN/8, x4, x1, x2) + +inst_434: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2800; op2val:0x7c00; + valaddr_reg:x3; val_offset:804*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 804*FLEN/8, x4, x1, x2) + +inst_435: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2800; op2val:0xfc00; + valaddr_reg:x3; val_offset:806*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 806*FLEN/8, x4, x1, x2) + +inst_436: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2800; op2val:0x7e00; + valaddr_reg:x3; val_offset:808*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 808*FLEN/8, x4, x1, x2) + +inst_437: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2800; op2val:0xfe00; + valaddr_reg:x3; val_offset:810*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 810*FLEN/8, x4, x1, x2) + +inst_438: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2800; op2val:0x7e01; + valaddr_reg:x3; val_offset:812*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 812*FLEN/8, x4, x1, x2) + +inst_439: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2800; op2val:0xfe55; + valaddr_reg:x3; val_offset:814*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 814*FLEN/8, x4, x1, x2) + +inst_440: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2800; op2val:0x7c01; + valaddr_reg:x3; val_offset:816*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 816*FLEN/8, x4, x1, x2) + +inst_441: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2800; op2val:0xfd55; + valaddr_reg:x3; val_offset:818*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 818*FLEN/8, x4, x1, x2) + +inst_442: +// fs1 == 1 and fe1 == 0x0a and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xa800; op2val:0x0; + valaddr_reg:x3; val_offset:820*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 820*FLEN/8, x4, x1, x2) + +inst_443: +// fs1 == 1 and fe1 == 0x0a and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xa800; op2val:0x8000; + valaddr_reg:x3; val_offset:822*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 822*FLEN/8, x4, x1, x2) + +inst_444: +// fs1 == 1 and fe1 == 0x0a and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xa800; op2val:0x2; + valaddr_reg:x3; val_offset:824*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 824*FLEN/8, x4, x1, x2) + +inst_445: +// fs1 == 1 and fe1 == 0x0a and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xa800; op2val:0x8002; + valaddr_reg:x3; val_offset:826*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 826*FLEN/8, x4, x1, x2) + +inst_446: +// fs1 == 1 and fe1 == 0x0a and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xa800; op2val:0x3fe; + valaddr_reg:x3; val_offset:828*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 828*FLEN/8, x4, x1, x2) + +inst_447: +// fs1 == 1 and fe1 == 0x0a and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xa800; op2val:0x83fe; + valaddr_reg:x3; val_offset:830*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 830*FLEN/8, x4, x1, x2) + +inst_448: +// fs1 == 1 and fe1 == 0x0a and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xa800; op2val:0x2aa; + valaddr_reg:x3; val_offset:832*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 832*FLEN/8, x4, x1, x2) + +inst_449: +// fs1 == 1 and fe1 == 0x0a and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xa800; op2val:0x82aa; + valaddr_reg:x3; val_offset:834*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 834*FLEN/8, x4, x1, x2) + +inst_450: +// fs1 == 1 and fe1 == 0x0a and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xa800; op2val:0x401; + valaddr_reg:x3; val_offset:836*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 836*FLEN/8, x4, x1, x2) + +inst_451: +// fs1 == 1 and fe1 == 0x0a and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xa800; op2val:0x8401; + valaddr_reg:x3; val_offset:838*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 838*FLEN/8, x4, x1, x2) + +inst_452: +// fs1 == 1 and fe1 == 0x0a and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xa800; op2val:0x455; + valaddr_reg:x3; val_offset:840*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 840*FLEN/8, x4, x1, x2) + +inst_453: +// fs1 == 1 and fe1 == 0x0a and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xa800; op2val:0x8455; + valaddr_reg:x3; val_offset:842*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 842*FLEN/8, x4, x1, x2) + +inst_454: +// fs1 == 1 and fe1 == 0x0a and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xa800; op2val:0x4aa; + valaddr_reg:x3; val_offset:844*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 844*FLEN/8, x4, x1, x2) + +inst_455: +// fs1 == 1 and fe1 == 0x0a and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xa800; op2val:0x84aa; + valaddr_reg:x3; val_offset:846*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 846*FLEN/8, x4, x1, x2) + +inst_456: +// fs1 == 1 and fe1 == 0x0a and fm1 == 0x000 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xa800; op2val:0x5400; + valaddr_reg:x3; val_offset:848*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 848*FLEN/8, x4, x1, x2) + +inst_457: +// fs1 == 1 and fe1 == 0x0a and fm1 == 0x000 and fs2 == 1 and fe2 == 0x15 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xa800; op2val:0xd400; + valaddr_reg:x3; val_offset:850*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 850*FLEN/8, x4, x1, x2) + +inst_458: +// fs1 == 1 and fe1 == 0x0a and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xa800; op2val:0x2800; + valaddr_reg:x3; val_offset:852*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 852*FLEN/8, x4, x1, x2) + +inst_459: +// fs1 == 1 and fe1 == 0x0a and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xa800; op2val:0xa800; + valaddr_reg:x3; val_offset:854*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 854*FLEN/8, x4, x1, x2) + +inst_460: +// fs1 == 1 and fe1 == 0x0a and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xa800; op2val:0x7c00; + valaddr_reg:x3; val_offset:856*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 856*FLEN/8, x4, x1, x2) + +inst_461: +// fs1 == 1 and fe1 == 0x0a and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xa800; op2val:0xfc00; + valaddr_reg:x3; val_offset:858*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 858*FLEN/8, x4, x1, x2) + +inst_462: +// fs1 == 1 and fe1 == 0x0a and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xa800; op2val:0x7e00; + valaddr_reg:x3; val_offset:860*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 860*FLEN/8, x4, x1, x2) + +inst_463: +// fs1 == 1 and fe1 == 0x0a and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xa800; op2val:0xfe00; + valaddr_reg:x3; val_offset:862*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 862*FLEN/8, x4, x1, x2) + +inst_464: +// fs1 == 1 and fe1 == 0x0a and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xa800; op2val:0x7e01; + valaddr_reg:x3; val_offset:864*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 864*FLEN/8, x4, x1, x2) + +inst_465: +// fs1 == 1 and fe1 == 0x0a and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xa800; op2val:0xfe55; + valaddr_reg:x3; val_offset:866*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 866*FLEN/8, x4, x1, x2) + +inst_466: +// fs1 == 1 and fe1 == 0x0a and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xa800; op2val:0x7c01; + valaddr_reg:x3; val_offset:868*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 868*FLEN/8, x4, x1, x2) + +inst_467: +// fs1 == 1 and fe1 == 0x0a and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xa800; op2val:0xfd55; + valaddr_reg:x3; val_offset:870*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 870*FLEN/8, x4, x1, x2) + +inst_468: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x0; + valaddr_reg:x3; val_offset:872*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 872*FLEN/8, x4, x1, x2) + +inst_469: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x8000; + valaddr_reg:x3; val_offset:874*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 874*FLEN/8, x4, x1, x2) + +inst_470: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x2; + valaddr_reg:x3; val_offset:876*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 876*FLEN/8, x4, x1, x2) + +inst_471: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x8002; + valaddr_reg:x3; val_offset:878*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 878*FLEN/8, x4, x1, x2) + +inst_472: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x3fe; + valaddr_reg:x3; val_offset:880*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 880*FLEN/8, x4, x1, x2) + +inst_473: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x83fe; + valaddr_reg:x3; val_offset:882*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 882*FLEN/8, x4, x1, x2) + +inst_474: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x2aa; + valaddr_reg:x3; val_offset:884*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 884*FLEN/8, x4, x1, x2) + +inst_475: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x82aa; + valaddr_reg:x3; val_offset:886*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 886*FLEN/8, x4, x1, x2) + +inst_476: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x401; + valaddr_reg:x3; val_offset:888*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 888*FLEN/8, x4, x1, x2) + +inst_477: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x8401; + valaddr_reg:x3; val_offset:890*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 890*FLEN/8, x4, x1, x2) + +inst_478: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x455; + valaddr_reg:x3; val_offset:892*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 892*FLEN/8, x4, x1, x2) + +inst_479: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x8455; + valaddr_reg:x3; val_offset:894*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 894*FLEN/8, x4, x1, x2) + +inst_480: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x4aa; + valaddr_reg:x3; val_offset:896*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 896*FLEN/8, x4, x1, x2) + +inst_481: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x84aa; + valaddr_reg:x3; val_offset:898*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 898*FLEN/8, x4, x1, x2) + +inst_482: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x5400; + valaddr_reg:x3; val_offset:900*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 900*FLEN/8, x4, x1, x2) + +inst_483: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x15 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xd400; + valaddr_reg:x3; val_offset:902*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 902*FLEN/8, x4, x1, x2) + +inst_484: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x2800; + valaddr_reg:x3; val_offset:904*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 904*FLEN/8, x4, x1, x2) + +inst_485: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xa800; + valaddr_reg:x3; val_offset:906*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 906*FLEN/8, x4, x1, x2) + +inst_486: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x7c00; + valaddr_reg:x3; val_offset:908*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 908*FLEN/8, x4, x1, x2) + +inst_487: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xfc00; + valaddr_reg:x3; val_offset:910*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 910*FLEN/8, x4, x1, x2) + +inst_488: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x7e00; + valaddr_reg:x3; val_offset:912*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 912*FLEN/8, x4, x1, x2) + +inst_489: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xfe00; + valaddr_reg:x3; val_offset:914*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 914*FLEN/8, x4, x1, x2) + +inst_490: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x7e01; + valaddr_reg:x3; val_offset:916*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 916*FLEN/8, x4, x1, x2) + +inst_491: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xfe55; + valaddr_reg:x3; val_offset:918*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 918*FLEN/8, x4, x1, x2) + +inst_492: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x7c01; + valaddr_reg:x3; val_offset:920*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 920*FLEN/8, x4, x1, x2) + +inst_493: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xfd55; + valaddr_reg:x3; val_offset:922*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 922*FLEN/8, x4, x1, x2) + +inst_494: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x0; + valaddr_reg:x3; val_offset:924*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 924*FLEN/8, x4, x1, x2) + +inst_495: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x8000; + valaddr_reg:x3; val_offset:926*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 926*FLEN/8, x4, x1, x2) + +inst_496: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x2; + valaddr_reg:x3; val_offset:928*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 928*FLEN/8, x4, x1, x2) + +inst_497: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x8002; + valaddr_reg:x3; val_offset:930*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 930*FLEN/8, x4, x1, x2) + +inst_498: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x3fe; + valaddr_reg:x3; val_offset:932*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 932*FLEN/8, x4, x1, x2) + +inst_499: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x83fe; + valaddr_reg:x3; val_offset:934*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 934*FLEN/8, x4, x1, x2) + +inst_500: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x2aa; + valaddr_reg:x3; val_offset:936*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 936*FLEN/8, x4, x1, x2) + +inst_501: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x82aa; + valaddr_reg:x3; val_offset:938*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 938*FLEN/8, x4, x1, x2) + +inst_502: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x401; + valaddr_reg:x3; val_offset:940*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 940*FLEN/8, x4, x1, x2) + +inst_503: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x8401; + valaddr_reg:x3; val_offset:942*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 942*FLEN/8, x4, x1, x2) + +inst_504: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x455; + valaddr_reg:x3; val_offset:944*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 944*FLEN/8, x4, x1, x2) + +inst_505: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x8455; + valaddr_reg:x3; val_offset:946*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 946*FLEN/8, x4, x1, x2) + +inst_506: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x4aa; + valaddr_reg:x3; val_offset:948*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 948*FLEN/8, x4, x1, x2) + +inst_507: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x84aa; + valaddr_reg:x3; val_offset:950*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 950*FLEN/8, x4, x1, x2) + +inst_508: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x5400; + valaddr_reg:x3; val_offset:952*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 952*FLEN/8, x4, x1, x2) + +inst_509: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x15 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xd400; + valaddr_reg:x3; val_offset:954*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 954*FLEN/8, x4, x1, x2) + +inst_510: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x2800; + valaddr_reg:x3; val_offset:956*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 956*FLEN/8, x4, x1, x2) + +inst_511: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xa800; + valaddr_reg:x3; val_offset:958*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 958*FLEN/8, x4, x1, x2) + +inst_512: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x7c00; + valaddr_reg:x3; val_offset:960*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 960*FLEN/8, x4, x1, x2) + +inst_513: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xfc00; + valaddr_reg:x3; val_offset:962*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 962*FLEN/8, x4, x1, x2) + +inst_514: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x7e00; + valaddr_reg:x3; val_offset:964*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 964*FLEN/8, x4, x1, x2) + +inst_515: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xfe00; + valaddr_reg:x3; val_offset:966*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 966*FLEN/8, x4, x1, x2) + +inst_516: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x7e01; + valaddr_reg:x3; val_offset:968*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 968*FLEN/8, x4, x1, x2) + +inst_517: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xfe55; + valaddr_reg:x3; val_offset:970*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 970*FLEN/8, x4, x1, x2) + +inst_518: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x7c01; + valaddr_reg:x3; val_offset:972*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 972*FLEN/8, x4, x1, x2) + +inst_519: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xfd55; + valaddr_reg:x3; val_offset:974*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 974*FLEN/8, x4, x1, x2) + +inst_520: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x0; + valaddr_reg:x3; val_offset:976*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 976*FLEN/8, x4, x1, x2) + +inst_521: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x8000; + valaddr_reg:x3; val_offset:978*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 978*FLEN/8, x4, x1, x2) + +inst_522: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x2; + valaddr_reg:x3; val_offset:980*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 980*FLEN/8, x4, x1, x2) + +inst_523: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x8002; + valaddr_reg:x3; val_offset:982*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 982*FLEN/8, x4, x1, x2) + +inst_524: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x3fe; + valaddr_reg:x3; val_offset:984*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 984*FLEN/8, x4, x1, x2) + +inst_525: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x83fe; + valaddr_reg:x3; val_offset:986*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 986*FLEN/8, x4, x1, x2) + +inst_526: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x2aa; + valaddr_reg:x3; val_offset:988*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 988*FLEN/8, x4, x1, x2) + +inst_527: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x82aa; + valaddr_reg:x3; val_offset:990*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 990*FLEN/8, x4, x1, x2) + +inst_528: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x401; + valaddr_reg:x3; val_offset:992*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 992*FLEN/8, x4, x1, x2) + +inst_529: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x8401; + valaddr_reg:x3; val_offset:994*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 994*FLEN/8, x4, x1, x2) + +inst_530: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x455; + valaddr_reg:x3; val_offset:996*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 996*FLEN/8, x4, x1, x2) + +inst_531: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x8455; + valaddr_reg:x3; val_offset:998*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 998*FLEN/8, x4, x1, x2) + +inst_532: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x4aa; + valaddr_reg:x3; val_offset:1000*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1000*FLEN/8, x4, x1, x2) + +inst_533: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x84aa; + valaddr_reg:x3; val_offset:1002*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1002*FLEN/8, x4, x1, x2) + +inst_534: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x5400; + valaddr_reg:x3; val_offset:1004*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1004*FLEN/8, x4, x1, x2) + +inst_535: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x15 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xd400; + valaddr_reg:x3; val_offset:1006*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1006*FLEN/8, x4, x1, x2) + +inst_536: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x2800; + valaddr_reg:x3; val_offset:1008*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1008*FLEN/8, x4, x1, x2) + +inst_537: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xa800; + valaddr_reg:x3; val_offset:1010*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1010*FLEN/8, x4, x1, x2) + +inst_538: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x7c00; + valaddr_reg:x3; val_offset:1012*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1012*FLEN/8, x4, x1, x2) + +inst_539: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xfc00; + valaddr_reg:x3; val_offset:1014*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1014*FLEN/8, x4, x1, x2) + +inst_540: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x7e00; + valaddr_reg:x3; val_offset:1016*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1016*FLEN/8, x4, x1, x2) + +inst_541: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xfe00; + valaddr_reg:x3; val_offset:1018*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1018*FLEN/8, x4, x1, x2) + +inst_542: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x7e01; + valaddr_reg:x3; val_offset:1020*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1020*FLEN/8, x4, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_4) + +inst_543: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xfe55; + valaddr_reg:x3; val_offset:1022*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1022*FLEN/8, x4, x1, x2) + +inst_544: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x7c01; + valaddr_reg:x3; val_offset:1024*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1024*FLEN/8, x4, x1, x2) + +inst_545: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xfd55; + valaddr_reg:x3; val_offset:1026*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1026*FLEN/8, x4, x1, x2) + +inst_546: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x0; + valaddr_reg:x3; val_offset:1028*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1028*FLEN/8, x4, x1, x2) + +inst_547: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x8000; + valaddr_reg:x3; val_offset:1030*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1030*FLEN/8, x4, x1, x2) + +inst_548: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x2; + valaddr_reg:x3; val_offset:1032*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1032*FLEN/8, x4, x1, x2) + +inst_549: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x8002; + valaddr_reg:x3; val_offset:1034*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1034*FLEN/8, x4, x1, x2) + +inst_550: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x3fe; + valaddr_reg:x3; val_offset:1036*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1036*FLEN/8, x4, x1, x2) + +inst_551: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x83fe; + valaddr_reg:x3; val_offset:1038*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1038*FLEN/8, x4, x1, x2) + +inst_552: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x2aa; + valaddr_reg:x3; val_offset:1040*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1040*FLEN/8, x4, x1, x2) + +inst_553: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x82aa; + valaddr_reg:x3; val_offset:1042*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1042*FLEN/8, x4, x1, x2) + +inst_554: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x401; + valaddr_reg:x3; val_offset:1044*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1044*FLEN/8, x4, x1, x2) + +inst_555: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x8401; + valaddr_reg:x3; val_offset:1046*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1046*FLEN/8, x4, x1, x2) + +inst_556: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x455; + valaddr_reg:x3; val_offset:1048*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1048*FLEN/8, x4, x1, x2) + +inst_557: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x8455; + valaddr_reg:x3; val_offset:1050*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1050*FLEN/8, x4, x1, x2) + +inst_558: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x4aa; + valaddr_reg:x3; val_offset:1052*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1052*FLEN/8, x4, x1, x2) + +inst_559: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x84aa; + valaddr_reg:x3; val_offset:1054*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1054*FLEN/8, x4, x1, x2) + +inst_560: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x5400; + valaddr_reg:x3; val_offset:1056*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1056*FLEN/8, x4, x1, x2) + +inst_561: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x15 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xd400; + valaddr_reg:x3; val_offset:1058*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1058*FLEN/8, x4, x1, x2) + +inst_562: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x2800; + valaddr_reg:x3; val_offset:1060*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1060*FLEN/8, x4, x1, x2) + +inst_563: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xa800; + valaddr_reg:x3; val_offset:1062*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1062*FLEN/8, x4, x1, x2) + +inst_564: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x7c00; + valaddr_reg:x3; val_offset:1064*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1064*FLEN/8, x4, x1, x2) + +inst_565: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xfc00; + valaddr_reg:x3; val_offset:1066*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1066*FLEN/8, x4, x1, x2) + +inst_566: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x7e00; + valaddr_reg:x3; val_offset:1068*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1068*FLEN/8, x4, x1, x2) + +inst_567: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xfe00; + valaddr_reg:x3; val_offset:1070*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1070*FLEN/8, x4, x1, x2) + +inst_568: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x7e01; + valaddr_reg:x3; val_offset:1072*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1072*FLEN/8, x4, x1, x2) + +inst_569: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xfe55; + valaddr_reg:x3; val_offset:1074*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1074*FLEN/8, x4, x1, x2) + +inst_570: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x7c01; + valaddr_reg:x3; val_offset:1076*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1076*FLEN/8, x4, x1, x2) + +inst_571: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xfd55; + valaddr_reg:x3; val_offset:1078*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1078*FLEN/8, x4, x1, x2) + +inst_572: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x0; + valaddr_reg:x3; val_offset:1080*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1080*FLEN/8, x4, x1, x2) + +inst_573: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x8000; + valaddr_reg:x3; val_offset:1082*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1082*FLEN/8, x4, x1, x2) + +inst_574: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x2; + valaddr_reg:x3; val_offset:1084*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1084*FLEN/8, x4, x1, x2) + +inst_575: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x8002; + valaddr_reg:x3; val_offset:1086*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1086*FLEN/8, x4, x1, x2) + +inst_576: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x3fe; + valaddr_reg:x3; val_offset:1088*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1088*FLEN/8, x4, x1, x2) + +inst_577: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x83fe; + valaddr_reg:x3; val_offset:1090*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1090*FLEN/8, x4, x1, x2) + +inst_578: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x2aa; + valaddr_reg:x3; val_offset:1092*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1092*FLEN/8, x4, x1, x2) + +inst_579: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x82aa; + valaddr_reg:x3; val_offset:1094*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1094*FLEN/8, x4, x1, x2) + +inst_580: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x401; + valaddr_reg:x3; val_offset:1096*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1096*FLEN/8, x4, x1, x2) + +inst_581: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x8401; + valaddr_reg:x3; val_offset:1098*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1098*FLEN/8, x4, x1, x2) + +inst_582: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x455; + valaddr_reg:x3; val_offset:1100*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1100*FLEN/8, x4, x1, x2) + +inst_583: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x8455; + valaddr_reg:x3; val_offset:1102*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1102*FLEN/8, x4, x1, x2) + +inst_584: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x4aa; + valaddr_reg:x3; val_offset:1104*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1104*FLEN/8, x4, x1, x2) + +inst_585: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x84aa; + valaddr_reg:x3; val_offset:1106*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1106*FLEN/8, x4, x1, x2) + +inst_586: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x5400; + valaddr_reg:x3; val_offset:1108*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1108*FLEN/8, x4, x1, x2) + +inst_587: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x15 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xd400; + valaddr_reg:x3; val_offset:1110*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1110*FLEN/8, x4, x1, x2) + +inst_588: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x2800; + valaddr_reg:x3; val_offset:1112*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1112*FLEN/8, x4, x1, x2) + +inst_589: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xa800; + valaddr_reg:x3; val_offset:1114*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1114*FLEN/8, x4, x1, x2) + +inst_590: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x7c00; + valaddr_reg:x3; val_offset:1116*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1116*FLEN/8, x4, x1, x2) + +inst_591: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xfc00; + valaddr_reg:x3; val_offset:1118*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1118*FLEN/8, x4, x1, x2) + +inst_592: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x7e00; + valaddr_reg:x3; val_offset:1120*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1120*FLEN/8, x4, x1, x2) + +inst_593: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xfe00; + valaddr_reg:x3; val_offset:1122*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1122*FLEN/8, x4, x1, x2) + +inst_594: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x7e01; + valaddr_reg:x3; val_offset:1124*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1124*FLEN/8, x4, x1, x2) + +inst_595: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xfe55; + valaddr_reg:x3; val_offset:1126*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1126*FLEN/8, x4, x1, x2) + +inst_596: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x7c01; + valaddr_reg:x3; val_offset:1128*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1128*FLEN/8, x4, x1, x2) + +inst_597: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xfd55; + valaddr_reg:x3; val_offset:1130*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1130*FLEN/8, x4, x1, x2) + +inst_598: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x0; + valaddr_reg:x3; val_offset:1132*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1132*FLEN/8, x4, x1, x2) + +inst_599: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x8000; + valaddr_reg:x3; val_offset:1134*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1134*FLEN/8, x4, x1, x2) + +inst_600: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x2; + valaddr_reg:x3; val_offset:1136*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1136*FLEN/8, x4, x1, x2) + +inst_601: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x8002; + valaddr_reg:x3; val_offset:1138*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1138*FLEN/8, x4, x1, x2) + +inst_602: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x3fe; + valaddr_reg:x3; val_offset:1140*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1140*FLEN/8, x4, x1, x2) + +inst_603: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x83fe; + valaddr_reg:x3; val_offset:1142*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1142*FLEN/8, x4, x1, x2) + +inst_604: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x2aa; + valaddr_reg:x3; val_offset:1144*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1144*FLEN/8, x4, x1, x2) + +inst_605: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x82aa; + valaddr_reg:x3; val_offset:1146*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1146*FLEN/8, x4, x1, x2) + +inst_606: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x401; + valaddr_reg:x3; val_offset:1148*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1148*FLEN/8, x4, x1, x2) + +inst_607: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x8401; + valaddr_reg:x3; val_offset:1150*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1150*FLEN/8, x4, x1, x2) + +inst_608: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x455; + valaddr_reg:x3; val_offset:1152*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1152*FLEN/8, x4, x1, x2) + +inst_609: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x8455; + valaddr_reg:x3; val_offset:1154*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1154*FLEN/8, x4, x1, x2) + +inst_610: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x4aa; + valaddr_reg:x3; val_offset:1156*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1156*FLEN/8, x4, x1, x2) + +inst_611: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x84aa; + valaddr_reg:x3; val_offset:1158*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1158*FLEN/8, x4, x1, x2) + +inst_612: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x5400; + valaddr_reg:x3; val_offset:1160*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1160*FLEN/8, x4, x1, x2) + +inst_613: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x15 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xd400; + valaddr_reg:x3; val_offset:1162*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1162*FLEN/8, x4, x1, x2) + +inst_614: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x2800; + valaddr_reg:x3; val_offset:1164*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1164*FLEN/8, x4, x1, x2) + +inst_615: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xa800; + valaddr_reg:x3; val_offset:1166*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1166*FLEN/8, x4, x1, x2) + +inst_616: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x7c00; + valaddr_reg:x3; val_offset:1168*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1168*FLEN/8, x4, x1, x2) + +inst_617: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xfc00; + valaddr_reg:x3; val_offset:1170*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1170*FLEN/8, x4, x1, x2) + +inst_618: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x7e00; + valaddr_reg:x3; val_offset:1172*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1172*FLEN/8, x4, x1, x2) + +inst_619: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xfe00; + valaddr_reg:x3; val_offset:1174*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1174*FLEN/8, x4, x1, x2) + +inst_620: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x7e01; + valaddr_reg:x3; val_offset:1176*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1176*FLEN/8, x4, x1, x2) + +inst_621: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xfe55; + valaddr_reg:x3; val_offset:1178*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1178*FLEN/8, x4, x1, x2) + +inst_622: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x7c01; + valaddr_reg:x3; val_offset:1180*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1180*FLEN/8, x4, x1, x2) + +inst_623: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xfd55; + valaddr_reg:x3; val_offset:1182*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1182*FLEN/8, x4, x1, x2) + +inst_624: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x0; + valaddr_reg:x3; val_offset:1184*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1184*FLEN/8, x4, x1, x2) + +inst_625: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x8000; + valaddr_reg:x3; val_offset:1186*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1186*FLEN/8, x4, x1, x2) + +inst_626: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x2; + valaddr_reg:x3; val_offset:1188*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1188*FLEN/8, x4, x1, x2) + +inst_627: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x8002; + valaddr_reg:x3; val_offset:1190*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1190*FLEN/8, x4, x1, x2) + +inst_628: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x3fe; + valaddr_reg:x3; val_offset:1192*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1192*FLEN/8, x4, x1, x2) + +inst_629: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x83fe; + valaddr_reg:x3; val_offset:1194*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1194*FLEN/8, x4, x1, x2) + +inst_630: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x2aa; + valaddr_reg:x3; val_offset:1196*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1196*FLEN/8, x4, x1, x2) + +inst_631: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x82aa; + valaddr_reg:x3; val_offset:1198*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1198*FLEN/8, x4, x1, x2) + +inst_632: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x401; + valaddr_reg:x3; val_offset:1200*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1200*FLEN/8, x4, x1, x2) + +inst_633: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x8401; + valaddr_reg:x3; val_offset:1202*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1202*FLEN/8, x4, x1, x2) + +inst_634: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x455; + valaddr_reg:x3; val_offset:1204*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1204*FLEN/8, x4, x1, x2) + +inst_635: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x8455; + valaddr_reg:x3; val_offset:1206*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1206*FLEN/8, x4, x1, x2) + +inst_636: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x4aa; + valaddr_reg:x3; val_offset:1208*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1208*FLEN/8, x4, x1, x2) + +inst_637: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x84aa; + valaddr_reg:x3; val_offset:1210*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1210*FLEN/8, x4, x1, x2) + +inst_638: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x5400; + valaddr_reg:x3; val_offset:1212*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1212*FLEN/8, x4, x1, x2) + +inst_639: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x15 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xd400; + valaddr_reg:x3; val_offset:1214*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1214*FLEN/8, x4, x1, x2) + +inst_640: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x2800; + valaddr_reg:x3; val_offset:1216*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1216*FLEN/8, x4, x1, x2) + +inst_641: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xa800; + valaddr_reg:x3; val_offset:1218*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1218*FLEN/8, x4, x1, x2) + +inst_642: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x7c00; + valaddr_reg:x3; val_offset:1220*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1220*FLEN/8, x4, x1, x2) + +inst_643: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xfc00; + valaddr_reg:x3; val_offset:1222*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1222*FLEN/8, x4, x1, x2) + +inst_644: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x7e00; + valaddr_reg:x3; val_offset:1224*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1224*FLEN/8, x4, x1, x2) + +inst_645: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xfe00; + valaddr_reg:x3; val_offset:1226*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1226*FLEN/8, x4, x1, x2) + +inst_646: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x7e01; + valaddr_reg:x3; val_offset:1228*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1228*FLEN/8, x4, x1, x2) + +inst_647: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xfe55; + valaddr_reg:x3; val_offset:1230*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1230*FLEN/8, x4, x1, x2) + +inst_648: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x7c01; + valaddr_reg:x3; val_offset:1232*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1232*FLEN/8, x4, x1, x2) + +inst_649: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xfd55; + valaddr_reg:x3; val_offset:1234*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1234*FLEN/8, x4, x1, x2) + +inst_650: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x0; + valaddr_reg:x3; val_offset:1236*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1236*FLEN/8, x4, x1, x2) + +inst_651: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x8000; + valaddr_reg:x3; val_offset:1238*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1238*FLEN/8, x4, x1, x2) + +inst_652: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x2; + valaddr_reg:x3; val_offset:1240*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1240*FLEN/8, x4, x1, x2) + +inst_653: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x8002; + valaddr_reg:x3; val_offset:1242*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1242*FLEN/8, x4, x1, x2) + +inst_654: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x3fe; + valaddr_reg:x3; val_offset:1244*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1244*FLEN/8, x4, x1, x2) + +inst_655: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x83fe; + valaddr_reg:x3; val_offset:1246*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1246*FLEN/8, x4, x1, x2) + +inst_656: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x2aa; + valaddr_reg:x3; val_offset:1248*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1248*FLEN/8, x4, x1, x2) + +inst_657: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x82aa; + valaddr_reg:x3; val_offset:1250*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1250*FLEN/8, x4, x1, x2) + +inst_658: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x401; + valaddr_reg:x3; val_offset:1252*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1252*FLEN/8, x4, x1, x2) + +inst_659: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x8401; + valaddr_reg:x3; val_offset:1254*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1254*FLEN/8, x4, x1, x2) + +inst_660: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x455; + valaddr_reg:x3; val_offset:1256*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1256*FLEN/8, x4, x1, x2) + +inst_661: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x8455; + valaddr_reg:x3; val_offset:1258*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1258*FLEN/8, x4, x1, x2) + +inst_662: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x4aa; + valaddr_reg:x3; val_offset:1260*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1260*FLEN/8, x4, x1, x2) + +inst_663: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x84aa; + valaddr_reg:x3; val_offset:1262*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1262*FLEN/8, x4, x1, x2) + +inst_664: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x5400; + valaddr_reg:x3; val_offset:1264*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1264*FLEN/8, x4, x1, x2) + +inst_665: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x15 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xd400; + valaddr_reg:x3; val_offset:1266*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1266*FLEN/8, x4, x1, x2) + +inst_666: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x2800; + valaddr_reg:x3; val_offset:1268*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1268*FLEN/8, x4, x1, x2) + +inst_667: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xa800; + valaddr_reg:x3; val_offset:1270*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1270*FLEN/8, x4, x1, x2) + +inst_668: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x7c00; + valaddr_reg:x3; val_offset:1272*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1272*FLEN/8, x4, x1, x2) + +inst_669: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xfc00; + valaddr_reg:x3; val_offset:1274*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1274*FLEN/8, x4, x1, x2) + +inst_670: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x7e00; + valaddr_reg:x3; val_offset:1276*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1276*FLEN/8, x4, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_5) + +inst_671: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xfe00; + valaddr_reg:x3; val_offset:1278*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1278*FLEN/8, x4, x1, x2) + +inst_672: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x7e01; + valaddr_reg:x3; val_offset:1280*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1280*FLEN/8, x4, x1, x2) + +inst_673: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xfe55; + valaddr_reg:x3; val_offset:1282*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1282*FLEN/8, x4, x1, x2) + +inst_674: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x7c01; + valaddr_reg:x3; val_offset:1284*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1284*FLEN/8, x4, x1, x2) + +inst_675: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xfd55; + valaddr_reg:x3; val_offset:1286*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1286*FLEN/8, x4, x1, x2) + +inst_676: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x8000; + valaddr_reg:x3; val_offset:1288*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1288*FLEN/8, x4, x1, x2) + +inst_677: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x2; + valaddr_reg:x3; val_offset:1290*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1290*FLEN/8, x4, x1, x2) + +inst_678: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x8401; + valaddr_reg:x3; val_offset:1292*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1292*FLEN/8, x4, x1, x2) + +inst_679: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x84aa; + valaddr_reg:x3; val_offset:1294*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 1294*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32770,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(1022,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(682,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(33450,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(1025,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(33793,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(1109,32,FLEN) +test_dataset_1: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(1194,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(21504,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(54272,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(10240,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(43008,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31744,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32256,32,FLEN) +test_dataset_2: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32257,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31745,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(2,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32770,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1022,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33790,16,FLEN) +test_dataset_3: +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(682,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33450,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33793,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1109,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1194,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33962,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(21504,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(54272,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(10240,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(43008,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(32770,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(1022,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(682,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(33450,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(2,16,FLEN) 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+NAN_BOXED(65024,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(32770,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(1022,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(682,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(33450,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(33793,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(1109,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(1194,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(33962,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(21504,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(54272,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(10240,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(43008,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(32770,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(1022,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(682,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(33450,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(33793,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(1109,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(1194,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(33962,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(21504,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(54272,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(10240,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(43008,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32770,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(1022,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(682,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(33450,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(33793,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(1109,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(1194,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(33962,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(21504,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(54272,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(10240,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(43008,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32770,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(1022,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(682,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(33450,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(33793,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(1109,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(1194,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(33962,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(21504,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(54272,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(10240,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(43008,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(33793,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(33962,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x15_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x15_1: + .fill 32*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x5_0: + .fill 30*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_0: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_2: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_3: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_4: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_5: + .fill 18*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fdiv_b3-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fdiv_b3-01.S new file mode 100644 index 000000000..e45a0b8aa --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fdiv_b3-01.S @@ -0,0 +1,11334 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 05:22:24 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fdiv.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fdiv.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fdiv_b3 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fdiv_b3) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x6,test_dataset_0) +RVTEST_SIGBASE(x3,signature_x3_1) + +inst_0: +// rs1 == rd != rs2, rs1==x28, rs2==x24, rd==x28,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x28; op2:x24; dest:x28; op1val:0x739c; op2val:0x7bff; + valaddr_reg:x6; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fdiv.h, x28, x28, x24, dyn, 0, 0, x6, 0*FLEN/8, x8, x3, x5) + +inst_1: +// rs1 == rs2 != rd, rs1==x29, rs2==x29, rd==x0,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x29; op2:x29; dest:x0; op1val:0x739c; op2val:0x739c; + valaddr_reg:x6; val_offset:2*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fdiv.h, x0, x29, x29, dyn, 32, 0, x6, 2*FLEN/8, x8, x3, x5) + +inst_2: +// rs1 == rs2 == rd, rs1==x31, rs2==x31, rd==x31,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x31; op2:x31; dest:x31; op1val:0x739c; op2val:0x739c; + valaddr_reg:x6; val_offset:4*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fdiv.h, x31, x31, x31, dyn, 64, 0, x6, 4*FLEN/8, x8, x3, x5) + +inst_3: +// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==x18, rs2==x22, rd==x19,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x18; op2:x22; dest:x19; op1val:0x739c; op2val:0x7bff; + valaddr_reg:x6; val_offset:6*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fdiv.h, x19, x18, x22, dyn, 96, 0, x6, 6*FLEN/8, x8, x3, x5) + +inst_4: +// rs2 == rd != rs1, rs1==x10, rs2==x27, rd==x27,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x10; op2:x27; dest:x27; op1val:0x739c; op2val:0x7bff; + valaddr_reg:x6; val_offset:8*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fdiv.h, x27, x10, x27, dyn, 128, 0, x6, 8*FLEN/8, x8, x3, x5) + +inst_5: +// rs1==x20, rs2==x4, rd==x23,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ea and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x20; op2:x4; dest:x23; op1val:0x75ea; op2val:0x7bff; + valaddr_reg:x6; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fdiv.h, x23, x20, x4, dyn, 0, 0, x6, 10*FLEN/8, x8, x3, x5) + +inst_6: +// rs1==x1, rs2==x26, rd==x20,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ea and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x1; op2:x26; dest:x20; op1val:0x75ea; op2val:0x7bff; + valaddr_reg:x6; val_offset:12*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fdiv.h, x20, x1, x26, dyn, 32, 0, x6, 12*FLEN/8, x8, x3, x5) + +inst_7: +// rs1==x7, rs2==x21, rd==x30,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ea and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x7; op2:x21; dest:x30; op1val:0x75ea; op2val:0x7bff; + valaddr_reg:x6; val_offset:14*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fdiv.h, x30, x7, x21, dyn, 64, 0, x6, 14*FLEN/8, x8, x3, x5) + +inst_8: +// rs1==x24, rs2==x7, rd==x1,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ea and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x24; op2:x7; dest:x1; op1val:0x75ea; op2val:0x7bff; + valaddr_reg:x6; val_offset:16*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fdiv.h, x1, x24, x7, dyn, 96, 0, x6, 16*FLEN/8, x8, x3, x5) + +inst_9: +// rs1==x11, rs2==x9, rd==x17,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ea and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x11; op2:x9; dest:x17; op1val:0x75ea; op2val:0x7bff; + valaddr_reg:x6; val_offset:18*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fdiv.h, x17, x11, x9, dyn, 128, 0, x6, 18*FLEN/8, x8, x3, x5) + +inst_10: +// rs1==x4, rs2==x16, rd==x13,fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x4; op2:x16; dest:x13; op1val:0x7900; op2val:0x7bff; + valaddr_reg:x6; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fdiv.h, x13, x4, x16, dyn, 0, 0, x6, 20*FLEN/8, x8, x3, x5) + +inst_11: +// rs1==x23, rs2==x2, rd==x11,fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x23; op2:x2; dest:x11; op1val:0x7900; op2val:0x7bff; + valaddr_reg:x6; val_offset:22*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fdiv.h, x11, x23, x2, dyn, 32, 0, x6, 22*FLEN/8, x8, x3, x5) +RVTEST_VALBASEUPD(x4,test_dataset_1) + +inst_12: +// rs1==x12, rs2==x6, rd==x21,fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x12; op2:x6; dest:x21; op1val:0x7900; op2val:0x7bff; + valaddr_reg:x4; val_offset:0*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fdiv.h, x21, x12, x6, dyn, 64, 0, x4, 0*FLEN/8, x11, x3, x5) + +inst_13: +// rs1==x25, rs2==x30, rd==x7,fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x25; op2:x30; dest:x7; op1val:0x7900; op2val:0x7bff; + valaddr_reg:x4; val_offset:2*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x7, x25, x30, dyn, 96, 0, x4, 2*FLEN/8, x11, x3, x2) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_14: +// rs1==x26, rs2==x14, rd==x12,fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x26; op2:x14; dest:x12; op1val:0x7900; op2val:0x7bff; + valaddr_reg:x4; val_offset:4*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x12, x26, x14, dyn, 128, 0, x4, 4*FLEN/8, x11, x1, x2) + +inst_15: +// rs1==x14, rs2==x0, rd==x26,fs1 == 0 and fe1 == 0x18 and fm1 == 0x2bf and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x14; op2:x0; dest:x26; op1val:0x62bf; op2val:0x0; + valaddr_reg:x4; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x26, x14, x0, dyn, 0, 0, x4, 6*FLEN/8, x11, x1, x2) + +inst_16: +// rs1==x8, rs2==x15, rd==x5,fs1 == 0 and fe1 == 0x18 and fm1 == 0x2bf and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x8; op2:x15; dest:x5; op1val:0x62bf; op2val:0x7bff; + valaddr_reg:x4; val_offset:8*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x5, x8, x15, dyn, 32, 0, x4, 8*FLEN/8, x11, x1, x2) + +inst_17: +// rs1==x16, rs2==x23, rd==x22,fs1 == 0 and fe1 == 0x18 and fm1 == 0x2bf and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x16; op2:x23; dest:x22; op1val:0x62bf; op2val:0x7bff; + valaddr_reg:x4; val_offset:10*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x22, x16, x23, dyn, 64, 0, x4, 10*FLEN/8, x11, x1, x2) + +inst_18: +// rs1==x30, rs2==x17, rd==x9,fs1 == 0 and fe1 == 0x18 and fm1 == 0x2bf and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x17; dest:x9; op1val:0x62bf; op2val:0x7bff; + valaddr_reg:x4; val_offset:12*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x9, x30, x17, dyn, 96, 0, x4, 12*FLEN/8, x11, x1, x2) + +inst_19: +// rs1==x27, rs2==x10, rd==x3,fs1 == 0 and fe1 == 0x18 and fm1 == 0x2bf and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x27; op2:x10; dest:x3; op1val:0x62bf; op2val:0x7bff; + valaddr_reg:x4; val_offset:14*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x3, x27, x10, dyn, 128, 0, x4, 14*FLEN/8, x11, x1, x2) + +inst_20: +// rs1==x15, rs2==x12, rd==x18,fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x15; op2:x12; dest:x18; op1val:0x7425; op2val:0x7bff; + valaddr_reg:x4; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x18, x15, x12, dyn, 0, 0, x4, 16*FLEN/8, x11, x1, x2) + +inst_21: +// rs1==x0, rs2==x5, rd==x24,fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x0; op2:x5; dest:x24; op1val:0x0; op2val:0x7bff; + valaddr_reg:x4; val_offset:18*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x24, x0, x5, dyn, 32, 0, x4, 18*FLEN/8, x11, x1, x2) + +inst_22: +// rs1==x21, rs2==x8, rd==x14,fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x21; op2:x8; dest:x14; op1val:0x7425; op2val:0x7bff; + valaddr_reg:x4; val_offset:20*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x14, x21, x8, dyn, 64, 0, x4, 20*FLEN/8, x11, x1, x2) + +inst_23: +// rs1==x22, rs2==x13, rd==x10,fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x22; op2:x13; dest:x10; op1val:0x7425; op2val:0x7bff; + valaddr_reg:x4; val_offset:22*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x10, x22, x13, dyn, 96, 0, x4, 22*FLEN/8, x11, x1, x2) + +inst_24: +// rs1==x6, rs2==x25, rd==x29,fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x6; op2:x25; dest:x29; op1val:0x7425; op2val:0x7bff; + valaddr_reg:x4; val_offset:24*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x29, x6, x25, dyn, 128, 0, x4, 24*FLEN/8, x11, x1, x2) +RVTEST_VALBASEUPD(x10,test_dataset_2) + +inst_25: +// rs1==x13, rs2==x28, rd==x4,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x13; op2:x28; dest:x4; op1val:0x7bf6; op2val:0x7bff; + valaddr_reg:x10; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x4, x13, x28, dyn, 0, 0, x10, 0*FLEN/8, x12, x1, x2) + +inst_26: +// rs1==x19, rs2==x3, rd==x2,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x19; op2:x3; dest:x2; op1val:0x7bf6; op2val:0x7bff; + valaddr_reg:x10; val_offset:2*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x2, x19, x3, dyn, 32, 0, x10, 2*FLEN/8, x12, x1, x7) +RVTEST_SIGBASE(x4,signature_x4_0) + +inst_27: +// rs1==x2, rs2==x20, rd==x8,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x2; op2:x20; dest:x8; op1val:0x7bf6; op2val:0x7bff; + valaddr_reg:x10; val_offset:4*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x8, x2, x20, dyn, 64, 0, x10, 4*FLEN/8, x12, x4, x7) + +inst_28: +// rs1==x17, rs2==x18, rd==x25,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x17; op2:x18; dest:x25; op1val:0x7bf6; op2val:0x7bff; + valaddr_reg:x10; val_offset:6*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x25, x17, x18, dyn, 96, 0, x10, 6*FLEN/8, x12, x4, x7) + +inst_29: +// rs1==x3, rs2==x11, rd==x16,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x3; op2:x11; dest:x16; op1val:0x7bf6; op2val:0x7bff; + valaddr_reg:x10; val_offset:8*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x16, x3, x11, dyn, 128, 0, x10, 8*FLEN/8, x12, x4, x7) + +inst_30: +// rs1==x5, rs2==x1, rd==x6,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x5; op2:x1; dest:x6; op1val:0x7ab0; op2val:0x7bff; + valaddr_reg:x10; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x6, x5, x1, dyn, 0, 0, x10, 10*FLEN/8, x12, x4, x7) + +inst_31: +// rs1==x9, rs2==x19, rd==x15,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x9; op2:x19; dest:x15; op1val:0x7ab0; op2val:0x7bff; + valaddr_reg:x10; val_offset:12*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x15, x9, x19, dyn, 32, 0, x10, 12*FLEN/8, x12, x4, x7) + +inst_32: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab0; op2val:0x7bff; + valaddr_reg:x10; val_offset:14*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 14*FLEN/8, x12, x4, x7) + +inst_33: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab0; op2val:0x7bff; + valaddr_reg:x10; val_offset:16*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 16*FLEN/8, x12, x4, x7) + +inst_34: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab0; op2val:0x7bff; + valaddr_reg:x10; val_offset:18*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 18*FLEN/8, x12, x4, x7) + +inst_35: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x11c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x791c; op2val:0xfbff; + valaddr_reg:x10; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 20*FLEN/8, x12, x4, x7) + +inst_36: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x11c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x791c; op2val:0xfbff; + valaddr_reg:x10; val_offset:22*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 22*FLEN/8, x12, x4, x7) + +inst_37: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x11c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x791c; op2val:0xfbff; + valaddr_reg:x10; val_offset:24*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 24*FLEN/8, x12, x4, x7) + +inst_38: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x11c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x791c; op2val:0xfbff; + valaddr_reg:x10; val_offset:26*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 26*FLEN/8, x12, x4, x7) + +inst_39: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x11c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x791c; op2val:0xfbff; + valaddr_reg:x10; val_offset:28*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 28*FLEN/8, x12, x4, x7) + +inst_40: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0xfbff; + valaddr_reg:x10; val_offset:30*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 30*FLEN/8, x12, x4, x7) + +inst_41: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0xfbff; + valaddr_reg:x10; val_offset:32*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 32*FLEN/8, x12, x4, x7) + +inst_42: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0xfbff; + valaddr_reg:x10; val_offset:34*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 34*FLEN/8, x12, x4, x7) + +inst_43: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0xfbff; + valaddr_reg:x10; val_offset:36*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 36*FLEN/8, x12, x4, x7) + +inst_44: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0xfbff; + valaddr_reg:x10; val_offset:38*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 38*FLEN/8, x12, x4, x7) + +inst_45: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x782e; op2val:0xfbff; + valaddr_reg:x10; val_offset:40*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 40*FLEN/8, x12, x4, x7) + +inst_46: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x782e; op2val:0xfbff; + valaddr_reg:x10; val_offset:42*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 42*FLEN/8, x12, x4, x7) + +inst_47: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x782e; op2val:0xfbff; + valaddr_reg:x10; val_offset:44*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 44*FLEN/8, x12, x4, x7) + +inst_48: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x782e; op2val:0xfbff; + valaddr_reg:x10; val_offset:46*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 46*FLEN/8, x12, x4, x7) + +inst_49: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x782e; op2val:0xfbff; + valaddr_reg:x10; val_offset:48*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 48*FLEN/8, x12, x4, x7) + +inst_50: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x795e; op2val:0xfbff; + valaddr_reg:x10; val_offset:50*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 50*FLEN/8, x12, x4, x7) + +inst_51: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x795e; op2val:0xfbff; + valaddr_reg:x10; val_offset:52*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 52*FLEN/8, x12, x4, x7) + +inst_52: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x795e; op2val:0xfbff; + valaddr_reg:x10; val_offset:54*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 54*FLEN/8, x12, x4, x7) + +inst_53: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x795e; op2val:0xfbff; + valaddr_reg:x10; val_offset:56*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 56*FLEN/8, x12, x4, x7) + +inst_54: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x795e; op2val:0xfbff; + valaddr_reg:x10; val_offset:58*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 58*FLEN/8, x12, x4, x7) + +inst_55: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x210 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a10; op2val:0xfbff; + valaddr_reg:x10; val_offset:60*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 60*FLEN/8, x12, x4, x7) + +inst_56: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x210 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a10; op2val:0xfbff; + valaddr_reg:x10; val_offset:62*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 62*FLEN/8, x12, x4, x7) + +inst_57: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x210 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a10; op2val:0xfbff; + valaddr_reg:x10; val_offset:64*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 64*FLEN/8, x12, x4, x7) + +inst_58: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x210 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a10; op2val:0xfbff; + valaddr_reg:x10; val_offset:66*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 66*FLEN/8, x12, x4, x7) + +inst_59: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x210 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a10; op2val:0xfbff; + valaddr_reg:x10; val_offset:68*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 68*FLEN/8, x12, x4, x7) + +inst_60: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d1 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74d1; op2val:0xfbff; + valaddr_reg:x10; val_offset:70*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 70*FLEN/8, x12, x4, x7) + +inst_61: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d1 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74d1; op2val:0xfbff; + valaddr_reg:x10; val_offset:72*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 72*FLEN/8, x12, x4, x7) + +inst_62: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d1 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74d1; op2val:0xfbff; + valaddr_reg:x10; val_offset:74*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 74*FLEN/8, x12, x4, x7) + +inst_63: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d1 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74d1; op2val:0xfbff; + valaddr_reg:x10; val_offset:76*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 76*FLEN/8, x12, x4, x7) + +inst_64: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d1 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74d1; op2val:0xfbff; + valaddr_reg:x10; val_offset:78*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 78*FLEN/8, x12, x4, x7) + +inst_65: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2eb and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aeb; op2val:0xfbff; + valaddr_reg:x10; val_offset:80*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 80*FLEN/8, x12, x4, x7) + +inst_66: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2eb and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aeb; op2val:0xfbff; + valaddr_reg:x10; val_offset:82*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 82*FLEN/8, x12, x4, x7) + +inst_67: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2eb and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aeb; op2val:0xfbff; + valaddr_reg:x10; val_offset:84*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 84*FLEN/8, x12, x4, x7) + +inst_68: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2eb and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aeb; op2val:0xfbff; + valaddr_reg:x10; val_offset:86*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 86*FLEN/8, x12, x4, x7) + +inst_69: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2eb and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aeb; op2val:0xfbff; + valaddr_reg:x10; val_offset:88*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 88*FLEN/8, x12, x4, x7) + +inst_70: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1bf and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79bf; op2val:0xfbff; + valaddr_reg:x10; val_offset:90*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 90*FLEN/8, x12, x4, x7) + +inst_71: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1bf and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79bf; op2val:0xfbff; + valaddr_reg:x10; val_offset:92*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 92*FLEN/8, x12, x4, x7) + +inst_72: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1bf and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79bf; op2val:0xfbff; + valaddr_reg:x10; val_offset:94*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 94*FLEN/8, x12, x4, x7) + +inst_73: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1bf and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79bf; op2val:0xfbff; + valaddr_reg:x10; val_offset:96*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 96*FLEN/8, x12, x4, x7) + +inst_74: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1bf and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79bf; op2val:0xfbff; + valaddr_reg:x10; val_offset:98*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 98*FLEN/8, x12, x4, x7) + +inst_75: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b5 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b5; op2val:0xfbff; + valaddr_reg:x10; val_offset:100*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 100*FLEN/8, x12, x4, x7) + +inst_76: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b5 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b5; op2val:0xfbff; + valaddr_reg:x10; val_offset:102*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 102*FLEN/8, x12, x4, x7) + +inst_77: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b5 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b5; op2val:0xfbff; + valaddr_reg:x10; val_offset:104*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 104*FLEN/8, x12, x4, x7) + +inst_78: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b5 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b5; op2val:0xfbff; + valaddr_reg:x10; val_offset:106*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 106*FLEN/8, x12, x4, x7) + +inst_79: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b5 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b5; op2val:0xfbff; + valaddr_reg:x10; val_offset:108*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 108*FLEN/8, x12, x4, x7) + +inst_80: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x251 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7651; op2val:0xfbff; + valaddr_reg:x10; val_offset:110*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 110*FLEN/8, x12, x4, x7) + +inst_81: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x251 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7651; op2val:0xfbff; + valaddr_reg:x10; val_offset:112*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 112*FLEN/8, x12, x4, x7) + +inst_82: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x251 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7651; op2val:0xfbff; + valaddr_reg:x10; val_offset:114*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 114*FLEN/8, x12, x4, x7) + +inst_83: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x251 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7651; op2val:0xfbff; + valaddr_reg:x10; val_offset:116*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 116*FLEN/8, x12, x4, x7) + +inst_84: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x251 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7651; op2val:0xfbff; + valaddr_reg:x10; val_offset:118*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 118*FLEN/8, x12, x4, x7) + +inst_85: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x771c; op2val:0xfbff; + valaddr_reg:x10; val_offset:120*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 120*FLEN/8, x12, x4, x7) + +inst_86: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x771c; op2val:0xfbff; + valaddr_reg:x10; val_offset:122*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 122*FLEN/8, x12, x4, x7) + +inst_87: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x771c; op2val:0xfbff; + valaddr_reg:x10; val_offset:124*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 124*FLEN/8, x12, x4, x7) + +inst_88: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x771c; op2val:0xfbff; + valaddr_reg:x10; val_offset:126*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 126*FLEN/8, x12, x4, x7) + +inst_89: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x771c; op2val:0xfbff; + valaddr_reg:x10; val_offset:128*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 128*FLEN/8, x12, x4, x7) + +inst_90: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x307 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b07; op2val:0xfbff; + valaddr_reg:x10; val_offset:130*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 130*FLEN/8, x12, x4, x7) + +inst_91: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x307 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b07; op2val:0xfbff; + valaddr_reg:x10; val_offset:132*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 132*FLEN/8, x12, x4, x7) + +inst_92: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x307 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b07; op2val:0xfbff; + valaddr_reg:x10; val_offset:134*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 134*FLEN/8, x12, x4, x7) + +inst_93: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x307 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b07; op2val:0xfbff; + valaddr_reg:x10; val_offset:136*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 136*FLEN/8, x12, x4, x7) + +inst_94: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x307 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b07; op2val:0xfbff; + valaddr_reg:x10; val_offset:138*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 138*FLEN/8, x12, x4, x7) + +inst_95: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x059 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7059; op2val:0xfbff; + valaddr_reg:x10; val_offset:140*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 140*FLEN/8, x12, x4, x7) + +inst_96: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x059 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7059; op2val:0xfbff; + valaddr_reg:x10; val_offset:142*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 142*FLEN/8, x12, x4, x7) + +inst_97: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x059 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7059; op2val:0xfbff; + valaddr_reg:x10; val_offset:144*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 144*FLEN/8, x12, x4, x7) + +inst_98: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x059 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7059; op2val:0xfbff; + valaddr_reg:x10; val_offset:146*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 146*FLEN/8, x12, x4, x7) + +inst_99: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x059 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7059; op2val:0xfbff; + valaddr_reg:x10; val_offset:148*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 148*FLEN/8, x12, x4, x7) + +inst_100: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b8 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb8; op2val:0xfbff; + valaddr_reg:x10; val_offset:150*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 150*FLEN/8, x12, x4, x7) + +inst_101: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b8 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb8; op2val:0xfbff; + valaddr_reg:x10; val_offset:152*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 152*FLEN/8, x12, x4, x7) + +inst_102: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b8 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb8; op2val:0xfbff; + valaddr_reg:x10; val_offset:154*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 154*FLEN/8, x12, x4, x7) + +inst_103: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b8 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb8; op2val:0xfbff; + valaddr_reg:x10; val_offset:156*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 156*FLEN/8, x12, x4, x7) + +inst_104: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b8 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb8; op2val:0xfbff; + valaddr_reg:x10; val_offset:158*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 158*FLEN/8, x12, x4, x7) + +inst_105: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x102 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7902; op2val:0x7bff; + valaddr_reg:x10; val_offset:160*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 160*FLEN/8, x12, x4, x7) + +inst_106: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x102 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7902; op2val:0x7bff; + valaddr_reg:x10; val_offset:162*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 162*FLEN/8, x12, x4, x7) + +inst_107: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x102 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7902; op2val:0x7bff; + valaddr_reg:x10; val_offset:164*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 164*FLEN/8, x12, x4, x7) + +inst_108: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x102 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7902; op2val:0x7bff; + valaddr_reg:x10; val_offset:166*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 166*FLEN/8, x12, x4, x7) + +inst_109: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x102 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7902; op2val:0x7bff; + valaddr_reg:x10; val_offset:168*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 168*FLEN/8, x12, x4, x7) + +inst_110: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x780e; op2val:0x7bff; + valaddr_reg:x10; val_offset:170*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 170*FLEN/8, x12, x4, x7) + +inst_111: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x780e; op2val:0x7bff; + valaddr_reg:x10; val_offset:172*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 172*FLEN/8, x12, x4, x7) + +inst_112: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x780e; op2val:0x7bff; + valaddr_reg:x10; val_offset:174*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 174*FLEN/8, x12, x4, x7) + +inst_113: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x780e; op2val:0x7bff; + valaddr_reg:x10; val_offset:176*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 176*FLEN/8, x12, x4, x7) + +inst_114: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x780e; op2val:0x7bff; + valaddr_reg:x10; val_offset:178*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 178*FLEN/8, x12, x4, x7) + +inst_115: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x19c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x759c; op2val:0x7bff; + valaddr_reg:x10; val_offset:180*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 180*FLEN/8, x12, x4, x7) + +inst_116: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x19c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x759c; op2val:0x7bff; + valaddr_reg:x10; val_offset:182*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 182*FLEN/8, x12, x4, x7) + +inst_117: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x19c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x759c; op2val:0x7bff; + valaddr_reg:x10; val_offset:184*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 184*FLEN/8, x12, x4, x7) + +inst_118: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x19c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x759c; op2val:0x7bff; + valaddr_reg:x10; val_offset:186*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 186*FLEN/8, x12, x4, x7) + +inst_119: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x19c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x759c; op2val:0x7bff; + valaddr_reg:x10; val_offset:188*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 188*FLEN/8, x12, x4, x7) + +inst_120: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ab and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78ab; op2val:0x7bff; + valaddr_reg:x10; val_offset:190*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 190*FLEN/8, x12, x4, x7) + +inst_121: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ab and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78ab; op2val:0x7bff; + valaddr_reg:x10; val_offset:192*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 192*FLEN/8, x12, x4, x7) + +inst_122: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ab and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78ab; op2val:0x7bff; + valaddr_reg:x10; val_offset:194*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 194*FLEN/8, x12, x4, x7) + +inst_123: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ab and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78ab; op2val:0x7bff; + valaddr_reg:x10; val_offset:196*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 196*FLEN/8, x12, x4, x7) + +inst_124: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ab and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78ab; op2val:0x7bff; + valaddr_reg:x10; val_offset:198*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 198*FLEN/8, x12, x4, x7) + +inst_125: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x174 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7974; op2val:0x7bff; + valaddr_reg:x10; val_offset:200*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 200*FLEN/8, x12, x4, x7) + +inst_126: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x174 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7974; op2val:0x7bff; + valaddr_reg:x10; val_offset:202*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 202*FLEN/8, x12, x4, x7) + +inst_127: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x174 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7974; op2val:0x7bff; + valaddr_reg:x10; val_offset:204*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 204*FLEN/8, x12, x4, x7) + +inst_128: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x174 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7974; op2val:0x7bff; + valaddr_reg:x10; val_offset:206*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 206*FLEN/8, x12, x4, x7) + +inst_129: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x174 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7974; op2val:0x7bff; + valaddr_reg:x10; val_offset:208*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 208*FLEN/8, x12, x4, x7) + +inst_130: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ad9; op2val:0x7bff; + valaddr_reg:x10; val_offset:210*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 210*FLEN/8, x12, x4, x7) + +inst_131: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ad9; op2val:0x7bff; + valaddr_reg:x10; val_offset:212*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 212*FLEN/8, x12, x4, x7) + +inst_132: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ad9; op2val:0x7bff; + valaddr_reg:x10; val_offset:214*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 214*FLEN/8, x12, x4, x7) + +inst_133: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ad9; op2val:0x7bff; + valaddr_reg:x10; val_offset:216*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 216*FLEN/8, x12, x4, x7) + +inst_134: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ad9; op2val:0x7bff; + valaddr_reg:x10; val_offset:218*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 218*FLEN/8, x12, x4, x7) + +inst_135: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x795e; op2val:0x7bff; + valaddr_reg:x10; val_offset:220*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 220*FLEN/8, x12, x4, x7) + +inst_136: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x795e; op2val:0x7bff; + valaddr_reg:x10; val_offset:222*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 222*FLEN/8, x12, x4, x7) + +inst_137: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x795e; op2val:0x7bff; + valaddr_reg:x10; val_offset:224*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 224*FLEN/8, x12, x4, x7) + +inst_138: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x795e; op2val:0x7bff; + valaddr_reg:x10; val_offset:226*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 226*FLEN/8, x12, x4, x7) + +inst_139: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x795e; op2val:0x7bff; + valaddr_reg:x10; val_offset:228*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 228*FLEN/8, x12, x4, x7) + +inst_140: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ae1; op2val:0x7bff; + valaddr_reg:x10; val_offset:230*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 230*FLEN/8, x12, x4, x7) + +inst_141: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ae1; op2val:0x7bff; + valaddr_reg:x10; val_offset:232*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 232*FLEN/8, x12, x4, x7) + +inst_142: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ae1; op2val:0x7bff; + valaddr_reg:x10; val_offset:234*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 234*FLEN/8, x12, x4, x7) + +inst_143: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ae1; op2val:0x7bff; + valaddr_reg:x10; val_offset:236*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 236*FLEN/8, x12, x4, x7) + +inst_144: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ae1; op2val:0x7bff; + valaddr_reg:x10; val_offset:238*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 238*FLEN/8, x12, x4, x7) + +inst_145: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x33b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b3b; op2val:0x7bff; + valaddr_reg:x10; val_offset:240*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 240*FLEN/8, x12, x4, x7) + +inst_146: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x33b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b3b; op2val:0x7bff; + valaddr_reg:x10; val_offset:242*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 242*FLEN/8, x12, x4, x7) + +inst_147: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x33b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b3b; op2val:0x7bff; + valaddr_reg:x10; val_offset:244*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 244*FLEN/8, x12, x4, x7) + +inst_148: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x33b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b3b; op2val:0x7bff; + valaddr_reg:x10; val_offset:246*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 246*FLEN/8, x12, x4, x7) + +inst_149: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x33b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b3b; op2val:0x7bff; + valaddr_reg:x10; val_offset:248*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 248*FLEN/8, x12, x4, x7) + +inst_150: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b5; op2val:0x7bff; + valaddr_reg:x10; val_offset:250*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 250*FLEN/8, x12, x4, x7) + +inst_151: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b5; op2val:0x7bff; + valaddr_reg:x10; val_offset:252*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 252*FLEN/8, x12, x4, x7) + +inst_152: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b5; op2val:0x7bff; + valaddr_reg:x10; val_offset:254*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 254*FLEN/8, x12, x4, x7) + +inst_153: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b5; op2val:0x7bff; + valaddr_reg:x10; val_offset:256*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 256*FLEN/8, x12, x4, x7) + +inst_154: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b5; op2val:0x7bff; + valaddr_reg:x10; val_offset:258*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 258*FLEN/8, x12, x4, x7) +RVTEST_SIGBASE(x4,signature_x4_1) + +inst_155: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aa6; op2val:0x7bff; + valaddr_reg:x10; val_offset:260*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 260*FLEN/8, x12, x4, x7) + +inst_156: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aa6; op2val:0x7bff; + valaddr_reg:x10; val_offset:262*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 262*FLEN/8, x12, x4, x7) + +inst_157: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aa6; op2val:0x7bff; + valaddr_reg:x10; val_offset:264*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 264*FLEN/8, x12, x4, x7) + +inst_158: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aa6; op2val:0x7bff; + valaddr_reg:x10; val_offset:266*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 266*FLEN/8, x12, x4, x7) + +inst_159: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aa6; op2val:0x7bff; + valaddr_reg:x10; val_offset:268*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 268*FLEN/8, x12, x4, x7) + +inst_160: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x08e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x748e; op2val:0x7bff; + valaddr_reg:x10; val_offset:270*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 270*FLEN/8, x12, x4, x7) + +inst_161: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x08e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x748e; op2val:0x7bff; + valaddr_reg:x10; val_offset:272*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 272*FLEN/8, x12, x4, x7) + +inst_162: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x08e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x748e; op2val:0x7bff; + valaddr_reg:x10; val_offset:274*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 274*FLEN/8, x12, x4, x7) + +inst_163: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x08e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x748e; op2val:0x7bff; + valaddr_reg:x10; val_offset:276*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 276*FLEN/8, x12, x4, x7) + +inst_164: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x08e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x748e; op2val:0x7bff; + valaddr_reg:x10; val_offset:278*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 278*FLEN/8, x12, x4, x7) + +inst_165: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ad4; op2val:0x7bff; + valaddr_reg:x10; val_offset:280*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 280*FLEN/8, x12, x4, x7) + +inst_166: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ad4; op2val:0x7bff; + valaddr_reg:x10; val_offset:282*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 282*FLEN/8, x12, x4, x7) + +inst_167: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ad4; op2val:0x7bff; + valaddr_reg:x10; val_offset:284*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 284*FLEN/8, x12, x4, x7) + +inst_168: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ad4; op2val:0x7bff; + valaddr_reg:x10; val_offset:286*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 286*FLEN/8, x12, x4, x7) + +inst_169: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ad4; op2val:0x7bff; + valaddr_reg:x10; val_offset:288*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 288*FLEN/8, x12, x4, x7) + +inst_170: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1a9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6da9; op2val:0x7bff; + valaddr_reg:x10; val_offset:290*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 290*FLEN/8, x12, x4, x7) + +inst_171: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1a9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6da9; op2val:0x7bff; + valaddr_reg:x10; val_offset:292*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 292*FLEN/8, x12, x4, x7) + +inst_172: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1a9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6da9; op2val:0x7bff; + valaddr_reg:x10; val_offset:294*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 294*FLEN/8, x12, x4, x7) + +inst_173: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1a9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6da9; op2val:0x7bff; + valaddr_reg:x10; val_offset:296*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 296*FLEN/8, x12, x4, x7) + +inst_174: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1a9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6da9; op2val:0x7bff; + valaddr_reg:x10; val_offset:298*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 298*FLEN/8, x12, x4, x7) + +inst_175: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x290 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7690; op2val:0xfbff; + valaddr_reg:x10; val_offset:300*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 300*FLEN/8, x12, x4, x7) + +inst_176: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x290 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7690; op2val:0xfbff; + valaddr_reg:x10; val_offset:302*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 302*FLEN/8, x12, x4, x7) + +inst_177: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x290 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7690; op2val:0xfbff; + valaddr_reg:x10; val_offset:304*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 304*FLEN/8, x12, x4, x7) + +inst_178: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x290 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7690; op2val:0xfbff; + valaddr_reg:x10; val_offset:306*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 306*FLEN/8, x12, x4, x7) + +inst_179: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x290 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7690; op2val:0xfbff; + valaddr_reg:x10; val_offset:308*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 308*FLEN/8, x12, x4, x7) + +inst_180: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0b3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74b3; op2val:0xfbff; + valaddr_reg:x10; val_offset:310*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 310*FLEN/8, x12, x4, x7) + +inst_181: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0b3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74b3; op2val:0xfbff; + valaddr_reg:x10; val_offset:312*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 312*FLEN/8, x12, x4, x7) + +inst_182: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0b3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74b3; op2val:0xfbff; + valaddr_reg:x10; val_offset:314*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 314*FLEN/8, x12, x4, x7) + +inst_183: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0b3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74b3; op2val:0xfbff; + valaddr_reg:x10; val_offset:316*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 316*FLEN/8, x12, x4, x7) + +inst_184: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0b3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74b3; op2val:0xfbff; + valaddr_reg:x10; val_offset:318*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 318*FLEN/8, x12, x4, x7) + +inst_185: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2fa and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7afa; op2val:0xfbff; + valaddr_reg:x10; val_offset:320*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 320*FLEN/8, x12, x4, x7) + +inst_186: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2fa and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7afa; op2val:0xfbff; + valaddr_reg:x10; val_offset:322*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 322*FLEN/8, x12, x4, x7) + +inst_187: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2fa and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7afa; op2val:0xfbff; + valaddr_reg:x10; val_offset:324*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 324*FLEN/8, x12, x4, x7) + +inst_188: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2fa and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7afa; op2val:0xfbff; + valaddr_reg:x10; val_offset:326*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 326*FLEN/8, x12, x4, x7) + +inst_189: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2fa and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7afa; op2val:0xfbff; + valaddr_reg:x10; val_offset:328*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 328*FLEN/8, x12, x4, x7) + +inst_190: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78e9; op2val:0xfbff; + valaddr_reg:x10; val_offset:330*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 330*FLEN/8, x12, x4, x7) + +inst_191: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78e9; op2val:0xfbff; + valaddr_reg:x10; val_offset:332*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 332*FLEN/8, x12, x4, x7) + +inst_192: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78e9; op2val:0xfbff; + valaddr_reg:x10; val_offset:334*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 334*FLEN/8, x12, x4, x7) + +inst_193: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78e9; op2val:0xfbff; + valaddr_reg:x10; val_offset:336*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 336*FLEN/8, x12, x4, x7) + +inst_194: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78e9; op2val:0xfbff; + valaddr_reg:x10; val_offset:338*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 338*FLEN/8, x12, x4, x7) + +inst_195: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1be and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79be; op2val:0xfbff; + valaddr_reg:x10; val_offset:340*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 340*FLEN/8, x12, x4, x7) + +inst_196: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1be and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79be; op2val:0xfbff; + valaddr_reg:x10; val_offset:342*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 342*FLEN/8, x12, x4, x7) + +inst_197: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1be and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79be; op2val:0xfbff; + valaddr_reg:x10; val_offset:344*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 344*FLEN/8, x12, x4, x7) + +inst_198: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1be and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79be; op2val:0xfbff; + valaddr_reg:x10; val_offset:346*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 346*FLEN/8, x12, x4, x7) + +inst_199: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1be and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79be; op2val:0xfbff; + valaddr_reg:x10; val_offset:348*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 348*FLEN/8, x12, x4, x7) + +inst_200: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b0b; op2val:0xfbff; + valaddr_reg:x10; val_offset:350*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 350*FLEN/8, x12, x4, x7) + +inst_201: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b0b; op2val:0xfbff; + valaddr_reg:x10; val_offset:352*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 352*FLEN/8, x12, x4, x7) + +inst_202: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b0b; op2val:0xfbff; + valaddr_reg:x10; val_offset:354*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 354*FLEN/8, x12, x4, x7) + +inst_203: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b0b; op2val:0xfbff; + valaddr_reg:x10; val_offset:356*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 356*FLEN/8, x12, x4, x7) + +inst_204: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b0b; op2val:0xfbff; + valaddr_reg:x10; val_offset:358*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 358*FLEN/8, x12, x4, x7) + +inst_205: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x780a; op2val:0xfbff; + valaddr_reg:x10; val_offset:360*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 360*FLEN/8, x12, x4, x7) + +inst_206: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x780a; op2val:0xfbff; + valaddr_reg:x10; val_offset:362*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 362*FLEN/8, x12, x4, x7) + +inst_207: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x780a; op2val:0xfbff; + valaddr_reg:x10; val_offset:364*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 364*FLEN/8, x12, x4, x7) + +inst_208: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x780a; op2val:0xfbff; + valaddr_reg:x10; val_offset:366*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 366*FLEN/8, x12, x4, x7) + +inst_209: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x780a; op2val:0xfbff; + valaddr_reg:x10; val_offset:368*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 368*FLEN/8, x12, x4, x7) + +inst_210: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74f3; op2val:0xfbff; + valaddr_reg:x10; val_offset:370*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 370*FLEN/8, x12, x4, x7) + +inst_211: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74f3; op2val:0xfbff; + valaddr_reg:x10; val_offset:372*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 372*FLEN/8, x12, x4, x7) + +inst_212: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74f3; op2val:0xfbff; + valaddr_reg:x10; val_offset:374*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 374*FLEN/8, x12, x4, x7) + +inst_213: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74f3; op2val:0xfbff; + valaddr_reg:x10; val_offset:376*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 376*FLEN/8, x12, x4, x7) + +inst_214: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74f3; op2val:0xfbff; + valaddr_reg:x10; val_offset:378*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 378*FLEN/8, x12, x4, x7) + +inst_215: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0cb and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78cb; op2val:0xfbff; + valaddr_reg:x10; val_offset:380*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 380*FLEN/8, x12, x4, x7) + +inst_216: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0cb and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78cb; op2val:0xfbff; + valaddr_reg:x10; val_offset:382*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 382*FLEN/8, x12, x4, x7) + +inst_217: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0cb and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78cb; op2val:0xfbff; + valaddr_reg:x10; val_offset:384*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 384*FLEN/8, x12, x4, x7) + +inst_218: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0cb and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78cb; op2val:0xfbff; + valaddr_reg:x10; val_offset:386*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 386*FLEN/8, x12, x4, x7) + +inst_219: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0cb and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78cb; op2val:0xfbff; + valaddr_reg:x10; val_offset:388*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 388*FLEN/8, x12, x4, x7) + +inst_220: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x250 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7250; op2val:0xfbff; + valaddr_reg:x10; val_offset:390*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 390*FLEN/8, x12, x4, x7) + +inst_221: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x250 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7250; op2val:0xfbff; + valaddr_reg:x10; val_offset:392*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 392*FLEN/8, x12, x4, x7) + +inst_222: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x250 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7250; op2val:0xfbff; + valaddr_reg:x10; val_offset:394*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 394*FLEN/8, x12, x4, x7) + +inst_223: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x250 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7250; op2val:0xfbff; + valaddr_reg:x10; val_offset:396*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 396*FLEN/8, x12, x4, x7) + +inst_224: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x250 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7250; op2val:0xfbff; + valaddr_reg:x10; val_offset:398*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 398*FLEN/8, x12, x4, x7) + +inst_225: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e1 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78e1; op2val:0xfbff; + valaddr_reg:x10; val_offset:400*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 400*FLEN/8, x12, x4, x7) + +inst_226: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e1 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78e1; op2val:0xfbff; + valaddr_reg:x10; val_offset:402*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 402*FLEN/8, x12, x4, x7) + +inst_227: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e1 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78e1; op2val:0xfbff; + valaddr_reg:x10; val_offset:404*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 404*FLEN/8, x12, x4, x7) + +inst_228: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e1 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78e1; op2val:0xfbff; + valaddr_reg:x10; val_offset:406*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 406*FLEN/8, x12, x4, x7) + +inst_229: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e1 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78e1; op2val:0xfbff; + valaddr_reg:x10; val_offset:408*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 408*FLEN/8, x12, x4, x7) + +inst_230: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x16e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x696e; op2val:0xfbff; + valaddr_reg:x10; val_offset:410*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 410*FLEN/8, x12, x4, x7) + +inst_231: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x16e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x696e; op2val:0xfbff; + valaddr_reg:x10; val_offset:412*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 412*FLEN/8, x12, x4, x7) + +inst_232: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x16e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x696e; op2val:0xfbff; + valaddr_reg:x10; val_offset:414*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 414*FLEN/8, x12, x4, x7) + +inst_233: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x16e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x696e; op2val:0xfbff; + valaddr_reg:x10; val_offset:416*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 416*FLEN/8, x12, x4, x7) + +inst_234: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x16e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x696e; op2val:0xfbff; + valaddr_reg:x10; val_offset:418*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 418*FLEN/8, x12, x4, x7) + +inst_235: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x104 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7504; op2val:0xfbff; + valaddr_reg:x10; val_offset:420*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 420*FLEN/8, x12, x4, x7) + +inst_236: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x104 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7504; op2val:0xfbff; + valaddr_reg:x10; val_offset:422*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 422*FLEN/8, x12, x4, x7) + +inst_237: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x104 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7504; op2val:0xfbff; + valaddr_reg:x10; val_offset:424*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 424*FLEN/8, x12, x4, x7) + +inst_238: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x104 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7504; op2val:0xfbff; + valaddr_reg:x10; val_offset:426*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 426*FLEN/8, x12, x4, x7) + +inst_239: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x104 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7504; op2val:0xfbff; + valaddr_reg:x10; val_offset:428*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 428*FLEN/8, x12, x4, x7) + +inst_240: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b2b; op2val:0xfbff; + valaddr_reg:x10; val_offset:430*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 430*FLEN/8, x12, x4, x7) + +inst_241: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b2b; op2val:0xfbff; + valaddr_reg:x10; val_offset:432*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 432*FLEN/8, x12, x4, x7) + +inst_242: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b2b; op2val:0xfbff; + valaddr_reg:x10; val_offset:434*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 434*FLEN/8, x12, x4, x7) + +inst_243: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b2b; op2val:0xfbff; + valaddr_reg:x10; val_offset:436*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 436*FLEN/8, x12, x4, x7) + +inst_244: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b2b; op2val:0xfbff; + valaddr_reg:x10; val_offset:438*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 438*FLEN/8, x12, x4, x7) + +inst_245: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x35c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x775c; op2val:0x7bff; + valaddr_reg:x10; val_offset:440*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 440*FLEN/8, x12, x4, x7) + +inst_246: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x35c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x775c; op2val:0x7bff; + valaddr_reg:x10; val_offset:442*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 442*FLEN/8, x12, x4, x7) + +inst_247: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x35c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x775c; op2val:0x7bff; + valaddr_reg:x10; val_offset:444*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 444*FLEN/8, x12, x4, x7) + +inst_248: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x35c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x775c; op2val:0x7bff; + valaddr_reg:x10; val_offset:446*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 446*FLEN/8, x12, x4, x7) + +inst_249: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x35c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x775c; op2val:0x7bff; + valaddr_reg:x10; val_offset:448*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 448*FLEN/8, x12, x4, x7) + +inst_250: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x126 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7926; op2val:0x7bff; + valaddr_reg:x10; val_offset:450*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 450*FLEN/8, x12, x4, x7) + +inst_251: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x126 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7926; op2val:0x7bff; + valaddr_reg:x10; val_offset:452*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 452*FLEN/8, x12, x4, x7) + +inst_252: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x126 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7926; op2val:0x7bff; + valaddr_reg:x10; val_offset:454*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 454*FLEN/8, x12, x4, x7) + +inst_253: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x126 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7926; op2val:0x7bff; + valaddr_reg:x10; val_offset:456*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 456*FLEN/8, x12, x4, x7) + +inst_254: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x126 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7926; op2val:0x7bff; + valaddr_reg:x10; val_offset:458*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 458*FLEN/8, x12, x4, x7) + +inst_255: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x078 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7878; op2val:0x7bff; + valaddr_reg:x10; val_offset:460*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 460*FLEN/8, x12, x4, x7) + +inst_256: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x078 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7878; op2val:0x7bff; + valaddr_reg:x10; val_offset:462*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 462*FLEN/8, x12, x4, x7) + +inst_257: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x078 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7878; op2val:0x7bff; + valaddr_reg:x10; val_offset:464*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 464*FLEN/8, x12, x4, x7) + +inst_258: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x078 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7878; op2val:0x7bff; + valaddr_reg:x10; val_offset:466*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 466*FLEN/8, x12, x4, x7) + +inst_259: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x078 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7878; op2val:0x7bff; + valaddr_reg:x10; val_offset:468*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 468*FLEN/8, x12, x4, x7) + +inst_260: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x385 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b85; op2val:0x7bff; + valaddr_reg:x10; val_offset:470*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 470*FLEN/8, x12, x4, x7) + +inst_261: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x385 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b85; op2val:0x7bff; + valaddr_reg:x10; val_offset:472*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 472*FLEN/8, x12, x4, x7) + +inst_262: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x385 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b85; op2val:0x7bff; + valaddr_reg:x10; val_offset:474*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 474*FLEN/8, x12, x4, x7) + +inst_263: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x385 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b85; op2val:0x7bff; + valaddr_reg:x10; val_offset:476*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 476*FLEN/8, x12, x4, x7) + +inst_264: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x385 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b85; op2val:0x7bff; + valaddr_reg:x10; val_offset:478*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 478*FLEN/8, x12, x4, x7) + +inst_265: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x76e5; op2val:0x7bff; + valaddr_reg:x10; val_offset:480*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 480*FLEN/8, x12, x4, x7) + +inst_266: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x76e5; op2val:0x7bff; + valaddr_reg:x10; val_offset:482*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 482*FLEN/8, x12, x4, x7) + +inst_267: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x76e5; op2val:0x7bff; + valaddr_reg:x10; val_offset:484*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 484*FLEN/8, x12, x4, x7) + +inst_268: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x76e5; op2val:0x7bff; + valaddr_reg:x10; val_offset:486*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 486*FLEN/8, x12, x4, x7) + +inst_269: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x76e5; op2val:0x7bff; + valaddr_reg:x10; val_offset:488*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 488*FLEN/8, x12, x4, x7) + +inst_270: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x399 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7399; op2val:0x7bff; + valaddr_reg:x10; val_offset:490*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 490*FLEN/8, x12, x4, x7) + +inst_271: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x399 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7399; op2val:0x7bff; + valaddr_reg:x10; val_offset:492*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 492*FLEN/8, x12, x4, x7) + +inst_272: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x399 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7399; op2val:0x7bff; + valaddr_reg:x10; val_offset:494*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 494*FLEN/8, x12, x4, x7) + +inst_273: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x399 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7399; op2val:0x7bff; + valaddr_reg:x10; val_offset:496*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 496*FLEN/8, x12, x4, x7) + +inst_274: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x399 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7399; op2val:0x7bff; + valaddr_reg:x10; val_offset:498*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 498*FLEN/8, x12, x4, x7) + +inst_275: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bd1; op2val:0x7bff; + valaddr_reg:x10; val_offset:500*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 500*FLEN/8, x12, x4, x7) + +inst_276: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bd1; op2val:0x7bff; + valaddr_reg:x10; val_offset:502*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 502*FLEN/8, x12, x4, x7) + +inst_277: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bd1; op2val:0x7bff; + valaddr_reg:x10; val_offset:504*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 504*FLEN/8, x12, x4, x7) + +inst_278: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bd1; op2val:0x7bff; + valaddr_reg:x10; val_offset:506*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 506*FLEN/8, x12, x4, x7) + +inst_279: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bd1; op2val:0x7bff; + valaddr_reg:x10; val_offset:508*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 508*FLEN/8, x12, x4, x7) + +inst_280: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x062 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7862; op2val:0x7bff; + valaddr_reg:x10; val_offset:510*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 510*FLEN/8, x12, x4, x7) + +inst_281: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x062 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7862; op2val:0x7bff; + valaddr_reg:x10; val_offset:512*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 512*FLEN/8, x12, x4, x7) + +inst_282: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x062 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7862; op2val:0x7bff; + valaddr_reg:x10; val_offset:514*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 514*FLEN/8, x12, x4, x7) +RVTEST_SIGBASE(x4,signature_x4_2) + +inst_283: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x062 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7862; op2val:0x7bff; + valaddr_reg:x10; val_offset:516*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 516*FLEN/8, x12, x4, x7) + +inst_284: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x062 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7862; op2val:0x7bff; + valaddr_reg:x10; val_offset:518*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 518*FLEN/8, x12, x4, x7) + +inst_285: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x76a3; op2val:0x7bff; + valaddr_reg:x10; val_offset:520*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 520*FLEN/8, x12, x4, x7) + +inst_286: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x76a3; op2val:0x7bff; + valaddr_reg:x10; val_offset:522*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 522*FLEN/8, x12, x4, x7) + +inst_287: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x76a3; op2val:0x7bff; + valaddr_reg:x10; val_offset:524*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 524*FLEN/8, x12, x4, x7) + +inst_288: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x76a3; op2val:0x7bff; + valaddr_reg:x10; val_offset:526*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 526*FLEN/8, x12, x4, x7) + +inst_289: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x76a3; op2val:0x7bff; + valaddr_reg:x10; val_offset:528*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 528*FLEN/8, x12, x4, x7) + +inst_290: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x122 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6522; op2val:0x7bff; + valaddr_reg:x10; val_offset:530*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 530*FLEN/8, x12, x4, x7) + +inst_291: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x122 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6522; op2val:0x7bff; + valaddr_reg:x10; val_offset:532*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 532*FLEN/8, x12, x4, x7) + +inst_292: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x122 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6522; op2val:0x7bff; + valaddr_reg:x10; val_offset:534*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 534*FLEN/8, x12, x4, x7) + +inst_293: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x122 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6522; op2val:0x7bff; + valaddr_reg:x10; val_offset:536*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 536*FLEN/8, x12, x4, x7) + +inst_294: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x122 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6522; op2val:0x7bff; + valaddr_reg:x10; val_offset:538*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 538*FLEN/8, x12, x4, x7) + +inst_295: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x10e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x790e; op2val:0x7bff; + valaddr_reg:x10; val_offset:540*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 540*FLEN/8, x12, x4, x7) + +inst_296: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x10e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x790e; op2val:0x7bff; + valaddr_reg:x10; val_offset:542*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 542*FLEN/8, x12, x4, x7) + +inst_297: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x10e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x790e; op2val:0x7bff; + valaddr_reg:x10; val_offset:544*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 544*FLEN/8, x12, x4, x7) + +inst_298: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x10e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x790e; op2val:0x7bff; + valaddr_reg:x10; val_offset:546*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 546*FLEN/8, x12, x4, x7) + +inst_299: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x10e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x790e; op2val:0x7bff; + valaddr_reg:x10; val_offset:548*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 548*FLEN/8, x12, x4, x7) + +inst_300: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x104 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7904; op2val:0x7bff; + valaddr_reg:x10; val_offset:550*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 550*FLEN/8, x12, x4, x7) + +inst_301: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x104 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7904; op2val:0x7bff; + valaddr_reg:x10; val_offset:552*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 552*FLEN/8, x12, x4, x7) + +inst_302: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x104 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7904; op2val:0x7bff; + valaddr_reg:x10; val_offset:554*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 554*FLEN/8, x12, x4, x7) + +inst_303: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x104 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7904; op2val:0x7bff; + valaddr_reg:x10; val_offset:556*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 556*FLEN/8, x12, x4, x7) + +inst_304: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x104 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7904; op2val:0x7bff; + valaddr_reg:x10; val_offset:558*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 558*FLEN/8, x12, x4, x7) + +inst_305: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x16e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x796e; op2val:0x7bff; + valaddr_reg:x10; val_offset:560*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 560*FLEN/8, x12, x4, x7) + +inst_306: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x16e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x796e; op2val:0x7bff; + valaddr_reg:x10; val_offset:562*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 562*FLEN/8, x12, x4, x7) + +inst_307: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x16e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x796e; op2val:0x7bff; + valaddr_reg:x10; val_offset:564*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 564*FLEN/8, x12, x4, x7) + +inst_308: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x16e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x796e; op2val:0x7bff; + valaddr_reg:x10; val_offset:566*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 566*FLEN/8, x12, x4, x7) + +inst_309: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x16e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x796e; op2val:0x7bff; + valaddr_reg:x10; val_offset:568*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 568*FLEN/8, x12, x4, x7) + +inst_310: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79a7; op2val:0x7bff; + valaddr_reg:x10; val_offset:570*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 570*FLEN/8, x12, x4, x7) + +inst_311: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79a7; op2val:0x7bff; + valaddr_reg:x10; val_offset:572*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 572*FLEN/8, x12, x4, x7) + +inst_312: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79a7; op2val:0x7bff; + valaddr_reg:x10; val_offset:574*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 574*FLEN/8, x12, x4, x7) + +inst_313: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79a7; op2val:0x7bff; + valaddr_reg:x10; val_offset:576*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 576*FLEN/8, x12, x4, x7) + +inst_314: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79a7; op2val:0x7bff; + valaddr_reg:x10; val_offset:578*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 578*FLEN/8, x12, x4, x7) + +inst_315: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x1ae and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x65ae; op2val:0xfbff; + valaddr_reg:x10; val_offset:580*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 580*FLEN/8, x12, x4, x7) + +inst_316: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x1ae and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x65ae; op2val:0xfbff; + valaddr_reg:x10; val_offset:582*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 582*FLEN/8, x12, x4, x7) + +inst_317: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x1ae and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x65ae; op2val:0xfbff; + valaddr_reg:x10; val_offset:584*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 584*FLEN/8, x12, x4, x7) + +inst_318: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x1ae and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x65ae; op2val:0xfbff; + valaddr_reg:x10; val_offset:586*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 586*FLEN/8, x12, x4, x7) + +inst_319: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x1ae and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x65ae; op2val:0xfbff; + valaddr_reg:x10; val_offset:588*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 588*FLEN/8, x12, x4, x7) + +inst_320: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x167 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7967; op2val:0xfbff; + valaddr_reg:x10; val_offset:590*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 590*FLEN/8, x12, x4, x7) + +inst_321: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x167 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7967; op2val:0xfbff; + valaddr_reg:x10; val_offset:592*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 592*FLEN/8, x12, x4, x7) + +inst_322: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x167 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7967; op2val:0xfbff; + valaddr_reg:x10; val_offset:594*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 594*FLEN/8, x12, x4, x7) + +inst_323: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x167 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7967; op2val:0xfbff; + valaddr_reg:x10; val_offset:596*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 596*FLEN/8, x12, x4, x7) + +inst_324: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x167 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7967; op2val:0xfbff; + valaddr_reg:x10; val_offset:598*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 598*FLEN/8, x12, x4, x7) + +inst_325: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x004 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7404; op2val:0xfbff; + valaddr_reg:x10; val_offset:600*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 600*FLEN/8, x12, x4, x7) + +inst_326: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x004 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7404; op2val:0xfbff; + valaddr_reg:x10; val_offset:602*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 602*FLEN/8, x12, x4, x7) + +inst_327: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x004 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7404; op2val:0xfbff; + valaddr_reg:x10; val_offset:604*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 604*FLEN/8, x12, x4, x7) + +inst_328: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x004 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7404; op2val:0xfbff; + valaddr_reg:x10; val_offset:606*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 606*FLEN/8, x12, x4, x7) + +inst_329: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x004 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7404; op2val:0xfbff; + valaddr_reg:x10; val_offset:608*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 608*FLEN/8, x12, x4, x7) + +inst_330: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0bd and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78bd; op2val:0xfbff; + valaddr_reg:x10; val_offset:610*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 610*FLEN/8, x12, x4, x7) + +inst_331: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0bd and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78bd; op2val:0xfbff; + valaddr_reg:x10; val_offset:612*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 612*FLEN/8, x12, x4, x7) + +inst_332: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0bd and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78bd; op2val:0xfbff; + valaddr_reg:x10; val_offset:614*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 614*FLEN/8, x12, x4, x7) + +inst_333: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0bd and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78bd; op2val:0xfbff; + valaddr_reg:x10; val_offset:616*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 616*FLEN/8, x12, x4, x7) + +inst_334: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0bd and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78bd; op2val:0xfbff; + valaddr_reg:x10; val_offset:618*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 618*FLEN/8, x12, x4, x7) + +inst_335: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1d2 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x75d2; op2val:0xfbff; + valaddr_reg:x10; val_offset:620*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 620*FLEN/8, x12, x4, x7) + +inst_336: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1d2 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x75d2; op2val:0xfbff; + valaddr_reg:x10; val_offset:622*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 622*FLEN/8, x12, x4, x7) + +inst_337: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1d2 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x75d2; op2val:0xfbff; + valaddr_reg:x10; val_offset:624*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 624*FLEN/8, x12, x4, x7) + +inst_338: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1d2 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x75d2; op2val:0xfbff; + valaddr_reg:x10; val_offset:626*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 626*FLEN/8, x12, x4, x7) + +inst_339: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1d2 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x75d2; op2val:0xfbff; + valaddr_reg:x10; val_offset:628*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 628*FLEN/8, x12, x4, x7) + +inst_340: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1e7 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x75e7; op2val:0xfbff; + valaddr_reg:x10; val_offset:630*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 630*FLEN/8, x12, x4, x7) + +inst_341: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1e7 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x75e7; op2val:0xfbff; + valaddr_reg:x10; val_offset:632*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 632*FLEN/8, x12, x4, x7) + +inst_342: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1e7 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x75e7; op2val:0xfbff; + valaddr_reg:x10; val_offset:634*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 634*FLEN/8, x12, x4, x7) + +inst_343: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1e7 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x75e7; op2val:0xfbff; + valaddr_reg:x10; val_offset:636*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 636*FLEN/8, x12, x4, x7) + +inst_344: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1e7 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x75e7; op2val:0xfbff; + valaddr_reg:x10; val_offset:638*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 638*FLEN/8, x12, x4, x7) + +inst_345: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0cd and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74cd; op2val:0xfbff; + valaddr_reg:x10; val_offset:640*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 640*FLEN/8, x12, x4, x7) + +inst_346: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0cd and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74cd; op2val:0xfbff; + valaddr_reg:x10; val_offset:642*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 642*FLEN/8, x12, x4, x7) + +inst_347: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0cd and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74cd; op2val:0xfbff; + valaddr_reg:x10; val_offset:644*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 644*FLEN/8, x12, x4, x7) + +inst_348: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0cd and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74cd; op2val:0xfbff; + valaddr_reg:x10; val_offset:646*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 646*FLEN/8, x12, x4, x7) + +inst_349: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0cd and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74cd; op2val:0xfbff; + valaddr_reg:x10; val_offset:648*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 648*FLEN/8, x12, x4, x7) + +inst_350: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x22c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a2c; op2val:0xfbff; + valaddr_reg:x10; val_offset:650*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 650*FLEN/8, x12, x4, x7) + +inst_351: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x22c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a2c; op2val:0xfbff; + valaddr_reg:x10; val_offset:652*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 652*FLEN/8, x12, x4, x7) + +inst_352: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x22c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a2c; op2val:0xfbff; + valaddr_reg:x10; val_offset:654*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 654*FLEN/8, x12, x4, x7) + +inst_353: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x22c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a2c; op2val:0xfbff; + valaddr_reg:x10; val_offset:656*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 656*FLEN/8, x12, x4, x7) + +inst_354: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x22c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a2c; op2val:0xfbff; + valaddr_reg:x10; val_offset:658*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 658*FLEN/8, x12, x4, x7) + +inst_355: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x08d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x788d; op2val:0xfbff; + valaddr_reg:x10; val_offset:660*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 660*FLEN/8, x12, x4, x7) + +inst_356: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x08d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x788d; op2val:0xfbff; + valaddr_reg:x10; val_offset:662*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 662*FLEN/8, x12, x4, x7) + +inst_357: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x08d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x788d; op2val:0xfbff; + valaddr_reg:x10; val_offset:664*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 664*FLEN/8, x12, x4, x7) + +inst_358: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x08d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x788d; op2val:0xfbff; + valaddr_reg:x10; val_offset:666*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 666*FLEN/8, x12, x4, x7) + +inst_359: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x08d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x788d; op2val:0xfbff; + valaddr_reg:x10; val_offset:668*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 668*FLEN/8, x12, x4, x7) + +inst_360: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f5 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74f5; op2val:0xfbff; + valaddr_reg:x10; val_offset:670*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 670*FLEN/8, x12, x4, x7) + +inst_361: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f5 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74f5; op2val:0xfbff; + valaddr_reg:x10; val_offset:672*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 672*FLEN/8, x12, x4, x7) + +inst_362: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f5 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74f5; op2val:0xfbff; + valaddr_reg:x10; val_offset:674*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 674*FLEN/8, x12, x4, x7) + +inst_363: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f5 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74f5; op2val:0xfbff; + valaddr_reg:x10; val_offset:676*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 676*FLEN/8, x12, x4, x7) + +inst_364: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f5 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74f5; op2val:0xfbff; + valaddr_reg:x10; val_offset:678*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 678*FLEN/8, x12, x4, x7) + +inst_365: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a6d; op2val:0xfbff; + valaddr_reg:x10; val_offset:680*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 680*FLEN/8, x12, x4, x7) + +inst_366: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a6d; op2val:0xfbff; + valaddr_reg:x10; val_offset:682*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 682*FLEN/8, x12, x4, x7) + +inst_367: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a6d; op2val:0xfbff; + valaddr_reg:x10; val_offset:684*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 684*FLEN/8, x12, x4, x7) + +inst_368: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a6d; op2val:0xfbff; + valaddr_reg:x10; val_offset:686*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 686*FLEN/8, x12, x4, x7) + +inst_369: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a6d; op2val:0xfbff; + valaddr_reg:x10; val_offset:688*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 688*FLEN/8, x12, x4, x7) + +inst_370: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x71fe; op2val:0xfbff; + valaddr_reg:x10; val_offset:690*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 690*FLEN/8, x12, x4, x7) + +inst_371: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x71fe; op2val:0xfbff; + valaddr_reg:x10; val_offset:692*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 692*FLEN/8, x12, x4, x7) + +inst_372: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x71fe; op2val:0xfbff; + valaddr_reg:x10; val_offset:694*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 694*FLEN/8, x12, x4, x7) + +inst_373: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x71fe; op2val:0xfbff; + valaddr_reg:x10; val_offset:696*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 696*FLEN/8, x12, x4, x7) + +inst_374: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x71fe; op2val:0xfbff; + valaddr_reg:x10; val_offset:698*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 698*FLEN/8, x12, x4, x7) + +inst_375: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x194 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7994; op2val:0xfbff; + valaddr_reg:x10; val_offset:700*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 700*FLEN/8, x12, x4, x7) + +inst_376: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x194 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7994; op2val:0xfbff; + valaddr_reg:x10; val_offset:702*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 702*FLEN/8, x12, x4, x7) + +inst_377: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x194 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7994; op2val:0xfbff; + valaddr_reg:x10; val_offset:704*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 704*FLEN/8, x12, x4, x7) + +inst_378: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x194 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7994; op2val:0xfbff; + valaddr_reg:x10; val_offset:706*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 706*FLEN/8, x12, x4, x7) + +inst_379: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x194 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7994; op2val:0xfbff; + valaddr_reg:x10; val_offset:708*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 708*FLEN/8, x12, x4, x7) + +inst_380: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x126 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7526; op2val:0xfbff; + valaddr_reg:x10; val_offset:710*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 710*FLEN/8, x12, x4, x7) + +inst_381: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x126 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7526; op2val:0xfbff; + valaddr_reg:x10; val_offset:712*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 712*FLEN/8, x12, x4, x7) + +inst_382: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x126 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7526; op2val:0xfbff; + valaddr_reg:x10; val_offset:714*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 714*FLEN/8, x12, x4, x7) + +inst_383: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x126 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7526; op2val:0xfbff; + valaddr_reg:x10; val_offset:716*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 716*FLEN/8, x12, x4, x7) + +inst_384: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x126 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7526; op2val:0xfbff; + valaddr_reg:x10; val_offset:718*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 718*FLEN/8, x12, x4, x7) + +inst_385: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2aa and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aaa; op2val:0x7bff; + valaddr_reg:x10; val_offset:720*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 720*FLEN/8, x12, x4, x7) + +inst_386: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2aa and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aaa; op2val:0x7bff; + valaddr_reg:x10; val_offset:722*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 722*FLEN/8, x12, x4, x7) + +inst_387: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2aa and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aaa; op2val:0x7bff; + valaddr_reg:x10; val_offset:724*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 724*FLEN/8, x12, x4, x7) + +inst_388: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2aa and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aaa; op2val:0x7bff; + valaddr_reg:x10; val_offset:726*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 726*FLEN/8, x12, x4, x7) + +inst_389: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2aa and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aaa; op2val:0x7bff; + valaddr_reg:x10; val_offset:728*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 728*FLEN/8, x12, x4, x7) + +inst_390: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ad7; op2val:0x7bff; + valaddr_reg:x10; val_offset:730*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 730*FLEN/8, x12, x4, x7) + +inst_391: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ad7; op2val:0x7bff; + valaddr_reg:x10; val_offset:732*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 732*FLEN/8, x12, x4, x7) + +inst_392: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ad7; op2val:0x7bff; + valaddr_reg:x10; val_offset:734*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 734*FLEN/8, x12, x4, x7) + +inst_393: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ad7; op2val:0x7bff; + valaddr_reg:x10; val_offset:736*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 736*FLEN/8, x12, x4, x7) + +inst_394: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ad7; op2val:0x7bff; + valaddr_reg:x10; val_offset:738*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 738*FLEN/8, x12, x4, x7) + +inst_395: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x162 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7562; op2val:0x7bff; + valaddr_reg:x10; val_offset:740*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 740*FLEN/8, x12, x4, x7) + +inst_396: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x162 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7562; op2val:0x7bff; + valaddr_reg:x10; val_offset:742*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 742*FLEN/8, x12, x4, x7) + +inst_397: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x162 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7562; op2val:0x7bff; + valaddr_reg:x10; val_offset:744*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 744*FLEN/8, x12, x4, x7) + +inst_398: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x162 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7562; op2val:0x7bff; + valaddr_reg:x10; val_offset:746*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 746*FLEN/8, x12, x4, x7) + +inst_399: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x162 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7562; op2val:0x7bff; + valaddr_reg:x10; val_offset:748*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 748*FLEN/8, x12, x4, x7) + +inst_400: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x313 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b13; op2val:0x7bff; + valaddr_reg:x10; val_offset:750*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 750*FLEN/8, x12, x4, x7) + +inst_401: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x313 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b13; op2val:0x7bff; + valaddr_reg:x10; val_offset:752*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 752*FLEN/8, x12, x4, x7) + +inst_402: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x313 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b13; op2val:0x7bff; + valaddr_reg:x10; val_offset:754*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 754*FLEN/8, x12, x4, x7) + +inst_403: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x313 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b13; op2val:0x7bff; + valaddr_reg:x10; val_offset:756*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 756*FLEN/8, x12, x4, x7) + +inst_404: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x313 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b13; op2val:0x7bff; + valaddr_reg:x10; val_offset:758*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 758*FLEN/8, x12, x4, x7) + +inst_405: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x332 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7332; op2val:0x7bff; + valaddr_reg:x10; val_offset:760*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 760*FLEN/8, x12, x4, x7) + +inst_406: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x332 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7332; op2val:0x7bff; + valaddr_reg:x10; val_offset:762*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 762*FLEN/8, x12, x4, x7) + +inst_407: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x332 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7332; op2val:0x7bff; + valaddr_reg:x10; val_offset:764*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 764*FLEN/8, x12, x4, x7) + +inst_408: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x332 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7332; op2val:0x7bff; + valaddr_reg:x10; val_offset:766*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 766*FLEN/8, x12, x4, x7) + +inst_409: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x332 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7332; op2val:0x7bff; + valaddr_reg:x10; val_offset:768*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 768*FLEN/8, x12, x4, x7) + +inst_410: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x03c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x783c; op2val:0x7bff; + valaddr_reg:x10; val_offset:770*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 770*FLEN/8, x12, x4, x7) +RVTEST_SIGBASE(x4,signature_x4_3) + +inst_411: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x03c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x783c; op2val:0x7bff; + valaddr_reg:x10; val_offset:772*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 772*FLEN/8, x12, x4, x7) + +inst_412: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x03c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x783c; op2val:0x7bff; + valaddr_reg:x10; val_offset:774*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 774*FLEN/8, x12, x4, x7) + +inst_413: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x03c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x783c; op2val:0x7bff; + valaddr_reg:x10; val_offset:776*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 776*FLEN/8, x12, x4, x7) + +inst_414: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x03c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x783c; op2val:0x7bff; + valaddr_reg:x10; val_offset:778*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 778*FLEN/8, x12, x4, x7) + +inst_415: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x273 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a73; op2val:0x7bff; + valaddr_reg:x10; val_offset:780*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 780*FLEN/8, x12, x4, x7) + +inst_416: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x273 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a73; op2val:0x7bff; + valaddr_reg:x10; val_offset:782*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 782*FLEN/8, x12, x4, x7) + +inst_417: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x273 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a73; op2val:0x7bff; + valaddr_reg:x10; val_offset:784*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 784*FLEN/8, x12, x4, x7) + +inst_418: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x273 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a73; op2val:0x7bff; + valaddr_reg:x10; val_offset:786*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 786*FLEN/8, x12, x4, x7) + +inst_419: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x273 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a73; op2val:0x7bff; + valaddr_reg:x10; val_offset:788*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 788*FLEN/8, x12, x4, x7) + +inst_420: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1df and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x71df; op2val:0x7bff; + valaddr_reg:x10; val_offset:790*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 790*FLEN/8, x12, x4, x7) + +inst_421: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1df and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x71df; op2val:0x7bff; + valaddr_reg:x10; val_offset:792*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 792*FLEN/8, x12, x4, x7) + +inst_422: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1df and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x71df; op2val:0x7bff; + valaddr_reg:x10; val_offset:794*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 794*FLEN/8, x12, x4, x7) + +inst_423: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1df and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x71df; op2val:0x7bff; + valaddr_reg:x10; val_offset:796*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 796*FLEN/8, x12, x4, x7) + +inst_424: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1df and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x71df; op2val:0x7bff; + valaddr_reg:x10; val_offset:798*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 798*FLEN/8, x12, x4, x7) + +inst_425: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x274 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a74; op2val:0x7bff; + valaddr_reg:x10; val_offset:800*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 800*FLEN/8, x12, x4, x7) + +inst_426: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x274 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a74; op2val:0x7bff; + valaddr_reg:x10; val_offset:802*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 802*FLEN/8, x12, x4, x7) + +inst_427: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x274 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a74; op2val:0x7bff; + valaddr_reg:x10; val_offset:804*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 804*FLEN/8, x12, x4, x7) + +inst_428: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x274 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a74; op2val:0x7bff; + valaddr_reg:x10; val_offset:806*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 806*FLEN/8, x12, x4, x7) + +inst_429: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x274 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a74; op2val:0x7bff; + valaddr_reg:x10; val_offset:808*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 808*FLEN/8, x12, x4, x7) + +inst_430: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x272 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a72; op2val:0x7bff; + valaddr_reg:x10; val_offset:810*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 810*FLEN/8, x12, x4, x7) + +inst_431: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x272 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a72; op2val:0x7bff; + valaddr_reg:x10; val_offset:812*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 812*FLEN/8, x12, x4, x7) + +inst_432: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x272 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a72; op2val:0x7bff; + valaddr_reg:x10; val_offset:814*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 814*FLEN/8, x12, x4, x7) + +inst_433: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x272 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a72; op2val:0x7bff; + valaddr_reg:x10; val_offset:816*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 816*FLEN/8, x12, x4, x7) + +inst_434: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x272 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a72; op2val:0x7bff; + valaddr_reg:x10; val_offset:818*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 818*FLEN/8, x12, x4, x7) + +inst_435: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x026 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7026; op2val:0x7bff; + valaddr_reg:x10; val_offset:820*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 820*FLEN/8, x12, x4, x7) + +inst_436: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x026 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7026; op2val:0x7bff; + valaddr_reg:x10; val_offset:822*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 822*FLEN/8, x12, x4, x7) + +inst_437: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x026 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7026; op2val:0x7bff; + valaddr_reg:x10; val_offset:824*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 824*FLEN/8, x12, x4, x7) + +inst_438: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x026 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7026; op2val:0x7bff; + valaddr_reg:x10; val_offset:826*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 826*FLEN/8, x12, x4, x7) + +inst_439: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x026 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7026; op2val:0x7bff; + valaddr_reg:x10; val_offset:828*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 828*FLEN/8, x12, x4, x7) + +inst_440: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x259 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a59; op2val:0x7bff; + valaddr_reg:x10; val_offset:830*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 830*FLEN/8, x12, x4, x7) + +inst_441: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x259 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a59; op2val:0x7bff; + valaddr_reg:x10; val_offset:832*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 832*FLEN/8, x12, x4, x7) + +inst_442: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x259 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a59; op2val:0x7bff; + valaddr_reg:x10; val_offset:834*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 834*FLEN/8, x12, x4, x7) + +inst_443: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x259 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a59; op2val:0x7bff; + valaddr_reg:x10; val_offset:836*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 836*FLEN/8, x12, x4, x7) + +inst_444: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x259 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a59; op2val:0x7bff; + valaddr_reg:x10; val_offset:838*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 838*FLEN/8, x12, x4, x7) + +inst_445: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x18a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x758a; op2val:0x7bff; + valaddr_reg:x10; val_offset:840*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 840*FLEN/8, x12, x4, x7) + +inst_446: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x18a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x758a; op2val:0x7bff; + valaddr_reg:x10; val_offset:842*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 842*FLEN/8, x12, x4, x7) + +inst_447: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x18a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x758a; op2val:0x7bff; + valaddr_reg:x10; val_offset:844*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 844*FLEN/8, x12, x4, x7) + +inst_448: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x18a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x758a; op2val:0x7bff; + valaddr_reg:x10; val_offset:846*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 846*FLEN/8, x12, x4, x7) + +inst_449: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x18a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x758a; op2val:0x7bff; + valaddr_reg:x10; val_offset:848*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 848*FLEN/8, x12, x4, x7) + +inst_450: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2b6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x76b6; op2val:0x7bff; + valaddr_reg:x10; val_offset:850*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 850*FLEN/8, x12, x4, x7) + +inst_451: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2b6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x76b6; op2val:0x7bff; + valaddr_reg:x10; val_offset:852*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 852*FLEN/8, x12, x4, x7) + +inst_452: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2b6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x76b6; op2val:0x7bff; + valaddr_reg:x10; val_offset:854*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 854*FLEN/8, x12, x4, x7) + +inst_453: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2b6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x76b6; op2val:0x7bff; + valaddr_reg:x10; val_offset:856*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 856*FLEN/8, x12, x4, x7) + +inst_454: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2b6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x76b6; op2val:0x7bff; + valaddr_reg:x10; val_offset:858*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 858*FLEN/8, x12, x4, x7) + +inst_455: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x35c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b5c; op2val:0xfbff; + valaddr_reg:x10; val_offset:860*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 860*FLEN/8, x12, x4, x7) + +inst_456: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x35c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b5c; op2val:0xfbff; + valaddr_reg:x10; val_offset:862*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 862*FLEN/8, x12, x4, x7) + +inst_457: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x35c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b5c; op2val:0xfbff; + valaddr_reg:x10; val_offset:864*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 864*FLEN/8, x12, x4, x7) + +inst_458: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x35c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b5c; op2val:0xfbff; + valaddr_reg:x10; val_offset:866*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 866*FLEN/8, x12, x4, x7) + +inst_459: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x35c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b5c; op2val:0xfbff; + valaddr_reg:x10; val_offset:868*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 868*FLEN/8, x12, x4, x7) + +inst_460: +// fs1 == 0 and fe1 == 0x17 and fm1 == 0x0c9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5cc9; op2val:0xfbff; + valaddr_reg:x10; val_offset:870*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 870*FLEN/8, x12, x4, x7) + +inst_461: +// fs1 == 0 and fe1 == 0x17 and fm1 == 0x0c9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5cc9; op2val:0xfbff; + valaddr_reg:x10; val_offset:872*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 872*FLEN/8, x12, x4, x7) + +inst_462: +// fs1 == 0 and fe1 == 0x17 and fm1 == 0x0c9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5cc9; op2val:0xfbff; + valaddr_reg:x10; val_offset:874*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 874*FLEN/8, x12, x4, x7) + +inst_463: +// fs1 == 0 and fe1 == 0x17 and fm1 == 0x0c9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5cc9; op2val:0xfbff; + valaddr_reg:x10; val_offset:876*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 876*FLEN/8, x12, x4, x7) + +inst_464: +// fs1 == 0 and fe1 == 0x17 and fm1 == 0x0c9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5cc9; op2val:0xfbff; + valaddr_reg:x10; val_offset:878*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 878*FLEN/8, x12, x4, x7) + +inst_465: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x309 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b09; op2val:0xfbff; + valaddr_reg:x10; val_offset:880*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 880*FLEN/8, x12, x4, x7) + +inst_466: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x309 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b09; op2val:0xfbff; + valaddr_reg:x10; val_offset:882*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 882*FLEN/8, x12, x4, x7) + +inst_467: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x309 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b09; op2val:0xfbff; + valaddr_reg:x10; val_offset:884*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 884*FLEN/8, x12, x4, x7) + +inst_468: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x309 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b09; op2val:0xfbff; + valaddr_reg:x10; val_offset:886*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 886*FLEN/8, x12, x4, x7) + +inst_469: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x309 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b09; op2val:0xfbff; + valaddr_reg:x10; val_offset:888*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 888*FLEN/8, x12, x4, x7) + +inst_470: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2f2 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x76f2; op2val:0xfbff; + valaddr_reg:x10; val_offset:890*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 890*FLEN/8, x12, x4, x7) + +inst_471: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2f2 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x76f2; op2val:0xfbff; + valaddr_reg:x10; val_offset:892*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 892*FLEN/8, x12, x4, x7) + +inst_472: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2f2 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x76f2; op2val:0xfbff; + valaddr_reg:x10; val_offset:894*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 894*FLEN/8, x12, x4, x7) + +inst_473: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2f2 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x76f2; op2val:0xfbff; + valaddr_reg:x10; val_offset:896*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 896*FLEN/8, x12, x4, x7) + +inst_474: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2f2 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x76f2; op2val:0xfbff; + valaddr_reg:x10; val_offset:898*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 898*FLEN/8, x12, x4, x7) + +inst_475: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x36a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b6a; op2val:0xfbff; + valaddr_reg:x10; val_offset:900*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 900*FLEN/8, x12, x4, x7) + +inst_476: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x36a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b6a; op2val:0xfbff; + valaddr_reg:x10; val_offset:902*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 902*FLEN/8, x12, x4, x7) + +inst_477: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x36a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b6a; op2val:0xfbff; + valaddr_reg:x10; val_offset:904*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 904*FLEN/8, x12, x4, x7) + +inst_478: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x36a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b6a; op2val:0xfbff; + valaddr_reg:x10; val_offset:906*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 906*FLEN/8, x12, x4, x7) + +inst_479: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x36a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b6a; op2val:0xfbff; + valaddr_reg:x10; val_offset:908*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 908*FLEN/8, x12, x4, x7) + +inst_480: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f6 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79f6; op2val:0xfbff; + valaddr_reg:x10; val_offset:910*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 910*FLEN/8, x12, x4, x7) + +inst_481: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f6 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79f6; op2val:0xfbff; + valaddr_reg:x10; val_offset:912*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 912*FLEN/8, x12, x4, x7) + +inst_482: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f6 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79f6; op2val:0xfbff; + valaddr_reg:x10; val_offset:914*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 914*FLEN/8, x12, x4, x7) + +inst_483: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f6 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79f6; op2val:0xfbff; + valaddr_reg:x10; val_offset:916*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 916*FLEN/8, x12, x4, x7) + +inst_484: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f6 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79f6; op2val:0xfbff; + valaddr_reg:x10; val_offset:918*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 918*FLEN/8, x12, x4, x7) + +inst_485: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x14d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x794d; op2val:0xfbff; + valaddr_reg:x10; val_offset:920*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 920*FLEN/8, x12, x4, x7) + +inst_486: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x14d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x794d; op2val:0xfbff; + valaddr_reg:x10; val_offset:922*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 922*FLEN/8, x12, x4, x7) + +inst_487: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x14d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x794d; op2val:0xfbff; + valaddr_reg:x10; val_offset:924*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 924*FLEN/8, x12, x4, x7) + +inst_488: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x14d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x794d; op2val:0xfbff; + valaddr_reg:x10; val_offset:926*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 926*FLEN/8, x12, x4, x7) + +inst_489: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x14d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x794d; op2val:0xfbff; + valaddr_reg:x10; val_offset:928*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 928*FLEN/8, x12, x4, x7) + +inst_490: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x09f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x749f; op2val:0xfbff; + valaddr_reg:x10; val_offset:930*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 930*FLEN/8, x12, x4, x7) + +inst_491: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x09f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x749f; op2val:0xfbff; + valaddr_reg:x10; val_offset:932*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 932*FLEN/8, x12, x4, x7) + +inst_492: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x09f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x749f; op2val:0xfbff; + valaddr_reg:x10; val_offset:934*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 934*FLEN/8, x12, x4, x7) + +inst_493: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x09f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x749f; op2val:0xfbff; + valaddr_reg:x10; val_offset:936*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 936*FLEN/8, x12, x4, x7) + +inst_494: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x09f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x749f; op2val:0xfbff; + valaddr_reg:x10; val_offset:938*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 938*FLEN/8, x12, x4, x7) + +inst_495: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x346 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7346; op2val:0xfbff; + valaddr_reg:x10; val_offset:940*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 940*FLEN/8, x12, x4, x7) + +inst_496: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x346 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7346; op2val:0xfbff; + valaddr_reg:x10; val_offset:942*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 942*FLEN/8, x12, x4, x7) + +inst_497: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x346 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7346; op2val:0xfbff; + valaddr_reg:x10; val_offset:944*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 944*FLEN/8, x12, x4, x7) + +inst_498: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x346 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7346; op2val:0xfbff; + valaddr_reg:x10; val_offset:946*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 946*FLEN/8, x12, x4, x7) + +inst_499: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x346 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7346; op2val:0xfbff; + valaddr_reg:x10; val_offset:948*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 948*FLEN/8, x12, x4, x7) + +inst_500: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b5 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78b5; op2val:0xfbff; + valaddr_reg:x10; val_offset:950*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 950*FLEN/8, x12, x4, x7) + +inst_501: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b5 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78b5; op2val:0xfbff; + valaddr_reg:x10; val_offset:952*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 952*FLEN/8, x12, x4, x7) + +inst_502: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b5 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78b5; op2val:0xfbff; + valaddr_reg:x10; val_offset:954*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 954*FLEN/8, x12, x4, x7) + +inst_503: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b5 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78b5; op2val:0xfbff; + valaddr_reg:x10; val_offset:956*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 956*FLEN/8, x12, x4, x7) + +inst_504: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b5 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78b5; op2val:0xfbff; + valaddr_reg:x10; val_offset:958*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 958*FLEN/8, x12, x4, x7) + +inst_505: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x27a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a7a; op2val:0xfbff; + valaddr_reg:x10; val_offset:960*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 960*FLEN/8, x12, x4, x7) + +inst_506: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x27a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a7a; op2val:0xfbff; + valaddr_reg:x10; val_offset:962*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 962*FLEN/8, x12, x4, x7) + +inst_507: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x27a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a7a; op2val:0xfbff; + valaddr_reg:x10; val_offset:964*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 964*FLEN/8, x12, x4, x7) + +inst_508: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x27a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a7a; op2val:0xfbff; + valaddr_reg:x10; val_offset:966*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 966*FLEN/8, x12, x4, x7) + +inst_509: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x27a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a7a; op2val:0xfbff; + valaddr_reg:x10; val_offset:968*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 968*FLEN/8, x12, x4, x7) + +inst_510: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x339 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b39; op2val:0xfbff; + valaddr_reg:x10; val_offset:970*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 970*FLEN/8, x12, x4, x7) + +inst_511: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x339 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b39; op2val:0xfbff; + valaddr_reg:x10; val_offset:972*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 972*FLEN/8, x12, x4, x7) + +inst_512: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x339 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b39; op2val:0xfbff; + valaddr_reg:x10; val_offset:974*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 974*FLEN/8, x12, x4, x7) + +inst_513: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x339 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b39; op2val:0xfbff; + valaddr_reg:x10; val_offset:976*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 976*FLEN/8, x12, x4, x7) + +inst_514: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x339 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b39; op2val:0xfbff; + valaddr_reg:x10; val_offset:978*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 978*FLEN/8, x12, x4, x7) + +inst_515: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x363 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b63; op2val:0xfbff; + valaddr_reg:x10; val_offset:980*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 980*FLEN/8, x12, x4, x7) + +inst_516: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x363 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b63; op2val:0xfbff; + valaddr_reg:x10; val_offset:982*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 982*FLEN/8, x12, x4, x7) + +inst_517: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x363 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b63; op2val:0xfbff; + valaddr_reg:x10; val_offset:984*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 984*FLEN/8, x12, x4, x7) + +inst_518: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x363 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b63; op2val:0xfbff; + valaddr_reg:x10; val_offset:986*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 986*FLEN/8, x12, x4, x7) + +inst_519: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x363 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b63; op2val:0xfbff; + valaddr_reg:x10; val_offset:988*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 988*FLEN/8, x12, x4, x7) + +inst_520: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x331 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b31; op2val:0xfbff; + valaddr_reg:x10; val_offset:990*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 990*FLEN/8, x12, x4, x7) + +inst_521: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x331 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b31; op2val:0xfbff; + valaddr_reg:x10; val_offset:992*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 992*FLEN/8, x12, x4, x7) + +inst_522: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x331 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b31; op2val:0xfbff; + valaddr_reg:x10; val_offset:994*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 994*FLEN/8, x12, x4, x7) + +inst_523: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x331 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b31; op2val:0xfbff; + valaddr_reg:x10; val_offset:996*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 996*FLEN/8, x12, x4, x7) + +inst_524: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x331 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b31; op2val:0xfbff; + valaddr_reg:x10; val_offset:998*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 998*FLEN/8, x12, x4, x7) + +inst_525: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x2bc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x62bc; op2val:0x7bff; + valaddr_reg:x10; val_offset:1000*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1000*FLEN/8, x12, x4, x7) + +inst_526: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x2bc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x62bc; op2val:0x7bff; + valaddr_reg:x10; val_offset:1002*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1002*FLEN/8, x12, x4, x7) + +inst_527: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x2bc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x62bc; op2val:0x7bff; + valaddr_reg:x10; val_offset:1004*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1004*FLEN/8, x12, x4, x7) + +inst_528: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x2bc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x62bc; op2val:0x7bff; + valaddr_reg:x10; val_offset:1006*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1006*FLEN/8, x12, x4, x7) + +inst_529: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x2bc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x62bc; op2val:0x7bff; + valaddr_reg:x10; val_offset:1008*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1008*FLEN/8, x12, x4, x7) + +inst_530: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x17e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x717e; op2val:0x7bff; + valaddr_reg:x10; val_offset:1010*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1010*FLEN/8, x12, x4, x7) + +inst_531: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x17e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x717e; op2val:0x7bff; + valaddr_reg:x10; val_offset:1012*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1012*FLEN/8, x12, x4, x7) + +inst_532: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x17e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x717e; op2val:0x7bff; + valaddr_reg:x10; val_offset:1014*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1014*FLEN/8, x12, x4, x7) + +inst_533: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x17e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x717e; op2val:0x7bff; + valaddr_reg:x10; val_offset:1016*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1016*FLEN/8, x12, x4, x7) + +inst_534: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x17e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x717e; op2val:0x7bff; + valaddr_reg:x10; val_offset:1018*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1018*FLEN/8, x12, x4, x7) + +inst_535: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x14c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x794c; op2val:0x7bff; + valaddr_reg:x10; val_offset:1020*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1020*FLEN/8, x12, x4, x7) + +inst_536: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x14c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x794c; op2val:0x7bff; + valaddr_reg:x10; val_offset:1022*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1022*FLEN/8, x12, x4, x7) + +inst_537: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x14c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x794c; op2val:0x7bff; + valaddr_reg:x10; val_offset:1024*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1024*FLEN/8, x12, x4, x7) + +inst_538: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x14c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x794c; op2val:0x7bff; + valaddr_reg:x10; val_offset:1026*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1026*FLEN/8, x12, x4, x7) +RVTEST_SIGBASE(x4,signature_x4_4) + +inst_539: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x14c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x794c; op2val:0x7bff; + valaddr_reg:x10; val_offset:1028*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1028*FLEN/8, x12, x4, x7) + +inst_540: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x29d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x769d; op2val:0x7bff; + valaddr_reg:x10; val_offset:1030*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1030*FLEN/8, x12, x4, x7) + +inst_541: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x29d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x769d; op2val:0x7bff; + valaddr_reg:x10; val_offset:1032*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1032*FLEN/8, x12, x4, x7) + +inst_542: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x29d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x769d; op2val:0x7bff; + valaddr_reg:x10; val_offset:1034*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1034*FLEN/8, x12, x4, x7) + +inst_543: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x29d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x769d; op2val:0x7bff; + valaddr_reg:x10; val_offset:1036*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1036*FLEN/8, x12, x4, x7) + +inst_544: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x29d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x769d; op2val:0x7bff; + valaddr_reg:x10; val_offset:1038*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1038*FLEN/8, x12, x4, x7) + +inst_545: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78e5; op2val:0x7bff; + valaddr_reg:x10; val_offset:1040*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1040*FLEN/8, x12, x4, x7) + +inst_546: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78e5; op2val:0x7bff; + valaddr_reg:x10; val_offset:1042*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1042*FLEN/8, x12, x4, x7) + +inst_547: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78e5; op2val:0x7bff; + valaddr_reg:x10; val_offset:1044*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1044*FLEN/8, x12, x4, x7) + +inst_548: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78e5; op2val:0x7bff; + valaddr_reg:x10; val_offset:1046*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1046*FLEN/8, x12, x4, x7) + +inst_549: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78e5; op2val:0x7bff; + valaddr_reg:x10; val_offset:1048*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1048*FLEN/8, x12, x4, x7) + +inst_550: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x009 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7409; op2val:0x7bff; + valaddr_reg:x10; val_offset:1050*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1050*FLEN/8, x12, x4, x7) + +inst_551: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x009 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7409; op2val:0x7bff; + valaddr_reg:x10; val_offset:1052*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1052*FLEN/8, x12, x4, x7) + +inst_552: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x009 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7409; op2val:0x7bff; + valaddr_reg:x10; val_offset:1054*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1054*FLEN/8, x12, x4, x7) + +inst_553: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x009 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7409; op2val:0x7bff; + valaddr_reg:x10; val_offset:1056*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1056*FLEN/8, x12, x4, x7) + +inst_554: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x009 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7409; op2val:0x7bff; + valaddr_reg:x10; val_offset:1058*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1058*FLEN/8, x12, x4, x7) + +inst_555: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x77a1; op2val:0x7bff; + valaddr_reg:x10; val_offset:1060*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1060*FLEN/8, x12, x4, x7) + +inst_556: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x77a1; op2val:0x7bff; + valaddr_reg:x10; val_offset:1062*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1062*FLEN/8, x12, x4, x7) + +inst_557: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x77a1; op2val:0x7bff; + valaddr_reg:x10; val_offset:1064*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1064*FLEN/8, x12, x4, x7) + +inst_558: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x77a1; op2val:0x7bff; + valaddr_reg:x10; val_offset:1066*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1066*FLEN/8, x12, x4, x7) + +inst_559: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x77a1; op2val:0x7bff; + valaddr_reg:x10; val_offset:1068*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1068*FLEN/8, x12, x4, x7) + +inst_560: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x75a0; op2val:0x7bff; + valaddr_reg:x10; val_offset:1070*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1070*FLEN/8, x12, x4, x7) + +inst_561: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x75a0; op2val:0x7bff; + valaddr_reg:x10; val_offset:1072*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1072*FLEN/8, x12, x4, x7) + +inst_562: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x75a0; op2val:0x7bff; + valaddr_reg:x10; val_offset:1074*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1074*FLEN/8, x12, x4, x7) + +inst_563: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x75a0; op2val:0x7bff; + valaddr_reg:x10; val_offset:1076*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1076*FLEN/8, x12, x4, x7) + +inst_564: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x75a0; op2val:0x7bff; + valaddr_reg:x10; val_offset:1078*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1078*FLEN/8, x12, x4, x7) + +inst_565: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x046 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7846; op2val:0x7bff; + valaddr_reg:x10; val_offset:1080*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1080*FLEN/8, x12, x4, x7) + +inst_566: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x046 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7846; op2val:0x7bff; + valaddr_reg:x10; val_offset:1082*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1082*FLEN/8, x12, x4, x7) + +inst_567: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x046 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7846; op2val:0x7bff; + valaddr_reg:x10; val_offset:1084*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1084*FLEN/8, x12, x4, x7) + +inst_568: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x046 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7846; op2val:0x7bff; + valaddr_reg:x10; val_offset:1086*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1086*FLEN/8, x12, x4, x7) + +inst_569: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x046 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7846; op2val:0x7bff; + valaddr_reg:x10; val_offset:1088*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1088*FLEN/8, x12, x4, x7) + +inst_570: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x17a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x717a; op2val:0x7bff; + valaddr_reg:x10; val_offset:1090*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1090*FLEN/8, x12, x4, x7) + +inst_571: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x17a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x717a; op2val:0x7bff; + valaddr_reg:x10; val_offset:1092*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1092*FLEN/8, x12, x4, x7) + +inst_572: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x17a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x717a; op2val:0x7bff; + valaddr_reg:x10; val_offset:1094*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1094*FLEN/8, x12, x4, x7) + +inst_573: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x17a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x717a; op2val:0x7bff; + valaddr_reg:x10; val_offset:1096*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1096*FLEN/8, x12, x4, x7) + +inst_574: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x17a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x717a; op2val:0x7bff; + valaddr_reg:x10; val_offset:1098*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1098*FLEN/8, x12, x4, x7) + +inst_575: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x35e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b5e; op2val:0x7bff; + valaddr_reg:x10; val_offset:1100*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1100*FLEN/8, x12, x4, x7) + +inst_576: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x35e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b5e; op2val:0x7bff; + valaddr_reg:x10; val_offset:1102*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1102*FLEN/8, x12, x4, x7) + +inst_577: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x35e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b5e; op2val:0x7bff; + valaddr_reg:x10; val_offset:1104*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1104*FLEN/8, x12, x4, x7) + +inst_578: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x35e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b5e; op2val:0x7bff; + valaddr_reg:x10; val_offset:1106*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1106*FLEN/8, x12, x4, x7) + +inst_579: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x35e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b5e; op2val:0x7bff; + valaddr_reg:x10; val_offset:1108*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1108*FLEN/8, x12, x4, x7) + +inst_580: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x295 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a95; op2val:0x7bff; + valaddr_reg:x10; val_offset:1110*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1110*FLEN/8, x12, x4, x7) + +inst_581: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x295 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a95; op2val:0x7bff; + valaddr_reg:x10; val_offset:1112*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1112*FLEN/8, x12, x4, x7) + +inst_582: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x295 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a95; op2val:0x7bff; + valaddr_reg:x10; val_offset:1114*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1114*FLEN/8, x12, x4, x7) + +inst_583: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x295 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a95; op2val:0x7bff; + valaddr_reg:x10; val_offset:1116*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1116*FLEN/8, x12, x4, x7) + +inst_584: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x295 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a95; op2val:0x7bff; + valaddr_reg:x10; val_offset:1118*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1118*FLEN/8, x12, x4, x7) + +inst_585: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x106 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7906; op2val:0x7bff; + valaddr_reg:x10; val_offset:1120*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1120*FLEN/8, x12, x4, x7) + +inst_586: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x106 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7906; op2val:0x7bff; + valaddr_reg:x10; val_offset:1122*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1122*FLEN/8, x12, x4, x7) + +inst_587: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x106 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7906; op2val:0x7bff; + valaddr_reg:x10; val_offset:1124*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1124*FLEN/8, x12, x4, x7) + +inst_588: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x106 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7906; op2val:0x7bff; + valaddr_reg:x10; val_offset:1126*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1126*FLEN/8, x12, x4, x7) + +inst_589: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x106 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7906; op2val:0x7bff; + valaddr_reg:x10; val_offset:1128*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1128*FLEN/8, x12, x4, x7) + +inst_590: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x263 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6a63; op2val:0x7bff; + valaddr_reg:x10; val_offset:1130*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1130*FLEN/8, x12, x4, x7) + +inst_591: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x263 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6a63; op2val:0x7bff; + valaddr_reg:x10; val_offset:1132*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1132*FLEN/8, x12, x4, x7) + +inst_592: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x263 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6a63; op2val:0x7bff; + valaddr_reg:x10; val_offset:1134*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1134*FLEN/8, x12, x4, x7) + +inst_593: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x263 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6a63; op2val:0x7bff; + valaddr_reg:x10; val_offset:1136*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1136*FLEN/8, x12, x4, x7) + +inst_594: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x263 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6a63; op2val:0x7bff; + valaddr_reg:x10; val_offset:1138*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1138*FLEN/8, x12, x4, x7) + +inst_595: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x04b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x744b; op2val:0xfbff; + valaddr_reg:x10; val_offset:1140*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1140*FLEN/8, x12, x4, x7) + +inst_596: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x04b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x744b; op2val:0xfbff; + valaddr_reg:x10; val_offset:1142*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1142*FLEN/8, x12, x4, x7) + +inst_597: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x04b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x744b; op2val:0xfbff; + valaddr_reg:x10; val_offset:1144*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1144*FLEN/8, x12, x4, x7) + +inst_598: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x04b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x744b; op2val:0xfbff; + valaddr_reg:x10; val_offset:1146*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1146*FLEN/8, x12, x4, x7) + +inst_599: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x04b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x744b; op2val:0xfbff; + valaddr_reg:x10; val_offset:1148*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1148*FLEN/8, x12, x4, x7) + +inst_600: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2c3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x76c3; op2val:0xfbff; + valaddr_reg:x10; val_offset:1150*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1150*FLEN/8, x12, x4, x7) + +inst_601: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2c3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x76c3; op2val:0xfbff; + valaddr_reg:x10; val_offset:1152*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1152*FLEN/8, x12, x4, x7) + +inst_602: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2c3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x76c3; op2val:0xfbff; + valaddr_reg:x10; val_offset:1154*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1154*FLEN/8, x12, x4, x7) + +inst_603: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2c3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x76c3; op2val:0xfbff; + valaddr_reg:x10; val_offset:1156*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1156*FLEN/8, x12, x4, x7) + +inst_604: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2c3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x76c3; op2val:0xfbff; + valaddr_reg:x10; val_offset:1158*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1158*FLEN/8, x12, x4, x7) + +inst_605: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x235 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a35; op2val:0xfbff; + valaddr_reg:x10; val_offset:1160*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1160*FLEN/8, x12, x4, x7) + +inst_606: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x235 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a35; op2val:0xfbff; + valaddr_reg:x10; val_offset:1162*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1162*FLEN/8, x12, x4, x7) + +inst_607: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x235 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a35; op2val:0xfbff; + valaddr_reg:x10; val_offset:1164*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1164*FLEN/8, x12, x4, x7) + +inst_608: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x235 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a35; op2val:0xfbff; + valaddr_reg:x10; val_offset:1166*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1166*FLEN/8, x12, x4, x7) + +inst_609: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x235 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a35; op2val:0xfbff; + valaddr_reg:x10; val_offset:1168*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1168*FLEN/8, x12, x4, x7) + +inst_610: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x304 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6b04; op2val:0xfbff; + valaddr_reg:x10; val_offset:1170*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1170*FLEN/8, x12, x4, x7) + +inst_611: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x304 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6b04; op2val:0xfbff; + valaddr_reg:x10; val_offset:1172*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1172*FLEN/8, x12, x4, x7) + +inst_612: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x304 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6b04; op2val:0xfbff; + valaddr_reg:x10; val_offset:1174*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1174*FLEN/8, x12, x4, x7) + +inst_613: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x304 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6b04; op2val:0xfbff; + valaddr_reg:x10; val_offset:1176*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1176*FLEN/8, x12, x4, x7) + +inst_614: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x304 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6b04; op2val:0xfbff; + valaddr_reg:x10; val_offset:1178*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1178*FLEN/8, x12, x4, x7) + +inst_615: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3f9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ff9; op2val:0xfbff; + valaddr_reg:x10; val_offset:1180*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1180*FLEN/8, x12, x4, x7) + +inst_616: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3f9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ff9; op2val:0xfbff; + valaddr_reg:x10; val_offset:1182*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1182*FLEN/8, x12, x4, x7) + +inst_617: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3f9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ff9; op2val:0xfbff; + valaddr_reg:x10; val_offset:1184*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1184*FLEN/8, x12, x4, x7) + +inst_618: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3f9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ff9; op2val:0xfbff; + valaddr_reg:x10; val_offset:1186*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1186*FLEN/8, x12, x4, x7) + +inst_619: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3f9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ff9; op2val:0xfbff; + valaddr_reg:x10; val_offset:1188*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1188*FLEN/8, x12, x4, x7) + +inst_620: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3cb and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bcb; op2val:0xfbff; + valaddr_reg:x10; val_offset:1190*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1190*FLEN/8, x12, x4, x7) + +inst_621: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3cb and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bcb; op2val:0xfbff; + valaddr_reg:x10; val_offset:1192*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1192*FLEN/8, x12, x4, x7) + +inst_622: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3cb and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bcb; op2val:0xfbff; + valaddr_reg:x10; val_offset:1194*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1194*FLEN/8, x12, x4, x7) + +inst_623: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3cb and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bcb; op2val:0xfbff; + valaddr_reg:x10; val_offset:1196*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1196*FLEN/8, x12, x4, x7) + +inst_624: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3cb and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bcb; op2val:0xfbff; + valaddr_reg:x10; val_offset:1198*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1198*FLEN/8, x12, x4, x7) + +inst_625: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x182 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d82; op2val:0xfbff; + valaddr_reg:x10; val_offset:1200*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1200*FLEN/8, x12, x4, x7) + +inst_626: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x182 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d82; op2val:0xfbff; + valaddr_reg:x10; val_offset:1202*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1202*FLEN/8, x12, x4, x7) + +inst_627: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x182 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d82; op2val:0xfbff; + valaddr_reg:x10; val_offset:1204*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1204*FLEN/8, x12, x4, x7) + +inst_628: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x182 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d82; op2val:0xfbff; + valaddr_reg:x10; val_offset:1206*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1206*FLEN/8, x12, x4, x7) + +inst_629: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x182 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d82; op2val:0xfbff; + valaddr_reg:x10; val_offset:1208*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1208*FLEN/8, x12, x4, x7) + +inst_630: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x10d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x750d; op2val:0xfbff; + valaddr_reg:x10; val_offset:1210*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1210*FLEN/8, x12, x4, x7) + +inst_631: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x10d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x750d; op2val:0xfbff; + valaddr_reg:x10; val_offset:1212*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1212*FLEN/8, x12, x4, x7) + +inst_632: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x10d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x750d; op2val:0xfbff; + valaddr_reg:x10; val_offset:1214*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1214*FLEN/8, x12, x4, x7) + +inst_633: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x10d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x750d; op2val:0xfbff; + valaddr_reg:x10; val_offset:1216*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1216*FLEN/8, x12, x4, x7) + +inst_634: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x10d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x750d; op2val:0xfbff; + valaddr_reg:x10; val_offset:1218*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1218*FLEN/8, x12, x4, x7) + +inst_635: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x19e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x759e; op2val:0xfbff; + valaddr_reg:x10; val_offset:1220*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1220*FLEN/8, x12, x4, x7) + +inst_636: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x19e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x759e; op2val:0xfbff; + valaddr_reg:x10; val_offset:1222*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1222*FLEN/8, x12, x4, x7) + +inst_637: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x19e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x759e; op2val:0xfbff; + valaddr_reg:x10; val_offset:1224*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1224*FLEN/8, x12, x4, x7) + +inst_638: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x19e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x759e; op2val:0xfbff; + valaddr_reg:x10; val_offset:1226*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1226*FLEN/8, x12, x4, x7) + +inst_639: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x19e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x759e; op2val:0xfbff; + valaddr_reg:x10; val_offset:1228*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1228*FLEN/8, x12, x4, x7) + +inst_640: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78b0; op2val:0xfbff; + valaddr_reg:x10; val_offset:1230*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1230*FLEN/8, x12, x4, x7) + +inst_641: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78b0; op2val:0xfbff; + valaddr_reg:x10; val_offset:1232*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1232*FLEN/8, x12, x4, x7) + +inst_642: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78b0; op2val:0xfbff; + valaddr_reg:x10; val_offset:1234*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1234*FLEN/8, x12, x4, x7) + +inst_643: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78b0; op2val:0xfbff; + valaddr_reg:x10; val_offset:1236*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1236*FLEN/8, x12, x4, x7) + +inst_644: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78b0; op2val:0xfbff; + valaddr_reg:x10; val_offset:1238*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1238*FLEN/8, x12, x4, x7) + +inst_645: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x21c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x721c; op2val:0xfbff; + valaddr_reg:x10; val_offset:1240*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1240*FLEN/8, x12, x4, x7) + +inst_646: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x21c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x721c; op2val:0xfbff; + valaddr_reg:x10; val_offset:1242*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1242*FLEN/8, x12, x4, x7) + +inst_647: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x21c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x721c; op2val:0xfbff; + valaddr_reg:x10; val_offset:1244*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1244*FLEN/8, x12, x4, x7) + +inst_648: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x21c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x721c; op2val:0xfbff; + valaddr_reg:x10; val_offset:1246*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1246*FLEN/8, x12, x4, x7) + +inst_649: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x21c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x721c; op2val:0xfbff; + valaddr_reg:x10; val_offset:1248*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1248*FLEN/8, x12, x4, x7) + +inst_650: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3ea and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6fea; op2val:0xfbff; + valaddr_reg:x10; val_offset:1250*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1250*FLEN/8, x12, x4, x7) + +inst_651: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3ea and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6fea; op2val:0xfbff; + valaddr_reg:x10; val_offset:1252*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1252*FLEN/8, x12, x4, x7) + +inst_652: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3ea and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6fea; op2val:0xfbff; + valaddr_reg:x10; val_offset:1254*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1254*FLEN/8, x12, x4, x7) + +inst_653: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3ea and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6fea; op2val:0xfbff; + valaddr_reg:x10; val_offset:1256*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1256*FLEN/8, x12, x4, x7) + +inst_654: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3ea and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6fea; op2val:0xfbff; + valaddr_reg:x10; val_offset:1258*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1258*FLEN/8, x12, x4, x7) + +inst_655: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b9; op2val:0xfbff; + valaddr_reg:x10; val_offset:1260*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1260*FLEN/8, x12, x4, x7) + +inst_656: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b9; op2val:0xfbff; + valaddr_reg:x10; val_offset:1262*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1262*FLEN/8, x12, x4, x7) + +inst_657: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b9; op2val:0xfbff; + valaddr_reg:x10; val_offset:1264*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1264*FLEN/8, x12, x4, x7) + +inst_658: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b9; op2val:0xfbff; + valaddr_reg:x10; val_offset:1266*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1266*FLEN/8, x12, x4, x7) + +inst_659: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b9; op2val:0xfbff; + valaddr_reg:x10; val_offset:1268*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1268*FLEN/8, x12, x4, x7) + +inst_660: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x11c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d1c; op2val:0xfbff; + valaddr_reg:x10; val_offset:1270*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1270*FLEN/8, x12, x4, x7) + +inst_661: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x11c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d1c; op2val:0xfbff; + valaddr_reg:x10; val_offset:1272*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1272*FLEN/8, x12, x4, x7) + +inst_662: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x11c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d1c; op2val:0xfbff; + valaddr_reg:x10; val_offset:1274*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1274*FLEN/8, x12, x4, x7) + +inst_663: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x11c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d1c; op2val:0xfbff; + valaddr_reg:x10; val_offset:1276*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1276*FLEN/8, x12, x4, x7) + +inst_664: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x11c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d1c; op2val:0xfbff; + valaddr_reg:x10; val_offset:1278*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1278*FLEN/8, x12, x4, x7) + +inst_665: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1f8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x75f8; op2val:0x7bff; + valaddr_reg:x10; val_offset:1280*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1280*FLEN/8, x12, x4, x7) + +inst_666: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1f8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x75f8; op2val:0x7bff; + valaddr_reg:x10; val_offset:1282*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1282*FLEN/8, x12, x4, x7) +RVTEST_SIGBASE(x4,signature_x4_5) + +inst_667: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1f8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x75f8; op2val:0x7bff; + valaddr_reg:x10; val_offset:1284*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1284*FLEN/8, x12, x4, x7) + +inst_668: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1f8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x75f8; op2val:0x7bff; + valaddr_reg:x10; val_offset:1286*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1286*FLEN/8, x12, x4, x7) + +inst_669: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1f8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x75f8; op2val:0x7bff; + valaddr_reg:x10; val_offset:1288*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1288*FLEN/8, x12, x4, x7) + +inst_670: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x242 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a42; op2val:0x7bff; + valaddr_reg:x10; val_offset:1290*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1290*FLEN/8, x12, x4, x7) + +inst_671: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x242 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a42; op2val:0x7bff; + valaddr_reg:x10; val_offset:1292*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1292*FLEN/8, x12, x4, x7) + +inst_672: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x242 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a42; op2val:0x7bff; + valaddr_reg:x10; val_offset:1294*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1294*FLEN/8, x12, x4, x7) + +inst_673: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x242 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a42; op2val:0x7bff; + valaddr_reg:x10; val_offset:1296*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1296*FLEN/8, x12, x4, x7) + +inst_674: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x242 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a42; op2val:0x7bff; + valaddr_reg:x10; val_offset:1298*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1298*FLEN/8, x12, x4, x7) + +inst_675: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x267 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a67; op2val:0x7bff; + valaddr_reg:x10; val_offset:1300*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1300*FLEN/8, x12, x4, x7) + +inst_676: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x267 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a67; op2val:0x7bff; + valaddr_reg:x10; val_offset:1302*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1302*FLEN/8, x12, x4, x7) + +inst_677: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x267 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a67; op2val:0x7bff; + valaddr_reg:x10; val_offset:1304*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1304*FLEN/8, x12, x4, x7) + +inst_678: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x267 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a67; op2val:0x7bff; + valaddr_reg:x10; val_offset:1306*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1306*FLEN/8, x12, x4, x7) + +inst_679: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x267 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a67; op2val:0x7bff; + valaddr_reg:x10; val_offset:1308*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1308*FLEN/8, x12, x4, x7) + +inst_680: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x76e6; op2val:0x7bff; + valaddr_reg:x10; val_offset:1310*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1310*FLEN/8, x12, x4, x7) + +inst_681: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x76e6; op2val:0x7bff; + valaddr_reg:x10; val_offset:1312*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1312*FLEN/8, x12, x4, x7) + +inst_682: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x76e6; op2val:0x7bff; + valaddr_reg:x10; val_offset:1314*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1314*FLEN/8, x12, x4, x7) + +inst_683: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x76e6; op2val:0x7bff; + valaddr_reg:x10; val_offset:1316*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1316*FLEN/8, x12, x4, x7) + +inst_684: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x76e6; op2val:0x7bff; + valaddr_reg:x10; val_offset:1318*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1318*FLEN/8, x12, x4, x7) + +inst_685: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ef and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x77ef; op2val:0x7bff; + valaddr_reg:x10; val_offset:1320*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1320*FLEN/8, x12, x4, x7) + +inst_686: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ef and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x77ef; op2val:0x7bff; + valaddr_reg:x10; val_offset:1322*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1322*FLEN/8, x12, x4, x7) + +inst_687: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ef and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x77ef; op2val:0x7bff; + valaddr_reg:x10; val_offset:1324*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1324*FLEN/8, x12, x4, x7) + +inst_688: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ef and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x77ef; op2val:0x7bff; + valaddr_reg:x10; val_offset:1326*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1326*FLEN/8, x12, x4, x7) + +inst_689: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ef and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x77ef; op2val:0x7bff; + valaddr_reg:x10; val_offset:1328*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1328*FLEN/8, x12, x4, x7) + +inst_690: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2b9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x76b9; op2val:0x7bff; + valaddr_reg:x10; val_offset:1330*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1330*FLEN/8, x12, x4, x7) + +inst_691: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2b9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x76b9; op2val:0x7bff; + valaddr_reg:x10; val_offset:1332*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1332*FLEN/8, x12, x4, x7) + +inst_692: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2b9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x76b9; op2val:0x7bff; + valaddr_reg:x10; val_offset:1334*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1334*FLEN/8, x12, x4, x7) + +inst_693: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2b9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x76b9; op2val:0x7bff; + valaddr_reg:x10; val_offset:1336*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1336*FLEN/8, x12, x4, x7) + +inst_694: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2b9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x76b9; op2val:0x7bff; + valaddr_reg:x10; val_offset:1338*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1338*FLEN/8, x12, x4, x7) + +inst_695: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x35e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x775e; op2val:0x7bff; + valaddr_reg:x10; val_offset:1340*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1340*FLEN/8, x12, x4, x7) + +inst_696: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x35e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x775e; op2val:0x7bff; + valaddr_reg:x10; val_offset:1342*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1342*FLEN/8, x12, x4, x7) + +inst_697: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x35e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x775e; op2val:0x7bff; + valaddr_reg:x10; val_offset:1344*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1344*FLEN/8, x12, x4, x7) + +inst_698: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x35e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x775e; op2val:0x7bff; + valaddr_reg:x10; val_offset:1346*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1346*FLEN/8, x12, x4, x7) + +inst_699: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x35e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x775e; op2val:0x7bff; + valaddr_reg:x10; val_offset:1348*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1348*FLEN/8, x12, x4, x7) + +inst_700: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x048 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7848; op2val:0x7bff; + valaddr_reg:x10; val_offset:1350*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1350*FLEN/8, x12, x4, x7) + +inst_701: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x048 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7848; op2val:0x7bff; + valaddr_reg:x10; val_offset:1352*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1352*FLEN/8, x12, x4, x7) + +inst_702: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x048 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7848; op2val:0x7bff; + valaddr_reg:x10; val_offset:1354*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1354*FLEN/8, x12, x4, x7) + +inst_703: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x048 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7848; op2val:0x7bff; + valaddr_reg:x10; val_offset:1356*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1356*FLEN/8, x12, x4, x7) + +inst_704: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x048 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7848; op2val:0x7bff; + valaddr_reg:x10; val_offset:1358*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1358*FLEN/8, x12, x4, x7) + +inst_705: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x094 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c94; op2val:0x7bff; + valaddr_reg:x10; val_offset:1360*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1360*FLEN/8, x12, x4, x7) + +inst_706: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x094 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c94; op2val:0x7bff; + valaddr_reg:x10; val_offset:1362*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1362*FLEN/8, x12, x4, x7) + +inst_707: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x094 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c94; op2val:0x7bff; + valaddr_reg:x10; val_offset:1364*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1364*FLEN/8, x12, x4, x7) + +inst_708: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x094 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c94; op2val:0x7bff; + valaddr_reg:x10; val_offset:1366*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1366*FLEN/8, x12, x4, x7) + +inst_709: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x094 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c94; op2val:0x7bff; + valaddr_reg:x10; val_offset:1368*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1368*FLEN/8, x12, x4, x7) + +inst_710: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2cf and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x76cf; op2val:0x7bff; + valaddr_reg:x10; val_offset:1370*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1370*FLEN/8, x12, x4, x7) + +inst_711: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2cf and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x76cf; op2val:0x7bff; + valaddr_reg:x10; val_offset:1372*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1372*FLEN/8, x12, x4, x7) + +inst_712: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2cf and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x76cf; op2val:0x7bff; + valaddr_reg:x10; val_offset:1374*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1374*FLEN/8, x12, x4, x7) + +inst_713: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2cf and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x76cf; op2val:0x7bff; + valaddr_reg:x10; val_offset:1376*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1376*FLEN/8, x12, x4, x7) + +inst_714: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2cf and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x76cf; op2val:0x7bff; + valaddr_reg:x10; val_offset:1378*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1378*FLEN/8, x12, x4, x7) + +inst_715: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b7c; op2val:0x7bff; + valaddr_reg:x10; val_offset:1380*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1380*FLEN/8, x12, x4, x7) + +inst_716: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b7c; op2val:0x7bff; + valaddr_reg:x10; val_offset:1382*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1382*FLEN/8, x12, x4, x7) + +inst_717: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b7c; op2val:0x7bff; + valaddr_reg:x10; val_offset:1384*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1384*FLEN/8, x12, x4, x7) + +inst_718: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b7c; op2val:0x7bff; + valaddr_reg:x10; val_offset:1386*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1386*FLEN/8, x12, x4, x7) + +inst_719: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b7c; op2val:0x7bff; + valaddr_reg:x10; val_offset:1388*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1388*FLEN/8, x12, x4, x7) + +inst_720: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b2d; op2val:0x7bff; + valaddr_reg:x10; val_offset:1390*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1390*FLEN/8, x12, x4, x7) + +inst_721: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b2d; op2val:0x7bff; + valaddr_reg:x10; val_offset:1392*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1392*FLEN/8, x12, x4, x7) + +inst_722: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b2d; op2val:0x7bff; + valaddr_reg:x10; val_offset:1394*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1394*FLEN/8, x12, x4, x7) + +inst_723: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b2d; op2val:0x7bff; + valaddr_reg:x10; val_offset:1396*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1396*FLEN/8, x12, x4, x7) + +inst_724: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b2d; op2val:0x7bff; + valaddr_reg:x10; val_offset:1398*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1398*FLEN/8, x12, x4, x7) + +inst_725: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x031 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7431; op2val:0x7bff; + valaddr_reg:x10; val_offset:1400*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1400*FLEN/8, x12, x4, x7) + +inst_726: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x031 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7431; op2val:0x7bff; + valaddr_reg:x10; val_offset:1402*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1402*FLEN/8, x12, x4, x7) + +inst_727: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x031 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7431; op2val:0x7bff; + valaddr_reg:x10; val_offset:1404*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1404*FLEN/8, x12, x4, x7) + +inst_728: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x031 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7431; op2val:0x7bff; + valaddr_reg:x10; val_offset:1406*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1406*FLEN/8, x12, x4, x7) + +inst_729: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x031 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7431; op2val:0x7bff; + valaddr_reg:x10; val_offset:1408*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1408*FLEN/8, x12, x4, x7) + +inst_730: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6fe0; op2val:0x7bff; + valaddr_reg:x10; val_offset:1410*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1410*FLEN/8, x12, x4, x7) + +inst_731: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6fe0; op2val:0x7bff; + valaddr_reg:x10; val_offset:1412*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1412*FLEN/8, x12, x4, x7) + +inst_732: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6fe0; op2val:0x7bff; + valaddr_reg:x10; val_offset:1414*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1414*FLEN/8, x12, x4, x7) + +inst_733: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6fe0; op2val:0x7bff; + valaddr_reg:x10; val_offset:1416*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1416*FLEN/8, x12, x4, x7) + +inst_734: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6fe0; op2val:0x7bff; + valaddr_reg:x10; val_offset:1418*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1418*FLEN/8, x12, x4, x7) + +inst_735: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x14b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x794b; op2val:0xfbff; + valaddr_reg:x10; val_offset:1420*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1420*FLEN/8, x12, x4, x7) + +inst_736: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x14b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x794b; op2val:0xfbff; + valaddr_reg:x10; val_offset:1422*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1422*FLEN/8, x12, x4, x7) + +inst_737: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x14b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x794b; op2val:0xfbff; + valaddr_reg:x10; val_offset:1424*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1424*FLEN/8, x12, x4, x7) + +inst_738: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x14b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x794b; op2val:0xfbff; + valaddr_reg:x10; val_offset:1426*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1426*FLEN/8, x12, x4, x7) + +inst_739: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x14b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x794b; op2val:0xfbff; + valaddr_reg:x10; val_offset:1428*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1428*FLEN/8, x12, x4, x7) + +inst_740: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x256 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a56; op2val:0xfbff; + valaddr_reg:x10; val_offset:1430*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1430*FLEN/8, x12, x4, x7) + +inst_741: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x256 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a56; op2val:0xfbff; + valaddr_reg:x10; val_offset:1432*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1432*FLEN/8, x12, x4, x7) + +inst_742: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x256 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a56; op2val:0xfbff; + valaddr_reg:x10; val_offset:1434*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1434*FLEN/8, x12, x4, x7) + +inst_743: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x256 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a56; op2val:0xfbff; + valaddr_reg:x10; val_offset:1436*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1436*FLEN/8, x12, x4, x7) + +inst_744: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x256 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a56; op2val:0xfbff; + valaddr_reg:x10; val_offset:1438*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1438*FLEN/8, x12, x4, x7) + +inst_745: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1dd and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79dd; op2val:0xfbff; + valaddr_reg:x10; val_offset:1440*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1440*FLEN/8, x12, x4, x7) + +inst_746: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1dd and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79dd; op2val:0xfbff; + valaddr_reg:x10; val_offset:1442*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1442*FLEN/8, x12, x4, x7) + +inst_747: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1dd and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79dd; op2val:0xfbff; + valaddr_reg:x10; val_offset:1444*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1444*FLEN/8, x12, x4, x7) + +inst_748: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1dd and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79dd; op2val:0xfbff; + valaddr_reg:x10; val_offset:1446*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1446*FLEN/8, x12, x4, x7) + +inst_749: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1dd and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79dd; op2val:0xfbff; + valaddr_reg:x10; val_offset:1448*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1448*FLEN/8, x12, x4, x7) + +inst_750: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x299 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e99; op2val:0xfbff; + valaddr_reg:x10; val_offset:1450*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1450*FLEN/8, x12, x4, x7) + +inst_751: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x299 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e99; op2val:0xfbff; + valaddr_reg:x10; val_offset:1452*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1452*FLEN/8, x12, x4, x7) + +inst_752: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x299 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e99; op2val:0xfbff; + valaddr_reg:x10; val_offset:1454*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1454*FLEN/8, x12, x4, x7) + +inst_753: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x299 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e99; op2val:0xfbff; + valaddr_reg:x10; val_offset:1456*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1456*FLEN/8, x12, x4, x7) + +inst_754: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x299 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e99; op2val:0xfbff; + valaddr_reg:x10; val_offset:1458*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1458*FLEN/8, x12, x4, x7) + +inst_755: +// fs1 == 0 and fe1 == 0x17 and fm1 == 0x108 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5d08; op2val:0xfbff; + valaddr_reg:x10; val_offset:1460*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1460*FLEN/8, x12, x4, x7) + +inst_756: +// fs1 == 0 and fe1 == 0x17 and fm1 == 0x108 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5d08; op2val:0xfbff; + valaddr_reg:x10; val_offset:1462*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1462*FLEN/8, x12, x4, x7) + +inst_757: +// fs1 == 0 and fe1 == 0x17 and fm1 == 0x108 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5d08; op2val:0xfbff; + valaddr_reg:x10; val_offset:1464*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1464*FLEN/8, x12, x4, x7) + +inst_758: +// fs1 == 0 and fe1 == 0x17 and fm1 == 0x108 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5d08; op2val:0xfbff; + valaddr_reg:x10; val_offset:1466*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1466*FLEN/8, x12, x4, x7) + +inst_759: +// fs1 == 0 and fe1 == 0x17 and fm1 == 0x108 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5d08; op2val:0xfbff; + valaddr_reg:x10; val_offset:1468*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1468*FLEN/8, x12, x4, x7) + +inst_760: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x231 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a31; op2val:0xfbff; + valaddr_reg:x10; val_offset:1470*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1470*FLEN/8, x12, x4, x7) + +inst_761: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x231 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a31; op2val:0xfbff; + valaddr_reg:x10; val_offset:1472*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1472*FLEN/8, x12, x4, x7) + +inst_762: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x231 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a31; op2val:0xfbff; + valaddr_reg:x10; val_offset:1474*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1474*FLEN/8, x12, x4, x7) + +inst_763: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x231 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a31; op2val:0xfbff; + valaddr_reg:x10; val_offset:1476*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1476*FLEN/8, x12, x4, x7) + +inst_764: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x231 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a31; op2val:0xfbff; + valaddr_reg:x10; val_offset:1478*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1478*FLEN/8, x12, x4, x7) + +inst_765: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1df and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ddf; op2val:0xfbff; + valaddr_reg:x10; val_offset:1480*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1480*FLEN/8, x12, x4, x7) + +inst_766: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1df and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ddf; op2val:0xfbff; + valaddr_reg:x10; val_offset:1482*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1482*FLEN/8, x12, x4, x7) + +inst_767: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1df and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ddf; op2val:0xfbff; + valaddr_reg:x10; val_offset:1484*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1484*FLEN/8, x12, x4, x7) + +inst_768: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1df and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ddf; op2val:0xfbff; + valaddr_reg:x10; val_offset:1486*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1486*FLEN/8, x12, x4, x7) + +inst_769: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1df and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ddf; op2val:0xfbff; + valaddr_reg:x10; val_offset:1488*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1488*FLEN/8, x12, x4, x7) + +inst_770: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b0a; op2val:0xfbff; + valaddr_reg:x10; val_offset:1490*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1490*FLEN/8, x12, x4, x7) + +inst_771: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b0a; op2val:0xfbff; + valaddr_reg:x10; val_offset:1492*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1492*FLEN/8, x12, x4, x7) + +inst_772: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b0a; op2val:0xfbff; + valaddr_reg:x10; val_offset:1494*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1494*FLEN/8, x12, x4, x7) + +inst_773: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b0a; op2val:0xfbff; + valaddr_reg:x10; val_offset:1496*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1496*FLEN/8, x12, x4, x7) + +inst_774: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b0a; op2val:0xfbff; + valaddr_reg:x10; val_offset:1498*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1498*FLEN/8, x12, x4, x7) + +inst_775: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x203 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6603; op2val:0xfbff; + valaddr_reg:x10; val_offset:1500*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1500*FLEN/8, x12, x4, x7) + +inst_776: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x203 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6603; op2val:0xfbff; + valaddr_reg:x10; val_offset:1502*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1502*FLEN/8, x12, x4, x7) + +inst_777: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x203 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6603; op2val:0xfbff; + valaddr_reg:x10; val_offset:1504*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1504*FLEN/8, x12, x4, x7) + +inst_778: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x203 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6603; op2val:0xfbff; + valaddr_reg:x10; val_offset:1506*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1506*FLEN/8, x12, x4, x7) + +inst_779: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x203 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6603; op2val:0xfbff; + valaddr_reg:x10; val_offset:1508*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1508*FLEN/8, x12, x4, x7) + +inst_780: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3c2 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6fc2; op2val:0xfbff; + valaddr_reg:x10; val_offset:1510*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1510*FLEN/8, x12, x4, x7) + +inst_781: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3c2 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6fc2; op2val:0xfbff; + valaddr_reg:x10; val_offset:1512*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1512*FLEN/8, x12, x4, x7) + +inst_782: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3c2 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6fc2; op2val:0xfbff; + valaddr_reg:x10; val_offset:1514*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1514*FLEN/8, x12, x4, x7) + +inst_783: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3c2 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6fc2; op2val:0xfbff; + valaddr_reg:x10; val_offset:1516*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1516*FLEN/8, x12, x4, x7) + +inst_784: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3c2 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6fc2; op2val:0xfbff; + valaddr_reg:x10; val_offset:1518*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1518*FLEN/8, x12, x4, x7) + +inst_785: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x162 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7962; op2val:0xfbff; + valaddr_reg:x10; val_offset:1520*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1520*FLEN/8, x12, x4, x7) + +inst_786: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x162 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7962; op2val:0xfbff; + valaddr_reg:x10; val_offset:1522*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1522*FLEN/8, x12, x4, x7) + +inst_787: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x162 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7962; op2val:0xfbff; + valaddr_reg:x10; val_offset:1524*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1524*FLEN/8, x12, x4, x7) + +inst_788: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x162 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7962; op2val:0xfbff; + valaddr_reg:x10; val_offset:1526*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1526*FLEN/8, x12, x4, x7) + +inst_789: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x162 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7962; op2val:0xfbff; + valaddr_reg:x10; val_offset:1528*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1528*FLEN/8, x12, x4, x7) + +inst_790: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x39d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b9d; op2val:0xfbff; + valaddr_reg:x10; val_offset:1530*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1530*FLEN/8, x12, x4, x7) + +inst_791: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x39d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b9d; op2val:0xfbff; + valaddr_reg:x10; val_offset:1532*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1532*FLEN/8, x12, x4, x7) + +inst_792: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x39d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b9d; op2val:0xfbff; + valaddr_reg:x10; val_offset:1534*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1534*FLEN/8, x12, x4, x7) + +inst_793: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x39d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b9d; op2val:0xfbff; + valaddr_reg:x10; val_offset:1536*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1536*FLEN/8, x12, x4, x7) + +inst_794: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x39d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b9d; op2val:0xfbff; + valaddr_reg:x10; val_offset:1538*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1538*FLEN/8, x12, x4, x7) +RVTEST_SIGBASE(x4,signature_x4_6) + +inst_795: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x263 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a63; op2val:0xfbff; + valaddr_reg:x10; val_offset:1540*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1540*FLEN/8, x12, x4, x7) + +inst_796: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x263 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a63; op2val:0xfbff; + valaddr_reg:x10; val_offset:1542*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1542*FLEN/8, x12, x4, x7) + +inst_797: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x263 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a63; op2val:0xfbff; + valaddr_reg:x10; val_offset:1544*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1544*FLEN/8, x12, x4, x7) + +inst_798: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x263 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a63; op2val:0xfbff; + valaddr_reg:x10; val_offset:1546*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1546*FLEN/8, x12, x4, x7) + +inst_799: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x263 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a63; op2val:0xfbff; + valaddr_reg:x10; val_offset:1548*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1548*FLEN/8, x12, x4, x7) + +inst_800: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x222 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a22; op2val:0xfbff; + valaddr_reg:x10; val_offset:1550*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1550*FLEN/8, x12, x4, x7) + +inst_801: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x222 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a22; op2val:0xfbff; + valaddr_reg:x10; val_offset:1552*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1552*FLEN/8, x12, x4, x7) + +inst_802: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x222 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a22; op2val:0xfbff; + valaddr_reg:x10; val_offset:1554*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1554*FLEN/8, x12, x4, x7) + +inst_803: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x222 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a22; op2val:0xfbff; + valaddr_reg:x10; val_offset:1556*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1556*FLEN/8, x12, x4, x7) + +inst_804: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x222 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a22; op2val:0xfbff; + valaddr_reg:x10; val_offset:1558*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1558*FLEN/8, x12, x4, x7) + +inst_805: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b7; op2val:0x7bff; + valaddr_reg:x10; val_offset:1560*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1560*FLEN/8, x12, x4, x7) + +inst_806: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b7; op2val:0x7bff; + valaddr_reg:x10; val_offset:1562*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1562*FLEN/8, x12, x4, x7) + +inst_807: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b7; op2val:0x7bff; + valaddr_reg:x10; val_offset:1564*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1564*FLEN/8, x12, x4, x7) + +inst_808: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b7; op2val:0x7bff; + valaddr_reg:x10; val_offset:1566*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1566*FLEN/8, x12, x4, x7) + +inst_809: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b7; op2val:0x7bff; + valaddr_reg:x10; val_offset:1568*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1568*FLEN/8, x12, x4, x7) + +inst_810: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1fd and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79fd; op2val:0x7bff; + valaddr_reg:x10; val_offset:1570*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1570*FLEN/8, x12, x4, x7) + +inst_811: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1fd and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79fd; op2val:0x7bff; + valaddr_reg:x10; val_offset:1572*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1572*FLEN/8, x12, x4, x7) + +inst_812: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1fd and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79fd; op2val:0x7bff; + valaddr_reg:x10; val_offset:1574*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1574*FLEN/8, x12, x4, x7) + +inst_813: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1fd and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79fd; op2val:0x7bff; + valaddr_reg:x10; val_offset:1576*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1576*FLEN/8, x12, x4, x7) + +inst_814: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1fd and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79fd; op2val:0x7bff; + valaddr_reg:x10; val_offset:1578*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1578*FLEN/8, x12, x4, x7) + +inst_815: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3d2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6bd2; op2val:0x7bff; + valaddr_reg:x10; val_offset:1580*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1580*FLEN/8, x12, x4, x7) + +inst_816: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3d2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6bd2; op2val:0x7bff; + valaddr_reg:x10; val_offset:1582*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1582*FLEN/8, x12, x4, x7) + +inst_817: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3d2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6bd2; op2val:0x7bff; + valaddr_reg:x10; val_offset:1584*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1584*FLEN/8, x12, x4, x7) + +inst_818: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3d2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6bd2; op2val:0x7bff; + valaddr_reg:x10; val_offset:1586*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1586*FLEN/8, x12, x4, x7) + +inst_819: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3d2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6bd2; op2val:0x7bff; + valaddr_reg:x10; val_offset:1588*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1588*FLEN/8, x12, x4, x7) + +inst_820: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x082 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7882; op2val:0x7bff; + valaddr_reg:x10; val_offset:1590*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1590*FLEN/8, x12, x4, x7) + +inst_821: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x082 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7882; op2val:0x7bff; + valaddr_reg:x10; val_offset:1592*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1592*FLEN/8, x12, x4, x7) + +inst_822: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x082 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7882; op2val:0x7bff; + valaddr_reg:x10; val_offset:1594*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1594*FLEN/8, x12, x4, x7) + +inst_823: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x082 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7882; op2val:0x7bff; + valaddr_reg:x10; val_offset:1596*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1596*FLEN/8, x12, x4, x7) + +inst_824: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x082 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7882; op2val:0x7bff; + valaddr_reg:x10; val_offset:1598*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1598*FLEN/8, x12, x4, x7) + +inst_825: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3be and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x73be; op2val:0x7bff; + valaddr_reg:x10; val_offset:1600*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1600*FLEN/8, x12, x4, x7) + +inst_826: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3be and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x73be; op2val:0x7bff; + valaddr_reg:x10; val_offset:1602*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1602*FLEN/8, x12, x4, x7) + +inst_827: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3be and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x73be; op2val:0x7bff; + valaddr_reg:x10; val_offset:1604*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1604*FLEN/8, x12, x4, x7) + +inst_828: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3be and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x73be; op2val:0x7bff; + valaddr_reg:x10; val_offset:1606*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1606*FLEN/8, x12, x4, x7) + +inst_829: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3be and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x73be; op2val:0x7bff; + valaddr_reg:x10; val_offset:1608*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1608*FLEN/8, x12, x4, x7) + +inst_830: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x73fe; op2val:0x7bff; + valaddr_reg:x10; val_offset:1610*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1610*FLEN/8, x12, x4, x7) + +inst_831: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x73fe; op2val:0x7bff; + valaddr_reg:x10; val_offset:1612*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1612*FLEN/8, x12, x4, x7) + +inst_832: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x73fe; op2val:0x7bff; + valaddr_reg:x10; val_offset:1614*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1614*FLEN/8, x12, x4, x7) + +inst_833: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x73fe; op2val:0x7bff; + valaddr_reg:x10; val_offset:1616*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1616*FLEN/8, x12, x4, x7) + +inst_834: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x73fe; op2val:0x7bff; + valaddr_reg:x10; val_offset:1618*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1618*FLEN/8, x12, x4, x7) + +inst_835: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x206 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a06; op2val:0x7bff; + valaddr_reg:x10; val_offset:1620*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1620*FLEN/8, x12, x4, x7) + +inst_836: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x206 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a06; op2val:0x7bff; + valaddr_reg:x10; val_offset:1622*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1622*FLEN/8, x12, x4, x7) + +inst_837: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x206 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a06; op2val:0x7bff; + valaddr_reg:x10; val_offset:1624*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1624*FLEN/8, x12, x4, x7) + +inst_838: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x206 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a06; op2val:0x7bff; + valaddr_reg:x10; val_offset:1626*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1626*FLEN/8, x12, x4, x7) + +inst_839: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x206 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a06; op2val:0x7bff; + valaddr_reg:x10; val_offset:1628*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1628*FLEN/8, x12, x4, x7) + +inst_840: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1e0 and fs2 == 0 and fe2 == 0x17 and fm2 == 0x1e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x75e0; op2val:0x5de0; + valaddr_reg:x10; val_offset:1630*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1630*FLEN/8, x12, x4, x7) + +inst_841: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1e0 and fs2 == 0 and fe2 == 0x17 and fm2 == 0x1e0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x75e0; op2val:0x5de0; + valaddr_reg:x10; val_offset:1632*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1632*FLEN/8, x12, x4, x7) + +inst_842: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1e0 and fs2 == 0 and fe2 == 0x17 and fm2 == 0x1e0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x75e0; op2val:0x5de0; + valaddr_reg:x10; val_offset:1634*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1634*FLEN/8, x12, x4, x7) + +inst_843: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1e0 and fs2 == 0 and fe2 == 0x17 and fm2 == 0x1e0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x75e0; op2val:0x5de0; + valaddr_reg:x10; val_offset:1636*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1636*FLEN/8, x12, x4, x7) + +inst_844: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1e0 and fs2 == 0 and fe2 == 0x17 and fm2 == 0x1e0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x75e0; op2val:0x5de0; + valaddr_reg:x10; val_offset:1638*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1638*FLEN/8, x12, x4, x7) + +inst_845: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x19a and fs2 == 0 and fe2 == 0x17 and fm2 == 0x19a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x759a; op2val:0x5d9a; + valaddr_reg:x10; val_offset:1640*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1640*FLEN/8, x12, x4, x7) + +inst_846: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x19a and fs2 == 0 and fe2 == 0x17 and fm2 == 0x19a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x759a; op2val:0x5d9a; + valaddr_reg:x10; val_offset:1642*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1642*FLEN/8, x12, x4, x7) + +inst_847: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x19a and fs2 == 0 and fe2 == 0x17 and fm2 == 0x19a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x759a; op2val:0x5d9a; + valaddr_reg:x10; val_offset:1644*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1644*FLEN/8, x12, x4, x7) + +inst_848: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x19a and fs2 == 0 and fe2 == 0x17 and fm2 == 0x19a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x759a; op2val:0x5d9a; + valaddr_reg:x10; val_offset:1646*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1646*FLEN/8, x12, x4, x7) + +inst_849: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x19a and fs2 == 0 and fe2 == 0x17 and fm2 == 0x19a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x759a; op2val:0x5d9a; + valaddr_reg:x10; val_offset:1648*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1648*FLEN/8, x12, x4, x7) + +inst_850: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x153 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x153 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d53; op2val:0x5553; + valaddr_reg:x10; val_offset:1650*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1650*FLEN/8, x12, x4, x7) + +inst_851: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x153 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x153 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d53; op2val:0x5553; + valaddr_reg:x10; val_offset:1652*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1652*FLEN/8, x12, x4, x7) + +inst_852: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x153 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x153 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d53; op2val:0x5553; + valaddr_reg:x10; val_offset:1654*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1654*FLEN/8, x12, x4, x7) + +inst_853: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x153 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x153 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d53; op2val:0x5553; + valaddr_reg:x10; val_offset:1656*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1656*FLEN/8, x12, x4, x7) + +inst_854: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x153 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x153 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d53; op2val:0x5553; + valaddr_reg:x10; val_offset:1658*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1658*FLEN/8, x12, x4, x7) + +inst_855: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c7 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x3c7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bc7; op2val:0x63c7; + valaddr_reg:x10; val_offset:1660*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1660*FLEN/8, x12, x4, x7) + +inst_856: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c7 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x3c7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bc7; op2val:0x63c7; + valaddr_reg:x10; val_offset:1662*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1662*FLEN/8, x12, x4, x7) + +inst_857: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c7 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x3c7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bc7; op2val:0x63c7; + valaddr_reg:x10; val_offset:1664*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1664*FLEN/8, x12, x4, x7) + +inst_858: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c7 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x3c7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bc7; op2val:0x63c7; + valaddr_reg:x10; val_offset:1666*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1666*FLEN/8, x12, x4, x7) + +inst_859: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c7 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x3c7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bc7; op2val:0x63c7; + valaddr_reg:x10; val_offset:1668*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1668*FLEN/8, x12, x4, x7) + +inst_860: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f9 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x1f9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79f9; op2val:0x61f9; + valaddr_reg:x10; val_offset:1670*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1670*FLEN/8, x12, x4, x7) + +inst_861: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f9 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x1f9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79f9; op2val:0x61f9; + valaddr_reg:x10; val_offset:1672*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1672*FLEN/8, x12, x4, x7) + +inst_862: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f9 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x1f9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79f9; op2val:0x61f9; + valaddr_reg:x10; val_offset:1674*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1674*FLEN/8, x12, x4, x7) + +inst_863: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f9 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x1f9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79f9; op2val:0x61f9; + valaddr_reg:x10; val_offset:1676*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1676*FLEN/8, x12, x4, x7) + +inst_864: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f9 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x1f9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79f9; op2val:0x61f9; + valaddr_reg:x10; val_offset:1678*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1678*FLEN/8, x12, x4, x7) + +inst_865: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x186 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x186 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7986; op2val:0x6186; + valaddr_reg:x10; val_offset:1680*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1680*FLEN/8, x12, x4, x7) + +inst_866: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x186 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x186 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7986; op2val:0x6186; + valaddr_reg:x10; val_offset:1682*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1682*FLEN/8, x12, x4, x7) + +inst_867: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x186 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x186 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7986; op2val:0x6186; + valaddr_reg:x10; val_offset:1684*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1684*FLEN/8, x12, x4, x7) + +inst_868: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x186 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x186 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7986; op2val:0x6186; + valaddr_reg:x10; val_offset:1686*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1686*FLEN/8, x12, x4, x7) + +inst_869: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x186 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x186 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7986; op2val:0x6186; + valaddr_reg:x10; val_offset:1688*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1688*FLEN/8, x12, x4, x7) + +inst_870: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x163 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x163 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7963; op2val:0x6163; + valaddr_reg:x10; val_offset:1690*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1690*FLEN/8, x12, x4, x7) + +inst_871: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x163 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x163 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7963; op2val:0x6163; + valaddr_reg:x10; val_offset:1692*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1692*FLEN/8, x12, x4, x7) + +inst_872: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x163 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x163 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7963; op2val:0x6163; + valaddr_reg:x10; val_offset:1694*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1694*FLEN/8, x12, x4, x7) + +inst_873: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x163 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x163 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7963; op2val:0x6163; + valaddr_reg:x10; val_offset:1696*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1696*FLEN/8, x12, x4, x7) + +inst_874: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x163 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x163 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7963; op2val:0x6163; + valaddr_reg:x10; val_offset:1698*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1698*FLEN/8, x12, x4, x7) + +inst_875: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3bc and fs2 == 1 and fe2 == 0x17 and fm2 == 0x3bc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x77bc; op2val:0xdfbc; + valaddr_reg:x10; val_offset:1700*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1700*FLEN/8, x12, x4, x7) + +inst_876: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3bc and fs2 == 1 and fe2 == 0x17 and fm2 == 0x3bc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x77bc; op2val:0xdfbc; + valaddr_reg:x10; val_offset:1702*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1702*FLEN/8, x12, x4, x7) + +inst_877: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3bc and fs2 == 1 and fe2 == 0x17 and fm2 == 0x3bc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x77bc; op2val:0xdfbc; + valaddr_reg:x10; val_offset:1704*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1704*FLEN/8, x12, x4, x7) + +inst_878: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3bc and fs2 == 1 and fe2 == 0x17 and fm2 == 0x3bc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x77bc; op2val:0xdfbc; + valaddr_reg:x10; val_offset:1706*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1706*FLEN/8, x12, x4, x7) + +inst_879: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3bc and fs2 == 1 and fe2 == 0x17 and fm2 == 0x3bc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x77bc; op2val:0xdfbc; + valaddr_reg:x10; val_offset:1708*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1708*FLEN/8, x12, x4, x7) + +inst_880: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32c and fs2 == 1 and fe2 == 0x18 and fm2 == 0x32c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b2c; op2val:0xe32c; + valaddr_reg:x10; val_offset:1710*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1710*FLEN/8, x12, x4, x7) + +inst_881: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32c and fs2 == 1 and fe2 == 0x18 and fm2 == 0x32c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b2c; op2val:0xe32c; + valaddr_reg:x10; val_offset:1712*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1712*FLEN/8, x12, x4, x7) + +inst_882: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32c and fs2 == 1 and fe2 == 0x18 and fm2 == 0x32c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b2c; op2val:0xe32c; + valaddr_reg:x10; val_offset:1714*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1714*FLEN/8, x12, x4, x7) + +inst_883: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32c and fs2 == 1 and fe2 == 0x18 and fm2 == 0x32c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b2c; op2val:0xe32c; + valaddr_reg:x10; val_offset:1716*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1716*FLEN/8, x12, x4, x7) + +inst_884: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32c and fs2 == 1 and fe2 == 0x18 and fm2 == 0x32c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b2c; op2val:0xe32c; + valaddr_reg:x10; val_offset:1718*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1718*FLEN/8, x12, x4, x7) + +inst_885: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x222 and fs2 == 1 and fe2 == 0x15 and fm2 == 0x222 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e22; op2val:0xd622; + valaddr_reg:x10; val_offset:1720*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1720*FLEN/8, x12, x4, x7) + +inst_886: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x222 and fs2 == 1 and fe2 == 0x15 and fm2 == 0x222 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e22; op2val:0xd622; + valaddr_reg:x10; val_offset:1722*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1722*FLEN/8, x12, x4, x7) + +inst_887: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x222 and fs2 == 1 and fe2 == 0x15 and fm2 == 0x222 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e22; op2val:0xd622; + valaddr_reg:x10; val_offset:1724*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1724*FLEN/8, x12, x4, x7) + +inst_888: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x222 and fs2 == 1 and fe2 == 0x15 and fm2 == 0x222 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e22; op2val:0xd622; + valaddr_reg:x10; val_offset:1726*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1726*FLEN/8, x12, x4, x7) + +inst_889: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x222 and fs2 == 1 and fe2 == 0x15 and fm2 == 0x222 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e22; op2val:0xd622; + valaddr_reg:x10; val_offset:1728*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1728*FLEN/8, x12, x4, x7) + +inst_890: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x354 and fs2 == 1 and fe2 == 0x18 and fm2 == 0x354 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b54; op2val:0xe354; + valaddr_reg:x10; val_offset:1730*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1730*FLEN/8, x12, x4, x7) + +inst_891: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x354 and fs2 == 1 and fe2 == 0x18 and fm2 == 0x354 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b54; op2val:0xe354; + valaddr_reg:x10; val_offset:1732*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1732*FLEN/8, x12, x4, x7) + +inst_892: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x354 and fs2 == 1 and fe2 == 0x18 and fm2 == 0x354 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b54; op2val:0xe354; + valaddr_reg:x10; val_offset:1734*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1734*FLEN/8, x12, x4, x7) + +inst_893: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x354 and fs2 == 1 and fe2 == 0x18 and fm2 == 0x354 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b54; op2val:0xe354; + valaddr_reg:x10; val_offset:1736*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1736*FLEN/8, x12, x4, x7) + +inst_894: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x354 and fs2 == 1 and fe2 == 0x18 and fm2 == 0x354 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b54; op2val:0xe354; + valaddr_reg:x10; val_offset:1738*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1738*FLEN/8, x12, x4, x7) + +inst_895: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x315 and fs2 == 1 and fe2 == 0x17 and fm2 == 0x315 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7715; op2val:0xdf15; + valaddr_reg:x10; val_offset:1740*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1740*FLEN/8, x12, x4, x7) + +inst_896: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x315 and fs2 == 1 and fe2 == 0x17 and fm2 == 0x315 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7715; op2val:0xdf15; + valaddr_reg:x10; val_offset:1742*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1742*FLEN/8, x12, x4, x7) + +inst_897: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x315 and fs2 == 1 and fe2 == 0x17 and fm2 == 0x315 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7715; op2val:0xdf15; + valaddr_reg:x10; val_offset:1744*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1744*FLEN/8, x12, x4, x7) + +inst_898: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x315 and fs2 == 1 and fe2 == 0x17 and fm2 == 0x315 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7715; op2val:0xdf15; + valaddr_reg:x10; val_offset:1746*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1746*FLEN/8, x12, x4, x7) + +inst_899: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x315 and fs2 == 1 and fe2 == 0x17 and fm2 == 0x315 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7715; op2val:0xdf15; + valaddr_reg:x10; val_offset:1748*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1748*FLEN/8, x12, x4, x7) + +inst_900: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1f3 and fs2 == 1 and fe2 == 0x16 and fm2 == 0x1f3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x71f3; op2val:0xd9f3; + valaddr_reg:x10; val_offset:1750*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1750*FLEN/8, x12, x4, x7) + +inst_901: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1f3 and fs2 == 1 and fe2 == 0x16 and fm2 == 0x1f3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x71f3; op2val:0xd9f3; + valaddr_reg:x10; val_offset:1752*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1752*FLEN/8, x12, x4, x7) + +inst_902: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1f3 and fs2 == 1 and fe2 == 0x16 and fm2 == 0x1f3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x71f3; op2val:0xd9f3; + valaddr_reg:x10; val_offset:1754*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1754*FLEN/8, x12, x4, x7) + +inst_903: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1f3 and fs2 == 1 and fe2 == 0x16 and fm2 == 0x1f3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x71f3; op2val:0xd9f3; + valaddr_reg:x10; val_offset:1756*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1756*FLEN/8, x12, x4, x7) + +inst_904: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1f3 and fs2 == 1 and fe2 == 0x16 and fm2 == 0x1f3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x71f3; op2val:0xd9f3; + valaddr_reg:x10; val_offset:1758*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1758*FLEN/8, x12, x4, x7) + +inst_905: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x25e and fs2 == 1 and fe2 == 0x16 and fm2 == 0x25e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x725e; op2val:0xda5e; + valaddr_reg:x10; val_offset:1760*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1760*FLEN/8, x12, x4, x7) + +inst_906: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x25e and fs2 == 1 and fe2 == 0x16 and fm2 == 0x25e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x725e; op2val:0xda5e; + valaddr_reg:x10; val_offset:1762*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1762*FLEN/8, x12, x4, x7) + +inst_907: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x25e and fs2 == 1 and fe2 == 0x16 and fm2 == 0x25e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x725e; op2val:0xda5e; + valaddr_reg:x10; val_offset:1764*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1764*FLEN/8, x12, x4, x7) + +inst_908: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x25e and fs2 == 1 and fe2 == 0x16 and fm2 == 0x25e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x725e; op2val:0xda5e; + valaddr_reg:x10; val_offset:1766*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1766*FLEN/8, x12, x4, x7) + +inst_909: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x25e and fs2 == 1 and fe2 == 0x16 and fm2 == 0x25e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x725e; op2val:0xda5e; + valaddr_reg:x10; val_offset:1768*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1768*FLEN/8, x12, x4, x7) + +inst_910: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x109 and fs2 == 1 and fe2 == 0x17 and fm2 == 0x109 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7509; op2val:0xdd09; + valaddr_reg:x10; val_offset:1770*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1770*FLEN/8, x12, x4, x7) + +inst_911: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x109 and fs2 == 1 and fe2 == 0x17 and fm2 == 0x109 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7509; op2val:0xdd09; + valaddr_reg:x10; val_offset:1772*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1772*FLEN/8, x12, x4, x7) + +inst_912: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x109 and fs2 == 1 and fe2 == 0x17 and fm2 == 0x109 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7509; op2val:0xdd09; + valaddr_reg:x10; val_offset:1774*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1774*FLEN/8, x12, x4, x7) + +inst_913: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x109 and fs2 == 1 and fe2 == 0x17 and fm2 == 0x109 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7509; op2val:0xdd09; + valaddr_reg:x10; val_offset:1776*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1776*FLEN/8, x12, x4, x7) + +inst_914: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x109 and fs2 == 1 and fe2 == 0x17 and fm2 == 0x109 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7509; op2val:0xdd09; + valaddr_reg:x10; val_offset:1778*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1778*FLEN/8, x12, x4, x7) + +inst_915: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x186 and fs2 == 1 and fe2 == 0x18 and fm2 == 0x186 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7986; op2val:0xe186; + valaddr_reg:x10; val_offset:1780*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1780*FLEN/8, x12, x4, x7) + +inst_916: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x186 and fs2 == 1 and fe2 == 0x18 and fm2 == 0x186 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7986; op2val:0xe186; + valaddr_reg:x10; val_offset:1782*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1782*FLEN/8, x12, x4, x7) + +inst_917: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x186 and fs2 == 1 and fe2 == 0x18 and fm2 == 0x186 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7986; op2val:0xe186; + valaddr_reg:x10; val_offset:1784*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1784*FLEN/8, x12, x4, x7) + +inst_918: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x186 and fs2 == 1 and fe2 == 0x18 and fm2 == 0x186 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7986; op2val:0xe186; + valaddr_reg:x10; val_offset:1786*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1786*FLEN/8, x12, x4, x7) + +inst_919: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x186 and fs2 == 1 and fe2 == 0x18 and fm2 == 0x186 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7986; op2val:0xe186; + valaddr_reg:x10; val_offset:1788*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1788*FLEN/8, x12, x4, x7) + +inst_920: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0bb and fs2 == 1 and fe2 == 0x17 and fm2 == 0x0bb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74bb; op2val:0xdcbb; + valaddr_reg:x10; val_offset:1790*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1790*FLEN/8, x12, x4, x7) + +inst_921: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0bb and fs2 == 1 and fe2 == 0x17 and fm2 == 0x0bb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74bb; op2val:0xdcbb; + valaddr_reg:x10; val_offset:1792*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1792*FLEN/8, x12, x4, x7) + +inst_922: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0bb and fs2 == 1 and fe2 == 0x17 and fm2 == 0x0bb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74bb; op2val:0xdcbb; + valaddr_reg:x10; val_offset:1794*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1794*FLEN/8, x12, x4, x7) +RVTEST_SIGBASE(x4,signature_x4_7) + +inst_923: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0bb and fs2 == 1 and fe2 == 0x17 and fm2 == 0x0bb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74bb; op2val:0xdcbb; + valaddr_reg:x10; val_offset:1796*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1796*FLEN/8, x12, x4, x7) + +inst_924: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0bb and fs2 == 1 and fe2 == 0x17 and fm2 == 0x0bb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74bb; op2val:0xdcbb; + valaddr_reg:x10; val_offset:1798*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1798*FLEN/8, x12, x4, x7) + +inst_925: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x29b and fs2 == 1 and fe2 == 0x17 and fm2 == 0x29b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x769b; op2val:0xde9b; + valaddr_reg:x10; val_offset:1800*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1800*FLEN/8, x12, x4, x7) + +inst_926: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x29b and fs2 == 1 and fe2 == 0x17 and fm2 == 0x29b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x769b; op2val:0xde9b; + valaddr_reg:x10; val_offset:1802*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1802*FLEN/8, x12, x4, x7) + +inst_927: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x29b and fs2 == 1 and fe2 == 0x17 and fm2 == 0x29b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x769b; op2val:0xde9b; + valaddr_reg:x10; val_offset:1804*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1804*FLEN/8, x12, x4, x7) + +inst_928: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x29b and fs2 == 1 and fe2 == 0x17 and fm2 == 0x29b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x769b; op2val:0xde9b; + valaddr_reg:x10; val_offset:1806*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1806*FLEN/8, x12, x4, x7) + +inst_929: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x29b and fs2 == 1 and fe2 == 0x17 and fm2 == 0x29b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x769b; op2val:0xde9b; + valaddr_reg:x10; val_offset:1808*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1808*FLEN/8, x12, x4, x7) + +inst_930: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ac and fs2 == 1 and fe2 == 0x18 and fm2 == 0x0ac and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78ac; op2val:0xe0ac; + valaddr_reg:x10; val_offset:1810*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1810*FLEN/8, x12, x4, x7) + +inst_931: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ac and fs2 == 1 and fe2 == 0x18 and fm2 == 0x0ac and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78ac; op2val:0xe0ac; + valaddr_reg:x10; val_offset:1812*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1812*FLEN/8, x12, x4, x7) + +inst_932: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ac and fs2 == 1 and fe2 == 0x18 and fm2 == 0x0ac and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78ac; op2val:0xe0ac; + valaddr_reg:x10; val_offset:1814*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1814*FLEN/8, x12, x4, x7) + +inst_933: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ac and fs2 == 1 and fe2 == 0x18 and fm2 == 0x0ac and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78ac; op2val:0xe0ac; + valaddr_reg:x10; val_offset:1816*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1816*FLEN/8, x12, x4, x7) + +inst_934: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ac and fs2 == 1 and fe2 == 0x18 and fm2 == 0x0ac and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78ac; op2val:0xe0ac; + valaddr_reg:x10; val_offset:1818*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1818*FLEN/8, x12, x4, x7) + +inst_935: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2f5 and fs2 == 1 and fe2 == 0x16 and fm2 == 0x2f5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x72f5; op2val:0xdaf5; + valaddr_reg:x10; val_offset:1820*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1820*FLEN/8, x12, x4, x7) + +inst_936: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2f5 and fs2 == 1 and fe2 == 0x16 and fm2 == 0x2f5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x72f5; op2val:0xdaf5; + valaddr_reg:x10; val_offset:1822*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1822*FLEN/8, x12, x4, x7) + +inst_937: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2f5 and fs2 == 1 and fe2 == 0x16 and fm2 == 0x2f5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x72f5; op2val:0xdaf5; + valaddr_reg:x10; val_offset:1824*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1824*FLEN/8, x12, x4, x7) + +inst_938: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2f5 and fs2 == 1 and fe2 == 0x16 and fm2 == 0x2f5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x72f5; op2val:0xdaf5; + valaddr_reg:x10; val_offset:1826*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1826*FLEN/8, x12, x4, x7) + +inst_939: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2f5 and fs2 == 1 and fe2 == 0x16 and fm2 == 0x2f5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x72f5; op2val:0xdaf5; + valaddr_reg:x10; val_offset:1828*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1828*FLEN/8, x12, x4, x7) + +inst_940: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ab and fs2 == 1 and fe2 == 0x17 and fm2 == 0x3ab and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x77ab; op2val:0xdfab; + valaddr_reg:x10; val_offset:1830*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1830*FLEN/8, x12, x4, x7) + +inst_941: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ab and fs2 == 1 and fe2 == 0x17 and fm2 == 0x3ab and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x77ab; op2val:0xdfab; + valaddr_reg:x10; val_offset:1832*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1832*FLEN/8, x12, x4, x7) + +inst_942: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ab and fs2 == 1 and fe2 == 0x17 and fm2 == 0x3ab and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x77ab; op2val:0xdfab; + valaddr_reg:x10; val_offset:1834*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1834*FLEN/8, x12, x4, x7) + +inst_943: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ab and fs2 == 1 and fe2 == 0x17 and fm2 == 0x3ab and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x77ab; op2val:0xdfab; + valaddr_reg:x10; val_offset:1836*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1836*FLEN/8, x12, x4, x7) + +inst_944: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ab and fs2 == 1 and fe2 == 0x17 and fm2 == 0x3ab and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x77ab; op2val:0xdfab; + valaddr_reg:x10; val_offset:1838*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1838*FLEN/8, x12, x4, x7) + +inst_945: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x182 and fs2 == 0 and fe2 == 0x16 and fm2 == 0x182 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7182; op2val:0x5982; + valaddr_reg:x10; val_offset:1840*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1840*FLEN/8, x12, x4, x7) + +inst_946: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x182 and fs2 == 0 and fe2 == 0x16 and fm2 == 0x182 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7182; op2val:0x5982; + valaddr_reg:x10; val_offset:1842*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1842*FLEN/8, x12, x4, x7) + +inst_947: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x182 and fs2 == 0 and fe2 == 0x16 and fm2 == 0x182 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7182; op2val:0x5982; + valaddr_reg:x10; val_offset:1844*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1844*FLEN/8, x12, x4, x7) + +inst_948: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x182 and fs2 == 0 and fe2 == 0x16 and fm2 == 0x182 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7182; op2val:0x5982; + valaddr_reg:x10; val_offset:1846*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1846*FLEN/8, x12, x4, x7) + +inst_949: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x182 and fs2 == 0 and fe2 == 0x16 and fm2 == 0x182 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7182; op2val:0x5982; + valaddr_reg:x10; val_offset:1848*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1848*FLEN/8, x12, x4, x7) + +inst_950: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x126 and fs2 == 0 and fe2 == 0x17 and fm2 == 0x126 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7526; op2val:0x5d26; + valaddr_reg:x10; val_offset:1850*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1850*FLEN/8, x12, x4, x7) + +inst_951: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x126 and fs2 == 0 and fe2 == 0x17 and fm2 == 0x126 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7526; op2val:0x5d26; + valaddr_reg:x10; val_offset:1852*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1852*FLEN/8, x12, x4, x7) + +inst_952: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x126 and fs2 == 0 and fe2 == 0x17 and fm2 == 0x126 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7526; op2val:0x5d26; + valaddr_reg:x10; val_offset:1854*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1854*FLEN/8, x12, x4, x7) + +inst_953: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x126 and fs2 == 0 and fe2 == 0x17 and fm2 == 0x126 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7526; op2val:0x5d26; + valaddr_reg:x10; val_offset:1856*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1856*FLEN/8, x12, x4, x7) + +inst_954: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x126 and fs2 == 0 and fe2 == 0x17 and fm2 == 0x126 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7526; op2val:0x5d26; + valaddr_reg:x10; val_offset:1858*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1858*FLEN/8, x12, x4, x7) + +inst_955: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x097 and fs2 == 0 and fe2 == 0x16 and fm2 == 0x097 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7097; op2val:0x5897; + valaddr_reg:x10; val_offset:1860*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1860*FLEN/8, x12, x4, x7) + +inst_956: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x097 and fs2 == 0 and fe2 == 0x16 and fm2 == 0x097 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7097; op2val:0x5897; + valaddr_reg:x10; val_offset:1862*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1862*FLEN/8, x12, x4, x7) + +inst_957: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x097 and fs2 == 0 and fe2 == 0x16 and fm2 == 0x097 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7097; op2val:0x5897; + valaddr_reg:x10; val_offset:1864*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1864*FLEN/8, x12, x4, x7) + +inst_958: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x097 and fs2 == 0 and fe2 == 0x16 and fm2 == 0x097 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7097; op2val:0x5897; + valaddr_reg:x10; val_offset:1866*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1866*FLEN/8, x12, x4, x7) + +inst_959: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x097 and fs2 == 0 and fe2 == 0x16 and fm2 == 0x097 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7097; op2val:0x5897; + valaddr_reg:x10; val_offset:1868*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1868*FLEN/8, x12, x4, x7) + +inst_960: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ab and fs2 == 0 and fe2 == 0x17 and fm2 == 0x3ab and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x77ab; op2val:0x5fab; + valaddr_reg:x10; val_offset:1870*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1870*FLEN/8, x12, x4, x7) + +inst_961: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ab and fs2 == 0 and fe2 == 0x17 and fm2 == 0x3ab and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x77ab; op2val:0x5fab; + valaddr_reg:x10; val_offset:1872*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1872*FLEN/8, x12, x4, x7) + +inst_962: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ab and fs2 == 0 and fe2 == 0x17 and fm2 == 0x3ab and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x77ab; op2val:0x5fab; + valaddr_reg:x10; val_offset:1874*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1874*FLEN/8, x12, x4, x7) + +inst_963: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ab and fs2 == 0 and fe2 == 0x17 and fm2 == 0x3ab and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x77ab; op2val:0x5fab; + valaddr_reg:x10; val_offset:1876*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1876*FLEN/8, x12, x4, x7) + +inst_964: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ab and fs2 == 0 and fe2 == 0x17 and fm2 == 0x3ab and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x77ab; op2val:0x5fab; + valaddr_reg:x10; val_offset:1878*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1878*FLEN/8, x12, x4, x7) + +inst_965: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x37c and fs2 == 0 and fe2 == 0x17 and fm2 == 0x37c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x777c; op2val:0x5f7c; + valaddr_reg:x10; val_offset:1880*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1880*FLEN/8, x12, x4, x7) + +inst_966: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x37c and fs2 == 0 and fe2 == 0x17 and fm2 == 0x37c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x777c; op2val:0x5f7c; + valaddr_reg:x10; val_offset:1882*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1882*FLEN/8, x12, x4, x7) + +inst_967: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x37c and fs2 == 0 and fe2 == 0x17 and fm2 == 0x37c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x777c; op2val:0x5f7c; + valaddr_reg:x10; val_offset:1884*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1884*FLEN/8, x12, x4, x7) + +inst_968: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x37c and fs2 == 0 and fe2 == 0x17 and fm2 == 0x37c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x777c; op2val:0x5f7c; + valaddr_reg:x10; val_offset:1886*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1886*FLEN/8, x12, x4, x7) + +inst_969: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x37c and fs2 == 0 and fe2 == 0x17 and fm2 == 0x37c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x777c; op2val:0x5f7c; + valaddr_reg:x10; val_offset:1888*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1888*FLEN/8, x12, x4, x7) + +inst_970: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x291 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x291 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a91; op2val:0x6291; + valaddr_reg:x10; val_offset:1890*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1890*FLEN/8, x12, x4, x7) + +inst_971: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x291 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x291 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a91; op2val:0x6291; + valaddr_reg:x10; val_offset:1892*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1892*FLEN/8, x12, x4, x7) + +inst_972: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x291 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x291 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a91; op2val:0x6291; + valaddr_reg:x10; val_offset:1894*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1894*FLEN/8, x12, x4, x7) + +inst_973: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x291 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x291 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a91; op2val:0x6291; + valaddr_reg:x10; val_offset:1896*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1896*FLEN/8, x12, x4, x7) + +inst_974: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x291 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x291 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a91; op2val:0x6291; + valaddr_reg:x10; val_offset:1898*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1898*FLEN/8, x12, x4, x7) + +inst_975: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3b2 and fs2 == 0 and fe2 == 0x17 and fm2 == 0x3b2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x77b2; op2val:0x5fb2; + valaddr_reg:x10; val_offset:1900*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1900*FLEN/8, x12, x4, x7) + +inst_976: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3b2 and fs2 == 0 and fe2 == 0x17 and fm2 == 0x3b2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x77b2; op2val:0x5fb2; + valaddr_reg:x10; val_offset:1902*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1902*FLEN/8, x12, x4, x7) + +inst_977: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3b2 and fs2 == 0 and fe2 == 0x17 and fm2 == 0x3b2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x77b2; op2val:0x5fb2; + valaddr_reg:x10; val_offset:1904*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1904*FLEN/8, x12, x4, x7) + +inst_978: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3b2 and fs2 == 0 and fe2 == 0x17 and fm2 == 0x3b2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x77b2; op2val:0x5fb2; + valaddr_reg:x10; val_offset:1906*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1906*FLEN/8, x12, x4, x7) + +inst_979: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3b2 and fs2 == 0 and fe2 == 0x17 and fm2 == 0x3b2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x77b2; op2val:0x5fb2; + valaddr_reg:x10; val_offset:1908*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1908*FLEN/8, x12, x4, x7) + +inst_980: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1dd and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79dd; op2val:0x7bff; + valaddr_reg:x10; val_offset:1910*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1910*FLEN/8, x12, x4, x7) + +inst_981: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1dd and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79dd; op2val:0x7bff; + valaddr_reg:x10; val_offset:1912*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1912*FLEN/8, x12, x4, x7) + +inst_982: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1dd and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79dd; op2val:0x7bff; + valaddr_reg:x10; val_offset:1914*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1914*FLEN/8, x12, x4, x7) + +inst_983: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1dd and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79dd; op2val:0x7bff; + valaddr_reg:x10; val_offset:1916*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1916*FLEN/8, x12, x4, x7) + +inst_984: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1dd and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79dd; op2val:0x7bff; + valaddr_reg:x10; val_offset:1918*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1918*FLEN/8, x12, x4, x7) + +inst_985: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x379 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7779; op2val:0x7bff; + valaddr_reg:x10; val_offset:1920*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1920*FLEN/8, x12, x4, x7) + +inst_986: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x379 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7779; op2val:0x7bff; + valaddr_reg:x10; val_offset:1922*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1922*FLEN/8, x12, x4, x7) + +inst_987: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x379 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7779; op2val:0x7bff; + valaddr_reg:x10; val_offset:1924*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1924*FLEN/8, x12, x4, x7) + +inst_988: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x379 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7779; op2val:0x7bff; + valaddr_reg:x10; val_offset:1926*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1926*FLEN/8, x12, x4, x7) + +inst_989: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x379 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7779; op2val:0x7bff; + valaddr_reg:x10; val_offset:1928*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1928*FLEN/8, x12, x4, x7) + +inst_990: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x382 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7382; op2val:0x7bff; + valaddr_reg:x10; val_offset:1930*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1930*FLEN/8, x12, x4, x7) + +inst_991: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x382 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7382; op2val:0x7bff; + valaddr_reg:x10; val_offset:1932*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1932*FLEN/8, x12, x4, x7) + +inst_992: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x382 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7382; op2val:0x7bff; + valaddr_reg:x10; val_offset:1934*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1934*FLEN/8, x12, x4, x7) + +inst_993: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x382 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7382; op2val:0x7bff; + valaddr_reg:x10; val_offset:1936*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1936*FLEN/8, x12, x4, x7) + +inst_994: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x382 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7382; op2val:0x7bff; + valaddr_reg:x10; val_offset:1938*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1938*FLEN/8, x12, x4, x7) + +inst_995: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x166 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7966; op2val:0x7bff; + valaddr_reg:x10; val_offset:1940*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1940*FLEN/8, x12, x4, x7) + +inst_996: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x166 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7966; op2val:0x7bff; + valaddr_reg:x10; val_offset:1942*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1942*FLEN/8, x12, x4, x7) + +inst_997: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x166 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7966; op2val:0x7bff; + valaddr_reg:x10; val_offset:1944*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1944*FLEN/8, x12, x4, x7) + +inst_998: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x166 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7966; op2val:0x7bff; + valaddr_reg:x10; val_offset:1946*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1946*FLEN/8, x12, x4, x7) + +inst_999: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x166 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7966; op2val:0x7bff; + valaddr_reg:x10; val_offset:1948*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1948*FLEN/8, x12, x4, x7) + +inst_1000: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ad3; op2val:0x7bff; + valaddr_reg:x10; val_offset:1950*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1950*FLEN/8, x12, x4, x7) + +inst_1001: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ad3; op2val:0x7bff; + valaddr_reg:x10; val_offset:1952*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1952*FLEN/8, x12, x4, x7) + +inst_1002: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ad3; op2val:0x7bff; + valaddr_reg:x10; val_offset:1954*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1954*FLEN/8, x12, x4, x7) + +inst_1003: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ad3; op2val:0x7bff; + valaddr_reg:x10; val_offset:1956*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1956*FLEN/8, x12, x4, x7) + +inst_1004: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ad3; op2val:0x7bff; + valaddr_reg:x10; val_offset:1958*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1958*FLEN/8, x12, x4, x7) + +inst_1005: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x210 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7210; op2val:0x7bff; + valaddr_reg:x10; val_offset:1960*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1960*FLEN/8, x12, x4, x7) + +inst_1006: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x210 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7210; op2val:0x7bff; + valaddr_reg:x10; val_offset:1962*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1962*FLEN/8, x12, x4, x7) + +inst_1007: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x210 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7210; op2val:0x7bff; + valaddr_reg:x10; val_offset:1964*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1964*FLEN/8, x12, x4, x7) + +inst_1008: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x210 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7210; op2val:0x7bff; + valaddr_reg:x10; val_offset:1966*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1966*FLEN/8, x12, x4, x7) + +inst_1009: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x210 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7210; op2val:0x7bff; + valaddr_reg:x10; val_offset:1968*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1968*FLEN/8, x12, x4, x7) + +inst_1010: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1fc and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x71fc; op2val:0xfbff; + valaddr_reg:x10; val_offset:1970*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1970*FLEN/8, x12, x4, x7) + +inst_1011: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1fc and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x71fc; op2val:0xfbff; + valaddr_reg:x10; val_offset:1972*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1972*FLEN/8, x12, x4, x7) + +inst_1012: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1fc and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x71fc; op2val:0xfbff; + valaddr_reg:x10; val_offset:1974*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1974*FLEN/8, x12, x4, x7) + +inst_1013: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1fc and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x71fc; op2val:0xfbff; + valaddr_reg:x10; val_offset:1976*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1976*FLEN/8, x12, x4, x7) + +inst_1014: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1fc and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x71fc; op2val:0xfbff; + valaddr_reg:x10; val_offset:1978*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1978*FLEN/8, x12, x4, x7) + +inst_1015: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2dd and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7add; op2val:0xfbff; + valaddr_reg:x10; val_offset:1980*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1980*FLEN/8, x12, x4, x7) + +inst_1016: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2dd and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7add; op2val:0xfbff; + valaddr_reg:x10; val_offset:1982*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1982*FLEN/8, x12, x4, x7) + +inst_1017: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2dd and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7add; op2val:0xfbff; + valaddr_reg:x10; val_offset:1984*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1984*FLEN/8, x12, x4, x7) + +inst_1018: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2dd and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7add; op2val:0xfbff; + valaddr_reg:x10; val_offset:1986*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1986*FLEN/8, x12, x4, x7) + +inst_1019: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2dd and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7add; op2val:0xfbff; + valaddr_reg:x10; val_offset:1988*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1988*FLEN/8, x12, x4, x7) + +inst_1020: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x014 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7414; op2val:0xfbff; + valaddr_reg:x10; val_offset:1990*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 1990*FLEN/8, x12, x4, x7) + +inst_1021: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x014 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7414; op2val:0xfbff; + valaddr_reg:x10; val_offset:1992*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 1992*FLEN/8, x12, x4, x7) + +inst_1022: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x014 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7414; op2val:0xfbff; + valaddr_reg:x10; val_offset:1994*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 1994*FLEN/8, x12, x4, x7) + +inst_1023: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x014 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7414; op2val:0xfbff; + valaddr_reg:x10; val_offset:1996*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 1996*FLEN/8, x12, x4, x7) + +inst_1024: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x014 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7414; op2val:0xfbff; + valaddr_reg:x10; val_offset:1998*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 1998*FLEN/8, x12, x4, x7) + +inst_1025: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x103 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7503; op2val:0xfbff; + valaddr_reg:x10; val_offset:2000*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 2000*FLEN/8, x12, x4, x7) + +inst_1026: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x103 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7503; op2val:0xfbff; + valaddr_reg:x10; val_offset:2002*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 2002*FLEN/8, x12, x4, x7) + +inst_1027: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x103 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7503; op2val:0xfbff; + valaddr_reg:x10; val_offset:2004*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 2004*FLEN/8, x12, x4, x7) + +inst_1028: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x103 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7503; op2val:0xfbff; + valaddr_reg:x10; val_offset:2006*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 2006*FLEN/8, x12, x4, x7) + +inst_1029: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x103 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7503; op2val:0xfbff; + valaddr_reg:x10; val_offset:2008*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 2008*FLEN/8, x12, x4, x7) + +inst_1030: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79d4; op2val:0xfbff; + valaddr_reg:x10; val_offset:2010*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 2010*FLEN/8, x12, x4, x7) + +inst_1031: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79d4; op2val:0xfbff; + valaddr_reg:x10; val_offset:2012*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 2012*FLEN/8, x12, x4, x7) + +inst_1032: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79d4; op2val:0xfbff; + valaddr_reg:x10; val_offset:2014*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 2014*FLEN/8, x12, x4, x7) + +inst_1033: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79d4; op2val:0xfbff; + valaddr_reg:x10; val_offset:2016*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 2016*FLEN/8, x12, x4, x7) + +inst_1034: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79d4; op2val:0xfbff; + valaddr_reg:x10; val_offset:2018*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 2018*FLEN/8, x12, x4, x7) + +inst_1035: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ed and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ded; op2val:0xfbff; + valaddr_reg:x10; val_offset:2020*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 2020*FLEN/8, x12, x4, x7) + +inst_1036: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ed and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ded; op2val:0xfbff; + valaddr_reg:x10; val_offset:2022*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 2022*FLEN/8, x12, x4, x7) + +inst_1037: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ed and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ded; op2val:0xfbff; + valaddr_reg:x10; val_offset:2024*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 2024*FLEN/8, x12, x4, x7) + +inst_1038: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ed and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ded; op2val:0xfbff; + valaddr_reg:x10; val_offset:2026*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 2026*FLEN/8, x12, x4, x7) + +inst_1039: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ed and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ded; op2val:0xfbff; + valaddr_reg:x10; val_offset:2028*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 2028*FLEN/8, x12, x4, x7) + +inst_1040: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0aa and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74aa; op2val:0xfbff; + valaddr_reg:x10; val_offset:2030*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 2030*FLEN/8, x12, x4, x7) + +inst_1041: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0aa and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74aa; op2val:0xfbff; + valaddr_reg:x10; val_offset:2032*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 2032*FLEN/8, x12, x4, x7) + +inst_1042: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0aa and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74aa; op2val:0xfbff; + valaddr_reg:x10; val_offset:2034*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 2034*FLEN/8, x12, x4, x7) + +inst_1043: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0aa and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74aa; op2val:0xfbff; + valaddr_reg:x10; val_offset:2036*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 2036*FLEN/8, x12, x4, x7) + +inst_1044: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0aa and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74aa; op2val:0xfbff; + valaddr_reg:x10; val_offset:2038*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 2038*FLEN/8, x12, x4, x7) + +inst_1045: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78a3; op2val:0xfbff; + valaddr_reg:x10; val_offset:2040*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 2040*FLEN/8, x12, x4, x7) + +inst_1046: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78a3; op2val:0xfbff; + valaddr_reg:x10; val_offset:2042*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 2042*FLEN/8, x12, x4, x7) + +inst_1047: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78a3; op2val:0xfbff; + valaddr_reg:x10; val_offset:2044*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 2044*FLEN/8, x12, x4, x7) + +inst_1048: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78a3; op2val:0xfbff; + valaddr_reg:x10; val_offset:2046*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 2046*FLEN/8, x12, x4, x7) + +inst_1049: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78a3; op2val:0xfbff; + valaddr_reg:x10; val_offset:2048*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 2048*FLEN/8, x12, x4, x7) + +inst_1050: +// fs1 == 0 and fe1 == 0x17 and fm1 == 0x30f and fs2 == 1 and fe2 == 0x1c and fm2 == 0x30f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5f0f; op2val:0xf30f; + valaddr_reg:x10; val_offset:2050*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 2050*FLEN/8, x12, x4, x7) +RVTEST_SIGBASE(x4,signature_x4_8) + +inst_1051: +// fs1 == 0 and fe1 == 0x17 and fm1 == 0x30f and fs2 == 1 and fe2 == 0x1c and fm2 == 0x30f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5f0f; op2val:0xf30f; + valaddr_reg:x10; val_offset:2052*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 2052*FLEN/8, x12, x4, x7) + +inst_1052: +// fs1 == 0 and fe1 == 0x17 and fm1 == 0x30f and fs2 == 1 and fe2 == 0x1c and fm2 == 0x30f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5f0f; op2val:0xf30f; + valaddr_reg:x10; val_offset:2054*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 2054*FLEN/8, x12, x4, x7) + +inst_1053: +// fs1 == 0 and fe1 == 0x17 and fm1 == 0x30f and fs2 == 1 and fe2 == 0x1c and fm2 == 0x30f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5f0f; op2val:0xf30f; + valaddr_reg:x10; val_offset:2056*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 2056*FLEN/8, x12, x4, x7) + +inst_1054: +// fs1 == 0 and fe1 == 0x17 and fm1 == 0x30f and fs2 == 1 and fe2 == 0x1c and fm2 == 0x30f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5f0f; op2val:0xf30f; + valaddr_reg:x10; val_offset:2058*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 2058*FLEN/8, x12, x4, x7) + +inst_1055: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2f9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x76f9; op2val:0xfbff; + valaddr_reg:x10; val_offset:2060*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 2060*FLEN/8, x12, x4, x7) + +inst_1056: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2f9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x76f9; op2val:0xfbff; + valaddr_reg:x10; val_offset:2062*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 2062*FLEN/8, x12, x4, x7) + +inst_1057: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2f9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x76f9; op2val:0xfbff; + valaddr_reg:x10; val_offset:2064*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 2064*FLEN/8, x12, x4, x7) + +inst_1058: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2f9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x76f9; op2val:0xfbff; + valaddr_reg:x10; val_offset:2066*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 2066*FLEN/8, x12, x4, x7) + +inst_1059: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2f9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x76f9; op2val:0xfbff; + valaddr_reg:x10; val_offset:2068*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 2068*FLEN/8, x12, x4, x7) + +inst_1060: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2b8 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x72b8; op2val:0xfbff; + valaddr_reg:x10; val_offset:2070*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 2070*FLEN/8, x12, x4, x7) + +inst_1061: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2b8 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x72b8; op2val:0xfbff; + valaddr_reg:x10; val_offset:2072*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 2072*FLEN/8, x12, x4, x7) + +inst_1062: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2b8 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x72b8; op2val:0xfbff; + valaddr_reg:x10; val_offset:2074*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 2074*FLEN/8, x12, x4, x7) + +inst_1063: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2b8 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x72b8; op2val:0xfbff; + valaddr_reg:x10; val_offset:2076*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 2076*FLEN/8, x12, x4, x7) + +inst_1064: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2b8 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x72b8; op2val:0xfbff; + valaddr_reg:x10; val_offset:2078*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 2078*FLEN/8, x12, x4, x7) + +inst_1065: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba3; op2val:0xfbff; + valaddr_reg:x10; val_offset:2080*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 2080*FLEN/8, x12, x4, x7) + +inst_1066: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba3; op2val:0xfbff; + valaddr_reg:x10; val_offset:2082*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 2082*FLEN/8, x12, x4, x7) + +inst_1067: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba3; op2val:0xfbff; + valaddr_reg:x10; val_offset:2084*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 2084*FLEN/8, x12, x4, x7) + +inst_1068: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba3; op2val:0xfbff; + valaddr_reg:x10; val_offset:2086*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 2086*FLEN/8, x12, x4, x7) + +inst_1069: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba3; op2val:0xfbff; + valaddr_reg:x10; val_offset:2088*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 2088*FLEN/8, x12, x4, x7) + +inst_1070: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x05a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x785a; op2val:0xfbff; + valaddr_reg:x10; val_offset:2090*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 2090*FLEN/8, x12, x4, x7) + +inst_1071: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x05a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x785a; op2val:0xfbff; + valaddr_reg:x10; val_offset:2092*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 2092*FLEN/8, x12, x4, x7) + +inst_1072: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x05a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x785a; op2val:0xfbff; + valaddr_reg:x10; val_offset:2094*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 2094*FLEN/8, x12, x4, x7) + +inst_1073: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x05a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x785a; op2val:0xfbff; + valaddr_reg:x10; val_offset:2096*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 2096*FLEN/8, x12, x4, x7) + +inst_1074: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x05a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x785a; op2val:0xfbff; + valaddr_reg:x10; val_offset:2098*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 2098*FLEN/8, x12, x4, x7) + +inst_1075: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x064 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7464; op2val:0xfbff; + valaddr_reg:x10; val_offset:2100*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 2100*FLEN/8, x12, x4, x7) + +inst_1076: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x064 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7464; op2val:0xfbff; + valaddr_reg:x10; val_offset:2102*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 2102*FLEN/8, x12, x4, x7) + +inst_1077: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x064 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7464; op2val:0xfbff; + valaddr_reg:x10; val_offset:2104*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 2104*FLEN/8, x12, x4, x7) + +inst_1078: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x064 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7464; op2val:0xfbff; + valaddr_reg:x10; val_offset:2106*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 2106*FLEN/8, x12, x4, x7) + +inst_1079: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x064 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7464; op2val:0xfbff; + valaddr_reg:x10; val_offset:2108*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 2108*FLEN/8, x12, x4, x7) + +inst_1080: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x332 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f32; op2val:0x7bff; + valaddr_reg:x10; val_offset:2110*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 2110*FLEN/8, x12, x4, x7) + +inst_1081: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x332 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f32; op2val:0x7bff; + valaddr_reg:x10; val_offset:2112*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 2112*FLEN/8, x12, x4, x7) + +inst_1082: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x332 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f32; op2val:0x7bff; + valaddr_reg:x10; val_offset:2114*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 2114*FLEN/8, x12, x4, x7) + +inst_1083: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x332 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f32; op2val:0x7bff; + valaddr_reg:x10; val_offset:2116*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 2116*FLEN/8, x12, x4, x7) + +inst_1084: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x332 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f32; op2val:0x7bff; + valaddr_reg:x10; val_offset:2118*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 2118*FLEN/8, x12, x4, x7) + +inst_1085: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x344 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b44; op2val:0x7bff; + valaddr_reg:x10; val_offset:2120*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 2120*FLEN/8, x12, x4, x7) + +inst_1086: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x344 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b44; op2val:0x7bff; + valaddr_reg:x10; val_offset:2122*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 2122*FLEN/8, x12, x4, x7) + +inst_1087: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x344 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b44; op2val:0x7bff; + valaddr_reg:x10; val_offset:2124*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 2124*FLEN/8, x12, x4, x7) + +inst_1088: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x344 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b44; op2val:0x7bff; + valaddr_reg:x10; val_offset:2126*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 2126*FLEN/8, x12, x4, x7) + +inst_1089: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x344 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b44; op2val:0x7bff; + valaddr_reg:x10; val_offset:2128*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 2128*FLEN/8, x12, x4, x7) + +inst_1090: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x386 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b86; op2val:0x7bff; + valaddr_reg:x10; val_offset:2130*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 2130*FLEN/8, x12, x4, x7) + +inst_1091: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x386 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b86; op2val:0x7bff; + valaddr_reg:x10; val_offset:2132*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 2132*FLEN/8, x12, x4, x7) + +inst_1092: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x386 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b86; op2val:0x7bff; + valaddr_reg:x10; val_offset:2134*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 2134*FLEN/8, x12, x4, x7) + +inst_1093: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x386 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b86; op2val:0x7bff; + valaddr_reg:x10; val_offset:2136*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 2136*FLEN/8, x12, x4, x7) + +inst_1094: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x386 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b86; op2val:0x7bff; + valaddr_reg:x10; val_offset:2138*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 2138*FLEN/8, x12, x4, x7) + +inst_1095: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x22d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a2d; op2val:0x7bff; + valaddr_reg:x10; val_offset:2140*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 2140*FLEN/8, x12, x4, x7) + +inst_1096: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x22d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a2d; op2val:0x7bff; + valaddr_reg:x10; val_offset:2142*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 2142*FLEN/8, x12, x4, x7) + +inst_1097: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x22d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a2d; op2val:0x7bff; + valaddr_reg:x10; val_offset:2144*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 2144*FLEN/8, x12, x4, x7) + +inst_1098: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x22d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a2d; op2val:0x7bff; + valaddr_reg:x10; val_offset:2146*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 2146*FLEN/8, x12, x4, x7) + +inst_1099: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x22d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a2d; op2val:0x7bff; + valaddr_reg:x10; val_offset:2148*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 2148*FLEN/8, x12, x4, x7) + +inst_1100: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0b9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74b9; op2val:0x7bff; + valaddr_reg:x10; val_offset:2150*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 2150*FLEN/8, x12, x4, x7) + +inst_1101: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0b9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74b9; op2val:0x7bff; + valaddr_reg:x10; val_offset:2152*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 2152*FLEN/8, x12, x4, x7) + +inst_1102: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0b9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74b9; op2val:0x7bff; + valaddr_reg:x10; val_offset:2154*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 2154*FLEN/8, x12, x4, x7) + +inst_1103: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0b9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74b9; op2val:0x7bff; + valaddr_reg:x10; val_offset:2156*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 2156*FLEN/8, x12, x4, x7) + +inst_1104: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0b9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74b9; op2val:0x7bff; + valaddr_reg:x10; val_offset:2158*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 2158*FLEN/8, x12, x4, x7) + +inst_1105: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x13a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x793a; op2val:0x7bff; + valaddr_reg:x10; val_offset:2160*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 2160*FLEN/8, x12, x4, x7) + +inst_1106: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x13a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x793a; op2val:0x7bff; + valaddr_reg:x10; val_offset:2162*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 2162*FLEN/8, x12, x4, x7) + +inst_1107: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x13a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x793a; op2val:0x7bff; + valaddr_reg:x10; val_offset:2164*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 2164*FLEN/8, x12, x4, x7) + +inst_1108: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x13a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x793a; op2val:0x7bff; + valaddr_reg:x10; val_offset:2166*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 2166*FLEN/8, x12, x4, x7) + +inst_1109: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x13a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x793a; op2val:0x7bff; + valaddr_reg:x10; val_offset:2168*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 2168*FLEN/8, x12, x4, x7) + +inst_1110: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x03f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x743f; op2val:0x7bff; + valaddr_reg:x10; val_offset:2170*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 2170*FLEN/8, x12, x4, x7) + +inst_1111: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x03f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x743f; op2val:0x7bff; + valaddr_reg:x10; val_offset:2172*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 2172*FLEN/8, x12, x4, x7) + +inst_1112: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x03f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x743f; op2val:0x7bff; + valaddr_reg:x10; val_offset:2174*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 2174*FLEN/8, x12, x4, x7) + +inst_1113: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x03f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x743f; op2val:0x7bff; + valaddr_reg:x10; val_offset:2176*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x10, 2176*FLEN/8, x12, x4, x7) + +inst_1114: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x03f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x743f; op2val:0x7bff; + valaddr_reg:x10; val_offset:2178*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x10, 2178*FLEN/8, x12, x4, x7) + +inst_1115: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x739c; op2val:0x7bff; + valaddr_reg:x10; val_offset:2180*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 2180*FLEN/8, x12, x4, x7) + +inst_1116: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x739c; op2val:0x7bff; + valaddr_reg:x10; val_offset:2182*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x10, 2182*FLEN/8, x12, x4, x7) + +inst_1117: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x2bf and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x62bf; op2val:0x7bff; + valaddr_reg:x10; val_offset:2184*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x10, 2184*FLEN/8, x12, x4, x7) + +inst_1118: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7425; op2val:0x7bff; + valaddr_reg:x10; val_offset:2186*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x10, 2186*FLEN/8, x12, x4, x7) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(30186,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(30186,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(30186,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(30186,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(30186,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(30976,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(30976,32,FLEN) +NAN_BOXED(31743,32,FLEN) +test_dataset_1: +NAN_BOXED(30976,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(30976,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(30976,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(25279,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(25279,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(25279,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(25279,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(25279,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(29733,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(29733,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(29733,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(29733,32,FLEN) +NAN_BOXED(31743,32,FLEN) +test_dataset_2: +NAN_BOXED(31734,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31734,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31734,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31734,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31734,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31408,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31408,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31408,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31408,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31408,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31004,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31004,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31004,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31004,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31004,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30995,16,FLEN) +NAN_BOXED(64511,16,FLEN) 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+signature_x4_0: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x4_1: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x4_2: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x4_3: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x4_4: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x4_5: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x4_6: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x4_7: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x4_8: + .fill 136*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fdiv_b4-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fdiv_b4-01.S new file mode 100644 index 000000000..9cadd829e --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fdiv_b4-01.S @@ -0,0 +1,1554 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 05:22:24 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fdiv.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fdiv.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fdiv_b4 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fdiv_b4) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x13,test_dataset_0) +RVTEST_SIGBASE(x6,signature_x6_1) + +inst_0: +// rs1 == rd != rs2, rs1==x3, rs2==x19, rd==x3,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x0c and fm2 == 0x39d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x3; op2:x19; dest:x3; op1val:0x739c; op2val:0x339d; + valaddr_reg:x13; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x11 +*/ +TEST_FPRR_OP(fdiv.h, x3, x3, x19, dyn, 0, 0, x13, 0*FLEN/8, x17, x6, x11) + +inst_1: +// rs1 == rs2 != rd, rs1==x26, rs2==x26, rd==x28,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x0c and fm2 == 0x39d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x26; op2:x26; dest:x28; op1val:0x739c; op2val:0x739c; + valaddr_reg:x13; val_offset:2*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x11 +*/ +TEST_FPRR_OP(fdiv.h, x28, x26, x26, dyn, 32, 0, x13, 2*FLEN/8, x17, x6, x11) + +inst_2: +// rs1 == rs2 == rd, rs1==x25, rs2==x25, rd==x25,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x0c and fm2 == 0x39d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x25; op2:x25; dest:x25; op1val:0x739c; op2val:0x739c; + valaddr_reg:x13; val_offset:4*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x11 +*/ +TEST_FPRR_OP(fdiv.h, x25, x25, x25, dyn, 64, 0, x13, 4*FLEN/8, x17, x6, x11) + +inst_3: +// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==x2, rs2==x10, rd==x29,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x0c and fm2 == 0x39d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x2; op2:x10; dest:x29; op1val:0x739c; op2val:0x339d; + valaddr_reg:x13; val_offset:6*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x11 +*/ +TEST_FPRR_OP(fdiv.h, x29, x2, x10, dyn, 96, 0, x13, 6*FLEN/8, x17, x6, x11) + +inst_4: +// rs2 == rd != rs1, rs1==x24, rs2==x1, rd==x1,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x0c and fm2 == 0x39d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x24; op2:x1; dest:x1; op1val:0x739c; op2val:0x339d; + valaddr_reg:x13; val_offset:8*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x11 +*/ +TEST_FPRR_OP(fdiv.h, x1, x24, x1, dyn, 128, 0, x13, 8*FLEN/8, x17, x6, x11) + +inst_5: +// rs1==x19, rs2==x16, rd==x22,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ea and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1eb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x19; op2:x16; dest:x22; op1val:0x75ea; op2val:0xb5eb; + valaddr_reg:x13; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x11 +*/ +TEST_FPRR_OP(fdiv.h, x22, x19, x16, dyn, 0, 0, x13, 10*FLEN/8, x17, x6, x11) + +inst_6: +// rs1==x15, rs2==x21, rd==x8,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ea and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1eb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x15; op2:x21; dest:x8; op1val:0x75ea; op2val:0xb5eb; + valaddr_reg:x13; val_offset:12*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x11 +*/ +TEST_FPRR_OP(fdiv.h, x8, x15, x21, dyn, 32, 0, x13, 12*FLEN/8, x17, x6, x11) + +inst_7: +// rs1==x12, rs2==x20, rd==x16,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ea and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1eb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x12; op2:x20; dest:x16; op1val:0x75ea; op2val:0xb5eb; + valaddr_reg:x13; val_offset:14*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x11 +*/ +TEST_FPRR_OP(fdiv.h, x16, x12, x20, dyn, 64, 0, x13, 14*FLEN/8, x17, x6, x11) + +inst_8: +// rs1==x9, rs2==x2, rd==x26,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ea and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1eb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x9; op2:x2; dest:x26; op1val:0x75ea; op2val:0xb5eb; + valaddr_reg:x13; val_offset:16*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x11 +*/ +TEST_FPRR_OP(fdiv.h, x26, x9, x2, dyn, 96, 0, x13, 16*FLEN/8, x17, x6, x11) + +inst_9: +// rs1==x1, rs2==x31, rd==x10,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ea and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1eb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x1; op2:x31; dest:x10; op1val:0x75ea; op2val:0xb5eb; + valaddr_reg:x13; val_offset:18*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x11 +*/ +TEST_FPRR_OP(fdiv.h, x10, x1, x31, dyn, 128, 0, x13, 18*FLEN/8, x17, x6, x11) + +inst_10: +// rs1==x7, rs2==x14, rd==x5,fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x101 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x7; op2:x14; dest:x5; op1val:0x7900; op2val:0x3901; + valaddr_reg:x13; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x11 +*/ +TEST_FPRR_OP(fdiv.h, x5, x7, x14, dyn, 0, 0, x13, 20*FLEN/8, x17, x6, x11) + +inst_11: +// rs1==x4, rs2==x22, rd==x21,fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x101 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x4; op2:x22; dest:x21; op1val:0x7900; op2val:0x3901; + valaddr_reg:x13; val_offset:22*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x11 +*/ +TEST_FPRR_OP(fdiv.h, x21, x4, x22, dyn, 32, 0, x13, 22*FLEN/8, x17, x6, x11) +RVTEST_VALBASEUPD(x4,test_dataset_1) + +inst_12: +// rs1==x18, rs2==x7, rd==x12,fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x101 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x18; op2:x7; dest:x12; op1val:0x7900; op2val:0x3901; + valaddr_reg:x4; val_offset:0*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x11 +*/ +TEST_FPRR_OP(fdiv.h, x12, x18, x7, dyn, 64, 0, x4, 0*FLEN/8, x8, x6, x11) + +inst_13: +// rs1==x17, rs2==x0, rd==x19,fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x101 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x17; op2:x0; dest:x19; op1val:0x7900; op2val:0x0; + valaddr_reg:x4; val_offset:2*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x11 +*/ +TEST_FPRR_OP(fdiv.h, x19, x17, x0, dyn, 96, 0, x4, 2*FLEN/8, x8, x6, x11) + +inst_14: +// rs1==x22, rs2==x9, rd==x30,fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x101 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x22; op2:x9; dest:x30; op1val:0x7900; op2val:0x3901; + valaddr_reg:x4; val_offset:4*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x30, x22, x9, dyn, 128, 0, x4, 4*FLEN/8, x8, x6, x3) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_15: +// rs1==x20, rs2==x24, rd==x31,fs1 == 0 and fe1 == 0x18 and fm1 == 0x2bf and fs2 == 1 and fe2 == 0x08 and fm2 == 0x2bf and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x20; op2:x24; dest:x31; op1val:0x62bf; op2val:0xa2bf; + valaddr_reg:x4; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x31, x20, x24, dyn, 0, 0, x4, 6*FLEN/8, x8, x1, x3) + +inst_16: +// rs1==x28, rs2==x5, rd==x27,fs1 == 0 and fe1 == 0x18 and fm1 == 0x2bf and fs2 == 1 and fe2 == 0x08 and fm2 == 0x2bf and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x28; op2:x5; dest:x27; op1val:0x62bf; op2val:0xa2bf; + valaddr_reg:x4; val_offset:8*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x27, x28, x5, dyn, 32, 0, x4, 8*FLEN/8, x8, x1, x3) + +inst_17: +// rs1==x6, rs2==x27, rd==x2,fs1 == 0 and fe1 == 0x18 and fm1 == 0x2bf and fs2 == 1 and fe2 == 0x08 and fm2 == 0x2bf and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x6; op2:x27; dest:x2; op1val:0x62bf; op2val:0xa2bf; + valaddr_reg:x4; val_offset:10*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x2, x6, x27, dyn, 64, 0, x4, 10*FLEN/8, x8, x1, x3) + +inst_18: +// rs1==x27, rs2==x28, rd==x20,fs1 == 0 and fe1 == 0x18 and fm1 == 0x2bf and fs2 == 1 and fe2 == 0x08 and fm2 == 0x2bf and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x27; op2:x28; dest:x20; op1val:0x62bf; op2val:0xa2bf; + valaddr_reg:x4; val_offset:12*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x20, x27, x28, dyn, 96, 0, x4, 12*FLEN/8, x8, x1, x3) + +inst_19: +// rs1==x21, rs2==x12, rd==x0,fs1 == 0 and fe1 == 0x18 and fm1 == 0x2bf and fs2 == 1 and fe2 == 0x08 and fm2 == 0x2bf and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x21; op2:x12; dest:x0; op1val:0x62bf; op2val:0xa2bf; + valaddr_reg:x4; val_offset:14*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x0, x21, x12, dyn, 128, 0, x4, 14*FLEN/8, x8, x1, x3) + +inst_20: +// rs1==x5, rs2==x18, rd==x6,fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x026 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x5; op2:x18; dest:x6; op1val:0x7425; op2val:0x3426; + valaddr_reg:x4; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x6, x5, x18, dyn, 0, 0, x4, 16*FLEN/8, x8, x1, x3) + +inst_21: +// rs1==x13, rs2==x15, rd==x9,fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x026 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x13; op2:x15; dest:x9; op1val:0x7425; op2val:0x3426; + valaddr_reg:x4; val_offset:18*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x9, x13, x15, dyn, 32, 0, x4, 18*FLEN/8, x8, x1, x3) + +inst_22: +// rs1==x10, rs2==x6, rd==x17,fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x026 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x10; op2:x6; dest:x17; op1val:0x7425; op2val:0x3426; + valaddr_reg:x4; val_offset:20*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x17, x10, x6, dyn, 64, 0, x4, 20*FLEN/8, x8, x1, x3) + +inst_23: +// rs1==x14, rs2==x23, rd==x13,fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x026 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x14; op2:x23; dest:x13; op1val:0x7425; op2val:0x3426; + valaddr_reg:x4; val_offset:22*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x13, x14, x23, dyn, 96, 0, x4, 22*FLEN/8, x8, x1, x3) +RVTEST_VALBASEUPD(x5,test_dataset_2) + +inst_24: +// rs1==x16, rs2==x13, rd==x18,fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x026 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x16; op2:x13; dest:x18; op1val:0x7425; op2val:0x3426; + valaddr_reg:x5; val_offset:0*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x18, x16, x13, dyn, 128, 0, x5, 0*FLEN/8, x6, x1, x3) + +inst_25: +// rs1==x29, rs2==x17, rd==x23,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f6 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3f7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x29; op2:x17; dest:x23; op1val:0x7bf6; op2val:0xbbf7; + valaddr_reg:x5; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x23, x29, x17, dyn, 0, 0, x5, 2*FLEN/8, x6, x1, x3) + +inst_26: +// rs1==x8, rs2==x29, rd==x15,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f6 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3f7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x8; op2:x29; dest:x15; op1val:0x7bf6; op2val:0xbbf7; + valaddr_reg:x5; val_offset:4*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x15, x8, x29, dyn, 32, 0, x5, 4*FLEN/8, x6, x1, x3) + +inst_27: +// rs1==x30, rs2==x4, rd==x7,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f6 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3f7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x4; dest:x7; op1val:0x7bf6; op2val:0xbbf7; + valaddr_reg:x5; val_offset:6*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x7, x30, x4, dyn, 64, 0, x5, 6*FLEN/8, x6, x1, x3) + +inst_28: +// rs1==x11, rs2==x3, rd==x24,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f6 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3f7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x11; op2:x3; dest:x24; op1val:0x7bf6; op2val:0xbbf7; + valaddr_reg:x5; val_offset:8*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x24, x11, x3, dyn, 96, 0, x5, 8*FLEN/8, x6, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_29: +// rs1==x0, rs2==x30, rd==x14,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f6 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3f7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x0; op2:x30; dest:x14; op1val:0x0; op2val:0xbbf7; + valaddr_reg:x5; val_offset:10*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x14, x0, x30, dyn, 128, 0, x5, 10*FLEN/8, x6, x1, x2) + +inst_30: +// rs1==x31, rs2==x11, rd==x4,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2b1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x31; op2:x11; dest:x4; op1val:0x7ab0; op2val:0x3ab1; + valaddr_reg:x5; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x4, x31, x11, dyn, 0, 0, x5, 12*FLEN/8, x6, x1, x2) + +inst_31: +// rs1==x23, rs2==x8, rd==x11,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2b1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x23; op2:x8; dest:x11; op1val:0x7ab0; op2val:0x3ab1; + valaddr_reg:x5; val_offset:14*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x11, x23, x8, dyn, 32, 0, x5, 14*FLEN/8, x6, x1, x2) + +inst_32: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2b1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab0; op2val:0x3ab1; + valaddr_reg:x5; val_offset:16*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x5, 16*FLEN/8, x6, x1, x2) + +inst_33: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2b1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab0; op2val:0x3ab1; + valaddr_reg:x5; val_offset:18*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x5, 18*FLEN/8, x6, x1, x2) + +inst_34: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2b1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab0; op2val:0x3ab1; + valaddr_reg:x5; val_offset:20*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x5, 20*FLEN/8, x6, x1, x2) + +inst_35: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x11c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x11c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x791c; op2val:0xb91c; + valaddr_reg:x5; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x5, 22*FLEN/8, x6, x1, x2) + +inst_36: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x11c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x11c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x791c; op2val:0xb91c; + valaddr_reg:x5; val_offset:24*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x5, 24*FLEN/8, x6, x1, x2) + +inst_37: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x11c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x11c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x791c; op2val:0xb91c; + valaddr_reg:x5; val_offset:26*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x5, 26*FLEN/8, x6, x1, x2) + +inst_38: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x11c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x11c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x791c; op2val:0xb91c; + valaddr_reg:x5; val_offset:28*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x5, 28*FLEN/8, x6, x1, x2) + +inst_39: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x11c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x11c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x791c; op2val:0xb91c; + valaddr_reg:x5; val_offset:30*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x5, 30*FLEN/8, x6, x1, x2) + +inst_40: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x114 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0x3914; + valaddr_reg:x5; val_offset:32*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x5, 32*FLEN/8, x6, x1, x2) + +inst_41: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x114 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0x3914; + valaddr_reg:x5; val_offset:34*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x5, 34*FLEN/8, x6, x1, x2) + +inst_42: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x114 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0x3914; + valaddr_reg:x5; val_offset:36*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x5, 36*FLEN/8, x6, x1, x2) + +inst_43: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x114 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0x3914; + valaddr_reg:x5; val_offset:38*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x5, 38*FLEN/8, x6, x1, x2) + +inst_44: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x114 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0x3914; + valaddr_reg:x5; val_offset:40*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x5, 40*FLEN/8, x6, x1, x2) + +inst_45: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x02f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x782e; op2val:0xb82f; + valaddr_reg:x5; val_offset:42*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x5, 42*FLEN/8, x6, x1, x2) + +inst_46: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x02f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x782e; op2val:0xb82f; + valaddr_reg:x5; val_offset:44*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x5, 44*FLEN/8, x6, x1, x2) + +inst_47: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x02f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x782e; op2val:0xb82f; + valaddr_reg:x5; val_offset:46*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x5, 46*FLEN/8, x6, x1, x2) + +inst_48: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x02f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x782e; op2val:0xb82f; + valaddr_reg:x5; val_offset:48*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x5, 48*FLEN/8, x6, x1, x2) + +inst_49: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x02f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x782e; op2val:0xb82f; + valaddr_reg:x5; val_offset:50*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x5, 50*FLEN/8, x6, x1, x2) + +inst_50: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x15f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x795e; op2val:0x395f; + valaddr_reg:x5; val_offset:52*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x5, 52*FLEN/8, x6, x1, x2) + +inst_51: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x15f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x795e; op2val:0x395f; + valaddr_reg:x5; val_offset:54*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x5, 54*FLEN/8, x6, x1, x2) + +inst_52: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x15f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x795e; op2val:0x395f; + valaddr_reg:x5; val_offset:56*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x5, 56*FLEN/8, x6, x1, x2) + +inst_53: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x15f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x795e; op2val:0x395f; + valaddr_reg:x5; val_offset:58*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x5, 58*FLEN/8, x6, x1, x2) + +inst_54: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x15f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x795e; op2val:0x395f; + valaddr_reg:x5; val_offset:60*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x5, 60*FLEN/8, x6, x1, x2) + +inst_55: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x210 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x210 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a10; op2val:0xba10; + valaddr_reg:x5; val_offset:62*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x5, 62*FLEN/8, x6, x1, x2) + +inst_56: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x210 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x210 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a10; op2val:0xba10; + valaddr_reg:x5; val_offset:64*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x5, 64*FLEN/8, x6, x1, x2) + +inst_57: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x210 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x210 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a10; op2val:0xba10; + valaddr_reg:x5; val_offset:66*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x5, 66*FLEN/8, x6, x1, x2) + +inst_58: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x210 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x210 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a10; op2val:0xba10; + valaddr_reg:x5; val_offset:68*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x5, 68*FLEN/8, x6, x1, x2) + +inst_59: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x210 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x210 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a10; op2val:0xba10; + valaddr_reg:x5; val_offset:70*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x5, 70*FLEN/8, x6, x1, x2) + +inst_60: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d1 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0d2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74d1; op2val:0x34d2; + valaddr_reg:x5; val_offset:72*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x5, 72*FLEN/8, x6, x1, x2) + +inst_61: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d1 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0d2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74d1; op2val:0x34d2; + valaddr_reg:x5; val_offset:74*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x5, 74*FLEN/8, x6, x1, x2) + +inst_62: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d1 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0d2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74d1; op2val:0x34d2; + valaddr_reg:x5; val_offset:76*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x5, 76*FLEN/8, x6, x1, x2) + +inst_63: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d1 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0d2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74d1; op2val:0x34d2; + valaddr_reg:x5; val_offset:78*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x5, 78*FLEN/8, x6, x1, x2) + +inst_64: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d1 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0d2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74d1; op2val:0x34d2; + valaddr_reg:x5; val_offset:80*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x5, 80*FLEN/8, x6, x1, x2) + +inst_65: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2eb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2ec and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aeb; op2val:0xbaec; + valaddr_reg:x5; val_offset:82*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x5, 82*FLEN/8, x6, x1, x2) + +inst_66: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2eb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2ec and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aeb; op2val:0xbaec; + valaddr_reg:x5; val_offset:84*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x5, 84*FLEN/8, x6, x1, x2) + +inst_67: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2eb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2ec and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aeb; op2val:0xbaec; + valaddr_reg:x5; val_offset:86*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x5, 86*FLEN/8, x6, x1, x2) + +inst_68: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2eb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2ec and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aeb; op2val:0xbaec; + valaddr_reg:x5; val_offset:88*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x5, 88*FLEN/8, x6, x1, x2) + +inst_69: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2eb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2ec and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aeb; op2val:0xbaec; + valaddr_reg:x5; val_offset:90*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x5, 90*FLEN/8, x6, x1, x2) + +inst_70: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1bf and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79bf; op2val:0x45c0; + valaddr_reg:x5; val_offset:92*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x5, 92*FLEN/8, x6, x1, x2) + +inst_71: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1bf and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1c0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79bf; op2val:0x45c0; + valaddr_reg:x5; val_offset:94*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x5, 94*FLEN/8, x6, x1, x2) + +inst_72: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1bf and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1c0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79bf; op2val:0x45c0; + valaddr_reg:x5; val_offset:96*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x5, 96*FLEN/8, x6, x1, x2) + +inst_73: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1bf and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1c0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79bf; op2val:0x45c0; + valaddr_reg:x5; val_offset:98*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x5, 98*FLEN/8, x6, x1, x2) + +inst_74: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1bf and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1c0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79bf; op2val:0x45c0; + valaddr_reg:x5; val_offset:100*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x5, 100*FLEN/8, x6, x1, x2) + +inst_75: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b5 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1b6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b5; op2val:0xc5b6; + valaddr_reg:x5; val_offset:102*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x5, 102*FLEN/8, x6, x1, x2) + +inst_76: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b5 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1b6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b5; op2val:0xc5b6; + valaddr_reg:x5; val_offset:104*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x5, 104*FLEN/8, x6, x1, x2) + +inst_77: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b5 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1b6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b5; op2val:0xc5b6; + valaddr_reg:x5; val_offset:106*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x5, 106*FLEN/8, x6, x1, x2) + +inst_78: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b5 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1b6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b5; op2val:0xc5b6; + valaddr_reg:x5; val_offset:108*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x5, 108*FLEN/8, x6, x1, x2) + +inst_79: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b5 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1b6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b5; op2val:0xc5b6; + valaddr_reg:x5; val_offset:110*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x5, 110*FLEN/8, x6, x1, x2) + +inst_80: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x251 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x251 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7651; op2val:0x3e51; + valaddr_reg:x5; val_offset:112*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x5, 112*FLEN/8, x6, x1, x2) + +inst_81: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x251 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x251 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7651; op2val:0x3e51; + valaddr_reg:x5; val_offset:114*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x5, 114*FLEN/8, x6, x1, x2) + +inst_82: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x251 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x251 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7651; op2val:0x3e51; + valaddr_reg:x5; val_offset:116*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x5, 116*FLEN/8, x6, x1, x2) + +inst_83: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x251 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x251 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7651; op2val:0x3e51; + valaddr_reg:x5; val_offset:118*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x5, 118*FLEN/8, x6, x1, x2) + +inst_84: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x251 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x251 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7651; op2val:0x3e51; + valaddr_reg:x5; val_offset:120*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x5, 120*FLEN/8, x6, x1, x2) + +inst_85: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x31d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x771c; op2val:0xbf1d; + valaddr_reg:x5; val_offset:122*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x5, 122*FLEN/8, x6, x1, x2) + +inst_86: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x31d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x771c; op2val:0xbf1d; + valaddr_reg:x5; val_offset:124*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x5, 124*FLEN/8, x6, x1, x2) + +inst_87: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x31d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x771c; op2val:0xbf1d; + valaddr_reg:x5; val_offset:126*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x5, 126*FLEN/8, x6, x1, x2) + +inst_88: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x31d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x771c; op2val:0xbf1d; + valaddr_reg:x5; val_offset:128*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x5, 128*FLEN/8, x6, x1, x2) + +inst_89: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x31d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x771c; op2val:0xbf1d; + valaddr_reg:x5; val_offset:130*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x5, 130*FLEN/8, x6, x1, x2) + +inst_90: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x307 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x307 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b07; op2val:0x3f07; + valaddr_reg:x5; val_offset:132*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x5, 132*FLEN/8, x6, x1, x2) + +inst_91: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x307 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x307 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b07; op2val:0x3f07; + valaddr_reg:x5; val_offset:134*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x5, 134*FLEN/8, x6, x1, x2) + +inst_92: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x307 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x307 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b07; op2val:0x3f07; + valaddr_reg:x5; val_offset:136*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x5, 136*FLEN/8, x6, x1, x2) + +inst_93: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x307 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x307 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b07; op2val:0x3f07; + valaddr_reg:x5; val_offset:138*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x5, 138*FLEN/8, x6, x1, x2) + +inst_94: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x307 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x307 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b07; op2val:0x3f07; + valaddr_reg:x5; val_offset:140*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x5, 140*FLEN/8, x6, x1, x2) + +inst_95: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x059 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x059 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7059; op2val:0xb459; + valaddr_reg:x5; val_offset:142*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x5, 142*FLEN/8, x6, x1, x2) + +inst_96: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x059 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x059 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7059; op2val:0xb459; + valaddr_reg:x5; val_offset:144*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x5, 144*FLEN/8, x6, x1, x2) + +inst_97: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x059 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x059 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7059; op2val:0xb459; + valaddr_reg:x5; val_offset:146*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x5, 146*FLEN/8, x6, x1, x2) + +inst_98: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x059 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x059 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7059; op2val:0xb459; + valaddr_reg:x5; val_offset:148*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x5, 148*FLEN/8, x6, x1, x2) + +inst_99: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x059 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x059 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7059; op2val:0xb459; + valaddr_reg:x5; val_offset:150*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x5, 150*FLEN/8, x6, x1, x2) + +inst_100: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3b9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb8; op2val:0x3bb9; + valaddr_reg:x5; val_offset:152*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x5, 152*FLEN/8, x6, x1, x2) + +inst_101: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3b9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb8; op2val:0x3bb9; + valaddr_reg:x5; val_offset:154*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x5, 154*FLEN/8, x6, x1, x2) + +inst_102: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3b9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb8; op2val:0x3bb9; + valaddr_reg:x5; val_offset:156*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x5, 156*FLEN/8, x6, x1, x2) + +inst_103: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3b9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb8; op2val:0x3bb9; + valaddr_reg:x5; val_offset:158*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x5, 158*FLEN/8, x6, x1, x2) + +inst_104: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3b9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb8; op2val:0x3bb9; + valaddr_reg:x5; val_offset:160*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x5, 160*FLEN/8, x6, x1, x2) + +inst_105: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x102 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x103 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7902; op2val:0xb903; + valaddr_reg:x5; val_offset:162*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x5, 162*FLEN/8, x6, x1, x2) + +inst_106: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x102 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x103 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7902; op2val:0xb903; + valaddr_reg:x5; val_offset:164*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x5, 164*FLEN/8, x6, x1, x2) + +inst_107: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x102 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x103 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7902; op2val:0xb903; + valaddr_reg:x5; val_offset:166*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x5, 166*FLEN/8, x6, x1, x2) + +inst_108: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x102 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x103 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7902; op2val:0xb903; + valaddr_reg:x5; val_offset:168*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x5, 168*FLEN/8, x6, x1, x2) + +inst_109: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x102 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x103 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7902; op2val:0xb903; + valaddr_reg:x5; val_offset:170*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x5, 170*FLEN/8, x6, x1, x2) + +inst_110: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00e and fs2 == 0 and fe2 == 0x0d and fm2 == 0x00e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x780e; op2val:0x340e; + valaddr_reg:x5; val_offset:172*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x5, 172*FLEN/8, x6, x1, x2) + +inst_111: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00e and fs2 == 0 and fe2 == 0x0d and fm2 == 0x00e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x780e; op2val:0x340e; + valaddr_reg:x5; val_offset:174*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x5, 174*FLEN/8, x6, x1, x2) + +inst_112: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00e and fs2 == 0 and fe2 == 0x0d and fm2 == 0x00e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x780e; op2val:0x340e; + valaddr_reg:x5; val_offset:176*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x5, 176*FLEN/8, x6, x1, x2) + +inst_113: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00e and fs2 == 0 and fe2 == 0x0d and fm2 == 0x00e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x780e; op2val:0x340e; + valaddr_reg:x5; val_offset:178*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x5, 178*FLEN/8, x6, x1, x2) + +inst_114: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00e and fs2 == 0 and fe2 == 0x0d and fm2 == 0x00e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x780e; op2val:0x340e; + valaddr_reg:x5; val_offset:180*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x5, 180*FLEN/8, x6, x1, x2) + +inst_115: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x19c and fs2 == 1 and fe2 == 0x0c and fm2 == 0x19d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x759c; op2val:0xb19d; + valaddr_reg:x5; val_offset:182*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x5, 182*FLEN/8, x6, x1, x2) + +inst_116: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x19c and fs2 == 1 and fe2 == 0x0c and fm2 == 0x19d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x759c; op2val:0xb19d; + valaddr_reg:x5; val_offset:184*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x5, 184*FLEN/8, x6, x1, x2) + +inst_117: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x19c and fs2 == 1 and fe2 == 0x0c and fm2 == 0x19d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x759c; op2val:0xb19d; + valaddr_reg:x5; val_offset:186*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x5, 186*FLEN/8, x6, x1, x2) + +inst_118: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x19c and fs2 == 1 and fe2 == 0x0c and fm2 == 0x19d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x759c; op2val:0xb19d; + valaddr_reg:x5; val_offset:188*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x5, 188*FLEN/8, x6, x1, x2) + +inst_119: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x19c and fs2 == 1 and fe2 == 0x0c and fm2 == 0x19d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x759c; op2val:0xb19d; + valaddr_reg:x5; val_offset:190*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x5, 190*FLEN/8, x6, x1, x2) + +inst_120: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ab and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0ac and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78ab; op2val:0x30ac; + valaddr_reg:x5; val_offset:192*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x5, 192*FLEN/8, x6, x1, x2) + +inst_121: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ab and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0ac and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78ab; op2val:0x30ac; + valaddr_reg:x5; val_offset:194*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x5, 194*FLEN/8, x6, x1, x2) + +inst_122: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ab and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0ac and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78ab; op2val:0x30ac; + valaddr_reg:x5; val_offset:196*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x5, 196*FLEN/8, x6, x1, x2) + +inst_123: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ab and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0ac and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78ab; op2val:0x30ac; + valaddr_reg:x5; val_offset:198*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x5, 198*FLEN/8, x6, x1, x2) + +inst_124: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ab and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0ac and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78ab; op2val:0x30ac; + valaddr_reg:x5; val_offset:200*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x5, 200*FLEN/8, x6, x1, x2) + +inst_125: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x174 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x174 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7974; op2val:0xb174; + valaddr_reg:x5; val_offset:202*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x5, 202*FLEN/8, x6, x1, x2) + +inst_126: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x174 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x174 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7974; op2val:0xb174; + valaddr_reg:x5; val_offset:204*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x5, 204*FLEN/8, x6, x1, x2) + +inst_127: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x174 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x174 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7974; op2val:0xb174; + valaddr_reg:x5; val_offset:206*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x5, 206*FLEN/8, x6, x1, x2) + +inst_128: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x174 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x174 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7974; op2val:0xb174; + valaddr_reg:x5; val_offset:208*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x5, 208*FLEN/8, x6, x1, x2) + +inst_129: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x174 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x174 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7974; op2val:0xb174; + valaddr_reg:x5; val_offset:210*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x5, 210*FLEN/8, x6, x1, x2) + +inst_130: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d9 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2d9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ad9; op2val:0x2ed9; + valaddr_reg:x5; val_offset:212*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x5, 212*FLEN/8, x6, x1, x2) + +inst_131: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d9 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2d9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ad9; op2val:0x2ed9; + valaddr_reg:x5; val_offset:214*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x5, 214*FLEN/8, x6, x1, x2) + +inst_132: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d9 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2d9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ad9; op2val:0x2ed9; + valaddr_reg:x5; val_offset:216*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x5, 216*FLEN/8, x6, x1, x2) + +inst_133: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d9 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2d9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ad9; op2val:0x2ed9; + valaddr_reg:x5; val_offset:218*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x5, 218*FLEN/8, x6, x1, x2) + +inst_134: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d9 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2d9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ad9; op2val:0x2ed9; + valaddr_reg:x5; val_offset:220*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x5, 220*FLEN/8, x6, x1, x2) + +inst_135: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15e and fs2 == 1 and fe2 == 0x0b and fm2 == 0x15e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x795e; op2val:0xad5e; + valaddr_reg:x5; val_offset:222*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x5, 222*FLEN/8, x6, x1, x2) + +inst_136: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15e and fs2 == 1 and fe2 == 0x0b and fm2 == 0x15e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x795e; op2val:0xad5e; + valaddr_reg:x5; val_offset:224*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x5, 224*FLEN/8, x6, x1, x2) + +inst_137: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15e and fs2 == 1 and fe2 == 0x0b and fm2 == 0x15e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x795e; op2val:0xad5e; + valaddr_reg:x5; val_offset:226*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x5, 226*FLEN/8, x6, x1, x2) + +inst_138: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15e and fs2 == 1 and fe2 == 0x0b and fm2 == 0x15e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x795e; op2val:0xad5e; + valaddr_reg:x5; val_offset:228*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x5, 228*FLEN/8, x6, x1, x2) + +inst_139: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15e and fs2 == 1 and fe2 == 0x0b and fm2 == 0x15e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x795e; op2val:0xad5e; + valaddr_reg:x5; val_offset:230*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x5, 230*FLEN/8, x6, x1, x2) + +inst_140: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x0c and fm2 == 0x39d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x739c; op2val:0x339d; + valaddr_reg:x5; val_offset:232*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x5, 232*FLEN/8, x6, x1, x2) + +inst_141: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x0c and fm2 == 0x39d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x739c; op2val:0x339d; + valaddr_reg:x5; val_offset:234*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x5, 234*FLEN/8, x6, x1, x2) + +inst_142: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x101 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7900; op2val:0x3901; + valaddr_reg:x5; val_offset:236*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x5, 236*FLEN/8, x6, x1, x2) + +inst_143: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x2bf and fs2 == 1 and fe2 == 0x08 and fm2 == 0x2bf and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x62bf; op2val:0xa2bf; + valaddr_reg:x5; val_offset:238*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x5, 238*FLEN/8, x6, x1, x2) + +inst_144: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f6 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3f7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bf6; op2val:0xbbf7; + valaddr_reg:x5; val_offset:240*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x5, 240*FLEN/8, x6, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(13213,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(13213,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(13213,32,FLEN) +NAN_BOXED(30186,32,FLEN) +NAN_BOXED(46571,16,FLEN) +NAN_BOXED(30186,32,FLEN) +NAN_BOXED(46571,16,FLEN) +NAN_BOXED(30186,32,FLEN) +NAN_BOXED(46571,16,FLEN) +NAN_BOXED(30186,32,FLEN) +NAN_BOXED(46571,16,FLEN) +NAN_BOXED(30186,32,FLEN) +NAN_BOXED(46571,16,FLEN) +NAN_BOXED(30976,32,FLEN) +NAN_BOXED(14593,32,FLEN) +NAN_BOXED(30976,32,FLEN) +NAN_BOXED(14593,32,FLEN) +test_dataset_1: +NAN_BOXED(30976,32,FLEN) +NAN_BOXED(14593,32,FLEN) +NAN_BOXED(30976,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(30976,32,FLEN) +NAN_BOXED(14593,32,FLEN) +NAN_BOXED(25279,32,FLEN) +NAN_BOXED(41663,16,FLEN) +NAN_BOXED(25279,32,FLEN) +NAN_BOXED(41663,16,FLEN) +NAN_BOXED(25279,32,FLEN) +NAN_BOXED(41663,16,FLEN) +NAN_BOXED(25279,32,FLEN) +NAN_BOXED(41663,16,FLEN) +NAN_BOXED(25279,32,FLEN) +NAN_BOXED(41663,16,FLEN) +NAN_BOXED(29733,32,FLEN) +NAN_BOXED(13350,32,FLEN) +NAN_BOXED(29733,32,FLEN) +NAN_BOXED(13350,32,FLEN) +NAN_BOXED(29733,32,FLEN) +NAN_BOXED(13350,32,FLEN) +NAN_BOXED(29733,32,FLEN) +NAN_BOXED(13350,32,FLEN) +test_dataset_2: +NAN_BOXED(29733,16,FLEN) +NAN_BOXED(13350,16,FLEN) +NAN_BOXED(31734,16,FLEN) +NAN_BOXED(48119,16,FLEN) +NAN_BOXED(31734,16,FLEN) +NAN_BOXED(48119,16,FLEN) +NAN_BOXED(31734,16,FLEN) +NAN_BOXED(48119,16,FLEN) +NAN_BOXED(31734,16,FLEN) +NAN_BOXED(48119,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(48119,16,FLEN) +NAN_BOXED(31408,16,FLEN) +NAN_BOXED(15025,16,FLEN) +NAN_BOXED(31408,16,FLEN) +NAN_BOXED(15025,16,FLEN) +NAN_BOXED(31408,16,FLEN) +NAN_BOXED(15025,16,FLEN) +NAN_BOXED(31408,16,FLEN) +NAN_BOXED(15025,16,FLEN) +NAN_BOXED(31408,16,FLEN) +NAN_BOXED(15025,16,FLEN) +NAN_BOXED(31004,16,FLEN) +NAN_BOXED(47388,16,FLEN) +NAN_BOXED(31004,16,FLEN) +NAN_BOXED(47388,16,FLEN) +NAN_BOXED(31004,16,FLEN) +NAN_BOXED(47388,16,FLEN) +NAN_BOXED(31004,16,FLEN) +NAN_BOXED(47388,16,FLEN) +NAN_BOXED(31004,16,FLEN) +NAN_BOXED(47388,16,FLEN) +NAN_BOXED(30995,16,FLEN) +NAN_BOXED(14612,16,FLEN) +NAN_BOXED(30995,16,FLEN) +NAN_BOXED(14612,16,FLEN) +NAN_BOXED(30995,16,FLEN) +NAN_BOXED(14612,16,FLEN) +NAN_BOXED(30995,16,FLEN) +NAN_BOXED(14612,16,FLEN) +NAN_BOXED(30995,16,FLEN) +NAN_BOXED(14612,16,FLEN) +NAN_BOXED(30766,16,FLEN) +NAN_BOXED(47151,16,FLEN) +NAN_BOXED(30766,16,FLEN) +NAN_BOXED(47151,16,FLEN) +NAN_BOXED(30766,16,FLEN) +NAN_BOXED(47151,16,FLEN) +NAN_BOXED(30766,16,FLEN) +NAN_BOXED(47151,16,FLEN) +NAN_BOXED(30766,16,FLEN) +NAN_BOXED(47151,16,FLEN) +NAN_BOXED(31070,16,FLEN) +NAN_BOXED(14687,16,FLEN) +NAN_BOXED(31070,16,FLEN) +NAN_BOXED(14687,16,FLEN) +NAN_BOXED(31070,16,FLEN) +NAN_BOXED(14687,16,FLEN) +NAN_BOXED(31070,16,FLEN) +NAN_BOXED(14687,16,FLEN) +NAN_BOXED(31070,16,FLEN) +NAN_BOXED(14687,16,FLEN) +NAN_BOXED(31248,16,FLEN) +NAN_BOXED(47632,16,FLEN) +NAN_BOXED(31248,16,FLEN) +NAN_BOXED(47632,16,FLEN) +NAN_BOXED(31248,16,FLEN) +NAN_BOXED(47632,16,FLEN) +NAN_BOXED(31248,16,FLEN) +NAN_BOXED(47632,16,FLEN) +NAN_BOXED(31248,16,FLEN) +NAN_BOXED(47632,16,FLEN) +NAN_BOXED(29905,16,FLEN) +NAN_BOXED(13522,16,FLEN) +NAN_BOXED(29905,16,FLEN) +NAN_BOXED(13522,16,FLEN) +NAN_BOXED(29905,16,FLEN) +NAN_BOXED(13522,16,FLEN) +NAN_BOXED(29905,16,FLEN) +NAN_BOXED(13522,16,FLEN) +NAN_BOXED(29905,16,FLEN) +NAN_BOXED(13522,16,FLEN) +NAN_BOXED(31467,16,FLEN) +NAN_BOXED(47852,16,FLEN) +NAN_BOXED(31467,16,FLEN) +NAN_BOXED(47852,16,FLEN) +NAN_BOXED(31467,16,FLEN) +NAN_BOXED(47852,16,FLEN) +NAN_BOXED(31467,16,FLEN) +NAN_BOXED(47852,16,FLEN) +NAN_BOXED(31467,16,FLEN) +NAN_BOXED(47852,16,FLEN) +NAN_BOXED(31167,16,FLEN) +NAN_BOXED(17856,16,FLEN) +NAN_BOXED(31167,16,FLEN) +NAN_BOXED(17856,16,FLEN) +NAN_BOXED(31167,16,FLEN) +NAN_BOXED(17856,16,FLEN) +NAN_BOXED(31167,16,FLEN) +NAN_BOXED(17856,16,FLEN) +NAN_BOXED(31167,16,FLEN) +NAN_BOXED(17856,16,FLEN) +NAN_BOXED(31157,16,FLEN) +NAN_BOXED(50614,16,FLEN) +NAN_BOXED(31157,16,FLEN) +NAN_BOXED(50614,16,FLEN) +NAN_BOXED(31157,16,FLEN) +NAN_BOXED(50614,16,FLEN) +NAN_BOXED(31157,16,FLEN) +NAN_BOXED(50614,16,FLEN) +NAN_BOXED(31157,16,FLEN) +NAN_BOXED(50614,16,FLEN) +NAN_BOXED(30289,16,FLEN) +NAN_BOXED(15953,16,FLEN) +NAN_BOXED(30289,16,FLEN) +NAN_BOXED(15953,16,FLEN) +NAN_BOXED(30289,16,FLEN) +NAN_BOXED(15953,16,FLEN) +NAN_BOXED(30289,16,FLEN) +NAN_BOXED(15953,16,FLEN) +NAN_BOXED(30289,16,FLEN) +NAN_BOXED(15953,16,FLEN) +NAN_BOXED(30492,16,FLEN) +NAN_BOXED(48925,16,FLEN) +NAN_BOXED(30492,16,FLEN) +NAN_BOXED(48925,16,FLEN) +NAN_BOXED(30492,16,FLEN) +NAN_BOXED(48925,16,FLEN) +NAN_BOXED(30492,16,FLEN) +NAN_BOXED(48925,16,FLEN) +NAN_BOXED(30492,16,FLEN) +NAN_BOXED(48925,16,FLEN) +NAN_BOXED(31495,16,FLEN) +NAN_BOXED(16135,16,FLEN) +NAN_BOXED(31495,16,FLEN) +NAN_BOXED(16135,16,FLEN) +NAN_BOXED(31495,16,FLEN) +NAN_BOXED(16135,16,FLEN) +NAN_BOXED(31495,16,FLEN) +NAN_BOXED(16135,16,FLEN) +NAN_BOXED(31495,16,FLEN) +NAN_BOXED(16135,16,FLEN) +NAN_BOXED(28761,16,FLEN) +NAN_BOXED(46169,16,FLEN) +NAN_BOXED(28761,16,FLEN) +NAN_BOXED(46169,16,FLEN) +NAN_BOXED(28761,16,FLEN) +NAN_BOXED(46169,16,FLEN) +NAN_BOXED(28761,16,FLEN) +NAN_BOXED(46169,16,FLEN) +NAN_BOXED(28761,16,FLEN) +NAN_BOXED(46169,16,FLEN) +NAN_BOXED(31672,16,FLEN) +NAN_BOXED(15289,16,FLEN) +NAN_BOXED(31672,16,FLEN) +NAN_BOXED(15289,16,FLEN) +NAN_BOXED(31672,16,FLEN) +NAN_BOXED(15289,16,FLEN) +NAN_BOXED(31672,16,FLEN) +NAN_BOXED(15289,16,FLEN) +NAN_BOXED(31672,16,FLEN) +NAN_BOXED(15289,16,FLEN) +NAN_BOXED(30978,16,FLEN) +NAN_BOXED(47363,16,FLEN) +NAN_BOXED(30978,16,FLEN) +NAN_BOXED(47363,16,FLEN) +NAN_BOXED(30978,16,FLEN) +NAN_BOXED(47363,16,FLEN) +NAN_BOXED(30978,16,FLEN) +NAN_BOXED(47363,16,FLEN) +NAN_BOXED(30978,16,FLEN) +NAN_BOXED(47363,16,FLEN) +NAN_BOXED(30734,16,FLEN) +NAN_BOXED(13326,16,FLEN) +NAN_BOXED(30734,16,FLEN) +NAN_BOXED(13326,16,FLEN) +NAN_BOXED(30734,16,FLEN) +NAN_BOXED(13326,16,FLEN) +NAN_BOXED(30734,16,FLEN) +NAN_BOXED(13326,16,FLEN) +NAN_BOXED(30734,16,FLEN) +NAN_BOXED(13326,16,FLEN) +NAN_BOXED(30108,16,FLEN) +NAN_BOXED(45469,16,FLEN) +NAN_BOXED(30108,16,FLEN) +NAN_BOXED(45469,16,FLEN) +NAN_BOXED(30108,16,FLEN) +NAN_BOXED(45469,16,FLEN) +NAN_BOXED(30108,16,FLEN) +NAN_BOXED(45469,16,FLEN) +NAN_BOXED(30108,16,FLEN) +NAN_BOXED(45469,16,FLEN) +NAN_BOXED(30891,16,FLEN) +NAN_BOXED(12460,16,FLEN) +NAN_BOXED(30891,16,FLEN) +NAN_BOXED(12460,16,FLEN) +NAN_BOXED(30891,16,FLEN) +NAN_BOXED(12460,16,FLEN) +NAN_BOXED(30891,16,FLEN) +NAN_BOXED(12460,16,FLEN) +NAN_BOXED(30891,16,FLEN) +NAN_BOXED(12460,16,FLEN) +NAN_BOXED(31092,16,FLEN) +NAN_BOXED(45428,16,FLEN) +NAN_BOXED(31092,16,FLEN) +NAN_BOXED(45428,16,FLEN) +NAN_BOXED(31092,16,FLEN) +NAN_BOXED(45428,16,FLEN) +NAN_BOXED(31092,16,FLEN) +NAN_BOXED(45428,16,FLEN) +NAN_BOXED(31092,16,FLEN) +NAN_BOXED(45428,16,FLEN) +NAN_BOXED(31449,16,FLEN) +NAN_BOXED(11993,16,FLEN) +NAN_BOXED(31449,16,FLEN) +NAN_BOXED(11993,16,FLEN) +NAN_BOXED(31449,16,FLEN) +NAN_BOXED(11993,16,FLEN) +NAN_BOXED(31449,16,FLEN) +NAN_BOXED(11993,16,FLEN) +NAN_BOXED(31449,16,FLEN) +NAN_BOXED(11993,16,FLEN) +NAN_BOXED(31070,16,FLEN) +NAN_BOXED(44382,16,FLEN) +NAN_BOXED(31070,16,FLEN) +NAN_BOXED(44382,16,FLEN) +NAN_BOXED(31070,16,FLEN) +NAN_BOXED(44382,16,FLEN) +NAN_BOXED(31070,16,FLEN) +NAN_BOXED(44382,16,FLEN) +NAN_BOXED(31070,16,FLEN) +NAN_BOXED(44382,16,FLEN) +NAN_BOXED(29596,16,FLEN) +NAN_BOXED(13213,16,FLEN) +NAN_BOXED(29596,16,FLEN) +NAN_BOXED(13213,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(14593,16,FLEN) +NAN_BOXED(25279,16,FLEN) +NAN_BOXED(41663,16,FLEN) +NAN_BOXED(31734,16,FLEN) +NAN_BOXED(48119,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x6_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x6_1: + .fill 30*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_0: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 232*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fdiv_b5-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fdiv_b5-01.S new file mode 100644 index 000000000..13a817fe2 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fdiv_b5-01.S @@ -0,0 +1,2359 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 05:22:24 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fdiv.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fdiv.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fdiv_b5 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fdiv_b5) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x15,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd != rs2, rs1==x14, rs2==x29, rd==x14,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x14; op2:x29; dest:x14; op1val:0x739c; op2val:0x7bff; + valaddr_reg:x15; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fdiv.h, x14, x14, x29, dyn, 0, 0, x15, 0*FLEN/8, x18, x1, x5) + +inst_1: +// rs1 == rs2 != rd, rs1==x10, rs2==x10, rd==x21,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x10; op2:x10; dest:x21; op1val:0x739c; op2val:0x739c; + valaddr_reg:x15; val_offset:2*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fdiv.h, x21, x10, x10, dyn, 32, 0, x15, 2*FLEN/8, x18, x1, x5) + +inst_2: +// rs1 == rs2 == rd, rs1==x4, rs2==x4, rd==x4,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x4; op2:x4; dest:x4; op1val:0x739c; op2val:0x739c; + valaddr_reg:x15; val_offset:4*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fdiv.h, x4, x4, x4, dyn, 64, 0, x15, 4*FLEN/8, x18, x1, x5) + +inst_3: +// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==x29, rs2==x3, rd==x27,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x29; op2:x3; dest:x27; op1val:0x739c; op2val:0x7bff; + valaddr_reg:x15; val_offset:6*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fdiv.h, x27, x29, x3, dyn, 96, 0, x15, 6*FLEN/8, x18, x1, x5) + +inst_4: +// rs2 == rd != rs1, rs1==x3, rs2==x8, rd==x8,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x3; op2:x8; dest:x8; op1val:0x739c; op2val:0x7bff; + valaddr_reg:x15; val_offset:8*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fdiv.h, x8, x3, x8, dyn, 128, 0, x15, 8*FLEN/8, x18, x1, x5) + +inst_5: +// rs1==x20, rs2==x17, rd==x30,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ea and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x20; op2:x17; dest:x30; op1val:0x75ea; op2val:0x7bff; + valaddr_reg:x15; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fdiv.h, x30, x20, x17, dyn, 0, 0, x15, 10*FLEN/8, x18, x1, x5) + +inst_6: +// rs1==x11, rs2==x22, rd==x12,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ea and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x11; op2:x22; dest:x12; op1val:0x75ea; op2val:0x7bff; + valaddr_reg:x15; val_offset:12*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fdiv.h, x12, x11, x22, dyn, 32, 0, x15, 12*FLEN/8, x18, x1, x5) + +inst_7: +// rs1==x2, rs2==x31, rd==x9,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ea and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x2; op2:x31; dest:x9; op1val:0x75ea; op2val:0x7bff; + valaddr_reg:x15; val_offset:14*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fdiv.h, x9, x2, x31, dyn, 64, 0, x15, 14*FLEN/8, x18, x1, x5) + +inst_8: +// rs1==x12, rs2==x23, rd==x16,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ea and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x12; op2:x23; dest:x16; op1val:0x75ea; op2val:0x7bff; + valaddr_reg:x15; val_offset:16*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fdiv.h, x16, x12, x23, dyn, 96, 0, x15, 16*FLEN/8, x18, x1, x5) + +inst_9: +// rs1==x26, rs2==x20, rd==x3,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ea and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x26; op2:x20; dest:x3; op1val:0x75ea; op2val:0x7bff; + valaddr_reg:x15; val_offset:18*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fdiv.h, x3, x26, x20, dyn, 128, 0, x15, 18*FLEN/8, x18, x1, x5) + +inst_10: +// rs1==x7, rs2==x13, rd==x6,fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x7; op2:x13; dest:x6; op1val:0x7900; op2val:0x7bff; + valaddr_reg:x15; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fdiv.h, x6, x7, x13, dyn, 0, 0, x15, 20*FLEN/8, x18, x1, x5) +RVTEST_VALBASEUPD(x6,test_dataset_1) + +inst_11: +// rs1==x13, rs2==x30, rd==x29,fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x13; op2:x30; dest:x29; op1val:0x7900; op2val:0x7bff; + valaddr_reg:x6; val_offset:0*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fdiv.h, x29, x13, x30, dyn, 32, 0, x6, 0*FLEN/8, x8, x1, x5) + +inst_12: +// rs1==x0, rs2==x19, rd==x7,fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x0; op2:x19; dest:x7; op1val:0x0; op2val:0x7bff; + valaddr_reg:x6; val_offset:2*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fdiv.h, x7, x0, x19, dyn, 64, 0, x6, 2*FLEN/8, x8, x1, x5) + +inst_13: +// rs1==x25, rs2==x28, rd==x17,fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x25; op2:x28; dest:x17; op1val:0x7900; op2val:0x7bff; + valaddr_reg:x6; val_offset:4*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fdiv.h, x17, x25, x28, dyn, 96, 0, x6, 4*FLEN/8, x8, x1, x5) +RVTEST_SIGBASE(x3,signature_x3_0) + +inst_14: +// rs1==x31, rs2==x11, rd==x26,fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x31; op2:x11; dest:x26; op1val:0x7900; op2val:0x7bff; + valaddr_reg:x6; val_offset:6*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x26, x31, x11, dyn, 128, 0, x6, 6*FLEN/8, x8, x3, x4) + +inst_15: +// rs1==x27, rs2==x18, rd==x25,fs1 == 0 and fe1 == 0x18 and fm1 == 0x2bf and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x27; op2:x18; dest:x25; op1val:0x62bf; op2val:0x7bff; + valaddr_reg:x6; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x25, x27, x18, dyn, 0, 0, x6, 8*FLEN/8, x8, x3, x4) + +inst_16: +// rs1==x9, rs2==x26, rd==x19,fs1 == 0 and fe1 == 0x18 and fm1 == 0x2bf and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x9; op2:x26; dest:x19; op1val:0x62bf; op2val:0x7bff; + valaddr_reg:x6; val_offset:10*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x19, x9, x26, dyn, 32, 0, x6, 10*FLEN/8, x8, x3, x4) + +inst_17: +// rs1==x21, rs2==x0, rd==x13,fs1 == 0 and fe1 == 0x18 and fm1 == 0x2bf and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x21; op2:x0; dest:x13; op1val:0x62bf; op2val:0x0; + valaddr_reg:x6; val_offset:12*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x13, x21, x0, dyn, 64, 0, x6, 12*FLEN/8, x8, x3, x4) + +inst_18: +// rs1==x19, rs2==x2, rd==x0,fs1 == 0 and fe1 == 0x18 and fm1 == 0x2bf and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x19; op2:x2; dest:x0; op1val:0x62bf; op2val:0x7bff; + valaddr_reg:x6; val_offset:14*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x0, x19, x2, dyn, 96, 0, x6, 14*FLEN/8, x8, x3, x4) + +inst_19: +// rs1==x23, rs2==x7, rd==x31,fs1 == 0 and fe1 == 0x18 and fm1 == 0x2bf and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x23; op2:x7; dest:x31; op1val:0x62bf; op2val:0x7bff; + valaddr_reg:x6; val_offset:16*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x23, x7, dyn, 128, 0, x6, 16*FLEN/8, x8, x3, x4) + +inst_20: +// rs1==x1, rs2==x21, rd==x5,fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x1; op2:x21; dest:x5; op1val:0x7425; op2val:0x7bff; + valaddr_reg:x6; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x5, x1, x21, dyn, 0, 0, x6, 18*FLEN/8, x8, x3, x4) + +inst_21: +// rs1==x22, rs2==x5, rd==x23,fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x22; op2:x5; dest:x23; op1val:0x7425; op2val:0x7bff; + valaddr_reg:x6; val_offset:20*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x23, x22, x5, dyn, 32, 0, x6, 20*FLEN/8, x8, x3, x4) + +inst_22: +// rs1==x17, rs2==x15, rd==x18,fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x17; op2:x15; dest:x18; op1val:0x7425; op2val:0x7bff; + valaddr_reg:x6; val_offset:22*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x18, x17, x15, dyn, 64, 0, x6, 22*FLEN/8, x8, x3, x4) + +inst_23: +// rs1==x24, rs2==x9, rd==x20,fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x24; op2:x9; dest:x20; op1val:0x7425; op2val:0x7bff; + valaddr_reg:x6; val_offset:24*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x20, x24, x9, dyn, 96, 0, x6, 24*FLEN/8, x8, x3, x4) +RVTEST_VALBASEUPD(x7,test_dataset_2) + +inst_24: +// rs1==x18, rs2==x6, rd==x11,fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x18; op2:x6; dest:x11; op1val:0x7425; op2val:0x7bff; + valaddr_reg:x7; val_offset:0*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x11, x18, x6, dyn, 128, 0, x7, 0*FLEN/8, x9, x3, x4) + +inst_25: +// rs1==x15, rs2==x24, rd==x1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x15; op2:x24; dest:x1; op1val:0x7bf6; op2val:0x7bff; + valaddr_reg:x7; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x1, x15, x24, dyn, 0, 0, x7, 2*FLEN/8, x9, x3, x4) + +inst_26: +// rs1==x16, rs2==x1, rd==x24,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x16; op2:x1; dest:x24; op1val:0x7bf6; op2val:0x7bff; + valaddr_reg:x7; val_offset:4*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x24, x16, x1, dyn, 32, 0, x7, 4*FLEN/8, x9, x3, x4) + +inst_27: +// rs1==x30, rs2==x27, rd==x28,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x27; dest:x28; op1val:0x7bf6; op2val:0x7bff; + valaddr_reg:x7; val_offset:6*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x28, x30, x27, dyn, 64, 0, x7, 6*FLEN/8, x9, x3, x4) + +inst_28: +// rs1==x6, rs2==x14, rd==x22,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x6; op2:x14; dest:x22; op1val:0x7bf6; op2val:0x7bff; + valaddr_reg:x7; val_offset:8*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x22, x6, x14, dyn, 96, 0, x7, 8*FLEN/8, x9, x3, x4) + +inst_29: +// rs1==x28, rs2==x12, rd==x15,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x28; op2:x12; dest:x15; op1val:0x7bf6; op2val:0x7bff; + valaddr_reg:x7; val_offset:10*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x15, x28, x12, dyn, 128, 0, x7, 10*FLEN/8, x9, x3, x4) +RVTEST_SIGBASE(x1,signature_x1_2) + +inst_30: +// rs1==x8, rs2==x25, rd==x10,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x8; op2:x25; dest:x10; op1val:0x7ab0; op2val:0x7bff; + valaddr_reg:x7; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x10, x8, x25, dyn, 0, 0, x7, 12*FLEN/8, x9, x1, x4) + +inst_31: +// rs1==x5, rs2==x16, rd==x2,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x5; op2:x16; dest:x2; op1val:0x7ab0; op2val:0x7bff; + valaddr_reg:x7; val_offset:14*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x2, x5, x16, dyn, 32, 0, x7, 14*FLEN/8, x9, x1, x4) + +inst_32: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab0; op2val:0x7bff; + valaddr_reg:x7; val_offset:16*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x7, 16*FLEN/8, x9, x1, x4) + +inst_33: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab0; op2val:0x7bff; + valaddr_reg:x7; val_offset:18*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x7, 18*FLEN/8, x9, x1, x4) + +inst_34: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab0; op2val:0x7bff; + valaddr_reg:x7; val_offset:20*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x7, 20*FLEN/8, x9, x1, x4) + +inst_35: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x11c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x791c; op2val:0x7bff; + valaddr_reg:x7; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x7, 22*FLEN/8, x9, x1, x4) + +inst_36: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x11c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x791c; op2val:0x7bff; + valaddr_reg:x7; val_offset:24*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x7, 24*FLEN/8, x9, x1, x4) + +inst_37: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x11c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x791c; op2val:0x7bff; + valaddr_reg:x7; val_offset:26*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x7, 26*FLEN/8, x9, x1, x4) + +inst_38: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x11c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x791c; op2val:0x7bff; + valaddr_reg:x7; val_offset:28*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x7, 28*FLEN/8, x9, x1, x4) + +inst_39: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x11c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x791c; op2val:0x7bff; + valaddr_reg:x7; val_offset:30*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x7, 30*FLEN/8, x9, x1, x4) + +inst_40: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0x7bff; + valaddr_reg:x7; val_offset:32*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x7, 32*FLEN/8, x9, x1, x4) + +inst_41: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0x7bff; + valaddr_reg:x7; val_offset:34*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x7, 34*FLEN/8, x9, x1, x4) + +inst_42: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0x7bff; + valaddr_reg:x7; val_offset:36*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x7, 36*FLEN/8, x9, x1, x4) + +inst_43: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0x7bff; + valaddr_reg:x7; val_offset:38*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x7, 38*FLEN/8, x9, x1, x4) + +inst_44: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0x7bff; + valaddr_reg:x7; val_offset:40*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x7, 40*FLEN/8, x9, x1, x4) + +inst_45: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x782e; op2val:0x7bff; + valaddr_reg:x7; val_offset:42*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x7, 42*FLEN/8, x9, x1, x4) + +inst_46: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x782e; op2val:0x7bff; + valaddr_reg:x7; val_offset:44*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x7, 44*FLEN/8, x9, x1, x4) + +inst_47: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x782e; op2val:0x7bff; + valaddr_reg:x7; val_offset:46*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x7, 46*FLEN/8, x9, x1, x4) + +inst_48: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x782e; op2val:0x7bff; + valaddr_reg:x7; val_offset:48*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x7, 48*FLEN/8, x9, x1, x4) + +inst_49: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x782e; op2val:0x7bff; + valaddr_reg:x7; val_offset:50*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x7, 50*FLEN/8, x9, x1, x4) + +inst_50: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x795e; op2val:0x7bff; + valaddr_reg:x7; val_offset:52*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x7, 52*FLEN/8, x9, x1, x4) + +inst_51: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x795e; op2val:0x7bff; + valaddr_reg:x7; val_offset:54*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x7, 54*FLEN/8, x9, x1, x4) + +inst_52: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x795e; op2val:0x7bff; + valaddr_reg:x7; val_offset:56*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x7, 56*FLEN/8, x9, x1, x4) + +inst_53: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x795e; op2val:0x7bff; + valaddr_reg:x7; val_offset:58*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x7, 58*FLEN/8, x9, x1, x4) + +inst_54: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x795e; op2val:0x7bff; + valaddr_reg:x7; val_offset:60*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x7, 60*FLEN/8, x9, x1, x4) + +inst_55: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x210 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a10; op2val:0x7bff; + valaddr_reg:x7; val_offset:62*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x7, 62*FLEN/8, x9, x1, x4) + +inst_56: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x210 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a10; op2val:0x7bff; + valaddr_reg:x7; val_offset:64*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x7, 64*FLEN/8, x9, x1, x4) + +inst_57: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x210 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a10; op2val:0x7bff; + valaddr_reg:x7; val_offset:66*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x7, 66*FLEN/8, x9, x1, x4) + +inst_58: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x210 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a10; op2val:0x7bff; + valaddr_reg:x7; val_offset:68*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x7, 68*FLEN/8, x9, x1, x4) + +inst_59: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x210 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a10; op2val:0x7bff; + valaddr_reg:x7; val_offset:70*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x7, 70*FLEN/8, x9, x1, x4) + +inst_60: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74d1; op2val:0x7bff; + valaddr_reg:x7; val_offset:72*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x7, 72*FLEN/8, x9, x1, x4) + +inst_61: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74d1; op2val:0x7bff; + valaddr_reg:x7; val_offset:74*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x7, 74*FLEN/8, x9, x1, x4) + +inst_62: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74d1; op2val:0x7bff; + valaddr_reg:x7; val_offset:76*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x7, 76*FLEN/8, x9, x1, x4) + +inst_63: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74d1; op2val:0x7bff; + valaddr_reg:x7; val_offset:78*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x7, 78*FLEN/8, x9, x1, x4) + +inst_64: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74d1; op2val:0x7bff; + valaddr_reg:x7; val_offset:80*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x7, 80*FLEN/8, x9, x1, x4) + +inst_65: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2eb and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aeb; op2val:0x7bff; + valaddr_reg:x7; val_offset:82*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x7, 82*FLEN/8, x9, x1, x4) + +inst_66: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2eb and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aeb; op2val:0x7bff; + valaddr_reg:x7; val_offset:84*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x7, 84*FLEN/8, x9, x1, x4) + +inst_67: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2eb and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aeb; op2val:0x7bff; + valaddr_reg:x7; val_offset:86*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x7, 86*FLEN/8, x9, x1, x4) + +inst_68: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2eb and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aeb; op2val:0x7bff; + valaddr_reg:x7; val_offset:88*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x7, 88*FLEN/8, x9, x1, x4) + +inst_69: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2eb and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aeb; op2val:0x7bff; + valaddr_reg:x7; val_offset:90*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x7, 90*FLEN/8, x9, x1, x4) + +inst_70: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1bf and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79bf; op2val:0x7bff; + valaddr_reg:x7; val_offset:92*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x7, 92*FLEN/8, x9, x1, x4) + +inst_71: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1bf and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79bf; op2val:0x7bff; + valaddr_reg:x7; val_offset:94*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x7, 94*FLEN/8, x9, x1, x4) + +inst_72: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1bf and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79bf; op2val:0x7bff; + valaddr_reg:x7; val_offset:96*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x7, 96*FLEN/8, x9, x1, x4) + +inst_73: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1bf and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79bf; op2val:0x7bff; + valaddr_reg:x7; val_offset:98*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x7, 98*FLEN/8, x9, x1, x4) + +inst_74: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1bf and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79bf; op2val:0x7bff; + valaddr_reg:x7; val_offset:100*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x7, 100*FLEN/8, x9, x1, x4) + +inst_75: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b5; op2val:0x7bff; + valaddr_reg:x7; val_offset:102*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x7, 102*FLEN/8, x9, x1, x4) + +inst_76: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b5; op2val:0x7bff; + valaddr_reg:x7; val_offset:104*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x7, 104*FLEN/8, x9, x1, x4) + +inst_77: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b5; op2val:0x7bff; + valaddr_reg:x7; val_offset:106*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x7, 106*FLEN/8, x9, x1, x4) + +inst_78: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b5; op2val:0x7bff; + valaddr_reg:x7; val_offset:108*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x7, 108*FLEN/8, x9, x1, x4) + +inst_79: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b5; op2val:0x7bff; + valaddr_reg:x7; val_offset:110*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x7, 110*FLEN/8, x9, x1, x4) + +inst_80: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x251 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7651; op2val:0x7bff; + valaddr_reg:x7; val_offset:112*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x7, 112*FLEN/8, x9, x1, x4) + +inst_81: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x251 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7651; op2val:0x7bff; + valaddr_reg:x7; val_offset:114*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x7, 114*FLEN/8, x9, x1, x4) + +inst_82: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x251 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7651; op2val:0x7bff; + valaddr_reg:x7; val_offset:116*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x7, 116*FLEN/8, x9, x1, x4) + +inst_83: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x251 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7651; op2val:0x7bff; + valaddr_reg:x7; val_offset:118*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x7, 118*FLEN/8, x9, x1, x4) + +inst_84: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x251 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7651; op2val:0x7bff; + valaddr_reg:x7; val_offset:120*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x7, 120*FLEN/8, x9, x1, x4) + +inst_85: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x771c; op2val:0x7bff; + valaddr_reg:x7; val_offset:122*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x7, 122*FLEN/8, x9, x1, x4) + +inst_86: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x771c; op2val:0x7bff; + valaddr_reg:x7; val_offset:124*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x7, 124*FLEN/8, x9, x1, x4) + +inst_87: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x771c; op2val:0x7bff; + valaddr_reg:x7; val_offset:126*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x7, 126*FLEN/8, x9, x1, x4) + +inst_88: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x771c; op2val:0x7bff; + valaddr_reg:x7; val_offset:128*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x7, 128*FLEN/8, x9, x1, x4) + +inst_89: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x771c; op2val:0x7bff; + valaddr_reg:x7; val_offset:130*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x7, 130*FLEN/8, x9, x1, x4) + +inst_90: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x307 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b07; op2val:0x7bff; + valaddr_reg:x7; val_offset:132*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x7, 132*FLEN/8, x9, x1, x4) + +inst_91: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x307 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b07; op2val:0x7bff; + valaddr_reg:x7; val_offset:134*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x7, 134*FLEN/8, x9, x1, x4) + +inst_92: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x307 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b07; op2val:0x7bff; + valaddr_reg:x7; val_offset:136*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x7, 136*FLEN/8, x9, x1, x4) + +inst_93: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x307 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b07; op2val:0x7bff; + valaddr_reg:x7; val_offset:138*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x7, 138*FLEN/8, x9, x1, x4) + +inst_94: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x307 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b07; op2val:0x7bff; + valaddr_reg:x7; val_offset:140*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x7, 140*FLEN/8, x9, x1, x4) + +inst_95: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x059 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7059; op2val:0x7bff; + valaddr_reg:x7; val_offset:142*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x7, 142*FLEN/8, x9, x1, x4) + +inst_96: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x059 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7059; op2val:0x7bff; + valaddr_reg:x7; val_offset:144*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x7, 144*FLEN/8, x9, x1, x4) + +inst_97: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x059 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7059; op2val:0x7bff; + valaddr_reg:x7; val_offset:146*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x7, 146*FLEN/8, x9, x1, x4) + +inst_98: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x059 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7059; op2val:0x7bff; + valaddr_reg:x7; val_offset:148*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x7, 148*FLEN/8, x9, x1, x4) + +inst_99: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x059 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7059; op2val:0x7bff; + valaddr_reg:x7; val_offset:150*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x7, 150*FLEN/8, x9, x1, x4) + +inst_100: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb8; op2val:0x7bff; + valaddr_reg:x7; val_offset:152*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x7, 152*FLEN/8, x9, x1, x4) + +inst_101: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb8; op2val:0x7bff; + valaddr_reg:x7; val_offset:154*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x7, 154*FLEN/8, x9, x1, x4) + +inst_102: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb8; op2val:0x7bff; + valaddr_reg:x7; val_offset:156*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x7, 156*FLEN/8, x9, x1, x4) + +inst_103: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb8; op2val:0x7bff; + valaddr_reg:x7; val_offset:158*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x7, 158*FLEN/8, x9, x1, x4) + +inst_104: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb8; op2val:0x7bff; + valaddr_reg:x7; val_offset:160*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x7, 160*FLEN/8, x9, x1, x4) + +inst_105: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x102 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7902; op2val:0x7bff; + valaddr_reg:x7; val_offset:162*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x7, 162*FLEN/8, x9, x1, x4) + +inst_106: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x102 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7902; op2val:0x7bff; + valaddr_reg:x7; val_offset:164*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x7, 164*FLEN/8, x9, x1, x4) + +inst_107: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x102 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7902; op2val:0x7bff; + valaddr_reg:x7; val_offset:166*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x7, 166*FLEN/8, x9, x1, x4) + +inst_108: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x102 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7902; op2val:0x7bff; + valaddr_reg:x7; val_offset:168*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x7, 168*FLEN/8, x9, x1, x4) + +inst_109: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x102 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7902; op2val:0x7bff; + valaddr_reg:x7; val_offset:170*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x7, 170*FLEN/8, x9, x1, x4) + +inst_110: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x780e; op2val:0xfbff; + valaddr_reg:x7; val_offset:172*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x7, 172*FLEN/8, x9, x1, x4) + +inst_111: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x780e; op2val:0xfbff; + valaddr_reg:x7; val_offset:174*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x7, 174*FLEN/8, x9, x1, x4) + +inst_112: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x780e; op2val:0xfbff; + valaddr_reg:x7; val_offset:176*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x7, 176*FLEN/8, x9, x1, x4) + +inst_113: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x780e; op2val:0xfbff; + valaddr_reg:x7; val_offset:178*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x7, 178*FLEN/8, x9, x1, x4) + +inst_114: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x780e; op2val:0xfbff; + valaddr_reg:x7; val_offset:180*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x7, 180*FLEN/8, x9, x1, x4) + +inst_115: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x19c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x759c; op2val:0xfbff; + valaddr_reg:x7; val_offset:182*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x7, 182*FLEN/8, x9, x1, x4) + +inst_116: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x19c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x759c; op2val:0xfbff; + valaddr_reg:x7; val_offset:184*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x7, 184*FLEN/8, x9, x1, x4) + +inst_117: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x19c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x759c; op2val:0xfbff; + valaddr_reg:x7; val_offset:186*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x7, 186*FLEN/8, x9, x1, x4) + +inst_118: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x19c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x759c; op2val:0xfbff; + valaddr_reg:x7; val_offset:188*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x7, 188*FLEN/8, x9, x1, x4) + +inst_119: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x19c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x759c; op2val:0xfbff; + valaddr_reg:x7; val_offset:190*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x7, 190*FLEN/8, x9, x1, x4) + +inst_120: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ab and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78ab; op2val:0xfbff; + valaddr_reg:x7; val_offset:192*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x7, 192*FLEN/8, x9, x1, x4) + +inst_121: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ab and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78ab; op2val:0xfbff; + valaddr_reg:x7; val_offset:194*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x7, 194*FLEN/8, x9, x1, x4) + +inst_122: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ab and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78ab; op2val:0xfbff; + valaddr_reg:x7; val_offset:196*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x7, 196*FLEN/8, x9, x1, x4) + +inst_123: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ab and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78ab; op2val:0xfbff; + valaddr_reg:x7; val_offset:198*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x7, 198*FLEN/8, x9, x1, x4) + +inst_124: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ab and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78ab; op2val:0xfbff; + valaddr_reg:x7; val_offset:200*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x7, 200*FLEN/8, x9, x1, x4) + +inst_125: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x174 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7974; op2val:0xfbff; + valaddr_reg:x7; val_offset:202*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x7, 202*FLEN/8, x9, x1, x4) + +inst_126: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x174 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7974; op2val:0xfbff; + valaddr_reg:x7; val_offset:204*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x7, 204*FLEN/8, x9, x1, x4) + +inst_127: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x174 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7974; op2val:0xfbff; + valaddr_reg:x7; val_offset:206*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x7, 206*FLEN/8, x9, x1, x4) + +inst_128: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x174 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7974; op2val:0xfbff; + valaddr_reg:x7; val_offset:208*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x7, 208*FLEN/8, x9, x1, x4) + +inst_129: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x174 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7974; op2val:0xfbff; + valaddr_reg:x7; val_offset:210*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x7, 210*FLEN/8, x9, x1, x4) + +inst_130: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ad9; op2val:0xfbff; + valaddr_reg:x7; val_offset:212*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x7, 212*FLEN/8, x9, x1, x4) + +inst_131: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ad9; op2val:0xfbff; + valaddr_reg:x7; val_offset:214*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x7, 214*FLEN/8, x9, x1, x4) + +inst_132: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ad9; op2val:0xfbff; + valaddr_reg:x7; val_offset:216*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x7, 216*FLEN/8, x9, x1, x4) + +inst_133: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ad9; op2val:0xfbff; + valaddr_reg:x7; val_offset:218*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x7, 218*FLEN/8, x9, x1, x4) + +inst_134: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ad9; op2val:0xfbff; + valaddr_reg:x7; val_offset:220*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x7, 220*FLEN/8, x9, x1, x4) + +inst_135: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x795e; op2val:0xfbff; + valaddr_reg:x7; val_offset:222*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x7, 222*FLEN/8, x9, x1, x4) + +inst_136: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x795e; op2val:0xfbff; + valaddr_reg:x7; val_offset:224*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x7, 224*FLEN/8, x9, x1, x4) + +inst_137: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x795e; op2val:0xfbff; + valaddr_reg:x7; val_offset:226*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x7, 226*FLEN/8, x9, x1, x4) + +inst_138: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x795e; op2val:0xfbff; + valaddr_reg:x7; val_offset:228*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x7, 228*FLEN/8, x9, x1, x4) + +inst_139: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x795e; op2val:0xfbff; + valaddr_reg:x7; val_offset:230*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x7, 230*FLEN/8, x9, x1, x4) + +inst_140: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e1 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ae1; op2val:0xfbff; + valaddr_reg:x7; val_offset:232*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x7, 232*FLEN/8, x9, x1, x4) + +inst_141: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e1 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ae1; op2val:0xfbff; + valaddr_reg:x7; val_offset:234*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x7, 234*FLEN/8, x9, x1, x4) + +inst_142: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e1 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ae1; op2val:0xfbff; + valaddr_reg:x7; val_offset:236*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x7, 236*FLEN/8, x9, x1, x4) + +inst_143: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e1 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ae1; op2val:0xfbff; + valaddr_reg:x7; val_offset:238*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x7, 238*FLEN/8, x9, x1, x4) + +inst_144: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e1 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ae1; op2val:0xfbff; + valaddr_reg:x7; val_offset:240*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x7, 240*FLEN/8, x9, x1, x4) + +inst_145: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x33b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b3b; op2val:0xfbff; + valaddr_reg:x7; val_offset:242*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x7, 242*FLEN/8, x9, x1, x4) + +inst_146: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x33b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b3b; op2val:0xfbff; + valaddr_reg:x7; val_offset:244*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x7, 244*FLEN/8, x9, x1, x4) + +inst_147: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x33b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b3b; op2val:0xfbff; + valaddr_reg:x7; val_offset:246*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x7, 246*FLEN/8, x9, x1, x4) + +inst_148: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x33b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b3b; op2val:0xfbff; + valaddr_reg:x7; val_offset:248*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x7, 248*FLEN/8, x9, x1, x4) + +inst_149: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x33b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b3b; op2val:0xfbff; + valaddr_reg:x7; val_offset:250*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x7, 250*FLEN/8, x9, x1, x4) + +inst_150: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b5 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b5; op2val:0xfbff; + valaddr_reg:x7; val_offset:252*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x7, 252*FLEN/8, x9, x1, x4) + +inst_151: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b5 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b5; op2val:0xfbff; + valaddr_reg:x7; val_offset:254*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x7, 254*FLEN/8, x9, x1, x4) + +inst_152: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b5 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b5; op2val:0xfbff; + valaddr_reg:x7; val_offset:256*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x7, 256*FLEN/8, x9, x1, x4) + +inst_153: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b5 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b5; op2val:0xfbff; + valaddr_reg:x7; val_offset:258*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x7, 258*FLEN/8, x9, x1, x4) + +inst_154: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b5 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b5; op2val:0xfbff; + valaddr_reg:x7; val_offset:260*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x7, 260*FLEN/8, x9, x1, x4) + +inst_155: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a6 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aa6; op2val:0xfbff; + valaddr_reg:x7; val_offset:262*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x7, 262*FLEN/8, x9, x1, x4) + +inst_156: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a6 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aa6; op2val:0xfbff; + valaddr_reg:x7; val_offset:264*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x7, 264*FLEN/8, x9, x1, x4) + +inst_157: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a6 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aa6; op2val:0xfbff; + valaddr_reg:x7; val_offset:266*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x7, 266*FLEN/8, x9, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_3) + +inst_158: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a6 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aa6; op2val:0xfbff; + valaddr_reg:x7; val_offset:268*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x7, 268*FLEN/8, x9, x1, x4) + +inst_159: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a6 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aa6; op2val:0xfbff; + valaddr_reg:x7; val_offset:270*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x7, 270*FLEN/8, x9, x1, x4) + +inst_160: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x08e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x748e; op2val:0xfbff; + valaddr_reg:x7; val_offset:272*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x7, 272*FLEN/8, x9, x1, x4) + +inst_161: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x08e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x748e; op2val:0xfbff; + valaddr_reg:x7; val_offset:274*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x7, 274*FLEN/8, x9, x1, x4) + +inst_162: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x08e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x748e; op2val:0xfbff; + valaddr_reg:x7; val_offset:276*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x7, 276*FLEN/8, x9, x1, x4) + +inst_163: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x08e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x748e; op2val:0xfbff; + valaddr_reg:x7; val_offset:278*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x7, 278*FLEN/8, x9, x1, x4) + +inst_164: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x08e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x748e; op2val:0xfbff; + valaddr_reg:x7; val_offset:280*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x7, 280*FLEN/8, x9, x1, x4) + +inst_165: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ad4; op2val:0xfbff; + valaddr_reg:x7; val_offset:282*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x7, 282*FLEN/8, x9, x1, x4) + +inst_166: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ad4; op2val:0xfbff; + valaddr_reg:x7; val_offset:284*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x7, 284*FLEN/8, x9, x1, x4) + +inst_167: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ad4; op2val:0xfbff; + valaddr_reg:x7; val_offset:286*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x7, 286*FLEN/8, x9, x1, x4) + +inst_168: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ad4; op2val:0xfbff; + valaddr_reg:x7; val_offset:288*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x7, 288*FLEN/8, x9, x1, x4) + +inst_169: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ad4; op2val:0xfbff; + valaddr_reg:x7; val_offset:290*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x7, 290*FLEN/8, x9, x1, x4) + +inst_170: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1a9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6da9; op2val:0xfbff; + valaddr_reg:x7; val_offset:292*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x7, 292*FLEN/8, x9, x1, x4) + +inst_171: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1a9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6da9; op2val:0xfbff; + valaddr_reg:x7; val_offset:294*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x7, 294*FLEN/8, x9, x1, x4) + +inst_172: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1a9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6da9; op2val:0xfbff; + valaddr_reg:x7; val_offset:296*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x7, 296*FLEN/8, x9, x1, x4) + +inst_173: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1a9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6da9; op2val:0xfbff; + valaddr_reg:x7; val_offset:298*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x7, 298*FLEN/8, x9, x1, x4) + +inst_174: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1a9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6da9; op2val:0xfbff; + valaddr_reg:x7; val_offset:300*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x7, 300*FLEN/8, x9, x1, x4) + +inst_175: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x290 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7690; op2val:0xfbff; + valaddr_reg:x7; val_offset:302*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x7, 302*FLEN/8, x9, x1, x4) + +inst_176: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x290 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7690; op2val:0xfbff; + valaddr_reg:x7; val_offset:304*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x7, 304*FLEN/8, x9, x1, x4) + +inst_177: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x290 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7690; op2val:0xfbff; + valaddr_reg:x7; val_offset:306*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x7, 306*FLEN/8, x9, x1, x4) + +inst_178: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x290 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7690; op2val:0xfbff; + valaddr_reg:x7; val_offset:308*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x7, 308*FLEN/8, x9, x1, x4) + +inst_179: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x290 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7690; op2val:0xfbff; + valaddr_reg:x7; val_offset:310*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x7, 310*FLEN/8, x9, x1, x4) + +inst_180: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0b3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74b3; op2val:0xfbff; + valaddr_reg:x7; val_offset:312*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x7, 312*FLEN/8, x9, x1, x4) + +inst_181: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0b3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74b3; op2val:0xfbff; + valaddr_reg:x7; val_offset:314*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x7, 314*FLEN/8, x9, x1, x4) + +inst_182: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0b3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74b3; op2val:0xfbff; + valaddr_reg:x7; val_offset:316*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x7, 316*FLEN/8, x9, x1, x4) + +inst_183: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0b3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74b3; op2val:0xfbff; + valaddr_reg:x7; val_offset:318*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x7, 318*FLEN/8, x9, x1, x4) + +inst_184: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0b3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74b3; op2val:0xfbff; + valaddr_reg:x7; val_offset:320*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x7, 320*FLEN/8, x9, x1, x4) + +inst_185: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2fa and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7afa; op2val:0xfbff; + valaddr_reg:x7; val_offset:322*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x7, 322*FLEN/8, x9, x1, x4) + +inst_186: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2fa and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7afa; op2val:0xfbff; + valaddr_reg:x7; val_offset:324*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x7, 324*FLEN/8, x9, x1, x4) + +inst_187: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2fa and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7afa; op2val:0xfbff; + valaddr_reg:x7; val_offset:326*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x7, 326*FLEN/8, x9, x1, x4) + +inst_188: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2fa and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7afa; op2val:0xfbff; + valaddr_reg:x7; val_offset:328*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x7, 328*FLEN/8, x9, x1, x4) + +inst_189: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2fa and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7afa; op2val:0xfbff; + valaddr_reg:x7; val_offset:330*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x7, 330*FLEN/8, x9, x1, x4) + +inst_190: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78e9; op2val:0xfbff; + valaddr_reg:x7; val_offset:332*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x7, 332*FLEN/8, x9, x1, x4) + +inst_191: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78e9; op2val:0xfbff; + valaddr_reg:x7; val_offset:334*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x7, 334*FLEN/8, x9, x1, x4) + +inst_192: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78e9; op2val:0xfbff; + valaddr_reg:x7; val_offset:336*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x7, 336*FLEN/8, x9, x1, x4) + +inst_193: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78e9; op2val:0xfbff; + valaddr_reg:x7; val_offset:338*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x7, 338*FLEN/8, x9, x1, x4) + +inst_194: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78e9; op2val:0xfbff; + valaddr_reg:x7; val_offset:340*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x7, 340*FLEN/8, x9, x1, x4) + +inst_195: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1be and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79be; op2val:0xfbff; + valaddr_reg:x7; val_offset:342*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x7, 342*FLEN/8, x9, x1, x4) + +inst_196: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1be and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79be; op2val:0xfbff; + valaddr_reg:x7; val_offset:344*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x7, 344*FLEN/8, x9, x1, x4) + +inst_197: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1be and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79be; op2val:0xfbff; + valaddr_reg:x7; val_offset:346*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x7, 346*FLEN/8, x9, x1, x4) + +inst_198: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1be and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79be; op2val:0xfbff; + valaddr_reg:x7; val_offset:348*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x7, 348*FLEN/8, x9, x1, x4) + +inst_199: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1be and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79be; op2val:0xfbff; + valaddr_reg:x7; val_offset:350*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x7, 350*FLEN/8, x9, x1, x4) + +inst_200: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b0b; op2val:0xfbff; + valaddr_reg:x7; val_offset:352*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x7, 352*FLEN/8, x9, x1, x4) + +inst_201: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b0b; op2val:0xfbff; + valaddr_reg:x7; val_offset:354*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x7, 354*FLEN/8, x9, x1, x4) + +inst_202: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b0b; op2val:0xfbff; + valaddr_reg:x7; val_offset:356*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x7, 356*FLEN/8, x9, x1, x4) + +inst_203: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b0b; op2val:0xfbff; + valaddr_reg:x7; val_offset:358*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x7, 358*FLEN/8, x9, x1, x4) + +inst_204: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b0b; op2val:0xfbff; + valaddr_reg:x7; val_offset:360*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x7, 360*FLEN/8, x9, x1, x4) + +inst_205: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x780a; op2val:0xfbff; + valaddr_reg:x7; val_offset:362*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x7, 362*FLEN/8, x9, x1, x4) + +inst_206: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x780a; op2val:0xfbff; + valaddr_reg:x7; val_offset:364*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x7, 364*FLEN/8, x9, x1, x4) + +inst_207: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x780a; op2val:0xfbff; + valaddr_reg:x7; val_offset:366*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x7, 366*FLEN/8, x9, x1, x4) + +inst_208: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x780a; op2val:0xfbff; + valaddr_reg:x7; val_offset:368*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x7, 368*FLEN/8, x9, x1, x4) + +inst_209: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x780a; op2val:0xfbff; + valaddr_reg:x7; val_offset:370*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x7, 370*FLEN/8, x9, x1, x4) + +inst_210: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74f3; op2val:0xfbff; + valaddr_reg:x7; val_offset:372*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x7, 372*FLEN/8, x9, x1, x4) + +inst_211: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74f3; op2val:0xfbff; + valaddr_reg:x7; val_offset:374*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x7, 374*FLEN/8, x9, x1, x4) + +inst_212: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74f3; op2val:0xfbff; + valaddr_reg:x7; val_offset:376*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x7, 376*FLEN/8, x9, x1, x4) + +inst_213: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74f3; op2val:0xfbff; + valaddr_reg:x7; val_offset:378*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x7, 378*FLEN/8, x9, x1, x4) + +inst_214: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74f3; op2val:0xfbff; + valaddr_reg:x7; val_offset:380*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x7, 380*FLEN/8, x9, x1, x4) + +inst_215: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0cb and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78cb; op2val:0xfbff; + valaddr_reg:x7; val_offset:382*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x7, 382*FLEN/8, x9, x1, x4) + +inst_216: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0cb and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78cb; op2val:0xfbff; + valaddr_reg:x7; val_offset:384*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x7, 384*FLEN/8, x9, x1, x4) + +inst_217: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0cb and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78cb; op2val:0xfbff; + valaddr_reg:x7; val_offset:386*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x7, 386*FLEN/8, x9, x1, x4) + +inst_218: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0cb and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78cb; op2val:0xfbff; + valaddr_reg:x7; val_offset:388*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x7, 388*FLEN/8, x9, x1, x4) + +inst_219: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0cb and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78cb; op2val:0xfbff; + valaddr_reg:x7; val_offset:390*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x7, 390*FLEN/8, x9, x1, x4) + +inst_220: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x739c; op2val:0x7bff; + valaddr_reg:x7; val_offset:392*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x7, 392*FLEN/8, x9, x1, x4) + +inst_221: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x739c; op2val:0x7bff; + valaddr_reg:x7; val_offset:394*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x7, 394*FLEN/8, x9, x1, x4) + +inst_222: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7900; op2val:0x7bff; + valaddr_reg:x7; val_offset:396*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x7, 396*FLEN/8, x9, x1, x4) + +inst_223: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x2bf and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x62bf; op2val:0x7bff; + valaddr_reg:x7; val_offset:398*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x7, 398*FLEN/8, x9, x1, x4) + +inst_224: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x2bf and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x62bf; op2val:0x7bff; + valaddr_reg:x7; val_offset:400*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x7, 400*FLEN/8, x9, x1, x4) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(30186,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(30186,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(30186,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(30186,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(30186,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(30976,32,FLEN) +NAN_BOXED(31743,32,FLEN) +test_dataset_1: +NAN_BOXED(30976,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(30976,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(30976,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(25279,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(25279,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(25279,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(25279,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(25279,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(29733,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(29733,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(29733,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(29733,32,FLEN) +NAN_BOXED(31743,32,FLEN) +test_dataset_2: +NAN_BOXED(29733,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31734,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31734,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31734,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31734,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31734,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31408,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31408,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31408,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31408,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31408,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31004,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31004,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31004,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31004,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31004,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30995,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30995,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30995,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30995,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30995,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30766,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30766,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30766,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30766,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30766,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31070,16,FLEN) +NAN_BOXED(31743,16,FLEN) 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+NAN_BOXED(31444,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31444,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31444,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31444,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31444,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28073,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28073,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28073,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28073,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28073,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30352,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30352,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30352,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30352,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30352,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29875,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29875,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29875,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29875,16,FLEN) +NAN_BOXED(64511,16,FLEN) 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+NAN_BOXED(31499,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31499,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30730,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30730,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30730,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30730,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30730,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29939,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29939,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29939,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29939,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29939,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30923,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30923,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30923,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30923,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30923,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29596,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29596,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(25279,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(25279,16,FLEN) +NAN_BOXED(31743,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x3_0: + .fill 32*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_2: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_3: + .fill 134*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fdiv_b6-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fdiv_b6-01.S new file mode 100644 index 000000000..c7e07c181 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fdiv_b6-01.S @@ -0,0 +1,444 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 05:22:24 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fdiv.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fdiv.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fdiv_b6 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fdiv_b6) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x11,test_dataset_0) +RVTEST_SIGBASE(x10,signature_x10_1) + +inst_0: +// rs1 == rd != rs2, rs1==x26, rs2==x13, rd==x26,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x26; op2:x13; dest:x26; op1val:0x0; op2val:0x8000; + valaddr_reg:x11; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x26, x26, x13, dyn, 0, 0, x11, 0*FLEN/8, x18, x10, x4) + +inst_1: +// rs1 == rs2 != rd, rs1==x9, rs2==x9, rd==x25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x9; op2:x9; dest:x25; op1val:0x0; op2val:0x0; + valaddr_reg:x11; val_offset:2*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x25, x9, x9, dyn, 32, 0, x11, 2*FLEN/8, x18, x10, x4) + +inst_2: +// rs1 == rs2 == rd, rs1==x24, rs2==x24, rd==x24,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x24; op2:x24; dest:x24; op1val:0x0; op2val:0x0; + valaddr_reg:x11; val_offset:4*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x24, x24, x24, dyn, 64, 0, x11, 4*FLEN/8, x18, x10, x4) + +inst_3: +// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==x5, rs2==x7, rd==x15,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x5; op2:x7; dest:x15; op1val:0x0; op2val:0x8000; + valaddr_reg:x11; val_offset:6*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x15, x5, x7, dyn, 96, 0, x11, 6*FLEN/8, x18, x10, x4) + +inst_4: +// rs2 == rd != rs1, rs1==x13, rs2==x1, rd==x1,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x13; op2:x1; dest:x1; op1val:0x0; op2val:0x8000; + valaddr_reg:x11; val_offset:8*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x1, x13, x1, dyn, 128, 0, x11, 8*FLEN/8, x18, x10, x4) + +inst_5: +// rs1==x31, rs2==x6, rd==x14,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x31; op2:x6; dest:x14; op1val:0x0; op2val:0x0; + valaddr_reg:x11; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x14, x31, x6, dyn, 0, 0, x11, 10*FLEN/8, x18, x10, x4) + +inst_6: +// rs1==x16, rs2==x2, rd==x22,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x16; op2:x2; dest:x22; op1val:0x0; op2val:0x0; + valaddr_reg:x11; val_offset:12*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x22, x16, x2, dyn, 32, 0, x11, 12*FLEN/8, x18, x10, x4) + +inst_7: +// rs1==x17, rs2==x20, rd==x28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x17; op2:x20; dest:x28; op1val:0x0; op2val:0x0; + valaddr_reg:x11; val_offset:14*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x28, x17, x20, dyn, 64, 0, x11, 14*FLEN/8, x18, x10, x4) + +inst_8: +// rs1==x20, rs2==x5, rd==x30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x20; op2:x5; dest:x30; op1val:0x0; op2val:0x0; + valaddr_reg:x11; val_offset:16*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x30, x20, x5, dyn, 96, 0, x11, 16*FLEN/8, x18, x10, x4) + +inst_9: +// rs1==x27, rs2==x8, rd==x5,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x27; op2:x8; dest:x5; op1val:0x0; op2val:0x0; + valaddr_reg:x11; val_offset:18*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x5, x27, x8, dyn, 128, 0, x11, 18*FLEN/8, x18, x10, x4) + +inst_10: +// rs1==x3, rs2==x31, rd==x20, +/* opcode: fdiv.h ; op1:x3; op2:x31; dest:x20; op1val:0x0; op2val:0x0; + valaddr_reg:x11; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x20, x3, x31, dyn, 0, 0, x11, 20*FLEN/8, x18, x10, x4) + +inst_11: +// rs1==x12, rs2==x29, rd==x23, +/* opcode: fdiv.h ; op1:x12; op2:x29; dest:x23; op1val:0x0; op2val:0x0; + valaddr_reg:x11; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x23, x12, x29, dyn, 0, 0, x11, 22*FLEN/8, x18, x10, x4) +RVTEST_VALBASEUPD(x13,test_dataset_1) + +inst_12: +// rs1==x7, rs2==x19, rd==x4, +/* opcode: fdiv.h ; op1:x7; op2:x19; dest:x4; op1val:0x0; op2val:0x0; + valaddr_reg:x13; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x11 +*/ +TEST_FPRR_OP(fdiv.h, x4, x7, x19, dyn, 0, 0, x13, 0*FLEN/8, x15, x10, x11) +RVTEST_SIGBASE(x5,signature_x5_0) + +inst_13: +// rs1==x8, rs2==x4, rd==x31, +/* opcode: fdiv.h ; op1:x8; op2:x4; dest:x31; op1val:0x0; op2val:0x0; + valaddr_reg:x13; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x11 +*/ +TEST_FPRR_OP(fdiv.h, x31, x8, x4, dyn, 0, 0, x13, 2*FLEN/8, x15, x5, x11) + +inst_14: +// rs1==x6, rs2==x10, rd==x7, +/* opcode: fdiv.h ; op1:x6; op2:x10; dest:x7; op1val:0x0; op2val:0x0; + valaddr_reg:x13; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x11 +*/ +TEST_FPRR_OP(fdiv.h, x7, x6, x10, dyn, 0, 0, x13, 4*FLEN/8, x15, x5, x11) + +inst_15: +// rs1==x23, rs2==x16, rd==x27, +/* opcode: fdiv.h ; op1:x23; op2:x16; dest:x27; op1val:0x0; op2val:0x0; + valaddr_reg:x13; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x11 +*/ +TEST_FPRR_OP(fdiv.h, x27, x23, x16, dyn, 0, 0, x13, 6*FLEN/8, x15, x5, x11) + +inst_16: +// rs1==x29, rs2==x28, rd==x3, +/* opcode: fdiv.h ; op1:x29; op2:x28; dest:x3; op1val:0x0; op2val:0x0; + valaddr_reg:x13; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x11 +*/ +TEST_FPRR_OP(fdiv.h, x3, x29, x28, dyn, 0, 0, x13, 8*FLEN/8, x15, x5, x11) + +inst_17: +// rs1==x19, rs2==x0, rd==x29, +/* opcode: fdiv.h ; op1:x19; op2:x0; dest:x29; op1val:0x0; op2val:0x0; + valaddr_reg:x13; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x11 +*/ +TEST_FPRR_OP(fdiv.h, x29, x19, x0, dyn, 0, 0, x13, 10*FLEN/8, x15, x5, x11) + +inst_18: +// rs1==x28, rs2==x3, rd==x9, +/* opcode: fdiv.h ; op1:x28; op2:x3; dest:x9; op1val:0x0; op2val:0x0; + valaddr_reg:x13; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x11 +*/ +TEST_FPRR_OP(fdiv.h, x9, x28, x3, dyn, 0, 0, x13, 12*FLEN/8, x15, x5, x11) + +inst_19: +// rs1==x0, rs2==x27, rd==x17, +/* opcode: fdiv.h ; op1:x0; op2:x27; dest:x17; op1val:0x0; op2val:0x0; + valaddr_reg:x13; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x11 +*/ +TEST_FPRR_OP(fdiv.h, x17, x0, x27, dyn, 0, 0, x13, 14*FLEN/8, x15, x5, x11) + +inst_20: +// rs1==x22, rs2==x26, rd==x16, +/* opcode: fdiv.h ; op1:x22; op2:x26; dest:x16; op1val:0x0; op2val:0x0; + valaddr_reg:x13; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x11 +*/ +TEST_FPRR_OP(fdiv.h, x16, x22, x26, dyn, 0, 0, x13, 16*FLEN/8, x15, x5, x11) + +inst_21: +// rs1==x10, rs2==x12, rd==x18, +/* opcode: fdiv.h ; op1:x10; op2:x12; dest:x18; op1val:0x0; op2val:0x0; + valaddr_reg:x13; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x11 +*/ +TEST_FPRR_OP(fdiv.h, x18, x10, x12, dyn, 0, 0, x13, 18*FLEN/8, x15, x5, x11) + +inst_22: +// rs1==x14, rs2==x17, rd==x8, +/* opcode: fdiv.h ; op1:x14; op2:x17; dest:x8; op1val:0x0; op2val:0x0; + valaddr_reg:x13; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x11 +*/ +TEST_FPRR_OP(fdiv.h, x8, x14, x17, dyn, 0, 0, x13, 20*FLEN/8, x15, x5, x11) + +inst_23: +// rs1==x4, rs2==x21, rd==x19, +/* opcode: fdiv.h ; op1:x4; op2:x21; dest:x19; op1val:0x0; op2val:0x0; + valaddr_reg:x13; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x11 +*/ +TEST_FPRR_OP(fdiv.h, x19, x4, x21, dyn, 0, 0, x13, 22*FLEN/8, x15, x5, x11) + +inst_24: +// rs1==x1, rs2==x30, rd==x2, +/* opcode: fdiv.h ; op1:x1; op2:x30; dest:x2; op1val:0x0; op2val:0x0; + valaddr_reg:x13; val_offset:24*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x11 +*/ +TEST_FPRR_OP(fdiv.h, x2, x1, x30, dyn, 0, 0, x13, 24*FLEN/8, x15, x5, x11) +RVTEST_VALBASEUPD(x4,test_dataset_2) + +inst_25: +// rs1==x21, rs2==x25, rd==x13, +/* opcode: fdiv.h ; op1:x21; op2:x25; dest:x13; op1val:0x0; op2val:0x0; + valaddr_reg:x4; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x11 +*/ +TEST_FPRR_OP(fdiv.h, x13, x21, x25, dyn, 0, 0, x4, 0*FLEN/8, x7, x5, x11) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_26: +// rs1==x30, rs2==x23, rd==x10, +/* opcode: fdiv.h ; op1:x30; op2:x23; dest:x10; op1val:0x0; op2val:0x0; + valaddr_reg:x4; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x10, x30, x23, dyn, 0, 0, x4, 2*FLEN/8, x7, x1, x3) + +inst_27: +// rs1==x18, rs2==x11, rd==x12, +/* opcode: fdiv.h ; op1:x18; op2:x11; dest:x12; op1val:0x0; op2val:0x0; + valaddr_reg:x4; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x12, x18, x11, dyn, 0, 0, x4, 4*FLEN/8, x7, x1, x3) + +inst_28: +// rs1==x2, rs2==x14, rd==x21, +/* opcode: fdiv.h ; op1:x2; op2:x14; dest:x21; op1val:0x0; op2val:0x0; + valaddr_reg:x4; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x21, x2, x14, dyn, 0, 0, x4, 6*FLEN/8, x7, x1, x3) + +inst_29: +// rs1==x11, rs2==x18, rd==x0, +/* opcode: fdiv.h ; op1:x11; op2:x18; dest:x0; op1val:0x0; op2val:0x0; + valaddr_reg:x4; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x0, x11, x18, dyn, 0, 0, x4, 8*FLEN/8, x7, x1, x3) + +inst_30: +// rs1==x25, rs2==x15, rd==x6, +/* opcode: fdiv.h ; op1:x25; op2:x15; dest:x6; op1val:0x0; op2val:0x0; + valaddr_reg:x4; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x6, x25, x15, dyn, 0, 0, x4, 10*FLEN/8, x7, x1, x3) + +inst_31: +// rs1==x15, rs2==x22, rd==x11, +/* opcode: fdiv.h ; op1:x15; op2:x22; dest:x11; op1val:0x0; op2val:0x0; + valaddr_reg:x4; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x11, x15, x22, dyn, 0, 0, x4, 12*FLEN/8, x7, x1, x3) + +inst_32: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x8000; + valaddr_reg:x4; val_offset:14*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x4, 14*FLEN/8, x7, x1, x3) + +inst_33: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x8000; + valaddr_reg:x4; val_offset:16*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x4, 16*FLEN/8, x7, x1, x3) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +test_dataset_1: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +test_dataset_2: +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32768,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x10_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x10_1: + .fill 26*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x5_0: + .fill 26*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_0: + .fill 16*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fdiv_b7-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fdiv_b7-01.S new file mode 100644 index 000000000..ab096665a --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fdiv_b7-01.S @@ -0,0 +1,694 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 05:22:24 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fdiv.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fdiv.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fdiv_b7 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fdiv_b7) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x6,test_dataset_0) +RVTEST_SIGBASE(x2,signature_x2_1) + +inst_0: +// rs1 == rd != rs2, rs1==x18, rs2==x4, rd==x18,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x18; op2:x4; dest:x18; op1val:0x739c; op2val:0x7bff; + valaddr_reg:x6; val_offset:0*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fdiv.h, x18, x18, x4, dyn, 96, 0, x6, 0*FLEN/8, x14, x2, x5) + +inst_1: +// rs1 == rs2 != rd, rs1==x15, rs2==x15, rd==x23,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ea and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x15; op2:x15; dest:x23; op1val:0x75ea; op2val:0x75ea; + valaddr_reg:x6; val_offset:2*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fdiv.h, x23, x15, x15, dyn, 96, 0, x6, 2*FLEN/8, x14, x2, x5) + +inst_2: +// rs1 == rs2 == rd, rs1==x9, rs2==x9, rd==x9,fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x9; op2:x9; dest:x9; op1val:0x7900; op2val:0x7900; + valaddr_reg:x6; val_offset:4*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fdiv.h, x9, x9, x9, dyn, 96, 0, x6, 4*FLEN/8, x14, x2, x5) + +inst_3: +// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==x0, rs2==x24, rd==x22,fs1 == 0 and fe1 == 0x18 and fm1 == 0x2bf and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x0; op2:x24; dest:x22; op1val:0x0; op2val:0x7bff; + valaddr_reg:x6; val_offset:6*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fdiv.h, x22, x0, x24, dyn, 96, 0, x6, 6*FLEN/8, x14, x2, x5) + +inst_4: +// rs2 == rd != rs1, rs1==x1, rs2==x8, rd==x8,fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x1; op2:x8; dest:x8; op1val:0x7425; op2val:0x7bff; + valaddr_reg:x6; val_offset:8*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fdiv.h, x8, x1, x8, dyn, 96, 0, x6, 8*FLEN/8, x14, x2, x5) + +inst_5: +// rs1==x22, rs2==x10, rd==x19,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x22; op2:x10; dest:x19; op1val:0x7bf6; op2val:0x7bff; + valaddr_reg:x6; val_offset:10*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fdiv.h, x19, x22, x10, dyn, 96, 0, x6, 10*FLEN/8, x14, x2, x5) + +inst_6: +// rs1==x29, rs2==x12, rd==x26,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x29; op2:x12; dest:x26; op1val:0x7ab0; op2val:0x7bff; + valaddr_reg:x6; val_offset:12*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fdiv.h, x26, x29, x12, dyn, 96, 0, x6, 12*FLEN/8, x14, x2, x5) + +inst_7: +// rs1==x20, rs2==x30, rd==x16,fs1 == 0 and fe1 == 0x1e and fm1 == 0x11c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x20; op2:x30; dest:x16; op1val:0x791c; op2val:0x7bff; + valaddr_reg:x6; val_offset:14*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fdiv.h, x16, x20, x30, dyn, 96, 0, x6, 14*FLEN/8, x14, x2, x5) + +inst_8: +// rs1==x3, rs2==x29, rd==x24,fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x3; op2:x29; dest:x24; op1val:0x7913; op2val:0x7bff; + valaddr_reg:x6; val_offset:16*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fdiv.h, x24, x3, x29, dyn, 96, 0, x6, 16*FLEN/8, x14, x2, x5) + +inst_9: +// rs1==x7, rs2==x21, rd==x13,fs1 == 0 and fe1 == 0x1e and fm1 == 0x02e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x7; op2:x21; dest:x13; op1val:0x782e; op2val:0x7bff; + valaddr_reg:x6; val_offset:18*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fdiv.h, x13, x7, x21, dyn, 96, 0, x6, 18*FLEN/8, x14, x2, x5) + +inst_10: +// rs1==x25, rs2==x19, rd==x20,fs1 == 0 and fe1 == 0x1e and fm1 == 0x15e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x25; op2:x19; dest:x20; op1val:0x795e; op2val:0x7bff; + valaddr_reg:x6; val_offset:20*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fdiv.h, x20, x25, x19, dyn, 96, 0, x6, 20*FLEN/8, x14, x2, x5) + +inst_11: +// rs1==x10, rs2==x11, rd==x7,fs1 == 0 and fe1 == 0x1e and fm1 == 0x210 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x10; op2:x11; dest:x7; op1val:0x7a10; op2val:0x7bff; + valaddr_reg:x6; val_offset:22*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fdiv.h, x7, x10, x11, dyn, 96, 0, x6, 22*FLEN/8, x14, x2, x5) +RVTEST_VALBASEUPD(x7,test_dataset_1) + +inst_12: +// rs1==x13, rs2==x0, rd==x12,fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x13; op2:x0; dest:x12; op1val:0x74d1; op2val:0x0; + valaddr_reg:x7; val_offset:0*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fdiv.h, x12, x13, x0, dyn, 96, 0, x7, 0*FLEN/8, x10, x2, x5) + +inst_13: +// rs1==x11, rs2==x3, rd==x28,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2eb and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x11; op2:x3; dest:x28; op1val:0x7aeb; op2val:0x7bff; + valaddr_reg:x7; val_offset:2*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fdiv.h, x28, x11, x3, dyn, 96, 0, x7, 2*FLEN/8, x10, x2, x5) + +inst_14: +// rs1==x4, rs2==x22, rd==x27,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1bf and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x4; op2:x22; dest:x27; op1val:0x79bf; op2val:0x7bff; + valaddr_reg:x7; val_offset:4*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fdiv.h, x27, x4, x22, dyn, 96, 0, x7, 4*FLEN/8, x10, x2, x5) + +inst_15: +// rs1==x30, rs2==x6, rd==x15,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x6; dest:x15; op1val:0x79b5; op2val:0x7bff; + valaddr_reg:x7; val_offset:6*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fdiv.h, x15, x30, x6, dyn, 96, 0, x7, 6*FLEN/8, x10, x2, x8) +RVTEST_SIGBASE(x9,signature_x9_0) + +inst_16: +// rs1==x26, rs2==x27, rd==x1,fs1 == 0 and fe1 == 0x1d and fm1 == 0x251 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x26; op2:x27; dest:x1; op1val:0x7651; op2val:0x7bff; + valaddr_reg:x7; val_offset:8*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fdiv.h, x1, x26, x27, dyn, 96, 0, x7, 8*FLEN/8, x10, x9, x8) + +inst_17: +// rs1==x6, rs2==x17, rd==x2,fs1 == 0 and fe1 == 0x1d and fm1 == 0x31c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x6; op2:x17; dest:x2; op1val:0x771c; op2val:0x7bff; + valaddr_reg:x7; val_offset:10*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fdiv.h, x2, x6, x17, dyn, 96, 0, x7, 10*FLEN/8, x10, x9, x8) + +inst_18: +// rs1==x17, rs2==x14, rd==x0,fs1 == 0 and fe1 == 0x1e and fm1 == 0x307 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x17; op2:x14; dest:x0; op1val:0x7b07; op2val:0x7bff; + valaddr_reg:x7; val_offset:12*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fdiv.h, x0, x17, x14, dyn, 96, 0, x7, 12*FLEN/8, x10, x9, x8) + +inst_19: +// rs1==x5, rs2==x20, rd==x4,fs1 == 0 and fe1 == 0x1c and fm1 == 0x059 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x5; op2:x20; dest:x4; op1val:0x7059; op2val:0x7bff; + valaddr_reg:x7; val_offset:14*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fdiv.h, x4, x5, x20, dyn, 96, 0, x7, 14*FLEN/8, x10, x9, x8) + +inst_20: +// rs1==x31, rs2==x28, rd==x11,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x31; op2:x28; dest:x11; op1val:0x7bb8; op2val:0x7bff; + valaddr_reg:x7; val_offset:16*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fdiv.h, x11, x31, x28, dyn, 96, 0, x7, 16*FLEN/8, x10, x9, x8) + +inst_21: +// rs1==x27, rs2==x23, rd==x14,fs1 == 0 and fe1 == 0x1e and fm1 == 0x102 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x27; op2:x23; dest:x14; op1val:0x7902; op2val:0x7bff; + valaddr_reg:x7; val_offset:18*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fdiv.h, x14, x27, x23, dyn, 96, 0, x7, 18*FLEN/8, x10, x9, x8) + +inst_22: +// rs1==x24, rs2==x5, rd==x29,fs1 == 0 and fe1 == 0x1e and fm1 == 0x00e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x24; op2:x5; dest:x29; op1val:0x780e; op2val:0x7bff; + valaddr_reg:x7; val_offset:20*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fdiv.h, x29, x24, x5, dyn, 96, 0, x7, 20*FLEN/8, x10, x9, x8) + +inst_23: +// rs1==x21, rs2==x18, rd==x17,fs1 == 0 and fe1 == 0x1d and fm1 == 0x19c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x21; op2:x18; dest:x17; op1val:0x759c; op2val:0x7bff; + valaddr_reg:x7; val_offset:22*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fdiv.h, x17, x21, x18, dyn, 96, 0, x7, 22*FLEN/8, x10, x9, x8) +RVTEST_VALBASEUPD(x4,test_dataset_2) + +inst_24: +// rs1==x28, rs2==x16, rd==x25,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ab and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x28; op2:x16; dest:x25; op1val:0x78ab; op2val:0x7bff; + valaddr_reg:x4; val_offset:0*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fdiv.h, x25, x28, x16, dyn, 96, 0, x4, 0*FLEN/8, x11, x9, x8) + +inst_25: +// rs1==x16, rs2==x7, rd==x5,fs1 == 0 and fe1 == 0x1e and fm1 == 0x174 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x16; op2:x7; dest:x5; op1val:0x7974; op2val:0x7bff; + valaddr_reg:x4; val_offset:2*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fdiv.h, x5, x16, x7, dyn, 96, 0, x4, 2*FLEN/8, x11, x9, x8) + +inst_26: +// rs1==x12, rs2==x1, rd==x6,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x12; op2:x1; dest:x6; op1val:0x7ad9; op2val:0x7bff; + valaddr_reg:x4; val_offset:4*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fdiv.h, x6, x12, x1, dyn, 96, 0, x4, 4*FLEN/8, x11, x9, x8) + +inst_27: +// rs1==x14, rs2==x2, rd==x3,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x14; op2:x2; dest:x3; op1val:0x7ae1; op2val:0x7bff; + valaddr_reg:x4; val_offset:6*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fdiv.h, x3, x14, x2, dyn, 96, 0, x4, 6*FLEN/8, x11, x9, x8) + +inst_28: +// rs1==x23, rs2==x31, rd==x10,fs1 == 0 and fe1 == 0x1e and fm1 == 0x33b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x23; op2:x31; dest:x10; op1val:0x7b3b; op2val:0x7bff; + valaddr_reg:x4; val_offset:8*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x10, x23, x31, dyn, 96, 0, x4, 8*FLEN/8, x11, x9, x3) + +inst_29: +// rs1==x8, rs2==x25, rd==x30,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x8; op2:x25; dest:x30; op1val:0x7aa6; op2val:0x7bff; + valaddr_reg:x4; val_offset:10*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x30, x8, x25, dyn, 96, 0, x4, 10*FLEN/8, x11, x9, x3) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_30: +// rs1==x19, rs2==x13, rd==x21,fs1 == 0 and fe1 == 0x1d and fm1 == 0x08e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x19; op2:x13; dest:x21; op1val:0x748e; op2val:0x7bff; + valaddr_reg:x4; val_offset:12*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x21, x19, x13, dyn, 96, 0, x4, 12*FLEN/8, x11, x1, x3) + +inst_31: +// rs1==x2, rs2==x26, rd==x31,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x2; op2:x26; dest:x31; op1val:0x7ad4; op2val:0x7bff; + valaddr_reg:x4; val_offset:14*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x31, x2, x26, dyn, 96, 0, x4, 14*FLEN/8, x11, x1, x3) + +inst_32: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1a9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6da9; op2val:0x7bff; + valaddr_reg:x4; val_offset:16*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x4, 16*FLEN/8, x11, x1, x3) + +inst_33: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x290 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7690; op2val:0x7bff; + valaddr_reg:x4; val_offset:18*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x4, 18*FLEN/8, x11, x1, x3) + +inst_34: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0b3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74b3; op2val:0x7bff; + valaddr_reg:x4; val_offset:20*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x4, 20*FLEN/8, x11, x1, x3) + +inst_35: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2fa and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7afa; op2val:0x7bff; + valaddr_reg:x4; val_offset:22*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x4, 22*FLEN/8, x11, x1, x3) + +inst_36: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78e9; op2val:0x7bff; + valaddr_reg:x4; val_offset:24*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x4, 24*FLEN/8, x11, x1, x3) + +inst_37: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1be and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79be; op2val:0x7bff; + valaddr_reg:x4; val_offset:26*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x4, 26*FLEN/8, x11, x1, x3) + +inst_38: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b0b; op2val:0x7bff; + valaddr_reg:x4; val_offset:28*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x4, 28*FLEN/8, x11, x1, x3) + +inst_39: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x780a; op2val:0x7bff; + valaddr_reg:x4; val_offset:30*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x4, 30*FLEN/8, x11, x1, x3) + +inst_40: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f3 and fs2 == 0 and fe2 == 0x17 and fm2 == 0x0f3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74f3; op2val:0x5cf3; + valaddr_reg:x4; val_offset:32*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x4, 32*FLEN/8, x11, x1, x3) + +inst_41: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0cb and fs2 == 0 and fe2 == 0x18 and fm2 == 0x0cb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78cb; op2val:0x60cb; + valaddr_reg:x4; val_offset:34*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x4, 34*FLEN/8, x11, x1, x3) + +inst_42: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x250 and fs2 == 0 and fe2 == 0x16 and fm2 == 0x250 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7250; op2val:0x5a50; + valaddr_reg:x4; val_offset:36*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x4, 36*FLEN/8, x11, x1, x3) + +inst_43: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e1 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x0e1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78e1; op2val:0x60e1; + valaddr_reg:x4; val_offset:38*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x4, 38*FLEN/8, x11, x1, x3) + +inst_44: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x16e and fs2 == 0 and fe2 == 0x14 and fm2 == 0x16e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x696e; op2val:0x516e; + valaddr_reg:x4; val_offset:40*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x4, 40*FLEN/8, x11, x1, x3) + +inst_45: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x104 and fs2 == 0 and fe2 == 0x17 and fm2 == 0x104 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7504; op2val:0x5d04; + valaddr_reg:x4; val_offset:42*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x4, 42*FLEN/8, x11, x1, x3) + +inst_46: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32b and fs2 == 0 and fe2 == 0x18 and fm2 == 0x32b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b2b; op2val:0x632b; + valaddr_reg:x4; val_offset:44*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x4, 44*FLEN/8, x11, x1, x3) + +inst_47: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x35c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x775c; op2val:0x7bff; + valaddr_reg:x4; val_offset:46*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x4, 46*FLEN/8, x11, x1, x3) + +inst_48: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x126 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7926; op2val:0x7bff; + valaddr_reg:x4; val_offset:48*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x4, 48*FLEN/8, x11, x1, x3) + +inst_49: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x078 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7878; op2val:0x7bff; + valaddr_reg:x4; val_offset:50*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x4, 50*FLEN/8, x11, x1, x3) + +inst_50: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x385 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b85; op2val:0x7bff; + valaddr_reg:x4; val_offset:52*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x4, 52*FLEN/8, x11, x1, x3) + +inst_51: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x76e5; op2val:0x7bff; + valaddr_reg:x4; val_offset:54*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x4, 54*FLEN/8, x11, x1, x3) + +inst_52: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x399 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7399; op2val:0x7bff; + valaddr_reg:x4; val_offset:56*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x4, 56*FLEN/8, x11, x1, x3) + +inst_53: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bd1; op2val:0x7bff; + valaddr_reg:x4; val_offset:58*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x4, 58*FLEN/8, x11, x1, x3) + +inst_54: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ea and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x75ea; op2val:0x7bff; + valaddr_reg:x4; val_offset:60*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x4, 60*FLEN/8, x11, x1, x3) + +inst_55: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7900; op2val:0x7bff; + valaddr_reg:x4; val_offset:62*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x4, 62*FLEN/8, x11, x1, x3) + +inst_56: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x2bf and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x62bf; op2val:0x7bff; + valaddr_reg:x4; val_offset:64*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x4, 64*FLEN/8, x11, x1, x3) + +inst_57: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74d1; op2val:0x7bff; + valaddr_reg:x4; val_offset:66*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x4, 66*FLEN/8, x11, x1, x3) + +inst_58: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x307 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b07; op2val:0x7bff; + valaddr_reg:x4; val_offset:68*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x4, 68*FLEN/8, x11, x1, x3) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(30186,32,FLEN) +NAN_BOXED(30186,32,FLEN) +NAN_BOXED(30976,32,FLEN) +NAN_BOXED(30976,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(29733,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(31734,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(31408,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(31004,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(30995,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(30766,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(31070,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(31248,32,FLEN) +NAN_BOXED(31743,32,FLEN) +test_dataset_1: +NAN_BOXED(29905,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31467,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(31167,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(31157,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(30289,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(30492,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(31495,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(28761,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(31672,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(30978,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(30734,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(30108,32,FLEN) +NAN_BOXED(31743,32,FLEN) +test_dataset_2: +NAN_BOXED(30891,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31092,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31449,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31457,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31547,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31398,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29838,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31444,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(28073,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30352,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29875,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31482,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30953,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31166,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31499,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30730,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29939,16,FLEN) +NAN_BOXED(23795,16,FLEN) +NAN_BOXED(30923,16,FLEN) +NAN_BOXED(24779,16,FLEN) +NAN_BOXED(29264,16,FLEN) +NAN_BOXED(23120,16,FLEN) +NAN_BOXED(30945,16,FLEN) +NAN_BOXED(24801,16,FLEN) +NAN_BOXED(26990,16,FLEN) +NAN_BOXED(20846,16,FLEN) +NAN_BOXED(29956,16,FLEN) +NAN_BOXED(23812,16,FLEN) +NAN_BOXED(31531,16,FLEN) +NAN_BOXED(25387,16,FLEN) +NAN_BOXED(30556,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31014,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30840,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31621,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30437,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29593,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31697,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30186,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(25279,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29905,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31495,16,FLEN) +NAN_BOXED(31743,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x2_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_1: + .fill 32*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x9_0: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_0: + .fill 58*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fdiv_b8-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fdiv_b8-01.S new file mode 100644 index 000000000..fef710926 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fdiv_b8-01.S @@ -0,0 +1,16964 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 05:22:24 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fdiv.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fdiv.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fdiv_b8 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fdiv_b8) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x17,test_dataset_0) +RVTEST_SIGBASE(x5,signature_x5_1) + +inst_0: +// rs1 == rd != rs2, rs1==x2, rs2==x14, rd==x2,fs1 == 0 and fe1 == 0x0e and fm1 == 0x218 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x2; op2:x14; dest:x2; op1val:0x3a18; op2val:0x7bff; + valaddr_reg:x17; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fdiv.h, x2, x2, x14, dyn, 0, 0, x17, 0*FLEN/8, x18, x5, x9) + +inst_1: +// rs1 == rs2 != rd, rs1==x30, rs2==x30, rd==x3,fs1 == 0 and fe1 == 0x0e and fm1 == 0x218 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x30; dest:x3; op1val:0x3a18; op2val:0x3a18; + valaddr_reg:x17; val_offset:2*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fdiv.h, x3, x30, x30, dyn, 32, 0, x17, 2*FLEN/8, x18, x5, x9) + +inst_2: +// rs1 == rs2 == rd, rs1==x10, rs2==x10, rd==x10,fs1 == 0 and fe1 == 0x0e and fm1 == 0x218 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x10; op2:x10; dest:x10; op1val:0x3a18; op2val:0x3a18; + valaddr_reg:x17; val_offset:4*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fdiv.h, x10, x10, x10, dyn, 64, 0, x17, 4*FLEN/8, x18, x5, x9) + +inst_3: +// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==x29, rs2==x23, rd==x30,fs1 == 0 and fe1 == 0x0e and fm1 == 0x218 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x29; op2:x23; dest:x30; op1val:0x3a18; op2val:0x7bff; + valaddr_reg:x17; val_offset:6*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fdiv.h, x30, x29, x23, dyn, 96, 0, x17, 6*FLEN/8, x18, x5, x9) + +inst_4: +// rs2 == rd != rs1, rs1==x24, rs2==x28, rd==x28,fs1 == 0 and fe1 == 0x0e and fm1 == 0x218 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x24; op2:x28; dest:x28; op1val:0x3a18; op2val:0x7bff; + valaddr_reg:x17; val_offset:8*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fdiv.h, x28, x24, x28, dyn, 128, 0, x17, 8*FLEN/8, x18, x5, x9) + +inst_5: +// rs1==x25, rs2==x19, rd==x22,fs1 == 0 and fe1 == 0x0e and fm1 == 0x10a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x25; op2:x19; dest:x22; op1val:0x390a; op2val:0x7bff; + valaddr_reg:x17; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fdiv.h, x22, x25, x19, dyn, 0, 0, x17, 10*FLEN/8, x18, x5, x9) + +inst_6: +// rs1==x7, rs2==x26, rd==x11,fs1 == 0 and fe1 == 0x0e and fm1 == 0x10a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x7; op2:x26; dest:x11; op1val:0x390a; op2val:0x7bff; + valaddr_reg:x17; val_offset:12*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fdiv.h, x11, x7, x26, dyn, 32, 0, x17, 12*FLEN/8, x18, x5, x9) + +inst_7: +// rs1==x6, rs2==x8, rd==x12,fs1 == 0 and fe1 == 0x0e and fm1 == 0x10a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x6; op2:x8; dest:x12; op1val:0x390a; op2val:0x7bff; + valaddr_reg:x17; val_offset:14*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fdiv.h, x12, x6, x8, dyn, 64, 0, x17, 14*FLEN/8, x18, x5, x9) + +inst_8: +// rs1==x16, rs2==x4, rd==x14,fs1 == 0 and fe1 == 0x0e and fm1 == 0x10a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x16; op2:x4; dest:x14; op1val:0x390a; op2val:0x7bff; + valaddr_reg:x17; val_offset:16*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fdiv.h, x14, x16, x4, dyn, 96, 0, x17, 16*FLEN/8, x18, x5, x9) + +inst_9: +// rs1==x15, rs2==x7, rd==x23,fs1 == 0 and fe1 == 0x0e and fm1 == 0x10a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x15; op2:x7; dest:x23; op1val:0x390a; op2val:0x7bff; + valaddr_reg:x17; val_offset:18*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fdiv.h, x23, x15, x7, dyn, 128, 0, x17, 18*FLEN/8, x18, x5, x9) + +inst_10: +// rs1==x1, rs2==x15, rd==x13,fs1 == 0 and fe1 == 0x0d and fm1 == 0x1fd and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x1; op2:x15; dest:x13; op1val:0x35fd; op2val:0x7bff; + valaddr_reg:x17; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fdiv.h, x13, x1, x15, dyn, 0, 0, x17, 20*FLEN/8, x18, x5, x9) +RVTEST_VALBASEUPD(x1,test_dataset_1) + +inst_11: +// rs1==x27, rs2==x3, rd==x8,fs1 == 0 and fe1 == 0x0d and fm1 == 0x1fd and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x27; op2:x3; dest:x8; op1val:0x35fd; op2val:0x7bff; + valaddr_reg:x1; val_offset:0*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fdiv.h, x8, x27, x3, dyn, 32, 0, x1, 0*FLEN/8, x7, x5, x9) + +inst_12: +// rs1==x20, rs2==x27, rd==x4,fs1 == 0 and fe1 == 0x0d and fm1 == 0x1fd and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x20; op2:x27; dest:x4; op1val:0x35fd; op2val:0x7bff; + valaddr_reg:x1; val_offset:2*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fdiv.h, x4, x20, x27, dyn, 64, 0, x1, 2*FLEN/8, x7, x5, x9) + +inst_13: +// rs1==x9, rs2==x17, rd==x26,fs1 == 0 and fe1 == 0x0d and fm1 == 0x1fd and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x9; op2:x17; dest:x26; op1val:0x35fd; op2val:0x7bff; + valaddr_reg:x1; val_offset:4*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x26, x9, x17, dyn, 96, 0, x1, 4*FLEN/8, x7, x5, x3) +RVTEST_SIGBASE(x2,signature_x2_0) + +inst_14: +// rs1==x22, rs2==x5, rd==x31,fs1 == 0 and fe1 == 0x0d and fm1 == 0x1fd and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x22; op2:x5; dest:x31; op1val:0x35fd; op2val:0x7bff; + valaddr_reg:x1; val_offset:6*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x31, x22, x5, dyn, 128, 0, x1, 6*FLEN/8, x7, x2, x3) + +inst_15: +// rs1==x17, rs2==x11, rd==x19,fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x17; op2:x11; dest:x19; op1val:0x3be5; op2val:0x7bff; + valaddr_reg:x1; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x19, x17, x11, dyn, 0, 0, x1, 8*FLEN/8, x7, x2, x3) + +inst_16: +// rs1==x8, rs2==x16, rd==x29,fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x8; op2:x16; dest:x29; op1val:0x3be5; op2val:0x7bff; + valaddr_reg:x1; val_offset:10*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x29, x8, x16, dyn, 32, 0, x1, 10*FLEN/8, x7, x2, x3) + +inst_17: +// rs1==x13, rs2==x12, rd==x9,fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x13; op2:x12; dest:x9; op1val:0x3be5; op2val:0x7bff; + valaddr_reg:x1; val_offset:12*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x9, x13, x12, dyn, 64, 0, x1, 12*FLEN/8, x7, x2, x3) + +inst_18: +// rs1==x31, rs2==x24, rd==x6,fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x31; op2:x24; dest:x6; op1val:0x3be5; op2val:0x7bff; + valaddr_reg:x1; val_offset:14*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x6, x31, x24, dyn, 96, 0, x1, 14*FLEN/8, x7, x2, x3) + +inst_19: +// rs1==x14, rs2==x13, rd==x24,fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x14; op2:x13; dest:x24; op1val:0x3be5; op2val:0x7bff; + valaddr_reg:x1; val_offset:16*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x24, x14, x13, dyn, 128, 0, x1, 16*FLEN/8, x7, x2, x3) + +inst_20: +// rs1==x4, rs2==x20, rd==x16,fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ec and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x4; op2:x20; dest:x16; op1val:0x39ec; op2val:0x7bff; + valaddr_reg:x1; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x16, x4, x20, dyn, 0, 0, x1, 18*FLEN/8, x7, x2, x3) + +inst_21: +// rs1==x23, rs2==x21, rd==x25,fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ec and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x23; op2:x21; dest:x25; op1val:0x39ec; op2val:0x7bff; + valaddr_reg:x1; val_offset:20*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x25, x23, x21, dyn, 32, 0, x1, 20*FLEN/8, x7, x2, x3) + +inst_22: +// rs1==x11, rs2==x31, rd==x27,fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ec and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x11; op2:x31; dest:x27; op1val:0x39ec; op2val:0x7bff; + valaddr_reg:x1; val_offset:22*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x27, x11, x31, dyn, 64, 0, x1, 22*FLEN/8, x7, x2, x3) + +inst_23: +// rs1==x12, rs2==x25, rd==x21,fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ec and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x12; op2:x25; dest:x21; op1val:0x39ec; op2val:0x7bff; + valaddr_reg:x1; val_offset:24*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x21, x12, x25, dyn, 96, 0, x1, 24*FLEN/8, x7, x2, x3) + +inst_24: +// rs1==x18, rs2==x0, rd==x20,fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ec and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x18; op2:x0; dest:x20; op1val:0x39ec; op2val:0x0; + valaddr_reg:x1; val_offset:26*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x20, x18, x0, dyn, 128, 0, x1, 26*FLEN/8, x7, x2, x3) +RVTEST_VALBASEUPD(x8,test_dataset_2) + +inst_25: +// rs1==x19, rs2==x6, rd==x5,fs1 == 0 and fe1 == 0x07 and fm1 == 0x075 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x075 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x19; op2:x6; dest:x5; op1val:0x1c75; op2val:0x7875; + valaddr_reg:x8; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x5, x19, x6, dyn, 0, 0, x8, 0*FLEN/8, x10, x2, x3) + +inst_26: +// rs1==x21, rs2==x18, rd==x0,fs1 == 0 and fe1 == 0x07 and fm1 == 0x075 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x075 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x21; op2:x18; dest:x0; op1val:0x1c75; op2val:0x7875; + valaddr_reg:x8; val_offset:2*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x0, x21, x18, dyn, 32, 0, x8, 2*FLEN/8, x10, x2, x3) + +inst_27: +// rs1==x26, rs2==x1, rd==x15,fs1 == 0 and fe1 == 0x07 and fm1 == 0x075 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x075 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x26; op2:x1; dest:x15; op1val:0x1c75; op2val:0x7875; + valaddr_reg:x8; val_offset:4*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fdiv.h, x15, x26, x1, dyn, 64, 0, x8, 4*FLEN/8, x10, x2, x3) + +inst_28: +// rs1==x5, rs2==x22, rd==x1,fs1 == 0 and fe1 == 0x07 and fm1 == 0x075 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x075 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x5; op2:x22; dest:x1; op1val:0x1c75; op2val:0x7875; + valaddr_reg:x8; val_offset:6*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x1, x5, x22, dyn, 96, 0, x8, 6*FLEN/8, x10, x2, x4) + +inst_29: +// rs1==x0, rs2==x29, rd==x7,fs1 == 0 and fe1 == 0x07 and fm1 == 0x075 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x075 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x0; op2:x29; dest:x7; op1val:0x0; op2val:0x7875; + valaddr_reg:x8; val_offset:8*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x7, x0, x29, dyn, 128, 0, x8, 8*FLEN/8, x10, x2, x4) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_30: +// rs1==x3, rs2==x2, rd==x18,fs1 == 0 and fe1 == 0x0c and fm1 == 0x13b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x3; op2:x2; dest:x18; op1val:0x313b; op2val:0x7bff; + valaddr_reg:x8; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x18, x3, x2, dyn, 0, 0, x8, 10*FLEN/8, x10, x1, x4) + +inst_31: +// rs1==x28, rs2==x9, rd==x17,fs1 == 0 and fe1 == 0x0c and fm1 == 0x13b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x28; op2:x9; dest:x17; op1val:0x313b; op2val:0x7bff; + valaddr_reg:x8; val_offset:12*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x17, x28, x9, dyn, 32, 0, x8, 12*FLEN/8, x10, x1, x4) + +inst_32: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x13b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x313b; op2val:0x7bff; + valaddr_reg:x8; val_offset:14*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 14*FLEN/8, x10, x1, x4) + +inst_33: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x13b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x313b; op2val:0x7bff; + valaddr_reg:x8; val_offset:16*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 16*FLEN/8, x10, x1, x4) + +inst_34: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x13b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x313b; op2val:0x7bff; + valaddr_reg:x8; val_offset:18*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 18*FLEN/8, x10, x1, x4) + +inst_35: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1c6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x35c6; op2val:0x7bff; + valaddr_reg:x8; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 20*FLEN/8, x10, x1, x4) + +inst_36: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1c6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x35c6; op2val:0x7bff; + valaddr_reg:x8; val_offset:22*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 22*FLEN/8, x10, x1, x4) + +inst_37: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1c6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x35c6; op2val:0x7bff; + valaddr_reg:x8; val_offset:24*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 24*FLEN/8, x10, x1, x4) + +inst_38: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1c6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x35c6; op2val:0x7bff; + valaddr_reg:x8; val_offset:26*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 26*FLEN/8, x10, x1, x4) + +inst_39: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1c6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x35c6; op2val:0x7bff; + valaddr_reg:x8; val_offset:28*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 28*FLEN/8, x10, x1, x4) + +inst_40: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1d7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x35d7; op2val:0x7bff; + valaddr_reg:x8; val_offset:30*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 30*FLEN/8, x10, x1, x4) + +inst_41: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1d7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x35d7; op2val:0x7bff; + valaddr_reg:x8; val_offset:32*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 32*FLEN/8, x10, x1, x4) + +inst_42: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1d7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x35d7; op2val:0x7bff; + valaddr_reg:x8; val_offset:34*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 34*FLEN/8, x10, x1, x4) + +inst_43: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1d7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x35d7; op2val:0x7bff; + valaddr_reg:x8; val_offset:36*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 36*FLEN/8, x10, x1, x4) + +inst_44: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1d7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x35d7; op2val:0x7bff; + valaddr_reg:x8; val_offset:38*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 38*FLEN/8, x10, x1, x4) + +inst_45: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x37a1; op2val:0x7bff; + valaddr_reg:x8; val_offset:40*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 40*FLEN/8, x10, x1, x4) + +inst_46: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x37a1; op2val:0x7bff; + valaddr_reg:x8; val_offset:42*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 42*FLEN/8, x10, x1, x4) + +inst_47: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x37a1; op2val:0x7bff; + valaddr_reg:x8; val_offset:44*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 44*FLEN/8, x10, x1, x4) + +inst_48: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x37a1; op2val:0x7bff; + valaddr_reg:x8; val_offset:46*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 46*FLEN/8, x10, x1, x4) + +inst_49: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x37a1; op2val:0x7bff; + valaddr_reg:x8; val_offset:48*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 48*FLEN/8, x10, x1, x4) + +inst_50: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x141 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3541; op2val:0x7bff; + valaddr_reg:x8; val_offset:50*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 50*FLEN/8, x10, x1, x4) + +inst_51: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x141 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3541; op2val:0x7bff; + valaddr_reg:x8; val_offset:52*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 52*FLEN/8, x10, x1, x4) + +inst_52: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x141 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3541; op2val:0x7bff; + valaddr_reg:x8; val_offset:54*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 54*FLEN/8, x10, x1, x4) + +inst_53: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x141 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3541; op2val:0x7bff; + valaddr_reg:x8; val_offset:56*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 56*FLEN/8, x10, x1, x4) + +inst_54: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x141 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3541; op2val:0x7bff; + valaddr_reg:x8; val_offset:58*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 58*FLEN/8, x10, x1, x4) + +inst_55: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3bc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x33bc; op2val:0x7bff; + valaddr_reg:x8; val_offset:60*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 60*FLEN/8, x10, x1, x4) + +inst_56: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3bc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x33bc; op2val:0x7bff; + valaddr_reg:x8; val_offset:62*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 62*FLEN/8, x10, x1, x4) + +inst_57: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3bc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x33bc; op2val:0x7bff; + valaddr_reg:x8; val_offset:64*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 64*FLEN/8, x10, x1, x4) + +inst_58: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3bc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x33bc; op2val:0x7bff; + valaddr_reg:x8; val_offset:66*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 66*FLEN/8, x10, x1, x4) + +inst_59: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3bc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x33bc; op2val:0x7bff; + valaddr_reg:x8; val_offset:68*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 68*FLEN/8, x10, x1, x4) + +inst_60: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x197 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3997; op2val:0x7bff; + valaddr_reg:x8; val_offset:70*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 70*FLEN/8, x10, x1, x4) + +inst_61: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x197 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3997; op2val:0x7bff; + valaddr_reg:x8; val_offset:72*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 72*FLEN/8, x10, x1, x4) + +inst_62: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x197 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3997; op2val:0x7bff; + valaddr_reg:x8; val_offset:74*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 74*FLEN/8, x10, x1, x4) + +inst_63: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x197 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3997; op2val:0x7bff; + valaddr_reg:x8; val_offset:76*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 76*FLEN/8, x10, x1, x4) + +inst_64: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x197 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3997; op2val:0x7bff; + valaddr_reg:x8; val_offset:78*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 78*FLEN/8, x10, x1, x4) + +inst_65: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x04d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x304d; op2val:0x7bff; + valaddr_reg:x8; val_offset:80*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 80*FLEN/8, x10, x1, x4) + +inst_66: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x04d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x304d; op2val:0x7bff; + valaddr_reg:x8; val_offset:82*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 82*FLEN/8, x10, x1, x4) + +inst_67: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x04d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x304d; op2val:0x7bff; + valaddr_reg:x8; val_offset:84*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 84*FLEN/8, x10, x1, x4) + +inst_68: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x04d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x304d; op2val:0x7bff; + valaddr_reg:x8; val_offset:86*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 86*FLEN/8, x10, x1, x4) + +inst_69: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x04d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x304d; op2val:0x7bff; + valaddr_reg:x8; val_offset:88*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 88*FLEN/8, x10, x1, x4) + +inst_70: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x07f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x347f; op2val:0x7bff; + valaddr_reg:x8; val_offset:90*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 90*FLEN/8, x10, x1, x4) + +inst_71: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x07f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x347f; op2val:0x7bff; + valaddr_reg:x8; val_offset:92*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 92*FLEN/8, x10, x1, x4) + +inst_72: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x07f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x347f; op2val:0x7bff; + valaddr_reg:x8; val_offset:94*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 94*FLEN/8, x10, x1, x4) + +inst_73: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x07f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x347f; op2val:0x7bff; + valaddr_reg:x8; val_offset:96*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 96*FLEN/8, x10, x1, x4) + +inst_74: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x07f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x347f; op2val:0x7bff; + valaddr_reg:x8; val_offset:98*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 98*FLEN/8, x10, x1, x4) + +inst_75: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x092 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3492; op2val:0x7bff; + valaddr_reg:x8; val_offset:100*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 100*FLEN/8, x10, x1, x4) + +inst_76: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x092 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3492; op2val:0x7bff; + valaddr_reg:x8; val_offset:102*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 102*FLEN/8, x10, x1, x4) + +inst_77: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x092 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3492; op2val:0x7bff; + valaddr_reg:x8; val_offset:104*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 104*FLEN/8, x10, x1, x4) + +inst_78: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x092 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3492; op2val:0x7bff; + valaddr_reg:x8; val_offset:106*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 106*FLEN/8, x10, x1, x4) + +inst_79: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x092 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3492; op2val:0x7bff; + valaddr_reg:x8; val_offset:108*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 108*FLEN/8, x10, x1, x4) + +inst_80: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x38d7; op2val:0x7bff; + valaddr_reg:x8; val_offset:110*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 110*FLEN/8, x10, x1, x4) + +inst_81: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x38d7; op2val:0x7bff; + valaddr_reg:x8; val_offset:112*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 112*FLEN/8, x10, x1, x4) + +inst_82: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x38d7; op2val:0x7bff; + valaddr_reg:x8; val_offset:114*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 114*FLEN/8, x10, x1, x4) + +inst_83: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x38d7; op2val:0x7bff; + valaddr_reg:x8; val_offset:116*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 116*FLEN/8, x10, x1, x4) + +inst_84: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x38d7; op2val:0x7bff; + valaddr_reg:x8; val_offset:118*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 118*FLEN/8, x10, x1, x4) + +inst_85: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x071 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3871; op2val:0x7bff; + valaddr_reg:x8; val_offset:120*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 120*FLEN/8, x10, x1, x4) + +inst_86: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x071 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3871; op2val:0x7bff; + valaddr_reg:x8; val_offset:122*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 122*FLEN/8, x10, x1, x4) + +inst_87: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x071 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3871; op2val:0x7bff; + valaddr_reg:x8; val_offset:124*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 124*FLEN/8, x10, x1, x4) + +inst_88: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x071 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3871; op2val:0x7bff; + valaddr_reg:x8; val_offset:126*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 126*FLEN/8, x10, x1, x4) + +inst_89: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x071 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3871; op2val:0x7bff; + valaddr_reg:x8; val_offset:128*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 128*FLEN/8, x10, x1, x4) + +inst_90: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2fc0; op2val:0x7bff; + valaddr_reg:x8; val_offset:130*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 130*FLEN/8, x10, x1, x4) + +inst_91: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2fc0; op2val:0x7bff; + valaddr_reg:x8; val_offset:132*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 132*FLEN/8, x10, x1, x4) + +inst_92: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2fc0; op2val:0x7bff; + valaddr_reg:x8; val_offset:134*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 134*FLEN/8, x10, x1, x4) + +inst_93: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2fc0; op2val:0x7bff; + valaddr_reg:x8; val_offset:136*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 136*FLEN/8, x10, x1, x4) + +inst_94: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2fc0; op2val:0x7bff; + valaddr_reg:x8; val_offset:138*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 138*FLEN/8, x10, x1, x4) + +inst_95: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2e9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ae9; op2val:0x7bff; + valaddr_reg:x8; val_offset:140*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 140*FLEN/8, x10, x1, x4) + +inst_96: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2e9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ae9; op2val:0x7bff; + valaddr_reg:x8; val_offset:142*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 142*FLEN/8, x10, x1, x4) + +inst_97: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2e9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ae9; op2val:0x7bff; + valaddr_reg:x8; val_offset:144*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 144*FLEN/8, x10, x1, x4) + +inst_98: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2e9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ae9; op2val:0x7bff; + valaddr_reg:x8; val_offset:146*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 146*FLEN/8, x10, x1, x4) + +inst_99: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2e9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ae9; op2val:0x7bff; + valaddr_reg:x8; val_offset:148*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 148*FLEN/8, x10, x1, x4) + +inst_100: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x06b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x286b; op2val:0x7bff; + valaddr_reg:x8; val_offset:150*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 150*FLEN/8, x10, x1, x4) + +inst_101: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x06b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x286b; op2val:0x7bff; + valaddr_reg:x8; val_offset:152*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 152*FLEN/8, x10, x1, x4) + +inst_102: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x06b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x286b; op2val:0x7bff; + valaddr_reg:x8; val_offset:154*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 154*FLEN/8, x10, x1, x4) + +inst_103: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x06b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x286b; op2val:0x7bff; + valaddr_reg:x8; val_offset:156*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 156*FLEN/8, x10, x1, x4) + +inst_104: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x06b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x286b; op2val:0x7bff; + valaddr_reg:x8; val_offset:158*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 158*FLEN/8, x10, x1, x4) + +inst_105: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1f9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x35f9; op2val:0x7bff; + valaddr_reg:x8; val_offset:160*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 160*FLEN/8, x10, x1, x4) + +inst_106: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1f9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x35f9; op2val:0x7bff; + valaddr_reg:x8; val_offset:162*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 162*FLEN/8, x10, x1, x4) + +inst_107: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1f9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x35f9; op2val:0x7bff; + valaddr_reg:x8; val_offset:164*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 164*FLEN/8, x10, x1, x4) + +inst_108: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1f9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x35f9; op2val:0x7bff; + valaddr_reg:x8; val_offset:166*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 166*FLEN/8, x10, x1, x4) + +inst_109: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1f9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x35f9; op2val:0x7bff; + valaddr_reg:x8; val_offset:168*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 168*FLEN/8, x10, x1, x4) + +inst_110: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3e2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x37e2; op2val:0x7bff; + valaddr_reg:x8; val_offset:170*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 170*FLEN/8, x10, x1, x4) + +inst_111: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3e2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x37e2; op2val:0x7bff; + valaddr_reg:x8; val_offset:172*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 172*FLEN/8, x10, x1, x4) + +inst_112: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3e2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x37e2; op2val:0x7bff; + valaddr_reg:x8; val_offset:174*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 174*FLEN/8, x10, x1, x4) + +inst_113: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3e2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x37e2; op2val:0x7bff; + valaddr_reg:x8; val_offset:176*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 176*FLEN/8, x10, x1, x4) + +inst_114: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3e2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x37e2; op2val:0x7bff; + valaddr_reg:x8; val_offset:178*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 178*FLEN/8, x10, x1, x4) + +inst_115: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x131 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3931; op2val:0x7bff; + valaddr_reg:x8; val_offset:180*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 180*FLEN/8, x10, x1, x4) + +inst_116: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x131 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3931; op2val:0x7bff; + valaddr_reg:x8; val_offset:182*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 182*FLEN/8, x10, x1, x4) + +inst_117: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x131 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3931; op2val:0x7bff; + valaddr_reg:x8; val_offset:184*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 184*FLEN/8, x10, x1, x4) + +inst_118: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x131 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3931; op2val:0x7bff; + valaddr_reg:x8; val_offset:186*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 186*FLEN/8, x10, x1, x4) + +inst_119: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x131 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3931; op2val:0x7bff; + valaddr_reg:x8; val_offset:188*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 188*FLEN/8, x10, x1, x4) + +inst_120: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2a6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x36a6; op2val:0x7bff; + valaddr_reg:x8; val_offset:190*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 190*FLEN/8, x10, x1, x4) + +inst_121: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2a6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x36a6; op2val:0x7bff; + valaddr_reg:x8; val_offset:192*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 192*FLEN/8, x10, x1, x4) + +inst_122: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2a6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x36a6; op2val:0x7bff; + valaddr_reg:x8; val_offset:194*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 194*FLEN/8, x10, x1, x4) + +inst_123: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2a6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x36a6; op2val:0x7bff; + valaddr_reg:x8; val_offset:196*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 196*FLEN/8, x10, x1, x4) + +inst_124: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2a6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x36a6; op2val:0x7bff; + valaddr_reg:x8; val_offset:198*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 198*FLEN/8, x10, x1, x4) + +inst_125: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x116 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3516; op2val:0x7bff; + valaddr_reg:x8; val_offset:200*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 200*FLEN/8, x10, x1, x4) + +inst_126: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x116 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3516; op2val:0x7bff; + valaddr_reg:x8; val_offset:202*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 202*FLEN/8, x10, x1, x4) + +inst_127: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x116 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3516; op2val:0x7bff; + valaddr_reg:x8; val_offset:204*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 204*FLEN/8, x10, x1, x4) + +inst_128: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x116 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3516; op2val:0x7bff; + valaddr_reg:x8; val_offset:206*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 206*FLEN/8, x10, x1, x4) + +inst_129: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x116 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3516; op2val:0x7bff; + valaddr_reg:x8; val_offset:208*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 208*FLEN/8, x10, x1, x4) + +inst_130: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x098 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3098; op2val:0x7bff; + valaddr_reg:x8; val_offset:210*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 210*FLEN/8, x10, x1, x4) + +inst_131: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x098 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3098; op2val:0x7bff; + valaddr_reg:x8; val_offset:212*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 212*FLEN/8, x10, x1, x4) + +inst_132: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x098 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3098; op2val:0x7bff; + valaddr_reg:x8; val_offset:214*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 214*FLEN/8, x10, x1, x4) + +inst_133: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x098 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3098; op2val:0x7bff; + valaddr_reg:x8; val_offset:216*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 216*FLEN/8, x10, x1, x4) + +inst_134: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x098 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3098; op2val:0x7bff; + valaddr_reg:x8; val_offset:218*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 218*FLEN/8, x10, x1, x4) + +inst_135: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x142 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3542; op2val:0x7bff; + valaddr_reg:x8; val_offset:220*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 220*FLEN/8, x10, x1, x4) + +inst_136: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x142 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3542; op2val:0x7bff; + valaddr_reg:x8; val_offset:222*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 222*FLEN/8, x10, x1, x4) + +inst_137: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x142 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3542; op2val:0x7bff; + valaddr_reg:x8; val_offset:224*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 224*FLEN/8, x10, x1, x4) + +inst_138: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x142 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3542; op2val:0x7bff; + valaddr_reg:x8; val_offset:226*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 226*FLEN/8, x10, x1, x4) + +inst_139: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x142 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3542; op2val:0x7bff; + valaddr_reg:x8; val_offset:228*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 228*FLEN/8, x10, x1, x4) + +inst_140: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x075 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3075; op2val:0x7bff; + valaddr_reg:x8; val_offset:230*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 230*FLEN/8, x10, x1, x4) + +inst_141: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x075 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3075; op2val:0x7bff; + valaddr_reg:x8; val_offset:232*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 232*FLEN/8, x10, x1, x4) + +inst_142: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x075 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3075; op2val:0x7bff; + valaddr_reg:x8; val_offset:234*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 234*FLEN/8, x10, x1, x4) + +inst_143: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x075 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3075; op2val:0x7bff; + valaddr_reg:x8; val_offset:236*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 236*FLEN/8, x10, x1, x4) + +inst_144: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x075 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3075; op2val:0x7bff; + valaddr_reg:x8; val_offset:238*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 238*FLEN/8, x10, x1, x4) + +inst_145: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x219 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e19; op2val:0x7bff; + valaddr_reg:x8; val_offset:240*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 240*FLEN/8, x10, x1, x4) + +inst_146: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x219 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e19; op2val:0x7bff; + valaddr_reg:x8; val_offset:242*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 242*FLEN/8, x10, x1, x4) + +inst_147: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x219 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e19; op2val:0x7bff; + valaddr_reg:x8; val_offset:244*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 244*FLEN/8, x10, x1, x4) + +inst_148: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x219 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e19; op2val:0x7bff; + valaddr_reg:x8; val_offset:246*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 246*FLEN/8, x10, x1, x4) + +inst_149: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x219 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e19; op2val:0x7bff; + valaddr_reg:x8; val_offset:248*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 248*FLEN/8, x10, x1, x4) + +inst_150: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x094 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3494; op2val:0x7bff; + valaddr_reg:x8; val_offset:250*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 250*FLEN/8, x10, x1, x4) + +inst_151: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x094 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3494; op2val:0x7bff; + valaddr_reg:x8; val_offset:252*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 252*FLEN/8, x10, x1, x4) + +inst_152: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x094 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3494; op2val:0x7bff; + valaddr_reg:x8; val_offset:254*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 254*FLEN/8, x10, x1, x4) + +inst_153: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x094 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3494; op2val:0x7bff; + valaddr_reg:x8; val_offset:256*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 256*FLEN/8, x10, x1, x4) + +inst_154: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x094 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3494; op2val:0x7bff; + valaddr_reg:x8; val_offset:258*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 258*FLEN/8, x10, x1, x4) + +inst_155: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x163 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3163; op2val:0x7bff; + valaddr_reg:x8; val_offset:260*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 260*FLEN/8, x10, x1, x4) + +inst_156: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x163 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3163; op2val:0x7bff; + valaddr_reg:x8; val_offset:262*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 262*FLEN/8, x10, x1, x4) + +inst_157: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x163 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3163; op2val:0x7bff; + valaddr_reg:x8; val_offset:264*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 264*FLEN/8, x10, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_158: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x163 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3163; op2val:0x7bff; + valaddr_reg:x8; val_offset:266*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 266*FLEN/8, x10, x1, x4) + +inst_159: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x163 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3163; op2val:0x7bff; + valaddr_reg:x8; val_offset:268*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 268*FLEN/8, x10, x1, x4) + +inst_160: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1b8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39b8; op2val:0x7bff; + valaddr_reg:x8; val_offset:270*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 270*FLEN/8, x10, x1, x4) + +inst_161: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1b8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39b8; op2val:0x7bff; + valaddr_reg:x8; val_offset:272*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 272*FLEN/8, x10, x1, x4) + +inst_162: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1b8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39b8; op2val:0x7bff; + valaddr_reg:x8; val_offset:274*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 274*FLEN/8, x10, x1, x4) + +inst_163: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1b8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39b8; op2val:0x7bff; + valaddr_reg:x8; val_offset:276*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 276*FLEN/8, x10, x1, x4) + +inst_164: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1b8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39b8; op2val:0x7bff; + valaddr_reg:x8; val_offset:278*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 278*FLEN/8, x10, x1, x4) + +inst_165: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0ac and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x30ac; op2val:0x7bff; + valaddr_reg:x8; val_offset:280*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 280*FLEN/8, x10, x1, x4) + +inst_166: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0ac and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x30ac; op2val:0x7bff; + valaddr_reg:x8; val_offset:282*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 282*FLEN/8, x10, x1, x4) + +inst_167: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0ac and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x30ac; op2val:0x7bff; + valaddr_reg:x8; val_offset:284*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 284*FLEN/8, x10, x1, x4) + +inst_168: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0ac and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x30ac; op2val:0x7bff; + valaddr_reg:x8; val_offset:286*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 286*FLEN/8, x10, x1, x4) + +inst_169: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0ac and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x30ac; op2val:0x7bff; + valaddr_reg:x8; val_offset:288*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 288*FLEN/8, x10, x1, x4) + +inst_170: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x34a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b4a; op2val:0x7bff; + valaddr_reg:x8; val_offset:290*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 290*FLEN/8, x10, x1, x4) + +inst_171: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x34a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b4a; op2val:0x7bff; + valaddr_reg:x8; val_offset:292*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 292*FLEN/8, x10, x1, x4) + +inst_172: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x34a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b4a; op2val:0x7bff; + valaddr_reg:x8; val_offset:294*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 294*FLEN/8, x10, x1, x4) + +inst_173: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x34a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b4a; op2val:0x7bff; + valaddr_reg:x8; val_offset:296*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 296*FLEN/8, x10, x1, x4) + +inst_174: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x34a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b4a; op2val:0x7bff; + valaddr_reg:x8; val_offset:298*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 298*FLEN/8, x10, x1, x4) + +inst_175: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0b7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x38b7; op2val:0x7bff; + valaddr_reg:x8; val_offset:300*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 300*FLEN/8, x10, x1, x4) + +inst_176: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0b7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x38b7; op2val:0x7bff; + valaddr_reg:x8; val_offset:302*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 302*FLEN/8, x10, x1, x4) + +inst_177: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0b7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x38b7; op2val:0x7bff; + valaddr_reg:x8; val_offset:304*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 304*FLEN/8, x10, x1, x4) + +inst_178: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0b7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x38b7; op2val:0x7bff; + valaddr_reg:x8; val_offset:306*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 306*FLEN/8, x10, x1, x4) + +inst_179: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0b7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x38b7; op2val:0x7bff; + valaddr_reg:x8; val_offset:308*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 308*FLEN/8, x10, x1, x4) + +inst_180: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39a6; op2val:0x7bff; + valaddr_reg:x8; val_offset:310*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 310*FLEN/8, x10, x1, x4) + +inst_181: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39a6; op2val:0x7bff; + valaddr_reg:x8; val_offset:312*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 312*FLEN/8, x10, x1, x4) + +inst_182: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39a6; op2val:0x7bff; + valaddr_reg:x8; val_offset:314*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 314*FLEN/8, x10, x1, x4) + +inst_183: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39a6; op2val:0x7bff; + valaddr_reg:x8; val_offset:316*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 316*FLEN/8, x10, x1, x4) + +inst_184: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39a6; op2val:0x7bff; + valaddr_reg:x8; val_offset:318*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 318*FLEN/8, x10, x1, x4) + +inst_185: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x012 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3012; op2val:0x7bff; + valaddr_reg:x8; val_offset:320*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 320*FLEN/8, x10, x1, x4) + +inst_186: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x012 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3012; op2val:0x7bff; + valaddr_reg:x8; val_offset:322*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 322*FLEN/8, x10, x1, x4) + +inst_187: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x012 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3012; op2val:0x7bff; + valaddr_reg:x8; val_offset:324*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 324*FLEN/8, x10, x1, x4) + +inst_188: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x012 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3012; op2val:0x7bff; + valaddr_reg:x8; val_offset:326*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 326*FLEN/8, x10, x1, x4) + +inst_189: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x012 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3012; op2val:0x7bff; + valaddr_reg:x8; val_offset:328*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 328*FLEN/8, x10, x1, x4) + +inst_190: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x22a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x362a; op2val:0x7bff; + valaddr_reg:x8; val_offset:330*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 330*FLEN/8, x10, x1, x4) + +inst_191: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x22a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x362a; op2val:0x7bff; + valaddr_reg:x8; val_offset:332*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 332*FLEN/8, x10, x1, x4) + +inst_192: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x22a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x362a; op2val:0x7bff; + valaddr_reg:x8; val_offset:334*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 334*FLEN/8, x10, x1, x4) + +inst_193: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x22a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x362a; op2val:0x7bff; + valaddr_reg:x8; val_offset:336*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 336*FLEN/8, x10, x1, x4) + +inst_194: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x22a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x362a; op2val:0x7bff; + valaddr_reg:x8; val_offset:338*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 338*FLEN/8, x10, x1, x4) + +inst_195: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x081 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3481; op2val:0x7bff; + valaddr_reg:x8; val_offset:340*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 340*FLEN/8, x10, x1, x4) + +inst_196: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x081 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3481; op2val:0x7bff; + valaddr_reg:x8; val_offset:342*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 342*FLEN/8, x10, x1, x4) + +inst_197: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x081 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3481; op2val:0x7bff; + valaddr_reg:x8; val_offset:344*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 344*FLEN/8, x10, x1, x4) + +inst_198: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x081 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3481; op2val:0x7bff; + valaddr_reg:x8; val_offset:346*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 346*FLEN/8, x10, x1, x4) + +inst_199: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x081 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3481; op2val:0x7bff; + valaddr_reg:x8; val_offset:348*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 348*FLEN/8, x10, x1, x4) + +inst_200: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x39f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2f9f; op2val:0x7bff; + valaddr_reg:x8; val_offset:350*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 350*FLEN/8, x10, x1, x4) + +inst_201: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x39f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2f9f; op2val:0x7bff; + valaddr_reg:x8; val_offset:352*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 352*FLEN/8, x10, x1, x4) + +inst_202: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x39f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2f9f; op2val:0x7bff; + valaddr_reg:x8; val_offset:354*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 354*FLEN/8, x10, x1, x4) + +inst_203: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x39f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2f9f; op2val:0x7bff; + valaddr_reg:x8; val_offset:356*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 356*FLEN/8, x10, x1, x4) + +inst_204: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x39f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2f9f; op2val:0x7bff; + valaddr_reg:x8; val_offset:358*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 358*FLEN/8, x10, x1, x4) + +inst_205: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3e9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x37e9; op2val:0x7bff; + valaddr_reg:x8; val_offset:360*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 360*FLEN/8, x10, x1, x4) + +inst_206: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3e9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x37e9; op2val:0x7bff; + valaddr_reg:x8; val_offset:362*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 362*FLEN/8, x10, x1, x4) + +inst_207: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3e9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x37e9; op2val:0x7bff; + valaddr_reg:x8; val_offset:364*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 364*FLEN/8, x10, x1, x4) + +inst_208: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3e9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x37e9; op2val:0x7bff; + valaddr_reg:x8; val_offset:366*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 366*FLEN/8, x10, x1, x4) + +inst_209: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3e9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x37e9; op2val:0x7bff; + valaddr_reg:x8; val_offset:368*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 368*FLEN/8, x10, x1, x4) + +inst_210: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x185 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x188 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3985; op2val:0x7188; + valaddr_reg:x8; val_offset:370*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 370*FLEN/8, x10, x1, x4) + +inst_211: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x185 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x188 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3985; op2val:0x7188; + valaddr_reg:x8; val_offset:372*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 372*FLEN/8, x10, x1, x4) + +inst_212: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x185 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x188 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3985; op2val:0x7188; + valaddr_reg:x8; val_offset:374*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 374*FLEN/8, x10, x1, x4) + +inst_213: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x185 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x188 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3985; op2val:0x7188; + valaddr_reg:x8; val_offset:376*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 376*FLEN/8, x10, x1, x4) + +inst_214: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x185 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x188 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3985; op2val:0x7188; + valaddr_reg:x8; val_offset:378*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 378*FLEN/8, x10, x1, x4) + +inst_215: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x267 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x26a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3667; op2val:0x6e6a; + valaddr_reg:x8; val_offset:380*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 380*FLEN/8, x10, x1, x4) + +inst_216: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x267 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x26a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3667; op2val:0x6e6a; + valaddr_reg:x8; val_offset:382*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 382*FLEN/8, x10, x1, x4) + +inst_217: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x267 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x26a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3667; op2val:0x6e6a; + valaddr_reg:x8; val_offset:384*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 384*FLEN/8, x10, x1, x4) + +inst_218: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x267 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x26a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3667; op2val:0x6e6a; + valaddr_reg:x8; val_offset:386*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 386*FLEN/8, x10, x1, x4) + +inst_219: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x267 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x26a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3667; op2val:0x6e6a; + valaddr_reg:x8; val_offset:388*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 388*FLEN/8, x10, x1, x4) + +inst_220: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x26b and fs2 == 0 and fe2 == 0x1c and fm2 == 0x26e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a6b; op2val:0x726e; + valaddr_reg:x8; val_offset:390*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 390*FLEN/8, x10, x1, x4) + +inst_221: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x26b and fs2 == 0 and fe2 == 0x1c and fm2 == 0x26e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a6b; op2val:0x726e; + valaddr_reg:x8; val_offset:392*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 392*FLEN/8, x10, x1, x4) + +inst_222: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x26b and fs2 == 0 and fe2 == 0x1c and fm2 == 0x26e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a6b; op2val:0x726e; + valaddr_reg:x8; val_offset:394*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 394*FLEN/8, x10, x1, x4) + +inst_223: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x26b and fs2 == 0 and fe2 == 0x1c and fm2 == 0x26e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a6b; op2val:0x726e; + valaddr_reg:x8; val_offset:396*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 396*FLEN/8, x10, x1, x4) + +inst_224: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x26b and fs2 == 0 and fe2 == 0x1c and fm2 == 0x26e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a6b; op2val:0x726e; + valaddr_reg:x8; val_offset:398*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 398*FLEN/8, x10, x1, x4) + +inst_225: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x23b and fs2 == 0 and fe2 == 0x1b and fm2 == 0x23e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x363b; op2val:0x6e3e; + valaddr_reg:x8; val_offset:400*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 400*FLEN/8, x10, x1, x4) + +inst_226: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x23b and fs2 == 0 and fe2 == 0x1b and fm2 == 0x23e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x363b; op2val:0x6e3e; + valaddr_reg:x8; val_offset:402*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 402*FLEN/8, x10, x1, x4) + +inst_227: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x23b and fs2 == 0 and fe2 == 0x1b and fm2 == 0x23e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x363b; op2val:0x6e3e; + valaddr_reg:x8; val_offset:404*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 404*FLEN/8, x10, x1, x4) + +inst_228: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x23b and fs2 == 0 and fe2 == 0x1b and fm2 == 0x23e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x363b; op2val:0x6e3e; + valaddr_reg:x8; val_offset:406*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 406*FLEN/8, x10, x1, x4) + +inst_229: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x23b and fs2 == 0 and fe2 == 0x1b and fm2 == 0x23e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x363b; op2val:0x6e3e; + valaddr_reg:x8; val_offset:408*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 408*FLEN/8, x10, x1, x4) + +inst_230: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3a9 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3ac and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ba9; op2val:0x73ac; + valaddr_reg:x8; val_offset:410*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 410*FLEN/8, x10, x1, x4) + +inst_231: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3a9 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3ac and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ba9; op2val:0x73ac; + valaddr_reg:x8; val_offset:412*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 412*FLEN/8, x10, x1, x4) + +inst_232: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3a9 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3ac and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ba9; op2val:0x73ac; + valaddr_reg:x8; val_offset:414*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 414*FLEN/8, x10, x1, x4) + +inst_233: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3a9 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3ac and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ba9; op2val:0x73ac; + valaddr_reg:x8; val_offset:416*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 416*FLEN/8, x10, x1, x4) + +inst_234: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3a9 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3ac and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ba9; op2val:0x73ac; + valaddr_reg:x8; val_offset:418*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 418*FLEN/8, x10, x1, x4) + +inst_235: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x17d and fs2 == 0 and fe2 == 0x1c and fm2 == 0x17f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x397d; op2val:0x717f; + valaddr_reg:x8; val_offset:420*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 420*FLEN/8, x10, x1, x4) + +inst_236: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x17d and fs2 == 0 and fe2 == 0x1c and fm2 == 0x17f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x397d; op2val:0x717f; + valaddr_reg:x8; val_offset:422*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 422*FLEN/8, x10, x1, x4) + +inst_237: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x17d and fs2 == 0 and fe2 == 0x1c and fm2 == 0x17f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x397d; op2val:0x717f; + valaddr_reg:x8; val_offset:424*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 424*FLEN/8, x10, x1, x4) + +inst_238: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x17d and fs2 == 0 and fe2 == 0x1c and fm2 == 0x17f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x397d; op2val:0x717f; + valaddr_reg:x8; val_offset:426*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 426*FLEN/8, x10, x1, x4) + +inst_239: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x17d and fs2 == 0 and fe2 == 0x1c and fm2 == 0x17f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x397d; op2val:0x717f; + valaddr_reg:x8; val_offset:428*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 428*FLEN/8, x10, x1, x4) + +inst_240: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x29e and fs2 == 0 and fe2 == 0x19 and fm2 == 0x2a1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e9e; op2val:0x66a1; + valaddr_reg:x8; val_offset:430*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 430*FLEN/8, x10, x1, x4) + +inst_241: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x29e and fs2 == 0 and fe2 == 0x19 and fm2 == 0x2a1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e9e; op2val:0x66a1; + valaddr_reg:x8; val_offset:432*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 432*FLEN/8, x10, x1, x4) + +inst_242: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x29e and fs2 == 0 and fe2 == 0x19 and fm2 == 0x2a1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e9e; op2val:0x66a1; + valaddr_reg:x8; val_offset:434*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 434*FLEN/8, x10, x1, x4) + +inst_243: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x29e and fs2 == 0 and fe2 == 0x19 and fm2 == 0x2a1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e9e; op2val:0x66a1; + valaddr_reg:x8; val_offset:436*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 436*FLEN/8, x10, x1, x4) + +inst_244: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x29e and fs2 == 0 and fe2 == 0x19 and fm2 == 0x2a1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e9e; op2val:0x66a1; + valaddr_reg:x8; val_offset:438*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 438*FLEN/8, x10, x1, x4) + +inst_245: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x051 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x053 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3851; op2val:0x7053; + valaddr_reg:x8; val_offset:440*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 440*FLEN/8, x10, x1, x4) + +inst_246: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x051 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x053 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3851; op2val:0x7053; + valaddr_reg:x8; val_offset:442*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 442*FLEN/8, x10, x1, x4) + +inst_247: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x051 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x053 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3851; op2val:0x7053; + valaddr_reg:x8; val_offset:444*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 444*FLEN/8, x10, x1, x4) + +inst_248: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x051 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x053 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3851; op2val:0x7053; + valaddr_reg:x8; val_offset:446*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 446*FLEN/8, x10, x1, x4) + +inst_249: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x051 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x053 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3851; op2val:0x7053; + valaddr_reg:x8; val_offset:448*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 448*FLEN/8, x10, x1, x4) + +inst_250: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1b2 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x1b5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x35b2; op2val:0x6db5; + valaddr_reg:x8; val_offset:450*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 450*FLEN/8, x10, x1, x4) + +inst_251: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1b2 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x1b5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x35b2; op2val:0x6db5; + valaddr_reg:x8; val_offset:452*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 452*FLEN/8, x10, x1, x4) + +inst_252: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1b2 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x1b5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x35b2; op2val:0x6db5; + valaddr_reg:x8; val_offset:454*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 454*FLEN/8, x10, x1, x4) + +inst_253: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1b2 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x1b5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x35b2; op2val:0x6db5; + valaddr_reg:x8; val_offset:456*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 456*FLEN/8, x10, x1, x4) + +inst_254: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1b2 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x1b5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x35b2; op2val:0x6db5; + valaddr_reg:x8; val_offset:458*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 458*FLEN/8, x10, x1, x4) + +inst_255: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x30d and fs2 == 0 and fe2 == 0x1b and fm2 == 0x310 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x370d; op2val:0x6f10; + valaddr_reg:x8; val_offset:460*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 460*FLEN/8, x10, x1, x4) + +inst_256: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x30d and fs2 == 0 and fe2 == 0x1b and fm2 == 0x310 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x370d; op2val:0x6f10; + valaddr_reg:x8; val_offset:462*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 462*FLEN/8, x10, x1, x4) + +inst_257: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x30d and fs2 == 0 and fe2 == 0x1b and fm2 == 0x310 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x370d; op2val:0x6f10; + valaddr_reg:x8; val_offset:464*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 464*FLEN/8, x10, x1, x4) + +inst_258: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x30d and fs2 == 0 and fe2 == 0x1b and fm2 == 0x310 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x370d; op2val:0x6f10; + valaddr_reg:x8; val_offset:466*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 466*FLEN/8, x10, x1, x4) + +inst_259: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x30d and fs2 == 0 and fe2 == 0x1b and fm2 == 0x310 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x370d; op2val:0x6f10; + valaddr_reg:x8; val_offset:468*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 468*FLEN/8, x10, x1, x4) + +inst_260: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x39b and fs2 == 0 and fe2 == 0x18 and fm2 == 0x39f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b9b; op2val:0x639f; + valaddr_reg:x8; val_offset:470*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 470*FLEN/8, x10, x1, x4) + +inst_261: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x39b and fs2 == 0 and fe2 == 0x18 and fm2 == 0x39f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b9b; op2val:0x639f; + valaddr_reg:x8; val_offset:472*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 472*FLEN/8, x10, x1, x4) + +inst_262: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x39b and fs2 == 0 and fe2 == 0x18 and fm2 == 0x39f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b9b; op2val:0x639f; + valaddr_reg:x8; val_offset:474*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 474*FLEN/8, x10, x1, x4) + +inst_263: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x39b and fs2 == 0 and fe2 == 0x18 and fm2 == 0x39f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b9b; op2val:0x639f; + valaddr_reg:x8; val_offset:476*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 476*FLEN/8, x10, x1, x4) + +inst_264: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x39b and fs2 == 0 and fe2 == 0x18 and fm2 == 0x39f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b9b; op2val:0x639f; + valaddr_reg:x8; val_offset:478*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 478*FLEN/8, x10, x1, x4) + +inst_265: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x08c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x08f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x388c; op2val:0x708f; + valaddr_reg:x8; val_offset:480*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 480*FLEN/8, x10, x1, x4) + +inst_266: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x08c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x08f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x388c; op2val:0x708f; + valaddr_reg:x8; val_offset:482*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 482*FLEN/8, x10, x1, x4) + +inst_267: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x08c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x08f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x388c; op2val:0x708f; + valaddr_reg:x8; val_offset:484*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 484*FLEN/8, x10, x1, x4) + +inst_268: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x08c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x08f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x388c; op2val:0x708f; + valaddr_reg:x8; val_offset:486*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 486*FLEN/8, x10, x1, x4) + +inst_269: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x08c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x08f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x388c; op2val:0x708f; + valaddr_reg:x8; val_offset:488*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 488*FLEN/8, x10, x1, x4) + +inst_270: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x219 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x21c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a19; op2val:0x721c; + valaddr_reg:x8; val_offset:490*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 490*FLEN/8, x10, x1, x4) + +inst_271: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x219 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x21c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a19; op2val:0x721c; + valaddr_reg:x8; val_offset:492*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 492*FLEN/8, x10, x1, x4) + +inst_272: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x219 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x21c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a19; op2val:0x721c; + valaddr_reg:x8; val_offset:494*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 494*FLEN/8, x10, x1, x4) + +inst_273: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x219 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x21c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a19; op2val:0x721c; + valaddr_reg:x8; val_offset:496*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 496*FLEN/8, x10, x1, x4) + +inst_274: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x219 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x21c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a19; op2val:0x721c; + valaddr_reg:x8; val_offset:498*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 498*FLEN/8, x10, x1, x4) + +inst_275: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x1b2 and fs2 == 0 and fe2 == 0x17 and fm2 == 0x1b5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x25b2; op2val:0x5db5; + valaddr_reg:x8; val_offset:500*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 500*FLEN/8, x10, x1, x4) + +inst_276: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x1b2 and fs2 == 0 and fe2 == 0x17 and fm2 == 0x1b5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x25b2; op2val:0x5db5; + valaddr_reg:x8; val_offset:502*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 502*FLEN/8, x10, x1, x4) + +inst_277: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x1b2 and fs2 == 0 and fe2 == 0x17 and fm2 == 0x1b5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x25b2; op2val:0x5db5; + valaddr_reg:x8; val_offset:504*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 504*FLEN/8, x10, x1, x4) + +inst_278: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x1b2 and fs2 == 0 and fe2 == 0x17 and fm2 == 0x1b5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x25b2; op2val:0x5db5; + valaddr_reg:x8; val_offset:506*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 506*FLEN/8, x10, x1, x4) + +inst_279: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x1b2 and fs2 == 0 and fe2 == 0x17 and fm2 == 0x1b5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x25b2; op2val:0x5db5; + valaddr_reg:x8; val_offset:508*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 508*FLEN/8, x10, x1, x4) + +inst_280: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x339 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x33d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3739; op2val:0x6f3d; + valaddr_reg:x8; val_offset:510*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 510*FLEN/8, x10, x1, x4) + +inst_281: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x339 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x33d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3739; op2val:0x6f3d; + valaddr_reg:x8; val_offset:512*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 512*FLEN/8, x10, x1, x4) + +inst_282: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x339 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x33d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3739; op2val:0x6f3d; + valaddr_reg:x8; val_offset:514*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 514*FLEN/8, x10, x1, x4) + +inst_283: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x339 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x33d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3739; op2val:0x6f3d; + valaddr_reg:x8; val_offset:516*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 516*FLEN/8, x10, x1, x4) + +inst_284: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x339 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x33d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3739; op2val:0x6f3d; + valaddr_reg:x8; val_offset:518*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 518*FLEN/8, x10, x1, x4) + +inst_285: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ad and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0b0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x38ad; op2val:0x70b0; + valaddr_reg:x8; val_offset:520*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 520*FLEN/8, x10, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_2) + +inst_286: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ad and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0b0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x38ad; op2val:0x70b0; + valaddr_reg:x8; val_offset:522*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 522*FLEN/8, x10, x1, x4) + +inst_287: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ad and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0b0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x38ad; op2val:0x70b0; + valaddr_reg:x8; val_offset:524*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 524*FLEN/8, x10, x1, x4) + +inst_288: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ad and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0b0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x38ad; op2val:0x70b0; + valaddr_reg:x8; val_offset:526*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 526*FLEN/8, x10, x1, x4) + +inst_289: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ad and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0b0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x38ad; op2val:0x70b0; + valaddr_reg:x8; val_offset:528*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 528*FLEN/8, x10, x1, x4) + +inst_290: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3da and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bd6; op2val:0x73da; + valaddr_reg:x8; val_offset:530*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 530*FLEN/8, x10, x1, x4) + +inst_291: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3da and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bd6; op2val:0x73da; + valaddr_reg:x8; val_offset:532*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 532*FLEN/8, x10, x1, x4) + +inst_292: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3da and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bd6; op2val:0x73da; + valaddr_reg:x8; val_offset:534*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 534*FLEN/8, x10, x1, x4) + +inst_293: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3da and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bd6; op2val:0x73da; + valaddr_reg:x8; val_offset:536*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 536*FLEN/8, x10, x1, x4) + +inst_294: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3da and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bd6; op2val:0x73da; + valaddr_reg:x8; val_offset:538*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 538*FLEN/8, x10, x1, x4) + +inst_295: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1e2 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x1e5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x35e2; op2val:0x6de5; + valaddr_reg:x8; val_offset:540*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 540*FLEN/8, x10, x1, x4) + +inst_296: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1e2 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x1e5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x35e2; op2val:0x6de5; + valaddr_reg:x8; val_offset:542*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 542*FLEN/8, x10, x1, x4) + +inst_297: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1e2 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x1e5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x35e2; op2val:0x6de5; + valaddr_reg:x8; val_offset:544*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 544*FLEN/8, x10, x1, x4) + +inst_298: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1e2 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x1e5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x35e2; op2val:0x6de5; + valaddr_reg:x8; val_offset:546*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 546*FLEN/8, x10, x1, x4) + +inst_299: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1e2 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x1e5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x35e2; op2val:0x6de5; + valaddr_reg:x8; val_offset:548*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 548*FLEN/8, x10, x1, x4) + +inst_300: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1f6 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x1f9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x35f6; op2val:0x6df9; + valaddr_reg:x8; val_offset:550*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 550*FLEN/8, x10, x1, x4) + +inst_301: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1f6 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x1f9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x35f6; op2val:0x6df9; + valaddr_reg:x8; val_offset:552*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 552*FLEN/8, x10, x1, x4) + +inst_302: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1f6 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x1f9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x35f6; op2val:0x6df9; + valaddr_reg:x8; val_offset:554*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 554*FLEN/8, x10, x1, x4) + +inst_303: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1f6 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x1f9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x35f6; op2val:0x6df9; + valaddr_reg:x8; val_offset:556*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 556*FLEN/8, x10, x1, x4) + +inst_304: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1f6 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x1f9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x35f6; op2val:0x6df9; + valaddr_reg:x8; val_offset:558*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 558*FLEN/8, x10, x1, x4) + +inst_305: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x121 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x124 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3521; op2val:0x6d24; + valaddr_reg:x8; val_offset:560*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 560*FLEN/8, x10, x1, x4) + +inst_306: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x121 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x124 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3521; op2val:0x6d24; + valaddr_reg:x8; val_offset:562*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 562*FLEN/8, x10, x1, x4) + +inst_307: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x121 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x124 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3521; op2val:0x6d24; + valaddr_reg:x8; val_offset:564*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 564*FLEN/8, x10, x1, x4) + +inst_308: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x121 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x124 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3521; op2val:0x6d24; + valaddr_reg:x8; val_offset:566*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 566*FLEN/8, x10, x1, x4) + +inst_309: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x121 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x124 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3521; op2val:0x6d24; + valaddr_reg:x8; val_offset:568*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 568*FLEN/8, x10, x1, x4) + +inst_310: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0b0 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0b2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x34b0; op2val:0x6cb2; + valaddr_reg:x8; val_offset:570*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 570*FLEN/8, x10, x1, x4) + +inst_311: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0b0 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0b2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x34b0; op2val:0x6cb2; + valaddr_reg:x8; val_offset:572*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 572*FLEN/8, x10, x1, x4) + +inst_312: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0b0 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0b2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x34b0; op2val:0x6cb2; + valaddr_reg:x8; val_offset:574*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 574*FLEN/8, x10, x1, x4) + +inst_313: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0b0 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0b2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x34b0; op2val:0x6cb2; + valaddr_reg:x8; val_offset:576*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 576*FLEN/8, x10, x1, x4) + +inst_314: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0b0 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0b2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x34b0; op2val:0x6cb2; + valaddr_reg:x8; val_offset:578*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 578*FLEN/8, x10, x1, x4) + +inst_315: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d2 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3d6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bd2; op2val:0x73d6; + valaddr_reg:x8; val_offset:580*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 580*FLEN/8, x10, x1, x4) + +inst_316: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d2 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3d6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bd2; op2val:0x73d6; + valaddr_reg:x8; val_offset:582*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 582*FLEN/8, x10, x1, x4) + +inst_317: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d2 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3d6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bd2; op2val:0x73d6; + valaddr_reg:x8; val_offset:584*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 584*FLEN/8, x10, x1, x4) + +inst_318: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d2 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3d6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bd2; op2val:0x73d6; + valaddr_reg:x8; val_offset:586*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 586*FLEN/8, x10, x1, x4) + +inst_319: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d2 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3d6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bd2; op2val:0x73d6; + valaddr_reg:x8; val_offset:588*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 588*FLEN/8, x10, x1, x4) + +inst_320: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x12f and fs2 == 0 and fe2 == 0x1b and fm2 == 0x131 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x352f; op2val:0x6d31; + valaddr_reg:x8; val_offset:590*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 590*FLEN/8, x10, x1, x4) + +inst_321: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x12f and fs2 == 0 and fe2 == 0x1b and fm2 == 0x131 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x352f; op2val:0x6d31; + valaddr_reg:x8; val_offset:592*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 592*FLEN/8, x10, x1, x4) + +inst_322: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x12f and fs2 == 0 and fe2 == 0x1b and fm2 == 0x131 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x352f; op2val:0x6d31; + valaddr_reg:x8; val_offset:594*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 594*FLEN/8, x10, x1, x4) + +inst_323: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x12f and fs2 == 0 and fe2 == 0x1b and fm2 == 0x131 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x352f; op2val:0x6d31; + valaddr_reg:x8; val_offset:596*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 596*FLEN/8, x10, x1, x4) + +inst_324: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x12f and fs2 == 0 and fe2 == 0x1b and fm2 == 0x131 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x352f; op2val:0x6d31; + valaddr_reg:x8; val_offset:598*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 598*FLEN/8, x10, x1, x4) + +inst_325: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fd and fs2 == 0 and fe2 == 0x1c and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39fd; op2val:0x7200; + valaddr_reg:x8; val_offset:600*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 600*FLEN/8, x10, x1, x4) + +inst_326: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fd and fs2 == 0 and fe2 == 0x1c and fm2 == 0x200 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39fd; op2val:0x7200; + valaddr_reg:x8; val_offset:602*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 602*FLEN/8, x10, x1, x4) + +inst_327: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fd and fs2 == 0 and fe2 == 0x1c and fm2 == 0x200 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39fd; op2val:0x7200; + valaddr_reg:x8; val_offset:604*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 604*FLEN/8, x10, x1, x4) + +inst_328: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fd and fs2 == 0 and fe2 == 0x1c and fm2 == 0x200 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39fd; op2val:0x7200; + valaddr_reg:x8; val_offset:606*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 606*FLEN/8, x10, x1, x4) + +inst_329: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fd and fs2 == 0 and fe2 == 0x1c and fm2 == 0x200 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39fd; op2val:0x7200; + valaddr_reg:x8; val_offset:608*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 608*FLEN/8, x10, x1, x4) + +inst_330: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x284 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x287 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3684; op2val:0x6e87; + valaddr_reg:x8; val_offset:610*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 610*FLEN/8, x10, x1, x4) + +inst_331: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x284 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x287 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3684; op2val:0x6e87; + valaddr_reg:x8; val_offset:612*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 612*FLEN/8, x10, x1, x4) + +inst_332: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x284 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x287 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3684; op2val:0x6e87; + valaddr_reg:x8; val_offset:614*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 614*FLEN/8, x10, x1, x4) + +inst_333: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x284 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x287 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3684; op2val:0x6e87; + valaddr_reg:x8; val_offset:616*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 616*FLEN/8, x10, x1, x4) + +inst_334: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x284 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x287 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3684; op2val:0x6e87; + valaddr_reg:x8; val_offset:618*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 618*FLEN/8, x10, x1, x4) + +inst_335: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x116 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x119 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3916; op2val:0x7119; + valaddr_reg:x8; val_offset:620*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 620*FLEN/8, x10, x1, x4) + +inst_336: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x116 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x119 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3916; op2val:0x7119; + valaddr_reg:x8; val_offset:622*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 622*FLEN/8, x10, x1, x4) + +inst_337: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x116 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x119 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3916; op2val:0x7119; + valaddr_reg:x8; val_offset:624*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 624*FLEN/8, x10, x1, x4) + +inst_338: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x116 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x119 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3916; op2val:0x7119; + valaddr_reg:x8; val_offset:626*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 626*FLEN/8, x10, x1, x4) + +inst_339: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x116 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x119 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3916; op2val:0x7119; + valaddr_reg:x8; val_offset:628*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 628*FLEN/8, x10, x1, x4) + +inst_340: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x10c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x10e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x390c; op2val:0x710e; + valaddr_reg:x8; val_offset:630*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 630*FLEN/8, x10, x1, x4) + +inst_341: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x10c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x10e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x390c; op2val:0x710e; + valaddr_reg:x8; val_offset:632*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 632*FLEN/8, x10, x1, x4) + +inst_342: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x10c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x10e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x390c; op2val:0x710e; + valaddr_reg:x8; val_offset:634*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 634*FLEN/8, x10, x1, x4) + +inst_343: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x10c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x10e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x390c; op2val:0x710e; + valaddr_reg:x8; val_offset:636*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 636*FLEN/8, x10, x1, x4) + +inst_344: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x10c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x10e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x390c; op2val:0x710e; + valaddr_reg:x8; val_offset:638*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 638*FLEN/8, x10, x1, x4) + +inst_345: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x198 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x19b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3998; op2val:0x719b; + valaddr_reg:x8; val_offset:640*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 640*FLEN/8, x10, x1, x4) + +inst_346: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x198 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x19b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3998; op2val:0x719b; + valaddr_reg:x8; val_offset:642*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 642*FLEN/8, x10, x1, x4) + +inst_347: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x198 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x19b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3998; op2val:0x719b; + valaddr_reg:x8; val_offset:644*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 644*FLEN/8, x10, x1, x4) + +inst_348: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x198 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x19b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3998; op2val:0x719b; + valaddr_reg:x8; val_offset:646*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 646*FLEN/8, x10, x1, x4) + +inst_349: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x198 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x19b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3998; op2val:0x719b; + valaddr_reg:x8; val_offset:648*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 648*FLEN/8, x10, x1, x4) + +inst_350: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x349 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x34d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3349; op2val:0x6b4d; + valaddr_reg:x8; val_offset:650*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 650*FLEN/8, x10, x1, x4) + +inst_351: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x349 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x34d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3349; op2val:0x6b4d; + valaddr_reg:x8; val_offset:652*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 652*FLEN/8, x10, x1, x4) + +inst_352: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x349 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x34d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3349; op2val:0x6b4d; + valaddr_reg:x8; val_offset:654*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 654*FLEN/8, x10, x1, x4) + +inst_353: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x349 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x34d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3349; op2val:0x6b4d; + valaddr_reg:x8; val_offset:656*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 656*FLEN/8, x10, x1, x4) + +inst_354: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x349 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x34d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3349; op2val:0x6b4d; + valaddr_reg:x8; val_offset:658*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 658*FLEN/8, x10, x1, x4) + +inst_355: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2e4 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2e7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x36e4; op2val:0x6ee7; + valaddr_reg:x8; val_offset:660*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 660*FLEN/8, x10, x1, x4) + +inst_356: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2e4 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2e7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x36e4; op2val:0x6ee7; + valaddr_reg:x8; val_offset:662*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 662*FLEN/8, x10, x1, x4) + +inst_357: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2e4 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2e7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x36e4; op2val:0x6ee7; + valaddr_reg:x8; val_offset:664*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 664*FLEN/8, x10, x1, x4) + +inst_358: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2e4 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2e7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x36e4; op2val:0x6ee7; + valaddr_reg:x8; val_offset:666*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 666*FLEN/8, x10, x1, x4) + +inst_359: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2e4 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2e7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x36e4; op2val:0x6ee7; + valaddr_reg:x8; val_offset:668*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 668*FLEN/8, x10, x1, x4) + +inst_360: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x185 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x187 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3985; op2val:0x7187; + valaddr_reg:x8; val_offset:670*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 670*FLEN/8, x10, x1, x4) + +inst_361: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x185 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x187 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3985; op2val:0x7187; + valaddr_reg:x8; val_offset:672*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 672*FLEN/8, x10, x1, x4) + +inst_362: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x185 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x187 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3985; op2val:0x7187; + valaddr_reg:x8; val_offset:674*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 674*FLEN/8, x10, x1, x4) + +inst_363: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x185 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x187 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3985; op2val:0x7187; + valaddr_reg:x8; val_offset:676*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 676*FLEN/8, x10, x1, x4) + +inst_364: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x185 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x187 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3985; op2val:0x7187; + valaddr_reg:x8; val_offset:678*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 678*FLEN/8, x10, x1, x4) + +inst_365: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x247 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x24a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3247; op2val:0x6a4a; + valaddr_reg:x8; val_offset:680*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 680*FLEN/8, x10, x1, x4) + +inst_366: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x247 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x24a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3247; op2val:0x6a4a; + valaddr_reg:x8; val_offset:682*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 682*FLEN/8, x10, x1, x4) + +inst_367: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x247 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x24a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3247; op2val:0x6a4a; + valaddr_reg:x8; val_offset:684*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 684*FLEN/8, x10, x1, x4) + +inst_368: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x247 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x24a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3247; op2val:0x6a4a; + valaddr_reg:x8; val_offset:686*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 686*FLEN/8, x10, x1, x4) + +inst_369: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x247 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x24a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3247; op2val:0x6a4a; + valaddr_reg:x8; val_offset:688*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 688*FLEN/8, x10, x1, x4) + +inst_370: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x280 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x283 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a80; op2val:0x7283; + valaddr_reg:x8; val_offset:690*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 690*FLEN/8, x10, x1, x4) + +inst_371: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x280 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x283 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a80; op2val:0x7283; + valaddr_reg:x8; val_offset:692*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 692*FLEN/8, x10, x1, x4) + +inst_372: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x280 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x283 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a80; op2val:0x7283; + valaddr_reg:x8; val_offset:694*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 694*FLEN/8, x10, x1, x4) + +inst_373: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x280 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x283 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a80; op2val:0x7283; + valaddr_reg:x8; val_offset:696*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 696*FLEN/8, x10, x1, x4) + +inst_374: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x280 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x283 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a80; op2val:0x7283; + valaddr_reg:x8; val_offset:698*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 698*FLEN/8, x10, x1, x4) + +inst_375: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0d4 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0d7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x34d4; op2val:0x6cd7; + valaddr_reg:x8; val_offset:700*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 700*FLEN/8, x10, x1, x4) + +inst_376: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0d4 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0d7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x34d4; op2val:0x6cd7; + valaddr_reg:x8; val_offset:702*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 702*FLEN/8, x10, x1, x4) + +inst_377: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0d4 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0d7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x34d4; op2val:0x6cd7; + valaddr_reg:x8; val_offset:704*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 704*FLEN/8, x10, x1, x4) + +inst_378: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0d4 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0d7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x34d4; op2val:0x6cd7; + valaddr_reg:x8; val_offset:706*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 706*FLEN/8, x10, x1, x4) + +inst_379: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0d4 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0d7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x34d4; op2val:0x6cd7; + valaddr_reg:x8; val_offset:708*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 708*FLEN/8, x10, x1, x4) + +inst_380: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x16c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x16f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x396c; op2val:0x716f; + valaddr_reg:x8; val_offset:710*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 710*FLEN/8, x10, x1, x4) + +inst_381: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x16c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x16f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x396c; op2val:0x716f; + valaddr_reg:x8; val_offset:712*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 712*FLEN/8, x10, x1, x4) + +inst_382: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x16c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x16f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x396c; op2val:0x716f; + valaddr_reg:x8; val_offset:714*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 714*FLEN/8, x10, x1, x4) + +inst_383: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x16c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x16f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x396c; op2val:0x716f; + valaddr_reg:x8; val_offset:716*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 716*FLEN/8, x10, x1, x4) + +inst_384: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x16c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x16f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x396c; op2val:0x716f; + valaddr_reg:x8; val_offset:718*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 718*FLEN/8, x10, x1, x4) + +inst_385: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x154 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x156 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3154; op2val:0x6956; + valaddr_reg:x8; val_offset:720*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 720*FLEN/8, x10, x1, x4) + +inst_386: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x154 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x156 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3154; op2val:0x6956; + valaddr_reg:x8; val_offset:722*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 722*FLEN/8, x10, x1, x4) + +inst_387: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x154 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x156 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3154; op2val:0x6956; + valaddr_reg:x8; val_offset:724*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 724*FLEN/8, x10, x1, x4) + +inst_388: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x154 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x156 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3154; op2val:0x6956; + valaddr_reg:x8; val_offset:726*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 726*FLEN/8, x10, x1, x4) + +inst_389: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x154 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x156 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3154; op2val:0x6956; + valaddr_reg:x8; val_offset:728*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 728*FLEN/8, x10, x1, x4) + +inst_390: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x09f and fs2 == 0 and fe2 == 0x1a and fm2 == 0x0a2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x309f; op2val:0x68a2; + valaddr_reg:x8; val_offset:730*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 730*FLEN/8, x10, x1, x4) + +inst_391: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x09f and fs2 == 0 and fe2 == 0x1a and fm2 == 0x0a2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x309f; op2val:0x68a2; + valaddr_reg:x8; val_offset:732*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 732*FLEN/8, x10, x1, x4) + +inst_392: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x09f and fs2 == 0 and fe2 == 0x1a and fm2 == 0x0a2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x309f; op2val:0x68a2; + valaddr_reg:x8; val_offset:734*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 734*FLEN/8, x10, x1, x4) + +inst_393: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x09f and fs2 == 0 and fe2 == 0x1a and fm2 == 0x0a2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x309f; op2val:0x68a2; + valaddr_reg:x8; val_offset:736*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 736*FLEN/8, x10, x1, x4) + +inst_394: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x09f and fs2 == 0 and fe2 == 0x1a and fm2 == 0x0a2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x309f; op2val:0x68a2; + valaddr_reg:x8; val_offset:738*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 738*FLEN/8, x10, x1, x4) + +inst_395: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x14e and fs2 == 0 and fe2 == 0x1c and fm2 == 0x150 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x394e; op2val:0x7150; + valaddr_reg:x8; val_offset:740*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 740*FLEN/8, x10, x1, x4) + +inst_396: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x14e and fs2 == 0 and fe2 == 0x1c and fm2 == 0x150 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x394e; op2val:0x7150; + valaddr_reg:x8; val_offset:742*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 742*FLEN/8, x10, x1, x4) + +inst_397: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x14e and fs2 == 0 and fe2 == 0x1c and fm2 == 0x150 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x394e; op2val:0x7150; + valaddr_reg:x8; val_offset:744*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 744*FLEN/8, x10, x1, x4) + +inst_398: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x14e and fs2 == 0 and fe2 == 0x1c and fm2 == 0x150 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x394e; op2val:0x7150; + valaddr_reg:x8; val_offset:746*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 746*FLEN/8, x10, x1, x4) + +inst_399: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x14e and fs2 == 0 and fe2 == 0x1c and fm2 == 0x150 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x394e; op2val:0x7150; + valaddr_reg:x8; val_offset:748*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 748*FLEN/8, x10, x1, x4) + +inst_400: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x35e and fs2 == 0 and fe2 == 0x19 and fm2 == 0x362 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2f5e; op2val:0x6762; + valaddr_reg:x8; val_offset:750*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 750*FLEN/8, x10, x1, x4) + +inst_401: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x35e and fs2 == 0 and fe2 == 0x19 and fm2 == 0x362 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2f5e; op2val:0x6762; + valaddr_reg:x8; val_offset:752*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 752*FLEN/8, x10, x1, x4) + +inst_402: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x35e and fs2 == 0 and fe2 == 0x19 and fm2 == 0x362 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2f5e; op2val:0x6762; + valaddr_reg:x8; val_offset:754*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 754*FLEN/8, x10, x1, x4) + +inst_403: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x35e and fs2 == 0 and fe2 == 0x19 and fm2 == 0x362 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2f5e; op2val:0x6762; + valaddr_reg:x8; val_offset:756*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 756*FLEN/8, x10, x1, x4) + +inst_404: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x35e and fs2 == 0 and fe2 == 0x19 and fm2 == 0x362 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2f5e; op2val:0x6762; + valaddr_reg:x8; val_offset:758*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 758*FLEN/8, x10, x1, x4) + +inst_405: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x233 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x236 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a33; op2val:0x7236; + valaddr_reg:x8; val_offset:760*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 760*FLEN/8, x10, x1, x4) + +inst_406: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x233 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x236 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a33; op2val:0x7236; + valaddr_reg:x8; val_offset:762*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 762*FLEN/8, x10, x1, x4) + +inst_407: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x233 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x236 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a33; op2val:0x7236; + valaddr_reg:x8; val_offset:764*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 764*FLEN/8, x10, x1, x4) + +inst_408: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x233 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x236 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a33; op2val:0x7236; + valaddr_reg:x8; val_offset:766*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 766*FLEN/8, x10, x1, x4) + +inst_409: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x233 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x236 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a33; op2val:0x7236; + valaddr_reg:x8; val_offset:768*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 768*FLEN/8, x10, x1, x4) + +inst_410: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x386 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x38a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3786; op2val:0x6f8a; + valaddr_reg:x8; val_offset:770*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 770*FLEN/8, x10, x1, x4) + +inst_411: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x386 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x38a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3786; op2val:0x6f8a; + valaddr_reg:x8; val_offset:772*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 772*FLEN/8, x10, x1, x4) + +inst_412: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x386 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x38a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3786; op2val:0x6f8a; + valaddr_reg:x8; val_offset:774*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 774*FLEN/8, x10, x1, x4) + +inst_413: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x386 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x38a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3786; op2val:0x6f8a; + valaddr_reg:x8; val_offset:776*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 776*FLEN/8, x10, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_3) + +inst_414: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x386 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x38a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3786; op2val:0x6f8a; + valaddr_reg:x8; val_offset:778*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 778*FLEN/8, x10, x1, x4) + +inst_415: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x22f and fs2 == 0 and fe2 == 0x1a and fm2 == 0x232 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x322f; op2val:0x6a32; + valaddr_reg:x8; val_offset:780*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 780*FLEN/8, x10, x1, x4) + +inst_416: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x22f and fs2 == 0 and fe2 == 0x1a and fm2 == 0x232 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x322f; op2val:0x6a32; + valaddr_reg:x8; val_offset:782*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 782*FLEN/8, x10, x1, x4) + +inst_417: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x22f and fs2 == 0 and fe2 == 0x1a and fm2 == 0x232 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x322f; op2val:0x6a32; + valaddr_reg:x8; val_offset:784*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 784*FLEN/8, x10, x1, x4) + +inst_418: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x22f and fs2 == 0 and fe2 == 0x1a and fm2 == 0x232 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x322f; op2val:0x6a32; + valaddr_reg:x8; val_offset:786*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 786*FLEN/8, x10, x1, x4) + +inst_419: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x22f and fs2 == 0 and fe2 == 0x1a and fm2 == 0x232 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x322f; op2val:0x6a32; + valaddr_reg:x8; val_offset:788*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 788*FLEN/8, x10, x1, x4) + +inst_420: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x288 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0e7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a88; op2val:0x74e7; + valaddr_reg:x8; val_offset:790*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 790*FLEN/8, x10, x1, x4) + +inst_421: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x288 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0e7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a88; op2val:0x74e7; + valaddr_reg:x8; val_offset:792*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 792*FLEN/8, x10, x1, x4) + +inst_422: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x288 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0e7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a88; op2val:0x74e7; + valaddr_reg:x8; val_offset:794*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 794*FLEN/8, x10, x1, x4) + +inst_423: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x288 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0e7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a88; op2val:0x74e7; + valaddr_reg:x8; val_offset:796*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 796*FLEN/8, x10, x1, x4) + +inst_424: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x288 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0e7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a88; op2val:0x74e7; + valaddr_reg:x8; val_offset:798*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 798*FLEN/8, x10, x1, x4) + +inst_425: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x22b and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0a1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x322b; op2val:0x6ca1; + valaddr_reg:x8; val_offset:800*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 800*FLEN/8, x10, x1, x4) + +inst_426: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x22b and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0a1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x322b; op2val:0x6ca1; + valaddr_reg:x8; val_offset:802*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 802*FLEN/8, x10, x1, x4) + +inst_427: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x22b and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0a1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x322b; op2val:0x6ca1; + valaddr_reg:x8; val_offset:804*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 804*FLEN/8, x10, x1, x4) + +inst_428: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x22b and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0a1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x322b; op2val:0x6ca1; + valaddr_reg:x8; val_offset:806*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 806*FLEN/8, x10, x1, x4) + +inst_429: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x22b and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0a1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x322b; op2val:0x6ca1; + valaddr_reg:x8; val_offset:808*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 808*FLEN/8, x10, x1, x4) + +inst_430: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x233 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0a7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3233; op2val:0x6ca7; + valaddr_reg:x8; val_offset:810*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 810*FLEN/8, x10, x1, x4) + +inst_431: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x233 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0a7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3233; op2val:0x6ca7; + valaddr_reg:x8; val_offset:812*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 812*FLEN/8, x10, x1, x4) + +inst_432: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x233 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0a7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3233; op2val:0x6ca7; + valaddr_reg:x8; val_offset:814*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 814*FLEN/8, x10, x1, x4) + +inst_433: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x233 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0a7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3233; op2val:0x6ca7; + valaddr_reg:x8; val_offset:816*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 816*FLEN/8, x10, x1, x4) + +inst_434: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x233 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0a7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3233; op2val:0x6ca7; + valaddr_reg:x8; val_offset:818*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 818*FLEN/8, x10, x1, x4) + +inst_435: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2f6 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x13a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3af6; op2val:0x753a; + valaddr_reg:x8; val_offset:820*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 820*FLEN/8, x10, x1, x4) + +inst_436: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2f6 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x13a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3af6; op2val:0x753a; + valaddr_reg:x8; val_offset:822*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 822*FLEN/8, x10, x1, x4) + +inst_437: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2f6 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x13a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3af6; op2val:0x753a; + valaddr_reg:x8; val_offset:824*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 824*FLEN/8, x10, x1, x4) + +inst_438: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2f6 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x13a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3af6; op2val:0x753a; + valaddr_reg:x8; val_offset:826*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 826*FLEN/8, x10, x1, x4) + +inst_439: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2f6 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x13a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3af6; op2val:0x753a; + valaddr_reg:x8; val_offset:828*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 828*FLEN/8, x10, x1, x4) + +inst_440: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x298 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0f3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3298; op2val:0x6cf3; + valaddr_reg:x8; val_offset:830*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 830*FLEN/8, x10, x1, x4) + +inst_441: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x298 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0f3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3298; op2val:0x6cf3; + valaddr_reg:x8; val_offset:832*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 832*FLEN/8, x10, x1, x4) + +inst_442: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x298 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0f3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3298; op2val:0x6cf3; + valaddr_reg:x8; val_offset:834*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 834*FLEN/8, x10, x1, x4) + +inst_443: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x298 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0f3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3298; op2val:0x6cf3; + valaddr_reg:x8; val_offset:836*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 836*FLEN/8, x10, x1, x4) + +inst_444: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x298 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0f3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3298; op2val:0x6cf3; + valaddr_reg:x8; val_offset:838*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 838*FLEN/8, x10, x1, x4) + +inst_445: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x13a and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3d9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x393a; op2val:0x73d9; + valaddr_reg:x8; val_offset:840*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 840*FLEN/8, x10, x1, x4) + +inst_446: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x13a and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3d9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x393a; op2val:0x73d9; + valaddr_reg:x8; val_offset:842*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 842*FLEN/8, x10, x1, x4) + +inst_447: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x13a and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3d9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x393a; op2val:0x73d9; + valaddr_reg:x8; val_offset:844*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 844*FLEN/8, x10, x1, x4) + +inst_448: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x13a and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3d9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x393a; op2val:0x73d9; + valaddr_reg:x8; val_offset:846*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 846*FLEN/8, x10, x1, x4) + +inst_449: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x13a and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3d9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x393a; op2val:0x73d9; + valaddr_reg:x8; val_offset:848*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 848*FLEN/8, x10, x1, x4) + +inst_450: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0a4 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x38a4; op2val:0x72f8; + valaddr_reg:x8; val_offset:850*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 850*FLEN/8, x10, x1, x4) + +inst_451: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0a4 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2f8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x38a4; op2val:0x72f8; + valaddr_reg:x8; val_offset:852*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 852*FLEN/8, x10, x1, x4) + +inst_452: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0a4 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2f8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x38a4; op2val:0x72f8; + valaddr_reg:x8; val_offset:854*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 854*FLEN/8, x10, x1, x4) + +inst_453: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0a4 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2f8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x38a4; op2val:0x72f8; + valaddr_reg:x8; val_offset:856*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 856*FLEN/8, x10, x1, x4) + +inst_454: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0a4 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2f8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x38a4; op2val:0x72f8; + valaddr_reg:x8; val_offset:858*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 858*FLEN/8, x10, x1, x4) + +inst_455: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x115 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x3a1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d15; op2val:0x67a1; + valaddr_reg:x8; val_offset:860*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 860*FLEN/8, x10, x1, x4) + +inst_456: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x115 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x3a1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d15; op2val:0x67a1; + valaddr_reg:x8; val_offset:862*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 862*FLEN/8, x10, x1, x4) + +inst_457: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x115 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x3a1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d15; op2val:0x67a1; + valaddr_reg:x8; val_offset:864*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 864*FLEN/8, x10, x1, x4) + +inst_458: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x115 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x3a1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d15; op2val:0x67a1; + valaddr_reg:x8; val_offset:866*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 866*FLEN/8, x10, x1, x4) + +inst_459: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x115 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x3a1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d15; op2val:0x67a1; + valaddr_reg:x8; val_offset:868*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 868*FLEN/8, x10, x1, x4) + +inst_460: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f6 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1fa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bf6; op2val:0x75fa; + valaddr_reg:x8; val_offset:870*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 870*FLEN/8, x10, x1, x4) + +inst_461: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f6 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1fa and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bf6; op2val:0x75fa; + valaddr_reg:x8; val_offset:872*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 872*FLEN/8, x10, x1, x4) + +inst_462: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f6 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1fa and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bf6; op2val:0x75fa; + valaddr_reg:x8; val_offset:874*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 874*FLEN/8, x10, x1, x4) + +inst_463: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f6 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1fa and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bf6; op2val:0x75fa; + valaddr_reg:x8; val_offset:876*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 876*FLEN/8, x10, x1, x4) + +inst_464: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f6 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1fa and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bf6; op2val:0x75fa; + valaddr_reg:x8; val_offset:878*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 878*FLEN/8, x10, x1, x4) + +inst_465: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3af and fs2 == 0 and fe2 == 0x1a and fm2 == 0x1c4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2faf; op2val:0x69c4; + valaddr_reg:x8; val_offset:880*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 880*FLEN/8, x10, x1, x4) + +inst_466: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3af and fs2 == 0 and fe2 == 0x1a and fm2 == 0x1c4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2faf; op2val:0x69c4; + valaddr_reg:x8; val_offset:882*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 882*FLEN/8, x10, x1, x4) + +inst_467: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3af and fs2 == 0 and fe2 == 0x1a and fm2 == 0x1c4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2faf; op2val:0x69c4; + valaddr_reg:x8; val_offset:884*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 884*FLEN/8, x10, x1, x4) + +inst_468: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3af and fs2 == 0 and fe2 == 0x1a and fm2 == 0x1c4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2faf; op2val:0x69c4; + valaddr_reg:x8; val_offset:886*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 886*FLEN/8, x10, x1, x4) + +inst_469: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3af and fs2 == 0 and fe2 == 0x1a and fm2 == 0x1c4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2faf; op2val:0x69c4; + valaddr_reg:x8; val_offset:888*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 888*FLEN/8, x10, x1, x4) + +inst_470: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x086 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2cb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3886; op2val:0x72cb; + valaddr_reg:x8; val_offset:890*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 890*FLEN/8, x10, x1, x4) + +inst_471: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x086 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2cb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3886; op2val:0x72cb; + valaddr_reg:x8; val_offset:892*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 892*FLEN/8, x10, x1, x4) + +inst_472: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x086 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2cb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3886; op2val:0x72cb; + valaddr_reg:x8; val_offset:894*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 894*FLEN/8, x10, x1, x4) + +inst_473: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x086 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2cb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3886; op2val:0x72cb; + valaddr_reg:x8; val_offset:896*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 896*FLEN/8, x10, x1, x4) + +inst_474: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x086 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2cb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3886; op2val:0x72cb; + valaddr_reg:x8; val_offset:898*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 898*FLEN/8, x10, x1, x4) + +inst_475: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0a6 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x2fb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ca6; op2val:0x66fb; + valaddr_reg:x8; val_offset:900*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 900*FLEN/8, x10, x1, x4) + +inst_476: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0a6 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x2fb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ca6; op2val:0x66fb; + valaddr_reg:x8; val_offset:902*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 902*FLEN/8, x10, x1, x4) + +inst_477: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0a6 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x2fb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ca6; op2val:0x66fb; + valaddr_reg:x8; val_offset:904*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 904*FLEN/8, x10, x1, x4) + +inst_478: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0a6 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x2fb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ca6; op2val:0x66fb; + valaddr_reg:x8; val_offset:906*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 906*FLEN/8, x10, x1, x4) + +inst_479: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0a6 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x2fb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ca6; op2val:0x66fb; + valaddr_reg:x8; val_offset:908*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 908*FLEN/8, x10, x1, x4) + +inst_480: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x012 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x21c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3412; op2val:0x6e1c; + valaddr_reg:x8; val_offset:910*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 910*FLEN/8, x10, x1, x4) + +inst_481: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x012 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x21c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3412; op2val:0x6e1c; + valaddr_reg:x8; val_offset:912*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 912*FLEN/8, x10, x1, x4) + +inst_482: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x012 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x21c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3412; op2val:0x6e1c; + valaddr_reg:x8; val_offset:914*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 914*FLEN/8, x10, x1, x4) + +inst_483: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x012 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x21c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3412; op2val:0x6e1c; + valaddr_reg:x8; val_offset:916*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 916*FLEN/8, x10, x1, x4) + +inst_484: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x012 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x21c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3412; op2val:0x6e1c; + valaddr_reg:x8; val_offset:918*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 918*FLEN/8, x10, x1, x4) + +inst_485: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x164 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x00c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3564; op2val:0x700c; + valaddr_reg:x8; val_offset:920*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 920*FLEN/8, x10, x1, x4) + +inst_486: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x164 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x00c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3564; op2val:0x700c; + valaddr_reg:x8; val_offset:922*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 922*FLEN/8, x10, x1, x4) + +inst_487: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x164 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x00c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3564; op2val:0x700c; + valaddr_reg:x8; val_offset:924*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 924*FLEN/8, x10, x1, x4) + +inst_488: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x164 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x00c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3564; op2val:0x700c; + valaddr_reg:x8; val_offset:926*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 926*FLEN/8, x10, x1, x4) + +inst_489: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x164 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x00c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3564; op2val:0x700c; + valaddr_reg:x8; val_offset:928*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 928*FLEN/8, x10, x1, x4) + +inst_490: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1b0 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x045 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39b0; op2val:0x7445; + valaddr_reg:x8; val_offset:930*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 930*FLEN/8, x10, x1, x4) + +inst_491: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1b0 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x045 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39b0; op2val:0x7445; + valaddr_reg:x8; val_offset:932*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 932*FLEN/8, x10, x1, x4) + +inst_492: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1b0 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x045 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39b0; op2val:0x7445; + valaddr_reg:x8; val_offset:934*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 934*FLEN/8, x10, x1, x4) + +inst_493: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1b0 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x045 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39b0; op2val:0x7445; + valaddr_reg:x8; val_offset:936*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 936*FLEN/8, x10, x1, x4) + +inst_494: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1b0 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x045 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39b0; op2val:0x7445; + valaddr_reg:x8; val_offset:938*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 938*FLEN/8, x10, x1, x4) + +inst_495: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x22e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0a3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a2e; op2val:0x74a3; + valaddr_reg:x8; val_offset:940*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 940*FLEN/8, x10, x1, x4) + +inst_496: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x22e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0a3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a2e; op2val:0x74a3; + valaddr_reg:x8; val_offset:942*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 942*FLEN/8, x10, x1, x4) + +inst_497: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x22e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0a3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a2e; op2val:0x74a3; + valaddr_reg:x8; val_offset:944*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 944*FLEN/8, x10, x1, x4) + +inst_498: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x22e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0a3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a2e; op2val:0x74a3; + valaddr_reg:x8; val_offset:946*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 946*FLEN/8, x10, x1, x4) + +inst_499: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x22e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0a3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a2e; op2val:0x74a3; + valaddr_reg:x8; val_offset:948*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 948*FLEN/8, x10, x1, x4) + +inst_500: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x294 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3694; op2val:0x70f0; + valaddr_reg:x8; val_offset:950*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 950*FLEN/8, x10, x1, x4) + +inst_501: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x294 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0f0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3694; op2val:0x70f0; + valaddr_reg:x8; val_offset:952*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 952*FLEN/8, x10, x1, x4) + +inst_502: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x294 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0f0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3694; op2val:0x70f0; + valaddr_reg:x8; val_offset:954*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 954*FLEN/8, x10, x1, x4) + +inst_503: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x294 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0f0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3694; op2val:0x70f0; + valaddr_reg:x8; val_offset:956*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 956*FLEN/8, x10, x1, x4) + +inst_504: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x294 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0f0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3694; op2val:0x70f0; + valaddr_reg:x8; val_offset:958*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 958*FLEN/8, x10, x1, x4) + +inst_505: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x213 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x08f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3213; op2val:0x6c8f; + valaddr_reg:x8; val_offset:960*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 960*FLEN/8, x10, x1, x4) + +inst_506: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x213 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x08f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3213; op2val:0x6c8f; + valaddr_reg:x8; val_offset:962*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 962*FLEN/8, x10, x1, x4) + +inst_507: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x213 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x08f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3213; op2val:0x6c8f; + valaddr_reg:x8; val_offset:964*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 964*FLEN/8, x10, x1, x4) + +inst_508: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x213 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x08f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3213; op2val:0x6c8f; + valaddr_reg:x8; val_offset:966*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 966*FLEN/8, x10, x1, x4) + +inst_509: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x213 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x08f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3213; op2val:0x6c8f; + valaddr_reg:x8; val_offset:968*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 968*FLEN/8, x10, x1, x4) + +inst_510: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x22b and fs2 == 0 and fe2 == 0x1a and fm2 == 0x0a1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e2b; op2val:0x68a1; + valaddr_reg:x8; val_offset:970*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 970*FLEN/8, x10, x1, x4) + +inst_511: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x22b and fs2 == 0 and fe2 == 0x1a and fm2 == 0x0a1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e2b; op2val:0x68a1; + valaddr_reg:x8; val_offset:972*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 972*FLEN/8, x10, x1, x4) + +inst_512: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x22b and fs2 == 0 and fe2 == 0x1a and fm2 == 0x0a1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e2b; op2val:0x68a1; + valaddr_reg:x8; val_offset:974*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 974*FLEN/8, x10, x1, x4) + +inst_513: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x22b and fs2 == 0 and fe2 == 0x1a and fm2 == 0x0a1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e2b; op2val:0x68a1; + valaddr_reg:x8; val_offset:976*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 976*FLEN/8, x10, x1, x4) + +inst_514: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x22b and fs2 == 0 and fe2 == 0x1a and fm2 == 0x0a1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e2b; op2val:0x68a1; + valaddr_reg:x8; val_offset:978*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 978*FLEN/8, x10, x1, x4) + +inst_515: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0e0 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x351 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ce0; op2val:0x6751; + valaddr_reg:x8; val_offset:980*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 980*FLEN/8, x10, x1, x4) + +inst_516: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0e0 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x351 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ce0; op2val:0x6751; + valaddr_reg:x8; val_offset:982*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 982*FLEN/8, x10, x1, x4) + +inst_517: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0e0 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x351 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ce0; op2val:0x6751; + valaddr_reg:x8; val_offset:984*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 984*FLEN/8, x10, x1, x4) + +inst_518: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0e0 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x351 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ce0; op2val:0x6751; + valaddr_reg:x8; val_offset:986*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 986*FLEN/8, x10, x1, x4) + +inst_519: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0e0 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x351 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ce0; op2val:0x6751; + valaddr_reg:x8; val_offset:988*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 988*FLEN/8, x10, x1, x4) + +inst_520: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x26c and fs2 == 0 and fe2 == 0x1a and fm2 == 0x0d2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e6c; op2val:0x68d2; + valaddr_reg:x8; val_offset:990*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 990*FLEN/8, x10, x1, x4) + +inst_521: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x26c and fs2 == 0 and fe2 == 0x1a and fm2 == 0x0d2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e6c; op2val:0x68d2; + valaddr_reg:x8; val_offset:992*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 992*FLEN/8, x10, x1, x4) + +inst_522: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x26c and fs2 == 0 and fe2 == 0x1a and fm2 == 0x0d2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e6c; op2val:0x68d2; + valaddr_reg:x8; val_offset:994*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 994*FLEN/8, x10, x1, x4) + +inst_523: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x26c and fs2 == 0 and fe2 == 0x1a and fm2 == 0x0d2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e6c; op2val:0x68d2; + valaddr_reg:x8; val_offset:996*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 996*FLEN/8, x10, x1, x4) + +inst_524: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x26c and fs2 == 0 and fe2 == 0x1a and fm2 == 0x0d2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e6c; op2val:0x68d2; + valaddr_reg:x8; val_offset:998*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 998*FLEN/8, x10, x1, x4) + +inst_525: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e5 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1ed and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3be5; op2val:0x75ed; + valaddr_reg:x8; val_offset:1000*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1000*FLEN/8, x10, x1, x4) + +inst_526: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e5 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1ed and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3be5; op2val:0x75ed; + valaddr_reg:x8; val_offset:1002*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1002*FLEN/8, x10, x1, x4) + +inst_527: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e5 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1ed and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3be5; op2val:0x75ed; + valaddr_reg:x8; val_offset:1004*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1004*FLEN/8, x10, x1, x4) + +inst_528: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e5 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1ed and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3be5; op2val:0x75ed; + valaddr_reg:x8; val_offset:1006*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1006*FLEN/8, x10, x1, x4) + +inst_529: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e5 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1ed and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3be5; op2val:0x75ed; + valaddr_reg:x8; val_offset:1008*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1008*FLEN/8, x10, x1, x4) + +inst_530: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2a0 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0f9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aa0; op2val:0x74f9; + valaddr_reg:x8; val_offset:1010*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1010*FLEN/8, x10, x1, x4) + +inst_531: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2a0 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0f9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aa0; op2val:0x74f9; + valaddr_reg:x8; val_offset:1012*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1012*FLEN/8, x10, x1, x4) + +inst_532: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2a0 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0f9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aa0; op2val:0x74f9; + valaddr_reg:x8; val_offset:1014*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1014*FLEN/8, x10, x1, x4) + +inst_533: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2a0 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0f9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aa0; op2val:0x74f9; + valaddr_reg:x8; val_offset:1016*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1016*FLEN/8, x10, x1, x4) + +inst_534: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2a0 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0f9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aa0; op2val:0x74f9; + valaddr_reg:x8; val_offset:1018*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1018*FLEN/8, x10, x1, x4) + +inst_535: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0b0 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x30a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x38b0; op2val:0x730a; + valaddr_reg:x8; val_offset:1020*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1020*FLEN/8, x10, x1, x4) + +inst_536: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0b0 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x30a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x38b0; op2val:0x730a; + valaddr_reg:x8; val_offset:1022*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1022*FLEN/8, x10, x1, x4) + +inst_537: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0b0 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x30a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x38b0; op2val:0x730a; + valaddr_reg:x8; val_offset:1024*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1024*FLEN/8, x10, x1, x4) + +inst_538: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0b0 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x30a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x38b0; op2val:0x730a; + valaddr_reg:x8; val_offset:1026*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1026*FLEN/8, x10, x1, x4) + +inst_539: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0b0 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x30a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x38b0; op2val:0x730a; + valaddr_reg:x8; val_offset:1028*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1028*FLEN/8, x10, x1, x4) + +inst_540: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x234 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0a8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3634; op2val:0x70a8; + valaddr_reg:x8; val_offset:1030*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1030*FLEN/8, x10, x1, x4) + +inst_541: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x234 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0a8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3634; op2val:0x70a8; + valaddr_reg:x8; val_offset:1032*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1032*FLEN/8, x10, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_4) + +inst_542: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x234 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0a8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3634; op2val:0x70a8; + valaddr_reg:x8; val_offset:1034*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1034*FLEN/8, x10, x1, x4) + +inst_543: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x234 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0a8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3634; op2val:0x70a8; + valaddr_reg:x8; val_offset:1036*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1036*FLEN/8, x10, x1, x4) + +inst_544: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x234 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0a8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3634; op2val:0x70a8; + valaddr_reg:x8; val_offset:1038*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1038*FLEN/8, x10, x1, x4) + +inst_545: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fa and fs2 == 0 and fe2 == 0x1d and fm2 == 0x07d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39fa; op2val:0x747d; + valaddr_reg:x8; val_offset:1040*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1040*FLEN/8, x10, x1, x4) + +inst_546: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fa and fs2 == 0 and fe2 == 0x1d and fm2 == 0x07d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39fa; op2val:0x747d; + valaddr_reg:x8; val_offset:1042*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1042*FLEN/8, x10, x1, x4) + +inst_547: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fa and fs2 == 0 and fe2 == 0x1d and fm2 == 0x07d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39fa; op2val:0x747d; + valaddr_reg:x8; val_offset:1044*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1044*FLEN/8, x10, x1, x4) + +inst_548: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fa and fs2 == 0 and fe2 == 0x1d and fm2 == 0x07d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39fa; op2val:0x747d; + valaddr_reg:x8; val_offset:1046*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1046*FLEN/8, x10, x1, x4) + +inst_549: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fa and fs2 == 0 and fe2 == 0x1d and fm2 == 0x07d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39fa; op2val:0x747d; + valaddr_reg:x8; val_offset:1048*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1048*FLEN/8, x10, x1, x4) + +inst_550: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02e and fs2 == 0 and fe2 == 0x1c and fm2 == 0x247 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x382e; op2val:0x7247; + valaddr_reg:x8; val_offset:1050*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1050*FLEN/8, x10, x1, x4) + +inst_551: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02e and fs2 == 0 and fe2 == 0x1c and fm2 == 0x247 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x382e; op2val:0x7247; + valaddr_reg:x8; val_offset:1052*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1052*FLEN/8, x10, x1, x4) + +inst_552: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02e and fs2 == 0 and fe2 == 0x1c and fm2 == 0x247 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x382e; op2val:0x7247; + valaddr_reg:x8; val_offset:1054*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1054*FLEN/8, x10, x1, x4) + +inst_553: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02e and fs2 == 0 and fe2 == 0x1c and fm2 == 0x247 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x382e; op2val:0x7247; + valaddr_reg:x8; val_offset:1056*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1056*FLEN/8, x10, x1, x4) + +inst_554: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02e and fs2 == 0 and fe2 == 0x1c and fm2 == 0x247 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x382e; op2val:0x7247; + valaddr_reg:x8; val_offset:1058*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1058*FLEN/8, x10, x1, x4) + +inst_555: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x12f and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3c9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x392f; op2val:0x73c9; + valaddr_reg:x8; val_offset:1060*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1060*FLEN/8, x10, x1, x4) + +inst_556: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x12f and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3c9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x392f; op2val:0x73c9; + valaddr_reg:x8; val_offset:1062*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1062*FLEN/8, x10, x1, x4) + +inst_557: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x12f and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3c9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x392f; op2val:0x73c9; + valaddr_reg:x8; val_offset:1064*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1064*FLEN/8, x10, x1, x4) + +inst_558: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x12f and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3c9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x392f; op2val:0x73c9; + valaddr_reg:x8; val_offset:1066*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1066*FLEN/8, x10, x1, x4) + +inst_559: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x12f and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3c9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x392f; op2val:0x73c9; + valaddr_reg:x8; val_offset:1068*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1068*FLEN/8, x10, x1, x4) + +inst_560: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x372 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x196 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3772; op2val:0x7196; + valaddr_reg:x8; val_offset:1070*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1070*FLEN/8, x10, x1, x4) + +inst_561: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x372 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x196 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3772; op2val:0x7196; + valaddr_reg:x8; val_offset:1072*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1072*FLEN/8, x10, x1, x4) + +inst_562: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x372 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x196 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3772; op2val:0x7196; + valaddr_reg:x8; val_offset:1074*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1074*FLEN/8, x10, x1, x4) + +inst_563: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x372 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x196 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3772; op2val:0x7196; + valaddr_reg:x8; val_offset:1076*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1076*FLEN/8, x10, x1, x4) + +inst_564: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x372 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x196 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3772; op2val:0x7196; + valaddr_reg:x8; val_offset:1078*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1078*FLEN/8, x10, x1, x4) + +inst_565: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2a1 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0fa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aa1; op2val:0x74fa; + valaddr_reg:x8; val_offset:1080*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1080*FLEN/8, x10, x1, x4) + +inst_566: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2a1 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0fa and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aa1; op2val:0x74fa; + valaddr_reg:x8; val_offset:1082*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1082*FLEN/8, x10, x1, x4) + +inst_567: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2a1 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0fa and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aa1; op2val:0x74fa; + valaddr_reg:x8; val_offset:1084*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1084*FLEN/8, x10, x1, x4) + +inst_568: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2a1 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0fa and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aa1; op2val:0x74fa; + valaddr_reg:x8; val_offset:1086*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1086*FLEN/8, x10, x1, x4) + +inst_569: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2a1 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0fa and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aa1; op2val:0x74fa; + valaddr_reg:x8; val_offset:1088*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1088*FLEN/8, x10, x1, x4) + +inst_570: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x102 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x385 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d02; op2val:0x6785; + valaddr_reg:x8; val_offset:1090*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1090*FLEN/8, x10, x1, x4) + +inst_571: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x102 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x385 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d02; op2val:0x6785; + valaddr_reg:x8; val_offset:1092*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1092*FLEN/8, x10, x1, x4) + +inst_572: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x102 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x385 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d02; op2val:0x6785; + valaddr_reg:x8; val_offset:1094*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1094*FLEN/8, x10, x1, x4) + +inst_573: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x102 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x385 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d02; op2val:0x6785; + valaddr_reg:x8; val_offset:1096*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1096*FLEN/8, x10, x1, x4) + +inst_574: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x102 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x385 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d02; op2val:0x6785; + valaddr_reg:x8; val_offset:1098*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1098*FLEN/8, x10, x1, x4) + +inst_575: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1a6 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x03d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x31a6; op2val:0x6c3d; + valaddr_reg:x8; val_offset:1100*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1100*FLEN/8, x10, x1, x4) + +inst_576: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1a6 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x03d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x31a6; op2val:0x6c3d; + valaddr_reg:x8; val_offset:1102*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1102*FLEN/8, x10, x1, x4) + +inst_577: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1a6 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x03d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x31a6; op2val:0x6c3d; + valaddr_reg:x8; val_offset:1104*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1104*FLEN/8, x10, x1, x4) + +inst_578: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1a6 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x03d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x31a6; op2val:0x6c3d; + valaddr_reg:x8; val_offset:1106*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1106*FLEN/8, x10, x1, x4) + +inst_579: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1a6 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x03d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x31a6; op2val:0x6c3d; + valaddr_reg:x8; val_offset:1108*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1108*FLEN/8, x10, x1, x4) + +inst_580: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1f1 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x076 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x35f1; op2val:0x7076; + valaddr_reg:x8; val_offset:1110*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1110*FLEN/8, x10, x1, x4) + +inst_581: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1f1 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x076 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x35f1; op2val:0x7076; + valaddr_reg:x8; val_offset:1112*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1112*FLEN/8, x10, x1, x4) + +inst_582: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1f1 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x076 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x35f1; op2val:0x7076; + valaddr_reg:x8; val_offset:1114*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1114*FLEN/8, x10, x1, x4) + +inst_583: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1f1 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x076 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x35f1; op2val:0x7076; + valaddr_reg:x8; val_offset:1116*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1116*FLEN/8, x10, x1, x4) + +inst_584: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1f1 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x076 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x35f1; op2val:0x7076; + valaddr_reg:x8; val_offset:1118*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1118*FLEN/8, x10, x1, x4) + +inst_585: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x399 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1b4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b99; op2val:0x75b4; + valaddr_reg:x8; val_offset:1120*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1120*FLEN/8, x10, x1, x4) + +inst_586: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x399 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1b4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b99; op2val:0x75b4; + valaddr_reg:x8; val_offset:1122*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1122*FLEN/8, x10, x1, x4) + +inst_587: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x399 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1b4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b99; op2val:0x75b4; + valaddr_reg:x8; val_offset:1124*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1124*FLEN/8, x10, x1, x4) + +inst_588: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x399 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1b4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b99; op2val:0x75b4; + valaddr_reg:x8; val_offset:1126*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1126*FLEN/8, x10, x1, x4) + +inst_589: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x399 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1b4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b99; op2val:0x75b4; + valaddr_reg:x8; val_offset:1128*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1128*FLEN/8, x10, x1, x4) + +inst_590: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1d9 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x064 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39d9; op2val:0x7464; + valaddr_reg:x8; val_offset:1130*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1130*FLEN/8, x10, x1, x4) + +inst_591: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1d9 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x064 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39d9; op2val:0x7464; + valaddr_reg:x8; val_offset:1132*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1132*FLEN/8, x10, x1, x4) + +inst_592: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1d9 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x064 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39d9; op2val:0x7464; + valaddr_reg:x8; val_offset:1134*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1134*FLEN/8, x10, x1, x4) + +inst_593: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1d9 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x064 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39d9; op2val:0x7464; + valaddr_reg:x8; val_offset:1136*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1136*FLEN/8, x10, x1, x4) + +inst_594: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1d9 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x064 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39d9; op2val:0x7464; + valaddr_reg:x8; val_offset:1138*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1138*FLEN/8, x10, x1, x4) + +inst_595: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x09d and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2ee and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x389d; op2val:0x72ee; + valaddr_reg:x8; val_offset:1140*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1140*FLEN/8, x10, x1, x4) + +inst_596: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x09d and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2ee and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x389d; op2val:0x72ee; + valaddr_reg:x8; val_offset:1142*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1142*FLEN/8, x10, x1, x4) + +inst_597: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x09d and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2ee and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x389d; op2val:0x72ee; + valaddr_reg:x8; val_offset:1144*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1144*FLEN/8, x10, x1, x4) + +inst_598: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x09d and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2ee and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x389d; op2val:0x72ee; + valaddr_reg:x8; val_offset:1146*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1146*FLEN/8, x10, x1, x4) + +inst_599: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x09d and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2ee and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x389d; op2val:0x72ee; + valaddr_reg:x8; val_offset:1148*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1148*FLEN/8, x10, x1, x4) + +inst_600: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x327 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x15e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3327; op2val:0x6d5e; + valaddr_reg:x8; val_offset:1150*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1150*FLEN/8, x10, x1, x4) + +inst_601: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x327 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x15e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3327; op2val:0x6d5e; + valaddr_reg:x8; val_offset:1152*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1152*FLEN/8, x10, x1, x4) + +inst_602: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x327 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x15e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3327; op2val:0x6d5e; + valaddr_reg:x8; val_offset:1154*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1154*FLEN/8, x10, x1, x4) + +inst_603: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x327 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x15e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3327; op2val:0x6d5e; + valaddr_reg:x8; val_offset:1156*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1156*FLEN/8, x10, x1, x4) + +inst_604: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x327 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x15e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3327; op2val:0x6d5e; + valaddr_reg:x8; val_offset:1158*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1158*FLEN/8, x10, x1, x4) + +inst_605: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x38f and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1ac and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b8f; op2val:0x75ac; + valaddr_reg:x8; val_offset:1160*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1160*FLEN/8, x10, x1, x4) + +inst_606: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x38f and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1ac and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b8f; op2val:0x75ac; + valaddr_reg:x8; val_offset:1162*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1162*FLEN/8, x10, x1, x4) + +inst_607: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x38f and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1ac and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b8f; op2val:0x75ac; + valaddr_reg:x8; val_offset:1164*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1164*FLEN/8, x10, x1, x4) + +inst_608: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x38f and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1ac and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b8f; op2val:0x75ac; + valaddr_reg:x8; val_offset:1166*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1166*FLEN/8, x10, x1, x4) + +inst_609: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x38f and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1ac and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b8f; op2val:0x75ac; + valaddr_reg:x8; val_offset:1168*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1168*FLEN/8, x10, x1, x4) + +inst_610: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x300 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x141 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b00; op2val:0x7541; + valaddr_reg:x8; val_offset:1170*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1170*FLEN/8, x10, x1, x4) + +inst_611: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x300 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x141 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b00; op2val:0x7541; + valaddr_reg:x8; val_offset:1172*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1172*FLEN/8, x10, x1, x4) + +inst_612: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x300 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x141 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b00; op2val:0x7541; + valaddr_reg:x8; val_offset:1174*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1174*FLEN/8, x10, x1, x4) + +inst_613: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x300 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x141 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b00; op2val:0x7541; + valaddr_reg:x8; val_offset:1176*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1176*FLEN/8, x10, x1, x4) + +inst_614: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x300 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x141 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b00; op2val:0x7541; + valaddr_reg:x8; val_offset:1178*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1178*FLEN/8, x10, x1, x4) + +inst_615: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x27d and fs2 == 0 and fe2 == 0x18 and fm2 == 0x0de and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x267d; op2val:0x60de; + valaddr_reg:x8; val_offset:1180*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1180*FLEN/8, x10, x1, x4) + +inst_616: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x27d and fs2 == 0 and fe2 == 0x18 and fm2 == 0x0de and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x267d; op2val:0x60de; + valaddr_reg:x8; val_offset:1182*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1182*FLEN/8, x10, x1, x4) + +inst_617: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x27d and fs2 == 0 and fe2 == 0x18 and fm2 == 0x0de and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x267d; op2val:0x60de; + valaddr_reg:x8; val_offset:1184*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1184*FLEN/8, x10, x1, x4) + +inst_618: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x27d and fs2 == 0 and fe2 == 0x18 and fm2 == 0x0de and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x267d; op2val:0x60de; + valaddr_reg:x8; val_offset:1186*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1186*FLEN/8, x10, x1, x4) + +inst_619: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x27d and fs2 == 0 and fe2 == 0x18 and fm2 == 0x0de and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x267d; op2val:0x60de; + valaddr_reg:x8; val_offset:1188*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1188*FLEN/8, x10, x1, x4) + +inst_620: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x34f and fs2 == 0 and fe2 == 0x1d and fm2 == 0x17c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b4f; op2val:0x757c; + valaddr_reg:x8; val_offset:1190*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1190*FLEN/8, x10, x1, x4) + +inst_621: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x34f and fs2 == 0 and fe2 == 0x1d and fm2 == 0x17c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b4f; op2val:0x757c; + valaddr_reg:x8; val_offset:1192*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1192*FLEN/8, x10, x1, x4) + +inst_622: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x34f and fs2 == 0 and fe2 == 0x1d and fm2 == 0x17c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b4f; op2val:0x757c; + valaddr_reg:x8; val_offset:1194*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1194*FLEN/8, x10, x1, x4) + +inst_623: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x34f and fs2 == 0 and fe2 == 0x1d and fm2 == 0x17c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b4f; op2val:0x757c; + valaddr_reg:x8; val_offset:1196*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1196*FLEN/8, x10, x1, x4) + +inst_624: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x34f and fs2 == 0 and fe2 == 0x1d and fm2 == 0x17c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b4f; op2val:0x757c; + valaddr_reg:x8; val_offset:1198*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1198*FLEN/8, x10, x1, x4) + +inst_625: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x179 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x177 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3979; op2val:0x7177; + valaddr_reg:x8; val_offset:1200*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1200*FLEN/8, x10, x1, x4) + +inst_626: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x179 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x177 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3979; op2val:0x7177; + valaddr_reg:x8; val_offset:1202*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1202*FLEN/8, x10, x1, x4) + +inst_627: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x179 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x177 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3979; op2val:0x7177; + valaddr_reg:x8; val_offset:1204*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1204*FLEN/8, x10, x1, x4) + +inst_628: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x179 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x177 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3979; op2val:0x7177; + valaddr_reg:x8; val_offset:1206*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1206*FLEN/8, x10, x1, x4) + +inst_629: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x179 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x177 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3979; op2val:0x7177; + valaddr_reg:x8; val_offset:1208*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1208*FLEN/8, x10, x1, x4) + +inst_630: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x130 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x12f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3930; op2val:0x712f; + valaddr_reg:x8; val_offset:1210*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1210*FLEN/8, x10, x1, x4) + +inst_631: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x130 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x12f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3930; op2val:0x712f; + valaddr_reg:x8; val_offset:1212*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1212*FLEN/8, x10, x1, x4) + +inst_632: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x130 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x12f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3930; op2val:0x712f; + valaddr_reg:x8; val_offset:1214*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1214*FLEN/8, x10, x1, x4) + +inst_633: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x130 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x12f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3930; op2val:0x712f; + valaddr_reg:x8; val_offset:1216*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1216*FLEN/8, x10, x1, x4) + +inst_634: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x130 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x12f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3930; op2val:0x712f; + valaddr_reg:x8; val_offset:1218*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1218*FLEN/8, x10, x1, x4) + +inst_635: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x29d and fs2 == 0 and fe2 == 0x1b and fm2 == 0x29b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x369d; op2val:0x6e9b; + valaddr_reg:x8; val_offset:1220*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1220*FLEN/8, x10, x1, x4) + +inst_636: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x29d and fs2 == 0 and fe2 == 0x1b and fm2 == 0x29b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x369d; op2val:0x6e9b; + valaddr_reg:x8; val_offset:1222*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1222*FLEN/8, x10, x1, x4) + +inst_637: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x29d and fs2 == 0 and fe2 == 0x1b and fm2 == 0x29b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x369d; op2val:0x6e9b; + valaddr_reg:x8; val_offset:1224*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1224*FLEN/8, x10, x1, x4) + +inst_638: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x29d and fs2 == 0 and fe2 == 0x1b and fm2 == 0x29b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x369d; op2val:0x6e9b; + valaddr_reg:x8; val_offset:1226*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1226*FLEN/8, x10, x1, x4) + +inst_639: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x29d and fs2 == 0 and fe2 == 0x1b and fm2 == 0x29b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x369d; op2val:0x6e9b; + valaddr_reg:x8; val_offset:1228*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1228*FLEN/8, x10, x1, x4) + +inst_640: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x278 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x276 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a78; op2val:0x7276; + valaddr_reg:x8; val_offset:1230*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1230*FLEN/8, x10, x1, x4) + +inst_641: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x278 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x276 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a78; op2val:0x7276; + valaddr_reg:x8; val_offset:1232*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1232*FLEN/8, x10, x1, x4) + +inst_642: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x278 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x276 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a78; op2val:0x7276; + valaddr_reg:x8; val_offset:1234*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1234*FLEN/8, x10, x1, x4) + +inst_643: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x278 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x276 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a78; op2val:0x7276; + valaddr_reg:x8; val_offset:1236*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1236*FLEN/8, x10, x1, x4) + +inst_644: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x278 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x276 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a78; op2val:0x7276; + valaddr_reg:x8; val_offset:1238*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1238*FLEN/8, x10, x1, x4) + +inst_645: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x302 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b02; op2val:0x7300; + valaddr_reg:x8; val_offset:1240*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1240*FLEN/8, x10, x1, x4) + +inst_646: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x302 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x300 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b02; op2val:0x7300; + valaddr_reg:x8; val_offset:1242*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1242*FLEN/8, x10, x1, x4) + +inst_647: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x302 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x300 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b02; op2val:0x7300; + valaddr_reg:x8; val_offset:1244*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1244*FLEN/8, x10, x1, x4) + +inst_648: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x302 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x300 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b02; op2val:0x7300; + valaddr_reg:x8; val_offset:1246*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1246*FLEN/8, x10, x1, x4) + +inst_649: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x302 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x300 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b02; op2val:0x7300; + valaddr_reg:x8; val_offset:1248*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1248*FLEN/8, x10, x1, x4) + +inst_650: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x08b and fs2 == 0 and fe2 == 0x1b and fm2 == 0x089 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x348b; op2val:0x6c89; + valaddr_reg:x8; val_offset:1250*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1250*FLEN/8, x10, x1, x4) + +inst_651: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x08b and fs2 == 0 and fe2 == 0x1b and fm2 == 0x089 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x348b; op2val:0x6c89; + valaddr_reg:x8; val_offset:1252*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1252*FLEN/8, x10, x1, x4) + +inst_652: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x08b and fs2 == 0 and fe2 == 0x1b and fm2 == 0x089 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x348b; op2val:0x6c89; + valaddr_reg:x8; val_offset:1254*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1254*FLEN/8, x10, x1, x4) + +inst_653: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x08b and fs2 == 0 and fe2 == 0x1b and fm2 == 0x089 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x348b; op2val:0x6c89; + valaddr_reg:x8; val_offset:1256*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1256*FLEN/8, x10, x1, x4) + +inst_654: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x08b and fs2 == 0 and fe2 == 0x1b and fm2 == 0x089 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x348b; op2val:0x6c89; + valaddr_reg:x8; val_offset:1258*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1258*FLEN/8, x10, x1, x4) + +inst_655: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x35c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x35a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b5c; op2val:0x735a; + valaddr_reg:x8; val_offset:1260*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1260*FLEN/8, x10, x1, x4) + +inst_656: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x35c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x35a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b5c; op2val:0x735a; + valaddr_reg:x8; val_offset:1262*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1262*FLEN/8, x10, x1, x4) + +inst_657: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x35c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x35a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b5c; op2val:0x735a; + valaddr_reg:x8; val_offset:1264*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1264*FLEN/8, x10, x1, x4) + +inst_658: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x35c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x35a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b5c; op2val:0x735a; + valaddr_reg:x8; val_offset:1266*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1266*FLEN/8, x10, x1, x4) + +inst_659: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x35c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x35a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b5c; op2val:0x735a; + valaddr_reg:x8; val_offset:1268*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1268*FLEN/8, x10, x1, x4) + +inst_660: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x103 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x102 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3903; op2val:0x7102; + valaddr_reg:x8; val_offset:1270*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1270*FLEN/8, x10, x1, x4) + +inst_661: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x103 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x102 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3903; op2val:0x7102; + valaddr_reg:x8; val_offset:1272*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1272*FLEN/8, x10, x1, x4) + +inst_662: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x103 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x102 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3903; op2val:0x7102; + valaddr_reg:x8; val_offset:1274*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1274*FLEN/8, x10, x1, x4) + +inst_663: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x103 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x102 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3903; op2val:0x7102; + valaddr_reg:x8; val_offset:1276*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1276*FLEN/8, x10, x1, x4) + +inst_664: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x103 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x102 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3903; op2val:0x7102; + valaddr_reg:x8; val_offset:1278*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1278*FLEN/8, x10, x1, x4) + +inst_665: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2f5 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x2f3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x32f5; op2val:0x6af3; + valaddr_reg:x8; val_offset:1280*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1280*FLEN/8, x10, x1, x4) + +inst_666: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2f5 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x2f3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x32f5; op2val:0x6af3; + valaddr_reg:x8; val_offset:1282*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1282*FLEN/8, x10, x1, x4) + +inst_667: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2f5 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x2f3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x32f5; op2val:0x6af3; + valaddr_reg:x8; val_offset:1284*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1284*FLEN/8, x10, x1, x4) + +inst_668: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2f5 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x2f3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x32f5; op2val:0x6af3; + valaddr_reg:x8; val_offset:1286*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1286*FLEN/8, x10, x1, x4) + +inst_669: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2f5 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x2f3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x32f5; op2val:0x6af3; + valaddr_reg:x8; val_offset:1288*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1288*FLEN/8, x10, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_5) + +inst_670: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x25d and fs2 == 0 and fe2 == 0x1a and fm2 == 0x25b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x325d; op2val:0x6a5b; + valaddr_reg:x8; val_offset:1290*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1290*FLEN/8, x10, x1, x4) + +inst_671: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x25d and fs2 == 0 and fe2 == 0x1a and fm2 == 0x25b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x325d; op2val:0x6a5b; + valaddr_reg:x8; val_offset:1292*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1292*FLEN/8, x10, x1, x4) + +inst_672: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x25d and fs2 == 0 and fe2 == 0x1a and fm2 == 0x25b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x325d; op2val:0x6a5b; + valaddr_reg:x8; val_offset:1294*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1294*FLEN/8, x10, x1, x4) + +inst_673: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x25d and fs2 == 0 and fe2 == 0x1a and fm2 == 0x25b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x325d; op2val:0x6a5b; + valaddr_reg:x8; val_offset:1296*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1296*FLEN/8, x10, x1, x4) + +inst_674: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x25d and fs2 == 0 and fe2 == 0x1a and fm2 == 0x25b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x325d; op2val:0x6a5b; + valaddr_reg:x8; val_offset:1298*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1298*FLEN/8, x10, x1, x4) + +inst_675: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x08c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x08a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x388c; op2val:0x708a; + valaddr_reg:x8; val_offset:1300*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1300*FLEN/8, x10, x1, x4) + +inst_676: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x08c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x08a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x388c; op2val:0x708a; + valaddr_reg:x8; val_offset:1302*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1302*FLEN/8, x10, x1, x4) + +inst_677: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x08c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x08a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x388c; op2val:0x708a; + valaddr_reg:x8; val_offset:1304*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1304*FLEN/8, x10, x1, x4) + +inst_678: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x08c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x08a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x388c; op2val:0x708a; + valaddr_reg:x8; val_offset:1306*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1306*FLEN/8, x10, x1, x4) + +inst_679: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x08c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x08a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x388c; op2val:0x708a; + valaddr_reg:x8; val_offset:1308*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1308*FLEN/8, x10, x1, x4) + +inst_680: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x007 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x006 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3807; op2val:0x7006; + valaddr_reg:x8; val_offset:1310*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1310*FLEN/8, x10, x1, x4) + +inst_681: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x007 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x006 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3807; op2val:0x7006; + valaddr_reg:x8; val_offset:1312*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1312*FLEN/8, x10, x1, x4) + +inst_682: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x007 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x006 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3807; op2val:0x7006; + valaddr_reg:x8; val_offset:1314*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1314*FLEN/8, x10, x1, x4) + +inst_683: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x007 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x006 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3807; op2val:0x7006; + valaddr_reg:x8; val_offset:1316*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1316*FLEN/8, x10, x1, x4) + +inst_684: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x007 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x006 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3807; op2val:0x7006; + valaddr_reg:x8; val_offset:1318*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1318*FLEN/8, x10, x1, x4) + +inst_685: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0a2 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0a1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x38a2; op2val:0x70a1; + valaddr_reg:x8; val_offset:1320*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1320*FLEN/8, x10, x1, x4) + +inst_686: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0a2 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0a1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x38a2; op2val:0x70a1; + valaddr_reg:x8; val_offset:1322*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1322*FLEN/8, x10, x1, x4) + +inst_687: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0a2 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0a1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x38a2; op2val:0x70a1; + valaddr_reg:x8; val_offset:1324*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1324*FLEN/8, x10, x1, x4) + +inst_688: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0a2 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0a1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x38a2; op2val:0x70a1; + valaddr_reg:x8; val_offset:1326*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1326*FLEN/8, x10, x1, x4) + +inst_689: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0a2 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0a1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x38a2; op2val:0x70a1; + valaddr_reg:x8; val_offset:1328*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1328*FLEN/8, x10, x1, x4) + +inst_690: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x050 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3850; op2val:0x704e; + valaddr_reg:x8; val_offset:1330*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1330*FLEN/8, x10, x1, x4) + +inst_691: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x050 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3850; op2val:0x704e; + valaddr_reg:x8; val_offset:1332*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1332*FLEN/8, x10, x1, x4) + +inst_692: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x050 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3850; op2val:0x704e; + valaddr_reg:x8; val_offset:1334*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1334*FLEN/8, x10, x1, x4) + +inst_693: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x050 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3850; op2val:0x704e; + valaddr_reg:x8; val_offset:1336*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1336*FLEN/8, x10, x1, x4) + +inst_694: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x050 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3850; op2val:0x704e; + valaddr_reg:x8; val_offset:1338*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1338*FLEN/8, x10, x1, x4) + +inst_695: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x36d and fs2 == 0 and fe2 == 0x1b and fm2 == 0x36b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x376d; op2val:0x6f6b; + valaddr_reg:x8; val_offset:1340*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1340*FLEN/8, x10, x1, x4) + +inst_696: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x36d and fs2 == 0 and fe2 == 0x1b and fm2 == 0x36b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x376d; op2val:0x6f6b; + valaddr_reg:x8; val_offset:1342*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1342*FLEN/8, x10, x1, x4) + +inst_697: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x36d and fs2 == 0 and fe2 == 0x1b and fm2 == 0x36b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x376d; op2val:0x6f6b; + valaddr_reg:x8; val_offset:1344*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1344*FLEN/8, x10, x1, x4) + +inst_698: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x36d and fs2 == 0 and fe2 == 0x1b and fm2 == 0x36b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x376d; op2val:0x6f6b; + valaddr_reg:x8; val_offset:1346*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1346*FLEN/8, x10, x1, x4) + +inst_699: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x36d and fs2 == 0 and fe2 == 0x1b and fm2 == 0x36b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x376d; op2val:0x6f6b; + valaddr_reg:x8; val_offset:1348*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1348*FLEN/8, x10, x1, x4) + +inst_700: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36d and fs2 == 0 and fe2 == 0x1c and fm2 == 0x36b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b6d; op2val:0x736b; + valaddr_reg:x8; val_offset:1350*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1350*FLEN/8, x10, x1, x4) + +inst_701: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36d and fs2 == 0 and fe2 == 0x1c and fm2 == 0x36b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b6d; op2val:0x736b; + valaddr_reg:x8; val_offset:1352*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1352*FLEN/8, x10, x1, x4) + +inst_702: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36d and fs2 == 0 and fe2 == 0x1c and fm2 == 0x36b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b6d; op2val:0x736b; + valaddr_reg:x8; val_offset:1354*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1354*FLEN/8, x10, x1, x4) + +inst_703: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36d and fs2 == 0 and fe2 == 0x1c and fm2 == 0x36b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b6d; op2val:0x736b; + valaddr_reg:x8; val_offset:1356*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1356*FLEN/8, x10, x1, x4) + +inst_704: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36d and fs2 == 0 and fe2 == 0x1c and fm2 == 0x36b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b6d; op2val:0x736b; + valaddr_reg:x8; val_offset:1358*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1358*FLEN/8, x10, x1, x4) + +inst_705: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x097 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x096 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3897; op2val:0x7096; + valaddr_reg:x8; val_offset:1360*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1360*FLEN/8, x10, x1, x4) + +inst_706: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x097 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x096 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3897; op2val:0x7096; + valaddr_reg:x8; val_offset:1362*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1362*FLEN/8, x10, x1, x4) + +inst_707: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x097 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x096 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3897; op2val:0x7096; + valaddr_reg:x8; val_offset:1364*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1364*FLEN/8, x10, x1, x4) + +inst_708: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x097 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x096 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3897; op2val:0x7096; + valaddr_reg:x8; val_offset:1366*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1366*FLEN/8, x10, x1, x4) + +inst_709: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x097 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x096 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3897; op2val:0x7096; + valaddr_reg:x8; val_offset:1368*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1368*FLEN/8, x10, x1, x4) + +inst_710: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x011 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x010 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2c11; op2val:0x6410; + valaddr_reg:x8; val_offset:1370*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1370*FLEN/8, x10, x1, x4) + +inst_711: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x011 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x010 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2c11; op2val:0x6410; + valaddr_reg:x8; val_offset:1372*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1372*FLEN/8, x10, x1, x4) + +inst_712: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x011 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x010 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2c11; op2val:0x6410; + valaddr_reg:x8; val_offset:1374*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1374*FLEN/8, x10, x1, x4) + +inst_713: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x011 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x010 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2c11; op2val:0x6410; + valaddr_reg:x8; val_offset:1376*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1376*FLEN/8, x10, x1, x4) + +inst_714: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x011 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x010 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2c11; op2val:0x6410; + valaddr_reg:x8; val_offset:1378*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1378*FLEN/8, x10, x1, x4) + +inst_715: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x28a and fs2 == 0 and fe2 == 0x19 and fm2 == 0x288 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e8a; op2val:0x6688; + valaddr_reg:x8; val_offset:1380*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1380*FLEN/8, x10, x1, x4) + +inst_716: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x28a and fs2 == 0 and fe2 == 0x19 and fm2 == 0x288 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e8a; op2val:0x6688; + valaddr_reg:x8; val_offset:1382*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1382*FLEN/8, x10, x1, x4) + +inst_717: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x28a and fs2 == 0 and fe2 == 0x19 and fm2 == 0x288 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e8a; op2val:0x6688; + valaddr_reg:x8; val_offset:1384*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1384*FLEN/8, x10, x1, x4) + +inst_718: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x28a and fs2 == 0 and fe2 == 0x19 and fm2 == 0x288 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e8a; op2val:0x6688; + valaddr_reg:x8; val_offset:1386*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1386*FLEN/8, x10, x1, x4) + +inst_719: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x28a and fs2 == 0 and fe2 == 0x19 and fm2 == 0x288 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e8a; op2val:0x6688; + valaddr_reg:x8; val_offset:1388*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1388*FLEN/8, x10, x1, x4) + +inst_720: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1e7 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1e5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39e7; op2val:0x71e5; + valaddr_reg:x8; val_offset:1390*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1390*FLEN/8, x10, x1, x4) + +inst_721: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1e7 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1e5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39e7; op2val:0x71e5; + valaddr_reg:x8; val_offset:1392*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1392*FLEN/8, x10, x1, x4) + +inst_722: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1e7 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1e5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39e7; op2val:0x71e5; + valaddr_reg:x8; val_offset:1394*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1394*FLEN/8, x10, x1, x4) + +inst_723: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1e7 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1e5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39e7; op2val:0x71e5; + valaddr_reg:x8; val_offset:1396*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1396*FLEN/8, x10, x1, x4) + +inst_724: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1e7 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1e5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39e7; op2val:0x71e5; + valaddr_reg:x8; val_offset:1398*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1398*FLEN/8, x10, x1, x4) + +inst_725: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x303 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x301 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b03; op2val:0x7301; + valaddr_reg:x8; val_offset:1400*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1400*FLEN/8, x10, x1, x4) + +inst_726: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x303 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x301 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b03; op2val:0x7301; + valaddr_reg:x8; val_offset:1402*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1402*FLEN/8, x10, x1, x4) + +inst_727: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x303 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x301 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b03; op2val:0x7301; + valaddr_reg:x8; val_offset:1404*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1404*FLEN/8, x10, x1, x4) + +inst_728: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x303 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x301 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b03; op2val:0x7301; + valaddr_reg:x8; val_offset:1406*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1406*FLEN/8, x10, x1, x4) + +inst_729: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x303 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x301 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b03; op2val:0x7301; + valaddr_reg:x8; val_offset:1408*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1408*FLEN/8, x10, x1, x4) + +inst_730: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x167 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x165 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3567; op2val:0x6d65; + valaddr_reg:x8; val_offset:1410*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1410*FLEN/8, x10, x1, x4) + +inst_731: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x167 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x165 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3567; op2val:0x6d65; + valaddr_reg:x8; val_offset:1412*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1412*FLEN/8, x10, x1, x4) + +inst_732: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x167 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x165 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3567; op2val:0x6d65; + valaddr_reg:x8; val_offset:1414*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1414*FLEN/8, x10, x1, x4) + +inst_733: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x167 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x165 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3567; op2val:0x6d65; + valaddr_reg:x8; val_offset:1416*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1416*FLEN/8, x10, x1, x4) + +inst_734: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x167 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x165 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3567; op2val:0x6d65; + valaddr_reg:x8; val_offset:1418*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1418*FLEN/8, x10, x1, x4) + +inst_735: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2a4 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x2a2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x32a4; op2val:0x6aa2; + valaddr_reg:x8; val_offset:1420*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1420*FLEN/8, x10, x1, x4) + +inst_736: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2a4 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x2a2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x32a4; op2val:0x6aa2; + valaddr_reg:x8; val_offset:1422*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1422*FLEN/8, x10, x1, x4) + +inst_737: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2a4 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x2a2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x32a4; op2val:0x6aa2; + valaddr_reg:x8; val_offset:1424*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1424*FLEN/8, x10, x1, x4) + +inst_738: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2a4 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x2a2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x32a4; op2val:0x6aa2; + valaddr_reg:x8; val_offset:1426*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1426*FLEN/8, x10, x1, x4) + +inst_739: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2a4 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x2a2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x32a4; op2val:0x6aa2; + valaddr_reg:x8; val_offset:1428*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1428*FLEN/8, x10, x1, x4) + +inst_740: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x042 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x041 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3442; op2val:0x6c41; + valaddr_reg:x8; val_offset:1430*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1430*FLEN/8, x10, x1, x4) + +inst_741: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x042 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x041 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3442; op2val:0x6c41; + valaddr_reg:x8; val_offset:1432*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1432*FLEN/8, x10, x1, x4) + +inst_742: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x042 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x041 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3442; op2val:0x6c41; + valaddr_reg:x8; val_offset:1434*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1434*FLEN/8, x10, x1, x4) + +inst_743: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x042 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x041 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3442; op2val:0x6c41; + valaddr_reg:x8; val_offset:1436*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1436*FLEN/8, x10, x1, x4) + +inst_744: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x042 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x041 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3442; op2val:0x6c41; + valaddr_reg:x8; val_offset:1438*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1438*FLEN/8, x10, x1, x4) + +inst_745: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x32c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x32a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b2c; op2val:0x732a; + valaddr_reg:x8; val_offset:1440*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1440*FLEN/8, x10, x1, x4) + +inst_746: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x32c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x32a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b2c; op2val:0x732a; + valaddr_reg:x8; val_offset:1442*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1442*FLEN/8, x10, x1, x4) + +inst_747: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x32c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x32a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b2c; op2val:0x732a; + valaddr_reg:x8; val_offset:1444*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1444*FLEN/8, x10, x1, x4) + +inst_748: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x32c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x32a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b2c; op2val:0x732a; + valaddr_reg:x8; val_offset:1446*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1446*FLEN/8, x10, x1, x4) + +inst_749: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x32c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x32a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b2c; op2val:0x732a; + valaddr_reg:x8; val_offset:1448*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1448*FLEN/8, x10, x1, x4) + +inst_750: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f5 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3f3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bf5; op2val:0x73f3; + valaddr_reg:x8; val_offset:1450*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1450*FLEN/8, x10, x1, x4) + +inst_751: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f5 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3f3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bf5; op2val:0x73f3; + valaddr_reg:x8; val_offset:1452*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1452*FLEN/8, x10, x1, x4) + +inst_752: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f5 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3f3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bf5; op2val:0x73f3; + valaddr_reg:x8; val_offset:1454*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1454*FLEN/8, x10, x1, x4) + +inst_753: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f5 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3f3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bf5; op2val:0x73f3; + valaddr_reg:x8; val_offset:1456*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1456*FLEN/8, x10, x1, x4) + +inst_754: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f5 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3f3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bf5; op2val:0x73f3; + valaddr_reg:x8; val_offset:1458*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1458*FLEN/8, x10, x1, x4) + +inst_755: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x339 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x337 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3339; op2val:0x6b37; + valaddr_reg:x8; val_offset:1460*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1460*FLEN/8, x10, x1, x4) + +inst_756: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x339 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x337 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3339; op2val:0x6b37; + valaddr_reg:x8; val_offset:1462*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1462*FLEN/8, x10, x1, x4) + +inst_757: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x339 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x337 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3339; op2val:0x6b37; + valaddr_reg:x8; val_offset:1464*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1464*FLEN/8, x10, x1, x4) + +inst_758: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x339 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x337 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3339; op2val:0x6b37; + valaddr_reg:x8; val_offset:1466*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1466*FLEN/8, x10, x1, x4) + +inst_759: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x339 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x337 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3339; op2val:0x6b37; + valaddr_reg:x8; val_offset:1468*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1468*FLEN/8, x10, x1, x4) + +inst_760: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x344 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x341 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b44; op2val:0x7341; + valaddr_reg:x8; val_offset:1470*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1470*FLEN/8, x10, x1, x4) + +inst_761: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x344 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x341 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b44; op2val:0x7341; + valaddr_reg:x8; val_offset:1472*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1472*FLEN/8, x10, x1, x4) + +inst_762: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x344 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x341 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b44; op2val:0x7341; + valaddr_reg:x8; val_offset:1474*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1474*FLEN/8, x10, x1, x4) + +inst_763: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x344 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x341 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b44; op2val:0x7341; + valaddr_reg:x8; val_offset:1476*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1476*FLEN/8, x10, x1, x4) + +inst_764: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x344 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x341 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b44; op2val:0x7341; + valaddr_reg:x8; val_offset:1478*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1478*FLEN/8, x10, x1, x4) + +inst_765: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3a7 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x3a5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2fa7; op2val:0x67a5; + valaddr_reg:x8; val_offset:1480*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1480*FLEN/8, x10, x1, x4) + +inst_766: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3a7 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x3a5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2fa7; op2val:0x67a5; + valaddr_reg:x8; val_offset:1482*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1482*FLEN/8, x10, x1, x4) + +inst_767: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3a7 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x3a5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2fa7; op2val:0x67a5; + valaddr_reg:x8; val_offset:1484*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1484*FLEN/8, x10, x1, x4) + +inst_768: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3a7 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x3a5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2fa7; op2val:0x67a5; + valaddr_reg:x8; val_offset:1486*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1486*FLEN/8, x10, x1, x4) + +inst_769: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3a7 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x3a5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2fa7; op2val:0x67a5; + valaddr_reg:x8; val_offset:1488*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1488*FLEN/8, x10, x1, x4) + +inst_770: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3cf and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3cd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bcf; op2val:0x73cd; + valaddr_reg:x8; val_offset:1490*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1490*FLEN/8, x10, x1, x4) + +inst_771: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3cf and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3cd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bcf; op2val:0x73cd; + valaddr_reg:x8; val_offset:1492*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1492*FLEN/8, x10, x1, x4) + +inst_772: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3cf and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3cd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bcf; op2val:0x73cd; + valaddr_reg:x8; val_offset:1494*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1494*FLEN/8, x10, x1, x4) + +inst_773: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3cf and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3cd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bcf; op2val:0x73cd; + valaddr_reg:x8; val_offset:1496*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1496*FLEN/8, x10, x1, x4) + +inst_774: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3cf and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3cd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bcf; op2val:0x73cd; + valaddr_reg:x8; val_offset:1498*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1498*FLEN/8, x10, x1, x4) + +inst_775: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x307 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x305 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b07; op2val:0x7305; + valaddr_reg:x8; val_offset:1500*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1500*FLEN/8, x10, x1, x4) + +inst_776: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x307 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x305 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b07; op2val:0x7305; + valaddr_reg:x8; val_offset:1502*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1502*FLEN/8, x10, x1, x4) + +inst_777: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x307 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x305 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b07; op2val:0x7305; + valaddr_reg:x8; val_offset:1504*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1504*FLEN/8, x10, x1, x4) + +inst_778: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x307 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x305 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b07; op2val:0x7305; + valaddr_reg:x8; val_offset:1506*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1506*FLEN/8, x10, x1, x4) + +inst_779: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x307 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x305 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b07; op2val:0x7305; + valaddr_reg:x8; val_offset:1508*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1508*FLEN/8, x10, x1, x4) + +inst_780: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x139 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x137 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3539; op2val:0x6d37; + valaddr_reg:x8; val_offset:1510*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1510*FLEN/8, x10, x1, x4) + +inst_781: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x139 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x137 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3539; op2val:0x6d37; + valaddr_reg:x8; val_offset:1512*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1512*FLEN/8, x10, x1, x4) + +inst_782: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x139 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x137 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3539; op2val:0x6d37; + valaddr_reg:x8; val_offset:1514*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1514*FLEN/8, x10, x1, x4) + +inst_783: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x139 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x137 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3539; op2val:0x6d37; + valaddr_reg:x8; val_offset:1516*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1516*FLEN/8, x10, x1, x4) + +inst_784: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x139 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x137 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3539; op2val:0x6d37; + valaddr_reg:x8; val_offset:1518*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1518*FLEN/8, x10, x1, x4) + +inst_785: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x219 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x217 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2a19; op2val:0x6217; + valaddr_reg:x8; val_offset:1520*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1520*FLEN/8, x10, x1, x4) + +inst_786: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x219 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x217 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2a19; op2val:0x6217; + valaddr_reg:x8; val_offset:1522*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1522*FLEN/8, x10, x1, x4) + +inst_787: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x219 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x217 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2a19; op2val:0x6217; + valaddr_reg:x8; val_offset:1524*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1524*FLEN/8, x10, x1, x4) + +inst_788: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x219 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x217 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2a19; op2val:0x6217; + valaddr_reg:x8; val_offset:1526*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1526*FLEN/8, x10, x1, x4) + +inst_789: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x219 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x217 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2a19; op2val:0x6217; + valaddr_reg:x8; val_offset:1528*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1528*FLEN/8, x10, x1, x4) + +inst_790: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x271 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x26f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3271; op2val:0x6a6f; + valaddr_reg:x8; val_offset:1530*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1530*FLEN/8, x10, x1, x4) + +inst_791: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x271 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x26f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3271; op2val:0x6a6f; + valaddr_reg:x8; val_offset:1532*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1532*FLEN/8, x10, x1, x4) + +inst_792: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x271 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x26f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3271; op2val:0x6a6f; + valaddr_reg:x8; val_offset:1534*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1534*FLEN/8, x10, x1, x4) + +inst_793: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x271 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x26f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3271; op2val:0x6a6f; + valaddr_reg:x8; val_offset:1536*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1536*FLEN/8, x10, x1, x4) + +inst_794: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x271 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x26f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3271; op2val:0x6a6f; + valaddr_reg:x8; val_offset:1538*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1538*FLEN/8, x10, x1, x4) + +inst_795: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x371 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x36f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3371; op2val:0x6b6f; + valaddr_reg:x8; val_offset:1540*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1540*FLEN/8, x10, x1, x4) + +inst_796: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x371 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x36f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3371; op2val:0x6b6f; + valaddr_reg:x8; val_offset:1542*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1542*FLEN/8, x10, x1, x4) + +inst_797: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x371 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x36f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3371; op2val:0x6b6f; + valaddr_reg:x8; val_offset:1544*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1544*FLEN/8, x10, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_6) + +inst_798: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x371 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x36f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3371; op2val:0x6b6f; + valaddr_reg:x8; val_offset:1546*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1546*FLEN/8, x10, x1, x4) + +inst_799: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x371 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x36f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3371; op2val:0x6b6f; + valaddr_reg:x8; val_offset:1548*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1548*FLEN/8, x10, x1, x4) + +inst_800: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x08e and fs2 == 0 and fe2 == 0x1b and fm2 == 0x08d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x348e; op2val:0x6c8d; + valaddr_reg:x8; val_offset:1550*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1550*FLEN/8, x10, x1, x4) + +inst_801: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x08e and fs2 == 0 and fe2 == 0x1b and fm2 == 0x08d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x348e; op2val:0x6c8d; + valaddr_reg:x8; val_offset:1552*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1552*FLEN/8, x10, x1, x4) + +inst_802: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x08e and fs2 == 0 and fe2 == 0x1b and fm2 == 0x08d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x348e; op2val:0x6c8d; + valaddr_reg:x8; val_offset:1554*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1554*FLEN/8, x10, x1, x4) + +inst_803: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x08e and fs2 == 0 and fe2 == 0x1b and fm2 == 0x08d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x348e; op2val:0x6c8d; + valaddr_reg:x8; val_offset:1556*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1556*FLEN/8, x10, x1, x4) + +inst_804: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x08e and fs2 == 0 and fe2 == 0x1b and fm2 == 0x08d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x348e; op2val:0x6c8d; + valaddr_reg:x8; val_offset:1558*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1558*FLEN/8, x10, x1, x4) + +inst_805: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x004 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3404; op2val:0x6c03; + valaddr_reg:x8; val_offset:1560*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1560*FLEN/8, x10, x1, x4) + +inst_806: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x004 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x003 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3404; op2val:0x6c03; + valaddr_reg:x8; val_offset:1562*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1562*FLEN/8, x10, x1, x4) + +inst_807: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x004 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x003 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3404; op2val:0x6c03; + valaddr_reg:x8; val_offset:1564*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1564*FLEN/8, x10, x1, x4) + +inst_808: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x004 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x003 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3404; op2val:0x6c03; + valaddr_reg:x8; val_offset:1566*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1566*FLEN/8, x10, x1, x4) + +inst_809: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x004 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x003 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3404; op2val:0x6c03; + valaddr_reg:x8; val_offset:1568*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1568*FLEN/8, x10, x1, x4) + +inst_810: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x382 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b82; op2val:0x7380; + valaddr_reg:x8; val_offset:1570*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1570*FLEN/8, x10, x1, x4) + +inst_811: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x382 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x380 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b82; op2val:0x7380; + valaddr_reg:x8; val_offset:1572*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1572*FLEN/8, x10, x1, x4) + +inst_812: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x382 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x380 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b82; op2val:0x7380; + valaddr_reg:x8; val_offset:1574*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1574*FLEN/8, x10, x1, x4) + +inst_813: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x382 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x380 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b82; op2val:0x7380; + valaddr_reg:x8; val_offset:1576*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1576*FLEN/8, x10, x1, x4) + +inst_814: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x382 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x380 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b82; op2val:0x7380; + valaddr_reg:x8; val_offset:1578*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1578*FLEN/8, x10, x1, x4) + +inst_815: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2fa and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x36fa; op2val:0x6ef8; + valaddr_reg:x8; val_offset:1580*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1580*FLEN/8, x10, x1, x4) + +inst_816: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2fa and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2f8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x36fa; op2val:0x6ef8; + valaddr_reg:x8; val_offset:1582*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1582*FLEN/8, x10, x1, x4) + +inst_817: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2fa and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2f8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x36fa; op2val:0x6ef8; + valaddr_reg:x8; val_offset:1584*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1584*FLEN/8, x10, x1, x4) + +inst_818: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2fa and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2f8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x36fa; op2val:0x6ef8; + valaddr_reg:x8; val_offset:1586*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1586*FLEN/8, x10, x1, x4) + +inst_819: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2fa and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2f8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x36fa; op2val:0x6ef8; + valaddr_reg:x8; val_offset:1588*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1588*FLEN/8, x10, x1, x4) + +inst_820: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x210 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x20e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a10; op2val:0x720e; + valaddr_reg:x8; val_offset:1590*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1590*FLEN/8, x10, x1, x4) + +inst_821: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x210 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x20e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a10; op2val:0x720e; + valaddr_reg:x8; val_offset:1592*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1592*FLEN/8, x10, x1, x4) + +inst_822: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x210 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x20e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a10; op2val:0x720e; + valaddr_reg:x8; val_offset:1594*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1594*FLEN/8, x10, x1, x4) + +inst_823: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x210 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x20e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a10; op2val:0x720e; + valaddr_reg:x8; val_offset:1596*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1596*FLEN/8, x10, x1, x4) + +inst_824: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x210 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x20e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a10; op2val:0x720e; + valaddr_reg:x8; val_offset:1598*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1598*FLEN/8, x10, x1, x4) + +inst_825: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a00; op2val:0x71fe; + valaddr_reg:x8; val_offset:1600*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1600*FLEN/8, x10, x1, x4) + +inst_826: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1fe and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a00; op2val:0x71fe; + valaddr_reg:x8; val_offset:1602*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1602*FLEN/8, x10, x1, x4) + +inst_827: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1fe and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a00; op2val:0x71fe; + valaddr_reg:x8; val_offset:1604*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1604*FLEN/8, x10, x1, x4) + +inst_828: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1fe and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a00; op2val:0x71fe; + valaddr_reg:x8; val_offset:1606*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1606*FLEN/8, x10, x1, x4) + +inst_829: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1fe and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a00; op2val:0x71fe; + valaddr_reg:x8; val_offset:1608*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1608*FLEN/8, x10, x1, x4) + +inst_830: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3e3 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x33e3; op2val:0x6be0; + valaddr_reg:x8; val_offset:1610*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1610*FLEN/8, x10, x1, x4) + +inst_831: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3e3 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x3e0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x33e3; op2val:0x6be0; + valaddr_reg:x8; val_offset:1612*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1612*FLEN/8, x10, x1, x4) + +inst_832: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3e3 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x3e0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x33e3; op2val:0x6be0; + valaddr_reg:x8; val_offset:1614*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1614*FLEN/8, x10, x1, x4) + +inst_833: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3e3 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x3e0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x33e3; op2val:0x6be0; + valaddr_reg:x8; val_offset:1616*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1616*FLEN/8, x10, x1, x4) + +inst_834: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3e3 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x3e0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x33e3; op2val:0x6be0; + valaddr_reg:x8; val_offset:1618*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1618*FLEN/8, x10, x1, x4) + +inst_835: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x10f and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0ac and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x390f; op2val:0x70ac; + valaddr_reg:x8; val_offset:1620*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1620*FLEN/8, x10, x1, x4) + +inst_836: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x10f and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0ac and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x390f; op2val:0x70ac; + valaddr_reg:x8; val_offset:1622*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1622*FLEN/8, x10, x1, x4) + +inst_837: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x10f and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0ac and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x390f; op2val:0x70ac; + valaddr_reg:x8; val_offset:1624*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1624*FLEN/8, x10, x1, x4) + +inst_838: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x10f and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0ac and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x390f; op2val:0x70ac; + valaddr_reg:x8; val_offset:1626*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1626*FLEN/8, x10, x1, x4) + +inst_839: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x10f and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0ac and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x390f; op2val:0x70ac; + valaddr_reg:x8; val_offset:1628*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1628*FLEN/8, x10, x1, x4) + +inst_840: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x132 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0cc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3932; op2val:0x70cc; + valaddr_reg:x8; val_offset:1630*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1630*FLEN/8, x10, x1, x4) + +inst_841: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x132 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0cc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3932; op2val:0x70cc; + valaddr_reg:x8; val_offset:1632*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1632*FLEN/8, x10, x1, x4) + +inst_842: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x132 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0cc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3932; op2val:0x70cc; + valaddr_reg:x8; val_offset:1634*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1634*FLEN/8, x10, x1, x4) + +inst_843: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x132 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0cc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3932; op2val:0x70cc; + valaddr_reg:x8; val_offset:1636*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1636*FLEN/8, x10, x1, x4) + +inst_844: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x132 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0cc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3932; op2val:0x70cc; + valaddr_reg:x8; val_offset:1638*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1638*FLEN/8, x10, x1, x4) + +inst_845: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x355 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2c5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b55; op2val:0x72c5; + valaddr_reg:x8; val_offset:1640*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1640*FLEN/8, x10, x1, x4) + +inst_846: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x355 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2c5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b55; op2val:0x72c5; + valaddr_reg:x8; val_offset:1642*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1642*FLEN/8, x10, x1, x4) + +inst_847: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x355 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2c5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b55; op2val:0x72c5; + valaddr_reg:x8; val_offset:1644*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1644*FLEN/8, x10, x1, x4) + +inst_848: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x355 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2c5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b55; op2val:0x72c5; + valaddr_reg:x8; val_offset:1646*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1646*FLEN/8, x10, x1, x4) + +inst_849: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x355 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2c5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b55; op2val:0x72c5; + valaddr_reg:x8; val_offset:1648*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1648*FLEN/8, x10, x1, x4) + +inst_850: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x2e9 and fs2 == 0 and fe2 == 0x17 and fm2 == 0x262 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x26e9; op2val:0x5e62; + valaddr_reg:x8; val_offset:1650*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1650*FLEN/8, x10, x1, x4) + +inst_851: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x2e9 and fs2 == 0 and fe2 == 0x17 and fm2 == 0x262 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x26e9; op2val:0x5e62; + valaddr_reg:x8; val_offset:1652*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1652*FLEN/8, x10, x1, x4) + +inst_852: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x2e9 and fs2 == 0 and fe2 == 0x17 and fm2 == 0x262 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x26e9; op2val:0x5e62; + valaddr_reg:x8; val_offset:1654*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1654*FLEN/8, x10, x1, x4) + +inst_853: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x2e9 and fs2 == 0 and fe2 == 0x17 and fm2 == 0x262 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x26e9; op2val:0x5e62; + valaddr_reg:x8; val_offset:1656*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1656*FLEN/8, x10, x1, x4) + +inst_854: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x2e9 and fs2 == 0 and fe2 == 0x17 and fm2 == 0x262 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x26e9; op2val:0x5e62; + valaddr_reg:x8; val_offset:1658*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1658*FLEN/8, x10, x1, x4) + +inst_855: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x00a and fs2 == 0 and fe2 == 0x1a and fm2 == 0x376 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x340a; op2val:0x6b76; + valaddr_reg:x8; val_offset:1660*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1660*FLEN/8, x10, x1, x4) + +inst_856: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x00a and fs2 == 0 and fe2 == 0x1a and fm2 == 0x376 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x340a; op2val:0x6b76; + valaddr_reg:x8; val_offset:1662*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1662*FLEN/8, x10, x1, x4) + +inst_857: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x00a and fs2 == 0 and fe2 == 0x1a and fm2 == 0x376 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x340a; op2val:0x6b76; + valaddr_reg:x8; val_offset:1664*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1664*FLEN/8, x10, x1, x4) + +inst_858: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x00a and fs2 == 0 and fe2 == 0x1a and fm2 == 0x376 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x340a; op2val:0x6b76; + valaddr_reg:x8; val_offset:1666*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1666*FLEN/8, x10, x1, x4) + +inst_859: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x00a and fs2 == 0 and fe2 == 0x1a and fm2 == 0x376 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x340a; op2val:0x6b76; + valaddr_reg:x8; val_offset:1668*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1668*FLEN/8, x10, x1, x4) + +inst_860: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0f2 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x091 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x34f2; op2val:0x6c91; + valaddr_reg:x8; val_offset:1670*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1670*FLEN/8, x10, x1, x4) + +inst_861: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0f2 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x091 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x34f2; op2val:0x6c91; + valaddr_reg:x8; val_offset:1672*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1672*FLEN/8, x10, x1, x4) + +inst_862: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0f2 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x091 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x34f2; op2val:0x6c91; + valaddr_reg:x8; val_offset:1674*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1674*FLEN/8, x10, x1, x4) + +inst_863: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0f2 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x091 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x34f2; op2val:0x6c91; + valaddr_reg:x8; val_offset:1676*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1676*FLEN/8, x10, x1, x4) + +inst_864: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0f2 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x091 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x34f2; op2val:0x6c91; + valaddr_reg:x8; val_offset:1678*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1678*FLEN/8, x10, x1, x4) + +inst_865: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x138 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0d1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3538; op2val:0x6cd1; + valaddr_reg:x8; val_offset:1680*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1680*FLEN/8, x10, x1, x4) + +inst_866: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x138 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0d1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3538; op2val:0x6cd1; + valaddr_reg:x8; val_offset:1682*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1682*FLEN/8, x10, x1, x4) + +inst_867: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x138 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0d1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3538; op2val:0x6cd1; + valaddr_reg:x8; val_offset:1684*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1684*FLEN/8, x10, x1, x4) + +inst_868: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x138 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0d1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3538; op2val:0x6cd1; + valaddr_reg:x8; val_offset:1686*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1686*FLEN/8, x10, x1, x4) + +inst_869: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x138 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0d1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3538; op2val:0x6cd1; + valaddr_reg:x8; val_offset:1688*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1688*FLEN/8, x10, x1, x4) + +inst_870: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x021 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3a0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3821; op2val:0x6fa0; + valaddr_reg:x8; val_offset:1690*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1690*FLEN/8, x10, x1, x4) + +inst_871: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x021 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3a0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3821; op2val:0x6fa0; + valaddr_reg:x8; val_offset:1692*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1692*FLEN/8, x10, x1, x4) + +inst_872: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x021 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3a0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3821; op2val:0x6fa0; + valaddr_reg:x8; val_offset:1694*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1694*FLEN/8, x10, x1, x4) + +inst_873: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x021 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3a0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3821; op2val:0x6fa0; + valaddr_reg:x8; val_offset:1696*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1696*FLEN/8, x10, x1, x4) + +inst_874: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x021 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3a0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3821; op2val:0x6fa0; + valaddr_reg:x8; val_offset:1698*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1698*FLEN/8, x10, x1, x4) + +inst_875: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x291 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x210 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e91; op2val:0x6610; + valaddr_reg:x8; val_offset:1700*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1700*FLEN/8, x10, x1, x4) + +inst_876: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x291 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x210 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e91; op2val:0x6610; + valaddr_reg:x8; val_offset:1702*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1702*FLEN/8, x10, x1, x4) + +inst_877: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x291 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x210 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e91; op2val:0x6610; + valaddr_reg:x8; val_offset:1704*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1704*FLEN/8, x10, x1, x4) + +inst_878: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x291 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x210 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e91; op2val:0x6610; + valaddr_reg:x8; val_offset:1706*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1706*FLEN/8, x10, x1, x4) + +inst_879: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x291 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x210 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e91; op2val:0x6610; + valaddr_reg:x8; val_offset:1708*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1708*FLEN/8, x10, x1, x4) + +inst_880: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x33b and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2ad and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b3b; op2val:0x72ad; + valaddr_reg:x8; val_offset:1710*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1710*FLEN/8, x10, x1, x4) + +inst_881: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x33b and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2ad and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b3b; op2val:0x72ad; + valaddr_reg:x8; val_offset:1712*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1712*FLEN/8, x10, x1, x4) + +inst_882: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x33b and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2ad and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b3b; op2val:0x72ad; + valaddr_reg:x8; val_offset:1714*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1714*FLEN/8, x10, x1, x4) + +inst_883: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x33b and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2ad and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b3b; op2val:0x72ad; + valaddr_reg:x8; val_offset:1716*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1716*FLEN/8, x10, x1, x4) + +inst_884: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x33b and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2ad and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b3b; op2val:0x72ad; + valaddr_reg:x8; val_offset:1718*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1718*FLEN/8, x10, x1, x4) + +inst_885: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x157 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x0ee and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d57; op2val:0x64ee; + valaddr_reg:x8; val_offset:1720*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1720*FLEN/8, x10, x1, x4) + +inst_886: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x157 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x0ee and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d57; op2val:0x64ee; + valaddr_reg:x8; val_offset:1722*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1722*FLEN/8, x10, x1, x4) + +inst_887: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x157 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x0ee and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d57; op2val:0x64ee; + valaddr_reg:x8; val_offset:1724*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1724*FLEN/8, x10, x1, x4) + +inst_888: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x157 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x0ee and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d57; op2val:0x64ee; + valaddr_reg:x8; val_offset:1726*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1726*FLEN/8, x10, x1, x4) + +inst_889: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x157 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x0ee and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d57; op2val:0x64ee; + valaddr_reg:x8; val_offset:1728*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1728*FLEN/8, x10, x1, x4) + +inst_890: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x074 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x01d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3874; op2val:0x701d; + valaddr_reg:x8; val_offset:1730*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1730*FLEN/8, x10, x1, x4) + +inst_891: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x074 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x01d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3874; op2val:0x701d; + valaddr_reg:x8; val_offset:1732*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1732*FLEN/8, x10, x1, x4) + +inst_892: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x074 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x01d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3874; op2val:0x701d; + valaddr_reg:x8; val_offset:1734*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1734*FLEN/8, x10, x1, x4) + +inst_893: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x074 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x01d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3874; op2val:0x701d; + valaddr_reg:x8; val_offset:1736*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1736*FLEN/8, x10, x1, x4) + +inst_894: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x074 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x01d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3874; op2val:0x701d; + valaddr_reg:x8; val_offset:1738*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1738*FLEN/8, x10, x1, x4) + +inst_895: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x282 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x202 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a82; op2val:0x7202; + valaddr_reg:x8; val_offset:1740*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1740*FLEN/8, x10, x1, x4) + +inst_896: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x282 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x202 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a82; op2val:0x7202; + valaddr_reg:x8; val_offset:1742*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1742*FLEN/8, x10, x1, x4) + +inst_897: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x282 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x202 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a82; op2val:0x7202; + valaddr_reg:x8; val_offset:1744*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1744*FLEN/8, x10, x1, x4) + +inst_898: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x282 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x202 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a82; op2val:0x7202; + valaddr_reg:x8; val_offset:1746*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1746*FLEN/8, x10, x1, x4) + +inst_899: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x282 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x202 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a82; op2val:0x7202; + valaddr_reg:x8; val_offset:1748*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1748*FLEN/8, x10, x1, x4) + +inst_900: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x268 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1ea and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a68; op2val:0x71ea; + valaddr_reg:x8; val_offset:1750*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1750*FLEN/8, x10, x1, x4) + +inst_901: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x268 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1ea and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a68; op2val:0x71ea; + valaddr_reg:x8; val_offset:1752*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1752*FLEN/8, x10, x1, x4) + +inst_902: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x268 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1ea and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a68; op2val:0x71ea; + valaddr_reg:x8; val_offset:1754*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1754*FLEN/8, x10, x1, x4) + +inst_903: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x268 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1ea and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a68; op2val:0x71ea; + valaddr_reg:x8; val_offset:1756*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1756*FLEN/8, x10, x1, x4) + +inst_904: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x268 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1ea and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a68; op2val:0x71ea; + valaddr_reg:x8; val_offset:1758*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1758*FLEN/8, x10, x1, x4) + +inst_905: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x17b and fs2 == 0 and fe2 == 0x1c and fm2 == 0x10f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x397b; op2val:0x710f; + valaddr_reg:x8; val_offset:1760*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1760*FLEN/8, x10, x1, x4) + +inst_906: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x17b and fs2 == 0 and fe2 == 0x1c and fm2 == 0x10f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x397b; op2val:0x710f; + valaddr_reg:x8; val_offset:1762*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1762*FLEN/8, x10, x1, x4) + +inst_907: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x17b and fs2 == 0 and fe2 == 0x1c and fm2 == 0x10f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x397b; op2val:0x710f; + valaddr_reg:x8; val_offset:1764*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1764*FLEN/8, x10, x1, x4) + +inst_908: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x17b and fs2 == 0 and fe2 == 0x1c and fm2 == 0x10f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x397b; op2val:0x710f; + valaddr_reg:x8; val_offset:1766*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1766*FLEN/8, x10, x1, x4) + +inst_909: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x17b and fs2 == 0 and fe2 == 0x1c and fm2 == 0x10f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x397b; op2val:0x710f; + valaddr_reg:x8; val_offset:1768*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1768*FLEN/8, x10, x1, x4) + +inst_910: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0f1 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x090 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x34f1; op2val:0x6c90; + valaddr_reg:x8; val_offset:1770*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1770*FLEN/8, x10, x1, x4) + +inst_911: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0f1 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x090 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x34f1; op2val:0x6c90; + valaddr_reg:x8; val_offset:1772*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1772*FLEN/8, x10, x1, x4) + +inst_912: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0f1 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x090 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x34f1; op2val:0x6c90; + valaddr_reg:x8; val_offset:1774*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1774*FLEN/8, x10, x1, x4) + +inst_913: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0f1 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x090 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x34f1; op2val:0x6c90; + valaddr_reg:x8; val_offset:1776*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1776*FLEN/8, x10, x1, x4) + +inst_914: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0f1 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x090 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x34f1; op2val:0x6c90; + valaddr_reg:x8; val_offset:1778*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1778*FLEN/8, x10, x1, x4) + +inst_915: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a2 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x133 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39a2; op2val:0x7133; + valaddr_reg:x8; val_offset:1780*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1780*FLEN/8, x10, x1, x4) + +inst_916: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a2 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x133 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39a2; op2val:0x7133; + valaddr_reg:x8; val_offset:1782*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1782*FLEN/8, x10, x1, x4) + +inst_917: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a2 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x133 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39a2; op2val:0x7133; + valaddr_reg:x8; val_offset:1784*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1784*FLEN/8, x10, x1, x4) + +inst_918: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a2 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x133 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39a2; op2val:0x7133; + valaddr_reg:x8; val_offset:1786*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1786*FLEN/8, x10, x1, x4) + +inst_919: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a2 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x133 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39a2; op2val:0x7133; + valaddr_reg:x8; val_offset:1788*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1788*FLEN/8, x10, x1, x4) + +inst_920: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0b1 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x38b1; op2val:0x7055; + valaddr_reg:x8; val_offset:1790*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1790*FLEN/8, x10, x1, x4) + +inst_921: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0b1 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x055 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x38b1; op2val:0x7055; + valaddr_reg:x8; val_offset:1792*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1792*FLEN/8, x10, x1, x4) + +inst_922: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0b1 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x055 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x38b1; op2val:0x7055; + valaddr_reg:x8; val_offset:1794*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1794*FLEN/8, x10, x1, x4) + +inst_923: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0b1 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x055 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x38b1; op2val:0x7055; + valaddr_reg:x8; val_offset:1796*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1796*FLEN/8, x10, x1, x4) + +inst_924: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0b1 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x055 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x38b1; op2val:0x7055; + valaddr_reg:x8; val_offset:1798*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1798*FLEN/8, x10, x1, x4) + +inst_925: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2a5 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x222 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x36a5; op2val:0x6e22; + valaddr_reg:x8; val_offset:1800*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1800*FLEN/8, x10, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_7) + +inst_926: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2a5 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x222 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x36a5; op2val:0x6e22; + valaddr_reg:x8; val_offset:1802*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1802*FLEN/8, x10, x1, x4) + +inst_927: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2a5 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x222 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x36a5; op2val:0x6e22; + valaddr_reg:x8; val_offset:1804*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1804*FLEN/8, x10, x1, x4) + +inst_928: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2a5 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x222 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x36a5; op2val:0x6e22; + valaddr_reg:x8; val_offset:1806*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1806*FLEN/8, x10, x1, x4) + +inst_929: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2a5 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x222 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x36a5; op2val:0x6e22; + valaddr_reg:x8; val_offset:1808*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1808*FLEN/8, x10, x1, x4) + +inst_930: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x242 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1c7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a42; op2val:0x71c7; + valaddr_reg:x8; val_offset:1810*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1810*FLEN/8, x10, x1, x4) + +inst_931: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x242 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1c7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a42; op2val:0x71c7; + valaddr_reg:x8; val_offset:1812*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1812*FLEN/8, x10, x1, x4) + +inst_932: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x242 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1c7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a42; op2val:0x71c7; + valaddr_reg:x8; val_offset:1814*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1814*FLEN/8, x10, x1, x4) + +inst_933: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x242 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1c7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a42; op2val:0x71c7; + valaddr_reg:x8; val_offset:1816*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1816*FLEN/8, x10, x1, x4) + +inst_934: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x242 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1c7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a42; op2val:0x71c7; + valaddr_reg:x8; val_offset:1818*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1818*FLEN/8, x10, x1, x4) + +inst_935: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02a and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3b0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x382a; op2val:0x6fb0; + valaddr_reg:x8; val_offset:1820*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1820*FLEN/8, x10, x1, x4) + +inst_936: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02a and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3b0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x382a; op2val:0x6fb0; + valaddr_reg:x8; val_offset:1822*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1822*FLEN/8, x10, x1, x4) + +inst_937: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02a and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3b0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x382a; op2val:0x6fb0; + valaddr_reg:x8; val_offset:1824*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1824*FLEN/8, x10, x1, x4) + +inst_938: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02a and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3b0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x382a; op2val:0x6fb0; + valaddr_reg:x8; val_offset:1826*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1826*FLEN/8, x10, x1, x4) + +inst_939: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02a and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3b0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x382a; op2val:0x6fb0; + valaddr_reg:x8; val_offset:1828*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1828*FLEN/8, x10, x1, x4) + +inst_940: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x29f and fs2 == 0 and fe2 == 0x1c and fm2 == 0x21d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a9f; op2val:0x721d; + valaddr_reg:x8; val_offset:1830*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1830*FLEN/8, x10, x1, x4) + +inst_941: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x29f and fs2 == 0 and fe2 == 0x1c and fm2 == 0x21d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a9f; op2val:0x721d; + valaddr_reg:x8; val_offset:1832*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1832*FLEN/8, x10, x1, x4) + +inst_942: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x29f and fs2 == 0 and fe2 == 0x1c and fm2 == 0x21d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a9f; op2val:0x721d; + valaddr_reg:x8; val_offset:1834*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1834*FLEN/8, x10, x1, x4) + +inst_943: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x29f and fs2 == 0 and fe2 == 0x1c and fm2 == 0x21d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a9f; op2val:0x721d; + valaddr_reg:x8; val_offset:1836*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1836*FLEN/8, x10, x1, x4) + +inst_944: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x29f and fs2 == 0 and fe2 == 0x1c and fm2 == 0x21d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a9f; op2val:0x721d; + valaddr_reg:x8; val_offset:1838*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1838*FLEN/8, x10, x1, x4) + +inst_945: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x16c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x101 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x396c; op2val:0x7101; + valaddr_reg:x8; val_offset:1840*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1840*FLEN/8, x10, x1, x4) + +inst_946: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x16c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x101 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x396c; op2val:0x7101; + valaddr_reg:x8; val_offset:1842*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1842*FLEN/8, x10, x1, x4) + +inst_947: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x16c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x101 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x396c; op2val:0x7101; + valaddr_reg:x8; val_offset:1844*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1844*FLEN/8, x10, x1, x4) + +inst_948: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x16c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x101 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x396c; op2val:0x7101; + valaddr_reg:x8; val_offset:1846*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1846*FLEN/8, x10, x1, x4) + +inst_949: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x16c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x101 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x396c; op2val:0x7101; + valaddr_reg:x8; val_offset:1848*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1848*FLEN/8, x10, x1, x4) + +inst_950: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d9 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x253 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ad9; op2val:0x7253; + valaddr_reg:x8; val_offset:1850*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1850*FLEN/8, x10, x1, x4) + +inst_951: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d9 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x253 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ad9; op2val:0x7253; + valaddr_reg:x8; val_offset:1852*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1852*FLEN/8, x10, x1, x4) + +inst_952: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d9 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x253 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ad9; op2val:0x7253; + valaddr_reg:x8; val_offset:1854*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1854*FLEN/8, x10, x1, x4) + +inst_953: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d9 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x253 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ad9; op2val:0x7253; + valaddr_reg:x8; val_offset:1856*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1856*FLEN/8, x10, x1, x4) + +inst_954: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d9 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x253 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ad9; op2val:0x7253; + valaddr_reg:x8; val_offset:1858*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1858*FLEN/8, x10, x1, x4) + +inst_955: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x029 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3b0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3829; op2val:0x6fb0; + valaddr_reg:x8; val_offset:1860*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1860*FLEN/8, x10, x1, x4) + +inst_956: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x029 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3b0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3829; op2val:0x6fb0; + valaddr_reg:x8; val_offset:1862*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1862*FLEN/8, x10, x1, x4) + +inst_957: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x029 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3b0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3829; op2val:0x6fb0; + valaddr_reg:x8; val_offset:1864*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1864*FLEN/8, x10, x1, x4) + +inst_958: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x029 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3b0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3829; op2val:0x6fb0; + valaddr_reg:x8; val_offset:1866*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1866*FLEN/8, x10, x1, x4) + +inst_959: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x029 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3b0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3829; op2val:0x6fb0; + valaddr_reg:x8; val_offset:1868*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1868*FLEN/8, x10, x1, x4) + +inst_960: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x041 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3db and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3841; op2val:0x6fdb; + valaddr_reg:x8; val_offset:1870*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1870*FLEN/8, x10, x1, x4) + +inst_961: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x041 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3db and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3841; op2val:0x6fdb; + valaddr_reg:x8; val_offset:1872*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1872*FLEN/8, x10, x1, x4) + +inst_962: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x041 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3db and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3841; op2val:0x6fdb; + valaddr_reg:x8; val_offset:1874*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1874*FLEN/8, x10, x1, x4) + +inst_963: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x041 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3db and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3841; op2val:0x6fdb; + valaddr_reg:x8; val_offset:1876*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1876*FLEN/8, x10, x1, x4) + +inst_964: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x041 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3db and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3841; op2val:0x6fdb; + valaddr_reg:x8; val_offset:1878*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1878*FLEN/8, x10, x1, x4) + +inst_965: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1b5 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x145 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x31b5; op2val:0x6945; + valaddr_reg:x8; val_offset:1880*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1880*FLEN/8, x10, x1, x4) + +inst_966: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1b5 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x145 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x31b5; op2val:0x6945; + valaddr_reg:x8; val_offset:1882*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1882*FLEN/8, x10, x1, x4) + +inst_967: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1b5 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x145 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x31b5; op2val:0x6945; + valaddr_reg:x8; val_offset:1884*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1884*FLEN/8, x10, x1, x4) + +inst_968: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1b5 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x145 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x31b5; op2val:0x6945; + valaddr_reg:x8; val_offset:1886*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1886*FLEN/8, x10, x1, x4) + +inst_969: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1b5 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x145 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x31b5; op2val:0x6945; + valaddr_reg:x8; val_offset:1888*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1888*FLEN/8, x10, x1, x4) + +inst_970: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x026 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3a9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3826; op2val:0x6fa9; + valaddr_reg:x8; val_offset:1890*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1890*FLEN/8, x10, x1, x4) + +inst_971: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x026 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3a9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3826; op2val:0x6fa9; + valaddr_reg:x8; val_offset:1892*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1892*FLEN/8, x10, x1, x4) + +inst_972: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x026 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3a9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3826; op2val:0x6fa9; + valaddr_reg:x8; val_offset:1894*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1894*FLEN/8, x10, x1, x4) + +inst_973: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x026 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3a9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3826; op2val:0x6fa9; + valaddr_reg:x8; val_offset:1896*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1896*FLEN/8, x10, x1, x4) + +inst_974: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x026 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3a9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3826; op2val:0x6fa9; + valaddr_reg:x8; val_offset:1898*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1898*FLEN/8, x10, x1, x4) + +inst_975: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x096 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x03c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3096; op2val:0x683c; + valaddr_reg:x8; val_offset:1900*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1900*FLEN/8, x10, x1, x4) + +inst_976: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x096 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x03c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3096; op2val:0x683c; + valaddr_reg:x8; val_offset:1902*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1902*FLEN/8, x10, x1, x4) + +inst_977: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x096 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x03c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3096; op2val:0x683c; + valaddr_reg:x8; val_offset:1904*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1904*FLEN/8, x10, x1, x4) + +inst_978: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x096 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x03c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3096; op2val:0x683c; + valaddr_reg:x8; val_offset:1906*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1906*FLEN/8, x10, x1, x4) + +inst_979: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x096 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x03c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3096; op2val:0x683c; + valaddr_reg:x8; val_offset:1908*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1908*FLEN/8, x10, x1, x4) + +inst_980: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x043 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x3df and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3443; op2val:0x6bdf; + valaddr_reg:x8; val_offset:1910*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1910*FLEN/8, x10, x1, x4) + +inst_981: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x043 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x3df and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3443; op2val:0x6bdf; + valaddr_reg:x8; val_offset:1912*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1912*FLEN/8, x10, x1, x4) + +inst_982: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x043 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x3df and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3443; op2val:0x6bdf; + valaddr_reg:x8; val_offset:1914*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1914*FLEN/8, x10, x1, x4) + +inst_983: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x043 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x3df and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3443; op2val:0x6bdf; + valaddr_reg:x8; val_offset:1916*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1916*FLEN/8, x10, x1, x4) + +inst_984: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x043 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x3df and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3443; op2val:0x6bdf; + valaddr_reg:x8; val_offset:1918*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1918*FLEN/8, x10, x1, x4) + +inst_985: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x042 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3de and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3842; op2val:0x6fde; + valaddr_reg:x8; val_offset:1920*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1920*FLEN/8, x10, x1, x4) + +inst_986: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x042 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3de and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3842; op2val:0x6fde; + valaddr_reg:x8; val_offset:1922*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1922*FLEN/8, x10, x1, x4) + +inst_987: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x042 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3de and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3842; op2val:0x6fde; + valaddr_reg:x8; val_offset:1924*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1924*FLEN/8, x10, x1, x4) + +inst_988: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x042 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3de and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3842; op2val:0x6fde; + valaddr_reg:x8; val_offset:1926*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1926*FLEN/8, x10, x1, x4) + +inst_989: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x042 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3de and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3842; op2val:0x6fde; + valaddr_reg:x8; val_offset:1928*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1928*FLEN/8, x10, x1, x4) + +inst_990: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x21f and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1a6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a1f; op2val:0x71a6; + valaddr_reg:x8; val_offset:1930*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1930*FLEN/8, x10, x1, x4) + +inst_991: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x21f and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1a6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a1f; op2val:0x71a6; + valaddr_reg:x8; val_offset:1932*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1932*FLEN/8, x10, x1, x4) + +inst_992: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x21f and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1a6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a1f; op2val:0x71a6; + valaddr_reg:x8; val_offset:1934*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1934*FLEN/8, x10, x1, x4) + +inst_993: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x21f and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1a6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a1f; op2val:0x71a6; + valaddr_reg:x8; val_offset:1936*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1936*FLEN/8, x10, x1, x4) + +inst_994: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x21f and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1a6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a1f; op2val:0x71a6; + valaddr_reg:x8; val_offset:1938*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1938*FLEN/8, x10, x1, x4) + +inst_995: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x131 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0cb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3531; op2val:0x6ccb; + valaddr_reg:x8; val_offset:1940*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1940*FLEN/8, x10, x1, x4) + +inst_996: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x131 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0cb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3531; op2val:0x6ccb; + valaddr_reg:x8; val_offset:1942*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1942*FLEN/8, x10, x1, x4) + +inst_997: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x131 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0cb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3531; op2val:0x6ccb; + valaddr_reg:x8; val_offset:1944*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1944*FLEN/8, x10, x1, x4) + +inst_998: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x131 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0cb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3531; op2val:0x6ccb; + valaddr_reg:x8; val_offset:1946*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1946*FLEN/8, x10, x1, x4) + +inst_999: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x131 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0cb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3531; op2val:0x6ccb; + valaddr_reg:x8; val_offset:1948*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1948*FLEN/8, x10, x1, x4) + +inst_1000: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0ad and fs2 == 0 and fe2 == 0x1a and fm2 == 0x051 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x30ad; op2val:0x6851; + valaddr_reg:x8; val_offset:1950*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1950*FLEN/8, x10, x1, x4) + +inst_1001: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0ad and fs2 == 0 and fe2 == 0x1a and fm2 == 0x051 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x30ad; op2val:0x6851; + valaddr_reg:x8; val_offset:1952*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1952*FLEN/8, x10, x1, x4) + +inst_1002: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0ad and fs2 == 0 and fe2 == 0x1a and fm2 == 0x051 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x30ad; op2val:0x6851; + valaddr_reg:x8; val_offset:1954*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1954*FLEN/8, x10, x1, x4) + +inst_1003: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0ad and fs2 == 0 and fe2 == 0x1a and fm2 == 0x051 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x30ad; op2val:0x6851; + valaddr_reg:x8; val_offset:1956*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1956*FLEN/8, x10, x1, x4) + +inst_1004: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0ad and fs2 == 0 and fe2 == 0x1a and fm2 == 0x051 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x30ad; op2val:0x6851; + valaddr_reg:x8; val_offset:1958*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1958*FLEN/8, x10, x1, x4) + +inst_1005: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x27b and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a7b; op2val:0x71fc; + valaddr_reg:x8; val_offset:1960*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1960*FLEN/8, x10, x1, x4) + +inst_1006: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x27b and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1fc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a7b; op2val:0x71fc; + valaddr_reg:x8; val_offset:1962*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1962*FLEN/8, x10, x1, x4) + +inst_1007: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x27b and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1fc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a7b; op2val:0x71fc; + valaddr_reg:x8; val_offset:1964*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1964*FLEN/8, x10, x1, x4) + +inst_1008: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x27b and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1fc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a7b; op2val:0x71fc; + valaddr_reg:x8; val_offset:1966*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1966*FLEN/8, x10, x1, x4) + +inst_1009: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x27b and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1fc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a7b; op2val:0x71fc; + valaddr_reg:x8; val_offset:1968*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1968*FLEN/8, x10, x1, x4) + +inst_1010: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x280 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a80; op2val:0x7200; + valaddr_reg:x8; val_offset:1970*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1970*FLEN/8, x10, x1, x4) + +inst_1011: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x280 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x200 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a80; op2val:0x7200; + valaddr_reg:x8; val_offset:1972*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1972*FLEN/8, x10, x1, x4) + +inst_1012: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x280 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x200 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a80; op2val:0x7200; + valaddr_reg:x8; val_offset:1974*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1974*FLEN/8, x10, x1, x4) + +inst_1013: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x280 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x200 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a80; op2val:0x7200; + valaddr_reg:x8; val_offset:1976*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1976*FLEN/8, x10, x1, x4) + +inst_1014: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x280 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x200 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a80; op2val:0x7200; + valaddr_reg:x8; val_offset:1978*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1978*FLEN/8, x10, x1, x4) + +inst_1015: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x086 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x02d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3086; op2val:0x682d; + valaddr_reg:x8; val_offset:1980*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1980*FLEN/8, x10, x1, x4) + +inst_1016: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x086 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x02d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3086; op2val:0x682d; + valaddr_reg:x8; val_offset:1982*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1982*FLEN/8, x10, x1, x4) + +inst_1017: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x086 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x02d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3086; op2val:0x682d; + valaddr_reg:x8; val_offset:1984*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1984*FLEN/8, x10, x1, x4) + +inst_1018: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x086 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x02d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3086; op2val:0x682d; + valaddr_reg:x8; val_offset:1986*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1986*FLEN/8, x10, x1, x4) + +inst_1019: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x086 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x02d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3086; op2val:0x682d; + valaddr_reg:x8; val_offset:1988*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1988*FLEN/8, x10, x1, x4) + +inst_1020: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1f5 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x180 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39f5; op2val:0x7180; + valaddr_reg:x8; val_offset:1990*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 1990*FLEN/8, x10, x1, x4) + +inst_1021: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1f5 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x180 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39f5; op2val:0x7180; + valaddr_reg:x8; val_offset:1992*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 1992*FLEN/8, x10, x1, x4) + +inst_1022: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1f5 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x180 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39f5; op2val:0x7180; + valaddr_reg:x8; val_offset:1994*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 1994*FLEN/8, x10, x1, x4) + +inst_1023: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1f5 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x180 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39f5; op2val:0x7180; + valaddr_reg:x8; val_offset:1996*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 1996*FLEN/8, x10, x1, x4) + +inst_1024: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1f5 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x180 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39f5; op2val:0x7180; + valaddr_reg:x8; val_offset:1998*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 1998*FLEN/8, x10, x1, x4) + +inst_1025: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x17e and fs2 == 0 and fe2 == 0x1c and fm2 == 0x112 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x397e; op2val:0x7112; + valaddr_reg:x8; val_offset:2000*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2000*FLEN/8, x10, x1, x4) + +inst_1026: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x17e and fs2 == 0 and fe2 == 0x1c and fm2 == 0x112 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x397e; op2val:0x7112; + valaddr_reg:x8; val_offset:2002*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2002*FLEN/8, x10, x1, x4) + +inst_1027: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x17e and fs2 == 0 and fe2 == 0x1c and fm2 == 0x112 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x397e; op2val:0x7112; + valaddr_reg:x8; val_offset:2004*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2004*FLEN/8, x10, x1, x4) + +inst_1028: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x17e and fs2 == 0 and fe2 == 0x1c and fm2 == 0x112 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x397e; op2val:0x7112; + valaddr_reg:x8; val_offset:2006*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2006*FLEN/8, x10, x1, x4) + +inst_1029: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x17e and fs2 == 0 and fe2 == 0x1c and fm2 == 0x112 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x397e; op2val:0x7112; + valaddr_reg:x8; val_offset:2008*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2008*FLEN/8, x10, x1, x4) + +inst_1030: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x056 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3456; op2val:0x6c01; + valaddr_reg:x8; val_offset:2010*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2010*FLEN/8, x10, x1, x4) + +inst_1031: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x056 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x001 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3456; op2val:0x6c01; + valaddr_reg:x8; val_offset:2012*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2012*FLEN/8, x10, x1, x4) + +inst_1032: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x056 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x001 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3456; op2val:0x6c01; + valaddr_reg:x8; val_offset:2014*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2014*FLEN/8, x10, x1, x4) + +inst_1033: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x056 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x001 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3456; op2val:0x6c01; + valaddr_reg:x8; val_offset:2016*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2016*FLEN/8, x10, x1, x4) + +inst_1034: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x056 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x001 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3456; op2val:0x6c01; + valaddr_reg:x8; val_offset:2018*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2018*FLEN/8, x10, x1, x4) + +inst_1035: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x342 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2b3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b42; op2val:0x72b3; + valaddr_reg:x8; val_offset:2020*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2020*FLEN/8, x10, x1, x4) + +inst_1036: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x342 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2b3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b42; op2val:0x72b3; + valaddr_reg:x8; val_offset:2022*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2022*FLEN/8, x10, x1, x4) + +inst_1037: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x342 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2b3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b42; op2val:0x72b3; + valaddr_reg:x8; val_offset:2024*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2024*FLEN/8, x10, x1, x4) + +inst_1038: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x342 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2b3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b42; op2val:0x72b3; + valaddr_reg:x8; val_offset:2026*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2026*FLEN/8, x10, x1, x4) + +inst_1039: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x342 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2b3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b42; op2val:0x72b3; + valaddr_reg:x8; val_offset:2028*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2028*FLEN/8, x10, x1, x4) + +inst_1040: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1aa and fs2 == 0 and fe2 == 0x1c and fm2 == 0x13b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39aa; op2val:0x713b; + valaddr_reg:x8; val_offset:2030*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2030*FLEN/8, x10, x1, x4) + +inst_1041: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1aa and fs2 == 0 and fe2 == 0x1c and fm2 == 0x13b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39aa; op2val:0x713b; + valaddr_reg:x8; val_offset:2032*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2032*FLEN/8, x10, x1, x4) + +inst_1042: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1aa and fs2 == 0 and fe2 == 0x1c and fm2 == 0x13b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39aa; op2val:0x713b; + valaddr_reg:x8; val_offset:2034*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2034*FLEN/8, x10, x1, x4) + +inst_1043: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1aa and fs2 == 0 and fe2 == 0x1c and fm2 == 0x13b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39aa; op2val:0x713b; + valaddr_reg:x8; val_offset:2036*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2036*FLEN/8, x10, x1, x4) + +inst_1044: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1aa and fs2 == 0 and fe2 == 0x1c and fm2 == 0x13b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39aa; op2val:0x713b; + valaddr_reg:x8; val_offset:2038*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2038*FLEN/8, x10, x1, x4) + +inst_1045: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2b7 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x1c2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x36b7; op2val:0x6dc2; + valaddr_reg:x8; val_offset:2040*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2040*FLEN/8, x10, x1, x4) + +inst_1046: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2b7 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x1c2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x36b7; op2val:0x6dc2; + valaddr_reg:x8; val_offset:2042*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2042*FLEN/8, x10, x1, x4) + +inst_1047: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2b7 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x1c2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x36b7; op2val:0x6dc2; + valaddr_reg:x8; val_offset:2044*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2044*FLEN/8, x10, x1, x4) + +inst_1048: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2b7 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x1c2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x36b7; op2val:0x6dc2; + valaddr_reg:x8; val_offset:2046*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2046*FLEN/8, x10, x1, x4) + +inst_1049: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2b7 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x1c2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x36b7; op2val:0x6dc2; + valaddr_reg:x8; val_offset:2048*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2048*FLEN/8, x10, x1, x4) + +inst_1050: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f1 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2d0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bf1; op2val:0x72d0; + valaddr_reg:x8; val_offset:2050*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2050*FLEN/8, x10, x1, x4) + +inst_1051: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f1 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2d0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bf1; op2val:0x72d0; + valaddr_reg:x8; val_offset:2052*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2052*FLEN/8, x10, x1, x4) + +inst_1052: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f1 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2d0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bf1; op2val:0x72d0; + valaddr_reg:x8; val_offset:2054*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2054*FLEN/8, x10, x1, x4) + +inst_1053: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f1 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2d0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bf1; op2val:0x72d0; + valaddr_reg:x8; val_offset:2056*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2056*FLEN/8, x10, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_8) + +inst_1054: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f1 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2d0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bf1; op2val:0x72d0; + valaddr_reg:x8; val_offset:2058*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2058*FLEN/8, x10, x1, x4) + +inst_1055: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x082 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3bc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3882; op2val:0x6fbc; + valaddr_reg:x8; val_offset:2060*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2060*FLEN/8, x10, x1, x4) + +inst_1056: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x082 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3bc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3882; op2val:0x6fbc; + valaddr_reg:x8; val_offset:2062*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2062*FLEN/8, x10, x1, x4) + +inst_1057: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x082 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3bc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3882; op2val:0x6fbc; + valaddr_reg:x8; val_offset:2064*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2064*FLEN/8, x10, x1, x4) + +inst_1058: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x082 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3bc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3882; op2val:0x6fbc; + valaddr_reg:x8; val_offset:2066*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2066*FLEN/8, x10, x1, x4) + +inst_1059: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x082 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3bc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3882; op2val:0x6fbc; + valaddr_reg:x8; val_offset:2068*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2068*FLEN/8, x10, x1, x4) + +inst_1060: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x251 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x16b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a51; op2val:0x716b; + valaddr_reg:x8; val_offset:2070*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2070*FLEN/8, x10, x1, x4) + +inst_1061: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x251 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x16b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a51; op2val:0x716b; + valaddr_reg:x8; val_offset:2072*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2072*FLEN/8, x10, x1, x4) + +inst_1062: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x251 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x16b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a51; op2val:0x716b; + valaddr_reg:x8; val_offset:2074*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2074*FLEN/8, x10, x1, x4) + +inst_1063: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x251 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x16b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a51; op2val:0x716b; + valaddr_reg:x8; val_offset:2076*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2076*FLEN/8, x10, x1, x4) + +inst_1064: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x251 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x16b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a51; op2val:0x716b; + valaddr_reg:x8; val_offset:2078*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2078*FLEN/8, x10, x1, x4) + +inst_1065: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x1b9 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x0e8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x29b9; op2val:0x60e8; + valaddr_reg:x8; val_offset:2080*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2080*FLEN/8, x10, x1, x4) + +inst_1066: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x1b9 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x0e8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x29b9; op2val:0x60e8; + valaddr_reg:x8; val_offset:2082*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2082*FLEN/8, x10, x1, x4) + +inst_1067: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x1b9 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x0e8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x29b9; op2val:0x60e8; + valaddr_reg:x8; val_offset:2084*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2084*FLEN/8, x10, x1, x4) + +inst_1068: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x1b9 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x0e8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x29b9; op2val:0x60e8; + valaddr_reg:x8; val_offset:2086*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2086*FLEN/8, x10, x1, x4) + +inst_1069: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x1b9 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x0e8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x29b9; op2val:0x60e8; + valaddr_reg:x8; val_offset:2088*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2088*FLEN/8, x10, x1, x4) + +inst_1070: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x34a and fs2 == 0 and fe2 == 0x1b and fm2 == 0x240 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x374a; op2val:0x6e40; + valaddr_reg:x8; val_offset:2090*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2090*FLEN/8, x10, x1, x4) + +inst_1071: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x34a and fs2 == 0 and fe2 == 0x1b and fm2 == 0x240 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x374a; op2val:0x6e40; + valaddr_reg:x8; val_offset:2092*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2092*FLEN/8, x10, x1, x4) + +inst_1072: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x34a and fs2 == 0 and fe2 == 0x1b and fm2 == 0x240 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x374a; op2val:0x6e40; + valaddr_reg:x8; val_offset:2094*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2094*FLEN/8, x10, x1, x4) + +inst_1073: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x34a and fs2 == 0 and fe2 == 0x1b and fm2 == 0x240 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x374a; op2val:0x6e40; + valaddr_reg:x8; val_offset:2096*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2096*FLEN/8, x10, x1, x4) + +inst_1074: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x34a and fs2 == 0 and fe2 == 0x1b and fm2 == 0x240 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x374a; op2val:0x6e40; + valaddr_reg:x8; val_offset:2098*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2098*FLEN/8, x10, x1, x4) + +inst_1075: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1cd and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0f9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39cd; op2val:0x70f9; + valaddr_reg:x8; val_offset:2100*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2100*FLEN/8, x10, x1, x4) + +inst_1076: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1cd and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0f9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39cd; op2val:0x70f9; + valaddr_reg:x8; val_offset:2102*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2102*FLEN/8, x10, x1, x4) + +inst_1077: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1cd and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0f9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39cd; op2val:0x70f9; + valaddr_reg:x8; val_offset:2104*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2104*FLEN/8, x10, x1, x4) + +inst_1078: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1cd and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0f9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39cd; op2val:0x70f9; + valaddr_reg:x8; val_offset:2106*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2106*FLEN/8, x10, x1, x4) + +inst_1079: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1cd and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0f9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39cd; op2val:0x70f9; + valaddr_reg:x8; val_offset:2108*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2108*FLEN/8, x10, x1, x4) + +inst_1080: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x319 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x216 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b19; op2val:0x7216; + valaddr_reg:x8; val_offset:2110*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2110*FLEN/8, x10, x1, x4) + +inst_1081: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x319 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x216 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b19; op2val:0x7216; + valaddr_reg:x8; val_offset:2112*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2112*FLEN/8, x10, x1, x4) + +inst_1082: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x319 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x216 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b19; op2val:0x7216; + valaddr_reg:x8; val_offset:2114*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2114*FLEN/8, x10, x1, x4) + +inst_1083: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x319 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x216 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b19; op2val:0x7216; + valaddr_reg:x8; val_offset:2116*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2116*FLEN/8, x10, x1, x4) + +inst_1084: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x319 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x216 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b19; op2val:0x7216; + valaddr_reg:x8; val_offset:2118*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2118*FLEN/8, x10, x1, x4) + +inst_1085: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1d7 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x102 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2dd7; op2val:0x6502; + valaddr_reg:x8; val_offset:2120*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2120*FLEN/8, x10, x1, x4) + +inst_1086: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1d7 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x102 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2dd7; op2val:0x6502; + valaddr_reg:x8; val_offset:2122*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2122*FLEN/8, x10, x1, x4) + +inst_1087: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1d7 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x102 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2dd7; op2val:0x6502; + valaddr_reg:x8; val_offset:2124*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2124*FLEN/8, x10, x1, x4) + +inst_1088: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1d7 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x102 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2dd7; op2val:0x6502; + valaddr_reg:x8; val_offset:2126*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2126*FLEN/8, x10, x1, x4) + +inst_1089: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1d7 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x102 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2dd7; op2val:0x6502; + valaddr_reg:x8; val_offset:2128*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2128*FLEN/8, x10, x1, x4) + +inst_1090: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x386 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x273 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b86; op2val:0x6273; + valaddr_reg:x8; val_offset:2130*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2130*FLEN/8, x10, x1, x4) + +inst_1091: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x386 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x273 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b86; op2val:0x6273; + valaddr_reg:x8; val_offset:2132*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2132*FLEN/8, x10, x1, x4) + +inst_1092: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x386 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x273 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b86; op2val:0x6273; + valaddr_reg:x8; val_offset:2134*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2134*FLEN/8, x10, x1, x4) + +inst_1093: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x386 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x273 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b86; op2val:0x6273; + valaddr_reg:x8; val_offset:2136*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2136*FLEN/8, x10, x1, x4) + +inst_1094: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x386 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x273 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b86; op2val:0x6273; + valaddr_reg:x8; val_offset:2138*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2138*FLEN/8, x10, x1, x4) + +inst_1095: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x348 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x23f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3348; op2val:0x6a3f; + valaddr_reg:x8; val_offset:2140*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2140*FLEN/8, x10, x1, x4) + +inst_1096: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x348 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x23f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3348; op2val:0x6a3f; + valaddr_reg:x8; val_offset:2142*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2142*FLEN/8, x10, x1, x4) + +inst_1097: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x348 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x23f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3348; op2val:0x6a3f; + valaddr_reg:x8; val_offset:2144*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2144*FLEN/8, x10, x1, x4) + +inst_1098: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x348 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x23f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3348; op2val:0x6a3f; + valaddr_reg:x8; val_offset:2146*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2146*FLEN/8, x10, x1, x4) + +inst_1099: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x348 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x23f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3348; op2val:0x6a3f; + valaddr_reg:x8; val_offset:2148*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2148*FLEN/8, x10, x1, x4) + +inst_1100: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a2 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0d5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39a2; op2val:0x70d5; + valaddr_reg:x8; val_offset:2150*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2150*FLEN/8, x10, x1, x4) + +inst_1101: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a2 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0d5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39a2; op2val:0x70d5; + valaddr_reg:x8; val_offset:2152*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2152*FLEN/8, x10, x1, x4) + +inst_1102: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a2 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0d5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39a2; op2val:0x70d5; + valaddr_reg:x8; val_offset:2154*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2154*FLEN/8, x10, x1, x4) + +inst_1103: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a2 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0d5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39a2; op2val:0x70d5; + valaddr_reg:x8; val_offset:2156*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2156*FLEN/8, x10, x1, x4) + +inst_1104: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a2 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0d5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39a2; op2val:0x70d5; + valaddr_reg:x8; val_offset:2158*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2158*FLEN/8, x10, x1, x4) + +inst_1105: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x189 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0bf and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3589; op2val:0x6cbf; + valaddr_reg:x8; val_offset:2160*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2160*FLEN/8, x10, x1, x4) + +inst_1106: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x189 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0bf and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3589; op2val:0x6cbf; + valaddr_reg:x8; val_offset:2162*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2162*FLEN/8, x10, x1, x4) + +inst_1107: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x189 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0bf and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3589; op2val:0x6cbf; + valaddr_reg:x8; val_offset:2164*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2164*FLEN/8, x10, x1, x4) + +inst_1108: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x189 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0bf and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3589; op2val:0x6cbf; + valaddr_reg:x8; val_offset:2166*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2166*FLEN/8, x10, x1, x4) + +inst_1109: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x189 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0bf and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3589; op2val:0x6cbf; + valaddr_reg:x8; val_offset:2168*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2168*FLEN/8, x10, x1, x4) + +inst_1110: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1e0 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x109 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39e0; op2val:0x7109; + valaddr_reg:x8; val_offset:2170*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2170*FLEN/8, x10, x1, x4) + +inst_1111: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1e0 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x109 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39e0; op2val:0x7109; + valaddr_reg:x8; val_offset:2172*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2172*FLEN/8, x10, x1, x4) + +inst_1112: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1e0 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x109 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39e0; op2val:0x7109; + valaddr_reg:x8; val_offset:2174*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2174*FLEN/8, x10, x1, x4) + +inst_1113: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1e0 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x109 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39e0; op2val:0x7109; + valaddr_reg:x8; val_offset:2176*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2176*FLEN/8, x10, x1, x4) + +inst_1114: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1e0 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x109 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39e0; op2val:0x7109; + valaddr_reg:x8; val_offset:2178*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2178*FLEN/8, x10, x1, x4) + +inst_1115: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x0f5 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x040 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x28f5; op2val:0x6040; + valaddr_reg:x8; val_offset:2180*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2180*FLEN/8, x10, x1, x4) + +inst_1116: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x0f5 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x040 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x28f5; op2val:0x6040; + valaddr_reg:x8; val_offset:2182*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2182*FLEN/8, x10, x1, x4) + +inst_1117: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x0f5 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x040 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x28f5; op2val:0x6040; + valaddr_reg:x8; val_offset:2184*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2184*FLEN/8, x10, x1, x4) + +inst_1118: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x0f5 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x040 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x28f5; op2val:0x6040; + valaddr_reg:x8; val_offset:2186*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2186*FLEN/8, x10, x1, x4) + +inst_1119: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x0f5 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x040 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x28f5; op2val:0x6040; + valaddr_reg:x8; val_offset:2188*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2188*FLEN/8, x10, x1, x4) + +inst_1120: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x36c and fs2 == 0 and fe2 == 0x1b and fm2 == 0x25d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x376c; op2val:0x6e5d; + valaddr_reg:x8; val_offset:2190*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2190*FLEN/8, x10, x1, x4) + +inst_1121: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x36c and fs2 == 0 and fe2 == 0x1b and fm2 == 0x25d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x376c; op2val:0x6e5d; + valaddr_reg:x8; val_offset:2192*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2192*FLEN/8, x10, x1, x4) + +inst_1122: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x36c and fs2 == 0 and fe2 == 0x1b and fm2 == 0x25d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x376c; op2val:0x6e5d; + valaddr_reg:x8; val_offset:2194*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2194*FLEN/8, x10, x1, x4) + +inst_1123: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x36c and fs2 == 0 and fe2 == 0x1b and fm2 == 0x25d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x376c; op2val:0x6e5d; + valaddr_reg:x8; val_offset:2196*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2196*FLEN/8, x10, x1, x4) + +inst_1124: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x36c and fs2 == 0 and fe2 == 0x1b and fm2 == 0x25d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x376c; op2val:0x6e5d; + valaddr_reg:x8; val_offset:2198*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2198*FLEN/8, x10, x1, x4) + +inst_1125: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x00c and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2f1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x380c; op2val:0x6ef1; + valaddr_reg:x8; val_offset:2200*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2200*FLEN/8, x10, x1, x4) + +inst_1126: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x00c and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2f1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x380c; op2val:0x6ef1; + valaddr_reg:x8; val_offset:2202*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2202*FLEN/8, x10, x1, x4) + +inst_1127: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x00c and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2f1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x380c; op2val:0x6ef1; + valaddr_reg:x8; val_offset:2204*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2204*FLEN/8, x10, x1, x4) + +inst_1128: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x00c and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2f1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x380c; op2val:0x6ef1; + valaddr_reg:x8; val_offset:2206*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2206*FLEN/8, x10, x1, x4) + +inst_1129: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x00c and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2f1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x380c; op2val:0x6ef1; + valaddr_reg:x8; val_offset:2208*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2208*FLEN/8, x10, x1, x4) + +inst_1130: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x082 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x3bc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3482; op2val:0x6bbc; + valaddr_reg:x8; val_offset:2210*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2210*FLEN/8, x10, x1, x4) + +inst_1131: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x082 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x3bc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3482; op2val:0x6bbc; + valaddr_reg:x8; val_offset:2212*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2212*FLEN/8, x10, x1, x4) + +inst_1132: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x082 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x3bc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3482; op2val:0x6bbc; + valaddr_reg:x8; val_offset:2214*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2214*FLEN/8, x10, x1, x4) + +inst_1133: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x082 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x3bc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3482; op2val:0x6bbc; + valaddr_reg:x8; val_offset:2216*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2216*FLEN/8, x10, x1, x4) + +inst_1134: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x082 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x3bc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3482; op2val:0x6bbc; + valaddr_reg:x8; val_offset:2218*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2218*FLEN/8, x10, x1, x4) + +inst_1135: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2f0 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x1f3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x36f0; op2val:0x6df3; + valaddr_reg:x8; val_offset:2220*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2220*FLEN/8, x10, x1, x4) + +inst_1136: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2f0 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x1f3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x36f0; op2val:0x6df3; + valaddr_reg:x8; val_offset:2222*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2222*FLEN/8, x10, x1, x4) + +inst_1137: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2f0 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x1f3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x36f0; op2val:0x6df3; + valaddr_reg:x8; val_offset:2224*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2224*FLEN/8, x10, x1, x4) + +inst_1138: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2f0 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x1f3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x36f0; op2val:0x6df3; + valaddr_reg:x8; val_offset:2226*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2226*FLEN/8, x10, x1, x4) + +inst_1139: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2f0 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x1f3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x36f0; op2val:0x6df3; + valaddr_reg:x8; val_offset:2228*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2228*FLEN/8, x10, x1, x4) + +inst_1140: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ab and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0dc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x35ab; op2val:0x6cdc; + valaddr_reg:x8; val_offset:2230*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2230*FLEN/8, x10, x1, x4) + +inst_1141: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ab and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0dc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x35ab; op2val:0x6cdc; + valaddr_reg:x8; val_offset:2232*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2232*FLEN/8, x10, x1, x4) + +inst_1142: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ab and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0dc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x35ab; op2val:0x6cdc; + valaddr_reg:x8; val_offset:2234*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2234*FLEN/8, x10, x1, x4) + +inst_1143: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ab and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0dc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x35ab; op2val:0x6cdc; + valaddr_reg:x8; val_offset:2236*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2236*FLEN/8, x10, x1, x4) + +inst_1144: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ab and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0dc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x35ab; op2val:0x6cdc; + valaddr_reg:x8; val_offset:2238*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2238*FLEN/8, x10, x1, x4) + +inst_1145: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x291 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1a1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a91; op2val:0x71a1; + valaddr_reg:x8; val_offset:2240*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2240*FLEN/8, x10, x1, x4) + +inst_1146: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x291 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1a1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a91; op2val:0x71a1; + valaddr_reg:x8; val_offset:2242*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2242*FLEN/8, x10, x1, x4) + +inst_1147: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x291 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1a1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a91; op2val:0x71a1; + valaddr_reg:x8; val_offset:2244*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2244*FLEN/8, x10, x1, x4) + +inst_1148: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x291 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1a1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a91; op2val:0x71a1; + valaddr_reg:x8; val_offset:2246*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2246*FLEN/8, x10, x1, x4) + +inst_1149: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x291 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1a1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a91; op2val:0x71a1; + valaddr_reg:x8; val_offset:2248*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2248*FLEN/8, x10, x1, x4) + +inst_1150: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x183 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0ba and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3583; op2val:0x6cba; + valaddr_reg:x8; val_offset:2250*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2250*FLEN/8, x10, x1, x4) + +inst_1151: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x183 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0ba and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3583; op2val:0x6cba; + valaddr_reg:x8; val_offset:2252*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2252*FLEN/8, x10, x1, x4) + +inst_1152: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x183 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0ba and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3583; op2val:0x6cba; + valaddr_reg:x8; val_offset:2254*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2254*FLEN/8, x10, x1, x4) + +inst_1153: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x183 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0ba and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3583; op2val:0x6cba; + valaddr_reg:x8; val_offset:2256*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2256*FLEN/8, x10, x1, x4) + +inst_1154: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x183 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0ba and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3583; op2val:0x6cba; + valaddr_reg:x8; val_offset:2258*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2258*FLEN/8, x10, x1, x4) + +inst_1155: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x05d and fs2 == 0 and fe2 == 0x18 and fm2 == 0x37c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2c5d; op2val:0x637c; + valaddr_reg:x8; val_offset:2260*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2260*FLEN/8, x10, x1, x4) + +inst_1156: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x05d and fs2 == 0 and fe2 == 0x18 and fm2 == 0x37c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2c5d; op2val:0x637c; + valaddr_reg:x8; val_offset:2262*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2262*FLEN/8, x10, x1, x4) + +inst_1157: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x05d and fs2 == 0 and fe2 == 0x18 and fm2 == 0x37c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2c5d; op2val:0x637c; + valaddr_reg:x8; val_offset:2264*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2264*FLEN/8, x10, x1, x4) + +inst_1158: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x05d and fs2 == 0 and fe2 == 0x18 and fm2 == 0x37c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2c5d; op2val:0x637c; + valaddr_reg:x8; val_offset:2266*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2266*FLEN/8, x10, x1, x4) + +inst_1159: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x05d and fs2 == 0 and fe2 == 0x18 and fm2 == 0x37c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2c5d; op2val:0x637c; + valaddr_reg:x8; val_offset:2268*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2268*FLEN/8, x10, x1, x4) + +inst_1160: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x159 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x095 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3959; op2val:0x7095; + valaddr_reg:x8; val_offset:2270*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2270*FLEN/8, x10, x1, x4) + +inst_1161: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x159 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x095 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3959; op2val:0x7095; + valaddr_reg:x8; val_offset:2272*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2272*FLEN/8, x10, x1, x4) + +inst_1162: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x159 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x095 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3959; op2val:0x7095; + valaddr_reg:x8; val_offset:2274*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2274*FLEN/8, x10, x1, x4) + +inst_1163: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x159 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x095 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3959; op2val:0x7095; + valaddr_reg:x8; val_offset:2276*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2276*FLEN/8, x10, x1, x4) + +inst_1164: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x159 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x095 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3959; op2val:0x7095; + valaddr_reg:x8; val_offset:2278*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2278*FLEN/8, x10, x1, x4) + +inst_1165: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x271 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x186 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3671; op2val:0x6d86; + valaddr_reg:x8; val_offset:2280*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2280*FLEN/8, x10, x1, x4) + +inst_1166: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x271 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x186 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3671; op2val:0x6d86; + valaddr_reg:x8; val_offset:2282*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2282*FLEN/8, x10, x1, x4) + +inst_1167: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x271 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x186 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3671; op2val:0x6d86; + valaddr_reg:x8; val_offset:2284*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2284*FLEN/8, x10, x1, x4) + +inst_1168: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x271 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x186 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3671; op2val:0x6d86; + valaddr_reg:x8; val_offset:2286*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2286*FLEN/8, x10, x1, x4) + +inst_1169: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x271 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x186 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3671; op2val:0x6d86; + valaddr_reg:x8; val_offset:2288*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2288*FLEN/8, x10, x1, x4) + +inst_1170: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a4 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0d6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x35a4; op2val:0x6cd6; + valaddr_reg:x8; val_offset:2290*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2290*FLEN/8, x10, x1, x4) + +inst_1171: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a4 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0d6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x35a4; op2val:0x6cd6; + valaddr_reg:x8; val_offset:2292*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2292*FLEN/8, x10, x1, x4) + +inst_1172: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a4 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0d6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x35a4; op2val:0x6cd6; + valaddr_reg:x8; val_offset:2294*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2294*FLEN/8, x10, x1, x4) + +inst_1173: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a4 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0d6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x35a4; op2val:0x6cd6; + valaddr_reg:x8; val_offset:2296*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2296*FLEN/8, x10, x1, x4) + +inst_1174: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a4 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0d6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x35a4; op2val:0x6cd6; + valaddr_reg:x8; val_offset:2298*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2298*FLEN/8, x10, x1, x4) + +inst_1175: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x180 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0b7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3980; op2val:0x70b7; + valaddr_reg:x8; val_offset:2300*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2300*FLEN/8, x10, x1, x4) + +inst_1176: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x180 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0b7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3980; op2val:0x70b7; + valaddr_reg:x8; val_offset:2302*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2302*FLEN/8, x10, x1, x4) + +inst_1177: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x180 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0b7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3980; op2val:0x70b7; + valaddr_reg:x8; val_offset:2304*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2304*FLEN/8, x10, x1, x4) + +inst_1178: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x180 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0b7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3980; op2val:0x70b7; + valaddr_reg:x8; val_offset:2306*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2306*FLEN/8, x10, x1, x4) + +inst_1179: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x180 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0b7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3980; op2val:0x70b7; + valaddr_reg:x8; val_offset:2308*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2308*FLEN/8, x10, x1, x4) + +inst_1180: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x373 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x263 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b73; op2val:0x7263; + valaddr_reg:x8; val_offset:2310*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2310*FLEN/8, x10, x1, x4) + +inst_1181: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x373 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x263 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b73; op2val:0x7263; + valaddr_reg:x8; val_offset:2312*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2312*FLEN/8, x10, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_9) + +inst_1182: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x373 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x263 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b73; op2val:0x7263; + valaddr_reg:x8; val_offset:2314*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2314*FLEN/8, x10, x1, x4) + +inst_1183: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x373 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x263 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b73; op2val:0x7263; + valaddr_reg:x8; val_offset:2316*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2316*FLEN/8, x10, x1, x4) + +inst_1184: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x373 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x263 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b73; op2val:0x7263; + valaddr_reg:x8; val_offset:2318*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2318*FLEN/8, x10, x1, x4) + +inst_1185: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3db and fs2 == 0 and fe2 == 0x1a and fm2 == 0x2bd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x33db; op2val:0x6abd; + valaddr_reg:x8; val_offset:2320*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2320*FLEN/8, x10, x1, x4) + +inst_1186: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3db and fs2 == 0 and fe2 == 0x1a and fm2 == 0x2bd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x33db; op2val:0x6abd; + valaddr_reg:x8; val_offset:2322*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2322*FLEN/8, x10, x1, x4) + +inst_1187: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3db and fs2 == 0 and fe2 == 0x1a and fm2 == 0x2bd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x33db; op2val:0x6abd; + valaddr_reg:x8; val_offset:2324*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2324*FLEN/8, x10, x1, x4) + +inst_1188: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3db and fs2 == 0 and fe2 == 0x1a and fm2 == 0x2bd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x33db; op2val:0x6abd; + valaddr_reg:x8; val_offset:2326*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2326*FLEN/8, x10, x1, x4) + +inst_1189: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3db and fs2 == 0 and fe2 == 0x1a and fm2 == 0x2bd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x33db; op2val:0x6abd; + valaddr_reg:x8; val_offset:2328*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2328*FLEN/8, x10, x1, x4) + +inst_1190: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x02a and fs2 == 0 and fe2 == 0x1a and fm2 == 0x325 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x342a; op2val:0x6b25; + valaddr_reg:x8; val_offset:2330*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2330*FLEN/8, x10, x1, x4) + +inst_1191: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x02a and fs2 == 0 and fe2 == 0x1a and fm2 == 0x325 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x342a; op2val:0x6b25; + valaddr_reg:x8; val_offset:2332*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2332*FLEN/8, x10, x1, x4) + +inst_1192: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x02a and fs2 == 0 and fe2 == 0x1a and fm2 == 0x325 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x342a; op2val:0x6b25; + valaddr_reg:x8; val_offset:2334*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2334*FLEN/8, x10, x1, x4) + +inst_1193: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x02a and fs2 == 0 and fe2 == 0x1a and fm2 == 0x325 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x342a; op2val:0x6b25; + valaddr_reg:x8; val_offset:2336*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2336*FLEN/8, x10, x1, x4) + +inst_1194: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x02a and fs2 == 0 and fe2 == 0x1a and fm2 == 0x325 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x342a; op2val:0x6b25; + valaddr_reg:x8; val_offset:2338*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2338*FLEN/8, x10, x1, x4) + +inst_1195: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1df and fs2 == 0 and fe2 == 0x1c and fm2 == 0x109 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39df; op2val:0x7109; + valaddr_reg:x8; val_offset:2340*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2340*FLEN/8, x10, x1, x4) + +inst_1196: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1df and fs2 == 0 and fe2 == 0x1c and fm2 == 0x109 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39df; op2val:0x7109; + valaddr_reg:x8; val_offset:2342*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2342*FLEN/8, x10, x1, x4) + +inst_1197: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1df and fs2 == 0 and fe2 == 0x1c and fm2 == 0x109 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39df; op2val:0x7109; + valaddr_reg:x8; val_offset:2344*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2344*FLEN/8, x10, x1, x4) + +inst_1198: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1df and fs2 == 0 and fe2 == 0x1c and fm2 == 0x109 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39df; op2val:0x7109; + valaddr_reg:x8; val_offset:2346*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2346*FLEN/8, x10, x1, x4) + +inst_1199: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1df and fs2 == 0 and fe2 == 0x1c and fm2 == 0x109 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39df; op2val:0x7109; + valaddr_reg:x8; val_offset:2348*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2348*FLEN/8, x10, x1, x4) + +inst_1200: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x014 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x2ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3014; op2val:0x66ff; + valaddr_reg:x8; val_offset:2350*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2350*FLEN/8, x10, x1, x4) + +inst_1201: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x014 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x2ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3014; op2val:0x66ff; + valaddr_reg:x8; val_offset:2352*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2352*FLEN/8, x10, x1, x4) + +inst_1202: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x014 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x2ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3014; op2val:0x66ff; + valaddr_reg:x8; val_offset:2354*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2354*FLEN/8, x10, x1, x4) + +inst_1203: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x014 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x2ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3014; op2val:0x66ff; + valaddr_reg:x8; val_offset:2356*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2356*FLEN/8, x10, x1, x4) + +inst_1204: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x014 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x2ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3014; op2val:0x66ff; + valaddr_reg:x8; val_offset:2358*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2358*FLEN/8, x10, x1, x4) + +inst_1205: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ec and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2cb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x37ec; op2val:0x6ecb; + valaddr_reg:x8; val_offset:2360*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2360*FLEN/8, x10, x1, x4) + +inst_1206: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ec and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2cb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x37ec; op2val:0x6ecb; + valaddr_reg:x8; val_offset:2362*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2362*FLEN/8, x10, x1, x4) + +inst_1207: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ec and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2cb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x37ec; op2val:0x6ecb; + valaddr_reg:x8; val_offset:2364*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2364*FLEN/8, x10, x1, x4) + +inst_1208: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ec and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2cb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x37ec; op2val:0x6ecb; + valaddr_reg:x8; val_offset:2366*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2366*FLEN/8, x10, x1, x4) + +inst_1209: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ec and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2cb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x37ec; op2val:0x6ecb; + valaddr_reg:x8; val_offset:2368*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2368*FLEN/8, x10, x1, x4) + +inst_1210: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x365 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x257 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3365; op2val:0x6a57; + valaddr_reg:x8; val_offset:2370*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2370*FLEN/8, x10, x1, x4) + +inst_1211: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x365 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x257 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3365; op2val:0x6a57; + valaddr_reg:x8; val_offset:2372*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2372*FLEN/8, x10, x1, x4) + +inst_1212: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x365 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x257 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3365; op2val:0x6a57; + valaddr_reg:x8; val_offset:2374*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2374*FLEN/8, x10, x1, x4) + +inst_1213: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x365 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x257 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3365; op2val:0x6a57; + valaddr_reg:x8; val_offset:2376*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2376*FLEN/8, x10, x1, x4) + +inst_1214: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x365 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x257 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3365; op2val:0x6a57; + valaddr_reg:x8; val_offset:2378*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2378*FLEN/8, x10, x1, x4) + +inst_1215: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x156 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x093 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3956; op2val:0x7093; + valaddr_reg:x8; val_offset:2380*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2380*FLEN/8, x10, x1, x4) + +inst_1216: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x156 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x093 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3956; op2val:0x7093; + valaddr_reg:x8; val_offset:2382*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2382*FLEN/8, x10, x1, x4) + +inst_1217: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x156 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x093 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3956; op2val:0x7093; + valaddr_reg:x8; val_offset:2384*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2384*FLEN/8, x10, x1, x4) + +inst_1218: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x156 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x093 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3956; op2val:0x7093; + valaddr_reg:x8; val_offset:2386*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2386*FLEN/8, x10, x1, x4) + +inst_1219: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x156 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x093 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3956; op2val:0x7093; + valaddr_reg:x8; val_offset:2388*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2388*FLEN/8, x10, x1, x4) + +inst_1220: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x356 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x24a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3756; op2val:0x6e4a; + valaddr_reg:x8; val_offset:2390*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2390*FLEN/8, x10, x1, x4) + +inst_1221: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x356 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x24a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3756; op2val:0x6e4a; + valaddr_reg:x8; val_offset:2392*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2392*FLEN/8, x10, x1, x4) + +inst_1222: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x356 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x24a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3756; op2val:0x6e4a; + valaddr_reg:x8; val_offset:2394*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2394*FLEN/8, x10, x1, x4) + +inst_1223: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x356 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x24a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3756; op2val:0x6e4a; + valaddr_reg:x8; val_offset:2396*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2396*FLEN/8, x10, x1, x4) + +inst_1224: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x356 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x24a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3756; op2val:0x6e4a; + valaddr_reg:x8; val_offset:2398*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2398*FLEN/8, x10, x1, x4) + +inst_1225: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x12d and fs2 == 0 and fe2 == 0x1c and fm2 == 0x070 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x392d; op2val:0x7070; + valaddr_reg:x8; val_offset:2400*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2400*FLEN/8, x10, x1, x4) + +inst_1226: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x12d and fs2 == 0 and fe2 == 0x1c and fm2 == 0x070 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x392d; op2val:0x7070; + valaddr_reg:x8; val_offset:2402*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2402*FLEN/8, x10, x1, x4) + +inst_1227: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x12d and fs2 == 0 and fe2 == 0x1c and fm2 == 0x070 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x392d; op2val:0x7070; + valaddr_reg:x8; val_offset:2404*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2404*FLEN/8, x10, x1, x4) + +inst_1228: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x12d and fs2 == 0 and fe2 == 0x1c and fm2 == 0x070 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x392d; op2val:0x7070; + valaddr_reg:x8; val_offset:2406*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2406*FLEN/8, x10, x1, x4) + +inst_1229: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x12d and fs2 == 0 and fe2 == 0x1c and fm2 == 0x070 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x392d; op2val:0x7070; + valaddr_reg:x8; val_offset:2408*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2408*FLEN/8, x10, x1, x4) + +inst_1230: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31a and fs2 == 0 and fe2 == 0x1c and fm2 == 0x217 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b1a; op2val:0x7217; + valaddr_reg:x8; val_offset:2410*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2410*FLEN/8, x10, x1, x4) + +inst_1231: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31a and fs2 == 0 and fe2 == 0x1c and fm2 == 0x217 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b1a; op2val:0x7217; + valaddr_reg:x8; val_offset:2412*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2412*FLEN/8, x10, x1, x4) + +inst_1232: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31a and fs2 == 0 and fe2 == 0x1c and fm2 == 0x217 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b1a; op2val:0x7217; + valaddr_reg:x8; val_offset:2414*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2414*FLEN/8, x10, x1, x4) + +inst_1233: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31a and fs2 == 0 and fe2 == 0x1c and fm2 == 0x217 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b1a; op2val:0x7217; + valaddr_reg:x8; val_offset:2416*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2416*FLEN/8, x10, x1, x4) + +inst_1234: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31a and fs2 == 0 and fe2 == 0x1c and fm2 == 0x217 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b1a; op2val:0x7217; + valaddr_reg:x8; val_offset:2418*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2418*FLEN/8, x10, x1, x4) + +inst_1235: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x333 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x22d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b33; op2val:0x722d; + valaddr_reg:x8; val_offset:2420*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2420*FLEN/8, x10, x1, x4) + +inst_1236: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x333 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x22d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b33; op2val:0x722d; + valaddr_reg:x8; val_offset:2422*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2422*FLEN/8, x10, x1, x4) + +inst_1237: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x333 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x22d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b33; op2val:0x722d; + valaddr_reg:x8; val_offset:2424*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2424*FLEN/8, x10, x1, x4) + +inst_1238: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x333 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x22d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b33; op2val:0x722d; + valaddr_reg:x8; val_offset:2426*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2426*FLEN/8, x10, x1, x4) + +inst_1239: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x333 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x22d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b33; op2val:0x722d; + valaddr_reg:x8; val_offset:2428*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2428*FLEN/8, x10, x1, x4) + +inst_1240: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x313 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x210 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3313; op2val:0x6a10; + valaddr_reg:x8; val_offset:2430*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2430*FLEN/8, x10, x1, x4) + +inst_1241: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x313 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x210 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3313; op2val:0x6a10; + valaddr_reg:x8; val_offset:2432*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2432*FLEN/8, x10, x1, x4) + +inst_1242: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x313 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x210 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3313; op2val:0x6a10; + valaddr_reg:x8; val_offset:2434*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2434*FLEN/8, x10, x1, x4) + +inst_1243: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x313 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x210 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3313; op2val:0x6a10; + valaddr_reg:x8; val_offset:2436*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2436*FLEN/8, x10, x1, x4) + +inst_1244: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x313 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x210 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3313; op2val:0x6a10; + valaddr_reg:x8; val_offset:2438*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2438*FLEN/8, x10, x1, x4) + +inst_1245: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x285 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x197 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a85; op2val:0x7197; + valaddr_reg:x8; val_offset:2440*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2440*FLEN/8, x10, x1, x4) + +inst_1246: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x285 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x197 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a85; op2val:0x7197; + valaddr_reg:x8; val_offset:2442*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2442*FLEN/8, x10, x1, x4) + +inst_1247: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x285 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x197 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a85; op2val:0x7197; + valaddr_reg:x8; val_offset:2444*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2444*FLEN/8, x10, x1, x4) + +inst_1248: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x285 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x197 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a85; op2val:0x7197; + valaddr_reg:x8; val_offset:2446*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2446*FLEN/8, x10, x1, x4) + +inst_1249: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x285 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x197 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a85; op2val:0x7197; + valaddr_reg:x8; val_offset:2448*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2448*FLEN/8, x10, x1, x4) + +inst_1250: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0aa and fs2 == 0 and fe2 == 0x1c and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x38aa; op2val:0x7000; + valaddr_reg:x8; val_offset:2450*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2450*FLEN/8, x10, x1, x4) + +inst_1251: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0aa and fs2 == 0 and fe2 == 0x1c and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x38aa; op2val:0x7000; + valaddr_reg:x8; val_offset:2452*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2452*FLEN/8, x10, x1, x4) + +inst_1252: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0aa and fs2 == 0 and fe2 == 0x1c and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x38aa; op2val:0x7000; + valaddr_reg:x8; val_offset:2454*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2454*FLEN/8, x10, x1, x4) + +inst_1253: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0aa and fs2 == 0 and fe2 == 0x1c and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x38aa; op2val:0x7000; + valaddr_reg:x8; val_offset:2456*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2456*FLEN/8, x10, x1, x4) + +inst_1254: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0aa and fs2 == 0 and fe2 == 0x1c and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x38aa; op2val:0x7000; + valaddr_reg:x8; val_offset:2458*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2458*FLEN/8, x10, x1, x4) + +inst_1255: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x28c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x28c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x528c; op2val:0x3a8c; + valaddr_reg:x8; val_offset:2460*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2460*FLEN/8, x10, x1, x4) + +inst_1256: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x28c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x28c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x528c; op2val:0x3a8c; + valaddr_reg:x8; val_offset:2462*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2462*FLEN/8, x10, x1, x4) + +inst_1257: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x28c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x28c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x528c; op2val:0x3a8c; + valaddr_reg:x8; val_offset:2464*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2464*FLEN/8, x10, x1, x4) + +inst_1258: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x28c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x28c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x528c; op2val:0x3a8c; + valaddr_reg:x8; val_offset:2466*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2466*FLEN/8, x10, x1, x4) + +inst_1259: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x28c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x28c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x528c; op2val:0x3a8c; + valaddr_reg:x8; val_offset:2468*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2468*FLEN/8, x10, x1, x4) + +inst_1260: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x0c9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0c9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x50c9; op2val:0x38c9; + valaddr_reg:x8; val_offset:2470*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2470*FLEN/8, x10, x1, x4) + +inst_1261: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x0c9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0c9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x50c9; op2val:0x38c9; + valaddr_reg:x8; val_offset:2472*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2472*FLEN/8, x10, x1, x4) + +inst_1262: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x0c9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0c9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x50c9; op2val:0x38c9; + valaddr_reg:x8; val_offset:2474*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2474*FLEN/8, x10, x1, x4) + +inst_1263: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x0c9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0c9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x50c9; op2val:0x38c9; + valaddr_reg:x8; val_offset:2476*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2476*FLEN/8, x10, x1, x4) + +inst_1264: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x0c9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0c9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x50c9; op2val:0x38c9; + valaddr_reg:x8; val_offset:2478*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2478*FLEN/8, x10, x1, x4) + +inst_1265: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x286 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x286 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4e86; op2val:0x3686; + valaddr_reg:x8; val_offset:2480*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2480*FLEN/8, x10, x1, x4) + +inst_1266: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x286 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x286 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4e86; op2val:0x3686; + valaddr_reg:x8; val_offset:2482*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2482*FLEN/8, x10, x1, x4) + +inst_1267: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x286 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x286 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4e86; op2val:0x3686; + valaddr_reg:x8; val_offset:2484*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2484*FLEN/8, x10, x1, x4) + +inst_1268: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x286 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x286 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4e86; op2val:0x3686; + valaddr_reg:x8; val_offset:2486*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2486*FLEN/8, x10, x1, x4) + +inst_1269: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x286 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x286 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4e86; op2val:0x3686; + valaddr_reg:x8; val_offset:2488*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2488*FLEN/8, x10, x1, x4) + +inst_1270: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x047 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x047 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5047; op2val:0x3847; + valaddr_reg:x8; val_offset:2490*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2490*FLEN/8, x10, x1, x4) + +inst_1271: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x047 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x047 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5047; op2val:0x3847; + valaddr_reg:x8; val_offset:2492*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2492*FLEN/8, x10, x1, x4) + +inst_1272: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x047 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x047 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5047; op2val:0x3847; + valaddr_reg:x8; val_offset:2494*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2494*FLEN/8, x10, x1, x4) + +inst_1273: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x047 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x047 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5047; op2val:0x3847; + valaddr_reg:x8; val_offset:2496*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2496*FLEN/8, x10, x1, x4) + +inst_1274: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x047 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x047 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5047; op2val:0x3847; + valaddr_reg:x8; val_offset:2498*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2498*FLEN/8, x10, x1, x4) + +inst_1275: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x2dd and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2dd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4add; op2val:0x32dd; + valaddr_reg:x8; val_offset:2500*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2500*FLEN/8, x10, x1, x4) + +inst_1276: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x2dd and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2dd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4add; op2val:0x32dd; + valaddr_reg:x8; val_offset:2502*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2502*FLEN/8, x10, x1, x4) + +inst_1277: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x2dd and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2dd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4add; op2val:0x32dd; + valaddr_reg:x8; val_offset:2504*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2504*FLEN/8, x10, x1, x4) + +inst_1278: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x2dd and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2dd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4add; op2val:0x32dd; + valaddr_reg:x8; val_offset:2506*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2506*FLEN/8, x10, x1, x4) + +inst_1279: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x2dd and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2dd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4add; op2val:0x32dd; + valaddr_reg:x8; val_offset:2508*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2508*FLEN/8, x10, x1, x4) + +inst_1280: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x248 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x247 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5248; op2val:0x3a47; + valaddr_reg:x8; val_offset:2510*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2510*FLEN/8, x10, x1, x4) + +inst_1281: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x248 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x247 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5248; op2val:0x3a47; + valaddr_reg:x8; val_offset:2512*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2512*FLEN/8, x10, x1, x4) + +inst_1282: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x248 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x247 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5248; op2val:0x3a47; + valaddr_reg:x8; val_offset:2514*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2514*FLEN/8, x10, x1, x4) + +inst_1283: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x248 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x247 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5248; op2val:0x3a47; + valaddr_reg:x8; val_offset:2516*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2516*FLEN/8, x10, x1, x4) + +inst_1284: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x248 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x247 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5248; op2val:0x3a47; + valaddr_reg:x8; val_offset:2518*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2518*FLEN/8, x10, x1, x4) + +inst_1285: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x273 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x273 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5273; op2val:0x3a73; + valaddr_reg:x8; val_offset:2520*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2520*FLEN/8, x10, x1, x4) + +inst_1286: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x273 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x273 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5273; op2val:0x3a73; + valaddr_reg:x8; val_offset:2522*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2522*FLEN/8, x10, x1, x4) + +inst_1287: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x273 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x273 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5273; op2val:0x3a73; + valaddr_reg:x8; val_offset:2524*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2524*FLEN/8, x10, x1, x4) + +inst_1288: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x273 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x273 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5273; op2val:0x3a73; + valaddr_reg:x8; val_offset:2526*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2526*FLEN/8, x10, x1, x4) + +inst_1289: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x273 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x273 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5273; op2val:0x3a73; + valaddr_reg:x8; val_offset:2528*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2528*FLEN/8, x10, x1, x4) + +inst_1290: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x39a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x399 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x539a; op2val:0x3b99; + valaddr_reg:x8; val_offset:2530*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2530*FLEN/8, x10, x1, x4) + +inst_1291: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x39a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x399 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x539a; op2val:0x3b99; + valaddr_reg:x8; val_offset:2532*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2532*FLEN/8, x10, x1, x4) + +inst_1292: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x39a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x399 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x539a; op2val:0x3b99; + valaddr_reg:x8; val_offset:2534*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2534*FLEN/8, x10, x1, x4) + +inst_1293: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x39a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x399 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x539a; op2val:0x3b99; + valaddr_reg:x8; val_offset:2536*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2536*FLEN/8, x10, x1, x4) + +inst_1294: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x39a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x399 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x539a; op2val:0x3b99; + valaddr_reg:x8; val_offset:2538*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2538*FLEN/8, x10, x1, x4) + +inst_1295: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x07a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x07a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x507a; op2val:0x387a; + valaddr_reg:x8; val_offset:2540*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2540*FLEN/8, x10, x1, x4) + +inst_1296: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x07a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x07a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x507a; op2val:0x387a; + valaddr_reg:x8; val_offset:2542*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2542*FLEN/8, x10, x1, x4) + +inst_1297: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x07a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x07a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x507a; op2val:0x387a; + valaddr_reg:x8; val_offset:2544*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2544*FLEN/8, x10, x1, x4) + +inst_1298: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x07a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x07a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x507a; op2val:0x387a; + valaddr_reg:x8; val_offset:2546*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2546*FLEN/8, x10, x1, x4) + +inst_1299: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x07a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x07a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x507a; op2val:0x387a; + valaddr_reg:x8; val_offset:2548*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2548*FLEN/8, x10, x1, x4) + +inst_1300: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x11d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x11d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x511d; op2val:0x391d; + valaddr_reg:x8; val_offset:2550*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2550*FLEN/8, x10, x1, x4) + +inst_1301: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x11d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x11d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x511d; op2val:0x391d; + valaddr_reg:x8; val_offset:2552*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2552*FLEN/8, x10, x1, x4) + +inst_1302: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x11d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x11d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x511d; op2val:0x391d; + valaddr_reg:x8; val_offset:2554*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2554*FLEN/8, x10, x1, x4) + +inst_1303: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x11d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x11d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x511d; op2val:0x391d; + valaddr_reg:x8; val_offset:2556*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2556*FLEN/8, x10, x1, x4) + +inst_1304: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x11d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x11d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x511d; op2val:0x391d; + valaddr_reg:x8; val_offset:2558*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2558*FLEN/8, x10, x1, x4) + +inst_1305: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x188 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x188 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5188; op2val:0x3988; + valaddr_reg:x8; val_offset:2560*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2560*FLEN/8, x10, x1, x4) + +inst_1306: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x188 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x188 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5188; op2val:0x3988; + valaddr_reg:x8; val_offset:2562*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2562*FLEN/8, x10, x1, x4) + +inst_1307: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x188 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x188 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5188; op2val:0x3988; + valaddr_reg:x8; val_offset:2564*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2564*FLEN/8, x10, x1, x4) + +inst_1308: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x188 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x188 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5188; op2val:0x3988; + valaddr_reg:x8; val_offset:2566*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2566*FLEN/8, x10, x1, x4) + +inst_1309: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x188 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x188 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5188; op2val:0x3988; + valaddr_reg:x8; val_offset:2568*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2568*FLEN/8, x10, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_10) + +inst_1310: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2e6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2e5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x52e6; op2val:0x3ae5; + valaddr_reg:x8; val_offset:2570*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2570*FLEN/8, x10, x1, x4) + +inst_1311: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2e6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2e5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x52e6; op2val:0x3ae5; + valaddr_reg:x8; val_offset:2572*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2572*FLEN/8, x10, x1, x4) + +inst_1312: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2e6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2e5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x52e6; op2val:0x3ae5; + valaddr_reg:x8; val_offset:2574*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2574*FLEN/8, x10, x1, x4) + +inst_1313: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2e6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2e5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x52e6; op2val:0x3ae5; + valaddr_reg:x8; val_offset:2576*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2576*FLEN/8, x10, x1, x4) + +inst_1314: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2e6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2e5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x52e6; op2val:0x3ae5; + valaddr_reg:x8; val_offset:2578*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2578*FLEN/8, x10, x1, x4) + +inst_1315: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x0dc and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0dc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x50dc; op2val:0x38dc; + valaddr_reg:x8; val_offset:2580*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2580*FLEN/8, x10, x1, x4) + +inst_1316: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x0dc and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0dc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x50dc; op2val:0x38dc; + valaddr_reg:x8; val_offset:2582*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2582*FLEN/8, x10, x1, x4) + +inst_1317: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x0dc and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0dc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x50dc; op2val:0x38dc; + valaddr_reg:x8; val_offset:2584*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2584*FLEN/8, x10, x1, x4) + +inst_1318: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x0dc and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0dc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x50dc; op2val:0x38dc; + valaddr_reg:x8; val_offset:2586*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2586*FLEN/8, x10, x1, x4) + +inst_1319: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x0dc and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0dc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x50dc; op2val:0x38dc; + valaddr_reg:x8; val_offset:2588*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2588*FLEN/8, x10, x1, x4) + +inst_1320: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x099 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x098 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c99; op2val:0x2498; + valaddr_reg:x8; val_offset:2590*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2590*FLEN/8, x10, x1, x4) + +inst_1321: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x099 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x098 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c99; op2val:0x2498; + valaddr_reg:x8; val_offset:2592*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2592*FLEN/8, x10, x1, x4) + +inst_1322: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x099 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x098 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c99; op2val:0x2498; + valaddr_reg:x8; val_offset:2594*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2594*FLEN/8, x10, x1, x4) + +inst_1323: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x099 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x098 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c99; op2val:0x2498; + valaddr_reg:x8; val_offset:2596*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2596*FLEN/8, x10, x1, x4) + +inst_1324: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x099 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x098 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c99; op2val:0x2498; + valaddr_reg:x8; val_offset:2598*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2598*FLEN/8, x10, x1, x4) + +inst_1325: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x156 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x156 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5156; op2val:0x3956; + valaddr_reg:x8; val_offset:2600*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2600*FLEN/8, x10, x1, x4) + +inst_1326: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x156 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x156 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5156; op2val:0x3956; + valaddr_reg:x8; val_offset:2602*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2602*FLEN/8, x10, x1, x4) + +inst_1327: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x156 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x156 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5156; op2val:0x3956; + valaddr_reg:x8; val_offset:2604*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2604*FLEN/8, x10, x1, x4) + +inst_1328: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x156 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x156 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5156; op2val:0x3956; + valaddr_reg:x8; val_offset:2606*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2606*FLEN/8, x10, x1, x4) + +inst_1329: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x156 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x156 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5156; op2val:0x3956; + valaddr_reg:x8; val_offset:2608*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2608*FLEN/8, x10, x1, x4) + +inst_1330: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x503f; op2val:0x383f; + valaddr_reg:x8; val_offset:2610*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2610*FLEN/8, x10, x1, x4) + +inst_1331: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x03f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x503f; op2val:0x383f; + valaddr_reg:x8; val_offset:2612*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2612*FLEN/8, x10, x1, x4) + +inst_1332: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x03f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x503f; op2val:0x383f; + valaddr_reg:x8; val_offset:2614*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2614*FLEN/8, x10, x1, x4) + +inst_1333: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x03f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x503f; op2val:0x383f; + valaddr_reg:x8; val_offset:2616*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2616*FLEN/8, x10, x1, x4) + +inst_1334: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x03f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x503f; op2val:0x383f; + valaddr_reg:x8; val_offset:2618*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2618*FLEN/8, x10, x1, x4) + +inst_1335: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x297 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x297 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4a97; op2val:0x3297; + valaddr_reg:x8; val_offset:2620*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2620*FLEN/8, x10, x1, x4) + +inst_1336: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x297 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x297 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4a97; op2val:0x3297; + valaddr_reg:x8; val_offset:2622*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2622*FLEN/8, x10, x1, x4) + +inst_1337: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x297 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x297 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4a97; op2val:0x3297; + valaddr_reg:x8; val_offset:2624*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2624*FLEN/8, x10, x1, x4) + +inst_1338: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x297 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x297 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4a97; op2val:0x3297; + valaddr_reg:x8; val_offset:2626*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2626*FLEN/8, x10, x1, x4) + +inst_1339: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x297 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x297 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4a97; op2val:0x3297; + valaddr_reg:x8; val_offset:2628*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2628*FLEN/8, x10, x1, x4) + +inst_1340: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x2ab and fs2 == 0 and fe2 == 0x0a and fm2 == 0x2ab and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x42ab; op2val:0x2aab; + valaddr_reg:x8; val_offset:2630*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2630*FLEN/8, x10, x1, x4) + +inst_1341: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x2ab and fs2 == 0 and fe2 == 0x0a and fm2 == 0x2ab and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x42ab; op2val:0x2aab; + valaddr_reg:x8; val_offset:2632*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2632*FLEN/8, x10, x1, x4) + +inst_1342: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x2ab and fs2 == 0 and fe2 == 0x0a and fm2 == 0x2ab and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x42ab; op2val:0x2aab; + valaddr_reg:x8; val_offset:2634*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2634*FLEN/8, x10, x1, x4) + +inst_1343: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x2ab and fs2 == 0 and fe2 == 0x0a and fm2 == 0x2ab and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x42ab; op2val:0x2aab; + valaddr_reg:x8; val_offset:2636*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2636*FLEN/8, x10, x1, x4) + +inst_1344: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x2ab and fs2 == 0 and fe2 == 0x0a and fm2 == 0x2ab and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x42ab; op2val:0x2aab; + valaddr_reg:x8; val_offset:2638*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2638*FLEN/8, x10, x1, x4) + +inst_1345: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x136 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x136 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5136; op2val:0x3936; + valaddr_reg:x8; val_offset:2640*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2640*FLEN/8, x10, x1, x4) + +inst_1346: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x136 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x136 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5136; op2val:0x3936; + valaddr_reg:x8; val_offset:2642*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2642*FLEN/8, x10, x1, x4) + +inst_1347: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x136 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x136 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5136; op2val:0x3936; + valaddr_reg:x8; val_offset:2644*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2644*FLEN/8, x10, x1, x4) + +inst_1348: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x136 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x136 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5136; op2val:0x3936; + valaddr_reg:x8; val_offset:2646*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2646*FLEN/8, x10, x1, x4) + +inst_1349: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x136 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x136 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5136; op2val:0x3936; + valaddr_reg:x8; val_offset:2648*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2648*FLEN/8, x10, x1, x4) + +inst_1350: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x095 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x095 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5095; op2val:0x3895; + valaddr_reg:x8; val_offset:2650*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2650*FLEN/8, x10, x1, x4) + +inst_1351: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x095 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x095 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5095; op2val:0x3895; + valaddr_reg:x8; val_offset:2652*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2652*FLEN/8, x10, x1, x4) + +inst_1352: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x095 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x095 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5095; op2val:0x3895; + valaddr_reg:x8; val_offset:2654*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2654*FLEN/8, x10, x1, x4) + +inst_1353: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x095 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x095 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5095; op2val:0x3895; + valaddr_reg:x8; val_offset:2656*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2656*FLEN/8, x10, x1, x4) + +inst_1354: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x095 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x095 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5095; op2val:0x3895; + valaddr_reg:x8; val_offset:2658*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2658*FLEN/8, x10, x1, x4) + +inst_1355: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x326 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x326 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5326; op2val:0x3b26; + valaddr_reg:x8; val_offset:2660*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2660*FLEN/8, x10, x1, x4) + +inst_1356: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x326 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x326 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5326; op2val:0x3b26; + valaddr_reg:x8; val_offset:2662*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2662*FLEN/8, x10, x1, x4) + +inst_1357: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x326 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x326 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5326; op2val:0x3b26; + valaddr_reg:x8; val_offset:2664*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2664*FLEN/8, x10, x1, x4) + +inst_1358: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x326 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x326 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5326; op2val:0x3b26; + valaddr_reg:x8; val_offset:2666*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2666*FLEN/8, x10, x1, x4) + +inst_1359: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x326 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x326 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5326; op2val:0x3b26; + valaddr_reg:x8; val_offset:2668*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2668*FLEN/8, x10, x1, x4) + +inst_1360: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x25d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x25d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x525d; op2val:0x3a5d; + valaddr_reg:x8; val_offset:2670*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2670*FLEN/8, x10, x1, x4) + +inst_1361: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x25d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x25d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x525d; op2val:0x3a5d; + valaddr_reg:x8; val_offset:2672*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2672*FLEN/8, x10, x1, x4) + +inst_1362: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x25d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x25d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x525d; op2val:0x3a5d; + valaddr_reg:x8; val_offset:2674*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2674*FLEN/8, x10, x1, x4) + +inst_1363: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x25d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x25d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x525d; op2val:0x3a5d; + valaddr_reg:x8; val_offset:2676*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2676*FLEN/8, x10, x1, x4) + +inst_1364: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x25d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x25d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x525d; op2val:0x3a5d; + valaddr_reg:x8; val_offset:2678*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2678*FLEN/8, x10, x1, x4) + +inst_1365: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x030 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x030 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4430; op2val:0x2c30; + valaddr_reg:x8; val_offset:2680*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2680*FLEN/8, x10, x1, x4) + +inst_1366: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x030 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x030 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4430; op2val:0x2c30; + valaddr_reg:x8; val_offset:2682*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2682*FLEN/8, x10, x1, x4) + +inst_1367: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x030 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x030 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4430; op2val:0x2c30; + valaddr_reg:x8; val_offset:2684*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2684*FLEN/8, x10, x1, x4) + +inst_1368: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x030 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x030 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4430; op2val:0x2c30; + valaddr_reg:x8; val_offset:2686*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2686*FLEN/8, x10, x1, x4) + +inst_1369: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x030 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x030 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4430; op2val:0x2c30; + valaddr_reg:x8; val_offset:2688*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2688*FLEN/8, x10, x1, x4) + +inst_1370: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x3da and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3da and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4bda; op2val:0x33da; + valaddr_reg:x8; val_offset:2690*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2690*FLEN/8, x10, x1, x4) + +inst_1371: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x3da and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3da and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4bda; op2val:0x33da; + valaddr_reg:x8; val_offset:2692*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2692*FLEN/8, x10, x1, x4) + +inst_1372: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x3da and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3da and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4bda; op2val:0x33da; + valaddr_reg:x8; val_offset:2694*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2694*FLEN/8, x10, x1, x4) + +inst_1373: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x3da and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3da and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4bda; op2val:0x33da; + valaddr_reg:x8; val_offset:2696*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2696*FLEN/8, x10, x1, x4) + +inst_1374: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x3da and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3da and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4bda; op2val:0x33da; + valaddr_reg:x8; val_offset:2698*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2698*FLEN/8, x10, x1, x4) + +inst_1375: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x05e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x05e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x505e; op2val:0x385e; + valaddr_reg:x8; val_offset:2700*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2700*FLEN/8, x10, x1, x4) + +inst_1376: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x05e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x05e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x505e; op2val:0x385e; + valaddr_reg:x8; val_offset:2702*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2702*FLEN/8, x10, x1, x4) + +inst_1377: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x05e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x05e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x505e; op2val:0x385e; + valaddr_reg:x8; val_offset:2704*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2704*FLEN/8, x10, x1, x4) + +inst_1378: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x05e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x05e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x505e; op2val:0x385e; + valaddr_reg:x8; val_offset:2706*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2706*FLEN/8, x10, x1, x4) + +inst_1379: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x05e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x05e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x505e; op2val:0x385e; + valaddr_reg:x8; val_offset:2708*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2708*FLEN/8, x10, x1, x4) + +inst_1380: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x157 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x156 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4d57; op2val:0x3556; + valaddr_reg:x8; val_offset:2710*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2710*FLEN/8, x10, x1, x4) + +inst_1381: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x157 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x156 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4d57; op2val:0x3556; + valaddr_reg:x8; val_offset:2712*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2712*FLEN/8, x10, x1, x4) + +inst_1382: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x157 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x156 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4d57; op2val:0x3556; + valaddr_reg:x8; val_offset:2714*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2714*FLEN/8, x10, x1, x4) + +inst_1383: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x157 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x156 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4d57; op2val:0x3556; + valaddr_reg:x8; val_offset:2716*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2716*FLEN/8, x10, x1, x4) + +inst_1384: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x157 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x156 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4d57; op2val:0x3556; + valaddr_reg:x8; val_offset:2718*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2718*FLEN/8, x10, x1, x4) + +inst_1385: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x198 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x198 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5198; op2val:0x3998; + valaddr_reg:x8; val_offset:2720*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2720*FLEN/8, x10, x1, x4) + +inst_1386: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x198 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x198 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5198; op2val:0x3998; + valaddr_reg:x8; val_offset:2722*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2722*FLEN/8, x10, x1, x4) + +inst_1387: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x198 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x198 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5198; op2val:0x3998; + valaddr_reg:x8; val_offset:2724*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2724*FLEN/8, x10, x1, x4) + +inst_1388: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x198 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x198 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5198; op2val:0x3998; + valaddr_reg:x8; val_offset:2726*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2726*FLEN/8, x10, x1, x4) + +inst_1389: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x198 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x198 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5198; op2val:0x3998; + valaddr_reg:x8; val_offset:2728*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2728*FLEN/8, x10, x1, x4) + +inst_1390: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2e2 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2e2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x52e2; op2val:0x3ae2; + valaddr_reg:x8; val_offset:2730*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2730*FLEN/8, x10, x1, x4) + +inst_1391: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2e2 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2e2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x52e2; op2val:0x3ae2; + valaddr_reg:x8; val_offset:2732*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2732*FLEN/8, x10, x1, x4) + +inst_1392: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2e2 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2e2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x52e2; op2val:0x3ae2; + valaddr_reg:x8; val_offset:2734*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2734*FLEN/8, x10, x1, x4) + +inst_1393: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2e2 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2e2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x52e2; op2val:0x3ae2; + valaddr_reg:x8; val_offset:2736*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2736*FLEN/8, x10, x1, x4) + +inst_1394: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2e2 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2e2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x52e2; op2val:0x3ae2; + valaddr_reg:x8; val_offset:2738*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2738*FLEN/8, x10, x1, x4) + +inst_1395: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x36c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x36c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x536c; op2val:0x3b6c; + valaddr_reg:x8; val_offset:2740*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2740*FLEN/8, x10, x1, x4) + +inst_1396: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x36c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x36c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x536c; op2val:0x3b6c; + valaddr_reg:x8; val_offset:2742*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2742*FLEN/8, x10, x1, x4) + +inst_1397: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x36c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x36c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x536c; op2val:0x3b6c; + valaddr_reg:x8; val_offset:2744*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2744*FLEN/8, x10, x1, x4) + +inst_1398: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x36c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x36c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x536c; op2val:0x3b6c; + valaddr_reg:x8; val_offset:2746*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2746*FLEN/8, x10, x1, x4) + +inst_1399: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x36c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x36c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x536c; op2val:0x3b6c; + valaddr_reg:x8; val_offset:2748*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2748*FLEN/8, x10, x1, x4) + +inst_1400: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1f3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1f3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x51f3; op2val:0x39f3; + valaddr_reg:x8; val_offset:2750*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2750*FLEN/8, x10, x1, x4) + +inst_1401: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1f3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1f3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x51f3; op2val:0x39f3; + valaddr_reg:x8; val_offset:2752*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2752*FLEN/8, x10, x1, x4) + +inst_1402: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1f3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1f3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x51f3; op2val:0x39f3; + valaddr_reg:x8; val_offset:2754*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2754*FLEN/8, x10, x1, x4) + +inst_1403: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1f3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1f3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x51f3; op2val:0x39f3; + valaddr_reg:x8; val_offset:2756*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2756*FLEN/8, x10, x1, x4) + +inst_1404: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1f3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1f3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x51f3; op2val:0x39f3; + valaddr_reg:x8; val_offset:2758*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2758*FLEN/8, x10, x1, x4) + +inst_1405: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x27a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x27a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x527a; op2val:0x3a7a; + valaddr_reg:x8; val_offset:2760*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2760*FLEN/8, x10, x1, x4) + +inst_1406: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x27a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x27a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x527a; op2val:0x3a7a; + valaddr_reg:x8; val_offset:2762*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2762*FLEN/8, x10, x1, x4) + +inst_1407: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x27a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x27a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x527a; op2val:0x3a7a; + valaddr_reg:x8; val_offset:2764*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2764*FLEN/8, x10, x1, x4) + +inst_1408: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x27a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x27a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x527a; op2val:0x3a7a; + valaddr_reg:x8; val_offset:2766*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2766*FLEN/8, x10, x1, x4) + +inst_1409: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x27a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x27a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x527a; op2val:0x3a7a; + valaddr_reg:x8; val_offset:2768*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2768*FLEN/8, x10, x1, x4) + +inst_1410: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2e8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2e8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x52e8; op2val:0x3ae8; + valaddr_reg:x8; val_offset:2770*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2770*FLEN/8, x10, x1, x4) + +inst_1411: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2e8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2e8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x52e8; op2val:0x3ae8; + valaddr_reg:x8; val_offset:2772*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2772*FLEN/8, x10, x1, x4) + +inst_1412: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2e8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2e8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x52e8; op2val:0x3ae8; + valaddr_reg:x8; val_offset:2774*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2774*FLEN/8, x10, x1, x4) + +inst_1413: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2e8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2e8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x52e8; op2val:0x3ae8; + valaddr_reg:x8; val_offset:2776*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2776*FLEN/8, x10, x1, x4) + +inst_1414: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2e8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2e8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x52e8; op2val:0x3ae8; + valaddr_reg:x8; val_offset:2778*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2778*FLEN/8, x10, x1, x4) + +inst_1415: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x215 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x215 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5215; op2val:0x3a15; + valaddr_reg:x8; val_offset:2780*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2780*FLEN/8, x10, x1, x4) + +inst_1416: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x215 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x215 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5215; op2val:0x3a15; + valaddr_reg:x8; val_offset:2782*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2782*FLEN/8, x10, x1, x4) + +inst_1417: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x215 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x215 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5215; op2val:0x3a15; + valaddr_reg:x8; val_offset:2784*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2784*FLEN/8, x10, x1, x4) + +inst_1418: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x215 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x215 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5215; op2val:0x3a15; + valaddr_reg:x8; val_offset:2786*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2786*FLEN/8, x10, x1, x4) + +inst_1419: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x215 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x215 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5215; op2val:0x3a15; + valaddr_reg:x8; val_offset:2788*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2788*FLEN/8, x10, x1, x4) + +inst_1420: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3df and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x47e0; op2val:0x2fdf; + valaddr_reg:x8; val_offset:2790*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2790*FLEN/8, x10, x1, x4) + +inst_1421: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3df and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x47e0; op2val:0x2fdf; + valaddr_reg:x8; val_offset:2792*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2792*FLEN/8, x10, x1, x4) + +inst_1422: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3df and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x47e0; op2val:0x2fdf; + valaddr_reg:x8; val_offset:2794*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2794*FLEN/8, x10, x1, x4) + +inst_1423: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3df and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x47e0; op2val:0x2fdf; + valaddr_reg:x8; val_offset:2796*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2796*FLEN/8, x10, x1, x4) + +inst_1424: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3df and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x47e0; op2val:0x2fdf; + valaddr_reg:x8; val_offset:2798*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2798*FLEN/8, x10, x1, x4) + +inst_1425: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x1e9 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x1e9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x45e9; op2val:0x2de9; + valaddr_reg:x8; val_offset:2800*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2800*FLEN/8, x10, x1, x4) + +inst_1426: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x1e9 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x1e9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x45e9; op2val:0x2de9; + valaddr_reg:x8; val_offset:2802*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2802*FLEN/8, x10, x1, x4) + +inst_1427: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x1e9 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x1e9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x45e9; op2val:0x2de9; + valaddr_reg:x8; val_offset:2804*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2804*FLEN/8, x10, x1, x4) + +inst_1428: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x1e9 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x1e9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x45e9; op2val:0x2de9; + valaddr_reg:x8; val_offset:2806*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2806*FLEN/8, x10, x1, x4) + +inst_1429: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x1e9 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x1e9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x45e9; op2val:0x2de9; + valaddr_reg:x8; val_offset:2808*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2808*FLEN/8, x10, x1, x4) + +inst_1430: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x191 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x190 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4991; op2val:0x3190; + valaddr_reg:x8; val_offset:2810*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2810*FLEN/8, x10, x1, x4) + +inst_1431: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x191 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x190 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4991; op2val:0x3190; + valaddr_reg:x8; val_offset:2812*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2812*FLEN/8, x10, x1, x4) + +inst_1432: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x191 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x190 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4991; op2val:0x3190; + valaddr_reg:x8; val_offset:2814*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2814*FLEN/8, x10, x1, x4) + +inst_1433: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x191 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x190 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4991; op2val:0x3190; + valaddr_reg:x8; val_offset:2816*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2816*FLEN/8, x10, x1, x4) + +inst_1434: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x191 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x190 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4991; op2val:0x3190; + valaddr_reg:x8; val_offset:2818*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2818*FLEN/8, x10, x1, x4) + +inst_1435: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1a1 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1a1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x51a1; op2val:0x39a1; + valaddr_reg:x8; val_offset:2820*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2820*FLEN/8, x10, x1, x4) + +inst_1436: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1a1 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1a1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x51a1; op2val:0x39a1; + valaddr_reg:x8; val_offset:2822*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2822*FLEN/8, x10, x1, x4) + +inst_1437: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1a1 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1a1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x51a1; op2val:0x39a1; + valaddr_reg:x8; val_offset:2824*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2824*FLEN/8, x10, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_11) + +inst_1438: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1a1 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1a1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x51a1; op2val:0x39a1; + valaddr_reg:x8; val_offset:2826*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2826*FLEN/8, x10, x1, x4) + +inst_1439: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1a1 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1a1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x51a1; op2val:0x39a1; + valaddr_reg:x8; val_offset:2828*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2828*FLEN/8, x10, x1, x4) + +inst_1440: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x2e6 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2e5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4ee6; op2val:0x36e5; + valaddr_reg:x8; val_offset:2830*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2830*FLEN/8, x10, x1, x4) + +inst_1441: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x2e6 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2e5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4ee6; op2val:0x36e5; + valaddr_reg:x8; val_offset:2832*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2832*FLEN/8, x10, x1, x4) + +inst_1442: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x2e6 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2e5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4ee6; op2val:0x36e5; + valaddr_reg:x8; val_offset:2834*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2834*FLEN/8, x10, x1, x4) + +inst_1443: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x2e6 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2e5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4ee6; op2val:0x36e5; + valaddr_reg:x8; val_offset:2836*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2836*FLEN/8, x10, x1, x4) + +inst_1444: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x2e6 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2e5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4ee6; op2val:0x36e5; + valaddr_reg:x8; val_offset:2838*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2838*FLEN/8, x10, x1, x4) + +inst_1445: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x10c and fs2 == 0 and fe2 == 0x0d and fm2 == 0x10c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4d0c; op2val:0x350c; + valaddr_reg:x8; val_offset:2840*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2840*FLEN/8, x10, x1, x4) + +inst_1446: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x10c and fs2 == 0 and fe2 == 0x0d and fm2 == 0x10c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4d0c; op2val:0x350c; + valaddr_reg:x8; val_offset:2842*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2842*FLEN/8, x10, x1, x4) + +inst_1447: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x10c and fs2 == 0 and fe2 == 0x0d and fm2 == 0x10c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4d0c; op2val:0x350c; + valaddr_reg:x8; val_offset:2844*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2844*FLEN/8, x10, x1, x4) + +inst_1448: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x10c and fs2 == 0 and fe2 == 0x0d and fm2 == 0x10c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4d0c; op2val:0x350c; + valaddr_reg:x8; val_offset:2846*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2846*FLEN/8, x10, x1, x4) + +inst_1449: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x10c and fs2 == 0 and fe2 == 0x0d and fm2 == 0x10c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4d0c; op2val:0x350c; + valaddr_reg:x8; val_offset:2848*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2848*FLEN/8, x10, x1, x4) + +inst_1450: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x216 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x216 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5216; op2val:0x3a16; + valaddr_reg:x8; val_offset:2850*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2850*FLEN/8, x10, x1, x4) + +inst_1451: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x216 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x216 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5216; op2val:0x3a16; + valaddr_reg:x8; val_offset:2852*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2852*FLEN/8, x10, x1, x4) + +inst_1452: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x216 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x216 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5216; op2val:0x3a16; + valaddr_reg:x8; val_offset:2854*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2854*FLEN/8, x10, x1, x4) + +inst_1453: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x216 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x216 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5216; op2val:0x3a16; + valaddr_reg:x8; val_offset:2856*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2856*FLEN/8, x10, x1, x4) + +inst_1454: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x216 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x216 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5216; op2val:0x3a16; + valaddr_reg:x8; val_offset:2858*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2858*FLEN/8, x10, x1, x4) + +inst_1455: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x230 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x230 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4a30; op2val:0x3230; + valaddr_reg:x8; val_offset:2860*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2860*FLEN/8, x10, x1, x4) + +inst_1456: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x230 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x230 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4a30; op2val:0x3230; + valaddr_reg:x8; val_offset:2862*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2862*FLEN/8, x10, x1, x4) + +inst_1457: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x230 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x230 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4a30; op2val:0x3230; + valaddr_reg:x8; val_offset:2864*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2864*FLEN/8, x10, x1, x4) + +inst_1458: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x230 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x230 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4a30; op2val:0x3230; + valaddr_reg:x8; val_offset:2866*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2866*FLEN/8, x10, x1, x4) + +inst_1459: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x230 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x230 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4a30; op2val:0x3230; + valaddr_reg:x8; val_offset:2868*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2868*FLEN/8, x10, x1, x4) + +inst_1460: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1cb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1ca and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x51cb; op2val:0x39ca; + valaddr_reg:x8; val_offset:2870*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2870*FLEN/8, x10, x1, x4) + +inst_1461: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1cb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1ca and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x51cb; op2val:0x39ca; + valaddr_reg:x8; val_offset:2872*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2872*FLEN/8, x10, x1, x4) + +inst_1462: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1cb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1ca and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x51cb; op2val:0x39ca; + valaddr_reg:x8; val_offset:2874*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2874*FLEN/8, x10, x1, x4) + +inst_1463: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1cb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1ca and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x51cb; op2val:0x39ca; + valaddr_reg:x8; val_offset:2876*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2876*FLEN/8, x10, x1, x4) + +inst_1464: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1cb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1ca and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x51cb; op2val:0x39ca; + valaddr_reg:x8; val_offset:2878*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2878*FLEN/8, x10, x1, x4) + +inst_1465: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11f and fs2 == 0 and fe2 == 0x13 and fm2 == 0x11f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x391f; op2val:0x4d1f; + valaddr_reg:x8; val_offset:2880*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2880*FLEN/8, x10, x1, x4) + +inst_1466: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11f and fs2 == 0 and fe2 == 0x13 and fm2 == 0x11f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x391f; op2val:0x4d1f; + valaddr_reg:x8; val_offset:2882*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2882*FLEN/8, x10, x1, x4) + +inst_1467: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11f and fs2 == 0 and fe2 == 0x13 and fm2 == 0x11f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x391f; op2val:0x4d1f; + valaddr_reg:x8; val_offset:2884*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2884*FLEN/8, x10, x1, x4) + +inst_1468: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11f and fs2 == 0 and fe2 == 0x13 and fm2 == 0x11f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x391f; op2val:0x4d1f; + valaddr_reg:x8; val_offset:2886*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2886*FLEN/8, x10, x1, x4) + +inst_1469: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11f and fs2 == 0 and fe2 == 0x13 and fm2 == 0x11f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x391f; op2val:0x4d1f; + valaddr_reg:x8; val_offset:2888*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2888*FLEN/8, x10, x1, x4) + +inst_1470: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2c1 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x2c1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x36c1; op2val:0x4ac1; + valaddr_reg:x8; val_offset:2890*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2890*FLEN/8, x10, x1, x4) + +inst_1471: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2c1 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x2c1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x36c1; op2val:0x4ac1; + valaddr_reg:x8; val_offset:2892*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2892*FLEN/8, x10, x1, x4) + +inst_1472: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2c1 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x2c1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x36c1; op2val:0x4ac1; + valaddr_reg:x8; val_offset:2894*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2894*FLEN/8, x10, x1, x4) + +inst_1473: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2c1 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x2c1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x36c1; op2val:0x4ac1; + valaddr_reg:x8; val_offset:2896*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2896*FLEN/8, x10, x1, x4) + +inst_1474: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2c1 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x2c1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x36c1; op2val:0x4ac1; + valaddr_reg:x8; val_offset:2898*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2898*FLEN/8, x10, x1, x4) + +inst_1475: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3fa and fs2 == 0 and fe2 == 0x13 and fm2 == 0x3fa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bfa; op2val:0x4ffa; + valaddr_reg:x8; val_offset:2900*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2900*FLEN/8, x10, x1, x4) + +inst_1476: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3fa and fs2 == 0 and fe2 == 0x13 and fm2 == 0x3fa and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bfa; op2val:0x4ffa; + valaddr_reg:x8; val_offset:2902*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2902*FLEN/8, x10, x1, x4) + +inst_1477: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3fa and fs2 == 0 and fe2 == 0x13 and fm2 == 0x3fa and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bfa; op2val:0x4ffa; + valaddr_reg:x8; val_offset:2904*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2904*FLEN/8, x10, x1, x4) + +inst_1478: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3fa and fs2 == 0 and fe2 == 0x13 and fm2 == 0x3fa and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bfa; op2val:0x4ffa; + valaddr_reg:x8; val_offset:2906*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2906*FLEN/8, x10, x1, x4) + +inst_1479: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3fa and fs2 == 0 and fe2 == 0x13 and fm2 == 0x3fa and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bfa; op2val:0x4ffa; + valaddr_reg:x8; val_offset:2908*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2908*FLEN/8, x10, x1, x4) + +inst_1480: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3b8 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3b8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x33b8; op2val:0x47b8; + valaddr_reg:x8; val_offset:2910*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2910*FLEN/8, x10, x1, x4) + +inst_1481: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3b8 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3b8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x33b8; op2val:0x47b8; + valaddr_reg:x8; val_offset:2912*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2912*FLEN/8, x10, x1, x4) + +inst_1482: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3b8 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3b8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x33b8; op2val:0x47b8; + valaddr_reg:x8; val_offset:2914*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2914*FLEN/8, x10, x1, x4) + +inst_1483: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3b8 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3b8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x33b8; op2val:0x47b8; + valaddr_reg:x8; val_offset:2916*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2916*FLEN/8, x10, x1, x4) + +inst_1484: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3b8 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3b8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x33b8; op2val:0x47b8; + valaddr_reg:x8; val_offset:2918*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2918*FLEN/8, x10, x1, x4) + +inst_1485: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x06f and fs2 == 0 and fe2 == 0x13 and fm2 == 0x06f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x386f; op2val:0x4c6f; + valaddr_reg:x8; val_offset:2920*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2920*FLEN/8, x10, x1, x4) + +inst_1486: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x06f and fs2 == 0 and fe2 == 0x13 and fm2 == 0x06f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x386f; op2val:0x4c6f; + valaddr_reg:x8; val_offset:2922*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2922*FLEN/8, x10, x1, x4) + +inst_1487: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x06f and fs2 == 0 and fe2 == 0x13 and fm2 == 0x06f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x386f; op2val:0x4c6f; + valaddr_reg:x8; val_offset:2924*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2924*FLEN/8, x10, x1, x4) + +inst_1488: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x06f and fs2 == 0 and fe2 == 0x13 and fm2 == 0x06f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x386f; op2val:0x4c6f; + valaddr_reg:x8; val_offset:2926*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2926*FLEN/8, x10, x1, x4) + +inst_1489: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x06f and fs2 == 0 and fe2 == 0x13 and fm2 == 0x06f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x386f; op2val:0x4c6f; + valaddr_reg:x8; val_offset:2928*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2928*FLEN/8, x10, x1, x4) + +inst_1490: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x260 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x260 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a60; op2val:0x4e60; + valaddr_reg:x8; val_offset:2930*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2930*FLEN/8, x10, x1, x4) + +inst_1491: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x260 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x260 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a60; op2val:0x4e60; + valaddr_reg:x8; val_offset:2932*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2932*FLEN/8, x10, x1, x4) + +inst_1492: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x260 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x260 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a60; op2val:0x4e60; + valaddr_reg:x8; val_offset:2934*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2934*FLEN/8, x10, x1, x4) + +inst_1493: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x260 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x260 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a60; op2val:0x4e60; + valaddr_reg:x8; val_offset:2936*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2936*FLEN/8, x10, x1, x4) + +inst_1494: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x260 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x260 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a60; op2val:0x4e60; + valaddr_reg:x8; val_offset:2938*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2938*FLEN/8, x10, x1, x4) + +inst_1495: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0de and fs2 == 0 and fe2 == 0x13 and fm2 == 0x0de and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x38de; op2val:0x4cde; + valaddr_reg:x8; val_offset:2940*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2940*FLEN/8, x10, x1, x4) + +inst_1496: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0de and fs2 == 0 and fe2 == 0x13 and fm2 == 0x0de and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x38de; op2val:0x4cde; + valaddr_reg:x8; val_offset:2942*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2942*FLEN/8, x10, x1, x4) + +inst_1497: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0de and fs2 == 0 and fe2 == 0x13 and fm2 == 0x0de and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x38de; op2val:0x4cde; + valaddr_reg:x8; val_offset:2944*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2944*FLEN/8, x10, x1, x4) + +inst_1498: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0de and fs2 == 0 and fe2 == 0x13 and fm2 == 0x0de and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x38de; op2val:0x4cde; + valaddr_reg:x8; val_offset:2946*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2946*FLEN/8, x10, x1, x4) + +inst_1499: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0de and fs2 == 0 and fe2 == 0x13 and fm2 == 0x0de and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x38de; op2val:0x4cde; + valaddr_reg:x8; val_offset:2948*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2948*FLEN/8, x10, x1, x4) + +inst_1500: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c9 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x3c9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bc9; op2val:0x4fc9; + valaddr_reg:x8; val_offset:2950*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2950*FLEN/8, x10, x1, x4) + +inst_1501: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c9 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x3c9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bc9; op2val:0x4fc9; + valaddr_reg:x8; val_offset:2952*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2952*FLEN/8, x10, x1, x4) + +inst_1502: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c9 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x3c9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bc9; op2val:0x4fc9; + valaddr_reg:x8; val_offset:2954*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2954*FLEN/8, x10, x1, x4) + +inst_1503: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c9 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x3c9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bc9; op2val:0x4fc9; + valaddr_reg:x8; val_offset:2956*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2956*FLEN/8, x10, x1, x4) + +inst_1504: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c9 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x3c9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bc9; op2val:0x4fc9; + valaddr_reg:x8; val_offset:2958*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2958*FLEN/8, x10, x1, x4) + +inst_1505: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b2 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x2b1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ab2; op2val:0x4eb1; + valaddr_reg:x8; val_offset:2960*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2960*FLEN/8, x10, x1, x4) + +inst_1506: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b2 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x2b1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ab2; op2val:0x4eb1; + valaddr_reg:x8; val_offset:2962*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2962*FLEN/8, x10, x1, x4) + +inst_1507: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b2 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x2b1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ab2; op2val:0x4eb1; + valaddr_reg:x8; val_offset:2964*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2964*FLEN/8, x10, x1, x4) + +inst_1508: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b2 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x2b1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ab2; op2val:0x4eb1; + valaddr_reg:x8; val_offset:2966*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2966*FLEN/8, x10, x1, x4) + +inst_1509: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b2 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x2b1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ab2; op2val:0x4eb1; + valaddr_reg:x8; val_offset:2968*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2968*FLEN/8, x10, x1, x4) + +inst_1510: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x389 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x389 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b89; op2val:0x4f89; + valaddr_reg:x8; val_offset:2970*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2970*FLEN/8, x10, x1, x4) + +inst_1511: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x389 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x389 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b89; op2val:0x4f89; + valaddr_reg:x8; val_offset:2972*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2972*FLEN/8, x10, x1, x4) + +inst_1512: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x389 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x389 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b89; op2val:0x4f89; + valaddr_reg:x8; val_offset:2974*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2974*FLEN/8, x10, x1, x4) + +inst_1513: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x389 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x389 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b89; op2val:0x4f89; + valaddr_reg:x8; val_offset:2976*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2976*FLEN/8, x10, x1, x4) + +inst_1514: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x389 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x389 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b89; op2val:0x4f89; + valaddr_reg:x8; val_offset:2978*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2978*FLEN/8, x10, x1, x4) + +inst_1515: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x087 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x086 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3887; op2val:0x4c86; + valaddr_reg:x8; val_offset:2980*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2980*FLEN/8, x10, x1, x4) + +inst_1516: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x087 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x086 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3887; op2val:0x4c86; + valaddr_reg:x8; val_offset:2982*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2982*FLEN/8, x10, x1, x4) + +inst_1517: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x087 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x086 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3887; op2val:0x4c86; + valaddr_reg:x8; val_offset:2984*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2984*FLEN/8, x10, x1, x4) + +inst_1518: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x087 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x086 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3887; op2val:0x4c86; + valaddr_reg:x8; val_offset:2986*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2986*FLEN/8, x10, x1, x4) + +inst_1519: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x087 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x086 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3887; op2val:0x4c86; + valaddr_reg:x8; val_offset:2988*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2988*FLEN/8, x10, x1, x4) + +inst_1520: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x118 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x118 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3518; op2val:0x4918; + valaddr_reg:x8; val_offset:2990*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 2990*FLEN/8, x10, x1, x4) + +inst_1521: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x118 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x118 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3518; op2val:0x4918; + valaddr_reg:x8; val_offset:2992*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 2992*FLEN/8, x10, x1, x4) + +inst_1522: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x118 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x118 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3518; op2val:0x4918; + valaddr_reg:x8; val_offset:2994*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 2994*FLEN/8, x10, x1, x4) + +inst_1523: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x118 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x118 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3518; op2val:0x4918; + valaddr_reg:x8; val_offset:2996*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 2996*FLEN/8, x10, x1, x4) + +inst_1524: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x118 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x118 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3518; op2val:0x4918; + valaddr_reg:x8; val_offset:2998*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 2998*FLEN/8, x10, x1, x4) + +inst_1525: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0df and fs2 == 0 and fe2 == 0x13 and fm2 == 0x0df and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x38df; op2val:0x4cdf; + valaddr_reg:x8; val_offset:3000*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 3000*FLEN/8, x10, x1, x4) + +inst_1526: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0df and fs2 == 0 and fe2 == 0x13 and fm2 == 0x0df and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x38df; op2val:0x4cdf; + valaddr_reg:x8; val_offset:3002*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 3002*FLEN/8, x10, x1, x4) + +inst_1527: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0df and fs2 == 0 and fe2 == 0x13 and fm2 == 0x0df and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x38df; op2val:0x4cdf; + valaddr_reg:x8; val_offset:3004*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 3004*FLEN/8, x10, x1, x4) + +inst_1528: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0df and fs2 == 0 and fe2 == 0x13 and fm2 == 0x0df and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x38df; op2val:0x4cdf; + valaddr_reg:x8; val_offset:3006*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 3006*FLEN/8, x10, x1, x4) + +inst_1529: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0df and fs2 == 0 and fe2 == 0x13 and fm2 == 0x0df and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x38df; op2val:0x4cdf; + valaddr_reg:x8; val_offset:3008*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 3008*FLEN/8, x10, x1, x4) + +inst_1530: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3cb and fs2 == 0 and fe2 == 0x13 and fm2 == 0x3ca and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bcb; op2val:0x4fca; + valaddr_reg:x8; val_offset:3010*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 3010*FLEN/8, x10, x1, x4) + +inst_1531: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3cb and fs2 == 0 and fe2 == 0x13 and fm2 == 0x3ca and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bcb; op2val:0x4fca; + valaddr_reg:x8; val_offset:3012*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 3012*FLEN/8, x10, x1, x4) + +inst_1532: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3cb and fs2 == 0 and fe2 == 0x13 and fm2 == 0x3ca and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bcb; op2val:0x4fca; + valaddr_reg:x8; val_offset:3014*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 3014*FLEN/8, x10, x1, x4) + +inst_1533: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3cb and fs2 == 0 and fe2 == 0x13 and fm2 == 0x3ca and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bcb; op2val:0x4fca; + valaddr_reg:x8; val_offset:3016*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 3016*FLEN/8, x10, x1, x4) + +inst_1534: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3cb and fs2 == 0 and fe2 == 0x13 and fm2 == 0x3ca and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bcb; op2val:0x4fca; + valaddr_reg:x8; val_offset:3018*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 3018*FLEN/8, x10, x1, x4) + +inst_1535: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x24d and fs2 == 0 and fe2 == 0x13 and fm2 == 0x24d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a4d; op2val:0x4e4d; + valaddr_reg:x8; val_offset:3020*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 3020*FLEN/8, x10, x1, x4) + +inst_1536: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x24d and fs2 == 0 and fe2 == 0x13 and fm2 == 0x24d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a4d; op2val:0x4e4d; + valaddr_reg:x8; val_offset:3022*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 3022*FLEN/8, x10, x1, x4) + +inst_1537: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x24d and fs2 == 0 and fe2 == 0x13 and fm2 == 0x24d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a4d; op2val:0x4e4d; + valaddr_reg:x8; val_offset:3024*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 3024*FLEN/8, x10, x1, x4) + +inst_1538: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x24d and fs2 == 0 and fe2 == 0x13 and fm2 == 0x24d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a4d; op2val:0x4e4d; + valaddr_reg:x8; val_offset:3026*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 3026*FLEN/8, x10, x1, x4) + +inst_1539: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x24d and fs2 == 0 and fe2 == 0x13 and fm2 == 0x24d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a4d; op2val:0x4e4d; + valaddr_reg:x8; val_offset:3028*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 3028*FLEN/8, x10, x1, x4) + +inst_1540: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x052 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x052 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3852; op2val:0x4c52; + valaddr_reg:x8; val_offset:3030*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 3030*FLEN/8, x10, x1, x4) + +inst_1541: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x052 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x052 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3852; op2val:0x4c52; + valaddr_reg:x8; val_offset:3032*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 3032*FLEN/8, x10, x1, x4) + +inst_1542: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x052 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x052 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3852; op2val:0x4c52; + valaddr_reg:x8; val_offset:3034*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 3034*FLEN/8, x10, x1, x4) + +inst_1543: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x052 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x052 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3852; op2val:0x4c52; + valaddr_reg:x8; val_offset:3036*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 3036*FLEN/8, x10, x1, x4) + +inst_1544: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x052 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x052 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3852; op2val:0x4c52; + valaddr_reg:x8; val_offset:3038*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 3038*FLEN/8, x10, x1, x4) + +inst_1545: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x25a and fs2 == 0 and fe2 == 0x12 and fm2 == 0x25a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x365a; op2val:0x4a5a; + valaddr_reg:x8; val_offset:3040*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 3040*FLEN/8, x10, x1, x4) + +inst_1546: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x25a and fs2 == 0 and fe2 == 0x12 and fm2 == 0x25a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x365a; op2val:0x4a5a; + valaddr_reg:x8; val_offset:3042*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 3042*FLEN/8, x10, x1, x4) + +inst_1547: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x25a and fs2 == 0 and fe2 == 0x12 and fm2 == 0x25a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x365a; op2val:0x4a5a; + valaddr_reg:x8; val_offset:3044*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 3044*FLEN/8, x10, x1, x4) + +inst_1548: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x25a and fs2 == 0 and fe2 == 0x12 and fm2 == 0x25a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x365a; op2val:0x4a5a; + valaddr_reg:x8; val_offset:3046*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 3046*FLEN/8, x10, x1, x4) + +inst_1549: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x25a and fs2 == 0 and fe2 == 0x12 and fm2 == 0x25a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x365a; op2val:0x4a5a; + valaddr_reg:x8; val_offset:3048*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 3048*FLEN/8, x10, x1, x4) + +inst_1550: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x30a and fs2 == 0 and fe2 == 0x13 and fm2 == 0x309 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b0a; op2val:0x4f09; + valaddr_reg:x8; val_offset:3050*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 3050*FLEN/8, x10, x1, x4) + +inst_1551: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x30a and fs2 == 0 and fe2 == 0x13 and fm2 == 0x309 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b0a; op2val:0x4f09; + valaddr_reg:x8; val_offset:3052*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 3052*FLEN/8, x10, x1, x4) + +inst_1552: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x30a and fs2 == 0 and fe2 == 0x13 and fm2 == 0x309 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b0a; op2val:0x4f09; + valaddr_reg:x8; val_offset:3054*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 3054*FLEN/8, x10, x1, x4) + +inst_1553: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x30a and fs2 == 0 and fe2 == 0x13 and fm2 == 0x309 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b0a; op2val:0x4f09; + valaddr_reg:x8; val_offset:3056*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 3056*FLEN/8, x10, x1, x4) + +inst_1554: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x30a and fs2 == 0 and fe2 == 0x13 and fm2 == 0x309 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b0a; op2val:0x4f09; + valaddr_reg:x8; val_offset:3058*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 3058*FLEN/8, x10, x1, x4) + +inst_1555: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0b8 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x0b8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x34b8; op2val:0x48b8; + valaddr_reg:x8; val_offset:3060*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 3060*FLEN/8, x10, x1, x4) + +inst_1556: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0b8 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x0b8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x34b8; op2val:0x48b8; + valaddr_reg:x8; val_offset:3062*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 3062*FLEN/8, x10, x1, x4) + +inst_1557: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0b8 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x0b8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x34b8; op2val:0x48b8; + valaddr_reg:x8; val_offset:3064*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 3064*FLEN/8, x10, x1, x4) + +inst_1558: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0b8 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x0b8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x34b8; op2val:0x48b8; + valaddr_reg:x8; val_offset:3066*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 3066*FLEN/8, x10, x1, x4) + +inst_1559: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0b8 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x0b8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x34b8; op2val:0x48b8; + valaddr_reg:x8; val_offset:3068*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 3068*FLEN/8, x10, x1, x4) + +inst_1560: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x393 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x393 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3393; op2val:0x4793; + valaddr_reg:x8; val_offset:3070*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 3070*FLEN/8, x10, x1, x4) + +inst_1561: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x393 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x393 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3393; op2val:0x4793; + valaddr_reg:x8; val_offset:3072*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 3072*FLEN/8, x10, x1, x4) + +inst_1562: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x393 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x393 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3393; op2val:0x4793; + valaddr_reg:x8; val_offset:3074*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 3074*FLEN/8, x10, x1, x4) + +inst_1563: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x393 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x393 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3393; op2val:0x4793; + valaddr_reg:x8; val_offset:3076*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 3076*FLEN/8, x10, x1, x4) + +inst_1564: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x393 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x393 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3393; op2val:0x4793; + valaddr_reg:x8; val_offset:3078*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 3078*FLEN/8, x10, x1, x4) + +inst_1565: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x228 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x228 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e28; op2val:0x4228; + valaddr_reg:x8; val_offset:3080*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 3080*FLEN/8, x10, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_12) + +inst_1566: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x228 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x228 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e28; op2val:0x4228; + valaddr_reg:x8; val_offset:3082*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 3082*FLEN/8, x10, x1, x4) + +inst_1567: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x228 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x228 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e28; op2val:0x4228; + valaddr_reg:x8; val_offset:3084*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 3084*FLEN/8, x10, x1, x4) + +inst_1568: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x228 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x228 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e28; op2val:0x4228; + valaddr_reg:x8; val_offset:3086*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 3086*FLEN/8, x10, x1, x4) + +inst_1569: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x228 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x228 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e28; op2val:0x4228; + valaddr_reg:x8; val_offset:3088*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 3088*FLEN/8, x10, x1, x4) + +inst_1570: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x210 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x20f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a10; op2val:0x4e0f; + valaddr_reg:x8; val_offset:3090*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 3090*FLEN/8, x10, x1, x4) + +inst_1571: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x210 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x20f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a10; op2val:0x4e0f; + valaddr_reg:x8; val_offset:3092*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 3092*FLEN/8, x10, x1, x4) + +inst_1572: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x210 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x20f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a10; op2val:0x4e0f; + valaddr_reg:x8; val_offset:3094*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 3094*FLEN/8, x10, x1, x4) + +inst_1573: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x210 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x20f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a10; op2val:0x4e0f; + valaddr_reg:x8; val_offset:3096*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 3096*FLEN/8, x10, x1, x4) + +inst_1574: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x210 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x20f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a10; op2val:0x4e0f; + valaddr_reg:x8; val_offset:3098*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 3098*FLEN/8, x10, x1, x4) + +inst_1575: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2be and fs2 == 0 and fe2 == 0x11 and fm2 == 0x2be and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x32be; op2val:0x46be; + valaddr_reg:x8; val_offset:3100*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 3100*FLEN/8, x10, x1, x4) + +inst_1576: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2be and fs2 == 0 and fe2 == 0x11 and fm2 == 0x2be and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x32be; op2val:0x46be; + valaddr_reg:x8; val_offset:3102*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 3102*FLEN/8, x10, x1, x4) + +inst_1577: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2be and fs2 == 0 and fe2 == 0x11 and fm2 == 0x2be and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x32be; op2val:0x46be; + valaddr_reg:x8; val_offset:3104*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 3104*FLEN/8, x10, x1, x4) + +inst_1578: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2be and fs2 == 0 and fe2 == 0x11 and fm2 == 0x2be and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x32be; op2val:0x46be; + valaddr_reg:x8; val_offset:3106*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 3106*FLEN/8, x10, x1, x4) + +inst_1579: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2be and fs2 == 0 and fe2 == 0x11 and fm2 == 0x2be and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x32be; op2val:0x46be; + valaddr_reg:x8; val_offset:3108*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 3108*FLEN/8, x10, x1, x4) + +inst_1580: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x154 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x153 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3954; op2val:0x4d53; + valaddr_reg:x8; val_offset:3110*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 3110*FLEN/8, x10, x1, x4) + +inst_1581: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x154 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x153 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3954; op2val:0x4d53; + valaddr_reg:x8; val_offset:3112*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 3112*FLEN/8, x10, x1, x4) + +inst_1582: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x154 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x153 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3954; op2val:0x4d53; + valaddr_reg:x8; val_offset:3114*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 3114*FLEN/8, x10, x1, x4) + +inst_1583: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x154 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x153 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3954; op2val:0x4d53; + valaddr_reg:x8; val_offset:3116*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 3116*FLEN/8, x10, x1, x4) + +inst_1584: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x154 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x153 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3954; op2val:0x4d53; + valaddr_reg:x8; val_offset:3118*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 3118*FLEN/8, x10, x1, x4) + +inst_1585: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x16c and fs2 == 0 and fe2 == 0x12 and fm2 == 0x16c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x356c; op2val:0x496c; + valaddr_reg:x8; val_offset:3120*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 3120*FLEN/8, x10, x1, x4) + +inst_1586: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x16c and fs2 == 0 and fe2 == 0x12 and fm2 == 0x16c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x356c; op2val:0x496c; + valaddr_reg:x8; val_offset:3122*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 3122*FLEN/8, x10, x1, x4) + +inst_1587: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x16c and fs2 == 0 and fe2 == 0x12 and fm2 == 0x16c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x356c; op2val:0x496c; + valaddr_reg:x8; val_offset:3124*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 3124*FLEN/8, x10, x1, x4) + +inst_1588: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x16c and fs2 == 0 and fe2 == 0x12 and fm2 == 0x16c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x356c; op2val:0x496c; + valaddr_reg:x8; val_offset:3126*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 3126*FLEN/8, x10, x1, x4) + +inst_1589: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x16c and fs2 == 0 and fe2 == 0x12 and fm2 == 0x16c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x356c; op2val:0x496c; + valaddr_reg:x8; val_offset:3128*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 3128*FLEN/8, x10, x1, x4) + +inst_1590: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2d1 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x2d1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x36d1; op2val:0x4ad1; + valaddr_reg:x8; val_offset:3130*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 3130*FLEN/8, x10, x1, x4) + +inst_1591: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2d1 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x2d1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x36d1; op2val:0x4ad1; + valaddr_reg:x8; val_offset:3132*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 3132*FLEN/8, x10, x1, x4) + +inst_1592: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2d1 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x2d1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x36d1; op2val:0x4ad1; + valaddr_reg:x8; val_offset:3134*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 3134*FLEN/8, x10, x1, x4) + +inst_1593: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2d1 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x2d1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x36d1; op2val:0x4ad1; + valaddr_reg:x8; val_offset:3136*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 3136*FLEN/8, x10, x1, x4) + +inst_1594: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2d1 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x2d1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x36d1; op2val:0x4ad1; + valaddr_reg:x8; val_offset:3138*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 3138*FLEN/8, x10, x1, x4) + +inst_1595: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c3 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x3c3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bc3; op2val:0x4fc3; + valaddr_reg:x8; val_offset:3140*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 3140*FLEN/8, x10, x1, x4) + +inst_1596: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c3 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x3c3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bc3; op2val:0x4fc3; + valaddr_reg:x8; val_offset:3142*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 3142*FLEN/8, x10, x1, x4) + +inst_1597: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c3 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x3c3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bc3; op2val:0x4fc3; + valaddr_reg:x8; val_offset:3144*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 3144*FLEN/8, x10, x1, x4) + +inst_1598: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c3 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x3c3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bc3; op2val:0x4fc3; + valaddr_reg:x8; val_offset:3146*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 3146*FLEN/8, x10, x1, x4) + +inst_1599: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c3 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x3c3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bc3; op2val:0x4fc3; + valaddr_reg:x8; val_offset:3148*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 3148*FLEN/8, x10, x1, x4) + +inst_1600: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x13 and fm2 == 0x2ad and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aae; op2val:0x4ead; + valaddr_reg:x8; val_offset:3150*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 3150*FLEN/8, x10, x1, x4) + +inst_1601: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x13 and fm2 == 0x2ad and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aae; op2val:0x4ead; + valaddr_reg:x8; val_offset:3152*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 3152*FLEN/8, x10, x1, x4) + +inst_1602: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x13 and fm2 == 0x2ad and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aae; op2val:0x4ead; + valaddr_reg:x8; val_offset:3154*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 3154*FLEN/8, x10, x1, x4) + +inst_1603: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x13 and fm2 == 0x2ad and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aae; op2val:0x4ead; + valaddr_reg:x8; val_offset:3156*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 3156*FLEN/8, x10, x1, x4) + +inst_1604: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x13 and fm2 == 0x2ad and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aae; op2val:0x4ead; + valaddr_reg:x8; val_offset:3158*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 3158*FLEN/8, x10, x1, x4) + +inst_1605: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x394 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x394 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b94; op2val:0x4f94; + valaddr_reg:x8; val_offset:3160*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 3160*FLEN/8, x10, x1, x4) + +inst_1606: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x394 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x394 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b94; op2val:0x4f94; + valaddr_reg:x8; val_offset:3162*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 3162*FLEN/8, x10, x1, x4) + +inst_1607: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x394 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x394 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b94; op2val:0x4f94; + valaddr_reg:x8; val_offset:3164*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 3164*FLEN/8, x10, x1, x4) + +inst_1608: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x394 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x394 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b94; op2val:0x4f94; + valaddr_reg:x8; val_offset:3166*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 3166*FLEN/8, x10, x1, x4) + +inst_1609: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x394 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x394 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b94; op2val:0x4f94; + valaddr_reg:x8; val_offset:3168*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 3168*FLEN/8, x10, x1, x4) + +inst_1610: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x017 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x017 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3017; op2val:0x4417; + valaddr_reg:x8; val_offset:3170*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 3170*FLEN/8, x10, x1, x4) + +inst_1611: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x017 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x017 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3017; op2val:0x4417; + valaddr_reg:x8; val_offset:3172*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 3172*FLEN/8, x10, x1, x4) + +inst_1612: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x017 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x017 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3017; op2val:0x4417; + valaddr_reg:x8; val_offset:3174*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 3174*FLEN/8, x10, x1, x4) + +inst_1613: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x017 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x017 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3017; op2val:0x4417; + valaddr_reg:x8; val_offset:3176*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 3176*FLEN/8, x10, x1, x4) + +inst_1614: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x017 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x017 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3017; op2val:0x4417; + valaddr_reg:x8; val_offset:3178*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 3178*FLEN/8, x10, x1, x4) + +inst_1615: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x33e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x33e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b3e; op2val:0x3f3e; + valaddr_reg:x8; val_offset:3180*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 3180*FLEN/8, x10, x1, x4) + +inst_1616: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x33e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x33e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b3e; op2val:0x3f3e; + valaddr_reg:x8; val_offset:3182*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 3182*FLEN/8, x10, x1, x4) + +inst_1617: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x33e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x33e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b3e; op2val:0x3f3e; + valaddr_reg:x8; val_offset:3184*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 3184*FLEN/8, x10, x1, x4) + +inst_1618: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x33e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x33e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b3e; op2val:0x3f3e; + valaddr_reg:x8; val_offset:3186*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 3186*FLEN/8, x10, x1, x4) + +inst_1619: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x33e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x33e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b3e; op2val:0x3f3e; + valaddr_reg:x8; val_offset:3188*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 3188*FLEN/8, x10, x1, x4) + +inst_1620: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x316 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x316 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3316; op2val:0x4716; + valaddr_reg:x8; val_offset:3190*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 3190*FLEN/8, x10, x1, x4) + +inst_1621: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x316 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x316 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3316; op2val:0x4716; + valaddr_reg:x8; val_offset:3192*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 3192*FLEN/8, x10, x1, x4) + +inst_1622: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x316 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x316 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3316; op2val:0x4716; + valaddr_reg:x8; val_offset:3194*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 3194*FLEN/8, x10, x1, x4) + +inst_1623: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x316 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x316 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3316; op2val:0x4716; + valaddr_reg:x8; val_offset:3196*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 3196*FLEN/8, x10, x1, x4) + +inst_1624: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x316 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x316 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3316; op2val:0x4716; + valaddr_reg:x8; val_offset:3198*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 3198*FLEN/8, x10, x1, x4) + +inst_1625: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1b6 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1b6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2db6; op2val:0x41b6; + valaddr_reg:x8; val_offset:3200*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 3200*FLEN/8, x10, x1, x4) + +inst_1626: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1b6 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1b6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2db6; op2val:0x41b6; + valaddr_reg:x8; val_offset:3202*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 3202*FLEN/8, x10, x1, x4) + +inst_1627: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1b6 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1b6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2db6; op2val:0x41b6; + valaddr_reg:x8; val_offset:3204*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 3204*FLEN/8, x10, x1, x4) + +inst_1628: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1b6 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1b6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2db6; op2val:0x41b6; + valaddr_reg:x8; val_offset:3206*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 3206*FLEN/8, x10, x1, x4) + +inst_1629: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1b6 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1b6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2db6; op2val:0x41b6; + valaddr_reg:x8; val_offset:3208*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 3208*FLEN/8, x10, x1, x4) + +inst_1630: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a3 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x1a3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39a3; op2val:0x4da3; + valaddr_reg:x8; val_offset:3210*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 3210*FLEN/8, x10, x1, x4) + +inst_1631: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a3 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x1a3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39a3; op2val:0x4da3; + valaddr_reg:x8; val_offset:3212*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 3212*FLEN/8, x10, x1, x4) + +inst_1632: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a3 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x1a3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39a3; op2val:0x4da3; + valaddr_reg:x8; val_offset:3214*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 3214*FLEN/8, x10, x1, x4) + +inst_1633: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a3 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x1a3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39a3; op2val:0x4da3; + valaddr_reg:x8; val_offset:3216*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 3216*FLEN/8, x10, x1, x4) + +inst_1634: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a3 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x1a3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39a3; op2val:0x4da3; + valaddr_reg:x8; val_offset:3218*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 3218*FLEN/8, x10, x1, x4) + +inst_1635: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x150 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x150 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d50; op2val:0x4150; + valaddr_reg:x8; val_offset:3220*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 3220*FLEN/8, x10, x1, x4) + +inst_1636: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x150 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x150 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d50; op2val:0x4150; + valaddr_reg:x8; val_offset:3222*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 3222*FLEN/8, x10, x1, x4) + +inst_1637: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x150 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x150 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d50; op2val:0x4150; + valaddr_reg:x8; val_offset:3224*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 3224*FLEN/8, x10, x1, x4) + +inst_1638: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x150 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x150 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d50; op2val:0x4150; + valaddr_reg:x8; val_offset:3226*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 3226*FLEN/8, x10, x1, x4) + +inst_1639: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x150 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x150 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d50; op2val:0x4150; + valaddr_reg:x8; val_offset:3228*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 3228*FLEN/8, x10, x1, x4) + +inst_1640: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1b9 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x1b9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39b9; op2val:0x4db9; + valaddr_reg:x8; val_offset:3230*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 3230*FLEN/8, x10, x1, x4) + +inst_1641: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1b9 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x1b9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39b9; op2val:0x4db9; + valaddr_reg:x8; val_offset:3232*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 3232*FLEN/8, x10, x1, x4) + +inst_1642: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1b9 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x1b9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39b9; op2val:0x4db9; + valaddr_reg:x8; val_offset:3234*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 3234*FLEN/8, x10, x1, x4) + +inst_1643: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1b9 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x1b9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39b9; op2val:0x4db9; + valaddr_reg:x8; val_offset:3236*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 3236*FLEN/8, x10, x1, x4) + +inst_1644: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1b9 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x1b9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39b9; op2val:0x4db9; + valaddr_reg:x8; val_offset:3238*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 3238*FLEN/8, x10, x1, x4) + +inst_1645: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31c and fs2 == 0 and fe2 == 0x13 and fm2 == 0x31c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b1c; op2val:0x4f1c; + valaddr_reg:x8; val_offset:3240*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 3240*FLEN/8, x10, x1, x4) + +inst_1646: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31c and fs2 == 0 and fe2 == 0x13 and fm2 == 0x31c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b1c; op2val:0x4f1c; + valaddr_reg:x8; val_offset:3242*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 3242*FLEN/8, x10, x1, x4) + +inst_1647: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31c and fs2 == 0 and fe2 == 0x13 and fm2 == 0x31c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b1c; op2val:0x4f1c; + valaddr_reg:x8; val_offset:3244*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 3244*FLEN/8, x10, x1, x4) + +inst_1648: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31c and fs2 == 0 and fe2 == 0x13 and fm2 == 0x31c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b1c; op2val:0x4f1c; + valaddr_reg:x8; val_offset:3246*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 3246*FLEN/8, x10, x1, x4) + +inst_1649: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31c and fs2 == 0 and fe2 == 0x13 and fm2 == 0x31c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b1c; op2val:0x4f1c; + valaddr_reg:x8; val_offset:3248*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 3248*FLEN/8, x10, x1, x4) + +inst_1650: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x168 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x168 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3968; op2val:0x4d68; + valaddr_reg:x8; val_offset:3250*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 3250*FLEN/8, x10, x1, x4) + +inst_1651: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x168 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x168 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3968; op2val:0x4d68; + valaddr_reg:x8; val_offset:3252*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 3252*FLEN/8, x10, x1, x4) + +inst_1652: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x168 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x168 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3968; op2val:0x4d68; + valaddr_reg:x8; val_offset:3254*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 3254*FLEN/8, x10, x1, x4) + +inst_1653: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x168 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x168 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3968; op2val:0x4d68; + valaddr_reg:x8; val_offset:3256*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 3256*FLEN/8, x10, x1, x4) + +inst_1654: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x168 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x168 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3968; op2val:0x4d68; + valaddr_reg:x8; val_offset:3258*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 3258*FLEN/8, x10, x1, x4) + +inst_1655: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x26e and fs2 == 0 and fe2 == 0x10 and fm2 == 0x26e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e6e; op2val:0x426e; + valaddr_reg:x8; val_offset:3260*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 3260*FLEN/8, x10, x1, x4) + +inst_1656: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x26e and fs2 == 0 and fe2 == 0x10 and fm2 == 0x26e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e6e; op2val:0x426e; + valaddr_reg:x8; val_offset:3262*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 3262*FLEN/8, x10, x1, x4) + +inst_1657: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x26e and fs2 == 0 and fe2 == 0x10 and fm2 == 0x26e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e6e; op2val:0x426e; + valaddr_reg:x8; val_offset:3264*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 3264*FLEN/8, x10, x1, x4) + +inst_1658: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x26e and fs2 == 0 and fe2 == 0x10 and fm2 == 0x26e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e6e; op2val:0x426e; + valaddr_reg:x8; val_offset:3266*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 3266*FLEN/8, x10, x1, x4) + +inst_1659: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x26e and fs2 == 0 and fe2 == 0x10 and fm2 == 0x26e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e6e; op2val:0x426e; + valaddr_reg:x8; val_offset:3268*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 3268*FLEN/8, x10, x1, x4) + +inst_1660: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x088 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x088 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3488; op2val:0x4888; + valaddr_reg:x8; val_offset:3270*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 3270*FLEN/8, x10, x1, x4) + +inst_1661: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x088 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x088 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3488; op2val:0x4888; + valaddr_reg:x8; val_offset:3272*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 3272*FLEN/8, x10, x1, x4) + +inst_1662: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x088 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x088 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3488; op2val:0x4888; + valaddr_reg:x8; val_offset:3274*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 3274*FLEN/8, x10, x1, x4) + +inst_1663: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x088 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x088 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3488; op2val:0x4888; + valaddr_reg:x8; val_offset:3276*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 3276*FLEN/8, x10, x1, x4) + +inst_1664: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x088 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x088 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3488; op2val:0x4888; + valaddr_reg:x8; val_offset:3278*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 3278*FLEN/8, x10, x1, x4) + +inst_1665: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x218 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x217 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3218; op2val:0x4617; + valaddr_reg:x8; val_offset:3280*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 3280*FLEN/8, x10, x1, x4) + +inst_1666: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x218 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x217 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3218; op2val:0x4617; + valaddr_reg:x8; val_offset:3282*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 3282*FLEN/8, x10, x1, x4) + +inst_1667: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x218 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x217 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3218; op2val:0x4617; + valaddr_reg:x8; val_offset:3284*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 3284*FLEN/8, x10, x1, x4) + +inst_1668: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x218 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x217 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3218; op2val:0x4617; + valaddr_reg:x8; val_offset:3286*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 3286*FLEN/8, x10, x1, x4) + +inst_1669: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x218 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x217 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3218; op2val:0x4617; + valaddr_reg:x8; val_offset:3288*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 3288*FLEN/8, x10, x1, x4) + +inst_1670: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2be and fs2 == 0 and fe2 == 0x10 and fm2 == 0x2bd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ebe; op2val:0x42bd; + valaddr_reg:x8; val_offset:3290*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x8, 3290*FLEN/8, x10, x1, x4) + +inst_1671: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2be and fs2 == 0 and fe2 == 0x10 and fm2 == 0x2bd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ebe; op2val:0x42bd; + valaddr_reg:x8; val_offset:3292*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 3292*FLEN/8, x10, x1, x4) + +inst_1672: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2be and fs2 == 0 and fe2 == 0x10 and fm2 == 0x2bd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ebe; op2val:0x42bd; + valaddr_reg:x8; val_offset:3294*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 3294*FLEN/8, x10, x1, x4) + +inst_1673: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2be and fs2 == 0 and fe2 == 0x10 and fm2 == 0x2bd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ebe; op2val:0x42bd; + valaddr_reg:x8; val_offset:3296*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x8, 3296*FLEN/8, x10, x1, x4) + +inst_1674: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2be and fs2 == 0 and fe2 == 0x10 and fm2 == 0x2bd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ebe; op2val:0x42bd; + valaddr_reg:x8; val_offset:3298*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 3298*FLEN/8, x10, x1, x4) + +inst_1675: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x218 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a18; op2val:0x7bff; + valaddr_reg:x8; val_offset:3300*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 3300*FLEN/8, x10, x1, x4) + +inst_1676: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x218 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a18; op2val:0x7bff; + valaddr_reg:x8; val_offset:3302*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x8, 3302*FLEN/8, x10, x1, x4) + +inst_1677: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ec and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x39ec; op2val:0x7bff; + valaddr_reg:x8; val_offset:3304*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 3304*FLEN/8, x10, x1, x4) + +inst_1678: +// fs1 == 0 and fe1 == 0x07 and fm1 == 0x075 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x075 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x1c75; op2val:0x7875; + valaddr_reg:x8; val_offset:3306*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x8, 3306*FLEN/8, x10, x1, x4) + +inst_1679: +// fs1 == 0 and fe1 == 0x07 and fm1 == 0x075 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x075 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x1c75; op2val:0x7875; + valaddr_reg:x8; val_offset:3308*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x8, 3308*FLEN/8, x10, x1, x4) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(14872,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(14872,32,FLEN) +NAN_BOXED(14872,32,FLEN) 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+NAN_BOXED(16720,16,FLEN) +NAN_BOXED(11600,16,FLEN) +NAN_BOXED(16720,16,FLEN) +NAN_BOXED(11600,16,FLEN) +NAN_BOXED(16720,16,FLEN) +NAN_BOXED(11600,16,FLEN) +NAN_BOXED(16720,16,FLEN) +NAN_BOXED(11600,16,FLEN) +NAN_BOXED(16720,16,FLEN) +NAN_BOXED(14777,16,FLEN) +NAN_BOXED(19897,16,FLEN) +NAN_BOXED(14777,16,FLEN) +NAN_BOXED(19897,16,FLEN) +NAN_BOXED(14777,16,FLEN) +NAN_BOXED(19897,16,FLEN) +NAN_BOXED(14777,16,FLEN) +NAN_BOXED(19897,16,FLEN) +NAN_BOXED(14777,16,FLEN) +NAN_BOXED(19897,16,FLEN) +NAN_BOXED(15132,16,FLEN) +NAN_BOXED(20252,16,FLEN) +NAN_BOXED(15132,16,FLEN) +NAN_BOXED(20252,16,FLEN) +NAN_BOXED(15132,16,FLEN) +NAN_BOXED(20252,16,FLEN) +NAN_BOXED(15132,16,FLEN) +NAN_BOXED(20252,16,FLEN) +NAN_BOXED(15132,16,FLEN) +NAN_BOXED(20252,16,FLEN) +NAN_BOXED(14696,16,FLEN) +NAN_BOXED(19816,16,FLEN) +NAN_BOXED(14696,16,FLEN) +NAN_BOXED(19816,16,FLEN) +NAN_BOXED(14696,16,FLEN) +NAN_BOXED(19816,16,FLEN) +NAN_BOXED(14696,16,FLEN) +NAN_BOXED(19816,16,FLEN) +NAN_BOXED(14696,16,FLEN) +NAN_BOXED(19816,16,FLEN) +NAN_BOXED(11886,16,FLEN) +NAN_BOXED(17006,16,FLEN) +NAN_BOXED(11886,16,FLEN) +NAN_BOXED(17006,16,FLEN) +NAN_BOXED(11886,16,FLEN) +NAN_BOXED(17006,16,FLEN) +NAN_BOXED(11886,16,FLEN) +NAN_BOXED(17006,16,FLEN) +NAN_BOXED(11886,16,FLEN) +NAN_BOXED(17006,16,FLEN) +NAN_BOXED(13448,16,FLEN) +NAN_BOXED(18568,16,FLEN) +NAN_BOXED(13448,16,FLEN) +NAN_BOXED(18568,16,FLEN) +NAN_BOXED(13448,16,FLEN) +NAN_BOXED(18568,16,FLEN) +NAN_BOXED(13448,16,FLEN) +NAN_BOXED(18568,16,FLEN) +NAN_BOXED(13448,16,FLEN) +NAN_BOXED(18568,16,FLEN) +NAN_BOXED(12824,16,FLEN) +NAN_BOXED(17943,16,FLEN) +NAN_BOXED(12824,16,FLEN) +NAN_BOXED(17943,16,FLEN) +NAN_BOXED(12824,16,FLEN) +NAN_BOXED(17943,16,FLEN) +NAN_BOXED(12824,16,FLEN) +NAN_BOXED(17943,16,FLEN) +NAN_BOXED(12824,16,FLEN) +NAN_BOXED(17943,16,FLEN) +NAN_BOXED(11966,16,FLEN) +NAN_BOXED(17085,16,FLEN) +NAN_BOXED(11966,16,FLEN) +NAN_BOXED(17085,16,FLEN) +NAN_BOXED(11966,16,FLEN) +NAN_BOXED(17085,16,FLEN) +NAN_BOXED(11966,16,FLEN) +NAN_BOXED(17085,16,FLEN) +NAN_BOXED(11966,16,FLEN) +NAN_BOXED(17085,16,FLEN) +NAN_BOXED(14872,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(14872,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(14828,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(7285,16,FLEN) +NAN_BOXED(30837,16,FLEN) +NAN_BOXED(7285,16,FLEN) +NAN_BOXED(30837,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x5_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x5_1: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_0: + .fill 32*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_0: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_2: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_3: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_4: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_5: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_6: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_7: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_8: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_9: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_10: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_11: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_12: + .fill 228*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fdiv_b9-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fdiv_b9-01.S new file mode 100644 index 000000000..e207978b1 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fdiv_b9-01.S @@ -0,0 +1,1494 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 05:22:24 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fdiv.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fdiv.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fdiv_b9 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fdiv_b9) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x15,test_dataset_0) +RVTEST_SIGBASE(x11,signature_x11_1) + +inst_0: +// rs1 == rd != rs2, rs1==x5, rs2==x18, rd==x5,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x5; op2:x18; dest:x5; op1val:0x0; op2val:0x0; + valaddr_reg:x15; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fdiv.h, x5, x5, x18, dyn, 0, 0, x15, 0*FLEN/8, x21, x11, x6) + +inst_1: +// rs1 == rs2 != rd, rs1==x7, rs2==x7, rd==x31,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x7; op2:x7; dest:x31; op1val:0x8000; op2val:0x8000; + valaddr_reg:x15; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fdiv.h, x31, x7, x7, dyn, 0, 0, x15, 2*FLEN/8, x21, x11, x6) + +inst_2: +// rs1 == rs2 == rd, rs1==x9, rs2==x9, rd==x9,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x08 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x9; op2:x9; dest:x9; op1val:0x3c00; op2val:0x3c00; + valaddr_reg:x15; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fdiv.h, x9, x9, x9, dyn, 0, 0, x15, 4*FLEN/8, x21, x11, x6) + +inst_3: +// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==x24, rs2==x4, rd==x0,fs1 == 0 and fe1 == 0x08 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x24; op2:x4; dest:x0; op1val:0x2000; op2val:0x3c00; + valaddr_reg:x15; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fdiv.h, x0, x24, x4, dyn, 0, 0, x15, 6*FLEN/8, x21, x11, x6) + +inst_4: +// rs2 == rd != rs1, rs1==x27, rs2==x28, rd==x28,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x27; op2:x28; dest:x28; op1val:0x3c00; op2val:0x3ff8; + valaddr_reg:x15; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fdiv.h, x28, x27, x28, dyn, 0, 0, x15, 8*FLEN/8, x21, x11, x6) + +inst_5: +// rs1==x17, rs2==x31, rd==x23,fs1 == 0 and fe1 == 0x0f and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x17; op2:x31; dest:x23; op1val:0x3ff8; op2val:0x3c00; + valaddr_reg:x15; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fdiv.h, x23, x17, x31, dyn, 0, 0, x15, 10*FLEN/8, x21, x11, x6) + +inst_6: +// rs1==x20, rs2==x17, rd==x13,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x20; op2:x17; dest:x13; op1val:0x3c00; op2val:0x3000; + valaddr_reg:x15; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fdiv.h, x13, x20, x17, dyn, 0, 0, x15, 12*FLEN/8, x21, x11, x6) + +inst_7: +// rs1==x10, rs2==x5, rd==x19,fs1 == 0 and fe1 == 0x0c and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x10; op2:x5; dest:x19; op1val:0x3000; op2val:0x3c00; + valaddr_reg:x15; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fdiv.h, x19, x10, x5, dyn, 0, 0, x15, 14*FLEN/8, x21, x11, x6) + +inst_8: +// rs1==x18, rs2==x12, rd==x8,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x18; op2:x12; dest:x8; op1val:0x3c00; op2val:0x2ff8; + valaddr_reg:x15; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fdiv.h, x8, x18, x12, dyn, 0, 0, x15, 16*FLEN/8, x21, x11, x6) + +inst_9: +// rs1==x25, rs2==x10, rd==x2,fs1 == 0 and fe1 == 0x0b and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x25; op2:x10; dest:x2; op1val:0x2ff8; op2val:0x3c00; + valaddr_reg:x15; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fdiv.h, x2, x25, x10, dyn, 0, 0, x15, 18*FLEN/8, x21, x11, x6) + +inst_10: +// rs1==x23, rs2==x2, rd==x25,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x23; op2:x2; dest:x25; op1val:0x3c00; op2val:0x3800; + valaddr_reg:x15; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fdiv.h, x25, x23, x2, dyn, 0, 0, x15, 20*FLEN/8, x21, x11, x6) + +inst_11: +// rs1==x1, rs2==x25, rd==x16,fs1 == 0 and fe1 == 0x0e and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x1; op2:x25; dest:x16; op1val:0x3800; op2val:0x3c00; + valaddr_reg:x15; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fdiv.h, x16, x1, x25, dyn, 0, 0, x15, 22*FLEN/8, x21, x11, x6) + +inst_12: +// rs1==x3, rs2==x0, rd==x12,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x3; op2:x0; dest:x12; op1val:0x3c00; op2val:0x0; + valaddr_reg:x15; val_offset:24*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fdiv.h, x12, x3, x0, dyn, 0, 0, x15, 24*FLEN/8, x21, x11, x6) + +inst_13: +// rs1==x0, rs2==x3, rd==x14,fs1 == 0 and fe1 == 0x09 and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x0; op2:x3; dest:x14; op1val:0x0; op2val:0x3c00; + valaddr_reg:x15; val_offset:26*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fdiv.h, x14, x0, x3, dyn, 0, 0, x15, 26*FLEN/8, x21, x11, x6) +RVTEST_VALBASEUPD(x1,test_dataset_1) + +inst_14: +// rs1==x26, rs2==x19, rd==x15,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x26; op2:x19; dest:x15; op1val:0x3c00; op2val:0x3c00; + valaddr_reg:x1; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fdiv.h, x15, x26, x19, dyn, 0, 0, x1, 0*FLEN/8, x9, x11, x6) + +inst_15: +// rs1==x14, rs2==x26, rd==x6,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x08 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x14; op2:x26; dest:x6; op1val:0x3c00; op2val:0x23f8; + valaddr_reg:x1; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x6, x14, x26, dyn, 0, 0, x1, 2*FLEN/8, x9, x11, x7) +RVTEST_SIGBASE(x5,signature_x5_0) + +inst_16: +// rs1==x31, rs2==x6, rd==x29,fs1 == 0 and fe1 == 0x08 and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x31; op2:x6; dest:x29; op1val:0x23f8; op2val:0x3c00; + valaddr_reg:x1; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x29, x31, x6, dyn, 0, 0, x1, 4*FLEN/8, x9, x5, x7) + +inst_17: +// rs1==x12, rs2==x11, rd==x27,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x12; op2:x11; dest:x27; op1val:0x3c00; op2val:0x3e00; + valaddr_reg:x1; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x27, x12, x11, dyn, 0, 0, x1, 6*FLEN/8, x9, x5, x7) + +inst_18: +// rs1==x16, rs2==x8, rd==x17,fs1 == 0 and fe1 == 0x0f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x16; op2:x8; dest:x17; op1val:0x3e00; op2val:0x3c00; + valaddr_reg:x1; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x17, x16, x8, dyn, 0, 0, x1, 8*FLEN/8, x9, x5, x7) + +inst_19: +// rs1==x2, rs2==x14, rd==x24,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x08 and fm2 == 0x1f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x2; op2:x14; dest:x24; op1val:0x3c00; op2val:0x21f8; + valaddr_reg:x1; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x24, x2, x14, dyn, 0, 0, x1, 10*FLEN/8, x9, x5, x7) + +inst_20: +// rs1==x11, rs2==x30, rd==x3,fs1 == 0 and fe1 == 0x08 and fm1 == 0x1f8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x11; op2:x30; dest:x3; op1val:0x21f8; op2val:0x3c00; + valaddr_reg:x1; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x3, x11, x30, dyn, 0, 0, x1, 12*FLEN/8, x9, x5, x7) + +inst_21: +// rs1==x22, rs2==x20, rd==x30,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x22; op2:x20; dest:x30; op1val:0x3c00; op2val:0x3f00; + valaddr_reg:x1; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x30, x22, x20, dyn, 0, 0, x1, 14*FLEN/8, x9, x5, x7) + +inst_22: +// rs1==x30, rs2==x16, rd==x18,fs1 == 0 and fe1 == 0x0f and fm1 == 0x300 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x16; dest:x18; op1val:0x3f00; op2val:0x3c00; + valaddr_reg:x1; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x18, x30, x16, dyn, 0, 0, x1, 16*FLEN/8, x9, x5, x7) + +inst_23: +// rs1==x4, rs2==x29, rd==x22,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x08 and fm2 == 0x0f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x4; op2:x29; dest:x22; op1val:0x3c00; op2val:0x20f8; + valaddr_reg:x1; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x22, x4, x29, dyn, 0, 0, x1, 18*FLEN/8, x9, x5, x7) + +inst_24: +// rs1==x28, rs2==x13, rd==x4,fs1 == 0 and fe1 == 0x08 and fm1 == 0x0f8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x28; op2:x13; dest:x4; op1val:0x20f8; op2val:0x3c00; + valaddr_reg:x1; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x4, x28, x13, dyn, 0, 0, x1, 20*FLEN/8, x9, x5, x7) +RVTEST_VALBASEUPD(x3,test_dataset_2) + +inst_25: +// rs1==x21, rs2==x27, rd==x10,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x21; op2:x27; dest:x10; op1val:0x3c00; op2val:0x3f80; + valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x10, x21, x27, dyn, 0, 0, x3, 0*FLEN/8, x4, x5, x7) + +inst_26: +// rs1==x29, rs2==x23, rd==x1,fs1 == 0 and fe1 == 0x0f and fm1 == 0x380 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x29; op2:x23; dest:x1; op1val:0x3f80; op2val:0x3c00; + valaddr_reg:x3; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7 +*/ +TEST_FPRR_OP(fdiv.h, x1, x29, x23, dyn, 0, 0, x3, 2*FLEN/8, x4, x5, x7) + +inst_27: +// rs1==x6, rs2==x15, rd==x11,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x08 and fm2 == 0x078 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x6; op2:x15; dest:x11; op1val:0x3c00; op2val:0x2078; + valaddr_reg:x3; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x11, x6, x15, dyn, 0, 0, x3, 4*FLEN/8, x4, x5, x2) + +inst_28: +// rs1==x15, rs2==x1, rd==x20,fs1 == 0 and fe1 == 0x08 and fm1 == 0x078 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x15; op2:x1; dest:x20; op1val:0x2078; op2val:0x3c00; + valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x20, x15, x1, dyn, 0, 0, x3, 6*FLEN/8, x4, x5, x2) + +inst_29: +// rs1==x19, rs2==x22, rd==x7,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x19; op2:x22; dest:x7; op1val:0x3c00; op2val:0x3fc0; + valaddr_reg:x3; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x7, x19, x22, dyn, 0, 0, x3, 8*FLEN/8, x4, x5, x2) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_30: +// rs1==x8, rs2==x24, rd==x21,fs1 == 0 and fe1 == 0x0f and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x8; op2:x24; dest:x21; op1val:0x3fc0; op2val:0x3c00; + valaddr_reg:x3; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x21, x8, x24, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==x13, rs2==x21, rd==x26,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x08 and fm2 == 0x038 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x13; op2:x21; dest:x26; op1val:0x3c00; op2val:0x2038; + valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x26, x13, x21, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_32: +// fs1 == 0 and fe1 == 0x08 and fm1 == 0x038 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2038; op2val:0x3c00; + valaddr_reg:x3; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_33: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3fe0; + valaddr_reg:x3; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_34: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fe0; op2val:0x3c00; + valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_35: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x08 and fm2 == 0x018 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2018; + valaddr_reg:x3; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_36: +// fs1 == 0 and fe1 == 0x08 and fm1 == 0x018 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2018; op2val:0x3c00; + valaddr_reg:x3; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_37: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3ff0; + valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_38: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff0; op2val:0x3c00; + valaddr_reg:x3; val_offset:26*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_39: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x08 and fm2 == 0x008 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2008; + valaddr_reg:x3; val_offset:28*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_40: +// fs1 == 0 and fe1 == 0x08 and fm1 == 0x008 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2008; op2val:0x3c00; + valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_41: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x1b0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2db0; + valaddr_reg:x3; val_offset:32*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 32*FLEN/8, x4, x1, x2) + +inst_42: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1b0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2db0; op2val:0x3c00; + valaddr_reg:x3; val_offset:34*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 34*FLEN/8, x4, x1, x2) + +inst_43: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x368 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3b68; + valaddr_reg:x3; val_offset:36*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 36*FLEN/8, x4, x1, x2) + +inst_44: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x368 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b68; op2val:0x3c00; + valaddr_reg:x3; val_offset:38*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 38*FLEN/8, x4, x1, x2) + +inst_45: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x260 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2660; + valaddr_reg:x3; val_offset:40*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 40*FLEN/8, x4, x1, x2) + +inst_46: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x260 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2660; op2val:0x3c00; + valaddr_reg:x3; val_offset:42*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 42*FLEN/8, x4, x1, x2) + +inst_47: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x198 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3998; + valaddr_reg:x3; val_offset:44*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 44*FLEN/8, x4, x1, x2) + +inst_48: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x198 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3998; op2val:0x3c00; + valaddr_reg:x3; val_offset:46*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 46*FLEN/8, x4, x1, x2) + +inst_49: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2e8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2ee8; + valaddr_reg:x3; val_offset:48*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 48*FLEN/8, x4, x1, x2) + +inst_50: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2e8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ee8; op2val:0x3c00; + valaddr_reg:x3; val_offset:50*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 50*FLEN/8, x4, x1, x2) + +inst_51: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x110 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3110; + valaddr_reg:x3; val_offset:52*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 52*FLEN/8, x4, x1, x2) + +inst_52: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x110 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3110; op2val:0x3c00; + valaddr_reg:x3; val_offset:54*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 54*FLEN/8, x4, x1, x2) + +inst_53: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x120 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2920; + valaddr_reg:x3; val_offset:56*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 56*FLEN/8, x4, x1, x2) + +inst_54: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x120 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2920; op2val:0x3c00; + valaddr_reg:x3; val_offset:58*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 58*FLEN/8, x4, x1, x2) + +inst_55: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2d8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x36d8; + valaddr_reg:x3; val_offset:60*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 60*FLEN/8, x4, x1, x2) + +inst_56: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2d8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x36d8; op2val:0x3c00; + valaddr_reg:x3; val_offset:62*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 62*FLEN/8, x4, x1, x2) + +inst_57: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x0c8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2cc8; + valaddr_reg:x3; val_offset:64*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 64*FLEN/8, x4, x1, x2) + +inst_58: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0c8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2cc8; op2val:0x3c00; + valaddr_reg:x3; val_offset:66*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 66*FLEN/8, x4, x1, x2) + +inst_59: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x330 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3330; + valaddr_reg:x3; val_offset:68*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 68*FLEN/8, x4, x1, x2) + +inst_60: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x330 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3330; op2val:0x3c00; + valaddr_reg:x3; val_offset:70*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 70*FLEN/8, x4, x1, x2) + +inst_61: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x08 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xa000; + valaddr_reg:x3; val_offset:72*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 72*FLEN/8, x4, x1, x2) + +inst_62: +// fs1 == 1 and fe1 == 0x08 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xa000; op2val:0xbc00; + valaddr_reg:x3; val_offset:74*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 74*FLEN/8, x4, x1, x2) + +inst_63: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbff8; + valaddr_reg:x3; val_offset:76*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 76*FLEN/8, x4, x1, x2) + +inst_64: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xbff8; op2val:0xbc00; + valaddr_reg:x3; val_offset:78*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 78*FLEN/8, x4, x1, x2) + +inst_65: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb000; + valaddr_reg:x3; val_offset:80*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 80*FLEN/8, x4, x1, x2) + +inst_66: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xb000; op2val:0xbc00; + valaddr_reg:x3; val_offset:82*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 82*FLEN/8, x4, x1, x2) + +inst_67: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xaff8; + valaddr_reg:x3; val_offset:84*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 84*FLEN/8, x4, x1, x2) + +inst_68: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xaff8; op2val:0xbc00; + valaddr_reg:x3; val_offset:86*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 86*FLEN/8, x4, x1, x2) + +inst_69: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb800; + valaddr_reg:x3; val_offset:88*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 88*FLEN/8, x4, x1, x2) + +inst_70: +// fs1 == 1 and fe1 == 0x0e and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xb800; op2val:0xbc00; + valaddr_reg:x3; val_offset:90*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 90*FLEN/8, x4, x1, x2) + +inst_71: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x09 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xa7f8; + valaddr_reg:x3; val_offset:92*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 92*FLEN/8, x4, x1, x2) + +inst_72: +// fs1 == 1 and fe1 == 0x09 and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xa7f8; op2val:0xbc00; + valaddr_reg:x3; val_offset:94*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 94*FLEN/8, x4, x1, x2) + +inst_73: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbc00; + valaddr_reg:x3; val_offset:96*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 96*FLEN/8, x4, x1, x2) + +inst_74: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x08 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xa3f8; + valaddr_reg:x3; val_offset:98*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 98*FLEN/8, x4, x1, x2) + +inst_75: +// fs1 == 1 and fe1 == 0x08 and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xa3f8; op2val:0xbc00; + valaddr_reg:x3; val_offset:100*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 100*FLEN/8, x4, x1, x2) + +inst_76: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbe00; + valaddr_reg:x3; val_offset:102*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 102*FLEN/8, x4, x1, x2) + +inst_77: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xbe00; op2val:0xbc00; + valaddr_reg:x3; val_offset:104*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 104*FLEN/8, x4, x1, x2) + +inst_78: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x08 and fm2 == 0x1f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xa1f8; + valaddr_reg:x3; val_offset:106*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 106*FLEN/8, x4, x1, x2) + +inst_79: +// fs1 == 1 and fe1 == 0x08 and fm1 == 0x1f8 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xa1f8; op2val:0xbc00; + valaddr_reg:x3; val_offset:108*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 108*FLEN/8, x4, x1, x2) + +inst_80: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbf00; + valaddr_reg:x3; val_offset:110*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 110*FLEN/8, x4, x1, x2) + +inst_81: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x300 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xbf00; op2val:0xbc00; + valaddr_reg:x3; val_offset:112*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 112*FLEN/8, x4, x1, x2) + +inst_82: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x08 and fm2 == 0x0f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xa0f8; + valaddr_reg:x3; val_offset:114*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 114*FLEN/8, x4, x1, x2) + +inst_83: +// fs1 == 1 and fe1 == 0x08 and fm1 == 0x0f8 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xa0f8; op2val:0xbc00; + valaddr_reg:x3; val_offset:116*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 116*FLEN/8, x4, x1, x2) + +inst_84: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbf80; + valaddr_reg:x3; val_offset:118*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 118*FLEN/8, x4, x1, x2) + +inst_85: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x380 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xbf80; op2val:0xbc00; + valaddr_reg:x3; val_offset:120*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 120*FLEN/8, x4, x1, x2) + +inst_86: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x08 and fm2 == 0x078 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xa078; + valaddr_reg:x3; val_offset:122*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 122*FLEN/8, x4, x1, x2) + +inst_87: +// fs1 == 1 and fe1 == 0x08 and fm1 == 0x078 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xa078; op2val:0xbc00; + valaddr_reg:x3; val_offset:124*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 124*FLEN/8, x4, x1, x2) + +inst_88: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbfc0; + valaddr_reg:x3; val_offset:126*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 126*FLEN/8, x4, x1, x2) + +inst_89: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xbfc0; op2val:0xbc00; + valaddr_reg:x3; val_offset:128*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 128*FLEN/8, x4, x1, x2) + +inst_90: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x08 and fm2 == 0x038 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xa038; + valaddr_reg:x3; val_offset:130*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 130*FLEN/8, x4, x1, x2) + +inst_91: +// fs1 == 1 and fe1 == 0x08 and fm1 == 0x038 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xa038; op2val:0xbc00; + valaddr_reg:x3; val_offset:132*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 132*FLEN/8, x4, x1, x2) + +inst_92: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbfe0; + valaddr_reg:x3; val_offset:134*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 134*FLEN/8, x4, x1, x2) + +inst_93: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xbfe0; op2val:0xbc00; + valaddr_reg:x3; val_offset:136*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 136*FLEN/8, x4, x1, x2) + +inst_94: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x08 and fm2 == 0x018 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xa018; + valaddr_reg:x3; val_offset:138*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 138*FLEN/8, x4, x1, x2) + +inst_95: +// fs1 == 1 and fe1 == 0x08 and fm1 == 0x018 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xa018; op2val:0xbc00; + valaddr_reg:x3; val_offset:140*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 140*FLEN/8, x4, x1, x2) + +inst_96: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbff0; + valaddr_reg:x3; val_offset:142*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 142*FLEN/8, x4, x1, x2) + +inst_97: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xbff0; op2val:0xbc00; + valaddr_reg:x3; val_offset:144*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 144*FLEN/8, x4, x1, x2) + +inst_98: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x08 and fm2 == 0x008 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xa008; + valaddr_reg:x3; val_offset:146*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 146*FLEN/8, x4, x1, x2) + +inst_99: +// fs1 == 1 and fe1 == 0x08 and fm1 == 0x008 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xa008; op2val:0xbc00; + valaddr_reg:x3; val_offset:148*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 148*FLEN/8, x4, x1, x2) + +inst_100: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1b0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xadb0; + valaddr_reg:x3; val_offset:150*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 150*FLEN/8, x4, x1, x2) + +inst_101: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x1b0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xadb0; op2val:0xbc00; + valaddr_reg:x3; val_offset:152*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 152*FLEN/8, x4, x1, x2) + +inst_102: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x368 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbb68; + valaddr_reg:x3; val_offset:154*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 154*FLEN/8, x4, x1, x2) + +inst_103: +// fs1 == 1 and fe1 == 0x0e and fm1 == 0x368 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xbb68; op2val:0xbc00; + valaddr_reg:x3; val_offset:156*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 156*FLEN/8, x4, x1, x2) + +inst_104: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x09 and fm2 == 0x260 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xa660; + valaddr_reg:x3; val_offset:158*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 158*FLEN/8, x4, x1, x2) + +inst_105: +// fs1 == 1 and fe1 == 0x09 and fm1 == 0x260 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xa660; op2val:0xbc00; + valaddr_reg:x3; val_offset:160*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 160*FLEN/8, x4, x1, x2) + +inst_106: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x198 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb998; + valaddr_reg:x3; val_offset:162*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 162*FLEN/8, x4, x1, x2) + +inst_107: +// fs1 == 1 and fe1 == 0x0e and fm1 == 0x198 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xb998; op2val:0xbc00; + valaddr_reg:x3; val_offset:164*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 164*FLEN/8, x4, x1, x2) + +inst_108: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x2e8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xaee8; + valaddr_reg:x3; val_offset:166*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 166*FLEN/8, x4, x1, x2) + +inst_109: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x2e8 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xaee8; op2val:0xbc00; + valaddr_reg:x3; val_offset:168*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 168*FLEN/8, x4, x1, x2) + +inst_110: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x110 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb110; + valaddr_reg:x3; val_offset:170*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 170*FLEN/8, x4, x1, x2) + +inst_111: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x110 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xb110; op2val:0xbc00; + valaddr_reg:x3; val_offset:172*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 172*FLEN/8, x4, x1, x2) + +inst_112: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x120 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xa920; + valaddr_reg:x3; val_offset:174*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 174*FLEN/8, x4, x1, x2) + +inst_113: +// fs1 == 1 and fe1 == 0x0a and fm1 == 0x120 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xa920; op2val:0xbc00; + valaddr_reg:x3; val_offset:176*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 176*FLEN/8, x4, x1, x2) + +inst_114: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2d8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb6d8; + valaddr_reg:x3; val_offset:178*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 178*FLEN/8, x4, x1, x2) + +inst_115: +// fs1 == 1 and fe1 == 0x0d and fm1 == 0x2d8 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xb6d8; op2val:0xbc00; + valaddr_reg:x3; val_offset:180*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 180*FLEN/8, x4, x1, x2) + +inst_116: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x0c8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xacc8; + valaddr_reg:x3; val_offset:182*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 182*FLEN/8, x4, x1, x2) + +inst_117: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x0c8 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xacc8; op2val:0xbc00; + valaddr_reg:x3; val_offset:184*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 184*FLEN/8, x4, x1, x2) + +inst_118: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x330 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb330; + valaddr_reg:x3; val_offset:186*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 186*FLEN/8, x4, x1, x2) + +inst_119: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x330 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xb330; op2val:0xbc00; + valaddr_reg:x3; val_offset:188*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 188*FLEN/8, x4, x1, x2) + +inst_120: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x0; + valaddr_reg:x3; val_offset:190*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 190*FLEN/8, x4, x1, x2) + +inst_121: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x1; + valaddr_reg:x3; val_offset:192*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 192*FLEN/8, x4, x1, x2) + +inst_122: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8000; + valaddr_reg:x3; val_offset:194*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 194*FLEN/8, x4, x1, x2) + +inst_123: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8001; + valaddr_reg:x3; val_offset:196*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 196*FLEN/8, x4, x1, x2) + +inst_124: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x0; + valaddr_reg:x3; val_offset:198*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 198*FLEN/8, x4, x1, x2) + +inst_125: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x3ff; + valaddr_reg:x3; val_offset:200*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 200*FLEN/8, x4, x1, x2) + +inst_126: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8000; + valaddr_reg:x3; val_offset:202*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 202*FLEN/8, x4, x1, x2) + +inst_127: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x83ff; + valaddr_reg:x3; val_offset:204*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 204*FLEN/8, x4, x1, x2) + +inst_128: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x0; + valaddr_reg:x3; val_offset:206*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 206*FLEN/8, x4, x1, x2) + +inst_129: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x400; + valaddr_reg:x3; val_offset:208*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 208*FLEN/8, x4, x1, x2) + +inst_130: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8000; + valaddr_reg:x3; val_offset:210*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 210*FLEN/8, x4, x1, x2) + +inst_131: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8400; + valaddr_reg:x3; val_offset:212*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 212*FLEN/8, x4, x1, x2) + +inst_132: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7bff; + valaddr_reg:x3; val_offset:214*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 214*FLEN/8, x4, x1, x2) + +inst_133: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfbff; + valaddr_reg:x3; val_offset:216*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 216*FLEN/8, x4, x1, x2) + +inst_134: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8000; + valaddr_reg:x3; val_offset:218*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 218*FLEN/8, x4, x1, x2) + +inst_135: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x08 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2000; + valaddr_reg:x3; val_offset:220*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 220*FLEN/8, x4, x1, x2) + +inst_136: +// fs1 == 0 and fe1 == 0x08 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2000; op2val:0x3c00; + valaddr_reg:x3; val_offset:222*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 222*FLEN/8, x4, x1, x2) + +inst_137: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x27f8; + valaddr_reg:x3; val_offset:224*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 224*FLEN/8, x4, x1, x2) + +inst_138: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x27f8; op2val:0x3c00; + valaddr_reg:x3; val_offset:226*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 226*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(15360,32,FLEN) +NAN_BOXED(15360,32,FLEN) +NAN_BOXED(8192,32,FLEN) +NAN_BOXED(15360,32,FLEN) +NAN_BOXED(15360,32,FLEN) +NAN_BOXED(16376,32,FLEN) +NAN_BOXED(16376,32,FLEN) +NAN_BOXED(15360,32,FLEN) +NAN_BOXED(15360,32,FLEN) +NAN_BOXED(12288,32,FLEN) +NAN_BOXED(12288,32,FLEN) +NAN_BOXED(15360,32,FLEN) +NAN_BOXED(15360,32,FLEN) +NAN_BOXED(12280,32,FLEN) +NAN_BOXED(12280,32,FLEN) +NAN_BOXED(15360,32,FLEN) +NAN_BOXED(15360,32,FLEN) +NAN_BOXED(14336,32,FLEN) +NAN_BOXED(14336,32,FLEN) +NAN_BOXED(15360,32,FLEN) +NAN_BOXED(15360,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(15360,32,FLEN) +test_dataset_1: +NAN_BOXED(15360,32,FLEN) +NAN_BOXED(15360,32,FLEN) +NAN_BOXED(15360,32,FLEN) +NAN_BOXED(9208,32,FLEN) +NAN_BOXED(9208,32,FLEN) +NAN_BOXED(15360,32,FLEN) +NAN_BOXED(15360,32,FLEN) +NAN_BOXED(15872,32,FLEN) +NAN_BOXED(15872,32,FLEN) +NAN_BOXED(15360,32,FLEN) +NAN_BOXED(15360,32,FLEN) +NAN_BOXED(8696,32,FLEN) +NAN_BOXED(8696,32,FLEN) +NAN_BOXED(15360,32,FLEN) +NAN_BOXED(15360,32,FLEN) +NAN_BOXED(16128,32,FLEN) +NAN_BOXED(16128,32,FLEN) +NAN_BOXED(15360,32,FLEN) +NAN_BOXED(15360,32,FLEN) +NAN_BOXED(8440,32,FLEN) +NAN_BOXED(8440,32,FLEN) +NAN_BOXED(15360,32,FLEN) +test_dataset_2: +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(16256,16,FLEN) +NAN_BOXED(16256,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(8312,16,FLEN) +NAN_BOXED(8312,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(16320,16,FLEN) +NAN_BOXED(16320,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(8248,16,FLEN) +NAN_BOXED(8248,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(16352,16,FLEN) +NAN_BOXED(16352,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(8216,16,FLEN) +NAN_BOXED(8216,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(16368,16,FLEN) +NAN_BOXED(16368,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(8200,16,FLEN) +NAN_BOXED(8200,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(11696,16,FLEN) +NAN_BOXED(11696,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15208,16,FLEN) +NAN_BOXED(15208,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(9824,16,FLEN) +NAN_BOXED(9824,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(14744,16,FLEN) +NAN_BOXED(14744,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(12008,16,FLEN) +NAN_BOXED(12008,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(12560,16,FLEN) +NAN_BOXED(12560,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(10528,16,FLEN) +NAN_BOXED(10528,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(14040,16,FLEN) +NAN_BOXED(14040,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(11464,16,FLEN) +NAN_BOXED(11464,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(13104,16,FLEN) +NAN_BOXED(13104,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(40960,16,FLEN) +NAN_BOXED(40960,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(49144,16,FLEN) +NAN_BOXED(49144,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(45056,16,FLEN) +NAN_BOXED(45056,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(45048,16,FLEN) +NAN_BOXED(45048,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(47104,16,FLEN) +NAN_BOXED(47104,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(43000,16,FLEN) +NAN_BOXED(43000,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(41976,16,FLEN) +NAN_BOXED(41976,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48640,16,FLEN) +NAN_BOXED(48640,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(41464,16,FLEN) +NAN_BOXED(41464,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48896,16,FLEN) +NAN_BOXED(48896,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(41208,16,FLEN) +NAN_BOXED(41208,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(49024,16,FLEN) +NAN_BOXED(49024,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(41080,16,FLEN) +NAN_BOXED(41080,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(49088,16,FLEN) +NAN_BOXED(49088,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(41016,16,FLEN) +NAN_BOXED(41016,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(49120,16,FLEN) +NAN_BOXED(49120,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(40984,16,FLEN) +NAN_BOXED(40984,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(49136,16,FLEN) +NAN_BOXED(49136,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(40968,16,FLEN) +NAN_BOXED(40968,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(44464,16,FLEN) +NAN_BOXED(44464,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(47976,16,FLEN) +NAN_BOXED(47976,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(42592,16,FLEN) +NAN_BOXED(42592,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(47512,16,FLEN) +NAN_BOXED(47512,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(44776,16,FLEN) +NAN_BOXED(44776,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(45328,16,FLEN) +NAN_BOXED(45328,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(43296,16,FLEN) +NAN_BOXED(43296,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(46808,16,FLEN) +NAN_BOXED(46808,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(44232,16,FLEN) +NAN_BOXED(44232,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(45872,16,FLEN) +NAN_BOXED(45872,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(8192,16,FLEN) +NAN_BOXED(8192,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(10232,16,FLEN) +NAN_BOXED(10232,16,FLEN) +NAN_BOXED(15360,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x11_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x11_1: + .fill 32*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x5_0: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_0: + .fill 218*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/feq_b1-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/feq_b1-01.S new file mode 100644 index 000000000..a679b9e72 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/feq_b1-01.S @@ -0,0 +1,4764 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 05:49:16 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_feq.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the feq.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the feq_b1 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",feq_b1) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x12,test_dataset_0) +RVTEST_SIGBASE(x22,signature_x22_1) + +inst_0:// rs1 == rs2, rs1==x14, rs2==x14, rd==x17,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x14; op2:x14; dest:x17; op1val:0x0; op2val:0x0; +valaddr_reg:x12; val_offset:0*FLEN/8; correctval:??; testreg:x11; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x17, x14, x14, 0, 0, x12, 0*FLEN/8, x15, x22, x11) + +inst_1:// rs1 != rs2, rs1==x5, rs2==x0, rd==x1,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x5; op2:x0; dest:x1; op1val:0x0; op2val:0x0; +valaddr_reg:x12; val_offset:2*FLEN/8; correctval:??; testreg:x11; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x1, x5, x0, 0, 0, x12, 2*FLEN/8, x15, x22, x11) + +inst_2:// rs1==x2, rs2==x16, rd==x8,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x2; op2:x16; dest:x8; op1val:0x0; op2val:0x1; +valaddr_reg:x12; val_offset:4*FLEN/8; correctval:??; testreg:x11; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x8, x2, x16, 0, 0, x12, 4*FLEN/8, x15, x22, x11) + +inst_3:// rs1==x6, rs2==x8, rd==x16,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x6; op2:x8; dest:x16; op1val:0x0; op2val:0x8001; +valaddr_reg:x12; val_offset:6*FLEN/8; correctval:??; testreg:x11; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x16, x6, x8, 0, 0, x12, 6*FLEN/8, x15, x22, x11) + +inst_4:// rs1==x25, rs2==x4, rd==x26,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x25; op2:x4; dest:x26; op1val:0x0; op2val:0x2; +valaddr_reg:x12; val_offset:8*FLEN/8; correctval:??; testreg:x11; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x26, x25, x4, 0, 0, x12, 8*FLEN/8, x15, x22, x11) + +inst_5:// rs1==x21, rs2==x25, rd==x18,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x21; op2:x25; dest:x18; op1val:0x0; op2val:0x83fe; +valaddr_reg:x12; val_offset:10*FLEN/8; correctval:??; testreg:x11; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x18, x21, x25, 0, 0, x12, 10*FLEN/8, x15, x22, x11) + +inst_6:// rs1==x0, rs2==x31, rd==x3,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x0; op2:x31; dest:x3; op1val:0x0; op2val:0x3ff; +valaddr_reg:x12; val_offset:12*FLEN/8; correctval:??; testreg:x11; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x3, x0, x31, 0, 0, x12, 12*FLEN/8, x15, x22, x11) + +inst_7:// rs1==x1, rs2==x28, rd==x7,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x1; op2:x28; dest:x7; op1val:0x0; op2val:0x83ff; +valaddr_reg:x12; val_offset:14*FLEN/8; correctval:??; testreg:x11; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x7, x1, x28, 0, 0, x12, 14*FLEN/8, x15, x22, x11) + +inst_8:// rs1==x8, rs2==x10, rd==x20,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x8; op2:x10; dest:x20; op1val:0x0; op2val:0x400; +valaddr_reg:x12; val_offset:16*FLEN/8; correctval:??; testreg:x11; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x20, x8, x10, 0, 0, x12, 16*FLEN/8, x15, x22, x11) + +inst_9:// rs1==x17, rs2==x19, rd==x13,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x17; op2:x19; dest:x13; op1val:0x0; op2val:0x8400; +valaddr_reg:x12; val_offset:18*FLEN/8; correctval:??; testreg:x11; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x13, x17, x19, 0, 0, x12, 18*FLEN/8, x15, x22, x11) + +inst_10:// rs1==x29, rs2==x9, rd==x4,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x29; op2:x9; dest:x4; op1val:0x0; op2val:0x401; +valaddr_reg:x12; val_offset:20*FLEN/8; correctval:??; testreg:x11; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x4, x29, x9, 0, 0, x12, 20*FLEN/8, x15, x22, x11) +RVTEST_VALBASEUPD(x7,test_dataset_1) + +inst_11:// rs1==x15, rs2==x18, rd==x25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x15; op2:x18; dest:x25; op1val:0x0; op2val:0x8455; +valaddr_reg:x7; val_offset:0*FLEN/8; correctval:??; testreg:x11; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x25, x15, x18, 0, 0, x7, 0*FLEN/8, x8, x22, x11) + +inst_12:// rs1==x4, rs2==x15, rd==x12,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x4; op2:x15; dest:x12; op1val:0x0; op2val:0x7bff; +valaddr_reg:x7; val_offset:2*FLEN/8; correctval:??; testreg:x11; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x12, x4, x15, 0, 0, x7, 2*FLEN/8, x8, x22, x11) + +inst_13:// rs1==x11, rs2==x2, rd==x0,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x11; op2:x2; dest:x0; op1val:0x0; op2val:0xfbff; +valaddr_reg:x7; val_offset:4*FLEN/8; correctval:??; testreg:x4; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x0, x11, x2, 0, 0, x7, 4*FLEN/8, x8, x22, x4) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_14:// rs1==x16, rs2==x26, rd==x27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x16; op2:x26; dest:x27; op1val:0x0; op2val:0x7c00; +valaddr_reg:x7; val_offset:6*FLEN/8; correctval:??; testreg:x4; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x27, x16, x26, 0, 0, x7, 6*FLEN/8, x8, x1, x4) + +inst_15:// rs1==x12, rs2==x21, rd==x5,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x12; op2:x21; dest:x5; op1val:0x0; op2val:0xfc00; +valaddr_reg:x7; val_offset:8*FLEN/8; correctval:??; testreg:x4; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x5, x12, x21, 0, 0, x7, 8*FLEN/8, x8, x1, x4) + +inst_16:// rs1==x27, rs2==x12, rd==x10,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x27; op2:x12; dest:x10; op1val:0x0; op2val:0x7e00; +valaddr_reg:x7; val_offset:10*FLEN/8; correctval:??; testreg:x4; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x10, x27, x12, 0, 0, x7, 10*FLEN/8, x8, x1, x4) + +inst_17:// rs1==x24, rs2==x30, rd==x29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x24; op2:x30; dest:x29; op1val:0x0; op2val:0xfe00; +valaddr_reg:x7; val_offset:12*FLEN/8; correctval:??; testreg:x4; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x29, x24, x30, 0, 0, x7, 12*FLEN/8, x8, x1, x4) + +inst_18:// rs1==x26, rs2==x13, rd==x6,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x26; op2:x13; dest:x6; op1val:0x0; op2val:0x7e01; +valaddr_reg:x7; val_offset:14*FLEN/8; correctval:??; testreg:x4; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x6, x26, x13, 0, 0, x7, 14*FLEN/8, x8, x1, x4) + +inst_19:// rs1==x22, rs2==x29, rd==x9,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x22; op2:x29; dest:x9; op1val:0x0; op2val:0xfe55; +valaddr_reg:x7; val_offset:16*FLEN/8; correctval:??; testreg:x4; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x9, x22, x29, 0, 0, x7, 16*FLEN/8, x8, x1, x4) + +inst_20:// rs1==x3, rs2==x20, rd==x11,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x3; op2:x20; dest:x11; op1val:0x0; op2val:0x7c01; +valaddr_reg:x7; val_offset:18*FLEN/8; correctval:??; testreg:x4; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x11, x3, x20, 0, 0, x7, 18*FLEN/8, x8, x1, x4) + +inst_21:// rs1==x9, rs2==x27, rd==x31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x9; op2:x27; dest:x31; op1val:0x0; op2val:0xfd55; +valaddr_reg:x7; val_offset:20*FLEN/8; correctval:??; testreg:x4; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x9, x27, 0, 0, x7, 20*FLEN/8, x8, x1, x4) + +inst_22:// rs1==x13, rs2==x23, rd==x15,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x13; op2:x23; dest:x15; op1val:0x0; op2val:0x3c00; +valaddr_reg:x7; val_offset:22*FLEN/8; correctval:??; testreg:x4; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x15, x13, x23, 0, 0, x7, 22*FLEN/8, x8, x1, x4) +RVTEST_VALBASEUPD(x8,test_dataset_2) + +inst_23:// rs1==x7, rs2==x17, rd==x2,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x7; op2:x17; dest:x2; op1val:0x0; op2val:0xbc00; +valaddr_reg:x8; val_offset:0*FLEN/8; correctval:??; testreg:x4; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x2, x7, x17, 0, 0, x8, 0*FLEN/8, x9, x1, x4) + +inst_24:// rs1==x30, rs2==x24, rd==x22,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x24; dest:x22; op1val:0x8000; op2val:0x0; +valaddr_reg:x8; val_offset:2*FLEN/8; correctval:??; testreg:x4; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x22, x30, x24, 0, 0, x8, 2*FLEN/8, x9, x1, x4) + +inst_25:// rs1==x28, rs2==x5, rd==x21,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x28; op2:x5; dest:x21; op1val:0x8000; op2val:0x8000; +valaddr_reg:x8; val_offset:4*FLEN/8; correctval:??; testreg:x4; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x21, x28, x5, 0, 0, x8, 4*FLEN/8, x9, x1, x4) + +inst_26:// rs1==x18, rs2==x3, rd==x24,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x18; op2:x3; dest:x24; op1val:0x8000; op2val:0x1; +valaddr_reg:x8; val_offset:6*FLEN/8; correctval:??; testreg:x4; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x24, x18, x3, 0, 0, x8, 6*FLEN/8, x9, x1, x4) + +inst_27:// rs1==x20, rs2==x7, rd==x14,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x20; op2:x7; dest:x14; op1val:0x8000; op2val:0x8001; +valaddr_reg:x8; val_offset:8*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x14, x20, x7, 0, 0, x8, 8*FLEN/8, x9, x1, x3) +RVTEST_SIGBASE(x2,signature_x2_0) + +inst_28:// rs1==x19, rs2==x11, rd==x23,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x19; op2:x11; dest:x23; op1val:0x8000; op2val:0x2; +valaddr_reg:x8; val_offset:10*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x23, x19, x11, 0, 0, x8, 10*FLEN/8, x9, x2, x3) + +inst_29:// rs1==x31, rs2==x6, rd==x19,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x31; op2:x6; dest:x19; op1val:0x8000; op2val:0x83fe; +valaddr_reg:x8; val_offset:12*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x19, x31, x6, 0, 0, x8, 12*FLEN/8, x9, x2, x3) + +inst_30:// rs1==x23, rs2==x22, rd==x28,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x23; op2:x22; dest:x28; op1val:0x8000; op2val:0x3ff; +valaddr_reg:x8; val_offset:14*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x28, x23, x22, 0, 0, x8, 14*FLEN/8, x9, x2, x3) + +inst_31:// rs1==x10, rs2==x1, rd==x30,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x10; op2:x1; dest:x30; op1val:0x8000; op2val:0x83ff; +valaddr_reg:x8; val_offset:16*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x30, x10, x1, 0, 0, x8, 16*FLEN/8, x9, x2, x3) + +inst_32:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x400; +valaddr_reg:x8; val_offset:18*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 18*FLEN/8, x9, x2, x3) + +inst_33:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8400; +valaddr_reg:x8; val_offset:20*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 20*FLEN/8, x9, x2, x3) + +inst_34:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x401; +valaddr_reg:x8; val_offset:22*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 22*FLEN/8, x9, x2, x3) + +inst_35:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8455; +valaddr_reg:x8; val_offset:24*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 24*FLEN/8, x9, x2, x3) + +inst_36:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x7bff; +valaddr_reg:x8; val_offset:26*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 26*FLEN/8, x9, x2, x3) + +inst_37:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xfbff; +valaddr_reg:x8; val_offset:28*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 28*FLEN/8, x9, x2, x3) + +inst_38:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x7c00; +valaddr_reg:x8; val_offset:30*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 30*FLEN/8, x9, x2, x3) + +inst_39:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xfc00; +valaddr_reg:x8; val_offset:32*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 32*FLEN/8, x9, x2, x3) + +inst_40:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x7e00; +valaddr_reg:x8; val_offset:34*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 34*FLEN/8, x9, x2, x3) + +inst_41:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xfe00; +valaddr_reg:x8; val_offset:36*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 36*FLEN/8, x9, x2, x3) + +inst_42:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x7e01; +valaddr_reg:x8; val_offset:38*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 38*FLEN/8, x9, x2, x3) + +inst_43:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xfe55; +valaddr_reg:x8; val_offset:40*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 40*FLEN/8, x9, x2, x3) + +inst_44:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x7c01; +valaddr_reg:x8; val_offset:42*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 42*FLEN/8, x9, x2, x3) + +inst_45:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xfd55; +valaddr_reg:x8; val_offset:44*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 44*FLEN/8, x9, x2, x3) + +inst_46:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x3c00; +valaddr_reg:x8; val_offset:46*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 46*FLEN/8, x9, x2, x3) + +inst_47:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xbc00; +valaddr_reg:x8; val_offset:48*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 48*FLEN/8, x9, x2, x3) + +inst_48:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x0; +valaddr_reg:x8; val_offset:50*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 50*FLEN/8, x9, x2, x3) + +inst_49:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x8000; +valaddr_reg:x8; val_offset:52*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 52*FLEN/8, x9, x2, x3) + +inst_50:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x1; +valaddr_reg:x8; val_offset:54*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 54*FLEN/8, x9, x2, x3) + +inst_51:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x8001; +valaddr_reg:x8; val_offset:56*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 56*FLEN/8, x9, x2, x3) + +inst_52:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x2; +valaddr_reg:x8; val_offset:58*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 58*FLEN/8, x9, x2, x3) + +inst_53:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x83fe; +valaddr_reg:x8; val_offset:60*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 60*FLEN/8, x9, x2, x3) + +inst_54:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x3ff; +valaddr_reg:x8; val_offset:62*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 62*FLEN/8, x9, x2, x3) + +inst_55:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x83ff; +valaddr_reg:x8; val_offset:64*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 64*FLEN/8, x9, x2, x3) + +inst_56:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x400; +valaddr_reg:x8; val_offset:66*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 66*FLEN/8, x9, x2, x3) + +inst_57:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x8400; +valaddr_reg:x8; val_offset:68*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 68*FLEN/8, x9, x2, x3) + +inst_58:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x401; +valaddr_reg:x8; val_offset:70*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 70*FLEN/8, x9, x2, x3) + +inst_59:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x8455; +valaddr_reg:x8; val_offset:72*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 72*FLEN/8, x9, x2, x3) + +inst_60:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7bff; +valaddr_reg:x8; val_offset:74*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 74*FLEN/8, x9, x2, x3) + +inst_61:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xfbff; +valaddr_reg:x8; val_offset:76*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 76*FLEN/8, x9, x2, x3) + +inst_62:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7c00; +valaddr_reg:x8; val_offset:78*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 78*FLEN/8, x9, x2, x3) + +inst_63:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xfc00; +valaddr_reg:x8; val_offset:80*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 80*FLEN/8, x9, x2, x3) + +inst_64:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7e00; +valaddr_reg:x8; val_offset:82*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 82*FLEN/8, x9, x2, x3) + +inst_65:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xfe00; +valaddr_reg:x8; val_offset:84*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 84*FLEN/8, x9, x2, x3) + +inst_66:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7e01; +valaddr_reg:x8; val_offset:86*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 86*FLEN/8, x9, x2, x3) + +inst_67:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xfe55; +valaddr_reg:x8; val_offset:88*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 88*FLEN/8, x9, x2, x3) + +inst_68:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7c01; +valaddr_reg:x8; val_offset:90*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 90*FLEN/8, x9, x2, x3) + +inst_69:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xfd55; +valaddr_reg:x8; val_offset:92*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 92*FLEN/8, x9, x2, x3) + +inst_70:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x3c00; +valaddr_reg:x8; val_offset:94*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 94*FLEN/8, x9, x2, x3) + +inst_71:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xbc00; +valaddr_reg:x8; val_offset:96*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 96*FLEN/8, x9, x2, x3) + +inst_72:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x0; +valaddr_reg:x8; val_offset:98*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 98*FLEN/8, x9, x2, x3) + +inst_73:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8000; +valaddr_reg:x8; val_offset:100*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 100*FLEN/8, x9, x2, x3) + +inst_74:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x1; +valaddr_reg:x8; val_offset:102*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 102*FLEN/8, x9, x2, x3) + +inst_75:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8001; +valaddr_reg:x8; val_offset:104*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 104*FLEN/8, x9, x2, x3) + +inst_76:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x2; +valaddr_reg:x8; val_offset:106*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 106*FLEN/8, x9, x2, x3) + +inst_77:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x83fe; +valaddr_reg:x8; val_offset:108*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 108*FLEN/8, x9, x2, x3) + +inst_78:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x3ff; +valaddr_reg:x8; val_offset:110*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 110*FLEN/8, x9, x2, x3) + +inst_79:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x83ff; +valaddr_reg:x8; val_offset:112*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 112*FLEN/8, x9, x2, x3) + +inst_80:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x400; +valaddr_reg:x8; val_offset:114*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 114*FLEN/8, x9, x2, x3) + +inst_81:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8400; +valaddr_reg:x8; val_offset:116*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 116*FLEN/8, x9, x2, x3) + +inst_82:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x401; +valaddr_reg:x8; val_offset:118*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 118*FLEN/8, x9, x2, x3) + +inst_83:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8455; +valaddr_reg:x8; val_offset:120*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 120*FLEN/8, x9, x2, x3) + +inst_84:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x7bff; +valaddr_reg:x8; val_offset:122*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 122*FLEN/8, x9, x2, x3) + +inst_85:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xfbff; +valaddr_reg:x8; val_offset:124*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 124*FLEN/8, x9, x2, x3) + +inst_86:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x7c00; +valaddr_reg:x8; val_offset:126*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 126*FLEN/8, x9, x2, x3) + +inst_87:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xfc00; +valaddr_reg:x8; val_offset:128*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 128*FLEN/8, x9, x2, x3) + +inst_88:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x7e00; +valaddr_reg:x8; val_offset:130*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 130*FLEN/8, x9, x2, x3) + +inst_89:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xfe00; +valaddr_reg:x8; val_offset:132*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 132*FLEN/8, x9, x2, x3) + +inst_90:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x7e01; +valaddr_reg:x8; val_offset:134*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 134*FLEN/8, x9, x2, x3) + +inst_91:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xfe55; +valaddr_reg:x8; val_offset:136*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 136*FLEN/8, x9, x2, x3) + +inst_92:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x7c01; +valaddr_reg:x8; val_offset:138*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 138*FLEN/8, x9, x2, x3) + +inst_93:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xfd55; +valaddr_reg:x8; val_offset:140*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 140*FLEN/8, x9, x2, x3) + +inst_94:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x3c00; +valaddr_reg:x8; val_offset:142*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 142*FLEN/8, x9, x2, x3) + +inst_95:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xbc00; +valaddr_reg:x8; val_offset:144*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 144*FLEN/8, x9, x2, x3) + +inst_96:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x0; +valaddr_reg:x8; val_offset:146*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 146*FLEN/8, x9, x2, x3) + +inst_97:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x8000; +valaddr_reg:x8; val_offset:148*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 148*FLEN/8, x9, x2, x3) + +inst_98:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x1; +valaddr_reg:x8; val_offset:150*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 150*FLEN/8, x9, x2, x3) + +inst_99:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x8001; +valaddr_reg:x8; val_offset:152*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 152*FLEN/8, x9, x2, x3) + +inst_100:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x2; +valaddr_reg:x8; val_offset:154*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 154*FLEN/8, x9, x2, x3) + +inst_101:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x83fe; +valaddr_reg:x8; val_offset:156*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 156*FLEN/8, x9, x2, x3) + +inst_102:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x3ff; +valaddr_reg:x8; val_offset:158*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 158*FLEN/8, x9, x2, x3) + +inst_103:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x83ff; +valaddr_reg:x8; val_offset:160*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 160*FLEN/8, x9, x2, x3) + +inst_104:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x400; +valaddr_reg:x8; val_offset:162*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 162*FLEN/8, x9, x2, x3) + +inst_105:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x8400; +valaddr_reg:x8; val_offset:164*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 164*FLEN/8, x9, x2, x3) + +inst_106:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x401; +valaddr_reg:x8; val_offset:166*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 166*FLEN/8, x9, x2, x3) + +inst_107:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x8455; +valaddr_reg:x8; val_offset:168*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 168*FLEN/8, x9, x2, x3) + +inst_108:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x7bff; +valaddr_reg:x8; val_offset:170*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 170*FLEN/8, x9, x2, x3) + +inst_109:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xfbff; +valaddr_reg:x8; val_offset:172*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 172*FLEN/8, x9, x2, x3) + +inst_110:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x7c00; +valaddr_reg:x8; val_offset:174*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 174*FLEN/8, x9, x2, x3) + +inst_111:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xfc00; +valaddr_reg:x8; val_offset:176*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 176*FLEN/8, x9, x2, x3) + +inst_112:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x7e00; +valaddr_reg:x8; val_offset:178*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 178*FLEN/8, x9, x2, x3) + +inst_113:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xfe00; +valaddr_reg:x8; val_offset:180*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 180*FLEN/8, x9, x2, x3) + +inst_114:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x7e01; +valaddr_reg:x8; val_offset:182*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 182*FLEN/8, x9, x2, x3) + +inst_115:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xfe55; +valaddr_reg:x8; val_offset:184*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 184*FLEN/8, x9, x2, x3) + +inst_116:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x7c01; +valaddr_reg:x8; val_offset:186*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 186*FLEN/8, x9, x2, x3) + +inst_117:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xfd55; +valaddr_reg:x8; val_offset:188*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 188*FLEN/8, x9, x2, x3) + +inst_118:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x3c00; +valaddr_reg:x8; val_offset:190*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 190*FLEN/8, x9, x2, x3) + +inst_119:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xbc00; +valaddr_reg:x8; val_offset:192*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 192*FLEN/8, x9, x2, x3) + +inst_120:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x0; +valaddr_reg:x8; val_offset:194*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 194*FLEN/8, x9, x2, x3) + +inst_121:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x8000; +valaddr_reg:x8; val_offset:196*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 196*FLEN/8, x9, x2, x3) + +inst_122:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x1; +valaddr_reg:x8; val_offset:198*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 198*FLEN/8, x9, x2, x3) + +inst_123:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x8001; +valaddr_reg:x8; val_offset:200*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 200*FLEN/8, x9, x2, x3) + +inst_124:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x2; +valaddr_reg:x8; val_offset:202*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 202*FLEN/8, x9, x2, x3) + +inst_125:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x83fe; +valaddr_reg:x8; val_offset:204*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 204*FLEN/8, x9, x2, x3) + +inst_126:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x3ff; +valaddr_reg:x8; val_offset:206*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 206*FLEN/8, x9, x2, x3) + +inst_127:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x83ff; +valaddr_reg:x8; val_offset:208*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 208*FLEN/8, x9, x2, x3) + +inst_128:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x400; +valaddr_reg:x8; val_offset:210*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 210*FLEN/8, x9, x2, x3) + +inst_129:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x8400; +valaddr_reg:x8; val_offset:212*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 212*FLEN/8, x9, x2, x3) + +inst_130:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x401; +valaddr_reg:x8; val_offset:214*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 214*FLEN/8, x9, x2, x3) + +inst_131:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x8455; +valaddr_reg:x8; val_offset:216*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 216*FLEN/8, x9, x2, x3) + +inst_132:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x7bff; +valaddr_reg:x8; val_offset:218*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 218*FLEN/8, x9, x2, x3) + +inst_133:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xfbff; +valaddr_reg:x8; val_offset:220*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 220*FLEN/8, x9, x2, x3) + +inst_134:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x7c00; +valaddr_reg:x8; val_offset:222*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 222*FLEN/8, x9, x2, x3) + +inst_135:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xfc00; +valaddr_reg:x8; val_offset:224*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 224*FLEN/8, x9, x2, x3) + +inst_136:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x7e00; +valaddr_reg:x8; val_offset:226*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 226*FLEN/8, x9, x2, x3) + +inst_137:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xfe00; +valaddr_reg:x8; val_offset:228*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 228*FLEN/8, x9, x2, x3) + +inst_138:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x7e01; +valaddr_reg:x8; val_offset:230*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 230*FLEN/8, x9, x2, x3) + +inst_139:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xfe55; +valaddr_reg:x8; val_offset:232*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 232*FLEN/8, x9, x2, x3) + +inst_140:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x7c01; +valaddr_reg:x8; val_offset:234*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 234*FLEN/8, x9, x2, x3) + +inst_141:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xfd55; +valaddr_reg:x8; val_offset:236*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 236*FLEN/8, x9, x2, x3) + +inst_142:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x3c00; +valaddr_reg:x8; val_offset:238*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 238*FLEN/8, x9, x2, x3) + +inst_143:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xbc00; +valaddr_reg:x8; val_offset:240*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 240*FLEN/8, x9, x2, x3) + +inst_144:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x0; +valaddr_reg:x8; val_offset:242*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 242*FLEN/8, x9, x2, x3) + +inst_145:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x8000; +valaddr_reg:x8; val_offset:244*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 244*FLEN/8, x9, x2, x3) + +inst_146:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x1; +valaddr_reg:x8; val_offset:246*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 246*FLEN/8, x9, x2, x3) + +inst_147:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x8001; +valaddr_reg:x8; val_offset:248*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 248*FLEN/8, x9, x2, x3) + +inst_148:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x2; +valaddr_reg:x8; val_offset:250*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 250*FLEN/8, x9, x2, x3) + +inst_149:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x83fe; +valaddr_reg:x8; val_offset:252*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 252*FLEN/8, x9, x2, x3) + +inst_150:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x3ff; +valaddr_reg:x8; val_offset:254*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 254*FLEN/8, x9, x2, x3) + +inst_151:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x83ff; +valaddr_reg:x8; val_offset:256*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 256*FLEN/8, x9, x2, x3) + +inst_152:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x400; +valaddr_reg:x8; val_offset:258*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 258*FLEN/8, x9, x2, x3) + +inst_153:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x8400; +valaddr_reg:x8; val_offset:260*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 260*FLEN/8, x9, x2, x3) + +inst_154:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x401; +valaddr_reg:x8; val_offset:262*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 262*FLEN/8, x9, x2, x3) + +inst_155:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x8455; +valaddr_reg:x8; val_offset:264*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 264*FLEN/8, x9, x2, x3) +RVTEST_SIGBASE(x2,signature_x2_1) + +inst_156:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7bff; +valaddr_reg:x8; val_offset:266*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 266*FLEN/8, x9, x2, x3) + +inst_157:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xfbff; +valaddr_reg:x8; val_offset:268*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 268*FLEN/8, x9, x2, x3) + +inst_158:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7c00; +valaddr_reg:x8; val_offset:270*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 270*FLEN/8, x9, x2, x3) + +inst_159:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xfc00; +valaddr_reg:x8; val_offset:272*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 272*FLEN/8, x9, x2, x3) + +inst_160:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7e00; +valaddr_reg:x8; val_offset:274*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 274*FLEN/8, x9, x2, x3) + +inst_161:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xfe00; +valaddr_reg:x8; val_offset:276*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 276*FLEN/8, x9, x2, x3) + +inst_162:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7e01; +valaddr_reg:x8; val_offset:278*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 278*FLEN/8, x9, x2, x3) + +inst_163:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xfe55; +valaddr_reg:x8; val_offset:280*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 280*FLEN/8, x9, x2, x3) + +inst_164:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7c01; +valaddr_reg:x8; val_offset:282*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 282*FLEN/8, x9, x2, x3) + +inst_165:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xfd55; +valaddr_reg:x8; val_offset:284*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 284*FLEN/8, x9, x2, x3) + +inst_166:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x3c00; +valaddr_reg:x8; val_offset:286*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 286*FLEN/8, x9, x2, x3) + +inst_167:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xbc00; +valaddr_reg:x8; val_offset:288*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 288*FLEN/8, x9, x2, x3) + +inst_168:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x0; +valaddr_reg:x8; val_offset:290*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 290*FLEN/8, x9, x2, x3) + +inst_169:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8000; +valaddr_reg:x8; val_offset:292*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 292*FLEN/8, x9, x2, x3) + +inst_170:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x1; +valaddr_reg:x8; val_offset:294*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 294*FLEN/8, x9, x2, x3) + +inst_171:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8001; +valaddr_reg:x8; val_offset:296*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 296*FLEN/8, x9, x2, x3) + +inst_172:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x2; +valaddr_reg:x8; val_offset:298*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 298*FLEN/8, x9, x2, x3) + +inst_173:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x83fe; +valaddr_reg:x8; val_offset:300*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 300*FLEN/8, x9, x2, x3) + +inst_174:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x3ff; +valaddr_reg:x8; val_offset:302*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 302*FLEN/8, x9, x2, x3) + +inst_175:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x83ff; +valaddr_reg:x8; val_offset:304*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 304*FLEN/8, x9, x2, x3) + +inst_176:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x400; +valaddr_reg:x8; val_offset:306*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 306*FLEN/8, x9, x2, x3) + +inst_177:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8400; +valaddr_reg:x8; val_offset:308*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 308*FLEN/8, x9, x2, x3) + +inst_178:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x401; +valaddr_reg:x8; val_offset:310*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 310*FLEN/8, x9, x2, x3) + +inst_179:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8455; +valaddr_reg:x8; val_offset:312*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 312*FLEN/8, x9, x2, x3) + +inst_180:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x7bff; +valaddr_reg:x8; val_offset:314*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 314*FLEN/8, x9, x2, x3) + +inst_181:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xfbff; +valaddr_reg:x8; val_offset:316*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 316*FLEN/8, x9, x2, x3) + +inst_182:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x7c00; +valaddr_reg:x8; val_offset:318*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 318*FLEN/8, x9, x2, x3) + +inst_183:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xfc00; +valaddr_reg:x8; val_offset:320*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 320*FLEN/8, x9, x2, x3) + +inst_184:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x7e00; +valaddr_reg:x8; val_offset:322*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 322*FLEN/8, x9, x2, x3) + +inst_185:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xfe00; +valaddr_reg:x8; val_offset:324*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 324*FLEN/8, x9, x2, x3) + +inst_186:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x7e01; +valaddr_reg:x8; val_offset:326*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 326*FLEN/8, x9, x2, x3) + +inst_187:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xfe55; +valaddr_reg:x8; val_offset:328*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 328*FLEN/8, x9, x2, x3) + +inst_188:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x7c01; +valaddr_reg:x8; val_offset:330*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 330*FLEN/8, x9, x2, x3) + +inst_189:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xfd55; +valaddr_reg:x8; val_offset:332*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 332*FLEN/8, x9, x2, x3) + +inst_190:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x3c00; +valaddr_reg:x8; val_offset:334*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 334*FLEN/8, x9, x2, x3) + +inst_191:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xbc00; +valaddr_reg:x8; val_offset:336*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 336*FLEN/8, x9, x2, x3) + +inst_192:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x0; +valaddr_reg:x8; val_offset:338*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 338*FLEN/8, x9, x2, x3) + +inst_193:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x8000; +valaddr_reg:x8; val_offset:340*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 340*FLEN/8, x9, x2, x3) + +inst_194:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x1; +valaddr_reg:x8; val_offset:342*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 342*FLEN/8, x9, x2, x3) + +inst_195:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x8001; +valaddr_reg:x8; val_offset:344*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 344*FLEN/8, x9, x2, x3) + +inst_196:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x2; +valaddr_reg:x8; val_offset:346*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 346*FLEN/8, x9, x2, x3) + +inst_197:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x83fe; +valaddr_reg:x8; val_offset:348*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 348*FLEN/8, x9, x2, x3) + +inst_198:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x3ff; +valaddr_reg:x8; val_offset:350*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 350*FLEN/8, x9, x2, x3) + +inst_199:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x83ff; +valaddr_reg:x8; val_offset:352*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 352*FLEN/8, x9, x2, x3) + +inst_200:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x400; +valaddr_reg:x8; val_offset:354*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 354*FLEN/8, x9, x2, x3) + +inst_201:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x8400; +valaddr_reg:x8; val_offset:356*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 356*FLEN/8, x9, x2, x3) + +inst_202:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x401; +valaddr_reg:x8; val_offset:358*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 358*FLEN/8, x9, x2, x3) + +inst_203:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x8455; +valaddr_reg:x8; val_offset:360*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 360*FLEN/8, x9, x2, x3) + +inst_204:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7bff; +valaddr_reg:x8; val_offset:362*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 362*FLEN/8, x9, x2, x3) + +inst_205:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xfbff; +valaddr_reg:x8; val_offset:364*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 364*FLEN/8, x9, x2, x3) + +inst_206:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7c00; +valaddr_reg:x8; val_offset:366*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 366*FLEN/8, x9, x2, x3) + +inst_207:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xfc00; +valaddr_reg:x8; val_offset:368*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 368*FLEN/8, x9, x2, x3) + +inst_208:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7e00; +valaddr_reg:x8; val_offset:370*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 370*FLEN/8, x9, x2, x3) + +inst_209:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xfe00; +valaddr_reg:x8; val_offset:372*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 372*FLEN/8, x9, x2, x3) + +inst_210:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7e01; +valaddr_reg:x8; val_offset:374*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 374*FLEN/8, x9, x2, x3) + +inst_211:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xfe55; +valaddr_reg:x8; val_offset:376*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 376*FLEN/8, x9, x2, x3) + +inst_212:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7c01; +valaddr_reg:x8; val_offset:378*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 378*FLEN/8, x9, x2, x3) + +inst_213:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xfd55; +valaddr_reg:x8; val_offset:380*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 380*FLEN/8, x9, x2, x3) + +inst_214:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x3c00; +valaddr_reg:x8; val_offset:382*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 382*FLEN/8, x9, x2, x3) + +inst_215:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xbc00; +valaddr_reg:x8; val_offset:384*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 384*FLEN/8, x9, x2, x3) + +inst_216:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x0; +valaddr_reg:x8; val_offset:386*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 386*FLEN/8, x9, x2, x3) + +inst_217:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8000; +valaddr_reg:x8; val_offset:388*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 388*FLEN/8, x9, x2, x3) + +inst_218:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x1; +valaddr_reg:x8; val_offset:390*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 390*FLEN/8, x9, x2, x3) + +inst_219:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8001; +valaddr_reg:x8; val_offset:392*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 392*FLEN/8, x9, x2, x3) + +inst_220:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x2; +valaddr_reg:x8; val_offset:394*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 394*FLEN/8, x9, x2, x3) + +inst_221:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x83fe; +valaddr_reg:x8; val_offset:396*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 396*FLEN/8, x9, x2, x3) + +inst_222:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x3ff; +valaddr_reg:x8; val_offset:398*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 398*FLEN/8, x9, x2, x3) + +inst_223:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x83ff; +valaddr_reg:x8; val_offset:400*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 400*FLEN/8, x9, x2, x3) + +inst_224:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x400; +valaddr_reg:x8; val_offset:402*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 402*FLEN/8, x9, x2, x3) + +inst_225:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8400; +valaddr_reg:x8; val_offset:404*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 404*FLEN/8, x9, x2, x3) + +inst_226:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x401; +valaddr_reg:x8; val_offset:406*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 406*FLEN/8, x9, x2, x3) + +inst_227:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8455; +valaddr_reg:x8; val_offset:408*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 408*FLEN/8, x9, x2, x3) + +inst_228:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x7bff; +valaddr_reg:x8; val_offset:410*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 410*FLEN/8, x9, x2, x3) + +inst_229:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xfbff; +valaddr_reg:x8; val_offset:412*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 412*FLEN/8, x9, x2, x3) + +inst_230:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x7c00; +valaddr_reg:x8; val_offset:414*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 414*FLEN/8, x9, x2, x3) + +inst_231:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xfc00; +valaddr_reg:x8; val_offset:416*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 416*FLEN/8, x9, x2, x3) + +inst_232:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x7e00; +valaddr_reg:x8; val_offset:418*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 418*FLEN/8, x9, x2, x3) + +inst_233:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xfe00; +valaddr_reg:x8; val_offset:420*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 420*FLEN/8, x9, x2, x3) + +inst_234:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x7e01; +valaddr_reg:x8; val_offset:422*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 422*FLEN/8, x9, x2, x3) + +inst_235:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xfe55; +valaddr_reg:x8; val_offset:424*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 424*FLEN/8, x9, x2, x3) + +inst_236:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x7c01; +valaddr_reg:x8; val_offset:426*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 426*FLEN/8, x9, x2, x3) + +inst_237:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xfd55; +valaddr_reg:x8; val_offset:428*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 428*FLEN/8, x9, x2, x3) + +inst_238:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x3c00; +valaddr_reg:x8; val_offset:430*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 430*FLEN/8, x9, x2, x3) + +inst_239:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xbc00; +valaddr_reg:x8; val_offset:432*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 432*FLEN/8, x9, x2, x3) + +inst_240:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x0; +valaddr_reg:x8; val_offset:434*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 434*FLEN/8, x9, x2, x3) + +inst_241:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x8000; +valaddr_reg:x8; val_offset:436*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 436*FLEN/8, x9, x2, x3) + +inst_242:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x1; +valaddr_reg:x8; val_offset:438*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 438*FLEN/8, x9, x2, x3) + +inst_243:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x8001; +valaddr_reg:x8; val_offset:440*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 440*FLEN/8, x9, x2, x3) + +inst_244:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x2; +valaddr_reg:x8; val_offset:442*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 442*FLEN/8, x9, x2, x3) + +inst_245:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x83fe; +valaddr_reg:x8; val_offset:444*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 444*FLEN/8, x9, x2, x3) + +inst_246:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x3ff; +valaddr_reg:x8; val_offset:446*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 446*FLEN/8, x9, x2, x3) + +inst_247:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x83ff; +valaddr_reg:x8; val_offset:448*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 448*FLEN/8, x9, x2, x3) + +inst_248:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x400; +valaddr_reg:x8; val_offset:450*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 450*FLEN/8, x9, x2, x3) + +inst_249:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x8400; +valaddr_reg:x8; val_offset:452*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 452*FLEN/8, x9, x2, x3) + +inst_250:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x401; +valaddr_reg:x8; val_offset:454*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 454*FLEN/8, x9, x2, x3) + +inst_251:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x8455; +valaddr_reg:x8; val_offset:456*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 456*FLEN/8, x9, x2, x3) + +inst_252:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x7bff; +valaddr_reg:x8; val_offset:458*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 458*FLEN/8, x9, x2, x3) + +inst_253:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xfbff; +valaddr_reg:x8; val_offset:460*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 460*FLEN/8, x9, x2, x3) + +inst_254:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x7c00; +valaddr_reg:x8; val_offset:462*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 462*FLEN/8, x9, x2, x3) + +inst_255:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xfc00; +valaddr_reg:x8; val_offset:464*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 464*FLEN/8, x9, x2, x3) + +inst_256:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x7e00; +valaddr_reg:x8; val_offset:466*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 466*FLEN/8, x9, x2, x3) + +inst_257:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xfe00; +valaddr_reg:x8; val_offset:468*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 468*FLEN/8, x9, x2, x3) + +inst_258:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x7e01; +valaddr_reg:x8; val_offset:470*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 470*FLEN/8, x9, x2, x3) + +inst_259:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xfe55; +valaddr_reg:x8; val_offset:472*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 472*FLEN/8, x9, x2, x3) + +inst_260:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x7c01; +valaddr_reg:x8; val_offset:474*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 474*FLEN/8, x9, x2, x3) + +inst_261:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xfd55; +valaddr_reg:x8; val_offset:476*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 476*FLEN/8, x9, x2, x3) + +inst_262:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x3c00; +valaddr_reg:x8; val_offset:478*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 478*FLEN/8, x9, x2, x3) + +inst_263:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xbc00; +valaddr_reg:x8; val_offset:480*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 480*FLEN/8, x9, x2, x3) + +inst_264:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x0; +valaddr_reg:x8; val_offset:482*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 482*FLEN/8, x9, x2, x3) + +inst_265:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x8000; +valaddr_reg:x8; val_offset:484*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 484*FLEN/8, x9, x2, x3) + +inst_266:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x1; +valaddr_reg:x8; val_offset:486*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 486*FLEN/8, x9, x2, x3) + +inst_267:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x8001; +valaddr_reg:x8; val_offset:488*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 488*FLEN/8, x9, x2, x3) + +inst_268:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x2; +valaddr_reg:x8; val_offset:490*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 490*FLEN/8, x9, x2, x3) + +inst_269:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x83fe; +valaddr_reg:x8; val_offset:492*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 492*FLEN/8, x9, x2, x3) + +inst_270:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x3ff; +valaddr_reg:x8; val_offset:494*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 494*FLEN/8, x9, x2, x3) + +inst_271:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x83ff; +valaddr_reg:x8; val_offset:496*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 496*FLEN/8, x9, x2, x3) + +inst_272:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x400; +valaddr_reg:x8; val_offset:498*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 498*FLEN/8, x9, x2, x3) + +inst_273:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x8400; +valaddr_reg:x8; val_offset:500*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 500*FLEN/8, x9, x2, x3) + +inst_274:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x401; +valaddr_reg:x8; val_offset:502*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 502*FLEN/8, x9, x2, x3) + +inst_275:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x8455; +valaddr_reg:x8; val_offset:504*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 504*FLEN/8, x9, x2, x3) + +inst_276:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x7bff; +valaddr_reg:x8; val_offset:506*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 506*FLEN/8, x9, x2, x3) + +inst_277:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xfbff; +valaddr_reg:x8; val_offset:508*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 508*FLEN/8, x9, x2, x3) + +inst_278:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x7c00; +valaddr_reg:x8; val_offset:510*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 510*FLEN/8, x9, x2, x3) + +inst_279:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xfc00; +valaddr_reg:x8; val_offset:512*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 512*FLEN/8, x9, x2, x3) + +inst_280:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x7e00; +valaddr_reg:x8; val_offset:514*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 514*FLEN/8, x9, x2, x3) + +inst_281:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xfe00; +valaddr_reg:x8; val_offset:516*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 516*FLEN/8, x9, x2, x3) + +inst_282:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x7e01; +valaddr_reg:x8; val_offset:518*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 518*FLEN/8, x9, x2, x3) + +inst_283:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xfe55; +valaddr_reg:x8; val_offset:520*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 520*FLEN/8, x9, x2, x3) +RVTEST_SIGBASE(x2,signature_x2_2) + +inst_284:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x7c01; +valaddr_reg:x8; val_offset:522*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 522*FLEN/8, x9, x2, x3) + +inst_285:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xfd55; +valaddr_reg:x8; val_offset:524*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 524*FLEN/8, x9, x2, x3) + +inst_286:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x3c00; +valaddr_reg:x8; val_offset:526*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 526*FLEN/8, x9, x2, x3) + +inst_287:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xbc00; +valaddr_reg:x8; val_offset:528*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 528*FLEN/8, x9, x2, x3) + +inst_288:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x0; +valaddr_reg:x8; val_offset:530*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 530*FLEN/8, x9, x2, x3) + +inst_289:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8000; +valaddr_reg:x8; val_offset:532*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 532*FLEN/8, x9, x2, x3) + +inst_290:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x1; +valaddr_reg:x8; val_offset:534*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 534*FLEN/8, x9, x2, x3) + +inst_291:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8001; +valaddr_reg:x8; val_offset:536*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 536*FLEN/8, x9, x2, x3) + +inst_292:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x2; +valaddr_reg:x8; val_offset:538*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 538*FLEN/8, x9, x2, x3) + +inst_293:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x83fe; +valaddr_reg:x8; val_offset:540*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 540*FLEN/8, x9, x2, x3) + +inst_294:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x3ff; +valaddr_reg:x8; val_offset:542*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 542*FLEN/8, x9, x2, x3) + +inst_295:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x83ff; +valaddr_reg:x8; val_offset:544*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 544*FLEN/8, x9, x2, x3) + +inst_296:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x400; +valaddr_reg:x8; val_offset:546*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 546*FLEN/8, x9, x2, x3) + +inst_297:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8400; +valaddr_reg:x8; val_offset:548*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 548*FLEN/8, x9, x2, x3) + +inst_298:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x401; +valaddr_reg:x8; val_offset:550*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 550*FLEN/8, x9, x2, x3) + +inst_299:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8455; +valaddr_reg:x8; val_offset:552*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 552*FLEN/8, x9, x2, x3) + +inst_300:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7bff; +valaddr_reg:x8; val_offset:554*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 554*FLEN/8, x9, x2, x3) + +inst_301:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xfbff; +valaddr_reg:x8; val_offset:556*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 556*FLEN/8, x9, x2, x3) + +inst_302:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7c00; +valaddr_reg:x8; val_offset:558*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 558*FLEN/8, x9, x2, x3) + +inst_303:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xfc00; +valaddr_reg:x8; val_offset:560*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 560*FLEN/8, x9, x2, x3) + +inst_304:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7e00; +valaddr_reg:x8; val_offset:562*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 562*FLEN/8, x9, x2, x3) + +inst_305:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xfe00; +valaddr_reg:x8; val_offset:564*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 564*FLEN/8, x9, x2, x3) + +inst_306:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7e01; +valaddr_reg:x8; val_offset:566*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 566*FLEN/8, x9, x2, x3) + +inst_307:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xfe55; +valaddr_reg:x8; val_offset:568*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 568*FLEN/8, x9, x2, x3) + +inst_308:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7c01; +valaddr_reg:x8; val_offset:570*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 570*FLEN/8, x9, x2, x3) + +inst_309:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xfd55; +valaddr_reg:x8; val_offset:572*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 572*FLEN/8, x9, x2, x3) + +inst_310:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x3c00; +valaddr_reg:x8; val_offset:574*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 574*FLEN/8, x9, x2, x3) + +inst_311:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xbc00; +valaddr_reg:x8; val_offset:576*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 576*FLEN/8, x9, x2, x3) + +inst_312:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x0; +valaddr_reg:x8; val_offset:578*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 578*FLEN/8, x9, x2, x3) + +inst_313:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8000; +valaddr_reg:x8; val_offset:580*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 580*FLEN/8, x9, x2, x3) + +inst_314:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x1; +valaddr_reg:x8; val_offset:582*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 582*FLEN/8, x9, x2, x3) + +inst_315:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8001; +valaddr_reg:x8; val_offset:584*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 584*FLEN/8, x9, x2, x3) + +inst_316:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x2; +valaddr_reg:x8; val_offset:586*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 586*FLEN/8, x9, x2, x3) + +inst_317:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x83fe; +valaddr_reg:x8; val_offset:588*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 588*FLEN/8, x9, x2, x3) + +inst_318:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x3ff; +valaddr_reg:x8; val_offset:590*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 590*FLEN/8, x9, x2, x3) + +inst_319:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x83ff; +valaddr_reg:x8; val_offset:592*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 592*FLEN/8, x9, x2, x3) + +inst_320:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x400; +valaddr_reg:x8; val_offset:594*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 594*FLEN/8, x9, x2, x3) + +inst_321:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8400; +valaddr_reg:x8; val_offset:596*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 596*FLEN/8, x9, x2, x3) + +inst_322:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x401; +valaddr_reg:x8; val_offset:598*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 598*FLEN/8, x9, x2, x3) + +inst_323:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8455; +valaddr_reg:x8; val_offset:600*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 600*FLEN/8, x9, x2, x3) + +inst_324:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7bff; +valaddr_reg:x8; val_offset:602*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 602*FLEN/8, x9, x2, x3) + +inst_325:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfbff; +valaddr_reg:x8; val_offset:604*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 604*FLEN/8, x9, x2, x3) + +inst_326:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7c00; +valaddr_reg:x8; val_offset:606*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 606*FLEN/8, x9, x2, x3) + +inst_327:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfc00; +valaddr_reg:x8; val_offset:608*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 608*FLEN/8, x9, x2, x3) + +inst_328:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7e00; +valaddr_reg:x8; val_offset:610*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 610*FLEN/8, x9, x2, x3) + +inst_329:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfe00; +valaddr_reg:x8; val_offset:612*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 612*FLEN/8, x9, x2, x3) + +inst_330:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7e01; +valaddr_reg:x8; val_offset:614*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 614*FLEN/8, x9, x2, x3) + +inst_331:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfe55; +valaddr_reg:x8; val_offset:616*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 616*FLEN/8, x9, x2, x3) + +inst_332:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7c01; +valaddr_reg:x8; val_offset:618*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 618*FLEN/8, x9, x2, x3) + +inst_333:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfd55; +valaddr_reg:x8; val_offset:620*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 620*FLEN/8, x9, x2, x3) + +inst_334:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x3c00; +valaddr_reg:x8; val_offset:622*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 622*FLEN/8, x9, x2, x3) + +inst_335:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xbc00; +valaddr_reg:x8; val_offset:624*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 624*FLEN/8, x9, x2, x3) + +inst_336:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x0; +valaddr_reg:x8; val_offset:626*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 626*FLEN/8, x9, x2, x3) + +inst_337:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x8000; +valaddr_reg:x8; val_offset:628*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 628*FLEN/8, x9, x2, x3) + +inst_338:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x1; +valaddr_reg:x8; val_offset:630*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 630*FLEN/8, x9, x2, x3) + +inst_339:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x8001; +valaddr_reg:x8; val_offset:632*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 632*FLEN/8, x9, x2, x3) + +inst_340:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x2; +valaddr_reg:x8; val_offset:634*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 634*FLEN/8, x9, x2, x3) + +inst_341:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x83fe; +valaddr_reg:x8; val_offset:636*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 636*FLEN/8, x9, x2, x3) + +inst_342:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x3ff; +valaddr_reg:x8; val_offset:638*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 638*FLEN/8, x9, x2, x3) + +inst_343:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x83ff; +valaddr_reg:x8; val_offset:640*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 640*FLEN/8, x9, x2, x3) + +inst_344:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x400; +valaddr_reg:x8; val_offset:642*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 642*FLEN/8, x9, x2, x3) + +inst_345:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x8400; +valaddr_reg:x8; val_offset:644*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 644*FLEN/8, x9, x2, x3) + +inst_346:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x401; +valaddr_reg:x8; val_offset:646*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 646*FLEN/8, x9, x2, x3) + +inst_347:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x8455; +valaddr_reg:x8; val_offset:648*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 648*FLEN/8, x9, x2, x3) + +inst_348:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x7bff; +valaddr_reg:x8; val_offset:650*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 650*FLEN/8, x9, x2, x3) + +inst_349:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xfbff; +valaddr_reg:x8; val_offset:652*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 652*FLEN/8, x9, x2, x3) + +inst_350:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x7c00; +valaddr_reg:x8; val_offset:654*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 654*FLEN/8, x9, x2, x3) + +inst_351:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xfc00; +valaddr_reg:x8; val_offset:656*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 656*FLEN/8, x9, x2, x3) + +inst_352:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x7e00; +valaddr_reg:x8; val_offset:658*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 658*FLEN/8, x9, x2, x3) + +inst_353:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xfe00; +valaddr_reg:x8; val_offset:660*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 660*FLEN/8, x9, x2, x3) + +inst_354:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x7e01; +valaddr_reg:x8; val_offset:662*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 662*FLEN/8, x9, x2, x3) + +inst_355:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xfe55; +valaddr_reg:x8; val_offset:664*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 664*FLEN/8, x9, x2, x3) + +inst_356:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x7c01; +valaddr_reg:x8; val_offset:666*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 666*FLEN/8, x9, x2, x3) + +inst_357:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xfd55; +valaddr_reg:x8; val_offset:668*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 668*FLEN/8, x9, x2, x3) + +inst_358:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x3c00; +valaddr_reg:x8; val_offset:670*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 670*FLEN/8, x9, x2, x3) + +inst_359:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xbc00; +valaddr_reg:x8; val_offset:672*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 672*FLEN/8, x9, x2, x3) + +inst_360:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x0; +valaddr_reg:x8; val_offset:674*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 674*FLEN/8, x9, x2, x3) + +inst_361:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x8000; +valaddr_reg:x8; val_offset:676*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 676*FLEN/8, x9, x2, x3) + +inst_362:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x1; +valaddr_reg:x8; val_offset:678*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 678*FLEN/8, x9, x2, x3) + +inst_363:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x8001; +valaddr_reg:x8; val_offset:680*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 680*FLEN/8, x9, x2, x3) + +inst_364:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x2; +valaddr_reg:x8; val_offset:682*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 682*FLEN/8, x9, x2, x3) + +inst_365:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x83fe; +valaddr_reg:x8; val_offset:684*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 684*FLEN/8, x9, x2, x3) + +inst_366:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x3ff; +valaddr_reg:x8; val_offset:686*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 686*FLEN/8, x9, x2, x3) + +inst_367:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x83ff; +valaddr_reg:x8; val_offset:688*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 688*FLEN/8, x9, x2, x3) + +inst_368:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x400; +valaddr_reg:x8; val_offset:690*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 690*FLEN/8, x9, x2, x3) + +inst_369:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x8400; +valaddr_reg:x8; val_offset:692*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 692*FLEN/8, x9, x2, x3) + +inst_370:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x401; +valaddr_reg:x8; val_offset:694*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 694*FLEN/8, x9, x2, x3) + +inst_371:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x8455; +valaddr_reg:x8; val_offset:696*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 696*FLEN/8, x9, x2, x3) + +inst_372:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x7bff; +valaddr_reg:x8; val_offset:698*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 698*FLEN/8, x9, x2, x3) + +inst_373:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xfbff; +valaddr_reg:x8; val_offset:700*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 700*FLEN/8, x9, x2, x3) + +inst_374:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x7c00; +valaddr_reg:x8; val_offset:702*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 702*FLEN/8, x9, x2, x3) + +inst_375:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xfc00; +valaddr_reg:x8; val_offset:704*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 704*FLEN/8, x9, x2, x3) + +inst_376:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x7e00; +valaddr_reg:x8; val_offset:706*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 706*FLEN/8, x9, x2, x3) + +inst_377:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xfe00; +valaddr_reg:x8; val_offset:708*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 708*FLEN/8, x9, x2, x3) + +inst_378:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x7e01; +valaddr_reg:x8; val_offset:710*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 710*FLEN/8, x9, x2, x3) + +inst_379:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xfe55; +valaddr_reg:x8; val_offset:712*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 712*FLEN/8, x9, x2, x3) + +inst_380:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x7c01; +valaddr_reg:x8; val_offset:714*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 714*FLEN/8, x9, x2, x3) + +inst_381:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xfd55; +valaddr_reg:x8; val_offset:716*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 716*FLEN/8, x9, x2, x3) + +inst_382:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x3c00; +valaddr_reg:x8; val_offset:718*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 718*FLEN/8, x9, x2, x3) + +inst_383:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xbc00; +valaddr_reg:x8; val_offset:720*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 720*FLEN/8, x9, x2, x3) + +inst_384:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x0; +valaddr_reg:x8; val_offset:722*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 722*FLEN/8, x9, x2, x3) + +inst_385:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x8000; +valaddr_reg:x8; val_offset:724*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 724*FLEN/8, x9, x2, x3) + +inst_386:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x1; +valaddr_reg:x8; val_offset:726*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 726*FLEN/8, x9, x2, x3) + +inst_387:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x8001; +valaddr_reg:x8; val_offset:728*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 728*FLEN/8, x9, x2, x3) + +inst_388:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x2; +valaddr_reg:x8; val_offset:730*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 730*FLEN/8, x9, x2, x3) + +inst_389:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x83fe; +valaddr_reg:x8; val_offset:732*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 732*FLEN/8, x9, x2, x3) + +inst_390:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x3ff; +valaddr_reg:x8; val_offset:734*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 734*FLEN/8, x9, x2, x3) + +inst_391:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x83ff; +valaddr_reg:x8; val_offset:736*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 736*FLEN/8, x9, x2, x3) + +inst_392:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x400; +valaddr_reg:x8; val_offset:738*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 738*FLEN/8, x9, x2, x3) + +inst_393:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x8400; +valaddr_reg:x8; val_offset:740*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 740*FLEN/8, x9, x2, x3) + +inst_394:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x401; +valaddr_reg:x8; val_offset:742*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 742*FLEN/8, x9, x2, x3) + +inst_395:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x8455; +valaddr_reg:x8; val_offset:744*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 744*FLEN/8, x9, x2, x3) + +inst_396:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x7bff; +valaddr_reg:x8; val_offset:746*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 746*FLEN/8, x9, x2, x3) + +inst_397:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xfbff; +valaddr_reg:x8; val_offset:748*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 748*FLEN/8, x9, x2, x3) + +inst_398:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x7c00; +valaddr_reg:x8; val_offset:750*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 750*FLEN/8, x9, x2, x3) + +inst_399:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xfc00; +valaddr_reg:x8; val_offset:752*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 752*FLEN/8, x9, x2, x3) + +inst_400:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x7e00; +valaddr_reg:x8; val_offset:754*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 754*FLEN/8, x9, x2, x3) + +inst_401:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xfe00; +valaddr_reg:x8; val_offset:756*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 756*FLEN/8, x9, x2, x3) + +inst_402:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x7e01; +valaddr_reg:x8; val_offset:758*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 758*FLEN/8, x9, x2, x3) + +inst_403:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xfe55; +valaddr_reg:x8; val_offset:760*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 760*FLEN/8, x9, x2, x3) + +inst_404:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x7c01; +valaddr_reg:x8; val_offset:762*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 762*FLEN/8, x9, x2, x3) + +inst_405:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xfd55; +valaddr_reg:x8; val_offset:764*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 764*FLEN/8, x9, x2, x3) + +inst_406:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x3c00; +valaddr_reg:x8; val_offset:766*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 766*FLEN/8, x9, x2, x3) + +inst_407:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xbc00; +valaddr_reg:x8; val_offset:768*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 768*FLEN/8, x9, x2, x3) + +inst_408:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x0; +valaddr_reg:x8; val_offset:770*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 770*FLEN/8, x9, x2, x3) + +inst_409:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x8000; +valaddr_reg:x8; val_offset:772*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 772*FLEN/8, x9, x2, x3) + +inst_410:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x1; +valaddr_reg:x8; val_offset:774*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 774*FLEN/8, x9, x2, x3) + +inst_411:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x8001; +valaddr_reg:x8; val_offset:776*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 776*FLEN/8, x9, x2, x3) +RVTEST_SIGBASE(x2,signature_x2_3) + +inst_412:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x2; +valaddr_reg:x8; val_offset:778*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 778*FLEN/8, x9, x2, x3) + +inst_413:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x83fe; +valaddr_reg:x8; val_offset:780*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 780*FLEN/8, x9, x2, x3) + +inst_414:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x3ff; +valaddr_reg:x8; val_offset:782*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 782*FLEN/8, x9, x2, x3) + +inst_415:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x83ff; +valaddr_reg:x8; val_offset:784*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 784*FLEN/8, x9, x2, x3) + +inst_416:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x400; +valaddr_reg:x8; val_offset:786*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 786*FLEN/8, x9, x2, x3) + +inst_417:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x8400; +valaddr_reg:x8; val_offset:788*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 788*FLEN/8, x9, x2, x3) + +inst_418:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x401; +valaddr_reg:x8; val_offset:790*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 790*FLEN/8, x9, x2, x3) + +inst_419:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x8455; +valaddr_reg:x8; val_offset:792*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 792*FLEN/8, x9, x2, x3) + +inst_420:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x7bff; +valaddr_reg:x8; val_offset:794*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 794*FLEN/8, x9, x2, x3) + +inst_421:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xfbff; +valaddr_reg:x8; val_offset:796*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 796*FLEN/8, x9, x2, x3) + +inst_422:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x7c00; +valaddr_reg:x8; val_offset:798*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 798*FLEN/8, x9, x2, x3) + +inst_423:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xfc00; +valaddr_reg:x8; val_offset:800*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 800*FLEN/8, x9, x2, x3) + +inst_424:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x7e00; +valaddr_reg:x8; val_offset:802*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 802*FLEN/8, x9, x2, x3) + +inst_425:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xfe00; +valaddr_reg:x8; val_offset:804*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 804*FLEN/8, x9, x2, x3) + +inst_426:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x7e01; +valaddr_reg:x8; val_offset:806*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 806*FLEN/8, x9, x2, x3) + +inst_427:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xfe55; +valaddr_reg:x8; val_offset:808*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 808*FLEN/8, x9, x2, x3) + +inst_428:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x7c01; +valaddr_reg:x8; val_offset:810*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 810*FLEN/8, x9, x2, x3) + +inst_429:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xfd55; +valaddr_reg:x8; val_offset:812*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 812*FLEN/8, x9, x2, x3) + +inst_430:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x3c00; +valaddr_reg:x8; val_offset:814*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 814*FLEN/8, x9, x2, x3) + +inst_431:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xbc00; +valaddr_reg:x8; val_offset:816*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 816*FLEN/8, x9, x2, x3) + +inst_432:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x0; +valaddr_reg:x8; val_offset:818*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 818*FLEN/8, x9, x2, x3) + +inst_433:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x8000; +valaddr_reg:x8; val_offset:820*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 820*FLEN/8, x9, x2, x3) + +inst_434:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x1; +valaddr_reg:x8; val_offset:822*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 822*FLEN/8, x9, x2, x3) + +inst_435:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x8001; +valaddr_reg:x8; val_offset:824*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 824*FLEN/8, x9, x2, x3) + +inst_436:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x2; +valaddr_reg:x8; val_offset:826*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 826*FLEN/8, x9, x2, x3) + +inst_437:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x83fe; +valaddr_reg:x8; val_offset:828*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 828*FLEN/8, x9, x2, x3) + +inst_438:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x3ff; +valaddr_reg:x8; val_offset:830*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 830*FLEN/8, x9, x2, x3) + +inst_439:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x83ff; +valaddr_reg:x8; val_offset:832*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 832*FLEN/8, x9, x2, x3) + +inst_440:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x400; +valaddr_reg:x8; val_offset:834*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 834*FLEN/8, x9, x2, x3) + +inst_441:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x8400; +valaddr_reg:x8; val_offset:836*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 836*FLEN/8, x9, x2, x3) + +inst_442:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x401; +valaddr_reg:x8; val_offset:838*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 838*FLEN/8, x9, x2, x3) + +inst_443:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x8455; +valaddr_reg:x8; val_offset:840*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 840*FLEN/8, x9, x2, x3) + +inst_444:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x7bff; +valaddr_reg:x8; val_offset:842*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 842*FLEN/8, x9, x2, x3) + +inst_445:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xfbff; +valaddr_reg:x8; val_offset:844*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 844*FLEN/8, x9, x2, x3) + +inst_446:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x7c00; +valaddr_reg:x8; val_offset:846*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 846*FLEN/8, x9, x2, x3) + +inst_447:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xfc00; +valaddr_reg:x8; val_offset:848*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 848*FLEN/8, x9, x2, x3) + +inst_448:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x7e00; +valaddr_reg:x8; val_offset:850*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 850*FLEN/8, x9, x2, x3) + +inst_449:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xfe00; +valaddr_reg:x8; val_offset:852*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 852*FLEN/8, x9, x2, x3) + +inst_450:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x7e01; +valaddr_reg:x8; val_offset:854*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 854*FLEN/8, x9, x2, x3) + +inst_451:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xfe55; +valaddr_reg:x8; val_offset:856*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 856*FLEN/8, x9, x2, x3) + +inst_452:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x7c01; +valaddr_reg:x8; val_offset:858*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 858*FLEN/8, x9, x2, x3) + +inst_453:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xfd55; +valaddr_reg:x8; val_offset:860*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 860*FLEN/8, x9, x2, x3) + +inst_454:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x3c00; +valaddr_reg:x8; val_offset:862*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 862*FLEN/8, x9, x2, x3) + +inst_455:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xbc00; +valaddr_reg:x8; val_offset:864*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 864*FLEN/8, x9, x2, x3) + +inst_456:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x0; +valaddr_reg:x8; val_offset:866*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 866*FLEN/8, x9, x2, x3) + +inst_457:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x8000; +valaddr_reg:x8; val_offset:868*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 868*FLEN/8, x9, x2, x3) + +inst_458:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x1; +valaddr_reg:x8; val_offset:870*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 870*FLEN/8, x9, x2, x3) + +inst_459:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x8001; +valaddr_reg:x8; val_offset:872*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 872*FLEN/8, x9, x2, x3) + +inst_460:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x2; +valaddr_reg:x8; val_offset:874*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 874*FLEN/8, x9, x2, x3) + +inst_461:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x83fe; +valaddr_reg:x8; val_offset:876*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 876*FLEN/8, x9, x2, x3) + +inst_462:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x3ff; +valaddr_reg:x8; val_offset:878*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 878*FLEN/8, x9, x2, x3) + +inst_463:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x83ff; +valaddr_reg:x8; val_offset:880*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 880*FLEN/8, x9, x2, x3) + +inst_464:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x400; +valaddr_reg:x8; val_offset:882*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 882*FLEN/8, x9, x2, x3) + +inst_465:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x8400; +valaddr_reg:x8; val_offset:884*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 884*FLEN/8, x9, x2, x3) + +inst_466:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x401; +valaddr_reg:x8; val_offset:886*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 886*FLEN/8, x9, x2, x3) + +inst_467:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x8455; +valaddr_reg:x8; val_offset:888*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 888*FLEN/8, x9, x2, x3) + +inst_468:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x7bff; +valaddr_reg:x8; val_offset:890*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 890*FLEN/8, x9, x2, x3) + +inst_469:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xfbff; +valaddr_reg:x8; val_offset:892*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 892*FLEN/8, x9, x2, x3) + +inst_470:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x7c00; +valaddr_reg:x8; val_offset:894*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 894*FLEN/8, x9, x2, x3) + +inst_471:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xfc00; +valaddr_reg:x8; val_offset:896*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 896*FLEN/8, x9, x2, x3) + +inst_472:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x7e00; +valaddr_reg:x8; val_offset:898*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 898*FLEN/8, x9, x2, x3) + +inst_473:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xfe00; +valaddr_reg:x8; val_offset:900*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 900*FLEN/8, x9, x2, x3) + +inst_474:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x7e01; +valaddr_reg:x8; val_offset:902*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 902*FLEN/8, x9, x2, x3) + +inst_475:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xfe55; +valaddr_reg:x8; val_offset:904*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 904*FLEN/8, x9, x2, x3) + +inst_476:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x7c01; +valaddr_reg:x8; val_offset:906*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 906*FLEN/8, x9, x2, x3) + +inst_477:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xfd55; +valaddr_reg:x8; val_offset:908*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 908*FLEN/8, x9, x2, x3) + +inst_478:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x3c00; +valaddr_reg:x8; val_offset:910*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 910*FLEN/8, x9, x2, x3) + +inst_479:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xbc00; +valaddr_reg:x8; val_offset:912*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 912*FLEN/8, x9, x2, x3) + +inst_480:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x0; +valaddr_reg:x8; val_offset:914*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 914*FLEN/8, x9, x2, x3) + +inst_481:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x8000; +valaddr_reg:x8; val_offset:916*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 916*FLEN/8, x9, x2, x3) + +inst_482:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x1; +valaddr_reg:x8; val_offset:918*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 918*FLEN/8, x9, x2, x3) + +inst_483:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x8001; +valaddr_reg:x8; val_offset:920*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 920*FLEN/8, x9, x2, x3) + +inst_484:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x2; +valaddr_reg:x8; val_offset:922*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 922*FLEN/8, x9, x2, x3) + +inst_485:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x83fe; +valaddr_reg:x8; val_offset:924*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 924*FLEN/8, x9, x2, x3) + +inst_486:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x3ff; +valaddr_reg:x8; val_offset:926*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 926*FLEN/8, x9, x2, x3) + +inst_487:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x83ff; +valaddr_reg:x8; val_offset:928*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 928*FLEN/8, x9, x2, x3) + +inst_488:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x400; +valaddr_reg:x8; val_offset:930*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 930*FLEN/8, x9, x2, x3) + +inst_489:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x8400; +valaddr_reg:x8; val_offset:932*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 932*FLEN/8, x9, x2, x3) + +inst_490:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x401; +valaddr_reg:x8; val_offset:934*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 934*FLEN/8, x9, x2, x3) + +inst_491:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x8455; +valaddr_reg:x8; val_offset:936*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 936*FLEN/8, x9, x2, x3) + +inst_492:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x7bff; +valaddr_reg:x8; val_offset:938*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 938*FLEN/8, x9, x2, x3) + +inst_493:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xfbff; +valaddr_reg:x8; val_offset:940*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 940*FLEN/8, x9, x2, x3) + +inst_494:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x7c00; +valaddr_reg:x8; val_offset:942*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 942*FLEN/8, x9, x2, x3) + +inst_495:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xfc00; +valaddr_reg:x8; val_offset:944*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 944*FLEN/8, x9, x2, x3) + +inst_496:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x7e00; +valaddr_reg:x8; val_offset:946*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 946*FLEN/8, x9, x2, x3) + +inst_497:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xfe00; +valaddr_reg:x8; val_offset:948*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 948*FLEN/8, x9, x2, x3) + +inst_498:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x7e01; +valaddr_reg:x8; val_offset:950*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 950*FLEN/8, x9, x2, x3) + +inst_499:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xfe55; +valaddr_reg:x8; val_offset:952*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 952*FLEN/8, x9, x2, x3) + +inst_500:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x7c01; +valaddr_reg:x8; val_offset:954*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 954*FLEN/8, x9, x2, x3) + +inst_501:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xfd55; +valaddr_reg:x8; val_offset:956*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 956*FLEN/8, x9, x2, x3) + +inst_502:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x3c00; +valaddr_reg:x8; val_offset:958*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 958*FLEN/8, x9, x2, x3) + +inst_503:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xbc00; +valaddr_reg:x8; val_offset:960*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 960*FLEN/8, x9, x2, x3) + +inst_504:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x0; +valaddr_reg:x8; val_offset:962*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 962*FLEN/8, x9, x2, x3) + +inst_505:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x8000; +valaddr_reg:x8; val_offset:964*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 964*FLEN/8, x9, x2, x3) + +inst_506:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x1; +valaddr_reg:x8; val_offset:966*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 966*FLEN/8, x9, x2, x3) + +inst_507:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x8001; +valaddr_reg:x8; val_offset:968*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 968*FLEN/8, x9, x2, x3) + +inst_508:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x2; +valaddr_reg:x8; val_offset:970*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 970*FLEN/8, x9, x2, x3) + +inst_509:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x83fe; +valaddr_reg:x8; val_offset:972*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 972*FLEN/8, x9, x2, x3) + +inst_510:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x3ff; +valaddr_reg:x8; val_offset:974*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 974*FLEN/8, x9, x2, x3) + +inst_511:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x83ff; +valaddr_reg:x8; val_offset:976*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 976*FLEN/8, x9, x2, x3) + +inst_512:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x400; +valaddr_reg:x8; val_offset:978*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 978*FLEN/8, x9, x2, x3) + +inst_513:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x8400; +valaddr_reg:x8; val_offset:980*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 980*FLEN/8, x9, x2, x3) + +inst_514:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x401; +valaddr_reg:x8; val_offset:982*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 982*FLEN/8, x9, x2, x3) + +inst_515:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x8455; +valaddr_reg:x8; val_offset:984*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 984*FLEN/8, x9, x2, x3) + +inst_516:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x7bff; +valaddr_reg:x8; val_offset:986*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 986*FLEN/8, x9, x2, x3) + +inst_517:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xfbff; +valaddr_reg:x8; val_offset:988*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 988*FLEN/8, x9, x2, x3) + +inst_518:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x7c00; +valaddr_reg:x8; val_offset:990*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 990*FLEN/8, x9, x2, x3) + +inst_519:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xfc00; +valaddr_reg:x8; val_offset:992*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 992*FLEN/8, x9, x2, x3) + +inst_520:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x7e00; +valaddr_reg:x8; val_offset:994*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 994*FLEN/8, x9, x2, x3) + +inst_521:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xfe00; +valaddr_reg:x8; val_offset:996*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 996*FLEN/8, x9, x2, x3) + +inst_522:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x7e01; +valaddr_reg:x8; val_offset:998*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 998*FLEN/8, x9, x2, x3) + +inst_523:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xfe55; +valaddr_reg:x8; val_offset:1000*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 1000*FLEN/8, x9, x2, x3) + +inst_524:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x7c01; +valaddr_reg:x8; val_offset:1002*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 1002*FLEN/8, x9, x2, x3) + +inst_525:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xfd55; +valaddr_reg:x8; val_offset:1004*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 1004*FLEN/8, x9, x2, x3) + +inst_526:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x3c00; +valaddr_reg:x8; val_offset:1006*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 1006*FLEN/8, x9, x2, x3) + +inst_527:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xbc00; +valaddr_reg:x8; val_offset:1008*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 1008*FLEN/8, x9, x2, x3) + +inst_528:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x0; +valaddr_reg:x8; val_offset:1010*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 1010*FLEN/8, x9, x2, x3) + +inst_529:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x8000; +valaddr_reg:x8; val_offset:1012*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 1012*FLEN/8, x9, x2, x3) + +inst_530:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x1; +valaddr_reg:x8; val_offset:1014*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 1014*FLEN/8, x9, x2, x3) + +inst_531:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x8001; +valaddr_reg:x8; val_offset:1016*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 1016*FLEN/8, x9, x2, x3) + +inst_532:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2; +valaddr_reg:x8; val_offset:1018*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 1018*FLEN/8, x9, x2, x3) + +inst_533:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x83fe; +valaddr_reg:x8; val_offset:1020*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 1020*FLEN/8, x9, x2, x3) + +inst_534:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3ff; +valaddr_reg:x8; val_offset:1022*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 1022*FLEN/8, x9, x2, x3) + +inst_535:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x83ff; +valaddr_reg:x8; val_offset:1024*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 1024*FLEN/8, x9, x2, x3) + +inst_536:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x400; +valaddr_reg:x8; val_offset:1026*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 1026*FLEN/8, x9, x2, x3) + +inst_537:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x8400; +valaddr_reg:x8; val_offset:1028*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 1028*FLEN/8, x9, x2, x3) + +inst_538:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x401; +valaddr_reg:x8; val_offset:1030*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 1030*FLEN/8, x9, x2, x3) + +inst_539:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x8455; +valaddr_reg:x8; val_offset:1032*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 1032*FLEN/8, x9, x2, x3) +RVTEST_SIGBASE(x2,signature_x2_4) + +inst_540:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7bff; +valaddr_reg:x8; val_offset:1034*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 1034*FLEN/8, x9, x2, x3) + +inst_541:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xfbff; +valaddr_reg:x8; val_offset:1036*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 1036*FLEN/8, x9, x2, x3) + +inst_542:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7c00; +valaddr_reg:x8; val_offset:1038*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 1038*FLEN/8, x9, x2, x3) + +inst_543:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xfc00; +valaddr_reg:x8; val_offset:1040*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 1040*FLEN/8, x9, x2, x3) + +inst_544:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7e00; +valaddr_reg:x8; val_offset:1042*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 1042*FLEN/8, x9, x2, x3) + +inst_545:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xfe00; +valaddr_reg:x8; val_offset:1044*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 1044*FLEN/8, x9, x2, x3) + +inst_546:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7e01; +valaddr_reg:x8; val_offset:1046*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 1046*FLEN/8, x9, x2, x3) + +inst_547:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xfe55; +valaddr_reg:x8; val_offset:1048*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 1048*FLEN/8, x9, x2, x3) + +inst_548:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7c01; +valaddr_reg:x8; val_offset:1050*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 1050*FLEN/8, x9, x2, x3) + +inst_549:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xfd55; +valaddr_reg:x8; val_offset:1052*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 1052*FLEN/8, x9, x2, x3) + +inst_550:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3c00; +valaddr_reg:x8; val_offset:1054*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 1054*FLEN/8, x9, x2, x3) + +inst_551:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xbc00; +valaddr_reg:x8; val_offset:1056*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 1056*FLEN/8, x9, x2, x3) + +inst_552:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x0; +valaddr_reg:x8; val_offset:1058*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 1058*FLEN/8, x9, x2, x3) + +inst_553:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x8000; +valaddr_reg:x8; val_offset:1060*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 1060*FLEN/8, x9, x2, x3) + +inst_554:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x1; +valaddr_reg:x8; val_offset:1062*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 1062*FLEN/8, x9, x2, x3) + +inst_555:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x8001; +valaddr_reg:x8; val_offset:1064*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 1064*FLEN/8, x9, x2, x3) + +inst_556:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x2; +valaddr_reg:x8; val_offset:1066*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 1066*FLEN/8, x9, x2, x3) + +inst_557:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x83fe; +valaddr_reg:x8; val_offset:1068*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 1068*FLEN/8, x9, x2, x3) + +inst_558:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x3ff; +valaddr_reg:x8; val_offset:1070*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 1070*FLEN/8, x9, x2, x3) + +inst_559:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x83ff; +valaddr_reg:x8; val_offset:1072*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 1072*FLEN/8, x9, x2, x3) + +inst_560:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x400; +valaddr_reg:x8; val_offset:1074*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 1074*FLEN/8, x9, x2, x3) + +inst_561:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x8400; +valaddr_reg:x8; val_offset:1076*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 1076*FLEN/8, x9, x2, x3) + +inst_562:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x401; +valaddr_reg:x8; val_offset:1078*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 1078*FLEN/8, x9, x2, x3) + +inst_563:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x8455; +valaddr_reg:x8; val_offset:1080*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 1080*FLEN/8, x9, x2, x3) + +inst_564:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x7bff; +valaddr_reg:x8; val_offset:1082*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 1082*FLEN/8, x9, x2, x3) + +inst_565:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xfbff; +valaddr_reg:x8; val_offset:1084*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 1084*FLEN/8, x9, x2, x3) + +inst_566:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x7c00; +valaddr_reg:x8; val_offset:1086*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 1086*FLEN/8, x9, x2, x3) + +inst_567:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xfc00; +valaddr_reg:x8; val_offset:1088*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 1088*FLEN/8, x9, x2, x3) + +inst_568:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x7e00; +valaddr_reg:x8; val_offset:1090*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 1090*FLEN/8, x9, x2, x3) + +inst_569:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xfe00; +valaddr_reg:x8; val_offset:1092*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 1092*FLEN/8, x9, x2, x3) + +inst_570:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x7e01; +valaddr_reg:x8; val_offset:1094*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 1094*FLEN/8, x9, x2, x3) + +inst_571:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xfe55; +valaddr_reg:x8; val_offset:1096*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 1096*FLEN/8, x9, x2, x3) + +inst_572:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x7c01; +valaddr_reg:x8; val_offset:1098*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 1098*FLEN/8, x9, x2, x3) + +inst_573:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xfd55; +valaddr_reg:x8; val_offset:1100*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 1100*FLEN/8, x9, x2, x3) + +inst_574:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x3c00; +valaddr_reg:x8; val_offset:1102*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 1102*FLEN/8, x9, x2, x3) + +inst_575:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbc00; +valaddr_reg:x8; val_offset:1104*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 1104*FLEN/8, x9, x2, x3) + +inst_576:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x0; +valaddr_reg:x8; val_offset:1106*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 1106*FLEN/8, x9, x2, x3) + +inst_577:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x8000; +valaddr_reg:x8; val_offset:1108*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 1108*FLEN/8, x9, x2, x3) + +inst_578:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x3ff; +valaddr_reg:x8; val_offset:1110*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 1110*FLEN/8, x9, x2, x3) + +inst_579:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xfbff; +valaddr_reg:x8; val_offset:1112*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x8, 1112*FLEN/8, x9, x2, x3) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(1,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(2,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(1023,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(1024,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(1025,32,FLEN) +test_dataset_1: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31744,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32256,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32257,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31745,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(15360,32,FLEN) +test_dataset_2: +NAN_BOXED(0,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(64511,16,FLEN) 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+NAN_BOXED(32769,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(2,16,FLEN) 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+NAN_BOXED(15360,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x22_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x22_1: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_0: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_0: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_1: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_2: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_3: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_4: + .fill 80*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/feq_b19-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/feq_b19-01.S new file mode 100644 index 000000000..741d1c83b --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/feq_b19-01.S @@ -0,0 +1,8688 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 05:49:16 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_feq.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the feq.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the feq_b19 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",feq_b19) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x16,test_dataset_0) +RVTEST_SIGBASE(x3,signature_x3_1) + +inst_0:// rs1 == rs2, rs1==x10, rs2==x10, rd==x11,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x10; op2:x10; dest:x11; op1val:0x739c; op2val:0x739c; +valaddr_reg:x16; val_offset:0*FLEN/8; correctval:??; testreg:x6; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x11, x10, x10, 0, 0, x16, 0*FLEN/8, x18, x3, x6) + +inst_1:// rs1 != rs2, rs1==x4, rs2==x25, rd==x10,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x100 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x4; op2:x25; dest:x10; op1val:0x739c; op2val:0x7900; +valaddr_reg:x16; val_offset:2*FLEN/8; correctval:??; testreg:x6; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x10, x4, x25, 0, 0, x16, 2*FLEN/8, x18, x3, x6) + +inst_2:// rs1==x28, rs2==x17, rd==x14,fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x28; op2:x17; dest:x14; op1val:0x7900; op2val:0x739c; +valaddr_reg:x16; val_offset:4*FLEN/8; correctval:??; testreg:x6; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x14, x28, x17, 0, 0, x16, 4*FLEN/8, x18, x3, x6) + +inst_3:// rs1==x2, rs2==x23, rd==x19,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1d and fm2 == 0x025 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x2; op2:x23; dest:x19; op1val:0x739c; op2val:0x7425; +valaddr_reg:x16; val_offset:6*FLEN/8; correctval:??; testreg:x6; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x19, x2, x23, 0, 0, x16, 6*FLEN/8, x18, x3, x6) + +inst_4:// rs1==x11, rs2==x15, rd==x25,fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x11; op2:x15; dest:x25; op1val:0x7425; op2val:0x739c; +valaddr_reg:x16; val_offset:8*FLEN/8; correctval:??; testreg:x6; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x25, x11, x15, 0, 0, x16, 8*FLEN/8, x18, x3, x6) + +inst_5:// rs1==x5, rs2==x11, rd==x13,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x5; op2:x11; dest:x13; op1val:0x739c; op2val:0x7ab0; +valaddr_reg:x16; val_offset:10*FLEN/8; correctval:??; testreg:x6; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x13, x5, x11, 0, 0, x16, 10*FLEN/8, x18, x3, x6) + +inst_6:// rs1==x7, rs2==x27, rd==x5,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x7; op2:x27; dest:x5; op1val:0x7ab0; op2val:0x739c; +valaddr_reg:x16; val_offset:12*FLEN/8; correctval:??; testreg:x6; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x5, x7, x27, 0, 0, x16, 12*FLEN/8, x18, x3, x6) + +inst_7:// rs1==x1, rs2==x13, rd==x8,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x1; op2:x13; dest:x8; op1val:0x739c; op2val:0x7913; +valaddr_reg:x16; val_offset:14*FLEN/8; correctval:??; testreg:x6; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x8, x1, x13, 0, 0, x16, 14*FLEN/8, x18, x3, x6) + +inst_8:// rs1==x19, rs2==x26, rd==x28,fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x19; op2:x26; dest:x28; op1val:0x7913; op2val:0x739c; +valaddr_reg:x16; val_offset:16*FLEN/8; correctval:??; testreg:x6; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x28, x19, x26, 0, 0, x16, 16*FLEN/8, x18, x3, x6) + +inst_9:// rs1==x9, rs2==x0, rd==x30,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 1 and fe2 == 0x1d and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x9; op2:x0; dest:x30; op1val:0x739c; op2val:0x0; +valaddr_reg:x16; val_offset:18*FLEN/8; correctval:??; testreg:x6; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x30, x9, x0, 0, 0, x16, 18*FLEN/8, x18, x3, x6) + +inst_10:// rs1==x13, rs2==x8, rd==x26,fs1 == 1 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x13; op2:x8; dest:x26; op1val:0xf749; op2val:0x739c; +valaddr_reg:x16; val_offset:20*FLEN/8; correctval:??; testreg:x6; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x26, x13, x8, 0, 0, x16, 20*FLEN/8, x18, x3, x6) + +inst_11:// rs1==x23, rs2==x5, rd==x31,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x378 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x23; op2:x5; dest:x31; op1val:0x739c; op2val:0xfb78; +valaddr_reg:x16; val_offset:22*FLEN/8; correctval:??; testreg:x6; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x23, x5, 0, 0, x16, 22*FLEN/8, x18, x3, x6) + +inst_12:// rs1==x14, rs2==x12, rd==x29,fs1 == 1 and fe1 == 0x1e and fm1 == 0x378 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x14; op2:x12; dest:x29; op1val:0xfb78; op2val:0x739c; +valaddr_reg:x16; val_offset:24*FLEN/8; correctval:??; testreg:x6; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x29, x14, x12, 0, 0, x16, 24*FLEN/8, x18, x3, x6) +RVTEST_VALBASEUPD(x1,test_dataset_1) + +inst_13:// rs1==x21, rs2==x18, rd==x20,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x21f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x21; op2:x18; dest:x20; op1val:0x739c; op2val:0xfa1f; +valaddr_reg:x1; val_offset:0*FLEN/8; correctval:??; testreg:x6; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x20, x21, x18, 0, 0, x1, 0*FLEN/8, x11, x3, x6) +RVTEST_SIGBASE(x5,signature_x5_0) + +inst_14:// rs1==x29, rs2==x20, rd==x16,fs1 == 1 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x29; op2:x20; dest:x16; op1val:0xfa1f; op2val:0x739c; +valaddr_reg:x1; val_offset:2*FLEN/8; correctval:??; testreg:x10; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x16, x29, x20, 0, 0, x1, 2*FLEN/8, x11, x5, x10) + +inst_15:// rs1==x27, rs2==x6, rd==x21,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x27; op2:x6; dest:x21; op1val:0x739c; op2val:0xf82f; +valaddr_reg:x1; val_offset:4*FLEN/8; correctval:??; testreg:x10; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x21, x27, x6, 0, 0, x1, 4*FLEN/8, x11, x5, x10) + +inst_16:// rs1==x24, rs2==x4, rd==x18,fs1 == 1 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x24; op2:x4; dest:x18; op1val:0xf82f; op2val:0x739c; +valaddr_reg:x1; val_offset:6*FLEN/8; correctval:??; testreg:x10; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x18, x24, x4, 0, 0, x1, 6*FLEN/8, x11, x5, x10) + +inst_17:// rs1==x18, rs2==x9, rd==x2,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x18; op2:x9; dest:x2; op1val:0x739c; op2val:0xf038; +valaddr_reg:x1; val_offset:8*FLEN/8; correctval:??; testreg:x10; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x2, x18, x9, 0, 0, x1, 8*FLEN/8, x11, x5, x10) + +inst_18:// rs1==x8, rs2==x16, rd==x12,fs1 == 0 and fe1 == 0x19 and fm1 == 0x216 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x8; op2:x16; dest:x12; op1val:0x6616; op2val:0xfbff; +valaddr_reg:x1; val_offset:10*FLEN/8; correctval:??; testreg:x10; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x12, x8, x16, 0, 0, x1, 10*FLEN/8, x11, x5, x10) + +inst_19:// rs1==x25, rs2==x7, rd==x15,fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x19 and fm2 == 0x216 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x25; op2:x7; dest:x15; op1val:0xfbff; op2val:0x6616; +valaddr_reg:x1; val_offset:12*FLEN/8; correctval:??; testreg:x10; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x15, x25, x7, 0, 0, x1, 12*FLEN/8, x11, x5, x10) + +inst_20:// rs1==x30, rs2==x3, rd==x24,fs1 == 0 and fe1 == 0x19 and fm1 == 0x216 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x3; dest:x24; op1val:0x6616; op2val:0xf038; +valaddr_reg:x1; val_offset:14*FLEN/8; correctval:??; testreg:x10; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x24, x30, x3, 0, 0, x1, 14*FLEN/8, x11, x5, x10) + +inst_21:// rs1==x22, rs2==x30, rd==x3,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x19 and fm2 == 0x216 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x22; op2:x30; dest:x3; op1val:0x739c; op2val:0x6616; +valaddr_reg:x1; val_offset:16*FLEN/8; correctval:??; testreg:x10; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x3, x22, x30, 0, 0, x1, 16*FLEN/8, x11, x5, x10) + +inst_22:// rs1==x12, rs2==x29, rd==x22,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x12; op2:x29; dest:x22; op1val:0x739c; op2val:0x17b; +valaddr_reg:x1; val_offset:18*FLEN/8; correctval:??; testreg:x10; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x22, x12, x29, 0, 0, x1, 18*FLEN/8, x11, x5, x10) + +inst_23:// rs1==x26, rs2==x19, rd==x27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x105 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x184 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x26; op2:x19; dest:x27; op1val:0x105; op2val:0x7584; +valaddr_reg:x1; val_offset:20*FLEN/8; correctval:??; testreg:x10; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x27, x26, x19, 0, 0, x1, 20*FLEN/8, x11, x5, x10) + +inst_24:// rs1==x15, rs2==x14, rd==x4,fs1 == 0 and fe1 == 0x1d and fm1 == 0x184 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x105 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x15; op2:x14; dest:x4; op1val:0x7584; op2val:0x105; +valaddr_reg:x1; val_offset:22*FLEN/8; correctval:??; testreg:x10; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x4, x15, x14, 0, 0, x1, 22*FLEN/8, x11, x5, x10) + +inst_25:// rs1==x17, rs2==x2, rd==x7,fs1 == 0 and fe1 == 0x00 and fm1 == 0x105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x17; op2:x2; dest:x7; op1val:0x105; op2val:0x17b; +valaddr_reg:x1; val_offset:24*FLEN/8; correctval:??; testreg:x10; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x7, x17, x2, 0, 0, x1, 24*FLEN/8, x11, x5, x10) +RVTEST_VALBASEUPD(x4,test_dataset_2) + +inst_26:// rs1==x0, rs2==x24, rd==x17,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x105 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x0; op2:x24; dest:x17; op1val:0x0; op2val:0x105; +valaddr_reg:x4; val_offset:0*FLEN/8; correctval:??; testreg:x10; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x17, x0, x24, 0, 0, x4, 0*FLEN/8, x7, x5, x10) + +inst_27:// rs1==x3, rs2==x22, rd==x9,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x3; op2:x22; dest:x9; op1val:0x739c; op2val:0xe; +valaddr_reg:x4; val_offset:2*FLEN/8; correctval:??; testreg:x10; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x9, x3, x22, 0, 0, x4, 2*FLEN/8, x7, x5, x10) + +inst_28:// rs1==x6, rs2==x28, rd==x1,fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x6; op2:x28; dest:x1; op1val:0x2; op2val:0x7bff; +valaddr_reg:x4; val_offset:4*FLEN/8; correctval:??; testreg:x10; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x1, x6, x28, 0, 0, x4, 4*FLEN/8, x7, x5, x10) + +inst_29:// rs1==x31, rs2==x1, rd==x0,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x31; op2:x1; dest:x0; op1val:0x7bff; op2val:0x2; +valaddr_reg:x4; val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x0, x31, x1, 0, 0, x4, 6*FLEN/8, x7, x5, x2) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_30:// rs1==x16, rs2==x31, rd==x6,fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x16; op2:x31; dest:x6; op1val:0x2; op2val:0xe; +valaddr_reg:x4; val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x6, x16, x31, 0, 0, x4, 8*FLEN/8, x7, x1, x2) + +inst_31:// rs1==x20, rs2==x21, rd==x23,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x20; op2:x21; dest:x23; op1val:0x739c; op2val:0x2; +valaddr_reg:x4; val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x23, x20, x21, 0, 0, x4, 10*FLEN/8, x7, x1, x2) + +inst_32:// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x739c; op2val:0x3fa; +valaddr_reg:x4; val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 12*FLEN/8, x7, x1, x2) + +inst_33:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x105 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x369 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x105; op2val:0x7b69; +valaddr_reg:x4; val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 14*FLEN/8, x7, x1, x2) + +inst_34:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x369 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x105 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b69; op2val:0x105; +valaddr_reg:x4; val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 16*FLEN/8, x7, x1, x2) + +inst_35:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x105; op2val:0x3fa; +valaddr_reg:x4; val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 18*FLEN/8, x7, x1, x2) + +inst_36:// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x739c; op2val:0x28e; +valaddr_reg:x4; val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 20*FLEN/8, x7, x1, x2) + +inst_37:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x105 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0c2 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x105; op2val:0x78c2; +valaddr_reg:x4; val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 22*FLEN/8, x7, x1, x2) + +inst_38:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x105 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x78c2; op2val:0x105; +valaddr_reg:x4; val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 24*FLEN/8, x7, x1, x2) + +inst_39:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x105; op2val:0x28e; +valaddr_reg:x4; val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 26*FLEN/8, x7, x1, x2) + +inst_40:// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x739c; op2val:0x217; +valaddr_reg:x4; val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 28*FLEN/8, x7, x1, x2) + +inst_41:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x105 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3cb and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x105; op2val:0x77cb; +valaddr_reg:x4; val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 30*FLEN/8, x7, x1, x2) + +inst_42:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3cb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x105 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x77cb; op2val:0x105; +valaddr_reg:x4; val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 32*FLEN/8, x7, x1, x2) + +inst_43:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x105; op2val:0x217; +valaddr_reg:x4; val_offset:34*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 34*FLEN/8, x7, x1, x2) + +inst_44:// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x195 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x739c; op2val:0x8195; +valaddr_reg:x4; val_offset:36*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 36*FLEN/8, x7, x1, x2) + +inst_45:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x105 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x1e7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x105; op2val:0xf5e7; +valaddr_reg:x4; val_offset:38*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 38*FLEN/8, x7, x1, x2) + +inst_46:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x1e7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x105 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf5e7; op2val:0x105; +valaddr_reg:x4; val_offset:40*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 40*FLEN/8, x7, x1, x2) + +inst_47:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x105 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x195 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x105; op2val:0x8195; +valaddr_reg:x4; val_offset:42*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 42*FLEN/8, x7, x1, x2) + +inst_48:// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x739c; op2val:0x80a7; +valaddr_reg:x4; val_offset:44*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 44*FLEN/8, x7, x1, x2) + +inst_49:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x01a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x1a; op2val:0xfbff; +valaddr_reg:x4; val_offset:46*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 46*FLEN/8, x7, x1, x2) + +inst_50:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x01a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x1a; +valaddr_reg:x4; val_offset:48*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 48*FLEN/8, x7, x1, x2) + +inst_51:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x01a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x1a; op2val:0x80a7; +valaddr_reg:x4; val_offset:50*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 50*FLEN/8, x7, x1, x2) + +inst_52:// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x01a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x739c; op2val:0x1a; +valaddr_reg:x4; val_offset:52*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 52*FLEN/8, x7, x1, x2) + +inst_53:// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x739c; op2val:0x821e; +valaddr_reg:x4; val_offset:54*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 54*FLEN/8, x7, x1, x2) + +inst_54:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x105 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3e4 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x105; op2val:0xf7e4; +valaddr_reg:x4; val_offset:56*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 56*FLEN/8, x7, x1, x2) + +inst_55:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x3e4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x105 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf7e4; op2val:0x105; +valaddr_reg:x4; val_offset:58*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 58*FLEN/8, x7, x1, x2) + +inst_56:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x105 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x105; op2val:0x821e; +valaddr_reg:x4; val_offset:60*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 60*FLEN/8, x7, x1, x2) + +inst_57:// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x739c; op2val:0x8365; +valaddr_reg:x4; val_offset:62*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 62*FLEN/8, x7, x1, x2) + +inst_58:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x105 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x252 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x105; op2val:0xfa52; +valaddr_reg:x4; val_offset:64*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 64*FLEN/8, x7, x1, x2) + +inst_59:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x252 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x105 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa52; op2val:0x105; +valaddr_reg:x4; val_offset:66*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 66*FLEN/8, x7, x1, x2) + +inst_60:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x105 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x105; op2val:0x8365; +valaddr_reg:x4; val_offset:68*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 68*FLEN/8, x7, x1, x2) + +inst_61:// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x109 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x739c; op2val:0x8109; +valaddr_reg:x4; val_offset:70*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 70*FLEN/8, x7, x1, x2) + +inst_62:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x105 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3b9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x105; op2val:0xf3b9; +valaddr_reg:x4; val_offset:72*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 72*FLEN/8, x7, x1, x2) + +inst_63:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x105 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3b9; op2val:0x105; +valaddr_reg:x4; val_offset:74*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 74*FLEN/8, x7, x1, x2) + +inst_64:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x105 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x109 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x105; op2val:0x8109; +valaddr_reg:x4; val_offset:76*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 76*FLEN/8, x7, x1, x2) + +inst_65:// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x739c; op2val:0xf0; +valaddr_reg:x4; val_offset:78*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 78*FLEN/8, x7, x1, x2) + +inst_66:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x23c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3e3c; op2val:0xf0; +valaddr_reg:x4; val_offset:80*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 80*FLEN/8, x7, x1, x2) + +inst_67:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x23c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x3e3c; +valaddr_reg:x4; val_offset:82*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 82*FLEN/8, x7, x1, x2) + +inst_68:// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x23c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x739c; op2val:0x3e3c; +valaddr_reg:x4; val_offset:84*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 84*FLEN/8, x7, x1, x2) + +inst_69:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x100 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7900; op2val:0x7900; +valaddr_reg:x4; val_offset:86*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 86*FLEN/8, x7, x1, x2) + +inst_70:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x025 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7900; op2val:0x7425; +valaddr_reg:x4; val_offset:88*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 88*FLEN/8, x7, x1, x2) + +inst_71:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x100 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7425; op2val:0x7900; +valaddr_reg:x4; val_offset:90*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 90*FLEN/8, x7, x1, x2) + +inst_72:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7900; op2val:0x7ab0; +valaddr_reg:x4; val_offset:92*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 92*FLEN/8, x7, x1, x2) + +inst_73:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x100 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab0; op2val:0x7900; +valaddr_reg:x4; val_offset:94*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 94*FLEN/8, x7, x1, x2) + +inst_74:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7900; op2val:0x7913; +valaddr_reg:x4; val_offset:96*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 96*FLEN/8, x7, x1, x2) + +inst_75:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x100 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0x7900; +valaddr_reg:x4; val_offset:98*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 98*FLEN/8, x7, x1, x2) + +inst_76:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7900; op2val:0xf749; +valaddr_reg:x4; val_offset:100*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 100*FLEN/8, x7, x1, x2) + +inst_77:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x100 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf749; op2val:0x7900; +valaddr_reg:x4; val_offset:102*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 102*FLEN/8, x7, x1, x2) + +inst_78:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x378 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7900; op2val:0xfb78; +valaddr_reg:x4; val_offset:104*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 104*FLEN/8, x7, x1, x2) + +inst_79:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x378 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x100 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb78; op2val:0x7900; +valaddr_reg:x4; val_offset:106*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 106*FLEN/8, x7, x1, x2) + +inst_80:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x21f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7900; op2val:0xfa1f; +valaddr_reg:x4; val_offset:108*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 108*FLEN/8, x7, x1, x2) + +inst_81:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x100 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa1f; op2val:0x7900; +valaddr_reg:x4; val_offset:110*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 110*FLEN/8, x7, x1, x2) + +inst_82:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7900; op2val:0xf82f; +valaddr_reg:x4; val_offset:112*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 112*FLEN/8, x7, x1, x2) + +inst_83:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x100 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82f; op2val:0x7900; +valaddr_reg:x4; val_offset:114*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 114*FLEN/8, x7, x1, x2) + +inst_84:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7900; op2val:0xf038; +valaddr_reg:x4; val_offset:116*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 116*FLEN/8, x7, x1, x2) + +inst_85:// fs1 == 0 and fe1 == 0x1b and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c00; op2val:0xfbff; +valaddr_reg:x4; val_offset:118*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 118*FLEN/8, x7, x1, x2) + +inst_86:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1b and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x6c00; +valaddr_reg:x4; val_offset:120*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 120*FLEN/8, x7, x1, x2) + +inst_87:// fs1 == 0 and fe1 == 0x1b and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c00; op2val:0xf038; +valaddr_reg:x4; val_offset:122*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 122*FLEN/8, x7, x1, x2) + +inst_88:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7900; op2val:0x6c00; +valaddr_reg:x4; val_offset:124*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 124*FLEN/8, x7, x1, x2) + +inst_89:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7900; op2val:0x17b; +valaddr_reg:x4; val_offset:126*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 126*FLEN/8, x7, x1, x2) + +inst_90:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2af and fs2 == 0 and fe2 == 0x1d and fm2 == 0x184 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x2af; op2val:0x7584; +valaddr_reg:x4; val_offset:128*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 128*FLEN/8, x7, x1, x2) + +inst_91:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x184 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2af and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7584; op2val:0x2af; +valaddr_reg:x4; val_offset:130*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 130*FLEN/8, x7, x1, x2) + +inst_92:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2af and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x2af; op2val:0x17b; +valaddr_reg:x4; val_offset:132*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 132*FLEN/8, x7, x1, x2) + +inst_93:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2af and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7900; op2val:0x2af; +valaddr_reg:x4; val_offset:134*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 134*FLEN/8, x7, x1, x2) + +inst_94:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7900; op2val:0xe; +valaddr_reg:x4; val_offset:136*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 136*FLEN/8, x7, x1, x2) + +inst_95:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x006 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x6; op2val:0x7bff; +valaddr_reg:x4; val_offset:138*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 138*FLEN/8, x7, x1, x2) + +inst_96:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x006 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6; +valaddr_reg:x4; val_offset:140*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 140*FLEN/8, x7, x1, x2) + +inst_97:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x006 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x6; op2val:0xe; +valaddr_reg:x4; val_offset:142*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 142*FLEN/8, x7, x1, x2) + +inst_98:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x006 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7900; op2val:0x6; +valaddr_reg:x4; val_offset:144*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 144*FLEN/8, x7, x1, x2) + +inst_99:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7900; op2val:0x3fa; +valaddr_reg:x4; val_offset:146*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 146*FLEN/8, x7, x1, x2) + +inst_100:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2af and fs2 == 0 and fe2 == 0x1e and fm2 == 0x369 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x2af; op2val:0x7b69; +valaddr_reg:x4; val_offset:148*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 148*FLEN/8, x7, x1, x2) + +inst_101:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x369 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2af and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b69; op2val:0x2af; +valaddr_reg:x4; val_offset:150*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 150*FLEN/8, x7, x1, x2) + +inst_102:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2af and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x2af; op2val:0x3fa; +valaddr_reg:x4; val_offset:152*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 152*FLEN/8, x7, x1, x2) + +inst_103:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7900; op2val:0x28e; +valaddr_reg:x4; val_offset:154*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 154*FLEN/8, x7, x1, x2) + +inst_104:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2af and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0c2 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x2af; op2val:0x78c2; +valaddr_reg:x4; val_offset:156*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 156*FLEN/8, x7, x1, x2) + +inst_105:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2af and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x78c2; op2val:0x2af; +valaddr_reg:x4; val_offset:158*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 158*FLEN/8, x7, x1, x2) + +inst_106:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2af and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x2af; op2val:0x28e; +valaddr_reg:x4; val_offset:160*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 160*FLEN/8, x7, x1, x2) + +inst_107:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7900; op2val:0x217; +valaddr_reg:x4; val_offset:162*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 162*FLEN/8, x7, x1, x2) + +inst_108:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2af and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3cb and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x2af; op2val:0x77cb; +valaddr_reg:x4; val_offset:164*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 164*FLEN/8, x7, x1, x2) + +inst_109:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3cb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2af and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x77cb; op2val:0x2af; +valaddr_reg:x4; val_offset:166*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 166*FLEN/8, x7, x1, x2) + +inst_110:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2af and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x2af; op2val:0x217; +valaddr_reg:x4; val_offset:168*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 168*FLEN/8, x7, x1, x2) + +inst_111:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x195 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7900; op2val:0x8195; +valaddr_reg:x4; val_offset:170*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 170*FLEN/8, x7, x1, x2) + +inst_112:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2af and fs2 == 1 and fe2 == 0x1d and fm2 == 0x1e7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x2af; op2val:0xf5e7; +valaddr_reg:x4; val_offset:172*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 172*FLEN/8, x7, x1, x2) + +inst_113:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x1e7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2af and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf5e7; op2val:0x2af; +valaddr_reg:x4; val_offset:174*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 174*FLEN/8, x7, x1, x2) + +inst_114:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2af and fs2 == 1 and fe2 == 0x00 and fm2 == 0x195 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x2af; op2val:0x8195; +valaddr_reg:x4; val_offset:176*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 176*FLEN/8, x7, x1, x2) + +inst_115:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7900; op2val:0x80a7; +valaddr_reg:x4; val_offset:178*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 178*FLEN/8, x7, x1, x2) + +inst_116:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x044 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x44; op2val:0xfbff; +valaddr_reg:x4; val_offset:180*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 180*FLEN/8, x7, x1, x2) + +inst_117:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x044 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x44; +valaddr_reg:x4; val_offset:182*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 182*FLEN/8, x7, x1, x2) + +inst_118:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x044 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x44; op2val:0x80a7; +valaddr_reg:x4; val_offset:184*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 184*FLEN/8, x7, x1, x2) + +inst_119:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x044 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7900; op2val:0x44; +valaddr_reg:x4; val_offset:186*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 186*FLEN/8, x7, x1, x2) + +inst_120:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7900; op2val:0x821e; +valaddr_reg:x4; val_offset:188*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 188*FLEN/8, x7, x1, x2) + +inst_121:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2af and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3e4 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x2af; op2val:0xf7e4; +valaddr_reg:x4; val_offset:190*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 190*FLEN/8, x7, x1, x2) + +inst_122:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x3e4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2af and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf7e4; op2val:0x2af; +valaddr_reg:x4; val_offset:192*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 192*FLEN/8, x7, x1, x2) + +inst_123:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2af and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x2af; op2val:0x821e; +valaddr_reg:x4; val_offset:194*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 194*FLEN/8, x7, x1, x2) + +inst_124:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7900; op2val:0x8365; +valaddr_reg:x4; val_offset:196*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 196*FLEN/8, x7, x1, x2) + +inst_125:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2af and fs2 == 1 and fe2 == 0x1e and fm2 == 0x252 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x2af; op2val:0xfa52; +valaddr_reg:x4; val_offset:198*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 198*FLEN/8, x7, x1, x2) + +inst_126:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x252 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2af and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa52; op2val:0x2af; +valaddr_reg:x4; val_offset:200*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 200*FLEN/8, x7, x1, x2) + +inst_127:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2af and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x2af; op2val:0x8365; +valaddr_reg:x4; val_offset:202*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 202*FLEN/8, x7, x1, x2) + +inst_128:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x109 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7900; op2val:0x8109; +valaddr_reg:x4; val_offset:204*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 204*FLEN/8, x7, x1, x2) + +inst_129:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2af and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3b9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x2af; op2val:0xf3b9; +valaddr_reg:x4; val_offset:206*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 206*FLEN/8, x7, x1, x2) + +inst_130:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2af and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3b9; op2val:0x2af; +valaddr_reg:x4; val_offset:208*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 208*FLEN/8, x7, x1, x2) + +inst_131:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2af and fs2 == 1 and fe2 == 0x00 and fm2 == 0x109 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x2af; op2val:0x8109; +valaddr_reg:x4; val_offset:210*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 210*FLEN/8, x7, x1, x2) + +inst_132:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7900; op2val:0xf0; +valaddr_reg:x4; val_offset:212*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 212*FLEN/8, x7, x1, x2) + +inst_133:// fs1 == 0 and fe1 == 0x11 and fm1 == 0x019 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x4419; op2val:0xf0; +valaddr_reg:x4; val_offset:214*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 214*FLEN/8, x7, x1, x2) + +inst_134:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x019 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x4419; +valaddr_reg:x4; val_offset:216*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 216*FLEN/8, x7, x1, x2) + +inst_135:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x019 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7900; op2val:0x4419; +valaddr_reg:x4; val_offset:218*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 218*FLEN/8, x7, x1, x2) + +inst_136:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x025 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7425; op2val:0x7425; +valaddr_reg:x4; val_offset:220*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 220*FLEN/8, x7, x1, x2) + +inst_137:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7425; op2val:0x7ab0; +valaddr_reg:x4; val_offset:222*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 222*FLEN/8, x7, x1, x2) + +inst_138:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x025 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab0; op2val:0x7425; +valaddr_reg:x4; val_offset:224*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 224*FLEN/8, x7, x1, x2) + +inst_139:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7425; op2val:0x7913; +valaddr_reg:x4; val_offset:226*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 226*FLEN/8, x7, x1, x2) + +inst_140:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x025 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0x7425; +valaddr_reg:x4; val_offset:228*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 228*FLEN/8, x7, x1, x2) + +inst_141:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7425; op2val:0xf749; +valaddr_reg:x4; val_offset:230*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 230*FLEN/8, x7, x1, x2) + +inst_142:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x025 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf749; op2val:0x7425; +valaddr_reg:x4; val_offset:232*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 232*FLEN/8, x7, x1, x2) + +inst_143:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x378 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7425; op2val:0xfb78; +valaddr_reg:x4; val_offset:234*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 234*FLEN/8, x7, x1, x2) + +inst_144:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x378 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x025 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb78; op2val:0x7425; +valaddr_reg:x4; val_offset:236*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 236*FLEN/8, x7, x1, x2) + +inst_145:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x21f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7425; op2val:0xfa1f; +valaddr_reg:x4; val_offset:238*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 238*FLEN/8, x7, x1, x2) + +inst_146:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 0 and fe2 == 0x1d and fm2 == 0x025 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa1f; op2val:0x7425; +valaddr_reg:x4; val_offset:240*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 240*FLEN/8, x7, x1, x2) + +inst_147:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7425; op2val:0xf82f; +valaddr_reg:x4; val_offset:242*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 242*FLEN/8, x7, x1, x2) + +inst_148:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 0 and fe2 == 0x1d and fm2 == 0x025 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82f; op2val:0x7425; +valaddr_reg:x4; val_offset:244*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 244*FLEN/8, x7, x1, x2) + +inst_149:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7425; op2val:0xf038; +valaddr_reg:x4; val_offset:246*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 246*FLEN/8, x7, x1, x2) + +inst_150:// fs1 == 0 and fe1 == 0x19 and fm1 == 0x2a2 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x66a2; op2val:0xfbff; +valaddr_reg:x4; val_offset:248*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 248*FLEN/8, x7, x1, x2) + +inst_151:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x19 and fm2 == 0x2a2 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x66a2; +valaddr_reg:x4; val_offset:250*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 250*FLEN/8, x7, x1, x2) + +inst_152:// fs1 == 0 and fe1 == 0x19 and fm1 == 0x2a2 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x66a2; op2val:0xf038; +valaddr_reg:x4; val_offset:252*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 252*FLEN/8, x7, x1, x2) + +inst_153:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x2a2 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7425; op2val:0x66a2; +valaddr_reg:x4; val_offset:254*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 254*FLEN/8, x7, x1, x2) + +inst_154:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7425; op2val:0x17b; +valaddr_reg:x4; val_offset:256*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 256*FLEN/8, x7, x1, x2) + +inst_155:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11d and fs2 == 0 and fe2 == 0x1d and fm2 == 0x184 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x11d; op2val:0x7584; +valaddr_reg:x4; val_offset:258*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 258*FLEN/8, x7, x1, x2) + +inst_156:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x184 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x11d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7584; op2val:0x11d; +valaddr_reg:x4; val_offset:260*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 260*FLEN/8, x7, x1, x2) + +inst_157:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x11d; op2val:0x17b; +valaddr_reg:x4; val_offset:262*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 262*FLEN/8, x7, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_158:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x11d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7425; op2val:0x11d; +valaddr_reg:x4; val_offset:264*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 264*FLEN/8, x7, x1, x2) + +inst_159:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7425; op2val:0xe; +valaddr_reg:x4; val_offset:266*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 266*FLEN/8, x7, x1, x2) + +inst_160:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7425; op2val:0x2; +valaddr_reg:x4; val_offset:268*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 268*FLEN/8, x7, x1, x2) + +inst_161:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7425; op2val:0x3fa; +valaddr_reg:x4; val_offset:270*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 270*FLEN/8, x7, x1, x2) + +inst_162:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x369 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x11d; op2val:0x7b69; +valaddr_reg:x4; val_offset:272*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 272*FLEN/8, x7, x1, x2) + +inst_163:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x369 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x11d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b69; op2val:0x11d; +valaddr_reg:x4; val_offset:274*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 274*FLEN/8, x7, x1, x2) + +inst_164:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x11d; op2val:0x3fa; +valaddr_reg:x4; val_offset:276*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 276*FLEN/8, x7, x1, x2) + +inst_165:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7425; op2val:0x28e; +valaddr_reg:x4; val_offset:278*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 278*FLEN/8, x7, x1, x2) + +inst_166:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0c2 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x11d; op2val:0x78c2; +valaddr_reg:x4; val_offset:280*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 280*FLEN/8, x7, x1, x2) + +inst_167:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x11d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x78c2; op2val:0x11d; +valaddr_reg:x4; val_offset:282*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 282*FLEN/8, x7, x1, x2) + +inst_168:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x11d; op2val:0x28e; +valaddr_reg:x4; val_offset:284*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 284*FLEN/8, x7, x1, x2) + +inst_169:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7425; op2val:0x217; +valaddr_reg:x4; val_offset:286*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 286*FLEN/8, x7, x1, x2) + +inst_170:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11d and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3cb and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x11d; op2val:0x77cb; +valaddr_reg:x4; val_offset:288*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 288*FLEN/8, x7, x1, x2) + +inst_171:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3cb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x11d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x77cb; op2val:0x11d; +valaddr_reg:x4; val_offset:290*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 290*FLEN/8, x7, x1, x2) + +inst_172:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x11d; op2val:0x217; +valaddr_reg:x4; val_offset:292*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 292*FLEN/8, x7, x1, x2) + +inst_173:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x195 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7425; op2val:0x8195; +valaddr_reg:x4; val_offset:294*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 294*FLEN/8, x7, x1, x2) + +inst_174:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11d and fs2 == 1 and fe2 == 0x1d and fm2 == 0x1e7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x11d; op2val:0xf5e7; +valaddr_reg:x4; val_offset:296*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 296*FLEN/8, x7, x1, x2) + +inst_175:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x1e7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x11d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf5e7; op2val:0x11d; +valaddr_reg:x4; val_offset:298*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 298*FLEN/8, x7, x1, x2) + +inst_176:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x195 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x11d; op2val:0x8195; +valaddr_reg:x4; val_offset:300*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 300*FLEN/8, x7, x1, x2) + +inst_177:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7425; op2val:0x80a7; +valaddr_reg:x4; val_offset:302*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 302*FLEN/8, x7, x1, x2) + +inst_178:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x01c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x1c; op2val:0xfbff; +valaddr_reg:x4; val_offset:304*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 304*FLEN/8, x7, x1, x2) + +inst_179:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x01c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x1c; +valaddr_reg:x4; val_offset:306*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 306*FLEN/8, x7, x1, x2) + +inst_180:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x01c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x1c; op2val:0x80a7; +valaddr_reg:x4; val_offset:308*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 308*FLEN/8, x7, x1, x2) + +inst_181:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x01c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7425; op2val:0x1c; +valaddr_reg:x4; val_offset:310*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 310*FLEN/8, x7, x1, x2) + +inst_182:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7425; op2val:0x821e; +valaddr_reg:x4; val_offset:312*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 312*FLEN/8, x7, x1, x2) + +inst_183:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11d and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3e4 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x11d; op2val:0xf7e4; +valaddr_reg:x4; val_offset:314*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 314*FLEN/8, x7, x1, x2) + +inst_184:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x3e4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x11d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf7e4; op2val:0x11d; +valaddr_reg:x4; val_offset:316*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 316*FLEN/8, x7, x1, x2) + +inst_185:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x11d; op2val:0x821e; +valaddr_reg:x4; val_offset:318*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 318*FLEN/8, x7, x1, x2) + +inst_186:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7425; op2val:0x8365; +valaddr_reg:x4; val_offset:320*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 320*FLEN/8, x7, x1, x2) + +inst_187:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x252 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x11d; op2val:0xfa52; +valaddr_reg:x4; val_offset:322*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 322*FLEN/8, x7, x1, x2) + +inst_188:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x252 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x11d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa52; op2val:0x11d; +valaddr_reg:x4; val_offset:324*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 324*FLEN/8, x7, x1, x2) + +inst_189:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x11d; op2val:0x8365; +valaddr_reg:x4; val_offset:326*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 326*FLEN/8, x7, x1, x2) + +inst_190:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x109 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7425; op2val:0x8109; +valaddr_reg:x4; val_offset:328*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 328*FLEN/8, x7, x1, x2) + +inst_191:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11d and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3b9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x11d; op2val:0xf3b9; +valaddr_reg:x4; val_offset:330*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 330*FLEN/8, x7, x1, x2) + +inst_192:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x11d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3b9; op2val:0x11d; +valaddr_reg:x4; val_offset:332*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 332*FLEN/8, x7, x1, x2) + +inst_193:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x109 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x11d; op2val:0x8109; +valaddr_reg:x4; val_offset:334*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 334*FLEN/8, x7, x1, x2) + +inst_194:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7425; op2val:0xf0; +valaddr_reg:x4; val_offset:336*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 336*FLEN/8, x7, x1, x2) + +inst_195:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x2cb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ecb; op2val:0xf0; +valaddr_reg:x4; val_offset:338*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 338*FLEN/8, x7, x1, x2) + +inst_196:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2cb and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x3ecb; +valaddr_reg:x4; val_offset:340*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 340*FLEN/8, x7, x1, x2) + +inst_197:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2cb and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7425; op2val:0x3ecb; +valaddr_reg:x4; val_offset:342*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 342*FLEN/8, x7, x1, x2) + +inst_198:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab0; op2val:0x7ab0; +valaddr_reg:x4; val_offset:344*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 344*FLEN/8, x7, x1, x2) + +inst_199:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab0; op2val:0x7913; +valaddr_reg:x4; val_offset:346*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 346*FLEN/8, x7, x1, x2) + +inst_200:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0x7ab0; +valaddr_reg:x4; val_offset:348*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 348*FLEN/8, x7, x1, x2) + +inst_201:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab0; op2val:0xf749; +valaddr_reg:x4; val_offset:350*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 350*FLEN/8, x7, x1, x2) + +inst_202:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf749; op2val:0x7ab0; +valaddr_reg:x4; val_offset:352*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 352*FLEN/8, x7, x1, x2) + +inst_203:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x378 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab0; op2val:0xfb78; +valaddr_reg:x4; val_offset:354*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 354*FLEN/8, x7, x1, x2) + +inst_204:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x378 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb78; op2val:0x7ab0; +valaddr_reg:x4; val_offset:356*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 356*FLEN/8, x7, x1, x2) + +inst_205:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x21f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab0; op2val:0xfa1f; +valaddr_reg:x4; val_offset:358*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 358*FLEN/8, x7, x1, x2) + +inst_206:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa1f; op2val:0x7ab0; +valaddr_reg:x4; val_offset:360*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 360*FLEN/8, x7, x1, x2) + +inst_207:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab0; op2val:0xf82f; +valaddr_reg:x4; val_offset:362*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 362*FLEN/8, x7, x1, x2) + +inst_208:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82f; op2val:0x7ab0; +valaddr_reg:x4; val_offset:364*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 364*FLEN/8, x7, x1, x2) + +inst_209:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab0; op2val:0xf038; +valaddr_reg:x4; val_offset:366*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 366*FLEN/8, x7, x1, x2) + +inst_210:// fs1 == 0 and fe1 == 0x1b and fm1 == 0x159 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d59; op2val:0xfbff; +valaddr_reg:x4; val_offset:368*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 368*FLEN/8, x7, x1, x2) + +inst_211:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1b and fm2 == 0x159 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x6d59; +valaddr_reg:x4; val_offset:370*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 370*FLEN/8, x7, x1, x2) + +inst_212:// fs1 == 0 and fe1 == 0x1b and fm1 == 0x159 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d59; op2val:0xf038; +valaddr_reg:x4; val_offset:372*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 372*FLEN/8, x7, x1, x2) + +inst_213:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x159 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab0; op2val:0x6d59; +valaddr_reg:x4; val_offset:374*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 374*FLEN/8, x7, x1, x2) + +inst_214:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab0; op2val:0x17b; +valaddr_reg:x4; val_offset:376*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 376*FLEN/8, x7, x1, x2) + +inst_215:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x397 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x184 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x397; op2val:0x7584; +valaddr_reg:x4; val_offset:378*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 378*FLEN/8, x7, x1, x2) + +inst_216:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x184 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x397 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7584; op2val:0x397; +valaddr_reg:x4; val_offset:380*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 380*FLEN/8, x7, x1, x2) + +inst_217:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x397 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x397; op2val:0x17b; +valaddr_reg:x4; val_offset:382*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 382*FLEN/8, x7, x1, x2) + +inst_218:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x397 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab0; op2val:0x397; +valaddr_reg:x4; val_offset:384*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 384*FLEN/8, x7, x1, x2) + +inst_219:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab0; op2val:0xe; +valaddr_reg:x4; val_offset:386*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 386*FLEN/8, x7, x1, x2) + +inst_220:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x009 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x9; op2val:0x7bff; +valaddr_reg:x4; val_offset:388*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 388*FLEN/8, x7, x1, x2) + +inst_221:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x009 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x9; +valaddr_reg:x4; val_offset:390*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 390*FLEN/8, x7, x1, x2) + +inst_222:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x009 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x9; op2val:0xe; +valaddr_reg:x4; val_offset:392*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 392*FLEN/8, x7, x1, x2) + +inst_223:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x009 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab0; op2val:0x9; +valaddr_reg:x4; val_offset:394*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 394*FLEN/8, x7, x1, x2) + +inst_224:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab0; op2val:0x3fa; +valaddr_reg:x4; val_offset:396*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 396*FLEN/8, x7, x1, x2) + +inst_225:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x397 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x369 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x397; op2val:0x7b69; +valaddr_reg:x4; val_offset:398*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 398*FLEN/8, x7, x1, x2) + +inst_226:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x369 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x397 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b69; op2val:0x397; +valaddr_reg:x4; val_offset:400*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 400*FLEN/8, x7, x1, x2) + +inst_227:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x397 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x397; op2val:0x3fa; +valaddr_reg:x4; val_offset:402*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 402*FLEN/8, x7, x1, x2) + +inst_228:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab0; op2val:0x28e; +valaddr_reg:x4; val_offset:404*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 404*FLEN/8, x7, x1, x2) + +inst_229:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x397 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0c2 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x397; op2val:0x78c2; +valaddr_reg:x4; val_offset:406*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 406*FLEN/8, x7, x1, x2) + +inst_230:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x397 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x78c2; op2val:0x397; +valaddr_reg:x4; val_offset:408*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 408*FLEN/8, x7, x1, x2) + +inst_231:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x397 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x397; op2val:0x28e; +valaddr_reg:x4; val_offset:410*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 410*FLEN/8, x7, x1, x2) + +inst_232:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab0; op2val:0x217; +valaddr_reg:x4; val_offset:412*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 412*FLEN/8, x7, x1, x2) + +inst_233:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x397 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3cb and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x397; op2val:0x77cb; +valaddr_reg:x4; val_offset:414*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 414*FLEN/8, x7, x1, x2) + +inst_234:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3cb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x397 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x77cb; op2val:0x397; +valaddr_reg:x4; val_offset:416*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 416*FLEN/8, x7, x1, x2) + +inst_235:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x397 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x397; op2val:0x217; +valaddr_reg:x4; val_offset:418*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 418*FLEN/8, x7, x1, x2) + +inst_236:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x195 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab0; op2val:0x8195; +valaddr_reg:x4; val_offset:420*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 420*FLEN/8, x7, x1, x2) + +inst_237:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x397 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x1e7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x397; op2val:0xf5e7; +valaddr_reg:x4; val_offset:422*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 422*FLEN/8, x7, x1, x2) + +inst_238:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x1e7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x397 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf5e7; op2val:0x397; +valaddr_reg:x4; val_offset:424*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 424*FLEN/8, x7, x1, x2) + +inst_239:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x397 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x195 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x397; op2val:0x8195; +valaddr_reg:x4; val_offset:426*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 426*FLEN/8, x7, x1, x2) + +inst_240:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab0; op2val:0x80a7; +valaddr_reg:x4; val_offset:428*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 428*FLEN/8, x7, x1, x2) + +inst_241:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x05b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x5b; op2val:0xfbff; +valaddr_reg:x4; val_offset:430*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 430*FLEN/8, x7, x1, x2) + +inst_242:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x05b and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x5b; +valaddr_reg:x4; val_offset:432*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 432*FLEN/8, x7, x1, x2) + +inst_243:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x05b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x5b; op2val:0x80a7; +valaddr_reg:x4; val_offset:434*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 434*FLEN/8, x7, x1, x2) + +inst_244:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x05b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab0; op2val:0x5b; +valaddr_reg:x4; val_offset:436*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 436*FLEN/8, x7, x1, x2) + +inst_245:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab0; op2val:0x821e; +valaddr_reg:x4; val_offset:438*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 438*FLEN/8, x7, x1, x2) + +inst_246:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x397 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3e4 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x397; op2val:0xf7e4; +valaddr_reg:x4; val_offset:440*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 440*FLEN/8, x7, x1, x2) + +inst_247:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x3e4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x397 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf7e4; op2val:0x397; +valaddr_reg:x4; val_offset:442*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 442*FLEN/8, x7, x1, x2) + +inst_248:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x397 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x397; op2val:0x821e; +valaddr_reg:x4; val_offset:444*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 444*FLEN/8, x7, x1, x2) + +inst_249:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab0; op2val:0x8365; +valaddr_reg:x4; val_offset:446*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 446*FLEN/8, x7, x1, x2) + +inst_250:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x397 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x252 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x397; op2val:0xfa52; +valaddr_reg:x4; val_offset:448*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 448*FLEN/8, x7, x1, x2) + +inst_251:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x252 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x397 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa52; op2val:0x397; +valaddr_reg:x4; val_offset:450*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 450*FLEN/8, x7, x1, x2) + +inst_252:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x397 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x397; op2val:0x8365; +valaddr_reg:x4; val_offset:452*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 452*FLEN/8, x7, x1, x2) + +inst_253:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x109 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab0; op2val:0x8109; +valaddr_reg:x4; val_offset:454*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 454*FLEN/8, x7, x1, x2) + +inst_254:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x397 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3b9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x397; op2val:0xf3b9; +valaddr_reg:x4; val_offset:456*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 456*FLEN/8, x7, x1, x2) + +inst_255:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x397 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3b9; op2val:0x397; +valaddr_reg:x4; val_offset:458*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 458*FLEN/8, x7, x1, x2) + +inst_256:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x397 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x109 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x397; op2val:0x8109; +valaddr_reg:x4; val_offset:460*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 460*FLEN/8, x7, x1, x2) + +inst_257:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab0; op2val:0xf0; +valaddr_reg:x4; val_offset:462*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 462*FLEN/8, x7, x1, x2) + +inst_258:// fs1 == 0 and fe1 == 0x11 and fm1 == 0x17a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x457a; op2val:0xf0; +valaddr_reg:x4; val_offset:464*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 464*FLEN/8, x7, x1, x2) + +inst_259:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x17a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x457a; +valaddr_reg:x4; val_offset:466*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 466*FLEN/8, x7, x1, x2) + +inst_260:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x17a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab0; op2val:0x457a; +valaddr_reg:x4; val_offset:468*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 468*FLEN/8, x7, x1, x2) + +inst_261:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0x7913; +valaddr_reg:x4; val_offset:470*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 470*FLEN/8, x7, x1, x2) + +inst_262:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0xf749; +valaddr_reg:x4; val_offset:472*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 472*FLEN/8, x7, x1, x2) + +inst_263:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf749; op2val:0x7913; +valaddr_reg:x4; val_offset:474*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 474*FLEN/8, x7, x1, x2) + +inst_264:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x378 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0xfb78; +valaddr_reg:x4; val_offset:476*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 476*FLEN/8, x7, x1, x2) + +inst_265:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x378 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb78; op2val:0x7913; +valaddr_reg:x4; val_offset:478*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 478*FLEN/8, x7, x1, x2) + +inst_266:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x21f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0xfa1f; +valaddr_reg:x4; val_offset:480*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 480*FLEN/8, x7, x1, x2) + +inst_267:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa1f; op2val:0x7913; +valaddr_reg:x4; val_offset:482*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 482*FLEN/8, x7, x1, x2) + +inst_268:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0xf82f; +valaddr_reg:x4; val_offset:484*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 484*FLEN/8, x7, x1, x2) + +inst_269:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82f; op2val:0x7913; +valaddr_reg:x4; val_offset:486*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 486*FLEN/8, x7, x1, x2) + +inst_270:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0xf038; +valaddr_reg:x4; val_offset:488*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 488*FLEN/8, x7, x1, x2) + +inst_271:// fs1 == 0 and fe1 == 0x1b and fm1 == 0x00f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c0f; op2val:0xfbff; +valaddr_reg:x4; val_offset:490*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 490*FLEN/8, x7, x1, x2) + +inst_272:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1b and fm2 == 0x00f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x6c0f; +valaddr_reg:x4; val_offset:492*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 492*FLEN/8, x7, x1, x2) + +inst_273:// fs1 == 0 and fe1 == 0x1b and fm1 == 0x00f and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c0f; op2val:0xf038; +valaddr_reg:x4; val_offset:494*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 494*FLEN/8, x7, x1, x2) + +inst_274:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x00f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0x6c0f; +valaddr_reg:x4; val_offset:496*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 496*FLEN/8, x7, x1, x2) + +inst_275:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0x17b; +valaddr_reg:x4; val_offset:498*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 498*FLEN/8, x7, x1, x2) + +inst_276:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2b9 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x184 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b9; op2val:0x7584; +valaddr_reg:x4; val_offset:500*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 500*FLEN/8, x7, x1, x2) + +inst_277:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x184 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2b9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7584; op2val:0x2b9; +valaddr_reg:x4; val_offset:502*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 502*FLEN/8, x7, x1, x2) + +inst_278:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b9; op2val:0x17b; +valaddr_reg:x4; val_offset:504*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 504*FLEN/8, x7, x1, x2) + +inst_279:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2b9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0x2b9; +valaddr_reg:x4; val_offset:506*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 506*FLEN/8, x7, x1, x2) + +inst_280:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0xe; +valaddr_reg:x4; val_offset:508*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 508*FLEN/8, x7, x1, x2) + +inst_281:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x006 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0x6; +valaddr_reg:x4; val_offset:510*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 510*FLEN/8, x7, x1, x2) + +inst_282:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0x3fa; +valaddr_reg:x4; val_offset:512*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 512*FLEN/8, x7, x1, x2) + +inst_283:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2b9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x369 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b9; op2val:0x7b69; +valaddr_reg:x4; val_offset:514*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 514*FLEN/8, x7, x1, x2) + +inst_284:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x369 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2b9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b69; op2val:0x2b9; +valaddr_reg:x4; val_offset:516*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 516*FLEN/8, x7, x1, x2) + +inst_285:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b9; op2val:0x3fa; +valaddr_reg:x4; val_offset:518*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 518*FLEN/8, x7, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_2) + +inst_286:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0x28e; +valaddr_reg:x4; val_offset:520*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 520*FLEN/8, x7, x1, x2) + +inst_287:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2b9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0c2 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b9; op2val:0x78c2; +valaddr_reg:x4; val_offset:522*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 522*FLEN/8, x7, x1, x2) + +inst_288:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2b9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x78c2; op2val:0x2b9; +valaddr_reg:x4; val_offset:524*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 524*FLEN/8, x7, x1, x2) + +inst_289:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b9; op2val:0x28e; +valaddr_reg:x4; val_offset:526*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 526*FLEN/8, x7, x1, x2) + +inst_290:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0x217; +valaddr_reg:x4; val_offset:528*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 528*FLEN/8, x7, x1, x2) + +inst_291:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2b9 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3cb and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b9; op2val:0x77cb; +valaddr_reg:x4; val_offset:530*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 530*FLEN/8, x7, x1, x2) + +inst_292:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3cb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2b9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x77cb; op2val:0x2b9; +valaddr_reg:x4; val_offset:532*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 532*FLEN/8, x7, x1, x2) + +inst_293:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b9; op2val:0x217; +valaddr_reg:x4; val_offset:534*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 534*FLEN/8, x7, x1, x2) + +inst_294:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x195 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0x8195; +valaddr_reg:x4; val_offset:536*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 536*FLEN/8, x7, x1, x2) + +inst_295:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2b9 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x1e7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b9; op2val:0xf5e7; +valaddr_reg:x4; val_offset:538*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 538*FLEN/8, x7, x1, x2) + +inst_296:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x1e7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2b9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf5e7; op2val:0x2b9; +valaddr_reg:x4; val_offset:540*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 540*FLEN/8, x7, x1, x2) + +inst_297:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x195 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b9; op2val:0x8195; +valaddr_reg:x4; val_offset:542*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 542*FLEN/8, x7, x1, x2) + +inst_298:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0x80a7; +valaddr_reg:x4; val_offset:544*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 544*FLEN/8, x7, x1, x2) + +inst_299:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x045 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x45; op2val:0xfbff; +valaddr_reg:x4; val_offset:546*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 546*FLEN/8, x7, x1, x2) + +inst_300:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x045 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x45; +valaddr_reg:x4; val_offset:548*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 548*FLEN/8, x7, x1, x2) + +inst_301:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x045 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x45; op2val:0x80a7; +valaddr_reg:x4; val_offset:550*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 550*FLEN/8, x7, x1, x2) + +inst_302:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x045 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0x45; +valaddr_reg:x4; val_offset:552*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 552*FLEN/8, x7, x1, x2) + +inst_303:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0x821e; +valaddr_reg:x4; val_offset:554*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 554*FLEN/8, x7, x1, x2) + +inst_304:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2b9 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3e4 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b9; op2val:0xf7e4; +valaddr_reg:x4; val_offset:556*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 556*FLEN/8, x7, x1, x2) + +inst_305:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x3e4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2b9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf7e4; op2val:0x2b9; +valaddr_reg:x4; val_offset:558*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 558*FLEN/8, x7, x1, x2) + +inst_306:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b9; op2val:0x821e; +valaddr_reg:x4; val_offset:560*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 560*FLEN/8, x7, x1, x2) + +inst_307:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0x8365; +valaddr_reg:x4; val_offset:562*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 562*FLEN/8, x7, x1, x2) + +inst_308:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2b9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x252 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b9; op2val:0xfa52; +valaddr_reg:x4; val_offset:564*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 564*FLEN/8, x7, x1, x2) + +inst_309:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x252 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2b9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa52; op2val:0x2b9; +valaddr_reg:x4; val_offset:566*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 566*FLEN/8, x7, x1, x2) + +inst_310:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b9; op2val:0x8365; +valaddr_reg:x4; val_offset:568*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 568*FLEN/8, x7, x1, x2) + +inst_311:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x109 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0x8109; +valaddr_reg:x4; val_offset:570*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 570*FLEN/8, x7, x1, x2) + +inst_312:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2b9 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3b9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b9; op2val:0xf3b9; +valaddr_reg:x4; val_offset:572*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 572*FLEN/8, x7, x1, x2) + +inst_313:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2b9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3b9; op2val:0x2b9; +valaddr_reg:x4; val_offset:574*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 574*FLEN/8, x7, x1, x2) + +inst_314:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x109 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b9; op2val:0x8109; +valaddr_reg:x4; val_offset:576*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 576*FLEN/8, x7, x1, x2) + +inst_315:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0xf0; +valaddr_reg:x4; val_offset:578*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 578*FLEN/8, x7, x1, x2) + +inst_316:// fs1 == 0 and fe1 == 0x11 and fm1 == 0x028 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x4428; op2val:0xf0; +valaddr_reg:x4; val_offset:580*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 580*FLEN/8, x7, x1, x2) + +inst_317:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x028 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x4428; +valaddr_reg:x4; val_offset:582*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 582*FLEN/8, x7, x1, x2) + +inst_318:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x028 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0x4428; +valaddr_reg:x4; val_offset:584*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 584*FLEN/8, x7, x1, x2) + +inst_319:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf749; op2val:0xf749; +valaddr_reg:x4; val_offset:586*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 586*FLEN/8, x7, x1, x2) + +inst_320:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x378 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf749; op2val:0xfb78; +valaddr_reg:x4; val_offset:588*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 588*FLEN/8, x7, x1, x2) + +inst_321:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x378 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb78; op2val:0xf749; +valaddr_reg:x4; val_offset:590*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 590*FLEN/8, x7, x1, x2) + +inst_322:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x21f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf749; op2val:0xfa1f; +valaddr_reg:x4; val_offset:592*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 592*FLEN/8, x7, x1, x2) + +inst_323:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 1 and fe2 == 0x1d and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa1f; op2val:0xf749; +valaddr_reg:x4; val_offset:594*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 594*FLEN/8, x7, x1, x2) + +inst_324:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf749; op2val:0xf82f; +valaddr_reg:x4; val_offset:596*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 596*FLEN/8, x7, x1, x2) + +inst_325:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 1 and fe2 == 0x1d and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82f; op2val:0xf749; +valaddr_reg:x4; val_offset:598*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 598*FLEN/8, x7, x1, x2) + +inst_326:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf749; op2val:0xf038; +valaddr_reg:x4; val_offset:600*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 600*FLEN/8, x7, x1, x2) + +inst_327:// fs1 == 1 and fe1 == 0x1a and fm1 == 0x1d4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xe9d4; op2val:0xfbff; +valaddr_reg:x4; val_offset:602*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 602*FLEN/8, x7, x1, x2) + +inst_328:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1a and fm2 == 0x1d4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xe9d4; +valaddr_reg:x4; val_offset:604*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 604*FLEN/8, x7, x1, x2) + +inst_329:// fs1 == 1 and fe1 == 0x1a and fm1 == 0x1d4 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xe9d4; op2val:0xf038; +valaddr_reg:x4; val_offset:606*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 606*FLEN/8, x7, x1, x2) + +inst_330:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x1d4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf749; op2val:0xe9d4; +valaddr_reg:x4; val_offset:608*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 608*FLEN/8, x7, x1, x2) + +inst_331:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17b and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf749; op2val:0x17b; +valaddr_reg:x4; val_offset:610*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 610*FLEN/8, x7, x1, x2) + +inst_332:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1f4 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x184 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x81f4; op2val:0x7584; +valaddr_reg:x4; val_offset:612*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 612*FLEN/8, x7, x1, x2) + +inst_333:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x184 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1f4 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7584; op2val:0x81f4; +valaddr_reg:x4; val_offset:614*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 614*FLEN/8, x7, x1, x2) + +inst_334:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1f4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17b and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x81f4; op2val:0x17b; +valaddr_reg:x4; val_offset:616*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 616*FLEN/8, x7, x1, x2) + +inst_335:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1f4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf749; op2val:0x81f4; +valaddr_reg:x4; val_offset:618*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 618*FLEN/8, x7, x1, x2) + +inst_336:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf749; op2val:0xe; +valaddr_reg:x4; val_offset:620*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 620*FLEN/8, x7, x1, x2) + +inst_337:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x005 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8005; op2val:0x7bff; +valaddr_reg:x4; val_offset:622*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 622*FLEN/8, x7, x1, x2) + +inst_338:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x005 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8005; +valaddr_reg:x4; val_offset:624*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 624*FLEN/8, x7, x1, x2) + +inst_339:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x005 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8005; op2val:0xe; +valaddr_reg:x4; val_offset:626*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 626*FLEN/8, x7, x1, x2) + +inst_340:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x005 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf749; op2val:0x8005; +valaddr_reg:x4; val_offset:628*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 628*FLEN/8, x7, x1, x2) + +inst_341:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf749; op2val:0x3fa; +valaddr_reg:x4; val_offset:630*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 630*FLEN/8, x7, x1, x2) + +inst_342:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1f4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x369 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x81f4; op2val:0x7b69; +valaddr_reg:x4; val_offset:632*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 632*FLEN/8, x7, x1, x2) + +inst_343:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x369 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1f4 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b69; op2val:0x81f4; +valaddr_reg:x4; val_offset:634*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 634*FLEN/8, x7, x1, x2) + +inst_344:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1f4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x81f4; op2val:0x3fa; +valaddr_reg:x4; val_offset:636*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 636*FLEN/8, x7, x1, x2) + +inst_345:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf749; op2val:0x28e; +valaddr_reg:x4; val_offset:638*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 638*FLEN/8, x7, x1, x2) + +inst_346:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1f4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0c2 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x81f4; op2val:0x78c2; +valaddr_reg:x4; val_offset:640*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 640*FLEN/8, x7, x1, x2) + +inst_347:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1f4 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x78c2; op2val:0x81f4; +valaddr_reg:x4; val_offset:642*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 642*FLEN/8, x7, x1, x2) + +inst_348:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1f4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x81f4; op2val:0x28e; +valaddr_reg:x4; val_offset:644*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 644*FLEN/8, x7, x1, x2) + +inst_349:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf749; op2val:0x217; +valaddr_reg:x4; val_offset:646*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 646*FLEN/8, x7, x1, x2) + +inst_350:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1f4 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3cb and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x81f4; op2val:0x77cb; +valaddr_reg:x4; val_offset:648*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 648*FLEN/8, x7, x1, x2) + +inst_351:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3cb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1f4 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x77cb; op2val:0x81f4; +valaddr_reg:x4; val_offset:650*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 650*FLEN/8, x7, x1, x2) + +inst_352:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1f4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x81f4; op2val:0x217; +valaddr_reg:x4; val_offset:652*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 652*FLEN/8, x7, x1, x2) + +inst_353:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x195 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf749; op2val:0x8195; +valaddr_reg:x4; val_offset:654*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 654*FLEN/8, x7, x1, x2) + +inst_354:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1f4 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x1e7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x81f4; op2val:0xf5e7; +valaddr_reg:x4; val_offset:656*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 656*FLEN/8, x7, x1, x2) + +inst_355:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x1e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1f4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf5e7; op2val:0x81f4; +valaddr_reg:x4; val_offset:658*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 658*FLEN/8, x7, x1, x2) + +inst_356:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1f4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x195 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x81f4; op2val:0x8195; +valaddr_reg:x4; val_offset:660*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 660*FLEN/8, x7, x1, x2) + +inst_357:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf749; op2val:0x80a7; +valaddr_reg:x4; val_offset:662*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 662*FLEN/8, x7, x1, x2) + +inst_358:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x032 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8032; op2val:0xfbff; +valaddr_reg:x4; val_offset:664*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 664*FLEN/8, x7, x1, x2) + +inst_359:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x032 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8032; +valaddr_reg:x4; val_offset:666*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 666*FLEN/8, x7, x1, x2) + +inst_360:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x032 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8032; op2val:0x80a7; +valaddr_reg:x4; val_offset:668*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 668*FLEN/8, x7, x1, x2) + +inst_361:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x032 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf749; op2val:0x8032; +valaddr_reg:x4; val_offset:670*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 670*FLEN/8, x7, x1, x2) + +inst_362:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf749; op2val:0x821e; +valaddr_reg:x4; val_offset:672*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 672*FLEN/8, x7, x1, x2) + +inst_363:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1f4 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3e4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x81f4; op2val:0xf7e4; +valaddr_reg:x4; val_offset:674*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 674*FLEN/8, x7, x1, x2) + +inst_364:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x3e4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1f4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf7e4; op2val:0x81f4; +valaddr_reg:x4; val_offset:676*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 676*FLEN/8, x7, x1, x2) + +inst_365:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1f4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x81f4; op2val:0x821e; +valaddr_reg:x4; val_offset:678*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 678*FLEN/8, x7, x1, x2) + +inst_366:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf749; op2val:0x8365; +valaddr_reg:x4; val_offset:680*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 680*FLEN/8, x7, x1, x2) + +inst_367:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1f4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x252 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x81f4; op2val:0xfa52; +valaddr_reg:x4; val_offset:682*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 682*FLEN/8, x7, x1, x2) + +inst_368:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x252 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1f4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa52; op2val:0x81f4; +valaddr_reg:x4; val_offset:684*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 684*FLEN/8, x7, x1, x2) + +inst_369:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1f4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x81f4; op2val:0x8365; +valaddr_reg:x4; val_offset:686*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 686*FLEN/8, x7, x1, x2) + +inst_370:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x109 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf749; op2val:0x8109; +valaddr_reg:x4; val_offset:688*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 688*FLEN/8, x7, x1, x2) + +inst_371:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1f4 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3b9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x81f4; op2val:0xf3b9; +valaddr_reg:x4; val_offset:690*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 690*FLEN/8, x7, x1, x2) + +inst_372:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1f4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3b9; op2val:0x81f4; +valaddr_reg:x4; val_offset:692*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 692*FLEN/8, x7, x1, x2) + +inst_373:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1f4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x109 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x81f4; op2val:0x8109; +valaddr_reg:x4; val_offset:694*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 694*FLEN/8, x7, x1, x2) + +inst_374:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf749; op2val:0xf0; +valaddr_reg:x4; val_offset:696*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 696*FLEN/8, x7, x1, x2) + +inst_375:// fs1 == 1 and fe1 == 0x10 and fm1 == 0x1f8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xc1f8; op2val:0xf0; +valaddr_reg:x4; val_offset:698*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 698*FLEN/8, x7, x1, x2) + +inst_376:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1f8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xc1f8; +valaddr_reg:x4; val_offset:700*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 700*FLEN/8, x7, x1, x2) + +inst_377:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1f8 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf749; op2val:0xc1f8; +valaddr_reg:x4; val_offset:702*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 702*FLEN/8, x7, x1, x2) + +inst_378:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x378 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x378 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb78; op2val:0xfb78; +valaddr_reg:x4; val_offset:704*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 704*FLEN/8, x7, x1, x2) + +inst_379:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x378 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x21f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb78; op2val:0xfa1f; +valaddr_reg:x4; val_offset:706*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 706*FLEN/8, x7, x1, x2) + +inst_380:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x378 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa1f; op2val:0xfb78; +valaddr_reg:x4; val_offset:708*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 708*FLEN/8, x7, x1, x2) + +inst_381:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x378 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb78; op2val:0xf82f; +valaddr_reg:x4; val_offset:710*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 710*FLEN/8, x7, x1, x2) + +inst_382:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x378 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82f; op2val:0xfb78; +valaddr_reg:x4; val_offset:712*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 712*FLEN/8, x7, x1, x2) + +inst_383:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x378 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb78; op2val:0xf038; +valaddr_reg:x4; val_offset:714*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 714*FLEN/8, x7, x1, x2) + +inst_384:// fs1 == 1 and fe1 == 0x1b and fm1 == 0x1fa and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xedfa; op2val:0xfbff; +valaddr_reg:x4; val_offset:716*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 716*FLEN/8, x7, x1, x2) + +inst_385:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1b and fm2 == 0x1fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xedfa; +valaddr_reg:x4; val_offset:718*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 718*FLEN/8, x7, x1, x2) + +inst_386:// fs1 == 1 and fe1 == 0x1b and fm1 == 0x1fa and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xedfa; op2val:0xf038; +valaddr_reg:x4; val_offset:720*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 720*FLEN/8, x7, x1, x2) + +inst_387:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x378 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x1fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb78; op2val:0xedfa; +valaddr_reg:x4; val_offset:722*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 722*FLEN/8, x7, x1, x2) + +inst_388:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x378 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17b and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb78; op2val:0x17b; +valaddr_reg:x4; val_offset:724*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 724*FLEN/8, x7, x1, x2) + +inst_389:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x184 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8402; op2val:0x7584; +valaddr_reg:x4; val_offset:726*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 726*FLEN/8, x7, x1, x2) + +inst_390:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x184 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7584; op2val:0x8402; +valaddr_reg:x4; val_offset:728*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 728*FLEN/8, x7, x1, x2) + +inst_391:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17b and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8402; op2val:0x17b; +valaddr_reg:x4; val_offset:730*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 730*FLEN/8, x7, x1, x2) + +inst_392:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x378 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb78; op2val:0x8402; +valaddr_reg:x4; val_offset:732*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 732*FLEN/8, x7, x1, x2) + +inst_393:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x378 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb78; op2val:0xe; +valaddr_reg:x4; val_offset:734*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 734*FLEN/8, x7, x1, x2) + +inst_394:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x00a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x800a; op2val:0x7bff; +valaddr_reg:x4; val_offset:736*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 736*FLEN/8, x7, x1, x2) + +inst_395:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x800a; +valaddr_reg:x4; val_offset:738*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 738*FLEN/8, x7, x1, x2) + +inst_396:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x00a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x800a; op2val:0xe; +valaddr_reg:x4; val_offset:740*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 740*FLEN/8, x7, x1, x2) + +inst_397:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x378 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb78; op2val:0x800a; +valaddr_reg:x4; val_offset:742*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 742*FLEN/8, x7, x1, x2) + +inst_398:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x378 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb78; op2val:0x3fa; +valaddr_reg:x4; val_offset:744*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 744*FLEN/8, x7, x1, x2) + +inst_399:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x369 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8402; op2val:0x7b69; +valaddr_reg:x4; val_offset:746*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 746*FLEN/8, x7, x1, x2) + +inst_400:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x369 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b69; op2val:0x8402; +valaddr_reg:x4; val_offset:748*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 748*FLEN/8, x7, x1, x2) + +inst_401:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8402; op2val:0x3fa; +valaddr_reg:x4; val_offset:750*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 750*FLEN/8, x7, x1, x2) + +inst_402:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x378 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb78; op2val:0x28e; +valaddr_reg:x4; val_offset:752*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 752*FLEN/8, x7, x1, x2) + +inst_403:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0c2 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8402; op2val:0x78c2; +valaddr_reg:x4; val_offset:754*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 754*FLEN/8, x7, x1, x2) + +inst_404:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x78c2; op2val:0x8402; +valaddr_reg:x4; val_offset:756*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 756*FLEN/8, x7, x1, x2) + +inst_405:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8402; op2val:0x28e; +valaddr_reg:x4; val_offset:758*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 758*FLEN/8, x7, x1, x2) + +inst_406:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x378 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb78; op2val:0x217; +valaddr_reg:x4; val_offset:760*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 760*FLEN/8, x7, x1, x2) + +inst_407:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3cb and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8402; op2val:0x77cb; +valaddr_reg:x4; val_offset:762*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 762*FLEN/8, x7, x1, x2) + +inst_408:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3cb and fs2 == 1 and fe2 == 0x01 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x77cb; op2val:0x8402; +valaddr_reg:x4; val_offset:764*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 764*FLEN/8, x7, x1, x2) + +inst_409:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8402; op2val:0x217; +valaddr_reg:x4; val_offset:766*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 766*FLEN/8, x7, x1, x2) + +inst_410:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x378 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x195 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb78; op2val:0x8195; +valaddr_reg:x4; val_offset:768*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 768*FLEN/8, x7, x1, x2) + +inst_411:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x1e7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8402; op2val:0xf5e7; +valaddr_reg:x4; val_offset:770*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 770*FLEN/8, x7, x1, x2) + +inst_412:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x1e7 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf5e7; op2val:0x8402; +valaddr_reg:x4; val_offset:772*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 772*FLEN/8, x7, x1, x2) + +inst_413:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x195 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8402; op2val:0x8195; +valaddr_reg:x4; val_offset:774*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 774*FLEN/8, x7, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_3) + +inst_414:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x378 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb78; op2val:0x80a7; +valaddr_reg:x4; val_offset:776*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 776*FLEN/8, x7, x1, x2) + +inst_415:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x066 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8066; op2val:0xfbff; +valaddr_reg:x4; val_offset:778*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 778*FLEN/8, x7, x1, x2) + +inst_416:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x066 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8066; +valaddr_reg:x4; val_offset:780*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 780*FLEN/8, x7, x1, x2) + +inst_417:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x066 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8066; op2val:0x80a7; +valaddr_reg:x4; val_offset:782*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 782*FLEN/8, x7, x1, x2) + +inst_418:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x378 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x066 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb78; op2val:0x8066; +valaddr_reg:x4; val_offset:784*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 784*FLEN/8, x7, x1, x2) + +inst_419:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x378 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb78; op2val:0x821e; +valaddr_reg:x4; val_offset:786*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 786*FLEN/8, x7, x1, x2) + +inst_420:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3e4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8402; op2val:0xf7e4; +valaddr_reg:x4; val_offset:788*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 788*FLEN/8, x7, x1, x2) + +inst_421:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x3e4 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf7e4; op2val:0x8402; +valaddr_reg:x4; val_offset:790*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 790*FLEN/8, x7, x1, x2) + +inst_422:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8402; op2val:0x821e; +valaddr_reg:x4; val_offset:792*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 792*FLEN/8, x7, x1, x2) + +inst_423:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x378 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb78; op2val:0x8365; +valaddr_reg:x4; val_offset:794*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 794*FLEN/8, x7, x1, x2) + +inst_424:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x252 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8402; op2val:0xfa52; +valaddr_reg:x4; val_offset:796*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 796*FLEN/8, x7, x1, x2) + +inst_425:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x252 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa52; op2val:0x8402; +valaddr_reg:x4; val_offset:798*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 798*FLEN/8, x7, x1, x2) + +inst_426:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8402; op2val:0x8365; +valaddr_reg:x4; val_offset:800*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 800*FLEN/8, x7, x1, x2) + +inst_427:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x378 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x109 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb78; op2val:0x8109; +valaddr_reg:x4; val_offset:802*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 802*FLEN/8, x7, x1, x2) + +inst_428:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3b9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8402; op2val:0xf3b9; +valaddr_reg:x4; val_offset:804*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 804*FLEN/8, x7, x1, x2) + +inst_429:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3b9 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3b9; op2val:0x8402; +valaddr_reg:x4; val_offset:806*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 806*FLEN/8, x7, x1, x2) + +inst_430:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x109 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8402; op2val:0x8109; +valaddr_reg:x4; val_offset:808*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 808*FLEN/8, x7, x1, x2) + +inst_431:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x378 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb78; op2val:0xf0; +valaddr_reg:x4; val_offset:810*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 810*FLEN/8, x7, x1, x2) + +inst_432:// fs1 == 1 and fe1 == 0x11 and fm1 == 0x21f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xc61f; op2val:0xf0; +valaddr_reg:x4; val_offset:812*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 812*FLEN/8, x7, x1, x2) + +inst_433:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x21f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xc61f; +valaddr_reg:x4; val_offset:814*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 814*FLEN/8, x7, x1, x2) + +inst_434:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x378 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x21f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb78; op2val:0xc61f; +valaddr_reg:x4; val_offset:816*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 816*FLEN/8, x7, x1, x2) + +inst_435:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x21f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa1f; op2val:0xfa1f; +valaddr_reg:x4; val_offset:818*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 818*FLEN/8, x7, x1, x2) + +inst_436:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa1f; op2val:0xf82f; +valaddr_reg:x4; val_offset:820*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 820*FLEN/8, x7, x1, x2) + +inst_437:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x21f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82f; op2val:0xfa1f; +valaddr_reg:x4; val_offset:822*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 822*FLEN/8, x7, x1, x2) + +inst_438:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa1f; op2val:0xf038; +valaddr_reg:x4; val_offset:824*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 824*FLEN/8, x7, x1, x2) + +inst_439:// fs1 == 1 and fe1 == 0x1b and fm1 == 0x0e5 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xece5; op2val:0xfbff; +valaddr_reg:x4; val_offset:826*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 826*FLEN/8, x7, x1, x2) + +inst_440:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1b and fm2 == 0x0e5 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xece5; +valaddr_reg:x4; val_offset:828*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 828*FLEN/8, x7, x1, x2) + +inst_441:// fs1 == 1 and fe1 == 0x1b and fm1 == 0x0e5 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xece5; op2val:0xf038; +valaddr_reg:x4; val_offset:830*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 830*FLEN/8, x7, x1, x2) + +inst_442:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 1 and fe2 == 0x1b and fm2 == 0x0e5 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa1f; op2val:0xece5; +valaddr_reg:x4; val_offset:832*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 832*FLEN/8, x7, x1, x2) + +inst_443:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17b and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa1f; op2val:0x17b; +valaddr_reg:x4; val_offset:834*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 834*FLEN/8, x7, x1, x2) + +inst_444:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x349 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x184 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8349; op2val:0x7584; +valaddr_reg:x4; val_offset:836*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 836*FLEN/8, x7, x1, x2) + +inst_445:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x184 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7584; op2val:0x8349; +valaddr_reg:x4; val_offset:838*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 838*FLEN/8, x7, x1, x2) + +inst_446:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x349 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17b and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8349; op2val:0x17b; +valaddr_reg:x4; val_offset:840*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 840*FLEN/8, x7, x1, x2) + +inst_447:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa1f; op2val:0x8349; +valaddr_reg:x4; val_offset:842*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 842*FLEN/8, x7, x1, x2) + +inst_448:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa1f; op2val:0xe; +valaddr_reg:x4; val_offset:844*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 844*FLEN/8, x7, x1, x2) + +inst_449:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x008 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8008; op2val:0x7bff; +valaddr_reg:x4; val_offset:846*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 846*FLEN/8, x7, x1, x2) + +inst_450:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x008 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8008; +valaddr_reg:x4; val_offset:848*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 848*FLEN/8, x7, x1, x2) + +inst_451:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x008 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8008; op2val:0xe; +valaddr_reg:x4; val_offset:850*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 850*FLEN/8, x7, x1, x2) + +inst_452:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x008 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa1f; op2val:0x8008; +valaddr_reg:x4; val_offset:852*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 852*FLEN/8, x7, x1, x2) + +inst_453:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa1f; op2val:0x3fa; +valaddr_reg:x4; val_offset:854*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 854*FLEN/8, x7, x1, x2) + +inst_454:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x349 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x369 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8349; op2val:0x7b69; +valaddr_reg:x4; val_offset:856*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 856*FLEN/8, x7, x1, x2) + +inst_455:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x369 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b69; op2val:0x8349; +valaddr_reg:x4; val_offset:858*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 858*FLEN/8, x7, x1, x2) + +inst_456:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x349 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8349; op2val:0x3fa; +valaddr_reg:x4; val_offset:860*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 860*FLEN/8, x7, x1, x2) + +inst_457:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa1f; op2val:0x28e; +valaddr_reg:x4; val_offset:862*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 862*FLEN/8, x7, x1, x2) + +inst_458:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x349 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0c2 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8349; op2val:0x78c2; +valaddr_reg:x4; val_offset:864*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 864*FLEN/8, x7, x1, x2) + +inst_459:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x78c2; op2val:0x8349; +valaddr_reg:x4; val_offset:866*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 866*FLEN/8, x7, x1, x2) + +inst_460:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x349 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8349; op2val:0x28e; +valaddr_reg:x4; val_offset:868*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 868*FLEN/8, x7, x1, x2) + +inst_461:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa1f; op2val:0x217; +valaddr_reg:x4; val_offset:870*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 870*FLEN/8, x7, x1, x2) + +inst_462:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x349 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3cb and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8349; op2val:0x77cb; +valaddr_reg:x4; val_offset:872*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 872*FLEN/8, x7, x1, x2) + +inst_463:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3cb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x77cb; op2val:0x8349; +valaddr_reg:x4; val_offset:874*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 874*FLEN/8, x7, x1, x2) + +inst_464:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x349 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8349; op2val:0x217; +valaddr_reg:x4; val_offset:876*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 876*FLEN/8, x7, x1, x2) + +inst_465:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x195 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa1f; op2val:0x8195; +valaddr_reg:x4; val_offset:878*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 878*FLEN/8, x7, x1, x2) + +inst_466:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x349 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x1e7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8349; op2val:0xf5e7; +valaddr_reg:x4; val_offset:880*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 880*FLEN/8, x7, x1, x2) + +inst_467:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x1e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf5e7; op2val:0x8349; +valaddr_reg:x4; val_offset:882*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 882*FLEN/8, x7, x1, x2) + +inst_468:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x349 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x195 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8349; op2val:0x8195; +valaddr_reg:x4; val_offset:884*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 884*FLEN/8, x7, x1, x2) + +inst_469:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa1f; op2val:0x80a7; +valaddr_reg:x4; val_offset:886*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 886*FLEN/8, x7, x1, x2) + +inst_470:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x054 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8054; op2val:0xfbff; +valaddr_reg:x4; val_offset:888*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 888*FLEN/8, x7, x1, x2) + +inst_471:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x054 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8054; +valaddr_reg:x4; val_offset:890*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 890*FLEN/8, x7, x1, x2) + +inst_472:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x054 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8054; op2val:0x80a7; +valaddr_reg:x4; val_offset:892*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 892*FLEN/8, x7, x1, x2) + +inst_473:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x054 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa1f; op2val:0x8054; +valaddr_reg:x4; val_offset:894*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 894*FLEN/8, x7, x1, x2) + +inst_474:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa1f; op2val:0x821e; +valaddr_reg:x4; val_offset:896*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 896*FLEN/8, x7, x1, x2) + +inst_475:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x349 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3e4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8349; op2val:0xf7e4; +valaddr_reg:x4; val_offset:898*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 898*FLEN/8, x7, x1, x2) + +inst_476:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x3e4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf7e4; op2val:0x8349; +valaddr_reg:x4; val_offset:900*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 900*FLEN/8, x7, x1, x2) + +inst_477:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x349 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8349; op2val:0x821e; +valaddr_reg:x4; val_offset:902*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 902*FLEN/8, x7, x1, x2) + +inst_478:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa1f; op2val:0x8365; +valaddr_reg:x4; val_offset:904*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 904*FLEN/8, x7, x1, x2) + +inst_479:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x349 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x252 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8349; op2val:0xfa52; +valaddr_reg:x4; val_offset:906*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 906*FLEN/8, x7, x1, x2) + +inst_480:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x252 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa52; op2val:0x8349; +valaddr_reg:x4; val_offset:908*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 908*FLEN/8, x7, x1, x2) + +inst_481:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x349 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8349; op2val:0x8365; +valaddr_reg:x4; val_offset:910*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 910*FLEN/8, x7, x1, x2) + +inst_482:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x109 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa1f; op2val:0x8109; +valaddr_reg:x4; val_offset:912*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 912*FLEN/8, x7, x1, x2) + +inst_483:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x349 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3b9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8349; op2val:0xf3b9; +valaddr_reg:x4; val_offset:914*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 914*FLEN/8, x7, x1, x2) + +inst_484:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3b9; op2val:0x8349; +valaddr_reg:x4; val_offset:916*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 916*FLEN/8, x7, x1, x2) + +inst_485:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x349 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x109 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8349; op2val:0x8109; +valaddr_reg:x4; val_offset:918*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 918*FLEN/8, x7, x1, x2) + +inst_486:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa1f; op2val:0xf0; +valaddr_reg:x4; val_offset:920*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 920*FLEN/8, x7, x1, x2) + +inst_487:// fs1 == 1 and fe1 == 0x11 and fm1 == 0x103 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xc503; op2val:0xf0; +valaddr_reg:x4; val_offset:922*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 922*FLEN/8, x7, x1, x2) + +inst_488:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x103 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xc503; +valaddr_reg:x4; val_offset:924*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 924*FLEN/8, x7, x1, x2) + +inst_489:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 1 and fe2 == 0x11 and fm2 == 0x103 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa1f; op2val:0xc503; +valaddr_reg:x4; val_offset:926*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 926*FLEN/8, x7, x1, x2) + +inst_490:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82f; op2val:0xf82f; +valaddr_reg:x4; val_offset:928*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 928*FLEN/8, x7, x1, x2) + +inst_491:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82f; op2val:0xf038; +valaddr_reg:x4; val_offset:930*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 930*FLEN/8, x7, x1, x2) + +inst_492:// fs1 == 1 and fe1 == 0x1a and fm1 == 0x2b3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xeab3; op2val:0xfbff; +valaddr_reg:x4; val_offset:932*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 932*FLEN/8, x7, x1, x2) + +inst_493:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1a and fm2 == 0x2b3 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xeab3; +valaddr_reg:x4; val_offset:934*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 934*FLEN/8, x7, x1, x2) + +inst_494:// fs1 == 1 and fe1 == 0x1a and fm1 == 0x2b3 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xeab3; op2val:0xf038; +valaddr_reg:x4; val_offset:936*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 936*FLEN/8, x7, x1, x2) + +inst_495:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 1 and fe2 == 0x1a and fm2 == 0x2b3 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82f; op2val:0xeab3; +valaddr_reg:x4; val_offset:938*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 938*FLEN/8, x7, x1, x2) + +inst_496:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17b and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82f; op2val:0x17b; +valaddr_reg:x4; val_offset:940*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 940*FLEN/8, x7, x1, x2) + +inst_497:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x23f and fs2 == 0 and fe2 == 0x1d and fm2 == 0x184 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x823f; op2val:0x7584; +valaddr_reg:x4; val_offset:942*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 942*FLEN/8, x7, x1, x2) + +inst_498:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x184 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x23f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7584; op2val:0x823f; +valaddr_reg:x4; val_offset:944*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 944*FLEN/8, x7, x1, x2) + +inst_499:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x23f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17b and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x823f; op2val:0x17b; +valaddr_reg:x4; val_offset:946*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 946*FLEN/8, x7, x1, x2) + +inst_500:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x23f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82f; op2val:0x823f; +valaddr_reg:x4; val_offset:948*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 948*FLEN/8, x7, x1, x2) + +inst_501:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82f; op2val:0xe; +valaddr_reg:x4; val_offset:950*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 950*FLEN/8, x7, x1, x2) + +inst_502:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x005 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82f; op2val:0x8005; +valaddr_reg:x4; val_offset:952*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 952*FLEN/8, x7, x1, x2) + +inst_503:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82f; op2val:0x3fa; +valaddr_reg:x4; val_offset:954*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 954*FLEN/8, x7, x1, x2) + +inst_504:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x23f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x369 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x823f; op2val:0x7b69; +valaddr_reg:x4; val_offset:956*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 956*FLEN/8, x7, x1, x2) + +inst_505:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x369 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x23f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b69; op2val:0x823f; +valaddr_reg:x4; val_offset:958*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 958*FLEN/8, x7, x1, x2) + +inst_506:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x23f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x823f; op2val:0x3fa; +valaddr_reg:x4; val_offset:960*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 960*FLEN/8, x7, x1, x2) + +inst_507:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82f; op2val:0x28e; +valaddr_reg:x4; val_offset:962*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 962*FLEN/8, x7, x1, x2) + +inst_508:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x23f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0c2 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x823f; op2val:0x78c2; +valaddr_reg:x4; val_offset:964*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 964*FLEN/8, x7, x1, x2) + +inst_509:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x23f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x78c2; op2val:0x823f; +valaddr_reg:x4; val_offset:966*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 966*FLEN/8, x7, x1, x2) + +inst_510:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x23f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x823f; op2val:0x28e; +valaddr_reg:x4; val_offset:968*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 968*FLEN/8, x7, x1, x2) + +inst_511:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82f; op2val:0x217; +valaddr_reg:x4; val_offset:970*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 970*FLEN/8, x7, x1, x2) + +inst_512:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x23f and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3cb and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x823f; op2val:0x77cb; +valaddr_reg:x4; val_offset:972*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 972*FLEN/8, x7, x1, x2) + +inst_513:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3cb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x23f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x77cb; op2val:0x823f; +valaddr_reg:x4; val_offset:974*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 974*FLEN/8, x7, x1, x2) + +inst_514:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x23f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x823f; op2val:0x217; +valaddr_reg:x4; val_offset:976*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 976*FLEN/8, x7, x1, x2) + +inst_515:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x195 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82f; op2val:0x8195; +valaddr_reg:x4; val_offset:978*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 978*FLEN/8, x7, x1, x2) + +inst_516:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x23f and fs2 == 1 and fe2 == 0x1d and fm2 == 0x1e7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x823f; op2val:0xf5e7; +valaddr_reg:x4; val_offset:980*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 980*FLEN/8, x7, x1, x2) + +inst_517:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x1e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x23f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf5e7; op2val:0x823f; +valaddr_reg:x4; val_offset:982*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 982*FLEN/8, x7, x1, x2) + +inst_518:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x23f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x195 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x823f; op2val:0x8195; +valaddr_reg:x4; val_offset:984*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 984*FLEN/8, x7, x1, x2) + +inst_519:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82f; op2val:0x80a7; +valaddr_reg:x4; val_offset:986*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 986*FLEN/8, x7, x1, x2) + +inst_520:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x039 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8039; op2val:0xfbff; +valaddr_reg:x4; val_offset:988*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 988*FLEN/8, x7, x1, x2) + +inst_521:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x039 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8039; +valaddr_reg:x4; val_offset:990*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 990*FLEN/8, x7, x1, x2) + +inst_522:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x039 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8039; op2val:0x80a7; +valaddr_reg:x4; val_offset:992*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 992*FLEN/8, x7, x1, x2) + +inst_523:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x039 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82f; op2val:0x8039; +valaddr_reg:x4; val_offset:994*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 994*FLEN/8, x7, x1, x2) + +inst_524:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82f; op2val:0x821e; +valaddr_reg:x4; val_offset:996*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 996*FLEN/8, x7, x1, x2) + +inst_525:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x23f and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3e4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x823f; op2val:0xf7e4; +valaddr_reg:x4; val_offset:998*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 998*FLEN/8, x7, x1, x2) + +inst_526:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x3e4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x23f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf7e4; op2val:0x823f; +valaddr_reg:x4; val_offset:1000*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1000*FLEN/8, x7, x1, x2) + +inst_527:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x23f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x823f; op2val:0x821e; +valaddr_reg:x4; val_offset:1002*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1002*FLEN/8, x7, x1, x2) + +inst_528:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82f; op2val:0x8365; +valaddr_reg:x4; val_offset:1004*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1004*FLEN/8, x7, x1, x2) + +inst_529:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x23f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x252 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x823f; op2val:0xfa52; +valaddr_reg:x4; val_offset:1006*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1006*FLEN/8, x7, x1, x2) + +inst_530:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x252 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x23f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa52; op2val:0x823f; +valaddr_reg:x4; val_offset:1008*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1008*FLEN/8, x7, x1, x2) + +inst_531:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x23f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x823f; op2val:0x8365; +valaddr_reg:x4; val_offset:1010*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1010*FLEN/8, x7, x1, x2) + +inst_532:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x109 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82f; op2val:0x8109; +valaddr_reg:x4; val_offset:1012*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1012*FLEN/8, x7, x1, x2) + +inst_533:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x23f and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3b9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x823f; op2val:0xf3b9; +valaddr_reg:x4; val_offset:1014*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1014*FLEN/8, x7, x1, x2) + +inst_534:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x23f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3b9; op2val:0x823f; +valaddr_reg:x4; val_offset:1016*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1016*FLEN/8, x7, x1, x2) + +inst_535:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x23f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x109 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x823f; op2val:0x8109; +valaddr_reg:x4; val_offset:1018*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1018*FLEN/8, x7, x1, x2) + +inst_536:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82f; op2val:0xf0; +valaddr_reg:x4; val_offset:1020*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1020*FLEN/8, x7, x1, x2) + +inst_537:// fs1 == 1 and fe1 == 0x10 and fm1 == 0x2dc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xc2dc; op2val:0xf0; +valaddr_reg:x4; val_offset:1022*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1022*FLEN/8, x7, x1, x2) + +inst_538:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2dc and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xc2dc; +valaddr_reg:x4; val_offset:1024*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1024*FLEN/8, x7, x1, x2) + +inst_539:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2dc and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82f; op2val:0xc2dc; +valaddr_reg:x4; val_offset:1026*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1026*FLEN/8, x7, x1, x2) + +inst_540:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x038 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf038; op2val:0x739c; +valaddr_reg:x4; val_offset:1028*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1028*FLEN/8, x7, x1, x2) + +inst_541:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x739c; +valaddr_reg:x4; val_offset:1030*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1030*FLEN/8, x7, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_4) + +inst_542:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x038 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf038; op2val:0xfbff; +valaddr_reg:x4; val_offset:1032*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1032*FLEN/8, x7, x1, x2) + +inst_543:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x038 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf038; op2val:0xf038; +valaddr_reg:x4; val_offset:1034*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1034*FLEN/8, x7, x1, x2) + +inst_544:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x038 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x100 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf038; op2val:0x7900; +valaddr_reg:x4; val_offset:1036*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1036*FLEN/8, x7, x1, x2) + +inst_545:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x100 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7900; +valaddr_reg:x4; val_offset:1038*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1038*FLEN/8, x7, x1, x2) + +inst_546:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x038 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x025 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf038; op2val:0x7425; +valaddr_reg:x4; val_offset:1040*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1040*FLEN/8, x7, x1, x2) + +inst_547:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1d and fm2 == 0x025 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7425; +valaddr_reg:x4; val_offset:1042*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1042*FLEN/8, x7, x1, x2) + +inst_548:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x038 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf038; op2val:0x7ab0; +valaddr_reg:x4; val_offset:1044*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1044*FLEN/8, x7, x1, x2) + +inst_549:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7ab0; +valaddr_reg:x4; val_offset:1046*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1046*FLEN/8, x7, x1, x2) + +inst_550:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x038 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf038; op2val:0x7913; +valaddr_reg:x4; val_offset:1048*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1048*FLEN/8, x7, x1, x2) + +inst_551:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7913; +valaddr_reg:x4; val_offset:1050*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1050*FLEN/8, x7, x1, x2) + +inst_552:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x038 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf038; op2val:0xf749; +valaddr_reg:x4; val_offset:1052*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1052*FLEN/8, x7, x1, x2) + +inst_553:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1d and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf749; +valaddr_reg:x4; val_offset:1054*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1054*FLEN/8, x7, x1, x2) + +inst_554:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x038 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x378 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf038; op2val:0xfb78; +valaddr_reg:x4; val_offset:1056*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1056*FLEN/8, x7, x1, x2) + +inst_555:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x378 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfb78; +valaddr_reg:x4; val_offset:1058*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1058*FLEN/8, x7, x1, x2) + +inst_556:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x038 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x21f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf038; op2val:0xfa1f; +valaddr_reg:x4; val_offset:1060*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1060*FLEN/8, x7, x1, x2) + +inst_557:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x21f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfa1f; +valaddr_reg:x4; val_offset:1062*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1062*FLEN/8, x7, x1, x2) + +inst_558:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x038 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf038; op2val:0xf82f; +valaddr_reg:x4; val_offset:1064*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1064*FLEN/8, x7, x1, x2) + +inst_559:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf82f; +valaddr_reg:x4; val_offset:1066*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1066*FLEN/8, x7, x1, x2) + +inst_560:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x038 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17b and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf038; op2val:0x17b; +valaddr_reg:x4; val_offset:1068*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1068*FLEN/8, x7, x1, x2) + +inst_561:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x1aa and fs2 == 0 and fe2 == 0x1a and fm2 == 0x069 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x85aa; op2val:0x6869; +valaddr_reg:x4; val_offset:1070*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1070*FLEN/8, x7, x1, x2) + +inst_562:// fs1 == 0 and fe1 == 0x1a and fm1 == 0x069 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x1aa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x6869; op2val:0x85aa; +valaddr_reg:x4; val_offset:1072*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1072*FLEN/8, x7, x1, x2) + +inst_563:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x1aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17b and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x85aa; op2val:0x17b; +valaddr_reg:x4; val_offset:1074*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1074*FLEN/8, x7, x1, x2) + +inst_564:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x038 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x1aa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf038; op2val:0x85aa; +valaddr_reg:x4; val_offset:1076*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1076*FLEN/8, x7, x1, x2) + +inst_565:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x038 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf038; op2val:0xe; +valaddr_reg:x4; val_offset:1078*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1078*FLEN/8, x7, x1, x2) + +inst_566:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 0 and fe2 == 0x1c and fm2 == 0x035 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x800e; op2val:0x7035; +valaddr_reg:x4; val_offset:1080*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1080*FLEN/8, x7, x1, x2) + +inst_567:// fs1 == 0 and fe1 == 0x1c and fm1 == 0x035 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7035; op2val:0x800e; +valaddr_reg:x4; val_offset:1082*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1082*FLEN/8, x7, x1, x2) + +inst_568:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x800e; op2val:0xe; +valaddr_reg:x4; val_offset:1084*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1084*FLEN/8, x7, x1, x2) + +inst_569:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x038 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf038; op2val:0x800e; +valaddr_reg:x4; val_offset:1086*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1086*FLEN/8, x7, x1, x2) + +inst_570:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x038 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf038; op2val:0x3fa; +valaddr_reg:x4; val_offset:1088*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1088*FLEN/8, x7, x1, x2) + +inst_571:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x1aa and fs2 == 0 and fe2 == 0x1b and fm2 == 0x1ed and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x85aa; op2val:0x6ded; +valaddr_reg:x4; val_offset:1090*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1090*FLEN/8, x7, x1, x2) + +inst_572:// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ed and fs2 == 1 and fe2 == 0x01 and fm2 == 0x1aa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ded; op2val:0x85aa; +valaddr_reg:x4; val_offset:1092*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1092*FLEN/8, x7, x1, x2) + +inst_573:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x1aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x85aa; op2val:0x3fa; +valaddr_reg:x4; val_offset:1094*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1094*FLEN/8, x7, x1, x2) + +inst_574:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x038 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf038; op2val:0x28e; +valaddr_reg:x4; val_offset:1096*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1096*FLEN/8, x7, x1, x2) + +inst_575:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x1aa and fs2 == 0 and fe2 == 0x1a and fm2 == 0x39d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x85aa; op2val:0x6b9d; +valaddr_reg:x4; val_offset:1098*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1098*FLEN/8, x7, x1, x2) + +inst_576:// fs1 == 0 and fe1 == 0x1a and fm1 == 0x39d and fs2 == 1 and fe2 == 0x01 and fm2 == 0x1aa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x6b9d; op2val:0x85aa; +valaddr_reg:x4; val_offset:1100*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1100*FLEN/8, x7, x1, x2) + +inst_577:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x1aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x85aa; op2val:0x28e; +valaddr_reg:x4; val_offset:1102*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1102*FLEN/8, x7, x1, x2) + +inst_578:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x038 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf038; op2val:0x217; +valaddr_reg:x4; val_offset:1104*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1104*FLEN/8, x7, x1, x2) + +inst_579:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x1aa and fs2 == 0 and fe2 == 0x1a and fm2 == 0x23c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x85aa; op2val:0x6a3c; +valaddr_reg:x4; val_offset:1106*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1106*FLEN/8, x7, x1, x2) + +inst_580:// fs1 == 0 and fe1 == 0x1a and fm1 == 0x23c and fs2 == 1 and fe2 == 0x01 and fm2 == 0x1aa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x6a3c; op2val:0x85aa; +valaddr_reg:x4; val_offset:1108*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1108*FLEN/8, x7, x1, x2) + +inst_581:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x1aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x85aa; op2val:0x217; +valaddr_reg:x4; val_offset:1110*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1110*FLEN/8, x7, x1, x2) + +inst_582:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x038 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x195 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf038; op2val:0x8195; +valaddr_reg:x4; val_offset:1112*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1112*FLEN/8, x7, x1, x2) + +inst_583:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x1aa and fs2 == 1 and fe2 == 0x1a and fm2 == 0x0b9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x85aa; op2val:0xe8b9; +valaddr_reg:x4; val_offset:1114*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1114*FLEN/8, x7, x1, x2) + +inst_584:// fs1 == 1 and fe1 == 0x1a and fm1 == 0x0b9 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x1aa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xe8b9; op2val:0x85aa; +valaddr_reg:x4; val_offset:1116*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1116*FLEN/8, x7, x1, x2) + +inst_585:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x1aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x195 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x85aa; op2val:0x8195; +valaddr_reg:x4; val_offset:1118*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1118*FLEN/8, x7, x1, x2) + +inst_586:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x038 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf038; op2val:0x80a7; +valaddr_reg:x4; val_offset:1120*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1120*FLEN/8, x7, x1, x2) + +inst_587:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x091 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0dd and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8091; op2val:0xf0dd; +valaddr_reg:x4; val_offset:1122*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1122*FLEN/8, x7, x1, x2) + +inst_588:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x0dd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x091 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0dd; op2val:0x8091; +valaddr_reg:x4; val_offset:1124*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1124*FLEN/8, x7, x1, x2) + +inst_589:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x091 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8091; op2val:0x80a7; +valaddr_reg:x4; val_offset:1126*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1126*FLEN/8, x7, x1, x2) + +inst_590:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x038 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x091 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf038; op2val:0x8091; +valaddr_reg:x4; val_offset:1128*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1128*FLEN/8, x7, x1, x2) + +inst_591:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x038 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf038; op2val:0x821e; +valaddr_reg:x4; val_offset:1130*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1130*FLEN/8, x7, x1, x2) + +inst_592:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x1aa and fs2 == 1 and fe2 == 0x1a and fm2 == 0x250 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x85aa; op2val:0xea50; +valaddr_reg:x4; val_offset:1132*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1132*FLEN/8, x7, x1, x2) + +inst_593:// fs1 == 1 and fe1 == 0x1a and fm1 == 0x250 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x1aa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xea50; op2val:0x85aa; +valaddr_reg:x4; val_offset:1134*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1134*FLEN/8, x7, x1, x2) + +inst_594:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x1aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x85aa; op2val:0x821e; +valaddr_reg:x4; val_offset:1136*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1136*FLEN/8, x7, x1, x2) + +inst_595:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x038 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf038; op2val:0x8365; +valaddr_reg:x4; val_offset:1138*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1138*FLEN/8, x7, x1, x2) + +inst_596:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x1aa and fs2 == 1 and fe2 == 0x1b and fm2 == 0x10f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x85aa; op2val:0xed0f; +valaddr_reg:x4; val_offset:1140*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1140*FLEN/8, x7, x1, x2) + +inst_597:// fs1 == 1 and fe1 == 0x1b and fm1 == 0x10f and fs2 == 1 and fe2 == 0x01 and fm2 == 0x1aa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xed0f; op2val:0x85aa; +valaddr_reg:x4; val_offset:1142*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1142*FLEN/8, x7, x1, x2) + +inst_598:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x1aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x85aa; op2val:0x8365; +valaddr_reg:x4; val_offset:1144*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1144*FLEN/8, x7, x1, x2) + +inst_599:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x038 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x109 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf038; op2val:0x8109; +valaddr_reg:x4; val_offset:1146*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1146*FLEN/8, x7, x1, x2) + +inst_600:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x1aa and fs2 == 1 and fe2 == 0x19 and fm2 == 0x22e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x85aa; op2val:0xe62e; +valaddr_reg:x4; val_offset:1148*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1148*FLEN/8, x7, x1, x2) + +inst_601:// fs1 == 1 and fe1 == 0x19 and fm1 == 0x22e and fs2 == 1 and fe2 == 0x01 and fm2 == 0x1aa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xe62e; op2val:0x85aa; +valaddr_reg:x4; val_offset:1150*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1150*FLEN/8, x7, x1, x2) + +inst_602:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x1aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x109 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x85aa; op2val:0x8109; +valaddr_reg:x4; val_offset:1152*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1152*FLEN/8, x7, x1, x2) + +inst_603:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x038 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf038; op2val:0xf0; +valaddr_reg:x4; val_offset:1154*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1154*FLEN/8, x7, x1, x2) + +inst_604:// fs1 == 1 and fe1 == 0x12 and fm1 == 0x052 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xc852; op2val:0xf0; +valaddr_reg:x4; val_offset:1156*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1156*FLEN/8, x7, x1, x2) + +inst_605:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x052 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xc852; +valaddr_reg:x4; val_offset:1158*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1158*FLEN/8, x7, x1, x2) + +inst_606:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x038 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x052 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf038; op2val:0xc852; +valaddr_reg:x4; val_offset:1160*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1160*FLEN/8, x7, x1, x2) + +inst_607:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17b and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x17b; op2val:0x739c; +valaddr_reg:x4; val_offset:1162*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1162*FLEN/8, x7, x1, x2) + +inst_608:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x184 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7584; op2val:0x739c; +valaddr_reg:x4; val_offset:1164*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1164*FLEN/8, x7, x1, x2) + +inst_609:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17b and fs2 == 0 and fe2 == 0x1d and fm2 == 0x184 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x17b; op2val:0x7584; +valaddr_reg:x4; val_offset:1166*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1166*FLEN/8, x7, x1, x2) + +inst_610:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x17b; op2val:0x17b; +valaddr_reg:x4; val_offset:1168*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1168*FLEN/8, x7, x1, x2) + +inst_611:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x100 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x17b; op2val:0x7900; +valaddr_reg:x4; val_offset:1170*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1170*FLEN/8, x7, x1, x2) + +inst_612:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x184 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x100 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7584; op2val:0x7900; +valaddr_reg:x4; val_offset:1172*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1172*FLEN/8, x7, x1, x2) + +inst_613:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17b and fs2 == 0 and fe2 == 0x1d and fm2 == 0x025 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x17b; op2val:0x7425; +valaddr_reg:x4; val_offset:1174*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1174*FLEN/8, x7, x1, x2) + +inst_614:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x184 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x025 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7584; op2val:0x7425; +valaddr_reg:x4; val_offset:1176*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1176*FLEN/8, x7, x1, x2) + +inst_615:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x17b; op2val:0x7ab0; +valaddr_reg:x4; val_offset:1178*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1178*FLEN/8, x7, x1, x2) + +inst_616:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x184 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7584; op2val:0x7ab0; +valaddr_reg:x4; val_offset:1180*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1180*FLEN/8, x7, x1, x2) + +inst_617:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x17b; op2val:0x7913; +valaddr_reg:x4; val_offset:1182*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1182*FLEN/8, x7, x1, x2) + +inst_618:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x184 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7584; op2val:0x7913; +valaddr_reg:x4; val_offset:1184*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1184*FLEN/8, x7, x1, x2) + +inst_619:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17b and fs2 == 1 and fe2 == 0x1d and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x17b; op2val:0xf749; +valaddr_reg:x4; val_offset:1186*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1186*FLEN/8, x7, x1, x2) + +inst_620:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x184 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7584; op2val:0xf749; +valaddr_reg:x4; val_offset:1188*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1188*FLEN/8, x7, x1, x2) + +inst_621:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x378 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x17b; op2val:0xfb78; +valaddr_reg:x4; val_offset:1190*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1190*FLEN/8, x7, x1, x2) + +inst_622:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x184 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x378 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7584; op2val:0xfb78; +valaddr_reg:x4; val_offset:1192*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1192*FLEN/8, x7, x1, x2) + +inst_623:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x21f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x17b; op2val:0xfa1f; +valaddr_reg:x4; val_offset:1194*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1194*FLEN/8, x7, x1, x2) + +inst_624:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x184 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x21f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7584; op2val:0xfa1f; +valaddr_reg:x4; val_offset:1196*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1196*FLEN/8, x7, x1, x2) + +inst_625:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x17b; op2val:0xf82f; +valaddr_reg:x4; val_offset:1198*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1198*FLEN/8, x7, x1, x2) + +inst_626:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x184 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7584; op2val:0xf82f; +valaddr_reg:x4; val_offset:1200*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1200*FLEN/8, x7, x1, x2) + +inst_627:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17b and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x17b; op2val:0xf038; +valaddr_reg:x4; val_offset:1202*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1202*FLEN/8, x7, x1, x2) + +inst_628:// fs1 == 0 and fe1 == 0x1a and fm1 == 0x069 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x6869; op2val:0xf038; +valaddr_reg:x4; val_offset:1204*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1204*FLEN/8, x7, x1, x2) + +inst_629:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17b and fs2 == 0 and fe2 == 0x1a and fm2 == 0x069 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x17b; op2val:0x6869; +valaddr_reg:x4; val_offset:1206*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1206*FLEN/8, x7, x1, x2) + +inst_630:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x17b; op2val:0xe; +valaddr_reg:x4; val_offset:1208*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1208*FLEN/8, x7, x1, x2) + +inst_631:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x003 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1a6 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3; op2val:0x5a6; +valaddr_reg:x4; val_offset:1210*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1210*FLEN/8, x7, x1, x2) + +inst_632:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x1a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x003 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x5a6; op2val:0x3; +valaddr_reg:x4; val_offset:1212*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1212*FLEN/8, x7, x1, x2) + +inst_633:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x003 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3; op2val:0xe; +valaddr_reg:x4; val_offset:1214*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1214*FLEN/8, x7, x1, x2) + +inst_634:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x003 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x17b; op2val:0x3; +valaddr_reg:x4; val_offset:1216*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1216*FLEN/8, x7, x1, x2) + +inst_635:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x17b; op2val:0x3fa; +valaddr_reg:x4; val_offset:1218*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1218*FLEN/8, x7, x1, x2) + +inst_636:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fa; op2val:0x17b; +valaddr_reg:x4; val_offset:1220*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1220*FLEN/8, x7, x1, x2) + +inst_637:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x17b; op2val:0x28e; +valaddr_reg:x4; val_offset:1222*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1222*FLEN/8, x7, x1, x2) + +inst_638:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x28e; op2val:0x17b; +valaddr_reg:x4; val_offset:1224*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1224*FLEN/8, x7, x1, x2) + +inst_639:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x17b; op2val:0x217; +valaddr_reg:x4; val_offset:1226*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1226*FLEN/8, x7, x1, x2) + +inst_640:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x217; op2val:0x17b; +valaddr_reg:x4; val_offset:1228*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1228*FLEN/8, x7, x1, x2) + +inst_641:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x195 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x17b; op2val:0x8195; +valaddr_reg:x4; val_offset:1230*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1230*FLEN/8, x7, x1, x2) + +inst_642:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x195 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17b and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8195; op2val:0x17b; +valaddr_reg:x4; val_offset:1232*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1232*FLEN/8, x7, x1, x2) + +inst_643:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x17b; op2val:0x80a7; +valaddr_reg:x4; val_offset:1234*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1234*FLEN/8, x7, x1, x2) + +inst_644:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x025 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x287 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x25; op2val:0x8687; +valaddr_reg:x4; val_offset:1236*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1236*FLEN/8, x7, x1, x2) + +inst_645:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x287 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x025 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8687; op2val:0x25; +valaddr_reg:x4; val_offset:1238*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1238*FLEN/8, x7, x1, x2) + +inst_646:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x025 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x25; op2val:0x80a7; +valaddr_reg:x4; val_offset:1240*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1240*FLEN/8, x7, x1, x2) + +inst_647:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x025 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x17b; op2val:0x25; +valaddr_reg:x4; val_offset:1242*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1242*FLEN/8, x7, x1, x2) + +inst_648:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x17b; op2val:0x821e; +valaddr_reg:x4; val_offset:1244*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1244*FLEN/8, x7, x1, x2) + +inst_649:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17b and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x821e; op2val:0x17b; +valaddr_reg:x4; val_offset:1246*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1246*FLEN/8, x7, x1, x2) + +inst_650:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x17b; op2val:0x8365; +valaddr_reg:x4; val_offset:1248*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1248*FLEN/8, x7, x1, x2) + +inst_651:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17b and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8365; op2val:0x17b; +valaddr_reg:x4; val_offset:1250*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1250*FLEN/8, x7, x1, x2) + +inst_652:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x109 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x17b; op2val:0x8109; +valaddr_reg:x4; val_offset:1252*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1252*FLEN/8, x7, x1, x2) + +inst_653:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x109 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17b and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8109; op2val:0x17b; +valaddr_reg:x4; val_offset:1254*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1254*FLEN/8, x7, x1, x2) + +inst_654:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x17b; op2val:0xf0; +valaddr_reg:x4; val_offset:1256*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1256*FLEN/8, x7, x1, x2) + +inst_655:// fs1 == 0 and fe1 == 0x10 and fm1 == 0x084 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x4084; op2val:0xf0; +valaddr_reg:x4; val_offset:1258*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1258*FLEN/8, x7, x1, x2) + +inst_656:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x084 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x4084; +valaddr_reg:x4; val_offset:1260*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1260*FLEN/8, x7, x1, x2) + +inst_657:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x084 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x17b; op2val:0x4084; +valaddr_reg:x4; val_offset:1262*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1262*FLEN/8, x7, x1, x2) + +inst_658:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xe; op2val:0x739c; +valaddr_reg:x4; val_offset:1264*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1264*FLEN/8, x7, x1, x2) + +inst_659:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x739c; +valaddr_reg:x4; val_offset:1266*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1266*FLEN/8, x7, x1, x2) + +inst_660:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xe; op2val:0x7bff; +valaddr_reg:x4; val_offset:1268*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1268*FLEN/8, x7, x1, x2) + +inst_661:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xe; op2val:0xe; +valaddr_reg:x4; val_offset:1270*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1270*FLEN/8, x7, x1, x2) + +inst_662:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x100 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xe; op2val:0x7900; +valaddr_reg:x4; val_offset:1272*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1272*FLEN/8, x7, x1, x2) + +inst_663:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x100 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7900; +valaddr_reg:x4; val_offset:1274*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1274*FLEN/8, x7, x1, x2) + +inst_664:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x025 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xe; op2val:0x7425; +valaddr_reg:x4; val_offset:1276*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1276*FLEN/8, x7, x1, x2) + +inst_665:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1d and fm2 == 0x025 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7425; +valaddr_reg:x4; val_offset:1278*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1278*FLEN/8, x7, x1, x2) + +inst_666:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xe; op2val:0x7ab0; +valaddr_reg:x4; val_offset:1280*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1280*FLEN/8, x7, x1, x2) + +inst_667:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7ab0; +valaddr_reg:x4; val_offset:1282*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1282*FLEN/8, x7, x1, x2) + +inst_668:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xe; op2val:0x7913; +valaddr_reg:x4; val_offset:1284*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1284*FLEN/8, x7, x1, x2) + +inst_669:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7913; +valaddr_reg:x4; val_offset:1286*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1286*FLEN/8, x7, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_5) + +inst_670:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 1 and fe2 == 0x1d and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xe; op2val:0xf749; +valaddr_reg:x4; val_offset:1288*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1288*FLEN/8, x7, x1, x2) + +inst_671:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1d and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xf749; +valaddr_reg:x4; val_offset:1290*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1290*FLEN/8, x7, x1, x2) + +inst_672:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x378 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xe; op2val:0xfb78; +valaddr_reg:x4; val_offset:1292*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1292*FLEN/8, x7, x1, x2) + +inst_673:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x378 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xfb78; +valaddr_reg:x4; val_offset:1294*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1294*FLEN/8, x7, x1, x2) + +inst_674:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x21f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xe; op2val:0xfa1f; +valaddr_reg:x4; val_offset:1296*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1296*FLEN/8, x7, x1, x2) + +inst_675:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x21f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xfa1f; +valaddr_reg:x4; val_offset:1298*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1298*FLEN/8, x7, x1, x2) + +inst_676:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xe; op2val:0xf82f; +valaddr_reg:x4; val_offset:1300*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1300*FLEN/8, x7, x1, x2) + +inst_677:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xf82f; +valaddr_reg:x4; val_offset:1302*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1302*FLEN/8, x7, x1, x2) + +inst_678:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xe; op2val:0xf038; +valaddr_reg:x4; val_offset:1304*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1304*FLEN/8, x7, x1, x2) + +inst_679:// fs1 == 0 and fe1 == 0x1c and fm1 == 0x035 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7035; op2val:0xf038; +valaddr_reg:x4; val_offset:1306*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1306*FLEN/8, x7, x1, x2) + +inst_680:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 0 and fe2 == 0x1c and fm2 == 0x035 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xe; op2val:0x7035; +valaddr_reg:x4; val_offset:1308*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1308*FLEN/8, x7, x1, x2) + +inst_681:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xe; op2val:0x17b; +valaddr_reg:x4; val_offset:1310*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1310*FLEN/8, x7, x1, x2) + +inst_682:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x1a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x5a6; op2val:0x17b; +valaddr_reg:x4; val_offset:1312*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1312*FLEN/8, x7, x1, x2) + +inst_683:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1a6 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xe; op2val:0x5a6; +valaddr_reg:x4; val_offset:1314*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1314*FLEN/8, x7, x1, x2) + +inst_684:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xe; op2val:0x3fa; +valaddr_reg:x4; val_offset:1316*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1316*FLEN/8, x7, x1, x2) + +inst_685:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x1a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x5a6; op2val:0xa; +valaddr_reg:x4; val_offset:1318*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1318*FLEN/8, x7, x1, x2) + +inst_686:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1a6 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xa; op2val:0x5a6; +valaddr_reg:x4; val_offset:1320*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1320*FLEN/8, x7, x1, x2) + +inst_687:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x1a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x5a6; op2val:0x3fa; +valaddr_reg:x4; val_offset:1322*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1322*FLEN/8, x7, x1, x2) + +inst_688:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xe; op2val:0x28e; +valaddr_reg:x4; val_offset:1324*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1324*FLEN/8, x7, x1, x2) + +inst_689:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x1a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x006 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x5a6; op2val:0x6; +valaddr_reg:x4; val_offset:1326*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1326*FLEN/8, x7, x1, x2) + +inst_690:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x006 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1a6 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x6; op2val:0x5a6; +valaddr_reg:x4; val_offset:1328*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1328*FLEN/8, x7, x1, x2) + +inst_691:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x1a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x5a6; op2val:0x28e; +valaddr_reg:x4; val_offset:1330*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1330*FLEN/8, x7, x1, x2) + +inst_692:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xe; op2val:0x217; +valaddr_reg:x4; val_offset:1332*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1332*FLEN/8, x7, x1, x2) + +inst_693:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x1a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x005 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x5a6; op2val:0x5; +valaddr_reg:x4; val_offset:1334*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1334*FLEN/8, x7, x1, x2) + +inst_694:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x005 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1a6 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x5; op2val:0x5a6; +valaddr_reg:x4; val_offset:1336*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1336*FLEN/8, x7, x1, x2) + +inst_695:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x1a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x5a6; op2val:0x217; +valaddr_reg:x4; val_offset:1338*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1338*FLEN/8, x7, x1, x2) + +inst_696:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x195 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xe; op2val:0x8195; +valaddr_reg:x4; val_offset:1340*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1340*FLEN/8, x7, x1, x2) + +inst_697:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x1a6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x004 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x5a6; op2val:0x8004; +valaddr_reg:x4; val_offset:1342*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1342*FLEN/8, x7, x1, x2) + +inst_698:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x004 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1a6 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8004; op2val:0x5a6; +valaddr_reg:x4; val_offset:1344*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1344*FLEN/8, x7, x1, x2) + +inst_699:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x1a6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x195 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x5a6; op2val:0x8195; +valaddr_reg:x4; val_offset:1346*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1346*FLEN/8, x7, x1, x2) + +inst_700:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xe; op2val:0x80a7; +valaddr_reg:x4; val_offset:1348*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1348*FLEN/8, x7, x1, x2) + +inst_701:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x090 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x010 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x90; op2val:0x8010; +valaddr_reg:x4; val_offset:1350*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1350*FLEN/8, x7, x1, x2) + +inst_702:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x010 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x090 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8010; op2val:0x90; +valaddr_reg:x4; val_offset:1352*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1352*FLEN/8, x7, x1, x2) + +inst_703:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x090 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x90; op2val:0x80a7; +valaddr_reg:x4; val_offset:1354*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1354*FLEN/8, x7, x1, x2) + +inst_704:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x090 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xe; op2val:0x90; +valaddr_reg:x4; val_offset:1356*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1356*FLEN/8, x7, x1, x2) + +inst_705:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xe; op2val:0x821e; +valaddr_reg:x4; val_offset:1358*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1358*FLEN/8, x7, x1, x2) + +inst_706:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x1a6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x005 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x5a6; op2val:0x8005; +valaddr_reg:x4; val_offset:1360*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1360*FLEN/8, x7, x1, x2) + +inst_707:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x005 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1a6 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8005; op2val:0x5a6; +valaddr_reg:x4; val_offset:1362*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1362*FLEN/8, x7, x1, x2) + +inst_708:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x1a6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x5a6; op2val:0x821e; +valaddr_reg:x4; val_offset:1364*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1364*FLEN/8, x7, x1, x2) + +inst_709:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xe; op2val:0x8365; +valaddr_reg:x4; val_offset:1366*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1366*FLEN/8, x7, x1, x2) + +inst_710:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x1a6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x008 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x5a6; op2val:0x8008; +valaddr_reg:x4; val_offset:1368*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1368*FLEN/8, x7, x1, x2) + +inst_711:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x008 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1a6 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8008; op2val:0x5a6; +valaddr_reg:x4; val_offset:1370*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1370*FLEN/8, x7, x1, x2) + +inst_712:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x1a6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x5a6; op2val:0x8365; +valaddr_reg:x4; val_offset:1372*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1372*FLEN/8, x7, x1, x2) + +inst_713:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x109 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xe; op2val:0x8109; +valaddr_reg:x4; val_offset:1374*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1374*FLEN/8, x7, x1, x2) + +inst_714:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x1a6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x5a6; op2val:0x8002; +valaddr_reg:x4; val_offset:1376*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1376*FLEN/8, x7, x1, x2) + +inst_715:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1a6 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8002; op2val:0x5a6; +valaddr_reg:x4; val_offset:1378*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1378*FLEN/8, x7, x1, x2) + +inst_716:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x1a6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x109 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x5a6; op2val:0x8109; +valaddr_reg:x4; val_offset:1380*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1380*FLEN/8, x7, x1, x2) + +inst_717:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xe; op2val:0xf0; +valaddr_reg:x4; val_offset:1382*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1382*FLEN/8, x7, x1, x2) + +inst_718:// fs1 == 0 and fe1 == 0x12 and fm1 == 0x04f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x484f; op2val:0xf0; +valaddr_reg:x4; val_offset:1384*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1384*FLEN/8, x7, x1, x2) + +inst_719:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x04f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x484f; +valaddr_reg:x4; val_offset:1386*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1386*FLEN/8, x7, x1, x2) + +inst_720:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 0 and fe2 == 0x12 and fm2 == 0x04f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xe; op2val:0x484f; +valaddr_reg:x4; val_offset:1388*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1388*FLEN/8, x7, x1, x2) + +inst_721:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fa and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fa; op2val:0x739c; +valaddr_reg:x4; val_offset:1390*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1390*FLEN/8, x7, x1, x2) + +inst_722:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x369 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b69; op2val:0x739c; +valaddr_reg:x4; val_offset:1392*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1392*FLEN/8, x7, x1, x2) + +inst_723:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fa and fs2 == 0 and fe2 == 0x1e and fm2 == 0x369 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fa; op2val:0x7b69; +valaddr_reg:x4; val_offset:1394*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1394*FLEN/8, x7, x1, x2) + +inst_724:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fa; op2val:0x3fa; +valaddr_reg:x4; val_offset:1396*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1396*FLEN/8, x7, x1, x2) + +inst_725:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fa and fs2 == 0 and fe2 == 0x1e and fm2 == 0x100 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fa; op2val:0x7900; +valaddr_reg:x4; val_offset:1398*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1398*FLEN/8, x7, x1, x2) + +inst_726:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x369 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x100 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b69; op2val:0x7900; +valaddr_reg:x4; val_offset:1400*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1400*FLEN/8, x7, x1, x2) + +inst_727:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fa and fs2 == 0 and fe2 == 0x1d and fm2 == 0x025 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fa; op2val:0x7425; +valaddr_reg:x4; val_offset:1402*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1402*FLEN/8, x7, x1, x2) + +inst_728:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x369 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x025 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b69; op2val:0x7425; +valaddr_reg:x4; val_offset:1404*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1404*FLEN/8, x7, x1, x2) + +inst_729:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fa and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fa; op2val:0x7ab0; +valaddr_reg:x4; val_offset:1406*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1406*FLEN/8, x7, x1, x2) + +inst_730:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x369 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b69; op2val:0x7ab0; +valaddr_reg:x4; val_offset:1408*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1408*FLEN/8, x7, x1, x2) + +inst_731:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fa and fs2 == 0 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fa; op2val:0x7913; +valaddr_reg:x4; val_offset:1410*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1410*FLEN/8, x7, x1, x2) + +inst_732:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x369 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b69; op2val:0x7913; +valaddr_reg:x4; val_offset:1412*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1412*FLEN/8, x7, x1, x2) + +inst_733:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fa and fs2 == 1 and fe2 == 0x1d and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fa; op2val:0xf749; +valaddr_reg:x4; val_offset:1414*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1414*FLEN/8, x7, x1, x2) + +inst_734:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x369 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b69; op2val:0xf749; +valaddr_reg:x4; val_offset:1416*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1416*FLEN/8, x7, x1, x2) + +inst_735:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fa and fs2 == 1 and fe2 == 0x1e and fm2 == 0x378 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fa; op2val:0xfb78; +valaddr_reg:x4; val_offset:1418*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1418*FLEN/8, x7, x1, x2) + +inst_736:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x369 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x378 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b69; op2val:0xfb78; +valaddr_reg:x4; val_offset:1420*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1420*FLEN/8, x7, x1, x2) + +inst_737:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fa and fs2 == 1 and fe2 == 0x1e and fm2 == 0x21f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fa; op2val:0xfa1f; +valaddr_reg:x4; val_offset:1422*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1422*FLEN/8, x7, x1, x2) + +inst_738:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x369 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x21f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b69; op2val:0xfa1f; +valaddr_reg:x4; val_offset:1424*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1424*FLEN/8, x7, x1, x2) + +inst_739:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fa and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fa; op2val:0xf82f; +valaddr_reg:x4; val_offset:1426*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1426*FLEN/8, x7, x1, x2) + +inst_740:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x369 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b69; op2val:0xf82f; +valaddr_reg:x4; val_offset:1428*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1428*FLEN/8, x7, x1, x2) + +inst_741:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fa and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fa; op2val:0xf038; +valaddr_reg:x4; val_offset:1430*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1430*FLEN/8, x7, x1, x2) + +inst_742:// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ed and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ded; op2val:0xf038; +valaddr_reg:x4; val_offset:1432*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1432*FLEN/8, x7, x1, x2) + +inst_743:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fa and fs2 == 0 and fe2 == 0x1b and fm2 == 0x1ed and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fa; op2val:0x6ded; +valaddr_reg:x4; val_offset:1434*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1434*FLEN/8, x7, x1, x2) + +inst_744:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fa; op2val:0xe; +valaddr_reg:x4; val_offset:1436*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1436*FLEN/8, x7, x1, x2) + +inst_745:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xa; op2val:0xe; +valaddr_reg:x4; val_offset:1438*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1438*FLEN/8, x7, x1, x2) + +inst_746:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fa; op2val:0xa; +valaddr_reg:x4; val_offset:1440*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1440*FLEN/8, x7, x1, x2) + +inst_747:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fa; op2val:0x28e; +valaddr_reg:x4; val_offset:1442*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1442*FLEN/8, x7, x1, x2) + +inst_748:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x28e; op2val:0x3fa; +valaddr_reg:x4; val_offset:1444*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1444*FLEN/8, x7, x1, x2) + +inst_749:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fa; op2val:0x217; +valaddr_reg:x4; val_offset:1446*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1446*FLEN/8, x7, x1, x2) + +inst_750:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x217; op2val:0x3fa; +valaddr_reg:x4; val_offset:1448*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1448*FLEN/8, x7, x1, x2) + +inst_751:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x195 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fa; op2val:0x8195; +valaddr_reg:x4; val_offset:1450*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1450*FLEN/8, x7, x1, x2) + +inst_752:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x195 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8195; op2val:0x3fa; +valaddr_reg:x4; val_offset:1452*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1452*FLEN/8, x7, x1, x2) + +inst_753:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fa; op2val:0x80a7; +valaddr_reg:x4; val_offset:1454*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1454*FLEN/8, x7, x1, x2) + +inst_754:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x065 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x287 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x65; op2val:0x8687; +valaddr_reg:x4; val_offset:1456*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1456*FLEN/8, x7, x1, x2) + +inst_755:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x287 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x065 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8687; op2val:0x65; +valaddr_reg:x4; val_offset:1458*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1458*FLEN/8, x7, x1, x2) + +inst_756:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x065 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x65; op2val:0x80a7; +valaddr_reg:x4; val_offset:1460*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1460*FLEN/8, x7, x1, x2) + +inst_757:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x065 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fa; op2val:0x65; +valaddr_reg:x4; val_offset:1462*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1462*FLEN/8, x7, x1, x2) + +inst_758:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fa; op2val:0x821e; +valaddr_reg:x4; val_offset:1464*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1464*FLEN/8, x7, x1, x2) + +inst_759:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x821e; op2val:0x3fa; +valaddr_reg:x4; val_offset:1466*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1466*FLEN/8, x7, x1, x2) + +inst_760:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fa; op2val:0x8365; +valaddr_reg:x4; val_offset:1468*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1468*FLEN/8, x7, x1, x2) + +inst_761:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8365; op2val:0x3fa; +valaddr_reg:x4; val_offset:1470*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1470*FLEN/8, x7, x1, x2) + +inst_762:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x109 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fa; op2val:0x8109; +valaddr_reg:x4; val_offset:1472*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1472*FLEN/8, x7, x1, x2) + +inst_763:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x109 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8109; op2val:0x3fa; +valaddr_reg:x4; val_offset:1474*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1474*FLEN/8, x7, x1, x2) + +inst_764:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fa; op2val:0xf0; +valaddr_reg:x4; val_offset:1476*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1476*FLEN/8, x7, x1, x2) + +inst_765:// fs1 == 0 and fe1 == 0x11 and fm1 == 0x212 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x4612; op2val:0xf0; +valaddr_reg:x4; val_offset:1478*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1478*FLEN/8, x7, x1, x2) + +inst_766:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x212 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x4612; +valaddr_reg:x4; val_offset:1480*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1480*FLEN/8, x7, x1, x2) + +inst_767:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fa and fs2 == 0 and fe2 == 0x11 and fm2 == 0x212 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fa; op2val:0x4612; +valaddr_reg:x4; val_offset:1482*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1482*FLEN/8, x7, x1, x2) + +inst_768:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x28e; op2val:0x739c; +valaddr_reg:x4; val_offset:1484*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1484*FLEN/8, x7, x1, x2) + +inst_769:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x78c2; op2val:0x739c; +valaddr_reg:x4; val_offset:1486*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1486*FLEN/8, x7, x1, x2) + +inst_770:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0c2 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x28e; op2val:0x78c2; +valaddr_reg:x4; val_offset:1488*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1488*FLEN/8, x7, x1, x2) + +inst_771:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x28e; op2val:0x28e; +valaddr_reg:x4; val_offset:1490*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1490*FLEN/8, x7, x1, x2) + +inst_772:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x100 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x28e; op2val:0x7900; +valaddr_reg:x4; val_offset:1492*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1492*FLEN/8, x7, x1, x2) + +inst_773:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x100 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x78c2; op2val:0x7900; +valaddr_reg:x4; val_offset:1494*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1494*FLEN/8, x7, x1, x2) + +inst_774:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x025 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x28e; op2val:0x7425; +valaddr_reg:x4; val_offset:1496*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1496*FLEN/8, x7, x1, x2) + +inst_775:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x025 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x78c2; op2val:0x7425; +valaddr_reg:x4; val_offset:1498*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1498*FLEN/8, x7, x1, x2) + +inst_776:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x28e; op2val:0x7ab0; +valaddr_reg:x4; val_offset:1500*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1500*FLEN/8, x7, x1, x2) + +inst_777:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x78c2; op2val:0x7ab0; +valaddr_reg:x4; val_offset:1502*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1502*FLEN/8, x7, x1, x2) + +inst_778:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x28e; op2val:0x7913; +valaddr_reg:x4; val_offset:1504*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1504*FLEN/8, x7, x1, x2) + +inst_779:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x78c2; op2val:0x7913; +valaddr_reg:x4; val_offset:1506*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1506*FLEN/8, x7, x1, x2) + +inst_780:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e and fs2 == 1 and fe2 == 0x1d and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x28e; op2val:0xf749; +valaddr_reg:x4; val_offset:1508*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1508*FLEN/8, x7, x1, x2) + +inst_781:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x78c2; op2val:0xf749; +valaddr_reg:x4; val_offset:1510*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1510*FLEN/8, x7, x1, x2) + +inst_782:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x378 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x28e; op2val:0xfb78; +valaddr_reg:x4; val_offset:1512*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1512*FLEN/8, x7, x1, x2) + +inst_783:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x378 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x78c2; op2val:0xfb78; +valaddr_reg:x4; val_offset:1514*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1514*FLEN/8, x7, x1, x2) + +inst_784:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x21f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x28e; op2val:0xfa1f; +valaddr_reg:x4; val_offset:1516*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1516*FLEN/8, x7, x1, x2) + +inst_785:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x21f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x78c2; op2val:0xfa1f; +valaddr_reg:x4; val_offset:1518*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1518*FLEN/8, x7, x1, x2) + +inst_786:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x28e; op2val:0xf82f; +valaddr_reg:x4; val_offset:1520*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1520*FLEN/8, x7, x1, x2) + +inst_787:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x78c2; op2val:0xf82f; +valaddr_reg:x4; val_offset:1522*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1522*FLEN/8, x7, x1, x2) + +inst_788:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x28e; op2val:0xf038; +valaddr_reg:x4; val_offset:1524*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1524*FLEN/8, x7, x1, x2) + +inst_789:// fs1 == 0 and fe1 == 0x1a and fm1 == 0x39d and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x6b9d; op2val:0xf038; +valaddr_reg:x4; val_offset:1526*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1526*FLEN/8, x7, x1, x2) + +inst_790:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e and fs2 == 0 and fe2 == 0x1a and fm2 == 0x39d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x28e; op2val:0x6b9d; +valaddr_reg:x4; val_offset:1528*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1528*FLEN/8, x7, x1, x2) + +inst_791:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x28e; op2val:0xe; +valaddr_reg:x4; val_offset:1530*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1530*FLEN/8, x7, x1, x2) + +inst_792:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x006 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x28e; op2val:0x6; +valaddr_reg:x4; val_offset:1532*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1532*FLEN/8, x7, x1, x2) + +inst_793:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x28e; op2val:0x217; +valaddr_reg:x4; val_offset:1534*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1534*FLEN/8, x7, x1, x2) + +inst_794:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x217; op2val:0x28e; +valaddr_reg:x4; val_offset:1536*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1536*FLEN/8, x7, x1, x2) + +inst_795:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x195 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x28e; op2val:0x8195; +valaddr_reg:x4; val_offset:1538*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1538*FLEN/8, x7, x1, x2) + +inst_796:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x195 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8195; op2val:0x28e; +valaddr_reg:x4; val_offset:1540*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1540*FLEN/8, x7, x1, x2) + +inst_797:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x28e; op2val:0x80a7; +valaddr_reg:x4; val_offset:1542*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1542*FLEN/8, x7, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_6) + +inst_798:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x041 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x287 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x41; op2val:0x8687; +valaddr_reg:x4; val_offset:1544*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1544*FLEN/8, x7, x1, x2) + +inst_799:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x287 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x041 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8687; op2val:0x41; +valaddr_reg:x4; val_offset:1546*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1546*FLEN/8, x7, x1, x2) + +inst_800:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x041 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x41; op2val:0x80a7; +valaddr_reg:x4; val_offset:1548*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1548*FLEN/8, x7, x1, x2) + +inst_801:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x041 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x28e; op2val:0x41; +valaddr_reg:x4; val_offset:1550*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1550*FLEN/8, x7, x1, x2) + +inst_802:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x28e; op2val:0x821e; +valaddr_reg:x4; val_offset:1552*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1552*FLEN/8, x7, x1, x2) + +inst_803:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x821e; op2val:0x28e; +valaddr_reg:x4; val_offset:1554*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1554*FLEN/8, x7, x1, x2) + +inst_804:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x28e; op2val:0x8365; +valaddr_reg:x4; val_offset:1556*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1556*FLEN/8, x7, x1, x2) + +inst_805:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8365; op2val:0x28e; +valaddr_reg:x4; val_offset:1558*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1558*FLEN/8, x7, x1, x2) + +inst_806:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x109 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x28e; op2val:0x8109; +valaddr_reg:x4; val_offset:1560*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1560*FLEN/8, x7, x1, x2) + +inst_807:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x109 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8109; op2val:0x28e; +valaddr_reg:x4; val_offset:1562*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1562*FLEN/8, x7, x1, x2) + +inst_808:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x28e; op2val:0xf0; +valaddr_reg:x4; val_offset:1564*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1564*FLEN/8, x7, x1, x2) + +inst_809:// fs1 == 0 and fe1 == 0x10 and fm1 == 0x3cc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x43cc; op2val:0xf0; +valaddr_reg:x4; val_offset:1566*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1566*FLEN/8, x7, x1, x2) + +inst_810:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3cc and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x43cc; +valaddr_reg:x4; val_offset:1568*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1568*FLEN/8, x7, x1, x2) + +inst_811:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3cc and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x28e; op2val:0x43cc; +valaddr_reg:x4; val_offset:1570*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1570*FLEN/8, x7, x1, x2) + +inst_812:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x217; op2val:0x739c; +valaddr_reg:x4; val_offset:1572*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1572*FLEN/8, x7, x1, x2) + +inst_813:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3cb and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x77cb; op2val:0x739c; +valaddr_reg:x4; val_offset:1574*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1574*FLEN/8, x7, x1, x2) + +inst_814:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3cb and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x217; op2val:0x77cb; +valaddr_reg:x4; val_offset:1576*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1576*FLEN/8, x7, x1, x2) + +inst_815:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x217; op2val:0x217; +valaddr_reg:x4; val_offset:1578*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1578*FLEN/8, x7, x1, x2) + +inst_816:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x100 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x217; op2val:0x7900; +valaddr_reg:x4; val_offset:1580*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1580*FLEN/8, x7, x1, x2) + +inst_817:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3cb and fs2 == 0 and fe2 == 0x1e and fm2 == 0x100 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x77cb; op2val:0x7900; +valaddr_reg:x4; val_offset:1582*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1582*FLEN/8, x7, x1, x2) + +inst_818:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x025 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x217; op2val:0x7425; +valaddr_reg:x4; val_offset:1584*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1584*FLEN/8, x7, x1, x2) + +inst_819:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3cb and fs2 == 0 and fe2 == 0x1d and fm2 == 0x025 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x77cb; op2val:0x7425; +valaddr_reg:x4; val_offset:1586*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1586*FLEN/8, x7, x1, x2) + +inst_820:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x217; op2val:0x7ab0; +valaddr_reg:x4; val_offset:1588*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1588*FLEN/8, x7, x1, x2) + +inst_821:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3cb and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x77cb; op2val:0x7ab0; +valaddr_reg:x4; val_offset:1590*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1590*FLEN/8, x7, x1, x2) + +inst_822:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x217; op2val:0x7913; +valaddr_reg:x4; val_offset:1592*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1592*FLEN/8, x7, x1, x2) + +inst_823:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3cb and fs2 == 0 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x77cb; op2val:0x7913; +valaddr_reg:x4; val_offset:1594*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1594*FLEN/8, x7, x1, x2) + +inst_824:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x217; op2val:0xf749; +valaddr_reg:x4; val_offset:1596*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1596*FLEN/8, x7, x1, x2) + +inst_825:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3cb and fs2 == 1 and fe2 == 0x1d and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x77cb; op2val:0xf749; +valaddr_reg:x4; val_offset:1598*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1598*FLEN/8, x7, x1, x2) + +inst_826:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x378 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x217; op2val:0xfb78; +valaddr_reg:x4; val_offset:1600*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1600*FLEN/8, x7, x1, x2) + +inst_827:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3cb and fs2 == 1 and fe2 == 0x1e and fm2 == 0x378 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x77cb; op2val:0xfb78; +valaddr_reg:x4; val_offset:1602*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1602*FLEN/8, x7, x1, x2) + +inst_828:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x21f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x217; op2val:0xfa1f; +valaddr_reg:x4; val_offset:1604*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1604*FLEN/8, x7, x1, x2) + +inst_829:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3cb and fs2 == 1 and fe2 == 0x1e and fm2 == 0x21f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x77cb; op2val:0xfa1f; +valaddr_reg:x4; val_offset:1606*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1606*FLEN/8, x7, x1, x2) + +inst_830:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x217; op2val:0xf82f; +valaddr_reg:x4; val_offset:1608*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1608*FLEN/8, x7, x1, x2) + +inst_831:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3cb and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x77cb; op2val:0xf82f; +valaddr_reg:x4; val_offset:1610*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1610*FLEN/8, x7, x1, x2) + +inst_832:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x217; op2val:0xf038; +valaddr_reg:x4; val_offset:1612*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1612*FLEN/8, x7, x1, x2) + +inst_833:// fs1 == 0 and fe1 == 0x1a and fm1 == 0x23c and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x6a3c; op2val:0xf038; +valaddr_reg:x4; val_offset:1614*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1614*FLEN/8, x7, x1, x2) + +inst_834:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x23c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x217; op2val:0x6a3c; +valaddr_reg:x4; val_offset:1616*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1616*FLEN/8, x7, x1, x2) + +inst_835:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x217; op2val:0xe; +valaddr_reg:x4; val_offset:1618*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1618*FLEN/8, x7, x1, x2) + +inst_836:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x005 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x5; op2val:0xe; +valaddr_reg:x4; val_offset:1620*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1620*FLEN/8, x7, x1, x2) + +inst_837:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x005 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x217; op2val:0x5; +valaddr_reg:x4; val_offset:1622*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1622*FLEN/8, x7, x1, x2) + +inst_838:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x195 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x217; op2val:0x8195; +valaddr_reg:x4; val_offset:1624*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1624*FLEN/8, x7, x1, x2) + +inst_839:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x195 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8195; op2val:0x217; +valaddr_reg:x4; val_offset:1626*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1626*FLEN/8, x7, x1, x2) + +inst_840:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x217; op2val:0x80a7; +valaddr_reg:x4; val_offset:1628*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1628*FLEN/8, x7, x1, x2) + +inst_841:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x035 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x287 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x35; op2val:0x8687; +valaddr_reg:x4; val_offset:1630*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1630*FLEN/8, x7, x1, x2) + +inst_842:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x287 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x035 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8687; op2val:0x35; +valaddr_reg:x4; val_offset:1632*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1632*FLEN/8, x7, x1, x2) + +inst_843:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x035 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x35; op2val:0x80a7; +valaddr_reg:x4; val_offset:1634*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1634*FLEN/8, x7, x1, x2) + +inst_844:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x035 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x217; op2val:0x35; +valaddr_reg:x4; val_offset:1636*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1636*FLEN/8, x7, x1, x2) + +inst_845:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x217; op2val:0x821e; +valaddr_reg:x4; val_offset:1638*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1638*FLEN/8, x7, x1, x2) + +inst_846:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x821e; op2val:0x217; +valaddr_reg:x4; val_offset:1640*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1640*FLEN/8, x7, x1, x2) + +inst_847:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x217; op2val:0x8365; +valaddr_reg:x4; val_offset:1642*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1642*FLEN/8, x7, x1, x2) + +inst_848:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8365; op2val:0x217; +valaddr_reg:x4; val_offset:1644*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1644*FLEN/8, x7, x1, x2) + +inst_849:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x109 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x217; op2val:0x8109; +valaddr_reg:x4; val_offset:1646*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1646*FLEN/8, x7, x1, x2) + +inst_850:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x109 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8109; op2val:0x217; +valaddr_reg:x4; val_offset:1648*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1648*FLEN/8, x7, x1, x2) + +inst_851:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x217; op2val:0xf0; +valaddr_reg:x4; val_offset:1650*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1650*FLEN/8, x7, x1, x2) + +inst_852:// fs1 == 0 and fe1 == 0x10 and fm1 == 0x262 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x4262; op2val:0xf0; +valaddr_reg:x4; val_offset:1652*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1652*FLEN/8, x7, x1, x2) + +inst_853:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x262 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x4262; +valaddr_reg:x4; val_offset:1654*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1654*FLEN/8, x7, x1, x2) + +inst_854:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x262 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x217; op2val:0x4262; +valaddr_reg:x4; val_offset:1656*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1656*FLEN/8, x7, x1, x2) + +inst_855:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x195 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8195; op2val:0x739c; +valaddr_reg:x4; val_offset:1658*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1658*FLEN/8, x7, x1, x2) + +inst_856:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x1e7 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf5e7; op2val:0x739c; +valaddr_reg:x4; val_offset:1660*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1660*FLEN/8, x7, x1, x2) + +inst_857:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x195 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x1e7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8195; op2val:0xf5e7; +valaddr_reg:x4; val_offset:1662*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1662*FLEN/8, x7, x1, x2) + +inst_858:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x195 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x195 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8195; op2val:0x8195; +valaddr_reg:x4; val_offset:1664*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1664*FLEN/8, x7, x1, x2) + +inst_859:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x195 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x100 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8195; op2val:0x7900; +valaddr_reg:x4; val_offset:1666*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1666*FLEN/8, x7, x1, x2) + +inst_860:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x1e7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x100 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf5e7; op2val:0x7900; +valaddr_reg:x4; val_offset:1668*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1668*FLEN/8, x7, x1, x2) + +inst_861:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x195 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x025 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8195; op2val:0x7425; +valaddr_reg:x4; val_offset:1670*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1670*FLEN/8, x7, x1, x2) + +inst_862:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x1e7 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x025 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf5e7; op2val:0x7425; +valaddr_reg:x4; val_offset:1672*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1672*FLEN/8, x7, x1, x2) + +inst_863:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x195 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8195; op2val:0x7ab0; +valaddr_reg:x4; val_offset:1674*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1674*FLEN/8, x7, x1, x2) + +inst_864:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x1e7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf5e7; op2val:0x7ab0; +valaddr_reg:x4; val_offset:1676*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1676*FLEN/8, x7, x1, x2) + +inst_865:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x195 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8195; op2val:0x7913; +valaddr_reg:x4; val_offset:1678*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1678*FLEN/8, x7, x1, x2) + +inst_866:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x1e7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf5e7; op2val:0x7913; +valaddr_reg:x4; val_offset:1680*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1680*FLEN/8, x7, x1, x2) + +inst_867:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x195 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8195; op2val:0xf749; +valaddr_reg:x4; val_offset:1682*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1682*FLEN/8, x7, x1, x2) + +inst_868:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x1e7 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf5e7; op2val:0xf749; +valaddr_reg:x4; val_offset:1684*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1684*FLEN/8, x7, x1, x2) + +inst_869:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x195 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x378 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8195; op2val:0xfb78; +valaddr_reg:x4; val_offset:1686*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1686*FLEN/8, x7, x1, x2) + +inst_870:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x1e7 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x378 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf5e7; op2val:0xfb78; +valaddr_reg:x4; val_offset:1688*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1688*FLEN/8, x7, x1, x2) + +inst_871:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x195 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x21f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8195; op2val:0xfa1f; +valaddr_reg:x4; val_offset:1690*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1690*FLEN/8, x7, x1, x2) + +inst_872:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x1e7 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x21f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf5e7; op2val:0xfa1f; +valaddr_reg:x4; val_offset:1692*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1692*FLEN/8, x7, x1, x2) + +inst_873:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x195 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8195; op2val:0xf82f; +valaddr_reg:x4; val_offset:1694*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1694*FLEN/8, x7, x1, x2) + +inst_874:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x1e7 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf5e7; op2val:0xf82f; +valaddr_reg:x4; val_offset:1696*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1696*FLEN/8, x7, x1, x2) + +inst_875:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x195 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8195; op2val:0xf038; +valaddr_reg:x4; val_offset:1698*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1698*FLEN/8, x7, x1, x2) + +inst_876:// fs1 == 1 and fe1 == 0x1a and fm1 == 0x0b9 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xe8b9; op2val:0xf038; +valaddr_reg:x4; val_offset:1700*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1700*FLEN/8, x7, x1, x2) + +inst_877:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x195 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x0b9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8195; op2val:0xe8b9; +valaddr_reg:x4; val_offset:1702*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1702*FLEN/8, x7, x1, x2) + +inst_878:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x195 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8195; op2val:0xe; +valaddr_reg:x4; val_offset:1704*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1704*FLEN/8, x7, x1, x2) + +inst_879:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x004 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8004; op2val:0xe; +valaddr_reg:x4; val_offset:1706*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1706*FLEN/8, x7, x1, x2) + +inst_880:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x195 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x004 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8195; op2val:0x8004; +valaddr_reg:x4; val_offset:1708*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1708*FLEN/8, x7, x1, x2) + +inst_881:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x195 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8195; op2val:0x80a7; +valaddr_reg:x4; val_offset:1710*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1710*FLEN/8, x7, x1, x2) + +inst_882:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x028 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x287 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8028; op2val:0x8687; +valaddr_reg:x4; val_offset:1712*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1712*FLEN/8, x7, x1, x2) + +inst_883:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x287 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x028 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8687; op2val:0x8028; +valaddr_reg:x4; val_offset:1714*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1714*FLEN/8, x7, x1, x2) + +inst_884:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x028 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8028; op2val:0x80a7; +valaddr_reg:x4; val_offset:1716*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1716*FLEN/8, x7, x1, x2) + +inst_885:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x195 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x028 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8195; op2val:0x8028; +valaddr_reg:x4; val_offset:1718*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1718*FLEN/8, x7, x1, x2) + +inst_886:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x195 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8195; op2val:0x821e; +valaddr_reg:x4; val_offset:1720*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1720*FLEN/8, x7, x1, x2) + +inst_887:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x195 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x821e; op2val:0x8195; +valaddr_reg:x4; val_offset:1722*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1722*FLEN/8, x7, x1, x2) + +inst_888:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x195 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8195; op2val:0x8365; +valaddr_reg:x4; val_offset:1724*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1724*FLEN/8, x7, x1, x2) + +inst_889:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x195 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8365; op2val:0x8195; +valaddr_reg:x4; val_offset:1726*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1726*FLEN/8, x7, x1, x2) + +inst_890:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x195 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x109 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8195; op2val:0x8109; +valaddr_reg:x4; val_offset:1728*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1728*FLEN/8, x7, x1, x2) + +inst_891:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x109 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x195 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8109; op2val:0x8195; +valaddr_reg:x4; val_offset:1730*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1730*FLEN/8, x7, x1, x2) + +inst_892:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x195 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8195; op2val:0xf0; +valaddr_reg:x4; val_offset:1732*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1732*FLEN/8, x7, x1, x2) + +inst_893:// fs1 == 1 and fe1 == 0x10 and fm1 == 0x0d6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xc0d6; op2val:0xf0; +valaddr_reg:x4; val_offset:1734*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1734*FLEN/8, x7, x1, x2) + +inst_894:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0d6 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xc0d6; +valaddr_reg:x4; val_offset:1736*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1736*FLEN/8, x7, x1, x2) + +inst_895:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x195 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0d6 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8195; op2val:0xc0d6; +valaddr_reg:x4; val_offset:1738*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1738*FLEN/8, x7, x1, x2) + +inst_896:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a7 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x80a7; op2val:0x739c; +valaddr_reg:x4; val_offset:1740*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1740*FLEN/8, x7, x1, x2) + +inst_897:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a7 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x80a7; op2val:0xfbff; +valaddr_reg:x4; val_offset:1742*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1742*FLEN/8, x7, x1, x2) + +inst_898:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x80a7; op2val:0x80a7; +valaddr_reg:x4; val_offset:1744*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1744*FLEN/8, x7, x1, x2) + +inst_899:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x100 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x80a7; op2val:0x7900; +valaddr_reg:x4; val_offset:1746*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1746*FLEN/8, x7, x1, x2) + +inst_900:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a7 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x025 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x80a7; op2val:0x7425; +valaddr_reg:x4; val_offset:1748*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1748*FLEN/8, x7, x1, x2) + +inst_901:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x80a7; op2val:0x7ab0; +valaddr_reg:x4; val_offset:1750*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1750*FLEN/8, x7, x1, x2) + +inst_902:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x80a7; op2val:0x7913; +valaddr_reg:x4; val_offset:1752*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1752*FLEN/8, x7, x1, x2) + +inst_903:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a7 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x80a7; op2val:0xf749; +valaddr_reg:x4; val_offset:1754*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1754*FLEN/8, x7, x1, x2) + +inst_904:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a7 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x378 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x80a7; op2val:0xfb78; +valaddr_reg:x4; val_offset:1756*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1756*FLEN/8, x7, x1, x2) + +inst_905:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a7 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x21f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x80a7; op2val:0xfa1f; +valaddr_reg:x4; val_offset:1758*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1758*FLEN/8, x7, x1, x2) + +inst_906:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a7 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x80a7; op2val:0xf82f; +valaddr_reg:x4; val_offset:1760*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1760*FLEN/8, x7, x1, x2) + +inst_907:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a7 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x80a7; op2val:0xf038; +valaddr_reg:x4; val_offset:1762*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1762*FLEN/8, x7, x1, x2) + +inst_908:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x0dd and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0dd; op2val:0xf038; +valaddr_reg:x4; val_offset:1764*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1764*FLEN/8, x7, x1, x2) + +inst_909:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a7 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0dd and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x80a7; op2val:0xf0dd; +valaddr_reg:x4; val_offset:1766*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1766*FLEN/8, x7, x1, x2) + +inst_910:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17b and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x80a7; op2val:0x17b; +valaddr_reg:x4; val_offset:1768*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1768*FLEN/8, x7, x1, x2) + +inst_911:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x287 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17b and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8687; op2val:0x17b; +valaddr_reg:x4; val_offset:1770*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1770*FLEN/8, x7, x1, x2) + +inst_912:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a7 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x287 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x80a7; op2val:0x8687; +valaddr_reg:x4; val_offset:1772*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1772*FLEN/8, x7, x1, x2) + +inst_913:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x80a7; op2val:0xe; +valaddr_reg:x4; val_offset:1774*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1774*FLEN/8, x7, x1, x2) + +inst_914:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x010 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8010; op2val:0xe; +valaddr_reg:x4; val_offset:1776*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1776*FLEN/8, x7, x1, x2) + +inst_915:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x010 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x80a7; op2val:0x8010; +valaddr_reg:x4; val_offset:1778*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1778*FLEN/8, x7, x1, x2) + +inst_916:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x80a7; op2val:0x3fa; +valaddr_reg:x4; val_offset:1780*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1780*FLEN/8, x7, x1, x2) + +inst_917:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x287 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8687; op2val:0x3fa; +valaddr_reg:x4; val_offset:1782*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1782*FLEN/8, x7, x1, x2) + +inst_918:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x80a7; op2val:0x28e; +valaddr_reg:x4; val_offset:1784*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1784*FLEN/8, x7, x1, x2) + +inst_919:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x287 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8687; op2val:0x28e; +valaddr_reg:x4; val_offset:1786*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1786*FLEN/8, x7, x1, x2) + +inst_920:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x80a7; op2val:0x217; +valaddr_reg:x4; val_offset:1788*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1788*FLEN/8, x7, x1, x2) + +inst_921:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x287 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8687; op2val:0x217; +valaddr_reg:x4; val_offset:1790*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1790*FLEN/8, x7, x1, x2) + +inst_922:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x195 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x80a7; op2val:0x8195; +valaddr_reg:x4; val_offset:1792*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1792*FLEN/8, x7, x1, x2) + +inst_923:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x287 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x195 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8687; op2val:0x8195; +valaddr_reg:x4; val_offset:1794*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1794*FLEN/8, x7, x1, x2) + +inst_924:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x80a7; op2val:0x821e; +valaddr_reg:x4; val_offset:1796*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1796*FLEN/8, x7, x1, x2) + +inst_925:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x287 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x036 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8687; op2val:0x8036; +valaddr_reg:x4; val_offset:1798*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1798*FLEN/8, x7, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_7) + +inst_926:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x036 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x287 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8036; op2val:0x8687; +valaddr_reg:x4; val_offset:1800*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1800*FLEN/8, x7, x1, x2) + +inst_927:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x287 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8687; op2val:0x821e; +valaddr_reg:x4; val_offset:1802*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1802*FLEN/8, x7, x1, x2) + +inst_928:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x80a7; op2val:0x8365; +valaddr_reg:x4; val_offset:1804*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1804*FLEN/8, x7, x1, x2) + +inst_929:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x287 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x056 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8687; op2val:0x8056; +valaddr_reg:x4; val_offset:1806*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1806*FLEN/8, x7, x1, x2) + +inst_930:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x056 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x287 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8056; op2val:0x8687; +valaddr_reg:x4; val_offset:1808*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1808*FLEN/8, x7, x1, x2) + +inst_931:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x287 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8687; op2val:0x8365; +valaddr_reg:x4; val_offset:1810*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1810*FLEN/8, x7, x1, x2) + +inst_932:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x109 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x80a7; op2val:0x8109; +valaddr_reg:x4; val_offset:1812*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1812*FLEN/8, x7, x1, x2) + +inst_933:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x287 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x01a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8687; op2val:0x801a; +valaddr_reg:x4; val_offset:1814*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1814*FLEN/8, x7, x1, x2) + +inst_934:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x01a and fs2 == 1 and fe2 == 0x01 and fm2 == 0x287 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x801a; op2val:0x8687; +valaddr_reg:x4; val_offset:1816*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1816*FLEN/8, x7, x1, x2) + +inst_935:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x287 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x109 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8687; op2val:0x8109; +valaddr_reg:x4; val_offset:1818*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1818*FLEN/8, x7, x1, x2) + +inst_936:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x80a7; op2val:0xf0; +valaddr_reg:x4; val_offset:1820*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1820*FLEN/8, x7, x1, x2) + +inst_937:// fs1 == 1 and fe1 == 0x12 and fm1 == 0x0fa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xc8fa; op2val:0xf0; +valaddr_reg:x4; val_offset:1822*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1822*FLEN/8, x7, x1, x2) + +inst_938:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xc8fa; +valaddr_reg:x4; val_offset:1824*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1824*FLEN/8, x7, x1, x2) + +inst_939:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a7 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x80a7; op2val:0xc8fa; +valaddr_reg:x4; val_offset:1826*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1826*FLEN/8, x7, x1, x2) + +inst_940:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x821e; op2val:0x739c; +valaddr_reg:x4; val_offset:1828*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1828*FLEN/8, x7, x1, x2) + +inst_941:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x3e4 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf7e4; op2val:0x739c; +valaddr_reg:x4; val_offset:1830*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1830*FLEN/8, x7, x1, x2) + +inst_942:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3e4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x821e; op2val:0xf7e4; +valaddr_reg:x4; val_offset:1832*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1832*FLEN/8, x7, x1, x2) + +inst_943:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x821e; op2val:0x821e; +valaddr_reg:x4; val_offset:1834*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1834*FLEN/8, x7, x1, x2) + +inst_944:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x100 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x821e; op2val:0x7900; +valaddr_reg:x4; val_offset:1836*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1836*FLEN/8, x7, x1, x2) + +inst_945:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x3e4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x100 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf7e4; op2val:0x7900; +valaddr_reg:x4; val_offset:1838*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1838*FLEN/8, x7, x1, x2) + +inst_946:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x025 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x821e; op2val:0x7425; +valaddr_reg:x4; val_offset:1840*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1840*FLEN/8, x7, x1, x2) + +inst_947:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x3e4 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x025 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf7e4; op2val:0x7425; +valaddr_reg:x4; val_offset:1842*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1842*FLEN/8, x7, x1, x2) + +inst_948:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x821e; op2val:0x7ab0; +valaddr_reg:x4; val_offset:1844*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1844*FLEN/8, x7, x1, x2) + +inst_949:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x3e4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf7e4; op2val:0x7ab0; +valaddr_reg:x4; val_offset:1846*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1846*FLEN/8, x7, x1, x2) + +inst_950:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x821e; op2val:0x7913; +valaddr_reg:x4; val_offset:1848*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1848*FLEN/8, x7, x1, x2) + +inst_951:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x3e4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf7e4; op2val:0x7913; +valaddr_reg:x4; val_offset:1850*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1850*FLEN/8, x7, x1, x2) + +inst_952:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e and fs2 == 1 and fe2 == 0x1d and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x821e; op2val:0xf749; +valaddr_reg:x4; val_offset:1852*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1852*FLEN/8, x7, x1, x2) + +inst_953:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x3e4 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf7e4; op2val:0xf749; +valaddr_reg:x4; val_offset:1854*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1854*FLEN/8, x7, x1, x2) + +inst_954:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x378 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x821e; op2val:0xfb78; +valaddr_reg:x4; val_offset:1856*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1856*FLEN/8, x7, x1, x2) + +inst_955:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x3e4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x378 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf7e4; op2val:0xfb78; +valaddr_reg:x4; val_offset:1858*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1858*FLEN/8, x7, x1, x2) + +inst_956:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x21f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x821e; op2val:0xfa1f; +valaddr_reg:x4; val_offset:1860*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1860*FLEN/8, x7, x1, x2) + +inst_957:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x3e4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x21f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf7e4; op2val:0xfa1f; +valaddr_reg:x4; val_offset:1862*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1862*FLEN/8, x7, x1, x2) + +inst_958:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x821e; op2val:0xf82f; +valaddr_reg:x4; val_offset:1864*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1864*FLEN/8, x7, x1, x2) + +inst_959:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x3e4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf7e4; op2val:0xf82f; +valaddr_reg:x4; val_offset:1866*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1866*FLEN/8, x7, x1, x2) + +inst_960:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x821e; op2val:0xf038; +valaddr_reg:x4; val_offset:1868*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1868*FLEN/8, x7, x1, x2) + +inst_961:// fs1 == 1 and fe1 == 0x1a and fm1 == 0x250 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xea50; op2val:0xf038; +valaddr_reg:x4; val_offset:1870*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1870*FLEN/8, x7, x1, x2) + +inst_962:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e and fs2 == 1 and fe2 == 0x1a and fm2 == 0x250 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x821e; op2val:0xea50; +valaddr_reg:x4; val_offset:1872*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1872*FLEN/8, x7, x1, x2) + +inst_963:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x821e; op2val:0xe; +valaddr_reg:x4; val_offset:1874*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1874*FLEN/8, x7, x1, x2) + +inst_964:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x005 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x821e; op2val:0x8005; +valaddr_reg:x4; val_offset:1876*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1876*FLEN/8, x7, x1, x2) + +inst_965:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x821e; op2val:0x80a7; +valaddr_reg:x4; val_offset:1878*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1878*FLEN/8, x7, x1, x2) + +inst_966:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x036 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8036; op2val:0x80a7; +valaddr_reg:x4; val_offset:1880*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1880*FLEN/8, x7, x1, x2) + +inst_967:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x036 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x821e; op2val:0x8036; +valaddr_reg:x4; val_offset:1882*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1882*FLEN/8, x7, x1, x2) + +inst_968:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x821e; op2val:0x8365; +valaddr_reg:x4; val_offset:1884*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1884*FLEN/8, x7, x1, x2) + +inst_969:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8365; op2val:0x821e; +valaddr_reg:x4; val_offset:1886*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1886*FLEN/8, x7, x1, x2) + +inst_970:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x109 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x821e; op2val:0x8109; +valaddr_reg:x4; val_offset:1888*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1888*FLEN/8, x7, x1, x2) + +inst_971:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x109 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8109; op2val:0x821e; +valaddr_reg:x4; val_offset:1890*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1890*FLEN/8, x7, x1, x2) + +inst_972:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x821e; op2val:0xf0; +valaddr_reg:x4; val_offset:1892*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1892*FLEN/8, x7, x1, x2) + +inst_973:// fs1 == 1 and fe1 == 0x10 and fm1 == 0x277 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xc277; op2val:0xf0; +valaddr_reg:x4; val_offset:1894*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1894*FLEN/8, x7, x1, x2) + +inst_974:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x277 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xc277; +valaddr_reg:x4; val_offset:1896*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1896*FLEN/8, x7, x1, x2) + +inst_975:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e and fs2 == 1 and fe2 == 0x10 and fm2 == 0x277 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x821e; op2val:0xc277; +valaddr_reg:x4; val_offset:1898*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1898*FLEN/8, x7, x1, x2) + +inst_976:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8365; op2val:0x739c; +valaddr_reg:x4; val_offset:1900*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1900*FLEN/8, x7, x1, x2) + +inst_977:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x252 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa52; op2val:0x739c; +valaddr_reg:x4; val_offset:1902*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1902*FLEN/8, x7, x1, x2) + +inst_978:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x252 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8365; op2val:0xfa52; +valaddr_reg:x4; val_offset:1904*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1904*FLEN/8, x7, x1, x2) + +inst_979:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8365; op2val:0x8365; +valaddr_reg:x4; val_offset:1906*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1906*FLEN/8, x7, x1, x2) + +inst_980:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x100 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8365; op2val:0x7900; +valaddr_reg:x4; val_offset:1908*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1908*FLEN/8, x7, x1, x2) + +inst_981:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x252 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x100 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa52; op2val:0x7900; +valaddr_reg:x4; val_offset:1910*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1910*FLEN/8, x7, x1, x2) + +inst_982:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x025 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8365; op2val:0x7425; +valaddr_reg:x4; val_offset:1912*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1912*FLEN/8, x7, x1, x2) + +inst_983:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x252 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x025 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa52; op2val:0x7425; +valaddr_reg:x4; val_offset:1914*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1914*FLEN/8, x7, x1, x2) + +inst_984:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8365; op2val:0x7ab0; +valaddr_reg:x4; val_offset:1916*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1916*FLEN/8, x7, x1, x2) + +inst_985:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x252 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa52; op2val:0x7ab0; +valaddr_reg:x4; val_offset:1918*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1918*FLEN/8, x7, x1, x2) + +inst_986:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8365; op2val:0x7913; +valaddr_reg:x4; val_offset:1920*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1920*FLEN/8, x7, x1, x2) + +inst_987:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x252 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa52; op2val:0x7913; +valaddr_reg:x4; val_offset:1922*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1922*FLEN/8, x7, x1, x2) + +inst_988:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8365; op2val:0xf749; +valaddr_reg:x4; val_offset:1924*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1924*FLEN/8, x7, x1, x2) + +inst_989:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x252 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa52; op2val:0xf749; +valaddr_reg:x4; val_offset:1926*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1926*FLEN/8, x7, x1, x2) + +inst_990:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x378 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8365; op2val:0xfb78; +valaddr_reg:x4; val_offset:1928*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1928*FLEN/8, x7, x1, x2) + +inst_991:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x252 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x378 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa52; op2val:0xfb78; +valaddr_reg:x4; val_offset:1930*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1930*FLEN/8, x7, x1, x2) + +inst_992:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x21f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8365; op2val:0xfa1f; +valaddr_reg:x4; val_offset:1932*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1932*FLEN/8, x7, x1, x2) + +inst_993:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x252 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x21f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa52; op2val:0xfa1f; +valaddr_reg:x4; val_offset:1934*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1934*FLEN/8, x7, x1, x2) + +inst_994:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8365; op2val:0xf82f; +valaddr_reg:x4; val_offset:1936*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1936*FLEN/8, x7, x1, x2) + +inst_995:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x252 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa52; op2val:0xf82f; +valaddr_reg:x4; val_offset:1938*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1938*FLEN/8, x7, x1, x2) + +inst_996:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8365; op2val:0xf038; +valaddr_reg:x4; val_offset:1940*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1940*FLEN/8, x7, x1, x2) + +inst_997:// fs1 == 1 and fe1 == 0x1b and fm1 == 0x10f and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xed0f; op2val:0xf038; +valaddr_reg:x4; val_offset:1942*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1942*FLEN/8, x7, x1, x2) + +inst_998:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x10f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8365; op2val:0xed0f; +valaddr_reg:x4; val_offset:1944*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1944*FLEN/8, x7, x1, x2) + +inst_999:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8365; op2val:0xe; +valaddr_reg:x4; val_offset:1946*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1946*FLEN/8, x7, x1, x2) + +inst_1000:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x008 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8365; op2val:0x8008; +valaddr_reg:x4; val_offset:1948*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1948*FLEN/8, x7, x1, x2) + +inst_1001:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8365; op2val:0x80a7; +valaddr_reg:x4; val_offset:1950*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1950*FLEN/8, x7, x1, x2) + +inst_1002:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x056 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8056; op2val:0x80a7; +valaddr_reg:x4; val_offset:1952*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1952*FLEN/8, x7, x1, x2) + +inst_1003:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x056 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8365; op2val:0x8056; +valaddr_reg:x4; val_offset:1954*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1954*FLEN/8, x7, x1, x2) + +inst_1004:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x109 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8365; op2val:0x8109; +valaddr_reg:x4; val_offset:1956*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1956*FLEN/8, x7, x1, x2) + +inst_1005:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x109 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8109; op2val:0x8365; +valaddr_reg:x4; val_offset:1958*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1958*FLEN/8, x7, x1, x2) + +inst_1006:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8365; op2val:0xf0; +valaddr_reg:x4; val_offset:1960*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1960*FLEN/8, x7, x1, x2) + +inst_1007:// fs1 == 1 and fe1 == 0x11 and fm1 == 0x12e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xc52e; op2val:0xf0; +valaddr_reg:x4; val_offset:1962*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1962*FLEN/8, x7, x1, x2) + +inst_1008:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x12e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xc52e; +valaddr_reg:x4; val_offset:1964*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1964*FLEN/8, x7, x1, x2) + +inst_1009:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x12e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8365; op2val:0xc52e; +valaddr_reg:x4; val_offset:1966*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1966*FLEN/8, x7, x1, x2) + +inst_1010:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x109 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8109; op2val:0x739c; +valaddr_reg:x4; val_offset:1968*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1968*FLEN/8, x7, x1, x2) + +inst_1011:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3b9 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3b9; op2val:0x739c; +valaddr_reg:x4; val_offset:1970*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1970*FLEN/8, x7, x1, x2) + +inst_1012:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x109 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3b9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8109; op2val:0xf3b9; +valaddr_reg:x4; val_offset:1972*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1972*FLEN/8, x7, x1, x2) + +inst_1013:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x109 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x109 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8109; op2val:0x8109; +valaddr_reg:x4; val_offset:1974*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1974*FLEN/8, x7, x1, x2) + +inst_1014:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x109 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x100 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8109; op2val:0x7900; +valaddr_reg:x4; val_offset:1976*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1976*FLEN/8, x7, x1, x2) + +inst_1015:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3b9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x100 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3b9; op2val:0x7900; +valaddr_reg:x4; val_offset:1978*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1978*FLEN/8, x7, x1, x2) + +inst_1016:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x109 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x025 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8109; op2val:0x7425; +valaddr_reg:x4; val_offset:1980*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1980*FLEN/8, x7, x1, x2) + +inst_1017:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3b9 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x025 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3b9; op2val:0x7425; +valaddr_reg:x4; val_offset:1982*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1982*FLEN/8, x7, x1, x2) + +inst_1018:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x109 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8109; op2val:0x7ab0; +valaddr_reg:x4; val_offset:1984*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1984*FLEN/8, x7, x1, x2) + +inst_1019:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3b9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3b9; op2val:0x7ab0; +valaddr_reg:x4; val_offset:1986*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1986*FLEN/8, x7, x1, x2) + +inst_1020:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x109 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8109; op2val:0x7913; +valaddr_reg:x4; val_offset:1988*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1988*FLEN/8, x7, x1, x2) + +inst_1021:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3b9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3b9; op2val:0x7913; +valaddr_reg:x4; val_offset:1990*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1990*FLEN/8, x7, x1, x2) + +inst_1022:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x109 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8109; op2val:0xf749; +valaddr_reg:x4; val_offset:1992*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1992*FLEN/8, x7, x1, x2) + +inst_1023:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3b9 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3b9; op2val:0xf749; +valaddr_reg:x4; val_offset:1994*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1994*FLEN/8, x7, x1, x2) + +inst_1024:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x109 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x378 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8109; op2val:0xfb78; +valaddr_reg:x4; val_offset:1996*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1996*FLEN/8, x7, x1, x2) + +inst_1025:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3b9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x378 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3b9; op2val:0xfb78; +valaddr_reg:x4; val_offset:1998*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 1998*FLEN/8, x7, x1, x2) + +inst_1026:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x109 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x21f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8109; op2val:0xfa1f; +valaddr_reg:x4; val_offset:2000*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 2000*FLEN/8, x7, x1, x2) + +inst_1027:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3b9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x21f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3b9; op2val:0xfa1f; +valaddr_reg:x4; val_offset:2002*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 2002*FLEN/8, x7, x1, x2) + +inst_1028:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x109 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8109; op2val:0xf82f; +valaddr_reg:x4; val_offset:2004*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 2004*FLEN/8, x7, x1, x2) + +inst_1029:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3b9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3b9; op2val:0xf82f; +valaddr_reg:x4; val_offset:2006*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 2006*FLEN/8, x7, x1, x2) + +inst_1030:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x109 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8109; op2val:0xf038; +valaddr_reg:x4; val_offset:2008*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 2008*FLEN/8, x7, x1, x2) + +inst_1031:// fs1 == 1 and fe1 == 0x19 and fm1 == 0x22e and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xe62e; op2val:0xf038; +valaddr_reg:x4; val_offset:2010*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 2010*FLEN/8, x7, x1, x2) + +inst_1032:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x109 and fs2 == 1 and fe2 == 0x19 and fm2 == 0x22e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8109; op2val:0xe62e; +valaddr_reg:x4; val_offset:2012*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 2012*FLEN/8, x7, x1, x2) + +inst_1033:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x109 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8109; op2val:0xe; +valaddr_reg:x4; val_offset:2014*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 2014*FLEN/8, x7, x1, x2) + +inst_1034:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8002; op2val:0xe; +valaddr_reg:x4; val_offset:2016*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 2016*FLEN/8, x7, x1, x2) + +inst_1035:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x109 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8109; op2val:0x8002; +valaddr_reg:x4; val_offset:2018*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 2018*FLEN/8, x7, x1, x2) + +inst_1036:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x109 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8109; op2val:0x80a7; +valaddr_reg:x4; val_offset:2020*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 2020*FLEN/8, x7, x1, x2) + +inst_1037:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x01a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x801a; op2val:0x80a7; +valaddr_reg:x4; val_offset:2022*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 2022*FLEN/8, x7, x1, x2) + +inst_1038:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x109 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x01a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8109; op2val:0x801a; +valaddr_reg:x4; val_offset:2024*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 2024*FLEN/8, x7, x1, x2) + +inst_1039:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x109 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8109; op2val:0xf0; +valaddr_reg:x4; val_offset:2026*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 2026*FLEN/8, x7, x1, x2) + +inst_1040:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x254 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xbe54; op2val:0xf0; +valaddr_reg:x4; val_offset:2028*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 2028*FLEN/8, x7, x1, x2) + +inst_1041:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x254 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xbe54; +valaddr_reg:x4; val_offset:2030*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 2030*FLEN/8, x7, x1, x2) + +inst_1042:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x109 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x254 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x8109; op2val:0xbe54; +valaddr_reg:x4; val_offset:2032*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 2032*FLEN/8, x7, x1, x2) + +inst_1043:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x739c; +valaddr_reg:x4; val_offset:2034*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 2034*FLEN/8, x7, x1, x2) + +inst_1044:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xf0; +valaddr_reg:x4; val_offset:2036*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 2036*FLEN/8, x7, x1, x2) + +inst_1045:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x100 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x7900; +valaddr_reg:x4; val_offset:2038*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 2038*FLEN/8, x7, x1, x2) + +inst_1046:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x025 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x7425; +valaddr_reg:x4; val_offset:2040*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 2040*FLEN/8, x7, x1, x2) + +inst_1047:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x7ab0; +valaddr_reg:x4; val_offset:2042*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 2042*FLEN/8, x7, x1, x2) + +inst_1048:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x7913; +valaddr_reg:x4; val_offset:2044*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 2044*FLEN/8, x7, x1, x2) + +inst_1049:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xf749; +valaddr_reg:x4; val_offset:2046*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 2046*FLEN/8, x7, x1, x2) + +inst_1050:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x378 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xfb78; +valaddr_reg:x4; val_offset:2048*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 2048*FLEN/8, x7, x1, x2) + +inst_1051:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x21f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xfa1f; +valaddr_reg:x4; val_offset:2050*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 2050*FLEN/8, x7, x1, x2) + +inst_1052:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xf82f; +valaddr_reg:x4; val_offset:2052*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 2052*FLEN/8, x7, x1, x2) + +inst_1053:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xf038; +valaddr_reg:x4; val_offset:2054*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 2054*FLEN/8, x7, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_8) + +inst_1054:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x17b; +valaddr_reg:x4; val_offset:2056*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 2056*FLEN/8, x7, x1, x2) + +inst_1055:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xe; +valaddr_reg:x4; val_offset:2058*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 2058*FLEN/8, x7, x1, x2) + +inst_1056:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x3fa; +valaddr_reg:x4; val_offset:2060*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 2060*FLEN/8, x7, x1, x2) + +inst_1057:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x28e; +valaddr_reg:x4; val_offset:2062*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 2062*FLEN/8, x7, x1, x2) + +inst_1058:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x217; +valaddr_reg:x4; val_offset:2064*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 2064*FLEN/8, x7, x1, x2) + +inst_1059:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x195 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x8195; +valaddr_reg:x4; val_offset:2066*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 2066*FLEN/8, x7, x1, x2) + +inst_1060:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x80a7; +valaddr_reg:x4; val_offset:2068*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 2068*FLEN/8, x7, x1, x2) + +inst_1061:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x821e; +valaddr_reg:x4; val_offset:2070*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 2070*FLEN/8, x7, x1, x2) + +inst_1062:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x8365; +valaddr_reg:x4; val_offset:2072*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 2072*FLEN/8, x7, x1, x2) + +inst_1063:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x109 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x8109; +valaddr_reg:x4; val_offset:2074*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 2074*FLEN/8, x7, x1, x2) + +inst_1064:// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x739c; op2val:0x739c; +valaddr_reg:x4; val_offset:2076*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 2076*FLEN/8, x7, x1, x2) + +inst_1065:// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 1 and fe2 == 0x1d and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x739c; op2val:0xf749; +valaddr_reg:x4; val_offset:2078*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 2078*FLEN/8, x7, x1, x2) + +inst_1066:// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x105 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x739c; op2val:0x105; +valaddr_reg:x4; val_offset:2080*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 2080*FLEN/8, x7, x1, x2) + +inst_1067:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: feq.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x2; +valaddr_reg:x4; val_offset:2082*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(feq.h, x31, x30, x29, 0, 0, x4, 2082*FLEN/8, x7, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(30976,32,FLEN) +NAN_BOXED(30976,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(29733,32,FLEN) +NAN_BOXED(29733,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(31408,32,FLEN) +NAN_BOXED(31408,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(30995,32,FLEN) +NAN_BOXED(30995,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(63305,16,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(64376,16,FLEN) +NAN_BOXED(64376,16,FLEN) +NAN_BOXED(29596,32,FLEN) +test_dataset_1: +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(64031,16,FLEN) +NAN_BOXED(64031,16,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(63535,16,FLEN) +NAN_BOXED(63535,16,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(61496,16,FLEN) +NAN_BOXED(26134,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(26134,32,FLEN) +NAN_BOXED(26134,32,FLEN) +NAN_BOXED(61496,16,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(26134,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(379,32,FLEN) +NAN_BOXED(261,32,FLEN) +NAN_BOXED(30084,32,FLEN) +NAN_BOXED(30084,32,FLEN) +NAN_BOXED(261,32,FLEN) +NAN_BOXED(261,32,FLEN) +NAN_BOXED(379,32,FLEN) +test_dataset_2: +NAN_BOXED(0,16,FLEN) +NAN_BOXED(261,16,FLEN) +NAN_BOXED(29596,16,FLEN) +NAN_BOXED(14,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(14,16,FLEN) +NAN_BOXED(29596,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(29596,16,FLEN) +NAN_BOXED(1018,16,FLEN) +NAN_BOXED(261,16,FLEN) +NAN_BOXED(31593,16,FLEN) +NAN_BOXED(31593,16,FLEN) +NAN_BOXED(261,16,FLEN) +NAN_BOXED(261,16,FLEN) +NAN_BOXED(1018,16,FLEN) +NAN_BOXED(29596,16,FLEN) +NAN_BOXED(654,16,FLEN) +NAN_BOXED(261,16,FLEN) +NAN_BOXED(30914,16,FLEN) +NAN_BOXED(30914,16,FLEN) +NAN_BOXED(261,16,FLEN) +NAN_BOXED(261,16,FLEN) +NAN_BOXED(654,16,FLEN) +NAN_BOXED(29596,16,FLEN) +NAN_BOXED(535,16,FLEN) +NAN_BOXED(261,16,FLEN) +NAN_BOXED(30667,16,FLEN) +NAN_BOXED(30667,16,FLEN) +NAN_BOXED(261,16,FLEN) +NAN_BOXED(261,16,FLEN) +NAN_BOXED(535,16,FLEN) +NAN_BOXED(29596,16,FLEN) +NAN_BOXED(33173,16,FLEN) +NAN_BOXED(261,16,FLEN) +NAN_BOXED(62951,16,FLEN) +NAN_BOXED(62951,16,FLEN) +NAN_BOXED(261,16,FLEN) +NAN_BOXED(261,16,FLEN) +NAN_BOXED(33173,16,FLEN) +NAN_BOXED(29596,16,FLEN) +NAN_BOXED(32935,16,FLEN) +NAN_BOXED(26,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(26,16,FLEN) +NAN_BOXED(26,16,FLEN) +NAN_BOXED(32935,16,FLEN) +NAN_BOXED(29596,16,FLEN) +NAN_BOXED(26,16,FLEN) +NAN_BOXED(29596,16,FLEN) +NAN_BOXED(33310,16,FLEN) +NAN_BOXED(261,16,FLEN) +NAN_BOXED(63460,16,FLEN) +NAN_BOXED(63460,16,FLEN) +NAN_BOXED(261,16,FLEN) +NAN_BOXED(261,16,FLEN) +NAN_BOXED(33310,16,FLEN) +NAN_BOXED(29596,16,FLEN) +NAN_BOXED(33637,16,FLEN) +NAN_BOXED(261,16,FLEN) +NAN_BOXED(64082,16,FLEN) +NAN_BOXED(64082,16,FLEN) +NAN_BOXED(261,16,FLEN) +NAN_BOXED(261,16,FLEN) +NAN_BOXED(33637,16,FLEN) +NAN_BOXED(29596,16,FLEN) +NAN_BOXED(33033,16,FLEN) +NAN_BOXED(261,16,FLEN) +NAN_BOXED(62393,16,FLEN) +NAN_BOXED(62393,16,FLEN) +NAN_BOXED(261,16,FLEN) +NAN_BOXED(261,16,FLEN) +NAN_BOXED(33033,16,FLEN) +NAN_BOXED(29596,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(15932,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(15932,16,FLEN) +NAN_BOXED(29596,16,FLEN) +NAN_BOXED(15932,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(29733,16,FLEN) +NAN_BOXED(29733,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(31408,16,FLEN) +NAN_BOXED(31408,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(30995,16,FLEN) +NAN_BOXED(30995,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(63305,16,FLEN) +NAN_BOXED(63305,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(64376,16,FLEN) +NAN_BOXED(64376,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(64031,16,FLEN) +NAN_BOXED(64031,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(63535,16,FLEN) +NAN_BOXED(63535,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(61496,16,FLEN) +NAN_BOXED(27648,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(27648,16,FLEN) +NAN_BOXED(27648,16,FLEN) +NAN_BOXED(61496,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(27648,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(379,16,FLEN) +NAN_BOXED(687,16,FLEN) +NAN_BOXED(30084,16,FLEN) +NAN_BOXED(30084,16,FLEN) +NAN_BOXED(687,16,FLEN) +NAN_BOXED(687,16,FLEN) +NAN_BOXED(379,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(687,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(14,16,FLEN) +NAN_BOXED(6,16,FLEN) +NAN_BOXED(31743,16,FLEN) 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+NAN_BOXED(240,16,FLEN) +NAN_BOXED(31408,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(30995,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(63305,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(64376,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(64031,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(63535,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(61496,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(379,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(14,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(1018,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(654,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(535,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(33173,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(32935,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(33310,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(33637,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(33033,16,FLEN) +NAN_BOXED(29596,16,FLEN) +NAN_BOXED(29596,16,FLEN) +NAN_BOXED(29596,16,FLEN) +NAN_BOXED(63305,16,FLEN) +NAN_BOXED(29596,16,FLEN) +NAN_BOXED(261,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(2,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x3_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x3_1: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x5_0: + .fill 32*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_0: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_2: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_3: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_4: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_5: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_6: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_7: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_8: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fle_b1-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fle_b1-01.S new file mode 100644 index 000000000..0bea4ed8e --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fle_b1-01.S @@ -0,0 +1,4759 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 05:47:34 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fle.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fle.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fle_b1 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fle_b1) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x12,test_dataset_0) +RVTEST_SIGBASE(x2,signature_x2_1) + +inst_0:// rs1 != rs2, rs1==x27, rs2==x1, rd==x16,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x27; op2:x1; dest:x16; op1val:0x0; op2val:0x0; +valaddr_reg:x12; val_offset:0*FLEN/8; correctval:??; testreg:x4; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x16, x27, x1, 0, 0, x12, 0*FLEN/8, x19, x2, x4) + +inst_1:// rs1 == rs2, rs1==x11, rs2==x11, rd==x22,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x11; op2:x11; dest:x22; op1val:0x0; op2val:0x0; +valaddr_reg:x12; val_offset:2*FLEN/8; correctval:??; testreg:x4; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x22, x11, x11, 0, 0, x12, 2*FLEN/8, x19, x2, x4) + +inst_2:// rs1==x23, rs2==x9, rd==x6,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x23; op2:x9; dest:x6; op1val:0x0; op2val:0x1; +valaddr_reg:x12; val_offset:4*FLEN/8; correctval:??; testreg:x4; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x6, x23, x9, 0, 0, x12, 4*FLEN/8, x19, x2, x4) + +inst_3:// rs1==x6, rs2==x3, rd==x9,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x6; op2:x3; dest:x9; op1val:0x0; op2val:0x8001; +valaddr_reg:x12; val_offset:6*FLEN/8; correctval:??; testreg:x4; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x9, x6, x3, 0, 0, x12, 6*FLEN/8, x19, x2, x4) + +inst_4:// rs1==x26, rs2==x15, rd==x13,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x26; op2:x15; dest:x13; op1val:0x0; op2val:0x2; +valaddr_reg:x12; val_offset:8*FLEN/8; correctval:??; testreg:x4; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x13, x26, x15, 0, 0, x12, 8*FLEN/8, x19, x2, x4) + +inst_5:// rs1==x31, rs2==x14, rd==x17,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x31; op2:x14; dest:x17; op1val:0x0; op2val:0x83fe; +valaddr_reg:x12; val_offset:10*FLEN/8; correctval:??; testreg:x4; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x17, x31, x14, 0, 0, x12, 10*FLEN/8, x19, x2, x4) + +inst_6:// rs1==x20, rs2==x18, rd==x25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x20; op2:x18; dest:x25; op1val:0x0; op2val:0x3ff; +valaddr_reg:x12; val_offset:12*FLEN/8; correctval:??; testreg:x4; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x25, x20, x18, 0, 0, x12, 12*FLEN/8, x19, x2, x4) + +inst_7:// rs1==x17, rs2==x26, rd==x31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x17; op2:x26; dest:x31; op1val:0x0; op2val:0x83ff; +valaddr_reg:x12; val_offset:14*FLEN/8; correctval:??; testreg:x4; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x17, x26, 0, 0, x12, 14*FLEN/8, x19, x2, x4) + +inst_8:// rs1==x16, rs2==x27, rd==x8,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x16; op2:x27; dest:x8; op1val:0x0; op2val:0x400; +valaddr_reg:x12; val_offset:16*FLEN/8; correctval:??; testreg:x4; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x8, x16, x27, 0, 0, x12, 16*FLEN/8, x19, x2, x4) + +inst_9:// rs1==x9, rs2==x31, rd==x7,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x9; op2:x31; dest:x7; op1val:0x0; op2val:0x8400; +valaddr_reg:x12; val_offset:18*FLEN/8; correctval:??; testreg:x4; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x7, x9, x31, 0, 0, x12, 18*FLEN/8, x19, x2, x4) + +inst_10:// rs1==x22, rs2==x10, rd==x20,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x22; op2:x10; dest:x20; op1val:0x0; op2val:0x401; +valaddr_reg:x12; val_offset:20*FLEN/8; correctval:??; testreg:x4; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x20, x22, x10, 0, 0, x12, 20*FLEN/8, x19, x2, x4) + +inst_11:// rs1==x14, rs2==x5, rd==x18,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x14; op2:x5; dest:x18; op1val:0x0; op2val:0x8455; +valaddr_reg:x12; val_offset:22*FLEN/8; correctval:??; testreg:x4; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x18, x14, x5, 0, 0, x12, 22*FLEN/8, x19, x2, x4) + +inst_12:// rs1==x21, rs2==x16, rd==x27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x21; op2:x16; dest:x27; op1val:0x0; op2val:0x7bff; +valaddr_reg:x12; val_offset:24*FLEN/8; correctval:??; testreg:x4; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x27, x21, x16, 0, 0, x12, 24*FLEN/8, x19, x2, x4) +RVTEST_VALBASEUPD(x6,test_dataset_1) + +inst_13:// rs1==x13, rs2==x17, rd==x19,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x13; op2:x17; dest:x19; op1val:0x0; op2val:0xfbff; +valaddr_reg:x6; val_offset:0*FLEN/8; correctval:??; testreg:x4; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x19, x13, x17, 0, 0, x6, 0*FLEN/8, x16, x2, x4) + +inst_14:// rs1==x7, rs2==x22, rd==x5,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x7; op2:x22; dest:x5; op1val:0x0; op2val:0x7c00; +valaddr_reg:x6; val_offset:2*FLEN/8; correctval:??; testreg:x4; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x5, x7, x22, 0, 0, x6, 2*FLEN/8, x16, x2, x4) + +inst_15:// rs1==x19, rs2==x13, rd==x26,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x19; op2:x13; dest:x26; op1val:0x0; op2val:0xfc00; +valaddr_reg:x6; val_offset:4*FLEN/8; correctval:??; testreg:x4; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x26, x19, x13, 0, 0, x6, 4*FLEN/8, x16, x2, x4) + +inst_16:// rs1==x10, rs2==x19, rd==x28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x10; op2:x19; dest:x28; op1val:0x0; op2val:0x7e00; +valaddr_reg:x6; val_offset:6*FLEN/8; correctval:??; testreg:x4; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x28, x10, x19, 0, 0, x6, 6*FLEN/8, x16, x2, x4) + +inst_17:// rs1==x24, rs2==x8, rd==x1,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x24; op2:x8; dest:x1; op1val:0x0; op2val:0xfe00; +valaddr_reg:x6; val_offset:8*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x1, x24, x8, 0, 0, x6, 8*FLEN/8, x16, x2, x13) +RVTEST_SIGBASE(x9,signature_x9_0) + +inst_18:// rs1==x3, rs2==x2, rd==x11,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x3; op2:x2; dest:x11; op1val:0x0; op2val:0x7e01; +valaddr_reg:x6; val_offset:10*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x11, x3, x2, 0, 0, x6, 10*FLEN/8, x16, x9, x13) + +inst_19:// rs1==x28, rs2==x25, rd==x23,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x28; op2:x25; dest:x23; op1val:0x0; op2val:0xfe55; +valaddr_reg:x6; val_offset:12*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x23, x28, x25, 0, 0, x6, 12*FLEN/8, x16, x9, x13) + +inst_20:// rs1==x15, rs2==x12, rd==x4,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x15; op2:x12; dest:x4; op1val:0x0; op2val:0x7c01; +valaddr_reg:x6; val_offset:14*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x4, x15, x12, 0, 0, x6, 14*FLEN/8, x16, x9, x13) + +inst_21:// rs1==x4, rs2==x28, rd==x24,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x4; op2:x28; dest:x24; op1val:0x0; op2val:0xfd55; +valaddr_reg:x6; val_offset:16*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x24, x4, x28, 0, 0, x6, 16*FLEN/8, x16, x9, x13) + +inst_22:// rs1==x12, rs2==x20, rd==x14,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x12; op2:x20; dest:x14; op1val:0x0; op2val:0x3c00; +valaddr_reg:x6; val_offset:18*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x14, x12, x20, 0, 0, x6, 18*FLEN/8, x16, x9, x13) + +inst_23:// rs1==x29, rs2==x23, rd==x3,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x29; op2:x23; dest:x3; op1val:0x0; op2val:0xbc00; +valaddr_reg:x6; val_offset:20*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x3, x29, x23, 0, 0, x6, 20*FLEN/8, x16, x9, x13) + +inst_24:// rs1==x5, rs2==x21, rd==x10,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x5; op2:x21; dest:x10; op1val:0x8000; op2val:0x0; +valaddr_reg:x6; val_offset:22*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x10, x5, x21, 0, 0, x6, 22*FLEN/8, x16, x9, x13) +RVTEST_VALBASEUPD(x3,test_dataset_2) + +inst_25:// rs1==x1, rs2==x29, rd==x12,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x1; op2:x29; dest:x12; op1val:0x8000; op2val:0x8000; +valaddr_reg:x3; val_offset:0*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x12, x1, x29, 0, 0, x3, 0*FLEN/8, x5, x9, x13) + +inst_26:// rs1==x30, rs2==x4, rd==x15,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x4; dest:x15; op1val:0x8000; op2val:0x1; +valaddr_reg:x3; val_offset:2*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x15, x30, x4, 0, 0, x3, 2*FLEN/8, x5, x9, x13) + +inst_27:// rs1==x0, rs2==x24, rd==x29,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x0; op2:x24; dest:x29; op1val:0x0; op2val:0x8001; +valaddr_reg:x3; val_offset:4*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x29, x0, x24, 0, 0, x3, 4*FLEN/8, x5, x9, x13) + +inst_28:// rs1==x25, rs2==x6, rd==x2,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x25; op2:x6; dest:x2; op1val:0x8000; op2val:0x2; +valaddr_reg:x3; val_offset:6*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x2, x25, x6, 0, 0, x3, 6*FLEN/8, x5, x9, x13) + +inst_29:// rs1==x18, rs2==x7, rd==x0,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x18; op2:x7; dest:x0; op1val:0x8000; op2val:0x83fe; +valaddr_reg:x3; val_offset:8*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x0, x18, x7, 0, 0, x3, 8*FLEN/8, x5, x9, x13) + +inst_30:// rs1==x8, rs2==x30, rd==x21,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x8; op2:x30; dest:x21; op1val:0x8000; op2val:0x3ff; +valaddr_reg:x3; val_offset:10*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x21, x8, x30, 0, 0, x3, 10*FLEN/8, x5, x9, x13) + +inst_31:// rs1==x2, rs2==x0, rd==x30,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x2; op2:x0; dest:x30; op1val:0x8000; op2val:0x0; +valaddr_reg:x3; val_offset:12*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x30, x2, x0, 0, 0, x3, 12*FLEN/8, x5, x9, x13) + +inst_32:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x400; +valaddr_reg:x3; val_offset:14*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 14*FLEN/8, x5, x9, x13) + +inst_33:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8400; +valaddr_reg:x3; val_offset:16*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 16*FLEN/8, x5, x9, x13) + +inst_34:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x401; +valaddr_reg:x3; val_offset:18*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 18*FLEN/8, x5, x9, x13) + +inst_35:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8455; +valaddr_reg:x3; val_offset:20*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 20*FLEN/8, x5, x9, x13) + +inst_36:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x7bff; +valaddr_reg:x3; val_offset:22*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 22*FLEN/8, x5, x9, x13) + +inst_37:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xfbff; +valaddr_reg:x3; val_offset:24*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 24*FLEN/8, x5, x9, x13) + +inst_38:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x7c00; +valaddr_reg:x3; val_offset:26*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 26*FLEN/8, x5, x9, x13) + +inst_39:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xfc00; +valaddr_reg:x3; val_offset:28*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 28*FLEN/8, x5, x9, x13) + +inst_40:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x7e00; +valaddr_reg:x3; val_offset:30*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 30*FLEN/8, x5, x9, x13) + +inst_41:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xfe00; +valaddr_reg:x3; val_offset:32*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 32*FLEN/8, x5, x9, x13) + +inst_42:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x7e01; +valaddr_reg:x3; val_offset:34*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 34*FLEN/8, x5, x9, x13) + +inst_43:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xfe55; +valaddr_reg:x3; val_offset:36*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 36*FLEN/8, x5, x9, x13) + +inst_44:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x7c01; +valaddr_reg:x3; val_offset:38*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 38*FLEN/8, x5, x9, x13) + +inst_45:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xfd55; +valaddr_reg:x3; val_offset:40*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 40*FLEN/8, x5, x9, x13) + +inst_46:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x3c00; +valaddr_reg:x3; val_offset:42*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 42*FLEN/8, x5, x9, x13) + +inst_47:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xbc00; +valaddr_reg:x3; val_offset:44*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 44*FLEN/8, x5, x9, x13) + +inst_48:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x0; +valaddr_reg:x3; val_offset:46*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 46*FLEN/8, x5, x9, x13) + +inst_49:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x8000; +valaddr_reg:x3; val_offset:48*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 48*FLEN/8, x5, x9, x13) + +inst_50:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x1; +valaddr_reg:x3; val_offset:50*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 50*FLEN/8, x5, x9, x13) + +inst_51:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x8001; +valaddr_reg:x3; val_offset:52*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 52*FLEN/8, x5, x9, x13) + +inst_52:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x2; +valaddr_reg:x3; val_offset:54*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 54*FLEN/8, x5, x9, x13) + +inst_53:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x83fe; +valaddr_reg:x3; val_offset:56*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 56*FLEN/8, x5, x9, x13) + +inst_54:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x3ff; +valaddr_reg:x3; val_offset:58*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 58*FLEN/8, x5, x9, x13) + +inst_55:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x83ff; +valaddr_reg:x3; val_offset:60*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 60*FLEN/8, x5, x9, x13) + +inst_56:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x400; +valaddr_reg:x3; val_offset:62*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 62*FLEN/8, x5, x9, x13) + +inst_57:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x8400; +valaddr_reg:x3; val_offset:64*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 64*FLEN/8, x5, x9, x13) + +inst_58:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x401; +valaddr_reg:x3; val_offset:66*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 66*FLEN/8, x5, x9, x13) + +inst_59:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x8455; +valaddr_reg:x3; val_offset:68*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 68*FLEN/8, x5, x9, x13) + +inst_60:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7bff; +valaddr_reg:x3; val_offset:70*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 70*FLEN/8, x5, x9, x13) + +inst_61:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xfbff; +valaddr_reg:x3; val_offset:72*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 72*FLEN/8, x5, x9, x13) + +inst_62:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7c00; +valaddr_reg:x3; val_offset:74*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 74*FLEN/8, x5, x9, x13) + +inst_63:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xfc00; +valaddr_reg:x3; val_offset:76*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 76*FLEN/8, x5, x9, x13) + +inst_64:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7e00; +valaddr_reg:x3; val_offset:78*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 78*FLEN/8, x5, x9, x13) + +inst_65:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xfe00; +valaddr_reg:x3; val_offset:80*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 80*FLEN/8, x5, x9, x13) + +inst_66:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7e01; +valaddr_reg:x3; val_offset:82*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 82*FLEN/8, x5, x9, x13) + +inst_67:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xfe55; +valaddr_reg:x3; val_offset:84*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 84*FLEN/8, x5, x9, x13) + +inst_68:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7c01; +valaddr_reg:x3; val_offset:86*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 86*FLEN/8, x5, x9, x13) + +inst_69:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xfd55; +valaddr_reg:x3; val_offset:88*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 88*FLEN/8, x5, x9, x13) + +inst_70:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x3c00; +valaddr_reg:x3; val_offset:90*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 90*FLEN/8, x5, x9, x13) + +inst_71:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xbc00; +valaddr_reg:x3; val_offset:92*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 92*FLEN/8, x5, x9, x13) + +inst_72:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x0; +valaddr_reg:x3; val_offset:94*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 94*FLEN/8, x5, x9, x13) + +inst_73:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8000; +valaddr_reg:x3; val_offset:96*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 96*FLEN/8, x5, x9, x13) + +inst_74:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x1; +valaddr_reg:x3; val_offset:98*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 98*FLEN/8, x5, x9, x13) + +inst_75:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8001; +valaddr_reg:x3; val_offset:100*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 100*FLEN/8, x5, x9, x13) + +inst_76:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x2; +valaddr_reg:x3; val_offset:102*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 102*FLEN/8, x5, x9, x13) + +inst_77:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x83fe; +valaddr_reg:x3; val_offset:104*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 104*FLEN/8, x5, x9, x13) + +inst_78:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x3ff; +valaddr_reg:x3; val_offset:106*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 106*FLEN/8, x5, x9, x13) + +inst_79:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x83ff; +valaddr_reg:x3; val_offset:108*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 108*FLEN/8, x5, x9, x13) + +inst_80:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x400; +valaddr_reg:x3; val_offset:110*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 110*FLEN/8, x5, x9, x13) + +inst_81:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8400; +valaddr_reg:x3; val_offset:112*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 112*FLEN/8, x5, x9, x13) + +inst_82:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x401; +valaddr_reg:x3; val_offset:114*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 114*FLEN/8, x5, x9, x13) + +inst_83:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8455; +valaddr_reg:x3; val_offset:116*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 116*FLEN/8, x5, x9, x13) + +inst_84:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x7bff; +valaddr_reg:x3; val_offset:118*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 118*FLEN/8, x5, x9, x13) + +inst_85:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xfbff; +valaddr_reg:x3; val_offset:120*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 120*FLEN/8, x5, x9, x13) + +inst_86:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x7c00; +valaddr_reg:x3; val_offset:122*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 122*FLEN/8, x5, x9, x13) + +inst_87:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xfc00; +valaddr_reg:x3; val_offset:124*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 124*FLEN/8, x5, x9, x13) + +inst_88:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x7e00; +valaddr_reg:x3; val_offset:126*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 126*FLEN/8, x5, x9, x13) + +inst_89:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xfe00; +valaddr_reg:x3; val_offset:128*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 128*FLEN/8, x5, x9, x13) + +inst_90:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x7e01; +valaddr_reg:x3; val_offset:130*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 130*FLEN/8, x5, x9, x13) + +inst_91:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xfe55; +valaddr_reg:x3; val_offset:132*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 132*FLEN/8, x5, x9, x13) + +inst_92:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x7c01; +valaddr_reg:x3; val_offset:134*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 134*FLEN/8, x5, x9, x13) + +inst_93:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xfd55; +valaddr_reg:x3; val_offset:136*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 136*FLEN/8, x5, x9, x13) + +inst_94:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x3c00; +valaddr_reg:x3; val_offset:138*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 138*FLEN/8, x5, x9, x13) + +inst_95:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xbc00; +valaddr_reg:x3; val_offset:140*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 140*FLEN/8, x5, x9, x13) + +inst_96:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x0; +valaddr_reg:x3; val_offset:142*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 142*FLEN/8, x5, x9, x13) + +inst_97:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x8000; +valaddr_reg:x3; val_offset:144*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 144*FLEN/8, x5, x9, x13) + +inst_98:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x1; +valaddr_reg:x3; val_offset:146*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 146*FLEN/8, x5, x9, x13) + +inst_99:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x8001; +valaddr_reg:x3; val_offset:148*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 148*FLEN/8, x5, x9, x13) + +inst_100:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x2; +valaddr_reg:x3; val_offset:150*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 150*FLEN/8, x5, x9, x13) + +inst_101:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x83fe; +valaddr_reg:x3; val_offset:152*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 152*FLEN/8, x5, x9, x13) + +inst_102:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x3ff; +valaddr_reg:x3; val_offset:154*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 154*FLEN/8, x5, x9, x13) + +inst_103:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x83ff; +valaddr_reg:x3; val_offset:156*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 156*FLEN/8, x5, x9, x13) + +inst_104:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x400; +valaddr_reg:x3; val_offset:158*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 158*FLEN/8, x5, x9, x13) + +inst_105:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x8400; +valaddr_reg:x3; val_offset:160*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 160*FLEN/8, x5, x9, x13) + +inst_106:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x401; +valaddr_reg:x3; val_offset:162*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 162*FLEN/8, x5, x9, x13) + +inst_107:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x8455; +valaddr_reg:x3; val_offset:164*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 164*FLEN/8, x5, x9, x13) + +inst_108:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x7bff; +valaddr_reg:x3; val_offset:166*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 166*FLEN/8, x5, x9, x13) + +inst_109:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xfbff; +valaddr_reg:x3; val_offset:168*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 168*FLEN/8, x5, x9, x13) + +inst_110:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x7c00; +valaddr_reg:x3; val_offset:170*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 170*FLEN/8, x5, x9, x13) + +inst_111:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xfc00; +valaddr_reg:x3; val_offset:172*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 172*FLEN/8, x5, x9, x13) + +inst_112:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x7e00; +valaddr_reg:x3; val_offset:174*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 174*FLEN/8, x5, x9, x13) + +inst_113:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xfe00; +valaddr_reg:x3; val_offset:176*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 176*FLEN/8, x5, x9, x13) + +inst_114:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x7e01; +valaddr_reg:x3; val_offset:178*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 178*FLEN/8, x5, x9, x13) + +inst_115:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xfe55; +valaddr_reg:x3; val_offset:180*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 180*FLEN/8, x5, x9, x13) + +inst_116:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x7c01; +valaddr_reg:x3; val_offset:182*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 182*FLEN/8, x5, x9, x13) + +inst_117:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xfd55; +valaddr_reg:x3; val_offset:184*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 184*FLEN/8, x5, x9, x13) + +inst_118:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x3c00; +valaddr_reg:x3; val_offset:186*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 186*FLEN/8, x5, x9, x13) + +inst_119:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xbc00; +valaddr_reg:x3; val_offset:188*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 188*FLEN/8, x5, x9, x13) + +inst_120:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x0; +valaddr_reg:x3; val_offset:190*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 190*FLEN/8, x5, x9, x13) + +inst_121:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x8000; +valaddr_reg:x3; val_offset:192*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 192*FLEN/8, x5, x9, x13) + +inst_122:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x1; +valaddr_reg:x3; val_offset:194*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 194*FLEN/8, x5, x9, x13) + +inst_123:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x8001; +valaddr_reg:x3; val_offset:196*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 196*FLEN/8, x5, x9, x13) + +inst_124:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x2; +valaddr_reg:x3; val_offset:198*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 198*FLEN/8, x5, x9, x13) + +inst_125:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x83fe; +valaddr_reg:x3; val_offset:200*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 200*FLEN/8, x5, x9, x13) + +inst_126:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x3ff; +valaddr_reg:x3; val_offset:202*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 202*FLEN/8, x5, x9, x13) + +inst_127:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x83ff; +valaddr_reg:x3; val_offset:204*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 204*FLEN/8, x5, x9, x13) + +inst_128:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x400; +valaddr_reg:x3; val_offset:206*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 206*FLEN/8, x5, x9, x13) + +inst_129:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x8400; +valaddr_reg:x3; val_offset:208*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 208*FLEN/8, x5, x9, x13) + +inst_130:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x401; +valaddr_reg:x3; val_offset:210*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 210*FLEN/8, x5, x9, x13) + +inst_131:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x8455; +valaddr_reg:x3; val_offset:212*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 212*FLEN/8, x5, x9, x13) + +inst_132:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x7bff; +valaddr_reg:x3; val_offset:214*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 214*FLEN/8, x5, x9, x13) + +inst_133:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xfbff; +valaddr_reg:x3; val_offset:216*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 216*FLEN/8, x5, x9, x13) + +inst_134:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x7c00; +valaddr_reg:x3; val_offset:218*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 218*FLEN/8, x5, x9, x13) + +inst_135:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xfc00; +valaddr_reg:x3; val_offset:220*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 220*FLEN/8, x5, x9, x13) + +inst_136:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x7e00; +valaddr_reg:x3; val_offset:222*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 222*FLEN/8, x5, x9, x13) + +inst_137:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xfe00; +valaddr_reg:x3; val_offset:224*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 224*FLEN/8, x5, x9, x13) + +inst_138:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x7e01; +valaddr_reg:x3; val_offset:226*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 226*FLEN/8, x5, x9, x13) + +inst_139:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xfe55; +valaddr_reg:x3; val_offset:228*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 228*FLEN/8, x5, x9, x13) + +inst_140:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x7c01; +valaddr_reg:x3; val_offset:230*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 230*FLEN/8, x5, x9, x13) + +inst_141:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xfd55; +valaddr_reg:x3; val_offset:232*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 232*FLEN/8, x5, x9, x13) + +inst_142:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x3c00; +valaddr_reg:x3; val_offset:234*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 234*FLEN/8, x5, x9, x13) + +inst_143:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xbc00; +valaddr_reg:x3; val_offset:236*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 236*FLEN/8, x5, x9, x13) + +inst_144:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x0; +valaddr_reg:x3; val_offset:238*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 238*FLEN/8, x5, x9, x13) + +inst_145:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x8000; +valaddr_reg:x3; val_offset:240*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 240*FLEN/8, x5, x9, x13) +RVTEST_SIGBASE(x9,signature_x9_1) + +inst_146:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x1; +valaddr_reg:x3; val_offset:242*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 242*FLEN/8, x5, x9, x13) + +inst_147:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x8001; +valaddr_reg:x3; val_offset:244*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 244*FLEN/8, x5, x9, x13) + +inst_148:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x2; +valaddr_reg:x3; val_offset:246*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 246*FLEN/8, x5, x9, x13) + +inst_149:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x83fe; +valaddr_reg:x3; val_offset:248*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 248*FLEN/8, x5, x9, x13) + +inst_150:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x3ff; +valaddr_reg:x3; val_offset:250*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 250*FLEN/8, x5, x9, x13) + +inst_151:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x83ff; +valaddr_reg:x3; val_offset:252*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 252*FLEN/8, x5, x9, x13) + +inst_152:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x400; +valaddr_reg:x3; val_offset:254*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 254*FLEN/8, x5, x9, x13) + +inst_153:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x8400; +valaddr_reg:x3; val_offset:256*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 256*FLEN/8, x5, x9, x13) + +inst_154:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x401; +valaddr_reg:x3; val_offset:258*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 258*FLEN/8, x5, x9, x13) + +inst_155:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x8455; +valaddr_reg:x3; val_offset:260*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 260*FLEN/8, x5, x9, x13) + +inst_156:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7bff; +valaddr_reg:x3; val_offset:262*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 262*FLEN/8, x5, x9, x13) + +inst_157:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xfbff; +valaddr_reg:x3; val_offset:264*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 264*FLEN/8, x5, x9, x13) + +inst_158:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7c00; +valaddr_reg:x3; val_offset:266*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 266*FLEN/8, x5, x9, x13) + +inst_159:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xfc00; +valaddr_reg:x3; val_offset:268*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 268*FLEN/8, x5, x9, x13) + +inst_160:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7e00; +valaddr_reg:x3; val_offset:270*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 270*FLEN/8, x5, x9, x13) + +inst_161:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xfe00; +valaddr_reg:x3; val_offset:272*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 272*FLEN/8, x5, x9, x13) + +inst_162:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7e01; +valaddr_reg:x3; val_offset:274*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 274*FLEN/8, x5, x9, x13) + +inst_163:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xfe55; +valaddr_reg:x3; val_offset:276*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 276*FLEN/8, x5, x9, x13) + +inst_164:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7c01; +valaddr_reg:x3; val_offset:278*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 278*FLEN/8, x5, x9, x13) + +inst_165:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xfd55; +valaddr_reg:x3; val_offset:280*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 280*FLEN/8, x5, x9, x13) + +inst_166:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x3c00; +valaddr_reg:x3; val_offset:282*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 282*FLEN/8, x5, x9, x13) + +inst_167:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xbc00; +valaddr_reg:x3; val_offset:284*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 284*FLEN/8, x5, x9, x13) + +inst_168:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x0; +valaddr_reg:x3; val_offset:286*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 286*FLEN/8, x5, x9, x13) + +inst_169:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8000; +valaddr_reg:x3; val_offset:288*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 288*FLEN/8, x5, x9, x13) + +inst_170:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x1; +valaddr_reg:x3; val_offset:290*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 290*FLEN/8, x5, x9, x13) + +inst_171:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8001; +valaddr_reg:x3; val_offset:292*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 292*FLEN/8, x5, x9, x13) + +inst_172:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x2; +valaddr_reg:x3; val_offset:294*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 294*FLEN/8, x5, x9, x13) + +inst_173:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x83fe; +valaddr_reg:x3; val_offset:296*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 296*FLEN/8, x5, x9, x13) + +inst_174:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x3ff; +valaddr_reg:x3; val_offset:298*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 298*FLEN/8, x5, x9, x13) + +inst_175:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x83ff; +valaddr_reg:x3; val_offset:300*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 300*FLEN/8, x5, x9, x13) + +inst_176:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x400; +valaddr_reg:x3; val_offset:302*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 302*FLEN/8, x5, x9, x13) + +inst_177:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8400; +valaddr_reg:x3; val_offset:304*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 304*FLEN/8, x5, x9, x13) + +inst_178:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x401; +valaddr_reg:x3; val_offset:306*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 306*FLEN/8, x5, x9, x13) + +inst_179:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8455; +valaddr_reg:x3; val_offset:308*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 308*FLEN/8, x5, x9, x13) + +inst_180:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x7bff; +valaddr_reg:x3; val_offset:310*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 310*FLEN/8, x5, x9, x13) + +inst_181:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xfbff; +valaddr_reg:x3; val_offset:312*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 312*FLEN/8, x5, x9, x13) + +inst_182:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x7c00; +valaddr_reg:x3; val_offset:314*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 314*FLEN/8, x5, x9, x13) + +inst_183:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xfc00; +valaddr_reg:x3; val_offset:316*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 316*FLEN/8, x5, x9, x13) + +inst_184:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x7e00; +valaddr_reg:x3; val_offset:318*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 318*FLEN/8, x5, x9, x13) + +inst_185:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xfe00; +valaddr_reg:x3; val_offset:320*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 320*FLEN/8, x5, x9, x13) + +inst_186:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x7e01; +valaddr_reg:x3; val_offset:322*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 322*FLEN/8, x5, x9, x13) + +inst_187:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xfe55; +valaddr_reg:x3; val_offset:324*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 324*FLEN/8, x5, x9, x13) + +inst_188:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x7c01; +valaddr_reg:x3; val_offset:326*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 326*FLEN/8, x5, x9, x13) + +inst_189:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xfd55; +valaddr_reg:x3; val_offset:328*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 328*FLEN/8, x5, x9, x13) + +inst_190:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x3c00; +valaddr_reg:x3; val_offset:330*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 330*FLEN/8, x5, x9, x13) + +inst_191:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xbc00; +valaddr_reg:x3; val_offset:332*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 332*FLEN/8, x5, x9, x13) + +inst_192:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x0; +valaddr_reg:x3; val_offset:334*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 334*FLEN/8, x5, x9, x13) + +inst_193:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x8000; +valaddr_reg:x3; val_offset:336*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 336*FLEN/8, x5, x9, x13) + +inst_194:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x1; +valaddr_reg:x3; val_offset:338*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 338*FLEN/8, x5, x9, x13) + +inst_195:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x8001; +valaddr_reg:x3; val_offset:340*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 340*FLEN/8, x5, x9, x13) + +inst_196:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x2; +valaddr_reg:x3; val_offset:342*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 342*FLEN/8, x5, x9, x13) + +inst_197:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x83fe; +valaddr_reg:x3; val_offset:344*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 344*FLEN/8, x5, x9, x13) + +inst_198:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x3ff; +valaddr_reg:x3; val_offset:346*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 346*FLEN/8, x5, x9, x13) + +inst_199:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x83ff; +valaddr_reg:x3; val_offset:348*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 348*FLEN/8, x5, x9, x13) + +inst_200:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x400; +valaddr_reg:x3; val_offset:350*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 350*FLEN/8, x5, x9, x13) + +inst_201:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x8400; +valaddr_reg:x3; val_offset:352*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 352*FLEN/8, x5, x9, x13) + +inst_202:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x401; +valaddr_reg:x3; val_offset:354*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 354*FLEN/8, x5, x9, x13) + +inst_203:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x8455; +valaddr_reg:x3; val_offset:356*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 356*FLEN/8, x5, x9, x13) + +inst_204:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7bff; +valaddr_reg:x3; val_offset:358*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 358*FLEN/8, x5, x9, x13) + +inst_205:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xfbff; +valaddr_reg:x3; val_offset:360*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 360*FLEN/8, x5, x9, x13) + +inst_206:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7c00; +valaddr_reg:x3; val_offset:362*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 362*FLEN/8, x5, x9, x13) + +inst_207:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xfc00; +valaddr_reg:x3; val_offset:364*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 364*FLEN/8, x5, x9, x13) + +inst_208:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7e00; +valaddr_reg:x3; val_offset:366*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 366*FLEN/8, x5, x9, x13) + +inst_209:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xfe00; +valaddr_reg:x3; val_offset:368*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 368*FLEN/8, x5, x9, x13) + +inst_210:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7e01; +valaddr_reg:x3; val_offset:370*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 370*FLEN/8, x5, x9, x13) + +inst_211:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xfe55; +valaddr_reg:x3; val_offset:372*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 372*FLEN/8, x5, x9, x13) + +inst_212:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7c01; +valaddr_reg:x3; val_offset:374*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 374*FLEN/8, x5, x9, x13) + +inst_213:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xfd55; +valaddr_reg:x3; val_offset:376*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 376*FLEN/8, x5, x9, x13) + +inst_214:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x3c00; +valaddr_reg:x3; val_offset:378*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 378*FLEN/8, x5, x9, x13) + +inst_215:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xbc00; +valaddr_reg:x3; val_offset:380*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 380*FLEN/8, x5, x9, x13) + +inst_216:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x0; +valaddr_reg:x3; val_offset:382*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 382*FLEN/8, x5, x9, x13) + +inst_217:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8000; +valaddr_reg:x3; val_offset:384*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 384*FLEN/8, x5, x9, x13) + +inst_218:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x1; +valaddr_reg:x3; val_offset:386*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 386*FLEN/8, x5, x9, x13) + +inst_219:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8001; +valaddr_reg:x3; val_offset:388*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 388*FLEN/8, x5, x9, x13) + +inst_220:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x2; +valaddr_reg:x3; val_offset:390*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 390*FLEN/8, x5, x9, x13) + +inst_221:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x83fe; +valaddr_reg:x3; val_offset:392*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 392*FLEN/8, x5, x9, x13) + +inst_222:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x3ff; +valaddr_reg:x3; val_offset:394*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 394*FLEN/8, x5, x9, x13) + +inst_223:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x83ff; +valaddr_reg:x3; val_offset:396*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 396*FLEN/8, x5, x9, x13) + +inst_224:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x400; +valaddr_reg:x3; val_offset:398*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 398*FLEN/8, x5, x9, x13) + +inst_225:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8400; +valaddr_reg:x3; val_offset:400*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 400*FLEN/8, x5, x9, x13) + +inst_226:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x401; +valaddr_reg:x3; val_offset:402*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 402*FLEN/8, x5, x9, x13) + +inst_227:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8455; +valaddr_reg:x3; val_offset:404*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 404*FLEN/8, x5, x9, x13) + +inst_228:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x7bff; +valaddr_reg:x3; val_offset:406*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 406*FLEN/8, x5, x9, x13) + +inst_229:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xfbff; +valaddr_reg:x3; val_offset:408*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 408*FLEN/8, x5, x9, x13) + +inst_230:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x7c00; +valaddr_reg:x3; val_offset:410*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 410*FLEN/8, x5, x9, x13) + +inst_231:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xfc00; +valaddr_reg:x3; val_offset:412*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 412*FLEN/8, x5, x9, x13) + +inst_232:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x7e00; +valaddr_reg:x3; val_offset:414*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 414*FLEN/8, x5, x9, x13) + +inst_233:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xfe00; +valaddr_reg:x3; val_offset:416*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 416*FLEN/8, x5, x9, x13) + +inst_234:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x7e01; +valaddr_reg:x3; val_offset:418*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 418*FLEN/8, x5, x9, x13) + +inst_235:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xfe55; +valaddr_reg:x3; val_offset:420*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 420*FLEN/8, x5, x9, x13) + +inst_236:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x7c01; +valaddr_reg:x3; val_offset:422*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 422*FLEN/8, x5, x9, x13) + +inst_237:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xfd55; +valaddr_reg:x3; val_offset:424*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 424*FLEN/8, x5, x9, x13) + +inst_238:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x3c00; +valaddr_reg:x3; val_offset:426*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 426*FLEN/8, x5, x9, x13) + +inst_239:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xbc00; +valaddr_reg:x3; val_offset:428*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 428*FLEN/8, x5, x9, x13) + +inst_240:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x0; +valaddr_reg:x3; val_offset:430*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 430*FLEN/8, x5, x9, x13) + +inst_241:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x8000; +valaddr_reg:x3; val_offset:432*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 432*FLEN/8, x5, x9, x13) + +inst_242:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x1; +valaddr_reg:x3; val_offset:434*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 434*FLEN/8, x5, x9, x13) + +inst_243:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x8001; +valaddr_reg:x3; val_offset:436*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 436*FLEN/8, x5, x9, x13) + +inst_244:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x2; +valaddr_reg:x3; val_offset:438*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 438*FLEN/8, x5, x9, x13) + +inst_245:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x83fe; +valaddr_reg:x3; val_offset:440*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 440*FLEN/8, x5, x9, x13) + +inst_246:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x3ff; +valaddr_reg:x3; val_offset:442*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 442*FLEN/8, x5, x9, x13) + +inst_247:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x83ff; +valaddr_reg:x3; val_offset:444*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 444*FLEN/8, x5, x9, x13) + +inst_248:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x400; +valaddr_reg:x3; val_offset:446*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 446*FLEN/8, x5, x9, x13) + +inst_249:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x8400; +valaddr_reg:x3; val_offset:448*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 448*FLEN/8, x5, x9, x13) + +inst_250:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x401; +valaddr_reg:x3; val_offset:450*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 450*FLEN/8, x5, x9, x13) + +inst_251:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x8455; +valaddr_reg:x3; val_offset:452*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 452*FLEN/8, x5, x9, x13) + +inst_252:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x7bff; +valaddr_reg:x3; val_offset:454*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 454*FLEN/8, x5, x9, x13) + +inst_253:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xfbff; +valaddr_reg:x3; val_offset:456*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 456*FLEN/8, x5, x9, x13) + +inst_254:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x7c00; +valaddr_reg:x3; val_offset:458*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 458*FLEN/8, x5, x9, x13) + +inst_255:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xfc00; +valaddr_reg:x3; val_offset:460*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 460*FLEN/8, x5, x9, x13) + +inst_256:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x7e00; +valaddr_reg:x3; val_offset:462*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 462*FLEN/8, x5, x9, x13) + +inst_257:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xfe00; +valaddr_reg:x3; val_offset:464*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 464*FLEN/8, x5, x9, x13) + +inst_258:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x7e01; +valaddr_reg:x3; val_offset:466*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 466*FLEN/8, x5, x9, x13) + +inst_259:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xfe55; +valaddr_reg:x3; val_offset:468*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 468*FLEN/8, x5, x9, x13) + +inst_260:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x7c01; +valaddr_reg:x3; val_offset:470*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 470*FLEN/8, x5, x9, x13) + +inst_261:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xfd55; +valaddr_reg:x3; val_offset:472*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 472*FLEN/8, x5, x9, x13) + +inst_262:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x3c00; +valaddr_reg:x3; val_offset:474*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 474*FLEN/8, x5, x9, x13) + +inst_263:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xbc00; +valaddr_reg:x3; val_offset:476*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 476*FLEN/8, x5, x9, x13) + +inst_264:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x0; +valaddr_reg:x3; val_offset:478*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 478*FLEN/8, x5, x9, x13) + +inst_265:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x8000; +valaddr_reg:x3; val_offset:480*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 480*FLEN/8, x5, x9, x13) + +inst_266:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x1; +valaddr_reg:x3; val_offset:482*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 482*FLEN/8, x5, x9, x13) + +inst_267:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x8001; +valaddr_reg:x3; val_offset:484*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 484*FLEN/8, x5, x9, x13) + +inst_268:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x2; +valaddr_reg:x3; val_offset:486*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 486*FLEN/8, x5, x9, x13) + +inst_269:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x83fe; +valaddr_reg:x3; val_offset:488*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 488*FLEN/8, x5, x9, x13) + +inst_270:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x3ff; +valaddr_reg:x3; val_offset:490*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 490*FLEN/8, x5, x9, x13) + +inst_271:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x83ff; +valaddr_reg:x3; val_offset:492*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 492*FLEN/8, x5, x9, x13) + +inst_272:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x400; +valaddr_reg:x3; val_offset:494*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 494*FLEN/8, x5, x9, x13) + +inst_273:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x8400; +valaddr_reg:x3; val_offset:496*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 496*FLEN/8, x5, x9, x13) +RVTEST_SIGBASE(x9,signature_x9_2) + +inst_274:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x401; +valaddr_reg:x3; val_offset:498*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 498*FLEN/8, x5, x9, x13) + +inst_275:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x8455; +valaddr_reg:x3; val_offset:500*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 500*FLEN/8, x5, x9, x13) + +inst_276:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x7bff; +valaddr_reg:x3; val_offset:502*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 502*FLEN/8, x5, x9, x13) + +inst_277:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xfbff; +valaddr_reg:x3; val_offset:504*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 504*FLEN/8, x5, x9, x13) + +inst_278:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x7c00; +valaddr_reg:x3; val_offset:506*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 506*FLEN/8, x5, x9, x13) + +inst_279:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xfc00; +valaddr_reg:x3; val_offset:508*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 508*FLEN/8, x5, x9, x13) + +inst_280:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x7e00; +valaddr_reg:x3; val_offset:510*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 510*FLEN/8, x5, x9, x13) + +inst_281:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xfe00; +valaddr_reg:x3; val_offset:512*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 512*FLEN/8, x5, x9, x13) + +inst_282:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x7e01; +valaddr_reg:x3; val_offset:514*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 514*FLEN/8, x5, x9, x13) + +inst_283:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xfe55; +valaddr_reg:x3; val_offset:516*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 516*FLEN/8, x5, x9, x13) + +inst_284:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x7c01; +valaddr_reg:x3; val_offset:518*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 518*FLEN/8, x5, x9, x13) + +inst_285:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xfd55; +valaddr_reg:x3; val_offset:520*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 520*FLEN/8, x5, x9, x13) + +inst_286:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x3c00; +valaddr_reg:x3; val_offset:522*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 522*FLEN/8, x5, x9, x13) + +inst_287:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xbc00; +valaddr_reg:x3; val_offset:524*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 524*FLEN/8, x5, x9, x13) + +inst_288:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x0; +valaddr_reg:x3; val_offset:526*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 526*FLEN/8, x5, x9, x13) + +inst_289:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8000; +valaddr_reg:x3; val_offset:528*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 528*FLEN/8, x5, x9, x13) + +inst_290:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x1; +valaddr_reg:x3; val_offset:530*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 530*FLEN/8, x5, x9, x13) + +inst_291:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8001; +valaddr_reg:x3; val_offset:532*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 532*FLEN/8, x5, x9, x13) + +inst_292:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x2; +valaddr_reg:x3; val_offset:534*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 534*FLEN/8, x5, x9, x13) + +inst_293:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x83fe; +valaddr_reg:x3; val_offset:536*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 536*FLEN/8, x5, x9, x13) + +inst_294:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x3ff; +valaddr_reg:x3; val_offset:538*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 538*FLEN/8, x5, x9, x13) + +inst_295:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x83ff; +valaddr_reg:x3; val_offset:540*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 540*FLEN/8, x5, x9, x13) + +inst_296:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x400; +valaddr_reg:x3; val_offset:542*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 542*FLEN/8, x5, x9, x13) + +inst_297:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8400; +valaddr_reg:x3; val_offset:544*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 544*FLEN/8, x5, x9, x13) + +inst_298:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x401; +valaddr_reg:x3; val_offset:546*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 546*FLEN/8, x5, x9, x13) + +inst_299:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8455; +valaddr_reg:x3; val_offset:548*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 548*FLEN/8, x5, x9, x13) + +inst_300:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7bff; +valaddr_reg:x3; val_offset:550*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 550*FLEN/8, x5, x9, x13) + +inst_301:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xfbff; +valaddr_reg:x3; val_offset:552*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 552*FLEN/8, x5, x9, x13) + +inst_302:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7c00; +valaddr_reg:x3; val_offset:554*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 554*FLEN/8, x5, x9, x13) + +inst_303:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xfc00; +valaddr_reg:x3; val_offset:556*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 556*FLEN/8, x5, x9, x13) + +inst_304:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7e00; +valaddr_reg:x3; val_offset:558*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 558*FLEN/8, x5, x9, x13) + +inst_305:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xfe00; +valaddr_reg:x3; val_offset:560*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 560*FLEN/8, x5, x9, x13) + +inst_306:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7e01; +valaddr_reg:x3; val_offset:562*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 562*FLEN/8, x5, x9, x13) + +inst_307:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xfe55; +valaddr_reg:x3; val_offset:564*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 564*FLEN/8, x5, x9, x13) + +inst_308:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7c01; +valaddr_reg:x3; val_offset:566*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 566*FLEN/8, x5, x9, x13) + +inst_309:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xfd55; +valaddr_reg:x3; val_offset:568*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 568*FLEN/8, x5, x9, x13) + +inst_310:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x3c00; +valaddr_reg:x3; val_offset:570*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 570*FLEN/8, x5, x9, x13) + +inst_311:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xbc00; +valaddr_reg:x3; val_offset:572*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 572*FLEN/8, x5, x9, x13) + +inst_312:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x0; +valaddr_reg:x3; val_offset:574*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 574*FLEN/8, x5, x9, x13) + +inst_313:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8000; +valaddr_reg:x3; val_offset:576*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 576*FLEN/8, x5, x9, x13) + +inst_314:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x1; +valaddr_reg:x3; val_offset:578*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 578*FLEN/8, x5, x9, x13) + +inst_315:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8001; +valaddr_reg:x3; val_offset:580*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 580*FLEN/8, x5, x9, x13) + +inst_316:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x2; +valaddr_reg:x3; val_offset:582*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 582*FLEN/8, x5, x9, x13) + +inst_317:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x83fe; +valaddr_reg:x3; val_offset:584*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 584*FLEN/8, x5, x9, x13) + +inst_318:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x3ff; +valaddr_reg:x3; val_offset:586*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 586*FLEN/8, x5, x9, x13) + +inst_319:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x83ff; +valaddr_reg:x3; val_offset:588*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 588*FLEN/8, x5, x9, x13) + +inst_320:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x400; +valaddr_reg:x3; val_offset:590*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 590*FLEN/8, x5, x9, x13) + +inst_321:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8400; +valaddr_reg:x3; val_offset:592*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 592*FLEN/8, x5, x9, x13) + +inst_322:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x401; +valaddr_reg:x3; val_offset:594*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 594*FLEN/8, x5, x9, x13) + +inst_323:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8455; +valaddr_reg:x3; val_offset:596*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 596*FLEN/8, x5, x9, x13) + +inst_324:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7bff; +valaddr_reg:x3; val_offset:598*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 598*FLEN/8, x5, x9, x13) + +inst_325:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfbff; +valaddr_reg:x3; val_offset:600*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 600*FLEN/8, x5, x9, x13) + +inst_326:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7c00; +valaddr_reg:x3; val_offset:602*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 602*FLEN/8, x5, x9, x13) + +inst_327:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfc00; +valaddr_reg:x3; val_offset:604*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 604*FLEN/8, x5, x9, x13) + +inst_328:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7e00; +valaddr_reg:x3; val_offset:606*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 606*FLEN/8, x5, x9, x13) + +inst_329:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfe00; +valaddr_reg:x3; val_offset:608*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 608*FLEN/8, x5, x9, x13) + +inst_330:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7e01; +valaddr_reg:x3; val_offset:610*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 610*FLEN/8, x5, x9, x13) + +inst_331:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfe55; +valaddr_reg:x3; val_offset:612*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 612*FLEN/8, x5, x9, x13) + +inst_332:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7c01; +valaddr_reg:x3; val_offset:614*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 614*FLEN/8, x5, x9, x13) + +inst_333:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfd55; +valaddr_reg:x3; val_offset:616*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 616*FLEN/8, x5, x9, x13) + +inst_334:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x3c00; +valaddr_reg:x3; val_offset:618*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 618*FLEN/8, x5, x9, x13) + +inst_335:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xbc00; +valaddr_reg:x3; val_offset:620*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 620*FLEN/8, x5, x9, x13) + +inst_336:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x0; +valaddr_reg:x3; val_offset:622*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 622*FLEN/8, x5, x9, x13) + +inst_337:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x8000; +valaddr_reg:x3; val_offset:624*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 624*FLEN/8, x5, x9, x13) + +inst_338:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x1; +valaddr_reg:x3; val_offset:626*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 626*FLEN/8, x5, x9, x13) + +inst_339:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x8001; +valaddr_reg:x3; val_offset:628*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 628*FLEN/8, x5, x9, x13) + +inst_340:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x2; +valaddr_reg:x3; val_offset:630*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 630*FLEN/8, x5, x9, x13) + +inst_341:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x83fe; +valaddr_reg:x3; val_offset:632*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 632*FLEN/8, x5, x9, x13) + +inst_342:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x3ff; +valaddr_reg:x3; val_offset:634*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 634*FLEN/8, x5, x9, x13) + +inst_343:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x83ff; +valaddr_reg:x3; val_offset:636*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 636*FLEN/8, x5, x9, x13) + +inst_344:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x400; +valaddr_reg:x3; val_offset:638*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 638*FLEN/8, x5, x9, x13) + +inst_345:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x8400; +valaddr_reg:x3; val_offset:640*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 640*FLEN/8, x5, x9, x13) + +inst_346:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x401; +valaddr_reg:x3; val_offset:642*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 642*FLEN/8, x5, x9, x13) + +inst_347:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x8455; +valaddr_reg:x3; val_offset:644*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 644*FLEN/8, x5, x9, x13) + +inst_348:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x7bff; +valaddr_reg:x3; val_offset:646*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 646*FLEN/8, x5, x9, x13) + +inst_349:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xfbff; +valaddr_reg:x3; val_offset:648*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 648*FLEN/8, x5, x9, x13) + +inst_350:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x7c00; +valaddr_reg:x3; val_offset:650*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 650*FLEN/8, x5, x9, x13) + +inst_351:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xfc00; +valaddr_reg:x3; val_offset:652*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 652*FLEN/8, x5, x9, x13) + +inst_352:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x7e00; +valaddr_reg:x3; val_offset:654*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 654*FLEN/8, x5, x9, x13) + +inst_353:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xfe00; +valaddr_reg:x3; val_offset:656*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 656*FLEN/8, x5, x9, x13) + +inst_354:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x7e01; +valaddr_reg:x3; val_offset:658*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 658*FLEN/8, x5, x9, x13) + +inst_355:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xfe55; +valaddr_reg:x3; val_offset:660*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 660*FLEN/8, x5, x9, x13) + +inst_356:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x7c01; +valaddr_reg:x3; val_offset:662*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 662*FLEN/8, x5, x9, x13) + +inst_357:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xfd55; +valaddr_reg:x3; val_offset:664*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 664*FLEN/8, x5, x9, x13) + +inst_358:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x3c00; +valaddr_reg:x3; val_offset:666*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 666*FLEN/8, x5, x9, x13) + +inst_359:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xbc00; +valaddr_reg:x3; val_offset:668*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 668*FLEN/8, x5, x9, x13) + +inst_360:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x0; +valaddr_reg:x3; val_offset:670*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 670*FLEN/8, x5, x9, x13) + +inst_361:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x8000; +valaddr_reg:x3; val_offset:672*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 672*FLEN/8, x5, x9, x13) + +inst_362:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x1; +valaddr_reg:x3; val_offset:674*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 674*FLEN/8, x5, x9, x13) + +inst_363:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x8001; +valaddr_reg:x3; val_offset:676*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 676*FLEN/8, x5, x9, x13) + +inst_364:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x2; +valaddr_reg:x3; val_offset:678*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 678*FLEN/8, x5, x9, x13) + +inst_365:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x83fe; +valaddr_reg:x3; val_offset:680*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 680*FLEN/8, x5, x9, x13) + +inst_366:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x3ff; +valaddr_reg:x3; val_offset:682*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 682*FLEN/8, x5, x9, x13) + +inst_367:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x83ff; +valaddr_reg:x3; val_offset:684*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 684*FLEN/8, x5, x9, x13) + +inst_368:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x400; +valaddr_reg:x3; val_offset:686*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 686*FLEN/8, x5, x9, x13) + +inst_369:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x8400; +valaddr_reg:x3; val_offset:688*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 688*FLEN/8, x5, x9, x13) + +inst_370:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x401; +valaddr_reg:x3; val_offset:690*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 690*FLEN/8, x5, x9, x13) + +inst_371:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x8455; +valaddr_reg:x3; val_offset:692*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 692*FLEN/8, x5, x9, x13) + +inst_372:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x7bff; +valaddr_reg:x3; val_offset:694*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 694*FLEN/8, x5, x9, x13) + +inst_373:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xfbff; +valaddr_reg:x3; val_offset:696*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 696*FLEN/8, x5, x9, x13) + +inst_374:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x7c00; +valaddr_reg:x3; val_offset:698*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 698*FLEN/8, x5, x9, x13) + +inst_375:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xfc00; +valaddr_reg:x3; val_offset:700*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 700*FLEN/8, x5, x9, x13) + +inst_376:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x7e00; +valaddr_reg:x3; val_offset:702*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 702*FLEN/8, x5, x9, x13) + +inst_377:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xfe00; +valaddr_reg:x3; val_offset:704*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 704*FLEN/8, x5, x9, x13) + +inst_378:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x7e01; +valaddr_reg:x3; val_offset:706*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 706*FLEN/8, x5, x9, x13) + +inst_379:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xfe55; +valaddr_reg:x3; val_offset:708*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 708*FLEN/8, x5, x9, x13) + +inst_380:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x7c01; +valaddr_reg:x3; val_offset:710*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 710*FLEN/8, x5, x9, x13) + +inst_381:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xfd55; +valaddr_reg:x3; val_offset:712*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 712*FLEN/8, x5, x9, x13) + +inst_382:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x3c00; +valaddr_reg:x3; val_offset:714*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 714*FLEN/8, x5, x9, x13) + +inst_383:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xbc00; +valaddr_reg:x3; val_offset:716*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 716*FLEN/8, x5, x9, x13) + +inst_384:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x0; +valaddr_reg:x3; val_offset:718*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 718*FLEN/8, x5, x9, x13) + +inst_385:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x8000; +valaddr_reg:x3; val_offset:720*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 720*FLEN/8, x5, x9, x13) + +inst_386:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x1; +valaddr_reg:x3; val_offset:722*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 722*FLEN/8, x5, x9, x13) + +inst_387:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x8001; +valaddr_reg:x3; val_offset:724*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 724*FLEN/8, x5, x9, x13) + +inst_388:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x2; +valaddr_reg:x3; val_offset:726*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 726*FLEN/8, x5, x9, x13) + +inst_389:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x83fe; +valaddr_reg:x3; val_offset:728*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 728*FLEN/8, x5, x9, x13) + +inst_390:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x3ff; +valaddr_reg:x3; val_offset:730*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 730*FLEN/8, x5, x9, x13) + +inst_391:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x83ff; +valaddr_reg:x3; val_offset:732*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 732*FLEN/8, x5, x9, x13) + +inst_392:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x400; +valaddr_reg:x3; val_offset:734*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 734*FLEN/8, x5, x9, x13) + +inst_393:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x8400; +valaddr_reg:x3; val_offset:736*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 736*FLEN/8, x5, x9, x13) + +inst_394:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x401; +valaddr_reg:x3; val_offset:738*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 738*FLEN/8, x5, x9, x13) + +inst_395:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x8455; +valaddr_reg:x3; val_offset:740*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 740*FLEN/8, x5, x9, x13) + +inst_396:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x7bff; +valaddr_reg:x3; val_offset:742*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 742*FLEN/8, x5, x9, x13) + +inst_397:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xfbff; +valaddr_reg:x3; val_offset:744*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 744*FLEN/8, x5, x9, x13) + +inst_398:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x7c00; +valaddr_reg:x3; val_offset:746*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 746*FLEN/8, x5, x9, x13) + +inst_399:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xfc00; +valaddr_reg:x3; val_offset:748*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 748*FLEN/8, x5, x9, x13) + +inst_400:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x7e00; +valaddr_reg:x3; val_offset:750*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 750*FLEN/8, x5, x9, x13) + +inst_401:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xfe00; +valaddr_reg:x3; val_offset:752*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 752*FLEN/8, x5, x9, x13) +RVTEST_SIGBASE(x9,signature_x9_3) + +inst_402:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x7e01; +valaddr_reg:x3; val_offset:754*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 754*FLEN/8, x5, x9, x13) + +inst_403:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xfe55; +valaddr_reg:x3; val_offset:756*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 756*FLEN/8, x5, x9, x13) + +inst_404:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x7c01; +valaddr_reg:x3; val_offset:758*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 758*FLEN/8, x5, x9, x13) + +inst_405:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xfd55; +valaddr_reg:x3; val_offset:760*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 760*FLEN/8, x5, x9, x13) + +inst_406:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x3c00; +valaddr_reg:x3; val_offset:762*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 762*FLEN/8, x5, x9, x13) + +inst_407:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xbc00; +valaddr_reg:x3; val_offset:764*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 764*FLEN/8, x5, x9, x13) + +inst_408:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x0; +valaddr_reg:x3; val_offset:766*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 766*FLEN/8, x5, x9, x13) + +inst_409:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x8000; +valaddr_reg:x3; val_offset:768*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 768*FLEN/8, x5, x9, x13) + +inst_410:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x1; +valaddr_reg:x3; val_offset:770*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 770*FLEN/8, x5, x9, x13) + +inst_411:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x8001; +valaddr_reg:x3; val_offset:772*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 772*FLEN/8, x5, x9, x13) + +inst_412:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x2; +valaddr_reg:x3; val_offset:774*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 774*FLEN/8, x5, x9, x13) + +inst_413:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x83fe; +valaddr_reg:x3; val_offset:776*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 776*FLEN/8, x5, x9, x13) + +inst_414:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x3ff; +valaddr_reg:x3; val_offset:778*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 778*FLEN/8, x5, x9, x13) + +inst_415:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x83ff; +valaddr_reg:x3; val_offset:780*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 780*FLEN/8, x5, x9, x13) + +inst_416:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x400; +valaddr_reg:x3; val_offset:782*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 782*FLEN/8, x5, x9, x13) + +inst_417:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x8400; +valaddr_reg:x3; val_offset:784*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 784*FLEN/8, x5, x9, x13) + +inst_418:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x401; +valaddr_reg:x3; val_offset:786*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 786*FLEN/8, x5, x9, x13) + +inst_419:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x8455; +valaddr_reg:x3; val_offset:788*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 788*FLEN/8, x5, x9, x13) + +inst_420:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x7bff; +valaddr_reg:x3; val_offset:790*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 790*FLEN/8, x5, x9, x13) + +inst_421:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xfbff; +valaddr_reg:x3; val_offset:792*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 792*FLEN/8, x5, x9, x13) + +inst_422:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x7c00; +valaddr_reg:x3; val_offset:794*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 794*FLEN/8, x5, x9, x13) + +inst_423:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xfc00; +valaddr_reg:x3; val_offset:796*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 796*FLEN/8, x5, x9, x13) + +inst_424:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x7e00; +valaddr_reg:x3; val_offset:798*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 798*FLEN/8, x5, x9, x13) + +inst_425:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xfe00; +valaddr_reg:x3; val_offset:800*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 800*FLEN/8, x5, x9, x13) + +inst_426:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x7e01; +valaddr_reg:x3; val_offset:802*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 802*FLEN/8, x5, x9, x13) + +inst_427:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xfe55; +valaddr_reg:x3; val_offset:804*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 804*FLEN/8, x5, x9, x13) + +inst_428:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x7c01; +valaddr_reg:x3; val_offset:806*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 806*FLEN/8, x5, x9, x13) + +inst_429:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xfd55; +valaddr_reg:x3; val_offset:808*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 808*FLEN/8, x5, x9, x13) + +inst_430:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x3c00; +valaddr_reg:x3; val_offset:810*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 810*FLEN/8, x5, x9, x13) + +inst_431:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xbc00; +valaddr_reg:x3; val_offset:812*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 812*FLEN/8, x5, x9, x13) + +inst_432:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x0; +valaddr_reg:x3; val_offset:814*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 814*FLEN/8, x5, x9, x13) + +inst_433:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x8000; +valaddr_reg:x3; val_offset:816*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 816*FLEN/8, x5, x9, x13) + +inst_434:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x1; +valaddr_reg:x3; val_offset:818*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 818*FLEN/8, x5, x9, x13) + +inst_435:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x8001; +valaddr_reg:x3; val_offset:820*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 820*FLEN/8, x5, x9, x13) + +inst_436:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x2; +valaddr_reg:x3; val_offset:822*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 822*FLEN/8, x5, x9, x13) + +inst_437:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x83fe; +valaddr_reg:x3; val_offset:824*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 824*FLEN/8, x5, x9, x13) + +inst_438:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x3ff; +valaddr_reg:x3; val_offset:826*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 826*FLEN/8, x5, x9, x13) + +inst_439:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x83ff; +valaddr_reg:x3; val_offset:828*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 828*FLEN/8, x5, x9, x13) + +inst_440:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x400; +valaddr_reg:x3; val_offset:830*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 830*FLEN/8, x5, x9, x13) + +inst_441:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x8400; +valaddr_reg:x3; val_offset:832*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 832*FLEN/8, x5, x9, x13) + +inst_442:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x401; +valaddr_reg:x3; val_offset:834*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 834*FLEN/8, x5, x9, x13) + +inst_443:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x8455; +valaddr_reg:x3; val_offset:836*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 836*FLEN/8, x5, x9, x13) + +inst_444:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x7bff; +valaddr_reg:x3; val_offset:838*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 838*FLEN/8, x5, x9, x13) + +inst_445:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xfbff; +valaddr_reg:x3; val_offset:840*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 840*FLEN/8, x5, x9, x13) + +inst_446:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x7c00; +valaddr_reg:x3; val_offset:842*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 842*FLEN/8, x5, x9, x13) + +inst_447:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xfc00; +valaddr_reg:x3; val_offset:844*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 844*FLEN/8, x5, x9, x13) + +inst_448:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x7e00; +valaddr_reg:x3; val_offset:846*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 846*FLEN/8, x5, x9, x13) + +inst_449:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xfe00; +valaddr_reg:x3; val_offset:848*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 848*FLEN/8, x5, x9, x13) + +inst_450:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x7e01; +valaddr_reg:x3; val_offset:850*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 850*FLEN/8, x5, x9, x13) + +inst_451:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xfe55; +valaddr_reg:x3; val_offset:852*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 852*FLEN/8, x5, x9, x13) + +inst_452:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x7c01; +valaddr_reg:x3; val_offset:854*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 854*FLEN/8, x5, x9, x13) + +inst_453:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xfd55; +valaddr_reg:x3; val_offset:856*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 856*FLEN/8, x5, x9, x13) + +inst_454:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x3c00; +valaddr_reg:x3; val_offset:858*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 858*FLEN/8, x5, x9, x13) + +inst_455:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xbc00; +valaddr_reg:x3; val_offset:860*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 860*FLEN/8, x5, x9, x13) + +inst_456:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x0; +valaddr_reg:x3; val_offset:862*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 862*FLEN/8, x5, x9, x13) + +inst_457:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x8000; +valaddr_reg:x3; val_offset:864*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 864*FLEN/8, x5, x9, x13) + +inst_458:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x1; +valaddr_reg:x3; val_offset:866*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 866*FLEN/8, x5, x9, x13) + +inst_459:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x8001; +valaddr_reg:x3; val_offset:868*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 868*FLEN/8, x5, x9, x13) + +inst_460:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x2; +valaddr_reg:x3; val_offset:870*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 870*FLEN/8, x5, x9, x13) + +inst_461:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x83fe; +valaddr_reg:x3; val_offset:872*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 872*FLEN/8, x5, x9, x13) + +inst_462:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x3ff; +valaddr_reg:x3; val_offset:874*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 874*FLEN/8, x5, x9, x13) + +inst_463:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x83ff; +valaddr_reg:x3; val_offset:876*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 876*FLEN/8, x5, x9, x13) + +inst_464:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x400; +valaddr_reg:x3; val_offset:878*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 878*FLEN/8, x5, x9, x13) + +inst_465:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x8400; +valaddr_reg:x3; val_offset:880*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 880*FLEN/8, x5, x9, x13) + +inst_466:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x401; +valaddr_reg:x3; val_offset:882*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 882*FLEN/8, x5, x9, x13) + +inst_467:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x8455; +valaddr_reg:x3; val_offset:884*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 884*FLEN/8, x5, x9, x13) + +inst_468:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x7bff; +valaddr_reg:x3; val_offset:886*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 886*FLEN/8, x5, x9, x13) + +inst_469:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xfbff; +valaddr_reg:x3; val_offset:888*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 888*FLEN/8, x5, x9, x13) + +inst_470:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x7c00; +valaddr_reg:x3; val_offset:890*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 890*FLEN/8, x5, x9, x13) + +inst_471:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xfc00; +valaddr_reg:x3; val_offset:892*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 892*FLEN/8, x5, x9, x13) + +inst_472:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x7e00; +valaddr_reg:x3; val_offset:894*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 894*FLEN/8, x5, x9, x13) + +inst_473:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xfe00; +valaddr_reg:x3; val_offset:896*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 896*FLEN/8, x5, x9, x13) + +inst_474:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x7e01; +valaddr_reg:x3; val_offset:898*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 898*FLEN/8, x5, x9, x13) + +inst_475:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xfe55; +valaddr_reg:x3; val_offset:900*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 900*FLEN/8, x5, x9, x13) + +inst_476:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x7c01; +valaddr_reg:x3; val_offset:902*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 902*FLEN/8, x5, x9, x13) + +inst_477:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xfd55; +valaddr_reg:x3; val_offset:904*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 904*FLEN/8, x5, x9, x13) + +inst_478:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x3c00; +valaddr_reg:x3; val_offset:906*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 906*FLEN/8, x5, x9, x13) + +inst_479:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xbc00; +valaddr_reg:x3; val_offset:908*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 908*FLEN/8, x5, x9, x13) + +inst_480:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x0; +valaddr_reg:x3; val_offset:910*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 910*FLEN/8, x5, x9, x13) + +inst_481:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x8000; +valaddr_reg:x3; val_offset:912*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 912*FLEN/8, x5, x9, x13) + +inst_482:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x1; +valaddr_reg:x3; val_offset:914*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 914*FLEN/8, x5, x9, x13) + +inst_483:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x8001; +valaddr_reg:x3; val_offset:916*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 916*FLEN/8, x5, x9, x13) + +inst_484:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x2; +valaddr_reg:x3; val_offset:918*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 918*FLEN/8, x5, x9, x13) + +inst_485:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x83fe; +valaddr_reg:x3; val_offset:920*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 920*FLEN/8, x5, x9, x13) + +inst_486:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x3ff; +valaddr_reg:x3; val_offset:922*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 922*FLEN/8, x5, x9, x13) + +inst_487:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x83ff; +valaddr_reg:x3; val_offset:924*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 924*FLEN/8, x5, x9, x13) + +inst_488:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x400; +valaddr_reg:x3; val_offset:926*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 926*FLEN/8, x5, x9, x13) + +inst_489:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x8400; +valaddr_reg:x3; val_offset:928*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 928*FLEN/8, x5, x9, x13) + +inst_490:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x401; +valaddr_reg:x3; val_offset:930*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 930*FLEN/8, x5, x9, x13) + +inst_491:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x8455; +valaddr_reg:x3; val_offset:932*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 932*FLEN/8, x5, x9, x13) + +inst_492:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x7bff; +valaddr_reg:x3; val_offset:934*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 934*FLEN/8, x5, x9, x13) + +inst_493:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xfbff; +valaddr_reg:x3; val_offset:936*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 936*FLEN/8, x5, x9, x13) + +inst_494:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x7c00; +valaddr_reg:x3; val_offset:938*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 938*FLEN/8, x5, x9, x13) + +inst_495:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xfc00; +valaddr_reg:x3; val_offset:940*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 940*FLEN/8, x5, x9, x13) + +inst_496:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x7e00; +valaddr_reg:x3; val_offset:942*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 942*FLEN/8, x5, x9, x13) + +inst_497:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xfe00; +valaddr_reg:x3; val_offset:944*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 944*FLEN/8, x5, x9, x13) + +inst_498:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x7e01; +valaddr_reg:x3; val_offset:946*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 946*FLEN/8, x5, x9, x13) + +inst_499:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xfe55; +valaddr_reg:x3; val_offset:948*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 948*FLEN/8, x5, x9, x13) + +inst_500:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x7c01; +valaddr_reg:x3; val_offset:950*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 950*FLEN/8, x5, x9, x13) + +inst_501:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xfd55; +valaddr_reg:x3; val_offset:952*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 952*FLEN/8, x5, x9, x13) + +inst_502:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x3c00; +valaddr_reg:x3; val_offset:954*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 954*FLEN/8, x5, x9, x13) + +inst_503:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xbc00; +valaddr_reg:x3; val_offset:956*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 956*FLEN/8, x5, x9, x13) + +inst_504:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x0; +valaddr_reg:x3; val_offset:958*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 958*FLEN/8, x5, x9, x13) + +inst_505:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x8000; +valaddr_reg:x3; val_offset:960*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 960*FLEN/8, x5, x9, x13) + +inst_506:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x1; +valaddr_reg:x3; val_offset:962*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 962*FLEN/8, x5, x9, x13) + +inst_507:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x8001; +valaddr_reg:x3; val_offset:964*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 964*FLEN/8, x5, x9, x13) + +inst_508:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x2; +valaddr_reg:x3; val_offset:966*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 966*FLEN/8, x5, x9, x13) + +inst_509:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x83fe; +valaddr_reg:x3; val_offset:968*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 968*FLEN/8, x5, x9, x13) + +inst_510:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x3ff; +valaddr_reg:x3; val_offset:970*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 970*FLEN/8, x5, x9, x13) + +inst_511:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x83ff; +valaddr_reg:x3; val_offset:972*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 972*FLEN/8, x5, x9, x13) + +inst_512:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x400; +valaddr_reg:x3; val_offset:974*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 974*FLEN/8, x5, x9, x13) + +inst_513:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x8400; +valaddr_reg:x3; val_offset:976*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 976*FLEN/8, x5, x9, x13) + +inst_514:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x401; +valaddr_reg:x3; val_offset:978*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 978*FLEN/8, x5, x9, x13) + +inst_515:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x8455; +valaddr_reg:x3; val_offset:980*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 980*FLEN/8, x5, x9, x13) + +inst_516:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x7bff; +valaddr_reg:x3; val_offset:982*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 982*FLEN/8, x5, x9, x13) + +inst_517:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xfbff; +valaddr_reg:x3; val_offset:984*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 984*FLEN/8, x5, x9, x13) + +inst_518:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x7c00; +valaddr_reg:x3; val_offset:986*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 986*FLEN/8, x5, x9, x13) + +inst_519:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xfc00; +valaddr_reg:x3; val_offset:988*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 988*FLEN/8, x5, x9, x13) + +inst_520:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x7e00; +valaddr_reg:x3; val_offset:990*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 990*FLEN/8, x5, x9, x13) + +inst_521:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xfe00; +valaddr_reg:x3; val_offset:992*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 992*FLEN/8, x5, x9, x13) + +inst_522:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x7e01; +valaddr_reg:x3; val_offset:994*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 994*FLEN/8, x5, x9, x13) + +inst_523:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xfe55; +valaddr_reg:x3; val_offset:996*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 996*FLEN/8, x5, x9, x13) + +inst_524:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x7c01; +valaddr_reg:x3; val_offset:998*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 998*FLEN/8, x5, x9, x13) + +inst_525:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xfd55; +valaddr_reg:x3; val_offset:1000*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1000*FLEN/8, x5, x9, x13) + +inst_526:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x3c00; +valaddr_reg:x3; val_offset:1002*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1002*FLEN/8, x5, x9, x13) + +inst_527:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xbc00; +valaddr_reg:x3; val_offset:1004*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1004*FLEN/8, x5, x9, x13) + +inst_528:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x0; +valaddr_reg:x3; val_offset:1006*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1006*FLEN/8, x5, x9, x13) + +inst_529:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x8000; +valaddr_reg:x3; val_offset:1008*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1008*FLEN/8, x5, x9, x13) +RVTEST_SIGBASE(x9,signature_x9_4) + +inst_530:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x1; +valaddr_reg:x3; val_offset:1010*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1010*FLEN/8, x5, x9, x13) + +inst_531:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x8001; +valaddr_reg:x3; val_offset:1012*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1012*FLEN/8, x5, x9, x13) + +inst_532:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2; +valaddr_reg:x3; val_offset:1014*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1014*FLEN/8, x5, x9, x13) + +inst_533:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x83fe; +valaddr_reg:x3; val_offset:1016*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1016*FLEN/8, x5, x9, x13) + +inst_534:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3ff; +valaddr_reg:x3; val_offset:1018*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1018*FLEN/8, x5, x9, x13) + +inst_535:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x83ff; +valaddr_reg:x3; val_offset:1020*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1020*FLEN/8, x5, x9, x13) + +inst_536:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x400; +valaddr_reg:x3; val_offset:1022*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1022*FLEN/8, x5, x9, x13) + +inst_537:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x8400; +valaddr_reg:x3; val_offset:1024*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1024*FLEN/8, x5, x9, x13) + +inst_538:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x401; +valaddr_reg:x3; val_offset:1026*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1026*FLEN/8, x5, x9, x13) + +inst_539:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x8455; +valaddr_reg:x3; val_offset:1028*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1028*FLEN/8, x5, x9, x13) + +inst_540:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7bff; +valaddr_reg:x3; val_offset:1030*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1030*FLEN/8, x5, x9, x13) + +inst_541:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xfbff; +valaddr_reg:x3; val_offset:1032*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1032*FLEN/8, x5, x9, x13) + +inst_542:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7c00; +valaddr_reg:x3; val_offset:1034*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1034*FLEN/8, x5, x9, x13) + +inst_543:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xfc00; +valaddr_reg:x3; val_offset:1036*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1036*FLEN/8, x5, x9, x13) + +inst_544:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7e00; +valaddr_reg:x3; val_offset:1038*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1038*FLEN/8, x5, x9, x13) + +inst_545:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xfe00; +valaddr_reg:x3; val_offset:1040*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1040*FLEN/8, x5, x9, x13) + +inst_546:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7e01; +valaddr_reg:x3; val_offset:1042*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1042*FLEN/8, x5, x9, x13) + +inst_547:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xfe55; +valaddr_reg:x3; val_offset:1044*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1044*FLEN/8, x5, x9, x13) + +inst_548:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7c01; +valaddr_reg:x3; val_offset:1046*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1046*FLEN/8, x5, x9, x13) + +inst_549:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xfd55; +valaddr_reg:x3; val_offset:1048*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1048*FLEN/8, x5, x9, x13) + +inst_550:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3c00; +valaddr_reg:x3; val_offset:1050*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1050*FLEN/8, x5, x9, x13) + +inst_551:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xbc00; +valaddr_reg:x3; val_offset:1052*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1052*FLEN/8, x5, x9, x13) + +inst_552:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x0; +valaddr_reg:x3; val_offset:1054*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1054*FLEN/8, x5, x9, x13) + +inst_553:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x8000; +valaddr_reg:x3; val_offset:1056*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1056*FLEN/8, x5, x9, x13) + +inst_554:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x1; +valaddr_reg:x3; val_offset:1058*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1058*FLEN/8, x5, x9, x13) + +inst_555:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x8001; +valaddr_reg:x3; val_offset:1060*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1060*FLEN/8, x5, x9, x13) + +inst_556:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x2; +valaddr_reg:x3; val_offset:1062*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1062*FLEN/8, x5, x9, x13) + +inst_557:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x83fe; +valaddr_reg:x3; val_offset:1064*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1064*FLEN/8, x5, x9, x13) + +inst_558:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x3ff; +valaddr_reg:x3; val_offset:1066*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1066*FLEN/8, x5, x9, x13) + +inst_559:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x83ff; +valaddr_reg:x3; val_offset:1068*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1068*FLEN/8, x5, x9, x13) + +inst_560:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x400; +valaddr_reg:x3; val_offset:1070*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1070*FLEN/8, x5, x9, x13) + +inst_561:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x8400; +valaddr_reg:x3; val_offset:1072*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1072*FLEN/8, x5, x9, x13) + +inst_562:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x401; +valaddr_reg:x3; val_offset:1074*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1074*FLEN/8, x5, x9, x13) + +inst_563:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x8455; +valaddr_reg:x3; val_offset:1076*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1076*FLEN/8, x5, x9, x13) + +inst_564:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x7bff; +valaddr_reg:x3; val_offset:1078*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1078*FLEN/8, x5, x9, x13) + +inst_565:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xfbff; +valaddr_reg:x3; val_offset:1080*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1080*FLEN/8, x5, x9, x13) + +inst_566:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x7c00; +valaddr_reg:x3; val_offset:1082*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1082*FLEN/8, x5, x9, x13) + +inst_567:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xfc00; +valaddr_reg:x3; val_offset:1084*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1084*FLEN/8, x5, x9, x13) + +inst_568:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x7e00; +valaddr_reg:x3; val_offset:1086*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1086*FLEN/8, x5, x9, x13) + +inst_569:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xfe00; +valaddr_reg:x3; val_offset:1088*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1088*FLEN/8, x5, x9, x13) + +inst_570:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x7e01; +valaddr_reg:x3; val_offset:1090*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1090*FLEN/8, x5, x9, x13) + +inst_571:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xfe55; +valaddr_reg:x3; val_offset:1092*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1092*FLEN/8, x5, x9, x13) + +inst_572:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x7c01; +valaddr_reg:x3; val_offset:1094*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1094*FLEN/8, x5, x9, x13) + +inst_573:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xfd55; +valaddr_reg:x3; val_offset:1096*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1096*FLEN/8, x5, x9, x13) + +inst_574:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x3c00; +valaddr_reg:x3; val_offset:1098*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1098*FLEN/8, x5, x9, x13) + +inst_575:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbc00; +valaddr_reg:x3; val_offset:1100*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1100*FLEN/8, x5, x9, x13) + +inst_576:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x8000; +valaddr_reg:x3; val_offset:1102*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1102*FLEN/8, x5, x9, x13) + +inst_577:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8001; +valaddr_reg:x3; val_offset:1104*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1104*FLEN/8, x5, x9, x13) + +inst_578:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x83fe; +valaddr_reg:x3; val_offset:1106*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1106*FLEN/8, x5, x9, x13) + +inst_579:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x83ff; +valaddr_reg:x3; val_offset:1108*FLEN/8; correctval:??; testreg:x13; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1108*FLEN/8, x5, x9, x13) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(1,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(2,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(1023,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(1024,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(1025,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31743,32,FLEN) +test_dataset_1: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31744,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32256,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32257,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31745,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(15360,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(0,32,FLEN) +test_dataset_2: +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(1023,16,FLEN) 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+NAN_BOXED(65024,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33791,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x2_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_1: + .fill 36*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x9_0: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x9_1: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x9_2: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x9_3: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x9_4: + .fill 100*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fle_b19-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fle_b19-01.S new file mode 100644 index 000000000..9f0749da4 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fle_b19-01.S @@ -0,0 +1,8688 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 05:47:34 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fle.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fle.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fle_b19 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fle_b19) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x2,test_dataset_0) +RVTEST_SIGBASE(x7,signature_x7_1) + +inst_0:// rs1 != rs2, rs1==x25, rs2==x6, rd==x15,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x25; op2:x6; dest:x15; op1val:0x739c; op2val:0x739c; +valaddr_reg:x2; val_offset:0*FLEN/8; correctval:??; testreg:x9; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x15, x25, x6, 0, 0, x2, 0*FLEN/8, x10, x7, x9) + +inst_1:// rs1 == rs2, rs1==x8, rs2==x8, rd==x21,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x100 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x8; op2:x8; dest:x21; op1val:0x739c; op2val:0x739c; +valaddr_reg:x2; val_offset:2*FLEN/8; correctval:??; testreg:x9; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x21, x8, x8, 0, 0, x2, 2*FLEN/8, x10, x7, x9) + +inst_2:// rs1==x16, rs2==x28, rd==x20,fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x16; op2:x28; dest:x20; op1val:0x7900; op2val:0x739c; +valaddr_reg:x2; val_offset:4*FLEN/8; correctval:??; testreg:x9; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x20, x16, x28, 0, 0, x2, 4*FLEN/8, x10, x7, x9) + +inst_3:// rs1==x5, rs2==x14, rd==x19,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1d and fm2 == 0x025 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x5; op2:x14; dest:x19; op1val:0x739c; op2val:0x7425; +valaddr_reg:x2; val_offset:6*FLEN/8; correctval:??; testreg:x9; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x19, x5, x14, 0, 0, x2, 6*FLEN/8, x10, x7, x9) + +inst_4:// rs1==x17, rs2==x25, rd==x5,fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x17; op2:x25; dest:x5; op1val:0x7425; op2val:0x739c; +valaddr_reg:x2; val_offset:8*FLEN/8; correctval:??; testreg:x9; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x5, x17, x25, 0, 0, x2, 8*FLEN/8, x10, x7, x9) + +inst_5:// rs1==x23, rs2==x12, rd==x22,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x23; op2:x12; dest:x22; op1val:0x739c; op2val:0x7ab0; +valaddr_reg:x2; val_offset:10*FLEN/8; correctval:??; testreg:x9; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x22, x23, x12, 0, 0, x2, 10*FLEN/8, x10, x7, x9) + +inst_6:// rs1==x6, rs2==x31, rd==x23,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x6; op2:x31; dest:x23; op1val:0x7ab0; op2val:0x739c; +valaddr_reg:x2; val_offset:12*FLEN/8; correctval:??; testreg:x9; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x23, x6, x31, 0, 0, x2, 12*FLEN/8, x10, x7, x9) + +inst_7:// rs1==x4, rs2==x5, rd==x14,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x4; op2:x5; dest:x14; op1val:0x739c; op2val:0x7913; +valaddr_reg:x2; val_offset:14*FLEN/8; correctval:??; testreg:x9; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x14, x4, x5, 0, 0, x2, 14*FLEN/8, x10, x7, x9) + +inst_8:// rs1==x11, rs2==x21, rd==x6,fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x11; op2:x21; dest:x6; op1val:0x7913; op2val:0x739c; +valaddr_reg:x2; val_offset:16*FLEN/8; correctval:??; testreg:x9; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x6, x11, x21, 0, 0, x2, 16*FLEN/8, x10, x7, x9) + +inst_9:// rs1==x18, rs2==x17, rd==x3,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 1 and fe2 == 0x1d and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x18; op2:x17; dest:x3; op1val:0x739c; op2val:0xf749; +valaddr_reg:x2; val_offset:18*FLEN/8; correctval:??; testreg:x9; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x3, x18, x17, 0, 0, x2, 18*FLEN/8, x10, x7, x9) + +inst_10:// rs1==x27, rs2==x29, rd==x25,fs1 == 1 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x27; op2:x29; dest:x25; op1val:0xf749; op2val:0x739c; +valaddr_reg:x2; val_offset:20*FLEN/8; correctval:??; testreg:x9; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x25, x27, x29, 0, 0, x2, 20*FLEN/8, x10, x7, x9) + +inst_11:// rs1==x29, rs2==x24, rd==x1,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x378 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x29; op2:x24; dest:x1; op1val:0x739c; op2val:0xfb78; +valaddr_reg:x2; val_offset:22*FLEN/8; correctval:??; testreg:x9; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x1, x29, x24, 0, 0, x2, 22*FLEN/8, x10, x7, x9) +RVTEST_VALBASEUPD(x1,test_dataset_1) + +inst_12:// rs1==x2, rs2==x16, rd==x18,fs1 == 1 and fe1 == 0x1e and fm1 == 0x378 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x2; op2:x16; dest:x18; op1val:0xfb78; op2val:0x739c; +valaddr_reg:x1; val_offset:0*FLEN/8; correctval:??; testreg:x9; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x18, x2, x16, 0, 0, x1, 0*FLEN/8, x14, x7, x9) + +inst_13:// rs1==x10, rs2==x19, rd==x12,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x21f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x10; op2:x19; dest:x12; op1val:0x739c; op2val:0xfa1f; +valaddr_reg:x1; val_offset:2*FLEN/8; correctval:??; testreg:x6; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x12, x10, x19, 0, 0, x1, 2*FLEN/8, x14, x7, x6) +RVTEST_SIGBASE(x5,signature_x5_0) + +inst_14:// rs1==x24, rs2==x7, rd==x8,fs1 == 1 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x24; op2:x7; dest:x8; op1val:0xfa1f; op2val:0x739c; +valaddr_reg:x1; val_offset:4*FLEN/8; correctval:??; testreg:x6; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x8, x24, x7, 0, 0, x1, 4*FLEN/8, x14, x5, x6) + +inst_15:// rs1==x19, rs2==x11, rd==x10,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x19; op2:x11; dest:x10; op1val:0x739c; op2val:0xf82f; +valaddr_reg:x1; val_offset:6*FLEN/8; correctval:??; testreg:x6; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x10, x19, x11, 0, 0, x1, 6*FLEN/8, x14, x5, x6) + +inst_16:// rs1==x15, rs2==x20, rd==x4,fs1 == 1 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x15; op2:x20; dest:x4; op1val:0xf82f; op2val:0x739c; +valaddr_reg:x1; val_offset:8*FLEN/8; correctval:??; testreg:x6; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x4, x15, x20, 0, 0, x1, 8*FLEN/8, x14, x5, x6) + +inst_17:// rs1==x20, rs2==x27, rd==x7,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x20; op2:x27; dest:x7; op1val:0x739c; op2val:0xf038; +valaddr_reg:x1; val_offset:10*FLEN/8; correctval:??; testreg:x6; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x7, x20, x27, 0, 0, x1, 10*FLEN/8, x14, x5, x6) + +inst_18:// rs1==x3, rs2==x9, rd==x24,fs1 == 0 and fe1 == 0x19 and fm1 == 0x216 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x3; op2:x9; dest:x24; op1val:0x6616; op2val:0xfbff; +valaddr_reg:x1; val_offset:12*FLEN/8; correctval:??; testreg:x6; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x24, x3, x9, 0, 0, x1, 12*FLEN/8, x14, x5, x6) + +inst_19:// rs1==x22, rs2==x10, rd==x16,fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x19 and fm2 == 0x216 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x22; op2:x10; dest:x16; op1val:0xfbff; op2val:0x6616; +valaddr_reg:x1; val_offset:14*FLEN/8; correctval:??; testreg:x6; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x16, x22, x10, 0, 0, x1, 14*FLEN/8, x14, x5, x6) + +inst_20:// rs1==x7, rs2==x0, rd==x2,fs1 == 0 and fe1 == 0x19 and fm1 == 0x216 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x7; op2:x0; dest:x2; op1val:0x6616; op2val:0x0; +valaddr_reg:x1; val_offset:16*FLEN/8; correctval:??; testreg:x6; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x2, x7, x0, 0, 0, x1, 16*FLEN/8, x14, x5, x6) + +inst_21:// rs1==x12, rs2==x26, rd==x11,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x19 and fm2 == 0x216 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x12; op2:x26; dest:x11; op1val:0x739c; op2val:0x6616; +valaddr_reg:x1; val_offset:18*FLEN/8; correctval:??; testreg:x6; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x11, x12, x26, 0, 0, x1, 18*FLEN/8, x14, x5, x6) + +inst_22:// rs1==x21, rs2==x23, rd==x29,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x21; op2:x23; dest:x29; op1val:0x739c; op2val:0x17b; +valaddr_reg:x1; val_offset:20*FLEN/8; correctval:??; testreg:x6; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x29, x21, x23, 0, 0, x1, 20*FLEN/8, x14, x5, x6) + +inst_23:// rs1==x31, rs2==x3, rd==x27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x105 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x184 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x31; op2:x3; dest:x27; op1val:0x105; op2val:0x7584; +valaddr_reg:x1; val_offset:22*FLEN/8; correctval:??; testreg:x6; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x27, x31, x3, 0, 0, x1, 22*FLEN/8, x14, x5, x6) + +inst_24:// rs1==x13, rs2==x15, rd==x26,fs1 == 0 and fe1 == 0x1d and fm1 == 0x184 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x105 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x13; op2:x15; dest:x26; op1val:0x7584; op2val:0x105; +valaddr_reg:x1; val_offset:24*FLEN/8; correctval:??; testreg:x6; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x26, x13, x15, 0, 0, x1, 24*FLEN/8, x14, x5, x6) +RVTEST_VALBASEUPD(x3,test_dataset_2) + +inst_25:// rs1==x9, rs2==x22, rd==x13,fs1 == 0 and fe1 == 0x00 and fm1 == 0x105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x9; op2:x22; dest:x13; op1val:0x105; op2val:0x17b; +valaddr_reg:x3; val_offset:0*FLEN/8; correctval:??; testreg:x6; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x13, x9, x22, 0, 0, x3, 0*FLEN/8, x7, x5, x6) + +inst_26:// rs1==x1, rs2==x2, rd==x28,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x105 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x1; op2:x2; dest:x28; op1val:0x739c; op2val:0x105; +valaddr_reg:x3; val_offset:2*FLEN/8; correctval:??; testreg:x6; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x28, x1, x2, 0, 0, x3, 2*FLEN/8, x7, x5, x6) + +inst_27:// rs1==x26, rs2==x18, rd==x31,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x26; op2:x18; dest:x31; op1val:0x739c; op2val:0xe; +valaddr_reg:x3; val_offset:4*FLEN/8; correctval:??; testreg:x6; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x26, x18, 0, 0, x3, 4*FLEN/8, x7, x5, x6) + +inst_28:// rs1==x30, rs2==x1, rd==x17,fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x1; dest:x17; op1val:0x2; op2val:0x7bff; +valaddr_reg:x3; val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x17, x30, x1, 0, 0, x3, 6*FLEN/8, x7, x5, x2) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_29:// rs1==x28, rs2==x30, rd==x9,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x28; op2:x30; dest:x9; op1val:0x7bff; op2val:0x2; +valaddr_reg:x3; val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x9, x28, x30, 0, 0, x3, 8*FLEN/8, x7, x1, x2) + +inst_30:// rs1==x14, rs2==x4, rd==x0,fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x14; op2:x4; dest:x0; op1val:0x2; op2val:0xe; +valaddr_reg:x3; val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x0, x14, x4, 0, 0, x3, 10*FLEN/8, x7, x1, x2) + +inst_31:// rs1==x0, rs2==x13, rd==x30,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x0; op2:x13; dest:x30; op1val:0x0; op2val:0x2; +valaddr_reg:x3; val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x30, x0, x13, 0, 0, x3, 12*FLEN/8, x7, x1, x2) + +inst_32:// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x739c; op2val:0x3fa; +valaddr_reg:x3; val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 14*FLEN/8, x7, x1, x2) + +inst_33:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x105 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x369 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x105; op2val:0x7b69; +valaddr_reg:x3; val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 16*FLEN/8, x7, x1, x2) + +inst_34:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x369 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x105 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b69; op2val:0x105; +valaddr_reg:x3; val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 18*FLEN/8, x7, x1, x2) + +inst_35:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x105; op2val:0x3fa; +valaddr_reg:x3; val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 20*FLEN/8, x7, x1, x2) + +inst_36:// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x739c; op2val:0x28e; +valaddr_reg:x3; val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 22*FLEN/8, x7, x1, x2) + +inst_37:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x105 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0c2 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x105; op2val:0x78c2; +valaddr_reg:x3; val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 24*FLEN/8, x7, x1, x2) + +inst_38:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x105 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x78c2; op2val:0x105; +valaddr_reg:x3; val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 26*FLEN/8, x7, x1, x2) + +inst_39:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x105; op2val:0x28e; +valaddr_reg:x3; val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 28*FLEN/8, x7, x1, x2) + +inst_40:// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x739c; op2val:0x217; +valaddr_reg:x3; val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 30*FLEN/8, x7, x1, x2) + +inst_41:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x105 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3cb and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x105; op2val:0x77cb; +valaddr_reg:x3; val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 32*FLEN/8, x7, x1, x2) + +inst_42:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3cb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x105 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x77cb; op2val:0x105; +valaddr_reg:x3; val_offset:34*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 34*FLEN/8, x7, x1, x2) + +inst_43:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x105; op2val:0x217; +valaddr_reg:x3; val_offset:36*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 36*FLEN/8, x7, x1, x2) + +inst_44:// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x195 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x739c; op2val:0x8195; +valaddr_reg:x3; val_offset:38*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 38*FLEN/8, x7, x1, x2) + +inst_45:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x105 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x1e7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x105; op2val:0xf5e7; +valaddr_reg:x3; val_offset:40*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 40*FLEN/8, x7, x1, x2) + +inst_46:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x1e7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x105 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf5e7; op2val:0x105; +valaddr_reg:x3; val_offset:42*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 42*FLEN/8, x7, x1, x2) + +inst_47:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x105 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x195 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x105; op2val:0x8195; +valaddr_reg:x3; val_offset:44*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 44*FLEN/8, x7, x1, x2) + +inst_48:// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x739c; op2val:0x80a7; +valaddr_reg:x3; val_offset:46*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 46*FLEN/8, x7, x1, x2) + +inst_49:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x01a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x1a; op2val:0xfbff; +valaddr_reg:x3; val_offset:48*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 48*FLEN/8, x7, x1, x2) + +inst_50:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x01a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x1a; +valaddr_reg:x3; val_offset:50*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 50*FLEN/8, x7, x1, x2) + +inst_51:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x01a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x1a; op2val:0x80a7; +valaddr_reg:x3; val_offset:52*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 52*FLEN/8, x7, x1, x2) + +inst_52:// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x01a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x739c; op2val:0x1a; +valaddr_reg:x3; val_offset:54*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 54*FLEN/8, x7, x1, x2) + +inst_53:// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x739c; op2val:0x821e; +valaddr_reg:x3; val_offset:56*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 56*FLEN/8, x7, x1, x2) + +inst_54:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x105 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3e4 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x105; op2val:0xf7e4; +valaddr_reg:x3; val_offset:58*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 58*FLEN/8, x7, x1, x2) + +inst_55:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x3e4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x105 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf7e4; op2val:0x105; +valaddr_reg:x3; val_offset:60*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 60*FLEN/8, x7, x1, x2) + +inst_56:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x105 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x105; op2val:0x821e; +valaddr_reg:x3; val_offset:62*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 62*FLEN/8, x7, x1, x2) + +inst_57:// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x739c; op2val:0x8365; +valaddr_reg:x3; val_offset:64*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 64*FLEN/8, x7, x1, x2) + +inst_58:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x105 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x252 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x105; op2val:0xfa52; +valaddr_reg:x3; val_offset:66*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 66*FLEN/8, x7, x1, x2) + +inst_59:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x252 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x105 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa52; op2val:0x105; +valaddr_reg:x3; val_offset:68*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 68*FLEN/8, x7, x1, x2) + +inst_60:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x105 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x105; op2val:0x8365; +valaddr_reg:x3; val_offset:70*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 70*FLEN/8, x7, x1, x2) + +inst_61:// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x109 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x739c; op2val:0x8109; +valaddr_reg:x3; val_offset:72*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 72*FLEN/8, x7, x1, x2) + +inst_62:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x105 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3b9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x105; op2val:0xf3b9; +valaddr_reg:x3; val_offset:74*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 74*FLEN/8, x7, x1, x2) + +inst_63:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x105 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3b9; op2val:0x105; +valaddr_reg:x3; val_offset:76*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 76*FLEN/8, x7, x1, x2) + +inst_64:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x105 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x109 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x105; op2val:0x8109; +valaddr_reg:x3; val_offset:78*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 78*FLEN/8, x7, x1, x2) + +inst_65:// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x739c; op2val:0xf0; +valaddr_reg:x3; val_offset:80*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 80*FLEN/8, x7, x1, x2) + +inst_66:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x23c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3e3c; op2val:0xf0; +valaddr_reg:x3; val_offset:82*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 82*FLEN/8, x7, x1, x2) + +inst_67:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x23c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x3e3c; +valaddr_reg:x3; val_offset:84*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 84*FLEN/8, x7, x1, x2) + +inst_68:// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x23c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x739c; op2val:0x3e3c; +valaddr_reg:x3; val_offset:86*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 86*FLEN/8, x7, x1, x2) + +inst_69:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x100 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7900; op2val:0x7900; +valaddr_reg:x3; val_offset:88*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 88*FLEN/8, x7, x1, x2) + +inst_70:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x025 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7900; op2val:0x7425; +valaddr_reg:x3; val_offset:90*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 90*FLEN/8, x7, x1, x2) + +inst_71:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x100 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7425; op2val:0x7900; +valaddr_reg:x3; val_offset:92*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 92*FLEN/8, x7, x1, x2) + +inst_72:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7900; op2val:0x7ab0; +valaddr_reg:x3; val_offset:94*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 94*FLEN/8, x7, x1, x2) + +inst_73:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x100 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab0; op2val:0x7900; +valaddr_reg:x3; val_offset:96*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 96*FLEN/8, x7, x1, x2) + +inst_74:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7900; op2val:0x7913; +valaddr_reg:x3; val_offset:98*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 98*FLEN/8, x7, x1, x2) + +inst_75:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x100 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0x7900; +valaddr_reg:x3; val_offset:100*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 100*FLEN/8, x7, x1, x2) + +inst_76:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7900; op2val:0xf749; +valaddr_reg:x3; val_offset:102*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 102*FLEN/8, x7, x1, x2) + +inst_77:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x100 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf749; op2val:0x7900; +valaddr_reg:x3; val_offset:104*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 104*FLEN/8, x7, x1, x2) + +inst_78:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x378 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7900; op2val:0xfb78; +valaddr_reg:x3; val_offset:106*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 106*FLEN/8, x7, x1, x2) + +inst_79:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x378 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x100 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb78; op2val:0x7900; +valaddr_reg:x3; val_offset:108*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 108*FLEN/8, x7, x1, x2) + +inst_80:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x21f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7900; op2val:0xfa1f; +valaddr_reg:x3; val_offset:110*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 110*FLEN/8, x7, x1, x2) + +inst_81:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x100 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa1f; op2val:0x7900; +valaddr_reg:x3; val_offset:112*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 112*FLEN/8, x7, x1, x2) + +inst_82:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7900; op2val:0xf82f; +valaddr_reg:x3; val_offset:114*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 114*FLEN/8, x7, x1, x2) + +inst_83:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x100 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82f; op2val:0x7900; +valaddr_reg:x3; val_offset:116*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 116*FLEN/8, x7, x1, x2) + +inst_84:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7900; op2val:0xf038; +valaddr_reg:x3; val_offset:118*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 118*FLEN/8, x7, x1, x2) + +inst_85:// fs1 == 0 and fe1 == 0x1b and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c00; op2val:0xfbff; +valaddr_reg:x3; val_offset:120*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 120*FLEN/8, x7, x1, x2) + +inst_86:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1b and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x6c00; +valaddr_reg:x3; val_offset:122*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 122*FLEN/8, x7, x1, x2) + +inst_87:// fs1 == 0 and fe1 == 0x1b and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c00; op2val:0xf038; +valaddr_reg:x3; val_offset:124*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 124*FLEN/8, x7, x1, x2) + +inst_88:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7900; op2val:0x6c00; +valaddr_reg:x3; val_offset:126*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 126*FLEN/8, x7, x1, x2) + +inst_89:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7900; op2val:0x17b; +valaddr_reg:x3; val_offset:128*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 128*FLEN/8, x7, x1, x2) + +inst_90:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2af and fs2 == 0 and fe2 == 0x1d and fm2 == 0x184 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x2af; op2val:0x7584; +valaddr_reg:x3; val_offset:130*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 130*FLEN/8, x7, x1, x2) + +inst_91:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x184 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2af and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7584; op2val:0x2af; +valaddr_reg:x3; val_offset:132*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 132*FLEN/8, x7, x1, x2) + +inst_92:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2af and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x2af; op2val:0x17b; +valaddr_reg:x3; val_offset:134*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 134*FLEN/8, x7, x1, x2) + +inst_93:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2af and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7900; op2val:0x2af; +valaddr_reg:x3; val_offset:136*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 136*FLEN/8, x7, x1, x2) + +inst_94:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7900; op2val:0xe; +valaddr_reg:x3; val_offset:138*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 138*FLEN/8, x7, x1, x2) + +inst_95:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x006 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x6; op2val:0x7bff; +valaddr_reg:x3; val_offset:140*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 140*FLEN/8, x7, x1, x2) + +inst_96:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x006 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6; +valaddr_reg:x3; val_offset:142*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 142*FLEN/8, x7, x1, x2) + +inst_97:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x006 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x6; op2val:0xe; +valaddr_reg:x3; val_offset:144*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 144*FLEN/8, x7, x1, x2) + +inst_98:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x006 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7900; op2val:0x6; +valaddr_reg:x3; val_offset:146*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 146*FLEN/8, x7, x1, x2) + +inst_99:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7900; op2val:0x3fa; +valaddr_reg:x3; val_offset:148*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 148*FLEN/8, x7, x1, x2) + +inst_100:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2af and fs2 == 0 and fe2 == 0x1e and fm2 == 0x369 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x2af; op2val:0x7b69; +valaddr_reg:x3; val_offset:150*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 150*FLEN/8, x7, x1, x2) + +inst_101:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x369 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2af and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b69; op2val:0x2af; +valaddr_reg:x3; val_offset:152*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 152*FLEN/8, x7, x1, x2) + +inst_102:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2af and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x2af; op2val:0x3fa; +valaddr_reg:x3; val_offset:154*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 154*FLEN/8, x7, x1, x2) + +inst_103:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7900; op2val:0x28e; +valaddr_reg:x3; val_offset:156*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 156*FLEN/8, x7, x1, x2) + +inst_104:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2af and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0c2 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x2af; op2val:0x78c2; +valaddr_reg:x3; val_offset:158*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 158*FLEN/8, x7, x1, x2) + +inst_105:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2af and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x78c2; op2val:0x2af; +valaddr_reg:x3; val_offset:160*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 160*FLEN/8, x7, x1, x2) + +inst_106:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2af and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x2af; op2val:0x28e; +valaddr_reg:x3; val_offset:162*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 162*FLEN/8, x7, x1, x2) + +inst_107:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7900; op2val:0x217; +valaddr_reg:x3; val_offset:164*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 164*FLEN/8, x7, x1, x2) + +inst_108:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2af and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3cb and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x2af; op2val:0x77cb; +valaddr_reg:x3; val_offset:166*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 166*FLEN/8, x7, x1, x2) + +inst_109:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3cb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2af and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x77cb; op2val:0x2af; +valaddr_reg:x3; val_offset:168*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 168*FLEN/8, x7, x1, x2) + +inst_110:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2af and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x2af; op2val:0x217; +valaddr_reg:x3; val_offset:170*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 170*FLEN/8, x7, x1, x2) + +inst_111:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x195 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7900; op2val:0x8195; +valaddr_reg:x3; val_offset:172*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 172*FLEN/8, x7, x1, x2) + +inst_112:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2af and fs2 == 1 and fe2 == 0x1d and fm2 == 0x1e7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x2af; op2val:0xf5e7; +valaddr_reg:x3; val_offset:174*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 174*FLEN/8, x7, x1, x2) + +inst_113:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x1e7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2af and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf5e7; op2val:0x2af; +valaddr_reg:x3; val_offset:176*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 176*FLEN/8, x7, x1, x2) + +inst_114:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2af and fs2 == 1 and fe2 == 0x00 and fm2 == 0x195 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x2af; op2val:0x8195; +valaddr_reg:x3; val_offset:178*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 178*FLEN/8, x7, x1, x2) + +inst_115:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7900; op2val:0x80a7; +valaddr_reg:x3; val_offset:180*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 180*FLEN/8, x7, x1, x2) + +inst_116:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x044 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x44; op2val:0xfbff; +valaddr_reg:x3; val_offset:182*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 182*FLEN/8, x7, x1, x2) + +inst_117:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x044 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x44; +valaddr_reg:x3; val_offset:184*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 184*FLEN/8, x7, x1, x2) + +inst_118:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x044 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x44; op2val:0x80a7; +valaddr_reg:x3; val_offset:186*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 186*FLEN/8, x7, x1, x2) + +inst_119:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x044 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7900; op2val:0x44; +valaddr_reg:x3; val_offset:188*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 188*FLEN/8, x7, x1, x2) + +inst_120:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7900; op2val:0x821e; +valaddr_reg:x3; val_offset:190*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 190*FLEN/8, x7, x1, x2) + +inst_121:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2af and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3e4 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x2af; op2val:0xf7e4; +valaddr_reg:x3; val_offset:192*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 192*FLEN/8, x7, x1, x2) + +inst_122:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x3e4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2af and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf7e4; op2val:0x2af; +valaddr_reg:x3; val_offset:194*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 194*FLEN/8, x7, x1, x2) + +inst_123:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2af and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x2af; op2val:0x821e; +valaddr_reg:x3; val_offset:196*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 196*FLEN/8, x7, x1, x2) + +inst_124:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7900; op2val:0x8365; +valaddr_reg:x3; val_offset:198*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 198*FLEN/8, x7, x1, x2) + +inst_125:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2af and fs2 == 1 and fe2 == 0x1e and fm2 == 0x252 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x2af; op2val:0xfa52; +valaddr_reg:x3; val_offset:200*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 200*FLEN/8, x7, x1, x2) + +inst_126:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x252 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2af and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa52; op2val:0x2af; +valaddr_reg:x3; val_offset:202*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 202*FLEN/8, x7, x1, x2) + +inst_127:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2af and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x2af; op2val:0x8365; +valaddr_reg:x3; val_offset:204*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 204*FLEN/8, x7, x1, x2) + +inst_128:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x109 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7900; op2val:0x8109; +valaddr_reg:x3; val_offset:206*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 206*FLEN/8, x7, x1, x2) + +inst_129:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2af and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3b9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x2af; op2val:0xf3b9; +valaddr_reg:x3; val_offset:208*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 208*FLEN/8, x7, x1, x2) + +inst_130:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2af and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3b9; op2val:0x2af; +valaddr_reg:x3; val_offset:210*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 210*FLEN/8, x7, x1, x2) + +inst_131:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2af and fs2 == 1 and fe2 == 0x00 and fm2 == 0x109 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x2af; op2val:0x8109; +valaddr_reg:x3; val_offset:212*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 212*FLEN/8, x7, x1, x2) + +inst_132:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7900; op2val:0xf0; +valaddr_reg:x3; val_offset:214*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 214*FLEN/8, x7, x1, x2) + +inst_133:// fs1 == 0 and fe1 == 0x11 and fm1 == 0x019 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x4419; op2val:0xf0; +valaddr_reg:x3; val_offset:216*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 216*FLEN/8, x7, x1, x2) + +inst_134:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x019 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x4419; +valaddr_reg:x3; val_offset:218*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 218*FLEN/8, x7, x1, x2) + +inst_135:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x019 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7900; op2val:0x4419; +valaddr_reg:x3; val_offset:220*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 220*FLEN/8, x7, x1, x2) + +inst_136:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x025 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7425; op2val:0x7425; +valaddr_reg:x3; val_offset:222*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 222*FLEN/8, x7, x1, x2) + +inst_137:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7425; op2val:0x7ab0; +valaddr_reg:x3; val_offset:224*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 224*FLEN/8, x7, x1, x2) + +inst_138:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x025 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab0; op2val:0x7425; +valaddr_reg:x3; val_offset:226*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 226*FLEN/8, x7, x1, x2) + +inst_139:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7425; op2val:0x7913; +valaddr_reg:x3; val_offset:228*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 228*FLEN/8, x7, x1, x2) + +inst_140:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x025 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0x7425; +valaddr_reg:x3; val_offset:230*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 230*FLEN/8, x7, x1, x2) + +inst_141:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7425; op2val:0xf749; +valaddr_reg:x3; val_offset:232*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 232*FLEN/8, x7, x1, x2) + +inst_142:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x025 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf749; op2val:0x7425; +valaddr_reg:x3; val_offset:234*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 234*FLEN/8, x7, x1, x2) + +inst_143:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x378 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7425; op2val:0xfb78; +valaddr_reg:x3; val_offset:236*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 236*FLEN/8, x7, x1, x2) + +inst_144:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x378 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x025 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb78; op2val:0x7425; +valaddr_reg:x3; val_offset:238*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 238*FLEN/8, x7, x1, x2) + +inst_145:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x21f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7425; op2val:0xfa1f; +valaddr_reg:x3; val_offset:240*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 240*FLEN/8, x7, x1, x2) + +inst_146:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 0 and fe2 == 0x1d and fm2 == 0x025 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa1f; op2val:0x7425; +valaddr_reg:x3; val_offset:242*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 242*FLEN/8, x7, x1, x2) + +inst_147:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7425; op2val:0xf82f; +valaddr_reg:x3; val_offset:244*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 244*FLEN/8, x7, x1, x2) + +inst_148:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 0 and fe2 == 0x1d and fm2 == 0x025 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82f; op2val:0x7425; +valaddr_reg:x3; val_offset:246*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 246*FLEN/8, x7, x1, x2) + +inst_149:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7425; op2val:0xf038; +valaddr_reg:x3; val_offset:248*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 248*FLEN/8, x7, x1, x2) + +inst_150:// fs1 == 0 and fe1 == 0x19 and fm1 == 0x2a2 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x66a2; op2val:0xfbff; +valaddr_reg:x3; val_offset:250*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 250*FLEN/8, x7, x1, x2) + +inst_151:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x19 and fm2 == 0x2a2 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x66a2; +valaddr_reg:x3; val_offset:252*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 252*FLEN/8, x7, x1, x2) + +inst_152:// fs1 == 0 and fe1 == 0x19 and fm1 == 0x2a2 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x66a2; op2val:0xf038; +valaddr_reg:x3; val_offset:254*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 254*FLEN/8, x7, x1, x2) + +inst_153:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x2a2 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7425; op2val:0x66a2; +valaddr_reg:x3; val_offset:256*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 256*FLEN/8, x7, x1, x2) + +inst_154:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7425; op2val:0x17b; +valaddr_reg:x3; val_offset:258*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 258*FLEN/8, x7, x1, x2) + +inst_155:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11d and fs2 == 0 and fe2 == 0x1d and fm2 == 0x184 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x11d; op2val:0x7584; +valaddr_reg:x3; val_offset:260*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 260*FLEN/8, x7, x1, x2) + +inst_156:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x184 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x11d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7584; op2val:0x11d; +valaddr_reg:x3; val_offset:262*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 262*FLEN/8, x7, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_157:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x11d; op2val:0x17b; +valaddr_reg:x3; val_offset:264*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 264*FLEN/8, x7, x1, x2) + +inst_158:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x11d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7425; op2val:0x11d; +valaddr_reg:x3; val_offset:266*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 266*FLEN/8, x7, x1, x2) + +inst_159:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7425; op2val:0xe; +valaddr_reg:x3; val_offset:268*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 268*FLEN/8, x7, x1, x2) + +inst_160:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7425; op2val:0x2; +valaddr_reg:x3; val_offset:270*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 270*FLEN/8, x7, x1, x2) + +inst_161:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7425; op2val:0x3fa; +valaddr_reg:x3; val_offset:272*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 272*FLEN/8, x7, x1, x2) + +inst_162:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x369 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x11d; op2val:0x7b69; +valaddr_reg:x3; val_offset:274*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 274*FLEN/8, x7, x1, x2) + +inst_163:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x369 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x11d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b69; op2val:0x11d; +valaddr_reg:x3; val_offset:276*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 276*FLEN/8, x7, x1, x2) + +inst_164:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x11d; op2val:0x3fa; +valaddr_reg:x3; val_offset:278*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 278*FLEN/8, x7, x1, x2) + +inst_165:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7425; op2val:0x28e; +valaddr_reg:x3; val_offset:280*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 280*FLEN/8, x7, x1, x2) + +inst_166:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0c2 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x11d; op2val:0x78c2; +valaddr_reg:x3; val_offset:282*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 282*FLEN/8, x7, x1, x2) + +inst_167:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x11d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x78c2; op2val:0x11d; +valaddr_reg:x3; val_offset:284*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 284*FLEN/8, x7, x1, x2) + +inst_168:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x11d; op2val:0x28e; +valaddr_reg:x3; val_offset:286*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 286*FLEN/8, x7, x1, x2) + +inst_169:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7425; op2val:0x217; +valaddr_reg:x3; val_offset:288*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 288*FLEN/8, x7, x1, x2) + +inst_170:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11d and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3cb and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x11d; op2val:0x77cb; +valaddr_reg:x3; val_offset:290*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 290*FLEN/8, x7, x1, x2) + +inst_171:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3cb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x11d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x77cb; op2val:0x11d; +valaddr_reg:x3; val_offset:292*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 292*FLEN/8, x7, x1, x2) + +inst_172:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x11d; op2val:0x217; +valaddr_reg:x3; val_offset:294*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 294*FLEN/8, x7, x1, x2) + +inst_173:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x195 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7425; op2val:0x8195; +valaddr_reg:x3; val_offset:296*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 296*FLEN/8, x7, x1, x2) + +inst_174:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11d and fs2 == 1 and fe2 == 0x1d and fm2 == 0x1e7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x11d; op2val:0xf5e7; +valaddr_reg:x3; val_offset:298*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 298*FLEN/8, x7, x1, x2) + +inst_175:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x1e7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x11d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf5e7; op2val:0x11d; +valaddr_reg:x3; val_offset:300*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 300*FLEN/8, x7, x1, x2) + +inst_176:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x195 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x11d; op2val:0x8195; +valaddr_reg:x3; val_offset:302*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 302*FLEN/8, x7, x1, x2) + +inst_177:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7425; op2val:0x80a7; +valaddr_reg:x3; val_offset:304*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 304*FLEN/8, x7, x1, x2) + +inst_178:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x01c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x1c; op2val:0xfbff; +valaddr_reg:x3; val_offset:306*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 306*FLEN/8, x7, x1, x2) + +inst_179:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x01c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x1c; +valaddr_reg:x3; val_offset:308*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 308*FLEN/8, x7, x1, x2) + +inst_180:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x01c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x1c; op2val:0x80a7; +valaddr_reg:x3; val_offset:310*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 310*FLEN/8, x7, x1, x2) + +inst_181:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x01c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7425; op2val:0x1c; +valaddr_reg:x3; val_offset:312*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 312*FLEN/8, x7, x1, x2) + +inst_182:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7425; op2val:0x821e; +valaddr_reg:x3; val_offset:314*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 314*FLEN/8, x7, x1, x2) + +inst_183:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11d and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3e4 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x11d; op2val:0xf7e4; +valaddr_reg:x3; val_offset:316*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 316*FLEN/8, x7, x1, x2) + +inst_184:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x3e4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x11d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf7e4; op2val:0x11d; +valaddr_reg:x3; val_offset:318*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 318*FLEN/8, x7, x1, x2) + +inst_185:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x11d; op2val:0x821e; +valaddr_reg:x3; val_offset:320*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 320*FLEN/8, x7, x1, x2) + +inst_186:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7425; op2val:0x8365; +valaddr_reg:x3; val_offset:322*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 322*FLEN/8, x7, x1, x2) + +inst_187:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x252 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x11d; op2val:0xfa52; +valaddr_reg:x3; val_offset:324*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 324*FLEN/8, x7, x1, x2) + +inst_188:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x252 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x11d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa52; op2val:0x11d; +valaddr_reg:x3; val_offset:326*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 326*FLEN/8, x7, x1, x2) + +inst_189:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x11d; op2val:0x8365; +valaddr_reg:x3; val_offset:328*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 328*FLEN/8, x7, x1, x2) + +inst_190:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x109 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7425; op2val:0x8109; +valaddr_reg:x3; val_offset:330*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 330*FLEN/8, x7, x1, x2) + +inst_191:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11d and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3b9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x11d; op2val:0xf3b9; +valaddr_reg:x3; val_offset:332*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 332*FLEN/8, x7, x1, x2) + +inst_192:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x11d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3b9; op2val:0x11d; +valaddr_reg:x3; val_offset:334*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 334*FLEN/8, x7, x1, x2) + +inst_193:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x109 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x11d; op2val:0x8109; +valaddr_reg:x3; val_offset:336*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 336*FLEN/8, x7, x1, x2) + +inst_194:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7425; op2val:0xf0; +valaddr_reg:x3; val_offset:338*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 338*FLEN/8, x7, x1, x2) + +inst_195:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x2cb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ecb; op2val:0xf0; +valaddr_reg:x3; val_offset:340*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 340*FLEN/8, x7, x1, x2) + +inst_196:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2cb and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x3ecb; +valaddr_reg:x3; val_offset:342*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 342*FLEN/8, x7, x1, x2) + +inst_197:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2cb and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7425; op2val:0x3ecb; +valaddr_reg:x3; val_offset:344*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 344*FLEN/8, x7, x1, x2) + +inst_198:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab0; op2val:0x7ab0; +valaddr_reg:x3; val_offset:346*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 346*FLEN/8, x7, x1, x2) + +inst_199:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab0; op2val:0x7913; +valaddr_reg:x3; val_offset:348*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 348*FLEN/8, x7, x1, x2) + +inst_200:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0x7ab0; +valaddr_reg:x3; val_offset:350*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 350*FLEN/8, x7, x1, x2) + +inst_201:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab0; op2val:0xf749; +valaddr_reg:x3; val_offset:352*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 352*FLEN/8, x7, x1, x2) + +inst_202:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf749; op2val:0x7ab0; +valaddr_reg:x3; val_offset:354*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 354*FLEN/8, x7, x1, x2) + +inst_203:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x378 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab0; op2val:0xfb78; +valaddr_reg:x3; val_offset:356*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 356*FLEN/8, x7, x1, x2) + +inst_204:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x378 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb78; op2val:0x7ab0; +valaddr_reg:x3; val_offset:358*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 358*FLEN/8, x7, x1, x2) + +inst_205:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x21f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab0; op2val:0xfa1f; +valaddr_reg:x3; val_offset:360*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 360*FLEN/8, x7, x1, x2) + +inst_206:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa1f; op2val:0x7ab0; +valaddr_reg:x3; val_offset:362*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 362*FLEN/8, x7, x1, x2) + +inst_207:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab0; op2val:0xf82f; +valaddr_reg:x3; val_offset:364*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 364*FLEN/8, x7, x1, x2) + +inst_208:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82f; op2val:0x7ab0; +valaddr_reg:x3; val_offset:366*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 366*FLEN/8, x7, x1, x2) + +inst_209:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab0; op2val:0xf038; +valaddr_reg:x3; val_offset:368*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 368*FLEN/8, x7, x1, x2) + +inst_210:// fs1 == 0 and fe1 == 0x1b and fm1 == 0x159 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d59; op2val:0xfbff; +valaddr_reg:x3; val_offset:370*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 370*FLEN/8, x7, x1, x2) + +inst_211:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1b and fm2 == 0x159 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x6d59; +valaddr_reg:x3; val_offset:372*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 372*FLEN/8, x7, x1, x2) + +inst_212:// fs1 == 0 and fe1 == 0x1b and fm1 == 0x159 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d59; op2val:0xf038; +valaddr_reg:x3; val_offset:374*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 374*FLEN/8, x7, x1, x2) + +inst_213:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x159 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab0; op2val:0x6d59; +valaddr_reg:x3; val_offset:376*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 376*FLEN/8, x7, x1, x2) + +inst_214:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab0; op2val:0x17b; +valaddr_reg:x3; val_offset:378*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 378*FLEN/8, x7, x1, x2) + +inst_215:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x397 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x184 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x397; op2val:0x7584; +valaddr_reg:x3; val_offset:380*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 380*FLEN/8, x7, x1, x2) + +inst_216:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x184 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x397 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7584; op2val:0x397; +valaddr_reg:x3; val_offset:382*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 382*FLEN/8, x7, x1, x2) + +inst_217:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x397 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x397; op2val:0x17b; +valaddr_reg:x3; val_offset:384*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 384*FLEN/8, x7, x1, x2) + +inst_218:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x397 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab0; op2val:0x397; +valaddr_reg:x3; val_offset:386*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 386*FLEN/8, x7, x1, x2) + +inst_219:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab0; op2val:0xe; +valaddr_reg:x3; val_offset:388*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 388*FLEN/8, x7, x1, x2) + +inst_220:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x009 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x9; op2val:0x7bff; +valaddr_reg:x3; val_offset:390*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 390*FLEN/8, x7, x1, x2) + +inst_221:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x009 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x9; +valaddr_reg:x3; val_offset:392*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 392*FLEN/8, x7, x1, x2) + +inst_222:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x009 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x9; op2val:0xe; +valaddr_reg:x3; val_offset:394*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 394*FLEN/8, x7, x1, x2) + +inst_223:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x009 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab0; op2val:0x9; +valaddr_reg:x3; val_offset:396*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 396*FLEN/8, x7, x1, x2) + +inst_224:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab0; op2val:0x3fa; +valaddr_reg:x3; val_offset:398*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 398*FLEN/8, x7, x1, x2) + +inst_225:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x397 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x369 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x397; op2val:0x7b69; +valaddr_reg:x3; val_offset:400*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 400*FLEN/8, x7, x1, x2) + +inst_226:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x369 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x397 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b69; op2val:0x397; +valaddr_reg:x3; val_offset:402*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 402*FLEN/8, x7, x1, x2) + +inst_227:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x397 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x397; op2val:0x3fa; +valaddr_reg:x3; val_offset:404*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 404*FLEN/8, x7, x1, x2) + +inst_228:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab0; op2val:0x28e; +valaddr_reg:x3; val_offset:406*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 406*FLEN/8, x7, x1, x2) + +inst_229:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x397 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0c2 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x397; op2val:0x78c2; +valaddr_reg:x3; val_offset:408*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 408*FLEN/8, x7, x1, x2) + +inst_230:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x397 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x78c2; op2val:0x397; +valaddr_reg:x3; val_offset:410*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 410*FLEN/8, x7, x1, x2) + +inst_231:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x397 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x397; op2val:0x28e; +valaddr_reg:x3; val_offset:412*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 412*FLEN/8, x7, x1, x2) + +inst_232:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab0; op2val:0x217; +valaddr_reg:x3; val_offset:414*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 414*FLEN/8, x7, x1, x2) + +inst_233:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x397 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3cb and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x397; op2val:0x77cb; +valaddr_reg:x3; val_offset:416*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 416*FLEN/8, x7, x1, x2) + +inst_234:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3cb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x397 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x77cb; op2val:0x397; +valaddr_reg:x3; val_offset:418*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 418*FLEN/8, x7, x1, x2) + +inst_235:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x397 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x397; op2val:0x217; +valaddr_reg:x3; val_offset:420*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 420*FLEN/8, x7, x1, x2) + +inst_236:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x195 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab0; op2val:0x8195; +valaddr_reg:x3; val_offset:422*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 422*FLEN/8, x7, x1, x2) + +inst_237:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x397 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x1e7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x397; op2val:0xf5e7; +valaddr_reg:x3; val_offset:424*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 424*FLEN/8, x7, x1, x2) + +inst_238:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x1e7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x397 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf5e7; op2val:0x397; +valaddr_reg:x3; val_offset:426*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 426*FLEN/8, x7, x1, x2) + +inst_239:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x397 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x195 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x397; op2val:0x8195; +valaddr_reg:x3; val_offset:428*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 428*FLEN/8, x7, x1, x2) + +inst_240:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab0; op2val:0x80a7; +valaddr_reg:x3; val_offset:430*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 430*FLEN/8, x7, x1, x2) + +inst_241:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x05b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x5b; op2val:0xfbff; +valaddr_reg:x3; val_offset:432*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 432*FLEN/8, x7, x1, x2) + +inst_242:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x05b and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x5b; +valaddr_reg:x3; val_offset:434*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 434*FLEN/8, x7, x1, x2) + +inst_243:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x05b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x5b; op2val:0x80a7; +valaddr_reg:x3; val_offset:436*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 436*FLEN/8, x7, x1, x2) + +inst_244:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x05b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab0; op2val:0x5b; +valaddr_reg:x3; val_offset:438*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 438*FLEN/8, x7, x1, x2) + +inst_245:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab0; op2val:0x821e; +valaddr_reg:x3; val_offset:440*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 440*FLEN/8, x7, x1, x2) + +inst_246:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x397 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3e4 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x397; op2val:0xf7e4; +valaddr_reg:x3; val_offset:442*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 442*FLEN/8, x7, x1, x2) + +inst_247:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x3e4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x397 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf7e4; op2val:0x397; +valaddr_reg:x3; val_offset:444*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 444*FLEN/8, x7, x1, x2) + +inst_248:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x397 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x397; op2val:0x821e; +valaddr_reg:x3; val_offset:446*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 446*FLEN/8, x7, x1, x2) + +inst_249:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab0; op2val:0x8365; +valaddr_reg:x3; val_offset:448*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 448*FLEN/8, x7, x1, x2) + +inst_250:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x397 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x252 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x397; op2val:0xfa52; +valaddr_reg:x3; val_offset:450*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 450*FLEN/8, x7, x1, x2) + +inst_251:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x252 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x397 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa52; op2val:0x397; +valaddr_reg:x3; val_offset:452*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 452*FLEN/8, x7, x1, x2) + +inst_252:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x397 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x397; op2val:0x8365; +valaddr_reg:x3; val_offset:454*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 454*FLEN/8, x7, x1, x2) + +inst_253:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x109 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab0; op2val:0x8109; +valaddr_reg:x3; val_offset:456*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 456*FLEN/8, x7, x1, x2) + +inst_254:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x397 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3b9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x397; op2val:0xf3b9; +valaddr_reg:x3; val_offset:458*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 458*FLEN/8, x7, x1, x2) + +inst_255:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x397 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3b9; op2val:0x397; +valaddr_reg:x3; val_offset:460*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 460*FLEN/8, x7, x1, x2) + +inst_256:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x397 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x109 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x397; op2val:0x8109; +valaddr_reg:x3; val_offset:462*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 462*FLEN/8, x7, x1, x2) + +inst_257:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab0; op2val:0xf0; +valaddr_reg:x3; val_offset:464*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 464*FLEN/8, x7, x1, x2) + +inst_258:// fs1 == 0 and fe1 == 0x11 and fm1 == 0x17a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x457a; op2val:0xf0; +valaddr_reg:x3; val_offset:466*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 466*FLEN/8, x7, x1, x2) + +inst_259:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x17a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x457a; +valaddr_reg:x3; val_offset:468*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 468*FLEN/8, x7, x1, x2) + +inst_260:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x17a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab0; op2val:0x457a; +valaddr_reg:x3; val_offset:470*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 470*FLEN/8, x7, x1, x2) + +inst_261:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0x7913; +valaddr_reg:x3; val_offset:472*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 472*FLEN/8, x7, x1, x2) + +inst_262:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0xf749; +valaddr_reg:x3; val_offset:474*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 474*FLEN/8, x7, x1, x2) + +inst_263:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf749; op2val:0x7913; +valaddr_reg:x3; val_offset:476*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 476*FLEN/8, x7, x1, x2) + +inst_264:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x378 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0xfb78; +valaddr_reg:x3; val_offset:478*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 478*FLEN/8, x7, x1, x2) + +inst_265:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x378 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb78; op2val:0x7913; +valaddr_reg:x3; val_offset:480*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 480*FLEN/8, x7, x1, x2) + +inst_266:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x21f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0xfa1f; +valaddr_reg:x3; val_offset:482*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 482*FLEN/8, x7, x1, x2) + +inst_267:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa1f; op2val:0x7913; +valaddr_reg:x3; val_offset:484*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 484*FLEN/8, x7, x1, x2) + +inst_268:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0xf82f; +valaddr_reg:x3; val_offset:486*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 486*FLEN/8, x7, x1, x2) + +inst_269:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82f; op2val:0x7913; +valaddr_reg:x3; val_offset:488*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 488*FLEN/8, x7, x1, x2) + +inst_270:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0xf038; +valaddr_reg:x3; val_offset:490*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 490*FLEN/8, x7, x1, x2) + +inst_271:// fs1 == 0 and fe1 == 0x1b and fm1 == 0x00f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c0f; op2val:0xfbff; +valaddr_reg:x3; val_offset:492*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 492*FLEN/8, x7, x1, x2) + +inst_272:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1b and fm2 == 0x00f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x6c0f; +valaddr_reg:x3; val_offset:494*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 494*FLEN/8, x7, x1, x2) + +inst_273:// fs1 == 0 and fe1 == 0x1b and fm1 == 0x00f and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c0f; op2val:0xf038; +valaddr_reg:x3; val_offset:496*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 496*FLEN/8, x7, x1, x2) + +inst_274:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x00f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0x6c0f; +valaddr_reg:x3; val_offset:498*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 498*FLEN/8, x7, x1, x2) + +inst_275:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0x17b; +valaddr_reg:x3; val_offset:500*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 500*FLEN/8, x7, x1, x2) + +inst_276:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2b9 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x184 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b9; op2val:0x7584; +valaddr_reg:x3; val_offset:502*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 502*FLEN/8, x7, x1, x2) + +inst_277:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x184 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2b9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7584; op2val:0x2b9; +valaddr_reg:x3; val_offset:504*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 504*FLEN/8, x7, x1, x2) + +inst_278:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b9; op2val:0x17b; +valaddr_reg:x3; val_offset:506*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 506*FLEN/8, x7, x1, x2) + +inst_279:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2b9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0x2b9; +valaddr_reg:x3; val_offset:508*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 508*FLEN/8, x7, x1, x2) + +inst_280:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0xe; +valaddr_reg:x3; val_offset:510*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 510*FLEN/8, x7, x1, x2) + +inst_281:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x006 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0x6; +valaddr_reg:x3; val_offset:512*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 512*FLEN/8, x7, x1, x2) + +inst_282:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0x3fa; +valaddr_reg:x3; val_offset:514*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 514*FLEN/8, x7, x1, x2) + +inst_283:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2b9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x369 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b9; op2val:0x7b69; +valaddr_reg:x3; val_offset:516*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 516*FLEN/8, x7, x1, x2) + +inst_284:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x369 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2b9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b69; op2val:0x2b9; +valaddr_reg:x3; val_offset:518*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 518*FLEN/8, x7, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_2) + +inst_285:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b9; op2val:0x3fa; +valaddr_reg:x3; val_offset:520*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 520*FLEN/8, x7, x1, x2) + +inst_286:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0x28e; +valaddr_reg:x3; val_offset:522*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 522*FLEN/8, x7, x1, x2) + +inst_287:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2b9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0c2 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b9; op2val:0x78c2; +valaddr_reg:x3; val_offset:524*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 524*FLEN/8, x7, x1, x2) + +inst_288:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2b9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x78c2; op2val:0x2b9; +valaddr_reg:x3; val_offset:526*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 526*FLEN/8, x7, x1, x2) + +inst_289:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b9; op2val:0x28e; +valaddr_reg:x3; val_offset:528*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 528*FLEN/8, x7, x1, x2) + +inst_290:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0x217; +valaddr_reg:x3; val_offset:530*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 530*FLEN/8, x7, x1, x2) + +inst_291:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2b9 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3cb and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b9; op2val:0x77cb; +valaddr_reg:x3; val_offset:532*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 532*FLEN/8, x7, x1, x2) + +inst_292:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3cb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2b9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x77cb; op2val:0x2b9; +valaddr_reg:x3; val_offset:534*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 534*FLEN/8, x7, x1, x2) + +inst_293:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b9; op2val:0x217; +valaddr_reg:x3; val_offset:536*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 536*FLEN/8, x7, x1, x2) + +inst_294:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x195 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0x8195; +valaddr_reg:x3; val_offset:538*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 538*FLEN/8, x7, x1, x2) + +inst_295:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2b9 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x1e7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b9; op2val:0xf5e7; +valaddr_reg:x3; val_offset:540*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 540*FLEN/8, x7, x1, x2) + +inst_296:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x1e7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2b9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf5e7; op2val:0x2b9; +valaddr_reg:x3; val_offset:542*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 542*FLEN/8, x7, x1, x2) + +inst_297:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x195 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b9; op2val:0x8195; +valaddr_reg:x3; val_offset:544*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 544*FLEN/8, x7, x1, x2) + +inst_298:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0x80a7; +valaddr_reg:x3; val_offset:546*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 546*FLEN/8, x7, x1, x2) + +inst_299:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x045 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x45; op2val:0xfbff; +valaddr_reg:x3; val_offset:548*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 548*FLEN/8, x7, x1, x2) + +inst_300:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x045 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x45; +valaddr_reg:x3; val_offset:550*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 550*FLEN/8, x7, x1, x2) + +inst_301:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x045 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x45; op2val:0x80a7; +valaddr_reg:x3; val_offset:552*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 552*FLEN/8, x7, x1, x2) + +inst_302:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x045 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0x45; +valaddr_reg:x3; val_offset:554*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 554*FLEN/8, x7, x1, x2) + +inst_303:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0x821e; +valaddr_reg:x3; val_offset:556*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 556*FLEN/8, x7, x1, x2) + +inst_304:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2b9 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3e4 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b9; op2val:0xf7e4; +valaddr_reg:x3; val_offset:558*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 558*FLEN/8, x7, x1, x2) + +inst_305:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x3e4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2b9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf7e4; op2val:0x2b9; +valaddr_reg:x3; val_offset:560*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 560*FLEN/8, x7, x1, x2) + +inst_306:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b9; op2val:0x821e; +valaddr_reg:x3; val_offset:562*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 562*FLEN/8, x7, x1, x2) + +inst_307:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0x8365; +valaddr_reg:x3; val_offset:564*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 564*FLEN/8, x7, x1, x2) + +inst_308:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2b9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x252 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b9; op2val:0xfa52; +valaddr_reg:x3; val_offset:566*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 566*FLEN/8, x7, x1, x2) + +inst_309:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x252 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2b9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa52; op2val:0x2b9; +valaddr_reg:x3; val_offset:568*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 568*FLEN/8, x7, x1, x2) + +inst_310:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b9; op2val:0x8365; +valaddr_reg:x3; val_offset:570*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 570*FLEN/8, x7, x1, x2) + +inst_311:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x109 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0x8109; +valaddr_reg:x3; val_offset:572*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 572*FLEN/8, x7, x1, x2) + +inst_312:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2b9 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3b9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b9; op2val:0xf3b9; +valaddr_reg:x3; val_offset:574*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 574*FLEN/8, x7, x1, x2) + +inst_313:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2b9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3b9; op2val:0x2b9; +valaddr_reg:x3; val_offset:576*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 576*FLEN/8, x7, x1, x2) + +inst_314:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x109 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b9; op2val:0x8109; +valaddr_reg:x3; val_offset:578*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 578*FLEN/8, x7, x1, x2) + +inst_315:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0xf0; +valaddr_reg:x3; val_offset:580*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 580*FLEN/8, x7, x1, x2) + +inst_316:// fs1 == 0 and fe1 == 0x11 and fm1 == 0x028 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x4428; op2val:0xf0; +valaddr_reg:x3; val_offset:582*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 582*FLEN/8, x7, x1, x2) + +inst_317:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x028 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x4428; +valaddr_reg:x3; val_offset:584*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 584*FLEN/8, x7, x1, x2) + +inst_318:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x028 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0x4428; +valaddr_reg:x3; val_offset:586*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 586*FLEN/8, x7, x1, x2) + +inst_319:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf749; op2val:0xf749; +valaddr_reg:x3; val_offset:588*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 588*FLEN/8, x7, x1, x2) + +inst_320:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x378 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf749; op2val:0xfb78; +valaddr_reg:x3; val_offset:590*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 590*FLEN/8, x7, x1, x2) + +inst_321:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x378 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb78; op2val:0xf749; +valaddr_reg:x3; val_offset:592*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 592*FLEN/8, x7, x1, x2) + +inst_322:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x21f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf749; op2val:0xfa1f; +valaddr_reg:x3; val_offset:594*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 594*FLEN/8, x7, x1, x2) + +inst_323:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 1 and fe2 == 0x1d and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa1f; op2val:0xf749; +valaddr_reg:x3; val_offset:596*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 596*FLEN/8, x7, x1, x2) + +inst_324:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf749; op2val:0xf82f; +valaddr_reg:x3; val_offset:598*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 598*FLEN/8, x7, x1, x2) + +inst_325:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 1 and fe2 == 0x1d and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82f; op2val:0xf749; +valaddr_reg:x3; val_offset:600*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 600*FLEN/8, x7, x1, x2) + +inst_326:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf749; op2val:0xf038; +valaddr_reg:x3; val_offset:602*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 602*FLEN/8, x7, x1, x2) + +inst_327:// fs1 == 1 and fe1 == 0x1a and fm1 == 0x1d4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xe9d4; op2val:0xfbff; +valaddr_reg:x3; val_offset:604*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 604*FLEN/8, x7, x1, x2) + +inst_328:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1a and fm2 == 0x1d4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xe9d4; +valaddr_reg:x3; val_offset:606*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 606*FLEN/8, x7, x1, x2) + +inst_329:// fs1 == 1 and fe1 == 0x1a and fm1 == 0x1d4 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xe9d4; op2val:0xf038; +valaddr_reg:x3; val_offset:608*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 608*FLEN/8, x7, x1, x2) + +inst_330:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x1d4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf749; op2val:0xe9d4; +valaddr_reg:x3; val_offset:610*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 610*FLEN/8, x7, x1, x2) + +inst_331:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17b and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf749; op2val:0x17b; +valaddr_reg:x3; val_offset:612*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 612*FLEN/8, x7, x1, x2) + +inst_332:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1f4 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x184 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x81f4; op2val:0x7584; +valaddr_reg:x3; val_offset:614*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 614*FLEN/8, x7, x1, x2) + +inst_333:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x184 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1f4 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7584; op2val:0x81f4; +valaddr_reg:x3; val_offset:616*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 616*FLEN/8, x7, x1, x2) + +inst_334:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1f4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17b and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x81f4; op2val:0x17b; +valaddr_reg:x3; val_offset:618*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 618*FLEN/8, x7, x1, x2) + +inst_335:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1f4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf749; op2val:0x81f4; +valaddr_reg:x3; val_offset:620*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 620*FLEN/8, x7, x1, x2) + +inst_336:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf749; op2val:0xe; +valaddr_reg:x3; val_offset:622*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 622*FLEN/8, x7, x1, x2) + +inst_337:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x005 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8005; op2val:0x7bff; +valaddr_reg:x3; val_offset:624*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 624*FLEN/8, x7, x1, x2) + +inst_338:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x005 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8005; +valaddr_reg:x3; val_offset:626*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 626*FLEN/8, x7, x1, x2) + +inst_339:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x005 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8005; op2val:0xe; +valaddr_reg:x3; val_offset:628*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 628*FLEN/8, x7, x1, x2) + +inst_340:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x005 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf749; op2val:0x8005; +valaddr_reg:x3; val_offset:630*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 630*FLEN/8, x7, x1, x2) + +inst_341:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf749; op2val:0x3fa; +valaddr_reg:x3; val_offset:632*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 632*FLEN/8, x7, x1, x2) + +inst_342:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1f4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x369 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x81f4; op2val:0x7b69; +valaddr_reg:x3; val_offset:634*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 634*FLEN/8, x7, x1, x2) + +inst_343:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x369 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1f4 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b69; op2val:0x81f4; +valaddr_reg:x3; val_offset:636*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 636*FLEN/8, x7, x1, x2) + +inst_344:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1f4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x81f4; op2val:0x3fa; +valaddr_reg:x3; val_offset:638*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 638*FLEN/8, x7, x1, x2) + +inst_345:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf749; op2val:0x28e; +valaddr_reg:x3; val_offset:640*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 640*FLEN/8, x7, x1, x2) + +inst_346:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1f4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0c2 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x81f4; op2val:0x78c2; +valaddr_reg:x3; val_offset:642*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 642*FLEN/8, x7, x1, x2) + +inst_347:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1f4 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x78c2; op2val:0x81f4; +valaddr_reg:x3; val_offset:644*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 644*FLEN/8, x7, x1, x2) + +inst_348:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1f4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x81f4; op2val:0x28e; +valaddr_reg:x3; val_offset:646*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 646*FLEN/8, x7, x1, x2) + +inst_349:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf749; op2val:0x217; +valaddr_reg:x3; val_offset:648*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 648*FLEN/8, x7, x1, x2) + +inst_350:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1f4 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3cb and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x81f4; op2val:0x77cb; +valaddr_reg:x3; val_offset:650*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 650*FLEN/8, x7, x1, x2) + +inst_351:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3cb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1f4 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x77cb; op2val:0x81f4; +valaddr_reg:x3; val_offset:652*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 652*FLEN/8, x7, x1, x2) + +inst_352:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1f4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x81f4; op2val:0x217; +valaddr_reg:x3; val_offset:654*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 654*FLEN/8, x7, x1, x2) + +inst_353:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x195 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf749; op2val:0x8195; +valaddr_reg:x3; val_offset:656*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 656*FLEN/8, x7, x1, x2) + +inst_354:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1f4 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x1e7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x81f4; op2val:0xf5e7; +valaddr_reg:x3; val_offset:658*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 658*FLEN/8, x7, x1, x2) + +inst_355:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x1e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1f4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf5e7; op2val:0x81f4; +valaddr_reg:x3; val_offset:660*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 660*FLEN/8, x7, x1, x2) + +inst_356:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1f4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x195 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x81f4; op2val:0x8195; +valaddr_reg:x3; val_offset:662*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 662*FLEN/8, x7, x1, x2) + +inst_357:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf749; op2val:0x80a7; +valaddr_reg:x3; val_offset:664*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 664*FLEN/8, x7, x1, x2) + +inst_358:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x032 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8032; op2val:0xfbff; +valaddr_reg:x3; val_offset:666*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 666*FLEN/8, x7, x1, x2) + +inst_359:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x032 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8032; +valaddr_reg:x3; val_offset:668*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 668*FLEN/8, x7, x1, x2) + +inst_360:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x032 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8032; op2val:0x80a7; +valaddr_reg:x3; val_offset:670*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 670*FLEN/8, x7, x1, x2) + +inst_361:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x032 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf749; op2val:0x8032; +valaddr_reg:x3; val_offset:672*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 672*FLEN/8, x7, x1, x2) + +inst_362:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf749; op2val:0x821e; +valaddr_reg:x3; val_offset:674*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 674*FLEN/8, x7, x1, x2) + +inst_363:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1f4 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3e4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x81f4; op2val:0xf7e4; +valaddr_reg:x3; val_offset:676*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 676*FLEN/8, x7, x1, x2) + +inst_364:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x3e4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1f4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf7e4; op2val:0x81f4; +valaddr_reg:x3; val_offset:678*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 678*FLEN/8, x7, x1, x2) + +inst_365:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1f4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x81f4; op2val:0x821e; +valaddr_reg:x3; val_offset:680*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 680*FLEN/8, x7, x1, x2) + +inst_366:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf749; op2val:0x8365; +valaddr_reg:x3; val_offset:682*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 682*FLEN/8, x7, x1, x2) + +inst_367:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1f4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x252 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x81f4; op2val:0xfa52; +valaddr_reg:x3; val_offset:684*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 684*FLEN/8, x7, x1, x2) + +inst_368:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x252 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1f4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa52; op2val:0x81f4; +valaddr_reg:x3; val_offset:686*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 686*FLEN/8, x7, x1, x2) + +inst_369:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1f4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x81f4; op2val:0x8365; +valaddr_reg:x3; val_offset:688*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 688*FLEN/8, x7, x1, x2) + +inst_370:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x109 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf749; op2val:0x8109; +valaddr_reg:x3; val_offset:690*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 690*FLEN/8, x7, x1, x2) + +inst_371:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1f4 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3b9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x81f4; op2val:0xf3b9; +valaddr_reg:x3; val_offset:692*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 692*FLEN/8, x7, x1, x2) + +inst_372:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1f4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3b9; op2val:0x81f4; +valaddr_reg:x3; val_offset:694*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 694*FLEN/8, x7, x1, x2) + +inst_373:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1f4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x109 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x81f4; op2val:0x8109; +valaddr_reg:x3; val_offset:696*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 696*FLEN/8, x7, x1, x2) + +inst_374:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf749; op2val:0xf0; +valaddr_reg:x3; val_offset:698*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 698*FLEN/8, x7, x1, x2) + +inst_375:// fs1 == 1 and fe1 == 0x10 and fm1 == 0x1f8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xc1f8; op2val:0xf0; +valaddr_reg:x3; val_offset:700*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 700*FLEN/8, x7, x1, x2) + +inst_376:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1f8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xc1f8; +valaddr_reg:x3; val_offset:702*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 702*FLEN/8, x7, x1, x2) + +inst_377:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1f8 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf749; op2val:0xc1f8; +valaddr_reg:x3; val_offset:704*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 704*FLEN/8, x7, x1, x2) + +inst_378:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x378 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x378 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb78; op2val:0xfb78; +valaddr_reg:x3; val_offset:706*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 706*FLEN/8, x7, x1, x2) + +inst_379:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x378 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x21f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb78; op2val:0xfa1f; +valaddr_reg:x3; val_offset:708*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 708*FLEN/8, x7, x1, x2) + +inst_380:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x378 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa1f; op2val:0xfb78; +valaddr_reg:x3; val_offset:710*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 710*FLEN/8, x7, x1, x2) + +inst_381:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x378 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb78; op2val:0xf82f; +valaddr_reg:x3; val_offset:712*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 712*FLEN/8, x7, x1, x2) + +inst_382:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x378 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82f; op2val:0xfb78; +valaddr_reg:x3; val_offset:714*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 714*FLEN/8, x7, x1, x2) + +inst_383:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x378 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb78; op2val:0xf038; +valaddr_reg:x3; val_offset:716*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 716*FLEN/8, x7, x1, x2) + +inst_384:// fs1 == 1 and fe1 == 0x1b and fm1 == 0x1fa and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xedfa; op2val:0xfbff; +valaddr_reg:x3; val_offset:718*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 718*FLEN/8, x7, x1, x2) + +inst_385:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1b and fm2 == 0x1fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xedfa; +valaddr_reg:x3; val_offset:720*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 720*FLEN/8, x7, x1, x2) + +inst_386:// fs1 == 1 and fe1 == 0x1b and fm1 == 0x1fa and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xedfa; op2val:0xf038; +valaddr_reg:x3; val_offset:722*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 722*FLEN/8, x7, x1, x2) + +inst_387:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x378 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x1fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb78; op2val:0xedfa; +valaddr_reg:x3; val_offset:724*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 724*FLEN/8, x7, x1, x2) + +inst_388:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x378 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17b and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb78; op2val:0x17b; +valaddr_reg:x3; val_offset:726*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 726*FLEN/8, x7, x1, x2) + +inst_389:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x184 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8402; op2val:0x7584; +valaddr_reg:x3; val_offset:728*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 728*FLEN/8, x7, x1, x2) + +inst_390:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x184 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7584; op2val:0x8402; +valaddr_reg:x3; val_offset:730*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 730*FLEN/8, x7, x1, x2) + +inst_391:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17b and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8402; op2val:0x17b; +valaddr_reg:x3; val_offset:732*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 732*FLEN/8, x7, x1, x2) + +inst_392:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x378 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb78; op2val:0x8402; +valaddr_reg:x3; val_offset:734*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 734*FLEN/8, x7, x1, x2) + +inst_393:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x378 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb78; op2val:0xe; +valaddr_reg:x3; val_offset:736*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 736*FLEN/8, x7, x1, x2) + +inst_394:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x00a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x800a; op2val:0x7bff; +valaddr_reg:x3; val_offset:738*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 738*FLEN/8, x7, x1, x2) + +inst_395:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x800a; +valaddr_reg:x3; val_offset:740*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 740*FLEN/8, x7, x1, x2) + +inst_396:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x00a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x800a; op2val:0xe; +valaddr_reg:x3; val_offset:742*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 742*FLEN/8, x7, x1, x2) + +inst_397:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x378 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb78; op2val:0x800a; +valaddr_reg:x3; val_offset:744*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 744*FLEN/8, x7, x1, x2) + +inst_398:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x378 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb78; op2val:0x3fa; +valaddr_reg:x3; val_offset:746*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 746*FLEN/8, x7, x1, x2) + +inst_399:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x369 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8402; op2val:0x7b69; +valaddr_reg:x3; val_offset:748*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 748*FLEN/8, x7, x1, x2) + +inst_400:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x369 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b69; op2val:0x8402; +valaddr_reg:x3; val_offset:750*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 750*FLEN/8, x7, x1, x2) + +inst_401:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8402; op2val:0x3fa; +valaddr_reg:x3; val_offset:752*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 752*FLEN/8, x7, x1, x2) + +inst_402:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x378 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb78; op2val:0x28e; +valaddr_reg:x3; val_offset:754*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 754*FLEN/8, x7, x1, x2) + +inst_403:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0c2 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8402; op2val:0x78c2; +valaddr_reg:x3; val_offset:756*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 756*FLEN/8, x7, x1, x2) + +inst_404:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x78c2; op2val:0x8402; +valaddr_reg:x3; val_offset:758*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 758*FLEN/8, x7, x1, x2) + +inst_405:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8402; op2val:0x28e; +valaddr_reg:x3; val_offset:760*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 760*FLEN/8, x7, x1, x2) + +inst_406:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x378 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb78; op2val:0x217; +valaddr_reg:x3; val_offset:762*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 762*FLEN/8, x7, x1, x2) + +inst_407:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3cb and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8402; op2val:0x77cb; +valaddr_reg:x3; val_offset:764*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 764*FLEN/8, x7, x1, x2) + +inst_408:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3cb and fs2 == 1 and fe2 == 0x01 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x77cb; op2val:0x8402; +valaddr_reg:x3; val_offset:766*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 766*FLEN/8, x7, x1, x2) + +inst_409:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8402; op2val:0x217; +valaddr_reg:x3; val_offset:768*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 768*FLEN/8, x7, x1, x2) + +inst_410:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x378 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x195 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb78; op2val:0x8195; +valaddr_reg:x3; val_offset:770*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 770*FLEN/8, x7, x1, x2) + +inst_411:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x1e7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8402; op2val:0xf5e7; +valaddr_reg:x3; val_offset:772*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 772*FLEN/8, x7, x1, x2) + +inst_412:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x1e7 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf5e7; op2val:0x8402; +valaddr_reg:x3; val_offset:774*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 774*FLEN/8, x7, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_3) + +inst_413:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x195 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8402; op2val:0x8195; +valaddr_reg:x3; val_offset:776*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 776*FLEN/8, x7, x1, x2) + +inst_414:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x378 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb78; op2val:0x80a7; +valaddr_reg:x3; val_offset:778*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 778*FLEN/8, x7, x1, x2) + +inst_415:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x066 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8066; op2val:0xfbff; +valaddr_reg:x3; val_offset:780*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 780*FLEN/8, x7, x1, x2) + +inst_416:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x066 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8066; +valaddr_reg:x3; val_offset:782*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 782*FLEN/8, x7, x1, x2) + +inst_417:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x066 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8066; op2val:0x80a7; +valaddr_reg:x3; val_offset:784*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 784*FLEN/8, x7, x1, x2) + +inst_418:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x378 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x066 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb78; op2val:0x8066; +valaddr_reg:x3; val_offset:786*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 786*FLEN/8, x7, x1, x2) + +inst_419:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x378 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb78; op2val:0x821e; +valaddr_reg:x3; val_offset:788*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 788*FLEN/8, x7, x1, x2) + +inst_420:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3e4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8402; op2val:0xf7e4; +valaddr_reg:x3; val_offset:790*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 790*FLEN/8, x7, x1, x2) + +inst_421:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x3e4 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf7e4; op2val:0x8402; +valaddr_reg:x3; val_offset:792*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 792*FLEN/8, x7, x1, x2) + +inst_422:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8402; op2val:0x821e; +valaddr_reg:x3; val_offset:794*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 794*FLEN/8, x7, x1, x2) + +inst_423:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x378 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb78; op2val:0x8365; +valaddr_reg:x3; val_offset:796*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 796*FLEN/8, x7, x1, x2) + +inst_424:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x252 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8402; op2val:0xfa52; +valaddr_reg:x3; val_offset:798*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 798*FLEN/8, x7, x1, x2) + +inst_425:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x252 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa52; op2val:0x8402; +valaddr_reg:x3; val_offset:800*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 800*FLEN/8, x7, x1, x2) + +inst_426:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8402; op2val:0x8365; +valaddr_reg:x3; val_offset:802*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 802*FLEN/8, x7, x1, x2) + +inst_427:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x378 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x109 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb78; op2val:0x8109; +valaddr_reg:x3; val_offset:804*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 804*FLEN/8, x7, x1, x2) + +inst_428:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3b9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8402; op2val:0xf3b9; +valaddr_reg:x3; val_offset:806*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 806*FLEN/8, x7, x1, x2) + +inst_429:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3b9 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3b9; op2val:0x8402; +valaddr_reg:x3; val_offset:808*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 808*FLEN/8, x7, x1, x2) + +inst_430:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x109 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8402; op2val:0x8109; +valaddr_reg:x3; val_offset:810*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 810*FLEN/8, x7, x1, x2) + +inst_431:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x378 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb78; op2val:0xf0; +valaddr_reg:x3; val_offset:812*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 812*FLEN/8, x7, x1, x2) + +inst_432:// fs1 == 1 and fe1 == 0x11 and fm1 == 0x21f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xc61f; op2val:0xf0; +valaddr_reg:x3; val_offset:814*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 814*FLEN/8, x7, x1, x2) + +inst_433:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x21f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xc61f; +valaddr_reg:x3; val_offset:816*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 816*FLEN/8, x7, x1, x2) + +inst_434:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x378 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x21f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb78; op2val:0xc61f; +valaddr_reg:x3; val_offset:818*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 818*FLEN/8, x7, x1, x2) + +inst_435:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x21f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa1f; op2val:0xfa1f; +valaddr_reg:x3; val_offset:820*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 820*FLEN/8, x7, x1, x2) + +inst_436:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa1f; op2val:0xf82f; +valaddr_reg:x3; val_offset:822*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 822*FLEN/8, x7, x1, x2) + +inst_437:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x21f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82f; op2val:0xfa1f; +valaddr_reg:x3; val_offset:824*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 824*FLEN/8, x7, x1, x2) + +inst_438:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa1f; op2val:0xf038; +valaddr_reg:x3; val_offset:826*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 826*FLEN/8, x7, x1, x2) + +inst_439:// fs1 == 1 and fe1 == 0x1b and fm1 == 0x0e5 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xece5; op2val:0xfbff; +valaddr_reg:x3; val_offset:828*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 828*FLEN/8, x7, x1, x2) + +inst_440:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1b and fm2 == 0x0e5 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xece5; +valaddr_reg:x3; val_offset:830*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 830*FLEN/8, x7, x1, x2) + +inst_441:// fs1 == 1 and fe1 == 0x1b and fm1 == 0x0e5 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xece5; op2val:0xf038; +valaddr_reg:x3; val_offset:832*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 832*FLEN/8, x7, x1, x2) + +inst_442:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 1 and fe2 == 0x1b and fm2 == 0x0e5 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa1f; op2val:0xece5; +valaddr_reg:x3; val_offset:834*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 834*FLEN/8, x7, x1, x2) + +inst_443:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17b and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa1f; op2val:0x17b; +valaddr_reg:x3; val_offset:836*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 836*FLEN/8, x7, x1, x2) + +inst_444:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x349 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x184 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8349; op2val:0x7584; +valaddr_reg:x3; val_offset:838*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 838*FLEN/8, x7, x1, x2) + +inst_445:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x184 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7584; op2val:0x8349; +valaddr_reg:x3; val_offset:840*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 840*FLEN/8, x7, x1, x2) + +inst_446:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x349 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17b and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8349; op2val:0x17b; +valaddr_reg:x3; val_offset:842*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 842*FLEN/8, x7, x1, x2) + +inst_447:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa1f; op2val:0x8349; +valaddr_reg:x3; val_offset:844*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 844*FLEN/8, x7, x1, x2) + +inst_448:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa1f; op2val:0xe; +valaddr_reg:x3; val_offset:846*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 846*FLEN/8, x7, x1, x2) + +inst_449:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x008 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8008; op2val:0x7bff; +valaddr_reg:x3; val_offset:848*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 848*FLEN/8, x7, x1, x2) + +inst_450:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x008 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8008; +valaddr_reg:x3; val_offset:850*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 850*FLEN/8, x7, x1, x2) + +inst_451:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x008 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8008; op2val:0xe; +valaddr_reg:x3; val_offset:852*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 852*FLEN/8, x7, x1, x2) + +inst_452:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x008 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa1f; op2val:0x8008; +valaddr_reg:x3; val_offset:854*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 854*FLEN/8, x7, x1, x2) + +inst_453:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa1f; op2val:0x3fa; +valaddr_reg:x3; val_offset:856*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 856*FLEN/8, x7, x1, x2) + +inst_454:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x349 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x369 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8349; op2val:0x7b69; +valaddr_reg:x3; val_offset:858*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 858*FLEN/8, x7, x1, x2) + +inst_455:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x369 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b69; op2val:0x8349; +valaddr_reg:x3; val_offset:860*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 860*FLEN/8, x7, x1, x2) + +inst_456:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x349 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8349; op2val:0x3fa; +valaddr_reg:x3; val_offset:862*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 862*FLEN/8, x7, x1, x2) + +inst_457:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa1f; op2val:0x28e; +valaddr_reg:x3; val_offset:864*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 864*FLEN/8, x7, x1, x2) + +inst_458:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x349 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0c2 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8349; op2val:0x78c2; +valaddr_reg:x3; val_offset:866*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 866*FLEN/8, x7, x1, x2) + +inst_459:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x78c2; op2val:0x8349; +valaddr_reg:x3; val_offset:868*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 868*FLEN/8, x7, x1, x2) + +inst_460:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x349 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8349; op2val:0x28e; +valaddr_reg:x3; val_offset:870*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 870*FLEN/8, x7, x1, x2) + +inst_461:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa1f; op2val:0x217; +valaddr_reg:x3; val_offset:872*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 872*FLEN/8, x7, x1, x2) + +inst_462:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x349 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3cb and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8349; op2val:0x77cb; +valaddr_reg:x3; val_offset:874*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 874*FLEN/8, x7, x1, x2) + +inst_463:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3cb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x77cb; op2val:0x8349; +valaddr_reg:x3; val_offset:876*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 876*FLEN/8, x7, x1, x2) + +inst_464:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x349 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8349; op2val:0x217; +valaddr_reg:x3; val_offset:878*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 878*FLEN/8, x7, x1, x2) + +inst_465:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x195 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa1f; op2val:0x8195; +valaddr_reg:x3; val_offset:880*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 880*FLEN/8, x7, x1, x2) + +inst_466:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x349 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x1e7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8349; op2val:0xf5e7; +valaddr_reg:x3; val_offset:882*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 882*FLEN/8, x7, x1, x2) + +inst_467:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x1e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf5e7; op2val:0x8349; +valaddr_reg:x3; val_offset:884*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 884*FLEN/8, x7, x1, x2) + +inst_468:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x349 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x195 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8349; op2val:0x8195; +valaddr_reg:x3; val_offset:886*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 886*FLEN/8, x7, x1, x2) + +inst_469:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa1f; op2val:0x80a7; +valaddr_reg:x3; val_offset:888*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 888*FLEN/8, x7, x1, x2) + +inst_470:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x054 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8054; op2val:0xfbff; +valaddr_reg:x3; val_offset:890*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 890*FLEN/8, x7, x1, x2) + +inst_471:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x054 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8054; +valaddr_reg:x3; val_offset:892*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 892*FLEN/8, x7, x1, x2) + +inst_472:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x054 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8054; op2val:0x80a7; +valaddr_reg:x3; val_offset:894*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 894*FLEN/8, x7, x1, x2) + +inst_473:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x054 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa1f; op2val:0x8054; +valaddr_reg:x3; val_offset:896*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 896*FLEN/8, x7, x1, x2) + +inst_474:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa1f; op2val:0x821e; +valaddr_reg:x3; val_offset:898*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 898*FLEN/8, x7, x1, x2) + +inst_475:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x349 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3e4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8349; op2val:0xf7e4; +valaddr_reg:x3; val_offset:900*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 900*FLEN/8, x7, x1, x2) + +inst_476:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x3e4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf7e4; op2val:0x8349; +valaddr_reg:x3; val_offset:902*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 902*FLEN/8, x7, x1, x2) + +inst_477:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x349 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8349; op2val:0x821e; +valaddr_reg:x3; val_offset:904*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 904*FLEN/8, x7, x1, x2) + +inst_478:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa1f; op2val:0x8365; +valaddr_reg:x3; val_offset:906*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 906*FLEN/8, x7, x1, x2) + +inst_479:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x349 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x252 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8349; op2val:0xfa52; +valaddr_reg:x3; val_offset:908*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 908*FLEN/8, x7, x1, x2) + +inst_480:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x252 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa52; op2val:0x8349; +valaddr_reg:x3; val_offset:910*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 910*FLEN/8, x7, x1, x2) + +inst_481:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x349 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8349; op2val:0x8365; +valaddr_reg:x3; val_offset:912*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 912*FLEN/8, x7, x1, x2) + +inst_482:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x109 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa1f; op2val:0x8109; +valaddr_reg:x3; val_offset:914*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 914*FLEN/8, x7, x1, x2) + +inst_483:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x349 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3b9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8349; op2val:0xf3b9; +valaddr_reg:x3; val_offset:916*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 916*FLEN/8, x7, x1, x2) + +inst_484:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3b9; op2val:0x8349; +valaddr_reg:x3; val_offset:918*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 918*FLEN/8, x7, x1, x2) + +inst_485:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x349 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x109 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8349; op2val:0x8109; +valaddr_reg:x3; val_offset:920*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 920*FLEN/8, x7, x1, x2) + +inst_486:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa1f; op2val:0xf0; +valaddr_reg:x3; val_offset:922*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 922*FLEN/8, x7, x1, x2) + +inst_487:// fs1 == 1 and fe1 == 0x11 and fm1 == 0x103 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xc503; op2val:0xf0; +valaddr_reg:x3; val_offset:924*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 924*FLEN/8, x7, x1, x2) + +inst_488:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x103 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xc503; +valaddr_reg:x3; val_offset:926*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 926*FLEN/8, x7, x1, x2) + +inst_489:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 1 and fe2 == 0x11 and fm2 == 0x103 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa1f; op2val:0xc503; +valaddr_reg:x3; val_offset:928*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 928*FLEN/8, x7, x1, x2) + +inst_490:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82f; op2val:0xf82f; +valaddr_reg:x3; val_offset:930*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 930*FLEN/8, x7, x1, x2) + +inst_491:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82f; op2val:0xf038; +valaddr_reg:x3; val_offset:932*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 932*FLEN/8, x7, x1, x2) + +inst_492:// fs1 == 1 and fe1 == 0x1a and fm1 == 0x2b3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xeab3; op2val:0xfbff; +valaddr_reg:x3; val_offset:934*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 934*FLEN/8, x7, x1, x2) + +inst_493:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1a and fm2 == 0x2b3 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xeab3; +valaddr_reg:x3; val_offset:936*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 936*FLEN/8, x7, x1, x2) + +inst_494:// fs1 == 1 and fe1 == 0x1a and fm1 == 0x2b3 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xeab3; op2val:0xf038; +valaddr_reg:x3; val_offset:938*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 938*FLEN/8, x7, x1, x2) + +inst_495:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 1 and fe2 == 0x1a and fm2 == 0x2b3 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82f; op2val:0xeab3; +valaddr_reg:x3; val_offset:940*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 940*FLEN/8, x7, x1, x2) + +inst_496:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17b and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82f; op2val:0x17b; +valaddr_reg:x3; val_offset:942*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 942*FLEN/8, x7, x1, x2) + +inst_497:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x23f and fs2 == 0 and fe2 == 0x1d and fm2 == 0x184 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x823f; op2val:0x7584; +valaddr_reg:x3; val_offset:944*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 944*FLEN/8, x7, x1, x2) + +inst_498:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x184 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x23f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7584; op2val:0x823f; +valaddr_reg:x3; val_offset:946*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 946*FLEN/8, x7, x1, x2) + +inst_499:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x23f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17b and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x823f; op2val:0x17b; +valaddr_reg:x3; val_offset:948*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 948*FLEN/8, x7, x1, x2) + +inst_500:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x23f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82f; op2val:0x823f; +valaddr_reg:x3; val_offset:950*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 950*FLEN/8, x7, x1, x2) + +inst_501:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82f; op2val:0xe; +valaddr_reg:x3; val_offset:952*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 952*FLEN/8, x7, x1, x2) + +inst_502:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x005 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82f; op2val:0x8005; +valaddr_reg:x3; val_offset:954*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 954*FLEN/8, x7, x1, x2) + +inst_503:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82f; op2val:0x3fa; +valaddr_reg:x3; val_offset:956*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 956*FLEN/8, x7, x1, x2) + +inst_504:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x23f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x369 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x823f; op2val:0x7b69; +valaddr_reg:x3; val_offset:958*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 958*FLEN/8, x7, x1, x2) + +inst_505:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x369 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x23f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b69; op2val:0x823f; +valaddr_reg:x3; val_offset:960*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 960*FLEN/8, x7, x1, x2) + +inst_506:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x23f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x823f; op2val:0x3fa; +valaddr_reg:x3; val_offset:962*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 962*FLEN/8, x7, x1, x2) + +inst_507:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82f; op2val:0x28e; +valaddr_reg:x3; val_offset:964*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 964*FLEN/8, x7, x1, x2) + +inst_508:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x23f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0c2 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x823f; op2val:0x78c2; +valaddr_reg:x3; val_offset:966*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 966*FLEN/8, x7, x1, x2) + +inst_509:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x23f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x78c2; op2val:0x823f; +valaddr_reg:x3; val_offset:968*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 968*FLEN/8, x7, x1, x2) + +inst_510:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x23f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x823f; op2val:0x28e; +valaddr_reg:x3; val_offset:970*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 970*FLEN/8, x7, x1, x2) + +inst_511:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82f; op2val:0x217; +valaddr_reg:x3; val_offset:972*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 972*FLEN/8, x7, x1, x2) + +inst_512:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x23f and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3cb and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x823f; op2val:0x77cb; +valaddr_reg:x3; val_offset:974*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 974*FLEN/8, x7, x1, x2) + +inst_513:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3cb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x23f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x77cb; op2val:0x823f; +valaddr_reg:x3; val_offset:976*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 976*FLEN/8, x7, x1, x2) + +inst_514:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x23f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x823f; op2val:0x217; +valaddr_reg:x3; val_offset:978*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 978*FLEN/8, x7, x1, x2) + +inst_515:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x195 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82f; op2val:0x8195; +valaddr_reg:x3; val_offset:980*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 980*FLEN/8, x7, x1, x2) + +inst_516:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x23f and fs2 == 1 and fe2 == 0x1d and fm2 == 0x1e7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x823f; op2val:0xf5e7; +valaddr_reg:x3; val_offset:982*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 982*FLEN/8, x7, x1, x2) + +inst_517:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x1e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x23f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf5e7; op2val:0x823f; +valaddr_reg:x3; val_offset:984*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 984*FLEN/8, x7, x1, x2) + +inst_518:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x23f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x195 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x823f; op2val:0x8195; +valaddr_reg:x3; val_offset:986*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 986*FLEN/8, x7, x1, x2) + +inst_519:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82f; op2val:0x80a7; +valaddr_reg:x3; val_offset:988*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 988*FLEN/8, x7, x1, x2) + +inst_520:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x039 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8039; op2val:0xfbff; +valaddr_reg:x3; val_offset:990*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 990*FLEN/8, x7, x1, x2) + +inst_521:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x039 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8039; +valaddr_reg:x3; val_offset:992*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 992*FLEN/8, x7, x1, x2) + +inst_522:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x039 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8039; op2val:0x80a7; +valaddr_reg:x3; val_offset:994*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 994*FLEN/8, x7, x1, x2) + +inst_523:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x039 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82f; op2val:0x8039; +valaddr_reg:x3; val_offset:996*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 996*FLEN/8, x7, x1, x2) + +inst_524:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82f; op2val:0x821e; +valaddr_reg:x3; val_offset:998*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 998*FLEN/8, x7, x1, x2) + +inst_525:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x23f and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3e4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x823f; op2val:0xf7e4; +valaddr_reg:x3; val_offset:1000*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1000*FLEN/8, x7, x1, x2) + +inst_526:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x3e4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x23f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf7e4; op2val:0x823f; +valaddr_reg:x3; val_offset:1002*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1002*FLEN/8, x7, x1, x2) + +inst_527:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x23f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x823f; op2val:0x821e; +valaddr_reg:x3; val_offset:1004*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1004*FLEN/8, x7, x1, x2) + +inst_528:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82f; op2val:0x8365; +valaddr_reg:x3; val_offset:1006*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1006*FLEN/8, x7, x1, x2) + +inst_529:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x23f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x252 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x823f; op2val:0xfa52; +valaddr_reg:x3; val_offset:1008*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1008*FLEN/8, x7, x1, x2) + +inst_530:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x252 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x23f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa52; op2val:0x823f; +valaddr_reg:x3; val_offset:1010*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1010*FLEN/8, x7, x1, x2) + +inst_531:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x23f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x823f; op2val:0x8365; +valaddr_reg:x3; val_offset:1012*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1012*FLEN/8, x7, x1, x2) + +inst_532:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x109 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82f; op2val:0x8109; +valaddr_reg:x3; val_offset:1014*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1014*FLEN/8, x7, x1, x2) + +inst_533:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x23f and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3b9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x823f; op2val:0xf3b9; +valaddr_reg:x3; val_offset:1016*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1016*FLEN/8, x7, x1, x2) + +inst_534:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x23f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3b9; op2val:0x823f; +valaddr_reg:x3; val_offset:1018*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1018*FLEN/8, x7, x1, x2) + +inst_535:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x23f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x109 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x823f; op2val:0x8109; +valaddr_reg:x3; val_offset:1020*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1020*FLEN/8, x7, x1, x2) + +inst_536:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82f; op2val:0xf0; +valaddr_reg:x3; val_offset:1022*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1022*FLEN/8, x7, x1, x2) + +inst_537:// fs1 == 1 and fe1 == 0x10 and fm1 == 0x2dc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xc2dc; op2val:0xf0; +valaddr_reg:x3; val_offset:1024*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1024*FLEN/8, x7, x1, x2) + +inst_538:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2dc and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xc2dc; +valaddr_reg:x3; val_offset:1026*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1026*FLEN/8, x7, x1, x2) + +inst_539:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2dc and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82f; op2val:0xc2dc; +valaddr_reg:x3; val_offset:1028*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1028*FLEN/8, x7, x1, x2) + +inst_540:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x038 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf038; op2val:0x739c; +valaddr_reg:x3; val_offset:1030*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1030*FLEN/8, x7, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_4) + +inst_541:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x739c; +valaddr_reg:x3; val_offset:1032*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1032*FLEN/8, x7, x1, x2) + +inst_542:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x038 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf038; op2val:0xfbff; +valaddr_reg:x3; val_offset:1034*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1034*FLEN/8, x7, x1, x2) + +inst_543:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x038 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf038; op2val:0xf038; +valaddr_reg:x3; val_offset:1036*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1036*FLEN/8, x7, x1, x2) + +inst_544:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x038 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x100 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf038; op2val:0x7900; +valaddr_reg:x3; val_offset:1038*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1038*FLEN/8, x7, x1, x2) + +inst_545:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x100 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7900; +valaddr_reg:x3; val_offset:1040*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1040*FLEN/8, x7, x1, x2) + +inst_546:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x038 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x025 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf038; op2val:0x7425; +valaddr_reg:x3; val_offset:1042*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1042*FLEN/8, x7, x1, x2) + +inst_547:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1d and fm2 == 0x025 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7425; +valaddr_reg:x3; val_offset:1044*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1044*FLEN/8, x7, x1, x2) + +inst_548:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x038 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf038; op2val:0x7ab0; +valaddr_reg:x3; val_offset:1046*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1046*FLEN/8, x7, x1, x2) + +inst_549:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7ab0; +valaddr_reg:x3; val_offset:1048*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1048*FLEN/8, x7, x1, x2) + +inst_550:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x038 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf038; op2val:0x7913; +valaddr_reg:x3; val_offset:1050*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1050*FLEN/8, x7, x1, x2) + +inst_551:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7913; +valaddr_reg:x3; val_offset:1052*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1052*FLEN/8, x7, x1, x2) + +inst_552:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x038 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf038; op2val:0xf749; +valaddr_reg:x3; val_offset:1054*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1054*FLEN/8, x7, x1, x2) + +inst_553:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1d and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf749; +valaddr_reg:x3; val_offset:1056*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1056*FLEN/8, x7, x1, x2) + +inst_554:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x038 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x378 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf038; op2val:0xfb78; +valaddr_reg:x3; val_offset:1058*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1058*FLEN/8, x7, x1, x2) + +inst_555:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x378 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfb78; +valaddr_reg:x3; val_offset:1060*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1060*FLEN/8, x7, x1, x2) + +inst_556:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x038 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x21f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf038; op2val:0xfa1f; +valaddr_reg:x3; val_offset:1062*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1062*FLEN/8, x7, x1, x2) + +inst_557:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x21f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfa1f; +valaddr_reg:x3; val_offset:1064*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1064*FLEN/8, x7, x1, x2) + +inst_558:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x038 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf038; op2val:0xf82f; +valaddr_reg:x3; val_offset:1066*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1066*FLEN/8, x7, x1, x2) + +inst_559:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf82f; +valaddr_reg:x3; val_offset:1068*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1068*FLEN/8, x7, x1, x2) + +inst_560:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x038 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17b and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf038; op2val:0x17b; +valaddr_reg:x3; val_offset:1070*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1070*FLEN/8, x7, x1, x2) + +inst_561:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x1aa and fs2 == 0 and fe2 == 0x1a and fm2 == 0x069 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x85aa; op2val:0x6869; +valaddr_reg:x3; val_offset:1072*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1072*FLEN/8, x7, x1, x2) + +inst_562:// fs1 == 0 and fe1 == 0x1a and fm1 == 0x069 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x1aa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x6869; op2val:0x85aa; +valaddr_reg:x3; val_offset:1074*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1074*FLEN/8, x7, x1, x2) + +inst_563:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x1aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17b and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x85aa; op2val:0x17b; +valaddr_reg:x3; val_offset:1076*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1076*FLEN/8, x7, x1, x2) + +inst_564:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x038 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x1aa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf038; op2val:0x85aa; +valaddr_reg:x3; val_offset:1078*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1078*FLEN/8, x7, x1, x2) + +inst_565:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x038 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf038; op2val:0xe; +valaddr_reg:x3; val_offset:1080*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1080*FLEN/8, x7, x1, x2) + +inst_566:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 0 and fe2 == 0x1c and fm2 == 0x035 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x800e; op2val:0x7035; +valaddr_reg:x3; val_offset:1082*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1082*FLEN/8, x7, x1, x2) + +inst_567:// fs1 == 0 and fe1 == 0x1c and fm1 == 0x035 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7035; op2val:0x800e; +valaddr_reg:x3; val_offset:1084*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1084*FLEN/8, x7, x1, x2) + +inst_568:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x800e; op2val:0xe; +valaddr_reg:x3; val_offset:1086*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1086*FLEN/8, x7, x1, x2) + +inst_569:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x038 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf038; op2val:0x800e; +valaddr_reg:x3; val_offset:1088*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1088*FLEN/8, x7, x1, x2) + +inst_570:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x038 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf038; op2val:0x3fa; +valaddr_reg:x3; val_offset:1090*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1090*FLEN/8, x7, x1, x2) + +inst_571:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x1aa and fs2 == 0 and fe2 == 0x1b and fm2 == 0x1ed and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x85aa; op2val:0x6ded; +valaddr_reg:x3; val_offset:1092*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1092*FLEN/8, x7, x1, x2) + +inst_572:// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ed and fs2 == 1 and fe2 == 0x01 and fm2 == 0x1aa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ded; op2val:0x85aa; +valaddr_reg:x3; val_offset:1094*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1094*FLEN/8, x7, x1, x2) + +inst_573:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x1aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x85aa; op2val:0x3fa; +valaddr_reg:x3; val_offset:1096*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1096*FLEN/8, x7, x1, x2) + +inst_574:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x038 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf038; op2val:0x28e; +valaddr_reg:x3; val_offset:1098*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1098*FLEN/8, x7, x1, x2) + +inst_575:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x1aa and fs2 == 0 and fe2 == 0x1a and fm2 == 0x39d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x85aa; op2val:0x6b9d; +valaddr_reg:x3; val_offset:1100*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1100*FLEN/8, x7, x1, x2) + +inst_576:// fs1 == 0 and fe1 == 0x1a and fm1 == 0x39d and fs2 == 1 and fe2 == 0x01 and fm2 == 0x1aa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x6b9d; op2val:0x85aa; +valaddr_reg:x3; val_offset:1102*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1102*FLEN/8, x7, x1, x2) + +inst_577:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x1aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x85aa; op2val:0x28e; +valaddr_reg:x3; val_offset:1104*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1104*FLEN/8, x7, x1, x2) + +inst_578:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x038 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf038; op2val:0x217; +valaddr_reg:x3; val_offset:1106*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1106*FLEN/8, x7, x1, x2) + +inst_579:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x1aa and fs2 == 0 and fe2 == 0x1a and fm2 == 0x23c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x85aa; op2val:0x6a3c; +valaddr_reg:x3; val_offset:1108*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1108*FLEN/8, x7, x1, x2) + +inst_580:// fs1 == 0 and fe1 == 0x1a and fm1 == 0x23c and fs2 == 1 and fe2 == 0x01 and fm2 == 0x1aa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x6a3c; op2val:0x85aa; +valaddr_reg:x3; val_offset:1110*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1110*FLEN/8, x7, x1, x2) + +inst_581:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x1aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x85aa; op2val:0x217; +valaddr_reg:x3; val_offset:1112*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1112*FLEN/8, x7, x1, x2) + +inst_582:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x038 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x195 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf038; op2val:0x8195; +valaddr_reg:x3; val_offset:1114*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1114*FLEN/8, x7, x1, x2) + +inst_583:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x1aa and fs2 == 1 and fe2 == 0x1a and fm2 == 0x0b9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x85aa; op2val:0xe8b9; +valaddr_reg:x3; val_offset:1116*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1116*FLEN/8, x7, x1, x2) + +inst_584:// fs1 == 1 and fe1 == 0x1a and fm1 == 0x0b9 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x1aa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xe8b9; op2val:0x85aa; +valaddr_reg:x3; val_offset:1118*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1118*FLEN/8, x7, x1, x2) + +inst_585:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x1aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x195 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x85aa; op2val:0x8195; +valaddr_reg:x3; val_offset:1120*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1120*FLEN/8, x7, x1, x2) + +inst_586:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x038 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf038; op2val:0x80a7; +valaddr_reg:x3; val_offset:1122*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1122*FLEN/8, x7, x1, x2) + +inst_587:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x091 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0dd and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8091; op2val:0xf0dd; +valaddr_reg:x3; val_offset:1124*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1124*FLEN/8, x7, x1, x2) + +inst_588:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x0dd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x091 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0dd; op2val:0x8091; +valaddr_reg:x3; val_offset:1126*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1126*FLEN/8, x7, x1, x2) + +inst_589:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x091 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8091; op2val:0x80a7; +valaddr_reg:x3; val_offset:1128*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1128*FLEN/8, x7, x1, x2) + +inst_590:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x038 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x091 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf038; op2val:0x8091; +valaddr_reg:x3; val_offset:1130*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1130*FLEN/8, x7, x1, x2) + +inst_591:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x038 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf038; op2val:0x821e; +valaddr_reg:x3; val_offset:1132*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1132*FLEN/8, x7, x1, x2) + +inst_592:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x1aa and fs2 == 1 and fe2 == 0x1a and fm2 == 0x250 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x85aa; op2val:0xea50; +valaddr_reg:x3; val_offset:1134*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1134*FLEN/8, x7, x1, x2) + +inst_593:// fs1 == 1 and fe1 == 0x1a and fm1 == 0x250 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x1aa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xea50; op2val:0x85aa; +valaddr_reg:x3; val_offset:1136*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1136*FLEN/8, x7, x1, x2) + +inst_594:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x1aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x85aa; op2val:0x821e; +valaddr_reg:x3; val_offset:1138*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1138*FLEN/8, x7, x1, x2) + +inst_595:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x038 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf038; op2val:0x8365; +valaddr_reg:x3; val_offset:1140*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1140*FLEN/8, x7, x1, x2) + +inst_596:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x1aa and fs2 == 1 and fe2 == 0x1b and fm2 == 0x10f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x85aa; op2val:0xed0f; +valaddr_reg:x3; val_offset:1142*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1142*FLEN/8, x7, x1, x2) + +inst_597:// fs1 == 1 and fe1 == 0x1b and fm1 == 0x10f and fs2 == 1 and fe2 == 0x01 and fm2 == 0x1aa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xed0f; op2val:0x85aa; +valaddr_reg:x3; val_offset:1144*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1144*FLEN/8, x7, x1, x2) + +inst_598:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x1aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x85aa; op2val:0x8365; +valaddr_reg:x3; val_offset:1146*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1146*FLEN/8, x7, x1, x2) + +inst_599:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x038 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x109 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf038; op2val:0x8109; +valaddr_reg:x3; val_offset:1148*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1148*FLEN/8, x7, x1, x2) + +inst_600:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x1aa and fs2 == 1 and fe2 == 0x19 and fm2 == 0x22e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x85aa; op2val:0xe62e; +valaddr_reg:x3; val_offset:1150*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1150*FLEN/8, x7, x1, x2) + +inst_601:// fs1 == 1 and fe1 == 0x19 and fm1 == 0x22e and fs2 == 1 and fe2 == 0x01 and fm2 == 0x1aa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xe62e; op2val:0x85aa; +valaddr_reg:x3; val_offset:1152*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1152*FLEN/8, x7, x1, x2) + +inst_602:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x1aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x109 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x85aa; op2val:0x8109; +valaddr_reg:x3; val_offset:1154*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1154*FLEN/8, x7, x1, x2) + +inst_603:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x038 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf038; op2val:0xf0; +valaddr_reg:x3; val_offset:1156*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1156*FLEN/8, x7, x1, x2) + +inst_604:// fs1 == 1 and fe1 == 0x12 and fm1 == 0x052 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xc852; op2val:0xf0; +valaddr_reg:x3; val_offset:1158*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1158*FLEN/8, x7, x1, x2) + +inst_605:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x052 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xc852; +valaddr_reg:x3; val_offset:1160*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1160*FLEN/8, x7, x1, x2) + +inst_606:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x038 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x052 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf038; op2val:0xc852; +valaddr_reg:x3; val_offset:1162*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1162*FLEN/8, x7, x1, x2) + +inst_607:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17b and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x17b; op2val:0x739c; +valaddr_reg:x3; val_offset:1164*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1164*FLEN/8, x7, x1, x2) + +inst_608:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x184 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7584; op2val:0x739c; +valaddr_reg:x3; val_offset:1166*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1166*FLEN/8, x7, x1, x2) + +inst_609:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17b and fs2 == 0 and fe2 == 0x1d and fm2 == 0x184 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x17b; op2val:0x7584; +valaddr_reg:x3; val_offset:1168*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1168*FLEN/8, x7, x1, x2) + +inst_610:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x17b; op2val:0x17b; +valaddr_reg:x3; val_offset:1170*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1170*FLEN/8, x7, x1, x2) + +inst_611:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x100 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x17b; op2val:0x7900; +valaddr_reg:x3; val_offset:1172*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1172*FLEN/8, x7, x1, x2) + +inst_612:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x184 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x100 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7584; op2val:0x7900; +valaddr_reg:x3; val_offset:1174*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1174*FLEN/8, x7, x1, x2) + +inst_613:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17b and fs2 == 0 and fe2 == 0x1d and fm2 == 0x025 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x17b; op2val:0x7425; +valaddr_reg:x3; val_offset:1176*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1176*FLEN/8, x7, x1, x2) + +inst_614:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x184 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x025 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7584; op2val:0x7425; +valaddr_reg:x3; val_offset:1178*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1178*FLEN/8, x7, x1, x2) + +inst_615:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x17b; op2val:0x7ab0; +valaddr_reg:x3; val_offset:1180*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1180*FLEN/8, x7, x1, x2) + +inst_616:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x184 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7584; op2val:0x7ab0; +valaddr_reg:x3; val_offset:1182*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1182*FLEN/8, x7, x1, x2) + +inst_617:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x17b; op2val:0x7913; +valaddr_reg:x3; val_offset:1184*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1184*FLEN/8, x7, x1, x2) + +inst_618:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x184 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7584; op2val:0x7913; +valaddr_reg:x3; val_offset:1186*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1186*FLEN/8, x7, x1, x2) + +inst_619:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17b and fs2 == 1 and fe2 == 0x1d and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x17b; op2val:0xf749; +valaddr_reg:x3; val_offset:1188*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1188*FLEN/8, x7, x1, x2) + +inst_620:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x184 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7584; op2val:0xf749; +valaddr_reg:x3; val_offset:1190*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1190*FLEN/8, x7, x1, x2) + +inst_621:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x378 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x17b; op2val:0xfb78; +valaddr_reg:x3; val_offset:1192*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1192*FLEN/8, x7, x1, x2) + +inst_622:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x184 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x378 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7584; op2val:0xfb78; +valaddr_reg:x3; val_offset:1194*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1194*FLEN/8, x7, x1, x2) + +inst_623:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x21f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x17b; op2val:0xfa1f; +valaddr_reg:x3; val_offset:1196*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1196*FLEN/8, x7, x1, x2) + +inst_624:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x184 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x21f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7584; op2val:0xfa1f; +valaddr_reg:x3; val_offset:1198*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1198*FLEN/8, x7, x1, x2) + +inst_625:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x17b; op2val:0xf82f; +valaddr_reg:x3; val_offset:1200*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1200*FLEN/8, x7, x1, x2) + +inst_626:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x184 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7584; op2val:0xf82f; +valaddr_reg:x3; val_offset:1202*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1202*FLEN/8, x7, x1, x2) + +inst_627:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17b and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x17b; op2val:0xf038; +valaddr_reg:x3; val_offset:1204*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1204*FLEN/8, x7, x1, x2) + +inst_628:// fs1 == 0 and fe1 == 0x1a and fm1 == 0x069 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x6869; op2val:0xf038; +valaddr_reg:x3; val_offset:1206*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1206*FLEN/8, x7, x1, x2) + +inst_629:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17b and fs2 == 0 and fe2 == 0x1a and fm2 == 0x069 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x17b; op2val:0x6869; +valaddr_reg:x3; val_offset:1208*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1208*FLEN/8, x7, x1, x2) + +inst_630:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x17b; op2val:0xe; +valaddr_reg:x3; val_offset:1210*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1210*FLEN/8, x7, x1, x2) + +inst_631:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x003 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1a6 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3; op2val:0x5a6; +valaddr_reg:x3; val_offset:1212*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1212*FLEN/8, x7, x1, x2) + +inst_632:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x1a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x003 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x5a6; op2val:0x3; +valaddr_reg:x3; val_offset:1214*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1214*FLEN/8, x7, x1, x2) + +inst_633:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x003 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3; op2val:0xe; +valaddr_reg:x3; val_offset:1216*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1216*FLEN/8, x7, x1, x2) + +inst_634:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x003 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x17b; op2val:0x3; +valaddr_reg:x3; val_offset:1218*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1218*FLEN/8, x7, x1, x2) + +inst_635:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x17b; op2val:0x3fa; +valaddr_reg:x3; val_offset:1220*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1220*FLEN/8, x7, x1, x2) + +inst_636:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fa; op2val:0x17b; +valaddr_reg:x3; val_offset:1222*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1222*FLEN/8, x7, x1, x2) + +inst_637:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x17b; op2val:0x28e; +valaddr_reg:x3; val_offset:1224*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1224*FLEN/8, x7, x1, x2) + +inst_638:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x28e; op2val:0x17b; +valaddr_reg:x3; val_offset:1226*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1226*FLEN/8, x7, x1, x2) + +inst_639:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x17b; op2val:0x217; +valaddr_reg:x3; val_offset:1228*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1228*FLEN/8, x7, x1, x2) + +inst_640:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x217; op2val:0x17b; +valaddr_reg:x3; val_offset:1230*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1230*FLEN/8, x7, x1, x2) + +inst_641:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x195 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x17b; op2val:0x8195; +valaddr_reg:x3; val_offset:1232*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1232*FLEN/8, x7, x1, x2) + +inst_642:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x195 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17b and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8195; op2val:0x17b; +valaddr_reg:x3; val_offset:1234*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1234*FLEN/8, x7, x1, x2) + +inst_643:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x17b; op2val:0x80a7; +valaddr_reg:x3; val_offset:1236*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1236*FLEN/8, x7, x1, x2) + +inst_644:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x025 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x287 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x25; op2val:0x8687; +valaddr_reg:x3; val_offset:1238*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1238*FLEN/8, x7, x1, x2) + +inst_645:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x287 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x025 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8687; op2val:0x25; +valaddr_reg:x3; val_offset:1240*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1240*FLEN/8, x7, x1, x2) + +inst_646:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x025 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x25; op2val:0x80a7; +valaddr_reg:x3; val_offset:1242*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1242*FLEN/8, x7, x1, x2) + +inst_647:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x025 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x17b; op2val:0x25; +valaddr_reg:x3; val_offset:1244*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1244*FLEN/8, x7, x1, x2) + +inst_648:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x17b; op2val:0x821e; +valaddr_reg:x3; val_offset:1246*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1246*FLEN/8, x7, x1, x2) + +inst_649:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17b and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x821e; op2val:0x17b; +valaddr_reg:x3; val_offset:1248*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1248*FLEN/8, x7, x1, x2) + +inst_650:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x17b; op2val:0x8365; +valaddr_reg:x3; val_offset:1250*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1250*FLEN/8, x7, x1, x2) + +inst_651:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17b and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8365; op2val:0x17b; +valaddr_reg:x3; val_offset:1252*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1252*FLEN/8, x7, x1, x2) + +inst_652:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x109 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x17b; op2val:0x8109; +valaddr_reg:x3; val_offset:1254*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1254*FLEN/8, x7, x1, x2) + +inst_653:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x109 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17b and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8109; op2val:0x17b; +valaddr_reg:x3; val_offset:1256*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1256*FLEN/8, x7, x1, x2) + +inst_654:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x17b; op2val:0xf0; +valaddr_reg:x3; val_offset:1258*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1258*FLEN/8, x7, x1, x2) + +inst_655:// fs1 == 0 and fe1 == 0x10 and fm1 == 0x084 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x4084; op2val:0xf0; +valaddr_reg:x3; val_offset:1260*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1260*FLEN/8, x7, x1, x2) + +inst_656:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x084 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x4084; +valaddr_reg:x3; val_offset:1262*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1262*FLEN/8, x7, x1, x2) + +inst_657:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x084 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x17b; op2val:0x4084; +valaddr_reg:x3; val_offset:1264*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1264*FLEN/8, x7, x1, x2) + +inst_658:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xe; op2val:0x739c; +valaddr_reg:x3; val_offset:1266*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1266*FLEN/8, x7, x1, x2) + +inst_659:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x739c; +valaddr_reg:x3; val_offset:1268*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1268*FLEN/8, x7, x1, x2) + +inst_660:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xe; op2val:0x7bff; +valaddr_reg:x3; val_offset:1270*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1270*FLEN/8, x7, x1, x2) + +inst_661:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xe; op2val:0xe; +valaddr_reg:x3; val_offset:1272*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1272*FLEN/8, x7, x1, x2) + +inst_662:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x100 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xe; op2val:0x7900; +valaddr_reg:x3; val_offset:1274*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1274*FLEN/8, x7, x1, x2) + +inst_663:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x100 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7900; +valaddr_reg:x3; val_offset:1276*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1276*FLEN/8, x7, x1, x2) + +inst_664:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x025 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xe; op2val:0x7425; +valaddr_reg:x3; val_offset:1278*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1278*FLEN/8, x7, x1, x2) + +inst_665:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1d and fm2 == 0x025 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7425; +valaddr_reg:x3; val_offset:1280*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1280*FLEN/8, x7, x1, x2) + +inst_666:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xe; op2val:0x7ab0; +valaddr_reg:x3; val_offset:1282*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1282*FLEN/8, x7, x1, x2) + +inst_667:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7ab0; +valaddr_reg:x3; val_offset:1284*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1284*FLEN/8, x7, x1, x2) + +inst_668:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xe; op2val:0x7913; +valaddr_reg:x3; val_offset:1286*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1286*FLEN/8, x7, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_5) + +inst_669:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7913; +valaddr_reg:x3; val_offset:1288*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1288*FLEN/8, x7, x1, x2) + +inst_670:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 1 and fe2 == 0x1d and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xe; op2val:0xf749; +valaddr_reg:x3; val_offset:1290*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1290*FLEN/8, x7, x1, x2) + +inst_671:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1d and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xf749; +valaddr_reg:x3; val_offset:1292*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1292*FLEN/8, x7, x1, x2) + +inst_672:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x378 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xe; op2val:0xfb78; +valaddr_reg:x3; val_offset:1294*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1294*FLEN/8, x7, x1, x2) + +inst_673:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x378 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xfb78; +valaddr_reg:x3; val_offset:1296*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1296*FLEN/8, x7, x1, x2) + +inst_674:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x21f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xe; op2val:0xfa1f; +valaddr_reg:x3; val_offset:1298*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1298*FLEN/8, x7, x1, x2) + +inst_675:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x21f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xfa1f; +valaddr_reg:x3; val_offset:1300*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1300*FLEN/8, x7, x1, x2) + +inst_676:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xe; op2val:0xf82f; +valaddr_reg:x3; val_offset:1302*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1302*FLEN/8, x7, x1, x2) + +inst_677:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xf82f; +valaddr_reg:x3; val_offset:1304*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1304*FLEN/8, x7, x1, x2) + +inst_678:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xe; op2val:0xf038; +valaddr_reg:x3; val_offset:1306*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1306*FLEN/8, x7, x1, x2) + +inst_679:// fs1 == 0 and fe1 == 0x1c and fm1 == 0x035 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7035; op2val:0xf038; +valaddr_reg:x3; val_offset:1308*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1308*FLEN/8, x7, x1, x2) + +inst_680:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 0 and fe2 == 0x1c and fm2 == 0x035 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xe; op2val:0x7035; +valaddr_reg:x3; val_offset:1310*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1310*FLEN/8, x7, x1, x2) + +inst_681:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xe; op2val:0x17b; +valaddr_reg:x3; val_offset:1312*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1312*FLEN/8, x7, x1, x2) + +inst_682:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x1a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x5a6; op2val:0x17b; +valaddr_reg:x3; val_offset:1314*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1314*FLEN/8, x7, x1, x2) + +inst_683:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1a6 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xe; op2val:0x5a6; +valaddr_reg:x3; val_offset:1316*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1316*FLEN/8, x7, x1, x2) + +inst_684:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xe; op2val:0x3fa; +valaddr_reg:x3; val_offset:1318*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1318*FLEN/8, x7, x1, x2) + +inst_685:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x1a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x5a6; op2val:0xa; +valaddr_reg:x3; val_offset:1320*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1320*FLEN/8, x7, x1, x2) + +inst_686:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1a6 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xa; op2val:0x5a6; +valaddr_reg:x3; val_offset:1322*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1322*FLEN/8, x7, x1, x2) + +inst_687:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x1a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x5a6; op2val:0x3fa; +valaddr_reg:x3; val_offset:1324*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1324*FLEN/8, x7, x1, x2) + +inst_688:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xe; op2val:0x28e; +valaddr_reg:x3; val_offset:1326*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1326*FLEN/8, x7, x1, x2) + +inst_689:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x1a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x006 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x5a6; op2val:0x6; +valaddr_reg:x3; val_offset:1328*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1328*FLEN/8, x7, x1, x2) + +inst_690:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x006 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1a6 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x6; op2val:0x5a6; +valaddr_reg:x3; val_offset:1330*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1330*FLEN/8, x7, x1, x2) + +inst_691:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x1a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x5a6; op2val:0x28e; +valaddr_reg:x3; val_offset:1332*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1332*FLEN/8, x7, x1, x2) + +inst_692:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xe; op2val:0x217; +valaddr_reg:x3; val_offset:1334*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1334*FLEN/8, x7, x1, x2) + +inst_693:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x1a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x005 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x5a6; op2val:0x5; +valaddr_reg:x3; val_offset:1336*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1336*FLEN/8, x7, x1, x2) + +inst_694:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x005 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1a6 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x5; op2val:0x5a6; +valaddr_reg:x3; val_offset:1338*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1338*FLEN/8, x7, x1, x2) + +inst_695:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x1a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x5a6; op2val:0x217; +valaddr_reg:x3; val_offset:1340*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1340*FLEN/8, x7, x1, x2) + +inst_696:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x195 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xe; op2val:0x8195; +valaddr_reg:x3; val_offset:1342*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1342*FLEN/8, x7, x1, x2) + +inst_697:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x1a6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x004 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x5a6; op2val:0x8004; +valaddr_reg:x3; val_offset:1344*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1344*FLEN/8, x7, x1, x2) + +inst_698:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x004 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1a6 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8004; op2val:0x5a6; +valaddr_reg:x3; val_offset:1346*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1346*FLEN/8, x7, x1, x2) + +inst_699:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x1a6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x195 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x5a6; op2val:0x8195; +valaddr_reg:x3; val_offset:1348*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1348*FLEN/8, x7, x1, x2) + +inst_700:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xe; op2val:0x80a7; +valaddr_reg:x3; val_offset:1350*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1350*FLEN/8, x7, x1, x2) + +inst_701:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x090 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x010 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x90; op2val:0x8010; +valaddr_reg:x3; val_offset:1352*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1352*FLEN/8, x7, x1, x2) + +inst_702:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x010 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x090 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8010; op2val:0x90; +valaddr_reg:x3; val_offset:1354*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1354*FLEN/8, x7, x1, x2) + +inst_703:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x090 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x90; op2val:0x80a7; +valaddr_reg:x3; val_offset:1356*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1356*FLEN/8, x7, x1, x2) + +inst_704:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x090 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xe; op2val:0x90; +valaddr_reg:x3; val_offset:1358*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1358*FLEN/8, x7, x1, x2) + +inst_705:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xe; op2val:0x821e; +valaddr_reg:x3; val_offset:1360*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1360*FLEN/8, x7, x1, x2) + +inst_706:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x1a6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x005 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x5a6; op2val:0x8005; +valaddr_reg:x3; val_offset:1362*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1362*FLEN/8, x7, x1, x2) + +inst_707:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x005 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1a6 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8005; op2val:0x5a6; +valaddr_reg:x3; val_offset:1364*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1364*FLEN/8, x7, x1, x2) + +inst_708:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x1a6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x5a6; op2val:0x821e; +valaddr_reg:x3; val_offset:1366*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1366*FLEN/8, x7, x1, x2) + +inst_709:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xe; op2val:0x8365; +valaddr_reg:x3; val_offset:1368*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1368*FLEN/8, x7, x1, x2) + +inst_710:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x1a6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x008 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x5a6; op2val:0x8008; +valaddr_reg:x3; val_offset:1370*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1370*FLEN/8, x7, x1, x2) + +inst_711:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x008 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1a6 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8008; op2val:0x5a6; +valaddr_reg:x3; val_offset:1372*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1372*FLEN/8, x7, x1, x2) + +inst_712:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x1a6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x5a6; op2val:0x8365; +valaddr_reg:x3; val_offset:1374*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1374*FLEN/8, x7, x1, x2) + +inst_713:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x109 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xe; op2val:0x8109; +valaddr_reg:x3; val_offset:1376*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1376*FLEN/8, x7, x1, x2) + +inst_714:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x1a6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x5a6; op2val:0x8002; +valaddr_reg:x3; val_offset:1378*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1378*FLEN/8, x7, x1, x2) + +inst_715:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1a6 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8002; op2val:0x5a6; +valaddr_reg:x3; val_offset:1380*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1380*FLEN/8, x7, x1, x2) + +inst_716:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x1a6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x109 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x5a6; op2val:0x8109; +valaddr_reg:x3; val_offset:1382*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1382*FLEN/8, x7, x1, x2) + +inst_717:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xe; op2val:0xf0; +valaddr_reg:x3; val_offset:1384*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1384*FLEN/8, x7, x1, x2) + +inst_718:// fs1 == 0 and fe1 == 0x12 and fm1 == 0x04f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x484f; op2val:0xf0; +valaddr_reg:x3; val_offset:1386*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1386*FLEN/8, x7, x1, x2) + +inst_719:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x04f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x484f; +valaddr_reg:x3; val_offset:1388*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1388*FLEN/8, x7, x1, x2) + +inst_720:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 0 and fe2 == 0x12 and fm2 == 0x04f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xe; op2val:0x484f; +valaddr_reg:x3; val_offset:1390*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1390*FLEN/8, x7, x1, x2) + +inst_721:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fa and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fa; op2val:0x739c; +valaddr_reg:x3; val_offset:1392*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1392*FLEN/8, x7, x1, x2) + +inst_722:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x369 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b69; op2val:0x739c; +valaddr_reg:x3; val_offset:1394*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1394*FLEN/8, x7, x1, x2) + +inst_723:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fa and fs2 == 0 and fe2 == 0x1e and fm2 == 0x369 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fa; op2val:0x7b69; +valaddr_reg:x3; val_offset:1396*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1396*FLEN/8, x7, x1, x2) + +inst_724:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fa; op2val:0x3fa; +valaddr_reg:x3; val_offset:1398*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1398*FLEN/8, x7, x1, x2) + +inst_725:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fa and fs2 == 0 and fe2 == 0x1e and fm2 == 0x100 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fa; op2val:0x7900; +valaddr_reg:x3; val_offset:1400*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1400*FLEN/8, x7, x1, x2) + +inst_726:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x369 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x100 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b69; op2val:0x7900; +valaddr_reg:x3; val_offset:1402*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1402*FLEN/8, x7, x1, x2) + +inst_727:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fa and fs2 == 0 and fe2 == 0x1d and fm2 == 0x025 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fa; op2val:0x7425; +valaddr_reg:x3; val_offset:1404*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1404*FLEN/8, x7, x1, x2) + +inst_728:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x369 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x025 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b69; op2val:0x7425; +valaddr_reg:x3; val_offset:1406*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1406*FLEN/8, x7, x1, x2) + +inst_729:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fa and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fa; op2val:0x7ab0; +valaddr_reg:x3; val_offset:1408*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1408*FLEN/8, x7, x1, x2) + +inst_730:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x369 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b69; op2val:0x7ab0; +valaddr_reg:x3; val_offset:1410*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1410*FLEN/8, x7, x1, x2) + +inst_731:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fa and fs2 == 0 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fa; op2val:0x7913; +valaddr_reg:x3; val_offset:1412*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1412*FLEN/8, x7, x1, x2) + +inst_732:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x369 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b69; op2val:0x7913; +valaddr_reg:x3; val_offset:1414*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1414*FLEN/8, x7, x1, x2) + +inst_733:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fa and fs2 == 1 and fe2 == 0x1d and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fa; op2val:0xf749; +valaddr_reg:x3; val_offset:1416*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1416*FLEN/8, x7, x1, x2) + +inst_734:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x369 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b69; op2val:0xf749; +valaddr_reg:x3; val_offset:1418*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1418*FLEN/8, x7, x1, x2) + +inst_735:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fa and fs2 == 1 and fe2 == 0x1e and fm2 == 0x378 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fa; op2val:0xfb78; +valaddr_reg:x3; val_offset:1420*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1420*FLEN/8, x7, x1, x2) + +inst_736:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x369 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x378 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b69; op2val:0xfb78; +valaddr_reg:x3; val_offset:1422*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1422*FLEN/8, x7, x1, x2) + +inst_737:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fa and fs2 == 1 and fe2 == 0x1e and fm2 == 0x21f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fa; op2val:0xfa1f; +valaddr_reg:x3; val_offset:1424*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1424*FLEN/8, x7, x1, x2) + +inst_738:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x369 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x21f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b69; op2val:0xfa1f; +valaddr_reg:x3; val_offset:1426*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1426*FLEN/8, x7, x1, x2) + +inst_739:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fa and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fa; op2val:0xf82f; +valaddr_reg:x3; val_offset:1428*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1428*FLEN/8, x7, x1, x2) + +inst_740:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x369 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b69; op2val:0xf82f; +valaddr_reg:x3; val_offset:1430*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1430*FLEN/8, x7, x1, x2) + +inst_741:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fa and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fa; op2val:0xf038; +valaddr_reg:x3; val_offset:1432*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1432*FLEN/8, x7, x1, x2) + +inst_742:// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ed and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ded; op2val:0xf038; +valaddr_reg:x3; val_offset:1434*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1434*FLEN/8, x7, x1, x2) + +inst_743:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fa and fs2 == 0 and fe2 == 0x1b and fm2 == 0x1ed and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fa; op2val:0x6ded; +valaddr_reg:x3; val_offset:1436*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1436*FLEN/8, x7, x1, x2) + +inst_744:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fa; op2val:0xe; +valaddr_reg:x3; val_offset:1438*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1438*FLEN/8, x7, x1, x2) + +inst_745:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xa; op2val:0xe; +valaddr_reg:x3; val_offset:1440*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1440*FLEN/8, x7, x1, x2) + +inst_746:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fa; op2val:0xa; +valaddr_reg:x3; val_offset:1442*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1442*FLEN/8, x7, x1, x2) + +inst_747:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fa; op2val:0x28e; +valaddr_reg:x3; val_offset:1444*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1444*FLEN/8, x7, x1, x2) + +inst_748:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x28e; op2val:0x3fa; +valaddr_reg:x3; val_offset:1446*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1446*FLEN/8, x7, x1, x2) + +inst_749:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fa; op2val:0x217; +valaddr_reg:x3; val_offset:1448*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1448*FLEN/8, x7, x1, x2) + +inst_750:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x217; op2val:0x3fa; +valaddr_reg:x3; val_offset:1450*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1450*FLEN/8, x7, x1, x2) + +inst_751:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x195 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fa; op2val:0x8195; +valaddr_reg:x3; val_offset:1452*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1452*FLEN/8, x7, x1, x2) + +inst_752:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x195 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8195; op2val:0x3fa; +valaddr_reg:x3; val_offset:1454*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1454*FLEN/8, x7, x1, x2) + +inst_753:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fa; op2val:0x80a7; +valaddr_reg:x3; val_offset:1456*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1456*FLEN/8, x7, x1, x2) + +inst_754:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x065 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x287 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x65; op2val:0x8687; +valaddr_reg:x3; val_offset:1458*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1458*FLEN/8, x7, x1, x2) + +inst_755:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x287 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x065 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8687; op2val:0x65; +valaddr_reg:x3; val_offset:1460*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1460*FLEN/8, x7, x1, x2) + +inst_756:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x065 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x65; op2val:0x80a7; +valaddr_reg:x3; val_offset:1462*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1462*FLEN/8, x7, x1, x2) + +inst_757:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x065 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fa; op2val:0x65; +valaddr_reg:x3; val_offset:1464*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1464*FLEN/8, x7, x1, x2) + +inst_758:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fa; op2val:0x821e; +valaddr_reg:x3; val_offset:1466*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1466*FLEN/8, x7, x1, x2) + +inst_759:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x821e; op2val:0x3fa; +valaddr_reg:x3; val_offset:1468*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1468*FLEN/8, x7, x1, x2) + +inst_760:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fa; op2val:0x8365; +valaddr_reg:x3; val_offset:1470*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1470*FLEN/8, x7, x1, x2) + +inst_761:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8365; op2val:0x3fa; +valaddr_reg:x3; val_offset:1472*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1472*FLEN/8, x7, x1, x2) + +inst_762:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x109 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fa; op2val:0x8109; +valaddr_reg:x3; val_offset:1474*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1474*FLEN/8, x7, x1, x2) + +inst_763:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x109 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8109; op2val:0x3fa; +valaddr_reg:x3; val_offset:1476*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1476*FLEN/8, x7, x1, x2) + +inst_764:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fa; op2val:0xf0; +valaddr_reg:x3; val_offset:1478*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1478*FLEN/8, x7, x1, x2) + +inst_765:// fs1 == 0 and fe1 == 0x11 and fm1 == 0x212 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x4612; op2val:0xf0; +valaddr_reg:x3; val_offset:1480*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1480*FLEN/8, x7, x1, x2) + +inst_766:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x212 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x4612; +valaddr_reg:x3; val_offset:1482*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1482*FLEN/8, x7, x1, x2) + +inst_767:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fa and fs2 == 0 and fe2 == 0x11 and fm2 == 0x212 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fa; op2val:0x4612; +valaddr_reg:x3; val_offset:1484*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1484*FLEN/8, x7, x1, x2) + +inst_768:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x28e; op2val:0x739c; +valaddr_reg:x3; val_offset:1486*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1486*FLEN/8, x7, x1, x2) + +inst_769:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x78c2; op2val:0x739c; +valaddr_reg:x3; val_offset:1488*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1488*FLEN/8, x7, x1, x2) + +inst_770:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0c2 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x28e; op2val:0x78c2; +valaddr_reg:x3; val_offset:1490*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1490*FLEN/8, x7, x1, x2) + +inst_771:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x28e; op2val:0x28e; +valaddr_reg:x3; val_offset:1492*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1492*FLEN/8, x7, x1, x2) + +inst_772:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x100 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x28e; op2val:0x7900; +valaddr_reg:x3; val_offset:1494*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1494*FLEN/8, x7, x1, x2) + +inst_773:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x100 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x78c2; op2val:0x7900; +valaddr_reg:x3; val_offset:1496*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1496*FLEN/8, x7, x1, x2) + +inst_774:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x025 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x28e; op2val:0x7425; +valaddr_reg:x3; val_offset:1498*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1498*FLEN/8, x7, x1, x2) + +inst_775:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x025 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x78c2; op2val:0x7425; +valaddr_reg:x3; val_offset:1500*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1500*FLEN/8, x7, x1, x2) + +inst_776:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x28e; op2val:0x7ab0; +valaddr_reg:x3; val_offset:1502*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1502*FLEN/8, x7, x1, x2) + +inst_777:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x78c2; op2val:0x7ab0; +valaddr_reg:x3; val_offset:1504*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1504*FLEN/8, x7, x1, x2) + +inst_778:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x28e; op2val:0x7913; +valaddr_reg:x3; val_offset:1506*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1506*FLEN/8, x7, x1, x2) + +inst_779:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x78c2; op2val:0x7913; +valaddr_reg:x3; val_offset:1508*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1508*FLEN/8, x7, x1, x2) + +inst_780:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e and fs2 == 1 and fe2 == 0x1d and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x28e; op2val:0xf749; +valaddr_reg:x3; val_offset:1510*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1510*FLEN/8, x7, x1, x2) + +inst_781:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x78c2; op2val:0xf749; +valaddr_reg:x3; val_offset:1512*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1512*FLEN/8, x7, x1, x2) + +inst_782:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x378 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x28e; op2val:0xfb78; +valaddr_reg:x3; val_offset:1514*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1514*FLEN/8, x7, x1, x2) + +inst_783:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x378 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x78c2; op2val:0xfb78; +valaddr_reg:x3; val_offset:1516*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1516*FLEN/8, x7, x1, x2) + +inst_784:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x21f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x28e; op2val:0xfa1f; +valaddr_reg:x3; val_offset:1518*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1518*FLEN/8, x7, x1, x2) + +inst_785:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x21f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x78c2; op2val:0xfa1f; +valaddr_reg:x3; val_offset:1520*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1520*FLEN/8, x7, x1, x2) + +inst_786:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x28e; op2val:0xf82f; +valaddr_reg:x3; val_offset:1522*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1522*FLEN/8, x7, x1, x2) + +inst_787:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x78c2; op2val:0xf82f; +valaddr_reg:x3; val_offset:1524*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1524*FLEN/8, x7, x1, x2) + +inst_788:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x28e; op2val:0xf038; +valaddr_reg:x3; val_offset:1526*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1526*FLEN/8, x7, x1, x2) + +inst_789:// fs1 == 0 and fe1 == 0x1a and fm1 == 0x39d and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x6b9d; op2val:0xf038; +valaddr_reg:x3; val_offset:1528*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1528*FLEN/8, x7, x1, x2) + +inst_790:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e and fs2 == 0 and fe2 == 0x1a and fm2 == 0x39d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x28e; op2val:0x6b9d; +valaddr_reg:x3; val_offset:1530*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1530*FLEN/8, x7, x1, x2) + +inst_791:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x28e; op2val:0xe; +valaddr_reg:x3; val_offset:1532*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1532*FLEN/8, x7, x1, x2) + +inst_792:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x006 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x28e; op2val:0x6; +valaddr_reg:x3; val_offset:1534*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1534*FLEN/8, x7, x1, x2) + +inst_793:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x28e; op2val:0x217; +valaddr_reg:x3; val_offset:1536*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1536*FLEN/8, x7, x1, x2) + +inst_794:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x217; op2val:0x28e; +valaddr_reg:x3; val_offset:1538*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1538*FLEN/8, x7, x1, x2) + +inst_795:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x195 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x28e; op2val:0x8195; +valaddr_reg:x3; val_offset:1540*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1540*FLEN/8, x7, x1, x2) + +inst_796:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x195 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8195; op2val:0x28e; +valaddr_reg:x3; val_offset:1542*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1542*FLEN/8, x7, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_6) + +inst_797:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x28e; op2val:0x80a7; +valaddr_reg:x3; val_offset:1544*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1544*FLEN/8, x7, x1, x2) + +inst_798:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x041 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x287 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x41; op2val:0x8687; +valaddr_reg:x3; val_offset:1546*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1546*FLEN/8, x7, x1, x2) + +inst_799:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x287 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x041 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8687; op2val:0x41; +valaddr_reg:x3; val_offset:1548*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1548*FLEN/8, x7, x1, x2) + +inst_800:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x041 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x41; op2val:0x80a7; +valaddr_reg:x3; val_offset:1550*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1550*FLEN/8, x7, x1, x2) + +inst_801:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x041 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x28e; op2val:0x41; +valaddr_reg:x3; val_offset:1552*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1552*FLEN/8, x7, x1, x2) + +inst_802:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x28e; op2val:0x821e; +valaddr_reg:x3; val_offset:1554*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1554*FLEN/8, x7, x1, x2) + +inst_803:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x821e; op2val:0x28e; +valaddr_reg:x3; val_offset:1556*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1556*FLEN/8, x7, x1, x2) + +inst_804:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x28e; op2val:0x8365; +valaddr_reg:x3; val_offset:1558*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1558*FLEN/8, x7, x1, x2) + +inst_805:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8365; op2val:0x28e; +valaddr_reg:x3; val_offset:1560*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1560*FLEN/8, x7, x1, x2) + +inst_806:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x109 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x28e; op2val:0x8109; +valaddr_reg:x3; val_offset:1562*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1562*FLEN/8, x7, x1, x2) + +inst_807:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x109 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8109; op2val:0x28e; +valaddr_reg:x3; val_offset:1564*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1564*FLEN/8, x7, x1, x2) + +inst_808:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x28e; op2val:0xf0; +valaddr_reg:x3; val_offset:1566*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1566*FLEN/8, x7, x1, x2) + +inst_809:// fs1 == 0 and fe1 == 0x10 and fm1 == 0x3cc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x43cc; op2val:0xf0; +valaddr_reg:x3; val_offset:1568*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1568*FLEN/8, x7, x1, x2) + +inst_810:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3cc and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x43cc; +valaddr_reg:x3; val_offset:1570*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1570*FLEN/8, x7, x1, x2) + +inst_811:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3cc and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x28e; op2val:0x43cc; +valaddr_reg:x3; val_offset:1572*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1572*FLEN/8, x7, x1, x2) + +inst_812:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x217; op2val:0x739c; +valaddr_reg:x3; val_offset:1574*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1574*FLEN/8, x7, x1, x2) + +inst_813:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3cb and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x77cb; op2val:0x739c; +valaddr_reg:x3; val_offset:1576*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1576*FLEN/8, x7, x1, x2) + +inst_814:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3cb and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x217; op2val:0x77cb; +valaddr_reg:x3; val_offset:1578*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1578*FLEN/8, x7, x1, x2) + +inst_815:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x217; op2val:0x217; +valaddr_reg:x3; val_offset:1580*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1580*FLEN/8, x7, x1, x2) + +inst_816:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x100 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x217; op2val:0x7900; +valaddr_reg:x3; val_offset:1582*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1582*FLEN/8, x7, x1, x2) + +inst_817:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3cb and fs2 == 0 and fe2 == 0x1e and fm2 == 0x100 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x77cb; op2val:0x7900; +valaddr_reg:x3; val_offset:1584*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1584*FLEN/8, x7, x1, x2) + +inst_818:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x025 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x217; op2val:0x7425; +valaddr_reg:x3; val_offset:1586*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1586*FLEN/8, x7, x1, x2) + +inst_819:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3cb and fs2 == 0 and fe2 == 0x1d and fm2 == 0x025 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x77cb; op2val:0x7425; +valaddr_reg:x3; val_offset:1588*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1588*FLEN/8, x7, x1, x2) + +inst_820:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x217; op2val:0x7ab0; +valaddr_reg:x3; val_offset:1590*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1590*FLEN/8, x7, x1, x2) + +inst_821:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3cb and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x77cb; op2val:0x7ab0; +valaddr_reg:x3; val_offset:1592*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1592*FLEN/8, x7, x1, x2) + +inst_822:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x217; op2val:0x7913; +valaddr_reg:x3; val_offset:1594*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1594*FLEN/8, x7, x1, x2) + +inst_823:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3cb and fs2 == 0 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x77cb; op2val:0x7913; +valaddr_reg:x3; val_offset:1596*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1596*FLEN/8, x7, x1, x2) + +inst_824:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x217; op2val:0xf749; +valaddr_reg:x3; val_offset:1598*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1598*FLEN/8, x7, x1, x2) + +inst_825:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3cb and fs2 == 1 and fe2 == 0x1d and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x77cb; op2val:0xf749; +valaddr_reg:x3; val_offset:1600*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1600*FLEN/8, x7, x1, x2) + +inst_826:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x378 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x217; op2val:0xfb78; +valaddr_reg:x3; val_offset:1602*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1602*FLEN/8, x7, x1, x2) + +inst_827:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3cb and fs2 == 1 and fe2 == 0x1e and fm2 == 0x378 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x77cb; op2val:0xfb78; +valaddr_reg:x3; val_offset:1604*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1604*FLEN/8, x7, x1, x2) + +inst_828:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x21f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x217; op2val:0xfa1f; +valaddr_reg:x3; val_offset:1606*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1606*FLEN/8, x7, x1, x2) + +inst_829:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3cb and fs2 == 1 and fe2 == 0x1e and fm2 == 0x21f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x77cb; op2val:0xfa1f; +valaddr_reg:x3; val_offset:1608*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1608*FLEN/8, x7, x1, x2) + +inst_830:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x217; op2val:0xf82f; +valaddr_reg:x3; val_offset:1610*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1610*FLEN/8, x7, x1, x2) + +inst_831:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3cb and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x77cb; op2val:0xf82f; +valaddr_reg:x3; val_offset:1612*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1612*FLEN/8, x7, x1, x2) + +inst_832:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x217; op2val:0xf038; +valaddr_reg:x3; val_offset:1614*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1614*FLEN/8, x7, x1, x2) + +inst_833:// fs1 == 0 and fe1 == 0x1a and fm1 == 0x23c and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x6a3c; op2val:0xf038; +valaddr_reg:x3; val_offset:1616*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1616*FLEN/8, x7, x1, x2) + +inst_834:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x23c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x217; op2val:0x6a3c; +valaddr_reg:x3; val_offset:1618*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1618*FLEN/8, x7, x1, x2) + +inst_835:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x217; op2val:0xe; +valaddr_reg:x3; val_offset:1620*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1620*FLEN/8, x7, x1, x2) + +inst_836:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x005 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x5; op2val:0xe; +valaddr_reg:x3; val_offset:1622*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1622*FLEN/8, x7, x1, x2) + +inst_837:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x005 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x217; op2val:0x5; +valaddr_reg:x3; val_offset:1624*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1624*FLEN/8, x7, x1, x2) + +inst_838:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x195 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x217; op2val:0x8195; +valaddr_reg:x3; val_offset:1626*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1626*FLEN/8, x7, x1, x2) + +inst_839:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x195 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8195; op2val:0x217; +valaddr_reg:x3; val_offset:1628*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1628*FLEN/8, x7, x1, x2) + +inst_840:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x217; op2val:0x80a7; +valaddr_reg:x3; val_offset:1630*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1630*FLEN/8, x7, x1, x2) + +inst_841:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x035 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x287 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x35; op2val:0x8687; +valaddr_reg:x3; val_offset:1632*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1632*FLEN/8, x7, x1, x2) + +inst_842:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x287 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x035 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8687; op2val:0x35; +valaddr_reg:x3; val_offset:1634*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1634*FLEN/8, x7, x1, x2) + +inst_843:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x035 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x35; op2val:0x80a7; +valaddr_reg:x3; val_offset:1636*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1636*FLEN/8, x7, x1, x2) + +inst_844:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x035 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x217; op2val:0x35; +valaddr_reg:x3; val_offset:1638*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1638*FLEN/8, x7, x1, x2) + +inst_845:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x217; op2val:0x821e; +valaddr_reg:x3; val_offset:1640*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1640*FLEN/8, x7, x1, x2) + +inst_846:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x821e; op2val:0x217; +valaddr_reg:x3; val_offset:1642*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1642*FLEN/8, x7, x1, x2) + +inst_847:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x217; op2val:0x8365; +valaddr_reg:x3; val_offset:1644*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1644*FLEN/8, x7, x1, x2) + +inst_848:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8365; op2val:0x217; +valaddr_reg:x3; val_offset:1646*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1646*FLEN/8, x7, x1, x2) + +inst_849:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x109 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x217; op2val:0x8109; +valaddr_reg:x3; val_offset:1648*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1648*FLEN/8, x7, x1, x2) + +inst_850:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x109 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8109; op2val:0x217; +valaddr_reg:x3; val_offset:1650*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1650*FLEN/8, x7, x1, x2) + +inst_851:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x217; op2val:0xf0; +valaddr_reg:x3; val_offset:1652*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1652*FLEN/8, x7, x1, x2) + +inst_852:// fs1 == 0 and fe1 == 0x10 and fm1 == 0x262 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x4262; op2val:0xf0; +valaddr_reg:x3; val_offset:1654*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1654*FLEN/8, x7, x1, x2) + +inst_853:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x262 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x4262; +valaddr_reg:x3; val_offset:1656*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1656*FLEN/8, x7, x1, x2) + +inst_854:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x262 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x217; op2val:0x4262; +valaddr_reg:x3; val_offset:1658*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1658*FLEN/8, x7, x1, x2) + +inst_855:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x195 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8195; op2val:0x739c; +valaddr_reg:x3; val_offset:1660*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1660*FLEN/8, x7, x1, x2) + +inst_856:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x1e7 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf5e7; op2val:0x739c; +valaddr_reg:x3; val_offset:1662*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1662*FLEN/8, x7, x1, x2) + +inst_857:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x195 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x1e7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8195; op2val:0xf5e7; +valaddr_reg:x3; val_offset:1664*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1664*FLEN/8, x7, x1, x2) + +inst_858:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x195 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x195 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8195; op2val:0x8195; +valaddr_reg:x3; val_offset:1666*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1666*FLEN/8, x7, x1, x2) + +inst_859:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x195 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x100 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8195; op2val:0x7900; +valaddr_reg:x3; val_offset:1668*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1668*FLEN/8, x7, x1, x2) + +inst_860:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x1e7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x100 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf5e7; op2val:0x7900; +valaddr_reg:x3; val_offset:1670*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1670*FLEN/8, x7, x1, x2) + +inst_861:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x195 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x025 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8195; op2val:0x7425; +valaddr_reg:x3; val_offset:1672*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1672*FLEN/8, x7, x1, x2) + +inst_862:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x1e7 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x025 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf5e7; op2val:0x7425; +valaddr_reg:x3; val_offset:1674*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1674*FLEN/8, x7, x1, x2) + +inst_863:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x195 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8195; op2val:0x7ab0; +valaddr_reg:x3; val_offset:1676*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1676*FLEN/8, x7, x1, x2) + +inst_864:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x1e7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf5e7; op2val:0x7ab0; +valaddr_reg:x3; val_offset:1678*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1678*FLEN/8, x7, x1, x2) + +inst_865:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x195 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8195; op2val:0x7913; +valaddr_reg:x3; val_offset:1680*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1680*FLEN/8, x7, x1, x2) + +inst_866:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x1e7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf5e7; op2val:0x7913; +valaddr_reg:x3; val_offset:1682*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1682*FLEN/8, x7, x1, x2) + +inst_867:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x195 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8195; op2val:0xf749; +valaddr_reg:x3; val_offset:1684*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1684*FLEN/8, x7, x1, x2) + +inst_868:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x1e7 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf5e7; op2val:0xf749; +valaddr_reg:x3; val_offset:1686*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1686*FLEN/8, x7, x1, x2) + +inst_869:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x195 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x378 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8195; op2val:0xfb78; +valaddr_reg:x3; val_offset:1688*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1688*FLEN/8, x7, x1, x2) + +inst_870:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x1e7 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x378 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf5e7; op2val:0xfb78; +valaddr_reg:x3; val_offset:1690*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1690*FLEN/8, x7, x1, x2) + +inst_871:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x195 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x21f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8195; op2val:0xfa1f; +valaddr_reg:x3; val_offset:1692*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1692*FLEN/8, x7, x1, x2) + +inst_872:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x1e7 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x21f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf5e7; op2val:0xfa1f; +valaddr_reg:x3; val_offset:1694*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1694*FLEN/8, x7, x1, x2) + +inst_873:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x195 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8195; op2val:0xf82f; +valaddr_reg:x3; val_offset:1696*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1696*FLEN/8, x7, x1, x2) + +inst_874:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x1e7 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf5e7; op2val:0xf82f; +valaddr_reg:x3; val_offset:1698*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1698*FLEN/8, x7, x1, x2) + +inst_875:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x195 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8195; op2val:0xf038; +valaddr_reg:x3; val_offset:1700*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1700*FLEN/8, x7, x1, x2) + +inst_876:// fs1 == 1 and fe1 == 0x1a and fm1 == 0x0b9 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xe8b9; op2val:0xf038; +valaddr_reg:x3; val_offset:1702*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1702*FLEN/8, x7, x1, x2) + +inst_877:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x195 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x0b9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8195; op2val:0xe8b9; +valaddr_reg:x3; val_offset:1704*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1704*FLEN/8, x7, x1, x2) + +inst_878:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x195 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8195; op2val:0xe; +valaddr_reg:x3; val_offset:1706*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1706*FLEN/8, x7, x1, x2) + +inst_879:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x004 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8004; op2val:0xe; +valaddr_reg:x3; val_offset:1708*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1708*FLEN/8, x7, x1, x2) + +inst_880:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x195 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x004 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8195; op2val:0x8004; +valaddr_reg:x3; val_offset:1710*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1710*FLEN/8, x7, x1, x2) + +inst_881:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x195 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8195; op2val:0x80a7; +valaddr_reg:x3; val_offset:1712*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1712*FLEN/8, x7, x1, x2) + +inst_882:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x028 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x287 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8028; op2val:0x8687; +valaddr_reg:x3; val_offset:1714*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1714*FLEN/8, x7, x1, x2) + +inst_883:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x287 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x028 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8687; op2val:0x8028; +valaddr_reg:x3; val_offset:1716*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1716*FLEN/8, x7, x1, x2) + +inst_884:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x028 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8028; op2val:0x80a7; +valaddr_reg:x3; val_offset:1718*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1718*FLEN/8, x7, x1, x2) + +inst_885:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x195 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x028 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8195; op2val:0x8028; +valaddr_reg:x3; val_offset:1720*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1720*FLEN/8, x7, x1, x2) + +inst_886:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x195 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8195; op2val:0x821e; +valaddr_reg:x3; val_offset:1722*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1722*FLEN/8, x7, x1, x2) + +inst_887:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x195 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x821e; op2val:0x8195; +valaddr_reg:x3; val_offset:1724*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1724*FLEN/8, x7, x1, x2) + +inst_888:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x195 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8195; op2val:0x8365; +valaddr_reg:x3; val_offset:1726*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1726*FLEN/8, x7, x1, x2) + +inst_889:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x195 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8365; op2val:0x8195; +valaddr_reg:x3; val_offset:1728*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1728*FLEN/8, x7, x1, x2) + +inst_890:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x195 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x109 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8195; op2val:0x8109; +valaddr_reg:x3; val_offset:1730*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1730*FLEN/8, x7, x1, x2) + +inst_891:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x109 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x195 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8109; op2val:0x8195; +valaddr_reg:x3; val_offset:1732*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1732*FLEN/8, x7, x1, x2) + +inst_892:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x195 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8195; op2val:0xf0; +valaddr_reg:x3; val_offset:1734*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1734*FLEN/8, x7, x1, x2) + +inst_893:// fs1 == 1 and fe1 == 0x10 and fm1 == 0x0d6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xc0d6; op2val:0xf0; +valaddr_reg:x3; val_offset:1736*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1736*FLEN/8, x7, x1, x2) + +inst_894:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0d6 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xc0d6; +valaddr_reg:x3; val_offset:1738*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1738*FLEN/8, x7, x1, x2) + +inst_895:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x195 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0d6 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8195; op2val:0xc0d6; +valaddr_reg:x3; val_offset:1740*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1740*FLEN/8, x7, x1, x2) + +inst_896:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a7 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x80a7; op2val:0x739c; +valaddr_reg:x3; val_offset:1742*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1742*FLEN/8, x7, x1, x2) + +inst_897:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a7 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x80a7; op2val:0xfbff; +valaddr_reg:x3; val_offset:1744*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1744*FLEN/8, x7, x1, x2) + +inst_898:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x80a7; op2val:0x80a7; +valaddr_reg:x3; val_offset:1746*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1746*FLEN/8, x7, x1, x2) + +inst_899:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x100 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x80a7; op2val:0x7900; +valaddr_reg:x3; val_offset:1748*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1748*FLEN/8, x7, x1, x2) + +inst_900:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a7 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x025 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x80a7; op2val:0x7425; +valaddr_reg:x3; val_offset:1750*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1750*FLEN/8, x7, x1, x2) + +inst_901:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x80a7; op2val:0x7ab0; +valaddr_reg:x3; val_offset:1752*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1752*FLEN/8, x7, x1, x2) + +inst_902:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x80a7; op2val:0x7913; +valaddr_reg:x3; val_offset:1754*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1754*FLEN/8, x7, x1, x2) + +inst_903:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a7 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x80a7; op2val:0xf749; +valaddr_reg:x3; val_offset:1756*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1756*FLEN/8, x7, x1, x2) + +inst_904:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a7 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x378 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x80a7; op2val:0xfb78; +valaddr_reg:x3; val_offset:1758*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1758*FLEN/8, x7, x1, x2) + +inst_905:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a7 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x21f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x80a7; op2val:0xfa1f; +valaddr_reg:x3; val_offset:1760*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1760*FLEN/8, x7, x1, x2) + +inst_906:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a7 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x80a7; op2val:0xf82f; +valaddr_reg:x3; val_offset:1762*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1762*FLEN/8, x7, x1, x2) + +inst_907:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a7 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x80a7; op2val:0xf038; +valaddr_reg:x3; val_offset:1764*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1764*FLEN/8, x7, x1, x2) + +inst_908:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x0dd and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0dd; op2val:0xf038; +valaddr_reg:x3; val_offset:1766*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1766*FLEN/8, x7, x1, x2) + +inst_909:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a7 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0dd and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x80a7; op2val:0xf0dd; +valaddr_reg:x3; val_offset:1768*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1768*FLEN/8, x7, x1, x2) + +inst_910:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17b and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x80a7; op2val:0x17b; +valaddr_reg:x3; val_offset:1770*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1770*FLEN/8, x7, x1, x2) + +inst_911:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x287 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17b and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8687; op2val:0x17b; +valaddr_reg:x3; val_offset:1772*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1772*FLEN/8, x7, x1, x2) + +inst_912:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a7 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x287 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x80a7; op2val:0x8687; +valaddr_reg:x3; val_offset:1774*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1774*FLEN/8, x7, x1, x2) + +inst_913:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x80a7; op2val:0xe; +valaddr_reg:x3; val_offset:1776*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1776*FLEN/8, x7, x1, x2) + +inst_914:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x010 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8010; op2val:0xe; +valaddr_reg:x3; val_offset:1778*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1778*FLEN/8, x7, x1, x2) + +inst_915:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x010 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x80a7; op2val:0x8010; +valaddr_reg:x3; val_offset:1780*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1780*FLEN/8, x7, x1, x2) + +inst_916:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x80a7; op2val:0x3fa; +valaddr_reg:x3; val_offset:1782*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1782*FLEN/8, x7, x1, x2) + +inst_917:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x287 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8687; op2val:0x3fa; +valaddr_reg:x3; val_offset:1784*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1784*FLEN/8, x7, x1, x2) + +inst_918:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x80a7; op2val:0x28e; +valaddr_reg:x3; val_offset:1786*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1786*FLEN/8, x7, x1, x2) + +inst_919:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x287 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8687; op2val:0x28e; +valaddr_reg:x3; val_offset:1788*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1788*FLEN/8, x7, x1, x2) + +inst_920:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x80a7; op2val:0x217; +valaddr_reg:x3; val_offset:1790*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1790*FLEN/8, x7, x1, x2) + +inst_921:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x287 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8687; op2val:0x217; +valaddr_reg:x3; val_offset:1792*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1792*FLEN/8, x7, x1, x2) + +inst_922:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x195 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x80a7; op2val:0x8195; +valaddr_reg:x3; val_offset:1794*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1794*FLEN/8, x7, x1, x2) + +inst_923:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x287 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x195 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8687; op2val:0x8195; +valaddr_reg:x3; val_offset:1796*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1796*FLEN/8, x7, x1, x2) + +inst_924:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x80a7; op2val:0x821e; +valaddr_reg:x3; val_offset:1798*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1798*FLEN/8, x7, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_7) + +inst_925:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x287 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x036 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8687; op2val:0x8036; +valaddr_reg:x3; val_offset:1800*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1800*FLEN/8, x7, x1, x2) + +inst_926:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x036 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x287 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8036; op2val:0x8687; +valaddr_reg:x3; val_offset:1802*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1802*FLEN/8, x7, x1, x2) + +inst_927:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x287 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8687; op2val:0x821e; +valaddr_reg:x3; val_offset:1804*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1804*FLEN/8, x7, x1, x2) + +inst_928:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x80a7; op2val:0x8365; +valaddr_reg:x3; val_offset:1806*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1806*FLEN/8, x7, x1, x2) + +inst_929:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x287 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x056 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8687; op2val:0x8056; +valaddr_reg:x3; val_offset:1808*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1808*FLEN/8, x7, x1, x2) + +inst_930:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x056 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x287 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8056; op2val:0x8687; +valaddr_reg:x3; val_offset:1810*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1810*FLEN/8, x7, x1, x2) + +inst_931:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x287 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8687; op2val:0x8365; +valaddr_reg:x3; val_offset:1812*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1812*FLEN/8, x7, x1, x2) + +inst_932:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x109 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x80a7; op2val:0x8109; +valaddr_reg:x3; val_offset:1814*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1814*FLEN/8, x7, x1, x2) + +inst_933:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x287 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x01a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8687; op2val:0x801a; +valaddr_reg:x3; val_offset:1816*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1816*FLEN/8, x7, x1, x2) + +inst_934:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x01a and fs2 == 1 and fe2 == 0x01 and fm2 == 0x287 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x801a; op2val:0x8687; +valaddr_reg:x3; val_offset:1818*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1818*FLEN/8, x7, x1, x2) + +inst_935:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x287 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x109 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8687; op2val:0x8109; +valaddr_reg:x3; val_offset:1820*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1820*FLEN/8, x7, x1, x2) + +inst_936:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x80a7; op2val:0xf0; +valaddr_reg:x3; val_offset:1822*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1822*FLEN/8, x7, x1, x2) + +inst_937:// fs1 == 1 and fe1 == 0x12 and fm1 == 0x0fa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xc8fa; op2val:0xf0; +valaddr_reg:x3; val_offset:1824*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1824*FLEN/8, x7, x1, x2) + +inst_938:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xc8fa; +valaddr_reg:x3; val_offset:1826*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1826*FLEN/8, x7, x1, x2) + +inst_939:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a7 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x80a7; op2val:0xc8fa; +valaddr_reg:x3; val_offset:1828*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1828*FLEN/8, x7, x1, x2) + +inst_940:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x821e; op2val:0x739c; +valaddr_reg:x3; val_offset:1830*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1830*FLEN/8, x7, x1, x2) + +inst_941:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x3e4 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf7e4; op2val:0x739c; +valaddr_reg:x3; val_offset:1832*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1832*FLEN/8, x7, x1, x2) + +inst_942:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3e4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x821e; op2val:0xf7e4; +valaddr_reg:x3; val_offset:1834*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1834*FLEN/8, x7, x1, x2) + +inst_943:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x821e; op2val:0x821e; +valaddr_reg:x3; val_offset:1836*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1836*FLEN/8, x7, x1, x2) + +inst_944:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x100 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x821e; op2val:0x7900; +valaddr_reg:x3; val_offset:1838*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1838*FLEN/8, x7, x1, x2) + +inst_945:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x3e4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x100 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf7e4; op2val:0x7900; +valaddr_reg:x3; val_offset:1840*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1840*FLEN/8, x7, x1, x2) + +inst_946:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x025 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x821e; op2val:0x7425; +valaddr_reg:x3; val_offset:1842*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1842*FLEN/8, x7, x1, x2) + +inst_947:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x3e4 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x025 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf7e4; op2val:0x7425; +valaddr_reg:x3; val_offset:1844*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1844*FLEN/8, x7, x1, x2) + +inst_948:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x821e; op2val:0x7ab0; +valaddr_reg:x3; val_offset:1846*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1846*FLEN/8, x7, x1, x2) + +inst_949:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x3e4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf7e4; op2val:0x7ab0; +valaddr_reg:x3; val_offset:1848*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1848*FLEN/8, x7, x1, x2) + +inst_950:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x821e; op2val:0x7913; +valaddr_reg:x3; val_offset:1850*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1850*FLEN/8, x7, x1, x2) + +inst_951:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x3e4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf7e4; op2val:0x7913; +valaddr_reg:x3; val_offset:1852*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1852*FLEN/8, x7, x1, x2) + +inst_952:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e and fs2 == 1 and fe2 == 0x1d and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x821e; op2val:0xf749; +valaddr_reg:x3; val_offset:1854*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1854*FLEN/8, x7, x1, x2) + +inst_953:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x3e4 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf7e4; op2val:0xf749; +valaddr_reg:x3; val_offset:1856*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1856*FLEN/8, x7, x1, x2) + +inst_954:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x378 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x821e; op2val:0xfb78; +valaddr_reg:x3; val_offset:1858*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1858*FLEN/8, x7, x1, x2) + +inst_955:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x3e4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x378 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf7e4; op2val:0xfb78; +valaddr_reg:x3; val_offset:1860*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1860*FLEN/8, x7, x1, x2) + +inst_956:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x21f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x821e; op2val:0xfa1f; +valaddr_reg:x3; val_offset:1862*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1862*FLEN/8, x7, x1, x2) + +inst_957:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x3e4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x21f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf7e4; op2val:0xfa1f; +valaddr_reg:x3; val_offset:1864*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1864*FLEN/8, x7, x1, x2) + +inst_958:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x821e; op2val:0xf82f; +valaddr_reg:x3; val_offset:1866*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1866*FLEN/8, x7, x1, x2) + +inst_959:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x3e4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf7e4; op2val:0xf82f; +valaddr_reg:x3; val_offset:1868*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1868*FLEN/8, x7, x1, x2) + +inst_960:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x821e; op2val:0xf038; +valaddr_reg:x3; val_offset:1870*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1870*FLEN/8, x7, x1, x2) + +inst_961:// fs1 == 1 and fe1 == 0x1a and fm1 == 0x250 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xea50; op2val:0xf038; +valaddr_reg:x3; val_offset:1872*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1872*FLEN/8, x7, x1, x2) + +inst_962:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e and fs2 == 1 and fe2 == 0x1a and fm2 == 0x250 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x821e; op2val:0xea50; +valaddr_reg:x3; val_offset:1874*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1874*FLEN/8, x7, x1, x2) + +inst_963:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x821e; op2val:0xe; +valaddr_reg:x3; val_offset:1876*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1876*FLEN/8, x7, x1, x2) + +inst_964:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x005 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x821e; op2val:0x8005; +valaddr_reg:x3; val_offset:1878*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1878*FLEN/8, x7, x1, x2) + +inst_965:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x821e; op2val:0x80a7; +valaddr_reg:x3; val_offset:1880*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1880*FLEN/8, x7, x1, x2) + +inst_966:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x036 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8036; op2val:0x80a7; +valaddr_reg:x3; val_offset:1882*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1882*FLEN/8, x7, x1, x2) + +inst_967:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x036 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x821e; op2val:0x8036; +valaddr_reg:x3; val_offset:1884*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1884*FLEN/8, x7, x1, x2) + +inst_968:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x821e; op2val:0x8365; +valaddr_reg:x3; val_offset:1886*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1886*FLEN/8, x7, x1, x2) + +inst_969:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8365; op2val:0x821e; +valaddr_reg:x3; val_offset:1888*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1888*FLEN/8, x7, x1, x2) + +inst_970:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x109 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x821e; op2val:0x8109; +valaddr_reg:x3; val_offset:1890*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1890*FLEN/8, x7, x1, x2) + +inst_971:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x109 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8109; op2val:0x821e; +valaddr_reg:x3; val_offset:1892*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1892*FLEN/8, x7, x1, x2) + +inst_972:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x821e; op2val:0xf0; +valaddr_reg:x3; val_offset:1894*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1894*FLEN/8, x7, x1, x2) + +inst_973:// fs1 == 1 and fe1 == 0x10 and fm1 == 0x277 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xc277; op2val:0xf0; +valaddr_reg:x3; val_offset:1896*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1896*FLEN/8, x7, x1, x2) + +inst_974:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x277 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xc277; +valaddr_reg:x3; val_offset:1898*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1898*FLEN/8, x7, x1, x2) + +inst_975:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e and fs2 == 1 and fe2 == 0x10 and fm2 == 0x277 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x821e; op2val:0xc277; +valaddr_reg:x3; val_offset:1900*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1900*FLEN/8, x7, x1, x2) + +inst_976:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8365; op2val:0x739c; +valaddr_reg:x3; val_offset:1902*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1902*FLEN/8, x7, x1, x2) + +inst_977:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x252 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa52; op2val:0x739c; +valaddr_reg:x3; val_offset:1904*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1904*FLEN/8, x7, x1, x2) + +inst_978:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x252 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8365; op2val:0xfa52; +valaddr_reg:x3; val_offset:1906*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1906*FLEN/8, x7, x1, x2) + +inst_979:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8365; op2val:0x8365; +valaddr_reg:x3; val_offset:1908*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1908*FLEN/8, x7, x1, x2) + +inst_980:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x100 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8365; op2val:0x7900; +valaddr_reg:x3; val_offset:1910*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1910*FLEN/8, x7, x1, x2) + +inst_981:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x252 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x100 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa52; op2val:0x7900; +valaddr_reg:x3; val_offset:1912*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1912*FLEN/8, x7, x1, x2) + +inst_982:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x025 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8365; op2val:0x7425; +valaddr_reg:x3; val_offset:1914*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1914*FLEN/8, x7, x1, x2) + +inst_983:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x252 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x025 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa52; op2val:0x7425; +valaddr_reg:x3; val_offset:1916*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1916*FLEN/8, x7, x1, x2) + +inst_984:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8365; op2val:0x7ab0; +valaddr_reg:x3; val_offset:1918*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1918*FLEN/8, x7, x1, x2) + +inst_985:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x252 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa52; op2val:0x7ab0; +valaddr_reg:x3; val_offset:1920*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1920*FLEN/8, x7, x1, x2) + +inst_986:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8365; op2val:0x7913; +valaddr_reg:x3; val_offset:1922*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1922*FLEN/8, x7, x1, x2) + +inst_987:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x252 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa52; op2val:0x7913; +valaddr_reg:x3; val_offset:1924*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1924*FLEN/8, x7, x1, x2) + +inst_988:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8365; op2val:0xf749; +valaddr_reg:x3; val_offset:1926*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1926*FLEN/8, x7, x1, x2) + +inst_989:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x252 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa52; op2val:0xf749; +valaddr_reg:x3; val_offset:1928*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1928*FLEN/8, x7, x1, x2) + +inst_990:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x378 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8365; op2val:0xfb78; +valaddr_reg:x3; val_offset:1930*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1930*FLEN/8, x7, x1, x2) + +inst_991:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x252 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x378 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa52; op2val:0xfb78; +valaddr_reg:x3; val_offset:1932*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1932*FLEN/8, x7, x1, x2) + +inst_992:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x21f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8365; op2val:0xfa1f; +valaddr_reg:x3; val_offset:1934*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1934*FLEN/8, x7, x1, x2) + +inst_993:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x252 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x21f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa52; op2val:0xfa1f; +valaddr_reg:x3; val_offset:1936*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1936*FLEN/8, x7, x1, x2) + +inst_994:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8365; op2val:0xf82f; +valaddr_reg:x3; val_offset:1938*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1938*FLEN/8, x7, x1, x2) + +inst_995:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x252 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa52; op2val:0xf82f; +valaddr_reg:x3; val_offset:1940*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1940*FLEN/8, x7, x1, x2) + +inst_996:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8365; op2val:0xf038; +valaddr_reg:x3; val_offset:1942*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1942*FLEN/8, x7, x1, x2) + +inst_997:// fs1 == 1 and fe1 == 0x1b and fm1 == 0x10f and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xed0f; op2val:0xf038; +valaddr_reg:x3; val_offset:1944*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1944*FLEN/8, x7, x1, x2) + +inst_998:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x10f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8365; op2val:0xed0f; +valaddr_reg:x3; val_offset:1946*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1946*FLEN/8, x7, x1, x2) + +inst_999:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8365; op2val:0xe; +valaddr_reg:x3; val_offset:1948*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1948*FLEN/8, x7, x1, x2) + +inst_1000:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x008 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8365; op2val:0x8008; +valaddr_reg:x3; val_offset:1950*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1950*FLEN/8, x7, x1, x2) + +inst_1001:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8365; op2val:0x80a7; +valaddr_reg:x3; val_offset:1952*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1952*FLEN/8, x7, x1, x2) + +inst_1002:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x056 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8056; op2val:0x80a7; +valaddr_reg:x3; val_offset:1954*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1954*FLEN/8, x7, x1, x2) + +inst_1003:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x056 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8365; op2val:0x8056; +valaddr_reg:x3; val_offset:1956*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1956*FLEN/8, x7, x1, x2) + +inst_1004:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x109 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8365; op2val:0x8109; +valaddr_reg:x3; val_offset:1958*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1958*FLEN/8, x7, x1, x2) + +inst_1005:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x109 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8109; op2val:0x8365; +valaddr_reg:x3; val_offset:1960*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1960*FLEN/8, x7, x1, x2) + +inst_1006:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8365; op2val:0xf0; +valaddr_reg:x3; val_offset:1962*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1962*FLEN/8, x7, x1, x2) + +inst_1007:// fs1 == 1 and fe1 == 0x11 and fm1 == 0x12e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xc52e; op2val:0xf0; +valaddr_reg:x3; val_offset:1964*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1964*FLEN/8, x7, x1, x2) + +inst_1008:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x12e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xc52e; +valaddr_reg:x3; val_offset:1966*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1966*FLEN/8, x7, x1, x2) + +inst_1009:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x12e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8365; op2val:0xc52e; +valaddr_reg:x3; val_offset:1968*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1968*FLEN/8, x7, x1, x2) + +inst_1010:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x109 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8109; op2val:0x739c; +valaddr_reg:x3; val_offset:1970*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1970*FLEN/8, x7, x1, x2) + +inst_1011:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3b9 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3b9; op2val:0x739c; +valaddr_reg:x3; val_offset:1972*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1972*FLEN/8, x7, x1, x2) + +inst_1012:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x109 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3b9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8109; op2val:0xf3b9; +valaddr_reg:x3; val_offset:1974*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1974*FLEN/8, x7, x1, x2) + +inst_1013:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x109 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x109 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8109; op2val:0x8109; +valaddr_reg:x3; val_offset:1976*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1976*FLEN/8, x7, x1, x2) + +inst_1014:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x109 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x100 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8109; op2val:0x7900; +valaddr_reg:x3; val_offset:1978*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1978*FLEN/8, x7, x1, x2) + +inst_1015:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3b9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x100 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3b9; op2val:0x7900; +valaddr_reg:x3; val_offset:1980*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1980*FLEN/8, x7, x1, x2) + +inst_1016:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x109 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x025 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8109; op2val:0x7425; +valaddr_reg:x3; val_offset:1982*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1982*FLEN/8, x7, x1, x2) + +inst_1017:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3b9 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x025 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3b9; op2val:0x7425; +valaddr_reg:x3; val_offset:1984*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1984*FLEN/8, x7, x1, x2) + +inst_1018:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x109 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8109; op2val:0x7ab0; +valaddr_reg:x3; val_offset:1986*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1986*FLEN/8, x7, x1, x2) + +inst_1019:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3b9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3b9; op2val:0x7ab0; +valaddr_reg:x3; val_offset:1988*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1988*FLEN/8, x7, x1, x2) + +inst_1020:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x109 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8109; op2val:0x7913; +valaddr_reg:x3; val_offset:1990*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1990*FLEN/8, x7, x1, x2) + +inst_1021:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3b9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3b9; op2val:0x7913; +valaddr_reg:x3; val_offset:1992*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1992*FLEN/8, x7, x1, x2) + +inst_1022:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x109 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8109; op2val:0xf749; +valaddr_reg:x3; val_offset:1994*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1994*FLEN/8, x7, x1, x2) + +inst_1023:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3b9 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3b9; op2val:0xf749; +valaddr_reg:x3; val_offset:1996*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1996*FLEN/8, x7, x1, x2) + +inst_1024:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x109 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x378 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8109; op2val:0xfb78; +valaddr_reg:x3; val_offset:1998*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 1998*FLEN/8, x7, x1, x2) + +inst_1025:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3b9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x378 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3b9; op2val:0xfb78; +valaddr_reg:x3; val_offset:2000*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 2000*FLEN/8, x7, x1, x2) + +inst_1026:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x109 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x21f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8109; op2val:0xfa1f; +valaddr_reg:x3; val_offset:2002*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 2002*FLEN/8, x7, x1, x2) + +inst_1027:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3b9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x21f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3b9; op2val:0xfa1f; +valaddr_reg:x3; val_offset:2004*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 2004*FLEN/8, x7, x1, x2) + +inst_1028:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x109 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8109; op2val:0xf82f; +valaddr_reg:x3; val_offset:2006*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 2006*FLEN/8, x7, x1, x2) + +inst_1029:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3b9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3b9; op2val:0xf82f; +valaddr_reg:x3; val_offset:2008*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 2008*FLEN/8, x7, x1, x2) + +inst_1030:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x109 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8109; op2val:0xf038; +valaddr_reg:x3; val_offset:2010*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 2010*FLEN/8, x7, x1, x2) + +inst_1031:// fs1 == 1 and fe1 == 0x19 and fm1 == 0x22e and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xe62e; op2val:0xf038; +valaddr_reg:x3; val_offset:2012*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 2012*FLEN/8, x7, x1, x2) + +inst_1032:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x109 and fs2 == 1 and fe2 == 0x19 and fm2 == 0x22e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8109; op2val:0xe62e; +valaddr_reg:x3; val_offset:2014*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 2014*FLEN/8, x7, x1, x2) + +inst_1033:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x109 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8109; op2val:0xe; +valaddr_reg:x3; val_offset:2016*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 2016*FLEN/8, x7, x1, x2) + +inst_1034:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8002; op2val:0xe; +valaddr_reg:x3; val_offset:2018*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 2018*FLEN/8, x7, x1, x2) + +inst_1035:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x109 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8109; op2val:0x8002; +valaddr_reg:x3; val_offset:2020*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 2020*FLEN/8, x7, x1, x2) + +inst_1036:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x109 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8109; op2val:0x80a7; +valaddr_reg:x3; val_offset:2022*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 2022*FLEN/8, x7, x1, x2) + +inst_1037:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x01a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x801a; op2val:0x80a7; +valaddr_reg:x3; val_offset:2024*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 2024*FLEN/8, x7, x1, x2) + +inst_1038:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x109 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x01a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8109; op2val:0x801a; +valaddr_reg:x3; val_offset:2026*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 2026*FLEN/8, x7, x1, x2) + +inst_1039:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x109 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8109; op2val:0xf0; +valaddr_reg:x3; val_offset:2028*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 2028*FLEN/8, x7, x1, x2) + +inst_1040:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x254 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xbe54; op2val:0xf0; +valaddr_reg:x3; val_offset:2030*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 2030*FLEN/8, x7, x1, x2) + +inst_1041:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x254 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xbe54; +valaddr_reg:x3; val_offset:2032*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 2032*FLEN/8, x7, x1, x2) + +inst_1042:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x109 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x254 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x8109; op2val:0xbe54; +valaddr_reg:x3; val_offset:2034*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 2034*FLEN/8, x7, x1, x2) + +inst_1043:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x739c; +valaddr_reg:x3; val_offset:2036*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 2036*FLEN/8, x7, x1, x2) + +inst_1044:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xf0; +valaddr_reg:x3; val_offset:2038*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 2038*FLEN/8, x7, x1, x2) + +inst_1045:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x100 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x7900; +valaddr_reg:x3; val_offset:2040*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 2040*FLEN/8, x7, x1, x2) + +inst_1046:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x025 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x7425; +valaddr_reg:x3; val_offset:2042*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 2042*FLEN/8, x7, x1, x2) + +inst_1047:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x7ab0; +valaddr_reg:x3; val_offset:2044*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 2044*FLEN/8, x7, x1, x2) + +inst_1048:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x113 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x7913; +valaddr_reg:x3; val_offset:2046*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 2046*FLEN/8, x7, x1, x2) + +inst_1049:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x349 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xf749; +valaddr_reg:x3; val_offset:2048*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 2048*FLEN/8, x7, x1, x2) + +inst_1050:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x378 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xfb78; +valaddr_reg:x3; val_offset:2050*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 2050*FLEN/8, x7, x1, x2) + +inst_1051:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x21f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xfa1f; +valaddr_reg:x3; val_offset:2052*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 2052*FLEN/8, x7, x1, x2) + +inst_1052:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xf82f; +valaddr_reg:x3; val_offset:2054*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 2054*FLEN/8, x7, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_8) + +inst_1053:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xf038; +valaddr_reg:x3; val_offset:2056*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 2056*FLEN/8, x7, x1, x2) + +inst_1054:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x17b; +valaddr_reg:x3; val_offset:2058*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 2058*FLEN/8, x7, x1, x2) + +inst_1055:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xe; +valaddr_reg:x3; val_offset:2060*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 2060*FLEN/8, x7, x1, x2) + +inst_1056:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x3fa; +valaddr_reg:x3; val_offset:2062*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 2062*FLEN/8, x7, x1, x2) + +inst_1057:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x28e; +valaddr_reg:x3; val_offset:2064*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 2064*FLEN/8, x7, x1, x2) + +inst_1058:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x217; +valaddr_reg:x3; val_offset:2066*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 2066*FLEN/8, x7, x1, x2) + +inst_1059:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x195 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x8195; +valaddr_reg:x3; val_offset:2068*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 2068*FLEN/8, x7, x1, x2) + +inst_1060:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x80a7; +valaddr_reg:x3; val_offset:2070*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 2070*FLEN/8, x7, x1, x2) + +inst_1061:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x821e; +valaddr_reg:x3; val_offset:2072*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 2072*FLEN/8, x7, x1, x2) + +inst_1062:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x8365; +valaddr_reg:x3; val_offset:2074*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 2074*FLEN/8, x7, x1, x2) + +inst_1063:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x109 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x8109; +valaddr_reg:x3; val_offset:2076*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 2076*FLEN/8, x7, x1, x2) + +inst_1064:// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x100 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x739c; op2val:0x7900; +valaddr_reg:x3; val_offset:2078*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 2078*FLEN/8, x7, x1, x2) + +inst_1065:// fs1 == 0 and fe1 == 0x19 and fm1 == 0x216 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x6616; op2val:0xf038; +valaddr_reg:x3; val_offset:2080*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 2080*FLEN/8, x7, x1, x2) + +inst_1066:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xe; +valaddr_reg:x3; val_offset:2082*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 2082*FLEN/8, x7, x1, x2) + +inst_1067:// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fle.h ; op1:x30; op2:x29; dest:x31; op1val:0x739c; op2val:0x2; +valaddr_reg:x3; val_offset:2084*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0*/ +TEST_FCMP_OP(fle.h, x31, x30, x29, 0, 0, x3, 2084*FLEN/8, x7, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(30976,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(29733,32,FLEN) +NAN_BOXED(29733,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(31408,32,FLEN) +NAN_BOXED(31408,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(30995,32,FLEN) +NAN_BOXED(30995,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(63305,16,FLEN) +NAN_BOXED(63305,16,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(64376,16,FLEN) +test_dataset_1: +NAN_BOXED(64376,16,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(64031,16,FLEN) +NAN_BOXED(64031,16,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(63535,16,FLEN) +NAN_BOXED(63535,16,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(61496,16,FLEN) +NAN_BOXED(26134,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(26134,32,FLEN) +NAN_BOXED(26134,32,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(26134,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(379,32,FLEN) +NAN_BOXED(261,32,FLEN) +NAN_BOXED(30084,32,FLEN) +NAN_BOXED(30084,32,FLEN) +NAN_BOXED(261,32,FLEN) +test_dataset_2: +NAN_BOXED(261,16,FLEN) +NAN_BOXED(379,16,FLEN) +NAN_BOXED(29596,16,FLEN) +NAN_BOXED(261,16,FLEN) +NAN_BOXED(29596,16,FLEN) +NAN_BOXED(14,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(14,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(29596,16,FLEN) +NAN_BOXED(1018,16,FLEN) +NAN_BOXED(261,16,FLEN) +NAN_BOXED(31593,16,FLEN) +NAN_BOXED(31593,16,FLEN) +NAN_BOXED(261,16,FLEN) +NAN_BOXED(261,16,FLEN) +NAN_BOXED(1018,16,FLEN) +NAN_BOXED(29596,16,FLEN) +NAN_BOXED(654,16,FLEN) +NAN_BOXED(261,16,FLEN) +NAN_BOXED(30914,16,FLEN) +NAN_BOXED(30914,16,FLEN) +NAN_BOXED(261,16,FLEN) +NAN_BOXED(261,16,FLEN) +NAN_BOXED(654,16,FLEN) +NAN_BOXED(29596,16,FLEN) +NAN_BOXED(535,16,FLEN) +NAN_BOXED(261,16,FLEN) +NAN_BOXED(30667,16,FLEN) +NAN_BOXED(30667,16,FLEN) +NAN_BOXED(261,16,FLEN) +NAN_BOXED(261,16,FLEN) +NAN_BOXED(535,16,FLEN) +NAN_BOXED(29596,16,FLEN) +NAN_BOXED(33173,16,FLEN) +NAN_BOXED(261,16,FLEN) +NAN_BOXED(62951,16,FLEN) +NAN_BOXED(62951,16,FLEN) +NAN_BOXED(261,16,FLEN) +NAN_BOXED(261,16,FLEN) +NAN_BOXED(33173,16,FLEN) +NAN_BOXED(29596,16,FLEN) +NAN_BOXED(32935,16,FLEN) +NAN_BOXED(26,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(26,16,FLEN) +NAN_BOXED(26,16,FLEN) +NAN_BOXED(32935,16,FLEN) +NAN_BOXED(29596,16,FLEN) +NAN_BOXED(26,16,FLEN) +NAN_BOXED(29596,16,FLEN) +NAN_BOXED(33310,16,FLEN) +NAN_BOXED(261,16,FLEN) +NAN_BOXED(63460,16,FLEN) +NAN_BOXED(63460,16,FLEN) +NAN_BOXED(261,16,FLEN) +NAN_BOXED(261,16,FLEN) +NAN_BOXED(33310,16,FLEN) +NAN_BOXED(29596,16,FLEN) +NAN_BOXED(33637,16,FLEN) +NAN_BOXED(261,16,FLEN) +NAN_BOXED(64082,16,FLEN) +NAN_BOXED(64082,16,FLEN) +NAN_BOXED(261,16,FLEN) +NAN_BOXED(261,16,FLEN) +NAN_BOXED(33637,16,FLEN) +NAN_BOXED(29596,16,FLEN) +NAN_BOXED(33033,16,FLEN) +NAN_BOXED(261,16,FLEN) +NAN_BOXED(62393,16,FLEN) +NAN_BOXED(62393,16,FLEN) +NAN_BOXED(261,16,FLEN) +NAN_BOXED(261,16,FLEN) +NAN_BOXED(33033,16,FLEN) +NAN_BOXED(29596,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(15932,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(15932,16,FLEN) +NAN_BOXED(29596,16,FLEN) +NAN_BOXED(15932,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(29733,16,FLEN) +NAN_BOXED(29733,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(31408,16,FLEN) +NAN_BOXED(31408,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(30995,16,FLEN) +NAN_BOXED(30995,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(63305,16,FLEN) +NAN_BOXED(63305,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(64376,16,FLEN) +NAN_BOXED(64376,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(64031,16,FLEN) +NAN_BOXED(64031,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(63535,16,FLEN) +NAN_BOXED(63535,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(61496,16,FLEN) +NAN_BOXED(27648,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(27648,16,FLEN) +NAN_BOXED(27648,16,FLEN) +NAN_BOXED(61496,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(27648,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(379,16,FLEN) +NAN_BOXED(687,16,FLEN) +NAN_BOXED(30084,16,FLEN) +NAN_BOXED(30084,16,FLEN) +NAN_BOXED(687,16,FLEN) +NAN_BOXED(687,16,FLEN) +NAN_BOXED(379,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(687,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(14,16,FLEN) +NAN_BOXED(6,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(6,16,FLEN) +NAN_BOXED(6,16,FLEN) +NAN_BOXED(14,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(6,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(1018,16,FLEN) +NAN_BOXED(687,16,FLEN) +NAN_BOXED(31593,16,FLEN) +NAN_BOXED(31593,16,FLEN) +NAN_BOXED(687,16,FLEN) +NAN_BOXED(687,16,FLEN) +NAN_BOXED(1018,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(654,16,FLEN) +NAN_BOXED(687,16,FLEN) +NAN_BOXED(30914,16,FLEN) +NAN_BOXED(30914,16,FLEN) +NAN_BOXED(687,16,FLEN) +NAN_BOXED(687,16,FLEN) +NAN_BOXED(654,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(535,16,FLEN) +NAN_BOXED(687,16,FLEN) +NAN_BOXED(30667,16,FLEN) +NAN_BOXED(30667,16,FLEN) +NAN_BOXED(687,16,FLEN) +NAN_BOXED(687,16,FLEN) +NAN_BOXED(535,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(33173,16,FLEN) +NAN_BOXED(687,16,FLEN) +NAN_BOXED(62951,16,FLEN) +NAN_BOXED(62951,16,FLEN) +NAN_BOXED(687,16,FLEN) +NAN_BOXED(687,16,FLEN) +NAN_BOXED(33173,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(32935,16,FLEN) +NAN_BOXED(68,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(68,16,FLEN) +NAN_BOXED(68,16,FLEN) +NAN_BOXED(32935,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(68,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(33310,16,FLEN) +NAN_BOXED(687,16,FLEN) +NAN_BOXED(63460,16,FLEN) +NAN_BOXED(63460,16,FLEN) +NAN_BOXED(687,16,FLEN) +NAN_BOXED(687,16,FLEN) +NAN_BOXED(33310,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(33637,16,FLEN) +NAN_BOXED(687,16,FLEN) +NAN_BOXED(64082,16,FLEN) +NAN_BOXED(64082,16,FLEN) +NAN_BOXED(687,16,FLEN) +NAN_BOXED(687,16,FLEN) +NAN_BOXED(33637,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(33033,16,FLEN) +NAN_BOXED(687,16,FLEN) +NAN_BOXED(62393,16,FLEN) +NAN_BOXED(62393,16,FLEN) +NAN_BOXED(687,16,FLEN) +NAN_BOXED(687,16,FLEN) +NAN_BOXED(33033,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(17433,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(17433,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(17433,16,FLEN) +NAN_BOXED(29733,16,FLEN) +NAN_BOXED(29733,16,FLEN) +NAN_BOXED(29733,16,FLEN) +NAN_BOXED(31408,16,FLEN) +NAN_BOXED(31408,16,FLEN) +NAN_BOXED(29733,16,FLEN) +NAN_BOXED(29733,16,FLEN) +NAN_BOXED(30995,16,FLEN) +NAN_BOXED(30995,16,FLEN) +NAN_BOXED(29733,16,FLEN) +NAN_BOXED(29733,16,FLEN) +NAN_BOXED(63305,16,FLEN) +NAN_BOXED(63305,16,FLEN) +NAN_BOXED(29733,16,FLEN) +NAN_BOXED(29733,16,FLEN) +NAN_BOXED(64376,16,FLEN) +NAN_BOXED(64376,16,FLEN) +NAN_BOXED(29733,16,FLEN) +NAN_BOXED(29733,16,FLEN) +NAN_BOXED(64031,16,FLEN) +NAN_BOXED(64031,16,FLEN) +NAN_BOXED(29733,16,FLEN) +NAN_BOXED(29733,16,FLEN) +NAN_BOXED(63535,16,FLEN) +NAN_BOXED(63535,16,FLEN) +NAN_BOXED(29733,16,FLEN) +NAN_BOXED(29733,16,FLEN) +NAN_BOXED(61496,16,FLEN) +NAN_BOXED(26274,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(26274,16,FLEN) +NAN_BOXED(26274,16,FLEN) +NAN_BOXED(61496,16,FLEN) +NAN_BOXED(29733,16,FLEN) +NAN_BOXED(26274,16,FLEN) +NAN_BOXED(29733,16,FLEN) +NAN_BOXED(379,16,FLEN) +NAN_BOXED(285,16,FLEN) +NAN_BOXED(30084,16,FLEN) +NAN_BOXED(30084,16,FLEN) +NAN_BOXED(285,16,FLEN) +NAN_BOXED(285,16,FLEN) +NAN_BOXED(379,16,FLEN) +NAN_BOXED(29733,16,FLEN) +NAN_BOXED(285,16,FLEN) +NAN_BOXED(29733,16,FLEN) +NAN_BOXED(14,16,FLEN) +NAN_BOXED(29733,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(29733,16,FLEN) +NAN_BOXED(1018,16,FLEN) +NAN_BOXED(285,16,FLEN) +NAN_BOXED(31593,16,FLEN) +NAN_BOXED(31593,16,FLEN) +NAN_BOXED(285,16,FLEN) +NAN_BOXED(285,16,FLEN) +NAN_BOXED(1018,16,FLEN) +NAN_BOXED(29733,16,FLEN) +NAN_BOXED(654,16,FLEN) +NAN_BOXED(285,16,FLEN) +NAN_BOXED(30914,16,FLEN) +NAN_BOXED(30914,16,FLEN) +NAN_BOXED(285,16,FLEN) +NAN_BOXED(285,16,FLEN) +NAN_BOXED(654,16,FLEN) +NAN_BOXED(29733,16,FLEN) +NAN_BOXED(535,16,FLEN) +NAN_BOXED(285,16,FLEN) +NAN_BOXED(30667,16,FLEN) +NAN_BOXED(30667,16,FLEN) +NAN_BOXED(285,16,FLEN) +NAN_BOXED(285,16,FLEN) +NAN_BOXED(535,16,FLEN) +NAN_BOXED(29733,16,FLEN) +NAN_BOXED(33173,16,FLEN) +NAN_BOXED(285,16,FLEN) +NAN_BOXED(62951,16,FLEN) +NAN_BOXED(62951,16,FLEN) +NAN_BOXED(285,16,FLEN) +NAN_BOXED(285,16,FLEN) +NAN_BOXED(33173,16,FLEN) +NAN_BOXED(29733,16,FLEN) +NAN_BOXED(32935,16,FLEN) +NAN_BOXED(28,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28,16,FLEN) +NAN_BOXED(28,16,FLEN) +NAN_BOXED(32935,16,FLEN) +NAN_BOXED(29733,16,FLEN) +NAN_BOXED(28,16,FLEN) +NAN_BOXED(29733,16,FLEN) +NAN_BOXED(33310,16,FLEN) +NAN_BOXED(285,16,FLEN) +NAN_BOXED(63460,16,FLEN) +NAN_BOXED(63460,16,FLEN) +NAN_BOXED(285,16,FLEN) +NAN_BOXED(285,16,FLEN) +NAN_BOXED(33310,16,FLEN) +NAN_BOXED(29733,16,FLEN) +NAN_BOXED(33637,16,FLEN) +NAN_BOXED(285,16,FLEN) +NAN_BOXED(64082,16,FLEN) +NAN_BOXED(64082,16,FLEN) +NAN_BOXED(285,16,FLEN) +NAN_BOXED(285,16,FLEN) +NAN_BOXED(33637,16,FLEN) +NAN_BOXED(29733,16,FLEN) +NAN_BOXED(33033,16,FLEN) +NAN_BOXED(285,16,FLEN) +NAN_BOXED(62393,16,FLEN) +NAN_BOXED(62393,16,FLEN) +NAN_BOXED(285,16,FLEN) +NAN_BOXED(285,16,FLEN) +NAN_BOXED(33033,16,FLEN) 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+NAN_BOXED(33033,16,FLEN) +NAN_BOXED(34439,16,FLEN) +NAN_BOXED(32794,16,FLEN) +NAN_BOXED(32794,16,FLEN) +NAN_BOXED(34439,16,FLEN) +NAN_BOXED(34439,16,FLEN) +NAN_BOXED(33033,16,FLEN) +NAN_BOXED(32935,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(51450,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(51450,16,FLEN) +NAN_BOXED(32935,16,FLEN) +NAN_BOXED(51450,16,FLEN) +NAN_BOXED(33310,16,FLEN) +NAN_BOXED(29596,16,FLEN) +NAN_BOXED(63460,16,FLEN) +NAN_BOXED(29596,16,FLEN) +NAN_BOXED(33310,16,FLEN) +NAN_BOXED(63460,16,FLEN) +NAN_BOXED(33310,16,FLEN) +NAN_BOXED(33310,16,FLEN) +NAN_BOXED(33310,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(63460,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(33310,16,FLEN) +NAN_BOXED(29733,16,FLEN) +NAN_BOXED(63460,16,FLEN) +NAN_BOXED(29733,16,FLEN) +NAN_BOXED(33310,16,FLEN) +NAN_BOXED(31408,16,FLEN) +NAN_BOXED(63460,16,FLEN) +NAN_BOXED(31408,16,FLEN) +NAN_BOXED(33310,16,FLEN) +NAN_BOXED(30995,16,FLEN) +NAN_BOXED(63460,16,FLEN) +NAN_BOXED(30995,16,FLEN) +NAN_BOXED(33310,16,FLEN) +NAN_BOXED(63305,16,FLEN) +NAN_BOXED(63460,16,FLEN) +NAN_BOXED(63305,16,FLEN) +NAN_BOXED(33310,16,FLEN) +NAN_BOXED(64376,16,FLEN) +NAN_BOXED(63460,16,FLEN) +NAN_BOXED(64376,16,FLEN) +NAN_BOXED(33310,16,FLEN) +NAN_BOXED(64031,16,FLEN) +NAN_BOXED(63460,16,FLEN) +NAN_BOXED(64031,16,FLEN) +NAN_BOXED(33310,16,FLEN) +NAN_BOXED(63535,16,FLEN) +NAN_BOXED(63460,16,FLEN) +NAN_BOXED(63535,16,FLEN) +NAN_BOXED(33310,16,FLEN) +NAN_BOXED(61496,16,FLEN) +NAN_BOXED(59984,16,FLEN) +NAN_BOXED(61496,16,FLEN) +NAN_BOXED(33310,16,FLEN) +NAN_BOXED(59984,16,FLEN) +NAN_BOXED(33310,16,FLEN) +NAN_BOXED(14,16,FLEN) +NAN_BOXED(33310,16,FLEN) +NAN_BOXED(32773,16,FLEN) +NAN_BOXED(33310,16,FLEN) +NAN_BOXED(32935,16,FLEN) +NAN_BOXED(32822,16,FLEN) +NAN_BOXED(32935,16,FLEN) +NAN_BOXED(33310,16,FLEN) +NAN_BOXED(32822,16,FLEN) +NAN_BOXED(33310,16,FLEN) +NAN_BOXED(33637,16,FLEN) +NAN_BOXED(33637,16,FLEN) +NAN_BOXED(33310,16,FLEN) +NAN_BOXED(33310,16,FLEN) +NAN_BOXED(33033,16,FLEN) +NAN_BOXED(33033,16,FLEN) +NAN_BOXED(33310,16,FLEN) +NAN_BOXED(33310,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(49783,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(49783,16,FLEN) +NAN_BOXED(33310,16,FLEN) +NAN_BOXED(49783,16,FLEN) +NAN_BOXED(33637,16,FLEN) +NAN_BOXED(29596,16,FLEN) +NAN_BOXED(64082,16,FLEN) +NAN_BOXED(29596,16,FLEN) +NAN_BOXED(33637,16,FLEN) +NAN_BOXED(64082,16,FLEN) +NAN_BOXED(33637,16,FLEN) +NAN_BOXED(33637,16,FLEN) +NAN_BOXED(33637,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(64082,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(33637,16,FLEN) +NAN_BOXED(29733,16,FLEN) +NAN_BOXED(64082,16,FLEN) +NAN_BOXED(29733,16,FLEN) +NAN_BOXED(33637,16,FLEN) +NAN_BOXED(31408,16,FLEN) +NAN_BOXED(64082,16,FLEN) +NAN_BOXED(31408,16,FLEN) +NAN_BOXED(33637,16,FLEN) +NAN_BOXED(30995,16,FLEN) +NAN_BOXED(64082,16,FLEN) +NAN_BOXED(30995,16,FLEN) +NAN_BOXED(33637,16,FLEN) +NAN_BOXED(63305,16,FLEN) +NAN_BOXED(64082,16,FLEN) +NAN_BOXED(63305,16,FLEN) +NAN_BOXED(33637,16,FLEN) +NAN_BOXED(64376,16,FLEN) +NAN_BOXED(64082,16,FLEN) +NAN_BOXED(64376,16,FLEN) +NAN_BOXED(33637,16,FLEN) +NAN_BOXED(64031,16,FLEN) +NAN_BOXED(64082,16,FLEN) +NAN_BOXED(64031,16,FLEN) +NAN_BOXED(33637,16,FLEN) +NAN_BOXED(63535,16,FLEN) +NAN_BOXED(64082,16,FLEN) +NAN_BOXED(63535,16,FLEN) +NAN_BOXED(33637,16,FLEN) +NAN_BOXED(61496,16,FLEN) +NAN_BOXED(60687,16,FLEN) +NAN_BOXED(61496,16,FLEN) +NAN_BOXED(33637,16,FLEN) +NAN_BOXED(60687,16,FLEN) +NAN_BOXED(33637,16,FLEN) +NAN_BOXED(14,16,FLEN) +NAN_BOXED(33637,16,FLEN) +NAN_BOXED(32776,16,FLEN) +NAN_BOXED(33637,16,FLEN) +NAN_BOXED(32935,16,FLEN) +NAN_BOXED(32854,16,FLEN) +NAN_BOXED(32935,16,FLEN) +NAN_BOXED(33637,16,FLEN) +NAN_BOXED(32854,16,FLEN) +NAN_BOXED(33637,16,FLEN) +NAN_BOXED(33033,16,FLEN) +NAN_BOXED(33033,16,FLEN) +NAN_BOXED(33637,16,FLEN) +NAN_BOXED(33637,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(50478,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(50478,16,FLEN) +NAN_BOXED(33637,16,FLEN) +NAN_BOXED(50478,16,FLEN) +NAN_BOXED(33033,16,FLEN) +NAN_BOXED(29596,16,FLEN) +NAN_BOXED(62393,16,FLEN) +NAN_BOXED(29596,16,FLEN) +NAN_BOXED(33033,16,FLEN) +NAN_BOXED(62393,16,FLEN) +NAN_BOXED(33033,16,FLEN) +NAN_BOXED(33033,16,FLEN) +NAN_BOXED(33033,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(62393,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(33033,16,FLEN) +NAN_BOXED(29733,16,FLEN) +NAN_BOXED(62393,16,FLEN) +NAN_BOXED(29733,16,FLEN) +NAN_BOXED(33033,16,FLEN) +NAN_BOXED(31408,16,FLEN) +NAN_BOXED(62393,16,FLEN) +NAN_BOXED(31408,16,FLEN) +NAN_BOXED(33033,16,FLEN) +NAN_BOXED(30995,16,FLEN) +NAN_BOXED(62393,16,FLEN) +NAN_BOXED(30995,16,FLEN) +NAN_BOXED(33033,16,FLEN) +NAN_BOXED(63305,16,FLEN) +NAN_BOXED(62393,16,FLEN) +NAN_BOXED(63305,16,FLEN) +NAN_BOXED(33033,16,FLEN) +NAN_BOXED(64376,16,FLEN) +NAN_BOXED(62393,16,FLEN) +NAN_BOXED(64376,16,FLEN) +NAN_BOXED(33033,16,FLEN) +NAN_BOXED(64031,16,FLEN) +NAN_BOXED(62393,16,FLEN) +NAN_BOXED(64031,16,FLEN) +NAN_BOXED(33033,16,FLEN) +NAN_BOXED(63535,16,FLEN) +NAN_BOXED(62393,16,FLEN) +NAN_BOXED(63535,16,FLEN) +NAN_BOXED(33033,16,FLEN) +NAN_BOXED(61496,16,FLEN) +NAN_BOXED(58926,16,FLEN) +NAN_BOXED(61496,16,FLEN) +NAN_BOXED(33033,16,FLEN) +NAN_BOXED(58926,16,FLEN) +NAN_BOXED(33033,16,FLEN) +NAN_BOXED(14,16,FLEN) +NAN_BOXED(32770,16,FLEN) +NAN_BOXED(14,16,FLEN) +NAN_BOXED(33033,16,FLEN) +NAN_BOXED(32770,16,FLEN) +NAN_BOXED(33033,16,FLEN) +NAN_BOXED(32935,16,FLEN) +NAN_BOXED(32794,16,FLEN) +NAN_BOXED(32935,16,FLEN) +NAN_BOXED(33033,16,FLEN) +NAN_BOXED(32794,16,FLEN) +NAN_BOXED(33033,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(48724,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(48724,16,FLEN) +NAN_BOXED(33033,16,FLEN) +NAN_BOXED(48724,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(29596,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(29733,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(31408,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(30995,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(63305,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(64376,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(64031,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(63535,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(61496,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(379,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(14,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(1018,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(654,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(535,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(33173,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(32935,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(33310,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(33637,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(33033,16,FLEN) +NAN_BOXED(29596,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(26134,16,FLEN) +NAN_BOXED(61496,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(14,16,FLEN) +NAN_BOXED(29596,16,FLEN) +NAN_BOXED(2,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x7_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x7_1: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x5_0: + .fill 30*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_0: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_2: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_3: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_4: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_5: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_6: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_7: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_8: + .fill 30*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/flt_b1-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/flt_b1-01.S new file mode 100644 index 000000000..828e2ab72 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/flt_b1-01.S @@ -0,0 +1,4764 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 05:48:16 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_flt.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the flt.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the flt_b1 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",flt_b1) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x1,test_dataset_0) +RVTEST_SIGBASE(x8,signature_x8_1) + +inst_0:// rs1 == rs2, rs1==x15, rs2==x15, rd==x9,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x15; op2:x15; dest:x9; op1val:0x0; op2val:0x0; +valaddr_reg:x1; val_offset:0*FLEN/8; correctval:??; testreg:x16; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x9, x15, x15, 0, 0, x1, 0*FLEN/8, x17, x8, x16) + +inst_1:// rs1 != rs2, rs1==x24, rs2==x11, rd==x25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x24; op2:x11; dest:x25; op1val:0x0; op2val:0x8000; +valaddr_reg:x1; val_offset:2*FLEN/8; correctval:??; testreg:x16; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x25, x24, x11, 0, 0, x1, 2*FLEN/8, x17, x8, x16) + +inst_2:// rs1==x22, rs2==x18, rd==x13,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x22; op2:x18; dest:x13; op1val:0x0; op2val:0x1; +valaddr_reg:x1; val_offset:4*FLEN/8; correctval:??; testreg:x16; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x13, x22, x18, 0, 0, x1, 4*FLEN/8, x17, x8, x16) + +inst_3:// rs1==x18, rs2==x24, rd==x29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x18; op2:x24; dest:x29; op1val:0x0; op2val:0x8001; +valaddr_reg:x1; val_offset:6*FLEN/8; correctval:??; testreg:x16; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x29, x18, x24, 0, 0, x1, 6*FLEN/8, x17, x8, x16) + +inst_4:// rs1==x0, rs2==x9, rd==x6,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x0; op2:x9; dest:x6; op1val:0x0; op2val:0x2; +valaddr_reg:x1; val_offset:8*FLEN/8; correctval:??; testreg:x16; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x6, x0, x9, 0, 0, x1, 8*FLEN/8, x17, x8, x16) + +inst_5:// rs1==x13, rs2==x3, rd==x19,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x13; op2:x3; dest:x19; op1val:0x0; op2val:0x83fe; +valaddr_reg:x1; val_offset:10*FLEN/8; correctval:??; testreg:x16; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x19, x13, x3, 0, 0, x1, 10*FLEN/8, x17, x8, x16) + +inst_6:// rs1==x7, rs2==x31, rd==x14,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x7; op2:x31; dest:x14; op1val:0x0; op2val:0x3ff; +valaddr_reg:x1; val_offset:12*FLEN/8; correctval:??; testreg:x16; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x14, x7, x31, 0, 0, x1, 12*FLEN/8, x17, x8, x16) + +inst_7:// rs1==x4, rs2==x26, rd==x10,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x4; op2:x26; dest:x10; op1val:0x0; op2val:0x83ff; +valaddr_reg:x1; val_offset:14*FLEN/8; correctval:??; testreg:x16; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x10, x4, x26, 0, 0, x1, 14*FLEN/8, x17, x8, x16) + +inst_8:// rs1==x2, rs2==x14, rd==x24,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x2; op2:x14; dest:x24; op1val:0x0; op2val:0x400; +valaddr_reg:x1; val_offset:16*FLEN/8; correctval:??; testreg:x16; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x24, x2, x14, 0, 0, x1, 16*FLEN/8, x17, x8, x16) + +inst_9:// rs1==x28, rs2==x12, rd==x22,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x28; op2:x12; dest:x22; op1val:0x0; op2val:0x8400; +valaddr_reg:x1; val_offset:18*FLEN/8; correctval:??; testreg:x16; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x22, x28, x12, 0, 0, x1, 18*FLEN/8, x17, x8, x16) + +inst_10:// rs1==x26, rs2==x29, rd==x5,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x26; op2:x29; dest:x5; op1val:0x0; op2val:0x401; +valaddr_reg:x1; val_offset:20*FLEN/8; correctval:??; testreg:x16; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x5, x26, x29, 0, 0, x1, 20*FLEN/8, x17, x8, x16) + +inst_11:// rs1==x11, rs2==x21, rd==x27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x11; op2:x21; dest:x27; op1val:0x0; op2val:0x8455; +valaddr_reg:x1; val_offset:22*FLEN/8; correctval:??; testreg:x16; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x27, x11, x21, 0, 0, x1, 22*FLEN/8, x17, x8, x16) +RVTEST_VALBASEUPD(x14,test_dataset_1) + +inst_12:// rs1==x29, rs2==x25, rd==x18,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x29; op2:x25; dest:x18; op1val:0x0; op2val:0x7bff; +valaddr_reg:x14; val_offset:0*FLEN/8; correctval:??; testreg:x16; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x18, x29, x25, 0, 0, x14, 0*FLEN/8, x19, x8, x16) + +inst_13:// rs1==x5, rs2==x4, rd==x1,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x5; op2:x4; dest:x1; op1val:0x0; op2val:0xfbff; +valaddr_reg:x14; val_offset:2*FLEN/8; correctval:??; testreg:x16; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x1, x5, x4, 0, 0, x14, 2*FLEN/8, x19, x8, x16) + +inst_14:// rs1==x12, rs2==x23, rd==x0,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x12; op2:x23; dest:x0; op1val:0x0; op2val:0x7c00; +valaddr_reg:x14; val_offset:4*FLEN/8; correctval:??; testreg:x6; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x0, x12, x23, 0, 0, x14, 4*FLEN/8, x19, x8, x6) +RVTEST_SIGBASE(x15,signature_x15_0) + +inst_15:// rs1==x8, rs2==x10, rd==x2,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x8; op2:x10; dest:x2; op1val:0x0; op2val:0xfc00; +valaddr_reg:x14; val_offset:6*FLEN/8; correctval:??; testreg:x6; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x2, x8, x10, 0, 0, x14, 6*FLEN/8, x19, x15, x6) + +inst_16:// rs1==x30, rs2==x17, rd==x3,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x17; dest:x3; op1val:0x0; op2val:0x7e00; +valaddr_reg:x14; val_offset:8*FLEN/8; correctval:??; testreg:x6; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x3, x30, x17, 0, 0, x14, 8*FLEN/8, x19, x15, x6) + +inst_17:// rs1==x25, rs2==x20, rd==x28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x25; op2:x20; dest:x28; op1val:0x0; op2val:0xfe00; +valaddr_reg:x14; val_offset:10*FLEN/8; correctval:??; testreg:x6; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x28, x25, x20, 0, 0, x14, 10*FLEN/8, x19, x15, x6) + +inst_18:// rs1==x20, rs2==x1, rd==x23,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x20; op2:x1; dest:x23; op1val:0x0; op2val:0x7e01; +valaddr_reg:x14; val_offset:12*FLEN/8; correctval:??; testreg:x6; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x23, x20, x1, 0, 0, x14, 12*FLEN/8, x19, x15, x6) + +inst_19:// rs1==x9, rs2==x30, rd==x12,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x9; op2:x30; dest:x12; op1val:0x0; op2val:0xfe55; +valaddr_reg:x14; val_offset:14*FLEN/8; correctval:??; testreg:x6; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x12, x9, x30, 0, 0, x14, 14*FLEN/8, x19, x15, x6) + +inst_20:// rs1==x10, rs2==x13, rd==x4,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x10; op2:x13; dest:x4; op1val:0x0; op2val:0x7c01; +valaddr_reg:x14; val_offset:16*FLEN/8; correctval:??; testreg:x6; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x4, x10, x13, 0, 0, x14, 16*FLEN/8, x19, x15, x6) + +inst_21:// rs1==x3, rs2==x5, rd==x11,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x3; op2:x5; dest:x11; op1val:0x0; op2val:0xfd55; +valaddr_reg:x14; val_offset:18*FLEN/8; correctval:??; testreg:x6; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x11, x3, x5, 0, 0, x14, 18*FLEN/8, x19, x15, x6) + +inst_22:// rs1==x23, rs2==x27, rd==x20,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x23; op2:x27; dest:x20; op1val:0x0; op2val:0x3c00; +valaddr_reg:x14; val_offset:20*FLEN/8; correctval:??; testreg:x6; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x20, x23, x27, 0, 0, x14, 20*FLEN/8, x19, x15, x6) + +inst_23:// rs1==x31, rs2==x28, rd==x8,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x31; op2:x28; dest:x8; op1val:0x0; op2val:0xbc00; +valaddr_reg:x14; val_offset:22*FLEN/8; correctval:??; testreg:x6; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x8, x31, x28, 0, 0, x14, 22*FLEN/8, x19, x15, x6) + +inst_24:// rs1==x16, rs2==x8, rd==x7,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x16; op2:x8; dest:x7; op1val:0x8000; op2val:0x0; +valaddr_reg:x14; val_offset:24*FLEN/8; correctval:??; testreg:x6; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x7, x16, x8, 0, 0, x14, 24*FLEN/8, x19, x15, x6) +RVTEST_VALBASEUPD(x4,test_dataset_2) + +inst_25:// rs1==x27, rs2==x16, rd==x17,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x27; op2:x16; dest:x17; op1val:0x8000; op2val:0x8000; +valaddr_reg:x4; val_offset:0*FLEN/8; correctval:??; testreg:x6; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x17, x27, x16, 0, 0, x4, 0*FLEN/8, x5, x15, x6) + +inst_26:// rs1==x21, rs2==x22, rd==x30,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x21; op2:x22; dest:x30; op1val:0x8000; op2val:0x1; +valaddr_reg:x4; val_offset:2*FLEN/8; correctval:??; testreg:x6; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x30, x21, x22, 0, 0, x4, 2*FLEN/8, x5, x15, x6) + +inst_27:// rs1==x14, rs2==x0, rd==x16,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x14; op2:x0; dest:x16; op1val:0x8000; op2val:0x0; +valaddr_reg:x4; val_offset:4*FLEN/8; correctval:??; testreg:x6; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x16, x14, x0, 0, 0, x4, 4*FLEN/8, x5, x15, x6) + +inst_28:// rs1==x19, rs2==x2, rd==x31,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x19; op2:x2; dest:x31; op1val:0x8000; op2val:0x2; +valaddr_reg:x4; val_offset:6*FLEN/8; correctval:??; testreg:x6; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x19, x2, 0, 0, x4, 6*FLEN/8, x5, x15, x6) + +inst_29:// rs1==x17, rs2==x6, rd==x21,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x17; op2:x6; dest:x21; op1val:0x8000; op2val:0x83fe; +valaddr_reg:x4; val_offset:8*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x21, x17, x6, 0, 0, x4, 8*FLEN/8, x5, x15, x3) +RVTEST_SIGBASE(x2,signature_x2_0) + +inst_30:// rs1==x1, rs2==x7, rd==x15,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x1; op2:x7; dest:x15; op1val:0x8000; op2val:0x3ff; +valaddr_reg:x4; val_offset:10*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x15, x1, x7, 0, 0, x4, 10*FLEN/8, x5, x2, x3) + +inst_31:// rs1==x6, rs2==x19, rd==x26,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x6; op2:x19; dest:x26; op1val:0x8000; op2val:0x83ff; +valaddr_reg:x4; val_offset:12*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x26, x6, x19, 0, 0, x4, 12*FLEN/8, x5, x2, x3) + +inst_32:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x400; +valaddr_reg:x4; val_offset:14*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 14*FLEN/8, x5, x2, x3) + +inst_33:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8400; +valaddr_reg:x4; val_offset:16*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 16*FLEN/8, x5, x2, x3) + +inst_34:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x401; +valaddr_reg:x4; val_offset:18*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 18*FLEN/8, x5, x2, x3) + +inst_35:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8455; +valaddr_reg:x4; val_offset:20*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 20*FLEN/8, x5, x2, x3) + +inst_36:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x7bff; +valaddr_reg:x4; val_offset:22*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 22*FLEN/8, x5, x2, x3) + +inst_37:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xfbff; +valaddr_reg:x4; val_offset:24*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 24*FLEN/8, x5, x2, x3) + +inst_38:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x7c00; +valaddr_reg:x4; val_offset:26*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 26*FLEN/8, x5, x2, x3) + +inst_39:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xfc00; +valaddr_reg:x4; val_offset:28*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 28*FLEN/8, x5, x2, x3) + +inst_40:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x7e00; +valaddr_reg:x4; val_offset:30*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 30*FLEN/8, x5, x2, x3) + +inst_41:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xfe00; +valaddr_reg:x4; val_offset:32*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 32*FLEN/8, x5, x2, x3) + +inst_42:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x7e01; +valaddr_reg:x4; val_offset:34*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 34*FLEN/8, x5, x2, x3) + +inst_43:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xfe55; +valaddr_reg:x4; val_offset:36*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 36*FLEN/8, x5, x2, x3) + +inst_44:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x7c01; +valaddr_reg:x4; val_offset:38*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 38*FLEN/8, x5, x2, x3) + +inst_45:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xfd55; +valaddr_reg:x4; val_offset:40*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 40*FLEN/8, x5, x2, x3) + +inst_46:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x3c00; +valaddr_reg:x4; val_offset:42*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 42*FLEN/8, x5, x2, x3) + +inst_47:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xbc00; +valaddr_reg:x4; val_offset:44*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 44*FLEN/8, x5, x2, x3) + +inst_48:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x0; +valaddr_reg:x4; val_offset:46*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 46*FLEN/8, x5, x2, x3) + +inst_49:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x8000; +valaddr_reg:x4; val_offset:48*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 48*FLEN/8, x5, x2, x3) + +inst_50:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x1; +valaddr_reg:x4; val_offset:50*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 50*FLEN/8, x5, x2, x3) + +inst_51:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x8001; +valaddr_reg:x4; val_offset:52*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 52*FLEN/8, x5, x2, x3) + +inst_52:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x2; +valaddr_reg:x4; val_offset:54*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 54*FLEN/8, x5, x2, x3) + +inst_53:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x83fe; +valaddr_reg:x4; val_offset:56*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 56*FLEN/8, x5, x2, x3) + +inst_54:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x3ff; +valaddr_reg:x4; val_offset:58*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 58*FLEN/8, x5, x2, x3) + +inst_55:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x83ff; +valaddr_reg:x4; val_offset:60*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 60*FLEN/8, x5, x2, x3) + +inst_56:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x400; +valaddr_reg:x4; val_offset:62*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 62*FLEN/8, x5, x2, x3) + +inst_57:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x8400; +valaddr_reg:x4; val_offset:64*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 64*FLEN/8, x5, x2, x3) + +inst_58:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x401; +valaddr_reg:x4; val_offset:66*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 66*FLEN/8, x5, x2, x3) + +inst_59:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x8455; +valaddr_reg:x4; val_offset:68*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 68*FLEN/8, x5, x2, x3) + +inst_60:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7bff; +valaddr_reg:x4; val_offset:70*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 70*FLEN/8, x5, x2, x3) + +inst_61:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xfbff; +valaddr_reg:x4; val_offset:72*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 72*FLEN/8, x5, x2, x3) + +inst_62:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7c00; +valaddr_reg:x4; val_offset:74*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 74*FLEN/8, x5, x2, x3) + +inst_63:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xfc00; +valaddr_reg:x4; val_offset:76*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 76*FLEN/8, x5, x2, x3) + +inst_64:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7e00; +valaddr_reg:x4; val_offset:78*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 78*FLEN/8, x5, x2, x3) + +inst_65:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xfe00; +valaddr_reg:x4; val_offset:80*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 80*FLEN/8, x5, x2, x3) + +inst_66:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7e01; +valaddr_reg:x4; val_offset:82*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 82*FLEN/8, x5, x2, x3) + +inst_67:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xfe55; +valaddr_reg:x4; val_offset:84*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 84*FLEN/8, x5, x2, x3) + +inst_68:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7c01; +valaddr_reg:x4; val_offset:86*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 86*FLEN/8, x5, x2, x3) + +inst_69:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xfd55; +valaddr_reg:x4; val_offset:88*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 88*FLEN/8, x5, x2, x3) + +inst_70:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x3c00; +valaddr_reg:x4; val_offset:90*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 90*FLEN/8, x5, x2, x3) + +inst_71:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xbc00; +valaddr_reg:x4; val_offset:92*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 92*FLEN/8, x5, x2, x3) + +inst_72:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x0; +valaddr_reg:x4; val_offset:94*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 94*FLEN/8, x5, x2, x3) + +inst_73:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8000; +valaddr_reg:x4; val_offset:96*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 96*FLEN/8, x5, x2, x3) + +inst_74:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x1; +valaddr_reg:x4; val_offset:98*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 98*FLEN/8, x5, x2, x3) + +inst_75:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8001; +valaddr_reg:x4; val_offset:100*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 100*FLEN/8, x5, x2, x3) + +inst_76:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x2; +valaddr_reg:x4; val_offset:102*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 102*FLEN/8, x5, x2, x3) + +inst_77:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x83fe; +valaddr_reg:x4; val_offset:104*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 104*FLEN/8, x5, x2, x3) + +inst_78:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x3ff; +valaddr_reg:x4; val_offset:106*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 106*FLEN/8, x5, x2, x3) + +inst_79:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x83ff; +valaddr_reg:x4; val_offset:108*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 108*FLEN/8, x5, x2, x3) + +inst_80:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x400; +valaddr_reg:x4; val_offset:110*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 110*FLEN/8, x5, x2, x3) + +inst_81:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8400; +valaddr_reg:x4; val_offset:112*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 112*FLEN/8, x5, x2, x3) + +inst_82:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x401; +valaddr_reg:x4; val_offset:114*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 114*FLEN/8, x5, x2, x3) + +inst_83:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8455; +valaddr_reg:x4; val_offset:116*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 116*FLEN/8, x5, x2, x3) + +inst_84:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x7bff; +valaddr_reg:x4; val_offset:118*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 118*FLEN/8, x5, x2, x3) + +inst_85:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xfbff; +valaddr_reg:x4; val_offset:120*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 120*FLEN/8, x5, x2, x3) + +inst_86:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x7c00; +valaddr_reg:x4; val_offset:122*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 122*FLEN/8, x5, x2, x3) + +inst_87:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xfc00; +valaddr_reg:x4; val_offset:124*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 124*FLEN/8, x5, x2, x3) + +inst_88:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x7e00; +valaddr_reg:x4; val_offset:126*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 126*FLEN/8, x5, x2, x3) + +inst_89:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xfe00; +valaddr_reg:x4; val_offset:128*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 128*FLEN/8, x5, x2, x3) + +inst_90:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x7e01; +valaddr_reg:x4; val_offset:130*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 130*FLEN/8, x5, x2, x3) + +inst_91:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xfe55; +valaddr_reg:x4; val_offset:132*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 132*FLEN/8, x5, x2, x3) + +inst_92:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x7c01; +valaddr_reg:x4; val_offset:134*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 134*FLEN/8, x5, x2, x3) + +inst_93:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xfd55; +valaddr_reg:x4; val_offset:136*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 136*FLEN/8, x5, x2, x3) + +inst_94:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x3c00; +valaddr_reg:x4; val_offset:138*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 138*FLEN/8, x5, x2, x3) + +inst_95:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xbc00; +valaddr_reg:x4; val_offset:140*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 140*FLEN/8, x5, x2, x3) + +inst_96:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x0; +valaddr_reg:x4; val_offset:142*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 142*FLEN/8, x5, x2, x3) + +inst_97:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x8000; +valaddr_reg:x4; val_offset:144*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 144*FLEN/8, x5, x2, x3) + +inst_98:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x1; +valaddr_reg:x4; val_offset:146*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 146*FLEN/8, x5, x2, x3) + +inst_99:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x8001; +valaddr_reg:x4; val_offset:148*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 148*FLEN/8, x5, x2, x3) + +inst_100:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x2; +valaddr_reg:x4; val_offset:150*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 150*FLEN/8, x5, x2, x3) + +inst_101:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x83fe; +valaddr_reg:x4; val_offset:152*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 152*FLEN/8, x5, x2, x3) + +inst_102:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x3ff; +valaddr_reg:x4; val_offset:154*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 154*FLEN/8, x5, x2, x3) + +inst_103:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x83ff; +valaddr_reg:x4; val_offset:156*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 156*FLEN/8, x5, x2, x3) + +inst_104:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x400; +valaddr_reg:x4; val_offset:158*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 158*FLEN/8, x5, x2, x3) + +inst_105:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x8400; +valaddr_reg:x4; val_offset:160*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 160*FLEN/8, x5, x2, x3) + +inst_106:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x401; +valaddr_reg:x4; val_offset:162*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 162*FLEN/8, x5, x2, x3) + +inst_107:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x8455; +valaddr_reg:x4; val_offset:164*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 164*FLEN/8, x5, x2, x3) + +inst_108:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x7bff; +valaddr_reg:x4; val_offset:166*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 166*FLEN/8, x5, x2, x3) + +inst_109:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xfbff; +valaddr_reg:x4; val_offset:168*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 168*FLEN/8, x5, x2, x3) + +inst_110:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x7c00; +valaddr_reg:x4; val_offset:170*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 170*FLEN/8, x5, x2, x3) + +inst_111:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xfc00; +valaddr_reg:x4; val_offset:172*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 172*FLEN/8, x5, x2, x3) + +inst_112:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x7e00; +valaddr_reg:x4; val_offset:174*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 174*FLEN/8, x5, x2, x3) + +inst_113:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xfe00; +valaddr_reg:x4; val_offset:176*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 176*FLEN/8, x5, x2, x3) + +inst_114:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x7e01; +valaddr_reg:x4; val_offset:178*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 178*FLEN/8, x5, x2, x3) + +inst_115:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xfe55; +valaddr_reg:x4; val_offset:180*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 180*FLEN/8, x5, x2, x3) + +inst_116:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x7c01; +valaddr_reg:x4; val_offset:182*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 182*FLEN/8, x5, x2, x3) + +inst_117:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xfd55; +valaddr_reg:x4; val_offset:184*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 184*FLEN/8, x5, x2, x3) + +inst_118:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x3c00; +valaddr_reg:x4; val_offset:186*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 186*FLEN/8, x5, x2, x3) + +inst_119:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xbc00; +valaddr_reg:x4; val_offset:188*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 188*FLEN/8, x5, x2, x3) + +inst_120:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x0; +valaddr_reg:x4; val_offset:190*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 190*FLEN/8, x5, x2, x3) + +inst_121:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x8000; +valaddr_reg:x4; val_offset:192*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 192*FLEN/8, x5, x2, x3) + +inst_122:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x1; +valaddr_reg:x4; val_offset:194*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 194*FLEN/8, x5, x2, x3) + +inst_123:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x8001; +valaddr_reg:x4; val_offset:196*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 196*FLEN/8, x5, x2, x3) + +inst_124:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x2; +valaddr_reg:x4; val_offset:198*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 198*FLEN/8, x5, x2, x3) + +inst_125:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x83fe; +valaddr_reg:x4; val_offset:200*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 200*FLEN/8, x5, x2, x3) + +inst_126:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x3ff; +valaddr_reg:x4; val_offset:202*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 202*FLEN/8, x5, x2, x3) + +inst_127:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x83ff; +valaddr_reg:x4; val_offset:204*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 204*FLEN/8, x5, x2, x3) + +inst_128:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x400; +valaddr_reg:x4; val_offset:206*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 206*FLEN/8, x5, x2, x3) + +inst_129:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x8400; +valaddr_reg:x4; val_offset:208*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 208*FLEN/8, x5, x2, x3) + +inst_130:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x401; +valaddr_reg:x4; val_offset:210*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 210*FLEN/8, x5, x2, x3) + +inst_131:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x8455; +valaddr_reg:x4; val_offset:212*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 212*FLEN/8, x5, x2, x3) + +inst_132:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x7bff; +valaddr_reg:x4; val_offset:214*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 214*FLEN/8, x5, x2, x3) + +inst_133:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xfbff; +valaddr_reg:x4; val_offset:216*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 216*FLEN/8, x5, x2, x3) + +inst_134:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x7c00; +valaddr_reg:x4; val_offset:218*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 218*FLEN/8, x5, x2, x3) + +inst_135:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xfc00; +valaddr_reg:x4; val_offset:220*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 220*FLEN/8, x5, x2, x3) + +inst_136:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x7e00; +valaddr_reg:x4; val_offset:222*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 222*FLEN/8, x5, x2, x3) + +inst_137:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xfe00; +valaddr_reg:x4; val_offset:224*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 224*FLEN/8, x5, x2, x3) + +inst_138:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x7e01; +valaddr_reg:x4; val_offset:226*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 226*FLEN/8, x5, x2, x3) + +inst_139:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xfe55; +valaddr_reg:x4; val_offset:228*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 228*FLEN/8, x5, x2, x3) + +inst_140:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x7c01; +valaddr_reg:x4; val_offset:230*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 230*FLEN/8, x5, x2, x3) + +inst_141:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xfd55; +valaddr_reg:x4; val_offset:232*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 232*FLEN/8, x5, x2, x3) + +inst_142:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x3c00; +valaddr_reg:x4; val_offset:234*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 234*FLEN/8, x5, x2, x3) + +inst_143:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xbc00; +valaddr_reg:x4; val_offset:236*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 236*FLEN/8, x5, x2, x3) + +inst_144:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x0; +valaddr_reg:x4; val_offset:238*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 238*FLEN/8, x5, x2, x3) + +inst_145:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x8000; +valaddr_reg:x4; val_offset:240*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 240*FLEN/8, x5, x2, x3) + +inst_146:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x1; +valaddr_reg:x4; val_offset:242*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 242*FLEN/8, x5, x2, x3) + +inst_147:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x8001; +valaddr_reg:x4; val_offset:244*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 244*FLEN/8, x5, x2, x3) + +inst_148:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x2; +valaddr_reg:x4; val_offset:246*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 246*FLEN/8, x5, x2, x3) + +inst_149:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x83fe; +valaddr_reg:x4; val_offset:248*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 248*FLEN/8, x5, x2, x3) + +inst_150:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x3ff; +valaddr_reg:x4; val_offset:250*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 250*FLEN/8, x5, x2, x3) + +inst_151:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x83ff; +valaddr_reg:x4; val_offset:252*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 252*FLEN/8, x5, x2, x3) + +inst_152:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x400; +valaddr_reg:x4; val_offset:254*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 254*FLEN/8, x5, x2, x3) + +inst_153:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x8400; +valaddr_reg:x4; val_offset:256*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 256*FLEN/8, x5, x2, x3) + +inst_154:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x401; +valaddr_reg:x4; val_offset:258*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 258*FLEN/8, x5, x2, x3) + +inst_155:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x8455; +valaddr_reg:x4; val_offset:260*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 260*FLEN/8, x5, x2, x3) + +inst_156:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7bff; +valaddr_reg:x4; val_offset:262*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 262*FLEN/8, x5, x2, x3) + +inst_157:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xfbff; +valaddr_reg:x4; val_offset:264*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 264*FLEN/8, x5, x2, x3) +RVTEST_SIGBASE(x2,signature_x2_1) + +inst_158:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7c00; +valaddr_reg:x4; val_offset:266*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 266*FLEN/8, x5, x2, x3) + +inst_159:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xfc00; +valaddr_reg:x4; val_offset:268*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 268*FLEN/8, x5, x2, x3) + +inst_160:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7e00; +valaddr_reg:x4; val_offset:270*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 270*FLEN/8, x5, x2, x3) + +inst_161:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xfe00; +valaddr_reg:x4; val_offset:272*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 272*FLEN/8, x5, x2, x3) + +inst_162:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7e01; +valaddr_reg:x4; val_offset:274*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 274*FLEN/8, x5, x2, x3) + +inst_163:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xfe55; +valaddr_reg:x4; val_offset:276*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 276*FLEN/8, x5, x2, x3) + +inst_164:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7c01; +valaddr_reg:x4; val_offset:278*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 278*FLEN/8, x5, x2, x3) + +inst_165:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xfd55; +valaddr_reg:x4; val_offset:280*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 280*FLEN/8, x5, x2, x3) + +inst_166:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x3c00; +valaddr_reg:x4; val_offset:282*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 282*FLEN/8, x5, x2, x3) + +inst_167:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xbc00; +valaddr_reg:x4; val_offset:284*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 284*FLEN/8, x5, x2, x3) + +inst_168:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x0; +valaddr_reg:x4; val_offset:286*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 286*FLEN/8, x5, x2, x3) + +inst_169:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8000; +valaddr_reg:x4; val_offset:288*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 288*FLEN/8, x5, x2, x3) + +inst_170:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x1; +valaddr_reg:x4; val_offset:290*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 290*FLEN/8, x5, x2, x3) + +inst_171:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8001; +valaddr_reg:x4; val_offset:292*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 292*FLEN/8, x5, x2, x3) + +inst_172:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x2; +valaddr_reg:x4; val_offset:294*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 294*FLEN/8, x5, x2, x3) + +inst_173:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x83fe; +valaddr_reg:x4; val_offset:296*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 296*FLEN/8, x5, x2, x3) + +inst_174:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x3ff; +valaddr_reg:x4; val_offset:298*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 298*FLEN/8, x5, x2, x3) + +inst_175:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x83ff; +valaddr_reg:x4; val_offset:300*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 300*FLEN/8, x5, x2, x3) + +inst_176:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x400; +valaddr_reg:x4; val_offset:302*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 302*FLEN/8, x5, x2, x3) + +inst_177:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8400; +valaddr_reg:x4; val_offset:304*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 304*FLEN/8, x5, x2, x3) + +inst_178:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x401; +valaddr_reg:x4; val_offset:306*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 306*FLEN/8, x5, x2, x3) + +inst_179:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8455; +valaddr_reg:x4; val_offset:308*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 308*FLEN/8, x5, x2, x3) + +inst_180:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x7bff; +valaddr_reg:x4; val_offset:310*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 310*FLEN/8, x5, x2, x3) + +inst_181:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xfbff; +valaddr_reg:x4; val_offset:312*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 312*FLEN/8, x5, x2, x3) + +inst_182:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x7c00; +valaddr_reg:x4; val_offset:314*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 314*FLEN/8, x5, x2, x3) + +inst_183:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xfc00; +valaddr_reg:x4; val_offset:316*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 316*FLEN/8, x5, x2, x3) + +inst_184:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x7e00; +valaddr_reg:x4; val_offset:318*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 318*FLEN/8, x5, x2, x3) + +inst_185:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xfe00; +valaddr_reg:x4; val_offset:320*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 320*FLEN/8, x5, x2, x3) + +inst_186:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x7e01; +valaddr_reg:x4; val_offset:322*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 322*FLEN/8, x5, x2, x3) + +inst_187:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xfe55; +valaddr_reg:x4; val_offset:324*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 324*FLEN/8, x5, x2, x3) + +inst_188:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x7c01; +valaddr_reg:x4; val_offset:326*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 326*FLEN/8, x5, x2, x3) + +inst_189:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xfd55; +valaddr_reg:x4; val_offset:328*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 328*FLEN/8, x5, x2, x3) + +inst_190:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x3c00; +valaddr_reg:x4; val_offset:330*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 330*FLEN/8, x5, x2, x3) + +inst_191:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xbc00; +valaddr_reg:x4; val_offset:332*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 332*FLEN/8, x5, x2, x3) + +inst_192:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x0; +valaddr_reg:x4; val_offset:334*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 334*FLEN/8, x5, x2, x3) + +inst_193:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x8000; +valaddr_reg:x4; val_offset:336*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 336*FLEN/8, x5, x2, x3) + +inst_194:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x1; +valaddr_reg:x4; val_offset:338*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 338*FLEN/8, x5, x2, x3) + +inst_195:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x8001; +valaddr_reg:x4; val_offset:340*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 340*FLEN/8, x5, x2, x3) + +inst_196:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x2; +valaddr_reg:x4; val_offset:342*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 342*FLEN/8, x5, x2, x3) + +inst_197:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x83fe; +valaddr_reg:x4; val_offset:344*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 344*FLEN/8, x5, x2, x3) + +inst_198:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x3ff; +valaddr_reg:x4; val_offset:346*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 346*FLEN/8, x5, x2, x3) + +inst_199:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x83ff; +valaddr_reg:x4; val_offset:348*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 348*FLEN/8, x5, x2, x3) + +inst_200:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x400; +valaddr_reg:x4; val_offset:350*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 350*FLEN/8, x5, x2, x3) + +inst_201:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x8400; +valaddr_reg:x4; val_offset:352*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 352*FLEN/8, x5, x2, x3) + +inst_202:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x401; +valaddr_reg:x4; val_offset:354*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 354*FLEN/8, x5, x2, x3) + +inst_203:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x8455; +valaddr_reg:x4; val_offset:356*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 356*FLEN/8, x5, x2, x3) + +inst_204:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7bff; +valaddr_reg:x4; val_offset:358*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 358*FLEN/8, x5, x2, x3) + +inst_205:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xfbff; +valaddr_reg:x4; val_offset:360*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 360*FLEN/8, x5, x2, x3) + +inst_206:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7c00; +valaddr_reg:x4; val_offset:362*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 362*FLEN/8, x5, x2, x3) + +inst_207:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xfc00; +valaddr_reg:x4; val_offset:364*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 364*FLEN/8, x5, x2, x3) + +inst_208:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7e00; +valaddr_reg:x4; val_offset:366*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 366*FLEN/8, x5, x2, x3) + +inst_209:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xfe00; +valaddr_reg:x4; val_offset:368*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 368*FLEN/8, x5, x2, x3) + +inst_210:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7e01; +valaddr_reg:x4; val_offset:370*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 370*FLEN/8, x5, x2, x3) + +inst_211:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xfe55; +valaddr_reg:x4; val_offset:372*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 372*FLEN/8, x5, x2, x3) + +inst_212:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7c01; +valaddr_reg:x4; val_offset:374*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 374*FLEN/8, x5, x2, x3) + +inst_213:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xfd55; +valaddr_reg:x4; val_offset:376*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 376*FLEN/8, x5, x2, x3) + +inst_214:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x3c00; +valaddr_reg:x4; val_offset:378*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 378*FLEN/8, x5, x2, x3) + +inst_215:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xbc00; +valaddr_reg:x4; val_offset:380*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 380*FLEN/8, x5, x2, x3) + +inst_216:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x0; +valaddr_reg:x4; val_offset:382*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 382*FLEN/8, x5, x2, x3) + +inst_217:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8000; +valaddr_reg:x4; val_offset:384*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 384*FLEN/8, x5, x2, x3) + +inst_218:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x1; +valaddr_reg:x4; val_offset:386*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 386*FLEN/8, x5, x2, x3) + +inst_219:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8001; +valaddr_reg:x4; val_offset:388*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 388*FLEN/8, x5, x2, x3) + +inst_220:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x2; +valaddr_reg:x4; val_offset:390*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 390*FLEN/8, x5, x2, x3) + +inst_221:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x83fe; +valaddr_reg:x4; val_offset:392*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 392*FLEN/8, x5, x2, x3) + +inst_222:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x3ff; +valaddr_reg:x4; val_offset:394*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 394*FLEN/8, x5, x2, x3) + +inst_223:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x83ff; +valaddr_reg:x4; val_offset:396*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 396*FLEN/8, x5, x2, x3) + +inst_224:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x400; +valaddr_reg:x4; val_offset:398*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 398*FLEN/8, x5, x2, x3) + +inst_225:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8400; +valaddr_reg:x4; val_offset:400*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 400*FLEN/8, x5, x2, x3) + +inst_226:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x401; +valaddr_reg:x4; val_offset:402*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 402*FLEN/8, x5, x2, x3) + +inst_227:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8455; +valaddr_reg:x4; val_offset:404*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 404*FLEN/8, x5, x2, x3) + +inst_228:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x7bff; +valaddr_reg:x4; val_offset:406*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 406*FLEN/8, x5, x2, x3) + +inst_229:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xfbff; +valaddr_reg:x4; val_offset:408*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 408*FLEN/8, x5, x2, x3) + +inst_230:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x7c00; +valaddr_reg:x4; val_offset:410*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 410*FLEN/8, x5, x2, x3) + +inst_231:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xfc00; +valaddr_reg:x4; val_offset:412*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 412*FLEN/8, x5, x2, x3) + +inst_232:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x7e00; +valaddr_reg:x4; val_offset:414*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 414*FLEN/8, x5, x2, x3) + +inst_233:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xfe00; +valaddr_reg:x4; val_offset:416*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 416*FLEN/8, x5, x2, x3) + +inst_234:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x7e01; +valaddr_reg:x4; val_offset:418*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 418*FLEN/8, x5, x2, x3) + +inst_235:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xfe55; +valaddr_reg:x4; val_offset:420*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 420*FLEN/8, x5, x2, x3) + +inst_236:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x7c01; +valaddr_reg:x4; val_offset:422*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 422*FLEN/8, x5, x2, x3) + +inst_237:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xfd55; +valaddr_reg:x4; val_offset:424*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 424*FLEN/8, x5, x2, x3) + +inst_238:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x3c00; +valaddr_reg:x4; val_offset:426*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 426*FLEN/8, x5, x2, x3) + +inst_239:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xbc00; +valaddr_reg:x4; val_offset:428*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 428*FLEN/8, x5, x2, x3) + +inst_240:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x0; +valaddr_reg:x4; val_offset:430*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 430*FLEN/8, x5, x2, x3) + +inst_241:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x8000; +valaddr_reg:x4; val_offset:432*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 432*FLEN/8, x5, x2, x3) + +inst_242:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x1; +valaddr_reg:x4; val_offset:434*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 434*FLEN/8, x5, x2, x3) + +inst_243:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x8001; +valaddr_reg:x4; val_offset:436*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 436*FLEN/8, x5, x2, x3) + +inst_244:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x2; +valaddr_reg:x4; val_offset:438*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 438*FLEN/8, x5, x2, x3) + +inst_245:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x83fe; +valaddr_reg:x4; val_offset:440*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 440*FLEN/8, x5, x2, x3) + +inst_246:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x3ff; +valaddr_reg:x4; val_offset:442*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 442*FLEN/8, x5, x2, x3) + +inst_247:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x83ff; +valaddr_reg:x4; val_offset:444*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 444*FLEN/8, x5, x2, x3) + +inst_248:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x400; +valaddr_reg:x4; val_offset:446*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 446*FLEN/8, x5, x2, x3) + +inst_249:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x8400; +valaddr_reg:x4; val_offset:448*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 448*FLEN/8, x5, x2, x3) + +inst_250:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x401; +valaddr_reg:x4; val_offset:450*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 450*FLEN/8, x5, x2, x3) + +inst_251:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x8455; +valaddr_reg:x4; val_offset:452*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 452*FLEN/8, x5, x2, x3) + +inst_252:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x7bff; +valaddr_reg:x4; val_offset:454*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 454*FLEN/8, x5, x2, x3) + +inst_253:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xfbff; +valaddr_reg:x4; val_offset:456*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 456*FLEN/8, x5, x2, x3) + +inst_254:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x7c00; +valaddr_reg:x4; val_offset:458*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 458*FLEN/8, x5, x2, x3) + +inst_255:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xfc00; +valaddr_reg:x4; val_offset:460*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 460*FLEN/8, x5, x2, x3) + +inst_256:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x7e00; +valaddr_reg:x4; val_offset:462*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 462*FLEN/8, x5, x2, x3) + +inst_257:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xfe00; +valaddr_reg:x4; val_offset:464*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 464*FLEN/8, x5, x2, x3) + +inst_258:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x7e01; +valaddr_reg:x4; val_offset:466*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 466*FLEN/8, x5, x2, x3) + +inst_259:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xfe55; +valaddr_reg:x4; val_offset:468*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 468*FLEN/8, x5, x2, x3) + +inst_260:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x7c01; +valaddr_reg:x4; val_offset:470*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 470*FLEN/8, x5, x2, x3) + +inst_261:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xfd55; +valaddr_reg:x4; val_offset:472*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 472*FLEN/8, x5, x2, x3) + +inst_262:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x3c00; +valaddr_reg:x4; val_offset:474*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 474*FLEN/8, x5, x2, x3) + +inst_263:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xbc00; +valaddr_reg:x4; val_offset:476*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 476*FLEN/8, x5, x2, x3) + +inst_264:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x0; +valaddr_reg:x4; val_offset:478*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 478*FLEN/8, x5, x2, x3) + +inst_265:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x8000; +valaddr_reg:x4; val_offset:480*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 480*FLEN/8, x5, x2, x3) + +inst_266:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x1; +valaddr_reg:x4; val_offset:482*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 482*FLEN/8, x5, x2, x3) + +inst_267:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x8001; +valaddr_reg:x4; val_offset:484*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 484*FLEN/8, x5, x2, x3) + +inst_268:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x2; +valaddr_reg:x4; val_offset:486*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 486*FLEN/8, x5, x2, x3) + +inst_269:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x83fe; +valaddr_reg:x4; val_offset:488*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 488*FLEN/8, x5, x2, x3) + +inst_270:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x3ff; +valaddr_reg:x4; val_offset:490*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 490*FLEN/8, x5, x2, x3) + +inst_271:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x83ff; +valaddr_reg:x4; val_offset:492*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 492*FLEN/8, x5, x2, x3) + +inst_272:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x400; +valaddr_reg:x4; val_offset:494*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 494*FLEN/8, x5, x2, x3) + +inst_273:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x8400; +valaddr_reg:x4; val_offset:496*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 496*FLEN/8, x5, x2, x3) + +inst_274:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x401; +valaddr_reg:x4; val_offset:498*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 498*FLEN/8, x5, x2, x3) + +inst_275:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x8455; +valaddr_reg:x4; val_offset:500*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 500*FLEN/8, x5, x2, x3) + +inst_276:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x7bff; +valaddr_reg:x4; val_offset:502*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 502*FLEN/8, x5, x2, x3) + +inst_277:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xfbff; +valaddr_reg:x4; val_offset:504*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 504*FLEN/8, x5, x2, x3) + +inst_278:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x7c00; +valaddr_reg:x4; val_offset:506*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 506*FLEN/8, x5, x2, x3) + +inst_279:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xfc00; +valaddr_reg:x4; val_offset:508*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 508*FLEN/8, x5, x2, x3) + +inst_280:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x7e00; +valaddr_reg:x4; val_offset:510*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 510*FLEN/8, x5, x2, x3) + +inst_281:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xfe00; +valaddr_reg:x4; val_offset:512*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 512*FLEN/8, x5, x2, x3) + +inst_282:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x7e01; +valaddr_reg:x4; val_offset:514*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 514*FLEN/8, x5, x2, x3) + +inst_283:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xfe55; +valaddr_reg:x4; val_offset:516*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 516*FLEN/8, x5, x2, x3) + +inst_284:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x7c01; +valaddr_reg:x4; val_offset:518*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 518*FLEN/8, x5, x2, x3) + +inst_285:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xfd55; +valaddr_reg:x4; val_offset:520*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 520*FLEN/8, x5, x2, x3) +RVTEST_SIGBASE(x2,signature_x2_2) + +inst_286:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x3c00; +valaddr_reg:x4; val_offset:522*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 522*FLEN/8, x5, x2, x3) + +inst_287:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xbc00; +valaddr_reg:x4; val_offset:524*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 524*FLEN/8, x5, x2, x3) + +inst_288:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x0; +valaddr_reg:x4; val_offset:526*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 526*FLEN/8, x5, x2, x3) + +inst_289:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8000; +valaddr_reg:x4; val_offset:528*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 528*FLEN/8, x5, x2, x3) + +inst_290:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x1; +valaddr_reg:x4; val_offset:530*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 530*FLEN/8, x5, x2, x3) + +inst_291:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8001; +valaddr_reg:x4; val_offset:532*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 532*FLEN/8, x5, x2, x3) + +inst_292:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x2; +valaddr_reg:x4; val_offset:534*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 534*FLEN/8, x5, x2, x3) + +inst_293:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x83fe; +valaddr_reg:x4; val_offset:536*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 536*FLEN/8, x5, x2, x3) + +inst_294:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x3ff; +valaddr_reg:x4; val_offset:538*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 538*FLEN/8, x5, x2, x3) + +inst_295:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x83ff; +valaddr_reg:x4; val_offset:540*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 540*FLEN/8, x5, x2, x3) + +inst_296:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x400; +valaddr_reg:x4; val_offset:542*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 542*FLEN/8, x5, x2, x3) + +inst_297:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8400; +valaddr_reg:x4; val_offset:544*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 544*FLEN/8, x5, x2, x3) + +inst_298:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x401; +valaddr_reg:x4; val_offset:546*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 546*FLEN/8, x5, x2, x3) + +inst_299:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8455; +valaddr_reg:x4; val_offset:548*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 548*FLEN/8, x5, x2, x3) + +inst_300:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7bff; +valaddr_reg:x4; val_offset:550*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 550*FLEN/8, x5, x2, x3) + +inst_301:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xfbff; +valaddr_reg:x4; val_offset:552*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 552*FLEN/8, x5, x2, x3) + +inst_302:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7c00; +valaddr_reg:x4; val_offset:554*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 554*FLEN/8, x5, x2, x3) + +inst_303:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xfc00; +valaddr_reg:x4; val_offset:556*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 556*FLEN/8, x5, x2, x3) + +inst_304:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7e00; +valaddr_reg:x4; val_offset:558*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 558*FLEN/8, x5, x2, x3) + +inst_305:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xfe00; +valaddr_reg:x4; val_offset:560*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 560*FLEN/8, x5, x2, x3) + +inst_306:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7e01; +valaddr_reg:x4; val_offset:562*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 562*FLEN/8, x5, x2, x3) + +inst_307:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xfe55; +valaddr_reg:x4; val_offset:564*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 564*FLEN/8, x5, x2, x3) + +inst_308:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7c01; +valaddr_reg:x4; val_offset:566*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 566*FLEN/8, x5, x2, x3) + +inst_309:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xfd55; +valaddr_reg:x4; val_offset:568*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 568*FLEN/8, x5, x2, x3) + +inst_310:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x3c00; +valaddr_reg:x4; val_offset:570*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 570*FLEN/8, x5, x2, x3) + +inst_311:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xbc00; +valaddr_reg:x4; val_offset:572*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 572*FLEN/8, x5, x2, x3) + +inst_312:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x0; +valaddr_reg:x4; val_offset:574*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 574*FLEN/8, x5, x2, x3) + +inst_313:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8000; +valaddr_reg:x4; val_offset:576*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 576*FLEN/8, x5, x2, x3) + +inst_314:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x1; +valaddr_reg:x4; val_offset:578*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 578*FLEN/8, x5, x2, x3) + +inst_315:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8001; +valaddr_reg:x4; val_offset:580*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 580*FLEN/8, x5, x2, x3) + +inst_316:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x2; +valaddr_reg:x4; val_offset:582*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 582*FLEN/8, x5, x2, x3) + +inst_317:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x83fe; +valaddr_reg:x4; val_offset:584*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 584*FLEN/8, x5, x2, x3) + +inst_318:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x3ff; +valaddr_reg:x4; val_offset:586*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 586*FLEN/8, x5, x2, x3) + +inst_319:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x83ff; +valaddr_reg:x4; val_offset:588*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 588*FLEN/8, x5, x2, x3) + +inst_320:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x400; +valaddr_reg:x4; val_offset:590*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 590*FLEN/8, x5, x2, x3) + +inst_321:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8400; +valaddr_reg:x4; val_offset:592*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 592*FLEN/8, x5, x2, x3) + +inst_322:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x401; +valaddr_reg:x4; val_offset:594*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 594*FLEN/8, x5, x2, x3) + +inst_323:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8455; +valaddr_reg:x4; val_offset:596*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 596*FLEN/8, x5, x2, x3) + +inst_324:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7bff; +valaddr_reg:x4; val_offset:598*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 598*FLEN/8, x5, x2, x3) + +inst_325:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfbff; +valaddr_reg:x4; val_offset:600*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 600*FLEN/8, x5, x2, x3) + +inst_326:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7c00; +valaddr_reg:x4; val_offset:602*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 602*FLEN/8, x5, x2, x3) + +inst_327:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfc00; +valaddr_reg:x4; val_offset:604*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 604*FLEN/8, x5, x2, x3) + +inst_328:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7e00; +valaddr_reg:x4; val_offset:606*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 606*FLEN/8, x5, x2, x3) + +inst_329:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfe00; +valaddr_reg:x4; val_offset:608*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 608*FLEN/8, x5, x2, x3) + +inst_330:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7e01; +valaddr_reg:x4; val_offset:610*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 610*FLEN/8, x5, x2, x3) + +inst_331:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfe55; +valaddr_reg:x4; val_offset:612*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 612*FLEN/8, x5, x2, x3) + +inst_332:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7c01; +valaddr_reg:x4; val_offset:614*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 614*FLEN/8, x5, x2, x3) + +inst_333:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfd55; +valaddr_reg:x4; val_offset:616*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 616*FLEN/8, x5, x2, x3) + +inst_334:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x3c00; +valaddr_reg:x4; val_offset:618*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 618*FLEN/8, x5, x2, x3) + +inst_335:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xbc00; +valaddr_reg:x4; val_offset:620*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 620*FLEN/8, x5, x2, x3) + +inst_336:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x0; +valaddr_reg:x4; val_offset:622*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 622*FLEN/8, x5, x2, x3) + +inst_337:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x8000; +valaddr_reg:x4; val_offset:624*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 624*FLEN/8, x5, x2, x3) + +inst_338:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x1; +valaddr_reg:x4; val_offset:626*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 626*FLEN/8, x5, x2, x3) + +inst_339:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x8001; +valaddr_reg:x4; val_offset:628*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 628*FLEN/8, x5, x2, x3) + +inst_340:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x2; +valaddr_reg:x4; val_offset:630*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 630*FLEN/8, x5, x2, x3) + +inst_341:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x83fe; +valaddr_reg:x4; val_offset:632*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 632*FLEN/8, x5, x2, x3) + +inst_342:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x3ff; +valaddr_reg:x4; val_offset:634*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 634*FLEN/8, x5, x2, x3) + +inst_343:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x83ff; +valaddr_reg:x4; val_offset:636*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 636*FLEN/8, x5, x2, x3) + +inst_344:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x400; +valaddr_reg:x4; val_offset:638*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 638*FLEN/8, x5, x2, x3) + +inst_345:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x8400; +valaddr_reg:x4; val_offset:640*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 640*FLEN/8, x5, x2, x3) + +inst_346:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x401; +valaddr_reg:x4; val_offset:642*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 642*FLEN/8, x5, x2, x3) + +inst_347:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x8455; +valaddr_reg:x4; val_offset:644*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 644*FLEN/8, x5, x2, x3) + +inst_348:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x7bff; +valaddr_reg:x4; val_offset:646*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 646*FLEN/8, x5, x2, x3) + +inst_349:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xfbff; +valaddr_reg:x4; val_offset:648*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 648*FLEN/8, x5, x2, x3) + +inst_350:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x7c00; +valaddr_reg:x4; val_offset:650*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 650*FLEN/8, x5, x2, x3) + +inst_351:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xfc00; +valaddr_reg:x4; val_offset:652*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 652*FLEN/8, x5, x2, x3) + +inst_352:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x7e00; +valaddr_reg:x4; val_offset:654*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 654*FLEN/8, x5, x2, x3) + +inst_353:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xfe00; +valaddr_reg:x4; val_offset:656*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 656*FLEN/8, x5, x2, x3) + +inst_354:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x7e01; +valaddr_reg:x4; val_offset:658*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 658*FLEN/8, x5, x2, x3) + +inst_355:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xfe55; +valaddr_reg:x4; val_offset:660*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 660*FLEN/8, x5, x2, x3) + +inst_356:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x7c01; +valaddr_reg:x4; val_offset:662*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 662*FLEN/8, x5, x2, x3) + +inst_357:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xfd55; +valaddr_reg:x4; val_offset:664*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 664*FLEN/8, x5, x2, x3) + +inst_358:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x3c00; +valaddr_reg:x4; val_offset:666*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 666*FLEN/8, x5, x2, x3) + +inst_359:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xbc00; +valaddr_reg:x4; val_offset:668*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 668*FLEN/8, x5, x2, x3) + +inst_360:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x0; +valaddr_reg:x4; val_offset:670*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 670*FLEN/8, x5, x2, x3) + +inst_361:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x8000; +valaddr_reg:x4; val_offset:672*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 672*FLEN/8, x5, x2, x3) + +inst_362:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x1; +valaddr_reg:x4; val_offset:674*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 674*FLEN/8, x5, x2, x3) + +inst_363:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x8001; +valaddr_reg:x4; val_offset:676*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 676*FLEN/8, x5, x2, x3) + +inst_364:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x2; +valaddr_reg:x4; val_offset:678*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 678*FLEN/8, x5, x2, x3) + +inst_365:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x83fe; +valaddr_reg:x4; val_offset:680*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 680*FLEN/8, x5, x2, x3) + +inst_366:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x3ff; +valaddr_reg:x4; val_offset:682*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 682*FLEN/8, x5, x2, x3) + +inst_367:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x83ff; +valaddr_reg:x4; val_offset:684*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 684*FLEN/8, x5, x2, x3) + +inst_368:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x400; +valaddr_reg:x4; val_offset:686*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 686*FLEN/8, x5, x2, x3) + +inst_369:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x8400; +valaddr_reg:x4; val_offset:688*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 688*FLEN/8, x5, x2, x3) + +inst_370:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x401; +valaddr_reg:x4; val_offset:690*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 690*FLEN/8, x5, x2, x3) + +inst_371:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x8455; +valaddr_reg:x4; val_offset:692*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 692*FLEN/8, x5, x2, x3) + +inst_372:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x7bff; +valaddr_reg:x4; val_offset:694*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 694*FLEN/8, x5, x2, x3) + +inst_373:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xfbff; +valaddr_reg:x4; val_offset:696*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 696*FLEN/8, x5, x2, x3) + +inst_374:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x7c00; +valaddr_reg:x4; val_offset:698*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 698*FLEN/8, x5, x2, x3) + +inst_375:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xfc00; +valaddr_reg:x4; val_offset:700*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 700*FLEN/8, x5, x2, x3) + +inst_376:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x7e00; +valaddr_reg:x4; val_offset:702*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 702*FLEN/8, x5, x2, x3) + +inst_377:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xfe00; +valaddr_reg:x4; val_offset:704*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 704*FLEN/8, x5, x2, x3) + +inst_378:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x7e01; +valaddr_reg:x4; val_offset:706*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 706*FLEN/8, x5, x2, x3) + +inst_379:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xfe55; +valaddr_reg:x4; val_offset:708*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 708*FLEN/8, x5, x2, x3) + +inst_380:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x7c01; +valaddr_reg:x4; val_offset:710*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 710*FLEN/8, x5, x2, x3) + +inst_381:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xfd55; +valaddr_reg:x4; val_offset:712*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 712*FLEN/8, x5, x2, x3) + +inst_382:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x3c00; +valaddr_reg:x4; val_offset:714*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 714*FLEN/8, x5, x2, x3) + +inst_383:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xbc00; +valaddr_reg:x4; val_offset:716*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 716*FLEN/8, x5, x2, x3) + +inst_384:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x0; +valaddr_reg:x4; val_offset:718*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 718*FLEN/8, x5, x2, x3) + +inst_385:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x8000; +valaddr_reg:x4; val_offset:720*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 720*FLEN/8, x5, x2, x3) + +inst_386:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x1; +valaddr_reg:x4; val_offset:722*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 722*FLEN/8, x5, x2, x3) + +inst_387:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x8001; +valaddr_reg:x4; val_offset:724*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 724*FLEN/8, x5, x2, x3) + +inst_388:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x2; +valaddr_reg:x4; val_offset:726*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 726*FLEN/8, x5, x2, x3) + +inst_389:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x83fe; +valaddr_reg:x4; val_offset:728*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 728*FLEN/8, x5, x2, x3) + +inst_390:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x3ff; +valaddr_reg:x4; val_offset:730*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 730*FLEN/8, x5, x2, x3) + +inst_391:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x83ff; +valaddr_reg:x4; val_offset:732*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 732*FLEN/8, x5, x2, x3) + +inst_392:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x400; +valaddr_reg:x4; val_offset:734*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 734*FLEN/8, x5, x2, x3) + +inst_393:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x8400; +valaddr_reg:x4; val_offset:736*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 736*FLEN/8, x5, x2, x3) + +inst_394:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x401; +valaddr_reg:x4; val_offset:738*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 738*FLEN/8, x5, x2, x3) + +inst_395:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x8455; +valaddr_reg:x4; val_offset:740*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 740*FLEN/8, x5, x2, x3) + +inst_396:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x7bff; +valaddr_reg:x4; val_offset:742*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 742*FLEN/8, x5, x2, x3) + +inst_397:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xfbff; +valaddr_reg:x4; val_offset:744*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 744*FLEN/8, x5, x2, x3) + +inst_398:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x7c00; +valaddr_reg:x4; val_offset:746*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 746*FLEN/8, x5, x2, x3) + +inst_399:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xfc00; +valaddr_reg:x4; val_offset:748*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 748*FLEN/8, x5, x2, x3) + +inst_400:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x7e00; +valaddr_reg:x4; val_offset:750*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 750*FLEN/8, x5, x2, x3) + +inst_401:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xfe00; +valaddr_reg:x4; val_offset:752*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 752*FLEN/8, x5, x2, x3) + +inst_402:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x7e01; +valaddr_reg:x4; val_offset:754*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 754*FLEN/8, x5, x2, x3) + +inst_403:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xfe55; +valaddr_reg:x4; val_offset:756*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 756*FLEN/8, x5, x2, x3) + +inst_404:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x7c01; +valaddr_reg:x4; val_offset:758*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 758*FLEN/8, x5, x2, x3) + +inst_405:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xfd55; +valaddr_reg:x4; val_offset:760*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 760*FLEN/8, x5, x2, x3) + +inst_406:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x3c00; +valaddr_reg:x4; val_offset:762*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 762*FLEN/8, x5, x2, x3) + +inst_407:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xbc00; +valaddr_reg:x4; val_offset:764*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 764*FLEN/8, x5, x2, x3) + +inst_408:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x0; +valaddr_reg:x4; val_offset:766*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 766*FLEN/8, x5, x2, x3) + +inst_409:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x8000; +valaddr_reg:x4; val_offset:768*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 768*FLEN/8, x5, x2, x3) + +inst_410:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x1; +valaddr_reg:x4; val_offset:770*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 770*FLEN/8, x5, x2, x3) + +inst_411:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x8001; +valaddr_reg:x4; val_offset:772*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 772*FLEN/8, x5, x2, x3) + +inst_412:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x2; +valaddr_reg:x4; val_offset:774*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 774*FLEN/8, x5, x2, x3) + +inst_413:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x83fe; +valaddr_reg:x4; val_offset:776*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 776*FLEN/8, x5, x2, x3) +RVTEST_SIGBASE(x2,signature_x2_3) + +inst_414:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x3ff; +valaddr_reg:x4; val_offset:778*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 778*FLEN/8, x5, x2, x3) + +inst_415:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x83ff; +valaddr_reg:x4; val_offset:780*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 780*FLEN/8, x5, x2, x3) + +inst_416:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x400; +valaddr_reg:x4; val_offset:782*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 782*FLEN/8, x5, x2, x3) + +inst_417:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x8400; +valaddr_reg:x4; val_offset:784*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 784*FLEN/8, x5, x2, x3) + +inst_418:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x401; +valaddr_reg:x4; val_offset:786*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 786*FLEN/8, x5, x2, x3) + +inst_419:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x8455; +valaddr_reg:x4; val_offset:788*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 788*FLEN/8, x5, x2, x3) + +inst_420:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x7bff; +valaddr_reg:x4; val_offset:790*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 790*FLEN/8, x5, x2, x3) + +inst_421:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xfbff; +valaddr_reg:x4; val_offset:792*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 792*FLEN/8, x5, x2, x3) + +inst_422:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x7c00; +valaddr_reg:x4; val_offset:794*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 794*FLEN/8, x5, x2, x3) + +inst_423:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xfc00; +valaddr_reg:x4; val_offset:796*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 796*FLEN/8, x5, x2, x3) + +inst_424:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x7e00; +valaddr_reg:x4; val_offset:798*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 798*FLEN/8, x5, x2, x3) + +inst_425:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xfe00; +valaddr_reg:x4; val_offset:800*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 800*FLEN/8, x5, x2, x3) + +inst_426:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x7e01; +valaddr_reg:x4; val_offset:802*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 802*FLEN/8, x5, x2, x3) + +inst_427:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xfe55; +valaddr_reg:x4; val_offset:804*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 804*FLEN/8, x5, x2, x3) + +inst_428:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x7c01; +valaddr_reg:x4; val_offset:806*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 806*FLEN/8, x5, x2, x3) + +inst_429:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xfd55; +valaddr_reg:x4; val_offset:808*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 808*FLEN/8, x5, x2, x3) + +inst_430:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x3c00; +valaddr_reg:x4; val_offset:810*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 810*FLEN/8, x5, x2, x3) + +inst_431:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xbc00; +valaddr_reg:x4; val_offset:812*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 812*FLEN/8, x5, x2, x3) + +inst_432:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x0; +valaddr_reg:x4; val_offset:814*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 814*FLEN/8, x5, x2, x3) + +inst_433:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x8000; +valaddr_reg:x4; val_offset:816*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 816*FLEN/8, x5, x2, x3) + +inst_434:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x1; +valaddr_reg:x4; val_offset:818*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 818*FLEN/8, x5, x2, x3) + +inst_435:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x8001; +valaddr_reg:x4; val_offset:820*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 820*FLEN/8, x5, x2, x3) + +inst_436:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x2; +valaddr_reg:x4; val_offset:822*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 822*FLEN/8, x5, x2, x3) + +inst_437:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x83fe; +valaddr_reg:x4; val_offset:824*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 824*FLEN/8, x5, x2, x3) + +inst_438:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x3ff; +valaddr_reg:x4; val_offset:826*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 826*FLEN/8, x5, x2, x3) + +inst_439:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x83ff; +valaddr_reg:x4; val_offset:828*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 828*FLEN/8, x5, x2, x3) + +inst_440:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x400; +valaddr_reg:x4; val_offset:830*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 830*FLEN/8, x5, x2, x3) + +inst_441:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x8400; +valaddr_reg:x4; val_offset:832*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 832*FLEN/8, x5, x2, x3) + +inst_442:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x401; +valaddr_reg:x4; val_offset:834*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 834*FLEN/8, x5, x2, x3) + +inst_443:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x8455; +valaddr_reg:x4; val_offset:836*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 836*FLEN/8, x5, x2, x3) + +inst_444:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x7bff; +valaddr_reg:x4; val_offset:838*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 838*FLEN/8, x5, x2, x3) + +inst_445:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xfbff; +valaddr_reg:x4; val_offset:840*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 840*FLEN/8, x5, x2, x3) + +inst_446:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x7c00; +valaddr_reg:x4; val_offset:842*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 842*FLEN/8, x5, x2, x3) + +inst_447:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xfc00; +valaddr_reg:x4; val_offset:844*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 844*FLEN/8, x5, x2, x3) + +inst_448:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x7e00; +valaddr_reg:x4; val_offset:846*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 846*FLEN/8, x5, x2, x3) + +inst_449:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xfe00; +valaddr_reg:x4; val_offset:848*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 848*FLEN/8, x5, x2, x3) + +inst_450:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x7e01; +valaddr_reg:x4; val_offset:850*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 850*FLEN/8, x5, x2, x3) + +inst_451:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xfe55; +valaddr_reg:x4; val_offset:852*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 852*FLEN/8, x5, x2, x3) + +inst_452:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x7c01; +valaddr_reg:x4; val_offset:854*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 854*FLEN/8, x5, x2, x3) + +inst_453:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xfd55; +valaddr_reg:x4; val_offset:856*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 856*FLEN/8, x5, x2, x3) + +inst_454:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x3c00; +valaddr_reg:x4; val_offset:858*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 858*FLEN/8, x5, x2, x3) + +inst_455:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xbc00; +valaddr_reg:x4; val_offset:860*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 860*FLEN/8, x5, x2, x3) + +inst_456:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x0; +valaddr_reg:x4; val_offset:862*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 862*FLEN/8, x5, x2, x3) + +inst_457:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x8000; +valaddr_reg:x4; val_offset:864*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 864*FLEN/8, x5, x2, x3) + +inst_458:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x1; +valaddr_reg:x4; val_offset:866*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 866*FLEN/8, x5, x2, x3) + +inst_459:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x8001; +valaddr_reg:x4; val_offset:868*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 868*FLEN/8, x5, x2, x3) + +inst_460:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x2; +valaddr_reg:x4; val_offset:870*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 870*FLEN/8, x5, x2, x3) + +inst_461:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x83fe; +valaddr_reg:x4; val_offset:872*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 872*FLEN/8, x5, x2, x3) + +inst_462:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x3ff; +valaddr_reg:x4; val_offset:874*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 874*FLEN/8, x5, x2, x3) + +inst_463:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x83ff; +valaddr_reg:x4; val_offset:876*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 876*FLEN/8, x5, x2, x3) + +inst_464:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x400; +valaddr_reg:x4; val_offset:878*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 878*FLEN/8, x5, x2, x3) + +inst_465:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x8400; +valaddr_reg:x4; val_offset:880*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 880*FLEN/8, x5, x2, x3) + +inst_466:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x401; +valaddr_reg:x4; val_offset:882*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 882*FLEN/8, x5, x2, x3) + +inst_467:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x8455; +valaddr_reg:x4; val_offset:884*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 884*FLEN/8, x5, x2, x3) + +inst_468:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x7bff; +valaddr_reg:x4; val_offset:886*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 886*FLEN/8, x5, x2, x3) + +inst_469:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xfbff; +valaddr_reg:x4; val_offset:888*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 888*FLEN/8, x5, x2, x3) + +inst_470:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x7c00; +valaddr_reg:x4; val_offset:890*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 890*FLEN/8, x5, x2, x3) + +inst_471:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xfc00; +valaddr_reg:x4; val_offset:892*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 892*FLEN/8, x5, x2, x3) + +inst_472:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x7e00; +valaddr_reg:x4; val_offset:894*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 894*FLEN/8, x5, x2, x3) + +inst_473:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xfe00; +valaddr_reg:x4; val_offset:896*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 896*FLEN/8, x5, x2, x3) + +inst_474:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x7e01; +valaddr_reg:x4; val_offset:898*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 898*FLEN/8, x5, x2, x3) + +inst_475:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xfe55; +valaddr_reg:x4; val_offset:900*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 900*FLEN/8, x5, x2, x3) + +inst_476:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x7c01; +valaddr_reg:x4; val_offset:902*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 902*FLEN/8, x5, x2, x3) + +inst_477:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xfd55; +valaddr_reg:x4; val_offset:904*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 904*FLEN/8, x5, x2, x3) + +inst_478:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x3c00; +valaddr_reg:x4; val_offset:906*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 906*FLEN/8, x5, x2, x3) + +inst_479:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xbc00; +valaddr_reg:x4; val_offset:908*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 908*FLEN/8, x5, x2, x3) + +inst_480:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x0; +valaddr_reg:x4; val_offset:910*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 910*FLEN/8, x5, x2, x3) + +inst_481:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x8000; +valaddr_reg:x4; val_offset:912*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 912*FLEN/8, x5, x2, x3) + +inst_482:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x1; +valaddr_reg:x4; val_offset:914*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 914*FLEN/8, x5, x2, x3) + +inst_483:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x8001; +valaddr_reg:x4; val_offset:916*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 916*FLEN/8, x5, x2, x3) + +inst_484:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x2; +valaddr_reg:x4; val_offset:918*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 918*FLEN/8, x5, x2, x3) + +inst_485:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x83fe; +valaddr_reg:x4; val_offset:920*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 920*FLEN/8, x5, x2, x3) + +inst_486:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x3ff; +valaddr_reg:x4; val_offset:922*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 922*FLEN/8, x5, x2, x3) + +inst_487:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x83ff; +valaddr_reg:x4; val_offset:924*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 924*FLEN/8, x5, x2, x3) + +inst_488:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x400; +valaddr_reg:x4; val_offset:926*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 926*FLEN/8, x5, x2, x3) + +inst_489:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x8400; +valaddr_reg:x4; val_offset:928*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 928*FLEN/8, x5, x2, x3) + +inst_490:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x401; +valaddr_reg:x4; val_offset:930*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 930*FLEN/8, x5, x2, x3) + +inst_491:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x8455; +valaddr_reg:x4; val_offset:932*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 932*FLEN/8, x5, x2, x3) + +inst_492:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x7bff; +valaddr_reg:x4; val_offset:934*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 934*FLEN/8, x5, x2, x3) + +inst_493:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xfbff; +valaddr_reg:x4; val_offset:936*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 936*FLEN/8, x5, x2, x3) + +inst_494:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x7c00; +valaddr_reg:x4; val_offset:938*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 938*FLEN/8, x5, x2, x3) + +inst_495:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xfc00; +valaddr_reg:x4; val_offset:940*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 940*FLEN/8, x5, x2, x3) + +inst_496:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x7e00; +valaddr_reg:x4; val_offset:942*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 942*FLEN/8, x5, x2, x3) + +inst_497:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xfe00; +valaddr_reg:x4; val_offset:944*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 944*FLEN/8, x5, x2, x3) + +inst_498:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x7e01; +valaddr_reg:x4; val_offset:946*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 946*FLEN/8, x5, x2, x3) + +inst_499:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xfe55; +valaddr_reg:x4; val_offset:948*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 948*FLEN/8, x5, x2, x3) + +inst_500:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x7c01; +valaddr_reg:x4; val_offset:950*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 950*FLEN/8, x5, x2, x3) + +inst_501:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xfd55; +valaddr_reg:x4; val_offset:952*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 952*FLEN/8, x5, x2, x3) + +inst_502:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x3c00; +valaddr_reg:x4; val_offset:954*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 954*FLEN/8, x5, x2, x3) + +inst_503:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xbc00; +valaddr_reg:x4; val_offset:956*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 956*FLEN/8, x5, x2, x3) + +inst_504:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x0; +valaddr_reg:x4; val_offset:958*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 958*FLEN/8, x5, x2, x3) + +inst_505:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x8000; +valaddr_reg:x4; val_offset:960*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 960*FLEN/8, x5, x2, x3) + +inst_506:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x1; +valaddr_reg:x4; val_offset:962*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 962*FLEN/8, x5, x2, x3) + +inst_507:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x8001; +valaddr_reg:x4; val_offset:964*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 964*FLEN/8, x5, x2, x3) + +inst_508:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x2; +valaddr_reg:x4; val_offset:966*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 966*FLEN/8, x5, x2, x3) + +inst_509:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x83fe; +valaddr_reg:x4; val_offset:968*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 968*FLEN/8, x5, x2, x3) + +inst_510:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x3ff; +valaddr_reg:x4; val_offset:970*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 970*FLEN/8, x5, x2, x3) + +inst_511:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x83ff; +valaddr_reg:x4; val_offset:972*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 972*FLEN/8, x5, x2, x3) + +inst_512:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x400; +valaddr_reg:x4; val_offset:974*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 974*FLEN/8, x5, x2, x3) + +inst_513:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x8400; +valaddr_reg:x4; val_offset:976*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 976*FLEN/8, x5, x2, x3) + +inst_514:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x401; +valaddr_reg:x4; val_offset:978*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 978*FLEN/8, x5, x2, x3) + +inst_515:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x8455; +valaddr_reg:x4; val_offset:980*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 980*FLEN/8, x5, x2, x3) + +inst_516:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x7bff; +valaddr_reg:x4; val_offset:982*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 982*FLEN/8, x5, x2, x3) + +inst_517:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xfbff; +valaddr_reg:x4; val_offset:984*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 984*FLEN/8, x5, x2, x3) + +inst_518:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x7c00; +valaddr_reg:x4; val_offset:986*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 986*FLEN/8, x5, x2, x3) + +inst_519:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xfc00; +valaddr_reg:x4; val_offset:988*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 988*FLEN/8, x5, x2, x3) + +inst_520:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x7e00; +valaddr_reg:x4; val_offset:990*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 990*FLEN/8, x5, x2, x3) + +inst_521:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xfe00; +valaddr_reg:x4; val_offset:992*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 992*FLEN/8, x5, x2, x3) + +inst_522:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x7e01; +valaddr_reg:x4; val_offset:994*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 994*FLEN/8, x5, x2, x3) + +inst_523:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xfe55; +valaddr_reg:x4; val_offset:996*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 996*FLEN/8, x5, x2, x3) + +inst_524:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x7c01; +valaddr_reg:x4; val_offset:998*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 998*FLEN/8, x5, x2, x3) + +inst_525:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xfd55; +valaddr_reg:x4; val_offset:1000*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 1000*FLEN/8, x5, x2, x3) + +inst_526:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x3c00; +valaddr_reg:x4; val_offset:1002*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 1002*FLEN/8, x5, x2, x3) + +inst_527:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xbc00; +valaddr_reg:x4; val_offset:1004*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 1004*FLEN/8, x5, x2, x3) + +inst_528:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x0; +valaddr_reg:x4; val_offset:1006*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 1006*FLEN/8, x5, x2, x3) + +inst_529:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x8000; +valaddr_reg:x4; val_offset:1008*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 1008*FLEN/8, x5, x2, x3) + +inst_530:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x1; +valaddr_reg:x4; val_offset:1010*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 1010*FLEN/8, x5, x2, x3) + +inst_531:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x8001; +valaddr_reg:x4; val_offset:1012*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 1012*FLEN/8, x5, x2, x3) + +inst_532:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2; +valaddr_reg:x4; val_offset:1014*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 1014*FLEN/8, x5, x2, x3) + +inst_533:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x83fe; +valaddr_reg:x4; val_offset:1016*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 1016*FLEN/8, x5, x2, x3) + +inst_534:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3ff; +valaddr_reg:x4; val_offset:1018*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 1018*FLEN/8, x5, x2, x3) + +inst_535:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x83ff; +valaddr_reg:x4; val_offset:1020*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 1020*FLEN/8, x5, x2, x3) + +inst_536:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x400; +valaddr_reg:x4; val_offset:1022*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 1022*FLEN/8, x5, x2, x3) + +inst_537:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x8400; +valaddr_reg:x4; val_offset:1024*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 1024*FLEN/8, x5, x2, x3) + +inst_538:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x401; +valaddr_reg:x4; val_offset:1026*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 1026*FLEN/8, x5, x2, x3) + +inst_539:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x8455; +valaddr_reg:x4; val_offset:1028*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 1028*FLEN/8, x5, x2, x3) + +inst_540:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7bff; +valaddr_reg:x4; val_offset:1030*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 1030*FLEN/8, x5, x2, x3) + +inst_541:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xfbff; +valaddr_reg:x4; val_offset:1032*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 1032*FLEN/8, x5, x2, x3) +RVTEST_SIGBASE(x2,signature_x2_4) + +inst_542:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7c00; +valaddr_reg:x4; val_offset:1034*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 1034*FLEN/8, x5, x2, x3) + +inst_543:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xfc00; +valaddr_reg:x4; val_offset:1036*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 1036*FLEN/8, x5, x2, x3) + +inst_544:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7e00; +valaddr_reg:x4; val_offset:1038*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 1038*FLEN/8, x5, x2, x3) + +inst_545:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xfe00; +valaddr_reg:x4; val_offset:1040*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 1040*FLEN/8, x5, x2, x3) + +inst_546:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7e01; +valaddr_reg:x4; val_offset:1042*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 1042*FLEN/8, x5, x2, x3) + +inst_547:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xfe55; +valaddr_reg:x4; val_offset:1044*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 1044*FLEN/8, x5, x2, x3) + +inst_548:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7c01; +valaddr_reg:x4; val_offset:1046*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 1046*FLEN/8, x5, x2, x3) + +inst_549:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xfd55; +valaddr_reg:x4; val_offset:1048*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 1048*FLEN/8, x5, x2, x3) + +inst_550:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3c00; +valaddr_reg:x4; val_offset:1050*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 1050*FLEN/8, x5, x2, x3) + +inst_551:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xbc00; +valaddr_reg:x4; val_offset:1052*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 1052*FLEN/8, x5, x2, x3) + +inst_552:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x0; +valaddr_reg:x4; val_offset:1054*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 1054*FLEN/8, x5, x2, x3) + +inst_553:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x8000; +valaddr_reg:x4; val_offset:1056*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 1056*FLEN/8, x5, x2, x3) + +inst_554:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x1; +valaddr_reg:x4; val_offset:1058*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 1058*FLEN/8, x5, x2, x3) + +inst_555:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x8001; +valaddr_reg:x4; val_offset:1060*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 1060*FLEN/8, x5, x2, x3) + +inst_556:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x2; +valaddr_reg:x4; val_offset:1062*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 1062*FLEN/8, x5, x2, x3) + +inst_557:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x83fe; +valaddr_reg:x4; val_offset:1064*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 1064*FLEN/8, x5, x2, x3) + +inst_558:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x3ff; +valaddr_reg:x4; val_offset:1066*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 1066*FLEN/8, x5, x2, x3) + +inst_559:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x83ff; +valaddr_reg:x4; val_offset:1068*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 1068*FLEN/8, x5, x2, x3) + +inst_560:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x400; +valaddr_reg:x4; val_offset:1070*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 1070*FLEN/8, x5, x2, x3) + +inst_561:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x8400; +valaddr_reg:x4; val_offset:1072*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 1072*FLEN/8, x5, x2, x3) + +inst_562:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x401; +valaddr_reg:x4; val_offset:1074*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 1074*FLEN/8, x5, x2, x3) + +inst_563:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x8455; +valaddr_reg:x4; val_offset:1076*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 1076*FLEN/8, x5, x2, x3) + +inst_564:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x7bff; +valaddr_reg:x4; val_offset:1078*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 1078*FLEN/8, x5, x2, x3) + +inst_565:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xfbff; +valaddr_reg:x4; val_offset:1080*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 1080*FLEN/8, x5, x2, x3) + +inst_566:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x7c00; +valaddr_reg:x4; val_offset:1082*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 1082*FLEN/8, x5, x2, x3) + +inst_567:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xfc00; +valaddr_reg:x4; val_offset:1084*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 1084*FLEN/8, x5, x2, x3) + +inst_568:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x7e00; +valaddr_reg:x4; val_offset:1086*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 1086*FLEN/8, x5, x2, x3) + +inst_569:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xfe00; +valaddr_reg:x4; val_offset:1088*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 1088*FLEN/8, x5, x2, x3) + +inst_570:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x7e01; +valaddr_reg:x4; val_offset:1090*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 1090*FLEN/8, x5, x2, x3) + +inst_571:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xfe55; +valaddr_reg:x4; val_offset:1092*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 1092*FLEN/8, x5, x2, x3) + +inst_572:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x7c01; +valaddr_reg:x4; val_offset:1094*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 1094*FLEN/8, x5, x2, x3) + +inst_573:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xfd55; +valaddr_reg:x4; val_offset:1096*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 1096*FLEN/8, x5, x2, x3) + +inst_574:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x3c00; +valaddr_reg:x4; val_offset:1098*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 1098*FLEN/8, x5, x2, x3) + +inst_575:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbc00; +valaddr_reg:x4; val_offset:1100*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 1100*FLEN/8, x5, x2, x3) + +inst_576:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x0; +valaddr_reg:x4; val_offset:1102*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 1102*FLEN/8, x5, x2, x3) + +inst_577:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x2; +valaddr_reg:x4; val_offset:1104*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 1104*FLEN/8, x5, x2, x3) + +inst_578:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x7c00; +valaddr_reg:x4; val_offset:1106*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 1106*FLEN/8, x5, x2, x3) + +inst_579:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8001; +valaddr_reg:x4; val_offset:1108*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x4, 1108*FLEN/8, x5, x2, x3) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(1,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(2,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(1023,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(1024,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(1025,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(33877,16,FLEN) +test_dataset_1: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31744,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32256,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32257,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31745,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(15360,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(0,32,FLEN) +test_dataset_2: +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(1024,16,FLEN) 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+NAN_BOXED(32769,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32769,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x8_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x8_1: + .fill 30*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x15_0: + .fill 30*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_0: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_1: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_2: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_3: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_4: + .fill 76*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/flt_b19-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/flt_b19-01.S new file mode 100644 index 000000000..0383eb7ec --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/flt_b19-01.S @@ -0,0 +1,8752 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 05:48:16 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_flt.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the flt.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the flt_b19 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",flt_b19) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x7,test_dataset_0) +RVTEST_SIGBASE(x2,signature_x2_1) + +inst_0:// rs1 == rs2, rs1==x4, rs2==x4, rd==x1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3a5 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x4; op2:x4; dest:x1; op1val:0x7ba5; op2val:0x7ba5; +valaddr_reg:x7; val_offset:0*FLEN/8; correctval:??; testreg:x10; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x1, x4, x4, 0, 0, x7, 0*FLEN/8, x12, x2, x10) + +inst_1:// rs1 != rs2, rs1==x25, rs2==x8, rd==x0,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ae and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x25; op2:x8; dest:x0; op1val:0x7ba5; op2val:0x7aae; +valaddr_reg:x7; val_offset:2*FLEN/8; correctval:??; testreg:x10; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x0, x25, x8, 0, 0, x7, 2*FLEN/8, x12, x2, x10) + +inst_2:// rs1==x20, rs2==x9, rd==x4,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3a5 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x20; op2:x9; dest:x4; op1val:0x7aae; op2val:0x7ba5; +valaddr_reg:x7; val_offset:4*FLEN/8; correctval:??; testreg:x10; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x4, x20, x9, 0, 0, x7, 4*FLEN/8, x12, x2, x10) + +inst_3:// rs1==x6, rs2==x19, rd==x9,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0d8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x6; op2:x19; dest:x9; op1val:0x7ba5; op2val:0x78d8; +valaddr_reg:x7; val_offset:6*FLEN/8; correctval:??; testreg:x10; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x9, x6, x19, 0, 0, x7, 6*FLEN/8, x12, x2, x10) + +inst_4:// rs1==x31, rs2==x0, rd==x17,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3a5 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x31; op2:x0; dest:x17; op1val:0x78d8; op2val:0x0; +valaddr_reg:x7; val_offset:8*FLEN/8; correctval:??; testreg:x10; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x17, x31, x0, 0, 0, x7, 8*FLEN/8, x12, x2, x10) + +inst_5:// rs1==x3, rs2==x14, rd==x11,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2e3 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x3; op2:x14; dest:x11; op1val:0x7ba5; op2val:0x76e3; +valaddr_reg:x7; val_offset:10*FLEN/8; correctval:??; testreg:x10; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x11, x3, x14, 0, 0, x7, 10*FLEN/8, x12, x2, x10) + +inst_6:// rs1==x24, rs2==x17, rd==x18,fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3a5 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x24; op2:x17; dest:x18; op1val:0x76e3; op2val:0x7ba5; +valaddr_reg:x7; val_offset:12*FLEN/8; correctval:??; testreg:x10; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x18, x24, x17, 0, 0, x7, 12*FLEN/8, x12, x2, x10) + +inst_7:// rs1==x17, rs2==x5, rd==x13,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x397 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x17; op2:x5; dest:x13; op1val:0x7ba5; op2val:0x7b97; +valaddr_reg:x7; val_offset:14*FLEN/8; correctval:??; testreg:x10; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x13, x17, x5, 0, 0, x7, 14*FLEN/8, x12, x2, x10) + +inst_8:// rs1==x16, rs2==x31, rd==x3,fs1 == 0 and fe1 == 0x1e and fm1 == 0x397 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3a5 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x16; op2:x31; dest:x3; op1val:0x7b97; op2val:0x7ba5; +valaddr_reg:x7; val_offset:16*FLEN/8; correctval:??; testreg:x10; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x3, x16, x31, 0, 0, x7, 16*FLEN/8, x12, x2, x10) + +inst_9:// rs1==x21, rs2==x22, rd==x30,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x21; op2:x22; dest:x30; op1val:0x7ba5; op2val:0xeaad; +valaddr_reg:x7; val_offset:18*FLEN/8; correctval:??; testreg:x10; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x30, x21, x22, 0, 0, x7, 18*FLEN/8, x12, x2, x10) + +inst_10:// rs1==x26, rs2==x21, rd==x8,fs1 == 0 and fe1 == 0x1b and fm1 == 0x21d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x26; op2:x21; dest:x8; op1val:0x6e1d; op2val:0xf82c; +valaddr_reg:x7; val_offset:20*FLEN/8; correctval:??; testreg:x10; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x8, x26, x21, 0, 0, x7, 20*FLEN/8, x12, x2, x10) + +inst_11:// rs1==x18, rs2==x11, rd==x23,fs1 == 1 and fe1 == 0x1e and fm1 == 0x02c and fs2 == 0 and fe2 == 0x1b and fm2 == 0x21d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x18; op2:x11; dest:x23; op1val:0xf82c; op2val:0x6e1d; +valaddr_reg:x7; val_offset:22*FLEN/8; correctval:??; testreg:x10; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x23, x18, x11, 0, 0, x7, 22*FLEN/8, x12, x2, x10) +RVTEST_VALBASEUPD(x9,test_dataset_1) + +inst_12:// rs1==x28, rs2==x7, rd==x24,fs1 == 0 and fe1 == 0x1b and fm1 == 0x21d and fs2 == 1 and fe2 == 0x1a and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x28; op2:x7; dest:x24; op1val:0x6e1d; op2val:0xeaad; +valaddr_reg:x9; val_offset:0*FLEN/8; correctval:??; testreg:x10; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x24, x28, x7, 0, 0, x9, 0*FLEN/8, x11, x2, x10) + +inst_13:// rs1==x7, rs2==x10, rd==x26,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x21d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x7; op2:x10; dest:x26; op1val:0x7ba5; op2val:0x6e1d; +valaddr_reg:x9; val_offset:2*FLEN/8; correctval:??; testreg:x6; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x26, x7, x10, 0, 0, x9, 2*FLEN/8, x11, x2, x6) +RVTEST_SIGBASE(x4,signature_x4_0) + +inst_14:// rs1==x10, rs2==x15, rd==x2,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x10; op2:x15; dest:x2; op1val:0x7ba5; op2val:0xf438; +valaddr_reg:x9; val_offset:4*FLEN/8; correctval:??; testreg:x6; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x2, x10, x15, 0, 0, x9, 4*FLEN/8, x11, x4, x6) + +inst_15:// rs1==x22, rs2==x28, rd==x21,fs1 == 1 and fe1 == 0x1d and fm1 == 0x038 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3a5 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x22; op2:x28; dest:x21; op1val:0xf438; op2val:0x7ba5; +valaddr_reg:x9; val_offset:6*FLEN/8; correctval:??; testreg:x6; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x21, x22, x28, 0, 0, x9, 6*FLEN/8, x11, x4, x6) + +inst_16:// rs1==x30, rs2==x3, rd==x5,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x249 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x3; dest:x5; op1val:0x7ba5; op2val:0xf649; +valaddr_reg:x9; val_offset:8*FLEN/8; correctval:??; testreg:x6; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x5, x30, x3, 0, 0, x9, 8*FLEN/8, x11, x4, x6) + +inst_17:// rs1==x2, rs2==x12, rd==x15,fs1 == 1 and fe1 == 0x1d and fm1 == 0x249 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3a5 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x2; op2:x12; dest:x15; op1val:0xf649; op2val:0x7ba5; +valaddr_reg:x9; val_offset:10*FLEN/8; correctval:??; testreg:x6; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x15, x2, x12, 0, 0, x9, 10*FLEN/8, x11, x4, x6) + +inst_18:// rs1==x27, rs2==x24, rd==x16,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0d9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x27; op2:x24; dest:x16; op1val:0x7ba5; op2val:0xf8d9; +valaddr_reg:x9; val_offset:12*FLEN/8; correctval:??; testreg:x6; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x16, x27, x24, 0, 0, x9, 12*FLEN/8, x11, x4, x6) + +inst_19:// rs1==x13, rs2==x1, rd==x25,fs1 == 1 and fe1 == 0x1e and fm1 == 0x0d9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3a5 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x13; op2:x1; dest:x25; op1val:0xf8d9; op2val:0x7ba5; +valaddr_reg:x9; val_offset:14*FLEN/8; correctval:??; testreg:x6; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x25, x13, x1, 0, 0, x9, 14*FLEN/8, x11, x4, x6) + +inst_20:// rs1==x8, rs2==x27, rd==x29,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x34a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x8; op2:x27; dest:x29; op1val:0x7ba5; op2val:0xf74a; +valaddr_reg:x9; val_offset:16*FLEN/8; correctval:??; testreg:x6; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x29, x8, x27, 0, 0, x9, 16*FLEN/8, x11, x4, x6) + +inst_21:// rs1==x5, rs2==x26, rd==x20,fs1 == 1 and fe1 == 0x1d and fm1 == 0x34a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3a5 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x5; op2:x26; dest:x20; op1val:0xf74a; op2val:0x7ba5; +valaddr_reg:x9; val_offset:18*FLEN/8; correctval:??; testreg:x6; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x20, x5, x26, 0, 0, x9, 18*FLEN/8, x11, x4, x6) + +inst_22:// rs1==x29, rs2==x20, rd==x28,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x29; op2:x20; dest:x28; op1val:0x7ba5; op2val:0x3a; +valaddr_reg:x9; val_offset:20*FLEN/8; correctval:??; testreg:x6; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x28, x29, x20, 0, 0, x9, 20*FLEN/8, x11, x4, x6) + +inst_23:// rs1==x23, rs2==x18, rd==x31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x069 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x047 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x23; op2:x18; dest:x31; op1val:0x69; op2val:0x7847; +valaddr_reg:x9; val_offset:22*FLEN/8; correctval:??; testreg:x6; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x23, x18, 0, 0, x9, 22*FLEN/8, x11, x4, x6) +RVTEST_VALBASEUPD(x5,test_dataset_2) + +inst_24:// rs1==x1, rs2==x13, rd==x7,fs1 == 0 and fe1 == 0x1e and fm1 == 0x047 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x069 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x1; op2:x13; dest:x7; op1val:0x7847; op2val:0x69; +valaddr_reg:x5; val_offset:0*FLEN/8; correctval:??; testreg:x6; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x7, x1, x13, 0, 0, x5, 0*FLEN/8, x8, x4, x6) + +inst_25:// rs1==x19, rs2==x30, rd==x14,fs1 == 0 and fe1 == 0x00 and fm1 == 0x069 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x19; op2:x30; dest:x14; op1val:0x69; op2val:0x3a; +valaddr_reg:x5; val_offset:2*FLEN/8; correctval:??; testreg:x6; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x14, x19, x30, 0, 0, x5, 2*FLEN/8, x8, x4, x6) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_26:// rs1==x15, rs2==x2, rd==x10,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x069 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x15; op2:x2; dest:x10; op1val:0x7ba5; op2val:0x69; +valaddr_reg:x5; val_offset:4*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x10, x15, x2, 0, 0, x5, 4*FLEN/8, x8, x1, x3) + +inst_27:// rs1==x14, rs2==x25, rd==x19,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x14; op2:x25; dest:x19; op1val:0x7ba5; op2val:0x2ad; +valaddr_reg:x5; val_offset:6*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x19, x14, x25, 0, 0, x5, 6*FLEN/8, x8, x1, x3) + +inst_28:// rs1==x0, rs2==x29, rd==x22,fs1 == 0 and fe1 == 0x01 and fm1 == 0x01a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0fc and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x0; op2:x29; dest:x22; op1val:0x0; op2val:0x78fc; +valaddr_reg:x5; val_offset:8*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x22, x0, x29, 0, 0, x5, 8*FLEN/8, x8, x1, x3) + +inst_29:// rs1==x11, rs2==x16, rd==x27,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fc and fs2 == 0 and fe2 == 0x01 and fm2 == 0x01a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x11; op2:x16; dest:x27; op1val:0x78fc; op2val:0x41a; +valaddr_reg:x5; val_offset:10*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x27, x11, x16, 0, 0, x5, 10*FLEN/8, x8, x1, x3) + +inst_30:// rs1==x9, rs2==x23, rd==x12,fs1 == 0 and fe1 == 0x01 and fm1 == 0x01a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x9; op2:x23; dest:x12; op1val:0x41a; op2val:0x2ad; +valaddr_reg:x5; val_offset:12*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x12, x9, x23, 0, 0, x5, 12*FLEN/8, x8, x1, x3) + +inst_31:// rs1==x12,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x01a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x12; op2:x18; dest:x2; op1val:0x7ba5; op2val:0x41a; +valaddr_reg:x5; val_offset:14*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x2, x12, x18, 0, 0, x5, 14*FLEN/8, x8, x1, x3) + +inst_32:// rs2==x6,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x252 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x6; dest:x9; op1val:0x7ba5; op2val:0x252; +valaddr_reg:x5; val_offset:16*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x9, x30, x6, 0, 0, x5, 16*FLEN/8, x8, x1, x3) + +inst_33:// rd==x6,fs1 == 0 and fe1 == 0x01 and fm1 == 0x01a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x054 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x4; op2:x12; dest:x6; op1val:0x41a; op2val:0x7854; +valaddr_reg:x5; val_offset:18*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x6, x4, x12, 0, 0, x5, 18*FLEN/8, x8, x1, x3) + +inst_34:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x054 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x01a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7854; op2val:0x41a; +valaddr_reg:x5; val_offset:20*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 20*FLEN/8, x8, x1, x3) + +inst_35:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x01a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x252 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x41a; op2val:0x252; +valaddr_reg:x5; val_offset:22*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 22*FLEN/8, x8, x1, x3) + +inst_36:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e3 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba5; op2val:0x2e3; +valaddr_reg:x5; val_offset:24*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 24*FLEN/8, x8, x1, x3) + +inst_37:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x01a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x162 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x41a; op2val:0x7962; +valaddr_reg:x5; val_offset:26*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 26*FLEN/8, x8, x1, x3) + +inst_38:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x162 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x01a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7962; op2val:0x41a; +valaddr_reg:x5; val_offset:28*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 28*FLEN/8, x8, x1, x3) + +inst_39:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x01a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e3 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x41a; op2val:0x2e3; +valaddr_reg:x5; val_offset:30*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 30*FLEN/8, x8, x1, x3) + +inst_40:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba5; op2val:0x1c7; +valaddr_reg:x5; val_offset:32*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 32*FLEN/8, x8, x1, x3) + +inst_41:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x01a and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2a1 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x41a; op2val:0x76a1; +valaddr_reg:x5; val_offset:34*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 34*FLEN/8, x8, x1, x3) + +inst_42:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a1 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x01a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x76a1; op2val:0x41a; +valaddr_reg:x5; val_offset:36*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 36*FLEN/8, x8, x1, x3) + +inst_43:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x01a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x41a; op2val:0x1c7; +valaddr_reg:x5; val_offset:38*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 38*FLEN/8, x8, x1, x3) + +inst_44:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba5; op2val:0x83a8; +valaddr_reg:x5; val_offset:40*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 40*FLEN/8, x8, x1, x3) + +inst_45:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x01a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2cf and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x41a; op2val:0xfacf; +valaddr_reg:x5; val_offset:42*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 42*FLEN/8, x8, x1, x3) + +inst_46:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x2cf and fs2 == 0 and fe2 == 0x01 and fm2 == 0x01a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfacf; op2val:0x41a; +valaddr_reg:x5; val_offset:44*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 44*FLEN/8, x8, x1, x3) + +inst_47:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x01a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x41a; op2val:0x83a8; +valaddr_reg:x5; val_offset:46*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 46*FLEN/8, x8, x1, x3) + +inst_48:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c4 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba5; op2val:0x82c4; +valaddr_reg:x5; val_offset:48*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 48*FLEN/8, x8, x1, x3) + +inst_49:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x01a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x126 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x41a; op2val:0xf926; +valaddr_reg:x5; val_offset:50*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 50*FLEN/8, x8, x1, x3) + +inst_50:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x126 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x01a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf926; op2val:0x41a; +valaddr_reg:x5; val_offset:52*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 52*FLEN/8, x8, x1, x3) + +inst_51:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x01a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c4 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x41a; op2val:0x82c4; +valaddr_reg:x5; val_offset:54*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 54*FLEN/8, x8, x1, x3) + +inst_52:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba5; op2val:0x835d; +valaddr_reg:x5; val_offset:56*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 56*FLEN/8, x8, x1, x3) + +inst_53:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x01a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x243 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x41a; op2val:0xfa43; +valaddr_reg:x5; val_offset:58*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 58*FLEN/8, x8, x1, x3) + +inst_54:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x243 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x01a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa43; op2val:0x41a; +valaddr_reg:x5; val_offset:60*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 60*FLEN/8, x8, x1, x3) + +inst_55:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x01a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x41a; op2val:0x835d; +valaddr_reg:x5; val_offset:62*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 62*FLEN/8, x8, x1, x3) + +inst_56:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x006 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba5; op2val:0x8006; +valaddr_reg:x5; val_offset:64*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 64*FLEN/8, x8, x1, x3) + +inst_57:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x095 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xa; op2val:0xf895; +valaddr_reg:x5; val_offset:66*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 66*FLEN/8, x8, x1, x3) + +inst_58:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x095 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf895; op2val:0xa; +valaddr_reg:x5; val_offset:68*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 68*FLEN/8, x8, x1, x3) + +inst_59:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x006 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xa; op2val:0x8006; +valaddr_reg:x5; val_offset:70*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 70*FLEN/8, x8, x1, x3) + +inst_60:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba5; op2val:0xa; +valaddr_reg:x5; val_offset:72*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 72*FLEN/8, x8, x1, x3) + +inst_61:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ec and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba5; op2val:0x82ec; +valaddr_reg:x5; val_offset:74*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 74*FLEN/8, x8, x1, x3) + +inst_62:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x01a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x172 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x41a; op2val:0xf972; +valaddr_reg:x5; val_offset:76*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 76*FLEN/8, x8, x1, x3) + +inst_63:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x172 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x01a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf972; op2val:0x41a; +valaddr_reg:x5; val_offset:78*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 78*FLEN/8, x8, x1, x3) + +inst_64:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x01a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ec and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x41a; op2val:0x82ec; +valaddr_reg:x5; val_offset:80*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 80*FLEN/8, x8, x1, x3) + +inst_65:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba5; op2val:0xf0; +valaddr_reg:x5; val_offset:82*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 82*FLEN/8, x8, x1, x3) + +inst_66:// fs1 == 0 and fe1 == 0x11 and fm1 == 0x243 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x4643; op2val:0xf0; +valaddr_reg:x5; val_offset:84*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 84*FLEN/8, x8, x1, x3) + +inst_67:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x243 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x4643; +valaddr_reg:x5; val_offset:86*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 86*FLEN/8, x8, x1, x3) + +inst_68:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x243 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba5; op2val:0x4643; +valaddr_reg:x5; val_offset:88*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 88*FLEN/8, x8, x1, x3) + +inst_69:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ae and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aae; op2val:0x7aae; +valaddr_reg:x5; val_offset:90*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 90*FLEN/8, x8, x1, x3) + +inst_70:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0d8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aae; op2val:0x78d8; +valaddr_reg:x5; val_offset:92*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 92*FLEN/8, x8, x1, x3) + +inst_71:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ae and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x78d8; op2val:0x7aae; +valaddr_reg:x5; val_offset:94*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 94*FLEN/8, x8, x1, x3) + +inst_72:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2e3 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aae; op2val:0x76e3; +valaddr_reg:x5; val_offset:96*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 96*FLEN/8, x8, x1, x3) + +inst_73:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ae and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x76e3; op2val:0x7aae; +valaddr_reg:x5; val_offset:98*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 98*FLEN/8, x8, x1, x3) + +inst_74:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x1e and fm2 == 0x397 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aae; op2val:0x7b97; +valaddr_reg:x5; val_offset:100*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 100*FLEN/8, x8, x1, x3) + +inst_75:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x397 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ae and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b97; op2val:0x7aae; +valaddr_reg:x5; val_offset:102*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 102*FLEN/8, x8, x1, x3) + +inst_76:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 1 and fe2 == 0x1a and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aae; op2val:0xeaad; +valaddr_reg:x5; val_offset:104*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 104*FLEN/8, x8, x1, x3) + +inst_77:// fs1 == 0 and fe1 == 0x1b and fm1 == 0x158 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d58; op2val:0xf82c; +valaddr_reg:x5; val_offset:106*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 106*FLEN/8, x8, x1, x3) + +inst_78:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02c and fs2 == 0 and fe2 == 0x1b and fm2 == 0x158 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82c; op2val:0x6d58; +valaddr_reg:x5; val_offset:108*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 108*FLEN/8, x8, x1, x3) + +inst_79:// fs1 == 0 and fe1 == 0x1b and fm1 == 0x158 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d58; op2val:0xeaad; +valaddr_reg:x5; val_offset:110*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 110*FLEN/8, x8, x1, x3) + +inst_80:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x1b and fm2 == 0x158 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aae; op2val:0x6d58; +valaddr_reg:x5; val_offset:112*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 112*FLEN/8, x8, x1, x3) + +inst_81:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 1 and fe2 == 0x1d and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aae; op2val:0xf438; +valaddr_reg:x5; val_offset:114*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 114*FLEN/8, x8, x1, x3) + +inst_82:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x038 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ae and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf438; op2val:0x7aae; +valaddr_reg:x5; val_offset:116*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 116*FLEN/8, x8, x1, x3) + +inst_83:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 1 and fe2 == 0x1d and fm2 == 0x249 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aae; op2val:0xf649; +valaddr_reg:x5; val_offset:118*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 118*FLEN/8, x8, x1, x3) + +inst_84:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x249 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ae and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf649; op2val:0x7aae; +valaddr_reg:x5; val_offset:120*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 120*FLEN/8, x8, x1, x3) + +inst_85:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0d9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aae; op2val:0xf8d9; +valaddr_reg:x5; val_offset:122*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 122*FLEN/8, x8, x1, x3) + +inst_86:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x0d9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ae and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf8d9; op2val:0x7aae; +valaddr_reg:x5; val_offset:124*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 124*FLEN/8, x8, x1, x3) + +inst_87:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 1 and fe2 == 0x1d and fm2 == 0x34a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aae; op2val:0xf74a; +valaddr_reg:x5; val_offset:126*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 126*FLEN/8, x8, x1, x3) + +inst_88:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x34a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ae and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf74a; op2val:0x7aae; +valaddr_reg:x5; val_offset:128*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 128*FLEN/8, x8, x1, x3) + +inst_89:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aae; op2val:0x3a; +valaddr_reg:x5; val_offset:130*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 130*FLEN/8, x8, x1, x3) + +inst_90:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x05b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x047 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x5b; op2val:0x7847; +valaddr_reg:x5; val_offset:132*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 132*FLEN/8, x8, x1, x3) + +inst_91:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x047 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x05b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7847; op2val:0x5b; +valaddr_reg:x5; val_offset:134*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 134*FLEN/8, x8, x1, x3) + +inst_92:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x05b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x5b; op2val:0x3a; +valaddr_reg:x5; val_offset:136*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 136*FLEN/8, x8, x1, x3) + +inst_93:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x00 and fm2 == 0x05b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aae; op2val:0x5b; +valaddr_reg:x5; val_offset:138*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 138*FLEN/8, x8, x1, x3) + +inst_94:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aae; op2val:0x2ad; +valaddr_reg:x5; val_offset:140*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 140*FLEN/8, x8, x1, x3) + +inst_95:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x396 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0fc and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x396; op2val:0x78fc; +valaddr_reg:x5; val_offset:142*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 142*FLEN/8, x8, x1, x3) + +inst_96:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x396 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x78fc; op2val:0x396; +valaddr_reg:x5; val_offset:144*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 144*FLEN/8, x8, x1, x3) + +inst_97:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x396 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x396; op2val:0x2ad; +valaddr_reg:x5; val_offset:146*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 146*FLEN/8, x8, x1, x3) + +inst_98:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x00 and fm2 == 0x396 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aae; op2val:0x396; +valaddr_reg:x5; val_offset:148*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 148*FLEN/8, x8, x1, x3) + +inst_99:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x00 and fm2 == 0x252 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aae; op2val:0x252; +valaddr_reg:x5; val_offset:150*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 150*FLEN/8, x8, x1, x3) + +inst_100:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x396 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x054 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x396; op2val:0x7854; +valaddr_reg:x5; val_offset:152*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 152*FLEN/8, x8, x1, x3) + +inst_101:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x054 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x396 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7854; op2val:0x396; +valaddr_reg:x5; val_offset:154*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 154*FLEN/8, x8, x1, x3) + +inst_102:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x396 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x252 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x396; op2val:0x252; +valaddr_reg:x5; val_offset:156*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 156*FLEN/8, x8, x1, x3) + +inst_103:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e3 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aae; op2val:0x2e3; +valaddr_reg:x5; val_offset:158*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 158*FLEN/8, x8, x1, x3) + +inst_104:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x396 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x162 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x396; op2val:0x7962; +valaddr_reg:x5; val_offset:160*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 160*FLEN/8, x8, x1, x3) + +inst_105:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x162 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x396 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7962; op2val:0x396; +valaddr_reg:x5; val_offset:162*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 162*FLEN/8, x8, x1, x3) + +inst_106:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x396 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e3 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x396; op2val:0x2e3; +valaddr_reg:x5; val_offset:164*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 164*FLEN/8, x8, x1, x3) + +inst_107:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aae; op2val:0x1c7; +valaddr_reg:x5; val_offset:166*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 166*FLEN/8, x8, x1, x3) + +inst_108:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x396 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2a1 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x396; op2val:0x76a1; +valaddr_reg:x5; val_offset:168*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 168*FLEN/8, x8, x1, x3) + +inst_109:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x396 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x76a1; op2val:0x396; +valaddr_reg:x5; val_offset:170*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 170*FLEN/8, x8, x1, x3) + +inst_110:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x396 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x396; op2val:0x1c7; +valaddr_reg:x5; val_offset:172*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 172*FLEN/8, x8, x1, x3) + +inst_111:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aae; op2val:0x83a8; +valaddr_reg:x5; val_offset:174*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 174*FLEN/8, x8, x1, x3) + +inst_112:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x396 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2cf and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x396; op2val:0xfacf; +valaddr_reg:x5; val_offset:176*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 176*FLEN/8, x8, x1, x3) + +inst_113:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x2cf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x396 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfacf; op2val:0x396; +valaddr_reg:x5; val_offset:178*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 178*FLEN/8, x8, x1, x3) + +inst_114:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x396 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x396; op2val:0x83a8; +valaddr_reg:x5; val_offset:180*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 180*FLEN/8, x8, x1, x3) + +inst_115:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c4 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aae; op2val:0x82c4; +valaddr_reg:x5; val_offset:182*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 182*FLEN/8, x8, x1, x3) + +inst_116:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x396 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x126 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x396; op2val:0xf926; +valaddr_reg:x5; val_offset:184*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 184*FLEN/8, x8, x1, x3) + +inst_117:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x126 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x396 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf926; op2val:0x396; +valaddr_reg:x5; val_offset:186*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 186*FLEN/8, x8, x1, x3) + +inst_118:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x396 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c4 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x396; op2val:0x82c4; +valaddr_reg:x5; val_offset:188*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 188*FLEN/8, x8, x1, x3) + +inst_119:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aae; op2val:0x835d; +valaddr_reg:x5; val_offset:190*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 190*FLEN/8, x8, x1, x3) + +inst_120:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x396 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x243 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x396; op2val:0xfa43; +valaddr_reg:x5; val_offset:192*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 192*FLEN/8, x8, x1, x3) + +inst_121:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x243 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x396 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa43; op2val:0x396; +valaddr_reg:x5; val_offset:194*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 194*FLEN/8, x8, x1, x3) + +inst_122:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x396 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x396; op2val:0x835d; +valaddr_reg:x5; val_offset:196*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 196*FLEN/8, x8, x1, x3) + +inst_123:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 1 and fe2 == 0x00 and fm2 == 0x006 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aae; op2val:0x8006; +valaddr_reg:x5; val_offset:198*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 198*FLEN/8, x8, x1, x3) + +inst_124:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x009 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x095 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x9; op2val:0xf895; +valaddr_reg:x5; val_offset:200*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 200*FLEN/8, x8, x1, x3) + +inst_125:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x095 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x009 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf895; op2val:0x9; +valaddr_reg:x5; val_offset:202*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 202*FLEN/8, x8, x1, x3) + +inst_126:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x009 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x006 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x9; op2val:0x8006; +valaddr_reg:x5; val_offset:204*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 204*FLEN/8, x8, x1, x3) + +inst_127:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x00 and fm2 == 0x009 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aae; op2val:0x9; +valaddr_reg:x5; val_offset:206*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 206*FLEN/8, x8, x1, x3) + +inst_128:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ec and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aae; op2val:0x82ec; +valaddr_reg:x5; val_offset:208*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 208*FLEN/8, x8, x1, x3) + +inst_129:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x396 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x172 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x396; op2val:0xf972; +valaddr_reg:x5; val_offset:210*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 210*FLEN/8, x8, x1, x3) + +inst_130:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x172 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x396 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf972; op2val:0x396; +valaddr_reg:x5; val_offset:212*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 212*FLEN/8, x8, x1, x3) + +inst_131:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x396 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ec and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x396; op2val:0x82ec; +valaddr_reg:x5; val_offset:214*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 214*FLEN/8, x8, x1, x3) + +inst_132:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aae; op2val:0xf0; +valaddr_reg:x5; val_offset:216*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 216*FLEN/8, x8, x1, x3) + +inst_133:// fs1 == 0 and fe1 == 0x11 and fm1 == 0x179 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x4579; op2val:0xf0; +valaddr_reg:x5; val_offset:218*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 218*FLEN/8, x8, x1, x3) + +inst_134:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x179 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x4579; +valaddr_reg:x5; val_offset:220*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 220*FLEN/8, x8, x1, x3) + +inst_135:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x11 and fm2 == 0x179 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aae; op2val:0x4579; +valaddr_reg:x5; val_offset:222*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 222*FLEN/8, x8, x1, x3) + +inst_136:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0d8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x78d8; op2val:0x78d8; +valaddr_reg:x5; val_offset:224*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 224*FLEN/8, x8, x1, x3) + +inst_137:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d8 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2e3 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x78d8; op2val:0x76e3; +valaddr_reg:x5; val_offset:226*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 226*FLEN/8, x8, x1, x3) + +inst_138:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0d8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x76e3; op2val:0x78d8; +valaddr_reg:x5; val_offset:228*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 228*FLEN/8, x8, x1, x3) + +inst_139:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x397 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x78d8; op2val:0x7b97; +valaddr_reg:x5; val_offset:230*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 230*FLEN/8, x8, x1, x3) + +inst_140:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x397 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0d8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b97; op2val:0x78d8; +valaddr_reg:x5; val_offset:232*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 232*FLEN/8, x8, x1, x3) + +inst_141:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d8 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x78d8; op2val:0xeaad; +valaddr_reg:x5; val_offset:234*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 234*FLEN/8, x8, x1, x3) + +inst_142:// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x6bc0; op2val:0xf82c; +valaddr_reg:x5; val_offset:236*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 236*FLEN/8, x8, x1, x3) + +inst_143:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02c and fs2 == 0 and fe2 == 0x1a and fm2 == 0x3c0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82c; op2val:0x6bc0; +valaddr_reg:x5; val_offset:238*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 238*FLEN/8, x8, x1, x3) + +inst_144:// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x6bc0; op2val:0xeaad; +valaddr_reg:x5; val_offset:240*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 240*FLEN/8, x8, x1, x3) + +inst_145:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d8 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x3c0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x78d8; op2val:0x6bc0; +valaddr_reg:x5; val_offset:242*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 242*FLEN/8, x8, x1, x3) + +inst_146:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d8 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x78d8; op2val:0xf438; +valaddr_reg:x5; val_offset:244*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 244*FLEN/8, x8, x1, x3) + +inst_147:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x038 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0d8 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf438; op2val:0x78d8; +valaddr_reg:x5; val_offset:246*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 246*FLEN/8, x8, x1, x3) + +inst_148:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d8 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x249 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x78d8; op2val:0xf649; +valaddr_reg:x5; val_offset:248*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 248*FLEN/8, x8, x1, x3) + +inst_149:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x249 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0d8 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf649; op2val:0x78d8; +valaddr_reg:x5; val_offset:250*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 250*FLEN/8, x8, x1, x3) + +inst_150:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d8 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0d9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x78d8; op2val:0xf8d9; +valaddr_reg:x5; val_offset:252*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 252*FLEN/8, x8, x1, x3) + +inst_151:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x0d9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0d8 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf8d9; op2val:0x78d8; +valaddr_reg:x5; val_offset:254*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 254*FLEN/8, x8, x1, x3) + +inst_152:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d8 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x34a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x78d8; op2val:0xf74a; +valaddr_reg:x5; val_offset:256*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 256*FLEN/8, x8, x1, x3) + +inst_153:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x34a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0d8 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf74a; op2val:0x78d8; +valaddr_reg:x5; val_offset:258*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 258*FLEN/8, x8, x1, x3) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_154:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x78d8; op2val:0x3a; +valaddr_reg:x5; val_offset:260*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 260*FLEN/8, x8, x1, x3) + +inst_155:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x042 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x047 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x42; op2val:0x7847; +valaddr_reg:x5; val_offset:262*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 262*FLEN/8, x8, x1, x3) + +inst_156:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x047 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x042 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7847; op2val:0x42; +valaddr_reg:x5; val_offset:264*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 264*FLEN/8, x8, x1, x3) + +inst_157:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x042 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x42; op2val:0x3a; +valaddr_reg:x5; val_offset:266*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 266*FLEN/8, x8, x1, x3) + +inst_158:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x042 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x78d8; op2val:0x42; +valaddr_reg:x5; val_offset:268*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 268*FLEN/8, x8, x1, x3) + +inst_159:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x78d8; op2val:0x2ad; +valaddr_reg:x5; val_offset:270*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 270*FLEN/8, x8, x1, x3) + +inst_160:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x299 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0fc and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x299; op2val:0x78fc; +valaddr_reg:x5; val_offset:272*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 272*FLEN/8, x8, x1, x3) + +inst_161:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x299 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x78fc; op2val:0x299; +valaddr_reg:x5; val_offset:274*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 274*FLEN/8, x8, x1, x3) + +inst_162:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x299 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x299; op2val:0x2ad; +valaddr_reg:x5; val_offset:276*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 276*FLEN/8, x8, x1, x3) + +inst_163:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x299 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x78d8; op2val:0x299; +valaddr_reg:x5; val_offset:278*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 278*FLEN/8, x8, x1, x3) + +inst_164:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x252 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x78d8; op2val:0x252; +valaddr_reg:x5; val_offset:280*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 280*FLEN/8, x8, x1, x3) + +inst_165:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x299 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x054 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x299; op2val:0x7854; +valaddr_reg:x5; val_offset:282*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 282*FLEN/8, x8, x1, x3) + +inst_166:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x054 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x299 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7854; op2val:0x299; +valaddr_reg:x5; val_offset:284*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 284*FLEN/8, x8, x1, x3) + +inst_167:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x299 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x252 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x299; op2val:0x252; +valaddr_reg:x5; val_offset:286*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 286*FLEN/8, x8, x1, x3) + +inst_168:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e3 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x78d8; op2val:0x2e3; +valaddr_reg:x5; val_offset:288*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 288*FLEN/8, x8, x1, x3) + +inst_169:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x299 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x162 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x299; op2val:0x7962; +valaddr_reg:x5; val_offset:290*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 290*FLEN/8, x8, x1, x3) + +inst_170:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x162 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x299 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7962; op2val:0x299; +valaddr_reg:x5; val_offset:292*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 292*FLEN/8, x8, x1, x3) + +inst_171:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x299 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e3 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x299; op2val:0x2e3; +valaddr_reg:x5; val_offset:294*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 294*FLEN/8, x8, x1, x3) + +inst_172:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x78d8; op2val:0x1c7; +valaddr_reg:x5; val_offset:296*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 296*FLEN/8, x8, x1, x3) + +inst_173:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x299 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2a1 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x299; op2val:0x76a1; +valaddr_reg:x5; val_offset:298*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 298*FLEN/8, x8, x1, x3) + +inst_174:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x299 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x76a1; op2val:0x299; +valaddr_reg:x5; val_offset:300*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 300*FLEN/8, x8, x1, x3) + +inst_175:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x299 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x299; op2val:0x1c7; +valaddr_reg:x5; val_offset:302*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 302*FLEN/8, x8, x1, x3) + +inst_176:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x78d8; op2val:0x83a8; +valaddr_reg:x5; val_offset:304*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 304*FLEN/8, x8, x1, x3) + +inst_177:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x299 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2cf and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x299; op2val:0xfacf; +valaddr_reg:x5; val_offset:306*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 306*FLEN/8, x8, x1, x3) + +inst_178:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x2cf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x299 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfacf; op2val:0x299; +valaddr_reg:x5; val_offset:308*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 308*FLEN/8, x8, x1, x3) + +inst_179:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x299 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x299; op2val:0x83a8; +valaddr_reg:x5; val_offset:310*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 310*FLEN/8, x8, x1, x3) + +inst_180:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c4 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x78d8; op2val:0x82c4; +valaddr_reg:x5; val_offset:312*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 312*FLEN/8, x8, x1, x3) + +inst_181:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x299 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x126 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x299; op2val:0xf926; +valaddr_reg:x5; val_offset:314*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 314*FLEN/8, x8, x1, x3) + +inst_182:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x126 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x299 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf926; op2val:0x299; +valaddr_reg:x5; val_offset:316*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 316*FLEN/8, x8, x1, x3) + +inst_183:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x299 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c4 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x299; op2val:0x82c4; +valaddr_reg:x5; val_offset:318*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 318*FLEN/8, x8, x1, x3) + +inst_184:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x78d8; op2val:0x835d; +valaddr_reg:x5; val_offset:320*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 320*FLEN/8, x8, x1, x3) + +inst_185:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x299 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x243 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x299; op2val:0xfa43; +valaddr_reg:x5; val_offset:322*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 322*FLEN/8, x8, x1, x3) + +inst_186:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x243 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x299 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa43; op2val:0x299; +valaddr_reg:x5; val_offset:324*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 324*FLEN/8, x8, x1, x3) + +inst_187:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x299 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x299; op2val:0x835d; +valaddr_reg:x5; val_offset:326*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 326*FLEN/8, x8, x1, x3) + +inst_188:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x006 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x78d8; op2val:0x8006; +valaddr_reg:x5; val_offset:328*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 328*FLEN/8, x8, x1, x3) + +inst_189:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x006 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x095 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x6; op2val:0xf895; +valaddr_reg:x5; val_offset:330*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 330*FLEN/8, x8, x1, x3) + +inst_190:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x095 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x006 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf895; op2val:0x6; +valaddr_reg:x5; val_offset:332*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 332*FLEN/8, x8, x1, x3) + +inst_191:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x006 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x006 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x6; op2val:0x8006; +valaddr_reg:x5; val_offset:334*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 334*FLEN/8, x8, x1, x3) + +inst_192:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x006 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x78d8; op2val:0x6; +valaddr_reg:x5; val_offset:336*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 336*FLEN/8, x8, x1, x3) + +inst_193:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ec and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x78d8; op2val:0x82ec; +valaddr_reg:x5; val_offset:338*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 338*FLEN/8, x8, x1, x3) + +inst_194:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x299 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x172 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x299; op2val:0xf972; +valaddr_reg:x5; val_offset:340*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 340*FLEN/8, x8, x1, x3) + +inst_195:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x172 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x299 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf972; op2val:0x299; +valaddr_reg:x5; val_offset:342*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 342*FLEN/8, x8, x1, x3) + +inst_196:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x299 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ec and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x299; op2val:0x82ec; +valaddr_reg:x5; val_offset:344*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 344*FLEN/8, x8, x1, x3) + +inst_197:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x78d8; op2val:0xf0; +valaddr_reg:x5; val_offset:346*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 346*FLEN/8, x8, x1, x3) + +inst_198:// fs1 == 0 and fe1 == 0x10 and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x43f0; op2val:0xf0; +valaddr_reg:x5; val_offset:348*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 348*FLEN/8, x8, x1, x3) + +inst_199:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x43f0; +valaddr_reg:x5; val_offset:350*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 350*FLEN/8, x8, x1, x3) + +inst_200:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d8 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x78d8; op2val:0x43f0; +valaddr_reg:x5; val_offset:352*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 352*FLEN/8, x8, x1, x3) + +inst_201:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2e3 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x76e3; op2val:0x76e3; +valaddr_reg:x5; val_offset:354*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 354*FLEN/8, x8, x1, x3) + +inst_202:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x397 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x76e3; op2val:0x7b97; +valaddr_reg:x5; val_offset:356*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 356*FLEN/8, x8, x1, x3) + +inst_203:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x397 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2e3 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b97; op2val:0x76e3; +valaddr_reg:x5; val_offset:358*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 358*FLEN/8, x8, x1, x3) + +inst_204:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e3 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x76e3; op2val:0xeaad; +valaddr_reg:x5; val_offset:360*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 360*FLEN/8, x8, x1, x3) + +inst_205:// fs1 == 0 and fe1 == 0x1a and fm1 == 0x182 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x6982; op2val:0xf82c; +valaddr_reg:x5; val_offset:362*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 362*FLEN/8, x8, x1, x3) + +inst_206:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02c and fs2 == 0 and fe2 == 0x1a and fm2 == 0x182 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82c; op2val:0x6982; +valaddr_reg:x5; val_offset:364*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 364*FLEN/8, x8, x1, x3) + +inst_207:// fs1 == 0 and fe1 == 0x1a and fm1 == 0x182 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x6982; op2val:0xeaad; +valaddr_reg:x5; val_offset:366*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 366*FLEN/8, x8, x1, x3) + +inst_208:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x182 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x76e3; op2val:0x6982; +valaddr_reg:x5; val_offset:368*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 368*FLEN/8, x8, x1, x3) + +inst_209:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e3 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x76e3; op2val:0xf438; +valaddr_reg:x5; val_offset:370*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 370*FLEN/8, x8, x1, x3) + +inst_210:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x038 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2e3 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf438; op2val:0x76e3; +valaddr_reg:x5; val_offset:372*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 372*FLEN/8, x8, x1, x3) + +inst_211:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e3 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x249 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x76e3; op2val:0xf649; +valaddr_reg:x5; val_offset:374*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 374*FLEN/8, x8, x1, x3) + +inst_212:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x249 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2e3 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf649; op2val:0x76e3; +valaddr_reg:x5; val_offset:376*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 376*FLEN/8, x8, x1, x3) + +inst_213:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0d9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x76e3; op2val:0xf8d9; +valaddr_reg:x5; val_offset:378*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 378*FLEN/8, x8, x1, x3) + +inst_214:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x0d9 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2e3 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf8d9; op2val:0x76e3; +valaddr_reg:x5; val_offset:380*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 380*FLEN/8, x8, x1, x3) + +inst_215:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e3 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x34a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x76e3; op2val:0xf74a; +valaddr_reg:x5; val_offset:382*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 382*FLEN/8, x8, x1, x3) + +inst_216:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x34a and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2e3 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf74a; op2val:0x76e3; +valaddr_reg:x5; val_offset:384*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 384*FLEN/8, x8, x1, x3) + +inst_217:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x76e3; op2val:0x3a; +valaddr_reg:x5; val_offset:386*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 386*FLEN/8, x8, x1, x3) + +inst_218:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x02f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x047 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2f; op2val:0x7847; +valaddr_reg:x5; val_offset:388*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 388*FLEN/8, x8, x1, x3) + +inst_219:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x047 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x02f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7847; op2val:0x2f; +valaddr_reg:x5; val_offset:390*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 390*FLEN/8, x8, x1, x3) + +inst_220:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x02f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2f; op2val:0x3a; +valaddr_reg:x5; val_offset:392*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 392*FLEN/8, x8, x1, x3) + +inst_221:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x02f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x76e3; op2val:0x2f; +valaddr_reg:x5; val_offset:394*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 394*FLEN/8, x8, x1, x3) + +inst_222:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x76e3; op2val:0x2ad; +valaddr_reg:x5; val_offset:396*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 396*FLEN/8, x8, x1, x3) + +inst_223:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1d9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0fc and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x1d9; op2val:0x78fc; +valaddr_reg:x5; val_offset:398*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 398*FLEN/8, x8, x1, x3) + +inst_224:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1d9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x78fc; op2val:0x1d9; +valaddr_reg:x5; val_offset:400*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 400*FLEN/8, x8, x1, x3) + +inst_225:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1d9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x1d9; op2val:0x2ad; +valaddr_reg:x5; val_offset:402*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 402*FLEN/8, x8, x1, x3) + +inst_226:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1d9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x76e3; op2val:0x1d9; +valaddr_reg:x5; val_offset:404*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 404*FLEN/8, x8, x1, x3) + +inst_227:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x252 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x76e3; op2val:0x252; +valaddr_reg:x5; val_offset:406*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 406*FLEN/8, x8, x1, x3) + +inst_228:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1d9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x054 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x1d9; op2val:0x7854; +valaddr_reg:x5; val_offset:408*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 408*FLEN/8, x8, x1, x3) + +inst_229:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x054 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1d9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7854; op2val:0x1d9; +valaddr_reg:x5; val_offset:410*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 410*FLEN/8, x8, x1, x3) + +inst_230:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1d9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x252 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x1d9; op2val:0x252; +valaddr_reg:x5; val_offset:412*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 412*FLEN/8, x8, x1, x3) + +inst_231:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e3 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x76e3; op2val:0x2e3; +valaddr_reg:x5; val_offset:414*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 414*FLEN/8, x8, x1, x3) + +inst_232:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1d9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x162 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x1d9; op2val:0x7962; +valaddr_reg:x5; val_offset:416*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 416*FLEN/8, x8, x1, x3) + +inst_233:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x162 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1d9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7962; op2val:0x1d9; +valaddr_reg:x5; val_offset:418*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 418*FLEN/8, x8, x1, x3) + +inst_234:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1d9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e3 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x1d9; op2val:0x2e3; +valaddr_reg:x5; val_offset:420*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 420*FLEN/8, x8, x1, x3) + +inst_235:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x76e3; op2val:0x1c7; +valaddr_reg:x5; val_offset:422*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 422*FLEN/8, x8, x1, x3) + +inst_236:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1d9 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2a1 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x1d9; op2val:0x76a1; +valaddr_reg:x5; val_offset:424*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 424*FLEN/8, x8, x1, x3) + +inst_237:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1d9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x76a1; op2val:0x1d9; +valaddr_reg:x5; val_offset:426*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 426*FLEN/8, x8, x1, x3) + +inst_238:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1d9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x1d9; op2val:0x1c7; +valaddr_reg:x5; val_offset:428*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 428*FLEN/8, x8, x1, x3) + +inst_239:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x76e3; op2val:0x83a8; +valaddr_reg:x5; val_offset:430*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 430*FLEN/8, x8, x1, x3) + +inst_240:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1d9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2cf and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x1d9; op2val:0xfacf; +valaddr_reg:x5; val_offset:432*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 432*FLEN/8, x8, x1, x3) + +inst_241:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x2cf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1d9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfacf; op2val:0x1d9; +valaddr_reg:x5; val_offset:434*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 434*FLEN/8, x8, x1, x3) + +inst_242:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1d9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x1d9; op2val:0x83a8; +valaddr_reg:x5; val_offset:436*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 436*FLEN/8, x8, x1, x3) + +inst_243:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c4 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x76e3; op2val:0x82c4; +valaddr_reg:x5; val_offset:438*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 438*FLEN/8, x8, x1, x3) + +inst_244:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1d9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x126 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x1d9; op2val:0xf926; +valaddr_reg:x5; val_offset:440*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 440*FLEN/8, x8, x1, x3) + +inst_245:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x126 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1d9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf926; op2val:0x1d9; +valaddr_reg:x5; val_offset:442*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 442*FLEN/8, x8, x1, x3) + +inst_246:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1d9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c4 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x1d9; op2val:0x82c4; +valaddr_reg:x5; val_offset:444*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 444*FLEN/8, x8, x1, x3) + +inst_247:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x76e3; op2val:0x835d; +valaddr_reg:x5; val_offset:446*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 446*FLEN/8, x8, x1, x3) + +inst_248:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1d9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x243 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x1d9; op2val:0xfa43; +valaddr_reg:x5; val_offset:448*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 448*FLEN/8, x8, x1, x3) + +inst_249:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x243 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1d9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa43; op2val:0x1d9; +valaddr_reg:x5; val_offset:450*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 450*FLEN/8, x8, x1, x3) + +inst_250:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1d9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x1d9; op2val:0x835d; +valaddr_reg:x5; val_offset:452*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 452*FLEN/8, x8, x1, x3) + +inst_251:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x006 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x76e3; op2val:0x8006; +valaddr_reg:x5; val_offset:454*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 454*FLEN/8, x8, x1, x3) + +inst_252:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x004 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x095 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x4; op2val:0xf895; +valaddr_reg:x5; val_offset:456*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 456*FLEN/8, x8, x1, x3) + +inst_253:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x095 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x004 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf895; op2val:0x4; +valaddr_reg:x5; val_offset:458*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 458*FLEN/8, x8, x1, x3) + +inst_254:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x004 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x006 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x4; op2val:0x8006; +valaddr_reg:x5; val_offset:460*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 460*FLEN/8, x8, x1, x3) + +inst_255:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x004 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x76e3; op2val:0x4; +valaddr_reg:x5; val_offset:462*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 462*FLEN/8, x8, x1, x3) + +inst_256:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ec and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x76e3; op2val:0x82ec; +valaddr_reg:x5; val_offset:464*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 464*FLEN/8, x8, x1, x3) + +inst_257:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1d9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x172 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x1d9; op2val:0xf972; +valaddr_reg:x5; val_offset:466*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 466*FLEN/8, x8, x1, x3) + +inst_258:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x172 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1d9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf972; op2val:0x1d9; +valaddr_reg:x5; val_offset:468*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 468*FLEN/8, x8, x1, x3) + +inst_259:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1d9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ec and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x1d9; op2val:0x82ec; +valaddr_reg:x5; val_offset:470*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 470*FLEN/8, x8, x1, x3) + +inst_260:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x76e3; op2val:0xf0; +valaddr_reg:x5; val_offset:472*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 472*FLEN/8, x8, x1, x3) + +inst_261:// fs1 == 0 and fe1 == 0x10 and fm1 == 0x1a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x41a4; op2val:0xf0; +valaddr_reg:x5; val_offset:474*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 474*FLEN/8, x8, x1, x3) + +inst_262:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1a4 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x41a4; +valaddr_reg:x5; val_offset:476*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 476*FLEN/8, x8, x1, x3) + +inst_263:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1a4 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x76e3; op2val:0x41a4; +valaddr_reg:x5; val_offset:478*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 478*FLEN/8, x8, x1, x3) + +inst_264:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x397 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x397 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b97; op2val:0x7b97; +valaddr_reg:x5; val_offset:480*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 480*FLEN/8, x8, x1, x3) + +inst_265:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x397 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b97; op2val:0xeaad; +valaddr_reg:x5; val_offset:482*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 482*FLEN/8, x8, x1, x3) + +inst_266:// fs1 == 0 and fe1 == 0x1b and fm1 == 0x212 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e12; op2val:0xf82c; +valaddr_reg:x5; val_offset:484*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 484*FLEN/8, x8, x1, x3) + +inst_267:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02c and fs2 == 0 and fe2 == 0x1b and fm2 == 0x212 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82c; op2val:0x6e12; +valaddr_reg:x5; val_offset:486*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 486*FLEN/8, x8, x1, x3) + +inst_268:// fs1 == 0 and fe1 == 0x1b and fm1 == 0x212 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e12; op2val:0xeaad; +valaddr_reg:x5; val_offset:488*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 488*FLEN/8, x8, x1, x3) + +inst_269:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x397 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x212 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b97; op2val:0x6e12; +valaddr_reg:x5; val_offset:490*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 490*FLEN/8, x8, x1, x3) + +inst_270:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x397 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b97; op2val:0xf438; +valaddr_reg:x5; val_offset:492*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 492*FLEN/8, x8, x1, x3) + +inst_271:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x038 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x397 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf438; op2val:0x7b97; +valaddr_reg:x5; val_offset:494*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 494*FLEN/8, x8, x1, x3) + +inst_272:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x397 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x249 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b97; op2val:0xf649; +valaddr_reg:x5; val_offset:496*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 496*FLEN/8, x8, x1, x3) + +inst_273:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x249 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x397 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf649; op2val:0x7b97; +valaddr_reg:x5; val_offset:498*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 498*FLEN/8, x8, x1, x3) + +inst_274:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x397 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0d9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b97; op2val:0xf8d9; +valaddr_reg:x5; val_offset:500*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 500*FLEN/8, x8, x1, x3) + +inst_275:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x0d9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x397 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf8d9; op2val:0x7b97; +valaddr_reg:x5; val_offset:502*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 502*FLEN/8, x8, x1, x3) + +inst_276:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x397 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x34a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b97; op2val:0xf74a; +valaddr_reg:x5; val_offset:504*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 504*FLEN/8, x8, x1, x3) + +inst_277:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x34a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x397 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf74a; op2val:0x7b97; +valaddr_reg:x5; val_offset:506*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 506*FLEN/8, x8, x1, x3) + +inst_278:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x397 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b97; op2val:0x3a; +valaddr_reg:x5; val_offset:508*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 508*FLEN/8, x8, x1, x3) + +inst_279:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x068 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x047 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x68; op2val:0x7847; +valaddr_reg:x5; val_offset:510*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 510*FLEN/8, x8, x1, x3) + +inst_280:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x047 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x068 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7847; op2val:0x68; +valaddr_reg:x5; val_offset:512*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 512*FLEN/8, x8, x1, x3) + +inst_281:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x068 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x68; op2val:0x3a; +valaddr_reg:x5; val_offset:514*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 514*FLEN/8, x8, x1, x3) +RVTEST_SIGBASE(x1,signature_x1_2) + +inst_282:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x397 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x068 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b97; op2val:0x68; +valaddr_reg:x5; val_offset:516*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 516*FLEN/8, x8, x1, x3) + +inst_283:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x397 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b97; op2val:0x2ad; +valaddr_reg:x5; val_offset:518*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 518*FLEN/8, x8, x1, x3) + +inst_284:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x013 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0fc and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x413; op2val:0x78fc; +valaddr_reg:x5; val_offset:520*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 520*FLEN/8, x8, x1, x3) + +inst_285:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fc and fs2 == 0 and fe2 == 0x01 and fm2 == 0x013 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x78fc; op2val:0x413; +valaddr_reg:x5; val_offset:522*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 522*FLEN/8, x8, x1, x3) + +inst_286:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x013 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x413; op2val:0x2ad; +valaddr_reg:x5; val_offset:524*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 524*FLEN/8, x8, x1, x3) + +inst_287:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x397 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x013 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b97; op2val:0x413; +valaddr_reg:x5; val_offset:526*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 526*FLEN/8, x8, x1, x3) + +inst_288:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x397 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x252 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b97; op2val:0x252; +valaddr_reg:x5; val_offset:528*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 528*FLEN/8, x8, x1, x3) + +inst_289:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x013 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x054 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x413; op2val:0x7854; +valaddr_reg:x5; val_offset:530*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 530*FLEN/8, x8, x1, x3) + +inst_290:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x054 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x013 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7854; op2val:0x413; +valaddr_reg:x5; val_offset:532*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 532*FLEN/8, x8, x1, x3) + +inst_291:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x013 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x252 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x413; op2val:0x252; +valaddr_reg:x5; val_offset:534*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 534*FLEN/8, x8, x1, x3) + +inst_292:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x397 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e3 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b97; op2val:0x2e3; +valaddr_reg:x5; val_offset:536*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 536*FLEN/8, x8, x1, x3) + +inst_293:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x013 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x162 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x413; op2val:0x7962; +valaddr_reg:x5; val_offset:538*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 538*FLEN/8, x8, x1, x3) + +inst_294:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x162 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x013 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7962; op2val:0x413; +valaddr_reg:x5; val_offset:540*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 540*FLEN/8, x8, x1, x3) + +inst_295:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x013 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e3 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x413; op2val:0x2e3; +valaddr_reg:x5; val_offset:542*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 542*FLEN/8, x8, x1, x3) + +inst_296:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x397 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b97; op2val:0x1c7; +valaddr_reg:x5; val_offset:544*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 544*FLEN/8, x8, x1, x3) + +inst_297:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x013 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2a1 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x413; op2val:0x76a1; +valaddr_reg:x5; val_offset:546*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 546*FLEN/8, x8, x1, x3) + +inst_298:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a1 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x013 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x76a1; op2val:0x413; +valaddr_reg:x5; val_offset:548*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 548*FLEN/8, x8, x1, x3) + +inst_299:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x013 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x413; op2val:0x1c7; +valaddr_reg:x5; val_offset:550*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 550*FLEN/8, x8, x1, x3) + +inst_300:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x397 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b97; op2val:0x83a8; +valaddr_reg:x5; val_offset:552*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 552*FLEN/8, x8, x1, x3) + +inst_301:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x013 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2cf and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x413; op2val:0xfacf; +valaddr_reg:x5; val_offset:554*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 554*FLEN/8, x8, x1, x3) + +inst_302:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x2cf and fs2 == 0 and fe2 == 0x01 and fm2 == 0x013 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfacf; op2val:0x413; +valaddr_reg:x5; val_offset:556*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 556*FLEN/8, x8, x1, x3) + +inst_303:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x013 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x413; op2val:0x83a8; +valaddr_reg:x5; val_offset:558*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 558*FLEN/8, x8, x1, x3) + +inst_304:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x397 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c4 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b97; op2val:0x82c4; +valaddr_reg:x5; val_offset:560*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 560*FLEN/8, x8, x1, x3) + +inst_305:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x013 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x126 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x413; op2val:0xf926; +valaddr_reg:x5; val_offset:562*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 562*FLEN/8, x8, x1, x3) + +inst_306:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x126 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x013 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf926; op2val:0x413; +valaddr_reg:x5; val_offset:564*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 564*FLEN/8, x8, x1, x3) + +inst_307:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x013 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c4 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x413; op2val:0x82c4; +valaddr_reg:x5; val_offset:566*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 566*FLEN/8, x8, x1, x3) + +inst_308:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x397 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b97; op2val:0x835d; +valaddr_reg:x5; val_offset:568*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 568*FLEN/8, x8, x1, x3) + +inst_309:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x013 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x243 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x413; op2val:0xfa43; +valaddr_reg:x5; val_offset:570*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 570*FLEN/8, x8, x1, x3) + +inst_310:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x243 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x013 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa43; op2val:0x413; +valaddr_reg:x5; val_offset:572*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 572*FLEN/8, x8, x1, x3) + +inst_311:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x013 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x413; op2val:0x835d; +valaddr_reg:x5; val_offset:574*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 574*FLEN/8, x8, x1, x3) + +inst_312:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x397 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x006 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b97; op2val:0x8006; +valaddr_reg:x5; val_offset:576*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 576*FLEN/8, x8, x1, x3) + +inst_313:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x397 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b97; op2val:0xa; +valaddr_reg:x5; val_offset:578*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 578*FLEN/8, x8, x1, x3) + +inst_314:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x397 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ec and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b97; op2val:0x82ec; +valaddr_reg:x5; val_offset:580*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 580*FLEN/8, x8, x1, x3) + +inst_315:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x013 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x172 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x413; op2val:0xf972; +valaddr_reg:x5; val_offset:582*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 582*FLEN/8, x8, x1, x3) + +inst_316:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x172 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x013 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf972; op2val:0x413; +valaddr_reg:x5; val_offset:584*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 584*FLEN/8, x8, x1, x3) + +inst_317:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x013 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ec and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x413; op2val:0x82ec; +valaddr_reg:x5; val_offset:586*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 586*FLEN/8, x8, x1, x3) + +inst_318:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x397 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b97; op2val:0xf0; +valaddr_reg:x5; val_offset:588*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 588*FLEN/8, x8, x1, x3) + +inst_319:// fs1 == 0 and fe1 == 0x11 and fm1 == 0x238 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x4638; op2val:0xf0; +valaddr_reg:x5; val_offset:590*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 590*FLEN/8, x8, x1, x3) + +inst_320:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x238 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x4638; +valaddr_reg:x5; val_offset:592*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 592*FLEN/8, x8, x1, x3) + +inst_321:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x397 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x238 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b97; op2val:0x4638; +valaddr_reg:x5; val_offset:594*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 594*FLEN/8, x8, x1, x3) + +inst_322:// fs1 == 1 and fe1 == 0x1a and fm1 == 0x2ad and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3a5 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xeaad; op2val:0x7ba5; +valaddr_reg:x5; val_offset:596*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 596*FLEN/8, x8, x1, x3) + +inst_323:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3a5 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82c; op2val:0x7ba5; +valaddr_reg:x5; val_offset:598*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 598*FLEN/8, x8, x1, x3) + +inst_324:// fs1 == 1 and fe1 == 0x1a and fm1 == 0x2ad and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xeaad; op2val:0xf82c; +valaddr_reg:x5; val_offset:600*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 600*FLEN/8, x8, x1, x3) + +inst_325:// fs1 == 1 and fe1 == 0x1a and fm1 == 0x2ad and fs2 == 1 and fe2 == 0x1a and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xeaad; op2val:0xeaad; +valaddr_reg:x5; val_offset:602*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 602*FLEN/8, x8, x1, x3) + +inst_326:// fs1 == 1 and fe1 == 0x1a and fm1 == 0x2ad and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ae and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xeaad; op2val:0x7aae; +valaddr_reg:x5; val_offset:604*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 604*FLEN/8, x8, x1, x3) + +inst_327:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ae and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82c; op2val:0x7aae; +valaddr_reg:x5; val_offset:606*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 606*FLEN/8, x8, x1, x3) + +inst_328:// fs1 == 1 and fe1 == 0x1a and fm1 == 0x2ad and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0d8 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xeaad; op2val:0x78d8; +valaddr_reg:x5; val_offset:608*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 608*FLEN/8, x8, x1, x3) + +inst_329:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0d8 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82c; op2val:0x78d8; +valaddr_reg:x5; val_offset:610*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 610*FLEN/8, x8, x1, x3) + +inst_330:// fs1 == 1 and fe1 == 0x1a and fm1 == 0x2ad and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2e3 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xeaad; op2val:0x76e3; +valaddr_reg:x5; val_offset:612*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 612*FLEN/8, x8, x1, x3) + +inst_331:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02c and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2e3 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82c; op2val:0x76e3; +valaddr_reg:x5; val_offset:614*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 614*FLEN/8, x8, x1, x3) + +inst_332:// fs1 == 1 and fe1 == 0x1a and fm1 == 0x2ad and fs2 == 0 and fe2 == 0x1e and fm2 == 0x397 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xeaad; op2val:0x7b97; +valaddr_reg:x5; val_offset:616*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 616*FLEN/8, x8, x1, x3) + +inst_333:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x397 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82c; op2val:0x7b97; +valaddr_reg:x5; val_offset:618*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 618*FLEN/8, x8, x1, x3) + +inst_334:// fs1 == 1 and fe1 == 0x1a and fm1 == 0x2ad and fs2 == 1 and fe2 == 0x1d and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xeaad; op2val:0xf438; +valaddr_reg:x5; val_offset:620*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 620*FLEN/8, x8, x1, x3) + +inst_335:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02c and fs2 == 1 and fe2 == 0x19 and fm2 == 0x2c1 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82c; op2val:0xe6c1; +valaddr_reg:x5; val_offset:622*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 622*FLEN/8, x8, x1, x3) + +inst_336:// fs1 == 1 and fe1 == 0x19 and fm1 == 0x2c1 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xe6c1; op2val:0xf82c; +valaddr_reg:x5; val_offset:624*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 624*FLEN/8, x8, x1, x3) + +inst_337:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02c and fs2 == 1 and fe2 == 0x1d and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82c; op2val:0xf438; +valaddr_reg:x5; val_offset:626*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 626*FLEN/8, x8, x1, x3) + +inst_338:// fs1 == 1 and fe1 == 0x1a and fm1 == 0x2ad and fs2 == 1 and fe2 == 0x1d and fm2 == 0x249 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xeaad; op2val:0xf649; +valaddr_reg:x5; val_offset:628*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 628*FLEN/8, x8, x1, x3) + +inst_339:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02c and fs2 == 1 and fe2 == 0x1a and fm2 == 0x107 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82c; op2val:0xe907; +valaddr_reg:x5; val_offset:630*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 630*FLEN/8, x8, x1, x3) + +inst_340:// fs1 == 1 and fe1 == 0x1a and fm1 == 0x107 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xe907; op2val:0xf82c; +valaddr_reg:x5; val_offset:632*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 632*FLEN/8, x8, x1, x3) + +inst_341:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02c and fs2 == 1 and fe2 == 0x1d and fm2 == 0x249 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82c; op2val:0xf649; +valaddr_reg:x5; val_offset:634*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 634*FLEN/8, x8, x1, x3) + +inst_342:// fs1 == 1 and fe1 == 0x1a and fm1 == 0x2ad and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0d9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xeaad; op2val:0xf8d9; +valaddr_reg:x5; val_offset:636*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 636*FLEN/8, x8, x1, x3) + +inst_343:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02c and fs2 == 1 and fe2 == 0x1a and fm2 == 0x3c2 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82c; op2val:0xebc2; +valaddr_reg:x5; val_offset:638*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 638*FLEN/8, x8, x1, x3) + +inst_344:// fs1 == 1 and fe1 == 0x1a and fm1 == 0x3c2 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xebc2; op2val:0xf82c; +valaddr_reg:x5; val_offset:640*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 640*FLEN/8, x8, x1, x3) + +inst_345:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0d9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82c; op2val:0xf8d9; +valaddr_reg:x5; val_offset:642*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 642*FLEN/8, x8, x1, x3) + +inst_346:// fs1 == 1 and fe1 == 0x1a and fm1 == 0x2ad and fs2 == 1 and fe2 == 0x1d and fm2 == 0x34a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xeaad; op2val:0xf74a; +valaddr_reg:x5; val_offset:644*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 644*FLEN/8, x8, x1, x3) + +inst_347:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02c and fs2 == 1 and fe2 == 0x1a and fm2 == 0x1d4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82c; op2val:0xe9d4; +valaddr_reg:x5; val_offset:646*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 646*FLEN/8, x8, x1, x3) + +inst_348:// fs1 == 1 and fe1 == 0x1a and fm1 == 0x1d4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x02c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xe9d4; op2val:0xf82c; +valaddr_reg:x5; val_offset:648*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 648*FLEN/8, x8, x1, x3) + +inst_349:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x02c and fs2 == 1 and fe2 == 0x1d and fm2 == 0x34a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf82c; op2val:0xf74a; +valaddr_reg:x5; val_offset:650*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 650*FLEN/8, x8, x1, x3) + +inst_350:// fs1 == 1 and fe1 == 0x1a and fm1 == 0x2ad and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xeaad; op2val:0x3a; +valaddr_reg:x5; val_offset:652*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 652*FLEN/8, x8, x1, x3) + +inst_351:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x039 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x2d8 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8039; op2val:0x6ad8; +valaddr_reg:x5; val_offset:654*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 654*FLEN/8, x8, x1, x3) + +inst_352:// fs1 == 0 and fe1 == 0x1a and fm1 == 0x2d8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x039 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ad8; op2val:0x8039; +valaddr_reg:x5; val_offset:656*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 656*FLEN/8, x8, x1, x3) + +inst_353:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x039 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8039; op2val:0x3a; +valaddr_reg:x5; val_offset:658*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 658*FLEN/8, x8, x1, x3) + +inst_354:// fs1 == 1 and fe1 == 0x1a and fm1 == 0x2ad and fs2 == 1 and fe2 == 0x00 and fm2 == 0x039 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xeaad; op2val:0x8039; +valaddr_reg:x5; val_offset:660*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 660*FLEN/8, x8, x1, x3) + +inst_355:// fs1 == 1 and fe1 == 0x1a and fm1 == 0x2ad and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xeaad; op2val:0x2ad; +valaddr_reg:x5; val_offset:662*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 662*FLEN/8, x8, x1, x3) + +inst_356:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x23d and fs2 == 0 and fe2 == 0x1a and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x823d; op2val:0x6bfa; +valaddr_reg:x5; val_offset:664*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 664*FLEN/8, x8, x1, x3) + +inst_357:// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3fa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x23d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x6bfa; op2val:0x823d; +valaddr_reg:x5; val_offset:666*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 666*FLEN/8, x8, x1, x3) + +inst_358:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x23d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x823d; op2val:0x2ad; +valaddr_reg:x5; val_offset:668*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 668*FLEN/8, x8, x1, x3) + +inst_359:// fs1 == 1 and fe1 == 0x1a and fm1 == 0x2ad and fs2 == 1 and fe2 == 0x00 and fm2 == 0x23d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xeaad; op2val:0x823d; +valaddr_reg:x5; val_offset:670*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 670*FLEN/8, x8, x1, x3) + +inst_360:// fs1 == 1 and fe1 == 0x1a and fm1 == 0x2ad and fs2 == 0 and fe2 == 0x00 and fm2 == 0x252 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xeaad; op2val:0x252; +valaddr_reg:x5; val_offset:672*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 672*FLEN/8, x8, x1, x3) + +inst_361:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x23d and fs2 == 0 and fe2 == 0x1a and fm2 == 0x2ed and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x823d; op2val:0x6aed; +valaddr_reg:x5; val_offset:674*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 674*FLEN/8, x8, x1, x3) + +inst_362:// fs1 == 0 and fe1 == 0x1a and fm1 == 0x2ed and fs2 == 1 and fe2 == 0x00 and fm2 == 0x23d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x6aed; op2val:0x823d; +valaddr_reg:x5; val_offset:676*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 676*FLEN/8, x8, x1, x3) + +inst_363:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x23d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x252 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x823d; op2val:0x252; +valaddr_reg:x5; val_offset:678*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 678*FLEN/8, x8, x1, x3) + +inst_364:// fs1 == 1 and fe1 == 0x1a and fm1 == 0x2ad and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e3 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xeaad; op2val:0x2e3; +valaddr_reg:x5; val_offset:680*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 680*FLEN/8, x8, x1, x3) + +inst_365:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x23d and fs2 == 0 and fe2 == 0x1b and fm2 == 0x04e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x823d; op2val:0x6c4e; +valaddr_reg:x5; val_offset:682*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 682*FLEN/8, x8, x1, x3) + +inst_366:// fs1 == 0 and fe1 == 0x1b and fm1 == 0x04e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x23d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c4e; op2val:0x823d; +valaddr_reg:x5; val_offset:684*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 684*FLEN/8, x8, x1, x3) + +inst_367:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x23d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e3 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x823d; op2val:0x2e3; +valaddr_reg:x5; val_offset:686*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 686*FLEN/8, x8, x1, x3) + +inst_368:// fs1 == 1 and fe1 == 0x1a and fm1 == 0x2ad and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xeaad; op2val:0x1c7; +valaddr_reg:x5; val_offset:688*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 688*FLEN/8, x8, x1, x3) + +inst_369:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x23d and fs2 == 0 and fe2 == 0x1a and fm2 == 0x14d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x823d; op2val:0x694d; +valaddr_reg:x5; val_offset:690*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 690*FLEN/8, x8, x1, x3) + +inst_370:// fs1 == 0 and fe1 == 0x1a and fm1 == 0x14d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x23d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x694d; op2val:0x823d; +valaddr_reg:x5; val_offset:692*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 692*FLEN/8, x8, x1, x3) + +inst_371:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x23d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x823d; op2val:0x1c7; +valaddr_reg:x5; val_offset:694*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 694*FLEN/8, x8, x1, x3) + +inst_372:// fs1 == 1 and fe1 == 0x1a and fm1 == 0x2ad and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a8 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xeaad; op2val:0x83a8; +valaddr_reg:x5; val_offset:696*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 696*FLEN/8, x8, x1, x3) + +inst_373:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x23d and fs2 == 1 and fe2 == 0x1b and fm2 == 0x173 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x823d; op2val:0xed73; +valaddr_reg:x5; val_offset:698*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 698*FLEN/8, x8, x1, x3) + +inst_374:// fs1 == 1 and fe1 == 0x1b and fm1 == 0x173 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x23d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xed73; op2val:0x823d; +valaddr_reg:x5; val_offset:700*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 700*FLEN/8, x8, x1, x3) + +inst_375:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x23d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a8 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x823d; op2val:0x83a8; +valaddr_reg:x5; val_offset:702*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 702*FLEN/8, x8, x1, x3) + +inst_376:// fs1 == 1 and fe1 == 0x1a and fm1 == 0x2ad and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xeaad; op2val:0x82c4; +valaddr_reg:x5; val_offset:704*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 704*FLEN/8, x8, x1, x3) + +inst_377:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x23d and fs2 == 1 and fe2 == 0x1b and fm2 == 0x01f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x823d; op2val:0xec1f; +valaddr_reg:x5; val_offset:706*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 706*FLEN/8, x8, x1, x3) + +inst_378:// fs1 == 1 and fe1 == 0x1b and fm1 == 0x01f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x23d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xec1f; op2val:0x823d; +valaddr_reg:x5; val_offset:708*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 708*FLEN/8, x8, x1, x3) + +inst_379:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x23d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x823d; op2val:0x82c4; +valaddr_reg:x5; val_offset:710*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 710*FLEN/8, x8, x1, x3) + +inst_380:// fs1 == 1 and fe1 == 0x1a and fm1 == 0x2ad and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xeaad; op2val:0x835d; +valaddr_reg:x5; val_offset:712*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 712*FLEN/8, x8, x1, x3) + +inst_381:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x23d and fs2 == 1 and fe2 == 0x1b and fm2 == 0x103 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x823d; op2val:0xed03; +valaddr_reg:x5; val_offset:714*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 714*FLEN/8, x8, x1, x3) + +inst_382:// fs1 == 1 and fe1 == 0x1b and fm1 == 0x103 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x23d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xed03; op2val:0x823d; +valaddr_reg:x5; val_offset:716*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 716*FLEN/8, x8, x1, x3) + +inst_383:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x23d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x823d; op2val:0x835d; +valaddr_reg:x5; val_offset:718*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 718*FLEN/8, x8, x1, x3) + +inst_384:// fs1 == 1 and fe1 == 0x1a and fm1 == 0x2ad and fs2 == 1 and fe2 == 0x00 and fm2 == 0x006 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xeaad; op2val:0x8006; +valaddr_reg:x5; val_offset:720*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 720*FLEN/8, x8, x1, x3) + +inst_385:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x005 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x355 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8005; op2val:0xeb55; +valaddr_reg:x5; val_offset:722*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 722*FLEN/8, x8, x1, x3) + +inst_386:// fs1 == 1 and fe1 == 0x1a and fm1 == 0x355 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x005 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xeb55; op2val:0x8005; +valaddr_reg:x5; val_offset:724*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 724*FLEN/8, x8, x1, x3) + +inst_387:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x005 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x006 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8005; op2val:0x8006; +valaddr_reg:x5; val_offset:726*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 726*FLEN/8, x8, x1, x3) + +inst_388:// fs1 == 1 and fe1 == 0x1a and fm1 == 0x2ad and fs2 == 1 and fe2 == 0x00 and fm2 == 0x005 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xeaad; op2val:0x8005; +valaddr_reg:x5; val_offset:728*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 728*FLEN/8, x8, x1, x3) + +inst_389:// fs1 == 1 and fe1 == 0x1a and fm1 == 0x2ad and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ec and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xeaad; op2val:0x82ec; +valaddr_reg:x5; val_offset:730*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 730*FLEN/8, x8, x1, x3) + +inst_390:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x23d and fs2 == 1 and fe2 == 0x1b and fm2 == 0x05b and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x823d; op2val:0xec5b; +valaddr_reg:x5; val_offset:732*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 732*FLEN/8, x8, x1, x3) + +inst_391:// fs1 == 1 and fe1 == 0x1b and fm1 == 0x05b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x23d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xec5b; op2val:0x823d; +valaddr_reg:x5; val_offset:734*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 734*FLEN/8, x8, x1, x3) + +inst_392:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x23d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ec and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x823d; op2val:0x82ec; +valaddr_reg:x5; val_offset:736*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 736*FLEN/8, x8, x1, x3) + +inst_393:// fs1 == 1 and fe1 == 0x1a and fm1 == 0x2ad and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xeaad; op2val:0xf0; +valaddr_reg:x5; val_offset:738*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 738*FLEN/8, x8, x1, x3) + +inst_394:// fs1 == 1 and fe1 == 0x10 and fm1 == 0x2d6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xc2d6; op2val:0xf0; +valaddr_reg:x5; val_offset:740*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 740*FLEN/8, x8, x1, x3) + +inst_395:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2d6 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xc2d6; +valaddr_reg:x5; val_offset:742*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 742*FLEN/8, x8, x1, x3) + +inst_396:// fs1 == 1 and fe1 == 0x1a and fm1 == 0x2ad and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2d6 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xeaad; op2val:0xc2d6; +valaddr_reg:x5; val_offset:744*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 744*FLEN/8, x8, x1, x3) + +inst_397:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x038 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf438; op2val:0xf438; +valaddr_reg:x5; val_offset:746*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 746*FLEN/8, x8, x1, x3) + +inst_398:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x038 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf438; op2val:0xeaad; +valaddr_reg:x5; val_offset:748*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 748*FLEN/8, x8, x1, x3) + +inst_399:// fs1 == 1 and fe1 == 0x19 and fm1 == 0x2c1 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xe6c1; op2val:0xeaad; +valaddr_reg:x5; val_offset:750*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 750*FLEN/8, x8, x1, x3) + +inst_400:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x038 and fs2 == 1 and fe2 == 0x19 and fm2 == 0x2c1 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf438; op2val:0xe6c1; +valaddr_reg:x5; val_offset:752*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 752*FLEN/8, x8, x1, x3) + +inst_401:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x038 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x249 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf438; op2val:0xf649; +valaddr_reg:x5; val_offset:754*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 754*FLEN/8, x8, x1, x3) + +inst_402:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x249 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf649; op2val:0xf438; +valaddr_reg:x5; val_offset:756*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 756*FLEN/8, x8, x1, x3) + +inst_403:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x038 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0d9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf438; op2val:0xf8d9; +valaddr_reg:x5; val_offset:758*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 758*FLEN/8, x8, x1, x3) + +inst_404:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x0d9 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf8d9; op2val:0xf438; +valaddr_reg:x5; val_offset:760*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 760*FLEN/8, x8, x1, x3) + +inst_405:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x038 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x34a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf438; op2val:0xf74a; +valaddr_reg:x5; val_offset:762*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 762*FLEN/8, x8, x1, x3) + +inst_406:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x34a and fs2 == 1 and fe2 == 0x1d and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf74a; op2val:0xf438; +valaddr_reg:x5; val_offset:764*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 764*FLEN/8, x8, x1, x3) + +inst_407:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x038 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf438; op2val:0x3a; +valaddr_reg:x5; val_offset:766*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 766*FLEN/8, x8, x1, x3) + +inst_408:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x01d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x047 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x801d; op2val:0x7847; +valaddr_reg:x5; val_offset:768*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 768*FLEN/8, x8, x1, x3) + +inst_409:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x01d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7847; op2val:0x801d; +valaddr_reg:x5; val_offset:770*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 770*FLEN/8, x8, x1, x3) +RVTEST_SIGBASE(x1,signature_x1_3) + +inst_410:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x01d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x801d; op2val:0x3a; +valaddr_reg:x5; val_offset:772*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 772*FLEN/8, x8, x1, x3) + +inst_411:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x038 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x01d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf438; op2val:0x801d; +valaddr_reg:x5; val_offset:774*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 774*FLEN/8, x8, x1, x3) + +inst_412:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x038 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf438; op2val:0x2ad; +valaddr_reg:x5; val_offset:776*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 776*FLEN/8, x8, x1, x3) + +inst_413:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x122 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0fc and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8122; op2val:0x78fc; +valaddr_reg:x5; val_offset:778*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 778*FLEN/8, x8, x1, x3) + +inst_414:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x122 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x78fc; op2val:0x8122; +valaddr_reg:x5; val_offset:780*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 780*FLEN/8, x8, x1, x3) + +inst_415:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x122 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8122; op2val:0x2ad; +valaddr_reg:x5; val_offset:782*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 782*FLEN/8, x8, x1, x3) + +inst_416:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x038 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x122 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf438; op2val:0x8122; +valaddr_reg:x5; val_offset:784*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 784*FLEN/8, x8, x1, x3) + +inst_417:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x038 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x252 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf438; op2val:0x252; +valaddr_reg:x5; val_offset:786*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 786*FLEN/8, x8, x1, x3) + +inst_418:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x122 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x054 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8122; op2val:0x7854; +valaddr_reg:x5; val_offset:788*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 788*FLEN/8, x8, x1, x3) + +inst_419:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x054 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x122 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7854; op2val:0x8122; +valaddr_reg:x5; val_offset:790*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 790*FLEN/8, x8, x1, x3) + +inst_420:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x122 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x252 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8122; op2val:0x252; +valaddr_reg:x5; val_offset:792*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 792*FLEN/8, x8, x1, x3) + +inst_421:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x038 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e3 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf438; op2val:0x2e3; +valaddr_reg:x5; val_offset:794*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 794*FLEN/8, x8, x1, x3) + +inst_422:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x122 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x162 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8122; op2val:0x7962; +valaddr_reg:x5; val_offset:796*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 796*FLEN/8, x8, x1, x3) + +inst_423:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x162 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x122 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7962; op2val:0x8122; +valaddr_reg:x5; val_offset:798*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 798*FLEN/8, x8, x1, x3) + +inst_424:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x122 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e3 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8122; op2val:0x2e3; +valaddr_reg:x5; val_offset:800*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 800*FLEN/8, x8, x1, x3) + +inst_425:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x038 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf438; op2val:0x1c7; +valaddr_reg:x5; val_offset:802*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 802*FLEN/8, x8, x1, x3) + +inst_426:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x122 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2a1 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8122; op2val:0x76a1; +valaddr_reg:x5; val_offset:804*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 804*FLEN/8, x8, x1, x3) + +inst_427:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x122 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x76a1; op2val:0x8122; +valaddr_reg:x5; val_offset:806*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 806*FLEN/8, x8, x1, x3) + +inst_428:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x122 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8122; op2val:0x1c7; +valaddr_reg:x5; val_offset:808*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 808*FLEN/8, x8, x1, x3) + +inst_429:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x038 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a8 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf438; op2val:0x83a8; +valaddr_reg:x5; val_offset:810*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 810*FLEN/8, x8, x1, x3) + +inst_430:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x122 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2cf and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8122; op2val:0xfacf; +valaddr_reg:x5; val_offset:812*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 812*FLEN/8, x8, x1, x3) + +inst_431:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x2cf and fs2 == 1 and fe2 == 0x00 and fm2 == 0x122 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfacf; op2val:0x8122; +valaddr_reg:x5; val_offset:814*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 814*FLEN/8, x8, x1, x3) + +inst_432:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x122 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a8 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8122; op2val:0x83a8; +valaddr_reg:x5; val_offset:816*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 816*FLEN/8, x8, x1, x3) + +inst_433:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x038 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf438; op2val:0x82c4; +valaddr_reg:x5; val_offset:818*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 818*FLEN/8, x8, x1, x3) + +inst_434:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x122 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x126 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8122; op2val:0xf926; +valaddr_reg:x5; val_offset:820*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 820*FLEN/8, x8, x1, x3) + +inst_435:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x126 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x122 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf926; op2val:0x8122; +valaddr_reg:x5; val_offset:822*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 822*FLEN/8, x8, x1, x3) + +inst_436:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x122 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8122; op2val:0x82c4; +valaddr_reg:x5; val_offset:824*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 824*FLEN/8, x8, x1, x3) + +inst_437:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x038 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf438; op2val:0x835d; +valaddr_reg:x5; val_offset:826*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 826*FLEN/8, x8, x1, x3) + +inst_438:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x122 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x243 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8122; op2val:0xfa43; +valaddr_reg:x5; val_offset:828*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 828*FLEN/8, x8, x1, x3) + +inst_439:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x243 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x122 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa43; op2val:0x8122; +valaddr_reg:x5; val_offset:830*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 830*FLEN/8, x8, x1, x3) + +inst_440:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x122 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8122; op2val:0x835d; +valaddr_reg:x5; val_offset:832*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 832*FLEN/8, x8, x1, x3) + +inst_441:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x038 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x006 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf438; op2val:0x8006; +valaddr_reg:x5; val_offset:834*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 834*FLEN/8, x8, x1, x3) + +inst_442:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x095 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8002; op2val:0xf895; +valaddr_reg:x5; val_offset:836*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 836*FLEN/8, x8, x1, x3) + +inst_443:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x095 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf895; op2val:0x8002; +valaddr_reg:x5; val_offset:838*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 838*FLEN/8, x8, x1, x3) + +inst_444:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x006 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8002; op2val:0x8006; +valaddr_reg:x5; val_offset:840*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 840*FLEN/8, x8, x1, x3) + +inst_445:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x038 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf438; op2val:0x8002; +valaddr_reg:x5; val_offset:842*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 842*FLEN/8, x8, x1, x3) + +inst_446:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x038 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ec and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf438; op2val:0x82ec; +valaddr_reg:x5; val_offset:844*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 844*FLEN/8, x8, x1, x3) + +inst_447:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x122 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x172 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8122; op2val:0xf972; +valaddr_reg:x5; val_offset:846*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 846*FLEN/8, x8, x1, x3) + +inst_448:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x172 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x122 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf972; op2val:0x8122; +valaddr_reg:x5; val_offset:848*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 848*FLEN/8, x8, x1, x3) + +inst_449:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x122 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ec and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8122; op2val:0x82ec; +valaddr_reg:x5; val_offset:850*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 850*FLEN/8, x8, x1, x3) + +inst_450:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x038 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf438; op2val:0xf0; +valaddr_reg:x5; val_offset:852*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 852*FLEN/8, x8, x1, x3) + +inst_451:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x2eb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xbeeb; op2val:0xf0; +valaddr_reg:x5; val_offset:854*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 854*FLEN/8, x8, x1, x3) + +inst_452:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2eb and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xbeeb; +valaddr_reg:x5; val_offset:856*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 856*FLEN/8, x8, x1, x3) + +inst_453:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x038 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2eb and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf438; op2val:0xbeeb; +valaddr_reg:x5; val_offset:858*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 858*FLEN/8, x8, x1, x3) + +inst_454:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x249 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x249 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf649; op2val:0xf649; +valaddr_reg:x5; val_offset:860*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 860*FLEN/8, x8, x1, x3) + +inst_455:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x249 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf649; op2val:0xeaad; +valaddr_reg:x5; val_offset:862*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 862*FLEN/8, x8, x1, x3) + +inst_456:// fs1 == 1 and fe1 == 0x1a and fm1 == 0x107 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xe907; op2val:0xeaad; +valaddr_reg:x5; val_offset:864*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 864*FLEN/8, x8, x1, x3) + +inst_457:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x249 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x107 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf649; op2val:0xe907; +valaddr_reg:x5; val_offset:866*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 866*FLEN/8, x8, x1, x3) + +inst_458:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x249 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0d9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf649; op2val:0xf8d9; +valaddr_reg:x5; val_offset:868*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 868*FLEN/8, x8, x1, x3) + +inst_459:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x0d9 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x249 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf8d9; op2val:0xf649; +valaddr_reg:x5; val_offset:870*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 870*FLEN/8, x8, x1, x3) + +inst_460:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x249 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x34a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf649; op2val:0xf74a; +valaddr_reg:x5; val_offset:872*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 872*FLEN/8, x8, x1, x3) + +inst_461:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x34a and fs2 == 1 and fe2 == 0x1d and fm2 == 0x249 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf74a; op2val:0xf649; +valaddr_reg:x5; val_offset:874*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 874*FLEN/8, x8, x1, x3) + +inst_462:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x249 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf649; op2val:0x3a; +valaddr_reg:x5; val_offset:876*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 876*FLEN/8, x8, x1, x3) + +inst_463:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x02b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x047 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x802b; op2val:0x7847; +valaddr_reg:x5; val_offset:878*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 878*FLEN/8, x8, x1, x3) + +inst_464:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x02b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7847; op2val:0x802b; +valaddr_reg:x5; val_offset:880*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 880*FLEN/8, x8, x1, x3) + +inst_465:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x02b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x802b; op2val:0x3a; +valaddr_reg:x5; val_offset:882*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 882*FLEN/8, x8, x1, x3) + +inst_466:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x249 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x02b and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf649; op2val:0x802b; +valaddr_reg:x5; val_offset:884*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 884*FLEN/8, x8, x1, x3) + +inst_467:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x249 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf649; op2val:0x2ad; +valaddr_reg:x5; val_offset:886*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 886*FLEN/8, x8, x1, x3) + +inst_468:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1b0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0fc and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x81b0; op2val:0x78fc; +valaddr_reg:x5; val_offset:888*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 888*FLEN/8, x8, x1, x3) + +inst_469:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1b0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x78fc; op2val:0x81b0; +valaddr_reg:x5; val_offset:890*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 890*FLEN/8, x8, x1, x3) + +inst_470:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1b0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x81b0; op2val:0x2ad; +valaddr_reg:x5; val_offset:892*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 892*FLEN/8, x8, x1, x3) + +inst_471:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x249 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1b0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf649; op2val:0x81b0; +valaddr_reg:x5; val_offset:894*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 894*FLEN/8, x8, x1, x3) + +inst_472:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x249 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x252 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf649; op2val:0x252; +valaddr_reg:x5; val_offset:896*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 896*FLEN/8, x8, x1, x3) + +inst_473:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1b0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x054 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x81b0; op2val:0x7854; +valaddr_reg:x5; val_offset:898*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 898*FLEN/8, x8, x1, x3) + +inst_474:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x054 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1b0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7854; op2val:0x81b0; +valaddr_reg:x5; val_offset:900*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 900*FLEN/8, x8, x1, x3) + +inst_475:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1b0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x252 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x81b0; op2val:0x252; +valaddr_reg:x5; val_offset:902*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 902*FLEN/8, x8, x1, x3) + +inst_476:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x249 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e3 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf649; op2val:0x2e3; +valaddr_reg:x5; val_offset:904*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 904*FLEN/8, x8, x1, x3) + +inst_477:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1b0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x162 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x81b0; op2val:0x7962; +valaddr_reg:x5; val_offset:906*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 906*FLEN/8, x8, x1, x3) + +inst_478:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x162 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1b0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7962; op2val:0x81b0; +valaddr_reg:x5; val_offset:908*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 908*FLEN/8, x8, x1, x3) + +inst_479:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1b0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e3 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x81b0; op2val:0x2e3; +valaddr_reg:x5; val_offset:910*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 910*FLEN/8, x8, x1, x3) + +inst_480:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x249 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf649; op2val:0x1c7; +valaddr_reg:x5; val_offset:912*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 912*FLEN/8, x8, x1, x3) + +inst_481:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1b0 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2a1 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x81b0; op2val:0x76a1; +valaddr_reg:x5; val_offset:914*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 914*FLEN/8, x8, x1, x3) + +inst_482:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1b0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x76a1; op2val:0x81b0; +valaddr_reg:x5; val_offset:916*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 916*FLEN/8, x8, x1, x3) + +inst_483:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1b0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x81b0; op2val:0x1c7; +valaddr_reg:x5; val_offset:918*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 918*FLEN/8, x8, x1, x3) + +inst_484:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x249 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a8 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf649; op2val:0x83a8; +valaddr_reg:x5; val_offset:920*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 920*FLEN/8, x8, x1, x3) + +inst_485:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1b0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2cf and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x81b0; op2val:0xfacf; +valaddr_reg:x5; val_offset:922*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 922*FLEN/8, x8, x1, x3) + +inst_486:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x2cf and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1b0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfacf; op2val:0x81b0; +valaddr_reg:x5; val_offset:924*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 924*FLEN/8, x8, x1, x3) + +inst_487:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1b0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a8 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x81b0; op2val:0x83a8; +valaddr_reg:x5; val_offset:926*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 926*FLEN/8, x8, x1, x3) + +inst_488:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x249 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf649; op2val:0x82c4; +valaddr_reg:x5; val_offset:928*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 928*FLEN/8, x8, x1, x3) + +inst_489:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1b0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x126 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x81b0; op2val:0xf926; +valaddr_reg:x5; val_offset:930*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 930*FLEN/8, x8, x1, x3) + +inst_490:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x126 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1b0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf926; op2val:0x81b0; +valaddr_reg:x5; val_offset:932*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 932*FLEN/8, x8, x1, x3) + +inst_491:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1b0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x81b0; op2val:0x82c4; +valaddr_reg:x5; val_offset:934*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 934*FLEN/8, x8, x1, x3) + +inst_492:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x249 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf649; op2val:0x835d; +valaddr_reg:x5; val_offset:936*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 936*FLEN/8, x8, x1, x3) + +inst_493:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1b0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x243 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x81b0; op2val:0xfa43; +valaddr_reg:x5; val_offset:938*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 938*FLEN/8, x8, x1, x3) + +inst_494:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x243 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1b0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa43; op2val:0x81b0; +valaddr_reg:x5; val_offset:940*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 940*FLEN/8, x8, x1, x3) + +inst_495:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1b0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x81b0; op2val:0x835d; +valaddr_reg:x5; val_offset:942*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 942*FLEN/8, x8, x1, x3) + +inst_496:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x249 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x006 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf649; op2val:0x8006; +valaddr_reg:x5; val_offset:944*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 944*FLEN/8, x8, x1, x3) + +inst_497:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x004 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x095 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8004; op2val:0xf895; +valaddr_reg:x5; val_offset:946*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 946*FLEN/8, x8, x1, x3) + +inst_498:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x095 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x004 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf895; op2val:0x8004; +valaddr_reg:x5; val_offset:948*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 948*FLEN/8, x8, x1, x3) + +inst_499:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x004 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x006 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8004; op2val:0x8006; +valaddr_reg:x5; val_offset:950*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 950*FLEN/8, x8, x1, x3) + +inst_500:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x249 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x004 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf649; op2val:0x8004; +valaddr_reg:x5; val_offset:952*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 952*FLEN/8, x8, x1, x3) + +inst_501:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x249 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ec and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf649; op2val:0x82ec; +valaddr_reg:x5; val_offset:954*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 954*FLEN/8, x8, x1, x3) + +inst_502:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1b0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x172 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x81b0; op2val:0xf972; +valaddr_reg:x5; val_offset:956*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 956*FLEN/8, x8, x1, x3) + +inst_503:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x172 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1b0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf972; op2val:0x81b0; +valaddr_reg:x5; val_offset:958*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 958*FLEN/8, x8, x1, x3) + +inst_504:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1b0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ec and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x81b0; op2val:0x82ec; +valaddr_reg:x5; val_offset:960*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 960*FLEN/8, x8, x1, x3) + +inst_505:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x249 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf649; op2val:0xf0; +valaddr_reg:x5; val_offset:962*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 962*FLEN/8, x8, x1, x3) + +inst_506:// fs1 == 1 and fe1 == 0x10 and fm1 == 0x126 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xc126; op2val:0xf0; +valaddr_reg:x5; val_offset:964*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 964*FLEN/8, x8, x1, x3) + +inst_507:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x126 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xc126; +valaddr_reg:x5; val_offset:966*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 966*FLEN/8, x8, x1, x3) + +inst_508:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x249 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x126 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf649; op2val:0xc126; +valaddr_reg:x5; val_offset:968*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 968*FLEN/8, x8, x1, x3) + +inst_509:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x0d9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0d9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf8d9; op2val:0xf8d9; +valaddr_reg:x5; val_offset:970*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 970*FLEN/8, x8, x1, x3) + +inst_510:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x0d9 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf8d9; op2val:0xeaad; +valaddr_reg:x5; val_offset:972*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 972*FLEN/8, x8, x1, x3) + +inst_511:// fs1 == 1 and fe1 == 0x1a and fm1 == 0x3c2 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xebc2; op2val:0xeaad; +valaddr_reg:x5; val_offset:974*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 974*FLEN/8, x8, x1, x3) + +inst_512:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x0d9 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x3c2 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf8d9; op2val:0xebc2; +valaddr_reg:x5; val_offset:976*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 976*FLEN/8, x8, x1, x3) + +inst_513:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x0d9 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x34a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf8d9; op2val:0xf74a; +valaddr_reg:x5; val_offset:978*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 978*FLEN/8, x8, x1, x3) + +inst_514:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x34a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0d9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf74a; op2val:0xf8d9; +valaddr_reg:x5; val_offset:980*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 980*FLEN/8, x8, x1, x3) + +inst_515:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x0d9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf8d9; op2val:0x3a; +valaddr_reg:x5; val_offset:982*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 982*FLEN/8, x8, x1, x3) + +inst_516:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x042 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x047 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8042; op2val:0x7847; +valaddr_reg:x5; val_offset:984*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 984*FLEN/8, x8, x1, x3) + +inst_517:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x042 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7847; op2val:0x8042; +valaddr_reg:x5; val_offset:986*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 986*FLEN/8, x8, x1, x3) + +inst_518:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x042 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8042; op2val:0x3a; +valaddr_reg:x5; val_offset:988*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 988*FLEN/8, x8, x1, x3) + +inst_519:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x0d9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x042 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf8d9; op2val:0x8042; +valaddr_reg:x5; val_offset:990*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 990*FLEN/8, x8, x1, x3) + +inst_520:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x0d9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf8d9; op2val:0x2ad; +valaddr_reg:x5; val_offset:992*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 992*FLEN/8, x8, x1, x3) + +inst_521:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x29a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0fc and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x829a; op2val:0x78fc; +valaddr_reg:x5; val_offset:994*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 994*FLEN/8, x8, x1, x3) + +inst_522:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x29a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x78fc; op2val:0x829a; +valaddr_reg:x5; val_offset:996*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 996*FLEN/8, x8, x1, x3) + +inst_523:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x29a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x829a; op2val:0x2ad; +valaddr_reg:x5; val_offset:998*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 998*FLEN/8, x8, x1, x3) + +inst_524:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x0d9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x29a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf8d9; op2val:0x829a; +valaddr_reg:x5; val_offset:1000*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1000*FLEN/8, x8, x1, x3) + +inst_525:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x0d9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x252 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf8d9; op2val:0x252; +valaddr_reg:x5; val_offset:1002*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1002*FLEN/8, x8, x1, x3) + +inst_526:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x29a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x054 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x829a; op2val:0x7854; +valaddr_reg:x5; val_offset:1004*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1004*FLEN/8, x8, x1, x3) + +inst_527:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x054 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x29a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7854; op2val:0x829a; +valaddr_reg:x5; val_offset:1006*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1006*FLEN/8, x8, x1, x3) + +inst_528:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x29a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x252 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x829a; op2val:0x252; +valaddr_reg:x5; val_offset:1008*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1008*FLEN/8, x8, x1, x3) + +inst_529:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x0d9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e3 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf8d9; op2val:0x2e3; +valaddr_reg:x5; val_offset:1010*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1010*FLEN/8, x8, x1, x3) + +inst_530:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x29a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x162 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x829a; op2val:0x7962; +valaddr_reg:x5; val_offset:1012*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1012*FLEN/8, x8, x1, x3) + +inst_531:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x162 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x29a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7962; op2val:0x829a; +valaddr_reg:x5; val_offset:1014*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1014*FLEN/8, x8, x1, x3) + +inst_532:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x29a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e3 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x829a; op2val:0x2e3; +valaddr_reg:x5; val_offset:1016*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1016*FLEN/8, x8, x1, x3) + +inst_533:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x0d9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf8d9; op2val:0x1c7; +valaddr_reg:x5; val_offset:1018*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1018*FLEN/8, x8, x1, x3) + +inst_534:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x29a and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2a1 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x829a; op2val:0x76a1; +valaddr_reg:x5; val_offset:1020*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1020*FLEN/8, x8, x1, x3) + +inst_535:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x29a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x76a1; op2val:0x829a; +valaddr_reg:x5; val_offset:1022*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1022*FLEN/8, x8, x1, x3) + +inst_536:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x29a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x829a; op2val:0x1c7; +valaddr_reg:x5; val_offset:1024*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1024*FLEN/8, x8, x1, x3) + +inst_537:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x0d9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a8 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf8d9; op2val:0x83a8; +valaddr_reg:x5; val_offset:1026*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1026*FLEN/8, x8, x1, x3) +RVTEST_SIGBASE(x1,signature_x1_4) + +inst_538:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x29a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2cf and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x829a; op2val:0xfacf; +valaddr_reg:x5; val_offset:1028*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1028*FLEN/8, x8, x1, x3) + +inst_539:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x2cf and fs2 == 1 and fe2 == 0x00 and fm2 == 0x29a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfacf; op2val:0x829a; +valaddr_reg:x5; val_offset:1030*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1030*FLEN/8, x8, x1, x3) + +inst_540:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x29a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a8 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x829a; op2val:0x83a8; +valaddr_reg:x5; val_offset:1032*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1032*FLEN/8, x8, x1, x3) + +inst_541:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x0d9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf8d9; op2val:0x82c4; +valaddr_reg:x5; val_offset:1034*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1034*FLEN/8, x8, x1, x3) + +inst_542:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x29a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x126 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x829a; op2val:0xf926; +valaddr_reg:x5; val_offset:1036*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1036*FLEN/8, x8, x1, x3) + +inst_543:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x126 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x29a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf926; op2val:0x829a; +valaddr_reg:x5; val_offset:1038*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1038*FLEN/8, x8, x1, x3) + +inst_544:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x29a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x829a; op2val:0x82c4; +valaddr_reg:x5; val_offset:1040*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1040*FLEN/8, x8, x1, x3) + +inst_545:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x0d9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf8d9; op2val:0x835d; +valaddr_reg:x5; val_offset:1042*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1042*FLEN/8, x8, x1, x3) + +inst_546:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x29a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x243 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x829a; op2val:0xfa43; +valaddr_reg:x5; val_offset:1044*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1044*FLEN/8, x8, x1, x3) + +inst_547:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x243 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x29a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa43; op2val:0x829a; +valaddr_reg:x5; val_offset:1046*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1046*FLEN/8, x8, x1, x3) + +inst_548:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x29a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x829a; op2val:0x835d; +valaddr_reg:x5; val_offset:1048*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1048*FLEN/8, x8, x1, x3) + +inst_549:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x0d9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x006 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf8d9; op2val:0x8006; +valaddr_reg:x5; val_offset:1050*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1050*FLEN/8, x8, x1, x3) + +inst_550:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x006 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x095 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8006; op2val:0xf895; +valaddr_reg:x5; val_offset:1052*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1052*FLEN/8, x8, x1, x3) + +inst_551:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x095 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x006 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf895; op2val:0x8006; +valaddr_reg:x5; val_offset:1054*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1054*FLEN/8, x8, x1, x3) + +inst_552:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x006 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x006 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8006; op2val:0x8006; +valaddr_reg:x5; val_offset:1056*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1056*FLEN/8, x8, x1, x3) + +inst_553:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x0d9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ec and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf8d9; op2val:0x82ec; +valaddr_reg:x5; val_offset:1058*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1058*FLEN/8, x8, x1, x3) + +inst_554:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x29a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x172 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x829a; op2val:0xf972; +valaddr_reg:x5; val_offset:1060*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1060*FLEN/8, x8, x1, x3) + +inst_555:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x172 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x29a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf972; op2val:0x829a; +valaddr_reg:x5; val_offset:1062*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1062*FLEN/8, x8, x1, x3) + +inst_556:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x29a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ec and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x829a; op2val:0x82ec; +valaddr_reg:x5; val_offset:1064*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1064*FLEN/8, x8, x1, x3) + +inst_557:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x0d9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf8d9; op2val:0xf0; +valaddr_reg:x5; val_offset:1066*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1066*FLEN/8, x8, x1, x3) + +inst_558:// fs1 == 1 and fe1 == 0x10 and fm1 == 0x3f1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xc3f1; op2val:0xf0; +valaddr_reg:x5; val_offset:1068*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1068*FLEN/8, x8, x1, x3) + +inst_559:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3f1 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xc3f1; +valaddr_reg:x5; val_offset:1070*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1070*FLEN/8, x8, x1, x3) + +inst_560:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x0d9 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3f1 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf8d9; op2val:0xc3f1; +valaddr_reg:x5; val_offset:1072*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1072*FLEN/8, x8, x1, x3) + +inst_561:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x34a and fs2 == 1 and fe2 == 0x1d and fm2 == 0x34a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf74a; op2val:0xf74a; +valaddr_reg:x5; val_offset:1074*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1074*FLEN/8, x8, x1, x3) + +inst_562:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x34a and fs2 == 1 and fe2 == 0x1a and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf74a; op2val:0xeaad; +valaddr_reg:x5; val_offset:1076*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1076*FLEN/8, x8, x1, x3) + +inst_563:// fs1 == 1 and fe1 == 0x1a and fm1 == 0x1d4 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xe9d4; op2val:0xeaad; +valaddr_reg:x5; val_offset:1078*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1078*FLEN/8, x8, x1, x3) + +inst_564:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x34a and fs2 == 1 and fe2 == 0x1a and fm2 == 0x1d4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf74a; op2val:0xe9d4; +valaddr_reg:x5; val_offset:1080*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1080*FLEN/8, x8, x1, x3) + +inst_565:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x34a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf74a; op2val:0x3a; +valaddr_reg:x5; val_offset:1082*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1082*FLEN/8, x8, x1, x3) + +inst_566:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x032 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x047 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8032; op2val:0x7847; +valaddr_reg:x5; val_offset:1084*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1084*FLEN/8, x8, x1, x3) + +inst_567:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x032 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7847; op2val:0x8032; +valaddr_reg:x5; val_offset:1086*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1086*FLEN/8, x8, x1, x3) + +inst_568:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x032 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8032; op2val:0x3a; +valaddr_reg:x5; val_offset:1088*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1088*FLEN/8, x8, x1, x3) + +inst_569:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x34a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x032 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf74a; op2val:0x8032; +valaddr_reg:x5; val_offset:1090*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1090*FLEN/8, x8, x1, x3) + +inst_570:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x34a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf74a; op2val:0x2ad; +valaddr_reg:x5; val_offset:1092*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1092*FLEN/8, x8, x1, x3) + +inst_571:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1f4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0fc and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x81f4; op2val:0x78fc; +valaddr_reg:x5; val_offset:1094*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1094*FLEN/8, x8, x1, x3) + +inst_572:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1f4 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x78fc; op2val:0x81f4; +valaddr_reg:x5; val_offset:1096*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1096*FLEN/8, x8, x1, x3) + +inst_573:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1f4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x81f4; op2val:0x2ad; +valaddr_reg:x5; val_offset:1098*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1098*FLEN/8, x8, x1, x3) + +inst_574:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x34a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1f4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf74a; op2val:0x81f4; +valaddr_reg:x5; val_offset:1100*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1100*FLEN/8, x8, x1, x3) + +inst_575:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x34a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x252 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf74a; op2val:0x252; +valaddr_reg:x5; val_offset:1102*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1102*FLEN/8, x8, x1, x3) + +inst_576:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1f4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x054 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x81f4; op2val:0x7854; +valaddr_reg:x5; val_offset:1104*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1104*FLEN/8, x8, x1, x3) + +inst_577:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x054 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1f4 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7854; op2val:0x81f4; +valaddr_reg:x5; val_offset:1106*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1106*FLEN/8, x8, x1, x3) + +inst_578:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1f4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x252 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x81f4; op2val:0x252; +valaddr_reg:x5; val_offset:1108*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1108*FLEN/8, x8, x1, x3) + +inst_579:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x34a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e3 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf74a; op2val:0x2e3; +valaddr_reg:x5; val_offset:1110*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1110*FLEN/8, x8, x1, x3) + +inst_580:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1f4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x162 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x81f4; op2val:0x7962; +valaddr_reg:x5; val_offset:1112*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1112*FLEN/8, x8, x1, x3) + +inst_581:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x162 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1f4 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7962; op2val:0x81f4; +valaddr_reg:x5; val_offset:1114*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1114*FLEN/8, x8, x1, x3) + +inst_582:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1f4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e3 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x81f4; op2val:0x2e3; +valaddr_reg:x5; val_offset:1116*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1116*FLEN/8, x8, x1, x3) + +inst_583:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x34a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf74a; op2val:0x1c7; +valaddr_reg:x5; val_offset:1118*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1118*FLEN/8, x8, x1, x3) + +inst_584:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1f4 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2a1 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x81f4; op2val:0x76a1; +valaddr_reg:x5; val_offset:1120*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1120*FLEN/8, x8, x1, x3) + +inst_585:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1f4 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x76a1; op2val:0x81f4; +valaddr_reg:x5; val_offset:1122*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1122*FLEN/8, x8, x1, x3) + +inst_586:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1f4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x81f4; op2val:0x1c7; +valaddr_reg:x5; val_offset:1124*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1124*FLEN/8, x8, x1, x3) + +inst_587:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x34a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a8 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf74a; op2val:0x83a8; +valaddr_reg:x5; val_offset:1126*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1126*FLEN/8, x8, x1, x3) + +inst_588:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1f4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2cf and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x81f4; op2val:0xfacf; +valaddr_reg:x5; val_offset:1128*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1128*FLEN/8, x8, x1, x3) + +inst_589:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x2cf and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1f4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfacf; op2val:0x81f4; +valaddr_reg:x5; val_offset:1130*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1130*FLEN/8, x8, x1, x3) + +inst_590:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1f4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a8 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x81f4; op2val:0x83a8; +valaddr_reg:x5; val_offset:1132*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1132*FLEN/8, x8, x1, x3) + +inst_591:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x34a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf74a; op2val:0x82c4; +valaddr_reg:x5; val_offset:1134*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1134*FLEN/8, x8, x1, x3) + +inst_592:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1f4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x126 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x81f4; op2val:0xf926; +valaddr_reg:x5; val_offset:1136*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1136*FLEN/8, x8, x1, x3) + +inst_593:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x126 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1f4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf926; op2val:0x81f4; +valaddr_reg:x5; val_offset:1138*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1138*FLEN/8, x8, x1, x3) + +inst_594:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1f4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x81f4; op2val:0x82c4; +valaddr_reg:x5; val_offset:1140*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1140*FLEN/8, x8, x1, x3) + +inst_595:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x34a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf74a; op2val:0x835d; +valaddr_reg:x5; val_offset:1142*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1142*FLEN/8, x8, x1, x3) + +inst_596:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1f4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x243 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x81f4; op2val:0xfa43; +valaddr_reg:x5; val_offset:1144*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1144*FLEN/8, x8, x1, x3) + +inst_597:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x243 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1f4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa43; op2val:0x81f4; +valaddr_reg:x5; val_offset:1146*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1146*FLEN/8, x8, x1, x3) + +inst_598:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1f4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x81f4; op2val:0x835d; +valaddr_reg:x5; val_offset:1148*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1148*FLEN/8, x8, x1, x3) + +inst_599:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x34a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x006 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf74a; op2val:0x8006; +valaddr_reg:x5; val_offset:1150*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1150*FLEN/8, x8, x1, x3) + +inst_600:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x005 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x095 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8005; op2val:0xf895; +valaddr_reg:x5; val_offset:1152*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1152*FLEN/8, x8, x1, x3) + +inst_601:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x095 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x005 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf895; op2val:0x8005; +valaddr_reg:x5; val_offset:1154*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1154*FLEN/8, x8, x1, x3) + +inst_602:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x34a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x005 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf74a; op2val:0x8005; +valaddr_reg:x5; val_offset:1156*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1156*FLEN/8, x8, x1, x3) + +inst_603:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x34a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ec and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf74a; op2val:0x82ec; +valaddr_reg:x5; val_offset:1158*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1158*FLEN/8, x8, x1, x3) + +inst_604:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1f4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x172 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x81f4; op2val:0xf972; +valaddr_reg:x5; val_offset:1160*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1160*FLEN/8, x8, x1, x3) + +inst_605:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x172 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1f4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf972; op2val:0x81f4; +valaddr_reg:x5; val_offset:1162*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1162*FLEN/8, x8, x1, x3) + +inst_606:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1f4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ec and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x81f4; op2val:0x82ec; +valaddr_reg:x5; val_offset:1164*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1164*FLEN/8, x8, x1, x3) + +inst_607:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x34a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf74a; op2val:0xf0; +valaddr_reg:x5; val_offset:1166*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1166*FLEN/8, x8, x1, x3) + +inst_608:// fs1 == 1 and fe1 == 0x10 and fm1 == 0x1f8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xc1f8; op2val:0xf0; +valaddr_reg:x5; val_offset:1168*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1168*FLEN/8, x8, x1, x3) + +inst_609:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1f8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xc1f8; +valaddr_reg:x5; val_offset:1170*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1170*FLEN/8, x8, x1, x3) + +inst_610:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x34a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1f8 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf74a; op2val:0xc1f8; +valaddr_reg:x5; val_offset:1172*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1172*FLEN/8, x8, x1, x3) + +inst_611:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3a5 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a; op2val:0x7ba5; +valaddr_reg:x5; val_offset:1174*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1174*FLEN/8, x8, x1, x3) + +inst_612:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x047 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3a5 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7847; op2val:0x7ba5; +valaddr_reg:x5; val_offset:1176*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1176*FLEN/8, x8, x1, x3) + +inst_613:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x047 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a; op2val:0x7847; +valaddr_reg:x5; val_offset:1178*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1178*FLEN/8, x8, x1, x3) + +inst_614:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a; op2val:0x3a; +valaddr_reg:x5; val_offset:1180*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1180*FLEN/8, x8, x1, x3) + +inst_615:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ae and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a; op2val:0x7aae; +valaddr_reg:x5; val_offset:1182*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1182*FLEN/8, x8, x1, x3) + +inst_616:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x047 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ae and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7847; op2val:0x7aae; +valaddr_reg:x5; val_offset:1184*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1184*FLEN/8, x8, x1, x3) + +inst_617:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0d8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a; op2val:0x78d8; +valaddr_reg:x5; val_offset:1186*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1186*FLEN/8, x8, x1, x3) + +inst_618:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x047 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0d8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7847; op2val:0x78d8; +valaddr_reg:x5; val_offset:1188*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1188*FLEN/8, x8, x1, x3) + +inst_619:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03a and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2e3 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a; op2val:0x76e3; +valaddr_reg:x5; val_offset:1190*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1190*FLEN/8, x8, x1, x3) + +inst_620:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x047 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2e3 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7847; op2val:0x76e3; +valaddr_reg:x5; val_offset:1192*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1192*FLEN/8, x8, x1, x3) + +inst_621:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x397 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a; op2val:0x7b97; +valaddr_reg:x5; val_offset:1194*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1194*FLEN/8, x8, x1, x3) + +inst_622:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x047 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x397 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7847; op2val:0x7b97; +valaddr_reg:x5; val_offset:1196*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1196*FLEN/8, x8, x1, x3) + +inst_623:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03a and fs2 == 1 and fe2 == 0x1a and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a; op2val:0xeaad; +valaddr_reg:x5; val_offset:1198*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1198*FLEN/8, x8, x1, x3) + +inst_624:// fs1 == 0 and fe1 == 0x1a and fm1 == 0x2d8 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ad8; op2val:0xeaad; +valaddr_reg:x5; val_offset:1200*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1200*FLEN/8, x8, x1, x3) + +inst_625:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03a and fs2 == 0 and fe2 == 0x1a and fm2 == 0x2d8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a; op2val:0x6ad8; +valaddr_reg:x5; val_offset:1202*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1202*FLEN/8, x8, x1, x3) + +inst_626:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03a and fs2 == 1 and fe2 == 0x1d and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a; op2val:0xf438; +valaddr_reg:x5; val_offset:1204*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1204*FLEN/8, x8, x1, x3) + +inst_627:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x047 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7847; op2val:0xf438; +valaddr_reg:x5; val_offset:1206*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1206*FLEN/8, x8, x1, x3) + +inst_628:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03a and fs2 == 1 and fe2 == 0x1d and fm2 == 0x249 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a; op2val:0xf649; +valaddr_reg:x5; val_offset:1208*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1208*FLEN/8, x8, x1, x3) + +inst_629:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x047 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x249 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7847; op2val:0xf649; +valaddr_reg:x5; val_offset:1210*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1210*FLEN/8, x8, x1, x3) + +inst_630:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0d9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a; op2val:0xf8d9; +valaddr_reg:x5; val_offset:1212*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1212*FLEN/8, x8, x1, x3) + +inst_631:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x047 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0d9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7847; op2val:0xf8d9; +valaddr_reg:x5; val_offset:1214*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1214*FLEN/8, x8, x1, x3) + +inst_632:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03a and fs2 == 1 and fe2 == 0x1d and fm2 == 0x34a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a; op2val:0xf74a; +valaddr_reg:x5; val_offset:1216*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1216*FLEN/8, x8, x1, x3) + +inst_633:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x047 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x34a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7847; op2val:0xf74a; +valaddr_reg:x5; val_offset:1218*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1218*FLEN/8, x8, x1, x3) + +inst_634:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a; op2val:0x2ad; +valaddr_reg:x5; val_offset:1220*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1220*FLEN/8, x8, x1, x3) + +inst_635:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x24c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x044 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x24c; op2val:0x44; +valaddr_reg:x5; val_offset:1222*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1222*FLEN/8, x8, x1, x3) + +inst_636:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x044 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x24c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x44; op2val:0x24c; +valaddr_reg:x5; val_offset:1224*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1224*FLEN/8, x8, x1, x3) + +inst_637:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x24c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x24c; op2val:0x2ad; +valaddr_reg:x5; val_offset:1226*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1226*FLEN/8, x8, x1, x3) + +inst_638:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x24c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a; op2val:0x24c; +valaddr_reg:x5; val_offset:1228*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1228*FLEN/8, x8, x1, x3) + +inst_639:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x252 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a; op2val:0x252; +valaddr_reg:x5; val_offset:1230*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1230*FLEN/8, x8, x1, x3) + +inst_640:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x24c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x24c; op2val:0x3b; +valaddr_reg:x5; val_offset:1232*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1232*FLEN/8, x8, x1, x3) + +inst_641:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x24c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b; op2val:0x24c; +valaddr_reg:x5; val_offset:1234*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1234*FLEN/8, x8, x1, x3) + +inst_642:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x24c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x252 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x24c; op2val:0x252; +valaddr_reg:x5; val_offset:1236*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1236*FLEN/8, x8, x1, x3) + +inst_643:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e3 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a; op2val:0x2e3; +valaddr_reg:x5; val_offset:1238*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1238*FLEN/8, x8, x1, x3) + +inst_644:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x24c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x049 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x24c; op2val:0x49; +valaddr_reg:x5; val_offset:1240*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1240*FLEN/8, x8, x1, x3) + +inst_645:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x049 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x24c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x49; op2val:0x24c; +valaddr_reg:x5; val_offset:1242*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1242*FLEN/8, x8, x1, x3) + +inst_646:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x24c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e3 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x24c; op2val:0x2e3; +valaddr_reg:x5; val_offset:1244*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1244*FLEN/8, x8, x1, x3) + +inst_647:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a; op2val:0x1c7; +valaddr_reg:x5; val_offset:1246*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1246*FLEN/8, x8, x1, x3) + +inst_648:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x24c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x02d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x24c; op2val:0x2d; +valaddr_reg:x5; val_offset:1248*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1248*FLEN/8, x8, x1, x3) + +inst_649:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x02d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x24c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d; op2val:0x24c; +valaddr_reg:x5; val_offset:1250*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1250*FLEN/8, x8, x1, x3) + +inst_650:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x24c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x24c; op2val:0x1c7; +valaddr_reg:x5; val_offset:1252*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1252*FLEN/8, x8, x1, x3) + +inst_651:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a; op2val:0x83a8; +valaddr_reg:x5; val_offset:1254*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1254*FLEN/8, x8, x1, x3) + +inst_652:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x24c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x05d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x24c; op2val:0x805d; +valaddr_reg:x5; val_offset:1256*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1256*FLEN/8, x8, x1, x3) + +inst_653:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x05d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x24c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x805d; op2val:0x24c; +valaddr_reg:x5; val_offset:1258*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1258*FLEN/8, x8, x1, x3) + +inst_654:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x24c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x24c; op2val:0x83a8; +valaddr_reg:x5; val_offset:1260*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1260*FLEN/8, x8, x1, x3) + +inst_655:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c4 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a; op2val:0x82c4; +valaddr_reg:x5; val_offset:1262*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1262*FLEN/8, x8, x1, x3) + +inst_656:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x24c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x046 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x24c; op2val:0x8046; +valaddr_reg:x5; val_offset:1264*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1264*FLEN/8, x8, x1, x3) + +inst_657:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x046 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x24c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8046; op2val:0x24c; +valaddr_reg:x5; val_offset:1266*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1266*FLEN/8, x8, x1, x3) + +inst_658:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x24c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c4 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x24c; op2val:0x82c4; +valaddr_reg:x5; val_offset:1268*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1268*FLEN/8, x8, x1, x3) + +inst_659:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a; op2val:0x835d; +valaddr_reg:x5; val_offset:1270*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1270*FLEN/8, x8, x1, x3) + +inst_660:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x24c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x056 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x24c; op2val:0x8056; +valaddr_reg:x5; val_offset:1272*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1272*FLEN/8, x8, x1, x3) + +inst_661:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x056 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x24c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8056; op2val:0x24c; +valaddr_reg:x5; val_offset:1274*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1274*FLEN/8, x8, x1, x3) + +inst_662:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x24c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x24c; op2val:0x835d; +valaddr_reg:x5; val_offset:1276*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1276*FLEN/8, x8, x1, x3) + +inst_663:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x006 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a; op2val:0x8006; +valaddr_reg:x5; val_offset:1278*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1278*FLEN/8, x8, x1, x3) + +inst_664:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x005 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x03f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x5; op2val:0x803f; +valaddr_reg:x5; val_offset:1280*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1280*FLEN/8, x8, x1, x3) + +inst_665:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x005 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x803f; op2val:0x5; +valaddr_reg:x5; val_offset:1282*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1282*FLEN/8, x8, x1, x3) +RVTEST_SIGBASE(x1,signature_x1_5) + +inst_666:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x005 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x006 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x5; op2val:0x8006; +valaddr_reg:x5; val_offset:1284*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1284*FLEN/8, x8, x1, x3) + +inst_667:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x005 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a; op2val:0x5; +valaddr_reg:x5; val_offset:1286*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1286*FLEN/8, x8, x1, x3) + +inst_668:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ec and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a; op2val:0x82ec; +valaddr_reg:x5; val_offset:1288*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1288*FLEN/8, x8, x1, x3) + +inst_669:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x24c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x04a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x24c; op2val:0x804a; +valaddr_reg:x5; val_offset:1290*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1290*FLEN/8, x8, x1, x3) + +inst_670:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x04a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x24c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x804a; op2val:0x24c; +valaddr_reg:x5; val_offset:1292*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1292*FLEN/8, x8, x1, x3) + +inst_671:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x24c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ec and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x24c; op2val:0x82ec; +valaddr_reg:x5; val_offset:1294*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1294*FLEN/8, x8, x1, x3) + +inst_672:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a; op2val:0xf0; +valaddr_reg:x5; val_offset:1296*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1296*FLEN/8, x8, x1, x3) + +inst_673:// fs1 == 0 and fe1 == 0x10 and fm1 == 0x302 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x4302; op2val:0xf0; +valaddr_reg:x5; val_offset:1298*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1298*FLEN/8, x8, x1, x3) + +inst_674:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x302 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x4302; +valaddr_reg:x5; val_offset:1300*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1300*FLEN/8, x8, x1, x3) + +inst_675:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03a and fs2 == 0 and fe2 == 0x10 and fm2 == 0x302 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a; op2val:0x4302; +valaddr_reg:x5; val_offset:1302*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1302*FLEN/8, x8, x1, x3) + +inst_676:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2ad and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3a5 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ad; op2val:0x7ba5; +valaddr_reg:x5; val_offset:1304*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1304*FLEN/8, x8, x1, x3) + +inst_677:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3a5 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x78fc; op2val:0x7ba5; +valaddr_reg:x5; val_offset:1306*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1306*FLEN/8, x8, x1, x3) + +inst_678:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2ad and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0fc and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ad; op2val:0x78fc; +valaddr_reg:x5; val_offset:1308*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1308*FLEN/8, x8, x1, x3) + +inst_679:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2ad and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ad; op2val:0x2ad; +valaddr_reg:x5; val_offset:1310*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1310*FLEN/8, x8, x1, x3) + +inst_680:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2ad and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ae and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ad; op2val:0x7aae; +valaddr_reg:x5; val_offset:1312*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1312*FLEN/8, x8, x1, x3) + +inst_681:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ae and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x78fc; op2val:0x7aae; +valaddr_reg:x5; val_offset:1314*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1314*FLEN/8, x8, x1, x3) + +inst_682:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2ad and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0d8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ad; op2val:0x78d8; +valaddr_reg:x5; val_offset:1316*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1316*FLEN/8, x8, x1, x3) + +inst_683:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0d8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x78fc; op2val:0x78d8; +valaddr_reg:x5; val_offset:1318*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1318*FLEN/8, x8, x1, x3) + +inst_684:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2ad and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2e3 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ad; op2val:0x76e3; +valaddr_reg:x5; val_offset:1320*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1320*FLEN/8, x8, x1, x3) + +inst_685:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fc and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2e3 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x78fc; op2val:0x76e3; +valaddr_reg:x5; val_offset:1322*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1322*FLEN/8, x8, x1, x3) + +inst_686:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2ad and fs2 == 0 and fe2 == 0x1e and fm2 == 0x397 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ad; op2val:0x7b97; +valaddr_reg:x5; val_offset:1324*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1324*FLEN/8, x8, x1, x3) + +inst_687:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x397 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x78fc; op2val:0x7b97; +valaddr_reg:x5; val_offset:1326*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1326*FLEN/8, x8, x1, x3) + +inst_688:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2ad and fs2 == 1 and fe2 == 0x1a and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ad; op2val:0xeaad; +valaddr_reg:x5; val_offset:1328*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1328*FLEN/8, x8, x1, x3) + +inst_689:// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3fa and fs2 == 1 and fe2 == 0x1a and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x6bfa; op2val:0xeaad; +valaddr_reg:x5; val_offset:1330*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1330*FLEN/8, x8, x1, x3) + +inst_690:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2ad and fs2 == 0 and fe2 == 0x1a and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ad; op2val:0x6bfa; +valaddr_reg:x5; val_offset:1332*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1332*FLEN/8, x8, x1, x3) + +inst_691:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2ad and fs2 == 1 and fe2 == 0x1d and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ad; op2val:0xf438; +valaddr_reg:x5; val_offset:1334*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1334*FLEN/8, x8, x1, x3) + +inst_692:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fc and fs2 == 1 and fe2 == 0x1d and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x78fc; op2val:0xf438; +valaddr_reg:x5; val_offset:1336*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1336*FLEN/8, x8, x1, x3) + +inst_693:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2ad and fs2 == 1 and fe2 == 0x1d and fm2 == 0x249 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ad; op2val:0xf649; +valaddr_reg:x5; val_offset:1338*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1338*FLEN/8, x8, x1, x3) + +inst_694:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fc and fs2 == 1 and fe2 == 0x1d and fm2 == 0x249 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x78fc; op2val:0xf649; +valaddr_reg:x5; val_offset:1340*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1340*FLEN/8, x8, x1, x3) + +inst_695:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2ad and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0d9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ad; op2val:0xf8d9; +valaddr_reg:x5; val_offset:1342*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1342*FLEN/8, x8, x1, x3) + +inst_696:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fc and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0d9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x78fc; op2val:0xf8d9; +valaddr_reg:x5; val_offset:1344*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1344*FLEN/8, x8, x1, x3) + +inst_697:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2ad and fs2 == 1 and fe2 == 0x1d and fm2 == 0x34a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ad; op2val:0xf74a; +valaddr_reg:x5; val_offset:1346*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1346*FLEN/8, x8, x1, x3) + +inst_698:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fc and fs2 == 1 and fe2 == 0x1d and fm2 == 0x34a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x78fc; op2val:0xf74a; +valaddr_reg:x5; val_offset:1348*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1348*FLEN/8, x8, x1, x3) + +inst_699:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2ad and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ad; op2val:0x3a; +valaddr_reg:x5; val_offset:1350*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1350*FLEN/8, x8, x1, x3) + +inst_700:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x044 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x44; op2val:0x3a; +valaddr_reg:x5; val_offset:1352*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1352*FLEN/8, x8, x1, x3) + +inst_701:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2ad and fs2 == 0 and fe2 == 0x00 and fm2 == 0x044 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ad; op2val:0x44; +valaddr_reg:x5; val_offset:1354*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1354*FLEN/8, x8, x1, x3) + +inst_702:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2ad and fs2 == 0 and fe2 == 0x00 and fm2 == 0x252 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ad; op2val:0x252; +valaddr_reg:x5; val_offset:1356*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1356*FLEN/8, x8, x1, x3) + +inst_703:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x252 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x252; op2val:0x2ad; +valaddr_reg:x5; val_offset:1358*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1358*FLEN/8, x8, x1, x3) + +inst_704:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2ad and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e3 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ad; op2val:0x2e3; +valaddr_reg:x5; val_offset:1360*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1360*FLEN/8, x8, x1, x3) + +inst_705:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e3; op2val:0x2ad; +valaddr_reg:x5; val_offset:1362*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1362*FLEN/8, x8, x1, x3) + +inst_706:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2ad and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ad; op2val:0x1c7; +valaddr_reg:x5; val_offset:1364*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1364*FLEN/8, x8, x1, x3) + +inst_707:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x1c7; op2val:0x2ad; +valaddr_reg:x5; val_offset:1366*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1366*FLEN/8, x8, x1, x3) + +inst_708:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2ad and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ad; op2val:0x83a8; +valaddr_reg:x5; val_offset:1368*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1368*FLEN/8, x8, x1, x3) + +inst_709:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83a8; op2val:0x2ad; +valaddr_reg:x5; val_offset:1370*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1370*FLEN/8, x8, x1, x3) + +inst_710:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2ad and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c4 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ad; op2val:0x82c4; +valaddr_reg:x5; val_offset:1372*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1372*FLEN/8, x8, x1, x3) + +inst_711:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x82c4; op2val:0x2ad; +valaddr_reg:x5; val_offset:1374*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1374*FLEN/8, x8, x1, x3) + +inst_712:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2ad and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ad; op2val:0x835d; +valaddr_reg:x5; val_offset:1376*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1376*FLEN/8, x8, x1, x3) + +inst_713:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x835d; op2val:0x2ad; +valaddr_reg:x5; val_offset:1378*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1378*FLEN/8, x8, x1, x3) + +inst_714:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2ad and fs2 == 1 and fe2 == 0x00 and fm2 == 0x006 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ad; op2val:0x8006; +valaddr_reg:x5; val_offset:1380*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1380*FLEN/8, x8, x1, x3) + +inst_715:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x006 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x276 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x6; op2val:0x8276; +valaddr_reg:x5; val_offset:1382*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1382*FLEN/8, x8, x1, x3) + +inst_716:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x276 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x006 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8276; op2val:0x6; +valaddr_reg:x5; val_offset:1384*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1384*FLEN/8, x8, x1, x3) + +inst_717:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2ad and fs2 == 0 and fe2 == 0x00 and fm2 == 0x006 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ad; op2val:0x6; +valaddr_reg:x5; val_offset:1386*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1386*FLEN/8, x8, x1, x3) + +inst_718:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2ad and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ec and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ad; op2val:0x82ec; +valaddr_reg:x5; val_offset:1388*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1388*FLEN/8, x8, x1, x3) + +inst_719:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ec and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x82ec; op2val:0x2ad; +valaddr_reg:x5; val_offset:1390*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1390*FLEN/8, x8, x1, x3) + +inst_720:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2ad and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ad; op2val:0xf0; +valaddr_reg:x5; val_offset:1392*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1392*FLEN/8, x8, x1, x3) + +inst_721:// fs1 == 0 and fe1 == 0x11 and fm1 == 0x015 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x4415; op2val:0xf0; +valaddr_reg:x5; val_offset:1394*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1394*FLEN/8, x8, x1, x3) + +inst_722:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x015 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x4415; +valaddr_reg:x5; val_offset:1396*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1396*FLEN/8, x8, x1, x3) + +inst_723:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2ad and fs2 == 0 and fe2 == 0x11 and fm2 == 0x015 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ad; op2val:0x4415; +valaddr_reg:x5; val_offset:1398*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1398*FLEN/8, x8, x1, x3) + +inst_724:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x252 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3a5 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x252; op2val:0x7ba5; +valaddr_reg:x5; val_offset:1400*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1400*FLEN/8, x8, x1, x3) + +inst_725:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x054 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3a5 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7854; op2val:0x7ba5; +valaddr_reg:x5; val_offset:1402*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1402*FLEN/8, x8, x1, x3) + +inst_726:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x252 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x054 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x252; op2val:0x7854; +valaddr_reg:x5; val_offset:1404*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1404*FLEN/8, x8, x1, x3) + +inst_727:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x252 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x252 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x252; op2val:0x252; +valaddr_reg:x5; val_offset:1406*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1406*FLEN/8, x8, x1, x3) + +inst_728:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x252 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ae and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x252; op2val:0x7aae; +valaddr_reg:x5; val_offset:1408*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1408*FLEN/8, x8, x1, x3) + +inst_729:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x054 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ae and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7854; op2val:0x7aae; +valaddr_reg:x5; val_offset:1410*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1410*FLEN/8, x8, x1, x3) + +inst_730:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x252 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0d8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x252; op2val:0x78d8; +valaddr_reg:x5; val_offset:1412*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1412*FLEN/8, x8, x1, x3) + +inst_731:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x054 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0d8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7854; op2val:0x78d8; +valaddr_reg:x5; val_offset:1414*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1414*FLEN/8, x8, x1, x3) + +inst_732:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x252 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2e3 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x252; op2val:0x76e3; +valaddr_reg:x5; val_offset:1416*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1416*FLEN/8, x8, x1, x3) + +inst_733:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x054 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2e3 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7854; op2val:0x76e3; +valaddr_reg:x5; val_offset:1418*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1418*FLEN/8, x8, x1, x3) + +inst_734:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x252 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x397 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x252; op2val:0x7b97; +valaddr_reg:x5; val_offset:1420*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1420*FLEN/8, x8, x1, x3) + +inst_735:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x054 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x397 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7854; op2val:0x7b97; +valaddr_reg:x5; val_offset:1422*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1422*FLEN/8, x8, x1, x3) + +inst_736:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x252 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x252; op2val:0xeaad; +valaddr_reg:x5; val_offset:1424*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1424*FLEN/8, x8, x1, x3) + +inst_737:// fs1 == 0 and fe1 == 0x1a and fm1 == 0x2ed and fs2 == 1 and fe2 == 0x1a and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x6aed; op2val:0xeaad; +valaddr_reg:x5; val_offset:1426*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1426*FLEN/8, x8, x1, x3) + +inst_738:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x252 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x2ed and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x252; op2val:0x6aed; +valaddr_reg:x5; val_offset:1428*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1428*FLEN/8, x8, x1, x3) + +inst_739:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x252 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x252; op2val:0xf438; +valaddr_reg:x5; val_offset:1430*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1430*FLEN/8, x8, x1, x3) + +inst_740:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x054 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7854; op2val:0xf438; +valaddr_reg:x5; val_offset:1432*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1432*FLEN/8, x8, x1, x3) + +inst_741:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x252 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x249 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x252; op2val:0xf649; +valaddr_reg:x5; val_offset:1434*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1434*FLEN/8, x8, x1, x3) + +inst_742:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x054 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x249 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7854; op2val:0xf649; +valaddr_reg:x5; val_offset:1436*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1436*FLEN/8, x8, x1, x3) + +inst_743:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x252 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0d9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x252; op2val:0xf8d9; +valaddr_reg:x5; val_offset:1438*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1438*FLEN/8, x8, x1, x3) + +inst_744:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x054 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0d9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7854; op2val:0xf8d9; +valaddr_reg:x5; val_offset:1440*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1440*FLEN/8, x8, x1, x3) + +inst_745:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x252 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x34a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x252; op2val:0xf74a; +valaddr_reg:x5; val_offset:1442*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1442*FLEN/8, x8, x1, x3) + +inst_746:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x054 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x34a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7854; op2val:0xf74a; +valaddr_reg:x5; val_offset:1444*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1444*FLEN/8, x8, x1, x3) + +inst_747:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x252 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x252; op2val:0x3a; +valaddr_reg:x5; val_offset:1446*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1446*FLEN/8, x8, x1, x3) + +inst_748:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b; op2val:0x3a; +valaddr_reg:x5; val_offset:1448*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1448*FLEN/8, x8, x1, x3) + +inst_749:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x252 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x252; op2val:0x3b; +valaddr_reg:x5; val_offset:1450*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1450*FLEN/8, x8, x1, x3) + +inst_750:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x252 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e3 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x252; op2val:0x2e3; +valaddr_reg:x5; val_offset:1452*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1452*FLEN/8, x8, x1, x3) + +inst_751:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x252 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e3; op2val:0x252; +valaddr_reg:x5; val_offset:1454*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1454*FLEN/8, x8, x1, x3) + +inst_752:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x252 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x252; op2val:0x1c7; +valaddr_reg:x5; val_offset:1456*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1456*FLEN/8, x8, x1, x3) + +inst_753:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x252 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x1c7; op2val:0x252; +valaddr_reg:x5; val_offset:1458*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1458*FLEN/8, x8, x1, x3) + +inst_754:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x252 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x252; op2val:0x83a8; +valaddr_reg:x5; val_offset:1460*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1460*FLEN/8, x8, x1, x3) + +inst_755:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x252 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83a8; op2val:0x252; +valaddr_reg:x5; val_offset:1462*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1462*FLEN/8, x8, x1, x3) + +inst_756:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x252 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c4 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x252; op2val:0x82c4; +valaddr_reg:x5; val_offset:1464*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1464*FLEN/8, x8, x1, x3) + +inst_757:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x252 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x82c4; op2val:0x252; +valaddr_reg:x5; val_offset:1466*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1466*FLEN/8, x8, x1, x3) + +inst_758:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x252 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x252; op2val:0x835d; +valaddr_reg:x5; val_offset:1468*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1468*FLEN/8, x8, x1, x3) + +inst_759:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x252 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x835d; op2val:0x252; +valaddr_reg:x5; val_offset:1470*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1470*FLEN/8, x8, x1, x3) + +inst_760:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x252 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x006 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x252; op2val:0x8006; +valaddr_reg:x5; val_offset:1472*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1472*FLEN/8, x8, x1, x3) + +inst_761:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x005 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x276 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x5; op2val:0x8276; +valaddr_reg:x5; val_offset:1474*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1474*FLEN/8, x8, x1, x3) + +inst_762:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x276 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x005 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8276; op2val:0x5; +valaddr_reg:x5; val_offset:1476*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1476*FLEN/8, x8, x1, x3) + +inst_763:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x252 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x005 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x252; op2val:0x5; +valaddr_reg:x5; val_offset:1478*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1478*FLEN/8, x8, x1, x3) + +inst_764:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x252 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ec and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x252; op2val:0x82ec; +valaddr_reg:x5; val_offset:1480*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1480*FLEN/8, x8, x1, x3) + +inst_765:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ec and fs2 == 0 and fe2 == 0x00 and fm2 == 0x252 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x82ec; op2val:0x252; +valaddr_reg:x5; val_offset:1482*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1482*FLEN/8, x8, x1, x3) + +inst_766:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x252 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x252; op2val:0xf0; +valaddr_reg:x5; val_offset:1484*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1484*FLEN/8, x8, x1, x3) + +inst_767:// fs1 == 0 and fe1 == 0x10 and fm1 == 0x317 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x4317; op2val:0xf0; +valaddr_reg:x5; val_offset:1486*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1486*FLEN/8, x8, x1, x3) + +inst_768:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x317 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x4317; +valaddr_reg:x5; val_offset:1488*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1488*FLEN/8, x8, x1, x3) + +inst_769:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x252 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x317 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x252; op2val:0x4317; +valaddr_reg:x5; val_offset:1490*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1490*FLEN/8, x8, x1, x3) + +inst_770:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3a5 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e3; op2val:0x7ba5; +valaddr_reg:x5; val_offset:1492*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1492*FLEN/8, x8, x1, x3) + +inst_771:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x162 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3a5 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7962; op2val:0x7ba5; +valaddr_reg:x5; val_offset:1494*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1494*FLEN/8, x8, x1, x3) + +inst_772:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x162 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e3; op2val:0x7962; +valaddr_reg:x5; val_offset:1496*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1496*FLEN/8, x8, x1, x3) + +inst_773:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e3 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e3; op2val:0x2e3; +valaddr_reg:x5; val_offset:1498*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1498*FLEN/8, x8, x1, x3) + +inst_774:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ae and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e3; op2val:0x7aae; +valaddr_reg:x5; val_offset:1500*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1500*FLEN/8, x8, x1, x3) + +inst_775:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x162 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ae and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7962; op2val:0x7aae; +valaddr_reg:x5; val_offset:1502*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1502*FLEN/8, x8, x1, x3) + +inst_776:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0d8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e3; op2val:0x78d8; +valaddr_reg:x5; val_offset:1504*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1504*FLEN/8, x8, x1, x3) + +inst_777:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x162 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0d8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7962; op2val:0x78d8; +valaddr_reg:x5; val_offset:1506*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1506*FLEN/8, x8, x1, x3) + +inst_778:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2e3 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e3; op2val:0x76e3; +valaddr_reg:x5; val_offset:1508*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1508*FLEN/8, x8, x1, x3) + +inst_779:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x162 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2e3 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7962; op2val:0x76e3; +valaddr_reg:x5; val_offset:1510*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1510*FLEN/8, x8, x1, x3) + +inst_780:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x397 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e3; op2val:0x7b97; +valaddr_reg:x5; val_offset:1512*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1512*FLEN/8, x8, x1, x3) + +inst_781:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x162 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x397 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7962; op2val:0x7b97; +valaddr_reg:x5; val_offset:1514*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1514*FLEN/8, x8, x1, x3) + +inst_782:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e3 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e3; op2val:0xeaad; +valaddr_reg:x5; val_offset:1516*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1516*FLEN/8, x8, x1, x3) + +inst_783:// fs1 == 0 and fe1 == 0x1b and fm1 == 0x04e and fs2 == 1 and fe2 == 0x1a and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c4e; op2val:0xeaad; +valaddr_reg:x5; val_offset:1518*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1518*FLEN/8, x8, x1, x3) + +inst_784:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x04e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e3; op2val:0x6c4e; +valaddr_reg:x5; val_offset:1520*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1520*FLEN/8, x8, x1, x3) + +inst_785:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e3 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e3; op2val:0xf438; +valaddr_reg:x5; val_offset:1522*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1522*FLEN/8, x8, x1, x3) + +inst_786:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x162 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7962; op2val:0xf438; +valaddr_reg:x5; val_offset:1524*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1524*FLEN/8, x8, x1, x3) + +inst_787:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e3 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x249 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e3; op2val:0xf649; +valaddr_reg:x5; val_offset:1526*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1526*FLEN/8, x8, x1, x3) + +inst_788:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x162 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x249 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7962; op2val:0xf649; +valaddr_reg:x5; val_offset:1528*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1528*FLEN/8, x8, x1, x3) + +inst_789:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0d9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e3; op2val:0xf8d9; +valaddr_reg:x5; val_offset:1530*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1530*FLEN/8, x8, x1, x3) + +inst_790:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x162 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0d9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7962; op2val:0xf8d9; +valaddr_reg:x5; val_offset:1532*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1532*FLEN/8, x8, x1, x3) + +inst_791:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e3 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x34a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e3; op2val:0xf74a; +valaddr_reg:x5; val_offset:1534*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1534*FLEN/8, x8, x1, x3) + +inst_792:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x162 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x34a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7962; op2val:0xf74a; +valaddr_reg:x5; val_offset:1536*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1536*FLEN/8, x8, x1, x3) + +inst_793:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e3; op2val:0x3a; +valaddr_reg:x5; val_offset:1538*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1538*FLEN/8, x8, x1, x3) +RVTEST_SIGBASE(x1,signature_x1_6) + +inst_794:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x049 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x49; op2val:0x3a; +valaddr_reg:x5; val_offset:1540*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1540*FLEN/8, x8, x1, x3) + +inst_795:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x049 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e3; op2val:0x49; +valaddr_reg:x5; val_offset:1542*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1542*FLEN/8, x8, x1, x3) + +inst_796:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e3; op2val:0x1c7; +valaddr_reg:x5; val_offset:1544*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1544*FLEN/8, x8, x1, x3) + +inst_797:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e3 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x1c7; op2val:0x2e3; +valaddr_reg:x5; val_offset:1546*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1546*FLEN/8, x8, x1, x3) + +inst_798:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e3; op2val:0x83a8; +valaddr_reg:x5; val_offset:1548*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1548*FLEN/8, x8, x1, x3) + +inst_799:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e3 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83a8; op2val:0x2e3; +valaddr_reg:x5; val_offset:1550*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1550*FLEN/8, x8, x1, x3) + +inst_800:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c4 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e3; op2val:0x82c4; +valaddr_reg:x5; val_offset:1552*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1552*FLEN/8, x8, x1, x3) + +inst_801:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e3 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x82c4; op2val:0x2e3; +valaddr_reg:x5; val_offset:1554*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1554*FLEN/8, x8, x1, x3) + +inst_802:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e3; op2val:0x835d; +valaddr_reg:x5; val_offset:1556*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1556*FLEN/8, x8, x1, x3) + +inst_803:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e3 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x835d; op2val:0x2e3; +valaddr_reg:x5; val_offset:1558*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1558*FLEN/8, x8, x1, x3) + +inst_804:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x006 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e3; op2val:0x8006; +valaddr_reg:x5; val_offset:1560*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1560*FLEN/8, x8, x1, x3) + +inst_805:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x276 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7; op2val:0x8276; +valaddr_reg:x5; val_offset:1562*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1562*FLEN/8, x8, x1, x3) + +inst_806:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x276 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x007 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8276; op2val:0x7; +valaddr_reg:x5; val_offset:1564*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1564*FLEN/8, x8, x1, x3) + +inst_807:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x006 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7; op2val:0x8006; +valaddr_reg:x5; val_offset:1566*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1566*FLEN/8, x8, x1, x3) + +inst_808:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x007 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e3; op2val:0x7; +valaddr_reg:x5; val_offset:1568*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1568*FLEN/8, x8, x1, x3) + +inst_809:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ec and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e3; op2val:0x82ec; +valaddr_reg:x5; val_offset:1570*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1570*FLEN/8, x8, x1, x3) + +inst_810:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ec and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e3 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x82ec; op2val:0x2e3; +valaddr_reg:x5; val_offset:1572*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1572*FLEN/8, x8, x1, x3) + +inst_811:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e3; op2val:0xf0; +valaddr_reg:x5; val_offset:1574*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1574*FLEN/8, x8, x1, x3) + +inst_812:// fs1 == 0 and fe1 == 0x11 and fm1 == 0x069 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x4469; op2val:0xf0; +valaddr_reg:x5; val_offset:1576*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1576*FLEN/8, x8, x1, x3) + +inst_813:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x069 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x4469; +valaddr_reg:x5; val_offset:1578*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1578*FLEN/8, x8, x1, x3) + +inst_814:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x069 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e3; op2val:0x4469; +valaddr_reg:x5; val_offset:1580*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1580*FLEN/8, x8, x1, x3) + +inst_815:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3a5 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x1c7; op2val:0x7ba5; +valaddr_reg:x5; val_offset:1582*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1582*FLEN/8, x8, x1, x3) + +inst_816:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3a5 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x76a1; op2val:0x7ba5; +valaddr_reg:x5; val_offset:1584*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1584*FLEN/8, x8, x1, x3) + +inst_817:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2a1 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x1c7; op2val:0x76a1; +valaddr_reg:x5; val_offset:1586*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1586*FLEN/8, x8, x1, x3) + +inst_818:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x1c7; op2val:0x1c7; +valaddr_reg:x5; val_offset:1588*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1588*FLEN/8, x8, x1, x3) + +inst_819:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ae and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x1c7; op2val:0x7aae; +valaddr_reg:x5; val_offset:1590*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1590*FLEN/8, x8, x1, x3) + +inst_820:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ae and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x76a1; op2val:0x7aae; +valaddr_reg:x5; val_offset:1592*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1592*FLEN/8, x8, x1, x3) + +inst_821:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0d8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x1c7; op2val:0x78d8; +valaddr_reg:x5; val_offset:1594*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1594*FLEN/8, x8, x1, x3) + +inst_822:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0d8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x76a1; op2val:0x78d8; +valaddr_reg:x5; val_offset:1596*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1596*FLEN/8, x8, x1, x3) + +inst_823:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2e3 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x1c7; op2val:0x76e3; +valaddr_reg:x5; val_offset:1598*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1598*FLEN/8, x8, x1, x3) + +inst_824:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a1 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2e3 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x76a1; op2val:0x76e3; +valaddr_reg:x5; val_offset:1600*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1600*FLEN/8, x8, x1, x3) + +inst_825:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x397 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x1c7; op2val:0x7b97; +valaddr_reg:x5; val_offset:1602*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1602*FLEN/8, x8, x1, x3) + +inst_826:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x397 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x76a1; op2val:0x7b97; +valaddr_reg:x5; val_offset:1604*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1604*FLEN/8, x8, x1, x3) + +inst_827:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c7 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x1c7; op2val:0xeaad; +valaddr_reg:x5; val_offset:1606*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1606*FLEN/8, x8, x1, x3) + +inst_828:// fs1 == 0 and fe1 == 0x1a and fm1 == 0x14d and fs2 == 1 and fe2 == 0x1a and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x694d; op2val:0xeaad; +valaddr_reg:x5; val_offset:1608*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1608*FLEN/8, x8, x1, x3) + +inst_829:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x14d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x1c7; op2val:0x694d; +valaddr_reg:x5; val_offset:1610*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1610*FLEN/8, x8, x1, x3) + +inst_830:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c7 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x1c7; op2val:0xf438; +valaddr_reg:x5; val_offset:1612*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1612*FLEN/8, x8, x1, x3) + +inst_831:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a1 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x76a1; op2val:0xf438; +valaddr_reg:x5; val_offset:1614*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1614*FLEN/8, x8, x1, x3) + +inst_832:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c7 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x249 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x1c7; op2val:0xf649; +valaddr_reg:x5; val_offset:1616*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1616*FLEN/8, x8, x1, x3) + +inst_833:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a1 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x249 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x76a1; op2val:0xf649; +valaddr_reg:x5; val_offset:1618*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1618*FLEN/8, x8, x1, x3) + +inst_834:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c7 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0d9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x1c7; op2val:0xf8d9; +valaddr_reg:x5; val_offset:1620*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1620*FLEN/8, x8, x1, x3) + +inst_835:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a1 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0d9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x76a1; op2val:0xf8d9; +valaddr_reg:x5; val_offset:1622*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1622*FLEN/8, x8, x1, x3) + +inst_836:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c7 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x34a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x1c7; op2val:0xf74a; +valaddr_reg:x5; val_offset:1624*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1624*FLEN/8, x8, x1, x3) + +inst_837:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a1 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x34a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x76a1; op2val:0xf74a; +valaddr_reg:x5; val_offset:1626*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1626*FLEN/8, x8, x1, x3) + +inst_838:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x1c7; op2val:0x3a; +valaddr_reg:x5; val_offset:1628*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1628*FLEN/8, x8, x1, x3) + +inst_839:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x02d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d; op2val:0x3a; +valaddr_reg:x5; val_offset:1630*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1630*FLEN/8, x8, x1, x3) + +inst_840:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x02d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x1c7; op2val:0x2d; +valaddr_reg:x5; val_offset:1632*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1632*FLEN/8, x8, x1, x3) + +inst_841:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x1c7; op2val:0x83a8; +valaddr_reg:x5; val_offset:1634*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1634*FLEN/8, x8, x1, x3) + +inst_842:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83a8; op2val:0x1c7; +valaddr_reg:x5; val_offset:1636*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1636*FLEN/8, x8, x1, x3) + +inst_843:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c4 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x1c7; op2val:0x82c4; +valaddr_reg:x5; val_offset:1638*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1638*FLEN/8, x8, x1, x3) + +inst_844:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x82c4; op2val:0x1c7; +valaddr_reg:x5; val_offset:1640*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1640*FLEN/8, x8, x1, x3) + +inst_845:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x1c7; op2val:0x835d; +valaddr_reg:x5; val_offset:1642*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1642*FLEN/8, x8, x1, x3) + +inst_846:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x835d; op2val:0x1c7; +valaddr_reg:x5; val_offset:1644*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1644*FLEN/8, x8, x1, x3) + +inst_847:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x006 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x1c7; op2val:0x8006; +valaddr_reg:x5; val_offset:1646*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1646*FLEN/8, x8, x1, x3) + +inst_848:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x004 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x276 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x4; op2val:0x8276; +valaddr_reg:x5; val_offset:1648*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1648*FLEN/8, x8, x1, x3) + +inst_849:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x276 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x004 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8276; op2val:0x4; +valaddr_reg:x5; val_offset:1650*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1650*FLEN/8, x8, x1, x3) + +inst_850:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x004 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x1c7; op2val:0x4; +valaddr_reg:x5; val_offset:1652*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1652*FLEN/8, x8, x1, x3) + +inst_851:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ec and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x1c7; op2val:0x82ec; +valaddr_reg:x5; val_offset:1654*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1654*FLEN/8, x8, x1, x3) + +inst_852:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ec and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x82ec; op2val:0x1c7; +valaddr_reg:x5; val_offset:1656*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1656*FLEN/8, x8, x1, x3) + +inst_853:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x1c7; op2val:0xf0; +valaddr_reg:x5; val_offset:1658*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1658*FLEN/8, x8, x1, x3) + +inst_854:// fs1 == 0 and fe1 == 0x10 and fm1 == 0x16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x416e; op2val:0xf0; +valaddr_reg:x5; val_offset:1660*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1660*FLEN/8, x8, x1, x3) + +inst_855:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x16e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x416e; +valaddr_reg:x5; val_offset:1662*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1662*FLEN/8, x8, x1, x3) + +inst_856:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x16e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x1c7; op2val:0x416e; +valaddr_reg:x5; val_offset:1664*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1664*FLEN/8, x8, x1, x3) + +inst_857:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3a5 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83a8; op2val:0x7ba5; +valaddr_reg:x5; val_offset:1666*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1666*FLEN/8, x8, x1, x3) + +inst_858:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x2cf and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3a5 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfacf; op2val:0x7ba5; +valaddr_reg:x5; val_offset:1668*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1668*FLEN/8, x8, x1, x3) + +inst_859:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a8 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2cf and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83a8; op2val:0xfacf; +valaddr_reg:x5; val_offset:1670*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1670*FLEN/8, x8, x1, x3) + +inst_860:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a8 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83a8; op2val:0x83a8; +valaddr_reg:x5; val_offset:1672*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1672*FLEN/8, x8, x1, x3) + +inst_861:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ae and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83a8; op2val:0x7aae; +valaddr_reg:x5; val_offset:1674*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1674*FLEN/8, x8, x1, x3) + +inst_862:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x2cf and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ae and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfacf; op2val:0x7aae; +valaddr_reg:x5; val_offset:1676*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1676*FLEN/8, x8, x1, x3) + +inst_863:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0d8 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83a8; op2val:0x78d8; +valaddr_reg:x5; val_offset:1678*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1678*FLEN/8, x8, x1, x3) + +inst_864:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x2cf and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0d8 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfacf; op2val:0x78d8; +valaddr_reg:x5; val_offset:1680*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1680*FLEN/8, x8, x1, x3) + +inst_865:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a8 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2e3 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83a8; op2val:0x76e3; +valaddr_reg:x5; val_offset:1682*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1682*FLEN/8, x8, x1, x3) + +inst_866:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x2cf and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2e3 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfacf; op2val:0x76e3; +valaddr_reg:x5; val_offset:1684*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1684*FLEN/8, x8, x1, x3) + +inst_867:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x397 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83a8; op2val:0x7b97; +valaddr_reg:x5; val_offset:1686*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1686*FLEN/8, x8, x1, x3) + +inst_868:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x2cf and fs2 == 0 and fe2 == 0x1e and fm2 == 0x397 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfacf; op2val:0x7b97; +valaddr_reg:x5; val_offset:1688*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1688*FLEN/8, x8, x1, x3) + +inst_869:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a8 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83a8; op2val:0xeaad; +valaddr_reg:x5; val_offset:1690*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1690*FLEN/8, x8, x1, x3) + +inst_870:// fs1 == 1 and fe1 == 0x1b and fm1 == 0x173 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xed73; op2val:0xeaad; +valaddr_reg:x5; val_offset:1692*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1692*FLEN/8, x8, x1, x3) + +inst_871:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a8 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x173 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83a8; op2val:0xed73; +valaddr_reg:x5; val_offset:1694*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1694*FLEN/8, x8, x1, x3) + +inst_872:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a8 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83a8; op2val:0xf438; +valaddr_reg:x5; val_offset:1696*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1696*FLEN/8, x8, x1, x3) + +inst_873:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x2cf and fs2 == 1 and fe2 == 0x1d and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfacf; op2val:0xf438; +valaddr_reg:x5; val_offset:1698*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1698*FLEN/8, x8, x1, x3) + +inst_874:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a8 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x249 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83a8; op2val:0xf649; +valaddr_reg:x5; val_offset:1700*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1700*FLEN/8, x8, x1, x3) + +inst_875:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x2cf and fs2 == 1 and fe2 == 0x1d and fm2 == 0x249 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfacf; op2val:0xf649; +valaddr_reg:x5; val_offset:1702*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1702*FLEN/8, x8, x1, x3) + +inst_876:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a8 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0d9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83a8; op2val:0xf8d9; +valaddr_reg:x5; val_offset:1704*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1704*FLEN/8, x8, x1, x3) + +inst_877:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x2cf and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0d9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfacf; op2val:0xf8d9; +valaddr_reg:x5; val_offset:1706*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1706*FLEN/8, x8, x1, x3) + +inst_878:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a8 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x34a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83a8; op2val:0xf74a; +valaddr_reg:x5; val_offset:1708*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1708*FLEN/8, x8, x1, x3) + +inst_879:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x2cf and fs2 == 1 and fe2 == 0x1d and fm2 == 0x34a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfacf; op2val:0xf74a; +valaddr_reg:x5; val_offset:1710*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1710*FLEN/8, x8, x1, x3) + +inst_880:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83a8; op2val:0x3a; +valaddr_reg:x5; val_offset:1712*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1712*FLEN/8, x8, x1, x3) + +inst_881:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x05d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x805d; op2val:0x3a; +valaddr_reg:x5; val_offset:1714*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1714*FLEN/8, x8, x1, x3) + +inst_882:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x05d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83a8; op2val:0x805d; +valaddr_reg:x5; val_offset:1716*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1716*FLEN/8, x8, x1, x3) + +inst_883:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83a8; op2val:0x82c4; +valaddr_reg:x5; val_offset:1718*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1718*FLEN/8, x8, x1, x3) + +inst_884:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a8 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x82c4; op2val:0x83a8; +valaddr_reg:x5; val_offset:1720*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1720*FLEN/8, x8, x1, x3) + +inst_885:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83a8; op2val:0x835d; +valaddr_reg:x5; val_offset:1722*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1722*FLEN/8, x8, x1, x3) + +inst_886:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a8 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x835d; op2val:0x83a8; +valaddr_reg:x5; val_offset:1724*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1724*FLEN/8, x8, x1, x3) + +inst_887:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x006 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83a8; op2val:0x8006; +valaddr_reg:x5; val_offset:1726*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1726*FLEN/8, x8, x1, x3) + +inst_888:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x009 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x276 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8009; op2val:0x8276; +valaddr_reg:x5; val_offset:1728*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1728*FLEN/8, x8, x1, x3) + +inst_889:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x276 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x009 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8276; op2val:0x8009; +valaddr_reg:x5; val_offset:1730*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1730*FLEN/8, x8, x1, x3) + +inst_890:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x009 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x006 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8009; op2val:0x8006; +valaddr_reg:x5; val_offset:1732*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1732*FLEN/8, x8, x1, x3) + +inst_891:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x009 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83a8; op2val:0x8009; +valaddr_reg:x5; val_offset:1734*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1734*FLEN/8, x8, x1, x3) + +inst_892:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ec and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83a8; op2val:0x82ec; +valaddr_reg:x5; val_offset:1736*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1736*FLEN/8, x8, x1, x3) + +inst_893:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ec and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a8 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x82ec; op2val:0x83a8; +valaddr_reg:x5; val_offset:1738*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1738*FLEN/8, x8, x1, x3) + +inst_894:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83a8; op2val:0xf0; +valaddr_reg:x5; val_offset:1740*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1740*FLEN/8, x8, x1, x3) + +inst_895:// fs1 == 1 and fe1 == 0x11 and fm1 == 0x194 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xc594; op2val:0xf0; +valaddr_reg:x5; val_offset:1742*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1742*FLEN/8, x8, x1, x3) + +inst_896:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x194 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xc594; +valaddr_reg:x5; val_offset:1744*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1744*FLEN/8, x8, x1, x3) + +inst_897:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a8 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x194 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x83a8; op2val:0xc594; +valaddr_reg:x5; val_offset:1746*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1746*FLEN/8, x8, x1, x3) + +inst_898:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3a5 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x82c4; op2val:0x7ba5; +valaddr_reg:x5; val_offset:1748*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1748*FLEN/8, x8, x1, x3) + +inst_899:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x126 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3a5 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf926; op2val:0x7ba5; +valaddr_reg:x5; val_offset:1750*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1750*FLEN/8, x8, x1, x3) + +inst_900:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x126 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x82c4; op2val:0xf926; +valaddr_reg:x5; val_offset:1752*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1752*FLEN/8, x8, x1, x3) + +inst_901:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x82c4; op2val:0x82c4; +valaddr_reg:x5; val_offset:1754*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1754*FLEN/8, x8, x1, x3) + +inst_902:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ae and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x82c4; op2val:0x7aae; +valaddr_reg:x5; val_offset:1756*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1756*FLEN/8, x8, x1, x3) + +inst_903:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x126 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ae and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf926; op2val:0x7aae; +valaddr_reg:x5; val_offset:1758*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1758*FLEN/8, x8, x1, x3) + +inst_904:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0d8 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x82c4; op2val:0x78d8; +valaddr_reg:x5; val_offset:1760*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1760*FLEN/8, x8, x1, x3) + +inst_905:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x126 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0d8 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf926; op2val:0x78d8; +valaddr_reg:x5; val_offset:1762*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1762*FLEN/8, x8, x1, x3) + +inst_906:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c4 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2e3 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x82c4; op2val:0x76e3; +valaddr_reg:x5; val_offset:1764*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1764*FLEN/8, x8, x1, x3) + +inst_907:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x126 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2e3 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf926; op2val:0x76e3; +valaddr_reg:x5; val_offset:1766*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1766*FLEN/8, x8, x1, x3) + +inst_908:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x397 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x82c4; op2val:0x7b97; +valaddr_reg:x5; val_offset:1768*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1768*FLEN/8, x8, x1, x3) + +inst_909:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x126 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x397 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf926; op2val:0x7b97; +valaddr_reg:x5; val_offset:1770*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1770*FLEN/8, x8, x1, x3) + +inst_910:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c4 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x82c4; op2val:0xeaad; +valaddr_reg:x5; val_offset:1772*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1772*FLEN/8, x8, x1, x3) + +inst_911:// fs1 == 1 and fe1 == 0x1b and fm1 == 0x01f and fs2 == 1 and fe2 == 0x1a and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xec1f; op2val:0xeaad; +valaddr_reg:x5; val_offset:1774*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1774*FLEN/8, x8, x1, x3) + +inst_912:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c4 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x01f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x82c4; op2val:0xec1f; +valaddr_reg:x5; val_offset:1776*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1776*FLEN/8, x8, x1, x3) + +inst_913:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c4 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x82c4; op2val:0xf438; +valaddr_reg:x5; val_offset:1778*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1778*FLEN/8, x8, x1, x3) + +inst_914:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x126 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf926; op2val:0xf438; +valaddr_reg:x5; val_offset:1780*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1780*FLEN/8, x8, x1, x3) + +inst_915:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c4 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x249 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x82c4; op2val:0xf649; +valaddr_reg:x5; val_offset:1782*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1782*FLEN/8, x8, x1, x3) + +inst_916:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x126 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x249 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf926; op2val:0xf649; +valaddr_reg:x5; val_offset:1784*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1784*FLEN/8, x8, x1, x3) + +inst_917:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0d9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x82c4; op2val:0xf8d9; +valaddr_reg:x5; val_offset:1786*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1786*FLEN/8, x8, x1, x3) + +inst_918:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x126 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0d9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf926; op2val:0xf8d9; +valaddr_reg:x5; val_offset:1788*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1788*FLEN/8, x8, x1, x3) + +inst_919:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c4 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x34a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x82c4; op2val:0xf74a; +valaddr_reg:x5; val_offset:1790*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1790*FLEN/8, x8, x1, x3) + +inst_920:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x126 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x34a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf926; op2val:0xf74a; +valaddr_reg:x5; val_offset:1792*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1792*FLEN/8, x8, x1, x3) + +inst_921:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x82c4; op2val:0x3a; +valaddr_reg:x5; val_offset:1794*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1794*FLEN/8, x8, x1, x3) +RVTEST_SIGBASE(x1,signature_x1_7) + +inst_922:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x046 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8046; op2val:0x3a; +valaddr_reg:x5; val_offset:1796*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1796*FLEN/8, x8, x1, x3) + +inst_923:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x046 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x82c4; op2val:0x8046; +valaddr_reg:x5; val_offset:1798*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1798*FLEN/8, x8, x1, x3) + +inst_924:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x82c4; op2val:0x835d; +valaddr_reg:x5; val_offset:1800*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1800*FLEN/8, x8, x1, x3) + +inst_925:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x835d; op2val:0x82c4; +valaddr_reg:x5; val_offset:1802*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1802*FLEN/8, x8, x1, x3) + +inst_926:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x006 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x82c4; op2val:0x8006; +valaddr_reg:x5; val_offset:1804*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1804*FLEN/8, x8, x1, x3) + +inst_927:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x276 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8007; op2val:0x8276; +valaddr_reg:x5; val_offset:1806*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1806*FLEN/8, x8, x1, x3) + +inst_928:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x276 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x007 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8276; op2val:0x8007; +valaddr_reg:x5; val_offset:1808*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1808*FLEN/8, x8, x1, x3) + +inst_929:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x006 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8007; op2val:0x8006; +valaddr_reg:x5; val_offset:1810*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1810*FLEN/8, x8, x1, x3) + +inst_930:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x007 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x82c4; op2val:0x8007; +valaddr_reg:x5; val_offset:1812*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1812*FLEN/8, x8, x1, x3) + +inst_931:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ec and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x82c4; op2val:0x82ec; +valaddr_reg:x5; val_offset:1814*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1814*FLEN/8, x8, x1, x3) + +inst_932:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ec and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x82ec; op2val:0x82c4; +valaddr_reg:x5; val_offset:1816*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1816*FLEN/8, x8, x1, x3) + +inst_933:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x82c4; op2val:0xf0; +valaddr_reg:x5; val_offset:1818*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1818*FLEN/8, x8, x1, x3) + +inst_934:// fs1 == 1 and fe1 == 0x11 and fm1 == 0x038 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xc438; op2val:0xf0; +valaddr_reg:x5; val_offset:1820*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1820*FLEN/8, x8, x1, x3) + +inst_935:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xc438; +valaddr_reg:x5; val_offset:1822*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1822*FLEN/8, x8, x1, x3) + +inst_936:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c4 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x82c4; op2val:0xc438; +valaddr_reg:x5; val_offset:1824*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1824*FLEN/8, x8, x1, x3) + +inst_937:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3a5 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x835d; op2val:0x7ba5; +valaddr_reg:x5; val_offset:1826*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1826*FLEN/8, x8, x1, x3) + +inst_938:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x243 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3a5 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa43; op2val:0x7ba5; +valaddr_reg:x5; val_offset:1828*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1828*FLEN/8, x8, x1, x3) + +inst_939:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x243 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x835d; op2val:0xfa43; +valaddr_reg:x5; val_offset:1830*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1830*FLEN/8, x8, x1, x3) + +inst_940:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x835d; op2val:0x835d; +valaddr_reg:x5; val_offset:1832*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1832*FLEN/8, x8, x1, x3) + +inst_941:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ae and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x835d; op2val:0x7aae; +valaddr_reg:x5; val_offset:1834*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1834*FLEN/8, x8, x1, x3) + +inst_942:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x243 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ae and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa43; op2val:0x7aae; +valaddr_reg:x5; val_offset:1836*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1836*FLEN/8, x8, x1, x3) + +inst_943:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0d8 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x835d; op2val:0x78d8; +valaddr_reg:x5; val_offset:1838*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1838*FLEN/8, x8, x1, x3) + +inst_944:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x243 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0d8 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa43; op2val:0x78d8; +valaddr_reg:x5; val_offset:1840*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1840*FLEN/8, x8, x1, x3) + +inst_945:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35d and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2e3 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x835d; op2val:0x76e3; +valaddr_reg:x5; val_offset:1842*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1842*FLEN/8, x8, x1, x3) + +inst_946:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x243 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2e3 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa43; op2val:0x76e3; +valaddr_reg:x5; val_offset:1844*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1844*FLEN/8, x8, x1, x3) + +inst_947:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x397 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x835d; op2val:0x7b97; +valaddr_reg:x5; val_offset:1846*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1846*FLEN/8, x8, x1, x3) + +inst_948:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x243 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x397 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa43; op2val:0x7b97; +valaddr_reg:x5; val_offset:1848*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1848*FLEN/8, x8, x1, x3) + +inst_949:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35d and fs2 == 1 and fe2 == 0x1a and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x835d; op2val:0xeaad; +valaddr_reg:x5; val_offset:1850*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1850*FLEN/8, x8, x1, x3) + +inst_950:// fs1 == 1 and fe1 == 0x1b and fm1 == 0x103 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xed03; op2val:0xeaad; +valaddr_reg:x5; val_offset:1852*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1852*FLEN/8, x8, x1, x3) + +inst_951:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35d and fs2 == 1 and fe2 == 0x1b and fm2 == 0x103 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x835d; op2val:0xed03; +valaddr_reg:x5; val_offset:1854*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1854*FLEN/8, x8, x1, x3) + +inst_952:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35d and fs2 == 1 and fe2 == 0x1d and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x835d; op2val:0xf438; +valaddr_reg:x5; val_offset:1856*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1856*FLEN/8, x8, x1, x3) + +inst_953:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x243 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa43; op2val:0xf438; +valaddr_reg:x5; val_offset:1858*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1858*FLEN/8, x8, x1, x3) + +inst_954:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35d and fs2 == 1 and fe2 == 0x1d and fm2 == 0x249 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x835d; op2val:0xf649; +valaddr_reg:x5; val_offset:1860*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1860*FLEN/8, x8, x1, x3) + +inst_955:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x243 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x249 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa43; op2val:0xf649; +valaddr_reg:x5; val_offset:1862*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1862*FLEN/8, x8, x1, x3) + +inst_956:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0d9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x835d; op2val:0xf8d9; +valaddr_reg:x5; val_offset:1864*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1864*FLEN/8, x8, x1, x3) + +inst_957:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x243 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0d9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa43; op2val:0xf8d9; +valaddr_reg:x5; val_offset:1866*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1866*FLEN/8, x8, x1, x3) + +inst_958:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35d and fs2 == 1 and fe2 == 0x1d and fm2 == 0x34a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x835d; op2val:0xf74a; +valaddr_reg:x5; val_offset:1868*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1868*FLEN/8, x8, x1, x3) + +inst_959:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x243 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x34a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa43; op2val:0xf74a; +valaddr_reg:x5; val_offset:1870*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1870*FLEN/8, x8, x1, x3) + +inst_960:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x835d; op2val:0x3a; +valaddr_reg:x5; val_offset:1872*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1872*FLEN/8, x8, x1, x3) + +inst_961:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x056 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8056; op2val:0x3a; +valaddr_reg:x5; val_offset:1874*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1874*FLEN/8, x8, x1, x3) + +inst_962:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x056 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x835d; op2val:0x8056; +valaddr_reg:x5; val_offset:1876*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1876*FLEN/8, x8, x1, x3) + +inst_963:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x006 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x835d; op2val:0x8006; +valaddr_reg:x5; val_offset:1878*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1878*FLEN/8, x8, x1, x3) + +inst_964:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x008 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x276 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8008; op2val:0x8276; +valaddr_reg:x5; val_offset:1880*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1880*FLEN/8, x8, x1, x3) + +inst_965:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x276 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x008 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8276; op2val:0x8008; +valaddr_reg:x5; val_offset:1882*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1882*FLEN/8, x8, x1, x3) + +inst_966:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x008 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x006 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8008; op2val:0x8006; +valaddr_reg:x5; val_offset:1884*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1884*FLEN/8, x8, x1, x3) + +inst_967:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x008 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x835d; op2val:0x8008; +valaddr_reg:x5; val_offset:1886*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1886*FLEN/8, x8, x1, x3) + +inst_968:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ec and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x835d; op2val:0x82ec; +valaddr_reg:x5; val_offset:1888*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1888*FLEN/8, x8, x1, x3) + +inst_969:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ec and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x82ec; op2val:0x835d; +valaddr_reg:x5; val_offset:1890*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1890*FLEN/8, x8, x1, x3) + +inst_970:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x835d; op2val:0xf0; +valaddr_reg:x5; val_offset:1892*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1892*FLEN/8, x8, x1, x3) + +inst_971:// fs1 == 1 and fe1 == 0x11 and fm1 == 0x121 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xc521; op2val:0xf0; +valaddr_reg:x5; val_offset:1894*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1894*FLEN/8, x8, x1, x3) + +inst_972:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x121 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xc521; +valaddr_reg:x5; val_offset:1896*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1896*FLEN/8, x8, x1, x3) + +inst_973:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35d and fs2 == 1 and fe2 == 0x11 and fm2 == 0x121 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x835d; op2val:0xc521; +valaddr_reg:x5; val_offset:1898*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1898*FLEN/8, x8, x1, x3) + +inst_974:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x006 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3a5 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8006; op2val:0x7ba5; +valaddr_reg:x5; val_offset:1900*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1900*FLEN/8, x8, x1, x3) + +inst_975:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x095 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3a5 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf895; op2val:0x7ba5; +valaddr_reg:x5; val_offset:1902*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1902*FLEN/8, x8, x1, x3) + +inst_976:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x006 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ae and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8006; op2val:0x7aae; +valaddr_reg:x5; val_offset:1904*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1904*FLEN/8, x8, x1, x3) + +inst_977:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x095 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ae and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf895; op2val:0x7aae; +valaddr_reg:x5; val_offset:1906*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1906*FLEN/8, x8, x1, x3) + +inst_978:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x006 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0d8 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8006; op2val:0x78d8; +valaddr_reg:x5; val_offset:1908*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1908*FLEN/8, x8, x1, x3) + +inst_979:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x095 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0d8 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf895; op2val:0x78d8; +valaddr_reg:x5; val_offset:1910*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1910*FLEN/8, x8, x1, x3) + +inst_980:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x006 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2e3 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8006; op2val:0x76e3; +valaddr_reg:x5; val_offset:1912*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1912*FLEN/8, x8, x1, x3) + +inst_981:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x095 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2e3 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf895; op2val:0x76e3; +valaddr_reg:x5; val_offset:1914*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1914*FLEN/8, x8, x1, x3) + +inst_982:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x006 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x397 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8006; op2val:0x7b97; +valaddr_reg:x5; val_offset:1916*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1916*FLEN/8, x8, x1, x3) + +inst_983:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x095 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x397 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf895; op2val:0x7b97; +valaddr_reg:x5; val_offset:1918*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1918*FLEN/8, x8, x1, x3) + +inst_984:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x006 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8006; op2val:0xeaad; +valaddr_reg:x5; val_offset:1920*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1920*FLEN/8, x8, x1, x3) + +inst_985:// fs1 == 1 and fe1 == 0x1a and fm1 == 0x355 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xeb55; op2val:0xeaad; +valaddr_reg:x5; val_offset:1922*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1922*FLEN/8, x8, x1, x3) + +inst_986:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x006 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x355 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8006; op2val:0xeb55; +valaddr_reg:x5; val_offset:1924*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1924*FLEN/8, x8, x1, x3) + +inst_987:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x006 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8006; op2val:0xf438; +valaddr_reg:x5; val_offset:1926*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1926*FLEN/8, x8, x1, x3) + +inst_988:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x095 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf895; op2val:0xf438; +valaddr_reg:x5; val_offset:1928*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1928*FLEN/8, x8, x1, x3) + +inst_989:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x006 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x249 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8006; op2val:0xf649; +valaddr_reg:x5; val_offset:1930*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1930*FLEN/8, x8, x1, x3) + +inst_990:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x095 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x249 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf895; op2val:0xf649; +valaddr_reg:x5; val_offset:1932*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1932*FLEN/8, x8, x1, x3) + +inst_991:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x006 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0d9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8006; op2val:0xf8d9; +valaddr_reg:x5; val_offset:1934*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1934*FLEN/8, x8, x1, x3) + +inst_992:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x095 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0d9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf895; op2val:0xf8d9; +valaddr_reg:x5; val_offset:1936*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1936*FLEN/8, x8, x1, x3) + +inst_993:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x006 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x34a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8006; op2val:0xf74a; +valaddr_reg:x5; val_offset:1938*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1938*FLEN/8, x8, x1, x3) + +inst_994:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x095 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x34a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf895; op2val:0xf74a; +valaddr_reg:x5; val_offset:1940*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1940*FLEN/8, x8, x1, x3) + +inst_995:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x006 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8006; op2val:0x3a; +valaddr_reg:x5; val_offset:1942*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1942*FLEN/8, x8, x1, x3) + +inst_996:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x803f; op2val:0x3a; +valaddr_reg:x5; val_offset:1944*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1944*FLEN/8, x8, x1, x3) + +inst_997:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x006 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x03f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8006; op2val:0x803f; +valaddr_reg:x5; val_offset:1946*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1946*FLEN/8, x8, x1, x3) + +inst_998:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x006 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8006; op2val:0x2ad; +valaddr_reg:x5; val_offset:1948*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1948*FLEN/8, x8, x1, x3) + +inst_999:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x276 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8276; op2val:0x2ad; +valaddr_reg:x5; val_offset:1950*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1950*FLEN/8, x8, x1, x3) + +inst_1000:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x006 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x276 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8006; op2val:0x8276; +valaddr_reg:x5; val_offset:1952*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1952*FLEN/8, x8, x1, x3) + +inst_1001:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x006 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x252 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8006; op2val:0x252; +valaddr_reg:x5; val_offset:1954*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1954*FLEN/8, x8, x1, x3) + +inst_1002:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x276 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x252 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8276; op2val:0x252; +valaddr_reg:x5; val_offset:1956*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1956*FLEN/8, x8, x1, x3) + +inst_1003:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x006 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e3 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8006; op2val:0x2e3; +valaddr_reg:x5; val_offset:1958*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1958*FLEN/8, x8, x1, x3) + +inst_1004:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x276 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e3 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8276; op2val:0x2e3; +valaddr_reg:x5; val_offset:1960*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1960*FLEN/8, x8, x1, x3) + +inst_1005:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x006 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8006; op2val:0x1c7; +valaddr_reg:x5; val_offset:1962*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1962*FLEN/8, x8, x1, x3) + +inst_1006:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x276 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8276; op2val:0x1c7; +valaddr_reg:x5; val_offset:1964*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1964*FLEN/8, x8, x1, x3) + +inst_1007:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x006 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a8 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8006; op2val:0x83a8; +valaddr_reg:x5; val_offset:1966*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1966*FLEN/8, x8, x1, x3) + +inst_1008:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x276 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a8 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8276; op2val:0x83a8; +valaddr_reg:x5; val_offset:1968*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1968*FLEN/8, x8, x1, x3) + +inst_1009:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x006 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8006; op2val:0x82c4; +valaddr_reg:x5; val_offset:1970*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1970*FLEN/8, x8, x1, x3) + +inst_1010:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x276 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8276; op2val:0x82c4; +valaddr_reg:x5; val_offset:1972*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1972*FLEN/8, x8, x1, x3) + +inst_1011:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x006 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8006; op2val:0x835d; +valaddr_reg:x5; val_offset:1974*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1974*FLEN/8, x8, x1, x3) + +inst_1012:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x276 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8276; op2val:0x835d; +valaddr_reg:x5; val_offset:1976*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1976*FLEN/8, x8, x1, x3) + +inst_1013:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x006 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ec and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8006; op2val:0x82ec; +valaddr_reg:x5; val_offset:1978*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1978*FLEN/8, x8, x1, x3) + +inst_1014:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x276 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ec and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8276; op2val:0x82ec; +valaddr_reg:x5; val_offset:1980*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1980*FLEN/8, x8, x1, x3) + +inst_1015:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x006 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8006; op2val:0xf0; +valaddr_reg:x5; val_offset:1982*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1982*FLEN/8, x8, x1, x3) + +inst_1016:// fs1 == 1 and fe1 == 0x10 and fm1 == 0x382 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xc382; op2val:0xf0; +valaddr_reg:x5; val_offset:1984*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1984*FLEN/8, x8, x1, x3) + +inst_1017:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x382 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xc382; +valaddr_reg:x5; val_offset:1986*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1986*FLEN/8, x8, x1, x3) + +inst_1018:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x006 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x382 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x8006; op2val:0xc382; +valaddr_reg:x5; val_offset:1988*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1988*FLEN/8, x8, x1, x3) + +inst_1019:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ec and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3a5 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x82ec; op2val:0x7ba5; +valaddr_reg:x5; val_offset:1990*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1990*FLEN/8, x8, x1, x3) + +inst_1020:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x172 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3a5 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf972; op2val:0x7ba5; +valaddr_reg:x5; val_offset:1992*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1992*FLEN/8, x8, x1, x3) + +inst_1021:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ec and fs2 == 1 and fe2 == 0x1e and fm2 == 0x172 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x82ec; op2val:0xf972; +valaddr_reg:x5; val_offset:1994*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1994*FLEN/8, x8, x1, x3) + +inst_1022:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ec and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ec and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x82ec; op2val:0x82ec; +valaddr_reg:x5; val_offset:1996*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1996*FLEN/8, x8, x1, x3) + +inst_1023:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ec and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ae and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x82ec; op2val:0x7aae; +valaddr_reg:x5; val_offset:1998*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 1998*FLEN/8, x8, x1, x3) + +inst_1024:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x172 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ae and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf972; op2val:0x7aae; +valaddr_reg:x5; val_offset:2000*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 2000*FLEN/8, x8, x1, x3) + +inst_1025:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ec and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0d8 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x82ec; op2val:0x78d8; +valaddr_reg:x5; val_offset:2002*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 2002*FLEN/8, x8, x1, x3) + +inst_1026:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x172 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0d8 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf972; op2val:0x78d8; +valaddr_reg:x5; val_offset:2004*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 2004*FLEN/8, x8, x1, x3) + +inst_1027:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ec and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2e3 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x82ec; op2val:0x76e3; +valaddr_reg:x5; val_offset:2006*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 2006*FLEN/8, x8, x1, x3) + +inst_1028:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x172 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2e3 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf972; op2val:0x76e3; +valaddr_reg:x5; val_offset:2008*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 2008*FLEN/8, x8, x1, x3) + +inst_1029:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ec and fs2 == 0 and fe2 == 0x1e and fm2 == 0x397 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x82ec; op2val:0x7b97; +valaddr_reg:x5; val_offset:2010*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 2010*FLEN/8, x8, x1, x3) + +inst_1030:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x172 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x397 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf972; op2val:0x7b97; +valaddr_reg:x5; val_offset:2012*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 2012*FLEN/8, x8, x1, x3) + +inst_1031:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ec and fs2 == 1 and fe2 == 0x1a and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x82ec; op2val:0xeaad; +valaddr_reg:x5; val_offset:2014*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 2014*FLEN/8, x8, x1, x3) + +inst_1032:// fs1 == 1 and fe1 == 0x1b and fm1 == 0x05b and fs2 == 1 and fe2 == 0x1a and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xec5b; op2val:0xeaad; +valaddr_reg:x5; val_offset:2016*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 2016*FLEN/8, x8, x1, x3) + +inst_1033:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ec and fs2 == 1 and fe2 == 0x1b and fm2 == 0x05b and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x82ec; op2val:0xec5b; +valaddr_reg:x5; val_offset:2018*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 2018*FLEN/8, x8, x1, x3) + +inst_1034:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ec and fs2 == 1 and fe2 == 0x1d and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x82ec; op2val:0xf438; +valaddr_reg:x5; val_offset:2020*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 2020*FLEN/8, x8, x1, x3) + +inst_1035:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x172 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf972; op2val:0xf438; +valaddr_reg:x5; val_offset:2022*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 2022*FLEN/8, x8, x1, x3) + +inst_1036:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ec and fs2 == 1 and fe2 == 0x1d and fm2 == 0x249 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x82ec; op2val:0xf649; +valaddr_reg:x5; val_offset:2024*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 2024*FLEN/8, x8, x1, x3) + +inst_1037:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x172 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x249 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf972; op2val:0xf649; +valaddr_reg:x5; val_offset:2026*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 2026*FLEN/8, x8, x1, x3) + +inst_1038:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ec and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0d9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x82ec; op2val:0xf8d9; +valaddr_reg:x5; val_offset:2028*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 2028*FLEN/8, x8, x1, x3) + +inst_1039:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x172 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0d9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf972; op2val:0xf8d9; +valaddr_reg:x5; val_offset:2030*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 2030*FLEN/8, x8, x1, x3) + +inst_1040:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ec and fs2 == 1 and fe2 == 0x1d and fm2 == 0x34a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x82ec; op2val:0xf74a; +valaddr_reg:x5; val_offset:2032*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 2032*FLEN/8, x8, x1, x3) + +inst_1041:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x172 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x34a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf972; op2val:0xf74a; +valaddr_reg:x5; val_offset:2034*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 2034*FLEN/8, x8, x1, x3) + +inst_1042:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ec and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x82ec; op2val:0x3a; +valaddr_reg:x5; val_offset:2036*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 2036*FLEN/8, x8, x1, x3) + +inst_1043:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x04a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x804a; op2val:0x3a; +valaddr_reg:x5; val_offset:2038*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 2038*FLEN/8, x8, x1, x3) + +inst_1044:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ec and fs2 == 1 and fe2 == 0x00 and fm2 == 0x04a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x82ec; op2val:0x804a; +valaddr_reg:x5; val_offset:2040*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 2040*FLEN/8, x8, x1, x3) + +inst_1045:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ec and fs2 == 1 and fe2 == 0x00 and fm2 == 0x006 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x82ec; op2val:0x8006; +valaddr_reg:x5; val_offset:2042*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 2042*FLEN/8, x8, x1, x3) + +inst_1046:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ec and fs2 == 1 and fe2 == 0x00 and fm2 == 0x007 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x82ec; op2val:0x8007; +valaddr_reg:x5; val_offset:2044*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 2044*FLEN/8, x8, x1, x3) + +inst_1047:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ec and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x82ec; op2val:0xf0; +valaddr_reg:x5; val_offset:2046*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 2046*FLEN/8, x8, x1, x3) + +inst_1048:// fs1 == 1 and fe1 == 0x11 and fm1 == 0x076 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xc476; op2val:0xf0; +valaddr_reg:x5; val_offset:2048*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 2048*FLEN/8, x8, x1, x3) + +inst_1049:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x076 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xc476; +valaddr_reg:x5; val_offset:2050*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 2050*FLEN/8, x8, x1, x3) +RVTEST_SIGBASE(x1,signature_x1_8) + +inst_1050:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ec and fs2 == 1 and fe2 == 0x11 and fm2 == 0x076 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x82ec; op2val:0xc476; +valaddr_reg:x5; val_offset:2052*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 2052*FLEN/8, x8, x1, x3) + +inst_1051:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3a5 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x7ba5; +valaddr_reg:x5; val_offset:2054*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 2054*FLEN/8, x8, x1, x3) + +inst_1052:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xf0; +valaddr_reg:x5; val_offset:2056*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 2056*FLEN/8, x8, x1, x3) + +inst_1053:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ae and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x7aae; +valaddr_reg:x5; val_offset:2058*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 2058*FLEN/8, x8, x1, x3) + +inst_1054:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0d8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x78d8; +valaddr_reg:x5; val_offset:2060*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 2060*FLEN/8, x8, x1, x3) + +inst_1055:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2e3 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x76e3; +valaddr_reg:x5; val_offset:2062*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 2062*FLEN/8, x8, x1, x3) + +inst_1056:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x397 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x7b97; +valaddr_reg:x5; val_offset:2064*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 2064*FLEN/8, x8, x1, x3) + +inst_1057:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xeaad; +valaddr_reg:x5; val_offset:2066*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 2066*FLEN/8, x8, x1, x3) + +inst_1058:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xf438; +valaddr_reg:x5; val_offset:2068*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 2068*FLEN/8, x8, x1, x3) + +inst_1059:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x249 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xf649; +valaddr_reg:x5; val_offset:2070*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 2070*FLEN/8, x8, x1, x3) + +inst_1060:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0d9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xf8d9; +valaddr_reg:x5; val_offset:2072*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 2072*FLEN/8, x8, x1, x3) + +inst_1061:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x34a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xf74a; +valaddr_reg:x5; val_offset:2074*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 2074*FLEN/8, x8, x1, x3) + +inst_1062:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x3a; +valaddr_reg:x5; val_offset:2076*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 2076*FLEN/8, x8, x1, x3) + +inst_1063:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2ad and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x2ad; +valaddr_reg:x5; val_offset:2078*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 2078*FLEN/8, x8, x1, x3) + +inst_1064:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x252 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x252; +valaddr_reg:x5; val_offset:2080*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 2080*FLEN/8, x8, x1, x3) + +inst_1065:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e3 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x2e3; +valaddr_reg:x5; val_offset:2082*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 2082*FLEN/8, x8, x1, x3) + +inst_1066:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x1c7; +valaddr_reg:x5; val_offset:2084*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 2084*FLEN/8, x8, x1, x3) + +inst_1067:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x83a8; +valaddr_reg:x5; val_offset:2086*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 2086*FLEN/8, x8, x1, x3) + +inst_1068:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c4 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x82c4; +valaddr_reg:x5; val_offset:2088*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 2088*FLEN/8, x8, x1, x3) + +inst_1069:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x835d; +valaddr_reg:x5; val_offset:2090*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 2090*FLEN/8, x8, x1, x3) + +inst_1070:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x006 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x8006; +valaddr_reg:x5; val_offset:2092*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 2092*FLEN/8, x8, x1, x3) + +inst_1071:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ec and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x82ec; +valaddr_reg:x5; val_offset:2094*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 2094*FLEN/8, x8, x1, x3) + +inst_1072:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3a5 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba5; op2val:0x7ba5; +valaddr_reg:x5; val_offset:2096*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 2096*FLEN/8, x8, x1, x3) + +inst_1073:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ae and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba5; op2val:0x7aae; +valaddr_reg:x5; val_offset:2098*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 2098*FLEN/8, x8, x1, x3) + +inst_1074:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3a5 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x78d8; op2val:0x7ba5; +valaddr_reg:x5; val_offset:2100*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 2100*FLEN/8, x8, x1, x3) + +inst_1075:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x01a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0fc and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: flt.h ; op1:x30; op2:x29; dest:x31; op1val:0x41a; op2val:0x78fc; +valaddr_reg:x5; val_offset:2102*FLEN/8; correctval:??; testreg:x3; +fcsr_val: 0*/ +TEST_FCMP_OP(flt.h, x31, x30, x29, 0, 0, x5, 2102*FLEN/8, x8, x1, x3) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(31406,32,FLEN) +NAN_BOXED(31406,32,FLEN) +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(30936,32,FLEN) +NAN_BOXED(30936,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(30435,32,FLEN) +NAN_BOXED(30435,32,FLEN) +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(31639,32,FLEN) +NAN_BOXED(31639,32,FLEN) +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(60077,16,FLEN) +NAN_BOXED(28189,32,FLEN) +NAN_BOXED(63532,16,FLEN) +NAN_BOXED(63532,16,FLEN) +NAN_BOXED(28189,32,FLEN) +test_dataset_1: +NAN_BOXED(28189,32,FLEN) +NAN_BOXED(60077,16,FLEN) +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(28189,32,FLEN) +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(62520,16,FLEN) +NAN_BOXED(62520,16,FLEN) +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(63049,16,FLEN) +NAN_BOXED(63049,16,FLEN) +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(63705,16,FLEN) +NAN_BOXED(63705,16,FLEN) +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(63306,16,FLEN) +NAN_BOXED(63306,16,FLEN) +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(58,32,FLEN) +NAN_BOXED(105,32,FLEN) +NAN_BOXED(30791,32,FLEN) +test_dataset_2: +NAN_BOXED(30791,16,FLEN) +NAN_BOXED(105,16,FLEN) +NAN_BOXED(105,16,FLEN) +NAN_BOXED(58,16,FLEN) +NAN_BOXED(31653,16,FLEN) +NAN_BOXED(105,16,FLEN) +NAN_BOXED(31653,16,FLEN) +NAN_BOXED(685,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(30972,16,FLEN) +NAN_BOXED(30972,16,FLEN) +NAN_BOXED(1050,16,FLEN) +NAN_BOXED(1050,16,FLEN) +NAN_BOXED(685,16,FLEN) +NAN_BOXED(31653,16,FLEN) +NAN_BOXED(1050,16,FLEN) +NAN_BOXED(31653,16,FLEN) +NAN_BOXED(594,16,FLEN) +NAN_BOXED(1050,16,FLEN) +NAN_BOXED(30804,16,FLEN) +NAN_BOXED(30804,16,FLEN) +NAN_BOXED(1050,16,FLEN) +NAN_BOXED(1050,16,FLEN) +NAN_BOXED(594,16,FLEN) +NAN_BOXED(31653,16,FLEN) +NAN_BOXED(739,16,FLEN) +NAN_BOXED(1050,16,FLEN) +NAN_BOXED(31074,16,FLEN) +NAN_BOXED(31074,16,FLEN) +NAN_BOXED(1050,16,FLEN) +NAN_BOXED(1050,16,FLEN) +NAN_BOXED(739,16,FLEN) +NAN_BOXED(31653,16,FLEN) +NAN_BOXED(455,16,FLEN) +NAN_BOXED(1050,16,FLEN) +NAN_BOXED(30369,16,FLEN) +NAN_BOXED(30369,16,FLEN) +NAN_BOXED(1050,16,FLEN) +NAN_BOXED(1050,16,FLEN) +NAN_BOXED(455,16,FLEN) +NAN_BOXED(31653,16,FLEN) +NAN_BOXED(33704,16,FLEN) +NAN_BOXED(1050,16,FLEN) +NAN_BOXED(64207,16,FLEN) +NAN_BOXED(64207,16,FLEN) +NAN_BOXED(1050,16,FLEN) +NAN_BOXED(1050,16,FLEN) +NAN_BOXED(33704,16,FLEN) +NAN_BOXED(31653,16,FLEN) +NAN_BOXED(33476,16,FLEN) +NAN_BOXED(1050,16,FLEN) +NAN_BOXED(63782,16,FLEN) +NAN_BOXED(63782,16,FLEN) +NAN_BOXED(1050,16,FLEN) +NAN_BOXED(1050,16,FLEN) +NAN_BOXED(33476,16,FLEN) +NAN_BOXED(31653,16,FLEN) +NAN_BOXED(33629,16,FLEN) +NAN_BOXED(1050,16,FLEN) +NAN_BOXED(64067,16,FLEN) +NAN_BOXED(64067,16,FLEN) +NAN_BOXED(1050,16,FLEN) +NAN_BOXED(1050,16,FLEN) +NAN_BOXED(33629,16,FLEN) +NAN_BOXED(31653,16,FLEN) +NAN_BOXED(32774,16,FLEN) +NAN_BOXED(10,16,FLEN) +NAN_BOXED(63637,16,FLEN) +NAN_BOXED(63637,16,FLEN) +NAN_BOXED(10,16,FLEN) +NAN_BOXED(10,16,FLEN) +NAN_BOXED(32774,16,FLEN) +NAN_BOXED(31653,16,FLEN) +NAN_BOXED(10,16,FLEN) +NAN_BOXED(31653,16,FLEN) +NAN_BOXED(33516,16,FLEN) +NAN_BOXED(1050,16,FLEN) +NAN_BOXED(63858,16,FLEN) +NAN_BOXED(63858,16,FLEN) +NAN_BOXED(1050,16,FLEN) +NAN_BOXED(1050,16,FLEN) +NAN_BOXED(33516,16,FLEN) +NAN_BOXED(31653,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(17987,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(17987,16,FLEN) +NAN_BOXED(31653,16,FLEN) +NAN_BOXED(17987,16,FLEN) +NAN_BOXED(31406,16,FLEN) +NAN_BOXED(31406,16,FLEN) +NAN_BOXED(31406,16,FLEN) +NAN_BOXED(30936,16,FLEN) +NAN_BOXED(30936,16,FLEN) +NAN_BOXED(31406,16,FLEN) +NAN_BOXED(31406,16,FLEN) +NAN_BOXED(30435,16,FLEN) +NAN_BOXED(30435,16,FLEN) +NAN_BOXED(31406,16,FLEN) +NAN_BOXED(31406,16,FLEN) +NAN_BOXED(31639,16,FLEN) +NAN_BOXED(31639,16,FLEN) +NAN_BOXED(31406,16,FLEN) +NAN_BOXED(31406,16,FLEN) +NAN_BOXED(60077,16,FLEN) +NAN_BOXED(27992,16,FLEN) +NAN_BOXED(63532,16,FLEN) +NAN_BOXED(63532,16,FLEN) +NAN_BOXED(27992,16,FLEN) +NAN_BOXED(27992,16,FLEN) +NAN_BOXED(60077,16,FLEN) +NAN_BOXED(31406,16,FLEN) +NAN_BOXED(27992,16,FLEN) +NAN_BOXED(31406,16,FLEN) +NAN_BOXED(62520,16,FLEN) +NAN_BOXED(62520,16,FLEN) +NAN_BOXED(31406,16,FLEN) +NAN_BOXED(31406,16,FLEN) +NAN_BOXED(63049,16,FLEN) +NAN_BOXED(63049,16,FLEN) +NAN_BOXED(31406,16,FLEN) +NAN_BOXED(31406,16,FLEN) +NAN_BOXED(63705,16,FLEN) +NAN_BOXED(63705,16,FLEN) +NAN_BOXED(31406,16,FLEN) +NAN_BOXED(31406,16,FLEN) +NAN_BOXED(63306,16,FLEN) +NAN_BOXED(63306,16,FLEN) +NAN_BOXED(31406,16,FLEN) +NAN_BOXED(31406,16,FLEN) +NAN_BOXED(58,16,FLEN) +NAN_BOXED(91,16,FLEN) +NAN_BOXED(30791,16,FLEN) +NAN_BOXED(30791,16,FLEN) +NAN_BOXED(91,16,FLEN) +NAN_BOXED(91,16,FLEN) +NAN_BOXED(58,16,FLEN) +NAN_BOXED(31406,16,FLEN) +NAN_BOXED(91,16,FLEN) +NAN_BOXED(31406,16,FLEN) +NAN_BOXED(685,16,FLEN) +NAN_BOXED(918,16,FLEN) +NAN_BOXED(30972,16,FLEN) +NAN_BOXED(30972,16,FLEN) +NAN_BOXED(918,16,FLEN) +NAN_BOXED(918,16,FLEN) +NAN_BOXED(685,16,FLEN) +NAN_BOXED(31406,16,FLEN) +NAN_BOXED(918,16,FLEN) +NAN_BOXED(31406,16,FLEN) +NAN_BOXED(594,16,FLEN) +NAN_BOXED(918,16,FLEN) +NAN_BOXED(30804,16,FLEN) +NAN_BOXED(30804,16,FLEN) +NAN_BOXED(918,16,FLEN) +NAN_BOXED(918,16,FLEN) +NAN_BOXED(594,16,FLEN) +NAN_BOXED(31406,16,FLEN) +NAN_BOXED(739,16,FLEN) +NAN_BOXED(918,16,FLEN) +NAN_BOXED(31074,16,FLEN) +NAN_BOXED(31074,16,FLEN) +NAN_BOXED(918,16,FLEN) +NAN_BOXED(918,16,FLEN) +NAN_BOXED(739,16,FLEN) +NAN_BOXED(31406,16,FLEN) +NAN_BOXED(455,16,FLEN) +NAN_BOXED(918,16,FLEN) +NAN_BOXED(30369,16,FLEN) +NAN_BOXED(30369,16,FLEN) +NAN_BOXED(918,16,FLEN) +NAN_BOXED(918,16,FLEN) +NAN_BOXED(455,16,FLEN) +NAN_BOXED(31406,16,FLEN) +NAN_BOXED(33704,16,FLEN) +NAN_BOXED(918,16,FLEN) +NAN_BOXED(64207,16,FLEN) +NAN_BOXED(64207,16,FLEN) +NAN_BOXED(918,16,FLEN) +NAN_BOXED(918,16,FLEN) +NAN_BOXED(33704,16,FLEN) +NAN_BOXED(31406,16,FLEN) +NAN_BOXED(33476,16,FLEN) +NAN_BOXED(918,16,FLEN) +NAN_BOXED(63782,16,FLEN) +NAN_BOXED(63782,16,FLEN) +NAN_BOXED(918,16,FLEN) +NAN_BOXED(918,16,FLEN) +NAN_BOXED(33476,16,FLEN) +NAN_BOXED(31406,16,FLEN) +NAN_BOXED(33629,16,FLEN) +NAN_BOXED(918,16,FLEN) +NAN_BOXED(64067,16,FLEN) +NAN_BOXED(64067,16,FLEN) +NAN_BOXED(918,16,FLEN) +NAN_BOXED(918,16,FLEN) +NAN_BOXED(33629,16,FLEN) +NAN_BOXED(31406,16,FLEN) +NAN_BOXED(32774,16,FLEN) +NAN_BOXED(9,16,FLEN) +NAN_BOXED(63637,16,FLEN) +NAN_BOXED(63637,16,FLEN) +NAN_BOXED(9,16,FLEN) +NAN_BOXED(9,16,FLEN) +NAN_BOXED(32774,16,FLEN) +NAN_BOXED(31406,16,FLEN) +NAN_BOXED(9,16,FLEN) +NAN_BOXED(31406,16,FLEN) +NAN_BOXED(33516,16,FLEN) +NAN_BOXED(918,16,FLEN) +NAN_BOXED(63858,16,FLEN) +NAN_BOXED(63858,16,FLEN) +NAN_BOXED(918,16,FLEN) +NAN_BOXED(918,16,FLEN) +NAN_BOXED(33516,16,FLEN) +NAN_BOXED(31406,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(17785,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(17785,16,FLEN) +NAN_BOXED(31406,16,FLEN) +NAN_BOXED(17785,16,FLEN) +NAN_BOXED(30936,16,FLEN) +NAN_BOXED(30936,16,FLEN) +NAN_BOXED(30936,16,FLEN) +NAN_BOXED(30435,16,FLEN) +NAN_BOXED(30435,16,FLEN) +NAN_BOXED(30936,16,FLEN) +NAN_BOXED(30936,16,FLEN) +NAN_BOXED(31639,16,FLEN) +NAN_BOXED(31639,16,FLEN) +NAN_BOXED(30936,16,FLEN) +NAN_BOXED(30936,16,FLEN) +NAN_BOXED(60077,16,FLEN) +NAN_BOXED(27584,16,FLEN) +NAN_BOXED(63532,16,FLEN) +NAN_BOXED(63532,16,FLEN) +NAN_BOXED(27584,16,FLEN) +NAN_BOXED(27584,16,FLEN) +NAN_BOXED(60077,16,FLEN) +NAN_BOXED(30936,16,FLEN) +NAN_BOXED(27584,16,FLEN) +NAN_BOXED(30936,16,FLEN) +NAN_BOXED(62520,16,FLEN) +NAN_BOXED(62520,16,FLEN) +NAN_BOXED(30936,16,FLEN) +NAN_BOXED(30936,16,FLEN) +NAN_BOXED(63049,16,FLEN) +NAN_BOXED(63049,16,FLEN) +NAN_BOXED(30936,16,FLEN) +NAN_BOXED(30936,16,FLEN) +NAN_BOXED(63705,16,FLEN) +NAN_BOXED(63705,16,FLEN) +NAN_BOXED(30936,16,FLEN) +NAN_BOXED(30936,16,FLEN) +NAN_BOXED(63306,16,FLEN) +NAN_BOXED(63306,16,FLEN) +NAN_BOXED(30936,16,FLEN) +NAN_BOXED(30936,16,FLEN) +NAN_BOXED(58,16,FLEN) +NAN_BOXED(66,16,FLEN) +NAN_BOXED(30791,16,FLEN) +NAN_BOXED(30791,16,FLEN) +NAN_BOXED(66,16,FLEN) +NAN_BOXED(66,16,FLEN) +NAN_BOXED(58,16,FLEN) +NAN_BOXED(30936,16,FLEN) +NAN_BOXED(66,16,FLEN) +NAN_BOXED(30936,16,FLEN) +NAN_BOXED(685,16,FLEN) +NAN_BOXED(665,16,FLEN) +NAN_BOXED(30972,16,FLEN) +NAN_BOXED(30972,16,FLEN) +NAN_BOXED(665,16,FLEN) +NAN_BOXED(665,16,FLEN) +NAN_BOXED(685,16,FLEN) +NAN_BOXED(30936,16,FLEN) +NAN_BOXED(665,16,FLEN) +NAN_BOXED(30936,16,FLEN) +NAN_BOXED(594,16,FLEN) +NAN_BOXED(665,16,FLEN) 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+NAN_BOXED(32774,16,FLEN) +NAN_BOXED(33398,16,FLEN) +NAN_BOXED(32774,16,FLEN) +NAN_BOXED(594,16,FLEN) +NAN_BOXED(33398,16,FLEN) +NAN_BOXED(594,16,FLEN) +NAN_BOXED(32774,16,FLEN) +NAN_BOXED(739,16,FLEN) +NAN_BOXED(33398,16,FLEN) +NAN_BOXED(739,16,FLEN) +NAN_BOXED(32774,16,FLEN) +NAN_BOXED(455,16,FLEN) +NAN_BOXED(33398,16,FLEN) +NAN_BOXED(455,16,FLEN) +NAN_BOXED(32774,16,FLEN) +NAN_BOXED(33704,16,FLEN) +NAN_BOXED(33398,16,FLEN) +NAN_BOXED(33704,16,FLEN) +NAN_BOXED(32774,16,FLEN) +NAN_BOXED(33476,16,FLEN) +NAN_BOXED(33398,16,FLEN) +NAN_BOXED(33476,16,FLEN) +NAN_BOXED(32774,16,FLEN) +NAN_BOXED(33629,16,FLEN) +NAN_BOXED(33398,16,FLEN) +NAN_BOXED(33629,16,FLEN) +NAN_BOXED(32774,16,FLEN) +NAN_BOXED(33516,16,FLEN) +NAN_BOXED(33398,16,FLEN) +NAN_BOXED(33516,16,FLEN) +NAN_BOXED(32774,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(50050,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(50050,16,FLEN) +NAN_BOXED(32774,16,FLEN) +NAN_BOXED(50050,16,FLEN) +NAN_BOXED(33516,16,FLEN) +NAN_BOXED(31653,16,FLEN) +NAN_BOXED(63858,16,FLEN) +NAN_BOXED(31653,16,FLEN) +NAN_BOXED(33516,16,FLEN) +NAN_BOXED(63858,16,FLEN) +NAN_BOXED(33516,16,FLEN) +NAN_BOXED(33516,16,FLEN) +NAN_BOXED(33516,16,FLEN) +NAN_BOXED(31406,16,FLEN) +NAN_BOXED(63858,16,FLEN) +NAN_BOXED(31406,16,FLEN) +NAN_BOXED(33516,16,FLEN) +NAN_BOXED(30936,16,FLEN) +NAN_BOXED(63858,16,FLEN) +NAN_BOXED(30936,16,FLEN) +NAN_BOXED(33516,16,FLEN) +NAN_BOXED(30435,16,FLEN) +NAN_BOXED(63858,16,FLEN) +NAN_BOXED(30435,16,FLEN) +NAN_BOXED(33516,16,FLEN) +NAN_BOXED(31639,16,FLEN) +NAN_BOXED(63858,16,FLEN) +NAN_BOXED(31639,16,FLEN) +NAN_BOXED(33516,16,FLEN) +NAN_BOXED(60077,16,FLEN) +NAN_BOXED(60507,16,FLEN) +NAN_BOXED(60077,16,FLEN) +NAN_BOXED(33516,16,FLEN) +NAN_BOXED(60507,16,FLEN) +NAN_BOXED(33516,16,FLEN) +NAN_BOXED(62520,16,FLEN) +NAN_BOXED(63858,16,FLEN) +NAN_BOXED(62520,16,FLEN) +NAN_BOXED(33516,16,FLEN) +NAN_BOXED(63049,16,FLEN) +NAN_BOXED(63858,16,FLEN) +NAN_BOXED(63049,16,FLEN) +NAN_BOXED(33516,16,FLEN) +NAN_BOXED(63705,16,FLEN) +NAN_BOXED(63858,16,FLEN) +NAN_BOXED(63705,16,FLEN) +NAN_BOXED(33516,16,FLEN) +NAN_BOXED(63306,16,FLEN) +NAN_BOXED(63858,16,FLEN) +NAN_BOXED(63306,16,FLEN) +NAN_BOXED(33516,16,FLEN) +NAN_BOXED(58,16,FLEN) +NAN_BOXED(32842,16,FLEN) +NAN_BOXED(58,16,FLEN) +NAN_BOXED(33516,16,FLEN) +NAN_BOXED(32842,16,FLEN) +NAN_BOXED(33516,16,FLEN) +NAN_BOXED(32774,16,FLEN) +NAN_BOXED(33516,16,FLEN) +NAN_BOXED(32775,16,FLEN) +NAN_BOXED(33516,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(50294,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(50294,16,FLEN) +NAN_BOXED(33516,16,FLEN) +NAN_BOXED(50294,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(31653,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(31406,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(30936,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(30435,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(31639,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(60077,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(62520,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(63049,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(63705,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(63306,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(58,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(685,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(594,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(739,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(455,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(33704,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(33476,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(33629,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(32774,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(33516,16,FLEN) +NAN_BOXED(31653,16,FLEN) +NAN_BOXED(31653,16,FLEN) +NAN_BOXED(31653,16,FLEN) +NAN_BOXED(31406,16,FLEN) +NAN_BOXED(30936,16,FLEN) +NAN_BOXED(31653,16,FLEN) +NAN_BOXED(1050,16,FLEN) +NAN_BOXED(30972,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x2_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_1: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x4_0: + .fill 24*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_0: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_2: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_3: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_4: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_5: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_6: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_7: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_8: + .fill 52*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fmadd_b1-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fmadd_b1-01.S new file mode 100644 index 000000000..5a873992a --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fmadd_b1-01.S @@ -0,0 +1,139001 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 04:10:09 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fmadd.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fmadd.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fmadd_b1 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fmadd_b1) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x2,test_dataset_0) +RVTEST_SIGBASE(x5,signature_x5_1) + +inst_0: +// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==x10, rs2==x10, rs3==x3, rd==x22,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x10; op2:x10; op3:x3; dest:x22; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x2; val_offset:0*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x22, x10, x10, x3, dyn, 0, 0, x2, 0*FLEN/8, x11, x5, x6) + +inst_1: +// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==x25, rs2==x27, rs3==x25, rd==x18,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x25; op2:x27; op3:x25; dest:x18; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x2; val_offset:3*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x18, x25, x27, x25, dyn, 0, 0, x2, 3*FLEN/8, x11, x5, x6) + +inst_2: +// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==x1, rs2==x8, rs3==x2, rd==x1,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x1; op2:x8; op3:x2; dest:x1; op1val:0x0; op2val:0x0; +op3val:0x1; valaddr_reg:x2; val_offset:6*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x1, x1, x8, x2, dyn, 0, 0, x2, 6*FLEN/8, x11, x5, x6) + +inst_3: +// rs1 == rs2 == rs3 != rd, rs1==x15, rs2==x15, rs3==x15, rd==x26,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x15; op2:x15; op3:x15; dest:x26; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x2; val_offset:9*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x26, x15, x15, x15, dyn, 0, 0, x2, 9*FLEN/8, x11, x5, x6) + +inst_4: +// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==x26, rs2==x12, rs3==x31, rd==x31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x26; op2:x12; op3:x31; dest:x31; op1val:0x0; op2val:0x0; +op3val:0x2; valaddr_reg:x2; val_offset:12*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x26, x12, x31, dyn, 0, 0, x2, 12*FLEN/8, x11, x5, x6) + +inst_5: +// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==x23, rs2==x13, rs3==x17, rd==x13,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x23; op2:x13; op3:x17; dest:x13; op1val:0x0; op2val:0x0; +op3val:0x83fe; valaddr_reg:x2; val_offset:15*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x13, x23, x13, x17, dyn, 0, 0, x2, 15*FLEN/8, x11, x5, x6) + +inst_6: +// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==x28, rs2==x14, rs3==x19, rd==x24,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x28; op2:x14; op3:x19; dest:x24; op1val:0x0; op2val:0x0; +op3val:0x3ff; valaddr_reg:x2; val_offset:18*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x24, x28, x14, x19, dyn, 0, 0, x2, 18*FLEN/8, x11, x5, x6) + +inst_7: +// rd == rs2 == rs3 != rs1, rs1==x18, rs2==x9, rs3==x9, rd==x9,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x18; op2:x9; op3:x9; dest:x9; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x2; val_offset:21*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x9, x18, x9, x9, dyn, 0, 0, x2, 21*FLEN/8, x11, x5, x6) + +inst_8: +// rs1 == rd == rs3 != rs2, rs1==x27, rs2==x29, rs3==x27, rd==x27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x27; op2:x29; op3:x27; dest:x27; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x2; val_offset:24*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x27, x27, x29, x27, dyn, 0, 0, x2, 24*FLEN/8, x11, x5, x6) + +inst_9: +// rs1 == rs2 == rs3 == rd, rs1==x7, rs2==x7, rs3==x7, rd==x7,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x7; op2:x7; op3:x7; dest:x7; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x2; val_offset:27*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x7, x7, x7, x7, dyn, 0, 0, x2, 27*FLEN/8, x11, x5, x6) + +inst_10: +// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==x4, rs2==x1, rs3==x1, rd==x3,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x4; op2:x1; op3:x1; dest:x3; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x2; val_offset:30*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x3, x4, x1, x1, dyn, 0, 0, x2, 30*FLEN/8, x11, x5, x6) + +inst_11: +// rs1 == rs2 == rd != rs3, rs1==x21, rs2==x21, rs3==x23, rd==x21,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x21; op2:x21; op3:x23; dest:x21; op1val:0x0; op2val:0x0; +op3val:0x8455; valaddr_reg:x2; val_offset:33*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x21, x21, x21, x23, dyn, 0, 0, x2, 33*FLEN/8, x11, x5, x6) +RVTEST_VALBASEUPD(x10,test_dataset_1) + +inst_12: +// rs1==x14, rs2==x2, rs3==x26, rd==x20,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x14; op2:x2; op3:x26; dest:x20; op1val:0x0; op2val:0x0; +op3val:0x7bff; valaddr_reg:x10; val_offset:0*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x20, x14, x2, x26, dyn, 0, 0, x10, 0*FLEN/8, x15, x5, x6) + +inst_13: +// rs1==x8, rs2==x6, rs3==x20, rd==x25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x8; op2:x6; op3:x20; dest:x25; op1val:0x0; op2val:0x0; +op3val:0xfbff; valaddr_reg:x10; val_offset:3*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x25, x8, x6, x20, dyn, 0, 0, x10, 3*FLEN/8, x15, x5, x7) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_14: +// rs1==x22, rs2==x5, rs3==x29, rd==x23,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x22; op2:x5; op3:x29; dest:x23; op1val:0x0; op2val:0x0; +op3val:0x7c00; valaddr_reg:x10; val_offset:6*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x23, x22, x5, x29, dyn, 0, 0, x10, 6*FLEN/8, x15, x1, x7) + +inst_15: +// rs1==x9, rs2==x17, rs3==x16, rd==x5,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x9; op2:x17; op3:x16; dest:x5; op1val:0x0; op2val:0x0; +op3val:0xfc00; valaddr_reg:x10; val_offset:9*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x5, x9, x17, x16, dyn, 0, 0, x10, 9*FLEN/8, x15, x1, x7) + +inst_16: +// rs1==x0, rs2==x24, rs3==x28, rd==x19,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x0; op2:x24; op3:x28; dest:x19; op1val:0x0; op2val:0x0; +op3val:0x7e00; valaddr_reg:x10; val_offset:12*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x19, x0, x24, x28, dyn, 0, 0, x10, 12*FLEN/8, x15, x1, x7) + +inst_17: +// rs1==x13, rs2==x16, rs3==x4, rd==x11,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x13; op2:x16; op3:x4; dest:x11; op1val:0x0; op2val:0x0; +op3val:0xfe00; valaddr_reg:x10; val_offset:15*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x11, x13, x16, x4, dyn, 0, 0, x10, 15*FLEN/8, x15, x1, x7) + +inst_18: +// rs1==x17, rs2==x3, rs3==x0, rd==x14,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x17; op2:x3; op3:x0; dest:x14; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x10; val_offset:18*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x14, x17, x3, x0, dyn, 0, 0, x10, 18*FLEN/8, x15, x1, x7) + +inst_19: +// rs1==x5, rs2==x23, rs3==x10, rd==x30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x5; op2:x23; op3:x10; dest:x30; op1val:0x0; op2val:0x0; +op3val:0xfe55; valaddr_reg:x10; val_offset:21*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x30, x5, x23, x10, dyn, 0, 0, x10, 21*FLEN/8, x15, x1, x7) + +inst_20: +// rs1==x30, rs2==x28, rs3==x13, rd==x17,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x28; op3:x13; dest:x17; op1val:0x0; op2val:0x0; +op3val:0x7c01; valaddr_reg:x10; val_offset:24*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x17, x30, x28, x13, dyn, 0, 0, x10, 24*FLEN/8, x15, x1, x7) + +inst_21: +// rs1==x20, rs2==x22, rs3==x8, rd==x29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x20; op2:x22; op3:x8; dest:x29; op1val:0x0; op2val:0x0; +op3val:0xfd55; valaddr_reg:x10; val_offset:27*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x29, x20, x22, x8, dyn, 0, 0, x10, 27*FLEN/8, x15, x1, x7) + +inst_22: +// rs1==x29, rs2==x4, rs3==x12, rd==x8,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x29; op2:x4; op3:x12; dest:x8; op1val:0x0; op2val:0x0; +op3val:0x3c00; valaddr_reg:x10; val_offset:30*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x8, x29, x4, x12, dyn, 0, 0, x10, 30*FLEN/8, x15, x1, x7) + +inst_23: +// rs1==x31, rs2==x0, rs3==x30, rd==x12,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x31; op2:x0; op3:x30; dest:x12; op1val:0x0; op2val:0x0; +op3val:0xbc00; valaddr_reg:x10; val_offset:33*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x12, x31, x0, x30, dyn, 0, 0, x10, 33*FLEN/8, x15, x1, x7) +RVTEST_VALBASEUPD(x5,test_dataset_2) + +inst_24: +// rs1==x11, rs2==x25, rs3==x24, rd==x28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x11; op2:x25; op3:x24; dest:x28; op1val:0x0; op2val:0x8000; +op3val:0x0; valaddr_reg:x5; val_offset:0*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x28, x11, x25, x24, dyn, 0, 0, x5, 0*FLEN/8, x9, x1, x7) + +inst_25: +// rs1==x24, rs2==x31, rs3==x14, rd==x4,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x24; op2:x31; op3:x14; dest:x4; op1val:0x0; op2val:0x8000; +op3val:0x8000; valaddr_reg:x5; val_offset:3*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x4, x24, x31, x14, dyn, 0, 0, x5, 3*FLEN/8, x9, x1, x7) + +inst_26: +// rs1==x2, rs2==x26, rs3==x11, rd==x10,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x2; op2:x26; op3:x11; dest:x10; op1val:0x0; op2val:0x8000; +op3val:0x1; valaddr_reg:x5; val_offset:6*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x10, x2, x26, x11, dyn, 0, 0, x5, 6*FLEN/8, x9, x1, x7) + +inst_27: +// rs1==x3, rs2==x19, rs3==x6, rd==x15,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x3; op2:x19; op3:x6; dest:x15; op1val:0x0; op2val:0x8000; +op3val:0x8001; valaddr_reg:x5; val_offset:9*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x15, x3, x19, x6, dyn, 0, 0, x5, 9*FLEN/8, x9, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_28: +// rs1==x12, rs2==x30, rs3==x22, rd==x0,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x12; op2:x30; op3:x22; dest:x0; op1val:0x0; op2val:0x8000; +op3val:0x2; valaddr_reg:x5; val_offset:12*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x0, x12, x30, x22, dyn, 0, 0, x5, 12*FLEN/8, x9, x1, x4) + +inst_29: +// rs1==x6, rs2==x20, rs3==x21, rd==x2,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x6; op2:x20; op3:x21; dest:x2; op1val:0x0; op2val:0x8000; +op3val:0x83fe; valaddr_reg:x5; val_offset:15*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x2, x6, x20, x21, dyn, 0, 0, x5, 15*FLEN/8, x9, x1, x4) + +inst_30: +// rs1==x19, rs2==x18, rs3==x5, rd==x6,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x19; op2:x18; op3:x5; dest:x6; op1val:0x0; op2val:0x8000; +op3val:0x3ff; valaddr_reg:x5; val_offset:18*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x6, x19, x18, x5, dyn, 0, 0, x5, 18*FLEN/8, x9, x1, x4) + +inst_31: +// rs1==x16,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x16; op2:x8; op3:x17; dest:x29; op1val:0x0; op2val:0x8000; +op3val:0x83ff; valaddr_reg:x5; val_offset:21*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x29, x16, x8, x17, dyn, 0, 0, x5, 21*FLEN/8, x9, x1, x4) + +inst_32: +// rs2==x11,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x27; op2:x11; op3:x28; dest:x2; op1val:0x0; op2val:0x8000; +op3val:0x400; valaddr_reg:x5; val_offset:24*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x2, x27, x11, x28, dyn, 0, 0, x5, 24*FLEN/8, x9, x1, x4) + +inst_33: +// rs3==x18,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x31; op2:x0; op3:x18; dest:x23; op1val:0x0; op2val:0x0; +op3val:0x8400; valaddr_reg:x5; val_offset:27*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x23, x31, x0, x18, dyn, 0, 0, x5, 27*FLEN/8, x9, x1, x4) +RVTEST_VALBASEUPD(x2,test_dataset_3) + +inst_34: +// rd==x16,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x10; op2:x23; op3:x27; dest:x16; op1val:0x0; op2val:0x8000; +op3val:0x401; valaddr_reg:x2; val_offset:0*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x16, x10, x23, x27, dyn, 0, 0, x2, 0*FLEN/8, x3, x1, x4) + +inst_35: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8000; +op3val:0x8455; valaddr_reg:x2; val_offset:3*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3*FLEN/8, x3, x1, x4) + +inst_36: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x2; val_offset:6*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6*FLEN/8, x3, x1, x4) + +inst_37: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x2; val_offset:9*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9*FLEN/8, x3, x1, x4) + +inst_38: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8000; +op3val:0x7c00; valaddr_reg:x2; val_offset:12*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12*FLEN/8, x3, x1, x4) + +inst_39: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8000; +op3val:0xfc00; valaddr_reg:x2; val_offset:15*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15*FLEN/8, x3, x1, x4) + +inst_40: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8000; +op3val:0x7e00; valaddr_reg:x2; val_offset:18*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18*FLEN/8, x3, x1, x4) + +inst_41: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8000; +op3val:0xfe00; valaddr_reg:x2; val_offset:21*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21*FLEN/8, x3, x1, x4) + +inst_42: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8000; +op3val:0x7e01; valaddr_reg:x2; val_offset:24*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24*FLEN/8, x3, x1, x4) + +inst_43: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8000; +op3val:0xfe55; valaddr_reg:x2; val_offset:27*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27*FLEN/8, x3, x1, x4) + +inst_44: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8000; +op3val:0x7c01; valaddr_reg:x2; val_offset:30*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30*FLEN/8, x3, x1, x4) + +inst_45: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8000; +op3val:0xfd55; valaddr_reg:x2; val_offset:33*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33*FLEN/8, x3, x1, x4) + +inst_46: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8000; +op3val:0x3c00; valaddr_reg:x2; val_offset:36*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36*FLEN/8, x3, x1, x4) + +inst_47: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8000; +op3val:0xbc00; valaddr_reg:x2; val_offset:39*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39*FLEN/8, x3, x1, x4) + +inst_48: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x1; +op3val:0x0; valaddr_reg:x2; val_offset:42*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 42*FLEN/8, x3, x1, x4) + +inst_49: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x1; +op3val:0x8000; valaddr_reg:x2; val_offset:45*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 45*FLEN/8, x3, x1, x4) + +inst_50: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x1; +op3val:0x1; valaddr_reg:x2; val_offset:48*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 48*FLEN/8, x3, x1, x4) + +inst_51: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x1; +op3val:0x8001; valaddr_reg:x2; val_offset:51*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 51*FLEN/8, x3, x1, x4) + +inst_52: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x1; +op3val:0x2; valaddr_reg:x2; val_offset:54*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 54*FLEN/8, x3, x1, x4) + +inst_53: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x1; +op3val:0x83fe; valaddr_reg:x2; val_offset:57*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 57*FLEN/8, x3, x1, x4) + +inst_54: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x1; +op3val:0x3ff; valaddr_reg:x2; val_offset:60*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 60*FLEN/8, x3, x1, x4) + +inst_55: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x1; +op3val:0x83ff; valaddr_reg:x2; val_offset:63*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 63*FLEN/8, x3, x1, x4) + +inst_56: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x1; +op3val:0x400; valaddr_reg:x2; val_offset:66*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 66*FLEN/8, x3, x1, x4) + +inst_57: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x1; +op3val:0x8400; valaddr_reg:x2; val_offset:69*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 69*FLEN/8, x3, x1, x4) + +inst_58: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x1; +op3val:0x401; valaddr_reg:x2; val_offset:72*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 72*FLEN/8, x3, x1, x4) + +inst_59: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x1; +op3val:0x8455; valaddr_reg:x2; val_offset:75*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 75*FLEN/8, x3, x1, x4) + +inst_60: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x1; +op3val:0x7bff; valaddr_reg:x2; val_offset:78*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 78*FLEN/8, x3, x1, x4) + +inst_61: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x1; +op3val:0xfbff; valaddr_reg:x2; val_offset:81*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 81*FLEN/8, x3, x1, x4) + +inst_62: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x1; +op3val:0x7c00; valaddr_reg:x2; val_offset:84*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 84*FLEN/8, x3, x1, x4) + +inst_63: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x1; +op3val:0xfc00; valaddr_reg:x2; val_offset:87*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 87*FLEN/8, x3, x1, x4) + +inst_64: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x1; +op3val:0x7e00; valaddr_reg:x2; val_offset:90*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 90*FLEN/8, x3, x1, x4) + +inst_65: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x1; +op3val:0xfe00; valaddr_reg:x2; val_offset:93*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 93*FLEN/8, x3, x1, x4) + +inst_66: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x1; +op3val:0x7e01; valaddr_reg:x2; val_offset:96*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 96*FLEN/8, x3, x1, x4) + +inst_67: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x1; +op3val:0xfe55; valaddr_reg:x2; val_offset:99*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 99*FLEN/8, x3, x1, x4) + +inst_68: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x1; +op3val:0x7c01; valaddr_reg:x2; val_offset:102*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 102*FLEN/8, x3, x1, x4) + +inst_69: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x1; +op3val:0xfd55; valaddr_reg:x2; val_offset:105*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 105*FLEN/8, x3, x1, x4) + +inst_70: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x1; +op3val:0x3c00; valaddr_reg:x2; val_offset:108*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 108*FLEN/8, x3, x1, x4) + +inst_71: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x1; +op3val:0xbc00; valaddr_reg:x2; val_offset:111*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 111*FLEN/8, x3, x1, x4) + +inst_72: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8001; +op3val:0x0; valaddr_reg:x2; val_offset:114*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 114*FLEN/8, x3, x1, x4) + +inst_73: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8001; +op3val:0x8000; valaddr_reg:x2; val_offset:117*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 117*FLEN/8, x3, x1, x4) + +inst_74: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8001; +op3val:0x1; valaddr_reg:x2; val_offset:120*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 120*FLEN/8, x3, x1, x4) + +inst_75: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8001; +op3val:0x8001; valaddr_reg:x2; val_offset:123*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 123*FLEN/8, x3, x1, x4) + +inst_76: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8001; +op3val:0x2; valaddr_reg:x2; val_offset:126*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 126*FLEN/8, x3, x1, x4) + +inst_77: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8001; +op3val:0x83fe; valaddr_reg:x2; val_offset:129*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 129*FLEN/8, x3, x1, x4) + +inst_78: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8001; +op3val:0x3ff; valaddr_reg:x2; val_offset:132*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 132*FLEN/8, x3, x1, x4) + +inst_79: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8001; +op3val:0x83ff; valaddr_reg:x2; val_offset:135*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 135*FLEN/8, x3, x1, x4) + +inst_80: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8001; +op3val:0x400; valaddr_reg:x2; val_offset:138*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 138*FLEN/8, x3, x1, x4) + +inst_81: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8001; +op3val:0x8400; valaddr_reg:x2; val_offset:141*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 141*FLEN/8, x3, x1, x4) + +inst_82: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8001; +op3val:0x401; valaddr_reg:x2; val_offset:144*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 144*FLEN/8, x3, x1, x4) + +inst_83: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8001; +op3val:0x8455; valaddr_reg:x2; val_offset:147*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 147*FLEN/8, x3, x1, x4) + +inst_84: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8001; +op3val:0x7bff; valaddr_reg:x2; val_offset:150*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 150*FLEN/8, x3, x1, x4) + +inst_85: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8001; +op3val:0xfbff; valaddr_reg:x2; val_offset:153*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 153*FLEN/8, x3, x1, x4) + +inst_86: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8001; +op3val:0x7c00; valaddr_reg:x2; val_offset:156*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 156*FLEN/8, x3, x1, x4) + +inst_87: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8001; +op3val:0xfc00; valaddr_reg:x2; val_offset:159*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 159*FLEN/8, x3, x1, x4) + +inst_88: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8001; +op3val:0x7e00; valaddr_reg:x2; val_offset:162*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 162*FLEN/8, x3, x1, x4) + +inst_89: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8001; +op3val:0xfe00; valaddr_reg:x2; val_offset:165*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 165*FLEN/8, x3, x1, x4) + +inst_90: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8001; +op3val:0x7e01; valaddr_reg:x2; val_offset:168*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 168*FLEN/8, x3, x1, x4) + +inst_91: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8001; +op3val:0xfe55; valaddr_reg:x2; val_offset:171*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 171*FLEN/8, x3, x1, x4) + +inst_92: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8001; +op3val:0x7c01; valaddr_reg:x2; val_offset:174*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 174*FLEN/8, x3, x1, x4) + +inst_93: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8001; +op3val:0xfd55; valaddr_reg:x2; val_offset:177*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 177*FLEN/8, x3, x1, x4) + +inst_94: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8001; +op3val:0x3c00; valaddr_reg:x2; val_offset:180*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 180*FLEN/8, x3, x1, x4) + +inst_95: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8001; +op3val:0xbc00; valaddr_reg:x2; val_offset:183*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 183*FLEN/8, x3, x1, x4) + +inst_96: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x2; +op3val:0x0; valaddr_reg:x2; val_offset:186*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 186*FLEN/8, x3, x1, x4) + +inst_97: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x2; +op3val:0x8000; valaddr_reg:x2; val_offset:189*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 189*FLEN/8, x3, x1, x4) + +inst_98: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x2; +op3val:0x1; valaddr_reg:x2; val_offset:192*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 192*FLEN/8, x3, x1, x4) + +inst_99: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x2; +op3val:0x8001; valaddr_reg:x2; val_offset:195*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 195*FLEN/8, x3, x1, x4) + +inst_100: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x2; +op3val:0x2; valaddr_reg:x2; val_offset:198*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 198*FLEN/8, x3, x1, x4) + +inst_101: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x2; +op3val:0x83fe; valaddr_reg:x2; val_offset:201*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 201*FLEN/8, x3, x1, x4) + +inst_102: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x2; +op3val:0x3ff; valaddr_reg:x2; val_offset:204*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 204*FLEN/8, x3, x1, x4) + +inst_103: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x2; +op3val:0x83ff; valaddr_reg:x2; val_offset:207*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 207*FLEN/8, x3, x1, x4) + +inst_104: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x2; +op3val:0x400; valaddr_reg:x2; val_offset:210*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 210*FLEN/8, x3, x1, x4) + +inst_105: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x2; +op3val:0x8400; valaddr_reg:x2; val_offset:213*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 213*FLEN/8, x3, x1, x4) + +inst_106: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x2; +op3val:0x401; valaddr_reg:x2; val_offset:216*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 216*FLEN/8, x3, x1, x4) + +inst_107: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x2; +op3val:0x8455; valaddr_reg:x2; val_offset:219*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 219*FLEN/8, x3, x1, x4) + +inst_108: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x2; +op3val:0x7bff; valaddr_reg:x2; val_offset:222*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 222*FLEN/8, x3, x1, x4) + +inst_109: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x2; +op3val:0xfbff; valaddr_reg:x2; val_offset:225*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 225*FLEN/8, x3, x1, x4) + +inst_110: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x2; +op3val:0x7c00; valaddr_reg:x2; val_offset:228*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 228*FLEN/8, x3, x1, x4) + +inst_111: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x2; +op3val:0xfc00; valaddr_reg:x2; val_offset:231*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 231*FLEN/8, x3, x1, x4) + +inst_112: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x2; +op3val:0x7e00; valaddr_reg:x2; val_offset:234*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 234*FLEN/8, x3, x1, x4) + +inst_113: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x2; +op3val:0xfe00; valaddr_reg:x2; val_offset:237*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 237*FLEN/8, x3, x1, x4) + +inst_114: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x2; +op3val:0x7e01; valaddr_reg:x2; val_offset:240*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 240*FLEN/8, x3, x1, x4) + +inst_115: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x2; +op3val:0xfe55; valaddr_reg:x2; val_offset:243*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 243*FLEN/8, x3, x1, x4) + +inst_116: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x2; +op3val:0x7c01; valaddr_reg:x2; val_offset:246*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 246*FLEN/8, x3, x1, x4) + +inst_117: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x2; +op3val:0xfd55; valaddr_reg:x2; val_offset:249*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 249*FLEN/8, x3, x1, x4) + +inst_118: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x2; +op3val:0x3c00; valaddr_reg:x2; val_offset:252*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 252*FLEN/8, x3, x1, x4) + +inst_119: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x2; +op3val:0xbc00; valaddr_reg:x2; val_offset:255*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 255*FLEN/8, x3, x1, x4) + +inst_120: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x83fe; +op3val:0x0; valaddr_reg:x2; val_offset:258*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 258*FLEN/8, x3, x1, x4) + +inst_121: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x83fe; +op3val:0x8000; valaddr_reg:x2; val_offset:261*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 261*FLEN/8, x3, x1, x4) + +inst_122: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x83fe; +op3val:0x1; valaddr_reg:x2; val_offset:264*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 264*FLEN/8, x3, x1, x4) + +inst_123: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x83fe; +op3val:0x8001; valaddr_reg:x2; val_offset:267*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 267*FLEN/8, x3, x1, x4) + +inst_124: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x83fe; +op3val:0x2; valaddr_reg:x2; val_offset:270*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 270*FLEN/8, x3, x1, x4) + +inst_125: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x83fe; +op3val:0x83fe; valaddr_reg:x2; val_offset:273*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 273*FLEN/8, x3, x1, x4) + +inst_126: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x83fe; +op3val:0x3ff; valaddr_reg:x2; val_offset:276*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 276*FLEN/8, x3, x1, x4) + +inst_127: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x83fe; +op3val:0x83ff; valaddr_reg:x2; val_offset:279*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 279*FLEN/8, x3, x1, x4) + +inst_128: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x83fe; +op3val:0x400; valaddr_reg:x2; val_offset:282*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 282*FLEN/8, x3, x1, x4) + +inst_129: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x83fe; +op3val:0x8400; valaddr_reg:x2; val_offset:285*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 285*FLEN/8, x3, x1, x4) + +inst_130: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x83fe; +op3val:0x401; valaddr_reg:x2; val_offset:288*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 288*FLEN/8, x3, x1, x4) + +inst_131: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x83fe; +op3val:0x8455; valaddr_reg:x2; val_offset:291*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 291*FLEN/8, x3, x1, x4) + +inst_132: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x83fe; +op3val:0x7bff; valaddr_reg:x2; val_offset:294*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 294*FLEN/8, x3, x1, x4) + +inst_133: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x83fe; +op3val:0xfbff; valaddr_reg:x2; val_offset:297*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 297*FLEN/8, x3, x1, x4) + +inst_134: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x83fe; +op3val:0x7c00; valaddr_reg:x2; val_offset:300*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 300*FLEN/8, x3, x1, x4) + +inst_135: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x83fe; +op3val:0xfc00; valaddr_reg:x2; val_offset:303*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 303*FLEN/8, x3, x1, x4) + +inst_136: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x83fe; +op3val:0x7e00; valaddr_reg:x2; val_offset:306*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 306*FLEN/8, x3, x1, x4) + +inst_137: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x83fe; +op3val:0xfe00; valaddr_reg:x2; val_offset:309*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 309*FLEN/8, x3, x1, x4) + +inst_138: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x83fe; +op3val:0x7e01; valaddr_reg:x2; val_offset:312*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 312*FLEN/8, x3, x1, x4) + +inst_139: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x83fe; +op3val:0xfe55; valaddr_reg:x2; val_offset:315*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 315*FLEN/8, x3, x1, x4) + +inst_140: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x83fe; +op3val:0x7c01; valaddr_reg:x2; val_offset:318*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 318*FLEN/8, x3, x1, x4) + +inst_141: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x83fe; +op3val:0xfd55; valaddr_reg:x2; val_offset:321*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 321*FLEN/8, x3, x1, x4) + +inst_142: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x83fe; +op3val:0x3c00; valaddr_reg:x2; val_offset:324*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 324*FLEN/8, x3, x1, x4) + +inst_143: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x83fe; +op3val:0xbc00; valaddr_reg:x2; val_offset:327*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 327*FLEN/8, x3, x1, x4) + +inst_144: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3ff; +op3val:0x0; valaddr_reg:x2; val_offset:330*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 330*FLEN/8, x3, x1, x4) + +inst_145: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3ff; +op3val:0x8000; valaddr_reg:x2; val_offset:333*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 333*FLEN/8, x3, x1, x4) + +inst_146: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3ff; +op3val:0x1; valaddr_reg:x2; val_offset:336*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 336*FLEN/8, x3, x1, x4) + +inst_147: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3ff; +op3val:0x8001; valaddr_reg:x2; val_offset:339*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 339*FLEN/8, x3, x1, x4) + +inst_148: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3ff; +op3val:0x2; valaddr_reg:x2; val_offset:342*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 342*FLEN/8, x3, x1, x4) + +inst_149: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3ff; +op3val:0x83fe; valaddr_reg:x2; val_offset:345*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 345*FLEN/8, x3, x1, x4) + +inst_150: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3ff; +op3val:0x3ff; valaddr_reg:x2; val_offset:348*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 348*FLEN/8, x3, x1, x4) + +inst_151: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3ff; +op3val:0x83ff; valaddr_reg:x2; val_offset:351*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 351*FLEN/8, x3, x1, x4) + +inst_152: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3ff; +op3val:0x400; valaddr_reg:x2; val_offset:354*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 354*FLEN/8, x3, x1, x4) + +inst_153: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3ff; +op3val:0x8400; valaddr_reg:x2; val_offset:357*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 357*FLEN/8, x3, x1, x4) + +inst_154: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3ff; +op3val:0x401; valaddr_reg:x2; val_offset:360*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 360*FLEN/8, x3, x1, x4) + +inst_155: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3ff; +op3val:0x8455; valaddr_reg:x2; val_offset:363*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 363*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_2) + +inst_156: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3ff; +op3val:0x7bff; valaddr_reg:x2; val_offset:366*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 366*FLEN/8, x3, x1, x4) + +inst_157: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3ff; +op3val:0xfbff; valaddr_reg:x2; val_offset:369*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 369*FLEN/8, x3, x1, x4) + +inst_158: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3ff; +op3val:0x7c00; valaddr_reg:x2; val_offset:372*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 372*FLEN/8, x3, x1, x4) + +inst_159: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3ff; +op3val:0xfc00; valaddr_reg:x2; val_offset:375*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 375*FLEN/8, x3, x1, x4) + +inst_160: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3ff; +op3val:0x7e00; valaddr_reg:x2; val_offset:378*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 378*FLEN/8, x3, x1, x4) + +inst_161: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3ff; +op3val:0xfe00; valaddr_reg:x2; val_offset:381*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 381*FLEN/8, x3, x1, x4) + +inst_162: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3ff; +op3val:0x7e01; valaddr_reg:x2; val_offset:384*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 384*FLEN/8, x3, x1, x4) + +inst_163: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3ff; +op3val:0xfe55; valaddr_reg:x2; val_offset:387*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 387*FLEN/8, x3, x1, x4) + +inst_164: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3ff; +op3val:0x7c01; valaddr_reg:x2; val_offset:390*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 390*FLEN/8, x3, x1, x4) + +inst_165: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3ff; +op3val:0xfd55; valaddr_reg:x2; val_offset:393*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 393*FLEN/8, x3, x1, x4) + +inst_166: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3ff; +op3val:0x3c00; valaddr_reg:x2; val_offset:396*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 396*FLEN/8, x3, x1, x4) + +inst_167: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3ff; +op3val:0xbc00; valaddr_reg:x2; val_offset:399*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 399*FLEN/8, x3, x1, x4) + +inst_168: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x83ff; +op3val:0x0; valaddr_reg:x2; val_offset:402*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 402*FLEN/8, x3, x1, x4) + +inst_169: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x83ff; +op3val:0x8000; valaddr_reg:x2; val_offset:405*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 405*FLEN/8, x3, x1, x4) + +inst_170: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x83ff; +op3val:0x1; valaddr_reg:x2; val_offset:408*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 408*FLEN/8, x3, x1, x4) + +inst_171: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x83ff; +op3val:0x8001; valaddr_reg:x2; val_offset:411*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 411*FLEN/8, x3, x1, x4) + +inst_172: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x83ff; +op3val:0x2; valaddr_reg:x2; val_offset:414*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 414*FLEN/8, x3, x1, x4) + +inst_173: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x83ff; +op3val:0x83fe; valaddr_reg:x2; val_offset:417*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 417*FLEN/8, x3, x1, x4) + +inst_174: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x83ff; +op3val:0x3ff; valaddr_reg:x2; val_offset:420*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 420*FLEN/8, x3, x1, x4) + +inst_175: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x83ff; +op3val:0x83ff; valaddr_reg:x2; val_offset:423*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 423*FLEN/8, x3, x1, x4) + +inst_176: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x83ff; +op3val:0x400; valaddr_reg:x2; val_offset:426*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 426*FLEN/8, x3, x1, x4) + +inst_177: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x83ff; +op3val:0x8400; valaddr_reg:x2; val_offset:429*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 429*FLEN/8, x3, x1, x4) + +inst_178: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x83ff; +op3val:0x401; valaddr_reg:x2; val_offset:432*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 432*FLEN/8, x3, x1, x4) + +inst_179: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x83ff; +op3val:0x8455; valaddr_reg:x2; val_offset:435*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 435*FLEN/8, x3, x1, x4) + +inst_180: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x83ff; +op3val:0x7bff; valaddr_reg:x2; val_offset:438*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 438*FLEN/8, x3, x1, x4) + +inst_181: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x83ff; +op3val:0xfbff; valaddr_reg:x2; val_offset:441*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 441*FLEN/8, x3, x1, x4) + +inst_182: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x83ff; +op3val:0x7c00; valaddr_reg:x2; val_offset:444*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 444*FLEN/8, x3, x1, x4) + +inst_183: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x83ff; +op3val:0xfc00; valaddr_reg:x2; val_offset:447*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 447*FLEN/8, x3, x1, x4) + +inst_184: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x83ff; +op3val:0x7e00; valaddr_reg:x2; val_offset:450*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 450*FLEN/8, x3, x1, x4) + +inst_185: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x83ff; +op3val:0xfe00; valaddr_reg:x2; val_offset:453*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 453*FLEN/8, x3, x1, x4) + +inst_186: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x83ff; +op3val:0x7e01; valaddr_reg:x2; val_offset:456*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 456*FLEN/8, x3, x1, x4) + +inst_187: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x83ff; +op3val:0xfe55; valaddr_reg:x2; val_offset:459*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 459*FLEN/8, x3, x1, x4) + +inst_188: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x83ff; +op3val:0x7c01; valaddr_reg:x2; val_offset:462*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 462*FLEN/8, x3, x1, x4) + +inst_189: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x83ff; +op3val:0xfd55; valaddr_reg:x2; val_offset:465*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 465*FLEN/8, x3, x1, x4) + +inst_190: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x83ff; +op3val:0x3c00; valaddr_reg:x2; val_offset:468*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 468*FLEN/8, x3, x1, x4) + +inst_191: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x83ff; +op3val:0xbc00; valaddr_reg:x2; val_offset:471*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 471*FLEN/8, x3, x1, x4) + +inst_192: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x400; +op3val:0x0; valaddr_reg:x2; val_offset:474*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 474*FLEN/8, x3, x1, x4) + +inst_193: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x400; +op3val:0x8000; valaddr_reg:x2; val_offset:477*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 477*FLEN/8, x3, x1, x4) + +inst_194: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x400; +op3val:0x1; valaddr_reg:x2; val_offset:480*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 480*FLEN/8, x3, x1, x4) + +inst_195: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x400; +op3val:0x8001; valaddr_reg:x2; val_offset:483*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 483*FLEN/8, x3, x1, x4) + +inst_196: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x400; +op3val:0x2; valaddr_reg:x2; val_offset:486*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 486*FLEN/8, x3, x1, x4) + +inst_197: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x400; +op3val:0x83fe; valaddr_reg:x2; val_offset:489*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 489*FLEN/8, x3, x1, x4) + +inst_198: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x400; +op3val:0x3ff; valaddr_reg:x2; val_offset:492*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 492*FLEN/8, x3, x1, x4) + +inst_199: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x400; +op3val:0x83ff; valaddr_reg:x2; val_offset:495*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 495*FLEN/8, x3, x1, x4) + +inst_200: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x400; +op3val:0x400; valaddr_reg:x2; val_offset:498*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 498*FLEN/8, x3, x1, x4) + +inst_201: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x400; +op3val:0x8400; valaddr_reg:x2; val_offset:501*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 501*FLEN/8, x3, x1, x4) + +inst_202: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x400; +op3val:0x401; valaddr_reg:x2; val_offset:504*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 504*FLEN/8, x3, x1, x4) + +inst_203: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x400; +op3val:0x8455; valaddr_reg:x2; val_offset:507*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 507*FLEN/8, x3, x1, x4) + +inst_204: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x400; +op3val:0x7bff; valaddr_reg:x2; val_offset:510*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 510*FLEN/8, x3, x1, x4) + +inst_205: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x400; +op3val:0xfbff; valaddr_reg:x2; val_offset:513*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 513*FLEN/8, x3, x1, x4) + +inst_206: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x400; +op3val:0x7c00; valaddr_reg:x2; val_offset:516*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 516*FLEN/8, x3, x1, x4) + +inst_207: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x400; +op3val:0xfc00; valaddr_reg:x2; val_offset:519*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 519*FLEN/8, x3, x1, x4) + +inst_208: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x400; +op3val:0x7e00; valaddr_reg:x2; val_offset:522*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 522*FLEN/8, x3, x1, x4) + +inst_209: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x400; +op3val:0xfe00; valaddr_reg:x2; val_offset:525*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 525*FLEN/8, x3, x1, x4) + +inst_210: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x400; +op3val:0x7e01; valaddr_reg:x2; val_offset:528*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 528*FLEN/8, x3, x1, x4) + +inst_211: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x400; +op3val:0xfe55; valaddr_reg:x2; val_offset:531*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 531*FLEN/8, x3, x1, x4) + +inst_212: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x400; +op3val:0x7c01; valaddr_reg:x2; val_offset:534*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 534*FLEN/8, x3, x1, x4) + +inst_213: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x400; +op3val:0xfd55; valaddr_reg:x2; val_offset:537*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 537*FLEN/8, x3, x1, x4) + +inst_214: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x400; +op3val:0x3c00; valaddr_reg:x2; val_offset:540*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 540*FLEN/8, x3, x1, x4) + +inst_215: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x400; +op3val:0xbc00; valaddr_reg:x2; val_offset:543*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 543*FLEN/8, x3, x1, x4) + +inst_216: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8400; +op3val:0x0; valaddr_reg:x2; val_offset:546*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 546*FLEN/8, x3, x1, x4) + +inst_217: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8400; +op3val:0x8000; valaddr_reg:x2; val_offset:549*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 549*FLEN/8, x3, x1, x4) + +inst_218: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8400; +op3val:0x1; valaddr_reg:x2; val_offset:552*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 552*FLEN/8, x3, x1, x4) + +inst_219: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8400; +op3val:0x8001; valaddr_reg:x2; val_offset:555*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 555*FLEN/8, x3, x1, x4) + +inst_220: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8400; +op3val:0x2; valaddr_reg:x2; val_offset:558*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 558*FLEN/8, x3, x1, x4) + +inst_221: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8400; +op3val:0x83fe; valaddr_reg:x2; val_offset:561*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 561*FLEN/8, x3, x1, x4) + +inst_222: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8400; +op3val:0x3ff; valaddr_reg:x2; val_offset:564*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 564*FLEN/8, x3, x1, x4) + +inst_223: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8400; +op3val:0x83ff; valaddr_reg:x2; val_offset:567*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 567*FLEN/8, x3, x1, x4) + +inst_224: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8400; +op3val:0x400; valaddr_reg:x2; val_offset:570*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 570*FLEN/8, x3, x1, x4) + +inst_225: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8400; +op3val:0x8400; valaddr_reg:x2; val_offset:573*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 573*FLEN/8, x3, x1, x4) + +inst_226: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8400; +op3val:0x401; valaddr_reg:x2; val_offset:576*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 576*FLEN/8, x3, x1, x4) + +inst_227: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8400; +op3val:0x8455; valaddr_reg:x2; val_offset:579*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 579*FLEN/8, x3, x1, x4) + +inst_228: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8400; +op3val:0x7bff; valaddr_reg:x2; val_offset:582*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 582*FLEN/8, x3, x1, x4) + +inst_229: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8400; +op3val:0xfbff; valaddr_reg:x2; val_offset:585*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 585*FLEN/8, x3, x1, x4) + +inst_230: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8400; +op3val:0x7c00; valaddr_reg:x2; val_offset:588*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 588*FLEN/8, x3, x1, x4) + +inst_231: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8400; +op3val:0xfc00; valaddr_reg:x2; val_offset:591*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 591*FLEN/8, x3, x1, x4) + +inst_232: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8400; +op3val:0x7e00; valaddr_reg:x2; val_offset:594*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 594*FLEN/8, x3, x1, x4) + +inst_233: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8400; +op3val:0xfe00; valaddr_reg:x2; val_offset:597*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 597*FLEN/8, x3, x1, x4) + +inst_234: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8400; +op3val:0x7e01; valaddr_reg:x2; val_offset:600*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 600*FLEN/8, x3, x1, x4) + +inst_235: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8400; +op3val:0xfe55; valaddr_reg:x2; val_offset:603*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 603*FLEN/8, x3, x1, x4) + +inst_236: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8400; +op3val:0x7c01; valaddr_reg:x2; val_offset:606*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 606*FLEN/8, x3, x1, x4) + +inst_237: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8400; +op3val:0xfd55; valaddr_reg:x2; val_offset:609*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 609*FLEN/8, x3, x1, x4) + +inst_238: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8400; +op3val:0x3c00; valaddr_reg:x2; val_offset:612*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 612*FLEN/8, x3, x1, x4) + +inst_239: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8400; +op3val:0xbc00; valaddr_reg:x2; val_offset:615*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 615*FLEN/8, x3, x1, x4) + +inst_240: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x401; +op3val:0x0; valaddr_reg:x2; val_offset:618*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 618*FLEN/8, x3, x1, x4) + +inst_241: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x401; +op3val:0x8000; valaddr_reg:x2; val_offset:621*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 621*FLEN/8, x3, x1, x4) + +inst_242: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x401; +op3val:0x1; valaddr_reg:x2; val_offset:624*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 624*FLEN/8, x3, x1, x4) + +inst_243: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x401; +op3val:0x8001; valaddr_reg:x2; val_offset:627*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 627*FLEN/8, x3, x1, x4) + +inst_244: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x401; +op3val:0x2; valaddr_reg:x2; val_offset:630*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 630*FLEN/8, x3, x1, x4) + +inst_245: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x401; +op3val:0x83fe; valaddr_reg:x2; val_offset:633*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 633*FLEN/8, x3, x1, x4) + +inst_246: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x401; +op3val:0x3ff; valaddr_reg:x2; val_offset:636*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 636*FLEN/8, x3, x1, x4) + +inst_247: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x401; +op3val:0x83ff; valaddr_reg:x2; val_offset:639*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 639*FLEN/8, x3, x1, x4) + +inst_248: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x401; +op3val:0x400; valaddr_reg:x2; val_offset:642*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 642*FLEN/8, x3, x1, x4) + +inst_249: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x401; +op3val:0x8400; valaddr_reg:x2; val_offset:645*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 645*FLEN/8, x3, x1, x4) + +inst_250: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x401; +op3val:0x401; valaddr_reg:x2; val_offset:648*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 648*FLEN/8, x3, x1, x4) + +inst_251: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x401; +op3val:0x8455; valaddr_reg:x2; val_offset:651*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 651*FLEN/8, x3, x1, x4) + +inst_252: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x401; +op3val:0x7bff; valaddr_reg:x2; val_offset:654*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 654*FLEN/8, x3, x1, x4) + +inst_253: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x401; +op3val:0xfbff; valaddr_reg:x2; val_offset:657*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 657*FLEN/8, x3, x1, x4) + +inst_254: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x401; +op3val:0x7c00; valaddr_reg:x2; val_offset:660*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 660*FLEN/8, x3, x1, x4) + +inst_255: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x401; +op3val:0xfc00; valaddr_reg:x2; val_offset:663*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 663*FLEN/8, x3, x1, x4) + +inst_256: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x401; +op3val:0x7e00; valaddr_reg:x2; val_offset:666*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 666*FLEN/8, x3, x1, x4) + +inst_257: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x401; +op3val:0xfe00; valaddr_reg:x2; val_offset:669*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 669*FLEN/8, x3, x1, x4) + +inst_258: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x401; +op3val:0x7e01; valaddr_reg:x2; val_offset:672*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 672*FLEN/8, x3, x1, x4) + +inst_259: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x401; +op3val:0xfe55; valaddr_reg:x2; val_offset:675*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 675*FLEN/8, x3, x1, x4) + +inst_260: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x401; +op3val:0x7c01; valaddr_reg:x2; val_offset:678*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 678*FLEN/8, x3, x1, x4) + +inst_261: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x401; +op3val:0xfd55; valaddr_reg:x2; val_offset:681*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 681*FLEN/8, x3, x1, x4) + +inst_262: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x401; +op3val:0x3c00; valaddr_reg:x2; val_offset:684*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 684*FLEN/8, x3, x1, x4) + +inst_263: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x401; +op3val:0xbc00; valaddr_reg:x2; val_offset:687*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 687*FLEN/8, x3, x1, x4) + +inst_264: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8455; +op3val:0x0; valaddr_reg:x2; val_offset:690*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 690*FLEN/8, x3, x1, x4) + +inst_265: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8455; +op3val:0x8000; valaddr_reg:x2; val_offset:693*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 693*FLEN/8, x3, x1, x4) + +inst_266: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8455; +op3val:0x1; valaddr_reg:x2; val_offset:696*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 696*FLEN/8, x3, x1, x4) + +inst_267: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8455; +op3val:0x8001; valaddr_reg:x2; val_offset:699*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 699*FLEN/8, x3, x1, x4) + +inst_268: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8455; +op3val:0x2; valaddr_reg:x2; val_offset:702*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 702*FLEN/8, x3, x1, x4) + +inst_269: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8455; +op3val:0x83fe; valaddr_reg:x2; val_offset:705*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 705*FLEN/8, x3, x1, x4) + +inst_270: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8455; +op3val:0x3ff; valaddr_reg:x2; val_offset:708*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 708*FLEN/8, x3, x1, x4) + +inst_271: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8455; +op3val:0x83ff; valaddr_reg:x2; val_offset:711*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 711*FLEN/8, x3, x1, x4) + +inst_272: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8455; +op3val:0x400; valaddr_reg:x2; val_offset:714*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 714*FLEN/8, x3, x1, x4) + +inst_273: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8455; +op3val:0x8400; valaddr_reg:x2; val_offset:717*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 717*FLEN/8, x3, x1, x4) + +inst_274: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8455; +op3val:0x401; valaddr_reg:x2; val_offset:720*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 720*FLEN/8, x3, x1, x4) + +inst_275: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8455; +op3val:0x8455; valaddr_reg:x2; val_offset:723*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 723*FLEN/8, x3, x1, x4) + +inst_276: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8455; +op3val:0x7bff; valaddr_reg:x2; val_offset:726*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 726*FLEN/8, x3, x1, x4) + +inst_277: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8455; +op3val:0xfbff; valaddr_reg:x2; val_offset:729*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 729*FLEN/8, x3, x1, x4) + +inst_278: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8455; +op3val:0x7c00; valaddr_reg:x2; val_offset:732*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 732*FLEN/8, x3, x1, x4) + +inst_279: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8455; +op3val:0xfc00; valaddr_reg:x2; val_offset:735*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 735*FLEN/8, x3, x1, x4) + +inst_280: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8455; +op3val:0x7e00; valaddr_reg:x2; val_offset:738*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 738*FLEN/8, x3, x1, x4) + +inst_281: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8455; +op3val:0xfe00; valaddr_reg:x2; val_offset:741*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 741*FLEN/8, x3, x1, x4) + +inst_282: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8455; +op3val:0x7e01; valaddr_reg:x2; val_offset:744*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 744*FLEN/8, x3, x1, x4) + +inst_283: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8455; +op3val:0xfe55; valaddr_reg:x2; val_offset:747*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 747*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_3) + +inst_284: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8455; +op3val:0x7c01; valaddr_reg:x2; val_offset:750*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 750*FLEN/8, x3, x1, x4) + +inst_285: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8455; +op3val:0xfd55; valaddr_reg:x2; val_offset:753*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 753*FLEN/8, x3, x1, x4) + +inst_286: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8455; +op3val:0x3c00; valaddr_reg:x2; val_offset:756*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 756*FLEN/8, x3, x1, x4) + +inst_287: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8455; +op3val:0xbc00; valaddr_reg:x2; val_offset:759*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 759*FLEN/8, x3, x1, x4) + +inst_288: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7bff; +op3val:0x0; valaddr_reg:x2; val_offset:762*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 762*FLEN/8, x3, x1, x4) + +inst_289: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7bff; +op3val:0x8000; valaddr_reg:x2; val_offset:765*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 765*FLEN/8, x3, x1, x4) + +inst_290: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7bff; +op3val:0x1; valaddr_reg:x2; val_offset:768*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 768*FLEN/8, x3, x1, x4) + +inst_291: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7bff; +op3val:0x8001; valaddr_reg:x2; val_offset:771*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 771*FLEN/8, x3, x1, x4) + +inst_292: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7bff; +op3val:0x2; valaddr_reg:x2; val_offset:774*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 774*FLEN/8, x3, x1, x4) + +inst_293: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7bff; +op3val:0x83fe; valaddr_reg:x2; val_offset:777*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 777*FLEN/8, x3, x1, x4) + +inst_294: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7bff; +op3val:0x3ff; valaddr_reg:x2; val_offset:780*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 780*FLEN/8, x3, x1, x4) + +inst_295: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7bff; +op3val:0x83ff; valaddr_reg:x2; val_offset:783*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 783*FLEN/8, x3, x1, x4) + +inst_296: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7bff; +op3val:0x400; valaddr_reg:x2; val_offset:786*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 786*FLEN/8, x3, x1, x4) + +inst_297: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7bff; +op3val:0x8400; valaddr_reg:x2; val_offset:789*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 789*FLEN/8, x3, x1, x4) + +inst_298: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7bff; +op3val:0x401; valaddr_reg:x2; val_offset:792*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 792*FLEN/8, x3, x1, x4) + +inst_299: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7bff; +op3val:0x8455; valaddr_reg:x2; val_offset:795*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 795*FLEN/8, x3, x1, x4) + +inst_300: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7bff; +op3val:0x7bff; valaddr_reg:x2; val_offset:798*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 798*FLEN/8, x3, x1, x4) + +inst_301: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7bff; +op3val:0xfbff; valaddr_reg:x2; val_offset:801*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 801*FLEN/8, x3, x1, x4) + +inst_302: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7bff; +op3val:0x7c00; valaddr_reg:x2; val_offset:804*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 804*FLEN/8, x3, x1, x4) + +inst_303: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7bff; +op3val:0xfc00; valaddr_reg:x2; val_offset:807*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 807*FLEN/8, x3, x1, x4) + +inst_304: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7bff; +op3val:0x7e00; valaddr_reg:x2; val_offset:810*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 810*FLEN/8, x3, x1, x4) + +inst_305: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7bff; +op3val:0xfe00; valaddr_reg:x2; val_offset:813*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 813*FLEN/8, x3, x1, x4) + +inst_306: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7bff; +op3val:0x7e01; valaddr_reg:x2; val_offset:816*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 816*FLEN/8, x3, x1, x4) + +inst_307: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7bff; +op3val:0xfe55; valaddr_reg:x2; val_offset:819*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 819*FLEN/8, x3, x1, x4) + +inst_308: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7bff; +op3val:0x7c01; valaddr_reg:x2; val_offset:822*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 822*FLEN/8, x3, x1, x4) + +inst_309: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7bff; +op3val:0xfd55; valaddr_reg:x2; val_offset:825*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 825*FLEN/8, x3, x1, x4) + +inst_310: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7bff; +op3val:0x3c00; valaddr_reg:x2; val_offset:828*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 828*FLEN/8, x3, x1, x4) + +inst_311: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7bff; +op3val:0xbc00; valaddr_reg:x2; val_offset:831*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 831*FLEN/8, x3, x1, x4) + +inst_312: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfbff; +op3val:0x0; valaddr_reg:x2; val_offset:834*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 834*FLEN/8, x3, x1, x4) + +inst_313: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfbff; +op3val:0x8000; valaddr_reg:x2; val_offset:837*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 837*FLEN/8, x3, x1, x4) + +inst_314: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfbff; +op3val:0x1; valaddr_reg:x2; val_offset:840*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 840*FLEN/8, x3, x1, x4) + +inst_315: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfbff; +op3val:0x8001; valaddr_reg:x2; val_offset:843*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 843*FLEN/8, x3, x1, x4) + +inst_316: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfbff; +op3val:0x2; valaddr_reg:x2; val_offset:846*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 846*FLEN/8, x3, x1, x4) + +inst_317: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfbff; +op3val:0x83fe; valaddr_reg:x2; val_offset:849*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 849*FLEN/8, x3, x1, x4) + +inst_318: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfbff; +op3val:0x3ff; valaddr_reg:x2; val_offset:852*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 852*FLEN/8, x3, x1, x4) + +inst_319: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfbff; +op3val:0x83ff; valaddr_reg:x2; val_offset:855*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 855*FLEN/8, x3, x1, x4) + +inst_320: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfbff; +op3val:0x400; valaddr_reg:x2; val_offset:858*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 858*FLEN/8, x3, x1, x4) + +inst_321: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfbff; +op3val:0x8400; valaddr_reg:x2; val_offset:861*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 861*FLEN/8, x3, x1, x4) + +inst_322: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfbff; +op3val:0x401; valaddr_reg:x2; val_offset:864*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 864*FLEN/8, x3, x1, x4) + +inst_323: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfbff; +op3val:0x8455; valaddr_reg:x2; val_offset:867*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 867*FLEN/8, x3, x1, x4) + +inst_324: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfbff; +op3val:0x7bff; valaddr_reg:x2; val_offset:870*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 870*FLEN/8, x3, x1, x4) + +inst_325: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfbff; +op3val:0xfbff; valaddr_reg:x2; val_offset:873*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 873*FLEN/8, x3, x1, x4) + +inst_326: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfbff; +op3val:0x7c00; valaddr_reg:x2; val_offset:876*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 876*FLEN/8, x3, x1, x4) + +inst_327: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfbff; +op3val:0xfc00; valaddr_reg:x2; val_offset:879*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 879*FLEN/8, x3, x1, x4) + +inst_328: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfbff; +op3val:0x7e00; valaddr_reg:x2; val_offset:882*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 882*FLEN/8, x3, x1, x4) + +inst_329: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfbff; +op3val:0xfe00; valaddr_reg:x2; val_offset:885*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 885*FLEN/8, x3, x1, x4) + +inst_330: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfbff; +op3val:0x7e01; valaddr_reg:x2; val_offset:888*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 888*FLEN/8, x3, x1, x4) + +inst_331: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfbff; +op3val:0xfe55; valaddr_reg:x2; val_offset:891*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 891*FLEN/8, x3, x1, x4) + +inst_332: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfbff; +op3val:0x7c01; valaddr_reg:x2; val_offset:894*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 894*FLEN/8, x3, x1, x4) + +inst_333: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfbff; +op3val:0xfd55; valaddr_reg:x2; val_offset:897*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 897*FLEN/8, x3, x1, x4) + +inst_334: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfbff; +op3val:0x3c00; valaddr_reg:x2; val_offset:900*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 900*FLEN/8, x3, x1, x4) + +inst_335: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfbff; +op3val:0xbc00; valaddr_reg:x2; val_offset:903*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 903*FLEN/8, x3, x1, x4) + +inst_336: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7c00; +op3val:0x0; valaddr_reg:x2; val_offset:906*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 906*FLEN/8, x3, x1, x4) + +inst_337: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7c00; +op3val:0x8000; valaddr_reg:x2; val_offset:909*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 909*FLEN/8, x3, x1, x4) + +inst_338: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7c00; +op3val:0x1; valaddr_reg:x2; val_offset:912*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 912*FLEN/8, x3, x1, x4) + +inst_339: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7c00; +op3val:0x8001; valaddr_reg:x2; val_offset:915*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 915*FLEN/8, x3, x1, x4) + +inst_340: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7c00; +op3val:0x2; valaddr_reg:x2; val_offset:918*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 918*FLEN/8, x3, x1, x4) + +inst_341: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7c00; +op3val:0x83fe; valaddr_reg:x2; val_offset:921*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 921*FLEN/8, x3, x1, x4) + +inst_342: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7c00; +op3val:0x3ff; valaddr_reg:x2; val_offset:924*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 924*FLEN/8, x3, x1, x4) + +inst_343: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7c00; +op3val:0x83ff; valaddr_reg:x2; val_offset:927*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 927*FLEN/8, x3, x1, x4) + +inst_344: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7c00; +op3val:0x400; valaddr_reg:x2; val_offset:930*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 930*FLEN/8, x3, x1, x4) + +inst_345: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7c00; +op3val:0x8400; valaddr_reg:x2; val_offset:933*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 933*FLEN/8, x3, x1, x4) + +inst_346: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7c00; +op3val:0x401; valaddr_reg:x2; val_offset:936*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 936*FLEN/8, x3, x1, x4) + +inst_347: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7c00; +op3val:0x8455; valaddr_reg:x2; val_offset:939*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 939*FLEN/8, x3, x1, x4) + +inst_348: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7c00; +op3val:0x7bff; valaddr_reg:x2; val_offset:942*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 942*FLEN/8, x3, x1, x4) + +inst_349: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7c00; +op3val:0xfbff; valaddr_reg:x2; val_offset:945*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 945*FLEN/8, x3, x1, x4) + +inst_350: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7c00; +op3val:0x7c00; valaddr_reg:x2; val_offset:948*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 948*FLEN/8, x3, x1, x4) + +inst_351: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7c00; +op3val:0xfc00; valaddr_reg:x2; val_offset:951*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 951*FLEN/8, x3, x1, x4) + +inst_352: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7c00; +op3val:0x7e00; valaddr_reg:x2; val_offset:954*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 954*FLEN/8, x3, x1, x4) + +inst_353: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7c00; +op3val:0xfe00; valaddr_reg:x2; val_offset:957*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 957*FLEN/8, x3, x1, x4) + +inst_354: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7c00; +op3val:0x7e01; valaddr_reg:x2; val_offset:960*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 960*FLEN/8, x3, x1, x4) + +inst_355: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7c00; +op3val:0xfe55; valaddr_reg:x2; val_offset:963*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 963*FLEN/8, x3, x1, x4) + +inst_356: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7c00; +op3val:0x7c01; valaddr_reg:x2; val_offset:966*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 966*FLEN/8, x3, x1, x4) + +inst_357: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7c00; +op3val:0xfd55; valaddr_reg:x2; val_offset:969*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 969*FLEN/8, x3, x1, x4) + +inst_358: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7c00; +op3val:0x3c00; valaddr_reg:x2; val_offset:972*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 972*FLEN/8, x3, x1, x4) + +inst_359: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7c00; +op3val:0xbc00; valaddr_reg:x2; val_offset:975*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 975*FLEN/8, x3, x1, x4) + +inst_360: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfc00; +op3val:0x0; valaddr_reg:x2; val_offset:978*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 978*FLEN/8, x3, x1, x4) + +inst_361: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfc00; +op3val:0x8000; valaddr_reg:x2; val_offset:981*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 981*FLEN/8, x3, x1, x4) + +inst_362: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfc00; +op3val:0x1; valaddr_reg:x2; val_offset:984*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 984*FLEN/8, x3, x1, x4) + +inst_363: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfc00; +op3val:0x8001; valaddr_reg:x2; val_offset:987*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 987*FLEN/8, x3, x1, x4) + +inst_364: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfc00; +op3val:0x2; valaddr_reg:x2; val_offset:990*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 990*FLEN/8, x3, x1, x4) + +inst_365: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfc00; +op3val:0x83fe; valaddr_reg:x2; val_offset:993*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 993*FLEN/8, x3, x1, x4) + +inst_366: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfc00; +op3val:0x3ff; valaddr_reg:x2; val_offset:996*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 996*FLEN/8, x3, x1, x4) + +inst_367: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfc00; +op3val:0x83ff; valaddr_reg:x2; val_offset:999*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 999*FLEN/8, x3, x1, x4) + +inst_368: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfc00; +op3val:0x400; valaddr_reg:x2; val_offset:1002*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1002*FLEN/8, x3, x1, x4) + +inst_369: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfc00; +op3val:0x8400; valaddr_reg:x2; val_offset:1005*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1005*FLEN/8, x3, x1, x4) + +inst_370: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfc00; +op3val:0x401; valaddr_reg:x2; val_offset:1008*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1008*FLEN/8, x3, x1, x4) + +inst_371: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfc00; +op3val:0x8455; valaddr_reg:x2; val_offset:1011*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1011*FLEN/8, x3, x1, x4) + +inst_372: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfc00; +op3val:0x7bff; valaddr_reg:x2; val_offset:1014*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1014*FLEN/8, x3, x1, x4) + +inst_373: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfc00; +op3val:0xfbff; valaddr_reg:x2; val_offset:1017*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1017*FLEN/8, x3, x1, x4) + +inst_374: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfc00; +op3val:0x7c00; valaddr_reg:x2; val_offset:1020*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1020*FLEN/8, x3, x1, x4) + +inst_375: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfc00; +op3val:0xfc00; valaddr_reg:x2; val_offset:1023*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1023*FLEN/8, x3, x1, x4) + +inst_376: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfc00; +op3val:0x7e00; valaddr_reg:x2; val_offset:1026*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1026*FLEN/8, x3, x1, x4) + +inst_377: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfc00; +op3val:0xfe00; valaddr_reg:x2; val_offset:1029*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1029*FLEN/8, x3, x1, x4) + +inst_378: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfc00; +op3val:0x7e01; valaddr_reg:x2; val_offset:1032*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1032*FLEN/8, x3, x1, x4) + +inst_379: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfc00; +op3val:0xfe55; valaddr_reg:x2; val_offset:1035*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1035*FLEN/8, x3, x1, x4) + +inst_380: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfc00; +op3val:0x7c01; valaddr_reg:x2; val_offset:1038*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1038*FLEN/8, x3, x1, x4) + +inst_381: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfc00; +op3val:0xfd55; valaddr_reg:x2; val_offset:1041*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1041*FLEN/8, x3, x1, x4) + +inst_382: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfc00; +op3val:0x3c00; valaddr_reg:x2; val_offset:1044*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1044*FLEN/8, x3, x1, x4) + +inst_383: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfc00; +op3val:0xbc00; valaddr_reg:x2; val_offset:1047*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1047*FLEN/8, x3, x1, x4) + +inst_384: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7e00; +op3val:0x0; valaddr_reg:x2; val_offset:1050*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1050*FLEN/8, x3, x1, x4) + +inst_385: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7e00; +op3val:0x8000; valaddr_reg:x2; val_offset:1053*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1053*FLEN/8, x3, x1, x4) + +inst_386: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7e00; +op3val:0x1; valaddr_reg:x2; val_offset:1056*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1056*FLEN/8, x3, x1, x4) + +inst_387: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7e00; +op3val:0x8001; valaddr_reg:x2; val_offset:1059*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1059*FLEN/8, x3, x1, x4) + +inst_388: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7e00; +op3val:0x2; valaddr_reg:x2; val_offset:1062*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1062*FLEN/8, x3, x1, x4) + +inst_389: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7e00; +op3val:0x83fe; valaddr_reg:x2; val_offset:1065*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1065*FLEN/8, x3, x1, x4) + +inst_390: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7e00; +op3val:0x3ff; valaddr_reg:x2; val_offset:1068*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1068*FLEN/8, x3, x1, x4) + +inst_391: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7e00; +op3val:0x83ff; valaddr_reg:x2; val_offset:1071*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1071*FLEN/8, x3, x1, x4) + +inst_392: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7e00; +op3val:0x400; valaddr_reg:x2; val_offset:1074*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1074*FLEN/8, x3, x1, x4) + +inst_393: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7e00; +op3val:0x8400; valaddr_reg:x2; val_offset:1077*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1077*FLEN/8, x3, x1, x4) + +inst_394: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7e00; +op3val:0x401; valaddr_reg:x2; val_offset:1080*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1080*FLEN/8, x3, x1, x4) + +inst_395: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7e00; +op3val:0x8455; valaddr_reg:x2; val_offset:1083*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1083*FLEN/8, x3, x1, x4) + +inst_396: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7e00; +op3val:0x7bff; valaddr_reg:x2; val_offset:1086*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1086*FLEN/8, x3, x1, x4) + +inst_397: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7e00; +op3val:0xfbff; valaddr_reg:x2; val_offset:1089*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1089*FLEN/8, x3, x1, x4) + +inst_398: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7e00; +op3val:0x7c00; valaddr_reg:x2; val_offset:1092*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1092*FLEN/8, x3, x1, x4) + +inst_399: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7e00; +op3val:0xfc00; valaddr_reg:x2; val_offset:1095*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1095*FLEN/8, x3, x1, x4) + +inst_400: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7e00; +op3val:0x7e00; valaddr_reg:x2; val_offset:1098*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1098*FLEN/8, x3, x1, x4) + +inst_401: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7e00; +op3val:0xfe00; valaddr_reg:x2; val_offset:1101*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1101*FLEN/8, x3, x1, x4) + +inst_402: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7e00; +op3val:0x7e01; valaddr_reg:x2; val_offset:1104*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1104*FLEN/8, x3, x1, x4) + +inst_403: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7e00; +op3val:0xfe55; valaddr_reg:x2; val_offset:1107*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1107*FLEN/8, x3, x1, x4) + +inst_404: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7e00; +op3val:0x7c01; valaddr_reg:x2; val_offset:1110*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1110*FLEN/8, x3, x1, x4) + +inst_405: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7e00; +op3val:0xfd55; valaddr_reg:x2; val_offset:1113*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1113*FLEN/8, x3, x1, x4) + +inst_406: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7e00; +op3val:0x3c00; valaddr_reg:x2; val_offset:1116*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1116*FLEN/8, x3, x1, x4) + +inst_407: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7e00; +op3val:0xbc00; valaddr_reg:x2; val_offset:1119*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1119*FLEN/8, x3, x1, x4) + +inst_408: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfe00; +op3val:0x0; valaddr_reg:x2; val_offset:1122*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1122*FLEN/8, x3, x1, x4) + +inst_409: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfe00; +op3val:0x8000; valaddr_reg:x2; val_offset:1125*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1125*FLEN/8, x3, x1, x4) + +inst_410: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfe00; +op3val:0x1; valaddr_reg:x2; val_offset:1128*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1128*FLEN/8, x3, x1, x4) + +inst_411: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfe00; +op3val:0x8001; valaddr_reg:x2; val_offset:1131*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1131*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_4) + +inst_412: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfe00; +op3val:0x2; valaddr_reg:x2; val_offset:1134*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1134*FLEN/8, x3, x1, x4) + +inst_413: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfe00; +op3val:0x83fe; valaddr_reg:x2; val_offset:1137*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1137*FLEN/8, x3, x1, x4) + +inst_414: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfe00; +op3val:0x3ff; valaddr_reg:x2; val_offset:1140*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1140*FLEN/8, x3, x1, x4) + +inst_415: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfe00; +op3val:0x83ff; valaddr_reg:x2; val_offset:1143*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1143*FLEN/8, x3, x1, x4) + +inst_416: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfe00; +op3val:0x400; valaddr_reg:x2; val_offset:1146*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1146*FLEN/8, x3, x1, x4) + +inst_417: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfe00; +op3val:0x8400; valaddr_reg:x2; val_offset:1149*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1149*FLEN/8, x3, x1, x4) + +inst_418: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfe00; +op3val:0x401; valaddr_reg:x2; val_offset:1152*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1152*FLEN/8, x3, x1, x4) + +inst_419: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfe00; +op3val:0x8455; valaddr_reg:x2; val_offset:1155*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1155*FLEN/8, x3, x1, x4) + +inst_420: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfe00; +op3val:0x7bff; valaddr_reg:x2; val_offset:1158*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1158*FLEN/8, x3, x1, x4) + +inst_421: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfe00; +op3val:0xfbff; valaddr_reg:x2; val_offset:1161*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1161*FLEN/8, x3, x1, x4) + +inst_422: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfe00; +op3val:0x7c00; valaddr_reg:x2; val_offset:1164*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1164*FLEN/8, x3, x1, x4) + +inst_423: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfe00; +op3val:0xfc00; valaddr_reg:x2; val_offset:1167*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1167*FLEN/8, x3, x1, x4) + +inst_424: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfe00; +op3val:0x7e00; valaddr_reg:x2; val_offset:1170*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1170*FLEN/8, x3, x1, x4) + +inst_425: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfe00; +op3val:0xfe00; valaddr_reg:x2; val_offset:1173*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1173*FLEN/8, x3, x1, x4) + +inst_426: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfe00; +op3val:0x7e01; valaddr_reg:x2; val_offset:1176*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1176*FLEN/8, x3, x1, x4) + +inst_427: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfe00; +op3val:0xfe55; valaddr_reg:x2; val_offset:1179*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1179*FLEN/8, x3, x1, x4) + +inst_428: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfe00; +op3val:0x7c01; valaddr_reg:x2; val_offset:1182*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1182*FLEN/8, x3, x1, x4) + +inst_429: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfe00; +op3val:0xfd55; valaddr_reg:x2; val_offset:1185*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1185*FLEN/8, x3, x1, x4) + +inst_430: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfe00; +op3val:0x3c00; valaddr_reg:x2; val_offset:1188*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1188*FLEN/8, x3, x1, x4) + +inst_431: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfe00; +op3val:0xbc00; valaddr_reg:x2; val_offset:1191*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1191*FLEN/8, x3, x1, x4) + +inst_432: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7e01; +op3val:0x0; valaddr_reg:x2; val_offset:1194*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1194*FLEN/8, x3, x1, x4) + +inst_433: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7e01; +op3val:0x8000; valaddr_reg:x2; val_offset:1197*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1197*FLEN/8, x3, x1, x4) + +inst_434: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7e01; +op3val:0x1; valaddr_reg:x2; val_offset:1200*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1200*FLEN/8, x3, x1, x4) + +inst_435: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7e01; +op3val:0x8001; valaddr_reg:x2; val_offset:1203*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1203*FLEN/8, x3, x1, x4) + +inst_436: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7e01; +op3val:0x2; valaddr_reg:x2; val_offset:1206*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1206*FLEN/8, x3, x1, x4) + +inst_437: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7e01; +op3val:0x83fe; valaddr_reg:x2; val_offset:1209*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1209*FLEN/8, x3, x1, x4) + +inst_438: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7e01; +op3val:0x3ff; valaddr_reg:x2; val_offset:1212*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1212*FLEN/8, x3, x1, x4) + +inst_439: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7e01; +op3val:0x83ff; valaddr_reg:x2; val_offset:1215*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1215*FLEN/8, x3, x1, x4) + +inst_440: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7e01; +op3val:0x400; valaddr_reg:x2; val_offset:1218*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1218*FLEN/8, x3, x1, x4) + +inst_441: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7e01; +op3val:0x8400; valaddr_reg:x2; val_offset:1221*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1221*FLEN/8, x3, x1, x4) + +inst_442: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7e01; +op3val:0x401; valaddr_reg:x2; val_offset:1224*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1224*FLEN/8, x3, x1, x4) + +inst_443: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7e01; +op3val:0x8455; valaddr_reg:x2; val_offset:1227*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1227*FLEN/8, x3, x1, x4) + +inst_444: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7e01; +op3val:0x7bff; valaddr_reg:x2; val_offset:1230*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1230*FLEN/8, x3, x1, x4) + +inst_445: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7e01; +op3val:0xfbff; valaddr_reg:x2; val_offset:1233*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1233*FLEN/8, x3, x1, x4) + +inst_446: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7e01; +op3val:0x7c00; valaddr_reg:x2; val_offset:1236*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1236*FLEN/8, x3, x1, x4) + +inst_447: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7e01; +op3val:0xfc00; valaddr_reg:x2; val_offset:1239*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1239*FLEN/8, x3, x1, x4) + +inst_448: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7e01; +op3val:0x7e00; valaddr_reg:x2; val_offset:1242*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1242*FLEN/8, x3, x1, x4) + +inst_449: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7e01; +op3val:0xfe00; valaddr_reg:x2; val_offset:1245*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1245*FLEN/8, x3, x1, x4) + +inst_450: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7e01; +op3val:0x7e01; valaddr_reg:x2; val_offset:1248*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1248*FLEN/8, x3, x1, x4) + +inst_451: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7e01; +op3val:0xfe55; valaddr_reg:x2; val_offset:1251*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1251*FLEN/8, x3, x1, x4) + +inst_452: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7e01; +op3val:0x7c01; valaddr_reg:x2; val_offset:1254*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1254*FLEN/8, x3, x1, x4) + +inst_453: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7e01; +op3val:0xfd55; valaddr_reg:x2; val_offset:1257*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1257*FLEN/8, x3, x1, x4) + +inst_454: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7e01; +op3val:0x3c00; valaddr_reg:x2; val_offset:1260*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1260*FLEN/8, x3, x1, x4) + +inst_455: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7e01; +op3val:0xbc00; valaddr_reg:x2; val_offset:1263*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1263*FLEN/8, x3, x1, x4) + +inst_456: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfe55; +op3val:0x0; valaddr_reg:x2; val_offset:1266*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1266*FLEN/8, x3, x1, x4) + +inst_457: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfe55; +op3val:0x8000; valaddr_reg:x2; val_offset:1269*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1269*FLEN/8, x3, x1, x4) + +inst_458: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfe55; +op3val:0x1; valaddr_reg:x2; val_offset:1272*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1272*FLEN/8, x3, x1, x4) + +inst_459: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfe55; +op3val:0x8001; valaddr_reg:x2; val_offset:1275*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1275*FLEN/8, x3, x1, x4) + +inst_460: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfe55; +op3val:0x2; valaddr_reg:x2; val_offset:1278*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1278*FLEN/8, x3, x1, x4) + +inst_461: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfe55; +op3val:0x83fe; valaddr_reg:x2; val_offset:1281*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1281*FLEN/8, x3, x1, x4) + +inst_462: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfe55; +op3val:0x3ff; valaddr_reg:x2; val_offset:1284*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1284*FLEN/8, x3, x1, x4) + +inst_463: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfe55; +op3val:0x83ff; valaddr_reg:x2; val_offset:1287*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1287*FLEN/8, x3, x1, x4) + +inst_464: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfe55; +op3val:0x400; valaddr_reg:x2; val_offset:1290*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1290*FLEN/8, x3, x1, x4) + +inst_465: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfe55; +op3val:0x8400; valaddr_reg:x2; val_offset:1293*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1293*FLEN/8, x3, x1, x4) + +inst_466: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfe55; +op3val:0x401; valaddr_reg:x2; val_offset:1296*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1296*FLEN/8, x3, x1, x4) + +inst_467: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfe55; +op3val:0x8455; valaddr_reg:x2; val_offset:1299*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1299*FLEN/8, x3, x1, x4) + +inst_468: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfe55; +op3val:0x7bff; valaddr_reg:x2; val_offset:1302*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1302*FLEN/8, x3, x1, x4) + +inst_469: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfe55; +op3val:0xfbff; valaddr_reg:x2; val_offset:1305*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1305*FLEN/8, x3, x1, x4) + +inst_470: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfe55; +op3val:0x7c00; valaddr_reg:x2; val_offset:1308*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1308*FLEN/8, x3, x1, x4) + +inst_471: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfe55; +op3val:0xfc00; valaddr_reg:x2; val_offset:1311*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1311*FLEN/8, x3, x1, x4) + +inst_472: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfe55; +op3val:0x7e00; valaddr_reg:x2; val_offset:1314*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1314*FLEN/8, x3, x1, x4) + +inst_473: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfe55; +op3val:0xfe00; valaddr_reg:x2; val_offset:1317*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1317*FLEN/8, x3, x1, x4) + +inst_474: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfe55; +op3val:0x7e01; valaddr_reg:x2; val_offset:1320*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1320*FLEN/8, x3, x1, x4) + +inst_475: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfe55; +op3val:0xfe55; valaddr_reg:x2; val_offset:1323*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1323*FLEN/8, x3, x1, x4) + +inst_476: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfe55; +op3val:0x7c01; valaddr_reg:x2; val_offset:1326*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1326*FLEN/8, x3, x1, x4) + +inst_477: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfe55; +op3val:0xfd55; valaddr_reg:x2; val_offset:1329*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1329*FLEN/8, x3, x1, x4) + +inst_478: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfe55; +op3val:0x3c00; valaddr_reg:x2; val_offset:1332*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1332*FLEN/8, x3, x1, x4) + +inst_479: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfe55; +op3val:0xbc00; valaddr_reg:x2; val_offset:1335*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1335*FLEN/8, x3, x1, x4) + +inst_480: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7c01; +op3val:0x0; valaddr_reg:x2; val_offset:1338*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1338*FLEN/8, x3, x1, x4) + +inst_481: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7c01; +op3val:0x8000; valaddr_reg:x2; val_offset:1341*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1341*FLEN/8, x3, x1, x4) + +inst_482: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7c01; +op3val:0x1; valaddr_reg:x2; val_offset:1344*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1344*FLEN/8, x3, x1, x4) + +inst_483: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7c01; +op3val:0x8001; valaddr_reg:x2; val_offset:1347*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1347*FLEN/8, x3, x1, x4) + +inst_484: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7c01; +op3val:0x2; valaddr_reg:x2; val_offset:1350*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1350*FLEN/8, x3, x1, x4) + +inst_485: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7c01; +op3val:0x83fe; valaddr_reg:x2; val_offset:1353*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1353*FLEN/8, x3, x1, x4) + +inst_486: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7c01; +op3val:0x3ff; valaddr_reg:x2; val_offset:1356*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1356*FLEN/8, x3, x1, x4) + +inst_487: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7c01; +op3val:0x83ff; valaddr_reg:x2; val_offset:1359*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1359*FLEN/8, x3, x1, x4) + +inst_488: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7c01; +op3val:0x400; valaddr_reg:x2; val_offset:1362*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1362*FLEN/8, x3, x1, x4) + +inst_489: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7c01; +op3val:0x8400; valaddr_reg:x2; val_offset:1365*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1365*FLEN/8, x3, x1, x4) + +inst_490: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7c01; +op3val:0x401; valaddr_reg:x2; val_offset:1368*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1368*FLEN/8, x3, x1, x4) + +inst_491: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7c01; +op3val:0x8455; valaddr_reg:x2; val_offset:1371*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1371*FLEN/8, x3, x1, x4) + +inst_492: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7c01; +op3val:0x7bff; valaddr_reg:x2; val_offset:1374*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1374*FLEN/8, x3, x1, x4) + +inst_493: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7c01; +op3val:0xfbff; valaddr_reg:x2; val_offset:1377*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1377*FLEN/8, x3, x1, x4) + +inst_494: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7c01; +op3val:0x7c00; valaddr_reg:x2; val_offset:1380*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1380*FLEN/8, x3, x1, x4) + +inst_495: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7c01; +op3val:0xfc00; valaddr_reg:x2; val_offset:1383*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1383*FLEN/8, x3, x1, x4) + +inst_496: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7c01; +op3val:0x7e00; valaddr_reg:x2; val_offset:1386*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1386*FLEN/8, x3, x1, x4) + +inst_497: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7c01; +op3val:0xfe00; valaddr_reg:x2; val_offset:1389*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1389*FLEN/8, x3, x1, x4) + +inst_498: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7c01; +op3val:0x7e01; valaddr_reg:x2; val_offset:1392*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1392*FLEN/8, x3, x1, x4) + +inst_499: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7c01; +op3val:0xfe55; valaddr_reg:x2; val_offset:1395*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1395*FLEN/8, x3, x1, x4) + +inst_500: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7c01; +op3val:0x7c01; valaddr_reg:x2; val_offset:1398*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1398*FLEN/8, x3, x1, x4) + +inst_501: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7c01; +op3val:0xfd55; valaddr_reg:x2; val_offset:1401*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1401*FLEN/8, x3, x1, x4) + +inst_502: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7c01; +op3val:0x3c00; valaddr_reg:x2; val_offset:1404*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1404*FLEN/8, x3, x1, x4) + +inst_503: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7c01; +op3val:0xbc00; valaddr_reg:x2; val_offset:1407*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1407*FLEN/8, x3, x1, x4) + +inst_504: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfd55; +op3val:0x0; valaddr_reg:x2; val_offset:1410*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1410*FLEN/8, x3, x1, x4) + +inst_505: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfd55; +op3val:0x8000; valaddr_reg:x2; val_offset:1413*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1413*FLEN/8, x3, x1, x4) + +inst_506: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfd55; +op3val:0x1; valaddr_reg:x2; val_offset:1416*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1416*FLEN/8, x3, x1, x4) + +inst_507: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfd55; +op3val:0x8001; valaddr_reg:x2; val_offset:1419*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1419*FLEN/8, x3, x1, x4) + +inst_508: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfd55; +op3val:0x2; valaddr_reg:x2; val_offset:1422*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1422*FLEN/8, x3, x1, x4) + +inst_509: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfd55; +op3val:0x83fe; valaddr_reg:x2; val_offset:1425*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1425*FLEN/8, x3, x1, x4) + +inst_510: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfd55; +op3val:0x3ff; valaddr_reg:x2; val_offset:1428*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1428*FLEN/8, x3, x1, x4) + +inst_511: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfd55; +op3val:0x83ff; valaddr_reg:x2; val_offset:1431*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1431*FLEN/8, x3, x1, x4) + +inst_512: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfd55; +op3val:0x400; valaddr_reg:x2; val_offset:1434*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1434*FLEN/8, x3, x1, x4) + +inst_513: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfd55; +op3val:0x8400; valaddr_reg:x2; val_offset:1437*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1437*FLEN/8, x3, x1, x4) + +inst_514: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfd55; +op3val:0x401; valaddr_reg:x2; val_offset:1440*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1440*FLEN/8, x3, x1, x4) + +inst_515: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfd55; +op3val:0x8455; valaddr_reg:x2; val_offset:1443*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1443*FLEN/8, x3, x1, x4) + +inst_516: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfd55; +op3val:0x7bff; valaddr_reg:x2; val_offset:1446*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1446*FLEN/8, x3, x1, x4) + +inst_517: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfd55; +op3val:0xfbff; valaddr_reg:x2; val_offset:1449*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1449*FLEN/8, x3, x1, x4) + +inst_518: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfd55; +op3val:0x7c00; valaddr_reg:x2; val_offset:1452*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1452*FLEN/8, x3, x1, x4) + +inst_519: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfd55; +op3val:0xfc00; valaddr_reg:x2; val_offset:1455*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1455*FLEN/8, x3, x1, x4) + +inst_520: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfd55; +op3val:0x7e00; valaddr_reg:x2; val_offset:1458*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1458*FLEN/8, x3, x1, x4) + +inst_521: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfd55; +op3val:0xfe00; valaddr_reg:x2; val_offset:1461*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1461*FLEN/8, x3, x1, x4) + +inst_522: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfd55; +op3val:0x7e01; valaddr_reg:x2; val_offset:1464*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1464*FLEN/8, x3, x1, x4) + +inst_523: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfd55; +op3val:0xfe55; valaddr_reg:x2; val_offset:1467*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1467*FLEN/8, x3, x1, x4) + +inst_524: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfd55; +op3val:0x7c01; valaddr_reg:x2; val_offset:1470*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1470*FLEN/8, x3, x1, x4) + +inst_525: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfd55; +op3val:0xfd55; valaddr_reg:x2; val_offset:1473*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1473*FLEN/8, x3, x1, x4) + +inst_526: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfd55; +op3val:0x3c00; valaddr_reg:x2; val_offset:1476*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1476*FLEN/8, x3, x1, x4) + +inst_527: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfd55; +op3val:0xbc00; valaddr_reg:x2; val_offset:1479*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1479*FLEN/8, x3, x1, x4) + +inst_528: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3c00; +op3val:0x0; valaddr_reg:x2; val_offset:1482*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1482*FLEN/8, x3, x1, x4) + +inst_529: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3c00; +op3val:0x8000; valaddr_reg:x2; val_offset:1485*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1485*FLEN/8, x3, x1, x4) + +inst_530: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3c00; +op3val:0x1; valaddr_reg:x2; val_offset:1488*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1488*FLEN/8, x3, x1, x4) + +inst_531: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3c00; +op3val:0x8001; valaddr_reg:x2; val_offset:1491*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1491*FLEN/8, x3, x1, x4) + +inst_532: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3c00; +op3val:0x2; valaddr_reg:x2; val_offset:1494*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1494*FLEN/8, x3, x1, x4) + +inst_533: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3c00; +op3val:0x83fe; valaddr_reg:x2; val_offset:1497*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1497*FLEN/8, x3, x1, x4) + +inst_534: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3c00; +op3val:0x3ff; valaddr_reg:x2; val_offset:1500*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1500*FLEN/8, x3, x1, x4) + +inst_535: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3c00; +op3val:0x83ff; valaddr_reg:x2; val_offset:1503*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1503*FLEN/8, x3, x1, x4) + +inst_536: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3c00; +op3val:0x400; valaddr_reg:x2; val_offset:1506*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1506*FLEN/8, x3, x1, x4) + +inst_537: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3c00; +op3val:0x8400; valaddr_reg:x2; val_offset:1509*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1509*FLEN/8, x3, x1, x4) + +inst_538: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3c00; +op3val:0x401; valaddr_reg:x2; val_offset:1512*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1512*FLEN/8, x3, x1, x4) + +inst_539: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3c00; +op3val:0x8455; valaddr_reg:x2; val_offset:1515*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1515*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_5) + +inst_540: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3c00; +op3val:0x7bff; valaddr_reg:x2; val_offset:1518*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1518*FLEN/8, x3, x1, x4) + +inst_541: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3c00; +op3val:0xfbff; valaddr_reg:x2; val_offset:1521*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1521*FLEN/8, x3, x1, x4) + +inst_542: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3c00; +op3val:0x7c00; valaddr_reg:x2; val_offset:1524*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1524*FLEN/8, x3, x1, x4) + +inst_543: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3c00; +op3val:0xfc00; valaddr_reg:x2; val_offset:1527*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1527*FLEN/8, x3, x1, x4) + +inst_544: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3c00; +op3val:0x7e00; valaddr_reg:x2; val_offset:1530*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1530*FLEN/8, x3, x1, x4) + +inst_545: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3c00; +op3val:0xfe00; valaddr_reg:x2; val_offset:1533*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1533*FLEN/8, x3, x1, x4) + +inst_546: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3c00; +op3val:0x7e01; valaddr_reg:x2; val_offset:1536*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1536*FLEN/8, x3, x1, x4) + +inst_547: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3c00; +op3val:0xfe55; valaddr_reg:x2; val_offset:1539*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1539*FLEN/8, x3, x1, x4) + +inst_548: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3c00; +op3val:0x7c01; valaddr_reg:x2; val_offset:1542*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1542*FLEN/8, x3, x1, x4) + +inst_549: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3c00; +op3val:0xfd55; valaddr_reg:x2; val_offset:1545*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1545*FLEN/8, x3, x1, x4) + +inst_550: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3c00; +op3val:0x3c00; valaddr_reg:x2; val_offset:1548*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1548*FLEN/8, x3, x1, x4) + +inst_551: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3c00; +op3val:0xbc00; valaddr_reg:x2; val_offset:1551*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1551*FLEN/8, x3, x1, x4) + +inst_552: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xbc00; +op3val:0x0; valaddr_reg:x2; val_offset:1554*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1554*FLEN/8, x3, x1, x4) + +inst_553: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xbc00; +op3val:0x8000; valaddr_reg:x2; val_offset:1557*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1557*FLEN/8, x3, x1, x4) + +inst_554: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xbc00; +op3val:0x1; valaddr_reg:x2; val_offset:1560*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1560*FLEN/8, x3, x1, x4) + +inst_555: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xbc00; +op3val:0x8001; valaddr_reg:x2; val_offset:1563*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1563*FLEN/8, x3, x1, x4) + +inst_556: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xbc00; +op3val:0x2; valaddr_reg:x2; val_offset:1566*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1566*FLEN/8, x3, x1, x4) + +inst_557: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xbc00; +op3val:0x83fe; valaddr_reg:x2; val_offset:1569*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1569*FLEN/8, x3, x1, x4) + +inst_558: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xbc00; +op3val:0x3ff; valaddr_reg:x2; val_offset:1572*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1572*FLEN/8, x3, x1, x4) + +inst_559: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xbc00; +op3val:0x83ff; valaddr_reg:x2; val_offset:1575*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1575*FLEN/8, x3, x1, x4) + +inst_560: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xbc00; +op3val:0x400; valaddr_reg:x2; val_offset:1578*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1578*FLEN/8, x3, x1, x4) + +inst_561: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xbc00; +op3val:0x8400; valaddr_reg:x2; val_offset:1581*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1581*FLEN/8, x3, x1, x4) + +inst_562: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xbc00; +op3val:0x401; valaddr_reg:x2; val_offset:1584*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1584*FLEN/8, x3, x1, x4) + +inst_563: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xbc00; +op3val:0x8455; valaddr_reg:x2; val_offset:1587*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1587*FLEN/8, x3, x1, x4) + +inst_564: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xbc00; +op3val:0x7bff; valaddr_reg:x2; val_offset:1590*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1590*FLEN/8, x3, x1, x4) + +inst_565: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xbc00; +op3val:0xfbff; valaddr_reg:x2; val_offset:1593*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1593*FLEN/8, x3, x1, x4) + +inst_566: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xbc00; +op3val:0x7c00; valaddr_reg:x2; val_offset:1596*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1596*FLEN/8, x3, x1, x4) + +inst_567: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xbc00; +op3val:0xfc00; valaddr_reg:x2; val_offset:1599*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1599*FLEN/8, x3, x1, x4) + +inst_568: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xbc00; +op3val:0x7e00; valaddr_reg:x2; val_offset:1602*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1602*FLEN/8, x3, x1, x4) + +inst_569: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xbc00; +op3val:0xfe00; valaddr_reg:x2; val_offset:1605*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1605*FLEN/8, x3, x1, x4) + +inst_570: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xbc00; +op3val:0x7e01; valaddr_reg:x2; val_offset:1608*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1608*FLEN/8, x3, x1, x4) + +inst_571: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xbc00; +op3val:0xfe55; valaddr_reg:x2; val_offset:1611*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1611*FLEN/8, x3, x1, x4) + +inst_572: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xbc00; +op3val:0x7c01; valaddr_reg:x2; val_offset:1614*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1614*FLEN/8, x3, x1, x4) + +inst_573: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xbc00; +op3val:0xfd55; valaddr_reg:x2; val_offset:1617*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1617*FLEN/8, x3, x1, x4) + +inst_574: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xbc00; +op3val:0x3c00; valaddr_reg:x2; val_offset:1620*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1620*FLEN/8, x3, x1, x4) + +inst_575: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xbc00; +op3val:0xbc00; valaddr_reg:x2; val_offset:1623*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1623*FLEN/8, x3, x1, x4) + +inst_576: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x0; +op3val:0x0; valaddr_reg:x2; val_offset:1626*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1626*FLEN/8, x3, x1, x4) + +inst_577: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x0; +op3val:0x8000; valaddr_reg:x2; val_offset:1629*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1629*FLEN/8, x3, x1, x4) + +inst_578: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x0; +op3val:0x1; valaddr_reg:x2; val_offset:1632*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1632*FLEN/8, x3, x1, x4) + +inst_579: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x0; +op3val:0x8001; valaddr_reg:x2; val_offset:1635*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1635*FLEN/8, x3, x1, x4) + +inst_580: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x0; +op3val:0x2; valaddr_reg:x2; val_offset:1638*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1638*FLEN/8, x3, x1, x4) + +inst_581: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x0; +op3val:0x83fe; valaddr_reg:x2; val_offset:1641*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1641*FLEN/8, x3, x1, x4) + +inst_582: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x0; +op3val:0x3ff; valaddr_reg:x2; val_offset:1644*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1644*FLEN/8, x3, x1, x4) + +inst_583: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x0; +op3val:0x83ff; valaddr_reg:x2; val_offset:1647*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1647*FLEN/8, x3, x1, x4) + +inst_584: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x0; +op3val:0x400; valaddr_reg:x2; val_offset:1650*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1650*FLEN/8, x3, x1, x4) + +inst_585: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x0; +op3val:0x8400; valaddr_reg:x2; val_offset:1653*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1653*FLEN/8, x3, x1, x4) + +inst_586: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x0; +op3val:0x401; valaddr_reg:x2; val_offset:1656*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1656*FLEN/8, x3, x1, x4) + +inst_587: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x0; +op3val:0x8455; valaddr_reg:x2; val_offset:1659*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1659*FLEN/8, x3, x1, x4) + +inst_588: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x0; +op3val:0x7bff; valaddr_reg:x2; val_offset:1662*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1662*FLEN/8, x3, x1, x4) + +inst_589: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x0; +op3val:0xfbff; valaddr_reg:x2; val_offset:1665*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1665*FLEN/8, x3, x1, x4) + +inst_590: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x0; +op3val:0x7c00; valaddr_reg:x2; val_offset:1668*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1668*FLEN/8, x3, x1, x4) + +inst_591: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x0; +op3val:0xfc00; valaddr_reg:x2; val_offset:1671*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1671*FLEN/8, x3, x1, x4) + +inst_592: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x0; +op3val:0x7e00; valaddr_reg:x2; val_offset:1674*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1674*FLEN/8, x3, x1, x4) + +inst_593: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x0; +op3val:0xfe00; valaddr_reg:x2; val_offset:1677*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1677*FLEN/8, x3, x1, x4) + +inst_594: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x0; +op3val:0x7e01; valaddr_reg:x2; val_offset:1680*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1680*FLEN/8, x3, x1, x4) + +inst_595: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x0; +op3val:0xfe55; valaddr_reg:x2; val_offset:1683*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1683*FLEN/8, x3, x1, x4) + +inst_596: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x0; +op3val:0x7c01; valaddr_reg:x2; val_offset:1686*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1686*FLEN/8, x3, x1, x4) + +inst_597: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x0; +op3val:0xfd55; valaddr_reg:x2; val_offset:1689*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1689*FLEN/8, x3, x1, x4) + +inst_598: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x0; +op3val:0x3c00; valaddr_reg:x2; val_offset:1692*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1692*FLEN/8, x3, x1, x4) + +inst_599: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x0; +op3val:0xbc00; valaddr_reg:x2; val_offset:1695*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1695*FLEN/8, x3, x1, x4) + +inst_600: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8000; +op3val:0x0; valaddr_reg:x2; val_offset:1698*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1698*FLEN/8, x3, x1, x4) + +inst_601: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8000; +op3val:0x8000; valaddr_reg:x2; val_offset:1701*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1701*FLEN/8, x3, x1, x4) + +inst_602: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8000; +op3val:0x1; valaddr_reg:x2; val_offset:1704*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1704*FLEN/8, x3, x1, x4) + +inst_603: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8000; +op3val:0x8001; valaddr_reg:x2; val_offset:1707*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1707*FLEN/8, x3, x1, x4) + +inst_604: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8000; +op3val:0x2; valaddr_reg:x2; val_offset:1710*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1710*FLEN/8, x3, x1, x4) + +inst_605: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8000; +op3val:0x83fe; valaddr_reg:x2; val_offset:1713*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1713*FLEN/8, x3, x1, x4) + +inst_606: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8000; +op3val:0x3ff; valaddr_reg:x2; val_offset:1716*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1716*FLEN/8, x3, x1, x4) + +inst_607: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8000; +op3val:0x83ff; valaddr_reg:x2; val_offset:1719*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1719*FLEN/8, x3, x1, x4) + +inst_608: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8000; +op3val:0x400; valaddr_reg:x2; val_offset:1722*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1722*FLEN/8, x3, x1, x4) + +inst_609: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8000; +op3val:0x8400; valaddr_reg:x2; val_offset:1725*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1725*FLEN/8, x3, x1, x4) + +inst_610: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8000; +op3val:0x401; valaddr_reg:x2; val_offset:1728*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1728*FLEN/8, x3, x1, x4) + +inst_611: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8000; +op3val:0x8455; valaddr_reg:x2; val_offset:1731*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1731*FLEN/8, x3, x1, x4) + +inst_612: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x2; val_offset:1734*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1734*FLEN/8, x3, x1, x4) + +inst_613: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x2; val_offset:1737*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1737*FLEN/8, x3, x1, x4) + +inst_614: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8000; +op3val:0x7c00; valaddr_reg:x2; val_offset:1740*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1740*FLEN/8, x3, x1, x4) + +inst_615: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8000; +op3val:0xfc00; valaddr_reg:x2; val_offset:1743*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1743*FLEN/8, x3, x1, x4) + +inst_616: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8000; +op3val:0x7e00; valaddr_reg:x2; val_offset:1746*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1746*FLEN/8, x3, x1, x4) + +inst_617: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8000; +op3val:0xfe00; valaddr_reg:x2; val_offset:1749*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1749*FLEN/8, x3, x1, x4) + +inst_618: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8000; +op3val:0x7e01; valaddr_reg:x2; val_offset:1752*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1752*FLEN/8, x3, x1, x4) + +inst_619: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8000; +op3val:0xfe55; valaddr_reg:x2; val_offset:1755*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1755*FLEN/8, x3, x1, x4) + +inst_620: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8000; +op3val:0x7c01; valaddr_reg:x2; val_offset:1758*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1758*FLEN/8, x3, x1, x4) + +inst_621: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8000; +op3val:0xfd55; valaddr_reg:x2; val_offset:1761*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1761*FLEN/8, x3, x1, x4) + +inst_622: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8000; +op3val:0x3c00; valaddr_reg:x2; val_offset:1764*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1764*FLEN/8, x3, x1, x4) + +inst_623: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8000; +op3val:0xbc00; valaddr_reg:x2; val_offset:1767*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1767*FLEN/8, x3, x1, x4) + +inst_624: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x1; +op3val:0x0; valaddr_reg:x2; val_offset:1770*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1770*FLEN/8, x3, x1, x4) + +inst_625: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x1; +op3val:0x8000; valaddr_reg:x2; val_offset:1773*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1773*FLEN/8, x3, x1, x4) + +inst_626: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x1; +op3val:0x1; valaddr_reg:x2; val_offset:1776*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1776*FLEN/8, x3, x1, x4) + +inst_627: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x1; +op3val:0x8001; valaddr_reg:x2; val_offset:1779*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1779*FLEN/8, x3, x1, x4) + +inst_628: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x1; +op3val:0x2; valaddr_reg:x2; val_offset:1782*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1782*FLEN/8, x3, x1, x4) + +inst_629: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x1; +op3val:0x83fe; valaddr_reg:x2; val_offset:1785*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1785*FLEN/8, x3, x1, x4) + +inst_630: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x1; +op3val:0x3ff; valaddr_reg:x2; val_offset:1788*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1788*FLEN/8, x3, x1, x4) + +inst_631: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x1; +op3val:0x83ff; valaddr_reg:x2; val_offset:1791*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1791*FLEN/8, x3, x1, x4) + +inst_632: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x1; +op3val:0x400; valaddr_reg:x2; val_offset:1794*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1794*FLEN/8, x3, x1, x4) + +inst_633: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x1; +op3val:0x8400; valaddr_reg:x2; val_offset:1797*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1797*FLEN/8, x3, x1, x4) + +inst_634: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x1; +op3val:0x401; valaddr_reg:x2; val_offset:1800*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1800*FLEN/8, x3, x1, x4) + +inst_635: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x1; +op3val:0x8455; valaddr_reg:x2; val_offset:1803*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1803*FLEN/8, x3, x1, x4) + +inst_636: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x1; +op3val:0x7bff; valaddr_reg:x2; val_offset:1806*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1806*FLEN/8, x3, x1, x4) + +inst_637: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x1; +op3val:0xfbff; valaddr_reg:x2; val_offset:1809*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1809*FLEN/8, x3, x1, x4) + +inst_638: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x1; +op3val:0x7c00; valaddr_reg:x2; val_offset:1812*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1812*FLEN/8, x3, x1, x4) + +inst_639: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x1; +op3val:0xfc00; valaddr_reg:x2; val_offset:1815*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1815*FLEN/8, x3, x1, x4) + +inst_640: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x1; +op3val:0x7e00; valaddr_reg:x2; val_offset:1818*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1818*FLEN/8, x3, x1, x4) + +inst_641: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x1; +op3val:0xfe00; valaddr_reg:x2; val_offset:1821*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1821*FLEN/8, x3, x1, x4) + +inst_642: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x1; +op3val:0x7e01; valaddr_reg:x2; val_offset:1824*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1824*FLEN/8, x3, x1, x4) + +inst_643: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x1; +op3val:0xfe55; valaddr_reg:x2; val_offset:1827*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1827*FLEN/8, x3, x1, x4) + +inst_644: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x1; +op3val:0x7c01; valaddr_reg:x2; val_offset:1830*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1830*FLEN/8, x3, x1, x4) + +inst_645: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x1; +op3val:0xfd55; valaddr_reg:x2; val_offset:1833*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1833*FLEN/8, x3, x1, x4) + +inst_646: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x1; +op3val:0x3c00; valaddr_reg:x2; val_offset:1836*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1836*FLEN/8, x3, x1, x4) + +inst_647: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x1; +op3val:0xbc00; valaddr_reg:x2; val_offset:1839*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1839*FLEN/8, x3, x1, x4) + +inst_648: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8001; +op3val:0x0; valaddr_reg:x2; val_offset:1842*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1842*FLEN/8, x3, x1, x4) + +inst_649: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8001; +op3val:0x8000; valaddr_reg:x2; val_offset:1845*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1845*FLEN/8, x3, x1, x4) + +inst_650: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8001; +op3val:0x1; valaddr_reg:x2; val_offset:1848*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1848*FLEN/8, x3, x1, x4) + +inst_651: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8001; +op3val:0x8001; valaddr_reg:x2; val_offset:1851*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1851*FLEN/8, x3, x1, x4) + +inst_652: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8001; +op3val:0x2; valaddr_reg:x2; val_offset:1854*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1854*FLEN/8, x3, x1, x4) + +inst_653: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8001; +op3val:0x83fe; valaddr_reg:x2; val_offset:1857*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1857*FLEN/8, x3, x1, x4) + +inst_654: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8001; +op3val:0x3ff; valaddr_reg:x2; val_offset:1860*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1860*FLEN/8, x3, x1, x4) + +inst_655: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8001; +op3val:0x83ff; valaddr_reg:x2; val_offset:1863*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1863*FLEN/8, x3, x1, x4) + +inst_656: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8001; +op3val:0x400; valaddr_reg:x2; val_offset:1866*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1866*FLEN/8, x3, x1, x4) + +inst_657: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8001; +op3val:0x8400; valaddr_reg:x2; val_offset:1869*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1869*FLEN/8, x3, x1, x4) + +inst_658: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8001; +op3val:0x401; valaddr_reg:x2; val_offset:1872*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1872*FLEN/8, x3, x1, x4) + +inst_659: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8001; +op3val:0x8455; valaddr_reg:x2; val_offset:1875*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1875*FLEN/8, x3, x1, x4) + +inst_660: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8001; +op3val:0x7bff; valaddr_reg:x2; val_offset:1878*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1878*FLEN/8, x3, x1, x4) + +inst_661: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8001; +op3val:0xfbff; valaddr_reg:x2; val_offset:1881*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1881*FLEN/8, x3, x1, x4) + +inst_662: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8001; +op3val:0x7c00; valaddr_reg:x2; val_offset:1884*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1884*FLEN/8, x3, x1, x4) + +inst_663: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8001; +op3val:0xfc00; valaddr_reg:x2; val_offset:1887*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1887*FLEN/8, x3, x1, x4) + +inst_664: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8001; +op3val:0x7e00; valaddr_reg:x2; val_offset:1890*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1890*FLEN/8, x3, x1, x4) + +inst_665: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8001; +op3val:0xfe00; valaddr_reg:x2; val_offset:1893*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1893*FLEN/8, x3, x1, x4) + +inst_666: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8001; +op3val:0x7e01; valaddr_reg:x2; val_offset:1896*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1896*FLEN/8, x3, x1, x4) + +inst_667: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8001; +op3val:0xfe55; valaddr_reg:x2; val_offset:1899*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1899*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_6) + +inst_668: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8001; +op3val:0x7c01; valaddr_reg:x2; val_offset:1902*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1902*FLEN/8, x3, x1, x4) + +inst_669: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8001; +op3val:0xfd55; valaddr_reg:x2; val_offset:1905*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1905*FLEN/8, x3, x1, x4) + +inst_670: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8001; +op3val:0x3c00; valaddr_reg:x2; val_offset:1908*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1908*FLEN/8, x3, x1, x4) + +inst_671: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8001; +op3val:0xbc00; valaddr_reg:x2; val_offset:1911*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1911*FLEN/8, x3, x1, x4) + +inst_672: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x2; +op3val:0x0; valaddr_reg:x2; val_offset:1914*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1914*FLEN/8, x3, x1, x4) + +inst_673: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x2; +op3val:0x8000; valaddr_reg:x2; val_offset:1917*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1917*FLEN/8, x3, x1, x4) + +inst_674: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x2; +op3val:0x1; valaddr_reg:x2; val_offset:1920*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1920*FLEN/8, x3, x1, x4) + +inst_675: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x2; +op3val:0x8001; valaddr_reg:x2; val_offset:1923*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1923*FLEN/8, x3, x1, x4) + +inst_676: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x2; +op3val:0x2; valaddr_reg:x2; val_offset:1926*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1926*FLEN/8, x3, x1, x4) + +inst_677: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x2; +op3val:0x83fe; valaddr_reg:x2; val_offset:1929*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1929*FLEN/8, x3, x1, x4) + +inst_678: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x2; +op3val:0x3ff; valaddr_reg:x2; val_offset:1932*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1932*FLEN/8, x3, x1, x4) + +inst_679: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x2; +op3val:0x83ff; valaddr_reg:x2; val_offset:1935*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1935*FLEN/8, x3, x1, x4) + +inst_680: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x2; +op3val:0x400; valaddr_reg:x2; val_offset:1938*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1938*FLEN/8, x3, x1, x4) + +inst_681: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x2; +op3val:0x8400; valaddr_reg:x2; val_offset:1941*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1941*FLEN/8, x3, x1, x4) + +inst_682: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x2; +op3val:0x401; valaddr_reg:x2; val_offset:1944*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1944*FLEN/8, x3, x1, x4) + +inst_683: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x2; +op3val:0x8455; valaddr_reg:x2; val_offset:1947*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1947*FLEN/8, x3, x1, x4) + +inst_684: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x2; +op3val:0x7bff; valaddr_reg:x2; val_offset:1950*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1950*FLEN/8, x3, x1, x4) + +inst_685: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x2; +op3val:0xfbff; valaddr_reg:x2; val_offset:1953*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1953*FLEN/8, x3, x1, x4) + +inst_686: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x2; +op3val:0x7c00; valaddr_reg:x2; val_offset:1956*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1956*FLEN/8, x3, x1, x4) + +inst_687: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x2; +op3val:0xfc00; valaddr_reg:x2; val_offset:1959*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1959*FLEN/8, x3, x1, x4) + +inst_688: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x2; +op3val:0x7e00; valaddr_reg:x2; val_offset:1962*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1962*FLEN/8, x3, x1, x4) + +inst_689: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x2; +op3val:0xfe00; valaddr_reg:x2; val_offset:1965*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1965*FLEN/8, x3, x1, x4) + +inst_690: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x2; +op3val:0x7e01; valaddr_reg:x2; val_offset:1968*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1968*FLEN/8, x3, x1, x4) + +inst_691: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x2; +op3val:0xfe55; valaddr_reg:x2; val_offset:1971*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1971*FLEN/8, x3, x1, x4) + +inst_692: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x2; +op3val:0x7c01; valaddr_reg:x2; val_offset:1974*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1974*FLEN/8, x3, x1, x4) + +inst_693: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x2; +op3val:0xfd55; valaddr_reg:x2; val_offset:1977*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1977*FLEN/8, x3, x1, x4) + +inst_694: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x2; +op3val:0x3c00; valaddr_reg:x2; val_offset:1980*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1980*FLEN/8, x3, x1, x4) + +inst_695: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x2; +op3val:0xbc00; valaddr_reg:x2; val_offset:1983*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1983*FLEN/8, x3, x1, x4) + +inst_696: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x83fe; +op3val:0x0; valaddr_reg:x2; val_offset:1986*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1986*FLEN/8, x3, x1, x4) + +inst_697: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x83fe; +op3val:0x8000; valaddr_reg:x2; val_offset:1989*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1989*FLEN/8, x3, x1, x4) + +inst_698: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x83fe; +op3val:0x1; valaddr_reg:x2; val_offset:1992*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1992*FLEN/8, x3, x1, x4) + +inst_699: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x83fe; +op3val:0x8001; valaddr_reg:x2; val_offset:1995*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1995*FLEN/8, x3, x1, x4) + +inst_700: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x83fe; +op3val:0x2; valaddr_reg:x2; val_offset:1998*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 1998*FLEN/8, x3, x1, x4) + +inst_701: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x83fe; +op3val:0x83fe; valaddr_reg:x2; val_offset:2001*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2001*FLEN/8, x3, x1, x4) + +inst_702: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x83fe; +op3val:0x3ff; valaddr_reg:x2; val_offset:2004*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2004*FLEN/8, x3, x1, x4) + +inst_703: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x83fe; +op3val:0x83ff; valaddr_reg:x2; val_offset:2007*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2007*FLEN/8, x3, x1, x4) + +inst_704: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x83fe; +op3val:0x400; valaddr_reg:x2; val_offset:2010*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2010*FLEN/8, x3, x1, x4) + +inst_705: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x83fe; +op3val:0x8400; valaddr_reg:x2; val_offset:2013*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2013*FLEN/8, x3, x1, x4) + +inst_706: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x83fe; +op3val:0x401; valaddr_reg:x2; val_offset:2016*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2016*FLEN/8, x3, x1, x4) + +inst_707: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x83fe; +op3val:0x8455; valaddr_reg:x2; val_offset:2019*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2019*FLEN/8, x3, x1, x4) + +inst_708: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x83fe; +op3val:0x7bff; valaddr_reg:x2; val_offset:2022*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2022*FLEN/8, x3, x1, x4) + +inst_709: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x83fe; +op3val:0xfbff; valaddr_reg:x2; val_offset:2025*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2025*FLEN/8, x3, x1, x4) + +inst_710: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x83fe; +op3val:0x7c00; valaddr_reg:x2; val_offset:2028*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2028*FLEN/8, x3, x1, x4) + +inst_711: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x83fe; +op3val:0xfc00; valaddr_reg:x2; val_offset:2031*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2031*FLEN/8, x3, x1, x4) + +inst_712: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x83fe; +op3val:0x7e00; valaddr_reg:x2; val_offset:2034*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2034*FLEN/8, x3, x1, x4) + +inst_713: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x83fe; +op3val:0xfe00; valaddr_reg:x2; val_offset:2037*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2037*FLEN/8, x3, x1, x4) + +inst_714: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x83fe; +op3val:0x7e01; valaddr_reg:x2; val_offset:2040*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2040*FLEN/8, x3, x1, x4) + +inst_715: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x83fe; +op3val:0xfe55; valaddr_reg:x2; val_offset:2043*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2043*FLEN/8, x3, x1, x4) + +inst_716: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x83fe; +op3val:0x7c01; valaddr_reg:x2; val_offset:2046*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2046*FLEN/8, x3, x1, x4) + +inst_717: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x83fe; +op3val:0xfd55; valaddr_reg:x2; val_offset:2049*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2049*FLEN/8, x3, x1, x4) + +inst_718: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x83fe; +op3val:0x3c00; valaddr_reg:x2; val_offset:2052*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2052*FLEN/8, x3, x1, x4) + +inst_719: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x83fe; +op3val:0xbc00; valaddr_reg:x2; val_offset:2055*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2055*FLEN/8, x3, x1, x4) + +inst_720: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x3ff; +op3val:0x0; valaddr_reg:x2; val_offset:2058*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2058*FLEN/8, x3, x1, x4) + +inst_721: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x3ff; +op3val:0x8000; valaddr_reg:x2; val_offset:2061*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2061*FLEN/8, x3, x1, x4) + +inst_722: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x3ff; +op3val:0x1; valaddr_reg:x2; val_offset:2064*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2064*FLEN/8, x3, x1, x4) + +inst_723: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x3ff; +op3val:0x8001; valaddr_reg:x2; val_offset:2067*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2067*FLEN/8, x3, x1, x4) + +inst_724: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x3ff; +op3val:0x2; valaddr_reg:x2; val_offset:2070*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2070*FLEN/8, x3, x1, x4) + +inst_725: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x3ff; +op3val:0x83fe; valaddr_reg:x2; val_offset:2073*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2073*FLEN/8, x3, x1, x4) + +inst_726: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x3ff; +op3val:0x3ff; valaddr_reg:x2; val_offset:2076*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2076*FLEN/8, x3, x1, x4) + +inst_727: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x3ff; +op3val:0x83ff; valaddr_reg:x2; val_offset:2079*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2079*FLEN/8, x3, x1, x4) + +inst_728: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x3ff; +op3val:0x400; valaddr_reg:x2; val_offset:2082*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2082*FLEN/8, x3, x1, x4) + +inst_729: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x3ff; +op3val:0x8400; valaddr_reg:x2; val_offset:2085*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2085*FLEN/8, x3, x1, x4) + +inst_730: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x3ff; +op3val:0x401; valaddr_reg:x2; val_offset:2088*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2088*FLEN/8, x3, x1, x4) + +inst_731: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x3ff; +op3val:0x8455; valaddr_reg:x2; val_offset:2091*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2091*FLEN/8, x3, x1, x4) + +inst_732: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x3ff; +op3val:0x7bff; valaddr_reg:x2; val_offset:2094*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2094*FLEN/8, x3, x1, x4) + +inst_733: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x3ff; +op3val:0xfbff; valaddr_reg:x2; val_offset:2097*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2097*FLEN/8, x3, x1, x4) + +inst_734: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x3ff; +op3val:0x7c00; valaddr_reg:x2; val_offset:2100*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2100*FLEN/8, x3, x1, x4) + +inst_735: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x3ff; +op3val:0xfc00; valaddr_reg:x2; val_offset:2103*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2103*FLEN/8, x3, x1, x4) + +inst_736: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x3ff; +op3val:0x7e00; valaddr_reg:x2; val_offset:2106*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2106*FLEN/8, x3, x1, x4) + +inst_737: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x3ff; +op3val:0xfe00; valaddr_reg:x2; val_offset:2109*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2109*FLEN/8, x3, x1, x4) + +inst_738: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x3ff; +op3val:0x7e01; valaddr_reg:x2; val_offset:2112*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2112*FLEN/8, x3, x1, x4) + +inst_739: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x3ff; +op3val:0xfe55; valaddr_reg:x2; val_offset:2115*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2115*FLEN/8, x3, x1, x4) + +inst_740: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x3ff; +op3val:0x7c01; valaddr_reg:x2; val_offset:2118*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2118*FLEN/8, x3, x1, x4) + +inst_741: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x3ff; +op3val:0xfd55; valaddr_reg:x2; val_offset:2121*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2121*FLEN/8, x3, x1, x4) + +inst_742: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x3ff; +op3val:0x3c00; valaddr_reg:x2; val_offset:2124*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2124*FLEN/8, x3, x1, x4) + +inst_743: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x3ff; +op3val:0xbc00; valaddr_reg:x2; val_offset:2127*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2127*FLEN/8, x3, x1, x4) + +inst_744: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x83ff; +op3val:0x0; valaddr_reg:x2; val_offset:2130*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2130*FLEN/8, x3, x1, x4) + +inst_745: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x83ff; +op3val:0x8000; valaddr_reg:x2; val_offset:2133*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2133*FLEN/8, x3, x1, x4) + +inst_746: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x83ff; +op3val:0x1; valaddr_reg:x2; val_offset:2136*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2136*FLEN/8, x3, x1, x4) + +inst_747: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x83ff; +op3val:0x8001; valaddr_reg:x2; val_offset:2139*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2139*FLEN/8, x3, x1, x4) + +inst_748: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x83ff; +op3val:0x2; valaddr_reg:x2; val_offset:2142*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2142*FLEN/8, x3, x1, x4) + +inst_749: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x83ff; +op3val:0x83fe; valaddr_reg:x2; val_offset:2145*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2145*FLEN/8, x3, x1, x4) + +inst_750: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x83ff; +op3val:0x3ff; valaddr_reg:x2; val_offset:2148*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2148*FLEN/8, x3, x1, x4) + +inst_751: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x83ff; +op3val:0x83ff; valaddr_reg:x2; val_offset:2151*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2151*FLEN/8, x3, x1, x4) + +inst_752: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x83ff; +op3val:0x400; valaddr_reg:x2; val_offset:2154*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2154*FLEN/8, x3, x1, x4) + +inst_753: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x83ff; +op3val:0x8400; valaddr_reg:x2; val_offset:2157*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2157*FLEN/8, x3, x1, x4) + +inst_754: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x83ff; +op3val:0x401; valaddr_reg:x2; val_offset:2160*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2160*FLEN/8, x3, x1, x4) + +inst_755: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x83ff; +op3val:0x8455; valaddr_reg:x2; val_offset:2163*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2163*FLEN/8, x3, x1, x4) + +inst_756: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x83ff; +op3val:0x7bff; valaddr_reg:x2; val_offset:2166*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2166*FLEN/8, x3, x1, x4) + +inst_757: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x83ff; +op3val:0xfbff; valaddr_reg:x2; val_offset:2169*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2169*FLEN/8, x3, x1, x4) + +inst_758: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x83ff; +op3val:0x7c00; valaddr_reg:x2; val_offset:2172*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2172*FLEN/8, x3, x1, x4) + +inst_759: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x83ff; +op3val:0xfc00; valaddr_reg:x2; val_offset:2175*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2175*FLEN/8, x3, x1, x4) + +inst_760: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x83ff; +op3val:0x7e00; valaddr_reg:x2; val_offset:2178*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2178*FLEN/8, x3, x1, x4) + +inst_761: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x83ff; +op3val:0xfe00; valaddr_reg:x2; val_offset:2181*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2181*FLEN/8, x3, x1, x4) + +inst_762: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x83ff; +op3val:0x7e01; valaddr_reg:x2; val_offset:2184*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2184*FLEN/8, x3, x1, x4) + +inst_763: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x83ff; +op3val:0xfe55; valaddr_reg:x2; val_offset:2187*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2187*FLEN/8, x3, x1, x4) + +inst_764: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x83ff; +op3val:0x7c01; valaddr_reg:x2; val_offset:2190*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2190*FLEN/8, x3, x1, x4) + +inst_765: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x83ff; +op3val:0xfd55; valaddr_reg:x2; val_offset:2193*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2193*FLEN/8, x3, x1, x4) + +inst_766: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x83ff; +op3val:0x3c00; valaddr_reg:x2; val_offset:2196*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2196*FLEN/8, x3, x1, x4) + +inst_767: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x83ff; +op3val:0xbc00; valaddr_reg:x2; val_offset:2199*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2199*FLEN/8, x3, x1, x4) + +inst_768: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x400; +op3val:0x0; valaddr_reg:x2; val_offset:2202*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2202*FLEN/8, x3, x1, x4) + +inst_769: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x400; +op3val:0x8000; valaddr_reg:x2; val_offset:2205*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2205*FLEN/8, x3, x1, x4) + +inst_770: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x400; +op3val:0x1; valaddr_reg:x2; val_offset:2208*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2208*FLEN/8, x3, x1, x4) + +inst_771: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x400; +op3val:0x8001; valaddr_reg:x2; val_offset:2211*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2211*FLEN/8, x3, x1, x4) + +inst_772: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x400; +op3val:0x2; valaddr_reg:x2; val_offset:2214*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2214*FLEN/8, x3, x1, x4) + +inst_773: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x400; +op3val:0x83fe; valaddr_reg:x2; val_offset:2217*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2217*FLEN/8, x3, x1, x4) + +inst_774: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x400; +op3val:0x3ff; valaddr_reg:x2; val_offset:2220*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2220*FLEN/8, x3, x1, x4) + +inst_775: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x400; +op3val:0x83ff; valaddr_reg:x2; val_offset:2223*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2223*FLEN/8, x3, x1, x4) + +inst_776: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x400; +op3val:0x400; valaddr_reg:x2; val_offset:2226*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2226*FLEN/8, x3, x1, x4) + +inst_777: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x400; +op3val:0x8400; valaddr_reg:x2; val_offset:2229*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2229*FLEN/8, x3, x1, x4) + +inst_778: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x400; +op3val:0x401; valaddr_reg:x2; val_offset:2232*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2232*FLEN/8, x3, x1, x4) + +inst_779: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x400; +op3val:0x8455; valaddr_reg:x2; val_offset:2235*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2235*FLEN/8, x3, x1, x4) + +inst_780: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x400; +op3val:0x7bff; valaddr_reg:x2; val_offset:2238*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2238*FLEN/8, x3, x1, x4) + +inst_781: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x400; +op3val:0xfbff; valaddr_reg:x2; val_offset:2241*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2241*FLEN/8, x3, x1, x4) + +inst_782: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x400; +op3val:0x7c00; valaddr_reg:x2; val_offset:2244*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2244*FLEN/8, x3, x1, x4) + +inst_783: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x400; +op3val:0xfc00; valaddr_reg:x2; val_offset:2247*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2247*FLEN/8, x3, x1, x4) + +inst_784: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x400; +op3val:0x7e00; valaddr_reg:x2; val_offset:2250*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2250*FLEN/8, x3, x1, x4) + +inst_785: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x400; +op3val:0xfe00; valaddr_reg:x2; val_offset:2253*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2253*FLEN/8, x3, x1, x4) + +inst_786: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x400; +op3val:0x7e01; valaddr_reg:x2; val_offset:2256*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2256*FLEN/8, x3, x1, x4) + +inst_787: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x400; +op3val:0xfe55; valaddr_reg:x2; val_offset:2259*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2259*FLEN/8, x3, x1, x4) + +inst_788: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x400; +op3val:0x7c01; valaddr_reg:x2; val_offset:2262*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2262*FLEN/8, x3, x1, x4) + +inst_789: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x400; +op3val:0xfd55; valaddr_reg:x2; val_offset:2265*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2265*FLEN/8, x3, x1, x4) + +inst_790: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x400; +op3val:0x3c00; valaddr_reg:x2; val_offset:2268*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2268*FLEN/8, x3, x1, x4) + +inst_791: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x400; +op3val:0xbc00; valaddr_reg:x2; val_offset:2271*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2271*FLEN/8, x3, x1, x4) + +inst_792: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8400; +op3val:0x0; valaddr_reg:x2; val_offset:2274*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2274*FLEN/8, x3, x1, x4) + +inst_793: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8400; +op3val:0x8000; valaddr_reg:x2; val_offset:2277*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2277*FLEN/8, x3, x1, x4) + +inst_794: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8400; +op3val:0x1; valaddr_reg:x2; val_offset:2280*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2280*FLEN/8, x3, x1, x4) + +inst_795: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8400; +op3val:0x8001; valaddr_reg:x2; val_offset:2283*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2283*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_7) + +inst_796: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8400; +op3val:0x2; valaddr_reg:x2; val_offset:2286*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2286*FLEN/8, x3, x1, x4) + +inst_797: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8400; +op3val:0x83fe; valaddr_reg:x2; val_offset:2289*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2289*FLEN/8, x3, x1, x4) + +inst_798: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8400; +op3val:0x3ff; valaddr_reg:x2; val_offset:2292*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2292*FLEN/8, x3, x1, x4) + +inst_799: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8400; +op3val:0x83ff; valaddr_reg:x2; val_offset:2295*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2295*FLEN/8, x3, x1, x4) + +inst_800: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8400; +op3val:0x400; valaddr_reg:x2; val_offset:2298*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2298*FLEN/8, x3, x1, x4) + +inst_801: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8400; +op3val:0x8400; valaddr_reg:x2; val_offset:2301*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2301*FLEN/8, x3, x1, x4) + +inst_802: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8400; +op3val:0x401; valaddr_reg:x2; val_offset:2304*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2304*FLEN/8, x3, x1, x4) + +inst_803: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8400; +op3val:0x8455; valaddr_reg:x2; val_offset:2307*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2307*FLEN/8, x3, x1, x4) + +inst_804: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8400; +op3val:0x7bff; valaddr_reg:x2; val_offset:2310*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2310*FLEN/8, x3, x1, x4) + +inst_805: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8400; +op3val:0xfbff; valaddr_reg:x2; val_offset:2313*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2313*FLEN/8, x3, x1, x4) + +inst_806: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8400; +op3val:0x7c00; valaddr_reg:x2; val_offset:2316*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2316*FLEN/8, x3, x1, x4) + +inst_807: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8400; +op3val:0xfc00; valaddr_reg:x2; val_offset:2319*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2319*FLEN/8, x3, x1, x4) + +inst_808: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8400; +op3val:0x7e00; valaddr_reg:x2; val_offset:2322*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2322*FLEN/8, x3, x1, x4) + +inst_809: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8400; +op3val:0xfe00; valaddr_reg:x2; val_offset:2325*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2325*FLEN/8, x3, x1, x4) + +inst_810: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8400; +op3val:0x7e01; valaddr_reg:x2; val_offset:2328*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2328*FLEN/8, x3, x1, x4) + +inst_811: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8400; +op3val:0xfe55; valaddr_reg:x2; val_offset:2331*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2331*FLEN/8, x3, x1, x4) + +inst_812: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8400; +op3val:0x7c01; valaddr_reg:x2; val_offset:2334*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2334*FLEN/8, x3, x1, x4) + +inst_813: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8400; +op3val:0xfd55; valaddr_reg:x2; val_offset:2337*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2337*FLEN/8, x3, x1, x4) + +inst_814: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8400; +op3val:0x3c00; valaddr_reg:x2; val_offset:2340*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2340*FLEN/8, x3, x1, x4) + +inst_815: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8400; +op3val:0xbc00; valaddr_reg:x2; val_offset:2343*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2343*FLEN/8, x3, x1, x4) + +inst_816: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x401; +op3val:0x0; valaddr_reg:x2; val_offset:2346*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2346*FLEN/8, x3, x1, x4) + +inst_817: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x401; +op3val:0x8000; valaddr_reg:x2; val_offset:2349*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2349*FLEN/8, x3, x1, x4) + +inst_818: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x401; +op3val:0x1; valaddr_reg:x2; val_offset:2352*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2352*FLEN/8, x3, x1, x4) + +inst_819: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x401; +op3val:0x8001; valaddr_reg:x2; val_offset:2355*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2355*FLEN/8, x3, x1, x4) + +inst_820: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x401; +op3val:0x2; valaddr_reg:x2; val_offset:2358*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2358*FLEN/8, x3, x1, x4) + +inst_821: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x401; +op3val:0x83fe; valaddr_reg:x2; val_offset:2361*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2361*FLEN/8, x3, x1, x4) + +inst_822: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x401; +op3val:0x3ff; valaddr_reg:x2; val_offset:2364*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2364*FLEN/8, x3, x1, x4) + +inst_823: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x401; +op3val:0x83ff; valaddr_reg:x2; val_offset:2367*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2367*FLEN/8, x3, x1, x4) + +inst_824: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x401; +op3val:0x400; valaddr_reg:x2; val_offset:2370*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2370*FLEN/8, x3, x1, x4) + +inst_825: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x401; +op3val:0x8400; valaddr_reg:x2; val_offset:2373*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2373*FLEN/8, x3, x1, x4) + +inst_826: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x401; +op3val:0x401; valaddr_reg:x2; val_offset:2376*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2376*FLEN/8, x3, x1, x4) + +inst_827: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x401; +op3val:0x8455; valaddr_reg:x2; val_offset:2379*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2379*FLEN/8, x3, x1, x4) + +inst_828: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x401; +op3val:0x7bff; valaddr_reg:x2; val_offset:2382*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2382*FLEN/8, x3, x1, x4) + +inst_829: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x401; +op3val:0xfbff; valaddr_reg:x2; val_offset:2385*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2385*FLEN/8, x3, x1, x4) + +inst_830: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x401; +op3val:0x7c00; valaddr_reg:x2; val_offset:2388*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2388*FLEN/8, x3, x1, x4) + +inst_831: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x401; +op3val:0xfc00; valaddr_reg:x2; val_offset:2391*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2391*FLEN/8, x3, x1, x4) + +inst_832: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x401; +op3val:0x7e00; valaddr_reg:x2; val_offset:2394*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2394*FLEN/8, x3, x1, x4) + +inst_833: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x401; +op3val:0xfe00; valaddr_reg:x2; val_offset:2397*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2397*FLEN/8, x3, x1, x4) + +inst_834: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x401; +op3val:0x7e01; valaddr_reg:x2; val_offset:2400*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2400*FLEN/8, x3, x1, x4) + +inst_835: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x401; +op3val:0xfe55; valaddr_reg:x2; val_offset:2403*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2403*FLEN/8, x3, x1, x4) + +inst_836: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x401; +op3val:0x7c01; valaddr_reg:x2; val_offset:2406*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2406*FLEN/8, x3, x1, x4) + +inst_837: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x401; +op3val:0xfd55; valaddr_reg:x2; val_offset:2409*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2409*FLEN/8, x3, x1, x4) + +inst_838: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x401; +op3val:0x3c00; valaddr_reg:x2; val_offset:2412*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2412*FLEN/8, x3, x1, x4) + +inst_839: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x401; +op3val:0xbc00; valaddr_reg:x2; val_offset:2415*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2415*FLEN/8, x3, x1, x4) + +inst_840: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8455; +op3val:0x0; valaddr_reg:x2; val_offset:2418*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2418*FLEN/8, x3, x1, x4) + +inst_841: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8455; +op3val:0x8000; valaddr_reg:x2; val_offset:2421*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2421*FLEN/8, x3, x1, x4) + +inst_842: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8455; +op3val:0x1; valaddr_reg:x2; val_offset:2424*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2424*FLEN/8, x3, x1, x4) + +inst_843: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8455; +op3val:0x8001; valaddr_reg:x2; val_offset:2427*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2427*FLEN/8, x3, x1, x4) + +inst_844: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8455; +op3val:0x2; valaddr_reg:x2; val_offset:2430*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2430*FLEN/8, x3, x1, x4) + +inst_845: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8455; +op3val:0x83fe; valaddr_reg:x2; val_offset:2433*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2433*FLEN/8, x3, x1, x4) + +inst_846: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8455; +op3val:0x3ff; valaddr_reg:x2; val_offset:2436*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2436*FLEN/8, x3, x1, x4) + +inst_847: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8455; +op3val:0x83ff; valaddr_reg:x2; val_offset:2439*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2439*FLEN/8, x3, x1, x4) + +inst_848: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8455; +op3val:0x400; valaddr_reg:x2; val_offset:2442*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2442*FLEN/8, x3, x1, x4) + +inst_849: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8455; +op3val:0x8400; valaddr_reg:x2; val_offset:2445*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2445*FLEN/8, x3, x1, x4) + +inst_850: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8455; +op3val:0x401; valaddr_reg:x2; val_offset:2448*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2448*FLEN/8, x3, x1, x4) + +inst_851: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8455; +op3val:0x8455; valaddr_reg:x2; val_offset:2451*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2451*FLEN/8, x3, x1, x4) + +inst_852: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8455; +op3val:0x7bff; valaddr_reg:x2; val_offset:2454*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2454*FLEN/8, x3, x1, x4) + +inst_853: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8455; +op3val:0xfbff; valaddr_reg:x2; val_offset:2457*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2457*FLEN/8, x3, x1, x4) + +inst_854: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8455; +op3val:0x7c00; valaddr_reg:x2; val_offset:2460*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2460*FLEN/8, x3, x1, x4) + +inst_855: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8455; +op3val:0xfc00; valaddr_reg:x2; val_offset:2463*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2463*FLEN/8, x3, x1, x4) + +inst_856: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8455; +op3val:0x7e00; valaddr_reg:x2; val_offset:2466*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2466*FLEN/8, x3, x1, x4) + +inst_857: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8455; +op3val:0xfe00; valaddr_reg:x2; val_offset:2469*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2469*FLEN/8, x3, x1, x4) + +inst_858: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8455; +op3val:0x7e01; valaddr_reg:x2; val_offset:2472*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2472*FLEN/8, x3, x1, x4) + +inst_859: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8455; +op3val:0xfe55; valaddr_reg:x2; val_offset:2475*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2475*FLEN/8, x3, x1, x4) + +inst_860: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8455; +op3val:0x7c01; valaddr_reg:x2; val_offset:2478*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2478*FLEN/8, x3, x1, x4) + +inst_861: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8455; +op3val:0xfd55; valaddr_reg:x2; val_offset:2481*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2481*FLEN/8, x3, x1, x4) + +inst_862: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8455; +op3val:0x3c00; valaddr_reg:x2; val_offset:2484*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2484*FLEN/8, x3, x1, x4) + +inst_863: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x8455; +op3val:0xbc00; valaddr_reg:x2; val_offset:2487*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2487*FLEN/8, x3, x1, x4) + +inst_864: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7bff; +op3val:0x0; valaddr_reg:x2; val_offset:2490*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2490*FLEN/8, x3, x1, x4) + +inst_865: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7bff; +op3val:0x8000; valaddr_reg:x2; val_offset:2493*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2493*FLEN/8, x3, x1, x4) + +inst_866: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7bff; +op3val:0x1; valaddr_reg:x2; val_offset:2496*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2496*FLEN/8, x3, x1, x4) + +inst_867: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7bff; +op3val:0x8001; valaddr_reg:x2; val_offset:2499*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2499*FLEN/8, x3, x1, x4) + +inst_868: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7bff; +op3val:0x2; valaddr_reg:x2; val_offset:2502*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2502*FLEN/8, x3, x1, x4) + +inst_869: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7bff; +op3val:0x83fe; valaddr_reg:x2; val_offset:2505*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2505*FLEN/8, x3, x1, x4) + +inst_870: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7bff; +op3val:0x3ff; valaddr_reg:x2; val_offset:2508*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2508*FLEN/8, x3, x1, x4) + +inst_871: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7bff; +op3val:0x83ff; valaddr_reg:x2; val_offset:2511*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2511*FLEN/8, x3, x1, x4) + +inst_872: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7bff; +op3val:0x400; valaddr_reg:x2; val_offset:2514*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2514*FLEN/8, x3, x1, x4) + +inst_873: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7bff; +op3val:0x8400; valaddr_reg:x2; val_offset:2517*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2517*FLEN/8, x3, x1, x4) + +inst_874: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7bff; +op3val:0x401; valaddr_reg:x2; val_offset:2520*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2520*FLEN/8, x3, x1, x4) + +inst_875: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7bff; +op3val:0x8455; valaddr_reg:x2; val_offset:2523*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2523*FLEN/8, x3, x1, x4) + +inst_876: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7bff; +op3val:0x7bff; valaddr_reg:x2; val_offset:2526*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2526*FLEN/8, x3, x1, x4) + +inst_877: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7bff; +op3val:0xfbff; valaddr_reg:x2; val_offset:2529*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2529*FLEN/8, x3, x1, x4) + +inst_878: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7bff; +op3val:0x7c00; valaddr_reg:x2; val_offset:2532*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2532*FLEN/8, x3, x1, x4) + +inst_879: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7bff; +op3val:0xfc00; valaddr_reg:x2; val_offset:2535*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2535*FLEN/8, x3, x1, x4) + +inst_880: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7bff; +op3val:0x7e00; valaddr_reg:x2; val_offset:2538*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2538*FLEN/8, x3, x1, x4) + +inst_881: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7bff; +op3val:0xfe00; valaddr_reg:x2; val_offset:2541*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2541*FLEN/8, x3, x1, x4) + +inst_882: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7bff; +op3val:0x7e01; valaddr_reg:x2; val_offset:2544*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2544*FLEN/8, x3, x1, x4) + +inst_883: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7bff; +op3val:0xfe55; valaddr_reg:x2; val_offset:2547*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2547*FLEN/8, x3, x1, x4) + +inst_884: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7bff; +op3val:0x7c01; valaddr_reg:x2; val_offset:2550*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2550*FLEN/8, x3, x1, x4) + +inst_885: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7bff; +op3val:0xfd55; valaddr_reg:x2; val_offset:2553*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2553*FLEN/8, x3, x1, x4) + +inst_886: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7bff; +op3val:0x3c00; valaddr_reg:x2; val_offset:2556*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2556*FLEN/8, x3, x1, x4) + +inst_887: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7bff; +op3val:0xbc00; valaddr_reg:x2; val_offset:2559*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2559*FLEN/8, x3, x1, x4) + +inst_888: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfbff; +op3val:0x0; valaddr_reg:x2; val_offset:2562*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2562*FLEN/8, x3, x1, x4) + +inst_889: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfbff; +op3val:0x8000; valaddr_reg:x2; val_offset:2565*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2565*FLEN/8, x3, x1, x4) + +inst_890: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfbff; +op3val:0x1; valaddr_reg:x2; val_offset:2568*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2568*FLEN/8, x3, x1, x4) + +inst_891: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfbff; +op3val:0x8001; valaddr_reg:x2; val_offset:2571*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2571*FLEN/8, x3, x1, x4) + +inst_892: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfbff; +op3val:0x2; valaddr_reg:x2; val_offset:2574*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2574*FLEN/8, x3, x1, x4) + +inst_893: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfbff; +op3val:0x83fe; valaddr_reg:x2; val_offset:2577*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2577*FLEN/8, x3, x1, x4) + +inst_894: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfbff; +op3val:0x3ff; valaddr_reg:x2; val_offset:2580*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2580*FLEN/8, x3, x1, x4) + +inst_895: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfbff; +op3val:0x83ff; valaddr_reg:x2; val_offset:2583*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2583*FLEN/8, x3, x1, x4) + +inst_896: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfbff; +op3val:0x400; valaddr_reg:x2; val_offset:2586*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2586*FLEN/8, x3, x1, x4) + +inst_897: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfbff; +op3val:0x8400; valaddr_reg:x2; val_offset:2589*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2589*FLEN/8, x3, x1, x4) + +inst_898: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfbff; +op3val:0x401; valaddr_reg:x2; val_offset:2592*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2592*FLEN/8, x3, x1, x4) + +inst_899: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfbff; +op3val:0x8455; valaddr_reg:x2; val_offset:2595*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2595*FLEN/8, x3, x1, x4) + +inst_900: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfbff; +op3val:0x7bff; valaddr_reg:x2; val_offset:2598*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2598*FLEN/8, x3, x1, x4) + +inst_901: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfbff; +op3val:0xfbff; valaddr_reg:x2; val_offset:2601*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2601*FLEN/8, x3, x1, x4) + +inst_902: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfbff; +op3val:0x7c00; valaddr_reg:x2; val_offset:2604*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2604*FLEN/8, x3, x1, x4) + +inst_903: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfbff; +op3val:0xfc00; valaddr_reg:x2; val_offset:2607*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2607*FLEN/8, x3, x1, x4) + +inst_904: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfbff; +op3val:0x7e00; valaddr_reg:x2; val_offset:2610*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2610*FLEN/8, x3, x1, x4) + +inst_905: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfbff; +op3val:0xfe00; valaddr_reg:x2; val_offset:2613*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2613*FLEN/8, x3, x1, x4) + +inst_906: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfbff; +op3val:0x7e01; valaddr_reg:x2; val_offset:2616*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2616*FLEN/8, x3, x1, x4) + +inst_907: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfbff; +op3val:0xfe55; valaddr_reg:x2; val_offset:2619*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2619*FLEN/8, x3, x1, x4) + +inst_908: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfbff; +op3val:0x7c01; valaddr_reg:x2; val_offset:2622*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2622*FLEN/8, x3, x1, x4) + +inst_909: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfbff; +op3val:0xfd55; valaddr_reg:x2; val_offset:2625*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2625*FLEN/8, x3, x1, x4) + +inst_910: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfbff; +op3val:0x3c00; valaddr_reg:x2; val_offset:2628*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2628*FLEN/8, x3, x1, x4) + +inst_911: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfbff; +op3val:0xbc00; valaddr_reg:x2; val_offset:2631*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2631*FLEN/8, x3, x1, x4) + +inst_912: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7c00; +op3val:0x0; valaddr_reg:x2; val_offset:2634*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2634*FLEN/8, x3, x1, x4) + +inst_913: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7c00; +op3val:0x8000; valaddr_reg:x2; val_offset:2637*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2637*FLEN/8, x3, x1, x4) + +inst_914: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7c00; +op3val:0x1; valaddr_reg:x2; val_offset:2640*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2640*FLEN/8, x3, x1, x4) + +inst_915: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7c00; +op3val:0x8001; valaddr_reg:x2; val_offset:2643*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2643*FLEN/8, x3, x1, x4) + +inst_916: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7c00; +op3val:0x2; valaddr_reg:x2; val_offset:2646*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2646*FLEN/8, x3, x1, x4) + +inst_917: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7c00; +op3val:0x83fe; valaddr_reg:x2; val_offset:2649*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2649*FLEN/8, x3, x1, x4) + +inst_918: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7c00; +op3val:0x3ff; valaddr_reg:x2; val_offset:2652*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2652*FLEN/8, x3, x1, x4) + +inst_919: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7c00; +op3val:0x83ff; valaddr_reg:x2; val_offset:2655*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2655*FLEN/8, x3, x1, x4) + +inst_920: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7c00; +op3val:0x400; valaddr_reg:x2; val_offset:2658*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2658*FLEN/8, x3, x1, x4) + +inst_921: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7c00; +op3val:0x8400; valaddr_reg:x2; val_offset:2661*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2661*FLEN/8, x3, x1, x4) + +inst_922: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7c00; +op3val:0x401; valaddr_reg:x2; val_offset:2664*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2664*FLEN/8, x3, x1, x4) + +inst_923: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7c00; +op3val:0x8455; valaddr_reg:x2; val_offset:2667*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2667*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_8) + +inst_924: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7c00; +op3val:0x7bff; valaddr_reg:x2; val_offset:2670*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2670*FLEN/8, x3, x1, x4) + +inst_925: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7c00; +op3val:0xfbff; valaddr_reg:x2; val_offset:2673*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2673*FLEN/8, x3, x1, x4) + +inst_926: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7c00; +op3val:0x7c00; valaddr_reg:x2; val_offset:2676*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2676*FLEN/8, x3, x1, x4) + +inst_927: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7c00; +op3val:0xfc00; valaddr_reg:x2; val_offset:2679*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2679*FLEN/8, x3, x1, x4) + +inst_928: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7c00; +op3val:0x7e00; valaddr_reg:x2; val_offset:2682*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2682*FLEN/8, x3, x1, x4) + +inst_929: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7c00; +op3val:0xfe00; valaddr_reg:x2; val_offset:2685*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2685*FLEN/8, x3, x1, x4) + +inst_930: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7c00; +op3val:0x7e01; valaddr_reg:x2; val_offset:2688*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2688*FLEN/8, x3, x1, x4) + +inst_931: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7c00; +op3val:0xfe55; valaddr_reg:x2; val_offset:2691*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2691*FLEN/8, x3, x1, x4) + +inst_932: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7c00; +op3val:0x7c01; valaddr_reg:x2; val_offset:2694*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2694*FLEN/8, x3, x1, x4) + +inst_933: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7c00; +op3val:0xfd55; valaddr_reg:x2; val_offset:2697*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2697*FLEN/8, x3, x1, x4) + +inst_934: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7c00; +op3val:0x3c00; valaddr_reg:x2; val_offset:2700*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2700*FLEN/8, x3, x1, x4) + +inst_935: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7c00; +op3val:0xbc00; valaddr_reg:x2; val_offset:2703*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2703*FLEN/8, x3, x1, x4) + +inst_936: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfc00; +op3val:0x0; valaddr_reg:x2; val_offset:2706*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2706*FLEN/8, x3, x1, x4) + +inst_937: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfc00; +op3val:0x8000; valaddr_reg:x2; val_offset:2709*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2709*FLEN/8, x3, x1, x4) + +inst_938: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfc00; +op3val:0x1; valaddr_reg:x2; val_offset:2712*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2712*FLEN/8, x3, x1, x4) + +inst_939: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfc00; +op3val:0x8001; valaddr_reg:x2; val_offset:2715*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2715*FLEN/8, x3, x1, x4) + +inst_940: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfc00; +op3val:0x2; valaddr_reg:x2; val_offset:2718*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2718*FLEN/8, x3, x1, x4) + +inst_941: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfc00; +op3val:0x83fe; valaddr_reg:x2; val_offset:2721*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2721*FLEN/8, x3, x1, x4) + +inst_942: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfc00; +op3val:0x3ff; valaddr_reg:x2; val_offset:2724*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2724*FLEN/8, x3, x1, x4) + +inst_943: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfc00; +op3val:0x83ff; valaddr_reg:x2; val_offset:2727*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2727*FLEN/8, x3, x1, x4) + +inst_944: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfc00; +op3val:0x400; valaddr_reg:x2; val_offset:2730*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2730*FLEN/8, x3, x1, x4) + +inst_945: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfc00; +op3val:0x8400; valaddr_reg:x2; val_offset:2733*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2733*FLEN/8, x3, x1, x4) + +inst_946: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfc00; +op3val:0x401; valaddr_reg:x2; val_offset:2736*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2736*FLEN/8, x3, x1, x4) + +inst_947: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfc00; +op3val:0x8455; valaddr_reg:x2; val_offset:2739*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2739*FLEN/8, x3, x1, x4) + +inst_948: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfc00; +op3val:0x7bff; valaddr_reg:x2; val_offset:2742*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2742*FLEN/8, x3, x1, x4) + +inst_949: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfc00; +op3val:0xfbff; valaddr_reg:x2; val_offset:2745*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2745*FLEN/8, x3, x1, x4) + +inst_950: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfc00; +op3val:0x7c00; valaddr_reg:x2; val_offset:2748*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2748*FLEN/8, x3, x1, x4) + +inst_951: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfc00; +op3val:0xfc00; valaddr_reg:x2; val_offset:2751*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2751*FLEN/8, x3, x1, x4) + +inst_952: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfc00; +op3val:0x7e00; valaddr_reg:x2; val_offset:2754*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2754*FLEN/8, x3, x1, x4) + +inst_953: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfc00; +op3val:0xfe00; valaddr_reg:x2; val_offset:2757*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2757*FLEN/8, x3, x1, x4) + +inst_954: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfc00; +op3val:0x7e01; valaddr_reg:x2; val_offset:2760*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2760*FLEN/8, x3, x1, x4) + +inst_955: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfc00; +op3val:0xfe55; valaddr_reg:x2; val_offset:2763*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2763*FLEN/8, x3, x1, x4) + +inst_956: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfc00; +op3val:0x7c01; valaddr_reg:x2; val_offset:2766*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2766*FLEN/8, x3, x1, x4) + +inst_957: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfc00; +op3val:0xfd55; valaddr_reg:x2; val_offset:2769*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2769*FLEN/8, x3, x1, x4) + +inst_958: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfc00; +op3val:0x3c00; valaddr_reg:x2; val_offset:2772*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2772*FLEN/8, x3, x1, x4) + +inst_959: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfc00; +op3val:0xbc00; valaddr_reg:x2; val_offset:2775*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2775*FLEN/8, x3, x1, x4) + +inst_960: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7e00; +op3val:0x0; valaddr_reg:x2; val_offset:2778*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2778*FLEN/8, x3, x1, x4) + +inst_961: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7e00; +op3val:0x8000; valaddr_reg:x2; val_offset:2781*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2781*FLEN/8, x3, x1, x4) + +inst_962: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7e00; +op3val:0x1; valaddr_reg:x2; val_offset:2784*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2784*FLEN/8, x3, x1, x4) + +inst_963: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7e00; +op3val:0x8001; valaddr_reg:x2; val_offset:2787*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2787*FLEN/8, x3, x1, x4) + +inst_964: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7e00; +op3val:0x2; valaddr_reg:x2; val_offset:2790*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2790*FLEN/8, x3, x1, x4) + +inst_965: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7e00; +op3val:0x83fe; valaddr_reg:x2; val_offset:2793*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2793*FLEN/8, x3, x1, x4) + +inst_966: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7e00; +op3val:0x3ff; valaddr_reg:x2; val_offset:2796*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2796*FLEN/8, x3, x1, x4) + +inst_967: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7e00; +op3val:0x83ff; valaddr_reg:x2; val_offset:2799*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2799*FLEN/8, x3, x1, x4) + +inst_968: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7e00; +op3val:0x400; valaddr_reg:x2; val_offset:2802*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2802*FLEN/8, x3, x1, x4) + +inst_969: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7e00; +op3val:0x8400; valaddr_reg:x2; val_offset:2805*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2805*FLEN/8, x3, x1, x4) + +inst_970: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7e00; +op3val:0x401; valaddr_reg:x2; val_offset:2808*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2808*FLEN/8, x3, x1, x4) + +inst_971: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7e00; +op3val:0x8455; valaddr_reg:x2; val_offset:2811*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2811*FLEN/8, x3, x1, x4) + +inst_972: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7e00; +op3val:0x7bff; valaddr_reg:x2; val_offset:2814*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2814*FLEN/8, x3, x1, x4) + +inst_973: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7e00; +op3val:0xfbff; valaddr_reg:x2; val_offset:2817*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2817*FLEN/8, x3, x1, x4) + +inst_974: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7e00; +op3val:0x7c00; valaddr_reg:x2; val_offset:2820*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2820*FLEN/8, x3, x1, x4) + +inst_975: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7e00; +op3val:0xfc00; valaddr_reg:x2; val_offset:2823*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2823*FLEN/8, x3, x1, x4) + +inst_976: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7e00; +op3val:0x7e00; valaddr_reg:x2; val_offset:2826*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2826*FLEN/8, x3, x1, x4) + +inst_977: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7e00; +op3val:0xfe00; valaddr_reg:x2; val_offset:2829*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2829*FLEN/8, x3, x1, x4) + +inst_978: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7e00; +op3val:0x7e01; valaddr_reg:x2; val_offset:2832*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2832*FLEN/8, x3, x1, x4) + +inst_979: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7e00; +op3val:0xfe55; valaddr_reg:x2; val_offset:2835*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2835*FLEN/8, x3, x1, x4) + +inst_980: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7e00; +op3val:0x7c01; valaddr_reg:x2; val_offset:2838*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2838*FLEN/8, x3, x1, x4) + +inst_981: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7e00; +op3val:0xfd55; valaddr_reg:x2; val_offset:2841*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2841*FLEN/8, x3, x1, x4) + +inst_982: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7e00; +op3val:0x3c00; valaddr_reg:x2; val_offset:2844*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2844*FLEN/8, x3, x1, x4) + +inst_983: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7e00; +op3val:0xbc00; valaddr_reg:x2; val_offset:2847*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2847*FLEN/8, x3, x1, x4) + +inst_984: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfe00; +op3val:0x0; valaddr_reg:x2; val_offset:2850*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2850*FLEN/8, x3, x1, x4) + +inst_985: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfe00; +op3val:0x8000; valaddr_reg:x2; val_offset:2853*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2853*FLEN/8, x3, x1, x4) + +inst_986: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfe00; +op3val:0x1; valaddr_reg:x2; val_offset:2856*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2856*FLEN/8, x3, x1, x4) + +inst_987: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfe00; +op3val:0x8001; valaddr_reg:x2; val_offset:2859*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2859*FLEN/8, x3, x1, x4) + +inst_988: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfe00; +op3val:0x2; valaddr_reg:x2; val_offset:2862*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2862*FLEN/8, x3, x1, x4) + +inst_989: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfe00; +op3val:0x83fe; valaddr_reg:x2; val_offset:2865*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2865*FLEN/8, x3, x1, x4) + +inst_990: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfe00; +op3val:0x3ff; valaddr_reg:x2; val_offset:2868*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2868*FLEN/8, x3, x1, x4) + +inst_991: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfe00; +op3val:0x83ff; valaddr_reg:x2; val_offset:2871*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2871*FLEN/8, x3, x1, x4) + +inst_992: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfe00; +op3val:0x400; valaddr_reg:x2; val_offset:2874*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2874*FLEN/8, x3, x1, x4) + +inst_993: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfe00; +op3val:0x8400; valaddr_reg:x2; val_offset:2877*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2877*FLEN/8, x3, x1, x4) + +inst_994: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfe00; +op3val:0x401; valaddr_reg:x2; val_offset:2880*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2880*FLEN/8, x3, x1, x4) + +inst_995: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfe00; +op3val:0x8455; valaddr_reg:x2; val_offset:2883*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2883*FLEN/8, x3, x1, x4) + +inst_996: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfe00; +op3val:0x7bff; valaddr_reg:x2; val_offset:2886*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2886*FLEN/8, x3, x1, x4) + +inst_997: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfe00; +op3val:0xfbff; valaddr_reg:x2; val_offset:2889*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2889*FLEN/8, x3, x1, x4) + +inst_998: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfe00; +op3val:0x7c00; valaddr_reg:x2; val_offset:2892*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2892*FLEN/8, x3, x1, x4) + +inst_999: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfe00; +op3val:0xfc00; valaddr_reg:x2; val_offset:2895*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2895*FLEN/8, x3, x1, x4) + +inst_1000: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfe00; +op3val:0x7e00; valaddr_reg:x2; val_offset:2898*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2898*FLEN/8, x3, x1, x4) + +inst_1001: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfe00; +op3val:0xfe00; valaddr_reg:x2; val_offset:2901*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2901*FLEN/8, x3, x1, x4) + +inst_1002: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfe00; +op3val:0x7e01; valaddr_reg:x2; val_offset:2904*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2904*FLEN/8, x3, x1, x4) + +inst_1003: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfe00; +op3val:0xfe55; valaddr_reg:x2; val_offset:2907*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2907*FLEN/8, x3, x1, x4) + +inst_1004: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfe00; +op3val:0x7c01; valaddr_reg:x2; val_offset:2910*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2910*FLEN/8, x3, x1, x4) + +inst_1005: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfe00; +op3val:0xfd55; valaddr_reg:x2; val_offset:2913*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2913*FLEN/8, x3, x1, x4) + +inst_1006: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfe00; +op3val:0x3c00; valaddr_reg:x2; val_offset:2916*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2916*FLEN/8, x3, x1, x4) + +inst_1007: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfe00; +op3val:0xbc00; valaddr_reg:x2; val_offset:2919*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2919*FLEN/8, x3, x1, x4) + +inst_1008: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7e01; +op3val:0x0; valaddr_reg:x2; val_offset:2922*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2922*FLEN/8, x3, x1, x4) + +inst_1009: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7e01; +op3val:0x8000; valaddr_reg:x2; val_offset:2925*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2925*FLEN/8, x3, x1, x4) + +inst_1010: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7e01; +op3val:0x1; valaddr_reg:x2; val_offset:2928*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2928*FLEN/8, x3, x1, x4) + +inst_1011: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7e01; +op3val:0x8001; valaddr_reg:x2; val_offset:2931*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2931*FLEN/8, x3, x1, x4) + +inst_1012: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7e01; +op3val:0x2; valaddr_reg:x2; val_offset:2934*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2934*FLEN/8, x3, x1, x4) + +inst_1013: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7e01; +op3val:0x83fe; valaddr_reg:x2; val_offset:2937*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2937*FLEN/8, x3, x1, x4) + +inst_1014: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7e01; +op3val:0x3ff; valaddr_reg:x2; val_offset:2940*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2940*FLEN/8, x3, x1, x4) + +inst_1015: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7e01; +op3val:0x83ff; valaddr_reg:x2; val_offset:2943*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2943*FLEN/8, x3, x1, x4) + +inst_1016: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7e01; +op3val:0x400; valaddr_reg:x2; val_offset:2946*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2946*FLEN/8, x3, x1, x4) + +inst_1017: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7e01; +op3val:0x8400; valaddr_reg:x2; val_offset:2949*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2949*FLEN/8, x3, x1, x4) + +inst_1018: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7e01; +op3val:0x401; valaddr_reg:x2; val_offset:2952*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2952*FLEN/8, x3, x1, x4) + +inst_1019: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7e01; +op3val:0x8455; valaddr_reg:x2; val_offset:2955*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2955*FLEN/8, x3, x1, x4) + +inst_1020: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7e01; +op3val:0x7bff; valaddr_reg:x2; val_offset:2958*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2958*FLEN/8, x3, x1, x4) + +inst_1021: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7e01; +op3val:0xfbff; valaddr_reg:x2; val_offset:2961*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2961*FLEN/8, x3, x1, x4) + +inst_1022: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7e01; +op3val:0x7c00; valaddr_reg:x2; val_offset:2964*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2964*FLEN/8, x3, x1, x4) + +inst_1023: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7e01; +op3val:0xfc00; valaddr_reg:x2; val_offset:2967*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2967*FLEN/8, x3, x1, x4) + +inst_1024: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7e01; +op3val:0x7e00; valaddr_reg:x2; val_offset:2970*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2970*FLEN/8, x3, x1, x4) + +inst_1025: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7e01; +op3val:0xfe00; valaddr_reg:x2; val_offset:2973*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2973*FLEN/8, x3, x1, x4) + +inst_1026: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7e01; +op3val:0x7e01; valaddr_reg:x2; val_offset:2976*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2976*FLEN/8, x3, x1, x4) + +inst_1027: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7e01; +op3val:0xfe55; valaddr_reg:x2; val_offset:2979*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2979*FLEN/8, x3, x1, x4) + +inst_1028: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7e01; +op3val:0x7c01; valaddr_reg:x2; val_offset:2982*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2982*FLEN/8, x3, x1, x4) + +inst_1029: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7e01; +op3val:0xfd55; valaddr_reg:x2; val_offset:2985*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2985*FLEN/8, x3, x1, x4) + +inst_1030: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7e01; +op3val:0x3c00; valaddr_reg:x2; val_offset:2988*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2988*FLEN/8, x3, x1, x4) + +inst_1031: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7e01; +op3val:0xbc00; valaddr_reg:x2; val_offset:2991*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2991*FLEN/8, x3, x1, x4) + +inst_1032: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfe55; +op3val:0x0; valaddr_reg:x2; val_offset:2994*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2994*FLEN/8, x3, x1, x4) + +inst_1033: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfe55; +op3val:0x8000; valaddr_reg:x2; val_offset:2997*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 2997*FLEN/8, x3, x1, x4) + +inst_1034: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfe55; +op3val:0x1; valaddr_reg:x2; val_offset:3000*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3000*FLEN/8, x3, x1, x4) + +inst_1035: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfe55; +op3val:0x8001; valaddr_reg:x2; val_offset:3003*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3003*FLEN/8, x3, x1, x4) + +inst_1036: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfe55; +op3val:0x2; valaddr_reg:x2; val_offset:3006*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3006*FLEN/8, x3, x1, x4) + +inst_1037: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfe55; +op3val:0x83fe; valaddr_reg:x2; val_offset:3009*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3009*FLEN/8, x3, x1, x4) + +inst_1038: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfe55; +op3val:0x3ff; valaddr_reg:x2; val_offset:3012*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3012*FLEN/8, x3, x1, x4) + +inst_1039: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfe55; +op3val:0x83ff; valaddr_reg:x2; val_offset:3015*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3015*FLEN/8, x3, x1, x4) + +inst_1040: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfe55; +op3val:0x400; valaddr_reg:x2; val_offset:3018*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3018*FLEN/8, x3, x1, x4) + +inst_1041: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfe55; +op3val:0x8400; valaddr_reg:x2; val_offset:3021*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3021*FLEN/8, x3, x1, x4) + +inst_1042: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfe55; +op3val:0x401; valaddr_reg:x2; val_offset:3024*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3024*FLEN/8, x3, x1, x4) + +inst_1043: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfe55; +op3val:0x8455; valaddr_reg:x2; val_offset:3027*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3027*FLEN/8, x3, x1, x4) + +inst_1044: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfe55; +op3val:0x7bff; valaddr_reg:x2; val_offset:3030*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3030*FLEN/8, x3, x1, x4) + +inst_1045: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfe55; +op3val:0xfbff; valaddr_reg:x2; val_offset:3033*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3033*FLEN/8, x3, x1, x4) + +inst_1046: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfe55; +op3val:0x7c00; valaddr_reg:x2; val_offset:3036*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3036*FLEN/8, x3, x1, x4) + +inst_1047: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfe55; +op3val:0xfc00; valaddr_reg:x2; val_offset:3039*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3039*FLEN/8, x3, x1, x4) + +inst_1048: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfe55; +op3val:0x7e00; valaddr_reg:x2; val_offset:3042*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3042*FLEN/8, x3, x1, x4) + +inst_1049: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfe55; +op3val:0xfe00; valaddr_reg:x2; val_offset:3045*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3045*FLEN/8, x3, x1, x4) + +inst_1050: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfe55; +op3val:0x7e01; valaddr_reg:x2; val_offset:3048*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3048*FLEN/8, x3, x1, x4) + +inst_1051: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfe55; +op3val:0xfe55; valaddr_reg:x2; val_offset:3051*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3051*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_9) + +inst_1052: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfe55; +op3val:0x7c01; valaddr_reg:x2; val_offset:3054*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3054*FLEN/8, x3, x1, x4) + +inst_1053: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfe55; +op3val:0xfd55; valaddr_reg:x2; val_offset:3057*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3057*FLEN/8, x3, x1, x4) + +inst_1054: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfe55; +op3val:0x3c00; valaddr_reg:x2; val_offset:3060*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3060*FLEN/8, x3, x1, x4) + +inst_1055: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfe55; +op3val:0xbc00; valaddr_reg:x2; val_offset:3063*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3063*FLEN/8, x3, x1, x4) + +inst_1056: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7c01; +op3val:0x0; valaddr_reg:x2; val_offset:3066*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3066*FLEN/8, x3, x1, x4) + +inst_1057: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7c01; +op3val:0x8000; valaddr_reg:x2; val_offset:3069*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3069*FLEN/8, x3, x1, x4) + +inst_1058: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7c01; +op3val:0x1; valaddr_reg:x2; val_offset:3072*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3072*FLEN/8, x3, x1, x4) + +inst_1059: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7c01; +op3val:0x8001; valaddr_reg:x2; val_offset:3075*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3075*FLEN/8, x3, x1, x4) + +inst_1060: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7c01; +op3val:0x2; valaddr_reg:x2; val_offset:3078*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3078*FLEN/8, x3, x1, x4) + +inst_1061: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7c01; +op3val:0x83fe; valaddr_reg:x2; val_offset:3081*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3081*FLEN/8, x3, x1, x4) + +inst_1062: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7c01; +op3val:0x3ff; valaddr_reg:x2; val_offset:3084*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3084*FLEN/8, x3, x1, x4) + +inst_1063: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7c01; +op3val:0x83ff; valaddr_reg:x2; val_offset:3087*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3087*FLEN/8, x3, x1, x4) + +inst_1064: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7c01; +op3val:0x400; valaddr_reg:x2; val_offset:3090*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3090*FLEN/8, x3, x1, x4) + +inst_1065: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7c01; +op3val:0x8400; valaddr_reg:x2; val_offset:3093*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3093*FLEN/8, x3, x1, x4) + +inst_1066: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7c01; +op3val:0x401; valaddr_reg:x2; val_offset:3096*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3096*FLEN/8, x3, x1, x4) + +inst_1067: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7c01; +op3val:0x8455; valaddr_reg:x2; val_offset:3099*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3099*FLEN/8, x3, x1, x4) + +inst_1068: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7c01; +op3val:0x7bff; valaddr_reg:x2; val_offset:3102*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3102*FLEN/8, x3, x1, x4) + +inst_1069: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7c01; +op3val:0xfbff; valaddr_reg:x2; val_offset:3105*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3105*FLEN/8, x3, x1, x4) + +inst_1070: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7c01; +op3val:0x7c00; valaddr_reg:x2; val_offset:3108*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3108*FLEN/8, x3, x1, x4) + +inst_1071: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7c01; +op3val:0xfc00; valaddr_reg:x2; val_offset:3111*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3111*FLEN/8, x3, x1, x4) + +inst_1072: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7c01; +op3val:0x7e00; valaddr_reg:x2; val_offset:3114*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3114*FLEN/8, x3, x1, x4) + +inst_1073: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7c01; +op3val:0xfe00; valaddr_reg:x2; val_offset:3117*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3117*FLEN/8, x3, x1, x4) + +inst_1074: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7c01; +op3val:0x7e01; valaddr_reg:x2; val_offset:3120*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3120*FLEN/8, x3, x1, x4) + +inst_1075: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7c01; +op3val:0xfe55; valaddr_reg:x2; val_offset:3123*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3123*FLEN/8, x3, x1, x4) + +inst_1076: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7c01; +op3val:0x7c01; valaddr_reg:x2; val_offset:3126*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3126*FLEN/8, x3, x1, x4) + +inst_1077: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7c01; +op3val:0xfd55; valaddr_reg:x2; val_offset:3129*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3129*FLEN/8, x3, x1, x4) + +inst_1078: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7c01; +op3val:0x3c00; valaddr_reg:x2; val_offset:3132*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3132*FLEN/8, x3, x1, x4) + +inst_1079: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x7c01; +op3val:0xbc00; valaddr_reg:x2; val_offset:3135*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3135*FLEN/8, x3, x1, x4) + +inst_1080: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfd55; +op3val:0x0; valaddr_reg:x2; val_offset:3138*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3138*FLEN/8, x3, x1, x4) + +inst_1081: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfd55; +op3val:0x8000; valaddr_reg:x2; val_offset:3141*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3141*FLEN/8, x3, x1, x4) + +inst_1082: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfd55; +op3val:0x1; valaddr_reg:x2; val_offset:3144*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3144*FLEN/8, x3, x1, x4) + +inst_1083: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfd55; +op3val:0x8001; valaddr_reg:x2; val_offset:3147*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3147*FLEN/8, x3, x1, x4) + +inst_1084: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfd55; +op3val:0x2; valaddr_reg:x2; val_offset:3150*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3150*FLEN/8, x3, x1, x4) + +inst_1085: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfd55; +op3val:0x83fe; valaddr_reg:x2; val_offset:3153*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3153*FLEN/8, x3, x1, x4) + +inst_1086: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfd55; +op3val:0x3ff; valaddr_reg:x2; val_offset:3156*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3156*FLEN/8, x3, x1, x4) + +inst_1087: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfd55; +op3val:0x83ff; valaddr_reg:x2; val_offset:3159*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3159*FLEN/8, x3, x1, x4) + +inst_1088: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfd55; +op3val:0x400; valaddr_reg:x2; val_offset:3162*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3162*FLEN/8, x3, x1, x4) + +inst_1089: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfd55; +op3val:0x8400; valaddr_reg:x2; val_offset:3165*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3165*FLEN/8, x3, x1, x4) + +inst_1090: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfd55; +op3val:0x401; valaddr_reg:x2; val_offset:3168*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3168*FLEN/8, x3, x1, x4) + +inst_1091: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfd55; +op3val:0x8455; valaddr_reg:x2; val_offset:3171*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3171*FLEN/8, x3, x1, x4) + +inst_1092: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfd55; +op3val:0x7bff; valaddr_reg:x2; val_offset:3174*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3174*FLEN/8, x3, x1, x4) + +inst_1093: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfd55; +op3val:0xfbff; valaddr_reg:x2; val_offset:3177*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3177*FLEN/8, x3, x1, x4) + +inst_1094: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfd55; +op3val:0x7c00; valaddr_reg:x2; val_offset:3180*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3180*FLEN/8, x3, x1, x4) + +inst_1095: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfd55; +op3val:0xfc00; valaddr_reg:x2; val_offset:3183*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3183*FLEN/8, x3, x1, x4) + +inst_1096: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfd55; +op3val:0x7e00; valaddr_reg:x2; val_offset:3186*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3186*FLEN/8, x3, x1, x4) + +inst_1097: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfd55; +op3val:0xfe00; valaddr_reg:x2; val_offset:3189*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3189*FLEN/8, x3, x1, x4) + +inst_1098: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfd55; +op3val:0x7e01; valaddr_reg:x2; val_offset:3192*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3192*FLEN/8, x3, x1, x4) + +inst_1099: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfd55; +op3val:0xfe55; valaddr_reg:x2; val_offset:3195*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3195*FLEN/8, x3, x1, x4) + +inst_1100: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfd55; +op3val:0x7c01; valaddr_reg:x2; val_offset:3198*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3198*FLEN/8, x3, x1, x4) + +inst_1101: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfd55; +op3val:0xfd55; valaddr_reg:x2; val_offset:3201*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3201*FLEN/8, x3, x1, x4) + +inst_1102: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfd55; +op3val:0x3c00; valaddr_reg:x2; val_offset:3204*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3204*FLEN/8, x3, x1, x4) + +inst_1103: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xfd55; +op3val:0xbc00; valaddr_reg:x2; val_offset:3207*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3207*FLEN/8, x3, x1, x4) + +inst_1104: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x3c00; +op3val:0x0; valaddr_reg:x2; val_offset:3210*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3210*FLEN/8, x3, x1, x4) + +inst_1105: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x3c00; +op3val:0x8000; valaddr_reg:x2; val_offset:3213*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3213*FLEN/8, x3, x1, x4) + +inst_1106: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x3c00; +op3val:0x1; valaddr_reg:x2; val_offset:3216*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3216*FLEN/8, x3, x1, x4) + +inst_1107: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x3c00; +op3val:0x8001; valaddr_reg:x2; val_offset:3219*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3219*FLEN/8, x3, x1, x4) + +inst_1108: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x3c00; +op3val:0x2; valaddr_reg:x2; val_offset:3222*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3222*FLEN/8, x3, x1, x4) + +inst_1109: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x3c00; +op3val:0x83fe; valaddr_reg:x2; val_offset:3225*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3225*FLEN/8, x3, x1, x4) + +inst_1110: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x3c00; +op3val:0x3ff; valaddr_reg:x2; val_offset:3228*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3228*FLEN/8, x3, x1, x4) + +inst_1111: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x3c00; +op3val:0x83ff; valaddr_reg:x2; val_offset:3231*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3231*FLEN/8, x3, x1, x4) + +inst_1112: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x3c00; +op3val:0x400; valaddr_reg:x2; val_offset:3234*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3234*FLEN/8, x3, x1, x4) + +inst_1113: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x3c00; +op3val:0x8400; valaddr_reg:x2; val_offset:3237*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3237*FLEN/8, x3, x1, x4) + +inst_1114: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x3c00; +op3val:0x401; valaddr_reg:x2; val_offset:3240*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3240*FLEN/8, x3, x1, x4) + +inst_1115: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x3c00; +op3val:0x8455; valaddr_reg:x2; val_offset:3243*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3243*FLEN/8, x3, x1, x4) + +inst_1116: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x3c00; +op3val:0x7bff; valaddr_reg:x2; val_offset:3246*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3246*FLEN/8, x3, x1, x4) + +inst_1117: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x3c00; +op3val:0xfbff; valaddr_reg:x2; val_offset:3249*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3249*FLEN/8, x3, x1, x4) + +inst_1118: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x3c00; +op3val:0x7c00; valaddr_reg:x2; val_offset:3252*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3252*FLEN/8, x3, x1, x4) + +inst_1119: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x3c00; +op3val:0xfc00; valaddr_reg:x2; val_offset:3255*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3255*FLEN/8, x3, x1, x4) + +inst_1120: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x3c00; +op3val:0x7e00; valaddr_reg:x2; val_offset:3258*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3258*FLEN/8, x3, x1, x4) + +inst_1121: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x3c00; +op3val:0xfe00; valaddr_reg:x2; val_offset:3261*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3261*FLEN/8, x3, x1, x4) + +inst_1122: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x3c00; +op3val:0x7e01; valaddr_reg:x2; val_offset:3264*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3264*FLEN/8, x3, x1, x4) + +inst_1123: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x3c00; +op3val:0xfe55; valaddr_reg:x2; val_offset:3267*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3267*FLEN/8, x3, x1, x4) + +inst_1124: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x3c00; +op3val:0x7c01; valaddr_reg:x2; val_offset:3270*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3270*FLEN/8, x3, x1, x4) + +inst_1125: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x3c00; +op3val:0xfd55; valaddr_reg:x2; val_offset:3273*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3273*FLEN/8, x3, x1, x4) + +inst_1126: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x3c00; +op3val:0x3c00; valaddr_reg:x2; val_offset:3276*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3276*FLEN/8, x3, x1, x4) + +inst_1127: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0x3c00; +op3val:0xbc00; valaddr_reg:x2; val_offset:3279*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3279*FLEN/8, x3, x1, x4) + +inst_1128: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xbc00; +op3val:0x0; valaddr_reg:x2; val_offset:3282*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3282*FLEN/8, x3, x1, x4) + +inst_1129: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xbc00; +op3val:0x8000; valaddr_reg:x2; val_offset:3285*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3285*FLEN/8, x3, x1, x4) + +inst_1130: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xbc00; +op3val:0x1; valaddr_reg:x2; val_offset:3288*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3288*FLEN/8, x3, x1, x4) + +inst_1131: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xbc00; +op3val:0x8001; valaddr_reg:x2; val_offset:3291*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3291*FLEN/8, x3, x1, x4) + +inst_1132: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xbc00; +op3val:0x2; valaddr_reg:x2; val_offset:3294*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3294*FLEN/8, x3, x1, x4) + +inst_1133: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xbc00; +op3val:0x83fe; valaddr_reg:x2; val_offset:3297*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3297*FLEN/8, x3, x1, x4) + +inst_1134: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xbc00; +op3val:0x3ff; valaddr_reg:x2; val_offset:3300*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3300*FLEN/8, x3, x1, x4) + +inst_1135: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xbc00; +op3val:0x83ff; valaddr_reg:x2; val_offset:3303*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3303*FLEN/8, x3, x1, x4) + +inst_1136: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xbc00; +op3val:0x400; valaddr_reg:x2; val_offset:3306*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3306*FLEN/8, x3, x1, x4) + +inst_1137: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xbc00; +op3val:0x8400; valaddr_reg:x2; val_offset:3309*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3309*FLEN/8, x3, x1, x4) + +inst_1138: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xbc00; +op3val:0x401; valaddr_reg:x2; val_offset:3312*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3312*FLEN/8, x3, x1, x4) + +inst_1139: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xbc00; +op3val:0x8455; valaddr_reg:x2; val_offset:3315*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3315*FLEN/8, x3, x1, x4) + +inst_1140: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xbc00; +op3val:0x7bff; valaddr_reg:x2; val_offset:3318*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3318*FLEN/8, x3, x1, x4) + +inst_1141: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xbc00; +op3val:0xfbff; valaddr_reg:x2; val_offset:3321*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3321*FLEN/8, x3, x1, x4) + +inst_1142: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xbc00; +op3val:0x7c00; valaddr_reg:x2; val_offset:3324*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3324*FLEN/8, x3, x1, x4) + +inst_1143: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xbc00; +op3val:0xfc00; valaddr_reg:x2; val_offset:3327*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3327*FLEN/8, x3, x1, x4) + +inst_1144: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xbc00; +op3val:0x7e00; valaddr_reg:x2; val_offset:3330*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3330*FLEN/8, x3, x1, x4) + +inst_1145: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xbc00; +op3val:0xfe00; valaddr_reg:x2; val_offset:3333*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3333*FLEN/8, x3, x1, x4) + +inst_1146: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xbc00; +op3val:0x7e01; valaddr_reg:x2; val_offset:3336*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3336*FLEN/8, x3, x1, x4) + +inst_1147: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xbc00; +op3val:0xfe55; valaddr_reg:x2; val_offset:3339*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3339*FLEN/8, x3, x1, x4) + +inst_1148: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xbc00; +op3val:0x7c01; valaddr_reg:x2; val_offset:3342*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3342*FLEN/8, x3, x1, x4) + +inst_1149: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xbc00; +op3val:0xfd55; valaddr_reg:x2; val_offset:3345*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3345*FLEN/8, x3, x1, x4) + +inst_1150: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xbc00; +op3val:0x3c00; valaddr_reg:x2; val_offset:3348*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3348*FLEN/8, x3, x1, x4) + +inst_1151: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8000; op2val:0xbc00; +op3val:0xbc00; valaddr_reg:x2; val_offset:3351*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3351*FLEN/8, x3, x1, x4) + +inst_1152: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x0; +op3val:0x0; valaddr_reg:x2; val_offset:3354*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3354*FLEN/8, x3, x1, x4) + +inst_1153: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x0; +op3val:0x8000; valaddr_reg:x2; val_offset:3357*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3357*FLEN/8, x3, x1, x4) + +inst_1154: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x0; +op3val:0x1; valaddr_reg:x2; val_offset:3360*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3360*FLEN/8, x3, x1, x4) + +inst_1155: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x0; +op3val:0x8001; valaddr_reg:x2; val_offset:3363*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3363*FLEN/8, x3, x1, x4) + +inst_1156: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x0; +op3val:0x2; valaddr_reg:x2; val_offset:3366*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3366*FLEN/8, x3, x1, x4) + +inst_1157: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x0; +op3val:0x83fe; valaddr_reg:x2; val_offset:3369*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3369*FLEN/8, x3, x1, x4) + +inst_1158: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x0; +op3val:0x3ff; valaddr_reg:x2; val_offset:3372*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3372*FLEN/8, x3, x1, x4) + +inst_1159: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x0; +op3val:0x83ff; valaddr_reg:x2; val_offset:3375*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3375*FLEN/8, x3, x1, x4) + +inst_1160: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x0; +op3val:0x400; valaddr_reg:x2; val_offset:3378*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3378*FLEN/8, x3, x1, x4) + +inst_1161: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x0; +op3val:0x8400; valaddr_reg:x2; val_offset:3381*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3381*FLEN/8, x3, x1, x4) + +inst_1162: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x0; +op3val:0x401; valaddr_reg:x2; val_offset:3384*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3384*FLEN/8, x3, x1, x4) + +inst_1163: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x0; +op3val:0x8455; valaddr_reg:x2; val_offset:3387*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3387*FLEN/8, x3, x1, x4) + +inst_1164: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x0; +op3val:0x7bff; valaddr_reg:x2; val_offset:3390*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3390*FLEN/8, x3, x1, x4) + +inst_1165: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x0; +op3val:0xfbff; valaddr_reg:x2; val_offset:3393*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3393*FLEN/8, x3, x1, x4) + +inst_1166: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x0; +op3val:0x7c00; valaddr_reg:x2; val_offset:3396*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3396*FLEN/8, x3, x1, x4) + +inst_1167: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x0; +op3val:0xfc00; valaddr_reg:x2; val_offset:3399*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3399*FLEN/8, x3, x1, x4) + +inst_1168: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x0; +op3val:0x7e00; valaddr_reg:x2; val_offset:3402*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3402*FLEN/8, x3, x1, x4) + +inst_1169: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x0; +op3val:0xfe00; valaddr_reg:x2; val_offset:3405*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3405*FLEN/8, x3, x1, x4) + +inst_1170: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x0; +op3val:0x7e01; valaddr_reg:x2; val_offset:3408*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3408*FLEN/8, x3, x1, x4) + +inst_1171: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x0; +op3val:0xfe55; valaddr_reg:x2; val_offset:3411*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3411*FLEN/8, x3, x1, x4) + +inst_1172: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x0; +op3val:0x7c01; valaddr_reg:x2; val_offset:3414*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3414*FLEN/8, x3, x1, x4) + +inst_1173: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x0; +op3val:0xfd55; valaddr_reg:x2; val_offset:3417*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3417*FLEN/8, x3, x1, x4) + +inst_1174: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x0; +op3val:0x3c00; valaddr_reg:x2; val_offset:3420*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3420*FLEN/8, x3, x1, x4) + +inst_1175: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x0; +op3val:0xbc00; valaddr_reg:x2; val_offset:3423*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3423*FLEN/8, x3, x1, x4) + +inst_1176: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8000; +op3val:0x0; valaddr_reg:x2; val_offset:3426*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3426*FLEN/8, x3, x1, x4) + +inst_1177: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8000; +op3val:0x8000; valaddr_reg:x2; val_offset:3429*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3429*FLEN/8, x3, x1, x4) + +inst_1178: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8000; +op3val:0x1; valaddr_reg:x2; val_offset:3432*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3432*FLEN/8, x3, x1, x4) + +inst_1179: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8000; +op3val:0x8001; valaddr_reg:x2; val_offset:3435*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3435*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_10) + +inst_1180: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8000; +op3val:0x2; valaddr_reg:x2; val_offset:3438*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3438*FLEN/8, x3, x1, x4) + +inst_1181: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8000; +op3val:0x83fe; valaddr_reg:x2; val_offset:3441*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3441*FLEN/8, x3, x1, x4) + +inst_1182: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8000; +op3val:0x3ff; valaddr_reg:x2; val_offset:3444*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3444*FLEN/8, x3, x1, x4) + +inst_1183: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8000; +op3val:0x83ff; valaddr_reg:x2; val_offset:3447*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3447*FLEN/8, x3, x1, x4) + +inst_1184: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8000; +op3val:0x400; valaddr_reg:x2; val_offset:3450*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3450*FLEN/8, x3, x1, x4) + +inst_1185: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8000; +op3val:0x8400; valaddr_reg:x2; val_offset:3453*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3453*FLEN/8, x3, x1, x4) + +inst_1186: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8000; +op3val:0x401; valaddr_reg:x2; val_offset:3456*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3456*FLEN/8, x3, x1, x4) + +inst_1187: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8000; +op3val:0x8455; valaddr_reg:x2; val_offset:3459*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3459*FLEN/8, x3, x1, x4) + +inst_1188: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x2; val_offset:3462*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3462*FLEN/8, x3, x1, x4) + +inst_1189: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x2; val_offset:3465*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3465*FLEN/8, x3, x1, x4) + +inst_1190: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8000; +op3val:0x7c00; valaddr_reg:x2; val_offset:3468*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3468*FLEN/8, x3, x1, x4) + +inst_1191: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8000; +op3val:0xfc00; valaddr_reg:x2; val_offset:3471*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3471*FLEN/8, x3, x1, x4) + +inst_1192: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8000; +op3val:0x7e00; valaddr_reg:x2; val_offset:3474*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3474*FLEN/8, x3, x1, x4) + +inst_1193: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8000; +op3val:0xfe00; valaddr_reg:x2; val_offset:3477*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3477*FLEN/8, x3, x1, x4) + +inst_1194: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8000; +op3val:0x7e01; valaddr_reg:x2; val_offset:3480*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3480*FLEN/8, x3, x1, x4) + +inst_1195: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8000; +op3val:0xfe55; valaddr_reg:x2; val_offset:3483*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3483*FLEN/8, x3, x1, x4) + +inst_1196: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8000; +op3val:0x7c01; valaddr_reg:x2; val_offset:3486*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3486*FLEN/8, x3, x1, x4) + +inst_1197: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8000; +op3val:0xfd55; valaddr_reg:x2; val_offset:3489*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3489*FLEN/8, x3, x1, x4) + +inst_1198: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8000; +op3val:0x3c00; valaddr_reg:x2; val_offset:3492*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3492*FLEN/8, x3, x1, x4) + +inst_1199: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8000; +op3val:0xbc00; valaddr_reg:x2; val_offset:3495*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3495*FLEN/8, x3, x1, x4) + +inst_1200: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x1; +op3val:0x0; valaddr_reg:x2; val_offset:3498*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3498*FLEN/8, x3, x1, x4) + +inst_1201: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x1; +op3val:0x8000; valaddr_reg:x2; val_offset:3501*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3501*FLEN/8, x3, x1, x4) + +inst_1202: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x1; +op3val:0x1; valaddr_reg:x2; val_offset:3504*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3504*FLEN/8, x3, x1, x4) + +inst_1203: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x1; +op3val:0x8001; valaddr_reg:x2; val_offset:3507*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3507*FLEN/8, x3, x1, x4) + +inst_1204: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x1; +op3val:0x2; valaddr_reg:x2; val_offset:3510*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3510*FLEN/8, x3, x1, x4) + +inst_1205: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x1; +op3val:0x83fe; valaddr_reg:x2; val_offset:3513*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3513*FLEN/8, x3, x1, x4) + +inst_1206: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x1; +op3val:0x3ff; valaddr_reg:x2; val_offset:3516*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3516*FLEN/8, x3, x1, x4) + +inst_1207: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x1; +op3val:0x83ff; valaddr_reg:x2; val_offset:3519*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3519*FLEN/8, x3, x1, x4) + +inst_1208: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x1; +op3val:0x400; valaddr_reg:x2; val_offset:3522*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3522*FLEN/8, x3, x1, x4) + +inst_1209: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x1; +op3val:0x8400; valaddr_reg:x2; val_offset:3525*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3525*FLEN/8, x3, x1, x4) + +inst_1210: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x1; +op3val:0x401; valaddr_reg:x2; val_offset:3528*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3528*FLEN/8, x3, x1, x4) + +inst_1211: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x1; +op3val:0x8455; valaddr_reg:x2; val_offset:3531*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3531*FLEN/8, x3, x1, x4) + +inst_1212: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x1; +op3val:0x7bff; valaddr_reg:x2; val_offset:3534*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3534*FLEN/8, x3, x1, x4) + +inst_1213: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x1; +op3val:0xfbff; valaddr_reg:x2; val_offset:3537*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3537*FLEN/8, x3, x1, x4) + +inst_1214: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x1; +op3val:0x7c00; valaddr_reg:x2; val_offset:3540*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3540*FLEN/8, x3, x1, x4) + +inst_1215: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x1; +op3val:0xfc00; valaddr_reg:x2; val_offset:3543*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3543*FLEN/8, x3, x1, x4) + +inst_1216: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x1; +op3val:0x7e00; valaddr_reg:x2; val_offset:3546*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3546*FLEN/8, x3, x1, x4) + +inst_1217: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x1; +op3val:0xfe00; valaddr_reg:x2; val_offset:3549*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3549*FLEN/8, x3, x1, x4) + +inst_1218: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x1; +op3val:0x7e01; valaddr_reg:x2; val_offset:3552*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3552*FLEN/8, x3, x1, x4) + +inst_1219: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x1; +op3val:0xfe55; valaddr_reg:x2; val_offset:3555*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3555*FLEN/8, x3, x1, x4) + +inst_1220: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x1; +op3val:0x7c01; valaddr_reg:x2; val_offset:3558*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3558*FLEN/8, x3, x1, x4) + +inst_1221: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x1; +op3val:0xfd55; valaddr_reg:x2; val_offset:3561*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3561*FLEN/8, x3, x1, x4) + +inst_1222: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x1; +op3val:0x3c00; valaddr_reg:x2; val_offset:3564*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3564*FLEN/8, x3, x1, x4) + +inst_1223: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x1; +op3val:0xbc00; valaddr_reg:x2; val_offset:3567*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3567*FLEN/8, x3, x1, x4) + +inst_1224: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8001; +op3val:0x0; valaddr_reg:x2; val_offset:3570*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3570*FLEN/8, x3, x1, x4) + +inst_1225: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8001; +op3val:0x8000; valaddr_reg:x2; val_offset:3573*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3573*FLEN/8, x3, x1, x4) + +inst_1226: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8001; +op3val:0x1; valaddr_reg:x2; val_offset:3576*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3576*FLEN/8, x3, x1, x4) + +inst_1227: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8001; +op3val:0x8001; valaddr_reg:x2; val_offset:3579*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3579*FLEN/8, x3, x1, x4) + +inst_1228: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8001; +op3val:0x2; valaddr_reg:x2; val_offset:3582*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3582*FLEN/8, x3, x1, x4) + +inst_1229: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8001; +op3val:0x83fe; valaddr_reg:x2; val_offset:3585*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3585*FLEN/8, x3, x1, x4) + +inst_1230: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8001; +op3val:0x3ff; valaddr_reg:x2; val_offset:3588*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3588*FLEN/8, x3, x1, x4) + +inst_1231: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8001; +op3val:0x83ff; valaddr_reg:x2; val_offset:3591*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3591*FLEN/8, x3, x1, x4) + +inst_1232: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8001; +op3val:0x400; valaddr_reg:x2; val_offset:3594*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3594*FLEN/8, x3, x1, x4) + +inst_1233: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8001; +op3val:0x8400; valaddr_reg:x2; val_offset:3597*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3597*FLEN/8, x3, x1, x4) + +inst_1234: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8001; +op3val:0x401; valaddr_reg:x2; val_offset:3600*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3600*FLEN/8, x3, x1, x4) + +inst_1235: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8001; +op3val:0x8455; valaddr_reg:x2; val_offset:3603*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3603*FLEN/8, x3, x1, x4) + +inst_1236: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8001; +op3val:0x7bff; valaddr_reg:x2; val_offset:3606*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3606*FLEN/8, x3, x1, x4) + +inst_1237: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8001; +op3val:0xfbff; valaddr_reg:x2; val_offset:3609*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3609*FLEN/8, x3, x1, x4) + +inst_1238: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8001; +op3val:0x7c00; valaddr_reg:x2; val_offset:3612*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3612*FLEN/8, x3, x1, x4) + +inst_1239: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8001; +op3val:0xfc00; valaddr_reg:x2; val_offset:3615*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3615*FLEN/8, x3, x1, x4) + +inst_1240: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8001; +op3val:0x7e00; valaddr_reg:x2; val_offset:3618*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3618*FLEN/8, x3, x1, x4) + +inst_1241: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8001; +op3val:0xfe00; valaddr_reg:x2; val_offset:3621*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3621*FLEN/8, x3, x1, x4) + +inst_1242: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8001; +op3val:0x7e01; valaddr_reg:x2; val_offset:3624*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3624*FLEN/8, x3, x1, x4) + +inst_1243: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8001; +op3val:0xfe55; valaddr_reg:x2; val_offset:3627*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3627*FLEN/8, x3, x1, x4) + +inst_1244: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8001; +op3val:0x7c01; valaddr_reg:x2; val_offset:3630*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3630*FLEN/8, x3, x1, x4) + +inst_1245: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8001; +op3val:0xfd55; valaddr_reg:x2; val_offset:3633*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3633*FLEN/8, x3, x1, x4) + +inst_1246: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8001; +op3val:0x3c00; valaddr_reg:x2; val_offset:3636*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3636*FLEN/8, x3, x1, x4) + +inst_1247: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8001; +op3val:0xbc00; valaddr_reg:x2; val_offset:3639*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3639*FLEN/8, x3, x1, x4) + +inst_1248: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x2; +op3val:0x0; valaddr_reg:x2; val_offset:3642*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3642*FLEN/8, x3, x1, x4) + +inst_1249: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x2; +op3val:0x8000; valaddr_reg:x2; val_offset:3645*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3645*FLEN/8, x3, x1, x4) + +inst_1250: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x2; +op3val:0x1; valaddr_reg:x2; val_offset:3648*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3648*FLEN/8, x3, x1, x4) + +inst_1251: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x2; +op3val:0x8001; valaddr_reg:x2; val_offset:3651*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3651*FLEN/8, x3, x1, x4) + +inst_1252: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x2; +op3val:0x2; valaddr_reg:x2; val_offset:3654*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3654*FLEN/8, x3, x1, x4) + +inst_1253: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x2; +op3val:0x83fe; valaddr_reg:x2; val_offset:3657*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3657*FLEN/8, x3, x1, x4) + +inst_1254: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x2; +op3val:0x3ff; valaddr_reg:x2; val_offset:3660*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3660*FLEN/8, x3, x1, x4) + +inst_1255: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x2; +op3val:0x83ff; valaddr_reg:x2; val_offset:3663*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3663*FLEN/8, x3, x1, x4) + +inst_1256: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x2; +op3val:0x400; valaddr_reg:x2; val_offset:3666*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3666*FLEN/8, x3, x1, x4) + +inst_1257: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x2; +op3val:0x8400; valaddr_reg:x2; val_offset:3669*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3669*FLEN/8, x3, x1, x4) + +inst_1258: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x2; +op3val:0x401; valaddr_reg:x2; val_offset:3672*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3672*FLEN/8, x3, x1, x4) + +inst_1259: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x2; +op3val:0x8455; valaddr_reg:x2; val_offset:3675*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3675*FLEN/8, x3, x1, x4) + +inst_1260: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x2; +op3val:0x7bff; valaddr_reg:x2; val_offset:3678*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3678*FLEN/8, x3, x1, x4) + +inst_1261: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x2; +op3val:0xfbff; valaddr_reg:x2; val_offset:3681*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3681*FLEN/8, x3, x1, x4) + +inst_1262: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x2; +op3val:0x7c00; valaddr_reg:x2; val_offset:3684*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3684*FLEN/8, x3, x1, x4) + +inst_1263: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x2; +op3val:0xfc00; valaddr_reg:x2; val_offset:3687*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3687*FLEN/8, x3, x1, x4) + +inst_1264: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x2; +op3val:0x7e00; valaddr_reg:x2; val_offset:3690*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3690*FLEN/8, x3, x1, x4) + +inst_1265: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x2; +op3val:0xfe00; valaddr_reg:x2; val_offset:3693*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3693*FLEN/8, x3, x1, x4) + +inst_1266: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x2; +op3val:0x7e01; valaddr_reg:x2; val_offset:3696*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3696*FLEN/8, x3, x1, x4) + +inst_1267: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x2; +op3val:0xfe55; valaddr_reg:x2; val_offset:3699*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3699*FLEN/8, x3, x1, x4) + +inst_1268: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x2; +op3val:0x7c01; valaddr_reg:x2; val_offset:3702*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3702*FLEN/8, x3, x1, x4) + +inst_1269: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x2; +op3val:0xfd55; valaddr_reg:x2; val_offset:3705*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3705*FLEN/8, x3, x1, x4) + +inst_1270: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x2; +op3val:0x3c00; valaddr_reg:x2; val_offset:3708*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3708*FLEN/8, x3, x1, x4) + +inst_1271: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x2; +op3val:0xbc00; valaddr_reg:x2; val_offset:3711*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3711*FLEN/8, x3, x1, x4) + +inst_1272: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x83fe; +op3val:0x0; valaddr_reg:x2; val_offset:3714*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3714*FLEN/8, x3, x1, x4) + +inst_1273: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x83fe; +op3val:0x8000; valaddr_reg:x2; val_offset:3717*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3717*FLEN/8, x3, x1, x4) + +inst_1274: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x83fe; +op3val:0x1; valaddr_reg:x2; val_offset:3720*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3720*FLEN/8, x3, x1, x4) + +inst_1275: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x83fe; +op3val:0x8001; valaddr_reg:x2; val_offset:3723*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3723*FLEN/8, x3, x1, x4) + +inst_1276: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x83fe; +op3val:0x2; valaddr_reg:x2; val_offset:3726*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3726*FLEN/8, x3, x1, x4) + +inst_1277: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x83fe; +op3val:0x83fe; valaddr_reg:x2; val_offset:3729*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3729*FLEN/8, x3, x1, x4) + +inst_1278: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x83fe; +op3val:0x3ff; valaddr_reg:x2; val_offset:3732*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3732*FLEN/8, x3, x1, x4) + +inst_1279: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x83fe; +op3val:0x83ff; valaddr_reg:x2; val_offset:3735*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3735*FLEN/8, x3, x1, x4) + +inst_1280: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x83fe; +op3val:0x400; valaddr_reg:x2; val_offset:3738*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3738*FLEN/8, x3, x1, x4) + +inst_1281: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x83fe; +op3val:0x8400; valaddr_reg:x2; val_offset:3741*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3741*FLEN/8, x3, x1, x4) + +inst_1282: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x83fe; +op3val:0x401; valaddr_reg:x2; val_offset:3744*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3744*FLEN/8, x3, x1, x4) + +inst_1283: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x83fe; +op3val:0x8455; valaddr_reg:x2; val_offset:3747*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3747*FLEN/8, x3, x1, x4) + +inst_1284: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x83fe; +op3val:0x7bff; valaddr_reg:x2; val_offset:3750*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3750*FLEN/8, x3, x1, x4) + +inst_1285: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x83fe; +op3val:0xfbff; valaddr_reg:x2; val_offset:3753*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3753*FLEN/8, x3, x1, x4) + +inst_1286: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x83fe; +op3val:0x7c00; valaddr_reg:x2; val_offset:3756*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3756*FLEN/8, x3, x1, x4) + +inst_1287: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x83fe; +op3val:0xfc00; valaddr_reg:x2; val_offset:3759*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3759*FLEN/8, x3, x1, x4) + +inst_1288: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x83fe; +op3val:0x7e00; valaddr_reg:x2; val_offset:3762*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3762*FLEN/8, x3, x1, x4) + +inst_1289: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x83fe; +op3val:0xfe00; valaddr_reg:x2; val_offset:3765*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3765*FLEN/8, x3, x1, x4) + +inst_1290: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x83fe; +op3val:0x7e01; valaddr_reg:x2; val_offset:3768*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3768*FLEN/8, x3, x1, x4) + +inst_1291: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x83fe; +op3val:0xfe55; valaddr_reg:x2; val_offset:3771*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3771*FLEN/8, x3, x1, x4) + +inst_1292: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x83fe; +op3val:0x7c01; valaddr_reg:x2; val_offset:3774*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3774*FLEN/8, x3, x1, x4) + +inst_1293: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x83fe; +op3val:0xfd55; valaddr_reg:x2; val_offset:3777*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3777*FLEN/8, x3, x1, x4) + +inst_1294: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x83fe; +op3val:0x3c00; valaddr_reg:x2; val_offset:3780*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3780*FLEN/8, x3, x1, x4) + +inst_1295: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x83fe; +op3val:0xbc00; valaddr_reg:x2; val_offset:3783*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3783*FLEN/8, x3, x1, x4) + +inst_1296: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3ff; +op3val:0x0; valaddr_reg:x2; val_offset:3786*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3786*FLEN/8, x3, x1, x4) + +inst_1297: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3ff; +op3val:0x8000; valaddr_reg:x2; val_offset:3789*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3789*FLEN/8, x3, x1, x4) + +inst_1298: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3ff; +op3val:0x1; valaddr_reg:x2; val_offset:3792*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3792*FLEN/8, x3, x1, x4) + +inst_1299: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3ff; +op3val:0x8001; valaddr_reg:x2; val_offset:3795*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3795*FLEN/8, x3, x1, x4) + +inst_1300: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3ff; +op3val:0x2; valaddr_reg:x2; val_offset:3798*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3798*FLEN/8, x3, x1, x4) + +inst_1301: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3ff; +op3val:0x83fe; valaddr_reg:x2; val_offset:3801*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3801*FLEN/8, x3, x1, x4) + +inst_1302: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3ff; +op3val:0x3ff; valaddr_reg:x2; val_offset:3804*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3804*FLEN/8, x3, x1, x4) + +inst_1303: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3ff; +op3val:0x83ff; valaddr_reg:x2; val_offset:3807*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3807*FLEN/8, x3, x1, x4) + +inst_1304: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3ff; +op3val:0x400; valaddr_reg:x2; val_offset:3810*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3810*FLEN/8, x3, x1, x4) + +inst_1305: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3ff; +op3val:0x8400; valaddr_reg:x2; val_offset:3813*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3813*FLEN/8, x3, x1, x4) + +inst_1306: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3ff; +op3val:0x401; valaddr_reg:x2; val_offset:3816*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3816*FLEN/8, x3, x1, x4) + +inst_1307: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3ff; +op3val:0x8455; valaddr_reg:x2; val_offset:3819*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3819*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_11) + +inst_1308: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3ff; +op3val:0x7bff; valaddr_reg:x2; val_offset:3822*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3822*FLEN/8, x3, x1, x4) + +inst_1309: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3ff; +op3val:0xfbff; valaddr_reg:x2; val_offset:3825*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3825*FLEN/8, x3, x1, x4) + +inst_1310: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3ff; +op3val:0x7c00; valaddr_reg:x2; val_offset:3828*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3828*FLEN/8, x3, x1, x4) + +inst_1311: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3ff; +op3val:0xfc00; valaddr_reg:x2; val_offset:3831*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3831*FLEN/8, x3, x1, x4) + +inst_1312: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3ff; +op3val:0x7e00; valaddr_reg:x2; val_offset:3834*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3834*FLEN/8, x3, x1, x4) + +inst_1313: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3ff; +op3val:0xfe00; valaddr_reg:x2; val_offset:3837*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3837*FLEN/8, x3, x1, x4) + +inst_1314: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3ff; +op3val:0x7e01; valaddr_reg:x2; val_offset:3840*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3840*FLEN/8, x3, x1, x4) + +inst_1315: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3ff; +op3val:0xfe55; valaddr_reg:x2; val_offset:3843*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3843*FLEN/8, x3, x1, x4) + +inst_1316: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3ff; +op3val:0x7c01; valaddr_reg:x2; val_offset:3846*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3846*FLEN/8, x3, x1, x4) + +inst_1317: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3ff; +op3val:0xfd55; valaddr_reg:x2; val_offset:3849*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3849*FLEN/8, x3, x1, x4) + +inst_1318: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3ff; +op3val:0x3c00; valaddr_reg:x2; val_offset:3852*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3852*FLEN/8, x3, x1, x4) + +inst_1319: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3ff; +op3val:0xbc00; valaddr_reg:x2; val_offset:3855*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3855*FLEN/8, x3, x1, x4) + +inst_1320: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x83ff; +op3val:0x0; valaddr_reg:x2; val_offset:3858*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3858*FLEN/8, x3, x1, x4) + +inst_1321: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x83ff; +op3val:0x8000; valaddr_reg:x2; val_offset:3861*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3861*FLEN/8, x3, x1, x4) + +inst_1322: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x83ff; +op3val:0x1; valaddr_reg:x2; val_offset:3864*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3864*FLEN/8, x3, x1, x4) + +inst_1323: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x83ff; +op3val:0x8001; valaddr_reg:x2; val_offset:3867*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3867*FLEN/8, x3, x1, x4) + +inst_1324: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x83ff; +op3val:0x2; valaddr_reg:x2; val_offset:3870*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3870*FLEN/8, x3, x1, x4) + +inst_1325: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x83ff; +op3val:0x83fe; valaddr_reg:x2; val_offset:3873*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3873*FLEN/8, x3, x1, x4) + +inst_1326: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x83ff; +op3val:0x3ff; valaddr_reg:x2; val_offset:3876*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3876*FLEN/8, x3, x1, x4) + +inst_1327: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x83ff; +op3val:0x83ff; valaddr_reg:x2; val_offset:3879*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3879*FLEN/8, x3, x1, x4) + +inst_1328: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x83ff; +op3val:0x400; valaddr_reg:x2; val_offset:3882*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3882*FLEN/8, x3, x1, x4) + +inst_1329: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x83ff; +op3val:0x8400; valaddr_reg:x2; val_offset:3885*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3885*FLEN/8, x3, x1, x4) + +inst_1330: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x83ff; +op3val:0x401; valaddr_reg:x2; val_offset:3888*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3888*FLEN/8, x3, x1, x4) + +inst_1331: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x83ff; +op3val:0x8455; valaddr_reg:x2; val_offset:3891*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3891*FLEN/8, x3, x1, x4) + +inst_1332: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x83ff; +op3val:0x7bff; valaddr_reg:x2; val_offset:3894*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3894*FLEN/8, x3, x1, x4) + +inst_1333: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x83ff; +op3val:0xfbff; valaddr_reg:x2; val_offset:3897*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3897*FLEN/8, x3, x1, x4) + +inst_1334: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x83ff; +op3val:0x7c00; valaddr_reg:x2; val_offset:3900*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3900*FLEN/8, x3, x1, x4) + +inst_1335: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x83ff; +op3val:0xfc00; valaddr_reg:x2; val_offset:3903*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3903*FLEN/8, x3, x1, x4) + +inst_1336: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x83ff; +op3val:0x7e00; valaddr_reg:x2; val_offset:3906*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3906*FLEN/8, x3, x1, x4) + +inst_1337: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x83ff; +op3val:0xfe00; valaddr_reg:x2; val_offset:3909*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3909*FLEN/8, x3, x1, x4) + +inst_1338: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x83ff; +op3val:0x7e01; valaddr_reg:x2; val_offset:3912*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3912*FLEN/8, x3, x1, x4) + +inst_1339: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x83ff; +op3val:0xfe55; valaddr_reg:x2; val_offset:3915*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3915*FLEN/8, x3, x1, x4) + +inst_1340: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x83ff; +op3val:0x7c01; valaddr_reg:x2; val_offset:3918*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3918*FLEN/8, x3, x1, x4) + +inst_1341: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x83ff; +op3val:0xfd55; valaddr_reg:x2; val_offset:3921*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3921*FLEN/8, x3, x1, x4) + +inst_1342: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x83ff; +op3val:0x3c00; valaddr_reg:x2; val_offset:3924*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3924*FLEN/8, x3, x1, x4) + +inst_1343: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x83ff; +op3val:0xbc00; valaddr_reg:x2; val_offset:3927*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3927*FLEN/8, x3, x1, x4) + +inst_1344: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x400; +op3val:0x0; valaddr_reg:x2; val_offset:3930*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3930*FLEN/8, x3, x1, x4) + +inst_1345: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x400; +op3val:0x8000; valaddr_reg:x2; val_offset:3933*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3933*FLEN/8, x3, x1, x4) + +inst_1346: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x400; +op3val:0x1; valaddr_reg:x2; val_offset:3936*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3936*FLEN/8, x3, x1, x4) + +inst_1347: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x400; +op3val:0x8001; valaddr_reg:x2; val_offset:3939*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3939*FLEN/8, x3, x1, x4) + +inst_1348: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x400; +op3val:0x2; valaddr_reg:x2; val_offset:3942*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3942*FLEN/8, x3, x1, x4) + +inst_1349: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x400; +op3val:0x83fe; valaddr_reg:x2; val_offset:3945*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3945*FLEN/8, x3, x1, x4) + +inst_1350: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x400; +op3val:0x3ff; valaddr_reg:x2; val_offset:3948*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3948*FLEN/8, x3, x1, x4) + +inst_1351: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x400; +op3val:0x83ff; valaddr_reg:x2; val_offset:3951*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3951*FLEN/8, x3, x1, x4) + +inst_1352: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x400; +op3val:0x400; valaddr_reg:x2; val_offset:3954*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3954*FLEN/8, x3, x1, x4) + +inst_1353: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x400; +op3val:0x8400; valaddr_reg:x2; val_offset:3957*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3957*FLEN/8, x3, x1, x4) + +inst_1354: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x400; +op3val:0x401; valaddr_reg:x2; val_offset:3960*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3960*FLEN/8, x3, x1, x4) + +inst_1355: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x400; +op3val:0x8455; valaddr_reg:x2; val_offset:3963*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3963*FLEN/8, x3, x1, x4) + +inst_1356: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x400; +op3val:0x7bff; valaddr_reg:x2; val_offset:3966*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3966*FLEN/8, x3, x1, x4) + +inst_1357: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x400; +op3val:0xfbff; valaddr_reg:x2; val_offset:3969*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3969*FLEN/8, x3, x1, x4) + +inst_1358: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x400; +op3val:0x7c00; valaddr_reg:x2; val_offset:3972*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3972*FLEN/8, x3, x1, x4) + +inst_1359: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x400; +op3val:0xfc00; valaddr_reg:x2; val_offset:3975*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3975*FLEN/8, x3, x1, x4) + +inst_1360: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x400; +op3val:0x7e00; valaddr_reg:x2; val_offset:3978*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3978*FLEN/8, x3, x1, x4) + +inst_1361: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x400; +op3val:0xfe00; valaddr_reg:x2; val_offset:3981*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3981*FLEN/8, x3, x1, x4) + +inst_1362: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x400; +op3val:0x7e01; valaddr_reg:x2; val_offset:3984*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3984*FLEN/8, x3, x1, x4) + +inst_1363: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x400; +op3val:0xfe55; valaddr_reg:x2; val_offset:3987*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3987*FLEN/8, x3, x1, x4) + +inst_1364: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x400; +op3val:0x7c01; valaddr_reg:x2; val_offset:3990*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3990*FLEN/8, x3, x1, x4) + +inst_1365: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x400; +op3val:0xfd55; valaddr_reg:x2; val_offset:3993*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3993*FLEN/8, x3, x1, x4) + +inst_1366: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x400; +op3val:0x3c00; valaddr_reg:x2; val_offset:3996*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3996*FLEN/8, x3, x1, x4) + +inst_1367: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x400; +op3val:0xbc00; valaddr_reg:x2; val_offset:3999*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3999*FLEN/8, x3, x1, x4) + +inst_1368: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8400; +op3val:0x0; valaddr_reg:x2; val_offset:4002*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4002*FLEN/8, x3, x1, x4) + +inst_1369: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8400; +op3val:0x8000; valaddr_reg:x2; val_offset:4005*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4005*FLEN/8, x3, x1, x4) + +inst_1370: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8400; +op3val:0x1; valaddr_reg:x2; val_offset:4008*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4008*FLEN/8, x3, x1, x4) + +inst_1371: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8400; +op3val:0x8001; valaddr_reg:x2; val_offset:4011*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4011*FLEN/8, x3, x1, x4) + +inst_1372: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8400; +op3val:0x2; valaddr_reg:x2; val_offset:4014*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4014*FLEN/8, x3, x1, x4) + +inst_1373: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8400; +op3val:0x83fe; valaddr_reg:x2; val_offset:4017*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4017*FLEN/8, x3, x1, x4) + +inst_1374: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8400; +op3val:0x3ff; valaddr_reg:x2; val_offset:4020*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4020*FLEN/8, x3, x1, x4) + +inst_1375: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8400; +op3val:0x83ff; valaddr_reg:x2; val_offset:4023*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4023*FLEN/8, x3, x1, x4) + +inst_1376: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8400; +op3val:0x400; valaddr_reg:x2; val_offset:4026*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4026*FLEN/8, x3, x1, x4) + +inst_1377: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8400; +op3val:0x8400; valaddr_reg:x2; val_offset:4029*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4029*FLEN/8, x3, x1, x4) + +inst_1378: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8400; +op3val:0x401; valaddr_reg:x2; val_offset:4032*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4032*FLEN/8, x3, x1, x4) + +inst_1379: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8400; +op3val:0x8455; valaddr_reg:x2; val_offset:4035*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4035*FLEN/8, x3, x1, x4) + +inst_1380: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8400; +op3val:0x7bff; valaddr_reg:x2; val_offset:4038*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4038*FLEN/8, x3, x1, x4) + +inst_1381: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8400; +op3val:0xfbff; valaddr_reg:x2; val_offset:4041*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4041*FLEN/8, x3, x1, x4) + +inst_1382: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8400; +op3val:0x7c00; valaddr_reg:x2; val_offset:4044*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4044*FLEN/8, x3, x1, x4) + +inst_1383: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8400; +op3val:0xfc00; valaddr_reg:x2; val_offset:4047*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4047*FLEN/8, x3, x1, x4) + +inst_1384: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8400; +op3val:0x7e00; valaddr_reg:x2; val_offset:4050*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4050*FLEN/8, x3, x1, x4) + +inst_1385: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8400; +op3val:0xfe00; valaddr_reg:x2; val_offset:4053*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4053*FLEN/8, x3, x1, x4) + +inst_1386: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8400; +op3val:0x7e01; valaddr_reg:x2; val_offset:4056*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4056*FLEN/8, x3, x1, x4) + +inst_1387: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8400; +op3val:0xfe55; valaddr_reg:x2; val_offset:4059*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4059*FLEN/8, x3, x1, x4) + +inst_1388: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8400; +op3val:0x7c01; valaddr_reg:x2; val_offset:4062*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4062*FLEN/8, x3, x1, x4) + +inst_1389: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8400; +op3val:0xfd55; valaddr_reg:x2; val_offset:4065*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4065*FLEN/8, x3, x1, x4) + +inst_1390: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8400; +op3val:0x3c00; valaddr_reg:x2; val_offset:4068*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4068*FLEN/8, x3, x1, x4) + +inst_1391: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8400; +op3val:0xbc00; valaddr_reg:x2; val_offset:4071*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4071*FLEN/8, x3, x1, x4) + +inst_1392: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x401; +op3val:0x0; valaddr_reg:x2; val_offset:4074*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4074*FLEN/8, x3, x1, x4) + +inst_1393: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x401; +op3val:0x8000; valaddr_reg:x2; val_offset:4077*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4077*FLEN/8, x3, x1, x4) + +inst_1394: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x401; +op3val:0x1; valaddr_reg:x2; val_offset:4080*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4080*FLEN/8, x3, x1, x4) + +inst_1395: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x401; +op3val:0x8001; valaddr_reg:x2; val_offset:4083*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4083*FLEN/8, x3, x1, x4) + +inst_1396: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x401; +op3val:0x2; valaddr_reg:x2; val_offset:4086*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4086*FLEN/8, x3, x1, x4) + +inst_1397: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x401; +op3val:0x83fe; valaddr_reg:x2; val_offset:4089*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4089*FLEN/8, x3, x1, x4) + +inst_1398: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x401; +op3val:0x3ff; valaddr_reg:x2; val_offset:4092*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4092*FLEN/8, x3, x1, x4) + +inst_1399: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x401; +op3val:0x83ff; valaddr_reg:x2; val_offset:4095*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4095*FLEN/8, x3, x1, x4) + +inst_1400: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x401; +op3val:0x400; valaddr_reg:x2; val_offset:4098*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4098*FLEN/8, x3, x1, x4) + +inst_1401: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x401; +op3val:0x8400; valaddr_reg:x2; val_offset:4101*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4101*FLEN/8, x3, x1, x4) + +inst_1402: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x401; +op3val:0x401; valaddr_reg:x2; val_offset:4104*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4104*FLEN/8, x3, x1, x4) + +inst_1403: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x401; +op3val:0x8455; valaddr_reg:x2; val_offset:4107*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4107*FLEN/8, x3, x1, x4) + +inst_1404: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x401; +op3val:0x7bff; valaddr_reg:x2; val_offset:4110*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4110*FLEN/8, x3, x1, x4) + +inst_1405: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x401; +op3val:0xfbff; valaddr_reg:x2; val_offset:4113*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4113*FLEN/8, x3, x1, x4) + +inst_1406: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x401; +op3val:0x7c00; valaddr_reg:x2; val_offset:4116*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4116*FLEN/8, x3, x1, x4) + +inst_1407: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x401; +op3val:0xfc00; valaddr_reg:x2; val_offset:4119*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4119*FLEN/8, x3, x1, x4) + +inst_1408: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x401; +op3val:0x7e00; valaddr_reg:x2; val_offset:4122*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4122*FLEN/8, x3, x1, x4) + +inst_1409: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x401; +op3val:0xfe00; valaddr_reg:x2; val_offset:4125*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4125*FLEN/8, x3, x1, x4) + +inst_1410: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x401; +op3val:0x7e01; valaddr_reg:x2; val_offset:4128*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4128*FLEN/8, x3, x1, x4) + +inst_1411: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x401; +op3val:0xfe55; valaddr_reg:x2; val_offset:4131*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4131*FLEN/8, x3, x1, x4) + +inst_1412: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x401; +op3val:0x7c01; valaddr_reg:x2; val_offset:4134*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4134*FLEN/8, x3, x1, x4) + +inst_1413: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x401; +op3val:0xfd55; valaddr_reg:x2; val_offset:4137*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4137*FLEN/8, x3, x1, x4) + +inst_1414: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x401; +op3val:0x3c00; valaddr_reg:x2; val_offset:4140*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4140*FLEN/8, x3, x1, x4) + +inst_1415: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x401; +op3val:0xbc00; valaddr_reg:x2; val_offset:4143*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4143*FLEN/8, x3, x1, x4) + +inst_1416: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8455; +op3val:0x0; valaddr_reg:x2; val_offset:4146*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4146*FLEN/8, x3, x1, x4) + +inst_1417: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8455; +op3val:0x8000; valaddr_reg:x2; val_offset:4149*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4149*FLEN/8, x3, x1, x4) + +inst_1418: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8455; +op3val:0x1; valaddr_reg:x2; val_offset:4152*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4152*FLEN/8, x3, x1, x4) + +inst_1419: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8455; +op3val:0x8001; valaddr_reg:x2; val_offset:4155*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4155*FLEN/8, x3, x1, x4) + +inst_1420: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8455; +op3val:0x2; valaddr_reg:x2; val_offset:4158*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4158*FLEN/8, x3, x1, x4) + +inst_1421: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8455; +op3val:0x83fe; valaddr_reg:x2; val_offset:4161*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4161*FLEN/8, x3, x1, x4) + +inst_1422: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8455; +op3val:0x3ff; valaddr_reg:x2; val_offset:4164*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4164*FLEN/8, x3, x1, x4) + +inst_1423: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8455; +op3val:0x83ff; valaddr_reg:x2; val_offset:4167*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4167*FLEN/8, x3, x1, x4) + +inst_1424: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8455; +op3val:0x400; valaddr_reg:x2; val_offset:4170*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4170*FLEN/8, x3, x1, x4) + +inst_1425: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8455; +op3val:0x8400; valaddr_reg:x2; val_offset:4173*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4173*FLEN/8, x3, x1, x4) + +inst_1426: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8455; +op3val:0x401; valaddr_reg:x2; val_offset:4176*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4176*FLEN/8, x3, x1, x4) + +inst_1427: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8455; +op3val:0x8455; valaddr_reg:x2; val_offset:4179*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4179*FLEN/8, x3, x1, x4) + +inst_1428: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8455; +op3val:0x7bff; valaddr_reg:x2; val_offset:4182*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4182*FLEN/8, x3, x1, x4) + +inst_1429: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8455; +op3val:0xfbff; valaddr_reg:x2; val_offset:4185*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4185*FLEN/8, x3, x1, x4) + +inst_1430: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8455; +op3val:0x7c00; valaddr_reg:x2; val_offset:4188*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4188*FLEN/8, x3, x1, x4) + +inst_1431: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8455; +op3val:0xfc00; valaddr_reg:x2; val_offset:4191*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4191*FLEN/8, x3, x1, x4) + +inst_1432: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8455; +op3val:0x7e00; valaddr_reg:x2; val_offset:4194*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4194*FLEN/8, x3, x1, x4) + +inst_1433: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8455; +op3val:0xfe00; valaddr_reg:x2; val_offset:4197*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4197*FLEN/8, x3, x1, x4) + +inst_1434: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8455; +op3val:0x7e01; valaddr_reg:x2; val_offset:4200*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4200*FLEN/8, x3, x1, x4) + +inst_1435: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8455; +op3val:0xfe55; valaddr_reg:x2; val_offset:4203*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4203*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_12) + +inst_1436: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8455; +op3val:0x7c01; valaddr_reg:x2; val_offset:4206*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4206*FLEN/8, x3, x1, x4) + +inst_1437: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8455; +op3val:0xfd55; valaddr_reg:x2; val_offset:4209*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4209*FLEN/8, x3, x1, x4) + +inst_1438: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8455; +op3val:0x3c00; valaddr_reg:x2; val_offset:4212*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4212*FLEN/8, x3, x1, x4) + +inst_1439: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x8455; +op3val:0xbc00; valaddr_reg:x2; val_offset:4215*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4215*FLEN/8, x3, x1, x4) + +inst_1440: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7bff; +op3val:0x0; valaddr_reg:x2; val_offset:4218*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4218*FLEN/8, x3, x1, x4) + +inst_1441: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7bff; +op3val:0x8000; valaddr_reg:x2; val_offset:4221*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4221*FLEN/8, x3, x1, x4) + +inst_1442: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7bff; +op3val:0x1; valaddr_reg:x2; val_offset:4224*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4224*FLEN/8, x3, x1, x4) + +inst_1443: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7bff; +op3val:0x8001; valaddr_reg:x2; val_offset:4227*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4227*FLEN/8, x3, x1, x4) + +inst_1444: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7bff; +op3val:0x2; valaddr_reg:x2; val_offset:4230*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4230*FLEN/8, x3, x1, x4) + +inst_1445: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7bff; +op3val:0x83fe; valaddr_reg:x2; val_offset:4233*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4233*FLEN/8, x3, x1, x4) + +inst_1446: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7bff; +op3val:0x3ff; valaddr_reg:x2; val_offset:4236*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4236*FLEN/8, x3, x1, x4) + +inst_1447: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7bff; +op3val:0x83ff; valaddr_reg:x2; val_offset:4239*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4239*FLEN/8, x3, x1, x4) + +inst_1448: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7bff; +op3val:0x400; valaddr_reg:x2; val_offset:4242*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4242*FLEN/8, x3, x1, x4) + +inst_1449: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7bff; +op3val:0x8400; valaddr_reg:x2; val_offset:4245*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4245*FLEN/8, x3, x1, x4) + +inst_1450: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7bff; +op3val:0x401; valaddr_reg:x2; val_offset:4248*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4248*FLEN/8, x3, x1, x4) + +inst_1451: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7bff; +op3val:0x8455; valaddr_reg:x2; val_offset:4251*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4251*FLEN/8, x3, x1, x4) + +inst_1452: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7bff; +op3val:0x7bff; valaddr_reg:x2; val_offset:4254*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4254*FLEN/8, x3, x1, x4) + +inst_1453: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7bff; +op3val:0xfbff; valaddr_reg:x2; val_offset:4257*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4257*FLEN/8, x3, x1, x4) + +inst_1454: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7bff; +op3val:0x7c00; valaddr_reg:x2; val_offset:4260*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4260*FLEN/8, x3, x1, x4) + +inst_1455: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7bff; +op3val:0xfc00; valaddr_reg:x2; val_offset:4263*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4263*FLEN/8, x3, x1, x4) + +inst_1456: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7bff; +op3val:0x7e00; valaddr_reg:x2; val_offset:4266*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4266*FLEN/8, x3, x1, x4) + +inst_1457: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7bff; +op3val:0xfe00; valaddr_reg:x2; val_offset:4269*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4269*FLEN/8, x3, x1, x4) + +inst_1458: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7bff; +op3val:0x7e01; valaddr_reg:x2; val_offset:4272*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4272*FLEN/8, x3, x1, x4) + +inst_1459: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7bff; +op3val:0xfe55; valaddr_reg:x2; val_offset:4275*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4275*FLEN/8, x3, x1, x4) + +inst_1460: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7bff; +op3val:0x7c01; valaddr_reg:x2; val_offset:4278*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4278*FLEN/8, x3, x1, x4) + +inst_1461: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7bff; +op3val:0xfd55; valaddr_reg:x2; val_offset:4281*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4281*FLEN/8, x3, x1, x4) + +inst_1462: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7bff; +op3val:0x3c00; valaddr_reg:x2; val_offset:4284*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4284*FLEN/8, x3, x1, x4) + +inst_1463: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7bff; +op3val:0xbc00; valaddr_reg:x2; val_offset:4287*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4287*FLEN/8, x3, x1, x4) + +inst_1464: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfbff; +op3val:0x0; valaddr_reg:x2; val_offset:4290*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4290*FLEN/8, x3, x1, x4) + +inst_1465: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfbff; +op3val:0x8000; valaddr_reg:x2; val_offset:4293*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4293*FLEN/8, x3, x1, x4) + +inst_1466: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfbff; +op3val:0x1; valaddr_reg:x2; val_offset:4296*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4296*FLEN/8, x3, x1, x4) + +inst_1467: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfbff; +op3val:0x8001; valaddr_reg:x2; val_offset:4299*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4299*FLEN/8, x3, x1, x4) + +inst_1468: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfbff; +op3val:0x2; valaddr_reg:x2; val_offset:4302*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4302*FLEN/8, x3, x1, x4) + +inst_1469: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfbff; +op3val:0x83fe; valaddr_reg:x2; val_offset:4305*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4305*FLEN/8, x3, x1, x4) + +inst_1470: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfbff; +op3val:0x3ff; valaddr_reg:x2; val_offset:4308*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4308*FLEN/8, x3, x1, x4) + +inst_1471: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfbff; +op3val:0x83ff; valaddr_reg:x2; val_offset:4311*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4311*FLEN/8, x3, x1, x4) + +inst_1472: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfbff; +op3val:0x400; valaddr_reg:x2; val_offset:4314*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4314*FLEN/8, x3, x1, x4) + +inst_1473: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfbff; +op3val:0x8400; valaddr_reg:x2; val_offset:4317*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4317*FLEN/8, x3, x1, x4) + +inst_1474: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfbff; +op3val:0x401; valaddr_reg:x2; val_offset:4320*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4320*FLEN/8, x3, x1, x4) + +inst_1475: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfbff; +op3val:0x8455; valaddr_reg:x2; val_offset:4323*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4323*FLEN/8, x3, x1, x4) + +inst_1476: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfbff; +op3val:0x7bff; valaddr_reg:x2; val_offset:4326*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4326*FLEN/8, x3, x1, x4) + +inst_1477: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfbff; +op3val:0xfbff; valaddr_reg:x2; val_offset:4329*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4329*FLEN/8, x3, x1, x4) + +inst_1478: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfbff; +op3val:0x7c00; valaddr_reg:x2; val_offset:4332*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4332*FLEN/8, x3, x1, x4) + +inst_1479: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfbff; +op3val:0xfc00; valaddr_reg:x2; val_offset:4335*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4335*FLEN/8, x3, x1, x4) + +inst_1480: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfbff; +op3val:0x7e00; valaddr_reg:x2; val_offset:4338*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4338*FLEN/8, x3, x1, x4) + +inst_1481: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfbff; +op3val:0xfe00; valaddr_reg:x2; val_offset:4341*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4341*FLEN/8, x3, x1, x4) + +inst_1482: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfbff; +op3val:0x7e01; valaddr_reg:x2; val_offset:4344*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4344*FLEN/8, x3, x1, x4) + +inst_1483: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfbff; +op3val:0xfe55; valaddr_reg:x2; val_offset:4347*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4347*FLEN/8, x3, x1, x4) + +inst_1484: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfbff; +op3val:0x7c01; valaddr_reg:x2; val_offset:4350*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4350*FLEN/8, x3, x1, x4) + +inst_1485: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfbff; +op3val:0xfd55; valaddr_reg:x2; val_offset:4353*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4353*FLEN/8, x3, x1, x4) + +inst_1486: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfbff; +op3val:0x3c00; valaddr_reg:x2; val_offset:4356*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4356*FLEN/8, x3, x1, x4) + +inst_1487: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfbff; +op3val:0xbc00; valaddr_reg:x2; val_offset:4359*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4359*FLEN/8, x3, x1, x4) + +inst_1488: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7c00; +op3val:0x0; valaddr_reg:x2; val_offset:4362*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4362*FLEN/8, x3, x1, x4) + +inst_1489: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7c00; +op3val:0x8000; valaddr_reg:x2; val_offset:4365*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4365*FLEN/8, x3, x1, x4) + +inst_1490: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7c00; +op3val:0x1; valaddr_reg:x2; val_offset:4368*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4368*FLEN/8, x3, x1, x4) + +inst_1491: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7c00; +op3val:0x8001; valaddr_reg:x2; val_offset:4371*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4371*FLEN/8, x3, x1, x4) + +inst_1492: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7c00; +op3val:0x2; valaddr_reg:x2; val_offset:4374*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4374*FLEN/8, x3, x1, x4) + +inst_1493: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7c00; +op3val:0x83fe; valaddr_reg:x2; val_offset:4377*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4377*FLEN/8, x3, x1, x4) + +inst_1494: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7c00; +op3val:0x3ff; valaddr_reg:x2; val_offset:4380*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4380*FLEN/8, x3, x1, x4) + +inst_1495: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7c00; +op3val:0x83ff; valaddr_reg:x2; val_offset:4383*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4383*FLEN/8, x3, x1, x4) + +inst_1496: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7c00; +op3val:0x400; valaddr_reg:x2; val_offset:4386*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4386*FLEN/8, x3, x1, x4) + +inst_1497: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7c00; +op3val:0x8400; valaddr_reg:x2; val_offset:4389*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4389*FLEN/8, x3, x1, x4) + +inst_1498: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7c00; +op3val:0x401; valaddr_reg:x2; val_offset:4392*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4392*FLEN/8, x3, x1, x4) + +inst_1499: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7c00; +op3val:0x8455; valaddr_reg:x2; val_offset:4395*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4395*FLEN/8, x3, x1, x4) + +inst_1500: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7c00; +op3val:0x7bff; valaddr_reg:x2; val_offset:4398*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4398*FLEN/8, x3, x1, x4) + +inst_1501: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7c00; +op3val:0xfbff; valaddr_reg:x2; val_offset:4401*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4401*FLEN/8, x3, x1, x4) + +inst_1502: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7c00; +op3val:0x7c00; valaddr_reg:x2; val_offset:4404*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4404*FLEN/8, x3, x1, x4) + +inst_1503: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7c00; +op3val:0xfc00; valaddr_reg:x2; val_offset:4407*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4407*FLEN/8, x3, x1, x4) + +inst_1504: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7c00; +op3val:0x7e00; valaddr_reg:x2; val_offset:4410*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4410*FLEN/8, x3, x1, x4) + +inst_1505: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7c00; +op3val:0xfe00; valaddr_reg:x2; val_offset:4413*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4413*FLEN/8, x3, x1, x4) + +inst_1506: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7c00; +op3val:0x7e01; valaddr_reg:x2; val_offset:4416*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4416*FLEN/8, x3, x1, x4) + +inst_1507: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7c00; +op3val:0xfe55; valaddr_reg:x2; val_offset:4419*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4419*FLEN/8, x3, x1, x4) + +inst_1508: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7c00; +op3val:0x7c01; valaddr_reg:x2; val_offset:4422*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4422*FLEN/8, x3, x1, x4) + +inst_1509: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7c00; +op3val:0xfd55; valaddr_reg:x2; val_offset:4425*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4425*FLEN/8, x3, x1, x4) + +inst_1510: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7c00; +op3val:0x3c00; valaddr_reg:x2; val_offset:4428*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4428*FLEN/8, x3, x1, x4) + +inst_1511: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7c00; +op3val:0xbc00; valaddr_reg:x2; val_offset:4431*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4431*FLEN/8, x3, x1, x4) + +inst_1512: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfc00; +op3val:0x0; valaddr_reg:x2; val_offset:4434*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4434*FLEN/8, x3, x1, x4) + +inst_1513: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfc00; +op3val:0x8000; valaddr_reg:x2; val_offset:4437*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4437*FLEN/8, x3, x1, x4) + +inst_1514: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfc00; +op3val:0x1; valaddr_reg:x2; val_offset:4440*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4440*FLEN/8, x3, x1, x4) + +inst_1515: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfc00; +op3val:0x8001; valaddr_reg:x2; val_offset:4443*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4443*FLEN/8, x3, x1, x4) + +inst_1516: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfc00; +op3val:0x2; valaddr_reg:x2; val_offset:4446*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4446*FLEN/8, x3, x1, x4) + +inst_1517: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfc00; +op3val:0x83fe; valaddr_reg:x2; val_offset:4449*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4449*FLEN/8, x3, x1, x4) + +inst_1518: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfc00; +op3val:0x3ff; valaddr_reg:x2; val_offset:4452*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4452*FLEN/8, x3, x1, x4) + +inst_1519: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfc00; +op3val:0x83ff; valaddr_reg:x2; val_offset:4455*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4455*FLEN/8, x3, x1, x4) + +inst_1520: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfc00; +op3val:0x400; valaddr_reg:x2; val_offset:4458*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4458*FLEN/8, x3, x1, x4) + +inst_1521: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfc00; +op3val:0x8400; valaddr_reg:x2; val_offset:4461*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4461*FLEN/8, x3, x1, x4) + +inst_1522: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfc00; +op3val:0x401; valaddr_reg:x2; val_offset:4464*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4464*FLEN/8, x3, x1, x4) + +inst_1523: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfc00; +op3val:0x8455; valaddr_reg:x2; val_offset:4467*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4467*FLEN/8, x3, x1, x4) + +inst_1524: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfc00; +op3val:0x7bff; valaddr_reg:x2; val_offset:4470*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4470*FLEN/8, x3, x1, x4) + +inst_1525: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfc00; +op3val:0xfbff; valaddr_reg:x2; val_offset:4473*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4473*FLEN/8, x3, x1, x4) + +inst_1526: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfc00; +op3val:0x7c00; valaddr_reg:x2; val_offset:4476*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4476*FLEN/8, x3, x1, x4) + +inst_1527: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfc00; +op3val:0xfc00; valaddr_reg:x2; val_offset:4479*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4479*FLEN/8, x3, x1, x4) + +inst_1528: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfc00; +op3val:0x7e00; valaddr_reg:x2; val_offset:4482*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4482*FLEN/8, x3, x1, x4) + +inst_1529: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfc00; +op3val:0xfe00; valaddr_reg:x2; val_offset:4485*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4485*FLEN/8, x3, x1, x4) + +inst_1530: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfc00; +op3val:0x7e01; valaddr_reg:x2; val_offset:4488*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4488*FLEN/8, x3, x1, x4) + +inst_1531: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfc00; +op3val:0xfe55; valaddr_reg:x2; val_offset:4491*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4491*FLEN/8, x3, x1, x4) + +inst_1532: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfc00; +op3val:0x7c01; valaddr_reg:x2; val_offset:4494*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4494*FLEN/8, x3, x1, x4) + +inst_1533: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfc00; +op3val:0xfd55; valaddr_reg:x2; val_offset:4497*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4497*FLEN/8, x3, x1, x4) + +inst_1534: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfc00; +op3val:0x3c00; valaddr_reg:x2; val_offset:4500*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4500*FLEN/8, x3, x1, x4) + +inst_1535: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfc00; +op3val:0xbc00; valaddr_reg:x2; val_offset:4503*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4503*FLEN/8, x3, x1, x4) + +inst_1536: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7e00; +op3val:0x0; valaddr_reg:x2; val_offset:4506*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4506*FLEN/8, x3, x1, x4) + +inst_1537: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7e00; +op3val:0x8000; valaddr_reg:x2; val_offset:4509*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4509*FLEN/8, x3, x1, x4) + +inst_1538: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7e00; +op3val:0x1; valaddr_reg:x2; val_offset:4512*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4512*FLEN/8, x3, x1, x4) + +inst_1539: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7e00; +op3val:0x8001; valaddr_reg:x2; val_offset:4515*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4515*FLEN/8, x3, x1, x4) + +inst_1540: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7e00; +op3val:0x2; valaddr_reg:x2; val_offset:4518*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4518*FLEN/8, x3, x1, x4) + +inst_1541: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7e00; +op3val:0x83fe; valaddr_reg:x2; val_offset:4521*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4521*FLEN/8, x3, x1, x4) + +inst_1542: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7e00; +op3val:0x3ff; valaddr_reg:x2; val_offset:4524*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4524*FLEN/8, x3, x1, x4) + +inst_1543: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7e00; +op3val:0x83ff; valaddr_reg:x2; val_offset:4527*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4527*FLEN/8, x3, x1, x4) + +inst_1544: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7e00; +op3val:0x400; valaddr_reg:x2; val_offset:4530*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4530*FLEN/8, x3, x1, x4) + +inst_1545: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7e00; +op3val:0x8400; valaddr_reg:x2; val_offset:4533*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4533*FLEN/8, x3, x1, x4) + +inst_1546: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7e00; +op3val:0x401; valaddr_reg:x2; val_offset:4536*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4536*FLEN/8, x3, x1, x4) + +inst_1547: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7e00; +op3val:0x8455; valaddr_reg:x2; val_offset:4539*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4539*FLEN/8, x3, x1, x4) + +inst_1548: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7e00; +op3val:0x7bff; valaddr_reg:x2; val_offset:4542*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4542*FLEN/8, x3, x1, x4) + +inst_1549: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7e00; +op3val:0xfbff; valaddr_reg:x2; val_offset:4545*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4545*FLEN/8, x3, x1, x4) + +inst_1550: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7e00; +op3val:0x7c00; valaddr_reg:x2; val_offset:4548*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4548*FLEN/8, x3, x1, x4) + +inst_1551: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7e00; +op3val:0xfc00; valaddr_reg:x2; val_offset:4551*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4551*FLEN/8, x3, x1, x4) + +inst_1552: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7e00; +op3val:0x7e00; valaddr_reg:x2; val_offset:4554*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4554*FLEN/8, x3, x1, x4) + +inst_1553: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7e00; +op3val:0xfe00; valaddr_reg:x2; val_offset:4557*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4557*FLEN/8, x3, x1, x4) + +inst_1554: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7e00; +op3val:0x7e01; valaddr_reg:x2; val_offset:4560*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4560*FLEN/8, x3, x1, x4) + +inst_1555: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7e00; +op3val:0xfe55; valaddr_reg:x2; val_offset:4563*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4563*FLEN/8, x3, x1, x4) + +inst_1556: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7e00; +op3val:0x7c01; valaddr_reg:x2; val_offset:4566*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4566*FLEN/8, x3, x1, x4) + +inst_1557: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7e00; +op3val:0xfd55; valaddr_reg:x2; val_offset:4569*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4569*FLEN/8, x3, x1, x4) + +inst_1558: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7e00; +op3val:0x3c00; valaddr_reg:x2; val_offset:4572*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4572*FLEN/8, x3, x1, x4) + +inst_1559: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7e00; +op3val:0xbc00; valaddr_reg:x2; val_offset:4575*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4575*FLEN/8, x3, x1, x4) + +inst_1560: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfe00; +op3val:0x0; valaddr_reg:x2; val_offset:4578*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4578*FLEN/8, x3, x1, x4) + +inst_1561: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfe00; +op3val:0x8000; valaddr_reg:x2; val_offset:4581*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4581*FLEN/8, x3, x1, x4) + +inst_1562: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfe00; +op3val:0x1; valaddr_reg:x2; val_offset:4584*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4584*FLEN/8, x3, x1, x4) + +inst_1563: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfe00; +op3val:0x8001; valaddr_reg:x2; val_offset:4587*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4587*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_13) + +inst_1564: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfe00; +op3val:0x2; valaddr_reg:x2; val_offset:4590*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4590*FLEN/8, x3, x1, x4) + +inst_1565: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfe00; +op3val:0x83fe; valaddr_reg:x2; val_offset:4593*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4593*FLEN/8, x3, x1, x4) + +inst_1566: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfe00; +op3val:0x3ff; valaddr_reg:x2; val_offset:4596*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4596*FLEN/8, x3, x1, x4) + +inst_1567: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfe00; +op3val:0x83ff; valaddr_reg:x2; val_offset:4599*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4599*FLEN/8, x3, x1, x4) + +inst_1568: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfe00; +op3val:0x400; valaddr_reg:x2; val_offset:4602*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4602*FLEN/8, x3, x1, x4) + +inst_1569: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfe00; +op3val:0x8400; valaddr_reg:x2; val_offset:4605*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4605*FLEN/8, x3, x1, x4) + +inst_1570: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfe00; +op3val:0x401; valaddr_reg:x2; val_offset:4608*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4608*FLEN/8, x3, x1, x4) + +inst_1571: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfe00; +op3val:0x8455; valaddr_reg:x2; val_offset:4611*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4611*FLEN/8, x3, x1, x4) + +inst_1572: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfe00; +op3val:0x7bff; valaddr_reg:x2; val_offset:4614*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4614*FLEN/8, x3, x1, x4) + +inst_1573: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfe00; +op3val:0xfbff; valaddr_reg:x2; val_offset:4617*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4617*FLEN/8, x3, x1, x4) + +inst_1574: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfe00; +op3val:0x7c00; valaddr_reg:x2; val_offset:4620*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4620*FLEN/8, x3, x1, x4) + +inst_1575: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfe00; +op3val:0xfc00; valaddr_reg:x2; val_offset:4623*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4623*FLEN/8, x3, x1, x4) + +inst_1576: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfe00; +op3val:0x7e00; valaddr_reg:x2; val_offset:4626*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4626*FLEN/8, x3, x1, x4) + +inst_1577: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfe00; +op3val:0xfe00; valaddr_reg:x2; val_offset:4629*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4629*FLEN/8, x3, x1, x4) + +inst_1578: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfe00; +op3val:0x7e01; valaddr_reg:x2; val_offset:4632*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4632*FLEN/8, x3, x1, x4) + +inst_1579: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfe00; +op3val:0xfe55; valaddr_reg:x2; val_offset:4635*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4635*FLEN/8, x3, x1, x4) + +inst_1580: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfe00; +op3val:0x7c01; valaddr_reg:x2; val_offset:4638*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4638*FLEN/8, x3, x1, x4) + +inst_1581: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfe00; +op3val:0xfd55; valaddr_reg:x2; val_offset:4641*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4641*FLEN/8, x3, x1, x4) + +inst_1582: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfe00; +op3val:0x3c00; valaddr_reg:x2; val_offset:4644*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4644*FLEN/8, x3, x1, x4) + +inst_1583: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfe00; +op3val:0xbc00; valaddr_reg:x2; val_offset:4647*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4647*FLEN/8, x3, x1, x4) + +inst_1584: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7e01; +op3val:0x0; valaddr_reg:x2; val_offset:4650*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4650*FLEN/8, x3, x1, x4) + +inst_1585: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7e01; +op3val:0x8000; valaddr_reg:x2; val_offset:4653*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4653*FLEN/8, x3, x1, x4) + +inst_1586: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7e01; +op3val:0x1; valaddr_reg:x2; val_offset:4656*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4656*FLEN/8, x3, x1, x4) + +inst_1587: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7e01; +op3val:0x8001; valaddr_reg:x2; val_offset:4659*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4659*FLEN/8, x3, x1, x4) + +inst_1588: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7e01; +op3val:0x2; valaddr_reg:x2; val_offset:4662*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4662*FLEN/8, x3, x1, x4) + +inst_1589: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7e01; +op3val:0x83fe; valaddr_reg:x2; val_offset:4665*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4665*FLEN/8, x3, x1, x4) + +inst_1590: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7e01; +op3val:0x3ff; valaddr_reg:x2; val_offset:4668*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4668*FLEN/8, x3, x1, x4) + +inst_1591: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7e01; +op3val:0x83ff; valaddr_reg:x2; val_offset:4671*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4671*FLEN/8, x3, x1, x4) + +inst_1592: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7e01; +op3val:0x400; valaddr_reg:x2; val_offset:4674*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4674*FLEN/8, x3, x1, x4) + +inst_1593: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7e01; +op3val:0x8400; valaddr_reg:x2; val_offset:4677*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4677*FLEN/8, x3, x1, x4) + +inst_1594: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7e01; +op3val:0x401; valaddr_reg:x2; val_offset:4680*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4680*FLEN/8, x3, x1, x4) + +inst_1595: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7e01; +op3val:0x8455; valaddr_reg:x2; val_offset:4683*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4683*FLEN/8, x3, x1, x4) + +inst_1596: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7e01; +op3val:0x7bff; valaddr_reg:x2; val_offset:4686*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4686*FLEN/8, x3, x1, x4) + +inst_1597: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7e01; +op3val:0xfbff; valaddr_reg:x2; val_offset:4689*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4689*FLEN/8, x3, x1, x4) + +inst_1598: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7e01; +op3val:0x7c00; valaddr_reg:x2; val_offset:4692*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4692*FLEN/8, x3, x1, x4) + +inst_1599: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7e01; +op3val:0xfc00; valaddr_reg:x2; val_offset:4695*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4695*FLEN/8, x3, x1, x4) + +inst_1600: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7e01; +op3val:0x7e00; valaddr_reg:x2; val_offset:4698*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4698*FLEN/8, x3, x1, x4) + +inst_1601: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7e01; +op3val:0xfe00; valaddr_reg:x2; val_offset:4701*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4701*FLEN/8, x3, x1, x4) + +inst_1602: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7e01; +op3val:0x7e01; valaddr_reg:x2; val_offset:4704*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4704*FLEN/8, x3, x1, x4) + +inst_1603: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7e01; +op3val:0xfe55; valaddr_reg:x2; val_offset:4707*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4707*FLEN/8, x3, x1, x4) + +inst_1604: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7e01; +op3val:0x7c01; valaddr_reg:x2; val_offset:4710*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4710*FLEN/8, x3, x1, x4) + +inst_1605: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7e01; +op3val:0xfd55; valaddr_reg:x2; val_offset:4713*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4713*FLEN/8, x3, x1, x4) + +inst_1606: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7e01; +op3val:0x3c00; valaddr_reg:x2; val_offset:4716*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4716*FLEN/8, x3, x1, x4) + +inst_1607: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7e01; +op3val:0xbc00; valaddr_reg:x2; val_offset:4719*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4719*FLEN/8, x3, x1, x4) + +inst_1608: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfe55; +op3val:0x0; valaddr_reg:x2; val_offset:4722*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4722*FLEN/8, x3, x1, x4) + +inst_1609: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfe55; +op3val:0x8000; valaddr_reg:x2; val_offset:4725*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4725*FLEN/8, x3, x1, x4) + +inst_1610: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfe55; +op3val:0x1; valaddr_reg:x2; val_offset:4728*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4728*FLEN/8, x3, x1, x4) + +inst_1611: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfe55; +op3val:0x8001; valaddr_reg:x2; val_offset:4731*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4731*FLEN/8, x3, x1, x4) + +inst_1612: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfe55; +op3val:0x2; valaddr_reg:x2; val_offset:4734*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4734*FLEN/8, x3, x1, x4) + +inst_1613: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfe55; +op3val:0x83fe; valaddr_reg:x2; val_offset:4737*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4737*FLEN/8, x3, x1, x4) + +inst_1614: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfe55; +op3val:0x3ff; valaddr_reg:x2; val_offset:4740*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4740*FLEN/8, x3, x1, x4) + +inst_1615: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfe55; +op3val:0x83ff; valaddr_reg:x2; val_offset:4743*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4743*FLEN/8, x3, x1, x4) + +inst_1616: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfe55; +op3val:0x400; valaddr_reg:x2; val_offset:4746*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4746*FLEN/8, x3, x1, x4) + +inst_1617: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfe55; +op3val:0x8400; valaddr_reg:x2; val_offset:4749*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4749*FLEN/8, x3, x1, x4) + +inst_1618: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfe55; +op3val:0x401; valaddr_reg:x2; val_offset:4752*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4752*FLEN/8, x3, x1, x4) + +inst_1619: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfe55; +op3val:0x8455; valaddr_reg:x2; val_offset:4755*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4755*FLEN/8, x3, x1, x4) + +inst_1620: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfe55; +op3val:0x7bff; valaddr_reg:x2; val_offset:4758*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4758*FLEN/8, x3, x1, x4) + +inst_1621: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfe55; +op3val:0xfbff; valaddr_reg:x2; val_offset:4761*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4761*FLEN/8, x3, x1, x4) + +inst_1622: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfe55; +op3val:0x7c00; valaddr_reg:x2; val_offset:4764*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4764*FLEN/8, x3, x1, x4) + +inst_1623: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfe55; +op3val:0xfc00; valaddr_reg:x2; val_offset:4767*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4767*FLEN/8, x3, x1, x4) + +inst_1624: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfe55; +op3val:0x7e00; valaddr_reg:x2; val_offset:4770*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4770*FLEN/8, x3, x1, x4) + +inst_1625: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfe55; +op3val:0xfe00; valaddr_reg:x2; val_offset:4773*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4773*FLEN/8, x3, x1, x4) + +inst_1626: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfe55; +op3val:0x7e01; valaddr_reg:x2; val_offset:4776*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4776*FLEN/8, x3, x1, x4) + +inst_1627: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfe55; +op3val:0xfe55; valaddr_reg:x2; val_offset:4779*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4779*FLEN/8, x3, x1, x4) + +inst_1628: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfe55; +op3val:0x7c01; valaddr_reg:x2; val_offset:4782*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4782*FLEN/8, x3, x1, x4) + +inst_1629: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfe55; +op3val:0xfd55; valaddr_reg:x2; val_offset:4785*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4785*FLEN/8, x3, x1, x4) + +inst_1630: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfe55; +op3val:0x3c00; valaddr_reg:x2; val_offset:4788*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4788*FLEN/8, x3, x1, x4) + +inst_1631: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfe55; +op3val:0xbc00; valaddr_reg:x2; val_offset:4791*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4791*FLEN/8, x3, x1, x4) + +inst_1632: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7c01; +op3val:0x0; valaddr_reg:x2; val_offset:4794*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4794*FLEN/8, x3, x1, x4) + +inst_1633: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7c01; +op3val:0x8000; valaddr_reg:x2; val_offset:4797*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4797*FLEN/8, x3, x1, x4) + +inst_1634: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7c01; +op3val:0x1; valaddr_reg:x2; val_offset:4800*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4800*FLEN/8, x3, x1, x4) + +inst_1635: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7c01; +op3val:0x8001; valaddr_reg:x2; val_offset:4803*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4803*FLEN/8, x3, x1, x4) + +inst_1636: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7c01; +op3val:0x2; valaddr_reg:x2; val_offset:4806*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4806*FLEN/8, x3, x1, x4) + +inst_1637: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7c01; +op3val:0x83fe; valaddr_reg:x2; val_offset:4809*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4809*FLEN/8, x3, x1, x4) + +inst_1638: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7c01; +op3val:0x3ff; valaddr_reg:x2; val_offset:4812*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4812*FLEN/8, x3, x1, x4) + +inst_1639: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7c01; +op3val:0x83ff; valaddr_reg:x2; val_offset:4815*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4815*FLEN/8, x3, x1, x4) + +inst_1640: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7c01; +op3val:0x400; valaddr_reg:x2; val_offset:4818*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4818*FLEN/8, x3, x1, x4) + +inst_1641: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7c01; +op3val:0x8400; valaddr_reg:x2; val_offset:4821*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4821*FLEN/8, x3, x1, x4) + +inst_1642: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7c01; +op3val:0x401; valaddr_reg:x2; val_offset:4824*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4824*FLEN/8, x3, x1, x4) + +inst_1643: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7c01; +op3val:0x8455; valaddr_reg:x2; val_offset:4827*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4827*FLEN/8, x3, x1, x4) + +inst_1644: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7c01; +op3val:0x7bff; valaddr_reg:x2; val_offset:4830*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4830*FLEN/8, x3, x1, x4) + +inst_1645: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7c01; +op3val:0xfbff; valaddr_reg:x2; val_offset:4833*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4833*FLEN/8, x3, x1, x4) + +inst_1646: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7c01; +op3val:0x7c00; valaddr_reg:x2; val_offset:4836*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4836*FLEN/8, x3, x1, x4) + +inst_1647: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7c01; +op3val:0xfc00; valaddr_reg:x2; val_offset:4839*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4839*FLEN/8, x3, x1, x4) + +inst_1648: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7c01; +op3val:0x7e00; valaddr_reg:x2; val_offset:4842*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4842*FLEN/8, x3, x1, x4) + +inst_1649: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7c01; +op3val:0xfe00; valaddr_reg:x2; val_offset:4845*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4845*FLEN/8, x3, x1, x4) + +inst_1650: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7c01; +op3val:0x7e01; valaddr_reg:x2; val_offset:4848*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4848*FLEN/8, x3, x1, x4) + +inst_1651: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7c01; +op3val:0xfe55; valaddr_reg:x2; val_offset:4851*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4851*FLEN/8, x3, x1, x4) + +inst_1652: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7c01; +op3val:0x7c01; valaddr_reg:x2; val_offset:4854*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4854*FLEN/8, x3, x1, x4) + +inst_1653: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7c01; +op3val:0xfd55; valaddr_reg:x2; val_offset:4857*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4857*FLEN/8, x3, x1, x4) + +inst_1654: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7c01; +op3val:0x3c00; valaddr_reg:x2; val_offset:4860*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4860*FLEN/8, x3, x1, x4) + +inst_1655: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7c01; +op3val:0xbc00; valaddr_reg:x2; val_offset:4863*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4863*FLEN/8, x3, x1, x4) + +inst_1656: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfd55; +op3val:0x0; valaddr_reg:x2; val_offset:4866*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4866*FLEN/8, x3, x1, x4) + +inst_1657: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfd55; +op3val:0x8000; valaddr_reg:x2; val_offset:4869*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4869*FLEN/8, x3, x1, x4) + +inst_1658: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfd55; +op3val:0x1; valaddr_reg:x2; val_offset:4872*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4872*FLEN/8, x3, x1, x4) + +inst_1659: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfd55; +op3val:0x8001; valaddr_reg:x2; val_offset:4875*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4875*FLEN/8, x3, x1, x4) + +inst_1660: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfd55; +op3val:0x2; valaddr_reg:x2; val_offset:4878*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4878*FLEN/8, x3, x1, x4) + +inst_1661: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfd55; +op3val:0x83fe; valaddr_reg:x2; val_offset:4881*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4881*FLEN/8, x3, x1, x4) + +inst_1662: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfd55; +op3val:0x3ff; valaddr_reg:x2; val_offset:4884*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4884*FLEN/8, x3, x1, x4) + +inst_1663: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfd55; +op3val:0x83ff; valaddr_reg:x2; val_offset:4887*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4887*FLEN/8, x3, x1, x4) + +inst_1664: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfd55; +op3val:0x400; valaddr_reg:x2; val_offset:4890*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4890*FLEN/8, x3, x1, x4) + +inst_1665: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfd55; +op3val:0x8400; valaddr_reg:x2; val_offset:4893*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4893*FLEN/8, x3, x1, x4) + +inst_1666: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfd55; +op3val:0x401; valaddr_reg:x2; val_offset:4896*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4896*FLEN/8, x3, x1, x4) + +inst_1667: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfd55; +op3val:0x8455; valaddr_reg:x2; val_offset:4899*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4899*FLEN/8, x3, x1, x4) + +inst_1668: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfd55; +op3val:0x7bff; valaddr_reg:x2; val_offset:4902*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4902*FLEN/8, x3, x1, x4) + +inst_1669: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfd55; +op3val:0xfbff; valaddr_reg:x2; val_offset:4905*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4905*FLEN/8, x3, x1, x4) + +inst_1670: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfd55; +op3val:0x7c00; valaddr_reg:x2; val_offset:4908*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4908*FLEN/8, x3, x1, x4) + +inst_1671: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfd55; +op3val:0xfc00; valaddr_reg:x2; val_offset:4911*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4911*FLEN/8, x3, x1, x4) + +inst_1672: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfd55; +op3val:0x7e00; valaddr_reg:x2; val_offset:4914*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4914*FLEN/8, x3, x1, x4) + +inst_1673: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfd55; +op3val:0xfe00; valaddr_reg:x2; val_offset:4917*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4917*FLEN/8, x3, x1, x4) + +inst_1674: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfd55; +op3val:0x7e01; valaddr_reg:x2; val_offset:4920*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4920*FLEN/8, x3, x1, x4) + +inst_1675: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfd55; +op3val:0xfe55; valaddr_reg:x2; val_offset:4923*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4923*FLEN/8, x3, x1, x4) + +inst_1676: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfd55; +op3val:0x7c01; valaddr_reg:x2; val_offset:4926*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4926*FLEN/8, x3, x1, x4) + +inst_1677: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfd55; +op3val:0xfd55; valaddr_reg:x2; val_offset:4929*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4929*FLEN/8, x3, x1, x4) + +inst_1678: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfd55; +op3val:0x3c00; valaddr_reg:x2; val_offset:4932*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4932*FLEN/8, x3, x1, x4) + +inst_1679: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xfd55; +op3val:0xbc00; valaddr_reg:x2; val_offset:4935*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4935*FLEN/8, x3, x1, x4) + +inst_1680: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3c00; +op3val:0x0; valaddr_reg:x2; val_offset:4938*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4938*FLEN/8, x3, x1, x4) + +inst_1681: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3c00; +op3val:0x8000; valaddr_reg:x2; val_offset:4941*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4941*FLEN/8, x3, x1, x4) + +inst_1682: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3c00; +op3val:0x1; valaddr_reg:x2; val_offset:4944*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4944*FLEN/8, x3, x1, x4) + +inst_1683: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3c00; +op3val:0x8001; valaddr_reg:x2; val_offset:4947*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4947*FLEN/8, x3, x1, x4) + +inst_1684: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3c00; +op3val:0x2; valaddr_reg:x2; val_offset:4950*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4950*FLEN/8, x3, x1, x4) + +inst_1685: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3c00; +op3val:0x83fe; valaddr_reg:x2; val_offset:4953*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4953*FLEN/8, x3, x1, x4) + +inst_1686: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3c00; +op3val:0x3ff; valaddr_reg:x2; val_offset:4956*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4956*FLEN/8, x3, x1, x4) + +inst_1687: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3c00; +op3val:0x83ff; valaddr_reg:x2; val_offset:4959*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4959*FLEN/8, x3, x1, x4) + +inst_1688: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3c00; +op3val:0x400; valaddr_reg:x2; val_offset:4962*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4962*FLEN/8, x3, x1, x4) + +inst_1689: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3c00; +op3val:0x8400; valaddr_reg:x2; val_offset:4965*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4965*FLEN/8, x3, x1, x4) + +inst_1690: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3c00; +op3val:0x401; valaddr_reg:x2; val_offset:4968*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4968*FLEN/8, x3, x1, x4) + +inst_1691: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3c00; +op3val:0x8455; valaddr_reg:x2; val_offset:4971*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4971*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_14) + +inst_1692: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3c00; +op3val:0x7bff; valaddr_reg:x2; val_offset:4974*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4974*FLEN/8, x3, x1, x4) + +inst_1693: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3c00; +op3val:0xfbff; valaddr_reg:x2; val_offset:4977*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4977*FLEN/8, x3, x1, x4) + +inst_1694: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3c00; +op3val:0x7c00; valaddr_reg:x2; val_offset:4980*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4980*FLEN/8, x3, x1, x4) + +inst_1695: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3c00; +op3val:0xfc00; valaddr_reg:x2; val_offset:4983*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4983*FLEN/8, x3, x1, x4) + +inst_1696: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3c00; +op3val:0x7e00; valaddr_reg:x2; val_offset:4986*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4986*FLEN/8, x3, x1, x4) + +inst_1697: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3c00; +op3val:0xfe00; valaddr_reg:x2; val_offset:4989*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4989*FLEN/8, x3, x1, x4) + +inst_1698: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3c00; +op3val:0x7e01; valaddr_reg:x2; val_offset:4992*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4992*FLEN/8, x3, x1, x4) + +inst_1699: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3c00; +op3val:0xfe55; valaddr_reg:x2; val_offset:4995*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4995*FLEN/8, x3, x1, x4) + +inst_1700: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3c00; +op3val:0x7c01; valaddr_reg:x2; val_offset:4998*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 4998*FLEN/8, x3, x1, x4) + +inst_1701: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3c00; +op3val:0xfd55; valaddr_reg:x2; val_offset:5001*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5001*FLEN/8, x3, x1, x4) + +inst_1702: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3c00; +op3val:0x3c00; valaddr_reg:x2; val_offset:5004*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5004*FLEN/8, x3, x1, x4) + +inst_1703: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3c00; +op3val:0xbc00; valaddr_reg:x2; val_offset:5007*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5007*FLEN/8, x3, x1, x4) + +inst_1704: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xbc00; +op3val:0x0; valaddr_reg:x2; val_offset:5010*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5010*FLEN/8, x3, x1, x4) + +inst_1705: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xbc00; +op3val:0x8000; valaddr_reg:x2; val_offset:5013*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5013*FLEN/8, x3, x1, x4) + +inst_1706: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xbc00; +op3val:0x1; valaddr_reg:x2; val_offset:5016*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5016*FLEN/8, x3, x1, x4) + +inst_1707: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xbc00; +op3val:0x8001; valaddr_reg:x2; val_offset:5019*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5019*FLEN/8, x3, x1, x4) + +inst_1708: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xbc00; +op3val:0x2; valaddr_reg:x2; val_offset:5022*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5022*FLEN/8, x3, x1, x4) + +inst_1709: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xbc00; +op3val:0x83fe; valaddr_reg:x2; val_offset:5025*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5025*FLEN/8, x3, x1, x4) + +inst_1710: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xbc00; +op3val:0x3ff; valaddr_reg:x2; val_offset:5028*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5028*FLEN/8, x3, x1, x4) + +inst_1711: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xbc00; +op3val:0x83ff; valaddr_reg:x2; val_offset:5031*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5031*FLEN/8, x3, x1, x4) + +inst_1712: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xbc00; +op3val:0x400; valaddr_reg:x2; val_offset:5034*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5034*FLEN/8, x3, x1, x4) + +inst_1713: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xbc00; +op3val:0x8400; valaddr_reg:x2; val_offset:5037*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5037*FLEN/8, x3, x1, x4) + +inst_1714: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xbc00; +op3val:0x401; valaddr_reg:x2; val_offset:5040*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5040*FLEN/8, x3, x1, x4) + +inst_1715: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xbc00; +op3val:0x8455; valaddr_reg:x2; val_offset:5043*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5043*FLEN/8, x3, x1, x4) + +inst_1716: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xbc00; +op3val:0x7bff; valaddr_reg:x2; val_offset:5046*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5046*FLEN/8, x3, x1, x4) + +inst_1717: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xbc00; +op3val:0xfbff; valaddr_reg:x2; val_offset:5049*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5049*FLEN/8, x3, x1, x4) + +inst_1718: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xbc00; +op3val:0x7c00; valaddr_reg:x2; val_offset:5052*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5052*FLEN/8, x3, x1, x4) + +inst_1719: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xbc00; +op3val:0xfc00; valaddr_reg:x2; val_offset:5055*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5055*FLEN/8, x3, x1, x4) + +inst_1720: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xbc00; +op3val:0x7e00; valaddr_reg:x2; val_offset:5058*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5058*FLEN/8, x3, x1, x4) + +inst_1721: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xbc00; +op3val:0xfe00; valaddr_reg:x2; val_offset:5061*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5061*FLEN/8, x3, x1, x4) + +inst_1722: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xbc00; +op3val:0x7e01; valaddr_reg:x2; val_offset:5064*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5064*FLEN/8, x3, x1, x4) + +inst_1723: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xbc00; +op3val:0xfe55; valaddr_reg:x2; val_offset:5067*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5067*FLEN/8, x3, x1, x4) + +inst_1724: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xbc00; +op3val:0x7c01; valaddr_reg:x2; val_offset:5070*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5070*FLEN/8, x3, x1, x4) + +inst_1725: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xbc00; +op3val:0xfd55; valaddr_reg:x2; val_offset:5073*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5073*FLEN/8, x3, x1, x4) + +inst_1726: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xbc00; +op3val:0x3c00; valaddr_reg:x2; val_offset:5076*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5076*FLEN/8, x3, x1, x4) + +inst_1727: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xbc00; +op3val:0xbc00; valaddr_reg:x2; val_offset:5079*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5079*FLEN/8, x3, x1, x4) + +inst_1728: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x0; +op3val:0x0; valaddr_reg:x2; val_offset:5082*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5082*FLEN/8, x3, x1, x4) + +inst_1729: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x0; +op3val:0x8000; valaddr_reg:x2; val_offset:5085*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5085*FLEN/8, x3, x1, x4) + +inst_1730: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x0; +op3val:0x1; valaddr_reg:x2; val_offset:5088*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5088*FLEN/8, x3, x1, x4) + +inst_1731: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x0; +op3val:0x8001; valaddr_reg:x2; val_offset:5091*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5091*FLEN/8, x3, x1, x4) + +inst_1732: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x0; +op3val:0x2; valaddr_reg:x2; val_offset:5094*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5094*FLEN/8, x3, x1, x4) + +inst_1733: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x0; +op3val:0x83fe; valaddr_reg:x2; val_offset:5097*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5097*FLEN/8, x3, x1, x4) + +inst_1734: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x0; +op3val:0x3ff; valaddr_reg:x2; val_offset:5100*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5100*FLEN/8, x3, x1, x4) + +inst_1735: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x0; +op3val:0x83ff; valaddr_reg:x2; val_offset:5103*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5103*FLEN/8, x3, x1, x4) + +inst_1736: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x0; +op3val:0x400; valaddr_reg:x2; val_offset:5106*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5106*FLEN/8, x3, x1, x4) + +inst_1737: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x0; +op3val:0x8400; valaddr_reg:x2; val_offset:5109*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5109*FLEN/8, x3, x1, x4) + +inst_1738: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x0; +op3val:0x401; valaddr_reg:x2; val_offset:5112*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5112*FLEN/8, x3, x1, x4) + +inst_1739: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x0; +op3val:0x8455; valaddr_reg:x2; val_offset:5115*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5115*FLEN/8, x3, x1, x4) + +inst_1740: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x0; +op3val:0x7bff; valaddr_reg:x2; val_offset:5118*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5118*FLEN/8, x3, x1, x4) + +inst_1741: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x0; +op3val:0xfbff; valaddr_reg:x2; val_offset:5121*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5121*FLEN/8, x3, x1, x4) + +inst_1742: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x0; +op3val:0x7c00; valaddr_reg:x2; val_offset:5124*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5124*FLEN/8, x3, x1, x4) + +inst_1743: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x0; +op3val:0xfc00; valaddr_reg:x2; val_offset:5127*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5127*FLEN/8, x3, x1, x4) + +inst_1744: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x0; +op3val:0x7e00; valaddr_reg:x2; val_offset:5130*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5130*FLEN/8, x3, x1, x4) + +inst_1745: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x0; +op3val:0xfe00; valaddr_reg:x2; val_offset:5133*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5133*FLEN/8, x3, x1, x4) + +inst_1746: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x0; +op3val:0x7e01; valaddr_reg:x2; val_offset:5136*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5136*FLEN/8, x3, x1, x4) + +inst_1747: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x0; +op3val:0xfe55; valaddr_reg:x2; val_offset:5139*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5139*FLEN/8, x3, x1, x4) + +inst_1748: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x0; +op3val:0x7c01; valaddr_reg:x2; val_offset:5142*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5142*FLEN/8, x3, x1, x4) + +inst_1749: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x0; +op3val:0xfd55; valaddr_reg:x2; val_offset:5145*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5145*FLEN/8, x3, x1, x4) + +inst_1750: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x0; +op3val:0x3c00; valaddr_reg:x2; val_offset:5148*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5148*FLEN/8, x3, x1, x4) + +inst_1751: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x0; +op3val:0xbc00; valaddr_reg:x2; val_offset:5151*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5151*FLEN/8, x3, x1, x4) + +inst_1752: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8000; +op3val:0x0; valaddr_reg:x2; val_offset:5154*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5154*FLEN/8, x3, x1, x4) + +inst_1753: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8000; +op3val:0x8000; valaddr_reg:x2; val_offset:5157*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5157*FLEN/8, x3, x1, x4) + +inst_1754: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8000; +op3val:0x1; valaddr_reg:x2; val_offset:5160*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5160*FLEN/8, x3, x1, x4) + +inst_1755: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8000; +op3val:0x8001; valaddr_reg:x2; val_offset:5163*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5163*FLEN/8, x3, x1, x4) + +inst_1756: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8000; +op3val:0x2; valaddr_reg:x2; val_offset:5166*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5166*FLEN/8, x3, x1, x4) + +inst_1757: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8000; +op3val:0x83fe; valaddr_reg:x2; val_offset:5169*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5169*FLEN/8, x3, x1, x4) + +inst_1758: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8000; +op3val:0x3ff; valaddr_reg:x2; val_offset:5172*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5172*FLEN/8, x3, x1, x4) + +inst_1759: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8000; +op3val:0x83ff; valaddr_reg:x2; val_offset:5175*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5175*FLEN/8, x3, x1, x4) + +inst_1760: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8000; +op3val:0x400; valaddr_reg:x2; val_offset:5178*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5178*FLEN/8, x3, x1, x4) + +inst_1761: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8000; +op3val:0x8400; valaddr_reg:x2; val_offset:5181*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5181*FLEN/8, x3, x1, x4) + +inst_1762: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8000; +op3val:0x401; valaddr_reg:x2; val_offset:5184*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5184*FLEN/8, x3, x1, x4) + +inst_1763: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8000; +op3val:0x8455; valaddr_reg:x2; val_offset:5187*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5187*FLEN/8, x3, x1, x4) + +inst_1764: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x2; val_offset:5190*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5190*FLEN/8, x3, x1, x4) + +inst_1765: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x2; val_offset:5193*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5193*FLEN/8, x3, x1, x4) + +inst_1766: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8000; +op3val:0x7c00; valaddr_reg:x2; val_offset:5196*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5196*FLEN/8, x3, x1, x4) + +inst_1767: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8000; +op3val:0xfc00; valaddr_reg:x2; val_offset:5199*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5199*FLEN/8, x3, x1, x4) + +inst_1768: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8000; +op3val:0x7e00; valaddr_reg:x2; val_offset:5202*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5202*FLEN/8, x3, x1, x4) + +inst_1769: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8000; +op3val:0xfe00; valaddr_reg:x2; val_offset:5205*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5205*FLEN/8, x3, x1, x4) + +inst_1770: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8000; +op3val:0x7e01; valaddr_reg:x2; val_offset:5208*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5208*FLEN/8, x3, x1, x4) + +inst_1771: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8000; +op3val:0xfe55; valaddr_reg:x2; val_offset:5211*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5211*FLEN/8, x3, x1, x4) + +inst_1772: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8000; +op3val:0x7c01; valaddr_reg:x2; val_offset:5214*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5214*FLEN/8, x3, x1, x4) + +inst_1773: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8000; +op3val:0xfd55; valaddr_reg:x2; val_offset:5217*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5217*FLEN/8, x3, x1, x4) + +inst_1774: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8000; +op3val:0x3c00; valaddr_reg:x2; val_offset:5220*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5220*FLEN/8, x3, x1, x4) + +inst_1775: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8000; +op3val:0xbc00; valaddr_reg:x2; val_offset:5223*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5223*FLEN/8, x3, x1, x4) + +inst_1776: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x1; +op3val:0x0; valaddr_reg:x2; val_offset:5226*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5226*FLEN/8, x3, x1, x4) + +inst_1777: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x1; +op3val:0x8000; valaddr_reg:x2; val_offset:5229*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5229*FLEN/8, x3, x1, x4) + +inst_1778: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x1; +op3val:0x1; valaddr_reg:x2; val_offset:5232*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5232*FLEN/8, x3, x1, x4) + +inst_1779: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x1; +op3val:0x8001; valaddr_reg:x2; val_offset:5235*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5235*FLEN/8, x3, x1, x4) + +inst_1780: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x1; +op3val:0x2; valaddr_reg:x2; val_offset:5238*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5238*FLEN/8, x3, x1, x4) + +inst_1781: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x1; +op3val:0x83fe; valaddr_reg:x2; val_offset:5241*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5241*FLEN/8, x3, x1, x4) + +inst_1782: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x1; +op3val:0x3ff; valaddr_reg:x2; val_offset:5244*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5244*FLEN/8, x3, x1, x4) + +inst_1783: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x1; +op3val:0x83ff; valaddr_reg:x2; val_offset:5247*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5247*FLEN/8, x3, x1, x4) + +inst_1784: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x1; +op3val:0x400; valaddr_reg:x2; val_offset:5250*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5250*FLEN/8, x3, x1, x4) + +inst_1785: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x1; +op3val:0x8400; valaddr_reg:x2; val_offset:5253*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5253*FLEN/8, x3, x1, x4) + +inst_1786: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x1; +op3val:0x401; valaddr_reg:x2; val_offset:5256*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5256*FLEN/8, x3, x1, x4) + +inst_1787: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x1; +op3val:0x8455; valaddr_reg:x2; val_offset:5259*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5259*FLEN/8, x3, x1, x4) + +inst_1788: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x1; +op3val:0x7bff; valaddr_reg:x2; val_offset:5262*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5262*FLEN/8, x3, x1, x4) + +inst_1789: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x1; +op3val:0xfbff; valaddr_reg:x2; val_offset:5265*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5265*FLEN/8, x3, x1, x4) + +inst_1790: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x1; +op3val:0x7c00; valaddr_reg:x2; val_offset:5268*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5268*FLEN/8, x3, x1, x4) + +inst_1791: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x1; +op3val:0xfc00; valaddr_reg:x2; val_offset:5271*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5271*FLEN/8, x3, x1, x4) + +inst_1792: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x1; +op3val:0x7e00; valaddr_reg:x2; val_offset:5274*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5274*FLEN/8, x3, x1, x4) + +inst_1793: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x1; +op3val:0xfe00; valaddr_reg:x2; val_offset:5277*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5277*FLEN/8, x3, x1, x4) + +inst_1794: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x1; +op3val:0x7e01; valaddr_reg:x2; val_offset:5280*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5280*FLEN/8, x3, x1, x4) + +inst_1795: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x1; +op3val:0xfe55; valaddr_reg:x2; val_offset:5283*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5283*FLEN/8, x3, x1, x4) + +inst_1796: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x1; +op3val:0x7c01; valaddr_reg:x2; val_offset:5286*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5286*FLEN/8, x3, x1, x4) + +inst_1797: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x1; +op3val:0xfd55; valaddr_reg:x2; val_offset:5289*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5289*FLEN/8, x3, x1, x4) + +inst_1798: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x1; +op3val:0x3c00; valaddr_reg:x2; val_offset:5292*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5292*FLEN/8, x3, x1, x4) + +inst_1799: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x1; +op3val:0xbc00; valaddr_reg:x2; val_offset:5295*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5295*FLEN/8, x3, x1, x4) + +inst_1800: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8001; +op3val:0x0; valaddr_reg:x2; val_offset:5298*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5298*FLEN/8, x3, x1, x4) + +inst_1801: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8001; +op3val:0x8000; valaddr_reg:x2; val_offset:5301*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5301*FLEN/8, x3, x1, x4) + +inst_1802: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8001; +op3val:0x1; valaddr_reg:x2; val_offset:5304*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5304*FLEN/8, x3, x1, x4) + +inst_1803: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8001; +op3val:0x8001; valaddr_reg:x2; val_offset:5307*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5307*FLEN/8, x3, x1, x4) + +inst_1804: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8001; +op3val:0x2; valaddr_reg:x2; val_offset:5310*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5310*FLEN/8, x3, x1, x4) + +inst_1805: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8001; +op3val:0x83fe; valaddr_reg:x2; val_offset:5313*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5313*FLEN/8, x3, x1, x4) + +inst_1806: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8001; +op3val:0x3ff; valaddr_reg:x2; val_offset:5316*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5316*FLEN/8, x3, x1, x4) + +inst_1807: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8001; +op3val:0x83ff; valaddr_reg:x2; val_offset:5319*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5319*FLEN/8, x3, x1, x4) + +inst_1808: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8001; +op3val:0x400; valaddr_reg:x2; val_offset:5322*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5322*FLEN/8, x3, x1, x4) + +inst_1809: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8001; +op3val:0x8400; valaddr_reg:x2; val_offset:5325*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5325*FLEN/8, x3, x1, x4) + +inst_1810: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8001; +op3val:0x401; valaddr_reg:x2; val_offset:5328*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5328*FLEN/8, x3, x1, x4) + +inst_1811: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8001; +op3val:0x8455; valaddr_reg:x2; val_offset:5331*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5331*FLEN/8, x3, x1, x4) + +inst_1812: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8001; +op3val:0x7bff; valaddr_reg:x2; val_offset:5334*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5334*FLEN/8, x3, x1, x4) + +inst_1813: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8001; +op3val:0xfbff; valaddr_reg:x2; val_offset:5337*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5337*FLEN/8, x3, x1, x4) + +inst_1814: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8001; +op3val:0x7c00; valaddr_reg:x2; val_offset:5340*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5340*FLEN/8, x3, x1, x4) + +inst_1815: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8001; +op3val:0xfc00; valaddr_reg:x2; val_offset:5343*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5343*FLEN/8, x3, x1, x4) + +inst_1816: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8001; +op3val:0x7e00; valaddr_reg:x2; val_offset:5346*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5346*FLEN/8, x3, x1, x4) + +inst_1817: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8001; +op3val:0xfe00; valaddr_reg:x2; val_offset:5349*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5349*FLEN/8, x3, x1, x4) + +inst_1818: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8001; +op3val:0x7e01; valaddr_reg:x2; val_offset:5352*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5352*FLEN/8, x3, x1, x4) + +inst_1819: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8001; +op3val:0xfe55; valaddr_reg:x2; val_offset:5355*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5355*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_15) + +inst_1820: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8001; +op3val:0x7c01; valaddr_reg:x2; val_offset:5358*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5358*FLEN/8, x3, x1, x4) + +inst_1821: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8001; +op3val:0xfd55; valaddr_reg:x2; val_offset:5361*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5361*FLEN/8, x3, x1, x4) + +inst_1822: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8001; +op3val:0x3c00; valaddr_reg:x2; val_offset:5364*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5364*FLEN/8, x3, x1, x4) + +inst_1823: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8001; +op3val:0xbc00; valaddr_reg:x2; val_offset:5367*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5367*FLEN/8, x3, x1, x4) + +inst_1824: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x2; +op3val:0x0; valaddr_reg:x2; val_offset:5370*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5370*FLEN/8, x3, x1, x4) + +inst_1825: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x2; +op3val:0x8000; valaddr_reg:x2; val_offset:5373*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5373*FLEN/8, x3, x1, x4) + +inst_1826: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x2; +op3val:0x1; valaddr_reg:x2; val_offset:5376*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5376*FLEN/8, x3, x1, x4) + +inst_1827: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x2; +op3val:0x8001; valaddr_reg:x2; val_offset:5379*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5379*FLEN/8, x3, x1, x4) + +inst_1828: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x2; +op3val:0x2; valaddr_reg:x2; val_offset:5382*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5382*FLEN/8, x3, x1, x4) + +inst_1829: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x2; +op3val:0x83fe; valaddr_reg:x2; val_offset:5385*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5385*FLEN/8, x3, x1, x4) + +inst_1830: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x2; +op3val:0x3ff; valaddr_reg:x2; val_offset:5388*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5388*FLEN/8, x3, x1, x4) + +inst_1831: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x2; +op3val:0x83ff; valaddr_reg:x2; val_offset:5391*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5391*FLEN/8, x3, x1, x4) + +inst_1832: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x2; +op3val:0x400; valaddr_reg:x2; val_offset:5394*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5394*FLEN/8, x3, x1, x4) + +inst_1833: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x2; +op3val:0x8400; valaddr_reg:x2; val_offset:5397*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5397*FLEN/8, x3, x1, x4) + +inst_1834: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x2; +op3val:0x401; valaddr_reg:x2; val_offset:5400*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5400*FLEN/8, x3, x1, x4) + +inst_1835: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x2; +op3val:0x8455; valaddr_reg:x2; val_offset:5403*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5403*FLEN/8, x3, x1, x4) + +inst_1836: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x2; +op3val:0x7bff; valaddr_reg:x2; val_offset:5406*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5406*FLEN/8, x3, x1, x4) + +inst_1837: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x2; +op3val:0xfbff; valaddr_reg:x2; val_offset:5409*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5409*FLEN/8, x3, x1, x4) + +inst_1838: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x2; +op3val:0x7c00; valaddr_reg:x2; val_offset:5412*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5412*FLEN/8, x3, x1, x4) + +inst_1839: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x2; +op3val:0xfc00; valaddr_reg:x2; val_offset:5415*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5415*FLEN/8, x3, x1, x4) + +inst_1840: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x2; +op3val:0x7e00; valaddr_reg:x2; val_offset:5418*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5418*FLEN/8, x3, x1, x4) + +inst_1841: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x2; +op3val:0xfe00; valaddr_reg:x2; val_offset:5421*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5421*FLEN/8, x3, x1, x4) + +inst_1842: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x2; +op3val:0x7e01; valaddr_reg:x2; val_offset:5424*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5424*FLEN/8, x3, x1, x4) + +inst_1843: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x2; +op3val:0xfe55; valaddr_reg:x2; val_offset:5427*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5427*FLEN/8, x3, x1, x4) + +inst_1844: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x2; +op3val:0x7c01; valaddr_reg:x2; val_offset:5430*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5430*FLEN/8, x3, x1, x4) + +inst_1845: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x2; +op3val:0xfd55; valaddr_reg:x2; val_offset:5433*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5433*FLEN/8, x3, x1, x4) + +inst_1846: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x2; +op3val:0x3c00; valaddr_reg:x2; val_offset:5436*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5436*FLEN/8, x3, x1, x4) + +inst_1847: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x2; +op3val:0xbc00; valaddr_reg:x2; val_offset:5439*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5439*FLEN/8, x3, x1, x4) + +inst_1848: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x83fe; +op3val:0x0; valaddr_reg:x2; val_offset:5442*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5442*FLEN/8, x3, x1, x4) + +inst_1849: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x83fe; +op3val:0x8000; valaddr_reg:x2; val_offset:5445*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5445*FLEN/8, x3, x1, x4) + +inst_1850: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x83fe; +op3val:0x1; valaddr_reg:x2; val_offset:5448*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5448*FLEN/8, x3, x1, x4) + +inst_1851: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x83fe; +op3val:0x8001; valaddr_reg:x2; val_offset:5451*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5451*FLEN/8, x3, x1, x4) + +inst_1852: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x83fe; +op3val:0x2; valaddr_reg:x2; val_offset:5454*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5454*FLEN/8, x3, x1, x4) + +inst_1853: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x83fe; +op3val:0x83fe; valaddr_reg:x2; val_offset:5457*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5457*FLEN/8, x3, x1, x4) + +inst_1854: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x83fe; +op3val:0x3ff; valaddr_reg:x2; val_offset:5460*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5460*FLEN/8, x3, x1, x4) + +inst_1855: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x83fe; +op3val:0x83ff; valaddr_reg:x2; val_offset:5463*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5463*FLEN/8, x3, x1, x4) + +inst_1856: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x83fe; +op3val:0x400; valaddr_reg:x2; val_offset:5466*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5466*FLEN/8, x3, x1, x4) + +inst_1857: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x83fe; +op3val:0x8400; valaddr_reg:x2; val_offset:5469*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5469*FLEN/8, x3, x1, x4) + +inst_1858: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x83fe; +op3val:0x401; valaddr_reg:x2; val_offset:5472*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5472*FLEN/8, x3, x1, x4) + +inst_1859: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x83fe; +op3val:0x8455; valaddr_reg:x2; val_offset:5475*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5475*FLEN/8, x3, x1, x4) + +inst_1860: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x83fe; +op3val:0x7bff; valaddr_reg:x2; val_offset:5478*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5478*FLEN/8, x3, x1, x4) + +inst_1861: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x83fe; +op3val:0xfbff; valaddr_reg:x2; val_offset:5481*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5481*FLEN/8, x3, x1, x4) + +inst_1862: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x83fe; +op3val:0x7c00; valaddr_reg:x2; val_offset:5484*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5484*FLEN/8, x3, x1, x4) + +inst_1863: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x83fe; +op3val:0xfc00; valaddr_reg:x2; val_offset:5487*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5487*FLEN/8, x3, x1, x4) + +inst_1864: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x83fe; +op3val:0x7e00; valaddr_reg:x2; val_offset:5490*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5490*FLEN/8, x3, x1, x4) + +inst_1865: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x83fe; +op3val:0xfe00; valaddr_reg:x2; val_offset:5493*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5493*FLEN/8, x3, x1, x4) + +inst_1866: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x83fe; +op3val:0x7e01; valaddr_reg:x2; val_offset:5496*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5496*FLEN/8, x3, x1, x4) + +inst_1867: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x83fe; +op3val:0xfe55; valaddr_reg:x2; val_offset:5499*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5499*FLEN/8, x3, x1, x4) + +inst_1868: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x83fe; +op3val:0x7c01; valaddr_reg:x2; val_offset:5502*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5502*FLEN/8, x3, x1, x4) + +inst_1869: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x83fe; +op3val:0xfd55; valaddr_reg:x2; val_offset:5505*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5505*FLEN/8, x3, x1, x4) + +inst_1870: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x83fe; +op3val:0x3c00; valaddr_reg:x2; val_offset:5508*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5508*FLEN/8, x3, x1, x4) + +inst_1871: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x83fe; +op3val:0xbc00; valaddr_reg:x2; val_offset:5511*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5511*FLEN/8, x3, x1, x4) + +inst_1872: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x3ff; +op3val:0x0; valaddr_reg:x2; val_offset:5514*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5514*FLEN/8, x3, x1, x4) + +inst_1873: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x3ff; +op3val:0x8000; valaddr_reg:x2; val_offset:5517*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5517*FLEN/8, x3, x1, x4) + +inst_1874: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x3ff; +op3val:0x1; valaddr_reg:x2; val_offset:5520*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5520*FLEN/8, x3, x1, x4) + +inst_1875: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x3ff; +op3val:0x8001; valaddr_reg:x2; val_offset:5523*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5523*FLEN/8, x3, x1, x4) + +inst_1876: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x3ff; +op3val:0x2; valaddr_reg:x2; val_offset:5526*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5526*FLEN/8, x3, x1, x4) + +inst_1877: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x3ff; +op3val:0x83fe; valaddr_reg:x2; val_offset:5529*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5529*FLEN/8, x3, x1, x4) + +inst_1878: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x3ff; +op3val:0x3ff; valaddr_reg:x2; val_offset:5532*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5532*FLEN/8, x3, x1, x4) + +inst_1879: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x3ff; +op3val:0x83ff; valaddr_reg:x2; val_offset:5535*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5535*FLEN/8, x3, x1, x4) + +inst_1880: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x3ff; +op3val:0x400; valaddr_reg:x2; val_offset:5538*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5538*FLEN/8, x3, x1, x4) + +inst_1881: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x3ff; +op3val:0x8400; valaddr_reg:x2; val_offset:5541*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5541*FLEN/8, x3, x1, x4) + +inst_1882: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x3ff; +op3val:0x401; valaddr_reg:x2; val_offset:5544*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5544*FLEN/8, x3, x1, x4) + +inst_1883: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x3ff; +op3val:0x8455; valaddr_reg:x2; val_offset:5547*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5547*FLEN/8, x3, x1, x4) + +inst_1884: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x3ff; +op3val:0x7bff; valaddr_reg:x2; val_offset:5550*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5550*FLEN/8, x3, x1, x4) + +inst_1885: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x3ff; +op3val:0xfbff; valaddr_reg:x2; val_offset:5553*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5553*FLEN/8, x3, x1, x4) + +inst_1886: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x3ff; +op3val:0x7c00; valaddr_reg:x2; val_offset:5556*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5556*FLEN/8, x3, x1, x4) + +inst_1887: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x3ff; +op3val:0xfc00; valaddr_reg:x2; val_offset:5559*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5559*FLEN/8, x3, x1, x4) + +inst_1888: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x3ff; +op3val:0x7e00; valaddr_reg:x2; val_offset:5562*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5562*FLEN/8, x3, x1, x4) + +inst_1889: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x3ff; +op3val:0xfe00; valaddr_reg:x2; val_offset:5565*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5565*FLEN/8, x3, x1, x4) + +inst_1890: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x3ff; +op3val:0x7e01; valaddr_reg:x2; val_offset:5568*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5568*FLEN/8, x3, x1, x4) + +inst_1891: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x3ff; +op3val:0xfe55; valaddr_reg:x2; val_offset:5571*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5571*FLEN/8, x3, x1, x4) + +inst_1892: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x3ff; +op3val:0x7c01; valaddr_reg:x2; val_offset:5574*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5574*FLEN/8, x3, x1, x4) + +inst_1893: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x3ff; +op3val:0xfd55; valaddr_reg:x2; val_offset:5577*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5577*FLEN/8, x3, x1, x4) + +inst_1894: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x3ff; +op3val:0x3c00; valaddr_reg:x2; val_offset:5580*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5580*FLEN/8, x3, x1, x4) + +inst_1895: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x3ff; +op3val:0xbc00; valaddr_reg:x2; val_offset:5583*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5583*FLEN/8, x3, x1, x4) + +inst_1896: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x83ff; +op3val:0x0; valaddr_reg:x2; val_offset:5586*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5586*FLEN/8, x3, x1, x4) + +inst_1897: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x83ff; +op3val:0x8000; valaddr_reg:x2; val_offset:5589*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5589*FLEN/8, x3, x1, x4) + +inst_1898: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x83ff; +op3val:0x1; valaddr_reg:x2; val_offset:5592*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5592*FLEN/8, x3, x1, x4) + +inst_1899: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x83ff; +op3val:0x8001; valaddr_reg:x2; val_offset:5595*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5595*FLEN/8, x3, x1, x4) + +inst_1900: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x83ff; +op3val:0x2; valaddr_reg:x2; val_offset:5598*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5598*FLEN/8, x3, x1, x4) + +inst_1901: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x83ff; +op3val:0x83fe; valaddr_reg:x2; val_offset:5601*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5601*FLEN/8, x3, x1, x4) + +inst_1902: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x83ff; +op3val:0x3ff; valaddr_reg:x2; val_offset:5604*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5604*FLEN/8, x3, x1, x4) + +inst_1903: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x83ff; +op3val:0x83ff; valaddr_reg:x2; val_offset:5607*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5607*FLEN/8, x3, x1, x4) + +inst_1904: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x83ff; +op3val:0x400; valaddr_reg:x2; val_offset:5610*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5610*FLEN/8, x3, x1, x4) + +inst_1905: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x83ff; +op3val:0x8400; valaddr_reg:x2; val_offset:5613*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5613*FLEN/8, x3, x1, x4) + +inst_1906: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x83ff; +op3val:0x401; valaddr_reg:x2; val_offset:5616*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5616*FLEN/8, x3, x1, x4) + +inst_1907: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x83ff; +op3val:0x8455; valaddr_reg:x2; val_offset:5619*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5619*FLEN/8, x3, x1, x4) + +inst_1908: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x83ff; +op3val:0x7bff; valaddr_reg:x2; val_offset:5622*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5622*FLEN/8, x3, x1, x4) + +inst_1909: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x83ff; +op3val:0xfbff; valaddr_reg:x2; val_offset:5625*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5625*FLEN/8, x3, x1, x4) + +inst_1910: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x83ff; +op3val:0x7c00; valaddr_reg:x2; val_offset:5628*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5628*FLEN/8, x3, x1, x4) + +inst_1911: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x83ff; +op3val:0xfc00; valaddr_reg:x2; val_offset:5631*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5631*FLEN/8, x3, x1, x4) + +inst_1912: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x83ff; +op3val:0x7e00; valaddr_reg:x2; val_offset:5634*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5634*FLEN/8, x3, x1, x4) + +inst_1913: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x83ff; +op3val:0xfe00; valaddr_reg:x2; val_offset:5637*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5637*FLEN/8, x3, x1, x4) + +inst_1914: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x83ff; +op3val:0x7e01; valaddr_reg:x2; val_offset:5640*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5640*FLEN/8, x3, x1, x4) + +inst_1915: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x83ff; +op3val:0xfe55; valaddr_reg:x2; val_offset:5643*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5643*FLEN/8, x3, x1, x4) + +inst_1916: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x83ff; +op3val:0x7c01; valaddr_reg:x2; val_offset:5646*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5646*FLEN/8, x3, x1, x4) + +inst_1917: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x83ff; +op3val:0xfd55; valaddr_reg:x2; val_offset:5649*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5649*FLEN/8, x3, x1, x4) + +inst_1918: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x83ff; +op3val:0x3c00; valaddr_reg:x2; val_offset:5652*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5652*FLEN/8, x3, x1, x4) + +inst_1919: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x83ff; +op3val:0xbc00; valaddr_reg:x2; val_offset:5655*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5655*FLEN/8, x3, x1, x4) + +inst_1920: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x400; +op3val:0x0; valaddr_reg:x2; val_offset:5658*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5658*FLEN/8, x3, x1, x4) + +inst_1921: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x400; +op3val:0x8000; valaddr_reg:x2; val_offset:5661*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5661*FLEN/8, x3, x1, x4) + +inst_1922: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x400; +op3val:0x1; valaddr_reg:x2; val_offset:5664*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5664*FLEN/8, x3, x1, x4) + +inst_1923: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x400; +op3val:0x8001; valaddr_reg:x2; val_offset:5667*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5667*FLEN/8, x3, x1, x4) + +inst_1924: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x400; +op3val:0x2; valaddr_reg:x2; val_offset:5670*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5670*FLEN/8, x3, x1, x4) + +inst_1925: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x400; +op3val:0x83fe; valaddr_reg:x2; val_offset:5673*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5673*FLEN/8, x3, x1, x4) + +inst_1926: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x400; +op3val:0x3ff; valaddr_reg:x2; val_offset:5676*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5676*FLEN/8, x3, x1, x4) + +inst_1927: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x400; +op3val:0x83ff; valaddr_reg:x2; val_offset:5679*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5679*FLEN/8, x3, x1, x4) + +inst_1928: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x400; +op3val:0x400; valaddr_reg:x2; val_offset:5682*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5682*FLEN/8, x3, x1, x4) + +inst_1929: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x400; +op3val:0x8400; valaddr_reg:x2; val_offset:5685*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5685*FLEN/8, x3, x1, x4) + +inst_1930: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x400; +op3val:0x401; valaddr_reg:x2; val_offset:5688*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5688*FLEN/8, x3, x1, x4) + +inst_1931: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x400; +op3val:0x8455; valaddr_reg:x2; val_offset:5691*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5691*FLEN/8, x3, x1, x4) + +inst_1932: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x400; +op3val:0x7bff; valaddr_reg:x2; val_offset:5694*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5694*FLEN/8, x3, x1, x4) + +inst_1933: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x400; +op3val:0xfbff; valaddr_reg:x2; val_offset:5697*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5697*FLEN/8, x3, x1, x4) + +inst_1934: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x400; +op3val:0x7c00; valaddr_reg:x2; val_offset:5700*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5700*FLEN/8, x3, x1, x4) + +inst_1935: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x400; +op3val:0xfc00; valaddr_reg:x2; val_offset:5703*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5703*FLEN/8, x3, x1, x4) + +inst_1936: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x400; +op3val:0x7e00; valaddr_reg:x2; val_offset:5706*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5706*FLEN/8, x3, x1, x4) + +inst_1937: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x400; +op3val:0xfe00; valaddr_reg:x2; val_offset:5709*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5709*FLEN/8, x3, x1, x4) + +inst_1938: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x400; +op3val:0x7e01; valaddr_reg:x2; val_offset:5712*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5712*FLEN/8, x3, x1, x4) + +inst_1939: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x400; +op3val:0xfe55; valaddr_reg:x2; val_offset:5715*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5715*FLEN/8, x3, x1, x4) + +inst_1940: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x400; +op3val:0x7c01; valaddr_reg:x2; val_offset:5718*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5718*FLEN/8, x3, x1, x4) + +inst_1941: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x400; +op3val:0xfd55; valaddr_reg:x2; val_offset:5721*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5721*FLEN/8, x3, x1, x4) + +inst_1942: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x400; +op3val:0x3c00; valaddr_reg:x2; val_offset:5724*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5724*FLEN/8, x3, x1, x4) + +inst_1943: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x400; +op3val:0xbc00; valaddr_reg:x2; val_offset:5727*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5727*FLEN/8, x3, x1, x4) + +inst_1944: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8400; +op3val:0x0; valaddr_reg:x2; val_offset:5730*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5730*FLEN/8, x3, x1, x4) + +inst_1945: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8400; +op3val:0x8000; valaddr_reg:x2; val_offset:5733*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5733*FLEN/8, x3, x1, x4) + +inst_1946: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8400; +op3val:0x1; valaddr_reg:x2; val_offset:5736*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5736*FLEN/8, x3, x1, x4) + +inst_1947: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8400; +op3val:0x8001; valaddr_reg:x2; val_offset:5739*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5739*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_16) + +inst_1948: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8400; +op3val:0x2; valaddr_reg:x2; val_offset:5742*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5742*FLEN/8, x3, x1, x4) + +inst_1949: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8400; +op3val:0x83fe; valaddr_reg:x2; val_offset:5745*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5745*FLEN/8, x3, x1, x4) + +inst_1950: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8400; +op3val:0x3ff; valaddr_reg:x2; val_offset:5748*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5748*FLEN/8, x3, x1, x4) + +inst_1951: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8400; +op3val:0x83ff; valaddr_reg:x2; val_offset:5751*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5751*FLEN/8, x3, x1, x4) + +inst_1952: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8400; +op3val:0x400; valaddr_reg:x2; val_offset:5754*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5754*FLEN/8, x3, x1, x4) + +inst_1953: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8400; +op3val:0x8400; valaddr_reg:x2; val_offset:5757*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5757*FLEN/8, x3, x1, x4) + +inst_1954: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8400; +op3val:0x401; valaddr_reg:x2; val_offset:5760*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5760*FLEN/8, x3, x1, x4) + +inst_1955: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8400; +op3val:0x8455; valaddr_reg:x2; val_offset:5763*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5763*FLEN/8, x3, x1, x4) + +inst_1956: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8400; +op3val:0x7bff; valaddr_reg:x2; val_offset:5766*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5766*FLEN/8, x3, x1, x4) + +inst_1957: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8400; +op3val:0xfbff; valaddr_reg:x2; val_offset:5769*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5769*FLEN/8, x3, x1, x4) + +inst_1958: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8400; +op3val:0x7c00; valaddr_reg:x2; val_offset:5772*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5772*FLEN/8, x3, x1, x4) + +inst_1959: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8400; +op3val:0xfc00; valaddr_reg:x2; val_offset:5775*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5775*FLEN/8, x3, x1, x4) + +inst_1960: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8400; +op3val:0x7e00; valaddr_reg:x2; val_offset:5778*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5778*FLEN/8, x3, x1, x4) + +inst_1961: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8400; +op3val:0xfe00; valaddr_reg:x2; val_offset:5781*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5781*FLEN/8, x3, x1, x4) + +inst_1962: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8400; +op3val:0x7e01; valaddr_reg:x2; val_offset:5784*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5784*FLEN/8, x3, x1, x4) + +inst_1963: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8400; +op3val:0xfe55; valaddr_reg:x2; val_offset:5787*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5787*FLEN/8, x3, x1, x4) + +inst_1964: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8400; +op3val:0x7c01; valaddr_reg:x2; val_offset:5790*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5790*FLEN/8, x3, x1, x4) + +inst_1965: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8400; +op3val:0xfd55; valaddr_reg:x2; val_offset:5793*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5793*FLEN/8, x3, x1, x4) + +inst_1966: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8400; +op3val:0x3c00; valaddr_reg:x2; val_offset:5796*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5796*FLEN/8, x3, x1, x4) + +inst_1967: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8400; +op3val:0xbc00; valaddr_reg:x2; val_offset:5799*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5799*FLEN/8, x3, x1, x4) + +inst_1968: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x401; +op3val:0x0; valaddr_reg:x2; val_offset:5802*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5802*FLEN/8, x3, x1, x4) + +inst_1969: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x401; +op3val:0x8000; valaddr_reg:x2; val_offset:5805*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5805*FLEN/8, x3, x1, x4) + +inst_1970: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x401; +op3val:0x1; valaddr_reg:x2; val_offset:5808*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5808*FLEN/8, x3, x1, x4) + +inst_1971: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x401; +op3val:0x8001; valaddr_reg:x2; val_offset:5811*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5811*FLEN/8, x3, x1, x4) + +inst_1972: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x401; +op3val:0x2; valaddr_reg:x2; val_offset:5814*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5814*FLEN/8, x3, x1, x4) + +inst_1973: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x401; +op3val:0x83fe; valaddr_reg:x2; val_offset:5817*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5817*FLEN/8, x3, x1, x4) + +inst_1974: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x401; +op3val:0x3ff; valaddr_reg:x2; val_offset:5820*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5820*FLEN/8, x3, x1, x4) + +inst_1975: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x401; +op3val:0x83ff; valaddr_reg:x2; val_offset:5823*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5823*FLEN/8, x3, x1, x4) + +inst_1976: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x401; +op3val:0x400; valaddr_reg:x2; val_offset:5826*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5826*FLEN/8, x3, x1, x4) + +inst_1977: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x401; +op3val:0x8400; valaddr_reg:x2; val_offset:5829*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5829*FLEN/8, x3, x1, x4) + +inst_1978: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x401; +op3val:0x401; valaddr_reg:x2; val_offset:5832*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5832*FLEN/8, x3, x1, x4) + +inst_1979: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x401; +op3val:0x8455; valaddr_reg:x2; val_offset:5835*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5835*FLEN/8, x3, x1, x4) + +inst_1980: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x401; +op3val:0x7bff; valaddr_reg:x2; val_offset:5838*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5838*FLEN/8, x3, x1, x4) + +inst_1981: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x401; +op3val:0xfbff; valaddr_reg:x2; val_offset:5841*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5841*FLEN/8, x3, x1, x4) + +inst_1982: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x401; +op3val:0x7c00; valaddr_reg:x2; val_offset:5844*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5844*FLEN/8, x3, x1, x4) + +inst_1983: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x401; +op3val:0xfc00; valaddr_reg:x2; val_offset:5847*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5847*FLEN/8, x3, x1, x4) + +inst_1984: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x401; +op3val:0x7e00; valaddr_reg:x2; val_offset:5850*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5850*FLEN/8, x3, x1, x4) + +inst_1985: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x401; +op3val:0xfe00; valaddr_reg:x2; val_offset:5853*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5853*FLEN/8, x3, x1, x4) + +inst_1986: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x401; +op3val:0x7e01; valaddr_reg:x2; val_offset:5856*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5856*FLEN/8, x3, x1, x4) + +inst_1987: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x401; +op3val:0xfe55; valaddr_reg:x2; val_offset:5859*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5859*FLEN/8, x3, x1, x4) + +inst_1988: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x401; +op3val:0x7c01; valaddr_reg:x2; val_offset:5862*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5862*FLEN/8, x3, x1, x4) + +inst_1989: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x401; +op3val:0xfd55; valaddr_reg:x2; val_offset:5865*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5865*FLEN/8, x3, x1, x4) + +inst_1990: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x401; +op3val:0x3c00; valaddr_reg:x2; val_offset:5868*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5868*FLEN/8, x3, x1, x4) + +inst_1991: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x401; +op3val:0xbc00; valaddr_reg:x2; val_offset:5871*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5871*FLEN/8, x3, x1, x4) + +inst_1992: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8455; +op3val:0x0; valaddr_reg:x2; val_offset:5874*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5874*FLEN/8, x3, x1, x4) + +inst_1993: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8455; +op3val:0x8000; valaddr_reg:x2; val_offset:5877*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5877*FLEN/8, x3, x1, x4) + +inst_1994: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8455; +op3val:0x1; valaddr_reg:x2; val_offset:5880*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5880*FLEN/8, x3, x1, x4) + +inst_1995: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8455; +op3val:0x8001; valaddr_reg:x2; val_offset:5883*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5883*FLEN/8, x3, x1, x4) + +inst_1996: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8455; +op3val:0x2; valaddr_reg:x2; val_offset:5886*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5886*FLEN/8, x3, x1, x4) + +inst_1997: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8455; +op3val:0x83fe; valaddr_reg:x2; val_offset:5889*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5889*FLEN/8, x3, x1, x4) + +inst_1998: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8455; +op3val:0x3ff; valaddr_reg:x2; val_offset:5892*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5892*FLEN/8, x3, x1, x4) + +inst_1999: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8455; +op3val:0x83ff; valaddr_reg:x2; val_offset:5895*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5895*FLEN/8, x3, x1, x4) + +inst_2000: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8455; +op3val:0x400; valaddr_reg:x2; val_offset:5898*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5898*FLEN/8, x3, x1, x4) + +inst_2001: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8455; +op3val:0x8400; valaddr_reg:x2; val_offset:5901*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5901*FLEN/8, x3, x1, x4) + +inst_2002: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8455; +op3val:0x401; valaddr_reg:x2; val_offset:5904*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5904*FLEN/8, x3, x1, x4) + +inst_2003: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8455; +op3val:0x8455; valaddr_reg:x2; val_offset:5907*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5907*FLEN/8, x3, x1, x4) + +inst_2004: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8455; +op3val:0x7bff; valaddr_reg:x2; val_offset:5910*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5910*FLEN/8, x3, x1, x4) + +inst_2005: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8455; +op3val:0xfbff; valaddr_reg:x2; val_offset:5913*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5913*FLEN/8, x3, x1, x4) + +inst_2006: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8455; +op3val:0x7c00; valaddr_reg:x2; val_offset:5916*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5916*FLEN/8, x3, x1, x4) + +inst_2007: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8455; +op3val:0xfc00; valaddr_reg:x2; val_offset:5919*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5919*FLEN/8, x3, x1, x4) + +inst_2008: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8455; +op3val:0x7e00; valaddr_reg:x2; val_offset:5922*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5922*FLEN/8, x3, x1, x4) + +inst_2009: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8455; +op3val:0xfe00; valaddr_reg:x2; val_offset:5925*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5925*FLEN/8, x3, x1, x4) + +inst_2010: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8455; +op3val:0x7e01; valaddr_reg:x2; val_offset:5928*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5928*FLEN/8, x3, x1, x4) + +inst_2011: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8455; +op3val:0xfe55; valaddr_reg:x2; val_offset:5931*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5931*FLEN/8, x3, x1, x4) + +inst_2012: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8455; +op3val:0x7c01; valaddr_reg:x2; val_offset:5934*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5934*FLEN/8, x3, x1, x4) + +inst_2013: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8455; +op3val:0xfd55; valaddr_reg:x2; val_offset:5937*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5937*FLEN/8, x3, x1, x4) + +inst_2014: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8455; +op3val:0x3c00; valaddr_reg:x2; val_offset:5940*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5940*FLEN/8, x3, x1, x4) + +inst_2015: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x8455; +op3val:0xbc00; valaddr_reg:x2; val_offset:5943*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5943*FLEN/8, x3, x1, x4) + +inst_2016: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7bff; +op3val:0x0; valaddr_reg:x2; val_offset:5946*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5946*FLEN/8, x3, x1, x4) + +inst_2017: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7bff; +op3val:0x8000; valaddr_reg:x2; val_offset:5949*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5949*FLEN/8, x3, x1, x4) + +inst_2018: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7bff; +op3val:0x1; valaddr_reg:x2; val_offset:5952*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5952*FLEN/8, x3, x1, x4) + +inst_2019: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7bff; +op3val:0x8001; valaddr_reg:x2; val_offset:5955*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5955*FLEN/8, x3, x1, x4) + +inst_2020: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7bff; +op3val:0x2; valaddr_reg:x2; val_offset:5958*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5958*FLEN/8, x3, x1, x4) + +inst_2021: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7bff; +op3val:0x83fe; valaddr_reg:x2; val_offset:5961*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5961*FLEN/8, x3, x1, x4) + +inst_2022: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7bff; +op3val:0x3ff; valaddr_reg:x2; val_offset:5964*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5964*FLEN/8, x3, x1, x4) + +inst_2023: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7bff; +op3val:0x83ff; valaddr_reg:x2; val_offset:5967*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5967*FLEN/8, x3, x1, x4) + +inst_2024: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7bff; +op3val:0x400; valaddr_reg:x2; val_offset:5970*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5970*FLEN/8, x3, x1, x4) + +inst_2025: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7bff; +op3val:0x8400; valaddr_reg:x2; val_offset:5973*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5973*FLEN/8, x3, x1, x4) + +inst_2026: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7bff; +op3val:0x401; valaddr_reg:x2; val_offset:5976*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5976*FLEN/8, x3, x1, x4) + +inst_2027: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7bff; +op3val:0x8455; valaddr_reg:x2; val_offset:5979*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5979*FLEN/8, x3, x1, x4) + +inst_2028: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7bff; +op3val:0x7bff; valaddr_reg:x2; val_offset:5982*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5982*FLEN/8, x3, x1, x4) + +inst_2029: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7bff; +op3val:0xfbff; valaddr_reg:x2; val_offset:5985*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5985*FLEN/8, x3, x1, x4) + +inst_2030: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7bff; +op3val:0x7c00; valaddr_reg:x2; val_offset:5988*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5988*FLEN/8, x3, x1, x4) + +inst_2031: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7bff; +op3val:0xfc00; valaddr_reg:x2; val_offset:5991*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5991*FLEN/8, x3, x1, x4) + +inst_2032: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7bff; +op3val:0x7e00; valaddr_reg:x2; val_offset:5994*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5994*FLEN/8, x3, x1, x4) + +inst_2033: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7bff; +op3val:0xfe00; valaddr_reg:x2; val_offset:5997*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 5997*FLEN/8, x3, x1, x4) + +inst_2034: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7bff; +op3val:0x7e01; valaddr_reg:x2; val_offset:6000*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6000*FLEN/8, x3, x1, x4) + +inst_2035: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7bff; +op3val:0xfe55; valaddr_reg:x2; val_offset:6003*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6003*FLEN/8, x3, x1, x4) + +inst_2036: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7bff; +op3val:0x7c01; valaddr_reg:x2; val_offset:6006*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6006*FLEN/8, x3, x1, x4) + +inst_2037: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7bff; +op3val:0xfd55; valaddr_reg:x2; val_offset:6009*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6009*FLEN/8, x3, x1, x4) + +inst_2038: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7bff; +op3val:0x3c00; valaddr_reg:x2; val_offset:6012*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6012*FLEN/8, x3, x1, x4) + +inst_2039: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7bff; +op3val:0xbc00; valaddr_reg:x2; val_offset:6015*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6015*FLEN/8, x3, x1, x4) + +inst_2040: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfbff; +op3val:0x0; valaddr_reg:x2; val_offset:6018*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6018*FLEN/8, x3, x1, x4) + +inst_2041: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfbff; +op3val:0x8000; valaddr_reg:x2; val_offset:6021*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6021*FLEN/8, x3, x1, x4) + +inst_2042: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfbff; +op3val:0x1; valaddr_reg:x2; val_offset:6024*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6024*FLEN/8, x3, x1, x4) + +inst_2043: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfbff; +op3val:0x8001; valaddr_reg:x2; val_offset:6027*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6027*FLEN/8, x3, x1, x4) + +inst_2044: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfbff; +op3val:0x2; valaddr_reg:x2; val_offset:6030*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6030*FLEN/8, x3, x1, x4) + +inst_2045: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfbff; +op3val:0x83fe; valaddr_reg:x2; val_offset:6033*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6033*FLEN/8, x3, x1, x4) + +inst_2046: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfbff; +op3val:0x3ff; valaddr_reg:x2; val_offset:6036*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6036*FLEN/8, x3, x1, x4) + +inst_2047: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfbff; +op3val:0x83ff; valaddr_reg:x2; val_offset:6039*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6039*FLEN/8, x3, x1, x4) + +inst_2048: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfbff; +op3val:0x400; valaddr_reg:x2; val_offset:6042*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6042*FLEN/8, x3, x1, x4) + +inst_2049: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfbff; +op3val:0x8400; valaddr_reg:x2; val_offset:6045*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6045*FLEN/8, x3, x1, x4) + +inst_2050: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfbff; +op3val:0x401; valaddr_reg:x2; val_offset:6048*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6048*FLEN/8, x3, x1, x4) + +inst_2051: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfbff; +op3val:0x8455; valaddr_reg:x2; val_offset:6051*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6051*FLEN/8, x3, x1, x4) + +inst_2052: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfbff; +op3val:0x7bff; valaddr_reg:x2; val_offset:6054*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6054*FLEN/8, x3, x1, x4) + +inst_2053: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfbff; +op3val:0xfbff; valaddr_reg:x2; val_offset:6057*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6057*FLEN/8, x3, x1, x4) + +inst_2054: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfbff; +op3val:0x7c00; valaddr_reg:x2; val_offset:6060*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6060*FLEN/8, x3, x1, x4) + +inst_2055: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfbff; +op3val:0xfc00; valaddr_reg:x2; val_offset:6063*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6063*FLEN/8, x3, x1, x4) + +inst_2056: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfbff; +op3val:0x7e00; valaddr_reg:x2; val_offset:6066*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6066*FLEN/8, x3, x1, x4) + +inst_2057: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfbff; +op3val:0xfe00; valaddr_reg:x2; val_offset:6069*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6069*FLEN/8, x3, x1, x4) + +inst_2058: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfbff; +op3val:0x7e01; valaddr_reg:x2; val_offset:6072*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6072*FLEN/8, x3, x1, x4) + +inst_2059: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfbff; +op3val:0xfe55; valaddr_reg:x2; val_offset:6075*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6075*FLEN/8, x3, x1, x4) + +inst_2060: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfbff; +op3val:0x7c01; valaddr_reg:x2; val_offset:6078*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6078*FLEN/8, x3, x1, x4) + +inst_2061: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfbff; +op3val:0xfd55; valaddr_reg:x2; val_offset:6081*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6081*FLEN/8, x3, x1, x4) + +inst_2062: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfbff; +op3val:0x3c00; valaddr_reg:x2; val_offset:6084*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6084*FLEN/8, x3, x1, x4) + +inst_2063: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfbff; +op3val:0xbc00; valaddr_reg:x2; val_offset:6087*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6087*FLEN/8, x3, x1, x4) + +inst_2064: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7c00; +op3val:0x0; valaddr_reg:x2; val_offset:6090*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6090*FLEN/8, x3, x1, x4) + +inst_2065: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7c00; +op3val:0x8000; valaddr_reg:x2; val_offset:6093*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6093*FLEN/8, x3, x1, x4) + +inst_2066: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7c00; +op3val:0x1; valaddr_reg:x2; val_offset:6096*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6096*FLEN/8, x3, x1, x4) + +inst_2067: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7c00; +op3val:0x8001; valaddr_reg:x2; val_offset:6099*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6099*FLEN/8, x3, x1, x4) + +inst_2068: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7c00; +op3val:0x2; valaddr_reg:x2; val_offset:6102*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6102*FLEN/8, x3, x1, x4) + +inst_2069: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7c00; +op3val:0x83fe; valaddr_reg:x2; val_offset:6105*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6105*FLEN/8, x3, x1, x4) + +inst_2070: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7c00; +op3val:0x3ff; valaddr_reg:x2; val_offset:6108*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6108*FLEN/8, x3, x1, x4) + +inst_2071: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7c00; +op3val:0x83ff; valaddr_reg:x2; val_offset:6111*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6111*FLEN/8, x3, x1, x4) + +inst_2072: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7c00; +op3val:0x400; valaddr_reg:x2; val_offset:6114*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6114*FLEN/8, x3, x1, x4) + +inst_2073: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7c00; +op3val:0x8400; valaddr_reg:x2; val_offset:6117*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6117*FLEN/8, x3, x1, x4) + +inst_2074: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7c00; +op3val:0x401; valaddr_reg:x2; val_offset:6120*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6120*FLEN/8, x3, x1, x4) + +inst_2075: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7c00; +op3val:0x8455; valaddr_reg:x2; val_offset:6123*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6123*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_17) + +inst_2076: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7c00; +op3val:0x7bff; valaddr_reg:x2; val_offset:6126*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6126*FLEN/8, x3, x1, x4) + +inst_2077: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7c00; +op3val:0xfbff; valaddr_reg:x2; val_offset:6129*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6129*FLEN/8, x3, x1, x4) + +inst_2078: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7c00; +op3val:0x7c00; valaddr_reg:x2; val_offset:6132*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6132*FLEN/8, x3, x1, x4) + +inst_2079: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7c00; +op3val:0xfc00; valaddr_reg:x2; val_offset:6135*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6135*FLEN/8, x3, x1, x4) + +inst_2080: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7c00; +op3val:0x7e00; valaddr_reg:x2; val_offset:6138*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6138*FLEN/8, x3, x1, x4) + +inst_2081: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7c00; +op3val:0xfe00; valaddr_reg:x2; val_offset:6141*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6141*FLEN/8, x3, x1, x4) + +inst_2082: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7c00; +op3val:0x7e01; valaddr_reg:x2; val_offset:6144*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6144*FLEN/8, x3, x1, x4) + +inst_2083: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7c00; +op3val:0xfe55; valaddr_reg:x2; val_offset:6147*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6147*FLEN/8, x3, x1, x4) + +inst_2084: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7c00; +op3val:0x7c01; valaddr_reg:x2; val_offset:6150*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6150*FLEN/8, x3, x1, x4) + +inst_2085: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7c00; +op3val:0xfd55; valaddr_reg:x2; val_offset:6153*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6153*FLEN/8, x3, x1, x4) + +inst_2086: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7c00; +op3val:0x3c00; valaddr_reg:x2; val_offset:6156*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6156*FLEN/8, x3, x1, x4) + +inst_2087: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7c00; +op3val:0xbc00; valaddr_reg:x2; val_offset:6159*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6159*FLEN/8, x3, x1, x4) + +inst_2088: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfc00; +op3val:0x0; valaddr_reg:x2; val_offset:6162*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6162*FLEN/8, x3, x1, x4) + +inst_2089: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfc00; +op3val:0x8000; valaddr_reg:x2; val_offset:6165*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6165*FLEN/8, x3, x1, x4) + +inst_2090: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfc00; +op3val:0x1; valaddr_reg:x2; val_offset:6168*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6168*FLEN/8, x3, x1, x4) + +inst_2091: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfc00; +op3val:0x8001; valaddr_reg:x2; val_offset:6171*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6171*FLEN/8, x3, x1, x4) + +inst_2092: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfc00; +op3val:0x2; valaddr_reg:x2; val_offset:6174*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6174*FLEN/8, x3, x1, x4) + +inst_2093: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfc00; +op3val:0x83fe; valaddr_reg:x2; val_offset:6177*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6177*FLEN/8, x3, x1, x4) + +inst_2094: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfc00; +op3val:0x3ff; valaddr_reg:x2; val_offset:6180*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6180*FLEN/8, x3, x1, x4) + +inst_2095: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfc00; +op3val:0x83ff; valaddr_reg:x2; val_offset:6183*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6183*FLEN/8, x3, x1, x4) + +inst_2096: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfc00; +op3val:0x400; valaddr_reg:x2; val_offset:6186*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6186*FLEN/8, x3, x1, x4) + +inst_2097: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfc00; +op3val:0x8400; valaddr_reg:x2; val_offset:6189*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6189*FLEN/8, x3, x1, x4) + +inst_2098: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfc00; +op3val:0x401; valaddr_reg:x2; val_offset:6192*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6192*FLEN/8, x3, x1, x4) + +inst_2099: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfc00; +op3val:0x8455; valaddr_reg:x2; val_offset:6195*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6195*FLEN/8, x3, x1, x4) + +inst_2100: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfc00; +op3val:0x7bff; valaddr_reg:x2; val_offset:6198*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6198*FLEN/8, x3, x1, x4) + +inst_2101: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfc00; +op3val:0xfbff; valaddr_reg:x2; val_offset:6201*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6201*FLEN/8, x3, x1, x4) + +inst_2102: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfc00; +op3val:0x7c00; valaddr_reg:x2; val_offset:6204*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6204*FLEN/8, x3, x1, x4) + +inst_2103: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfc00; +op3val:0xfc00; valaddr_reg:x2; val_offset:6207*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6207*FLEN/8, x3, x1, x4) + +inst_2104: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfc00; +op3val:0x7e00; valaddr_reg:x2; val_offset:6210*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6210*FLEN/8, x3, x1, x4) + +inst_2105: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfc00; +op3val:0xfe00; valaddr_reg:x2; val_offset:6213*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6213*FLEN/8, x3, x1, x4) + +inst_2106: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfc00; +op3val:0x7e01; valaddr_reg:x2; val_offset:6216*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6216*FLEN/8, x3, x1, x4) + +inst_2107: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfc00; +op3val:0xfe55; valaddr_reg:x2; val_offset:6219*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6219*FLEN/8, x3, x1, x4) + +inst_2108: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfc00; +op3val:0x7c01; valaddr_reg:x2; val_offset:6222*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6222*FLEN/8, x3, x1, x4) + +inst_2109: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfc00; +op3val:0xfd55; valaddr_reg:x2; val_offset:6225*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6225*FLEN/8, x3, x1, x4) + +inst_2110: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfc00; +op3val:0x3c00; valaddr_reg:x2; val_offset:6228*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6228*FLEN/8, x3, x1, x4) + +inst_2111: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfc00; +op3val:0xbc00; valaddr_reg:x2; val_offset:6231*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6231*FLEN/8, x3, x1, x4) + +inst_2112: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7e00; +op3val:0x0; valaddr_reg:x2; val_offset:6234*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6234*FLEN/8, x3, x1, x4) + +inst_2113: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7e00; +op3val:0x8000; valaddr_reg:x2; val_offset:6237*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6237*FLEN/8, x3, x1, x4) + +inst_2114: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7e00; +op3val:0x1; valaddr_reg:x2; val_offset:6240*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6240*FLEN/8, x3, x1, x4) + +inst_2115: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7e00; +op3val:0x8001; valaddr_reg:x2; val_offset:6243*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6243*FLEN/8, x3, x1, x4) + +inst_2116: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7e00; +op3val:0x2; valaddr_reg:x2; val_offset:6246*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6246*FLEN/8, x3, x1, x4) + +inst_2117: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7e00; +op3val:0x83fe; valaddr_reg:x2; val_offset:6249*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6249*FLEN/8, x3, x1, x4) + +inst_2118: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7e00; +op3val:0x3ff; valaddr_reg:x2; val_offset:6252*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6252*FLEN/8, x3, x1, x4) + +inst_2119: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7e00; +op3val:0x83ff; valaddr_reg:x2; val_offset:6255*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6255*FLEN/8, x3, x1, x4) + +inst_2120: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7e00; +op3val:0x400; valaddr_reg:x2; val_offset:6258*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6258*FLEN/8, x3, x1, x4) + +inst_2121: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7e00; +op3val:0x8400; valaddr_reg:x2; val_offset:6261*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6261*FLEN/8, x3, x1, x4) + +inst_2122: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7e00; +op3val:0x401; valaddr_reg:x2; val_offset:6264*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6264*FLEN/8, x3, x1, x4) + +inst_2123: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7e00; +op3val:0x8455; valaddr_reg:x2; val_offset:6267*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6267*FLEN/8, x3, x1, x4) + +inst_2124: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7e00; +op3val:0x7bff; valaddr_reg:x2; val_offset:6270*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6270*FLEN/8, x3, x1, x4) + +inst_2125: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7e00; +op3val:0xfbff; valaddr_reg:x2; val_offset:6273*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6273*FLEN/8, x3, x1, x4) + +inst_2126: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7e00; +op3val:0x7c00; valaddr_reg:x2; val_offset:6276*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6276*FLEN/8, x3, x1, x4) + +inst_2127: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7e00; +op3val:0xfc00; valaddr_reg:x2; val_offset:6279*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6279*FLEN/8, x3, x1, x4) + +inst_2128: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7e00; +op3val:0x7e00; valaddr_reg:x2; val_offset:6282*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6282*FLEN/8, x3, x1, x4) + +inst_2129: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7e00; +op3val:0xfe00; valaddr_reg:x2; val_offset:6285*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6285*FLEN/8, x3, x1, x4) + +inst_2130: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7e00; +op3val:0x7e01; valaddr_reg:x2; val_offset:6288*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6288*FLEN/8, x3, x1, x4) + +inst_2131: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7e00; +op3val:0xfe55; valaddr_reg:x2; val_offset:6291*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6291*FLEN/8, x3, x1, x4) + +inst_2132: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7e00; +op3val:0x7c01; valaddr_reg:x2; val_offset:6294*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6294*FLEN/8, x3, x1, x4) + +inst_2133: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7e00; +op3val:0xfd55; valaddr_reg:x2; val_offset:6297*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6297*FLEN/8, x3, x1, x4) + +inst_2134: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7e00; +op3val:0x3c00; valaddr_reg:x2; val_offset:6300*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6300*FLEN/8, x3, x1, x4) + +inst_2135: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7e00; +op3val:0xbc00; valaddr_reg:x2; val_offset:6303*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6303*FLEN/8, x3, x1, x4) + +inst_2136: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfe00; +op3val:0x0; valaddr_reg:x2; val_offset:6306*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6306*FLEN/8, x3, x1, x4) + +inst_2137: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfe00; +op3val:0x8000; valaddr_reg:x2; val_offset:6309*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6309*FLEN/8, x3, x1, x4) + +inst_2138: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfe00; +op3val:0x1; valaddr_reg:x2; val_offset:6312*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6312*FLEN/8, x3, x1, x4) + +inst_2139: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfe00; +op3val:0x8001; valaddr_reg:x2; val_offset:6315*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6315*FLEN/8, x3, x1, x4) + +inst_2140: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfe00; +op3val:0x2; valaddr_reg:x2; val_offset:6318*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6318*FLEN/8, x3, x1, x4) + +inst_2141: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfe00; +op3val:0x83fe; valaddr_reg:x2; val_offset:6321*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6321*FLEN/8, x3, x1, x4) + +inst_2142: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfe00; +op3val:0x3ff; valaddr_reg:x2; val_offset:6324*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6324*FLEN/8, x3, x1, x4) + +inst_2143: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfe00; +op3val:0x83ff; valaddr_reg:x2; val_offset:6327*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6327*FLEN/8, x3, x1, x4) + +inst_2144: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfe00; +op3val:0x400; valaddr_reg:x2; val_offset:6330*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6330*FLEN/8, x3, x1, x4) + +inst_2145: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfe00; +op3val:0x8400; valaddr_reg:x2; val_offset:6333*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6333*FLEN/8, x3, x1, x4) + +inst_2146: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfe00; +op3val:0x401; valaddr_reg:x2; val_offset:6336*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6336*FLEN/8, x3, x1, x4) + +inst_2147: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfe00; +op3val:0x8455; valaddr_reg:x2; val_offset:6339*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6339*FLEN/8, x3, x1, x4) + +inst_2148: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfe00; +op3val:0x7bff; valaddr_reg:x2; val_offset:6342*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6342*FLEN/8, x3, x1, x4) + +inst_2149: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfe00; +op3val:0xfbff; valaddr_reg:x2; val_offset:6345*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6345*FLEN/8, x3, x1, x4) + +inst_2150: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfe00; +op3val:0x7c00; valaddr_reg:x2; val_offset:6348*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6348*FLEN/8, x3, x1, x4) + +inst_2151: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfe00; +op3val:0xfc00; valaddr_reg:x2; val_offset:6351*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6351*FLEN/8, x3, x1, x4) + +inst_2152: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfe00; +op3val:0x7e00; valaddr_reg:x2; val_offset:6354*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6354*FLEN/8, x3, x1, x4) + +inst_2153: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfe00; +op3val:0xfe00; valaddr_reg:x2; val_offset:6357*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6357*FLEN/8, x3, x1, x4) + +inst_2154: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfe00; +op3val:0x7e01; valaddr_reg:x2; val_offset:6360*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6360*FLEN/8, x3, x1, x4) + +inst_2155: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfe00; +op3val:0xfe55; valaddr_reg:x2; val_offset:6363*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6363*FLEN/8, x3, x1, x4) + +inst_2156: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfe00; +op3val:0x7c01; valaddr_reg:x2; val_offset:6366*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6366*FLEN/8, x3, x1, x4) + +inst_2157: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfe00; +op3val:0xfd55; valaddr_reg:x2; val_offset:6369*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6369*FLEN/8, x3, x1, x4) + +inst_2158: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfe00; +op3val:0x3c00; valaddr_reg:x2; val_offset:6372*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6372*FLEN/8, x3, x1, x4) + +inst_2159: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfe00; +op3val:0xbc00; valaddr_reg:x2; val_offset:6375*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6375*FLEN/8, x3, x1, x4) + +inst_2160: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7e01; +op3val:0x0; valaddr_reg:x2; val_offset:6378*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6378*FLEN/8, x3, x1, x4) + +inst_2161: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7e01; +op3val:0x8000; valaddr_reg:x2; val_offset:6381*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6381*FLEN/8, x3, x1, x4) + +inst_2162: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7e01; +op3val:0x1; valaddr_reg:x2; val_offset:6384*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6384*FLEN/8, x3, x1, x4) + +inst_2163: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7e01; +op3val:0x8001; valaddr_reg:x2; val_offset:6387*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6387*FLEN/8, x3, x1, x4) + +inst_2164: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7e01; +op3val:0x2; valaddr_reg:x2; val_offset:6390*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6390*FLEN/8, x3, x1, x4) + +inst_2165: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7e01; +op3val:0x83fe; valaddr_reg:x2; val_offset:6393*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6393*FLEN/8, x3, x1, x4) + +inst_2166: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7e01; +op3val:0x3ff; valaddr_reg:x2; val_offset:6396*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6396*FLEN/8, x3, x1, x4) + +inst_2167: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7e01; +op3val:0x83ff; valaddr_reg:x2; val_offset:6399*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6399*FLEN/8, x3, x1, x4) + +inst_2168: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7e01; +op3val:0x400; valaddr_reg:x2; val_offset:6402*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6402*FLEN/8, x3, x1, x4) + +inst_2169: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7e01; +op3val:0x8400; valaddr_reg:x2; val_offset:6405*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6405*FLEN/8, x3, x1, x4) + +inst_2170: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7e01; +op3val:0x401; valaddr_reg:x2; val_offset:6408*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6408*FLEN/8, x3, x1, x4) + +inst_2171: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7e01; +op3val:0x8455; valaddr_reg:x2; val_offset:6411*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6411*FLEN/8, x3, x1, x4) + +inst_2172: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7e01; +op3val:0x7bff; valaddr_reg:x2; val_offset:6414*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6414*FLEN/8, x3, x1, x4) + +inst_2173: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7e01; +op3val:0xfbff; valaddr_reg:x2; val_offset:6417*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6417*FLEN/8, x3, x1, x4) + +inst_2174: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7e01; +op3val:0x7c00; valaddr_reg:x2; val_offset:6420*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6420*FLEN/8, x3, x1, x4) + +inst_2175: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7e01; +op3val:0xfc00; valaddr_reg:x2; val_offset:6423*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6423*FLEN/8, x3, x1, x4) + +inst_2176: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7e01; +op3val:0x7e00; valaddr_reg:x2; val_offset:6426*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6426*FLEN/8, x3, x1, x4) + +inst_2177: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7e01; +op3val:0xfe00; valaddr_reg:x2; val_offset:6429*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6429*FLEN/8, x3, x1, x4) + +inst_2178: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7e01; +op3val:0x7e01; valaddr_reg:x2; val_offset:6432*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6432*FLEN/8, x3, x1, x4) + +inst_2179: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7e01; +op3val:0xfe55; valaddr_reg:x2; val_offset:6435*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6435*FLEN/8, x3, x1, x4) + +inst_2180: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7e01; +op3val:0x7c01; valaddr_reg:x2; val_offset:6438*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6438*FLEN/8, x3, x1, x4) + +inst_2181: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7e01; +op3val:0xfd55; valaddr_reg:x2; val_offset:6441*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6441*FLEN/8, x3, x1, x4) + +inst_2182: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7e01; +op3val:0x3c00; valaddr_reg:x2; val_offset:6444*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6444*FLEN/8, x3, x1, x4) + +inst_2183: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7e01; +op3val:0xbc00; valaddr_reg:x2; val_offset:6447*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6447*FLEN/8, x3, x1, x4) + +inst_2184: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfe55; +op3val:0x0; valaddr_reg:x2; val_offset:6450*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6450*FLEN/8, x3, x1, x4) + +inst_2185: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfe55; +op3val:0x8000; valaddr_reg:x2; val_offset:6453*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6453*FLEN/8, x3, x1, x4) + +inst_2186: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfe55; +op3val:0x1; valaddr_reg:x2; val_offset:6456*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6456*FLEN/8, x3, x1, x4) + +inst_2187: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfe55; +op3val:0x8001; valaddr_reg:x2; val_offset:6459*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6459*FLEN/8, x3, x1, x4) + +inst_2188: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfe55; +op3val:0x2; valaddr_reg:x2; val_offset:6462*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6462*FLEN/8, x3, x1, x4) + +inst_2189: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfe55; +op3val:0x83fe; valaddr_reg:x2; val_offset:6465*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6465*FLEN/8, x3, x1, x4) + +inst_2190: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfe55; +op3val:0x3ff; valaddr_reg:x2; val_offset:6468*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6468*FLEN/8, x3, x1, x4) + +inst_2191: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfe55; +op3val:0x83ff; valaddr_reg:x2; val_offset:6471*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6471*FLEN/8, x3, x1, x4) + +inst_2192: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfe55; +op3val:0x400; valaddr_reg:x2; val_offset:6474*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6474*FLEN/8, x3, x1, x4) + +inst_2193: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfe55; +op3val:0x8400; valaddr_reg:x2; val_offset:6477*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6477*FLEN/8, x3, x1, x4) + +inst_2194: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfe55; +op3val:0x401; valaddr_reg:x2; val_offset:6480*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6480*FLEN/8, x3, x1, x4) + +inst_2195: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfe55; +op3val:0x8455; valaddr_reg:x2; val_offset:6483*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6483*FLEN/8, x3, x1, x4) + +inst_2196: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfe55; +op3val:0x7bff; valaddr_reg:x2; val_offset:6486*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6486*FLEN/8, x3, x1, x4) + +inst_2197: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfe55; +op3val:0xfbff; valaddr_reg:x2; val_offset:6489*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6489*FLEN/8, x3, x1, x4) + +inst_2198: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfe55; +op3val:0x7c00; valaddr_reg:x2; val_offset:6492*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6492*FLEN/8, x3, x1, x4) + +inst_2199: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfe55; +op3val:0xfc00; valaddr_reg:x2; val_offset:6495*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6495*FLEN/8, x3, x1, x4) + +inst_2200: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfe55; +op3val:0x7e00; valaddr_reg:x2; val_offset:6498*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6498*FLEN/8, x3, x1, x4) + +inst_2201: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfe55; +op3val:0xfe00; valaddr_reg:x2; val_offset:6501*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6501*FLEN/8, x3, x1, x4) + +inst_2202: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfe55; +op3val:0x7e01; valaddr_reg:x2; val_offset:6504*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6504*FLEN/8, x3, x1, x4) + +inst_2203: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfe55; +op3val:0xfe55; valaddr_reg:x2; val_offset:6507*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6507*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_18) + +inst_2204: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfe55; +op3val:0x7c01; valaddr_reg:x2; val_offset:6510*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6510*FLEN/8, x3, x1, x4) + +inst_2205: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfe55; +op3val:0xfd55; valaddr_reg:x2; val_offset:6513*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6513*FLEN/8, x3, x1, x4) + +inst_2206: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfe55; +op3val:0x3c00; valaddr_reg:x2; val_offset:6516*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6516*FLEN/8, x3, x1, x4) + +inst_2207: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfe55; +op3val:0xbc00; valaddr_reg:x2; val_offset:6519*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6519*FLEN/8, x3, x1, x4) + +inst_2208: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7c01; +op3val:0x0; valaddr_reg:x2; val_offset:6522*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6522*FLEN/8, x3, x1, x4) + +inst_2209: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7c01; +op3val:0x8000; valaddr_reg:x2; val_offset:6525*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6525*FLEN/8, x3, x1, x4) + +inst_2210: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7c01; +op3val:0x1; valaddr_reg:x2; val_offset:6528*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6528*FLEN/8, x3, x1, x4) + +inst_2211: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7c01; +op3val:0x8001; valaddr_reg:x2; val_offset:6531*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6531*FLEN/8, x3, x1, x4) + +inst_2212: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7c01; +op3val:0x2; valaddr_reg:x2; val_offset:6534*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6534*FLEN/8, x3, x1, x4) + +inst_2213: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7c01; +op3val:0x83fe; valaddr_reg:x2; val_offset:6537*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6537*FLEN/8, x3, x1, x4) + +inst_2214: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7c01; +op3val:0x3ff; valaddr_reg:x2; val_offset:6540*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6540*FLEN/8, x3, x1, x4) + +inst_2215: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7c01; +op3val:0x83ff; valaddr_reg:x2; val_offset:6543*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6543*FLEN/8, x3, x1, x4) + +inst_2216: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7c01; +op3val:0x400; valaddr_reg:x2; val_offset:6546*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6546*FLEN/8, x3, x1, x4) + +inst_2217: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7c01; +op3val:0x8400; valaddr_reg:x2; val_offset:6549*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6549*FLEN/8, x3, x1, x4) + +inst_2218: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7c01; +op3val:0x401; valaddr_reg:x2; val_offset:6552*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6552*FLEN/8, x3, x1, x4) + +inst_2219: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7c01; +op3val:0x8455; valaddr_reg:x2; val_offset:6555*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6555*FLEN/8, x3, x1, x4) + +inst_2220: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7c01; +op3val:0x7bff; valaddr_reg:x2; val_offset:6558*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6558*FLEN/8, x3, x1, x4) + +inst_2221: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7c01; +op3val:0xfbff; valaddr_reg:x2; val_offset:6561*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6561*FLEN/8, x3, x1, x4) + +inst_2222: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7c01; +op3val:0x7c00; valaddr_reg:x2; val_offset:6564*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6564*FLEN/8, x3, x1, x4) + +inst_2223: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7c01; +op3val:0xfc00; valaddr_reg:x2; val_offset:6567*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6567*FLEN/8, x3, x1, x4) + +inst_2224: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7c01; +op3val:0x7e00; valaddr_reg:x2; val_offset:6570*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6570*FLEN/8, x3, x1, x4) + +inst_2225: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7c01; +op3val:0xfe00; valaddr_reg:x2; val_offset:6573*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6573*FLEN/8, x3, x1, x4) + +inst_2226: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7c01; +op3val:0x7e01; valaddr_reg:x2; val_offset:6576*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6576*FLEN/8, x3, x1, x4) + +inst_2227: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7c01; +op3val:0xfe55; valaddr_reg:x2; val_offset:6579*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6579*FLEN/8, x3, x1, x4) + +inst_2228: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7c01; +op3val:0x7c01; valaddr_reg:x2; val_offset:6582*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6582*FLEN/8, x3, x1, x4) + +inst_2229: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7c01; +op3val:0xfd55; valaddr_reg:x2; val_offset:6585*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6585*FLEN/8, x3, x1, x4) + +inst_2230: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7c01; +op3val:0x3c00; valaddr_reg:x2; val_offset:6588*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6588*FLEN/8, x3, x1, x4) + +inst_2231: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x7c01; +op3val:0xbc00; valaddr_reg:x2; val_offset:6591*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6591*FLEN/8, x3, x1, x4) + +inst_2232: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfd55; +op3val:0x0; valaddr_reg:x2; val_offset:6594*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6594*FLEN/8, x3, x1, x4) + +inst_2233: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfd55; +op3val:0x8000; valaddr_reg:x2; val_offset:6597*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6597*FLEN/8, x3, x1, x4) + +inst_2234: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfd55; +op3val:0x1; valaddr_reg:x2; val_offset:6600*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6600*FLEN/8, x3, x1, x4) + +inst_2235: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfd55; +op3val:0x8001; valaddr_reg:x2; val_offset:6603*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6603*FLEN/8, x3, x1, x4) + +inst_2236: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfd55; +op3val:0x2; valaddr_reg:x2; val_offset:6606*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6606*FLEN/8, x3, x1, x4) + +inst_2237: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfd55; +op3val:0x83fe; valaddr_reg:x2; val_offset:6609*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6609*FLEN/8, x3, x1, x4) + +inst_2238: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfd55; +op3val:0x3ff; valaddr_reg:x2; val_offset:6612*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6612*FLEN/8, x3, x1, x4) + +inst_2239: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfd55; +op3val:0x83ff; valaddr_reg:x2; val_offset:6615*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6615*FLEN/8, x3, x1, x4) + +inst_2240: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfd55; +op3val:0x400; valaddr_reg:x2; val_offset:6618*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6618*FLEN/8, x3, x1, x4) + +inst_2241: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfd55; +op3val:0x8400; valaddr_reg:x2; val_offset:6621*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6621*FLEN/8, x3, x1, x4) + +inst_2242: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfd55; +op3val:0x401; valaddr_reg:x2; val_offset:6624*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6624*FLEN/8, x3, x1, x4) + +inst_2243: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfd55; +op3val:0x8455; valaddr_reg:x2; val_offset:6627*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6627*FLEN/8, x3, x1, x4) + +inst_2244: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfd55; +op3val:0x7bff; valaddr_reg:x2; val_offset:6630*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6630*FLEN/8, x3, x1, x4) + +inst_2245: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfd55; +op3val:0xfbff; valaddr_reg:x2; val_offset:6633*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6633*FLEN/8, x3, x1, x4) + +inst_2246: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfd55; +op3val:0x7c00; valaddr_reg:x2; val_offset:6636*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6636*FLEN/8, x3, x1, x4) + +inst_2247: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfd55; +op3val:0xfc00; valaddr_reg:x2; val_offset:6639*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6639*FLEN/8, x3, x1, x4) + +inst_2248: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfd55; +op3val:0x7e00; valaddr_reg:x2; val_offset:6642*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6642*FLEN/8, x3, x1, x4) + +inst_2249: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfd55; +op3val:0xfe00; valaddr_reg:x2; val_offset:6645*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6645*FLEN/8, x3, x1, x4) + +inst_2250: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfd55; +op3val:0x7e01; valaddr_reg:x2; val_offset:6648*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6648*FLEN/8, x3, x1, x4) + +inst_2251: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfd55; +op3val:0xfe55; valaddr_reg:x2; val_offset:6651*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6651*FLEN/8, x3, x1, x4) + +inst_2252: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfd55; +op3val:0x7c01; valaddr_reg:x2; val_offset:6654*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6654*FLEN/8, x3, x1, x4) + +inst_2253: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfd55; +op3val:0xfd55; valaddr_reg:x2; val_offset:6657*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6657*FLEN/8, x3, x1, x4) + +inst_2254: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfd55; +op3val:0x3c00; valaddr_reg:x2; val_offset:6660*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6660*FLEN/8, x3, x1, x4) + +inst_2255: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xfd55; +op3val:0xbc00; valaddr_reg:x2; val_offset:6663*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6663*FLEN/8, x3, x1, x4) + +inst_2256: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x3c00; +op3val:0x0; valaddr_reg:x2; val_offset:6666*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6666*FLEN/8, x3, x1, x4) + +inst_2257: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x3c00; +op3val:0x8000; valaddr_reg:x2; val_offset:6669*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6669*FLEN/8, x3, x1, x4) + +inst_2258: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x3c00; +op3val:0x1; valaddr_reg:x2; val_offset:6672*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6672*FLEN/8, x3, x1, x4) + +inst_2259: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x3c00; +op3val:0x8001; valaddr_reg:x2; val_offset:6675*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6675*FLEN/8, x3, x1, x4) + +inst_2260: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x3c00; +op3val:0x2; valaddr_reg:x2; val_offset:6678*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6678*FLEN/8, x3, x1, x4) + +inst_2261: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x3c00; +op3val:0x83fe; valaddr_reg:x2; val_offset:6681*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6681*FLEN/8, x3, x1, x4) + +inst_2262: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x3c00; +op3val:0x3ff; valaddr_reg:x2; val_offset:6684*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6684*FLEN/8, x3, x1, x4) + +inst_2263: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x3c00; +op3val:0x83ff; valaddr_reg:x2; val_offset:6687*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6687*FLEN/8, x3, x1, x4) + +inst_2264: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x3c00; +op3val:0x400; valaddr_reg:x2; val_offset:6690*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6690*FLEN/8, x3, x1, x4) + +inst_2265: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x3c00; +op3val:0x8400; valaddr_reg:x2; val_offset:6693*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6693*FLEN/8, x3, x1, x4) + +inst_2266: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x3c00; +op3val:0x401; valaddr_reg:x2; val_offset:6696*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6696*FLEN/8, x3, x1, x4) + +inst_2267: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x3c00; +op3val:0x8455; valaddr_reg:x2; val_offset:6699*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6699*FLEN/8, x3, x1, x4) + +inst_2268: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x3c00; +op3val:0x7bff; valaddr_reg:x2; val_offset:6702*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6702*FLEN/8, x3, x1, x4) + +inst_2269: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x3c00; +op3val:0xfbff; valaddr_reg:x2; val_offset:6705*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6705*FLEN/8, x3, x1, x4) + +inst_2270: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x3c00; +op3val:0x7c00; valaddr_reg:x2; val_offset:6708*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6708*FLEN/8, x3, x1, x4) + +inst_2271: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x3c00; +op3val:0xfc00; valaddr_reg:x2; val_offset:6711*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6711*FLEN/8, x3, x1, x4) + +inst_2272: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x3c00; +op3val:0x7e00; valaddr_reg:x2; val_offset:6714*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6714*FLEN/8, x3, x1, x4) + +inst_2273: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x3c00; +op3val:0xfe00; valaddr_reg:x2; val_offset:6717*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6717*FLEN/8, x3, x1, x4) + +inst_2274: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x3c00; +op3val:0x7e01; valaddr_reg:x2; val_offset:6720*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6720*FLEN/8, x3, x1, x4) + +inst_2275: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x3c00; +op3val:0xfe55; valaddr_reg:x2; val_offset:6723*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6723*FLEN/8, x3, x1, x4) + +inst_2276: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x3c00; +op3val:0x7c01; valaddr_reg:x2; val_offset:6726*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6726*FLEN/8, x3, x1, x4) + +inst_2277: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x3c00; +op3val:0xfd55; valaddr_reg:x2; val_offset:6729*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6729*FLEN/8, x3, x1, x4) + +inst_2278: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x3c00; +op3val:0x3c00; valaddr_reg:x2; val_offset:6732*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6732*FLEN/8, x3, x1, x4) + +inst_2279: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0x3c00; +op3val:0xbc00; valaddr_reg:x2; val_offset:6735*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6735*FLEN/8, x3, x1, x4) + +inst_2280: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xbc00; +op3val:0x0; valaddr_reg:x2; val_offset:6738*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6738*FLEN/8, x3, x1, x4) + +inst_2281: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xbc00; +op3val:0x8000; valaddr_reg:x2; val_offset:6741*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6741*FLEN/8, x3, x1, x4) + +inst_2282: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xbc00; +op3val:0x1; valaddr_reg:x2; val_offset:6744*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6744*FLEN/8, x3, x1, x4) + +inst_2283: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xbc00; +op3val:0x8001; valaddr_reg:x2; val_offset:6747*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6747*FLEN/8, x3, x1, x4) + +inst_2284: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xbc00; +op3val:0x2; valaddr_reg:x2; val_offset:6750*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6750*FLEN/8, x3, x1, x4) + +inst_2285: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xbc00; +op3val:0x83fe; valaddr_reg:x2; val_offset:6753*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6753*FLEN/8, x3, x1, x4) + +inst_2286: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xbc00; +op3val:0x3ff; valaddr_reg:x2; val_offset:6756*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6756*FLEN/8, x3, x1, x4) + +inst_2287: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xbc00; +op3val:0x83ff; valaddr_reg:x2; val_offset:6759*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6759*FLEN/8, x3, x1, x4) + +inst_2288: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xbc00; +op3val:0x400; valaddr_reg:x2; val_offset:6762*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6762*FLEN/8, x3, x1, x4) + +inst_2289: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xbc00; +op3val:0x8400; valaddr_reg:x2; val_offset:6765*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6765*FLEN/8, x3, x1, x4) + +inst_2290: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xbc00; +op3val:0x401; valaddr_reg:x2; val_offset:6768*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6768*FLEN/8, x3, x1, x4) + +inst_2291: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xbc00; +op3val:0x8455; valaddr_reg:x2; val_offset:6771*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6771*FLEN/8, x3, x1, x4) + +inst_2292: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xbc00; +op3val:0x7bff; valaddr_reg:x2; val_offset:6774*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6774*FLEN/8, x3, x1, x4) + +inst_2293: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xbc00; +op3val:0xfbff; valaddr_reg:x2; val_offset:6777*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6777*FLEN/8, x3, x1, x4) + +inst_2294: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xbc00; +op3val:0x7c00; valaddr_reg:x2; val_offset:6780*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6780*FLEN/8, x3, x1, x4) + +inst_2295: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xbc00; +op3val:0xfc00; valaddr_reg:x2; val_offset:6783*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6783*FLEN/8, x3, x1, x4) + +inst_2296: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xbc00; +op3val:0x7e00; valaddr_reg:x2; val_offset:6786*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6786*FLEN/8, x3, x1, x4) + +inst_2297: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xbc00; +op3val:0xfe00; valaddr_reg:x2; val_offset:6789*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6789*FLEN/8, x3, x1, x4) + +inst_2298: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xbc00; +op3val:0x7e01; valaddr_reg:x2; val_offset:6792*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6792*FLEN/8, x3, x1, x4) + +inst_2299: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xbc00; +op3val:0xfe55; valaddr_reg:x2; val_offset:6795*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6795*FLEN/8, x3, x1, x4) + +inst_2300: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xbc00; +op3val:0x7c01; valaddr_reg:x2; val_offset:6798*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6798*FLEN/8, x3, x1, x4) + +inst_2301: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xbc00; +op3val:0xfd55; valaddr_reg:x2; val_offset:6801*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6801*FLEN/8, x3, x1, x4) + +inst_2302: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xbc00; +op3val:0x3c00; valaddr_reg:x2; val_offset:6804*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6804*FLEN/8, x3, x1, x4) + +inst_2303: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8001; op2val:0xbc00; +op3val:0xbc00; valaddr_reg:x2; val_offset:6807*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6807*FLEN/8, x3, x1, x4) + +inst_2304: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x0; +op3val:0x0; valaddr_reg:x2; val_offset:6810*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6810*FLEN/8, x3, x1, x4) + +inst_2305: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x0; +op3val:0x8000; valaddr_reg:x2; val_offset:6813*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6813*FLEN/8, x3, x1, x4) + +inst_2306: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x0; +op3val:0x1; valaddr_reg:x2; val_offset:6816*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6816*FLEN/8, x3, x1, x4) + +inst_2307: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x0; +op3val:0x8001; valaddr_reg:x2; val_offset:6819*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6819*FLEN/8, x3, x1, x4) + +inst_2308: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x0; +op3val:0x2; valaddr_reg:x2; val_offset:6822*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6822*FLEN/8, x3, x1, x4) + +inst_2309: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x0; +op3val:0x83fe; valaddr_reg:x2; val_offset:6825*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6825*FLEN/8, x3, x1, x4) + +inst_2310: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x0; +op3val:0x3ff; valaddr_reg:x2; val_offset:6828*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6828*FLEN/8, x3, x1, x4) + +inst_2311: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x0; +op3val:0x83ff; valaddr_reg:x2; val_offset:6831*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6831*FLEN/8, x3, x1, x4) + +inst_2312: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x0; +op3val:0x400; valaddr_reg:x2; val_offset:6834*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6834*FLEN/8, x3, x1, x4) + +inst_2313: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x0; +op3val:0x8400; valaddr_reg:x2; val_offset:6837*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6837*FLEN/8, x3, x1, x4) + +inst_2314: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x0; +op3val:0x401; valaddr_reg:x2; val_offset:6840*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6840*FLEN/8, x3, x1, x4) + +inst_2315: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x0; +op3val:0x8455; valaddr_reg:x2; val_offset:6843*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6843*FLEN/8, x3, x1, x4) + +inst_2316: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x0; +op3val:0x7bff; valaddr_reg:x2; val_offset:6846*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6846*FLEN/8, x3, x1, x4) + +inst_2317: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x0; +op3val:0xfbff; valaddr_reg:x2; val_offset:6849*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6849*FLEN/8, x3, x1, x4) + +inst_2318: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x0; +op3val:0x7c00; valaddr_reg:x2; val_offset:6852*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6852*FLEN/8, x3, x1, x4) + +inst_2319: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x0; +op3val:0xfc00; valaddr_reg:x2; val_offset:6855*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6855*FLEN/8, x3, x1, x4) + +inst_2320: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x0; +op3val:0x7e00; valaddr_reg:x2; val_offset:6858*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6858*FLEN/8, x3, x1, x4) + +inst_2321: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x0; +op3val:0xfe00; valaddr_reg:x2; val_offset:6861*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6861*FLEN/8, x3, x1, x4) + +inst_2322: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x0; +op3val:0x7e01; valaddr_reg:x2; val_offset:6864*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6864*FLEN/8, x3, x1, x4) + +inst_2323: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x0; +op3val:0xfe55; valaddr_reg:x2; val_offset:6867*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6867*FLEN/8, x3, x1, x4) + +inst_2324: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x0; +op3val:0x7c01; valaddr_reg:x2; val_offset:6870*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6870*FLEN/8, x3, x1, x4) + +inst_2325: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x0; +op3val:0xfd55; valaddr_reg:x2; val_offset:6873*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6873*FLEN/8, x3, x1, x4) + +inst_2326: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x0; +op3val:0x3c00; valaddr_reg:x2; val_offset:6876*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6876*FLEN/8, x3, x1, x4) + +inst_2327: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x0; +op3val:0xbc00; valaddr_reg:x2; val_offset:6879*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6879*FLEN/8, x3, x1, x4) + +inst_2328: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8000; +op3val:0x0; valaddr_reg:x2; val_offset:6882*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6882*FLEN/8, x3, x1, x4) + +inst_2329: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8000; +op3val:0x8000; valaddr_reg:x2; val_offset:6885*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6885*FLEN/8, x3, x1, x4) + +inst_2330: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8000; +op3val:0x1; valaddr_reg:x2; val_offset:6888*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6888*FLEN/8, x3, x1, x4) + +inst_2331: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8000; +op3val:0x8001; valaddr_reg:x2; val_offset:6891*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6891*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_19) + +inst_2332: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8000; +op3val:0x2; valaddr_reg:x2; val_offset:6894*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6894*FLEN/8, x3, x1, x4) + +inst_2333: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8000; +op3val:0x83fe; valaddr_reg:x2; val_offset:6897*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6897*FLEN/8, x3, x1, x4) + +inst_2334: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8000; +op3val:0x3ff; valaddr_reg:x2; val_offset:6900*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6900*FLEN/8, x3, x1, x4) + +inst_2335: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8000; +op3val:0x83ff; valaddr_reg:x2; val_offset:6903*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6903*FLEN/8, x3, x1, x4) + +inst_2336: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8000; +op3val:0x400; valaddr_reg:x2; val_offset:6906*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6906*FLEN/8, x3, x1, x4) + +inst_2337: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8000; +op3val:0x8400; valaddr_reg:x2; val_offset:6909*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6909*FLEN/8, x3, x1, x4) + +inst_2338: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8000; +op3val:0x401; valaddr_reg:x2; val_offset:6912*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6912*FLEN/8, x3, x1, x4) + +inst_2339: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8000; +op3val:0x8455; valaddr_reg:x2; val_offset:6915*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6915*FLEN/8, x3, x1, x4) + +inst_2340: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x2; val_offset:6918*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6918*FLEN/8, x3, x1, x4) + +inst_2341: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x2; val_offset:6921*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6921*FLEN/8, x3, x1, x4) + +inst_2342: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8000; +op3val:0x7c00; valaddr_reg:x2; val_offset:6924*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6924*FLEN/8, x3, x1, x4) + +inst_2343: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8000; +op3val:0xfc00; valaddr_reg:x2; val_offset:6927*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6927*FLEN/8, x3, x1, x4) + +inst_2344: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8000; +op3val:0x7e00; valaddr_reg:x2; val_offset:6930*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6930*FLEN/8, x3, x1, x4) + +inst_2345: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8000; +op3val:0xfe00; valaddr_reg:x2; val_offset:6933*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6933*FLEN/8, x3, x1, x4) + +inst_2346: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8000; +op3val:0x7e01; valaddr_reg:x2; val_offset:6936*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6936*FLEN/8, x3, x1, x4) + +inst_2347: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8000; +op3val:0xfe55; valaddr_reg:x2; val_offset:6939*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6939*FLEN/8, x3, x1, x4) + +inst_2348: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8000; +op3val:0x7c01; valaddr_reg:x2; val_offset:6942*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6942*FLEN/8, x3, x1, x4) + +inst_2349: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8000; +op3val:0xfd55; valaddr_reg:x2; val_offset:6945*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6945*FLEN/8, x3, x1, x4) + +inst_2350: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8000; +op3val:0x3c00; valaddr_reg:x2; val_offset:6948*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6948*FLEN/8, x3, x1, x4) + +inst_2351: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8000; +op3val:0xbc00; valaddr_reg:x2; val_offset:6951*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6951*FLEN/8, x3, x1, x4) + +inst_2352: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x1; +op3val:0x0; valaddr_reg:x2; val_offset:6954*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6954*FLEN/8, x3, x1, x4) + +inst_2353: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x1; +op3val:0x8000; valaddr_reg:x2; val_offset:6957*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6957*FLEN/8, x3, x1, x4) + +inst_2354: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x1; +op3val:0x1; valaddr_reg:x2; val_offset:6960*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6960*FLEN/8, x3, x1, x4) + +inst_2355: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x1; +op3val:0x8001; valaddr_reg:x2; val_offset:6963*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6963*FLEN/8, x3, x1, x4) + +inst_2356: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x1; +op3val:0x2; valaddr_reg:x2; val_offset:6966*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6966*FLEN/8, x3, x1, x4) + +inst_2357: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x1; +op3val:0x83fe; valaddr_reg:x2; val_offset:6969*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6969*FLEN/8, x3, x1, x4) + +inst_2358: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x1; +op3val:0x3ff; valaddr_reg:x2; val_offset:6972*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6972*FLEN/8, x3, x1, x4) + +inst_2359: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x1; +op3val:0x83ff; valaddr_reg:x2; val_offset:6975*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6975*FLEN/8, x3, x1, x4) + +inst_2360: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x1; +op3val:0x400; valaddr_reg:x2; val_offset:6978*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6978*FLEN/8, x3, x1, x4) + +inst_2361: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x1; +op3val:0x8400; valaddr_reg:x2; val_offset:6981*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6981*FLEN/8, x3, x1, x4) + +inst_2362: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x1; +op3val:0x401; valaddr_reg:x2; val_offset:6984*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6984*FLEN/8, x3, x1, x4) + +inst_2363: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x1; +op3val:0x8455; valaddr_reg:x2; val_offset:6987*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6987*FLEN/8, x3, x1, x4) + +inst_2364: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x1; +op3val:0x7bff; valaddr_reg:x2; val_offset:6990*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6990*FLEN/8, x3, x1, x4) + +inst_2365: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x1; +op3val:0xfbff; valaddr_reg:x2; val_offset:6993*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6993*FLEN/8, x3, x1, x4) + +inst_2366: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x1; +op3val:0x7c00; valaddr_reg:x2; val_offset:6996*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6996*FLEN/8, x3, x1, x4) + +inst_2367: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x1; +op3val:0xfc00; valaddr_reg:x2; val_offset:6999*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6999*FLEN/8, x3, x1, x4) + +inst_2368: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x1; +op3val:0x7e00; valaddr_reg:x2; val_offset:7002*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7002*FLEN/8, x3, x1, x4) + +inst_2369: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x1; +op3val:0xfe00; valaddr_reg:x2; val_offset:7005*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7005*FLEN/8, x3, x1, x4) + +inst_2370: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x1; +op3val:0x7e01; valaddr_reg:x2; val_offset:7008*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7008*FLEN/8, x3, x1, x4) + +inst_2371: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x1; +op3val:0xfe55; valaddr_reg:x2; val_offset:7011*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7011*FLEN/8, x3, x1, x4) + +inst_2372: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x1; +op3val:0x7c01; valaddr_reg:x2; val_offset:7014*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7014*FLEN/8, x3, x1, x4) + +inst_2373: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x1; +op3val:0xfd55; valaddr_reg:x2; val_offset:7017*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7017*FLEN/8, x3, x1, x4) + +inst_2374: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x1; +op3val:0x3c00; valaddr_reg:x2; val_offset:7020*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7020*FLEN/8, x3, x1, x4) + +inst_2375: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x1; +op3val:0xbc00; valaddr_reg:x2; val_offset:7023*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7023*FLEN/8, x3, x1, x4) + +inst_2376: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8001; +op3val:0x0; valaddr_reg:x2; val_offset:7026*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7026*FLEN/8, x3, x1, x4) + +inst_2377: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8001; +op3val:0x8000; valaddr_reg:x2; val_offset:7029*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7029*FLEN/8, x3, x1, x4) + +inst_2378: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8001; +op3val:0x1; valaddr_reg:x2; val_offset:7032*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7032*FLEN/8, x3, x1, x4) + +inst_2379: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8001; +op3val:0x8001; valaddr_reg:x2; val_offset:7035*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7035*FLEN/8, x3, x1, x4) + +inst_2380: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8001; +op3val:0x2; valaddr_reg:x2; val_offset:7038*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7038*FLEN/8, x3, x1, x4) + +inst_2381: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8001; +op3val:0x83fe; valaddr_reg:x2; val_offset:7041*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7041*FLEN/8, x3, x1, x4) + +inst_2382: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8001; +op3val:0x3ff; valaddr_reg:x2; val_offset:7044*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7044*FLEN/8, x3, x1, x4) + +inst_2383: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8001; +op3val:0x83ff; valaddr_reg:x2; val_offset:7047*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7047*FLEN/8, x3, x1, x4) + +inst_2384: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8001; +op3val:0x400; valaddr_reg:x2; val_offset:7050*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7050*FLEN/8, x3, x1, x4) + +inst_2385: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8001; +op3val:0x8400; valaddr_reg:x2; val_offset:7053*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7053*FLEN/8, x3, x1, x4) + +inst_2386: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8001; +op3val:0x401; valaddr_reg:x2; val_offset:7056*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7056*FLEN/8, x3, x1, x4) + +inst_2387: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8001; +op3val:0x8455; valaddr_reg:x2; val_offset:7059*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7059*FLEN/8, x3, x1, x4) + +inst_2388: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8001; +op3val:0x7bff; valaddr_reg:x2; val_offset:7062*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7062*FLEN/8, x3, x1, x4) + +inst_2389: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8001; +op3val:0xfbff; valaddr_reg:x2; val_offset:7065*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7065*FLEN/8, x3, x1, x4) + +inst_2390: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8001; +op3val:0x7c00; valaddr_reg:x2; val_offset:7068*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7068*FLEN/8, x3, x1, x4) + +inst_2391: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8001; +op3val:0xfc00; valaddr_reg:x2; val_offset:7071*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7071*FLEN/8, x3, x1, x4) + +inst_2392: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8001; +op3val:0x7e00; valaddr_reg:x2; val_offset:7074*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7074*FLEN/8, x3, x1, x4) + +inst_2393: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8001; +op3val:0xfe00; valaddr_reg:x2; val_offset:7077*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7077*FLEN/8, x3, x1, x4) + +inst_2394: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8001; +op3val:0x7e01; valaddr_reg:x2; val_offset:7080*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7080*FLEN/8, x3, x1, x4) + +inst_2395: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8001; +op3val:0xfe55; valaddr_reg:x2; val_offset:7083*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7083*FLEN/8, x3, x1, x4) + +inst_2396: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8001; +op3val:0x7c01; valaddr_reg:x2; val_offset:7086*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7086*FLEN/8, x3, x1, x4) + +inst_2397: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8001; +op3val:0xfd55; valaddr_reg:x2; val_offset:7089*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7089*FLEN/8, x3, x1, x4) + +inst_2398: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8001; +op3val:0x3c00; valaddr_reg:x2; val_offset:7092*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7092*FLEN/8, x3, x1, x4) + +inst_2399: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8001; +op3val:0xbc00; valaddr_reg:x2; val_offset:7095*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7095*FLEN/8, x3, x1, x4) + +inst_2400: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x2; +op3val:0x0; valaddr_reg:x2; val_offset:7098*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7098*FLEN/8, x3, x1, x4) + +inst_2401: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x2; +op3val:0x8000; valaddr_reg:x2; val_offset:7101*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7101*FLEN/8, x3, x1, x4) + +inst_2402: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x2; +op3val:0x1; valaddr_reg:x2; val_offset:7104*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7104*FLEN/8, x3, x1, x4) + +inst_2403: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x2; +op3val:0x8001; valaddr_reg:x2; val_offset:7107*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7107*FLEN/8, x3, x1, x4) + +inst_2404: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x2; +op3val:0x2; valaddr_reg:x2; val_offset:7110*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7110*FLEN/8, x3, x1, x4) + +inst_2405: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x2; +op3val:0x83fe; valaddr_reg:x2; val_offset:7113*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7113*FLEN/8, x3, x1, x4) + +inst_2406: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x2; +op3val:0x3ff; valaddr_reg:x2; val_offset:7116*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7116*FLEN/8, x3, x1, x4) + +inst_2407: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x2; +op3val:0x83ff; valaddr_reg:x2; val_offset:7119*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7119*FLEN/8, x3, x1, x4) + +inst_2408: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x2; +op3val:0x400; valaddr_reg:x2; val_offset:7122*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7122*FLEN/8, x3, x1, x4) + +inst_2409: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x2; +op3val:0x8400; valaddr_reg:x2; val_offset:7125*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7125*FLEN/8, x3, x1, x4) + +inst_2410: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x2; +op3val:0x401; valaddr_reg:x2; val_offset:7128*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7128*FLEN/8, x3, x1, x4) + +inst_2411: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x2; +op3val:0x8455; valaddr_reg:x2; val_offset:7131*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7131*FLEN/8, x3, x1, x4) + +inst_2412: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x2; +op3val:0x7bff; valaddr_reg:x2; val_offset:7134*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7134*FLEN/8, x3, x1, x4) + +inst_2413: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x2; +op3val:0xfbff; valaddr_reg:x2; val_offset:7137*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7137*FLEN/8, x3, x1, x4) + +inst_2414: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x2; +op3val:0x7c00; valaddr_reg:x2; val_offset:7140*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7140*FLEN/8, x3, x1, x4) + +inst_2415: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x2; +op3val:0xfc00; valaddr_reg:x2; val_offset:7143*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7143*FLEN/8, x3, x1, x4) + +inst_2416: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x2; +op3val:0x7e00; valaddr_reg:x2; val_offset:7146*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7146*FLEN/8, x3, x1, x4) + +inst_2417: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x2; +op3val:0xfe00; valaddr_reg:x2; val_offset:7149*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7149*FLEN/8, x3, x1, x4) + +inst_2418: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x2; +op3val:0x7e01; valaddr_reg:x2; val_offset:7152*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7152*FLEN/8, x3, x1, x4) + +inst_2419: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x2; +op3val:0xfe55; valaddr_reg:x2; val_offset:7155*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7155*FLEN/8, x3, x1, x4) + +inst_2420: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x2; +op3val:0x7c01; valaddr_reg:x2; val_offset:7158*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7158*FLEN/8, x3, x1, x4) + +inst_2421: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x2; +op3val:0xfd55; valaddr_reg:x2; val_offset:7161*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7161*FLEN/8, x3, x1, x4) + +inst_2422: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x2; +op3val:0x3c00; valaddr_reg:x2; val_offset:7164*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7164*FLEN/8, x3, x1, x4) + +inst_2423: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x2; +op3val:0xbc00; valaddr_reg:x2; val_offset:7167*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7167*FLEN/8, x3, x1, x4) + +inst_2424: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x83fe; +op3val:0x0; valaddr_reg:x2; val_offset:7170*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7170*FLEN/8, x3, x1, x4) + +inst_2425: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x83fe; +op3val:0x8000; valaddr_reg:x2; val_offset:7173*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7173*FLEN/8, x3, x1, x4) + +inst_2426: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x83fe; +op3val:0x1; valaddr_reg:x2; val_offset:7176*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7176*FLEN/8, x3, x1, x4) + +inst_2427: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x83fe; +op3val:0x8001; valaddr_reg:x2; val_offset:7179*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7179*FLEN/8, x3, x1, x4) + +inst_2428: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x83fe; +op3val:0x2; valaddr_reg:x2; val_offset:7182*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7182*FLEN/8, x3, x1, x4) + +inst_2429: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x83fe; +op3val:0x83fe; valaddr_reg:x2; val_offset:7185*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7185*FLEN/8, x3, x1, x4) + +inst_2430: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x83fe; +op3val:0x3ff; valaddr_reg:x2; val_offset:7188*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7188*FLEN/8, x3, x1, x4) + +inst_2431: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x83fe; +op3val:0x83ff; valaddr_reg:x2; val_offset:7191*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7191*FLEN/8, x3, x1, x4) + +inst_2432: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x83fe; +op3val:0x400; valaddr_reg:x2; val_offset:7194*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7194*FLEN/8, x3, x1, x4) + +inst_2433: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x83fe; +op3val:0x8400; valaddr_reg:x2; val_offset:7197*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7197*FLEN/8, x3, x1, x4) + +inst_2434: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x83fe; +op3val:0x401; valaddr_reg:x2; val_offset:7200*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7200*FLEN/8, x3, x1, x4) + +inst_2435: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x83fe; +op3val:0x8455; valaddr_reg:x2; val_offset:7203*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7203*FLEN/8, x3, x1, x4) + +inst_2436: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x83fe; +op3val:0x7bff; valaddr_reg:x2; val_offset:7206*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7206*FLEN/8, x3, x1, x4) + +inst_2437: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x83fe; +op3val:0xfbff; valaddr_reg:x2; val_offset:7209*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7209*FLEN/8, x3, x1, x4) + +inst_2438: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x83fe; +op3val:0x7c00; valaddr_reg:x2; val_offset:7212*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7212*FLEN/8, x3, x1, x4) + +inst_2439: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x83fe; +op3val:0xfc00; valaddr_reg:x2; val_offset:7215*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7215*FLEN/8, x3, x1, x4) + +inst_2440: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x83fe; +op3val:0x7e00; valaddr_reg:x2; val_offset:7218*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7218*FLEN/8, x3, x1, x4) + +inst_2441: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x83fe; +op3val:0xfe00; valaddr_reg:x2; val_offset:7221*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7221*FLEN/8, x3, x1, x4) + +inst_2442: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x83fe; +op3val:0x7e01; valaddr_reg:x2; val_offset:7224*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7224*FLEN/8, x3, x1, x4) + +inst_2443: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x83fe; +op3val:0xfe55; valaddr_reg:x2; val_offset:7227*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7227*FLEN/8, x3, x1, x4) + +inst_2444: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x83fe; +op3val:0x7c01; valaddr_reg:x2; val_offset:7230*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7230*FLEN/8, x3, x1, x4) + +inst_2445: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x83fe; +op3val:0xfd55; valaddr_reg:x2; val_offset:7233*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7233*FLEN/8, x3, x1, x4) + +inst_2446: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x83fe; +op3val:0x3c00; valaddr_reg:x2; val_offset:7236*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7236*FLEN/8, x3, x1, x4) + +inst_2447: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x83fe; +op3val:0xbc00; valaddr_reg:x2; val_offset:7239*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7239*FLEN/8, x3, x1, x4) + +inst_2448: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3ff; +op3val:0x0; valaddr_reg:x2; val_offset:7242*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7242*FLEN/8, x3, x1, x4) + +inst_2449: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3ff; +op3val:0x8000; valaddr_reg:x2; val_offset:7245*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7245*FLEN/8, x3, x1, x4) + +inst_2450: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3ff; +op3val:0x1; valaddr_reg:x2; val_offset:7248*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7248*FLEN/8, x3, x1, x4) + +inst_2451: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3ff; +op3val:0x8001; valaddr_reg:x2; val_offset:7251*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7251*FLEN/8, x3, x1, x4) + +inst_2452: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3ff; +op3val:0x2; valaddr_reg:x2; val_offset:7254*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7254*FLEN/8, x3, x1, x4) + +inst_2453: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3ff; +op3val:0x83fe; valaddr_reg:x2; val_offset:7257*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7257*FLEN/8, x3, x1, x4) + +inst_2454: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3ff; +op3val:0x3ff; valaddr_reg:x2; val_offset:7260*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7260*FLEN/8, x3, x1, x4) + +inst_2455: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3ff; +op3val:0x83ff; valaddr_reg:x2; val_offset:7263*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7263*FLEN/8, x3, x1, x4) + +inst_2456: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3ff; +op3val:0x400; valaddr_reg:x2; val_offset:7266*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7266*FLEN/8, x3, x1, x4) + +inst_2457: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3ff; +op3val:0x8400; valaddr_reg:x2; val_offset:7269*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7269*FLEN/8, x3, x1, x4) + +inst_2458: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3ff; +op3val:0x401; valaddr_reg:x2; val_offset:7272*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7272*FLEN/8, x3, x1, x4) + +inst_2459: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3ff; +op3val:0x8455; valaddr_reg:x2; val_offset:7275*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7275*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_20) + +inst_2460: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3ff; +op3val:0x7bff; valaddr_reg:x2; val_offset:7278*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7278*FLEN/8, x3, x1, x4) + +inst_2461: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3ff; +op3val:0xfbff; valaddr_reg:x2; val_offset:7281*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7281*FLEN/8, x3, x1, x4) + +inst_2462: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3ff; +op3val:0x7c00; valaddr_reg:x2; val_offset:7284*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7284*FLEN/8, x3, x1, x4) + +inst_2463: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3ff; +op3val:0xfc00; valaddr_reg:x2; val_offset:7287*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7287*FLEN/8, x3, x1, x4) + +inst_2464: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3ff; +op3val:0x7e00; valaddr_reg:x2; val_offset:7290*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7290*FLEN/8, x3, x1, x4) + +inst_2465: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3ff; +op3val:0xfe00; valaddr_reg:x2; val_offset:7293*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7293*FLEN/8, x3, x1, x4) + +inst_2466: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3ff; +op3val:0x7e01; valaddr_reg:x2; val_offset:7296*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7296*FLEN/8, x3, x1, x4) + +inst_2467: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3ff; +op3val:0xfe55; valaddr_reg:x2; val_offset:7299*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7299*FLEN/8, x3, x1, x4) + +inst_2468: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3ff; +op3val:0x7c01; valaddr_reg:x2; val_offset:7302*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7302*FLEN/8, x3, x1, x4) + +inst_2469: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3ff; +op3val:0xfd55; valaddr_reg:x2; val_offset:7305*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7305*FLEN/8, x3, x1, x4) + +inst_2470: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3ff; +op3val:0x3c00; valaddr_reg:x2; val_offset:7308*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7308*FLEN/8, x3, x1, x4) + +inst_2471: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3ff; +op3val:0xbc00; valaddr_reg:x2; val_offset:7311*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7311*FLEN/8, x3, x1, x4) + +inst_2472: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x83ff; +op3val:0x0; valaddr_reg:x2; val_offset:7314*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7314*FLEN/8, x3, x1, x4) + +inst_2473: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x83ff; +op3val:0x8000; valaddr_reg:x2; val_offset:7317*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7317*FLEN/8, x3, x1, x4) + +inst_2474: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x83ff; +op3val:0x1; valaddr_reg:x2; val_offset:7320*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7320*FLEN/8, x3, x1, x4) + +inst_2475: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x83ff; +op3val:0x8001; valaddr_reg:x2; val_offset:7323*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7323*FLEN/8, x3, x1, x4) + +inst_2476: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x83ff; +op3val:0x2; valaddr_reg:x2; val_offset:7326*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7326*FLEN/8, x3, x1, x4) + +inst_2477: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x83ff; +op3val:0x83fe; valaddr_reg:x2; val_offset:7329*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7329*FLEN/8, x3, x1, x4) + +inst_2478: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x83ff; +op3val:0x3ff; valaddr_reg:x2; val_offset:7332*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7332*FLEN/8, x3, x1, x4) + +inst_2479: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x83ff; +op3val:0x83ff; valaddr_reg:x2; val_offset:7335*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7335*FLEN/8, x3, x1, x4) + +inst_2480: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x83ff; +op3val:0x400; valaddr_reg:x2; val_offset:7338*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7338*FLEN/8, x3, x1, x4) + +inst_2481: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x83ff; +op3val:0x8400; valaddr_reg:x2; val_offset:7341*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7341*FLEN/8, x3, x1, x4) + +inst_2482: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x83ff; +op3val:0x401; valaddr_reg:x2; val_offset:7344*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7344*FLEN/8, x3, x1, x4) + +inst_2483: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x83ff; +op3val:0x8455; valaddr_reg:x2; val_offset:7347*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7347*FLEN/8, x3, x1, x4) + +inst_2484: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x83ff; +op3val:0x7bff; valaddr_reg:x2; val_offset:7350*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7350*FLEN/8, x3, x1, x4) + +inst_2485: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x83ff; +op3val:0xfbff; valaddr_reg:x2; val_offset:7353*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7353*FLEN/8, x3, x1, x4) + +inst_2486: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x83ff; +op3val:0x7c00; valaddr_reg:x2; val_offset:7356*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7356*FLEN/8, x3, x1, x4) + +inst_2487: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x83ff; +op3val:0xfc00; valaddr_reg:x2; val_offset:7359*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7359*FLEN/8, x3, x1, x4) + +inst_2488: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x83ff; +op3val:0x7e00; valaddr_reg:x2; val_offset:7362*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7362*FLEN/8, x3, x1, x4) + +inst_2489: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x83ff; +op3val:0xfe00; valaddr_reg:x2; val_offset:7365*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7365*FLEN/8, x3, x1, x4) + +inst_2490: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x83ff; +op3val:0x7e01; valaddr_reg:x2; val_offset:7368*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7368*FLEN/8, x3, x1, x4) + +inst_2491: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x83ff; +op3val:0xfe55; valaddr_reg:x2; val_offset:7371*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7371*FLEN/8, x3, x1, x4) + +inst_2492: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x83ff; +op3val:0x7c01; valaddr_reg:x2; val_offset:7374*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7374*FLEN/8, x3, x1, x4) + +inst_2493: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x83ff; +op3val:0xfd55; valaddr_reg:x2; val_offset:7377*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7377*FLEN/8, x3, x1, x4) + +inst_2494: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x83ff; +op3val:0x3c00; valaddr_reg:x2; val_offset:7380*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7380*FLEN/8, x3, x1, x4) + +inst_2495: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x83ff; +op3val:0xbc00; valaddr_reg:x2; val_offset:7383*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7383*FLEN/8, x3, x1, x4) + +inst_2496: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x400; +op3val:0x0; valaddr_reg:x2; val_offset:7386*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7386*FLEN/8, x3, x1, x4) + +inst_2497: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x400; +op3val:0x8000; valaddr_reg:x2; val_offset:7389*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7389*FLEN/8, x3, x1, x4) + +inst_2498: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x400; +op3val:0x1; valaddr_reg:x2; val_offset:7392*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7392*FLEN/8, x3, x1, x4) + +inst_2499: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x400; +op3val:0x8001; valaddr_reg:x2; val_offset:7395*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7395*FLEN/8, x3, x1, x4) + +inst_2500: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x400; +op3val:0x2; valaddr_reg:x2; val_offset:7398*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7398*FLEN/8, x3, x1, x4) + +inst_2501: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x400; +op3val:0x83fe; valaddr_reg:x2; val_offset:7401*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7401*FLEN/8, x3, x1, x4) + +inst_2502: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x400; +op3val:0x3ff; valaddr_reg:x2; val_offset:7404*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7404*FLEN/8, x3, x1, x4) + +inst_2503: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x400; +op3val:0x83ff; valaddr_reg:x2; val_offset:7407*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7407*FLEN/8, x3, x1, x4) + +inst_2504: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x400; +op3val:0x400; valaddr_reg:x2; val_offset:7410*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7410*FLEN/8, x3, x1, x4) + +inst_2505: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x400; +op3val:0x8400; valaddr_reg:x2; val_offset:7413*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7413*FLEN/8, x3, x1, x4) + +inst_2506: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x400; +op3val:0x401; valaddr_reg:x2; val_offset:7416*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7416*FLEN/8, x3, x1, x4) + +inst_2507: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x400; +op3val:0x8455; valaddr_reg:x2; val_offset:7419*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7419*FLEN/8, x3, x1, x4) + +inst_2508: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x400; +op3val:0x7bff; valaddr_reg:x2; val_offset:7422*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7422*FLEN/8, x3, x1, x4) + +inst_2509: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x400; +op3val:0xfbff; valaddr_reg:x2; val_offset:7425*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7425*FLEN/8, x3, x1, x4) + +inst_2510: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x400; +op3val:0x7c00; valaddr_reg:x2; val_offset:7428*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7428*FLEN/8, x3, x1, x4) + +inst_2511: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x400; +op3val:0xfc00; valaddr_reg:x2; val_offset:7431*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7431*FLEN/8, x3, x1, x4) + +inst_2512: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x400; +op3val:0x7e00; valaddr_reg:x2; val_offset:7434*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7434*FLEN/8, x3, x1, x4) + +inst_2513: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x400; +op3val:0xfe00; valaddr_reg:x2; val_offset:7437*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7437*FLEN/8, x3, x1, x4) + +inst_2514: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x400; +op3val:0x7e01; valaddr_reg:x2; val_offset:7440*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7440*FLEN/8, x3, x1, x4) + +inst_2515: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x400; +op3val:0xfe55; valaddr_reg:x2; val_offset:7443*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7443*FLEN/8, x3, x1, x4) + +inst_2516: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x400; +op3val:0x7c01; valaddr_reg:x2; val_offset:7446*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7446*FLEN/8, x3, x1, x4) + +inst_2517: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x400; +op3val:0xfd55; valaddr_reg:x2; val_offset:7449*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7449*FLEN/8, x3, x1, x4) + +inst_2518: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x400; +op3val:0x3c00; valaddr_reg:x2; val_offset:7452*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7452*FLEN/8, x3, x1, x4) + +inst_2519: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x400; +op3val:0xbc00; valaddr_reg:x2; val_offset:7455*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7455*FLEN/8, x3, x1, x4) + +inst_2520: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8400; +op3val:0x0; valaddr_reg:x2; val_offset:7458*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7458*FLEN/8, x3, x1, x4) + +inst_2521: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8400; +op3val:0x8000; valaddr_reg:x2; val_offset:7461*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7461*FLEN/8, x3, x1, x4) + +inst_2522: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8400; +op3val:0x1; valaddr_reg:x2; val_offset:7464*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7464*FLEN/8, x3, x1, x4) + +inst_2523: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8400; +op3val:0x8001; valaddr_reg:x2; val_offset:7467*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7467*FLEN/8, x3, x1, x4) + +inst_2524: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8400; +op3val:0x2; valaddr_reg:x2; val_offset:7470*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7470*FLEN/8, x3, x1, x4) + +inst_2525: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8400; +op3val:0x83fe; valaddr_reg:x2; val_offset:7473*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7473*FLEN/8, x3, x1, x4) + +inst_2526: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8400; +op3val:0x3ff; valaddr_reg:x2; val_offset:7476*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7476*FLEN/8, x3, x1, x4) + +inst_2527: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8400; +op3val:0x83ff; valaddr_reg:x2; val_offset:7479*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7479*FLEN/8, x3, x1, x4) + +inst_2528: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8400; +op3val:0x400; valaddr_reg:x2; val_offset:7482*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7482*FLEN/8, x3, x1, x4) + +inst_2529: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8400; +op3val:0x8400; valaddr_reg:x2; val_offset:7485*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7485*FLEN/8, x3, x1, x4) + +inst_2530: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8400; +op3val:0x401; valaddr_reg:x2; val_offset:7488*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7488*FLEN/8, x3, x1, x4) + +inst_2531: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8400; +op3val:0x8455; valaddr_reg:x2; val_offset:7491*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7491*FLEN/8, x3, x1, x4) + +inst_2532: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8400; +op3val:0x7bff; valaddr_reg:x2; val_offset:7494*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7494*FLEN/8, x3, x1, x4) + +inst_2533: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8400; +op3val:0xfbff; valaddr_reg:x2; val_offset:7497*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7497*FLEN/8, x3, x1, x4) + +inst_2534: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8400; +op3val:0x7c00; valaddr_reg:x2; val_offset:7500*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7500*FLEN/8, x3, x1, x4) + +inst_2535: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8400; +op3val:0xfc00; valaddr_reg:x2; val_offset:7503*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7503*FLEN/8, x3, x1, x4) + +inst_2536: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8400; +op3val:0x7e00; valaddr_reg:x2; val_offset:7506*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7506*FLEN/8, x3, x1, x4) + +inst_2537: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8400; +op3val:0xfe00; valaddr_reg:x2; val_offset:7509*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7509*FLEN/8, x3, x1, x4) + +inst_2538: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8400; +op3val:0x7e01; valaddr_reg:x2; val_offset:7512*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7512*FLEN/8, x3, x1, x4) + +inst_2539: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8400; +op3val:0xfe55; valaddr_reg:x2; val_offset:7515*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7515*FLEN/8, x3, x1, x4) + +inst_2540: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8400; +op3val:0x7c01; valaddr_reg:x2; val_offset:7518*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7518*FLEN/8, x3, x1, x4) + +inst_2541: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8400; +op3val:0xfd55; valaddr_reg:x2; val_offset:7521*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7521*FLEN/8, x3, x1, x4) + +inst_2542: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8400; +op3val:0x3c00; valaddr_reg:x2; val_offset:7524*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7524*FLEN/8, x3, x1, x4) + +inst_2543: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8400; +op3val:0xbc00; valaddr_reg:x2; val_offset:7527*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7527*FLEN/8, x3, x1, x4) + +inst_2544: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x401; +op3val:0x0; valaddr_reg:x2; val_offset:7530*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7530*FLEN/8, x3, x1, x4) + +inst_2545: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x401; +op3val:0x8000; valaddr_reg:x2; val_offset:7533*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7533*FLEN/8, x3, x1, x4) + +inst_2546: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x401; +op3val:0x1; valaddr_reg:x2; val_offset:7536*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7536*FLEN/8, x3, x1, x4) + +inst_2547: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x401; +op3val:0x8001; valaddr_reg:x2; val_offset:7539*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7539*FLEN/8, x3, x1, x4) + +inst_2548: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x401; +op3val:0x2; valaddr_reg:x2; val_offset:7542*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7542*FLEN/8, x3, x1, x4) + +inst_2549: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x401; +op3val:0x83fe; valaddr_reg:x2; val_offset:7545*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7545*FLEN/8, x3, x1, x4) + +inst_2550: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x401; +op3val:0x3ff; valaddr_reg:x2; val_offset:7548*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7548*FLEN/8, x3, x1, x4) + +inst_2551: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x401; +op3val:0x83ff; valaddr_reg:x2; val_offset:7551*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7551*FLEN/8, x3, x1, x4) + +inst_2552: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x401; +op3val:0x400; valaddr_reg:x2; val_offset:7554*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7554*FLEN/8, x3, x1, x4) + +inst_2553: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x401; +op3val:0x8400; valaddr_reg:x2; val_offset:7557*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7557*FLEN/8, x3, x1, x4) + +inst_2554: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x401; +op3val:0x401; valaddr_reg:x2; val_offset:7560*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7560*FLEN/8, x3, x1, x4) + +inst_2555: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x401; +op3val:0x8455; valaddr_reg:x2; val_offset:7563*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7563*FLEN/8, x3, x1, x4) + +inst_2556: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x401; +op3val:0x7bff; valaddr_reg:x2; val_offset:7566*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7566*FLEN/8, x3, x1, x4) + +inst_2557: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x401; +op3val:0xfbff; valaddr_reg:x2; val_offset:7569*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7569*FLEN/8, x3, x1, x4) + +inst_2558: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x401; +op3val:0x7c00; valaddr_reg:x2; val_offset:7572*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7572*FLEN/8, x3, x1, x4) + +inst_2559: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x401; +op3val:0xfc00; valaddr_reg:x2; val_offset:7575*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7575*FLEN/8, x3, x1, x4) + +inst_2560: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x401; +op3val:0x7e00; valaddr_reg:x2; val_offset:7578*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7578*FLEN/8, x3, x1, x4) + +inst_2561: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x401; +op3val:0xfe00; valaddr_reg:x2; val_offset:7581*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7581*FLEN/8, x3, x1, x4) + +inst_2562: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x401; +op3val:0x7e01; valaddr_reg:x2; val_offset:7584*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7584*FLEN/8, x3, x1, x4) + +inst_2563: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x401; +op3val:0xfe55; valaddr_reg:x2; val_offset:7587*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7587*FLEN/8, x3, x1, x4) + +inst_2564: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x401; +op3val:0x7c01; valaddr_reg:x2; val_offset:7590*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7590*FLEN/8, x3, x1, x4) + +inst_2565: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x401; +op3val:0xfd55; valaddr_reg:x2; val_offset:7593*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7593*FLEN/8, x3, x1, x4) + +inst_2566: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x401; +op3val:0x3c00; valaddr_reg:x2; val_offset:7596*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7596*FLEN/8, x3, x1, x4) + +inst_2567: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x401; +op3val:0xbc00; valaddr_reg:x2; val_offset:7599*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7599*FLEN/8, x3, x1, x4) + +inst_2568: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8455; +op3val:0x0; valaddr_reg:x2; val_offset:7602*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7602*FLEN/8, x3, x1, x4) + +inst_2569: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8455; +op3val:0x8000; valaddr_reg:x2; val_offset:7605*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7605*FLEN/8, x3, x1, x4) + +inst_2570: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8455; +op3val:0x1; valaddr_reg:x2; val_offset:7608*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7608*FLEN/8, x3, x1, x4) + +inst_2571: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8455; +op3val:0x8001; valaddr_reg:x2; val_offset:7611*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7611*FLEN/8, x3, x1, x4) + +inst_2572: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8455; +op3val:0x2; valaddr_reg:x2; val_offset:7614*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7614*FLEN/8, x3, x1, x4) + +inst_2573: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8455; +op3val:0x83fe; valaddr_reg:x2; val_offset:7617*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7617*FLEN/8, x3, x1, x4) + +inst_2574: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8455; +op3val:0x3ff; valaddr_reg:x2; val_offset:7620*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7620*FLEN/8, x3, x1, x4) + +inst_2575: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8455; +op3val:0x83ff; valaddr_reg:x2; val_offset:7623*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7623*FLEN/8, x3, x1, x4) + +inst_2576: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8455; +op3val:0x400; valaddr_reg:x2; val_offset:7626*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7626*FLEN/8, x3, x1, x4) + +inst_2577: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8455; +op3val:0x8400; valaddr_reg:x2; val_offset:7629*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7629*FLEN/8, x3, x1, x4) + +inst_2578: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8455; +op3val:0x401; valaddr_reg:x2; val_offset:7632*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7632*FLEN/8, x3, x1, x4) + +inst_2579: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8455; +op3val:0x8455; valaddr_reg:x2; val_offset:7635*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7635*FLEN/8, x3, x1, x4) + +inst_2580: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8455; +op3val:0x7bff; valaddr_reg:x2; val_offset:7638*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7638*FLEN/8, x3, x1, x4) + +inst_2581: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8455; +op3val:0xfbff; valaddr_reg:x2; val_offset:7641*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7641*FLEN/8, x3, x1, x4) + +inst_2582: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8455; +op3val:0x7c00; valaddr_reg:x2; val_offset:7644*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7644*FLEN/8, x3, x1, x4) + +inst_2583: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8455; +op3val:0xfc00; valaddr_reg:x2; val_offset:7647*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7647*FLEN/8, x3, x1, x4) + +inst_2584: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8455; +op3val:0x7e00; valaddr_reg:x2; val_offset:7650*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7650*FLEN/8, x3, x1, x4) + +inst_2585: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8455; +op3val:0xfe00; valaddr_reg:x2; val_offset:7653*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7653*FLEN/8, x3, x1, x4) + +inst_2586: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8455; +op3val:0x7e01; valaddr_reg:x2; val_offset:7656*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7656*FLEN/8, x3, x1, x4) + +inst_2587: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8455; +op3val:0xfe55; valaddr_reg:x2; val_offset:7659*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7659*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_21) + +inst_2588: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8455; +op3val:0x7c01; valaddr_reg:x2; val_offset:7662*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7662*FLEN/8, x3, x1, x4) + +inst_2589: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8455; +op3val:0xfd55; valaddr_reg:x2; val_offset:7665*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7665*FLEN/8, x3, x1, x4) + +inst_2590: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8455; +op3val:0x3c00; valaddr_reg:x2; val_offset:7668*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7668*FLEN/8, x3, x1, x4) + +inst_2591: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x8455; +op3val:0xbc00; valaddr_reg:x2; val_offset:7671*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7671*FLEN/8, x3, x1, x4) + +inst_2592: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7bff; +op3val:0x0; valaddr_reg:x2; val_offset:7674*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7674*FLEN/8, x3, x1, x4) + +inst_2593: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7bff; +op3val:0x8000; valaddr_reg:x2; val_offset:7677*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7677*FLEN/8, x3, x1, x4) + +inst_2594: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7bff; +op3val:0x1; valaddr_reg:x2; val_offset:7680*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7680*FLEN/8, x3, x1, x4) + +inst_2595: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7bff; +op3val:0x8001; valaddr_reg:x2; val_offset:7683*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7683*FLEN/8, x3, x1, x4) + +inst_2596: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7bff; +op3val:0x2; valaddr_reg:x2; val_offset:7686*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7686*FLEN/8, x3, x1, x4) + +inst_2597: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7bff; +op3val:0x83fe; valaddr_reg:x2; val_offset:7689*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7689*FLEN/8, x3, x1, x4) + +inst_2598: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7bff; +op3val:0x3ff; valaddr_reg:x2; val_offset:7692*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7692*FLEN/8, x3, x1, x4) + +inst_2599: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7bff; +op3val:0x83ff; valaddr_reg:x2; val_offset:7695*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7695*FLEN/8, x3, x1, x4) + +inst_2600: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7bff; +op3val:0x400; valaddr_reg:x2; val_offset:7698*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7698*FLEN/8, x3, x1, x4) + +inst_2601: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7bff; +op3val:0x8400; valaddr_reg:x2; val_offset:7701*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7701*FLEN/8, x3, x1, x4) + +inst_2602: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7bff; +op3val:0x401; valaddr_reg:x2; val_offset:7704*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7704*FLEN/8, x3, x1, x4) + +inst_2603: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7bff; +op3val:0x8455; valaddr_reg:x2; val_offset:7707*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7707*FLEN/8, x3, x1, x4) + +inst_2604: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7bff; +op3val:0x7bff; valaddr_reg:x2; val_offset:7710*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7710*FLEN/8, x3, x1, x4) + +inst_2605: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7bff; +op3val:0xfbff; valaddr_reg:x2; val_offset:7713*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7713*FLEN/8, x3, x1, x4) + +inst_2606: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7bff; +op3val:0x7c00; valaddr_reg:x2; val_offset:7716*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7716*FLEN/8, x3, x1, x4) + +inst_2607: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7bff; +op3val:0xfc00; valaddr_reg:x2; val_offset:7719*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7719*FLEN/8, x3, x1, x4) + +inst_2608: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7bff; +op3val:0x7e00; valaddr_reg:x2; val_offset:7722*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7722*FLEN/8, x3, x1, x4) + +inst_2609: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7bff; +op3val:0xfe00; valaddr_reg:x2; val_offset:7725*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7725*FLEN/8, x3, x1, x4) + +inst_2610: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7bff; +op3val:0x7e01; valaddr_reg:x2; val_offset:7728*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7728*FLEN/8, x3, x1, x4) + +inst_2611: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7bff; +op3val:0xfe55; valaddr_reg:x2; val_offset:7731*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7731*FLEN/8, x3, x1, x4) + +inst_2612: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7bff; +op3val:0x7c01; valaddr_reg:x2; val_offset:7734*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7734*FLEN/8, x3, x1, x4) + +inst_2613: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7bff; +op3val:0xfd55; valaddr_reg:x2; val_offset:7737*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7737*FLEN/8, x3, x1, x4) + +inst_2614: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7bff; +op3val:0x3c00; valaddr_reg:x2; val_offset:7740*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7740*FLEN/8, x3, x1, x4) + +inst_2615: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7bff; +op3val:0xbc00; valaddr_reg:x2; val_offset:7743*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7743*FLEN/8, x3, x1, x4) + +inst_2616: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfbff; +op3val:0x0; valaddr_reg:x2; val_offset:7746*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7746*FLEN/8, x3, x1, x4) + +inst_2617: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfbff; +op3val:0x8000; valaddr_reg:x2; val_offset:7749*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7749*FLEN/8, x3, x1, x4) + +inst_2618: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfbff; +op3val:0x1; valaddr_reg:x2; val_offset:7752*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7752*FLEN/8, x3, x1, x4) + +inst_2619: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfbff; +op3val:0x8001; valaddr_reg:x2; val_offset:7755*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7755*FLEN/8, x3, x1, x4) + +inst_2620: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfbff; +op3val:0x2; valaddr_reg:x2; val_offset:7758*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7758*FLEN/8, x3, x1, x4) + +inst_2621: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfbff; +op3val:0x83fe; valaddr_reg:x2; val_offset:7761*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7761*FLEN/8, x3, x1, x4) + +inst_2622: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfbff; +op3val:0x3ff; valaddr_reg:x2; val_offset:7764*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7764*FLEN/8, x3, x1, x4) + +inst_2623: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfbff; +op3val:0x83ff; valaddr_reg:x2; val_offset:7767*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7767*FLEN/8, x3, x1, x4) + +inst_2624: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfbff; +op3val:0x400; valaddr_reg:x2; val_offset:7770*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7770*FLEN/8, x3, x1, x4) + +inst_2625: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfbff; +op3val:0x8400; valaddr_reg:x2; val_offset:7773*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7773*FLEN/8, x3, x1, x4) + +inst_2626: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfbff; +op3val:0x401; valaddr_reg:x2; val_offset:7776*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7776*FLEN/8, x3, x1, x4) + +inst_2627: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfbff; +op3val:0x8455; valaddr_reg:x2; val_offset:7779*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7779*FLEN/8, x3, x1, x4) + +inst_2628: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfbff; +op3val:0x7bff; valaddr_reg:x2; val_offset:7782*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7782*FLEN/8, x3, x1, x4) + +inst_2629: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfbff; +op3val:0xfbff; valaddr_reg:x2; val_offset:7785*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7785*FLEN/8, x3, x1, x4) + +inst_2630: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfbff; +op3val:0x7c00; valaddr_reg:x2; val_offset:7788*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7788*FLEN/8, x3, x1, x4) + +inst_2631: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfbff; +op3val:0xfc00; valaddr_reg:x2; val_offset:7791*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7791*FLEN/8, x3, x1, x4) + +inst_2632: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfbff; +op3val:0x7e00; valaddr_reg:x2; val_offset:7794*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7794*FLEN/8, x3, x1, x4) + +inst_2633: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfbff; +op3val:0xfe00; valaddr_reg:x2; val_offset:7797*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7797*FLEN/8, x3, x1, x4) + +inst_2634: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfbff; +op3val:0x7e01; valaddr_reg:x2; val_offset:7800*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7800*FLEN/8, x3, x1, x4) + +inst_2635: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfbff; +op3val:0xfe55; valaddr_reg:x2; val_offset:7803*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7803*FLEN/8, x3, x1, x4) + +inst_2636: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfbff; +op3val:0x7c01; valaddr_reg:x2; val_offset:7806*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7806*FLEN/8, x3, x1, x4) + +inst_2637: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfbff; +op3val:0xfd55; valaddr_reg:x2; val_offset:7809*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7809*FLEN/8, x3, x1, x4) + +inst_2638: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfbff; +op3val:0x3c00; valaddr_reg:x2; val_offset:7812*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7812*FLEN/8, x3, x1, x4) + +inst_2639: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfbff; +op3val:0xbc00; valaddr_reg:x2; val_offset:7815*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7815*FLEN/8, x3, x1, x4) + +inst_2640: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7c00; +op3val:0x0; valaddr_reg:x2; val_offset:7818*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7818*FLEN/8, x3, x1, x4) + +inst_2641: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7c00; +op3val:0x8000; valaddr_reg:x2; val_offset:7821*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7821*FLEN/8, x3, x1, x4) + +inst_2642: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7c00; +op3val:0x1; valaddr_reg:x2; val_offset:7824*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7824*FLEN/8, x3, x1, x4) + +inst_2643: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7c00; +op3val:0x8001; valaddr_reg:x2; val_offset:7827*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7827*FLEN/8, x3, x1, x4) + +inst_2644: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7c00; +op3val:0x2; valaddr_reg:x2; val_offset:7830*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7830*FLEN/8, x3, x1, x4) + +inst_2645: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7c00; +op3val:0x83fe; valaddr_reg:x2; val_offset:7833*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7833*FLEN/8, x3, x1, x4) + +inst_2646: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7c00; +op3val:0x3ff; valaddr_reg:x2; val_offset:7836*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7836*FLEN/8, x3, x1, x4) + +inst_2647: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7c00; +op3val:0x83ff; valaddr_reg:x2; val_offset:7839*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7839*FLEN/8, x3, x1, x4) + +inst_2648: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7c00; +op3val:0x400; valaddr_reg:x2; val_offset:7842*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7842*FLEN/8, x3, x1, x4) + +inst_2649: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7c00; +op3val:0x8400; valaddr_reg:x2; val_offset:7845*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7845*FLEN/8, x3, x1, x4) + +inst_2650: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7c00; +op3val:0x401; valaddr_reg:x2; val_offset:7848*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7848*FLEN/8, x3, x1, x4) + +inst_2651: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7c00; +op3val:0x8455; valaddr_reg:x2; val_offset:7851*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7851*FLEN/8, x3, x1, x4) + +inst_2652: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7c00; +op3val:0x7bff; valaddr_reg:x2; val_offset:7854*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7854*FLEN/8, x3, x1, x4) + +inst_2653: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7c00; +op3val:0xfbff; valaddr_reg:x2; val_offset:7857*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7857*FLEN/8, x3, x1, x4) + +inst_2654: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7c00; +op3val:0x7c00; valaddr_reg:x2; val_offset:7860*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7860*FLEN/8, x3, x1, x4) + +inst_2655: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7c00; +op3val:0xfc00; valaddr_reg:x2; val_offset:7863*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7863*FLEN/8, x3, x1, x4) + +inst_2656: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7c00; +op3val:0x7e00; valaddr_reg:x2; val_offset:7866*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7866*FLEN/8, x3, x1, x4) + +inst_2657: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7c00; +op3val:0xfe00; valaddr_reg:x2; val_offset:7869*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7869*FLEN/8, x3, x1, x4) + +inst_2658: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7c00; +op3val:0x7e01; valaddr_reg:x2; val_offset:7872*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7872*FLEN/8, x3, x1, x4) + +inst_2659: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7c00; +op3val:0xfe55; valaddr_reg:x2; val_offset:7875*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7875*FLEN/8, x3, x1, x4) + +inst_2660: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7c00; +op3val:0x7c01; valaddr_reg:x2; val_offset:7878*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7878*FLEN/8, x3, x1, x4) + +inst_2661: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7c00; +op3val:0xfd55; valaddr_reg:x2; val_offset:7881*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7881*FLEN/8, x3, x1, x4) + +inst_2662: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7c00; +op3val:0x3c00; valaddr_reg:x2; val_offset:7884*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7884*FLEN/8, x3, x1, x4) + +inst_2663: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7c00; +op3val:0xbc00; valaddr_reg:x2; val_offset:7887*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7887*FLEN/8, x3, x1, x4) + +inst_2664: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfc00; +op3val:0x0; valaddr_reg:x2; val_offset:7890*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7890*FLEN/8, x3, x1, x4) + +inst_2665: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfc00; +op3val:0x8000; valaddr_reg:x2; val_offset:7893*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7893*FLEN/8, x3, x1, x4) + +inst_2666: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfc00; +op3val:0x1; valaddr_reg:x2; val_offset:7896*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7896*FLEN/8, x3, x1, x4) + +inst_2667: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfc00; +op3val:0x8001; valaddr_reg:x2; val_offset:7899*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7899*FLEN/8, x3, x1, x4) + +inst_2668: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfc00; +op3val:0x2; valaddr_reg:x2; val_offset:7902*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7902*FLEN/8, x3, x1, x4) + +inst_2669: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfc00; +op3val:0x83fe; valaddr_reg:x2; val_offset:7905*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7905*FLEN/8, x3, x1, x4) + +inst_2670: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfc00; +op3val:0x3ff; valaddr_reg:x2; val_offset:7908*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7908*FLEN/8, x3, x1, x4) + +inst_2671: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfc00; +op3val:0x83ff; valaddr_reg:x2; val_offset:7911*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7911*FLEN/8, x3, x1, x4) + +inst_2672: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfc00; +op3val:0x400; valaddr_reg:x2; val_offset:7914*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7914*FLEN/8, x3, x1, x4) + +inst_2673: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfc00; +op3val:0x8400; valaddr_reg:x2; val_offset:7917*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7917*FLEN/8, x3, x1, x4) + +inst_2674: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfc00; +op3val:0x401; valaddr_reg:x2; val_offset:7920*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7920*FLEN/8, x3, x1, x4) + +inst_2675: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfc00; +op3val:0x8455; valaddr_reg:x2; val_offset:7923*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7923*FLEN/8, x3, x1, x4) + +inst_2676: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfc00; +op3val:0x7bff; valaddr_reg:x2; val_offset:7926*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7926*FLEN/8, x3, x1, x4) + +inst_2677: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfc00; +op3val:0xfbff; valaddr_reg:x2; val_offset:7929*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7929*FLEN/8, x3, x1, x4) + +inst_2678: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfc00; +op3val:0x7c00; valaddr_reg:x2; val_offset:7932*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7932*FLEN/8, x3, x1, x4) + +inst_2679: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfc00; +op3val:0xfc00; valaddr_reg:x2; val_offset:7935*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7935*FLEN/8, x3, x1, x4) + +inst_2680: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfc00; +op3val:0x7e00; valaddr_reg:x2; val_offset:7938*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7938*FLEN/8, x3, x1, x4) + +inst_2681: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfc00; +op3val:0xfe00; valaddr_reg:x2; val_offset:7941*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7941*FLEN/8, x3, x1, x4) + +inst_2682: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfc00; +op3val:0x7e01; valaddr_reg:x2; val_offset:7944*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7944*FLEN/8, x3, x1, x4) + +inst_2683: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfc00; +op3val:0xfe55; valaddr_reg:x2; val_offset:7947*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7947*FLEN/8, x3, x1, x4) + +inst_2684: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfc00; +op3val:0x7c01; valaddr_reg:x2; val_offset:7950*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7950*FLEN/8, x3, x1, x4) + +inst_2685: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfc00; +op3val:0xfd55; valaddr_reg:x2; val_offset:7953*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7953*FLEN/8, x3, x1, x4) + +inst_2686: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfc00; +op3val:0x3c00; valaddr_reg:x2; val_offset:7956*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7956*FLEN/8, x3, x1, x4) + +inst_2687: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfc00; +op3val:0xbc00; valaddr_reg:x2; val_offset:7959*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7959*FLEN/8, x3, x1, x4) + +inst_2688: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7e00; +op3val:0x0; valaddr_reg:x2; val_offset:7962*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7962*FLEN/8, x3, x1, x4) + +inst_2689: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7e00; +op3val:0x8000; valaddr_reg:x2; val_offset:7965*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7965*FLEN/8, x3, x1, x4) + +inst_2690: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7e00; +op3val:0x1; valaddr_reg:x2; val_offset:7968*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7968*FLEN/8, x3, x1, x4) + +inst_2691: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7e00; +op3val:0x8001; valaddr_reg:x2; val_offset:7971*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7971*FLEN/8, x3, x1, x4) + +inst_2692: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7e00; +op3val:0x2; valaddr_reg:x2; val_offset:7974*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7974*FLEN/8, x3, x1, x4) + +inst_2693: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7e00; +op3val:0x83fe; valaddr_reg:x2; val_offset:7977*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7977*FLEN/8, x3, x1, x4) + +inst_2694: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7e00; +op3val:0x3ff; valaddr_reg:x2; val_offset:7980*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7980*FLEN/8, x3, x1, x4) + +inst_2695: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7e00; +op3val:0x83ff; valaddr_reg:x2; val_offset:7983*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7983*FLEN/8, x3, x1, x4) + +inst_2696: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7e00; +op3val:0x400; valaddr_reg:x2; val_offset:7986*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7986*FLEN/8, x3, x1, x4) + +inst_2697: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7e00; +op3val:0x8400; valaddr_reg:x2; val_offset:7989*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7989*FLEN/8, x3, x1, x4) + +inst_2698: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7e00; +op3val:0x401; valaddr_reg:x2; val_offset:7992*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7992*FLEN/8, x3, x1, x4) + +inst_2699: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7e00; +op3val:0x8455; valaddr_reg:x2; val_offset:7995*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7995*FLEN/8, x3, x1, x4) + +inst_2700: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7e00; +op3val:0x7bff; valaddr_reg:x2; val_offset:7998*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 7998*FLEN/8, x3, x1, x4) + +inst_2701: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7e00; +op3val:0xfbff; valaddr_reg:x2; val_offset:8001*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8001*FLEN/8, x3, x1, x4) + +inst_2702: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7e00; +op3val:0x7c00; valaddr_reg:x2; val_offset:8004*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8004*FLEN/8, x3, x1, x4) + +inst_2703: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7e00; +op3val:0xfc00; valaddr_reg:x2; val_offset:8007*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8007*FLEN/8, x3, x1, x4) + +inst_2704: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7e00; +op3val:0x7e00; valaddr_reg:x2; val_offset:8010*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8010*FLEN/8, x3, x1, x4) + +inst_2705: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7e00; +op3val:0xfe00; valaddr_reg:x2; val_offset:8013*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8013*FLEN/8, x3, x1, x4) + +inst_2706: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7e00; +op3val:0x7e01; valaddr_reg:x2; val_offset:8016*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8016*FLEN/8, x3, x1, x4) + +inst_2707: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7e00; +op3val:0xfe55; valaddr_reg:x2; val_offset:8019*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8019*FLEN/8, x3, x1, x4) + +inst_2708: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7e00; +op3val:0x7c01; valaddr_reg:x2; val_offset:8022*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8022*FLEN/8, x3, x1, x4) + +inst_2709: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7e00; +op3val:0xfd55; valaddr_reg:x2; val_offset:8025*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8025*FLEN/8, x3, x1, x4) + +inst_2710: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7e00; +op3val:0x3c00; valaddr_reg:x2; val_offset:8028*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8028*FLEN/8, x3, x1, x4) + +inst_2711: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7e00; +op3val:0xbc00; valaddr_reg:x2; val_offset:8031*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8031*FLEN/8, x3, x1, x4) + +inst_2712: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfe00; +op3val:0x0; valaddr_reg:x2; val_offset:8034*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8034*FLEN/8, x3, x1, x4) + +inst_2713: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfe00; +op3val:0x8000; valaddr_reg:x2; val_offset:8037*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8037*FLEN/8, x3, x1, x4) + +inst_2714: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfe00; +op3val:0x1; valaddr_reg:x2; val_offset:8040*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8040*FLEN/8, x3, x1, x4) + +inst_2715: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfe00; +op3val:0x8001; valaddr_reg:x2; val_offset:8043*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8043*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_22) + +inst_2716: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfe00; +op3val:0x2; valaddr_reg:x2; val_offset:8046*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8046*FLEN/8, x3, x1, x4) + +inst_2717: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfe00; +op3val:0x83fe; valaddr_reg:x2; val_offset:8049*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8049*FLEN/8, x3, x1, x4) + +inst_2718: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfe00; +op3val:0x3ff; valaddr_reg:x2; val_offset:8052*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8052*FLEN/8, x3, x1, x4) + +inst_2719: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfe00; +op3val:0x83ff; valaddr_reg:x2; val_offset:8055*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8055*FLEN/8, x3, x1, x4) + +inst_2720: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfe00; +op3val:0x400; valaddr_reg:x2; val_offset:8058*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8058*FLEN/8, x3, x1, x4) + +inst_2721: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfe00; +op3val:0x8400; valaddr_reg:x2; val_offset:8061*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8061*FLEN/8, x3, x1, x4) + +inst_2722: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfe00; +op3val:0x401; valaddr_reg:x2; val_offset:8064*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8064*FLEN/8, x3, x1, x4) + +inst_2723: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfe00; +op3val:0x8455; valaddr_reg:x2; val_offset:8067*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8067*FLEN/8, x3, x1, x4) + +inst_2724: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfe00; +op3val:0x7bff; valaddr_reg:x2; val_offset:8070*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8070*FLEN/8, x3, x1, x4) + +inst_2725: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfe00; +op3val:0xfbff; valaddr_reg:x2; val_offset:8073*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8073*FLEN/8, x3, x1, x4) + +inst_2726: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfe00; +op3val:0x7c00; valaddr_reg:x2; val_offset:8076*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8076*FLEN/8, x3, x1, x4) + +inst_2727: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfe00; +op3val:0xfc00; valaddr_reg:x2; val_offset:8079*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8079*FLEN/8, x3, x1, x4) + +inst_2728: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfe00; +op3val:0x7e00; valaddr_reg:x2; val_offset:8082*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8082*FLEN/8, x3, x1, x4) + +inst_2729: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfe00; +op3val:0xfe00; valaddr_reg:x2; val_offset:8085*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8085*FLEN/8, x3, x1, x4) + +inst_2730: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfe00; +op3val:0x7e01; valaddr_reg:x2; val_offset:8088*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8088*FLEN/8, x3, x1, x4) + +inst_2731: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfe00; +op3val:0xfe55; valaddr_reg:x2; val_offset:8091*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8091*FLEN/8, x3, x1, x4) + +inst_2732: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfe00; +op3val:0x7c01; valaddr_reg:x2; val_offset:8094*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8094*FLEN/8, x3, x1, x4) + +inst_2733: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfe00; +op3val:0xfd55; valaddr_reg:x2; val_offset:8097*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8097*FLEN/8, x3, x1, x4) + +inst_2734: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfe00; +op3val:0x3c00; valaddr_reg:x2; val_offset:8100*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8100*FLEN/8, x3, x1, x4) + +inst_2735: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfe00; +op3val:0xbc00; valaddr_reg:x2; val_offset:8103*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8103*FLEN/8, x3, x1, x4) + +inst_2736: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7e01; +op3val:0x0; valaddr_reg:x2; val_offset:8106*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8106*FLEN/8, x3, x1, x4) + +inst_2737: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7e01; +op3val:0x8000; valaddr_reg:x2; val_offset:8109*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8109*FLEN/8, x3, x1, x4) + +inst_2738: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7e01; +op3val:0x1; valaddr_reg:x2; val_offset:8112*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8112*FLEN/8, x3, x1, x4) + +inst_2739: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7e01; +op3val:0x8001; valaddr_reg:x2; val_offset:8115*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8115*FLEN/8, x3, x1, x4) + +inst_2740: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7e01; +op3val:0x2; valaddr_reg:x2; val_offset:8118*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8118*FLEN/8, x3, x1, x4) + +inst_2741: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7e01; +op3val:0x83fe; valaddr_reg:x2; val_offset:8121*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8121*FLEN/8, x3, x1, x4) + +inst_2742: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7e01; +op3val:0x3ff; valaddr_reg:x2; val_offset:8124*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8124*FLEN/8, x3, x1, x4) + +inst_2743: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7e01; +op3val:0x83ff; valaddr_reg:x2; val_offset:8127*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8127*FLEN/8, x3, x1, x4) + +inst_2744: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7e01; +op3val:0x400; valaddr_reg:x2; val_offset:8130*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8130*FLEN/8, x3, x1, x4) + +inst_2745: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7e01; +op3val:0x8400; valaddr_reg:x2; val_offset:8133*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8133*FLEN/8, x3, x1, x4) + +inst_2746: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7e01; +op3val:0x401; valaddr_reg:x2; val_offset:8136*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8136*FLEN/8, x3, x1, x4) + +inst_2747: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7e01; +op3val:0x8455; valaddr_reg:x2; val_offset:8139*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8139*FLEN/8, x3, x1, x4) + +inst_2748: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7e01; +op3val:0x7bff; valaddr_reg:x2; val_offset:8142*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8142*FLEN/8, x3, x1, x4) + +inst_2749: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7e01; +op3val:0xfbff; valaddr_reg:x2; val_offset:8145*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8145*FLEN/8, x3, x1, x4) + +inst_2750: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7e01; +op3val:0x7c00; valaddr_reg:x2; val_offset:8148*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8148*FLEN/8, x3, x1, x4) + +inst_2751: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7e01; +op3val:0xfc00; valaddr_reg:x2; val_offset:8151*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8151*FLEN/8, x3, x1, x4) + +inst_2752: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7e01; +op3val:0x7e00; valaddr_reg:x2; val_offset:8154*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8154*FLEN/8, x3, x1, x4) + +inst_2753: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7e01; +op3val:0xfe00; valaddr_reg:x2; val_offset:8157*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8157*FLEN/8, x3, x1, x4) + +inst_2754: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7e01; +op3val:0x7e01; valaddr_reg:x2; val_offset:8160*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8160*FLEN/8, x3, x1, x4) + +inst_2755: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7e01; +op3val:0xfe55; valaddr_reg:x2; val_offset:8163*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8163*FLEN/8, x3, x1, x4) + +inst_2756: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7e01; +op3val:0x7c01; valaddr_reg:x2; val_offset:8166*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8166*FLEN/8, x3, x1, x4) + +inst_2757: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7e01; +op3val:0xfd55; valaddr_reg:x2; val_offset:8169*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8169*FLEN/8, x3, x1, x4) + +inst_2758: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7e01; +op3val:0x3c00; valaddr_reg:x2; val_offset:8172*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8172*FLEN/8, x3, x1, x4) + +inst_2759: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7e01; +op3val:0xbc00; valaddr_reg:x2; val_offset:8175*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8175*FLEN/8, x3, x1, x4) + +inst_2760: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfe55; +op3val:0x0; valaddr_reg:x2; val_offset:8178*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8178*FLEN/8, x3, x1, x4) + +inst_2761: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfe55; +op3val:0x8000; valaddr_reg:x2; val_offset:8181*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8181*FLEN/8, x3, x1, x4) + +inst_2762: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfe55; +op3val:0x1; valaddr_reg:x2; val_offset:8184*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8184*FLEN/8, x3, x1, x4) + +inst_2763: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfe55; +op3val:0x8001; valaddr_reg:x2; val_offset:8187*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8187*FLEN/8, x3, x1, x4) + +inst_2764: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfe55; +op3val:0x2; valaddr_reg:x2; val_offset:8190*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8190*FLEN/8, x3, x1, x4) + +inst_2765: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfe55; +op3val:0x83fe; valaddr_reg:x2; val_offset:8193*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8193*FLEN/8, x3, x1, x4) + +inst_2766: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfe55; +op3val:0x3ff; valaddr_reg:x2; val_offset:8196*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8196*FLEN/8, x3, x1, x4) + +inst_2767: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfe55; +op3val:0x83ff; valaddr_reg:x2; val_offset:8199*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8199*FLEN/8, x3, x1, x4) + +inst_2768: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfe55; +op3val:0x400; valaddr_reg:x2; val_offset:8202*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8202*FLEN/8, x3, x1, x4) + +inst_2769: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfe55; +op3val:0x8400; valaddr_reg:x2; val_offset:8205*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8205*FLEN/8, x3, x1, x4) + +inst_2770: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfe55; +op3val:0x401; valaddr_reg:x2; val_offset:8208*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8208*FLEN/8, x3, x1, x4) + +inst_2771: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfe55; +op3val:0x8455; valaddr_reg:x2; val_offset:8211*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8211*FLEN/8, x3, x1, x4) + +inst_2772: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfe55; +op3val:0x7bff; valaddr_reg:x2; val_offset:8214*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8214*FLEN/8, x3, x1, x4) + +inst_2773: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfe55; +op3val:0xfbff; valaddr_reg:x2; val_offset:8217*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8217*FLEN/8, x3, x1, x4) + +inst_2774: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfe55; +op3val:0x7c00; valaddr_reg:x2; val_offset:8220*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8220*FLEN/8, x3, x1, x4) + +inst_2775: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfe55; +op3val:0xfc00; valaddr_reg:x2; val_offset:8223*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8223*FLEN/8, x3, x1, x4) + +inst_2776: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfe55; +op3val:0x7e00; valaddr_reg:x2; val_offset:8226*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8226*FLEN/8, x3, x1, x4) + +inst_2777: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfe55; +op3val:0xfe00; valaddr_reg:x2; val_offset:8229*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8229*FLEN/8, x3, x1, x4) + +inst_2778: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfe55; +op3val:0x7e01; valaddr_reg:x2; val_offset:8232*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8232*FLEN/8, x3, x1, x4) + +inst_2779: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfe55; +op3val:0xfe55; valaddr_reg:x2; val_offset:8235*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8235*FLEN/8, x3, x1, x4) + +inst_2780: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfe55; +op3val:0x7c01; valaddr_reg:x2; val_offset:8238*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8238*FLEN/8, x3, x1, x4) + +inst_2781: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfe55; +op3val:0xfd55; valaddr_reg:x2; val_offset:8241*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8241*FLEN/8, x3, x1, x4) + +inst_2782: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfe55; +op3val:0x3c00; valaddr_reg:x2; val_offset:8244*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8244*FLEN/8, x3, x1, x4) + +inst_2783: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfe55; +op3val:0xbc00; valaddr_reg:x2; val_offset:8247*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8247*FLEN/8, x3, x1, x4) + +inst_2784: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7c01; +op3val:0x0; valaddr_reg:x2; val_offset:8250*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8250*FLEN/8, x3, x1, x4) + +inst_2785: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7c01; +op3val:0x8000; valaddr_reg:x2; val_offset:8253*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8253*FLEN/8, x3, x1, x4) + +inst_2786: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7c01; +op3val:0x1; valaddr_reg:x2; val_offset:8256*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8256*FLEN/8, x3, x1, x4) + +inst_2787: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7c01; +op3val:0x8001; valaddr_reg:x2; val_offset:8259*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8259*FLEN/8, x3, x1, x4) + +inst_2788: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7c01; +op3val:0x2; valaddr_reg:x2; val_offset:8262*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8262*FLEN/8, x3, x1, x4) + +inst_2789: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7c01; +op3val:0x83fe; valaddr_reg:x2; val_offset:8265*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8265*FLEN/8, x3, x1, x4) + +inst_2790: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7c01; +op3val:0x3ff; valaddr_reg:x2; val_offset:8268*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8268*FLEN/8, x3, x1, x4) + +inst_2791: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7c01; +op3val:0x83ff; valaddr_reg:x2; val_offset:8271*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8271*FLEN/8, x3, x1, x4) + +inst_2792: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7c01; +op3val:0x400; valaddr_reg:x2; val_offset:8274*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8274*FLEN/8, x3, x1, x4) + +inst_2793: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7c01; +op3val:0x8400; valaddr_reg:x2; val_offset:8277*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8277*FLEN/8, x3, x1, x4) + +inst_2794: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7c01; +op3val:0x401; valaddr_reg:x2; val_offset:8280*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8280*FLEN/8, x3, x1, x4) + +inst_2795: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7c01; +op3val:0x8455; valaddr_reg:x2; val_offset:8283*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8283*FLEN/8, x3, x1, x4) + +inst_2796: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7c01; +op3val:0x7bff; valaddr_reg:x2; val_offset:8286*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8286*FLEN/8, x3, x1, x4) + +inst_2797: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7c01; +op3val:0xfbff; valaddr_reg:x2; val_offset:8289*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8289*FLEN/8, x3, x1, x4) + +inst_2798: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7c01; +op3val:0x7c00; valaddr_reg:x2; val_offset:8292*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8292*FLEN/8, x3, x1, x4) + +inst_2799: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7c01; +op3val:0xfc00; valaddr_reg:x2; val_offset:8295*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8295*FLEN/8, x3, x1, x4) + +inst_2800: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7c01; +op3val:0x7e00; valaddr_reg:x2; val_offset:8298*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8298*FLEN/8, x3, x1, x4) + +inst_2801: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7c01; +op3val:0xfe00; valaddr_reg:x2; val_offset:8301*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8301*FLEN/8, x3, x1, x4) + +inst_2802: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7c01; +op3val:0x7e01; valaddr_reg:x2; val_offset:8304*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8304*FLEN/8, x3, x1, x4) + +inst_2803: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7c01; +op3val:0xfe55; valaddr_reg:x2; val_offset:8307*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8307*FLEN/8, x3, x1, x4) + +inst_2804: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7c01; +op3val:0x7c01; valaddr_reg:x2; val_offset:8310*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8310*FLEN/8, x3, x1, x4) + +inst_2805: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7c01; +op3val:0xfd55; valaddr_reg:x2; val_offset:8313*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8313*FLEN/8, x3, x1, x4) + +inst_2806: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7c01; +op3val:0x3c00; valaddr_reg:x2; val_offset:8316*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8316*FLEN/8, x3, x1, x4) + +inst_2807: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7c01; +op3val:0xbc00; valaddr_reg:x2; val_offset:8319*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8319*FLEN/8, x3, x1, x4) + +inst_2808: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfd55; +op3val:0x0; valaddr_reg:x2; val_offset:8322*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8322*FLEN/8, x3, x1, x4) + +inst_2809: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfd55; +op3val:0x8000; valaddr_reg:x2; val_offset:8325*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8325*FLEN/8, x3, x1, x4) + +inst_2810: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfd55; +op3val:0x1; valaddr_reg:x2; val_offset:8328*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8328*FLEN/8, x3, x1, x4) + +inst_2811: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfd55; +op3val:0x8001; valaddr_reg:x2; val_offset:8331*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8331*FLEN/8, x3, x1, x4) + +inst_2812: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfd55; +op3val:0x2; valaddr_reg:x2; val_offset:8334*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8334*FLEN/8, x3, x1, x4) + +inst_2813: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfd55; +op3val:0x83fe; valaddr_reg:x2; val_offset:8337*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8337*FLEN/8, x3, x1, x4) + +inst_2814: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfd55; +op3val:0x3ff; valaddr_reg:x2; val_offset:8340*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8340*FLEN/8, x3, x1, x4) + +inst_2815: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfd55; +op3val:0x83ff; valaddr_reg:x2; val_offset:8343*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8343*FLEN/8, x3, x1, x4) + +inst_2816: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfd55; +op3val:0x400; valaddr_reg:x2; val_offset:8346*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8346*FLEN/8, x3, x1, x4) + +inst_2817: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfd55; +op3val:0x8400; valaddr_reg:x2; val_offset:8349*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8349*FLEN/8, x3, x1, x4) + +inst_2818: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfd55; +op3val:0x401; valaddr_reg:x2; val_offset:8352*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8352*FLEN/8, x3, x1, x4) + +inst_2819: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfd55; +op3val:0x8455; valaddr_reg:x2; val_offset:8355*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8355*FLEN/8, x3, x1, x4) + +inst_2820: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfd55; +op3val:0x7bff; valaddr_reg:x2; val_offset:8358*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8358*FLEN/8, x3, x1, x4) + +inst_2821: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfd55; +op3val:0xfbff; valaddr_reg:x2; val_offset:8361*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8361*FLEN/8, x3, x1, x4) + +inst_2822: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfd55; +op3val:0x7c00; valaddr_reg:x2; val_offset:8364*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8364*FLEN/8, x3, x1, x4) + +inst_2823: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfd55; +op3val:0xfc00; valaddr_reg:x2; val_offset:8367*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8367*FLEN/8, x3, x1, x4) + +inst_2824: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfd55; +op3val:0x7e00; valaddr_reg:x2; val_offset:8370*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8370*FLEN/8, x3, x1, x4) + +inst_2825: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfd55; +op3val:0xfe00; valaddr_reg:x2; val_offset:8373*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8373*FLEN/8, x3, x1, x4) + +inst_2826: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfd55; +op3val:0x7e01; valaddr_reg:x2; val_offset:8376*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8376*FLEN/8, x3, x1, x4) + +inst_2827: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfd55; +op3val:0xfe55; valaddr_reg:x2; val_offset:8379*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8379*FLEN/8, x3, x1, x4) + +inst_2828: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfd55; +op3val:0x7c01; valaddr_reg:x2; val_offset:8382*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8382*FLEN/8, x3, x1, x4) + +inst_2829: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfd55; +op3val:0xfd55; valaddr_reg:x2; val_offset:8385*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8385*FLEN/8, x3, x1, x4) + +inst_2830: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfd55; +op3val:0x3c00; valaddr_reg:x2; val_offset:8388*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8388*FLEN/8, x3, x1, x4) + +inst_2831: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xfd55; +op3val:0xbc00; valaddr_reg:x2; val_offset:8391*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8391*FLEN/8, x3, x1, x4) + +inst_2832: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3c00; +op3val:0x0; valaddr_reg:x2; val_offset:8394*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8394*FLEN/8, x3, x1, x4) + +inst_2833: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3c00; +op3val:0x8000; valaddr_reg:x2; val_offset:8397*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8397*FLEN/8, x3, x1, x4) + +inst_2834: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3c00; +op3val:0x1; valaddr_reg:x2; val_offset:8400*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8400*FLEN/8, x3, x1, x4) + +inst_2835: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3c00; +op3val:0x8001; valaddr_reg:x2; val_offset:8403*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8403*FLEN/8, x3, x1, x4) + +inst_2836: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3c00; +op3val:0x2; valaddr_reg:x2; val_offset:8406*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8406*FLEN/8, x3, x1, x4) + +inst_2837: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3c00; +op3val:0x83fe; valaddr_reg:x2; val_offset:8409*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8409*FLEN/8, x3, x1, x4) + +inst_2838: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3c00; +op3val:0x3ff; valaddr_reg:x2; val_offset:8412*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8412*FLEN/8, x3, x1, x4) + +inst_2839: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3c00; +op3val:0x83ff; valaddr_reg:x2; val_offset:8415*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8415*FLEN/8, x3, x1, x4) + +inst_2840: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3c00; +op3val:0x400; valaddr_reg:x2; val_offset:8418*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8418*FLEN/8, x3, x1, x4) + +inst_2841: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3c00; +op3val:0x8400; valaddr_reg:x2; val_offset:8421*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8421*FLEN/8, x3, x1, x4) + +inst_2842: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3c00; +op3val:0x401; valaddr_reg:x2; val_offset:8424*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8424*FLEN/8, x3, x1, x4) + +inst_2843: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3c00; +op3val:0x8455; valaddr_reg:x2; val_offset:8427*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8427*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_23) + +inst_2844: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3c00; +op3val:0x7bff; valaddr_reg:x2; val_offset:8430*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8430*FLEN/8, x3, x1, x4) + +inst_2845: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3c00; +op3val:0xfbff; valaddr_reg:x2; val_offset:8433*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8433*FLEN/8, x3, x1, x4) + +inst_2846: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3c00; +op3val:0x7c00; valaddr_reg:x2; val_offset:8436*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8436*FLEN/8, x3, x1, x4) + +inst_2847: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3c00; +op3val:0xfc00; valaddr_reg:x2; val_offset:8439*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8439*FLEN/8, x3, x1, x4) + +inst_2848: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3c00; +op3val:0x7e00; valaddr_reg:x2; val_offset:8442*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8442*FLEN/8, x3, x1, x4) + +inst_2849: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3c00; +op3val:0xfe00; valaddr_reg:x2; val_offset:8445*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8445*FLEN/8, x3, x1, x4) + +inst_2850: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3c00; +op3val:0x7e01; valaddr_reg:x2; val_offset:8448*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8448*FLEN/8, x3, x1, x4) + +inst_2851: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3c00; +op3val:0xfe55; valaddr_reg:x2; val_offset:8451*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8451*FLEN/8, x3, x1, x4) + +inst_2852: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3c00; +op3val:0x7c01; valaddr_reg:x2; val_offset:8454*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8454*FLEN/8, x3, x1, x4) + +inst_2853: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3c00; +op3val:0xfd55; valaddr_reg:x2; val_offset:8457*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8457*FLEN/8, x3, x1, x4) + +inst_2854: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3c00; +op3val:0x3c00; valaddr_reg:x2; val_offset:8460*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8460*FLEN/8, x3, x1, x4) + +inst_2855: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3c00; +op3val:0xbc00; valaddr_reg:x2; val_offset:8463*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8463*FLEN/8, x3, x1, x4) + +inst_2856: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xbc00; +op3val:0x0; valaddr_reg:x2; val_offset:8466*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8466*FLEN/8, x3, x1, x4) + +inst_2857: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xbc00; +op3val:0x8000; valaddr_reg:x2; val_offset:8469*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8469*FLEN/8, x3, x1, x4) + +inst_2858: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xbc00; +op3val:0x1; valaddr_reg:x2; val_offset:8472*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8472*FLEN/8, x3, x1, x4) + +inst_2859: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xbc00; +op3val:0x8001; valaddr_reg:x2; val_offset:8475*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8475*FLEN/8, x3, x1, x4) + +inst_2860: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xbc00; +op3val:0x2; valaddr_reg:x2; val_offset:8478*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8478*FLEN/8, x3, x1, x4) + +inst_2861: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xbc00; +op3val:0x83fe; valaddr_reg:x2; val_offset:8481*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8481*FLEN/8, x3, x1, x4) + +inst_2862: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xbc00; +op3val:0x3ff; valaddr_reg:x2; val_offset:8484*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8484*FLEN/8, x3, x1, x4) + +inst_2863: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xbc00; +op3val:0x83ff; valaddr_reg:x2; val_offset:8487*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8487*FLEN/8, x3, x1, x4) + +inst_2864: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xbc00; +op3val:0x400; valaddr_reg:x2; val_offset:8490*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8490*FLEN/8, x3, x1, x4) + +inst_2865: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xbc00; +op3val:0x8400; valaddr_reg:x2; val_offset:8493*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8493*FLEN/8, x3, x1, x4) + +inst_2866: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xbc00; +op3val:0x401; valaddr_reg:x2; val_offset:8496*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8496*FLEN/8, x3, x1, x4) + +inst_2867: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xbc00; +op3val:0x8455; valaddr_reg:x2; val_offset:8499*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8499*FLEN/8, x3, x1, x4) + +inst_2868: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xbc00; +op3val:0x7bff; valaddr_reg:x2; val_offset:8502*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8502*FLEN/8, x3, x1, x4) + +inst_2869: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xbc00; +op3val:0xfbff; valaddr_reg:x2; val_offset:8505*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8505*FLEN/8, x3, x1, x4) + +inst_2870: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xbc00; +op3val:0x7c00; valaddr_reg:x2; val_offset:8508*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8508*FLEN/8, x3, x1, x4) + +inst_2871: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xbc00; +op3val:0xfc00; valaddr_reg:x2; val_offset:8511*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8511*FLEN/8, x3, x1, x4) + +inst_2872: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xbc00; +op3val:0x7e00; valaddr_reg:x2; val_offset:8514*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8514*FLEN/8, x3, x1, x4) + +inst_2873: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xbc00; +op3val:0xfe00; valaddr_reg:x2; val_offset:8517*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8517*FLEN/8, x3, x1, x4) + +inst_2874: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xbc00; +op3val:0x7e01; valaddr_reg:x2; val_offset:8520*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8520*FLEN/8, x3, x1, x4) + +inst_2875: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xbc00; +op3val:0xfe55; valaddr_reg:x2; val_offset:8523*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8523*FLEN/8, x3, x1, x4) + +inst_2876: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xbc00; +op3val:0x7c01; valaddr_reg:x2; val_offset:8526*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8526*FLEN/8, x3, x1, x4) + +inst_2877: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xbc00; +op3val:0xfd55; valaddr_reg:x2; val_offset:8529*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8529*FLEN/8, x3, x1, x4) + +inst_2878: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xbc00; +op3val:0x3c00; valaddr_reg:x2; val_offset:8532*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8532*FLEN/8, x3, x1, x4) + +inst_2879: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xbc00; +op3val:0xbc00; valaddr_reg:x2; val_offset:8535*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8535*FLEN/8, x3, x1, x4) + +inst_2880: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x0; +op3val:0x0; valaddr_reg:x2; val_offset:8538*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8538*FLEN/8, x3, x1, x4) + +inst_2881: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x0; +op3val:0x8000; valaddr_reg:x2; val_offset:8541*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8541*FLEN/8, x3, x1, x4) + +inst_2882: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x0; +op3val:0x1; valaddr_reg:x2; val_offset:8544*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8544*FLEN/8, x3, x1, x4) + +inst_2883: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x0; +op3val:0x8001; valaddr_reg:x2; val_offset:8547*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8547*FLEN/8, x3, x1, x4) + +inst_2884: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x0; +op3val:0x2; valaddr_reg:x2; val_offset:8550*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8550*FLEN/8, x3, x1, x4) + +inst_2885: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x0; +op3val:0x83fe; valaddr_reg:x2; val_offset:8553*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8553*FLEN/8, x3, x1, x4) + +inst_2886: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x0; +op3val:0x3ff; valaddr_reg:x2; val_offset:8556*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8556*FLEN/8, x3, x1, x4) + +inst_2887: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x0; +op3val:0x83ff; valaddr_reg:x2; val_offset:8559*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8559*FLEN/8, x3, x1, x4) + +inst_2888: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x0; +op3val:0x400; valaddr_reg:x2; val_offset:8562*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8562*FLEN/8, x3, x1, x4) + +inst_2889: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x0; +op3val:0x8400; valaddr_reg:x2; val_offset:8565*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8565*FLEN/8, x3, x1, x4) + +inst_2890: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x0; +op3val:0x401; valaddr_reg:x2; val_offset:8568*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8568*FLEN/8, x3, x1, x4) + +inst_2891: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x0; +op3val:0x8455; valaddr_reg:x2; val_offset:8571*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8571*FLEN/8, x3, x1, x4) + +inst_2892: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x0; +op3val:0x7bff; valaddr_reg:x2; val_offset:8574*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8574*FLEN/8, x3, x1, x4) + +inst_2893: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x0; +op3val:0xfbff; valaddr_reg:x2; val_offset:8577*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8577*FLEN/8, x3, x1, x4) + +inst_2894: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x0; +op3val:0x7c00; valaddr_reg:x2; val_offset:8580*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8580*FLEN/8, x3, x1, x4) + +inst_2895: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x0; +op3val:0xfc00; valaddr_reg:x2; val_offset:8583*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8583*FLEN/8, x3, x1, x4) + +inst_2896: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x0; +op3val:0x7e00; valaddr_reg:x2; val_offset:8586*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8586*FLEN/8, x3, x1, x4) + +inst_2897: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x0; +op3val:0xfe00; valaddr_reg:x2; val_offset:8589*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8589*FLEN/8, x3, x1, x4) + +inst_2898: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x0; +op3val:0x7e01; valaddr_reg:x2; val_offset:8592*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8592*FLEN/8, x3, x1, x4) + +inst_2899: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x0; +op3val:0xfe55; valaddr_reg:x2; val_offset:8595*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8595*FLEN/8, x3, x1, x4) + +inst_2900: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x0; +op3val:0x7c01; valaddr_reg:x2; val_offset:8598*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8598*FLEN/8, x3, x1, x4) + +inst_2901: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x0; +op3val:0xfd55; valaddr_reg:x2; val_offset:8601*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8601*FLEN/8, x3, x1, x4) + +inst_2902: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x0; +op3val:0x3c00; valaddr_reg:x2; val_offset:8604*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8604*FLEN/8, x3, x1, x4) + +inst_2903: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x0; +op3val:0xbc00; valaddr_reg:x2; val_offset:8607*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8607*FLEN/8, x3, x1, x4) + +inst_2904: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8000; +op3val:0x0; valaddr_reg:x2; val_offset:8610*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8610*FLEN/8, x3, x1, x4) + +inst_2905: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8000; +op3val:0x8000; valaddr_reg:x2; val_offset:8613*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8613*FLEN/8, x3, x1, x4) + +inst_2906: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8000; +op3val:0x1; valaddr_reg:x2; val_offset:8616*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8616*FLEN/8, x3, x1, x4) + +inst_2907: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8000; +op3val:0x8001; valaddr_reg:x2; val_offset:8619*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8619*FLEN/8, x3, x1, x4) + +inst_2908: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8000; +op3val:0x2; valaddr_reg:x2; val_offset:8622*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8622*FLEN/8, x3, x1, x4) + +inst_2909: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8000; +op3val:0x83fe; valaddr_reg:x2; val_offset:8625*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8625*FLEN/8, x3, x1, x4) + +inst_2910: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8000; +op3val:0x3ff; valaddr_reg:x2; val_offset:8628*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8628*FLEN/8, x3, x1, x4) + +inst_2911: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8000; +op3val:0x83ff; valaddr_reg:x2; val_offset:8631*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8631*FLEN/8, x3, x1, x4) + +inst_2912: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8000; +op3val:0x400; valaddr_reg:x2; val_offset:8634*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8634*FLEN/8, x3, x1, x4) + +inst_2913: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8000; +op3val:0x8400; valaddr_reg:x2; val_offset:8637*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8637*FLEN/8, x3, x1, x4) + +inst_2914: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8000; +op3val:0x401; valaddr_reg:x2; val_offset:8640*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8640*FLEN/8, x3, x1, x4) + +inst_2915: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8000; +op3val:0x8455; valaddr_reg:x2; val_offset:8643*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8643*FLEN/8, x3, x1, x4) + +inst_2916: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x2; val_offset:8646*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8646*FLEN/8, x3, x1, x4) + +inst_2917: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x2; val_offset:8649*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8649*FLEN/8, x3, x1, x4) + +inst_2918: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8000; +op3val:0x7c00; valaddr_reg:x2; val_offset:8652*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8652*FLEN/8, x3, x1, x4) + +inst_2919: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8000; +op3val:0xfc00; valaddr_reg:x2; val_offset:8655*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8655*FLEN/8, x3, x1, x4) + +inst_2920: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8000; +op3val:0x7e00; valaddr_reg:x2; val_offset:8658*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8658*FLEN/8, x3, x1, x4) + +inst_2921: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8000; +op3val:0xfe00; valaddr_reg:x2; val_offset:8661*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8661*FLEN/8, x3, x1, x4) + +inst_2922: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8000; +op3val:0x7e01; valaddr_reg:x2; val_offset:8664*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8664*FLEN/8, x3, x1, x4) + +inst_2923: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8000; +op3val:0xfe55; valaddr_reg:x2; val_offset:8667*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8667*FLEN/8, x3, x1, x4) + +inst_2924: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8000; +op3val:0x7c01; valaddr_reg:x2; val_offset:8670*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8670*FLEN/8, x3, x1, x4) + +inst_2925: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8000; +op3val:0xfd55; valaddr_reg:x2; val_offset:8673*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8673*FLEN/8, x3, x1, x4) + +inst_2926: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8000; +op3val:0x3c00; valaddr_reg:x2; val_offset:8676*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8676*FLEN/8, x3, x1, x4) + +inst_2927: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8000; +op3val:0xbc00; valaddr_reg:x2; val_offset:8679*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8679*FLEN/8, x3, x1, x4) + +inst_2928: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x1; +op3val:0x0; valaddr_reg:x2; val_offset:8682*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8682*FLEN/8, x3, x1, x4) + +inst_2929: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x1; +op3val:0x8000; valaddr_reg:x2; val_offset:8685*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8685*FLEN/8, x3, x1, x4) + +inst_2930: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x1; +op3val:0x1; valaddr_reg:x2; val_offset:8688*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8688*FLEN/8, x3, x1, x4) + +inst_2931: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x1; +op3val:0x8001; valaddr_reg:x2; val_offset:8691*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8691*FLEN/8, x3, x1, x4) + +inst_2932: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x1; +op3val:0x2; valaddr_reg:x2; val_offset:8694*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8694*FLEN/8, x3, x1, x4) + +inst_2933: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x1; +op3val:0x83fe; valaddr_reg:x2; val_offset:8697*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8697*FLEN/8, x3, x1, x4) + +inst_2934: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x1; +op3val:0x3ff; valaddr_reg:x2; val_offset:8700*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8700*FLEN/8, x3, x1, x4) + +inst_2935: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x1; +op3val:0x83ff; valaddr_reg:x2; val_offset:8703*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8703*FLEN/8, x3, x1, x4) + +inst_2936: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x1; +op3val:0x400; valaddr_reg:x2; val_offset:8706*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8706*FLEN/8, x3, x1, x4) + +inst_2937: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x1; +op3val:0x8400; valaddr_reg:x2; val_offset:8709*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8709*FLEN/8, x3, x1, x4) + +inst_2938: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x1; +op3val:0x401; valaddr_reg:x2; val_offset:8712*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8712*FLEN/8, x3, x1, x4) + +inst_2939: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x1; +op3val:0x8455; valaddr_reg:x2; val_offset:8715*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8715*FLEN/8, x3, x1, x4) + +inst_2940: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x1; +op3val:0x7bff; valaddr_reg:x2; val_offset:8718*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8718*FLEN/8, x3, x1, x4) + +inst_2941: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x1; +op3val:0xfbff; valaddr_reg:x2; val_offset:8721*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8721*FLEN/8, x3, x1, x4) + +inst_2942: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x1; +op3val:0x7c00; valaddr_reg:x2; val_offset:8724*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8724*FLEN/8, x3, x1, x4) + +inst_2943: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x1; +op3val:0xfc00; valaddr_reg:x2; val_offset:8727*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8727*FLEN/8, x3, x1, x4) + +inst_2944: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x1; +op3val:0x7e00; valaddr_reg:x2; val_offset:8730*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8730*FLEN/8, x3, x1, x4) + +inst_2945: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x1; +op3val:0xfe00; valaddr_reg:x2; val_offset:8733*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8733*FLEN/8, x3, x1, x4) + +inst_2946: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x1; +op3val:0x7e01; valaddr_reg:x2; val_offset:8736*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8736*FLEN/8, x3, x1, x4) + +inst_2947: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x1; +op3val:0xfe55; valaddr_reg:x2; val_offset:8739*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8739*FLEN/8, x3, x1, x4) + +inst_2948: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x1; +op3val:0x7c01; valaddr_reg:x2; val_offset:8742*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8742*FLEN/8, x3, x1, x4) + +inst_2949: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x1; +op3val:0xfd55; valaddr_reg:x2; val_offset:8745*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8745*FLEN/8, x3, x1, x4) + +inst_2950: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x1; +op3val:0x3c00; valaddr_reg:x2; val_offset:8748*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8748*FLEN/8, x3, x1, x4) + +inst_2951: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x1; +op3val:0xbc00; valaddr_reg:x2; val_offset:8751*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8751*FLEN/8, x3, x1, x4) + +inst_2952: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8001; +op3val:0x0; valaddr_reg:x2; val_offset:8754*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8754*FLEN/8, x3, x1, x4) + +inst_2953: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8001; +op3val:0x8000; valaddr_reg:x2; val_offset:8757*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8757*FLEN/8, x3, x1, x4) + +inst_2954: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8001; +op3val:0x1; valaddr_reg:x2; val_offset:8760*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8760*FLEN/8, x3, x1, x4) + +inst_2955: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8001; +op3val:0x8001; valaddr_reg:x2; val_offset:8763*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8763*FLEN/8, x3, x1, x4) + +inst_2956: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8001; +op3val:0x2; valaddr_reg:x2; val_offset:8766*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8766*FLEN/8, x3, x1, x4) + +inst_2957: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8001; +op3val:0x83fe; valaddr_reg:x2; val_offset:8769*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8769*FLEN/8, x3, x1, x4) + +inst_2958: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8001; +op3val:0x3ff; valaddr_reg:x2; val_offset:8772*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8772*FLEN/8, x3, x1, x4) + +inst_2959: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8001; +op3val:0x83ff; valaddr_reg:x2; val_offset:8775*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8775*FLEN/8, x3, x1, x4) + +inst_2960: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8001; +op3val:0x400; valaddr_reg:x2; val_offset:8778*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8778*FLEN/8, x3, x1, x4) + +inst_2961: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8001; +op3val:0x8400; valaddr_reg:x2; val_offset:8781*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8781*FLEN/8, x3, x1, x4) + +inst_2962: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8001; +op3val:0x401; valaddr_reg:x2; val_offset:8784*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8784*FLEN/8, x3, x1, x4) + +inst_2963: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8001; +op3val:0x8455; valaddr_reg:x2; val_offset:8787*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8787*FLEN/8, x3, x1, x4) + +inst_2964: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8001; +op3val:0x7bff; valaddr_reg:x2; val_offset:8790*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8790*FLEN/8, x3, x1, x4) + +inst_2965: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8001; +op3val:0xfbff; valaddr_reg:x2; val_offset:8793*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8793*FLEN/8, x3, x1, x4) + +inst_2966: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8001; +op3val:0x7c00; valaddr_reg:x2; val_offset:8796*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8796*FLEN/8, x3, x1, x4) + +inst_2967: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8001; +op3val:0xfc00; valaddr_reg:x2; val_offset:8799*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8799*FLEN/8, x3, x1, x4) + +inst_2968: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8001; +op3val:0x7e00; valaddr_reg:x2; val_offset:8802*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8802*FLEN/8, x3, x1, x4) + +inst_2969: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8001; +op3val:0xfe00; valaddr_reg:x2; val_offset:8805*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8805*FLEN/8, x3, x1, x4) + +inst_2970: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8001; +op3val:0x7e01; valaddr_reg:x2; val_offset:8808*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8808*FLEN/8, x3, x1, x4) + +inst_2971: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8001; +op3val:0xfe55; valaddr_reg:x2; val_offset:8811*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8811*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_24) + +inst_2972: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8001; +op3val:0x7c01; valaddr_reg:x2; val_offset:8814*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8814*FLEN/8, x3, x1, x4) + +inst_2973: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8001; +op3val:0xfd55; valaddr_reg:x2; val_offset:8817*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8817*FLEN/8, x3, x1, x4) + +inst_2974: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8001; +op3val:0x3c00; valaddr_reg:x2; val_offset:8820*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8820*FLEN/8, x3, x1, x4) + +inst_2975: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8001; +op3val:0xbc00; valaddr_reg:x2; val_offset:8823*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8823*FLEN/8, x3, x1, x4) + +inst_2976: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x2; +op3val:0x0; valaddr_reg:x2; val_offset:8826*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8826*FLEN/8, x3, x1, x4) + +inst_2977: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x2; +op3val:0x8000; valaddr_reg:x2; val_offset:8829*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8829*FLEN/8, x3, x1, x4) + +inst_2978: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x2; +op3val:0x1; valaddr_reg:x2; val_offset:8832*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8832*FLEN/8, x3, x1, x4) + +inst_2979: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x2; +op3val:0x8001; valaddr_reg:x2; val_offset:8835*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8835*FLEN/8, x3, x1, x4) + +inst_2980: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x2; +op3val:0x2; valaddr_reg:x2; val_offset:8838*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8838*FLEN/8, x3, x1, x4) + +inst_2981: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x2; +op3val:0x83fe; valaddr_reg:x2; val_offset:8841*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8841*FLEN/8, x3, x1, x4) + +inst_2982: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x2; +op3val:0x3ff; valaddr_reg:x2; val_offset:8844*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8844*FLEN/8, x3, x1, x4) + +inst_2983: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x2; +op3val:0x83ff; valaddr_reg:x2; val_offset:8847*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8847*FLEN/8, x3, x1, x4) + +inst_2984: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x2; +op3val:0x400; valaddr_reg:x2; val_offset:8850*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8850*FLEN/8, x3, x1, x4) + +inst_2985: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x2; +op3val:0x8400; valaddr_reg:x2; val_offset:8853*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8853*FLEN/8, x3, x1, x4) + +inst_2986: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x2; +op3val:0x401; valaddr_reg:x2; val_offset:8856*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8856*FLEN/8, x3, x1, x4) + +inst_2987: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x2; +op3val:0x8455; valaddr_reg:x2; val_offset:8859*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8859*FLEN/8, x3, x1, x4) + +inst_2988: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x2; +op3val:0x7bff; valaddr_reg:x2; val_offset:8862*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8862*FLEN/8, x3, x1, x4) + +inst_2989: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x2; +op3val:0xfbff; valaddr_reg:x2; val_offset:8865*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8865*FLEN/8, x3, x1, x4) + +inst_2990: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x2; +op3val:0x7c00; valaddr_reg:x2; val_offset:8868*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8868*FLEN/8, x3, x1, x4) + +inst_2991: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x2; +op3val:0xfc00; valaddr_reg:x2; val_offset:8871*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8871*FLEN/8, x3, x1, x4) + +inst_2992: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x2; +op3val:0x7e00; valaddr_reg:x2; val_offset:8874*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8874*FLEN/8, x3, x1, x4) + +inst_2993: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x2; +op3val:0xfe00; valaddr_reg:x2; val_offset:8877*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8877*FLEN/8, x3, x1, x4) + +inst_2994: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x2; +op3val:0x7e01; valaddr_reg:x2; val_offset:8880*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8880*FLEN/8, x3, x1, x4) + +inst_2995: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x2; +op3val:0xfe55; valaddr_reg:x2; val_offset:8883*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8883*FLEN/8, x3, x1, x4) + +inst_2996: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x2; +op3val:0x7c01; valaddr_reg:x2; val_offset:8886*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8886*FLEN/8, x3, x1, x4) + +inst_2997: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x2; +op3val:0xfd55; valaddr_reg:x2; val_offset:8889*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8889*FLEN/8, x3, x1, x4) + +inst_2998: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x2; +op3val:0x3c00; valaddr_reg:x2; val_offset:8892*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8892*FLEN/8, x3, x1, x4) + +inst_2999: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x2; +op3val:0xbc00; valaddr_reg:x2; val_offset:8895*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8895*FLEN/8, x3, x1, x4) + +inst_3000: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x83fe; +op3val:0x0; valaddr_reg:x2; val_offset:8898*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8898*FLEN/8, x3, x1, x4) + +inst_3001: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x83fe; +op3val:0x8000; valaddr_reg:x2; val_offset:8901*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8901*FLEN/8, x3, x1, x4) + +inst_3002: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x83fe; +op3val:0x1; valaddr_reg:x2; val_offset:8904*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8904*FLEN/8, x3, x1, x4) + +inst_3003: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x83fe; +op3val:0x8001; valaddr_reg:x2; val_offset:8907*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8907*FLEN/8, x3, x1, x4) + +inst_3004: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x83fe; +op3val:0x2; valaddr_reg:x2; val_offset:8910*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8910*FLEN/8, x3, x1, x4) + +inst_3005: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x83fe; +op3val:0x83fe; valaddr_reg:x2; val_offset:8913*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8913*FLEN/8, x3, x1, x4) + +inst_3006: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x83fe; +op3val:0x3ff; valaddr_reg:x2; val_offset:8916*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8916*FLEN/8, x3, x1, x4) + +inst_3007: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x83fe; +op3val:0x83ff; valaddr_reg:x2; val_offset:8919*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8919*FLEN/8, x3, x1, x4) + +inst_3008: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x83fe; +op3val:0x400; valaddr_reg:x2; val_offset:8922*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8922*FLEN/8, x3, x1, x4) + +inst_3009: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x83fe; +op3val:0x8400; valaddr_reg:x2; val_offset:8925*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8925*FLEN/8, x3, x1, x4) + +inst_3010: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x83fe; +op3val:0x401; valaddr_reg:x2; val_offset:8928*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8928*FLEN/8, x3, x1, x4) + +inst_3011: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x83fe; +op3val:0x8455; valaddr_reg:x2; val_offset:8931*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8931*FLEN/8, x3, x1, x4) + +inst_3012: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x83fe; +op3val:0x7bff; valaddr_reg:x2; val_offset:8934*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8934*FLEN/8, x3, x1, x4) + +inst_3013: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x83fe; +op3val:0xfbff; valaddr_reg:x2; val_offset:8937*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8937*FLEN/8, x3, x1, x4) + +inst_3014: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x83fe; +op3val:0x7c00; valaddr_reg:x2; val_offset:8940*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8940*FLEN/8, x3, x1, x4) + +inst_3015: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x83fe; +op3val:0xfc00; valaddr_reg:x2; val_offset:8943*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8943*FLEN/8, x3, x1, x4) + +inst_3016: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x83fe; +op3val:0x7e00; valaddr_reg:x2; val_offset:8946*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8946*FLEN/8, x3, x1, x4) + +inst_3017: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x83fe; +op3val:0xfe00; valaddr_reg:x2; val_offset:8949*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8949*FLEN/8, x3, x1, x4) + +inst_3018: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x83fe; +op3val:0x7e01; valaddr_reg:x2; val_offset:8952*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8952*FLEN/8, x3, x1, x4) + +inst_3019: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x83fe; +op3val:0xfe55; valaddr_reg:x2; val_offset:8955*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8955*FLEN/8, x3, x1, x4) + +inst_3020: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x83fe; +op3val:0x7c01; valaddr_reg:x2; val_offset:8958*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8958*FLEN/8, x3, x1, x4) + +inst_3021: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x83fe; +op3val:0xfd55; valaddr_reg:x2; val_offset:8961*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8961*FLEN/8, x3, x1, x4) + +inst_3022: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x83fe; +op3val:0x3c00; valaddr_reg:x2; val_offset:8964*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8964*FLEN/8, x3, x1, x4) + +inst_3023: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x83fe; +op3val:0xbc00; valaddr_reg:x2; val_offset:8967*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8967*FLEN/8, x3, x1, x4) + +inst_3024: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x3ff; +op3val:0x0; valaddr_reg:x2; val_offset:8970*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8970*FLEN/8, x3, x1, x4) + +inst_3025: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x3ff; +op3val:0x8000; valaddr_reg:x2; val_offset:8973*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8973*FLEN/8, x3, x1, x4) + +inst_3026: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x3ff; +op3val:0x1; valaddr_reg:x2; val_offset:8976*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8976*FLEN/8, x3, x1, x4) + +inst_3027: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x3ff; +op3val:0x8001; valaddr_reg:x2; val_offset:8979*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8979*FLEN/8, x3, x1, x4) + +inst_3028: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x3ff; +op3val:0x2; valaddr_reg:x2; val_offset:8982*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8982*FLEN/8, x3, x1, x4) + +inst_3029: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x3ff; +op3val:0x83fe; valaddr_reg:x2; val_offset:8985*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8985*FLEN/8, x3, x1, x4) + +inst_3030: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x3ff; +op3val:0x3ff; valaddr_reg:x2; val_offset:8988*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8988*FLEN/8, x3, x1, x4) + +inst_3031: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x3ff; +op3val:0x83ff; valaddr_reg:x2; val_offset:8991*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8991*FLEN/8, x3, x1, x4) + +inst_3032: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x3ff; +op3val:0x400; valaddr_reg:x2; val_offset:8994*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8994*FLEN/8, x3, x1, x4) + +inst_3033: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x3ff; +op3val:0x8400; valaddr_reg:x2; val_offset:8997*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 8997*FLEN/8, x3, x1, x4) + +inst_3034: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x3ff; +op3val:0x401; valaddr_reg:x2; val_offset:9000*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9000*FLEN/8, x3, x1, x4) + +inst_3035: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x3ff; +op3val:0x8455; valaddr_reg:x2; val_offset:9003*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9003*FLEN/8, x3, x1, x4) + +inst_3036: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x3ff; +op3val:0x7bff; valaddr_reg:x2; val_offset:9006*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9006*FLEN/8, x3, x1, x4) + +inst_3037: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x3ff; +op3val:0xfbff; valaddr_reg:x2; val_offset:9009*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9009*FLEN/8, x3, x1, x4) + +inst_3038: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x3ff; +op3val:0x7c00; valaddr_reg:x2; val_offset:9012*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9012*FLEN/8, x3, x1, x4) + +inst_3039: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x3ff; +op3val:0xfc00; valaddr_reg:x2; val_offset:9015*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9015*FLEN/8, x3, x1, x4) + +inst_3040: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x3ff; +op3val:0x7e00; valaddr_reg:x2; val_offset:9018*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9018*FLEN/8, x3, x1, x4) + +inst_3041: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x3ff; +op3val:0xfe00; valaddr_reg:x2; val_offset:9021*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9021*FLEN/8, x3, x1, x4) + +inst_3042: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x3ff; +op3val:0x7e01; valaddr_reg:x2; val_offset:9024*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9024*FLEN/8, x3, x1, x4) + +inst_3043: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x3ff; +op3val:0xfe55; valaddr_reg:x2; val_offset:9027*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9027*FLEN/8, x3, x1, x4) + +inst_3044: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x3ff; +op3val:0x7c01; valaddr_reg:x2; val_offset:9030*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9030*FLEN/8, x3, x1, x4) + +inst_3045: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x3ff; +op3val:0xfd55; valaddr_reg:x2; val_offset:9033*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9033*FLEN/8, x3, x1, x4) + +inst_3046: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x3ff; +op3val:0x3c00; valaddr_reg:x2; val_offset:9036*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9036*FLEN/8, x3, x1, x4) + +inst_3047: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x3ff; +op3val:0xbc00; valaddr_reg:x2; val_offset:9039*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9039*FLEN/8, x3, x1, x4) + +inst_3048: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x83ff; +op3val:0x0; valaddr_reg:x2; val_offset:9042*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9042*FLEN/8, x3, x1, x4) + +inst_3049: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x83ff; +op3val:0x8000; valaddr_reg:x2; val_offset:9045*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9045*FLEN/8, x3, x1, x4) + +inst_3050: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x83ff; +op3val:0x1; valaddr_reg:x2; val_offset:9048*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9048*FLEN/8, x3, x1, x4) + +inst_3051: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x83ff; +op3val:0x8001; valaddr_reg:x2; val_offset:9051*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9051*FLEN/8, x3, x1, x4) + +inst_3052: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x83ff; +op3val:0x2; valaddr_reg:x2; val_offset:9054*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9054*FLEN/8, x3, x1, x4) + +inst_3053: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x83ff; +op3val:0x83fe; valaddr_reg:x2; val_offset:9057*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9057*FLEN/8, x3, x1, x4) + +inst_3054: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x83ff; +op3val:0x3ff; valaddr_reg:x2; val_offset:9060*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9060*FLEN/8, x3, x1, x4) + +inst_3055: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x83ff; +op3val:0x83ff; valaddr_reg:x2; val_offset:9063*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9063*FLEN/8, x3, x1, x4) + +inst_3056: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x83ff; +op3val:0x400; valaddr_reg:x2; val_offset:9066*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9066*FLEN/8, x3, x1, x4) + +inst_3057: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x83ff; +op3val:0x8400; valaddr_reg:x2; val_offset:9069*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9069*FLEN/8, x3, x1, x4) + +inst_3058: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x83ff; +op3val:0x401; valaddr_reg:x2; val_offset:9072*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9072*FLEN/8, x3, x1, x4) + +inst_3059: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x83ff; +op3val:0x8455; valaddr_reg:x2; val_offset:9075*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9075*FLEN/8, x3, x1, x4) + +inst_3060: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x83ff; +op3val:0x7bff; valaddr_reg:x2; val_offset:9078*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9078*FLEN/8, x3, x1, x4) + +inst_3061: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x83ff; +op3val:0xfbff; valaddr_reg:x2; val_offset:9081*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9081*FLEN/8, x3, x1, x4) + +inst_3062: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x83ff; +op3val:0x7c00; valaddr_reg:x2; val_offset:9084*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9084*FLEN/8, x3, x1, x4) + +inst_3063: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x83ff; +op3val:0xfc00; valaddr_reg:x2; val_offset:9087*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9087*FLEN/8, x3, x1, x4) + +inst_3064: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x83ff; +op3val:0x7e00; valaddr_reg:x2; val_offset:9090*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9090*FLEN/8, x3, x1, x4) + +inst_3065: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x83ff; +op3val:0xfe00; valaddr_reg:x2; val_offset:9093*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9093*FLEN/8, x3, x1, x4) + +inst_3066: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x83ff; +op3val:0x7e01; valaddr_reg:x2; val_offset:9096*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9096*FLEN/8, x3, x1, x4) + +inst_3067: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x83ff; +op3val:0xfe55; valaddr_reg:x2; val_offset:9099*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9099*FLEN/8, x3, x1, x4) + +inst_3068: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x83ff; +op3val:0x7c01; valaddr_reg:x2; val_offset:9102*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9102*FLEN/8, x3, x1, x4) + +inst_3069: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x83ff; +op3val:0xfd55; valaddr_reg:x2; val_offset:9105*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9105*FLEN/8, x3, x1, x4) + +inst_3070: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x83ff; +op3val:0x3c00; valaddr_reg:x2; val_offset:9108*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9108*FLEN/8, x3, x1, x4) + +inst_3071: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x83ff; +op3val:0xbc00; valaddr_reg:x2; val_offset:9111*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9111*FLEN/8, x3, x1, x4) + +inst_3072: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x400; +op3val:0x0; valaddr_reg:x2; val_offset:9114*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9114*FLEN/8, x3, x1, x4) + +inst_3073: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x400; +op3val:0x8000; valaddr_reg:x2; val_offset:9117*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9117*FLEN/8, x3, x1, x4) + +inst_3074: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x400; +op3val:0x1; valaddr_reg:x2; val_offset:9120*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9120*FLEN/8, x3, x1, x4) + +inst_3075: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x400; +op3val:0x8001; valaddr_reg:x2; val_offset:9123*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9123*FLEN/8, x3, x1, x4) + +inst_3076: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x400; +op3val:0x2; valaddr_reg:x2; val_offset:9126*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9126*FLEN/8, x3, x1, x4) + +inst_3077: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x400; +op3val:0x83fe; valaddr_reg:x2; val_offset:9129*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9129*FLEN/8, x3, x1, x4) + +inst_3078: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x400; +op3val:0x3ff; valaddr_reg:x2; val_offset:9132*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9132*FLEN/8, x3, x1, x4) + +inst_3079: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x400; +op3val:0x83ff; valaddr_reg:x2; val_offset:9135*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9135*FLEN/8, x3, x1, x4) + +inst_3080: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x400; +op3val:0x400; valaddr_reg:x2; val_offset:9138*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9138*FLEN/8, x3, x1, x4) + +inst_3081: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x400; +op3val:0x8400; valaddr_reg:x2; val_offset:9141*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9141*FLEN/8, x3, x1, x4) + +inst_3082: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x400; +op3val:0x401; valaddr_reg:x2; val_offset:9144*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9144*FLEN/8, x3, x1, x4) + +inst_3083: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x400; +op3val:0x8455; valaddr_reg:x2; val_offset:9147*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9147*FLEN/8, x3, x1, x4) + +inst_3084: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x400; +op3val:0x7bff; valaddr_reg:x2; val_offset:9150*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9150*FLEN/8, x3, x1, x4) + +inst_3085: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x400; +op3val:0xfbff; valaddr_reg:x2; val_offset:9153*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9153*FLEN/8, x3, x1, x4) + +inst_3086: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x400; +op3val:0x7c00; valaddr_reg:x2; val_offset:9156*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9156*FLEN/8, x3, x1, x4) + +inst_3087: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x400; +op3val:0xfc00; valaddr_reg:x2; val_offset:9159*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9159*FLEN/8, x3, x1, x4) + +inst_3088: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x400; +op3val:0x7e00; valaddr_reg:x2; val_offset:9162*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9162*FLEN/8, x3, x1, x4) + +inst_3089: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x400; +op3val:0xfe00; valaddr_reg:x2; val_offset:9165*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9165*FLEN/8, x3, x1, x4) + +inst_3090: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x400; +op3val:0x7e01; valaddr_reg:x2; val_offset:9168*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9168*FLEN/8, x3, x1, x4) + +inst_3091: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x400; +op3val:0xfe55; valaddr_reg:x2; val_offset:9171*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9171*FLEN/8, x3, x1, x4) + +inst_3092: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x400; +op3val:0x7c01; valaddr_reg:x2; val_offset:9174*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9174*FLEN/8, x3, x1, x4) + +inst_3093: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x400; +op3val:0xfd55; valaddr_reg:x2; val_offset:9177*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9177*FLEN/8, x3, x1, x4) + +inst_3094: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x400; +op3val:0x3c00; valaddr_reg:x2; val_offset:9180*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9180*FLEN/8, x3, x1, x4) + +inst_3095: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x400; +op3val:0xbc00; valaddr_reg:x2; val_offset:9183*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9183*FLEN/8, x3, x1, x4) + +inst_3096: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8400; +op3val:0x0; valaddr_reg:x2; val_offset:9186*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9186*FLEN/8, x3, x1, x4) + +inst_3097: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8400; +op3val:0x8000; valaddr_reg:x2; val_offset:9189*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9189*FLEN/8, x3, x1, x4) + +inst_3098: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8400; +op3val:0x1; valaddr_reg:x2; val_offset:9192*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9192*FLEN/8, x3, x1, x4) + +inst_3099: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8400; +op3val:0x8001; valaddr_reg:x2; val_offset:9195*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9195*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_25) + +inst_3100: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8400; +op3val:0x2; valaddr_reg:x2; val_offset:9198*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9198*FLEN/8, x3, x1, x4) + +inst_3101: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8400; +op3val:0x83fe; valaddr_reg:x2; val_offset:9201*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9201*FLEN/8, x3, x1, x4) + +inst_3102: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8400; +op3val:0x3ff; valaddr_reg:x2; val_offset:9204*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9204*FLEN/8, x3, x1, x4) + +inst_3103: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8400; +op3val:0x83ff; valaddr_reg:x2; val_offset:9207*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9207*FLEN/8, x3, x1, x4) + +inst_3104: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8400; +op3val:0x400; valaddr_reg:x2; val_offset:9210*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9210*FLEN/8, x3, x1, x4) + +inst_3105: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8400; +op3val:0x8400; valaddr_reg:x2; val_offset:9213*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9213*FLEN/8, x3, x1, x4) + +inst_3106: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8400; +op3val:0x401; valaddr_reg:x2; val_offset:9216*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9216*FLEN/8, x3, x1, x4) + +inst_3107: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8400; +op3val:0x8455; valaddr_reg:x2; val_offset:9219*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9219*FLEN/8, x3, x1, x4) + +inst_3108: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8400; +op3val:0x7bff; valaddr_reg:x2; val_offset:9222*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9222*FLEN/8, x3, x1, x4) + +inst_3109: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8400; +op3val:0xfbff; valaddr_reg:x2; val_offset:9225*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9225*FLEN/8, x3, x1, x4) + +inst_3110: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8400; +op3val:0x7c00; valaddr_reg:x2; val_offset:9228*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9228*FLEN/8, x3, x1, x4) + +inst_3111: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8400; +op3val:0xfc00; valaddr_reg:x2; val_offset:9231*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9231*FLEN/8, x3, x1, x4) + +inst_3112: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8400; +op3val:0x7e00; valaddr_reg:x2; val_offset:9234*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9234*FLEN/8, x3, x1, x4) + +inst_3113: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8400; +op3val:0xfe00; valaddr_reg:x2; val_offset:9237*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9237*FLEN/8, x3, x1, x4) + +inst_3114: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8400; +op3val:0x7e01; valaddr_reg:x2; val_offset:9240*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9240*FLEN/8, x3, x1, x4) + +inst_3115: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8400; +op3val:0xfe55; valaddr_reg:x2; val_offset:9243*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9243*FLEN/8, x3, x1, x4) + +inst_3116: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8400; +op3val:0x7c01; valaddr_reg:x2; val_offset:9246*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9246*FLEN/8, x3, x1, x4) + +inst_3117: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8400; +op3val:0xfd55; valaddr_reg:x2; val_offset:9249*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9249*FLEN/8, x3, x1, x4) + +inst_3118: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8400; +op3val:0x3c00; valaddr_reg:x2; val_offset:9252*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9252*FLEN/8, x3, x1, x4) + +inst_3119: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8400; +op3val:0xbc00; valaddr_reg:x2; val_offset:9255*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9255*FLEN/8, x3, x1, x4) + +inst_3120: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x401; +op3val:0x0; valaddr_reg:x2; val_offset:9258*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9258*FLEN/8, x3, x1, x4) + +inst_3121: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x401; +op3val:0x8000; valaddr_reg:x2; val_offset:9261*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9261*FLEN/8, x3, x1, x4) + +inst_3122: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x401; +op3val:0x1; valaddr_reg:x2; val_offset:9264*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9264*FLEN/8, x3, x1, x4) + +inst_3123: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x401; +op3val:0x8001; valaddr_reg:x2; val_offset:9267*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9267*FLEN/8, x3, x1, x4) + +inst_3124: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x401; +op3val:0x2; valaddr_reg:x2; val_offset:9270*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9270*FLEN/8, x3, x1, x4) + +inst_3125: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x401; +op3val:0x83fe; valaddr_reg:x2; val_offset:9273*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9273*FLEN/8, x3, x1, x4) + +inst_3126: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x401; +op3val:0x3ff; valaddr_reg:x2; val_offset:9276*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9276*FLEN/8, x3, x1, x4) + +inst_3127: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x401; +op3val:0x83ff; valaddr_reg:x2; val_offset:9279*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9279*FLEN/8, x3, x1, x4) + +inst_3128: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x401; +op3val:0x400; valaddr_reg:x2; val_offset:9282*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9282*FLEN/8, x3, x1, x4) + +inst_3129: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x401; +op3val:0x8400; valaddr_reg:x2; val_offset:9285*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9285*FLEN/8, x3, x1, x4) + +inst_3130: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x401; +op3val:0x401; valaddr_reg:x2; val_offset:9288*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9288*FLEN/8, x3, x1, x4) + +inst_3131: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x401; +op3val:0x8455; valaddr_reg:x2; val_offset:9291*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9291*FLEN/8, x3, x1, x4) + +inst_3132: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x401; +op3val:0x7bff; valaddr_reg:x2; val_offset:9294*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9294*FLEN/8, x3, x1, x4) + +inst_3133: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x401; +op3val:0xfbff; valaddr_reg:x2; val_offset:9297*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9297*FLEN/8, x3, x1, x4) + +inst_3134: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x401; +op3val:0x7c00; valaddr_reg:x2; val_offset:9300*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9300*FLEN/8, x3, x1, x4) + +inst_3135: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x401; +op3val:0xfc00; valaddr_reg:x2; val_offset:9303*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9303*FLEN/8, x3, x1, x4) + +inst_3136: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x401; +op3val:0x7e00; valaddr_reg:x2; val_offset:9306*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9306*FLEN/8, x3, x1, x4) + +inst_3137: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x401; +op3val:0xfe00; valaddr_reg:x2; val_offset:9309*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9309*FLEN/8, x3, x1, x4) + +inst_3138: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x401; +op3val:0x7e01; valaddr_reg:x2; val_offset:9312*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9312*FLEN/8, x3, x1, x4) + +inst_3139: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x401; +op3val:0xfe55; valaddr_reg:x2; val_offset:9315*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9315*FLEN/8, x3, x1, x4) + +inst_3140: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x401; +op3val:0x7c01; valaddr_reg:x2; val_offset:9318*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9318*FLEN/8, x3, x1, x4) + +inst_3141: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x401; +op3val:0xfd55; valaddr_reg:x2; val_offset:9321*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9321*FLEN/8, x3, x1, x4) + +inst_3142: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x401; +op3val:0x3c00; valaddr_reg:x2; val_offset:9324*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9324*FLEN/8, x3, x1, x4) + +inst_3143: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x401; +op3val:0xbc00; valaddr_reg:x2; val_offset:9327*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9327*FLEN/8, x3, x1, x4) + +inst_3144: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8455; +op3val:0x0; valaddr_reg:x2; val_offset:9330*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9330*FLEN/8, x3, x1, x4) + +inst_3145: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8455; +op3val:0x8000; valaddr_reg:x2; val_offset:9333*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9333*FLEN/8, x3, x1, x4) + +inst_3146: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8455; +op3val:0x1; valaddr_reg:x2; val_offset:9336*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9336*FLEN/8, x3, x1, x4) + +inst_3147: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8455; +op3val:0x8001; valaddr_reg:x2; val_offset:9339*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9339*FLEN/8, x3, x1, x4) + +inst_3148: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8455; +op3val:0x2; valaddr_reg:x2; val_offset:9342*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9342*FLEN/8, x3, x1, x4) + +inst_3149: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8455; +op3val:0x83fe; valaddr_reg:x2; val_offset:9345*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9345*FLEN/8, x3, x1, x4) + +inst_3150: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8455; +op3val:0x3ff; valaddr_reg:x2; val_offset:9348*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9348*FLEN/8, x3, x1, x4) + +inst_3151: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8455; +op3val:0x83ff; valaddr_reg:x2; val_offset:9351*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9351*FLEN/8, x3, x1, x4) + +inst_3152: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8455; +op3val:0x400; valaddr_reg:x2; val_offset:9354*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9354*FLEN/8, x3, x1, x4) + +inst_3153: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8455; +op3val:0x8400; valaddr_reg:x2; val_offset:9357*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9357*FLEN/8, x3, x1, x4) + +inst_3154: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8455; +op3val:0x401; valaddr_reg:x2; val_offset:9360*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9360*FLEN/8, x3, x1, x4) + +inst_3155: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8455; +op3val:0x8455; valaddr_reg:x2; val_offset:9363*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9363*FLEN/8, x3, x1, x4) + +inst_3156: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8455; +op3val:0x7bff; valaddr_reg:x2; val_offset:9366*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9366*FLEN/8, x3, x1, x4) + +inst_3157: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8455; +op3val:0xfbff; valaddr_reg:x2; val_offset:9369*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9369*FLEN/8, x3, x1, x4) + +inst_3158: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8455; +op3val:0x7c00; valaddr_reg:x2; val_offset:9372*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9372*FLEN/8, x3, x1, x4) + +inst_3159: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8455; +op3val:0xfc00; valaddr_reg:x2; val_offset:9375*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9375*FLEN/8, x3, x1, x4) + +inst_3160: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8455; +op3val:0x7e00; valaddr_reg:x2; val_offset:9378*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9378*FLEN/8, x3, x1, x4) + +inst_3161: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8455; +op3val:0xfe00; valaddr_reg:x2; val_offset:9381*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9381*FLEN/8, x3, x1, x4) + +inst_3162: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8455; +op3val:0x7e01; valaddr_reg:x2; val_offset:9384*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9384*FLEN/8, x3, x1, x4) + +inst_3163: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8455; +op3val:0xfe55; valaddr_reg:x2; val_offset:9387*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9387*FLEN/8, x3, x1, x4) + +inst_3164: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8455; +op3val:0x7c01; valaddr_reg:x2; val_offset:9390*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9390*FLEN/8, x3, x1, x4) + +inst_3165: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8455; +op3val:0xfd55; valaddr_reg:x2; val_offset:9393*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9393*FLEN/8, x3, x1, x4) + +inst_3166: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8455; +op3val:0x3c00; valaddr_reg:x2; val_offset:9396*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9396*FLEN/8, x3, x1, x4) + +inst_3167: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x8455; +op3val:0xbc00; valaddr_reg:x2; val_offset:9399*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9399*FLEN/8, x3, x1, x4) + +inst_3168: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7bff; +op3val:0x0; valaddr_reg:x2; val_offset:9402*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9402*FLEN/8, x3, x1, x4) + +inst_3169: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7bff; +op3val:0x8000; valaddr_reg:x2; val_offset:9405*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9405*FLEN/8, x3, x1, x4) + +inst_3170: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7bff; +op3val:0x1; valaddr_reg:x2; val_offset:9408*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9408*FLEN/8, x3, x1, x4) + +inst_3171: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7bff; +op3val:0x8001; valaddr_reg:x2; val_offset:9411*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9411*FLEN/8, x3, x1, x4) + +inst_3172: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7bff; +op3val:0x2; valaddr_reg:x2; val_offset:9414*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9414*FLEN/8, x3, x1, x4) + +inst_3173: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7bff; +op3val:0x83fe; valaddr_reg:x2; val_offset:9417*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9417*FLEN/8, x3, x1, x4) + +inst_3174: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7bff; +op3val:0x3ff; valaddr_reg:x2; val_offset:9420*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9420*FLEN/8, x3, x1, x4) + +inst_3175: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7bff; +op3val:0x83ff; valaddr_reg:x2; val_offset:9423*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9423*FLEN/8, x3, x1, x4) + +inst_3176: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7bff; +op3val:0x400; valaddr_reg:x2; val_offset:9426*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9426*FLEN/8, x3, x1, x4) + +inst_3177: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7bff; +op3val:0x8400; valaddr_reg:x2; val_offset:9429*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9429*FLEN/8, x3, x1, x4) + +inst_3178: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7bff; +op3val:0x401; valaddr_reg:x2; val_offset:9432*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9432*FLEN/8, x3, x1, x4) + +inst_3179: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7bff; +op3val:0x8455; valaddr_reg:x2; val_offset:9435*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9435*FLEN/8, x3, x1, x4) + +inst_3180: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7bff; +op3val:0x7bff; valaddr_reg:x2; val_offset:9438*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9438*FLEN/8, x3, x1, x4) + +inst_3181: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7bff; +op3val:0xfbff; valaddr_reg:x2; val_offset:9441*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9441*FLEN/8, x3, x1, x4) + +inst_3182: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7bff; +op3val:0x7c00; valaddr_reg:x2; val_offset:9444*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9444*FLEN/8, x3, x1, x4) + +inst_3183: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7bff; +op3val:0xfc00; valaddr_reg:x2; val_offset:9447*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9447*FLEN/8, x3, x1, x4) + +inst_3184: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7bff; +op3val:0x7e00; valaddr_reg:x2; val_offset:9450*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9450*FLEN/8, x3, x1, x4) + +inst_3185: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7bff; +op3val:0xfe00; valaddr_reg:x2; val_offset:9453*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9453*FLEN/8, x3, x1, x4) + +inst_3186: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7bff; +op3val:0x7e01; valaddr_reg:x2; val_offset:9456*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9456*FLEN/8, x3, x1, x4) + +inst_3187: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7bff; +op3val:0xfe55; valaddr_reg:x2; val_offset:9459*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9459*FLEN/8, x3, x1, x4) + +inst_3188: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7bff; +op3val:0x7c01; valaddr_reg:x2; val_offset:9462*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9462*FLEN/8, x3, x1, x4) + +inst_3189: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7bff; +op3val:0xfd55; valaddr_reg:x2; val_offset:9465*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9465*FLEN/8, x3, x1, x4) + +inst_3190: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7bff; +op3val:0x3c00; valaddr_reg:x2; val_offset:9468*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9468*FLEN/8, x3, x1, x4) + +inst_3191: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7bff; +op3val:0xbc00; valaddr_reg:x2; val_offset:9471*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9471*FLEN/8, x3, x1, x4) + +inst_3192: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfbff; +op3val:0x0; valaddr_reg:x2; val_offset:9474*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9474*FLEN/8, x3, x1, x4) + +inst_3193: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfbff; +op3val:0x8000; valaddr_reg:x2; val_offset:9477*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9477*FLEN/8, x3, x1, x4) + +inst_3194: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfbff; +op3val:0x1; valaddr_reg:x2; val_offset:9480*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9480*FLEN/8, x3, x1, x4) + +inst_3195: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfbff; +op3val:0x8001; valaddr_reg:x2; val_offset:9483*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9483*FLEN/8, x3, x1, x4) + +inst_3196: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfbff; +op3val:0x2; valaddr_reg:x2; val_offset:9486*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9486*FLEN/8, x3, x1, x4) + +inst_3197: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfbff; +op3val:0x83fe; valaddr_reg:x2; val_offset:9489*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9489*FLEN/8, x3, x1, x4) + +inst_3198: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfbff; +op3val:0x3ff; valaddr_reg:x2; val_offset:9492*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9492*FLEN/8, x3, x1, x4) + +inst_3199: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfbff; +op3val:0x83ff; valaddr_reg:x2; val_offset:9495*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9495*FLEN/8, x3, x1, x4) + +inst_3200: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfbff; +op3val:0x400; valaddr_reg:x2; val_offset:9498*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9498*FLEN/8, x3, x1, x4) + +inst_3201: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfbff; +op3val:0x8400; valaddr_reg:x2; val_offset:9501*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9501*FLEN/8, x3, x1, x4) + +inst_3202: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfbff; +op3val:0x401; valaddr_reg:x2; val_offset:9504*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9504*FLEN/8, x3, x1, x4) + +inst_3203: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfbff; +op3val:0x8455; valaddr_reg:x2; val_offset:9507*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9507*FLEN/8, x3, x1, x4) + +inst_3204: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfbff; +op3val:0x7bff; valaddr_reg:x2; val_offset:9510*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9510*FLEN/8, x3, x1, x4) + +inst_3205: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfbff; +op3val:0xfbff; valaddr_reg:x2; val_offset:9513*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9513*FLEN/8, x3, x1, x4) + +inst_3206: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfbff; +op3val:0x7c00; valaddr_reg:x2; val_offset:9516*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9516*FLEN/8, x3, x1, x4) + +inst_3207: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfbff; +op3val:0xfc00; valaddr_reg:x2; val_offset:9519*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9519*FLEN/8, x3, x1, x4) + +inst_3208: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfbff; +op3val:0x7e00; valaddr_reg:x2; val_offset:9522*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9522*FLEN/8, x3, x1, x4) + +inst_3209: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfbff; +op3val:0xfe00; valaddr_reg:x2; val_offset:9525*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9525*FLEN/8, x3, x1, x4) + +inst_3210: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfbff; +op3val:0x7e01; valaddr_reg:x2; val_offset:9528*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9528*FLEN/8, x3, x1, x4) + +inst_3211: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfbff; +op3val:0xfe55; valaddr_reg:x2; val_offset:9531*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9531*FLEN/8, x3, x1, x4) + +inst_3212: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfbff; +op3val:0x7c01; valaddr_reg:x2; val_offset:9534*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9534*FLEN/8, x3, x1, x4) + +inst_3213: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfbff; +op3val:0xfd55; valaddr_reg:x2; val_offset:9537*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9537*FLEN/8, x3, x1, x4) + +inst_3214: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfbff; +op3val:0x3c00; valaddr_reg:x2; val_offset:9540*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9540*FLEN/8, x3, x1, x4) + +inst_3215: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfbff; +op3val:0xbc00; valaddr_reg:x2; val_offset:9543*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9543*FLEN/8, x3, x1, x4) + +inst_3216: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7c00; +op3val:0x0; valaddr_reg:x2; val_offset:9546*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9546*FLEN/8, x3, x1, x4) + +inst_3217: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7c00; +op3val:0x8000; valaddr_reg:x2; val_offset:9549*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9549*FLEN/8, x3, x1, x4) + +inst_3218: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7c00; +op3val:0x1; valaddr_reg:x2; val_offset:9552*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9552*FLEN/8, x3, x1, x4) + +inst_3219: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7c00; +op3val:0x8001; valaddr_reg:x2; val_offset:9555*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9555*FLEN/8, x3, x1, x4) + +inst_3220: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7c00; +op3val:0x2; valaddr_reg:x2; val_offset:9558*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9558*FLEN/8, x3, x1, x4) + +inst_3221: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7c00; +op3val:0x83fe; valaddr_reg:x2; val_offset:9561*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9561*FLEN/8, x3, x1, x4) + +inst_3222: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7c00; +op3val:0x3ff; valaddr_reg:x2; val_offset:9564*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9564*FLEN/8, x3, x1, x4) + +inst_3223: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7c00; +op3val:0x83ff; valaddr_reg:x2; val_offset:9567*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9567*FLEN/8, x3, x1, x4) + +inst_3224: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7c00; +op3val:0x400; valaddr_reg:x2; val_offset:9570*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9570*FLEN/8, x3, x1, x4) + +inst_3225: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7c00; +op3val:0x8400; valaddr_reg:x2; val_offset:9573*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9573*FLEN/8, x3, x1, x4) + +inst_3226: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7c00; +op3val:0x401; valaddr_reg:x2; val_offset:9576*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9576*FLEN/8, x3, x1, x4) + +inst_3227: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7c00; +op3val:0x8455; valaddr_reg:x2; val_offset:9579*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9579*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_26) + +inst_3228: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7c00; +op3val:0x7bff; valaddr_reg:x2; val_offset:9582*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9582*FLEN/8, x3, x1, x4) + +inst_3229: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7c00; +op3val:0xfbff; valaddr_reg:x2; val_offset:9585*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9585*FLEN/8, x3, x1, x4) + +inst_3230: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7c00; +op3val:0x7c00; valaddr_reg:x2; val_offset:9588*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9588*FLEN/8, x3, x1, x4) + +inst_3231: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7c00; +op3val:0xfc00; valaddr_reg:x2; val_offset:9591*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9591*FLEN/8, x3, x1, x4) + +inst_3232: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7c00; +op3val:0x7e00; valaddr_reg:x2; val_offset:9594*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9594*FLEN/8, x3, x1, x4) + +inst_3233: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7c00; +op3val:0xfe00; valaddr_reg:x2; val_offset:9597*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9597*FLEN/8, x3, x1, x4) + +inst_3234: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7c00; +op3val:0x7e01; valaddr_reg:x2; val_offset:9600*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9600*FLEN/8, x3, x1, x4) + +inst_3235: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7c00; +op3val:0xfe55; valaddr_reg:x2; val_offset:9603*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9603*FLEN/8, x3, x1, x4) + +inst_3236: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7c00; +op3val:0x7c01; valaddr_reg:x2; val_offset:9606*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9606*FLEN/8, x3, x1, x4) + +inst_3237: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7c00; +op3val:0xfd55; valaddr_reg:x2; val_offset:9609*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9609*FLEN/8, x3, x1, x4) + +inst_3238: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7c00; +op3val:0x3c00; valaddr_reg:x2; val_offset:9612*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9612*FLEN/8, x3, x1, x4) + +inst_3239: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7c00; +op3val:0xbc00; valaddr_reg:x2; val_offset:9615*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9615*FLEN/8, x3, x1, x4) + +inst_3240: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfc00; +op3val:0x0; valaddr_reg:x2; val_offset:9618*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9618*FLEN/8, x3, x1, x4) + +inst_3241: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfc00; +op3val:0x8000; valaddr_reg:x2; val_offset:9621*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9621*FLEN/8, x3, x1, x4) + +inst_3242: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfc00; +op3val:0x1; valaddr_reg:x2; val_offset:9624*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9624*FLEN/8, x3, x1, x4) + +inst_3243: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfc00; +op3val:0x8001; valaddr_reg:x2; val_offset:9627*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9627*FLEN/8, x3, x1, x4) + +inst_3244: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfc00; +op3val:0x2; valaddr_reg:x2; val_offset:9630*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9630*FLEN/8, x3, x1, x4) + +inst_3245: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfc00; +op3val:0x83fe; valaddr_reg:x2; val_offset:9633*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9633*FLEN/8, x3, x1, x4) + +inst_3246: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfc00; +op3val:0x3ff; valaddr_reg:x2; val_offset:9636*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9636*FLEN/8, x3, x1, x4) + +inst_3247: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfc00; +op3val:0x83ff; valaddr_reg:x2; val_offset:9639*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9639*FLEN/8, x3, x1, x4) + +inst_3248: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfc00; +op3val:0x400; valaddr_reg:x2; val_offset:9642*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9642*FLEN/8, x3, x1, x4) + +inst_3249: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfc00; +op3val:0x8400; valaddr_reg:x2; val_offset:9645*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9645*FLEN/8, x3, x1, x4) + +inst_3250: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfc00; +op3val:0x401; valaddr_reg:x2; val_offset:9648*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9648*FLEN/8, x3, x1, x4) + +inst_3251: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfc00; +op3val:0x8455; valaddr_reg:x2; val_offset:9651*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9651*FLEN/8, x3, x1, x4) + +inst_3252: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfc00; +op3val:0x7bff; valaddr_reg:x2; val_offset:9654*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9654*FLEN/8, x3, x1, x4) + +inst_3253: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfc00; +op3val:0xfbff; valaddr_reg:x2; val_offset:9657*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9657*FLEN/8, x3, x1, x4) + +inst_3254: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfc00; +op3val:0x7c00; valaddr_reg:x2; val_offset:9660*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9660*FLEN/8, x3, x1, x4) + +inst_3255: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfc00; +op3val:0xfc00; valaddr_reg:x2; val_offset:9663*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9663*FLEN/8, x3, x1, x4) + +inst_3256: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfc00; +op3val:0x7e00; valaddr_reg:x2; val_offset:9666*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9666*FLEN/8, x3, x1, x4) + +inst_3257: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfc00; +op3val:0xfe00; valaddr_reg:x2; val_offset:9669*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9669*FLEN/8, x3, x1, x4) + +inst_3258: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfc00; +op3val:0x7e01; valaddr_reg:x2; val_offset:9672*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9672*FLEN/8, x3, x1, x4) + +inst_3259: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfc00; +op3val:0xfe55; valaddr_reg:x2; val_offset:9675*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9675*FLEN/8, x3, x1, x4) + +inst_3260: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfc00; +op3val:0x7c01; valaddr_reg:x2; val_offset:9678*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9678*FLEN/8, x3, x1, x4) + +inst_3261: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfc00; +op3val:0xfd55; valaddr_reg:x2; val_offset:9681*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9681*FLEN/8, x3, x1, x4) + +inst_3262: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfc00; +op3val:0x3c00; valaddr_reg:x2; val_offset:9684*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9684*FLEN/8, x3, x1, x4) + +inst_3263: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfc00; +op3val:0xbc00; valaddr_reg:x2; val_offset:9687*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9687*FLEN/8, x3, x1, x4) + +inst_3264: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7e00; +op3val:0x0; valaddr_reg:x2; val_offset:9690*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9690*FLEN/8, x3, x1, x4) + +inst_3265: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7e00; +op3val:0x8000; valaddr_reg:x2; val_offset:9693*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9693*FLEN/8, x3, x1, x4) + +inst_3266: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7e00; +op3val:0x1; valaddr_reg:x2; val_offset:9696*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9696*FLEN/8, x3, x1, x4) + +inst_3267: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7e00; +op3val:0x8001; valaddr_reg:x2; val_offset:9699*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9699*FLEN/8, x3, x1, x4) + +inst_3268: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7e00; +op3val:0x2; valaddr_reg:x2; val_offset:9702*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9702*FLEN/8, x3, x1, x4) + +inst_3269: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7e00; +op3val:0x83fe; valaddr_reg:x2; val_offset:9705*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9705*FLEN/8, x3, x1, x4) + +inst_3270: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7e00; +op3val:0x3ff; valaddr_reg:x2; val_offset:9708*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9708*FLEN/8, x3, x1, x4) + +inst_3271: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7e00; +op3val:0x83ff; valaddr_reg:x2; val_offset:9711*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9711*FLEN/8, x3, x1, x4) + +inst_3272: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7e00; +op3val:0x400; valaddr_reg:x2; val_offset:9714*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9714*FLEN/8, x3, x1, x4) + +inst_3273: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7e00; +op3val:0x8400; valaddr_reg:x2; val_offset:9717*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9717*FLEN/8, x3, x1, x4) + +inst_3274: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7e00; +op3val:0x401; valaddr_reg:x2; val_offset:9720*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9720*FLEN/8, x3, x1, x4) + +inst_3275: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7e00; +op3val:0x8455; valaddr_reg:x2; val_offset:9723*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9723*FLEN/8, x3, x1, x4) + +inst_3276: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7e00; +op3val:0x7bff; valaddr_reg:x2; val_offset:9726*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9726*FLEN/8, x3, x1, x4) + +inst_3277: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7e00; +op3val:0xfbff; valaddr_reg:x2; val_offset:9729*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9729*FLEN/8, x3, x1, x4) + +inst_3278: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7e00; +op3val:0x7c00; valaddr_reg:x2; val_offset:9732*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9732*FLEN/8, x3, x1, x4) + +inst_3279: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7e00; +op3val:0xfc00; valaddr_reg:x2; val_offset:9735*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9735*FLEN/8, x3, x1, x4) + +inst_3280: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7e00; +op3val:0x7e00; valaddr_reg:x2; val_offset:9738*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9738*FLEN/8, x3, x1, x4) + +inst_3281: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7e00; +op3val:0xfe00; valaddr_reg:x2; val_offset:9741*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9741*FLEN/8, x3, x1, x4) + +inst_3282: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7e00; +op3val:0x7e01; valaddr_reg:x2; val_offset:9744*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9744*FLEN/8, x3, x1, x4) + +inst_3283: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7e00; +op3val:0xfe55; valaddr_reg:x2; val_offset:9747*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9747*FLEN/8, x3, x1, x4) + +inst_3284: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7e00; +op3val:0x7c01; valaddr_reg:x2; val_offset:9750*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9750*FLEN/8, x3, x1, x4) + +inst_3285: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7e00; +op3val:0xfd55; valaddr_reg:x2; val_offset:9753*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9753*FLEN/8, x3, x1, x4) + +inst_3286: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7e00; +op3val:0x3c00; valaddr_reg:x2; val_offset:9756*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9756*FLEN/8, x3, x1, x4) + +inst_3287: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7e00; +op3val:0xbc00; valaddr_reg:x2; val_offset:9759*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9759*FLEN/8, x3, x1, x4) + +inst_3288: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfe00; +op3val:0x0; valaddr_reg:x2; val_offset:9762*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9762*FLEN/8, x3, x1, x4) + +inst_3289: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfe00; +op3val:0x8000; valaddr_reg:x2; val_offset:9765*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9765*FLEN/8, x3, x1, x4) + +inst_3290: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfe00; +op3val:0x1; valaddr_reg:x2; val_offset:9768*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9768*FLEN/8, x3, x1, x4) + +inst_3291: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfe00; +op3val:0x8001; valaddr_reg:x2; val_offset:9771*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9771*FLEN/8, x3, x1, x4) + +inst_3292: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfe00; +op3val:0x2; valaddr_reg:x2; val_offset:9774*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9774*FLEN/8, x3, x1, x4) + +inst_3293: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfe00; +op3val:0x83fe; valaddr_reg:x2; val_offset:9777*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9777*FLEN/8, x3, x1, x4) + +inst_3294: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfe00; +op3val:0x3ff; valaddr_reg:x2; val_offset:9780*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9780*FLEN/8, x3, x1, x4) + +inst_3295: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfe00; +op3val:0x83ff; valaddr_reg:x2; val_offset:9783*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9783*FLEN/8, x3, x1, x4) + +inst_3296: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfe00; +op3val:0x400; valaddr_reg:x2; val_offset:9786*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9786*FLEN/8, x3, x1, x4) + +inst_3297: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfe00; +op3val:0x8400; valaddr_reg:x2; val_offset:9789*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9789*FLEN/8, x3, x1, x4) + +inst_3298: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfe00; +op3val:0x401; valaddr_reg:x2; val_offset:9792*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9792*FLEN/8, x3, x1, x4) + +inst_3299: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfe00; +op3val:0x8455; valaddr_reg:x2; val_offset:9795*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9795*FLEN/8, x3, x1, x4) + +inst_3300: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfe00; +op3val:0x7bff; valaddr_reg:x2; val_offset:9798*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9798*FLEN/8, x3, x1, x4) + +inst_3301: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfe00; +op3val:0xfbff; valaddr_reg:x2; val_offset:9801*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9801*FLEN/8, x3, x1, x4) + +inst_3302: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfe00; +op3val:0x7c00; valaddr_reg:x2; val_offset:9804*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9804*FLEN/8, x3, x1, x4) + +inst_3303: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfe00; +op3val:0xfc00; valaddr_reg:x2; val_offset:9807*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9807*FLEN/8, x3, x1, x4) + +inst_3304: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfe00; +op3val:0x7e00; valaddr_reg:x2; val_offset:9810*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9810*FLEN/8, x3, x1, x4) + +inst_3305: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfe00; +op3val:0xfe00; valaddr_reg:x2; val_offset:9813*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9813*FLEN/8, x3, x1, x4) + +inst_3306: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfe00; +op3val:0x7e01; valaddr_reg:x2; val_offset:9816*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9816*FLEN/8, x3, x1, x4) + +inst_3307: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfe00; +op3val:0xfe55; valaddr_reg:x2; val_offset:9819*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9819*FLEN/8, x3, x1, x4) + +inst_3308: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfe00; +op3val:0x7c01; valaddr_reg:x2; val_offset:9822*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9822*FLEN/8, x3, x1, x4) + +inst_3309: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfe00; +op3val:0xfd55; valaddr_reg:x2; val_offset:9825*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9825*FLEN/8, x3, x1, x4) + +inst_3310: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfe00; +op3val:0x3c00; valaddr_reg:x2; val_offset:9828*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9828*FLEN/8, x3, x1, x4) + +inst_3311: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfe00; +op3val:0xbc00; valaddr_reg:x2; val_offset:9831*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9831*FLEN/8, x3, x1, x4) + +inst_3312: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7e01; +op3val:0x0; valaddr_reg:x2; val_offset:9834*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9834*FLEN/8, x3, x1, x4) + +inst_3313: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7e01; +op3val:0x8000; valaddr_reg:x2; val_offset:9837*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9837*FLEN/8, x3, x1, x4) + +inst_3314: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7e01; +op3val:0x1; valaddr_reg:x2; val_offset:9840*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9840*FLEN/8, x3, x1, x4) + +inst_3315: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7e01; +op3val:0x8001; valaddr_reg:x2; val_offset:9843*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9843*FLEN/8, x3, x1, x4) + +inst_3316: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7e01; +op3val:0x2; valaddr_reg:x2; val_offset:9846*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9846*FLEN/8, x3, x1, x4) + +inst_3317: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7e01; +op3val:0x83fe; valaddr_reg:x2; val_offset:9849*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9849*FLEN/8, x3, x1, x4) + +inst_3318: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7e01; +op3val:0x3ff; valaddr_reg:x2; val_offset:9852*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9852*FLEN/8, x3, x1, x4) + +inst_3319: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7e01; +op3val:0x83ff; valaddr_reg:x2; val_offset:9855*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9855*FLEN/8, x3, x1, x4) + +inst_3320: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7e01; +op3val:0x400; valaddr_reg:x2; val_offset:9858*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9858*FLEN/8, x3, x1, x4) + +inst_3321: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7e01; +op3val:0x8400; valaddr_reg:x2; val_offset:9861*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9861*FLEN/8, x3, x1, x4) + +inst_3322: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7e01; +op3val:0x401; valaddr_reg:x2; val_offset:9864*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9864*FLEN/8, x3, x1, x4) + +inst_3323: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7e01; +op3val:0x8455; valaddr_reg:x2; val_offset:9867*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9867*FLEN/8, x3, x1, x4) + +inst_3324: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7e01; +op3val:0x7bff; valaddr_reg:x2; val_offset:9870*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9870*FLEN/8, x3, x1, x4) + +inst_3325: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7e01; +op3val:0xfbff; valaddr_reg:x2; val_offset:9873*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9873*FLEN/8, x3, x1, x4) + +inst_3326: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7e01; +op3val:0x7c00; valaddr_reg:x2; val_offset:9876*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9876*FLEN/8, x3, x1, x4) + +inst_3327: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7e01; +op3val:0xfc00; valaddr_reg:x2; val_offset:9879*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9879*FLEN/8, x3, x1, x4) + +inst_3328: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7e01; +op3val:0x7e00; valaddr_reg:x2; val_offset:9882*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9882*FLEN/8, x3, x1, x4) + +inst_3329: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7e01; +op3val:0xfe00; valaddr_reg:x2; val_offset:9885*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9885*FLEN/8, x3, x1, x4) + +inst_3330: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7e01; +op3val:0x7e01; valaddr_reg:x2; val_offset:9888*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9888*FLEN/8, x3, x1, x4) + +inst_3331: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7e01; +op3val:0xfe55; valaddr_reg:x2; val_offset:9891*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9891*FLEN/8, x3, x1, x4) + +inst_3332: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7e01; +op3val:0x7c01; valaddr_reg:x2; val_offset:9894*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9894*FLEN/8, x3, x1, x4) + +inst_3333: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7e01; +op3val:0xfd55; valaddr_reg:x2; val_offset:9897*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9897*FLEN/8, x3, x1, x4) + +inst_3334: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7e01; +op3val:0x3c00; valaddr_reg:x2; val_offset:9900*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9900*FLEN/8, x3, x1, x4) + +inst_3335: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7e01; +op3val:0xbc00; valaddr_reg:x2; val_offset:9903*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9903*FLEN/8, x3, x1, x4) + +inst_3336: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfe55; +op3val:0x0; valaddr_reg:x2; val_offset:9906*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9906*FLEN/8, x3, x1, x4) + +inst_3337: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfe55; +op3val:0x8000; valaddr_reg:x2; val_offset:9909*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9909*FLEN/8, x3, x1, x4) + +inst_3338: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfe55; +op3val:0x1; valaddr_reg:x2; val_offset:9912*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9912*FLEN/8, x3, x1, x4) + +inst_3339: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfe55; +op3val:0x8001; valaddr_reg:x2; val_offset:9915*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9915*FLEN/8, x3, x1, x4) + +inst_3340: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfe55; +op3val:0x2; valaddr_reg:x2; val_offset:9918*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9918*FLEN/8, x3, x1, x4) + +inst_3341: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfe55; +op3val:0x83fe; valaddr_reg:x2; val_offset:9921*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9921*FLEN/8, x3, x1, x4) + +inst_3342: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfe55; +op3val:0x3ff; valaddr_reg:x2; val_offset:9924*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9924*FLEN/8, x3, x1, x4) + +inst_3343: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfe55; +op3val:0x83ff; valaddr_reg:x2; val_offset:9927*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9927*FLEN/8, x3, x1, x4) + +inst_3344: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfe55; +op3val:0x400; valaddr_reg:x2; val_offset:9930*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9930*FLEN/8, x3, x1, x4) + +inst_3345: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfe55; +op3val:0x8400; valaddr_reg:x2; val_offset:9933*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9933*FLEN/8, x3, x1, x4) + +inst_3346: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfe55; +op3val:0x401; valaddr_reg:x2; val_offset:9936*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9936*FLEN/8, x3, x1, x4) + +inst_3347: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfe55; +op3val:0x8455; valaddr_reg:x2; val_offset:9939*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9939*FLEN/8, x3, x1, x4) + +inst_3348: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfe55; +op3val:0x7bff; valaddr_reg:x2; val_offset:9942*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9942*FLEN/8, x3, x1, x4) + +inst_3349: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfe55; +op3val:0xfbff; valaddr_reg:x2; val_offset:9945*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9945*FLEN/8, x3, x1, x4) + +inst_3350: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfe55; +op3val:0x7c00; valaddr_reg:x2; val_offset:9948*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9948*FLEN/8, x3, x1, x4) + +inst_3351: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfe55; +op3val:0xfc00; valaddr_reg:x2; val_offset:9951*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9951*FLEN/8, x3, x1, x4) + +inst_3352: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfe55; +op3val:0x7e00; valaddr_reg:x2; val_offset:9954*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9954*FLEN/8, x3, x1, x4) + +inst_3353: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfe55; +op3val:0xfe00; valaddr_reg:x2; val_offset:9957*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9957*FLEN/8, x3, x1, x4) + +inst_3354: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfe55; +op3val:0x7e01; valaddr_reg:x2; val_offset:9960*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9960*FLEN/8, x3, x1, x4) + +inst_3355: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfe55; +op3val:0xfe55; valaddr_reg:x2; val_offset:9963*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9963*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_27) + +inst_3356: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfe55; +op3val:0x7c01; valaddr_reg:x2; val_offset:9966*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9966*FLEN/8, x3, x1, x4) + +inst_3357: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfe55; +op3val:0xfd55; valaddr_reg:x2; val_offset:9969*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9969*FLEN/8, x3, x1, x4) + +inst_3358: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfe55; +op3val:0x3c00; valaddr_reg:x2; val_offset:9972*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9972*FLEN/8, x3, x1, x4) + +inst_3359: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfe55; +op3val:0xbc00; valaddr_reg:x2; val_offset:9975*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9975*FLEN/8, x3, x1, x4) + +inst_3360: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7c01; +op3val:0x0; valaddr_reg:x2; val_offset:9978*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9978*FLEN/8, x3, x1, x4) + +inst_3361: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7c01; +op3val:0x8000; valaddr_reg:x2; val_offset:9981*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9981*FLEN/8, x3, x1, x4) + +inst_3362: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7c01; +op3val:0x1; valaddr_reg:x2; val_offset:9984*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9984*FLEN/8, x3, x1, x4) + +inst_3363: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7c01; +op3val:0x8001; valaddr_reg:x2; val_offset:9987*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9987*FLEN/8, x3, x1, x4) + +inst_3364: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7c01; +op3val:0x2; valaddr_reg:x2; val_offset:9990*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9990*FLEN/8, x3, x1, x4) + +inst_3365: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7c01; +op3val:0x83fe; valaddr_reg:x2; val_offset:9993*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9993*FLEN/8, x3, x1, x4) + +inst_3366: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7c01; +op3val:0x3ff; valaddr_reg:x2; val_offset:9996*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9996*FLEN/8, x3, x1, x4) + +inst_3367: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7c01; +op3val:0x83ff; valaddr_reg:x2; val_offset:9999*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9999*FLEN/8, x3, x1, x4) + +inst_3368: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7c01; +op3val:0x400; valaddr_reg:x2; val_offset:10002*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10002*FLEN/8, x3, x1, x4) + +inst_3369: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7c01; +op3val:0x8400; valaddr_reg:x2; val_offset:10005*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10005*FLEN/8, x3, x1, x4) + +inst_3370: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7c01; +op3val:0x401; valaddr_reg:x2; val_offset:10008*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10008*FLEN/8, x3, x1, x4) + +inst_3371: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7c01; +op3val:0x8455; valaddr_reg:x2; val_offset:10011*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10011*FLEN/8, x3, x1, x4) + +inst_3372: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7c01; +op3val:0x7bff; valaddr_reg:x2; val_offset:10014*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10014*FLEN/8, x3, x1, x4) + +inst_3373: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7c01; +op3val:0xfbff; valaddr_reg:x2; val_offset:10017*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10017*FLEN/8, x3, x1, x4) + +inst_3374: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7c01; +op3val:0x7c00; valaddr_reg:x2; val_offset:10020*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10020*FLEN/8, x3, x1, x4) + +inst_3375: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7c01; +op3val:0xfc00; valaddr_reg:x2; val_offset:10023*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10023*FLEN/8, x3, x1, x4) + +inst_3376: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7c01; +op3val:0x7e00; valaddr_reg:x2; val_offset:10026*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10026*FLEN/8, x3, x1, x4) + +inst_3377: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7c01; +op3val:0xfe00; valaddr_reg:x2; val_offset:10029*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10029*FLEN/8, x3, x1, x4) + +inst_3378: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7c01; +op3val:0x7e01; valaddr_reg:x2; val_offset:10032*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10032*FLEN/8, x3, x1, x4) + +inst_3379: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7c01; +op3val:0xfe55; valaddr_reg:x2; val_offset:10035*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10035*FLEN/8, x3, x1, x4) + +inst_3380: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7c01; +op3val:0x7c01; valaddr_reg:x2; val_offset:10038*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10038*FLEN/8, x3, x1, x4) + +inst_3381: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7c01; +op3val:0xfd55; valaddr_reg:x2; val_offset:10041*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10041*FLEN/8, x3, x1, x4) + +inst_3382: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7c01; +op3val:0x3c00; valaddr_reg:x2; val_offset:10044*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10044*FLEN/8, x3, x1, x4) + +inst_3383: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x7c01; +op3val:0xbc00; valaddr_reg:x2; val_offset:10047*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10047*FLEN/8, x3, x1, x4) + +inst_3384: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfd55; +op3val:0x0; valaddr_reg:x2; val_offset:10050*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10050*FLEN/8, x3, x1, x4) + +inst_3385: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfd55; +op3val:0x8000; valaddr_reg:x2; val_offset:10053*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10053*FLEN/8, x3, x1, x4) + +inst_3386: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfd55; +op3val:0x1; valaddr_reg:x2; val_offset:10056*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10056*FLEN/8, x3, x1, x4) + +inst_3387: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfd55; +op3val:0x8001; valaddr_reg:x2; val_offset:10059*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10059*FLEN/8, x3, x1, x4) + +inst_3388: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfd55; +op3val:0x2; valaddr_reg:x2; val_offset:10062*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10062*FLEN/8, x3, x1, x4) + +inst_3389: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfd55; +op3val:0x83fe; valaddr_reg:x2; val_offset:10065*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10065*FLEN/8, x3, x1, x4) + +inst_3390: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfd55; +op3val:0x3ff; valaddr_reg:x2; val_offset:10068*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10068*FLEN/8, x3, x1, x4) + +inst_3391: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfd55; +op3val:0x83ff; valaddr_reg:x2; val_offset:10071*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10071*FLEN/8, x3, x1, x4) + +inst_3392: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfd55; +op3val:0x400; valaddr_reg:x2; val_offset:10074*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10074*FLEN/8, x3, x1, x4) + +inst_3393: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfd55; +op3val:0x8400; valaddr_reg:x2; val_offset:10077*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10077*FLEN/8, x3, x1, x4) + +inst_3394: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfd55; +op3val:0x401; valaddr_reg:x2; val_offset:10080*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10080*FLEN/8, x3, x1, x4) + +inst_3395: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfd55; +op3val:0x8455; valaddr_reg:x2; val_offset:10083*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10083*FLEN/8, x3, x1, x4) + +inst_3396: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfd55; +op3val:0x7bff; valaddr_reg:x2; val_offset:10086*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10086*FLEN/8, x3, x1, x4) + +inst_3397: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfd55; +op3val:0xfbff; valaddr_reg:x2; val_offset:10089*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10089*FLEN/8, x3, x1, x4) + +inst_3398: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfd55; +op3val:0x7c00; valaddr_reg:x2; val_offset:10092*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10092*FLEN/8, x3, x1, x4) + +inst_3399: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfd55; +op3val:0xfc00; valaddr_reg:x2; val_offset:10095*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10095*FLEN/8, x3, x1, x4) + +inst_3400: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfd55; +op3val:0x7e00; valaddr_reg:x2; val_offset:10098*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10098*FLEN/8, x3, x1, x4) + +inst_3401: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfd55; +op3val:0xfe00; valaddr_reg:x2; val_offset:10101*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10101*FLEN/8, x3, x1, x4) + +inst_3402: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfd55; +op3val:0x7e01; valaddr_reg:x2; val_offset:10104*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10104*FLEN/8, x3, x1, x4) + +inst_3403: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfd55; +op3val:0xfe55; valaddr_reg:x2; val_offset:10107*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10107*FLEN/8, x3, x1, x4) + +inst_3404: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfd55; +op3val:0x7c01; valaddr_reg:x2; val_offset:10110*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10110*FLEN/8, x3, x1, x4) + +inst_3405: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfd55; +op3val:0xfd55; valaddr_reg:x2; val_offset:10113*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10113*FLEN/8, x3, x1, x4) + +inst_3406: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfd55; +op3val:0x3c00; valaddr_reg:x2; val_offset:10116*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10116*FLEN/8, x3, x1, x4) + +inst_3407: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xfd55; +op3val:0xbc00; valaddr_reg:x2; val_offset:10119*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10119*FLEN/8, x3, x1, x4) + +inst_3408: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x3c00; +op3val:0x0; valaddr_reg:x2; val_offset:10122*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10122*FLEN/8, x3, x1, x4) + +inst_3409: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x3c00; +op3val:0x8000; valaddr_reg:x2; val_offset:10125*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10125*FLEN/8, x3, x1, x4) + +inst_3410: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x3c00; +op3val:0x1; valaddr_reg:x2; val_offset:10128*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10128*FLEN/8, x3, x1, x4) + +inst_3411: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x3c00; +op3val:0x8001; valaddr_reg:x2; val_offset:10131*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10131*FLEN/8, x3, x1, x4) + +inst_3412: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x3c00; +op3val:0x2; valaddr_reg:x2; val_offset:10134*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10134*FLEN/8, x3, x1, x4) + +inst_3413: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x3c00; +op3val:0x83fe; valaddr_reg:x2; val_offset:10137*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10137*FLEN/8, x3, x1, x4) + +inst_3414: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x3c00; +op3val:0x3ff; valaddr_reg:x2; val_offset:10140*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10140*FLEN/8, x3, x1, x4) + +inst_3415: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x3c00; +op3val:0x83ff; valaddr_reg:x2; val_offset:10143*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10143*FLEN/8, x3, x1, x4) + +inst_3416: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x3c00; +op3val:0x400; valaddr_reg:x2; val_offset:10146*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10146*FLEN/8, x3, x1, x4) + +inst_3417: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x3c00; +op3val:0x8400; valaddr_reg:x2; val_offset:10149*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10149*FLEN/8, x3, x1, x4) + +inst_3418: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x3c00; +op3val:0x401; valaddr_reg:x2; val_offset:10152*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10152*FLEN/8, x3, x1, x4) + +inst_3419: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x3c00; +op3val:0x8455; valaddr_reg:x2; val_offset:10155*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10155*FLEN/8, x3, x1, x4) + +inst_3420: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x3c00; +op3val:0x7bff; valaddr_reg:x2; val_offset:10158*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10158*FLEN/8, x3, x1, x4) + +inst_3421: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x3c00; +op3val:0xfbff; valaddr_reg:x2; val_offset:10161*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10161*FLEN/8, x3, x1, x4) + +inst_3422: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x3c00; +op3val:0x7c00; valaddr_reg:x2; val_offset:10164*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10164*FLEN/8, x3, x1, x4) + +inst_3423: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x3c00; +op3val:0xfc00; valaddr_reg:x2; val_offset:10167*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10167*FLEN/8, x3, x1, x4) + +inst_3424: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x3c00; +op3val:0x7e00; valaddr_reg:x2; val_offset:10170*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10170*FLEN/8, x3, x1, x4) + +inst_3425: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x3c00; +op3val:0xfe00; valaddr_reg:x2; val_offset:10173*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10173*FLEN/8, x3, x1, x4) + +inst_3426: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x3c00; +op3val:0x7e01; valaddr_reg:x2; val_offset:10176*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10176*FLEN/8, x3, x1, x4) + +inst_3427: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x3c00; +op3val:0xfe55; valaddr_reg:x2; val_offset:10179*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10179*FLEN/8, x3, x1, x4) + +inst_3428: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x3c00; +op3val:0x7c01; valaddr_reg:x2; val_offset:10182*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10182*FLEN/8, x3, x1, x4) + +inst_3429: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x3c00; +op3val:0xfd55; valaddr_reg:x2; val_offset:10185*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10185*FLEN/8, x3, x1, x4) + +inst_3430: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x3c00; +op3val:0x3c00; valaddr_reg:x2; val_offset:10188*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10188*FLEN/8, x3, x1, x4) + +inst_3431: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0x3c00; +op3val:0xbc00; valaddr_reg:x2; val_offset:10191*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10191*FLEN/8, x3, x1, x4) + +inst_3432: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xbc00; +op3val:0x0; valaddr_reg:x2; val_offset:10194*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10194*FLEN/8, x3, x1, x4) + +inst_3433: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xbc00; +op3val:0x8000; valaddr_reg:x2; val_offset:10197*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10197*FLEN/8, x3, x1, x4) + +inst_3434: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xbc00; +op3val:0x1; valaddr_reg:x2; val_offset:10200*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10200*FLEN/8, x3, x1, x4) + +inst_3435: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xbc00; +op3val:0x8001; valaddr_reg:x2; val_offset:10203*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10203*FLEN/8, x3, x1, x4) + +inst_3436: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xbc00; +op3val:0x2; valaddr_reg:x2; val_offset:10206*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10206*FLEN/8, x3, x1, x4) + +inst_3437: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xbc00; +op3val:0x83fe; valaddr_reg:x2; val_offset:10209*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10209*FLEN/8, x3, x1, x4) + +inst_3438: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xbc00; +op3val:0x3ff; valaddr_reg:x2; val_offset:10212*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10212*FLEN/8, x3, x1, x4) + +inst_3439: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xbc00; +op3val:0x83ff; valaddr_reg:x2; val_offset:10215*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10215*FLEN/8, x3, x1, x4) + +inst_3440: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xbc00; +op3val:0x400; valaddr_reg:x2; val_offset:10218*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10218*FLEN/8, x3, x1, x4) + +inst_3441: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xbc00; +op3val:0x8400; valaddr_reg:x2; val_offset:10221*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10221*FLEN/8, x3, x1, x4) + +inst_3442: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xbc00; +op3val:0x401; valaddr_reg:x2; val_offset:10224*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10224*FLEN/8, x3, x1, x4) + +inst_3443: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xbc00; +op3val:0x8455; valaddr_reg:x2; val_offset:10227*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10227*FLEN/8, x3, x1, x4) + +inst_3444: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xbc00; +op3val:0x7bff; valaddr_reg:x2; val_offset:10230*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10230*FLEN/8, x3, x1, x4) + +inst_3445: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xbc00; +op3val:0xfbff; valaddr_reg:x2; val_offset:10233*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10233*FLEN/8, x3, x1, x4) + +inst_3446: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xbc00; +op3val:0x7c00; valaddr_reg:x2; val_offset:10236*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10236*FLEN/8, x3, x1, x4) + +inst_3447: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xbc00; +op3val:0xfc00; valaddr_reg:x2; val_offset:10239*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10239*FLEN/8, x3, x1, x4) + +inst_3448: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xbc00; +op3val:0x7e00; valaddr_reg:x2; val_offset:10242*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10242*FLEN/8, x3, x1, x4) + +inst_3449: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xbc00; +op3val:0xfe00; valaddr_reg:x2; val_offset:10245*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10245*FLEN/8, x3, x1, x4) + +inst_3450: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xbc00; +op3val:0x7e01; valaddr_reg:x2; val_offset:10248*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10248*FLEN/8, x3, x1, x4) + +inst_3451: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xbc00; +op3val:0xfe55; valaddr_reg:x2; val_offset:10251*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10251*FLEN/8, x3, x1, x4) + +inst_3452: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xbc00; +op3val:0x7c01; valaddr_reg:x2; val_offset:10254*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10254*FLEN/8, x3, x1, x4) + +inst_3453: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xbc00; +op3val:0xfd55; valaddr_reg:x2; val_offset:10257*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10257*FLEN/8, x3, x1, x4) + +inst_3454: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xbc00; +op3val:0x3c00; valaddr_reg:x2; val_offset:10260*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10260*FLEN/8, x3, x1, x4) + +inst_3455: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83fe; op2val:0xbc00; +op3val:0xbc00; valaddr_reg:x2; val_offset:10263*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10263*FLEN/8, x3, x1, x4) + +inst_3456: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x0; +op3val:0x0; valaddr_reg:x2; val_offset:10266*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10266*FLEN/8, x3, x1, x4) + +inst_3457: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x0; +op3val:0x8000; valaddr_reg:x2; val_offset:10269*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10269*FLEN/8, x3, x1, x4) + +inst_3458: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x0; +op3val:0x1; valaddr_reg:x2; val_offset:10272*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10272*FLEN/8, x3, x1, x4) + +inst_3459: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x0; +op3val:0x8001; valaddr_reg:x2; val_offset:10275*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10275*FLEN/8, x3, x1, x4) + +inst_3460: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x0; +op3val:0x2; valaddr_reg:x2; val_offset:10278*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10278*FLEN/8, x3, x1, x4) + +inst_3461: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x0; +op3val:0x83fe; valaddr_reg:x2; val_offset:10281*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10281*FLEN/8, x3, x1, x4) + +inst_3462: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x0; +op3val:0x3ff; valaddr_reg:x2; val_offset:10284*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10284*FLEN/8, x3, x1, x4) + +inst_3463: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x0; +op3val:0x83ff; valaddr_reg:x2; val_offset:10287*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10287*FLEN/8, x3, x1, x4) + +inst_3464: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x0; +op3val:0x400; valaddr_reg:x2; val_offset:10290*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10290*FLEN/8, x3, x1, x4) + +inst_3465: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x0; +op3val:0x8400; valaddr_reg:x2; val_offset:10293*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10293*FLEN/8, x3, x1, x4) + +inst_3466: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x0; +op3val:0x401; valaddr_reg:x2; val_offset:10296*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10296*FLEN/8, x3, x1, x4) + +inst_3467: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x0; +op3val:0x8455; valaddr_reg:x2; val_offset:10299*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10299*FLEN/8, x3, x1, x4) + +inst_3468: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x0; +op3val:0x7bff; valaddr_reg:x2; val_offset:10302*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10302*FLEN/8, x3, x1, x4) + +inst_3469: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x0; +op3val:0xfbff; valaddr_reg:x2; val_offset:10305*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10305*FLEN/8, x3, x1, x4) + +inst_3470: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x0; +op3val:0x7c00; valaddr_reg:x2; val_offset:10308*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10308*FLEN/8, x3, x1, x4) + +inst_3471: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x0; +op3val:0xfc00; valaddr_reg:x2; val_offset:10311*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10311*FLEN/8, x3, x1, x4) + +inst_3472: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x0; +op3val:0x7e00; valaddr_reg:x2; val_offset:10314*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10314*FLEN/8, x3, x1, x4) + +inst_3473: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x0; +op3val:0xfe00; valaddr_reg:x2; val_offset:10317*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10317*FLEN/8, x3, x1, x4) + +inst_3474: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x0; +op3val:0x7e01; valaddr_reg:x2; val_offset:10320*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10320*FLEN/8, x3, x1, x4) + +inst_3475: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x0; +op3val:0xfe55; valaddr_reg:x2; val_offset:10323*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10323*FLEN/8, x3, x1, x4) + +inst_3476: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x0; +op3val:0x7c01; valaddr_reg:x2; val_offset:10326*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10326*FLEN/8, x3, x1, x4) + +inst_3477: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x0; +op3val:0xfd55; valaddr_reg:x2; val_offset:10329*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10329*FLEN/8, x3, x1, x4) + +inst_3478: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x0; +op3val:0x3c00; valaddr_reg:x2; val_offset:10332*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10332*FLEN/8, x3, x1, x4) + +inst_3479: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x0; +op3val:0xbc00; valaddr_reg:x2; val_offset:10335*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10335*FLEN/8, x3, x1, x4) + +inst_3480: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8000; +op3val:0x0; valaddr_reg:x2; val_offset:10338*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10338*FLEN/8, x3, x1, x4) + +inst_3481: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8000; +op3val:0x8000; valaddr_reg:x2; val_offset:10341*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10341*FLEN/8, x3, x1, x4) + +inst_3482: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8000; +op3val:0x1; valaddr_reg:x2; val_offset:10344*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10344*FLEN/8, x3, x1, x4) + +inst_3483: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8000; +op3val:0x8001; valaddr_reg:x2; val_offset:10347*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10347*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_28) + +inst_3484: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8000; +op3val:0x2; valaddr_reg:x2; val_offset:10350*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10350*FLEN/8, x3, x1, x4) + +inst_3485: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8000; +op3val:0x83fe; valaddr_reg:x2; val_offset:10353*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10353*FLEN/8, x3, x1, x4) + +inst_3486: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8000; +op3val:0x3ff; valaddr_reg:x2; val_offset:10356*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10356*FLEN/8, x3, x1, x4) + +inst_3487: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8000; +op3val:0x83ff; valaddr_reg:x2; val_offset:10359*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10359*FLEN/8, x3, x1, x4) + +inst_3488: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8000; +op3val:0x400; valaddr_reg:x2; val_offset:10362*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10362*FLEN/8, x3, x1, x4) + +inst_3489: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8000; +op3val:0x8400; valaddr_reg:x2; val_offset:10365*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10365*FLEN/8, x3, x1, x4) + +inst_3490: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8000; +op3val:0x401; valaddr_reg:x2; val_offset:10368*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10368*FLEN/8, x3, x1, x4) + +inst_3491: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8000; +op3val:0x8455; valaddr_reg:x2; val_offset:10371*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10371*FLEN/8, x3, x1, x4) + +inst_3492: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x2; val_offset:10374*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10374*FLEN/8, x3, x1, x4) + +inst_3493: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x2; val_offset:10377*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10377*FLEN/8, x3, x1, x4) + +inst_3494: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8000; +op3val:0x7c00; valaddr_reg:x2; val_offset:10380*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10380*FLEN/8, x3, x1, x4) + +inst_3495: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8000; +op3val:0xfc00; valaddr_reg:x2; val_offset:10383*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10383*FLEN/8, x3, x1, x4) + +inst_3496: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8000; +op3val:0x7e00; valaddr_reg:x2; val_offset:10386*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10386*FLEN/8, x3, x1, x4) + +inst_3497: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8000; +op3val:0xfe00; valaddr_reg:x2; val_offset:10389*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10389*FLEN/8, x3, x1, x4) + +inst_3498: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8000; +op3val:0x7e01; valaddr_reg:x2; val_offset:10392*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10392*FLEN/8, x3, x1, x4) + +inst_3499: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8000; +op3val:0xfe55; valaddr_reg:x2; val_offset:10395*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10395*FLEN/8, x3, x1, x4) + +inst_3500: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8000; +op3val:0x7c01; valaddr_reg:x2; val_offset:10398*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10398*FLEN/8, x3, x1, x4) + +inst_3501: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8000; +op3val:0xfd55; valaddr_reg:x2; val_offset:10401*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10401*FLEN/8, x3, x1, x4) + +inst_3502: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8000; +op3val:0x3c00; valaddr_reg:x2; val_offset:10404*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10404*FLEN/8, x3, x1, x4) + +inst_3503: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8000; +op3val:0xbc00; valaddr_reg:x2; val_offset:10407*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10407*FLEN/8, x3, x1, x4) + +inst_3504: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x1; +op3val:0x0; valaddr_reg:x2; val_offset:10410*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10410*FLEN/8, x3, x1, x4) + +inst_3505: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x1; +op3val:0x8000; valaddr_reg:x2; val_offset:10413*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10413*FLEN/8, x3, x1, x4) + +inst_3506: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x1; +op3val:0x1; valaddr_reg:x2; val_offset:10416*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10416*FLEN/8, x3, x1, x4) + +inst_3507: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x1; +op3val:0x8001; valaddr_reg:x2; val_offset:10419*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10419*FLEN/8, x3, x1, x4) + +inst_3508: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x1; +op3val:0x2; valaddr_reg:x2; val_offset:10422*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10422*FLEN/8, x3, x1, x4) + +inst_3509: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x1; +op3val:0x83fe; valaddr_reg:x2; val_offset:10425*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10425*FLEN/8, x3, x1, x4) + +inst_3510: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x1; +op3val:0x3ff; valaddr_reg:x2; val_offset:10428*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10428*FLEN/8, x3, x1, x4) + +inst_3511: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x1; +op3val:0x83ff; valaddr_reg:x2; val_offset:10431*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10431*FLEN/8, x3, x1, x4) + +inst_3512: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x1; +op3val:0x400; valaddr_reg:x2; val_offset:10434*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10434*FLEN/8, x3, x1, x4) + +inst_3513: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x1; +op3val:0x8400; valaddr_reg:x2; val_offset:10437*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10437*FLEN/8, x3, x1, x4) + +inst_3514: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x1; +op3val:0x401; valaddr_reg:x2; val_offset:10440*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10440*FLEN/8, x3, x1, x4) + +inst_3515: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x1; +op3val:0x8455; valaddr_reg:x2; val_offset:10443*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10443*FLEN/8, x3, x1, x4) + +inst_3516: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x1; +op3val:0x7bff; valaddr_reg:x2; val_offset:10446*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10446*FLEN/8, x3, x1, x4) + +inst_3517: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x1; +op3val:0xfbff; valaddr_reg:x2; val_offset:10449*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10449*FLEN/8, x3, x1, x4) + +inst_3518: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x1; +op3val:0x7c00; valaddr_reg:x2; val_offset:10452*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10452*FLEN/8, x3, x1, x4) + +inst_3519: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x1; +op3val:0xfc00; valaddr_reg:x2; val_offset:10455*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10455*FLEN/8, x3, x1, x4) + +inst_3520: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x1; +op3val:0x7e00; valaddr_reg:x2; val_offset:10458*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10458*FLEN/8, x3, x1, x4) + +inst_3521: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x1; +op3val:0xfe00; valaddr_reg:x2; val_offset:10461*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10461*FLEN/8, x3, x1, x4) + +inst_3522: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x1; +op3val:0x7e01; valaddr_reg:x2; val_offset:10464*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10464*FLEN/8, x3, x1, x4) + +inst_3523: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x1; +op3val:0xfe55; valaddr_reg:x2; val_offset:10467*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10467*FLEN/8, x3, x1, x4) + +inst_3524: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x1; +op3val:0x7c01; valaddr_reg:x2; val_offset:10470*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10470*FLEN/8, x3, x1, x4) + +inst_3525: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x1; +op3val:0xfd55; valaddr_reg:x2; val_offset:10473*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10473*FLEN/8, x3, x1, x4) + +inst_3526: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x1; +op3val:0x3c00; valaddr_reg:x2; val_offset:10476*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10476*FLEN/8, x3, x1, x4) + +inst_3527: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x1; +op3val:0xbc00; valaddr_reg:x2; val_offset:10479*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10479*FLEN/8, x3, x1, x4) + +inst_3528: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8001; +op3val:0x0; valaddr_reg:x2; val_offset:10482*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10482*FLEN/8, x3, x1, x4) + +inst_3529: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8001; +op3val:0x8000; valaddr_reg:x2; val_offset:10485*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10485*FLEN/8, x3, x1, x4) + +inst_3530: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8001; +op3val:0x1; valaddr_reg:x2; val_offset:10488*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10488*FLEN/8, x3, x1, x4) + +inst_3531: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8001; +op3val:0x8001; valaddr_reg:x2; val_offset:10491*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10491*FLEN/8, x3, x1, x4) + +inst_3532: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8001; +op3val:0x2; valaddr_reg:x2; val_offset:10494*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10494*FLEN/8, x3, x1, x4) + +inst_3533: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8001; +op3val:0x83fe; valaddr_reg:x2; val_offset:10497*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10497*FLEN/8, x3, x1, x4) + +inst_3534: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8001; +op3val:0x3ff; valaddr_reg:x2; val_offset:10500*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10500*FLEN/8, x3, x1, x4) + +inst_3535: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8001; +op3val:0x83ff; valaddr_reg:x2; val_offset:10503*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10503*FLEN/8, x3, x1, x4) + +inst_3536: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8001; +op3val:0x400; valaddr_reg:x2; val_offset:10506*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10506*FLEN/8, x3, x1, x4) + +inst_3537: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8001; +op3val:0x8400; valaddr_reg:x2; val_offset:10509*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10509*FLEN/8, x3, x1, x4) + +inst_3538: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8001; +op3val:0x401; valaddr_reg:x2; val_offset:10512*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10512*FLEN/8, x3, x1, x4) + +inst_3539: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8001; +op3val:0x8455; valaddr_reg:x2; val_offset:10515*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10515*FLEN/8, x3, x1, x4) + +inst_3540: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8001; +op3val:0x7bff; valaddr_reg:x2; val_offset:10518*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10518*FLEN/8, x3, x1, x4) + +inst_3541: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8001; +op3val:0xfbff; valaddr_reg:x2; val_offset:10521*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10521*FLEN/8, x3, x1, x4) + +inst_3542: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8001; +op3val:0x7c00; valaddr_reg:x2; val_offset:10524*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10524*FLEN/8, x3, x1, x4) + +inst_3543: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8001; +op3val:0xfc00; valaddr_reg:x2; val_offset:10527*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10527*FLEN/8, x3, x1, x4) + +inst_3544: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8001; +op3val:0x7e00; valaddr_reg:x2; val_offset:10530*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10530*FLEN/8, x3, x1, x4) + +inst_3545: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8001; +op3val:0xfe00; valaddr_reg:x2; val_offset:10533*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10533*FLEN/8, x3, x1, x4) + +inst_3546: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8001; +op3val:0x7e01; valaddr_reg:x2; val_offset:10536*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10536*FLEN/8, x3, x1, x4) + +inst_3547: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8001; +op3val:0xfe55; valaddr_reg:x2; val_offset:10539*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10539*FLEN/8, x3, x1, x4) + +inst_3548: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8001; +op3val:0x7c01; valaddr_reg:x2; val_offset:10542*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10542*FLEN/8, x3, x1, x4) + +inst_3549: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8001; +op3val:0xfd55; valaddr_reg:x2; val_offset:10545*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10545*FLEN/8, x3, x1, x4) + +inst_3550: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8001; +op3val:0x3c00; valaddr_reg:x2; val_offset:10548*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10548*FLEN/8, x3, x1, x4) + +inst_3551: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8001; +op3val:0xbc00; valaddr_reg:x2; val_offset:10551*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10551*FLEN/8, x3, x1, x4) + +inst_3552: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x2; +op3val:0x0; valaddr_reg:x2; val_offset:10554*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10554*FLEN/8, x3, x1, x4) + +inst_3553: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x2; +op3val:0x8000; valaddr_reg:x2; val_offset:10557*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10557*FLEN/8, x3, x1, x4) + +inst_3554: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x2; +op3val:0x1; valaddr_reg:x2; val_offset:10560*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10560*FLEN/8, x3, x1, x4) + +inst_3555: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x2; +op3val:0x8001; valaddr_reg:x2; val_offset:10563*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10563*FLEN/8, x3, x1, x4) + +inst_3556: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x2; +op3val:0x2; valaddr_reg:x2; val_offset:10566*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10566*FLEN/8, x3, x1, x4) + +inst_3557: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x2; +op3val:0x83fe; valaddr_reg:x2; val_offset:10569*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10569*FLEN/8, x3, x1, x4) + +inst_3558: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x2; +op3val:0x3ff; valaddr_reg:x2; val_offset:10572*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10572*FLEN/8, x3, x1, x4) + +inst_3559: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x2; +op3val:0x83ff; valaddr_reg:x2; val_offset:10575*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10575*FLEN/8, x3, x1, x4) + +inst_3560: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x2; +op3val:0x400; valaddr_reg:x2; val_offset:10578*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10578*FLEN/8, x3, x1, x4) + +inst_3561: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x2; +op3val:0x8400; valaddr_reg:x2; val_offset:10581*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10581*FLEN/8, x3, x1, x4) + +inst_3562: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x2; +op3val:0x401; valaddr_reg:x2; val_offset:10584*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10584*FLEN/8, x3, x1, x4) + +inst_3563: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x2; +op3val:0x8455; valaddr_reg:x2; val_offset:10587*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10587*FLEN/8, x3, x1, x4) + +inst_3564: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x2; +op3val:0x7bff; valaddr_reg:x2; val_offset:10590*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10590*FLEN/8, x3, x1, x4) + +inst_3565: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x2; +op3val:0xfbff; valaddr_reg:x2; val_offset:10593*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10593*FLEN/8, x3, x1, x4) + +inst_3566: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x2; +op3val:0x7c00; valaddr_reg:x2; val_offset:10596*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10596*FLEN/8, x3, x1, x4) + +inst_3567: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x2; +op3val:0xfc00; valaddr_reg:x2; val_offset:10599*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10599*FLEN/8, x3, x1, x4) + +inst_3568: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x2; +op3val:0x7e00; valaddr_reg:x2; val_offset:10602*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10602*FLEN/8, x3, x1, x4) + +inst_3569: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x2; +op3val:0xfe00; valaddr_reg:x2; val_offset:10605*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10605*FLEN/8, x3, x1, x4) + +inst_3570: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x2; +op3val:0x7e01; valaddr_reg:x2; val_offset:10608*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10608*FLEN/8, x3, x1, x4) + +inst_3571: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x2; +op3val:0xfe55; valaddr_reg:x2; val_offset:10611*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10611*FLEN/8, x3, x1, x4) + +inst_3572: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x2; +op3val:0x7c01; valaddr_reg:x2; val_offset:10614*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10614*FLEN/8, x3, x1, x4) + +inst_3573: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x2; +op3val:0xfd55; valaddr_reg:x2; val_offset:10617*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10617*FLEN/8, x3, x1, x4) + +inst_3574: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x2; +op3val:0x3c00; valaddr_reg:x2; val_offset:10620*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10620*FLEN/8, x3, x1, x4) + +inst_3575: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x2; +op3val:0xbc00; valaddr_reg:x2; val_offset:10623*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10623*FLEN/8, x3, x1, x4) + +inst_3576: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x83fe; +op3val:0x0; valaddr_reg:x2; val_offset:10626*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10626*FLEN/8, x3, x1, x4) + +inst_3577: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x83fe; +op3val:0x8000; valaddr_reg:x2; val_offset:10629*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10629*FLEN/8, x3, x1, x4) + +inst_3578: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x83fe; +op3val:0x1; valaddr_reg:x2; val_offset:10632*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10632*FLEN/8, x3, x1, x4) + +inst_3579: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x83fe; +op3val:0x8001; valaddr_reg:x2; val_offset:10635*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10635*FLEN/8, x3, x1, x4) + +inst_3580: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x83fe; +op3val:0x2; valaddr_reg:x2; val_offset:10638*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10638*FLEN/8, x3, x1, x4) + +inst_3581: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x83fe; +op3val:0x83fe; valaddr_reg:x2; val_offset:10641*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10641*FLEN/8, x3, x1, x4) + +inst_3582: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x83fe; +op3val:0x3ff; valaddr_reg:x2; val_offset:10644*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10644*FLEN/8, x3, x1, x4) + +inst_3583: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x83fe; +op3val:0x83ff; valaddr_reg:x2; val_offset:10647*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10647*FLEN/8, x3, x1, x4) + +inst_3584: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x83fe; +op3val:0x400; valaddr_reg:x2; val_offset:10650*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10650*FLEN/8, x3, x1, x4) + +inst_3585: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x83fe; +op3val:0x8400; valaddr_reg:x2; val_offset:10653*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10653*FLEN/8, x3, x1, x4) + +inst_3586: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x83fe; +op3val:0x401; valaddr_reg:x2; val_offset:10656*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10656*FLEN/8, x3, x1, x4) + +inst_3587: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x83fe; +op3val:0x8455; valaddr_reg:x2; val_offset:10659*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10659*FLEN/8, x3, x1, x4) + +inst_3588: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x83fe; +op3val:0x7bff; valaddr_reg:x2; val_offset:10662*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10662*FLEN/8, x3, x1, x4) + +inst_3589: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x83fe; +op3val:0xfbff; valaddr_reg:x2; val_offset:10665*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10665*FLEN/8, x3, x1, x4) + +inst_3590: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x83fe; +op3val:0x7c00; valaddr_reg:x2; val_offset:10668*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10668*FLEN/8, x3, x1, x4) + +inst_3591: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x83fe; +op3val:0xfc00; valaddr_reg:x2; val_offset:10671*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10671*FLEN/8, x3, x1, x4) + +inst_3592: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x83fe; +op3val:0x7e00; valaddr_reg:x2; val_offset:10674*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10674*FLEN/8, x3, x1, x4) + +inst_3593: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x83fe; +op3val:0xfe00; valaddr_reg:x2; val_offset:10677*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10677*FLEN/8, x3, x1, x4) + +inst_3594: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x83fe; +op3val:0x7e01; valaddr_reg:x2; val_offset:10680*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10680*FLEN/8, x3, x1, x4) + +inst_3595: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x83fe; +op3val:0xfe55; valaddr_reg:x2; val_offset:10683*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10683*FLEN/8, x3, x1, x4) + +inst_3596: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x83fe; +op3val:0x7c01; valaddr_reg:x2; val_offset:10686*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10686*FLEN/8, x3, x1, x4) + +inst_3597: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x83fe; +op3val:0xfd55; valaddr_reg:x2; val_offset:10689*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10689*FLEN/8, x3, x1, x4) + +inst_3598: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x83fe; +op3val:0x3c00; valaddr_reg:x2; val_offset:10692*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10692*FLEN/8, x3, x1, x4) + +inst_3599: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x83fe; +op3val:0xbc00; valaddr_reg:x2; val_offset:10695*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10695*FLEN/8, x3, x1, x4) + +inst_3600: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x3ff; +op3val:0x0; valaddr_reg:x2; val_offset:10698*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10698*FLEN/8, x3, x1, x4) + +inst_3601: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x3ff; +op3val:0x8000; valaddr_reg:x2; val_offset:10701*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10701*FLEN/8, x3, x1, x4) + +inst_3602: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x3ff; +op3val:0x1; valaddr_reg:x2; val_offset:10704*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10704*FLEN/8, x3, x1, x4) + +inst_3603: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x3ff; +op3val:0x8001; valaddr_reg:x2; val_offset:10707*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10707*FLEN/8, x3, x1, x4) + +inst_3604: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x3ff; +op3val:0x2; valaddr_reg:x2; val_offset:10710*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10710*FLEN/8, x3, x1, x4) + +inst_3605: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x3ff; +op3val:0x83fe; valaddr_reg:x2; val_offset:10713*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10713*FLEN/8, x3, x1, x4) + +inst_3606: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x3ff; +op3val:0x3ff; valaddr_reg:x2; val_offset:10716*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10716*FLEN/8, x3, x1, x4) + +inst_3607: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x3ff; +op3val:0x83ff; valaddr_reg:x2; val_offset:10719*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10719*FLEN/8, x3, x1, x4) + +inst_3608: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x3ff; +op3val:0x400; valaddr_reg:x2; val_offset:10722*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10722*FLEN/8, x3, x1, x4) + +inst_3609: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x3ff; +op3val:0x8400; valaddr_reg:x2; val_offset:10725*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10725*FLEN/8, x3, x1, x4) + +inst_3610: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x3ff; +op3val:0x401; valaddr_reg:x2; val_offset:10728*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10728*FLEN/8, x3, x1, x4) + +inst_3611: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x3ff; +op3val:0x8455; valaddr_reg:x2; val_offset:10731*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10731*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_29) + +inst_3612: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x3ff; +op3val:0x7bff; valaddr_reg:x2; val_offset:10734*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10734*FLEN/8, x3, x1, x4) + +inst_3613: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x3ff; +op3val:0xfbff; valaddr_reg:x2; val_offset:10737*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10737*FLEN/8, x3, x1, x4) + +inst_3614: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x3ff; +op3val:0x7c00; valaddr_reg:x2; val_offset:10740*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10740*FLEN/8, x3, x1, x4) + +inst_3615: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x3ff; +op3val:0xfc00; valaddr_reg:x2; val_offset:10743*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10743*FLEN/8, x3, x1, x4) + +inst_3616: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x3ff; +op3val:0x7e00; valaddr_reg:x2; val_offset:10746*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10746*FLEN/8, x3, x1, x4) + +inst_3617: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x3ff; +op3val:0xfe00; valaddr_reg:x2; val_offset:10749*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10749*FLEN/8, x3, x1, x4) + +inst_3618: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x3ff; +op3val:0x7e01; valaddr_reg:x2; val_offset:10752*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10752*FLEN/8, x3, x1, x4) + +inst_3619: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x3ff; +op3val:0xfe55; valaddr_reg:x2; val_offset:10755*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10755*FLEN/8, x3, x1, x4) + +inst_3620: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x3ff; +op3val:0x7c01; valaddr_reg:x2; val_offset:10758*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10758*FLEN/8, x3, x1, x4) + +inst_3621: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x3ff; +op3val:0xfd55; valaddr_reg:x2; val_offset:10761*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10761*FLEN/8, x3, x1, x4) + +inst_3622: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x3ff; +op3val:0x3c00; valaddr_reg:x2; val_offset:10764*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10764*FLEN/8, x3, x1, x4) + +inst_3623: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x3ff; +op3val:0xbc00; valaddr_reg:x2; val_offset:10767*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10767*FLEN/8, x3, x1, x4) + +inst_3624: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x83ff; +op3val:0x0; valaddr_reg:x2; val_offset:10770*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10770*FLEN/8, x3, x1, x4) + +inst_3625: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x83ff; +op3val:0x8000; valaddr_reg:x2; val_offset:10773*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10773*FLEN/8, x3, x1, x4) + +inst_3626: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x83ff; +op3val:0x1; valaddr_reg:x2; val_offset:10776*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10776*FLEN/8, x3, x1, x4) + +inst_3627: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x83ff; +op3val:0x8001; valaddr_reg:x2; val_offset:10779*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10779*FLEN/8, x3, x1, x4) + +inst_3628: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x83ff; +op3val:0x2; valaddr_reg:x2; val_offset:10782*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10782*FLEN/8, x3, x1, x4) + +inst_3629: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x83ff; +op3val:0x83fe; valaddr_reg:x2; val_offset:10785*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10785*FLEN/8, x3, x1, x4) + +inst_3630: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x83ff; +op3val:0x3ff; valaddr_reg:x2; val_offset:10788*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10788*FLEN/8, x3, x1, x4) + +inst_3631: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x83ff; +op3val:0x83ff; valaddr_reg:x2; val_offset:10791*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10791*FLEN/8, x3, x1, x4) + +inst_3632: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x83ff; +op3val:0x400; valaddr_reg:x2; val_offset:10794*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10794*FLEN/8, x3, x1, x4) + +inst_3633: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x83ff; +op3val:0x8400; valaddr_reg:x2; val_offset:10797*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10797*FLEN/8, x3, x1, x4) + +inst_3634: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x83ff; +op3val:0x401; valaddr_reg:x2; val_offset:10800*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10800*FLEN/8, x3, x1, x4) + +inst_3635: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x83ff; +op3val:0x8455; valaddr_reg:x2; val_offset:10803*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10803*FLEN/8, x3, x1, x4) + +inst_3636: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x83ff; +op3val:0x7bff; valaddr_reg:x2; val_offset:10806*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10806*FLEN/8, x3, x1, x4) + +inst_3637: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x83ff; +op3val:0xfbff; valaddr_reg:x2; val_offset:10809*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10809*FLEN/8, x3, x1, x4) + +inst_3638: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x83ff; +op3val:0x7c00; valaddr_reg:x2; val_offset:10812*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10812*FLEN/8, x3, x1, x4) + +inst_3639: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x83ff; +op3val:0xfc00; valaddr_reg:x2; val_offset:10815*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10815*FLEN/8, x3, x1, x4) + +inst_3640: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x83ff; +op3val:0x7e00; valaddr_reg:x2; val_offset:10818*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10818*FLEN/8, x3, x1, x4) + +inst_3641: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x83ff; +op3val:0xfe00; valaddr_reg:x2; val_offset:10821*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10821*FLEN/8, x3, x1, x4) + +inst_3642: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x83ff; +op3val:0x7e01; valaddr_reg:x2; val_offset:10824*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10824*FLEN/8, x3, x1, x4) + +inst_3643: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x83ff; +op3val:0xfe55; valaddr_reg:x2; val_offset:10827*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10827*FLEN/8, x3, x1, x4) + +inst_3644: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x83ff; +op3val:0x7c01; valaddr_reg:x2; val_offset:10830*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10830*FLEN/8, x3, x1, x4) + +inst_3645: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x83ff; +op3val:0xfd55; valaddr_reg:x2; val_offset:10833*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10833*FLEN/8, x3, x1, x4) + +inst_3646: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x83ff; +op3val:0x3c00; valaddr_reg:x2; val_offset:10836*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10836*FLEN/8, x3, x1, x4) + +inst_3647: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x83ff; +op3val:0xbc00; valaddr_reg:x2; val_offset:10839*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10839*FLEN/8, x3, x1, x4) + +inst_3648: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x400; +op3val:0x0; valaddr_reg:x2; val_offset:10842*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10842*FLEN/8, x3, x1, x4) + +inst_3649: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x400; +op3val:0x8000; valaddr_reg:x2; val_offset:10845*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10845*FLEN/8, x3, x1, x4) + +inst_3650: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x400; +op3val:0x1; valaddr_reg:x2; val_offset:10848*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10848*FLEN/8, x3, x1, x4) + +inst_3651: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x400; +op3val:0x8001; valaddr_reg:x2; val_offset:10851*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10851*FLEN/8, x3, x1, x4) + +inst_3652: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x400; +op3val:0x2; valaddr_reg:x2; val_offset:10854*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10854*FLEN/8, x3, x1, x4) + +inst_3653: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x400; +op3val:0x83fe; valaddr_reg:x2; val_offset:10857*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10857*FLEN/8, x3, x1, x4) + +inst_3654: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x400; +op3val:0x3ff; valaddr_reg:x2; val_offset:10860*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10860*FLEN/8, x3, x1, x4) + +inst_3655: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x400; +op3val:0x83ff; valaddr_reg:x2; val_offset:10863*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10863*FLEN/8, x3, x1, x4) + +inst_3656: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x400; +op3val:0x400; valaddr_reg:x2; val_offset:10866*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10866*FLEN/8, x3, x1, x4) + +inst_3657: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x400; +op3val:0x8400; valaddr_reg:x2; val_offset:10869*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10869*FLEN/8, x3, x1, x4) + +inst_3658: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x400; +op3val:0x401; valaddr_reg:x2; val_offset:10872*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10872*FLEN/8, x3, x1, x4) + +inst_3659: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x400; +op3val:0x8455; valaddr_reg:x2; val_offset:10875*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10875*FLEN/8, x3, x1, x4) + +inst_3660: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x400; +op3val:0x7bff; valaddr_reg:x2; val_offset:10878*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10878*FLEN/8, x3, x1, x4) + +inst_3661: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x400; +op3val:0xfbff; valaddr_reg:x2; val_offset:10881*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10881*FLEN/8, x3, x1, x4) + +inst_3662: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x400; +op3val:0x7c00; valaddr_reg:x2; val_offset:10884*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10884*FLEN/8, x3, x1, x4) + +inst_3663: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x400; +op3val:0xfc00; valaddr_reg:x2; val_offset:10887*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10887*FLEN/8, x3, x1, x4) + +inst_3664: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x400; +op3val:0x7e00; valaddr_reg:x2; val_offset:10890*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10890*FLEN/8, x3, x1, x4) + +inst_3665: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x400; +op3val:0xfe00; valaddr_reg:x2; val_offset:10893*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10893*FLEN/8, x3, x1, x4) + +inst_3666: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x400; +op3val:0x7e01; valaddr_reg:x2; val_offset:10896*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10896*FLEN/8, x3, x1, x4) + +inst_3667: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x400; +op3val:0xfe55; valaddr_reg:x2; val_offset:10899*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10899*FLEN/8, x3, x1, x4) + +inst_3668: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x400; +op3val:0x7c01; valaddr_reg:x2; val_offset:10902*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10902*FLEN/8, x3, x1, x4) + +inst_3669: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x400; +op3val:0xfd55; valaddr_reg:x2; val_offset:10905*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10905*FLEN/8, x3, x1, x4) + +inst_3670: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x400; +op3val:0x3c00; valaddr_reg:x2; val_offset:10908*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10908*FLEN/8, x3, x1, x4) + +inst_3671: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x400; +op3val:0xbc00; valaddr_reg:x2; val_offset:10911*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10911*FLEN/8, x3, x1, x4) + +inst_3672: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8400; +op3val:0x0; valaddr_reg:x2; val_offset:10914*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10914*FLEN/8, x3, x1, x4) + +inst_3673: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8400; +op3val:0x8000; valaddr_reg:x2; val_offset:10917*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10917*FLEN/8, x3, x1, x4) + +inst_3674: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8400; +op3val:0x1; valaddr_reg:x2; val_offset:10920*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10920*FLEN/8, x3, x1, x4) + +inst_3675: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8400; +op3val:0x8001; valaddr_reg:x2; val_offset:10923*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10923*FLEN/8, x3, x1, x4) + +inst_3676: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8400; +op3val:0x2; valaddr_reg:x2; val_offset:10926*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10926*FLEN/8, x3, x1, x4) + +inst_3677: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8400; +op3val:0x83fe; valaddr_reg:x2; val_offset:10929*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10929*FLEN/8, x3, x1, x4) + +inst_3678: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8400; +op3val:0x3ff; valaddr_reg:x2; val_offset:10932*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10932*FLEN/8, x3, x1, x4) + +inst_3679: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8400; +op3val:0x83ff; valaddr_reg:x2; val_offset:10935*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10935*FLEN/8, x3, x1, x4) + +inst_3680: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8400; +op3val:0x400; valaddr_reg:x2; val_offset:10938*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10938*FLEN/8, x3, x1, x4) + +inst_3681: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8400; +op3val:0x8400; valaddr_reg:x2; val_offset:10941*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10941*FLEN/8, x3, x1, x4) + +inst_3682: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8400; +op3val:0x401; valaddr_reg:x2; val_offset:10944*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10944*FLEN/8, x3, x1, x4) + +inst_3683: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8400; +op3val:0x8455; valaddr_reg:x2; val_offset:10947*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10947*FLEN/8, x3, x1, x4) + +inst_3684: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8400; +op3val:0x7bff; valaddr_reg:x2; val_offset:10950*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10950*FLEN/8, x3, x1, x4) + +inst_3685: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8400; +op3val:0xfbff; valaddr_reg:x2; val_offset:10953*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10953*FLEN/8, x3, x1, x4) + +inst_3686: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8400; +op3val:0x7c00; valaddr_reg:x2; val_offset:10956*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10956*FLEN/8, x3, x1, x4) + +inst_3687: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8400; +op3val:0xfc00; valaddr_reg:x2; val_offset:10959*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10959*FLEN/8, x3, x1, x4) + +inst_3688: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8400; +op3val:0x7e00; valaddr_reg:x2; val_offset:10962*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10962*FLEN/8, x3, x1, x4) + +inst_3689: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8400; +op3val:0xfe00; valaddr_reg:x2; val_offset:10965*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10965*FLEN/8, x3, x1, x4) + +inst_3690: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8400; +op3val:0x7e01; valaddr_reg:x2; val_offset:10968*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10968*FLEN/8, x3, x1, x4) + +inst_3691: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8400; +op3val:0xfe55; valaddr_reg:x2; val_offset:10971*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10971*FLEN/8, x3, x1, x4) + +inst_3692: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8400; +op3val:0x7c01; valaddr_reg:x2; val_offset:10974*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10974*FLEN/8, x3, x1, x4) + +inst_3693: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8400; +op3val:0xfd55; valaddr_reg:x2; val_offset:10977*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10977*FLEN/8, x3, x1, x4) + +inst_3694: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8400; +op3val:0x3c00; valaddr_reg:x2; val_offset:10980*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10980*FLEN/8, x3, x1, x4) + +inst_3695: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8400; +op3val:0xbc00; valaddr_reg:x2; val_offset:10983*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10983*FLEN/8, x3, x1, x4) + +inst_3696: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x401; +op3val:0x0; valaddr_reg:x2; val_offset:10986*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10986*FLEN/8, x3, x1, x4) + +inst_3697: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x401; +op3val:0x8000; valaddr_reg:x2; val_offset:10989*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10989*FLEN/8, x3, x1, x4) + +inst_3698: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x401; +op3val:0x1; valaddr_reg:x2; val_offset:10992*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10992*FLEN/8, x3, x1, x4) + +inst_3699: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x401; +op3val:0x8001; valaddr_reg:x2; val_offset:10995*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10995*FLEN/8, x3, x1, x4) + +inst_3700: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x401; +op3val:0x2; valaddr_reg:x2; val_offset:10998*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 10998*FLEN/8, x3, x1, x4) + +inst_3701: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x401; +op3val:0x83fe; valaddr_reg:x2; val_offset:11001*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11001*FLEN/8, x3, x1, x4) + +inst_3702: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x401; +op3val:0x3ff; valaddr_reg:x2; val_offset:11004*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11004*FLEN/8, x3, x1, x4) + +inst_3703: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x401; +op3val:0x83ff; valaddr_reg:x2; val_offset:11007*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11007*FLEN/8, x3, x1, x4) + +inst_3704: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x401; +op3val:0x400; valaddr_reg:x2; val_offset:11010*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11010*FLEN/8, x3, x1, x4) + +inst_3705: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x401; +op3val:0x8400; valaddr_reg:x2; val_offset:11013*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11013*FLEN/8, x3, x1, x4) + +inst_3706: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x401; +op3val:0x401; valaddr_reg:x2; val_offset:11016*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11016*FLEN/8, x3, x1, x4) + +inst_3707: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x401; +op3val:0x8455; valaddr_reg:x2; val_offset:11019*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11019*FLEN/8, x3, x1, x4) + +inst_3708: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x401; +op3val:0x7bff; valaddr_reg:x2; val_offset:11022*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11022*FLEN/8, x3, x1, x4) + +inst_3709: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x401; +op3val:0xfbff; valaddr_reg:x2; val_offset:11025*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11025*FLEN/8, x3, x1, x4) + +inst_3710: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x401; +op3val:0x7c00; valaddr_reg:x2; val_offset:11028*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11028*FLEN/8, x3, x1, x4) + +inst_3711: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x401; +op3val:0xfc00; valaddr_reg:x2; val_offset:11031*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11031*FLEN/8, x3, x1, x4) + +inst_3712: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x401; +op3val:0x7e00; valaddr_reg:x2; val_offset:11034*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11034*FLEN/8, x3, x1, x4) + +inst_3713: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x401; +op3val:0xfe00; valaddr_reg:x2; val_offset:11037*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11037*FLEN/8, x3, x1, x4) + +inst_3714: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x401; +op3val:0x7e01; valaddr_reg:x2; val_offset:11040*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11040*FLEN/8, x3, x1, x4) + +inst_3715: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x401; +op3val:0xfe55; valaddr_reg:x2; val_offset:11043*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11043*FLEN/8, x3, x1, x4) + +inst_3716: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x401; +op3val:0x7c01; valaddr_reg:x2; val_offset:11046*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11046*FLEN/8, x3, x1, x4) + +inst_3717: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x401; +op3val:0xfd55; valaddr_reg:x2; val_offset:11049*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11049*FLEN/8, x3, x1, x4) + +inst_3718: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x401; +op3val:0x3c00; valaddr_reg:x2; val_offset:11052*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11052*FLEN/8, x3, x1, x4) + +inst_3719: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x401; +op3val:0xbc00; valaddr_reg:x2; val_offset:11055*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11055*FLEN/8, x3, x1, x4) + +inst_3720: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8455; +op3val:0x0; valaddr_reg:x2; val_offset:11058*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11058*FLEN/8, x3, x1, x4) + +inst_3721: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8455; +op3val:0x8000; valaddr_reg:x2; val_offset:11061*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11061*FLEN/8, x3, x1, x4) + +inst_3722: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8455; +op3val:0x1; valaddr_reg:x2; val_offset:11064*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11064*FLEN/8, x3, x1, x4) + +inst_3723: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8455; +op3val:0x8001; valaddr_reg:x2; val_offset:11067*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11067*FLEN/8, x3, x1, x4) + +inst_3724: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8455; +op3val:0x2; valaddr_reg:x2; val_offset:11070*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11070*FLEN/8, x3, x1, x4) + +inst_3725: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8455; +op3val:0x83fe; valaddr_reg:x2; val_offset:11073*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11073*FLEN/8, x3, x1, x4) + +inst_3726: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8455; +op3val:0x3ff; valaddr_reg:x2; val_offset:11076*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11076*FLEN/8, x3, x1, x4) + +inst_3727: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8455; +op3val:0x83ff; valaddr_reg:x2; val_offset:11079*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11079*FLEN/8, x3, x1, x4) + +inst_3728: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8455; +op3val:0x400; valaddr_reg:x2; val_offset:11082*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11082*FLEN/8, x3, x1, x4) + +inst_3729: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8455; +op3val:0x8400; valaddr_reg:x2; val_offset:11085*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11085*FLEN/8, x3, x1, x4) + +inst_3730: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8455; +op3val:0x401; valaddr_reg:x2; val_offset:11088*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11088*FLEN/8, x3, x1, x4) + +inst_3731: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8455; +op3val:0x8455; valaddr_reg:x2; val_offset:11091*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11091*FLEN/8, x3, x1, x4) + +inst_3732: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8455; +op3val:0x7bff; valaddr_reg:x2; val_offset:11094*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11094*FLEN/8, x3, x1, x4) + +inst_3733: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8455; +op3val:0xfbff; valaddr_reg:x2; val_offset:11097*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11097*FLEN/8, x3, x1, x4) + +inst_3734: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8455; +op3val:0x7c00; valaddr_reg:x2; val_offset:11100*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11100*FLEN/8, x3, x1, x4) + +inst_3735: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8455; +op3val:0xfc00; valaddr_reg:x2; val_offset:11103*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11103*FLEN/8, x3, x1, x4) + +inst_3736: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8455; +op3val:0x7e00; valaddr_reg:x2; val_offset:11106*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11106*FLEN/8, x3, x1, x4) + +inst_3737: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8455; +op3val:0xfe00; valaddr_reg:x2; val_offset:11109*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11109*FLEN/8, x3, x1, x4) + +inst_3738: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8455; +op3val:0x7e01; valaddr_reg:x2; val_offset:11112*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11112*FLEN/8, x3, x1, x4) + +inst_3739: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8455; +op3val:0xfe55; valaddr_reg:x2; val_offset:11115*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11115*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_30) + +inst_3740: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8455; +op3val:0x7c01; valaddr_reg:x2; val_offset:11118*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11118*FLEN/8, x3, x1, x4) + +inst_3741: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8455; +op3val:0xfd55; valaddr_reg:x2; val_offset:11121*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11121*FLEN/8, x3, x1, x4) + +inst_3742: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8455; +op3val:0x3c00; valaddr_reg:x2; val_offset:11124*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11124*FLEN/8, x3, x1, x4) + +inst_3743: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x8455; +op3val:0xbc00; valaddr_reg:x2; val_offset:11127*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11127*FLEN/8, x3, x1, x4) + +inst_3744: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7bff; +op3val:0x0; valaddr_reg:x2; val_offset:11130*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11130*FLEN/8, x3, x1, x4) + +inst_3745: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7bff; +op3val:0x8000; valaddr_reg:x2; val_offset:11133*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11133*FLEN/8, x3, x1, x4) + +inst_3746: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7bff; +op3val:0x1; valaddr_reg:x2; val_offset:11136*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11136*FLEN/8, x3, x1, x4) + +inst_3747: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7bff; +op3val:0x8001; valaddr_reg:x2; val_offset:11139*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11139*FLEN/8, x3, x1, x4) + +inst_3748: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7bff; +op3val:0x2; valaddr_reg:x2; val_offset:11142*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11142*FLEN/8, x3, x1, x4) + +inst_3749: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7bff; +op3val:0x83fe; valaddr_reg:x2; val_offset:11145*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11145*FLEN/8, x3, x1, x4) + +inst_3750: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7bff; +op3val:0x3ff; valaddr_reg:x2; val_offset:11148*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11148*FLEN/8, x3, x1, x4) + +inst_3751: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7bff; +op3val:0x83ff; valaddr_reg:x2; val_offset:11151*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11151*FLEN/8, x3, x1, x4) + +inst_3752: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7bff; +op3val:0x400; valaddr_reg:x2; val_offset:11154*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11154*FLEN/8, x3, x1, x4) + +inst_3753: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7bff; +op3val:0x8400; valaddr_reg:x2; val_offset:11157*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11157*FLEN/8, x3, x1, x4) + +inst_3754: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7bff; +op3val:0x401; valaddr_reg:x2; val_offset:11160*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11160*FLEN/8, x3, x1, x4) + +inst_3755: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7bff; +op3val:0x8455; valaddr_reg:x2; val_offset:11163*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11163*FLEN/8, x3, x1, x4) + +inst_3756: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7bff; +op3val:0x7bff; valaddr_reg:x2; val_offset:11166*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11166*FLEN/8, x3, x1, x4) + +inst_3757: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7bff; +op3val:0xfbff; valaddr_reg:x2; val_offset:11169*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11169*FLEN/8, x3, x1, x4) + +inst_3758: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7bff; +op3val:0x7c00; valaddr_reg:x2; val_offset:11172*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11172*FLEN/8, x3, x1, x4) + +inst_3759: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7bff; +op3val:0xfc00; valaddr_reg:x2; val_offset:11175*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11175*FLEN/8, x3, x1, x4) + +inst_3760: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7bff; +op3val:0x7e00; valaddr_reg:x2; val_offset:11178*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11178*FLEN/8, x3, x1, x4) + +inst_3761: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7bff; +op3val:0xfe00; valaddr_reg:x2; val_offset:11181*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11181*FLEN/8, x3, x1, x4) + +inst_3762: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7bff; +op3val:0x7e01; valaddr_reg:x2; val_offset:11184*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11184*FLEN/8, x3, x1, x4) + +inst_3763: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7bff; +op3val:0xfe55; valaddr_reg:x2; val_offset:11187*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11187*FLEN/8, x3, x1, x4) + +inst_3764: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7bff; +op3val:0x7c01; valaddr_reg:x2; val_offset:11190*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11190*FLEN/8, x3, x1, x4) + +inst_3765: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7bff; +op3val:0xfd55; valaddr_reg:x2; val_offset:11193*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11193*FLEN/8, x3, x1, x4) + +inst_3766: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7bff; +op3val:0x3c00; valaddr_reg:x2; val_offset:11196*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11196*FLEN/8, x3, x1, x4) + +inst_3767: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7bff; +op3val:0xbc00; valaddr_reg:x2; val_offset:11199*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11199*FLEN/8, x3, x1, x4) + +inst_3768: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfbff; +op3val:0x0; valaddr_reg:x2; val_offset:11202*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11202*FLEN/8, x3, x1, x4) + +inst_3769: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfbff; +op3val:0x8000; valaddr_reg:x2; val_offset:11205*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11205*FLEN/8, x3, x1, x4) + +inst_3770: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfbff; +op3val:0x1; valaddr_reg:x2; val_offset:11208*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11208*FLEN/8, x3, x1, x4) + +inst_3771: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfbff; +op3val:0x8001; valaddr_reg:x2; val_offset:11211*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11211*FLEN/8, x3, x1, x4) + +inst_3772: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfbff; +op3val:0x2; valaddr_reg:x2; val_offset:11214*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11214*FLEN/8, x3, x1, x4) + +inst_3773: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfbff; +op3val:0x83fe; valaddr_reg:x2; val_offset:11217*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11217*FLEN/8, x3, x1, x4) + +inst_3774: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfbff; +op3val:0x3ff; valaddr_reg:x2; val_offset:11220*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11220*FLEN/8, x3, x1, x4) + +inst_3775: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfbff; +op3val:0x83ff; valaddr_reg:x2; val_offset:11223*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11223*FLEN/8, x3, x1, x4) + +inst_3776: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfbff; +op3val:0x400; valaddr_reg:x2; val_offset:11226*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11226*FLEN/8, x3, x1, x4) + +inst_3777: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfbff; +op3val:0x8400; valaddr_reg:x2; val_offset:11229*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11229*FLEN/8, x3, x1, x4) + +inst_3778: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfbff; +op3val:0x401; valaddr_reg:x2; val_offset:11232*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11232*FLEN/8, x3, x1, x4) + +inst_3779: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfbff; +op3val:0x8455; valaddr_reg:x2; val_offset:11235*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11235*FLEN/8, x3, x1, x4) + +inst_3780: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfbff; +op3val:0x7bff; valaddr_reg:x2; val_offset:11238*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11238*FLEN/8, x3, x1, x4) + +inst_3781: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfbff; +op3val:0xfbff; valaddr_reg:x2; val_offset:11241*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11241*FLEN/8, x3, x1, x4) + +inst_3782: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfbff; +op3val:0x7c00; valaddr_reg:x2; val_offset:11244*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11244*FLEN/8, x3, x1, x4) + +inst_3783: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfbff; +op3val:0xfc00; valaddr_reg:x2; val_offset:11247*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11247*FLEN/8, x3, x1, x4) + +inst_3784: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfbff; +op3val:0x7e00; valaddr_reg:x2; val_offset:11250*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11250*FLEN/8, x3, x1, x4) + +inst_3785: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfbff; +op3val:0xfe00; valaddr_reg:x2; val_offset:11253*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11253*FLEN/8, x3, x1, x4) + +inst_3786: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfbff; +op3val:0x7e01; valaddr_reg:x2; val_offset:11256*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11256*FLEN/8, x3, x1, x4) + +inst_3787: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfbff; +op3val:0xfe55; valaddr_reg:x2; val_offset:11259*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11259*FLEN/8, x3, x1, x4) + +inst_3788: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfbff; +op3val:0x7c01; valaddr_reg:x2; val_offset:11262*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11262*FLEN/8, x3, x1, x4) + +inst_3789: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfbff; +op3val:0xfd55; valaddr_reg:x2; val_offset:11265*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11265*FLEN/8, x3, x1, x4) + +inst_3790: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfbff; +op3val:0x3c00; valaddr_reg:x2; val_offset:11268*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11268*FLEN/8, x3, x1, x4) + +inst_3791: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfbff; +op3val:0xbc00; valaddr_reg:x2; val_offset:11271*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11271*FLEN/8, x3, x1, x4) + +inst_3792: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7c00; +op3val:0x0; valaddr_reg:x2; val_offset:11274*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11274*FLEN/8, x3, x1, x4) + +inst_3793: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7c00; +op3val:0x8000; valaddr_reg:x2; val_offset:11277*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11277*FLEN/8, x3, x1, x4) + +inst_3794: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7c00; +op3val:0x1; valaddr_reg:x2; val_offset:11280*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11280*FLEN/8, x3, x1, x4) + +inst_3795: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7c00; +op3val:0x8001; valaddr_reg:x2; val_offset:11283*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11283*FLEN/8, x3, x1, x4) + +inst_3796: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7c00; +op3val:0x2; valaddr_reg:x2; val_offset:11286*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11286*FLEN/8, x3, x1, x4) + +inst_3797: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7c00; +op3val:0x83fe; valaddr_reg:x2; val_offset:11289*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11289*FLEN/8, x3, x1, x4) + +inst_3798: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7c00; +op3val:0x3ff; valaddr_reg:x2; val_offset:11292*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11292*FLEN/8, x3, x1, x4) + +inst_3799: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7c00; +op3val:0x83ff; valaddr_reg:x2; val_offset:11295*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11295*FLEN/8, x3, x1, x4) + +inst_3800: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7c00; +op3val:0x400; valaddr_reg:x2; val_offset:11298*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11298*FLEN/8, x3, x1, x4) + +inst_3801: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7c00; +op3val:0x8400; valaddr_reg:x2; val_offset:11301*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11301*FLEN/8, x3, x1, x4) + +inst_3802: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7c00; +op3val:0x401; valaddr_reg:x2; val_offset:11304*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11304*FLEN/8, x3, x1, x4) + +inst_3803: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7c00; +op3val:0x8455; valaddr_reg:x2; val_offset:11307*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11307*FLEN/8, x3, x1, x4) + +inst_3804: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7c00; +op3val:0x7bff; valaddr_reg:x2; val_offset:11310*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11310*FLEN/8, x3, x1, x4) + +inst_3805: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7c00; +op3val:0xfbff; valaddr_reg:x2; val_offset:11313*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11313*FLEN/8, x3, x1, x4) + +inst_3806: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7c00; +op3val:0x7c00; valaddr_reg:x2; val_offset:11316*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11316*FLEN/8, x3, x1, x4) + +inst_3807: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7c00; +op3val:0xfc00; valaddr_reg:x2; val_offset:11319*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11319*FLEN/8, x3, x1, x4) + +inst_3808: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7c00; +op3val:0x7e00; valaddr_reg:x2; val_offset:11322*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11322*FLEN/8, x3, x1, x4) + +inst_3809: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7c00; +op3val:0xfe00; valaddr_reg:x2; val_offset:11325*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11325*FLEN/8, x3, x1, x4) + +inst_3810: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7c00; +op3val:0x7e01; valaddr_reg:x2; val_offset:11328*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11328*FLEN/8, x3, x1, x4) + +inst_3811: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7c00; +op3val:0xfe55; valaddr_reg:x2; val_offset:11331*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11331*FLEN/8, x3, x1, x4) + +inst_3812: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7c00; +op3val:0x7c01; valaddr_reg:x2; val_offset:11334*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11334*FLEN/8, x3, x1, x4) + +inst_3813: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7c00; +op3val:0xfd55; valaddr_reg:x2; val_offset:11337*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11337*FLEN/8, x3, x1, x4) + +inst_3814: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7c00; +op3val:0x3c00; valaddr_reg:x2; val_offset:11340*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11340*FLEN/8, x3, x1, x4) + +inst_3815: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7c00; +op3val:0xbc00; valaddr_reg:x2; val_offset:11343*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11343*FLEN/8, x3, x1, x4) + +inst_3816: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfc00; +op3val:0x0; valaddr_reg:x2; val_offset:11346*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11346*FLEN/8, x3, x1, x4) + +inst_3817: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfc00; +op3val:0x8000; valaddr_reg:x2; val_offset:11349*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11349*FLEN/8, x3, x1, x4) + +inst_3818: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfc00; +op3val:0x1; valaddr_reg:x2; val_offset:11352*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11352*FLEN/8, x3, x1, x4) + +inst_3819: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfc00; +op3val:0x8001; valaddr_reg:x2; val_offset:11355*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11355*FLEN/8, x3, x1, x4) + +inst_3820: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfc00; +op3val:0x2; valaddr_reg:x2; val_offset:11358*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11358*FLEN/8, x3, x1, x4) + +inst_3821: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfc00; +op3val:0x83fe; valaddr_reg:x2; val_offset:11361*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11361*FLEN/8, x3, x1, x4) + +inst_3822: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfc00; +op3val:0x3ff; valaddr_reg:x2; val_offset:11364*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11364*FLEN/8, x3, x1, x4) + +inst_3823: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfc00; +op3val:0x83ff; valaddr_reg:x2; val_offset:11367*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11367*FLEN/8, x3, x1, x4) + +inst_3824: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfc00; +op3val:0x400; valaddr_reg:x2; val_offset:11370*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11370*FLEN/8, x3, x1, x4) + +inst_3825: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfc00; +op3val:0x8400; valaddr_reg:x2; val_offset:11373*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11373*FLEN/8, x3, x1, x4) + +inst_3826: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfc00; +op3val:0x401; valaddr_reg:x2; val_offset:11376*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11376*FLEN/8, x3, x1, x4) + +inst_3827: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfc00; +op3val:0x8455; valaddr_reg:x2; val_offset:11379*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11379*FLEN/8, x3, x1, x4) + +inst_3828: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfc00; +op3val:0x7bff; valaddr_reg:x2; val_offset:11382*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11382*FLEN/8, x3, x1, x4) + +inst_3829: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfc00; +op3val:0xfbff; valaddr_reg:x2; val_offset:11385*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11385*FLEN/8, x3, x1, x4) + +inst_3830: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfc00; +op3val:0x7c00; valaddr_reg:x2; val_offset:11388*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11388*FLEN/8, x3, x1, x4) + +inst_3831: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfc00; +op3val:0xfc00; valaddr_reg:x2; val_offset:11391*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11391*FLEN/8, x3, x1, x4) + +inst_3832: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfc00; +op3val:0x7e00; valaddr_reg:x2; val_offset:11394*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11394*FLEN/8, x3, x1, x4) + +inst_3833: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfc00; +op3val:0xfe00; valaddr_reg:x2; val_offset:11397*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11397*FLEN/8, x3, x1, x4) + +inst_3834: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfc00; +op3val:0x7e01; valaddr_reg:x2; val_offset:11400*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11400*FLEN/8, x3, x1, x4) + +inst_3835: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfc00; +op3val:0xfe55; valaddr_reg:x2; val_offset:11403*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11403*FLEN/8, x3, x1, x4) + +inst_3836: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfc00; +op3val:0x7c01; valaddr_reg:x2; val_offset:11406*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11406*FLEN/8, x3, x1, x4) + +inst_3837: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfc00; +op3val:0xfd55; valaddr_reg:x2; val_offset:11409*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11409*FLEN/8, x3, x1, x4) + +inst_3838: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfc00; +op3val:0x3c00; valaddr_reg:x2; val_offset:11412*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11412*FLEN/8, x3, x1, x4) + +inst_3839: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfc00; +op3val:0xbc00; valaddr_reg:x2; val_offset:11415*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11415*FLEN/8, x3, x1, x4) + +inst_3840: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7e00; +op3val:0x0; valaddr_reg:x2; val_offset:11418*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11418*FLEN/8, x3, x1, x4) + +inst_3841: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7e00; +op3val:0x8000; valaddr_reg:x2; val_offset:11421*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11421*FLEN/8, x3, x1, x4) + +inst_3842: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7e00; +op3val:0x1; valaddr_reg:x2; val_offset:11424*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11424*FLEN/8, x3, x1, x4) + +inst_3843: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7e00; +op3val:0x8001; valaddr_reg:x2; val_offset:11427*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11427*FLEN/8, x3, x1, x4) + +inst_3844: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7e00; +op3val:0x2; valaddr_reg:x2; val_offset:11430*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11430*FLEN/8, x3, x1, x4) + +inst_3845: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7e00; +op3val:0x83fe; valaddr_reg:x2; val_offset:11433*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11433*FLEN/8, x3, x1, x4) + +inst_3846: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7e00; +op3val:0x3ff; valaddr_reg:x2; val_offset:11436*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11436*FLEN/8, x3, x1, x4) + +inst_3847: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7e00; +op3val:0x83ff; valaddr_reg:x2; val_offset:11439*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11439*FLEN/8, x3, x1, x4) + +inst_3848: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7e00; +op3val:0x400; valaddr_reg:x2; val_offset:11442*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11442*FLEN/8, x3, x1, x4) + +inst_3849: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7e00; +op3val:0x8400; valaddr_reg:x2; val_offset:11445*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11445*FLEN/8, x3, x1, x4) + +inst_3850: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7e00; +op3val:0x401; valaddr_reg:x2; val_offset:11448*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11448*FLEN/8, x3, x1, x4) + +inst_3851: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7e00; +op3val:0x8455; valaddr_reg:x2; val_offset:11451*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11451*FLEN/8, x3, x1, x4) + +inst_3852: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7e00; +op3val:0x7bff; valaddr_reg:x2; val_offset:11454*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11454*FLEN/8, x3, x1, x4) + +inst_3853: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7e00; +op3val:0xfbff; valaddr_reg:x2; val_offset:11457*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11457*FLEN/8, x3, x1, x4) + +inst_3854: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7e00; +op3val:0x7c00; valaddr_reg:x2; val_offset:11460*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11460*FLEN/8, x3, x1, x4) + +inst_3855: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7e00; +op3val:0xfc00; valaddr_reg:x2; val_offset:11463*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11463*FLEN/8, x3, x1, x4) + +inst_3856: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7e00; +op3val:0x7e00; valaddr_reg:x2; val_offset:11466*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11466*FLEN/8, x3, x1, x4) + +inst_3857: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7e00; +op3val:0xfe00; valaddr_reg:x2; val_offset:11469*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11469*FLEN/8, x3, x1, x4) + +inst_3858: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7e00; +op3val:0x7e01; valaddr_reg:x2; val_offset:11472*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11472*FLEN/8, x3, x1, x4) + +inst_3859: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7e00; +op3val:0xfe55; valaddr_reg:x2; val_offset:11475*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11475*FLEN/8, x3, x1, x4) + +inst_3860: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7e00; +op3val:0x7c01; valaddr_reg:x2; val_offset:11478*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11478*FLEN/8, x3, x1, x4) + +inst_3861: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7e00; +op3val:0xfd55; valaddr_reg:x2; val_offset:11481*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11481*FLEN/8, x3, x1, x4) + +inst_3862: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7e00; +op3val:0x3c00; valaddr_reg:x2; val_offset:11484*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11484*FLEN/8, x3, x1, x4) + +inst_3863: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7e00; +op3val:0xbc00; valaddr_reg:x2; val_offset:11487*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11487*FLEN/8, x3, x1, x4) + +inst_3864: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfe00; +op3val:0x0; valaddr_reg:x2; val_offset:11490*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11490*FLEN/8, x3, x1, x4) + +inst_3865: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfe00; +op3val:0x8000; valaddr_reg:x2; val_offset:11493*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11493*FLEN/8, x3, x1, x4) + +inst_3866: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfe00; +op3val:0x1; valaddr_reg:x2; val_offset:11496*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11496*FLEN/8, x3, x1, x4) + +inst_3867: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfe00; +op3val:0x8001; valaddr_reg:x2; val_offset:11499*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11499*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_31) + +inst_3868: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfe00; +op3val:0x2; valaddr_reg:x2; val_offset:11502*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11502*FLEN/8, x3, x1, x4) + +inst_3869: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfe00; +op3val:0x83fe; valaddr_reg:x2; val_offset:11505*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11505*FLEN/8, x3, x1, x4) + +inst_3870: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfe00; +op3val:0x3ff; valaddr_reg:x2; val_offset:11508*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11508*FLEN/8, x3, x1, x4) + +inst_3871: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfe00; +op3val:0x83ff; valaddr_reg:x2; val_offset:11511*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11511*FLEN/8, x3, x1, x4) + +inst_3872: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfe00; +op3val:0x400; valaddr_reg:x2; val_offset:11514*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11514*FLEN/8, x3, x1, x4) + +inst_3873: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfe00; +op3val:0x8400; valaddr_reg:x2; val_offset:11517*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11517*FLEN/8, x3, x1, x4) + +inst_3874: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfe00; +op3val:0x401; valaddr_reg:x2; val_offset:11520*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11520*FLEN/8, x3, x1, x4) + +inst_3875: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfe00; +op3val:0x8455; valaddr_reg:x2; val_offset:11523*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11523*FLEN/8, x3, x1, x4) + +inst_3876: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfe00; +op3val:0x7bff; valaddr_reg:x2; val_offset:11526*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11526*FLEN/8, x3, x1, x4) + +inst_3877: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfe00; +op3val:0xfbff; valaddr_reg:x2; val_offset:11529*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11529*FLEN/8, x3, x1, x4) + +inst_3878: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfe00; +op3val:0x7c00; valaddr_reg:x2; val_offset:11532*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11532*FLEN/8, x3, x1, x4) + +inst_3879: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfe00; +op3val:0xfc00; valaddr_reg:x2; val_offset:11535*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11535*FLEN/8, x3, x1, x4) + +inst_3880: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfe00; +op3val:0x7e00; valaddr_reg:x2; val_offset:11538*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11538*FLEN/8, x3, x1, x4) + +inst_3881: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfe00; +op3val:0xfe00; valaddr_reg:x2; val_offset:11541*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11541*FLEN/8, x3, x1, x4) + +inst_3882: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfe00; +op3val:0x7e01; valaddr_reg:x2; val_offset:11544*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11544*FLEN/8, x3, x1, x4) + +inst_3883: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfe00; +op3val:0xfe55; valaddr_reg:x2; val_offset:11547*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11547*FLEN/8, x3, x1, x4) + +inst_3884: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfe00; +op3val:0x7c01; valaddr_reg:x2; val_offset:11550*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11550*FLEN/8, x3, x1, x4) + +inst_3885: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfe00; +op3val:0xfd55; valaddr_reg:x2; val_offset:11553*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11553*FLEN/8, x3, x1, x4) + +inst_3886: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfe00; +op3val:0x3c00; valaddr_reg:x2; val_offset:11556*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11556*FLEN/8, x3, x1, x4) + +inst_3887: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfe00; +op3val:0xbc00; valaddr_reg:x2; val_offset:11559*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11559*FLEN/8, x3, x1, x4) + +inst_3888: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7e01; +op3val:0x0; valaddr_reg:x2; val_offset:11562*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11562*FLEN/8, x3, x1, x4) + +inst_3889: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7e01; +op3val:0x8000; valaddr_reg:x2; val_offset:11565*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11565*FLEN/8, x3, x1, x4) + +inst_3890: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7e01; +op3val:0x1; valaddr_reg:x2; val_offset:11568*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11568*FLEN/8, x3, x1, x4) + +inst_3891: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7e01; +op3val:0x8001; valaddr_reg:x2; val_offset:11571*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11571*FLEN/8, x3, x1, x4) + +inst_3892: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7e01; +op3val:0x2; valaddr_reg:x2; val_offset:11574*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11574*FLEN/8, x3, x1, x4) + +inst_3893: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7e01; +op3val:0x83fe; valaddr_reg:x2; val_offset:11577*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11577*FLEN/8, x3, x1, x4) + +inst_3894: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7e01; +op3val:0x3ff; valaddr_reg:x2; val_offset:11580*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11580*FLEN/8, x3, x1, x4) + +inst_3895: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7e01; +op3val:0x83ff; valaddr_reg:x2; val_offset:11583*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11583*FLEN/8, x3, x1, x4) + +inst_3896: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7e01; +op3val:0x400; valaddr_reg:x2; val_offset:11586*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11586*FLEN/8, x3, x1, x4) + +inst_3897: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7e01; +op3val:0x8400; valaddr_reg:x2; val_offset:11589*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11589*FLEN/8, x3, x1, x4) + +inst_3898: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7e01; +op3val:0x401; valaddr_reg:x2; val_offset:11592*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11592*FLEN/8, x3, x1, x4) + +inst_3899: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7e01; +op3val:0x8455; valaddr_reg:x2; val_offset:11595*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11595*FLEN/8, x3, x1, x4) + +inst_3900: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7e01; +op3val:0x7bff; valaddr_reg:x2; val_offset:11598*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11598*FLEN/8, x3, x1, x4) + +inst_3901: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7e01; +op3val:0xfbff; valaddr_reg:x2; val_offset:11601*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11601*FLEN/8, x3, x1, x4) + +inst_3902: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7e01; +op3val:0x7c00; valaddr_reg:x2; val_offset:11604*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11604*FLEN/8, x3, x1, x4) + +inst_3903: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7e01; +op3val:0xfc00; valaddr_reg:x2; val_offset:11607*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11607*FLEN/8, x3, x1, x4) + +inst_3904: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7e01; +op3val:0x7e00; valaddr_reg:x2; val_offset:11610*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11610*FLEN/8, x3, x1, x4) + +inst_3905: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7e01; +op3val:0xfe00; valaddr_reg:x2; val_offset:11613*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11613*FLEN/8, x3, x1, x4) + +inst_3906: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7e01; +op3val:0x7e01; valaddr_reg:x2; val_offset:11616*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11616*FLEN/8, x3, x1, x4) + +inst_3907: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7e01; +op3val:0xfe55; valaddr_reg:x2; val_offset:11619*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11619*FLEN/8, x3, x1, x4) + +inst_3908: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7e01; +op3val:0x7c01; valaddr_reg:x2; val_offset:11622*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11622*FLEN/8, x3, x1, x4) + +inst_3909: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7e01; +op3val:0xfd55; valaddr_reg:x2; val_offset:11625*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11625*FLEN/8, x3, x1, x4) + +inst_3910: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7e01; +op3val:0x3c00; valaddr_reg:x2; val_offset:11628*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11628*FLEN/8, x3, x1, x4) + +inst_3911: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7e01; +op3val:0xbc00; valaddr_reg:x2; val_offset:11631*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11631*FLEN/8, x3, x1, x4) + +inst_3912: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfe55; +op3val:0x0; valaddr_reg:x2; val_offset:11634*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11634*FLEN/8, x3, x1, x4) + +inst_3913: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfe55; +op3val:0x8000; valaddr_reg:x2; val_offset:11637*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11637*FLEN/8, x3, x1, x4) + +inst_3914: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfe55; +op3val:0x1; valaddr_reg:x2; val_offset:11640*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11640*FLEN/8, x3, x1, x4) + +inst_3915: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfe55; +op3val:0x8001; valaddr_reg:x2; val_offset:11643*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11643*FLEN/8, x3, x1, x4) + +inst_3916: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfe55; +op3val:0x2; valaddr_reg:x2; val_offset:11646*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11646*FLEN/8, x3, x1, x4) + +inst_3917: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfe55; +op3val:0x83fe; valaddr_reg:x2; val_offset:11649*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11649*FLEN/8, x3, x1, x4) + +inst_3918: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfe55; +op3val:0x3ff; valaddr_reg:x2; val_offset:11652*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11652*FLEN/8, x3, x1, x4) + +inst_3919: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfe55; +op3val:0x83ff; valaddr_reg:x2; val_offset:11655*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11655*FLEN/8, x3, x1, x4) + +inst_3920: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfe55; +op3val:0x400; valaddr_reg:x2; val_offset:11658*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11658*FLEN/8, x3, x1, x4) + +inst_3921: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfe55; +op3val:0x8400; valaddr_reg:x2; val_offset:11661*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11661*FLEN/8, x3, x1, x4) + +inst_3922: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfe55; +op3val:0x401; valaddr_reg:x2; val_offset:11664*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11664*FLEN/8, x3, x1, x4) + +inst_3923: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfe55; +op3val:0x8455; valaddr_reg:x2; val_offset:11667*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11667*FLEN/8, x3, x1, x4) + +inst_3924: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfe55; +op3val:0x7bff; valaddr_reg:x2; val_offset:11670*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11670*FLEN/8, x3, x1, x4) + +inst_3925: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfe55; +op3val:0xfbff; valaddr_reg:x2; val_offset:11673*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11673*FLEN/8, x3, x1, x4) + +inst_3926: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfe55; +op3val:0x7c00; valaddr_reg:x2; val_offset:11676*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11676*FLEN/8, x3, x1, x4) + +inst_3927: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfe55; +op3val:0xfc00; valaddr_reg:x2; val_offset:11679*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11679*FLEN/8, x3, x1, x4) + +inst_3928: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfe55; +op3val:0x7e00; valaddr_reg:x2; val_offset:11682*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11682*FLEN/8, x3, x1, x4) + +inst_3929: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfe55; +op3val:0xfe00; valaddr_reg:x2; val_offset:11685*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11685*FLEN/8, x3, x1, x4) + +inst_3930: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfe55; +op3val:0x7e01; valaddr_reg:x2; val_offset:11688*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11688*FLEN/8, x3, x1, x4) + +inst_3931: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfe55; +op3val:0xfe55; valaddr_reg:x2; val_offset:11691*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11691*FLEN/8, x3, x1, x4) + +inst_3932: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfe55; +op3val:0x7c01; valaddr_reg:x2; val_offset:11694*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11694*FLEN/8, x3, x1, x4) + +inst_3933: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfe55; +op3val:0xfd55; valaddr_reg:x2; val_offset:11697*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11697*FLEN/8, x3, x1, x4) + +inst_3934: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfe55; +op3val:0x3c00; valaddr_reg:x2; val_offset:11700*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11700*FLEN/8, x3, x1, x4) + +inst_3935: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfe55; +op3val:0xbc00; valaddr_reg:x2; val_offset:11703*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11703*FLEN/8, x3, x1, x4) + +inst_3936: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7c01; +op3val:0x0; valaddr_reg:x2; val_offset:11706*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11706*FLEN/8, x3, x1, x4) + +inst_3937: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7c01; +op3val:0x8000; valaddr_reg:x2; val_offset:11709*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11709*FLEN/8, x3, x1, x4) + +inst_3938: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7c01; +op3val:0x1; valaddr_reg:x2; val_offset:11712*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11712*FLEN/8, x3, x1, x4) + +inst_3939: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7c01; +op3val:0x8001; valaddr_reg:x2; val_offset:11715*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11715*FLEN/8, x3, x1, x4) + +inst_3940: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7c01; +op3val:0x2; valaddr_reg:x2; val_offset:11718*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11718*FLEN/8, x3, x1, x4) + +inst_3941: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7c01; +op3val:0x83fe; valaddr_reg:x2; val_offset:11721*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11721*FLEN/8, x3, x1, x4) + +inst_3942: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7c01; +op3val:0x3ff; valaddr_reg:x2; val_offset:11724*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11724*FLEN/8, x3, x1, x4) + +inst_3943: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7c01; +op3val:0x83ff; valaddr_reg:x2; val_offset:11727*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11727*FLEN/8, x3, x1, x4) + +inst_3944: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7c01; +op3val:0x400; valaddr_reg:x2; val_offset:11730*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11730*FLEN/8, x3, x1, x4) + +inst_3945: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7c01; +op3val:0x8400; valaddr_reg:x2; val_offset:11733*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11733*FLEN/8, x3, x1, x4) + +inst_3946: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7c01; +op3val:0x401; valaddr_reg:x2; val_offset:11736*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11736*FLEN/8, x3, x1, x4) + +inst_3947: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7c01; +op3val:0x8455; valaddr_reg:x2; val_offset:11739*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11739*FLEN/8, x3, x1, x4) + +inst_3948: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7c01; +op3val:0x7bff; valaddr_reg:x2; val_offset:11742*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11742*FLEN/8, x3, x1, x4) + +inst_3949: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7c01; +op3val:0xfbff; valaddr_reg:x2; val_offset:11745*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11745*FLEN/8, x3, x1, x4) + +inst_3950: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7c01; +op3val:0x7c00; valaddr_reg:x2; val_offset:11748*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11748*FLEN/8, x3, x1, x4) + +inst_3951: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7c01; +op3val:0xfc00; valaddr_reg:x2; val_offset:11751*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11751*FLEN/8, x3, x1, x4) + +inst_3952: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7c01; +op3val:0x7e00; valaddr_reg:x2; val_offset:11754*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11754*FLEN/8, x3, x1, x4) + +inst_3953: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7c01; +op3val:0xfe00; valaddr_reg:x2; val_offset:11757*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11757*FLEN/8, x3, x1, x4) + +inst_3954: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7c01; +op3val:0x7e01; valaddr_reg:x2; val_offset:11760*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11760*FLEN/8, x3, x1, x4) + +inst_3955: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7c01; +op3val:0xfe55; valaddr_reg:x2; val_offset:11763*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11763*FLEN/8, x3, x1, x4) + +inst_3956: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7c01; +op3val:0x7c01; valaddr_reg:x2; val_offset:11766*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11766*FLEN/8, x3, x1, x4) + +inst_3957: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7c01; +op3val:0xfd55; valaddr_reg:x2; val_offset:11769*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11769*FLEN/8, x3, x1, x4) + +inst_3958: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7c01; +op3val:0x3c00; valaddr_reg:x2; val_offset:11772*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11772*FLEN/8, x3, x1, x4) + +inst_3959: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x7c01; +op3val:0xbc00; valaddr_reg:x2; val_offset:11775*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11775*FLEN/8, x3, x1, x4) + +inst_3960: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfd55; +op3val:0x0; valaddr_reg:x2; val_offset:11778*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11778*FLEN/8, x3, x1, x4) + +inst_3961: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfd55; +op3val:0x8000; valaddr_reg:x2; val_offset:11781*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11781*FLEN/8, x3, x1, x4) + +inst_3962: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfd55; +op3val:0x1; valaddr_reg:x2; val_offset:11784*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11784*FLEN/8, x3, x1, x4) + +inst_3963: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfd55; +op3val:0x8001; valaddr_reg:x2; val_offset:11787*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11787*FLEN/8, x3, x1, x4) + +inst_3964: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfd55; +op3val:0x2; valaddr_reg:x2; val_offset:11790*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11790*FLEN/8, x3, x1, x4) + +inst_3965: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfd55; +op3val:0x83fe; valaddr_reg:x2; val_offset:11793*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11793*FLEN/8, x3, x1, x4) + +inst_3966: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfd55; +op3val:0x3ff; valaddr_reg:x2; val_offset:11796*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11796*FLEN/8, x3, x1, x4) + +inst_3967: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfd55; +op3val:0x83ff; valaddr_reg:x2; val_offset:11799*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11799*FLEN/8, x3, x1, x4) + +inst_3968: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfd55; +op3val:0x400; valaddr_reg:x2; val_offset:11802*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11802*FLEN/8, x3, x1, x4) + +inst_3969: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfd55; +op3val:0x8400; valaddr_reg:x2; val_offset:11805*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11805*FLEN/8, x3, x1, x4) + +inst_3970: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfd55; +op3val:0x401; valaddr_reg:x2; val_offset:11808*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11808*FLEN/8, x3, x1, x4) + +inst_3971: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfd55; +op3val:0x8455; valaddr_reg:x2; val_offset:11811*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11811*FLEN/8, x3, x1, x4) + +inst_3972: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfd55; +op3val:0x7bff; valaddr_reg:x2; val_offset:11814*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11814*FLEN/8, x3, x1, x4) + +inst_3973: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfd55; +op3val:0xfbff; valaddr_reg:x2; val_offset:11817*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11817*FLEN/8, x3, x1, x4) + +inst_3974: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfd55; +op3val:0x7c00; valaddr_reg:x2; val_offset:11820*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11820*FLEN/8, x3, x1, x4) + +inst_3975: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfd55; +op3val:0xfc00; valaddr_reg:x2; val_offset:11823*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11823*FLEN/8, x3, x1, x4) + +inst_3976: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfd55; +op3val:0x7e00; valaddr_reg:x2; val_offset:11826*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11826*FLEN/8, x3, x1, x4) + +inst_3977: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfd55; +op3val:0xfe00; valaddr_reg:x2; val_offset:11829*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11829*FLEN/8, x3, x1, x4) + +inst_3978: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfd55; +op3val:0x7e01; valaddr_reg:x2; val_offset:11832*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11832*FLEN/8, x3, x1, x4) + +inst_3979: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfd55; +op3val:0xfe55; valaddr_reg:x2; val_offset:11835*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11835*FLEN/8, x3, x1, x4) + +inst_3980: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfd55; +op3val:0x7c01; valaddr_reg:x2; val_offset:11838*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11838*FLEN/8, x3, x1, x4) + +inst_3981: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfd55; +op3val:0xfd55; valaddr_reg:x2; val_offset:11841*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11841*FLEN/8, x3, x1, x4) + +inst_3982: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfd55; +op3val:0x3c00; valaddr_reg:x2; val_offset:11844*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11844*FLEN/8, x3, x1, x4) + +inst_3983: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xfd55; +op3val:0xbc00; valaddr_reg:x2; val_offset:11847*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11847*FLEN/8, x3, x1, x4) + +inst_3984: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x3c00; +op3val:0x0; valaddr_reg:x2; val_offset:11850*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11850*FLEN/8, x3, x1, x4) + +inst_3985: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x3c00; +op3val:0x8000; valaddr_reg:x2; val_offset:11853*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11853*FLEN/8, x3, x1, x4) + +inst_3986: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x3c00; +op3val:0x1; valaddr_reg:x2; val_offset:11856*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11856*FLEN/8, x3, x1, x4) + +inst_3987: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x3c00; +op3val:0x8001; valaddr_reg:x2; val_offset:11859*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11859*FLEN/8, x3, x1, x4) + +inst_3988: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x3c00; +op3val:0x2; valaddr_reg:x2; val_offset:11862*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11862*FLEN/8, x3, x1, x4) + +inst_3989: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x3c00; +op3val:0x83fe; valaddr_reg:x2; val_offset:11865*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11865*FLEN/8, x3, x1, x4) + +inst_3990: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x3c00; +op3val:0x3ff; valaddr_reg:x2; val_offset:11868*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11868*FLEN/8, x3, x1, x4) + +inst_3991: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x3c00; +op3val:0x83ff; valaddr_reg:x2; val_offset:11871*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11871*FLEN/8, x3, x1, x4) + +inst_3992: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x3c00; +op3val:0x400; valaddr_reg:x2; val_offset:11874*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11874*FLEN/8, x3, x1, x4) + +inst_3993: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x3c00; +op3val:0x8400; valaddr_reg:x2; val_offset:11877*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11877*FLEN/8, x3, x1, x4) + +inst_3994: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x3c00; +op3val:0x401; valaddr_reg:x2; val_offset:11880*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11880*FLEN/8, x3, x1, x4) + +inst_3995: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x3c00; +op3val:0x8455; valaddr_reg:x2; val_offset:11883*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11883*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_32) + +inst_3996: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x3c00; +op3val:0x7bff; valaddr_reg:x2; val_offset:11886*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11886*FLEN/8, x3, x1, x4) + +inst_3997: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x3c00; +op3val:0xfbff; valaddr_reg:x2; val_offset:11889*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11889*FLEN/8, x3, x1, x4) + +inst_3998: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x3c00; +op3val:0x7c00; valaddr_reg:x2; val_offset:11892*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11892*FLEN/8, x3, x1, x4) + +inst_3999: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x3c00; +op3val:0xfc00; valaddr_reg:x2; val_offset:11895*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11895*FLEN/8, x3, x1, x4) + +inst_4000: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x3c00; +op3val:0x7e00; valaddr_reg:x2; val_offset:11898*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11898*FLEN/8, x3, x1, x4) + +inst_4001: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x3c00; +op3val:0xfe00; valaddr_reg:x2; val_offset:11901*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11901*FLEN/8, x3, x1, x4) + +inst_4002: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x3c00; +op3val:0x7e01; valaddr_reg:x2; val_offset:11904*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11904*FLEN/8, x3, x1, x4) + +inst_4003: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x3c00; +op3val:0xfe55; valaddr_reg:x2; val_offset:11907*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11907*FLEN/8, x3, x1, x4) + +inst_4004: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x3c00; +op3val:0x7c01; valaddr_reg:x2; val_offset:11910*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11910*FLEN/8, x3, x1, x4) + +inst_4005: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x3c00; +op3val:0xfd55; valaddr_reg:x2; val_offset:11913*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11913*FLEN/8, x3, x1, x4) + +inst_4006: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x3c00; +op3val:0x3c00; valaddr_reg:x2; val_offset:11916*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11916*FLEN/8, x3, x1, x4) + +inst_4007: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0x3c00; +op3val:0xbc00; valaddr_reg:x2; val_offset:11919*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11919*FLEN/8, x3, x1, x4) + +inst_4008: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xbc00; +op3val:0x0; valaddr_reg:x2; val_offset:11922*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11922*FLEN/8, x3, x1, x4) + +inst_4009: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xbc00; +op3val:0x8000; valaddr_reg:x2; val_offset:11925*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11925*FLEN/8, x3, x1, x4) + +inst_4010: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xbc00; +op3val:0x1; valaddr_reg:x2; val_offset:11928*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11928*FLEN/8, x3, x1, x4) + +inst_4011: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xbc00; +op3val:0x8001; valaddr_reg:x2; val_offset:11931*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11931*FLEN/8, x3, x1, x4) + +inst_4012: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xbc00; +op3val:0x2; valaddr_reg:x2; val_offset:11934*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11934*FLEN/8, x3, x1, x4) + +inst_4013: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xbc00; +op3val:0x83fe; valaddr_reg:x2; val_offset:11937*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11937*FLEN/8, x3, x1, x4) + +inst_4014: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xbc00; +op3val:0x3ff; valaddr_reg:x2; val_offset:11940*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11940*FLEN/8, x3, x1, x4) + +inst_4015: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xbc00; +op3val:0x83ff; valaddr_reg:x2; val_offset:11943*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11943*FLEN/8, x3, x1, x4) + +inst_4016: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xbc00; +op3val:0x400; valaddr_reg:x2; val_offset:11946*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11946*FLEN/8, x3, x1, x4) + +inst_4017: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xbc00; +op3val:0x8400; valaddr_reg:x2; val_offset:11949*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11949*FLEN/8, x3, x1, x4) + +inst_4018: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xbc00; +op3val:0x401; valaddr_reg:x2; val_offset:11952*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11952*FLEN/8, x3, x1, x4) + +inst_4019: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xbc00; +op3val:0x8455; valaddr_reg:x2; val_offset:11955*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11955*FLEN/8, x3, x1, x4) + +inst_4020: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xbc00; +op3val:0x7bff; valaddr_reg:x2; val_offset:11958*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11958*FLEN/8, x3, x1, x4) + +inst_4021: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xbc00; +op3val:0xfbff; valaddr_reg:x2; val_offset:11961*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11961*FLEN/8, x3, x1, x4) + +inst_4022: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xbc00; +op3val:0x7c00; valaddr_reg:x2; val_offset:11964*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11964*FLEN/8, x3, x1, x4) + +inst_4023: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xbc00; +op3val:0xfc00; valaddr_reg:x2; val_offset:11967*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11967*FLEN/8, x3, x1, x4) + +inst_4024: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xbc00; +op3val:0x7e00; valaddr_reg:x2; val_offset:11970*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11970*FLEN/8, x3, x1, x4) + +inst_4025: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xbc00; +op3val:0xfe00; valaddr_reg:x2; val_offset:11973*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11973*FLEN/8, x3, x1, x4) + +inst_4026: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xbc00; +op3val:0x7e01; valaddr_reg:x2; val_offset:11976*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11976*FLEN/8, x3, x1, x4) + +inst_4027: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xbc00; +op3val:0xfe55; valaddr_reg:x2; val_offset:11979*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11979*FLEN/8, x3, x1, x4) + +inst_4028: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xbc00; +op3val:0x7c01; valaddr_reg:x2; val_offset:11982*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11982*FLEN/8, x3, x1, x4) + +inst_4029: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xbc00; +op3val:0xfd55; valaddr_reg:x2; val_offset:11985*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11985*FLEN/8, x3, x1, x4) + +inst_4030: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xbc00; +op3val:0x3c00; valaddr_reg:x2; val_offset:11988*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11988*FLEN/8, x3, x1, x4) + +inst_4031: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ff; op2val:0xbc00; +op3val:0xbc00; valaddr_reg:x2; val_offset:11991*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11991*FLEN/8, x3, x1, x4) + +inst_4032: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x0; +op3val:0x0; valaddr_reg:x2; val_offset:11994*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11994*FLEN/8, x3, x1, x4) + +inst_4033: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x0; +op3val:0x8000; valaddr_reg:x2; val_offset:11997*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 11997*FLEN/8, x3, x1, x4) + +inst_4034: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x0; +op3val:0x1; valaddr_reg:x2; val_offset:12000*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12000*FLEN/8, x3, x1, x4) + +inst_4035: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x0; +op3val:0x8001; valaddr_reg:x2; val_offset:12003*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12003*FLEN/8, x3, x1, x4) + +inst_4036: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x0; +op3val:0x2; valaddr_reg:x2; val_offset:12006*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12006*FLEN/8, x3, x1, x4) + +inst_4037: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x0; +op3val:0x83fe; valaddr_reg:x2; val_offset:12009*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12009*FLEN/8, x3, x1, x4) + +inst_4038: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x0; +op3val:0x3ff; valaddr_reg:x2; val_offset:12012*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12012*FLEN/8, x3, x1, x4) + +inst_4039: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x0; +op3val:0x83ff; valaddr_reg:x2; val_offset:12015*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12015*FLEN/8, x3, x1, x4) + +inst_4040: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x0; +op3val:0x400; valaddr_reg:x2; val_offset:12018*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12018*FLEN/8, x3, x1, x4) + +inst_4041: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x0; +op3val:0x8400; valaddr_reg:x2; val_offset:12021*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12021*FLEN/8, x3, x1, x4) + +inst_4042: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x0; +op3val:0x401; valaddr_reg:x2; val_offset:12024*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12024*FLEN/8, x3, x1, x4) + +inst_4043: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x0; +op3val:0x8455; valaddr_reg:x2; val_offset:12027*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12027*FLEN/8, x3, x1, x4) + +inst_4044: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x0; +op3val:0x7bff; valaddr_reg:x2; val_offset:12030*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12030*FLEN/8, x3, x1, x4) + +inst_4045: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x0; +op3val:0xfbff; valaddr_reg:x2; val_offset:12033*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12033*FLEN/8, x3, x1, x4) + +inst_4046: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x0; +op3val:0x7c00; valaddr_reg:x2; val_offset:12036*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12036*FLEN/8, x3, x1, x4) + +inst_4047: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x0; +op3val:0xfc00; valaddr_reg:x2; val_offset:12039*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12039*FLEN/8, x3, x1, x4) + +inst_4048: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x0; +op3val:0x7e00; valaddr_reg:x2; val_offset:12042*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12042*FLEN/8, x3, x1, x4) + +inst_4049: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x0; +op3val:0xfe00; valaddr_reg:x2; val_offset:12045*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12045*FLEN/8, x3, x1, x4) + +inst_4050: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x0; +op3val:0x7e01; valaddr_reg:x2; val_offset:12048*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12048*FLEN/8, x3, x1, x4) + +inst_4051: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x0; +op3val:0xfe55; valaddr_reg:x2; val_offset:12051*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12051*FLEN/8, x3, x1, x4) + +inst_4052: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x0; +op3val:0x7c01; valaddr_reg:x2; val_offset:12054*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12054*FLEN/8, x3, x1, x4) + +inst_4053: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x0; +op3val:0xfd55; valaddr_reg:x2; val_offset:12057*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12057*FLEN/8, x3, x1, x4) + +inst_4054: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x0; +op3val:0x3c00; valaddr_reg:x2; val_offset:12060*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12060*FLEN/8, x3, x1, x4) + +inst_4055: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x0; +op3val:0xbc00; valaddr_reg:x2; val_offset:12063*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12063*FLEN/8, x3, x1, x4) + +inst_4056: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8000; +op3val:0x0; valaddr_reg:x2; val_offset:12066*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12066*FLEN/8, x3, x1, x4) + +inst_4057: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8000; +op3val:0x8000; valaddr_reg:x2; val_offset:12069*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12069*FLEN/8, x3, x1, x4) + +inst_4058: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8000; +op3val:0x1; valaddr_reg:x2; val_offset:12072*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12072*FLEN/8, x3, x1, x4) + +inst_4059: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8000; +op3val:0x8001; valaddr_reg:x2; val_offset:12075*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12075*FLEN/8, x3, x1, x4) + +inst_4060: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8000; +op3val:0x2; valaddr_reg:x2; val_offset:12078*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12078*FLEN/8, x3, x1, x4) + +inst_4061: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8000; +op3val:0x83fe; valaddr_reg:x2; val_offset:12081*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12081*FLEN/8, x3, x1, x4) + +inst_4062: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8000; +op3val:0x3ff; valaddr_reg:x2; val_offset:12084*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12084*FLEN/8, x3, x1, x4) + +inst_4063: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8000; +op3val:0x83ff; valaddr_reg:x2; val_offset:12087*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12087*FLEN/8, x3, x1, x4) + +inst_4064: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8000; +op3val:0x400; valaddr_reg:x2; val_offset:12090*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12090*FLEN/8, x3, x1, x4) + +inst_4065: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8000; +op3val:0x8400; valaddr_reg:x2; val_offset:12093*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12093*FLEN/8, x3, x1, x4) + +inst_4066: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8000; +op3val:0x401; valaddr_reg:x2; val_offset:12096*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12096*FLEN/8, x3, x1, x4) + +inst_4067: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8000; +op3val:0x8455; valaddr_reg:x2; val_offset:12099*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12099*FLEN/8, x3, x1, x4) + +inst_4068: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x2; val_offset:12102*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12102*FLEN/8, x3, x1, x4) + +inst_4069: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x2; val_offset:12105*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12105*FLEN/8, x3, x1, x4) + +inst_4070: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8000; +op3val:0x7c00; valaddr_reg:x2; val_offset:12108*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12108*FLEN/8, x3, x1, x4) + +inst_4071: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8000; +op3val:0xfc00; valaddr_reg:x2; val_offset:12111*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12111*FLEN/8, x3, x1, x4) + +inst_4072: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8000; +op3val:0x7e00; valaddr_reg:x2; val_offset:12114*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12114*FLEN/8, x3, x1, x4) + +inst_4073: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8000; +op3val:0xfe00; valaddr_reg:x2; val_offset:12117*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12117*FLEN/8, x3, x1, x4) + +inst_4074: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8000; +op3val:0x7e01; valaddr_reg:x2; val_offset:12120*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12120*FLEN/8, x3, x1, x4) + +inst_4075: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8000; +op3val:0xfe55; valaddr_reg:x2; val_offset:12123*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12123*FLEN/8, x3, x1, x4) + +inst_4076: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8000; +op3val:0x7c01; valaddr_reg:x2; val_offset:12126*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12126*FLEN/8, x3, x1, x4) + +inst_4077: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8000; +op3val:0xfd55; valaddr_reg:x2; val_offset:12129*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12129*FLEN/8, x3, x1, x4) + +inst_4078: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8000; +op3val:0x3c00; valaddr_reg:x2; val_offset:12132*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12132*FLEN/8, x3, x1, x4) + +inst_4079: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8000; +op3val:0xbc00; valaddr_reg:x2; val_offset:12135*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12135*FLEN/8, x3, x1, x4) + +inst_4080: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x1; +op3val:0x0; valaddr_reg:x2; val_offset:12138*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12138*FLEN/8, x3, x1, x4) + +inst_4081: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x1; +op3val:0x8000; valaddr_reg:x2; val_offset:12141*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12141*FLEN/8, x3, x1, x4) + +inst_4082: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x1; +op3val:0x1; valaddr_reg:x2; val_offset:12144*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12144*FLEN/8, x3, x1, x4) + +inst_4083: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x1; +op3val:0x8001; valaddr_reg:x2; val_offset:12147*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12147*FLEN/8, x3, x1, x4) + +inst_4084: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x1; +op3val:0x2; valaddr_reg:x2; val_offset:12150*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12150*FLEN/8, x3, x1, x4) + +inst_4085: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x1; +op3val:0x83fe; valaddr_reg:x2; val_offset:12153*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12153*FLEN/8, x3, x1, x4) + +inst_4086: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x1; +op3val:0x3ff; valaddr_reg:x2; val_offset:12156*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12156*FLEN/8, x3, x1, x4) + +inst_4087: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x1; +op3val:0x83ff; valaddr_reg:x2; val_offset:12159*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12159*FLEN/8, x3, x1, x4) + +inst_4088: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x1; +op3val:0x400; valaddr_reg:x2; val_offset:12162*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12162*FLEN/8, x3, x1, x4) + +inst_4089: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x1; +op3val:0x8400; valaddr_reg:x2; val_offset:12165*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12165*FLEN/8, x3, x1, x4) + +inst_4090: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x1; +op3val:0x401; valaddr_reg:x2; val_offset:12168*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12168*FLEN/8, x3, x1, x4) + +inst_4091: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x1; +op3val:0x8455; valaddr_reg:x2; val_offset:12171*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12171*FLEN/8, x3, x1, x4) + +inst_4092: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x1; +op3val:0x7bff; valaddr_reg:x2; val_offset:12174*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12174*FLEN/8, x3, x1, x4) + +inst_4093: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x1; +op3val:0xfbff; valaddr_reg:x2; val_offset:12177*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12177*FLEN/8, x3, x1, x4) + +inst_4094: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x1; +op3val:0x7c00; valaddr_reg:x2; val_offset:12180*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12180*FLEN/8, x3, x1, x4) + +inst_4095: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x1; +op3val:0xfc00; valaddr_reg:x2; val_offset:12183*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12183*FLEN/8, x3, x1, x4) + +inst_4096: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x1; +op3val:0x7e00; valaddr_reg:x2; val_offset:12186*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12186*FLEN/8, x3, x1, x4) + +inst_4097: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x1; +op3val:0xfe00; valaddr_reg:x2; val_offset:12189*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12189*FLEN/8, x3, x1, x4) + +inst_4098: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x1; +op3val:0x7e01; valaddr_reg:x2; val_offset:12192*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12192*FLEN/8, x3, x1, x4) + +inst_4099: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x1; +op3val:0xfe55; valaddr_reg:x2; val_offset:12195*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12195*FLEN/8, x3, x1, x4) + +inst_4100: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x1; +op3val:0x7c01; valaddr_reg:x2; val_offset:12198*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12198*FLEN/8, x3, x1, x4) + +inst_4101: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x1; +op3val:0xfd55; valaddr_reg:x2; val_offset:12201*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12201*FLEN/8, x3, x1, x4) + +inst_4102: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x1; +op3val:0x3c00; valaddr_reg:x2; val_offset:12204*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12204*FLEN/8, x3, x1, x4) + +inst_4103: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x1; +op3val:0xbc00; valaddr_reg:x2; val_offset:12207*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12207*FLEN/8, x3, x1, x4) + +inst_4104: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8001; +op3val:0x0; valaddr_reg:x2; val_offset:12210*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12210*FLEN/8, x3, x1, x4) + +inst_4105: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8001; +op3val:0x8000; valaddr_reg:x2; val_offset:12213*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12213*FLEN/8, x3, x1, x4) + +inst_4106: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8001; +op3val:0x1; valaddr_reg:x2; val_offset:12216*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12216*FLEN/8, x3, x1, x4) + +inst_4107: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8001; +op3val:0x8001; valaddr_reg:x2; val_offset:12219*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12219*FLEN/8, x3, x1, x4) + +inst_4108: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8001; +op3val:0x2; valaddr_reg:x2; val_offset:12222*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12222*FLEN/8, x3, x1, x4) + +inst_4109: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8001; +op3val:0x83fe; valaddr_reg:x2; val_offset:12225*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12225*FLEN/8, x3, x1, x4) + +inst_4110: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8001; +op3val:0x3ff; valaddr_reg:x2; val_offset:12228*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12228*FLEN/8, x3, x1, x4) + +inst_4111: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8001; +op3val:0x83ff; valaddr_reg:x2; val_offset:12231*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12231*FLEN/8, x3, x1, x4) + +inst_4112: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8001; +op3val:0x400; valaddr_reg:x2; val_offset:12234*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12234*FLEN/8, x3, x1, x4) + +inst_4113: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8001; +op3val:0x8400; valaddr_reg:x2; val_offset:12237*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12237*FLEN/8, x3, x1, x4) + +inst_4114: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8001; +op3val:0x401; valaddr_reg:x2; val_offset:12240*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12240*FLEN/8, x3, x1, x4) + +inst_4115: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8001; +op3val:0x8455; valaddr_reg:x2; val_offset:12243*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12243*FLEN/8, x3, x1, x4) + +inst_4116: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8001; +op3val:0x7bff; valaddr_reg:x2; val_offset:12246*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12246*FLEN/8, x3, x1, x4) + +inst_4117: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8001; +op3val:0xfbff; valaddr_reg:x2; val_offset:12249*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12249*FLEN/8, x3, x1, x4) + +inst_4118: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8001; +op3val:0x7c00; valaddr_reg:x2; val_offset:12252*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12252*FLEN/8, x3, x1, x4) + +inst_4119: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8001; +op3val:0xfc00; valaddr_reg:x2; val_offset:12255*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12255*FLEN/8, x3, x1, x4) + +inst_4120: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8001; +op3val:0x7e00; valaddr_reg:x2; val_offset:12258*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12258*FLEN/8, x3, x1, x4) + +inst_4121: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8001; +op3val:0xfe00; valaddr_reg:x2; val_offset:12261*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12261*FLEN/8, x3, x1, x4) + +inst_4122: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8001; +op3val:0x7e01; valaddr_reg:x2; val_offset:12264*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12264*FLEN/8, x3, x1, x4) + +inst_4123: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8001; +op3val:0xfe55; valaddr_reg:x2; val_offset:12267*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12267*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_33) + +inst_4124: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8001; +op3val:0x7c01; valaddr_reg:x2; val_offset:12270*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12270*FLEN/8, x3, x1, x4) + +inst_4125: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8001; +op3val:0xfd55; valaddr_reg:x2; val_offset:12273*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12273*FLEN/8, x3, x1, x4) + +inst_4126: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8001; +op3val:0x3c00; valaddr_reg:x2; val_offset:12276*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12276*FLEN/8, x3, x1, x4) + +inst_4127: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8001; +op3val:0xbc00; valaddr_reg:x2; val_offset:12279*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12279*FLEN/8, x3, x1, x4) + +inst_4128: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x2; +op3val:0x0; valaddr_reg:x2; val_offset:12282*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12282*FLEN/8, x3, x1, x4) + +inst_4129: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x2; +op3val:0x8000; valaddr_reg:x2; val_offset:12285*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12285*FLEN/8, x3, x1, x4) + +inst_4130: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x2; +op3val:0x1; valaddr_reg:x2; val_offset:12288*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12288*FLEN/8, x3, x1, x4) + +inst_4131: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x2; +op3val:0x8001; valaddr_reg:x2; val_offset:12291*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12291*FLEN/8, x3, x1, x4) + +inst_4132: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x2; +op3val:0x2; valaddr_reg:x2; val_offset:12294*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12294*FLEN/8, x3, x1, x4) + +inst_4133: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x2; +op3val:0x83fe; valaddr_reg:x2; val_offset:12297*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12297*FLEN/8, x3, x1, x4) + +inst_4134: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x2; +op3val:0x3ff; valaddr_reg:x2; val_offset:12300*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12300*FLEN/8, x3, x1, x4) + +inst_4135: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x2; +op3val:0x83ff; valaddr_reg:x2; val_offset:12303*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12303*FLEN/8, x3, x1, x4) + +inst_4136: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x2; +op3val:0x400; valaddr_reg:x2; val_offset:12306*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12306*FLEN/8, x3, x1, x4) + +inst_4137: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x2; +op3val:0x8400; valaddr_reg:x2; val_offset:12309*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12309*FLEN/8, x3, x1, x4) + +inst_4138: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x2; +op3val:0x401; valaddr_reg:x2; val_offset:12312*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12312*FLEN/8, x3, x1, x4) + +inst_4139: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x2; +op3val:0x8455; valaddr_reg:x2; val_offset:12315*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12315*FLEN/8, x3, x1, x4) + +inst_4140: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x2; +op3val:0x7bff; valaddr_reg:x2; val_offset:12318*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12318*FLEN/8, x3, x1, x4) + +inst_4141: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x2; +op3val:0xfbff; valaddr_reg:x2; val_offset:12321*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12321*FLEN/8, x3, x1, x4) + +inst_4142: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x2; +op3val:0x7c00; valaddr_reg:x2; val_offset:12324*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12324*FLEN/8, x3, x1, x4) + +inst_4143: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x2; +op3val:0xfc00; valaddr_reg:x2; val_offset:12327*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12327*FLEN/8, x3, x1, x4) + +inst_4144: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x2; +op3val:0x7e00; valaddr_reg:x2; val_offset:12330*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12330*FLEN/8, x3, x1, x4) + +inst_4145: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x2; +op3val:0xfe00; valaddr_reg:x2; val_offset:12333*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12333*FLEN/8, x3, x1, x4) + +inst_4146: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x2; +op3val:0x7e01; valaddr_reg:x2; val_offset:12336*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12336*FLEN/8, x3, x1, x4) + +inst_4147: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x2; +op3val:0xfe55; valaddr_reg:x2; val_offset:12339*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12339*FLEN/8, x3, x1, x4) + +inst_4148: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x2; +op3val:0x7c01; valaddr_reg:x2; val_offset:12342*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12342*FLEN/8, x3, x1, x4) + +inst_4149: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x2; +op3val:0xfd55; valaddr_reg:x2; val_offset:12345*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12345*FLEN/8, x3, x1, x4) + +inst_4150: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x2; +op3val:0x3c00; valaddr_reg:x2; val_offset:12348*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12348*FLEN/8, x3, x1, x4) + +inst_4151: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x2; +op3val:0xbc00; valaddr_reg:x2; val_offset:12351*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12351*FLEN/8, x3, x1, x4) + +inst_4152: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x83fe; +op3val:0x0; valaddr_reg:x2; val_offset:12354*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12354*FLEN/8, x3, x1, x4) + +inst_4153: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x83fe; +op3val:0x8000; valaddr_reg:x2; val_offset:12357*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12357*FLEN/8, x3, x1, x4) + +inst_4154: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x83fe; +op3val:0x1; valaddr_reg:x2; val_offset:12360*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12360*FLEN/8, x3, x1, x4) + +inst_4155: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x83fe; +op3val:0x8001; valaddr_reg:x2; val_offset:12363*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12363*FLEN/8, x3, x1, x4) + +inst_4156: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x83fe; +op3val:0x2; valaddr_reg:x2; val_offset:12366*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12366*FLEN/8, x3, x1, x4) + +inst_4157: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x83fe; +op3val:0x83fe; valaddr_reg:x2; val_offset:12369*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12369*FLEN/8, x3, x1, x4) + +inst_4158: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x83fe; +op3val:0x3ff; valaddr_reg:x2; val_offset:12372*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12372*FLEN/8, x3, x1, x4) + +inst_4159: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x83fe; +op3val:0x83ff; valaddr_reg:x2; val_offset:12375*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12375*FLEN/8, x3, x1, x4) + +inst_4160: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x83fe; +op3val:0x400; valaddr_reg:x2; val_offset:12378*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12378*FLEN/8, x3, x1, x4) + +inst_4161: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x83fe; +op3val:0x8400; valaddr_reg:x2; val_offset:12381*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12381*FLEN/8, x3, x1, x4) + +inst_4162: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x83fe; +op3val:0x401; valaddr_reg:x2; val_offset:12384*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12384*FLEN/8, x3, x1, x4) + +inst_4163: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x83fe; +op3val:0x8455; valaddr_reg:x2; val_offset:12387*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12387*FLEN/8, x3, x1, x4) + +inst_4164: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x83fe; +op3val:0x7bff; valaddr_reg:x2; val_offset:12390*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12390*FLEN/8, x3, x1, x4) + +inst_4165: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x83fe; +op3val:0xfbff; valaddr_reg:x2; val_offset:12393*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12393*FLEN/8, x3, x1, x4) + +inst_4166: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x83fe; +op3val:0x7c00; valaddr_reg:x2; val_offset:12396*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12396*FLEN/8, x3, x1, x4) + +inst_4167: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x83fe; +op3val:0xfc00; valaddr_reg:x2; val_offset:12399*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12399*FLEN/8, x3, x1, x4) + +inst_4168: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x83fe; +op3val:0x7e00; valaddr_reg:x2; val_offset:12402*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12402*FLEN/8, x3, x1, x4) + +inst_4169: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x83fe; +op3val:0xfe00; valaddr_reg:x2; val_offset:12405*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12405*FLEN/8, x3, x1, x4) + +inst_4170: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x83fe; +op3val:0x7e01; valaddr_reg:x2; val_offset:12408*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12408*FLEN/8, x3, x1, x4) + +inst_4171: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x83fe; +op3val:0xfe55; valaddr_reg:x2; val_offset:12411*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12411*FLEN/8, x3, x1, x4) + +inst_4172: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x83fe; +op3val:0x7c01; valaddr_reg:x2; val_offset:12414*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12414*FLEN/8, x3, x1, x4) + +inst_4173: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x83fe; +op3val:0xfd55; valaddr_reg:x2; val_offset:12417*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12417*FLEN/8, x3, x1, x4) + +inst_4174: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x83fe; +op3val:0x3c00; valaddr_reg:x2; val_offset:12420*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12420*FLEN/8, x3, x1, x4) + +inst_4175: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x83fe; +op3val:0xbc00; valaddr_reg:x2; val_offset:12423*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12423*FLEN/8, x3, x1, x4) + +inst_4176: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x3ff; +op3val:0x0; valaddr_reg:x2; val_offset:12426*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12426*FLEN/8, x3, x1, x4) + +inst_4177: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x3ff; +op3val:0x8000; valaddr_reg:x2; val_offset:12429*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12429*FLEN/8, x3, x1, x4) + +inst_4178: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x3ff; +op3val:0x1; valaddr_reg:x2; val_offset:12432*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12432*FLEN/8, x3, x1, x4) + +inst_4179: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x3ff; +op3val:0x8001; valaddr_reg:x2; val_offset:12435*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12435*FLEN/8, x3, x1, x4) + +inst_4180: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x3ff; +op3val:0x2; valaddr_reg:x2; val_offset:12438*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12438*FLEN/8, x3, x1, x4) + +inst_4181: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x3ff; +op3val:0x83fe; valaddr_reg:x2; val_offset:12441*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12441*FLEN/8, x3, x1, x4) + +inst_4182: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x3ff; +op3val:0x3ff; valaddr_reg:x2; val_offset:12444*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12444*FLEN/8, x3, x1, x4) + +inst_4183: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x3ff; +op3val:0x83ff; valaddr_reg:x2; val_offset:12447*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12447*FLEN/8, x3, x1, x4) + +inst_4184: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x3ff; +op3val:0x400; valaddr_reg:x2; val_offset:12450*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12450*FLEN/8, x3, x1, x4) + +inst_4185: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x3ff; +op3val:0x8400; valaddr_reg:x2; val_offset:12453*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12453*FLEN/8, x3, x1, x4) + +inst_4186: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x3ff; +op3val:0x401; valaddr_reg:x2; val_offset:12456*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12456*FLEN/8, x3, x1, x4) + +inst_4187: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x3ff; +op3val:0x8455; valaddr_reg:x2; val_offset:12459*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12459*FLEN/8, x3, x1, x4) + +inst_4188: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x3ff; +op3val:0x7bff; valaddr_reg:x2; val_offset:12462*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12462*FLEN/8, x3, x1, x4) + +inst_4189: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x3ff; +op3val:0xfbff; valaddr_reg:x2; val_offset:12465*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12465*FLEN/8, x3, x1, x4) + +inst_4190: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x3ff; +op3val:0x7c00; valaddr_reg:x2; val_offset:12468*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12468*FLEN/8, x3, x1, x4) + +inst_4191: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x3ff; +op3val:0xfc00; valaddr_reg:x2; val_offset:12471*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12471*FLEN/8, x3, x1, x4) + +inst_4192: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x3ff; +op3val:0x7e00; valaddr_reg:x2; val_offset:12474*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12474*FLEN/8, x3, x1, x4) + +inst_4193: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x3ff; +op3val:0xfe00; valaddr_reg:x2; val_offset:12477*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12477*FLEN/8, x3, x1, x4) + +inst_4194: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x3ff; +op3val:0x7e01; valaddr_reg:x2; val_offset:12480*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12480*FLEN/8, x3, x1, x4) + +inst_4195: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x3ff; +op3val:0xfe55; valaddr_reg:x2; val_offset:12483*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12483*FLEN/8, x3, x1, x4) + +inst_4196: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x3ff; +op3val:0x7c01; valaddr_reg:x2; val_offset:12486*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12486*FLEN/8, x3, x1, x4) + +inst_4197: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x3ff; +op3val:0xfd55; valaddr_reg:x2; val_offset:12489*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12489*FLEN/8, x3, x1, x4) + +inst_4198: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x3ff; +op3val:0x3c00; valaddr_reg:x2; val_offset:12492*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12492*FLEN/8, x3, x1, x4) + +inst_4199: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x3ff; +op3val:0xbc00; valaddr_reg:x2; val_offset:12495*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12495*FLEN/8, x3, x1, x4) + +inst_4200: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x83ff; +op3val:0x0; valaddr_reg:x2; val_offset:12498*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12498*FLEN/8, x3, x1, x4) + +inst_4201: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x83ff; +op3val:0x8000; valaddr_reg:x2; val_offset:12501*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12501*FLEN/8, x3, x1, x4) + +inst_4202: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x83ff; +op3val:0x1; valaddr_reg:x2; val_offset:12504*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12504*FLEN/8, x3, x1, x4) + +inst_4203: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x83ff; +op3val:0x8001; valaddr_reg:x2; val_offset:12507*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12507*FLEN/8, x3, x1, x4) + +inst_4204: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x83ff; +op3val:0x2; valaddr_reg:x2; val_offset:12510*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12510*FLEN/8, x3, x1, x4) + +inst_4205: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x83ff; +op3val:0x83fe; valaddr_reg:x2; val_offset:12513*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12513*FLEN/8, x3, x1, x4) + +inst_4206: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x83ff; +op3val:0x3ff; valaddr_reg:x2; val_offset:12516*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12516*FLEN/8, x3, x1, x4) + +inst_4207: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x83ff; +op3val:0x83ff; valaddr_reg:x2; val_offset:12519*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12519*FLEN/8, x3, x1, x4) + +inst_4208: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x83ff; +op3val:0x400; valaddr_reg:x2; val_offset:12522*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12522*FLEN/8, x3, x1, x4) + +inst_4209: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x83ff; +op3val:0x8400; valaddr_reg:x2; val_offset:12525*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12525*FLEN/8, x3, x1, x4) + +inst_4210: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x83ff; +op3val:0x401; valaddr_reg:x2; val_offset:12528*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12528*FLEN/8, x3, x1, x4) + +inst_4211: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x83ff; +op3val:0x8455; valaddr_reg:x2; val_offset:12531*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12531*FLEN/8, x3, x1, x4) + +inst_4212: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x83ff; +op3val:0x7bff; valaddr_reg:x2; val_offset:12534*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12534*FLEN/8, x3, x1, x4) + +inst_4213: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x83ff; +op3val:0xfbff; valaddr_reg:x2; val_offset:12537*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12537*FLEN/8, x3, x1, x4) + +inst_4214: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x83ff; +op3val:0x7c00; valaddr_reg:x2; val_offset:12540*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12540*FLEN/8, x3, x1, x4) + +inst_4215: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x83ff; +op3val:0xfc00; valaddr_reg:x2; val_offset:12543*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12543*FLEN/8, x3, x1, x4) + +inst_4216: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x83ff; +op3val:0x7e00; valaddr_reg:x2; val_offset:12546*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12546*FLEN/8, x3, x1, x4) + +inst_4217: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x83ff; +op3val:0xfe00; valaddr_reg:x2; val_offset:12549*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12549*FLEN/8, x3, x1, x4) + +inst_4218: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x83ff; +op3val:0x7e01; valaddr_reg:x2; val_offset:12552*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12552*FLEN/8, x3, x1, x4) + +inst_4219: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x83ff; +op3val:0xfe55; valaddr_reg:x2; val_offset:12555*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12555*FLEN/8, x3, x1, x4) + +inst_4220: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x83ff; +op3val:0x7c01; valaddr_reg:x2; val_offset:12558*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12558*FLEN/8, x3, x1, x4) + +inst_4221: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x83ff; +op3val:0xfd55; valaddr_reg:x2; val_offset:12561*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12561*FLEN/8, x3, x1, x4) + +inst_4222: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x83ff; +op3val:0x3c00; valaddr_reg:x2; val_offset:12564*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12564*FLEN/8, x3, x1, x4) + +inst_4223: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x83ff; +op3val:0xbc00; valaddr_reg:x2; val_offset:12567*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12567*FLEN/8, x3, x1, x4) + +inst_4224: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x400; +op3val:0x0; valaddr_reg:x2; val_offset:12570*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12570*FLEN/8, x3, x1, x4) + +inst_4225: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x400; +op3val:0x8000; valaddr_reg:x2; val_offset:12573*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12573*FLEN/8, x3, x1, x4) + +inst_4226: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x400; +op3val:0x1; valaddr_reg:x2; val_offset:12576*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12576*FLEN/8, x3, x1, x4) + +inst_4227: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x400; +op3val:0x8001; valaddr_reg:x2; val_offset:12579*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12579*FLEN/8, x3, x1, x4) + +inst_4228: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x400; +op3val:0x2; valaddr_reg:x2; val_offset:12582*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12582*FLEN/8, x3, x1, x4) + +inst_4229: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x400; +op3val:0x83fe; valaddr_reg:x2; val_offset:12585*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12585*FLEN/8, x3, x1, x4) + +inst_4230: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x400; +op3val:0x3ff; valaddr_reg:x2; val_offset:12588*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12588*FLEN/8, x3, x1, x4) + +inst_4231: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x400; +op3val:0x83ff; valaddr_reg:x2; val_offset:12591*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12591*FLEN/8, x3, x1, x4) + +inst_4232: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x400; +op3val:0x400; valaddr_reg:x2; val_offset:12594*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12594*FLEN/8, x3, x1, x4) + +inst_4233: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x400; +op3val:0x8400; valaddr_reg:x2; val_offset:12597*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12597*FLEN/8, x3, x1, x4) + +inst_4234: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x400; +op3val:0x401; valaddr_reg:x2; val_offset:12600*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12600*FLEN/8, x3, x1, x4) + +inst_4235: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x400; +op3val:0x8455; valaddr_reg:x2; val_offset:12603*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12603*FLEN/8, x3, x1, x4) + +inst_4236: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x400; +op3val:0x7bff; valaddr_reg:x2; val_offset:12606*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12606*FLEN/8, x3, x1, x4) + +inst_4237: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x400; +op3val:0xfbff; valaddr_reg:x2; val_offset:12609*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12609*FLEN/8, x3, x1, x4) + +inst_4238: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x400; +op3val:0x7c00; valaddr_reg:x2; val_offset:12612*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12612*FLEN/8, x3, x1, x4) + +inst_4239: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x400; +op3val:0xfc00; valaddr_reg:x2; val_offset:12615*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12615*FLEN/8, x3, x1, x4) + +inst_4240: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x400; +op3val:0x7e00; valaddr_reg:x2; val_offset:12618*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12618*FLEN/8, x3, x1, x4) + +inst_4241: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x400; +op3val:0xfe00; valaddr_reg:x2; val_offset:12621*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12621*FLEN/8, x3, x1, x4) + +inst_4242: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x400; +op3val:0x7e01; valaddr_reg:x2; val_offset:12624*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12624*FLEN/8, x3, x1, x4) + +inst_4243: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x400; +op3val:0xfe55; valaddr_reg:x2; val_offset:12627*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12627*FLEN/8, x3, x1, x4) + +inst_4244: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x400; +op3val:0x7c01; valaddr_reg:x2; val_offset:12630*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12630*FLEN/8, x3, x1, x4) + +inst_4245: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x400; +op3val:0xfd55; valaddr_reg:x2; val_offset:12633*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12633*FLEN/8, x3, x1, x4) + +inst_4246: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x400; +op3val:0x3c00; valaddr_reg:x2; val_offset:12636*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12636*FLEN/8, x3, x1, x4) + +inst_4247: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x400; +op3val:0xbc00; valaddr_reg:x2; val_offset:12639*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12639*FLEN/8, x3, x1, x4) + +inst_4248: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8400; +op3val:0x0; valaddr_reg:x2; val_offset:12642*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12642*FLEN/8, x3, x1, x4) + +inst_4249: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8400; +op3val:0x8000; valaddr_reg:x2; val_offset:12645*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12645*FLEN/8, x3, x1, x4) + +inst_4250: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8400; +op3val:0x1; valaddr_reg:x2; val_offset:12648*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12648*FLEN/8, x3, x1, x4) + +inst_4251: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8400; +op3val:0x8001; valaddr_reg:x2; val_offset:12651*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12651*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_34) + +inst_4252: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8400; +op3val:0x2; valaddr_reg:x2; val_offset:12654*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12654*FLEN/8, x3, x1, x4) + +inst_4253: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8400; +op3val:0x83fe; valaddr_reg:x2; val_offset:12657*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12657*FLEN/8, x3, x1, x4) + +inst_4254: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8400; +op3val:0x3ff; valaddr_reg:x2; val_offset:12660*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12660*FLEN/8, x3, x1, x4) + +inst_4255: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8400; +op3val:0x83ff; valaddr_reg:x2; val_offset:12663*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12663*FLEN/8, x3, x1, x4) + +inst_4256: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8400; +op3val:0x400; valaddr_reg:x2; val_offset:12666*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12666*FLEN/8, x3, x1, x4) + +inst_4257: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8400; +op3val:0x8400; valaddr_reg:x2; val_offset:12669*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12669*FLEN/8, x3, x1, x4) + +inst_4258: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8400; +op3val:0x401; valaddr_reg:x2; val_offset:12672*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12672*FLEN/8, x3, x1, x4) + +inst_4259: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8400; +op3val:0x8455; valaddr_reg:x2; val_offset:12675*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12675*FLEN/8, x3, x1, x4) + +inst_4260: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8400; +op3val:0x7bff; valaddr_reg:x2; val_offset:12678*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12678*FLEN/8, x3, x1, x4) + +inst_4261: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8400; +op3val:0xfbff; valaddr_reg:x2; val_offset:12681*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12681*FLEN/8, x3, x1, x4) + +inst_4262: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8400; +op3val:0x7c00; valaddr_reg:x2; val_offset:12684*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12684*FLEN/8, x3, x1, x4) + +inst_4263: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8400; +op3val:0xfc00; valaddr_reg:x2; val_offset:12687*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12687*FLEN/8, x3, x1, x4) + +inst_4264: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8400; +op3val:0x7e00; valaddr_reg:x2; val_offset:12690*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12690*FLEN/8, x3, x1, x4) + +inst_4265: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8400; +op3val:0xfe00; valaddr_reg:x2; val_offset:12693*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12693*FLEN/8, x3, x1, x4) + +inst_4266: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8400; +op3val:0x7e01; valaddr_reg:x2; val_offset:12696*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12696*FLEN/8, x3, x1, x4) + +inst_4267: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8400; +op3val:0xfe55; valaddr_reg:x2; val_offset:12699*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12699*FLEN/8, x3, x1, x4) + +inst_4268: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8400; +op3val:0x7c01; valaddr_reg:x2; val_offset:12702*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12702*FLEN/8, x3, x1, x4) + +inst_4269: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8400; +op3val:0xfd55; valaddr_reg:x2; val_offset:12705*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12705*FLEN/8, x3, x1, x4) + +inst_4270: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8400; +op3val:0x3c00; valaddr_reg:x2; val_offset:12708*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12708*FLEN/8, x3, x1, x4) + +inst_4271: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8400; +op3val:0xbc00; valaddr_reg:x2; val_offset:12711*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12711*FLEN/8, x3, x1, x4) + +inst_4272: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x401; +op3val:0x0; valaddr_reg:x2; val_offset:12714*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12714*FLEN/8, x3, x1, x4) + +inst_4273: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x401; +op3val:0x8000; valaddr_reg:x2; val_offset:12717*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12717*FLEN/8, x3, x1, x4) + +inst_4274: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x401; +op3val:0x1; valaddr_reg:x2; val_offset:12720*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12720*FLEN/8, x3, x1, x4) + +inst_4275: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x401; +op3val:0x8001; valaddr_reg:x2; val_offset:12723*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12723*FLEN/8, x3, x1, x4) + +inst_4276: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x401; +op3val:0x2; valaddr_reg:x2; val_offset:12726*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12726*FLEN/8, x3, x1, x4) + +inst_4277: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x401; +op3val:0x83fe; valaddr_reg:x2; val_offset:12729*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12729*FLEN/8, x3, x1, x4) + +inst_4278: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x401; +op3val:0x3ff; valaddr_reg:x2; val_offset:12732*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12732*FLEN/8, x3, x1, x4) + +inst_4279: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x401; +op3val:0x83ff; valaddr_reg:x2; val_offset:12735*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12735*FLEN/8, x3, x1, x4) + +inst_4280: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x401; +op3val:0x400; valaddr_reg:x2; val_offset:12738*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12738*FLEN/8, x3, x1, x4) + +inst_4281: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x401; +op3val:0x8400; valaddr_reg:x2; val_offset:12741*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12741*FLEN/8, x3, x1, x4) + +inst_4282: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x401; +op3val:0x401; valaddr_reg:x2; val_offset:12744*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12744*FLEN/8, x3, x1, x4) + +inst_4283: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x401; +op3val:0x8455; valaddr_reg:x2; val_offset:12747*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12747*FLEN/8, x3, x1, x4) + +inst_4284: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x401; +op3val:0x7bff; valaddr_reg:x2; val_offset:12750*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12750*FLEN/8, x3, x1, x4) + +inst_4285: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x401; +op3val:0xfbff; valaddr_reg:x2; val_offset:12753*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12753*FLEN/8, x3, x1, x4) + +inst_4286: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x401; +op3val:0x7c00; valaddr_reg:x2; val_offset:12756*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12756*FLEN/8, x3, x1, x4) + +inst_4287: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x401; +op3val:0xfc00; valaddr_reg:x2; val_offset:12759*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12759*FLEN/8, x3, x1, x4) + +inst_4288: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x401; +op3val:0x7e00; valaddr_reg:x2; val_offset:12762*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12762*FLEN/8, x3, x1, x4) + +inst_4289: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x401; +op3val:0xfe00; valaddr_reg:x2; val_offset:12765*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12765*FLEN/8, x3, x1, x4) + +inst_4290: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x401; +op3val:0x7e01; valaddr_reg:x2; val_offset:12768*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12768*FLEN/8, x3, x1, x4) + +inst_4291: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x401; +op3val:0xfe55; valaddr_reg:x2; val_offset:12771*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12771*FLEN/8, x3, x1, x4) + +inst_4292: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x401; +op3val:0x7c01; valaddr_reg:x2; val_offset:12774*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12774*FLEN/8, x3, x1, x4) + +inst_4293: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x401; +op3val:0xfd55; valaddr_reg:x2; val_offset:12777*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12777*FLEN/8, x3, x1, x4) + +inst_4294: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x401; +op3val:0x3c00; valaddr_reg:x2; val_offset:12780*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12780*FLEN/8, x3, x1, x4) + +inst_4295: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x401; +op3val:0xbc00; valaddr_reg:x2; val_offset:12783*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12783*FLEN/8, x3, x1, x4) + +inst_4296: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8455; +op3val:0x0; valaddr_reg:x2; val_offset:12786*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12786*FLEN/8, x3, x1, x4) + +inst_4297: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8455; +op3val:0x8000; valaddr_reg:x2; val_offset:12789*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12789*FLEN/8, x3, x1, x4) + +inst_4298: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8455; +op3val:0x1; valaddr_reg:x2; val_offset:12792*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12792*FLEN/8, x3, x1, x4) + +inst_4299: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8455; +op3val:0x8001; valaddr_reg:x2; val_offset:12795*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12795*FLEN/8, x3, x1, x4) + +inst_4300: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8455; +op3val:0x2; valaddr_reg:x2; val_offset:12798*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12798*FLEN/8, x3, x1, x4) + +inst_4301: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8455; +op3val:0x83fe; valaddr_reg:x2; val_offset:12801*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12801*FLEN/8, x3, x1, x4) + +inst_4302: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8455; +op3val:0x3ff; valaddr_reg:x2; val_offset:12804*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12804*FLEN/8, x3, x1, x4) + +inst_4303: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8455; +op3val:0x83ff; valaddr_reg:x2; val_offset:12807*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12807*FLEN/8, x3, x1, x4) + +inst_4304: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8455; +op3val:0x400; valaddr_reg:x2; val_offset:12810*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12810*FLEN/8, x3, x1, x4) + +inst_4305: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8455; +op3val:0x8400; valaddr_reg:x2; val_offset:12813*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12813*FLEN/8, x3, x1, x4) + +inst_4306: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8455; +op3val:0x401; valaddr_reg:x2; val_offset:12816*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12816*FLEN/8, x3, x1, x4) + +inst_4307: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8455; +op3val:0x8455; valaddr_reg:x2; val_offset:12819*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12819*FLEN/8, x3, x1, x4) + +inst_4308: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8455; +op3val:0x7bff; valaddr_reg:x2; val_offset:12822*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12822*FLEN/8, x3, x1, x4) + +inst_4309: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8455; +op3val:0xfbff; valaddr_reg:x2; val_offset:12825*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12825*FLEN/8, x3, x1, x4) + +inst_4310: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8455; +op3val:0x7c00; valaddr_reg:x2; val_offset:12828*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12828*FLEN/8, x3, x1, x4) + +inst_4311: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8455; +op3val:0xfc00; valaddr_reg:x2; val_offset:12831*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12831*FLEN/8, x3, x1, x4) + +inst_4312: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8455; +op3val:0x7e00; valaddr_reg:x2; val_offset:12834*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12834*FLEN/8, x3, x1, x4) + +inst_4313: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8455; +op3val:0xfe00; valaddr_reg:x2; val_offset:12837*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12837*FLEN/8, x3, x1, x4) + +inst_4314: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8455; +op3val:0x7e01; valaddr_reg:x2; val_offset:12840*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12840*FLEN/8, x3, x1, x4) + +inst_4315: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8455; +op3val:0xfe55; valaddr_reg:x2; val_offset:12843*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12843*FLEN/8, x3, x1, x4) + +inst_4316: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8455; +op3val:0x7c01; valaddr_reg:x2; val_offset:12846*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12846*FLEN/8, x3, x1, x4) + +inst_4317: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8455; +op3val:0xfd55; valaddr_reg:x2; val_offset:12849*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12849*FLEN/8, x3, x1, x4) + +inst_4318: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8455; +op3val:0x3c00; valaddr_reg:x2; val_offset:12852*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12852*FLEN/8, x3, x1, x4) + +inst_4319: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x8455; +op3val:0xbc00; valaddr_reg:x2; val_offset:12855*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12855*FLEN/8, x3, x1, x4) + +inst_4320: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7bff; +op3val:0x0; valaddr_reg:x2; val_offset:12858*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12858*FLEN/8, x3, x1, x4) + +inst_4321: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7bff; +op3val:0x8000; valaddr_reg:x2; val_offset:12861*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12861*FLEN/8, x3, x1, x4) + +inst_4322: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7bff; +op3val:0x1; valaddr_reg:x2; val_offset:12864*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12864*FLEN/8, x3, x1, x4) + +inst_4323: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7bff; +op3val:0x8001; valaddr_reg:x2; val_offset:12867*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12867*FLEN/8, x3, x1, x4) + +inst_4324: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7bff; +op3val:0x2; valaddr_reg:x2; val_offset:12870*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12870*FLEN/8, x3, x1, x4) + +inst_4325: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7bff; +op3val:0x83fe; valaddr_reg:x2; val_offset:12873*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12873*FLEN/8, x3, x1, x4) + +inst_4326: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7bff; +op3val:0x3ff; valaddr_reg:x2; val_offset:12876*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12876*FLEN/8, x3, x1, x4) + +inst_4327: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7bff; +op3val:0x83ff; valaddr_reg:x2; val_offset:12879*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12879*FLEN/8, x3, x1, x4) + +inst_4328: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7bff; +op3val:0x400; valaddr_reg:x2; val_offset:12882*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12882*FLEN/8, x3, x1, x4) + +inst_4329: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7bff; +op3val:0x8400; valaddr_reg:x2; val_offset:12885*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12885*FLEN/8, x3, x1, x4) + +inst_4330: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7bff; +op3val:0x401; valaddr_reg:x2; val_offset:12888*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12888*FLEN/8, x3, x1, x4) + +inst_4331: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7bff; +op3val:0x8455; valaddr_reg:x2; val_offset:12891*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12891*FLEN/8, x3, x1, x4) + +inst_4332: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7bff; +op3val:0x7bff; valaddr_reg:x2; val_offset:12894*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12894*FLEN/8, x3, x1, x4) + +inst_4333: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7bff; +op3val:0xfbff; valaddr_reg:x2; val_offset:12897*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12897*FLEN/8, x3, x1, x4) + +inst_4334: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7bff; +op3val:0x7c00; valaddr_reg:x2; val_offset:12900*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12900*FLEN/8, x3, x1, x4) + +inst_4335: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7bff; +op3val:0xfc00; valaddr_reg:x2; val_offset:12903*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12903*FLEN/8, x3, x1, x4) + +inst_4336: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7bff; +op3val:0x7e00; valaddr_reg:x2; val_offset:12906*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12906*FLEN/8, x3, x1, x4) + +inst_4337: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7bff; +op3val:0xfe00; valaddr_reg:x2; val_offset:12909*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12909*FLEN/8, x3, x1, x4) + +inst_4338: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7bff; +op3val:0x7e01; valaddr_reg:x2; val_offset:12912*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12912*FLEN/8, x3, x1, x4) + +inst_4339: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7bff; +op3val:0xfe55; valaddr_reg:x2; val_offset:12915*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12915*FLEN/8, x3, x1, x4) + +inst_4340: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7bff; +op3val:0x7c01; valaddr_reg:x2; val_offset:12918*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12918*FLEN/8, x3, x1, x4) + +inst_4341: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7bff; +op3val:0xfd55; valaddr_reg:x2; val_offset:12921*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12921*FLEN/8, x3, x1, x4) + +inst_4342: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7bff; +op3val:0x3c00; valaddr_reg:x2; val_offset:12924*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12924*FLEN/8, x3, x1, x4) + +inst_4343: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7bff; +op3val:0xbc00; valaddr_reg:x2; val_offset:12927*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12927*FLEN/8, x3, x1, x4) + +inst_4344: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfbff; +op3val:0x0; valaddr_reg:x2; val_offset:12930*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12930*FLEN/8, x3, x1, x4) + +inst_4345: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfbff; +op3val:0x8000; valaddr_reg:x2; val_offset:12933*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12933*FLEN/8, x3, x1, x4) + +inst_4346: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfbff; +op3val:0x1; valaddr_reg:x2; val_offset:12936*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12936*FLEN/8, x3, x1, x4) + +inst_4347: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfbff; +op3val:0x8001; valaddr_reg:x2; val_offset:12939*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12939*FLEN/8, x3, x1, x4) + +inst_4348: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfbff; +op3val:0x2; valaddr_reg:x2; val_offset:12942*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12942*FLEN/8, x3, x1, x4) + +inst_4349: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfbff; +op3val:0x83fe; valaddr_reg:x2; val_offset:12945*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12945*FLEN/8, x3, x1, x4) + +inst_4350: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfbff; +op3val:0x3ff; valaddr_reg:x2; val_offset:12948*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12948*FLEN/8, x3, x1, x4) + +inst_4351: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfbff; +op3val:0x83ff; valaddr_reg:x2; val_offset:12951*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12951*FLEN/8, x3, x1, x4) + +inst_4352: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfbff; +op3val:0x400; valaddr_reg:x2; val_offset:12954*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12954*FLEN/8, x3, x1, x4) + +inst_4353: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfbff; +op3val:0x8400; valaddr_reg:x2; val_offset:12957*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12957*FLEN/8, x3, x1, x4) + +inst_4354: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfbff; +op3val:0x401; valaddr_reg:x2; val_offset:12960*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12960*FLEN/8, x3, x1, x4) + +inst_4355: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfbff; +op3val:0x8455; valaddr_reg:x2; val_offset:12963*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12963*FLEN/8, x3, x1, x4) + +inst_4356: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfbff; +op3val:0x7bff; valaddr_reg:x2; val_offset:12966*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12966*FLEN/8, x3, x1, x4) + +inst_4357: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfbff; +op3val:0xfbff; valaddr_reg:x2; val_offset:12969*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12969*FLEN/8, x3, x1, x4) + +inst_4358: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfbff; +op3val:0x7c00; valaddr_reg:x2; val_offset:12972*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12972*FLEN/8, x3, x1, x4) + +inst_4359: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfbff; +op3val:0xfc00; valaddr_reg:x2; val_offset:12975*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12975*FLEN/8, x3, x1, x4) + +inst_4360: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfbff; +op3val:0x7e00; valaddr_reg:x2; val_offset:12978*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12978*FLEN/8, x3, x1, x4) + +inst_4361: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfbff; +op3val:0xfe00; valaddr_reg:x2; val_offset:12981*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12981*FLEN/8, x3, x1, x4) + +inst_4362: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfbff; +op3val:0x7e01; valaddr_reg:x2; val_offset:12984*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12984*FLEN/8, x3, x1, x4) + +inst_4363: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfbff; +op3val:0xfe55; valaddr_reg:x2; val_offset:12987*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12987*FLEN/8, x3, x1, x4) + +inst_4364: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfbff; +op3val:0x7c01; valaddr_reg:x2; val_offset:12990*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12990*FLEN/8, x3, x1, x4) + +inst_4365: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfbff; +op3val:0xfd55; valaddr_reg:x2; val_offset:12993*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12993*FLEN/8, x3, x1, x4) + +inst_4366: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfbff; +op3val:0x3c00; valaddr_reg:x2; val_offset:12996*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12996*FLEN/8, x3, x1, x4) + +inst_4367: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfbff; +op3val:0xbc00; valaddr_reg:x2; val_offset:12999*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12999*FLEN/8, x3, x1, x4) + +inst_4368: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7c00; +op3val:0x0; valaddr_reg:x2; val_offset:13002*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13002*FLEN/8, x3, x1, x4) + +inst_4369: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7c00; +op3val:0x8000; valaddr_reg:x2; val_offset:13005*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13005*FLEN/8, x3, x1, x4) + +inst_4370: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7c00; +op3val:0x1; valaddr_reg:x2; val_offset:13008*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13008*FLEN/8, x3, x1, x4) + +inst_4371: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7c00; +op3val:0x8001; valaddr_reg:x2; val_offset:13011*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13011*FLEN/8, x3, x1, x4) + +inst_4372: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7c00; +op3val:0x2; valaddr_reg:x2; val_offset:13014*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13014*FLEN/8, x3, x1, x4) + +inst_4373: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7c00; +op3val:0x83fe; valaddr_reg:x2; val_offset:13017*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13017*FLEN/8, x3, x1, x4) + +inst_4374: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7c00; +op3val:0x3ff; valaddr_reg:x2; val_offset:13020*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13020*FLEN/8, x3, x1, x4) + +inst_4375: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7c00; +op3val:0x83ff; valaddr_reg:x2; val_offset:13023*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13023*FLEN/8, x3, x1, x4) + +inst_4376: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7c00; +op3val:0x400; valaddr_reg:x2; val_offset:13026*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13026*FLEN/8, x3, x1, x4) + +inst_4377: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7c00; +op3val:0x8400; valaddr_reg:x2; val_offset:13029*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13029*FLEN/8, x3, x1, x4) + +inst_4378: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7c00; +op3val:0x401; valaddr_reg:x2; val_offset:13032*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13032*FLEN/8, x3, x1, x4) + +inst_4379: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7c00; +op3val:0x8455; valaddr_reg:x2; val_offset:13035*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13035*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_35) + +inst_4380: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7c00; +op3val:0x7bff; valaddr_reg:x2; val_offset:13038*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13038*FLEN/8, x3, x1, x4) + +inst_4381: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7c00; +op3val:0xfbff; valaddr_reg:x2; val_offset:13041*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13041*FLEN/8, x3, x1, x4) + +inst_4382: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7c00; +op3val:0x7c00; valaddr_reg:x2; val_offset:13044*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13044*FLEN/8, x3, x1, x4) + +inst_4383: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7c00; +op3val:0xfc00; valaddr_reg:x2; val_offset:13047*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13047*FLEN/8, x3, x1, x4) + +inst_4384: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7c00; +op3val:0x7e00; valaddr_reg:x2; val_offset:13050*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13050*FLEN/8, x3, x1, x4) + +inst_4385: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7c00; +op3val:0xfe00; valaddr_reg:x2; val_offset:13053*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13053*FLEN/8, x3, x1, x4) + +inst_4386: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7c00; +op3val:0x7e01; valaddr_reg:x2; val_offset:13056*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13056*FLEN/8, x3, x1, x4) + +inst_4387: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7c00; +op3val:0xfe55; valaddr_reg:x2; val_offset:13059*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13059*FLEN/8, x3, x1, x4) + +inst_4388: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7c00; +op3val:0x7c01; valaddr_reg:x2; val_offset:13062*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13062*FLEN/8, x3, x1, x4) + +inst_4389: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7c00; +op3val:0xfd55; valaddr_reg:x2; val_offset:13065*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13065*FLEN/8, x3, x1, x4) + +inst_4390: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7c00; +op3val:0x3c00; valaddr_reg:x2; val_offset:13068*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13068*FLEN/8, x3, x1, x4) + +inst_4391: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7c00; +op3val:0xbc00; valaddr_reg:x2; val_offset:13071*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13071*FLEN/8, x3, x1, x4) + +inst_4392: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfc00; +op3val:0x0; valaddr_reg:x2; val_offset:13074*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13074*FLEN/8, x3, x1, x4) + +inst_4393: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfc00; +op3val:0x8000; valaddr_reg:x2; val_offset:13077*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13077*FLEN/8, x3, x1, x4) + +inst_4394: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfc00; +op3val:0x1; valaddr_reg:x2; val_offset:13080*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13080*FLEN/8, x3, x1, x4) + +inst_4395: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfc00; +op3val:0x8001; valaddr_reg:x2; val_offset:13083*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13083*FLEN/8, x3, x1, x4) + +inst_4396: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfc00; +op3val:0x2; valaddr_reg:x2; val_offset:13086*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13086*FLEN/8, x3, x1, x4) + +inst_4397: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfc00; +op3val:0x83fe; valaddr_reg:x2; val_offset:13089*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13089*FLEN/8, x3, x1, x4) + +inst_4398: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfc00; +op3val:0x3ff; valaddr_reg:x2; val_offset:13092*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13092*FLEN/8, x3, x1, x4) + +inst_4399: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfc00; +op3val:0x83ff; valaddr_reg:x2; val_offset:13095*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13095*FLEN/8, x3, x1, x4) + +inst_4400: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfc00; +op3val:0x400; valaddr_reg:x2; val_offset:13098*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13098*FLEN/8, x3, x1, x4) + +inst_4401: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfc00; +op3val:0x8400; valaddr_reg:x2; val_offset:13101*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13101*FLEN/8, x3, x1, x4) + +inst_4402: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfc00; +op3val:0x401; valaddr_reg:x2; val_offset:13104*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13104*FLEN/8, x3, x1, x4) + +inst_4403: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfc00; +op3val:0x8455; valaddr_reg:x2; val_offset:13107*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13107*FLEN/8, x3, x1, x4) + +inst_4404: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfc00; +op3val:0x7bff; valaddr_reg:x2; val_offset:13110*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13110*FLEN/8, x3, x1, x4) + +inst_4405: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfc00; +op3val:0xfbff; valaddr_reg:x2; val_offset:13113*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13113*FLEN/8, x3, x1, x4) + +inst_4406: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfc00; +op3val:0x7c00; valaddr_reg:x2; val_offset:13116*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13116*FLEN/8, x3, x1, x4) + +inst_4407: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfc00; +op3val:0xfc00; valaddr_reg:x2; val_offset:13119*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13119*FLEN/8, x3, x1, x4) + +inst_4408: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfc00; +op3val:0x7e00; valaddr_reg:x2; val_offset:13122*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13122*FLEN/8, x3, x1, x4) + +inst_4409: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfc00; +op3val:0xfe00; valaddr_reg:x2; val_offset:13125*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13125*FLEN/8, x3, x1, x4) + +inst_4410: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfc00; +op3val:0x7e01; valaddr_reg:x2; val_offset:13128*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13128*FLEN/8, x3, x1, x4) + +inst_4411: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfc00; +op3val:0xfe55; valaddr_reg:x2; val_offset:13131*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13131*FLEN/8, x3, x1, x4) + +inst_4412: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfc00; +op3val:0x7c01; valaddr_reg:x2; val_offset:13134*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13134*FLEN/8, x3, x1, x4) + +inst_4413: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfc00; +op3val:0xfd55; valaddr_reg:x2; val_offset:13137*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13137*FLEN/8, x3, x1, x4) + +inst_4414: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfc00; +op3val:0x3c00; valaddr_reg:x2; val_offset:13140*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13140*FLEN/8, x3, x1, x4) + +inst_4415: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfc00; +op3val:0xbc00; valaddr_reg:x2; val_offset:13143*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13143*FLEN/8, x3, x1, x4) + +inst_4416: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7e00; +op3val:0x0; valaddr_reg:x2; val_offset:13146*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13146*FLEN/8, x3, x1, x4) + +inst_4417: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7e00; +op3val:0x8000; valaddr_reg:x2; val_offset:13149*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13149*FLEN/8, x3, x1, x4) + +inst_4418: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7e00; +op3val:0x1; valaddr_reg:x2; val_offset:13152*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13152*FLEN/8, x3, x1, x4) + +inst_4419: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7e00; +op3val:0x8001; valaddr_reg:x2; val_offset:13155*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13155*FLEN/8, x3, x1, x4) + +inst_4420: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7e00; +op3val:0x2; valaddr_reg:x2; val_offset:13158*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13158*FLEN/8, x3, x1, x4) + +inst_4421: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7e00; +op3val:0x83fe; valaddr_reg:x2; val_offset:13161*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13161*FLEN/8, x3, x1, x4) + +inst_4422: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7e00; +op3val:0x3ff; valaddr_reg:x2; val_offset:13164*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13164*FLEN/8, x3, x1, x4) + +inst_4423: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7e00; +op3val:0x83ff; valaddr_reg:x2; val_offset:13167*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13167*FLEN/8, x3, x1, x4) + +inst_4424: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7e00; +op3val:0x400; valaddr_reg:x2; val_offset:13170*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13170*FLEN/8, x3, x1, x4) + +inst_4425: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7e00; +op3val:0x8400; valaddr_reg:x2; val_offset:13173*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13173*FLEN/8, x3, x1, x4) + +inst_4426: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7e00; +op3val:0x401; valaddr_reg:x2; val_offset:13176*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13176*FLEN/8, x3, x1, x4) + +inst_4427: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7e00; +op3val:0x8455; valaddr_reg:x2; val_offset:13179*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13179*FLEN/8, x3, x1, x4) + +inst_4428: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7e00; +op3val:0x7bff; valaddr_reg:x2; val_offset:13182*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13182*FLEN/8, x3, x1, x4) + +inst_4429: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7e00; +op3val:0xfbff; valaddr_reg:x2; val_offset:13185*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13185*FLEN/8, x3, x1, x4) + +inst_4430: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7e00; +op3val:0x7c00; valaddr_reg:x2; val_offset:13188*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13188*FLEN/8, x3, x1, x4) + +inst_4431: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7e00; +op3val:0xfc00; valaddr_reg:x2; val_offset:13191*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13191*FLEN/8, x3, x1, x4) + +inst_4432: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7e00; +op3val:0x7e00; valaddr_reg:x2; val_offset:13194*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13194*FLEN/8, x3, x1, x4) + +inst_4433: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7e00; +op3val:0xfe00; valaddr_reg:x2; val_offset:13197*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13197*FLEN/8, x3, x1, x4) + +inst_4434: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7e00; +op3val:0x7e01; valaddr_reg:x2; val_offset:13200*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13200*FLEN/8, x3, x1, x4) + +inst_4435: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7e00; +op3val:0xfe55; valaddr_reg:x2; val_offset:13203*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13203*FLEN/8, x3, x1, x4) + +inst_4436: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7e00; +op3val:0x7c01; valaddr_reg:x2; val_offset:13206*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13206*FLEN/8, x3, x1, x4) + +inst_4437: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7e00; +op3val:0xfd55; valaddr_reg:x2; val_offset:13209*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13209*FLEN/8, x3, x1, x4) + +inst_4438: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7e00; +op3val:0x3c00; valaddr_reg:x2; val_offset:13212*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13212*FLEN/8, x3, x1, x4) + +inst_4439: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7e00; +op3val:0xbc00; valaddr_reg:x2; val_offset:13215*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13215*FLEN/8, x3, x1, x4) + +inst_4440: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfe00; +op3val:0x0; valaddr_reg:x2; val_offset:13218*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13218*FLEN/8, x3, x1, x4) + +inst_4441: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfe00; +op3val:0x8000; valaddr_reg:x2; val_offset:13221*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13221*FLEN/8, x3, x1, x4) + +inst_4442: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfe00; +op3val:0x1; valaddr_reg:x2; val_offset:13224*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13224*FLEN/8, x3, x1, x4) + +inst_4443: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfe00; +op3val:0x8001; valaddr_reg:x2; val_offset:13227*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13227*FLEN/8, x3, x1, x4) + +inst_4444: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfe00; +op3val:0x2; valaddr_reg:x2; val_offset:13230*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13230*FLEN/8, x3, x1, x4) + +inst_4445: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfe00; +op3val:0x83fe; valaddr_reg:x2; val_offset:13233*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13233*FLEN/8, x3, x1, x4) + +inst_4446: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfe00; +op3val:0x3ff; valaddr_reg:x2; val_offset:13236*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13236*FLEN/8, x3, x1, x4) + +inst_4447: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfe00; +op3val:0x83ff; valaddr_reg:x2; val_offset:13239*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13239*FLEN/8, x3, x1, x4) + +inst_4448: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfe00; +op3val:0x400; valaddr_reg:x2; val_offset:13242*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13242*FLEN/8, x3, x1, x4) + +inst_4449: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfe00; +op3val:0x8400; valaddr_reg:x2; val_offset:13245*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13245*FLEN/8, x3, x1, x4) + +inst_4450: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfe00; +op3val:0x401; valaddr_reg:x2; val_offset:13248*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13248*FLEN/8, x3, x1, x4) + +inst_4451: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfe00; +op3val:0x8455; valaddr_reg:x2; val_offset:13251*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13251*FLEN/8, x3, x1, x4) + +inst_4452: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfe00; +op3val:0x7bff; valaddr_reg:x2; val_offset:13254*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13254*FLEN/8, x3, x1, x4) + +inst_4453: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfe00; +op3val:0xfbff; valaddr_reg:x2; val_offset:13257*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13257*FLEN/8, x3, x1, x4) + +inst_4454: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfe00; +op3val:0x7c00; valaddr_reg:x2; val_offset:13260*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13260*FLEN/8, x3, x1, x4) + +inst_4455: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfe00; +op3val:0xfc00; valaddr_reg:x2; val_offset:13263*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13263*FLEN/8, x3, x1, x4) + +inst_4456: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfe00; +op3val:0x7e00; valaddr_reg:x2; val_offset:13266*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13266*FLEN/8, x3, x1, x4) + +inst_4457: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfe00; +op3val:0xfe00; valaddr_reg:x2; val_offset:13269*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13269*FLEN/8, x3, x1, x4) + +inst_4458: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfe00; +op3val:0x7e01; valaddr_reg:x2; val_offset:13272*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13272*FLEN/8, x3, x1, x4) + +inst_4459: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfe00; +op3val:0xfe55; valaddr_reg:x2; val_offset:13275*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13275*FLEN/8, x3, x1, x4) + +inst_4460: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfe00; +op3val:0x7c01; valaddr_reg:x2; val_offset:13278*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13278*FLEN/8, x3, x1, x4) + +inst_4461: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfe00; +op3val:0xfd55; valaddr_reg:x2; val_offset:13281*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13281*FLEN/8, x3, x1, x4) + +inst_4462: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfe00; +op3val:0x3c00; valaddr_reg:x2; val_offset:13284*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13284*FLEN/8, x3, x1, x4) + +inst_4463: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfe00; +op3val:0xbc00; valaddr_reg:x2; val_offset:13287*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13287*FLEN/8, x3, x1, x4) + +inst_4464: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7e01; +op3val:0x0; valaddr_reg:x2; val_offset:13290*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13290*FLEN/8, x3, x1, x4) + +inst_4465: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7e01; +op3val:0x8000; valaddr_reg:x2; val_offset:13293*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13293*FLEN/8, x3, x1, x4) + +inst_4466: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7e01; +op3val:0x1; valaddr_reg:x2; val_offset:13296*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13296*FLEN/8, x3, x1, x4) + +inst_4467: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7e01; +op3val:0x8001; valaddr_reg:x2; val_offset:13299*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13299*FLEN/8, x3, x1, x4) + +inst_4468: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7e01; +op3val:0x2; valaddr_reg:x2; val_offset:13302*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13302*FLEN/8, x3, x1, x4) + +inst_4469: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7e01; +op3val:0x83fe; valaddr_reg:x2; val_offset:13305*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13305*FLEN/8, x3, x1, x4) + +inst_4470: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7e01; +op3val:0x3ff; valaddr_reg:x2; val_offset:13308*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13308*FLEN/8, x3, x1, x4) + +inst_4471: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7e01; +op3val:0x83ff; valaddr_reg:x2; val_offset:13311*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13311*FLEN/8, x3, x1, x4) + +inst_4472: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7e01; +op3val:0x400; valaddr_reg:x2; val_offset:13314*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13314*FLEN/8, x3, x1, x4) + +inst_4473: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7e01; +op3val:0x8400; valaddr_reg:x2; val_offset:13317*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13317*FLEN/8, x3, x1, x4) + +inst_4474: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7e01; +op3val:0x401; valaddr_reg:x2; val_offset:13320*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13320*FLEN/8, x3, x1, x4) + +inst_4475: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7e01; +op3val:0x8455; valaddr_reg:x2; val_offset:13323*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13323*FLEN/8, x3, x1, x4) + +inst_4476: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7e01; +op3val:0x7bff; valaddr_reg:x2; val_offset:13326*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13326*FLEN/8, x3, x1, x4) + +inst_4477: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7e01; +op3val:0xfbff; valaddr_reg:x2; val_offset:13329*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13329*FLEN/8, x3, x1, x4) + +inst_4478: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7e01; +op3val:0x7c00; valaddr_reg:x2; val_offset:13332*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13332*FLEN/8, x3, x1, x4) + +inst_4479: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7e01; +op3val:0xfc00; valaddr_reg:x2; val_offset:13335*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13335*FLEN/8, x3, x1, x4) + +inst_4480: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7e01; +op3val:0x7e00; valaddr_reg:x2; val_offset:13338*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13338*FLEN/8, x3, x1, x4) + +inst_4481: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7e01; +op3val:0xfe00; valaddr_reg:x2; val_offset:13341*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13341*FLEN/8, x3, x1, x4) + +inst_4482: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7e01; +op3val:0x7e01; valaddr_reg:x2; val_offset:13344*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13344*FLEN/8, x3, x1, x4) + +inst_4483: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7e01; +op3val:0xfe55; valaddr_reg:x2; val_offset:13347*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13347*FLEN/8, x3, x1, x4) + +inst_4484: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7e01; +op3val:0x7c01; valaddr_reg:x2; val_offset:13350*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13350*FLEN/8, x3, x1, x4) + +inst_4485: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7e01; +op3val:0xfd55; valaddr_reg:x2; val_offset:13353*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13353*FLEN/8, x3, x1, x4) + +inst_4486: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7e01; +op3val:0x3c00; valaddr_reg:x2; val_offset:13356*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13356*FLEN/8, x3, x1, x4) + +inst_4487: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7e01; +op3val:0xbc00; valaddr_reg:x2; val_offset:13359*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13359*FLEN/8, x3, x1, x4) + +inst_4488: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfe55; +op3val:0x0; valaddr_reg:x2; val_offset:13362*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13362*FLEN/8, x3, x1, x4) + +inst_4489: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfe55; +op3val:0x8000; valaddr_reg:x2; val_offset:13365*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13365*FLEN/8, x3, x1, x4) + +inst_4490: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfe55; +op3val:0x1; valaddr_reg:x2; val_offset:13368*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13368*FLEN/8, x3, x1, x4) + +inst_4491: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfe55; +op3val:0x8001; valaddr_reg:x2; val_offset:13371*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13371*FLEN/8, x3, x1, x4) + +inst_4492: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfe55; +op3val:0x2; valaddr_reg:x2; val_offset:13374*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13374*FLEN/8, x3, x1, x4) + +inst_4493: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfe55; +op3val:0x83fe; valaddr_reg:x2; val_offset:13377*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13377*FLEN/8, x3, x1, x4) + +inst_4494: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfe55; +op3val:0x3ff; valaddr_reg:x2; val_offset:13380*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13380*FLEN/8, x3, x1, x4) + +inst_4495: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfe55; +op3val:0x83ff; valaddr_reg:x2; val_offset:13383*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13383*FLEN/8, x3, x1, x4) + +inst_4496: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfe55; +op3val:0x400; valaddr_reg:x2; val_offset:13386*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13386*FLEN/8, x3, x1, x4) + +inst_4497: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfe55; +op3val:0x8400; valaddr_reg:x2; val_offset:13389*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13389*FLEN/8, x3, x1, x4) + +inst_4498: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfe55; +op3val:0x401; valaddr_reg:x2; val_offset:13392*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13392*FLEN/8, x3, x1, x4) + +inst_4499: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfe55; +op3val:0x8455; valaddr_reg:x2; val_offset:13395*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13395*FLEN/8, x3, x1, x4) + +inst_4500: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfe55; +op3val:0x7bff; valaddr_reg:x2; val_offset:13398*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13398*FLEN/8, x3, x1, x4) + +inst_4501: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfe55; +op3val:0xfbff; valaddr_reg:x2; val_offset:13401*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13401*FLEN/8, x3, x1, x4) + +inst_4502: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfe55; +op3val:0x7c00; valaddr_reg:x2; val_offset:13404*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13404*FLEN/8, x3, x1, x4) + +inst_4503: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfe55; +op3val:0xfc00; valaddr_reg:x2; val_offset:13407*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13407*FLEN/8, x3, x1, x4) + +inst_4504: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfe55; +op3val:0x7e00; valaddr_reg:x2; val_offset:13410*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13410*FLEN/8, x3, x1, x4) + +inst_4505: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfe55; +op3val:0xfe00; valaddr_reg:x2; val_offset:13413*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13413*FLEN/8, x3, x1, x4) + +inst_4506: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfe55; +op3val:0x7e01; valaddr_reg:x2; val_offset:13416*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13416*FLEN/8, x3, x1, x4) + +inst_4507: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfe55; +op3val:0xfe55; valaddr_reg:x2; val_offset:13419*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13419*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_36) + +inst_4508: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfe55; +op3val:0x7c01; valaddr_reg:x2; val_offset:13422*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13422*FLEN/8, x3, x1, x4) + +inst_4509: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfe55; +op3val:0xfd55; valaddr_reg:x2; val_offset:13425*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13425*FLEN/8, x3, x1, x4) + +inst_4510: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfe55; +op3val:0x3c00; valaddr_reg:x2; val_offset:13428*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13428*FLEN/8, x3, x1, x4) + +inst_4511: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfe55; +op3val:0xbc00; valaddr_reg:x2; val_offset:13431*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13431*FLEN/8, x3, x1, x4) + +inst_4512: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7c01; +op3val:0x0; valaddr_reg:x2; val_offset:13434*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13434*FLEN/8, x3, x1, x4) + +inst_4513: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7c01; +op3val:0x8000; valaddr_reg:x2; val_offset:13437*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13437*FLEN/8, x3, x1, x4) + +inst_4514: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7c01; +op3val:0x1; valaddr_reg:x2; val_offset:13440*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13440*FLEN/8, x3, x1, x4) + +inst_4515: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7c01; +op3val:0x8001; valaddr_reg:x2; val_offset:13443*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13443*FLEN/8, x3, x1, x4) + +inst_4516: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7c01; +op3val:0x2; valaddr_reg:x2; val_offset:13446*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13446*FLEN/8, x3, x1, x4) + +inst_4517: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7c01; +op3val:0x83fe; valaddr_reg:x2; val_offset:13449*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13449*FLEN/8, x3, x1, x4) + +inst_4518: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7c01; +op3val:0x3ff; valaddr_reg:x2; val_offset:13452*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13452*FLEN/8, x3, x1, x4) + +inst_4519: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7c01; +op3val:0x83ff; valaddr_reg:x2; val_offset:13455*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13455*FLEN/8, x3, x1, x4) + +inst_4520: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7c01; +op3val:0x400; valaddr_reg:x2; val_offset:13458*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13458*FLEN/8, x3, x1, x4) + +inst_4521: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7c01; +op3val:0x8400; valaddr_reg:x2; val_offset:13461*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13461*FLEN/8, x3, x1, x4) + +inst_4522: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7c01; +op3val:0x401; valaddr_reg:x2; val_offset:13464*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13464*FLEN/8, x3, x1, x4) + +inst_4523: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7c01; +op3val:0x8455; valaddr_reg:x2; val_offset:13467*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13467*FLEN/8, x3, x1, x4) + +inst_4524: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7c01; +op3val:0x7bff; valaddr_reg:x2; val_offset:13470*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13470*FLEN/8, x3, x1, x4) + +inst_4525: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7c01; +op3val:0xfbff; valaddr_reg:x2; val_offset:13473*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13473*FLEN/8, x3, x1, x4) + +inst_4526: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7c01; +op3val:0x7c00; valaddr_reg:x2; val_offset:13476*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13476*FLEN/8, x3, x1, x4) + +inst_4527: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7c01; +op3val:0xfc00; valaddr_reg:x2; val_offset:13479*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13479*FLEN/8, x3, x1, x4) + +inst_4528: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7c01; +op3val:0x7e00; valaddr_reg:x2; val_offset:13482*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13482*FLEN/8, x3, x1, x4) + +inst_4529: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7c01; +op3val:0xfe00; valaddr_reg:x2; val_offset:13485*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13485*FLEN/8, x3, x1, x4) + +inst_4530: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7c01; +op3val:0x7e01; valaddr_reg:x2; val_offset:13488*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13488*FLEN/8, x3, x1, x4) + +inst_4531: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7c01; +op3val:0xfe55; valaddr_reg:x2; val_offset:13491*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13491*FLEN/8, x3, x1, x4) + +inst_4532: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7c01; +op3val:0x7c01; valaddr_reg:x2; val_offset:13494*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13494*FLEN/8, x3, x1, x4) + +inst_4533: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7c01; +op3val:0xfd55; valaddr_reg:x2; val_offset:13497*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13497*FLEN/8, x3, x1, x4) + +inst_4534: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7c01; +op3val:0x3c00; valaddr_reg:x2; val_offset:13500*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13500*FLEN/8, x3, x1, x4) + +inst_4535: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x7c01; +op3val:0xbc00; valaddr_reg:x2; val_offset:13503*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13503*FLEN/8, x3, x1, x4) + +inst_4536: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfd55; +op3val:0x0; valaddr_reg:x2; val_offset:13506*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13506*FLEN/8, x3, x1, x4) + +inst_4537: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfd55; +op3val:0x8000; valaddr_reg:x2; val_offset:13509*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13509*FLEN/8, x3, x1, x4) + +inst_4538: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfd55; +op3val:0x1; valaddr_reg:x2; val_offset:13512*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13512*FLEN/8, x3, x1, x4) + +inst_4539: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfd55; +op3val:0x8001; valaddr_reg:x2; val_offset:13515*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13515*FLEN/8, x3, x1, x4) + +inst_4540: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfd55; +op3val:0x2; valaddr_reg:x2; val_offset:13518*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13518*FLEN/8, x3, x1, x4) + +inst_4541: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfd55; +op3val:0x83fe; valaddr_reg:x2; val_offset:13521*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13521*FLEN/8, x3, x1, x4) + +inst_4542: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfd55; +op3val:0x3ff; valaddr_reg:x2; val_offset:13524*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13524*FLEN/8, x3, x1, x4) + +inst_4543: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfd55; +op3val:0x83ff; valaddr_reg:x2; val_offset:13527*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13527*FLEN/8, x3, x1, x4) + +inst_4544: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfd55; +op3val:0x400; valaddr_reg:x2; val_offset:13530*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13530*FLEN/8, x3, x1, x4) + +inst_4545: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfd55; +op3val:0x8400; valaddr_reg:x2; val_offset:13533*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13533*FLEN/8, x3, x1, x4) + +inst_4546: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfd55; +op3val:0x401; valaddr_reg:x2; val_offset:13536*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13536*FLEN/8, x3, x1, x4) + +inst_4547: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfd55; +op3val:0x8455; valaddr_reg:x2; val_offset:13539*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13539*FLEN/8, x3, x1, x4) + +inst_4548: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfd55; +op3val:0x7bff; valaddr_reg:x2; val_offset:13542*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13542*FLEN/8, x3, x1, x4) + +inst_4549: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfd55; +op3val:0xfbff; valaddr_reg:x2; val_offset:13545*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13545*FLEN/8, x3, x1, x4) + +inst_4550: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfd55; +op3val:0x7c00; valaddr_reg:x2; val_offset:13548*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13548*FLEN/8, x3, x1, x4) + +inst_4551: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfd55; +op3val:0xfc00; valaddr_reg:x2; val_offset:13551*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13551*FLEN/8, x3, x1, x4) + +inst_4552: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfd55; +op3val:0x7e00; valaddr_reg:x2; val_offset:13554*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13554*FLEN/8, x3, x1, x4) + +inst_4553: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfd55; +op3val:0xfe00; valaddr_reg:x2; val_offset:13557*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13557*FLEN/8, x3, x1, x4) + +inst_4554: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfd55; +op3val:0x7e01; valaddr_reg:x2; val_offset:13560*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13560*FLEN/8, x3, x1, x4) + +inst_4555: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfd55; +op3val:0xfe55; valaddr_reg:x2; val_offset:13563*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13563*FLEN/8, x3, x1, x4) + +inst_4556: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfd55; +op3val:0x7c01; valaddr_reg:x2; val_offset:13566*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13566*FLEN/8, x3, x1, x4) + +inst_4557: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfd55; +op3val:0xfd55; valaddr_reg:x2; val_offset:13569*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13569*FLEN/8, x3, x1, x4) + +inst_4558: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfd55; +op3val:0x3c00; valaddr_reg:x2; val_offset:13572*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13572*FLEN/8, x3, x1, x4) + +inst_4559: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xfd55; +op3val:0xbc00; valaddr_reg:x2; val_offset:13575*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13575*FLEN/8, x3, x1, x4) + +inst_4560: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x3c00; +op3val:0x0; valaddr_reg:x2; val_offset:13578*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13578*FLEN/8, x3, x1, x4) + +inst_4561: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x3c00; +op3val:0x8000; valaddr_reg:x2; val_offset:13581*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13581*FLEN/8, x3, x1, x4) + +inst_4562: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x3c00; +op3val:0x1; valaddr_reg:x2; val_offset:13584*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13584*FLEN/8, x3, x1, x4) + +inst_4563: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x3c00; +op3val:0x8001; valaddr_reg:x2; val_offset:13587*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13587*FLEN/8, x3, x1, x4) + +inst_4564: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x3c00; +op3val:0x2; valaddr_reg:x2; val_offset:13590*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13590*FLEN/8, x3, x1, x4) + +inst_4565: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x3c00; +op3val:0x83fe; valaddr_reg:x2; val_offset:13593*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13593*FLEN/8, x3, x1, x4) + +inst_4566: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x3c00; +op3val:0x3ff; valaddr_reg:x2; val_offset:13596*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13596*FLEN/8, x3, x1, x4) + +inst_4567: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x3c00; +op3val:0x83ff; valaddr_reg:x2; val_offset:13599*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13599*FLEN/8, x3, x1, x4) + +inst_4568: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x3c00; +op3val:0x400; valaddr_reg:x2; val_offset:13602*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13602*FLEN/8, x3, x1, x4) + +inst_4569: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x3c00; +op3val:0x8400; valaddr_reg:x2; val_offset:13605*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13605*FLEN/8, x3, x1, x4) + +inst_4570: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x3c00; +op3val:0x401; valaddr_reg:x2; val_offset:13608*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13608*FLEN/8, x3, x1, x4) + +inst_4571: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x3c00; +op3val:0x8455; valaddr_reg:x2; val_offset:13611*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13611*FLEN/8, x3, x1, x4) + +inst_4572: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x3c00; +op3val:0x7bff; valaddr_reg:x2; val_offset:13614*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13614*FLEN/8, x3, x1, x4) + +inst_4573: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x3c00; +op3val:0xfbff; valaddr_reg:x2; val_offset:13617*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13617*FLEN/8, x3, x1, x4) + +inst_4574: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x3c00; +op3val:0x7c00; valaddr_reg:x2; val_offset:13620*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13620*FLEN/8, x3, x1, x4) + +inst_4575: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x3c00; +op3val:0xfc00; valaddr_reg:x2; val_offset:13623*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13623*FLEN/8, x3, x1, x4) + +inst_4576: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x3c00; +op3val:0x7e00; valaddr_reg:x2; val_offset:13626*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13626*FLEN/8, x3, x1, x4) + +inst_4577: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x3c00; +op3val:0xfe00; valaddr_reg:x2; val_offset:13629*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13629*FLEN/8, x3, x1, x4) + +inst_4578: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x3c00; +op3val:0x7e01; valaddr_reg:x2; val_offset:13632*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13632*FLEN/8, x3, x1, x4) + +inst_4579: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x3c00; +op3val:0xfe55; valaddr_reg:x2; val_offset:13635*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13635*FLEN/8, x3, x1, x4) + +inst_4580: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x3c00; +op3val:0x7c01; valaddr_reg:x2; val_offset:13638*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13638*FLEN/8, x3, x1, x4) + +inst_4581: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x3c00; +op3val:0xfd55; valaddr_reg:x2; val_offset:13641*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13641*FLEN/8, x3, x1, x4) + +inst_4582: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x3c00; +op3val:0x3c00; valaddr_reg:x2; val_offset:13644*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13644*FLEN/8, x3, x1, x4) + +inst_4583: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0x3c00; +op3val:0xbc00; valaddr_reg:x2; val_offset:13647*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13647*FLEN/8, x3, x1, x4) + +inst_4584: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xbc00; +op3val:0x0; valaddr_reg:x2; val_offset:13650*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13650*FLEN/8, x3, x1, x4) + +inst_4585: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xbc00; +op3val:0x8000; valaddr_reg:x2; val_offset:13653*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13653*FLEN/8, x3, x1, x4) + +inst_4586: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xbc00; +op3val:0x1; valaddr_reg:x2; val_offset:13656*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13656*FLEN/8, x3, x1, x4) + +inst_4587: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xbc00; +op3val:0x8001; valaddr_reg:x2; val_offset:13659*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13659*FLEN/8, x3, x1, x4) + +inst_4588: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xbc00; +op3val:0x2; valaddr_reg:x2; val_offset:13662*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13662*FLEN/8, x3, x1, x4) + +inst_4589: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xbc00; +op3val:0x83fe; valaddr_reg:x2; val_offset:13665*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13665*FLEN/8, x3, x1, x4) + +inst_4590: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xbc00; +op3val:0x3ff; valaddr_reg:x2; val_offset:13668*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13668*FLEN/8, x3, x1, x4) + +inst_4591: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xbc00; +op3val:0x83ff; valaddr_reg:x2; val_offset:13671*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13671*FLEN/8, x3, x1, x4) + +inst_4592: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xbc00; +op3val:0x400; valaddr_reg:x2; val_offset:13674*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13674*FLEN/8, x3, x1, x4) + +inst_4593: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xbc00; +op3val:0x8400; valaddr_reg:x2; val_offset:13677*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13677*FLEN/8, x3, x1, x4) + +inst_4594: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xbc00; +op3val:0x401; valaddr_reg:x2; val_offset:13680*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13680*FLEN/8, x3, x1, x4) + +inst_4595: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xbc00; +op3val:0x8455; valaddr_reg:x2; val_offset:13683*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13683*FLEN/8, x3, x1, x4) + +inst_4596: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xbc00; +op3val:0x7bff; valaddr_reg:x2; val_offset:13686*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13686*FLEN/8, x3, x1, x4) + +inst_4597: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xbc00; +op3val:0xfbff; valaddr_reg:x2; val_offset:13689*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13689*FLEN/8, x3, x1, x4) + +inst_4598: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xbc00; +op3val:0x7c00; valaddr_reg:x2; val_offset:13692*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13692*FLEN/8, x3, x1, x4) + +inst_4599: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xbc00; +op3val:0xfc00; valaddr_reg:x2; val_offset:13695*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13695*FLEN/8, x3, x1, x4) + +inst_4600: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xbc00; +op3val:0x7e00; valaddr_reg:x2; val_offset:13698*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13698*FLEN/8, x3, x1, x4) + +inst_4601: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xbc00; +op3val:0xfe00; valaddr_reg:x2; val_offset:13701*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13701*FLEN/8, x3, x1, x4) + +inst_4602: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xbc00; +op3val:0x7e01; valaddr_reg:x2; val_offset:13704*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13704*FLEN/8, x3, x1, x4) + +inst_4603: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xbc00; +op3val:0xfe55; valaddr_reg:x2; val_offset:13707*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13707*FLEN/8, x3, x1, x4) + +inst_4604: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xbc00; +op3val:0x7c01; valaddr_reg:x2; val_offset:13710*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13710*FLEN/8, x3, x1, x4) + +inst_4605: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xbc00; +op3val:0xfd55; valaddr_reg:x2; val_offset:13713*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13713*FLEN/8, x3, x1, x4) + +inst_4606: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xbc00; +op3val:0x3c00; valaddr_reg:x2; val_offset:13716*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13716*FLEN/8, x3, x1, x4) + +inst_4607: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x83ff; op2val:0xbc00; +op3val:0xbc00; valaddr_reg:x2; val_offset:13719*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13719*FLEN/8, x3, x1, x4) + +inst_4608: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x0; +op3val:0x0; valaddr_reg:x2; val_offset:13722*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13722*FLEN/8, x3, x1, x4) + +inst_4609: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x0; +op3val:0x8000; valaddr_reg:x2; val_offset:13725*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13725*FLEN/8, x3, x1, x4) + +inst_4610: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x0; +op3val:0x1; valaddr_reg:x2; val_offset:13728*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13728*FLEN/8, x3, x1, x4) + +inst_4611: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x0; +op3val:0x8001; valaddr_reg:x2; val_offset:13731*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13731*FLEN/8, x3, x1, x4) + +inst_4612: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x0; +op3val:0x2; valaddr_reg:x2; val_offset:13734*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13734*FLEN/8, x3, x1, x4) + +inst_4613: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x0; +op3val:0x83fe; valaddr_reg:x2; val_offset:13737*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13737*FLEN/8, x3, x1, x4) + +inst_4614: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x0; +op3val:0x3ff; valaddr_reg:x2; val_offset:13740*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13740*FLEN/8, x3, x1, x4) + +inst_4615: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x0; +op3val:0x83ff; valaddr_reg:x2; val_offset:13743*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13743*FLEN/8, x3, x1, x4) + +inst_4616: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x0; +op3val:0x400; valaddr_reg:x2; val_offset:13746*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13746*FLEN/8, x3, x1, x4) + +inst_4617: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x0; +op3val:0x8400; valaddr_reg:x2; val_offset:13749*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13749*FLEN/8, x3, x1, x4) + +inst_4618: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x0; +op3val:0x401; valaddr_reg:x2; val_offset:13752*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13752*FLEN/8, x3, x1, x4) + +inst_4619: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x0; +op3val:0x8455; valaddr_reg:x2; val_offset:13755*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13755*FLEN/8, x3, x1, x4) + +inst_4620: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x0; +op3val:0x7bff; valaddr_reg:x2; val_offset:13758*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13758*FLEN/8, x3, x1, x4) + +inst_4621: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x0; +op3val:0xfbff; valaddr_reg:x2; val_offset:13761*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13761*FLEN/8, x3, x1, x4) + +inst_4622: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x0; +op3val:0x7c00; valaddr_reg:x2; val_offset:13764*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13764*FLEN/8, x3, x1, x4) + +inst_4623: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x0; +op3val:0xfc00; valaddr_reg:x2; val_offset:13767*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13767*FLEN/8, x3, x1, x4) + +inst_4624: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x0; +op3val:0x7e00; valaddr_reg:x2; val_offset:13770*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13770*FLEN/8, x3, x1, x4) + +inst_4625: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x0; +op3val:0xfe00; valaddr_reg:x2; val_offset:13773*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13773*FLEN/8, x3, x1, x4) + +inst_4626: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x0; +op3val:0x7e01; valaddr_reg:x2; val_offset:13776*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13776*FLEN/8, x3, x1, x4) + +inst_4627: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x0; +op3val:0xfe55; valaddr_reg:x2; val_offset:13779*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13779*FLEN/8, x3, x1, x4) + +inst_4628: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x0; +op3val:0x7c01; valaddr_reg:x2; val_offset:13782*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13782*FLEN/8, x3, x1, x4) + +inst_4629: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x0; +op3val:0xfd55; valaddr_reg:x2; val_offset:13785*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13785*FLEN/8, x3, x1, x4) + +inst_4630: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x0; +op3val:0x3c00; valaddr_reg:x2; val_offset:13788*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13788*FLEN/8, x3, x1, x4) + +inst_4631: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x0; +op3val:0xbc00; valaddr_reg:x2; val_offset:13791*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13791*FLEN/8, x3, x1, x4) + +inst_4632: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8000; +op3val:0x0; valaddr_reg:x2; val_offset:13794*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13794*FLEN/8, x3, x1, x4) + +inst_4633: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8000; +op3val:0x8000; valaddr_reg:x2; val_offset:13797*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13797*FLEN/8, x3, x1, x4) + +inst_4634: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8000; +op3val:0x1; valaddr_reg:x2; val_offset:13800*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13800*FLEN/8, x3, x1, x4) + +inst_4635: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8000; +op3val:0x8001; valaddr_reg:x2; val_offset:13803*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13803*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_37) + +inst_4636: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8000; +op3val:0x2; valaddr_reg:x2; val_offset:13806*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13806*FLEN/8, x3, x1, x4) + +inst_4637: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8000; +op3val:0x83fe; valaddr_reg:x2; val_offset:13809*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13809*FLEN/8, x3, x1, x4) + +inst_4638: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8000; +op3val:0x3ff; valaddr_reg:x2; val_offset:13812*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13812*FLEN/8, x3, x1, x4) + +inst_4639: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8000; +op3val:0x83ff; valaddr_reg:x2; val_offset:13815*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13815*FLEN/8, x3, x1, x4) + +inst_4640: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8000; +op3val:0x400; valaddr_reg:x2; val_offset:13818*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13818*FLEN/8, x3, x1, x4) + +inst_4641: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8000; +op3val:0x8400; valaddr_reg:x2; val_offset:13821*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13821*FLEN/8, x3, x1, x4) + +inst_4642: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8000; +op3val:0x401; valaddr_reg:x2; val_offset:13824*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13824*FLEN/8, x3, x1, x4) + +inst_4643: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8000; +op3val:0x8455; valaddr_reg:x2; val_offset:13827*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13827*FLEN/8, x3, x1, x4) + +inst_4644: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x2; val_offset:13830*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13830*FLEN/8, x3, x1, x4) + +inst_4645: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x2; val_offset:13833*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13833*FLEN/8, x3, x1, x4) + +inst_4646: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8000; +op3val:0x7c00; valaddr_reg:x2; val_offset:13836*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13836*FLEN/8, x3, x1, x4) + +inst_4647: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8000; +op3val:0xfc00; valaddr_reg:x2; val_offset:13839*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13839*FLEN/8, x3, x1, x4) + +inst_4648: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8000; +op3val:0x7e00; valaddr_reg:x2; val_offset:13842*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13842*FLEN/8, x3, x1, x4) + +inst_4649: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8000; +op3val:0xfe00; valaddr_reg:x2; val_offset:13845*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13845*FLEN/8, x3, x1, x4) + +inst_4650: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8000; +op3val:0x7e01; valaddr_reg:x2; val_offset:13848*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13848*FLEN/8, x3, x1, x4) + +inst_4651: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8000; +op3val:0xfe55; valaddr_reg:x2; val_offset:13851*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13851*FLEN/8, x3, x1, x4) + +inst_4652: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8000; +op3val:0x7c01; valaddr_reg:x2; val_offset:13854*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13854*FLEN/8, x3, x1, x4) + +inst_4653: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8000; +op3val:0xfd55; valaddr_reg:x2; val_offset:13857*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13857*FLEN/8, x3, x1, x4) + +inst_4654: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8000; +op3val:0x3c00; valaddr_reg:x2; val_offset:13860*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13860*FLEN/8, x3, x1, x4) + +inst_4655: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8000; +op3val:0xbc00; valaddr_reg:x2; val_offset:13863*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13863*FLEN/8, x3, x1, x4) + +inst_4656: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x1; +op3val:0x0; valaddr_reg:x2; val_offset:13866*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13866*FLEN/8, x3, x1, x4) + +inst_4657: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x1; +op3val:0x8000; valaddr_reg:x2; val_offset:13869*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13869*FLEN/8, x3, x1, x4) + +inst_4658: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x1; +op3val:0x1; valaddr_reg:x2; val_offset:13872*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13872*FLEN/8, x3, x1, x4) + +inst_4659: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x1; +op3val:0x8001; valaddr_reg:x2; val_offset:13875*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13875*FLEN/8, x3, x1, x4) + +inst_4660: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x1; +op3val:0x2; valaddr_reg:x2; val_offset:13878*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13878*FLEN/8, x3, x1, x4) + +inst_4661: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x1; +op3val:0x83fe; valaddr_reg:x2; val_offset:13881*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13881*FLEN/8, x3, x1, x4) + +inst_4662: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x1; +op3val:0x3ff; valaddr_reg:x2; val_offset:13884*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13884*FLEN/8, x3, x1, x4) + +inst_4663: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x1; +op3val:0x83ff; valaddr_reg:x2; val_offset:13887*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13887*FLEN/8, x3, x1, x4) + +inst_4664: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x1; +op3val:0x400; valaddr_reg:x2; val_offset:13890*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13890*FLEN/8, x3, x1, x4) + +inst_4665: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x1; +op3val:0x8400; valaddr_reg:x2; val_offset:13893*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13893*FLEN/8, x3, x1, x4) + +inst_4666: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x1; +op3val:0x401; valaddr_reg:x2; val_offset:13896*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13896*FLEN/8, x3, x1, x4) + +inst_4667: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x1; +op3val:0x8455; valaddr_reg:x2; val_offset:13899*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13899*FLEN/8, x3, x1, x4) + +inst_4668: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x1; +op3val:0x7bff; valaddr_reg:x2; val_offset:13902*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13902*FLEN/8, x3, x1, x4) + +inst_4669: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x1; +op3val:0xfbff; valaddr_reg:x2; val_offset:13905*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13905*FLEN/8, x3, x1, x4) + +inst_4670: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x1; +op3val:0x7c00; valaddr_reg:x2; val_offset:13908*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13908*FLEN/8, x3, x1, x4) + +inst_4671: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x1; +op3val:0xfc00; valaddr_reg:x2; val_offset:13911*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13911*FLEN/8, x3, x1, x4) + +inst_4672: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x1; +op3val:0x7e00; valaddr_reg:x2; val_offset:13914*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13914*FLEN/8, x3, x1, x4) + +inst_4673: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x1; +op3val:0xfe00; valaddr_reg:x2; val_offset:13917*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13917*FLEN/8, x3, x1, x4) + +inst_4674: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x1; +op3val:0x7e01; valaddr_reg:x2; val_offset:13920*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13920*FLEN/8, x3, x1, x4) + +inst_4675: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x1; +op3val:0xfe55; valaddr_reg:x2; val_offset:13923*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13923*FLEN/8, x3, x1, x4) + +inst_4676: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x1; +op3val:0x7c01; valaddr_reg:x2; val_offset:13926*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13926*FLEN/8, x3, x1, x4) + +inst_4677: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x1; +op3val:0xfd55; valaddr_reg:x2; val_offset:13929*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13929*FLEN/8, x3, x1, x4) + +inst_4678: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x1; +op3val:0x3c00; valaddr_reg:x2; val_offset:13932*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13932*FLEN/8, x3, x1, x4) + +inst_4679: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x1; +op3val:0xbc00; valaddr_reg:x2; val_offset:13935*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13935*FLEN/8, x3, x1, x4) + +inst_4680: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8001; +op3val:0x0; valaddr_reg:x2; val_offset:13938*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13938*FLEN/8, x3, x1, x4) + +inst_4681: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8001; +op3val:0x8000; valaddr_reg:x2; val_offset:13941*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13941*FLEN/8, x3, x1, x4) + +inst_4682: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8001; +op3val:0x1; valaddr_reg:x2; val_offset:13944*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13944*FLEN/8, x3, x1, x4) + +inst_4683: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8001; +op3val:0x8001; valaddr_reg:x2; val_offset:13947*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13947*FLEN/8, x3, x1, x4) + +inst_4684: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8001; +op3val:0x2; valaddr_reg:x2; val_offset:13950*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13950*FLEN/8, x3, x1, x4) + +inst_4685: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8001; +op3val:0x83fe; valaddr_reg:x2; val_offset:13953*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13953*FLEN/8, x3, x1, x4) + +inst_4686: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8001; +op3val:0x3ff; valaddr_reg:x2; val_offset:13956*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13956*FLEN/8, x3, x1, x4) + +inst_4687: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8001; +op3val:0x83ff; valaddr_reg:x2; val_offset:13959*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13959*FLEN/8, x3, x1, x4) + +inst_4688: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8001; +op3val:0x400; valaddr_reg:x2; val_offset:13962*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13962*FLEN/8, x3, x1, x4) + +inst_4689: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8001; +op3val:0x8400; valaddr_reg:x2; val_offset:13965*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13965*FLEN/8, x3, x1, x4) + +inst_4690: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8001; +op3val:0x401; valaddr_reg:x2; val_offset:13968*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13968*FLEN/8, x3, x1, x4) + +inst_4691: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8001; +op3val:0x8455; valaddr_reg:x2; val_offset:13971*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13971*FLEN/8, x3, x1, x4) + +inst_4692: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8001; +op3val:0x7bff; valaddr_reg:x2; val_offset:13974*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13974*FLEN/8, x3, x1, x4) + +inst_4693: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8001; +op3val:0xfbff; valaddr_reg:x2; val_offset:13977*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13977*FLEN/8, x3, x1, x4) + +inst_4694: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8001; +op3val:0x7c00; valaddr_reg:x2; val_offset:13980*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13980*FLEN/8, x3, x1, x4) + +inst_4695: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8001; +op3val:0xfc00; valaddr_reg:x2; val_offset:13983*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13983*FLEN/8, x3, x1, x4) + +inst_4696: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8001; +op3val:0x7e00; valaddr_reg:x2; val_offset:13986*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13986*FLEN/8, x3, x1, x4) + +inst_4697: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8001; +op3val:0xfe00; valaddr_reg:x2; val_offset:13989*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13989*FLEN/8, x3, x1, x4) + +inst_4698: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8001; +op3val:0x7e01; valaddr_reg:x2; val_offset:13992*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13992*FLEN/8, x3, x1, x4) + +inst_4699: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8001; +op3val:0xfe55; valaddr_reg:x2; val_offset:13995*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13995*FLEN/8, x3, x1, x4) + +inst_4700: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8001; +op3val:0x7c01; valaddr_reg:x2; val_offset:13998*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 13998*FLEN/8, x3, x1, x4) + +inst_4701: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8001; +op3val:0xfd55; valaddr_reg:x2; val_offset:14001*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14001*FLEN/8, x3, x1, x4) + +inst_4702: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8001; +op3val:0x3c00; valaddr_reg:x2; val_offset:14004*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14004*FLEN/8, x3, x1, x4) + +inst_4703: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8001; +op3val:0xbc00; valaddr_reg:x2; val_offset:14007*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14007*FLEN/8, x3, x1, x4) + +inst_4704: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x2; +op3val:0x0; valaddr_reg:x2; val_offset:14010*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14010*FLEN/8, x3, x1, x4) + +inst_4705: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x2; +op3val:0x8000; valaddr_reg:x2; val_offset:14013*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14013*FLEN/8, x3, x1, x4) + +inst_4706: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x2; +op3val:0x1; valaddr_reg:x2; val_offset:14016*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14016*FLEN/8, x3, x1, x4) + +inst_4707: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x2; +op3val:0x8001; valaddr_reg:x2; val_offset:14019*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14019*FLEN/8, x3, x1, x4) + +inst_4708: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x2; +op3val:0x2; valaddr_reg:x2; val_offset:14022*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14022*FLEN/8, x3, x1, x4) + +inst_4709: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x2; +op3val:0x83fe; valaddr_reg:x2; val_offset:14025*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14025*FLEN/8, x3, x1, x4) + +inst_4710: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x2; +op3val:0x3ff; valaddr_reg:x2; val_offset:14028*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14028*FLEN/8, x3, x1, x4) + +inst_4711: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x2; +op3val:0x83ff; valaddr_reg:x2; val_offset:14031*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14031*FLEN/8, x3, x1, x4) + +inst_4712: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x2; +op3val:0x400; valaddr_reg:x2; val_offset:14034*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14034*FLEN/8, x3, x1, x4) + +inst_4713: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x2; +op3val:0x8400; valaddr_reg:x2; val_offset:14037*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14037*FLEN/8, x3, x1, x4) + +inst_4714: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x2; +op3val:0x401; valaddr_reg:x2; val_offset:14040*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14040*FLEN/8, x3, x1, x4) + +inst_4715: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x2; +op3val:0x8455; valaddr_reg:x2; val_offset:14043*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14043*FLEN/8, x3, x1, x4) + +inst_4716: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x2; +op3val:0x7bff; valaddr_reg:x2; val_offset:14046*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14046*FLEN/8, x3, x1, x4) + +inst_4717: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x2; +op3val:0xfbff; valaddr_reg:x2; val_offset:14049*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14049*FLEN/8, x3, x1, x4) + +inst_4718: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x2; +op3val:0x7c00; valaddr_reg:x2; val_offset:14052*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14052*FLEN/8, x3, x1, x4) + +inst_4719: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x2; +op3val:0xfc00; valaddr_reg:x2; val_offset:14055*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14055*FLEN/8, x3, x1, x4) + +inst_4720: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x2; +op3val:0x7e00; valaddr_reg:x2; val_offset:14058*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14058*FLEN/8, x3, x1, x4) + +inst_4721: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x2; +op3val:0xfe00; valaddr_reg:x2; val_offset:14061*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14061*FLEN/8, x3, x1, x4) + +inst_4722: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x2; +op3val:0x7e01; valaddr_reg:x2; val_offset:14064*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14064*FLEN/8, x3, x1, x4) + +inst_4723: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x2; +op3val:0xfe55; valaddr_reg:x2; val_offset:14067*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14067*FLEN/8, x3, x1, x4) + +inst_4724: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x2; +op3val:0x7c01; valaddr_reg:x2; val_offset:14070*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14070*FLEN/8, x3, x1, x4) + +inst_4725: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x2; +op3val:0xfd55; valaddr_reg:x2; val_offset:14073*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14073*FLEN/8, x3, x1, x4) + +inst_4726: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x2; +op3val:0x3c00; valaddr_reg:x2; val_offset:14076*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14076*FLEN/8, x3, x1, x4) + +inst_4727: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x2; +op3val:0xbc00; valaddr_reg:x2; val_offset:14079*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14079*FLEN/8, x3, x1, x4) + +inst_4728: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x83fe; +op3val:0x0; valaddr_reg:x2; val_offset:14082*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14082*FLEN/8, x3, x1, x4) + +inst_4729: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x83fe; +op3val:0x8000; valaddr_reg:x2; val_offset:14085*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14085*FLEN/8, x3, x1, x4) + +inst_4730: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x83fe; +op3val:0x1; valaddr_reg:x2; val_offset:14088*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14088*FLEN/8, x3, x1, x4) + +inst_4731: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x83fe; +op3val:0x8001; valaddr_reg:x2; val_offset:14091*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14091*FLEN/8, x3, x1, x4) + +inst_4732: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x83fe; +op3val:0x2; valaddr_reg:x2; val_offset:14094*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14094*FLEN/8, x3, x1, x4) + +inst_4733: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x83fe; +op3val:0x83fe; valaddr_reg:x2; val_offset:14097*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14097*FLEN/8, x3, x1, x4) + +inst_4734: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x83fe; +op3val:0x3ff; valaddr_reg:x2; val_offset:14100*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14100*FLEN/8, x3, x1, x4) + +inst_4735: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x83fe; +op3val:0x83ff; valaddr_reg:x2; val_offset:14103*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14103*FLEN/8, x3, x1, x4) + +inst_4736: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x83fe; +op3val:0x400; valaddr_reg:x2; val_offset:14106*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14106*FLEN/8, x3, x1, x4) + +inst_4737: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x83fe; +op3val:0x8400; valaddr_reg:x2; val_offset:14109*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14109*FLEN/8, x3, x1, x4) + +inst_4738: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x83fe; +op3val:0x401; valaddr_reg:x2; val_offset:14112*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14112*FLEN/8, x3, x1, x4) + +inst_4739: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x83fe; +op3val:0x8455; valaddr_reg:x2; val_offset:14115*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14115*FLEN/8, x3, x1, x4) + +inst_4740: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x83fe; +op3val:0x7bff; valaddr_reg:x2; val_offset:14118*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14118*FLEN/8, x3, x1, x4) + +inst_4741: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x83fe; +op3val:0xfbff; valaddr_reg:x2; val_offset:14121*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14121*FLEN/8, x3, x1, x4) + +inst_4742: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x83fe; +op3val:0x7c00; valaddr_reg:x2; val_offset:14124*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14124*FLEN/8, x3, x1, x4) + +inst_4743: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x83fe; +op3val:0xfc00; valaddr_reg:x2; val_offset:14127*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14127*FLEN/8, x3, x1, x4) + +inst_4744: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x83fe; +op3val:0x7e00; valaddr_reg:x2; val_offset:14130*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14130*FLEN/8, x3, x1, x4) + +inst_4745: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x83fe; +op3val:0xfe00; valaddr_reg:x2; val_offset:14133*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14133*FLEN/8, x3, x1, x4) + +inst_4746: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x83fe; +op3val:0x7e01; valaddr_reg:x2; val_offset:14136*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14136*FLEN/8, x3, x1, x4) + +inst_4747: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x83fe; +op3val:0xfe55; valaddr_reg:x2; val_offset:14139*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14139*FLEN/8, x3, x1, x4) + +inst_4748: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x83fe; +op3val:0x7c01; valaddr_reg:x2; val_offset:14142*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14142*FLEN/8, x3, x1, x4) + +inst_4749: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x83fe; +op3val:0xfd55; valaddr_reg:x2; val_offset:14145*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14145*FLEN/8, x3, x1, x4) + +inst_4750: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x83fe; +op3val:0x3c00; valaddr_reg:x2; val_offset:14148*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14148*FLEN/8, x3, x1, x4) + +inst_4751: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x83fe; +op3val:0xbc00; valaddr_reg:x2; val_offset:14151*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14151*FLEN/8, x3, x1, x4) + +inst_4752: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x3ff; +op3val:0x0; valaddr_reg:x2; val_offset:14154*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14154*FLEN/8, x3, x1, x4) + +inst_4753: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x3ff; +op3val:0x8000; valaddr_reg:x2; val_offset:14157*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14157*FLEN/8, x3, x1, x4) + +inst_4754: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x3ff; +op3val:0x1; valaddr_reg:x2; val_offset:14160*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14160*FLEN/8, x3, x1, x4) + +inst_4755: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x3ff; +op3val:0x8001; valaddr_reg:x2; val_offset:14163*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14163*FLEN/8, x3, x1, x4) + +inst_4756: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x3ff; +op3val:0x2; valaddr_reg:x2; val_offset:14166*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14166*FLEN/8, x3, x1, x4) + +inst_4757: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x3ff; +op3val:0x83fe; valaddr_reg:x2; val_offset:14169*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14169*FLEN/8, x3, x1, x4) + +inst_4758: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x3ff; +op3val:0x3ff; valaddr_reg:x2; val_offset:14172*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14172*FLEN/8, x3, x1, x4) + +inst_4759: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x3ff; +op3val:0x83ff; valaddr_reg:x2; val_offset:14175*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14175*FLEN/8, x3, x1, x4) + +inst_4760: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x3ff; +op3val:0x400; valaddr_reg:x2; val_offset:14178*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14178*FLEN/8, x3, x1, x4) + +inst_4761: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x3ff; +op3val:0x8400; valaddr_reg:x2; val_offset:14181*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14181*FLEN/8, x3, x1, x4) + +inst_4762: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x3ff; +op3val:0x401; valaddr_reg:x2; val_offset:14184*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14184*FLEN/8, x3, x1, x4) + +inst_4763: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x3ff; +op3val:0x8455; valaddr_reg:x2; val_offset:14187*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14187*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_38) + +inst_4764: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x3ff; +op3val:0x7bff; valaddr_reg:x2; val_offset:14190*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14190*FLEN/8, x3, x1, x4) + +inst_4765: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x3ff; +op3val:0xfbff; valaddr_reg:x2; val_offset:14193*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14193*FLEN/8, x3, x1, x4) + +inst_4766: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x3ff; +op3val:0x7c00; valaddr_reg:x2; val_offset:14196*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14196*FLEN/8, x3, x1, x4) + +inst_4767: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x3ff; +op3val:0xfc00; valaddr_reg:x2; val_offset:14199*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14199*FLEN/8, x3, x1, x4) + +inst_4768: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x3ff; +op3val:0x7e00; valaddr_reg:x2; val_offset:14202*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14202*FLEN/8, x3, x1, x4) + +inst_4769: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x3ff; +op3val:0xfe00; valaddr_reg:x2; val_offset:14205*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14205*FLEN/8, x3, x1, x4) + +inst_4770: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x3ff; +op3val:0x7e01; valaddr_reg:x2; val_offset:14208*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14208*FLEN/8, x3, x1, x4) + +inst_4771: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x3ff; +op3val:0xfe55; valaddr_reg:x2; val_offset:14211*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14211*FLEN/8, x3, x1, x4) + +inst_4772: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x3ff; +op3val:0x7c01; valaddr_reg:x2; val_offset:14214*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14214*FLEN/8, x3, x1, x4) + +inst_4773: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x3ff; +op3val:0xfd55; valaddr_reg:x2; val_offset:14217*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14217*FLEN/8, x3, x1, x4) + +inst_4774: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x3ff; +op3val:0x3c00; valaddr_reg:x2; val_offset:14220*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14220*FLEN/8, x3, x1, x4) + +inst_4775: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x3ff; +op3val:0xbc00; valaddr_reg:x2; val_offset:14223*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14223*FLEN/8, x3, x1, x4) + +inst_4776: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x83ff; +op3val:0x0; valaddr_reg:x2; val_offset:14226*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14226*FLEN/8, x3, x1, x4) + +inst_4777: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x83ff; +op3val:0x8000; valaddr_reg:x2; val_offset:14229*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14229*FLEN/8, x3, x1, x4) + +inst_4778: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x83ff; +op3val:0x1; valaddr_reg:x2; val_offset:14232*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14232*FLEN/8, x3, x1, x4) + +inst_4779: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x83ff; +op3val:0x8001; valaddr_reg:x2; val_offset:14235*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14235*FLEN/8, x3, x1, x4) + +inst_4780: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x83ff; +op3val:0x2; valaddr_reg:x2; val_offset:14238*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14238*FLEN/8, x3, x1, x4) + +inst_4781: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x83ff; +op3val:0x83fe; valaddr_reg:x2; val_offset:14241*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14241*FLEN/8, x3, x1, x4) + +inst_4782: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x83ff; +op3val:0x3ff; valaddr_reg:x2; val_offset:14244*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14244*FLEN/8, x3, x1, x4) + +inst_4783: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x83ff; +op3val:0x83ff; valaddr_reg:x2; val_offset:14247*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14247*FLEN/8, x3, x1, x4) + +inst_4784: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x83ff; +op3val:0x400; valaddr_reg:x2; val_offset:14250*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14250*FLEN/8, x3, x1, x4) + +inst_4785: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x83ff; +op3val:0x8400; valaddr_reg:x2; val_offset:14253*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14253*FLEN/8, x3, x1, x4) + +inst_4786: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x83ff; +op3val:0x401; valaddr_reg:x2; val_offset:14256*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14256*FLEN/8, x3, x1, x4) + +inst_4787: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x83ff; +op3val:0x8455; valaddr_reg:x2; val_offset:14259*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14259*FLEN/8, x3, x1, x4) + +inst_4788: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x83ff; +op3val:0x7bff; valaddr_reg:x2; val_offset:14262*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14262*FLEN/8, x3, x1, x4) + +inst_4789: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x83ff; +op3val:0xfbff; valaddr_reg:x2; val_offset:14265*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14265*FLEN/8, x3, x1, x4) + +inst_4790: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x83ff; +op3val:0x7c00; valaddr_reg:x2; val_offset:14268*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14268*FLEN/8, x3, x1, x4) + +inst_4791: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x83ff; +op3val:0xfc00; valaddr_reg:x2; val_offset:14271*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14271*FLEN/8, x3, x1, x4) + +inst_4792: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x83ff; +op3val:0x7e00; valaddr_reg:x2; val_offset:14274*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14274*FLEN/8, x3, x1, x4) + +inst_4793: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x83ff; +op3val:0xfe00; valaddr_reg:x2; val_offset:14277*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14277*FLEN/8, x3, x1, x4) + +inst_4794: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x83ff; +op3val:0x7e01; valaddr_reg:x2; val_offset:14280*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14280*FLEN/8, x3, x1, x4) + +inst_4795: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x83ff; +op3val:0xfe55; valaddr_reg:x2; val_offset:14283*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14283*FLEN/8, x3, x1, x4) + +inst_4796: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x83ff; +op3val:0x7c01; valaddr_reg:x2; val_offset:14286*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14286*FLEN/8, x3, x1, x4) + +inst_4797: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x83ff; +op3val:0xfd55; valaddr_reg:x2; val_offset:14289*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14289*FLEN/8, x3, x1, x4) + +inst_4798: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x83ff; +op3val:0x3c00; valaddr_reg:x2; val_offset:14292*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14292*FLEN/8, x3, x1, x4) + +inst_4799: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x83ff; +op3val:0xbc00; valaddr_reg:x2; val_offset:14295*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14295*FLEN/8, x3, x1, x4) + +inst_4800: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x400; +op3val:0x0; valaddr_reg:x2; val_offset:14298*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14298*FLEN/8, x3, x1, x4) + +inst_4801: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x400; +op3val:0x8000; valaddr_reg:x2; val_offset:14301*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14301*FLEN/8, x3, x1, x4) + +inst_4802: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x400; +op3val:0x1; valaddr_reg:x2; val_offset:14304*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14304*FLEN/8, x3, x1, x4) + +inst_4803: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x400; +op3val:0x8001; valaddr_reg:x2; val_offset:14307*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14307*FLEN/8, x3, x1, x4) + +inst_4804: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x400; +op3val:0x2; valaddr_reg:x2; val_offset:14310*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14310*FLEN/8, x3, x1, x4) + +inst_4805: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x400; +op3val:0x83fe; valaddr_reg:x2; val_offset:14313*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14313*FLEN/8, x3, x1, x4) + +inst_4806: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x400; +op3val:0x3ff; valaddr_reg:x2; val_offset:14316*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14316*FLEN/8, x3, x1, x4) + +inst_4807: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x400; +op3val:0x83ff; valaddr_reg:x2; val_offset:14319*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14319*FLEN/8, x3, x1, x4) + +inst_4808: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x400; +op3val:0x400; valaddr_reg:x2; val_offset:14322*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14322*FLEN/8, x3, x1, x4) + +inst_4809: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x400; +op3val:0x8400; valaddr_reg:x2; val_offset:14325*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14325*FLEN/8, x3, x1, x4) + +inst_4810: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x400; +op3val:0x401; valaddr_reg:x2; val_offset:14328*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14328*FLEN/8, x3, x1, x4) + +inst_4811: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x400; +op3val:0x8455; valaddr_reg:x2; val_offset:14331*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14331*FLEN/8, x3, x1, x4) + +inst_4812: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x400; +op3val:0x7bff; valaddr_reg:x2; val_offset:14334*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14334*FLEN/8, x3, x1, x4) + +inst_4813: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x400; +op3val:0xfbff; valaddr_reg:x2; val_offset:14337*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14337*FLEN/8, x3, x1, x4) + +inst_4814: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x400; +op3val:0x7c00; valaddr_reg:x2; val_offset:14340*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14340*FLEN/8, x3, x1, x4) + +inst_4815: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x400; +op3val:0xfc00; valaddr_reg:x2; val_offset:14343*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14343*FLEN/8, x3, x1, x4) + +inst_4816: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x400; +op3val:0x7e00; valaddr_reg:x2; val_offset:14346*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14346*FLEN/8, x3, x1, x4) + +inst_4817: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x400; +op3val:0xfe00; valaddr_reg:x2; val_offset:14349*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14349*FLEN/8, x3, x1, x4) + +inst_4818: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x400; +op3val:0x7e01; valaddr_reg:x2; val_offset:14352*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14352*FLEN/8, x3, x1, x4) + +inst_4819: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x400; +op3val:0xfe55; valaddr_reg:x2; val_offset:14355*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14355*FLEN/8, x3, x1, x4) + +inst_4820: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x400; +op3val:0x7c01; valaddr_reg:x2; val_offset:14358*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14358*FLEN/8, x3, x1, x4) + +inst_4821: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x400; +op3val:0xfd55; valaddr_reg:x2; val_offset:14361*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14361*FLEN/8, x3, x1, x4) + +inst_4822: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x400; +op3val:0x3c00; valaddr_reg:x2; val_offset:14364*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14364*FLEN/8, x3, x1, x4) + +inst_4823: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x400; +op3val:0xbc00; valaddr_reg:x2; val_offset:14367*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14367*FLEN/8, x3, x1, x4) + +inst_4824: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8400; +op3val:0x0; valaddr_reg:x2; val_offset:14370*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14370*FLEN/8, x3, x1, x4) + +inst_4825: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8400; +op3val:0x8000; valaddr_reg:x2; val_offset:14373*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14373*FLEN/8, x3, x1, x4) + +inst_4826: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8400; +op3val:0x1; valaddr_reg:x2; val_offset:14376*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14376*FLEN/8, x3, x1, x4) + +inst_4827: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8400; +op3val:0x8001; valaddr_reg:x2; val_offset:14379*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14379*FLEN/8, x3, x1, x4) + +inst_4828: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8400; +op3val:0x2; valaddr_reg:x2; val_offset:14382*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14382*FLEN/8, x3, x1, x4) + +inst_4829: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8400; +op3val:0x83fe; valaddr_reg:x2; val_offset:14385*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14385*FLEN/8, x3, x1, x4) + +inst_4830: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8400; +op3val:0x3ff; valaddr_reg:x2; val_offset:14388*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14388*FLEN/8, x3, x1, x4) + +inst_4831: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8400; +op3val:0x83ff; valaddr_reg:x2; val_offset:14391*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14391*FLEN/8, x3, x1, x4) + +inst_4832: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8400; +op3val:0x400; valaddr_reg:x2; val_offset:14394*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14394*FLEN/8, x3, x1, x4) + +inst_4833: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8400; +op3val:0x8400; valaddr_reg:x2; val_offset:14397*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14397*FLEN/8, x3, x1, x4) + +inst_4834: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8400; +op3val:0x401; valaddr_reg:x2; val_offset:14400*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14400*FLEN/8, x3, x1, x4) + +inst_4835: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8400; +op3val:0x8455; valaddr_reg:x2; val_offset:14403*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14403*FLEN/8, x3, x1, x4) + +inst_4836: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8400; +op3val:0x7bff; valaddr_reg:x2; val_offset:14406*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14406*FLEN/8, x3, x1, x4) + +inst_4837: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8400; +op3val:0xfbff; valaddr_reg:x2; val_offset:14409*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14409*FLEN/8, x3, x1, x4) + +inst_4838: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8400; +op3val:0x7c00; valaddr_reg:x2; val_offset:14412*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14412*FLEN/8, x3, x1, x4) + +inst_4839: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8400; +op3val:0xfc00; valaddr_reg:x2; val_offset:14415*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14415*FLEN/8, x3, x1, x4) + +inst_4840: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8400; +op3val:0x7e00; valaddr_reg:x2; val_offset:14418*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14418*FLEN/8, x3, x1, x4) + +inst_4841: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8400; +op3val:0xfe00; valaddr_reg:x2; val_offset:14421*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14421*FLEN/8, x3, x1, x4) + +inst_4842: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8400; +op3val:0x7e01; valaddr_reg:x2; val_offset:14424*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14424*FLEN/8, x3, x1, x4) + +inst_4843: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8400; +op3val:0xfe55; valaddr_reg:x2; val_offset:14427*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14427*FLEN/8, x3, x1, x4) + +inst_4844: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8400; +op3val:0x7c01; valaddr_reg:x2; val_offset:14430*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14430*FLEN/8, x3, x1, x4) + +inst_4845: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8400; +op3val:0xfd55; valaddr_reg:x2; val_offset:14433*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14433*FLEN/8, x3, x1, x4) + +inst_4846: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8400; +op3val:0x3c00; valaddr_reg:x2; val_offset:14436*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14436*FLEN/8, x3, x1, x4) + +inst_4847: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8400; +op3val:0xbc00; valaddr_reg:x2; val_offset:14439*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14439*FLEN/8, x3, x1, x4) + +inst_4848: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x401; +op3val:0x0; valaddr_reg:x2; val_offset:14442*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14442*FLEN/8, x3, x1, x4) + +inst_4849: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x401; +op3val:0x8000; valaddr_reg:x2; val_offset:14445*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14445*FLEN/8, x3, x1, x4) + +inst_4850: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x401; +op3val:0x1; valaddr_reg:x2; val_offset:14448*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14448*FLEN/8, x3, x1, x4) + +inst_4851: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x401; +op3val:0x8001; valaddr_reg:x2; val_offset:14451*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14451*FLEN/8, x3, x1, x4) + +inst_4852: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x401; +op3val:0x2; valaddr_reg:x2; val_offset:14454*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14454*FLEN/8, x3, x1, x4) + +inst_4853: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x401; +op3val:0x83fe; valaddr_reg:x2; val_offset:14457*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14457*FLEN/8, x3, x1, x4) + +inst_4854: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x401; +op3val:0x3ff; valaddr_reg:x2; val_offset:14460*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14460*FLEN/8, x3, x1, x4) + +inst_4855: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x401; +op3val:0x83ff; valaddr_reg:x2; val_offset:14463*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14463*FLEN/8, x3, x1, x4) + +inst_4856: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x401; +op3val:0x400; valaddr_reg:x2; val_offset:14466*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14466*FLEN/8, x3, x1, x4) + +inst_4857: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x401; +op3val:0x8400; valaddr_reg:x2; val_offset:14469*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14469*FLEN/8, x3, x1, x4) + +inst_4858: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x401; +op3val:0x401; valaddr_reg:x2; val_offset:14472*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14472*FLEN/8, x3, x1, x4) + +inst_4859: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x401; +op3val:0x8455; valaddr_reg:x2; val_offset:14475*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14475*FLEN/8, x3, x1, x4) + +inst_4860: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x401; +op3val:0x7bff; valaddr_reg:x2; val_offset:14478*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14478*FLEN/8, x3, x1, x4) + +inst_4861: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x401; +op3val:0xfbff; valaddr_reg:x2; val_offset:14481*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14481*FLEN/8, x3, x1, x4) + +inst_4862: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x401; +op3val:0x7c00; valaddr_reg:x2; val_offset:14484*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14484*FLEN/8, x3, x1, x4) + +inst_4863: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x401; +op3val:0xfc00; valaddr_reg:x2; val_offset:14487*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14487*FLEN/8, x3, x1, x4) + +inst_4864: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x401; +op3val:0x7e00; valaddr_reg:x2; val_offset:14490*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14490*FLEN/8, x3, x1, x4) + +inst_4865: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x401; +op3val:0xfe00; valaddr_reg:x2; val_offset:14493*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14493*FLEN/8, x3, x1, x4) + +inst_4866: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x401; +op3val:0x7e01; valaddr_reg:x2; val_offset:14496*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14496*FLEN/8, x3, x1, x4) + +inst_4867: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x401; +op3val:0xfe55; valaddr_reg:x2; val_offset:14499*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14499*FLEN/8, x3, x1, x4) + +inst_4868: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x401; +op3val:0x7c01; valaddr_reg:x2; val_offset:14502*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14502*FLEN/8, x3, x1, x4) + +inst_4869: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x401; +op3val:0xfd55; valaddr_reg:x2; val_offset:14505*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14505*FLEN/8, x3, x1, x4) + +inst_4870: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x401; +op3val:0x3c00; valaddr_reg:x2; val_offset:14508*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14508*FLEN/8, x3, x1, x4) + +inst_4871: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x401; +op3val:0xbc00; valaddr_reg:x2; val_offset:14511*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14511*FLEN/8, x3, x1, x4) + +inst_4872: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8455; +op3val:0x0; valaddr_reg:x2; val_offset:14514*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14514*FLEN/8, x3, x1, x4) + +inst_4873: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8455; +op3val:0x8000; valaddr_reg:x2; val_offset:14517*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14517*FLEN/8, x3, x1, x4) + +inst_4874: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8455; +op3val:0x1; valaddr_reg:x2; val_offset:14520*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14520*FLEN/8, x3, x1, x4) + +inst_4875: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8455; +op3val:0x8001; valaddr_reg:x2; val_offset:14523*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14523*FLEN/8, x3, x1, x4) + +inst_4876: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8455; +op3val:0x2; valaddr_reg:x2; val_offset:14526*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14526*FLEN/8, x3, x1, x4) + +inst_4877: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8455; +op3val:0x83fe; valaddr_reg:x2; val_offset:14529*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14529*FLEN/8, x3, x1, x4) + +inst_4878: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8455; +op3val:0x3ff; valaddr_reg:x2; val_offset:14532*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14532*FLEN/8, x3, x1, x4) + +inst_4879: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8455; +op3val:0x83ff; valaddr_reg:x2; val_offset:14535*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14535*FLEN/8, x3, x1, x4) + +inst_4880: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8455; +op3val:0x400; valaddr_reg:x2; val_offset:14538*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14538*FLEN/8, x3, x1, x4) + +inst_4881: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8455; +op3val:0x8400; valaddr_reg:x2; val_offset:14541*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14541*FLEN/8, x3, x1, x4) + +inst_4882: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8455; +op3val:0x401; valaddr_reg:x2; val_offset:14544*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14544*FLEN/8, x3, x1, x4) + +inst_4883: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8455; +op3val:0x8455; valaddr_reg:x2; val_offset:14547*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14547*FLEN/8, x3, x1, x4) + +inst_4884: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8455; +op3val:0x7bff; valaddr_reg:x2; val_offset:14550*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14550*FLEN/8, x3, x1, x4) + +inst_4885: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8455; +op3val:0xfbff; valaddr_reg:x2; val_offset:14553*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14553*FLEN/8, x3, x1, x4) + +inst_4886: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8455; +op3val:0x7c00; valaddr_reg:x2; val_offset:14556*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14556*FLEN/8, x3, x1, x4) + +inst_4887: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8455; +op3val:0xfc00; valaddr_reg:x2; val_offset:14559*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14559*FLEN/8, x3, x1, x4) + +inst_4888: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8455; +op3val:0x7e00; valaddr_reg:x2; val_offset:14562*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14562*FLEN/8, x3, x1, x4) + +inst_4889: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8455; +op3val:0xfe00; valaddr_reg:x2; val_offset:14565*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14565*FLEN/8, x3, x1, x4) + +inst_4890: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8455; +op3val:0x7e01; valaddr_reg:x2; val_offset:14568*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14568*FLEN/8, x3, x1, x4) + +inst_4891: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8455; +op3val:0xfe55; valaddr_reg:x2; val_offset:14571*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14571*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_39) + +inst_4892: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8455; +op3val:0x7c01; valaddr_reg:x2; val_offset:14574*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14574*FLEN/8, x3, x1, x4) + +inst_4893: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8455; +op3val:0xfd55; valaddr_reg:x2; val_offset:14577*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14577*FLEN/8, x3, x1, x4) + +inst_4894: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8455; +op3val:0x3c00; valaddr_reg:x2; val_offset:14580*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14580*FLEN/8, x3, x1, x4) + +inst_4895: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x8455; +op3val:0xbc00; valaddr_reg:x2; val_offset:14583*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14583*FLEN/8, x3, x1, x4) + +inst_4896: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7bff; +op3val:0x0; valaddr_reg:x2; val_offset:14586*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14586*FLEN/8, x3, x1, x4) + +inst_4897: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7bff; +op3val:0x8000; valaddr_reg:x2; val_offset:14589*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14589*FLEN/8, x3, x1, x4) + +inst_4898: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7bff; +op3val:0x1; valaddr_reg:x2; val_offset:14592*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14592*FLEN/8, x3, x1, x4) + +inst_4899: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7bff; +op3val:0x8001; valaddr_reg:x2; val_offset:14595*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14595*FLEN/8, x3, x1, x4) + +inst_4900: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7bff; +op3val:0x2; valaddr_reg:x2; val_offset:14598*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14598*FLEN/8, x3, x1, x4) + +inst_4901: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7bff; +op3val:0x83fe; valaddr_reg:x2; val_offset:14601*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14601*FLEN/8, x3, x1, x4) + +inst_4902: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7bff; +op3val:0x3ff; valaddr_reg:x2; val_offset:14604*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14604*FLEN/8, x3, x1, x4) + +inst_4903: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7bff; +op3val:0x83ff; valaddr_reg:x2; val_offset:14607*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14607*FLEN/8, x3, x1, x4) + +inst_4904: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7bff; +op3val:0x400; valaddr_reg:x2; val_offset:14610*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14610*FLEN/8, x3, x1, x4) + +inst_4905: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7bff; +op3val:0x8400; valaddr_reg:x2; val_offset:14613*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14613*FLEN/8, x3, x1, x4) + +inst_4906: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7bff; +op3val:0x401; valaddr_reg:x2; val_offset:14616*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14616*FLEN/8, x3, x1, x4) + +inst_4907: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7bff; +op3val:0x8455; valaddr_reg:x2; val_offset:14619*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14619*FLEN/8, x3, x1, x4) + +inst_4908: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7bff; +op3val:0x7bff; valaddr_reg:x2; val_offset:14622*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14622*FLEN/8, x3, x1, x4) + +inst_4909: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7bff; +op3val:0xfbff; valaddr_reg:x2; val_offset:14625*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14625*FLEN/8, x3, x1, x4) + +inst_4910: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7bff; +op3val:0x7c00; valaddr_reg:x2; val_offset:14628*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14628*FLEN/8, x3, x1, x4) + +inst_4911: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7bff; +op3val:0xfc00; valaddr_reg:x2; val_offset:14631*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14631*FLEN/8, x3, x1, x4) + +inst_4912: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7bff; +op3val:0x7e00; valaddr_reg:x2; val_offset:14634*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14634*FLEN/8, x3, x1, x4) + +inst_4913: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7bff; +op3val:0xfe00; valaddr_reg:x2; val_offset:14637*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14637*FLEN/8, x3, x1, x4) + +inst_4914: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7bff; +op3val:0x7e01; valaddr_reg:x2; val_offset:14640*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14640*FLEN/8, x3, x1, x4) + +inst_4915: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7bff; +op3val:0xfe55; valaddr_reg:x2; val_offset:14643*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14643*FLEN/8, x3, x1, x4) + +inst_4916: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7bff; +op3val:0x7c01; valaddr_reg:x2; val_offset:14646*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14646*FLEN/8, x3, x1, x4) + +inst_4917: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7bff; +op3val:0xfd55; valaddr_reg:x2; val_offset:14649*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14649*FLEN/8, x3, x1, x4) + +inst_4918: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7bff; +op3val:0x3c00; valaddr_reg:x2; val_offset:14652*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14652*FLEN/8, x3, x1, x4) + +inst_4919: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7bff; +op3val:0xbc00; valaddr_reg:x2; val_offset:14655*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14655*FLEN/8, x3, x1, x4) + +inst_4920: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfbff; +op3val:0x0; valaddr_reg:x2; val_offset:14658*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14658*FLEN/8, x3, x1, x4) + +inst_4921: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfbff; +op3val:0x8000; valaddr_reg:x2; val_offset:14661*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14661*FLEN/8, x3, x1, x4) + +inst_4922: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfbff; +op3val:0x1; valaddr_reg:x2; val_offset:14664*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14664*FLEN/8, x3, x1, x4) + +inst_4923: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfbff; +op3val:0x8001; valaddr_reg:x2; val_offset:14667*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14667*FLEN/8, x3, x1, x4) + +inst_4924: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfbff; +op3val:0x2; valaddr_reg:x2; val_offset:14670*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14670*FLEN/8, x3, x1, x4) + +inst_4925: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfbff; +op3val:0x83fe; valaddr_reg:x2; val_offset:14673*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14673*FLEN/8, x3, x1, x4) + +inst_4926: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfbff; +op3val:0x3ff; valaddr_reg:x2; val_offset:14676*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14676*FLEN/8, x3, x1, x4) + +inst_4927: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfbff; +op3val:0x83ff; valaddr_reg:x2; val_offset:14679*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14679*FLEN/8, x3, x1, x4) + +inst_4928: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfbff; +op3val:0x400; valaddr_reg:x2; val_offset:14682*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14682*FLEN/8, x3, x1, x4) + +inst_4929: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfbff; +op3val:0x8400; valaddr_reg:x2; val_offset:14685*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14685*FLEN/8, x3, x1, x4) + +inst_4930: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfbff; +op3val:0x401; valaddr_reg:x2; val_offset:14688*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14688*FLEN/8, x3, x1, x4) + +inst_4931: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfbff; +op3val:0x8455; valaddr_reg:x2; val_offset:14691*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14691*FLEN/8, x3, x1, x4) + +inst_4932: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfbff; +op3val:0x7bff; valaddr_reg:x2; val_offset:14694*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14694*FLEN/8, x3, x1, x4) + +inst_4933: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfbff; +op3val:0xfbff; valaddr_reg:x2; val_offset:14697*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14697*FLEN/8, x3, x1, x4) + +inst_4934: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfbff; +op3val:0x7c00; valaddr_reg:x2; val_offset:14700*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14700*FLEN/8, x3, x1, x4) + +inst_4935: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfbff; +op3val:0xfc00; valaddr_reg:x2; val_offset:14703*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14703*FLEN/8, x3, x1, x4) + +inst_4936: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfbff; +op3val:0x7e00; valaddr_reg:x2; val_offset:14706*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14706*FLEN/8, x3, x1, x4) + +inst_4937: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfbff; +op3val:0xfe00; valaddr_reg:x2; val_offset:14709*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14709*FLEN/8, x3, x1, x4) + +inst_4938: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfbff; +op3val:0x7e01; valaddr_reg:x2; val_offset:14712*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14712*FLEN/8, x3, x1, x4) + +inst_4939: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfbff; +op3val:0xfe55; valaddr_reg:x2; val_offset:14715*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14715*FLEN/8, x3, x1, x4) + +inst_4940: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfbff; +op3val:0x7c01; valaddr_reg:x2; val_offset:14718*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14718*FLEN/8, x3, x1, x4) + +inst_4941: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfbff; +op3val:0xfd55; valaddr_reg:x2; val_offset:14721*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14721*FLEN/8, x3, x1, x4) + +inst_4942: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfbff; +op3val:0x3c00; valaddr_reg:x2; val_offset:14724*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14724*FLEN/8, x3, x1, x4) + +inst_4943: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfbff; +op3val:0xbc00; valaddr_reg:x2; val_offset:14727*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14727*FLEN/8, x3, x1, x4) + +inst_4944: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7c00; +op3val:0x0; valaddr_reg:x2; val_offset:14730*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14730*FLEN/8, x3, x1, x4) + +inst_4945: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7c00; +op3val:0x8000; valaddr_reg:x2; val_offset:14733*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14733*FLEN/8, x3, x1, x4) + +inst_4946: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7c00; +op3val:0x1; valaddr_reg:x2; val_offset:14736*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14736*FLEN/8, x3, x1, x4) + +inst_4947: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7c00; +op3val:0x8001; valaddr_reg:x2; val_offset:14739*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14739*FLEN/8, x3, x1, x4) + +inst_4948: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7c00; +op3val:0x2; valaddr_reg:x2; val_offset:14742*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14742*FLEN/8, x3, x1, x4) + +inst_4949: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7c00; +op3val:0x83fe; valaddr_reg:x2; val_offset:14745*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14745*FLEN/8, x3, x1, x4) + +inst_4950: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7c00; +op3val:0x3ff; valaddr_reg:x2; val_offset:14748*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14748*FLEN/8, x3, x1, x4) + +inst_4951: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7c00; +op3val:0x83ff; valaddr_reg:x2; val_offset:14751*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14751*FLEN/8, x3, x1, x4) + +inst_4952: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7c00; +op3val:0x400; valaddr_reg:x2; val_offset:14754*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14754*FLEN/8, x3, x1, x4) + +inst_4953: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7c00; +op3val:0x8400; valaddr_reg:x2; val_offset:14757*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14757*FLEN/8, x3, x1, x4) + +inst_4954: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7c00; +op3val:0x401; valaddr_reg:x2; val_offset:14760*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14760*FLEN/8, x3, x1, x4) + +inst_4955: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7c00; +op3val:0x8455; valaddr_reg:x2; val_offset:14763*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14763*FLEN/8, x3, x1, x4) + +inst_4956: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7c00; +op3val:0x7bff; valaddr_reg:x2; val_offset:14766*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14766*FLEN/8, x3, x1, x4) + +inst_4957: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7c00; +op3val:0xfbff; valaddr_reg:x2; val_offset:14769*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14769*FLEN/8, x3, x1, x4) + +inst_4958: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7c00; +op3val:0x7c00; valaddr_reg:x2; val_offset:14772*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14772*FLEN/8, x3, x1, x4) + +inst_4959: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7c00; +op3val:0xfc00; valaddr_reg:x2; val_offset:14775*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14775*FLEN/8, x3, x1, x4) + +inst_4960: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7c00; +op3val:0x7e00; valaddr_reg:x2; val_offset:14778*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14778*FLEN/8, x3, x1, x4) + +inst_4961: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7c00; +op3val:0xfe00; valaddr_reg:x2; val_offset:14781*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14781*FLEN/8, x3, x1, x4) + +inst_4962: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7c00; +op3val:0x7e01; valaddr_reg:x2; val_offset:14784*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14784*FLEN/8, x3, x1, x4) + +inst_4963: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7c00; +op3val:0xfe55; valaddr_reg:x2; val_offset:14787*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14787*FLEN/8, x3, x1, x4) + +inst_4964: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7c00; +op3val:0x7c01; valaddr_reg:x2; val_offset:14790*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14790*FLEN/8, x3, x1, x4) + +inst_4965: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7c00; +op3val:0xfd55; valaddr_reg:x2; val_offset:14793*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14793*FLEN/8, x3, x1, x4) + +inst_4966: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7c00; +op3val:0x3c00; valaddr_reg:x2; val_offset:14796*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14796*FLEN/8, x3, x1, x4) + +inst_4967: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7c00; +op3val:0xbc00; valaddr_reg:x2; val_offset:14799*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14799*FLEN/8, x3, x1, x4) + +inst_4968: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfc00; +op3val:0x0; valaddr_reg:x2; val_offset:14802*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14802*FLEN/8, x3, x1, x4) + +inst_4969: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfc00; +op3val:0x8000; valaddr_reg:x2; val_offset:14805*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14805*FLEN/8, x3, x1, x4) + +inst_4970: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfc00; +op3val:0x1; valaddr_reg:x2; val_offset:14808*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14808*FLEN/8, x3, x1, x4) + +inst_4971: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfc00; +op3val:0x8001; valaddr_reg:x2; val_offset:14811*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14811*FLEN/8, x3, x1, x4) + +inst_4972: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfc00; +op3val:0x2; valaddr_reg:x2; val_offset:14814*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14814*FLEN/8, x3, x1, x4) + +inst_4973: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfc00; +op3val:0x83fe; valaddr_reg:x2; val_offset:14817*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14817*FLEN/8, x3, x1, x4) + +inst_4974: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfc00; +op3val:0x3ff; valaddr_reg:x2; val_offset:14820*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14820*FLEN/8, x3, x1, x4) + +inst_4975: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfc00; +op3val:0x83ff; valaddr_reg:x2; val_offset:14823*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14823*FLEN/8, x3, x1, x4) + +inst_4976: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfc00; +op3val:0x400; valaddr_reg:x2; val_offset:14826*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14826*FLEN/8, x3, x1, x4) + +inst_4977: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfc00; +op3val:0x8400; valaddr_reg:x2; val_offset:14829*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14829*FLEN/8, x3, x1, x4) + +inst_4978: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfc00; +op3val:0x401; valaddr_reg:x2; val_offset:14832*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14832*FLEN/8, x3, x1, x4) + +inst_4979: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfc00; +op3val:0x8455; valaddr_reg:x2; val_offset:14835*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14835*FLEN/8, x3, x1, x4) + +inst_4980: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfc00; +op3val:0x7bff; valaddr_reg:x2; val_offset:14838*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14838*FLEN/8, x3, x1, x4) + +inst_4981: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfc00; +op3val:0xfbff; valaddr_reg:x2; val_offset:14841*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14841*FLEN/8, x3, x1, x4) + +inst_4982: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfc00; +op3val:0x7c00; valaddr_reg:x2; val_offset:14844*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14844*FLEN/8, x3, x1, x4) + +inst_4983: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfc00; +op3val:0xfc00; valaddr_reg:x2; val_offset:14847*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14847*FLEN/8, x3, x1, x4) + +inst_4984: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfc00; +op3val:0x7e00; valaddr_reg:x2; val_offset:14850*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14850*FLEN/8, x3, x1, x4) + +inst_4985: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfc00; +op3val:0xfe00; valaddr_reg:x2; val_offset:14853*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14853*FLEN/8, x3, x1, x4) + +inst_4986: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfc00; +op3val:0x7e01; valaddr_reg:x2; val_offset:14856*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14856*FLEN/8, x3, x1, x4) + +inst_4987: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfc00; +op3val:0xfe55; valaddr_reg:x2; val_offset:14859*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14859*FLEN/8, x3, x1, x4) + +inst_4988: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfc00; +op3val:0x7c01; valaddr_reg:x2; val_offset:14862*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14862*FLEN/8, x3, x1, x4) + +inst_4989: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfc00; +op3val:0xfd55; valaddr_reg:x2; val_offset:14865*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14865*FLEN/8, x3, x1, x4) + +inst_4990: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfc00; +op3val:0x3c00; valaddr_reg:x2; val_offset:14868*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14868*FLEN/8, x3, x1, x4) + +inst_4991: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfc00; +op3val:0xbc00; valaddr_reg:x2; val_offset:14871*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14871*FLEN/8, x3, x1, x4) + +inst_4992: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7e00; +op3val:0x0; valaddr_reg:x2; val_offset:14874*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14874*FLEN/8, x3, x1, x4) + +inst_4993: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7e00; +op3val:0x8000; valaddr_reg:x2; val_offset:14877*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14877*FLEN/8, x3, x1, x4) + +inst_4994: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7e00; +op3val:0x1; valaddr_reg:x2; val_offset:14880*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14880*FLEN/8, x3, x1, x4) + +inst_4995: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7e00; +op3val:0x8001; valaddr_reg:x2; val_offset:14883*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14883*FLEN/8, x3, x1, x4) + +inst_4996: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7e00; +op3val:0x2; valaddr_reg:x2; val_offset:14886*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14886*FLEN/8, x3, x1, x4) + +inst_4997: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7e00; +op3val:0x83fe; valaddr_reg:x2; val_offset:14889*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14889*FLEN/8, x3, x1, x4) + +inst_4998: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7e00; +op3val:0x3ff; valaddr_reg:x2; val_offset:14892*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14892*FLEN/8, x3, x1, x4) + +inst_4999: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7e00; +op3val:0x83ff; valaddr_reg:x2; val_offset:14895*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14895*FLEN/8, x3, x1, x4) + +inst_5000: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7e00; +op3val:0x400; valaddr_reg:x2; val_offset:14898*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14898*FLEN/8, x3, x1, x4) + +inst_5001: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7e00; +op3val:0x8400; valaddr_reg:x2; val_offset:14901*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14901*FLEN/8, x3, x1, x4) + +inst_5002: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7e00; +op3val:0x401; valaddr_reg:x2; val_offset:14904*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14904*FLEN/8, x3, x1, x4) + +inst_5003: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7e00; +op3val:0x8455; valaddr_reg:x2; val_offset:14907*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14907*FLEN/8, x3, x1, x4) + +inst_5004: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7e00; +op3val:0x7bff; valaddr_reg:x2; val_offset:14910*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14910*FLEN/8, x3, x1, x4) + +inst_5005: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7e00; +op3val:0xfbff; valaddr_reg:x2; val_offset:14913*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14913*FLEN/8, x3, x1, x4) + +inst_5006: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7e00; +op3val:0x7c00; valaddr_reg:x2; val_offset:14916*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14916*FLEN/8, x3, x1, x4) + +inst_5007: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7e00; +op3val:0xfc00; valaddr_reg:x2; val_offset:14919*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14919*FLEN/8, x3, x1, x4) + +inst_5008: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7e00; +op3val:0x7e00; valaddr_reg:x2; val_offset:14922*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14922*FLEN/8, x3, x1, x4) + +inst_5009: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7e00; +op3val:0xfe00; valaddr_reg:x2; val_offset:14925*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14925*FLEN/8, x3, x1, x4) + +inst_5010: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7e00; +op3val:0x7e01; valaddr_reg:x2; val_offset:14928*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14928*FLEN/8, x3, x1, x4) + +inst_5011: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7e00; +op3val:0xfe55; valaddr_reg:x2; val_offset:14931*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14931*FLEN/8, x3, x1, x4) + +inst_5012: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7e00; +op3val:0x7c01; valaddr_reg:x2; val_offset:14934*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14934*FLEN/8, x3, x1, x4) + +inst_5013: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7e00; +op3val:0xfd55; valaddr_reg:x2; val_offset:14937*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14937*FLEN/8, x3, x1, x4) + +inst_5014: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7e00; +op3val:0x3c00; valaddr_reg:x2; val_offset:14940*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14940*FLEN/8, x3, x1, x4) + +inst_5015: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7e00; +op3val:0xbc00; valaddr_reg:x2; val_offset:14943*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14943*FLEN/8, x3, x1, x4) + +inst_5016: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfe00; +op3val:0x0; valaddr_reg:x2; val_offset:14946*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14946*FLEN/8, x3, x1, x4) + +inst_5017: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfe00; +op3val:0x8000; valaddr_reg:x2; val_offset:14949*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14949*FLEN/8, x3, x1, x4) + +inst_5018: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfe00; +op3val:0x1; valaddr_reg:x2; val_offset:14952*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14952*FLEN/8, x3, x1, x4) + +inst_5019: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfe00; +op3val:0x8001; valaddr_reg:x2; val_offset:14955*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14955*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_40) + +inst_5020: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfe00; +op3val:0x2; valaddr_reg:x2; val_offset:14958*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14958*FLEN/8, x3, x1, x4) + +inst_5021: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfe00; +op3val:0x83fe; valaddr_reg:x2; val_offset:14961*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14961*FLEN/8, x3, x1, x4) + +inst_5022: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfe00; +op3val:0x3ff; valaddr_reg:x2; val_offset:14964*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14964*FLEN/8, x3, x1, x4) + +inst_5023: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfe00; +op3val:0x83ff; valaddr_reg:x2; val_offset:14967*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14967*FLEN/8, x3, x1, x4) + +inst_5024: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfe00; +op3val:0x400; valaddr_reg:x2; val_offset:14970*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14970*FLEN/8, x3, x1, x4) + +inst_5025: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfe00; +op3val:0x8400; valaddr_reg:x2; val_offset:14973*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14973*FLEN/8, x3, x1, x4) + +inst_5026: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfe00; +op3val:0x401; valaddr_reg:x2; val_offset:14976*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14976*FLEN/8, x3, x1, x4) + +inst_5027: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfe00; +op3val:0x8455; valaddr_reg:x2; val_offset:14979*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14979*FLEN/8, x3, x1, x4) + +inst_5028: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfe00; +op3val:0x7bff; valaddr_reg:x2; val_offset:14982*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14982*FLEN/8, x3, x1, x4) + +inst_5029: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfe00; +op3val:0xfbff; valaddr_reg:x2; val_offset:14985*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14985*FLEN/8, x3, x1, x4) + +inst_5030: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfe00; +op3val:0x7c00; valaddr_reg:x2; val_offset:14988*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14988*FLEN/8, x3, x1, x4) + +inst_5031: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfe00; +op3val:0xfc00; valaddr_reg:x2; val_offset:14991*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14991*FLEN/8, x3, x1, x4) + +inst_5032: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfe00; +op3val:0x7e00; valaddr_reg:x2; val_offset:14994*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14994*FLEN/8, x3, x1, x4) + +inst_5033: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfe00; +op3val:0xfe00; valaddr_reg:x2; val_offset:14997*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 14997*FLEN/8, x3, x1, x4) + +inst_5034: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfe00; +op3val:0x7e01; valaddr_reg:x2; val_offset:15000*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15000*FLEN/8, x3, x1, x4) + +inst_5035: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfe00; +op3val:0xfe55; valaddr_reg:x2; val_offset:15003*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15003*FLEN/8, x3, x1, x4) + +inst_5036: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfe00; +op3val:0x7c01; valaddr_reg:x2; val_offset:15006*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15006*FLEN/8, x3, x1, x4) + +inst_5037: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfe00; +op3val:0xfd55; valaddr_reg:x2; val_offset:15009*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15009*FLEN/8, x3, x1, x4) + +inst_5038: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfe00; +op3val:0x3c00; valaddr_reg:x2; val_offset:15012*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15012*FLEN/8, x3, x1, x4) + +inst_5039: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfe00; +op3val:0xbc00; valaddr_reg:x2; val_offset:15015*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15015*FLEN/8, x3, x1, x4) + +inst_5040: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7e01; +op3val:0x0; valaddr_reg:x2; val_offset:15018*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15018*FLEN/8, x3, x1, x4) + +inst_5041: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7e01; +op3val:0x8000; valaddr_reg:x2; val_offset:15021*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15021*FLEN/8, x3, x1, x4) + +inst_5042: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7e01; +op3val:0x1; valaddr_reg:x2; val_offset:15024*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15024*FLEN/8, x3, x1, x4) + +inst_5043: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7e01; +op3val:0x8001; valaddr_reg:x2; val_offset:15027*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15027*FLEN/8, x3, x1, x4) + +inst_5044: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7e01; +op3val:0x2; valaddr_reg:x2; val_offset:15030*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15030*FLEN/8, x3, x1, x4) + +inst_5045: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7e01; +op3val:0x83fe; valaddr_reg:x2; val_offset:15033*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15033*FLEN/8, x3, x1, x4) + +inst_5046: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7e01; +op3val:0x3ff; valaddr_reg:x2; val_offset:15036*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15036*FLEN/8, x3, x1, x4) + +inst_5047: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7e01; +op3val:0x83ff; valaddr_reg:x2; val_offset:15039*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15039*FLEN/8, x3, x1, x4) + +inst_5048: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7e01; +op3val:0x400; valaddr_reg:x2; val_offset:15042*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15042*FLEN/8, x3, x1, x4) + +inst_5049: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7e01; +op3val:0x8400; valaddr_reg:x2; val_offset:15045*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15045*FLEN/8, x3, x1, x4) + +inst_5050: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7e01; +op3val:0x401; valaddr_reg:x2; val_offset:15048*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15048*FLEN/8, x3, x1, x4) + +inst_5051: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7e01; +op3val:0x8455; valaddr_reg:x2; val_offset:15051*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15051*FLEN/8, x3, x1, x4) + +inst_5052: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7e01; +op3val:0x7bff; valaddr_reg:x2; val_offset:15054*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15054*FLEN/8, x3, x1, x4) + +inst_5053: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7e01; +op3val:0xfbff; valaddr_reg:x2; val_offset:15057*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15057*FLEN/8, x3, x1, x4) + +inst_5054: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7e01; +op3val:0x7c00; valaddr_reg:x2; val_offset:15060*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15060*FLEN/8, x3, x1, x4) + +inst_5055: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7e01; +op3val:0xfc00; valaddr_reg:x2; val_offset:15063*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15063*FLEN/8, x3, x1, x4) + +inst_5056: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7e01; +op3val:0x7e00; valaddr_reg:x2; val_offset:15066*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15066*FLEN/8, x3, x1, x4) + +inst_5057: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7e01; +op3val:0xfe00; valaddr_reg:x2; val_offset:15069*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15069*FLEN/8, x3, x1, x4) + +inst_5058: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7e01; +op3val:0x7e01; valaddr_reg:x2; val_offset:15072*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15072*FLEN/8, x3, x1, x4) + +inst_5059: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7e01; +op3val:0xfe55; valaddr_reg:x2; val_offset:15075*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15075*FLEN/8, x3, x1, x4) + +inst_5060: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7e01; +op3val:0x7c01; valaddr_reg:x2; val_offset:15078*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15078*FLEN/8, x3, x1, x4) + +inst_5061: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7e01; +op3val:0xfd55; valaddr_reg:x2; val_offset:15081*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15081*FLEN/8, x3, x1, x4) + +inst_5062: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7e01; +op3val:0x3c00; valaddr_reg:x2; val_offset:15084*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15084*FLEN/8, x3, x1, x4) + +inst_5063: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7e01; +op3val:0xbc00; valaddr_reg:x2; val_offset:15087*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15087*FLEN/8, x3, x1, x4) + +inst_5064: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfe55; +op3val:0x0; valaddr_reg:x2; val_offset:15090*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15090*FLEN/8, x3, x1, x4) + +inst_5065: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfe55; +op3val:0x8000; valaddr_reg:x2; val_offset:15093*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15093*FLEN/8, x3, x1, x4) + +inst_5066: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfe55; +op3val:0x1; valaddr_reg:x2; val_offset:15096*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15096*FLEN/8, x3, x1, x4) + +inst_5067: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfe55; +op3val:0x8001; valaddr_reg:x2; val_offset:15099*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15099*FLEN/8, x3, x1, x4) + +inst_5068: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfe55; +op3val:0x2; valaddr_reg:x2; val_offset:15102*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15102*FLEN/8, x3, x1, x4) + +inst_5069: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfe55; +op3val:0x83fe; valaddr_reg:x2; val_offset:15105*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15105*FLEN/8, x3, x1, x4) + +inst_5070: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfe55; +op3val:0x3ff; valaddr_reg:x2; val_offset:15108*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15108*FLEN/8, x3, x1, x4) + +inst_5071: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfe55; +op3val:0x83ff; valaddr_reg:x2; val_offset:15111*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15111*FLEN/8, x3, x1, x4) + +inst_5072: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfe55; +op3val:0x400; valaddr_reg:x2; val_offset:15114*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15114*FLEN/8, x3, x1, x4) + +inst_5073: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfe55; +op3val:0x8400; valaddr_reg:x2; val_offset:15117*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15117*FLEN/8, x3, x1, x4) + +inst_5074: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfe55; +op3val:0x401; valaddr_reg:x2; val_offset:15120*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15120*FLEN/8, x3, x1, x4) + +inst_5075: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfe55; +op3val:0x8455; valaddr_reg:x2; val_offset:15123*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15123*FLEN/8, x3, x1, x4) + +inst_5076: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfe55; +op3val:0x7bff; valaddr_reg:x2; val_offset:15126*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15126*FLEN/8, x3, x1, x4) + +inst_5077: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfe55; +op3val:0xfbff; valaddr_reg:x2; val_offset:15129*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15129*FLEN/8, x3, x1, x4) + +inst_5078: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfe55; +op3val:0x7c00; valaddr_reg:x2; val_offset:15132*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15132*FLEN/8, x3, x1, x4) + +inst_5079: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfe55; +op3val:0xfc00; valaddr_reg:x2; val_offset:15135*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15135*FLEN/8, x3, x1, x4) + +inst_5080: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfe55; +op3val:0x7e00; valaddr_reg:x2; val_offset:15138*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15138*FLEN/8, x3, x1, x4) + +inst_5081: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfe55; +op3val:0xfe00; valaddr_reg:x2; val_offset:15141*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15141*FLEN/8, x3, x1, x4) + +inst_5082: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfe55; +op3val:0x7e01; valaddr_reg:x2; val_offset:15144*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15144*FLEN/8, x3, x1, x4) + +inst_5083: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfe55; +op3val:0xfe55; valaddr_reg:x2; val_offset:15147*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15147*FLEN/8, x3, x1, x4) + +inst_5084: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfe55; +op3val:0x7c01; valaddr_reg:x2; val_offset:15150*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15150*FLEN/8, x3, x1, x4) + +inst_5085: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfe55; +op3val:0xfd55; valaddr_reg:x2; val_offset:15153*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15153*FLEN/8, x3, x1, x4) + +inst_5086: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfe55; +op3val:0x3c00; valaddr_reg:x2; val_offset:15156*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15156*FLEN/8, x3, x1, x4) + +inst_5087: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfe55; +op3val:0xbc00; valaddr_reg:x2; val_offset:15159*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15159*FLEN/8, x3, x1, x4) + +inst_5088: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7c01; +op3val:0x0; valaddr_reg:x2; val_offset:15162*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15162*FLEN/8, x3, x1, x4) + +inst_5089: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7c01; +op3val:0x8000; valaddr_reg:x2; val_offset:15165*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15165*FLEN/8, x3, x1, x4) + +inst_5090: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7c01; +op3val:0x1; valaddr_reg:x2; val_offset:15168*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15168*FLEN/8, x3, x1, x4) + +inst_5091: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7c01; +op3val:0x8001; valaddr_reg:x2; val_offset:15171*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15171*FLEN/8, x3, x1, x4) + +inst_5092: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7c01; +op3val:0x2; valaddr_reg:x2; val_offset:15174*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15174*FLEN/8, x3, x1, x4) + +inst_5093: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7c01; +op3val:0x83fe; valaddr_reg:x2; val_offset:15177*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15177*FLEN/8, x3, x1, x4) + +inst_5094: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7c01; +op3val:0x3ff; valaddr_reg:x2; val_offset:15180*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15180*FLEN/8, x3, x1, x4) + +inst_5095: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7c01; +op3val:0x83ff; valaddr_reg:x2; val_offset:15183*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15183*FLEN/8, x3, x1, x4) + +inst_5096: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7c01; +op3val:0x400; valaddr_reg:x2; val_offset:15186*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15186*FLEN/8, x3, x1, x4) + +inst_5097: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7c01; +op3val:0x8400; valaddr_reg:x2; val_offset:15189*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15189*FLEN/8, x3, x1, x4) + +inst_5098: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7c01; +op3val:0x401; valaddr_reg:x2; val_offset:15192*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15192*FLEN/8, x3, x1, x4) + +inst_5099: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7c01; +op3val:0x8455; valaddr_reg:x2; val_offset:15195*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15195*FLEN/8, x3, x1, x4) + +inst_5100: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7c01; +op3val:0x7bff; valaddr_reg:x2; val_offset:15198*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15198*FLEN/8, x3, x1, x4) + +inst_5101: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7c01; +op3val:0xfbff; valaddr_reg:x2; val_offset:15201*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15201*FLEN/8, x3, x1, x4) + +inst_5102: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7c01; +op3val:0x7c00; valaddr_reg:x2; val_offset:15204*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15204*FLEN/8, x3, x1, x4) + +inst_5103: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7c01; +op3val:0xfc00; valaddr_reg:x2; val_offset:15207*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15207*FLEN/8, x3, x1, x4) + +inst_5104: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7c01; +op3val:0x7e00; valaddr_reg:x2; val_offset:15210*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15210*FLEN/8, x3, x1, x4) + +inst_5105: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7c01; +op3val:0xfe00; valaddr_reg:x2; val_offset:15213*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15213*FLEN/8, x3, x1, x4) + +inst_5106: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7c01; +op3val:0x7e01; valaddr_reg:x2; val_offset:15216*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15216*FLEN/8, x3, x1, x4) + +inst_5107: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7c01; +op3val:0xfe55; valaddr_reg:x2; val_offset:15219*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15219*FLEN/8, x3, x1, x4) + +inst_5108: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7c01; +op3val:0x7c01; valaddr_reg:x2; val_offset:15222*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15222*FLEN/8, x3, x1, x4) + +inst_5109: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7c01; +op3val:0xfd55; valaddr_reg:x2; val_offset:15225*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15225*FLEN/8, x3, x1, x4) + +inst_5110: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7c01; +op3val:0x3c00; valaddr_reg:x2; val_offset:15228*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15228*FLEN/8, x3, x1, x4) + +inst_5111: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x7c01; +op3val:0xbc00; valaddr_reg:x2; val_offset:15231*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15231*FLEN/8, x3, x1, x4) + +inst_5112: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfd55; +op3val:0x0; valaddr_reg:x2; val_offset:15234*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15234*FLEN/8, x3, x1, x4) + +inst_5113: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfd55; +op3val:0x8000; valaddr_reg:x2; val_offset:15237*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15237*FLEN/8, x3, x1, x4) + +inst_5114: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfd55; +op3val:0x1; valaddr_reg:x2; val_offset:15240*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15240*FLEN/8, x3, x1, x4) + +inst_5115: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfd55; +op3val:0x8001; valaddr_reg:x2; val_offset:15243*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15243*FLEN/8, x3, x1, x4) + +inst_5116: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfd55; +op3val:0x2; valaddr_reg:x2; val_offset:15246*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15246*FLEN/8, x3, x1, x4) + +inst_5117: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfd55; +op3val:0x83fe; valaddr_reg:x2; val_offset:15249*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15249*FLEN/8, x3, x1, x4) + +inst_5118: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfd55; +op3val:0x3ff; valaddr_reg:x2; val_offset:15252*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15252*FLEN/8, x3, x1, x4) + +inst_5119: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfd55; +op3val:0x83ff; valaddr_reg:x2; val_offset:15255*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15255*FLEN/8, x3, x1, x4) + +inst_5120: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfd55; +op3val:0x400; valaddr_reg:x2; val_offset:15258*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15258*FLEN/8, x3, x1, x4) + +inst_5121: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfd55; +op3val:0x8400; valaddr_reg:x2; val_offset:15261*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15261*FLEN/8, x3, x1, x4) + +inst_5122: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfd55; +op3val:0x401; valaddr_reg:x2; val_offset:15264*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15264*FLEN/8, x3, x1, x4) + +inst_5123: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfd55; +op3val:0x8455; valaddr_reg:x2; val_offset:15267*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15267*FLEN/8, x3, x1, x4) + +inst_5124: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfd55; +op3val:0x7bff; valaddr_reg:x2; val_offset:15270*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15270*FLEN/8, x3, x1, x4) + +inst_5125: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfd55; +op3val:0xfbff; valaddr_reg:x2; val_offset:15273*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15273*FLEN/8, x3, x1, x4) + +inst_5126: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfd55; +op3val:0x7c00; valaddr_reg:x2; val_offset:15276*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15276*FLEN/8, x3, x1, x4) + +inst_5127: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfd55; +op3val:0xfc00; valaddr_reg:x2; val_offset:15279*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15279*FLEN/8, x3, x1, x4) + +inst_5128: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfd55; +op3val:0x7e00; valaddr_reg:x2; val_offset:15282*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15282*FLEN/8, x3, x1, x4) + +inst_5129: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfd55; +op3val:0xfe00; valaddr_reg:x2; val_offset:15285*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15285*FLEN/8, x3, x1, x4) + +inst_5130: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfd55; +op3val:0x7e01; valaddr_reg:x2; val_offset:15288*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15288*FLEN/8, x3, x1, x4) + +inst_5131: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfd55; +op3val:0xfe55; valaddr_reg:x2; val_offset:15291*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15291*FLEN/8, x3, x1, x4) + +inst_5132: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfd55; +op3val:0x7c01; valaddr_reg:x2; val_offset:15294*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15294*FLEN/8, x3, x1, x4) + +inst_5133: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfd55; +op3val:0xfd55; valaddr_reg:x2; val_offset:15297*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15297*FLEN/8, x3, x1, x4) + +inst_5134: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfd55; +op3val:0x3c00; valaddr_reg:x2; val_offset:15300*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15300*FLEN/8, x3, x1, x4) + +inst_5135: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xfd55; +op3val:0xbc00; valaddr_reg:x2; val_offset:15303*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15303*FLEN/8, x3, x1, x4) + +inst_5136: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x3c00; +op3val:0x0; valaddr_reg:x2; val_offset:15306*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15306*FLEN/8, x3, x1, x4) + +inst_5137: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x3c00; +op3val:0x8000; valaddr_reg:x2; val_offset:15309*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15309*FLEN/8, x3, x1, x4) + +inst_5138: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x3c00; +op3val:0x1; valaddr_reg:x2; val_offset:15312*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15312*FLEN/8, x3, x1, x4) + +inst_5139: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x3c00; +op3val:0x8001; valaddr_reg:x2; val_offset:15315*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15315*FLEN/8, x3, x1, x4) + +inst_5140: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x3c00; +op3val:0x2; valaddr_reg:x2; val_offset:15318*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15318*FLEN/8, x3, x1, x4) + +inst_5141: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x3c00; +op3val:0x83fe; valaddr_reg:x2; val_offset:15321*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15321*FLEN/8, x3, x1, x4) + +inst_5142: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x3c00; +op3val:0x3ff; valaddr_reg:x2; val_offset:15324*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15324*FLEN/8, x3, x1, x4) + +inst_5143: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x3c00; +op3val:0x83ff; valaddr_reg:x2; val_offset:15327*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15327*FLEN/8, x3, x1, x4) + +inst_5144: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x3c00; +op3val:0x400; valaddr_reg:x2; val_offset:15330*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15330*FLEN/8, x3, x1, x4) + +inst_5145: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x3c00; +op3val:0x8400; valaddr_reg:x2; val_offset:15333*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15333*FLEN/8, x3, x1, x4) + +inst_5146: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x3c00; +op3val:0x401; valaddr_reg:x2; val_offset:15336*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15336*FLEN/8, x3, x1, x4) + +inst_5147: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x3c00; +op3val:0x8455; valaddr_reg:x2; val_offset:15339*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15339*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_41) + +inst_5148: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x3c00; +op3val:0x7bff; valaddr_reg:x2; val_offset:15342*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15342*FLEN/8, x3, x1, x4) + +inst_5149: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x3c00; +op3val:0xfbff; valaddr_reg:x2; val_offset:15345*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15345*FLEN/8, x3, x1, x4) + +inst_5150: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x3c00; +op3val:0x7c00; valaddr_reg:x2; val_offset:15348*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15348*FLEN/8, x3, x1, x4) + +inst_5151: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x3c00; +op3val:0xfc00; valaddr_reg:x2; val_offset:15351*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15351*FLEN/8, x3, x1, x4) + +inst_5152: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x3c00; +op3val:0x7e00; valaddr_reg:x2; val_offset:15354*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15354*FLEN/8, x3, x1, x4) + +inst_5153: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x3c00; +op3val:0xfe00; valaddr_reg:x2; val_offset:15357*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15357*FLEN/8, x3, x1, x4) + +inst_5154: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x3c00; +op3val:0x7e01; valaddr_reg:x2; val_offset:15360*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15360*FLEN/8, x3, x1, x4) + +inst_5155: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x3c00; +op3val:0xfe55; valaddr_reg:x2; val_offset:15363*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15363*FLEN/8, x3, x1, x4) + +inst_5156: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x3c00; +op3val:0x7c01; valaddr_reg:x2; val_offset:15366*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15366*FLEN/8, x3, x1, x4) + +inst_5157: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x3c00; +op3val:0xfd55; valaddr_reg:x2; val_offset:15369*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15369*FLEN/8, x3, x1, x4) + +inst_5158: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x3c00; +op3val:0x3c00; valaddr_reg:x2; val_offset:15372*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15372*FLEN/8, x3, x1, x4) + +inst_5159: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0x3c00; +op3val:0xbc00; valaddr_reg:x2; val_offset:15375*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15375*FLEN/8, x3, x1, x4) + +inst_5160: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xbc00; +op3val:0x0; valaddr_reg:x2; val_offset:15378*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15378*FLEN/8, x3, x1, x4) + +inst_5161: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xbc00; +op3val:0x8000; valaddr_reg:x2; val_offset:15381*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15381*FLEN/8, x3, x1, x4) + +inst_5162: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xbc00; +op3val:0x1; valaddr_reg:x2; val_offset:15384*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15384*FLEN/8, x3, x1, x4) + +inst_5163: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xbc00; +op3val:0x8001; valaddr_reg:x2; val_offset:15387*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15387*FLEN/8, x3, x1, x4) + +inst_5164: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xbc00; +op3val:0x2; valaddr_reg:x2; val_offset:15390*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15390*FLEN/8, x3, x1, x4) + +inst_5165: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xbc00; +op3val:0x83fe; valaddr_reg:x2; val_offset:15393*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15393*FLEN/8, x3, x1, x4) + +inst_5166: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xbc00; +op3val:0x3ff; valaddr_reg:x2; val_offset:15396*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15396*FLEN/8, x3, x1, x4) + +inst_5167: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xbc00; +op3val:0x83ff; valaddr_reg:x2; val_offset:15399*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15399*FLEN/8, x3, x1, x4) + +inst_5168: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xbc00; +op3val:0x400; valaddr_reg:x2; val_offset:15402*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15402*FLEN/8, x3, x1, x4) + +inst_5169: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xbc00; +op3val:0x8400; valaddr_reg:x2; val_offset:15405*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15405*FLEN/8, x3, x1, x4) + +inst_5170: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xbc00; +op3val:0x401; valaddr_reg:x2; val_offset:15408*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15408*FLEN/8, x3, x1, x4) + +inst_5171: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xbc00; +op3val:0x8455; valaddr_reg:x2; val_offset:15411*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15411*FLEN/8, x3, x1, x4) + +inst_5172: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xbc00; +op3val:0x7bff; valaddr_reg:x2; val_offset:15414*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15414*FLEN/8, x3, x1, x4) + +inst_5173: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xbc00; +op3val:0xfbff; valaddr_reg:x2; val_offset:15417*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15417*FLEN/8, x3, x1, x4) + +inst_5174: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xbc00; +op3val:0x7c00; valaddr_reg:x2; val_offset:15420*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15420*FLEN/8, x3, x1, x4) + +inst_5175: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xbc00; +op3val:0xfc00; valaddr_reg:x2; val_offset:15423*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15423*FLEN/8, x3, x1, x4) + +inst_5176: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xbc00; +op3val:0x7e00; valaddr_reg:x2; val_offset:15426*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15426*FLEN/8, x3, x1, x4) + +inst_5177: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xbc00; +op3val:0xfe00; valaddr_reg:x2; val_offset:15429*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15429*FLEN/8, x3, x1, x4) + +inst_5178: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xbc00; +op3val:0x7e01; valaddr_reg:x2; val_offset:15432*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15432*FLEN/8, x3, x1, x4) + +inst_5179: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xbc00; +op3val:0xfe55; valaddr_reg:x2; val_offset:15435*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15435*FLEN/8, x3, x1, x4) + +inst_5180: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xbc00; +op3val:0x7c01; valaddr_reg:x2; val_offset:15438*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15438*FLEN/8, x3, x1, x4) + +inst_5181: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xbc00; +op3val:0xfd55; valaddr_reg:x2; val_offset:15441*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15441*FLEN/8, x3, x1, x4) + +inst_5182: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xbc00; +op3val:0x3c00; valaddr_reg:x2; val_offset:15444*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15444*FLEN/8, x3, x1, x4) + +inst_5183: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x400; op2val:0xbc00; +op3val:0xbc00; valaddr_reg:x2; val_offset:15447*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15447*FLEN/8, x3, x1, x4) + +inst_5184: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x0; +op3val:0x0; valaddr_reg:x2; val_offset:15450*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15450*FLEN/8, x3, x1, x4) + +inst_5185: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x0; +op3val:0x8000; valaddr_reg:x2; val_offset:15453*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15453*FLEN/8, x3, x1, x4) + +inst_5186: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x0; +op3val:0x1; valaddr_reg:x2; val_offset:15456*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15456*FLEN/8, x3, x1, x4) + +inst_5187: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x0; +op3val:0x8001; valaddr_reg:x2; val_offset:15459*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15459*FLEN/8, x3, x1, x4) + +inst_5188: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x0; +op3val:0x2; valaddr_reg:x2; val_offset:15462*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15462*FLEN/8, x3, x1, x4) + +inst_5189: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x0; +op3val:0x83fe; valaddr_reg:x2; val_offset:15465*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15465*FLEN/8, x3, x1, x4) + +inst_5190: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x0; +op3val:0x3ff; valaddr_reg:x2; val_offset:15468*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15468*FLEN/8, x3, x1, x4) + +inst_5191: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x0; +op3val:0x83ff; valaddr_reg:x2; val_offset:15471*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15471*FLEN/8, x3, x1, x4) + +inst_5192: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x0; +op3val:0x400; valaddr_reg:x2; val_offset:15474*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15474*FLEN/8, x3, x1, x4) + +inst_5193: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x0; +op3val:0x8400; valaddr_reg:x2; val_offset:15477*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15477*FLEN/8, x3, x1, x4) + +inst_5194: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x0; +op3val:0x401; valaddr_reg:x2; val_offset:15480*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15480*FLEN/8, x3, x1, x4) + +inst_5195: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x0; +op3val:0x8455; valaddr_reg:x2; val_offset:15483*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15483*FLEN/8, x3, x1, x4) + +inst_5196: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x0; +op3val:0x7bff; valaddr_reg:x2; val_offset:15486*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15486*FLEN/8, x3, x1, x4) + +inst_5197: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x0; +op3val:0xfbff; valaddr_reg:x2; val_offset:15489*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15489*FLEN/8, x3, x1, x4) + +inst_5198: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x0; +op3val:0x7c00; valaddr_reg:x2; val_offset:15492*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15492*FLEN/8, x3, x1, x4) + +inst_5199: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x0; +op3val:0xfc00; valaddr_reg:x2; val_offset:15495*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15495*FLEN/8, x3, x1, x4) + +inst_5200: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x0; +op3val:0x7e00; valaddr_reg:x2; val_offset:15498*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15498*FLEN/8, x3, x1, x4) + +inst_5201: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x0; +op3val:0xfe00; valaddr_reg:x2; val_offset:15501*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15501*FLEN/8, x3, x1, x4) + +inst_5202: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x0; +op3val:0x7e01; valaddr_reg:x2; val_offset:15504*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15504*FLEN/8, x3, x1, x4) + +inst_5203: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x0; +op3val:0xfe55; valaddr_reg:x2; val_offset:15507*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15507*FLEN/8, x3, x1, x4) + +inst_5204: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x0; +op3val:0x7c01; valaddr_reg:x2; val_offset:15510*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15510*FLEN/8, x3, x1, x4) + +inst_5205: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x0; +op3val:0xfd55; valaddr_reg:x2; val_offset:15513*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15513*FLEN/8, x3, x1, x4) + +inst_5206: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x0; +op3val:0x3c00; valaddr_reg:x2; val_offset:15516*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15516*FLEN/8, x3, x1, x4) + +inst_5207: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x0; +op3val:0xbc00; valaddr_reg:x2; val_offset:15519*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15519*FLEN/8, x3, x1, x4) + +inst_5208: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8000; +op3val:0x0; valaddr_reg:x2; val_offset:15522*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15522*FLEN/8, x3, x1, x4) + +inst_5209: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8000; +op3val:0x8000; valaddr_reg:x2; val_offset:15525*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15525*FLEN/8, x3, x1, x4) + +inst_5210: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8000; +op3val:0x1; valaddr_reg:x2; val_offset:15528*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15528*FLEN/8, x3, x1, x4) + +inst_5211: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8000; +op3val:0x8001; valaddr_reg:x2; val_offset:15531*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15531*FLEN/8, x3, x1, x4) + +inst_5212: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8000; +op3val:0x2; valaddr_reg:x2; val_offset:15534*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15534*FLEN/8, x3, x1, x4) + +inst_5213: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8000; +op3val:0x83fe; valaddr_reg:x2; val_offset:15537*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15537*FLEN/8, x3, x1, x4) + +inst_5214: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8000; +op3val:0x3ff; valaddr_reg:x2; val_offset:15540*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15540*FLEN/8, x3, x1, x4) + +inst_5215: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8000; +op3val:0x83ff; valaddr_reg:x2; val_offset:15543*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15543*FLEN/8, x3, x1, x4) + +inst_5216: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8000; +op3val:0x400; valaddr_reg:x2; val_offset:15546*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15546*FLEN/8, x3, x1, x4) + +inst_5217: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8000; +op3val:0x8400; valaddr_reg:x2; val_offset:15549*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15549*FLEN/8, x3, x1, x4) + +inst_5218: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8000; +op3val:0x401; valaddr_reg:x2; val_offset:15552*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15552*FLEN/8, x3, x1, x4) + +inst_5219: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8000; +op3val:0x8455; valaddr_reg:x2; val_offset:15555*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15555*FLEN/8, x3, x1, x4) + +inst_5220: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x2; val_offset:15558*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15558*FLEN/8, x3, x1, x4) + +inst_5221: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x2; val_offset:15561*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15561*FLEN/8, x3, x1, x4) + +inst_5222: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8000; +op3val:0x7c00; valaddr_reg:x2; val_offset:15564*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15564*FLEN/8, x3, x1, x4) + +inst_5223: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8000; +op3val:0xfc00; valaddr_reg:x2; val_offset:15567*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15567*FLEN/8, x3, x1, x4) + +inst_5224: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8000; +op3val:0x7e00; valaddr_reg:x2; val_offset:15570*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15570*FLEN/8, x3, x1, x4) + +inst_5225: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8000; +op3val:0xfe00; valaddr_reg:x2; val_offset:15573*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15573*FLEN/8, x3, x1, x4) + +inst_5226: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8000; +op3val:0x7e01; valaddr_reg:x2; val_offset:15576*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15576*FLEN/8, x3, x1, x4) + +inst_5227: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8000; +op3val:0xfe55; valaddr_reg:x2; val_offset:15579*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15579*FLEN/8, x3, x1, x4) + +inst_5228: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8000; +op3val:0x7c01; valaddr_reg:x2; val_offset:15582*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15582*FLEN/8, x3, x1, x4) + +inst_5229: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8000; +op3val:0xfd55; valaddr_reg:x2; val_offset:15585*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15585*FLEN/8, x3, x1, x4) + +inst_5230: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8000; +op3val:0x3c00; valaddr_reg:x2; val_offset:15588*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15588*FLEN/8, x3, x1, x4) + +inst_5231: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8000; +op3val:0xbc00; valaddr_reg:x2; val_offset:15591*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15591*FLEN/8, x3, x1, x4) + +inst_5232: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x1; +op3val:0x0; valaddr_reg:x2; val_offset:15594*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15594*FLEN/8, x3, x1, x4) + +inst_5233: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x1; +op3val:0x8000; valaddr_reg:x2; val_offset:15597*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15597*FLEN/8, x3, x1, x4) + +inst_5234: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x1; +op3val:0x1; valaddr_reg:x2; val_offset:15600*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15600*FLEN/8, x3, x1, x4) + +inst_5235: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x1; +op3val:0x8001; valaddr_reg:x2; val_offset:15603*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15603*FLEN/8, x3, x1, x4) + +inst_5236: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x1; +op3val:0x2; valaddr_reg:x2; val_offset:15606*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15606*FLEN/8, x3, x1, x4) + +inst_5237: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x1; +op3val:0x83fe; valaddr_reg:x2; val_offset:15609*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15609*FLEN/8, x3, x1, x4) + +inst_5238: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x1; +op3val:0x3ff; valaddr_reg:x2; val_offset:15612*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15612*FLEN/8, x3, x1, x4) + +inst_5239: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x1; +op3val:0x83ff; valaddr_reg:x2; val_offset:15615*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15615*FLEN/8, x3, x1, x4) + +inst_5240: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x1; +op3val:0x400; valaddr_reg:x2; val_offset:15618*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15618*FLEN/8, x3, x1, x4) + +inst_5241: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x1; +op3val:0x8400; valaddr_reg:x2; val_offset:15621*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15621*FLEN/8, x3, x1, x4) + +inst_5242: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x1; +op3val:0x401; valaddr_reg:x2; val_offset:15624*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15624*FLEN/8, x3, x1, x4) + +inst_5243: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x1; +op3val:0x8455; valaddr_reg:x2; val_offset:15627*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15627*FLEN/8, x3, x1, x4) + +inst_5244: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x1; +op3val:0x7bff; valaddr_reg:x2; val_offset:15630*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15630*FLEN/8, x3, x1, x4) + +inst_5245: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x1; +op3val:0xfbff; valaddr_reg:x2; val_offset:15633*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15633*FLEN/8, x3, x1, x4) + +inst_5246: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x1; +op3val:0x7c00; valaddr_reg:x2; val_offset:15636*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15636*FLEN/8, x3, x1, x4) + +inst_5247: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x1; +op3val:0xfc00; valaddr_reg:x2; val_offset:15639*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15639*FLEN/8, x3, x1, x4) + +inst_5248: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x1; +op3val:0x7e00; valaddr_reg:x2; val_offset:15642*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15642*FLEN/8, x3, x1, x4) + +inst_5249: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x1; +op3val:0xfe00; valaddr_reg:x2; val_offset:15645*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15645*FLEN/8, x3, x1, x4) + +inst_5250: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x1; +op3val:0x7e01; valaddr_reg:x2; val_offset:15648*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15648*FLEN/8, x3, x1, x4) + +inst_5251: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x1; +op3val:0xfe55; valaddr_reg:x2; val_offset:15651*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15651*FLEN/8, x3, x1, x4) + +inst_5252: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x1; +op3val:0x7c01; valaddr_reg:x2; val_offset:15654*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15654*FLEN/8, x3, x1, x4) + +inst_5253: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x1; +op3val:0xfd55; valaddr_reg:x2; val_offset:15657*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15657*FLEN/8, x3, x1, x4) + +inst_5254: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x1; +op3val:0x3c00; valaddr_reg:x2; val_offset:15660*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15660*FLEN/8, x3, x1, x4) + +inst_5255: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x1; +op3val:0xbc00; valaddr_reg:x2; val_offset:15663*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15663*FLEN/8, x3, x1, x4) + +inst_5256: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8001; +op3val:0x0; valaddr_reg:x2; val_offset:15666*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15666*FLEN/8, x3, x1, x4) + +inst_5257: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8001; +op3val:0x8000; valaddr_reg:x2; val_offset:15669*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15669*FLEN/8, x3, x1, x4) + +inst_5258: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8001; +op3val:0x1; valaddr_reg:x2; val_offset:15672*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15672*FLEN/8, x3, x1, x4) + +inst_5259: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8001; +op3val:0x8001; valaddr_reg:x2; val_offset:15675*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15675*FLEN/8, x3, x1, x4) + +inst_5260: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8001; +op3val:0x2; valaddr_reg:x2; val_offset:15678*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15678*FLEN/8, x3, x1, x4) + +inst_5261: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8001; +op3val:0x83fe; valaddr_reg:x2; val_offset:15681*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15681*FLEN/8, x3, x1, x4) + +inst_5262: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8001; +op3val:0x3ff; valaddr_reg:x2; val_offset:15684*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15684*FLEN/8, x3, x1, x4) + +inst_5263: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8001; +op3val:0x83ff; valaddr_reg:x2; val_offset:15687*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15687*FLEN/8, x3, x1, x4) + +inst_5264: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8001; +op3val:0x400; valaddr_reg:x2; val_offset:15690*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15690*FLEN/8, x3, x1, x4) + +inst_5265: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8001; +op3val:0x8400; valaddr_reg:x2; val_offset:15693*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15693*FLEN/8, x3, x1, x4) + +inst_5266: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8001; +op3val:0x401; valaddr_reg:x2; val_offset:15696*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15696*FLEN/8, x3, x1, x4) + +inst_5267: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8001; +op3val:0x8455; valaddr_reg:x2; val_offset:15699*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15699*FLEN/8, x3, x1, x4) + +inst_5268: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8001; +op3val:0x7bff; valaddr_reg:x2; val_offset:15702*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15702*FLEN/8, x3, x1, x4) + +inst_5269: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8001; +op3val:0xfbff; valaddr_reg:x2; val_offset:15705*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15705*FLEN/8, x3, x1, x4) + +inst_5270: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8001; +op3val:0x7c00; valaddr_reg:x2; val_offset:15708*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15708*FLEN/8, x3, x1, x4) + +inst_5271: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8001; +op3val:0xfc00; valaddr_reg:x2; val_offset:15711*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15711*FLEN/8, x3, x1, x4) + +inst_5272: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8001; +op3val:0x7e00; valaddr_reg:x2; val_offset:15714*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15714*FLEN/8, x3, x1, x4) + +inst_5273: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8001; +op3val:0xfe00; valaddr_reg:x2; val_offset:15717*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15717*FLEN/8, x3, x1, x4) + +inst_5274: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8001; +op3val:0x7e01; valaddr_reg:x2; val_offset:15720*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15720*FLEN/8, x3, x1, x4) + +inst_5275: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8001; +op3val:0xfe55; valaddr_reg:x2; val_offset:15723*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15723*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_42) + +inst_5276: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8001; +op3val:0x7c01; valaddr_reg:x2; val_offset:15726*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15726*FLEN/8, x3, x1, x4) + +inst_5277: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8001; +op3val:0xfd55; valaddr_reg:x2; val_offset:15729*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15729*FLEN/8, x3, x1, x4) + +inst_5278: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8001; +op3val:0x3c00; valaddr_reg:x2; val_offset:15732*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15732*FLEN/8, x3, x1, x4) + +inst_5279: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8001; +op3val:0xbc00; valaddr_reg:x2; val_offset:15735*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15735*FLEN/8, x3, x1, x4) + +inst_5280: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x2; +op3val:0x0; valaddr_reg:x2; val_offset:15738*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15738*FLEN/8, x3, x1, x4) + +inst_5281: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x2; +op3val:0x8000; valaddr_reg:x2; val_offset:15741*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15741*FLEN/8, x3, x1, x4) + +inst_5282: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x2; +op3val:0x1; valaddr_reg:x2; val_offset:15744*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15744*FLEN/8, x3, x1, x4) + +inst_5283: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x2; +op3val:0x8001; valaddr_reg:x2; val_offset:15747*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15747*FLEN/8, x3, x1, x4) + +inst_5284: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x2; +op3val:0x2; valaddr_reg:x2; val_offset:15750*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15750*FLEN/8, x3, x1, x4) + +inst_5285: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x2; +op3val:0x83fe; valaddr_reg:x2; val_offset:15753*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15753*FLEN/8, x3, x1, x4) + +inst_5286: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x2; +op3val:0x3ff; valaddr_reg:x2; val_offset:15756*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15756*FLEN/8, x3, x1, x4) + +inst_5287: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x2; +op3val:0x83ff; valaddr_reg:x2; val_offset:15759*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15759*FLEN/8, x3, x1, x4) + +inst_5288: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x2; +op3val:0x400; valaddr_reg:x2; val_offset:15762*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15762*FLEN/8, x3, x1, x4) + +inst_5289: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x2; +op3val:0x8400; valaddr_reg:x2; val_offset:15765*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15765*FLEN/8, x3, x1, x4) + +inst_5290: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x2; +op3val:0x401; valaddr_reg:x2; val_offset:15768*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15768*FLEN/8, x3, x1, x4) + +inst_5291: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x2; +op3val:0x8455; valaddr_reg:x2; val_offset:15771*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15771*FLEN/8, x3, x1, x4) + +inst_5292: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x2; +op3val:0x7bff; valaddr_reg:x2; val_offset:15774*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15774*FLEN/8, x3, x1, x4) + +inst_5293: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x2; +op3val:0xfbff; valaddr_reg:x2; val_offset:15777*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15777*FLEN/8, x3, x1, x4) + +inst_5294: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x2; +op3val:0x7c00; valaddr_reg:x2; val_offset:15780*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15780*FLEN/8, x3, x1, x4) + +inst_5295: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x2; +op3val:0xfc00; valaddr_reg:x2; val_offset:15783*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15783*FLEN/8, x3, x1, x4) + +inst_5296: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x2; +op3val:0x7e00; valaddr_reg:x2; val_offset:15786*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15786*FLEN/8, x3, x1, x4) + +inst_5297: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x2; +op3val:0xfe00; valaddr_reg:x2; val_offset:15789*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15789*FLEN/8, x3, x1, x4) + +inst_5298: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x2; +op3val:0x7e01; valaddr_reg:x2; val_offset:15792*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15792*FLEN/8, x3, x1, x4) + +inst_5299: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x2; +op3val:0xfe55; valaddr_reg:x2; val_offset:15795*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15795*FLEN/8, x3, x1, x4) + +inst_5300: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x2; +op3val:0x7c01; valaddr_reg:x2; val_offset:15798*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15798*FLEN/8, x3, x1, x4) + +inst_5301: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x2; +op3val:0xfd55; valaddr_reg:x2; val_offset:15801*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15801*FLEN/8, x3, x1, x4) + +inst_5302: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x2; +op3val:0x3c00; valaddr_reg:x2; val_offset:15804*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15804*FLEN/8, x3, x1, x4) + +inst_5303: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x2; +op3val:0xbc00; valaddr_reg:x2; val_offset:15807*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15807*FLEN/8, x3, x1, x4) + +inst_5304: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x83fe; +op3val:0x0; valaddr_reg:x2; val_offset:15810*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15810*FLEN/8, x3, x1, x4) + +inst_5305: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x83fe; +op3val:0x8000; valaddr_reg:x2; val_offset:15813*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15813*FLEN/8, x3, x1, x4) + +inst_5306: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x83fe; +op3val:0x1; valaddr_reg:x2; val_offset:15816*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15816*FLEN/8, x3, x1, x4) + +inst_5307: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x83fe; +op3val:0x8001; valaddr_reg:x2; val_offset:15819*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15819*FLEN/8, x3, x1, x4) + +inst_5308: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x83fe; +op3val:0x2; valaddr_reg:x2; val_offset:15822*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15822*FLEN/8, x3, x1, x4) + +inst_5309: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x83fe; +op3val:0x83fe; valaddr_reg:x2; val_offset:15825*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15825*FLEN/8, x3, x1, x4) + +inst_5310: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x83fe; +op3val:0x3ff; valaddr_reg:x2; val_offset:15828*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15828*FLEN/8, x3, x1, x4) + +inst_5311: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x83fe; +op3val:0x83ff; valaddr_reg:x2; val_offset:15831*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15831*FLEN/8, x3, x1, x4) + +inst_5312: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x83fe; +op3val:0x400; valaddr_reg:x2; val_offset:15834*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15834*FLEN/8, x3, x1, x4) + +inst_5313: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x83fe; +op3val:0x8400; valaddr_reg:x2; val_offset:15837*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15837*FLEN/8, x3, x1, x4) + +inst_5314: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x83fe; +op3val:0x401; valaddr_reg:x2; val_offset:15840*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15840*FLEN/8, x3, x1, x4) + +inst_5315: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x83fe; +op3val:0x8455; valaddr_reg:x2; val_offset:15843*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15843*FLEN/8, x3, x1, x4) + +inst_5316: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x83fe; +op3val:0x7bff; valaddr_reg:x2; val_offset:15846*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15846*FLEN/8, x3, x1, x4) + +inst_5317: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x83fe; +op3val:0xfbff; valaddr_reg:x2; val_offset:15849*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15849*FLEN/8, x3, x1, x4) + +inst_5318: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x83fe; +op3val:0x7c00; valaddr_reg:x2; val_offset:15852*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15852*FLEN/8, x3, x1, x4) + +inst_5319: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x83fe; +op3val:0xfc00; valaddr_reg:x2; val_offset:15855*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15855*FLEN/8, x3, x1, x4) + +inst_5320: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x83fe; +op3val:0x7e00; valaddr_reg:x2; val_offset:15858*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15858*FLEN/8, x3, x1, x4) + +inst_5321: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x83fe; +op3val:0xfe00; valaddr_reg:x2; val_offset:15861*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15861*FLEN/8, x3, x1, x4) + +inst_5322: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x83fe; +op3val:0x7e01; valaddr_reg:x2; val_offset:15864*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15864*FLEN/8, x3, x1, x4) + +inst_5323: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x83fe; +op3val:0xfe55; valaddr_reg:x2; val_offset:15867*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15867*FLEN/8, x3, x1, x4) + +inst_5324: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x83fe; +op3val:0x7c01; valaddr_reg:x2; val_offset:15870*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15870*FLEN/8, x3, x1, x4) + +inst_5325: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x83fe; +op3val:0xfd55; valaddr_reg:x2; val_offset:15873*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15873*FLEN/8, x3, x1, x4) + +inst_5326: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x83fe; +op3val:0x3c00; valaddr_reg:x2; val_offset:15876*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15876*FLEN/8, x3, x1, x4) + +inst_5327: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x83fe; +op3val:0xbc00; valaddr_reg:x2; val_offset:15879*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15879*FLEN/8, x3, x1, x4) + +inst_5328: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x3ff; +op3val:0x0; valaddr_reg:x2; val_offset:15882*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15882*FLEN/8, x3, x1, x4) + +inst_5329: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x3ff; +op3val:0x8000; valaddr_reg:x2; val_offset:15885*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15885*FLEN/8, x3, x1, x4) + +inst_5330: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x3ff; +op3val:0x1; valaddr_reg:x2; val_offset:15888*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15888*FLEN/8, x3, x1, x4) + +inst_5331: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x3ff; +op3val:0x8001; valaddr_reg:x2; val_offset:15891*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15891*FLEN/8, x3, x1, x4) + +inst_5332: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x3ff; +op3val:0x2; valaddr_reg:x2; val_offset:15894*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15894*FLEN/8, x3, x1, x4) + +inst_5333: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x3ff; +op3val:0x83fe; valaddr_reg:x2; val_offset:15897*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15897*FLEN/8, x3, x1, x4) + +inst_5334: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x3ff; +op3val:0x3ff; valaddr_reg:x2; val_offset:15900*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15900*FLEN/8, x3, x1, x4) + +inst_5335: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x3ff; +op3val:0x83ff; valaddr_reg:x2; val_offset:15903*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15903*FLEN/8, x3, x1, x4) + +inst_5336: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x3ff; +op3val:0x400; valaddr_reg:x2; val_offset:15906*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15906*FLEN/8, x3, x1, x4) + +inst_5337: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x3ff; +op3val:0x8400; valaddr_reg:x2; val_offset:15909*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15909*FLEN/8, x3, x1, x4) + +inst_5338: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x3ff; +op3val:0x401; valaddr_reg:x2; val_offset:15912*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15912*FLEN/8, x3, x1, x4) + +inst_5339: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x3ff; +op3val:0x8455; valaddr_reg:x2; val_offset:15915*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15915*FLEN/8, x3, x1, x4) + +inst_5340: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x3ff; +op3val:0x7bff; valaddr_reg:x2; val_offset:15918*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15918*FLEN/8, x3, x1, x4) + +inst_5341: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x3ff; +op3val:0xfbff; valaddr_reg:x2; val_offset:15921*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15921*FLEN/8, x3, x1, x4) + +inst_5342: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x3ff; +op3val:0x7c00; valaddr_reg:x2; val_offset:15924*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15924*FLEN/8, x3, x1, x4) + +inst_5343: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x3ff; +op3val:0xfc00; valaddr_reg:x2; val_offset:15927*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15927*FLEN/8, x3, x1, x4) + +inst_5344: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x3ff; +op3val:0x7e00; valaddr_reg:x2; val_offset:15930*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15930*FLEN/8, x3, x1, x4) + +inst_5345: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x3ff; +op3val:0xfe00; valaddr_reg:x2; val_offset:15933*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15933*FLEN/8, x3, x1, x4) + +inst_5346: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x3ff; +op3val:0x7e01; valaddr_reg:x2; val_offset:15936*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15936*FLEN/8, x3, x1, x4) + +inst_5347: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x3ff; +op3val:0xfe55; valaddr_reg:x2; val_offset:15939*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15939*FLEN/8, x3, x1, x4) + +inst_5348: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x3ff; +op3val:0x7c01; valaddr_reg:x2; val_offset:15942*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15942*FLEN/8, x3, x1, x4) + +inst_5349: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x3ff; +op3val:0xfd55; valaddr_reg:x2; val_offset:15945*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15945*FLEN/8, x3, x1, x4) + +inst_5350: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x3ff; +op3val:0x3c00; valaddr_reg:x2; val_offset:15948*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15948*FLEN/8, x3, x1, x4) + +inst_5351: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x3ff; +op3val:0xbc00; valaddr_reg:x2; val_offset:15951*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15951*FLEN/8, x3, x1, x4) + +inst_5352: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x83ff; +op3val:0x0; valaddr_reg:x2; val_offset:15954*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15954*FLEN/8, x3, x1, x4) + +inst_5353: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x83ff; +op3val:0x8000; valaddr_reg:x2; val_offset:15957*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15957*FLEN/8, x3, x1, x4) + +inst_5354: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x83ff; +op3val:0x1; valaddr_reg:x2; val_offset:15960*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15960*FLEN/8, x3, x1, x4) + +inst_5355: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x83ff; +op3val:0x8001; valaddr_reg:x2; val_offset:15963*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15963*FLEN/8, x3, x1, x4) + +inst_5356: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x83ff; +op3val:0x2; valaddr_reg:x2; val_offset:15966*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15966*FLEN/8, x3, x1, x4) + +inst_5357: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x83ff; +op3val:0x83fe; valaddr_reg:x2; val_offset:15969*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15969*FLEN/8, x3, x1, x4) + +inst_5358: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x83ff; +op3val:0x3ff; valaddr_reg:x2; val_offset:15972*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15972*FLEN/8, x3, x1, x4) + +inst_5359: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x83ff; +op3val:0x83ff; valaddr_reg:x2; val_offset:15975*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15975*FLEN/8, x3, x1, x4) + +inst_5360: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x83ff; +op3val:0x400; valaddr_reg:x2; val_offset:15978*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15978*FLEN/8, x3, x1, x4) + +inst_5361: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x83ff; +op3val:0x8400; valaddr_reg:x2; val_offset:15981*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15981*FLEN/8, x3, x1, x4) + +inst_5362: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x83ff; +op3val:0x401; valaddr_reg:x2; val_offset:15984*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15984*FLEN/8, x3, x1, x4) + +inst_5363: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x83ff; +op3val:0x8455; valaddr_reg:x2; val_offset:15987*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15987*FLEN/8, x3, x1, x4) + +inst_5364: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x83ff; +op3val:0x7bff; valaddr_reg:x2; val_offset:15990*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15990*FLEN/8, x3, x1, x4) + +inst_5365: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x83ff; +op3val:0xfbff; valaddr_reg:x2; val_offset:15993*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15993*FLEN/8, x3, x1, x4) + +inst_5366: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x83ff; +op3val:0x7c00; valaddr_reg:x2; val_offset:15996*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15996*FLEN/8, x3, x1, x4) + +inst_5367: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x83ff; +op3val:0xfc00; valaddr_reg:x2; val_offset:15999*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15999*FLEN/8, x3, x1, x4) + +inst_5368: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x83ff; +op3val:0x7e00; valaddr_reg:x2; val_offset:16002*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16002*FLEN/8, x3, x1, x4) + +inst_5369: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x83ff; +op3val:0xfe00; valaddr_reg:x2; val_offset:16005*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16005*FLEN/8, x3, x1, x4) + +inst_5370: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x83ff; +op3val:0x7e01; valaddr_reg:x2; val_offset:16008*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16008*FLEN/8, x3, x1, x4) + +inst_5371: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x83ff; +op3val:0xfe55; valaddr_reg:x2; val_offset:16011*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16011*FLEN/8, x3, x1, x4) + +inst_5372: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x83ff; +op3val:0x7c01; valaddr_reg:x2; val_offset:16014*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16014*FLEN/8, x3, x1, x4) + +inst_5373: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x83ff; +op3val:0xfd55; valaddr_reg:x2; val_offset:16017*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16017*FLEN/8, x3, x1, x4) + +inst_5374: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x83ff; +op3val:0x3c00; valaddr_reg:x2; val_offset:16020*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16020*FLEN/8, x3, x1, x4) + +inst_5375: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x83ff; +op3val:0xbc00; valaddr_reg:x2; val_offset:16023*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16023*FLEN/8, x3, x1, x4) + +inst_5376: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x400; +op3val:0x0; valaddr_reg:x2; val_offset:16026*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16026*FLEN/8, x3, x1, x4) + +inst_5377: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x400; +op3val:0x8000; valaddr_reg:x2; val_offset:16029*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16029*FLEN/8, x3, x1, x4) + +inst_5378: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x400; +op3val:0x1; valaddr_reg:x2; val_offset:16032*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16032*FLEN/8, x3, x1, x4) + +inst_5379: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x400; +op3val:0x8001; valaddr_reg:x2; val_offset:16035*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16035*FLEN/8, x3, x1, x4) + +inst_5380: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x400; +op3val:0x2; valaddr_reg:x2; val_offset:16038*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16038*FLEN/8, x3, x1, x4) + +inst_5381: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x400; +op3val:0x83fe; valaddr_reg:x2; val_offset:16041*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16041*FLEN/8, x3, x1, x4) + +inst_5382: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x400; +op3val:0x3ff; valaddr_reg:x2; val_offset:16044*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16044*FLEN/8, x3, x1, x4) + +inst_5383: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x400; +op3val:0x83ff; valaddr_reg:x2; val_offset:16047*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16047*FLEN/8, x3, x1, x4) + +inst_5384: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x400; +op3val:0x400; valaddr_reg:x2; val_offset:16050*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16050*FLEN/8, x3, x1, x4) + +inst_5385: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x400; +op3val:0x8400; valaddr_reg:x2; val_offset:16053*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16053*FLEN/8, x3, x1, x4) + +inst_5386: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x400; +op3val:0x401; valaddr_reg:x2; val_offset:16056*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16056*FLEN/8, x3, x1, x4) + +inst_5387: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x400; +op3val:0x8455; valaddr_reg:x2; val_offset:16059*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16059*FLEN/8, x3, x1, x4) + +inst_5388: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x400; +op3val:0x7bff; valaddr_reg:x2; val_offset:16062*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16062*FLEN/8, x3, x1, x4) + +inst_5389: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x400; +op3val:0xfbff; valaddr_reg:x2; val_offset:16065*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16065*FLEN/8, x3, x1, x4) + +inst_5390: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x400; +op3val:0x7c00; valaddr_reg:x2; val_offset:16068*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16068*FLEN/8, x3, x1, x4) + +inst_5391: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x400; +op3val:0xfc00; valaddr_reg:x2; val_offset:16071*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16071*FLEN/8, x3, x1, x4) + +inst_5392: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x400; +op3val:0x7e00; valaddr_reg:x2; val_offset:16074*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16074*FLEN/8, x3, x1, x4) + +inst_5393: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x400; +op3val:0xfe00; valaddr_reg:x2; val_offset:16077*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16077*FLEN/8, x3, x1, x4) + +inst_5394: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x400; +op3val:0x7e01; valaddr_reg:x2; val_offset:16080*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16080*FLEN/8, x3, x1, x4) + +inst_5395: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x400; +op3val:0xfe55; valaddr_reg:x2; val_offset:16083*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16083*FLEN/8, x3, x1, x4) + +inst_5396: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x400; +op3val:0x7c01; valaddr_reg:x2; val_offset:16086*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16086*FLEN/8, x3, x1, x4) + +inst_5397: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x400; +op3val:0xfd55; valaddr_reg:x2; val_offset:16089*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16089*FLEN/8, x3, x1, x4) + +inst_5398: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x400; +op3val:0x3c00; valaddr_reg:x2; val_offset:16092*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16092*FLEN/8, x3, x1, x4) + +inst_5399: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x400; +op3val:0xbc00; valaddr_reg:x2; val_offset:16095*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16095*FLEN/8, x3, x1, x4) + +inst_5400: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8400; +op3val:0x0; valaddr_reg:x2; val_offset:16098*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16098*FLEN/8, x3, x1, x4) + +inst_5401: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8400; +op3val:0x8000; valaddr_reg:x2; val_offset:16101*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16101*FLEN/8, x3, x1, x4) + +inst_5402: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8400; +op3val:0x1; valaddr_reg:x2; val_offset:16104*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16104*FLEN/8, x3, x1, x4) + +inst_5403: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8400; +op3val:0x8001; valaddr_reg:x2; val_offset:16107*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16107*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_43) + +inst_5404: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8400; +op3val:0x2; valaddr_reg:x2; val_offset:16110*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16110*FLEN/8, x3, x1, x4) + +inst_5405: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8400; +op3val:0x83fe; valaddr_reg:x2; val_offset:16113*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16113*FLEN/8, x3, x1, x4) + +inst_5406: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8400; +op3val:0x3ff; valaddr_reg:x2; val_offset:16116*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16116*FLEN/8, x3, x1, x4) + +inst_5407: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8400; +op3val:0x83ff; valaddr_reg:x2; val_offset:16119*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16119*FLEN/8, x3, x1, x4) + +inst_5408: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8400; +op3val:0x400; valaddr_reg:x2; val_offset:16122*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16122*FLEN/8, x3, x1, x4) + +inst_5409: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8400; +op3val:0x8400; valaddr_reg:x2; val_offset:16125*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16125*FLEN/8, x3, x1, x4) + +inst_5410: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8400; +op3val:0x401; valaddr_reg:x2; val_offset:16128*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16128*FLEN/8, x3, x1, x4) + +inst_5411: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8400; +op3val:0x8455; valaddr_reg:x2; val_offset:16131*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16131*FLEN/8, x3, x1, x4) + +inst_5412: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8400; +op3val:0x7bff; valaddr_reg:x2; val_offset:16134*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16134*FLEN/8, x3, x1, x4) + +inst_5413: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8400; +op3val:0xfbff; valaddr_reg:x2; val_offset:16137*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16137*FLEN/8, x3, x1, x4) + +inst_5414: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8400; +op3val:0x7c00; valaddr_reg:x2; val_offset:16140*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16140*FLEN/8, x3, x1, x4) + +inst_5415: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8400; +op3val:0xfc00; valaddr_reg:x2; val_offset:16143*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16143*FLEN/8, x3, x1, x4) + +inst_5416: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8400; +op3val:0x7e00; valaddr_reg:x2; val_offset:16146*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16146*FLEN/8, x3, x1, x4) + +inst_5417: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8400; +op3val:0xfe00; valaddr_reg:x2; val_offset:16149*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16149*FLEN/8, x3, x1, x4) + +inst_5418: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8400; +op3val:0x7e01; valaddr_reg:x2; val_offset:16152*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16152*FLEN/8, x3, x1, x4) + +inst_5419: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8400; +op3val:0xfe55; valaddr_reg:x2; val_offset:16155*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16155*FLEN/8, x3, x1, x4) + +inst_5420: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8400; +op3val:0x7c01; valaddr_reg:x2; val_offset:16158*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16158*FLEN/8, x3, x1, x4) + +inst_5421: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8400; +op3val:0xfd55; valaddr_reg:x2; val_offset:16161*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16161*FLEN/8, x3, x1, x4) + +inst_5422: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8400; +op3val:0x3c00; valaddr_reg:x2; val_offset:16164*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16164*FLEN/8, x3, x1, x4) + +inst_5423: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8400; +op3val:0xbc00; valaddr_reg:x2; val_offset:16167*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16167*FLEN/8, x3, x1, x4) + +inst_5424: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x401; +op3val:0x0; valaddr_reg:x2; val_offset:16170*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16170*FLEN/8, x3, x1, x4) + +inst_5425: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x401; +op3val:0x8000; valaddr_reg:x2; val_offset:16173*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16173*FLEN/8, x3, x1, x4) + +inst_5426: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x401; +op3val:0x1; valaddr_reg:x2; val_offset:16176*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16176*FLEN/8, x3, x1, x4) + +inst_5427: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x401; +op3val:0x8001; valaddr_reg:x2; val_offset:16179*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16179*FLEN/8, x3, x1, x4) + +inst_5428: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x401; +op3val:0x2; valaddr_reg:x2; val_offset:16182*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16182*FLEN/8, x3, x1, x4) + +inst_5429: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x401; +op3val:0x83fe; valaddr_reg:x2; val_offset:16185*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16185*FLEN/8, x3, x1, x4) + +inst_5430: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x401; +op3val:0x3ff; valaddr_reg:x2; val_offset:16188*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16188*FLEN/8, x3, x1, x4) + +inst_5431: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x401; +op3val:0x83ff; valaddr_reg:x2; val_offset:16191*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16191*FLEN/8, x3, x1, x4) + +inst_5432: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x401; +op3val:0x400; valaddr_reg:x2; val_offset:16194*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16194*FLEN/8, x3, x1, x4) + +inst_5433: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x401; +op3val:0x8400; valaddr_reg:x2; val_offset:16197*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16197*FLEN/8, x3, x1, x4) + +inst_5434: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x401; +op3val:0x401; valaddr_reg:x2; val_offset:16200*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16200*FLEN/8, x3, x1, x4) + +inst_5435: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x401; +op3val:0x8455; valaddr_reg:x2; val_offset:16203*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16203*FLEN/8, x3, x1, x4) + +inst_5436: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x401; +op3val:0x7bff; valaddr_reg:x2; val_offset:16206*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16206*FLEN/8, x3, x1, x4) + +inst_5437: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x401; +op3val:0xfbff; valaddr_reg:x2; val_offset:16209*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16209*FLEN/8, x3, x1, x4) + +inst_5438: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x401; +op3val:0x7c00; valaddr_reg:x2; val_offset:16212*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16212*FLEN/8, x3, x1, x4) + +inst_5439: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x401; +op3val:0xfc00; valaddr_reg:x2; val_offset:16215*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16215*FLEN/8, x3, x1, x4) + +inst_5440: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x401; +op3val:0x7e00; valaddr_reg:x2; val_offset:16218*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16218*FLEN/8, x3, x1, x4) + +inst_5441: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x401; +op3val:0xfe00; valaddr_reg:x2; val_offset:16221*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16221*FLEN/8, x3, x1, x4) + +inst_5442: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x401; +op3val:0x7e01; valaddr_reg:x2; val_offset:16224*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16224*FLEN/8, x3, x1, x4) + +inst_5443: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x401; +op3val:0xfe55; valaddr_reg:x2; val_offset:16227*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16227*FLEN/8, x3, x1, x4) + +inst_5444: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x401; +op3val:0x7c01; valaddr_reg:x2; val_offset:16230*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16230*FLEN/8, x3, x1, x4) + +inst_5445: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x401; +op3val:0xfd55; valaddr_reg:x2; val_offset:16233*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16233*FLEN/8, x3, x1, x4) + +inst_5446: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x401; +op3val:0x3c00; valaddr_reg:x2; val_offset:16236*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16236*FLEN/8, x3, x1, x4) + +inst_5447: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x401; +op3val:0xbc00; valaddr_reg:x2; val_offset:16239*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16239*FLEN/8, x3, x1, x4) + +inst_5448: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8455; +op3val:0x0; valaddr_reg:x2; val_offset:16242*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16242*FLEN/8, x3, x1, x4) + +inst_5449: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8455; +op3val:0x8000; valaddr_reg:x2; val_offset:16245*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16245*FLEN/8, x3, x1, x4) + +inst_5450: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8455; +op3val:0x1; valaddr_reg:x2; val_offset:16248*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16248*FLEN/8, x3, x1, x4) + +inst_5451: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8455; +op3val:0x8001; valaddr_reg:x2; val_offset:16251*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16251*FLEN/8, x3, x1, x4) + +inst_5452: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8455; +op3val:0x2; valaddr_reg:x2; val_offset:16254*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16254*FLEN/8, x3, x1, x4) + +inst_5453: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8455; +op3val:0x83fe; valaddr_reg:x2; val_offset:16257*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16257*FLEN/8, x3, x1, x4) + +inst_5454: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8455; +op3val:0x3ff; valaddr_reg:x2; val_offset:16260*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16260*FLEN/8, x3, x1, x4) + +inst_5455: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8455; +op3val:0x83ff; valaddr_reg:x2; val_offset:16263*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16263*FLEN/8, x3, x1, x4) + +inst_5456: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8455; +op3val:0x400; valaddr_reg:x2; val_offset:16266*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16266*FLEN/8, x3, x1, x4) + +inst_5457: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8455; +op3val:0x8400; valaddr_reg:x2; val_offset:16269*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16269*FLEN/8, x3, x1, x4) + +inst_5458: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8455; +op3val:0x401; valaddr_reg:x2; val_offset:16272*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16272*FLEN/8, x3, x1, x4) + +inst_5459: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8455; +op3val:0x8455; valaddr_reg:x2; val_offset:16275*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16275*FLEN/8, x3, x1, x4) + +inst_5460: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8455; +op3val:0x7bff; valaddr_reg:x2; val_offset:16278*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16278*FLEN/8, x3, x1, x4) + +inst_5461: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8455; +op3val:0xfbff; valaddr_reg:x2; val_offset:16281*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16281*FLEN/8, x3, x1, x4) + +inst_5462: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8455; +op3val:0x7c00; valaddr_reg:x2; val_offset:16284*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16284*FLEN/8, x3, x1, x4) + +inst_5463: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8455; +op3val:0xfc00; valaddr_reg:x2; val_offset:16287*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16287*FLEN/8, x3, x1, x4) + +inst_5464: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8455; +op3val:0x7e00; valaddr_reg:x2; val_offset:16290*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16290*FLEN/8, x3, x1, x4) + +inst_5465: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8455; +op3val:0xfe00; valaddr_reg:x2; val_offset:16293*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16293*FLEN/8, x3, x1, x4) + +inst_5466: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8455; +op3val:0x7e01; valaddr_reg:x2; val_offset:16296*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16296*FLEN/8, x3, x1, x4) + +inst_5467: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8455; +op3val:0xfe55; valaddr_reg:x2; val_offset:16299*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16299*FLEN/8, x3, x1, x4) + +inst_5468: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8455; +op3val:0x7c01; valaddr_reg:x2; val_offset:16302*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16302*FLEN/8, x3, x1, x4) + +inst_5469: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8455; +op3val:0xfd55; valaddr_reg:x2; val_offset:16305*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16305*FLEN/8, x3, x1, x4) + +inst_5470: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8455; +op3val:0x3c00; valaddr_reg:x2; val_offset:16308*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16308*FLEN/8, x3, x1, x4) + +inst_5471: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x8455; +op3val:0xbc00; valaddr_reg:x2; val_offset:16311*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16311*FLEN/8, x3, x1, x4) + +inst_5472: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7bff; +op3val:0x0; valaddr_reg:x2; val_offset:16314*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16314*FLEN/8, x3, x1, x4) + +inst_5473: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7bff; +op3val:0x8000; valaddr_reg:x2; val_offset:16317*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16317*FLEN/8, x3, x1, x4) + +inst_5474: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7bff; +op3val:0x1; valaddr_reg:x2; val_offset:16320*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16320*FLEN/8, x3, x1, x4) + +inst_5475: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7bff; +op3val:0x8001; valaddr_reg:x2; val_offset:16323*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16323*FLEN/8, x3, x1, x4) + +inst_5476: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7bff; +op3val:0x2; valaddr_reg:x2; val_offset:16326*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16326*FLEN/8, x3, x1, x4) + +inst_5477: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7bff; +op3val:0x83fe; valaddr_reg:x2; val_offset:16329*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16329*FLEN/8, x3, x1, x4) + +inst_5478: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7bff; +op3val:0x3ff; valaddr_reg:x2; val_offset:16332*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16332*FLEN/8, x3, x1, x4) + +inst_5479: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7bff; +op3val:0x83ff; valaddr_reg:x2; val_offset:16335*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16335*FLEN/8, x3, x1, x4) + +inst_5480: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7bff; +op3val:0x400; valaddr_reg:x2; val_offset:16338*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16338*FLEN/8, x3, x1, x4) + +inst_5481: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7bff; +op3val:0x8400; valaddr_reg:x2; val_offset:16341*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16341*FLEN/8, x3, x1, x4) + +inst_5482: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7bff; +op3val:0x401; valaddr_reg:x2; val_offset:16344*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16344*FLEN/8, x3, x1, x4) + +inst_5483: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7bff; +op3val:0x8455; valaddr_reg:x2; val_offset:16347*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16347*FLEN/8, x3, x1, x4) + +inst_5484: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7bff; +op3val:0x7bff; valaddr_reg:x2; val_offset:16350*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16350*FLEN/8, x3, x1, x4) + +inst_5485: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7bff; +op3val:0xfbff; valaddr_reg:x2; val_offset:16353*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16353*FLEN/8, x3, x1, x4) + +inst_5486: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7bff; +op3val:0x7c00; valaddr_reg:x2; val_offset:16356*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16356*FLEN/8, x3, x1, x4) + +inst_5487: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7bff; +op3val:0xfc00; valaddr_reg:x2; val_offset:16359*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16359*FLEN/8, x3, x1, x4) + +inst_5488: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7bff; +op3val:0x7e00; valaddr_reg:x2; val_offset:16362*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16362*FLEN/8, x3, x1, x4) + +inst_5489: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7bff; +op3val:0xfe00; valaddr_reg:x2; val_offset:16365*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16365*FLEN/8, x3, x1, x4) + +inst_5490: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7bff; +op3val:0x7e01; valaddr_reg:x2; val_offset:16368*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16368*FLEN/8, x3, x1, x4) + +inst_5491: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7bff; +op3val:0xfe55; valaddr_reg:x2; val_offset:16371*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16371*FLEN/8, x3, x1, x4) + +inst_5492: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7bff; +op3val:0x7c01; valaddr_reg:x2; val_offset:16374*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16374*FLEN/8, x3, x1, x4) + +inst_5493: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7bff; +op3val:0xfd55; valaddr_reg:x2; val_offset:16377*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16377*FLEN/8, x3, x1, x4) + +inst_5494: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7bff; +op3val:0x3c00; valaddr_reg:x2; val_offset:16380*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16380*FLEN/8, x3, x1, x4) + +inst_5495: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7bff; +op3val:0xbc00; valaddr_reg:x2; val_offset:16383*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16383*FLEN/8, x3, x1, x4) + +inst_5496: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfbff; +op3val:0x0; valaddr_reg:x2; val_offset:16386*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16386*FLEN/8, x3, x1, x4) + +inst_5497: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfbff; +op3val:0x8000; valaddr_reg:x2; val_offset:16389*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16389*FLEN/8, x3, x1, x4) + +inst_5498: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfbff; +op3val:0x1; valaddr_reg:x2; val_offset:16392*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16392*FLEN/8, x3, x1, x4) + +inst_5499: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfbff; +op3val:0x8001; valaddr_reg:x2; val_offset:16395*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16395*FLEN/8, x3, x1, x4) + +inst_5500: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfbff; +op3val:0x2; valaddr_reg:x2; val_offset:16398*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16398*FLEN/8, x3, x1, x4) + +inst_5501: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfbff; +op3val:0x83fe; valaddr_reg:x2; val_offset:16401*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16401*FLEN/8, x3, x1, x4) + +inst_5502: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfbff; +op3val:0x3ff; valaddr_reg:x2; val_offset:16404*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16404*FLEN/8, x3, x1, x4) + +inst_5503: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfbff; +op3val:0x83ff; valaddr_reg:x2; val_offset:16407*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16407*FLEN/8, x3, x1, x4) + +inst_5504: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfbff; +op3val:0x400; valaddr_reg:x2; val_offset:16410*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16410*FLEN/8, x3, x1, x4) + +inst_5505: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfbff; +op3val:0x8400; valaddr_reg:x2; val_offset:16413*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16413*FLEN/8, x3, x1, x4) + +inst_5506: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfbff; +op3val:0x401; valaddr_reg:x2; val_offset:16416*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16416*FLEN/8, x3, x1, x4) + +inst_5507: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfbff; +op3val:0x8455; valaddr_reg:x2; val_offset:16419*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16419*FLEN/8, x3, x1, x4) + +inst_5508: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfbff; +op3val:0x7bff; valaddr_reg:x2; val_offset:16422*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16422*FLEN/8, x3, x1, x4) + +inst_5509: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfbff; +op3val:0xfbff; valaddr_reg:x2; val_offset:16425*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16425*FLEN/8, x3, x1, x4) + +inst_5510: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfbff; +op3val:0x7c00; valaddr_reg:x2; val_offset:16428*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16428*FLEN/8, x3, x1, x4) + +inst_5511: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfbff; +op3val:0xfc00; valaddr_reg:x2; val_offset:16431*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16431*FLEN/8, x3, x1, x4) + +inst_5512: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfbff; +op3val:0x7e00; valaddr_reg:x2; val_offset:16434*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16434*FLEN/8, x3, x1, x4) + +inst_5513: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfbff; +op3val:0xfe00; valaddr_reg:x2; val_offset:16437*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16437*FLEN/8, x3, x1, x4) + +inst_5514: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfbff; +op3val:0x7e01; valaddr_reg:x2; val_offset:16440*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16440*FLEN/8, x3, x1, x4) + +inst_5515: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfbff; +op3val:0xfe55; valaddr_reg:x2; val_offset:16443*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16443*FLEN/8, x3, x1, x4) + +inst_5516: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfbff; +op3val:0x7c01; valaddr_reg:x2; val_offset:16446*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16446*FLEN/8, x3, x1, x4) + +inst_5517: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfbff; +op3val:0xfd55; valaddr_reg:x2; val_offset:16449*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16449*FLEN/8, x3, x1, x4) + +inst_5518: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfbff; +op3val:0x3c00; valaddr_reg:x2; val_offset:16452*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16452*FLEN/8, x3, x1, x4) + +inst_5519: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfbff; +op3val:0xbc00; valaddr_reg:x2; val_offset:16455*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16455*FLEN/8, x3, x1, x4) + +inst_5520: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7c00; +op3val:0x0; valaddr_reg:x2; val_offset:16458*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16458*FLEN/8, x3, x1, x4) + +inst_5521: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7c00; +op3val:0x8000; valaddr_reg:x2; val_offset:16461*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16461*FLEN/8, x3, x1, x4) + +inst_5522: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7c00; +op3val:0x1; valaddr_reg:x2; val_offset:16464*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16464*FLEN/8, x3, x1, x4) + +inst_5523: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7c00; +op3val:0x8001; valaddr_reg:x2; val_offset:16467*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16467*FLEN/8, x3, x1, x4) + +inst_5524: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7c00; +op3val:0x2; valaddr_reg:x2; val_offset:16470*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16470*FLEN/8, x3, x1, x4) + +inst_5525: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7c00; +op3val:0x83fe; valaddr_reg:x2; val_offset:16473*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16473*FLEN/8, x3, x1, x4) + +inst_5526: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7c00; +op3val:0x3ff; valaddr_reg:x2; val_offset:16476*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16476*FLEN/8, x3, x1, x4) + +inst_5527: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7c00; +op3val:0x83ff; valaddr_reg:x2; val_offset:16479*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16479*FLEN/8, x3, x1, x4) + +inst_5528: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7c00; +op3val:0x400; valaddr_reg:x2; val_offset:16482*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16482*FLEN/8, x3, x1, x4) + +inst_5529: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7c00; +op3val:0x8400; valaddr_reg:x2; val_offset:16485*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16485*FLEN/8, x3, x1, x4) + +inst_5530: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7c00; +op3val:0x401; valaddr_reg:x2; val_offset:16488*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16488*FLEN/8, x3, x1, x4) + +inst_5531: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7c00; +op3val:0x8455; valaddr_reg:x2; val_offset:16491*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16491*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_44) + +inst_5532: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7c00; +op3val:0x7bff; valaddr_reg:x2; val_offset:16494*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16494*FLEN/8, x3, x1, x4) + +inst_5533: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7c00; +op3val:0xfbff; valaddr_reg:x2; val_offset:16497*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16497*FLEN/8, x3, x1, x4) + +inst_5534: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7c00; +op3val:0x7c00; valaddr_reg:x2; val_offset:16500*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16500*FLEN/8, x3, x1, x4) + +inst_5535: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7c00; +op3val:0xfc00; valaddr_reg:x2; val_offset:16503*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16503*FLEN/8, x3, x1, x4) + +inst_5536: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7c00; +op3val:0x7e00; valaddr_reg:x2; val_offset:16506*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16506*FLEN/8, x3, x1, x4) + +inst_5537: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7c00; +op3val:0xfe00; valaddr_reg:x2; val_offset:16509*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16509*FLEN/8, x3, x1, x4) + +inst_5538: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7c00; +op3val:0x7e01; valaddr_reg:x2; val_offset:16512*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16512*FLEN/8, x3, x1, x4) + +inst_5539: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7c00; +op3val:0xfe55; valaddr_reg:x2; val_offset:16515*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16515*FLEN/8, x3, x1, x4) + +inst_5540: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7c00; +op3val:0x7c01; valaddr_reg:x2; val_offset:16518*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16518*FLEN/8, x3, x1, x4) + +inst_5541: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7c00; +op3val:0xfd55; valaddr_reg:x2; val_offset:16521*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16521*FLEN/8, x3, x1, x4) + +inst_5542: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7c00; +op3val:0x3c00; valaddr_reg:x2; val_offset:16524*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16524*FLEN/8, x3, x1, x4) + +inst_5543: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7c00; +op3val:0xbc00; valaddr_reg:x2; val_offset:16527*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16527*FLEN/8, x3, x1, x4) + +inst_5544: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfc00; +op3val:0x0; valaddr_reg:x2; val_offset:16530*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16530*FLEN/8, x3, x1, x4) + +inst_5545: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfc00; +op3val:0x8000; valaddr_reg:x2; val_offset:16533*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16533*FLEN/8, x3, x1, x4) + +inst_5546: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfc00; +op3val:0x1; valaddr_reg:x2; val_offset:16536*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16536*FLEN/8, x3, x1, x4) + +inst_5547: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfc00; +op3val:0x8001; valaddr_reg:x2; val_offset:16539*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16539*FLEN/8, x3, x1, x4) + +inst_5548: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfc00; +op3val:0x2; valaddr_reg:x2; val_offset:16542*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16542*FLEN/8, x3, x1, x4) + +inst_5549: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfc00; +op3val:0x83fe; valaddr_reg:x2; val_offset:16545*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16545*FLEN/8, x3, x1, x4) + +inst_5550: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfc00; +op3val:0x3ff; valaddr_reg:x2; val_offset:16548*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16548*FLEN/8, x3, x1, x4) + +inst_5551: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfc00; +op3val:0x83ff; valaddr_reg:x2; val_offset:16551*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16551*FLEN/8, x3, x1, x4) + +inst_5552: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfc00; +op3val:0x400; valaddr_reg:x2; val_offset:16554*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16554*FLEN/8, x3, x1, x4) + +inst_5553: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfc00; +op3val:0x8400; valaddr_reg:x2; val_offset:16557*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16557*FLEN/8, x3, x1, x4) + +inst_5554: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfc00; +op3val:0x401; valaddr_reg:x2; val_offset:16560*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16560*FLEN/8, x3, x1, x4) + +inst_5555: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfc00; +op3val:0x8455; valaddr_reg:x2; val_offset:16563*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16563*FLEN/8, x3, x1, x4) + +inst_5556: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfc00; +op3val:0x7bff; valaddr_reg:x2; val_offset:16566*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16566*FLEN/8, x3, x1, x4) + +inst_5557: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfc00; +op3val:0xfbff; valaddr_reg:x2; val_offset:16569*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16569*FLEN/8, x3, x1, x4) + +inst_5558: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfc00; +op3val:0x7c00; valaddr_reg:x2; val_offset:16572*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16572*FLEN/8, x3, x1, x4) + +inst_5559: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfc00; +op3val:0xfc00; valaddr_reg:x2; val_offset:16575*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16575*FLEN/8, x3, x1, x4) + +inst_5560: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfc00; +op3val:0x7e00; valaddr_reg:x2; val_offset:16578*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16578*FLEN/8, x3, x1, x4) + +inst_5561: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfc00; +op3val:0xfe00; valaddr_reg:x2; val_offset:16581*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16581*FLEN/8, x3, x1, x4) + +inst_5562: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfc00; +op3val:0x7e01; valaddr_reg:x2; val_offset:16584*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16584*FLEN/8, x3, x1, x4) + +inst_5563: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfc00; +op3val:0xfe55; valaddr_reg:x2; val_offset:16587*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16587*FLEN/8, x3, x1, x4) + +inst_5564: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfc00; +op3val:0x7c01; valaddr_reg:x2; val_offset:16590*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16590*FLEN/8, x3, x1, x4) + +inst_5565: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfc00; +op3val:0xfd55; valaddr_reg:x2; val_offset:16593*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16593*FLEN/8, x3, x1, x4) + +inst_5566: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfc00; +op3val:0x3c00; valaddr_reg:x2; val_offset:16596*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16596*FLEN/8, x3, x1, x4) + +inst_5567: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfc00; +op3val:0xbc00; valaddr_reg:x2; val_offset:16599*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16599*FLEN/8, x3, x1, x4) + +inst_5568: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7e00; +op3val:0x0; valaddr_reg:x2; val_offset:16602*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16602*FLEN/8, x3, x1, x4) + +inst_5569: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7e00; +op3val:0x8000; valaddr_reg:x2; val_offset:16605*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16605*FLEN/8, x3, x1, x4) + +inst_5570: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7e00; +op3val:0x1; valaddr_reg:x2; val_offset:16608*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16608*FLEN/8, x3, x1, x4) + +inst_5571: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7e00; +op3val:0x8001; valaddr_reg:x2; val_offset:16611*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16611*FLEN/8, x3, x1, x4) + +inst_5572: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7e00; +op3val:0x2; valaddr_reg:x2; val_offset:16614*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16614*FLEN/8, x3, x1, x4) + +inst_5573: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7e00; +op3val:0x83fe; valaddr_reg:x2; val_offset:16617*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16617*FLEN/8, x3, x1, x4) + +inst_5574: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7e00; +op3val:0x3ff; valaddr_reg:x2; val_offset:16620*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16620*FLEN/8, x3, x1, x4) + +inst_5575: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7e00; +op3val:0x83ff; valaddr_reg:x2; val_offset:16623*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16623*FLEN/8, x3, x1, x4) + +inst_5576: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7e00; +op3val:0x400; valaddr_reg:x2; val_offset:16626*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16626*FLEN/8, x3, x1, x4) + +inst_5577: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7e00; +op3val:0x8400; valaddr_reg:x2; val_offset:16629*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16629*FLEN/8, x3, x1, x4) + +inst_5578: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7e00; +op3val:0x401; valaddr_reg:x2; val_offset:16632*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16632*FLEN/8, x3, x1, x4) + +inst_5579: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7e00; +op3val:0x8455; valaddr_reg:x2; val_offset:16635*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16635*FLEN/8, x3, x1, x4) + +inst_5580: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7e00; +op3val:0x7bff; valaddr_reg:x2; val_offset:16638*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16638*FLEN/8, x3, x1, x4) + +inst_5581: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7e00; +op3val:0xfbff; valaddr_reg:x2; val_offset:16641*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16641*FLEN/8, x3, x1, x4) + +inst_5582: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7e00; +op3val:0x7c00; valaddr_reg:x2; val_offset:16644*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16644*FLEN/8, x3, x1, x4) + +inst_5583: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7e00; +op3val:0xfc00; valaddr_reg:x2; val_offset:16647*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16647*FLEN/8, x3, x1, x4) + +inst_5584: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7e00; +op3val:0x7e00; valaddr_reg:x2; val_offset:16650*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16650*FLEN/8, x3, x1, x4) + +inst_5585: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7e00; +op3val:0xfe00; valaddr_reg:x2; val_offset:16653*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16653*FLEN/8, x3, x1, x4) + +inst_5586: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7e00; +op3val:0x7e01; valaddr_reg:x2; val_offset:16656*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16656*FLEN/8, x3, x1, x4) + +inst_5587: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7e00; +op3val:0xfe55; valaddr_reg:x2; val_offset:16659*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16659*FLEN/8, x3, x1, x4) + +inst_5588: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7e00; +op3val:0x7c01; valaddr_reg:x2; val_offset:16662*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16662*FLEN/8, x3, x1, x4) + +inst_5589: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7e00; +op3val:0xfd55; valaddr_reg:x2; val_offset:16665*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16665*FLEN/8, x3, x1, x4) + +inst_5590: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7e00; +op3val:0x3c00; valaddr_reg:x2; val_offset:16668*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16668*FLEN/8, x3, x1, x4) + +inst_5591: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7e00; +op3val:0xbc00; valaddr_reg:x2; val_offset:16671*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16671*FLEN/8, x3, x1, x4) + +inst_5592: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfe00; +op3val:0x0; valaddr_reg:x2; val_offset:16674*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16674*FLEN/8, x3, x1, x4) + +inst_5593: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfe00; +op3val:0x8000; valaddr_reg:x2; val_offset:16677*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16677*FLEN/8, x3, x1, x4) + +inst_5594: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfe00; +op3val:0x1; valaddr_reg:x2; val_offset:16680*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16680*FLEN/8, x3, x1, x4) + +inst_5595: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfe00; +op3val:0x8001; valaddr_reg:x2; val_offset:16683*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16683*FLEN/8, x3, x1, x4) + +inst_5596: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfe00; +op3val:0x2; valaddr_reg:x2; val_offset:16686*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16686*FLEN/8, x3, x1, x4) + +inst_5597: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfe00; +op3val:0x83fe; valaddr_reg:x2; val_offset:16689*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16689*FLEN/8, x3, x1, x4) + +inst_5598: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfe00; +op3val:0x3ff; valaddr_reg:x2; val_offset:16692*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16692*FLEN/8, x3, x1, x4) + +inst_5599: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfe00; +op3val:0x83ff; valaddr_reg:x2; val_offset:16695*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16695*FLEN/8, x3, x1, x4) + +inst_5600: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfe00; +op3val:0x400; valaddr_reg:x2; val_offset:16698*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16698*FLEN/8, x3, x1, x4) + +inst_5601: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfe00; +op3val:0x8400; valaddr_reg:x2; val_offset:16701*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16701*FLEN/8, x3, x1, x4) + +inst_5602: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfe00; +op3val:0x401; valaddr_reg:x2; val_offset:16704*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16704*FLEN/8, x3, x1, x4) + +inst_5603: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfe00; +op3val:0x8455; valaddr_reg:x2; val_offset:16707*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16707*FLEN/8, x3, x1, x4) + +inst_5604: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfe00; +op3val:0x7bff; valaddr_reg:x2; val_offset:16710*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16710*FLEN/8, x3, x1, x4) + +inst_5605: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfe00; +op3val:0xfbff; valaddr_reg:x2; val_offset:16713*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16713*FLEN/8, x3, x1, x4) + +inst_5606: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfe00; +op3val:0x7c00; valaddr_reg:x2; val_offset:16716*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16716*FLEN/8, x3, x1, x4) + +inst_5607: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfe00; +op3val:0xfc00; valaddr_reg:x2; val_offset:16719*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16719*FLEN/8, x3, x1, x4) + +inst_5608: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfe00; +op3val:0x7e00; valaddr_reg:x2; val_offset:16722*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16722*FLEN/8, x3, x1, x4) + +inst_5609: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfe00; +op3val:0xfe00; valaddr_reg:x2; val_offset:16725*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16725*FLEN/8, x3, x1, x4) + +inst_5610: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfe00; +op3val:0x7e01; valaddr_reg:x2; val_offset:16728*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16728*FLEN/8, x3, x1, x4) + +inst_5611: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfe00; +op3val:0xfe55; valaddr_reg:x2; val_offset:16731*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16731*FLEN/8, x3, x1, x4) + +inst_5612: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfe00; +op3val:0x7c01; valaddr_reg:x2; val_offset:16734*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16734*FLEN/8, x3, x1, x4) + +inst_5613: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfe00; +op3val:0xfd55; valaddr_reg:x2; val_offset:16737*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16737*FLEN/8, x3, x1, x4) + +inst_5614: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfe00; +op3val:0x3c00; valaddr_reg:x2; val_offset:16740*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16740*FLEN/8, x3, x1, x4) + +inst_5615: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfe00; +op3val:0xbc00; valaddr_reg:x2; val_offset:16743*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16743*FLEN/8, x3, x1, x4) + +inst_5616: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7e01; +op3val:0x0; valaddr_reg:x2; val_offset:16746*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16746*FLEN/8, x3, x1, x4) + +inst_5617: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7e01; +op3val:0x8000; valaddr_reg:x2; val_offset:16749*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16749*FLEN/8, x3, x1, x4) + +inst_5618: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7e01; +op3val:0x1; valaddr_reg:x2; val_offset:16752*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16752*FLEN/8, x3, x1, x4) + +inst_5619: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7e01; +op3val:0x8001; valaddr_reg:x2; val_offset:16755*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16755*FLEN/8, x3, x1, x4) + +inst_5620: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7e01; +op3val:0x2; valaddr_reg:x2; val_offset:16758*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16758*FLEN/8, x3, x1, x4) + +inst_5621: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7e01; +op3val:0x83fe; valaddr_reg:x2; val_offset:16761*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16761*FLEN/8, x3, x1, x4) + +inst_5622: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7e01; +op3val:0x3ff; valaddr_reg:x2; val_offset:16764*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16764*FLEN/8, x3, x1, x4) + +inst_5623: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7e01; +op3val:0x83ff; valaddr_reg:x2; val_offset:16767*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16767*FLEN/8, x3, x1, x4) + +inst_5624: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7e01; +op3val:0x400; valaddr_reg:x2; val_offset:16770*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16770*FLEN/8, x3, x1, x4) + +inst_5625: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7e01; +op3val:0x8400; valaddr_reg:x2; val_offset:16773*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16773*FLEN/8, x3, x1, x4) + +inst_5626: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7e01; +op3val:0x401; valaddr_reg:x2; val_offset:16776*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16776*FLEN/8, x3, x1, x4) + +inst_5627: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7e01; +op3val:0x8455; valaddr_reg:x2; val_offset:16779*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16779*FLEN/8, x3, x1, x4) + +inst_5628: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7e01; +op3val:0x7bff; valaddr_reg:x2; val_offset:16782*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16782*FLEN/8, x3, x1, x4) + +inst_5629: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7e01; +op3val:0xfbff; valaddr_reg:x2; val_offset:16785*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16785*FLEN/8, x3, x1, x4) + +inst_5630: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7e01; +op3val:0x7c00; valaddr_reg:x2; val_offset:16788*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16788*FLEN/8, x3, x1, x4) + +inst_5631: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7e01; +op3val:0xfc00; valaddr_reg:x2; val_offset:16791*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16791*FLEN/8, x3, x1, x4) + +inst_5632: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7e01; +op3val:0x7e00; valaddr_reg:x2; val_offset:16794*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16794*FLEN/8, x3, x1, x4) + +inst_5633: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7e01; +op3val:0xfe00; valaddr_reg:x2; val_offset:16797*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16797*FLEN/8, x3, x1, x4) + +inst_5634: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7e01; +op3val:0x7e01; valaddr_reg:x2; val_offset:16800*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16800*FLEN/8, x3, x1, x4) + +inst_5635: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7e01; +op3val:0xfe55; valaddr_reg:x2; val_offset:16803*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16803*FLEN/8, x3, x1, x4) + +inst_5636: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7e01; +op3val:0x7c01; valaddr_reg:x2; val_offset:16806*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16806*FLEN/8, x3, x1, x4) + +inst_5637: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7e01; +op3val:0xfd55; valaddr_reg:x2; val_offset:16809*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16809*FLEN/8, x3, x1, x4) + +inst_5638: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7e01; +op3val:0x3c00; valaddr_reg:x2; val_offset:16812*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16812*FLEN/8, x3, x1, x4) + +inst_5639: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7e01; +op3val:0xbc00; valaddr_reg:x2; val_offset:16815*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16815*FLEN/8, x3, x1, x4) + +inst_5640: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfe55; +op3val:0x0; valaddr_reg:x2; val_offset:16818*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16818*FLEN/8, x3, x1, x4) + +inst_5641: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfe55; +op3val:0x8000; valaddr_reg:x2; val_offset:16821*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16821*FLEN/8, x3, x1, x4) + +inst_5642: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfe55; +op3val:0x1; valaddr_reg:x2; val_offset:16824*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16824*FLEN/8, x3, x1, x4) + +inst_5643: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfe55; +op3val:0x8001; valaddr_reg:x2; val_offset:16827*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16827*FLEN/8, x3, x1, x4) + +inst_5644: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfe55; +op3val:0x2; valaddr_reg:x2; val_offset:16830*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16830*FLEN/8, x3, x1, x4) + +inst_5645: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfe55; +op3val:0x83fe; valaddr_reg:x2; val_offset:16833*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16833*FLEN/8, x3, x1, x4) + +inst_5646: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfe55; +op3val:0x3ff; valaddr_reg:x2; val_offset:16836*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16836*FLEN/8, x3, x1, x4) + +inst_5647: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfe55; +op3val:0x83ff; valaddr_reg:x2; val_offset:16839*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16839*FLEN/8, x3, x1, x4) + +inst_5648: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfe55; +op3val:0x400; valaddr_reg:x2; val_offset:16842*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16842*FLEN/8, x3, x1, x4) + +inst_5649: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfe55; +op3val:0x8400; valaddr_reg:x2; val_offset:16845*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16845*FLEN/8, x3, x1, x4) + +inst_5650: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfe55; +op3val:0x401; valaddr_reg:x2; val_offset:16848*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16848*FLEN/8, x3, x1, x4) + +inst_5651: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfe55; +op3val:0x8455; valaddr_reg:x2; val_offset:16851*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16851*FLEN/8, x3, x1, x4) + +inst_5652: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfe55; +op3val:0x7bff; valaddr_reg:x2; val_offset:16854*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16854*FLEN/8, x3, x1, x4) + +inst_5653: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfe55; +op3val:0xfbff; valaddr_reg:x2; val_offset:16857*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16857*FLEN/8, x3, x1, x4) + +inst_5654: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfe55; +op3val:0x7c00; valaddr_reg:x2; val_offset:16860*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16860*FLEN/8, x3, x1, x4) + +inst_5655: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfe55; +op3val:0xfc00; valaddr_reg:x2; val_offset:16863*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16863*FLEN/8, x3, x1, x4) + +inst_5656: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfe55; +op3val:0x7e00; valaddr_reg:x2; val_offset:16866*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16866*FLEN/8, x3, x1, x4) + +inst_5657: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfe55; +op3val:0xfe00; valaddr_reg:x2; val_offset:16869*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16869*FLEN/8, x3, x1, x4) + +inst_5658: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfe55; +op3val:0x7e01; valaddr_reg:x2; val_offset:16872*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16872*FLEN/8, x3, x1, x4) + +inst_5659: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfe55; +op3val:0xfe55; valaddr_reg:x2; val_offset:16875*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16875*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_45) + +inst_5660: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfe55; +op3val:0x7c01; valaddr_reg:x2; val_offset:16878*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16878*FLEN/8, x3, x1, x4) + +inst_5661: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfe55; +op3val:0xfd55; valaddr_reg:x2; val_offset:16881*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16881*FLEN/8, x3, x1, x4) + +inst_5662: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfe55; +op3val:0x3c00; valaddr_reg:x2; val_offset:16884*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16884*FLEN/8, x3, x1, x4) + +inst_5663: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfe55; +op3val:0xbc00; valaddr_reg:x2; val_offset:16887*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16887*FLEN/8, x3, x1, x4) + +inst_5664: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7c01; +op3val:0x0; valaddr_reg:x2; val_offset:16890*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16890*FLEN/8, x3, x1, x4) + +inst_5665: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7c01; +op3val:0x8000; valaddr_reg:x2; val_offset:16893*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16893*FLEN/8, x3, x1, x4) + +inst_5666: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7c01; +op3val:0x1; valaddr_reg:x2; val_offset:16896*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16896*FLEN/8, x3, x1, x4) + +inst_5667: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7c01; +op3val:0x8001; valaddr_reg:x2; val_offset:16899*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16899*FLEN/8, x3, x1, x4) + +inst_5668: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7c01; +op3val:0x2; valaddr_reg:x2; val_offset:16902*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16902*FLEN/8, x3, x1, x4) + +inst_5669: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7c01; +op3val:0x83fe; valaddr_reg:x2; val_offset:16905*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16905*FLEN/8, x3, x1, x4) + +inst_5670: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7c01; +op3val:0x3ff; valaddr_reg:x2; val_offset:16908*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16908*FLEN/8, x3, x1, x4) + +inst_5671: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7c01; +op3val:0x83ff; valaddr_reg:x2; val_offset:16911*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16911*FLEN/8, x3, x1, x4) + +inst_5672: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7c01; +op3val:0x400; valaddr_reg:x2; val_offset:16914*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16914*FLEN/8, x3, x1, x4) + +inst_5673: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7c01; +op3val:0x8400; valaddr_reg:x2; val_offset:16917*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16917*FLEN/8, x3, x1, x4) + +inst_5674: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7c01; +op3val:0x401; valaddr_reg:x2; val_offset:16920*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16920*FLEN/8, x3, x1, x4) + +inst_5675: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7c01; +op3val:0x8455; valaddr_reg:x2; val_offset:16923*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16923*FLEN/8, x3, x1, x4) + +inst_5676: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7c01; +op3val:0x7bff; valaddr_reg:x2; val_offset:16926*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16926*FLEN/8, x3, x1, x4) + +inst_5677: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7c01; +op3val:0xfbff; valaddr_reg:x2; val_offset:16929*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16929*FLEN/8, x3, x1, x4) + +inst_5678: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7c01; +op3val:0x7c00; valaddr_reg:x2; val_offset:16932*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16932*FLEN/8, x3, x1, x4) + +inst_5679: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7c01; +op3val:0xfc00; valaddr_reg:x2; val_offset:16935*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16935*FLEN/8, x3, x1, x4) + +inst_5680: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7c01; +op3val:0x7e00; valaddr_reg:x2; val_offset:16938*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16938*FLEN/8, x3, x1, x4) + +inst_5681: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7c01; +op3val:0xfe00; valaddr_reg:x2; val_offset:16941*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16941*FLEN/8, x3, x1, x4) + +inst_5682: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7c01; +op3val:0x7e01; valaddr_reg:x2; val_offset:16944*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16944*FLEN/8, x3, x1, x4) + +inst_5683: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7c01; +op3val:0xfe55; valaddr_reg:x2; val_offset:16947*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16947*FLEN/8, x3, x1, x4) + +inst_5684: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7c01; +op3val:0x7c01; valaddr_reg:x2; val_offset:16950*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16950*FLEN/8, x3, x1, x4) + +inst_5685: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7c01; +op3val:0xfd55; valaddr_reg:x2; val_offset:16953*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16953*FLEN/8, x3, x1, x4) + +inst_5686: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7c01; +op3val:0x3c00; valaddr_reg:x2; val_offset:16956*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16956*FLEN/8, x3, x1, x4) + +inst_5687: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x7c01; +op3val:0xbc00; valaddr_reg:x2; val_offset:16959*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16959*FLEN/8, x3, x1, x4) + +inst_5688: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfd55; +op3val:0x0; valaddr_reg:x2; val_offset:16962*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16962*FLEN/8, x3, x1, x4) + +inst_5689: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfd55; +op3val:0x8000; valaddr_reg:x2; val_offset:16965*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16965*FLEN/8, x3, x1, x4) + +inst_5690: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfd55; +op3val:0x1; valaddr_reg:x2; val_offset:16968*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16968*FLEN/8, x3, x1, x4) + +inst_5691: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfd55; +op3val:0x8001; valaddr_reg:x2; val_offset:16971*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16971*FLEN/8, x3, x1, x4) + +inst_5692: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfd55; +op3val:0x2; valaddr_reg:x2; val_offset:16974*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16974*FLEN/8, x3, x1, x4) + +inst_5693: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfd55; +op3val:0x83fe; valaddr_reg:x2; val_offset:16977*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16977*FLEN/8, x3, x1, x4) + +inst_5694: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfd55; +op3val:0x3ff; valaddr_reg:x2; val_offset:16980*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16980*FLEN/8, x3, x1, x4) + +inst_5695: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfd55; +op3val:0x83ff; valaddr_reg:x2; val_offset:16983*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16983*FLEN/8, x3, x1, x4) + +inst_5696: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfd55; +op3val:0x400; valaddr_reg:x2; val_offset:16986*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16986*FLEN/8, x3, x1, x4) + +inst_5697: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfd55; +op3val:0x8400; valaddr_reg:x2; val_offset:16989*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16989*FLEN/8, x3, x1, x4) + +inst_5698: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfd55; +op3val:0x401; valaddr_reg:x2; val_offset:16992*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16992*FLEN/8, x3, x1, x4) + +inst_5699: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfd55; +op3val:0x8455; valaddr_reg:x2; val_offset:16995*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16995*FLEN/8, x3, x1, x4) + +inst_5700: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfd55; +op3val:0x7bff; valaddr_reg:x2; val_offset:16998*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 16998*FLEN/8, x3, x1, x4) + +inst_5701: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfd55; +op3val:0xfbff; valaddr_reg:x2; val_offset:17001*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17001*FLEN/8, x3, x1, x4) + +inst_5702: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfd55; +op3val:0x7c00; valaddr_reg:x2; val_offset:17004*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17004*FLEN/8, x3, x1, x4) + +inst_5703: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfd55; +op3val:0xfc00; valaddr_reg:x2; val_offset:17007*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17007*FLEN/8, x3, x1, x4) + +inst_5704: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfd55; +op3val:0x7e00; valaddr_reg:x2; val_offset:17010*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17010*FLEN/8, x3, x1, x4) + +inst_5705: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfd55; +op3val:0xfe00; valaddr_reg:x2; val_offset:17013*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17013*FLEN/8, x3, x1, x4) + +inst_5706: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfd55; +op3val:0x7e01; valaddr_reg:x2; val_offset:17016*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17016*FLEN/8, x3, x1, x4) + +inst_5707: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfd55; +op3val:0xfe55; valaddr_reg:x2; val_offset:17019*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17019*FLEN/8, x3, x1, x4) + +inst_5708: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfd55; +op3val:0x7c01; valaddr_reg:x2; val_offset:17022*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17022*FLEN/8, x3, x1, x4) + +inst_5709: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfd55; +op3val:0xfd55; valaddr_reg:x2; val_offset:17025*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17025*FLEN/8, x3, x1, x4) + +inst_5710: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfd55; +op3val:0x3c00; valaddr_reg:x2; val_offset:17028*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17028*FLEN/8, x3, x1, x4) + +inst_5711: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xfd55; +op3val:0xbc00; valaddr_reg:x2; val_offset:17031*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17031*FLEN/8, x3, x1, x4) + +inst_5712: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x3c00; +op3val:0x0; valaddr_reg:x2; val_offset:17034*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17034*FLEN/8, x3, x1, x4) + +inst_5713: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x3c00; +op3val:0x8000; valaddr_reg:x2; val_offset:17037*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17037*FLEN/8, x3, x1, x4) + +inst_5714: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x3c00; +op3val:0x1; valaddr_reg:x2; val_offset:17040*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17040*FLEN/8, x3, x1, x4) + +inst_5715: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x3c00; +op3val:0x8001; valaddr_reg:x2; val_offset:17043*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17043*FLEN/8, x3, x1, x4) + +inst_5716: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x3c00; +op3val:0x2; valaddr_reg:x2; val_offset:17046*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17046*FLEN/8, x3, x1, x4) + +inst_5717: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x3c00; +op3val:0x83fe; valaddr_reg:x2; val_offset:17049*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17049*FLEN/8, x3, x1, x4) + +inst_5718: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x3c00; +op3val:0x3ff; valaddr_reg:x2; val_offset:17052*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17052*FLEN/8, x3, x1, x4) + +inst_5719: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x3c00; +op3val:0x83ff; valaddr_reg:x2; val_offset:17055*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17055*FLEN/8, x3, x1, x4) + +inst_5720: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x3c00; +op3val:0x400; valaddr_reg:x2; val_offset:17058*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17058*FLEN/8, x3, x1, x4) + +inst_5721: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x3c00; +op3val:0x8400; valaddr_reg:x2; val_offset:17061*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17061*FLEN/8, x3, x1, x4) + +inst_5722: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x3c00; +op3val:0x401; valaddr_reg:x2; val_offset:17064*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17064*FLEN/8, x3, x1, x4) + +inst_5723: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x3c00; +op3val:0x8455; valaddr_reg:x2; val_offset:17067*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17067*FLEN/8, x3, x1, x4) + +inst_5724: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x3c00; +op3val:0x7bff; valaddr_reg:x2; val_offset:17070*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17070*FLEN/8, x3, x1, x4) + +inst_5725: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x3c00; +op3val:0xfbff; valaddr_reg:x2; val_offset:17073*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17073*FLEN/8, x3, x1, x4) + +inst_5726: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x3c00; +op3val:0x7c00; valaddr_reg:x2; val_offset:17076*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17076*FLEN/8, x3, x1, x4) + +inst_5727: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x3c00; +op3val:0xfc00; valaddr_reg:x2; val_offset:17079*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17079*FLEN/8, x3, x1, x4) + +inst_5728: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x3c00; +op3val:0x7e00; valaddr_reg:x2; val_offset:17082*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17082*FLEN/8, x3, x1, x4) + +inst_5729: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x3c00; +op3val:0xfe00; valaddr_reg:x2; val_offset:17085*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17085*FLEN/8, x3, x1, x4) + +inst_5730: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x3c00; +op3val:0x7e01; valaddr_reg:x2; val_offset:17088*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17088*FLEN/8, x3, x1, x4) + +inst_5731: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x3c00; +op3val:0xfe55; valaddr_reg:x2; val_offset:17091*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17091*FLEN/8, x3, x1, x4) + +inst_5732: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x3c00; +op3val:0x7c01; valaddr_reg:x2; val_offset:17094*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17094*FLEN/8, x3, x1, x4) + +inst_5733: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x3c00; +op3val:0xfd55; valaddr_reg:x2; val_offset:17097*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17097*FLEN/8, x3, x1, x4) + +inst_5734: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x3c00; +op3val:0x3c00; valaddr_reg:x2; val_offset:17100*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17100*FLEN/8, x3, x1, x4) + +inst_5735: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0x3c00; +op3val:0xbc00; valaddr_reg:x2; val_offset:17103*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17103*FLEN/8, x3, x1, x4) + +inst_5736: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xbc00; +op3val:0x0; valaddr_reg:x2; val_offset:17106*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17106*FLEN/8, x3, x1, x4) + +inst_5737: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xbc00; +op3val:0x8000; valaddr_reg:x2; val_offset:17109*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17109*FLEN/8, x3, x1, x4) + +inst_5738: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xbc00; +op3val:0x1; valaddr_reg:x2; val_offset:17112*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17112*FLEN/8, x3, x1, x4) + +inst_5739: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xbc00; +op3val:0x8001; valaddr_reg:x2; val_offset:17115*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17115*FLEN/8, x3, x1, x4) + +inst_5740: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xbc00; +op3val:0x2; valaddr_reg:x2; val_offset:17118*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17118*FLEN/8, x3, x1, x4) + +inst_5741: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xbc00; +op3val:0x83fe; valaddr_reg:x2; val_offset:17121*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17121*FLEN/8, x3, x1, x4) + +inst_5742: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xbc00; +op3val:0x3ff; valaddr_reg:x2; val_offset:17124*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17124*FLEN/8, x3, x1, x4) + +inst_5743: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xbc00; +op3val:0x83ff; valaddr_reg:x2; val_offset:17127*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17127*FLEN/8, x3, x1, x4) + +inst_5744: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xbc00; +op3val:0x400; valaddr_reg:x2; val_offset:17130*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17130*FLEN/8, x3, x1, x4) + +inst_5745: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xbc00; +op3val:0x8400; valaddr_reg:x2; val_offset:17133*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17133*FLEN/8, x3, x1, x4) + +inst_5746: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xbc00; +op3val:0x401; valaddr_reg:x2; val_offset:17136*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17136*FLEN/8, x3, x1, x4) + +inst_5747: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xbc00; +op3val:0x8455; valaddr_reg:x2; val_offset:17139*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17139*FLEN/8, x3, x1, x4) + +inst_5748: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xbc00; +op3val:0x7bff; valaddr_reg:x2; val_offset:17142*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17142*FLEN/8, x3, x1, x4) + +inst_5749: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xbc00; +op3val:0xfbff; valaddr_reg:x2; val_offset:17145*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17145*FLEN/8, x3, x1, x4) + +inst_5750: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xbc00; +op3val:0x7c00; valaddr_reg:x2; val_offset:17148*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17148*FLEN/8, x3, x1, x4) + +inst_5751: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xbc00; +op3val:0xfc00; valaddr_reg:x2; val_offset:17151*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17151*FLEN/8, x3, x1, x4) + +inst_5752: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xbc00; +op3val:0x7e00; valaddr_reg:x2; val_offset:17154*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17154*FLEN/8, x3, x1, x4) + +inst_5753: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xbc00; +op3val:0xfe00; valaddr_reg:x2; val_offset:17157*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17157*FLEN/8, x3, x1, x4) + +inst_5754: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xbc00; +op3val:0x7e01; valaddr_reg:x2; val_offset:17160*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17160*FLEN/8, x3, x1, x4) + +inst_5755: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xbc00; +op3val:0xfe55; valaddr_reg:x2; val_offset:17163*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17163*FLEN/8, x3, x1, x4) + +inst_5756: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xbc00; +op3val:0x7c01; valaddr_reg:x2; val_offset:17166*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17166*FLEN/8, x3, x1, x4) + +inst_5757: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xbc00; +op3val:0xfd55; valaddr_reg:x2; val_offset:17169*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17169*FLEN/8, x3, x1, x4) + +inst_5758: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xbc00; +op3val:0x3c00; valaddr_reg:x2; val_offset:17172*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17172*FLEN/8, x3, x1, x4) + +inst_5759: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8400; op2val:0xbc00; +op3val:0xbc00; valaddr_reg:x2; val_offset:17175*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17175*FLEN/8, x3, x1, x4) + +inst_5760: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x0; +op3val:0x0; valaddr_reg:x2; val_offset:17178*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17178*FLEN/8, x3, x1, x4) + +inst_5761: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x0; +op3val:0x8000; valaddr_reg:x2; val_offset:17181*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17181*FLEN/8, x3, x1, x4) + +inst_5762: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x0; +op3val:0x1; valaddr_reg:x2; val_offset:17184*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17184*FLEN/8, x3, x1, x4) + +inst_5763: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x0; +op3val:0x8001; valaddr_reg:x2; val_offset:17187*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17187*FLEN/8, x3, x1, x4) + +inst_5764: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x0; +op3val:0x2; valaddr_reg:x2; val_offset:17190*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17190*FLEN/8, x3, x1, x4) + +inst_5765: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x0; +op3val:0x83fe; valaddr_reg:x2; val_offset:17193*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17193*FLEN/8, x3, x1, x4) + +inst_5766: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x0; +op3val:0x3ff; valaddr_reg:x2; val_offset:17196*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17196*FLEN/8, x3, x1, x4) + +inst_5767: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x0; +op3val:0x83ff; valaddr_reg:x2; val_offset:17199*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17199*FLEN/8, x3, x1, x4) + +inst_5768: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x0; +op3val:0x400; valaddr_reg:x2; val_offset:17202*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17202*FLEN/8, x3, x1, x4) + +inst_5769: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x0; +op3val:0x8400; valaddr_reg:x2; val_offset:17205*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17205*FLEN/8, x3, x1, x4) + +inst_5770: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x0; +op3val:0x401; valaddr_reg:x2; val_offset:17208*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17208*FLEN/8, x3, x1, x4) + +inst_5771: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x0; +op3val:0x8455; valaddr_reg:x2; val_offset:17211*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17211*FLEN/8, x3, x1, x4) + +inst_5772: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x0; +op3val:0x7bff; valaddr_reg:x2; val_offset:17214*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17214*FLEN/8, x3, x1, x4) + +inst_5773: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x0; +op3val:0xfbff; valaddr_reg:x2; val_offset:17217*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17217*FLEN/8, x3, x1, x4) + +inst_5774: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x0; +op3val:0x7c00; valaddr_reg:x2; val_offset:17220*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17220*FLEN/8, x3, x1, x4) + +inst_5775: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x0; +op3val:0xfc00; valaddr_reg:x2; val_offset:17223*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17223*FLEN/8, x3, x1, x4) + +inst_5776: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x0; +op3val:0x7e00; valaddr_reg:x2; val_offset:17226*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17226*FLEN/8, x3, x1, x4) + +inst_5777: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x0; +op3val:0xfe00; valaddr_reg:x2; val_offset:17229*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17229*FLEN/8, x3, x1, x4) + +inst_5778: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x0; +op3val:0x7e01; valaddr_reg:x2; val_offset:17232*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17232*FLEN/8, x3, x1, x4) + +inst_5779: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x0; +op3val:0xfe55; valaddr_reg:x2; val_offset:17235*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17235*FLEN/8, x3, x1, x4) + +inst_5780: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x0; +op3val:0x7c01; valaddr_reg:x2; val_offset:17238*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17238*FLEN/8, x3, x1, x4) + +inst_5781: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x0; +op3val:0xfd55; valaddr_reg:x2; val_offset:17241*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17241*FLEN/8, x3, x1, x4) + +inst_5782: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x0; +op3val:0x3c00; valaddr_reg:x2; val_offset:17244*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17244*FLEN/8, x3, x1, x4) + +inst_5783: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x0; +op3val:0xbc00; valaddr_reg:x2; val_offset:17247*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17247*FLEN/8, x3, x1, x4) + +inst_5784: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8000; +op3val:0x0; valaddr_reg:x2; val_offset:17250*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17250*FLEN/8, x3, x1, x4) + +inst_5785: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8000; +op3val:0x8000; valaddr_reg:x2; val_offset:17253*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17253*FLEN/8, x3, x1, x4) + +inst_5786: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8000; +op3val:0x1; valaddr_reg:x2; val_offset:17256*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17256*FLEN/8, x3, x1, x4) + +inst_5787: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8000; +op3val:0x8001; valaddr_reg:x2; val_offset:17259*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17259*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_46) + +inst_5788: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8000; +op3val:0x2; valaddr_reg:x2; val_offset:17262*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17262*FLEN/8, x3, x1, x4) + +inst_5789: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8000; +op3val:0x83fe; valaddr_reg:x2; val_offset:17265*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17265*FLEN/8, x3, x1, x4) + +inst_5790: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8000; +op3val:0x3ff; valaddr_reg:x2; val_offset:17268*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17268*FLEN/8, x3, x1, x4) + +inst_5791: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8000; +op3val:0x83ff; valaddr_reg:x2; val_offset:17271*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17271*FLEN/8, x3, x1, x4) + +inst_5792: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8000; +op3val:0x400; valaddr_reg:x2; val_offset:17274*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17274*FLEN/8, x3, x1, x4) + +inst_5793: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8000; +op3val:0x8400; valaddr_reg:x2; val_offset:17277*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17277*FLEN/8, x3, x1, x4) + +inst_5794: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8000; +op3val:0x401; valaddr_reg:x2; val_offset:17280*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17280*FLEN/8, x3, x1, x4) + +inst_5795: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8000; +op3val:0x8455; valaddr_reg:x2; val_offset:17283*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17283*FLEN/8, x3, x1, x4) + +inst_5796: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x2; val_offset:17286*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17286*FLEN/8, x3, x1, x4) + +inst_5797: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x2; val_offset:17289*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17289*FLEN/8, x3, x1, x4) + +inst_5798: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8000; +op3val:0x7c00; valaddr_reg:x2; val_offset:17292*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17292*FLEN/8, x3, x1, x4) + +inst_5799: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8000; +op3val:0xfc00; valaddr_reg:x2; val_offset:17295*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17295*FLEN/8, x3, x1, x4) + +inst_5800: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8000; +op3val:0x7e00; valaddr_reg:x2; val_offset:17298*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17298*FLEN/8, x3, x1, x4) + +inst_5801: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8000; +op3val:0xfe00; valaddr_reg:x2; val_offset:17301*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17301*FLEN/8, x3, x1, x4) + +inst_5802: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8000; +op3val:0x7e01; valaddr_reg:x2; val_offset:17304*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17304*FLEN/8, x3, x1, x4) + +inst_5803: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8000; +op3val:0xfe55; valaddr_reg:x2; val_offset:17307*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17307*FLEN/8, x3, x1, x4) + +inst_5804: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8000; +op3val:0x7c01; valaddr_reg:x2; val_offset:17310*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17310*FLEN/8, x3, x1, x4) + +inst_5805: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8000; +op3val:0xfd55; valaddr_reg:x2; val_offset:17313*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17313*FLEN/8, x3, x1, x4) + +inst_5806: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8000; +op3val:0x3c00; valaddr_reg:x2; val_offset:17316*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17316*FLEN/8, x3, x1, x4) + +inst_5807: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8000; +op3val:0xbc00; valaddr_reg:x2; val_offset:17319*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17319*FLEN/8, x3, x1, x4) + +inst_5808: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x1; +op3val:0x0; valaddr_reg:x2; val_offset:17322*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17322*FLEN/8, x3, x1, x4) + +inst_5809: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x1; +op3val:0x8000; valaddr_reg:x2; val_offset:17325*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17325*FLEN/8, x3, x1, x4) + +inst_5810: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x1; +op3val:0x1; valaddr_reg:x2; val_offset:17328*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17328*FLEN/8, x3, x1, x4) + +inst_5811: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x1; +op3val:0x8001; valaddr_reg:x2; val_offset:17331*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17331*FLEN/8, x3, x1, x4) + +inst_5812: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x1; +op3val:0x2; valaddr_reg:x2; val_offset:17334*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17334*FLEN/8, x3, x1, x4) + +inst_5813: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x1; +op3val:0x83fe; valaddr_reg:x2; val_offset:17337*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17337*FLEN/8, x3, x1, x4) + +inst_5814: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x1; +op3val:0x3ff; valaddr_reg:x2; val_offset:17340*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17340*FLEN/8, x3, x1, x4) + +inst_5815: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x1; +op3val:0x83ff; valaddr_reg:x2; val_offset:17343*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17343*FLEN/8, x3, x1, x4) + +inst_5816: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x1; +op3val:0x400; valaddr_reg:x2; val_offset:17346*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17346*FLEN/8, x3, x1, x4) + +inst_5817: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x1; +op3val:0x8400; valaddr_reg:x2; val_offset:17349*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17349*FLEN/8, x3, x1, x4) + +inst_5818: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x1; +op3val:0x401; valaddr_reg:x2; val_offset:17352*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17352*FLEN/8, x3, x1, x4) + +inst_5819: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x1; +op3val:0x8455; valaddr_reg:x2; val_offset:17355*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17355*FLEN/8, x3, x1, x4) + +inst_5820: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x1; +op3val:0x7bff; valaddr_reg:x2; val_offset:17358*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17358*FLEN/8, x3, x1, x4) + +inst_5821: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x1; +op3val:0xfbff; valaddr_reg:x2; val_offset:17361*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17361*FLEN/8, x3, x1, x4) + +inst_5822: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x1; +op3val:0x7c00; valaddr_reg:x2; val_offset:17364*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17364*FLEN/8, x3, x1, x4) + +inst_5823: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x1; +op3val:0xfc00; valaddr_reg:x2; val_offset:17367*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17367*FLEN/8, x3, x1, x4) + +inst_5824: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x1; +op3val:0x7e00; valaddr_reg:x2; val_offset:17370*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17370*FLEN/8, x3, x1, x4) + +inst_5825: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x1; +op3val:0xfe00; valaddr_reg:x2; val_offset:17373*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17373*FLEN/8, x3, x1, x4) + +inst_5826: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x1; +op3val:0x7e01; valaddr_reg:x2; val_offset:17376*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17376*FLEN/8, x3, x1, x4) + +inst_5827: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x1; +op3val:0xfe55; valaddr_reg:x2; val_offset:17379*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17379*FLEN/8, x3, x1, x4) + +inst_5828: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x1; +op3val:0x7c01; valaddr_reg:x2; val_offset:17382*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17382*FLEN/8, x3, x1, x4) + +inst_5829: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x1; +op3val:0xfd55; valaddr_reg:x2; val_offset:17385*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17385*FLEN/8, x3, x1, x4) + +inst_5830: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x1; +op3val:0x3c00; valaddr_reg:x2; val_offset:17388*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17388*FLEN/8, x3, x1, x4) + +inst_5831: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x1; +op3val:0xbc00; valaddr_reg:x2; val_offset:17391*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17391*FLEN/8, x3, x1, x4) + +inst_5832: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8001; +op3val:0x0; valaddr_reg:x2; val_offset:17394*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17394*FLEN/8, x3, x1, x4) + +inst_5833: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8001; +op3val:0x8000; valaddr_reg:x2; val_offset:17397*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17397*FLEN/8, x3, x1, x4) + +inst_5834: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8001; +op3val:0x1; valaddr_reg:x2; val_offset:17400*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17400*FLEN/8, x3, x1, x4) + +inst_5835: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8001; +op3val:0x8001; valaddr_reg:x2; val_offset:17403*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17403*FLEN/8, x3, x1, x4) + +inst_5836: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8001; +op3val:0x2; valaddr_reg:x2; val_offset:17406*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17406*FLEN/8, x3, x1, x4) + +inst_5837: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8001; +op3val:0x83fe; valaddr_reg:x2; val_offset:17409*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17409*FLEN/8, x3, x1, x4) + +inst_5838: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8001; +op3val:0x3ff; valaddr_reg:x2; val_offset:17412*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17412*FLEN/8, x3, x1, x4) + +inst_5839: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8001; +op3val:0x83ff; valaddr_reg:x2; val_offset:17415*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17415*FLEN/8, x3, x1, x4) + +inst_5840: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8001; +op3val:0x400; valaddr_reg:x2; val_offset:17418*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17418*FLEN/8, x3, x1, x4) + +inst_5841: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8001; +op3val:0x8400; valaddr_reg:x2; val_offset:17421*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17421*FLEN/8, x3, x1, x4) + +inst_5842: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8001; +op3val:0x401; valaddr_reg:x2; val_offset:17424*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17424*FLEN/8, x3, x1, x4) + +inst_5843: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8001; +op3val:0x8455; valaddr_reg:x2; val_offset:17427*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17427*FLEN/8, x3, x1, x4) + +inst_5844: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8001; +op3val:0x7bff; valaddr_reg:x2; val_offset:17430*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17430*FLEN/8, x3, x1, x4) + +inst_5845: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8001; +op3val:0xfbff; valaddr_reg:x2; val_offset:17433*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17433*FLEN/8, x3, x1, x4) + +inst_5846: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8001; +op3val:0x7c00; valaddr_reg:x2; val_offset:17436*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17436*FLEN/8, x3, x1, x4) + +inst_5847: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8001; +op3val:0xfc00; valaddr_reg:x2; val_offset:17439*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17439*FLEN/8, x3, x1, x4) + +inst_5848: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8001; +op3val:0x7e00; valaddr_reg:x2; val_offset:17442*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17442*FLEN/8, x3, x1, x4) + +inst_5849: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8001; +op3val:0xfe00; valaddr_reg:x2; val_offset:17445*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17445*FLEN/8, x3, x1, x4) + +inst_5850: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8001; +op3val:0x7e01; valaddr_reg:x2; val_offset:17448*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17448*FLEN/8, x3, x1, x4) + +inst_5851: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8001; +op3val:0xfe55; valaddr_reg:x2; val_offset:17451*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17451*FLEN/8, x3, x1, x4) + +inst_5852: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8001; +op3val:0x7c01; valaddr_reg:x2; val_offset:17454*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17454*FLEN/8, x3, x1, x4) + +inst_5853: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8001; +op3val:0xfd55; valaddr_reg:x2; val_offset:17457*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17457*FLEN/8, x3, x1, x4) + +inst_5854: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8001; +op3val:0x3c00; valaddr_reg:x2; val_offset:17460*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17460*FLEN/8, x3, x1, x4) + +inst_5855: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8001; +op3val:0xbc00; valaddr_reg:x2; val_offset:17463*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17463*FLEN/8, x3, x1, x4) + +inst_5856: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x2; +op3val:0x0; valaddr_reg:x2; val_offset:17466*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17466*FLEN/8, x3, x1, x4) + +inst_5857: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x2; +op3val:0x8000; valaddr_reg:x2; val_offset:17469*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17469*FLEN/8, x3, x1, x4) + +inst_5858: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x2; +op3val:0x1; valaddr_reg:x2; val_offset:17472*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17472*FLEN/8, x3, x1, x4) + +inst_5859: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x2; +op3val:0x8001; valaddr_reg:x2; val_offset:17475*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17475*FLEN/8, x3, x1, x4) + +inst_5860: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x2; +op3val:0x2; valaddr_reg:x2; val_offset:17478*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17478*FLEN/8, x3, x1, x4) + +inst_5861: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x2; +op3val:0x83fe; valaddr_reg:x2; val_offset:17481*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17481*FLEN/8, x3, x1, x4) + +inst_5862: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x2; +op3val:0x3ff; valaddr_reg:x2; val_offset:17484*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17484*FLEN/8, x3, x1, x4) + +inst_5863: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x2; +op3val:0x83ff; valaddr_reg:x2; val_offset:17487*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17487*FLEN/8, x3, x1, x4) + +inst_5864: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x2; +op3val:0x400; valaddr_reg:x2; val_offset:17490*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17490*FLEN/8, x3, x1, x4) + +inst_5865: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x2; +op3val:0x8400; valaddr_reg:x2; val_offset:17493*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17493*FLEN/8, x3, x1, x4) + +inst_5866: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x2; +op3val:0x401; valaddr_reg:x2; val_offset:17496*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17496*FLEN/8, x3, x1, x4) + +inst_5867: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x2; +op3val:0x8455; valaddr_reg:x2; val_offset:17499*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17499*FLEN/8, x3, x1, x4) + +inst_5868: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x2; +op3val:0x7bff; valaddr_reg:x2; val_offset:17502*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17502*FLEN/8, x3, x1, x4) + +inst_5869: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x2; +op3val:0xfbff; valaddr_reg:x2; val_offset:17505*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17505*FLEN/8, x3, x1, x4) + +inst_5870: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x2; +op3val:0x7c00; valaddr_reg:x2; val_offset:17508*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17508*FLEN/8, x3, x1, x4) + +inst_5871: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x2; +op3val:0xfc00; valaddr_reg:x2; val_offset:17511*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17511*FLEN/8, x3, x1, x4) + +inst_5872: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x2; +op3val:0x7e00; valaddr_reg:x2; val_offset:17514*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17514*FLEN/8, x3, x1, x4) + +inst_5873: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x2; +op3val:0xfe00; valaddr_reg:x2; val_offset:17517*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17517*FLEN/8, x3, x1, x4) + +inst_5874: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x2; +op3val:0x7e01; valaddr_reg:x2; val_offset:17520*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17520*FLEN/8, x3, x1, x4) + +inst_5875: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x2; +op3val:0xfe55; valaddr_reg:x2; val_offset:17523*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17523*FLEN/8, x3, x1, x4) + +inst_5876: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x2; +op3val:0x7c01; valaddr_reg:x2; val_offset:17526*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17526*FLEN/8, x3, x1, x4) + +inst_5877: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x2; +op3val:0xfd55; valaddr_reg:x2; val_offset:17529*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17529*FLEN/8, x3, x1, x4) + +inst_5878: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x2; +op3val:0x3c00; valaddr_reg:x2; val_offset:17532*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17532*FLEN/8, x3, x1, x4) + +inst_5879: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x2; +op3val:0xbc00; valaddr_reg:x2; val_offset:17535*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17535*FLEN/8, x3, x1, x4) + +inst_5880: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x83fe; +op3val:0x0; valaddr_reg:x2; val_offset:17538*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17538*FLEN/8, x3, x1, x4) + +inst_5881: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x83fe; +op3val:0x8000; valaddr_reg:x2; val_offset:17541*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17541*FLEN/8, x3, x1, x4) + +inst_5882: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x83fe; +op3val:0x1; valaddr_reg:x2; val_offset:17544*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17544*FLEN/8, x3, x1, x4) + +inst_5883: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x83fe; +op3val:0x8001; valaddr_reg:x2; val_offset:17547*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17547*FLEN/8, x3, x1, x4) + +inst_5884: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x83fe; +op3val:0x2; valaddr_reg:x2; val_offset:17550*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17550*FLEN/8, x3, x1, x4) + +inst_5885: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x83fe; +op3val:0x83fe; valaddr_reg:x2; val_offset:17553*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17553*FLEN/8, x3, x1, x4) + +inst_5886: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x83fe; +op3val:0x3ff; valaddr_reg:x2; val_offset:17556*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17556*FLEN/8, x3, x1, x4) + +inst_5887: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x83fe; +op3val:0x83ff; valaddr_reg:x2; val_offset:17559*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17559*FLEN/8, x3, x1, x4) + +inst_5888: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x83fe; +op3val:0x400; valaddr_reg:x2; val_offset:17562*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17562*FLEN/8, x3, x1, x4) + +inst_5889: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x83fe; +op3val:0x8400; valaddr_reg:x2; val_offset:17565*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17565*FLEN/8, x3, x1, x4) + +inst_5890: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x83fe; +op3val:0x401; valaddr_reg:x2; val_offset:17568*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17568*FLEN/8, x3, x1, x4) + +inst_5891: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x83fe; +op3val:0x8455; valaddr_reg:x2; val_offset:17571*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17571*FLEN/8, x3, x1, x4) + +inst_5892: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x83fe; +op3val:0x7bff; valaddr_reg:x2; val_offset:17574*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17574*FLEN/8, x3, x1, x4) + +inst_5893: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x83fe; +op3val:0xfbff; valaddr_reg:x2; val_offset:17577*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17577*FLEN/8, x3, x1, x4) + +inst_5894: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x83fe; +op3val:0x7c00; valaddr_reg:x2; val_offset:17580*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17580*FLEN/8, x3, x1, x4) + +inst_5895: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x83fe; +op3val:0xfc00; valaddr_reg:x2; val_offset:17583*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17583*FLEN/8, x3, x1, x4) + +inst_5896: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x83fe; +op3val:0x7e00; valaddr_reg:x2; val_offset:17586*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17586*FLEN/8, x3, x1, x4) + +inst_5897: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x83fe; +op3val:0xfe00; valaddr_reg:x2; val_offset:17589*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17589*FLEN/8, x3, x1, x4) + +inst_5898: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x83fe; +op3val:0x7e01; valaddr_reg:x2; val_offset:17592*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17592*FLEN/8, x3, x1, x4) + +inst_5899: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x83fe; +op3val:0xfe55; valaddr_reg:x2; val_offset:17595*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17595*FLEN/8, x3, x1, x4) + +inst_5900: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x83fe; +op3val:0x7c01; valaddr_reg:x2; val_offset:17598*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17598*FLEN/8, x3, x1, x4) + +inst_5901: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x83fe; +op3val:0xfd55; valaddr_reg:x2; val_offset:17601*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17601*FLEN/8, x3, x1, x4) + +inst_5902: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x83fe; +op3val:0x3c00; valaddr_reg:x2; val_offset:17604*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17604*FLEN/8, x3, x1, x4) + +inst_5903: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x83fe; +op3val:0xbc00; valaddr_reg:x2; val_offset:17607*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17607*FLEN/8, x3, x1, x4) + +inst_5904: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x3ff; +op3val:0x0; valaddr_reg:x2; val_offset:17610*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17610*FLEN/8, x3, x1, x4) + +inst_5905: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x3ff; +op3val:0x8000; valaddr_reg:x2; val_offset:17613*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17613*FLEN/8, x3, x1, x4) + +inst_5906: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x3ff; +op3val:0x1; valaddr_reg:x2; val_offset:17616*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17616*FLEN/8, x3, x1, x4) + +inst_5907: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x3ff; +op3val:0x8001; valaddr_reg:x2; val_offset:17619*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17619*FLEN/8, x3, x1, x4) + +inst_5908: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x3ff; +op3val:0x2; valaddr_reg:x2; val_offset:17622*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17622*FLEN/8, x3, x1, x4) + +inst_5909: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x3ff; +op3val:0x83fe; valaddr_reg:x2; val_offset:17625*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17625*FLEN/8, x3, x1, x4) + +inst_5910: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x3ff; +op3val:0x3ff; valaddr_reg:x2; val_offset:17628*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17628*FLEN/8, x3, x1, x4) + +inst_5911: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x3ff; +op3val:0x83ff; valaddr_reg:x2; val_offset:17631*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17631*FLEN/8, x3, x1, x4) + +inst_5912: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x3ff; +op3val:0x400; valaddr_reg:x2; val_offset:17634*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17634*FLEN/8, x3, x1, x4) + +inst_5913: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x3ff; +op3val:0x8400; valaddr_reg:x2; val_offset:17637*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17637*FLEN/8, x3, x1, x4) + +inst_5914: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x3ff; +op3val:0x401; valaddr_reg:x2; val_offset:17640*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17640*FLEN/8, x3, x1, x4) + +inst_5915: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x3ff; +op3val:0x8455; valaddr_reg:x2; val_offset:17643*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17643*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_47) + +inst_5916: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x3ff; +op3val:0x7bff; valaddr_reg:x2; val_offset:17646*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17646*FLEN/8, x3, x1, x4) + +inst_5917: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x3ff; +op3val:0xfbff; valaddr_reg:x2; val_offset:17649*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17649*FLEN/8, x3, x1, x4) + +inst_5918: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x3ff; +op3val:0x7c00; valaddr_reg:x2; val_offset:17652*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17652*FLEN/8, x3, x1, x4) + +inst_5919: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x3ff; +op3val:0xfc00; valaddr_reg:x2; val_offset:17655*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17655*FLEN/8, x3, x1, x4) + +inst_5920: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x3ff; +op3val:0x7e00; valaddr_reg:x2; val_offset:17658*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17658*FLEN/8, x3, x1, x4) + +inst_5921: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x3ff; +op3val:0xfe00; valaddr_reg:x2; val_offset:17661*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17661*FLEN/8, x3, x1, x4) + +inst_5922: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x3ff; +op3val:0x7e01; valaddr_reg:x2; val_offset:17664*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17664*FLEN/8, x3, x1, x4) + +inst_5923: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x3ff; +op3val:0xfe55; valaddr_reg:x2; val_offset:17667*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17667*FLEN/8, x3, x1, x4) + +inst_5924: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x3ff; +op3val:0x7c01; valaddr_reg:x2; val_offset:17670*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17670*FLEN/8, x3, x1, x4) + +inst_5925: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x3ff; +op3val:0xfd55; valaddr_reg:x2; val_offset:17673*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17673*FLEN/8, x3, x1, x4) + +inst_5926: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x3ff; +op3val:0x3c00; valaddr_reg:x2; val_offset:17676*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17676*FLEN/8, x3, x1, x4) + +inst_5927: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x3ff; +op3val:0xbc00; valaddr_reg:x2; val_offset:17679*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17679*FLEN/8, x3, x1, x4) + +inst_5928: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x83ff; +op3val:0x0; valaddr_reg:x2; val_offset:17682*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17682*FLEN/8, x3, x1, x4) + +inst_5929: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x83ff; +op3val:0x8000; valaddr_reg:x2; val_offset:17685*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17685*FLEN/8, x3, x1, x4) + +inst_5930: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x83ff; +op3val:0x1; valaddr_reg:x2; val_offset:17688*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17688*FLEN/8, x3, x1, x4) + +inst_5931: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x83ff; +op3val:0x8001; valaddr_reg:x2; val_offset:17691*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17691*FLEN/8, x3, x1, x4) + +inst_5932: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x83ff; +op3val:0x2; valaddr_reg:x2; val_offset:17694*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17694*FLEN/8, x3, x1, x4) + +inst_5933: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x83ff; +op3val:0x83fe; valaddr_reg:x2; val_offset:17697*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17697*FLEN/8, x3, x1, x4) + +inst_5934: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x83ff; +op3val:0x3ff; valaddr_reg:x2; val_offset:17700*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17700*FLEN/8, x3, x1, x4) + +inst_5935: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x83ff; +op3val:0x83ff; valaddr_reg:x2; val_offset:17703*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17703*FLEN/8, x3, x1, x4) + +inst_5936: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x83ff; +op3val:0x400; valaddr_reg:x2; val_offset:17706*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17706*FLEN/8, x3, x1, x4) + +inst_5937: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x83ff; +op3val:0x8400; valaddr_reg:x2; val_offset:17709*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17709*FLEN/8, x3, x1, x4) + +inst_5938: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x83ff; +op3val:0x401; valaddr_reg:x2; val_offset:17712*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17712*FLEN/8, x3, x1, x4) + +inst_5939: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x83ff; +op3val:0x8455; valaddr_reg:x2; val_offset:17715*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17715*FLEN/8, x3, x1, x4) + +inst_5940: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x83ff; +op3val:0x7bff; valaddr_reg:x2; val_offset:17718*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17718*FLEN/8, x3, x1, x4) + +inst_5941: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x83ff; +op3val:0xfbff; valaddr_reg:x2; val_offset:17721*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17721*FLEN/8, x3, x1, x4) + +inst_5942: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x83ff; +op3val:0x7c00; valaddr_reg:x2; val_offset:17724*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17724*FLEN/8, x3, x1, x4) + +inst_5943: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x83ff; +op3val:0xfc00; valaddr_reg:x2; val_offset:17727*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17727*FLEN/8, x3, x1, x4) + +inst_5944: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x83ff; +op3val:0x7e00; valaddr_reg:x2; val_offset:17730*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17730*FLEN/8, x3, x1, x4) + +inst_5945: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x83ff; +op3val:0xfe00; valaddr_reg:x2; val_offset:17733*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17733*FLEN/8, x3, x1, x4) + +inst_5946: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x83ff; +op3val:0x7e01; valaddr_reg:x2; val_offset:17736*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17736*FLEN/8, x3, x1, x4) + +inst_5947: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x83ff; +op3val:0xfe55; valaddr_reg:x2; val_offset:17739*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17739*FLEN/8, x3, x1, x4) + +inst_5948: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x83ff; +op3val:0x7c01; valaddr_reg:x2; val_offset:17742*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17742*FLEN/8, x3, x1, x4) + +inst_5949: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x83ff; +op3val:0xfd55; valaddr_reg:x2; val_offset:17745*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17745*FLEN/8, x3, x1, x4) + +inst_5950: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x83ff; +op3val:0x3c00; valaddr_reg:x2; val_offset:17748*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17748*FLEN/8, x3, x1, x4) + +inst_5951: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x83ff; +op3val:0xbc00; valaddr_reg:x2; val_offset:17751*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17751*FLEN/8, x3, x1, x4) + +inst_5952: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x400; +op3val:0x0; valaddr_reg:x2; val_offset:17754*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17754*FLEN/8, x3, x1, x4) + +inst_5953: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x400; +op3val:0x8000; valaddr_reg:x2; val_offset:17757*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17757*FLEN/8, x3, x1, x4) + +inst_5954: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x400; +op3val:0x1; valaddr_reg:x2; val_offset:17760*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17760*FLEN/8, x3, x1, x4) + +inst_5955: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x400; +op3val:0x8001; valaddr_reg:x2; val_offset:17763*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17763*FLEN/8, x3, x1, x4) + +inst_5956: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x400; +op3val:0x2; valaddr_reg:x2; val_offset:17766*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17766*FLEN/8, x3, x1, x4) + +inst_5957: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x400; +op3val:0x83fe; valaddr_reg:x2; val_offset:17769*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17769*FLEN/8, x3, x1, x4) + +inst_5958: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x400; +op3val:0x3ff; valaddr_reg:x2; val_offset:17772*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17772*FLEN/8, x3, x1, x4) + +inst_5959: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x400; +op3val:0x83ff; valaddr_reg:x2; val_offset:17775*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17775*FLEN/8, x3, x1, x4) + +inst_5960: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x400; +op3val:0x400; valaddr_reg:x2; val_offset:17778*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17778*FLEN/8, x3, x1, x4) + +inst_5961: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x400; +op3val:0x8400; valaddr_reg:x2; val_offset:17781*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17781*FLEN/8, x3, x1, x4) + +inst_5962: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x400; +op3val:0x401; valaddr_reg:x2; val_offset:17784*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17784*FLEN/8, x3, x1, x4) + +inst_5963: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x400; +op3val:0x8455; valaddr_reg:x2; val_offset:17787*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17787*FLEN/8, x3, x1, x4) + +inst_5964: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x400; +op3val:0x7bff; valaddr_reg:x2; val_offset:17790*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17790*FLEN/8, x3, x1, x4) + +inst_5965: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x400; +op3val:0xfbff; valaddr_reg:x2; val_offset:17793*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17793*FLEN/8, x3, x1, x4) + +inst_5966: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x400; +op3val:0x7c00; valaddr_reg:x2; val_offset:17796*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17796*FLEN/8, x3, x1, x4) + +inst_5967: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x400; +op3val:0xfc00; valaddr_reg:x2; val_offset:17799*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17799*FLEN/8, x3, x1, x4) + +inst_5968: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x400; +op3val:0x7e00; valaddr_reg:x2; val_offset:17802*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17802*FLEN/8, x3, x1, x4) + +inst_5969: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x400; +op3val:0xfe00; valaddr_reg:x2; val_offset:17805*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17805*FLEN/8, x3, x1, x4) + +inst_5970: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x400; +op3val:0x7e01; valaddr_reg:x2; val_offset:17808*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17808*FLEN/8, x3, x1, x4) + +inst_5971: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x400; +op3val:0xfe55; valaddr_reg:x2; val_offset:17811*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17811*FLEN/8, x3, x1, x4) + +inst_5972: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x400; +op3val:0x7c01; valaddr_reg:x2; val_offset:17814*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17814*FLEN/8, x3, x1, x4) + +inst_5973: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x400; +op3val:0xfd55; valaddr_reg:x2; val_offset:17817*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17817*FLEN/8, x3, x1, x4) + +inst_5974: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x400; +op3val:0x3c00; valaddr_reg:x2; val_offset:17820*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17820*FLEN/8, x3, x1, x4) + +inst_5975: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x400; +op3val:0xbc00; valaddr_reg:x2; val_offset:17823*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17823*FLEN/8, x3, x1, x4) + +inst_5976: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8400; +op3val:0x0; valaddr_reg:x2; val_offset:17826*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17826*FLEN/8, x3, x1, x4) + +inst_5977: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8400; +op3val:0x8000; valaddr_reg:x2; val_offset:17829*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17829*FLEN/8, x3, x1, x4) + +inst_5978: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8400; +op3val:0x1; valaddr_reg:x2; val_offset:17832*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17832*FLEN/8, x3, x1, x4) + +inst_5979: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8400; +op3val:0x8001; valaddr_reg:x2; val_offset:17835*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17835*FLEN/8, x3, x1, x4) + +inst_5980: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8400; +op3val:0x2; valaddr_reg:x2; val_offset:17838*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17838*FLEN/8, x3, x1, x4) + +inst_5981: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8400; +op3val:0x83fe; valaddr_reg:x2; val_offset:17841*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17841*FLEN/8, x3, x1, x4) + +inst_5982: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8400; +op3val:0x3ff; valaddr_reg:x2; val_offset:17844*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17844*FLEN/8, x3, x1, x4) + +inst_5983: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8400; +op3val:0x83ff; valaddr_reg:x2; val_offset:17847*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17847*FLEN/8, x3, x1, x4) + +inst_5984: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8400; +op3val:0x400; valaddr_reg:x2; val_offset:17850*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17850*FLEN/8, x3, x1, x4) + +inst_5985: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8400; +op3val:0x8400; valaddr_reg:x2; val_offset:17853*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17853*FLEN/8, x3, x1, x4) + +inst_5986: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8400; +op3val:0x401; valaddr_reg:x2; val_offset:17856*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17856*FLEN/8, x3, x1, x4) + +inst_5987: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8400; +op3val:0x8455; valaddr_reg:x2; val_offset:17859*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17859*FLEN/8, x3, x1, x4) + +inst_5988: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8400; +op3val:0x7bff; valaddr_reg:x2; val_offset:17862*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17862*FLEN/8, x3, x1, x4) + +inst_5989: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8400; +op3val:0xfbff; valaddr_reg:x2; val_offset:17865*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17865*FLEN/8, x3, x1, x4) + +inst_5990: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8400; +op3val:0x7c00; valaddr_reg:x2; val_offset:17868*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17868*FLEN/8, x3, x1, x4) + +inst_5991: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8400; +op3val:0xfc00; valaddr_reg:x2; val_offset:17871*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17871*FLEN/8, x3, x1, x4) + +inst_5992: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8400; +op3val:0x7e00; valaddr_reg:x2; val_offset:17874*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17874*FLEN/8, x3, x1, x4) + +inst_5993: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8400; +op3val:0xfe00; valaddr_reg:x2; val_offset:17877*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17877*FLEN/8, x3, x1, x4) + +inst_5994: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8400; +op3val:0x7e01; valaddr_reg:x2; val_offset:17880*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17880*FLEN/8, x3, x1, x4) + +inst_5995: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8400; +op3val:0xfe55; valaddr_reg:x2; val_offset:17883*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17883*FLEN/8, x3, x1, x4) + +inst_5996: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8400; +op3val:0x7c01; valaddr_reg:x2; val_offset:17886*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17886*FLEN/8, x3, x1, x4) + +inst_5997: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8400; +op3val:0xfd55; valaddr_reg:x2; val_offset:17889*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17889*FLEN/8, x3, x1, x4) + +inst_5998: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8400; +op3val:0x3c00; valaddr_reg:x2; val_offset:17892*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17892*FLEN/8, x3, x1, x4) + +inst_5999: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8400; +op3val:0xbc00; valaddr_reg:x2; val_offset:17895*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17895*FLEN/8, x3, x1, x4) + +inst_6000: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x401; +op3val:0x0; valaddr_reg:x2; val_offset:17898*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17898*FLEN/8, x3, x1, x4) + +inst_6001: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x401; +op3val:0x8000; valaddr_reg:x2; val_offset:17901*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17901*FLEN/8, x3, x1, x4) + +inst_6002: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x401; +op3val:0x1; valaddr_reg:x2; val_offset:17904*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17904*FLEN/8, x3, x1, x4) + +inst_6003: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x401; +op3val:0x8001; valaddr_reg:x2; val_offset:17907*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17907*FLEN/8, x3, x1, x4) + +inst_6004: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x401; +op3val:0x2; valaddr_reg:x2; val_offset:17910*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17910*FLEN/8, x3, x1, x4) + +inst_6005: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x401; +op3val:0x83fe; valaddr_reg:x2; val_offset:17913*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17913*FLEN/8, x3, x1, x4) + +inst_6006: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x401; +op3val:0x3ff; valaddr_reg:x2; val_offset:17916*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17916*FLEN/8, x3, x1, x4) + +inst_6007: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x401; +op3val:0x83ff; valaddr_reg:x2; val_offset:17919*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17919*FLEN/8, x3, x1, x4) + +inst_6008: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x401; +op3val:0x400; valaddr_reg:x2; val_offset:17922*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17922*FLEN/8, x3, x1, x4) + +inst_6009: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x401; +op3val:0x8400; valaddr_reg:x2; val_offset:17925*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17925*FLEN/8, x3, x1, x4) + +inst_6010: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x401; +op3val:0x401; valaddr_reg:x2; val_offset:17928*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17928*FLEN/8, x3, x1, x4) + +inst_6011: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x401; +op3val:0x8455; valaddr_reg:x2; val_offset:17931*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17931*FLEN/8, x3, x1, x4) + +inst_6012: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x401; +op3val:0x7bff; valaddr_reg:x2; val_offset:17934*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17934*FLEN/8, x3, x1, x4) + +inst_6013: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x401; +op3val:0xfbff; valaddr_reg:x2; val_offset:17937*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17937*FLEN/8, x3, x1, x4) + +inst_6014: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x401; +op3val:0x7c00; valaddr_reg:x2; val_offset:17940*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17940*FLEN/8, x3, x1, x4) + +inst_6015: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x401; +op3val:0xfc00; valaddr_reg:x2; val_offset:17943*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17943*FLEN/8, x3, x1, x4) + +inst_6016: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x401; +op3val:0x7e00; valaddr_reg:x2; val_offset:17946*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17946*FLEN/8, x3, x1, x4) + +inst_6017: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x401; +op3val:0xfe00; valaddr_reg:x2; val_offset:17949*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17949*FLEN/8, x3, x1, x4) + +inst_6018: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x401; +op3val:0x7e01; valaddr_reg:x2; val_offset:17952*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17952*FLEN/8, x3, x1, x4) + +inst_6019: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x401; +op3val:0xfe55; valaddr_reg:x2; val_offset:17955*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17955*FLEN/8, x3, x1, x4) + +inst_6020: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x401; +op3val:0x7c01; valaddr_reg:x2; val_offset:17958*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17958*FLEN/8, x3, x1, x4) + +inst_6021: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x401; +op3val:0xfd55; valaddr_reg:x2; val_offset:17961*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17961*FLEN/8, x3, x1, x4) + +inst_6022: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x401; +op3val:0x3c00; valaddr_reg:x2; val_offset:17964*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17964*FLEN/8, x3, x1, x4) + +inst_6023: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x401; +op3val:0xbc00; valaddr_reg:x2; val_offset:17967*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17967*FLEN/8, x3, x1, x4) + +inst_6024: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8455; +op3val:0x0; valaddr_reg:x2; val_offset:17970*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17970*FLEN/8, x3, x1, x4) + +inst_6025: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8455; +op3val:0x8000; valaddr_reg:x2; val_offset:17973*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17973*FLEN/8, x3, x1, x4) + +inst_6026: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8455; +op3val:0x1; valaddr_reg:x2; val_offset:17976*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17976*FLEN/8, x3, x1, x4) + +inst_6027: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8455; +op3val:0x8001; valaddr_reg:x2; val_offset:17979*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17979*FLEN/8, x3, x1, x4) + +inst_6028: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8455; +op3val:0x2; valaddr_reg:x2; val_offset:17982*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17982*FLEN/8, x3, x1, x4) + +inst_6029: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8455; +op3val:0x83fe; valaddr_reg:x2; val_offset:17985*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17985*FLEN/8, x3, x1, x4) + +inst_6030: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8455; +op3val:0x3ff; valaddr_reg:x2; val_offset:17988*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17988*FLEN/8, x3, x1, x4) + +inst_6031: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8455; +op3val:0x83ff; valaddr_reg:x2; val_offset:17991*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17991*FLEN/8, x3, x1, x4) + +inst_6032: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8455; +op3val:0x400; valaddr_reg:x2; val_offset:17994*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17994*FLEN/8, x3, x1, x4) + +inst_6033: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8455; +op3val:0x8400; valaddr_reg:x2; val_offset:17997*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 17997*FLEN/8, x3, x1, x4) + +inst_6034: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8455; +op3val:0x401; valaddr_reg:x2; val_offset:18000*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18000*FLEN/8, x3, x1, x4) + +inst_6035: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8455; +op3val:0x8455; valaddr_reg:x2; val_offset:18003*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18003*FLEN/8, x3, x1, x4) + +inst_6036: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8455; +op3val:0x7bff; valaddr_reg:x2; val_offset:18006*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18006*FLEN/8, x3, x1, x4) + +inst_6037: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8455; +op3val:0xfbff; valaddr_reg:x2; val_offset:18009*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18009*FLEN/8, x3, x1, x4) + +inst_6038: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8455; +op3val:0x7c00; valaddr_reg:x2; val_offset:18012*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18012*FLEN/8, x3, x1, x4) + +inst_6039: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8455; +op3val:0xfc00; valaddr_reg:x2; val_offset:18015*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18015*FLEN/8, x3, x1, x4) + +inst_6040: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8455; +op3val:0x7e00; valaddr_reg:x2; val_offset:18018*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18018*FLEN/8, x3, x1, x4) + +inst_6041: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8455; +op3val:0xfe00; valaddr_reg:x2; val_offset:18021*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18021*FLEN/8, x3, x1, x4) + +inst_6042: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8455; +op3val:0x7e01; valaddr_reg:x2; val_offset:18024*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18024*FLEN/8, x3, x1, x4) + +inst_6043: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8455; +op3val:0xfe55; valaddr_reg:x2; val_offset:18027*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18027*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_48) + +inst_6044: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8455; +op3val:0x7c01; valaddr_reg:x2; val_offset:18030*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18030*FLEN/8, x3, x1, x4) + +inst_6045: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8455; +op3val:0xfd55; valaddr_reg:x2; val_offset:18033*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18033*FLEN/8, x3, x1, x4) + +inst_6046: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8455; +op3val:0x3c00; valaddr_reg:x2; val_offset:18036*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18036*FLEN/8, x3, x1, x4) + +inst_6047: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x8455; +op3val:0xbc00; valaddr_reg:x2; val_offset:18039*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18039*FLEN/8, x3, x1, x4) + +inst_6048: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7bff; +op3val:0x0; valaddr_reg:x2; val_offset:18042*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18042*FLEN/8, x3, x1, x4) + +inst_6049: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7bff; +op3val:0x8000; valaddr_reg:x2; val_offset:18045*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18045*FLEN/8, x3, x1, x4) + +inst_6050: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7bff; +op3val:0x1; valaddr_reg:x2; val_offset:18048*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18048*FLEN/8, x3, x1, x4) + +inst_6051: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7bff; +op3val:0x8001; valaddr_reg:x2; val_offset:18051*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18051*FLEN/8, x3, x1, x4) + +inst_6052: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7bff; +op3val:0x2; valaddr_reg:x2; val_offset:18054*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18054*FLEN/8, x3, x1, x4) + +inst_6053: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7bff; +op3val:0x83fe; valaddr_reg:x2; val_offset:18057*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18057*FLEN/8, x3, x1, x4) + +inst_6054: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7bff; +op3val:0x3ff; valaddr_reg:x2; val_offset:18060*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18060*FLEN/8, x3, x1, x4) + +inst_6055: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7bff; +op3val:0x83ff; valaddr_reg:x2; val_offset:18063*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18063*FLEN/8, x3, x1, x4) + +inst_6056: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7bff; +op3val:0x400; valaddr_reg:x2; val_offset:18066*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18066*FLEN/8, x3, x1, x4) + +inst_6057: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7bff; +op3val:0x8400; valaddr_reg:x2; val_offset:18069*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18069*FLEN/8, x3, x1, x4) + +inst_6058: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7bff; +op3val:0x401; valaddr_reg:x2; val_offset:18072*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18072*FLEN/8, x3, x1, x4) + +inst_6059: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7bff; +op3val:0x8455; valaddr_reg:x2; val_offset:18075*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18075*FLEN/8, x3, x1, x4) + +inst_6060: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7bff; +op3val:0x7bff; valaddr_reg:x2; val_offset:18078*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18078*FLEN/8, x3, x1, x4) + +inst_6061: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7bff; +op3val:0xfbff; valaddr_reg:x2; val_offset:18081*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18081*FLEN/8, x3, x1, x4) + +inst_6062: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7bff; +op3val:0x7c00; valaddr_reg:x2; val_offset:18084*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18084*FLEN/8, x3, x1, x4) + +inst_6063: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7bff; +op3val:0xfc00; valaddr_reg:x2; val_offset:18087*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18087*FLEN/8, x3, x1, x4) + +inst_6064: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7bff; +op3val:0x7e00; valaddr_reg:x2; val_offset:18090*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18090*FLEN/8, x3, x1, x4) + +inst_6065: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7bff; +op3val:0xfe00; valaddr_reg:x2; val_offset:18093*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18093*FLEN/8, x3, x1, x4) + +inst_6066: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7bff; +op3val:0x7e01; valaddr_reg:x2; val_offset:18096*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18096*FLEN/8, x3, x1, x4) + +inst_6067: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7bff; +op3val:0xfe55; valaddr_reg:x2; val_offset:18099*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18099*FLEN/8, x3, x1, x4) + +inst_6068: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7bff; +op3val:0x7c01; valaddr_reg:x2; val_offset:18102*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18102*FLEN/8, x3, x1, x4) + +inst_6069: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7bff; +op3val:0xfd55; valaddr_reg:x2; val_offset:18105*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18105*FLEN/8, x3, x1, x4) + +inst_6070: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7bff; +op3val:0x3c00; valaddr_reg:x2; val_offset:18108*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18108*FLEN/8, x3, x1, x4) + +inst_6071: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7bff; +op3val:0xbc00; valaddr_reg:x2; val_offset:18111*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18111*FLEN/8, x3, x1, x4) + +inst_6072: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfbff; +op3val:0x0; valaddr_reg:x2; val_offset:18114*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18114*FLEN/8, x3, x1, x4) + +inst_6073: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfbff; +op3val:0x8000; valaddr_reg:x2; val_offset:18117*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18117*FLEN/8, x3, x1, x4) + +inst_6074: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfbff; +op3val:0x1; valaddr_reg:x2; val_offset:18120*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18120*FLEN/8, x3, x1, x4) + +inst_6075: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfbff; +op3val:0x8001; valaddr_reg:x2; val_offset:18123*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18123*FLEN/8, x3, x1, x4) + +inst_6076: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfbff; +op3val:0x2; valaddr_reg:x2; val_offset:18126*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18126*FLEN/8, x3, x1, x4) + +inst_6077: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfbff; +op3val:0x83fe; valaddr_reg:x2; val_offset:18129*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18129*FLEN/8, x3, x1, x4) + +inst_6078: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfbff; +op3val:0x3ff; valaddr_reg:x2; val_offset:18132*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18132*FLEN/8, x3, x1, x4) + +inst_6079: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfbff; +op3val:0x83ff; valaddr_reg:x2; val_offset:18135*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18135*FLEN/8, x3, x1, x4) + +inst_6080: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfbff; +op3val:0x400; valaddr_reg:x2; val_offset:18138*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18138*FLEN/8, x3, x1, x4) + +inst_6081: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfbff; +op3val:0x8400; valaddr_reg:x2; val_offset:18141*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18141*FLEN/8, x3, x1, x4) + +inst_6082: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfbff; +op3val:0x401; valaddr_reg:x2; val_offset:18144*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18144*FLEN/8, x3, x1, x4) + +inst_6083: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfbff; +op3val:0x8455; valaddr_reg:x2; val_offset:18147*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18147*FLEN/8, x3, x1, x4) + +inst_6084: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfbff; +op3val:0x7bff; valaddr_reg:x2; val_offset:18150*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18150*FLEN/8, x3, x1, x4) + +inst_6085: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfbff; +op3val:0xfbff; valaddr_reg:x2; val_offset:18153*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18153*FLEN/8, x3, x1, x4) + +inst_6086: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfbff; +op3val:0x7c00; valaddr_reg:x2; val_offset:18156*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18156*FLEN/8, x3, x1, x4) + +inst_6087: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfbff; +op3val:0xfc00; valaddr_reg:x2; val_offset:18159*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18159*FLEN/8, x3, x1, x4) + +inst_6088: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfbff; +op3val:0x7e00; valaddr_reg:x2; val_offset:18162*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18162*FLEN/8, x3, x1, x4) + +inst_6089: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfbff; +op3val:0xfe00; valaddr_reg:x2; val_offset:18165*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18165*FLEN/8, x3, x1, x4) + +inst_6090: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfbff; +op3val:0x7e01; valaddr_reg:x2; val_offset:18168*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18168*FLEN/8, x3, x1, x4) + +inst_6091: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfbff; +op3val:0xfe55; valaddr_reg:x2; val_offset:18171*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18171*FLEN/8, x3, x1, x4) + +inst_6092: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfbff; +op3val:0x7c01; valaddr_reg:x2; val_offset:18174*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18174*FLEN/8, x3, x1, x4) + +inst_6093: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfbff; +op3val:0xfd55; valaddr_reg:x2; val_offset:18177*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18177*FLEN/8, x3, x1, x4) + +inst_6094: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfbff; +op3val:0x3c00; valaddr_reg:x2; val_offset:18180*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18180*FLEN/8, x3, x1, x4) + +inst_6095: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfbff; +op3val:0xbc00; valaddr_reg:x2; val_offset:18183*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18183*FLEN/8, x3, x1, x4) + +inst_6096: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7c00; +op3val:0x0; valaddr_reg:x2; val_offset:18186*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18186*FLEN/8, x3, x1, x4) + +inst_6097: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7c00; +op3val:0x8000; valaddr_reg:x2; val_offset:18189*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18189*FLEN/8, x3, x1, x4) + +inst_6098: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7c00; +op3val:0x1; valaddr_reg:x2; val_offset:18192*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18192*FLEN/8, x3, x1, x4) + +inst_6099: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7c00; +op3val:0x8001; valaddr_reg:x2; val_offset:18195*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18195*FLEN/8, x3, x1, x4) + +inst_6100: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7c00; +op3val:0x2; valaddr_reg:x2; val_offset:18198*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18198*FLEN/8, x3, x1, x4) + +inst_6101: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7c00; +op3val:0x83fe; valaddr_reg:x2; val_offset:18201*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18201*FLEN/8, x3, x1, x4) + +inst_6102: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7c00; +op3val:0x3ff; valaddr_reg:x2; val_offset:18204*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18204*FLEN/8, x3, x1, x4) + +inst_6103: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7c00; +op3val:0x83ff; valaddr_reg:x2; val_offset:18207*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18207*FLEN/8, x3, x1, x4) + +inst_6104: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7c00; +op3val:0x400; valaddr_reg:x2; val_offset:18210*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18210*FLEN/8, x3, x1, x4) + +inst_6105: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7c00; +op3val:0x8400; valaddr_reg:x2; val_offset:18213*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18213*FLEN/8, x3, x1, x4) + +inst_6106: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7c00; +op3val:0x401; valaddr_reg:x2; val_offset:18216*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18216*FLEN/8, x3, x1, x4) + +inst_6107: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7c00; +op3val:0x8455; valaddr_reg:x2; val_offset:18219*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18219*FLEN/8, x3, x1, x4) + +inst_6108: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7c00; +op3val:0x7bff; valaddr_reg:x2; val_offset:18222*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18222*FLEN/8, x3, x1, x4) + +inst_6109: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7c00; +op3val:0xfbff; valaddr_reg:x2; val_offset:18225*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18225*FLEN/8, x3, x1, x4) + +inst_6110: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7c00; +op3val:0x7c00; valaddr_reg:x2; val_offset:18228*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18228*FLEN/8, x3, x1, x4) + +inst_6111: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7c00; +op3val:0xfc00; valaddr_reg:x2; val_offset:18231*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18231*FLEN/8, x3, x1, x4) + +inst_6112: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7c00; +op3val:0x7e00; valaddr_reg:x2; val_offset:18234*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18234*FLEN/8, x3, x1, x4) + +inst_6113: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7c00; +op3val:0xfe00; valaddr_reg:x2; val_offset:18237*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18237*FLEN/8, x3, x1, x4) + +inst_6114: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7c00; +op3val:0x7e01; valaddr_reg:x2; val_offset:18240*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18240*FLEN/8, x3, x1, x4) + +inst_6115: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7c00; +op3val:0xfe55; valaddr_reg:x2; val_offset:18243*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18243*FLEN/8, x3, x1, x4) + +inst_6116: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7c00; +op3val:0x7c01; valaddr_reg:x2; val_offset:18246*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18246*FLEN/8, x3, x1, x4) + +inst_6117: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7c00; +op3val:0xfd55; valaddr_reg:x2; val_offset:18249*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18249*FLEN/8, x3, x1, x4) + +inst_6118: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7c00; +op3val:0x3c00; valaddr_reg:x2; val_offset:18252*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18252*FLEN/8, x3, x1, x4) + +inst_6119: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7c00; +op3val:0xbc00; valaddr_reg:x2; val_offset:18255*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18255*FLEN/8, x3, x1, x4) + +inst_6120: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfc00; +op3val:0x0; valaddr_reg:x2; val_offset:18258*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18258*FLEN/8, x3, x1, x4) + +inst_6121: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfc00; +op3val:0x8000; valaddr_reg:x2; val_offset:18261*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18261*FLEN/8, x3, x1, x4) + +inst_6122: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfc00; +op3val:0x1; valaddr_reg:x2; val_offset:18264*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18264*FLEN/8, x3, x1, x4) + +inst_6123: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfc00; +op3val:0x8001; valaddr_reg:x2; val_offset:18267*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18267*FLEN/8, x3, x1, x4) + +inst_6124: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfc00; +op3val:0x2; valaddr_reg:x2; val_offset:18270*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18270*FLEN/8, x3, x1, x4) + +inst_6125: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfc00; +op3val:0x83fe; valaddr_reg:x2; val_offset:18273*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18273*FLEN/8, x3, x1, x4) + +inst_6126: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfc00; +op3val:0x3ff; valaddr_reg:x2; val_offset:18276*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18276*FLEN/8, x3, x1, x4) + +inst_6127: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfc00; +op3val:0x83ff; valaddr_reg:x2; val_offset:18279*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18279*FLEN/8, x3, x1, x4) + +inst_6128: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfc00; +op3val:0x400; valaddr_reg:x2; val_offset:18282*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18282*FLEN/8, x3, x1, x4) + +inst_6129: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfc00; +op3val:0x8400; valaddr_reg:x2; val_offset:18285*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18285*FLEN/8, x3, x1, x4) + +inst_6130: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfc00; +op3val:0x401; valaddr_reg:x2; val_offset:18288*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18288*FLEN/8, x3, x1, x4) + +inst_6131: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfc00; +op3val:0x8455; valaddr_reg:x2; val_offset:18291*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18291*FLEN/8, x3, x1, x4) + +inst_6132: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfc00; +op3val:0x7bff; valaddr_reg:x2; val_offset:18294*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18294*FLEN/8, x3, x1, x4) + +inst_6133: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfc00; +op3val:0xfbff; valaddr_reg:x2; val_offset:18297*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18297*FLEN/8, x3, x1, x4) + +inst_6134: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfc00; +op3val:0x7c00; valaddr_reg:x2; val_offset:18300*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18300*FLEN/8, x3, x1, x4) + +inst_6135: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfc00; +op3val:0xfc00; valaddr_reg:x2; val_offset:18303*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18303*FLEN/8, x3, x1, x4) + +inst_6136: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfc00; +op3val:0x7e00; valaddr_reg:x2; val_offset:18306*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18306*FLEN/8, x3, x1, x4) + +inst_6137: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfc00; +op3val:0xfe00; valaddr_reg:x2; val_offset:18309*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18309*FLEN/8, x3, x1, x4) + +inst_6138: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfc00; +op3val:0x7e01; valaddr_reg:x2; val_offset:18312*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18312*FLEN/8, x3, x1, x4) + +inst_6139: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfc00; +op3val:0xfe55; valaddr_reg:x2; val_offset:18315*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18315*FLEN/8, x3, x1, x4) + +inst_6140: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfc00; +op3val:0x7c01; valaddr_reg:x2; val_offset:18318*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18318*FLEN/8, x3, x1, x4) + +inst_6141: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfc00; +op3val:0xfd55; valaddr_reg:x2; val_offset:18321*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18321*FLEN/8, x3, x1, x4) + +inst_6142: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfc00; +op3val:0x3c00; valaddr_reg:x2; val_offset:18324*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18324*FLEN/8, x3, x1, x4) + +inst_6143: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfc00; +op3val:0xbc00; valaddr_reg:x2; val_offset:18327*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18327*FLEN/8, x3, x1, x4) + +inst_6144: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7e00; +op3val:0x0; valaddr_reg:x2; val_offset:18330*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18330*FLEN/8, x3, x1, x4) + +inst_6145: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7e00; +op3val:0x8000; valaddr_reg:x2; val_offset:18333*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18333*FLEN/8, x3, x1, x4) + +inst_6146: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7e00; +op3val:0x1; valaddr_reg:x2; val_offset:18336*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18336*FLEN/8, x3, x1, x4) + +inst_6147: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7e00; +op3val:0x8001; valaddr_reg:x2; val_offset:18339*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18339*FLEN/8, x3, x1, x4) + +inst_6148: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7e00; +op3val:0x2; valaddr_reg:x2; val_offset:18342*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18342*FLEN/8, x3, x1, x4) + +inst_6149: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7e00; +op3val:0x83fe; valaddr_reg:x2; val_offset:18345*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18345*FLEN/8, x3, x1, x4) + +inst_6150: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7e00; +op3val:0x3ff; valaddr_reg:x2; val_offset:18348*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18348*FLEN/8, x3, x1, x4) + +inst_6151: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7e00; +op3val:0x83ff; valaddr_reg:x2; val_offset:18351*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18351*FLEN/8, x3, x1, x4) + +inst_6152: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7e00; +op3val:0x400; valaddr_reg:x2; val_offset:18354*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18354*FLEN/8, x3, x1, x4) + +inst_6153: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7e00; +op3val:0x8400; valaddr_reg:x2; val_offset:18357*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18357*FLEN/8, x3, x1, x4) + +inst_6154: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7e00; +op3val:0x401; valaddr_reg:x2; val_offset:18360*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18360*FLEN/8, x3, x1, x4) + +inst_6155: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7e00; +op3val:0x8455; valaddr_reg:x2; val_offset:18363*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18363*FLEN/8, x3, x1, x4) + +inst_6156: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7e00; +op3val:0x7bff; valaddr_reg:x2; val_offset:18366*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18366*FLEN/8, x3, x1, x4) + +inst_6157: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7e00; +op3val:0xfbff; valaddr_reg:x2; val_offset:18369*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18369*FLEN/8, x3, x1, x4) + +inst_6158: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7e00; +op3val:0x7c00; valaddr_reg:x2; val_offset:18372*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18372*FLEN/8, x3, x1, x4) + +inst_6159: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7e00; +op3val:0xfc00; valaddr_reg:x2; val_offset:18375*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18375*FLEN/8, x3, x1, x4) + +inst_6160: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7e00; +op3val:0x7e00; valaddr_reg:x2; val_offset:18378*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18378*FLEN/8, x3, x1, x4) + +inst_6161: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7e00; +op3val:0xfe00; valaddr_reg:x2; val_offset:18381*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18381*FLEN/8, x3, x1, x4) + +inst_6162: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7e00; +op3val:0x7e01; valaddr_reg:x2; val_offset:18384*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18384*FLEN/8, x3, x1, x4) + +inst_6163: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7e00; +op3val:0xfe55; valaddr_reg:x2; val_offset:18387*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18387*FLEN/8, x3, x1, x4) + +inst_6164: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7e00; +op3val:0x7c01; valaddr_reg:x2; val_offset:18390*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18390*FLEN/8, x3, x1, x4) + +inst_6165: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7e00; +op3val:0xfd55; valaddr_reg:x2; val_offset:18393*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18393*FLEN/8, x3, x1, x4) + +inst_6166: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7e00; +op3val:0x3c00; valaddr_reg:x2; val_offset:18396*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18396*FLEN/8, x3, x1, x4) + +inst_6167: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7e00; +op3val:0xbc00; valaddr_reg:x2; val_offset:18399*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18399*FLEN/8, x3, x1, x4) + +inst_6168: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfe00; +op3val:0x0; valaddr_reg:x2; val_offset:18402*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18402*FLEN/8, x3, x1, x4) + +inst_6169: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfe00; +op3val:0x8000; valaddr_reg:x2; val_offset:18405*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18405*FLEN/8, x3, x1, x4) + +inst_6170: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfe00; +op3val:0x1; valaddr_reg:x2; val_offset:18408*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18408*FLEN/8, x3, x1, x4) + +inst_6171: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfe00; +op3val:0x8001; valaddr_reg:x2; val_offset:18411*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18411*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_49) + +inst_6172: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfe00; +op3val:0x2; valaddr_reg:x2; val_offset:18414*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18414*FLEN/8, x3, x1, x4) + +inst_6173: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfe00; +op3val:0x83fe; valaddr_reg:x2; val_offset:18417*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18417*FLEN/8, x3, x1, x4) + +inst_6174: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfe00; +op3val:0x3ff; valaddr_reg:x2; val_offset:18420*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18420*FLEN/8, x3, x1, x4) + +inst_6175: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfe00; +op3val:0x83ff; valaddr_reg:x2; val_offset:18423*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18423*FLEN/8, x3, x1, x4) + +inst_6176: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfe00; +op3val:0x400; valaddr_reg:x2; val_offset:18426*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18426*FLEN/8, x3, x1, x4) + +inst_6177: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfe00; +op3val:0x8400; valaddr_reg:x2; val_offset:18429*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18429*FLEN/8, x3, x1, x4) + +inst_6178: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfe00; +op3val:0x401; valaddr_reg:x2; val_offset:18432*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18432*FLEN/8, x3, x1, x4) + +inst_6179: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfe00; +op3val:0x8455; valaddr_reg:x2; val_offset:18435*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18435*FLEN/8, x3, x1, x4) + +inst_6180: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfe00; +op3val:0x7bff; valaddr_reg:x2; val_offset:18438*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18438*FLEN/8, x3, x1, x4) + +inst_6181: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfe00; +op3val:0xfbff; valaddr_reg:x2; val_offset:18441*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18441*FLEN/8, x3, x1, x4) + +inst_6182: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfe00; +op3val:0x7c00; valaddr_reg:x2; val_offset:18444*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18444*FLEN/8, x3, x1, x4) + +inst_6183: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfe00; +op3val:0xfc00; valaddr_reg:x2; val_offset:18447*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18447*FLEN/8, x3, x1, x4) + +inst_6184: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfe00; +op3val:0x7e00; valaddr_reg:x2; val_offset:18450*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18450*FLEN/8, x3, x1, x4) + +inst_6185: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfe00; +op3val:0xfe00; valaddr_reg:x2; val_offset:18453*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18453*FLEN/8, x3, x1, x4) + +inst_6186: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfe00; +op3val:0x7e01; valaddr_reg:x2; val_offset:18456*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18456*FLEN/8, x3, x1, x4) + +inst_6187: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfe00; +op3val:0xfe55; valaddr_reg:x2; val_offset:18459*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18459*FLEN/8, x3, x1, x4) + +inst_6188: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfe00; +op3val:0x7c01; valaddr_reg:x2; val_offset:18462*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18462*FLEN/8, x3, x1, x4) + +inst_6189: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfe00; +op3val:0xfd55; valaddr_reg:x2; val_offset:18465*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18465*FLEN/8, x3, x1, x4) + +inst_6190: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfe00; +op3val:0x3c00; valaddr_reg:x2; val_offset:18468*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18468*FLEN/8, x3, x1, x4) + +inst_6191: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfe00; +op3val:0xbc00; valaddr_reg:x2; val_offset:18471*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18471*FLEN/8, x3, x1, x4) + +inst_6192: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7e01; +op3val:0x0; valaddr_reg:x2; val_offset:18474*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18474*FLEN/8, x3, x1, x4) + +inst_6193: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7e01; +op3val:0x8000; valaddr_reg:x2; val_offset:18477*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18477*FLEN/8, x3, x1, x4) + +inst_6194: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7e01; +op3val:0x1; valaddr_reg:x2; val_offset:18480*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18480*FLEN/8, x3, x1, x4) + +inst_6195: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7e01; +op3val:0x8001; valaddr_reg:x2; val_offset:18483*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18483*FLEN/8, x3, x1, x4) + +inst_6196: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7e01; +op3val:0x2; valaddr_reg:x2; val_offset:18486*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18486*FLEN/8, x3, x1, x4) + +inst_6197: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7e01; +op3val:0x83fe; valaddr_reg:x2; val_offset:18489*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18489*FLEN/8, x3, x1, x4) + +inst_6198: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7e01; +op3val:0x3ff; valaddr_reg:x2; val_offset:18492*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18492*FLEN/8, x3, x1, x4) + +inst_6199: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7e01; +op3val:0x83ff; valaddr_reg:x2; val_offset:18495*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18495*FLEN/8, x3, x1, x4) + +inst_6200: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7e01; +op3val:0x400; valaddr_reg:x2; val_offset:18498*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18498*FLEN/8, x3, x1, x4) + +inst_6201: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7e01; +op3val:0x8400; valaddr_reg:x2; val_offset:18501*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18501*FLEN/8, x3, x1, x4) + +inst_6202: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7e01; +op3val:0x401; valaddr_reg:x2; val_offset:18504*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18504*FLEN/8, x3, x1, x4) + +inst_6203: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7e01; +op3val:0x8455; valaddr_reg:x2; val_offset:18507*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18507*FLEN/8, x3, x1, x4) + +inst_6204: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7e01; +op3val:0x7bff; valaddr_reg:x2; val_offset:18510*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18510*FLEN/8, x3, x1, x4) + +inst_6205: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7e01; +op3val:0xfbff; valaddr_reg:x2; val_offset:18513*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18513*FLEN/8, x3, x1, x4) + +inst_6206: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7e01; +op3val:0x7c00; valaddr_reg:x2; val_offset:18516*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18516*FLEN/8, x3, x1, x4) + +inst_6207: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7e01; +op3val:0xfc00; valaddr_reg:x2; val_offset:18519*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18519*FLEN/8, x3, x1, x4) + +inst_6208: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7e01; +op3val:0x7e00; valaddr_reg:x2; val_offset:18522*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18522*FLEN/8, x3, x1, x4) + +inst_6209: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7e01; +op3val:0xfe00; valaddr_reg:x2; val_offset:18525*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18525*FLEN/8, x3, x1, x4) + +inst_6210: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7e01; +op3val:0x7e01; valaddr_reg:x2; val_offset:18528*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18528*FLEN/8, x3, x1, x4) + +inst_6211: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7e01; +op3val:0xfe55; valaddr_reg:x2; val_offset:18531*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18531*FLEN/8, x3, x1, x4) + +inst_6212: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7e01; +op3val:0x7c01; valaddr_reg:x2; val_offset:18534*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18534*FLEN/8, x3, x1, x4) + +inst_6213: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7e01; +op3val:0xfd55; valaddr_reg:x2; val_offset:18537*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18537*FLEN/8, x3, x1, x4) + +inst_6214: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7e01; +op3val:0x3c00; valaddr_reg:x2; val_offset:18540*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18540*FLEN/8, x3, x1, x4) + +inst_6215: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7e01; +op3val:0xbc00; valaddr_reg:x2; val_offset:18543*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18543*FLEN/8, x3, x1, x4) + +inst_6216: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfe55; +op3val:0x0; valaddr_reg:x2; val_offset:18546*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18546*FLEN/8, x3, x1, x4) + +inst_6217: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfe55; +op3val:0x8000; valaddr_reg:x2; val_offset:18549*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18549*FLEN/8, x3, x1, x4) + +inst_6218: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfe55; +op3val:0x1; valaddr_reg:x2; val_offset:18552*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18552*FLEN/8, x3, x1, x4) + +inst_6219: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfe55; +op3val:0x8001; valaddr_reg:x2; val_offset:18555*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18555*FLEN/8, x3, x1, x4) + +inst_6220: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfe55; +op3val:0x2; valaddr_reg:x2; val_offset:18558*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18558*FLEN/8, x3, x1, x4) + +inst_6221: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfe55; +op3val:0x83fe; valaddr_reg:x2; val_offset:18561*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18561*FLEN/8, x3, x1, x4) + +inst_6222: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfe55; +op3val:0x3ff; valaddr_reg:x2; val_offset:18564*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18564*FLEN/8, x3, x1, x4) + +inst_6223: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfe55; +op3val:0x83ff; valaddr_reg:x2; val_offset:18567*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18567*FLEN/8, x3, x1, x4) + +inst_6224: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfe55; +op3val:0x400; valaddr_reg:x2; val_offset:18570*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18570*FLEN/8, x3, x1, x4) + +inst_6225: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfe55; +op3val:0x8400; valaddr_reg:x2; val_offset:18573*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18573*FLEN/8, x3, x1, x4) + +inst_6226: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfe55; +op3val:0x401; valaddr_reg:x2; val_offset:18576*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18576*FLEN/8, x3, x1, x4) + +inst_6227: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfe55; +op3val:0x8455; valaddr_reg:x2; val_offset:18579*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18579*FLEN/8, x3, x1, x4) + +inst_6228: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfe55; +op3val:0x7bff; valaddr_reg:x2; val_offset:18582*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18582*FLEN/8, x3, x1, x4) + +inst_6229: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfe55; +op3val:0xfbff; valaddr_reg:x2; val_offset:18585*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18585*FLEN/8, x3, x1, x4) + +inst_6230: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfe55; +op3val:0x7c00; valaddr_reg:x2; val_offset:18588*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18588*FLEN/8, x3, x1, x4) + +inst_6231: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfe55; +op3val:0xfc00; valaddr_reg:x2; val_offset:18591*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18591*FLEN/8, x3, x1, x4) + +inst_6232: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfe55; +op3val:0x7e00; valaddr_reg:x2; val_offset:18594*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18594*FLEN/8, x3, x1, x4) + +inst_6233: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfe55; +op3val:0xfe00; valaddr_reg:x2; val_offset:18597*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18597*FLEN/8, x3, x1, x4) + +inst_6234: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfe55; +op3val:0x7e01; valaddr_reg:x2; val_offset:18600*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18600*FLEN/8, x3, x1, x4) + +inst_6235: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfe55; +op3val:0xfe55; valaddr_reg:x2; val_offset:18603*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18603*FLEN/8, x3, x1, x4) + +inst_6236: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfe55; +op3val:0x7c01; valaddr_reg:x2; val_offset:18606*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18606*FLEN/8, x3, x1, x4) + +inst_6237: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfe55; +op3val:0xfd55; valaddr_reg:x2; val_offset:18609*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18609*FLEN/8, x3, x1, x4) + +inst_6238: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfe55; +op3val:0x3c00; valaddr_reg:x2; val_offset:18612*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18612*FLEN/8, x3, x1, x4) + +inst_6239: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfe55; +op3val:0xbc00; valaddr_reg:x2; val_offset:18615*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18615*FLEN/8, x3, x1, x4) + +inst_6240: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7c01; +op3val:0x0; valaddr_reg:x2; val_offset:18618*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18618*FLEN/8, x3, x1, x4) + +inst_6241: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7c01; +op3val:0x8000; valaddr_reg:x2; val_offset:18621*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18621*FLEN/8, x3, x1, x4) + +inst_6242: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7c01; +op3val:0x1; valaddr_reg:x2; val_offset:18624*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18624*FLEN/8, x3, x1, x4) + +inst_6243: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7c01; +op3val:0x8001; valaddr_reg:x2; val_offset:18627*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18627*FLEN/8, x3, x1, x4) + +inst_6244: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7c01; +op3val:0x2; valaddr_reg:x2; val_offset:18630*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18630*FLEN/8, x3, x1, x4) + +inst_6245: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7c01; +op3val:0x83fe; valaddr_reg:x2; val_offset:18633*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18633*FLEN/8, x3, x1, x4) + +inst_6246: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7c01; +op3val:0x3ff; valaddr_reg:x2; val_offset:18636*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18636*FLEN/8, x3, x1, x4) + +inst_6247: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7c01; +op3val:0x83ff; valaddr_reg:x2; val_offset:18639*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18639*FLEN/8, x3, x1, x4) + +inst_6248: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7c01; +op3val:0x400; valaddr_reg:x2; val_offset:18642*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18642*FLEN/8, x3, x1, x4) + +inst_6249: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7c01; +op3val:0x8400; valaddr_reg:x2; val_offset:18645*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18645*FLEN/8, x3, x1, x4) + +inst_6250: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7c01; +op3val:0x401; valaddr_reg:x2; val_offset:18648*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18648*FLEN/8, x3, x1, x4) + +inst_6251: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7c01; +op3val:0x8455; valaddr_reg:x2; val_offset:18651*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18651*FLEN/8, x3, x1, x4) + +inst_6252: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7c01; +op3val:0x7bff; valaddr_reg:x2; val_offset:18654*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18654*FLEN/8, x3, x1, x4) + +inst_6253: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7c01; +op3val:0xfbff; valaddr_reg:x2; val_offset:18657*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18657*FLEN/8, x3, x1, x4) + +inst_6254: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7c01; +op3val:0x7c00; valaddr_reg:x2; val_offset:18660*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18660*FLEN/8, x3, x1, x4) + +inst_6255: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7c01; +op3val:0xfc00; valaddr_reg:x2; val_offset:18663*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18663*FLEN/8, x3, x1, x4) + +inst_6256: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7c01; +op3val:0x7e00; valaddr_reg:x2; val_offset:18666*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18666*FLEN/8, x3, x1, x4) + +inst_6257: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7c01; +op3val:0xfe00; valaddr_reg:x2; val_offset:18669*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18669*FLEN/8, x3, x1, x4) + +inst_6258: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7c01; +op3val:0x7e01; valaddr_reg:x2; val_offset:18672*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18672*FLEN/8, x3, x1, x4) + +inst_6259: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7c01; +op3val:0xfe55; valaddr_reg:x2; val_offset:18675*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18675*FLEN/8, x3, x1, x4) + +inst_6260: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7c01; +op3val:0x7c01; valaddr_reg:x2; val_offset:18678*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18678*FLEN/8, x3, x1, x4) + +inst_6261: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7c01; +op3val:0xfd55; valaddr_reg:x2; val_offset:18681*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18681*FLEN/8, x3, x1, x4) + +inst_6262: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7c01; +op3val:0x3c00; valaddr_reg:x2; val_offset:18684*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18684*FLEN/8, x3, x1, x4) + +inst_6263: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x7c01; +op3val:0xbc00; valaddr_reg:x2; val_offset:18687*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18687*FLEN/8, x3, x1, x4) + +inst_6264: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfd55; +op3val:0x0; valaddr_reg:x2; val_offset:18690*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18690*FLEN/8, x3, x1, x4) + +inst_6265: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfd55; +op3val:0x8000; valaddr_reg:x2; val_offset:18693*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18693*FLEN/8, x3, x1, x4) + +inst_6266: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfd55; +op3val:0x1; valaddr_reg:x2; val_offset:18696*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18696*FLEN/8, x3, x1, x4) + +inst_6267: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfd55; +op3val:0x8001; valaddr_reg:x2; val_offset:18699*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18699*FLEN/8, x3, x1, x4) + +inst_6268: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfd55; +op3val:0x2; valaddr_reg:x2; val_offset:18702*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18702*FLEN/8, x3, x1, x4) + +inst_6269: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfd55; +op3val:0x83fe; valaddr_reg:x2; val_offset:18705*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18705*FLEN/8, x3, x1, x4) + +inst_6270: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfd55; +op3val:0x3ff; valaddr_reg:x2; val_offset:18708*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18708*FLEN/8, x3, x1, x4) + +inst_6271: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfd55; +op3val:0x83ff; valaddr_reg:x2; val_offset:18711*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18711*FLEN/8, x3, x1, x4) + +inst_6272: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfd55; +op3val:0x400; valaddr_reg:x2; val_offset:18714*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18714*FLEN/8, x3, x1, x4) + +inst_6273: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfd55; +op3val:0x8400; valaddr_reg:x2; val_offset:18717*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18717*FLEN/8, x3, x1, x4) + +inst_6274: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfd55; +op3val:0x401; valaddr_reg:x2; val_offset:18720*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18720*FLEN/8, x3, x1, x4) + +inst_6275: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfd55; +op3val:0x8455; valaddr_reg:x2; val_offset:18723*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18723*FLEN/8, x3, x1, x4) + +inst_6276: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfd55; +op3val:0x7bff; valaddr_reg:x2; val_offset:18726*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18726*FLEN/8, x3, x1, x4) + +inst_6277: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfd55; +op3val:0xfbff; valaddr_reg:x2; val_offset:18729*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18729*FLEN/8, x3, x1, x4) + +inst_6278: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfd55; +op3val:0x7c00; valaddr_reg:x2; val_offset:18732*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18732*FLEN/8, x3, x1, x4) + +inst_6279: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfd55; +op3val:0xfc00; valaddr_reg:x2; val_offset:18735*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18735*FLEN/8, x3, x1, x4) + +inst_6280: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfd55; +op3val:0x7e00; valaddr_reg:x2; val_offset:18738*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18738*FLEN/8, x3, x1, x4) + +inst_6281: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfd55; +op3val:0xfe00; valaddr_reg:x2; val_offset:18741*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18741*FLEN/8, x3, x1, x4) + +inst_6282: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfd55; +op3val:0x7e01; valaddr_reg:x2; val_offset:18744*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18744*FLEN/8, x3, x1, x4) + +inst_6283: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfd55; +op3val:0xfe55; valaddr_reg:x2; val_offset:18747*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18747*FLEN/8, x3, x1, x4) + +inst_6284: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfd55; +op3val:0x7c01; valaddr_reg:x2; val_offset:18750*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18750*FLEN/8, x3, x1, x4) + +inst_6285: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfd55; +op3val:0xfd55; valaddr_reg:x2; val_offset:18753*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18753*FLEN/8, x3, x1, x4) + +inst_6286: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfd55; +op3val:0x3c00; valaddr_reg:x2; val_offset:18756*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18756*FLEN/8, x3, x1, x4) + +inst_6287: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xfd55; +op3val:0xbc00; valaddr_reg:x2; val_offset:18759*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18759*FLEN/8, x3, x1, x4) + +inst_6288: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x3c00; +op3val:0x0; valaddr_reg:x2; val_offset:18762*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18762*FLEN/8, x3, x1, x4) + +inst_6289: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x3c00; +op3val:0x8000; valaddr_reg:x2; val_offset:18765*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18765*FLEN/8, x3, x1, x4) + +inst_6290: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x3c00; +op3val:0x1; valaddr_reg:x2; val_offset:18768*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18768*FLEN/8, x3, x1, x4) + +inst_6291: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x3c00; +op3val:0x8001; valaddr_reg:x2; val_offset:18771*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18771*FLEN/8, x3, x1, x4) + +inst_6292: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x3c00; +op3val:0x2; valaddr_reg:x2; val_offset:18774*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18774*FLEN/8, x3, x1, x4) + +inst_6293: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x3c00; +op3val:0x83fe; valaddr_reg:x2; val_offset:18777*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18777*FLEN/8, x3, x1, x4) + +inst_6294: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x3c00; +op3val:0x3ff; valaddr_reg:x2; val_offset:18780*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18780*FLEN/8, x3, x1, x4) + +inst_6295: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x3c00; +op3val:0x83ff; valaddr_reg:x2; val_offset:18783*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18783*FLEN/8, x3, x1, x4) + +inst_6296: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x3c00; +op3val:0x400; valaddr_reg:x2; val_offset:18786*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18786*FLEN/8, x3, x1, x4) + +inst_6297: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x3c00; +op3val:0x8400; valaddr_reg:x2; val_offset:18789*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18789*FLEN/8, x3, x1, x4) + +inst_6298: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x3c00; +op3val:0x401; valaddr_reg:x2; val_offset:18792*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18792*FLEN/8, x3, x1, x4) + +inst_6299: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x3c00; +op3val:0x8455; valaddr_reg:x2; val_offset:18795*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18795*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_50) + +inst_6300: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x3c00; +op3val:0x7bff; valaddr_reg:x2; val_offset:18798*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18798*FLEN/8, x3, x1, x4) + +inst_6301: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x3c00; +op3val:0xfbff; valaddr_reg:x2; val_offset:18801*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18801*FLEN/8, x3, x1, x4) + +inst_6302: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x3c00; +op3val:0x7c00; valaddr_reg:x2; val_offset:18804*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18804*FLEN/8, x3, x1, x4) + +inst_6303: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x3c00; +op3val:0xfc00; valaddr_reg:x2; val_offset:18807*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18807*FLEN/8, x3, x1, x4) + +inst_6304: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x3c00; +op3val:0x7e00; valaddr_reg:x2; val_offset:18810*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18810*FLEN/8, x3, x1, x4) + +inst_6305: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x3c00; +op3val:0xfe00; valaddr_reg:x2; val_offset:18813*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18813*FLEN/8, x3, x1, x4) + +inst_6306: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x3c00; +op3val:0x7e01; valaddr_reg:x2; val_offset:18816*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18816*FLEN/8, x3, x1, x4) + +inst_6307: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x3c00; +op3val:0xfe55; valaddr_reg:x2; val_offset:18819*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18819*FLEN/8, x3, x1, x4) + +inst_6308: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x3c00; +op3val:0x7c01; valaddr_reg:x2; val_offset:18822*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18822*FLEN/8, x3, x1, x4) + +inst_6309: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x3c00; +op3val:0xfd55; valaddr_reg:x2; val_offset:18825*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18825*FLEN/8, x3, x1, x4) + +inst_6310: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x3c00; +op3val:0x3c00; valaddr_reg:x2; val_offset:18828*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18828*FLEN/8, x3, x1, x4) + +inst_6311: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x3c00; +op3val:0xbc00; valaddr_reg:x2; val_offset:18831*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18831*FLEN/8, x3, x1, x4) + +inst_6312: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xbc00; +op3val:0x0; valaddr_reg:x2; val_offset:18834*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18834*FLEN/8, x3, x1, x4) + +inst_6313: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xbc00; +op3val:0x8000; valaddr_reg:x2; val_offset:18837*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18837*FLEN/8, x3, x1, x4) + +inst_6314: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xbc00; +op3val:0x1; valaddr_reg:x2; val_offset:18840*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18840*FLEN/8, x3, x1, x4) + +inst_6315: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xbc00; +op3val:0x8001; valaddr_reg:x2; val_offset:18843*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18843*FLEN/8, x3, x1, x4) + +inst_6316: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xbc00; +op3val:0x2; valaddr_reg:x2; val_offset:18846*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18846*FLEN/8, x3, x1, x4) + +inst_6317: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xbc00; +op3val:0x83fe; valaddr_reg:x2; val_offset:18849*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18849*FLEN/8, x3, x1, x4) + +inst_6318: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xbc00; +op3val:0x3ff; valaddr_reg:x2; val_offset:18852*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18852*FLEN/8, x3, x1, x4) + +inst_6319: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xbc00; +op3val:0x83ff; valaddr_reg:x2; val_offset:18855*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18855*FLEN/8, x3, x1, x4) + +inst_6320: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xbc00; +op3val:0x400; valaddr_reg:x2; val_offset:18858*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18858*FLEN/8, x3, x1, x4) + +inst_6321: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xbc00; +op3val:0x8400; valaddr_reg:x2; val_offset:18861*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18861*FLEN/8, x3, x1, x4) + +inst_6322: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xbc00; +op3val:0x401; valaddr_reg:x2; val_offset:18864*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18864*FLEN/8, x3, x1, x4) + +inst_6323: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xbc00; +op3val:0x8455; valaddr_reg:x2; val_offset:18867*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18867*FLEN/8, x3, x1, x4) + +inst_6324: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xbc00; +op3val:0x7bff; valaddr_reg:x2; val_offset:18870*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18870*FLEN/8, x3, x1, x4) + +inst_6325: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xbc00; +op3val:0xfbff; valaddr_reg:x2; val_offset:18873*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18873*FLEN/8, x3, x1, x4) + +inst_6326: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xbc00; +op3val:0x7c00; valaddr_reg:x2; val_offset:18876*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18876*FLEN/8, x3, x1, x4) + +inst_6327: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xbc00; +op3val:0xfc00; valaddr_reg:x2; val_offset:18879*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18879*FLEN/8, x3, x1, x4) + +inst_6328: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xbc00; +op3val:0x7e00; valaddr_reg:x2; val_offset:18882*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18882*FLEN/8, x3, x1, x4) + +inst_6329: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xbc00; +op3val:0xfe00; valaddr_reg:x2; val_offset:18885*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18885*FLEN/8, x3, x1, x4) + +inst_6330: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xbc00; +op3val:0x7e01; valaddr_reg:x2; val_offset:18888*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18888*FLEN/8, x3, x1, x4) + +inst_6331: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xbc00; +op3val:0xfe55; valaddr_reg:x2; val_offset:18891*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18891*FLEN/8, x3, x1, x4) + +inst_6332: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xbc00; +op3val:0x7c01; valaddr_reg:x2; val_offset:18894*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18894*FLEN/8, x3, x1, x4) + +inst_6333: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xbc00; +op3val:0xfd55; valaddr_reg:x2; val_offset:18897*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18897*FLEN/8, x3, x1, x4) + +inst_6334: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xbc00; +op3val:0x3c00; valaddr_reg:x2; val_offset:18900*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18900*FLEN/8, x3, x1, x4) + +inst_6335: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xbc00; +op3val:0xbc00; valaddr_reg:x2; val_offset:18903*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18903*FLEN/8, x3, x1, x4) + +inst_6336: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x0; +op3val:0x0; valaddr_reg:x2; val_offset:18906*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18906*FLEN/8, x3, x1, x4) + +inst_6337: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x0; +op3val:0x8000; valaddr_reg:x2; val_offset:18909*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18909*FLEN/8, x3, x1, x4) + +inst_6338: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x0; +op3val:0x1; valaddr_reg:x2; val_offset:18912*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18912*FLEN/8, x3, x1, x4) + +inst_6339: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x0; +op3val:0x8001; valaddr_reg:x2; val_offset:18915*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18915*FLEN/8, x3, x1, x4) + +inst_6340: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x0; +op3val:0x2; valaddr_reg:x2; val_offset:18918*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18918*FLEN/8, x3, x1, x4) + +inst_6341: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x0; +op3val:0x83fe; valaddr_reg:x2; val_offset:18921*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18921*FLEN/8, x3, x1, x4) + +inst_6342: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x0; +op3val:0x3ff; valaddr_reg:x2; val_offset:18924*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18924*FLEN/8, x3, x1, x4) + +inst_6343: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x0; +op3val:0x83ff; valaddr_reg:x2; val_offset:18927*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18927*FLEN/8, x3, x1, x4) + +inst_6344: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x0; +op3val:0x400; valaddr_reg:x2; val_offset:18930*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18930*FLEN/8, x3, x1, x4) + +inst_6345: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x0; +op3val:0x8400; valaddr_reg:x2; val_offset:18933*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18933*FLEN/8, x3, x1, x4) + +inst_6346: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x0; +op3val:0x401; valaddr_reg:x2; val_offset:18936*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18936*FLEN/8, x3, x1, x4) + +inst_6347: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x0; +op3val:0x8455; valaddr_reg:x2; val_offset:18939*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18939*FLEN/8, x3, x1, x4) + +inst_6348: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x0; +op3val:0x7bff; valaddr_reg:x2; val_offset:18942*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18942*FLEN/8, x3, x1, x4) + +inst_6349: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x0; +op3val:0xfbff; valaddr_reg:x2; val_offset:18945*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18945*FLEN/8, x3, x1, x4) + +inst_6350: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x0; +op3val:0x7c00; valaddr_reg:x2; val_offset:18948*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18948*FLEN/8, x3, x1, x4) + +inst_6351: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x0; +op3val:0xfc00; valaddr_reg:x2; val_offset:18951*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18951*FLEN/8, x3, x1, x4) + +inst_6352: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x0; +op3val:0x7e00; valaddr_reg:x2; val_offset:18954*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18954*FLEN/8, x3, x1, x4) + +inst_6353: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x0; +op3val:0xfe00; valaddr_reg:x2; val_offset:18957*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18957*FLEN/8, x3, x1, x4) + +inst_6354: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x0; +op3val:0x7e01; valaddr_reg:x2; val_offset:18960*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18960*FLEN/8, x3, x1, x4) + +inst_6355: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x0; +op3val:0xfe55; valaddr_reg:x2; val_offset:18963*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18963*FLEN/8, x3, x1, x4) + +inst_6356: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x0; +op3val:0x7c01; valaddr_reg:x2; val_offset:18966*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18966*FLEN/8, x3, x1, x4) + +inst_6357: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x0; +op3val:0xfd55; valaddr_reg:x2; val_offset:18969*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18969*FLEN/8, x3, x1, x4) + +inst_6358: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x0; +op3val:0x3c00; valaddr_reg:x2; val_offset:18972*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18972*FLEN/8, x3, x1, x4) + +inst_6359: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x0; +op3val:0xbc00; valaddr_reg:x2; val_offset:18975*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18975*FLEN/8, x3, x1, x4) + +inst_6360: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8000; +op3val:0x0; valaddr_reg:x2; val_offset:18978*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18978*FLEN/8, x3, x1, x4) + +inst_6361: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8000; +op3val:0x8000; valaddr_reg:x2; val_offset:18981*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18981*FLEN/8, x3, x1, x4) + +inst_6362: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8000; +op3val:0x1; valaddr_reg:x2; val_offset:18984*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18984*FLEN/8, x3, x1, x4) + +inst_6363: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8000; +op3val:0x8001; valaddr_reg:x2; val_offset:18987*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18987*FLEN/8, x3, x1, x4) + +inst_6364: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8000; +op3val:0x2; valaddr_reg:x2; val_offset:18990*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18990*FLEN/8, x3, x1, x4) + +inst_6365: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8000; +op3val:0x83fe; valaddr_reg:x2; val_offset:18993*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18993*FLEN/8, x3, x1, x4) + +inst_6366: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8000; +op3val:0x3ff; valaddr_reg:x2; val_offset:18996*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18996*FLEN/8, x3, x1, x4) + +inst_6367: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8000; +op3val:0x83ff; valaddr_reg:x2; val_offset:18999*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18999*FLEN/8, x3, x1, x4) + +inst_6368: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8000; +op3val:0x400; valaddr_reg:x2; val_offset:19002*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19002*FLEN/8, x3, x1, x4) + +inst_6369: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8000; +op3val:0x8400; valaddr_reg:x2; val_offset:19005*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19005*FLEN/8, x3, x1, x4) + +inst_6370: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8000; +op3val:0x401; valaddr_reg:x2; val_offset:19008*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19008*FLEN/8, x3, x1, x4) + +inst_6371: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8000; +op3val:0x8455; valaddr_reg:x2; val_offset:19011*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19011*FLEN/8, x3, x1, x4) + +inst_6372: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x2; val_offset:19014*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19014*FLEN/8, x3, x1, x4) + +inst_6373: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x2; val_offset:19017*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19017*FLEN/8, x3, x1, x4) + +inst_6374: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8000; +op3val:0x7c00; valaddr_reg:x2; val_offset:19020*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19020*FLEN/8, x3, x1, x4) + +inst_6375: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8000; +op3val:0xfc00; valaddr_reg:x2; val_offset:19023*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19023*FLEN/8, x3, x1, x4) + +inst_6376: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8000; +op3val:0x7e00; valaddr_reg:x2; val_offset:19026*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19026*FLEN/8, x3, x1, x4) + +inst_6377: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8000; +op3val:0xfe00; valaddr_reg:x2; val_offset:19029*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19029*FLEN/8, x3, x1, x4) + +inst_6378: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8000; +op3val:0x7e01; valaddr_reg:x2; val_offset:19032*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19032*FLEN/8, x3, x1, x4) + +inst_6379: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8000; +op3val:0xfe55; valaddr_reg:x2; val_offset:19035*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19035*FLEN/8, x3, x1, x4) + +inst_6380: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8000; +op3val:0x7c01; valaddr_reg:x2; val_offset:19038*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19038*FLEN/8, x3, x1, x4) + +inst_6381: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8000; +op3val:0xfd55; valaddr_reg:x2; val_offset:19041*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19041*FLEN/8, x3, x1, x4) + +inst_6382: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8000; +op3val:0x3c00; valaddr_reg:x2; val_offset:19044*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19044*FLEN/8, x3, x1, x4) + +inst_6383: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8000; +op3val:0xbc00; valaddr_reg:x2; val_offset:19047*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19047*FLEN/8, x3, x1, x4) + +inst_6384: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x1; +op3val:0x0; valaddr_reg:x2; val_offset:19050*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19050*FLEN/8, x3, x1, x4) + +inst_6385: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x1; +op3val:0x8000; valaddr_reg:x2; val_offset:19053*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19053*FLEN/8, x3, x1, x4) + +inst_6386: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x1; +op3val:0x1; valaddr_reg:x2; val_offset:19056*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19056*FLEN/8, x3, x1, x4) + +inst_6387: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x1; +op3val:0x8001; valaddr_reg:x2; val_offset:19059*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19059*FLEN/8, x3, x1, x4) + +inst_6388: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x1; +op3val:0x2; valaddr_reg:x2; val_offset:19062*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19062*FLEN/8, x3, x1, x4) + +inst_6389: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x1; +op3val:0x83fe; valaddr_reg:x2; val_offset:19065*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19065*FLEN/8, x3, x1, x4) + +inst_6390: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x1; +op3val:0x3ff; valaddr_reg:x2; val_offset:19068*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19068*FLEN/8, x3, x1, x4) + +inst_6391: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x1; +op3val:0x83ff; valaddr_reg:x2; val_offset:19071*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19071*FLEN/8, x3, x1, x4) + +inst_6392: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x1; +op3val:0x400; valaddr_reg:x2; val_offset:19074*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19074*FLEN/8, x3, x1, x4) + +inst_6393: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x1; +op3val:0x8400; valaddr_reg:x2; val_offset:19077*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19077*FLEN/8, x3, x1, x4) + +inst_6394: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x1; +op3val:0x401; valaddr_reg:x2; val_offset:19080*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19080*FLEN/8, x3, x1, x4) + +inst_6395: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x1; +op3val:0x8455; valaddr_reg:x2; val_offset:19083*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19083*FLEN/8, x3, x1, x4) + +inst_6396: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x1; +op3val:0x7bff; valaddr_reg:x2; val_offset:19086*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19086*FLEN/8, x3, x1, x4) + +inst_6397: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x1; +op3val:0xfbff; valaddr_reg:x2; val_offset:19089*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19089*FLEN/8, x3, x1, x4) + +inst_6398: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x1; +op3val:0x7c00; valaddr_reg:x2; val_offset:19092*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19092*FLEN/8, x3, x1, x4) + +inst_6399: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x1; +op3val:0xfc00; valaddr_reg:x2; val_offset:19095*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19095*FLEN/8, x3, x1, x4) + +inst_6400: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x1; +op3val:0x7e00; valaddr_reg:x2; val_offset:19098*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19098*FLEN/8, x3, x1, x4) + +inst_6401: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x1; +op3val:0xfe00; valaddr_reg:x2; val_offset:19101*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19101*FLEN/8, x3, x1, x4) + +inst_6402: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x1; +op3val:0x7e01; valaddr_reg:x2; val_offset:19104*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19104*FLEN/8, x3, x1, x4) + +inst_6403: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x1; +op3val:0xfe55; valaddr_reg:x2; val_offset:19107*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19107*FLEN/8, x3, x1, x4) + +inst_6404: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x1; +op3val:0x7c01; valaddr_reg:x2; val_offset:19110*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19110*FLEN/8, x3, x1, x4) + +inst_6405: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x1; +op3val:0xfd55; valaddr_reg:x2; val_offset:19113*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19113*FLEN/8, x3, x1, x4) + +inst_6406: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x1; +op3val:0x3c00; valaddr_reg:x2; val_offset:19116*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19116*FLEN/8, x3, x1, x4) + +inst_6407: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x1; +op3val:0xbc00; valaddr_reg:x2; val_offset:19119*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19119*FLEN/8, x3, x1, x4) + +inst_6408: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8001; +op3val:0x0; valaddr_reg:x2; val_offset:19122*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19122*FLEN/8, x3, x1, x4) + +inst_6409: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8001; +op3val:0x8000; valaddr_reg:x2; val_offset:19125*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19125*FLEN/8, x3, x1, x4) + +inst_6410: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8001; +op3val:0x1; valaddr_reg:x2; val_offset:19128*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19128*FLEN/8, x3, x1, x4) + +inst_6411: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8001; +op3val:0x8001; valaddr_reg:x2; val_offset:19131*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19131*FLEN/8, x3, x1, x4) + +inst_6412: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8001; +op3val:0x2; valaddr_reg:x2; val_offset:19134*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19134*FLEN/8, x3, x1, x4) + +inst_6413: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8001; +op3val:0x83fe; valaddr_reg:x2; val_offset:19137*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19137*FLEN/8, x3, x1, x4) + +inst_6414: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8001; +op3val:0x3ff; valaddr_reg:x2; val_offset:19140*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19140*FLEN/8, x3, x1, x4) + +inst_6415: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8001; +op3val:0x83ff; valaddr_reg:x2; val_offset:19143*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19143*FLEN/8, x3, x1, x4) + +inst_6416: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8001; +op3val:0x400; valaddr_reg:x2; val_offset:19146*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19146*FLEN/8, x3, x1, x4) + +inst_6417: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8001; +op3val:0x8400; valaddr_reg:x2; val_offset:19149*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19149*FLEN/8, x3, x1, x4) + +inst_6418: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8001; +op3val:0x401; valaddr_reg:x2; val_offset:19152*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19152*FLEN/8, x3, x1, x4) + +inst_6419: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8001; +op3val:0x8455; valaddr_reg:x2; val_offset:19155*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19155*FLEN/8, x3, x1, x4) + +inst_6420: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8001; +op3val:0x7bff; valaddr_reg:x2; val_offset:19158*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19158*FLEN/8, x3, x1, x4) + +inst_6421: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8001; +op3val:0xfbff; valaddr_reg:x2; val_offset:19161*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19161*FLEN/8, x3, x1, x4) + +inst_6422: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8001; +op3val:0x7c00; valaddr_reg:x2; val_offset:19164*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19164*FLEN/8, x3, x1, x4) + +inst_6423: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8001; +op3val:0xfc00; valaddr_reg:x2; val_offset:19167*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19167*FLEN/8, x3, x1, x4) + +inst_6424: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8001; +op3val:0x7e00; valaddr_reg:x2; val_offset:19170*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19170*FLEN/8, x3, x1, x4) + +inst_6425: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8001; +op3val:0xfe00; valaddr_reg:x2; val_offset:19173*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19173*FLEN/8, x3, x1, x4) + +inst_6426: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8001; +op3val:0x7e01; valaddr_reg:x2; val_offset:19176*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19176*FLEN/8, x3, x1, x4) + +inst_6427: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8001; +op3val:0xfe55; valaddr_reg:x2; val_offset:19179*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19179*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_51) + +inst_6428: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8001; +op3val:0x7c01; valaddr_reg:x2; val_offset:19182*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19182*FLEN/8, x3, x1, x4) + +inst_6429: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8001; +op3val:0xfd55; valaddr_reg:x2; val_offset:19185*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19185*FLEN/8, x3, x1, x4) + +inst_6430: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8001; +op3val:0x3c00; valaddr_reg:x2; val_offset:19188*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19188*FLEN/8, x3, x1, x4) + +inst_6431: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8001; +op3val:0xbc00; valaddr_reg:x2; val_offset:19191*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19191*FLEN/8, x3, x1, x4) + +inst_6432: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x2; +op3val:0x0; valaddr_reg:x2; val_offset:19194*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19194*FLEN/8, x3, x1, x4) + +inst_6433: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x2; +op3val:0x8000; valaddr_reg:x2; val_offset:19197*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19197*FLEN/8, x3, x1, x4) + +inst_6434: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x2; +op3val:0x1; valaddr_reg:x2; val_offset:19200*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19200*FLEN/8, x3, x1, x4) + +inst_6435: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x2; +op3val:0x8001; valaddr_reg:x2; val_offset:19203*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19203*FLEN/8, x3, x1, x4) + +inst_6436: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x2; +op3val:0x2; valaddr_reg:x2; val_offset:19206*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19206*FLEN/8, x3, x1, x4) + +inst_6437: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x2; +op3val:0x83fe; valaddr_reg:x2; val_offset:19209*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19209*FLEN/8, x3, x1, x4) + +inst_6438: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x2; +op3val:0x3ff; valaddr_reg:x2; val_offset:19212*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19212*FLEN/8, x3, x1, x4) + +inst_6439: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x2; +op3val:0x83ff; valaddr_reg:x2; val_offset:19215*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19215*FLEN/8, x3, x1, x4) + +inst_6440: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x2; +op3val:0x400; valaddr_reg:x2; val_offset:19218*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19218*FLEN/8, x3, x1, x4) + +inst_6441: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x2; +op3val:0x8400; valaddr_reg:x2; val_offset:19221*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19221*FLEN/8, x3, x1, x4) + +inst_6442: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x2; +op3val:0x401; valaddr_reg:x2; val_offset:19224*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19224*FLEN/8, x3, x1, x4) + +inst_6443: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x2; +op3val:0x8455; valaddr_reg:x2; val_offset:19227*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19227*FLEN/8, x3, x1, x4) + +inst_6444: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x2; +op3val:0x7bff; valaddr_reg:x2; val_offset:19230*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19230*FLEN/8, x3, x1, x4) + +inst_6445: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x2; +op3val:0xfbff; valaddr_reg:x2; val_offset:19233*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19233*FLEN/8, x3, x1, x4) + +inst_6446: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x2; +op3val:0x7c00; valaddr_reg:x2; val_offset:19236*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19236*FLEN/8, x3, x1, x4) + +inst_6447: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x2; +op3val:0xfc00; valaddr_reg:x2; val_offset:19239*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19239*FLEN/8, x3, x1, x4) + +inst_6448: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x2; +op3val:0x7e00; valaddr_reg:x2; val_offset:19242*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19242*FLEN/8, x3, x1, x4) + +inst_6449: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x2; +op3val:0xfe00; valaddr_reg:x2; val_offset:19245*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19245*FLEN/8, x3, x1, x4) + +inst_6450: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x2; +op3val:0x7e01; valaddr_reg:x2; val_offset:19248*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19248*FLEN/8, x3, x1, x4) + +inst_6451: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x2; +op3val:0xfe55; valaddr_reg:x2; val_offset:19251*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19251*FLEN/8, x3, x1, x4) + +inst_6452: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x2; +op3val:0x7c01; valaddr_reg:x2; val_offset:19254*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19254*FLEN/8, x3, x1, x4) + +inst_6453: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x2; +op3val:0xfd55; valaddr_reg:x2; val_offset:19257*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19257*FLEN/8, x3, x1, x4) + +inst_6454: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x2; +op3val:0x3c00; valaddr_reg:x2; val_offset:19260*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19260*FLEN/8, x3, x1, x4) + +inst_6455: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x2; +op3val:0xbc00; valaddr_reg:x2; val_offset:19263*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19263*FLEN/8, x3, x1, x4) + +inst_6456: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x83fe; +op3val:0x0; valaddr_reg:x2; val_offset:19266*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19266*FLEN/8, x3, x1, x4) + +inst_6457: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x83fe; +op3val:0x8000; valaddr_reg:x2; val_offset:19269*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19269*FLEN/8, x3, x1, x4) + +inst_6458: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x83fe; +op3val:0x1; valaddr_reg:x2; val_offset:19272*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19272*FLEN/8, x3, x1, x4) + +inst_6459: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x83fe; +op3val:0x8001; valaddr_reg:x2; val_offset:19275*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19275*FLEN/8, x3, x1, x4) + +inst_6460: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x83fe; +op3val:0x2; valaddr_reg:x2; val_offset:19278*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19278*FLEN/8, x3, x1, x4) + +inst_6461: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x83fe; +op3val:0x83fe; valaddr_reg:x2; val_offset:19281*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19281*FLEN/8, x3, x1, x4) + +inst_6462: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x83fe; +op3val:0x3ff; valaddr_reg:x2; val_offset:19284*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19284*FLEN/8, x3, x1, x4) + +inst_6463: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x83fe; +op3val:0x83ff; valaddr_reg:x2; val_offset:19287*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19287*FLEN/8, x3, x1, x4) + +inst_6464: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x83fe; +op3val:0x400; valaddr_reg:x2; val_offset:19290*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19290*FLEN/8, x3, x1, x4) + +inst_6465: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x83fe; +op3val:0x8400; valaddr_reg:x2; val_offset:19293*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19293*FLEN/8, x3, x1, x4) + +inst_6466: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x83fe; +op3val:0x401; valaddr_reg:x2; val_offset:19296*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19296*FLEN/8, x3, x1, x4) + +inst_6467: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x83fe; +op3val:0x8455; valaddr_reg:x2; val_offset:19299*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19299*FLEN/8, x3, x1, x4) + +inst_6468: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x83fe; +op3val:0x7bff; valaddr_reg:x2; val_offset:19302*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19302*FLEN/8, x3, x1, x4) + +inst_6469: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x83fe; +op3val:0xfbff; valaddr_reg:x2; val_offset:19305*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19305*FLEN/8, x3, x1, x4) + +inst_6470: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x83fe; +op3val:0x7c00; valaddr_reg:x2; val_offset:19308*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19308*FLEN/8, x3, x1, x4) + +inst_6471: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x83fe; +op3val:0xfc00; valaddr_reg:x2; val_offset:19311*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19311*FLEN/8, x3, x1, x4) + +inst_6472: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x83fe; +op3val:0x7e00; valaddr_reg:x2; val_offset:19314*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19314*FLEN/8, x3, x1, x4) + +inst_6473: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x83fe; +op3val:0xfe00; valaddr_reg:x2; val_offset:19317*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19317*FLEN/8, x3, x1, x4) + +inst_6474: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x83fe; +op3val:0x7e01; valaddr_reg:x2; val_offset:19320*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19320*FLEN/8, x3, x1, x4) + +inst_6475: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x83fe; +op3val:0xfe55; valaddr_reg:x2; val_offset:19323*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19323*FLEN/8, x3, x1, x4) + +inst_6476: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x83fe; +op3val:0x7c01; valaddr_reg:x2; val_offset:19326*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19326*FLEN/8, x3, x1, x4) + +inst_6477: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x83fe; +op3val:0xfd55; valaddr_reg:x2; val_offset:19329*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19329*FLEN/8, x3, x1, x4) + +inst_6478: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x83fe; +op3val:0x3c00; valaddr_reg:x2; val_offset:19332*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19332*FLEN/8, x3, x1, x4) + +inst_6479: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x83fe; +op3val:0xbc00; valaddr_reg:x2; val_offset:19335*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19335*FLEN/8, x3, x1, x4) + +inst_6480: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x3ff; +op3val:0x0; valaddr_reg:x2; val_offset:19338*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19338*FLEN/8, x3, x1, x4) + +inst_6481: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x3ff; +op3val:0x8000; valaddr_reg:x2; val_offset:19341*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19341*FLEN/8, x3, x1, x4) + +inst_6482: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x3ff; +op3val:0x1; valaddr_reg:x2; val_offset:19344*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19344*FLEN/8, x3, x1, x4) + +inst_6483: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x3ff; +op3val:0x8001; valaddr_reg:x2; val_offset:19347*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19347*FLEN/8, x3, x1, x4) + +inst_6484: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x3ff; +op3val:0x2; valaddr_reg:x2; val_offset:19350*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19350*FLEN/8, x3, x1, x4) + +inst_6485: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x3ff; +op3val:0x83fe; valaddr_reg:x2; val_offset:19353*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19353*FLEN/8, x3, x1, x4) + +inst_6486: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x3ff; +op3val:0x3ff; valaddr_reg:x2; val_offset:19356*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19356*FLEN/8, x3, x1, x4) + +inst_6487: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x3ff; +op3val:0x83ff; valaddr_reg:x2; val_offset:19359*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19359*FLEN/8, x3, x1, x4) + +inst_6488: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x3ff; +op3val:0x400; valaddr_reg:x2; val_offset:19362*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19362*FLEN/8, x3, x1, x4) + +inst_6489: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x3ff; +op3val:0x8400; valaddr_reg:x2; val_offset:19365*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19365*FLEN/8, x3, x1, x4) + +inst_6490: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x3ff; +op3val:0x401; valaddr_reg:x2; val_offset:19368*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19368*FLEN/8, x3, x1, x4) + +inst_6491: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x3ff; +op3val:0x8455; valaddr_reg:x2; val_offset:19371*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19371*FLEN/8, x3, x1, x4) + +inst_6492: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x3ff; +op3val:0x7bff; valaddr_reg:x2; val_offset:19374*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19374*FLEN/8, x3, x1, x4) + +inst_6493: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x3ff; +op3val:0xfbff; valaddr_reg:x2; val_offset:19377*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19377*FLEN/8, x3, x1, x4) + +inst_6494: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x3ff; +op3val:0x7c00; valaddr_reg:x2; val_offset:19380*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19380*FLEN/8, x3, x1, x4) + +inst_6495: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x3ff; +op3val:0xfc00; valaddr_reg:x2; val_offset:19383*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19383*FLEN/8, x3, x1, x4) + +inst_6496: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x3ff; +op3val:0x7e00; valaddr_reg:x2; val_offset:19386*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19386*FLEN/8, x3, x1, x4) + +inst_6497: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x3ff; +op3val:0xfe00; valaddr_reg:x2; val_offset:19389*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19389*FLEN/8, x3, x1, x4) + +inst_6498: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x3ff; +op3val:0x7e01; valaddr_reg:x2; val_offset:19392*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19392*FLEN/8, x3, x1, x4) + +inst_6499: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x3ff; +op3val:0xfe55; valaddr_reg:x2; val_offset:19395*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19395*FLEN/8, x3, x1, x4) + +inst_6500: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x3ff; +op3val:0x7c01; valaddr_reg:x2; val_offset:19398*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19398*FLEN/8, x3, x1, x4) + +inst_6501: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x3ff; +op3val:0xfd55; valaddr_reg:x2; val_offset:19401*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19401*FLEN/8, x3, x1, x4) + +inst_6502: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x3ff; +op3val:0x3c00; valaddr_reg:x2; val_offset:19404*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19404*FLEN/8, x3, x1, x4) + +inst_6503: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x3ff; +op3val:0xbc00; valaddr_reg:x2; val_offset:19407*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19407*FLEN/8, x3, x1, x4) + +inst_6504: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x83ff; +op3val:0x0; valaddr_reg:x2; val_offset:19410*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19410*FLEN/8, x3, x1, x4) + +inst_6505: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x83ff; +op3val:0x8000; valaddr_reg:x2; val_offset:19413*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19413*FLEN/8, x3, x1, x4) + +inst_6506: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x83ff; +op3val:0x1; valaddr_reg:x2; val_offset:19416*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19416*FLEN/8, x3, x1, x4) + +inst_6507: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x83ff; +op3val:0x8001; valaddr_reg:x2; val_offset:19419*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19419*FLEN/8, x3, x1, x4) + +inst_6508: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x83ff; +op3val:0x2; valaddr_reg:x2; val_offset:19422*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19422*FLEN/8, x3, x1, x4) + +inst_6509: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x83ff; +op3val:0x83fe; valaddr_reg:x2; val_offset:19425*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19425*FLEN/8, x3, x1, x4) + +inst_6510: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x83ff; +op3val:0x3ff; valaddr_reg:x2; val_offset:19428*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19428*FLEN/8, x3, x1, x4) + +inst_6511: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x83ff; +op3val:0x83ff; valaddr_reg:x2; val_offset:19431*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19431*FLEN/8, x3, x1, x4) + +inst_6512: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x83ff; +op3val:0x400; valaddr_reg:x2; val_offset:19434*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19434*FLEN/8, x3, x1, x4) + +inst_6513: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x83ff; +op3val:0x8400; valaddr_reg:x2; val_offset:19437*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19437*FLEN/8, x3, x1, x4) + +inst_6514: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x83ff; +op3val:0x401; valaddr_reg:x2; val_offset:19440*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19440*FLEN/8, x3, x1, x4) + +inst_6515: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x83ff; +op3val:0x8455; valaddr_reg:x2; val_offset:19443*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19443*FLEN/8, x3, x1, x4) + +inst_6516: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x83ff; +op3val:0x7bff; valaddr_reg:x2; val_offset:19446*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19446*FLEN/8, x3, x1, x4) + +inst_6517: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x83ff; +op3val:0xfbff; valaddr_reg:x2; val_offset:19449*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19449*FLEN/8, x3, x1, x4) + +inst_6518: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x83ff; +op3val:0x7c00; valaddr_reg:x2; val_offset:19452*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19452*FLEN/8, x3, x1, x4) + +inst_6519: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x83ff; +op3val:0xfc00; valaddr_reg:x2; val_offset:19455*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19455*FLEN/8, x3, x1, x4) + +inst_6520: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x83ff; +op3val:0x7e00; valaddr_reg:x2; val_offset:19458*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19458*FLEN/8, x3, x1, x4) + +inst_6521: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x83ff; +op3val:0xfe00; valaddr_reg:x2; val_offset:19461*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19461*FLEN/8, x3, x1, x4) + +inst_6522: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x83ff; +op3val:0x7e01; valaddr_reg:x2; val_offset:19464*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19464*FLEN/8, x3, x1, x4) + +inst_6523: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x83ff; +op3val:0xfe55; valaddr_reg:x2; val_offset:19467*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19467*FLEN/8, x3, x1, x4) + +inst_6524: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x83ff; +op3val:0x7c01; valaddr_reg:x2; val_offset:19470*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19470*FLEN/8, x3, x1, x4) + +inst_6525: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x83ff; +op3val:0xfd55; valaddr_reg:x2; val_offset:19473*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19473*FLEN/8, x3, x1, x4) + +inst_6526: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x83ff; +op3val:0x3c00; valaddr_reg:x2; val_offset:19476*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19476*FLEN/8, x3, x1, x4) + +inst_6527: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x83ff; +op3val:0xbc00; valaddr_reg:x2; val_offset:19479*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19479*FLEN/8, x3, x1, x4) + +inst_6528: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x400; +op3val:0x0; valaddr_reg:x2; val_offset:19482*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19482*FLEN/8, x3, x1, x4) + +inst_6529: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x400; +op3val:0x8000; valaddr_reg:x2; val_offset:19485*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19485*FLEN/8, x3, x1, x4) + +inst_6530: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x400; +op3val:0x1; valaddr_reg:x2; val_offset:19488*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19488*FLEN/8, x3, x1, x4) + +inst_6531: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x400; +op3val:0x8001; valaddr_reg:x2; val_offset:19491*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19491*FLEN/8, x3, x1, x4) + +inst_6532: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x400; +op3val:0x2; valaddr_reg:x2; val_offset:19494*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19494*FLEN/8, x3, x1, x4) + +inst_6533: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x400; +op3val:0x83fe; valaddr_reg:x2; val_offset:19497*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19497*FLEN/8, x3, x1, x4) + +inst_6534: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x400; +op3val:0x3ff; valaddr_reg:x2; val_offset:19500*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19500*FLEN/8, x3, x1, x4) + +inst_6535: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x400; +op3val:0x83ff; valaddr_reg:x2; val_offset:19503*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19503*FLEN/8, x3, x1, x4) + +inst_6536: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x400; +op3val:0x400; valaddr_reg:x2; val_offset:19506*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19506*FLEN/8, x3, x1, x4) + +inst_6537: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x400; +op3val:0x8400; valaddr_reg:x2; val_offset:19509*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19509*FLEN/8, x3, x1, x4) + +inst_6538: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x400; +op3val:0x401; valaddr_reg:x2; val_offset:19512*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19512*FLEN/8, x3, x1, x4) + +inst_6539: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x400; +op3val:0x8455; valaddr_reg:x2; val_offset:19515*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19515*FLEN/8, x3, x1, x4) + +inst_6540: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x400; +op3val:0x7bff; valaddr_reg:x2; val_offset:19518*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19518*FLEN/8, x3, x1, x4) + +inst_6541: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x400; +op3val:0xfbff; valaddr_reg:x2; val_offset:19521*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19521*FLEN/8, x3, x1, x4) + +inst_6542: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x400; +op3val:0x7c00; valaddr_reg:x2; val_offset:19524*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19524*FLEN/8, x3, x1, x4) + +inst_6543: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x400; +op3val:0xfc00; valaddr_reg:x2; val_offset:19527*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19527*FLEN/8, x3, x1, x4) + +inst_6544: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x400; +op3val:0x7e00; valaddr_reg:x2; val_offset:19530*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19530*FLEN/8, x3, x1, x4) + +inst_6545: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x400; +op3val:0xfe00; valaddr_reg:x2; val_offset:19533*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19533*FLEN/8, x3, x1, x4) + +inst_6546: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x400; +op3val:0x7e01; valaddr_reg:x2; val_offset:19536*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19536*FLEN/8, x3, x1, x4) + +inst_6547: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x400; +op3val:0xfe55; valaddr_reg:x2; val_offset:19539*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19539*FLEN/8, x3, x1, x4) + +inst_6548: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x400; +op3val:0x7c01; valaddr_reg:x2; val_offset:19542*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19542*FLEN/8, x3, x1, x4) + +inst_6549: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x400; +op3val:0xfd55; valaddr_reg:x2; val_offset:19545*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19545*FLEN/8, x3, x1, x4) + +inst_6550: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x400; +op3val:0x3c00; valaddr_reg:x2; val_offset:19548*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19548*FLEN/8, x3, x1, x4) + +inst_6551: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x400; +op3val:0xbc00; valaddr_reg:x2; val_offset:19551*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19551*FLEN/8, x3, x1, x4) + +inst_6552: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8400; +op3val:0x0; valaddr_reg:x2; val_offset:19554*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19554*FLEN/8, x3, x1, x4) + +inst_6553: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8400; +op3val:0x8000; valaddr_reg:x2; val_offset:19557*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19557*FLEN/8, x3, x1, x4) + +inst_6554: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8400; +op3val:0x1; valaddr_reg:x2; val_offset:19560*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19560*FLEN/8, x3, x1, x4) + +inst_6555: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8400; +op3val:0x8001; valaddr_reg:x2; val_offset:19563*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19563*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_52) + +inst_6556: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8400; +op3val:0x2; valaddr_reg:x2; val_offset:19566*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19566*FLEN/8, x3, x1, x4) + +inst_6557: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8400; +op3val:0x83fe; valaddr_reg:x2; val_offset:19569*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19569*FLEN/8, x3, x1, x4) + +inst_6558: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8400; +op3val:0x3ff; valaddr_reg:x2; val_offset:19572*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19572*FLEN/8, x3, x1, x4) + +inst_6559: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8400; +op3val:0x83ff; valaddr_reg:x2; val_offset:19575*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19575*FLEN/8, x3, x1, x4) + +inst_6560: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8400; +op3val:0x400; valaddr_reg:x2; val_offset:19578*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19578*FLEN/8, x3, x1, x4) + +inst_6561: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8400; +op3val:0x8400; valaddr_reg:x2; val_offset:19581*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19581*FLEN/8, x3, x1, x4) + +inst_6562: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8400; +op3val:0x401; valaddr_reg:x2; val_offset:19584*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19584*FLEN/8, x3, x1, x4) + +inst_6563: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8400; +op3val:0x8455; valaddr_reg:x2; val_offset:19587*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19587*FLEN/8, x3, x1, x4) + +inst_6564: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8400; +op3val:0x7bff; valaddr_reg:x2; val_offset:19590*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19590*FLEN/8, x3, x1, x4) + +inst_6565: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8400; +op3val:0xfbff; valaddr_reg:x2; val_offset:19593*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19593*FLEN/8, x3, x1, x4) + +inst_6566: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8400; +op3val:0x7c00; valaddr_reg:x2; val_offset:19596*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19596*FLEN/8, x3, x1, x4) + +inst_6567: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8400; +op3val:0xfc00; valaddr_reg:x2; val_offset:19599*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19599*FLEN/8, x3, x1, x4) + +inst_6568: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8400; +op3val:0x7e00; valaddr_reg:x2; val_offset:19602*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19602*FLEN/8, x3, x1, x4) + +inst_6569: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8400; +op3val:0xfe00; valaddr_reg:x2; val_offset:19605*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19605*FLEN/8, x3, x1, x4) + +inst_6570: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8400; +op3val:0x7e01; valaddr_reg:x2; val_offset:19608*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19608*FLEN/8, x3, x1, x4) + +inst_6571: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8400; +op3val:0xfe55; valaddr_reg:x2; val_offset:19611*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19611*FLEN/8, x3, x1, x4) + +inst_6572: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8400; +op3val:0x7c01; valaddr_reg:x2; val_offset:19614*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19614*FLEN/8, x3, x1, x4) + +inst_6573: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8400; +op3val:0xfd55; valaddr_reg:x2; val_offset:19617*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19617*FLEN/8, x3, x1, x4) + +inst_6574: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8400; +op3val:0x3c00; valaddr_reg:x2; val_offset:19620*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19620*FLEN/8, x3, x1, x4) + +inst_6575: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8400; +op3val:0xbc00; valaddr_reg:x2; val_offset:19623*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19623*FLEN/8, x3, x1, x4) + +inst_6576: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x401; +op3val:0x0; valaddr_reg:x2; val_offset:19626*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19626*FLEN/8, x3, x1, x4) + +inst_6577: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x401; +op3val:0x8000; valaddr_reg:x2; val_offset:19629*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19629*FLEN/8, x3, x1, x4) + +inst_6578: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x401; +op3val:0x1; valaddr_reg:x2; val_offset:19632*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19632*FLEN/8, x3, x1, x4) + +inst_6579: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x401; +op3val:0x8001; valaddr_reg:x2; val_offset:19635*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19635*FLEN/8, x3, x1, x4) + +inst_6580: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x401; +op3val:0x2; valaddr_reg:x2; val_offset:19638*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19638*FLEN/8, x3, x1, x4) + +inst_6581: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x401; +op3val:0x83fe; valaddr_reg:x2; val_offset:19641*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19641*FLEN/8, x3, x1, x4) + +inst_6582: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x401; +op3val:0x3ff; valaddr_reg:x2; val_offset:19644*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19644*FLEN/8, x3, x1, x4) + +inst_6583: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x401; +op3val:0x83ff; valaddr_reg:x2; val_offset:19647*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19647*FLEN/8, x3, x1, x4) + +inst_6584: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x401; +op3val:0x400; valaddr_reg:x2; val_offset:19650*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19650*FLEN/8, x3, x1, x4) + +inst_6585: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x401; +op3val:0x8400; valaddr_reg:x2; val_offset:19653*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19653*FLEN/8, x3, x1, x4) + +inst_6586: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x401; +op3val:0x401; valaddr_reg:x2; val_offset:19656*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19656*FLEN/8, x3, x1, x4) + +inst_6587: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x401; +op3val:0x8455; valaddr_reg:x2; val_offset:19659*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19659*FLEN/8, x3, x1, x4) + +inst_6588: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x401; +op3val:0x7bff; valaddr_reg:x2; val_offset:19662*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19662*FLEN/8, x3, x1, x4) + +inst_6589: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x401; +op3val:0xfbff; valaddr_reg:x2; val_offset:19665*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19665*FLEN/8, x3, x1, x4) + +inst_6590: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x401; +op3val:0x7c00; valaddr_reg:x2; val_offset:19668*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19668*FLEN/8, x3, x1, x4) + +inst_6591: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x401; +op3val:0xfc00; valaddr_reg:x2; val_offset:19671*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19671*FLEN/8, x3, x1, x4) + +inst_6592: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x401; +op3val:0x7e00; valaddr_reg:x2; val_offset:19674*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19674*FLEN/8, x3, x1, x4) + +inst_6593: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x401; +op3val:0xfe00; valaddr_reg:x2; val_offset:19677*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19677*FLEN/8, x3, x1, x4) + +inst_6594: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x401; +op3val:0x7e01; valaddr_reg:x2; val_offset:19680*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19680*FLEN/8, x3, x1, x4) + +inst_6595: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x401; +op3val:0xfe55; valaddr_reg:x2; val_offset:19683*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19683*FLEN/8, x3, x1, x4) + +inst_6596: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x401; +op3val:0x7c01; valaddr_reg:x2; val_offset:19686*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19686*FLEN/8, x3, x1, x4) + +inst_6597: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x401; +op3val:0xfd55; valaddr_reg:x2; val_offset:19689*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19689*FLEN/8, x3, x1, x4) + +inst_6598: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x401; +op3val:0x3c00; valaddr_reg:x2; val_offset:19692*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19692*FLEN/8, x3, x1, x4) + +inst_6599: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x401; +op3val:0xbc00; valaddr_reg:x2; val_offset:19695*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19695*FLEN/8, x3, x1, x4) + +inst_6600: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8455; +op3val:0x0; valaddr_reg:x2; val_offset:19698*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19698*FLEN/8, x3, x1, x4) + +inst_6601: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8455; +op3val:0x8000; valaddr_reg:x2; val_offset:19701*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19701*FLEN/8, x3, x1, x4) + +inst_6602: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8455; +op3val:0x1; valaddr_reg:x2; val_offset:19704*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19704*FLEN/8, x3, x1, x4) + +inst_6603: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8455; +op3val:0x8001; valaddr_reg:x2; val_offset:19707*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19707*FLEN/8, x3, x1, x4) + +inst_6604: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8455; +op3val:0x2; valaddr_reg:x2; val_offset:19710*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19710*FLEN/8, x3, x1, x4) + +inst_6605: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8455; +op3val:0x83fe; valaddr_reg:x2; val_offset:19713*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19713*FLEN/8, x3, x1, x4) + +inst_6606: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8455; +op3val:0x3ff; valaddr_reg:x2; val_offset:19716*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19716*FLEN/8, x3, x1, x4) + +inst_6607: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8455; +op3val:0x83ff; valaddr_reg:x2; val_offset:19719*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19719*FLEN/8, x3, x1, x4) + +inst_6608: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8455; +op3val:0x400; valaddr_reg:x2; val_offset:19722*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19722*FLEN/8, x3, x1, x4) + +inst_6609: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8455; +op3val:0x8400; valaddr_reg:x2; val_offset:19725*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19725*FLEN/8, x3, x1, x4) + +inst_6610: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8455; +op3val:0x401; valaddr_reg:x2; val_offset:19728*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19728*FLEN/8, x3, x1, x4) + +inst_6611: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8455; +op3val:0x8455; valaddr_reg:x2; val_offset:19731*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19731*FLEN/8, x3, x1, x4) + +inst_6612: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8455; +op3val:0x7bff; valaddr_reg:x2; val_offset:19734*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19734*FLEN/8, x3, x1, x4) + +inst_6613: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8455; +op3val:0xfbff; valaddr_reg:x2; val_offset:19737*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19737*FLEN/8, x3, x1, x4) + +inst_6614: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8455; +op3val:0x7c00; valaddr_reg:x2; val_offset:19740*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19740*FLEN/8, x3, x1, x4) + +inst_6615: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8455; +op3val:0xfc00; valaddr_reg:x2; val_offset:19743*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19743*FLEN/8, x3, x1, x4) + +inst_6616: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8455; +op3val:0x7e00; valaddr_reg:x2; val_offset:19746*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19746*FLEN/8, x3, x1, x4) + +inst_6617: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8455; +op3val:0xfe00; valaddr_reg:x2; val_offset:19749*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19749*FLEN/8, x3, x1, x4) + +inst_6618: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8455; +op3val:0x7e01; valaddr_reg:x2; val_offset:19752*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19752*FLEN/8, x3, x1, x4) + +inst_6619: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8455; +op3val:0xfe55; valaddr_reg:x2; val_offset:19755*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19755*FLEN/8, x3, x1, x4) + +inst_6620: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8455; +op3val:0x7c01; valaddr_reg:x2; val_offset:19758*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19758*FLEN/8, x3, x1, x4) + +inst_6621: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8455; +op3val:0xfd55; valaddr_reg:x2; val_offset:19761*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19761*FLEN/8, x3, x1, x4) + +inst_6622: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8455; +op3val:0x3c00; valaddr_reg:x2; val_offset:19764*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19764*FLEN/8, x3, x1, x4) + +inst_6623: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x8455; +op3val:0xbc00; valaddr_reg:x2; val_offset:19767*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19767*FLEN/8, x3, x1, x4) + +inst_6624: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7bff; +op3val:0x0; valaddr_reg:x2; val_offset:19770*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19770*FLEN/8, x3, x1, x4) + +inst_6625: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7bff; +op3val:0x8000; valaddr_reg:x2; val_offset:19773*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19773*FLEN/8, x3, x1, x4) + +inst_6626: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7bff; +op3val:0x1; valaddr_reg:x2; val_offset:19776*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19776*FLEN/8, x3, x1, x4) + +inst_6627: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7bff; +op3val:0x8001; valaddr_reg:x2; val_offset:19779*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19779*FLEN/8, x3, x1, x4) + +inst_6628: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7bff; +op3val:0x2; valaddr_reg:x2; val_offset:19782*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19782*FLEN/8, x3, x1, x4) + +inst_6629: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7bff; +op3val:0x83fe; valaddr_reg:x2; val_offset:19785*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19785*FLEN/8, x3, x1, x4) + +inst_6630: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7bff; +op3val:0x3ff; valaddr_reg:x2; val_offset:19788*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19788*FLEN/8, x3, x1, x4) + +inst_6631: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7bff; +op3val:0x83ff; valaddr_reg:x2; val_offset:19791*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19791*FLEN/8, x3, x1, x4) + +inst_6632: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7bff; +op3val:0x400; valaddr_reg:x2; val_offset:19794*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19794*FLEN/8, x3, x1, x4) + +inst_6633: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7bff; +op3val:0x8400; valaddr_reg:x2; val_offset:19797*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19797*FLEN/8, x3, x1, x4) + +inst_6634: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7bff; +op3val:0x401; valaddr_reg:x2; val_offset:19800*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19800*FLEN/8, x3, x1, x4) + +inst_6635: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7bff; +op3val:0x8455; valaddr_reg:x2; val_offset:19803*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19803*FLEN/8, x3, x1, x4) + +inst_6636: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7bff; +op3val:0x7bff; valaddr_reg:x2; val_offset:19806*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19806*FLEN/8, x3, x1, x4) + +inst_6637: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7bff; +op3val:0xfbff; valaddr_reg:x2; val_offset:19809*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19809*FLEN/8, x3, x1, x4) + +inst_6638: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7bff; +op3val:0x7c00; valaddr_reg:x2; val_offset:19812*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19812*FLEN/8, x3, x1, x4) + +inst_6639: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7bff; +op3val:0xfc00; valaddr_reg:x2; val_offset:19815*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19815*FLEN/8, x3, x1, x4) + +inst_6640: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7bff; +op3val:0x7e00; valaddr_reg:x2; val_offset:19818*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19818*FLEN/8, x3, x1, x4) + +inst_6641: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7bff; +op3val:0xfe00; valaddr_reg:x2; val_offset:19821*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19821*FLEN/8, x3, x1, x4) + +inst_6642: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7bff; +op3val:0x7e01; valaddr_reg:x2; val_offset:19824*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19824*FLEN/8, x3, x1, x4) + +inst_6643: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7bff; +op3val:0xfe55; valaddr_reg:x2; val_offset:19827*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19827*FLEN/8, x3, x1, x4) + +inst_6644: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7bff; +op3val:0x7c01; valaddr_reg:x2; val_offset:19830*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19830*FLEN/8, x3, x1, x4) + +inst_6645: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7bff; +op3val:0xfd55; valaddr_reg:x2; val_offset:19833*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19833*FLEN/8, x3, x1, x4) + +inst_6646: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7bff; +op3val:0x3c00; valaddr_reg:x2; val_offset:19836*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19836*FLEN/8, x3, x1, x4) + +inst_6647: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7bff; +op3val:0xbc00; valaddr_reg:x2; val_offset:19839*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19839*FLEN/8, x3, x1, x4) + +inst_6648: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfbff; +op3val:0x0; valaddr_reg:x2; val_offset:19842*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19842*FLEN/8, x3, x1, x4) + +inst_6649: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfbff; +op3val:0x8000; valaddr_reg:x2; val_offset:19845*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19845*FLEN/8, x3, x1, x4) + +inst_6650: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfbff; +op3val:0x1; valaddr_reg:x2; val_offset:19848*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19848*FLEN/8, x3, x1, x4) + +inst_6651: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfbff; +op3val:0x8001; valaddr_reg:x2; val_offset:19851*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19851*FLEN/8, x3, x1, x4) + +inst_6652: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfbff; +op3val:0x2; valaddr_reg:x2; val_offset:19854*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19854*FLEN/8, x3, x1, x4) + +inst_6653: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfbff; +op3val:0x83fe; valaddr_reg:x2; val_offset:19857*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19857*FLEN/8, x3, x1, x4) + +inst_6654: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfbff; +op3val:0x3ff; valaddr_reg:x2; val_offset:19860*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19860*FLEN/8, x3, x1, x4) + +inst_6655: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfbff; +op3val:0x83ff; valaddr_reg:x2; val_offset:19863*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19863*FLEN/8, x3, x1, x4) + +inst_6656: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfbff; +op3val:0x400; valaddr_reg:x2; val_offset:19866*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19866*FLEN/8, x3, x1, x4) + +inst_6657: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfbff; +op3val:0x8400; valaddr_reg:x2; val_offset:19869*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19869*FLEN/8, x3, x1, x4) + +inst_6658: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfbff; +op3val:0x401; valaddr_reg:x2; val_offset:19872*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19872*FLEN/8, x3, x1, x4) + +inst_6659: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfbff; +op3val:0x8455; valaddr_reg:x2; val_offset:19875*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19875*FLEN/8, x3, x1, x4) + +inst_6660: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfbff; +op3val:0x7bff; valaddr_reg:x2; val_offset:19878*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19878*FLEN/8, x3, x1, x4) + +inst_6661: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfbff; +op3val:0xfbff; valaddr_reg:x2; val_offset:19881*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19881*FLEN/8, x3, x1, x4) + +inst_6662: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfbff; +op3val:0x7c00; valaddr_reg:x2; val_offset:19884*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19884*FLEN/8, x3, x1, x4) + +inst_6663: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfbff; +op3val:0xfc00; valaddr_reg:x2; val_offset:19887*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19887*FLEN/8, x3, x1, x4) + +inst_6664: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfbff; +op3val:0x7e00; valaddr_reg:x2; val_offset:19890*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19890*FLEN/8, x3, x1, x4) + +inst_6665: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfbff; +op3val:0xfe00; valaddr_reg:x2; val_offset:19893*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19893*FLEN/8, x3, x1, x4) + +inst_6666: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfbff; +op3val:0x7e01; valaddr_reg:x2; val_offset:19896*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19896*FLEN/8, x3, x1, x4) + +inst_6667: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfbff; +op3val:0xfe55; valaddr_reg:x2; val_offset:19899*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19899*FLEN/8, x3, x1, x4) + +inst_6668: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfbff; +op3val:0x7c01; valaddr_reg:x2; val_offset:19902*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19902*FLEN/8, x3, x1, x4) + +inst_6669: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfbff; +op3val:0xfd55; valaddr_reg:x2; val_offset:19905*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19905*FLEN/8, x3, x1, x4) + +inst_6670: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfbff; +op3val:0x3c00; valaddr_reg:x2; val_offset:19908*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19908*FLEN/8, x3, x1, x4) + +inst_6671: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfbff; +op3val:0xbc00; valaddr_reg:x2; val_offset:19911*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19911*FLEN/8, x3, x1, x4) + +inst_6672: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7c00; +op3val:0x0; valaddr_reg:x2; val_offset:19914*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19914*FLEN/8, x3, x1, x4) + +inst_6673: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7c00; +op3val:0x8000; valaddr_reg:x2; val_offset:19917*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19917*FLEN/8, x3, x1, x4) + +inst_6674: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7c00; +op3val:0x1; valaddr_reg:x2; val_offset:19920*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19920*FLEN/8, x3, x1, x4) + +inst_6675: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7c00; +op3val:0x8001; valaddr_reg:x2; val_offset:19923*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19923*FLEN/8, x3, x1, x4) + +inst_6676: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7c00; +op3val:0x2; valaddr_reg:x2; val_offset:19926*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19926*FLEN/8, x3, x1, x4) + +inst_6677: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7c00; +op3val:0x83fe; valaddr_reg:x2; val_offset:19929*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19929*FLEN/8, x3, x1, x4) + +inst_6678: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7c00; +op3val:0x3ff; valaddr_reg:x2; val_offset:19932*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19932*FLEN/8, x3, x1, x4) + +inst_6679: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7c00; +op3val:0x83ff; valaddr_reg:x2; val_offset:19935*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19935*FLEN/8, x3, x1, x4) + +inst_6680: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7c00; +op3val:0x400; valaddr_reg:x2; val_offset:19938*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19938*FLEN/8, x3, x1, x4) + +inst_6681: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7c00; +op3val:0x8400; valaddr_reg:x2; val_offset:19941*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19941*FLEN/8, x3, x1, x4) + +inst_6682: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7c00; +op3val:0x401; valaddr_reg:x2; val_offset:19944*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19944*FLEN/8, x3, x1, x4) + +inst_6683: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7c00; +op3val:0x8455; valaddr_reg:x2; val_offset:19947*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19947*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_53) + +inst_6684: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7c00; +op3val:0x7bff; valaddr_reg:x2; val_offset:19950*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19950*FLEN/8, x3, x1, x4) + +inst_6685: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7c00; +op3val:0xfbff; valaddr_reg:x2; val_offset:19953*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19953*FLEN/8, x3, x1, x4) + +inst_6686: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7c00; +op3val:0x7c00; valaddr_reg:x2; val_offset:19956*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19956*FLEN/8, x3, x1, x4) + +inst_6687: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7c00; +op3val:0xfc00; valaddr_reg:x2; val_offset:19959*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19959*FLEN/8, x3, x1, x4) + +inst_6688: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7c00; +op3val:0x7e00; valaddr_reg:x2; val_offset:19962*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19962*FLEN/8, x3, x1, x4) + +inst_6689: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7c00; +op3val:0xfe00; valaddr_reg:x2; val_offset:19965*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19965*FLEN/8, x3, x1, x4) + +inst_6690: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7c00; +op3val:0x7e01; valaddr_reg:x2; val_offset:19968*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19968*FLEN/8, x3, x1, x4) + +inst_6691: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7c00; +op3val:0xfe55; valaddr_reg:x2; val_offset:19971*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19971*FLEN/8, x3, x1, x4) + +inst_6692: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7c00; +op3val:0x7c01; valaddr_reg:x2; val_offset:19974*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19974*FLEN/8, x3, x1, x4) + +inst_6693: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7c00; +op3val:0xfd55; valaddr_reg:x2; val_offset:19977*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19977*FLEN/8, x3, x1, x4) + +inst_6694: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7c00; +op3val:0x3c00; valaddr_reg:x2; val_offset:19980*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19980*FLEN/8, x3, x1, x4) + +inst_6695: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7c00; +op3val:0xbc00; valaddr_reg:x2; val_offset:19983*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19983*FLEN/8, x3, x1, x4) + +inst_6696: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfc00; +op3val:0x0; valaddr_reg:x2; val_offset:19986*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19986*FLEN/8, x3, x1, x4) + +inst_6697: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfc00; +op3val:0x8000; valaddr_reg:x2; val_offset:19989*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19989*FLEN/8, x3, x1, x4) + +inst_6698: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfc00; +op3val:0x1; valaddr_reg:x2; val_offset:19992*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19992*FLEN/8, x3, x1, x4) + +inst_6699: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfc00; +op3val:0x8001; valaddr_reg:x2; val_offset:19995*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19995*FLEN/8, x3, x1, x4) + +inst_6700: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfc00; +op3val:0x2; valaddr_reg:x2; val_offset:19998*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 19998*FLEN/8, x3, x1, x4) + +inst_6701: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfc00; +op3val:0x83fe; valaddr_reg:x2; val_offset:20001*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20001*FLEN/8, x3, x1, x4) + +inst_6702: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfc00; +op3val:0x3ff; valaddr_reg:x2; val_offset:20004*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20004*FLEN/8, x3, x1, x4) + +inst_6703: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfc00; +op3val:0x83ff; valaddr_reg:x2; val_offset:20007*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20007*FLEN/8, x3, x1, x4) + +inst_6704: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfc00; +op3val:0x400; valaddr_reg:x2; val_offset:20010*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20010*FLEN/8, x3, x1, x4) + +inst_6705: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfc00; +op3val:0x8400; valaddr_reg:x2; val_offset:20013*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20013*FLEN/8, x3, x1, x4) + +inst_6706: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfc00; +op3val:0x401; valaddr_reg:x2; val_offset:20016*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20016*FLEN/8, x3, x1, x4) + +inst_6707: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfc00; +op3val:0x8455; valaddr_reg:x2; val_offset:20019*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20019*FLEN/8, x3, x1, x4) + +inst_6708: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfc00; +op3val:0x7bff; valaddr_reg:x2; val_offset:20022*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20022*FLEN/8, x3, x1, x4) + +inst_6709: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfc00; +op3val:0xfbff; valaddr_reg:x2; val_offset:20025*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20025*FLEN/8, x3, x1, x4) + +inst_6710: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfc00; +op3val:0x7c00; valaddr_reg:x2; val_offset:20028*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20028*FLEN/8, x3, x1, x4) + +inst_6711: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfc00; +op3val:0xfc00; valaddr_reg:x2; val_offset:20031*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20031*FLEN/8, x3, x1, x4) + +inst_6712: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfc00; +op3val:0x7e00; valaddr_reg:x2; val_offset:20034*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20034*FLEN/8, x3, x1, x4) + +inst_6713: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfc00; +op3val:0xfe00; valaddr_reg:x2; val_offset:20037*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20037*FLEN/8, x3, x1, x4) + +inst_6714: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfc00; +op3val:0x7e01; valaddr_reg:x2; val_offset:20040*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20040*FLEN/8, x3, x1, x4) + +inst_6715: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfc00; +op3val:0xfe55; valaddr_reg:x2; val_offset:20043*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20043*FLEN/8, x3, x1, x4) + +inst_6716: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfc00; +op3val:0x7c01; valaddr_reg:x2; val_offset:20046*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20046*FLEN/8, x3, x1, x4) + +inst_6717: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfc00; +op3val:0xfd55; valaddr_reg:x2; val_offset:20049*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20049*FLEN/8, x3, x1, x4) + +inst_6718: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfc00; +op3val:0x3c00; valaddr_reg:x2; val_offset:20052*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20052*FLEN/8, x3, x1, x4) + +inst_6719: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfc00; +op3val:0xbc00; valaddr_reg:x2; val_offset:20055*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20055*FLEN/8, x3, x1, x4) + +inst_6720: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7e00; +op3val:0x0; valaddr_reg:x2; val_offset:20058*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20058*FLEN/8, x3, x1, x4) + +inst_6721: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7e00; +op3val:0x8000; valaddr_reg:x2; val_offset:20061*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20061*FLEN/8, x3, x1, x4) + +inst_6722: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7e00; +op3val:0x1; valaddr_reg:x2; val_offset:20064*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20064*FLEN/8, x3, x1, x4) + +inst_6723: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7e00; +op3val:0x8001; valaddr_reg:x2; val_offset:20067*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20067*FLEN/8, x3, x1, x4) + +inst_6724: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7e00; +op3val:0x2; valaddr_reg:x2; val_offset:20070*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20070*FLEN/8, x3, x1, x4) + +inst_6725: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7e00; +op3val:0x83fe; valaddr_reg:x2; val_offset:20073*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20073*FLEN/8, x3, x1, x4) + +inst_6726: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7e00; +op3val:0x3ff; valaddr_reg:x2; val_offset:20076*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20076*FLEN/8, x3, x1, x4) + +inst_6727: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7e00; +op3val:0x83ff; valaddr_reg:x2; val_offset:20079*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20079*FLEN/8, x3, x1, x4) + +inst_6728: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7e00; +op3val:0x400; valaddr_reg:x2; val_offset:20082*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20082*FLEN/8, x3, x1, x4) + +inst_6729: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7e00; +op3val:0x8400; valaddr_reg:x2; val_offset:20085*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20085*FLEN/8, x3, x1, x4) + +inst_6730: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7e00; +op3val:0x401; valaddr_reg:x2; val_offset:20088*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20088*FLEN/8, x3, x1, x4) + +inst_6731: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7e00; +op3val:0x8455; valaddr_reg:x2; val_offset:20091*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20091*FLEN/8, x3, x1, x4) + +inst_6732: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7e00; +op3val:0x7bff; valaddr_reg:x2; val_offset:20094*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20094*FLEN/8, x3, x1, x4) + +inst_6733: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7e00; +op3val:0xfbff; valaddr_reg:x2; val_offset:20097*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20097*FLEN/8, x3, x1, x4) + +inst_6734: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7e00; +op3val:0x7c00; valaddr_reg:x2; val_offset:20100*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20100*FLEN/8, x3, x1, x4) + +inst_6735: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7e00; +op3val:0xfc00; valaddr_reg:x2; val_offset:20103*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20103*FLEN/8, x3, x1, x4) + +inst_6736: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7e00; +op3val:0x7e00; valaddr_reg:x2; val_offset:20106*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20106*FLEN/8, x3, x1, x4) + +inst_6737: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7e00; +op3val:0xfe00; valaddr_reg:x2; val_offset:20109*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20109*FLEN/8, x3, x1, x4) + +inst_6738: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7e00; +op3val:0x7e01; valaddr_reg:x2; val_offset:20112*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20112*FLEN/8, x3, x1, x4) + +inst_6739: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7e00; +op3val:0xfe55; valaddr_reg:x2; val_offset:20115*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20115*FLEN/8, x3, x1, x4) + +inst_6740: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7e00; +op3val:0x7c01; valaddr_reg:x2; val_offset:20118*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20118*FLEN/8, x3, x1, x4) + +inst_6741: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7e00; +op3val:0xfd55; valaddr_reg:x2; val_offset:20121*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20121*FLEN/8, x3, x1, x4) + +inst_6742: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7e00; +op3val:0x3c00; valaddr_reg:x2; val_offset:20124*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20124*FLEN/8, x3, x1, x4) + +inst_6743: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7e00; +op3val:0xbc00; valaddr_reg:x2; val_offset:20127*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20127*FLEN/8, x3, x1, x4) + +inst_6744: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfe00; +op3val:0x0; valaddr_reg:x2; val_offset:20130*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20130*FLEN/8, x3, x1, x4) + +inst_6745: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfe00; +op3val:0x8000; valaddr_reg:x2; val_offset:20133*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20133*FLEN/8, x3, x1, x4) + +inst_6746: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfe00; +op3val:0x1; valaddr_reg:x2; val_offset:20136*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20136*FLEN/8, x3, x1, x4) + +inst_6747: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfe00; +op3val:0x8001; valaddr_reg:x2; val_offset:20139*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20139*FLEN/8, x3, x1, x4) + +inst_6748: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfe00; +op3val:0x2; valaddr_reg:x2; val_offset:20142*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20142*FLEN/8, x3, x1, x4) + +inst_6749: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfe00; +op3val:0x83fe; valaddr_reg:x2; val_offset:20145*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20145*FLEN/8, x3, x1, x4) + +inst_6750: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfe00; +op3val:0x3ff; valaddr_reg:x2; val_offset:20148*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20148*FLEN/8, x3, x1, x4) + +inst_6751: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfe00; +op3val:0x83ff; valaddr_reg:x2; val_offset:20151*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20151*FLEN/8, x3, x1, x4) + +inst_6752: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfe00; +op3val:0x400; valaddr_reg:x2; val_offset:20154*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20154*FLEN/8, x3, x1, x4) + +inst_6753: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfe00; +op3val:0x8400; valaddr_reg:x2; val_offset:20157*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20157*FLEN/8, x3, x1, x4) + +inst_6754: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfe00; +op3val:0x401; valaddr_reg:x2; val_offset:20160*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20160*FLEN/8, x3, x1, x4) + +inst_6755: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfe00; +op3val:0x8455; valaddr_reg:x2; val_offset:20163*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20163*FLEN/8, x3, x1, x4) + +inst_6756: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfe00; +op3val:0x7bff; valaddr_reg:x2; val_offset:20166*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20166*FLEN/8, x3, x1, x4) + +inst_6757: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfe00; +op3val:0xfbff; valaddr_reg:x2; val_offset:20169*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20169*FLEN/8, x3, x1, x4) + +inst_6758: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfe00; +op3val:0x7c00; valaddr_reg:x2; val_offset:20172*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20172*FLEN/8, x3, x1, x4) + +inst_6759: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfe00; +op3val:0xfc00; valaddr_reg:x2; val_offset:20175*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20175*FLEN/8, x3, x1, x4) + +inst_6760: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfe00; +op3val:0x7e00; valaddr_reg:x2; val_offset:20178*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20178*FLEN/8, x3, x1, x4) + +inst_6761: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfe00; +op3val:0xfe00; valaddr_reg:x2; val_offset:20181*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20181*FLEN/8, x3, x1, x4) + +inst_6762: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfe00; +op3val:0x7e01; valaddr_reg:x2; val_offset:20184*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20184*FLEN/8, x3, x1, x4) + +inst_6763: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfe00; +op3val:0xfe55; valaddr_reg:x2; val_offset:20187*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20187*FLEN/8, x3, x1, x4) + +inst_6764: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfe00; +op3val:0x7c01; valaddr_reg:x2; val_offset:20190*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20190*FLEN/8, x3, x1, x4) + +inst_6765: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfe00; +op3val:0xfd55; valaddr_reg:x2; val_offset:20193*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20193*FLEN/8, x3, x1, x4) + +inst_6766: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfe00; +op3val:0x3c00; valaddr_reg:x2; val_offset:20196*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20196*FLEN/8, x3, x1, x4) + +inst_6767: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfe00; +op3val:0xbc00; valaddr_reg:x2; val_offset:20199*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20199*FLEN/8, x3, x1, x4) + +inst_6768: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7e01; +op3val:0x0; valaddr_reg:x2; val_offset:20202*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20202*FLEN/8, x3, x1, x4) + +inst_6769: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7e01; +op3val:0x8000; valaddr_reg:x2; val_offset:20205*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20205*FLEN/8, x3, x1, x4) + +inst_6770: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7e01; +op3val:0x1; valaddr_reg:x2; val_offset:20208*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20208*FLEN/8, x3, x1, x4) + +inst_6771: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7e01; +op3val:0x8001; valaddr_reg:x2; val_offset:20211*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20211*FLEN/8, x3, x1, x4) + +inst_6772: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7e01; +op3val:0x2; valaddr_reg:x2; val_offset:20214*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20214*FLEN/8, x3, x1, x4) + +inst_6773: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7e01; +op3val:0x83fe; valaddr_reg:x2; val_offset:20217*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20217*FLEN/8, x3, x1, x4) + +inst_6774: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7e01; +op3val:0x3ff; valaddr_reg:x2; val_offset:20220*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20220*FLEN/8, x3, x1, x4) + +inst_6775: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7e01; +op3val:0x83ff; valaddr_reg:x2; val_offset:20223*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20223*FLEN/8, x3, x1, x4) + +inst_6776: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7e01; +op3val:0x400; valaddr_reg:x2; val_offset:20226*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20226*FLEN/8, x3, x1, x4) + +inst_6777: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7e01; +op3val:0x8400; valaddr_reg:x2; val_offset:20229*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20229*FLEN/8, x3, x1, x4) + +inst_6778: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7e01; +op3val:0x401; valaddr_reg:x2; val_offset:20232*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20232*FLEN/8, x3, x1, x4) + +inst_6779: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7e01; +op3val:0x8455; valaddr_reg:x2; val_offset:20235*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20235*FLEN/8, x3, x1, x4) + +inst_6780: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7e01; +op3val:0x7bff; valaddr_reg:x2; val_offset:20238*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20238*FLEN/8, x3, x1, x4) + +inst_6781: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7e01; +op3val:0xfbff; valaddr_reg:x2; val_offset:20241*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20241*FLEN/8, x3, x1, x4) + +inst_6782: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7e01; +op3val:0x7c00; valaddr_reg:x2; val_offset:20244*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20244*FLEN/8, x3, x1, x4) + +inst_6783: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7e01; +op3val:0xfc00; valaddr_reg:x2; val_offset:20247*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20247*FLEN/8, x3, x1, x4) + +inst_6784: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7e01; +op3val:0x7e00; valaddr_reg:x2; val_offset:20250*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20250*FLEN/8, x3, x1, x4) + +inst_6785: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7e01; +op3val:0xfe00; valaddr_reg:x2; val_offset:20253*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20253*FLEN/8, x3, x1, x4) + +inst_6786: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7e01; +op3val:0x7e01; valaddr_reg:x2; val_offset:20256*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20256*FLEN/8, x3, x1, x4) + +inst_6787: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7e01; +op3val:0xfe55; valaddr_reg:x2; val_offset:20259*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20259*FLEN/8, x3, x1, x4) + +inst_6788: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7e01; +op3val:0x7c01; valaddr_reg:x2; val_offset:20262*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20262*FLEN/8, x3, x1, x4) + +inst_6789: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7e01; +op3val:0xfd55; valaddr_reg:x2; val_offset:20265*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20265*FLEN/8, x3, x1, x4) + +inst_6790: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7e01; +op3val:0x3c00; valaddr_reg:x2; val_offset:20268*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20268*FLEN/8, x3, x1, x4) + +inst_6791: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7e01; +op3val:0xbc00; valaddr_reg:x2; val_offset:20271*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20271*FLEN/8, x3, x1, x4) + +inst_6792: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfe55; +op3val:0x0; valaddr_reg:x2; val_offset:20274*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20274*FLEN/8, x3, x1, x4) + +inst_6793: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfe55; +op3val:0x8000; valaddr_reg:x2; val_offset:20277*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20277*FLEN/8, x3, x1, x4) + +inst_6794: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfe55; +op3val:0x1; valaddr_reg:x2; val_offset:20280*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20280*FLEN/8, x3, x1, x4) + +inst_6795: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfe55; +op3val:0x8001; valaddr_reg:x2; val_offset:20283*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20283*FLEN/8, x3, x1, x4) + +inst_6796: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfe55; +op3val:0x2; valaddr_reg:x2; val_offset:20286*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20286*FLEN/8, x3, x1, x4) + +inst_6797: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfe55; +op3val:0x83fe; valaddr_reg:x2; val_offset:20289*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20289*FLEN/8, x3, x1, x4) + +inst_6798: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfe55; +op3val:0x3ff; valaddr_reg:x2; val_offset:20292*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20292*FLEN/8, x3, x1, x4) + +inst_6799: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfe55; +op3val:0x83ff; valaddr_reg:x2; val_offset:20295*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20295*FLEN/8, x3, x1, x4) + +inst_6800: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfe55; +op3val:0x400; valaddr_reg:x2; val_offset:20298*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20298*FLEN/8, x3, x1, x4) + +inst_6801: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfe55; +op3val:0x8400; valaddr_reg:x2; val_offset:20301*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20301*FLEN/8, x3, x1, x4) + +inst_6802: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfe55; +op3val:0x401; valaddr_reg:x2; val_offset:20304*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20304*FLEN/8, x3, x1, x4) + +inst_6803: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfe55; +op3val:0x8455; valaddr_reg:x2; val_offset:20307*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20307*FLEN/8, x3, x1, x4) + +inst_6804: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfe55; +op3val:0x7bff; valaddr_reg:x2; val_offset:20310*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20310*FLEN/8, x3, x1, x4) + +inst_6805: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfe55; +op3val:0xfbff; valaddr_reg:x2; val_offset:20313*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20313*FLEN/8, x3, x1, x4) + +inst_6806: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfe55; +op3val:0x7c00; valaddr_reg:x2; val_offset:20316*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20316*FLEN/8, x3, x1, x4) + +inst_6807: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfe55; +op3val:0xfc00; valaddr_reg:x2; val_offset:20319*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20319*FLEN/8, x3, x1, x4) + +inst_6808: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfe55; +op3val:0x7e00; valaddr_reg:x2; val_offset:20322*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20322*FLEN/8, x3, x1, x4) + +inst_6809: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfe55; +op3val:0xfe00; valaddr_reg:x2; val_offset:20325*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20325*FLEN/8, x3, x1, x4) + +inst_6810: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfe55; +op3val:0x7e01; valaddr_reg:x2; val_offset:20328*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20328*FLEN/8, x3, x1, x4) + +inst_6811: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfe55; +op3val:0xfe55; valaddr_reg:x2; val_offset:20331*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20331*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_54) + +inst_6812: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfe55; +op3val:0x7c01; valaddr_reg:x2; val_offset:20334*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20334*FLEN/8, x3, x1, x4) + +inst_6813: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfe55; +op3val:0xfd55; valaddr_reg:x2; val_offset:20337*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20337*FLEN/8, x3, x1, x4) + +inst_6814: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfe55; +op3val:0x3c00; valaddr_reg:x2; val_offset:20340*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20340*FLEN/8, x3, x1, x4) + +inst_6815: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfe55; +op3val:0xbc00; valaddr_reg:x2; val_offset:20343*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20343*FLEN/8, x3, x1, x4) + +inst_6816: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7c01; +op3val:0x0; valaddr_reg:x2; val_offset:20346*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20346*FLEN/8, x3, x1, x4) + +inst_6817: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7c01; +op3val:0x8000; valaddr_reg:x2; val_offset:20349*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20349*FLEN/8, x3, x1, x4) + +inst_6818: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7c01; +op3val:0x1; valaddr_reg:x2; val_offset:20352*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20352*FLEN/8, x3, x1, x4) + +inst_6819: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7c01; +op3val:0x8001; valaddr_reg:x2; val_offset:20355*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20355*FLEN/8, x3, x1, x4) + +inst_6820: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7c01; +op3val:0x2; valaddr_reg:x2; val_offset:20358*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20358*FLEN/8, x3, x1, x4) + +inst_6821: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7c01; +op3val:0x83fe; valaddr_reg:x2; val_offset:20361*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20361*FLEN/8, x3, x1, x4) + +inst_6822: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7c01; +op3val:0x3ff; valaddr_reg:x2; val_offset:20364*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20364*FLEN/8, x3, x1, x4) + +inst_6823: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7c01; +op3val:0x83ff; valaddr_reg:x2; val_offset:20367*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20367*FLEN/8, x3, x1, x4) + +inst_6824: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7c01; +op3val:0x400; valaddr_reg:x2; val_offset:20370*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20370*FLEN/8, x3, x1, x4) + +inst_6825: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7c01; +op3val:0x8400; valaddr_reg:x2; val_offset:20373*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20373*FLEN/8, x3, x1, x4) + +inst_6826: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7c01; +op3val:0x401; valaddr_reg:x2; val_offset:20376*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20376*FLEN/8, x3, x1, x4) + +inst_6827: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7c01; +op3val:0x8455; valaddr_reg:x2; val_offset:20379*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20379*FLEN/8, x3, x1, x4) + +inst_6828: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7c01; +op3val:0x7bff; valaddr_reg:x2; val_offset:20382*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20382*FLEN/8, x3, x1, x4) + +inst_6829: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7c01; +op3val:0xfbff; valaddr_reg:x2; val_offset:20385*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20385*FLEN/8, x3, x1, x4) + +inst_6830: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7c01; +op3val:0x7c00; valaddr_reg:x2; val_offset:20388*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20388*FLEN/8, x3, x1, x4) + +inst_6831: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7c01; +op3val:0xfc00; valaddr_reg:x2; val_offset:20391*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20391*FLEN/8, x3, x1, x4) + +inst_6832: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7c01; +op3val:0x7e00; valaddr_reg:x2; val_offset:20394*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20394*FLEN/8, x3, x1, x4) + +inst_6833: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7c01; +op3val:0xfe00; valaddr_reg:x2; val_offset:20397*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20397*FLEN/8, x3, x1, x4) + +inst_6834: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7c01; +op3val:0x7e01; valaddr_reg:x2; val_offset:20400*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20400*FLEN/8, x3, x1, x4) + +inst_6835: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7c01; +op3val:0xfe55; valaddr_reg:x2; val_offset:20403*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20403*FLEN/8, x3, x1, x4) + +inst_6836: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7c01; +op3val:0x7c01; valaddr_reg:x2; val_offset:20406*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20406*FLEN/8, x3, x1, x4) + +inst_6837: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7c01; +op3val:0xfd55; valaddr_reg:x2; val_offset:20409*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20409*FLEN/8, x3, x1, x4) + +inst_6838: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7c01; +op3val:0x3c00; valaddr_reg:x2; val_offset:20412*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20412*FLEN/8, x3, x1, x4) + +inst_6839: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x7c01; +op3val:0xbc00; valaddr_reg:x2; val_offset:20415*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20415*FLEN/8, x3, x1, x4) + +inst_6840: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfd55; +op3val:0x0; valaddr_reg:x2; val_offset:20418*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20418*FLEN/8, x3, x1, x4) + +inst_6841: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfd55; +op3val:0x8000; valaddr_reg:x2; val_offset:20421*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20421*FLEN/8, x3, x1, x4) + +inst_6842: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfd55; +op3val:0x1; valaddr_reg:x2; val_offset:20424*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20424*FLEN/8, x3, x1, x4) + +inst_6843: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfd55; +op3val:0x8001; valaddr_reg:x2; val_offset:20427*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20427*FLEN/8, x3, x1, x4) + +inst_6844: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfd55; +op3val:0x2; valaddr_reg:x2; val_offset:20430*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20430*FLEN/8, x3, x1, x4) + +inst_6845: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfd55; +op3val:0x83fe; valaddr_reg:x2; val_offset:20433*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20433*FLEN/8, x3, x1, x4) + +inst_6846: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfd55; +op3val:0x3ff; valaddr_reg:x2; val_offset:20436*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20436*FLEN/8, x3, x1, x4) + +inst_6847: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfd55; +op3val:0x83ff; valaddr_reg:x2; val_offset:20439*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20439*FLEN/8, x3, x1, x4) + +inst_6848: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfd55; +op3val:0x400; valaddr_reg:x2; val_offset:20442*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20442*FLEN/8, x3, x1, x4) + +inst_6849: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfd55; +op3val:0x8400; valaddr_reg:x2; val_offset:20445*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20445*FLEN/8, x3, x1, x4) + +inst_6850: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfd55; +op3val:0x401; valaddr_reg:x2; val_offset:20448*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20448*FLEN/8, x3, x1, x4) + +inst_6851: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfd55; +op3val:0x8455; valaddr_reg:x2; val_offset:20451*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20451*FLEN/8, x3, x1, x4) + +inst_6852: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfd55; +op3val:0x7bff; valaddr_reg:x2; val_offset:20454*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20454*FLEN/8, x3, x1, x4) + +inst_6853: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfd55; +op3val:0xfbff; valaddr_reg:x2; val_offset:20457*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20457*FLEN/8, x3, x1, x4) + +inst_6854: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfd55; +op3val:0x7c00; valaddr_reg:x2; val_offset:20460*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20460*FLEN/8, x3, x1, x4) + +inst_6855: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfd55; +op3val:0xfc00; valaddr_reg:x2; val_offset:20463*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20463*FLEN/8, x3, x1, x4) + +inst_6856: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfd55; +op3val:0x7e00; valaddr_reg:x2; val_offset:20466*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20466*FLEN/8, x3, x1, x4) + +inst_6857: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfd55; +op3val:0xfe00; valaddr_reg:x2; val_offset:20469*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20469*FLEN/8, x3, x1, x4) + +inst_6858: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfd55; +op3val:0x7e01; valaddr_reg:x2; val_offset:20472*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20472*FLEN/8, x3, x1, x4) + +inst_6859: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfd55; +op3val:0xfe55; valaddr_reg:x2; val_offset:20475*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20475*FLEN/8, x3, x1, x4) + +inst_6860: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfd55; +op3val:0x7c01; valaddr_reg:x2; val_offset:20478*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20478*FLEN/8, x3, x1, x4) + +inst_6861: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfd55; +op3val:0xfd55; valaddr_reg:x2; val_offset:20481*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20481*FLEN/8, x3, x1, x4) + +inst_6862: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfd55; +op3val:0x3c00; valaddr_reg:x2; val_offset:20484*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20484*FLEN/8, x3, x1, x4) + +inst_6863: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xfd55; +op3val:0xbc00; valaddr_reg:x2; val_offset:20487*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20487*FLEN/8, x3, x1, x4) + +inst_6864: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x3c00; +op3val:0x0; valaddr_reg:x2; val_offset:20490*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20490*FLEN/8, x3, x1, x4) + +inst_6865: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x3c00; +op3val:0x8000; valaddr_reg:x2; val_offset:20493*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20493*FLEN/8, x3, x1, x4) + +inst_6866: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x3c00; +op3val:0x1; valaddr_reg:x2; val_offset:20496*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20496*FLEN/8, x3, x1, x4) + +inst_6867: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x3c00; +op3val:0x8001; valaddr_reg:x2; val_offset:20499*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20499*FLEN/8, x3, x1, x4) + +inst_6868: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x3c00; +op3val:0x2; valaddr_reg:x2; val_offset:20502*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20502*FLEN/8, x3, x1, x4) + +inst_6869: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x3c00; +op3val:0x83fe; valaddr_reg:x2; val_offset:20505*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20505*FLEN/8, x3, x1, x4) + +inst_6870: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x3c00; +op3val:0x3ff; valaddr_reg:x2; val_offset:20508*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20508*FLEN/8, x3, x1, x4) + +inst_6871: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x3c00; +op3val:0x83ff; valaddr_reg:x2; val_offset:20511*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20511*FLEN/8, x3, x1, x4) + +inst_6872: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x3c00; +op3val:0x400; valaddr_reg:x2; val_offset:20514*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20514*FLEN/8, x3, x1, x4) + +inst_6873: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x3c00; +op3val:0x8400; valaddr_reg:x2; val_offset:20517*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20517*FLEN/8, x3, x1, x4) + +inst_6874: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x3c00; +op3val:0x401; valaddr_reg:x2; val_offset:20520*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20520*FLEN/8, x3, x1, x4) + +inst_6875: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x3c00; +op3val:0x8455; valaddr_reg:x2; val_offset:20523*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20523*FLEN/8, x3, x1, x4) + +inst_6876: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x3c00; +op3val:0x7bff; valaddr_reg:x2; val_offset:20526*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20526*FLEN/8, x3, x1, x4) + +inst_6877: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x3c00; +op3val:0xfbff; valaddr_reg:x2; val_offset:20529*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20529*FLEN/8, x3, x1, x4) + +inst_6878: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x3c00; +op3val:0x7c00; valaddr_reg:x2; val_offset:20532*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20532*FLEN/8, x3, x1, x4) + +inst_6879: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x3c00; +op3val:0xfc00; valaddr_reg:x2; val_offset:20535*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20535*FLEN/8, x3, x1, x4) + +inst_6880: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x3c00; +op3val:0x7e00; valaddr_reg:x2; val_offset:20538*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20538*FLEN/8, x3, x1, x4) + +inst_6881: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x3c00; +op3val:0xfe00; valaddr_reg:x2; val_offset:20541*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20541*FLEN/8, x3, x1, x4) + +inst_6882: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x3c00; +op3val:0x7e01; valaddr_reg:x2; val_offset:20544*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20544*FLEN/8, x3, x1, x4) + +inst_6883: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x3c00; +op3val:0xfe55; valaddr_reg:x2; val_offset:20547*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20547*FLEN/8, x3, x1, x4) + +inst_6884: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x3c00; +op3val:0x7c01; valaddr_reg:x2; val_offset:20550*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20550*FLEN/8, x3, x1, x4) + +inst_6885: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x3c00; +op3val:0xfd55; valaddr_reg:x2; val_offset:20553*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20553*FLEN/8, x3, x1, x4) + +inst_6886: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x3c00; +op3val:0x3c00; valaddr_reg:x2; val_offset:20556*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20556*FLEN/8, x3, x1, x4) + +inst_6887: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0x3c00; +op3val:0xbc00; valaddr_reg:x2; val_offset:20559*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20559*FLEN/8, x3, x1, x4) + +inst_6888: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xbc00; +op3val:0x0; valaddr_reg:x2; val_offset:20562*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20562*FLEN/8, x3, x1, x4) + +inst_6889: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xbc00; +op3val:0x8000; valaddr_reg:x2; val_offset:20565*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20565*FLEN/8, x3, x1, x4) + +inst_6890: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xbc00; +op3val:0x1; valaddr_reg:x2; val_offset:20568*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20568*FLEN/8, x3, x1, x4) + +inst_6891: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xbc00; +op3val:0x8001; valaddr_reg:x2; val_offset:20571*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20571*FLEN/8, x3, x1, x4) + +inst_6892: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xbc00; +op3val:0x2; valaddr_reg:x2; val_offset:20574*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20574*FLEN/8, x3, x1, x4) + +inst_6893: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xbc00; +op3val:0x83fe; valaddr_reg:x2; val_offset:20577*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20577*FLEN/8, x3, x1, x4) + +inst_6894: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xbc00; +op3val:0x3ff; valaddr_reg:x2; val_offset:20580*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20580*FLEN/8, x3, x1, x4) + +inst_6895: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xbc00; +op3val:0x83ff; valaddr_reg:x2; val_offset:20583*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20583*FLEN/8, x3, x1, x4) + +inst_6896: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xbc00; +op3val:0x400; valaddr_reg:x2; val_offset:20586*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20586*FLEN/8, x3, x1, x4) + +inst_6897: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xbc00; +op3val:0x8400; valaddr_reg:x2; val_offset:20589*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20589*FLEN/8, x3, x1, x4) + +inst_6898: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xbc00; +op3val:0x401; valaddr_reg:x2; val_offset:20592*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20592*FLEN/8, x3, x1, x4) + +inst_6899: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xbc00; +op3val:0x8455; valaddr_reg:x2; val_offset:20595*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20595*FLEN/8, x3, x1, x4) + +inst_6900: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xbc00; +op3val:0x7bff; valaddr_reg:x2; val_offset:20598*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20598*FLEN/8, x3, x1, x4) + +inst_6901: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xbc00; +op3val:0xfbff; valaddr_reg:x2; val_offset:20601*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20601*FLEN/8, x3, x1, x4) + +inst_6902: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xbc00; +op3val:0x7c00; valaddr_reg:x2; val_offset:20604*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20604*FLEN/8, x3, x1, x4) + +inst_6903: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xbc00; +op3val:0xfc00; valaddr_reg:x2; val_offset:20607*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20607*FLEN/8, x3, x1, x4) + +inst_6904: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xbc00; +op3val:0x7e00; valaddr_reg:x2; val_offset:20610*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20610*FLEN/8, x3, x1, x4) + +inst_6905: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xbc00; +op3val:0xfe00; valaddr_reg:x2; val_offset:20613*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20613*FLEN/8, x3, x1, x4) + +inst_6906: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xbc00; +op3val:0x7e01; valaddr_reg:x2; val_offset:20616*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20616*FLEN/8, x3, x1, x4) + +inst_6907: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xbc00; +op3val:0xfe55; valaddr_reg:x2; val_offset:20619*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20619*FLEN/8, x3, x1, x4) + +inst_6908: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xbc00; +op3val:0x7c01; valaddr_reg:x2; val_offset:20622*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20622*FLEN/8, x3, x1, x4) + +inst_6909: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xbc00; +op3val:0xfd55; valaddr_reg:x2; val_offset:20625*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20625*FLEN/8, x3, x1, x4) + +inst_6910: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xbc00; +op3val:0x3c00; valaddr_reg:x2; val_offset:20628*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20628*FLEN/8, x3, x1, x4) + +inst_6911: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8455; op2val:0xbc00; +op3val:0xbc00; valaddr_reg:x2; val_offset:20631*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20631*FLEN/8, x3, x1, x4) + +inst_6912: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x0; +op3val:0x0; valaddr_reg:x2; val_offset:20634*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20634*FLEN/8, x3, x1, x4) + +inst_6913: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x0; +op3val:0x8000; valaddr_reg:x2; val_offset:20637*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20637*FLEN/8, x3, x1, x4) + +inst_6914: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x0; +op3val:0x1; valaddr_reg:x2; val_offset:20640*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20640*FLEN/8, x3, x1, x4) + +inst_6915: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x0; +op3val:0x8001; valaddr_reg:x2; val_offset:20643*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20643*FLEN/8, x3, x1, x4) + +inst_6916: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x0; +op3val:0x2; valaddr_reg:x2; val_offset:20646*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20646*FLEN/8, x3, x1, x4) + +inst_6917: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x0; +op3val:0x83fe; valaddr_reg:x2; val_offset:20649*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20649*FLEN/8, x3, x1, x4) + +inst_6918: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x0; +op3val:0x3ff; valaddr_reg:x2; val_offset:20652*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20652*FLEN/8, x3, x1, x4) + +inst_6919: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x0; +op3val:0x83ff; valaddr_reg:x2; val_offset:20655*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20655*FLEN/8, x3, x1, x4) + +inst_6920: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x0; +op3val:0x400; valaddr_reg:x2; val_offset:20658*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20658*FLEN/8, x3, x1, x4) + +inst_6921: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x0; +op3val:0x8400; valaddr_reg:x2; val_offset:20661*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20661*FLEN/8, x3, x1, x4) + +inst_6922: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x0; +op3val:0x401; valaddr_reg:x2; val_offset:20664*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20664*FLEN/8, x3, x1, x4) + +inst_6923: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x0; +op3val:0x8455; valaddr_reg:x2; val_offset:20667*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20667*FLEN/8, x3, x1, x4) + +inst_6924: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x0; +op3val:0x7bff; valaddr_reg:x2; val_offset:20670*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20670*FLEN/8, x3, x1, x4) + +inst_6925: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x0; +op3val:0xfbff; valaddr_reg:x2; val_offset:20673*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20673*FLEN/8, x3, x1, x4) + +inst_6926: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x0; +op3val:0x7c00; valaddr_reg:x2; val_offset:20676*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20676*FLEN/8, x3, x1, x4) + +inst_6927: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x0; +op3val:0xfc00; valaddr_reg:x2; val_offset:20679*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20679*FLEN/8, x3, x1, x4) + +inst_6928: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x0; +op3val:0x7e00; valaddr_reg:x2; val_offset:20682*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20682*FLEN/8, x3, x1, x4) + +inst_6929: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x0; +op3val:0xfe00; valaddr_reg:x2; val_offset:20685*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20685*FLEN/8, x3, x1, x4) + +inst_6930: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x0; +op3val:0x7e01; valaddr_reg:x2; val_offset:20688*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20688*FLEN/8, x3, x1, x4) + +inst_6931: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x0; +op3val:0xfe55; valaddr_reg:x2; val_offset:20691*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20691*FLEN/8, x3, x1, x4) + +inst_6932: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x0; +op3val:0x7c01; valaddr_reg:x2; val_offset:20694*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20694*FLEN/8, x3, x1, x4) + +inst_6933: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x0; +op3val:0xfd55; valaddr_reg:x2; val_offset:20697*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20697*FLEN/8, x3, x1, x4) + +inst_6934: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x0; +op3val:0x3c00; valaddr_reg:x2; val_offset:20700*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20700*FLEN/8, x3, x1, x4) + +inst_6935: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x0; +op3val:0xbc00; valaddr_reg:x2; val_offset:20703*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20703*FLEN/8, x3, x1, x4) + +inst_6936: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8000; +op3val:0x0; valaddr_reg:x2; val_offset:20706*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20706*FLEN/8, x3, x1, x4) + +inst_6937: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8000; +op3val:0x8000; valaddr_reg:x2; val_offset:20709*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20709*FLEN/8, x3, x1, x4) + +inst_6938: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8000; +op3val:0x1; valaddr_reg:x2; val_offset:20712*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20712*FLEN/8, x3, x1, x4) + +inst_6939: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8000; +op3val:0x8001; valaddr_reg:x2; val_offset:20715*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20715*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_55) + +inst_6940: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8000; +op3val:0x2; valaddr_reg:x2; val_offset:20718*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20718*FLEN/8, x3, x1, x4) + +inst_6941: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8000; +op3val:0x83fe; valaddr_reg:x2; val_offset:20721*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20721*FLEN/8, x3, x1, x4) + +inst_6942: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8000; +op3val:0x3ff; valaddr_reg:x2; val_offset:20724*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20724*FLEN/8, x3, x1, x4) + +inst_6943: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8000; +op3val:0x83ff; valaddr_reg:x2; val_offset:20727*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20727*FLEN/8, x3, x1, x4) + +inst_6944: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8000; +op3val:0x400; valaddr_reg:x2; val_offset:20730*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20730*FLEN/8, x3, x1, x4) + +inst_6945: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8000; +op3val:0x8400; valaddr_reg:x2; val_offset:20733*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20733*FLEN/8, x3, x1, x4) + +inst_6946: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8000; +op3val:0x401; valaddr_reg:x2; val_offset:20736*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20736*FLEN/8, x3, x1, x4) + +inst_6947: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8000; +op3val:0x8455; valaddr_reg:x2; val_offset:20739*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20739*FLEN/8, x3, x1, x4) + +inst_6948: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x2; val_offset:20742*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20742*FLEN/8, x3, x1, x4) + +inst_6949: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x2; val_offset:20745*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20745*FLEN/8, x3, x1, x4) + +inst_6950: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8000; +op3val:0x7c00; valaddr_reg:x2; val_offset:20748*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20748*FLEN/8, x3, x1, x4) + +inst_6951: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8000; +op3val:0xfc00; valaddr_reg:x2; val_offset:20751*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20751*FLEN/8, x3, x1, x4) + +inst_6952: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8000; +op3val:0x7e00; valaddr_reg:x2; val_offset:20754*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20754*FLEN/8, x3, x1, x4) + +inst_6953: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8000; +op3val:0xfe00; valaddr_reg:x2; val_offset:20757*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20757*FLEN/8, x3, x1, x4) + +inst_6954: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8000; +op3val:0x7e01; valaddr_reg:x2; val_offset:20760*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20760*FLEN/8, x3, x1, x4) + +inst_6955: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8000; +op3val:0xfe55; valaddr_reg:x2; val_offset:20763*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20763*FLEN/8, x3, x1, x4) + +inst_6956: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8000; +op3val:0x7c01; valaddr_reg:x2; val_offset:20766*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20766*FLEN/8, x3, x1, x4) + +inst_6957: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8000; +op3val:0xfd55; valaddr_reg:x2; val_offset:20769*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20769*FLEN/8, x3, x1, x4) + +inst_6958: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8000; +op3val:0x3c00; valaddr_reg:x2; val_offset:20772*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20772*FLEN/8, x3, x1, x4) + +inst_6959: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8000; +op3val:0xbc00; valaddr_reg:x2; val_offset:20775*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20775*FLEN/8, x3, x1, x4) + +inst_6960: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x1; +op3val:0x0; valaddr_reg:x2; val_offset:20778*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20778*FLEN/8, x3, x1, x4) + +inst_6961: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x1; +op3val:0x8000; valaddr_reg:x2; val_offset:20781*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20781*FLEN/8, x3, x1, x4) + +inst_6962: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x1; +op3val:0x1; valaddr_reg:x2; val_offset:20784*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20784*FLEN/8, x3, x1, x4) + +inst_6963: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x1; +op3val:0x8001; valaddr_reg:x2; val_offset:20787*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20787*FLEN/8, x3, x1, x4) + +inst_6964: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x1; +op3val:0x2; valaddr_reg:x2; val_offset:20790*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20790*FLEN/8, x3, x1, x4) + +inst_6965: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x1; +op3val:0x83fe; valaddr_reg:x2; val_offset:20793*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20793*FLEN/8, x3, x1, x4) + +inst_6966: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x1; +op3val:0x3ff; valaddr_reg:x2; val_offset:20796*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20796*FLEN/8, x3, x1, x4) + +inst_6967: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x1; +op3val:0x83ff; valaddr_reg:x2; val_offset:20799*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20799*FLEN/8, x3, x1, x4) + +inst_6968: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x1; +op3val:0x400; valaddr_reg:x2; val_offset:20802*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20802*FLEN/8, x3, x1, x4) + +inst_6969: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x1; +op3val:0x8400; valaddr_reg:x2; val_offset:20805*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20805*FLEN/8, x3, x1, x4) + +inst_6970: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x1; +op3val:0x401; valaddr_reg:x2; val_offset:20808*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20808*FLEN/8, x3, x1, x4) + +inst_6971: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x1; +op3val:0x8455; valaddr_reg:x2; val_offset:20811*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20811*FLEN/8, x3, x1, x4) + +inst_6972: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x1; +op3val:0x7bff; valaddr_reg:x2; val_offset:20814*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20814*FLEN/8, x3, x1, x4) + +inst_6973: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x1; +op3val:0xfbff; valaddr_reg:x2; val_offset:20817*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20817*FLEN/8, x3, x1, x4) + +inst_6974: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x1; +op3val:0x7c00; valaddr_reg:x2; val_offset:20820*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20820*FLEN/8, x3, x1, x4) + +inst_6975: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x1; +op3val:0xfc00; valaddr_reg:x2; val_offset:20823*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20823*FLEN/8, x3, x1, x4) + +inst_6976: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x1; +op3val:0x7e00; valaddr_reg:x2; val_offset:20826*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20826*FLEN/8, x3, x1, x4) + +inst_6977: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x1; +op3val:0xfe00; valaddr_reg:x2; val_offset:20829*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20829*FLEN/8, x3, x1, x4) + +inst_6978: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x1; +op3val:0x7e01; valaddr_reg:x2; val_offset:20832*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20832*FLEN/8, x3, x1, x4) + +inst_6979: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x1; +op3val:0xfe55; valaddr_reg:x2; val_offset:20835*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20835*FLEN/8, x3, x1, x4) + +inst_6980: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x1; +op3val:0x7c01; valaddr_reg:x2; val_offset:20838*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20838*FLEN/8, x3, x1, x4) + +inst_6981: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x1; +op3val:0xfd55; valaddr_reg:x2; val_offset:20841*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20841*FLEN/8, x3, x1, x4) + +inst_6982: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x1; +op3val:0x3c00; valaddr_reg:x2; val_offset:20844*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20844*FLEN/8, x3, x1, x4) + +inst_6983: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x1; +op3val:0xbc00; valaddr_reg:x2; val_offset:20847*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20847*FLEN/8, x3, x1, x4) + +inst_6984: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8001; +op3val:0x0; valaddr_reg:x2; val_offset:20850*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20850*FLEN/8, x3, x1, x4) + +inst_6985: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8001; +op3val:0x8000; valaddr_reg:x2; val_offset:20853*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20853*FLEN/8, x3, x1, x4) + +inst_6986: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8001; +op3val:0x1; valaddr_reg:x2; val_offset:20856*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20856*FLEN/8, x3, x1, x4) + +inst_6987: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8001; +op3val:0x8001; valaddr_reg:x2; val_offset:20859*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20859*FLEN/8, x3, x1, x4) + +inst_6988: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8001; +op3val:0x2; valaddr_reg:x2; val_offset:20862*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20862*FLEN/8, x3, x1, x4) + +inst_6989: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8001; +op3val:0x83fe; valaddr_reg:x2; val_offset:20865*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20865*FLEN/8, x3, x1, x4) + +inst_6990: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8001; +op3val:0x3ff; valaddr_reg:x2; val_offset:20868*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20868*FLEN/8, x3, x1, x4) + +inst_6991: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8001; +op3val:0x83ff; valaddr_reg:x2; val_offset:20871*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20871*FLEN/8, x3, x1, x4) + +inst_6992: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8001; +op3val:0x400; valaddr_reg:x2; val_offset:20874*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20874*FLEN/8, x3, x1, x4) + +inst_6993: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8001; +op3val:0x8400; valaddr_reg:x2; val_offset:20877*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20877*FLEN/8, x3, x1, x4) + +inst_6994: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8001; +op3val:0x401; valaddr_reg:x2; val_offset:20880*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20880*FLEN/8, x3, x1, x4) + +inst_6995: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8001; +op3val:0x8455; valaddr_reg:x2; val_offset:20883*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20883*FLEN/8, x3, x1, x4) + +inst_6996: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8001; +op3val:0x7bff; valaddr_reg:x2; val_offset:20886*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20886*FLEN/8, x3, x1, x4) + +inst_6997: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8001; +op3val:0xfbff; valaddr_reg:x2; val_offset:20889*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20889*FLEN/8, x3, x1, x4) + +inst_6998: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8001; +op3val:0x7c00; valaddr_reg:x2; val_offset:20892*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20892*FLEN/8, x3, x1, x4) + +inst_6999: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8001; +op3val:0xfc00; valaddr_reg:x2; val_offset:20895*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20895*FLEN/8, x3, x1, x4) + +inst_7000: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8001; +op3val:0x7e00; valaddr_reg:x2; val_offset:20898*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20898*FLEN/8, x3, x1, x4) + +inst_7001: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8001; +op3val:0xfe00; valaddr_reg:x2; val_offset:20901*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20901*FLEN/8, x3, x1, x4) + +inst_7002: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8001; +op3val:0x7e01; valaddr_reg:x2; val_offset:20904*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20904*FLEN/8, x3, x1, x4) + +inst_7003: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8001; +op3val:0xfe55; valaddr_reg:x2; val_offset:20907*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20907*FLEN/8, x3, x1, x4) + +inst_7004: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8001; +op3val:0x7c01; valaddr_reg:x2; val_offset:20910*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20910*FLEN/8, x3, x1, x4) + +inst_7005: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8001; +op3val:0xfd55; valaddr_reg:x2; val_offset:20913*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20913*FLEN/8, x3, x1, x4) + +inst_7006: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8001; +op3val:0x3c00; valaddr_reg:x2; val_offset:20916*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20916*FLEN/8, x3, x1, x4) + +inst_7007: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8001; +op3val:0xbc00; valaddr_reg:x2; val_offset:20919*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20919*FLEN/8, x3, x1, x4) + +inst_7008: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x2; +op3val:0x0; valaddr_reg:x2; val_offset:20922*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20922*FLEN/8, x3, x1, x4) + +inst_7009: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x2; +op3val:0x8000; valaddr_reg:x2; val_offset:20925*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20925*FLEN/8, x3, x1, x4) + +inst_7010: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x2; +op3val:0x1; valaddr_reg:x2; val_offset:20928*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20928*FLEN/8, x3, x1, x4) + +inst_7011: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x2; +op3val:0x8001; valaddr_reg:x2; val_offset:20931*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20931*FLEN/8, x3, x1, x4) + +inst_7012: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x2; +op3val:0x2; valaddr_reg:x2; val_offset:20934*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20934*FLEN/8, x3, x1, x4) + +inst_7013: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x2; +op3val:0x83fe; valaddr_reg:x2; val_offset:20937*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20937*FLEN/8, x3, x1, x4) + +inst_7014: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x2; +op3val:0x3ff; valaddr_reg:x2; val_offset:20940*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20940*FLEN/8, x3, x1, x4) + +inst_7015: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x2; +op3val:0x83ff; valaddr_reg:x2; val_offset:20943*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20943*FLEN/8, x3, x1, x4) + +inst_7016: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x2; +op3val:0x400; valaddr_reg:x2; val_offset:20946*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20946*FLEN/8, x3, x1, x4) + +inst_7017: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x2; +op3val:0x8400; valaddr_reg:x2; val_offset:20949*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20949*FLEN/8, x3, x1, x4) + +inst_7018: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x2; +op3val:0x401; valaddr_reg:x2; val_offset:20952*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20952*FLEN/8, x3, x1, x4) + +inst_7019: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x2; +op3val:0x8455; valaddr_reg:x2; val_offset:20955*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20955*FLEN/8, x3, x1, x4) + +inst_7020: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x2; +op3val:0x7bff; valaddr_reg:x2; val_offset:20958*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20958*FLEN/8, x3, x1, x4) + +inst_7021: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x2; +op3val:0xfbff; valaddr_reg:x2; val_offset:20961*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20961*FLEN/8, x3, x1, x4) + +inst_7022: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x2; +op3val:0x7c00; valaddr_reg:x2; val_offset:20964*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20964*FLEN/8, x3, x1, x4) + +inst_7023: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x2; +op3val:0xfc00; valaddr_reg:x2; val_offset:20967*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20967*FLEN/8, x3, x1, x4) + +inst_7024: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x2; +op3val:0x7e00; valaddr_reg:x2; val_offset:20970*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20970*FLEN/8, x3, x1, x4) + +inst_7025: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x2; +op3val:0xfe00; valaddr_reg:x2; val_offset:20973*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20973*FLEN/8, x3, x1, x4) + +inst_7026: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x2; +op3val:0x7e01; valaddr_reg:x2; val_offset:20976*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20976*FLEN/8, x3, x1, x4) + +inst_7027: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x2; +op3val:0xfe55; valaddr_reg:x2; val_offset:20979*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20979*FLEN/8, x3, x1, x4) + +inst_7028: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x2; +op3val:0x7c01; valaddr_reg:x2; val_offset:20982*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20982*FLEN/8, x3, x1, x4) + +inst_7029: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x2; +op3val:0xfd55; valaddr_reg:x2; val_offset:20985*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20985*FLEN/8, x3, x1, x4) + +inst_7030: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x2; +op3val:0x3c00; valaddr_reg:x2; val_offset:20988*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20988*FLEN/8, x3, x1, x4) + +inst_7031: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x2; +op3val:0xbc00; valaddr_reg:x2; val_offset:20991*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20991*FLEN/8, x3, x1, x4) + +inst_7032: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x83fe; +op3val:0x0; valaddr_reg:x2; val_offset:20994*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20994*FLEN/8, x3, x1, x4) + +inst_7033: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x83fe; +op3val:0x8000; valaddr_reg:x2; val_offset:20997*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 20997*FLEN/8, x3, x1, x4) + +inst_7034: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x83fe; +op3val:0x1; valaddr_reg:x2; val_offset:21000*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21000*FLEN/8, x3, x1, x4) + +inst_7035: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x83fe; +op3val:0x8001; valaddr_reg:x2; val_offset:21003*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21003*FLEN/8, x3, x1, x4) + +inst_7036: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x83fe; +op3val:0x2; valaddr_reg:x2; val_offset:21006*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21006*FLEN/8, x3, x1, x4) + +inst_7037: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x83fe; +op3val:0x83fe; valaddr_reg:x2; val_offset:21009*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21009*FLEN/8, x3, x1, x4) + +inst_7038: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x83fe; +op3val:0x3ff; valaddr_reg:x2; val_offset:21012*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21012*FLEN/8, x3, x1, x4) + +inst_7039: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x83fe; +op3val:0x83ff; valaddr_reg:x2; val_offset:21015*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21015*FLEN/8, x3, x1, x4) + +inst_7040: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x83fe; +op3val:0x400; valaddr_reg:x2; val_offset:21018*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21018*FLEN/8, x3, x1, x4) + +inst_7041: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x83fe; +op3val:0x8400; valaddr_reg:x2; val_offset:21021*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21021*FLEN/8, x3, x1, x4) + +inst_7042: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x83fe; +op3val:0x401; valaddr_reg:x2; val_offset:21024*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21024*FLEN/8, x3, x1, x4) + +inst_7043: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x83fe; +op3val:0x8455; valaddr_reg:x2; val_offset:21027*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21027*FLEN/8, x3, x1, x4) + +inst_7044: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x83fe; +op3val:0x7bff; valaddr_reg:x2; val_offset:21030*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21030*FLEN/8, x3, x1, x4) + +inst_7045: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x83fe; +op3val:0xfbff; valaddr_reg:x2; val_offset:21033*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21033*FLEN/8, x3, x1, x4) + +inst_7046: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x83fe; +op3val:0x7c00; valaddr_reg:x2; val_offset:21036*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21036*FLEN/8, x3, x1, x4) + +inst_7047: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x83fe; +op3val:0xfc00; valaddr_reg:x2; val_offset:21039*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21039*FLEN/8, x3, x1, x4) + +inst_7048: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x83fe; +op3val:0x7e00; valaddr_reg:x2; val_offset:21042*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21042*FLEN/8, x3, x1, x4) + +inst_7049: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x83fe; +op3val:0xfe00; valaddr_reg:x2; val_offset:21045*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21045*FLEN/8, x3, x1, x4) + +inst_7050: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x83fe; +op3val:0x7e01; valaddr_reg:x2; val_offset:21048*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21048*FLEN/8, x3, x1, x4) + +inst_7051: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x83fe; +op3val:0xfe55; valaddr_reg:x2; val_offset:21051*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21051*FLEN/8, x3, x1, x4) + +inst_7052: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x83fe; +op3val:0x7c01; valaddr_reg:x2; val_offset:21054*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21054*FLEN/8, x3, x1, x4) + +inst_7053: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x83fe; +op3val:0xfd55; valaddr_reg:x2; val_offset:21057*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21057*FLEN/8, x3, x1, x4) + +inst_7054: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x83fe; +op3val:0x3c00; valaddr_reg:x2; val_offset:21060*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21060*FLEN/8, x3, x1, x4) + +inst_7055: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x83fe; +op3val:0xbc00; valaddr_reg:x2; val_offset:21063*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21063*FLEN/8, x3, x1, x4) + +inst_7056: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x3ff; +op3val:0x0; valaddr_reg:x2; val_offset:21066*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21066*FLEN/8, x3, x1, x4) + +inst_7057: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x3ff; +op3val:0x8000; valaddr_reg:x2; val_offset:21069*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21069*FLEN/8, x3, x1, x4) + +inst_7058: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x3ff; +op3val:0x1; valaddr_reg:x2; val_offset:21072*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21072*FLEN/8, x3, x1, x4) + +inst_7059: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x3ff; +op3val:0x8001; valaddr_reg:x2; val_offset:21075*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21075*FLEN/8, x3, x1, x4) + +inst_7060: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x3ff; +op3val:0x2; valaddr_reg:x2; val_offset:21078*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21078*FLEN/8, x3, x1, x4) + +inst_7061: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x3ff; +op3val:0x83fe; valaddr_reg:x2; val_offset:21081*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21081*FLEN/8, x3, x1, x4) + +inst_7062: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x3ff; +op3val:0x3ff; valaddr_reg:x2; val_offset:21084*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21084*FLEN/8, x3, x1, x4) + +inst_7063: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x3ff; +op3val:0x83ff; valaddr_reg:x2; val_offset:21087*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21087*FLEN/8, x3, x1, x4) + +inst_7064: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x3ff; +op3val:0x400; valaddr_reg:x2; val_offset:21090*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21090*FLEN/8, x3, x1, x4) + +inst_7065: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x3ff; +op3val:0x8400; valaddr_reg:x2; val_offset:21093*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21093*FLEN/8, x3, x1, x4) + +inst_7066: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x3ff; +op3val:0x401; valaddr_reg:x2; val_offset:21096*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21096*FLEN/8, x3, x1, x4) + +inst_7067: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x3ff; +op3val:0x8455; valaddr_reg:x2; val_offset:21099*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21099*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_56) + +inst_7068: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x3ff; +op3val:0x7bff; valaddr_reg:x2; val_offset:21102*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21102*FLEN/8, x3, x1, x4) + +inst_7069: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x3ff; +op3val:0xfbff; valaddr_reg:x2; val_offset:21105*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21105*FLEN/8, x3, x1, x4) + +inst_7070: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x3ff; +op3val:0x7c00; valaddr_reg:x2; val_offset:21108*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21108*FLEN/8, x3, x1, x4) + +inst_7071: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x3ff; +op3val:0xfc00; valaddr_reg:x2; val_offset:21111*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21111*FLEN/8, x3, x1, x4) + +inst_7072: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x3ff; +op3val:0x7e00; valaddr_reg:x2; val_offset:21114*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21114*FLEN/8, x3, x1, x4) + +inst_7073: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x3ff; +op3val:0xfe00; valaddr_reg:x2; val_offset:21117*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21117*FLEN/8, x3, x1, x4) + +inst_7074: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x3ff; +op3val:0x7e01; valaddr_reg:x2; val_offset:21120*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21120*FLEN/8, x3, x1, x4) + +inst_7075: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x3ff; +op3val:0xfe55; valaddr_reg:x2; val_offset:21123*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21123*FLEN/8, x3, x1, x4) + +inst_7076: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x3ff; +op3val:0x7c01; valaddr_reg:x2; val_offset:21126*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21126*FLEN/8, x3, x1, x4) + +inst_7077: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x3ff; +op3val:0xfd55; valaddr_reg:x2; val_offset:21129*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21129*FLEN/8, x3, x1, x4) + +inst_7078: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x3ff; +op3val:0x3c00; valaddr_reg:x2; val_offset:21132*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21132*FLEN/8, x3, x1, x4) + +inst_7079: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x3ff; +op3val:0xbc00; valaddr_reg:x2; val_offset:21135*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21135*FLEN/8, x3, x1, x4) + +inst_7080: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x83ff; +op3val:0x0; valaddr_reg:x2; val_offset:21138*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21138*FLEN/8, x3, x1, x4) + +inst_7081: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x83ff; +op3val:0x8000; valaddr_reg:x2; val_offset:21141*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21141*FLEN/8, x3, x1, x4) + +inst_7082: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x83ff; +op3val:0x1; valaddr_reg:x2; val_offset:21144*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21144*FLEN/8, x3, x1, x4) + +inst_7083: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x83ff; +op3val:0x8001; valaddr_reg:x2; val_offset:21147*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21147*FLEN/8, x3, x1, x4) + +inst_7084: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x83ff; +op3val:0x2; valaddr_reg:x2; val_offset:21150*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21150*FLEN/8, x3, x1, x4) + +inst_7085: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x83ff; +op3val:0x83fe; valaddr_reg:x2; val_offset:21153*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21153*FLEN/8, x3, x1, x4) + +inst_7086: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x83ff; +op3val:0x3ff; valaddr_reg:x2; val_offset:21156*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21156*FLEN/8, x3, x1, x4) + +inst_7087: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x83ff; +op3val:0x83ff; valaddr_reg:x2; val_offset:21159*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21159*FLEN/8, x3, x1, x4) + +inst_7088: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x83ff; +op3val:0x400; valaddr_reg:x2; val_offset:21162*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21162*FLEN/8, x3, x1, x4) + +inst_7089: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x83ff; +op3val:0x8400; valaddr_reg:x2; val_offset:21165*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21165*FLEN/8, x3, x1, x4) + +inst_7090: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x83ff; +op3val:0x401; valaddr_reg:x2; val_offset:21168*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21168*FLEN/8, x3, x1, x4) + +inst_7091: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x83ff; +op3val:0x8455; valaddr_reg:x2; val_offset:21171*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21171*FLEN/8, x3, x1, x4) + +inst_7092: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x83ff; +op3val:0x7bff; valaddr_reg:x2; val_offset:21174*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21174*FLEN/8, x3, x1, x4) + +inst_7093: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x83ff; +op3val:0xfbff; valaddr_reg:x2; val_offset:21177*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21177*FLEN/8, x3, x1, x4) + +inst_7094: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x83ff; +op3val:0x7c00; valaddr_reg:x2; val_offset:21180*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21180*FLEN/8, x3, x1, x4) + +inst_7095: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x83ff; +op3val:0xfc00; valaddr_reg:x2; val_offset:21183*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21183*FLEN/8, x3, x1, x4) + +inst_7096: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x83ff; +op3val:0x7e00; valaddr_reg:x2; val_offset:21186*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21186*FLEN/8, x3, x1, x4) + +inst_7097: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x83ff; +op3val:0xfe00; valaddr_reg:x2; val_offset:21189*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21189*FLEN/8, x3, x1, x4) + +inst_7098: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x83ff; +op3val:0x7e01; valaddr_reg:x2; val_offset:21192*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21192*FLEN/8, x3, x1, x4) + +inst_7099: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x83ff; +op3val:0xfe55; valaddr_reg:x2; val_offset:21195*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21195*FLEN/8, x3, x1, x4) + +inst_7100: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x83ff; +op3val:0x7c01; valaddr_reg:x2; val_offset:21198*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21198*FLEN/8, x3, x1, x4) + +inst_7101: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x83ff; +op3val:0xfd55; valaddr_reg:x2; val_offset:21201*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21201*FLEN/8, x3, x1, x4) + +inst_7102: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x83ff; +op3val:0x3c00; valaddr_reg:x2; val_offset:21204*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21204*FLEN/8, x3, x1, x4) + +inst_7103: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x83ff; +op3val:0xbc00; valaddr_reg:x2; val_offset:21207*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21207*FLEN/8, x3, x1, x4) + +inst_7104: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x400; +op3val:0x0; valaddr_reg:x2; val_offset:21210*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21210*FLEN/8, x3, x1, x4) + +inst_7105: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x400; +op3val:0x8000; valaddr_reg:x2; val_offset:21213*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21213*FLEN/8, x3, x1, x4) + +inst_7106: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x400; +op3val:0x1; valaddr_reg:x2; val_offset:21216*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21216*FLEN/8, x3, x1, x4) + +inst_7107: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x400; +op3val:0x8001; valaddr_reg:x2; val_offset:21219*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21219*FLEN/8, x3, x1, x4) + +inst_7108: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x400; +op3val:0x2; valaddr_reg:x2; val_offset:21222*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21222*FLEN/8, x3, x1, x4) + +inst_7109: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x400; +op3val:0x83fe; valaddr_reg:x2; val_offset:21225*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21225*FLEN/8, x3, x1, x4) + +inst_7110: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x400; +op3val:0x3ff; valaddr_reg:x2; val_offset:21228*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21228*FLEN/8, x3, x1, x4) + +inst_7111: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x400; +op3val:0x83ff; valaddr_reg:x2; val_offset:21231*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21231*FLEN/8, x3, x1, x4) + +inst_7112: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x400; +op3val:0x400; valaddr_reg:x2; val_offset:21234*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21234*FLEN/8, x3, x1, x4) + +inst_7113: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x400; +op3val:0x8400; valaddr_reg:x2; val_offset:21237*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21237*FLEN/8, x3, x1, x4) + +inst_7114: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x400; +op3val:0x401; valaddr_reg:x2; val_offset:21240*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21240*FLEN/8, x3, x1, x4) + +inst_7115: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x400; +op3val:0x8455; valaddr_reg:x2; val_offset:21243*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21243*FLEN/8, x3, x1, x4) + +inst_7116: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x400; +op3val:0x7bff; valaddr_reg:x2; val_offset:21246*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21246*FLEN/8, x3, x1, x4) + +inst_7117: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x400; +op3val:0xfbff; valaddr_reg:x2; val_offset:21249*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21249*FLEN/8, x3, x1, x4) + +inst_7118: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x400; +op3val:0x7c00; valaddr_reg:x2; val_offset:21252*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21252*FLEN/8, x3, x1, x4) + +inst_7119: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x400; +op3val:0xfc00; valaddr_reg:x2; val_offset:21255*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21255*FLEN/8, x3, x1, x4) + +inst_7120: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x400; +op3val:0x7e00; valaddr_reg:x2; val_offset:21258*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21258*FLEN/8, x3, x1, x4) + +inst_7121: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x400; +op3val:0xfe00; valaddr_reg:x2; val_offset:21261*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21261*FLEN/8, x3, x1, x4) + +inst_7122: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x400; +op3val:0x7e01; valaddr_reg:x2; val_offset:21264*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21264*FLEN/8, x3, x1, x4) + +inst_7123: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x400; +op3val:0xfe55; valaddr_reg:x2; val_offset:21267*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21267*FLEN/8, x3, x1, x4) + +inst_7124: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x400; +op3val:0x7c01; valaddr_reg:x2; val_offset:21270*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21270*FLEN/8, x3, x1, x4) + +inst_7125: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x400; +op3val:0xfd55; valaddr_reg:x2; val_offset:21273*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21273*FLEN/8, x3, x1, x4) + +inst_7126: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x400; +op3val:0x3c00; valaddr_reg:x2; val_offset:21276*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21276*FLEN/8, x3, x1, x4) + +inst_7127: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x400; +op3val:0xbc00; valaddr_reg:x2; val_offset:21279*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21279*FLEN/8, x3, x1, x4) + +inst_7128: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8400; +op3val:0x0; valaddr_reg:x2; val_offset:21282*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21282*FLEN/8, x3, x1, x4) + +inst_7129: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8400; +op3val:0x8000; valaddr_reg:x2; val_offset:21285*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21285*FLEN/8, x3, x1, x4) + +inst_7130: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8400; +op3val:0x1; valaddr_reg:x2; val_offset:21288*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21288*FLEN/8, x3, x1, x4) + +inst_7131: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8400; +op3val:0x8001; valaddr_reg:x2; val_offset:21291*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21291*FLEN/8, x3, x1, x4) + +inst_7132: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8400; +op3val:0x2; valaddr_reg:x2; val_offset:21294*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21294*FLEN/8, x3, x1, x4) + +inst_7133: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8400; +op3val:0x83fe; valaddr_reg:x2; val_offset:21297*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21297*FLEN/8, x3, x1, x4) + +inst_7134: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8400; +op3val:0x3ff; valaddr_reg:x2; val_offset:21300*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21300*FLEN/8, x3, x1, x4) + +inst_7135: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8400; +op3val:0x83ff; valaddr_reg:x2; val_offset:21303*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21303*FLEN/8, x3, x1, x4) + +inst_7136: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8400; +op3val:0x400; valaddr_reg:x2; val_offset:21306*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21306*FLEN/8, x3, x1, x4) + +inst_7137: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8400; +op3val:0x8400; valaddr_reg:x2; val_offset:21309*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21309*FLEN/8, x3, x1, x4) + +inst_7138: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8400; +op3val:0x401; valaddr_reg:x2; val_offset:21312*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21312*FLEN/8, x3, x1, x4) + +inst_7139: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8400; +op3val:0x8455; valaddr_reg:x2; val_offset:21315*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21315*FLEN/8, x3, x1, x4) + +inst_7140: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8400; +op3val:0x7bff; valaddr_reg:x2; val_offset:21318*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21318*FLEN/8, x3, x1, x4) + +inst_7141: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8400; +op3val:0xfbff; valaddr_reg:x2; val_offset:21321*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21321*FLEN/8, x3, x1, x4) + +inst_7142: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8400; +op3val:0x7c00; valaddr_reg:x2; val_offset:21324*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21324*FLEN/8, x3, x1, x4) + +inst_7143: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8400; +op3val:0xfc00; valaddr_reg:x2; val_offset:21327*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21327*FLEN/8, x3, x1, x4) + +inst_7144: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8400; +op3val:0x7e00; valaddr_reg:x2; val_offset:21330*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21330*FLEN/8, x3, x1, x4) + +inst_7145: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8400; +op3val:0xfe00; valaddr_reg:x2; val_offset:21333*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21333*FLEN/8, x3, x1, x4) + +inst_7146: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8400; +op3val:0x7e01; valaddr_reg:x2; val_offset:21336*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21336*FLEN/8, x3, x1, x4) + +inst_7147: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8400; +op3val:0xfe55; valaddr_reg:x2; val_offset:21339*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21339*FLEN/8, x3, x1, x4) + +inst_7148: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8400; +op3val:0x7c01; valaddr_reg:x2; val_offset:21342*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21342*FLEN/8, x3, x1, x4) + +inst_7149: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8400; +op3val:0xfd55; valaddr_reg:x2; val_offset:21345*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21345*FLEN/8, x3, x1, x4) + +inst_7150: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8400; +op3val:0x3c00; valaddr_reg:x2; val_offset:21348*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21348*FLEN/8, x3, x1, x4) + +inst_7151: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8400; +op3val:0xbc00; valaddr_reg:x2; val_offset:21351*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21351*FLEN/8, x3, x1, x4) + +inst_7152: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x401; +op3val:0x0; valaddr_reg:x2; val_offset:21354*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21354*FLEN/8, x3, x1, x4) + +inst_7153: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x401; +op3val:0x8000; valaddr_reg:x2; val_offset:21357*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21357*FLEN/8, x3, x1, x4) + +inst_7154: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x401; +op3val:0x1; valaddr_reg:x2; val_offset:21360*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21360*FLEN/8, x3, x1, x4) + +inst_7155: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x401; +op3val:0x8001; valaddr_reg:x2; val_offset:21363*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21363*FLEN/8, x3, x1, x4) + +inst_7156: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x401; +op3val:0x2; valaddr_reg:x2; val_offset:21366*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21366*FLEN/8, x3, x1, x4) + +inst_7157: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x401; +op3val:0x83fe; valaddr_reg:x2; val_offset:21369*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21369*FLEN/8, x3, x1, x4) + +inst_7158: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x401; +op3val:0x3ff; valaddr_reg:x2; val_offset:21372*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21372*FLEN/8, x3, x1, x4) + +inst_7159: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x401; +op3val:0x83ff; valaddr_reg:x2; val_offset:21375*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21375*FLEN/8, x3, x1, x4) + +inst_7160: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x401; +op3val:0x400; valaddr_reg:x2; val_offset:21378*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21378*FLEN/8, x3, x1, x4) + +inst_7161: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x401; +op3val:0x8400; valaddr_reg:x2; val_offset:21381*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21381*FLEN/8, x3, x1, x4) + +inst_7162: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x401; +op3val:0x401; valaddr_reg:x2; val_offset:21384*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21384*FLEN/8, x3, x1, x4) + +inst_7163: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x401; +op3val:0x8455; valaddr_reg:x2; val_offset:21387*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21387*FLEN/8, x3, x1, x4) + +inst_7164: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x401; +op3val:0x7bff; valaddr_reg:x2; val_offset:21390*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21390*FLEN/8, x3, x1, x4) + +inst_7165: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x401; +op3val:0xfbff; valaddr_reg:x2; val_offset:21393*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21393*FLEN/8, x3, x1, x4) + +inst_7166: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x401; +op3val:0x7c00; valaddr_reg:x2; val_offset:21396*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21396*FLEN/8, x3, x1, x4) + +inst_7167: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x401; +op3val:0xfc00; valaddr_reg:x2; val_offset:21399*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21399*FLEN/8, x3, x1, x4) + +inst_7168: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x401; +op3val:0x7e00; valaddr_reg:x2; val_offset:21402*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21402*FLEN/8, x3, x1, x4) + +inst_7169: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x401; +op3val:0xfe00; valaddr_reg:x2; val_offset:21405*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21405*FLEN/8, x3, x1, x4) + +inst_7170: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x401; +op3val:0x7e01; valaddr_reg:x2; val_offset:21408*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21408*FLEN/8, x3, x1, x4) + +inst_7171: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x401; +op3val:0xfe55; valaddr_reg:x2; val_offset:21411*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21411*FLEN/8, x3, x1, x4) + +inst_7172: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x401; +op3val:0x7c01; valaddr_reg:x2; val_offset:21414*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21414*FLEN/8, x3, x1, x4) + +inst_7173: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x401; +op3val:0xfd55; valaddr_reg:x2; val_offset:21417*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21417*FLEN/8, x3, x1, x4) + +inst_7174: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x401; +op3val:0x3c00; valaddr_reg:x2; val_offset:21420*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21420*FLEN/8, x3, x1, x4) + +inst_7175: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x401; +op3val:0xbc00; valaddr_reg:x2; val_offset:21423*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21423*FLEN/8, x3, x1, x4) + +inst_7176: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8455; +op3val:0x0; valaddr_reg:x2; val_offset:21426*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21426*FLEN/8, x3, x1, x4) + +inst_7177: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8455; +op3val:0x8000; valaddr_reg:x2; val_offset:21429*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21429*FLEN/8, x3, x1, x4) + +inst_7178: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8455; +op3val:0x1; valaddr_reg:x2; val_offset:21432*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21432*FLEN/8, x3, x1, x4) + +inst_7179: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8455; +op3val:0x8001; valaddr_reg:x2; val_offset:21435*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21435*FLEN/8, x3, x1, x4) + +inst_7180: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8455; +op3val:0x2; valaddr_reg:x2; val_offset:21438*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21438*FLEN/8, x3, x1, x4) + +inst_7181: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8455; +op3val:0x83fe; valaddr_reg:x2; val_offset:21441*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21441*FLEN/8, x3, x1, x4) + +inst_7182: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8455; +op3val:0x3ff; valaddr_reg:x2; val_offset:21444*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21444*FLEN/8, x3, x1, x4) + +inst_7183: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8455; +op3val:0x83ff; valaddr_reg:x2; val_offset:21447*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21447*FLEN/8, x3, x1, x4) + +inst_7184: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8455; +op3val:0x400; valaddr_reg:x2; val_offset:21450*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21450*FLEN/8, x3, x1, x4) + +inst_7185: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8455; +op3val:0x8400; valaddr_reg:x2; val_offset:21453*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21453*FLEN/8, x3, x1, x4) + +inst_7186: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8455; +op3val:0x401; valaddr_reg:x2; val_offset:21456*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21456*FLEN/8, x3, x1, x4) + +inst_7187: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8455; +op3val:0x8455; valaddr_reg:x2; val_offset:21459*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21459*FLEN/8, x3, x1, x4) + +inst_7188: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8455; +op3val:0x7bff; valaddr_reg:x2; val_offset:21462*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21462*FLEN/8, x3, x1, x4) + +inst_7189: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8455; +op3val:0xfbff; valaddr_reg:x2; val_offset:21465*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21465*FLEN/8, x3, x1, x4) + +inst_7190: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8455; +op3val:0x7c00; valaddr_reg:x2; val_offset:21468*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21468*FLEN/8, x3, x1, x4) + +inst_7191: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8455; +op3val:0xfc00; valaddr_reg:x2; val_offset:21471*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21471*FLEN/8, x3, x1, x4) + +inst_7192: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8455; +op3val:0x7e00; valaddr_reg:x2; val_offset:21474*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21474*FLEN/8, x3, x1, x4) + +inst_7193: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8455; +op3val:0xfe00; valaddr_reg:x2; val_offset:21477*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21477*FLEN/8, x3, x1, x4) + +inst_7194: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8455; +op3val:0x7e01; valaddr_reg:x2; val_offset:21480*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21480*FLEN/8, x3, x1, x4) + +inst_7195: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8455; +op3val:0xfe55; valaddr_reg:x2; val_offset:21483*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21483*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_57) + +inst_7196: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8455; +op3val:0x7c01; valaddr_reg:x2; val_offset:21486*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21486*FLEN/8, x3, x1, x4) + +inst_7197: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8455; +op3val:0xfd55; valaddr_reg:x2; val_offset:21489*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21489*FLEN/8, x3, x1, x4) + +inst_7198: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8455; +op3val:0x3c00; valaddr_reg:x2; val_offset:21492*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21492*FLEN/8, x3, x1, x4) + +inst_7199: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x8455; +op3val:0xbc00; valaddr_reg:x2; val_offset:21495*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21495*FLEN/8, x3, x1, x4) + +inst_7200: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7bff; +op3val:0x0; valaddr_reg:x2; val_offset:21498*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21498*FLEN/8, x3, x1, x4) + +inst_7201: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7bff; +op3val:0x8000; valaddr_reg:x2; val_offset:21501*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21501*FLEN/8, x3, x1, x4) + +inst_7202: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7bff; +op3val:0x1; valaddr_reg:x2; val_offset:21504*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21504*FLEN/8, x3, x1, x4) + +inst_7203: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7bff; +op3val:0x8001; valaddr_reg:x2; val_offset:21507*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21507*FLEN/8, x3, x1, x4) + +inst_7204: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7bff; +op3val:0x2; valaddr_reg:x2; val_offset:21510*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21510*FLEN/8, x3, x1, x4) + +inst_7205: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7bff; +op3val:0x83fe; valaddr_reg:x2; val_offset:21513*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21513*FLEN/8, x3, x1, x4) + +inst_7206: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7bff; +op3val:0x3ff; valaddr_reg:x2; val_offset:21516*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21516*FLEN/8, x3, x1, x4) + +inst_7207: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7bff; +op3val:0x83ff; valaddr_reg:x2; val_offset:21519*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21519*FLEN/8, x3, x1, x4) + +inst_7208: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7bff; +op3val:0x400; valaddr_reg:x2; val_offset:21522*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21522*FLEN/8, x3, x1, x4) + +inst_7209: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7bff; +op3val:0x8400; valaddr_reg:x2; val_offset:21525*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21525*FLEN/8, x3, x1, x4) + +inst_7210: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7bff; +op3val:0x401; valaddr_reg:x2; val_offset:21528*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21528*FLEN/8, x3, x1, x4) + +inst_7211: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7bff; +op3val:0x8455; valaddr_reg:x2; val_offset:21531*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21531*FLEN/8, x3, x1, x4) + +inst_7212: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7bff; +op3val:0x7bff; valaddr_reg:x2; val_offset:21534*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21534*FLEN/8, x3, x1, x4) + +inst_7213: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7bff; +op3val:0xfbff; valaddr_reg:x2; val_offset:21537*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21537*FLEN/8, x3, x1, x4) + +inst_7214: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7bff; +op3val:0x7c00; valaddr_reg:x2; val_offset:21540*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21540*FLEN/8, x3, x1, x4) + +inst_7215: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7bff; +op3val:0xfc00; valaddr_reg:x2; val_offset:21543*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21543*FLEN/8, x3, x1, x4) + +inst_7216: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7bff; +op3val:0x7e00; valaddr_reg:x2; val_offset:21546*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21546*FLEN/8, x3, x1, x4) + +inst_7217: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7bff; +op3val:0xfe00; valaddr_reg:x2; val_offset:21549*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21549*FLEN/8, x3, x1, x4) + +inst_7218: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7bff; +op3val:0x7e01; valaddr_reg:x2; val_offset:21552*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21552*FLEN/8, x3, x1, x4) + +inst_7219: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7bff; +op3val:0xfe55; valaddr_reg:x2; val_offset:21555*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21555*FLEN/8, x3, x1, x4) + +inst_7220: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7bff; +op3val:0x7c01; valaddr_reg:x2; val_offset:21558*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21558*FLEN/8, x3, x1, x4) + +inst_7221: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7bff; +op3val:0xfd55; valaddr_reg:x2; val_offset:21561*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21561*FLEN/8, x3, x1, x4) + +inst_7222: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7bff; +op3val:0x3c00; valaddr_reg:x2; val_offset:21564*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21564*FLEN/8, x3, x1, x4) + +inst_7223: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7bff; +op3val:0xbc00; valaddr_reg:x2; val_offset:21567*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21567*FLEN/8, x3, x1, x4) + +inst_7224: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfbff; +op3val:0x0; valaddr_reg:x2; val_offset:21570*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21570*FLEN/8, x3, x1, x4) + +inst_7225: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfbff; +op3val:0x8000; valaddr_reg:x2; val_offset:21573*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21573*FLEN/8, x3, x1, x4) + +inst_7226: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfbff; +op3val:0x1; valaddr_reg:x2; val_offset:21576*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21576*FLEN/8, x3, x1, x4) + +inst_7227: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfbff; +op3val:0x8001; valaddr_reg:x2; val_offset:21579*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21579*FLEN/8, x3, x1, x4) + +inst_7228: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfbff; +op3val:0x2; valaddr_reg:x2; val_offset:21582*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21582*FLEN/8, x3, x1, x4) + +inst_7229: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfbff; +op3val:0x83fe; valaddr_reg:x2; val_offset:21585*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21585*FLEN/8, x3, x1, x4) + +inst_7230: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfbff; +op3val:0x3ff; valaddr_reg:x2; val_offset:21588*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21588*FLEN/8, x3, x1, x4) + +inst_7231: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfbff; +op3val:0x83ff; valaddr_reg:x2; val_offset:21591*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21591*FLEN/8, x3, x1, x4) + +inst_7232: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfbff; +op3val:0x400; valaddr_reg:x2; val_offset:21594*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21594*FLEN/8, x3, x1, x4) + +inst_7233: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfbff; +op3val:0x8400; valaddr_reg:x2; val_offset:21597*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21597*FLEN/8, x3, x1, x4) + +inst_7234: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfbff; +op3val:0x401; valaddr_reg:x2; val_offset:21600*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21600*FLEN/8, x3, x1, x4) + +inst_7235: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfbff; +op3val:0x8455; valaddr_reg:x2; val_offset:21603*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21603*FLEN/8, x3, x1, x4) + +inst_7236: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfbff; +op3val:0x7bff; valaddr_reg:x2; val_offset:21606*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21606*FLEN/8, x3, x1, x4) + +inst_7237: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfbff; +op3val:0xfbff; valaddr_reg:x2; val_offset:21609*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21609*FLEN/8, x3, x1, x4) + +inst_7238: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfbff; +op3val:0x7c00; valaddr_reg:x2; val_offset:21612*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21612*FLEN/8, x3, x1, x4) + +inst_7239: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfbff; +op3val:0xfc00; valaddr_reg:x2; val_offset:21615*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21615*FLEN/8, x3, x1, x4) + +inst_7240: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfbff; +op3val:0x7e00; valaddr_reg:x2; val_offset:21618*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21618*FLEN/8, x3, x1, x4) + +inst_7241: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfbff; +op3val:0xfe00; valaddr_reg:x2; val_offset:21621*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21621*FLEN/8, x3, x1, x4) + +inst_7242: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfbff; +op3val:0x7e01; valaddr_reg:x2; val_offset:21624*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21624*FLEN/8, x3, x1, x4) + +inst_7243: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfbff; +op3val:0xfe55; valaddr_reg:x2; val_offset:21627*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21627*FLEN/8, x3, x1, x4) + +inst_7244: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfbff; +op3val:0x7c01; valaddr_reg:x2; val_offset:21630*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21630*FLEN/8, x3, x1, x4) + +inst_7245: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfbff; +op3val:0xfd55; valaddr_reg:x2; val_offset:21633*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21633*FLEN/8, x3, x1, x4) + +inst_7246: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfbff; +op3val:0x3c00; valaddr_reg:x2; val_offset:21636*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21636*FLEN/8, x3, x1, x4) + +inst_7247: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfbff; +op3val:0xbc00; valaddr_reg:x2; val_offset:21639*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21639*FLEN/8, x3, x1, x4) + +inst_7248: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7c00; +op3val:0x0; valaddr_reg:x2; val_offset:21642*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21642*FLEN/8, x3, x1, x4) + +inst_7249: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7c00; +op3val:0x8000; valaddr_reg:x2; val_offset:21645*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21645*FLEN/8, x3, x1, x4) + +inst_7250: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7c00; +op3val:0x1; valaddr_reg:x2; val_offset:21648*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21648*FLEN/8, x3, x1, x4) + +inst_7251: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7c00; +op3val:0x8001; valaddr_reg:x2; val_offset:21651*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21651*FLEN/8, x3, x1, x4) + +inst_7252: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7c00; +op3val:0x2; valaddr_reg:x2; val_offset:21654*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21654*FLEN/8, x3, x1, x4) + +inst_7253: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7c00; +op3val:0x83fe; valaddr_reg:x2; val_offset:21657*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21657*FLEN/8, x3, x1, x4) + +inst_7254: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7c00; +op3val:0x3ff; valaddr_reg:x2; val_offset:21660*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21660*FLEN/8, x3, x1, x4) + +inst_7255: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7c00; +op3val:0x83ff; valaddr_reg:x2; val_offset:21663*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21663*FLEN/8, x3, x1, x4) + +inst_7256: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7c00; +op3val:0x400; valaddr_reg:x2; val_offset:21666*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21666*FLEN/8, x3, x1, x4) + +inst_7257: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7c00; +op3val:0x8400; valaddr_reg:x2; val_offset:21669*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21669*FLEN/8, x3, x1, x4) + +inst_7258: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7c00; +op3val:0x401; valaddr_reg:x2; val_offset:21672*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21672*FLEN/8, x3, x1, x4) + +inst_7259: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7c00; +op3val:0x8455; valaddr_reg:x2; val_offset:21675*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21675*FLEN/8, x3, x1, x4) + +inst_7260: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7c00; +op3val:0x7bff; valaddr_reg:x2; val_offset:21678*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21678*FLEN/8, x3, x1, x4) + +inst_7261: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7c00; +op3val:0xfbff; valaddr_reg:x2; val_offset:21681*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21681*FLEN/8, x3, x1, x4) + +inst_7262: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7c00; +op3val:0x7c00; valaddr_reg:x2; val_offset:21684*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21684*FLEN/8, x3, x1, x4) + +inst_7263: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7c00; +op3val:0xfc00; valaddr_reg:x2; val_offset:21687*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21687*FLEN/8, x3, x1, x4) + +inst_7264: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7c00; +op3val:0x7e00; valaddr_reg:x2; val_offset:21690*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21690*FLEN/8, x3, x1, x4) + +inst_7265: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7c00; +op3val:0xfe00; valaddr_reg:x2; val_offset:21693*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21693*FLEN/8, x3, x1, x4) + +inst_7266: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7c00; +op3val:0x7e01; valaddr_reg:x2; val_offset:21696*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21696*FLEN/8, x3, x1, x4) + +inst_7267: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7c00; +op3val:0xfe55; valaddr_reg:x2; val_offset:21699*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21699*FLEN/8, x3, x1, x4) + +inst_7268: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7c00; +op3val:0x7c01; valaddr_reg:x2; val_offset:21702*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21702*FLEN/8, x3, x1, x4) + +inst_7269: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7c00; +op3val:0xfd55; valaddr_reg:x2; val_offset:21705*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21705*FLEN/8, x3, x1, x4) + +inst_7270: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7c00; +op3val:0x3c00; valaddr_reg:x2; val_offset:21708*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21708*FLEN/8, x3, x1, x4) + +inst_7271: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7c00; +op3val:0xbc00; valaddr_reg:x2; val_offset:21711*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21711*FLEN/8, x3, x1, x4) + +inst_7272: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfc00; +op3val:0x0; valaddr_reg:x2; val_offset:21714*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21714*FLEN/8, x3, x1, x4) + +inst_7273: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfc00; +op3val:0x8000; valaddr_reg:x2; val_offset:21717*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21717*FLEN/8, x3, x1, x4) + +inst_7274: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfc00; +op3val:0x1; valaddr_reg:x2; val_offset:21720*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21720*FLEN/8, x3, x1, x4) + +inst_7275: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfc00; +op3val:0x8001; valaddr_reg:x2; val_offset:21723*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21723*FLEN/8, x3, x1, x4) + +inst_7276: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfc00; +op3val:0x2; valaddr_reg:x2; val_offset:21726*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21726*FLEN/8, x3, x1, x4) + +inst_7277: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfc00; +op3val:0x83fe; valaddr_reg:x2; val_offset:21729*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21729*FLEN/8, x3, x1, x4) + +inst_7278: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfc00; +op3val:0x3ff; valaddr_reg:x2; val_offset:21732*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21732*FLEN/8, x3, x1, x4) + +inst_7279: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfc00; +op3val:0x83ff; valaddr_reg:x2; val_offset:21735*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21735*FLEN/8, x3, x1, x4) + +inst_7280: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfc00; +op3val:0x400; valaddr_reg:x2; val_offset:21738*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21738*FLEN/8, x3, x1, x4) + +inst_7281: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfc00; +op3val:0x8400; valaddr_reg:x2; val_offset:21741*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21741*FLEN/8, x3, x1, x4) + +inst_7282: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfc00; +op3val:0x401; valaddr_reg:x2; val_offset:21744*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21744*FLEN/8, x3, x1, x4) + +inst_7283: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfc00; +op3val:0x8455; valaddr_reg:x2; val_offset:21747*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21747*FLEN/8, x3, x1, x4) + +inst_7284: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfc00; +op3val:0x7bff; valaddr_reg:x2; val_offset:21750*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21750*FLEN/8, x3, x1, x4) + +inst_7285: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfc00; +op3val:0xfbff; valaddr_reg:x2; val_offset:21753*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21753*FLEN/8, x3, x1, x4) + +inst_7286: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfc00; +op3val:0x7c00; valaddr_reg:x2; val_offset:21756*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21756*FLEN/8, x3, x1, x4) + +inst_7287: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfc00; +op3val:0xfc00; valaddr_reg:x2; val_offset:21759*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21759*FLEN/8, x3, x1, x4) + +inst_7288: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfc00; +op3val:0x7e00; valaddr_reg:x2; val_offset:21762*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21762*FLEN/8, x3, x1, x4) + +inst_7289: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfc00; +op3val:0xfe00; valaddr_reg:x2; val_offset:21765*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21765*FLEN/8, x3, x1, x4) + +inst_7290: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfc00; +op3val:0x7e01; valaddr_reg:x2; val_offset:21768*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21768*FLEN/8, x3, x1, x4) + +inst_7291: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfc00; +op3val:0xfe55; valaddr_reg:x2; val_offset:21771*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21771*FLEN/8, x3, x1, x4) + +inst_7292: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfc00; +op3val:0x7c01; valaddr_reg:x2; val_offset:21774*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21774*FLEN/8, x3, x1, x4) + +inst_7293: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfc00; +op3val:0xfd55; valaddr_reg:x2; val_offset:21777*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21777*FLEN/8, x3, x1, x4) + +inst_7294: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfc00; +op3val:0x3c00; valaddr_reg:x2; val_offset:21780*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21780*FLEN/8, x3, x1, x4) + +inst_7295: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfc00; +op3val:0xbc00; valaddr_reg:x2; val_offset:21783*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21783*FLEN/8, x3, x1, x4) + +inst_7296: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7e00; +op3val:0x0; valaddr_reg:x2; val_offset:21786*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21786*FLEN/8, x3, x1, x4) + +inst_7297: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7e00; +op3val:0x8000; valaddr_reg:x2; val_offset:21789*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21789*FLEN/8, x3, x1, x4) + +inst_7298: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7e00; +op3val:0x1; valaddr_reg:x2; val_offset:21792*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21792*FLEN/8, x3, x1, x4) + +inst_7299: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7e00; +op3val:0x8001; valaddr_reg:x2; val_offset:21795*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21795*FLEN/8, x3, x1, x4) + +inst_7300: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7e00; +op3val:0x2; valaddr_reg:x2; val_offset:21798*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21798*FLEN/8, x3, x1, x4) + +inst_7301: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7e00; +op3val:0x83fe; valaddr_reg:x2; val_offset:21801*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21801*FLEN/8, x3, x1, x4) + +inst_7302: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7e00; +op3val:0x3ff; valaddr_reg:x2; val_offset:21804*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21804*FLEN/8, x3, x1, x4) + +inst_7303: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7e00; +op3val:0x83ff; valaddr_reg:x2; val_offset:21807*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21807*FLEN/8, x3, x1, x4) + +inst_7304: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7e00; +op3val:0x400; valaddr_reg:x2; val_offset:21810*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21810*FLEN/8, x3, x1, x4) + +inst_7305: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7e00; +op3val:0x8400; valaddr_reg:x2; val_offset:21813*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21813*FLEN/8, x3, x1, x4) + +inst_7306: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7e00; +op3val:0x401; valaddr_reg:x2; val_offset:21816*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21816*FLEN/8, x3, x1, x4) + +inst_7307: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7e00; +op3val:0x8455; valaddr_reg:x2; val_offset:21819*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21819*FLEN/8, x3, x1, x4) + +inst_7308: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7e00; +op3val:0x7bff; valaddr_reg:x2; val_offset:21822*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21822*FLEN/8, x3, x1, x4) + +inst_7309: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7e00; +op3val:0xfbff; valaddr_reg:x2; val_offset:21825*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21825*FLEN/8, x3, x1, x4) + +inst_7310: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7e00; +op3val:0x7c00; valaddr_reg:x2; val_offset:21828*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21828*FLEN/8, x3, x1, x4) + +inst_7311: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7e00; +op3val:0xfc00; valaddr_reg:x2; val_offset:21831*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21831*FLEN/8, x3, x1, x4) + +inst_7312: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7e00; +op3val:0x7e00; valaddr_reg:x2; val_offset:21834*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21834*FLEN/8, x3, x1, x4) + +inst_7313: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7e00; +op3val:0xfe00; valaddr_reg:x2; val_offset:21837*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21837*FLEN/8, x3, x1, x4) + +inst_7314: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7e00; +op3val:0x7e01; valaddr_reg:x2; val_offset:21840*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21840*FLEN/8, x3, x1, x4) + +inst_7315: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7e00; +op3val:0xfe55; valaddr_reg:x2; val_offset:21843*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21843*FLEN/8, x3, x1, x4) + +inst_7316: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7e00; +op3val:0x7c01; valaddr_reg:x2; val_offset:21846*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21846*FLEN/8, x3, x1, x4) + +inst_7317: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7e00; +op3val:0xfd55; valaddr_reg:x2; val_offset:21849*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21849*FLEN/8, x3, x1, x4) + +inst_7318: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7e00; +op3val:0x3c00; valaddr_reg:x2; val_offset:21852*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21852*FLEN/8, x3, x1, x4) + +inst_7319: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7e00; +op3val:0xbc00; valaddr_reg:x2; val_offset:21855*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21855*FLEN/8, x3, x1, x4) + +inst_7320: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfe00; +op3val:0x0; valaddr_reg:x2; val_offset:21858*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21858*FLEN/8, x3, x1, x4) + +inst_7321: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfe00; +op3val:0x8000; valaddr_reg:x2; val_offset:21861*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21861*FLEN/8, x3, x1, x4) + +inst_7322: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfe00; +op3val:0x1; valaddr_reg:x2; val_offset:21864*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21864*FLEN/8, x3, x1, x4) + +inst_7323: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfe00; +op3val:0x8001; valaddr_reg:x2; val_offset:21867*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21867*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_58) + +inst_7324: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfe00; +op3val:0x2; valaddr_reg:x2; val_offset:21870*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21870*FLEN/8, x3, x1, x4) + +inst_7325: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfe00; +op3val:0x83fe; valaddr_reg:x2; val_offset:21873*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21873*FLEN/8, x3, x1, x4) + +inst_7326: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfe00; +op3val:0x3ff; valaddr_reg:x2; val_offset:21876*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21876*FLEN/8, x3, x1, x4) + +inst_7327: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfe00; +op3val:0x83ff; valaddr_reg:x2; val_offset:21879*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21879*FLEN/8, x3, x1, x4) + +inst_7328: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfe00; +op3val:0x400; valaddr_reg:x2; val_offset:21882*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21882*FLEN/8, x3, x1, x4) + +inst_7329: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfe00; +op3val:0x8400; valaddr_reg:x2; val_offset:21885*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21885*FLEN/8, x3, x1, x4) + +inst_7330: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfe00; +op3val:0x401; valaddr_reg:x2; val_offset:21888*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21888*FLEN/8, x3, x1, x4) + +inst_7331: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfe00; +op3val:0x8455; valaddr_reg:x2; val_offset:21891*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21891*FLEN/8, x3, x1, x4) + +inst_7332: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfe00; +op3val:0x7bff; valaddr_reg:x2; val_offset:21894*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21894*FLEN/8, x3, x1, x4) + +inst_7333: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfe00; +op3val:0xfbff; valaddr_reg:x2; val_offset:21897*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21897*FLEN/8, x3, x1, x4) + +inst_7334: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfe00; +op3val:0x7c00; valaddr_reg:x2; val_offset:21900*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21900*FLEN/8, x3, x1, x4) + +inst_7335: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfe00; +op3val:0xfc00; valaddr_reg:x2; val_offset:21903*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21903*FLEN/8, x3, x1, x4) + +inst_7336: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfe00; +op3val:0x7e00; valaddr_reg:x2; val_offset:21906*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21906*FLEN/8, x3, x1, x4) + +inst_7337: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfe00; +op3val:0xfe00; valaddr_reg:x2; val_offset:21909*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21909*FLEN/8, x3, x1, x4) + +inst_7338: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfe00; +op3val:0x7e01; valaddr_reg:x2; val_offset:21912*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21912*FLEN/8, x3, x1, x4) + +inst_7339: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfe00; +op3val:0xfe55; valaddr_reg:x2; val_offset:21915*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21915*FLEN/8, x3, x1, x4) + +inst_7340: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfe00; +op3val:0x7c01; valaddr_reg:x2; val_offset:21918*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21918*FLEN/8, x3, x1, x4) + +inst_7341: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfe00; +op3val:0xfd55; valaddr_reg:x2; val_offset:21921*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21921*FLEN/8, x3, x1, x4) + +inst_7342: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfe00; +op3val:0x3c00; valaddr_reg:x2; val_offset:21924*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21924*FLEN/8, x3, x1, x4) + +inst_7343: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfe00; +op3val:0xbc00; valaddr_reg:x2; val_offset:21927*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21927*FLEN/8, x3, x1, x4) + +inst_7344: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7e01; +op3val:0x0; valaddr_reg:x2; val_offset:21930*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21930*FLEN/8, x3, x1, x4) + +inst_7345: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7e01; +op3val:0x8000; valaddr_reg:x2; val_offset:21933*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21933*FLEN/8, x3, x1, x4) + +inst_7346: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7e01; +op3val:0x1; valaddr_reg:x2; val_offset:21936*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21936*FLEN/8, x3, x1, x4) + +inst_7347: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7e01; +op3val:0x8001; valaddr_reg:x2; val_offset:21939*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21939*FLEN/8, x3, x1, x4) + +inst_7348: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7e01; +op3val:0x2; valaddr_reg:x2; val_offset:21942*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21942*FLEN/8, x3, x1, x4) + +inst_7349: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7e01; +op3val:0x83fe; valaddr_reg:x2; val_offset:21945*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21945*FLEN/8, x3, x1, x4) + +inst_7350: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7e01; +op3val:0x3ff; valaddr_reg:x2; val_offset:21948*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21948*FLEN/8, x3, x1, x4) + +inst_7351: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7e01; +op3val:0x83ff; valaddr_reg:x2; val_offset:21951*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21951*FLEN/8, x3, x1, x4) + +inst_7352: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7e01; +op3val:0x400; valaddr_reg:x2; val_offset:21954*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21954*FLEN/8, x3, x1, x4) + +inst_7353: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7e01; +op3val:0x8400; valaddr_reg:x2; val_offset:21957*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21957*FLEN/8, x3, x1, x4) + +inst_7354: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7e01; +op3val:0x401; valaddr_reg:x2; val_offset:21960*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21960*FLEN/8, x3, x1, x4) + +inst_7355: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7e01; +op3val:0x8455; valaddr_reg:x2; val_offset:21963*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21963*FLEN/8, x3, x1, x4) + +inst_7356: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7e01; +op3val:0x7bff; valaddr_reg:x2; val_offset:21966*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21966*FLEN/8, x3, x1, x4) + +inst_7357: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7e01; +op3val:0xfbff; valaddr_reg:x2; val_offset:21969*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21969*FLEN/8, x3, x1, x4) + +inst_7358: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7e01; +op3val:0x7c00; valaddr_reg:x2; val_offset:21972*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21972*FLEN/8, x3, x1, x4) + +inst_7359: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7e01; +op3val:0xfc00; valaddr_reg:x2; val_offset:21975*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21975*FLEN/8, x3, x1, x4) + +inst_7360: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7e01; +op3val:0x7e00; valaddr_reg:x2; val_offset:21978*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21978*FLEN/8, x3, x1, x4) + +inst_7361: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7e01; +op3val:0xfe00; valaddr_reg:x2; val_offset:21981*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21981*FLEN/8, x3, x1, x4) + +inst_7362: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7e01; +op3val:0x7e01; valaddr_reg:x2; val_offset:21984*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21984*FLEN/8, x3, x1, x4) + +inst_7363: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7e01; +op3val:0xfe55; valaddr_reg:x2; val_offset:21987*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21987*FLEN/8, x3, x1, x4) + +inst_7364: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7e01; +op3val:0x7c01; valaddr_reg:x2; val_offset:21990*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21990*FLEN/8, x3, x1, x4) + +inst_7365: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7e01; +op3val:0xfd55; valaddr_reg:x2; val_offset:21993*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21993*FLEN/8, x3, x1, x4) + +inst_7366: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7e01; +op3val:0x3c00; valaddr_reg:x2; val_offset:21996*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21996*FLEN/8, x3, x1, x4) + +inst_7367: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7e01; +op3val:0xbc00; valaddr_reg:x2; val_offset:21999*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21999*FLEN/8, x3, x1, x4) + +inst_7368: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfe55; +op3val:0x0; valaddr_reg:x2; val_offset:22002*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22002*FLEN/8, x3, x1, x4) + +inst_7369: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfe55; +op3val:0x8000; valaddr_reg:x2; val_offset:22005*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22005*FLEN/8, x3, x1, x4) + +inst_7370: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfe55; +op3val:0x1; valaddr_reg:x2; val_offset:22008*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22008*FLEN/8, x3, x1, x4) + +inst_7371: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfe55; +op3val:0x8001; valaddr_reg:x2; val_offset:22011*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22011*FLEN/8, x3, x1, x4) + +inst_7372: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfe55; +op3val:0x2; valaddr_reg:x2; val_offset:22014*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22014*FLEN/8, x3, x1, x4) + +inst_7373: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfe55; +op3val:0x83fe; valaddr_reg:x2; val_offset:22017*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22017*FLEN/8, x3, x1, x4) + +inst_7374: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfe55; +op3val:0x3ff; valaddr_reg:x2; val_offset:22020*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22020*FLEN/8, x3, x1, x4) + +inst_7375: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfe55; +op3val:0x83ff; valaddr_reg:x2; val_offset:22023*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22023*FLEN/8, x3, x1, x4) + +inst_7376: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfe55; +op3val:0x400; valaddr_reg:x2; val_offset:22026*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22026*FLEN/8, x3, x1, x4) + +inst_7377: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfe55; +op3val:0x8400; valaddr_reg:x2; val_offset:22029*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22029*FLEN/8, x3, x1, x4) + +inst_7378: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfe55; +op3val:0x401; valaddr_reg:x2; val_offset:22032*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22032*FLEN/8, x3, x1, x4) + +inst_7379: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfe55; +op3val:0x8455; valaddr_reg:x2; val_offset:22035*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22035*FLEN/8, x3, x1, x4) + +inst_7380: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfe55; +op3val:0x7bff; valaddr_reg:x2; val_offset:22038*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22038*FLEN/8, x3, x1, x4) + +inst_7381: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfe55; +op3val:0xfbff; valaddr_reg:x2; val_offset:22041*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22041*FLEN/8, x3, x1, x4) + +inst_7382: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfe55; +op3val:0x7c00; valaddr_reg:x2; val_offset:22044*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22044*FLEN/8, x3, x1, x4) + +inst_7383: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfe55; +op3val:0xfc00; valaddr_reg:x2; val_offset:22047*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22047*FLEN/8, x3, x1, x4) + +inst_7384: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfe55; +op3val:0x7e00; valaddr_reg:x2; val_offset:22050*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22050*FLEN/8, x3, x1, x4) + +inst_7385: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfe55; +op3val:0xfe00; valaddr_reg:x2; val_offset:22053*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22053*FLEN/8, x3, x1, x4) + +inst_7386: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfe55; +op3val:0x7e01; valaddr_reg:x2; val_offset:22056*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22056*FLEN/8, x3, x1, x4) + +inst_7387: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfe55; +op3val:0xfe55; valaddr_reg:x2; val_offset:22059*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22059*FLEN/8, x3, x1, x4) + +inst_7388: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfe55; +op3val:0x7c01; valaddr_reg:x2; val_offset:22062*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22062*FLEN/8, x3, x1, x4) + +inst_7389: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfe55; +op3val:0xfd55; valaddr_reg:x2; val_offset:22065*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22065*FLEN/8, x3, x1, x4) + +inst_7390: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfe55; +op3val:0x3c00; valaddr_reg:x2; val_offset:22068*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22068*FLEN/8, x3, x1, x4) + +inst_7391: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfe55; +op3val:0xbc00; valaddr_reg:x2; val_offset:22071*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22071*FLEN/8, x3, x1, x4) + +inst_7392: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7c01; +op3val:0x0; valaddr_reg:x2; val_offset:22074*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22074*FLEN/8, x3, x1, x4) + +inst_7393: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7c01; +op3val:0x8000; valaddr_reg:x2; val_offset:22077*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22077*FLEN/8, x3, x1, x4) + +inst_7394: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7c01; +op3val:0x1; valaddr_reg:x2; val_offset:22080*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22080*FLEN/8, x3, x1, x4) + +inst_7395: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7c01; +op3val:0x8001; valaddr_reg:x2; val_offset:22083*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22083*FLEN/8, x3, x1, x4) + +inst_7396: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7c01; +op3val:0x2; valaddr_reg:x2; val_offset:22086*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22086*FLEN/8, x3, x1, x4) + +inst_7397: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7c01; +op3val:0x83fe; valaddr_reg:x2; val_offset:22089*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22089*FLEN/8, x3, x1, x4) + +inst_7398: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7c01; +op3val:0x3ff; valaddr_reg:x2; val_offset:22092*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22092*FLEN/8, x3, x1, x4) + +inst_7399: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7c01; +op3val:0x83ff; valaddr_reg:x2; val_offset:22095*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22095*FLEN/8, x3, x1, x4) + +inst_7400: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7c01; +op3val:0x400; valaddr_reg:x2; val_offset:22098*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22098*FLEN/8, x3, x1, x4) + +inst_7401: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7c01; +op3val:0x8400; valaddr_reg:x2; val_offset:22101*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22101*FLEN/8, x3, x1, x4) + +inst_7402: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7c01; +op3val:0x401; valaddr_reg:x2; val_offset:22104*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22104*FLEN/8, x3, x1, x4) + +inst_7403: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7c01; +op3val:0x8455; valaddr_reg:x2; val_offset:22107*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22107*FLEN/8, x3, x1, x4) + +inst_7404: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7c01; +op3val:0x7bff; valaddr_reg:x2; val_offset:22110*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22110*FLEN/8, x3, x1, x4) + +inst_7405: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7c01; +op3val:0xfbff; valaddr_reg:x2; val_offset:22113*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22113*FLEN/8, x3, x1, x4) + +inst_7406: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7c01; +op3val:0x7c00; valaddr_reg:x2; val_offset:22116*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22116*FLEN/8, x3, x1, x4) + +inst_7407: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7c01; +op3val:0xfc00; valaddr_reg:x2; val_offset:22119*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22119*FLEN/8, x3, x1, x4) + +inst_7408: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7c01; +op3val:0x7e00; valaddr_reg:x2; val_offset:22122*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22122*FLEN/8, x3, x1, x4) + +inst_7409: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7c01; +op3val:0xfe00; valaddr_reg:x2; val_offset:22125*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22125*FLEN/8, x3, x1, x4) + +inst_7410: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7c01; +op3val:0x7e01; valaddr_reg:x2; val_offset:22128*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22128*FLEN/8, x3, x1, x4) + +inst_7411: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7c01; +op3val:0xfe55; valaddr_reg:x2; val_offset:22131*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22131*FLEN/8, x3, x1, x4) + +inst_7412: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7c01; +op3val:0x7c01; valaddr_reg:x2; val_offset:22134*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22134*FLEN/8, x3, x1, x4) + +inst_7413: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7c01; +op3val:0xfd55; valaddr_reg:x2; val_offset:22137*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22137*FLEN/8, x3, x1, x4) + +inst_7414: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7c01; +op3val:0x3c00; valaddr_reg:x2; val_offset:22140*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22140*FLEN/8, x3, x1, x4) + +inst_7415: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x7c01; +op3val:0xbc00; valaddr_reg:x2; val_offset:22143*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22143*FLEN/8, x3, x1, x4) + +inst_7416: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfd55; +op3val:0x0; valaddr_reg:x2; val_offset:22146*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22146*FLEN/8, x3, x1, x4) + +inst_7417: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfd55; +op3val:0x8000; valaddr_reg:x2; val_offset:22149*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22149*FLEN/8, x3, x1, x4) + +inst_7418: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfd55; +op3val:0x1; valaddr_reg:x2; val_offset:22152*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22152*FLEN/8, x3, x1, x4) + +inst_7419: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfd55; +op3val:0x8001; valaddr_reg:x2; val_offset:22155*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22155*FLEN/8, x3, x1, x4) + +inst_7420: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfd55; +op3val:0x2; valaddr_reg:x2; val_offset:22158*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22158*FLEN/8, x3, x1, x4) + +inst_7421: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfd55; +op3val:0x83fe; valaddr_reg:x2; val_offset:22161*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22161*FLEN/8, x3, x1, x4) + +inst_7422: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfd55; +op3val:0x3ff; valaddr_reg:x2; val_offset:22164*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22164*FLEN/8, x3, x1, x4) + +inst_7423: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfd55; +op3val:0x83ff; valaddr_reg:x2; val_offset:22167*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22167*FLEN/8, x3, x1, x4) + +inst_7424: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfd55; +op3val:0x400; valaddr_reg:x2; val_offset:22170*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22170*FLEN/8, x3, x1, x4) + +inst_7425: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfd55; +op3val:0x8400; valaddr_reg:x2; val_offset:22173*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22173*FLEN/8, x3, x1, x4) + +inst_7426: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfd55; +op3val:0x401; valaddr_reg:x2; val_offset:22176*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22176*FLEN/8, x3, x1, x4) + +inst_7427: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfd55; +op3val:0x8455; valaddr_reg:x2; val_offset:22179*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22179*FLEN/8, x3, x1, x4) + +inst_7428: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfd55; +op3val:0x7bff; valaddr_reg:x2; val_offset:22182*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22182*FLEN/8, x3, x1, x4) + +inst_7429: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfd55; +op3val:0xfbff; valaddr_reg:x2; val_offset:22185*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22185*FLEN/8, x3, x1, x4) + +inst_7430: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfd55; +op3val:0x7c00; valaddr_reg:x2; val_offset:22188*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22188*FLEN/8, x3, x1, x4) + +inst_7431: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfd55; +op3val:0xfc00; valaddr_reg:x2; val_offset:22191*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22191*FLEN/8, x3, x1, x4) + +inst_7432: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfd55; +op3val:0x7e00; valaddr_reg:x2; val_offset:22194*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22194*FLEN/8, x3, x1, x4) + +inst_7433: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfd55; +op3val:0xfe00; valaddr_reg:x2; val_offset:22197*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22197*FLEN/8, x3, x1, x4) + +inst_7434: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfd55; +op3val:0x7e01; valaddr_reg:x2; val_offset:22200*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22200*FLEN/8, x3, x1, x4) + +inst_7435: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfd55; +op3val:0xfe55; valaddr_reg:x2; val_offset:22203*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22203*FLEN/8, x3, x1, x4) + +inst_7436: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfd55; +op3val:0x7c01; valaddr_reg:x2; val_offset:22206*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22206*FLEN/8, x3, x1, x4) + +inst_7437: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfd55; +op3val:0xfd55; valaddr_reg:x2; val_offset:22209*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22209*FLEN/8, x3, x1, x4) + +inst_7438: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfd55; +op3val:0x3c00; valaddr_reg:x2; val_offset:22212*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22212*FLEN/8, x3, x1, x4) + +inst_7439: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xfd55; +op3val:0xbc00; valaddr_reg:x2; val_offset:22215*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22215*FLEN/8, x3, x1, x4) + +inst_7440: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x3c00; +op3val:0x0; valaddr_reg:x2; val_offset:22218*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22218*FLEN/8, x3, x1, x4) + +inst_7441: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x3c00; +op3val:0x8000; valaddr_reg:x2; val_offset:22221*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22221*FLEN/8, x3, x1, x4) + +inst_7442: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x3c00; +op3val:0x1; valaddr_reg:x2; val_offset:22224*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22224*FLEN/8, x3, x1, x4) + +inst_7443: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x3c00; +op3val:0x8001; valaddr_reg:x2; val_offset:22227*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22227*FLEN/8, x3, x1, x4) + +inst_7444: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x3c00; +op3val:0x2; valaddr_reg:x2; val_offset:22230*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22230*FLEN/8, x3, x1, x4) + +inst_7445: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x3c00; +op3val:0x83fe; valaddr_reg:x2; val_offset:22233*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22233*FLEN/8, x3, x1, x4) + +inst_7446: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x3c00; +op3val:0x3ff; valaddr_reg:x2; val_offset:22236*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22236*FLEN/8, x3, x1, x4) + +inst_7447: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x3c00; +op3val:0x83ff; valaddr_reg:x2; val_offset:22239*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22239*FLEN/8, x3, x1, x4) + +inst_7448: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x3c00; +op3val:0x400; valaddr_reg:x2; val_offset:22242*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22242*FLEN/8, x3, x1, x4) + +inst_7449: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x3c00; +op3val:0x8400; valaddr_reg:x2; val_offset:22245*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22245*FLEN/8, x3, x1, x4) + +inst_7450: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x3c00; +op3val:0x401; valaddr_reg:x2; val_offset:22248*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22248*FLEN/8, x3, x1, x4) + +inst_7451: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x3c00; +op3val:0x8455; valaddr_reg:x2; val_offset:22251*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22251*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_59) + +inst_7452: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x3c00; +op3val:0x7bff; valaddr_reg:x2; val_offset:22254*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22254*FLEN/8, x3, x1, x4) + +inst_7453: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x3c00; +op3val:0xfbff; valaddr_reg:x2; val_offset:22257*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22257*FLEN/8, x3, x1, x4) + +inst_7454: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x3c00; +op3val:0x7c00; valaddr_reg:x2; val_offset:22260*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22260*FLEN/8, x3, x1, x4) + +inst_7455: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x3c00; +op3val:0xfc00; valaddr_reg:x2; val_offset:22263*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22263*FLEN/8, x3, x1, x4) + +inst_7456: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x3c00; +op3val:0x7e00; valaddr_reg:x2; val_offset:22266*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22266*FLEN/8, x3, x1, x4) + +inst_7457: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x3c00; +op3val:0xfe00; valaddr_reg:x2; val_offset:22269*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22269*FLEN/8, x3, x1, x4) + +inst_7458: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x3c00; +op3val:0x7e01; valaddr_reg:x2; val_offset:22272*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22272*FLEN/8, x3, x1, x4) + +inst_7459: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x3c00; +op3val:0xfe55; valaddr_reg:x2; val_offset:22275*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22275*FLEN/8, x3, x1, x4) + +inst_7460: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x3c00; +op3val:0x7c01; valaddr_reg:x2; val_offset:22278*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22278*FLEN/8, x3, x1, x4) + +inst_7461: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x3c00; +op3val:0xfd55; valaddr_reg:x2; val_offset:22281*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22281*FLEN/8, x3, x1, x4) + +inst_7462: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x3c00; +op3val:0x3c00; valaddr_reg:x2; val_offset:22284*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22284*FLEN/8, x3, x1, x4) + +inst_7463: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0x3c00; +op3val:0xbc00; valaddr_reg:x2; val_offset:22287*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22287*FLEN/8, x3, x1, x4) + +inst_7464: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xbc00; +op3val:0x0; valaddr_reg:x2; val_offset:22290*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22290*FLEN/8, x3, x1, x4) + +inst_7465: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xbc00; +op3val:0x8000; valaddr_reg:x2; val_offset:22293*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22293*FLEN/8, x3, x1, x4) + +inst_7466: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xbc00; +op3val:0x1; valaddr_reg:x2; val_offset:22296*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22296*FLEN/8, x3, x1, x4) + +inst_7467: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xbc00; +op3val:0x8001; valaddr_reg:x2; val_offset:22299*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22299*FLEN/8, x3, x1, x4) + +inst_7468: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xbc00; +op3val:0x2; valaddr_reg:x2; val_offset:22302*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22302*FLEN/8, x3, x1, x4) + +inst_7469: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xbc00; +op3val:0x83fe; valaddr_reg:x2; val_offset:22305*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22305*FLEN/8, x3, x1, x4) + +inst_7470: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xbc00; +op3val:0x3ff; valaddr_reg:x2; val_offset:22308*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22308*FLEN/8, x3, x1, x4) + +inst_7471: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xbc00; +op3val:0x83ff; valaddr_reg:x2; val_offset:22311*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22311*FLEN/8, x3, x1, x4) + +inst_7472: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xbc00; +op3val:0x400; valaddr_reg:x2; val_offset:22314*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22314*FLEN/8, x3, x1, x4) + +inst_7473: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xbc00; +op3val:0x8400; valaddr_reg:x2; val_offset:22317*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22317*FLEN/8, x3, x1, x4) + +inst_7474: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xbc00; +op3val:0x401; valaddr_reg:x2; val_offset:22320*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22320*FLEN/8, x3, x1, x4) + +inst_7475: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xbc00; +op3val:0x8455; valaddr_reg:x2; val_offset:22323*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22323*FLEN/8, x3, x1, x4) + +inst_7476: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xbc00; +op3val:0x7bff; valaddr_reg:x2; val_offset:22326*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22326*FLEN/8, x3, x1, x4) + +inst_7477: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xbc00; +op3val:0xfbff; valaddr_reg:x2; val_offset:22329*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22329*FLEN/8, x3, x1, x4) + +inst_7478: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xbc00; +op3val:0x7c00; valaddr_reg:x2; val_offset:22332*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22332*FLEN/8, x3, x1, x4) + +inst_7479: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xbc00; +op3val:0xfc00; valaddr_reg:x2; val_offset:22335*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22335*FLEN/8, x3, x1, x4) + +inst_7480: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xbc00; +op3val:0x7e00; valaddr_reg:x2; val_offset:22338*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22338*FLEN/8, x3, x1, x4) + +inst_7481: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xbc00; +op3val:0xfe00; valaddr_reg:x2; val_offset:22341*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22341*FLEN/8, x3, x1, x4) + +inst_7482: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xbc00; +op3val:0x7e01; valaddr_reg:x2; val_offset:22344*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22344*FLEN/8, x3, x1, x4) + +inst_7483: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xbc00; +op3val:0xfe55; valaddr_reg:x2; val_offset:22347*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22347*FLEN/8, x3, x1, x4) + +inst_7484: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xbc00; +op3val:0x7c01; valaddr_reg:x2; val_offset:22350*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22350*FLEN/8, x3, x1, x4) + +inst_7485: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xbc00; +op3val:0xfd55; valaddr_reg:x2; val_offset:22353*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22353*FLEN/8, x3, x1, x4) + +inst_7486: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xbc00; +op3val:0x3c00; valaddr_reg:x2; val_offset:22356*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22356*FLEN/8, x3, x1, x4) + +inst_7487: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bff; op2val:0xbc00; +op3val:0xbc00; valaddr_reg:x2; val_offset:22359*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22359*FLEN/8, x3, x1, x4) + +inst_7488: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x0; +op3val:0x0; valaddr_reg:x2; val_offset:22362*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22362*FLEN/8, x3, x1, x4) + +inst_7489: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x0; +op3val:0x8000; valaddr_reg:x2; val_offset:22365*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22365*FLEN/8, x3, x1, x4) + +inst_7490: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x0; +op3val:0x1; valaddr_reg:x2; val_offset:22368*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22368*FLEN/8, x3, x1, x4) + +inst_7491: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x0; +op3val:0x8001; valaddr_reg:x2; val_offset:22371*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22371*FLEN/8, x3, x1, x4) + +inst_7492: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x0; +op3val:0x2; valaddr_reg:x2; val_offset:22374*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22374*FLEN/8, x3, x1, x4) + +inst_7493: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x0; +op3val:0x83fe; valaddr_reg:x2; val_offset:22377*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22377*FLEN/8, x3, x1, x4) + +inst_7494: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x0; +op3val:0x3ff; valaddr_reg:x2; val_offset:22380*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22380*FLEN/8, x3, x1, x4) + +inst_7495: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x0; +op3val:0x83ff; valaddr_reg:x2; val_offset:22383*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22383*FLEN/8, x3, x1, x4) + +inst_7496: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x0; +op3val:0x400; valaddr_reg:x2; val_offset:22386*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22386*FLEN/8, x3, x1, x4) + +inst_7497: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x0; +op3val:0x8400; valaddr_reg:x2; val_offset:22389*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22389*FLEN/8, x3, x1, x4) + +inst_7498: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x0; +op3val:0x401; valaddr_reg:x2; val_offset:22392*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22392*FLEN/8, x3, x1, x4) + +inst_7499: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x0; +op3val:0x8455; valaddr_reg:x2; val_offset:22395*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22395*FLEN/8, x3, x1, x4) + +inst_7500: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x0; +op3val:0x7bff; valaddr_reg:x2; val_offset:22398*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22398*FLEN/8, x3, x1, x4) + +inst_7501: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x0; +op3val:0xfbff; valaddr_reg:x2; val_offset:22401*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22401*FLEN/8, x3, x1, x4) + +inst_7502: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x0; +op3val:0x7c00; valaddr_reg:x2; val_offset:22404*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22404*FLEN/8, x3, x1, x4) + +inst_7503: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x0; +op3val:0xfc00; valaddr_reg:x2; val_offset:22407*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22407*FLEN/8, x3, x1, x4) + +inst_7504: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x0; +op3val:0x7e00; valaddr_reg:x2; val_offset:22410*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22410*FLEN/8, x3, x1, x4) + +inst_7505: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x0; +op3val:0xfe00; valaddr_reg:x2; val_offset:22413*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22413*FLEN/8, x3, x1, x4) + +inst_7506: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x0; +op3val:0x7e01; valaddr_reg:x2; val_offset:22416*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22416*FLEN/8, x3, x1, x4) + +inst_7507: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x0; +op3val:0xfe55; valaddr_reg:x2; val_offset:22419*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22419*FLEN/8, x3, x1, x4) + +inst_7508: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x0; +op3val:0x7c01; valaddr_reg:x2; val_offset:22422*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22422*FLEN/8, x3, x1, x4) + +inst_7509: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x0; +op3val:0xfd55; valaddr_reg:x2; val_offset:22425*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22425*FLEN/8, x3, x1, x4) + +inst_7510: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x0; +op3val:0x3c00; valaddr_reg:x2; val_offset:22428*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22428*FLEN/8, x3, x1, x4) + +inst_7511: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x0; +op3val:0xbc00; valaddr_reg:x2; val_offset:22431*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22431*FLEN/8, x3, x1, x4) + +inst_7512: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8000; +op3val:0x0; valaddr_reg:x2; val_offset:22434*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22434*FLEN/8, x3, x1, x4) + +inst_7513: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8000; +op3val:0x8000; valaddr_reg:x2; val_offset:22437*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22437*FLEN/8, x3, x1, x4) + +inst_7514: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8000; +op3val:0x1; valaddr_reg:x2; val_offset:22440*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22440*FLEN/8, x3, x1, x4) + +inst_7515: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8000; +op3val:0x8001; valaddr_reg:x2; val_offset:22443*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22443*FLEN/8, x3, x1, x4) + +inst_7516: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8000; +op3val:0x2; valaddr_reg:x2; val_offset:22446*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22446*FLEN/8, x3, x1, x4) + +inst_7517: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8000; +op3val:0x83fe; valaddr_reg:x2; val_offset:22449*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22449*FLEN/8, x3, x1, x4) + +inst_7518: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8000; +op3val:0x3ff; valaddr_reg:x2; val_offset:22452*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22452*FLEN/8, x3, x1, x4) + +inst_7519: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8000; +op3val:0x83ff; valaddr_reg:x2; val_offset:22455*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22455*FLEN/8, x3, x1, x4) + +inst_7520: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8000; +op3val:0x400; valaddr_reg:x2; val_offset:22458*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22458*FLEN/8, x3, x1, x4) + +inst_7521: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8000; +op3val:0x8400; valaddr_reg:x2; val_offset:22461*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22461*FLEN/8, x3, x1, x4) + +inst_7522: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8000; +op3val:0x401; valaddr_reg:x2; val_offset:22464*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22464*FLEN/8, x3, x1, x4) + +inst_7523: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8000; +op3val:0x8455; valaddr_reg:x2; val_offset:22467*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22467*FLEN/8, x3, x1, x4) + +inst_7524: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x2; val_offset:22470*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22470*FLEN/8, x3, x1, x4) + +inst_7525: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x2; val_offset:22473*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22473*FLEN/8, x3, x1, x4) + +inst_7526: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8000; +op3val:0x7c00; valaddr_reg:x2; val_offset:22476*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22476*FLEN/8, x3, x1, x4) + +inst_7527: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8000; +op3val:0xfc00; valaddr_reg:x2; val_offset:22479*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22479*FLEN/8, x3, x1, x4) + +inst_7528: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8000; +op3val:0x7e00; valaddr_reg:x2; val_offset:22482*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22482*FLEN/8, x3, x1, x4) + +inst_7529: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8000; +op3val:0xfe00; valaddr_reg:x2; val_offset:22485*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22485*FLEN/8, x3, x1, x4) + +inst_7530: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8000; +op3val:0x7e01; valaddr_reg:x2; val_offset:22488*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22488*FLEN/8, x3, x1, x4) + +inst_7531: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8000; +op3val:0xfe55; valaddr_reg:x2; val_offset:22491*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22491*FLEN/8, x3, x1, x4) + +inst_7532: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8000; +op3val:0x7c01; valaddr_reg:x2; val_offset:22494*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22494*FLEN/8, x3, x1, x4) + +inst_7533: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8000; +op3val:0xfd55; valaddr_reg:x2; val_offset:22497*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22497*FLEN/8, x3, x1, x4) + +inst_7534: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8000; +op3val:0x3c00; valaddr_reg:x2; val_offset:22500*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22500*FLEN/8, x3, x1, x4) + +inst_7535: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8000; +op3val:0xbc00; valaddr_reg:x2; val_offset:22503*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22503*FLEN/8, x3, x1, x4) + +inst_7536: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x1; +op3val:0x0; valaddr_reg:x2; val_offset:22506*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22506*FLEN/8, x3, x1, x4) + +inst_7537: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x1; +op3val:0x8000; valaddr_reg:x2; val_offset:22509*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22509*FLEN/8, x3, x1, x4) + +inst_7538: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x1; +op3val:0x1; valaddr_reg:x2; val_offset:22512*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22512*FLEN/8, x3, x1, x4) + +inst_7539: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x1; +op3val:0x8001; valaddr_reg:x2; val_offset:22515*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22515*FLEN/8, x3, x1, x4) + +inst_7540: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x1; +op3val:0x2; valaddr_reg:x2; val_offset:22518*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22518*FLEN/8, x3, x1, x4) + +inst_7541: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x1; +op3val:0x83fe; valaddr_reg:x2; val_offset:22521*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22521*FLEN/8, x3, x1, x4) + +inst_7542: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x1; +op3val:0x3ff; valaddr_reg:x2; val_offset:22524*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22524*FLEN/8, x3, x1, x4) + +inst_7543: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x1; +op3val:0x83ff; valaddr_reg:x2; val_offset:22527*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22527*FLEN/8, x3, x1, x4) + +inst_7544: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x1; +op3val:0x400; valaddr_reg:x2; val_offset:22530*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22530*FLEN/8, x3, x1, x4) + +inst_7545: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x1; +op3val:0x8400; valaddr_reg:x2; val_offset:22533*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22533*FLEN/8, x3, x1, x4) + +inst_7546: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x1; +op3val:0x401; valaddr_reg:x2; val_offset:22536*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22536*FLEN/8, x3, x1, x4) + +inst_7547: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x1; +op3val:0x8455; valaddr_reg:x2; val_offset:22539*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22539*FLEN/8, x3, x1, x4) + +inst_7548: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x1; +op3val:0x7bff; valaddr_reg:x2; val_offset:22542*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22542*FLEN/8, x3, x1, x4) + +inst_7549: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x1; +op3val:0xfbff; valaddr_reg:x2; val_offset:22545*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22545*FLEN/8, x3, x1, x4) + +inst_7550: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x1; +op3val:0x7c00; valaddr_reg:x2; val_offset:22548*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22548*FLEN/8, x3, x1, x4) + +inst_7551: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x1; +op3val:0xfc00; valaddr_reg:x2; val_offset:22551*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22551*FLEN/8, x3, x1, x4) + +inst_7552: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x1; +op3val:0x7e00; valaddr_reg:x2; val_offset:22554*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22554*FLEN/8, x3, x1, x4) + +inst_7553: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x1; +op3val:0xfe00; valaddr_reg:x2; val_offset:22557*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22557*FLEN/8, x3, x1, x4) + +inst_7554: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x1; +op3val:0x7e01; valaddr_reg:x2; val_offset:22560*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22560*FLEN/8, x3, x1, x4) + +inst_7555: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x1; +op3val:0xfe55; valaddr_reg:x2; val_offset:22563*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22563*FLEN/8, x3, x1, x4) + +inst_7556: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x1; +op3val:0x7c01; valaddr_reg:x2; val_offset:22566*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22566*FLEN/8, x3, x1, x4) + +inst_7557: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x1; +op3val:0xfd55; valaddr_reg:x2; val_offset:22569*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22569*FLEN/8, x3, x1, x4) + +inst_7558: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x1; +op3val:0x3c00; valaddr_reg:x2; val_offset:22572*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22572*FLEN/8, x3, x1, x4) + +inst_7559: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x1; +op3val:0xbc00; valaddr_reg:x2; val_offset:22575*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22575*FLEN/8, x3, x1, x4) + +inst_7560: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8001; +op3val:0x0; valaddr_reg:x2; val_offset:22578*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22578*FLEN/8, x3, x1, x4) + +inst_7561: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8001; +op3val:0x8000; valaddr_reg:x2; val_offset:22581*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22581*FLEN/8, x3, x1, x4) + +inst_7562: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8001; +op3val:0x1; valaddr_reg:x2; val_offset:22584*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22584*FLEN/8, x3, x1, x4) + +inst_7563: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8001; +op3val:0x8001; valaddr_reg:x2; val_offset:22587*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22587*FLEN/8, x3, x1, x4) + +inst_7564: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8001; +op3val:0x2; valaddr_reg:x2; val_offset:22590*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22590*FLEN/8, x3, x1, x4) + +inst_7565: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8001; +op3val:0x83fe; valaddr_reg:x2; val_offset:22593*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22593*FLEN/8, x3, x1, x4) + +inst_7566: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8001; +op3val:0x3ff; valaddr_reg:x2; val_offset:22596*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22596*FLEN/8, x3, x1, x4) + +inst_7567: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8001; +op3val:0x83ff; valaddr_reg:x2; val_offset:22599*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22599*FLEN/8, x3, x1, x4) + +inst_7568: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8001; +op3val:0x400; valaddr_reg:x2; val_offset:22602*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22602*FLEN/8, x3, x1, x4) + +inst_7569: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8001; +op3val:0x8400; valaddr_reg:x2; val_offset:22605*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22605*FLEN/8, x3, x1, x4) + +inst_7570: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8001; +op3val:0x401; valaddr_reg:x2; val_offset:22608*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22608*FLEN/8, x3, x1, x4) + +inst_7571: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8001; +op3val:0x8455; valaddr_reg:x2; val_offset:22611*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22611*FLEN/8, x3, x1, x4) + +inst_7572: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8001; +op3val:0x7bff; valaddr_reg:x2; val_offset:22614*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22614*FLEN/8, x3, x1, x4) + +inst_7573: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8001; +op3val:0xfbff; valaddr_reg:x2; val_offset:22617*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22617*FLEN/8, x3, x1, x4) + +inst_7574: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8001; +op3val:0x7c00; valaddr_reg:x2; val_offset:22620*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22620*FLEN/8, x3, x1, x4) + +inst_7575: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8001; +op3val:0xfc00; valaddr_reg:x2; val_offset:22623*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22623*FLEN/8, x3, x1, x4) + +inst_7576: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8001; +op3val:0x7e00; valaddr_reg:x2; val_offset:22626*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22626*FLEN/8, x3, x1, x4) + +inst_7577: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8001; +op3val:0xfe00; valaddr_reg:x2; val_offset:22629*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22629*FLEN/8, x3, x1, x4) + +inst_7578: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8001; +op3val:0x7e01; valaddr_reg:x2; val_offset:22632*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22632*FLEN/8, x3, x1, x4) + +inst_7579: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8001; +op3val:0xfe55; valaddr_reg:x2; val_offset:22635*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22635*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_60) + +inst_7580: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8001; +op3val:0x7c01; valaddr_reg:x2; val_offset:22638*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22638*FLEN/8, x3, x1, x4) + +inst_7581: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8001; +op3val:0xfd55; valaddr_reg:x2; val_offset:22641*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22641*FLEN/8, x3, x1, x4) + +inst_7582: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8001; +op3val:0x3c00; valaddr_reg:x2; val_offset:22644*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22644*FLEN/8, x3, x1, x4) + +inst_7583: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8001; +op3val:0xbc00; valaddr_reg:x2; val_offset:22647*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22647*FLEN/8, x3, x1, x4) + +inst_7584: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x2; +op3val:0x0; valaddr_reg:x2; val_offset:22650*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22650*FLEN/8, x3, x1, x4) + +inst_7585: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x2; +op3val:0x8000; valaddr_reg:x2; val_offset:22653*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22653*FLEN/8, x3, x1, x4) + +inst_7586: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x2; +op3val:0x1; valaddr_reg:x2; val_offset:22656*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22656*FLEN/8, x3, x1, x4) + +inst_7587: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x2; +op3val:0x8001; valaddr_reg:x2; val_offset:22659*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22659*FLEN/8, x3, x1, x4) + +inst_7588: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x2; +op3val:0x2; valaddr_reg:x2; val_offset:22662*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22662*FLEN/8, x3, x1, x4) + +inst_7589: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x2; +op3val:0x83fe; valaddr_reg:x2; val_offset:22665*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22665*FLEN/8, x3, x1, x4) + +inst_7590: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x2; +op3val:0x3ff; valaddr_reg:x2; val_offset:22668*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22668*FLEN/8, x3, x1, x4) + +inst_7591: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x2; +op3val:0x83ff; valaddr_reg:x2; val_offset:22671*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22671*FLEN/8, x3, x1, x4) + +inst_7592: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x2; +op3val:0x400; valaddr_reg:x2; val_offset:22674*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22674*FLEN/8, x3, x1, x4) + +inst_7593: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x2; +op3val:0x8400; valaddr_reg:x2; val_offset:22677*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22677*FLEN/8, x3, x1, x4) + +inst_7594: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x2; +op3val:0x401; valaddr_reg:x2; val_offset:22680*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22680*FLEN/8, x3, x1, x4) + +inst_7595: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x2; +op3val:0x8455; valaddr_reg:x2; val_offset:22683*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22683*FLEN/8, x3, x1, x4) + +inst_7596: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x2; +op3val:0x7bff; valaddr_reg:x2; val_offset:22686*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22686*FLEN/8, x3, x1, x4) + +inst_7597: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x2; +op3val:0xfbff; valaddr_reg:x2; val_offset:22689*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22689*FLEN/8, x3, x1, x4) + +inst_7598: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x2; +op3val:0x7c00; valaddr_reg:x2; val_offset:22692*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22692*FLEN/8, x3, x1, x4) + +inst_7599: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x2; +op3val:0xfc00; valaddr_reg:x2; val_offset:22695*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22695*FLEN/8, x3, x1, x4) + +inst_7600: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x2; +op3val:0x7e00; valaddr_reg:x2; val_offset:22698*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22698*FLEN/8, x3, x1, x4) + +inst_7601: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x2; +op3val:0xfe00; valaddr_reg:x2; val_offset:22701*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22701*FLEN/8, x3, x1, x4) + +inst_7602: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x2; +op3val:0x7e01; valaddr_reg:x2; val_offset:22704*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22704*FLEN/8, x3, x1, x4) + +inst_7603: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x2; +op3val:0xfe55; valaddr_reg:x2; val_offset:22707*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22707*FLEN/8, x3, x1, x4) + +inst_7604: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x2; +op3val:0x7c01; valaddr_reg:x2; val_offset:22710*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22710*FLEN/8, x3, x1, x4) + +inst_7605: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x2; +op3val:0xfd55; valaddr_reg:x2; val_offset:22713*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22713*FLEN/8, x3, x1, x4) + +inst_7606: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x2; +op3val:0x3c00; valaddr_reg:x2; val_offset:22716*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22716*FLEN/8, x3, x1, x4) + +inst_7607: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x2; +op3val:0xbc00; valaddr_reg:x2; val_offset:22719*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22719*FLEN/8, x3, x1, x4) + +inst_7608: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x83fe; +op3val:0x0; valaddr_reg:x2; val_offset:22722*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22722*FLEN/8, x3, x1, x4) + +inst_7609: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x83fe; +op3val:0x8000; valaddr_reg:x2; val_offset:22725*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22725*FLEN/8, x3, x1, x4) + +inst_7610: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x83fe; +op3val:0x1; valaddr_reg:x2; val_offset:22728*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22728*FLEN/8, x3, x1, x4) + +inst_7611: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x83fe; +op3val:0x8001; valaddr_reg:x2; val_offset:22731*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22731*FLEN/8, x3, x1, x4) + +inst_7612: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x83fe; +op3val:0x2; valaddr_reg:x2; val_offset:22734*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22734*FLEN/8, x3, x1, x4) + +inst_7613: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x83fe; +op3val:0x83fe; valaddr_reg:x2; val_offset:22737*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22737*FLEN/8, x3, x1, x4) + +inst_7614: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x83fe; +op3val:0x3ff; valaddr_reg:x2; val_offset:22740*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22740*FLEN/8, x3, x1, x4) + +inst_7615: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x83fe; +op3val:0x83ff; valaddr_reg:x2; val_offset:22743*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22743*FLEN/8, x3, x1, x4) + +inst_7616: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x83fe; +op3val:0x400; valaddr_reg:x2; val_offset:22746*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22746*FLEN/8, x3, x1, x4) + +inst_7617: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x83fe; +op3val:0x8400; valaddr_reg:x2; val_offset:22749*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22749*FLEN/8, x3, x1, x4) + +inst_7618: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x83fe; +op3val:0x401; valaddr_reg:x2; val_offset:22752*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22752*FLEN/8, x3, x1, x4) + +inst_7619: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x83fe; +op3val:0x8455; valaddr_reg:x2; val_offset:22755*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22755*FLEN/8, x3, x1, x4) + +inst_7620: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x83fe; +op3val:0x7bff; valaddr_reg:x2; val_offset:22758*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22758*FLEN/8, x3, x1, x4) + +inst_7621: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x83fe; +op3val:0xfbff; valaddr_reg:x2; val_offset:22761*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22761*FLEN/8, x3, x1, x4) + +inst_7622: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x83fe; +op3val:0x7c00; valaddr_reg:x2; val_offset:22764*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22764*FLEN/8, x3, x1, x4) + +inst_7623: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x83fe; +op3val:0xfc00; valaddr_reg:x2; val_offset:22767*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22767*FLEN/8, x3, x1, x4) + +inst_7624: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x83fe; +op3val:0x7e00; valaddr_reg:x2; val_offset:22770*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22770*FLEN/8, x3, x1, x4) + +inst_7625: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x83fe; +op3val:0xfe00; valaddr_reg:x2; val_offset:22773*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22773*FLEN/8, x3, x1, x4) + +inst_7626: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x83fe; +op3val:0x7e01; valaddr_reg:x2; val_offset:22776*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22776*FLEN/8, x3, x1, x4) + +inst_7627: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x83fe; +op3val:0xfe55; valaddr_reg:x2; val_offset:22779*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22779*FLEN/8, x3, x1, x4) + +inst_7628: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x83fe; +op3val:0x7c01; valaddr_reg:x2; val_offset:22782*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22782*FLEN/8, x3, x1, x4) + +inst_7629: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x83fe; +op3val:0xfd55; valaddr_reg:x2; val_offset:22785*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22785*FLEN/8, x3, x1, x4) + +inst_7630: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x83fe; +op3val:0x3c00; valaddr_reg:x2; val_offset:22788*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22788*FLEN/8, x3, x1, x4) + +inst_7631: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x83fe; +op3val:0xbc00; valaddr_reg:x2; val_offset:22791*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22791*FLEN/8, x3, x1, x4) + +inst_7632: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x3ff; +op3val:0x0; valaddr_reg:x2; val_offset:22794*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22794*FLEN/8, x3, x1, x4) + +inst_7633: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x3ff; +op3val:0x8000; valaddr_reg:x2; val_offset:22797*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22797*FLEN/8, x3, x1, x4) + +inst_7634: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x3ff; +op3val:0x1; valaddr_reg:x2; val_offset:22800*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22800*FLEN/8, x3, x1, x4) + +inst_7635: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x3ff; +op3val:0x8001; valaddr_reg:x2; val_offset:22803*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22803*FLEN/8, x3, x1, x4) + +inst_7636: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x3ff; +op3val:0x2; valaddr_reg:x2; val_offset:22806*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22806*FLEN/8, x3, x1, x4) + +inst_7637: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x3ff; +op3val:0x83fe; valaddr_reg:x2; val_offset:22809*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22809*FLEN/8, x3, x1, x4) + +inst_7638: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x3ff; +op3val:0x3ff; valaddr_reg:x2; val_offset:22812*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22812*FLEN/8, x3, x1, x4) + +inst_7639: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x3ff; +op3val:0x83ff; valaddr_reg:x2; val_offset:22815*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22815*FLEN/8, x3, x1, x4) + +inst_7640: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x3ff; +op3val:0x400; valaddr_reg:x2; val_offset:22818*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22818*FLEN/8, x3, x1, x4) + +inst_7641: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x3ff; +op3val:0x8400; valaddr_reg:x2; val_offset:22821*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22821*FLEN/8, x3, x1, x4) + +inst_7642: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x3ff; +op3val:0x401; valaddr_reg:x2; val_offset:22824*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22824*FLEN/8, x3, x1, x4) + +inst_7643: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x3ff; +op3val:0x8455; valaddr_reg:x2; val_offset:22827*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22827*FLEN/8, x3, x1, x4) + +inst_7644: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x3ff; +op3val:0x7bff; valaddr_reg:x2; val_offset:22830*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22830*FLEN/8, x3, x1, x4) + +inst_7645: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x3ff; +op3val:0xfbff; valaddr_reg:x2; val_offset:22833*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22833*FLEN/8, x3, x1, x4) + +inst_7646: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x3ff; +op3val:0x7c00; valaddr_reg:x2; val_offset:22836*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22836*FLEN/8, x3, x1, x4) + +inst_7647: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x3ff; +op3val:0xfc00; valaddr_reg:x2; val_offset:22839*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22839*FLEN/8, x3, x1, x4) + +inst_7648: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x3ff; +op3val:0x7e00; valaddr_reg:x2; val_offset:22842*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22842*FLEN/8, x3, x1, x4) + +inst_7649: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x3ff; +op3val:0xfe00; valaddr_reg:x2; val_offset:22845*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22845*FLEN/8, x3, x1, x4) + +inst_7650: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x3ff; +op3val:0x7e01; valaddr_reg:x2; val_offset:22848*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22848*FLEN/8, x3, x1, x4) + +inst_7651: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x3ff; +op3val:0xfe55; valaddr_reg:x2; val_offset:22851*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22851*FLEN/8, x3, x1, x4) + +inst_7652: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x3ff; +op3val:0x7c01; valaddr_reg:x2; val_offset:22854*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22854*FLEN/8, x3, x1, x4) + +inst_7653: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x3ff; +op3val:0xfd55; valaddr_reg:x2; val_offset:22857*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22857*FLEN/8, x3, x1, x4) + +inst_7654: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x3ff; +op3val:0x3c00; valaddr_reg:x2; val_offset:22860*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22860*FLEN/8, x3, x1, x4) + +inst_7655: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x3ff; +op3val:0xbc00; valaddr_reg:x2; val_offset:22863*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22863*FLEN/8, x3, x1, x4) + +inst_7656: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x83ff; +op3val:0x0; valaddr_reg:x2; val_offset:22866*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22866*FLEN/8, x3, x1, x4) + +inst_7657: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x83ff; +op3val:0x8000; valaddr_reg:x2; val_offset:22869*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22869*FLEN/8, x3, x1, x4) + +inst_7658: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x83ff; +op3val:0x1; valaddr_reg:x2; val_offset:22872*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22872*FLEN/8, x3, x1, x4) + +inst_7659: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x83ff; +op3val:0x8001; valaddr_reg:x2; val_offset:22875*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22875*FLEN/8, x3, x1, x4) + +inst_7660: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x83ff; +op3val:0x2; valaddr_reg:x2; val_offset:22878*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22878*FLEN/8, x3, x1, x4) + +inst_7661: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x83ff; +op3val:0x83fe; valaddr_reg:x2; val_offset:22881*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22881*FLEN/8, x3, x1, x4) + +inst_7662: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x83ff; +op3val:0x3ff; valaddr_reg:x2; val_offset:22884*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22884*FLEN/8, x3, x1, x4) + +inst_7663: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x83ff; +op3val:0x83ff; valaddr_reg:x2; val_offset:22887*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22887*FLEN/8, x3, x1, x4) + +inst_7664: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x83ff; +op3val:0x400; valaddr_reg:x2; val_offset:22890*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22890*FLEN/8, x3, x1, x4) + +inst_7665: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x83ff; +op3val:0x8400; valaddr_reg:x2; val_offset:22893*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22893*FLEN/8, x3, x1, x4) + +inst_7666: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x83ff; +op3val:0x401; valaddr_reg:x2; val_offset:22896*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22896*FLEN/8, x3, x1, x4) + +inst_7667: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x83ff; +op3val:0x8455; valaddr_reg:x2; val_offset:22899*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22899*FLEN/8, x3, x1, x4) + +inst_7668: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x83ff; +op3val:0x7bff; valaddr_reg:x2; val_offset:22902*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22902*FLEN/8, x3, x1, x4) + +inst_7669: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x83ff; +op3val:0xfbff; valaddr_reg:x2; val_offset:22905*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22905*FLEN/8, x3, x1, x4) + +inst_7670: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x83ff; +op3val:0x7c00; valaddr_reg:x2; val_offset:22908*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22908*FLEN/8, x3, x1, x4) + +inst_7671: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x83ff; +op3val:0xfc00; valaddr_reg:x2; val_offset:22911*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22911*FLEN/8, x3, x1, x4) + +inst_7672: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x83ff; +op3val:0x7e00; valaddr_reg:x2; val_offset:22914*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22914*FLEN/8, x3, x1, x4) + +inst_7673: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x83ff; +op3val:0xfe00; valaddr_reg:x2; val_offset:22917*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22917*FLEN/8, x3, x1, x4) + +inst_7674: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x83ff; +op3val:0x7e01; valaddr_reg:x2; val_offset:22920*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22920*FLEN/8, x3, x1, x4) + +inst_7675: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x83ff; +op3val:0xfe55; valaddr_reg:x2; val_offset:22923*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22923*FLEN/8, x3, x1, x4) + +inst_7676: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x83ff; +op3val:0x7c01; valaddr_reg:x2; val_offset:22926*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22926*FLEN/8, x3, x1, x4) + +inst_7677: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x83ff; +op3val:0xfd55; valaddr_reg:x2; val_offset:22929*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22929*FLEN/8, x3, x1, x4) + +inst_7678: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x83ff; +op3val:0x3c00; valaddr_reg:x2; val_offset:22932*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22932*FLEN/8, x3, x1, x4) + +inst_7679: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x83ff; +op3val:0xbc00; valaddr_reg:x2; val_offset:22935*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22935*FLEN/8, x3, x1, x4) + +inst_7680: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x400; +op3val:0x0; valaddr_reg:x2; val_offset:22938*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22938*FLEN/8, x3, x1, x4) + +inst_7681: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x400; +op3val:0x8000; valaddr_reg:x2; val_offset:22941*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22941*FLEN/8, x3, x1, x4) + +inst_7682: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x400; +op3val:0x1; valaddr_reg:x2; val_offset:22944*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22944*FLEN/8, x3, x1, x4) + +inst_7683: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x400; +op3val:0x8001; valaddr_reg:x2; val_offset:22947*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22947*FLEN/8, x3, x1, x4) + +inst_7684: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x400; +op3val:0x2; valaddr_reg:x2; val_offset:22950*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22950*FLEN/8, x3, x1, x4) + +inst_7685: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x400; +op3val:0x83fe; valaddr_reg:x2; val_offset:22953*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22953*FLEN/8, x3, x1, x4) + +inst_7686: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x400; +op3val:0x3ff; valaddr_reg:x2; val_offset:22956*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22956*FLEN/8, x3, x1, x4) + +inst_7687: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x400; +op3val:0x83ff; valaddr_reg:x2; val_offset:22959*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22959*FLEN/8, x3, x1, x4) + +inst_7688: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x400; +op3val:0x400; valaddr_reg:x2; val_offset:22962*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22962*FLEN/8, x3, x1, x4) + +inst_7689: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x400; +op3val:0x8400; valaddr_reg:x2; val_offset:22965*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22965*FLEN/8, x3, x1, x4) + +inst_7690: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x400; +op3val:0x401; valaddr_reg:x2; val_offset:22968*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22968*FLEN/8, x3, x1, x4) + +inst_7691: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x400; +op3val:0x8455; valaddr_reg:x2; val_offset:22971*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22971*FLEN/8, x3, x1, x4) + +inst_7692: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x400; +op3val:0x7bff; valaddr_reg:x2; val_offset:22974*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22974*FLEN/8, x3, x1, x4) + +inst_7693: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x400; +op3val:0xfbff; valaddr_reg:x2; val_offset:22977*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22977*FLEN/8, x3, x1, x4) + +inst_7694: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x400; +op3val:0x7c00; valaddr_reg:x2; val_offset:22980*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22980*FLEN/8, x3, x1, x4) + +inst_7695: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x400; +op3val:0xfc00; valaddr_reg:x2; val_offset:22983*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22983*FLEN/8, x3, x1, x4) + +inst_7696: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x400; +op3val:0x7e00; valaddr_reg:x2; val_offset:22986*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22986*FLEN/8, x3, x1, x4) + +inst_7697: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x400; +op3val:0xfe00; valaddr_reg:x2; val_offset:22989*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22989*FLEN/8, x3, x1, x4) + +inst_7698: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x400; +op3val:0x7e01; valaddr_reg:x2; val_offset:22992*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22992*FLEN/8, x3, x1, x4) + +inst_7699: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x400; +op3val:0xfe55; valaddr_reg:x2; val_offset:22995*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22995*FLEN/8, x3, x1, x4) + +inst_7700: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x400; +op3val:0x7c01; valaddr_reg:x2; val_offset:22998*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 22998*FLEN/8, x3, x1, x4) + +inst_7701: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x400; +op3val:0xfd55; valaddr_reg:x2; val_offset:23001*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23001*FLEN/8, x3, x1, x4) + +inst_7702: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x400; +op3val:0x3c00; valaddr_reg:x2; val_offset:23004*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23004*FLEN/8, x3, x1, x4) + +inst_7703: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x400; +op3val:0xbc00; valaddr_reg:x2; val_offset:23007*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23007*FLEN/8, x3, x1, x4) + +inst_7704: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8400; +op3val:0x0; valaddr_reg:x2; val_offset:23010*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23010*FLEN/8, x3, x1, x4) + +inst_7705: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8400; +op3val:0x8000; valaddr_reg:x2; val_offset:23013*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23013*FLEN/8, x3, x1, x4) + +inst_7706: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8400; +op3val:0x1; valaddr_reg:x2; val_offset:23016*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23016*FLEN/8, x3, x1, x4) + +inst_7707: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8400; +op3val:0x8001; valaddr_reg:x2; val_offset:23019*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23019*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_61) + +inst_7708: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8400; +op3val:0x2; valaddr_reg:x2; val_offset:23022*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23022*FLEN/8, x3, x1, x4) + +inst_7709: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8400; +op3val:0x83fe; valaddr_reg:x2; val_offset:23025*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23025*FLEN/8, x3, x1, x4) + +inst_7710: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8400; +op3val:0x3ff; valaddr_reg:x2; val_offset:23028*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23028*FLEN/8, x3, x1, x4) + +inst_7711: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8400; +op3val:0x83ff; valaddr_reg:x2; val_offset:23031*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23031*FLEN/8, x3, x1, x4) + +inst_7712: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8400; +op3val:0x400; valaddr_reg:x2; val_offset:23034*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23034*FLEN/8, x3, x1, x4) + +inst_7713: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8400; +op3val:0x8400; valaddr_reg:x2; val_offset:23037*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23037*FLEN/8, x3, x1, x4) + +inst_7714: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8400; +op3val:0x401; valaddr_reg:x2; val_offset:23040*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23040*FLEN/8, x3, x1, x4) + +inst_7715: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8400; +op3val:0x8455; valaddr_reg:x2; val_offset:23043*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23043*FLEN/8, x3, x1, x4) + +inst_7716: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8400; +op3val:0x7bff; valaddr_reg:x2; val_offset:23046*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23046*FLEN/8, x3, x1, x4) + +inst_7717: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8400; +op3val:0xfbff; valaddr_reg:x2; val_offset:23049*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23049*FLEN/8, x3, x1, x4) + +inst_7718: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8400; +op3val:0x7c00; valaddr_reg:x2; val_offset:23052*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23052*FLEN/8, x3, x1, x4) + +inst_7719: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8400; +op3val:0xfc00; valaddr_reg:x2; val_offset:23055*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23055*FLEN/8, x3, x1, x4) + +inst_7720: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8400; +op3val:0x7e00; valaddr_reg:x2; val_offset:23058*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23058*FLEN/8, x3, x1, x4) + +inst_7721: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8400; +op3val:0xfe00; valaddr_reg:x2; val_offset:23061*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23061*FLEN/8, x3, x1, x4) + +inst_7722: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8400; +op3val:0x7e01; valaddr_reg:x2; val_offset:23064*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23064*FLEN/8, x3, x1, x4) + +inst_7723: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8400; +op3val:0xfe55; valaddr_reg:x2; val_offset:23067*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23067*FLEN/8, x3, x1, x4) + +inst_7724: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8400; +op3val:0x7c01; valaddr_reg:x2; val_offset:23070*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23070*FLEN/8, x3, x1, x4) + +inst_7725: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8400; +op3val:0xfd55; valaddr_reg:x2; val_offset:23073*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23073*FLEN/8, x3, x1, x4) + +inst_7726: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8400; +op3val:0x3c00; valaddr_reg:x2; val_offset:23076*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23076*FLEN/8, x3, x1, x4) + +inst_7727: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8400; +op3val:0xbc00; valaddr_reg:x2; val_offset:23079*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23079*FLEN/8, x3, x1, x4) + +inst_7728: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x401; +op3val:0x0; valaddr_reg:x2; val_offset:23082*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23082*FLEN/8, x3, x1, x4) + +inst_7729: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x401; +op3val:0x8000; valaddr_reg:x2; val_offset:23085*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23085*FLEN/8, x3, x1, x4) + +inst_7730: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x401; +op3val:0x1; valaddr_reg:x2; val_offset:23088*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23088*FLEN/8, x3, x1, x4) + +inst_7731: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x401; +op3val:0x8001; valaddr_reg:x2; val_offset:23091*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23091*FLEN/8, x3, x1, x4) + +inst_7732: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x401; +op3val:0x2; valaddr_reg:x2; val_offset:23094*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23094*FLEN/8, x3, x1, x4) + +inst_7733: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x401; +op3val:0x83fe; valaddr_reg:x2; val_offset:23097*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23097*FLEN/8, x3, x1, x4) + +inst_7734: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x401; +op3val:0x3ff; valaddr_reg:x2; val_offset:23100*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23100*FLEN/8, x3, x1, x4) + +inst_7735: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x401; +op3val:0x83ff; valaddr_reg:x2; val_offset:23103*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23103*FLEN/8, x3, x1, x4) + +inst_7736: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x401; +op3val:0x400; valaddr_reg:x2; val_offset:23106*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23106*FLEN/8, x3, x1, x4) + +inst_7737: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x401; +op3val:0x8400; valaddr_reg:x2; val_offset:23109*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23109*FLEN/8, x3, x1, x4) + +inst_7738: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x401; +op3val:0x401; valaddr_reg:x2; val_offset:23112*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23112*FLEN/8, x3, x1, x4) + +inst_7739: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x401; +op3val:0x8455; valaddr_reg:x2; val_offset:23115*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23115*FLEN/8, x3, x1, x4) + +inst_7740: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x401; +op3val:0x7bff; valaddr_reg:x2; val_offset:23118*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23118*FLEN/8, x3, x1, x4) + +inst_7741: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x401; +op3val:0xfbff; valaddr_reg:x2; val_offset:23121*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23121*FLEN/8, x3, x1, x4) + +inst_7742: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x401; +op3val:0x7c00; valaddr_reg:x2; val_offset:23124*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23124*FLEN/8, x3, x1, x4) + +inst_7743: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x401; +op3val:0xfc00; valaddr_reg:x2; val_offset:23127*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23127*FLEN/8, x3, x1, x4) + +inst_7744: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x401; +op3val:0x7e00; valaddr_reg:x2; val_offset:23130*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23130*FLEN/8, x3, x1, x4) + +inst_7745: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x401; +op3val:0xfe00; valaddr_reg:x2; val_offset:23133*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23133*FLEN/8, x3, x1, x4) + +inst_7746: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x401; +op3val:0x7e01; valaddr_reg:x2; val_offset:23136*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23136*FLEN/8, x3, x1, x4) + +inst_7747: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x401; +op3val:0xfe55; valaddr_reg:x2; val_offset:23139*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23139*FLEN/8, x3, x1, x4) + +inst_7748: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x401; +op3val:0x7c01; valaddr_reg:x2; val_offset:23142*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23142*FLEN/8, x3, x1, x4) + +inst_7749: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x401; +op3val:0xfd55; valaddr_reg:x2; val_offset:23145*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23145*FLEN/8, x3, x1, x4) + +inst_7750: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x401; +op3val:0x3c00; valaddr_reg:x2; val_offset:23148*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23148*FLEN/8, x3, x1, x4) + +inst_7751: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x401; +op3val:0xbc00; valaddr_reg:x2; val_offset:23151*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23151*FLEN/8, x3, x1, x4) + +inst_7752: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8455; +op3val:0x0; valaddr_reg:x2; val_offset:23154*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23154*FLEN/8, x3, x1, x4) + +inst_7753: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8455; +op3val:0x8000; valaddr_reg:x2; val_offset:23157*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23157*FLEN/8, x3, x1, x4) + +inst_7754: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8455; +op3val:0x1; valaddr_reg:x2; val_offset:23160*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23160*FLEN/8, x3, x1, x4) + +inst_7755: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8455; +op3val:0x8001; valaddr_reg:x2; val_offset:23163*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23163*FLEN/8, x3, x1, x4) + +inst_7756: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8455; +op3val:0x2; valaddr_reg:x2; val_offset:23166*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23166*FLEN/8, x3, x1, x4) + +inst_7757: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8455; +op3val:0x83fe; valaddr_reg:x2; val_offset:23169*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23169*FLEN/8, x3, x1, x4) + +inst_7758: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8455; +op3val:0x3ff; valaddr_reg:x2; val_offset:23172*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23172*FLEN/8, x3, x1, x4) + +inst_7759: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8455; +op3val:0x83ff; valaddr_reg:x2; val_offset:23175*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23175*FLEN/8, x3, x1, x4) + +inst_7760: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8455; +op3val:0x400; valaddr_reg:x2; val_offset:23178*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23178*FLEN/8, x3, x1, x4) + +inst_7761: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8455; +op3val:0x8400; valaddr_reg:x2; val_offset:23181*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23181*FLEN/8, x3, x1, x4) + +inst_7762: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8455; +op3val:0x401; valaddr_reg:x2; val_offset:23184*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23184*FLEN/8, x3, x1, x4) + +inst_7763: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8455; +op3val:0x8455; valaddr_reg:x2; val_offset:23187*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23187*FLEN/8, x3, x1, x4) + +inst_7764: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8455; +op3val:0x7bff; valaddr_reg:x2; val_offset:23190*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23190*FLEN/8, x3, x1, x4) + +inst_7765: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8455; +op3val:0xfbff; valaddr_reg:x2; val_offset:23193*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23193*FLEN/8, x3, x1, x4) + +inst_7766: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8455; +op3val:0x7c00; valaddr_reg:x2; val_offset:23196*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23196*FLEN/8, x3, x1, x4) + +inst_7767: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8455; +op3val:0xfc00; valaddr_reg:x2; val_offset:23199*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23199*FLEN/8, x3, x1, x4) + +inst_7768: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8455; +op3val:0x7e00; valaddr_reg:x2; val_offset:23202*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23202*FLEN/8, x3, x1, x4) + +inst_7769: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8455; +op3val:0xfe00; valaddr_reg:x2; val_offset:23205*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23205*FLEN/8, x3, x1, x4) + +inst_7770: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8455; +op3val:0x7e01; valaddr_reg:x2; val_offset:23208*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23208*FLEN/8, x3, x1, x4) + +inst_7771: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8455; +op3val:0xfe55; valaddr_reg:x2; val_offset:23211*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23211*FLEN/8, x3, x1, x4) + +inst_7772: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8455; +op3val:0x7c01; valaddr_reg:x2; val_offset:23214*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23214*FLEN/8, x3, x1, x4) + +inst_7773: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8455; +op3val:0xfd55; valaddr_reg:x2; val_offset:23217*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23217*FLEN/8, x3, x1, x4) + +inst_7774: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8455; +op3val:0x3c00; valaddr_reg:x2; val_offset:23220*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23220*FLEN/8, x3, x1, x4) + +inst_7775: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x8455; +op3val:0xbc00; valaddr_reg:x2; val_offset:23223*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23223*FLEN/8, x3, x1, x4) + +inst_7776: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7bff; +op3val:0x0; valaddr_reg:x2; val_offset:23226*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23226*FLEN/8, x3, x1, x4) + +inst_7777: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7bff; +op3val:0x8000; valaddr_reg:x2; val_offset:23229*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23229*FLEN/8, x3, x1, x4) + +inst_7778: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7bff; +op3val:0x1; valaddr_reg:x2; val_offset:23232*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23232*FLEN/8, x3, x1, x4) + +inst_7779: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7bff; +op3val:0x8001; valaddr_reg:x2; val_offset:23235*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23235*FLEN/8, x3, x1, x4) + +inst_7780: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7bff; +op3val:0x2; valaddr_reg:x2; val_offset:23238*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23238*FLEN/8, x3, x1, x4) + +inst_7781: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7bff; +op3val:0x83fe; valaddr_reg:x2; val_offset:23241*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23241*FLEN/8, x3, x1, x4) + +inst_7782: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7bff; +op3val:0x3ff; valaddr_reg:x2; val_offset:23244*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23244*FLEN/8, x3, x1, x4) + +inst_7783: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7bff; +op3val:0x83ff; valaddr_reg:x2; val_offset:23247*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23247*FLEN/8, x3, x1, x4) + +inst_7784: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7bff; +op3val:0x400; valaddr_reg:x2; val_offset:23250*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23250*FLEN/8, x3, x1, x4) + +inst_7785: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7bff; +op3val:0x8400; valaddr_reg:x2; val_offset:23253*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23253*FLEN/8, x3, x1, x4) + +inst_7786: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7bff; +op3val:0x401; valaddr_reg:x2; val_offset:23256*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23256*FLEN/8, x3, x1, x4) + +inst_7787: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7bff; +op3val:0x8455; valaddr_reg:x2; val_offset:23259*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23259*FLEN/8, x3, x1, x4) + +inst_7788: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7bff; +op3val:0x7bff; valaddr_reg:x2; val_offset:23262*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23262*FLEN/8, x3, x1, x4) + +inst_7789: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7bff; +op3val:0xfbff; valaddr_reg:x2; val_offset:23265*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23265*FLEN/8, x3, x1, x4) + +inst_7790: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7bff; +op3val:0x7c00; valaddr_reg:x2; val_offset:23268*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23268*FLEN/8, x3, x1, x4) + +inst_7791: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7bff; +op3val:0xfc00; valaddr_reg:x2; val_offset:23271*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23271*FLEN/8, x3, x1, x4) + +inst_7792: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7bff; +op3val:0x7e00; valaddr_reg:x2; val_offset:23274*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23274*FLEN/8, x3, x1, x4) + +inst_7793: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7bff; +op3val:0xfe00; valaddr_reg:x2; val_offset:23277*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23277*FLEN/8, x3, x1, x4) + +inst_7794: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7bff; +op3val:0x7e01; valaddr_reg:x2; val_offset:23280*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23280*FLEN/8, x3, x1, x4) + +inst_7795: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7bff; +op3val:0xfe55; valaddr_reg:x2; val_offset:23283*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23283*FLEN/8, x3, x1, x4) + +inst_7796: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7bff; +op3val:0x7c01; valaddr_reg:x2; val_offset:23286*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23286*FLEN/8, x3, x1, x4) + +inst_7797: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7bff; +op3val:0xfd55; valaddr_reg:x2; val_offset:23289*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23289*FLEN/8, x3, x1, x4) + +inst_7798: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7bff; +op3val:0x3c00; valaddr_reg:x2; val_offset:23292*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23292*FLEN/8, x3, x1, x4) + +inst_7799: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7bff; +op3val:0xbc00; valaddr_reg:x2; val_offset:23295*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23295*FLEN/8, x3, x1, x4) + +inst_7800: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfbff; +op3val:0x0; valaddr_reg:x2; val_offset:23298*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23298*FLEN/8, x3, x1, x4) + +inst_7801: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfbff; +op3val:0x8000; valaddr_reg:x2; val_offset:23301*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23301*FLEN/8, x3, x1, x4) + +inst_7802: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfbff; +op3val:0x1; valaddr_reg:x2; val_offset:23304*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23304*FLEN/8, x3, x1, x4) + +inst_7803: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfbff; +op3val:0x8001; valaddr_reg:x2; val_offset:23307*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23307*FLEN/8, x3, x1, x4) + +inst_7804: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfbff; +op3val:0x2; valaddr_reg:x2; val_offset:23310*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23310*FLEN/8, x3, x1, x4) + +inst_7805: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfbff; +op3val:0x83fe; valaddr_reg:x2; val_offset:23313*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23313*FLEN/8, x3, x1, x4) + +inst_7806: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfbff; +op3val:0x3ff; valaddr_reg:x2; val_offset:23316*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23316*FLEN/8, x3, x1, x4) + +inst_7807: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfbff; +op3val:0x83ff; valaddr_reg:x2; val_offset:23319*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23319*FLEN/8, x3, x1, x4) + +inst_7808: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfbff; +op3val:0x400; valaddr_reg:x2; val_offset:23322*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23322*FLEN/8, x3, x1, x4) + +inst_7809: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfbff; +op3val:0x8400; valaddr_reg:x2; val_offset:23325*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23325*FLEN/8, x3, x1, x4) + +inst_7810: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfbff; +op3val:0x401; valaddr_reg:x2; val_offset:23328*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23328*FLEN/8, x3, x1, x4) + +inst_7811: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfbff; +op3val:0x8455; valaddr_reg:x2; val_offset:23331*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23331*FLEN/8, x3, x1, x4) + +inst_7812: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfbff; +op3val:0x7bff; valaddr_reg:x2; val_offset:23334*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23334*FLEN/8, x3, x1, x4) + +inst_7813: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfbff; +op3val:0xfbff; valaddr_reg:x2; val_offset:23337*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23337*FLEN/8, x3, x1, x4) + +inst_7814: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfbff; +op3val:0x7c00; valaddr_reg:x2; val_offset:23340*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23340*FLEN/8, x3, x1, x4) + +inst_7815: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfbff; +op3val:0xfc00; valaddr_reg:x2; val_offset:23343*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23343*FLEN/8, x3, x1, x4) + +inst_7816: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfbff; +op3val:0x7e00; valaddr_reg:x2; val_offset:23346*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23346*FLEN/8, x3, x1, x4) + +inst_7817: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfbff; +op3val:0xfe00; valaddr_reg:x2; val_offset:23349*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23349*FLEN/8, x3, x1, x4) + +inst_7818: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfbff; +op3val:0x7e01; valaddr_reg:x2; val_offset:23352*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23352*FLEN/8, x3, x1, x4) + +inst_7819: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfbff; +op3val:0xfe55; valaddr_reg:x2; val_offset:23355*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23355*FLEN/8, x3, x1, x4) + +inst_7820: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfbff; +op3val:0x7c01; valaddr_reg:x2; val_offset:23358*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23358*FLEN/8, x3, x1, x4) + +inst_7821: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfbff; +op3val:0xfd55; valaddr_reg:x2; val_offset:23361*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23361*FLEN/8, x3, x1, x4) + +inst_7822: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfbff; +op3val:0x3c00; valaddr_reg:x2; val_offset:23364*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23364*FLEN/8, x3, x1, x4) + +inst_7823: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfbff; +op3val:0xbc00; valaddr_reg:x2; val_offset:23367*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23367*FLEN/8, x3, x1, x4) + +inst_7824: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7c00; +op3val:0x0; valaddr_reg:x2; val_offset:23370*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23370*FLEN/8, x3, x1, x4) + +inst_7825: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7c00; +op3val:0x8000; valaddr_reg:x2; val_offset:23373*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23373*FLEN/8, x3, x1, x4) + +inst_7826: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7c00; +op3val:0x1; valaddr_reg:x2; val_offset:23376*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23376*FLEN/8, x3, x1, x4) + +inst_7827: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7c00; +op3val:0x8001; valaddr_reg:x2; val_offset:23379*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23379*FLEN/8, x3, x1, x4) + +inst_7828: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7c00; +op3val:0x2; valaddr_reg:x2; val_offset:23382*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23382*FLEN/8, x3, x1, x4) + +inst_7829: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7c00; +op3val:0x83fe; valaddr_reg:x2; val_offset:23385*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23385*FLEN/8, x3, x1, x4) + +inst_7830: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7c00; +op3val:0x3ff; valaddr_reg:x2; val_offset:23388*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23388*FLEN/8, x3, x1, x4) + +inst_7831: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7c00; +op3val:0x83ff; valaddr_reg:x2; val_offset:23391*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23391*FLEN/8, x3, x1, x4) + +inst_7832: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7c00; +op3val:0x400; valaddr_reg:x2; val_offset:23394*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23394*FLEN/8, x3, x1, x4) + +inst_7833: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7c00; +op3val:0x8400; valaddr_reg:x2; val_offset:23397*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23397*FLEN/8, x3, x1, x4) + +inst_7834: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7c00; +op3val:0x401; valaddr_reg:x2; val_offset:23400*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23400*FLEN/8, x3, x1, x4) + +inst_7835: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7c00; +op3val:0x8455; valaddr_reg:x2; val_offset:23403*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23403*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_62) + +inst_7836: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7c00; +op3val:0x7bff; valaddr_reg:x2; val_offset:23406*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23406*FLEN/8, x3, x1, x4) + +inst_7837: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7c00; +op3val:0xfbff; valaddr_reg:x2; val_offset:23409*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23409*FLEN/8, x3, x1, x4) + +inst_7838: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7c00; +op3val:0x7c00; valaddr_reg:x2; val_offset:23412*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23412*FLEN/8, x3, x1, x4) + +inst_7839: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7c00; +op3val:0xfc00; valaddr_reg:x2; val_offset:23415*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23415*FLEN/8, x3, x1, x4) + +inst_7840: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7c00; +op3val:0x7e00; valaddr_reg:x2; val_offset:23418*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23418*FLEN/8, x3, x1, x4) + +inst_7841: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7c00; +op3val:0xfe00; valaddr_reg:x2; val_offset:23421*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23421*FLEN/8, x3, x1, x4) + +inst_7842: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7c00; +op3val:0x7e01; valaddr_reg:x2; val_offset:23424*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23424*FLEN/8, x3, x1, x4) + +inst_7843: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7c00; +op3val:0xfe55; valaddr_reg:x2; val_offset:23427*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23427*FLEN/8, x3, x1, x4) + +inst_7844: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7c00; +op3val:0x7c01; valaddr_reg:x2; val_offset:23430*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23430*FLEN/8, x3, x1, x4) + +inst_7845: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7c00; +op3val:0xfd55; valaddr_reg:x2; val_offset:23433*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23433*FLEN/8, x3, x1, x4) + +inst_7846: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7c00; +op3val:0x3c00; valaddr_reg:x2; val_offset:23436*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23436*FLEN/8, x3, x1, x4) + +inst_7847: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7c00; +op3val:0xbc00; valaddr_reg:x2; val_offset:23439*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23439*FLEN/8, x3, x1, x4) + +inst_7848: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfc00; +op3val:0x0; valaddr_reg:x2; val_offset:23442*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23442*FLEN/8, x3, x1, x4) + +inst_7849: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfc00; +op3val:0x8000; valaddr_reg:x2; val_offset:23445*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23445*FLEN/8, x3, x1, x4) + +inst_7850: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfc00; +op3val:0x1; valaddr_reg:x2; val_offset:23448*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23448*FLEN/8, x3, x1, x4) + +inst_7851: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfc00; +op3val:0x8001; valaddr_reg:x2; val_offset:23451*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23451*FLEN/8, x3, x1, x4) + +inst_7852: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfc00; +op3val:0x2; valaddr_reg:x2; val_offset:23454*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23454*FLEN/8, x3, x1, x4) + +inst_7853: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfc00; +op3val:0x83fe; valaddr_reg:x2; val_offset:23457*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23457*FLEN/8, x3, x1, x4) + +inst_7854: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfc00; +op3val:0x3ff; valaddr_reg:x2; val_offset:23460*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23460*FLEN/8, x3, x1, x4) + +inst_7855: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfc00; +op3val:0x83ff; valaddr_reg:x2; val_offset:23463*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23463*FLEN/8, x3, x1, x4) + +inst_7856: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfc00; +op3val:0x400; valaddr_reg:x2; val_offset:23466*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23466*FLEN/8, x3, x1, x4) + +inst_7857: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfc00; +op3val:0x8400; valaddr_reg:x2; val_offset:23469*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23469*FLEN/8, x3, x1, x4) + +inst_7858: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfc00; +op3val:0x401; valaddr_reg:x2; val_offset:23472*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23472*FLEN/8, x3, x1, x4) + +inst_7859: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfc00; +op3val:0x8455; valaddr_reg:x2; val_offset:23475*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23475*FLEN/8, x3, x1, x4) + +inst_7860: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfc00; +op3val:0x7bff; valaddr_reg:x2; val_offset:23478*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23478*FLEN/8, x3, x1, x4) + +inst_7861: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfc00; +op3val:0xfbff; valaddr_reg:x2; val_offset:23481*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23481*FLEN/8, x3, x1, x4) + +inst_7862: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfc00; +op3val:0x7c00; valaddr_reg:x2; val_offset:23484*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23484*FLEN/8, x3, x1, x4) + +inst_7863: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfc00; +op3val:0xfc00; valaddr_reg:x2; val_offset:23487*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23487*FLEN/8, x3, x1, x4) + +inst_7864: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfc00; +op3val:0x7e00; valaddr_reg:x2; val_offset:23490*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23490*FLEN/8, x3, x1, x4) + +inst_7865: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfc00; +op3val:0xfe00; valaddr_reg:x2; val_offset:23493*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23493*FLEN/8, x3, x1, x4) + +inst_7866: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfc00; +op3val:0x7e01; valaddr_reg:x2; val_offset:23496*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23496*FLEN/8, x3, x1, x4) + +inst_7867: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfc00; +op3val:0xfe55; valaddr_reg:x2; val_offset:23499*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23499*FLEN/8, x3, x1, x4) + +inst_7868: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfc00; +op3val:0x7c01; valaddr_reg:x2; val_offset:23502*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23502*FLEN/8, x3, x1, x4) + +inst_7869: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfc00; +op3val:0xfd55; valaddr_reg:x2; val_offset:23505*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23505*FLEN/8, x3, x1, x4) + +inst_7870: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfc00; +op3val:0x3c00; valaddr_reg:x2; val_offset:23508*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23508*FLEN/8, x3, x1, x4) + +inst_7871: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfc00; +op3val:0xbc00; valaddr_reg:x2; val_offset:23511*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23511*FLEN/8, x3, x1, x4) + +inst_7872: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7e00; +op3val:0x0; valaddr_reg:x2; val_offset:23514*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23514*FLEN/8, x3, x1, x4) + +inst_7873: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7e00; +op3val:0x8000; valaddr_reg:x2; val_offset:23517*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23517*FLEN/8, x3, x1, x4) + +inst_7874: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7e00; +op3val:0x1; valaddr_reg:x2; val_offset:23520*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23520*FLEN/8, x3, x1, x4) + +inst_7875: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7e00; +op3val:0x8001; valaddr_reg:x2; val_offset:23523*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23523*FLEN/8, x3, x1, x4) + +inst_7876: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7e00; +op3val:0x2; valaddr_reg:x2; val_offset:23526*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23526*FLEN/8, x3, x1, x4) + +inst_7877: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7e00; +op3val:0x83fe; valaddr_reg:x2; val_offset:23529*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23529*FLEN/8, x3, x1, x4) + +inst_7878: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7e00; +op3val:0x3ff; valaddr_reg:x2; val_offset:23532*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23532*FLEN/8, x3, x1, x4) + +inst_7879: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7e00; +op3val:0x83ff; valaddr_reg:x2; val_offset:23535*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23535*FLEN/8, x3, x1, x4) + +inst_7880: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7e00; +op3val:0x400; valaddr_reg:x2; val_offset:23538*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23538*FLEN/8, x3, x1, x4) + +inst_7881: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7e00; +op3val:0x8400; valaddr_reg:x2; val_offset:23541*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23541*FLEN/8, x3, x1, x4) + +inst_7882: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7e00; +op3val:0x401; valaddr_reg:x2; val_offset:23544*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23544*FLEN/8, x3, x1, x4) + +inst_7883: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7e00; +op3val:0x8455; valaddr_reg:x2; val_offset:23547*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23547*FLEN/8, x3, x1, x4) + +inst_7884: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7e00; +op3val:0x7bff; valaddr_reg:x2; val_offset:23550*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23550*FLEN/8, x3, x1, x4) + +inst_7885: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7e00; +op3val:0xfbff; valaddr_reg:x2; val_offset:23553*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23553*FLEN/8, x3, x1, x4) + +inst_7886: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7e00; +op3val:0x7c00; valaddr_reg:x2; val_offset:23556*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23556*FLEN/8, x3, x1, x4) + +inst_7887: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7e00; +op3val:0xfc00; valaddr_reg:x2; val_offset:23559*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23559*FLEN/8, x3, x1, x4) + +inst_7888: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7e00; +op3val:0x7e00; valaddr_reg:x2; val_offset:23562*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23562*FLEN/8, x3, x1, x4) + +inst_7889: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7e00; +op3val:0xfe00; valaddr_reg:x2; val_offset:23565*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23565*FLEN/8, x3, x1, x4) + +inst_7890: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7e00; +op3val:0x7e01; valaddr_reg:x2; val_offset:23568*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23568*FLEN/8, x3, x1, x4) + +inst_7891: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7e00; +op3val:0xfe55; valaddr_reg:x2; val_offset:23571*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23571*FLEN/8, x3, x1, x4) + +inst_7892: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7e00; +op3val:0x7c01; valaddr_reg:x2; val_offset:23574*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23574*FLEN/8, x3, x1, x4) + +inst_7893: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7e00; +op3val:0xfd55; valaddr_reg:x2; val_offset:23577*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23577*FLEN/8, x3, x1, x4) + +inst_7894: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7e00; +op3val:0x3c00; valaddr_reg:x2; val_offset:23580*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23580*FLEN/8, x3, x1, x4) + +inst_7895: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7e00; +op3val:0xbc00; valaddr_reg:x2; val_offset:23583*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23583*FLEN/8, x3, x1, x4) + +inst_7896: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfe00; +op3val:0x0; valaddr_reg:x2; val_offset:23586*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23586*FLEN/8, x3, x1, x4) + +inst_7897: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfe00; +op3val:0x8000; valaddr_reg:x2; val_offset:23589*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23589*FLEN/8, x3, x1, x4) + +inst_7898: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfe00; +op3val:0x1; valaddr_reg:x2; val_offset:23592*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23592*FLEN/8, x3, x1, x4) + +inst_7899: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfe00; +op3val:0x8001; valaddr_reg:x2; val_offset:23595*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23595*FLEN/8, x3, x1, x4) + +inst_7900: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfe00; +op3val:0x2; valaddr_reg:x2; val_offset:23598*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23598*FLEN/8, x3, x1, x4) + +inst_7901: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfe00; +op3val:0x83fe; valaddr_reg:x2; val_offset:23601*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23601*FLEN/8, x3, x1, x4) + +inst_7902: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfe00; +op3val:0x3ff; valaddr_reg:x2; val_offset:23604*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23604*FLEN/8, x3, x1, x4) + +inst_7903: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfe00; +op3val:0x83ff; valaddr_reg:x2; val_offset:23607*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23607*FLEN/8, x3, x1, x4) + +inst_7904: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfe00; +op3val:0x400; valaddr_reg:x2; val_offset:23610*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23610*FLEN/8, x3, x1, x4) + +inst_7905: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfe00; +op3val:0x8400; valaddr_reg:x2; val_offset:23613*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23613*FLEN/8, x3, x1, x4) + +inst_7906: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfe00; +op3val:0x401; valaddr_reg:x2; val_offset:23616*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23616*FLEN/8, x3, x1, x4) + +inst_7907: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfe00; +op3val:0x8455; valaddr_reg:x2; val_offset:23619*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23619*FLEN/8, x3, x1, x4) + +inst_7908: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfe00; +op3val:0x7bff; valaddr_reg:x2; val_offset:23622*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23622*FLEN/8, x3, x1, x4) + +inst_7909: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfe00; +op3val:0xfbff; valaddr_reg:x2; val_offset:23625*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23625*FLEN/8, x3, x1, x4) + +inst_7910: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfe00; +op3val:0x7c00; valaddr_reg:x2; val_offset:23628*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23628*FLEN/8, x3, x1, x4) + +inst_7911: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfe00; +op3val:0xfc00; valaddr_reg:x2; val_offset:23631*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23631*FLEN/8, x3, x1, x4) + +inst_7912: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfe00; +op3val:0x7e00; valaddr_reg:x2; val_offset:23634*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23634*FLEN/8, x3, x1, x4) + +inst_7913: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfe00; +op3val:0xfe00; valaddr_reg:x2; val_offset:23637*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23637*FLEN/8, x3, x1, x4) + +inst_7914: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfe00; +op3val:0x7e01; valaddr_reg:x2; val_offset:23640*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23640*FLEN/8, x3, x1, x4) + +inst_7915: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfe00; +op3val:0xfe55; valaddr_reg:x2; val_offset:23643*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23643*FLEN/8, x3, x1, x4) + +inst_7916: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfe00; +op3val:0x7c01; valaddr_reg:x2; val_offset:23646*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23646*FLEN/8, x3, x1, x4) + +inst_7917: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfe00; +op3val:0xfd55; valaddr_reg:x2; val_offset:23649*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23649*FLEN/8, x3, x1, x4) + +inst_7918: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfe00; +op3val:0x3c00; valaddr_reg:x2; val_offset:23652*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23652*FLEN/8, x3, x1, x4) + +inst_7919: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfe00; +op3val:0xbc00; valaddr_reg:x2; val_offset:23655*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23655*FLEN/8, x3, x1, x4) + +inst_7920: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7e01; +op3val:0x0; valaddr_reg:x2; val_offset:23658*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23658*FLEN/8, x3, x1, x4) + +inst_7921: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7e01; +op3val:0x8000; valaddr_reg:x2; val_offset:23661*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23661*FLEN/8, x3, x1, x4) + +inst_7922: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7e01; +op3val:0x1; valaddr_reg:x2; val_offset:23664*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23664*FLEN/8, x3, x1, x4) + +inst_7923: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7e01; +op3val:0x8001; valaddr_reg:x2; val_offset:23667*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23667*FLEN/8, x3, x1, x4) + +inst_7924: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7e01; +op3val:0x2; valaddr_reg:x2; val_offset:23670*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23670*FLEN/8, x3, x1, x4) + +inst_7925: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7e01; +op3val:0x83fe; valaddr_reg:x2; val_offset:23673*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23673*FLEN/8, x3, x1, x4) + +inst_7926: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7e01; +op3val:0x3ff; valaddr_reg:x2; val_offset:23676*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23676*FLEN/8, x3, x1, x4) + +inst_7927: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7e01; +op3val:0x83ff; valaddr_reg:x2; val_offset:23679*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23679*FLEN/8, x3, x1, x4) + +inst_7928: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7e01; +op3val:0x400; valaddr_reg:x2; val_offset:23682*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23682*FLEN/8, x3, x1, x4) + +inst_7929: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7e01; +op3val:0x8400; valaddr_reg:x2; val_offset:23685*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23685*FLEN/8, x3, x1, x4) + +inst_7930: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7e01; +op3val:0x401; valaddr_reg:x2; val_offset:23688*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23688*FLEN/8, x3, x1, x4) + +inst_7931: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7e01; +op3val:0x8455; valaddr_reg:x2; val_offset:23691*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23691*FLEN/8, x3, x1, x4) + +inst_7932: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7e01; +op3val:0x7bff; valaddr_reg:x2; val_offset:23694*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23694*FLEN/8, x3, x1, x4) + +inst_7933: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7e01; +op3val:0xfbff; valaddr_reg:x2; val_offset:23697*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23697*FLEN/8, x3, x1, x4) + +inst_7934: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7e01; +op3val:0x7c00; valaddr_reg:x2; val_offset:23700*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23700*FLEN/8, x3, x1, x4) + +inst_7935: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7e01; +op3val:0xfc00; valaddr_reg:x2; val_offset:23703*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23703*FLEN/8, x3, x1, x4) + +inst_7936: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7e01; +op3val:0x7e00; valaddr_reg:x2; val_offset:23706*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23706*FLEN/8, x3, x1, x4) + +inst_7937: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7e01; +op3val:0xfe00; valaddr_reg:x2; val_offset:23709*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23709*FLEN/8, x3, x1, x4) + +inst_7938: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7e01; +op3val:0x7e01; valaddr_reg:x2; val_offset:23712*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23712*FLEN/8, x3, x1, x4) + +inst_7939: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7e01; +op3val:0xfe55; valaddr_reg:x2; val_offset:23715*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23715*FLEN/8, x3, x1, x4) + +inst_7940: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7e01; +op3val:0x7c01; valaddr_reg:x2; val_offset:23718*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23718*FLEN/8, x3, x1, x4) + +inst_7941: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7e01; +op3val:0xfd55; valaddr_reg:x2; val_offset:23721*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23721*FLEN/8, x3, x1, x4) + +inst_7942: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7e01; +op3val:0x3c00; valaddr_reg:x2; val_offset:23724*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23724*FLEN/8, x3, x1, x4) + +inst_7943: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7e01; +op3val:0xbc00; valaddr_reg:x2; val_offset:23727*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23727*FLEN/8, x3, x1, x4) + +inst_7944: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfe55; +op3val:0x0; valaddr_reg:x2; val_offset:23730*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23730*FLEN/8, x3, x1, x4) + +inst_7945: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfe55; +op3val:0x8000; valaddr_reg:x2; val_offset:23733*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23733*FLEN/8, x3, x1, x4) + +inst_7946: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfe55; +op3val:0x1; valaddr_reg:x2; val_offset:23736*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23736*FLEN/8, x3, x1, x4) + +inst_7947: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfe55; +op3val:0x8001; valaddr_reg:x2; val_offset:23739*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23739*FLEN/8, x3, x1, x4) + +inst_7948: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfe55; +op3val:0x2; valaddr_reg:x2; val_offset:23742*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23742*FLEN/8, x3, x1, x4) + +inst_7949: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfe55; +op3val:0x83fe; valaddr_reg:x2; val_offset:23745*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23745*FLEN/8, x3, x1, x4) + +inst_7950: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfe55; +op3val:0x3ff; valaddr_reg:x2; val_offset:23748*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23748*FLEN/8, x3, x1, x4) + +inst_7951: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfe55; +op3val:0x83ff; valaddr_reg:x2; val_offset:23751*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23751*FLEN/8, x3, x1, x4) + +inst_7952: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfe55; +op3val:0x400; valaddr_reg:x2; val_offset:23754*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23754*FLEN/8, x3, x1, x4) + +inst_7953: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfe55; +op3val:0x8400; valaddr_reg:x2; val_offset:23757*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23757*FLEN/8, x3, x1, x4) + +inst_7954: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfe55; +op3val:0x401; valaddr_reg:x2; val_offset:23760*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23760*FLEN/8, x3, x1, x4) + +inst_7955: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfe55; +op3val:0x8455; valaddr_reg:x2; val_offset:23763*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23763*FLEN/8, x3, x1, x4) + +inst_7956: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfe55; +op3val:0x7bff; valaddr_reg:x2; val_offset:23766*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23766*FLEN/8, x3, x1, x4) + +inst_7957: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfe55; +op3val:0xfbff; valaddr_reg:x2; val_offset:23769*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23769*FLEN/8, x3, x1, x4) + +inst_7958: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfe55; +op3val:0x7c00; valaddr_reg:x2; val_offset:23772*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23772*FLEN/8, x3, x1, x4) + +inst_7959: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfe55; +op3val:0xfc00; valaddr_reg:x2; val_offset:23775*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23775*FLEN/8, x3, x1, x4) + +inst_7960: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfe55; +op3val:0x7e00; valaddr_reg:x2; val_offset:23778*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23778*FLEN/8, x3, x1, x4) + +inst_7961: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfe55; +op3val:0xfe00; valaddr_reg:x2; val_offset:23781*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23781*FLEN/8, x3, x1, x4) + +inst_7962: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfe55; +op3val:0x7e01; valaddr_reg:x2; val_offset:23784*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23784*FLEN/8, x3, x1, x4) + +inst_7963: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfe55; +op3val:0xfe55; valaddr_reg:x2; val_offset:23787*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23787*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_63) + +inst_7964: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfe55; +op3val:0x7c01; valaddr_reg:x2; val_offset:23790*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23790*FLEN/8, x3, x1, x4) + +inst_7965: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfe55; +op3val:0xfd55; valaddr_reg:x2; val_offset:23793*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23793*FLEN/8, x3, x1, x4) + +inst_7966: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfe55; +op3val:0x3c00; valaddr_reg:x2; val_offset:23796*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23796*FLEN/8, x3, x1, x4) + +inst_7967: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfe55; +op3val:0xbc00; valaddr_reg:x2; val_offset:23799*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23799*FLEN/8, x3, x1, x4) + +inst_7968: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7c01; +op3val:0x0; valaddr_reg:x2; val_offset:23802*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23802*FLEN/8, x3, x1, x4) + +inst_7969: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7c01; +op3val:0x8000; valaddr_reg:x2; val_offset:23805*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23805*FLEN/8, x3, x1, x4) + +inst_7970: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7c01; +op3val:0x1; valaddr_reg:x2; val_offset:23808*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23808*FLEN/8, x3, x1, x4) + +inst_7971: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7c01; +op3val:0x8001; valaddr_reg:x2; val_offset:23811*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23811*FLEN/8, x3, x1, x4) + +inst_7972: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7c01; +op3val:0x2; valaddr_reg:x2; val_offset:23814*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23814*FLEN/8, x3, x1, x4) + +inst_7973: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7c01; +op3val:0x83fe; valaddr_reg:x2; val_offset:23817*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23817*FLEN/8, x3, x1, x4) + +inst_7974: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7c01; +op3val:0x3ff; valaddr_reg:x2; val_offset:23820*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23820*FLEN/8, x3, x1, x4) + +inst_7975: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7c01; +op3val:0x83ff; valaddr_reg:x2; val_offset:23823*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23823*FLEN/8, x3, x1, x4) + +inst_7976: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7c01; +op3val:0x400; valaddr_reg:x2; val_offset:23826*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23826*FLEN/8, x3, x1, x4) + +inst_7977: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7c01; +op3val:0x8400; valaddr_reg:x2; val_offset:23829*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23829*FLEN/8, x3, x1, x4) + +inst_7978: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7c01; +op3val:0x401; valaddr_reg:x2; val_offset:23832*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23832*FLEN/8, x3, x1, x4) + +inst_7979: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7c01; +op3val:0x8455; valaddr_reg:x2; val_offset:23835*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23835*FLEN/8, x3, x1, x4) + +inst_7980: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7c01; +op3val:0x7bff; valaddr_reg:x2; val_offset:23838*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23838*FLEN/8, x3, x1, x4) + +inst_7981: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7c01; +op3val:0xfbff; valaddr_reg:x2; val_offset:23841*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23841*FLEN/8, x3, x1, x4) + +inst_7982: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7c01; +op3val:0x7c00; valaddr_reg:x2; val_offset:23844*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23844*FLEN/8, x3, x1, x4) + +inst_7983: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7c01; +op3val:0xfc00; valaddr_reg:x2; val_offset:23847*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23847*FLEN/8, x3, x1, x4) + +inst_7984: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7c01; +op3val:0x7e00; valaddr_reg:x2; val_offset:23850*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23850*FLEN/8, x3, x1, x4) + +inst_7985: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7c01; +op3val:0xfe00; valaddr_reg:x2; val_offset:23853*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23853*FLEN/8, x3, x1, x4) + +inst_7986: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7c01; +op3val:0x7e01; valaddr_reg:x2; val_offset:23856*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23856*FLEN/8, x3, x1, x4) + +inst_7987: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7c01; +op3val:0xfe55; valaddr_reg:x2; val_offset:23859*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23859*FLEN/8, x3, x1, x4) + +inst_7988: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7c01; +op3val:0x7c01; valaddr_reg:x2; val_offset:23862*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23862*FLEN/8, x3, x1, x4) + +inst_7989: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7c01; +op3val:0xfd55; valaddr_reg:x2; val_offset:23865*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23865*FLEN/8, x3, x1, x4) + +inst_7990: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7c01; +op3val:0x3c00; valaddr_reg:x2; val_offset:23868*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23868*FLEN/8, x3, x1, x4) + +inst_7991: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x7c01; +op3val:0xbc00; valaddr_reg:x2; val_offset:23871*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23871*FLEN/8, x3, x1, x4) + +inst_7992: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfd55; +op3val:0x0; valaddr_reg:x2; val_offset:23874*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23874*FLEN/8, x3, x1, x4) + +inst_7993: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfd55; +op3val:0x8000; valaddr_reg:x2; val_offset:23877*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23877*FLEN/8, x3, x1, x4) + +inst_7994: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfd55; +op3val:0x1; valaddr_reg:x2; val_offset:23880*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23880*FLEN/8, x3, x1, x4) + +inst_7995: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfd55; +op3val:0x8001; valaddr_reg:x2; val_offset:23883*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23883*FLEN/8, x3, x1, x4) + +inst_7996: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfd55; +op3val:0x2; valaddr_reg:x2; val_offset:23886*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23886*FLEN/8, x3, x1, x4) + +inst_7997: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfd55; +op3val:0x83fe; valaddr_reg:x2; val_offset:23889*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23889*FLEN/8, x3, x1, x4) + +inst_7998: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfd55; +op3val:0x3ff; valaddr_reg:x2; val_offset:23892*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23892*FLEN/8, x3, x1, x4) + +inst_7999: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfd55; +op3val:0x83ff; valaddr_reg:x2; val_offset:23895*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23895*FLEN/8, x3, x1, x4) + +inst_8000: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfd55; +op3val:0x400; valaddr_reg:x2; val_offset:23898*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23898*FLEN/8, x3, x1, x4) + +inst_8001: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfd55; +op3val:0x8400; valaddr_reg:x2; val_offset:23901*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23901*FLEN/8, x3, x1, x4) + +inst_8002: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfd55; +op3val:0x401; valaddr_reg:x2; val_offset:23904*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23904*FLEN/8, x3, x1, x4) + +inst_8003: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfd55; +op3val:0x8455; valaddr_reg:x2; val_offset:23907*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23907*FLEN/8, x3, x1, x4) + +inst_8004: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfd55; +op3val:0x7bff; valaddr_reg:x2; val_offset:23910*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23910*FLEN/8, x3, x1, x4) + +inst_8005: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfd55; +op3val:0xfbff; valaddr_reg:x2; val_offset:23913*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23913*FLEN/8, x3, x1, x4) + +inst_8006: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfd55; +op3val:0x7c00; valaddr_reg:x2; val_offset:23916*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23916*FLEN/8, x3, x1, x4) + +inst_8007: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfd55; +op3val:0xfc00; valaddr_reg:x2; val_offset:23919*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23919*FLEN/8, x3, x1, x4) + +inst_8008: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfd55; +op3val:0x7e00; valaddr_reg:x2; val_offset:23922*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23922*FLEN/8, x3, x1, x4) + +inst_8009: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfd55; +op3val:0xfe00; valaddr_reg:x2; val_offset:23925*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23925*FLEN/8, x3, x1, x4) + +inst_8010: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfd55; +op3val:0x7e01; valaddr_reg:x2; val_offset:23928*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23928*FLEN/8, x3, x1, x4) + +inst_8011: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfd55; +op3val:0xfe55; valaddr_reg:x2; val_offset:23931*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23931*FLEN/8, x3, x1, x4) + +inst_8012: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfd55; +op3val:0x7c01; valaddr_reg:x2; val_offset:23934*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23934*FLEN/8, x3, x1, x4) + +inst_8013: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfd55; +op3val:0xfd55; valaddr_reg:x2; val_offset:23937*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23937*FLEN/8, x3, x1, x4) + +inst_8014: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfd55; +op3val:0x3c00; valaddr_reg:x2; val_offset:23940*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23940*FLEN/8, x3, x1, x4) + +inst_8015: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xfd55; +op3val:0xbc00; valaddr_reg:x2; val_offset:23943*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23943*FLEN/8, x3, x1, x4) + +inst_8016: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x3c00; +op3val:0x0; valaddr_reg:x2; val_offset:23946*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23946*FLEN/8, x3, x1, x4) + +inst_8017: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x3c00; +op3val:0x8000; valaddr_reg:x2; val_offset:23949*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23949*FLEN/8, x3, x1, x4) + +inst_8018: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x3c00; +op3val:0x1; valaddr_reg:x2; val_offset:23952*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23952*FLEN/8, x3, x1, x4) + +inst_8019: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x3c00; +op3val:0x8001; valaddr_reg:x2; val_offset:23955*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23955*FLEN/8, x3, x1, x4) + +inst_8020: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x3c00; +op3val:0x2; valaddr_reg:x2; val_offset:23958*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23958*FLEN/8, x3, x1, x4) + +inst_8021: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x3c00; +op3val:0x83fe; valaddr_reg:x2; val_offset:23961*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23961*FLEN/8, x3, x1, x4) + +inst_8022: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x3c00; +op3val:0x3ff; valaddr_reg:x2; val_offset:23964*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23964*FLEN/8, x3, x1, x4) + +inst_8023: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x3c00; +op3val:0x83ff; valaddr_reg:x2; val_offset:23967*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23967*FLEN/8, x3, x1, x4) + +inst_8024: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x3c00; +op3val:0x400; valaddr_reg:x2; val_offset:23970*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23970*FLEN/8, x3, x1, x4) + +inst_8025: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x3c00; +op3val:0x8400; valaddr_reg:x2; val_offset:23973*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23973*FLEN/8, x3, x1, x4) + +inst_8026: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x3c00; +op3val:0x401; valaddr_reg:x2; val_offset:23976*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23976*FLEN/8, x3, x1, x4) + +inst_8027: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x3c00; +op3val:0x8455; valaddr_reg:x2; val_offset:23979*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23979*FLEN/8, x3, x1, x4) + +inst_8028: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x3c00; +op3val:0x7bff; valaddr_reg:x2; val_offset:23982*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23982*FLEN/8, x3, x1, x4) + +inst_8029: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x3c00; +op3val:0xfbff; valaddr_reg:x2; val_offset:23985*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23985*FLEN/8, x3, x1, x4) + +inst_8030: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x3c00; +op3val:0x7c00; valaddr_reg:x2; val_offset:23988*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23988*FLEN/8, x3, x1, x4) + +inst_8031: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x3c00; +op3val:0xfc00; valaddr_reg:x2; val_offset:23991*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23991*FLEN/8, x3, x1, x4) + +inst_8032: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x3c00; +op3val:0x7e00; valaddr_reg:x2; val_offset:23994*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23994*FLEN/8, x3, x1, x4) + +inst_8033: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x3c00; +op3val:0xfe00; valaddr_reg:x2; val_offset:23997*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 23997*FLEN/8, x3, x1, x4) + +inst_8034: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x3c00; +op3val:0x7e01; valaddr_reg:x2; val_offset:24000*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24000*FLEN/8, x3, x1, x4) + +inst_8035: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x3c00; +op3val:0xfe55; valaddr_reg:x2; val_offset:24003*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24003*FLEN/8, x3, x1, x4) + +inst_8036: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x3c00; +op3val:0x7c01; valaddr_reg:x2; val_offset:24006*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24006*FLEN/8, x3, x1, x4) + +inst_8037: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x3c00; +op3val:0xfd55; valaddr_reg:x2; val_offset:24009*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24009*FLEN/8, x3, x1, x4) + +inst_8038: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x3c00; +op3val:0x3c00; valaddr_reg:x2; val_offset:24012*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24012*FLEN/8, x3, x1, x4) + +inst_8039: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0x3c00; +op3val:0xbc00; valaddr_reg:x2; val_offset:24015*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24015*FLEN/8, x3, x1, x4) + +inst_8040: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xbc00; +op3val:0x0; valaddr_reg:x2; val_offset:24018*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24018*FLEN/8, x3, x1, x4) + +inst_8041: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xbc00; +op3val:0x8000; valaddr_reg:x2; val_offset:24021*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24021*FLEN/8, x3, x1, x4) + +inst_8042: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xbc00; +op3val:0x1; valaddr_reg:x2; val_offset:24024*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24024*FLEN/8, x3, x1, x4) + +inst_8043: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xbc00; +op3val:0x8001; valaddr_reg:x2; val_offset:24027*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24027*FLEN/8, x3, x1, x4) + +inst_8044: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xbc00; +op3val:0x2; valaddr_reg:x2; val_offset:24030*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24030*FLEN/8, x3, x1, x4) + +inst_8045: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xbc00; +op3val:0x83fe; valaddr_reg:x2; val_offset:24033*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24033*FLEN/8, x3, x1, x4) + +inst_8046: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xbc00; +op3val:0x3ff; valaddr_reg:x2; val_offset:24036*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24036*FLEN/8, x3, x1, x4) + +inst_8047: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xbc00; +op3val:0x83ff; valaddr_reg:x2; val_offset:24039*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24039*FLEN/8, x3, x1, x4) + +inst_8048: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xbc00; +op3val:0x400; valaddr_reg:x2; val_offset:24042*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24042*FLEN/8, x3, x1, x4) + +inst_8049: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xbc00; +op3val:0x8400; valaddr_reg:x2; val_offset:24045*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24045*FLEN/8, x3, x1, x4) + +inst_8050: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xbc00; +op3val:0x401; valaddr_reg:x2; val_offset:24048*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24048*FLEN/8, x3, x1, x4) + +inst_8051: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xbc00; +op3val:0x8455; valaddr_reg:x2; val_offset:24051*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24051*FLEN/8, x3, x1, x4) + +inst_8052: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xbc00; +op3val:0x7bff; valaddr_reg:x2; val_offset:24054*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24054*FLEN/8, x3, x1, x4) + +inst_8053: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xbc00; +op3val:0xfbff; valaddr_reg:x2; val_offset:24057*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24057*FLEN/8, x3, x1, x4) + +inst_8054: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xbc00; +op3val:0x7c00; valaddr_reg:x2; val_offset:24060*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24060*FLEN/8, x3, x1, x4) + +inst_8055: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xbc00; +op3val:0xfc00; valaddr_reg:x2; val_offset:24063*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24063*FLEN/8, x3, x1, x4) + +inst_8056: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xbc00; +op3val:0x7e00; valaddr_reg:x2; val_offset:24066*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24066*FLEN/8, x3, x1, x4) + +inst_8057: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xbc00; +op3val:0xfe00; valaddr_reg:x2; val_offset:24069*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24069*FLEN/8, x3, x1, x4) + +inst_8058: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xbc00; +op3val:0x7e01; valaddr_reg:x2; val_offset:24072*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24072*FLEN/8, x3, x1, x4) + +inst_8059: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xbc00; +op3val:0xfe55; valaddr_reg:x2; val_offset:24075*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24075*FLEN/8, x3, x1, x4) + +inst_8060: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xbc00; +op3val:0x7c01; valaddr_reg:x2; val_offset:24078*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24078*FLEN/8, x3, x1, x4) + +inst_8061: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xbc00; +op3val:0xfd55; valaddr_reg:x2; val_offset:24081*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24081*FLEN/8, x3, x1, x4) + +inst_8062: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xbc00; +op3val:0x3c00; valaddr_reg:x2; val_offset:24084*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24084*FLEN/8, x3, x1, x4) + +inst_8063: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfbff; op2val:0xbc00; +op3val:0xbc00; valaddr_reg:x2; val_offset:24087*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24087*FLEN/8, x3, x1, x4) + +inst_8064: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x0; +op3val:0x0; valaddr_reg:x2; val_offset:24090*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24090*FLEN/8, x3, x1, x4) + +inst_8065: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x0; +op3val:0x8000; valaddr_reg:x2; val_offset:24093*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24093*FLEN/8, x3, x1, x4) + +inst_8066: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x0; +op3val:0x1; valaddr_reg:x2; val_offset:24096*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24096*FLEN/8, x3, x1, x4) + +inst_8067: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x0; +op3val:0x8001; valaddr_reg:x2; val_offset:24099*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24099*FLEN/8, x3, x1, x4) + +inst_8068: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x0; +op3val:0x2; valaddr_reg:x2; val_offset:24102*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24102*FLEN/8, x3, x1, x4) + +inst_8069: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x0; +op3val:0x83fe; valaddr_reg:x2; val_offset:24105*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24105*FLEN/8, x3, x1, x4) + +inst_8070: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x0; +op3val:0x3ff; valaddr_reg:x2; val_offset:24108*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24108*FLEN/8, x3, x1, x4) + +inst_8071: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x0; +op3val:0x83ff; valaddr_reg:x2; val_offset:24111*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24111*FLEN/8, x3, x1, x4) + +inst_8072: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x0; +op3val:0x400; valaddr_reg:x2; val_offset:24114*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24114*FLEN/8, x3, x1, x4) + +inst_8073: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x0; +op3val:0x8400; valaddr_reg:x2; val_offset:24117*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24117*FLEN/8, x3, x1, x4) + +inst_8074: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x0; +op3val:0x401; valaddr_reg:x2; val_offset:24120*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24120*FLEN/8, x3, x1, x4) + +inst_8075: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x0; +op3val:0x8455; valaddr_reg:x2; val_offset:24123*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24123*FLEN/8, x3, x1, x4) + +inst_8076: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x0; +op3val:0x7bff; valaddr_reg:x2; val_offset:24126*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24126*FLEN/8, x3, x1, x4) + +inst_8077: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x0; +op3val:0xfbff; valaddr_reg:x2; val_offset:24129*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24129*FLEN/8, x3, x1, x4) + +inst_8078: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x0; +op3val:0x7c00; valaddr_reg:x2; val_offset:24132*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24132*FLEN/8, x3, x1, x4) + +inst_8079: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x0; +op3val:0xfc00; valaddr_reg:x2; val_offset:24135*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24135*FLEN/8, x3, x1, x4) + +inst_8080: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x0; +op3val:0x7e00; valaddr_reg:x2; val_offset:24138*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24138*FLEN/8, x3, x1, x4) + +inst_8081: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x0; +op3val:0xfe00; valaddr_reg:x2; val_offset:24141*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24141*FLEN/8, x3, x1, x4) + +inst_8082: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x0; +op3val:0x7e01; valaddr_reg:x2; val_offset:24144*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24144*FLEN/8, x3, x1, x4) + +inst_8083: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x0; +op3val:0xfe55; valaddr_reg:x2; val_offset:24147*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24147*FLEN/8, x3, x1, x4) + +inst_8084: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x0; +op3val:0x7c01; valaddr_reg:x2; val_offset:24150*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24150*FLEN/8, x3, x1, x4) + +inst_8085: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x0; +op3val:0xfd55; valaddr_reg:x2; val_offset:24153*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24153*FLEN/8, x3, x1, x4) + +inst_8086: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x0; +op3val:0x3c00; valaddr_reg:x2; val_offset:24156*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24156*FLEN/8, x3, x1, x4) + +inst_8087: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x0; +op3val:0xbc00; valaddr_reg:x2; val_offset:24159*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24159*FLEN/8, x3, x1, x4) + +inst_8088: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8000; +op3val:0x0; valaddr_reg:x2; val_offset:24162*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24162*FLEN/8, x3, x1, x4) + +inst_8089: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8000; +op3val:0x8000; valaddr_reg:x2; val_offset:24165*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24165*FLEN/8, x3, x1, x4) + +inst_8090: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8000; +op3val:0x1; valaddr_reg:x2; val_offset:24168*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24168*FLEN/8, x3, x1, x4) + +inst_8091: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8000; +op3val:0x8001; valaddr_reg:x2; val_offset:24171*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24171*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_64) + +inst_8092: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8000; +op3val:0x2; valaddr_reg:x2; val_offset:24174*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24174*FLEN/8, x3, x1, x4) + +inst_8093: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8000; +op3val:0x83fe; valaddr_reg:x2; val_offset:24177*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24177*FLEN/8, x3, x1, x4) + +inst_8094: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8000; +op3val:0x3ff; valaddr_reg:x2; val_offset:24180*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24180*FLEN/8, x3, x1, x4) + +inst_8095: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8000; +op3val:0x83ff; valaddr_reg:x2; val_offset:24183*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24183*FLEN/8, x3, x1, x4) + +inst_8096: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8000; +op3val:0x400; valaddr_reg:x2; val_offset:24186*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24186*FLEN/8, x3, x1, x4) + +inst_8097: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8000; +op3val:0x8400; valaddr_reg:x2; val_offset:24189*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24189*FLEN/8, x3, x1, x4) + +inst_8098: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8000; +op3val:0x401; valaddr_reg:x2; val_offset:24192*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24192*FLEN/8, x3, x1, x4) + +inst_8099: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8000; +op3val:0x8455; valaddr_reg:x2; val_offset:24195*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24195*FLEN/8, x3, x1, x4) + +inst_8100: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x2; val_offset:24198*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24198*FLEN/8, x3, x1, x4) + +inst_8101: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x2; val_offset:24201*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24201*FLEN/8, x3, x1, x4) + +inst_8102: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8000; +op3val:0x7c00; valaddr_reg:x2; val_offset:24204*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24204*FLEN/8, x3, x1, x4) + +inst_8103: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8000; +op3val:0xfc00; valaddr_reg:x2; val_offset:24207*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24207*FLEN/8, x3, x1, x4) + +inst_8104: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8000; +op3val:0x7e00; valaddr_reg:x2; val_offset:24210*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24210*FLEN/8, x3, x1, x4) + +inst_8105: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8000; +op3val:0xfe00; valaddr_reg:x2; val_offset:24213*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24213*FLEN/8, x3, x1, x4) + +inst_8106: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8000; +op3val:0x7e01; valaddr_reg:x2; val_offset:24216*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24216*FLEN/8, x3, x1, x4) + +inst_8107: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8000; +op3val:0xfe55; valaddr_reg:x2; val_offset:24219*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24219*FLEN/8, x3, x1, x4) + +inst_8108: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8000; +op3val:0x7c01; valaddr_reg:x2; val_offset:24222*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24222*FLEN/8, x3, x1, x4) + +inst_8109: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8000; +op3val:0xfd55; valaddr_reg:x2; val_offset:24225*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24225*FLEN/8, x3, x1, x4) + +inst_8110: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8000; +op3val:0x3c00; valaddr_reg:x2; val_offset:24228*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24228*FLEN/8, x3, x1, x4) + +inst_8111: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8000; +op3val:0xbc00; valaddr_reg:x2; val_offset:24231*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24231*FLEN/8, x3, x1, x4) + +inst_8112: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x1; +op3val:0x0; valaddr_reg:x2; val_offset:24234*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24234*FLEN/8, x3, x1, x4) + +inst_8113: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x1; +op3val:0x8000; valaddr_reg:x2; val_offset:24237*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24237*FLEN/8, x3, x1, x4) + +inst_8114: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x1; +op3val:0x1; valaddr_reg:x2; val_offset:24240*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24240*FLEN/8, x3, x1, x4) + +inst_8115: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x1; +op3val:0x8001; valaddr_reg:x2; val_offset:24243*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24243*FLEN/8, x3, x1, x4) + +inst_8116: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x1; +op3val:0x2; valaddr_reg:x2; val_offset:24246*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24246*FLEN/8, x3, x1, x4) + +inst_8117: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x1; +op3val:0x83fe; valaddr_reg:x2; val_offset:24249*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24249*FLEN/8, x3, x1, x4) + +inst_8118: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x1; +op3val:0x3ff; valaddr_reg:x2; val_offset:24252*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24252*FLEN/8, x3, x1, x4) + +inst_8119: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x1; +op3val:0x83ff; valaddr_reg:x2; val_offset:24255*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24255*FLEN/8, x3, x1, x4) + +inst_8120: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x1; +op3val:0x400; valaddr_reg:x2; val_offset:24258*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24258*FLEN/8, x3, x1, x4) + +inst_8121: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x1; +op3val:0x8400; valaddr_reg:x2; val_offset:24261*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24261*FLEN/8, x3, x1, x4) + +inst_8122: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x1; +op3val:0x401; valaddr_reg:x2; val_offset:24264*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24264*FLEN/8, x3, x1, x4) + +inst_8123: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x1; +op3val:0x8455; valaddr_reg:x2; val_offset:24267*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24267*FLEN/8, x3, x1, x4) + +inst_8124: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x1; +op3val:0x7bff; valaddr_reg:x2; val_offset:24270*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24270*FLEN/8, x3, x1, x4) + +inst_8125: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x1; +op3val:0xfbff; valaddr_reg:x2; val_offset:24273*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24273*FLEN/8, x3, x1, x4) + +inst_8126: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x1; +op3val:0x7c00; valaddr_reg:x2; val_offset:24276*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24276*FLEN/8, x3, x1, x4) + +inst_8127: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x1; +op3val:0xfc00; valaddr_reg:x2; val_offset:24279*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24279*FLEN/8, x3, x1, x4) + +inst_8128: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x1; +op3val:0x7e00; valaddr_reg:x2; val_offset:24282*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24282*FLEN/8, x3, x1, x4) + +inst_8129: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x1; +op3val:0xfe00; valaddr_reg:x2; val_offset:24285*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24285*FLEN/8, x3, x1, x4) + +inst_8130: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x1; +op3val:0x7e01; valaddr_reg:x2; val_offset:24288*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24288*FLEN/8, x3, x1, x4) + +inst_8131: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x1; +op3val:0xfe55; valaddr_reg:x2; val_offset:24291*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24291*FLEN/8, x3, x1, x4) + +inst_8132: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x1; +op3val:0x7c01; valaddr_reg:x2; val_offset:24294*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24294*FLEN/8, x3, x1, x4) + +inst_8133: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x1; +op3val:0xfd55; valaddr_reg:x2; val_offset:24297*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24297*FLEN/8, x3, x1, x4) + +inst_8134: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x1; +op3val:0x3c00; valaddr_reg:x2; val_offset:24300*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24300*FLEN/8, x3, x1, x4) + +inst_8135: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x1; +op3val:0xbc00; valaddr_reg:x2; val_offset:24303*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24303*FLEN/8, x3, x1, x4) + +inst_8136: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8001; +op3val:0x0; valaddr_reg:x2; val_offset:24306*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24306*FLEN/8, x3, x1, x4) + +inst_8137: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8001; +op3val:0x8000; valaddr_reg:x2; val_offset:24309*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24309*FLEN/8, x3, x1, x4) + +inst_8138: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8001; +op3val:0x1; valaddr_reg:x2; val_offset:24312*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24312*FLEN/8, x3, x1, x4) + +inst_8139: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8001; +op3val:0x8001; valaddr_reg:x2; val_offset:24315*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24315*FLEN/8, x3, x1, x4) + +inst_8140: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8001; +op3val:0x2; valaddr_reg:x2; val_offset:24318*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24318*FLEN/8, x3, x1, x4) + +inst_8141: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8001; +op3val:0x83fe; valaddr_reg:x2; val_offset:24321*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24321*FLEN/8, x3, x1, x4) + +inst_8142: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8001; +op3val:0x3ff; valaddr_reg:x2; val_offset:24324*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24324*FLEN/8, x3, x1, x4) + +inst_8143: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8001; +op3val:0x83ff; valaddr_reg:x2; val_offset:24327*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24327*FLEN/8, x3, x1, x4) + +inst_8144: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8001; +op3val:0x400; valaddr_reg:x2; val_offset:24330*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24330*FLEN/8, x3, x1, x4) + +inst_8145: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8001; +op3val:0x8400; valaddr_reg:x2; val_offset:24333*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24333*FLEN/8, x3, x1, x4) + +inst_8146: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8001; +op3val:0x401; valaddr_reg:x2; val_offset:24336*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24336*FLEN/8, x3, x1, x4) + +inst_8147: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8001; +op3val:0x8455; valaddr_reg:x2; val_offset:24339*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24339*FLEN/8, x3, x1, x4) + +inst_8148: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8001; +op3val:0x7bff; valaddr_reg:x2; val_offset:24342*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24342*FLEN/8, x3, x1, x4) + +inst_8149: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8001; +op3val:0xfbff; valaddr_reg:x2; val_offset:24345*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24345*FLEN/8, x3, x1, x4) + +inst_8150: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8001; +op3val:0x7c00; valaddr_reg:x2; val_offset:24348*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24348*FLEN/8, x3, x1, x4) + +inst_8151: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8001; +op3val:0xfc00; valaddr_reg:x2; val_offset:24351*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24351*FLEN/8, x3, x1, x4) + +inst_8152: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8001; +op3val:0x7e00; valaddr_reg:x2; val_offset:24354*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24354*FLEN/8, x3, x1, x4) + +inst_8153: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8001; +op3val:0xfe00; valaddr_reg:x2; val_offset:24357*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24357*FLEN/8, x3, x1, x4) + +inst_8154: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8001; +op3val:0x7e01; valaddr_reg:x2; val_offset:24360*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24360*FLEN/8, x3, x1, x4) + +inst_8155: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8001; +op3val:0xfe55; valaddr_reg:x2; val_offset:24363*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24363*FLEN/8, x3, x1, x4) + +inst_8156: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8001; +op3val:0x7c01; valaddr_reg:x2; val_offset:24366*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24366*FLEN/8, x3, x1, x4) + +inst_8157: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8001; +op3val:0xfd55; valaddr_reg:x2; val_offset:24369*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24369*FLEN/8, x3, x1, x4) + +inst_8158: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8001; +op3val:0x3c00; valaddr_reg:x2; val_offset:24372*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24372*FLEN/8, x3, x1, x4) + +inst_8159: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8001; +op3val:0xbc00; valaddr_reg:x2; val_offset:24375*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24375*FLEN/8, x3, x1, x4) + +inst_8160: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x2; +op3val:0x0; valaddr_reg:x2; val_offset:24378*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24378*FLEN/8, x3, x1, x4) + +inst_8161: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x2; +op3val:0x8000; valaddr_reg:x2; val_offset:24381*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24381*FLEN/8, x3, x1, x4) + +inst_8162: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x2; +op3val:0x1; valaddr_reg:x2; val_offset:24384*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24384*FLEN/8, x3, x1, x4) + +inst_8163: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x2; +op3val:0x8001; valaddr_reg:x2; val_offset:24387*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24387*FLEN/8, x3, x1, x4) + +inst_8164: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x2; +op3val:0x2; valaddr_reg:x2; val_offset:24390*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24390*FLEN/8, x3, x1, x4) + +inst_8165: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x2; +op3val:0x83fe; valaddr_reg:x2; val_offset:24393*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24393*FLEN/8, x3, x1, x4) + +inst_8166: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x2; +op3val:0x3ff; valaddr_reg:x2; val_offset:24396*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24396*FLEN/8, x3, x1, x4) + +inst_8167: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x2; +op3val:0x83ff; valaddr_reg:x2; val_offset:24399*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24399*FLEN/8, x3, x1, x4) + +inst_8168: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x2; +op3val:0x400; valaddr_reg:x2; val_offset:24402*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24402*FLEN/8, x3, x1, x4) + +inst_8169: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x2; +op3val:0x8400; valaddr_reg:x2; val_offset:24405*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24405*FLEN/8, x3, x1, x4) + +inst_8170: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x2; +op3val:0x401; valaddr_reg:x2; val_offset:24408*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24408*FLEN/8, x3, x1, x4) + +inst_8171: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x2; +op3val:0x8455; valaddr_reg:x2; val_offset:24411*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24411*FLEN/8, x3, x1, x4) + +inst_8172: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x2; +op3val:0x7bff; valaddr_reg:x2; val_offset:24414*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24414*FLEN/8, x3, x1, x4) + +inst_8173: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x2; +op3val:0xfbff; valaddr_reg:x2; val_offset:24417*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24417*FLEN/8, x3, x1, x4) + +inst_8174: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x2; +op3val:0x7c00; valaddr_reg:x2; val_offset:24420*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24420*FLEN/8, x3, x1, x4) + +inst_8175: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x2; +op3val:0xfc00; valaddr_reg:x2; val_offset:24423*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24423*FLEN/8, x3, x1, x4) + +inst_8176: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x2; +op3val:0x7e00; valaddr_reg:x2; val_offset:24426*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24426*FLEN/8, x3, x1, x4) + +inst_8177: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x2; +op3val:0xfe00; valaddr_reg:x2; val_offset:24429*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24429*FLEN/8, x3, x1, x4) + +inst_8178: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x2; +op3val:0x7e01; valaddr_reg:x2; val_offset:24432*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24432*FLEN/8, x3, x1, x4) + +inst_8179: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x2; +op3val:0xfe55; valaddr_reg:x2; val_offset:24435*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24435*FLEN/8, x3, x1, x4) + +inst_8180: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x2; +op3val:0x7c01; valaddr_reg:x2; val_offset:24438*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24438*FLEN/8, x3, x1, x4) + +inst_8181: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x2; +op3val:0xfd55; valaddr_reg:x2; val_offset:24441*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24441*FLEN/8, x3, x1, x4) + +inst_8182: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x2; +op3val:0x3c00; valaddr_reg:x2; val_offset:24444*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24444*FLEN/8, x3, x1, x4) + +inst_8183: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x2; +op3val:0xbc00; valaddr_reg:x2; val_offset:24447*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24447*FLEN/8, x3, x1, x4) + +inst_8184: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x83fe; +op3val:0x0; valaddr_reg:x2; val_offset:24450*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24450*FLEN/8, x3, x1, x4) + +inst_8185: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x83fe; +op3val:0x8000; valaddr_reg:x2; val_offset:24453*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24453*FLEN/8, x3, x1, x4) + +inst_8186: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x83fe; +op3val:0x1; valaddr_reg:x2; val_offset:24456*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24456*FLEN/8, x3, x1, x4) + +inst_8187: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x83fe; +op3val:0x8001; valaddr_reg:x2; val_offset:24459*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24459*FLEN/8, x3, x1, x4) + +inst_8188: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x83fe; +op3val:0x2; valaddr_reg:x2; val_offset:24462*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24462*FLEN/8, x3, x1, x4) + +inst_8189: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x83fe; +op3val:0x83fe; valaddr_reg:x2; val_offset:24465*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24465*FLEN/8, x3, x1, x4) + +inst_8190: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x83fe; +op3val:0x3ff; valaddr_reg:x2; val_offset:24468*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24468*FLEN/8, x3, x1, x4) + +inst_8191: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x83fe; +op3val:0x83ff; valaddr_reg:x2; val_offset:24471*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24471*FLEN/8, x3, x1, x4) + +inst_8192: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x83fe; +op3val:0x400; valaddr_reg:x2; val_offset:24474*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24474*FLEN/8, x3, x1, x4) + +inst_8193: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x83fe; +op3val:0x8400; valaddr_reg:x2; val_offset:24477*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24477*FLEN/8, x3, x1, x4) + +inst_8194: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x83fe; +op3val:0x401; valaddr_reg:x2; val_offset:24480*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24480*FLEN/8, x3, x1, x4) + +inst_8195: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x83fe; +op3val:0x8455; valaddr_reg:x2; val_offset:24483*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24483*FLEN/8, x3, x1, x4) + +inst_8196: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x83fe; +op3val:0x7bff; valaddr_reg:x2; val_offset:24486*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24486*FLEN/8, x3, x1, x4) + +inst_8197: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x83fe; +op3val:0xfbff; valaddr_reg:x2; val_offset:24489*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24489*FLEN/8, x3, x1, x4) + +inst_8198: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x83fe; +op3val:0x7c00; valaddr_reg:x2; val_offset:24492*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24492*FLEN/8, x3, x1, x4) + +inst_8199: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x83fe; +op3val:0xfc00; valaddr_reg:x2; val_offset:24495*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24495*FLEN/8, x3, x1, x4) + +inst_8200: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x83fe; +op3val:0x7e00; valaddr_reg:x2; val_offset:24498*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24498*FLEN/8, x3, x1, x4) + +inst_8201: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x83fe; +op3val:0xfe00; valaddr_reg:x2; val_offset:24501*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24501*FLEN/8, x3, x1, x4) + +inst_8202: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x83fe; +op3val:0x7e01; valaddr_reg:x2; val_offset:24504*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24504*FLEN/8, x3, x1, x4) + +inst_8203: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x83fe; +op3val:0xfe55; valaddr_reg:x2; val_offset:24507*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24507*FLEN/8, x3, x1, x4) + +inst_8204: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x83fe; +op3val:0x7c01; valaddr_reg:x2; val_offset:24510*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24510*FLEN/8, x3, x1, x4) + +inst_8205: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x83fe; +op3val:0xfd55; valaddr_reg:x2; val_offset:24513*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24513*FLEN/8, x3, x1, x4) + +inst_8206: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x83fe; +op3val:0x3c00; valaddr_reg:x2; val_offset:24516*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24516*FLEN/8, x3, x1, x4) + +inst_8207: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x83fe; +op3val:0xbc00; valaddr_reg:x2; val_offset:24519*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24519*FLEN/8, x3, x1, x4) + +inst_8208: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x3ff; +op3val:0x0; valaddr_reg:x2; val_offset:24522*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24522*FLEN/8, x3, x1, x4) + +inst_8209: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x3ff; +op3val:0x8000; valaddr_reg:x2; val_offset:24525*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24525*FLEN/8, x3, x1, x4) + +inst_8210: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x3ff; +op3val:0x1; valaddr_reg:x2; val_offset:24528*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24528*FLEN/8, x3, x1, x4) + +inst_8211: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x3ff; +op3val:0x8001; valaddr_reg:x2; val_offset:24531*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24531*FLEN/8, x3, x1, x4) + +inst_8212: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x3ff; +op3val:0x2; valaddr_reg:x2; val_offset:24534*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24534*FLEN/8, x3, x1, x4) + +inst_8213: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x3ff; +op3val:0x83fe; valaddr_reg:x2; val_offset:24537*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24537*FLEN/8, x3, x1, x4) + +inst_8214: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x3ff; +op3val:0x3ff; valaddr_reg:x2; val_offset:24540*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24540*FLEN/8, x3, x1, x4) + +inst_8215: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x3ff; +op3val:0x83ff; valaddr_reg:x2; val_offset:24543*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24543*FLEN/8, x3, x1, x4) + +inst_8216: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x3ff; +op3val:0x400; valaddr_reg:x2; val_offset:24546*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24546*FLEN/8, x3, x1, x4) + +inst_8217: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x3ff; +op3val:0x8400; valaddr_reg:x2; val_offset:24549*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24549*FLEN/8, x3, x1, x4) + +inst_8218: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x3ff; +op3val:0x401; valaddr_reg:x2; val_offset:24552*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24552*FLEN/8, x3, x1, x4) + +inst_8219: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x3ff; +op3val:0x8455; valaddr_reg:x2; val_offset:24555*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24555*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_65) + +inst_8220: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x3ff; +op3val:0x7bff; valaddr_reg:x2; val_offset:24558*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24558*FLEN/8, x3, x1, x4) + +inst_8221: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x3ff; +op3val:0xfbff; valaddr_reg:x2; val_offset:24561*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24561*FLEN/8, x3, x1, x4) + +inst_8222: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x3ff; +op3val:0x7c00; valaddr_reg:x2; val_offset:24564*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24564*FLEN/8, x3, x1, x4) + +inst_8223: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x3ff; +op3val:0xfc00; valaddr_reg:x2; val_offset:24567*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24567*FLEN/8, x3, x1, x4) + +inst_8224: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x3ff; +op3val:0x7e00; valaddr_reg:x2; val_offset:24570*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24570*FLEN/8, x3, x1, x4) + +inst_8225: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x3ff; +op3val:0xfe00; valaddr_reg:x2; val_offset:24573*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24573*FLEN/8, x3, x1, x4) + +inst_8226: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x3ff; +op3val:0x7e01; valaddr_reg:x2; val_offset:24576*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24576*FLEN/8, x3, x1, x4) + +inst_8227: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x3ff; +op3val:0xfe55; valaddr_reg:x2; val_offset:24579*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24579*FLEN/8, x3, x1, x4) + +inst_8228: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x3ff; +op3val:0x7c01; valaddr_reg:x2; val_offset:24582*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24582*FLEN/8, x3, x1, x4) + +inst_8229: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x3ff; +op3val:0xfd55; valaddr_reg:x2; val_offset:24585*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24585*FLEN/8, x3, x1, x4) + +inst_8230: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x3ff; +op3val:0x3c00; valaddr_reg:x2; val_offset:24588*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24588*FLEN/8, x3, x1, x4) + +inst_8231: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x3ff; +op3val:0xbc00; valaddr_reg:x2; val_offset:24591*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24591*FLEN/8, x3, x1, x4) + +inst_8232: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x83ff; +op3val:0x0; valaddr_reg:x2; val_offset:24594*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24594*FLEN/8, x3, x1, x4) + +inst_8233: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x83ff; +op3val:0x8000; valaddr_reg:x2; val_offset:24597*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24597*FLEN/8, x3, x1, x4) + +inst_8234: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x83ff; +op3val:0x1; valaddr_reg:x2; val_offset:24600*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24600*FLEN/8, x3, x1, x4) + +inst_8235: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x83ff; +op3val:0x8001; valaddr_reg:x2; val_offset:24603*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24603*FLEN/8, x3, x1, x4) + +inst_8236: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x83ff; +op3val:0x2; valaddr_reg:x2; val_offset:24606*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24606*FLEN/8, x3, x1, x4) + +inst_8237: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x83ff; +op3val:0x83fe; valaddr_reg:x2; val_offset:24609*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24609*FLEN/8, x3, x1, x4) + +inst_8238: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x83ff; +op3val:0x3ff; valaddr_reg:x2; val_offset:24612*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24612*FLEN/8, x3, x1, x4) + +inst_8239: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x83ff; +op3val:0x83ff; valaddr_reg:x2; val_offset:24615*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24615*FLEN/8, x3, x1, x4) + +inst_8240: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x83ff; +op3val:0x400; valaddr_reg:x2; val_offset:24618*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24618*FLEN/8, x3, x1, x4) + +inst_8241: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x83ff; +op3val:0x8400; valaddr_reg:x2; val_offset:24621*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24621*FLEN/8, x3, x1, x4) + +inst_8242: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x83ff; +op3val:0x401; valaddr_reg:x2; val_offset:24624*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24624*FLEN/8, x3, x1, x4) + +inst_8243: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x83ff; +op3val:0x8455; valaddr_reg:x2; val_offset:24627*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24627*FLEN/8, x3, x1, x4) + +inst_8244: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x83ff; +op3val:0x7bff; valaddr_reg:x2; val_offset:24630*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24630*FLEN/8, x3, x1, x4) + +inst_8245: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x83ff; +op3val:0xfbff; valaddr_reg:x2; val_offset:24633*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24633*FLEN/8, x3, x1, x4) + +inst_8246: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x83ff; +op3val:0x7c00; valaddr_reg:x2; val_offset:24636*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24636*FLEN/8, x3, x1, x4) + +inst_8247: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x83ff; +op3val:0xfc00; valaddr_reg:x2; val_offset:24639*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24639*FLEN/8, x3, x1, x4) + +inst_8248: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x83ff; +op3val:0x7e00; valaddr_reg:x2; val_offset:24642*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24642*FLEN/8, x3, x1, x4) + +inst_8249: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x83ff; +op3val:0xfe00; valaddr_reg:x2; val_offset:24645*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24645*FLEN/8, x3, x1, x4) + +inst_8250: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x83ff; +op3val:0x7e01; valaddr_reg:x2; val_offset:24648*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24648*FLEN/8, x3, x1, x4) + +inst_8251: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x83ff; +op3val:0xfe55; valaddr_reg:x2; val_offset:24651*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24651*FLEN/8, x3, x1, x4) + +inst_8252: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x83ff; +op3val:0x7c01; valaddr_reg:x2; val_offset:24654*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24654*FLEN/8, x3, x1, x4) + +inst_8253: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x83ff; +op3val:0xfd55; valaddr_reg:x2; val_offset:24657*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24657*FLEN/8, x3, x1, x4) + +inst_8254: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x83ff; +op3val:0x3c00; valaddr_reg:x2; val_offset:24660*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24660*FLEN/8, x3, x1, x4) + +inst_8255: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x83ff; +op3val:0xbc00; valaddr_reg:x2; val_offset:24663*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24663*FLEN/8, x3, x1, x4) + +inst_8256: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x400; +op3val:0x0; valaddr_reg:x2; val_offset:24666*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24666*FLEN/8, x3, x1, x4) + +inst_8257: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x400; +op3val:0x8000; valaddr_reg:x2; val_offset:24669*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24669*FLEN/8, x3, x1, x4) + +inst_8258: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x400; +op3val:0x1; valaddr_reg:x2; val_offset:24672*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24672*FLEN/8, x3, x1, x4) + +inst_8259: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x400; +op3val:0x8001; valaddr_reg:x2; val_offset:24675*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24675*FLEN/8, x3, x1, x4) + +inst_8260: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x400; +op3val:0x2; valaddr_reg:x2; val_offset:24678*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24678*FLEN/8, x3, x1, x4) + +inst_8261: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x400; +op3val:0x83fe; valaddr_reg:x2; val_offset:24681*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24681*FLEN/8, x3, x1, x4) + +inst_8262: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x400; +op3val:0x3ff; valaddr_reg:x2; val_offset:24684*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24684*FLEN/8, x3, x1, x4) + +inst_8263: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x400; +op3val:0x83ff; valaddr_reg:x2; val_offset:24687*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24687*FLEN/8, x3, x1, x4) + +inst_8264: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x400; +op3val:0x400; valaddr_reg:x2; val_offset:24690*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24690*FLEN/8, x3, x1, x4) + +inst_8265: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x400; +op3val:0x8400; valaddr_reg:x2; val_offset:24693*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24693*FLEN/8, x3, x1, x4) + +inst_8266: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x400; +op3val:0x401; valaddr_reg:x2; val_offset:24696*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24696*FLEN/8, x3, x1, x4) + +inst_8267: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x400; +op3val:0x8455; valaddr_reg:x2; val_offset:24699*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24699*FLEN/8, x3, x1, x4) + +inst_8268: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x400; +op3val:0x7bff; valaddr_reg:x2; val_offset:24702*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24702*FLEN/8, x3, x1, x4) + +inst_8269: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x400; +op3val:0xfbff; valaddr_reg:x2; val_offset:24705*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24705*FLEN/8, x3, x1, x4) + +inst_8270: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x400; +op3val:0x7c00; valaddr_reg:x2; val_offset:24708*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24708*FLEN/8, x3, x1, x4) + +inst_8271: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x400; +op3val:0xfc00; valaddr_reg:x2; val_offset:24711*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24711*FLEN/8, x3, x1, x4) + +inst_8272: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x400; +op3val:0x7e00; valaddr_reg:x2; val_offset:24714*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24714*FLEN/8, x3, x1, x4) + +inst_8273: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x400; +op3val:0xfe00; valaddr_reg:x2; val_offset:24717*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24717*FLEN/8, x3, x1, x4) + +inst_8274: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x400; +op3val:0x7e01; valaddr_reg:x2; val_offset:24720*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24720*FLEN/8, x3, x1, x4) + +inst_8275: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x400; +op3val:0xfe55; valaddr_reg:x2; val_offset:24723*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24723*FLEN/8, x3, x1, x4) + +inst_8276: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x400; +op3val:0x7c01; valaddr_reg:x2; val_offset:24726*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24726*FLEN/8, x3, x1, x4) + +inst_8277: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x400; +op3val:0xfd55; valaddr_reg:x2; val_offset:24729*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24729*FLEN/8, x3, x1, x4) + +inst_8278: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x400; +op3val:0x3c00; valaddr_reg:x2; val_offset:24732*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24732*FLEN/8, x3, x1, x4) + +inst_8279: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x400; +op3val:0xbc00; valaddr_reg:x2; val_offset:24735*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24735*FLEN/8, x3, x1, x4) + +inst_8280: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8400; +op3val:0x0; valaddr_reg:x2; val_offset:24738*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24738*FLEN/8, x3, x1, x4) + +inst_8281: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8400; +op3val:0x8000; valaddr_reg:x2; val_offset:24741*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24741*FLEN/8, x3, x1, x4) + +inst_8282: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8400; +op3val:0x1; valaddr_reg:x2; val_offset:24744*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24744*FLEN/8, x3, x1, x4) + +inst_8283: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8400; +op3val:0x8001; valaddr_reg:x2; val_offset:24747*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24747*FLEN/8, x3, x1, x4) + +inst_8284: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8400; +op3val:0x2; valaddr_reg:x2; val_offset:24750*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24750*FLEN/8, x3, x1, x4) + +inst_8285: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8400; +op3val:0x83fe; valaddr_reg:x2; val_offset:24753*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24753*FLEN/8, x3, x1, x4) + +inst_8286: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8400; +op3val:0x3ff; valaddr_reg:x2; val_offset:24756*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24756*FLEN/8, x3, x1, x4) + +inst_8287: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8400; +op3val:0x83ff; valaddr_reg:x2; val_offset:24759*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24759*FLEN/8, x3, x1, x4) + +inst_8288: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8400; +op3val:0x400; valaddr_reg:x2; val_offset:24762*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24762*FLEN/8, x3, x1, x4) + +inst_8289: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8400; +op3val:0x8400; valaddr_reg:x2; val_offset:24765*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24765*FLEN/8, x3, x1, x4) + +inst_8290: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8400; +op3val:0x401; valaddr_reg:x2; val_offset:24768*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24768*FLEN/8, x3, x1, x4) + +inst_8291: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8400; +op3val:0x8455; valaddr_reg:x2; val_offset:24771*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24771*FLEN/8, x3, x1, x4) + +inst_8292: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8400; +op3val:0x7bff; valaddr_reg:x2; val_offset:24774*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24774*FLEN/8, x3, x1, x4) + +inst_8293: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8400; +op3val:0xfbff; valaddr_reg:x2; val_offset:24777*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24777*FLEN/8, x3, x1, x4) + +inst_8294: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8400; +op3val:0x7c00; valaddr_reg:x2; val_offset:24780*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24780*FLEN/8, x3, x1, x4) + +inst_8295: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8400; +op3val:0xfc00; valaddr_reg:x2; val_offset:24783*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24783*FLEN/8, x3, x1, x4) + +inst_8296: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8400; +op3val:0x7e00; valaddr_reg:x2; val_offset:24786*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24786*FLEN/8, x3, x1, x4) + +inst_8297: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8400; +op3val:0xfe00; valaddr_reg:x2; val_offset:24789*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24789*FLEN/8, x3, x1, x4) + +inst_8298: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8400; +op3val:0x7e01; valaddr_reg:x2; val_offset:24792*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24792*FLEN/8, x3, x1, x4) + +inst_8299: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8400; +op3val:0xfe55; valaddr_reg:x2; val_offset:24795*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24795*FLEN/8, x3, x1, x4) + +inst_8300: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8400; +op3val:0x7c01; valaddr_reg:x2; val_offset:24798*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24798*FLEN/8, x3, x1, x4) + +inst_8301: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8400; +op3val:0xfd55; valaddr_reg:x2; val_offset:24801*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24801*FLEN/8, x3, x1, x4) + +inst_8302: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8400; +op3val:0x3c00; valaddr_reg:x2; val_offset:24804*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24804*FLEN/8, x3, x1, x4) + +inst_8303: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8400; +op3val:0xbc00; valaddr_reg:x2; val_offset:24807*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24807*FLEN/8, x3, x1, x4) + +inst_8304: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x401; +op3val:0x0; valaddr_reg:x2; val_offset:24810*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24810*FLEN/8, x3, x1, x4) + +inst_8305: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x401; +op3val:0x8000; valaddr_reg:x2; val_offset:24813*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24813*FLEN/8, x3, x1, x4) + +inst_8306: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x401; +op3val:0x1; valaddr_reg:x2; val_offset:24816*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24816*FLEN/8, x3, x1, x4) + +inst_8307: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x401; +op3val:0x8001; valaddr_reg:x2; val_offset:24819*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24819*FLEN/8, x3, x1, x4) + +inst_8308: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x401; +op3val:0x2; valaddr_reg:x2; val_offset:24822*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24822*FLEN/8, x3, x1, x4) + +inst_8309: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x401; +op3val:0x83fe; valaddr_reg:x2; val_offset:24825*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24825*FLEN/8, x3, x1, x4) + +inst_8310: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x401; +op3val:0x3ff; valaddr_reg:x2; val_offset:24828*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24828*FLEN/8, x3, x1, x4) + +inst_8311: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x401; +op3val:0x83ff; valaddr_reg:x2; val_offset:24831*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24831*FLEN/8, x3, x1, x4) + +inst_8312: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x401; +op3val:0x400; valaddr_reg:x2; val_offset:24834*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24834*FLEN/8, x3, x1, x4) + +inst_8313: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x401; +op3val:0x8400; valaddr_reg:x2; val_offset:24837*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24837*FLEN/8, x3, x1, x4) + +inst_8314: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x401; +op3val:0x401; valaddr_reg:x2; val_offset:24840*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24840*FLEN/8, x3, x1, x4) + +inst_8315: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x401; +op3val:0x8455; valaddr_reg:x2; val_offset:24843*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24843*FLEN/8, x3, x1, x4) + +inst_8316: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x401; +op3val:0x7bff; valaddr_reg:x2; val_offset:24846*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24846*FLEN/8, x3, x1, x4) + +inst_8317: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x401; +op3val:0xfbff; valaddr_reg:x2; val_offset:24849*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24849*FLEN/8, x3, x1, x4) + +inst_8318: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x401; +op3val:0x7c00; valaddr_reg:x2; val_offset:24852*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24852*FLEN/8, x3, x1, x4) + +inst_8319: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x401; +op3val:0xfc00; valaddr_reg:x2; val_offset:24855*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24855*FLEN/8, x3, x1, x4) + +inst_8320: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x401; +op3val:0x7e00; valaddr_reg:x2; val_offset:24858*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24858*FLEN/8, x3, x1, x4) + +inst_8321: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x401; +op3val:0xfe00; valaddr_reg:x2; val_offset:24861*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24861*FLEN/8, x3, x1, x4) + +inst_8322: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x401; +op3val:0x7e01; valaddr_reg:x2; val_offset:24864*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24864*FLEN/8, x3, x1, x4) + +inst_8323: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x401; +op3val:0xfe55; valaddr_reg:x2; val_offset:24867*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24867*FLEN/8, x3, x1, x4) + +inst_8324: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x401; +op3val:0x7c01; valaddr_reg:x2; val_offset:24870*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24870*FLEN/8, x3, x1, x4) + +inst_8325: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x401; +op3val:0xfd55; valaddr_reg:x2; val_offset:24873*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24873*FLEN/8, x3, x1, x4) + +inst_8326: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x401; +op3val:0x3c00; valaddr_reg:x2; val_offset:24876*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24876*FLEN/8, x3, x1, x4) + +inst_8327: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x401; +op3val:0xbc00; valaddr_reg:x2; val_offset:24879*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24879*FLEN/8, x3, x1, x4) + +inst_8328: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8455; +op3val:0x0; valaddr_reg:x2; val_offset:24882*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24882*FLEN/8, x3, x1, x4) + +inst_8329: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8455; +op3val:0x8000; valaddr_reg:x2; val_offset:24885*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24885*FLEN/8, x3, x1, x4) + +inst_8330: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8455; +op3val:0x1; valaddr_reg:x2; val_offset:24888*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24888*FLEN/8, x3, x1, x4) + +inst_8331: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8455; +op3val:0x8001; valaddr_reg:x2; val_offset:24891*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24891*FLEN/8, x3, x1, x4) + +inst_8332: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8455; +op3val:0x2; valaddr_reg:x2; val_offset:24894*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24894*FLEN/8, x3, x1, x4) + +inst_8333: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8455; +op3val:0x83fe; valaddr_reg:x2; val_offset:24897*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24897*FLEN/8, x3, x1, x4) + +inst_8334: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8455; +op3val:0x3ff; valaddr_reg:x2; val_offset:24900*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24900*FLEN/8, x3, x1, x4) + +inst_8335: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8455; +op3val:0x83ff; valaddr_reg:x2; val_offset:24903*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24903*FLEN/8, x3, x1, x4) + +inst_8336: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8455; +op3val:0x400; valaddr_reg:x2; val_offset:24906*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24906*FLEN/8, x3, x1, x4) + +inst_8337: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8455; +op3val:0x8400; valaddr_reg:x2; val_offset:24909*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24909*FLEN/8, x3, x1, x4) + +inst_8338: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8455; +op3val:0x401; valaddr_reg:x2; val_offset:24912*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24912*FLEN/8, x3, x1, x4) + +inst_8339: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8455; +op3val:0x8455; valaddr_reg:x2; val_offset:24915*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24915*FLEN/8, x3, x1, x4) + +inst_8340: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8455; +op3val:0x7bff; valaddr_reg:x2; val_offset:24918*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24918*FLEN/8, x3, x1, x4) + +inst_8341: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8455; +op3val:0xfbff; valaddr_reg:x2; val_offset:24921*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24921*FLEN/8, x3, x1, x4) + +inst_8342: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8455; +op3val:0x7c00; valaddr_reg:x2; val_offset:24924*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24924*FLEN/8, x3, x1, x4) + +inst_8343: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8455; +op3val:0xfc00; valaddr_reg:x2; val_offset:24927*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24927*FLEN/8, x3, x1, x4) + +inst_8344: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8455; +op3val:0x7e00; valaddr_reg:x2; val_offset:24930*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24930*FLEN/8, x3, x1, x4) + +inst_8345: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8455; +op3val:0xfe00; valaddr_reg:x2; val_offset:24933*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24933*FLEN/8, x3, x1, x4) + +inst_8346: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8455; +op3val:0x7e01; valaddr_reg:x2; val_offset:24936*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24936*FLEN/8, x3, x1, x4) + +inst_8347: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8455; +op3val:0xfe55; valaddr_reg:x2; val_offset:24939*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24939*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_66) + +inst_8348: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8455; +op3val:0x7c01; valaddr_reg:x2; val_offset:24942*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24942*FLEN/8, x3, x1, x4) + +inst_8349: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8455; +op3val:0xfd55; valaddr_reg:x2; val_offset:24945*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24945*FLEN/8, x3, x1, x4) + +inst_8350: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8455; +op3val:0x3c00; valaddr_reg:x2; val_offset:24948*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24948*FLEN/8, x3, x1, x4) + +inst_8351: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x8455; +op3val:0xbc00; valaddr_reg:x2; val_offset:24951*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24951*FLEN/8, x3, x1, x4) + +inst_8352: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7bff; +op3val:0x0; valaddr_reg:x2; val_offset:24954*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24954*FLEN/8, x3, x1, x4) + +inst_8353: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7bff; +op3val:0x8000; valaddr_reg:x2; val_offset:24957*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24957*FLEN/8, x3, x1, x4) + +inst_8354: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7bff; +op3val:0x1; valaddr_reg:x2; val_offset:24960*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24960*FLEN/8, x3, x1, x4) + +inst_8355: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7bff; +op3val:0x8001; valaddr_reg:x2; val_offset:24963*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24963*FLEN/8, x3, x1, x4) + +inst_8356: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7bff; +op3val:0x2; valaddr_reg:x2; val_offset:24966*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24966*FLEN/8, x3, x1, x4) + +inst_8357: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7bff; +op3val:0x83fe; valaddr_reg:x2; val_offset:24969*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24969*FLEN/8, x3, x1, x4) + +inst_8358: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7bff; +op3val:0x3ff; valaddr_reg:x2; val_offset:24972*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24972*FLEN/8, x3, x1, x4) + +inst_8359: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7bff; +op3val:0x83ff; valaddr_reg:x2; val_offset:24975*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24975*FLEN/8, x3, x1, x4) + +inst_8360: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7bff; +op3val:0x400; valaddr_reg:x2; val_offset:24978*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24978*FLEN/8, x3, x1, x4) + +inst_8361: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7bff; +op3val:0x8400; valaddr_reg:x2; val_offset:24981*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24981*FLEN/8, x3, x1, x4) + +inst_8362: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7bff; +op3val:0x401; valaddr_reg:x2; val_offset:24984*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24984*FLEN/8, x3, x1, x4) + +inst_8363: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7bff; +op3val:0x8455; valaddr_reg:x2; val_offset:24987*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24987*FLEN/8, x3, x1, x4) + +inst_8364: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7bff; +op3val:0x7bff; valaddr_reg:x2; val_offset:24990*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24990*FLEN/8, x3, x1, x4) + +inst_8365: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7bff; +op3val:0xfbff; valaddr_reg:x2; val_offset:24993*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24993*FLEN/8, x3, x1, x4) + +inst_8366: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7bff; +op3val:0x7c00; valaddr_reg:x2; val_offset:24996*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24996*FLEN/8, x3, x1, x4) + +inst_8367: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7bff; +op3val:0xfc00; valaddr_reg:x2; val_offset:24999*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24999*FLEN/8, x3, x1, x4) + +inst_8368: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7bff; +op3val:0x7e00; valaddr_reg:x2; val_offset:25002*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25002*FLEN/8, x3, x1, x4) + +inst_8369: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7bff; +op3val:0xfe00; valaddr_reg:x2; val_offset:25005*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25005*FLEN/8, x3, x1, x4) + +inst_8370: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7bff; +op3val:0x7e01; valaddr_reg:x2; val_offset:25008*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25008*FLEN/8, x3, x1, x4) + +inst_8371: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7bff; +op3val:0xfe55; valaddr_reg:x2; val_offset:25011*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25011*FLEN/8, x3, x1, x4) + +inst_8372: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7bff; +op3val:0x7c01; valaddr_reg:x2; val_offset:25014*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25014*FLEN/8, x3, x1, x4) + +inst_8373: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7bff; +op3val:0xfd55; valaddr_reg:x2; val_offset:25017*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25017*FLEN/8, x3, x1, x4) + +inst_8374: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7bff; +op3val:0x3c00; valaddr_reg:x2; val_offset:25020*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25020*FLEN/8, x3, x1, x4) + +inst_8375: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7bff; +op3val:0xbc00; valaddr_reg:x2; val_offset:25023*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25023*FLEN/8, x3, x1, x4) + +inst_8376: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfbff; +op3val:0x0; valaddr_reg:x2; val_offset:25026*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25026*FLEN/8, x3, x1, x4) + +inst_8377: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfbff; +op3val:0x8000; valaddr_reg:x2; val_offset:25029*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25029*FLEN/8, x3, x1, x4) + +inst_8378: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfbff; +op3val:0x1; valaddr_reg:x2; val_offset:25032*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25032*FLEN/8, x3, x1, x4) + +inst_8379: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfbff; +op3val:0x8001; valaddr_reg:x2; val_offset:25035*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25035*FLEN/8, x3, x1, x4) + +inst_8380: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfbff; +op3val:0x2; valaddr_reg:x2; val_offset:25038*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25038*FLEN/8, x3, x1, x4) + +inst_8381: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfbff; +op3val:0x83fe; valaddr_reg:x2; val_offset:25041*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25041*FLEN/8, x3, x1, x4) + +inst_8382: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfbff; +op3val:0x3ff; valaddr_reg:x2; val_offset:25044*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25044*FLEN/8, x3, x1, x4) + +inst_8383: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfbff; +op3val:0x83ff; valaddr_reg:x2; val_offset:25047*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25047*FLEN/8, x3, x1, x4) + +inst_8384: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfbff; +op3val:0x400; valaddr_reg:x2; val_offset:25050*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25050*FLEN/8, x3, x1, x4) + +inst_8385: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfbff; +op3val:0x8400; valaddr_reg:x2; val_offset:25053*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25053*FLEN/8, x3, x1, x4) + +inst_8386: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfbff; +op3val:0x401; valaddr_reg:x2; val_offset:25056*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25056*FLEN/8, x3, x1, x4) + +inst_8387: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfbff; +op3val:0x8455; valaddr_reg:x2; val_offset:25059*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25059*FLEN/8, x3, x1, x4) + +inst_8388: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfbff; +op3val:0x7bff; valaddr_reg:x2; val_offset:25062*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25062*FLEN/8, x3, x1, x4) + +inst_8389: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfbff; +op3val:0xfbff; valaddr_reg:x2; val_offset:25065*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25065*FLEN/8, x3, x1, x4) + +inst_8390: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfbff; +op3val:0x7c00; valaddr_reg:x2; val_offset:25068*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25068*FLEN/8, x3, x1, x4) + +inst_8391: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfbff; +op3val:0xfc00; valaddr_reg:x2; val_offset:25071*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25071*FLEN/8, x3, x1, x4) + +inst_8392: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfbff; +op3val:0x7e00; valaddr_reg:x2; val_offset:25074*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25074*FLEN/8, x3, x1, x4) + +inst_8393: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfbff; +op3val:0xfe00; valaddr_reg:x2; val_offset:25077*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25077*FLEN/8, x3, x1, x4) + +inst_8394: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfbff; +op3val:0x7e01; valaddr_reg:x2; val_offset:25080*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25080*FLEN/8, x3, x1, x4) + +inst_8395: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfbff; +op3val:0xfe55; valaddr_reg:x2; val_offset:25083*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25083*FLEN/8, x3, x1, x4) + +inst_8396: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfbff; +op3val:0x7c01; valaddr_reg:x2; val_offset:25086*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25086*FLEN/8, x3, x1, x4) + +inst_8397: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfbff; +op3val:0xfd55; valaddr_reg:x2; val_offset:25089*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25089*FLEN/8, x3, x1, x4) + +inst_8398: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfbff; +op3val:0x3c00; valaddr_reg:x2; val_offset:25092*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25092*FLEN/8, x3, x1, x4) + +inst_8399: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfbff; +op3val:0xbc00; valaddr_reg:x2; val_offset:25095*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25095*FLEN/8, x3, x1, x4) + +inst_8400: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7c00; +op3val:0x0; valaddr_reg:x2; val_offset:25098*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25098*FLEN/8, x3, x1, x4) + +inst_8401: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7c00; +op3val:0x8000; valaddr_reg:x2; val_offset:25101*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25101*FLEN/8, x3, x1, x4) + +inst_8402: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7c00; +op3val:0x1; valaddr_reg:x2; val_offset:25104*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25104*FLEN/8, x3, x1, x4) + +inst_8403: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7c00; +op3val:0x8001; valaddr_reg:x2; val_offset:25107*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25107*FLEN/8, x3, x1, x4) + +inst_8404: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7c00; +op3val:0x2; valaddr_reg:x2; val_offset:25110*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25110*FLEN/8, x3, x1, x4) + +inst_8405: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7c00; +op3val:0x83fe; valaddr_reg:x2; val_offset:25113*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25113*FLEN/8, x3, x1, x4) + +inst_8406: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7c00; +op3val:0x3ff; valaddr_reg:x2; val_offset:25116*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25116*FLEN/8, x3, x1, x4) + +inst_8407: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7c00; +op3val:0x83ff; valaddr_reg:x2; val_offset:25119*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25119*FLEN/8, x3, x1, x4) + +inst_8408: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7c00; +op3val:0x400; valaddr_reg:x2; val_offset:25122*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25122*FLEN/8, x3, x1, x4) + +inst_8409: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7c00; +op3val:0x8400; valaddr_reg:x2; val_offset:25125*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25125*FLEN/8, x3, x1, x4) + +inst_8410: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7c00; +op3val:0x401; valaddr_reg:x2; val_offset:25128*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25128*FLEN/8, x3, x1, x4) + +inst_8411: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7c00; +op3val:0x8455; valaddr_reg:x2; val_offset:25131*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25131*FLEN/8, x3, x1, x4) + +inst_8412: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7c00; +op3val:0x7bff; valaddr_reg:x2; val_offset:25134*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25134*FLEN/8, x3, x1, x4) + +inst_8413: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7c00; +op3val:0xfbff; valaddr_reg:x2; val_offset:25137*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25137*FLEN/8, x3, x1, x4) + +inst_8414: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7c00; +op3val:0x7c00; valaddr_reg:x2; val_offset:25140*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25140*FLEN/8, x3, x1, x4) + +inst_8415: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7c00; +op3val:0xfc00; valaddr_reg:x2; val_offset:25143*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25143*FLEN/8, x3, x1, x4) + +inst_8416: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7c00; +op3val:0x7e00; valaddr_reg:x2; val_offset:25146*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25146*FLEN/8, x3, x1, x4) + +inst_8417: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7c00; +op3val:0xfe00; valaddr_reg:x2; val_offset:25149*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25149*FLEN/8, x3, x1, x4) + +inst_8418: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7c00; +op3val:0x7e01; valaddr_reg:x2; val_offset:25152*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25152*FLEN/8, x3, x1, x4) + +inst_8419: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7c00; +op3val:0xfe55; valaddr_reg:x2; val_offset:25155*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25155*FLEN/8, x3, x1, x4) + +inst_8420: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7c00; +op3val:0x7c01; valaddr_reg:x2; val_offset:25158*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25158*FLEN/8, x3, x1, x4) + +inst_8421: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7c00; +op3val:0xfd55; valaddr_reg:x2; val_offset:25161*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25161*FLEN/8, x3, x1, x4) + +inst_8422: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7c00; +op3val:0x3c00; valaddr_reg:x2; val_offset:25164*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25164*FLEN/8, x3, x1, x4) + +inst_8423: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7c00; +op3val:0xbc00; valaddr_reg:x2; val_offset:25167*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25167*FLEN/8, x3, x1, x4) + +inst_8424: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfc00; +op3val:0x0; valaddr_reg:x2; val_offset:25170*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25170*FLEN/8, x3, x1, x4) + +inst_8425: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfc00; +op3val:0x8000; valaddr_reg:x2; val_offset:25173*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25173*FLEN/8, x3, x1, x4) + +inst_8426: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfc00; +op3val:0x1; valaddr_reg:x2; val_offset:25176*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25176*FLEN/8, x3, x1, x4) + +inst_8427: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfc00; +op3val:0x8001; valaddr_reg:x2; val_offset:25179*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25179*FLEN/8, x3, x1, x4) + +inst_8428: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfc00; +op3val:0x2; valaddr_reg:x2; val_offset:25182*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25182*FLEN/8, x3, x1, x4) + +inst_8429: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfc00; +op3val:0x83fe; valaddr_reg:x2; val_offset:25185*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25185*FLEN/8, x3, x1, x4) + +inst_8430: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfc00; +op3val:0x3ff; valaddr_reg:x2; val_offset:25188*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25188*FLEN/8, x3, x1, x4) + +inst_8431: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfc00; +op3val:0x83ff; valaddr_reg:x2; val_offset:25191*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25191*FLEN/8, x3, x1, x4) + +inst_8432: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfc00; +op3val:0x400; valaddr_reg:x2; val_offset:25194*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25194*FLEN/8, x3, x1, x4) + +inst_8433: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfc00; +op3val:0x8400; valaddr_reg:x2; val_offset:25197*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25197*FLEN/8, x3, x1, x4) + +inst_8434: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfc00; +op3val:0x401; valaddr_reg:x2; val_offset:25200*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25200*FLEN/8, x3, x1, x4) + +inst_8435: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfc00; +op3val:0x8455; valaddr_reg:x2; val_offset:25203*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25203*FLEN/8, x3, x1, x4) + +inst_8436: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfc00; +op3val:0x7bff; valaddr_reg:x2; val_offset:25206*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25206*FLEN/8, x3, x1, x4) + +inst_8437: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfc00; +op3val:0xfbff; valaddr_reg:x2; val_offset:25209*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25209*FLEN/8, x3, x1, x4) + +inst_8438: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfc00; +op3val:0x7c00; valaddr_reg:x2; val_offset:25212*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25212*FLEN/8, x3, x1, x4) + +inst_8439: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfc00; +op3val:0xfc00; valaddr_reg:x2; val_offset:25215*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25215*FLEN/8, x3, x1, x4) + +inst_8440: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfc00; +op3val:0x7e00; valaddr_reg:x2; val_offset:25218*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25218*FLEN/8, x3, x1, x4) + +inst_8441: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfc00; +op3val:0xfe00; valaddr_reg:x2; val_offset:25221*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25221*FLEN/8, x3, x1, x4) + +inst_8442: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfc00; +op3val:0x7e01; valaddr_reg:x2; val_offset:25224*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25224*FLEN/8, x3, x1, x4) + +inst_8443: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfc00; +op3val:0xfe55; valaddr_reg:x2; val_offset:25227*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25227*FLEN/8, x3, x1, x4) + +inst_8444: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfc00; +op3val:0x7c01; valaddr_reg:x2; val_offset:25230*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25230*FLEN/8, x3, x1, x4) + +inst_8445: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfc00; +op3val:0xfd55; valaddr_reg:x2; val_offset:25233*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25233*FLEN/8, x3, x1, x4) + +inst_8446: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfc00; +op3val:0x3c00; valaddr_reg:x2; val_offset:25236*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25236*FLEN/8, x3, x1, x4) + +inst_8447: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfc00; +op3val:0xbc00; valaddr_reg:x2; val_offset:25239*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25239*FLEN/8, x3, x1, x4) + +inst_8448: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7e00; +op3val:0x0; valaddr_reg:x2; val_offset:25242*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25242*FLEN/8, x3, x1, x4) + +inst_8449: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7e00; +op3val:0x8000; valaddr_reg:x2; val_offset:25245*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25245*FLEN/8, x3, x1, x4) + +inst_8450: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7e00; +op3val:0x1; valaddr_reg:x2; val_offset:25248*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25248*FLEN/8, x3, x1, x4) + +inst_8451: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7e00; +op3val:0x8001; valaddr_reg:x2; val_offset:25251*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25251*FLEN/8, x3, x1, x4) + +inst_8452: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7e00; +op3val:0x2; valaddr_reg:x2; val_offset:25254*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25254*FLEN/8, x3, x1, x4) + +inst_8453: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7e00; +op3val:0x83fe; valaddr_reg:x2; val_offset:25257*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25257*FLEN/8, x3, x1, x4) + +inst_8454: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7e00; +op3val:0x3ff; valaddr_reg:x2; val_offset:25260*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25260*FLEN/8, x3, x1, x4) + +inst_8455: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7e00; +op3val:0x83ff; valaddr_reg:x2; val_offset:25263*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25263*FLEN/8, x3, x1, x4) + +inst_8456: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7e00; +op3val:0x400; valaddr_reg:x2; val_offset:25266*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25266*FLEN/8, x3, x1, x4) + +inst_8457: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7e00; +op3val:0x8400; valaddr_reg:x2; val_offset:25269*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25269*FLEN/8, x3, x1, x4) + +inst_8458: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7e00; +op3val:0x401; valaddr_reg:x2; val_offset:25272*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25272*FLEN/8, x3, x1, x4) + +inst_8459: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7e00; +op3val:0x8455; valaddr_reg:x2; val_offset:25275*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25275*FLEN/8, x3, x1, x4) + +inst_8460: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7e00; +op3val:0x7bff; valaddr_reg:x2; val_offset:25278*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25278*FLEN/8, x3, x1, x4) + +inst_8461: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7e00; +op3val:0xfbff; valaddr_reg:x2; val_offset:25281*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25281*FLEN/8, x3, x1, x4) + +inst_8462: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7e00; +op3val:0x7c00; valaddr_reg:x2; val_offset:25284*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25284*FLEN/8, x3, x1, x4) + +inst_8463: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7e00; +op3val:0xfc00; valaddr_reg:x2; val_offset:25287*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25287*FLEN/8, x3, x1, x4) + +inst_8464: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7e00; +op3val:0x7e00; valaddr_reg:x2; val_offset:25290*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25290*FLEN/8, x3, x1, x4) + +inst_8465: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7e00; +op3val:0xfe00; valaddr_reg:x2; val_offset:25293*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25293*FLEN/8, x3, x1, x4) + +inst_8466: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7e00; +op3val:0x7e01; valaddr_reg:x2; val_offset:25296*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25296*FLEN/8, x3, x1, x4) + +inst_8467: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7e00; +op3val:0xfe55; valaddr_reg:x2; val_offset:25299*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25299*FLEN/8, x3, x1, x4) + +inst_8468: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7e00; +op3val:0x7c01; valaddr_reg:x2; val_offset:25302*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25302*FLEN/8, x3, x1, x4) + +inst_8469: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7e00; +op3val:0xfd55; valaddr_reg:x2; val_offset:25305*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25305*FLEN/8, x3, x1, x4) + +inst_8470: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7e00; +op3val:0x3c00; valaddr_reg:x2; val_offset:25308*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25308*FLEN/8, x3, x1, x4) + +inst_8471: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7e00; +op3val:0xbc00; valaddr_reg:x2; val_offset:25311*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25311*FLEN/8, x3, x1, x4) + +inst_8472: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfe00; +op3val:0x0; valaddr_reg:x2; val_offset:25314*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25314*FLEN/8, x3, x1, x4) + +inst_8473: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfe00; +op3val:0x8000; valaddr_reg:x2; val_offset:25317*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25317*FLEN/8, x3, x1, x4) + +inst_8474: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfe00; +op3val:0x1; valaddr_reg:x2; val_offset:25320*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25320*FLEN/8, x3, x1, x4) + +inst_8475: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfe00; +op3val:0x8001; valaddr_reg:x2; val_offset:25323*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25323*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_67) + +inst_8476: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfe00; +op3val:0x2; valaddr_reg:x2; val_offset:25326*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25326*FLEN/8, x3, x1, x4) + +inst_8477: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfe00; +op3val:0x83fe; valaddr_reg:x2; val_offset:25329*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25329*FLEN/8, x3, x1, x4) + +inst_8478: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfe00; +op3val:0x3ff; valaddr_reg:x2; val_offset:25332*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25332*FLEN/8, x3, x1, x4) + +inst_8479: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfe00; +op3val:0x83ff; valaddr_reg:x2; val_offset:25335*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25335*FLEN/8, x3, x1, x4) + +inst_8480: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfe00; +op3val:0x400; valaddr_reg:x2; val_offset:25338*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25338*FLEN/8, x3, x1, x4) + +inst_8481: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfe00; +op3val:0x8400; valaddr_reg:x2; val_offset:25341*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25341*FLEN/8, x3, x1, x4) + +inst_8482: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfe00; +op3val:0x401; valaddr_reg:x2; val_offset:25344*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25344*FLEN/8, x3, x1, x4) + +inst_8483: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfe00; +op3val:0x8455; valaddr_reg:x2; val_offset:25347*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25347*FLEN/8, x3, x1, x4) + +inst_8484: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfe00; +op3val:0x7bff; valaddr_reg:x2; val_offset:25350*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25350*FLEN/8, x3, x1, x4) + +inst_8485: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfe00; +op3val:0xfbff; valaddr_reg:x2; val_offset:25353*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25353*FLEN/8, x3, x1, x4) + +inst_8486: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfe00; +op3val:0x7c00; valaddr_reg:x2; val_offset:25356*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25356*FLEN/8, x3, x1, x4) + +inst_8487: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfe00; +op3val:0xfc00; valaddr_reg:x2; val_offset:25359*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25359*FLEN/8, x3, x1, x4) + +inst_8488: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfe00; +op3val:0x7e00; valaddr_reg:x2; val_offset:25362*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25362*FLEN/8, x3, x1, x4) + +inst_8489: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfe00; +op3val:0xfe00; valaddr_reg:x2; val_offset:25365*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25365*FLEN/8, x3, x1, x4) + +inst_8490: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfe00; +op3val:0x7e01; valaddr_reg:x2; val_offset:25368*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25368*FLEN/8, x3, x1, x4) + +inst_8491: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfe00; +op3val:0xfe55; valaddr_reg:x2; val_offset:25371*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25371*FLEN/8, x3, x1, x4) + +inst_8492: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfe00; +op3val:0x7c01; valaddr_reg:x2; val_offset:25374*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25374*FLEN/8, x3, x1, x4) + +inst_8493: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfe00; +op3val:0xfd55; valaddr_reg:x2; val_offset:25377*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25377*FLEN/8, x3, x1, x4) + +inst_8494: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfe00; +op3val:0x3c00; valaddr_reg:x2; val_offset:25380*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25380*FLEN/8, x3, x1, x4) + +inst_8495: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfe00; +op3val:0xbc00; valaddr_reg:x2; val_offset:25383*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25383*FLEN/8, x3, x1, x4) + +inst_8496: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7e01; +op3val:0x0; valaddr_reg:x2; val_offset:25386*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25386*FLEN/8, x3, x1, x4) + +inst_8497: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7e01; +op3val:0x8000; valaddr_reg:x2; val_offset:25389*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25389*FLEN/8, x3, x1, x4) + +inst_8498: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7e01; +op3val:0x1; valaddr_reg:x2; val_offset:25392*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25392*FLEN/8, x3, x1, x4) + +inst_8499: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7e01; +op3val:0x8001; valaddr_reg:x2; val_offset:25395*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25395*FLEN/8, x3, x1, x4) + +inst_8500: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7e01; +op3val:0x2; valaddr_reg:x2; val_offset:25398*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25398*FLEN/8, x3, x1, x4) + +inst_8501: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7e01; +op3val:0x83fe; valaddr_reg:x2; val_offset:25401*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25401*FLEN/8, x3, x1, x4) + +inst_8502: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7e01; +op3val:0x3ff; valaddr_reg:x2; val_offset:25404*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25404*FLEN/8, x3, x1, x4) + +inst_8503: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7e01; +op3val:0x83ff; valaddr_reg:x2; val_offset:25407*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25407*FLEN/8, x3, x1, x4) + +inst_8504: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7e01; +op3val:0x400; valaddr_reg:x2; val_offset:25410*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25410*FLEN/8, x3, x1, x4) + +inst_8505: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7e01; +op3val:0x8400; valaddr_reg:x2; val_offset:25413*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25413*FLEN/8, x3, x1, x4) + +inst_8506: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7e01; +op3val:0x401; valaddr_reg:x2; val_offset:25416*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25416*FLEN/8, x3, x1, x4) + +inst_8507: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7e01; +op3val:0x8455; valaddr_reg:x2; val_offset:25419*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25419*FLEN/8, x3, x1, x4) + +inst_8508: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7e01; +op3val:0x7bff; valaddr_reg:x2; val_offset:25422*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25422*FLEN/8, x3, x1, x4) + +inst_8509: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7e01; +op3val:0xfbff; valaddr_reg:x2; val_offset:25425*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25425*FLEN/8, x3, x1, x4) + +inst_8510: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7e01; +op3val:0x7c00; valaddr_reg:x2; val_offset:25428*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25428*FLEN/8, x3, x1, x4) + +inst_8511: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7e01; +op3val:0xfc00; valaddr_reg:x2; val_offset:25431*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25431*FLEN/8, x3, x1, x4) + +inst_8512: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7e01; +op3val:0x7e00; valaddr_reg:x2; val_offset:25434*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25434*FLEN/8, x3, x1, x4) + +inst_8513: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7e01; +op3val:0xfe00; valaddr_reg:x2; val_offset:25437*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25437*FLEN/8, x3, x1, x4) + +inst_8514: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7e01; +op3val:0x7e01; valaddr_reg:x2; val_offset:25440*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25440*FLEN/8, x3, x1, x4) + +inst_8515: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7e01; +op3val:0xfe55; valaddr_reg:x2; val_offset:25443*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25443*FLEN/8, x3, x1, x4) + +inst_8516: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7e01; +op3val:0x7c01; valaddr_reg:x2; val_offset:25446*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25446*FLEN/8, x3, x1, x4) + +inst_8517: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7e01; +op3val:0xfd55; valaddr_reg:x2; val_offset:25449*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25449*FLEN/8, x3, x1, x4) + +inst_8518: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7e01; +op3val:0x3c00; valaddr_reg:x2; val_offset:25452*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25452*FLEN/8, x3, x1, x4) + +inst_8519: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7e01; +op3val:0xbc00; valaddr_reg:x2; val_offset:25455*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25455*FLEN/8, x3, x1, x4) + +inst_8520: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfe55; +op3val:0x0; valaddr_reg:x2; val_offset:25458*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25458*FLEN/8, x3, x1, x4) + +inst_8521: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfe55; +op3val:0x8000; valaddr_reg:x2; val_offset:25461*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25461*FLEN/8, x3, x1, x4) + +inst_8522: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfe55; +op3val:0x1; valaddr_reg:x2; val_offset:25464*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25464*FLEN/8, x3, x1, x4) + +inst_8523: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfe55; +op3val:0x8001; valaddr_reg:x2; val_offset:25467*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25467*FLEN/8, x3, x1, x4) + +inst_8524: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfe55; +op3val:0x2; valaddr_reg:x2; val_offset:25470*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25470*FLEN/8, x3, x1, x4) + +inst_8525: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfe55; +op3val:0x83fe; valaddr_reg:x2; val_offset:25473*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25473*FLEN/8, x3, x1, x4) + +inst_8526: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfe55; +op3val:0x3ff; valaddr_reg:x2; val_offset:25476*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25476*FLEN/8, x3, x1, x4) + +inst_8527: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfe55; +op3val:0x83ff; valaddr_reg:x2; val_offset:25479*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25479*FLEN/8, x3, x1, x4) + +inst_8528: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfe55; +op3val:0x400; valaddr_reg:x2; val_offset:25482*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25482*FLEN/8, x3, x1, x4) + +inst_8529: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfe55; +op3val:0x8400; valaddr_reg:x2; val_offset:25485*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25485*FLEN/8, x3, x1, x4) + +inst_8530: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfe55; +op3val:0x401; valaddr_reg:x2; val_offset:25488*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25488*FLEN/8, x3, x1, x4) + +inst_8531: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfe55; +op3val:0x8455; valaddr_reg:x2; val_offset:25491*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25491*FLEN/8, x3, x1, x4) + +inst_8532: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfe55; +op3val:0x7bff; valaddr_reg:x2; val_offset:25494*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25494*FLEN/8, x3, x1, x4) + +inst_8533: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfe55; +op3val:0xfbff; valaddr_reg:x2; val_offset:25497*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25497*FLEN/8, x3, x1, x4) + +inst_8534: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfe55; +op3val:0x7c00; valaddr_reg:x2; val_offset:25500*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25500*FLEN/8, x3, x1, x4) + +inst_8535: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfe55; +op3val:0xfc00; valaddr_reg:x2; val_offset:25503*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25503*FLEN/8, x3, x1, x4) + +inst_8536: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfe55; +op3val:0x7e00; valaddr_reg:x2; val_offset:25506*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25506*FLEN/8, x3, x1, x4) + +inst_8537: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfe55; +op3val:0xfe00; valaddr_reg:x2; val_offset:25509*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25509*FLEN/8, x3, x1, x4) + +inst_8538: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfe55; +op3val:0x7e01; valaddr_reg:x2; val_offset:25512*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25512*FLEN/8, x3, x1, x4) + +inst_8539: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfe55; +op3val:0xfe55; valaddr_reg:x2; val_offset:25515*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25515*FLEN/8, x3, x1, x4) + +inst_8540: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfe55; +op3val:0x7c01; valaddr_reg:x2; val_offset:25518*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25518*FLEN/8, x3, x1, x4) + +inst_8541: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfe55; +op3val:0xfd55; valaddr_reg:x2; val_offset:25521*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25521*FLEN/8, x3, x1, x4) + +inst_8542: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfe55; +op3val:0x3c00; valaddr_reg:x2; val_offset:25524*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25524*FLEN/8, x3, x1, x4) + +inst_8543: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfe55; +op3val:0xbc00; valaddr_reg:x2; val_offset:25527*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25527*FLEN/8, x3, x1, x4) + +inst_8544: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7c01; +op3val:0x0; valaddr_reg:x2; val_offset:25530*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25530*FLEN/8, x3, x1, x4) + +inst_8545: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7c01; +op3val:0x8000; valaddr_reg:x2; val_offset:25533*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25533*FLEN/8, x3, x1, x4) + +inst_8546: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7c01; +op3val:0x1; valaddr_reg:x2; val_offset:25536*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25536*FLEN/8, x3, x1, x4) + +inst_8547: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7c01; +op3val:0x8001; valaddr_reg:x2; val_offset:25539*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25539*FLEN/8, x3, x1, x4) + +inst_8548: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7c01; +op3val:0x2; valaddr_reg:x2; val_offset:25542*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25542*FLEN/8, x3, x1, x4) + +inst_8549: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7c01; +op3val:0x83fe; valaddr_reg:x2; val_offset:25545*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25545*FLEN/8, x3, x1, x4) + +inst_8550: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7c01; +op3val:0x3ff; valaddr_reg:x2; val_offset:25548*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25548*FLEN/8, x3, x1, x4) + +inst_8551: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7c01; +op3val:0x83ff; valaddr_reg:x2; val_offset:25551*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25551*FLEN/8, x3, x1, x4) + +inst_8552: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7c01; +op3val:0x400; valaddr_reg:x2; val_offset:25554*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25554*FLEN/8, x3, x1, x4) + +inst_8553: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7c01; +op3val:0x8400; valaddr_reg:x2; val_offset:25557*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25557*FLEN/8, x3, x1, x4) + +inst_8554: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7c01; +op3val:0x401; valaddr_reg:x2; val_offset:25560*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25560*FLEN/8, x3, x1, x4) + +inst_8555: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7c01; +op3val:0x8455; valaddr_reg:x2; val_offset:25563*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25563*FLEN/8, x3, x1, x4) + +inst_8556: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7c01; +op3val:0x7bff; valaddr_reg:x2; val_offset:25566*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25566*FLEN/8, x3, x1, x4) + +inst_8557: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7c01; +op3val:0xfbff; valaddr_reg:x2; val_offset:25569*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25569*FLEN/8, x3, x1, x4) + +inst_8558: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7c01; +op3val:0x7c00; valaddr_reg:x2; val_offset:25572*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25572*FLEN/8, x3, x1, x4) + +inst_8559: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7c01; +op3val:0xfc00; valaddr_reg:x2; val_offset:25575*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25575*FLEN/8, x3, x1, x4) + +inst_8560: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7c01; +op3val:0x7e00; valaddr_reg:x2; val_offset:25578*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25578*FLEN/8, x3, x1, x4) + +inst_8561: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7c01; +op3val:0xfe00; valaddr_reg:x2; val_offset:25581*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25581*FLEN/8, x3, x1, x4) + +inst_8562: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7c01; +op3val:0x7e01; valaddr_reg:x2; val_offset:25584*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25584*FLEN/8, x3, x1, x4) + +inst_8563: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7c01; +op3val:0xfe55; valaddr_reg:x2; val_offset:25587*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25587*FLEN/8, x3, x1, x4) + +inst_8564: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7c01; +op3val:0x7c01; valaddr_reg:x2; val_offset:25590*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25590*FLEN/8, x3, x1, x4) + +inst_8565: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7c01; +op3val:0xfd55; valaddr_reg:x2; val_offset:25593*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25593*FLEN/8, x3, x1, x4) + +inst_8566: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7c01; +op3val:0x3c00; valaddr_reg:x2; val_offset:25596*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25596*FLEN/8, x3, x1, x4) + +inst_8567: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x7c01; +op3val:0xbc00; valaddr_reg:x2; val_offset:25599*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25599*FLEN/8, x3, x1, x4) + +inst_8568: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfd55; +op3val:0x0; valaddr_reg:x2; val_offset:25602*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25602*FLEN/8, x3, x1, x4) + +inst_8569: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfd55; +op3val:0x8000; valaddr_reg:x2; val_offset:25605*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25605*FLEN/8, x3, x1, x4) + +inst_8570: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfd55; +op3val:0x1; valaddr_reg:x2; val_offset:25608*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25608*FLEN/8, x3, x1, x4) + +inst_8571: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfd55; +op3val:0x8001; valaddr_reg:x2; val_offset:25611*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25611*FLEN/8, x3, x1, x4) + +inst_8572: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfd55; +op3val:0x2; valaddr_reg:x2; val_offset:25614*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25614*FLEN/8, x3, x1, x4) + +inst_8573: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfd55; +op3val:0x83fe; valaddr_reg:x2; val_offset:25617*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25617*FLEN/8, x3, x1, x4) + +inst_8574: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfd55; +op3val:0x3ff; valaddr_reg:x2; val_offset:25620*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25620*FLEN/8, x3, x1, x4) + +inst_8575: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfd55; +op3val:0x83ff; valaddr_reg:x2; val_offset:25623*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25623*FLEN/8, x3, x1, x4) + +inst_8576: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfd55; +op3val:0x400; valaddr_reg:x2; val_offset:25626*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25626*FLEN/8, x3, x1, x4) + +inst_8577: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfd55; +op3val:0x8400; valaddr_reg:x2; val_offset:25629*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25629*FLEN/8, x3, x1, x4) + +inst_8578: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfd55; +op3val:0x401; valaddr_reg:x2; val_offset:25632*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25632*FLEN/8, x3, x1, x4) + +inst_8579: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfd55; +op3val:0x8455; valaddr_reg:x2; val_offset:25635*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25635*FLEN/8, x3, x1, x4) + +inst_8580: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfd55; +op3val:0x7bff; valaddr_reg:x2; val_offset:25638*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25638*FLEN/8, x3, x1, x4) + +inst_8581: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfd55; +op3val:0xfbff; valaddr_reg:x2; val_offset:25641*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25641*FLEN/8, x3, x1, x4) + +inst_8582: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfd55; +op3val:0x7c00; valaddr_reg:x2; val_offset:25644*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25644*FLEN/8, x3, x1, x4) + +inst_8583: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfd55; +op3val:0xfc00; valaddr_reg:x2; val_offset:25647*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25647*FLEN/8, x3, x1, x4) + +inst_8584: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfd55; +op3val:0x7e00; valaddr_reg:x2; val_offset:25650*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25650*FLEN/8, x3, x1, x4) + +inst_8585: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfd55; +op3val:0xfe00; valaddr_reg:x2; val_offset:25653*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25653*FLEN/8, x3, x1, x4) + +inst_8586: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfd55; +op3val:0x7e01; valaddr_reg:x2; val_offset:25656*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25656*FLEN/8, x3, x1, x4) + +inst_8587: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfd55; +op3val:0xfe55; valaddr_reg:x2; val_offset:25659*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25659*FLEN/8, x3, x1, x4) + +inst_8588: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfd55; +op3val:0x7c01; valaddr_reg:x2; val_offset:25662*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25662*FLEN/8, x3, x1, x4) + +inst_8589: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfd55; +op3val:0xfd55; valaddr_reg:x2; val_offset:25665*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25665*FLEN/8, x3, x1, x4) + +inst_8590: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfd55; +op3val:0x3c00; valaddr_reg:x2; val_offset:25668*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25668*FLEN/8, x3, x1, x4) + +inst_8591: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xfd55; +op3val:0xbc00; valaddr_reg:x2; val_offset:25671*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25671*FLEN/8, x3, x1, x4) + +inst_8592: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x3c00; +op3val:0x0; valaddr_reg:x2; val_offset:25674*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25674*FLEN/8, x3, x1, x4) + +inst_8593: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x3c00; +op3val:0x8000; valaddr_reg:x2; val_offset:25677*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25677*FLEN/8, x3, x1, x4) + +inst_8594: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x3c00; +op3val:0x1; valaddr_reg:x2; val_offset:25680*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25680*FLEN/8, x3, x1, x4) + +inst_8595: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x3c00; +op3val:0x8001; valaddr_reg:x2; val_offset:25683*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25683*FLEN/8, x3, x1, x4) + +inst_8596: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x3c00; +op3val:0x2; valaddr_reg:x2; val_offset:25686*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25686*FLEN/8, x3, x1, x4) + +inst_8597: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x3c00; +op3val:0x83fe; valaddr_reg:x2; val_offset:25689*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25689*FLEN/8, x3, x1, x4) + +inst_8598: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x3c00; +op3val:0x3ff; valaddr_reg:x2; val_offset:25692*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25692*FLEN/8, x3, x1, x4) + +inst_8599: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x3c00; +op3val:0x83ff; valaddr_reg:x2; val_offset:25695*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25695*FLEN/8, x3, x1, x4) + +inst_8600: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x3c00; +op3val:0x400; valaddr_reg:x2; val_offset:25698*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25698*FLEN/8, x3, x1, x4) + +inst_8601: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x3c00; +op3val:0x8400; valaddr_reg:x2; val_offset:25701*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25701*FLEN/8, x3, x1, x4) + +inst_8602: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x3c00; +op3val:0x401; valaddr_reg:x2; val_offset:25704*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25704*FLEN/8, x3, x1, x4) + +inst_8603: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x3c00; +op3val:0x8455; valaddr_reg:x2; val_offset:25707*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25707*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_68) + +inst_8604: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x3c00; +op3val:0x7bff; valaddr_reg:x2; val_offset:25710*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25710*FLEN/8, x3, x1, x4) + +inst_8605: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x3c00; +op3val:0xfbff; valaddr_reg:x2; val_offset:25713*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25713*FLEN/8, x3, x1, x4) + +inst_8606: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x3c00; +op3val:0x7c00; valaddr_reg:x2; val_offset:25716*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25716*FLEN/8, x3, x1, x4) + +inst_8607: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x3c00; +op3val:0xfc00; valaddr_reg:x2; val_offset:25719*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25719*FLEN/8, x3, x1, x4) + +inst_8608: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x3c00; +op3val:0x7e00; valaddr_reg:x2; val_offset:25722*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25722*FLEN/8, x3, x1, x4) + +inst_8609: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x3c00; +op3val:0xfe00; valaddr_reg:x2; val_offset:25725*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25725*FLEN/8, x3, x1, x4) + +inst_8610: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x3c00; +op3val:0x7e01; valaddr_reg:x2; val_offset:25728*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25728*FLEN/8, x3, x1, x4) + +inst_8611: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x3c00; +op3val:0xfe55; valaddr_reg:x2; val_offset:25731*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25731*FLEN/8, x3, x1, x4) + +inst_8612: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x3c00; +op3val:0x7c01; valaddr_reg:x2; val_offset:25734*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25734*FLEN/8, x3, x1, x4) + +inst_8613: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x3c00; +op3val:0xfd55; valaddr_reg:x2; val_offset:25737*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25737*FLEN/8, x3, x1, x4) + +inst_8614: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x3c00; +op3val:0x3c00; valaddr_reg:x2; val_offset:25740*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25740*FLEN/8, x3, x1, x4) + +inst_8615: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0x3c00; +op3val:0xbc00; valaddr_reg:x2; val_offset:25743*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25743*FLEN/8, x3, x1, x4) + +inst_8616: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xbc00; +op3val:0x0; valaddr_reg:x2; val_offset:25746*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25746*FLEN/8, x3, x1, x4) + +inst_8617: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xbc00; +op3val:0x8000; valaddr_reg:x2; val_offset:25749*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25749*FLEN/8, x3, x1, x4) + +inst_8618: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xbc00; +op3val:0x1; valaddr_reg:x2; val_offset:25752*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25752*FLEN/8, x3, x1, x4) + +inst_8619: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xbc00; +op3val:0x8001; valaddr_reg:x2; val_offset:25755*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25755*FLEN/8, x3, x1, x4) + +inst_8620: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xbc00; +op3val:0x2; valaddr_reg:x2; val_offset:25758*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25758*FLEN/8, x3, x1, x4) + +inst_8621: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xbc00; +op3val:0x83fe; valaddr_reg:x2; val_offset:25761*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25761*FLEN/8, x3, x1, x4) + +inst_8622: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xbc00; +op3val:0x3ff; valaddr_reg:x2; val_offset:25764*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25764*FLEN/8, x3, x1, x4) + +inst_8623: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xbc00; +op3val:0x83ff; valaddr_reg:x2; val_offset:25767*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25767*FLEN/8, x3, x1, x4) + +inst_8624: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xbc00; +op3val:0x400; valaddr_reg:x2; val_offset:25770*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25770*FLEN/8, x3, x1, x4) + +inst_8625: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xbc00; +op3val:0x8400; valaddr_reg:x2; val_offset:25773*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25773*FLEN/8, x3, x1, x4) + +inst_8626: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xbc00; +op3val:0x401; valaddr_reg:x2; val_offset:25776*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25776*FLEN/8, x3, x1, x4) + +inst_8627: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xbc00; +op3val:0x8455; valaddr_reg:x2; val_offset:25779*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25779*FLEN/8, x3, x1, x4) + +inst_8628: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xbc00; +op3val:0x7bff; valaddr_reg:x2; val_offset:25782*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25782*FLEN/8, x3, x1, x4) + +inst_8629: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xbc00; +op3val:0xfbff; valaddr_reg:x2; val_offset:25785*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25785*FLEN/8, x3, x1, x4) + +inst_8630: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xbc00; +op3val:0x7c00; valaddr_reg:x2; val_offset:25788*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25788*FLEN/8, x3, x1, x4) + +inst_8631: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xbc00; +op3val:0xfc00; valaddr_reg:x2; val_offset:25791*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25791*FLEN/8, x3, x1, x4) + +inst_8632: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xbc00; +op3val:0x7e00; valaddr_reg:x2; val_offset:25794*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25794*FLEN/8, x3, x1, x4) + +inst_8633: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xbc00; +op3val:0xfe00; valaddr_reg:x2; val_offset:25797*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25797*FLEN/8, x3, x1, x4) + +inst_8634: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xbc00; +op3val:0x7e01; valaddr_reg:x2; val_offset:25800*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25800*FLEN/8, x3, x1, x4) + +inst_8635: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xbc00; +op3val:0xfe55; valaddr_reg:x2; val_offset:25803*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25803*FLEN/8, x3, x1, x4) + +inst_8636: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xbc00; +op3val:0x7c01; valaddr_reg:x2; val_offset:25806*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25806*FLEN/8, x3, x1, x4) + +inst_8637: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xbc00; +op3val:0xfd55; valaddr_reg:x2; val_offset:25809*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25809*FLEN/8, x3, x1, x4) + +inst_8638: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xbc00; +op3val:0x3c00; valaddr_reg:x2; val_offset:25812*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25812*FLEN/8, x3, x1, x4) + +inst_8639: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c00; op2val:0xbc00; +op3val:0xbc00; valaddr_reg:x2; val_offset:25815*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25815*FLEN/8, x3, x1, x4) + +inst_8640: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x0; +op3val:0x0; valaddr_reg:x2; val_offset:25818*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25818*FLEN/8, x3, x1, x4) + +inst_8641: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x0; +op3val:0x8000; valaddr_reg:x2; val_offset:25821*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25821*FLEN/8, x3, x1, x4) + +inst_8642: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x0; +op3val:0x1; valaddr_reg:x2; val_offset:25824*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25824*FLEN/8, x3, x1, x4) + +inst_8643: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x0; +op3val:0x8001; valaddr_reg:x2; val_offset:25827*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25827*FLEN/8, x3, x1, x4) + +inst_8644: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x0; +op3val:0x2; valaddr_reg:x2; val_offset:25830*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25830*FLEN/8, x3, x1, x4) + +inst_8645: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x0; +op3val:0x83fe; valaddr_reg:x2; val_offset:25833*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25833*FLEN/8, x3, x1, x4) + +inst_8646: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x0; +op3val:0x3ff; valaddr_reg:x2; val_offset:25836*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25836*FLEN/8, x3, x1, x4) + +inst_8647: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x0; +op3val:0x83ff; valaddr_reg:x2; val_offset:25839*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25839*FLEN/8, x3, x1, x4) + +inst_8648: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x0; +op3val:0x400; valaddr_reg:x2; val_offset:25842*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25842*FLEN/8, x3, x1, x4) + +inst_8649: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x0; +op3val:0x8400; valaddr_reg:x2; val_offset:25845*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25845*FLEN/8, x3, x1, x4) + +inst_8650: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x0; +op3val:0x401; valaddr_reg:x2; val_offset:25848*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25848*FLEN/8, x3, x1, x4) + +inst_8651: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x0; +op3val:0x8455; valaddr_reg:x2; val_offset:25851*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25851*FLEN/8, x3, x1, x4) + +inst_8652: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x0; +op3val:0x7bff; valaddr_reg:x2; val_offset:25854*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25854*FLEN/8, x3, x1, x4) + +inst_8653: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x0; +op3val:0xfbff; valaddr_reg:x2; val_offset:25857*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25857*FLEN/8, x3, x1, x4) + +inst_8654: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x0; +op3val:0x7c00; valaddr_reg:x2; val_offset:25860*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25860*FLEN/8, x3, x1, x4) + +inst_8655: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x0; +op3val:0xfc00; valaddr_reg:x2; val_offset:25863*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25863*FLEN/8, x3, x1, x4) + +inst_8656: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x0; +op3val:0x7e00; valaddr_reg:x2; val_offset:25866*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25866*FLEN/8, x3, x1, x4) + +inst_8657: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x0; +op3val:0xfe00; valaddr_reg:x2; val_offset:25869*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25869*FLEN/8, x3, x1, x4) + +inst_8658: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x0; +op3val:0x7e01; valaddr_reg:x2; val_offset:25872*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25872*FLEN/8, x3, x1, x4) + +inst_8659: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x0; +op3val:0xfe55; valaddr_reg:x2; val_offset:25875*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25875*FLEN/8, x3, x1, x4) + +inst_8660: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x0; +op3val:0x7c01; valaddr_reg:x2; val_offset:25878*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25878*FLEN/8, x3, x1, x4) + +inst_8661: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x0; +op3val:0xfd55; valaddr_reg:x2; val_offset:25881*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25881*FLEN/8, x3, x1, x4) + +inst_8662: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x0; +op3val:0x3c00; valaddr_reg:x2; val_offset:25884*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25884*FLEN/8, x3, x1, x4) + +inst_8663: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x0; +op3val:0xbc00; valaddr_reg:x2; val_offset:25887*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25887*FLEN/8, x3, x1, x4) + +inst_8664: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8000; +op3val:0x0; valaddr_reg:x2; val_offset:25890*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25890*FLEN/8, x3, x1, x4) + +inst_8665: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8000; +op3val:0x8000; valaddr_reg:x2; val_offset:25893*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25893*FLEN/8, x3, x1, x4) + +inst_8666: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8000; +op3val:0x1; valaddr_reg:x2; val_offset:25896*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25896*FLEN/8, x3, x1, x4) + +inst_8667: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8000; +op3val:0x8001; valaddr_reg:x2; val_offset:25899*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25899*FLEN/8, x3, x1, x4) + +inst_8668: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8000; +op3val:0x2; valaddr_reg:x2; val_offset:25902*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25902*FLEN/8, x3, x1, x4) + +inst_8669: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8000; +op3val:0x83fe; valaddr_reg:x2; val_offset:25905*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25905*FLEN/8, x3, x1, x4) + +inst_8670: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8000; +op3val:0x3ff; valaddr_reg:x2; val_offset:25908*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25908*FLEN/8, x3, x1, x4) + +inst_8671: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8000; +op3val:0x83ff; valaddr_reg:x2; val_offset:25911*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25911*FLEN/8, x3, x1, x4) + +inst_8672: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8000; +op3val:0x400; valaddr_reg:x2; val_offset:25914*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25914*FLEN/8, x3, x1, x4) + +inst_8673: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8000; +op3val:0x8400; valaddr_reg:x2; val_offset:25917*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25917*FLEN/8, x3, x1, x4) + +inst_8674: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8000; +op3val:0x401; valaddr_reg:x2; val_offset:25920*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25920*FLEN/8, x3, x1, x4) + +inst_8675: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8000; +op3val:0x8455; valaddr_reg:x2; val_offset:25923*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25923*FLEN/8, x3, x1, x4) + +inst_8676: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x2; val_offset:25926*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25926*FLEN/8, x3, x1, x4) + +inst_8677: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x2; val_offset:25929*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25929*FLEN/8, x3, x1, x4) + +inst_8678: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8000; +op3val:0x7c00; valaddr_reg:x2; val_offset:25932*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25932*FLEN/8, x3, x1, x4) + +inst_8679: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8000; +op3val:0xfc00; valaddr_reg:x2; val_offset:25935*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25935*FLEN/8, x3, x1, x4) + +inst_8680: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8000; +op3val:0x7e00; valaddr_reg:x2; val_offset:25938*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25938*FLEN/8, x3, x1, x4) + +inst_8681: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8000; +op3val:0xfe00; valaddr_reg:x2; val_offset:25941*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25941*FLEN/8, x3, x1, x4) + +inst_8682: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8000; +op3val:0x7e01; valaddr_reg:x2; val_offset:25944*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25944*FLEN/8, x3, x1, x4) + +inst_8683: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8000; +op3val:0xfe55; valaddr_reg:x2; val_offset:25947*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25947*FLEN/8, x3, x1, x4) + +inst_8684: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8000; +op3val:0x7c01; valaddr_reg:x2; val_offset:25950*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25950*FLEN/8, x3, x1, x4) + +inst_8685: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8000; +op3val:0xfd55; valaddr_reg:x2; val_offset:25953*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25953*FLEN/8, x3, x1, x4) + +inst_8686: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8000; +op3val:0x3c00; valaddr_reg:x2; val_offset:25956*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25956*FLEN/8, x3, x1, x4) + +inst_8687: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8000; +op3val:0xbc00; valaddr_reg:x2; val_offset:25959*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25959*FLEN/8, x3, x1, x4) + +inst_8688: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x1; +op3val:0x0; valaddr_reg:x2; val_offset:25962*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25962*FLEN/8, x3, x1, x4) + +inst_8689: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x1; +op3val:0x8000; valaddr_reg:x2; val_offset:25965*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25965*FLEN/8, x3, x1, x4) + +inst_8690: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x1; +op3val:0x1; valaddr_reg:x2; val_offset:25968*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25968*FLEN/8, x3, x1, x4) + +inst_8691: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x1; +op3val:0x8001; valaddr_reg:x2; val_offset:25971*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25971*FLEN/8, x3, x1, x4) + +inst_8692: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x1; +op3val:0x2; valaddr_reg:x2; val_offset:25974*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25974*FLEN/8, x3, x1, x4) + +inst_8693: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x1; +op3val:0x83fe; valaddr_reg:x2; val_offset:25977*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25977*FLEN/8, x3, x1, x4) + +inst_8694: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x1; +op3val:0x3ff; valaddr_reg:x2; val_offset:25980*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25980*FLEN/8, x3, x1, x4) + +inst_8695: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x1; +op3val:0x83ff; valaddr_reg:x2; val_offset:25983*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25983*FLEN/8, x3, x1, x4) + +inst_8696: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x1; +op3val:0x400; valaddr_reg:x2; val_offset:25986*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25986*FLEN/8, x3, x1, x4) + +inst_8697: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x1; +op3val:0x8400; valaddr_reg:x2; val_offset:25989*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25989*FLEN/8, x3, x1, x4) + +inst_8698: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x1; +op3val:0x401; valaddr_reg:x2; val_offset:25992*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25992*FLEN/8, x3, x1, x4) + +inst_8699: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x1; +op3val:0x8455; valaddr_reg:x2; val_offset:25995*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25995*FLEN/8, x3, x1, x4) + +inst_8700: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x1; +op3val:0x7bff; valaddr_reg:x2; val_offset:25998*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 25998*FLEN/8, x3, x1, x4) + +inst_8701: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x1; +op3val:0xfbff; valaddr_reg:x2; val_offset:26001*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26001*FLEN/8, x3, x1, x4) + +inst_8702: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x1; +op3val:0x7c00; valaddr_reg:x2; val_offset:26004*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26004*FLEN/8, x3, x1, x4) + +inst_8703: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x1; +op3val:0xfc00; valaddr_reg:x2; val_offset:26007*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26007*FLEN/8, x3, x1, x4) + +inst_8704: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x1; +op3val:0x7e00; valaddr_reg:x2; val_offset:26010*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26010*FLEN/8, x3, x1, x4) + +inst_8705: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x1; +op3val:0xfe00; valaddr_reg:x2; val_offset:26013*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26013*FLEN/8, x3, x1, x4) + +inst_8706: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x1; +op3val:0x7e01; valaddr_reg:x2; val_offset:26016*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26016*FLEN/8, x3, x1, x4) + +inst_8707: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x1; +op3val:0xfe55; valaddr_reg:x2; val_offset:26019*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26019*FLEN/8, x3, x1, x4) + +inst_8708: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x1; +op3val:0x7c01; valaddr_reg:x2; val_offset:26022*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26022*FLEN/8, x3, x1, x4) + +inst_8709: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x1; +op3val:0xfd55; valaddr_reg:x2; val_offset:26025*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26025*FLEN/8, x3, x1, x4) + +inst_8710: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x1; +op3val:0x3c00; valaddr_reg:x2; val_offset:26028*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26028*FLEN/8, x3, x1, x4) + +inst_8711: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x1; +op3val:0xbc00; valaddr_reg:x2; val_offset:26031*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26031*FLEN/8, x3, x1, x4) + +inst_8712: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8001; +op3val:0x0; valaddr_reg:x2; val_offset:26034*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26034*FLEN/8, x3, x1, x4) + +inst_8713: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8001; +op3val:0x8000; valaddr_reg:x2; val_offset:26037*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26037*FLEN/8, x3, x1, x4) + +inst_8714: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8001; +op3val:0x1; valaddr_reg:x2; val_offset:26040*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26040*FLEN/8, x3, x1, x4) + +inst_8715: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8001; +op3val:0x8001; valaddr_reg:x2; val_offset:26043*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26043*FLEN/8, x3, x1, x4) + +inst_8716: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8001; +op3val:0x2; valaddr_reg:x2; val_offset:26046*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26046*FLEN/8, x3, x1, x4) + +inst_8717: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8001; +op3val:0x83fe; valaddr_reg:x2; val_offset:26049*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26049*FLEN/8, x3, x1, x4) + +inst_8718: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8001; +op3val:0x3ff; valaddr_reg:x2; val_offset:26052*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26052*FLEN/8, x3, x1, x4) + +inst_8719: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8001; +op3val:0x83ff; valaddr_reg:x2; val_offset:26055*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26055*FLEN/8, x3, x1, x4) + +inst_8720: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8001; +op3val:0x400; valaddr_reg:x2; val_offset:26058*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26058*FLEN/8, x3, x1, x4) + +inst_8721: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8001; +op3val:0x8400; valaddr_reg:x2; val_offset:26061*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26061*FLEN/8, x3, x1, x4) + +inst_8722: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8001; +op3val:0x401; valaddr_reg:x2; val_offset:26064*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26064*FLEN/8, x3, x1, x4) + +inst_8723: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8001; +op3val:0x8455; valaddr_reg:x2; val_offset:26067*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26067*FLEN/8, x3, x1, x4) + +inst_8724: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8001; +op3val:0x7bff; valaddr_reg:x2; val_offset:26070*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26070*FLEN/8, x3, x1, x4) + +inst_8725: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8001; +op3val:0xfbff; valaddr_reg:x2; val_offset:26073*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26073*FLEN/8, x3, x1, x4) + +inst_8726: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8001; +op3val:0x7c00; valaddr_reg:x2; val_offset:26076*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26076*FLEN/8, x3, x1, x4) + +inst_8727: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8001; +op3val:0xfc00; valaddr_reg:x2; val_offset:26079*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26079*FLEN/8, x3, x1, x4) + +inst_8728: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8001; +op3val:0x7e00; valaddr_reg:x2; val_offset:26082*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26082*FLEN/8, x3, x1, x4) + +inst_8729: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8001; +op3val:0xfe00; valaddr_reg:x2; val_offset:26085*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26085*FLEN/8, x3, x1, x4) + +inst_8730: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8001; +op3val:0x7e01; valaddr_reg:x2; val_offset:26088*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26088*FLEN/8, x3, x1, x4) + +inst_8731: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8001; +op3val:0xfe55; valaddr_reg:x2; val_offset:26091*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26091*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_69) + +inst_8732: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8001; +op3val:0x7c01; valaddr_reg:x2; val_offset:26094*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26094*FLEN/8, x3, x1, x4) + +inst_8733: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8001; +op3val:0xfd55; valaddr_reg:x2; val_offset:26097*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26097*FLEN/8, x3, x1, x4) + +inst_8734: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8001; +op3val:0x3c00; valaddr_reg:x2; val_offset:26100*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26100*FLEN/8, x3, x1, x4) + +inst_8735: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8001; +op3val:0xbc00; valaddr_reg:x2; val_offset:26103*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26103*FLEN/8, x3, x1, x4) + +inst_8736: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x2; +op3val:0x0; valaddr_reg:x2; val_offset:26106*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26106*FLEN/8, x3, x1, x4) + +inst_8737: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x2; +op3val:0x8000; valaddr_reg:x2; val_offset:26109*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26109*FLEN/8, x3, x1, x4) + +inst_8738: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x2; +op3val:0x1; valaddr_reg:x2; val_offset:26112*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26112*FLEN/8, x3, x1, x4) + +inst_8739: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x2; +op3val:0x8001; valaddr_reg:x2; val_offset:26115*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26115*FLEN/8, x3, x1, x4) + +inst_8740: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x2; +op3val:0x2; valaddr_reg:x2; val_offset:26118*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26118*FLEN/8, x3, x1, x4) + +inst_8741: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x2; +op3val:0x83fe; valaddr_reg:x2; val_offset:26121*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26121*FLEN/8, x3, x1, x4) + +inst_8742: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x2; +op3val:0x3ff; valaddr_reg:x2; val_offset:26124*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26124*FLEN/8, x3, x1, x4) + +inst_8743: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x2; +op3val:0x83ff; valaddr_reg:x2; val_offset:26127*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26127*FLEN/8, x3, x1, x4) + +inst_8744: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x2; +op3val:0x400; valaddr_reg:x2; val_offset:26130*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26130*FLEN/8, x3, x1, x4) + +inst_8745: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x2; +op3val:0x8400; valaddr_reg:x2; val_offset:26133*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26133*FLEN/8, x3, x1, x4) + +inst_8746: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x2; +op3val:0x401; valaddr_reg:x2; val_offset:26136*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26136*FLEN/8, x3, x1, x4) + +inst_8747: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x2; +op3val:0x8455; valaddr_reg:x2; val_offset:26139*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26139*FLEN/8, x3, x1, x4) + +inst_8748: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x2; +op3val:0x7bff; valaddr_reg:x2; val_offset:26142*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26142*FLEN/8, x3, x1, x4) + +inst_8749: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x2; +op3val:0xfbff; valaddr_reg:x2; val_offset:26145*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26145*FLEN/8, x3, x1, x4) + +inst_8750: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x2; +op3val:0x7c00; valaddr_reg:x2; val_offset:26148*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26148*FLEN/8, x3, x1, x4) + +inst_8751: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x2; +op3val:0xfc00; valaddr_reg:x2; val_offset:26151*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26151*FLEN/8, x3, x1, x4) + +inst_8752: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x2; +op3val:0x7e00; valaddr_reg:x2; val_offset:26154*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26154*FLEN/8, x3, x1, x4) + +inst_8753: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x2; +op3val:0xfe00; valaddr_reg:x2; val_offset:26157*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26157*FLEN/8, x3, x1, x4) + +inst_8754: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x2; +op3val:0x7e01; valaddr_reg:x2; val_offset:26160*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26160*FLEN/8, x3, x1, x4) + +inst_8755: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x2; +op3val:0xfe55; valaddr_reg:x2; val_offset:26163*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26163*FLEN/8, x3, x1, x4) + +inst_8756: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x2; +op3val:0x7c01; valaddr_reg:x2; val_offset:26166*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26166*FLEN/8, x3, x1, x4) + +inst_8757: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x2; +op3val:0xfd55; valaddr_reg:x2; val_offset:26169*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26169*FLEN/8, x3, x1, x4) + +inst_8758: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x2; +op3val:0x3c00; valaddr_reg:x2; val_offset:26172*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26172*FLEN/8, x3, x1, x4) + +inst_8759: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x2; +op3val:0xbc00; valaddr_reg:x2; val_offset:26175*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26175*FLEN/8, x3, x1, x4) + +inst_8760: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x83fe; +op3val:0x0; valaddr_reg:x2; val_offset:26178*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26178*FLEN/8, x3, x1, x4) + +inst_8761: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x83fe; +op3val:0x8000; valaddr_reg:x2; val_offset:26181*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26181*FLEN/8, x3, x1, x4) + +inst_8762: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x83fe; +op3val:0x1; valaddr_reg:x2; val_offset:26184*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26184*FLEN/8, x3, x1, x4) + +inst_8763: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x83fe; +op3val:0x8001; valaddr_reg:x2; val_offset:26187*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26187*FLEN/8, x3, x1, x4) + +inst_8764: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x83fe; +op3val:0x2; valaddr_reg:x2; val_offset:26190*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26190*FLEN/8, x3, x1, x4) + +inst_8765: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x83fe; +op3val:0x83fe; valaddr_reg:x2; val_offset:26193*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26193*FLEN/8, x3, x1, x4) + +inst_8766: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x83fe; +op3val:0x3ff; valaddr_reg:x2; val_offset:26196*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26196*FLEN/8, x3, x1, x4) + +inst_8767: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x83fe; +op3val:0x83ff; valaddr_reg:x2; val_offset:26199*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26199*FLEN/8, x3, x1, x4) + +inst_8768: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x83fe; +op3val:0x400; valaddr_reg:x2; val_offset:26202*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26202*FLEN/8, x3, x1, x4) + +inst_8769: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x83fe; +op3val:0x8400; valaddr_reg:x2; val_offset:26205*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26205*FLEN/8, x3, x1, x4) + +inst_8770: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x83fe; +op3val:0x401; valaddr_reg:x2; val_offset:26208*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26208*FLEN/8, x3, x1, x4) + +inst_8771: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x83fe; +op3val:0x8455; valaddr_reg:x2; val_offset:26211*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26211*FLEN/8, x3, x1, x4) + +inst_8772: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x83fe; +op3val:0x7bff; valaddr_reg:x2; val_offset:26214*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26214*FLEN/8, x3, x1, x4) + +inst_8773: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x83fe; +op3val:0xfbff; valaddr_reg:x2; val_offset:26217*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26217*FLEN/8, x3, x1, x4) + +inst_8774: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x83fe; +op3val:0x7c00; valaddr_reg:x2; val_offset:26220*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26220*FLEN/8, x3, x1, x4) + +inst_8775: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x83fe; +op3val:0xfc00; valaddr_reg:x2; val_offset:26223*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26223*FLEN/8, x3, x1, x4) + +inst_8776: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x83fe; +op3val:0x7e00; valaddr_reg:x2; val_offset:26226*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26226*FLEN/8, x3, x1, x4) + +inst_8777: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x83fe; +op3val:0xfe00; valaddr_reg:x2; val_offset:26229*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26229*FLEN/8, x3, x1, x4) + +inst_8778: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x83fe; +op3val:0x7e01; valaddr_reg:x2; val_offset:26232*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26232*FLEN/8, x3, x1, x4) + +inst_8779: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x83fe; +op3val:0xfe55; valaddr_reg:x2; val_offset:26235*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26235*FLEN/8, x3, x1, x4) + +inst_8780: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x83fe; +op3val:0x7c01; valaddr_reg:x2; val_offset:26238*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26238*FLEN/8, x3, x1, x4) + +inst_8781: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x83fe; +op3val:0xfd55; valaddr_reg:x2; val_offset:26241*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26241*FLEN/8, x3, x1, x4) + +inst_8782: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x83fe; +op3val:0x3c00; valaddr_reg:x2; val_offset:26244*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26244*FLEN/8, x3, x1, x4) + +inst_8783: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x83fe; +op3val:0xbc00; valaddr_reg:x2; val_offset:26247*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26247*FLEN/8, x3, x1, x4) + +inst_8784: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x3ff; +op3val:0x0; valaddr_reg:x2; val_offset:26250*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26250*FLEN/8, x3, x1, x4) + +inst_8785: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x3ff; +op3val:0x8000; valaddr_reg:x2; val_offset:26253*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26253*FLEN/8, x3, x1, x4) + +inst_8786: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x3ff; +op3val:0x1; valaddr_reg:x2; val_offset:26256*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26256*FLEN/8, x3, x1, x4) + +inst_8787: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x3ff; +op3val:0x8001; valaddr_reg:x2; val_offset:26259*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26259*FLEN/8, x3, x1, x4) + +inst_8788: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x3ff; +op3val:0x2; valaddr_reg:x2; val_offset:26262*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26262*FLEN/8, x3, x1, x4) + +inst_8789: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x3ff; +op3val:0x83fe; valaddr_reg:x2; val_offset:26265*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26265*FLEN/8, x3, x1, x4) + +inst_8790: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x3ff; +op3val:0x3ff; valaddr_reg:x2; val_offset:26268*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26268*FLEN/8, x3, x1, x4) + +inst_8791: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x3ff; +op3val:0x83ff; valaddr_reg:x2; val_offset:26271*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26271*FLEN/8, x3, x1, x4) + +inst_8792: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x3ff; +op3val:0x400; valaddr_reg:x2; val_offset:26274*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26274*FLEN/8, x3, x1, x4) + +inst_8793: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x3ff; +op3val:0x8400; valaddr_reg:x2; val_offset:26277*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26277*FLEN/8, x3, x1, x4) + +inst_8794: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x3ff; +op3val:0x401; valaddr_reg:x2; val_offset:26280*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26280*FLEN/8, x3, x1, x4) + +inst_8795: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x3ff; +op3val:0x8455; valaddr_reg:x2; val_offset:26283*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26283*FLEN/8, x3, x1, x4) + +inst_8796: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x3ff; +op3val:0x7bff; valaddr_reg:x2; val_offset:26286*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26286*FLEN/8, x3, x1, x4) + +inst_8797: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x3ff; +op3val:0xfbff; valaddr_reg:x2; val_offset:26289*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26289*FLEN/8, x3, x1, x4) + +inst_8798: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x3ff; +op3val:0x7c00; valaddr_reg:x2; val_offset:26292*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26292*FLEN/8, x3, x1, x4) + +inst_8799: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x3ff; +op3val:0xfc00; valaddr_reg:x2; val_offset:26295*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26295*FLEN/8, x3, x1, x4) + +inst_8800: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x3ff; +op3val:0x7e00; valaddr_reg:x2; val_offset:26298*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26298*FLEN/8, x3, x1, x4) + +inst_8801: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x3ff; +op3val:0xfe00; valaddr_reg:x2; val_offset:26301*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26301*FLEN/8, x3, x1, x4) + +inst_8802: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x3ff; +op3val:0x7e01; valaddr_reg:x2; val_offset:26304*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26304*FLEN/8, x3, x1, x4) + +inst_8803: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x3ff; +op3val:0xfe55; valaddr_reg:x2; val_offset:26307*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26307*FLEN/8, x3, x1, x4) + +inst_8804: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x3ff; +op3val:0x7c01; valaddr_reg:x2; val_offset:26310*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26310*FLEN/8, x3, x1, x4) + +inst_8805: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x3ff; +op3val:0xfd55; valaddr_reg:x2; val_offset:26313*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26313*FLEN/8, x3, x1, x4) + +inst_8806: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x3ff; +op3val:0x3c00; valaddr_reg:x2; val_offset:26316*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26316*FLEN/8, x3, x1, x4) + +inst_8807: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x3ff; +op3val:0xbc00; valaddr_reg:x2; val_offset:26319*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26319*FLEN/8, x3, x1, x4) + +inst_8808: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x83ff; +op3val:0x0; valaddr_reg:x2; val_offset:26322*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26322*FLEN/8, x3, x1, x4) + +inst_8809: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x83ff; +op3val:0x8000; valaddr_reg:x2; val_offset:26325*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26325*FLEN/8, x3, x1, x4) + +inst_8810: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x83ff; +op3val:0x1; valaddr_reg:x2; val_offset:26328*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26328*FLEN/8, x3, x1, x4) + +inst_8811: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x83ff; +op3val:0x8001; valaddr_reg:x2; val_offset:26331*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26331*FLEN/8, x3, x1, x4) + +inst_8812: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x83ff; +op3val:0x2; valaddr_reg:x2; val_offset:26334*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26334*FLEN/8, x3, x1, x4) + +inst_8813: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x83ff; +op3val:0x83fe; valaddr_reg:x2; val_offset:26337*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26337*FLEN/8, x3, x1, x4) + +inst_8814: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x83ff; +op3val:0x3ff; valaddr_reg:x2; val_offset:26340*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26340*FLEN/8, x3, x1, x4) + +inst_8815: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x83ff; +op3val:0x83ff; valaddr_reg:x2; val_offset:26343*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26343*FLEN/8, x3, x1, x4) + +inst_8816: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x83ff; +op3val:0x400; valaddr_reg:x2; val_offset:26346*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26346*FLEN/8, x3, x1, x4) + +inst_8817: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x83ff; +op3val:0x8400; valaddr_reg:x2; val_offset:26349*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26349*FLEN/8, x3, x1, x4) + +inst_8818: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x83ff; +op3val:0x401; valaddr_reg:x2; val_offset:26352*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26352*FLEN/8, x3, x1, x4) + +inst_8819: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x83ff; +op3val:0x8455; valaddr_reg:x2; val_offset:26355*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26355*FLEN/8, x3, x1, x4) + +inst_8820: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x83ff; +op3val:0x7bff; valaddr_reg:x2; val_offset:26358*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26358*FLEN/8, x3, x1, x4) + +inst_8821: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x83ff; +op3val:0xfbff; valaddr_reg:x2; val_offset:26361*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26361*FLEN/8, x3, x1, x4) + +inst_8822: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x83ff; +op3val:0x7c00; valaddr_reg:x2; val_offset:26364*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26364*FLEN/8, x3, x1, x4) + +inst_8823: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x83ff; +op3val:0xfc00; valaddr_reg:x2; val_offset:26367*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26367*FLEN/8, x3, x1, x4) + +inst_8824: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x83ff; +op3val:0x7e00; valaddr_reg:x2; val_offset:26370*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26370*FLEN/8, x3, x1, x4) + +inst_8825: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x83ff; +op3val:0xfe00; valaddr_reg:x2; val_offset:26373*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26373*FLEN/8, x3, x1, x4) + +inst_8826: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x83ff; +op3val:0x7e01; valaddr_reg:x2; val_offset:26376*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26376*FLEN/8, x3, x1, x4) + +inst_8827: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x83ff; +op3val:0xfe55; valaddr_reg:x2; val_offset:26379*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26379*FLEN/8, x3, x1, x4) + +inst_8828: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x83ff; +op3val:0x7c01; valaddr_reg:x2; val_offset:26382*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26382*FLEN/8, x3, x1, x4) + +inst_8829: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x83ff; +op3val:0xfd55; valaddr_reg:x2; val_offset:26385*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26385*FLEN/8, x3, x1, x4) + +inst_8830: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x83ff; +op3val:0x3c00; valaddr_reg:x2; val_offset:26388*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26388*FLEN/8, x3, x1, x4) + +inst_8831: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x83ff; +op3val:0xbc00; valaddr_reg:x2; val_offset:26391*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26391*FLEN/8, x3, x1, x4) + +inst_8832: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x400; +op3val:0x0; valaddr_reg:x2; val_offset:26394*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26394*FLEN/8, x3, x1, x4) + +inst_8833: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x400; +op3val:0x8000; valaddr_reg:x2; val_offset:26397*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26397*FLEN/8, x3, x1, x4) + +inst_8834: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x400; +op3val:0x1; valaddr_reg:x2; val_offset:26400*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26400*FLEN/8, x3, x1, x4) + +inst_8835: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x400; +op3val:0x8001; valaddr_reg:x2; val_offset:26403*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26403*FLEN/8, x3, x1, x4) + +inst_8836: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x400; +op3val:0x2; valaddr_reg:x2; val_offset:26406*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26406*FLEN/8, x3, x1, x4) + +inst_8837: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x400; +op3val:0x83fe; valaddr_reg:x2; val_offset:26409*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26409*FLEN/8, x3, x1, x4) + +inst_8838: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x400; +op3val:0x3ff; valaddr_reg:x2; val_offset:26412*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26412*FLEN/8, x3, x1, x4) + +inst_8839: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x400; +op3val:0x83ff; valaddr_reg:x2; val_offset:26415*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26415*FLEN/8, x3, x1, x4) + +inst_8840: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x400; +op3val:0x400; valaddr_reg:x2; val_offset:26418*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26418*FLEN/8, x3, x1, x4) + +inst_8841: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x400; +op3val:0x8400; valaddr_reg:x2; val_offset:26421*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26421*FLEN/8, x3, x1, x4) + +inst_8842: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x400; +op3val:0x401; valaddr_reg:x2; val_offset:26424*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26424*FLEN/8, x3, x1, x4) + +inst_8843: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x400; +op3val:0x8455; valaddr_reg:x2; val_offset:26427*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26427*FLEN/8, x3, x1, x4) + +inst_8844: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x400; +op3val:0x7bff; valaddr_reg:x2; val_offset:26430*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26430*FLEN/8, x3, x1, x4) + +inst_8845: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x400; +op3val:0xfbff; valaddr_reg:x2; val_offset:26433*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26433*FLEN/8, x3, x1, x4) + +inst_8846: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x400; +op3val:0x7c00; valaddr_reg:x2; val_offset:26436*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26436*FLEN/8, x3, x1, x4) + +inst_8847: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x400; +op3val:0xfc00; valaddr_reg:x2; val_offset:26439*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26439*FLEN/8, x3, x1, x4) + +inst_8848: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x400; +op3val:0x7e00; valaddr_reg:x2; val_offset:26442*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26442*FLEN/8, x3, x1, x4) + +inst_8849: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x400; +op3val:0xfe00; valaddr_reg:x2; val_offset:26445*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26445*FLEN/8, x3, x1, x4) + +inst_8850: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x400; +op3val:0x7e01; valaddr_reg:x2; val_offset:26448*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26448*FLEN/8, x3, x1, x4) + +inst_8851: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x400; +op3val:0xfe55; valaddr_reg:x2; val_offset:26451*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26451*FLEN/8, x3, x1, x4) + +inst_8852: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x400; +op3val:0x7c01; valaddr_reg:x2; val_offset:26454*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26454*FLEN/8, x3, x1, x4) + +inst_8853: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x400; +op3val:0xfd55; valaddr_reg:x2; val_offset:26457*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26457*FLEN/8, x3, x1, x4) + +inst_8854: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x400; +op3val:0x3c00; valaddr_reg:x2; val_offset:26460*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26460*FLEN/8, x3, x1, x4) + +inst_8855: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x400; +op3val:0xbc00; valaddr_reg:x2; val_offset:26463*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26463*FLEN/8, x3, x1, x4) + +inst_8856: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8400; +op3val:0x0; valaddr_reg:x2; val_offset:26466*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26466*FLEN/8, x3, x1, x4) + +inst_8857: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8400; +op3val:0x8000; valaddr_reg:x2; val_offset:26469*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26469*FLEN/8, x3, x1, x4) + +inst_8858: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8400; +op3val:0x1; valaddr_reg:x2; val_offset:26472*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26472*FLEN/8, x3, x1, x4) + +inst_8859: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8400; +op3val:0x8001; valaddr_reg:x2; val_offset:26475*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26475*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_70) + +inst_8860: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8400; +op3val:0x2; valaddr_reg:x2; val_offset:26478*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26478*FLEN/8, x3, x1, x4) + +inst_8861: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8400; +op3val:0x83fe; valaddr_reg:x2; val_offset:26481*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26481*FLEN/8, x3, x1, x4) + +inst_8862: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8400; +op3val:0x3ff; valaddr_reg:x2; val_offset:26484*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26484*FLEN/8, x3, x1, x4) + +inst_8863: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8400; +op3val:0x83ff; valaddr_reg:x2; val_offset:26487*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26487*FLEN/8, x3, x1, x4) + +inst_8864: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8400; +op3val:0x400; valaddr_reg:x2; val_offset:26490*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26490*FLEN/8, x3, x1, x4) + +inst_8865: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8400; +op3val:0x8400; valaddr_reg:x2; val_offset:26493*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26493*FLEN/8, x3, x1, x4) + +inst_8866: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8400; +op3val:0x401; valaddr_reg:x2; val_offset:26496*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26496*FLEN/8, x3, x1, x4) + +inst_8867: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8400; +op3val:0x8455; valaddr_reg:x2; val_offset:26499*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26499*FLEN/8, x3, x1, x4) + +inst_8868: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8400; +op3val:0x7bff; valaddr_reg:x2; val_offset:26502*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26502*FLEN/8, x3, x1, x4) + +inst_8869: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8400; +op3val:0xfbff; valaddr_reg:x2; val_offset:26505*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26505*FLEN/8, x3, x1, x4) + +inst_8870: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8400; +op3val:0x7c00; valaddr_reg:x2; val_offset:26508*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26508*FLEN/8, x3, x1, x4) + +inst_8871: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8400; +op3val:0xfc00; valaddr_reg:x2; val_offset:26511*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26511*FLEN/8, x3, x1, x4) + +inst_8872: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8400; +op3val:0x7e00; valaddr_reg:x2; val_offset:26514*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26514*FLEN/8, x3, x1, x4) + +inst_8873: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8400; +op3val:0xfe00; valaddr_reg:x2; val_offset:26517*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26517*FLEN/8, x3, x1, x4) + +inst_8874: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8400; +op3val:0x7e01; valaddr_reg:x2; val_offset:26520*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26520*FLEN/8, x3, x1, x4) + +inst_8875: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8400; +op3val:0xfe55; valaddr_reg:x2; val_offset:26523*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26523*FLEN/8, x3, x1, x4) + +inst_8876: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8400; +op3val:0x7c01; valaddr_reg:x2; val_offset:26526*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26526*FLEN/8, x3, x1, x4) + +inst_8877: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8400; +op3val:0xfd55; valaddr_reg:x2; val_offset:26529*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26529*FLEN/8, x3, x1, x4) + +inst_8878: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8400; +op3val:0x3c00; valaddr_reg:x2; val_offset:26532*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26532*FLEN/8, x3, x1, x4) + +inst_8879: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8400; +op3val:0xbc00; valaddr_reg:x2; val_offset:26535*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26535*FLEN/8, x3, x1, x4) + +inst_8880: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x401; +op3val:0x0; valaddr_reg:x2; val_offset:26538*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26538*FLEN/8, x3, x1, x4) + +inst_8881: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x401; +op3val:0x8000; valaddr_reg:x2; val_offset:26541*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26541*FLEN/8, x3, x1, x4) + +inst_8882: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x401; +op3val:0x1; valaddr_reg:x2; val_offset:26544*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26544*FLEN/8, x3, x1, x4) + +inst_8883: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x401; +op3val:0x8001; valaddr_reg:x2; val_offset:26547*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26547*FLEN/8, x3, x1, x4) + +inst_8884: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x401; +op3val:0x2; valaddr_reg:x2; val_offset:26550*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26550*FLEN/8, x3, x1, x4) + +inst_8885: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x401; +op3val:0x83fe; valaddr_reg:x2; val_offset:26553*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26553*FLEN/8, x3, x1, x4) + +inst_8886: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x401; +op3val:0x3ff; valaddr_reg:x2; val_offset:26556*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26556*FLEN/8, x3, x1, x4) + +inst_8887: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x401; +op3val:0x83ff; valaddr_reg:x2; val_offset:26559*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26559*FLEN/8, x3, x1, x4) + +inst_8888: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x401; +op3val:0x400; valaddr_reg:x2; val_offset:26562*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26562*FLEN/8, x3, x1, x4) + +inst_8889: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x401; +op3val:0x8400; valaddr_reg:x2; val_offset:26565*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26565*FLEN/8, x3, x1, x4) + +inst_8890: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x401; +op3val:0x401; valaddr_reg:x2; val_offset:26568*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26568*FLEN/8, x3, x1, x4) + +inst_8891: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x401; +op3val:0x8455; valaddr_reg:x2; val_offset:26571*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26571*FLEN/8, x3, x1, x4) + +inst_8892: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x401; +op3val:0x7bff; valaddr_reg:x2; val_offset:26574*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26574*FLEN/8, x3, x1, x4) + +inst_8893: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x401; +op3val:0xfbff; valaddr_reg:x2; val_offset:26577*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26577*FLEN/8, x3, x1, x4) + +inst_8894: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x401; +op3val:0x7c00; valaddr_reg:x2; val_offset:26580*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26580*FLEN/8, x3, x1, x4) + +inst_8895: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x401; +op3val:0xfc00; valaddr_reg:x2; val_offset:26583*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26583*FLEN/8, x3, x1, x4) + +inst_8896: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x401; +op3val:0x7e00; valaddr_reg:x2; val_offset:26586*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26586*FLEN/8, x3, x1, x4) + +inst_8897: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x401; +op3val:0xfe00; valaddr_reg:x2; val_offset:26589*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26589*FLEN/8, x3, x1, x4) + +inst_8898: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x401; +op3val:0x7e01; valaddr_reg:x2; val_offset:26592*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26592*FLEN/8, x3, x1, x4) + +inst_8899: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x401; +op3val:0xfe55; valaddr_reg:x2; val_offset:26595*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26595*FLEN/8, x3, x1, x4) + +inst_8900: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x401; +op3val:0x7c01; valaddr_reg:x2; val_offset:26598*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26598*FLEN/8, x3, x1, x4) + +inst_8901: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x401; +op3val:0xfd55; valaddr_reg:x2; val_offset:26601*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26601*FLEN/8, x3, x1, x4) + +inst_8902: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x401; +op3val:0x3c00; valaddr_reg:x2; val_offset:26604*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26604*FLEN/8, x3, x1, x4) + +inst_8903: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x401; +op3val:0xbc00; valaddr_reg:x2; val_offset:26607*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26607*FLEN/8, x3, x1, x4) + +inst_8904: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8455; +op3val:0x0; valaddr_reg:x2; val_offset:26610*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26610*FLEN/8, x3, x1, x4) + +inst_8905: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8455; +op3val:0x8000; valaddr_reg:x2; val_offset:26613*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26613*FLEN/8, x3, x1, x4) + +inst_8906: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8455; +op3val:0x1; valaddr_reg:x2; val_offset:26616*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26616*FLEN/8, x3, x1, x4) + +inst_8907: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8455; +op3val:0x8001; valaddr_reg:x2; val_offset:26619*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26619*FLEN/8, x3, x1, x4) + +inst_8908: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8455; +op3val:0x2; valaddr_reg:x2; val_offset:26622*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26622*FLEN/8, x3, x1, x4) + +inst_8909: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8455; +op3val:0x83fe; valaddr_reg:x2; val_offset:26625*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26625*FLEN/8, x3, x1, x4) + +inst_8910: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8455; +op3val:0x3ff; valaddr_reg:x2; val_offset:26628*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26628*FLEN/8, x3, x1, x4) + +inst_8911: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8455; +op3val:0x83ff; valaddr_reg:x2; val_offset:26631*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26631*FLEN/8, x3, x1, x4) + +inst_8912: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8455; +op3val:0x400; valaddr_reg:x2; val_offset:26634*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26634*FLEN/8, x3, x1, x4) + +inst_8913: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8455; +op3val:0x8400; valaddr_reg:x2; val_offset:26637*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26637*FLEN/8, x3, x1, x4) + +inst_8914: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8455; +op3val:0x401; valaddr_reg:x2; val_offset:26640*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26640*FLEN/8, x3, x1, x4) + +inst_8915: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8455; +op3val:0x8455; valaddr_reg:x2; val_offset:26643*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26643*FLEN/8, x3, x1, x4) + +inst_8916: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8455; +op3val:0x7bff; valaddr_reg:x2; val_offset:26646*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26646*FLEN/8, x3, x1, x4) + +inst_8917: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8455; +op3val:0xfbff; valaddr_reg:x2; val_offset:26649*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26649*FLEN/8, x3, x1, x4) + +inst_8918: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8455; +op3val:0x7c00; valaddr_reg:x2; val_offset:26652*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26652*FLEN/8, x3, x1, x4) + +inst_8919: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8455; +op3val:0xfc00; valaddr_reg:x2; val_offset:26655*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26655*FLEN/8, x3, x1, x4) + +inst_8920: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8455; +op3val:0x7e00; valaddr_reg:x2; val_offset:26658*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26658*FLEN/8, x3, x1, x4) + +inst_8921: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8455; +op3val:0xfe00; valaddr_reg:x2; val_offset:26661*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26661*FLEN/8, x3, x1, x4) + +inst_8922: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8455; +op3val:0x7e01; valaddr_reg:x2; val_offset:26664*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26664*FLEN/8, x3, x1, x4) + +inst_8923: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8455; +op3val:0xfe55; valaddr_reg:x2; val_offset:26667*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26667*FLEN/8, x3, x1, x4) + +inst_8924: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8455; +op3val:0x7c01; valaddr_reg:x2; val_offset:26670*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26670*FLEN/8, x3, x1, x4) + +inst_8925: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8455; +op3val:0xfd55; valaddr_reg:x2; val_offset:26673*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26673*FLEN/8, x3, x1, x4) + +inst_8926: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8455; +op3val:0x3c00; valaddr_reg:x2; val_offset:26676*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26676*FLEN/8, x3, x1, x4) + +inst_8927: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x8455; +op3val:0xbc00; valaddr_reg:x2; val_offset:26679*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26679*FLEN/8, x3, x1, x4) + +inst_8928: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7bff; +op3val:0x0; valaddr_reg:x2; val_offset:26682*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26682*FLEN/8, x3, x1, x4) + +inst_8929: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7bff; +op3val:0x8000; valaddr_reg:x2; val_offset:26685*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26685*FLEN/8, x3, x1, x4) + +inst_8930: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7bff; +op3val:0x1; valaddr_reg:x2; val_offset:26688*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26688*FLEN/8, x3, x1, x4) + +inst_8931: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7bff; +op3val:0x8001; valaddr_reg:x2; val_offset:26691*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26691*FLEN/8, x3, x1, x4) + +inst_8932: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7bff; +op3val:0x2; valaddr_reg:x2; val_offset:26694*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26694*FLEN/8, x3, x1, x4) + +inst_8933: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7bff; +op3val:0x83fe; valaddr_reg:x2; val_offset:26697*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26697*FLEN/8, x3, x1, x4) + +inst_8934: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7bff; +op3val:0x3ff; valaddr_reg:x2; val_offset:26700*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26700*FLEN/8, x3, x1, x4) + +inst_8935: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7bff; +op3val:0x83ff; valaddr_reg:x2; val_offset:26703*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26703*FLEN/8, x3, x1, x4) + +inst_8936: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7bff; +op3val:0x400; valaddr_reg:x2; val_offset:26706*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26706*FLEN/8, x3, x1, x4) + +inst_8937: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7bff; +op3val:0x8400; valaddr_reg:x2; val_offset:26709*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26709*FLEN/8, x3, x1, x4) + +inst_8938: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7bff; +op3val:0x401; valaddr_reg:x2; val_offset:26712*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26712*FLEN/8, x3, x1, x4) + +inst_8939: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7bff; +op3val:0x8455; valaddr_reg:x2; val_offset:26715*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26715*FLEN/8, x3, x1, x4) + +inst_8940: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7bff; +op3val:0x7bff; valaddr_reg:x2; val_offset:26718*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26718*FLEN/8, x3, x1, x4) + +inst_8941: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7bff; +op3val:0xfbff; valaddr_reg:x2; val_offset:26721*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26721*FLEN/8, x3, x1, x4) + +inst_8942: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7bff; +op3val:0x7c00; valaddr_reg:x2; val_offset:26724*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26724*FLEN/8, x3, x1, x4) + +inst_8943: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7bff; +op3val:0xfc00; valaddr_reg:x2; val_offset:26727*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26727*FLEN/8, x3, x1, x4) + +inst_8944: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7bff; +op3val:0x7e00; valaddr_reg:x2; val_offset:26730*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26730*FLEN/8, x3, x1, x4) + +inst_8945: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7bff; +op3val:0xfe00; valaddr_reg:x2; val_offset:26733*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26733*FLEN/8, x3, x1, x4) + +inst_8946: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7bff; +op3val:0x7e01; valaddr_reg:x2; val_offset:26736*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26736*FLEN/8, x3, x1, x4) + +inst_8947: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7bff; +op3val:0xfe55; valaddr_reg:x2; val_offset:26739*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26739*FLEN/8, x3, x1, x4) + +inst_8948: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7bff; +op3val:0x7c01; valaddr_reg:x2; val_offset:26742*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26742*FLEN/8, x3, x1, x4) + +inst_8949: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7bff; +op3val:0xfd55; valaddr_reg:x2; val_offset:26745*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26745*FLEN/8, x3, x1, x4) + +inst_8950: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7bff; +op3val:0x3c00; valaddr_reg:x2; val_offset:26748*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26748*FLEN/8, x3, x1, x4) + +inst_8951: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7bff; +op3val:0xbc00; valaddr_reg:x2; val_offset:26751*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26751*FLEN/8, x3, x1, x4) + +inst_8952: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfbff; +op3val:0x0; valaddr_reg:x2; val_offset:26754*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26754*FLEN/8, x3, x1, x4) + +inst_8953: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfbff; +op3val:0x8000; valaddr_reg:x2; val_offset:26757*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26757*FLEN/8, x3, x1, x4) + +inst_8954: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfbff; +op3val:0x1; valaddr_reg:x2; val_offset:26760*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26760*FLEN/8, x3, x1, x4) + +inst_8955: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfbff; +op3val:0x8001; valaddr_reg:x2; val_offset:26763*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26763*FLEN/8, x3, x1, x4) + +inst_8956: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfbff; +op3val:0x2; valaddr_reg:x2; val_offset:26766*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26766*FLEN/8, x3, x1, x4) + +inst_8957: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfbff; +op3val:0x83fe; valaddr_reg:x2; val_offset:26769*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26769*FLEN/8, x3, x1, x4) + +inst_8958: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfbff; +op3val:0x3ff; valaddr_reg:x2; val_offset:26772*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26772*FLEN/8, x3, x1, x4) + +inst_8959: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfbff; +op3val:0x83ff; valaddr_reg:x2; val_offset:26775*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26775*FLEN/8, x3, x1, x4) + +inst_8960: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfbff; +op3val:0x400; valaddr_reg:x2; val_offset:26778*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26778*FLEN/8, x3, x1, x4) + +inst_8961: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfbff; +op3val:0x8400; valaddr_reg:x2; val_offset:26781*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26781*FLEN/8, x3, x1, x4) + +inst_8962: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfbff; +op3val:0x401; valaddr_reg:x2; val_offset:26784*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26784*FLEN/8, x3, x1, x4) + +inst_8963: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfbff; +op3val:0x8455; valaddr_reg:x2; val_offset:26787*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26787*FLEN/8, x3, x1, x4) + +inst_8964: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfbff; +op3val:0x7bff; valaddr_reg:x2; val_offset:26790*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26790*FLEN/8, x3, x1, x4) + +inst_8965: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfbff; +op3val:0xfbff; valaddr_reg:x2; val_offset:26793*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26793*FLEN/8, x3, x1, x4) + +inst_8966: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfbff; +op3val:0x7c00; valaddr_reg:x2; val_offset:26796*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26796*FLEN/8, x3, x1, x4) + +inst_8967: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfbff; +op3val:0xfc00; valaddr_reg:x2; val_offset:26799*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26799*FLEN/8, x3, x1, x4) + +inst_8968: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfbff; +op3val:0x7e00; valaddr_reg:x2; val_offset:26802*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26802*FLEN/8, x3, x1, x4) + +inst_8969: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfbff; +op3val:0xfe00; valaddr_reg:x2; val_offset:26805*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26805*FLEN/8, x3, x1, x4) + +inst_8970: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfbff; +op3val:0x7e01; valaddr_reg:x2; val_offset:26808*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26808*FLEN/8, x3, x1, x4) + +inst_8971: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfbff; +op3val:0xfe55; valaddr_reg:x2; val_offset:26811*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26811*FLEN/8, x3, x1, x4) + +inst_8972: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfbff; +op3val:0x7c01; valaddr_reg:x2; val_offset:26814*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26814*FLEN/8, x3, x1, x4) + +inst_8973: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfbff; +op3val:0xfd55; valaddr_reg:x2; val_offset:26817*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26817*FLEN/8, x3, x1, x4) + +inst_8974: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfbff; +op3val:0x3c00; valaddr_reg:x2; val_offset:26820*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26820*FLEN/8, x3, x1, x4) + +inst_8975: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfbff; +op3val:0xbc00; valaddr_reg:x2; val_offset:26823*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26823*FLEN/8, x3, x1, x4) + +inst_8976: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7c00; +op3val:0x0; valaddr_reg:x2; val_offset:26826*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26826*FLEN/8, x3, x1, x4) + +inst_8977: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7c00; +op3val:0x8000; valaddr_reg:x2; val_offset:26829*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26829*FLEN/8, x3, x1, x4) + +inst_8978: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7c00; +op3val:0x1; valaddr_reg:x2; val_offset:26832*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26832*FLEN/8, x3, x1, x4) + +inst_8979: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7c00; +op3val:0x8001; valaddr_reg:x2; val_offset:26835*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26835*FLEN/8, x3, x1, x4) + +inst_8980: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7c00; +op3val:0x2; valaddr_reg:x2; val_offset:26838*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26838*FLEN/8, x3, x1, x4) + +inst_8981: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7c00; +op3val:0x83fe; valaddr_reg:x2; val_offset:26841*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26841*FLEN/8, x3, x1, x4) + +inst_8982: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7c00; +op3val:0x3ff; valaddr_reg:x2; val_offset:26844*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26844*FLEN/8, x3, x1, x4) + +inst_8983: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7c00; +op3val:0x83ff; valaddr_reg:x2; val_offset:26847*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26847*FLEN/8, x3, x1, x4) + +inst_8984: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7c00; +op3val:0x400; valaddr_reg:x2; val_offset:26850*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26850*FLEN/8, x3, x1, x4) + +inst_8985: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7c00; +op3val:0x8400; valaddr_reg:x2; val_offset:26853*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26853*FLEN/8, x3, x1, x4) + +inst_8986: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7c00; +op3val:0x401; valaddr_reg:x2; val_offset:26856*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26856*FLEN/8, x3, x1, x4) + +inst_8987: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7c00; +op3val:0x8455; valaddr_reg:x2; val_offset:26859*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26859*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_71) + +inst_8988: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7c00; +op3val:0x7bff; valaddr_reg:x2; val_offset:26862*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26862*FLEN/8, x3, x1, x4) + +inst_8989: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7c00; +op3val:0xfbff; valaddr_reg:x2; val_offset:26865*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26865*FLEN/8, x3, x1, x4) + +inst_8990: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7c00; +op3val:0x7c00; valaddr_reg:x2; val_offset:26868*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26868*FLEN/8, x3, x1, x4) + +inst_8991: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7c00; +op3val:0xfc00; valaddr_reg:x2; val_offset:26871*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26871*FLEN/8, x3, x1, x4) + +inst_8992: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7c00; +op3val:0x7e00; valaddr_reg:x2; val_offset:26874*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26874*FLEN/8, x3, x1, x4) + +inst_8993: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7c00; +op3val:0xfe00; valaddr_reg:x2; val_offset:26877*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26877*FLEN/8, x3, x1, x4) + +inst_8994: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7c00; +op3val:0x7e01; valaddr_reg:x2; val_offset:26880*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26880*FLEN/8, x3, x1, x4) + +inst_8995: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7c00; +op3val:0xfe55; valaddr_reg:x2; val_offset:26883*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26883*FLEN/8, x3, x1, x4) + +inst_8996: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7c00; +op3val:0x7c01; valaddr_reg:x2; val_offset:26886*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26886*FLEN/8, x3, x1, x4) + +inst_8997: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7c00; +op3val:0xfd55; valaddr_reg:x2; val_offset:26889*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26889*FLEN/8, x3, x1, x4) + +inst_8998: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7c00; +op3val:0x3c00; valaddr_reg:x2; val_offset:26892*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26892*FLEN/8, x3, x1, x4) + +inst_8999: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7c00; +op3val:0xbc00; valaddr_reg:x2; val_offset:26895*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26895*FLEN/8, x3, x1, x4) + +inst_9000: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfc00; +op3val:0x0; valaddr_reg:x2; val_offset:26898*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26898*FLEN/8, x3, x1, x4) + +inst_9001: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfc00; +op3val:0x8000; valaddr_reg:x2; val_offset:26901*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26901*FLEN/8, x3, x1, x4) + +inst_9002: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfc00; +op3val:0x1; valaddr_reg:x2; val_offset:26904*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26904*FLEN/8, x3, x1, x4) + +inst_9003: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfc00; +op3val:0x8001; valaddr_reg:x2; val_offset:26907*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26907*FLEN/8, x3, x1, x4) + +inst_9004: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfc00; +op3val:0x2; valaddr_reg:x2; val_offset:26910*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26910*FLEN/8, x3, x1, x4) + +inst_9005: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfc00; +op3val:0x83fe; valaddr_reg:x2; val_offset:26913*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26913*FLEN/8, x3, x1, x4) + +inst_9006: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfc00; +op3val:0x3ff; valaddr_reg:x2; val_offset:26916*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26916*FLEN/8, x3, x1, x4) + +inst_9007: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfc00; +op3val:0x83ff; valaddr_reg:x2; val_offset:26919*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26919*FLEN/8, x3, x1, x4) + +inst_9008: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfc00; +op3val:0x400; valaddr_reg:x2; val_offset:26922*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26922*FLEN/8, x3, x1, x4) + +inst_9009: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfc00; +op3val:0x8400; valaddr_reg:x2; val_offset:26925*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26925*FLEN/8, x3, x1, x4) + +inst_9010: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfc00; +op3val:0x401; valaddr_reg:x2; val_offset:26928*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26928*FLEN/8, x3, x1, x4) + +inst_9011: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfc00; +op3val:0x8455; valaddr_reg:x2; val_offset:26931*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26931*FLEN/8, x3, x1, x4) + +inst_9012: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfc00; +op3val:0x7bff; valaddr_reg:x2; val_offset:26934*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26934*FLEN/8, x3, x1, x4) + +inst_9013: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfc00; +op3val:0xfbff; valaddr_reg:x2; val_offset:26937*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26937*FLEN/8, x3, x1, x4) + +inst_9014: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfc00; +op3val:0x7c00; valaddr_reg:x2; val_offset:26940*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26940*FLEN/8, x3, x1, x4) + +inst_9015: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfc00; +op3val:0xfc00; valaddr_reg:x2; val_offset:26943*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26943*FLEN/8, x3, x1, x4) + +inst_9016: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfc00; +op3val:0x7e00; valaddr_reg:x2; val_offset:26946*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26946*FLEN/8, x3, x1, x4) + +inst_9017: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfc00; +op3val:0xfe00; valaddr_reg:x2; val_offset:26949*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26949*FLEN/8, x3, x1, x4) + +inst_9018: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfc00; +op3val:0x7e01; valaddr_reg:x2; val_offset:26952*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26952*FLEN/8, x3, x1, x4) + +inst_9019: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfc00; +op3val:0xfe55; valaddr_reg:x2; val_offset:26955*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26955*FLEN/8, x3, x1, x4) + +inst_9020: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfc00; +op3val:0x7c01; valaddr_reg:x2; val_offset:26958*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26958*FLEN/8, x3, x1, x4) + +inst_9021: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfc00; +op3val:0xfd55; valaddr_reg:x2; val_offset:26961*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26961*FLEN/8, x3, x1, x4) + +inst_9022: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfc00; +op3val:0x3c00; valaddr_reg:x2; val_offset:26964*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26964*FLEN/8, x3, x1, x4) + +inst_9023: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfc00; +op3val:0xbc00; valaddr_reg:x2; val_offset:26967*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26967*FLEN/8, x3, x1, x4) + +inst_9024: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7e00; +op3val:0x0; valaddr_reg:x2; val_offset:26970*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26970*FLEN/8, x3, x1, x4) + +inst_9025: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7e00; +op3val:0x8000; valaddr_reg:x2; val_offset:26973*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26973*FLEN/8, x3, x1, x4) + +inst_9026: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7e00; +op3val:0x1; valaddr_reg:x2; val_offset:26976*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26976*FLEN/8, x3, x1, x4) + +inst_9027: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7e00; +op3val:0x8001; valaddr_reg:x2; val_offset:26979*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26979*FLEN/8, x3, x1, x4) + +inst_9028: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7e00; +op3val:0x2; valaddr_reg:x2; val_offset:26982*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26982*FLEN/8, x3, x1, x4) + +inst_9029: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7e00; +op3val:0x83fe; valaddr_reg:x2; val_offset:26985*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26985*FLEN/8, x3, x1, x4) + +inst_9030: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7e00; +op3val:0x3ff; valaddr_reg:x2; val_offset:26988*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26988*FLEN/8, x3, x1, x4) + +inst_9031: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7e00; +op3val:0x83ff; valaddr_reg:x2; val_offset:26991*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26991*FLEN/8, x3, x1, x4) + +inst_9032: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7e00; +op3val:0x400; valaddr_reg:x2; val_offset:26994*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26994*FLEN/8, x3, x1, x4) + +inst_9033: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7e00; +op3val:0x8400; valaddr_reg:x2; val_offset:26997*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 26997*FLEN/8, x3, x1, x4) + +inst_9034: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7e00; +op3val:0x401; valaddr_reg:x2; val_offset:27000*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27000*FLEN/8, x3, x1, x4) + +inst_9035: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7e00; +op3val:0x8455; valaddr_reg:x2; val_offset:27003*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27003*FLEN/8, x3, x1, x4) + +inst_9036: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7e00; +op3val:0x7bff; valaddr_reg:x2; val_offset:27006*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27006*FLEN/8, x3, x1, x4) + +inst_9037: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7e00; +op3val:0xfbff; valaddr_reg:x2; val_offset:27009*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27009*FLEN/8, x3, x1, x4) + +inst_9038: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7e00; +op3val:0x7c00; valaddr_reg:x2; val_offset:27012*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27012*FLEN/8, x3, x1, x4) + +inst_9039: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7e00; +op3val:0xfc00; valaddr_reg:x2; val_offset:27015*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27015*FLEN/8, x3, x1, x4) + +inst_9040: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7e00; +op3val:0x7e00; valaddr_reg:x2; val_offset:27018*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27018*FLEN/8, x3, x1, x4) + +inst_9041: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7e00; +op3val:0xfe00; valaddr_reg:x2; val_offset:27021*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27021*FLEN/8, x3, x1, x4) + +inst_9042: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7e00; +op3val:0x7e01; valaddr_reg:x2; val_offset:27024*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27024*FLEN/8, x3, x1, x4) + +inst_9043: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7e00; +op3val:0xfe55; valaddr_reg:x2; val_offset:27027*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27027*FLEN/8, x3, x1, x4) + +inst_9044: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7e00; +op3val:0x7c01; valaddr_reg:x2; val_offset:27030*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27030*FLEN/8, x3, x1, x4) + +inst_9045: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7e00; +op3val:0xfd55; valaddr_reg:x2; val_offset:27033*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27033*FLEN/8, x3, x1, x4) + +inst_9046: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7e00; +op3val:0x3c00; valaddr_reg:x2; val_offset:27036*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27036*FLEN/8, x3, x1, x4) + +inst_9047: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7e00; +op3val:0xbc00; valaddr_reg:x2; val_offset:27039*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27039*FLEN/8, x3, x1, x4) + +inst_9048: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfe00; +op3val:0x0; valaddr_reg:x2; val_offset:27042*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27042*FLEN/8, x3, x1, x4) + +inst_9049: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfe00; +op3val:0x8000; valaddr_reg:x2; val_offset:27045*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27045*FLEN/8, x3, x1, x4) + +inst_9050: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfe00; +op3val:0x1; valaddr_reg:x2; val_offset:27048*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27048*FLEN/8, x3, x1, x4) + +inst_9051: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfe00; +op3val:0x8001; valaddr_reg:x2; val_offset:27051*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27051*FLEN/8, x3, x1, x4) + +inst_9052: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfe00; +op3val:0x2; valaddr_reg:x2; val_offset:27054*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27054*FLEN/8, x3, x1, x4) + +inst_9053: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfe00; +op3val:0x83fe; valaddr_reg:x2; val_offset:27057*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27057*FLEN/8, x3, x1, x4) + +inst_9054: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfe00; +op3val:0x3ff; valaddr_reg:x2; val_offset:27060*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27060*FLEN/8, x3, x1, x4) + +inst_9055: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfe00; +op3val:0x83ff; valaddr_reg:x2; val_offset:27063*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27063*FLEN/8, x3, x1, x4) + +inst_9056: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfe00; +op3val:0x400; valaddr_reg:x2; val_offset:27066*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27066*FLEN/8, x3, x1, x4) + +inst_9057: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfe00; +op3val:0x8400; valaddr_reg:x2; val_offset:27069*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27069*FLEN/8, x3, x1, x4) + +inst_9058: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfe00; +op3val:0x401; valaddr_reg:x2; val_offset:27072*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27072*FLEN/8, x3, x1, x4) + +inst_9059: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfe00; +op3val:0x8455; valaddr_reg:x2; val_offset:27075*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27075*FLEN/8, x3, x1, x4) + +inst_9060: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfe00; +op3val:0x7bff; valaddr_reg:x2; val_offset:27078*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27078*FLEN/8, x3, x1, x4) + +inst_9061: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfe00; +op3val:0xfbff; valaddr_reg:x2; val_offset:27081*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27081*FLEN/8, x3, x1, x4) + +inst_9062: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfe00; +op3val:0x7c00; valaddr_reg:x2; val_offset:27084*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27084*FLEN/8, x3, x1, x4) + +inst_9063: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfe00; +op3val:0xfc00; valaddr_reg:x2; val_offset:27087*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27087*FLEN/8, x3, x1, x4) + +inst_9064: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfe00; +op3val:0x7e00; valaddr_reg:x2; val_offset:27090*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27090*FLEN/8, x3, x1, x4) + +inst_9065: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfe00; +op3val:0xfe00; valaddr_reg:x2; val_offset:27093*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27093*FLEN/8, x3, x1, x4) + +inst_9066: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfe00; +op3val:0x7e01; valaddr_reg:x2; val_offset:27096*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27096*FLEN/8, x3, x1, x4) + +inst_9067: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfe00; +op3val:0xfe55; valaddr_reg:x2; val_offset:27099*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27099*FLEN/8, x3, x1, x4) + +inst_9068: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfe00; +op3val:0x7c01; valaddr_reg:x2; val_offset:27102*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27102*FLEN/8, x3, x1, x4) + +inst_9069: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfe00; +op3val:0xfd55; valaddr_reg:x2; val_offset:27105*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27105*FLEN/8, x3, x1, x4) + +inst_9070: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfe00; +op3val:0x3c00; valaddr_reg:x2; val_offset:27108*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27108*FLEN/8, x3, x1, x4) + +inst_9071: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfe00; +op3val:0xbc00; valaddr_reg:x2; val_offset:27111*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27111*FLEN/8, x3, x1, x4) + +inst_9072: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7e01; +op3val:0x0; valaddr_reg:x2; val_offset:27114*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27114*FLEN/8, x3, x1, x4) + +inst_9073: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7e01; +op3val:0x8000; valaddr_reg:x2; val_offset:27117*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27117*FLEN/8, x3, x1, x4) + +inst_9074: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7e01; +op3val:0x1; valaddr_reg:x2; val_offset:27120*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27120*FLEN/8, x3, x1, x4) + +inst_9075: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7e01; +op3val:0x8001; valaddr_reg:x2; val_offset:27123*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27123*FLEN/8, x3, x1, x4) + +inst_9076: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7e01; +op3val:0x2; valaddr_reg:x2; val_offset:27126*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27126*FLEN/8, x3, x1, x4) + +inst_9077: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7e01; +op3val:0x83fe; valaddr_reg:x2; val_offset:27129*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27129*FLEN/8, x3, x1, x4) + +inst_9078: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7e01; +op3val:0x3ff; valaddr_reg:x2; val_offset:27132*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27132*FLEN/8, x3, x1, x4) + +inst_9079: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7e01; +op3val:0x83ff; valaddr_reg:x2; val_offset:27135*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27135*FLEN/8, x3, x1, x4) + +inst_9080: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7e01; +op3val:0x400; valaddr_reg:x2; val_offset:27138*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27138*FLEN/8, x3, x1, x4) + +inst_9081: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7e01; +op3val:0x8400; valaddr_reg:x2; val_offset:27141*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27141*FLEN/8, x3, x1, x4) + +inst_9082: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7e01; +op3val:0x401; valaddr_reg:x2; val_offset:27144*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27144*FLEN/8, x3, x1, x4) + +inst_9083: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7e01; +op3val:0x8455; valaddr_reg:x2; val_offset:27147*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27147*FLEN/8, x3, x1, x4) + +inst_9084: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7e01; +op3val:0x7bff; valaddr_reg:x2; val_offset:27150*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27150*FLEN/8, x3, x1, x4) + +inst_9085: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7e01; +op3val:0xfbff; valaddr_reg:x2; val_offset:27153*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27153*FLEN/8, x3, x1, x4) + +inst_9086: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7e01; +op3val:0x7c00; valaddr_reg:x2; val_offset:27156*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27156*FLEN/8, x3, x1, x4) + +inst_9087: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7e01; +op3val:0xfc00; valaddr_reg:x2; val_offset:27159*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27159*FLEN/8, x3, x1, x4) + +inst_9088: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7e01; +op3val:0x7e00; valaddr_reg:x2; val_offset:27162*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27162*FLEN/8, x3, x1, x4) + +inst_9089: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7e01; +op3val:0xfe00; valaddr_reg:x2; val_offset:27165*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27165*FLEN/8, x3, x1, x4) + +inst_9090: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7e01; +op3val:0x7e01; valaddr_reg:x2; val_offset:27168*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27168*FLEN/8, x3, x1, x4) + +inst_9091: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7e01; +op3val:0xfe55; valaddr_reg:x2; val_offset:27171*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27171*FLEN/8, x3, x1, x4) + +inst_9092: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7e01; +op3val:0x7c01; valaddr_reg:x2; val_offset:27174*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27174*FLEN/8, x3, x1, x4) + +inst_9093: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7e01; +op3val:0xfd55; valaddr_reg:x2; val_offset:27177*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27177*FLEN/8, x3, x1, x4) + +inst_9094: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7e01; +op3val:0x3c00; valaddr_reg:x2; val_offset:27180*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27180*FLEN/8, x3, x1, x4) + +inst_9095: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7e01; +op3val:0xbc00; valaddr_reg:x2; val_offset:27183*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27183*FLEN/8, x3, x1, x4) + +inst_9096: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfe55; +op3val:0x0; valaddr_reg:x2; val_offset:27186*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27186*FLEN/8, x3, x1, x4) + +inst_9097: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfe55; +op3val:0x8000; valaddr_reg:x2; val_offset:27189*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27189*FLEN/8, x3, x1, x4) + +inst_9098: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfe55; +op3val:0x1; valaddr_reg:x2; val_offset:27192*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27192*FLEN/8, x3, x1, x4) + +inst_9099: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfe55; +op3val:0x8001; valaddr_reg:x2; val_offset:27195*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27195*FLEN/8, x3, x1, x4) + +inst_9100: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfe55; +op3val:0x2; valaddr_reg:x2; val_offset:27198*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27198*FLEN/8, x3, x1, x4) + +inst_9101: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfe55; +op3val:0x83fe; valaddr_reg:x2; val_offset:27201*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27201*FLEN/8, x3, x1, x4) + +inst_9102: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfe55; +op3val:0x3ff; valaddr_reg:x2; val_offset:27204*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27204*FLEN/8, x3, x1, x4) + +inst_9103: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfe55; +op3val:0x83ff; valaddr_reg:x2; val_offset:27207*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27207*FLEN/8, x3, x1, x4) + +inst_9104: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfe55; +op3val:0x400; valaddr_reg:x2; val_offset:27210*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27210*FLEN/8, x3, x1, x4) + +inst_9105: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfe55; +op3val:0x8400; valaddr_reg:x2; val_offset:27213*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27213*FLEN/8, x3, x1, x4) + +inst_9106: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfe55; +op3val:0x401; valaddr_reg:x2; val_offset:27216*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27216*FLEN/8, x3, x1, x4) + +inst_9107: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfe55; +op3val:0x8455; valaddr_reg:x2; val_offset:27219*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27219*FLEN/8, x3, x1, x4) + +inst_9108: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfe55; +op3val:0x7bff; valaddr_reg:x2; val_offset:27222*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27222*FLEN/8, x3, x1, x4) + +inst_9109: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfe55; +op3val:0xfbff; valaddr_reg:x2; val_offset:27225*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27225*FLEN/8, x3, x1, x4) + +inst_9110: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfe55; +op3val:0x7c00; valaddr_reg:x2; val_offset:27228*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27228*FLEN/8, x3, x1, x4) + +inst_9111: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfe55; +op3val:0xfc00; valaddr_reg:x2; val_offset:27231*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27231*FLEN/8, x3, x1, x4) + +inst_9112: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfe55; +op3val:0x7e00; valaddr_reg:x2; val_offset:27234*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27234*FLEN/8, x3, x1, x4) + +inst_9113: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfe55; +op3val:0xfe00; valaddr_reg:x2; val_offset:27237*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27237*FLEN/8, x3, x1, x4) + +inst_9114: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfe55; +op3val:0x7e01; valaddr_reg:x2; val_offset:27240*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27240*FLEN/8, x3, x1, x4) + +inst_9115: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfe55; +op3val:0xfe55; valaddr_reg:x2; val_offset:27243*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27243*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_72) + +inst_9116: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfe55; +op3val:0x7c01; valaddr_reg:x2; val_offset:27246*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27246*FLEN/8, x3, x1, x4) + +inst_9117: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfe55; +op3val:0xfd55; valaddr_reg:x2; val_offset:27249*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27249*FLEN/8, x3, x1, x4) + +inst_9118: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfe55; +op3val:0x3c00; valaddr_reg:x2; val_offset:27252*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27252*FLEN/8, x3, x1, x4) + +inst_9119: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfe55; +op3val:0xbc00; valaddr_reg:x2; val_offset:27255*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27255*FLEN/8, x3, x1, x4) + +inst_9120: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7c01; +op3val:0x0; valaddr_reg:x2; val_offset:27258*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27258*FLEN/8, x3, x1, x4) + +inst_9121: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7c01; +op3val:0x8000; valaddr_reg:x2; val_offset:27261*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27261*FLEN/8, x3, x1, x4) + +inst_9122: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7c01; +op3val:0x1; valaddr_reg:x2; val_offset:27264*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27264*FLEN/8, x3, x1, x4) + +inst_9123: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7c01; +op3val:0x8001; valaddr_reg:x2; val_offset:27267*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27267*FLEN/8, x3, x1, x4) + +inst_9124: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7c01; +op3val:0x2; valaddr_reg:x2; val_offset:27270*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27270*FLEN/8, x3, x1, x4) + +inst_9125: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7c01; +op3val:0x83fe; valaddr_reg:x2; val_offset:27273*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27273*FLEN/8, x3, x1, x4) + +inst_9126: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7c01; +op3val:0x3ff; valaddr_reg:x2; val_offset:27276*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27276*FLEN/8, x3, x1, x4) + +inst_9127: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7c01; +op3val:0x83ff; valaddr_reg:x2; val_offset:27279*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27279*FLEN/8, x3, x1, x4) + +inst_9128: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7c01; +op3val:0x400; valaddr_reg:x2; val_offset:27282*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27282*FLEN/8, x3, x1, x4) + +inst_9129: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7c01; +op3val:0x8400; valaddr_reg:x2; val_offset:27285*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27285*FLEN/8, x3, x1, x4) + +inst_9130: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7c01; +op3val:0x401; valaddr_reg:x2; val_offset:27288*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27288*FLEN/8, x3, x1, x4) + +inst_9131: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7c01; +op3val:0x8455; valaddr_reg:x2; val_offset:27291*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27291*FLEN/8, x3, x1, x4) + +inst_9132: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7c01; +op3val:0x7bff; valaddr_reg:x2; val_offset:27294*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27294*FLEN/8, x3, x1, x4) + +inst_9133: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7c01; +op3val:0xfbff; valaddr_reg:x2; val_offset:27297*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27297*FLEN/8, x3, x1, x4) + +inst_9134: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7c01; +op3val:0x7c00; valaddr_reg:x2; val_offset:27300*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27300*FLEN/8, x3, x1, x4) + +inst_9135: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7c01; +op3val:0xfc00; valaddr_reg:x2; val_offset:27303*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27303*FLEN/8, x3, x1, x4) + +inst_9136: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7c01; +op3val:0x7e00; valaddr_reg:x2; val_offset:27306*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27306*FLEN/8, x3, x1, x4) + +inst_9137: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7c01; +op3val:0xfe00; valaddr_reg:x2; val_offset:27309*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27309*FLEN/8, x3, x1, x4) + +inst_9138: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7c01; +op3val:0x7e01; valaddr_reg:x2; val_offset:27312*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27312*FLEN/8, x3, x1, x4) + +inst_9139: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7c01; +op3val:0xfe55; valaddr_reg:x2; val_offset:27315*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27315*FLEN/8, x3, x1, x4) + +inst_9140: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7c01; +op3val:0x7c01; valaddr_reg:x2; val_offset:27318*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27318*FLEN/8, x3, x1, x4) + +inst_9141: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7c01; +op3val:0xfd55; valaddr_reg:x2; val_offset:27321*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27321*FLEN/8, x3, x1, x4) + +inst_9142: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7c01; +op3val:0x3c00; valaddr_reg:x2; val_offset:27324*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27324*FLEN/8, x3, x1, x4) + +inst_9143: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x7c01; +op3val:0xbc00; valaddr_reg:x2; val_offset:27327*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27327*FLEN/8, x3, x1, x4) + +inst_9144: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfd55; +op3val:0x0; valaddr_reg:x2; val_offset:27330*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27330*FLEN/8, x3, x1, x4) + +inst_9145: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfd55; +op3val:0x8000; valaddr_reg:x2; val_offset:27333*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27333*FLEN/8, x3, x1, x4) + +inst_9146: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfd55; +op3val:0x1; valaddr_reg:x2; val_offset:27336*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27336*FLEN/8, x3, x1, x4) + +inst_9147: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfd55; +op3val:0x8001; valaddr_reg:x2; val_offset:27339*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27339*FLEN/8, x3, x1, x4) + +inst_9148: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfd55; +op3val:0x2; valaddr_reg:x2; val_offset:27342*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27342*FLEN/8, x3, x1, x4) + +inst_9149: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfd55; +op3val:0x83fe; valaddr_reg:x2; val_offset:27345*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27345*FLEN/8, x3, x1, x4) + +inst_9150: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfd55; +op3val:0x3ff; valaddr_reg:x2; val_offset:27348*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27348*FLEN/8, x3, x1, x4) + +inst_9151: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfd55; +op3val:0x83ff; valaddr_reg:x2; val_offset:27351*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27351*FLEN/8, x3, x1, x4) + +inst_9152: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfd55; +op3val:0x400; valaddr_reg:x2; val_offset:27354*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27354*FLEN/8, x3, x1, x4) + +inst_9153: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfd55; +op3val:0x8400; valaddr_reg:x2; val_offset:27357*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27357*FLEN/8, x3, x1, x4) + +inst_9154: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfd55; +op3val:0x401; valaddr_reg:x2; val_offset:27360*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27360*FLEN/8, x3, x1, x4) + +inst_9155: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfd55; +op3val:0x8455; valaddr_reg:x2; val_offset:27363*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27363*FLEN/8, x3, x1, x4) + +inst_9156: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfd55; +op3val:0x7bff; valaddr_reg:x2; val_offset:27366*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27366*FLEN/8, x3, x1, x4) + +inst_9157: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfd55; +op3val:0xfbff; valaddr_reg:x2; val_offset:27369*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27369*FLEN/8, x3, x1, x4) + +inst_9158: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfd55; +op3val:0x7c00; valaddr_reg:x2; val_offset:27372*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27372*FLEN/8, x3, x1, x4) + +inst_9159: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfd55; +op3val:0xfc00; valaddr_reg:x2; val_offset:27375*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27375*FLEN/8, x3, x1, x4) + +inst_9160: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfd55; +op3val:0x7e00; valaddr_reg:x2; val_offset:27378*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27378*FLEN/8, x3, x1, x4) + +inst_9161: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfd55; +op3val:0xfe00; valaddr_reg:x2; val_offset:27381*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27381*FLEN/8, x3, x1, x4) + +inst_9162: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfd55; +op3val:0x7e01; valaddr_reg:x2; val_offset:27384*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27384*FLEN/8, x3, x1, x4) + +inst_9163: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfd55; +op3val:0xfe55; valaddr_reg:x2; val_offset:27387*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27387*FLEN/8, x3, x1, x4) + +inst_9164: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfd55; +op3val:0x7c01; valaddr_reg:x2; val_offset:27390*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27390*FLEN/8, x3, x1, x4) + +inst_9165: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfd55; +op3val:0xfd55; valaddr_reg:x2; val_offset:27393*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27393*FLEN/8, x3, x1, x4) + +inst_9166: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfd55; +op3val:0x3c00; valaddr_reg:x2; val_offset:27396*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27396*FLEN/8, x3, x1, x4) + +inst_9167: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xfd55; +op3val:0xbc00; valaddr_reg:x2; val_offset:27399*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27399*FLEN/8, x3, x1, x4) + +inst_9168: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x3c00; +op3val:0x0; valaddr_reg:x2; val_offset:27402*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27402*FLEN/8, x3, x1, x4) + +inst_9169: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x3c00; +op3val:0x8000; valaddr_reg:x2; val_offset:27405*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27405*FLEN/8, x3, x1, x4) + +inst_9170: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x3c00; +op3val:0x1; valaddr_reg:x2; val_offset:27408*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27408*FLEN/8, x3, x1, x4) + +inst_9171: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x3c00; +op3val:0x8001; valaddr_reg:x2; val_offset:27411*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27411*FLEN/8, x3, x1, x4) + +inst_9172: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x3c00; +op3val:0x2; valaddr_reg:x2; val_offset:27414*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27414*FLEN/8, x3, x1, x4) + +inst_9173: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x3c00; +op3val:0x83fe; valaddr_reg:x2; val_offset:27417*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27417*FLEN/8, x3, x1, x4) + +inst_9174: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x3c00; +op3val:0x3ff; valaddr_reg:x2; val_offset:27420*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27420*FLEN/8, x3, x1, x4) + +inst_9175: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x3c00; +op3val:0x83ff; valaddr_reg:x2; val_offset:27423*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27423*FLEN/8, x3, x1, x4) + +inst_9176: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x3c00; +op3val:0x400; valaddr_reg:x2; val_offset:27426*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27426*FLEN/8, x3, x1, x4) + +inst_9177: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x3c00; +op3val:0x8400; valaddr_reg:x2; val_offset:27429*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27429*FLEN/8, x3, x1, x4) + +inst_9178: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x3c00; +op3val:0x401; valaddr_reg:x2; val_offset:27432*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27432*FLEN/8, x3, x1, x4) + +inst_9179: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x3c00; +op3val:0x8455; valaddr_reg:x2; val_offset:27435*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27435*FLEN/8, x3, x1, x4) + +inst_9180: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x3c00; +op3val:0x7bff; valaddr_reg:x2; val_offset:27438*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27438*FLEN/8, x3, x1, x4) + +inst_9181: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x3c00; +op3val:0xfbff; valaddr_reg:x2; val_offset:27441*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27441*FLEN/8, x3, x1, x4) + +inst_9182: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x3c00; +op3val:0x7c00; valaddr_reg:x2; val_offset:27444*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27444*FLEN/8, x3, x1, x4) + +inst_9183: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x3c00; +op3val:0xfc00; valaddr_reg:x2; val_offset:27447*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27447*FLEN/8, x3, x1, x4) + +inst_9184: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x3c00; +op3val:0x7e00; valaddr_reg:x2; val_offset:27450*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27450*FLEN/8, x3, x1, x4) + +inst_9185: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x3c00; +op3val:0xfe00; valaddr_reg:x2; val_offset:27453*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27453*FLEN/8, x3, x1, x4) + +inst_9186: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x3c00; +op3val:0x7e01; valaddr_reg:x2; val_offset:27456*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27456*FLEN/8, x3, x1, x4) + +inst_9187: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x3c00; +op3val:0xfe55; valaddr_reg:x2; val_offset:27459*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27459*FLEN/8, x3, x1, x4) + +inst_9188: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x3c00; +op3val:0x7c01; valaddr_reg:x2; val_offset:27462*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27462*FLEN/8, x3, x1, x4) + +inst_9189: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x3c00; +op3val:0xfd55; valaddr_reg:x2; val_offset:27465*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27465*FLEN/8, x3, x1, x4) + +inst_9190: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x3c00; +op3val:0x3c00; valaddr_reg:x2; val_offset:27468*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27468*FLEN/8, x3, x1, x4) + +inst_9191: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0x3c00; +op3val:0xbc00; valaddr_reg:x2; val_offset:27471*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27471*FLEN/8, x3, x1, x4) + +inst_9192: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xbc00; +op3val:0x0; valaddr_reg:x2; val_offset:27474*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27474*FLEN/8, x3, x1, x4) + +inst_9193: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xbc00; +op3val:0x8000; valaddr_reg:x2; val_offset:27477*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27477*FLEN/8, x3, x1, x4) + +inst_9194: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xbc00; +op3val:0x1; valaddr_reg:x2; val_offset:27480*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27480*FLEN/8, x3, x1, x4) + +inst_9195: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xbc00; +op3val:0x8001; valaddr_reg:x2; val_offset:27483*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27483*FLEN/8, x3, x1, x4) + +inst_9196: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xbc00; +op3val:0x2; valaddr_reg:x2; val_offset:27486*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27486*FLEN/8, x3, x1, x4) + +inst_9197: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xbc00; +op3val:0x83fe; valaddr_reg:x2; val_offset:27489*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27489*FLEN/8, x3, x1, x4) + +inst_9198: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xbc00; +op3val:0x3ff; valaddr_reg:x2; val_offset:27492*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27492*FLEN/8, x3, x1, x4) + +inst_9199: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xbc00; +op3val:0x83ff; valaddr_reg:x2; val_offset:27495*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27495*FLEN/8, x3, x1, x4) + +inst_9200: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xbc00; +op3val:0x400; valaddr_reg:x2; val_offset:27498*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27498*FLEN/8, x3, x1, x4) + +inst_9201: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xbc00; +op3val:0x8400; valaddr_reg:x2; val_offset:27501*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27501*FLEN/8, x3, x1, x4) + +inst_9202: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xbc00; +op3val:0x401; valaddr_reg:x2; val_offset:27504*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27504*FLEN/8, x3, x1, x4) + +inst_9203: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xbc00; +op3val:0x8455; valaddr_reg:x2; val_offset:27507*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27507*FLEN/8, x3, x1, x4) + +inst_9204: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xbc00; +op3val:0x7bff; valaddr_reg:x2; val_offset:27510*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27510*FLEN/8, x3, x1, x4) + +inst_9205: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xbc00; +op3val:0xfbff; valaddr_reg:x2; val_offset:27513*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27513*FLEN/8, x3, x1, x4) + +inst_9206: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xbc00; +op3val:0x7c00; valaddr_reg:x2; val_offset:27516*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27516*FLEN/8, x3, x1, x4) + +inst_9207: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xbc00; +op3val:0xfc00; valaddr_reg:x2; val_offset:27519*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27519*FLEN/8, x3, x1, x4) + +inst_9208: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xbc00; +op3val:0x7e00; valaddr_reg:x2; val_offset:27522*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27522*FLEN/8, x3, x1, x4) + +inst_9209: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xbc00; +op3val:0xfe00; valaddr_reg:x2; val_offset:27525*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27525*FLEN/8, x3, x1, x4) + +inst_9210: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xbc00; +op3val:0x7e01; valaddr_reg:x2; val_offset:27528*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27528*FLEN/8, x3, x1, x4) + +inst_9211: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xbc00; +op3val:0xfe55; valaddr_reg:x2; val_offset:27531*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27531*FLEN/8, x3, x1, x4) + +inst_9212: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xbc00; +op3val:0x7c01; valaddr_reg:x2; val_offset:27534*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27534*FLEN/8, x3, x1, x4) + +inst_9213: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xbc00; +op3val:0xfd55; valaddr_reg:x2; val_offset:27537*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27537*FLEN/8, x3, x1, x4) + +inst_9214: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xbc00; +op3val:0x3c00; valaddr_reg:x2; val_offset:27540*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27540*FLEN/8, x3, x1, x4) + +inst_9215: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfc00; op2val:0xbc00; +op3val:0xbc00; valaddr_reg:x2; val_offset:27543*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27543*FLEN/8, x3, x1, x4) + +inst_9216: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x0; +op3val:0x0; valaddr_reg:x2; val_offset:27546*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27546*FLEN/8, x3, x1, x4) + +inst_9217: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x0; +op3val:0x8000; valaddr_reg:x2; val_offset:27549*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27549*FLEN/8, x3, x1, x4) + +inst_9218: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x0; +op3val:0x1; valaddr_reg:x2; val_offset:27552*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27552*FLEN/8, x3, x1, x4) + +inst_9219: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x0; +op3val:0x8001; valaddr_reg:x2; val_offset:27555*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27555*FLEN/8, x3, x1, x4) + +inst_9220: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x0; +op3val:0x2; valaddr_reg:x2; val_offset:27558*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27558*FLEN/8, x3, x1, x4) + +inst_9221: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x0; +op3val:0x83fe; valaddr_reg:x2; val_offset:27561*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27561*FLEN/8, x3, x1, x4) + +inst_9222: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x0; +op3val:0x3ff; valaddr_reg:x2; val_offset:27564*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27564*FLEN/8, x3, x1, x4) + +inst_9223: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x0; +op3val:0x83ff; valaddr_reg:x2; val_offset:27567*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27567*FLEN/8, x3, x1, x4) + +inst_9224: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x0; +op3val:0x400; valaddr_reg:x2; val_offset:27570*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27570*FLEN/8, x3, x1, x4) + +inst_9225: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x0; +op3val:0x8400; valaddr_reg:x2; val_offset:27573*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27573*FLEN/8, x3, x1, x4) + +inst_9226: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x0; +op3val:0x401; valaddr_reg:x2; val_offset:27576*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27576*FLEN/8, x3, x1, x4) + +inst_9227: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x0; +op3val:0x8455; valaddr_reg:x2; val_offset:27579*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27579*FLEN/8, x3, x1, x4) + +inst_9228: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x0; +op3val:0x7bff; valaddr_reg:x2; val_offset:27582*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27582*FLEN/8, x3, x1, x4) + +inst_9229: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x0; +op3val:0xfbff; valaddr_reg:x2; val_offset:27585*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27585*FLEN/8, x3, x1, x4) + +inst_9230: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x0; +op3val:0x7c00; valaddr_reg:x2; val_offset:27588*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27588*FLEN/8, x3, x1, x4) + +inst_9231: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x0; +op3val:0xfc00; valaddr_reg:x2; val_offset:27591*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27591*FLEN/8, x3, x1, x4) + +inst_9232: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x0; +op3val:0x7e00; valaddr_reg:x2; val_offset:27594*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27594*FLEN/8, x3, x1, x4) + +inst_9233: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x0; +op3val:0xfe00; valaddr_reg:x2; val_offset:27597*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27597*FLEN/8, x3, x1, x4) + +inst_9234: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x0; +op3val:0x7e01; valaddr_reg:x2; val_offset:27600*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27600*FLEN/8, x3, x1, x4) + +inst_9235: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x0; +op3val:0xfe55; valaddr_reg:x2; val_offset:27603*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27603*FLEN/8, x3, x1, x4) + +inst_9236: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x0; +op3val:0x7c01; valaddr_reg:x2; val_offset:27606*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27606*FLEN/8, x3, x1, x4) + +inst_9237: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x0; +op3val:0xfd55; valaddr_reg:x2; val_offset:27609*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27609*FLEN/8, x3, x1, x4) + +inst_9238: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x0; +op3val:0x3c00; valaddr_reg:x2; val_offset:27612*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27612*FLEN/8, x3, x1, x4) + +inst_9239: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x0; +op3val:0xbc00; valaddr_reg:x2; val_offset:27615*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27615*FLEN/8, x3, x1, x4) + +inst_9240: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8000; +op3val:0x0; valaddr_reg:x2; val_offset:27618*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27618*FLEN/8, x3, x1, x4) + +inst_9241: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8000; +op3val:0x8000; valaddr_reg:x2; val_offset:27621*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27621*FLEN/8, x3, x1, x4) + +inst_9242: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8000; +op3val:0x1; valaddr_reg:x2; val_offset:27624*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27624*FLEN/8, x3, x1, x4) + +inst_9243: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8000; +op3val:0x8001; valaddr_reg:x2; val_offset:27627*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27627*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_73) + +inst_9244: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8000; +op3val:0x2; valaddr_reg:x2; val_offset:27630*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27630*FLEN/8, x3, x1, x4) + +inst_9245: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8000; +op3val:0x83fe; valaddr_reg:x2; val_offset:27633*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27633*FLEN/8, x3, x1, x4) + +inst_9246: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8000; +op3val:0x3ff; valaddr_reg:x2; val_offset:27636*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27636*FLEN/8, x3, x1, x4) + +inst_9247: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8000; +op3val:0x83ff; valaddr_reg:x2; val_offset:27639*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27639*FLEN/8, x3, x1, x4) + +inst_9248: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8000; +op3val:0x400; valaddr_reg:x2; val_offset:27642*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27642*FLEN/8, x3, x1, x4) + +inst_9249: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8000; +op3val:0x8400; valaddr_reg:x2; val_offset:27645*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27645*FLEN/8, x3, x1, x4) + +inst_9250: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8000; +op3val:0x401; valaddr_reg:x2; val_offset:27648*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27648*FLEN/8, x3, x1, x4) + +inst_9251: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8000; +op3val:0x8455; valaddr_reg:x2; val_offset:27651*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27651*FLEN/8, x3, x1, x4) + +inst_9252: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x2; val_offset:27654*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27654*FLEN/8, x3, x1, x4) + +inst_9253: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x2; val_offset:27657*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27657*FLEN/8, x3, x1, x4) + +inst_9254: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8000; +op3val:0x7c00; valaddr_reg:x2; val_offset:27660*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27660*FLEN/8, x3, x1, x4) + +inst_9255: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8000; +op3val:0xfc00; valaddr_reg:x2; val_offset:27663*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27663*FLEN/8, x3, x1, x4) + +inst_9256: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8000; +op3val:0x7e00; valaddr_reg:x2; val_offset:27666*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27666*FLEN/8, x3, x1, x4) + +inst_9257: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8000; +op3val:0xfe00; valaddr_reg:x2; val_offset:27669*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27669*FLEN/8, x3, x1, x4) + +inst_9258: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8000; +op3val:0x7e01; valaddr_reg:x2; val_offset:27672*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27672*FLEN/8, x3, x1, x4) + +inst_9259: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8000; +op3val:0xfe55; valaddr_reg:x2; val_offset:27675*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27675*FLEN/8, x3, x1, x4) + +inst_9260: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8000; +op3val:0x7c01; valaddr_reg:x2; val_offset:27678*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27678*FLEN/8, x3, x1, x4) + +inst_9261: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8000; +op3val:0xfd55; valaddr_reg:x2; val_offset:27681*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27681*FLEN/8, x3, x1, x4) + +inst_9262: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8000; +op3val:0x3c00; valaddr_reg:x2; val_offset:27684*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27684*FLEN/8, x3, x1, x4) + +inst_9263: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8000; +op3val:0xbc00; valaddr_reg:x2; val_offset:27687*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27687*FLEN/8, x3, x1, x4) + +inst_9264: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x1; +op3val:0x0; valaddr_reg:x2; val_offset:27690*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27690*FLEN/8, x3, x1, x4) + +inst_9265: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x1; +op3val:0x8000; valaddr_reg:x2; val_offset:27693*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27693*FLEN/8, x3, x1, x4) + +inst_9266: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x1; +op3val:0x1; valaddr_reg:x2; val_offset:27696*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27696*FLEN/8, x3, x1, x4) + +inst_9267: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x1; +op3val:0x8001; valaddr_reg:x2; val_offset:27699*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27699*FLEN/8, x3, x1, x4) + +inst_9268: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x1; +op3val:0x2; valaddr_reg:x2; val_offset:27702*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27702*FLEN/8, x3, x1, x4) + +inst_9269: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x1; +op3val:0x83fe; valaddr_reg:x2; val_offset:27705*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27705*FLEN/8, x3, x1, x4) + +inst_9270: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x1; +op3val:0x3ff; valaddr_reg:x2; val_offset:27708*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27708*FLEN/8, x3, x1, x4) + +inst_9271: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x1; +op3val:0x83ff; valaddr_reg:x2; val_offset:27711*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27711*FLEN/8, x3, x1, x4) + +inst_9272: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x1; +op3val:0x400; valaddr_reg:x2; val_offset:27714*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27714*FLEN/8, x3, x1, x4) + +inst_9273: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x1; +op3val:0x8400; valaddr_reg:x2; val_offset:27717*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27717*FLEN/8, x3, x1, x4) + +inst_9274: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x1; +op3val:0x401; valaddr_reg:x2; val_offset:27720*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27720*FLEN/8, x3, x1, x4) + +inst_9275: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x1; +op3val:0x8455; valaddr_reg:x2; val_offset:27723*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27723*FLEN/8, x3, x1, x4) + +inst_9276: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x1; +op3val:0x7bff; valaddr_reg:x2; val_offset:27726*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27726*FLEN/8, x3, x1, x4) + +inst_9277: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x1; +op3val:0xfbff; valaddr_reg:x2; val_offset:27729*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27729*FLEN/8, x3, x1, x4) + +inst_9278: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x1; +op3val:0x7c00; valaddr_reg:x2; val_offset:27732*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27732*FLEN/8, x3, x1, x4) + +inst_9279: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x1; +op3val:0xfc00; valaddr_reg:x2; val_offset:27735*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27735*FLEN/8, x3, x1, x4) + +inst_9280: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x1; +op3val:0x7e00; valaddr_reg:x2; val_offset:27738*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27738*FLEN/8, x3, x1, x4) + +inst_9281: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x1; +op3val:0xfe00; valaddr_reg:x2; val_offset:27741*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27741*FLEN/8, x3, x1, x4) + +inst_9282: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x1; +op3val:0x7e01; valaddr_reg:x2; val_offset:27744*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27744*FLEN/8, x3, x1, x4) + +inst_9283: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x1; +op3val:0xfe55; valaddr_reg:x2; val_offset:27747*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27747*FLEN/8, x3, x1, x4) + +inst_9284: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x1; +op3val:0x7c01; valaddr_reg:x2; val_offset:27750*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27750*FLEN/8, x3, x1, x4) + +inst_9285: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x1; +op3val:0xfd55; valaddr_reg:x2; val_offset:27753*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27753*FLEN/8, x3, x1, x4) + +inst_9286: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x1; +op3val:0x3c00; valaddr_reg:x2; val_offset:27756*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27756*FLEN/8, x3, x1, x4) + +inst_9287: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x1; +op3val:0xbc00; valaddr_reg:x2; val_offset:27759*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27759*FLEN/8, x3, x1, x4) + +inst_9288: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8001; +op3val:0x0; valaddr_reg:x2; val_offset:27762*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27762*FLEN/8, x3, x1, x4) + +inst_9289: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8001; +op3val:0x8000; valaddr_reg:x2; val_offset:27765*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27765*FLEN/8, x3, x1, x4) + +inst_9290: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8001; +op3val:0x1; valaddr_reg:x2; val_offset:27768*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27768*FLEN/8, x3, x1, x4) + +inst_9291: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8001; +op3val:0x8001; valaddr_reg:x2; val_offset:27771*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27771*FLEN/8, x3, x1, x4) + +inst_9292: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8001; +op3val:0x2; valaddr_reg:x2; val_offset:27774*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27774*FLEN/8, x3, x1, x4) + +inst_9293: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8001; +op3val:0x83fe; valaddr_reg:x2; val_offset:27777*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27777*FLEN/8, x3, x1, x4) + +inst_9294: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8001; +op3val:0x3ff; valaddr_reg:x2; val_offset:27780*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27780*FLEN/8, x3, x1, x4) + +inst_9295: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8001; +op3val:0x83ff; valaddr_reg:x2; val_offset:27783*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27783*FLEN/8, x3, x1, x4) + +inst_9296: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8001; +op3val:0x400; valaddr_reg:x2; val_offset:27786*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27786*FLEN/8, x3, x1, x4) + +inst_9297: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8001; +op3val:0x8400; valaddr_reg:x2; val_offset:27789*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27789*FLEN/8, x3, x1, x4) + +inst_9298: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8001; +op3val:0x401; valaddr_reg:x2; val_offset:27792*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27792*FLEN/8, x3, x1, x4) + +inst_9299: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8001; +op3val:0x8455; valaddr_reg:x2; val_offset:27795*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27795*FLEN/8, x3, x1, x4) + +inst_9300: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8001; +op3val:0x7bff; valaddr_reg:x2; val_offset:27798*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27798*FLEN/8, x3, x1, x4) + +inst_9301: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8001; +op3val:0xfbff; valaddr_reg:x2; val_offset:27801*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27801*FLEN/8, x3, x1, x4) + +inst_9302: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8001; +op3val:0x7c00; valaddr_reg:x2; val_offset:27804*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27804*FLEN/8, x3, x1, x4) + +inst_9303: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8001; +op3val:0xfc00; valaddr_reg:x2; val_offset:27807*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27807*FLEN/8, x3, x1, x4) + +inst_9304: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8001; +op3val:0x7e00; valaddr_reg:x2; val_offset:27810*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27810*FLEN/8, x3, x1, x4) + +inst_9305: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8001; +op3val:0xfe00; valaddr_reg:x2; val_offset:27813*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27813*FLEN/8, x3, x1, x4) + +inst_9306: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8001; +op3val:0x7e01; valaddr_reg:x2; val_offset:27816*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27816*FLEN/8, x3, x1, x4) + +inst_9307: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8001; +op3val:0xfe55; valaddr_reg:x2; val_offset:27819*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27819*FLEN/8, x3, x1, x4) + +inst_9308: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8001; +op3val:0x7c01; valaddr_reg:x2; val_offset:27822*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27822*FLEN/8, x3, x1, x4) + +inst_9309: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8001; +op3val:0xfd55; valaddr_reg:x2; val_offset:27825*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27825*FLEN/8, x3, x1, x4) + +inst_9310: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8001; +op3val:0x3c00; valaddr_reg:x2; val_offset:27828*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27828*FLEN/8, x3, x1, x4) + +inst_9311: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8001; +op3val:0xbc00; valaddr_reg:x2; val_offset:27831*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27831*FLEN/8, x3, x1, x4) + +inst_9312: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x2; +op3val:0x0; valaddr_reg:x2; val_offset:27834*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27834*FLEN/8, x3, x1, x4) + +inst_9313: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x2; +op3val:0x8000; valaddr_reg:x2; val_offset:27837*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27837*FLEN/8, x3, x1, x4) + +inst_9314: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x2; +op3val:0x1; valaddr_reg:x2; val_offset:27840*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27840*FLEN/8, x3, x1, x4) + +inst_9315: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x2; +op3val:0x8001; valaddr_reg:x2; val_offset:27843*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27843*FLEN/8, x3, x1, x4) + +inst_9316: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x2; +op3val:0x2; valaddr_reg:x2; val_offset:27846*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27846*FLEN/8, x3, x1, x4) + +inst_9317: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x2; +op3val:0x83fe; valaddr_reg:x2; val_offset:27849*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27849*FLEN/8, x3, x1, x4) + +inst_9318: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x2; +op3val:0x3ff; valaddr_reg:x2; val_offset:27852*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27852*FLEN/8, x3, x1, x4) + +inst_9319: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x2; +op3val:0x83ff; valaddr_reg:x2; val_offset:27855*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27855*FLEN/8, x3, x1, x4) + +inst_9320: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x2; +op3val:0x400; valaddr_reg:x2; val_offset:27858*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27858*FLEN/8, x3, x1, x4) + +inst_9321: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x2; +op3val:0x8400; valaddr_reg:x2; val_offset:27861*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27861*FLEN/8, x3, x1, x4) + +inst_9322: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x2; +op3val:0x401; valaddr_reg:x2; val_offset:27864*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27864*FLEN/8, x3, x1, x4) + +inst_9323: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x2; +op3val:0x8455; valaddr_reg:x2; val_offset:27867*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27867*FLEN/8, x3, x1, x4) + +inst_9324: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x2; +op3val:0x7bff; valaddr_reg:x2; val_offset:27870*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27870*FLEN/8, x3, x1, x4) + +inst_9325: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x2; +op3val:0xfbff; valaddr_reg:x2; val_offset:27873*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27873*FLEN/8, x3, x1, x4) + +inst_9326: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x2; +op3val:0x7c00; valaddr_reg:x2; val_offset:27876*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27876*FLEN/8, x3, x1, x4) + +inst_9327: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x2; +op3val:0xfc00; valaddr_reg:x2; val_offset:27879*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27879*FLEN/8, x3, x1, x4) + +inst_9328: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x2; +op3val:0x7e00; valaddr_reg:x2; val_offset:27882*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27882*FLEN/8, x3, x1, x4) + +inst_9329: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x2; +op3val:0xfe00; valaddr_reg:x2; val_offset:27885*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27885*FLEN/8, x3, x1, x4) + +inst_9330: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x2; +op3val:0x7e01; valaddr_reg:x2; val_offset:27888*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27888*FLEN/8, x3, x1, x4) + +inst_9331: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x2; +op3val:0xfe55; valaddr_reg:x2; val_offset:27891*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27891*FLEN/8, x3, x1, x4) + +inst_9332: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x2; +op3val:0x7c01; valaddr_reg:x2; val_offset:27894*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27894*FLEN/8, x3, x1, x4) + +inst_9333: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x2; +op3val:0xfd55; valaddr_reg:x2; val_offset:27897*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27897*FLEN/8, x3, x1, x4) + +inst_9334: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x2; +op3val:0x3c00; valaddr_reg:x2; val_offset:27900*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27900*FLEN/8, x3, x1, x4) + +inst_9335: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x2; +op3val:0xbc00; valaddr_reg:x2; val_offset:27903*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27903*FLEN/8, x3, x1, x4) + +inst_9336: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x83fe; +op3val:0x0; valaddr_reg:x2; val_offset:27906*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27906*FLEN/8, x3, x1, x4) + +inst_9337: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x83fe; +op3val:0x8000; valaddr_reg:x2; val_offset:27909*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27909*FLEN/8, x3, x1, x4) + +inst_9338: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x83fe; +op3val:0x1; valaddr_reg:x2; val_offset:27912*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27912*FLEN/8, x3, x1, x4) + +inst_9339: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x83fe; +op3val:0x8001; valaddr_reg:x2; val_offset:27915*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27915*FLEN/8, x3, x1, x4) + +inst_9340: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x83fe; +op3val:0x2; valaddr_reg:x2; val_offset:27918*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27918*FLEN/8, x3, x1, x4) + +inst_9341: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x83fe; +op3val:0x83fe; valaddr_reg:x2; val_offset:27921*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27921*FLEN/8, x3, x1, x4) + +inst_9342: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x83fe; +op3val:0x3ff; valaddr_reg:x2; val_offset:27924*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27924*FLEN/8, x3, x1, x4) + +inst_9343: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x83fe; +op3val:0x83ff; valaddr_reg:x2; val_offset:27927*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27927*FLEN/8, x3, x1, x4) + +inst_9344: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x83fe; +op3val:0x400; valaddr_reg:x2; val_offset:27930*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27930*FLEN/8, x3, x1, x4) + +inst_9345: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x83fe; +op3val:0x8400; valaddr_reg:x2; val_offset:27933*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27933*FLEN/8, x3, x1, x4) + +inst_9346: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x83fe; +op3val:0x401; valaddr_reg:x2; val_offset:27936*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27936*FLEN/8, x3, x1, x4) + +inst_9347: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x83fe; +op3val:0x8455; valaddr_reg:x2; val_offset:27939*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27939*FLEN/8, x3, x1, x4) + +inst_9348: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x83fe; +op3val:0x7bff; valaddr_reg:x2; val_offset:27942*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27942*FLEN/8, x3, x1, x4) + +inst_9349: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x83fe; +op3val:0xfbff; valaddr_reg:x2; val_offset:27945*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27945*FLEN/8, x3, x1, x4) + +inst_9350: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x83fe; +op3val:0x7c00; valaddr_reg:x2; val_offset:27948*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27948*FLEN/8, x3, x1, x4) + +inst_9351: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x83fe; +op3val:0xfc00; valaddr_reg:x2; val_offset:27951*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27951*FLEN/8, x3, x1, x4) + +inst_9352: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x83fe; +op3val:0x7e00; valaddr_reg:x2; val_offset:27954*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27954*FLEN/8, x3, x1, x4) + +inst_9353: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x83fe; +op3val:0xfe00; valaddr_reg:x2; val_offset:27957*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27957*FLEN/8, x3, x1, x4) + +inst_9354: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x83fe; +op3val:0x7e01; valaddr_reg:x2; val_offset:27960*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27960*FLEN/8, x3, x1, x4) + +inst_9355: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x83fe; +op3val:0xfe55; valaddr_reg:x2; val_offset:27963*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27963*FLEN/8, x3, x1, x4) + +inst_9356: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x83fe; +op3val:0x7c01; valaddr_reg:x2; val_offset:27966*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27966*FLEN/8, x3, x1, x4) + +inst_9357: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x83fe; +op3val:0xfd55; valaddr_reg:x2; val_offset:27969*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27969*FLEN/8, x3, x1, x4) + +inst_9358: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x83fe; +op3val:0x3c00; valaddr_reg:x2; val_offset:27972*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27972*FLEN/8, x3, x1, x4) + +inst_9359: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x83fe; +op3val:0xbc00; valaddr_reg:x2; val_offset:27975*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27975*FLEN/8, x3, x1, x4) + +inst_9360: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x3ff; +op3val:0x0; valaddr_reg:x2; val_offset:27978*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27978*FLEN/8, x3, x1, x4) + +inst_9361: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x3ff; +op3val:0x8000; valaddr_reg:x2; val_offset:27981*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27981*FLEN/8, x3, x1, x4) + +inst_9362: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x3ff; +op3val:0x1; valaddr_reg:x2; val_offset:27984*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27984*FLEN/8, x3, x1, x4) + +inst_9363: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x3ff; +op3val:0x8001; valaddr_reg:x2; val_offset:27987*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27987*FLEN/8, x3, x1, x4) + +inst_9364: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x3ff; +op3val:0x2; valaddr_reg:x2; val_offset:27990*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27990*FLEN/8, x3, x1, x4) + +inst_9365: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x3ff; +op3val:0x83fe; valaddr_reg:x2; val_offset:27993*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27993*FLEN/8, x3, x1, x4) + +inst_9366: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x3ff; +op3val:0x3ff; valaddr_reg:x2; val_offset:27996*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27996*FLEN/8, x3, x1, x4) + +inst_9367: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x3ff; +op3val:0x83ff; valaddr_reg:x2; val_offset:27999*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27999*FLEN/8, x3, x1, x4) + +inst_9368: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x3ff; +op3val:0x400; valaddr_reg:x2; val_offset:28002*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28002*FLEN/8, x3, x1, x4) + +inst_9369: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x3ff; +op3val:0x8400; valaddr_reg:x2; val_offset:28005*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28005*FLEN/8, x3, x1, x4) + +inst_9370: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x3ff; +op3val:0x401; valaddr_reg:x2; val_offset:28008*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28008*FLEN/8, x3, x1, x4) + +inst_9371: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x3ff; +op3val:0x8455; valaddr_reg:x2; val_offset:28011*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28011*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_74) + +inst_9372: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x3ff; +op3val:0x7bff; valaddr_reg:x2; val_offset:28014*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28014*FLEN/8, x3, x1, x4) + +inst_9373: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x3ff; +op3val:0xfbff; valaddr_reg:x2; val_offset:28017*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28017*FLEN/8, x3, x1, x4) + +inst_9374: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x3ff; +op3val:0x7c00; valaddr_reg:x2; val_offset:28020*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28020*FLEN/8, x3, x1, x4) + +inst_9375: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x3ff; +op3val:0xfc00; valaddr_reg:x2; val_offset:28023*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28023*FLEN/8, x3, x1, x4) + +inst_9376: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x3ff; +op3val:0x7e00; valaddr_reg:x2; val_offset:28026*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28026*FLEN/8, x3, x1, x4) + +inst_9377: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x3ff; +op3val:0xfe00; valaddr_reg:x2; val_offset:28029*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28029*FLEN/8, x3, x1, x4) + +inst_9378: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x3ff; +op3val:0x7e01; valaddr_reg:x2; val_offset:28032*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28032*FLEN/8, x3, x1, x4) + +inst_9379: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x3ff; +op3val:0xfe55; valaddr_reg:x2; val_offset:28035*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28035*FLEN/8, x3, x1, x4) + +inst_9380: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x3ff; +op3val:0x7c01; valaddr_reg:x2; val_offset:28038*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28038*FLEN/8, x3, x1, x4) + +inst_9381: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x3ff; +op3val:0xfd55; valaddr_reg:x2; val_offset:28041*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28041*FLEN/8, x3, x1, x4) + +inst_9382: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x3ff; +op3val:0x3c00; valaddr_reg:x2; val_offset:28044*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28044*FLEN/8, x3, x1, x4) + +inst_9383: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x3ff; +op3val:0xbc00; valaddr_reg:x2; val_offset:28047*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28047*FLEN/8, x3, x1, x4) + +inst_9384: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x83ff; +op3val:0x0; valaddr_reg:x2; val_offset:28050*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28050*FLEN/8, x3, x1, x4) + +inst_9385: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x83ff; +op3val:0x8000; valaddr_reg:x2; val_offset:28053*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28053*FLEN/8, x3, x1, x4) + +inst_9386: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x83ff; +op3val:0x1; valaddr_reg:x2; val_offset:28056*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28056*FLEN/8, x3, x1, x4) + +inst_9387: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x83ff; +op3val:0x8001; valaddr_reg:x2; val_offset:28059*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28059*FLEN/8, x3, x1, x4) + +inst_9388: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x83ff; +op3val:0x2; valaddr_reg:x2; val_offset:28062*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28062*FLEN/8, x3, x1, x4) + +inst_9389: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x83ff; +op3val:0x83fe; valaddr_reg:x2; val_offset:28065*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28065*FLEN/8, x3, x1, x4) + +inst_9390: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x83ff; +op3val:0x3ff; valaddr_reg:x2; val_offset:28068*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28068*FLEN/8, x3, x1, x4) + +inst_9391: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x83ff; +op3val:0x83ff; valaddr_reg:x2; val_offset:28071*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28071*FLEN/8, x3, x1, x4) + +inst_9392: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x83ff; +op3val:0x400; valaddr_reg:x2; val_offset:28074*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28074*FLEN/8, x3, x1, x4) + +inst_9393: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x83ff; +op3val:0x8400; valaddr_reg:x2; val_offset:28077*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28077*FLEN/8, x3, x1, x4) + +inst_9394: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x83ff; +op3val:0x401; valaddr_reg:x2; val_offset:28080*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28080*FLEN/8, x3, x1, x4) + +inst_9395: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x83ff; +op3val:0x8455; valaddr_reg:x2; val_offset:28083*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28083*FLEN/8, x3, x1, x4) + +inst_9396: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x83ff; +op3val:0x7bff; valaddr_reg:x2; val_offset:28086*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28086*FLEN/8, x3, x1, x4) + +inst_9397: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x83ff; +op3val:0xfbff; valaddr_reg:x2; val_offset:28089*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28089*FLEN/8, x3, x1, x4) + +inst_9398: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x83ff; +op3val:0x7c00; valaddr_reg:x2; val_offset:28092*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28092*FLEN/8, x3, x1, x4) + +inst_9399: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x83ff; +op3val:0xfc00; valaddr_reg:x2; val_offset:28095*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28095*FLEN/8, x3, x1, x4) + +inst_9400: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x83ff; +op3val:0x7e00; valaddr_reg:x2; val_offset:28098*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28098*FLEN/8, x3, x1, x4) + +inst_9401: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x83ff; +op3val:0xfe00; valaddr_reg:x2; val_offset:28101*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28101*FLEN/8, x3, x1, x4) + +inst_9402: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x83ff; +op3val:0x7e01; valaddr_reg:x2; val_offset:28104*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28104*FLEN/8, x3, x1, x4) + +inst_9403: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x83ff; +op3val:0xfe55; valaddr_reg:x2; val_offset:28107*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28107*FLEN/8, x3, x1, x4) + +inst_9404: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x83ff; +op3val:0x7c01; valaddr_reg:x2; val_offset:28110*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28110*FLEN/8, x3, x1, x4) + +inst_9405: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x83ff; +op3val:0xfd55; valaddr_reg:x2; val_offset:28113*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28113*FLEN/8, x3, x1, x4) + +inst_9406: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x83ff; +op3val:0x3c00; valaddr_reg:x2; val_offset:28116*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28116*FLEN/8, x3, x1, x4) + +inst_9407: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x83ff; +op3val:0xbc00; valaddr_reg:x2; val_offset:28119*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28119*FLEN/8, x3, x1, x4) + +inst_9408: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x400; +op3val:0x0; valaddr_reg:x2; val_offset:28122*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28122*FLEN/8, x3, x1, x4) + +inst_9409: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x400; +op3val:0x8000; valaddr_reg:x2; val_offset:28125*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28125*FLEN/8, x3, x1, x4) + +inst_9410: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x400; +op3val:0x1; valaddr_reg:x2; val_offset:28128*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28128*FLEN/8, x3, x1, x4) + +inst_9411: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x400; +op3val:0x8001; valaddr_reg:x2; val_offset:28131*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28131*FLEN/8, x3, x1, x4) + +inst_9412: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x400; +op3val:0x2; valaddr_reg:x2; val_offset:28134*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28134*FLEN/8, x3, x1, x4) + +inst_9413: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x400; +op3val:0x83fe; valaddr_reg:x2; val_offset:28137*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28137*FLEN/8, x3, x1, x4) + +inst_9414: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x400; +op3val:0x3ff; valaddr_reg:x2; val_offset:28140*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28140*FLEN/8, x3, x1, x4) + +inst_9415: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x400; +op3val:0x83ff; valaddr_reg:x2; val_offset:28143*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28143*FLEN/8, x3, x1, x4) + +inst_9416: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x400; +op3val:0x400; valaddr_reg:x2; val_offset:28146*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28146*FLEN/8, x3, x1, x4) + +inst_9417: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x400; +op3val:0x8400; valaddr_reg:x2; val_offset:28149*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28149*FLEN/8, x3, x1, x4) + +inst_9418: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x400; +op3val:0x401; valaddr_reg:x2; val_offset:28152*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28152*FLEN/8, x3, x1, x4) + +inst_9419: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x400; +op3val:0x8455; valaddr_reg:x2; val_offset:28155*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28155*FLEN/8, x3, x1, x4) + +inst_9420: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x400; +op3val:0x7bff; valaddr_reg:x2; val_offset:28158*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28158*FLEN/8, x3, x1, x4) + +inst_9421: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x400; +op3val:0xfbff; valaddr_reg:x2; val_offset:28161*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28161*FLEN/8, x3, x1, x4) + +inst_9422: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x400; +op3val:0x7c00; valaddr_reg:x2; val_offset:28164*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28164*FLEN/8, x3, x1, x4) + +inst_9423: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x400; +op3val:0xfc00; valaddr_reg:x2; val_offset:28167*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28167*FLEN/8, x3, x1, x4) + +inst_9424: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x400; +op3val:0x7e00; valaddr_reg:x2; val_offset:28170*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28170*FLEN/8, x3, x1, x4) + +inst_9425: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x400; +op3val:0xfe00; valaddr_reg:x2; val_offset:28173*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28173*FLEN/8, x3, x1, x4) + +inst_9426: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x400; +op3val:0x7e01; valaddr_reg:x2; val_offset:28176*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28176*FLEN/8, x3, x1, x4) + +inst_9427: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x400; +op3val:0xfe55; valaddr_reg:x2; val_offset:28179*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28179*FLEN/8, x3, x1, x4) + +inst_9428: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x400; +op3val:0x7c01; valaddr_reg:x2; val_offset:28182*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28182*FLEN/8, x3, x1, x4) + +inst_9429: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x400; +op3val:0xfd55; valaddr_reg:x2; val_offset:28185*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28185*FLEN/8, x3, x1, x4) + +inst_9430: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x400; +op3val:0x3c00; valaddr_reg:x2; val_offset:28188*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28188*FLEN/8, x3, x1, x4) + +inst_9431: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x400; +op3val:0xbc00; valaddr_reg:x2; val_offset:28191*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28191*FLEN/8, x3, x1, x4) + +inst_9432: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8400; +op3val:0x0; valaddr_reg:x2; val_offset:28194*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28194*FLEN/8, x3, x1, x4) + +inst_9433: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8400; +op3val:0x8000; valaddr_reg:x2; val_offset:28197*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28197*FLEN/8, x3, x1, x4) + +inst_9434: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8400; +op3val:0x1; valaddr_reg:x2; val_offset:28200*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28200*FLEN/8, x3, x1, x4) + +inst_9435: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8400; +op3val:0x8001; valaddr_reg:x2; val_offset:28203*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28203*FLEN/8, x3, x1, x4) + +inst_9436: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8400; +op3val:0x2; valaddr_reg:x2; val_offset:28206*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28206*FLEN/8, x3, x1, x4) + +inst_9437: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8400; +op3val:0x83fe; valaddr_reg:x2; val_offset:28209*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28209*FLEN/8, x3, x1, x4) + +inst_9438: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8400; +op3val:0x3ff; valaddr_reg:x2; val_offset:28212*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28212*FLEN/8, x3, x1, x4) + +inst_9439: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8400; +op3val:0x83ff; valaddr_reg:x2; val_offset:28215*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28215*FLEN/8, x3, x1, x4) + +inst_9440: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8400; +op3val:0x400; valaddr_reg:x2; val_offset:28218*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28218*FLEN/8, x3, x1, x4) + +inst_9441: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8400; +op3val:0x8400; valaddr_reg:x2; val_offset:28221*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28221*FLEN/8, x3, x1, x4) + +inst_9442: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8400; +op3val:0x401; valaddr_reg:x2; val_offset:28224*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28224*FLEN/8, x3, x1, x4) + +inst_9443: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8400; +op3val:0x8455; valaddr_reg:x2; val_offset:28227*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28227*FLEN/8, x3, x1, x4) + +inst_9444: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8400; +op3val:0x7bff; valaddr_reg:x2; val_offset:28230*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28230*FLEN/8, x3, x1, x4) + +inst_9445: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8400; +op3val:0xfbff; valaddr_reg:x2; val_offset:28233*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28233*FLEN/8, x3, x1, x4) + +inst_9446: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8400; +op3val:0x7c00; valaddr_reg:x2; val_offset:28236*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28236*FLEN/8, x3, x1, x4) + +inst_9447: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8400; +op3val:0xfc00; valaddr_reg:x2; val_offset:28239*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28239*FLEN/8, x3, x1, x4) + +inst_9448: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8400; +op3val:0x7e00; valaddr_reg:x2; val_offset:28242*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28242*FLEN/8, x3, x1, x4) + +inst_9449: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8400; +op3val:0xfe00; valaddr_reg:x2; val_offset:28245*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28245*FLEN/8, x3, x1, x4) + +inst_9450: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8400; +op3val:0x7e01; valaddr_reg:x2; val_offset:28248*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28248*FLEN/8, x3, x1, x4) + +inst_9451: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8400; +op3val:0xfe55; valaddr_reg:x2; val_offset:28251*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28251*FLEN/8, x3, x1, x4) + +inst_9452: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8400; +op3val:0x7c01; valaddr_reg:x2; val_offset:28254*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28254*FLEN/8, x3, x1, x4) + +inst_9453: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8400; +op3val:0xfd55; valaddr_reg:x2; val_offset:28257*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28257*FLEN/8, x3, x1, x4) + +inst_9454: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8400; +op3val:0x3c00; valaddr_reg:x2; val_offset:28260*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28260*FLEN/8, x3, x1, x4) + +inst_9455: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8400; +op3val:0xbc00; valaddr_reg:x2; val_offset:28263*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28263*FLEN/8, x3, x1, x4) + +inst_9456: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x401; +op3val:0x0; valaddr_reg:x2; val_offset:28266*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28266*FLEN/8, x3, x1, x4) + +inst_9457: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x401; +op3val:0x8000; valaddr_reg:x2; val_offset:28269*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28269*FLEN/8, x3, x1, x4) + +inst_9458: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x401; +op3val:0x1; valaddr_reg:x2; val_offset:28272*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28272*FLEN/8, x3, x1, x4) + +inst_9459: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x401; +op3val:0x8001; valaddr_reg:x2; val_offset:28275*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28275*FLEN/8, x3, x1, x4) + +inst_9460: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x401; +op3val:0x2; valaddr_reg:x2; val_offset:28278*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28278*FLEN/8, x3, x1, x4) + +inst_9461: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x401; +op3val:0x83fe; valaddr_reg:x2; val_offset:28281*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28281*FLEN/8, x3, x1, x4) + +inst_9462: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x401; +op3val:0x3ff; valaddr_reg:x2; val_offset:28284*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28284*FLEN/8, x3, x1, x4) + +inst_9463: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x401; +op3val:0x83ff; valaddr_reg:x2; val_offset:28287*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28287*FLEN/8, x3, x1, x4) + +inst_9464: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x401; +op3val:0x400; valaddr_reg:x2; val_offset:28290*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28290*FLEN/8, x3, x1, x4) + +inst_9465: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x401; +op3val:0x8400; valaddr_reg:x2; val_offset:28293*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28293*FLEN/8, x3, x1, x4) + +inst_9466: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x401; +op3val:0x401; valaddr_reg:x2; val_offset:28296*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28296*FLEN/8, x3, x1, x4) + +inst_9467: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x401; +op3val:0x8455; valaddr_reg:x2; val_offset:28299*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28299*FLEN/8, x3, x1, x4) + +inst_9468: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x401; +op3val:0x7bff; valaddr_reg:x2; val_offset:28302*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28302*FLEN/8, x3, x1, x4) + +inst_9469: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x401; +op3val:0xfbff; valaddr_reg:x2; val_offset:28305*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28305*FLEN/8, x3, x1, x4) + +inst_9470: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x401; +op3val:0x7c00; valaddr_reg:x2; val_offset:28308*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28308*FLEN/8, x3, x1, x4) + +inst_9471: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x401; +op3val:0xfc00; valaddr_reg:x2; val_offset:28311*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28311*FLEN/8, x3, x1, x4) + +inst_9472: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x401; +op3val:0x7e00; valaddr_reg:x2; val_offset:28314*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28314*FLEN/8, x3, x1, x4) + +inst_9473: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x401; +op3val:0xfe00; valaddr_reg:x2; val_offset:28317*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28317*FLEN/8, x3, x1, x4) + +inst_9474: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x401; +op3val:0x7e01; valaddr_reg:x2; val_offset:28320*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28320*FLEN/8, x3, x1, x4) + +inst_9475: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x401; +op3val:0xfe55; valaddr_reg:x2; val_offset:28323*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28323*FLEN/8, x3, x1, x4) + +inst_9476: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x401; +op3val:0x7c01; valaddr_reg:x2; val_offset:28326*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28326*FLEN/8, x3, x1, x4) + +inst_9477: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x401; +op3val:0xfd55; valaddr_reg:x2; val_offset:28329*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28329*FLEN/8, x3, x1, x4) + +inst_9478: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x401; +op3val:0x3c00; valaddr_reg:x2; val_offset:28332*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28332*FLEN/8, x3, x1, x4) + +inst_9479: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x401; +op3val:0xbc00; valaddr_reg:x2; val_offset:28335*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28335*FLEN/8, x3, x1, x4) + +inst_9480: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8455; +op3val:0x0; valaddr_reg:x2; val_offset:28338*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28338*FLEN/8, x3, x1, x4) + +inst_9481: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8455; +op3val:0x8000; valaddr_reg:x2; val_offset:28341*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28341*FLEN/8, x3, x1, x4) + +inst_9482: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8455; +op3val:0x1; valaddr_reg:x2; val_offset:28344*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28344*FLEN/8, x3, x1, x4) + +inst_9483: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8455; +op3val:0x8001; valaddr_reg:x2; val_offset:28347*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28347*FLEN/8, x3, x1, x4) + +inst_9484: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8455; +op3val:0x2; valaddr_reg:x2; val_offset:28350*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28350*FLEN/8, x3, x1, x4) + +inst_9485: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8455; +op3val:0x83fe; valaddr_reg:x2; val_offset:28353*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28353*FLEN/8, x3, x1, x4) + +inst_9486: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8455; +op3val:0x3ff; valaddr_reg:x2; val_offset:28356*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28356*FLEN/8, x3, x1, x4) + +inst_9487: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8455; +op3val:0x83ff; valaddr_reg:x2; val_offset:28359*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28359*FLEN/8, x3, x1, x4) + +inst_9488: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8455; +op3val:0x400; valaddr_reg:x2; val_offset:28362*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28362*FLEN/8, x3, x1, x4) + +inst_9489: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8455; +op3val:0x8400; valaddr_reg:x2; val_offset:28365*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28365*FLEN/8, x3, x1, x4) + +inst_9490: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8455; +op3val:0x401; valaddr_reg:x2; val_offset:28368*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28368*FLEN/8, x3, x1, x4) + +inst_9491: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8455; +op3val:0x8455; valaddr_reg:x2; val_offset:28371*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28371*FLEN/8, x3, x1, x4) + +inst_9492: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8455; +op3val:0x7bff; valaddr_reg:x2; val_offset:28374*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28374*FLEN/8, x3, x1, x4) + +inst_9493: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8455; +op3val:0xfbff; valaddr_reg:x2; val_offset:28377*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28377*FLEN/8, x3, x1, x4) + +inst_9494: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8455; +op3val:0x7c00; valaddr_reg:x2; val_offset:28380*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28380*FLEN/8, x3, x1, x4) + +inst_9495: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8455; +op3val:0xfc00; valaddr_reg:x2; val_offset:28383*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28383*FLEN/8, x3, x1, x4) + +inst_9496: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8455; +op3val:0x7e00; valaddr_reg:x2; val_offset:28386*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28386*FLEN/8, x3, x1, x4) + +inst_9497: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8455; +op3val:0xfe00; valaddr_reg:x2; val_offset:28389*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28389*FLEN/8, x3, x1, x4) + +inst_9498: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8455; +op3val:0x7e01; valaddr_reg:x2; val_offset:28392*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28392*FLEN/8, x3, x1, x4) + +inst_9499: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8455; +op3val:0xfe55; valaddr_reg:x2; val_offset:28395*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28395*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_75) + +inst_9500: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8455; +op3val:0x7c01; valaddr_reg:x2; val_offset:28398*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28398*FLEN/8, x3, x1, x4) + +inst_9501: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8455; +op3val:0xfd55; valaddr_reg:x2; val_offset:28401*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28401*FLEN/8, x3, x1, x4) + +inst_9502: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8455; +op3val:0x3c00; valaddr_reg:x2; val_offset:28404*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28404*FLEN/8, x3, x1, x4) + +inst_9503: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x8455; +op3val:0xbc00; valaddr_reg:x2; val_offset:28407*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28407*FLEN/8, x3, x1, x4) + +inst_9504: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7bff; +op3val:0x0; valaddr_reg:x2; val_offset:28410*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28410*FLEN/8, x3, x1, x4) + +inst_9505: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7bff; +op3val:0x8000; valaddr_reg:x2; val_offset:28413*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28413*FLEN/8, x3, x1, x4) + +inst_9506: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7bff; +op3val:0x1; valaddr_reg:x2; val_offset:28416*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28416*FLEN/8, x3, x1, x4) + +inst_9507: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7bff; +op3val:0x8001; valaddr_reg:x2; val_offset:28419*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28419*FLEN/8, x3, x1, x4) + +inst_9508: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7bff; +op3val:0x2; valaddr_reg:x2; val_offset:28422*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28422*FLEN/8, x3, x1, x4) + +inst_9509: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7bff; +op3val:0x83fe; valaddr_reg:x2; val_offset:28425*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28425*FLEN/8, x3, x1, x4) + +inst_9510: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7bff; +op3val:0x3ff; valaddr_reg:x2; val_offset:28428*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28428*FLEN/8, x3, x1, x4) + +inst_9511: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7bff; +op3val:0x83ff; valaddr_reg:x2; val_offset:28431*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28431*FLEN/8, x3, x1, x4) + +inst_9512: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7bff; +op3val:0x400; valaddr_reg:x2; val_offset:28434*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28434*FLEN/8, x3, x1, x4) + +inst_9513: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7bff; +op3val:0x8400; valaddr_reg:x2; val_offset:28437*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28437*FLEN/8, x3, x1, x4) + +inst_9514: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7bff; +op3val:0x401; valaddr_reg:x2; val_offset:28440*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28440*FLEN/8, x3, x1, x4) + +inst_9515: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7bff; +op3val:0x8455; valaddr_reg:x2; val_offset:28443*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28443*FLEN/8, x3, x1, x4) + +inst_9516: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7bff; +op3val:0x7bff; valaddr_reg:x2; val_offset:28446*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28446*FLEN/8, x3, x1, x4) + +inst_9517: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7bff; +op3val:0xfbff; valaddr_reg:x2; val_offset:28449*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28449*FLEN/8, x3, x1, x4) + +inst_9518: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7bff; +op3val:0x7c00; valaddr_reg:x2; val_offset:28452*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28452*FLEN/8, x3, x1, x4) + +inst_9519: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7bff; +op3val:0xfc00; valaddr_reg:x2; val_offset:28455*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28455*FLEN/8, x3, x1, x4) + +inst_9520: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7bff; +op3val:0x7e00; valaddr_reg:x2; val_offset:28458*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28458*FLEN/8, x3, x1, x4) + +inst_9521: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7bff; +op3val:0xfe00; valaddr_reg:x2; val_offset:28461*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28461*FLEN/8, x3, x1, x4) + +inst_9522: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7bff; +op3val:0x7e01; valaddr_reg:x2; val_offset:28464*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28464*FLEN/8, x3, x1, x4) + +inst_9523: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7bff; +op3val:0xfe55; valaddr_reg:x2; val_offset:28467*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28467*FLEN/8, x3, x1, x4) + +inst_9524: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7bff; +op3val:0x7c01; valaddr_reg:x2; val_offset:28470*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28470*FLEN/8, x3, x1, x4) + +inst_9525: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7bff; +op3val:0xfd55; valaddr_reg:x2; val_offset:28473*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28473*FLEN/8, x3, x1, x4) + +inst_9526: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7bff; +op3val:0x3c00; valaddr_reg:x2; val_offset:28476*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28476*FLEN/8, x3, x1, x4) + +inst_9527: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7bff; +op3val:0xbc00; valaddr_reg:x2; val_offset:28479*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28479*FLEN/8, x3, x1, x4) + +inst_9528: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfbff; +op3val:0x0; valaddr_reg:x2; val_offset:28482*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28482*FLEN/8, x3, x1, x4) + +inst_9529: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfbff; +op3val:0x8000; valaddr_reg:x2; val_offset:28485*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28485*FLEN/8, x3, x1, x4) + +inst_9530: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfbff; +op3val:0x1; valaddr_reg:x2; val_offset:28488*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28488*FLEN/8, x3, x1, x4) + +inst_9531: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfbff; +op3val:0x8001; valaddr_reg:x2; val_offset:28491*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28491*FLEN/8, x3, x1, x4) + +inst_9532: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfbff; +op3val:0x2; valaddr_reg:x2; val_offset:28494*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28494*FLEN/8, x3, x1, x4) + +inst_9533: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfbff; +op3val:0x83fe; valaddr_reg:x2; val_offset:28497*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28497*FLEN/8, x3, x1, x4) + +inst_9534: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfbff; +op3val:0x3ff; valaddr_reg:x2; val_offset:28500*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28500*FLEN/8, x3, x1, x4) + +inst_9535: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfbff; +op3val:0x83ff; valaddr_reg:x2; val_offset:28503*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28503*FLEN/8, x3, x1, x4) + +inst_9536: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfbff; +op3val:0x400; valaddr_reg:x2; val_offset:28506*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28506*FLEN/8, x3, x1, x4) + +inst_9537: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfbff; +op3val:0x8400; valaddr_reg:x2; val_offset:28509*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28509*FLEN/8, x3, x1, x4) + +inst_9538: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfbff; +op3val:0x401; valaddr_reg:x2; val_offset:28512*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28512*FLEN/8, x3, x1, x4) + +inst_9539: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfbff; +op3val:0x8455; valaddr_reg:x2; val_offset:28515*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28515*FLEN/8, x3, x1, x4) + +inst_9540: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfbff; +op3val:0x7bff; valaddr_reg:x2; val_offset:28518*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28518*FLEN/8, x3, x1, x4) + +inst_9541: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfbff; +op3val:0xfbff; valaddr_reg:x2; val_offset:28521*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28521*FLEN/8, x3, x1, x4) + +inst_9542: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfbff; +op3val:0x7c00; valaddr_reg:x2; val_offset:28524*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28524*FLEN/8, x3, x1, x4) + +inst_9543: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfbff; +op3val:0xfc00; valaddr_reg:x2; val_offset:28527*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28527*FLEN/8, x3, x1, x4) + +inst_9544: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfbff; +op3val:0x7e00; valaddr_reg:x2; val_offset:28530*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28530*FLEN/8, x3, x1, x4) + +inst_9545: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfbff; +op3val:0xfe00; valaddr_reg:x2; val_offset:28533*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28533*FLEN/8, x3, x1, x4) + +inst_9546: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfbff; +op3val:0x7e01; valaddr_reg:x2; val_offset:28536*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28536*FLEN/8, x3, x1, x4) + +inst_9547: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfbff; +op3val:0xfe55; valaddr_reg:x2; val_offset:28539*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28539*FLEN/8, x3, x1, x4) + +inst_9548: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfbff; +op3val:0x7c01; valaddr_reg:x2; val_offset:28542*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28542*FLEN/8, x3, x1, x4) + +inst_9549: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfbff; +op3val:0xfd55; valaddr_reg:x2; val_offset:28545*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28545*FLEN/8, x3, x1, x4) + +inst_9550: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfbff; +op3val:0x3c00; valaddr_reg:x2; val_offset:28548*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28548*FLEN/8, x3, x1, x4) + +inst_9551: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfbff; +op3val:0xbc00; valaddr_reg:x2; val_offset:28551*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28551*FLEN/8, x3, x1, x4) + +inst_9552: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7c00; +op3val:0x0; valaddr_reg:x2; val_offset:28554*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28554*FLEN/8, x3, x1, x4) + +inst_9553: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7c00; +op3val:0x8000; valaddr_reg:x2; val_offset:28557*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28557*FLEN/8, x3, x1, x4) + +inst_9554: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7c00; +op3val:0x1; valaddr_reg:x2; val_offset:28560*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28560*FLEN/8, x3, x1, x4) + +inst_9555: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7c00; +op3val:0x8001; valaddr_reg:x2; val_offset:28563*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28563*FLEN/8, x3, x1, x4) + +inst_9556: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7c00; +op3val:0x2; valaddr_reg:x2; val_offset:28566*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28566*FLEN/8, x3, x1, x4) + +inst_9557: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7c00; +op3val:0x83fe; valaddr_reg:x2; val_offset:28569*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28569*FLEN/8, x3, x1, x4) + +inst_9558: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7c00; +op3val:0x3ff; valaddr_reg:x2; val_offset:28572*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28572*FLEN/8, x3, x1, x4) + +inst_9559: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7c00; +op3val:0x83ff; valaddr_reg:x2; val_offset:28575*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28575*FLEN/8, x3, x1, x4) + +inst_9560: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7c00; +op3val:0x400; valaddr_reg:x2; val_offset:28578*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28578*FLEN/8, x3, x1, x4) + +inst_9561: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7c00; +op3val:0x8400; valaddr_reg:x2; val_offset:28581*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28581*FLEN/8, x3, x1, x4) + +inst_9562: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7c00; +op3val:0x401; valaddr_reg:x2; val_offset:28584*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28584*FLEN/8, x3, x1, x4) + +inst_9563: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7c00; +op3val:0x8455; valaddr_reg:x2; val_offset:28587*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28587*FLEN/8, x3, x1, x4) + +inst_9564: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7c00; +op3val:0x7bff; valaddr_reg:x2; val_offset:28590*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28590*FLEN/8, x3, x1, x4) + +inst_9565: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7c00; +op3val:0xfbff; valaddr_reg:x2; val_offset:28593*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28593*FLEN/8, x3, x1, x4) + +inst_9566: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7c00; +op3val:0x7c00; valaddr_reg:x2; val_offset:28596*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28596*FLEN/8, x3, x1, x4) + +inst_9567: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7c00; +op3val:0xfc00; valaddr_reg:x2; val_offset:28599*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28599*FLEN/8, x3, x1, x4) + +inst_9568: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7c00; +op3val:0x7e00; valaddr_reg:x2; val_offset:28602*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28602*FLEN/8, x3, x1, x4) + +inst_9569: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7c00; +op3val:0xfe00; valaddr_reg:x2; val_offset:28605*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28605*FLEN/8, x3, x1, x4) + +inst_9570: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7c00; +op3val:0x7e01; valaddr_reg:x2; val_offset:28608*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28608*FLEN/8, x3, x1, x4) + +inst_9571: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7c00; +op3val:0xfe55; valaddr_reg:x2; val_offset:28611*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28611*FLEN/8, x3, x1, x4) + +inst_9572: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7c00; +op3val:0x7c01; valaddr_reg:x2; val_offset:28614*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28614*FLEN/8, x3, x1, x4) + +inst_9573: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7c00; +op3val:0xfd55; valaddr_reg:x2; val_offset:28617*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28617*FLEN/8, x3, x1, x4) + +inst_9574: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7c00; +op3val:0x3c00; valaddr_reg:x2; val_offset:28620*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28620*FLEN/8, x3, x1, x4) + +inst_9575: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7c00; +op3val:0xbc00; valaddr_reg:x2; val_offset:28623*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28623*FLEN/8, x3, x1, x4) + +inst_9576: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfc00; +op3val:0x0; valaddr_reg:x2; val_offset:28626*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28626*FLEN/8, x3, x1, x4) + +inst_9577: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfc00; +op3val:0x8000; valaddr_reg:x2; val_offset:28629*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28629*FLEN/8, x3, x1, x4) + +inst_9578: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfc00; +op3val:0x1; valaddr_reg:x2; val_offset:28632*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28632*FLEN/8, x3, x1, x4) + +inst_9579: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfc00; +op3val:0x8001; valaddr_reg:x2; val_offset:28635*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28635*FLEN/8, x3, x1, x4) + +inst_9580: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfc00; +op3val:0x2; valaddr_reg:x2; val_offset:28638*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28638*FLEN/8, x3, x1, x4) + +inst_9581: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfc00; +op3val:0x83fe; valaddr_reg:x2; val_offset:28641*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28641*FLEN/8, x3, x1, x4) + +inst_9582: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfc00; +op3val:0x3ff; valaddr_reg:x2; val_offset:28644*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28644*FLEN/8, x3, x1, x4) + +inst_9583: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfc00; +op3val:0x83ff; valaddr_reg:x2; val_offset:28647*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28647*FLEN/8, x3, x1, x4) + +inst_9584: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfc00; +op3val:0x400; valaddr_reg:x2; val_offset:28650*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28650*FLEN/8, x3, x1, x4) + +inst_9585: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfc00; +op3val:0x8400; valaddr_reg:x2; val_offset:28653*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28653*FLEN/8, x3, x1, x4) + +inst_9586: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfc00; +op3val:0x401; valaddr_reg:x2; val_offset:28656*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28656*FLEN/8, x3, x1, x4) + +inst_9587: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfc00; +op3val:0x8455; valaddr_reg:x2; val_offset:28659*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28659*FLEN/8, x3, x1, x4) + +inst_9588: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfc00; +op3val:0x7bff; valaddr_reg:x2; val_offset:28662*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28662*FLEN/8, x3, x1, x4) + +inst_9589: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfc00; +op3val:0xfbff; valaddr_reg:x2; val_offset:28665*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28665*FLEN/8, x3, x1, x4) + +inst_9590: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfc00; +op3val:0x7c00; valaddr_reg:x2; val_offset:28668*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28668*FLEN/8, x3, x1, x4) + +inst_9591: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfc00; +op3val:0xfc00; valaddr_reg:x2; val_offset:28671*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28671*FLEN/8, x3, x1, x4) + +inst_9592: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfc00; +op3val:0x7e00; valaddr_reg:x2; val_offset:28674*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28674*FLEN/8, x3, x1, x4) + +inst_9593: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfc00; +op3val:0xfe00; valaddr_reg:x2; val_offset:28677*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28677*FLEN/8, x3, x1, x4) + +inst_9594: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfc00; +op3val:0x7e01; valaddr_reg:x2; val_offset:28680*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28680*FLEN/8, x3, x1, x4) + +inst_9595: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfc00; +op3val:0xfe55; valaddr_reg:x2; val_offset:28683*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28683*FLEN/8, x3, x1, x4) + +inst_9596: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfc00; +op3val:0x7c01; valaddr_reg:x2; val_offset:28686*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28686*FLEN/8, x3, x1, x4) + +inst_9597: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfc00; +op3val:0xfd55; valaddr_reg:x2; val_offset:28689*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28689*FLEN/8, x3, x1, x4) + +inst_9598: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfc00; +op3val:0x3c00; valaddr_reg:x2; val_offset:28692*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28692*FLEN/8, x3, x1, x4) + +inst_9599: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfc00; +op3val:0xbc00; valaddr_reg:x2; val_offset:28695*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28695*FLEN/8, x3, x1, x4) + +inst_9600: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7e00; +op3val:0x0; valaddr_reg:x2; val_offset:28698*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28698*FLEN/8, x3, x1, x4) + +inst_9601: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7e00; +op3val:0x8000; valaddr_reg:x2; val_offset:28701*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28701*FLEN/8, x3, x1, x4) + +inst_9602: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7e00; +op3val:0x1; valaddr_reg:x2; val_offset:28704*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28704*FLEN/8, x3, x1, x4) + +inst_9603: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7e00; +op3val:0x8001; valaddr_reg:x2; val_offset:28707*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28707*FLEN/8, x3, x1, x4) + +inst_9604: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7e00; +op3val:0x2; valaddr_reg:x2; val_offset:28710*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28710*FLEN/8, x3, x1, x4) + +inst_9605: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7e00; +op3val:0x83fe; valaddr_reg:x2; val_offset:28713*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28713*FLEN/8, x3, x1, x4) + +inst_9606: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7e00; +op3val:0x3ff; valaddr_reg:x2; val_offset:28716*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28716*FLEN/8, x3, x1, x4) + +inst_9607: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7e00; +op3val:0x83ff; valaddr_reg:x2; val_offset:28719*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28719*FLEN/8, x3, x1, x4) + +inst_9608: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7e00; +op3val:0x400; valaddr_reg:x2; val_offset:28722*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28722*FLEN/8, x3, x1, x4) + +inst_9609: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7e00; +op3val:0x8400; valaddr_reg:x2; val_offset:28725*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28725*FLEN/8, x3, x1, x4) + +inst_9610: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7e00; +op3val:0x401; valaddr_reg:x2; val_offset:28728*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28728*FLEN/8, x3, x1, x4) + +inst_9611: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7e00; +op3val:0x8455; valaddr_reg:x2; val_offset:28731*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28731*FLEN/8, x3, x1, x4) + +inst_9612: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7e00; +op3val:0x7bff; valaddr_reg:x2; val_offset:28734*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28734*FLEN/8, x3, x1, x4) + +inst_9613: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7e00; +op3val:0xfbff; valaddr_reg:x2; val_offset:28737*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28737*FLEN/8, x3, x1, x4) + +inst_9614: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7e00; +op3val:0x7c00; valaddr_reg:x2; val_offset:28740*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28740*FLEN/8, x3, x1, x4) + +inst_9615: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7e00; +op3val:0xfc00; valaddr_reg:x2; val_offset:28743*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28743*FLEN/8, x3, x1, x4) + +inst_9616: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7e00; +op3val:0x7e00; valaddr_reg:x2; val_offset:28746*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28746*FLEN/8, x3, x1, x4) + +inst_9617: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7e00; +op3val:0xfe00; valaddr_reg:x2; val_offset:28749*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28749*FLEN/8, x3, x1, x4) + +inst_9618: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7e00; +op3val:0x7e01; valaddr_reg:x2; val_offset:28752*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28752*FLEN/8, x3, x1, x4) + +inst_9619: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7e00; +op3val:0xfe55; valaddr_reg:x2; val_offset:28755*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28755*FLEN/8, x3, x1, x4) + +inst_9620: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7e00; +op3val:0x7c01; valaddr_reg:x2; val_offset:28758*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28758*FLEN/8, x3, x1, x4) + +inst_9621: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7e00; +op3val:0xfd55; valaddr_reg:x2; val_offset:28761*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28761*FLEN/8, x3, x1, x4) + +inst_9622: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7e00; +op3val:0x3c00; valaddr_reg:x2; val_offset:28764*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28764*FLEN/8, x3, x1, x4) + +inst_9623: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7e00; +op3val:0xbc00; valaddr_reg:x2; val_offset:28767*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28767*FLEN/8, x3, x1, x4) + +inst_9624: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfe00; +op3val:0x0; valaddr_reg:x2; val_offset:28770*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28770*FLEN/8, x3, x1, x4) + +inst_9625: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfe00; +op3val:0x8000; valaddr_reg:x2; val_offset:28773*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28773*FLEN/8, x3, x1, x4) + +inst_9626: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfe00; +op3val:0x1; valaddr_reg:x2; val_offset:28776*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28776*FLEN/8, x3, x1, x4) + +inst_9627: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfe00; +op3val:0x8001; valaddr_reg:x2; val_offset:28779*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28779*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_76) + +inst_9628: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfe00; +op3val:0x2; valaddr_reg:x2; val_offset:28782*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28782*FLEN/8, x3, x1, x4) + +inst_9629: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfe00; +op3val:0x83fe; valaddr_reg:x2; val_offset:28785*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28785*FLEN/8, x3, x1, x4) + +inst_9630: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfe00; +op3val:0x3ff; valaddr_reg:x2; val_offset:28788*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28788*FLEN/8, x3, x1, x4) + +inst_9631: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfe00; +op3val:0x83ff; valaddr_reg:x2; val_offset:28791*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28791*FLEN/8, x3, x1, x4) + +inst_9632: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfe00; +op3val:0x400; valaddr_reg:x2; val_offset:28794*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28794*FLEN/8, x3, x1, x4) + +inst_9633: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfe00; +op3val:0x8400; valaddr_reg:x2; val_offset:28797*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28797*FLEN/8, x3, x1, x4) + +inst_9634: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfe00; +op3val:0x401; valaddr_reg:x2; val_offset:28800*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28800*FLEN/8, x3, x1, x4) + +inst_9635: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfe00; +op3val:0x8455; valaddr_reg:x2; val_offset:28803*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28803*FLEN/8, x3, x1, x4) + +inst_9636: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfe00; +op3val:0x7bff; valaddr_reg:x2; val_offset:28806*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28806*FLEN/8, x3, x1, x4) + +inst_9637: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfe00; +op3val:0xfbff; valaddr_reg:x2; val_offset:28809*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28809*FLEN/8, x3, x1, x4) + +inst_9638: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfe00; +op3val:0x7c00; valaddr_reg:x2; val_offset:28812*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28812*FLEN/8, x3, x1, x4) + +inst_9639: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfe00; +op3val:0xfc00; valaddr_reg:x2; val_offset:28815*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28815*FLEN/8, x3, x1, x4) + +inst_9640: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfe00; +op3val:0x7e00; valaddr_reg:x2; val_offset:28818*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28818*FLEN/8, x3, x1, x4) + +inst_9641: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfe00; +op3val:0xfe00; valaddr_reg:x2; val_offset:28821*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28821*FLEN/8, x3, x1, x4) + +inst_9642: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfe00; +op3val:0x7e01; valaddr_reg:x2; val_offset:28824*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28824*FLEN/8, x3, x1, x4) + +inst_9643: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfe00; +op3val:0xfe55; valaddr_reg:x2; val_offset:28827*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28827*FLEN/8, x3, x1, x4) + +inst_9644: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfe00; +op3val:0x7c01; valaddr_reg:x2; val_offset:28830*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28830*FLEN/8, x3, x1, x4) + +inst_9645: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfe00; +op3val:0xfd55; valaddr_reg:x2; val_offset:28833*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28833*FLEN/8, x3, x1, x4) + +inst_9646: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfe00; +op3val:0x3c00; valaddr_reg:x2; val_offset:28836*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28836*FLEN/8, x3, x1, x4) + +inst_9647: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfe00; +op3val:0xbc00; valaddr_reg:x2; val_offset:28839*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28839*FLEN/8, x3, x1, x4) + +inst_9648: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7e01; +op3val:0x0; valaddr_reg:x2; val_offset:28842*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28842*FLEN/8, x3, x1, x4) + +inst_9649: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7e01; +op3val:0x8000; valaddr_reg:x2; val_offset:28845*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28845*FLEN/8, x3, x1, x4) + +inst_9650: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7e01; +op3val:0x1; valaddr_reg:x2; val_offset:28848*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28848*FLEN/8, x3, x1, x4) + +inst_9651: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7e01; +op3val:0x8001; valaddr_reg:x2; val_offset:28851*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28851*FLEN/8, x3, x1, x4) + +inst_9652: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7e01; +op3val:0x2; valaddr_reg:x2; val_offset:28854*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28854*FLEN/8, x3, x1, x4) + +inst_9653: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7e01; +op3val:0x83fe; valaddr_reg:x2; val_offset:28857*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28857*FLEN/8, x3, x1, x4) + +inst_9654: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7e01; +op3val:0x3ff; valaddr_reg:x2; val_offset:28860*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28860*FLEN/8, x3, x1, x4) + +inst_9655: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7e01; +op3val:0x83ff; valaddr_reg:x2; val_offset:28863*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28863*FLEN/8, x3, x1, x4) + +inst_9656: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7e01; +op3val:0x400; valaddr_reg:x2; val_offset:28866*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28866*FLEN/8, x3, x1, x4) + +inst_9657: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7e01; +op3val:0x8400; valaddr_reg:x2; val_offset:28869*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28869*FLEN/8, x3, x1, x4) + +inst_9658: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7e01; +op3val:0x401; valaddr_reg:x2; val_offset:28872*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28872*FLEN/8, x3, x1, x4) + +inst_9659: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7e01; +op3val:0x8455; valaddr_reg:x2; val_offset:28875*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28875*FLEN/8, x3, x1, x4) + +inst_9660: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7e01; +op3val:0x7bff; valaddr_reg:x2; val_offset:28878*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28878*FLEN/8, x3, x1, x4) + +inst_9661: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7e01; +op3val:0xfbff; valaddr_reg:x2; val_offset:28881*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28881*FLEN/8, x3, x1, x4) + +inst_9662: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7e01; +op3val:0x7c00; valaddr_reg:x2; val_offset:28884*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28884*FLEN/8, x3, x1, x4) + +inst_9663: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7e01; +op3val:0xfc00; valaddr_reg:x2; val_offset:28887*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28887*FLEN/8, x3, x1, x4) + +inst_9664: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7e01; +op3val:0x7e00; valaddr_reg:x2; val_offset:28890*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28890*FLEN/8, x3, x1, x4) + +inst_9665: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7e01; +op3val:0xfe00; valaddr_reg:x2; val_offset:28893*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28893*FLEN/8, x3, x1, x4) + +inst_9666: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7e01; +op3val:0x7e01; valaddr_reg:x2; val_offset:28896*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28896*FLEN/8, x3, x1, x4) + +inst_9667: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7e01; +op3val:0xfe55; valaddr_reg:x2; val_offset:28899*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28899*FLEN/8, x3, x1, x4) + +inst_9668: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7e01; +op3val:0x7c01; valaddr_reg:x2; val_offset:28902*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28902*FLEN/8, x3, x1, x4) + +inst_9669: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7e01; +op3val:0xfd55; valaddr_reg:x2; val_offset:28905*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28905*FLEN/8, x3, x1, x4) + +inst_9670: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7e01; +op3val:0x3c00; valaddr_reg:x2; val_offset:28908*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28908*FLEN/8, x3, x1, x4) + +inst_9671: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7e01; +op3val:0xbc00; valaddr_reg:x2; val_offset:28911*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28911*FLEN/8, x3, x1, x4) + +inst_9672: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfe55; +op3val:0x0; valaddr_reg:x2; val_offset:28914*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28914*FLEN/8, x3, x1, x4) + +inst_9673: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfe55; +op3val:0x8000; valaddr_reg:x2; val_offset:28917*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28917*FLEN/8, x3, x1, x4) + +inst_9674: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfe55; +op3val:0x1; valaddr_reg:x2; val_offset:28920*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28920*FLEN/8, x3, x1, x4) + +inst_9675: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfe55; +op3val:0x8001; valaddr_reg:x2; val_offset:28923*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28923*FLEN/8, x3, x1, x4) + +inst_9676: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfe55; +op3val:0x2; valaddr_reg:x2; val_offset:28926*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28926*FLEN/8, x3, x1, x4) + +inst_9677: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfe55; +op3val:0x83fe; valaddr_reg:x2; val_offset:28929*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28929*FLEN/8, x3, x1, x4) + +inst_9678: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfe55; +op3val:0x3ff; valaddr_reg:x2; val_offset:28932*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28932*FLEN/8, x3, x1, x4) + +inst_9679: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfe55; +op3val:0x83ff; valaddr_reg:x2; val_offset:28935*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28935*FLEN/8, x3, x1, x4) + +inst_9680: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfe55; +op3val:0x400; valaddr_reg:x2; val_offset:28938*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28938*FLEN/8, x3, x1, x4) + +inst_9681: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfe55; +op3val:0x8400; valaddr_reg:x2; val_offset:28941*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28941*FLEN/8, x3, x1, x4) + +inst_9682: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfe55; +op3val:0x401; valaddr_reg:x2; val_offset:28944*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28944*FLEN/8, x3, x1, x4) + +inst_9683: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfe55; +op3val:0x8455; valaddr_reg:x2; val_offset:28947*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28947*FLEN/8, x3, x1, x4) + +inst_9684: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfe55; +op3val:0x7bff; valaddr_reg:x2; val_offset:28950*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28950*FLEN/8, x3, x1, x4) + +inst_9685: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfe55; +op3val:0xfbff; valaddr_reg:x2; val_offset:28953*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28953*FLEN/8, x3, x1, x4) + +inst_9686: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfe55; +op3val:0x7c00; valaddr_reg:x2; val_offset:28956*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28956*FLEN/8, x3, x1, x4) + +inst_9687: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfe55; +op3val:0xfc00; valaddr_reg:x2; val_offset:28959*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28959*FLEN/8, x3, x1, x4) + +inst_9688: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfe55; +op3val:0x7e00; valaddr_reg:x2; val_offset:28962*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28962*FLEN/8, x3, x1, x4) + +inst_9689: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfe55; +op3val:0xfe00; valaddr_reg:x2; val_offset:28965*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28965*FLEN/8, x3, x1, x4) + +inst_9690: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfe55; +op3val:0x7e01; valaddr_reg:x2; val_offset:28968*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28968*FLEN/8, x3, x1, x4) + +inst_9691: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfe55; +op3val:0xfe55; valaddr_reg:x2; val_offset:28971*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28971*FLEN/8, x3, x1, x4) + +inst_9692: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfe55; +op3val:0x7c01; valaddr_reg:x2; val_offset:28974*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28974*FLEN/8, x3, x1, x4) + +inst_9693: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfe55; +op3val:0xfd55; valaddr_reg:x2; val_offset:28977*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28977*FLEN/8, x3, x1, x4) + +inst_9694: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfe55; +op3val:0x3c00; valaddr_reg:x2; val_offset:28980*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28980*FLEN/8, x3, x1, x4) + +inst_9695: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfe55; +op3val:0xbc00; valaddr_reg:x2; val_offset:28983*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28983*FLEN/8, x3, x1, x4) + +inst_9696: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7c01; +op3val:0x0; valaddr_reg:x2; val_offset:28986*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28986*FLEN/8, x3, x1, x4) + +inst_9697: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7c01; +op3val:0x8000; valaddr_reg:x2; val_offset:28989*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28989*FLEN/8, x3, x1, x4) + +inst_9698: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7c01; +op3val:0x1; valaddr_reg:x2; val_offset:28992*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28992*FLEN/8, x3, x1, x4) + +inst_9699: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7c01; +op3val:0x8001; valaddr_reg:x2; val_offset:28995*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28995*FLEN/8, x3, x1, x4) + +inst_9700: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7c01; +op3val:0x2; valaddr_reg:x2; val_offset:28998*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 28998*FLEN/8, x3, x1, x4) + +inst_9701: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7c01; +op3val:0x83fe; valaddr_reg:x2; val_offset:29001*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29001*FLEN/8, x3, x1, x4) + +inst_9702: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7c01; +op3val:0x3ff; valaddr_reg:x2; val_offset:29004*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29004*FLEN/8, x3, x1, x4) + +inst_9703: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7c01; +op3val:0x83ff; valaddr_reg:x2; val_offset:29007*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29007*FLEN/8, x3, x1, x4) + +inst_9704: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7c01; +op3val:0x400; valaddr_reg:x2; val_offset:29010*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29010*FLEN/8, x3, x1, x4) + +inst_9705: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7c01; +op3val:0x8400; valaddr_reg:x2; val_offset:29013*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29013*FLEN/8, x3, x1, x4) + +inst_9706: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7c01; +op3val:0x401; valaddr_reg:x2; val_offset:29016*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29016*FLEN/8, x3, x1, x4) + +inst_9707: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7c01; +op3val:0x8455; valaddr_reg:x2; val_offset:29019*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29019*FLEN/8, x3, x1, x4) + +inst_9708: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7c01; +op3val:0x7bff; valaddr_reg:x2; val_offset:29022*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29022*FLEN/8, x3, x1, x4) + +inst_9709: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7c01; +op3val:0xfbff; valaddr_reg:x2; val_offset:29025*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29025*FLEN/8, x3, x1, x4) + +inst_9710: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7c01; +op3val:0x7c00; valaddr_reg:x2; val_offset:29028*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29028*FLEN/8, x3, x1, x4) + +inst_9711: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7c01; +op3val:0xfc00; valaddr_reg:x2; val_offset:29031*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29031*FLEN/8, x3, x1, x4) + +inst_9712: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7c01; +op3val:0x7e00; valaddr_reg:x2; val_offset:29034*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29034*FLEN/8, x3, x1, x4) + +inst_9713: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7c01; +op3val:0xfe00; valaddr_reg:x2; val_offset:29037*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29037*FLEN/8, x3, x1, x4) + +inst_9714: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7c01; +op3val:0x7e01; valaddr_reg:x2; val_offset:29040*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29040*FLEN/8, x3, x1, x4) + +inst_9715: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7c01; +op3val:0xfe55; valaddr_reg:x2; val_offset:29043*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29043*FLEN/8, x3, x1, x4) + +inst_9716: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7c01; +op3val:0x7c01; valaddr_reg:x2; val_offset:29046*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29046*FLEN/8, x3, x1, x4) + +inst_9717: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7c01; +op3val:0xfd55; valaddr_reg:x2; val_offset:29049*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29049*FLEN/8, x3, x1, x4) + +inst_9718: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7c01; +op3val:0x3c00; valaddr_reg:x2; val_offset:29052*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29052*FLEN/8, x3, x1, x4) + +inst_9719: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x7c01; +op3val:0xbc00; valaddr_reg:x2; val_offset:29055*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29055*FLEN/8, x3, x1, x4) + +inst_9720: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfd55; +op3val:0x0; valaddr_reg:x2; val_offset:29058*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29058*FLEN/8, x3, x1, x4) + +inst_9721: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfd55; +op3val:0x8000; valaddr_reg:x2; val_offset:29061*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29061*FLEN/8, x3, x1, x4) + +inst_9722: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfd55; +op3val:0x1; valaddr_reg:x2; val_offset:29064*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29064*FLEN/8, x3, x1, x4) + +inst_9723: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfd55; +op3val:0x8001; valaddr_reg:x2; val_offset:29067*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29067*FLEN/8, x3, x1, x4) + +inst_9724: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfd55; +op3val:0x2; valaddr_reg:x2; val_offset:29070*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29070*FLEN/8, x3, x1, x4) + +inst_9725: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfd55; +op3val:0x83fe; valaddr_reg:x2; val_offset:29073*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29073*FLEN/8, x3, x1, x4) + +inst_9726: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfd55; +op3val:0x3ff; valaddr_reg:x2; val_offset:29076*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29076*FLEN/8, x3, x1, x4) + +inst_9727: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfd55; +op3val:0x83ff; valaddr_reg:x2; val_offset:29079*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29079*FLEN/8, x3, x1, x4) + +inst_9728: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfd55; +op3val:0x400; valaddr_reg:x2; val_offset:29082*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29082*FLEN/8, x3, x1, x4) + +inst_9729: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfd55; +op3val:0x8400; valaddr_reg:x2; val_offset:29085*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29085*FLEN/8, x3, x1, x4) + +inst_9730: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfd55; +op3val:0x401; valaddr_reg:x2; val_offset:29088*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29088*FLEN/8, x3, x1, x4) + +inst_9731: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfd55; +op3val:0x8455; valaddr_reg:x2; val_offset:29091*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29091*FLEN/8, x3, x1, x4) + +inst_9732: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfd55; +op3val:0x7bff; valaddr_reg:x2; val_offset:29094*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29094*FLEN/8, x3, x1, x4) + +inst_9733: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfd55; +op3val:0xfbff; valaddr_reg:x2; val_offset:29097*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29097*FLEN/8, x3, x1, x4) + +inst_9734: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfd55; +op3val:0x7c00; valaddr_reg:x2; val_offset:29100*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29100*FLEN/8, x3, x1, x4) + +inst_9735: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfd55; +op3val:0xfc00; valaddr_reg:x2; val_offset:29103*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29103*FLEN/8, x3, x1, x4) + +inst_9736: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfd55; +op3val:0x7e00; valaddr_reg:x2; val_offset:29106*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29106*FLEN/8, x3, x1, x4) + +inst_9737: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfd55; +op3val:0xfe00; valaddr_reg:x2; val_offset:29109*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29109*FLEN/8, x3, x1, x4) + +inst_9738: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfd55; +op3val:0x7e01; valaddr_reg:x2; val_offset:29112*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29112*FLEN/8, x3, x1, x4) + +inst_9739: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfd55; +op3val:0xfe55; valaddr_reg:x2; val_offset:29115*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29115*FLEN/8, x3, x1, x4) + +inst_9740: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfd55; +op3val:0x7c01; valaddr_reg:x2; val_offset:29118*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29118*FLEN/8, x3, x1, x4) + +inst_9741: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfd55; +op3val:0xfd55; valaddr_reg:x2; val_offset:29121*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29121*FLEN/8, x3, x1, x4) + +inst_9742: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfd55; +op3val:0x3c00; valaddr_reg:x2; val_offset:29124*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29124*FLEN/8, x3, x1, x4) + +inst_9743: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xfd55; +op3val:0xbc00; valaddr_reg:x2; val_offset:29127*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29127*FLEN/8, x3, x1, x4) + +inst_9744: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x3c00; +op3val:0x0; valaddr_reg:x2; val_offset:29130*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29130*FLEN/8, x3, x1, x4) + +inst_9745: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x3c00; +op3val:0x8000; valaddr_reg:x2; val_offset:29133*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29133*FLEN/8, x3, x1, x4) + +inst_9746: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x3c00; +op3val:0x1; valaddr_reg:x2; val_offset:29136*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29136*FLEN/8, x3, x1, x4) + +inst_9747: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x3c00; +op3val:0x8001; valaddr_reg:x2; val_offset:29139*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29139*FLEN/8, x3, x1, x4) + +inst_9748: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x3c00; +op3val:0x2; valaddr_reg:x2; val_offset:29142*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29142*FLEN/8, x3, x1, x4) + +inst_9749: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x3c00; +op3val:0x83fe; valaddr_reg:x2; val_offset:29145*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29145*FLEN/8, x3, x1, x4) + +inst_9750: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x3c00; +op3val:0x3ff; valaddr_reg:x2; val_offset:29148*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29148*FLEN/8, x3, x1, x4) + +inst_9751: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x3c00; +op3val:0x83ff; valaddr_reg:x2; val_offset:29151*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29151*FLEN/8, x3, x1, x4) + +inst_9752: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x3c00; +op3val:0x400; valaddr_reg:x2; val_offset:29154*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29154*FLEN/8, x3, x1, x4) + +inst_9753: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x3c00; +op3val:0x8400; valaddr_reg:x2; val_offset:29157*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29157*FLEN/8, x3, x1, x4) + +inst_9754: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x3c00; +op3val:0x401; valaddr_reg:x2; val_offset:29160*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29160*FLEN/8, x3, x1, x4) + +inst_9755: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x3c00; +op3val:0x8455; valaddr_reg:x2; val_offset:29163*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29163*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_77) + +inst_9756: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x3c00; +op3val:0x7bff; valaddr_reg:x2; val_offset:29166*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29166*FLEN/8, x3, x1, x4) + +inst_9757: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x3c00; +op3val:0xfbff; valaddr_reg:x2; val_offset:29169*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29169*FLEN/8, x3, x1, x4) + +inst_9758: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x3c00; +op3val:0x7c00; valaddr_reg:x2; val_offset:29172*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29172*FLEN/8, x3, x1, x4) + +inst_9759: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x3c00; +op3val:0xfc00; valaddr_reg:x2; val_offset:29175*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29175*FLEN/8, x3, x1, x4) + +inst_9760: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x3c00; +op3val:0x7e00; valaddr_reg:x2; val_offset:29178*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29178*FLEN/8, x3, x1, x4) + +inst_9761: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x3c00; +op3val:0xfe00; valaddr_reg:x2; val_offset:29181*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29181*FLEN/8, x3, x1, x4) + +inst_9762: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x3c00; +op3val:0x7e01; valaddr_reg:x2; val_offset:29184*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29184*FLEN/8, x3, x1, x4) + +inst_9763: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x3c00; +op3val:0xfe55; valaddr_reg:x2; val_offset:29187*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29187*FLEN/8, x3, x1, x4) + +inst_9764: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x3c00; +op3val:0x7c01; valaddr_reg:x2; val_offset:29190*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29190*FLEN/8, x3, x1, x4) + +inst_9765: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x3c00; +op3val:0xfd55; valaddr_reg:x2; val_offset:29193*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29193*FLEN/8, x3, x1, x4) + +inst_9766: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x3c00; +op3val:0x3c00; valaddr_reg:x2; val_offset:29196*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29196*FLEN/8, x3, x1, x4) + +inst_9767: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0x3c00; +op3val:0xbc00; valaddr_reg:x2; val_offset:29199*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29199*FLEN/8, x3, x1, x4) + +inst_9768: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xbc00; +op3val:0x0; valaddr_reg:x2; val_offset:29202*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29202*FLEN/8, x3, x1, x4) + +inst_9769: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xbc00; +op3val:0x8000; valaddr_reg:x2; val_offset:29205*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29205*FLEN/8, x3, x1, x4) + +inst_9770: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xbc00; +op3val:0x1; valaddr_reg:x2; val_offset:29208*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29208*FLEN/8, x3, x1, x4) + +inst_9771: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xbc00; +op3val:0x8001; valaddr_reg:x2; val_offset:29211*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29211*FLEN/8, x3, x1, x4) + +inst_9772: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xbc00; +op3val:0x2; valaddr_reg:x2; val_offset:29214*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29214*FLEN/8, x3, x1, x4) + +inst_9773: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xbc00; +op3val:0x83fe; valaddr_reg:x2; val_offset:29217*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29217*FLEN/8, x3, x1, x4) + +inst_9774: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xbc00; +op3val:0x3ff; valaddr_reg:x2; val_offset:29220*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29220*FLEN/8, x3, x1, x4) + +inst_9775: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xbc00; +op3val:0x83ff; valaddr_reg:x2; val_offset:29223*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29223*FLEN/8, x3, x1, x4) + +inst_9776: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xbc00; +op3val:0x400; valaddr_reg:x2; val_offset:29226*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29226*FLEN/8, x3, x1, x4) + +inst_9777: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xbc00; +op3val:0x8400; valaddr_reg:x2; val_offset:29229*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29229*FLEN/8, x3, x1, x4) + +inst_9778: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xbc00; +op3val:0x401; valaddr_reg:x2; val_offset:29232*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29232*FLEN/8, x3, x1, x4) + +inst_9779: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xbc00; +op3val:0x8455; valaddr_reg:x2; val_offset:29235*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29235*FLEN/8, x3, x1, x4) + +inst_9780: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xbc00; +op3val:0x7bff; valaddr_reg:x2; val_offset:29238*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29238*FLEN/8, x3, x1, x4) + +inst_9781: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xbc00; +op3val:0xfbff; valaddr_reg:x2; val_offset:29241*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29241*FLEN/8, x3, x1, x4) + +inst_9782: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xbc00; +op3val:0x7c00; valaddr_reg:x2; val_offset:29244*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29244*FLEN/8, x3, x1, x4) + +inst_9783: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xbc00; +op3val:0xfc00; valaddr_reg:x2; val_offset:29247*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29247*FLEN/8, x3, x1, x4) + +inst_9784: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xbc00; +op3val:0x7e00; valaddr_reg:x2; val_offset:29250*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29250*FLEN/8, x3, x1, x4) + +inst_9785: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xbc00; +op3val:0xfe00; valaddr_reg:x2; val_offset:29253*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29253*FLEN/8, x3, x1, x4) + +inst_9786: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xbc00; +op3val:0x7e01; valaddr_reg:x2; val_offset:29256*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29256*FLEN/8, x3, x1, x4) + +inst_9787: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xbc00; +op3val:0xfe55; valaddr_reg:x2; val_offset:29259*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29259*FLEN/8, x3, x1, x4) + +inst_9788: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xbc00; +op3val:0x7c01; valaddr_reg:x2; val_offset:29262*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29262*FLEN/8, x3, x1, x4) + +inst_9789: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xbc00; +op3val:0xfd55; valaddr_reg:x2; val_offset:29265*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29265*FLEN/8, x3, x1, x4) + +inst_9790: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xbc00; +op3val:0x3c00; valaddr_reg:x2; val_offset:29268*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29268*FLEN/8, x3, x1, x4) + +inst_9791: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e00; op2val:0xbc00; +op3val:0xbc00; valaddr_reg:x2; val_offset:29271*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29271*FLEN/8, x3, x1, x4) + +inst_9792: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x0; +op3val:0x0; valaddr_reg:x2; val_offset:29274*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29274*FLEN/8, x3, x1, x4) + +inst_9793: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x0; +op3val:0x8000; valaddr_reg:x2; val_offset:29277*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29277*FLEN/8, x3, x1, x4) + +inst_9794: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x0; +op3val:0x1; valaddr_reg:x2; val_offset:29280*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29280*FLEN/8, x3, x1, x4) + +inst_9795: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x0; +op3val:0x8001; valaddr_reg:x2; val_offset:29283*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29283*FLEN/8, x3, x1, x4) + +inst_9796: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x0; +op3val:0x2; valaddr_reg:x2; val_offset:29286*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29286*FLEN/8, x3, x1, x4) + +inst_9797: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x0; +op3val:0x83fe; valaddr_reg:x2; val_offset:29289*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29289*FLEN/8, x3, x1, x4) + +inst_9798: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x0; +op3val:0x3ff; valaddr_reg:x2; val_offset:29292*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29292*FLEN/8, x3, x1, x4) + +inst_9799: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x0; +op3val:0x83ff; valaddr_reg:x2; val_offset:29295*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29295*FLEN/8, x3, x1, x4) + +inst_9800: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x0; +op3val:0x400; valaddr_reg:x2; val_offset:29298*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29298*FLEN/8, x3, x1, x4) + +inst_9801: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x0; +op3val:0x8400; valaddr_reg:x2; val_offset:29301*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29301*FLEN/8, x3, x1, x4) + +inst_9802: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x0; +op3val:0x401; valaddr_reg:x2; val_offset:29304*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29304*FLEN/8, x3, x1, x4) + +inst_9803: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x0; +op3val:0x8455; valaddr_reg:x2; val_offset:29307*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29307*FLEN/8, x3, x1, x4) + +inst_9804: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x0; +op3val:0x7bff; valaddr_reg:x2; val_offset:29310*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29310*FLEN/8, x3, x1, x4) + +inst_9805: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x0; +op3val:0xfbff; valaddr_reg:x2; val_offset:29313*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29313*FLEN/8, x3, x1, x4) + +inst_9806: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x0; +op3val:0x7c00; valaddr_reg:x2; val_offset:29316*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29316*FLEN/8, x3, x1, x4) + +inst_9807: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x0; +op3val:0xfc00; valaddr_reg:x2; val_offset:29319*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29319*FLEN/8, x3, x1, x4) + +inst_9808: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x0; +op3val:0x7e00; valaddr_reg:x2; val_offset:29322*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29322*FLEN/8, x3, x1, x4) + +inst_9809: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x0; +op3val:0xfe00; valaddr_reg:x2; val_offset:29325*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29325*FLEN/8, x3, x1, x4) + +inst_9810: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x0; +op3val:0x7e01; valaddr_reg:x2; val_offset:29328*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29328*FLEN/8, x3, x1, x4) + +inst_9811: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x0; +op3val:0xfe55; valaddr_reg:x2; val_offset:29331*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29331*FLEN/8, x3, x1, x4) + +inst_9812: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x0; +op3val:0x7c01; valaddr_reg:x2; val_offset:29334*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29334*FLEN/8, x3, x1, x4) + +inst_9813: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x0; +op3val:0xfd55; valaddr_reg:x2; val_offset:29337*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29337*FLEN/8, x3, x1, x4) + +inst_9814: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x0; +op3val:0x3c00; valaddr_reg:x2; val_offset:29340*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29340*FLEN/8, x3, x1, x4) + +inst_9815: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x0; +op3val:0xbc00; valaddr_reg:x2; val_offset:29343*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29343*FLEN/8, x3, x1, x4) + +inst_9816: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8000; +op3val:0x0; valaddr_reg:x2; val_offset:29346*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29346*FLEN/8, x3, x1, x4) + +inst_9817: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8000; +op3val:0x8000; valaddr_reg:x2; val_offset:29349*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29349*FLEN/8, x3, x1, x4) + +inst_9818: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8000; +op3val:0x1; valaddr_reg:x2; val_offset:29352*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29352*FLEN/8, x3, x1, x4) + +inst_9819: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8000; +op3val:0x8001; valaddr_reg:x2; val_offset:29355*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29355*FLEN/8, x3, x1, x4) + +inst_9820: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8000; +op3val:0x2; valaddr_reg:x2; val_offset:29358*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29358*FLEN/8, x3, x1, x4) + +inst_9821: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8000; +op3val:0x83fe; valaddr_reg:x2; val_offset:29361*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29361*FLEN/8, x3, x1, x4) + +inst_9822: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8000; +op3val:0x3ff; valaddr_reg:x2; val_offset:29364*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29364*FLEN/8, x3, x1, x4) + +inst_9823: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8000; +op3val:0x83ff; valaddr_reg:x2; val_offset:29367*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29367*FLEN/8, x3, x1, x4) + +inst_9824: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8000; +op3val:0x400; valaddr_reg:x2; val_offset:29370*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29370*FLEN/8, x3, x1, x4) + +inst_9825: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8000; +op3val:0x8400; valaddr_reg:x2; val_offset:29373*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29373*FLEN/8, x3, x1, x4) + +inst_9826: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8000; +op3val:0x401; valaddr_reg:x2; val_offset:29376*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29376*FLEN/8, x3, x1, x4) + +inst_9827: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8000; +op3val:0x8455; valaddr_reg:x2; val_offset:29379*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29379*FLEN/8, x3, x1, x4) + +inst_9828: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x2; val_offset:29382*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29382*FLEN/8, x3, x1, x4) + +inst_9829: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x2; val_offset:29385*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29385*FLEN/8, x3, x1, x4) + +inst_9830: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8000; +op3val:0x7c00; valaddr_reg:x2; val_offset:29388*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29388*FLEN/8, x3, x1, x4) + +inst_9831: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8000; +op3val:0xfc00; valaddr_reg:x2; val_offset:29391*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29391*FLEN/8, x3, x1, x4) + +inst_9832: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8000; +op3val:0x7e00; valaddr_reg:x2; val_offset:29394*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29394*FLEN/8, x3, x1, x4) + +inst_9833: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8000; +op3val:0xfe00; valaddr_reg:x2; val_offset:29397*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29397*FLEN/8, x3, x1, x4) + +inst_9834: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8000; +op3val:0x7e01; valaddr_reg:x2; val_offset:29400*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29400*FLEN/8, x3, x1, x4) + +inst_9835: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8000; +op3val:0xfe55; valaddr_reg:x2; val_offset:29403*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29403*FLEN/8, x3, x1, x4) + +inst_9836: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8000; +op3val:0x7c01; valaddr_reg:x2; val_offset:29406*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29406*FLEN/8, x3, x1, x4) + +inst_9837: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8000; +op3val:0xfd55; valaddr_reg:x2; val_offset:29409*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29409*FLEN/8, x3, x1, x4) + +inst_9838: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8000; +op3val:0x3c00; valaddr_reg:x2; val_offset:29412*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29412*FLEN/8, x3, x1, x4) + +inst_9839: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8000; +op3val:0xbc00; valaddr_reg:x2; val_offset:29415*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29415*FLEN/8, x3, x1, x4) + +inst_9840: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x1; +op3val:0x0; valaddr_reg:x2; val_offset:29418*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29418*FLEN/8, x3, x1, x4) + +inst_9841: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x1; +op3val:0x8000; valaddr_reg:x2; val_offset:29421*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29421*FLEN/8, x3, x1, x4) + +inst_9842: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x1; +op3val:0x1; valaddr_reg:x2; val_offset:29424*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29424*FLEN/8, x3, x1, x4) + +inst_9843: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x1; +op3val:0x8001; valaddr_reg:x2; val_offset:29427*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29427*FLEN/8, x3, x1, x4) + +inst_9844: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x1; +op3val:0x2; valaddr_reg:x2; val_offset:29430*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29430*FLEN/8, x3, x1, x4) + +inst_9845: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x1; +op3val:0x83fe; valaddr_reg:x2; val_offset:29433*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29433*FLEN/8, x3, x1, x4) + +inst_9846: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x1; +op3val:0x3ff; valaddr_reg:x2; val_offset:29436*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29436*FLEN/8, x3, x1, x4) + +inst_9847: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x1; +op3val:0x83ff; valaddr_reg:x2; val_offset:29439*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29439*FLEN/8, x3, x1, x4) + +inst_9848: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x1; +op3val:0x400; valaddr_reg:x2; val_offset:29442*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29442*FLEN/8, x3, x1, x4) + +inst_9849: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x1; +op3val:0x8400; valaddr_reg:x2; val_offset:29445*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29445*FLEN/8, x3, x1, x4) + +inst_9850: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x1; +op3val:0x401; valaddr_reg:x2; val_offset:29448*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29448*FLEN/8, x3, x1, x4) + +inst_9851: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x1; +op3val:0x8455; valaddr_reg:x2; val_offset:29451*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29451*FLEN/8, x3, x1, x4) + +inst_9852: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x1; +op3val:0x7bff; valaddr_reg:x2; val_offset:29454*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29454*FLEN/8, x3, x1, x4) + +inst_9853: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x1; +op3val:0xfbff; valaddr_reg:x2; val_offset:29457*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29457*FLEN/8, x3, x1, x4) + +inst_9854: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x1; +op3val:0x7c00; valaddr_reg:x2; val_offset:29460*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29460*FLEN/8, x3, x1, x4) + +inst_9855: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x1; +op3val:0xfc00; valaddr_reg:x2; val_offset:29463*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29463*FLEN/8, x3, x1, x4) + +inst_9856: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x1; +op3val:0x7e00; valaddr_reg:x2; val_offset:29466*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29466*FLEN/8, x3, x1, x4) + +inst_9857: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x1; +op3val:0xfe00; valaddr_reg:x2; val_offset:29469*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29469*FLEN/8, x3, x1, x4) + +inst_9858: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x1; +op3val:0x7e01; valaddr_reg:x2; val_offset:29472*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29472*FLEN/8, x3, x1, x4) + +inst_9859: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x1; +op3val:0xfe55; valaddr_reg:x2; val_offset:29475*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29475*FLEN/8, x3, x1, x4) + +inst_9860: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x1; +op3val:0x7c01; valaddr_reg:x2; val_offset:29478*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29478*FLEN/8, x3, x1, x4) + +inst_9861: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x1; +op3val:0xfd55; valaddr_reg:x2; val_offset:29481*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29481*FLEN/8, x3, x1, x4) + +inst_9862: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x1; +op3val:0x3c00; valaddr_reg:x2; val_offset:29484*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29484*FLEN/8, x3, x1, x4) + +inst_9863: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x1; +op3val:0xbc00; valaddr_reg:x2; val_offset:29487*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29487*FLEN/8, x3, x1, x4) + +inst_9864: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8001; +op3val:0x0; valaddr_reg:x2; val_offset:29490*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29490*FLEN/8, x3, x1, x4) + +inst_9865: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8001; +op3val:0x8000; valaddr_reg:x2; val_offset:29493*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29493*FLEN/8, x3, x1, x4) + +inst_9866: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8001; +op3val:0x1; valaddr_reg:x2; val_offset:29496*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29496*FLEN/8, x3, x1, x4) + +inst_9867: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8001; +op3val:0x8001; valaddr_reg:x2; val_offset:29499*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29499*FLEN/8, x3, x1, x4) + +inst_9868: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8001; +op3val:0x2; valaddr_reg:x2; val_offset:29502*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29502*FLEN/8, x3, x1, x4) + +inst_9869: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8001; +op3val:0x83fe; valaddr_reg:x2; val_offset:29505*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29505*FLEN/8, x3, x1, x4) + +inst_9870: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8001; +op3val:0x3ff; valaddr_reg:x2; val_offset:29508*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29508*FLEN/8, x3, x1, x4) + +inst_9871: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8001; +op3val:0x83ff; valaddr_reg:x2; val_offset:29511*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29511*FLEN/8, x3, x1, x4) + +inst_9872: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8001; +op3val:0x400; valaddr_reg:x2; val_offset:29514*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29514*FLEN/8, x3, x1, x4) + +inst_9873: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8001; +op3val:0x8400; valaddr_reg:x2; val_offset:29517*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29517*FLEN/8, x3, x1, x4) + +inst_9874: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8001; +op3val:0x401; valaddr_reg:x2; val_offset:29520*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29520*FLEN/8, x3, x1, x4) + +inst_9875: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8001; +op3val:0x8455; valaddr_reg:x2; val_offset:29523*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29523*FLEN/8, x3, x1, x4) + +inst_9876: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8001; +op3val:0x7bff; valaddr_reg:x2; val_offset:29526*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29526*FLEN/8, x3, x1, x4) + +inst_9877: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8001; +op3val:0xfbff; valaddr_reg:x2; val_offset:29529*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29529*FLEN/8, x3, x1, x4) + +inst_9878: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8001; +op3val:0x7c00; valaddr_reg:x2; val_offset:29532*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29532*FLEN/8, x3, x1, x4) + +inst_9879: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8001; +op3val:0xfc00; valaddr_reg:x2; val_offset:29535*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29535*FLEN/8, x3, x1, x4) + +inst_9880: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8001; +op3val:0x7e00; valaddr_reg:x2; val_offset:29538*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29538*FLEN/8, x3, x1, x4) + +inst_9881: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8001; +op3val:0xfe00; valaddr_reg:x2; val_offset:29541*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29541*FLEN/8, x3, x1, x4) + +inst_9882: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8001; +op3val:0x7e01; valaddr_reg:x2; val_offset:29544*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29544*FLEN/8, x3, x1, x4) + +inst_9883: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8001; +op3val:0xfe55; valaddr_reg:x2; val_offset:29547*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29547*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_78) + +inst_9884: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8001; +op3val:0x7c01; valaddr_reg:x2; val_offset:29550*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29550*FLEN/8, x3, x1, x4) + +inst_9885: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8001; +op3val:0xfd55; valaddr_reg:x2; val_offset:29553*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29553*FLEN/8, x3, x1, x4) + +inst_9886: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8001; +op3val:0x3c00; valaddr_reg:x2; val_offset:29556*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29556*FLEN/8, x3, x1, x4) + +inst_9887: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8001; +op3val:0xbc00; valaddr_reg:x2; val_offset:29559*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29559*FLEN/8, x3, x1, x4) + +inst_9888: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x2; +op3val:0x0; valaddr_reg:x2; val_offset:29562*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29562*FLEN/8, x3, x1, x4) + +inst_9889: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x2; +op3val:0x8000; valaddr_reg:x2; val_offset:29565*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29565*FLEN/8, x3, x1, x4) + +inst_9890: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x2; +op3val:0x1; valaddr_reg:x2; val_offset:29568*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29568*FLEN/8, x3, x1, x4) + +inst_9891: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x2; +op3val:0x8001; valaddr_reg:x2; val_offset:29571*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29571*FLEN/8, x3, x1, x4) + +inst_9892: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x2; +op3val:0x2; valaddr_reg:x2; val_offset:29574*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29574*FLEN/8, x3, x1, x4) + +inst_9893: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x2; +op3val:0x83fe; valaddr_reg:x2; val_offset:29577*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29577*FLEN/8, x3, x1, x4) + +inst_9894: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x2; +op3val:0x3ff; valaddr_reg:x2; val_offset:29580*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29580*FLEN/8, x3, x1, x4) + +inst_9895: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x2; +op3val:0x83ff; valaddr_reg:x2; val_offset:29583*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29583*FLEN/8, x3, x1, x4) + +inst_9896: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x2; +op3val:0x400; valaddr_reg:x2; val_offset:29586*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29586*FLEN/8, x3, x1, x4) + +inst_9897: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x2; +op3val:0x8400; valaddr_reg:x2; val_offset:29589*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29589*FLEN/8, x3, x1, x4) + +inst_9898: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x2; +op3val:0x401; valaddr_reg:x2; val_offset:29592*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29592*FLEN/8, x3, x1, x4) + +inst_9899: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x2; +op3val:0x8455; valaddr_reg:x2; val_offset:29595*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29595*FLEN/8, x3, x1, x4) + +inst_9900: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x2; +op3val:0x7bff; valaddr_reg:x2; val_offset:29598*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29598*FLEN/8, x3, x1, x4) + +inst_9901: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x2; +op3val:0xfbff; valaddr_reg:x2; val_offset:29601*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29601*FLEN/8, x3, x1, x4) + +inst_9902: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x2; +op3val:0x7c00; valaddr_reg:x2; val_offset:29604*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29604*FLEN/8, x3, x1, x4) + +inst_9903: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x2; +op3val:0xfc00; valaddr_reg:x2; val_offset:29607*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29607*FLEN/8, x3, x1, x4) + +inst_9904: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x2; +op3val:0x7e00; valaddr_reg:x2; val_offset:29610*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29610*FLEN/8, x3, x1, x4) + +inst_9905: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x2; +op3val:0xfe00; valaddr_reg:x2; val_offset:29613*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29613*FLEN/8, x3, x1, x4) + +inst_9906: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x2; +op3val:0x7e01; valaddr_reg:x2; val_offset:29616*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29616*FLEN/8, x3, x1, x4) + +inst_9907: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x2; +op3val:0xfe55; valaddr_reg:x2; val_offset:29619*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29619*FLEN/8, x3, x1, x4) + +inst_9908: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x2; +op3val:0x7c01; valaddr_reg:x2; val_offset:29622*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29622*FLEN/8, x3, x1, x4) + +inst_9909: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x2; +op3val:0xfd55; valaddr_reg:x2; val_offset:29625*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29625*FLEN/8, x3, x1, x4) + +inst_9910: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x2; +op3val:0x3c00; valaddr_reg:x2; val_offset:29628*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29628*FLEN/8, x3, x1, x4) + +inst_9911: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x2; +op3val:0xbc00; valaddr_reg:x2; val_offset:29631*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29631*FLEN/8, x3, x1, x4) + +inst_9912: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x83fe; +op3val:0x0; valaddr_reg:x2; val_offset:29634*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29634*FLEN/8, x3, x1, x4) + +inst_9913: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x83fe; +op3val:0x8000; valaddr_reg:x2; val_offset:29637*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29637*FLEN/8, x3, x1, x4) + +inst_9914: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x83fe; +op3val:0x1; valaddr_reg:x2; val_offset:29640*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29640*FLEN/8, x3, x1, x4) + +inst_9915: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x83fe; +op3val:0x8001; valaddr_reg:x2; val_offset:29643*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29643*FLEN/8, x3, x1, x4) + +inst_9916: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x83fe; +op3val:0x2; valaddr_reg:x2; val_offset:29646*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29646*FLEN/8, x3, x1, x4) + +inst_9917: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x83fe; +op3val:0x83fe; valaddr_reg:x2; val_offset:29649*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29649*FLEN/8, x3, x1, x4) + +inst_9918: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x83fe; +op3val:0x3ff; valaddr_reg:x2; val_offset:29652*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29652*FLEN/8, x3, x1, x4) + +inst_9919: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x83fe; +op3val:0x83ff; valaddr_reg:x2; val_offset:29655*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29655*FLEN/8, x3, x1, x4) + +inst_9920: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x83fe; +op3val:0x400; valaddr_reg:x2; val_offset:29658*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29658*FLEN/8, x3, x1, x4) + +inst_9921: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x83fe; +op3val:0x8400; valaddr_reg:x2; val_offset:29661*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29661*FLEN/8, x3, x1, x4) + +inst_9922: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x83fe; +op3val:0x401; valaddr_reg:x2; val_offset:29664*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29664*FLEN/8, x3, x1, x4) + +inst_9923: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x83fe; +op3val:0x8455; valaddr_reg:x2; val_offset:29667*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29667*FLEN/8, x3, x1, x4) + +inst_9924: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x83fe; +op3val:0x7bff; valaddr_reg:x2; val_offset:29670*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29670*FLEN/8, x3, x1, x4) + +inst_9925: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x83fe; +op3val:0xfbff; valaddr_reg:x2; val_offset:29673*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29673*FLEN/8, x3, x1, x4) + +inst_9926: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x83fe; +op3val:0x7c00; valaddr_reg:x2; val_offset:29676*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29676*FLEN/8, x3, x1, x4) + +inst_9927: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x83fe; +op3val:0xfc00; valaddr_reg:x2; val_offset:29679*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29679*FLEN/8, x3, x1, x4) + +inst_9928: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x83fe; +op3val:0x7e00; valaddr_reg:x2; val_offset:29682*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29682*FLEN/8, x3, x1, x4) + +inst_9929: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x83fe; +op3val:0xfe00; valaddr_reg:x2; val_offset:29685*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29685*FLEN/8, x3, x1, x4) + +inst_9930: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x83fe; +op3val:0x7e01; valaddr_reg:x2; val_offset:29688*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29688*FLEN/8, x3, x1, x4) + +inst_9931: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x83fe; +op3val:0xfe55; valaddr_reg:x2; val_offset:29691*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29691*FLEN/8, x3, x1, x4) + +inst_9932: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x83fe; +op3val:0x7c01; valaddr_reg:x2; val_offset:29694*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29694*FLEN/8, x3, x1, x4) + +inst_9933: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x83fe; +op3val:0xfd55; valaddr_reg:x2; val_offset:29697*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29697*FLEN/8, x3, x1, x4) + +inst_9934: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x83fe; +op3val:0x3c00; valaddr_reg:x2; val_offset:29700*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29700*FLEN/8, x3, x1, x4) + +inst_9935: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x83fe; +op3val:0xbc00; valaddr_reg:x2; val_offset:29703*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29703*FLEN/8, x3, x1, x4) + +inst_9936: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x3ff; +op3val:0x0; valaddr_reg:x2; val_offset:29706*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29706*FLEN/8, x3, x1, x4) + +inst_9937: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x3ff; +op3val:0x8000; valaddr_reg:x2; val_offset:29709*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29709*FLEN/8, x3, x1, x4) + +inst_9938: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x3ff; +op3val:0x1; valaddr_reg:x2; val_offset:29712*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29712*FLEN/8, x3, x1, x4) + +inst_9939: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x3ff; +op3val:0x8001; valaddr_reg:x2; val_offset:29715*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29715*FLEN/8, x3, x1, x4) + +inst_9940: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x3ff; +op3val:0x2; valaddr_reg:x2; val_offset:29718*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29718*FLEN/8, x3, x1, x4) + +inst_9941: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x3ff; +op3val:0x83fe; valaddr_reg:x2; val_offset:29721*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29721*FLEN/8, x3, x1, x4) + +inst_9942: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x3ff; +op3val:0x3ff; valaddr_reg:x2; val_offset:29724*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29724*FLEN/8, x3, x1, x4) + +inst_9943: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x3ff; +op3val:0x83ff; valaddr_reg:x2; val_offset:29727*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29727*FLEN/8, x3, x1, x4) + +inst_9944: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x3ff; +op3val:0x400; valaddr_reg:x2; val_offset:29730*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29730*FLEN/8, x3, x1, x4) + +inst_9945: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x3ff; +op3val:0x8400; valaddr_reg:x2; val_offset:29733*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29733*FLEN/8, x3, x1, x4) + +inst_9946: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x3ff; +op3val:0x401; valaddr_reg:x2; val_offset:29736*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29736*FLEN/8, x3, x1, x4) + +inst_9947: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x3ff; +op3val:0x8455; valaddr_reg:x2; val_offset:29739*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29739*FLEN/8, x3, x1, x4) + +inst_9948: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x3ff; +op3val:0x7bff; valaddr_reg:x2; val_offset:29742*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29742*FLEN/8, x3, x1, x4) + +inst_9949: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x3ff; +op3val:0xfbff; valaddr_reg:x2; val_offset:29745*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29745*FLEN/8, x3, x1, x4) + +inst_9950: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x3ff; +op3val:0x7c00; valaddr_reg:x2; val_offset:29748*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29748*FLEN/8, x3, x1, x4) + +inst_9951: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x3ff; +op3val:0xfc00; valaddr_reg:x2; val_offset:29751*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29751*FLEN/8, x3, x1, x4) + +inst_9952: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x3ff; +op3val:0x7e00; valaddr_reg:x2; val_offset:29754*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29754*FLEN/8, x3, x1, x4) + +inst_9953: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x3ff; +op3val:0xfe00; valaddr_reg:x2; val_offset:29757*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29757*FLEN/8, x3, x1, x4) + +inst_9954: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x3ff; +op3val:0x7e01; valaddr_reg:x2; val_offset:29760*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29760*FLEN/8, x3, x1, x4) + +inst_9955: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x3ff; +op3val:0xfe55; valaddr_reg:x2; val_offset:29763*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29763*FLEN/8, x3, x1, x4) + +inst_9956: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x3ff; +op3val:0x7c01; valaddr_reg:x2; val_offset:29766*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29766*FLEN/8, x3, x1, x4) + +inst_9957: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x3ff; +op3val:0xfd55; valaddr_reg:x2; val_offset:29769*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29769*FLEN/8, x3, x1, x4) + +inst_9958: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x3ff; +op3val:0x3c00; valaddr_reg:x2; val_offset:29772*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29772*FLEN/8, x3, x1, x4) + +inst_9959: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x3ff; +op3val:0xbc00; valaddr_reg:x2; val_offset:29775*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29775*FLEN/8, x3, x1, x4) + +inst_9960: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x83ff; +op3val:0x0; valaddr_reg:x2; val_offset:29778*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29778*FLEN/8, x3, x1, x4) + +inst_9961: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x83ff; +op3val:0x8000; valaddr_reg:x2; val_offset:29781*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29781*FLEN/8, x3, x1, x4) + +inst_9962: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x83ff; +op3val:0x1; valaddr_reg:x2; val_offset:29784*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29784*FLEN/8, x3, x1, x4) + +inst_9963: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x83ff; +op3val:0x8001; valaddr_reg:x2; val_offset:29787*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29787*FLEN/8, x3, x1, x4) + +inst_9964: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x83ff; +op3val:0x2; valaddr_reg:x2; val_offset:29790*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29790*FLEN/8, x3, x1, x4) + +inst_9965: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x83ff; +op3val:0x83fe; valaddr_reg:x2; val_offset:29793*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29793*FLEN/8, x3, x1, x4) + +inst_9966: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x83ff; +op3val:0x3ff; valaddr_reg:x2; val_offset:29796*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29796*FLEN/8, x3, x1, x4) + +inst_9967: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x83ff; +op3val:0x83ff; valaddr_reg:x2; val_offset:29799*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29799*FLEN/8, x3, x1, x4) + +inst_9968: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x83ff; +op3val:0x400; valaddr_reg:x2; val_offset:29802*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29802*FLEN/8, x3, x1, x4) + +inst_9969: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x83ff; +op3val:0x8400; valaddr_reg:x2; val_offset:29805*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29805*FLEN/8, x3, x1, x4) + +inst_9970: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x83ff; +op3val:0x401; valaddr_reg:x2; val_offset:29808*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29808*FLEN/8, x3, x1, x4) + +inst_9971: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x83ff; +op3val:0x8455; valaddr_reg:x2; val_offset:29811*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29811*FLEN/8, x3, x1, x4) + +inst_9972: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x83ff; +op3val:0x7bff; valaddr_reg:x2; val_offset:29814*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29814*FLEN/8, x3, x1, x4) + +inst_9973: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x83ff; +op3val:0xfbff; valaddr_reg:x2; val_offset:29817*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29817*FLEN/8, x3, x1, x4) + +inst_9974: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x83ff; +op3val:0x7c00; valaddr_reg:x2; val_offset:29820*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29820*FLEN/8, x3, x1, x4) + +inst_9975: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x83ff; +op3val:0xfc00; valaddr_reg:x2; val_offset:29823*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29823*FLEN/8, x3, x1, x4) + +inst_9976: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x83ff; +op3val:0x7e00; valaddr_reg:x2; val_offset:29826*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29826*FLEN/8, x3, x1, x4) + +inst_9977: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x83ff; +op3val:0xfe00; valaddr_reg:x2; val_offset:29829*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29829*FLEN/8, x3, x1, x4) + +inst_9978: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x83ff; +op3val:0x7e01; valaddr_reg:x2; val_offset:29832*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29832*FLEN/8, x3, x1, x4) + +inst_9979: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x83ff; +op3val:0xfe55; valaddr_reg:x2; val_offset:29835*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29835*FLEN/8, x3, x1, x4) + +inst_9980: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x83ff; +op3val:0x7c01; valaddr_reg:x2; val_offset:29838*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29838*FLEN/8, x3, x1, x4) + +inst_9981: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x83ff; +op3val:0xfd55; valaddr_reg:x2; val_offset:29841*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29841*FLEN/8, x3, x1, x4) + +inst_9982: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x83ff; +op3val:0x3c00; valaddr_reg:x2; val_offset:29844*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29844*FLEN/8, x3, x1, x4) + +inst_9983: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x83ff; +op3val:0xbc00; valaddr_reg:x2; val_offset:29847*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29847*FLEN/8, x3, x1, x4) + +inst_9984: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x400; +op3val:0x0; valaddr_reg:x2; val_offset:29850*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29850*FLEN/8, x3, x1, x4) + +inst_9985: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x400; +op3val:0x8000; valaddr_reg:x2; val_offset:29853*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29853*FLEN/8, x3, x1, x4) + +inst_9986: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x400; +op3val:0x1; valaddr_reg:x2; val_offset:29856*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29856*FLEN/8, x3, x1, x4) + +inst_9987: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x400; +op3val:0x8001; valaddr_reg:x2; val_offset:29859*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29859*FLEN/8, x3, x1, x4) + +inst_9988: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x400; +op3val:0x2; valaddr_reg:x2; val_offset:29862*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29862*FLEN/8, x3, x1, x4) + +inst_9989: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x400; +op3val:0x83fe; valaddr_reg:x2; val_offset:29865*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29865*FLEN/8, x3, x1, x4) + +inst_9990: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x400; +op3val:0x3ff; valaddr_reg:x2; val_offset:29868*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29868*FLEN/8, x3, x1, x4) + +inst_9991: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x400; +op3val:0x83ff; valaddr_reg:x2; val_offset:29871*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29871*FLEN/8, x3, x1, x4) + +inst_9992: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x400; +op3val:0x400; valaddr_reg:x2; val_offset:29874*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29874*FLEN/8, x3, x1, x4) + +inst_9993: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x400; +op3val:0x8400; valaddr_reg:x2; val_offset:29877*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29877*FLEN/8, x3, x1, x4) + +inst_9994: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x400; +op3val:0x401; valaddr_reg:x2; val_offset:29880*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29880*FLEN/8, x3, x1, x4) + +inst_9995: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x400; +op3val:0x8455; valaddr_reg:x2; val_offset:29883*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29883*FLEN/8, x3, x1, x4) + +inst_9996: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x400; +op3val:0x7bff; valaddr_reg:x2; val_offset:29886*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29886*FLEN/8, x3, x1, x4) + +inst_9997: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x400; +op3val:0xfbff; valaddr_reg:x2; val_offset:29889*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29889*FLEN/8, x3, x1, x4) + +inst_9998: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x400; +op3val:0x7c00; valaddr_reg:x2; val_offset:29892*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29892*FLEN/8, x3, x1, x4) + +inst_9999: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x400; +op3val:0xfc00; valaddr_reg:x2; val_offset:29895*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29895*FLEN/8, x3, x1, x4) + +inst_10000: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x400; +op3val:0x7e00; valaddr_reg:x2; val_offset:29898*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29898*FLEN/8, x3, x1, x4) + +inst_10001: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x400; +op3val:0xfe00; valaddr_reg:x2; val_offset:29901*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29901*FLEN/8, x3, x1, x4) + +inst_10002: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x400; +op3val:0x7e01; valaddr_reg:x2; val_offset:29904*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29904*FLEN/8, x3, x1, x4) + +inst_10003: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x400; +op3val:0xfe55; valaddr_reg:x2; val_offset:29907*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29907*FLEN/8, x3, x1, x4) + +inst_10004: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x400; +op3val:0x7c01; valaddr_reg:x2; val_offset:29910*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29910*FLEN/8, x3, x1, x4) + +inst_10005: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x400; +op3val:0xfd55; valaddr_reg:x2; val_offset:29913*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29913*FLEN/8, x3, x1, x4) + +inst_10006: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x400; +op3val:0x3c00; valaddr_reg:x2; val_offset:29916*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29916*FLEN/8, x3, x1, x4) + +inst_10007: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x400; +op3val:0xbc00; valaddr_reg:x2; val_offset:29919*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29919*FLEN/8, x3, x1, x4) + +inst_10008: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8400; +op3val:0x0; valaddr_reg:x2; val_offset:29922*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29922*FLEN/8, x3, x1, x4) + +inst_10009: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8400; +op3val:0x8000; valaddr_reg:x2; val_offset:29925*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29925*FLEN/8, x3, x1, x4) + +inst_10010: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8400; +op3val:0x1; valaddr_reg:x2; val_offset:29928*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29928*FLEN/8, x3, x1, x4) + +inst_10011: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8400; +op3val:0x8001; valaddr_reg:x2; val_offset:29931*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29931*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_79) + +inst_10012: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8400; +op3val:0x2; valaddr_reg:x2; val_offset:29934*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29934*FLEN/8, x3, x1, x4) + +inst_10013: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8400; +op3val:0x83fe; valaddr_reg:x2; val_offset:29937*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29937*FLEN/8, x3, x1, x4) + +inst_10014: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8400; +op3val:0x3ff; valaddr_reg:x2; val_offset:29940*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29940*FLEN/8, x3, x1, x4) + +inst_10015: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8400; +op3val:0x83ff; valaddr_reg:x2; val_offset:29943*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29943*FLEN/8, x3, x1, x4) + +inst_10016: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8400; +op3val:0x400; valaddr_reg:x2; val_offset:29946*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29946*FLEN/8, x3, x1, x4) + +inst_10017: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8400; +op3val:0x8400; valaddr_reg:x2; val_offset:29949*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29949*FLEN/8, x3, x1, x4) + +inst_10018: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8400; +op3val:0x401; valaddr_reg:x2; val_offset:29952*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29952*FLEN/8, x3, x1, x4) + +inst_10019: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8400; +op3val:0x8455; valaddr_reg:x2; val_offset:29955*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29955*FLEN/8, x3, x1, x4) + +inst_10020: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8400; +op3val:0x7bff; valaddr_reg:x2; val_offset:29958*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29958*FLEN/8, x3, x1, x4) + +inst_10021: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8400; +op3val:0xfbff; valaddr_reg:x2; val_offset:29961*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29961*FLEN/8, x3, x1, x4) + +inst_10022: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8400; +op3val:0x7c00; valaddr_reg:x2; val_offset:29964*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29964*FLEN/8, x3, x1, x4) + +inst_10023: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8400; +op3val:0xfc00; valaddr_reg:x2; val_offset:29967*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29967*FLEN/8, x3, x1, x4) + +inst_10024: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8400; +op3val:0x7e00; valaddr_reg:x2; val_offset:29970*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29970*FLEN/8, x3, x1, x4) + +inst_10025: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8400; +op3val:0xfe00; valaddr_reg:x2; val_offset:29973*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29973*FLEN/8, x3, x1, x4) + +inst_10026: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8400; +op3val:0x7e01; valaddr_reg:x2; val_offset:29976*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29976*FLEN/8, x3, x1, x4) + +inst_10027: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8400; +op3val:0xfe55; valaddr_reg:x2; val_offset:29979*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29979*FLEN/8, x3, x1, x4) + +inst_10028: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8400; +op3val:0x7c01; valaddr_reg:x2; val_offset:29982*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29982*FLEN/8, x3, x1, x4) + +inst_10029: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8400; +op3val:0xfd55; valaddr_reg:x2; val_offset:29985*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29985*FLEN/8, x3, x1, x4) + +inst_10030: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8400; +op3val:0x3c00; valaddr_reg:x2; val_offset:29988*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29988*FLEN/8, x3, x1, x4) + +inst_10031: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8400; +op3val:0xbc00; valaddr_reg:x2; val_offset:29991*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29991*FLEN/8, x3, x1, x4) + +inst_10032: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x401; +op3val:0x0; valaddr_reg:x2; val_offset:29994*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29994*FLEN/8, x3, x1, x4) + +inst_10033: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x401; +op3val:0x8000; valaddr_reg:x2; val_offset:29997*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 29997*FLEN/8, x3, x1, x4) + +inst_10034: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x401; +op3val:0x1; valaddr_reg:x2; val_offset:30000*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30000*FLEN/8, x3, x1, x4) + +inst_10035: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x401; +op3val:0x8001; valaddr_reg:x2; val_offset:30003*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30003*FLEN/8, x3, x1, x4) + +inst_10036: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x401; +op3val:0x2; valaddr_reg:x2; val_offset:30006*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30006*FLEN/8, x3, x1, x4) + +inst_10037: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x401; +op3val:0x83fe; valaddr_reg:x2; val_offset:30009*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30009*FLEN/8, x3, x1, x4) + +inst_10038: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x401; +op3val:0x3ff; valaddr_reg:x2; val_offset:30012*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30012*FLEN/8, x3, x1, x4) + +inst_10039: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x401; +op3val:0x83ff; valaddr_reg:x2; val_offset:30015*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30015*FLEN/8, x3, x1, x4) + +inst_10040: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x401; +op3val:0x400; valaddr_reg:x2; val_offset:30018*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30018*FLEN/8, x3, x1, x4) + +inst_10041: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x401; +op3val:0x8400; valaddr_reg:x2; val_offset:30021*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30021*FLEN/8, x3, x1, x4) + +inst_10042: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x401; +op3val:0x401; valaddr_reg:x2; val_offset:30024*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30024*FLEN/8, x3, x1, x4) + +inst_10043: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x401; +op3val:0x8455; valaddr_reg:x2; val_offset:30027*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30027*FLEN/8, x3, x1, x4) + +inst_10044: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x401; +op3val:0x7bff; valaddr_reg:x2; val_offset:30030*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30030*FLEN/8, x3, x1, x4) + +inst_10045: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x401; +op3val:0xfbff; valaddr_reg:x2; val_offset:30033*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30033*FLEN/8, x3, x1, x4) + +inst_10046: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x401; +op3val:0x7c00; valaddr_reg:x2; val_offset:30036*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30036*FLEN/8, x3, x1, x4) + +inst_10047: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x401; +op3val:0xfc00; valaddr_reg:x2; val_offset:30039*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30039*FLEN/8, x3, x1, x4) + +inst_10048: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x401; +op3val:0x7e00; valaddr_reg:x2; val_offset:30042*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30042*FLEN/8, x3, x1, x4) + +inst_10049: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x401; +op3val:0xfe00; valaddr_reg:x2; val_offset:30045*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30045*FLEN/8, x3, x1, x4) + +inst_10050: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x401; +op3val:0x7e01; valaddr_reg:x2; val_offset:30048*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30048*FLEN/8, x3, x1, x4) + +inst_10051: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x401; +op3val:0xfe55; valaddr_reg:x2; val_offset:30051*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30051*FLEN/8, x3, x1, x4) + +inst_10052: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x401; +op3val:0x7c01; valaddr_reg:x2; val_offset:30054*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30054*FLEN/8, x3, x1, x4) + +inst_10053: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x401; +op3val:0xfd55; valaddr_reg:x2; val_offset:30057*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30057*FLEN/8, x3, x1, x4) + +inst_10054: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x401; +op3val:0x3c00; valaddr_reg:x2; val_offset:30060*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30060*FLEN/8, x3, x1, x4) + +inst_10055: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x401; +op3val:0xbc00; valaddr_reg:x2; val_offset:30063*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30063*FLEN/8, x3, x1, x4) + +inst_10056: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8455; +op3val:0x0; valaddr_reg:x2; val_offset:30066*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30066*FLEN/8, x3, x1, x4) + +inst_10057: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8455; +op3val:0x8000; valaddr_reg:x2; val_offset:30069*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30069*FLEN/8, x3, x1, x4) + +inst_10058: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8455; +op3val:0x1; valaddr_reg:x2; val_offset:30072*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30072*FLEN/8, x3, x1, x4) + +inst_10059: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8455; +op3val:0x8001; valaddr_reg:x2; val_offset:30075*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30075*FLEN/8, x3, x1, x4) + +inst_10060: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8455; +op3val:0x2; valaddr_reg:x2; val_offset:30078*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30078*FLEN/8, x3, x1, x4) + +inst_10061: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8455; +op3val:0x83fe; valaddr_reg:x2; val_offset:30081*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30081*FLEN/8, x3, x1, x4) + +inst_10062: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8455; +op3val:0x3ff; valaddr_reg:x2; val_offset:30084*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30084*FLEN/8, x3, x1, x4) + +inst_10063: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8455; +op3val:0x83ff; valaddr_reg:x2; val_offset:30087*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30087*FLEN/8, x3, x1, x4) + +inst_10064: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8455; +op3val:0x400; valaddr_reg:x2; val_offset:30090*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30090*FLEN/8, x3, x1, x4) + +inst_10065: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8455; +op3val:0x8400; valaddr_reg:x2; val_offset:30093*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30093*FLEN/8, x3, x1, x4) + +inst_10066: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8455; +op3val:0x401; valaddr_reg:x2; val_offset:30096*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30096*FLEN/8, x3, x1, x4) + +inst_10067: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8455; +op3val:0x8455; valaddr_reg:x2; val_offset:30099*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30099*FLEN/8, x3, x1, x4) + +inst_10068: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8455; +op3val:0x7bff; valaddr_reg:x2; val_offset:30102*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30102*FLEN/8, x3, x1, x4) + +inst_10069: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8455; +op3val:0xfbff; valaddr_reg:x2; val_offset:30105*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30105*FLEN/8, x3, x1, x4) + +inst_10070: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8455; +op3val:0x7c00; valaddr_reg:x2; val_offset:30108*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30108*FLEN/8, x3, x1, x4) + +inst_10071: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8455; +op3val:0xfc00; valaddr_reg:x2; val_offset:30111*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30111*FLEN/8, x3, x1, x4) + +inst_10072: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8455; +op3val:0x7e00; valaddr_reg:x2; val_offset:30114*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30114*FLEN/8, x3, x1, x4) + +inst_10073: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8455; +op3val:0xfe00; valaddr_reg:x2; val_offset:30117*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30117*FLEN/8, x3, x1, x4) + +inst_10074: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8455; +op3val:0x7e01; valaddr_reg:x2; val_offset:30120*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30120*FLEN/8, x3, x1, x4) + +inst_10075: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8455; +op3val:0xfe55; valaddr_reg:x2; val_offset:30123*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30123*FLEN/8, x3, x1, x4) + +inst_10076: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8455; +op3val:0x7c01; valaddr_reg:x2; val_offset:30126*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30126*FLEN/8, x3, x1, x4) + +inst_10077: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8455; +op3val:0xfd55; valaddr_reg:x2; val_offset:30129*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30129*FLEN/8, x3, x1, x4) + +inst_10078: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8455; +op3val:0x3c00; valaddr_reg:x2; val_offset:30132*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30132*FLEN/8, x3, x1, x4) + +inst_10079: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x8455; +op3val:0xbc00; valaddr_reg:x2; val_offset:30135*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30135*FLEN/8, x3, x1, x4) + +inst_10080: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7bff; +op3val:0x0; valaddr_reg:x2; val_offset:30138*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30138*FLEN/8, x3, x1, x4) + +inst_10081: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7bff; +op3val:0x8000; valaddr_reg:x2; val_offset:30141*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30141*FLEN/8, x3, x1, x4) + +inst_10082: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7bff; +op3val:0x1; valaddr_reg:x2; val_offset:30144*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30144*FLEN/8, x3, x1, x4) + +inst_10083: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7bff; +op3val:0x8001; valaddr_reg:x2; val_offset:30147*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30147*FLEN/8, x3, x1, x4) + +inst_10084: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7bff; +op3val:0x2; valaddr_reg:x2; val_offset:30150*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30150*FLEN/8, x3, x1, x4) + +inst_10085: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7bff; +op3val:0x83fe; valaddr_reg:x2; val_offset:30153*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30153*FLEN/8, x3, x1, x4) + +inst_10086: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7bff; +op3val:0x3ff; valaddr_reg:x2; val_offset:30156*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30156*FLEN/8, x3, x1, x4) + +inst_10087: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7bff; +op3val:0x83ff; valaddr_reg:x2; val_offset:30159*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30159*FLEN/8, x3, x1, x4) + +inst_10088: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7bff; +op3val:0x400; valaddr_reg:x2; val_offset:30162*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30162*FLEN/8, x3, x1, x4) + +inst_10089: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7bff; +op3val:0x8400; valaddr_reg:x2; val_offset:30165*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30165*FLEN/8, x3, x1, x4) + +inst_10090: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7bff; +op3val:0x401; valaddr_reg:x2; val_offset:30168*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30168*FLEN/8, x3, x1, x4) + +inst_10091: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7bff; +op3val:0x8455; valaddr_reg:x2; val_offset:30171*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30171*FLEN/8, x3, x1, x4) + +inst_10092: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7bff; +op3val:0x7bff; valaddr_reg:x2; val_offset:30174*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30174*FLEN/8, x3, x1, x4) + +inst_10093: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7bff; +op3val:0xfbff; valaddr_reg:x2; val_offset:30177*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30177*FLEN/8, x3, x1, x4) + +inst_10094: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7bff; +op3val:0x7c00; valaddr_reg:x2; val_offset:30180*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30180*FLEN/8, x3, x1, x4) + +inst_10095: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7bff; +op3val:0xfc00; valaddr_reg:x2; val_offset:30183*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30183*FLEN/8, x3, x1, x4) + +inst_10096: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7bff; +op3val:0x7e00; valaddr_reg:x2; val_offset:30186*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30186*FLEN/8, x3, x1, x4) + +inst_10097: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7bff; +op3val:0xfe00; valaddr_reg:x2; val_offset:30189*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30189*FLEN/8, x3, x1, x4) + +inst_10098: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7bff; +op3val:0x7e01; valaddr_reg:x2; val_offset:30192*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30192*FLEN/8, x3, x1, x4) + +inst_10099: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7bff; +op3val:0xfe55; valaddr_reg:x2; val_offset:30195*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30195*FLEN/8, x3, x1, x4) + +inst_10100: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7bff; +op3val:0x7c01; valaddr_reg:x2; val_offset:30198*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30198*FLEN/8, x3, x1, x4) + +inst_10101: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7bff; +op3val:0xfd55; valaddr_reg:x2; val_offset:30201*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30201*FLEN/8, x3, x1, x4) + +inst_10102: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7bff; +op3val:0x3c00; valaddr_reg:x2; val_offset:30204*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30204*FLEN/8, x3, x1, x4) + +inst_10103: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7bff; +op3val:0xbc00; valaddr_reg:x2; val_offset:30207*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30207*FLEN/8, x3, x1, x4) + +inst_10104: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfbff; +op3val:0x0; valaddr_reg:x2; val_offset:30210*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30210*FLEN/8, x3, x1, x4) + +inst_10105: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfbff; +op3val:0x8000; valaddr_reg:x2; val_offset:30213*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30213*FLEN/8, x3, x1, x4) + +inst_10106: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfbff; +op3val:0x1; valaddr_reg:x2; val_offset:30216*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30216*FLEN/8, x3, x1, x4) + +inst_10107: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfbff; +op3val:0x8001; valaddr_reg:x2; val_offset:30219*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30219*FLEN/8, x3, x1, x4) + +inst_10108: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfbff; +op3val:0x2; valaddr_reg:x2; val_offset:30222*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30222*FLEN/8, x3, x1, x4) + +inst_10109: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfbff; +op3val:0x83fe; valaddr_reg:x2; val_offset:30225*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30225*FLEN/8, x3, x1, x4) + +inst_10110: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfbff; +op3val:0x3ff; valaddr_reg:x2; val_offset:30228*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30228*FLEN/8, x3, x1, x4) + +inst_10111: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfbff; +op3val:0x83ff; valaddr_reg:x2; val_offset:30231*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30231*FLEN/8, x3, x1, x4) + +inst_10112: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfbff; +op3val:0x400; valaddr_reg:x2; val_offset:30234*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30234*FLEN/8, x3, x1, x4) + +inst_10113: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfbff; +op3val:0x8400; valaddr_reg:x2; val_offset:30237*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30237*FLEN/8, x3, x1, x4) + +inst_10114: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfbff; +op3val:0x401; valaddr_reg:x2; val_offset:30240*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30240*FLEN/8, x3, x1, x4) + +inst_10115: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfbff; +op3val:0x8455; valaddr_reg:x2; val_offset:30243*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30243*FLEN/8, x3, x1, x4) + +inst_10116: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfbff; +op3val:0x7bff; valaddr_reg:x2; val_offset:30246*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30246*FLEN/8, x3, x1, x4) + +inst_10117: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfbff; +op3val:0xfbff; valaddr_reg:x2; val_offset:30249*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30249*FLEN/8, x3, x1, x4) + +inst_10118: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfbff; +op3val:0x7c00; valaddr_reg:x2; val_offset:30252*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30252*FLEN/8, x3, x1, x4) + +inst_10119: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfbff; +op3val:0xfc00; valaddr_reg:x2; val_offset:30255*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30255*FLEN/8, x3, x1, x4) + +inst_10120: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfbff; +op3val:0x7e00; valaddr_reg:x2; val_offset:30258*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30258*FLEN/8, x3, x1, x4) + +inst_10121: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfbff; +op3val:0xfe00; valaddr_reg:x2; val_offset:30261*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30261*FLEN/8, x3, x1, x4) + +inst_10122: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfbff; +op3val:0x7e01; valaddr_reg:x2; val_offset:30264*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30264*FLEN/8, x3, x1, x4) + +inst_10123: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfbff; +op3val:0xfe55; valaddr_reg:x2; val_offset:30267*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30267*FLEN/8, x3, x1, x4) + +inst_10124: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfbff; +op3val:0x7c01; valaddr_reg:x2; val_offset:30270*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30270*FLEN/8, x3, x1, x4) + +inst_10125: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfbff; +op3val:0xfd55; valaddr_reg:x2; val_offset:30273*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30273*FLEN/8, x3, x1, x4) + +inst_10126: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfbff; +op3val:0x3c00; valaddr_reg:x2; val_offset:30276*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30276*FLEN/8, x3, x1, x4) + +inst_10127: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfbff; +op3val:0xbc00; valaddr_reg:x2; val_offset:30279*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30279*FLEN/8, x3, x1, x4) + +inst_10128: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7c00; +op3val:0x0; valaddr_reg:x2; val_offset:30282*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30282*FLEN/8, x3, x1, x4) + +inst_10129: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7c00; +op3val:0x8000; valaddr_reg:x2; val_offset:30285*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30285*FLEN/8, x3, x1, x4) + +inst_10130: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7c00; +op3val:0x1; valaddr_reg:x2; val_offset:30288*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30288*FLEN/8, x3, x1, x4) + +inst_10131: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7c00; +op3val:0x8001; valaddr_reg:x2; val_offset:30291*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30291*FLEN/8, x3, x1, x4) + +inst_10132: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7c00; +op3val:0x2; valaddr_reg:x2; val_offset:30294*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30294*FLEN/8, x3, x1, x4) + +inst_10133: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7c00; +op3val:0x83fe; valaddr_reg:x2; val_offset:30297*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30297*FLEN/8, x3, x1, x4) + +inst_10134: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7c00; +op3val:0x3ff; valaddr_reg:x2; val_offset:30300*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30300*FLEN/8, x3, x1, x4) + +inst_10135: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7c00; +op3val:0x83ff; valaddr_reg:x2; val_offset:30303*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30303*FLEN/8, x3, x1, x4) + +inst_10136: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7c00; +op3val:0x400; valaddr_reg:x2; val_offset:30306*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30306*FLEN/8, x3, x1, x4) + +inst_10137: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7c00; +op3val:0x8400; valaddr_reg:x2; val_offset:30309*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30309*FLEN/8, x3, x1, x4) + +inst_10138: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7c00; +op3val:0x401; valaddr_reg:x2; val_offset:30312*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30312*FLEN/8, x3, x1, x4) + +inst_10139: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7c00; +op3val:0x8455; valaddr_reg:x2; val_offset:30315*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30315*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_80) + +inst_10140: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7c00; +op3val:0x7bff; valaddr_reg:x2; val_offset:30318*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30318*FLEN/8, x3, x1, x4) + +inst_10141: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7c00; +op3val:0xfbff; valaddr_reg:x2; val_offset:30321*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30321*FLEN/8, x3, x1, x4) + +inst_10142: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7c00; +op3val:0x7c00; valaddr_reg:x2; val_offset:30324*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30324*FLEN/8, x3, x1, x4) + +inst_10143: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7c00; +op3val:0xfc00; valaddr_reg:x2; val_offset:30327*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30327*FLEN/8, x3, x1, x4) + +inst_10144: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7c00; +op3val:0x7e00; valaddr_reg:x2; val_offset:30330*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30330*FLEN/8, x3, x1, x4) + +inst_10145: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7c00; +op3val:0xfe00; valaddr_reg:x2; val_offset:30333*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30333*FLEN/8, x3, x1, x4) + +inst_10146: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7c00; +op3val:0x7e01; valaddr_reg:x2; val_offset:30336*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30336*FLEN/8, x3, x1, x4) + +inst_10147: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7c00; +op3val:0xfe55; valaddr_reg:x2; val_offset:30339*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30339*FLEN/8, x3, x1, x4) + +inst_10148: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7c00; +op3val:0x7c01; valaddr_reg:x2; val_offset:30342*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30342*FLEN/8, x3, x1, x4) + +inst_10149: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7c00; +op3val:0xfd55; valaddr_reg:x2; val_offset:30345*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30345*FLEN/8, x3, x1, x4) + +inst_10150: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7c00; +op3val:0x3c00; valaddr_reg:x2; val_offset:30348*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30348*FLEN/8, x3, x1, x4) + +inst_10151: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7c00; +op3val:0xbc00; valaddr_reg:x2; val_offset:30351*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30351*FLEN/8, x3, x1, x4) + +inst_10152: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfc00; +op3val:0x0; valaddr_reg:x2; val_offset:30354*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30354*FLEN/8, x3, x1, x4) + +inst_10153: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfc00; +op3val:0x8000; valaddr_reg:x2; val_offset:30357*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30357*FLEN/8, x3, x1, x4) + +inst_10154: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfc00; +op3val:0x1; valaddr_reg:x2; val_offset:30360*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30360*FLEN/8, x3, x1, x4) + +inst_10155: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfc00; +op3val:0x8001; valaddr_reg:x2; val_offset:30363*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30363*FLEN/8, x3, x1, x4) + +inst_10156: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfc00; +op3val:0x2; valaddr_reg:x2; val_offset:30366*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30366*FLEN/8, x3, x1, x4) + +inst_10157: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfc00; +op3val:0x83fe; valaddr_reg:x2; val_offset:30369*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30369*FLEN/8, x3, x1, x4) + +inst_10158: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfc00; +op3val:0x3ff; valaddr_reg:x2; val_offset:30372*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30372*FLEN/8, x3, x1, x4) + +inst_10159: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfc00; +op3val:0x83ff; valaddr_reg:x2; val_offset:30375*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30375*FLEN/8, x3, x1, x4) + +inst_10160: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfc00; +op3val:0x400; valaddr_reg:x2; val_offset:30378*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30378*FLEN/8, x3, x1, x4) + +inst_10161: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfc00; +op3val:0x8400; valaddr_reg:x2; val_offset:30381*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30381*FLEN/8, x3, x1, x4) + +inst_10162: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfc00; +op3val:0x401; valaddr_reg:x2; val_offset:30384*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30384*FLEN/8, x3, x1, x4) + +inst_10163: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfc00; +op3val:0x8455; valaddr_reg:x2; val_offset:30387*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30387*FLEN/8, x3, x1, x4) + +inst_10164: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfc00; +op3val:0x7bff; valaddr_reg:x2; val_offset:30390*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30390*FLEN/8, x3, x1, x4) + +inst_10165: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfc00; +op3val:0xfbff; valaddr_reg:x2; val_offset:30393*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30393*FLEN/8, x3, x1, x4) + +inst_10166: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfc00; +op3val:0x7c00; valaddr_reg:x2; val_offset:30396*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30396*FLEN/8, x3, x1, x4) + +inst_10167: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfc00; +op3val:0xfc00; valaddr_reg:x2; val_offset:30399*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30399*FLEN/8, x3, x1, x4) + +inst_10168: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfc00; +op3val:0x7e00; valaddr_reg:x2; val_offset:30402*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30402*FLEN/8, x3, x1, x4) + +inst_10169: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfc00; +op3val:0xfe00; valaddr_reg:x2; val_offset:30405*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30405*FLEN/8, x3, x1, x4) + +inst_10170: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfc00; +op3val:0x7e01; valaddr_reg:x2; val_offset:30408*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30408*FLEN/8, x3, x1, x4) + +inst_10171: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfc00; +op3val:0xfe55; valaddr_reg:x2; val_offset:30411*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30411*FLEN/8, x3, x1, x4) + +inst_10172: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfc00; +op3val:0x7c01; valaddr_reg:x2; val_offset:30414*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30414*FLEN/8, x3, x1, x4) + +inst_10173: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfc00; +op3val:0xfd55; valaddr_reg:x2; val_offset:30417*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30417*FLEN/8, x3, x1, x4) + +inst_10174: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfc00; +op3val:0x3c00; valaddr_reg:x2; val_offset:30420*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30420*FLEN/8, x3, x1, x4) + +inst_10175: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfc00; +op3val:0xbc00; valaddr_reg:x2; val_offset:30423*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30423*FLEN/8, x3, x1, x4) + +inst_10176: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7e00; +op3val:0x0; valaddr_reg:x2; val_offset:30426*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30426*FLEN/8, x3, x1, x4) + +inst_10177: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7e00; +op3val:0x8000; valaddr_reg:x2; val_offset:30429*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30429*FLEN/8, x3, x1, x4) + +inst_10178: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7e00; +op3val:0x1; valaddr_reg:x2; val_offset:30432*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30432*FLEN/8, x3, x1, x4) + +inst_10179: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7e00; +op3val:0x8001; valaddr_reg:x2; val_offset:30435*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30435*FLEN/8, x3, x1, x4) + +inst_10180: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7e00; +op3val:0x2; valaddr_reg:x2; val_offset:30438*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30438*FLEN/8, x3, x1, x4) + +inst_10181: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7e00; +op3val:0x83fe; valaddr_reg:x2; val_offset:30441*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30441*FLEN/8, x3, x1, x4) + +inst_10182: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7e00; +op3val:0x3ff; valaddr_reg:x2; val_offset:30444*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30444*FLEN/8, x3, x1, x4) + +inst_10183: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7e00; +op3val:0x83ff; valaddr_reg:x2; val_offset:30447*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30447*FLEN/8, x3, x1, x4) + +inst_10184: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7e00; +op3val:0x400; valaddr_reg:x2; val_offset:30450*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30450*FLEN/8, x3, x1, x4) + +inst_10185: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7e00; +op3val:0x8400; valaddr_reg:x2; val_offset:30453*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30453*FLEN/8, x3, x1, x4) + +inst_10186: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7e00; +op3val:0x401; valaddr_reg:x2; val_offset:30456*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30456*FLEN/8, x3, x1, x4) + +inst_10187: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7e00; +op3val:0x8455; valaddr_reg:x2; val_offset:30459*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30459*FLEN/8, x3, x1, x4) + +inst_10188: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7e00; +op3val:0x7bff; valaddr_reg:x2; val_offset:30462*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30462*FLEN/8, x3, x1, x4) + +inst_10189: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7e00; +op3val:0xfbff; valaddr_reg:x2; val_offset:30465*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30465*FLEN/8, x3, x1, x4) + +inst_10190: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7e00; +op3val:0x7c00; valaddr_reg:x2; val_offset:30468*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30468*FLEN/8, x3, x1, x4) + +inst_10191: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7e00; +op3val:0xfc00; valaddr_reg:x2; val_offset:30471*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30471*FLEN/8, x3, x1, x4) + +inst_10192: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7e00; +op3val:0x7e00; valaddr_reg:x2; val_offset:30474*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30474*FLEN/8, x3, x1, x4) + +inst_10193: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7e00; +op3val:0xfe00; valaddr_reg:x2; val_offset:30477*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30477*FLEN/8, x3, x1, x4) + +inst_10194: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7e00; +op3val:0x7e01; valaddr_reg:x2; val_offset:30480*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30480*FLEN/8, x3, x1, x4) + +inst_10195: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7e00; +op3val:0xfe55; valaddr_reg:x2; val_offset:30483*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30483*FLEN/8, x3, x1, x4) + +inst_10196: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7e00; +op3val:0x7c01; valaddr_reg:x2; val_offset:30486*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30486*FLEN/8, x3, x1, x4) + +inst_10197: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7e00; +op3val:0xfd55; valaddr_reg:x2; val_offset:30489*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30489*FLEN/8, x3, x1, x4) + +inst_10198: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7e00; +op3val:0x3c00; valaddr_reg:x2; val_offset:30492*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30492*FLEN/8, x3, x1, x4) + +inst_10199: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7e00; +op3val:0xbc00; valaddr_reg:x2; val_offset:30495*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30495*FLEN/8, x3, x1, x4) + +inst_10200: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfe00; +op3val:0x0; valaddr_reg:x2; val_offset:30498*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30498*FLEN/8, x3, x1, x4) + +inst_10201: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfe00; +op3val:0x8000; valaddr_reg:x2; val_offset:30501*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30501*FLEN/8, x3, x1, x4) + +inst_10202: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfe00; +op3val:0x1; valaddr_reg:x2; val_offset:30504*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30504*FLEN/8, x3, x1, x4) + +inst_10203: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfe00; +op3val:0x8001; valaddr_reg:x2; val_offset:30507*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30507*FLEN/8, x3, x1, x4) + +inst_10204: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfe00; +op3val:0x2; valaddr_reg:x2; val_offset:30510*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30510*FLEN/8, x3, x1, x4) + +inst_10205: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfe00; +op3val:0x83fe; valaddr_reg:x2; val_offset:30513*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30513*FLEN/8, x3, x1, x4) + +inst_10206: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfe00; +op3val:0x3ff; valaddr_reg:x2; val_offset:30516*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30516*FLEN/8, x3, x1, x4) + +inst_10207: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfe00; +op3val:0x83ff; valaddr_reg:x2; val_offset:30519*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30519*FLEN/8, x3, x1, x4) + +inst_10208: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfe00; +op3val:0x400; valaddr_reg:x2; val_offset:30522*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30522*FLEN/8, x3, x1, x4) + +inst_10209: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfe00; +op3val:0x8400; valaddr_reg:x2; val_offset:30525*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30525*FLEN/8, x3, x1, x4) + +inst_10210: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfe00; +op3val:0x401; valaddr_reg:x2; val_offset:30528*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30528*FLEN/8, x3, x1, x4) + +inst_10211: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfe00; +op3val:0x8455; valaddr_reg:x2; val_offset:30531*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30531*FLEN/8, x3, x1, x4) + +inst_10212: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfe00; +op3val:0x7bff; valaddr_reg:x2; val_offset:30534*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30534*FLEN/8, x3, x1, x4) + +inst_10213: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfe00; +op3val:0xfbff; valaddr_reg:x2; val_offset:30537*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30537*FLEN/8, x3, x1, x4) + +inst_10214: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfe00; +op3val:0x7c00; valaddr_reg:x2; val_offset:30540*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30540*FLEN/8, x3, x1, x4) + +inst_10215: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfe00; +op3val:0xfc00; valaddr_reg:x2; val_offset:30543*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30543*FLEN/8, x3, x1, x4) + +inst_10216: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfe00; +op3val:0x7e00; valaddr_reg:x2; val_offset:30546*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30546*FLEN/8, x3, x1, x4) + +inst_10217: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfe00; +op3val:0xfe00; valaddr_reg:x2; val_offset:30549*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30549*FLEN/8, x3, x1, x4) + +inst_10218: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfe00; +op3val:0x7e01; valaddr_reg:x2; val_offset:30552*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30552*FLEN/8, x3, x1, x4) + +inst_10219: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfe00; +op3val:0xfe55; valaddr_reg:x2; val_offset:30555*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30555*FLEN/8, x3, x1, x4) + +inst_10220: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfe00; +op3val:0x7c01; valaddr_reg:x2; val_offset:30558*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30558*FLEN/8, x3, x1, x4) + +inst_10221: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfe00; +op3val:0xfd55; valaddr_reg:x2; val_offset:30561*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30561*FLEN/8, x3, x1, x4) + +inst_10222: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfe00; +op3val:0x3c00; valaddr_reg:x2; val_offset:30564*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30564*FLEN/8, x3, x1, x4) + +inst_10223: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfe00; +op3val:0xbc00; valaddr_reg:x2; val_offset:30567*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30567*FLEN/8, x3, x1, x4) + +inst_10224: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7e01; +op3val:0x0; valaddr_reg:x2; val_offset:30570*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30570*FLEN/8, x3, x1, x4) + +inst_10225: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7e01; +op3val:0x8000; valaddr_reg:x2; val_offset:30573*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30573*FLEN/8, x3, x1, x4) + +inst_10226: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7e01; +op3val:0x1; valaddr_reg:x2; val_offset:30576*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30576*FLEN/8, x3, x1, x4) + +inst_10227: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7e01; +op3val:0x8001; valaddr_reg:x2; val_offset:30579*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30579*FLEN/8, x3, x1, x4) + +inst_10228: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7e01; +op3val:0x2; valaddr_reg:x2; val_offset:30582*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30582*FLEN/8, x3, x1, x4) + +inst_10229: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7e01; +op3val:0x83fe; valaddr_reg:x2; val_offset:30585*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30585*FLEN/8, x3, x1, x4) + +inst_10230: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7e01; +op3val:0x3ff; valaddr_reg:x2; val_offset:30588*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30588*FLEN/8, x3, x1, x4) + +inst_10231: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7e01; +op3val:0x83ff; valaddr_reg:x2; val_offset:30591*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30591*FLEN/8, x3, x1, x4) + +inst_10232: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7e01; +op3val:0x400; valaddr_reg:x2; val_offset:30594*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30594*FLEN/8, x3, x1, x4) + +inst_10233: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7e01; +op3val:0x8400; valaddr_reg:x2; val_offset:30597*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30597*FLEN/8, x3, x1, x4) + +inst_10234: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7e01; +op3val:0x401; valaddr_reg:x2; val_offset:30600*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30600*FLEN/8, x3, x1, x4) + +inst_10235: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7e01; +op3val:0x8455; valaddr_reg:x2; val_offset:30603*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30603*FLEN/8, x3, x1, x4) + +inst_10236: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7e01; +op3val:0x7bff; valaddr_reg:x2; val_offset:30606*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30606*FLEN/8, x3, x1, x4) + +inst_10237: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7e01; +op3val:0xfbff; valaddr_reg:x2; val_offset:30609*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30609*FLEN/8, x3, x1, x4) + +inst_10238: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7e01; +op3val:0x7c00; valaddr_reg:x2; val_offset:30612*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30612*FLEN/8, x3, x1, x4) + +inst_10239: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7e01; +op3val:0xfc00; valaddr_reg:x2; val_offset:30615*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30615*FLEN/8, x3, x1, x4) + +inst_10240: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7e01; +op3val:0x7e00; valaddr_reg:x2; val_offset:30618*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30618*FLEN/8, x3, x1, x4) + +inst_10241: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7e01; +op3val:0xfe00; valaddr_reg:x2; val_offset:30621*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30621*FLEN/8, x3, x1, x4) + +inst_10242: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7e01; +op3val:0x7e01; valaddr_reg:x2; val_offset:30624*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30624*FLEN/8, x3, x1, x4) + +inst_10243: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7e01; +op3val:0xfe55; valaddr_reg:x2; val_offset:30627*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30627*FLEN/8, x3, x1, x4) + +inst_10244: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7e01; +op3val:0x7c01; valaddr_reg:x2; val_offset:30630*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30630*FLEN/8, x3, x1, x4) + +inst_10245: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7e01; +op3val:0xfd55; valaddr_reg:x2; val_offset:30633*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30633*FLEN/8, x3, x1, x4) + +inst_10246: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7e01; +op3val:0x3c00; valaddr_reg:x2; val_offset:30636*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30636*FLEN/8, x3, x1, x4) + +inst_10247: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7e01; +op3val:0xbc00; valaddr_reg:x2; val_offset:30639*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30639*FLEN/8, x3, x1, x4) + +inst_10248: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfe55; +op3val:0x0; valaddr_reg:x2; val_offset:30642*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30642*FLEN/8, x3, x1, x4) + +inst_10249: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfe55; +op3val:0x8000; valaddr_reg:x2; val_offset:30645*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30645*FLEN/8, x3, x1, x4) + +inst_10250: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfe55; +op3val:0x1; valaddr_reg:x2; val_offset:30648*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30648*FLEN/8, x3, x1, x4) + +inst_10251: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfe55; +op3val:0x8001; valaddr_reg:x2; val_offset:30651*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30651*FLEN/8, x3, x1, x4) + +inst_10252: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfe55; +op3val:0x2; valaddr_reg:x2; val_offset:30654*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30654*FLEN/8, x3, x1, x4) + +inst_10253: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfe55; +op3val:0x83fe; valaddr_reg:x2; val_offset:30657*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30657*FLEN/8, x3, x1, x4) + +inst_10254: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfe55; +op3val:0x3ff; valaddr_reg:x2; val_offset:30660*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30660*FLEN/8, x3, x1, x4) + +inst_10255: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfe55; +op3val:0x83ff; valaddr_reg:x2; val_offset:30663*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30663*FLEN/8, x3, x1, x4) + +inst_10256: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfe55; +op3val:0x400; valaddr_reg:x2; val_offset:30666*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30666*FLEN/8, x3, x1, x4) + +inst_10257: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfe55; +op3val:0x8400; valaddr_reg:x2; val_offset:30669*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30669*FLEN/8, x3, x1, x4) + +inst_10258: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfe55; +op3val:0x401; valaddr_reg:x2; val_offset:30672*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30672*FLEN/8, x3, x1, x4) + +inst_10259: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfe55; +op3val:0x8455; valaddr_reg:x2; val_offset:30675*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30675*FLEN/8, x3, x1, x4) + +inst_10260: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfe55; +op3val:0x7bff; valaddr_reg:x2; val_offset:30678*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30678*FLEN/8, x3, x1, x4) + +inst_10261: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfe55; +op3val:0xfbff; valaddr_reg:x2; val_offset:30681*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30681*FLEN/8, x3, x1, x4) + +inst_10262: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfe55; +op3val:0x7c00; valaddr_reg:x2; val_offset:30684*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30684*FLEN/8, x3, x1, x4) + +inst_10263: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfe55; +op3val:0xfc00; valaddr_reg:x2; val_offset:30687*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30687*FLEN/8, x3, x1, x4) + +inst_10264: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfe55; +op3val:0x7e00; valaddr_reg:x2; val_offset:30690*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30690*FLEN/8, x3, x1, x4) + +inst_10265: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfe55; +op3val:0xfe00; valaddr_reg:x2; val_offset:30693*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30693*FLEN/8, x3, x1, x4) + +inst_10266: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfe55; +op3val:0x7e01; valaddr_reg:x2; val_offset:30696*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30696*FLEN/8, x3, x1, x4) + +inst_10267: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfe55; +op3val:0xfe55; valaddr_reg:x2; val_offset:30699*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30699*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_81) + +inst_10268: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfe55; +op3val:0x7c01; valaddr_reg:x2; val_offset:30702*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30702*FLEN/8, x3, x1, x4) + +inst_10269: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfe55; +op3val:0xfd55; valaddr_reg:x2; val_offset:30705*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30705*FLEN/8, x3, x1, x4) + +inst_10270: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfe55; +op3val:0x3c00; valaddr_reg:x2; val_offset:30708*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30708*FLEN/8, x3, x1, x4) + +inst_10271: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfe55; +op3val:0xbc00; valaddr_reg:x2; val_offset:30711*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30711*FLEN/8, x3, x1, x4) + +inst_10272: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7c01; +op3val:0x0; valaddr_reg:x2; val_offset:30714*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30714*FLEN/8, x3, x1, x4) + +inst_10273: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7c01; +op3val:0x8000; valaddr_reg:x2; val_offset:30717*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30717*FLEN/8, x3, x1, x4) + +inst_10274: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7c01; +op3val:0x1; valaddr_reg:x2; val_offset:30720*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30720*FLEN/8, x3, x1, x4) + +inst_10275: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7c01; +op3val:0x8001; valaddr_reg:x2; val_offset:30723*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30723*FLEN/8, x3, x1, x4) + +inst_10276: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7c01; +op3val:0x2; valaddr_reg:x2; val_offset:30726*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30726*FLEN/8, x3, x1, x4) + +inst_10277: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7c01; +op3val:0x83fe; valaddr_reg:x2; val_offset:30729*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30729*FLEN/8, x3, x1, x4) + +inst_10278: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7c01; +op3val:0x3ff; valaddr_reg:x2; val_offset:30732*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30732*FLEN/8, x3, x1, x4) + +inst_10279: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7c01; +op3val:0x83ff; valaddr_reg:x2; val_offset:30735*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30735*FLEN/8, x3, x1, x4) + +inst_10280: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7c01; +op3val:0x400; valaddr_reg:x2; val_offset:30738*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30738*FLEN/8, x3, x1, x4) + +inst_10281: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7c01; +op3val:0x8400; valaddr_reg:x2; val_offset:30741*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30741*FLEN/8, x3, x1, x4) + +inst_10282: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7c01; +op3val:0x401; valaddr_reg:x2; val_offset:30744*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30744*FLEN/8, x3, x1, x4) + +inst_10283: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7c01; +op3val:0x8455; valaddr_reg:x2; val_offset:30747*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30747*FLEN/8, x3, x1, x4) + +inst_10284: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7c01; +op3val:0x7bff; valaddr_reg:x2; val_offset:30750*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30750*FLEN/8, x3, x1, x4) + +inst_10285: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7c01; +op3val:0xfbff; valaddr_reg:x2; val_offset:30753*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30753*FLEN/8, x3, x1, x4) + +inst_10286: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7c01; +op3val:0x7c00; valaddr_reg:x2; val_offset:30756*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30756*FLEN/8, x3, x1, x4) + +inst_10287: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7c01; +op3val:0xfc00; valaddr_reg:x2; val_offset:30759*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30759*FLEN/8, x3, x1, x4) + +inst_10288: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7c01; +op3val:0x7e00; valaddr_reg:x2; val_offset:30762*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30762*FLEN/8, x3, x1, x4) + +inst_10289: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7c01; +op3val:0xfe00; valaddr_reg:x2; val_offset:30765*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30765*FLEN/8, x3, x1, x4) + +inst_10290: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7c01; +op3val:0x7e01; valaddr_reg:x2; val_offset:30768*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30768*FLEN/8, x3, x1, x4) + +inst_10291: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7c01; +op3val:0xfe55; valaddr_reg:x2; val_offset:30771*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30771*FLEN/8, x3, x1, x4) + +inst_10292: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7c01; +op3val:0x7c01; valaddr_reg:x2; val_offset:30774*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30774*FLEN/8, x3, x1, x4) + +inst_10293: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7c01; +op3val:0xfd55; valaddr_reg:x2; val_offset:30777*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30777*FLEN/8, x3, x1, x4) + +inst_10294: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7c01; +op3val:0x3c00; valaddr_reg:x2; val_offset:30780*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30780*FLEN/8, x3, x1, x4) + +inst_10295: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x7c01; +op3val:0xbc00; valaddr_reg:x2; val_offset:30783*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30783*FLEN/8, x3, x1, x4) + +inst_10296: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfd55; +op3val:0x0; valaddr_reg:x2; val_offset:30786*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30786*FLEN/8, x3, x1, x4) + +inst_10297: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfd55; +op3val:0x8000; valaddr_reg:x2; val_offset:30789*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30789*FLEN/8, x3, x1, x4) + +inst_10298: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfd55; +op3val:0x1; valaddr_reg:x2; val_offset:30792*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30792*FLEN/8, x3, x1, x4) + +inst_10299: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfd55; +op3val:0x8001; valaddr_reg:x2; val_offset:30795*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30795*FLEN/8, x3, x1, x4) + +inst_10300: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfd55; +op3val:0x2; valaddr_reg:x2; val_offset:30798*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30798*FLEN/8, x3, x1, x4) + +inst_10301: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfd55; +op3val:0x83fe; valaddr_reg:x2; val_offset:30801*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30801*FLEN/8, x3, x1, x4) + +inst_10302: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfd55; +op3val:0x3ff; valaddr_reg:x2; val_offset:30804*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30804*FLEN/8, x3, x1, x4) + +inst_10303: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfd55; +op3val:0x83ff; valaddr_reg:x2; val_offset:30807*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30807*FLEN/8, x3, x1, x4) + +inst_10304: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfd55; +op3val:0x400; valaddr_reg:x2; val_offset:30810*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30810*FLEN/8, x3, x1, x4) + +inst_10305: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfd55; +op3val:0x8400; valaddr_reg:x2; val_offset:30813*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30813*FLEN/8, x3, x1, x4) + +inst_10306: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfd55; +op3val:0x401; valaddr_reg:x2; val_offset:30816*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30816*FLEN/8, x3, x1, x4) + +inst_10307: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfd55; +op3val:0x8455; valaddr_reg:x2; val_offset:30819*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30819*FLEN/8, x3, x1, x4) + +inst_10308: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfd55; +op3val:0x7bff; valaddr_reg:x2; val_offset:30822*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30822*FLEN/8, x3, x1, x4) + +inst_10309: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfd55; +op3val:0xfbff; valaddr_reg:x2; val_offset:30825*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30825*FLEN/8, x3, x1, x4) + +inst_10310: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfd55; +op3val:0x7c00; valaddr_reg:x2; val_offset:30828*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30828*FLEN/8, x3, x1, x4) + +inst_10311: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfd55; +op3val:0xfc00; valaddr_reg:x2; val_offset:30831*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30831*FLEN/8, x3, x1, x4) + +inst_10312: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfd55; +op3val:0x7e00; valaddr_reg:x2; val_offset:30834*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30834*FLEN/8, x3, x1, x4) + +inst_10313: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfd55; +op3val:0xfe00; valaddr_reg:x2; val_offset:30837*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30837*FLEN/8, x3, x1, x4) + +inst_10314: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfd55; +op3val:0x7e01; valaddr_reg:x2; val_offset:30840*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30840*FLEN/8, x3, x1, x4) + +inst_10315: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfd55; +op3val:0xfe55; valaddr_reg:x2; val_offset:30843*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30843*FLEN/8, x3, x1, x4) + +inst_10316: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfd55; +op3val:0x7c01; valaddr_reg:x2; val_offset:30846*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30846*FLEN/8, x3, x1, x4) + +inst_10317: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfd55; +op3val:0xfd55; valaddr_reg:x2; val_offset:30849*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30849*FLEN/8, x3, x1, x4) + +inst_10318: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfd55; +op3val:0x3c00; valaddr_reg:x2; val_offset:30852*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30852*FLEN/8, x3, x1, x4) + +inst_10319: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xfd55; +op3val:0xbc00; valaddr_reg:x2; val_offset:30855*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30855*FLEN/8, x3, x1, x4) + +inst_10320: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x3c00; +op3val:0x0; valaddr_reg:x2; val_offset:30858*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30858*FLEN/8, x3, x1, x4) + +inst_10321: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x3c00; +op3val:0x8000; valaddr_reg:x2; val_offset:30861*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30861*FLEN/8, x3, x1, x4) + +inst_10322: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x3c00; +op3val:0x1; valaddr_reg:x2; val_offset:30864*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30864*FLEN/8, x3, x1, x4) + +inst_10323: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x3c00; +op3val:0x8001; valaddr_reg:x2; val_offset:30867*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30867*FLEN/8, x3, x1, x4) + +inst_10324: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x3c00; +op3val:0x2; valaddr_reg:x2; val_offset:30870*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30870*FLEN/8, x3, x1, x4) + +inst_10325: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x3c00; +op3val:0x83fe; valaddr_reg:x2; val_offset:30873*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30873*FLEN/8, x3, x1, x4) + +inst_10326: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x3c00; +op3val:0x3ff; valaddr_reg:x2; val_offset:30876*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30876*FLEN/8, x3, x1, x4) + +inst_10327: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x3c00; +op3val:0x83ff; valaddr_reg:x2; val_offset:30879*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30879*FLEN/8, x3, x1, x4) + +inst_10328: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x3c00; +op3val:0x400; valaddr_reg:x2; val_offset:30882*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30882*FLEN/8, x3, x1, x4) + +inst_10329: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x3c00; +op3val:0x8400; valaddr_reg:x2; val_offset:30885*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30885*FLEN/8, x3, x1, x4) + +inst_10330: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x3c00; +op3val:0x401; valaddr_reg:x2; val_offset:30888*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30888*FLEN/8, x3, x1, x4) + +inst_10331: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x3c00; +op3val:0x8455; valaddr_reg:x2; val_offset:30891*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30891*FLEN/8, x3, x1, x4) + +inst_10332: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x3c00; +op3val:0x7bff; valaddr_reg:x2; val_offset:30894*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30894*FLEN/8, x3, x1, x4) + +inst_10333: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x3c00; +op3val:0xfbff; valaddr_reg:x2; val_offset:30897*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30897*FLEN/8, x3, x1, x4) + +inst_10334: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x3c00; +op3val:0x7c00; valaddr_reg:x2; val_offset:30900*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30900*FLEN/8, x3, x1, x4) + +inst_10335: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x3c00; +op3val:0xfc00; valaddr_reg:x2; val_offset:30903*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30903*FLEN/8, x3, x1, x4) + +inst_10336: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x3c00; +op3val:0x7e00; valaddr_reg:x2; val_offset:30906*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30906*FLEN/8, x3, x1, x4) + +inst_10337: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x3c00; +op3val:0xfe00; valaddr_reg:x2; val_offset:30909*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30909*FLEN/8, x3, x1, x4) + +inst_10338: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x3c00; +op3val:0x7e01; valaddr_reg:x2; val_offset:30912*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30912*FLEN/8, x3, x1, x4) + +inst_10339: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x3c00; +op3val:0xfe55; valaddr_reg:x2; val_offset:30915*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30915*FLEN/8, x3, x1, x4) + +inst_10340: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x3c00; +op3val:0x7c01; valaddr_reg:x2; val_offset:30918*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30918*FLEN/8, x3, x1, x4) + +inst_10341: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x3c00; +op3val:0xfd55; valaddr_reg:x2; val_offset:30921*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30921*FLEN/8, x3, x1, x4) + +inst_10342: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x3c00; +op3val:0x3c00; valaddr_reg:x2; val_offset:30924*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30924*FLEN/8, x3, x1, x4) + +inst_10343: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0x3c00; +op3val:0xbc00; valaddr_reg:x2; val_offset:30927*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30927*FLEN/8, x3, x1, x4) + +inst_10344: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xbc00; +op3val:0x0; valaddr_reg:x2; val_offset:30930*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30930*FLEN/8, x3, x1, x4) + +inst_10345: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xbc00; +op3val:0x8000; valaddr_reg:x2; val_offset:30933*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30933*FLEN/8, x3, x1, x4) + +inst_10346: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xbc00; +op3val:0x1; valaddr_reg:x2; val_offset:30936*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30936*FLEN/8, x3, x1, x4) + +inst_10347: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xbc00; +op3val:0x8001; valaddr_reg:x2; val_offset:30939*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30939*FLEN/8, x3, x1, x4) + +inst_10348: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xbc00; +op3val:0x2; valaddr_reg:x2; val_offset:30942*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30942*FLEN/8, x3, x1, x4) + +inst_10349: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xbc00; +op3val:0x83fe; valaddr_reg:x2; val_offset:30945*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30945*FLEN/8, x3, x1, x4) + +inst_10350: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xbc00; +op3val:0x3ff; valaddr_reg:x2; val_offset:30948*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30948*FLEN/8, x3, x1, x4) + +inst_10351: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xbc00; +op3val:0x83ff; valaddr_reg:x2; val_offset:30951*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30951*FLEN/8, x3, x1, x4) + +inst_10352: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xbc00; +op3val:0x400; valaddr_reg:x2; val_offset:30954*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30954*FLEN/8, x3, x1, x4) + +inst_10353: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xbc00; +op3val:0x8400; valaddr_reg:x2; val_offset:30957*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30957*FLEN/8, x3, x1, x4) + +inst_10354: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xbc00; +op3val:0x401; valaddr_reg:x2; val_offset:30960*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30960*FLEN/8, x3, x1, x4) + +inst_10355: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xbc00; +op3val:0x8455; valaddr_reg:x2; val_offset:30963*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30963*FLEN/8, x3, x1, x4) + +inst_10356: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xbc00; +op3val:0x7bff; valaddr_reg:x2; val_offset:30966*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30966*FLEN/8, x3, x1, x4) + +inst_10357: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xbc00; +op3val:0xfbff; valaddr_reg:x2; val_offset:30969*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30969*FLEN/8, x3, x1, x4) + +inst_10358: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xbc00; +op3val:0x7c00; valaddr_reg:x2; val_offset:30972*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30972*FLEN/8, x3, x1, x4) + +inst_10359: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xbc00; +op3val:0xfc00; valaddr_reg:x2; val_offset:30975*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30975*FLEN/8, x3, x1, x4) + +inst_10360: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xbc00; +op3val:0x7e00; valaddr_reg:x2; val_offset:30978*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30978*FLEN/8, x3, x1, x4) + +inst_10361: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xbc00; +op3val:0xfe00; valaddr_reg:x2; val_offset:30981*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30981*FLEN/8, x3, x1, x4) + +inst_10362: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xbc00; +op3val:0x7e01; valaddr_reg:x2; val_offset:30984*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30984*FLEN/8, x3, x1, x4) + +inst_10363: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xbc00; +op3val:0xfe55; valaddr_reg:x2; val_offset:30987*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30987*FLEN/8, x3, x1, x4) + +inst_10364: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xbc00; +op3val:0x7c01; valaddr_reg:x2; val_offset:30990*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30990*FLEN/8, x3, x1, x4) + +inst_10365: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xbc00; +op3val:0xfd55; valaddr_reg:x2; val_offset:30993*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30993*FLEN/8, x3, x1, x4) + +inst_10366: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xbc00; +op3val:0x3c00; valaddr_reg:x2; val_offset:30996*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30996*FLEN/8, x3, x1, x4) + +inst_10367: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe00; op2val:0xbc00; +op3val:0xbc00; valaddr_reg:x2; val_offset:30999*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30999*FLEN/8, x3, x1, x4) + +inst_10368: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x0; +op3val:0x0; valaddr_reg:x2; val_offset:31002*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31002*FLEN/8, x3, x1, x4) + +inst_10369: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x0; +op3val:0x8000; valaddr_reg:x2; val_offset:31005*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31005*FLEN/8, x3, x1, x4) + +inst_10370: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x0; +op3val:0x1; valaddr_reg:x2; val_offset:31008*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31008*FLEN/8, x3, x1, x4) + +inst_10371: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x0; +op3val:0x8001; valaddr_reg:x2; val_offset:31011*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31011*FLEN/8, x3, x1, x4) + +inst_10372: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x0; +op3val:0x2; valaddr_reg:x2; val_offset:31014*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31014*FLEN/8, x3, x1, x4) + +inst_10373: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x0; +op3val:0x83fe; valaddr_reg:x2; val_offset:31017*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31017*FLEN/8, x3, x1, x4) + +inst_10374: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x0; +op3val:0x3ff; valaddr_reg:x2; val_offset:31020*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31020*FLEN/8, x3, x1, x4) + +inst_10375: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x0; +op3val:0x83ff; valaddr_reg:x2; val_offset:31023*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31023*FLEN/8, x3, x1, x4) + +inst_10376: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x0; +op3val:0x400; valaddr_reg:x2; val_offset:31026*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31026*FLEN/8, x3, x1, x4) + +inst_10377: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x0; +op3val:0x8400; valaddr_reg:x2; val_offset:31029*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31029*FLEN/8, x3, x1, x4) + +inst_10378: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x0; +op3val:0x401; valaddr_reg:x2; val_offset:31032*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31032*FLEN/8, x3, x1, x4) + +inst_10379: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x0; +op3val:0x8455; valaddr_reg:x2; val_offset:31035*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31035*FLEN/8, x3, x1, x4) + +inst_10380: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x0; +op3val:0x7bff; valaddr_reg:x2; val_offset:31038*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31038*FLEN/8, x3, x1, x4) + +inst_10381: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x0; +op3val:0xfbff; valaddr_reg:x2; val_offset:31041*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31041*FLEN/8, x3, x1, x4) + +inst_10382: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x0; +op3val:0x7c00; valaddr_reg:x2; val_offset:31044*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31044*FLEN/8, x3, x1, x4) + +inst_10383: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x0; +op3val:0xfc00; valaddr_reg:x2; val_offset:31047*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31047*FLEN/8, x3, x1, x4) + +inst_10384: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x0; +op3val:0x7e00; valaddr_reg:x2; val_offset:31050*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31050*FLEN/8, x3, x1, x4) + +inst_10385: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x0; +op3val:0xfe00; valaddr_reg:x2; val_offset:31053*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31053*FLEN/8, x3, x1, x4) + +inst_10386: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x0; +op3val:0x7e01; valaddr_reg:x2; val_offset:31056*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31056*FLEN/8, x3, x1, x4) + +inst_10387: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x0; +op3val:0xfe55; valaddr_reg:x2; val_offset:31059*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31059*FLEN/8, x3, x1, x4) + +inst_10388: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x0; +op3val:0x7c01; valaddr_reg:x2; val_offset:31062*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31062*FLEN/8, x3, x1, x4) + +inst_10389: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x0; +op3val:0xfd55; valaddr_reg:x2; val_offset:31065*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31065*FLEN/8, x3, x1, x4) + +inst_10390: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x0; +op3val:0x3c00; valaddr_reg:x2; val_offset:31068*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31068*FLEN/8, x3, x1, x4) + +inst_10391: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x0; +op3val:0xbc00; valaddr_reg:x2; val_offset:31071*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31071*FLEN/8, x3, x1, x4) + +inst_10392: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8000; +op3val:0x0; valaddr_reg:x2; val_offset:31074*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31074*FLEN/8, x3, x1, x4) + +inst_10393: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8000; +op3val:0x8000; valaddr_reg:x2; val_offset:31077*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31077*FLEN/8, x3, x1, x4) + +inst_10394: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8000; +op3val:0x1; valaddr_reg:x2; val_offset:31080*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31080*FLEN/8, x3, x1, x4) + +inst_10395: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8000; +op3val:0x8001; valaddr_reg:x2; val_offset:31083*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31083*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_82) + +inst_10396: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8000; +op3val:0x2; valaddr_reg:x2; val_offset:31086*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31086*FLEN/8, x3, x1, x4) + +inst_10397: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8000; +op3val:0x83fe; valaddr_reg:x2; val_offset:31089*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31089*FLEN/8, x3, x1, x4) + +inst_10398: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8000; +op3val:0x3ff; valaddr_reg:x2; val_offset:31092*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31092*FLEN/8, x3, x1, x4) + +inst_10399: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8000; +op3val:0x83ff; valaddr_reg:x2; val_offset:31095*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31095*FLEN/8, x3, x1, x4) + +inst_10400: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8000; +op3val:0x400; valaddr_reg:x2; val_offset:31098*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31098*FLEN/8, x3, x1, x4) + +inst_10401: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8000; +op3val:0x8400; valaddr_reg:x2; val_offset:31101*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31101*FLEN/8, x3, x1, x4) + +inst_10402: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8000; +op3val:0x401; valaddr_reg:x2; val_offset:31104*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31104*FLEN/8, x3, x1, x4) + +inst_10403: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8000; +op3val:0x8455; valaddr_reg:x2; val_offset:31107*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31107*FLEN/8, x3, x1, x4) + +inst_10404: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x2; val_offset:31110*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31110*FLEN/8, x3, x1, x4) + +inst_10405: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x2; val_offset:31113*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31113*FLEN/8, x3, x1, x4) + +inst_10406: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8000; +op3val:0x7c00; valaddr_reg:x2; val_offset:31116*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31116*FLEN/8, x3, x1, x4) + +inst_10407: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8000; +op3val:0xfc00; valaddr_reg:x2; val_offset:31119*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31119*FLEN/8, x3, x1, x4) + +inst_10408: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8000; +op3val:0x7e00; valaddr_reg:x2; val_offset:31122*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31122*FLEN/8, x3, x1, x4) + +inst_10409: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8000; +op3val:0xfe00; valaddr_reg:x2; val_offset:31125*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31125*FLEN/8, x3, x1, x4) + +inst_10410: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8000; +op3val:0x7e01; valaddr_reg:x2; val_offset:31128*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31128*FLEN/8, x3, x1, x4) + +inst_10411: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8000; +op3val:0xfe55; valaddr_reg:x2; val_offset:31131*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31131*FLEN/8, x3, x1, x4) + +inst_10412: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8000; +op3val:0x7c01; valaddr_reg:x2; val_offset:31134*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31134*FLEN/8, x3, x1, x4) + +inst_10413: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8000; +op3val:0xfd55; valaddr_reg:x2; val_offset:31137*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31137*FLEN/8, x3, x1, x4) + +inst_10414: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8000; +op3val:0x3c00; valaddr_reg:x2; val_offset:31140*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31140*FLEN/8, x3, x1, x4) + +inst_10415: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8000; +op3val:0xbc00; valaddr_reg:x2; val_offset:31143*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31143*FLEN/8, x3, x1, x4) + +inst_10416: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x1; +op3val:0x0; valaddr_reg:x2; val_offset:31146*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31146*FLEN/8, x3, x1, x4) + +inst_10417: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x1; +op3val:0x8000; valaddr_reg:x2; val_offset:31149*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31149*FLEN/8, x3, x1, x4) + +inst_10418: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x1; +op3val:0x1; valaddr_reg:x2; val_offset:31152*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31152*FLEN/8, x3, x1, x4) + +inst_10419: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x1; +op3val:0x8001; valaddr_reg:x2; val_offset:31155*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31155*FLEN/8, x3, x1, x4) + +inst_10420: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x1; +op3val:0x2; valaddr_reg:x2; val_offset:31158*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31158*FLEN/8, x3, x1, x4) + +inst_10421: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x1; +op3val:0x83fe; valaddr_reg:x2; val_offset:31161*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31161*FLEN/8, x3, x1, x4) + +inst_10422: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x1; +op3val:0x3ff; valaddr_reg:x2; val_offset:31164*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31164*FLEN/8, x3, x1, x4) + +inst_10423: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x1; +op3val:0x83ff; valaddr_reg:x2; val_offset:31167*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31167*FLEN/8, x3, x1, x4) + +inst_10424: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x1; +op3val:0x400; valaddr_reg:x2; val_offset:31170*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31170*FLEN/8, x3, x1, x4) + +inst_10425: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x1; +op3val:0x8400; valaddr_reg:x2; val_offset:31173*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31173*FLEN/8, x3, x1, x4) + +inst_10426: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x1; +op3val:0x401; valaddr_reg:x2; val_offset:31176*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31176*FLEN/8, x3, x1, x4) + +inst_10427: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x1; +op3val:0x8455; valaddr_reg:x2; val_offset:31179*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31179*FLEN/8, x3, x1, x4) + +inst_10428: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x1; +op3val:0x7bff; valaddr_reg:x2; val_offset:31182*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31182*FLEN/8, x3, x1, x4) + +inst_10429: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x1; +op3val:0xfbff; valaddr_reg:x2; val_offset:31185*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31185*FLEN/8, x3, x1, x4) + +inst_10430: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x1; +op3val:0x7c00; valaddr_reg:x2; val_offset:31188*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31188*FLEN/8, x3, x1, x4) + +inst_10431: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x1; +op3val:0xfc00; valaddr_reg:x2; val_offset:31191*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31191*FLEN/8, x3, x1, x4) + +inst_10432: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x1; +op3val:0x7e00; valaddr_reg:x2; val_offset:31194*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31194*FLEN/8, x3, x1, x4) + +inst_10433: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x1; +op3val:0xfe00; valaddr_reg:x2; val_offset:31197*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31197*FLEN/8, x3, x1, x4) + +inst_10434: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x1; +op3val:0x7e01; valaddr_reg:x2; val_offset:31200*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31200*FLEN/8, x3, x1, x4) + +inst_10435: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x1; +op3val:0xfe55; valaddr_reg:x2; val_offset:31203*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31203*FLEN/8, x3, x1, x4) + +inst_10436: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x1; +op3val:0x7c01; valaddr_reg:x2; val_offset:31206*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31206*FLEN/8, x3, x1, x4) + +inst_10437: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x1; +op3val:0xfd55; valaddr_reg:x2; val_offset:31209*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31209*FLEN/8, x3, x1, x4) + +inst_10438: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x1; +op3val:0x3c00; valaddr_reg:x2; val_offset:31212*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31212*FLEN/8, x3, x1, x4) + +inst_10439: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x1; +op3val:0xbc00; valaddr_reg:x2; val_offset:31215*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31215*FLEN/8, x3, x1, x4) + +inst_10440: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8001; +op3val:0x0; valaddr_reg:x2; val_offset:31218*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31218*FLEN/8, x3, x1, x4) + +inst_10441: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8001; +op3val:0x8000; valaddr_reg:x2; val_offset:31221*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31221*FLEN/8, x3, x1, x4) + +inst_10442: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8001; +op3val:0x1; valaddr_reg:x2; val_offset:31224*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31224*FLEN/8, x3, x1, x4) + +inst_10443: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8001; +op3val:0x8001; valaddr_reg:x2; val_offset:31227*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31227*FLEN/8, x3, x1, x4) + +inst_10444: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8001; +op3val:0x2; valaddr_reg:x2; val_offset:31230*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31230*FLEN/8, x3, x1, x4) + +inst_10445: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8001; +op3val:0x83fe; valaddr_reg:x2; val_offset:31233*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31233*FLEN/8, x3, x1, x4) + +inst_10446: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8001; +op3val:0x3ff; valaddr_reg:x2; val_offset:31236*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31236*FLEN/8, x3, x1, x4) + +inst_10447: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8001; +op3val:0x83ff; valaddr_reg:x2; val_offset:31239*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31239*FLEN/8, x3, x1, x4) + +inst_10448: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8001; +op3val:0x400; valaddr_reg:x2; val_offset:31242*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31242*FLEN/8, x3, x1, x4) + +inst_10449: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8001; +op3val:0x8400; valaddr_reg:x2; val_offset:31245*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31245*FLEN/8, x3, x1, x4) + +inst_10450: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8001; +op3val:0x401; valaddr_reg:x2; val_offset:31248*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31248*FLEN/8, x3, x1, x4) + +inst_10451: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8001; +op3val:0x8455; valaddr_reg:x2; val_offset:31251*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31251*FLEN/8, x3, x1, x4) + +inst_10452: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8001; +op3val:0x7bff; valaddr_reg:x2; val_offset:31254*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31254*FLEN/8, x3, x1, x4) + +inst_10453: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8001; +op3val:0xfbff; valaddr_reg:x2; val_offset:31257*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31257*FLEN/8, x3, x1, x4) + +inst_10454: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8001; +op3val:0x7c00; valaddr_reg:x2; val_offset:31260*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31260*FLEN/8, x3, x1, x4) + +inst_10455: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8001; +op3val:0xfc00; valaddr_reg:x2; val_offset:31263*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31263*FLEN/8, x3, x1, x4) + +inst_10456: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8001; +op3val:0x7e00; valaddr_reg:x2; val_offset:31266*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31266*FLEN/8, x3, x1, x4) + +inst_10457: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8001; +op3val:0xfe00; valaddr_reg:x2; val_offset:31269*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31269*FLEN/8, x3, x1, x4) + +inst_10458: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8001; +op3val:0x7e01; valaddr_reg:x2; val_offset:31272*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31272*FLEN/8, x3, x1, x4) + +inst_10459: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8001; +op3val:0xfe55; valaddr_reg:x2; val_offset:31275*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31275*FLEN/8, x3, x1, x4) + +inst_10460: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8001; +op3val:0x7c01; valaddr_reg:x2; val_offset:31278*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31278*FLEN/8, x3, x1, x4) + +inst_10461: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8001; +op3val:0xfd55; valaddr_reg:x2; val_offset:31281*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31281*FLEN/8, x3, x1, x4) + +inst_10462: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8001; +op3val:0x3c00; valaddr_reg:x2; val_offset:31284*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31284*FLEN/8, x3, x1, x4) + +inst_10463: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8001; +op3val:0xbc00; valaddr_reg:x2; val_offset:31287*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31287*FLEN/8, x3, x1, x4) + +inst_10464: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x2; +op3val:0x0; valaddr_reg:x2; val_offset:31290*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31290*FLEN/8, x3, x1, x4) + +inst_10465: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x2; +op3val:0x8000; valaddr_reg:x2; val_offset:31293*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31293*FLEN/8, x3, x1, x4) + +inst_10466: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x2; +op3val:0x1; valaddr_reg:x2; val_offset:31296*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31296*FLEN/8, x3, x1, x4) + +inst_10467: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x2; +op3val:0x8001; valaddr_reg:x2; val_offset:31299*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31299*FLEN/8, x3, x1, x4) + +inst_10468: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x2; +op3val:0x2; valaddr_reg:x2; val_offset:31302*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31302*FLEN/8, x3, x1, x4) + +inst_10469: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x2; +op3val:0x83fe; valaddr_reg:x2; val_offset:31305*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31305*FLEN/8, x3, x1, x4) + +inst_10470: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x2; +op3val:0x3ff; valaddr_reg:x2; val_offset:31308*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31308*FLEN/8, x3, x1, x4) + +inst_10471: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x2; +op3val:0x83ff; valaddr_reg:x2; val_offset:31311*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31311*FLEN/8, x3, x1, x4) + +inst_10472: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x2; +op3val:0x400; valaddr_reg:x2; val_offset:31314*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31314*FLEN/8, x3, x1, x4) + +inst_10473: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x2; +op3val:0x8400; valaddr_reg:x2; val_offset:31317*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31317*FLEN/8, x3, x1, x4) + +inst_10474: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x2; +op3val:0x401; valaddr_reg:x2; val_offset:31320*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31320*FLEN/8, x3, x1, x4) + +inst_10475: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x2; +op3val:0x8455; valaddr_reg:x2; val_offset:31323*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31323*FLEN/8, x3, x1, x4) + +inst_10476: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x2; +op3val:0x7bff; valaddr_reg:x2; val_offset:31326*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31326*FLEN/8, x3, x1, x4) + +inst_10477: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x2; +op3val:0xfbff; valaddr_reg:x2; val_offset:31329*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31329*FLEN/8, x3, x1, x4) + +inst_10478: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x2; +op3val:0x7c00; valaddr_reg:x2; val_offset:31332*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31332*FLEN/8, x3, x1, x4) + +inst_10479: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x2; +op3val:0xfc00; valaddr_reg:x2; val_offset:31335*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31335*FLEN/8, x3, x1, x4) + +inst_10480: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x2; +op3val:0x7e00; valaddr_reg:x2; val_offset:31338*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31338*FLEN/8, x3, x1, x4) + +inst_10481: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x2; +op3val:0xfe00; valaddr_reg:x2; val_offset:31341*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31341*FLEN/8, x3, x1, x4) + +inst_10482: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x2; +op3val:0x7e01; valaddr_reg:x2; val_offset:31344*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31344*FLEN/8, x3, x1, x4) + +inst_10483: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x2; +op3val:0xfe55; valaddr_reg:x2; val_offset:31347*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31347*FLEN/8, x3, x1, x4) + +inst_10484: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x2; +op3val:0x7c01; valaddr_reg:x2; val_offset:31350*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31350*FLEN/8, x3, x1, x4) + +inst_10485: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x2; +op3val:0xfd55; valaddr_reg:x2; val_offset:31353*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31353*FLEN/8, x3, x1, x4) + +inst_10486: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x2; +op3val:0x3c00; valaddr_reg:x2; val_offset:31356*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31356*FLEN/8, x3, x1, x4) + +inst_10487: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x2; +op3val:0xbc00; valaddr_reg:x2; val_offset:31359*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31359*FLEN/8, x3, x1, x4) + +inst_10488: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x83fe; +op3val:0x0; valaddr_reg:x2; val_offset:31362*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31362*FLEN/8, x3, x1, x4) + +inst_10489: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x83fe; +op3val:0x8000; valaddr_reg:x2; val_offset:31365*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31365*FLEN/8, x3, x1, x4) + +inst_10490: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x83fe; +op3val:0x1; valaddr_reg:x2; val_offset:31368*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31368*FLEN/8, x3, x1, x4) + +inst_10491: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x83fe; +op3val:0x8001; valaddr_reg:x2; val_offset:31371*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31371*FLEN/8, x3, x1, x4) + +inst_10492: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x83fe; +op3val:0x2; valaddr_reg:x2; val_offset:31374*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31374*FLEN/8, x3, x1, x4) + +inst_10493: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x83fe; +op3val:0x83fe; valaddr_reg:x2; val_offset:31377*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31377*FLEN/8, x3, x1, x4) + +inst_10494: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x83fe; +op3val:0x3ff; valaddr_reg:x2; val_offset:31380*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31380*FLEN/8, x3, x1, x4) + +inst_10495: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x83fe; +op3val:0x83ff; valaddr_reg:x2; val_offset:31383*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31383*FLEN/8, x3, x1, x4) + +inst_10496: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x83fe; +op3val:0x400; valaddr_reg:x2; val_offset:31386*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31386*FLEN/8, x3, x1, x4) + +inst_10497: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x83fe; +op3val:0x8400; valaddr_reg:x2; val_offset:31389*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31389*FLEN/8, x3, x1, x4) + +inst_10498: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x83fe; +op3val:0x401; valaddr_reg:x2; val_offset:31392*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31392*FLEN/8, x3, x1, x4) + +inst_10499: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x83fe; +op3val:0x8455; valaddr_reg:x2; val_offset:31395*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31395*FLEN/8, x3, x1, x4) + +inst_10500: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x83fe; +op3val:0x7bff; valaddr_reg:x2; val_offset:31398*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31398*FLEN/8, x3, x1, x4) + +inst_10501: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x83fe; +op3val:0xfbff; valaddr_reg:x2; val_offset:31401*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31401*FLEN/8, x3, x1, x4) + +inst_10502: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x83fe; +op3val:0x7c00; valaddr_reg:x2; val_offset:31404*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31404*FLEN/8, x3, x1, x4) + +inst_10503: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x83fe; +op3val:0xfc00; valaddr_reg:x2; val_offset:31407*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31407*FLEN/8, x3, x1, x4) + +inst_10504: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x83fe; +op3val:0x7e00; valaddr_reg:x2; val_offset:31410*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31410*FLEN/8, x3, x1, x4) + +inst_10505: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x83fe; +op3val:0xfe00; valaddr_reg:x2; val_offset:31413*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31413*FLEN/8, x3, x1, x4) + +inst_10506: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x83fe; +op3val:0x7e01; valaddr_reg:x2; val_offset:31416*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31416*FLEN/8, x3, x1, x4) + +inst_10507: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x83fe; +op3val:0xfe55; valaddr_reg:x2; val_offset:31419*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31419*FLEN/8, x3, x1, x4) + +inst_10508: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x83fe; +op3val:0x7c01; valaddr_reg:x2; val_offset:31422*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31422*FLEN/8, x3, x1, x4) + +inst_10509: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x83fe; +op3val:0xfd55; valaddr_reg:x2; val_offset:31425*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31425*FLEN/8, x3, x1, x4) + +inst_10510: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x83fe; +op3val:0x3c00; valaddr_reg:x2; val_offset:31428*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31428*FLEN/8, x3, x1, x4) + +inst_10511: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x83fe; +op3val:0xbc00; valaddr_reg:x2; val_offset:31431*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31431*FLEN/8, x3, x1, x4) + +inst_10512: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x3ff; +op3val:0x0; valaddr_reg:x2; val_offset:31434*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31434*FLEN/8, x3, x1, x4) + +inst_10513: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x3ff; +op3val:0x8000; valaddr_reg:x2; val_offset:31437*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31437*FLEN/8, x3, x1, x4) + +inst_10514: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x3ff; +op3val:0x1; valaddr_reg:x2; val_offset:31440*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31440*FLEN/8, x3, x1, x4) + +inst_10515: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x3ff; +op3val:0x8001; valaddr_reg:x2; val_offset:31443*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31443*FLEN/8, x3, x1, x4) + +inst_10516: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x3ff; +op3val:0x2; valaddr_reg:x2; val_offset:31446*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31446*FLEN/8, x3, x1, x4) + +inst_10517: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x3ff; +op3val:0x83fe; valaddr_reg:x2; val_offset:31449*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31449*FLEN/8, x3, x1, x4) + +inst_10518: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x3ff; +op3val:0x3ff; valaddr_reg:x2; val_offset:31452*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31452*FLEN/8, x3, x1, x4) + +inst_10519: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x3ff; +op3val:0x83ff; valaddr_reg:x2; val_offset:31455*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31455*FLEN/8, x3, x1, x4) + +inst_10520: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x3ff; +op3val:0x400; valaddr_reg:x2; val_offset:31458*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31458*FLEN/8, x3, x1, x4) + +inst_10521: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x3ff; +op3val:0x8400; valaddr_reg:x2; val_offset:31461*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31461*FLEN/8, x3, x1, x4) + +inst_10522: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x3ff; +op3val:0x401; valaddr_reg:x2; val_offset:31464*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31464*FLEN/8, x3, x1, x4) + +inst_10523: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x3ff; +op3val:0x8455; valaddr_reg:x2; val_offset:31467*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31467*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_83) + +inst_10524: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x3ff; +op3val:0x7bff; valaddr_reg:x2; val_offset:31470*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31470*FLEN/8, x3, x1, x4) + +inst_10525: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x3ff; +op3val:0xfbff; valaddr_reg:x2; val_offset:31473*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31473*FLEN/8, x3, x1, x4) + +inst_10526: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x3ff; +op3val:0x7c00; valaddr_reg:x2; val_offset:31476*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31476*FLEN/8, x3, x1, x4) + +inst_10527: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x3ff; +op3val:0xfc00; valaddr_reg:x2; val_offset:31479*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31479*FLEN/8, x3, x1, x4) + +inst_10528: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x3ff; +op3val:0x7e00; valaddr_reg:x2; val_offset:31482*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31482*FLEN/8, x3, x1, x4) + +inst_10529: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x3ff; +op3val:0xfe00; valaddr_reg:x2; val_offset:31485*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31485*FLEN/8, x3, x1, x4) + +inst_10530: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x3ff; +op3val:0x7e01; valaddr_reg:x2; val_offset:31488*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31488*FLEN/8, x3, x1, x4) + +inst_10531: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x3ff; +op3val:0xfe55; valaddr_reg:x2; val_offset:31491*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31491*FLEN/8, x3, x1, x4) + +inst_10532: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x3ff; +op3val:0x7c01; valaddr_reg:x2; val_offset:31494*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31494*FLEN/8, x3, x1, x4) + +inst_10533: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x3ff; +op3val:0xfd55; valaddr_reg:x2; val_offset:31497*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31497*FLEN/8, x3, x1, x4) + +inst_10534: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x3ff; +op3val:0x3c00; valaddr_reg:x2; val_offset:31500*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31500*FLEN/8, x3, x1, x4) + +inst_10535: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x3ff; +op3val:0xbc00; valaddr_reg:x2; val_offset:31503*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31503*FLEN/8, x3, x1, x4) + +inst_10536: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x83ff; +op3val:0x0; valaddr_reg:x2; val_offset:31506*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31506*FLEN/8, x3, x1, x4) + +inst_10537: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x83ff; +op3val:0x8000; valaddr_reg:x2; val_offset:31509*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31509*FLEN/8, x3, x1, x4) + +inst_10538: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x83ff; +op3val:0x1; valaddr_reg:x2; val_offset:31512*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31512*FLEN/8, x3, x1, x4) + +inst_10539: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x83ff; +op3val:0x8001; valaddr_reg:x2; val_offset:31515*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31515*FLEN/8, x3, x1, x4) + +inst_10540: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x83ff; +op3val:0x2; valaddr_reg:x2; val_offset:31518*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31518*FLEN/8, x3, x1, x4) + +inst_10541: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x83ff; +op3val:0x83fe; valaddr_reg:x2; val_offset:31521*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31521*FLEN/8, x3, x1, x4) + +inst_10542: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x83ff; +op3val:0x3ff; valaddr_reg:x2; val_offset:31524*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31524*FLEN/8, x3, x1, x4) + +inst_10543: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x83ff; +op3val:0x83ff; valaddr_reg:x2; val_offset:31527*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31527*FLEN/8, x3, x1, x4) + +inst_10544: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x83ff; +op3val:0x400; valaddr_reg:x2; val_offset:31530*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31530*FLEN/8, x3, x1, x4) + +inst_10545: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x83ff; +op3val:0x8400; valaddr_reg:x2; val_offset:31533*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31533*FLEN/8, x3, x1, x4) + +inst_10546: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x83ff; +op3val:0x401; valaddr_reg:x2; val_offset:31536*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31536*FLEN/8, x3, x1, x4) + +inst_10547: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x83ff; +op3val:0x8455; valaddr_reg:x2; val_offset:31539*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31539*FLEN/8, x3, x1, x4) + +inst_10548: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x83ff; +op3val:0x7bff; valaddr_reg:x2; val_offset:31542*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31542*FLEN/8, x3, x1, x4) + +inst_10549: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x83ff; +op3val:0xfbff; valaddr_reg:x2; val_offset:31545*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31545*FLEN/8, x3, x1, x4) + +inst_10550: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x83ff; +op3val:0x7c00; valaddr_reg:x2; val_offset:31548*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31548*FLEN/8, x3, x1, x4) + +inst_10551: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x83ff; +op3val:0xfc00; valaddr_reg:x2; val_offset:31551*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31551*FLEN/8, x3, x1, x4) + +inst_10552: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x83ff; +op3val:0x7e00; valaddr_reg:x2; val_offset:31554*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31554*FLEN/8, x3, x1, x4) + +inst_10553: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x83ff; +op3val:0xfe00; valaddr_reg:x2; val_offset:31557*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31557*FLEN/8, x3, x1, x4) + +inst_10554: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x83ff; +op3val:0x7e01; valaddr_reg:x2; val_offset:31560*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31560*FLEN/8, x3, x1, x4) + +inst_10555: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x83ff; +op3val:0xfe55; valaddr_reg:x2; val_offset:31563*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31563*FLEN/8, x3, x1, x4) + +inst_10556: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x83ff; +op3val:0x7c01; valaddr_reg:x2; val_offset:31566*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31566*FLEN/8, x3, x1, x4) + +inst_10557: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x83ff; +op3val:0xfd55; valaddr_reg:x2; val_offset:31569*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31569*FLEN/8, x3, x1, x4) + +inst_10558: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x83ff; +op3val:0x3c00; valaddr_reg:x2; val_offset:31572*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31572*FLEN/8, x3, x1, x4) + +inst_10559: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x83ff; +op3val:0xbc00; valaddr_reg:x2; val_offset:31575*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31575*FLEN/8, x3, x1, x4) + +inst_10560: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x400; +op3val:0x0; valaddr_reg:x2; val_offset:31578*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31578*FLEN/8, x3, x1, x4) + +inst_10561: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x400; +op3val:0x8000; valaddr_reg:x2; val_offset:31581*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31581*FLEN/8, x3, x1, x4) + +inst_10562: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x400; +op3val:0x1; valaddr_reg:x2; val_offset:31584*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31584*FLEN/8, x3, x1, x4) + +inst_10563: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x400; +op3val:0x8001; valaddr_reg:x2; val_offset:31587*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31587*FLEN/8, x3, x1, x4) + +inst_10564: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x400; +op3val:0x2; valaddr_reg:x2; val_offset:31590*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31590*FLEN/8, x3, x1, x4) + +inst_10565: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x400; +op3val:0x83fe; valaddr_reg:x2; val_offset:31593*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31593*FLEN/8, x3, x1, x4) + +inst_10566: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x400; +op3val:0x3ff; valaddr_reg:x2; val_offset:31596*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31596*FLEN/8, x3, x1, x4) + +inst_10567: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x400; +op3val:0x83ff; valaddr_reg:x2; val_offset:31599*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31599*FLEN/8, x3, x1, x4) + +inst_10568: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x400; +op3val:0x400; valaddr_reg:x2; val_offset:31602*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31602*FLEN/8, x3, x1, x4) + +inst_10569: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x400; +op3val:0x8400; valaddr_reg:x2; val_offset:31605*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31605*FLEN/8, x3, x1, x4) + +inst_10570: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x400; +op3val:0x401; valaddr_reg:x2; val_offset:31608*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31608*FLEN/8, x3, x1, x4) + +inst_10571: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x400; +op3val:0x8455; valaddr_reg:x2; val_offset:31611*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31611*FLEN/8, x3, x1, x4) + +inst_10572: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x400; +op3val:0x7bff; valaddr_reg:x2; val_offset:31614*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31614*FLEN/8, x3, x1, x4) + +inst_10573: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x400; +op3val:0xfbff; valaddr_reg:x2; val_offset:31617*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31617*FLEN/8, x3, x1, x4) + +inst_10574: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x400; +op3val:0x7c00; valaddr_reg:x2; val_offset:31620*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31620*FLEN/8, x3, x1, x4) + +inst_10575: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x400; +op3val:0xfc00; valaddr_reg:x2; val_offset:31623*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31623*FLEN/8, x3, x1, x4) + +inst_10576: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x400; +op3val:0x7e00; valaddr_reg:x2; val_offset:31626*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31626*FLEN/8, x3, x1, x4) + +inst_10577: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x400; +op3val:0xfe00; valaddr_reg:x2; val_offset:31629*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31629*FLEN/8, x3, x1, x4) + +inst_10578: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x400; +op3val:0x7e01; valaddr_reg:x2; val_offset:31632*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31632*FLEN/8, x3, x1, x4) + +inst_10579: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x400; +op3val:0xfe55; valaddr_reg:x2; val_offset:31635*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31635*FLEN/8, x3, x1, x4) + +inst_10580: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x400; +op3val:0x7c01; valaddr_reg:x2; val_offset:31638*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31638*FLEN/8, x3, x1, x4) + +inst_10581: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x400; +op3val:0xfd55; valaddr_reg:x2; val_offset:31641*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31641*FLEN/8, x3, x1, x4) + +inst_10582: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x400; +op3val:0x3c00; valaddr_reg:x2; val_offset:31644*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31644*FLEN/8, x3, x1, x4) + +inst_10583: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x400; +op3val:0xbc00; valaddr_reg:x2; val_offset:31647*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31647*FLEN/8, x3, x1, x4) + +inst_10584: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8400; +op3val:0x0; valaddr_reg:x2; val_offset:31650*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31650*FLEN/8, x3, x1, x4) + +inst_10585: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8400; +op3val:0x8000; valaddr_reg:x2; val_offset:31653*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31653*FLEN/8, x3, x1, x4) + +inst_10586: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8400; +op3val:0x1; valaddr_reg:x2; val_offset:31656*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31656*FLEN/8, x3, x1, x4) + +inst_10587: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8400; +op3val:0x8001; valaddr_reg:x2; val_offset:31659*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31659*FLEN/8, x3, x1, x4) + +inst_10588: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8400; +op3val:0x2; valaddr_reg:x2; val_offset:31662*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31662*FLEN/8, x3, x1, x4) + +inst_10589: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8400; +op3val:0x83fe; valaddr_reg:x2; val_offset:31665*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31665*FLEN/8, x3, x1, x4) + +inst_10590: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8400; +op3val:0x3ff; valaddr_reg:x2; val_offset:31668*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31668*FLEN/8, x3, x1, x4) + +inst_10591: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8400; +op3val:0x83ff; valaddr_reg:x2; val_offset:31671*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31671*FLEN/8, x3, x1, x4) + +inst_10592: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8400; +op3val:0x400; valaddr_reg:x2; val_offset:31674*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31674*FLEN/8, x3, x1, x4) + +inst_10593: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8400; +op3val:0x8400; valaddr_reg:x2; val_offset:31677*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31677*FLEN/8, x3, x1, x4) + +inst_10594: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8400; +op3val:0x401; valaddr_reg:x2; val_offset:31680*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31680*FLEN/8, x3, x1, x4) + +inst_10595: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8400; +op3val:0x8455; valaddr_reg:x2; val_offset:31683*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31683*FLEN/8, x3, x1, x4) + +inst_10596: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8400; +op3val:0x7bff; valaddr_reg:x2; val_offset:31686*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31686*FLEN/8, x3, x1, x4) + +inst_10597: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8400; +op3val:0xfbff; valaddr_reg:x2; val_offset:31689*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31689*FLEN/8, x3, x1, x4) + +inst_10598: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8400; +op3val:0x7c00; valaddr_reg:x2; val_offset:31692*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31692*FLEN/8, x3, x1, x4) + +inst_10599: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8400; +op3val:0xfc00; valaddr_reg:x2; val_offset:31695*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31695*FLEN/8, x3, x1, x4) + +inst_10600: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8400; +op3val:0x7e00; valaddr_reg:x2; val_offset:31698*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31698*FLEN/8, x3, x1, x4) + +inst_10601: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8400; +op3val:0xfe00; valaddr_reg:x2; val_offset:31701*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31701*FLEN/8, x3, x1, x4) + +inst_10602: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8400; +op3val:0x7e01; valaddr_reg:x2; val_offset:31704*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31704*FLEN/8, x3, x1, x4) + +inst_10603: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8400; +op3val:0xfe55; valaddr_reg:x2; val_offset:31707*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31707*FLEN/8, x3, x1, x4) + +inst_10604: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8400; +op3val:0x7c01; valaddr_reg:x2; val_offset:31710*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31710*FLEN/8, x3, x1, x4) + +inst_10605: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8400; +op3val:0xfd55; valaddr_reg:x2; val_offset:31713*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31713*FLEN/8, x3, x1, x4) + +inst_10606: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8400; +op3val:0x3c00; valaddr_reg:x2; val_offset:31716*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31716*FLEN/8, x3, x1, x4) + +inst_10607: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8400; +op3val:0xbc00; valaddr_reg:x2; val_offset:31719*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31719*FLEN/8, x3, x1, x4) + +inst_10608: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x401; +op3val:0x0; valaddr_reg:x2; val_offset:31722*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31722*FLEN/8, x3, x1, x4) + +inst_10609: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x401; +op3val:0x8000; valaddr_reg:x2; val_offset:31725*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31725*FLEN/8, x3, x1, x4) + +inst_10610: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x401; +op3val:0x1; valaddr_reg:x2; val_offset:31728*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31728*FLEN/8, x3, x1, x4) + +inst_10611: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x401; +op3val:0x8001; valaddr_reg:x2; val_offset:31731*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31731*FLEN/8, x3, x1, x4) + +inst_10612: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x401; +op3val:0x2; valaddr_reg:x2; val_offset:31734*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31734*FLEN/8, x3, x1, x4) + +inst_10613: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x401; +op3val:0x83fe; valaddr_reg:x2; val_offset:31737*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31737*FLEN/8, x3, x1, x4) + +inst_10614: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x401; +op3val:0x3ff; valaddr_reg:x2; val_offset:31740*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31740*FLEN/8, x3, x1, x4) + +inst_10615: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x401; +op3val:0x83ff; valaddr_reg:x2; val_offset:31743*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31743*FLEN/8, x3, x1, x4) + +inst_10616: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x401; +op3val:0x400; valaddr_reg:x2; val_offset:31746*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31746*FLEN/8, x3, x1, x4) + +inst_10617: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x401; +op3val:0x8400; valaddr_reg:x2; val_offset:31749*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31749*FLEN/8, x3, x1, x4) + +inst_10618: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x401; +op3val:0x401; valaddr_reg:x2; val_offset:31752*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31752*FLEN/8, x3, x1, x4) + +inst_10619: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x401; +op3val:0x8455; valaddr_reg:x2; val_offset:31755*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31755*FLEN/8, x3, x1, x4) + +inst_10620: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x401; +op3val:0x7bff; valaddr_reg:x2; val_offset:31758*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31758*FLEN/8, x3, x1, x4) + +inst_10621: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x401; +op3val:0xfbff; valaddr_reg:x2; val_offset:31761*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31761*FLEN/8, x3, x1, x4) + +inst_10622: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x401; +op3val:0x7c00; valaddr_reg:x2; val_offset:31764*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31764*FLEN/8, x3, x1, x4) + +inst_10623: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x401; +op3val:0xfc00; valaddr_reg:x2; val_offset:31767*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31767*FLEN/8, x3, x1, x4) + +inst_10624: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x401; +op3val:0x7e00; valaddr_reg:x2; val_offset:31770*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31770*FLEN/8, x3, x1, x4) + +inst_10625: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x401; +op3val:0xfe00; valaddr_reg:x2; val_offset:31773*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31773*FLEN/8, x3, x1, x4) + +inst_10626: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x401; +op3val:0x7e01; valaddr_reg:x2; val_offset:31776*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31776*FLEN/8, x3, x1, x4) + +inst_10627: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x401; +op3val:0xfe55; valaddr_reg:x2; val_offset:31779*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31779*FLEN/8, x3, x1, x4) + +inst_10628: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x401; +op3val:0x7c01; valaddr_reg:x2; val_offset:31782*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31782*FLEN/8, x3, x1, x4) + +inst_10629: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x401; +op3val:0xfd55; valaddr_reg:x2; val_offset:31785*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31785*FLEN/8, x3, x1, x4) + +inst_10630: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x401; +op3val:0x3c00; valaddr_reg:x2; val_offset:31788*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31788*FLEN/8, x3, x1, x4) + +inst_10631: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x401; +op3val:0xbc00; valaddr_reg:x2; val_offset:31791*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31791*FLEN/8, x3, x1, x4) + +inst_10632: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8455; +op3val:0x0; valaddr_reg:x2; val_offset:31794*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31794*FLEN/8, x3, x1, x4) + +inst_10633: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8455; +op3val:0x8000; valaddr_reg:x2; val_offset:31797*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31797*FLEN/8, x3, x1, x4) + +inst_10634: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8455; +op3val:0x1; valaddr_reg:x2; val_offset:31800*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31800*FLEN/8, x3, x1, x4) + +inst_10635: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8455; +op3val:0x8001; valaddr_reg:x2; val_offset:31803*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31803*FLEN/8, x3, x1, x4) + +inst_10636: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8455; +op3val:0x2; valaddr_reg:x2; val_offset:31806*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31806*FLEN/8, x3, x1, x4) + +inst_10637: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8455; +op3val:0x83fe; valaddr_reg:x2; val_offset:31809*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31809*FLEN/8, x3, x1, x4) + +inst_10638: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8455; +op3val:0x3ff; valaddr_reg:x2; val_offset:31812*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31812*FLEN/8, x3, x1, x4) + +inst_10639: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8455; +op3val:0x83ff; valaddr_reg:x2; val_offset:31815*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31815*FLEN/8, x3, x1, x4) + +inst_10640: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8455; +op3val:0x400; valaddr_reg:x2; val_offset:31818*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31818*FLEN/8, x3, x1, x4) + +inst_10641: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8455; +op3val:0x8400; valaddr_reg:x2; val_offset:31821*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31821*FLEN/8, x3, x1, x4) + +inst_10642: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8455; +op3val:0x401; valaddr_reg:x2; val_offset:31824*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31824*FLEN/8, x3, x1, x4) + +inst_10643: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8455; +op3val:0x8455; valaddr_reg:x2; val_offset:31827*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31827*FLEN/8, x3, x1, x4) + +inst_10644: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8455; +op3val:0x7bff; valaddr_reg:x2; val_offset:31830*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31830*FLEN/8, x3, x1, x4) + +inst_10645: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8455; +op3val:0xfbff; valaddr_reg:x2; val_offset:31833*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31833*FLEN/8, x3, x1, x4) + +inst_10646: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8455; +op3val:0x7c00; valaddr_reg:x2; val_offset:31836*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31836*FLEN/8, x3, x1, x4) + +inst_10647: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8455; +op3val:0xfc00; valaddr_reg:x2; val_offset:31839*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31839*FLEN/8, x3, x1, x4) + +inst_10648: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8455; +op3val:0x7e00; valaddr_reg:x2; val_offset:31842*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31842*FLEN/8, x3, x1, x4) + +inst_10649: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8455; +op3val:0xfe00; valaddr_reg:x2; val_offset:31845*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31845*FLEN/8, x3, x1, x4) + +inst_10650: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8455; +op3val:0x7e01; valaddr_reg:x2; val_offset:31848*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31848*FLEN/8, x3, x1, x4) + +inst_10651: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8455; +op3val:0xfe55; valaddr_reg:x2; val_offset:31851*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31851*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_84) + +inst_10652: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8455; +op3val:0x7c01; valaddr_reg:x2; val_offset:31854*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31854*FLEN/8, x3, x1, x4) + +inst_10653: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8455; +op3val:0xfd55; valaddr_reg:x2; val_offset:31857*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31857*FLEN/8, x3, x1, x4) + +inst_10654: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8455; +op3val:0x3c00; valaddr_reg:x2; val_offset:31860*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31860*FLEN/8, x3, x1, x4) + +inst_10655: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x8455; +op3val:0xbc00; valaddr_reg:x2; val_offset:31863*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31863*FLEN/8, x3, x1, x4) + +inst_10656: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7bff; +op3val:0x0; valaddr_reg:x2; val_offset:31866*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31866*FLEN/8, x3, x1, x4) + +inst_10657: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7bff; +op3val:0x8000; valaddr_reg:x2; val_offset:31869*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31869*FLEN/8, x3, x1, x4) + +inst_10658: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7bff; +op3val:0x1; valaddr_reg:x2; val_offset:31872*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31872*FLEN/8, x3, x1, x4) + +inst_10659: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7bff; +op3val:0x8001; valaddr_reg:x2; val_offset:31875*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31875*FLEN/8, x3, x1, x4) + +inst_10660: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7bff; +op3val:0x2; valaddr_reg:x2; val_offset:31878*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31878*FLEN/8, x3, x1, x4) + +inst_10661: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7bff; +op3val:0x83fe; valaddr_reg:x2; val_offset:31881*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31881*FLEN/8, x3, x1, x4) + +inst_10662: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7bff; +op3val:0x3ff; valaddr_reg:x2; val_offset:31884*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31884*FLEN/8, x3, x1, x4) + +inst_10663: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7bff; +op3val:0x83ff; valaddr_reg:x2; val_offset:31887*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31887*FLEN/8, x3, x1, x4) + +inst_10664: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7bff; +op3val:0x400; valaddr_reg:x2; val_offset:31890*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31890*FLEN/8, x3, x1, x4) + +inst_10665: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7bff; +op3val:0x8400; valaddr_reg:x2; val_offset:31893*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31893*FLEN/8, x3, x1, x4) + +inst_10666: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7bff; +op3val:0x401; valaddr_reg:x2; val_offset:31896*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31896*FLEN/8, x3, x1, x4) + +inst_10667: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7bff; +op3val:0x8455; valaddr_reg:x2; val_offset:31899*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31899*FLEN/8, x3, x1, x4) + +inst_10668: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7bff; +op3val:0x7bff; valaddr_reg:x2; val_offset:31902*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31902*FLEN/8, x3, x1, x4) + +inst_10669: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7bff; +op3val:0xfbff; valaddr_reg:x2; val_offset:31905*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31905*FLEN/8, x3, x1, x4) + +inst_10670: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7bff; +op3val:0x7c00; valaddr_reg:x2; val_offset:31908*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31908*FLEN/8, x3, x1, x4) + +inst_10671: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7bff; +op3val:0xfc00; valaddr_reg:x2; val_offset:31911*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31911*FLEN/8, x3, x1, x4) + +inst_10672: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7bff; +op3val:0x7e00; valaddr_reg:x2; val_offset:31914*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31914*FLEN/8, x3, x1, x4) + +inst_10673: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7bff; +op3val:0xfe00; valaddr_reg:x2; val_offset:31917*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31917*FLEN/8, x3, x1, x4) + +inst_10674: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7bff; +op3val:0x7e01; valaddr_reg:x2; val_offset:31920*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31920*FLEN/8, x3, x1, x4) + +inst_10675: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7bff; +op3val:0xfe55; valaddr_reg:x2; val_offset:31923*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31923*FLEN/8, x3, x1, x4) + +inst_10676: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7bff; +op3val:0x7c01; valaddr_reg:x2; val_offset:31926*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31926*FLEN/8, x3, x1, x4) + +inst_10677: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7bff; +op3val:0xfd55; valaddr_reg:x2; val_offset:31929*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31929*FLEN/8, x3, x1, x4) + +inst_10678: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7bff; +op3val:0x3c00; valaddr_reg:x2; val_offset:31932*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31932*FLEN/8, x3, x1, x4) + +inst_10679: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7bff; +op3val:0xbc00; valaddr_reg:x2; val_offset:31935*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31935*FLEN/8, x3, x1, x4) + +inst_10680: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfbff; +op3val:0x0; valaddr_reg:x2; val_offset:31938*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31938*FLEN/8, x3, x1, x4) + +inst_10681: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfbff; +op3val:0x8000; valaddr_reg:x2; val_offset:31941*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31941*FLEN/8, x3, x1, x4) + +inst_10682: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfbff; +op3val:0x1; valaddr_reg:x2; val_offset:31944*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31944*FLEN/8, x3, x1, x4) + +inst_10683: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfbff; +op3val:0x8001; valaddr_reg:x2; val_offset:31947*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31947*FLEN/8, x3, x1, x4) + +inst_10684: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfbff; +op3val:0x2; valaddr_reg:x2; val_offset:31950*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31950*FLEN/8, x3, x1, x4) + +inst_10685: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfbff; +op3val:0x83fe; valaddr_reg:x2; val_offset:31953*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31953*FLEN/8, x3, x1, x4) + +inst_10686: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfbff; +op3val:0x3ff; valaddr_reg:x2; val_offset:31956*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31956*FLEN/8, x3, x1, x4) + +inst_10687: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfbff; +op3val:0x83ff; valaddr_reg:x2; val_offset:31959*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31959*FLEN/8, x3, x1, x4) + +inst_10688: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfbff; +op3val:0x400; valaddr_reg:x2; val_offset:31962*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31962*FLEN/8, x3, x1, x4) + +inst_10689: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfbff; +op3val:0x8400; valaddr_reg:x2; val_offset:31965*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31965*FLEN/8, x3, x1, x4) + +inst_10690: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfbff; +op3val:0x401; valaddr_reg:x2; val_offset:31968*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31968*FLEN/8, x3, x1, x4) + +inst_10691: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfbff; +op3val:0x8455; valaddr_reg:x2; val_offset:31971*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31971*FLEN/8, x3, x1, x4) + +inst_10692: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfbff; +op3val:0x7bff; valaddr_reg:x2; val_offset:31974*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31974*FLEN/8, x3, x1, x4) + +inst_10693: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfbff; +op3val:0xfbff; valaddr_reg:x2; val_offset:31977*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31977*FLEN/8, x3, x1, x4) + +inst_10694: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfbff; +op3val:0x7c00; valaddr_reg:x2; val_offset:31980*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31980*FLEN/8, x3, x1, x4) + +inst_10695: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfbff; +op3val:0xfc00; valaddr_reg:x2; val_offset:31983*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31983*FLEN/8, x3, x1, x4) + +inst_10696: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfbff; +op3val:0x7e00; valaddr_reg:x2; val_offset:31986*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31986*FLEN/8, x3, x1, x4) + +inst_10697: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfbff; +op3val:0xfe00; valaddr_reg:x2; val_offset:31989*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31989*FLEN/8, x3, x1, x4) + +inst_10698: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfbff; +op3val:0x7e01; valaddr_reg:x2; val_offset:31992*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31992*FLEN/8, x3, x1, x4) + +inst_10699: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfbff; +op3val:0xfe55; valaddr_reg:x2; val_offset:31995*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31995*FLEN/8, x3, x1, x4) + +inst_10700: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfbff; +op3val:0x7c01; valaddr_reg:x2; val_offset:31998*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 31998*FLEN/8, x3, x1, x4) + +inst_10701: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfbff; +op3val:0xfd55; valaddr_reg:x2; val_offset:32001*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32001*FLEN/8, x3, x1, x4) + +inst_10702: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfbff; +op3val:0x3c00; valaddr_reg:x2; val_offset:32004*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32004*FLEN/8, x3, x1, x4) + +inst_10703: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfbff; +op3val:0xbc00; valaddr_reg:x2; val_offset:32007*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32007*FLEN/8, x3, x1, x4) + +inst_10704: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7c00; +op3val:0x0; valaddr_reg:x2; val_offset:32010*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32010*FLEN/8, x3, x1, x4) + +inst_10705: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7c00; +op3val:0x8000; valaddr_reg:x2; val_offset:32013*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32013*FLEN/8, x3, x1, x4) + +inst_10706: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7c00; +op3val:0x1; valaddr_reg:x2; val_offset:32016*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32016*FLEN/8, x3, x1, x4) + +inst_10707: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7c00; +op3val:0x8001; valaddr_reg:x2; val_offset:32019*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32019*FLEN/8, x3, x1, x4) + +inst_10708: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7c00; +op3val:0x2; valaddr_reg:x2; val_offset:32022*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32022*FLEN/8, x3, x1, x4) + +inst_10709: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7c00; +op3val:0x83fe; valaddr_reg:x2; val_offset:32025*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32025*FLEN/8, x3, x1, x4) + +inst_10710: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7c00; +op3val:0x3ff; valaddr_reg:x2; val_offset:32028*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32028*FLEN/8, x3, x1, x4) + +inst_10711: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7c00; +op3val:0x83ff; valaddr_reg:x2; val_offset:32031*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32031*FLEN/8, x3, x1, x4) + +inst_10712: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7c00; +op3val:0x400; valaddr_reg:x2; val_offset:32034*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32034*FLEN/8, x3, x1, x4) + +inst_10713: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7c00; +op3val:0x8400; valaddr_reg:x2; val_offset:32037*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32037*FLEN/8, x3, x1, x4) + +inst_10714: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7c00; +op3val:0x401; valaddr_reg:x2; val_offset:32040*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32040*FLEN/8, x3, x1, x4) + +inst_10715: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7c00; +op3val:0x8455; valaddr_reg:x2; val_offset:32043*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32043*FLEN/8, x3, x1, x4) + +inst_10716: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7c00; +op3val:0x7bff; valaddr_reg:x2; val_offset:32046*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32046*FLEN/8, x3, x1, x4) + +inst_10717: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7c00; +op3val:0xfbff; valaddr_reg:x2; val_offset:32049*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32049*FLEN/8, x3, x1, x4) + +inst_10718: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7c00; +op3val:0x7c00; valaddr_reg:x2; val_offset:32052*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32052*FLEN/8, x3, x1, x4) + +inst_10719: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7c00; +op3val:0xfc00; valaddr_reg:x2; val_offset:32055*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32055*FLEN/8, x3, x1, x4) + +inst_10720: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7c00; +op3val:0x7e00; valaddr_reg:x2; val_offset:32058*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32058*FLEN/8, x3, x1, x4) + +inst_10721: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7c00; +op3val:0xfe00; valaddr_reg:x2; val_offset:32061*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32061*FLEN/8, x3, x1, x4) + +inst_10722: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7c00; +op3val:0x7e01; valaddr_reg:x2; val_offset:32064*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32064*FLEN/8, x3, x1, x4) + +inst_10723: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7c00; +op3val:0xfe55; valaddr_reg:x2; val_offset:32067*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32067*FLEN/8, x3, x1, x4) + +inst_10724: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7c00; +op3val:0x7c01; valaddr_reg:x2; val_offset:32070*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32070*FLEN/8, x3, x1, x4) + +inst_10725: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7c00; +op3val:0xfd55; valaddr_reg:x2; val_offset:32073*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32073*FLEN/8, x3, x1, x4) + +inst_10726: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7c00; +op3val:0x3c00; valaddr_reg:x2; val_offset:32076*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32076*FLEN/8, x3, x1, x4) + +inst_10727: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7c00; +op3val:0xbc00; valaddr_reg:x2; val_offset:32079*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32079*FLEN/8, x3, x1, x4) + +inst_10728: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfc00; +op3val:0x0; valaddr_reg:x2; val_offset:32082*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32082*FLEN/8, x3, x1, x4) + +inst_10729: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfc00; +op3val:0x8000; valaddr_reg:x2; val_offset:32085*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32085*FLEN/8, x3, x1, x4) + +inst_10730: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfc00; +op3val:0x1; valaddr_reg:x2; val_offset:32088*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32088*FLEN/8, x3, x1, x4) + +inst_10731: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfc00; +op3val:0x8001; valaddr_reg:x2; val_offset:32091*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32091*FLEN/8, x3, x1, x4) + +inst_10732: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfc00; +op3val:0x2; valaddr_reg:x2; val_offset:32094*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32094*FLEN/8, x3, x1, x4) + +inst_10733: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfc00; +op3val:0x83fe; valaddr_reg:x2; val_offset:32097*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32097*FLEN/8, x3, x1, x4) + +inst_10734: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfc00; +op3val:0x3ff; valaddr_reg:x2; val_offset:32100*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32100*FLEN/8, x3, x1, x4) + +inst_10735: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfc00; +op3val:0x83ff; valaddr_reg:x2; val_offset:32103*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32103*FLEN/8, x3, x1, x4) + +inst_10736: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfc00; +op3val:0x400; valaddr_reg:x2; val_offset:32106*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32106*FLEN/8, x3, x1, x4) + +inst_10737: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfc00; +op3val:0x8400; valaddr_reg:x2; val_offset:32109*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32109*FLEN/8, x3, x1, x4) + +inst_10738: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfc00; +op3val:0x401; valaddr_reg:x2; val_offset:32112*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32112*FLEN/8, x3, x1, x4) + +inst_10739: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfc00; +op3val:0x8455; valaddr_reg:x2; val_offset:32115*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32115*FLEN/8, x3, x1, x4) + +inst_10740: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfc00; +op3val:0x7bff; valaddr_reg:x2; val_offset:32118*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32118*FLEN/8, x3, x1, x4) + +inst_10741: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfc00; +op3val:0xfbff; valaddr_reg:x2; val_offset:32121*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32121*FLEN/8, x3, x1, x4) + +inst_10742: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfc00; +op3val:0x7c00; valaddr_reg:x2; val_offset:32124*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32124*FLEN/8, x3, x1, x4) + +inst_10743: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfc00; +op3val:0xfc00; valaddr_reg:x2; val_offset:32127*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32127*FLEN/8, x3, x1, x4) + +inst_10744: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfc00; +op3val:0x7e00; valaddr_reg:x2; val_offset:32130*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32130*FLEN/8, x3, x1, x4) + +inst_10745: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfc00; +op3val:0xfe00; valaddr_reg:x2; val_offset:32133*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32133*FLEN/8, x3, x1, x4) + +inst_10746: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfc00; +op3val:0x7e01; valaddr_reg:x2; val_offset:32136*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32136*FLEN/8, x3, x1, x4) + +inst_10747: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfc00; +op3val:0xfe55; valaddr_reg:x2; val_offset:32139*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32139*FLEN/8, x3, x1, x4) + +inst_10748: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfc00; +op3val:0x7c01; valaddr_reg:x2; val_offset:32142*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32142*FLEN/8, x3, x1, x4) + +inst_10749: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfc00; +op3val:0xfd55; valaddr_reg:x2; val_offset:32145*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32145*FLEN/8, x3, x1, x4) + +inst_10750: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfc00; +op3val:0x3c00; valaddr_reg:x2; val_offset:32148*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32148*FLEN/8, x3, x1, x4) + +inst_10751: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfc00; +op3val:0xbc00; valaddr_reg:x2; val_offset:32151*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32151*FLEN/8, x3, x1, x4) + +inst_10752: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7e00; +op3val:0x0; valaddr_reg:x2; val_offset:32154*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32154*FLEN/8, x3, x1, x4) + +inst_10753: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7e00; +op3val:0x8000; valaddr_reg:x2; val_offset:32157*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32157*FLEN/8, x3, x1, x4) + +inst_10754: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7e00; +op3val:0x1; valaddr_reg:x2; val_offset:32160*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32160*FLEN/8, x3, x1, x4) + +inst_10755: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7e00; +op3val:0x8001; valaddr_reg:x2; val_offset:32163*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32163*FLEN/8, x3, x1, x4) + +inst_10756: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7e00; +op3val:0x2; valaddr_reg:x2; val_offset:32166*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32166*FLEN/8, x3, x1, x4) + +inst_10757: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7e00; +op3val:0x83fe; valaddr_reg:x2; val_offset:32169*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32169*FLEN/8, x3, x1, x4) + +inst_10758: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7e00; +op3val:0x3ff; valaddr_reg:x2; val_offset:32172*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32172*FLEN/8, x3, x1, x4) + +inst_10759: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7e00; +op3val:0x83ff; valaddr_reg:x2; val_offset:32175*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32175*FLEN/8, x3, x1, x4) + +inst_10760: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7e00; +op3val:0x400; valaddr_reg:x2; val_offset:32178*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32178*FLEN/8, x3, x1, x4) + +inst_10761: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7e00; +op3val:0x8400; valaddr_reg:x2; val_offset:32181*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32181*FLEN/8, x3, x1, x4) + +inst_10762: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7e00; +op3val:0x401; valaddr_reg:x2; val_offset:32184*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32184*FLEN/8, x3, x1, x4) + +inst_10763: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7e00; +op3val:0x8455; valaddr_reg:x2; val_offset:32187*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32187*FLEN/8, x3, x1, x4) + +inst_10764: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7e00; +op3val:0x7bff; valaddr_reg:x2; val_offset:32190*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32190*FLEN/8, x3, x1, x4) + +inst_10765: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7e00; +op3val:0xfbff; valaddr_reg:x2; val_offset:32193*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32193*FLEN/8, x3, x1, x4) + +inst_10766: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7e00; +op3val:0x7c00; valaddr_reg:x2; val_offset:32196*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32196*FLEN/8, x3, x1, x4) + +inst_10767: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7e00; +op3val:0xfc00; valaddr_reg:x2; val_offset:32199*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32199*FLEN/8, x3, x1, x4) + +inst_10768: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7e00; +op3val:0x7e00; valaddr_reg:x2; val_offset:32202*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32202*FLEN/8, x3, x1, x4) + +inst_10769: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7e00; +op3val:0xfe00; valaddr_reg:x2; val_offset:32205*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32205*FLEN/8, x3, x1, x4) + +inst_10770: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7e00; +op3val:0x7e01; valaddr_reg:x2; val_offset:32208*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32208*FLEN/8, x3, x1, x4) + +inst_10771: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7e00; +op3val:0xfe55; valaddr_reg:x2; val_offset:32211*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32211*FLEN/8, x3, x1, x4) + +inst_10772: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7e00; +op3val:0x7c01; valaddr_reg:x2; val_offset:32214*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32214*FLEN/8, x3, x1, x4) + +inst_10773: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7e00; +op3val:0xfd55; valaddr_reg:x2; val_offset:32217*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32217*FLEN/8, x3, x1, x4) + +inst_10774: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7e00; +op3val:0x3c00; valaddr_reg:x2; val_offset:32220*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32220*FLEN/8, x3, x1, x4) + +inst_10775: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7e00; +op3val:0xbc00; valaddr_reg:x2; val_offset:32223*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32223*FLEN/8, x3, x1, x4) + +inst_10776: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfe00; +op3val:0x0; valaddr_reg:x2; val_offset:32226*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32226*FLEN/8, x3, x1, x4) + +inst_10777: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfe00; +op3val:0x8000; valaddr_reg:x2; val_offset:32229*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32229*FLEN/8, x3, x1, x4) + +inst_10778: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfe00; +op3val:0x1; valaddr_reg:x2; val_offset:32232*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32232*FLEN/8, x3, x1, x4) + +inst_10779: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfe00; +op3val:0x8001; valaddr_reg:x2; val_offset:32235*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32235*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_85) + +inst_10780: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfe00; +op3val:0x2; valaddr_reg:x2; val_offset:32238*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32238*FLEN/8, x3, x1, x4) + +inst_10781: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfe00; +op3val:0x83fe; valaddr_reg:x2; val_offset:32241*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32241*FLEN/8, x3, x1, x4) + +inst_10782: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfe00; +op3val:0x3ff; valaddr_reg:x2; val_offset:32244*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32244*FLEN/8, x3, x1, x4) + +inst_10783: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfe00; +op3val:0x83ff; valaddr_reg:x2; val_offset:32247*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32247*FLEN/8, x3, x1, x4) + +inst_10784: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfe00; +op3val:0x400; valaddr_reg:x2; val_offset:32250*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32250*FLEN/8, x3, x1, x4) + +inst_10785: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfe00; +op3val:0x8400; valaddr_reg:x2; val_offset:32253*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32253*FLEN/8, x3, x1, x4) + +inst_10786: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfe00; +op3val:0x401; valaddr_reg:x2; val_offset:32256*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32256*FLEN/8, x3, x1, x4) + +inst_10787: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfe00; +op3val:0x8455; valaddr_reg:x2; val_offset:32259*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32259*FLEN/8, x3, x1, x4) + +inst_10788: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfe00; +op3val:0x7bff; valaddr_reg:x2; val_offset:32262*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32262*FLEN/8, x3, x1, x4) + +inst_10789: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfe00; +op3val:0xfbff; valaddr_reg:x2; val_offset:32265*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32265*FLEN/8, x3, x1, x4) + +inst_10790: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfe00; +op3val:0x7c00; valaddr_reg:x2; val_offset:32268*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32268*FLEN/8, x3, x1, x4) + +inst_10791: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfe00; +op3val:0xfc00; valaddr_reg:x2; val_offset:32271*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32271*FLEN/8, x3, x1, x4) + +inst_10792: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfe00; +op3val:0x7e00; valaddr_reg:x2; val_offset:32274*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32274*FLEN/8, x3, x1, x4) + +inst_10793: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfe00; +op3val:0xfe00; valaddr_reg:x2; val_offset:32277*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32277*FLEN/8, x3, x1, x4) + +inst_10794: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfe00; +op3val:0x7e01; valaddr_reg:x2; val_offset:32280*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32280*FLEN/8, x3, x1, x4) + +inst_10795: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfe00; +op3val:0xfe55; valaddr_reg:x2; val_offset:32283*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32283*FLEN/8, x3, x1, x4) + +inst_10796: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfe00; +op3val:0x7c01; valaddr_reg:x2; val_offset:32286*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32286*FLEN/8, x3, x1, x4) + +inst_10797: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfe00; +op3val:0xfd55; valaddr_reg:x2; val_offset:32289*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32289*FLEN/8, x3, x1, x4) + +inst_10798: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfe00; +op3val:0x3c00; valaddr_reg:x2; val_offset:32292*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32292*FLEN/8, x3, x1, x4) + +inst_10799: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfe00; +op3val:0xbc00; valaddr_reg:x2; val_offset:32295*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32295*FLEN/8, x3, x1, x4) + +inst_10800: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7e01; +op3val:0x0; valaddr_reg:x2; val_offset:32298*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32298*FLEN/8, x3, x1, x4) + +inst_10801: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7e01; +op3val:0x8000; valaddr_reg:x2; val_offset:32301*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32301*FLEN/8, x3, x1, x4) + +inst_10802: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7e01; +op3val:0x1; valaddr_reg:x2; val_offset:32304*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32304*FLEN/8, x3, x1, x4) + +inst_10803: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7e01; +op3val:0x8001; valaddr_reg:x2; val_offset:32307*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32307*FLEN/8, x3, x1, x4) + +inst_10804: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7e01; +op3val:0x2; valaddr_reg:x2; val_offset:32310*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32310*FLEN/8, x3, x1, x4) + +inst_10805: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7e01; +op3val:0x83fe; valaddr_reg:x2; val_offset:32313*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32313*FLEN/8, x3, x1, x4) + +inst_10806: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7e01; +op3val:0x3ff; valaddr_reg:x2; val_offset:32316*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32316*FLEN/8, x3, x1, x4) + +inst_10807: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7e01; +op3val:0x83ff; valaddr_reg:x2; val_offset:32319*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32319*FLEN/8, x3, x1, x4) + +inst_10808: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7e01; +op3val:0x400; valaddr_reg:x2; val_offset:32322*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32322*FLEN/8, x3, x1, x4) + +inst_10809: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7e01; +op3val:0x8400; valaddr_reg:x2; val_offset:32325*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32325*FLEN/8, x3, x1, x4) + +inst_10810: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7e01; +op3val:0x401; valaddr_reg:x2; val_offset:32328*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32328*FLEN/8, x3, x1, x4) + +inst_10811: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7e01; +op3val:0x8455; valaddr_reg:x2; val_offset:32331*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32331*FLEN/8, x3, x1, x4) + +inst_10812: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7e01; +op3val:0x7bff; valaddr_reg:x2; val_offset:32334*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32334*FLEN/8, x3, x1, x4) + +inst_10813: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7e01; +op3val:0xfbff; valaddr_reg:x2; val_offset:32337*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32337*FLEN/8, x3, x1, x4) + +inst_10814: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7e01; +op3val:0x7c00; valaddr_reg:x2; val_offset:32340*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32340*FLEN/8, x3, x1, x4) + +inst_10815: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7e01; +op3val:0xfc00; valaddr_reg:x2; val_offset:32343*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32343*FLEN/8, x3, x1, x4) + +inst_10816: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7e01; +op3val:0x7e00; valaddr_reg:x2; val_offset:32346*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32346*FLEN/8, x3, x1, x4) + +inst_10817: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7e01; +op3val:0xfe00; valaddr_reg:x2; val_offset:32349*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32349*FLEN/8, x3, x1, x4) + +inst_10818: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7e01; +op3val:0x7e01; valaddr_reg:x2; val_offset:32352*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32352*FLEN/8, x3, x1, x4) + +inst_10819: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7e01; +op3val:0xfe55; valaddr_reg:x2; val_offset:32355*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32355*FLEN/8, x3, x1, x4) + +inst_10820: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7e01; +op3val:0x7c01; valaddr_reg:x2; val_offset:32358*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32358*FLEN/8, x3, x1, x4) + +inst_10821: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7e01; +op3val:0xfd55; valaddr_reg:x2; val_offset:32361*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32361*FLEN/8, x3, x1, x4) + +inst_10822: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7e01; +op3val:0x3c00; valaddr_reg:x2; val_offset:32364*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32364*FLEN/8, x3, x1, x4) + +inst_10823: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7e01; +op3val:0xbc00; valaddr_reg:x2; val_offset:32367*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32367*FLEN/8, x3, x1, x4) + +inst_10824: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfe55; +op3val:0x0; valaddr_reg:x2; val_offset:32370*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32370*FLEN/8, x3, x1, x4) + +inst_10825: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfe55; +op3val:0x8000; valaddr_reg:x2; val_offset:32373*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32373*FLEN/8, x3, x1, x4) + +inst_10826: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfe55; +op3val:0x1; valaddr_reg:x2; val_offset:32376*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32376*FLEN/8, x3, x1, x4) + +inst_10827: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfe55; +op3val:0x8001; valaddr_reg:x2; val_offset:32379*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32379*FLEN/8, x3, x1, x4) + +inst_10828: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfe55; +op3val:0x2; valaddr_reg:x2; val_offset:32382*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32382*FLEN/8, x3, x1, x4) + +inst_10829: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfe55; +op3val:0x83fe; valaddr_reg:x2; val_offset:32385*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32385*FLEN/8, x3, x1, x4) + +inst_10830: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfe55; +op3val:0x3ff; valaddr_reg:x2; val_offset:32388*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32388*FLEN/8, x3, x1, x4) + +inst_10831: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfe55; +op3val:0x83ff; valaddr_reg:x2; val_offset:32391*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32391*FLEN/8, x3, x1, x4) + +inst_10832: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfe55; +op3val:0x400; valaddr_reg:x2; val_offset:32394*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32394*FLEN/8, x3, x1, x4) + +inst_10833: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfe55; +op3val:0x8400; valaddr_reg:x2; val_offset:32397*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32397*FLEN/8, x3, x1, x4) + +inst_10834: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfe55; +op3val:0x401; valaddr_reg:x2; val_offset:32400*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32400*FLEN/8, x3, x1, x4) + +inst_10835: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfe55; +op3val:0x8455; valaddr_reg:x2; val_offset:32403*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32403*FLEN/8, x3, x1, x4) + +inst_10836: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfe55; +op3val:0x7bff; valaddr_reg:x2; val_offset:32406*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32406*FLEN/8, x3, x1, x4) + +inst_10837: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfe55; +op3val:0xfbff; valaddr_reg:x2; val_offset:32409*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32409*FLEN/8, x3, x1, x4) + +inst_10838: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfe55; +op3val:0x7c00; valaddr_reg:x2; val_offset:32412*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32412*FLEN/8, x3, x1, x4) + +inst_10839: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfe55; +op3val:0xfc00; valaddr_reg:x2; val_offset:32415*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32415*FLEN/8, x3, x1, x4) + +inst_10840: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfe55; +op3val:0x7e00; valaddr_reg:x2; val_offset:32418*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32418*FLEN/8, x3, x1, x4) + +inst_10841: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfe55; +op3val:0xfe00; valaddr_reg:x2; val_offset:32421*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32421*FLEN/8, x3, x1, x4) + +inst_10842: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfe55; +op3val:0x7e01; valaddr_reg:x2; val_offset:32424*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32424*FLEN/8, x3, x1, x4) + +inst_10843: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfe55; +op3val:0xfe55; valaddr_reg:x2; val_offset:32427*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32427*FLEN/8, x3, x1, x4) + +inst_10844: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfe55; +op3val:0x7c01; valaddr_reg:x2; val_offset:32430*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32430*FLEN/8, x3, x1, x4) + +inst_10845: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfe55; +op3val:0xfd55; valaddr_reg:x2; val_offset:32433*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32433*FLEN/8, x3, x1, x4) + +inst_10846: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfe55; +op3val:0x3c00; valaddr_reg:x2; val_offset:32436*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32436*FLEN/8, x3, x1, x4) + +inst_10847: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfe55; +op3val:0xbc00; valaddr_reg:x2; val_offset:32439*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32439*FLEN/8, x3, x1, x4) + +inst_10848: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7c01; +op3val:0x0; valaddr_reg:x2; val_offset:32442*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32442*FLEN/8, x3, x1, x4) + +inst_10849: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7c01; +op3val:0x8000; valaddr_reg:x2; val_offset:32445*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32445*FLEN/8, x3, x1, x4) + +inst_10850: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7c01; +op3val:0x1; valaddr_reg:x2; val_offset:32448*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32448*FLEN/8, x3, x1, x4) + +inst_10851: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7c01; +op3val:0x8001; valaddr_reg:x2; val_offset:32451*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32451*FLEN/8, x3, x1, x4) + +inst_10852: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7c01; +op3val:0x2; valaddr_reg:x2; val_offset:32454*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32454*FLEN/8, x3, x1, x4) + +inst_10853: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7c01; +op3val:0x83fe; valaddr_reg:x2; val_offset:32457*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32457*FLEN/8, x3, x1, x4) + +inst_10854: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7c01; +op3val:0x3ff; valaddr_reg:x2; val_offset:32460*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32460*FLEN/8, x3, x1, x4) + +inst_10855: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7c01; +op3val:0x83ff; valaddr_reg:x2; val_offset:32463*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32463*FLEN/8, x3, x1, x4) + +inst_10856: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7c01; +op3val:0x400; valaddr_reg:x2; val_offset:32466*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32466*FLEN/8, x3, x1, x4) + +inst_10857: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7c01; +op3val:0x8400; valaddr_reg:x2; val_offset:32469*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32469*FLEN/8, x3, x1, x4) + +inst_10858: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7c01; +op3val:0x401; valaddr_reg:x2; val_offset:32472*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32472*FLEN/8, x3, x1, x4) + +inst_10859: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7c01; +op3val:0x8455; valaddr_reg:x2; val_offset:32475*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32475*FLEN/8, x3, x1, x4) + +inst_10860: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7c01; +op3val:0x7bff; valaddr_reg:x2; val_offset:32478*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32478*FLEN/8, x3, x1, x4) + +inst_10861: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7c01; +op3val:0xfbff; valaddr_reg:x2; val_offset:32481*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32481*FLEN/8, x3, x1, x4) + +inst_10862: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7c01; +op3val:0x7c00; valaddr_reg:x2; val_offset:32484*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32484*FLEN/8, x3, x1, x4) + +inst_10863: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7c01; +op3val:0xfc00; valaddr_reg:x2; val_offset:32487*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32487*FLEN/8, x3, x1, x4) + +inst_10864: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7c01; +op3val:0x7e00; valaddr_reg:x2; val_offset:32490*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32490*FLEN/8, x3, x1, x4) + +inst_10865: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7c01; +op3val:0xfe00; valaddr_reg:x2; val_offset:32493*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32493*FLEN/8, x3, x1, x4) + +inst_10866: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7c01; +op3val:0x7e01; valaddr_reg:x2; val_offset:32496*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32496*FLEN/8, x3, x1, x4) + +inst_10867: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7c01; +op3val:0xfe55; valaddr_reg:x2; val_offset:32499*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32499*FLEN/8, x3, x1, x4) + +inst_10868: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7c01; +op3val:0x7c01; valaddr_reg:x2; val_offset:32502*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32502*FLEN/8, x3, x1, x4) + +inst_10869: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7c01; +op3val:0xfd55; valaddr_reg:x2; val_offset:32505*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32505*FLEN/8, x3, x1, x4) + +inst_10870: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7c01; +op3val:0x3c00; valaddr_reg:x2; val_offset:32508*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32508*FLEN/8, x3, x1, x4) + +inst_10871: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x7c01; +op3val:0xbc00; valaddr_reg:x2; val_offset:32511*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32511*FLEN/8, x3, x1, x4) + +inst_10872: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfd55; +op3val:0x0; valaddr_reg:x2; val_offset:32514*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32514*FLEN/8, x3, x1, x4) + +inst_10873: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfd55; +op3val:0x8000; valaddr_reg:x2; val_offset:32517*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32517*FLEN/8, x3, x1, x4) + +inst_10874: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfd55; +op3val:0x1; valaddr_reg:x2; val_offset:32520*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32520*FLEN/8, x3, x1, x4) + +inst_10875: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfd55; +op3val:0x8001; valaddr_reg:x2; val_offset:32523*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32523*FLEN/8, x3, x1, x4) + +inst_10876: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfd55; +op3val:0x2; valaddr_reg:x2; val_offset:32526*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32526*FLEN/8, x3, x1, x4) + +inst_10877: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfd55; +op3val:0x83fe; valaddr_reg:x2; val_offset:32529*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32529*FLEN/8, x3, x1, x4) + +inst_10878: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfd55; +op3val:0x3ff; valaddr_reg:x2; val_offset:32532*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32532*FLEN/8, x3, x1, x4) + +inst_10879: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfd55; +op3val:0x83ff; valaddr_reg:x2; val_offset:32535*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32535*FLEN/8, x3, x1, x4) + +inst_10880: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfd55; +op3val:0x400; valaddr_reg:x2; val_offset:32538*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32538*FLEN/8, x3, x1, x4) + +inst_10881: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfd55; +op3val:0x8400; valaddr_reg:x2; val_offset:32541*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32541*FLEN/8, x3, x1, x4) + +inst_10882: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfd55; +op3val:0x401; valaddr_reg:x2; val_offset:32544*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32544*FLEN/8, x3, x1, x4) + +inst_10883: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfd55; +op3val:0x8455; valaddr_reg:x2; val_offset:32547*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32547*FLEN/8, x3, x1, x4) + +inst_10884: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfd55; +op3val:0x7bff; valaddr_reg:x2; val_offset:32550*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32550*FLEN/8, x3, x1, x4) + +inst_10885: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfd55; +op3val:0xfbff; valaddr_reg:x2; val_offset:32553*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32553*FLEN/8, x3, x1, x4) + +inst_10886: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfd55; +op3val:0x7c00; valaddr_reg:x2; val_offset:32556*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32556*FLEN/8, x3, x1, x4) + +inst_10887: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfd55; +op3val:0xfc00; valaddr_reg:x2; val_offset:32559*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32559*FLEN/8, x3, x1, x4) + +inst_10888: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfd55; +op3val:0x7e00; valaddr_reg:x2; val_offset:32562*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32562*FLEN/8, x3, x1, x4) + +inst_10889: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfd55; +op3val:0xfe00; valaddr_reg:x2; val_offset:32565*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32565*FLEN/8, x3, x1, x4) + +inst_10890: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfd55; +op3val:0x7e01; valaddr_reg:x2; val_offset:32568*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32568*FLEN/8, x3, x1, x4) + +inst_10891: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfd55; +op3val:0xfe55; valaddr_reg:x2; val_offset:32571*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32571*FLEN/8, x3, x1, x4) + +inst_10892: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfd55; +op3val:0x7c01; valaddr_reg:x2; val_offset:32574*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32574*FLEN/8, x3, x1, x4) + +inst_10893: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfd55; +op3val:0xfd55; valaddr_reg:x2; val_offset:32577*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32577*FLEN/8, x3, x1, x4) + +inst_10894: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfd55; +op3val:0x3c00; valaddr_reg:x2; val_offset:32580*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32580*FLEN/8, x3, x1, x4) + +inst_10895: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xfd55; +op3val:0xbc00; valaddr_reg:x2; val_offset:32583*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32583*FLEN/8, x3, x1, x4) + +inst_10896: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x3c00; +op3val:0x0; valaddr_reg:x2; val_offset:32586*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32586*FLEN/8, x3, x1, x4) + +inst_10897: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x3c00; +op3val:0x8000; valaddr_reg:x2; val_offset:32589*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32589*FLEN/8, x3, x1, x4) + +inst_10898: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x3c00; +op3val:0x1; valaddr_reg:x2; val_offset:32592*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32592*FLEN/8, x3, x1, x4) + +inst_10899: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x3c00; +op3val:0x8001; valaddr_reg:x2; val_offset:32595*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32595*FLEN/8, x3, x1, x4) + +inst_10900: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x3c00; +op3val:0x2; valaddr_reg:x2; val_offset:32598*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32598*FLEN/8, x3, x1, x4) + +inst_10901: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x3c00; +op3val:0x83fe; valaddr_reg:x2; val_offset:32601*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32601*FLEN/8, x3, x1, x4) + +inst_10902: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x3c00; +op3val:0x3ff; valaddr_reg:x2; val_offset:32604*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32604*FLEN/8, x3, x1, x4) + +inst_10903: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x3c00; +op3val:0x83ff; valaddr_reg:x2; val_offset:32607*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32607*FLEN/8, x3, x1, x4) + +inst_10904: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x3c00; +op3val:0x400; valaddr_reg:x2; val_offset:32610*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32610*FLEN/8, x3, x1, x4) + +inst_10905: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x3c00; +op3val:0x8400; valaddr_reg:x2; val_offset:32613*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32613*FLEN/8, x3, x1, x4) + +inst_10906: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x3c00; +op3val:0x401; valaddr_reg:x2; val_offset:32616*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32616*FLEN/8, x3, x1, x4) + +inst_10907: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x3c00; +op3val:0x8455; valaddr_reg:x2; val_offset:32619*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32619*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_86) + +inst_10908: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x3c00; +op3val:0x7bff; valaddr_reg:x2; val_offset:32622*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32622*FLEN/8, x3, x1, x4) + +inst_10909: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x3c00; +op3val:0xfbff; valaddr_reg:x2; val_offset:32625*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32625*FLEN/8, x3, x1, x4) + +inst_10910: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x3c00; +op3val:0x7c00; valaddr_reg:x2; val_offset:32628*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32628*FLEN/8, x3, x1, x4) + +inst_10911: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x3c00; +op3val:0xfc00; valaddr_reg:x2; val_offset:32631*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32631*FLEN/8, x3, x1, x4) + +inst_10912: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x3c00; +op3val:0x7e00; valaddr_reg:x2; val_offset:32634*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32634*FLEN/8, x3, x1, x4) + +inst_10913: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x3c00; +op3val:0xfe00; valaddr_reg:x2; val_offset:32637*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32637*FLEN/8, x3, x1, x4) + +inst_10914: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x3c00; +op3val:0x7e01; valaddr_reg:x2; val_offset:32640*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32640*FLEN/8, x3, x1, x4) + +inst_10915: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x3c00; +op3val:0xfe55; valaddr_reg:x2; val_offset:32643*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32643*FLEN/8, x3, x1, x4) + +inst_10916: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x3c00; +op3val:0x7c01; valaddr_reg:x2; val_offset:32646*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32646*FLEN/8, x3, x1, x4) + +inst_10917: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x3c00; +op3val:0xfd55; valaddr_reg:x2; val_offset:32649*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32649*FLEN/8, x3, x1, x4) + +inst_10918: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x3c00; +op3val:0x3c00; valaddr_reg:x2; val_offset:32652*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32652*FLEN/8, x3, x1, x4) + +inst_10919: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0x3c00; +op3val:0xbc00; valaddr_reg:x2; val_offset:32655*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32655*FLEN/8, x3, x1, x4) + +inst_10920: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xbc00; +op3val:0x0; valaddr_reg:x2; val_offset:32658*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32658*FLEN/8, x3, x1, x4) + +inst_10921: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xbc00; +op3val:0x8000; valaddr_reg:x2; val_offset:32661*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32661*FLEN/8, x3, x1, x4) + +inst_10922: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xbc00; +op3val:0x1; valaddr_reg:x2; val_offset:32664*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32664*FLEN/8, x3, x1, x4) + +inst_10923: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xbc00; +op3val:0x8001; valaddr_reg:x2; val_offset:32667*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32667*FLEN/8, x3, x1, x4) + +inst_10924: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xbc00; +op3val:0x2; valaddr_reg:x2; val_offset:32670*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32670*FLEN/8, x3, x1, x4) + +inst_10925: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xbc00; +op3val:0x83fe; valaddr_reg:x2; val_offset:32673*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32673*FLEN/8, x3, x1, x4) + +inst_10926: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xbc00; +op3val:0x3ff; valaddr_reg:x2; val_offset:32676*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32676*FLEN/8, x3, x1, x4) + +inst_10927: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xbc00; +op3val:0x83ff; valaddr_reg:x2; val_offset:32679*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32679*FLEN/8, x3, x1, x4) + +inst_10928: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xbc00; +op3val:0x400; valaddr_reg:x2; val_offset:32682*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32682*FLEN/8, x3, x1, x4) + +inst_10929: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xbc00; +op3val:0x8400; valaddr_reg:x2; val_offset:32685*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32685*FLEN/8, x3, x1, x4) + +inst_10930: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xbc00; +op3val:0x401; valaddr_reg:x2; val_offset:32688*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32688*FLEN/8, x3, x1, x4) + +inst_10931: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xbc00; +op3val:0x8455; valaddr_reg:x2; val_offset:32691*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32691*FLEN/8, x3, x1, x4) + +inst_10932: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xbc00; +op3val:0x7bff; valaddr_reg:x2; val_offset:32694*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32694*FLEN/8, x3, x1, x4) + +inst_10933: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xbc00; +op3val:0xfbff; valaddr_reg:x2; val_offset:32697*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32697*FLEN/8, x3, x1, x4) + +inst_10934: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xbc00; +op3val:0x7c00; valaddr_reg:x2; val_offset:32700*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32700*FLEN/8, x3, x1, x4) + +inst_10935: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xbc00; +op3val:0xfc00; valaddr_reg:x2; val_offset:32703*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32703*FLEN/8, x3, x1, x4) + +inst_10936: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xbc00; +op3val:0x7e00; valaddr_reg:x2; val_offset:32706*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32706*FLEN/8, x3, x1, x4) + +inst_10937: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xbc00; +op3val:0xfe00; valaddr_reg:x2; val_offset:32709*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32709*FLEN/8, x3, x1, x4) + +inst_10938: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xbc00; +op3val:0x7e01; valaddr_reg:x2; val_offset:32712*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32712*FLEN/8, x3, x1, x4) + +inst_10939: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xbc00; +op3val:0xfe55; valaddr_reg:x2; val_offset:32715*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32715*FLEN/8, x3, x1, x4) + +inst_10940: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xbc00; +op3val:0x7c01; valaddr_reg:x2; val_offset:32718*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32718*FLEN/8, x3, x1, x4) + +inst_10941: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xbc00; +op3val:0xfd55; valaddr_reg:x2; val_offset:32721*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32721*FLEN/8, x3, x1, x4) + +inst_10942: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xbc00; +op3val:0x3c00; valaddr_reg:x2; val_offset:32724*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32724*FLEN/8, x3, x1, x4) + +inst_10943: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e01; op2val:0xbc00; +op3val:0xbc00; valaddr_reg:x2; val_offset:32727*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32727*FLEN/8, x3, x1, x4) + +inst_10944: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x0; +op3val:0x0; valaddr_reg:x2; val_offset:32730*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32730*FLEN/8, x3, x1, x4) + +inst_10945: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x0; +op3val:0x8000; valaddr_reg:x2; val_offset:32733*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32733*FLEN/8, x3, x1, x4) + +inst_10946: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x0; +op3val:0x1; valaddr_reg:x2; val_offset:32736*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32736*FLEN/8, x3, x1, x4) + +inst_10947: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x0; +op3val:0x8001; valaddr_reg:x2; val_offset:32739*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32739*FLEN/8, x3, x1, x4) + +inst_10948: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x0; +op3val:0x2; valaddr_reg:x2; val_offset:32742*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32742*FLEN/8, x3, x1, x4) + +inst_10949: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x0; +op3val:0x83fe; valaddr_reg:x2; val_offset:32745*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32745*FLEN/8, x3, x1, x4) + +inst_10950: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x0; +op3val:0x3ff; valaddr_reg:x2; val_offset:32748*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32748*FLEN/8, x3, x1, x4) + +inst_10951: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x0; +op3val:0x83ff; valaddr_reg:x2; val_offset:32751*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32751*FLEN/8, x3, x1, x4) + +inst_10952: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x0; +op3val:0x400; valaddr_reg:x2; val_offset:32754*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32754*FLEN/8, x3, x1, x4) + +inst_10953: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x0; +op3val:0x8400; valaddr_reg:x2; val_offset:32757*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32757*FLEN/8, x3, x1, x4) + +inst_10954: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x0; +op3val:0x401; valaddr_reg:x2; val_offset:32760*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32760*FLEN/8, x3, x1, x4) + +inst_10955: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x0; +op3val:0x8455; valaddr_reg:x2; val_offset:32763*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32763*FLEN/8, x3, x1, x4) + +inst_10956: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x0; +op3val:0x7bff; valaddr_reg:x2; val_offset:32766*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32766*FLEN/8, x3, x1, x4) + +inst_10957: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x0; +op3val:0xfbff; valaddr_reg:x2; val_offset:32769*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32769*FLEN/8, x3, x1, x4) + +inst_10958: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x0; +op3val:0x7c00; valaddr_reg:x2; val_offset:32772*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32772*FLEN/8, x3, x1, x4) + +inst_10959: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x0; +op3val:0xfc00; valaddr_reg:x2; val_offset:32775*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32775*FLEN/8, x3, x1, x4) + +inst_10960: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x0; +op3val:0x7e00; valaddr_reg:x2; val_offset:32778*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32778*FLEN/8, x3, x1, x4) + +inst_10961: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x0; +op3val:0xfe00; valaddr_reg:x2; val_offset:32781*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32781*FLEN/8, x3, x1, x4) + +inst_10962: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x0; +op3val:0x7e01; valaddr_reg:x2; val_offset:32784*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32784*FLEN/8, x3, x1, x4) + +inst_10963: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x0; +op3val:0xfe55; valaddr_reg:x2; val_offset:32787*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32787*FLEN/8, x3, x1, x4) + +inst_10964: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x0; +op3val:0x7c01; valaddr_reg:x2; val_offset:32790*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32790*FLEN/8, x3, x1, x4) + +inst_10965: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x0; +op3val:0xfd55; valaddr_reg:x2; val_offset:32793*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32793*FLEN/8, x3, x1, x4) + +inst_10966: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x0; +op3val:0x3c00; valaddr_reg:x2; val_offset:32796*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32796*FLEN/8, x3, x1, x4) + +inst_10967: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x0; +op3val:0xbc00; valaddr_reg:x2; val_offset:32799*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32799*FLEN/8, x3, x1, x4) + +inst_10968: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8000; +op3val:0x0; valaddr_reg:x2; val_offset:32802*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32802*FLEN/8, x3, x1, x4) + +inst_10969: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8000; +op3val:0x8000; valaddr_reg:x2; val_offset:32805*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32805*FLEN/8, x3, x1, x4) + +inst_10970: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8000; +op3val:0x1; valaddr_reg:x2; val_offset:32808*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32808*FLEN/8, x3, x1, x4) + +inst_10971: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8000; +op3val:0x8001; valaddr_reg:x2; val_offset:32811*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32811*FLEN/8, x3, x1, x4) + +inst_10972: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8000; +op3val:0x2; valaddr_reg:x2; val_offset:32814*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32814*FLEN/8, x3, x1, x4) + +inst_10973: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8000; +op3val:0x83fe; valaddr_reg:x2; val_offset:32817*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32817*FLEN/8, x3, x1, x4) + +inst_10974: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8000; +op3val:0x3ff; valaddr_reg:x2; val_offset:32820*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32820*FLEN/8, x3, x1, x4) + +inst_10975: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8000; +op3val:0x83ff; valaddr_reg:x2; val_offset:32823*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32823*FLEN/8, x3, x1, x4) + +inst_10976: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8000; +op3val:0x400; valaddr_reg:x2; val_offset:32826*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32826*FLEN/8, x3, x1, x4) + +inst_10977: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8000; +op3val:0x8400; valaddr_reg:x2; val_offset:32829*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32829*FLEN/8, x3, x1, x4) + +inst_10978: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8000; +op3val:0x401; valaddr_reg:x2; val_offset:32832*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32832*FLEN/8, x3, x1, x4) + +inst_10979: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8000; +op3val:0x8455; valaddr_reg:x2; val_offset:32835*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32835*FLEN/8, x3, x1, x4) + +inst_10980: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x2; val_offset:32838*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32838*FLEN/8, x3, x1, x4) + +inst_10981: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x2; val_offset:32841*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32841*FLEN/8, x3, x1, x4) + +inst_10982: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8000; +op3val:0x7c00; valaddr_reg:x2; val_offset:32844*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32844*FLEN/8, x3, x1, x4) + +inst_10983: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8000; +op3val:0xfc00; valaddr_reg:x2; val_offset:32847*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32847*FLEN/8, x3, x1, x4) + +inst_10984: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8000; +op3val:0x7e00; valaddr_reg:x2; val_offset:32850*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32850*FLEN/8, x3, x1, x4) + +inst_10985: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8000; +op3val:0xfe00; valaddr_reg:x2; val_offset:32853*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32853*FLEN/8, x3, x1, x4) + +inst_10986: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8000; +op3val:0x7e01; valaddr_reg:x2; val_offset:32856*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32856*FLEN/8, x3, x1, x4) + +inst_10987: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8000; +op3val:0xfe55; valaddr_reg:x2; val_offset:32859*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32859*FLEN/8, x3, x1, x4) + +inst_10988: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8000; +op3val:0x7c01; valaddr_reg:x2; val_offset:32862*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32862*FLEN/8, x3, x1, x4) + +inst_10989: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8000; +op3val:0xfd55; valaddr_reg:x2; val_offset:32865*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32865*FLEN/8, x3, x1, x4) + +inst_10990: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8000; +op3val:0x3c00; valaddr_reg:x2; val_offset:32868*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32868*FLEN/8, x3, x1, x4) + +inst_10991: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8000; +op3val:0xbc00; valaddr_reg:x2; val_offset:32871*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32871*FLEN/8, x3, x1, x4) + +inst_10992: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x1; +op3val:0x0; valaddr_reg:x2; val_offset:32874*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32874*FLEN/8, x3, x1, x4) + +inst_10993: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x1; +op3val:0x8000; valaddr_reg:x2; val_offset:32877*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32877*FLEN/8, x3, x1, x4) + +inst_10994: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x1; +op3val:0x1; valaddr_reg:x2; val_offset:32880*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32880*FLEN/8, x3, x1, x4) + +inst_10995: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x1; +op3val:0x8001; valaddr_reg:x2; val_offset:32883*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32883*FLEN/8, x3, x1, x4) + +inst_10996: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x1; +op3val:0x2; valaddr_reg:x2; val_offset:32886*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32886*FLEN/8, x3, x1, x4) + +inst_10997: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x1; +op3val:0x83fe; valaddr_reg:x2; val_offset:32889*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32889*FLEN/8, x3, x1, x4) + +inst_10998: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x1; +op3val:0x3ff; valaddr_reg:x2; val_offset:32892*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32892*FLEN/8, x3, x1, x4) + +inst_10999: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x1; +op3val:0x83ff; valaddr_reg:x2; val_offset:32895*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32895*FLEN/8, x3, x1, x4) + +inst_11000: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x1; +op3val:0x400; valaddr_reg:x2; val_offset:32898*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32898*FLEN/8, x3, x1, x4) + +inst_11001: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x1; +op3val:0x8400; valaddr_reg:x2; val_offset:32901*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32901*FLEN/8, x3, x1, x4) + +inst_11002: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x1; +op3val:0x401; valaddr_reg:x2; val_offset:32904*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32904*FLEN/8, x3, x1, x4) + +inst_11003: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x1; +op3val:0x8455; valaddr_reg:x2; val_offset:32907*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32907*FLEN/8, x3, x1, x4) + +inst_11004: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x1; +op3val:0x7bff; valaddr_reg:x2; val_offset:32910*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32910*FLEN/8, x3, x1, x4) + +inst_11005: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x1; +op3val:0xfbff; valaddr_reg:x2; val_offset:32913*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32913*FLEN/8, x3, x1, x4) + +inst_11006: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x1; +op3val:0x7c00; valaddr_reg:x2; val_offset:32916*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32916*FLEN/8, x3, x1, x4) + +inst_11007: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x1; +op3val:0xfc00; valaddr_reg:x2; val_offset:32919*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32919*FLEN/8, x3, x1, x4) + +inst_11008: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x1; +op3val:0x7e00; valaddr_reg:x2; val_offset:32922*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32922*FLEN/8, x3, x1, x4) + +inst_11009: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x1; +op3val:0xfe00; valaddr_reg:x2; val_offset:32925*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32925*FLEN/8, x3, x1, x4) + +inst_11010: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x1; +op3val:0x7e01; valaddr_reg:x2; val_offset:32928*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32928*FLEN/8, x3, x1, x4) + +inst_11011: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x1; +op3val:0xfe55; valaddr_reg:x2; val_offset:32931*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32931*FLEN/8, x3, x1, x4) + +inst_11012: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x1; +op3val:0x7c01; valaddr_reg:x2; val_offset:32934*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32934*FLEN/8, x3, x1, x4) + +inst_11013: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x1; +op3val:0xfd55; valaddr_reg:x2; val_offset:32937*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32937*FLEN/8, x3, x1, x4) + +inst_11014: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x1; +op3val:0x3c00; valaddr_reg:x2; val_offset:32940*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32940*FLEN/8, x3, x1, x4) + +inst_11015: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x1; +op3val:0xbc00; valaddr_reg:x2; val_offset:32943*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32943*FLEN/8, x3, x1, x4) + +inst_11016: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8001; +op3val:0x0; valaddr_reg:x2; val_offset:32946*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32946*FLEN/8, x3, x1, x4) + +inst_11017: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8001; +op3val:0x8000; valaddr_reg:x2; val_offset:32949*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32949*FLEN/8, x3, x1, x4) + +inst_11018: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8001; +op3val:0x1; valaddr_reg:x2; val_offset:32952*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32952*FLEN/8, x3, x1, x4) + +inst_11019: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8001; +op3val:0x8001; valaddr_reg:x2; val_offset:32955*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32955*FLEN/8, x3, x1, x4) + +inst_11020: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8001; +op3val:0x2; valaddr_reg:x2; val_offset:32958*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32958*FLEN/8, x3, x1, x4) + +inst_11021: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8001; +op3val:0x83fe; valaddr_reg:x2; val_offset:32961*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32961*FLEN/8, x3, x1, x4) + +inst_11022: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8001; +op3val:0x3ff; valaddr_reg:x2; val_offset:32964*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32964*FLEN/8, x3, x1, x4) + +inst_11023: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8001; +op3val:0x83ff; valaddr_reg:x2; val_offset:32967*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32967*FLEN/8, x3, x1, x4) + +inst_11024: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8001; +op3val:0x400; valaddr_reg:x2; val_offset:32970*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32970*FLEN/8, x3, x1, x4) + +inst_11025: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8001; +op3val:0x8400; valaddr_reg:x2; val_offset:32973*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32973*FLEN/8, x3, x1, x4) + +inst_11026: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8001; +op3val:0x401; valaddr_reg:x2; val_offset:32976*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32976*FLEN/8, x3, x1, x4) + +inst_11027: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8001; +op3val:0x8455; valaddr_reg:x2; val_offset:32979*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32979*FLEN/8, x3, x1, x4) + +inst_11028: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8001; +op3val:0x7bff; valaddr_reg:x2; val_offset:32982*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32982*FLEN/8, x3, x1, x4) + +inst_11029: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8001; +op3val:0xfbff; valaddr_reg:x2; val_offset:32985*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32985*FLEN/8, x3, x1, x4) + +inst_11030: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8001; +op3val:0x7c00; valaddr_reg:x2; val_offset:32988*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32988*FLEN/8, x3, x1, x4) + +inst_11031: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8001; +op3val:0xfc00; valaddr_reg:x2; val_offset:32991*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32991*FLEN/8, x3, x1, x4) + +inst_11032: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8001; +op3val:0x7e00; valaddr_reg:x2; val_offset:32994*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32994*FLEN/8, x3, x1, x4) + +inst_11033: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8001; +op3val:0xfe00; valaddr_reg:x2; val_offset:32997*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 32997*FLEN/8, x3, x1, x4) + +inst_11034: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8001; +op3val:0x7e01; valaddr_reg:x2; val_offset:33000*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33000*FLEN/8, x3, x1, x4) + +inst_11035: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8001; +op3val:0xfe55; valaddr_reg:x2; val_offset:33003*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33003*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_87) + +inst_11036: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8001; +op3val:0x7c01; valaddr_reg:x2; val_offset:33006*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33006*FLEN/8, x3, x1, x4) + +inst_11037: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8001; +op3val:0xfd55; valaddr_reg:x2; val_offset:33009*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33009*FLEN/8, x3, x1, x4) + +inst_11038: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8001; +op3val:0x3c00; valaddr_reg:x2; val_offset:33012*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33012*FLEN/8, x3, x1, x4) + +inst_11039: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8001; +op3val:0xbc00; valaddr_reg:x2; val_offset:33015*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33015*FLEN/8, x3, x1, x4) + +inst_11040: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x2; +op3val:0x0; valaddr_reg:x2; val_offset:33018*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33018*FLEN/8, x3, x1, x4) + +inst_11041: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x2; +op3val:0x8000; valaddr_reg:x2; val_offset:33021*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33021*FLEN/8, x3, x1, x4) + +inst_11042: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x2; +op3val:0x1; valaddr_reg:x2; val_offset:33024*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33024*FLEN/8, x3, x1, x4) + +inst_11043: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x2; +op3val:0x8001; valaddr_reg:x2; val_offset:33027*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33027*FLEN/8, x3, x1, x4) + +inst_11044: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x2; +op3val:0x2; valaddr_reg:x2; val_offset:33030*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33030*FLEN/8, x3, x1, x4) + +inst_11045: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x2; +op3val:0x83fe; valaddr_reg:x2; val_offset:33033*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33033*FLEN/8, x3, x1, x4) + +inst_11046: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x2; +op3val:0x3ff; valaddr_reg:x2; val_offset:33036*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33036*FLEN/8, x3, x1, x4) + +inst_11047: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x2; +op3val:0x83ff; valaddr_reg:x2; val_offset:33039*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33039*FLEN/8, x3, x1, x4) + +inst_11048: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x2; +op3val:0x400; valaddr_reg:x2; val_offset:33042*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33042*FLEN/8, x3, x1, x4) + +inst_11049: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x2; +op3val:0x8400; valaddr_reg:x2; val_offset:33045*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33045*FLEN/8, x3, x1, x4) + +inst_11050: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x2; +op3val:0x401; valaddr_reg:x2; val_offset:33048*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33048*FLEN/8, x3, x1, x4) + +inst_11051: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x2; +op3val:0x8455; valaddr_reg:x2; val_offset:33051*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33051*FLEN/8, x3, x1, x4) + +inst_11052: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x2; +op3val:0x7bff; valaddr_reg:x2; val_offset:33054*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33054*FLEN/8, x3, x1, x4) + +inst_11053: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x2; +op3val:0xfbff; valaddr_reg:x2; val_offset:33057*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33057*FLEN/8, x3, x1, x4) + +inst_11054: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x2; +op3val:0x7c00; valaddr_reg:x2; val_offset:33060*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33060*FLEN/8, x3, x1, x4) + +inst_11055: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x2; +op3val:0xfc00; valaddr_reg:x2; val_offset:33063*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33063*FLEN/8, x3, x1, x4) + +inst_11056: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x2; +op3val:0x7e00; valaddr_reg:x2; val_offset:33066*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33066*FLEN/8, x3, x1, x4) + +inst_11057: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x2; +op3val:0xfe00; valaddr_reg:x2; val_offset:33069*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33069*FLEN/8, x3, x1, x4) + +inst_11058: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x2; +op3val:0x7e01; valaddr_reg:x2; val_offset:33072*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33072*FLEN/8, x3, x1, x4) + +inst_11059: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x2; +op3val:0xfe55; valaddr_reg:x2; val_offset:33075*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33075*FLEN/8, x3, x1, x4) + +inst_11060: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x2; +op3val:0x7c01; valaddr_reg:x2; val_offset:33078*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33078*FLEN/8, x3, x1, x4) + +inst_11061: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x2; +op3val:0xfd55; valaddr_reg:x2; val_offset:33081*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33081*FLEN/8, x3, x1, x4) + +inst_11062: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x2; +op3val:0x3c00; valaddr_reg:x2; val_offset:33084*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33084*FLEN/8, x3, x1, x4) + +inst_11063: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x2; +op3val:0xbc00; valaddr_reg:x2; val_offset:33087*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33087*FLEN/8, x3, x1, x4) + +inst_11064: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x83fe; +op3val:0x0; valaddr_reg:x2; val_offset:33090*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33090*FLEN/8, x3, x1, x4) + +inst_11065: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x83fe; +op3val:0x8000; valaddr_reg:x2; val_offset:33093*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33093*FLEN/8, x3, x1, x4) + +inst_11066: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x83fe; +op3val:0x1; valaddr_reg:x2; val_offset:33096*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33096*FLEN/8, x3, x1, x4) + +inst_11067: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x83fe; +op3val:0x8001; valaddr_reg:x2; val_offset:33099*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33099*FLEN/8, x3, x1, x4) + +inst_11068: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x83fe; +op3val:0x2; valaddr_reg:x2; val_offset:33102*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33102*FLEN/8, x3, x1, x4) + +inst_11069: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x83fe; +op3val:0x83fe; valaddr_reg:x2; val_offset:33105*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33105*FLEN/8, x3, x1, x4) + +inst_11070: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x83fe; +op3val:0x3ff; valaddr_reg:x2; val_offset:33108*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33108*FLEN/8, x3, x1, x4) + +inst_11071: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x83fe; +op3val:0x83ff; valaddr_reg:x2; val_offset:33111*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33111*FLEN/8, x3, x1, x4) + +inst_11072: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x83fe; +op3val:0x400; valaddr_reg:x2; val_offset:33114*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33114*FLEN/8, x3, x1, x4) + +inst_11073: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x83fe; +op3val:0x8400; valaddr_reg:x2; val_offset:33117*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33117*FLEN/8, x3, x1, x4) + +inst_11074: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x83fe; +op3val:0x401; valaddr_reg:x2; val_offset:33120*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33120*FLEN/8, x3, x1, x4) + +inst_11075: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x83fe; +op3val:0x8455; valaddr_reg:x2; val_offset:33123*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33123*FLEN/8, x3, x1, x4) + +inst_11076: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x83fe; +op3val:0x7bff; valaddr_reg:x2; val_offset:33126*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33126*FLEN/8, x3, x1, x4) + +inst_11077: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x83fe; +op3val:0xfbff; valaddr_reg:x2; val_offset:33129*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33129*FLEN/8, x3, x1, x4) + +inst_11078: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x83fe; +op3val:0x7c00; valaddr_reg:x2; val_offset:33132*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33132*FLEN/8, x3, x1, x4) + +inst_11079: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x83fe; +op3val:0xfc00; valaddr_reg:x2; val_offset:33135*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33135*FLEN/8, x3, x1, x4) + +inst_11080: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x83fe; +op3val:0x7e00; valaddr_reg:x2; val_offset:33138*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33138*FLEN/8, x3, x1, x4) + +inst_11081: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x83fe; +op3val:0xfe00; valaddr_reg:x2; val_offset:33141*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33141*FLEN/8, x3, x1, x4) + +inst_11082: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x83fe; +op3val:0x7e01; valaddr_reg:x2; val_offset:33144*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33144*FLEN/8, x3, x1, x4) + +inst_11083: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x83fe; +op3val:0xfe55; valaddr_reg:x2; val_offset:33147*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33147*FLEN/8, x3, x1, x4) + +inst_11084: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x83fe; +op3val:0x7c01; valaddr_reg:x2; val_offset:33150*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33150*FLEN/8, x3, x1, x4) + +inst_11085: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x83fe; +op3val:0xfd55; valaddr_reg:x2; val_offset:33153*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33153*FLEN/8, x3, x1, x4) + +inst_11086: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x83fe; +op3val:0x3c00; valaddr_reg:x2; val_offset:33156*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33156*FLEN/8, x3, x1, x4) + +inst_11087: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x83fe; +op3val:0xbc00; valaddr_reg:x2; val_offset:33159*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33159*FLEN/8, x3, x1, x4) + +inst_11088: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x3ff; +op3val:0x0; valaddr_reg:x2; val_offset:33162*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33162*FLEN/8, x3, x1, x4) + +inst_11089: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x3ff; +op3val:0x8000; valaddr_reg:x2; val_offset:33165*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33165*FLEN/8, x3, x1, x4) + +inst_11090: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x3ff; +op3val:0x1; valaddr_reg:x2; val_offset:33168*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33168*FLEN/8, x3, x1, x4) + +inst_11091: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x3ff; +op3val:0x8001; valaddr_reg:x2; val_offset:33171*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33171*FLEN/8, x3, x1, x4) + +inst_11092: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x3ff; +op3val:0x2; valaddr_reg:x2; val_offset:33174*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33174*FLEN/8, x3, x1, x4) + +inst_11093: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x3ff; +op3val:0x83fe; valaddr_reg:x2; val_offset:33177*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33177*FLEN/8, x3, x1, x4) + +inst_11094: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x3ff; +op3val:0x3ff; valaddr_reg:x2; val_offset:33180*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33180*FLEN/8, x3, x1, x4) + +inst_11095: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x3ff; +op3val:0x83ff; valaddr_reg:x2; val_offset:33183*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33183*FLEN/8, x3, x1, x4) + +inst_11096: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x3ff; +op3val:0x400; valaddr_reg:x2; val_offset:33186*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33186*FLEN/8, x3, x1, x4) + +inst_11097: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x3ff; +op3val:0x8400; valaddr_reg:x2; val_offset:33189*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33189*FLEN/8, x3, x1, x4) + +inst_11098: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x3ff; +op3val:0x401; valaddr_reg:x2; val_offset:33192*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33192*FLEN/8, x3, x1, x4) + +inst_11099: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x3ff; +op3val:0x8455; valaddr_reg:x2; val_offset:33195*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33195*FLEN/8, x3, x1, x4) + +inst_11100: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x3ff; +op3val:0x7bff; valaddr_reg:x2; val_offset:33198*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33198*FLEN/8, x3, x1, x4) + +inst_11101: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x3ff; +op3val:0xfbff; valaddr_reg:x2; val_offset:33201*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33201*FLEN/8, x3, x1, x4) + +inst_11102: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x3ff; +op3val:0x7c00; valaddr_reg:x2; val_offset:33204*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33204*FLEN/8, x3, x1, x4) + +inst_11103: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x3ff; +op3val:0xfc00; valaddr_reg:x2; val_offset:33207*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33207*FLEN/8, x3, x1, x4) + +inst_11104: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x3ff; +op3val:0x7e00; valaddr_reg:x2; val_offset:33210*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33210*FLEN/8, x3, x1, x4) + +inst_11105: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x3ff; +op3val:0xfe00; valaddr_reg:x2; val_offset:33213*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33213*FLEN/8, x3, x1, x4) + +inst_11106: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x3ff; +op3val:0x7e01; valaddr_reg:x2; val_offset:33216*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33216*FLEN/8, x3, x1, x4) + +inst_11107: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x3ff; +op3val:0xfe55; valaddr_reg:x2; val_offset:33219*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33219*FLEN/8, x3, x1, x4) + +inst_11108: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x3ff; +op3val:0x7c01; valaddr_reg:x2; val_offset:33222*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33222*FLEN/8, x3, x1, x4) + +inst_11109: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x3ff; +op3val:0xfd55; valaddr_reg:x2; val_offset:33225*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33225*FLEN/8, x3, x1, x4) + +inst_11110: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x3ff; +op3val:0x3c00; valaddr_reg:x2; val_offset:33228*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33228*FLEN/8, x3, x1, x4) + +inst_11111: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x3ff; +op3val:0xbc00; valaddr_reg:x2; val_offset:33231*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33231*FLEN/8, x3, x1, x4) + +inst_11112: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x83ff; +op3val:0x0; valaddr_reg:x2; val_offset:33234*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33234*FLEN/8, x3, x1, x4) + +inst_11113: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x83ff; +op3val:0x8000; valaddr_reg:x2; val_offset:33237*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33237*FLEN/8, x3, x1, x4) + +inst_11114: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x83ff; +op3val:0x1; valaddr_reg:x2; val_offset:33240*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33240*FLEN/8, x3, x1, x4) + +inst_11115: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x83ff; +op3val:0x8001; valaddr_reg:x2; val_offset:33243*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33243*FLEN/8, x3, x1, x4) + +inst_11116: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x83ff; +op3val:0x2; valaddr_reg:x2; val_offset:33246*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33246*FLEN/8, x3, x1, x4) + +inst_11117: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x83ff; +op3val:0x83fe; valaddr_reg:x2; val_offset:33249*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33249*FLEN/8, x3, x1, x4) + +inst_11118: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x83ff; +op3val:0x3ff; valaddr_reg:x2; val_offset:33252*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33252*FLEN/8, x3, x1, x4) + +inst_11119: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x83ff; +op3val:0x83ff; valaddr_reg:x2; val_offset:33255*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33255*FLEN/8, x3, x1, x4) + +inst_11120: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x83ff; +op3val:0x400; valaddr_reg:x2; val_offset:33258*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33258*FLEN/8, x3, x1, x4) + +inst_11121: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x83ff; +op3val:0x8400; valaddr_reg:x2; val_offset:33261*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33261*FLEN/8, x3, x1, x4) + +inst_11122: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x83ff; +op3val:0x401; valaddr_reg:x2; val_offset:33264*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33264*FLEN/8, x3, x1, x4) + +inst_11123: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x83ff; +op3val:0x8455; valaddr_reg:x2; val_offset:33267*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33267*FLEN/8, x3, x1, x4) + +inst_11124: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x83ff; +op3val:0x7bff; valaddr_reg:x2; val_offset:33270*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33270*FLEN/8, x3, x1, x4) + +inst_11125: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x83ff; +op3val:0xfbff; valaddr_reg:x2; val_offset:33273*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33273*FLEN/8, x3, x1, x4) + +inst_11126: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x83ff; +op3val:0x7c00; valaddr_reg:x2; val_offset:33276*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33276*FLEN/8, x3, x1, x4) + +inst_11127: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x83ff; +op3val:0xfc00; valaddr_reg:x2; val_offset:33279*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33279*FLEN/8, x3, x1, x4) + +inst_11128: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x83ff; +op3val:0x7e00; valaddr_reg:x2; val_offset:33282*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33282*FLEN/8, x3, x1, x4) + +inst_11129: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x83ff; +op3val:0xfe00; valaddr_reg:x2; val_offset:33285*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33285*FLEN/8, x3, x1, x4) + +inst_11130: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x83ff; +op3val:0x7e01; valaddr_reg:x2; val_offset:33288*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33288*FLEN/8, x3, x1, x4) + +inst_11131: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x83ff; +op3val:0xfe55; valaddr_reg:x2; val_offset:33291*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33291*FLEN/8, x3, x1, x4) + +inst_11132: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x83ff; +op3val:0x7c01; valaddr_reg:x2; val_offset:33294*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33294*FLEN/8, x3, x1, x4) + +inst_11133: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x83ff; +op3val:0xfd55; valaddr_reg:x2; val_offset:33297*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33297*FLEN/8, x3, x1, x4) + +inst_11134: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x83ff; +op3val:0x3c00; valaddr_reg:x2; val_offset:33300*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33300*FLEN/8, x3, x1, x4) + +inst_11135: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x83ff; +op3val:0xbc00; valaddr_reg:x2; val_offset:33303*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33303*FLEN/8, x3, x1, x4) + +inst_11136: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x400; +op3val:0x0; valaddr_reg:x2; val_offset:33306*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33306*FLEN/8, x3, x1, x4) + +inst_11137: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x400; +op3val:0x8000; valaddr_reg:x2; val_offset:33309*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33309*FLEN/8, x3, x1, x4) + +inst_11138: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x400; +op3val:0x1; valaddr_reg:x2; val_offset:33312*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33312*FLEN/8, x3, x1, x4) + +inst_11139: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x400; +op3val:0x8001; valaddr_reg:x2; val_offset:33315*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33315*FLEN/8, x3, x1, x4) + +inst_11140: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x400; +op3val:0x2; valaddr_reg:x2; val_offset:33318*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33318*FLEN/8, x3, x1, x4) + +inst_11141: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x400; +op3val:0x83fe; valaddr_reg:x2; val_offset:33321*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33321*FLEN/8, x3, x1, x4) + +inst_11142: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x400; +op3val:0x3ff; valaddr_reg:x2; val_offset:33324*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33324*FLEN/8, x3, x1, x4) + +inst_11143: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x400; +op3val:0x83ff; valaddr_reg:x2; val_offset:33327*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33327*FLEN/8, x3, x1, x4) + +inst_11144: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x400; +op3val:0x400; valaddr_reg:x2; val_offset:33330*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33330*FLEN/8, x3, x1, x4) + +inst_11145: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x400; +op3val:0x8400; valaddr_reg:x2; val_offset:33333*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33333*FLEN/8, x3, x1, x4) + +inst_11146: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x400; +op3val:0x401; valaddr_reg:x2; val_offset:33336*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33336*FLEN/8, x3, x1, x4) + +inst_11147: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x400; +op3val:0x8455; valaddr_reg:x2; val_offset:33339*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33339*FLEN/8, x3, x1, x4) + +inst_11148: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x400; +op3val:0x7bff; valaddr_reg:x2; val_offset:33342*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33342*FLEN/8, x3, x1, x4) + +inst_11149: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x400; +op3val:0xfbff; valaddr_reg:x2; val_offset:33345*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33345*FLEN/8, x3, x1, x4) + +inst_11150: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x400; +op3val:0x7c00; valaddr_reg:x2; val_offset:33348*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33348*FLEN/8, x3, x1, x4) + +inst_11151: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x400; +op3val:0xfc00; valaddr_reg:x2; val_offset:33351*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33351*FLEN/8, x3, x1, x4) + +inst_11152: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x400; +op3val:0x7e00; valaddr_reg:x2; val_offset:33354*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33354*FLEN/8, x3, x1, x4) + +inst_11153: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x400; +op3val:0xfe00; valaddr_reg:x2; val_offset:33357*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33357*FLEN/8, x3, x1, x4) + +inst_11154: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x400; +op3val:0x7e01; valaddr_reg:x2; val_offset:33360*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33360*FLEN/8, x3, x1, x4) + +inst_11155: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x400; +op3val:0xfe55; valaddr_reg:x2; val_offset:33363*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33363*FLEN/8, x3, x1, x4) + +inst_11156: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x400; +op3val:0x7c01; valaddr_reg:x2; val_offset:33366*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33366*FLEN/8, x3, x1, x4) + +inst_11157: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x400; +op3val:0xfd55; valaddr_reg:x2; val_offset:33369*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33369*FLEN/8, x3, x1, x4) + +inst_11158: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x400; +op3val:0x3c00; valaddr_reg:x2; val_offset:33372*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33372*FLEN/8, x3, x1, x4) + +inst_11159: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x400; +op3val:0xbc00; valaddr_reg:x2; val_offset:33375*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33375*FLEN/8, x3, x1, x4) + +inst_11160: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8400; +op3val:0x0; valaddr_reg:x2; val_offset:33378*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33378*FLEN/8, x3, x1, x4) + +inst_11161: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8400; +op3val:0x8000; valaddr_reg:x2; val_offset:33381*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33381*FLEN/8, x3, x1, x4) + +inst_11162: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8400; +op3val:0x1; valaddr_reg:x2; val_offset:33384*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33384*FLEN/8, x3, x1, x4) + +inst_11163: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8400; +op3val:0x8001; valaddr_reg:x2; val_offset:33387*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33387*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_88) + +inst_11164: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8400; +op3val:0x2; valaddr_reg:x2; val_offset:33390*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33390*FLEN/8, x3, x1, x4) + +inst_11165: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8400; +op3val:0x83fe; valaddr_reg:x2; val_offset:33393*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33393*FLEN/8, x3, x1, x4) + +inst_11166: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8400; +op3val:0x3ff; valaddr_reg:x2; val_offset:33396*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33396*FLEN/8, x3, x1, x4) + +inst_11167: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8400; +op3val:0x83ff; valaddr_reg:x2; val_offset:33399*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33399*FLEN/8, x3, x1, x4) + +inst_11168: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8400; +op3val:0x400; valaddr_reg:x2; val_offset:33402*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33402*FLEN/8, x3, x1, x4) + +inst_11169: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8400; +op3val:0x8400; valaddr_reg:x2; val_offset:33405*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33405*FLEN/8, x3, x1, x4) + +inst_11170: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8400; +op3val:0x401; valaddr_reg:x2; val_offset:33408*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33408*FLEN/8, x3, x1, x4) + +inst_11171: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8400; +op3val:0x8455; valaddr_reg:x2; val_offset:33411*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33411*FLEN/8, x3, x1, x4) + +inst_11172: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8400; +op3val:0x7bff; valaddr_reg:x2; val_offset:33414*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33414*FLEN/8, x3, x1, x4) + +inst_11173: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8400; +op3val:0xfbff; valaddr_reg:x2; val_offset:33417*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33417*FLEN/8, x3, x1, x4) + +inst_11174: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8400; +op3val:0x7c00; valaddr_reg:x2; val_offset:33420*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33420*FLEN/8, x3, x1, x4) + +inst_11175: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8400; +op3val:0xfc00; valaddr_reg:x2; val_offset:33423*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33423*FLEN/8, x3, x1, x4) + +inst_11176: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8400; +op3val:0x7e00; valaddr_reg:x2; val_offset:33426*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33426*FLEN/8, x3, x1, x4) + +inst_11177: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8400; +op3val:0xfe00; valaddr_reg:x2; val_offset:33429*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33429*FLEN/8, x3, x1, x4) + +inst_11178: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8400; +op3val:0x7e01; valaddr_reg:x2; val_offset:33432*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33432*FLEN/8, x3, x1, x4) + +inst_11179: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8400; +op3val:0xfe55; valaddr_reg:x2; val_offset:33435*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33435*FLEN/8, x3, x1, x4) + +inst_11180: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8400; +op3val:0x7c01; valaddr_reg:x2; val_offset:33438*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33438*FLEN/8, x3, x1, x4) + +inst_11181: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8400; +op3val:0xfd55; valaddr_reg:x2; val_offset:33441*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33441*FLEN/8, x3, x1, x4) + +inst_11182: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8400; +op3val:0x3c00; valaddr_reg:x2; val_offset:33444*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33444*FLEN/8, x3, x1, x4) + +inst_11183: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8400; +op3val:0xbc00; valaddr_reg:x2; val_offset:33447*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33447*FLEN/8, x3, x1, x4) + +inst_11184: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x401; +op3val:0x0; valaddr_reg:x2; val_offset:33450*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33450*FLEN/8, x3, x1, x4) + +inst_11185: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x401; +op3val:0x8000; valaddr_reg:x2; val_offset:33453*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33453*FLEN/8, x3, x1, x4) + +inst_11186: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x401; +op3val:0x1; valaddr_reg:x2; val_offset:33456*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33456*FLEN/8, x3, x1, x4) + +inst_11187: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x401; +op3val:0x8001; valaddr_reg:x2; val_offset:33459*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33459*FLEN/8, x3, x1, x4) + +inst_11188: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x401; +op3val:0x2; valaddr_reg:x2; val_offset:33462*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33462*FLEN/8, x3, x1, x4) + +inst_11189: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x401; +op3val:0x83fe; valaddr_reg:x2; val_offset:33465*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33465*FLEN/8, x3, x1, x4) + +inst_11190: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x401; +op3val:0x3ff; valaddr_reg:x2; val_offset:33468*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33468*FLEN/8, x3, x1, x4) + +inst_11191: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x401; +op3val:0x83ff; valaddr_reg:x2; val_offset:33471*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33471*FLEN/8, x3, x1, x4) + +inst_11192: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x401; +op3val:0x400; valaddr_reg:x2; val_offset:33474*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33474*FLEN/8, x3, x1, x4) + +inst_11193: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x401; +op3val:0x8400; valaddr_reg:x2; val_offset:33477*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33477*FLEN/8, x3, x1, x4) + +inst_11194: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x401; +op3val:0x401; valaddr_reg:x2; val_offset:33480*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33480*FLEN/8, x3, x1, x4) + +inst_11195: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x401; +op3val:0x8455; valaddr_reg:x2; val_offset:33483*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33483*FLEN/8, x3, x1, x4) + +inst_11196: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x401; +op3val:0x7bff; valaddr_reg:x2; val_offset:33486*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33486*FLEN/8, x3, x1, x4) + +inst_11197: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x401; +op3val:0xfbff; valaddr_reg:x2; val_offset:33489*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33489*FLEN/8, x3, x1, x4) + +inst_11198: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x401; +op3val:0x7c00; valaddr_reg:x2; val_offset:33492*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33492*FLEN/8, x3, x1, x4) + +inst_11199: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x401; +op3val:0xfc00; valaddr_reg:x2; val_offset:33495*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33495*FLEN/8, x3, x1, x4) + +inst_11200: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x401; +op3val:0x7e00; valaddr_reg:x2; val_offset:33498*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33498*FLEN/8, x3, x1, x4) + +inst_11201: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x401; +op3val:0xfe00; valaddr_reg:x2; val_offset:33501*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33501*FLEN/8, x3, x1, x4) + +inst_11202: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x401; +op3val:0x7e01; valaddr_reg:x2; val_offset:33504*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33504*FLEN/8, x3, x1, x4) + +inst_11203: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x401; +op3val:0xfe55; valaddr_reg:x2; val_offset:33507*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33507*FLEN/8, x3, x1, x4) + +inst_11204: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x401; +op3val:0x7c01; valaddr_reg:x2; val_offset:33510*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33510*FLEN/8, x3, x1, x4) + +inst_11205: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x401; +op3val:0xfd55; valaddr_reg:x2; val_offset:33513*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33513*FLEN/8, x3, x1, x4) + +inst_11206: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x401; +op3val:0x3c00; valaddr_reg:x2; val_offset:33516*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33516*FLEN/8, x3, x1, x4) + +inst_11207: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x401; +op3val:0xbc00; valaddr_reg:x2; val_offset:33519*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33519*FLEN/8, x3, x1, x4) + +inst_11208: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8455; +op3val:0x0; valaddr_reg:x2; val_offset:33522*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33522*FLEN/8, x3, x1, x4) + +inst_11209: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8455; +op3val:0x8000; valaddr_reg:x2; val_offset:33525*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33525*FLEN/8, x3, x1, x4) + +inst_11210: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8455; +op3val:0x1; valaddr_reg:x2; val_offset:33528*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33528*FLEN/8, x3, x1, x4) + +inst_11211: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8455; +op3val:0x8001; valaddr_reg:x2; val_offset:33531*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33531*FLEN/8, x3, x1, x4) + +inst_11212: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8455; +op3val:0x2; valaddr_reg:x2; val_offset:33534*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33534*FLEN/8, x3, x1, x4) + +inst_11213: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8455; +op3val:0x83fe; valaddr_reg:x2; val_offset:33537*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33537*FLEN/8, x3, x1, x4) + +inst_11214: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8455; +op3val:0x3ff; valaddr_reg:x2; val_offset:33540*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33540*FLEN/8, x3, x1, x4) + +inst_11215: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8455; +op3val:0x83ff; valaddr_reg:x2; val_offset:33543*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33543*FLEN/8, x3, x1, x4) + +inst_11216: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8455; +op3val:0x400; valaddr_reg:x2; val_offset:33546*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33546*FLEN/8, x3, x1, x4) + +inst_11217: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8455; +op3val:0x8400; valaddr_reg:x2; val_offset:33549*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33549*FLEN/8, x3, x1, x4) + +inst_11218: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8455; +op3val:0x401; valaddr_reg:x2; val_offset:33552*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33552*FLEN/8, x3, x1, x4) + +inst_11219: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8455; +op3val:0x8455; valaddr_reg:x2; val_offset:33555*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33555*FLEN/8, x3, x1, x4) + +inst_11220: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8455; +op3val:0x7bff; valaddr_reg:x2; val_offset:33558*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33558*FLEN/8, x3, x1, x4) + +inst_11221: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8455; +op3val:0xfbff; valaddr_reg:x2; val_offset:33561*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33561*FLEN/8, x3, x1, x4) + +inst_11222: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8455; +op3val:0x7c00; valaddr_reg:x2; val_offset:33564*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33564*FLEN/8, x3, x1, x4) + +inst_11223: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8455; +op3val:0xfc00; valaddr_reg:x2; val_offset:33567*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33567*FLEN/8, x3, x1, x4) + +inst_11224: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8455; +op3val:0x7e00; valaddr_reg:x2; val_offset:33570*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33570*FLEN/8, x3, x1, x4) + +inst_11225: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8455; +op3val:0xfe00; valaddr_reg:x2; val_offset:33573*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33573*FLEN/8, x3, x1, x4) + +inst_11226: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8455; +op3val:0x7e01; valaddr_reg:x2; val_offset:33576*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33576*FLEN/8, x3, x1, x4) + +inst_11227: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8455; +op3val:0xfe55; valaddr_reg:x2; val_offset:33579*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33579*FLEN/8, x3, x1, x4) + +inst_11228: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8455; +op3val:0x7c01; valaddr_reg:x2; val_offset:33582*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33582*FLEN/8, x3, x1, x4) + +inst_11229: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8455; +op3val:0xfd55; valaddr_reg:x2; val_offset:33585*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33585*FLEN/8, x3, x1, x4) + +inst_11230: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8455; +op3val:0x3c00; valaddr_reg:x2; val_offset:33588*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33588*FLEN/8, x3, x1, x4) + +inst_11231: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x8455; +op3val:0xbc00; valaddr_reg:x2; val_offset:33591*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33591*FLEN/8, x3, x1, x4) + +inst_11232: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7bff; +op3val:0x0; valaddr_reg:x2; val_offset:33594*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33594*FLEN/8, x3, x1, x4) + +inst_11233: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7bff; +op3val:0x8000; valaddr_reg:x2; val_offset:33597*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33597*FLEN/8, x3, x1, x4) + +inst_11234: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7bff; +op3val:0x1; valaddr_reg:x2; val_offset:33600*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33600*FLEN/8, x3, x1, x4) + +inst_11235: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7bff; +op3val:0x8001; valaddr_reg:x2; val_offset:33603*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33603*FLEN/8, x3, x1, x4) + +inst_11236: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7bff; +op3val:0x2; valaddr_reg:x2; val_offset:33606*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33606*FLEN/8, x3, x1, x4) + +inst_11237: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7bff; +op3val:0x83fe; valaddr_reg:x2; val_offset:33609*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33609*FLEN/8, x3, x1, x4) + +inst_11238: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7bff; +op3val:0x3ff; valaddr_reg:x2; val_offset:33612*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33612*FLEN/8, x3, x1, x4) + +inst_11239: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7bff; +op3val:0x83ff; valaddr_reg:x2; val_offset:33615*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33615*FLEN/8, x3, x1, x4) + +inst_11240: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7bff; +op3val:0x400; valaddr_reg:x2; val_offset:33618*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33618*FLEN/8, x3, x1, x4) + +inst_11241: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7bff; +op3val:0x8400; valaddr_reg:x2; val_offset:33621*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33621*FLEN/8, x3, x1, x4) + +inst_11242: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7bff; +op3val:0x401; valaddr_reg:x2; val_offset:33624*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33624*FLEN/8, x3, x1, x4) + +inst_11243: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7bff; +op3val:0x8455; valaddr_reg:x2; val_offset:33627*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33627*FLEN/8, x3, x1, x4) + +inst_11244: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7bff; +op3val:0x7bff; valaddr_reg:x2; val_offset:33630*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33630*FLEN/8, x3, x1, x4) + +inst_11245: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7bff; +op3val:0xfbff; valaddr_reg:x2; val_offset:33633*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33633*FLEN/8, x3, x1, x4) + +inst_11246: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7bff; +op3val:0x7c00; valaddr_reg:x2; val_offset:33636*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33636*FLEN/8, x3, x1, x4) + +inst_11247: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7bff; +op3val:0xfc00; valaddr_reg:x2; val_offset:33639*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33639*FLEN/8, x3, x1, x4) + +inst_11248: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7bff; +op3val:0x7e00; valaddr_reg:x2; val_offset:33642*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33642*FLEN/8, x3, x1, x4) + +inst_11249: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7bff; +op3val:0xfe00; valaddr_reg:x2; val_offset:33645*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33645*FLEN/8, x3, x1, x4) + +inst_11250: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7bff; +op3val:0x7e01; valaddr_reg:x2; val_offset:33648*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33648*FLEN/8, x3, x1, x4) + +inst_11251: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7bff; +op3val:0xfe55; valaddr_reg:x2; val_offset:33651*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33651*FLEN/8, x3, x1, x4) + +inst_11252: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7bff; +op3val:0x7c01; valaddr_reg:x2; val_offset:33654*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33654*FLEN/8, x3, x1, x4) + +inst_11253: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7bff; +op3val:0xfd55; valaddr_reg:x2; val_offset:33657*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33657*FLEN/8, x3, x1, x4) + +inst_11254: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7bff; +op3val:0x3c00; valaddr_reg:x2; val_offset:33660*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33660*FLEN/8, x3, x1, x4) + +inst_11255: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7bff; +op3val:0xbc00; valaddr_reg:x2; val_offset:33663*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33663*FLEN/8, x3, x1, x4) + +inst_11256: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfbff; +op3val:0x0; valaddr_reg:x2; val_offset:33666*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33666*FLEN/8, x3, x1, x4) + +inst_11257: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfbff; +op3val:0x8000; valaddr_reg:x2; val_offset:33669*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33669*FLEN/8, x3, x1, x4) + +inst_11258: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfbff; +op3val:0x1; valaddr_reg:x2; val_offset:33672*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33672*FLEN/8, x3, x1, x4) + +inst_11259: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfbff; +op3val:0x8001; valaddr_reg:x2; val_offset:33675*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33675*FLEN/8, x3, x1, x4) + +inst_11260: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfbff; +op3val:0x2; valaddr_reg:x2; val_offset:33678*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33678*FLEN/8, x3, x1, x4) + +inst_11261: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfbff; +op3val:0x83fe; valaddr_reg:x2; val_offset:33681*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33681*FLEN/8, x3, x1, x4) + +inst_11262: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfbff; +op3val:0x3ff; valaddr_reg:x2; val_offset:33684*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33684*FLEN/8, x3, x1, x4) + +inst_11263: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfbff; +op3val:0x83ff; valaddr_reg:x2; val_offset:33687*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33687*FLEN/8, x3, x1, x4) + +inst_11264: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfbff; +op3val:0x400; valaddr_reg:x2; val_offset:33690*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33690*FLEN/8, x3, x1, x4) + +inst_11265: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfbff; +op3val:0x8400; valaddr_reg:x2; val_offset:33693*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33693*FLEN/8, x3, x1, x4) + +inst_11266: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfbff; +op3val:0x401; valaddr_reg:x2; val_offset:33696*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33696*FLEN/8, x3, x1, x4) + +inst_11267: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfbff; +op3val:0x8455; valaddr_reg:x2; val_offset:33699*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33699*FLEN/8, x3, x1, x4) + +inst_11268: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfbff; +op3val:0x7bff; valaddr_reg:x2; val_offset:33702*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33702*FLEN/8, x3, x1, x4) + +inst_11269: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfbff; +op3val:0xfbff; valaddr_reg:x2; val_offset:33705*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33705*FLEN/8, x3, x1, x4) + +inst_11270: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfbff; +op3val:0x7c00; valaddr_reg:x2; val_offset:33708*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33708*FLEN/8, x3, x1, x4) + +inst_11271: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfbff; +op3val:0xfc00; valaddr_reg:x2; val_offset:33711*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33711*FLEN/8, x3, x1, x4) + +inst_11272: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfbff; +op3val:0x7e00; valaddr_reg:x2; val_offset:33714*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33714*FLEN/8, x3, x1, x4) + +inst_11273: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfbff; +op3val:0xfe00; valaddr_reg:x2; val_offset:33717*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33717*FLEN/8, x3, x1, x4) + +inst_11274: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfbff; +op3val:0x7e01; valaddr_reg:x2; val_offset:33720*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33720*FLEN/8, x3, x1, x4) + +inst_11275: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfbff; +op3val:0xfe55; valaddr_reg:x2; val_offset:33723*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33723*FLEN/8, x3, x1, x4) + +inst_11276: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfbff; +op3val:0x7c01; valaddr_reg:x2; val_offset:33726*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33726*FLEN/8, x3, x1, x4) + +inst_11277: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfbff; +op3val:0xfd55; valaddr_reg:x2; val_offset:33729*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33729*FLEN/8, x3, x1, x4) + +inst_11278: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfbff; +op3val:0x3c00; valaddr_reg:x2; val_offset:33732*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33732*FLEN/8, x3, x1, x4) + +inst_11279: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfbff; +op3val:0xbc00; valaddr_reg:x2; val_offset:33735*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33735*FLEN/8, x3, x1, x4) + +inst_11280: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7c00; +op3val:0x0; valaddr_reg:x2; val_offset:33738*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33738*FLEN/8, x3, x1, x4) + +inst_11281: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7c00; +op3val:0x8000; valaddr_reg:x2; val_offset:33741*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33741*FLEN/8, x3, x1, x4) + +inst_11282: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7c00; +op3val:0x1; valaddr_reg:x2; val_offset:33744*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33744*FLEN/8, x3, x1, x4) + +inst_11283: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7c00; +op3val:0x8001; valaddr_reg:x2; val_offset:33747*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33747*FLEN/8, x3, x1, x4) + +inst_11284: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7c00; +op3val:0x2; valaddr_reg:x2; val_offset:33750*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33750*FLEN/8, x3, x1, x4) + +inst_11285: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7c00; +op3val:0x83fe; valaddr_reg:x2; val_offset:33753*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33753*FLEN/8, x3, x1, x4) + +inst_11286: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7c00; +op3val:0x3ff; valaddr_reg:x2; val_offset:33756*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33756*FLEN/8, x3, x1, x4) + +inst_11287: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7c00; +op3val:0x83ff; valaddr_reg:x2; val_offset:33759*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33759*FLEN/8, x3, x1, x4) + +inst_11288: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7c00; +op3val:0x400; valaddr_reg:x2; val_offset:33762*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33762*FLEN/8, x3, x1, x4) + +inst_11289: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7c00; +op3val:0x8400; valaddr_reg:x2; val_offset:33765*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33765*FLEN/8, x3, x1, x4) + +inst_11290: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7c00; +op3val:0x401; valaddr_reg:x2; val_offset:33768*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33768*FLEN/8, x3, x1, x4) + +inst_11291: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7c00; +op3val:0x8455; valaddr_reg:x2; val_offset:33771*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33771*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_89) + +inst_11292: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7c00; +op3val:0x7bff; valaddr_reg:x2; val_offset:33774*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33774*FLEN/8, x3, x1, x4) + +inst_11293: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7c00; +op3val:0xfbff; valaddr_reg:x2; val_offset:33777*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33777*FLEN/8, x3, x1, x4) + +inst_11294: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7c00; +op3val:0x7c00; valaddr_reg:x2; val_offset:33780*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33780*FLEN/8, x3, x1, x4) + +inst_11295: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7c00; +op3val:0xfc00; valaddr_reg:x2; val_offset:33783*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33783*FLEN/8, x3, x1, x4) + +inst_11296: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7c00; +op3val:0x7e00; valaddr_reg:x2; val_offset:33786*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33786*FLEN/8, x3, x1, x4) + +inst_11297: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7c00; +op3val:0xfe00; valaddr_reg:x2; val_offset:33789*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33789*FLEN/8, x3, x1, x4) + +inst_11298: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7c00; +op3val:0x7e01; valaddr_reg:x2; val_offset:33792*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33792*FLEN/8, x3, x1, x4) + +inst_11299: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7c00; +op3val:0xfe55; valaddr_reg:x2; val_offset:33795*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33795*FLEN/8, x3, x1, x4) + +inst_11300: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7c00; +op3val:0x7c01; valaddr_reg:x2; val_offset:33798*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33798*FLEN/8, x3, x1, x4) + +inst_11301: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7c00; +op3val:0xfd55; valaddr_reg:x2; val_offset:33801*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33801*FLEN/8, x3, x1, x4) + +inst_11302: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7c00; +op3val:0x3c00; valaddr_reg:x2; val_offset:33804*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33804*FLEN/8, x3, x1, x4) + +inst_11303: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7c00; +op3val:0xbc00; valaddr_reg:x2; val_offset:33807*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33807*FLEN/8, x3, x1, x4) + +inst_11304: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfc00; +op3val:0x0; valaddr_reg:x2; val_offset:33810*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33810*FLEN/8, x3, x1, x4) + +inst_11305: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfc00; +op3val:0x8000; valaddr_reg:x2; val_offset:33813*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33813*FLEN/8, x3, x1, x4) + +inst_11306: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfc00; +op3val:0x1; valaddr_reg:x2; val_offset:33816*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33816*FLEN/8, x3, x1, x4) + +inst_11307: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfc00; +op3val:0x8001; valaddr_reg:x2; val_offset:33819*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33819*FLEN/8, x3, x1, x4) + +inst_11308: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfc00; +op3val:0x2; valaddr_reg:x2; val_offset:33822*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33822*FLEN/8, x3, x1, x4) + +inst_11309: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfc00; +op3val:0x83fe; valaddr_reg:x2; val_offset:33825*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33825*FLEN/8, x3, x1, x4) + +inst_11310: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfc00; +op3val:0x3ff; valaddr_reg:x2; val_offset:33828*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33828*FLEN/8, x3, x1, x4) + +inst_11311: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfc00; +op3val:0x83ff; valaddr_reg:x2; val_offset:33831*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33831*FLEN/8, x3, x1, x4) + +inst_11312: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfc00; +op3val:0x400; valaddr_reg:x2; val_offset:33834*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33834*FLEN/8, x3, x1, x4) + +inst_11313: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfc00; +op3val:0x8400; valaddr_reg:x2; val_offset:33837*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33837*FLEN/8, x3, x1, x4) + +inst_11314: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfc00; +op3val:0x401; valaddr_reg:x2; val_offset:33840*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33840*FLEN/8, x3, x1, x4) + +inst_11315: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfc00; +op3val:0x8455; valaddr_reg:x2; val_offset:33843*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33843*FLEN/8, x3, x1, x4) + +inst_11316: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfc00; +op3val:0x7bff; valaddr_reg:x2; val_offset:33846*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33846*FLEN/8, x3, x1, x4) + +inst_11317: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfc00; +op3val:0xfbff; valaddr_reg:x2; val_offset:33849*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33849*FLEN/8, x3, x1, x4) + +inst_11318: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfc00; +op3val:0x7c00; valaddr_reg:x2; val_offset:33852*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33852*FLEN/8, x3, x1, x4) + +inst_11319: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfc00; +op3val:0xfc00; valaddr_reg:x2; val_offset:33855*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33855*FLEN/8, x3, x1, x4) + +inst_11320: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfc00; +op3val:0x7e00; valaddr_reg:x2; val_offset:33858*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33858*FLEN/8, x3, x1, x4) + +inst_11321: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfc00; +op3val:0xfe00; valaddr_reg:x2; val_offset:33861*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33861*FLEN/8, x3, x1, x4) + +inst_11322: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfc00; +op3val:0x7e01; valaddr_reg:x2; val_offset:33864*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33864*FLEN/8, x3, x1, x4) + +inst_11323: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfc00; +op3val:0xfe55; valaddr_reg:x2; val_offset:33867*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33867*FLEN/8, x3, x1, x4) + +inst_11324: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfc00; +op3val:0x7c01; valaddr_reg:x2; val_offset:33870*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33870*FLEN/8, x3, x1, x4) + +inst_11325: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfc00; +op3val:0xfd55; valaddr_reg:x2; val_offset:33873*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33873*FLEN/8, x3, x1, x4) + +inst_11326: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfc00; +op3val:0x3c00; valaddr_reg:x2; val_offset:33876*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33876*FLEN/8, x3, x1, x4) + +inst_11327: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfc00; +op3val:0xbc00; valaddr_reg:x2; val_offset:33879*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33879*FLEN/8, x3, x1, x4) + +inst_11328: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7e00; +op3val:0x0; valaddr_reg:x2; val_offset:33882*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33882*FLEN/8, x3, x1, x4) + +inst_11329: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7e00; +op3val:0x8000; valaddr_reg:x2; val_offset:33885*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33885*FLEN/8, x3, x1, x4) + +inst_11330: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7e00; +op3val:0x1; valaddr_reg:x2; val_offset:33888*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33888*FLEN/8, x3, x1, x4) + +inst_11331: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7e00; +op3val:0x8001; valaddr_reg:x2; val_offset:33891*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33891*FLEN/8, x3, x1, x4) + +inst_11332: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7e00; +op3val:0x2; valaddr_reg:x2; val_offset:33894*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33894*FLEN/8, x3, x1, x4) + +inst_11333: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7e00; +op3val:0x83fe; valaddr_reg:x2; val_offset:33897*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33897*FLEN/8, x3, x1, x4) + +inst_11334: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7e00; +op3val:0x3ff; valaddr_reg:x2; val_offset:33900*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33900*FLEN/8, x3, x1, x4) + +inst_11335: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7e00; +op3val:0x83ff; valaddr_reg:x2; val_offset:33903*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33903*FLEN/8, x3, x1, x4) + +inst_11336: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7e00; +op3val:0x400; valaddr_reg:x2; val_offset:33906*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33906*FLEN/8, x3, x1, x4) + +inst_11337: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7e00; +op3val:0x8400; valaddr_reg:x2; val_offset:33909*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33909*FLEN/8, x3, x1, x4) + +inst_11338: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7e00; +op3val:0x401; valaddr_reg:x2; val_offset:33912*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33912*FLEN/8, x3, x1, x4) + +inst_11339: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7e00; +op3val:0x8455; valaddr_reg:x2; val_offset:33915*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33915*FLEN/8, x3, x1, x4) + +inst_11340: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7e00; +op3val:0x7bff; valaddr_reg:x2; val_offset:33918*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33918*FLEN/8, x3, x1, x4) + +inst_11341: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7e00; +op3val:0xfbff; valaddr_reg:x2; val_offset:33921*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33921*FLEN/8, x3, x1, x4) + +inst_11342: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7e00; +op3val:0x7c00; valaddr_reg:x2; val_offset:33924*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33924*FLEN/8, x3, x1, x4) + +inst_11343: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7e00; +op3val:0xfc00; valaddr_reg:x2; val_offset:33927*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33927*FLEN/8, x3, x1, x4) + +inst_11344: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7e00; +op3val:0x7e00; valaddr_reg:x2; val_offset:33930*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33930*FLEN/8, x3, x1, x4) + +inst_11345: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7e00; +op3val:0xfe00; valaddr_reg:x2; val_offset:33933*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33933*FLEN/8, x3, x1, x4) + +inst_11346: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7e00; +op3val:0x7e01; valaddr_reg:x2; val_offset:33936*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33936*FLEN/8, x3, x1, x4) + +inst_11347: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7e00; +op3val:0xfe55; valaddr_reg:x2; val_offset:33939*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33939*FLEN/8, x3, x1, x4) + +inst_11348: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7e00; +op3val:0x7c01; valaddr_reg:x2; val_offset:33942*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33942*FLEN/8, x3, x1, x4) + +inst_11349: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7e00; +op3val:0xfd55; valaddr_reg:x2; val_offset:33945*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33945*FLEN/8, x3, x1, x4) + +inst_11350: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7e00; +op3val:0x3c00; valaddr_reg:x2; val_offset:33948*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33948*FLEN/8, x3, x1, x4) + +inst_11351: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7e00; +op3val:0xbc00; valaddr_reg:x2; val_offset:33951*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33951*FLEN/8, x3, x1, x4) + +inst_11352: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfe00; +op3val:0x0; valaddr_reg:x2; val_offset:33954*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33954*FLEN/8, x3, x1, x4) + +inst_11353: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfe00; +op3val:0x8000; valaddr_reg:x2; val_offset:33957*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33957*FLEN/8, x3, x1, x4) + +inst_11354: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfe00; +op3val:0x1; valaddr_reg:x2; val_offset:33960*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33960*FLEN/8, x3, x1, x4) + +inst_11355: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfe00; +op3val:0x8001; valaddr_reg:x2; val_offset:33963*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33963*FLEN/8, x3, x1, x4) + +inst_11356: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfe00; +op3val:0x2; valaddr_reg:x2; val_offset:33966*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33966*FLEN/8, x3, x1, x4) + +inst_11357: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfe00; +op3val:0x83fe; valaddr_reg:x2; val_offset:33969*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33969*FLEN/8, x3, x1, x4) + +inst_11358: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfe00; +op3val:0x3ff; valaddr_reg:x2; val_offset:33972*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33972*FLEN/8, x3, x1, x4) + +inst_11359: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfe00; +op3val:0x83ff; valaddr_reg:x2; val_offset:33975*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33975*FLEN/8, x3, x1, x4) + +inst_11360: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfe00; +op3val:0x400; valaddr_reg:x2; val_offset:33978*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33978*FLEN/8, x3, x1, x4) + +inst_11361: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfe00; +op3val:0x8400; valaddr_reg:x2; val_offset:33981*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33981*FLEN/8, x3, x1, x4) + +inst_11362: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfe00; +op3val:0x401; valaddr_reg:x2; val_offset:33984*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33984*FLEN/8, x3, x1, x4) + +inst_11363: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfe00; +op3val:0x8455; valaddr_reg:x2; val_offset:33987*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33987*FLEN/8, x3, x1, x4) + +inst_11364: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfe00; +op3val:0x7bff; valaddr_reg:x2; val_offset:33990*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33990*FLEN/8, x3, x1, x4) + +inst_11365: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfe00; +op3val:0xfbff; valaddr_reg:x2; val_offset:33993*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33993*FLEN/8, x3, x1, x4) + +inst_11366: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfe00; +op3val:0x7c00; valaddr_reg:x2; val_offset:33996*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33996*FLEN/8, x3, x1, x4) + +inst_11367: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfe00; +op3val:0xfc00; valaddr_reg:x2; val_offset:33999*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33999*FLEN/8, x3, x1, x4) + +inst_11368: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfe00; +op3val:0x7e00; valaddr_reg:x2; val_offset:34002*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34002*FLEN/8, x3, x1, x4) + +inst_11369: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfe00; +op3val:0xfe00; valaddr_reg:x2; val_offset:34005*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34005*FLEN/8, x3, x1, x4) + +inst_11370: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfe00; +op3val:0x7e01; valaddr_reg:x2; val_offset:34008*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34008*FLEN/8, x3, x1, x4) + +inst_11371: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfe00; +op3val:0xfe55; valaddr_reg:x2; val_offset:34011*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34011*FLEN/8, x3, x1, x4) + +inst_11372: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfe00; +op3val:0x7c01; valaddr_reg:x2; val_offset:34014*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34014*FLEN/8, x3, x1, x4) + +inst_11373: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfe00; +op3val:0xfd55; valaddr_reg:x2; val_offset:34017*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34017*FLEN/8, x3, x1, x4) + +inst_11374: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfe00; +op3val:0x3c00; valaddr_reg:x2; val_offset:34020*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34020*FLEN/8, x3, x1, x4) + +inst_11375: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfe00; +op3val:0xbc00; valaddr_reg:x2; val_offset:34023*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34023*FLEN/8, x3, x1, x4) + +inst_11376: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7e01; +op3val:0x0; valaddr_reg:x2; val_offset:34026*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34026*FLEN/8, x3, x1, x4) + +inst_11377: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7e01; +op3val:0x8000; valaddr_reg:x2; val_offset:34029*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34029*FLEN/8, x3, x1, x4) + +inst_11378: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7e01; +op3val:0x1; valaddr_reg:x2; val_offset:34032*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34032*FLEN/8, x3, x1, x4) + +inst_11379: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7e01; +op3val:0x8001; valaddr_reg:x2; val_offset:34035*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34035*FLEN/8, x3, x1, x4) + +inst_11380: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7e01; +op3val:0x2; valaddr_reg:x2; val_offset:34038*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34038*FLEN/8, x3, x1, x4) + +inst_11381: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7e01; +op3val:0x83fe; valaddr_reg:x2; val_offset:34041*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34041*FLEN/8, x3, x1, x4) + +inst_11382: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7e01; +op3val:0x3ff; valaddr_reg:x2; val_offset:34044*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34044*FLEN/8, x3, x1, x4) + +inst_11383: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7e01; +op3val:0x83ff; valaddr_reg:x2; val_offset:34047*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34047*FLEN/8, x3, x1, x4) + +inst_11384: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7e01; +op3val:0x400; valaddr_reg:x2; val_offset:34050*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34050*FLEN/8, x3, x1, x4) + +inst_11385: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7e01; +op3val:0x8400; valaddr_reg:x2; val_offset:34053*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34053*FLEN/8, x3, x1, x4) + +inst_11386: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7e01; +op3val:0x401; valaddr_reg:x2; val_offset:34056*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34056*FLEN/8, x3, x1, x4) + +inst_11387: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7e01; +op3val:0x8455; valaddr_reg:x2; val_offset:34059*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34059*FLEN/8, x3, x1, x4) + +inst_11388: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7e01; +op3val:0x7bff; valaddr_reg:x2; val_offset:34062*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34062*FLEN/8, x3, x1, x4) + +inst_11389: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7e01; +op3val:0xfbff; valaddr_reg:x2; val_offset:34065*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34065*FLEN/8, x3, x1, x4) + +inst_11390: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7e01; +op3val:0x7c00; valaddr_reg:x2; val_offset:34068*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34068*FLEN/8, x3, x1, x4) + +inst_11391: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7e01; +op3val:0xfc00; valaddr_reg:x2; val_offset:34071*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34071*FLEN/8, x3, x1, x4) + +inst_11392: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7e01; +op3val:0x7e00; valaddr_reg:x2; val_offset:34074*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34074*FLEN/8, x3, x1, x4) + +inst_11393: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7e01; +op3val:0xfe00; valaddr_reg:x2; val_offset:34077*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34077*FLEN/8, x3, x1, x4) + +inst_11394: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7e01; +op3val:0x7e01; valaddr_reg:x2; val_offset:34080*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34080*FLEN/8, x3, x1, x4) + +inst_11395: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7e01; +op3val:0xfe55; valaddr_reg:x2; val_offset:34083*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34083*FLEN/8, x3, x1, x4) + +inst_11396: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7e01; +op3val:0x7c01; valaddr_reg:x2; val_offset:34086*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34086*FLEN/8, x3, x1, x4) + +inst_11397: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7e01; +op3val:0xfd55; valaddr_reg:x2; val_offset:34089*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34089*FLEN/8, x3, x1, x4) + +inst_11398: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7e01; +op3val:0x3c00; valaddr_reg:x2; val_offset:34092*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34092*FLEN/8, x3, x1, x4) + +inst_11399: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7e01; +op3val:0xbc00; valaddr_reg:x2; val_offset:34095*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34095*FLEN/8, x3, x1, x4) + +inst_11400: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfe55; +op3val:0x0; valaddr_reg:x2; val_offset:34098*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34098*FLEN/8, x3, x1, x4) + +inst_11401: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfe55; +op3val:0x8000; valaddr_reg:x2; val_offset:34101*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34101*FLEN/8, x3, x1, x4) + +inst_11402: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfe55; +op3val:0x1; valaddr_reg:x2; val_offset:34104*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34104*FLEN/8, x3, x1, x4) + +inst_11403: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfe55; +op3val:0x8001; valaddr_reg:x2; val_offset:34107*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34107*FLEN/8, x3, x1, x4) + +inst_11404: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfe55; +op3val:0x2; valaddr_reg:x2; val_offset:34110*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34110*FLEN/8, x3, x1, x4) + +inst_11405: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfe55; +op3val:0x83fe; valaddr_reg:x2; val_offset:34113*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34113*FLEN/8, x3, x1, x4) + +inst_11406: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfe55; +op3val:0x3ff; valaddr_reg:x2; val_offset:34116*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34116*FLEN/8, x3, x1, x4) + +inst_11407: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfe55; +op3val:0x83ff; valaddr_reg:x2; val_offset:34119*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34119*FLEN/8, x3, x1, x4) + +inst_11408: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfe55; +op3val:0x400; valaddr_reg:x2; val_offset:34122*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34122*FLEN/8, x3, x1, x4) + +inst_11409: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfe55; +op3val:0x8400; valaddr_reg:x2; val_offset:34125*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34125*FLEN/8, x3, x1, x4) + +inst_11410: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfe55; +op3val:0x401; valaddr_reg:x2; val_offset:34128*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34128*FLEN/8, x3, x1, x4) + +inst_11411: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfe55; +op3val:0x8455; valaddr_reg:x2; val_offset:34131*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34131*FLEN/8, x3, x1, x4) + +inst_11412: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfe55; +op3val:0x7bff; valaddr_reg:x2; val_offset:34134*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34134*FLEN/8, x3, x1, x4) + +inst_11413: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfe55; +op3val:0xfbff; valaddr_reg:x2; val_offset:34137*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34137*FLEN/8, x3, x1, x4) + +inst_11414: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfe55; +op3val:0x7c00; valaddr_reg:x2; val_offset:34140*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34140*FLEN/8, x3, x1, x4) + +inst_11415: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfe55; +op3val:0xfc00; valaddr_reg:x2; val_offset:34143*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34143*FLEN/8, x3, x1, x4) + +inst_11416: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfe55; +op3val:0x7e00; valaddr_reg:x2; val_offset:34146*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34146*FLEN/8, x3, x1, x4) + +inst_11417: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfe55; +op3val:0xfe00; valaddr_reg:x2; val_offset:34149*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34149*FLEN/8, x3, x1, x4) + +inst_11418: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfe55; +op3val:0x7e01; valaddr_reg:x2; val_offset:34152*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34152*FLEN/8, x3, x1, x4) + +inst_11419: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfe55; +op3val:0xfe55; valaddr_reg:x2; val_offset:34155*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34155*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_90) + +inst_11420: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfe55; +op3val:0x7c01; valaddr_reg:x2; val_offset:34158*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34158*FLEN/8, x3, x1, x4) + +inst_11421: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfe55; +op3val:0xfd55; valaddr_reg:x2; val_offset:34161*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34161*FLEN/8, x3, x1, x4) + +inst_11422: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfe55; +op3val:0x3c00; valaddr_reg:x2; val_offset:34164*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34164*FLEN/8, x3, x1, x4) + +inst_11423: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfe55; +op3val:0xbc00; valaddr_reg:x2; val_offset:34167*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34167*FLEN/8, x3, x1, x4) + +inst_11424: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7c01; +op3val:0x0; valaddr_reg:x2; val_offset:34170*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34170*FLEN/8, x3, x1, x4) + +inst_11425: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7c01; +op3val:0x8000; valaddr_reg:x2; val_offset:34173*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34173*FLEN/8, x3, x1, x4) + +inst_11426: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7c01; +op3val:0x1; valaddr_reg:x2; val_offset:34176*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34176*FLEN/8, x3, x1, x4) + +inst_11427: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7c01; +op3val:0x8001; valaddr_reg:x2; val_offset:34179*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34179*FLEN/8, x3, x1, x4) + +inst_11428: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7c01; +op3val:0x2; valaddr_reg:x2; val_offset:34182*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34182*FLEN/8, x3, x1, x4) + +inst_11429: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7c01; +op3val:0x83fe; valaddr_reg:x2; val_offset:34185*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34185*FLEN/8, x3, x1, x4) + +inst_11430: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7c01; +op3val:0x3ff; valaddr_reg:x2; val_offset:34188*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34188*FLEN/8, x3, x1, x4) + +inst_11431: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7c01; +op3val:0x83ff; valaddr_reg:x2; val_offset:34191*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34191*FLEN/8, x3, x1, x4) + +inst_11432: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7c01; +op3val:0x400; valaddr_reg:x2; val_offset:34194*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34194*FLEN/8, x3, x1, x4) + +inst_11433: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7c01; +op3val:0x8400; valaddr_reg:x2; val_offset:34197*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34197*FLEN/8, x3, x1, x4) + +inst_11434: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7c01; +op3val:0x401; valaddr_reg:x2; val_offset:34200*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34200*FLEN/8, x3, x1, x4) + +inst_11435: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7c01; +op3val:0x8455; valaddr_reg:x2; val_offset:34203*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34203*FLEN/8, x3, x1, x4) + +inst_11436: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7c01; +op3val:0x7bff; valaddr_reg:x2; val_offset:34206*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34206*FLEN/8, x3, x1, x4) + +inst_11437: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7c01; +op3val:0xfbff; valaddr_reg:x2; val_offset:34209*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34209*FLEN/8, x3, x1, x4) + +inst_11438: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7c01; +op3val:0x7c00; valaddr_reg:x2; val_offset:34212*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34212*FLEN/8, x3, x1, x4) + +inst_11439: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7c01; +op3val:0xfc00; valaddr_reg:x2; val_offset:34215*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34215*FLEN/8, x3, x1, x4) + +inst_11440: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7c01; +op3val:0x7e00; valaddr_reg:x2; val_offset:34218*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34218*FLEN/8, x3, x1, x4) + +inst_11441: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7c01; +op3val:0xfe00; valaddr_reg:x2; val_offset:34221*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34221*FLEN/8, x3, x1, x4) + +inst_11442: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7c01; +op3val:0x7e01; valaddr_reg:x2; val_offset:34224*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34224*FLEN/8, x3, x1, x4) + +inst_11443: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7c01; +op3val:0xfe55; valaddr_reg:x2; val_offset:34227*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34227*FLEN/8, x3, x1, x4) + +inst_11444: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7c01; +op3val:0x7c01; valaddr_reg:x2; val_offset:34230*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34230*FLEN/8, x3, x1, x4) + +inst_11445: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7c01; +op3val:0xfd55; valaddr_reg:x2; val_offset:34233*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34233*FLEN/8, x3, x1, x4) + +inst_11446: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7c01; +op3val:0x3c00; valaddr_reg:x2; val_offset:34236*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34236*FLEN/8, x3, x1, x4) + +inst_11447: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x7c01; +op3val:0xbc00; valaddr_reg:x2; val_offset:34239*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34239*FLEN/8, x3, x1, x4) + +inst_11448: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfd55; +op3val:0x0; valaddr_reg:x2; val_offset:34242*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34242*FLEN/8, x3, x1, x4) + +inst_11449: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfd55; +op3val:0x8000; valaddr_reg:x2; val_offset:34245*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34245*FLEN/8, x3, x1, x4) + +inst_11450: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfd55; +op3val:0x1; valaddr_reg:x2; val_offset:34248*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34248*FLEN/8, x3, x1, x4) + +inst_11451: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfd55; +op3val:0x8001; valaddr_reg:x2; val_offset:34251*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34251*FLEN/8, x3, x1, x4) + +inst_11452: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfd55; +op3val:0x2; valaddr_reg:x2; val_offset:34254*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34254*FLEN/8, x3, x1, x4) + +inst_11453: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfd55; +op3val:0x83fe; valaddr_reg:x2; val_offset:34257*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34257*FLEN/8, x3, x1, x4) + +inst_11454: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfd55; +op3val:0x3ff; valaddr_reg:x2; val_offset:34260*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34260*FLEN/8, x3, x1, x4) + +inst_11455: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfd55; +op3val:0x83ff; valaddr_reg:x2; val_offset:34263*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34263*FLEN/8, x3, x1, x4) + +inst_11456: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfd55; +op3val:0x400; valaddr_reg:x2; val_offset:34266*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34266*FLEN/8, x3, x1, x4) + +inst_11457: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfd55; +op3val:0x8400; valaddr_reg:x2; val_offset:34269*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34269*FLEN/8, x3, x1, x4) + +inst_11458: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfd55; +op3val:0x401; valaddr_reg:x2; val_offset:34272*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34272*FLEN/8, x3, x1, x4) + +inst_11459: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfd55; +op3val:0x8455; valaddr_reg:x2; val_offset:34275*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34275*FLEN/8, x3, x1, x4) + +inst_11460: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfd55; +op3val:0x7bff; valaddr_reg:x2; val_offset:34278*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34278*FLEN/8, x3, x1, x4) + +inst_11461: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfd55; +op3val:0xfbff; valaddr_reg:x2; val_offset:34281*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34281*FLEN/8, x3, x1, x4) + +inst_11462: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfd55; +op3val:0x7c00; valaddr_reg:x2; val_offset:34284*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34284*FLEN/8, x3, x1, x4) + +inst_11463: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfd55; +op3val:0xfc00; valaddr_reg:x2; val_offset:34287*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34287*FLEN/8, x3, x1, x4) + +inst_11464: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfd55; +op3val:0x7e00; valaddr_reg:x2; val_offset:34290*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34290*FLEN/8, x3, x1, x4) + +inst_11465: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfd55; +op3val:0xfe00; valaddr_reg:x2; val_offset:34293*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34293*FLEN/8, x3, x1, x4) + +inst_11466: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfd55; +op3val:0x7e01; valaddr_reg:x2; val_offset:34296*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34296*FLEN/8, x3, x1, x4) + +inst_11467: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfd55; +op3val:0xfe55; valaddr_reg:x2; val_offset:34299*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34299*FLEN/8, x3, x1, x4) + +inst_11468: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfd55; +op3val:0x7c01; valaddr_reg:x2; val_offset:34302*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34302*FLEN/8, x3, x1, x4) + +inst_11469: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfd55; +op3val:0xfd55; valaddr_reg:x2; val_offset:34305*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34305*FLEN/8, x3, x1, x4) + +inst_11470: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfd55; +op3val:0x3c00; valaddr_reg:x2; val_offset:34308*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34308*FLEN/8, x3, x1, x4) + +inst_11471: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xfd55; +op3val:0xbc00; valaddr_reg:x2; val_offset:34311*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34311*FLEN/8, x3, x1, x4) + +inst_11472: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x3c00; +op3val:0x0; valaddr_reg:x2; val_offset:34314*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34314*FLEN/8, x3, x1, x4) + +inst_11473: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x3c00; +op3val:0x8000; valaddr_reg:x2; val_offset:34317*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34317*FLEN/8, x3, x1, x4) + +inst_11474: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x3c00; +op3val:0x1; valaddr_reg:x2; val_offset:34320*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34320*FLEN/8, x3, x1, x4) + +inst_11475: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x3c00; +op3val:0x8001; valaddr_reg:x2; val_offset:34323*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34323*FLEN/8, x3, x1, x4) + +inst_11476: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x3c00; +op3val:0x2; valaddr_reg:x2; val_offset:34326*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34326*FLEN/8, x3, x1, x4) + +inst_11477: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x3c00; +op3val:0x83fe; valaddr_reg:x2; val_offset:34329*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34329*FLEN/8, x3, x1, x4) + +inst_11478: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x3c00; +op3val:0x3ff; valaddr_reg:x2; val_offset:34332*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34332*FLEN/8, x3, x1, x4) + +inst_11479: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x3c00; +op3val:0x83ff; valaddr_reg:x2; val_offset:34335*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34335*FLEN/8, x3, x1, x4) + +inst_11480: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x3c00; +op3val:0x400; valaddr_reg:x2; val_offset:34338*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34338*FLEN/8, x3, x1, x4) + +inst_11481: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x3c00; +op3val:0x8400; valaddr_reg:x2; val_offset:34341*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34341*FLEN/8, x3, x1, x4) + +inst_11482: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x3c00; +op3val:0x401; valaddr_reg:x2; val_offset:34344*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34344*FLEN/8, x3, x1, x4) + +inst_11483: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x3c00; +op3val:0x8455; valaddr_reg:x2; val_offset:34347*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34347*FLEN/8, x3, x1, x4) + +inst_11484: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x3c00; +op3val:0x7bff; valaddr_reg:x2; val_offset:34350*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34350*FLEN/8, x3, x1, x4) + +inst_11485: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x3c00; +op3val:0xfbff; valaddr_reg:x2; val_offset:34353*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34353*FLEN/8, x3, x1, x4) + +inst_11486: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x3c00; +op3val:0x7c00; valaddr_reg:x2; val_offset:34356*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34356*FLEN/8, x3, x1, x4) + +inst_11487: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x3c00; +op3val:0xfc00; valaddr_reg:x2; val_offset:34359*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34359*FLEN/8, x3, x1, x4) + +inst_11488: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x3c00; +op3val:0x7e00; valaddr_reg:x2; val_offset:34362*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34362*FLEN/8, x3, x1, x4) + +inst_11489: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x3c00; +op3val:0xfe00; valaddr_reg:x2; val_offset:34365*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34365*FLEN/8, x3, x1, x4) + +inst_11490: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x3c00; +op3val:0x7e01; valaddr_reg:x2; val_offset:34368*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34368*FLEN/8, x3, x1, x4) + +inst_11491: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x3c00; +op3val:0xfe55; valaddr_reg:x2; val_offset:34371*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34371*FLEN/8, x3, x1, x4) + +inst_11492: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x3c00; +op3val:0x7c01; valaddr_reg:x2; val_offset:34374*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34374*FLEN/8, x3, x1, x4) + +inst_11493: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x3c00; +op3val:0xfd55; valaddr_reg:x2; val_offset:34377*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34377*FLEN/8, x3, x1, x4) + +inst_11494: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x3c00; +op3val:0x3c00; valaddr_reg:x2; val_offset:34380*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34380*FLEN/8, x3, x1, x4) + +inst_11495: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0x3c00; +op3val:0xbc00; valaddr_reg:x2; val_offset:34383*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34383*FLEN/8, x3, x1, x4) + +inst_11496: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xbc00; +op3val:0x0; valaddr_reg:x2; val_offset:34386*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34386*FLEN/8, x3, x1, x4) + +inst_11497: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xbc00; +op3val:0x8000; valaddr_reg:x2; val_offset:34389*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34389*FLEN/8, x3, x1, x4) + +inst_11498: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xbc00; +op3val:0x1; valaddr_reg:x2; val_offset:34392*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34392*FLEN/8, x3, x1, x4) + +inst_11499: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xbc00; +op3val:0x8001; valaddr_reg:x2; val_offset:34395*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34395*FLEN/8, x3, x1, x4) + +inst_11500: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xbc00; +op3val:0x2; valaddr_reg:x2; val_offset:34398*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34398*FLEN/8, x3, x1, x4) + +inst_11501: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xbc00; +op3val:0x83fe; valaddr_reg:x2; val_offset:34401*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34401*FLEN/8, x3, x1, x4) + +inst_11502: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xbc00; +op3val:0x3ff; valaddr_reg:x2; val_offset:34404*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34404*FLEN/8, x3, x1, x4) + +inst_11503: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xbc00; +op3val:0x83ff; valaddr_reg:x2; val_offset:34407*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34407*FLEN/8, x3, x1, x4) + +inst_11504: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xbc00; +op3val:0x400; valaddr_reg:x2; val_offset:34410*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34410*FLEN/8, x3, x1, x4) + +inst_11505: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xbc00; +op3val:0x8400; valaddr_reg:x2; val_offset:34413*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34413*FLEN/8, x3, x1, x4) + +inst_11506: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xbc00; +op3val:0x401; valaddr_reg:x2; val_offset:34416*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34416*FLEN/8, x3, x1, x4) + +inst_11507: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xbc00; +op3val:0x8455; valaddr_reg:x2; val_offset:34419*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34419*FLEN/8, x3, x1, x4) + +inst_11508: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xbc00; +op3val:0x7bff; valaddr_reg:x2; val_offset:34422*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34422*FLEN/8, x3, x1, x4) + +inst_11509: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xbc00; +op3val:0xfbff; valaddr_reg:x2; val_offset:34425*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34425*FLEN/8, x3, x1, x4) + +inst_11510: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xbc00; +op3val:0x7c00; valaddr_reg:x2; val_offset:34428*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34428*FLEN/8, x3, x1, x4) + +inst_11511: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xbc00; +op3val:0xfc00; valaddr_reg:x2; val_offset:34431*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34431*FLEN/8, x3, x1, x4) + +inst_11512: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xbc00; +op3val:0x7e00; valaddr_reg:x2; val_offset:34434*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34434*FLEN/8, x3, x1, x4) + +inst_11513: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xbc00; +op3val:0xfe00; valaddr_reg:x2; val_offset:34437*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34437*FLEN/8, x3, x1, x4) + +inst_11514: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xbc00; +op3val:0x7e01; valaddr_reg:x2; val_offset:34440*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34440*FLEN/8, x3, x1, x4) + +inst_11515: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xbc00; +op3val:0xfe55; valaddr_reg:x2; val_offset:34443*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34443*FLEN/8, x3, x1, x4) + +inst_11516: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xbc00; +op3val:0x7c01; valaddr_reg:x2; val_offset:34446*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34446*FLEN/8, x3, x1, x4) + +inst_11517: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xbc00; +op3val:0xfd55; valaddr_reg:x2; val_offset:34449*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34449*FLEN/8, x3, x1, x4) + +inst_11518: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xbc00; +op3val:0x3c00; valaddr_reg:x2; val_offset:34452*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34452*FLEN/8, x3, x1, x4) + +inst_11519: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfe55; op2val:0xbc00; +op3val:0xbc00; valaddr_reg:x2; val_offset:34455*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34455*FLEN/8, x3, x1, x4) + +inst_11520: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x0; +op3val:0x0; valaddr_reg:x2; val_offset:34458*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34458*FLEN/8, x3, x1, x4) + +inst_11521: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x0; +op3val:0x8000; valaddr_reg:x2; val_offset:34461*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34461*FLEN/8, x3, x1, x4) + +inst_11522: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x0; +op3val:0x1; valaddr_reg:x2; val_offset:34464*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34464*FLEN/8, x3, x1, x4) + +inst_11523: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x0; +op3val:0x8001; valaddr_reg:x2; val_offset:34467*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34467*FLEN/8, x3, x1, x4) + +inst_11524: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x0; +op3val:0x2; valaddr_reg:x2; val_offset:34470*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34470*FLEN/8, x3, x1, x4) + +inst_11525: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x0; +op3val:0x83fe; valaddr_reg:x2; val_offset:34473*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34473*FLEN/8, x3, x1, x4) + +inst_11526: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x0; +op3val:0x3ff; valaddr_reg:x2; val_offset:34476*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34476*FLEN/8, x3, x1, x4) + +inst_11527: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x0; +op3val:0x83ff; valaddr_reg:x2; val_offset:34479*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34479*FLEN/8, x3, x1, x4) + +inst_11528: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x0; +op3val:0x400; valaddr_reg:x2; val_offset:34482*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34482*FLEN/8, x3, x1, x4) + +inst_11529: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x0; +op3val:0x8400; valaddr_reg:x2; val_offset:34485*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34485*FLEN/8, x3, x1, x4) + +inst_11530: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x0; +op3val:0x401; valaddr_reg:x2; val_offset:34488*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34488*FLEN/8, x3, x1, x4) + +inst_11531: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x0; +op3val:0x8455; valaddr_reg:x2; val_offset:34491*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34491*FLEN/8, x3, x1, x4) + +inst_11532: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x0; +op3val:0x7bff; valaddr_reg:x2; val_offset:34494*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34494*FLEN/8, x3, x1, x4) + +inst_11533: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x0; +op3val:0xfbff; valaddr_reg:x2; val_offset:34497*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34497*FLEN/8, x3, x1, x4) + +inst_11534: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x0; +op3val:0x7c00; valaddr_reg:x2; val_offset:34500*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34500*FLEN/8, x3, x1, x4) + +inst_11535: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x0; +op3val:0xfc00; valaddr_reg:x2; val_offset:34503*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34503*FLEN/8, x3, x1, x4) + +inst_11536: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x0; +op3val:0x7e00; valaddr_reg:x2; val_offset:34506*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34506*FLEN/8, x3, x1, x4) + +inst_11537: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x0; +op3val:0xfe00; valaddr_reg:x2; val_offset:34509*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34509*FLEN/8, x3, x1, x4) + +inst_11538: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x0; +op3val:0x7e01; valaddr_reg:x2; val_offset:34512*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34512*FLEN/8, x3, x1, x4) + +inst_11539: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x0; +op3val:0xfe55; valaddr_reg:x2; val_offset:34515*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34515*FLEN/8, x3, x1, x4) + +inst_11540: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x0; +op3val:0x7c01; valaddr_reg:x2; val_offset:34518*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34518*FLEN/8, x3, x1, x4) + +inst_11541: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x0; +op3val:0xfd55; valaddr_reg:x2; val_offset:34521*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34521*FLEN/8, x3, x1, x4) + +inst_11542: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x0; +op3val:0x3c00; valaddr_reg:x2; val_offset:34524*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34524*FLEN/8, x3, x1, x4) + +inst_11543: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x0; +op3val:0xbc00; valaddr_reg:x2; val_offset:34527*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34527*FLEN/8, x3, x1, x4) + +inst_11544: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8000; +op3val:0x0; valaddr_reg:x2; val_offset:34530*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34530*FLEN/8, x3, x1, x4) + +inst_11545: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8000; +op3val:0x8000; valaddr_reg:x2; val_offset:34533*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34533*FLEN/8, x3, x1, x4) + +inst_11546: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8000; +op3val:0x1; valaddr_reg:x2; val_offset:34536*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34536*FLEN/8, x3, x1, x4) + +inst_11547: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8000; +op3val:0x8001; valaddr_reg:x2; val_offset:34539*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34539*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_91) + +inst_11548: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8000; +op3val:0x2; valaddr_reg:x2; val_offset:34542*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34542*FLEN/8, x3, x1, x4) + +inst_11549: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8000; +op3val:0x83fe; valaddr_reg:x2; val_offset:34545*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34545*FLEN/8, x3, x1, x4) + +inst_11550: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8000; +op3val:0x3ff; valaddr_reg:x2; val_offset:34548*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34548*FLEN/8, x3, x1, x4) + +inst_11551: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8000; +op3val:0x83ff; valaddr_reg:x2; val_offset:34551*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34551*FLEN/8, x3, x1, x4) + +inst_11552: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8000; +op3val:0x400; valaddr_reg:x2; val_offset:34554*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34554*FLEN/8, x3, x1, x4) + +inst_11553: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8000; +op3val:0x8400; valaddr_reg:x2; val_offset:34557*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34557*FLEN/8, x3, x1, x4) + +inst_11554: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8000; +op3val:0x401; valaddr_reg:x2; val_offset:34560*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34560*FLEN/8, x3, x1, x4) + +inst_11555: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8000; +op3val:0x8455; valaddr_reg:x2; val_offset:34563*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34563*FLEN/8, x3, x1, x4) + +inst_11556: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x2; val_offset:34566*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34566*FLEN/8, x3, x1, x4) + +inst_11557: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x2; val_offset:34569*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34569*FLEN/8, x3, x1, x4) + +inst_11558: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8000; +op3val:0x7c00; valaddr_reg:x2; val_offset:34572*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34572*FLEN/8, x3, x1, x4) + +inst_11559: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8000; +op3val:0xfc00; valaddr_reg:x2; val_offset:34575*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34575*FLEN/8, x3, x1, x4) + +inst_11560: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8000; +op3val:0x7e00; valaddr_reg:x2; val_offset:34578*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34578*FLEN/8, x3, x1, x4) + +inst_11561: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8000; +op3val:0xfe00; valaddr_reg:x2; val_offset:34581*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34581*FLEN/8, x3, x1, x4) + +inst_11562: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8000; +op3val:0x7e01; valaddr_reg:x2; val_offset:34584*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34584*FLEN/8, x3, x1, x4) + +inst_11563: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8000; +op3val:0xfe55; valaddr_reg:x2; val_offset:34587*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34587*FLEN/8, x3, x1, x4) + +inst_11564: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8000; +op3val:0x7c01; valaddr_reg:x2; val_offset:34590*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34590*FLEN/8, x3, x1, x4) + +inst_11565: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8000; +op3val:0xfd55; valaddr_reg:x2; val_offset:34593*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34593*FLEN/8, x3, x1, x4) + +inst_11566: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8000; +op3val:0x3c00; valaddr_reg:x2; val_offset:34596*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34596*FLEN/8, x3, x1, x4) + +inst_11567: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8000; +op3val:0xbc00; valaddr_reg:x2; val_offset:34599*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34599*FLEN/8, x3, x1, x4) + +inst_11568: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x1; +op3val:0x0; valaddr_reg:x2; val_offset:34602*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34602*FLEN/8, x3, x1, x4) + +inst_11569: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x1; +op3val:0x8000; valaddr_reg:x2; val_offset:34605*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34605*FLEN/8, x3, x1, x4) + +inst_11570: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x1; +op3val:0x1; valaddr_reg:x2; val_offset:34608*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34608*FLEN/8, x3, x1, x4) + +inst_11571: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x1; +op3val:0x8001; valaddr_reg:x2; val_offset:34611*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34611*FLEN/8, x3, x1, x4) + +inst_11572: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x1; +op3val:0x2; valaddr_reg:x2; val_offset:34614*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34614*FLEN/8, x3, x1, x4) + +inst_11573: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x1; +op3val:0x83fe; valaddr_reg:x2; val_offset:34617*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34617*FLEN/8, x3, x1, x4) + +inst_11574: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x1; +op3val:0x3ff; valaddr_reg:x2; val_offset:34620*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34620*FLEN/8, x3, x1, x4) + +inst_11575: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x1; +op3val:0x83ff; valaddr_reg:x2; val_offset:34623*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34623*FLEN/8, x3, x1, x4) + +inst_11576: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x1; +op3val:0x400; valaddr_reg:x2; val_offset:34626*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34626*FLEN/8, x3, x1, x4) + +inst_11577: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x1; +op3val:0x8400; valaddr_reg:x2; val_offset:34629*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34629*FLEN/8, x3, x1, x4) + +inst_11578: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x1; +op3val:0x401; valaddr_reg:x2; val_offset:34632*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34632*FLEN/8, x3, x1, x4) + +inst_11579: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x1; +op3val:0x8455; valaddr_reg:x2; val_offset:34635*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34635*FLEN/8, x3, x1, x4) + +inst_11580: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x1; +op3val:0x7bff; valaddr_reg:x2; val_offset:34638*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34638*FLEN/8, x3, x1, x4) + +inst_11581: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x1; +op3val:0xfbff; valaddr_reg:x2; val_offset:34641*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34641*FLEN/8, x3, x1, x4) + +inst_11582: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x1; +op3val:0x7c00; valaddr_reg:x2; val_offset:34644*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34644*FLEN/8, x3, x1, x4) + +inst_11583: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x1; +op3val:0xfc00; valaddr_reg:x2; val_offset:34647*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34647*FLEN/8, x3, x1, x4) + +inst_11584: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x1; +op3val:0x7e00; valaddr_reg:x2; val_offset:34650*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34650*FLEN/8, x3, x1, x4) + +inst_11585: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x1; +op3val:0xfe00; valaddr_reg:x2; val_offset:34653*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34653*FLEN/8, x3, x1, x4) + +inst_11586: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x1; +op3val:0x7e01; valaddr_reg:x2; val_offset:34656*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34656*FLEN/8, x3, x1, x4) + +inst_11587: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x1; +op3val:0xfe55; valaddr_reg:x2; val_offset:34659*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34659*FLEN/8, x3, x1, x4) + +inst_11588: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x1; +op3val:0x7c01; valaddr_reg:x2; val_offset:34662*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34662*FLEN/8, x3, x1, x4) + +inst_11589: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x1; +op3val:0xfd55; valaddr_reg:x2; val_offset:34665*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34665*FLEN/8, x3, x1, x4) + +inst_11590: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x1; +op3val:0x3c00; valaddr_reg:x2; val_offset:34668*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34668*FLEN/8, x3, x1, x4) + +inst_11591: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x1; +op3val:0xbc00; valaddr_reg:x2; val_offset:34671*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34671*FLEN/8, x3, x1, x4) + +inst_11592: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8001; +op3val:0x0; valaddr_reg:x2; val_offset:34674*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34674*FLEN/8, x3, x1, x4) + +inst_11593: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8001; +op3val:0x8000; valaddr_reg:x2; val_offset:34677*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34677*FLEN/8, x3, x1, x4) + +inst_11594: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8001; +op3val:0x1; valaddr_reg:x2; val_offset:34680*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34680*FLEN/8, x3, x1, x4) + +inst_11595: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8001; +op3val:0x8001; valaddr_reg:x2; val_offset:34683*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34683*FLEN/8, x3, x1, x4) + +inst_11596: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8001; +op3val:0x2; valaddr_reg:x2; val_offset:34686*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34686*FLEN/8, x3, x1, x4) + +inst_11597: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8001; +op3val:0x83fe; valaddr_reg:x2; val_offset:34689*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34689*FLEN/8, x3, x1, x4) + +inst_11598: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8001; +op3val:0x3ff; valaddr_reg:x2; val_offset:34692*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34692*FLEN/8, x3, x1, x4) + +inst_11599: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8001; +op3val:0x83ff; valaddr_reg:x2; val_offset:34695*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34695*FLEN/8, x3, x1, x4) + +inst_11600: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8001; +op3val:0x400; valaddr_reg:x2; val_offset:34698*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34698*FLEN/8, x3, x1, x4) + +inst_11601: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8001; +op3val:0x8400; valaddr_reg:x2; val_offset:34701*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34701*FLEN/8, x3, x1, x4) + +inst_11602: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8001; +op3val:0x401; valaddr_reg:x2; val_offset:34704*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34704*FLEN/8, x3, x1, x4) + +inst_11603: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8001; +op3val:0x8455; valaddr_reg:x2; val_offset:34707*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34707*FLEN/8, x3, x1, x4) + +inst_11604: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8001; +op3val:0x7bff; valaddr_reg:x2; val_offset:34710*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34710*FLEN/8, x3, x1, x4) + +inst_11605: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8001; +op3val:0xfbff; valaddr_reg:x2; val_offset:34713*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34713*FLEN/8, x3, x1, x4) + +inst_11606: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8001; +op3val:0x7c00; valaddr_reg:x2; val_offset:34716*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34716*FLEN/8, x3, x1, x4) + +inst_11607: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8001; +op3val:0xfc00; valaddr_reg:x2; val_offset:34719*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34719*FLEN/8, x3, x1, x4) + +inst_11608: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8001; +op3val:0x7e00; valaddr_reg:x2; val_offset:34722*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34722*FLEN/8, x3, x1, x4) + +inst_11609: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8001; +op3val:0xfe00; valaddr_reg:x2; val_offset:34725*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34725*FLEN/8, x3, x1, x4) + +inst_11610: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8001; +op3val:0x7e01; valaddr_reg:x2; val_offset:34728*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34728*FLEN/8, x3, x1, x4) + +inst_11611: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8001; +op3val:0xfe55; valaddr_reg:x2; val_offset:34731*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34731*FLEN/8, x3, x1, x4) + +inst_11612: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8001; +op3val:0x7c01; valaddr_reg:x2; val_offset:34734*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34734*FLEN/8, x3, x1, x4) + +inst_11613: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8001; +op3val:0xfd55; valaddr_reg:x2; val_offset:34737*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34737*FLEN/8, x3, x1, x4) + +inst_11614: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8001; +op3val:0x3c00; valaddr_reg:x2; val_offset:34740*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34740*FLEN/8, x3, x1, x4) + +inst_11615: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8001; +op3val:0xbc00; valaddr_reg:x2; val_offset:34743*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34743*FLEN/8, x3, x1, x4) + +inst_11616: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x2; +op3val:0x0; valaddr_reg:x2; val_offset:34746*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34746*FLEN/8, x3, x1, x4) + +inst_11617: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x2; +op3val:0x8000; valaddr_reg:x2; val_offset:34749*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34749*FLEN/8, x3, x1, x4) + +inst_11618: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x2; +op3val:0x1; valaddr_reg:x2; val_offset:34752*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34752*FLEN/8, x3, x1, x4) + +inst_11619: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x2; +op3val:0x8001; valaddr_reg:x2; val_offset:34755*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34755*FLEN/8, x3, x1, x4) + +inst_11620: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x2; +op3val:0x2; valaddr_reg:x2; val_offset:34758*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34758*FLEN/8, x3, x1, x4) + +inst_11621: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x2; +op3val:0x83fe; valaddr_reg:x2; val_offset:34761*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34761*FLEN/8, x3, x1, x4) + +inst_11622: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x2; +op3val:0x3ff; valaddr_reg:x2; val_offset:34764*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34764*FLEN/8, x3, x1, x4) + +inst_11623: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x2; +op3val:0x83ff; valaddr_reg:x2; val_offset:34767*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34767*FLEN/8, x3, x1, x4) + +inst_11624: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x2; +op3val:0x400; valaddr_reg:x2; val_offset:34770*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34770*FLEN/8, x3, x1, x4) + +inst_11625: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x2; +op3val:0x8400; valaddr_reg:x2; val_offset:34773*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34773*FLEN/8, x3, x1, x4) + +inst_11626: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x2; +op3val:0x401; valaddr_reg:x2; val_offset:34776*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34776*FLEN/8, x3, x1, x4) + +inst_11627: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x2; +op3val:0x8455; valaddr_reg:x2; val_offset:34779*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34779*FLEN/8, x3, x1, x4) + +inst_11628: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x2; +op3val:0x7bff; valaddr_reg:x2; val_offset:34782*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34782*FLEN/8, x3, x1, x4) + +inst_11629: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x2; +op3val:0xfbff; valaddr_reg:x2; val_offset:34785*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34785*FLEN/8, x3, x1, x4) + +inst_11630: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x2; +op3val:0x7c00; valaddr_reg:x2; val_offset:34788*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34788*FLEN/8, x3, x1, x4) + +inst_11631: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x2; +op3val:0xfc00; valaddr_reg:x2; val_offset:34791*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34791*FLEN/8, x3, x1, x4) + +inst_11632: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x2; +op3val:0x7e00; valaddr_reg:x2; val_offset:34794*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34794*FLEN/8, x3, x1, x4) + +inst_11633: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x2; +op3val:0xfe00; valaddr_reg:x2; val_offset:34797*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34797*FLEN/8, x3, x1, x4) + +inst_11634: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x2; +op3val:0x7e01; valaddr_reg:x2; val_offset:34800*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34800*FLEN/8, x3, x1, x4) + +inst_11635: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x2; +op3val:0xfe55; valaddr_reg:x2; val_offset:34803*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34803*FLEN/8, x3, x1, x4) + +inst_11636: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x2; +op3val:0x7c01; valaddr_reg:x2; val_offset:34806*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34806*FLEN/8, x3, x1, x4) + +inst_11637: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x2; +op3val:0xfd55; valaddr_reg:x2; val_offset:34809*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34809*FLEN/8, x3, x1, x4) + +inst_11638: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x2; +op3val:0x3c00; valaddr_reg:x2; val_offset:34812*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34812*FLEN/8, x3, x1, x4) + +inst_11639: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x2; +op3val:0xbc00; valaddr_reg:x2; val_offset:34815*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34815*FLEN/8, x3, x1, x4) + +inst_11640: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x83fe; +op3val:0x0; valaddr_reg:x2; val_offset:34818*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34818*FLEN/8, x3, x1, x4) + +inst_11641: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x83fe; +op3val:0x8000; valaddr_reg:x2; val_offset:34821*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34821*FLEN/8, x3, x1, x4) + +inst_11642: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x83fe; +op3val:0x1; valaddr_reg:x2; val_offset:34824*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34824*FLEN/8, x3, x1, x4) + +inst_11643: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x83fe; +op3val:0x8001; valaddr_reg:x2; val_offset:34827*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34827*FLEN/8, x3, x1, x4) + +inst_11644: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x83fe; +op3val:0x2; valaddr_reg:x2; val_offset:34830*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34830*FLEN/8, x3, x1, x4) + +inst_11645: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x83fe; +op3val:0x83fe; valaddr_reg:x2; val_offset:34833*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34833*FLEN/8, x3, x1, x4) + +inst_11646: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x83fe; +op3val:0x3ff; valaddr_reg:x2; val_offset:34836*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34836*FLEN/8, x3, x1, x4) + +inst_11647: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x83fe; +op3val:0x83ff; valaddr_reg:x2; val_offset:34839*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34839*FLEN/8, x3, x1, x4) + +inst_11648: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x83fe; +op3val:0x400; valaddr_reg:x2; val_offset:34842*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34842*FLEN/8, x3, x1, x4) + +inst_11649: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x83fe; +op3val:0x8400; valaddr_reg:x2; val_offset:34845*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34845*FLEN/8, x3, x1, x4) + +inst_11650: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x83fe; +op3val:0x401; valaddr_reg:x2; val_offset:34848*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34848*FLEN/8, x3, x1, x4) + +inst_11651: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x83fe; +op3val:0x8455; valaddr_reg:x2; val_offset:34851*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34851*FLEN/8, x3, x1, x4) + +inst_11652: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x83fe; +op3val:0x7bff; valaddr_reg:x2; val_offset:34854*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34854*FLEN/8, x3, x1, x4) + +inst_11653: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x83fe; +op3val:0xfbff; valaddr_reg:x2; val_offset:34857*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34857*FLEN/8, x3, x1, x4) + +inst_11654: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x83fe; +op3val:0x7c00; valaddr_reg:x2; val_offset:34860*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34860*FLEN/8, x3, x1, x4) + +inst_11655: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x83fe; +op3val:0xfc00; valaddr_reg:x2; val_offset:34863*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34863*FLEN/8, x3, x1, x4) + +inst_11656: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x83fe; +op3val:0x7e00; valaddr_reg:x2; val_offset:34866*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34866*FLEN/8, x3, x1, x4) + +inst_11657: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x83fe; +op3val:0xfe00; valaddr_reg:x2; val_offset:34869*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34869*FLEN/8, x3, x1, x4) + +inst_11658: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x83fe; +op3val:0x7e01; valaddr_reg:x2; val_offset:34872*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34872*FLEN/8, x3, x1, x4) + +inst_11659: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x83fe; +op3val:0xfe55; valaddr_reg:x2; val_offset:34875*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34875*FLEN/8, x3, x1, x4) + +inst_11660: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x83fe; +op3val:0x7c01; valaddr_reg:x2; val_offset:34878*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34878*FLEN/8, x3, x1, x4) + +inst_11661: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x83fe; +op3val:0xfd55; valaddr_reg:x2; val_offset:34881*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34881*FLEN/8, x3, x1, x4) + +inst_11662: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x83fe; +op3val:0x3c00; valaddr_reg:x2; val_offset:34884*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34884*FLEN/8, x3, x1, x4) + +inst_11663: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x83fe; +op3val:0xbc00; valaddr_reg:x2; val_offset:34887*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34887*FLEN/8, x3, x1, x4) + +inst_11664: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x3ff; +op3val:0x0; valaddr_reg:x2; val_offset:34890*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34890*FLEN/8, x3, x1, x4) + +inst_11665: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x3ff; +op3val:0x8000; valaddr_reg:x2; val_offset:34893*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34893*FLEN/8, x3, x1, x4) + +inst_11666: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x3ff; +op3val:0x1; valaddr_reg:x2; val_offset:34896*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34896*FLEN/8, x3, x1, x4) + +inst_11667: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x3ff; +op3val:0x8001; valaddr_reg:x2; val_offset:34899*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34899*FLEN/8, x3, x1, x4) + +inst_11668: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x3ff; +op3val:0x2; valaddr_reg:x2; val_offset:34902*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34902*FLEN/8, x3, x1, x4) + +inst_11669: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x3ff; +op3val:0x83fe; valaddr_reg:x2; val_offset:34905*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34905*FLEN/8, x3, x1, x4) + +inst_11670: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x3ff; +op3val:0x3ff; valaddr_reg:x2; val_offset:34908*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34908*FLEN/8, x3, x1, x4) + +inst_11671: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x3ff; +op3val:0x83ff; valaddr_reg:x2; val_offset:34911*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34911*FLEN/8, x3, x1, x4) + +inst_11672: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x3ff; +op3val:0x400; valaddr_reg:x2; val_offset:34914*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34914*FLEN/8, x3, x1, x4) + +inst_11673: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x3ff; +op3val:0x8400; valaddr_reg:x2; val_offset:34917*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34917*FLEN/8, x3, x1, x4) + +inst_11674: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x3ff; +op3val:0x401; valaddr_reg:x2; val_offset:34920*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34920*FLEN/8, x3, x1, x4) + +inst_11675: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x3ff; +op3val:0x8455; valaddr_reg:x2; val_offset:34923*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34923*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_92) + +inst_11676: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x3ff; +op3val:0x7bff; valaddr_reg:x2; val_offset:34926*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34926*FLEN/8, x3, x1, x4) + +inst_11677: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x3ff; +op3val:0xfbff; valaddr_reg:x2; val_offset:34929*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34929*FLEN/8, x3, x1, x4) + +inst_11678: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x3ff; +op3val:0x7c00; valaddr_reg:x2; val_offset:34932*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34932*FLEN/8, x3, x1, x4) + +inst_11679: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x3ff; +op3val:0xfc00; valaddr_reg:x2; val_offset:34935*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34935*FLEN/8, x3, x1, x4) + +inst_11680: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x3ff; +op3val:0x7e00; valaddr_reg:x2; val_offset:34938*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34938*FLEN/8, x3, x1, x4) + +inst_11681: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x3ff; +op3val:0xfe00; valaddr_reg:x2; val_offset:34941*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34941*FLEN/8, x3, x1, x4) + +inst_11682: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x3ff; +op3val:0x7e01; valaddr_reg:x2; val_offset:34944*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34944*FLEN/8, x3, x1, x4) + +inst_11683: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x3ff; +op3val:0xfe55; valaddr_reg:x2; val_offset:34947*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34947*FLEN/8, x3, x1, x4) + +inst_11684: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x3ff; +op3val:0x7c01; valaddr_reg:x2; val_offset:34950*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34950*FLEN/8, x3, x1, x4) + +inst_11685: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x3ff; +op3val:0xfd55; valaddr_reg:x2; val_offset:34953*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34953*FLEN/8, x3, x1, x4) + +inst_11686: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x3ff; +op3val:0x3c00; valaddr_reg:x2; val_offset:34956*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34956*FLEN/8, x3, x1, x4) + +inst_11687: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x3ff; +op3val:0xbc00; valaddr_reg:x2; val_offset:34959*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34959*FLEN/8, x3, x1, x4) + +inst_11688: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x83ff; +op3val:0x0; valaddr_reg:x2; val_offset:34962*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34962*FLEN/8, x3, x1, x4) + +inst_11689: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x83ff; +op3val:0x8000; valaddr_reg:x2; val_offset:34965*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34965*FLEN/8, x3, x1, x4) + +inst_11690: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x83ff; +op3val:0x1; valaddr_reg:x2; val_offset:34968*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34968*FLEN/8, x3, x1, x4) + +inst_11691: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x83ff; +op3val:0x8001; valaddr_reg:x2; val_offset:34971*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34971*FLEN/8, x3, x1, x4) + +inst_11692: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x83ff; +op3val:0x2; valaddr_reg:x2; val_offset:34974*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34974*FLEN/8, x3, x1, x4) + +inst_11693: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x83ff; +op3val:0x83fe; valaddr_reg:x2; val_offset:34977*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34977*FLEN/8, x3, x1, x4) + +inst_11694: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x83ff; +op3val:0x3ff; valaddr_reg:x2; val_offset:34980*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34980*FLEN/8, x3, x1, x4) + +inst_11695: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x83ff; +op3val:0x83ff; valaddr_reg:x2; val_offset:34983*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34983*FLEN/8, x3, x1, x4) + +inst_11696: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x83ff; +op3val:0x400; valaddr_reg:x2; val_offset:34986*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34986*FLEN/8, x3, x1, x4) + +inst_11697: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x83ff; +op3val:0x8400; valaddr_reg:x2; val_offset:34989*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34989*FLEN/8, x3, x1, x4) + +inst_11698: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x83ff; +op3val:0x401; valaddr_reg:x2; val_offset:34992*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34992*FLEN/8, x3, x1, x4) + +inst_11699: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x83ff; +op3val:0x8455; valaddr_reg:x2; val_offset:34995*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34995*FLEN/8, x3, x1, x4) + +inst_11700: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x83ff; +op3val:0x7bff; valaddr_reg:x2; val_offset:34998*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 34998*FLEN/8, x3, x1, x4) + +inst_11701: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x83ff; +op3val:0xfbff; valaddr_reg:x2; val_offset:35001*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35001*FLEN/8, x3, x1, x4) + +inst_11702: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x83ff; +op3val:0x7c00; valaddr_reg:x2; val_offset:35004*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35004*FLEN/8, x3, x1, x4) + +inst_11703: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x83ff; +op3val:0xfc00; valaddr_reg:x2; val_offset:35007*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35007*FLEN/8, x3, x1, x4) + +inst_11704: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x83ff; +op3val:0x7e00; valaddr_reg:x2; val_offset:35010*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35010*FLEN/8, x3, x1, x4) + +inst_11705: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x83ff; +op3val:0xfe00; valaddr_reg:x2; val_offset:35013*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35013*FLEN/8, x3, x1, x4) + +inst_11706: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x83ff; +op3val:0x7e01; valaddr_reg:x2; val_offset:35016*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35016*FLEN/8, x3, x1, x4) + +inst_11707: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x83ff; +op3val:0xfe55; valaddr_reg:x2; val_offset:35019*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35019*FLEN/8, x3, x1, x4) + +inst_11708: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x83ff; +op3val:0x7c01; valaddr_reg:x2; val_offset:35022*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35022*FLEN/8, x3, x1, x4) + +inst_11709: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x83ff; +op3val:0xfd55; valaddr_reg:x2; val_offset:35025*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35025*FLEN/8, x3, x1, x4) + +inst_11710: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x83ff; +op3val:0x3c00; valaddr_reg:x2; val_offset:35028*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35028*FLEN/8, x3, x1, x4) + +inst_11711: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x83ff; +op3val:0xbc00; valaddr_reg:x2; val_offset:35031*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35031*FLEN/8, x3, x1, x4) + +inst_11712: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x400; +op3val:0x0; valaddr_reg:x2; val_offset:35034*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35034*FLEN/8, x3, x1, x4) + +inst_11713: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x400; +op3val:0x8000; valaddr_reg:x2; val_offset:35037*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35037*FLEN/8, x3, x1, x4) + +inst_11714: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x400; +op3val:0x1; valaddr_reg:x2; val_offset:35040*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35040*FLEN/8, x3, x1, x4) + +inst_11715: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x400; +op3val:0x8001; valaddr_reg:x2; val_offset:35043*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35043*FLEN/8, x3, x1, x4) + +inst_11716: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x400; +op3val:0x2; valaddr_reg:x2; val_offset:35046*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35046*FLEN/8, x3, x1, x4) + +inst_11717: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x400; +op3val:0x83fe; valaddr_reg:x2; val_offset:35049*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35049*FLEN/8, x3, x1, x4) + +inst_11718: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x400; +op3val:0x3ff; valaddr_reg:x2; val_offset:35052*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35052*FLEN/8, x3, x1, x4) + +inst_11719: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x400; +op3val:0x83ff; valaddr_reg:x2; val_offset:35055*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35055*FLEN/8, x3, x1, x4) + +inst_11720: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x400; +op3val:0x400; valaddr_reg:x2; val_offset:35058*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35058*FLEN/8, x3, x1, x4) + +inst_11721: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x400; +op3val:0x8400; valaddr_reg:x2; val_offset:35061*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35061*FLEN/8, x3, x1, x4) + +inst_11722: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x400; +op3val:0x401; valaddr_reg:x2; val_offset:35064*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35064*FLEN/8, x3, x1, x4) + +inst_11723: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x400; +op3val:0x8455; valaddr_reg:x2; val_offset:35067*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35067*FLEN/8, x3, x1, x4) + +inst_11724: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x400; +op3val:0x7bff; valaddr_reg:x2; val_offset:35070*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35070*FLEN/8, x3, x1, x4) + +inst_11725: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x400; +op3val:0xfbff; valaddr_reg:x2; val_offset:35073*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35073*FLEN/8, x3, x1, x4) + +inst_11726: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x400; +op3val:0x7c00; valaddr_reg:x2; val_offset:35076*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35076*FLEN/8, x3, x1, x4) + +inst_11727: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x400; +op3val:0xfc00; valaddr_reg:x2; val_offset:35079*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35079*FLEN/8, x3, x1, x4) + +inst_11728: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x400; +op3val:0x7e00; valaddr_reg:x2; val_offset:35082*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35082*FLEN/8, x3, x1, x4) + +inst_11729: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x400; +op3val:0xfe00; valaddr_reg:x2; val_offset:35085*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35085*FLEN/8, x3, x1, x4) + +inst_11730: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x400; +op3val:0x7e01; valaddr_reg:x2; val_offset:35088*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35088*FLEN/8, x3, x1, x4) + +inst_11731: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x400; +op3val:0xfe55; valaddr_reg:x2; val_offset:35091*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35091*FLEN/8, x3, x1, x4) + +inst_11732: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x400; +op3val:0x7c01; valaddr_reg:x2; val_offset:35094*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35094*FLEN/8, x3, x1, x4) + +inst_11733: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x400; +op3val:0xfd55; valaddr_reg:x2; val_offset:35097*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35097*FLEN/8, x3, x1, x4) + +inst_11734: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x400; +op3val:0x3c00; valaddr_reg:x2; val_offset:35100*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35100*FLEN/8, x3, x1, x4) + +inst_11735: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x400; +op3val:0xbc00; valaddr_reg:x2; val_offset:35103*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35103*FLEN/8, x3, x1, x4) + +inst_11736: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8400; +op3val:0x0; valaddr_reg:x2; val_offset:35106*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35106*FLEN/8, x3, x1, x4) + +inst_11737: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8400; +op3val:0x8000; valaddr_reg:x2; val_offset:35109*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35109*FLEN/8, x3, x1, x4) + +inst_11738: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8400; +op3val:0x1; valaddr_reg:x2; val_offset:35112*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35112*FLEN/8, x3, x1, x4) + +inst_11739: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8400; +op3val:0x8001; valaddr_reg:x2; val_offset:35115*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35115*FLEN/8, x3, x1, x4) + +inst_11740: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8400; +op3val:0x2; valaddr_reg:x2; val_offset:35118*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35118*FLEN/8, x3, x1, x4) + +inst_11741: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8400; +op3val:0x83fe; valaddr_reg:x2; val_offset:35121*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35121*FLEN/8, x3, x1, x4) + +inst_11742: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8400; +op3val:0x3ff; valaddr_reg:x2; val_offset:35124*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35124*FLEN/8, x3, x1, x4) + +inst_11743: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8400; +op3val:0x83ff; valaddr_reg:x2; val_offset:35127*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35127*FLEN/8, x3, x1, x4) + +inst_11744: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8400; +op3val:0x400; valaddr_reg:x2; val_offset:35130*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35130*FLEN/8, x3, x1, x4) + +inst_11745: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8400; +op3val:0x8400; valaddr_reg:x2; val_offset:35133*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35133*FLEN/8, x3, x1, x4) + +inst_11746: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8400; +op3val:0x401; valaddr_reg:x2; val_offset:35136*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35136*FLEN/8, x3, x1, x4) + +inst_11747: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8400; +op3val:0x8455; valaddr_reg:x2; val_offset:35139*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35139*FLEN/8, x3, x1, x4) + +inst_11748: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8400; +op3val:0x7bff; valaddr_reg:x2; val_offset:35142*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35142*FLEN/8, x3, x1, x4) + +inst_11749: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8400; +op3val:0xfbff; valaddr_reg:x2; val_offset:35145*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35145*FLEN/8, x3, x1, x4) + +inst_11750: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8400; +op3val:0x7c00; valaddr_reg:x2; val_offset:35148*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35148*FLEN/8, x3, x1, x4) + +inst_11751: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8400; +op3val:0xfc00; valaddr_reg:x2; val_offset:35151*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35151*FLEN/8, x3, x1, x4) + +inst_11752: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8400; +op3val:0x7e00; valaddr_reg:x2; val_offset:35154*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35154*FLEN/8, x3, x1, x4) + +inst_11753: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8400; +op3val:0xfe00; valaddr_reg:x2; val_offset:35157*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35157*FLEN/8, x3, x1, x4) + +inst_11754: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8400; +op3val:0x7e01; valaddr_reg:x2; val_offset:35160*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35160*FLEN/8, x3, x1, x4) + +inst_11755: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8400; +op3val:0xfe55; valaddr_reg:x2; val_offset:35163*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35163*FLEN/8, x3, x1, x4) + +inst_11756: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8400; +op3val:0x7c01; valaddr_reg:x2; val_offset:35166*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35166*FLEN/8, x3, x1, x4) + +inst_11757: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8400; +op3val:0xfd55; valaddr_reg:x2; val_offset:35169*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35169*FLEN/8, x3, x1, x4) + +inst_11758: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8400; +op3val:0x3c00; valaddr_reg:x2; val_offset:35172*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35172*FLEN/8, x3, x1, x4) + +inst_11759: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8400; +op3val:0xbc00; valaddr_reg:x2; val_offset:35175*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35175*FLEN/8, x3, x1, x4) + +inst_11760: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x401; +op3val:0x0; valaddr_reg:x2; val_offset:35178*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35178*FLEN/8, x3, x1, x4) + +inst_11761: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x401; +op3val:0x8000; valaddr_reg:x2; val_offset:35181*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35181*FLEN/8, x3, x1, x4) + +inst_11762: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x401; +op3val:0x1; valaddr_reg:x2; val_offset:35184*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35184*FLEN/8, x3, x1, x4) + +inst_11763: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x401; +op3val:0x8001; valaddr_reg:x2; val_offset:35187*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35187*FLEN/8, x3, x1, x4) + +inst_11764: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x401; +op3val:0x2; valaddr_reg:x2; val_offset:35190*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35190*FLEN/8, x3, x1, x4) + +inst_11765: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x401; +op3val:0x83fe; valaddr_reg:x2; val_offset:35193*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35193*FLEN/8, x3, x1, x4) + +inst_11766: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x401; +op3val:0x3ff; valaddr_reg:x2; val_offset:35196*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35196*FLEN/8, x3, x1, x4) + +inst_11767: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x401; +op3val:0x83ff; valaddr_reg:x2; val_offset:35199*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35199*FLEN/8, x3, x1, x4) + +inst_11768: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x401; +op3val:0x400; valaddr_reg:x2; val_offset:35202*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35202*FLEN/8, x3, x1, x4) + +inst_11769: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x401; +op3val:0x8400; valaddr_reg:x2; val_offset:35205*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35205*FLEN/8, x3, x1, x4) + +inst_11770: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x401; +op3val:0x401; valaddr_reg:x2; val_offset:35208*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35208*FLEN/8, x3, x1, x4) + +inst_11771: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x401; +op3val:0x8455; valaddr_reg:x2; val_offset:35211*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35211*FLEN/8, x3, x1, x4) + +inst_11772: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x401; +op3val:0x7bff; valaddr_reg:x2; val_offset:35214*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35214*FLEN/8, x3, x1, x4) + +inst_11773: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x401; +op3val:0xfbff; valaddr_reg:x2; val_offset:35217*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35217*FLEN/8, x3, x1, x4) + +inst_11774: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x401; +op3val:0x7c00; valaddr_reg:x2; val_offset:35220*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35220*FLEN/8, x3, x1, x4) + +inst_11775: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x401; +op3val:0xfc00; valaddr_reg:x2; val_offset:35223*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35223*FLEN/8, x3, x1, x4) + +inst_11776: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x401; +op3val:0x7e00; valaddr_reg:x2; val_offset:35226*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35226*FLEN/8, x3, x1, x4) + +inst_11777: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x401; +op3val:0xfe00; valaddr_reg:x2; val_offset:35229*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35229*FLEN/8, x3, x1, x4) + +inst_11778: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x401; +op3val:0x7e01; valaddr_reg:x2; val_offset:35232*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35232*FLEN/8, x3, x1, x4) + +inst_11779: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x401; +op3val:0xfe55; valaddr_reg:x2; val_offset:35235*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35235*FLEN/8, x3, x1, x4) + +inst_11780: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x401; +op3val:0x7c01; valaddr_reg:x2; val_offset:35238*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35238*FLEN/8, x3, x1, x4) + +inst_11781: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x401; +op3val:0xfd55; valaddr_reg:x2; val_offset:35241*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35241*FLEN/8, x3, x1, x4) + +inst_11782: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x401; +op3val:0x3c00; valaddr_reg:x2; val_offset:35244*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35244*FLEN/8, x3, x1, x4) + +inst_11783: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x401; +op3val:0xbc00; valaddr_reg:x2; val_offset:35247*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35247*FLEN/8, x3, x1, x4) + +inst_11784: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8455; +op3val:0x0; valaddr_reg:x2; val_offset:35250*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35250*FLEN/8, x3, x1, x4) + +inst_11785: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8455; +op3val:0x8000; valaddr_reg:x2; val_offset:35253*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35253*FLEN/8, x3, x1, x4) + +inst_11786: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8455; +op3val:0x1; valaddr_reg:x2; val_offset:35256*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35256*FLEN/8, x3, x1, x4) + +inst_11787: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8455; +op3val:0x8001; valaddr_reg:x2; val_offset:35259*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35259*FLEN/8, x3, x1, x4) + +inst_11788: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8455; +op3val:0x2; valaddr_reg:x2; val_offset:35262*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35262*FLEN/8, x3, x1, x4) + +inst_11789: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8455; +op3val:0x83fe; valaddr_reg:x2; val_offset:35265*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35265*FLEN/8, x3, x1, x4) + +inst_11790: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8455; +op3val:0x3ff; valaddr_reg:x2; val_offset:35268*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35268*FLEN/8, x3, x1, x4) + +inst_11791: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8455; +op3val:0x83ff; valaddr_reg:x2; val_offset:35271*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35271*FLEN/8, x3, x1, x4) + +inst_11792: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8455; +op3val:0x400; valaddr_reg:x2; val_offset:35274*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35274*FLEN/8, x3, x1, x4) + +inst_11793: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8455; +op3val:0x8400; valaddr_reg:x2; val_offset:35277*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35277*FLEN/8, x3, x1, x4) + +inst_11794: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8455; +op3val:0x401; valaddr_reg:x2; val_offset:35280*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35280*FLEN/8, x3, x1, x4) + +inst_11795: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8455; +op3val:0x8455; valaddr_reg:x2; val_offset:35283*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35283*FLEN/8, x3, x1, x4) + +inst_11796: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8455; +op3val:0x7bff; valaddr_reg:x2; val_offset:35286*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35286*FLEN/8, x3, x1, x4) + +inst_11797: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8455; +op3val:0xfbff; valaddr_reg:x2; val_offset:35289*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35289*FLEN/8, x3, x1, x4) + +inst_11798: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8455; +op3val:0x7c00; valaddr_reg:x2; val_offset:35292*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35292*FLEN/8, x3, x1, x4) + +inst_11799: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8455; +op3val:0xfc00; valaddr_reg:x2; val_offset:35295*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35295*FLEN/8, x3, x1, x4) + +inst_11800: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8455; +op3val:0x7e00; valaddr_reg:x2; val_offset:35298*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35298*FLEN/8, x3, x1, x4) + +inst_11801: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8455; +op3val:0xfe00; valaddr_reg:x2; val_offset:35301*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35301*FLEN/8, x3, x1, x4) + +inst_11802: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8455; +op3val:0x7e01; valaddr_reg:x2; val_offset:35304*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35304*FLEN/8, x3, x1, x4) + +inst_11803: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8455; +op3val:0xfe55; valaddr_reg:x2; val_offset:35307*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35307*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_93) + +inst_11804: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8455; +op3val:0x7c01; valaddr_reg:x2; val_offset:35310*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35310*FLEN/8, x3, x1, x4) + +inst_11805: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8455; +op3val:0xfd55; valaddr_reg:x2; val_offset:35313*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35313*FLEN/8, x3, x1, x4) + +inst_11806: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8455; +op3val:0x3c00; valaddr_reg:x2; val_offset:35316*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35316*FLEN/8, x3, x1, x4) + +inst_11807: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x8455; +op3val:0xbc00; valaddr_reg:x2; val_offset:35319*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35319*FLEN/8, x3, x1, x4) + +inst_11808: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7bff; +op3val:0x0; valaddr_reg:x2; val_offset:35322*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35322*FLEN/8, x3, x1, x4) + +inst_11809: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7bff; +op3val:0x8000; valaddr_reg:x2; val_offset:35325*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35325*FLEN/8, x3, x1, x4) + +inst_11810: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7bff; +op3val:0x1; valaddr_reg:x2; val_offset:35328*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35328*FLEN/8, x3, x1, x4) + +inst_11811: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7bff; +op3val:0x8001; valaddr_reg:x2; val_offset:35331*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35331*FLEN/8, x3, x1, x4) + +inst_11812: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7bff; +op3val:0x2; valaddr_reg:x2; val_offset:35334*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35334*FLEN/8, x3, x1, x4) + +inst_11813: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7bff; +op3val:0x83fe; valaddr_reg:x2; val_offset:35337*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35337*FLEN/8, x3, x1, x4) + +inst_11814: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7bff; +op3val:0x3ff; valaddr_reg:x2; val_offset:35340*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35340*FLEN/8, x3, x1, x4) + +inst_11815: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7bff; +op3val:0x83ff; valaddr_reg:x2; val_offset:35343*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35343*FLEN/8, x3, x1, x4) + +inst_11816: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7bff; +op3val:0x400; valaddr_reg:x2; val_offset:35346*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35346*FLEN/8, x3, x1, x4) + +inst_11817: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7bff; +op3val:0x8400; valaddr_reg:x2; val_offset:35349*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35349*FLEN/8, x3, x1, x4) + +inst_11818: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7bff; +op3val:0x401; valaddr_reg:x2; val_offset:35352*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35352*FLEN/8, x3, x1, x4) + +inst_11819: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7bff; +op3val:0x8455; valaddr_reg:x2; val_offset:35355*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35355*FLEN/8, x3, x1, x4) + +inst_11820: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7bff; +op3val:0x7bff; valaddr_reg:x2; val_offset:35358*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35358*FLEN/8, x3, x1, x4) + +inst_11821: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7bff; +op3val:0xfbff; valaddr_reg:x2; val_offset:35361*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35361*FLEN/8, x3, x1, x4) + +inst_11822: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7bff; +op3val:0x7c00; valaddr_reg:x2; val_offset:35364*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35364*FLEN/8, x3, x1, x4) + +inst_11823: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7bff; +op3val:0xfc00; valaddr_reg:x2; val_offset:35367*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35367*FLEN/8, x3, x1, x4) + +inst_11824: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7bff; +op3val:0x7e00; valaddr_reg:x2; val_offset:35370*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35370*FLEN/8, x3, x1, x4) + +inst_11825: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7bff; +op3val:0xfe00; valaddr_reg:x2; val_offset:35373*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35373*FLEN/8, x3, x1, x4) + +inst_11826: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7bff; +op3val:0x7e01; valaddr_reg:x2; val_offset:35376*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35376*FLEN/8, x3, x1, x4) + +inst_11827: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7bff; +op3val:0xfe55; valaddr_reg:x2; val_offset:35379*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35379*FLEN/8, x3, x1, x4) + +inst_11828: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7bff; +op3val:0x7c01; valaddr_reg:x2; val_offset:35382*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35382*FLEN/8, x3, x1, x4) + +inst_11829: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7bff; +op3val:0xfd55; valaddr_reg:x2; val_offset:35385*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35385*FLEN/8, x3, x1, x4) + +inst_11830: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7bff; +op3val:0x3c00; valaddr_reg:x2; val_offset:35388*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35388*FLEN/8, x3, x1, x4) + +inst_11831: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7bff; +op3val:0xbc00; valaddr_reg:x2; val_offset:35391*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35391*FLEN/8, x3, x1, x4) + +inst_11832: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfbff; +op3val:0x0; valaddr_reg:x2; val_offset:35394*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35394*FLEN/8, x3, x1, x4) + +inst_11833: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfbff; +op3val:0x8000; valaddr_reg:x2; val_offset:35397*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35397*FLEN/8, x3, x1, x4) + +inst_11834: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfbff; +op3val:0x1; valaddr_reg:x2; val_offset:35400*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35400*FLEN/8, x3, x1, x4) + +inst_11835: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfbff; +op3val:0x8001; valaddr_reg:x2; val_offset:35403*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35403*FLEN/8, x3, x1, x4) + +inst_11836: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfbff; +op3val:0x2; valaddr_reg:x2; val_offset:35406*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35406*FLEN/8, x3, x1, x4) + +inst_11837: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfbff; +op3val:0x83fe; valaddr_reg:x2; val_offset:35409*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35409*FLEN/8, x3, x1, x4) + +inst_11838: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfbff; +op3val:0x3ff; valaddr_reg:x2; val_offset:35412*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35412*FLEN/8, x3, x1, x4) + +inst_11839: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfbff; +op3val:0x83ff; valaddr_reg:x2; val_offset:35415*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35415*FLEN/8, x3, x1, x4) + +inst_11840: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfbff; +op3val:0x400; valaddr_reg:x2; val_offset:35418*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35418*FLEN/8, x3, x1, x4) + +inst_11841: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfbff; +op3val:0x8400; valaddr_reg:x2; val_offset:35421*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35421*FLEN/8, x3, x1, x4) + +inst_11842: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfbff; +op3val:0x401; valaddr_reg:x2; val_offset:35424*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35424*FLEN/8, x3, x1, x4) + +inst_11843: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfbff; +op3val:0x8455; valaddr_reg:x2; val_offset:35427*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35427*FLEN/8, x3, x1, x4) + +inst_11844: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfbff; +op3val:0x7bff; valaddr_reg:x2; val_offset:35430*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35430*FLEN/8, x3, x1, x4) + +inst_11845: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfbff; +op3val:0xfbff; valaddr_reg:x2; val_offset:35433*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35433*FLEN/8, x3, x1, x4) + +inst_11846: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfbff; +op3val:0x7c00; valaddr_reg:x2; val_offset:35436*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35436*FLEN/8, x3, x1, x4) + +inst_11847: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfbff; +op3val:0xfc00; valaddr_reg:x2; val_offset:35439*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35439*FLEN/8, x3, x1, x4) + +inst_11848: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfbff; +op3val:0x7e00; valaddr_reg:x2; val_offset:35442*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35442*FLEN/8, x3, x1, x4) + +inst_11849: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfbff; +op3val:0xfe00; valaddr_reg:x2; val_offset:35445*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35445*FLEN/8, x3, x1, x4) + +inst_11850: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfbff; +op3val:0x7e01; valaddr_reg:x2; val_offset:35448*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35448*FLEN/8, x3, x1, x4) + +inst_11851: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfbff; +op3val:0xfe55; valaddr_reg:x2; val_offset:35451*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35451*FLEN/8, x3, x1, x4) + +inst_11852: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfbff; +op3val:0x7c01; valaddr_reg:x2; val_offset:35454*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35454*FLEN/8, x3, x1, x4) + +inst_11853: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfbff; +op3val:0xfd55; valaddr_reg:x2; val_offset:35457*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35457*FLEN/8, x3, x1, x4) + +inst_11854: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfbff; +op3val:0x3c00; valaddr_reg:x2; val_offset:35460*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35460*FLEN/8, x3, x1, x4) + +inst_11855: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfbff; +op3val:0xbc00; valaddr_reg:x2; val_offset:35463*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35463*FLEN/8, x3, x1, x4) + +inst_11856: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7c00; +op3val:0x0; valaddr_reg:x2; val_offset:35466*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35466*FLEN/8, x3, x1, x4) + +inst_11857: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7c00; +op3val:0x8000; valaddr_reg:x2; val_offset:35469*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35469*FLEN/8, x3, x1, x4) + +inst_11858: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7c00; +op3val:0x1; valaddr_reg:x2; val_offset:35472*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35472*FLEN/8, x3, x1, x4) + +inst_11859: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7c00; +op3val:0x8001; valaddr_reg:x2; val_offset:35475*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35475*FLEN/8, x3, x1, x4) + +inst_11860: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7c00; +op3val:0x2; valaddr_reg:x2; val_offset:35478*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35478*FLEN/8, x3, x1, x4) + +inst_11861: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7c00; +op3val:0x83fe; valaddr_reg:x2; val_offset:35481*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35481*FLEN/8, x3, x1, x4) + +inst_11862: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7c00; +op3val:0x3ff; valaddr_reg:x2; val_offset:35484*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35484*FLEN/8, x3, x1, x4) + +inst_11863: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7c00; +op3val:0x83ff; valaddr_reg:x2; val_offset:35487*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35487*FLEN/8, x3, x1, x4) + +inst_11864: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7c00; +op3val:0x400; valaddr_reg:x2; val_offset:35490*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35490*FLEN/8, x3, x1, x4) + +inst_11865: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7c00; +op3val:0x8400; valaddr_reg:x2; val_offset:35493*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35493*FLEN/8, x3, x1, x4) + +inst_11866: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7c00; +op3val:0x401; valaddr_reg:x2; val_offset:35496*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35496*FLEN/8, x3, x1, x4) + +inst_11867: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7c00; +op3val:0x8455; valaddr_reg:x2; val_offset:35499*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35499*FLEN/8, x3, x1, x4) + +inst_11868: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7c00; +op3val:0x7bff; valaddr_reg:x2; val_offset:35502*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35502*FLEN/8, x3, x1, x4) + +inst_11869: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7c00; +op3val:0xfbff; valaddr_reg:x2; val_offset:35505*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35505*FLEN/8, x3, x1, x4) + +inst_11870: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7c00; +op3val:0x7c00; valaddr_reg:x2; val_offset:35508*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35508*FLEN/8, x3, x1, x4) + +inst_11871: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7c00; +op3val:0xfc00; valaddr_reg:x2; val_offset:35511*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35511*FLEN/8, x3, x1, x4) + +inst_11872: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7c00; +op3val:0x7e00; valaddr_reg:x2; val_offset:35514*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35514*FLEN/8, x3, x1, x4) + +inst_11873: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7c00; +op3val:0xfe00; valaddr_reg:x2; val_offset:35517*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35517*FLEN/8, x3, x1, x4) + +inst_11874: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7c00; +op3val:0x7e01; valaddr_reg:x2; val_offset:35520*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35520*FLEN/8, x3, x1, x4) + +inst_11875: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7c00; +op3val:0xfe55; valaddr_reg:x2; val_offset:35523*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35523*FLEN/8, x3, x1, x4) + +inst_11876: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7c00; +op3val:0x7c01; valaddr_reg:x2; val_offset:35526*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35526*FLEN/8, x3, x1, x4) + +inst_11877: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7c00; +op3val:0xfd55; valaddr_reg:x2; val_offset:35529*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35529*FLEN/8, x3, x1, x4) + +inst_11878: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7c00; +op3val:0x3c00; valaddr_reg:x2; val_offset:35532*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35532*FLEN/8, x3, x1, x4) + +inst_11879: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7c00; +op3val:0xbc00; valaddr_reg:x2; val_offset:35535*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35535*FLEN/8, x3, x1, x4) + +inst_11880: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfc00; +op3val:0x0; valaddr_reg:x2; val_offset:35538*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35538*FLEN/8, x3, x1, x4) + +inst_11881: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfc00; +op3val:0x8000; valaddr_reg:x2; val_offset:35541*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35541*FLEN/8, x3, x1, x4) + +inst_11882: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfc00; +op3val:0x1; valaddr_reg:x2; val_offset:35544*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35544*FLEN/8, x3, x1, x4) + +inst_11883: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfc00; +op3val:0x8001; valaddr_reg:x2; val_offset:35547*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35547*FLEN/8, x3, x1, x4) + +inst_11884: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfc00; +op3val:0x2; valaddr_reg:x2; val_offset:35550*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35550*FLEN/8, x3, x1, x4) + +inst_11885: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfc00; +op3val:0x83fe; valaddr_reg:x2; val_offset:35553*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35553*FLEN/8, x3, x1, x4) + +inst_11886: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfc00; +op3val:0x3ff; valaddr_reg:x2; val_offset:35556*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35556*FLEN/8, x3, x1, x4) + +inst_11887: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfc00; +op3val:0x83ff; valaddr_reg:x2; val_offset:35559*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35559*FLEN/8, x3, x1, x4) + +inst_11888: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfc00; +op3val:0x400; valaddr_reg:x2; val_offset:35562*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35562*FLEN/8, x3, x1, x4) + +inst_11889: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfc00; +op3val:0x8400; valaddr_reg:x2; val_offset:35565*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35565*FLEN/8, x3, x1, x4) + +inst_11890: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfc00; +op3val:0x401; valaddr_reg:x2; val_offset:35568*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35568*FLEN/8, x3, x1, x4) + +inst_11891: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfc00; +op3val:0x8455; valaddr_reg:x2; val_offset:35571*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35571*FLEN/8, x3, x1, x4) + +inst_11892: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfc00; +op3val:0x7bff; valaddr_reg:x2; val_offset:35574*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35574*FLEN/8, x3, x1, x4) + +inst_11893: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfc00; +op3val:0xfbff; valaddr_reg:x2; val_offset:35577*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35577*FLEN/8, x3, x1, x4) + +inst_11894: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfc00; +op3val:0x7c00; valaddr_reg:x2; val_offset:35580*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35580*FLEN/8, x3, x1, x4) + +inst_11895: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfc00; +op3val:0xfc00; valaddr_reg:x2; val_offset:35583*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35583*FLEN/8, x3, x1, x4) + +inst_11896: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfc00; +op3val:0x7e00; valaddr_reg:x2; val_offset:35586*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35586*FLEN/8, x3, x1, x4) + +inst_11897: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfc00; +op3val:0xfe00; valaddr_reg:x2; val_offset:35589*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35589*FLEN/8, x3, x1, x4) + +inst_11898: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfc00; +op3val:0x7e01; valaddr_reg:x2; val_offset:35592*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35592*FLEN/8, x3, x1, x4) + +inst_11899: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfc00; +op3val:0xfe55; valaddr_reg:x2; val_offset:35595*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35595*FLEN/8, x3, x1, x4) + +inst_11900: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfc00; +op3val:0x7c01; valaddr_reg:x2; val_offset:35598*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35598*FLEN/8, x3, x1, x4) + +inst_11901: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfc00; +op3val:0xfd55; valaddr_reg:x2; val_offset:35601*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35601*FLEN/8, x3, x1, x4) + +inst_11902: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfc00; +op3val:0x3c00; valaddr_reg:x2; val_offset:35604*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35604*FLEN/8, x3, x1, x4) + +inst_11903: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfc00; +op3val:0xbc00; valaddr_reg:x2; val_offset:35607*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35607*FLEN/8, x3, x1, x4) + +inst_11904: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7e00; +op3val:0x0; valaddr_reg:x2; val_offset:35610*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35610*FLEN/8, x3, x1, x4) + +inst_11905: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7e00; +op3val:0x8000; valaddr_reg:x2; val_offset:35613*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35613*FLEN/8, x3, x1, x4) + +inst_11906: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7e00; +op3val:0x1; valaddr_reg:x2; val_offset:35616*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35616*FLEN/8, x3, x1, x4) + +inst_11907: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7e00; +op3val:0x8001; valaddr_reg:x2; val_offset:35619*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35619*FLEN/8, x3, x1, x4) + +inst_11908: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7e00; +op3val:0x2; valaddr_reg:x2; val_offset:35622*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35622*FLEN/8, x3, x1, x4) + +inst_11909: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7e00; +op3val:0x83fe; valaddr_reg:x2; val_offset:35625*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35625*FLEN/8, x3, x1, x4) + +inst_11910: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7e00; +op3val:0x3ff; valaddr_reg:x2; val_offset:35628*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35628*FLEN/8, x3, x1, x4) + +inst_11911: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7e00; +op3val:0x83ff; valaddr_reg:x2; val_offset:35631*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35631*FLEN/8, x3, x1, x4) + +inst_11912: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7e00; +op3val:0x400; valaddr_reg:x2; val_offset:35634*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35634*FLEN/8, x3, x1, x4) + +inst_11913: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7e00; +op3val:0x8400; valaddr_reg:x2; val_offset:35637*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35637*FLEN/8, x3, x1, x4) + +inst_11914: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7e00; +op3val:0x401; valaddr_reg:x2; val_offset:35640*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35640*FLEN/8, x3, x1, x4) + +inst_11915: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7e00; +op3val:0x8455; valaddr_reg:x2; val_offset:35643*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35643*FLEN/8, x3, x1, x4) + +inst_11916: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7e00; +op3val:0x7bff; valaddr_reg:x2; val_offset:35646*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35646*FLEN/8, x3, x1, x4) + +inst_11917: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7e00; +op3val:0xfbff; valaddr_reg:x2; val_offset:35649*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35649*FLEN/8, x3, x1, x4) + +inst_11918: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7e00; +op3val:0x7c00; valaddr_reg:x2; val_offset:35652*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35652*FLEN/8, x3, x1, x4) + +inst_11919: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7e00; +op3val:0xfc00; valaddr_reg:x2; val_offset:35655*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35655*FLEN/8, x3, x1, x4) + +inst_11920: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7e00; +op3val:0x7e00; valaddr_reg:x2; val_offset:35658*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35658*FLEN/8, x3, x1, x4) + +inst_11921: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7e00; +op3val:0xfe00; valaddr_reg:x2; val_offset:35661*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35661*FLEN/8, x3, x1, x4) + +inst_11922: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7e00; +op3val:0x7e01; valaddr_reg:x2; val_offset:35664*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35664*FLEN/8, x3, x1, x4) + +inst_11923: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7e00; +op3val:0xfe55; valaddr_reg:x2; val_offset:35667*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35667*FLEN/8, x3, x1, x4) + +inst_11924: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7e00; +op3val:0x7c01; valaddr_reg:x2; val_offset:35670*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35670*FLEN/8, x3, x1, x4) + +inst_11925: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7e00; +op3val:0xfd55; valaddr_reg:x2; val_offset:35673*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35673*FLEN/8, x3, x1, x4) + +inst_11926: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7e00; +op3val:0x3c00; valaddr_reg:x2; val_offset:35676*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35676*FLEN/8, x3, x1, x4) + +inst_11927: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7e00; +op3val:0xbc00; valaddr_reg:x2; val_offset:35679*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35679*FLEN/8, x3, x1, x4) + +inst_11928: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfe00; +op3val:0x0; valaddr_reg:x2; val_offset:35682*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35682*FLEN/8, x3, x1, x4) + +inst_11929: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfe00; +op3val:0x8000; valaddr_reg:x2; val_offset:35685*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35685*FLEN/8, x3, x1, x4) + +inst_11930: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfe00; +op3val:0x1; valaddr_reg:x2; val_offset:35688*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35688*FLEN/8, x3, x1, x4) + +inst_11931: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfe00; +op3val:0x8001; valaddr_reg:x2; val_offset:35691*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35691*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_94) + +inst_11932: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfe00; +op3val:0x2; valaddr_reg:x2; val_offset:35694*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35694*FLEN/8, x3, x1, x4) + +inst_11933: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfe00; +op3val:0x83fe; valaddr_reg:x2; val_offset:35697*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35697*FLEN/8, x3, x1, x4) + +inst_11934: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfe00; +op3val:0x3ff; valaddr_reg:x2; val_offset:35700*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35700*FLEN/8, x3, x1, x4) + +inst_11935: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfe00; +op3val:0x83ff; valaddr_reg:x2; val_offset:35703*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35703*FLEN/8, x3, x1, x4) + +inst_11936: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfe00; +op3val:0x400; valaddr_reg:x2; val_offset:35706*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35706*FLEN/8, x3, x1, x4) + +inst_11937: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfe00; +op3val:0x8400; valaddr_reg:x2; val_offset:35709*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35709*FLEN/8, x3, x1, x4) + +inst_11938: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfe00; +op3val:0x401; valaddr_reg:x2; val_offset:35712*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35712*FLEN/8, x3, x1, x4) + +inst_11939: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfe00; +op3val:0x8455; valaddr_reg:x2; val_offset:35715*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35715*FLEN/8, x3, x1, x4) + +inst_11940: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfe00; +op3val:0x7bff; valaddr_reg:x2; val_offset:35718*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35718*FLEN/8, x3, x1, x4) + +inst_11941: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfe00; +op3val:0xfbff; valaddr_reg:x2; val_offset:35721*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35721*FLEN/8, x3, x1, x4) + +inst_11942: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfe00; +op3val:0x7c00; valaddr_reg:x2; val_offset:35724*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35724*FLEN/8, x3, x1, x4) + +inst_11943: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfe00; +op3val:0xfc00; valaddr_reg:x2; val_offset:35727*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35727*FLEN/8, x3, x1, x4) + +inst_11944: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfe00; +op3val:0x7e00; valaddr_reg:x2; val_offset:35730*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35730*FLEN/8, x3, x1, x4) + +inst_11945: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfe00; +op3val:0xfe00; valaddr_reg:x2; val_offset:35733*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35733*FLEN/8, x3, x1, x4) + +inst_11946: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfe00; +op3val:0x7e01; valaddr_reg:x2; val_offset:35736*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35736*FLEN/8, x3, x1, x4) + +inst_11947: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfe00; +op3val:0xfe55; valaddr_reg:x2; val_offset:35739*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35739*FLEN/8, x3, x1, x4) + +inst_11948: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfe00; +op3val:0x7c01; valaddr_reg:x2; val_offset:35742*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35742*FLEN/8, x3, x1, x4) + +inst_11949: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfe00; +op3val:0xfd55; valaddr_reg:x2; val_offset:35745*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35745*FLEN/8, x3, x1, x4) + +inst_11950: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfe00; +op3val:0x3c00; valaddr_reg:x2; val_offset:35748*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35748*FLEN/8, x3, x1, x4) + +inst_11951: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfe00; +op3val:0xbc00; valaddr_reg:x2; val_offset:35751*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35751*FLEN/8, x3, x1, x4) + +inst_11952: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7e01; +op3val:0x0; valaddr_reg:x2; val_offset:35754*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35754*FLEN/8, x3, x1, x4) + +inst_11953: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7e01; +op3val:0x8000; valaddr_reg:x2; val_offset:35757*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35757*FLEN/8, x3, x1, x4) + +inst_11954: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7e01; +op3val:0x1; valaddr_reg:x2; val_offset:35760*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35760*FLEN/8, x3, x1, x4) + +inst_11955: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7e01; +op3val:0x8001; valaddr_reg:x2; val_offset:35763*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35763*FLEN/8, x3, x1, x4) + +inst_11956: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7e01; +op3val:0x2; valaddr_reg:x2; val_offset:35766*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35766*FLEN/8, x3, x1, x4) + +inst_11957: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7e01; +op3val:0x83fe; valaddr_reg:x2; val_offset:35769*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35769*FLEN/8, x3, x1, x4) + +inst_11958: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7e01; +op3val:0x3ff; valaddr_reg:x2; val_offset:35772*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35772*FLEN/8, x3, x1, x4) + +inst_11959: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7e01; +op3val:0x83ff; valaddr_reg:x2; val_offset:35775*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35775*FLEN/8, x3, x1, x4) + +inst_11960: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7e01; +op3val:0x400; valaddr_reg:x2; val_offset:35778*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35778*FLEN/8, x3, x1, x4) + +inst_11961: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7e01; +op3val:0x8400; valaddr_reg:x2; val_offset:35781*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35781*FLEN/8, x3, x1, x4) + +inst_11962: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7e01; +op3val:0x401; valaddr_reg:x2; val_offset:35784*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35784*FLEN/8, x3, x1, x4) + +inst_11963: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7e01; +op3val:0x8455; valaddr_reg:x2; val_offset:35787*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35787*FLEN/8, x3, x1, x4) + +inst_11964: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7e01; +op3val:0x7bff; valaddr_reg:x2; val_offset:35790*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35790*FLEN/8, x3, x1, x4) + +inst_11965: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7e01; +op3val:0xfbff; valaddr_reg:x2; val_offset:35793*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35793*FLEN/8, x3, x1, x4) + +inst_11966: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7e01; +op3val:0x7c00; valaddr_reg:x2; val_offset:35796*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35796*FLEN/8, x3, x1, x4) + +inst_11967: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7e01; +op3val:0xfc00; valaddr_reg:x2; val_offset:35799*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35799*FLEN/8, x3, x1, x4) + +inst_11968: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7e01; +op3val:0x7e00; valaddr_reg:x2; val_offset:35802*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35802*FLEN/8, x3, x1, x4) + +inst_11969: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7e01; +op3val:0xfe00; valaddr_reg:x2; val_offset:35805*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35805*FLEN/8, x3, x1, x4) + +inst_11970: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7e01; +op3val:0x7e01; valaddr_reg:x2; val_offset:35808*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35808*FLEN/8, x3, x1, x4) + +inst_11971: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7e01; +op3val:0xfe55; valaddr_reg:x2; val_offset:35811*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35811*FLEN/8, x3, x1, x4) + +inst_11972: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7e01; +op3val:0x7c01; valaddr_reg:x2; val_offset:35814*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35814*FLEN/8, x3, x1, x4) + +inst_11973: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7e01; +op3val:0xfd55; valaddr_reg:x2; val_offset:35817*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35817*FLEN/8, x3, x1, x4) + +inst_11974: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7e01; +op3val:0x3c00; valaddr_reg:x2; val_offset:35820*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35820*FLEN/8, x3, x1, x4) + +inst_11975: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7e01; +op3val:0xbc00; valaddr_reg:x2; val_offset:35823*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35823*FLEN/8, x3, x1, x4) + +inst_11976: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfe55; +op3val:0x0; valaddr_reg:x2; val_offset:35826*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35826*FLEN/8, x3, x1, x4) + +inst_11977: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfe55; +op3val:0x8000; valaddr_reg:x2; val_offset:35829*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35829*FLEN/8, x3, x1, x4) + +inst_11978: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfe55; +op3val:0x1; valaddr_reg:x2; val_offset:35832*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35832*FLEN/8, x3, x1, x4) + +inst_11979: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfe55; +op3val:0x8001; valaddr_reg:x2; val_offset:35835*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35835*FLEN/8, x3, x1, x4) + +inst_11980: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfe55; +op3val:0x2; valaddr_reg:x2; val_offset:35838*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35838*FLEN/8, x3, x1, x4) + +inst_11981: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfe55; +op3val:0x83fe; valaddr_reg:x2; val_offset:35841*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35841*FLEN/8, x3, x1, x4) + +inst_11982: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfe55; +op3val:0x3ff; valaddr_reg:x2; val_offset:35844*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35844*FLEN/8, x3, x1, x4) + +inst_11983: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfe55; +op3val:0x83ff; valaddr_reg:x2; val_offset:35847*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35847*FLEN/8, x3, x1, x4) + +inst_11984: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfe55; +op3val:0x400; valaddr_reg:x2; val_offset:35850*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35850*FLEN/8, x3, x1, x4) + +inst_11985: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfe55; +op3val:0x8400; valaddr_reg:x2; val_offset:35853*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35853*FLEN/8, x3, x1, x4) + +inst_11986: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfe55; +op3val:0x401; valaddr_reg:x2; val_offset:35856*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35856*FLEN/8, x3, x1, x4) + +inst_11987: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfe55; +op3val:0x8455; valaddr_reg:x2; val_offset:35859*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35859*FLEN/8, x3, x1, x4) + +inst_11988: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfe55; +op3val:0x7bff; valaddr_reg:x2; val_offset:35862*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35862*FLEN/8, x3, x1, x4) + +inst_11989: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfe55; +op3val:0xfbff; valaddr_reg:x2; val_offset:35865*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35865*FLEN/8, x3, x1, x4) + +inst_11990: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfe55; +op3val:0x7c00; valaddr_reg:x2; val_offset:35868*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35868*FLEN/8, x3, x1, x4) + +inst_11991: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfe55; +op3val:0xfc00; valaddr_reg:x2; val_offset:35871*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35871*FLEN/8, x3, x1, x4) + +inst_11992: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfe55; +op3val:0x7e00; valaddr_reg:x2; val_offset:35874*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35874*FLEN/8, x3, x1, x4) + +inst_11993: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfe55; +op3val:0xfe00; valaddr_reg:x2; val_offset:35877*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35877*FLEN/8, x3, x1, x4) + +inst_11994: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfe55; +op3val:0x7e01; valaddr_reg:x2; val_offset:35880*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35880*FLEN/8, x3, x1, x4) + +inst_11995: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfe55; +op3val:0xfe55; valaddr_reg:x2; val_offset:35883*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35883*FLEN/8, x3, x1, x4) + +inst_11996: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfe55; +op3val:0x7c01; valaddr_reg:x2; val_offset:35886*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35886*FLEN/8, x3, x1, x4) + +inst_11997: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfe55; +op3val:0xfd55; valaddr_reg:x2; val_offset:35889*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35889*FLEN/8, x3, x1, x4) + +inst_11998: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfe55; +op3val:0x3c00; valaddr_reg:x2; val_offset:35892*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35892*FLEN/8, x3, x1, x4) + +inst_11999: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfe55; +op3val:0xbc00; valaddr_reg:x2; val_offset:35895*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35895*FLEN/8, x3, x1, x4) + +inst_12000: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7c01; +op3val:0x0; valaddr_reg:x2; val_offset:35898*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35898*FLEN/8, x3, x1, x4) + +inst_12001: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7c01; +op3val:0x8000; valaddr_reg:x2; val_offset:35901*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35901*FLEN/8, x3, x1, x4) + +inst_12002: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7c01; +op3val:0x1; valaddr_reg:x2; val_offset:35904*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35904*FLEN/8, x3, x1, x4) + +inst_12003: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7c01; +op3val:0x8001; valaddr_reg:x2; val_offset:35907*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35907*FLEN/8, x3, x1, x4) + +inst_12004: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7c01; +op3val:0x2; valaddr_reg:x2; val_offset:35910*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35910*FLEN/8, x3, x1, x4) + +inst_12005: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7c01; +op3val:0x83fe; valaddr_reg:x2; val_offset:35913*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35913*FLEN/8, x3, x1, x4) + +inst_12006: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7c01; +op3val:0x3ff; valaddr_reg:x2; val_offset:35916*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35916*FLEN/8, x3, x1, x4) + +inst_12007: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7c01; +op3val:0x83ff; valaddr_reg:x2; val_offset:35919*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35919*FLEN/8, x3, x1, x4) + +inst_12008: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7c01; +op3val:0x400; valaddr_reg:x2; val_offset:35922*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35922*FLEN/8, x3, x1, x4) + +inst_12009: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7c01; +op3val:0x8400; valaddr_reg:x2; val_offset:35925*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35925*FLEN/8, x3, x1, x4) + +inst_12010: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7c01; +op3val:0x401; valaddr_reg:x2; val_offset:35928*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35928*FLEN/8, x3, x1, x4) + +inst_12011: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7c01; +op3val:0x8455; valaddr_reg:x2; val_offset:35931*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35931*FLEN/8, x3, x1, x4) + +inst_12012: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7c01; +op3val:0x7bff; valaddr_reg:x2; val_offset:35934*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35934*FLEN/8, x3, x1, x4) + +inst_12013: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7c01; +op3val:0xfbff; valaddr_reg:x2; val_offset:35937*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35937*FLEN/8, x3, x1, x4) + +inst_12014: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7c01; +op3val:0x7c00; valaddr_reg:x2; val_offset:35940*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35940*FLEN/8, x3, x1, x4) + +inst_12015: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7c01; +op3val:0xfc00; valaddr_reg:x2; val_offset:35943*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35943*FLEN/8, x3, x1, x4) + +inst_12016: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7c01; +op3val:0x7e00; valaddr_reg:x2; val_offset:35946*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35946*FLEN/8, x3, x1, x4) + +inst_12017: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7c01; +op3val:0xfe00; valaddr_reg:x2; val_offset:35949*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35949*FLEN/8, x3, x1, x4) + +inst_12018: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7c01; +op3val:0x7e01; valaddr_reg:x2; val_offset:35952*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35952*FLEN/8, x3, x1, x4) + +inst_12019: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7c01; +op3val:0xfe55; valaddr_reg:x2; val_offset:35955*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35955*FLEN/8, x3, x1, x4) + +inst_12020: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7c01; +op3val:0x7c01; valaddr_reg:x2; val_offset:35958*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35958*FLEN/8, x3, x1, x4) + +inst_12021: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7c01; +op3val:0xfd55; valaddr_reg:x2; val_offset:35961*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35961*FLEN/8, x3, x1, x4) + +inst_12022: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7c01; +op3val:0x3c00; valaddr_reg:x2; val_offset:35964*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35964*FLEN/8, x3, x1, x4) + +inst_12023: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x7c01; +op3val:0xbc00; valaddr_reg:x2; val_offset:35967*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35967*FLEN/8, x3, x1, x4) + +inst_12024: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfd55; +op3val:0x0; valaddr_reg:x2; val_offset:35970*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35970*FLEN/8, x3, x1, x4) + +inst_12025: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfd55; +op3val:0x8000; valaddr_reg:x2; val_offset:35973*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35973*FLEN/8, x3, x1, x4) + +inst_12026: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfd55; +op3val:0x1; valaddr_reg:x2; val_offset:35976*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35976*FLEN/8, x3, x1, x4) + +inst_12027: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfd55; +op3val:0x8001; valaddr_reg:x2; val_offset:35979*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35979*FLEN/8, x3, x1, x4) + +inst_12028: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfd55; +op3val:0x2; valaddr_reg:x2; val_offset:35982*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35982*FLEN/8, x3, x1, x4) + +inst_12029: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfd55; +op3val:0x83fe; valaddr_reg:x2; val_offset:35985*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35985*FLEN/8, x3, x1, x4) + +inst_12030: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfd55; +op3val:0x3ff; valaddr_reg:x2; val_offset:35988*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35988*FLEN/8, x3, x1, x4) + +inst_12031: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfd55; +op3val:0x83ff; valaddr_reg:x2; val_offset:35991*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35991*FLEN/8, x3, x1, x4) + +inst_12032: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfd55; +op3val:0x400; valaddr_reg:x2; val_offset:35994*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35994*FLEN/8, x3, x1, x4) + +inst_12033: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfd55; +op3val:0x8400; valaddr_reg:x2; val_offset:35997*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 35997*FLEN/8, x3, x1, x4) + +inst_12034: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfd55; +op3val:0x401; valaddr_reg:x2; val_offset:36000*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36000*FLEN/8, x3, x1, x4) + +inst_12035: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfd55; +op3val:0x8455; valaddr_reg:x2; val_offset:36003*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36003*FLEN/8, x3, x1, x4) + +inst_12036: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfd55; +op3val:0x7bff; valaddr_reg:x2; val_offset:36006*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36006*FLEN/8, x3, x1, x4) + +inst_12037: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfd55; +op3val:0xfbff; valaddr_reg:x2; val_offset:36009*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36009*FLEN/8, x3, x1, x4) + +inst_12038: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfd55; +op3val:0x7c00; valaddr_reg:x2; val_offset:36012*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36012*FLEN/8, x3, x1, x4) + +inst_12039: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfd55; +op3val:0xfc00; valaddr_reg:x2; val_offset:36015*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36015*FLEN/8, x3, x1, x4) + +inst_12040: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfd55; +op3val:0x7e00; valaddr_reg:x2; val_offset:36018*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36018*FLEN/8, x3, x1, x4) + +inst_12041: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfd55; +op3val:0xfe00; valaddr_reg:x2; val_offset:36021*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36021*FLEN/8, x3, x1, x4) + +inst_12042: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfd55; +op3val:0x7e01; valaddr_reg:x2; val_offset:36024*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36024*FLEN/8, x3, x1, x4) + +inst_12043: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfd55; +op3val:0xfe55; valaddr_reg:x2; val_offset:36027*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36027*FLEN/8, x3, x1, x4) + +inst_12044: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfd55; +op3val:0x7c01; valaddr_reg:x2; val_offset:36030*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36030*FLEN/8, x3, x1, x4) + +inst_12045: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfd55; +op3val:0xfd55; valaddr_reg:x2; val_offset:36033*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36033*FLEN/8, x3, x1, x4) + +inst_12046: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfd55; +op3val:0x3c00; valaddr_reg:x2; val_offset:36036*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36036*FLEN/8, x3, x1, x4) + +inst_12047: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xfd55; +op3val:0xbc00; valaddr_reg:x2; val_offset:36039*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36039*FLEN/8, x3, x1, x4) + +inst_12048: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x3c00; +op3val:0x0; valaddr_reg:x2; val_offset:36042*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36042*FLEN/8, x3, x1, x4) + +inst_12049: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x3c00; +op3val:0x8000; valaddr_reg:x2; val_offset:36045*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36045*FLEN/8, x3, x1, x4) + +inst_12050: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x3c00; +op3val:0x1; valaddr_reg:x2; val_offset:36048*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36048*FLEN/8, x3, x1, x4) + +inst_12051: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x3c00; +op3val:0x8001; valaddr_reg:x2; val_offset:36051*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36051*FLEN/8, x3, x1, x4) + +inst_12052: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x3c00; +op3val:0x2; valaddr_reg:x2; val_offset:36054*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36054*FLEN/8, x3, x1, x4) + +inst_12053: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x3c00; +op3val:0x83fe; valaddr_reg:x2; val_offset:36057*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36057*FLEN/8, x3, x1, x4) + +inst_12054: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x3c00; +op3val:0x3ff; valaddr_reg:x2; val_offset:36060*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36060*FLEN/8, x3, x1, x4) + +inst_12055: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x3c00; +op3val:0x83ff; valaddr_reg:x2; val_offset:36063*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36063*FLEN/8, x3, x1, x4) + +inst_12056: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x3c00; +op3val:0x400; valaddr_reg:x2; val_offset:36066*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36066*FLEN/8, x3, x1, x4) + +inst_12057: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x3c00; +op3val:0x8400; valaddr_reg:x2; val_offset:36069*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36069*FLEN/8, x3, x1, x4) + +inst_12058: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x3c00; +op3val:0x401; valaddr_reg:x2; val_offset:36072*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36072*FLEN/8, x3, x1, x4) + +inst_12059: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x3c00; +op3val:0x8455; valaddr_reg:x2; val_offset:36075*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36075*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_95) + +inst_12060: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x3c00; +op3val:0x7bff; valaddr_reg:x2; val_offset:36078*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36078*FLEN/8, x3, x1, x4) + +inst_12061: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x3c00; +op3val:0xfbff; valaddr_reg:x2; val_offset:36081*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36081*FLEN/8, x3, x1, x4) + +inst_12062: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x3c00; +op3val:0x7c00; valaddr_reg:x2; val_offset:36084*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36084*FLEN/8, x3, x1, x4) + +inst_12063: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x3c00; +op3val:0xfc00; valaddr_reg:x2; val_offset:36087*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36087*FLEN/8, x3, x1, x4) + +inst_12064: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x3c00; +op3val:0x7e00; valaddr_reg:x2; val_offset:36090*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36090*FLEN/8, x3, x1, x4) + +inst_12065: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x3c00; +op3val:0xfe00; valaddr_reg:x2; val_offset:36093*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36093*FLEN/8, x3, x1, x4) + +inst_12066: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x3c00; +op3val:0x7e01; valaddr_reg:x2; val_offset:36096*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36096*FLEN/8, x3, x1, x4) + +inst_12067: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x3c00; +op3val:0xfe55; valaddr_reg:x2; val_offset:36099*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36099*FLEN/8, x3, x1, x4) + +inst_12068: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x3c00; +op3val:0x7c01; valaddr_reg:x2; val_offset:36102*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36102*FLEN/8, x3, x1, x4) + +inst_12069: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x3c00; +op3val:0xfd55; valaddr_reg:x2; val_offset:36105*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36105*FLEN/8, x3, x1, x4) + +inst_12070: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x3c00; +op3val:0x3c00; valaddr_reg:x2; val_offset:36108*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36108*FLEN/8, x3, x1, x4) + +inst_12071: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0x3c00; +op3val:0xbc00; valaddr_reg:x2; val_offset:36111*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36111*FLEN/8, x3, x1, x4) + +inst_12072: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xbc00; +op3val:0x0; valaddr_reg:x2; val_offset:36114*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36114*FLEN/8, x3, x1, x4) + +inst_12073: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xbc00; +op3val:0x8000; valaddr_reg:x2; val_offset:36117*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36117*FLEN/8, x3, x1, x4) + +inst_12074: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xbc00; +op3val:0x1; valaddr_reg:x2; val_offset:36120*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36120*FLEN/8, x3, x1, x4) + +inst_12075: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xbc00; +op3val:0x8001; valaddr_reg:x2; val_offset:36123*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36123*FLEN/8, x3, x1, x4) + +inst_12076: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xbc00; +op3val:0x2; valaddr_reg:x2; val_offset:36126*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36126*FLEN/8, x3, x1, x4) + +inst_12077: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xbc00; +op3val:0x83fe; valaddr_reg:x2; val_offset:36129*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36129*FLEN/8, x3, x1, x4) + +inst_12078: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xbc00; +op3val:0x3ff; valaddr_reg:x2; val_offset:36132*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36132*FLEN/8, x3, x1, x4) + +inst_12079: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xbc00; +op3val:0x83ff; valaddr_reg:x2; val_offset:36135*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36135*FLEN/8, x3, x1, x4) + +inst_12080: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xbc00; +op3val:0x400; valaddr_reg:x2; val_offset:36138*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36138*FLEN/8, x3, x1, x4) + +inst_12081: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xbc00; +op3val:0x8400; valaddr_reg:x2; val_offset:36141*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36141*FLEN/8, x3, x1, x4) + +inst_12082: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xbc00; +op3val:0x401; valaddr_reg:x2; val_offset:36144*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36144*FLEN/8, x3, x1, x4) + +inst_12083: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xbc00; +op3val:0x8455; valaddr_reg:x2; val_offset:36147*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36147*FLEN/8, x3, x1, x4) + +inst_12084: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xbc00; +op3val:0x7bff; valaddr_reg:x2; val_offset:36150*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36150*FLEN/8, x3, x1, x4) + +inst_12085: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xbc00; +op3val:0xfbff; valaddr_reg:x2; val_offset:36153*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36153*FLEN/8, x3, x1, x4) + +inst_12086: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xbc00; +op3val:0x7c00; valaddr_reg:x2; val_offset:36156*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36156*FLEN/8, x3, x1, x4) + +inst_12087: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xbc00; +op3val:0xfc00; valaddr_reg:x2; val_offset:36159*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36159*FLEN/8, x3, x1, x4) + +inst_12088: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xbc00; +op3val:0x7e00; valaddr_reg:x2; val_offset:36162*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36162*FLEN/8, x3, x1, x4) + +inst_12089: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xbc00; +op3val:0xfe00; valaddr_reg:x2; val_offset:36165*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36165*FLEN/8, x3, x1, x4) + +inst_12090: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xbc00; +op3val:0x7e01; valaddr_reg:x2; val_offset:36168*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36168*FLEN/8, x3, x1, x4) + +inst_12091: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xbc00; +op3val:0xfe55; valaddr_reg:x2; val_offset:36171*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36171*FLEN/8, x3, x1, x4) + +inst_12092: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xbc00; +op3val:0x7c01; valaddr_reg:x2; val_offset:36174*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36174*FLEN/8, x3, x1, x4) + +inst_12093: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xbc00; +op3val:0xfd55; valaddr_reg:x2; val_offset:36177*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36177*FLEN/8, x3, x1, x4) + +inst_12094: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xbc00; +op3val:0x3c00; valaddr_reg:x2; val_offset:36180*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36180*FLEN/8, x3, x1, x4) + +inst_12095: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c01; op2val:0xbc00; +op3val:0xbc00; valaddr_reg:x2; val_offset:36183*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36183*FLEN/8, x3, x1, x4) + +inst_12096: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x0; +op3val:0x0; valaddr_reg:x2; val_offset:36186*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36186*FLEN/8, x3, x1, x4) + +inst_12097: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x0; +op3val:0x8000; valaddr_reg:x2; val_offset:36189*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36189*FLEN/8, x3, x1, x4) + +inst_12098: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x0; +op3val:0x1; valaddr_reg:x2; val_offset:36192*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36192*FLEN/8, x3, x1, x4) + +inst_12099: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x0; +op3val:0x8001; valaddr_reg:x2; val_offset:36195*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36195*FLEN/8, x3, x1, x4) + +inst_12100: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x0; +op3val:0x2; valaddr_reg:x2; val_offset:36198*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36198*FLEN/8, x3, x1, x4) + +inst_12101: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x0; +op3val:0x83fe; valaddr_reg:x2; val_offset:36201*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36201*FLEN/8, x3, x1, x4) + +inst_12102: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x0; +op3val:0x3ff; valaddr_reg:x2; val_offset:36204*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36204*FLEN/8, x3, x1, x4) + +inst_12103: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x0; +op3val:0x83ff; valaddr_reg:x2; val_offset:36207*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36207*FLEN/8, x3, x1, x4) + +inst_12104: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x0; +op3val:0x400; valaddr_reg:x2; val_offset:36210*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36210*FLEN/8, x3, x1, x4) + +inst_12105: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x0; +op3val:0x8400; valaddr_reg:x2; val_offset:36213*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36213*FLEN/8, x3, x1, x4) + +inst_12106: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x0; +op3val:0x401; valaddr_reg:x2; val_offset:36216*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36216*FLEN/8, x3, x1, x4) + +inst_12107: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x0; +op3val:0x8455; valaddr_reg:x2; val_offset:36219*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36219*FLEN/8, x3, x1, x4) + +inst_12108: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x0; +op3val:0x7bff; valaddr_reg:x2; val_offset:36222*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36222*FLEN/8, x3, x1, x4) + +inst_12109: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x0; +op3val:0xfbff; valaddr_reg:x2; val_offset:36225*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36225*FLEN/8, x3, x1, x4) + +inst_12110: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x0; +op3val:0x7c00; valaddr_reg:x2; val_offset:36228*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36228*FLEN/8, x3, x1, x4) + +inst_12111: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x0; +op3val:0xfc00; valaddr_reg:x2; val_offset:36231*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36231*FLEN/8, x3, x1, x4) + +inst_12112: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x0; +op3val:0x7e00; valaddr_reg:x2; val_offset:36234*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36234*FLEN/8, x3, x1, x4) + +inst_12113: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x0; +op3val:0xfe00; valaddr_reg:x2; val_offset:36237*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36237*FLEN/8, x3, x1, x4) + +inst_12114: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x0; +op3val:0x7e01; valaddr_reg:x2; val_offset:36240*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36240*FLEN/8, x3, x1, x4) + +inst_12115: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x0; +op3val:0xfe55; valaddr_reg:x2; val_offset:36243*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36243*FLEN/8, x3, x1, x4) + +inst_12116: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x0; +op3val:0x7c01; valaddr_reg:x2; val_offset:36246*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36246*FLEN/8, x3, x1, x4) + +inst_12117: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x0; +op3val:0xfd55; valaddr_reg:x2; val_offset:36249*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36249*FLEN/8, x3, x1, x4) + +inst_12118: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x0; +op3val:0x3c00; valaddr_reg:x2; val_offset:36252*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36252*FLEN/8, x3, x1, x4) + +inst_12119: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x0; +op3val:0xbc00; valaddr_reg:x2; val_offset:36255*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36255*FLEN/8, x3, x1, x4) + +inst_12120: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8000; +op3val:0x0; valaddr_reg:x2; val_offset:36258*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36258*FLEN/8, x3, x1, x4) + +inst_12121: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8000; +op3val:0x8000; valaddr_reg:x2; val_offset:36261*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36261*FLEN/8, x3, x1, x4) + +inst_12122: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8000; +op3val:0x1; valaddr_reg:x2; val_offset:36264*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36264*FLEN/8, x3, x1, x4) + +inst_12123: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8000; +op3val:0x8001; valaddr_reg:x2; val_offset:36267*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36267*FLEN/8, x3, x1, x4) + +inst_12124: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8000; +op3val:0x2; valaddr_reg:x2; val_offset:36270*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36270*FLEN/8, x3, x1, x4) + +inst_12125: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8000; +op3val:0x83fe; valaddr_reg:x2; val_offset:36273*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36273*FLEN/8, x3, x1, x4) + +inst_12126: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8000; +op3val:0x3ff; valaddr_reg:x2; val_offset:36276*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36276*FLEN/8, x3, x1, x4) + +inst_12127: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8000; +op3val:0x83ff; valaddr_reg:x2; val_offset:36279*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36279*FLEN/8, x3, x1, x4) + +inst_12128: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8000; +op3val:0x400; valaddr_reg:x2; val_offset:36282*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36282*FLEN/8, x3, x1, x4) + +inst_12129: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8000; +op3val:0x8400; valaddr_reg:x2; val_offset:36285*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36285*FLEN/8, x3, x1, x4) + +inst_12130: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8000; +op3val:0x401; valaddr_reg:x2; val_offset:36288*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36288*FLEN/8, x3, x1, x4) + +inst_12131: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8000; +op3val:0x8455; valaddr_reg:x2; val_offset:36291*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36291*FLEN/8, x3, x1, x4) + +inst_12132: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x2; val_offset:36294*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36294*FLEN/8, x3, x1, x4) + +inst_12133: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x2; val_offset:36297*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36297*FLEN/8, x3, x1, x4) + +inst_12134: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8000; +op3val:0x7c00; valaddr_reg:x2; val_offset:36300*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36300*FLEN/8, x3, x1, x4) + +inst_12135: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8000; +op3val:0xfc00; valaddr_reg:x2; val_offset:36303*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36303*FLEN/8, x3, x1, x4) + +inst_12136: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8000; +op3val:0x7e00; valaddr_reg:x2; val_offset:36306*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36306*FLEN/8, x3, x1, x4) + +inst_12137: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8000; +op3val:0xfe00; valaddr_reg:x2; val_offset:36309*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36309*FLEN/8, x3, x1, x4) + +inst_12138: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8000; +op3val:0x7e01; valaddr_reg:x2; val_offset:36312*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36312*FLEN/8, x3, x1, x4) + +inst_12139: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8000; +op3val:0xfe55; valaddr_reg:x2; val_offset:36315*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36315*FLEN/8, x3, x1, x4) + +inst_12140: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8000; +op3val:0x7c01; valaddr_reg:x2; val_offset:36318*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36318*FLEN/8, x3, x1, x4) + +inst_12141: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8000; +op3val:0xfd55; valaddr_reg:x2; val_offset:36321*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36321*FLEN/8, x3, x1, x4) + +inst_12142: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8000; +op3val:0x3c00; valaddr_reg:x2; val_offset:36324*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36324*FLEN/8, x3, x1, x4) + +inst_12143: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8000; +op3val:0xbc00; valaddr_reg:x2; val_offset:36327*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36327*FLEN/8, x3, x1, x4) + +inst_12144: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x1; +op3val:0x0; valaddr_reg:x2; val_offset:36330*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36330*FLEN/8, x3, x1, x4) + +inst_12145: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x1; +op3val:0x8000; valaddr_reg:x2; val_offset:36333*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36333*FLEN/8, x3, x1, x4) + +inst_12146: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x1; +op3val:0x1; valaddr_reg:x2; val_offset:36336*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36336*FLEN/8, x3, x1, x4) + +inst_12147: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x1; +op3val:0x8001; valaddr_reg:x2; val_offset:36339*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36339*FLEN/8, x3, x1, x4) + +inst_12148: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x1; +op3val:0x2; valaddr_reg:x2; val_offset:36342*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36342*FLEN/8, x3, x1, x4) + +inst_12149: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x1; +op3val:0x83fe; valaddr_reg:x2; val_offset:36345*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36345*FLEN/8, x3, x1, x4) + +inst_12150: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x1; +op3val:0x3ff; valaddr_reg:x2; val_offset:36348*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36348*FLEN/8, x3, x1, x4) + +inst_12151: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x1; +op3val:0x83ff; valaddr_reg:x2; val_offset:36351*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36351*FLEN/8, x3, x1, x4) + +inst_12152: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x1; +op3val:0x400; valaddr_reg:x2; val_offset:36354*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36354*FLEN/8, x3, x1, x4) + +inst_12153: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x1; +op3val:0x8400; valaddr_reg:x2; val_offset:36357*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36357*FLEN/8, x3, x1, x4) + +inst_12154: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x1; +op3val:0x401; valaddr_reg:x2; val_offset:36360*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36360*FLEN/8, x3, x1, x4) + +inst_12155: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x1; +op3val:0x8455; valaddr_reg:x2; val_offset:36363*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36363*FLEN/8, x3, x1, x4) + +inst_12156: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x1; +op3val:0x7bff; valaddr_reg:x2; val_offset:36366*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36366*FLEN/8, x3, x1, x4) + +inst_12157: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x1; +op3val:0xfbff; valaddr_reg:x2; val_offset:36369*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36369*FLEN/8, x3, x1, x4) + +inst_12158: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x1; +op3val:0x7c00; valaddr_reg:x2; val_offset:36372*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36372*FLEN/8, x3, x1, x4) + +inst_12159: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x1; +op3val:0xfc00; valaddr_reg:x2; val_offset:36375*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36375*FLEN/8, x3, x1, x4) + +inst_12160: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x1; +op3val:0x7e00; valaddr_reg:x2; val_offset:36378*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36378*FLEN/8, x3, x1, x4) + +inst_12161: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x1; +op3val:0xfe00; valaddr_reg:x2; val_offset:36381*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36381*FLEN/8, x3, x1, x4) + +inst_12162: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x1; +op3val:0x7e01; valaddr_reg:x2; val_offset:36384*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36384*FLEN/8, x3, x1, x4) + +inst_12163: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x1; +op3val:0xfe55; valaddr_reg:x2; val_offset:36387*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36387*FLEN/8, x3, x1, x4) + +inst_12164: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x1; +op3val:0x7c01; valaddr_reg:x2; val_offset:36390*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36390*FLEN/8, x3, x1, x4) + +inst_12165: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x1; +op3val:0xfd55; valaddr_reg:x2; val_offset:36393*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36393*FLEN/8, x3, x1, x4) + +inst_12166: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x1; +op3val:0x3c00; valaddr_reg:x2; val_offset:36396*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36396*FLEN/8, x3, x1, x4) + +inst_12167: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x1; +op3val:0xbc00; valaddr_reg:x2; val_offset:36399*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36399*FLEN/8, x3, x1, x4) + +inst_12168: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8001; +op3val:0x0; valaddr_reg:x2; val_offset:36402*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36402*FLEN/8, x3, x1, x4) + +inst_12169: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8001; +op3val:0x8000; valaddr_reg:x2; val_offset:36405*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36405*FLEN/8, x3, x1, x4) + +inst_12170: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8001; +op3val:0x1; valaddr_reg:x2; val_offset:36408*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36408*FLEN/8, x3, x1, x4) + +inst_12171: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8001; +op3val:0x8001; valaddr_reg:x2; val_offset:36411*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36411*FLEN/8, x3, x1, x4) + +inst_12172: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8001; +op3val:0x2; valaddr_reg:x2; val_offset:36414*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36414*FLEN/8, x3, x1, x4) + +inst_12173: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8001; +op3val:0x83fe; valaddr_reg:x2; val_offset:36417*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36417*FLEN/8, x3, x1, x4) + +inst_12174: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8001; +op3val:0x3ff; valaddr_reg:x2; val_offset:36420*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36420*FLEN/8, x3, x1, x4) + +inst_12175: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8001; +op3val:0x83ff; valaddr_reg:x2; val_offset:36423*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36423*FLEN/8, x3, x1, x4) + +inst_12176: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8001; +op3val:0x400; valaddr_reg:x2; val_offset:36426*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36426*FLEN/8, x3, x1, x4) + +inst_12177: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8001; +op3val:0x8400; valaddr_reg:x2; val_offset:36429*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36429*FLEN/8, x3, x1, x4) + +inst_12178: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8001; +op3val:0x401; valaddr_reg:x2; val_offset:36432*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36432*FLEN/8, x3, x1, x4) + +inst_12179: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8001; +op3val:0x8455; valaddr_reg:x2; val_offset:36435*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36435*FLEN/8, x3, x1, x4) + +inst_12180: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8001; +op3val:0x7bff; valaddr_reg:x2; val_offset:36438*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36438*FLEN/8, x3, x1, x4) + +inst_12181: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8001; +op3val:0xfbff; valaddr_reg:x2; val_offset:36441*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36441*FLEN/8, x3, x1, x4) + +inst_12182: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8001; +op3val:0x7c00; valaddr_reg:x2; val_offset:36444*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36444*FLEN/8, x3, x1, x4) + +inst_12183: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8001; +op3val:0xfc00; valaddr_reg:x2; val_offset:36447*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36447*FLEN/8, x3, x1, x4) + +inst_12184: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8001; +op3val:0x7e00; valaddr_reg:x2; val_offset:36450*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36450*FLEN/8, x3, x1, x4) + +inst_12185: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8001; +op3val:0xfe00; valaddr_reg:x2; val_offset:36453*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36453*FLEN/8, x3, x1, x4) + +inst_12186: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8001; +op3val:0x7e01; valaddr_reg:x2; val_offset:36456*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36456*FLEN/8, x3, x1, x4) + +inst_12187: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8001; +op3val:0xfe55; valaddr_reg:x2; val_offset:36459*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36459*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_96) + +inst_12188: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8001; +op3val:0x7c01; valaddr_reg:x2; val_offset:36462*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36462*FLEN/8, x3, x1, x4) + +inst_12189: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8001; +op3val:0xfd55; valaddr_reg:x2; val_offset:36465*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36465*FLEN/8, x3, x1, x4) + +inst_12190: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8001; +op3val:0x3c00; valaddr_reg:x2; val_offset:36468*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36468*FLEN/8, x3, x1, x4) + +inst_12191: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8001; +op3val:0xbc00; valaddr_reg:x2; val_offset:36471*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36471*FLEN/8, x3, x1, x4) + +inst_12192: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x2; +op3val:0x0; valaddr_reg:x2; val_offset:36474*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36474*FLEN/8, x3, x1, x4) + +inst_12193: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x2; +op3val:0x8000; valaddr_reg:x2; val_offset:36477*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36477*FLEN/8, x3, x1, x4) + +inst_12194: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x2; +op3val:0x1; valaddr_reg:x2; val_offset:36480*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36480*FLEN/8, x3, x1, x4) + +inst_12195: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x2; +op3val:0x8001; valaddr_reg:x2; val_offset:36483*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36483*FLEN/8, x3, x1, x4) + +inst_12196: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x2; +op3val:0x2; valaddr_reg:x2; val_offset:36486*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36486*FLEN/8, x3, x1, x4) + +inst_12197: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x2; +op3val:0x83fe; valaddr_reg:x2; val_offset:36489*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36489*FLEN/8, x3, x1, x4) + +inst_12198: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x2; +op3val:0x3ff; valaddr_reg:x2; val_offset:36492*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36492*FLEN/8, x3, x1, x4) + +inst_12199: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x2; +op3val:0x83ff; valaddr_reg:x2; val_offset:36495*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36495*FLEN/8, x3, x1, x4) + +inst_12200: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x2; +op3val:0x400; valaddr_reg:x2; val_offset:36498*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36498*FLEN/8, x3, x1, x4) + +inst_12201: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x2; +op3val:0x8400; valaddr_reg:x2; val_offset:36501*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36501*FLEN/8, x3, x1, x4) + +inst_12202: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x2; +op3val:0x401; valaddr_reg:x2; val_offset:36504*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36504*FLEN/8, x3, x1, x4) + +inst_12203: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x2; +op3val:0x8455; valaddr_reg:x2; val_offset:36507*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36507*FLEN/8, x3, x1, x4) + +inst_12204: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x2; +op3val:0x7bff; valaddr_reg:x2; val_offset:36510*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36510*FLEN/8, x3, x1, x4) + +inst_12205: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x2; +op3val:0xfbff; valaddr_reg:x2; val_offset:36513*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36513*FLEN/8, x3, x1, x4) + +inst_12206: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x2; +op3val:0x7c00; valaddr_reg:x2; val_offset:36516*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36516*FLEN/8, x3, x1, x4) + +inst_12207: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x2; +op3val:0xfc00; valaddr_reg:x2; val_offset:36519*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36519*FLEN/8, x3, x1, x4) + +inst_12208: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x2; +op3val:0x7e00; valaddr_reg:x2; val_offset:36522*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36522*FLEN/8, x3, x1, x4) + +inst_12209: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x2; +op3val:0xfe00; valaddr_reg:x2; val_offset:36525*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36525*FLEN/8, x3, x1, x4) + +inst_12210: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x2; +op3val:0x7e01; valaddr_reg:x2; val_offset:36528*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36528*FLEN/8, x3, x1, x4) + +inst_12211: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x2; +op3val:0xfe55; valaddr_reg:x2; val_offset:36531*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36531*FLEN/8, x3, x1, x4) + +inst_12212: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x2; +op3val:0x7c01; valaddr_reg:x2; val_offset:36534*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36534*FLEN/8, x3, x1, x4) + +inst_12213: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x2; +op3val:0xfd55; valaddr_reg:x2; val_offset:36537*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36537*FLEN/8, x3, x1, x4) + +inst_12214: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x2; +op3val:0x3c00; valaddr_reg:x2; val_offset:36540*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36540*FLEN/8, x3, x1, x4) + +inst_12215: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x2; +op3val:0xbc00; valaddr_reg:x2; val_offset:36543*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36543*FLEN/8, x3, x1, x4) + +inst_12216: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x83fe; +op3val:0x0; valaddr_reg:x2; val_offset:36546*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36546*FLEN/8, x3, x1, x4) + +inst_12217: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x83fe; +op3val:0x8000; valaddr_reg:x2; val_offset:36549*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36549*FLEN/8, x3, x1, x4) + +inst_12218: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x83fe; +op3val:0x1; valaddr_reg:x2; val_offset:36552*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36552*FLEN/8, x3, x1, x4) + +inst_12219: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x83fe; +op3val:0x8001; valaddr_reg:x2; val_offset:36555*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36555*FLEN/8, x3, x1, x4) + +inst_12220: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x83fe; +op3val:0x2; valaddr_reg:x2; val_offset:36558*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36558*FLEN/8, x3, x1, x4) + +inst_12221: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x83fe; +op3val:0x83fe; valaddr_reg:x2; val_offset:36561*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36561*FLEN/8, x3, x1, x4) + +inst_12222: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x83fe; +op3val:0x3ff; valaddr_reg:x2; val_offset:36564*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36564*FLEN/8, x3, x1, x4) + +inst_12223: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x83fe; +op3val:0x83ff; valaddr_reg:x2; val_offset:36567*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36567*FLEN/8, x3, x1, x4) + +inst_12224: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x83fe; +op3val:0x400; valaddr_reg:x2; val_offset:36570*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36570*FLEN/8, x3, x1, x4) + +inst_12225: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x83fe; +op3val:0x8400; valaddr_reg:x2; val_offset:36573*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36573*FLEN/8, x3, x1, x4) + +inst_12226: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x83fe; +op3val:0x401; valaddr_reg:x2; val_offset:36576*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36576*FLEN/8, x3, x1, x4) + +inst_12227: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x83fe; +op3val:0x8455; valaddr_reg:x2; val_offset:36579*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36579*FLEN/8, x3, x1, x4) + +inst_12228: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x83fe; +op3val:0x7bff; valaddr_reg:x2; val_offset:36582*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36582*FLEN/8, x3, x1, x4) + +inst_12229: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x83fe; +op3val:0xfbff; valaddr_reg:x2; val_offset:36585*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36585*FLEN/8, x3, x1, x4) + +inst_12230: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x83fe; +op3val:0x7c00; valaddr_reg:x2; val_offset:36588*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36588*FLEN/8, x3, x1, x4) + +inst_12231: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x83fe; +op3val:0xfc00; valaddr_reg:x2; val_offset:36591*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36591*FLEN/8, x3, x1, x4) + +inst_12232: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x83fe; +op3val:0x7e00; valaddr_reg:x2; val_offset:36594*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36594*FLEN/8, x3, x1, x4) + +inst_12233: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x83fe; +op3val:0xfe00; valaddr_reg:x2; val_offset:36597*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36597*FLEN/8, x3, x1, x4) + +inst_12234: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x83fe; +op3val:0x7e01; valaddr_reg:x2; val_offset:36600*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36600*FLEN/8, x3, x1, x4) + +inst_12235: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x83fe; +op3val:0xfe55; valaddr_reg:x2; val_offset:36603*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36603*FLEN/8, x3, x1, x4) + +inst_12236: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x83fe; +op3val:0x7c01; valaddr_reg:x2; val_offset:36606*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36606*FLEN/8, x3, x1, x4) + +inst_12237: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x83fe; +op3val:0xfd55; valaddr_reg:x2; val_offset:36609*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36609*FLEN/8, x3, x1, x4) + +inst_12238: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x83fe; +op3val:0x3c00; valaddr_reg:x2; val_offset:36612*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36612*FLEN/8, x3, x1, x4) + +inst_12239: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x83fe; +op3val:0xbc00; valaddr_reg:x2; val_offset:36615*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36615*FLEN/8, x3, x1, x4) + +inst_12240: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x3ff; +op3val:0x0; valaddr_reg:x2; val_offset:36618*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36618*FLEN/8, x3, x1, x4) + +inst_12241: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x3ff; +op3val:0x8000; valaddr_reg:x2; val_offset:36621*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36621*FLEN/8, x3, x1, x4) + +inst_12242: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x3ff; +op3val:0x1; valaddr_reg:x2; val_offset:36624*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36624*FLEN/8, x3, x1, x4) + +inst_12243: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x3ff; +op3val:0x8001; valaddr_reg:x2; val_offset:36627*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36627*FLEN/8, x3, x1, x4) + +inst_12244: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x3ff; +op3val:0x2; valaddr_reg:x2; val_offset:36630*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36630*FLEN/8, x3, x1, x4) + +inst_12245: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x3ff; +op3val:0x83fe; valaddr_reg:x2; val_offset:36633*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36633*FLEN/8, x3, x1, x4) + +inst_12246: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x3ff; +op3val:0x3ff; valaddr_reg:x2; val_offset:36636*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36636*FLEN/8, x3, x1, x4) + +inst_12247: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x3ff; +op3val:0x83ff; valaddr_reg:x2; val_offset:36639*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36639*FLEN/8, x3, x1, x4) + +inst_12248: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x3ff; +op3val:0x400; valaddr_reg:x2; val_offset:36642*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36642*FLEN/8, x3, x1, x4) + +inst_12249: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x3ff; +op3val:0x8400; valaddr_reg:x2; val_offset:36645*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36645*FLEN/8, x3, x1, x4) + +inst_12250: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x3ff; +op3val:0x401; valaddr_reg:x2; val_offset:36648*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36648*FLEN/8, x3, x1, x4) + +inst_12251: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x3ff; +op3val:0x8455; valaddr_reg:x2; val_offset:36651*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36651*FLEN/8, x3, x1, x4) + +inst_12252: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x3ff; +op3val:0x7bff; valaddr_reg:x2; val_offset:36654*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36654*FLEN/8, x3, x1, x4) + +inst_12253: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x3ff; +op3val:0xfbff; valaddr_reg:x2; val_offset:36657*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36657*FLEN/8, x3, x1, x4) + +inst_12254: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x3ff; +op3val:0x7c00; valaddr_reg:x2; val_offset:36660*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36660*FLEN/8, x3, x1, x4) + +inst_12255: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x3ff; +op3val:0xfc00; valaddr_reg:x2; val_offset:36663*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36663*FLEN/8, x3, x1, x4) + +inst_12256: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x3ff; +op3val:0x7e00; valaddr_reg:x2; val_offset:36666*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36666*FLEN/8, x3, x1, x4) + +inst_12257: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x3ff; +op3val:0xfe00; valaddr_reg:x2; val_offset:36669*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36669*FLEN/8, x3, x1, x4) + +inst_12258: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x3ff; +op3val:0x7e01; valaddr_reg:x2; val_offset:36672*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36672*FLEN/8, x3, x1, x4) + +inst_12259: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x3ff; +op3val:0xfe55; valaddr_reg:x2; val_offset:36675*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36675*FLEN/8, x3, x1, x4) + +inst_12260: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x3ff; +op3val:0x7c01; valaddr_reg:x2; val_offset:36678*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36678*FLEN/8, x3, x1, x4) + +inst_12261: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x3ff; +op3val:0xfd55; valaddr_reg:x2; val_offset:36681*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36681*FLEN/8, x3, x1, x4) + +inst_12262: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x3ff; +op3val:0x3c00; valaddr_reg:x2; val_offset:36684*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36684*FLEN/8, x3, x1, x4) + +inst_12263: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x3ff; +op3val:0xbc00; valaddr_reg:x2; val_offset:36687*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36687*FLEN/8, x3, x1, x4) + +inst_12264: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x83ff; +op3val:0x0; valaddr_reg:x2; val_offset:36690*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36690*FLEN/8, x3, x1, x4) + +inst_12265: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x83ff; +op3val:0x8000; valaddr_reg:x2; val_offset:36693*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36693*FLEN/8, x3, x1, x4) + +inst_12266: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x83ff; +op3val:0x1; valaddr_reg:x2; val_offset:36696*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36696*FLEN/8, x3, x1, x4) + +inst_12267: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x83ff; +op3val:0x8001; valaddr_reg:x2; val_offset:36699*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36699*FLEN/8, x3, x1, x4) + +inst_12268: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x83ff; +op3val:0x2; valaddr_reg:x2; val_offset:36702*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36702*FLEN/8, x3, x1, x4) + +inst_12269: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x83ff; +op3val:0x83fe; valaddr_reg:x2; val_offset:36705*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36705*FLEN/8, x3, x1, x4) + +inst_12270: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x83ff; +op3val:0x3ff; valaddr_reg:x2; val_offset:36708*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36708*FLEN/8, x3, x1, x4) + +inst_12271: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x83ff; +op3val:0x83ff; valaddr_reg:x2; val_offset:36711*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36711*FLEN/8, x3, x1, x4) + +inst_12272: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x83ff; +op3val:0x400; valaddr_reg:x2; val_offset:36714*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36714*FLEN/8, x3, x1, x4) + +inst_12273: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x83ff; +op3val:0x8400; valaddr_reg:x2; val_offset:36717*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36717*FLEN/8, x3, x1, x4) + +inst_12274: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x83ff; +op3val:0x401; valaddr_reg:x2; val_offset:36720*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36720*FLEN/8, x3, x1, x4) + +inst_12275: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x83ff; +op3val:0x8455; valaddr_reg:x2; val_offset:36723*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36723*FLEN/8, x3, x1, x4) + +inst_12276: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x83ff; +op3val:0x7bff; valaddr_reg:x2; val_offset:36726*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36726*FLEN/8, x3, x1, x4) + +inst_12277: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x83ff; +op3val:0xfbff; valaddr_reg:x2; val_offset:36729*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36729*FLEN/8, x3, x1, x4) + +inst_12278: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x83ff; +op3val:0x7c00; valaddr_reg:x2; val_offset:36732*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36732*FLEN/8, x3, x1, x4) + +inst_12279: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x83ff; +op3val:0xfc00; valaddr_reg:x2; val_offset:36735*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36735*FLEN/8, x3, x1, x4) + +inst_12280: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x83ff; +op3val:0x7e00; valaddr_reg:x2; val_offset:36738*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36738*FLEN/8, x3, x1, x4) + +inst_12281: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x83ff; +op3val:0xfe00; valaddr_reg:x2; val_offset:36741*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36741*FLEN/8, x3, x1, x4) + +inst_12282: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x83ff; +op3val:0x7e01; valaddr_reg:x2; val_offset:36744*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36744*FLEN/8, x3, x1, x4) + +inst_12283: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x83ff; +op3val:0xfe55; valaddr_reg:x2; val_offset:36747*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36747*FLEN/8, x3, x1, x4) + +inst_12284: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x83ff; +op3val:0x7c01; valaddr_reg:x2; val_offset:36750*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36750*FLEN/8, x3, x1, x4) + +inst_12285: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x83ff; +op3val:0xfd55; valaddr_reg:x2; val_offset:36753*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36753*FLEN/8, x3, x1, x4) + +inst_12286: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x83ff; +op3val:0x3c00; valaddr_reg:x2; val_offset:36756*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36756*FLEN/8, x3, x1, x4) + +inst_12287: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x83ff; +op3val:0xbc00; valaddr_reg:x2; val_offset:36759*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36759*FLEN/8, x3, x1, x4) + +inst_12288: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x400; +op3val:0x0; valaddr_reg:x2; val_offset:36762*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36762*FLEN/8, x3, x1, x4) + +inst_12289: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x400; +op3val:0x8000; valaddr_reg:x2; val_offset:36765*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36765*FLEN/8, x3, x1, x4) + +inst_12290: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x400; +op3val:0x1; valaddr_reg:x2; val_offset:36768*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36768*FLEN/8, x3, x1, x4) + +inst_12291: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x400; +op3val:0x8001; valaddr_reg:x2; val_offset:36771*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36771*FLEN/8, x3, x1, x4) + +inst_12292: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x400; +op3val:0x2; valaddr_reg:x2; val_offset:36774*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36774*FLEN/8, x3, x1, x4) + +inst_12293: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x400; +op3val:0x83fe; valaddr_reg:x2; val_offset:36777*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36777*FLEN/8, x3, x1, x4) + +inst_12294: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x400; +op3val:0x3ff; valaddr_reg:x2; val_offset:36780*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36780*FLEN/8, x3, x1, x4) + +inst_12295: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x400; +op3val:0x83ff; valaddr_reg:x2; val_offset:36783*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36783*FLEN/8, x3, x1, x4) + +inst_12296: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x400; +op3val:0x400; valaddr_reg:x2; val_offset:36786*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36786*FLEN/8, x3, x1, x4) + +inst_12297: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x400; +op3val:0x8400; valaddr_reg:x2; val_offset:36789*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36789*FLEN/8, x3, x1, x4) + +inst_12298: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x400; +op3val:0x401; valaddr_reg:x2; val_offset:36792*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36792*FLEN/8, x3, x1, x4) + +inst_12299: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x400; +op3val:0x8455; valaddr_reg:x2; val_offset:36795*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36795*FLEN/8, x3, x1, x4) + +inst_12300: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x400; +op3val:0x7bff; valaddr_reg:x2; val_offset:36798*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36798*FLEN/8, x3, x1, x4) + +inst_12301: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x400; +op3val:0xfbff; valaddr_reg:x2; val_offset:36801*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36801*FLEN/8, x3, x1, x4) + +inst_12302: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x400; +op3val:0x7c00; valaddr_reg:x2; val_offset:36804*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36804*FLEN/8, x3, x1, x4) + +inst_12303: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x400; +op3val:0xfc00; valaddr_reg:x2; val_offset:36807*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36807*FLEN/8, x3, x1, x4) + +inst_12304: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x400; +op3val:0x7e00; valaddr_reg:x2; val_offset:36810*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36810*FLEN/8, x3, x1, x4) + +inst_12305: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x400; +op3val:0xfe00; valaddr_reg:x2; val_offset:36813*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36813*FLEN/8, x3, x1, x4) + +inst_12306: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x400; +op3val:0x7e01; valaddr_reg:x2; val_offset:36816*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36816*FLEN/8, x3, x1, x4) + +inst_12307: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x400; +op3val:0xfe55; valaddr_reg:x2; val_offset:36819*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36819*FLEN/8, x3, x1, x4) + +inst_12308: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x400; +op3val:0x7c01; valaddr_reg:x2; val_offset:36822*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36822*FLEN/8, x3, x1, x4) + +inst_12309: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x400; +op3val:0xfd55; valaddr_reg:x2; val_offset:36825*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36825*FLEN/8, x3, x1, x4) + +inst_12310: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x400; +op3val:0x3c00; valaddr_reg:x2; val_offset:36828*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36828*FLEN/8, x3, x1, x4) + +inst_12311: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x400; +op3val:0xbc00; valaddr_reg:x2; val_offset:36831*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36831*FLEN/8, x3, x1, x4) + +inst_12312: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8400; +op3val:0x0; valaddr_reg:x2; val_offset:36834*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36834*FLEN/8, x3, x1, x4) + +inst_12313: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8400; +op3val:0x8000; valaddr_reg:x2; val_offset:36837*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36837*FLEN/8, x3, x1, x4) + +inst_12314: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8400; +op3val:0x1; valaddr_reg:x2; val_offset:36840*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36840*FLEN/8, x3, x1, x4) + +inst_12315: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8400; +op3val:0x8001; valaddr_reg:x2; val_offset:36843*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36843*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_97) + +inst_12316: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8400; +op3val:0x2; valaddr_reg:x2; val_offset:36846*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36846*FLEN/8, x3, x1, x4) + +inst_12317: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8400; +op3val:0x83fe; valaddr_reg:x2; val_offset:36849*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36849*FLEN/8, x3, x1, x4) + +inst_12318: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8400; +op3val:0x3ff; valaddr_reg:x2; val_offset:36852*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36852*FLEN/8, x3, x1, x4) + +inst_12319: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8400; +op3val:0x83ff; valaddr_reg:x2; val_offset:36855*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36855*FLEN/8, x3, x1, x4) + +inst_12320: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8400; +op3val:0x400; valaddr_reg:x2; val_offset:36858*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36858*FLEN/8, x3, x1, x4) + +inst_12321: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8400; +op3val:0x8400; valaddr_reg:x2; val_offset:36861*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36861*FLEN/8, x3, x1, x4) + +inst_12322: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8400; +op3val:0x401; valaddr_reg:x2; val_offset:36864*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36864*FLEN/8, x3, x1, x4) + +inst_12323: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8400; +op3val:0x8455; valaddr_reg:x2; val_offset:36867*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36867*FLEN/8, x3, x1, x4) + +inst_12324: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8400; +op3val:0x7bff; valaddr_reg:x2; val_offset:36870*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36870*FLEN/8, x3, x1, x4) + +inst_12325: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8400; +op3val:0xfbff; valaddr_reg:x2; val_offset:36873*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36873*FLEN/8, x3, x1, x4) + +inst_12326: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8400; +op3val:0x7c00; valaddr_reg:x2; val_offset:36876*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36876*FLEN/8, x3, x1, x4) + +inst_12327: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8400; +op3val:0xfc00; valaddr_reg:x2; val_offset:36879*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36879*FLEN/8, x3, x1, x4) + +inst_12328: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8400; +op3val:0x7e00; valaddr_reg:x2; val_offset:36882*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36882*FLEN/8, x3, x1, x4) + +inst_12329: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8400; +op3val:0xfe00; valaddr_reg:x2; val_offset:36885*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36885*FLEN/8, x3, x1, x4) + +inst_12330: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8400; +op3val:0x7e01; valaddr_reg:x2; val_offset:36888*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36888*FLEN/8, x3, x1, x4) + +inst_12331: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8400; +op3val:0xfe55; valaddr_reg:x2; val_offset:36891*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36891*FLEN/8, x3, x1, x4) + +inst_12332: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8400; +op3val:0x7c01; valaddr_reg:x2; val_offset:36894*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36894*FLEN/8, x3, x1, x4) + +inst_12333: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8400; +op3val:0xfd55; valaddr_reg:x2; val_offset:36897*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36897*FLEN/8, x3, x1, x4) + +inst_12334: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8400; +op3val:0x3c00; valaddr_reg:x2; val_offset:36900*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36900*FLEN/8, x3, x1, x4) + +inst_12335: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8400; +op3val:0xbc00; valaddr_reg:x2; val_offset:36903*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36903*FLEN/8, x3, x1, x4) + +inst_12336: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x401; +op3val:0x0; valaddr_reg:x2; val_offset:36906*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36906*FLEN/8, x3, x1, x4) + +inst_12337: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x401; +op3val:0x8000; valaddr_reg:x2; val_offset:36909*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36909*FLEN/8, x3, x1, x4) + +inst_12338: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x401; +op3val:0x1; valaddr_reg:x2; val_offset:36912*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36912*FLEN/8, x3, x1, x4) + +inst_12339: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x401; +op3val:0x8001; valaddr_reg:x2; val_offset:36915*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36915*FLEN/8, x3, x1, x4) + +inst_12340: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x401; +op3val:0x2; valaddr_reg:x2; val_offset:36918*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36918*FLEN/8, x3, x1, x4) + +inst_12341: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x401; +op3val:0x83fe; valaddr_reg:x2; val_offset:36921*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36921*FLEN/8, x3, x1, x4) + +inst_12342: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x401; +op3val:0x3ff; valaddr_reg:x2; val_offset:36924*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36924*FLEN/8, x3, x1, x4) + +inst_12343: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x401; +op3val:0x83ff; valaddr_reg:x2; val_offset:36927*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36927*FLEN/8, x3, x1, x4) + +inst_12344: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x401; +op3val:0x400; valaddr_reg:x2; val_offset:36930*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36930*FLEN/8, x3, x1, x4) + +inst_12345: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x401; +op3val:0x8400; valaddr_reg:x2; val_offset:36933*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36933*FLEN/8, x3, x1, x4) + +inst_12346: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x401; +op3val:0x401; valaddr_reg:x2; val_offset:36936*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36936*FLEN/8, x3, x1, x4) + +inst_12347: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x401; +op3val:0x8455; valaddr_reg:x2; val_offset:36939*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36939*FLEN/8, x3, x1, x4) + +inst_12348: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x401; +op3val:0x7bff; valaddr_reg:x2; val_offset:36942*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36942*FLEN/8, x3, x1, x4) + +inst_12349: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x401; +op3val:0xfbff; valaddr_reg:x2; val_offset:36945*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36945*FLEN/8, x3, x1, x4) + +inst_12350: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x401; +op3val:0x7c00; valaddr_reg:x2; val_offset:36948*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36948*FLEN/8, x3, x1, x4) + +inst_12351: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x401; +op3val:0xfc00; valaddr_reg:x2; val_offset:36951*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36951*FLEN/8, x3, x1, x4) + +inst_12352: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x401; +op3val:0x7e00; valaddr_reg:x2; val_offset:36954*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36954*FLEN/8, x3, x1, x4) + +inst_12353: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x401; +op3val:0xfe00; valaddr_reg:x2; val_offset:36957*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36957*FLEN/8, x3, x1, x4) + +inst_12354: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x401; +op3val:0x7e01; valaddr_reg:x2; val_offset:36960*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36960*FLEN/8, x3, x1, x4) + +inst_12355: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x401; +op3val:0xfe55; valaddr_reg:x2; val_offset:36963*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36963*FLEN/8, x3, x1, x4) + +inst_12356: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x401; +op3val:0x7c01; valaddr_reg:x2; val_offset:36966*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36966*FLEN/8, x3, x1, x4) + +inst_12357: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x401; +op3val:0xfd55; valaddr_reg:x2; val_offset:36969*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36969*FLEN/8, x3, x1, x4) + +inst_12358: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x401; +op3val:0x3c00; valaddr_reg:x2; val_offset:36972*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36972*FLEN/8, x3, x1, x4) + +inst_12359: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x401; +op3val:0xbc00; valaddr_reg:x2; val_offset:36975*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36975*FLEN/8, x3, x1, x4) + +inst_12360: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8455; +op3val:0x0; valaddr_reg:x2; val_offset:36978*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36978*FLEN/8, x3, x1, x4) + +inst_12361: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8455; +op3val:0x8000; valaddr_reg:x2; val_offset:36981*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36981*FLEN/8, x3, x1, x4) + +inst_12362: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8455; +op3val:0x1; valaddr_reg:x2; val_offset:36984*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36984*FLEN/8, x3, x1, x4) + +inst_12363: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8455; +op3val:0x8001; valaddr_reg:x2; val_offset:36987*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36987*FLEN/8, x3, x1, x4) + +inst_12364: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8455; +op3val:0x2; valaddr_reg:x2; val_offset:36990*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36990*FLEN/8, x3, x1, x4) + +inst_12365: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8455; +op3val:0x83fe; valaddr_reg:x2; val_offset:36993*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36993*FLEN/8, x3, x1, x4) + +inst_12366: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8455; +op3val:0x3ff; valaddr_reg:x2; val_offset:36996*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36996*FLEN/8, x3, x1, x4) + +inst_12367: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8455; +op3val:0x83ff; valaddr_reg:x2; val_offset:36999*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36999*FLEN/8, x3, x1, x4) + +inst_12368: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8455; +op3val:0x400; valaddr_reg:x2; val_offset:37002*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37002*FLEN/8, x3, x1, x4) + +inst_12369: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8455; +op3val:0x8400; valaddr_reg:x2; val_offset:37005*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37005*FLEN/8, x3, x1, x4) + +inst_12370: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8455; +op3val:0x401; valaddr_reg:x2; val_offset:37008*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37008*FLEN/8, x3, x1, x4) + +inst_12371: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8455; +op3val:0x8455; valaddr_reg:x2; val_offset:37011*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37011*FLEN/8, x3, x1, x4) + +inst_12372: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8455; +op3val:0x7bff; valaddr_reg:x2; val_offset:37014*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37014*FLEN/8, x3, x1, x4) + +inst_12373: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8455; +op3val:0xfbff; valaddr_reg:x2; val_offset:37017*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37017*FLEN/8, x3, x1, x4) + +inst_12374: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8455; +op3val:0x7c00; valaddr_reg:x2; val_offset:37020*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37020*FLEN/8, x3, x1, x4) + +inst_12375: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8455; +op3val:0xfc00; valaddr_reg:x2; val_offset:37023*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37023*FLEN/8, x3, x1, x4) + +inst_12376: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8455; +op3val:0x7e00; valaddr_reg:x2; val_offset:37026*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37026*FLEN/8, x3, x1, x4) + +inst_12377: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8455; +op3val:0xfe00; valaddr_reg:x2; val_offset:37029*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37029*FLEN/8, x3, x1, x4) + +inst_12378: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8455; +op3val:0x7e01; valaddr_reg:x2; val_offset:37032*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37032*FLEN/8, x3, x1, x4) + +inst_12379: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8455; +op3val:0xfe55; valaddr_reg:x2; val_offset:37035*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37035*FLEN/8, x3, x1, x4) + +inst_12380: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8455; +op3val:0x7c01; valaddr_reg:x2; val_offset:37038*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37038*FLEN/8, x3, x1, x4) + +inst_12381: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8455; +op3val:0xfd55; valaddr_reg:x2; val_offset:37041*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37041*FLEN/8, x3, x1, x4) + +inst_12382: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8455; +op3val:0x3c00; valaddr_reg:x2; val_offset:37044*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37044*FLEN/8, x3, x1, x4) + +inst_12383: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x8455; +op3val:0xbc00; valaddr_reg:x2; val_offset:37047*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37047*FLEN/8, x3, x1, x4) + +inst_12384: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7bff; +op3val:0x0; valaddr_reg:x2; val_offset:37050*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37050*FLEN/8, x3, x1, x4) + +inst_12385: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7bff; +op3val:0x8000; valaddr_reg:x2; val_offset:37053*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37053*FLEN/8, x3, x1, x4) + +inst_12386: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7bff; +op3val:0x1; valaddr_reg:x2; val_offset:37056*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37056*FLEN/8, x3, x1, x4) + +inst_12387: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7bff; +op3val:0x8001; valaddr_reg:x2; val_offset:37059*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37059*FLEN/8, x3, x1, x4) + +inst_12388: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7bff; +op3val:0x2; valaddr_reg:x2; val_offset:37062*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37062*FLEN/8, x3, x1, x4) + +inst_12389: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7bff; +op3val:0x83fe; valaddr_reg:x2; val_offset:37065*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37065*FLEN/8, x3, x1, x4) + +inst_12390: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7bff; +op3val:0x3ff; valaddr_reg:x2; val_offset:37068*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37068*FLEN/8, x3, x1, x4) + +inst_12391: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7bff; +op3val:0x83ff; valaddr_reg:x2; val_offset:37071*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37071*FLEN/8, x3, x1, x4) + +inst_12392: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7bff; +op3val:0x400; valaddr_reg:x2; val_offset:37074*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37074*FLEN/8, x3, x1, x4) + +inst_12393: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7bff; +op3val:0x8400; valaddr_reg:x2; val_offset:37077*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37077*FLEN/8, x3, x1, x4) + +inst_12394: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7bff; +op3val:0x401; valaddr_reg:x2; val_offset:37080*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37080*FLEN/8, x3, x1, x4) + +inst_12395: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7bff; +op3val:0x8455; valaddr_reg:x2; val_offset:37083*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37083*FLEN/8, x3, x1, x4) + +inst_12396: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7bff; +op3val:0x7bff; valaddr_reg:x2; val_offset:37086*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37086*FLEN/8, x3, x1, x4) + +inst_12397: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7bff; +op3val:0xfbff; valaddr_reg:x2; val_offset:37089*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37089*FLEN/8, x3, x1, x4) + +inst_12398: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7bff; +op3val:0x7c00; valaddr_reg:x2; val_offset:37092*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37092*FLEN/8, x3, x1, x4) + +inst_12399: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7bff; +op3val:0xfc00; valaddr_reg:x2; val_offset:37095*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37095*FLEN/8, x3, x1, x4) + +inst_12400: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7bff; +op3val:0x7e00; valaddr_reg:x2; val_offset:37098*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37098*FLEN/8, x3, x1, x4) + +inst_12401: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7bff; +op3val:0xfe00; valaddr_reg:x2; val_offset:37101*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37101*FLEN/8, x3, x1, x4) + +inst_12402: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7bff; +op3val:0x7e01; valaddr_reg:x2; val_offset:37104*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37104*FLEN/8, x3, x1, x4) + +inst_12403: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7bff; +op3val:0xfe55; valaddr_reg:x2; val_offset:37107*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37107*FLEN/8, x3, x1, x4) + +inst_12404: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7bff; +op3val:0x7c01; valaddr_reg:x2; val_offset:37110*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37110*FLEN/8, x3, x1, x4) + +inst_12405: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7bff; +op3val:0xfd55; valaddr_reg:x2; val_offset:37113*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37113*FLEN/8, x3, x1, x4) + +inst_12406: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7bff; +op3val:0x3c00; valaddr_reg:x2; val_offset:37116*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37116*FLEN/8, x3, x1, x4) + +inst_12407: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7bff; +op3val:0xbc00; valaddr_reg:x2; val_offset:37119*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37119*FLEN/8, x3, x1, x4) + +inst_12408: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfbff; +op3val:0x0; valaddr_reg:x2; val_offset:37122*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37122*FLEN/8, x3, x1, x4) + +inst_12409: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfbff; +op3val:0x8000; valaddr_reg:x2; val_offset:37125*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37125*FLEN/8, x3, x1, x4) + +inst_12410: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfbff; +op3val:0x1; valaddr_reg:x2; val_offset:37128*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37128*FLEN/8, x3, x1, x4) + +inst_12411: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfbff; +op3val:0x8001; valaddr_reg:x2; val_offset:37131*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37131*FLEN/8, x3, x1, x4) + +inst_12412: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfbff; +op3val:0x2; valaddr_reg:x2; val_offset:37134*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37134*FLEN/8, x3, x1, x4) + +inst_12413: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfbff; +op3val:0x83fe; valaddr_reg:x2; val_offset:37137*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37137*FLEN/8, x3, x1, x4) + +inst_12414: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfbff; +op3val:0x3ff; valaddr_reg:x2; val_offset:37140*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37140*FLEN/8, x3, x1, x4) + +inst_12415: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfbff; +op3val:0x83ff; valaddr_reg:x2; val_offset:37143*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37143*FLEN/8, x3, x1, x4) + +inst_12416: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfbff; +op3val:0x400; valaddr_reg:x2; val_offset:37146*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37146*FLEN/8, x3, x1, x4) + +inst_12417: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfbff; +op3val:0x8400; valaddr_reg:x2; val_offset:37149*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37149*FLEN/8, x3, x1, x4) + +inst_12418: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfbff; +op3val:0x401; valaddr_reg:x2; val_offset:37152*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37152*FLEN/8, x3, x1, x4) + +inst_12419: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfbff; +op3val:0x8455; valaddr_reg:x2; val_offset:37155*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37155*FLEN/8, x3, x1, x4) + +inst_12420: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfbff; +op3val:0x7bff; valaddr_reg:x2; val_offset:37158*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37158*FLEN/8, x3, x1, x4) + +inst_12421: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfbff; +op3val:0xfbff; valaddr_reg:x2; val_offset:37161*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37161*FLEN/8, x3, x1, x4) + +inst_12422: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfbff; +op3val:0x7c00; valaddr_reg:x2; val_offset:37164*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37164*FLEN/8, x3, x1, x4) + +inst_12423: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfbff; +op3val:0xfc00; valaddr_reg:x2; val_offset:37167*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37167*FLEN/8, x3, x1, x4) + +inst_12424: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfbff; +op3val:0x7e00; valaddr_reg:x2; val_offset:37170*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37170*FLEN/8, x3, x1, x4) + +inst_12425: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfbff; +op3val:0xfe00; valaddr_reg:x2; val_offset:37173*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37173*FLEN/8, x3, x1, x4) + +inst_12426: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfbff; +op3val:0x7e01; valaddr_reg:x2; val_offset:37176*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37176*FLEN/8, x3, x1, x4) + +inst_12427: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfbff; +op3val:0xfe55; valaddr_reg:x2; val_offset:37179*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37179*FLEN/8, x3, x1, x4) + +inst_12428: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfbff; +op3val:0x7c01; valaddr_reg:x2; val_offset:37182*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37182*FLEN/8, x3, x1, x4) + +inst_12429: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfbff; +op3val:0xfd55; valaddr_reg:x2; val_offset:37185*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37185*FLEN/8, x3, x1, x4) + +inst_12430: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfbff; +op3val:0x3c00; valaddr_reg:x2; val_offset:37188*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37188*FLEN/8, x3, x1, x4) + +inst_12431: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfbff; +op3val:0xbc00; valaddr_reg:x2; val_offset:37191*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37191*FLEN/8, x3, x1, x4) + +inst_12432: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7c00; +op3val:0x0; valaddr_reg:x2; val_offset:37194*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37194*FLEN/8, x3, x1, x4) + +inst_12433: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7c00; +op3val:0x8000; valaddr_reg:x2; val_offset:37197*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37197*FLEN/8, x3, x1, x4) + +inst_12434: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7c00; +op3val:0x1; valaddr_reg:x2; val_offset:37200*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37200*FLEN/8, x3, x1, x4) + +inst_12435: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7c00; +op3val:0x8001; valaddr_reg:x2; val_offset:37203*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37203*FLEN/8, x3, x1, x4) + +inst_12436: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7c00; +op3val:0x2; valaddr_reg:x2; val_offset:37206*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37206*FLEN/8, x3, x1, x4) + +inst_12437: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7c00; +op3val:0x83fe; valaddr_reg:x2; val_offset:37209*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37209*FLEN/8, x3, x1, x4) + +inst_12438: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7c00; +op3val:0x3ff; valaddr_reg:x2; val_offset:37212*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37212*FLEN/8, x3, x1, x4) + +inst_12439: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7c00; +op3val:0x83ff; valaddr_reg:x2; val_offset:37215*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37215*FLEN/8, x3, x1, x4) + +inst_12440: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7c00; +op3val:0x400; valaddr_reg:x2; val_offset:37218*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37218*FLEN/8, x3, x1, x4) + +inst_12441: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7c00; +op3val:0x8400; valaddr_reg:x2; val_offset:37221*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37221*FLEN/8, x3, x1, x4) + +inst_12442: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7c00; +op3val:0x401; valaddr_reg:x2; val_offset:37224*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37224*FLEN/8, x3, x1, x4) + +inst_12443: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7c00; +op3val:0x8455; valaddr_reg:x2; val_offset:37227*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37227*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_98) + +inst_12444: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7c00; +op3val:0x7bff; valaddr_reg:x2; val_offset:37230*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37230*FLEN/8, x3, x1, x4) + +inst_12445: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7c00; +op3val:0xfbff; valaddr_reg:x2; val_offset:37233*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37233*FLEN/8, x3, x1, x4) + +inst_12446: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7c00; +op3val:0x7c00; valaddr_reg:x2; val_offset:37236*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37236*FLEN/8, x3, x1, x4) + +inst_12447: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7c00; +op3val:0xfc00; valaddr_reg:x2; val_offset:37239*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37239*FLEN/8, x3, x1, x4) + +inst_12448: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7c00; +op3val:0x7e00; valaddr_reg:x2; val_offset:37242*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37242*FLEN/8, x3, x1, x4) + +inst_12449: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7c00; +op3val:0xfe00; valaddr_reg:x2; val_offset:37245*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37245*FLEN/8, x3, x1, x4) + +inst_12450: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7c00; +op3val:0x7e01; valaddr_reg:x2; val_offset:37248*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37248*FLEN/8, x3, x1, x4) + +inst_12451: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7c00; +op3val:0xfe55; valaddr_reg:x2; val_offset:37251*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37251*FLEN/8, x3, x1, x4) + +inst_12452: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7c00; +op3val:0x7c01; valaddr_reg:x2; val_offset:37254*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37254*FLEN/8, x3, x1, x4) + +inst_12453: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7c00; +op3val:0xfd55; valaddr_reg:x2; val_offset:37257*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37257*FLEN/8, x3, x1, x4) + +inst_12454: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7c00; +op3val:0x3c00; valaddr_reg:x2; val_offset:37260*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37260*FLEN/8, x3, x1, x4) + +inst_12455: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7c00; +op3val:0xbc00; valaddr_reg:x2; val_offset:37263*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37263*FLEN/8, x3, x1, x4) + +inst_12456: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfc00; +op3val:0x0; valaddr_reg:x2; val_offset:37266*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37266*FLEN/8, x3, x1, x4) + +inst_12457: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfc00; +op3val:0x8000; valaddr_reg:x2; val_offset:37269*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37269*FLEN/8, x3, x1, x4) + +inst_12458: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfc00; +op3val:0x1; valaddr_reg:x2; val_offset:37272*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37272*FLEN/8, x3, x1, x4) + +inst_12459: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfc00; +op3val:0x8001; valaddr_reg:x2; val_offset:37275*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37275*FLEN/8, x3, x1, x4) + +inst_12460: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfc00; +op3val:0x2; valaddr_reg:x2; val_offset:37278*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37278*FLEN/8, x3, x1, x4) + +inst_12461: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfc00; +op3val:0x83fe; valaddr_reg:x2; val_offset:37281*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37281*FLEN/8, x3, x1, x4) + +inst_12462: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfc00; +op3val:0x3ff; valaddr_reg:x2; val_offset:37284*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37284*FLEN/8, x3, x1, x4) + +inst_12463: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfc00; +op3val:0x83ff; valaddr_reg:x2; val_offset:37287*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37287*FLEN/8, x3, x1, x4) + +inst_12464: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfc00; +op3val:0x400; valaddr_reg:x2; val_offset:37290*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37290*FLEN/8, x3, x1, x4) + +inst_12465: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfc00; +op3val:0x8400; valaddr_reg:x2; val_offset:37293*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37293*FLEN/8, x3, x1, x4) + +inst_12466: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfc00; +op3val:0x401; valaddr_reg:x2; val_offset:37296*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37296*FLEN/8, x3, x1, x4) + +inst_12467: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfc00; +op3val:0x8455; valaddr_reg:x2; val_offset:37299*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37299*FLEN/8, x3, x1, x4) + +inst_12468: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfc00; +op3val:0x7bff; valaddr_reg:x2; val_offset:37302*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37302*FLEN/8, x3, x1, x4) + +inst_12469: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfc00; +op3val:0xfbff; valaddr_reg:x2; val_offset:37305*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37305*FLEN/8, x3, x1, x4) + +inst_12470: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfc00; +op3val:0x7c00; valaddr_reg:x2; val_offset:37308*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37308*FLEN/8, x3, x1, x4) + +inst_12471: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfc00; +op3val:0xfc00; valaddr_reg:x2; val_offset:37311*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37311*FLEN/8, x3, x1, x4) + +inst_12472: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfc00; +op3val:0x7e00; valaddr_reg:x2; val_offset:37314*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37314*FLEN/8, x3, x1, x4) + +inst_12473: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfc00; +op3val:0xfe00; valaddr_reg:x2; val_offset:37317*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37317*FLEN/8, x3, x1, x4) + +inst_12474: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfc00; +op3val:0x7e01; valaddr_reg:x2; val_offset:37320*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37320*FLEN/8, x3, x1, x4) + +inst_12475: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfc00; +op3val:0xfe55; valaddr_reg:x2; val_offset:37323*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37323*FLEN/8, x3, x1, x4) + +inst_12476: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfc00; +op3val:0x7c01; valaddr_reg:x2; val_offset:37326*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37326*FLEN/8, x3, x1, x4) + +inst_12477: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfc00; +op3val:0xfd55; valaddr_reg:x2; val_offset:37329*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37329*FLEN/8, x3, x1, x4) + +inst_12478: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfc00; +op3val:0x3c00; valaddr_reg:x2; val_offset:37332*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37332*FLEN/8, x3, x1, x4) + +inst_12479: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfc00; +op3val:0xbc00; valaddr_reg:x2; val_offset:37335*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37335*FLEN/8, x3, x1, x4) + +inst_12480: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7e00; +op3val:0x0; valaddr_reg:x2; val_offset:37338*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37338*FLEN/8, x3, x1, x4) + +inst_12481: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7e00; +op3val:0x8000; valaddr_reg:x2; val_offset:37341*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37341*FLEN/8, x3, x1, x4) + +inst_12482: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7e00; +op3val:0x1; valaddr_reg:x2; val_offset:37344*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37344*FLEN/8, x3, x1, x4) + +inst_12483: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7e00; +op3val:0x8001; valaddr_reg:x2; val_offset:37347*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37347*FLEN/8, x3, x1, x4) + +inst_12484: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7e00; +op3val:0x2; valaddr_reg:x2; val_offset:37350*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37350*FLEN/8, x3, x1, x4) + +inst_12485: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7e00; +op3val:0x83fe; valaddr_reg:x2; val_offset:37353*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37353*FLEN/8, x3, x1, x4) + +inst_12486: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7e00; +op3val:0x3ff; valaddr_reg:x2; val_offset:37356*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37356*FLEN/8, x3, x1, x4) + +inst_12487: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7e00; +op3val:0x83ff; valaddr_reg:x2; val_offset:37359*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37359*FLEN/8, x3, x1, x4) + +inst_12488: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7e00; +op3val:0x400; valaddr_reg:x2; val_offset:37362*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37362*FLEN/8, x3, x1, x4) + +inst_12489: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7e00; +op3val:0x8400; valaddr_reg:x2; val_offset:37365*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37365*FLEN/8, x3, x1, x4) + +inst_12490: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7e00; +op3val:0x401; valaddr_reg:x2; val_offset:37368*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37368*FLEN/8, x3, x1, x4) + +inst_12491: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7e00; +op3val:0x8455; valaddr_reg:x2; val_offset:37371*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37371*FLEN/8, x3, x1, x4) + +inst_12492: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7e00; +op3val:0x7bff; valaddr_reg:x2; val_offset:37374*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37374*FLEN/8, x3, x1, x4) + +inst_12493: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7e00; +op3val:0xfbff; valaddr_reg:x2; val_offset:37377*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37377*FLEN/8, x3, x1, x4) + +inst_12494: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7e00; +op3val:0x7c00; valaddr_reg:x2; val_offset:37380*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37380*FLEN/8, x3, x1, x4) + +inst_12495: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7e00; +op3val:0xfc00; valaddr_reg:x2; val_offset:37383*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37383*FLEN/8, x3, x1, x4) + +inst_12496: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7e00; +op3val:0x7e00; valaddr_reg:x2; val_offset:37386*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37386*FLEN/8, x3, x1, x4) + +inst_12497: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7e00; +op3val:0xfe00; valaddr_reg:x2; val_offset:37389*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37389*FLEN/8, x3, x1, x4) + +inst_12498: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7e00; +op3val:0x7e01; valaddr_reg:x2; val_offset:37392*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37392*FLEN/8, x3, x1, x4) + +inst_12499: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7e00; +op3val:0xfe55; valaddr_reg:x2; val_offset:37395*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37395*FLEN/8, x3, x1, x4) + +inst_12500: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7e00; +op3val:0x7c01; valaddr_reg:x2; val_offset:37398*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37398*FLEN/8, x3, x1, x4) + +inst_12501: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7e00; +op3val:0xfd55; valaddr_reg:x2; val_offset:37401*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37401*FLEN/8, x3, x1, x4) + +inst_12502: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7e00; +op3val:0x3c00; valaddr_reg:x2; val_offset:37404*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37404*FLEN/8, x3, x1, x4) + +inst_12503: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7e00; +op3val:0xbc00; valaddr_reg:x2; val_offset:37407*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37407*FLEN/8, x3, x1, x4) + +inst_12504: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfe00; +op3val:0x0; valaddr_reg:x2; val_offset:37410*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37410*FLEN/8, x3, x1, x4) + +inst_12505: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfe00; +op3val:0x8000; valaddr_reg:x2; val_offset:37413*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37413*FLEN/8, x3, x1, x4) + +inst_12506: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfe00; +op3val:0x1; valaddr_reg:x2; val_offset:37416*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37416*FLEN/8, x3, x1, x4) + +inst_12507: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfe00; +op3val:0x8001; valaddr_reg:x2; val_offset:37419*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37419*FLEN/8, x3, x1, x4) + +inst_12508: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfe00; +op3val:0x2; valaddr_reg:x2; val_offset:37422*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37422*FLEN/8, x3, x1, x4) + +inst_12509: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfe00; +op3val:0x83fe; valaddr_reg:x2; val_offset:37425*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37425*FLEN/8, x3, x1, x4) + +inst_12510: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfe00; +op3val:0x3ff; valaddr_reg:x2; val_offset:37428*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37428*FLEN/8, x3, x1, x4) + +inst_12511: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfe00; +op3val:0x83ff; valaddr_reg:x2; val_offset:37431*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37431*FLEN/8, x3, x1, x4) + +inst_12512: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfe00; +op3val:0x400; valaddr_reg:x2; val_offset:37434*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37434*FLEN/8, x3, x1, x4) + +inst_12513: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfe00; +op3val:0x8400; valaddr_reg:x2; val_offset:37437*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37437*FLEN/8, x3, x1, x4) + +inst_12514: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfe00; +op3val:0x401; valaddr_reg:x2; val_offset:37440*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37440*FLEN/8, x3, x1, x4) + +inst_12515: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfe00; +op3val:0x8455; valaddr_reg:x2; val_offset:37443*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37443*FLEN/8, x3, x1, x4) + +inst_12516: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfe00; +op3val:0x7bff; valaddr_reg:x2; val_offset:37446*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37446*FLEN/8, x3, x1, x4) + +inst_12517: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfe00; +op3val:0xfbff; valaddr_reg:x2; val_offset:37449*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37449*FLEN/8, x3, x1, x4) + +inst_12518: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfe00; +op3val:0x7c00; valaddr_reg:x2; val_offset:37452*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37452*FLEN/8, x3, x1, x4) + +inst_12519: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfe00; +op3val:0xfc00; valaddr_reg:x2; val_offset:37455*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37455*FLEN/8, x3, x1, x4) + +inst_12520: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfe00; +op3val:0x7e00; valaddr_reg:x2; val_offset:37458*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37458*FLEN/8, x3, x1, x4) + +inst_12521: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfe00; +op3val:0xfe00; valaddr_reg:x2; val_offset:37461*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37461*FLEN/8, x3, x1, x4) + +inst_12522: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfe00; +op3val:0x7e01; valaddr_reg:x2; val_offset:37464*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37464*FLEN/8, x3, x1, x4) + +inst_12523: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfe00; +op3val:0xfe55; valaddr_reg:x2; val_offset:37467*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37467*FLEN/8, x3, x1, x4) + +inst_12524: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfe00; +op3val:0x7c01; valaddr_reg:x2; val_offset:37470*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37470*FLEN/8, x3, x1, x4) + +inst_12525: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfe00; +op3val:0xfd55; valaddr_reg:x2; val_offset:37473*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37473*FLEN/8, x3, x1, x4) + +inst_12526: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfe00; +op3val:0x3c00; valaddr_reg:x2; val_offset:37476*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37476*FLEN/8, x3, x1, x4) + +inst_12527: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfe00; +op3val:0xbc00; valaddr_reg:x2; val_offset:37479*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37479*FLEN/8, x3, x1, x4) + +inst_12528: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7e01; +op3val:0x0; valaddr_reg:x2; val_offset:37482*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37482*FLEN/8, x3, x1, x4) + +inst_12529: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7e01; +op3val:0x8000; valaddr_reg:x2; val_offset:37485*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37485*FLEN/8, x3, x1, x4) + +inst_12530: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7e01; +op3val:0x1; valaddr_reg:x2; val_offset:37488*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37488*FLEN/8, x3, x1, x4) + +inst_12531: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7e01; +op3val:0x8001; valaddr_reg:x2; val_offset:37491*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37491*FLEN/8, x3, x1, x4) + +inst_12532: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7e01; +op3val:0x2; valaddr_reg:x2; val_offset:37494*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37494*FLEN/8, x3, x1, x4) + +inst_12533: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7e01; +op3val:0x83fe; valaddr_reg:x2; val_offset:37497*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37497*FLEN/8, x3, x1, x4) + +inst_12534: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7e01; +op3val:0x3ff; valaddr_reg:x2; val_offset:37500*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37500*FLEN/8, x3, x1, x4) + +inst_12535: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7e01; +op3val:0x83ff; valaddr_reg:x2; val_offset:37503*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37503*FLEN/8, x3, x1, x4) + +inst_12536: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7e01; +op3val:0x400; valaddr_reg:x2; val_offset:37506*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37506*FLEN/8, x3, x1, x4) + +inst_12537: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7e01; +op3val:0x8400; valaddr_reg:x2; val_offset:37509*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37509*FLEN/8, x3, x1, x4) + +inst_12538: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7e01; +op3val:0x401; valaddr_reg:x2; val_offset:37512*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37512*FLEN/8, x3, x1, x4) + +inst_12539: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7e01; +op3val:0x8455; valaddr_reg:x2; val_offset:37515*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37515*FLEN/8, x3, x1, x4) + +inst_12540: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7e01; +op3val:0x7bff; valaddr_reg:x2; val_offset:37518*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37518*FLEN/8, x3, x1, x4) + +inst_12541: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7e01; +op3val:0xfbff; valaddr_reg:x2; val_offset:37521*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37521*FLEN/8, x3, x1, x4) + +inst_12542: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7e01; +op3val:0x7c00; valaddr_reg:x2; val_offset:37524*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37524*FLEN/8, x3, x1, x4) + +inst_12543: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7e01; +op3val:0xfc00; valaddr_reg:x2; val_offset:37527*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37527*FLEN/8, x3, x1, x4) + +inst_12544: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7e01; +op3val:0x7e00; valaddr_reg:x2; val_offset:37530*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37530*FLEN/8, x3, x1, x4) + +inst_12545: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7e01; +op3val:0xfe00; valaddr_reg:x2; val_offset:37533*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37533*FLEN/8, x3, x1, x4) + +inst_12546: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7e01; +op3val:0x7e01; valaddr_reg:x2; val_offset:37536*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37536*FLEN/8, x3, x1, x4) + +inst_12547: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7e01; +op3val:0xfe55; valaddr_reg:x2; val_offset:37539*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37539*FLEN/8, x3, x1, x4) + +inst_12548: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7e01; +op3val:0x7c01; valaddr_reg:x2; val_offset:37542*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37542*FLEN/8, x3, x1, x4) + +inst_12549: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7e01; +op3val:0xfd55; valaddr_reg:x2; val_offset:37545*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37545*FLEN/8, x3, x1, x4) + +inst_12550: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7e01; +op3val:0x3c00; valaddr_reg:x2; val_offset:37548*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37548*FLEN/8, x3, x1, x4) + +inst_12551: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7e01; +op3val:0xbc00; valaddr_reg:x2; val_offset:37551*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37551*FLEN/8, x3, x1, x4) + +inst_12552: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfe55; +op3val:0x0; valaddr_reg:x2; val_offset:37554*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37554*FLEN/8, x3, x1, x4) + +inst_12553: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfe55; +op3val:0x8000; valaddr_reg:x2; val_offset:37557*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37557*FLEN/8, x3, x1, x4) + +inst_12554: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfe55; +op3val:0x1; valaddr_reg:x2; val_offset:37560*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37560*FLEN/8, x3, x1, x4) + +inst_12555: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfe55; +op3val:0x8001; valaddr_reg:x2; val_offset:37563*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37563*FLEN/8, x3, x1, x4) + +inst_12556: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfe55; +op3val:0x2; valaddr_reg:x2; val_offset:37566*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37566*FLEN/8, x3, x1, x4) + +inst_12557: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfe55; +op3val:0x83fe; valaddr_reg:x2; val_offset:37569*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37569*FLEN/8, x3, x1, x4) + +inst_12558: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfe55; +op3val:0x3ff; valaddr_reg:x2; val_offset:37572*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37572*FLEN/8, x3, x1, x4) + +inst_12559: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfe55; +op3val:0x83ff; valaddr_reg:x2; val_offset:37575*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37575*FLEN/8, x3, x1, x4) + +inst_12560: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfe55; +op3val:0x400; valaddr_reg:x2; val_offset:37578*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37578*FLEN/8, x3, x1, x4) + +inst_12561: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfe55; +op3val:0x8400; valaddr_reg:x2; val_offset:37581*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37581*FLEN/8, x3, x1, x4) + +inst_12562: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfe55; +op3val:0x401; valaddr_reg:x2; val_offset:37584*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37584*FLEN/8, x3, x1, x4) + +inst_12563: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfe55; +op3val:0x8455; valaddr_reg:x2; val_offset:37587*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37587*FLEN/8, x3, x1, x4) + +inst_12564: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfe55; +op3val:0x7bff; valaddr_reg:x2; val_offset:37590*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37590*FLEN/8, x3, x1, x4) + +inst_12565: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfe55; +op3val:0xfbff; valaddr_reg:x2; val_offset:37593*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37593*FLEN/8, x3, x1, x4) + +inst_12566: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfe55; +op3val:0x7c00; valaddr_reg:x2; val_offset:37596*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37596*FLEN/8, x3, x1, x4) + +inst_12567: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfe55; +op3val:0xfc00; valaddr_reg:x2; val_offset:37599*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37599*FLEN/8, x3, x1, x4) + +inst_12568: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfe55; +op3val:0x7e00; valaddr_reg:x2; val_offset:37602*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37602*FLEN/8, x3, x1, x4) + +inst_12569: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfe55; +op3val:0xfe00; valaddr_reg:x2; val_offset:37605*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37605*FLEN/8, x3, x1, x4) + +inst_12570: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfe55; +op3val:0x7e01; valaddr_reg:x2; val_offset:37608*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37608*FLEN/8, x3, x1, x4) + +inst_12571: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfe55; +op3val:0xfe55; valaddr_reg:x2; val_offset:37611*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37611*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_99) + +inst_12572: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfe55; +op3val:0x7c01; valaddr_reg:x2; val_offset:37614*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37614*FLEN/8, x3, x1, x4) + +inst_12573: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfe55; +op3val:0xfd55; valaddr_reg:x2; val_offset:37617*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37617*FLEN/8, x3, x1, x4) + +inst_12574: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfe55; +op3val:0x3c00; valaddr_reg:x2; val_offset:37620*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37620*FLEN/8, x3, x1, x4) + +inst_12575: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfe55; +op3val:0xbc00; valaddr_reg:x2; val_offset:37623*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37623*FLEN/8, x3, x1, x4) + +inst_12576: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7c01; +op3val:0x0; valaddr_reg:x2; val_offset:37626*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37626*FLEN/8, x3, x1, x4) + +inst_12577: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7c01; +op3val:0x8000; valaddr_reg:x2; val_offset:37629*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37629*FLEN/8, x3, x1, x4) + +inst_12578: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7c01; +op3val:0x1; valaddr_reg:x2; val_offset:37632*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37632*FLEN/8, x3, x1, x4) + +inst_12579: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7c01; +op3val:0x8001; valaddr_reg:x2; val_offset:37635*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37635*FLEN/8, x3, x1, x4) + +inst_12580: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7c01; +op3val:0x2; valaddr_reg:x2; val_offset:37638*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37638*FLEN/8, x3, x1, x4) + +inst_12581: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7c01; +op3val:0x83fe; valaddr_reg:x2; val_offset:37641*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37641*FLEN/8, x3, x1, x4) + +inst_12582: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7c01; +op3val:0x3ff; valaddr_reg:x2; val_offset:37644*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37644*FLEN/8, x3, x1, x4) + +inst_12583: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7c01; +op3val:0x83ff; valaddr_reg:x2; val_offset:37647*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37647*FLEN/8, x3, x1, x4) + +inst_12584: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7c01; +op3val:0x400; valaddr_reg:x2; val_offset:37650*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37650*FLEN/8, x3, x1, x4) + +inst_12585: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7c01; +op3val:0x8400; valaddr_reg:x2; val_offset:37653*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37653*FLEN/8, x3, x1, x4) + +inst_12586: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7c01; +op3val:0x401; valaddr_reg:x2; val_offset:37656*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37656*FLEN/8, x3, x1, x4) + +inst_12587: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7c01; +op3val:0x8455; valaddr_reg:x2; val_offset:37659*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37659*FLEN/8, x3, x1, x4) + +inst_12588: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7c01; +op3val:0x7bff; valaddr_reg:x2; val_offset:37662*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37662*FLEN/8, x3, x1, x4) + +inst_12589: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7c01; +op3val:0xfbff; valaddr_reg:x2; val_offset:37665*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37665*FLEN/8, x3, x1, x4) + +inst_12590: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7c01; +op3val:0x7c00; valaddr_reg:x2; val_offset:37668*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37668*FLEN/8, x3, x1, x4) + +inst_12591: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7c01; +op3val:0xfc00; valaddr_reg:x2; val_offset:37671*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37671*FLEN/8, x3, x1, x4) + +inst_12592: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7c01; +op3val:0x7e00; valaddr_reg:x2; val_offset:37674*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37674*FLEN/8, x3, x1, x4) + +inst_12593: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7c01; +op3val:0xfe00; valaddr_reg:x2; val_offset:37677*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37677*FLEN/8, x3, x1, x4) + +inst_12594: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7c01; +op3val:0x7e01; valaddr_reg:x2; val_offset:37680*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37680*FLEN/8, x3, x1, x4) + +inst_12595: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7c01; +op3val:0xfe55; valaddr_reg:x2; val_offset:37683*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37683*FLEN/8, x3, x1, x4) + +inst_12596: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7c01; +op3val:0x7c01; valaddr_reg:x2; val_offset:37686*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37686*FLEN/8, x3, x1, x4) + +inst_12597: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7c01; +op3val:0xfd55; valaddr_reg:x2; val_offset:37689*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37689*FLEN/8, x3, x1, x4) + +inst_12598: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7c01; +op3val:0x3c00; valaddr_reg:x2; val_offset:37692*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37692*FLEN/8, x3, x1, x4) + +inst_12599: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x7c01; +op3val:0xbc00; valaddr_reg:x2; val_offset:37695*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37695*FLEN/8, x3, x1, x4) + +inst_12600: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfd55; +op3val:0x0; valaddr_reg:x2; val_offset:37698*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37698*FLEN/8, x3, x1, x4) + +inst_12601: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfd55; +op3val:0x8000; valaddr_reg:x2; val_offset:37701*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37701*FLEN/8, x3, x1, x4) + +inst_12602: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfd55; +op3val:0x1; valaddr_reg:x2; val_offset:37704*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37704*FLEN/8, x3, x1, x4) + +inst_12603: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfd55; +op3val:0x8001; valaddr_reg:x2; val_offset:37707*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37707*FLEN/8, x3, x1, x4) + +inst_12604: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfd55; +op3val:0x2; valaddr_reg:x2; val_offset:37710*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37710*FLEN/8, x3, x1, x4) + +inst_12605: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfd55; +op3val:0x83fe; valaddr_reg:x2; val_offset:37713*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37713*FLEN/8, x3, x1, x4) + +inst_12606: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfd55; +op3val:0x3ff; valaddr_reg:x2; val_offset:37716*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37716*FLEN/8, x3, x1, x4) + +inst_12607: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfd55; +op3val:0x83ff; valaddr_reg:x2; val_offset:37719*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37719*FLEN/8, x3, x1, x4) + +inst_12608: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfd55; +op3val:0x400; valaddr_reg:x2; val_offset:37722*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37722*FLEN/8, x3, x1, x4) + +inst_12609: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfd55; +op3val:0x8400; valaddr_reg:x2; val_offset:37725*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37725*FLEN/8, x3, x1, x4) + +inst_12610: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfd55; +op3val:0x401; valaddr_reg:x2; val_offset:37728*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37728*FLEN/8, x3, x1, x4) + +inst_12611: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfd55; +op3val:0x8455; valaddr_reg:x2; val_offset:37731*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37731*FLEN/8, x3, x1, x4) + +inst_12612: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfd55; +op3val:0x7bff; valaddr_reg:x2; val_offset:37734*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37734*FLEN/8, x3, x1, x4) + +inst_12613: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfd55; +op3val:0xfbff; valaddr_reg:x2; val_offset:37737*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37737*FLEN/8, x3, x1, x4) + +inst_12614: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfd55; +op3val:0x7c00; valaddr_reg:x2; val_offset:37740*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37740*FLEN/8, x3, x1, x4) + +inst_12615: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfd55; +op3val:0xfc00; valaddr_reg:x2; val_offset:37743*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37743*FLEN/8, x3, x1, x4) + +inst_12616: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfd55; +op3val:0x7e00; valaddr_reg:x2; val_offset:37746*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37746*FLEN/8, x3, x1, x4) + +inst_12617: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfd55; +op3val:0xfe00; valaddr_reg:x2; val_offset:37749*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37749*FLEN/8, x3, x1, x4) + +inst_12618: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfd55; +op3val:0x7e01; valaddr_reg:x2; val_offset:37752*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37752*FLEN/8, x3, x1, x4) + +inst_12619: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfd55; +op3val:0xfe55; valaddr_reg:x2; val_offset:37755*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37755*FLEN/8, x3, x1, x4) + +inst_12620: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfd55; +op3val:0x7c01; valaddr_reg:x2; val_offset:37758*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37758*FLEN/8, x3, x1, x4) + +inst_12621: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfd55; +op3val:0xfd55; valaddr_reg:x2; val_offset:37761*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37761*FLEN/8, x3, x1, x4) + +inst_12622: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfd55; +op3val:0x3c00; valaddr_reg:x2; val_offset:37764*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37764*FLEN/8, x3, x1, x4) + +inst_12623: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xfd55; +op3val:0xbc00; valaddr_reg:x2; val_offset:37767*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37767*FLEN/8, x3, x1, x4) + +inst_12624: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x3c00; +op3val:0x0; valaddr_reg:x2; val_offset:37770*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37770*FLEN/8, x3, x1, x4) + +inst_12625: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x3c00; +op3val:0x8000; valaddr_reg:x2; val_offset:37773*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37773*FLEN/8, x3, x1, x4) + +inst_12626: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x3c00; +op3val:0x1; valaddr_reg:x2; val_offset:37776*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37776*FLEN/8, x3, x1, x4) + +inst_12627: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x3c00; +op3val:0x8001; valaddr_reg:x2; val_offset:37779*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37779*FLEN/8, x3, x1, x4) + +inst_12628: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x3c00; +op3val:0x2; valaddr_reg:x2; val_offset:37782*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37782*FLEN/8, x3, x1, x4) + +inst_12629: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x3c00; +op3val:0x83fe; valaddr_reg:x2; val_offset:37785*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37785*FLEN/8, x3, x1, x4) + +inst_12630: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x3c00; +op3val:0x3ff; valaddr_reg:x2; val_offset:37788*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37788*FLEN/8, x3, x1, x4) + +inst_12631: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x3c00; +op3val:0x83ff; valaddr_reg:x2; val_offset:37791*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37791*FLEN/8, x3, x1, x4) + +inst_12632: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x3c00; +op3val:0x400; valaddr_reg:x2; val_offset:37794*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37794*FLEN/8, x3, x1, x4) + +inst_12633: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x3c00; +op3val:0x8400; valaddr_reg:x2; val_offset:37797*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37797*FLEN/8, x3, x1, x4) + +inst_12634: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x3c00; +op3val:0x401; valaddr_reg:x2; val_offset:37800*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37800*FLEN/8, x3, x1, x4) + +inst_12635: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x3c00; +op3val:0x8455; valaddr_reg:x2; val_offset:37803*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37803*FLEN/8, x3, x1, x4) + +inst_12636: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x3c00; +op3val:0x7bff; valaddr_reg:x2; val_offset:37806*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37806*FLEN/8, x3, x1, x4) + +inst_12637: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x3c00; +op3val:0xfbff; valaddr_reg:x2; val_offset:37809*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37809*FLEN/8, x3, x1, x4) + +inst_12638: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x3c00; +op3val:0x7c00; valaddr_reg:x2; val_offset:37812*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37812*FLEN/8, x3, x1, x4) + +inst_12639: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x3c00; +op3val:0xfc00; valaddr_reg:x2; val_offset:37815*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37815*FLEN/8, x3, x1, x4) + +inst_12640: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x3c00; +op3val:0x7e00; valaddr_reg:x2; val_offset:37818*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37818*FLEN/8, x3, x1, x4) + +inst_12641: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x3c00; +op3val:0xfe00; valaddr_reg:x2; val_offset:37821*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37821*FLEN/8, x3, x1, x4) + +inst_12642: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x3c00; +op3val:0x7e01; valaddr_reg:x2; val_offset:37824*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37824*FLEN/8, x3, x1, x4) + +inst_12643: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x3c00; +op3val:0xfe55; valaddr_reg:x2; val_offset:37827*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37827*FLEN/8, x3, x1, x4) + +inst_12644: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x3c00; +op3val:0x7c01; valaddr_reg:x2; val_offset:37830*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37830*FLEN/8, x3, x1, x4) + +inst_12645: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x3c00; +op3val:0xfd55; valaddr_reg:x2; val_offset:37833*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37833*FLEN/8, x3, x1, x4) + +inst_12646: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x3c00; +op3val:0x3c00; valaddr_reg:x2; val_offset:37836*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37836*FLEN/8, x3, x1, x4) + +inst_12647: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0x3c00; +op3val:0xbc00; valaddr_reg:x2; val_offset:37839*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37839*FLEN/8, x3, x1, x4) + +inst_12648: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xbc00; +op3val:0x0; valaddr_reg:x2; val_offset:37842*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37842*FLEN/8, x3, x1, x4) + +inst_12649: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xbc00; +op3val:0x8000; valaddr_reg:x2; val_offset:37845*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37845*FLEN/8, x3, x1, x4) + +inst_12650: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xbc00; +op3val:0x1; valaddr_reg:x2; val_offset:37848*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37848*FLEN/8, x3, x1, x4) + +inst_12651: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xbc00; +op3val:0x8001; valaddr_reg:x2; val_offset:37851*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37851*FLEN/8, x3, x1, x4) + +inst_12652: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xbc00; +op3val:0x2; valaddr_reg:x2; val_offset:37854*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37854*FLEN/8, x3, x1, x4) + +inst_12653: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xbc00; +op3val:0x83fe; valaddr_reg:x2; val_offset:37857*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37857*FLEN/8, x3, x1, x4) + +inst_12654: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xbc00; +op3val:0x3ff; valaddr_reg:x2; val_offset:37860*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37860*FLEN/8, x3, x1, x4) + +inst_12655: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xbc00; +op3val:0x83ff; valaddr_reg:x2; val_offset:37863*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37863*FLEN/8, x3, x1, x4) + +inst_12656: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xbc00; +op3val:0x400; valaddr_reg:x2; val_offset:37866*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37866*FLEN/8, x3, x1, x4) + +inst_12657: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xbc00; +op3val:0x8400; valaddr_reg:x2; val_offset:37869*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37869*FLEN/8, x3, x1, x4) + +inst_12658: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xbc00; +op3val:0x401; valaddr_reg:x2; val_offset:37872*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37872*FLEN/8, x3, x1, x4) + +inst_12659: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xbc00; +op3val:0x8455; valaddr_reg:x2; val_offset:37875*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37875*FLEN/8, x3, x1, x4) + +inst_12660: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xbc00; +op3val:0x7bff; valaddr_reg:x2; val_offset:37878*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37878*FLEN/8, x3, x1, x4) + +inst_12661: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xbc00; +op3val:0xfbff; valaddr_reg:x2; val_offset:37881*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37881*FLEN/8, x3, x1, x4) + +inst_12662: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xbc00; +op3val:0x7c00; valaddr_reg:x2; val_offset:37884*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37884*FLEN/8, x3, x1, x4) + +inst_12663: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xbc00; +op3val:0xfc00; valaddr_reg:x2; val_offset:37887*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37887*FLEN/8, x3, x1, x4) + +inst_12664: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xbc00; +op3val:0x7e00; valaddr_reg:x2; val_offset:37890*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37890*FLEN/8, x3, x1, x4) + +inst_12665: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xbc00; +op3val:0xfe00; valaddr_reg:x2; val_offset:37893*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37893*FLEN/8, x3, x1, x4) + +inst_12666: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xbc00; +op3val:0x7e01; valaddr_reg:x2; val_offset:37896*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37896*FLEN/8, x3, x1, x4) + +inst_12667: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xbc00; +op3val:0xfe55; valaddr_reg:x2; val_offset:37899*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37899*FLEN/8, x3, x1, x4) + +inst_12668: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xbc00; +op3val:0x7c01; valaddr_reg:x2; val_offset:37902*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37902*FLEN/8, x3, x1, x4) + +inst_12669: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xbc00; +op3val:0xfd55; valaddr_reg:x2; val_offset:37905*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37905*FLEN/8, x3, x1, x4) + +inst_12670: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xbc00; +op3val:0x3c00; valaddr_reg:x2; val_offset:37908*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37908*FLEN/8, x3, x1, x4) + +inst_12671: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xfd55; op2val:0xbc00; +op3val:0xbc00; valaddr_reg:x2; val_offset:37911*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37911*FLEN/8, x3, x1, x4) + +inst_12672: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x0; +op3val:0x0; valaddr_reg:x2; val_offset:37914*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37914*FLEN/8, x3, x1, x4) + +inst_12673: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x0; +op3val:0x8000; valaddr_reg:x2; val_offset:37917*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37917*FLEN/8, x3, x1, x4) + +inst_12674: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x0; +op3val:0x1; valaddr_reg:x2; val_offset:37920*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37920*FLEN/8, x3, x1, x4) + +inst_12675: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x0; +op3val:0x8001; valaddr_reg:x2; val_offset:37923*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37923*FLEN/8, x3, x1, x4) + +inst_12676: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x0; +op3val:0x2; valaddr_reg:x2; val_offset:37926*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37926*FLEN/8, x3, x1, x4) + +inst_12677: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x0; +op3val:0x83fe; valaddr_reg:x2; val_offset:37929*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37929*FLEN/8, x3, x1, x4) + +inst_12678: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x0; +op3val:0x3ff; valaddr_reg:x2; val_offset:37932*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37932*FLEN/8, x3, x1, x4) + +inst_12679: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x0; +op3val:0x83ff; valaddr_reg:x2; val_offset:37935*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37935*FLEN/8, x3, x1, x4) + +inst_12680: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x0; +op3val:0x400; valaddr_reg:x2; val_offset:37938*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37938*FLEN/8, x3, x1, x4) + +inst_12681: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x0; +op3val:0x8400; valaddr_reg:x2; val_offset:37941*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37941*FLEN/8, x3, x1, x4) + +inst_12682: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x0; +op3val:0x401; valaddr_reg:x2; val_offset:37944*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37944*FLEN/8, x3, x1, x4) + +inst_12683: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x0; +op3val:0x8455; valaddr_reg:x2; val_offset:37947*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37947*FLEN/8, x3, x1, x4) + +inst_12684: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x0; +op3val:0x7bff; valaddr_reg:x2; val_offset:37950*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37950*FLEN/8, x3, x1, x4) + +inst_12685: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x0; +op3val:0xfbff; valaddr_reg:x2; val_offset:37953*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37953*FLEN/8, x3, x1, x4) + +inst_12686: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x0; +op3val:0x7c00; valaddr_reg:x2; val_offset:37956*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37956*FLEN/8, x3, x1, x4) + +inst_12687: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x0; +op3val:0xfc00; valaddr_reg:x2; val_offset:37959*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37959*FLEN/8, x3, x1, x4) + +inst_12688: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x0; +op3val:0x7e00; valaddr_reg:x2; val_offset:37962*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37962*FLEN/8, x3, x1, x4) + +inst_12689: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x0; +op3val:0xfe00; valaddr_reg:x2; val_offset:37965*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37965*FLEN/8, x3, x1, x4) + +inst_12690: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x0; +op3val:0x7e01; valaddr_reg:x2; val_offset:37968*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37968*FLEN/8, x3, x1, x4) + +inst_12691: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x0; +op3val:0xfe55; valaddr_reg:x2; val_offset:37971*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37971*FLEN/8, x3, x1, x4) + +inst_12692: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x0; +op3val:0x7c01; valaddr_reg:x2; val_offset:37974*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37974*FLEN/8, x3, x1, x4) + +inst_12693: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x0; +op3val:0xfd55; valaddr_reg:x2; val_offset:37977*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37977*FLEN/8, x3, x1, x4) + +inst_12694: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x0; +op3val:0x3c00; valaddr_reg:x2; val_offset:37980*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37980*FLEN/8, x3, x1, x4) + +inst_12695: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x0; +op3val:0xbc00; valaddr_reg:x2; val_offset:37983*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37983*FLEN/8, x3, x1, x4) + +inst_12696: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8000; +op3val:0x0; valaddr_reg:x2; val_offset:37986*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37986*FLEN/8, x3, x1, x4) + +inst_12697: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8000; +op3val:0x8000; valaddr_reg:x2; val_offset:37989*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37989*FLEN/8, x3, x1, x4) + +inst_12698: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8000; +op3val:0x1; valaddr_reg:x2; val_offset:37992*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37992*FLEN/8, x3, x1, x4) + +inst_12699: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8000; +op3val:0x8001; valaddr_reg:x2; val_offset:37995*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37995*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_100) + +inst_12700: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8000; +op3val:0x2; valaddr_reg:x2; val_offset:37998*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 37998*FLEN/8, x3, x1, x4) + +inst_12701: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8000; +op3val:0x83fe; valaddr_reg:x2; val_offset:38001*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38001*FLEN/8, x3, x1, x4) + +inst_12702: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8000; +op3val:0x3ff; valaddr_reg:x2; val_offset:38004*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38004*FLEN/8, x3, x1, x4) + +inst_12703: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8000; +op3val:0x83ff; valaddr_reg:x2; val_offset:38007*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38007*FLEN/8, x3, x1, x4) + +inst_12704: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8000; +op3val:0x400; valaddr_reg:x2; val_offset:38010*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38010*FLEN/8, x3, x1, x4) + +inst_12705: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8000; +op3val:0x8400; valaddr_reg:x2; val_offset:38013*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38013*FLEN/8, x3, x1, x4) + +inst_12706: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8000; +op3val:0x401; valaddr_reg:x2; val_offset:38016*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38016*FLEN/8, x3, x1, x4) + +inst_12707: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8000; +op3val:0x8455; valaddr_reg:x2; val_offset:38019*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38019*FLEN/8, x3, x1, x4) + +inst_12708: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x2; val_offset:38022*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38022*FLEN/8, x3, x1, x4) + +inst_12709: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x2; val_offset:38025*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38025*FLEN/8, x3, x1, x4) + +inst_12710: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8000; +op3val:0x7c00; valaddr_reg:x2; val_offset:38028*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38028*FLEN/8, x3, x1, x4) + +inst_12711: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8000; +op3val:0xfc00; valaddr_reg:x2; val_offset:38031*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38031*FLEN/8, x3, x1, x4) + +inst_12712: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8000; +op3val:0x7e00; valaddr_reg:x2; val_offset:38034*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38034*FLEN/8, x3, x1, x4) + +inst_12713: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8000; +op3val:0xfe00; valaddr_reg:x2; val_offset:38037*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38037*FLEN/8, x3, x1, x4) + +inst_12714: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8000; +op3val:0x7e01; valaddr_reg:x2; val_offset:38040*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38040*FLEN/8, x3, x1, x4) + +inst_12715: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8000; +op3val:0xfe55; valaddr_reg:x2; val_offset:38043*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38043*FLEN/8, x3, x1, x4) + +inst_12716: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8000; +op3val:0x7c01; valaddr_reg:x2; val_offset:38046*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38046*FLEN/8, x3, x1, x4) + +inst_12717: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8000; +op3val:0xfd55; valaddr_reg:x2; val_offset:38049*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38049*FLEN/8, x3, x1, x4) + +inst_12718: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8000; +op3val:0x3c00; valaddr_reg:x2; val_offset:38052*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38052*FLEN/8, x3, x1, x4) + +inst_12719: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8000; +op3val:0xbc00; valaddr_reg:x2; val_offset:38055*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38055*FLEN/8, x3, x1, x4) + +inst_12720: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x1; +op3val:0x0; valaddr_reg:x2; val_offset:38058*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38058*FLEN/8, x3, x1, x4) + +inst_12721: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x1; +op3val:0x8000; valaddr_reg:x2; val_offset:38061*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38061*FLEN/8, x3, x1, x4) + +inst_12722: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x1; +op3val:0x1; valaddr_reg:x2; val_offset:38064*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38064*FLEN/8, x3, x1, x4) + +inst_12723: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x1; +op3val:0x8001; valaddr_reg:x2; val_offset:38067*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38067*FLEN/8, x3, x1, x4) + +inst_12724: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x1; +op3val:0x2; valaddr_reg:x2; val_offset:38070*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38070*FLEN/8, x3, x1, x4) + +inst_12725: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x1; +op3val:0x83fe; valaddr_reg:x2; val_offset:38073*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38073*FLEN/8, x3, x1, x4) + +inst_12726: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x1; +op3val:0x3ff; valaddr_reg:x2; val_offset:38076*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38076*FLEN/8, x3, x1, x4) + +inst_12727: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x1; +op3val:0x83ff; valaddr_reg:x2; val_offset:38079*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38079*FLEN/8, x3, x1, x4) + +inst_12728: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x1; +op3val:0x400; valaddr_reg:x2; val_offset:38082*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38082*FLEN/8, x3, x1, x4) + +inst_12729: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x1; +op3val:0x8400; valaddr_reg:x2; val_offset:38085*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38085*FLEN/8, x3, x1, x4) + +inst_12730: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x1; +op3val:0x401; valaddr_reg:x2; val_offset:38088*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38088*FLEN/8, x3, x1, x4) + +inst_12731: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x1; +op3val:0x8455; valaddr_reg:x2; val_offset:38091*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38091*FLEN/8, x3, x1, x4) + +inst_12732: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x1; +op3val:0x7bff; valaddr_reg:x2; val_offset:38094*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38094*FLEN/8, x3, x1, x4) + +inst_12733: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x1; +op3val:0xfbff; valaddr_reg:x2; val_offset:38097*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38097*FLEN/8, x3, x1, x4) + +inst_12734: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x1; +op3val:0x7c00; valaddr_reg:x2; val_offset:38100*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38100*FLEN/8, x3, x1, x4) + +inst_12735: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x1; +op3val:0xfc00; valaddr_reg:x2; val_offset:38103*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38103*FLEN/8, x3, x1, x4) + +inst_12736: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x1; +op3val:0x7e00; valaddr_reg:x2; val_offset:38106*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38106*FLEN/8, x3, x1, x4) + +inst_12737: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x1; +op3val:0xfe00; valaddr_reg:x2; val_offset:38109*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38109*FLEN/8, x3, x1, x4) + +inst_12738: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x1; +op3val:0x7e01; valaddr_reg:x2; val_offset:38112*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38112*FLEN/8, x3, x1, x4) + +inst_12739: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x1; +op3val:0xfe55; valaddr_reg:x2; val_offset:38115*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38115*FLEN/8, x3, x1, x4) + +inst_12740: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x1; +op3val:0x7c01; valaddr_reg:x2; val_offset:38118*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38118*FLEN/8, x3, x1, x4) + +inst_12741: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x1; +op3val:0xfd55; valaddr_reg:x2; val_offset:38121*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38121*FLEN/8, x3, x1, x4) + +inst_12742: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x1; +op3val:0x3c00; valaddr_reg:x2; val_offset:38124*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38124*FLEN/8, x3, x1, x4) + +inst_12743: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x1; +op3val:0xbc00; valaddr_reg:x2; val_offset:38127*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38127*FLEN/8, x3, x1, x4) + +inst_12744: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8001; +op3val:0x0; valaddr_reg:x2; val_offset:38130*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38130*FLEN/8, x3, x1, x4) + +inst_12745: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8001; +op3val:0x8000; valaddr_reg:x2; val_offset:38133*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38133*FLEN/8, x3, x1, x4) + +inst_12746: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8001; +op3val:0x1; valaddr_reg:x2; val_offset:38136*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38136*FLEN/8, x3, x1, x4) + +inst_12747: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8001; +op3val:0x8001; valaddr_reg:x2; val_offset:38139*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38139*FLEN/8, x3, x1, x4) + +inst_12748: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8001; +op3val:0x2; valaddr_reg:x2; val_offset:38142*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38142*FLEN/8, x3, x1, x4) + +inst_12749: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8001; +op3val:0x83fe; valaddr_reg:x2; val_offset:38145*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38145*FLEN/8, x3, x1, x4) + +inst_12750: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8001; +op3val:0x3ff; valaddr_reg:x2; val_offset:38148*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38148*FLEN/8, x3, x1, x4) + +inst_12751: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8001; +op3val:0x83ff; valaddr_reg:x2; val_offset:38151*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38151*FLEN/8, x3, x1, x4) + +inst_12752: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8001; +op3val:0x400; valaddr_reg:x2; val_offset:38154*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38154*FLEN/8, x3, x1, x4) + +inst_12753: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8001; +op3val:0x8400; valaddr_reg:x2; val_offset:38157*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38157*FLEN/8, x3, x1, x4) + +inst_12754: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8001; +op3val:0x401; valaddr_reg:x2; val_offset:38160*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38160*FLEN/8, x3, x1, x4) + +inst_12755: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8001; +op3val:0x8455; valaddr_reg:x2; val_offset:38163*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38163*FLEN/8, x3, x1, x4) + +inst_12756: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8001; +op3val:0x7bff; valaddr_reg:x2; val_offset:38166*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38166*FLEN/8, x3, x1, x4) + +inst_12757: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8001; +op3val:0xfbff; valaddr_reg:x2; val_offset:38169*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38169*FLEN/8, x3, x1, x4) + +inst_12758: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8001; +op3val:0x7c00; valaddr_reg:x2; val_offset:38172*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38172*FLEN/8, x3, x1, x4) + +inst_12759: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8001; +op3val:0xfc00; valaddr_reg:x2; val_offset:38175*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38175*FLEN/8, x3, x1, x4) + +inst_12760: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8001; +op3val:0x7e00; valaddr_reg:x2; val_offset:38178*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38178*FLEN/8, x3, x1, x4) + +inst_12761: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8001; +op3val:0xfe00; valaddr_reg:x2; val_offset:38181*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38181*FLEN/8, x3, x1, x4) + +inst_12762: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8001; +op3val:0x7e01; valaddr_reg:x2; val_offset:38184*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38184*FLEN/8, x3, x1, x4) + +inst_12763: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8001; +op3val:0xfe55; valaddr_reg:x2; val_offset:38187*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38187*FLEN/8, x3, x1, x4) + +inst_12764: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8001; +op3val:0x7c01; valaddr_reg:x2; val_offset:38190*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38190*FLEN/8, x3, x1, x4) + +inst_12765: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8001; +op3val:0xfd55; valaddr_reg:x2; val_offset:38193*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38193*FLEN/8, x3, x1, x4) + +inst_12766: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8001; +op3val:0x3c00; valaddr_reg:x2; val_offset:38196*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38196*FLEN/8, x3, x1, x4) + +inst_12767: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8001; +op3val:0xbc00; valaddr_reg:x2; val_offset:38199*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38199*FLEN/8, x3, x1, x4) + +inst_12768: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x2; +op3val:0x0; valaddr_reg:x2; val_offset:38202*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38202*FLEN/8, x3, x1, x4) + +inst_12769: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x2; +op3val:0x8000; valaddr_reg:x2; val_offset:38205*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38205*FLEN/8, x3, x1, x4) + +inst_12770: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x2; +op3val:0x1; valaddr_reg:x2; val_offset:38208*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38208*FLEN/8, x3, x1, x4) + +inst_12771: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x2; +op3val:0x8001; valaddr_reg:x2; val_offset:38211*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38211*FLEN/8, x3, x1, x4) + +inst_12772: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x2; +op3val:0x2; valaddr_reg:x2; val_offset:38214*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38214*FLEN/8, x3, x1, x4) + +inst_12773: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x2; +op3val:0x83fe; valaddr_reg:x2; val_offset:38217*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38217*FLEN/8, x3, x1, x4) + +inst_12774: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x2; +op3val:0x3ff; valaddr_reg:x2; val_offset:38220*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38220*FLEN/8, x3, x1, x4) + +inst_12775: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x2; +op3val:0x83ff; valaddr_reg:x2; val_offset:38223*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38223*FLEN/8, x3, x1, x4) + +inst_12776: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x2; +op3val:0x400; valaddr_reg:x2; val_offset:38226*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38226*FLEN/8, x3, x1, x4) + +inst_12777: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x2; +op3val:0x8400; valaddr_reg:x2; val_offset:38229*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38229*FLEN/8, x3, x1, x4) + +inst_12778: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x2; +op3val:0x401; valaddr_reg:x2; val_offset:38232*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38232*FLEN/8, x3, x1, x4) + +inst_12779: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x2; +op3val:0x8455; valaddr_reg:x2; val_offset:38235*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38235*FLEN/8, x3, x1, x4) + +inst_12780: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x2; +op3val:0x7bff; valaddr_reg:x2; val_offset:38238*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38238*FLEN/8, x3, x1, x4) + +inst_12781: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x2; +op3val:0xfbff; valaddr_reg:x2; val_offset:38241*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38241*FLEN/8, x3, x1, x4) + +inst_12782: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x2; +op3val:0x7c00; valaddr_reg:x2; val_offset:38244*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38244*FLEN/8, x3, x1, x4) + +inst_12783: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x2; +op3val:0xfc00; valaddr_reg:x2; val_offset:38247*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38247*FLEN/8, x3, x1, x4) + +inst_12784: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x2; +op3val:0x7e00; valaddr_reg:x2; val_offset:38250*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38250*FLEN/8, x3, x1, x4) + +inst_12785: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x2; +op3val:0xfe00; valaddr_reg:x2; val_offset:38253*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38253*FLEN/8, x3, x1, x4) + +inst_12786: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x2; +op3val:0x7e01; valaddr_reg:x2; val_offset:38256*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38256*FLEN/8, x3, x1, x4) + +inst_12787: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x2; +op3val:0xfe55; valaddr_reg:x2; val_offset:38259*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38259*FLEN/8, x3, x1, x4) + +inst_12788: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x2; +op3val:0x7c01; valaddr_reg:x2; val_offset:38262*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38262*FLEN/8, x3, x1, x4) + +inst_12789: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x2; +op3val:0xfd55; valaddr_reg:x2; val_offset:38265*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38265*FLEN/8, x3, x1, x4) + +inst_12790: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x2; +op3val:0x3c00; valaddr_reg:x2; val_offset:38268*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38268*FLEN/8, x3, x1, x4) + +inst_12791: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x2; +op3val:0xbc00; valaddr_reg:x2; val_offset:38271*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38271*FLEN/8, x3, x1, x4) + +inst_12792: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x83fe; +op3val:0x0; valaddr_reg:x2; val_offset:38274*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38274*FLEN/8, x3, x1, x4) + +inst_12793: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x83fe; +op3val:0x8000; valaddr_reg:x2; val_offset:38277*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38277*FLEN/8, x3, x1, x4) + +inst_12794: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x83fe; +op3val:0x1; valaddr_reg:x2; val_offset:38280*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38280*FLEN/8, x3, x1, x4) + +inst_12795: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x83fe; +op3val:0x8001; valaddr_reg:x2; val_offset:38283*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38283*FLEN/8, x3, x1, x4) + +inst_12796: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x83fe; +op3val:0x2; valaddr_reg:x2; val_offset:38286*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38286*FLEN/8, x3, x1, x4) + +inst_12797: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x83fe; +op3val:0x83fe; valaddr_reg:x2; val_offset:38289*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38289*FLEN/8, x3, x1, x4) + +inst_12798: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x83fe; +op3val:0x3ff; valaddr_reg:x2; val_offset:38292*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38292*FLEN/8, x3, x1, x4) + +inst_12799: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x83fe; +op3val:0x83ff; valaddr_reg:x2; val_offset:38295*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38295*FLEN/8, x3, x1, x4) + +inst_12800: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x83fe; +op3val:0x400; valaddr_reg:x2; val_offset:38298*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38298*FLEN/8, x3, x1, x4) + +inst_12801: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x83fe; +op3val:0x8400; valaddr_reg:x2; val_offset:38301*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38301*FLEN/8, x3, x1, x4) + +inst_12802: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x83fe; +op3val:0x401; valaddr_reg:x2; val_offset:38304*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38304*FLEN/8, x3, x1, x4) + +inst_12803: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x83fe; +op3val:0x8455; valaddr_reg:x2; val_offset:38307*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38307*FLEN/8, x3, x1, x4) + +inst_12804: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x83fe; +op3val:0x7bff; valaddr_reg:x2; val_offset:38310*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38310*FLEN/8, x3, x1, x4) + +inst_12805: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x83fe; +op3val:0xfbff; valaddr_reg:x2; val_offset:38313*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38313*FLEN/8, x3, x1, x4) + +inst_12806: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x83fe; +op3val:0x7c00; valaddr_reg:x2; val_offset:38316*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38316*FLEN/8, x3, x1, x4) + +inst_12807: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x83fe; +op3val:0xfc00; valaddr_reg:x2; val_offset:38319*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38319*FLEN/8, x3, x1, x4) + +inst_12808: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x83fe; +op3val:0x7e00; valaddr_reg:x2; val_offset:38322*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38322*FLEN/8, x3, x1, x4) + +inst_12809: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x83fe; +op3val:0xfe00; valaddr_reg:x2; val_offset:38325*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38325*FLEN/8, x3, x1, x4) + +inst_12810: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x83fe; +op3val:0x7e01; valaddr_reg:x2; val_offset:38328*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38328*FLEN/8, x3, x1, x4) + +inst_12811: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x83fe; +op3val:0xfe55; valaddr_reg:x2; val_offset:38331*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38331*FLEN/8, x3, x1, x4) + +inst_12812: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x83fe; +op3val:0x7c01; valaddr_reg:x2; val_offset:38334*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38334*FLEN/8, x3, x1, x4) + +inst_12813: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x83fe; +op3val:0xfd55; valaddr_reg:x2; val_offset:38337*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38337*FLEN/8, x3, x1, x4) + +inst_12814: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x83fe; +op3val:0x3c00; valaddr_reg:x2; val_offset:38340*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38340*FLEN/8, x3, x1, x4) + +inst_12815: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x83fe; +op3val:0xbc00; valaddr_reg:x2; val_offset:38343*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38343*FLEN/8, x3, x1, x4) + +inst_12816: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x3ff; +op3val:0x0; valaddr_reg:x2; val_offset:38346*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38346*FLEN/8, x3, x1, x4) + +inst_12817: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x3ff; +op3val:0x8000; valaddr_reg:x2; val_offset:38349*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38349*FLEN/8, x3, x1, x4) + +inst_12818: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x3ff; +op3val:0x1; valaddr_reg:x2; val_offset:38352*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38352*FLEN/8, x3, x1, x4) + +inst_12819: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x3ff; +op3val:0x8001; valaddr_reg:x2; val_offset:38355*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38355*FLEN/8, x3, x1, x4) + +inst_12820: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x3ff; +op3val:0x2; valaddr_reg:x2; val_offset:38358*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38358*FLEN/8, x3, x1, x4) + +inst_12821: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x3ff; +op3val:0x83fe; valaddr_reg:x2; val_offset:38361*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38361*FLEN/8, x3, x1, x4) + +inst_12822: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x3ff; +op3val:0x3ff; valaddr_reg:x2; val_offset:38364*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38364*FLEN/8, x3, x1, x4) + +inst_12823: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x3ff; +op3val:0x83ff; valaddr_reg:x2; val_offset:38367*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38367*FLEN/8, x3, x1, x4) + +inst_12824: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x3ff; +op3val:0x400; valaddr_reg:x2; val_offset:38370*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38370*FLEN/8, x3, x1, x4) + +inst_12825: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x3ff; +op3val:0x8400; valaddr_reg:x2; val_offset:38373*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38373*FLEN/8, x3, x1, x4) + +inst_12826: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x3ff; +op3val:0x401; valaddr_reg:x2; val_offset:38376*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38376*FLEN/8, x3, x1, x4) + +inst_12827: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x3ff; +op3val:0x8455; valaddr_reg:x2; val_offset:38379*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38379*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_101) + +inst_12828: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x3ff; +op3val:0x7bff; valaddr_reg:x2; val_offset:38382*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38382*FLEN/8, x3, x1, x4) + +inst_12829: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x3ff; +op3val:0xfbff; valaddr_reg:x2; val_offset:38385*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38385*FLEN/8, x3, x1, x4) + +inst_12830: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x3ff; +op3val:0x7c00; valaddr_reg:x2; val_offset:38388*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38388*FLEN/8, x3, x1, x4) + +inst_12831: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x3ff; +op3val:0xfc00; valaddr_reg:x2; val_offset:38391*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38391*FLEN/8, x3, x1, x4) + +inst_12832: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x3ff; +op3val:0x7e00; valaddr_reg:x2; val_offset:38394*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38394*FLEN/8, x3, x1, x4) + +inst_12833: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x3ff; +op3val:0xfe00; valaddr_reg:x2; val_offset:38397*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38397*FLEN/8, x3, x1, x4) + +inst_12834: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x3ff; +op3val:0x7e01; valaddr_reg:x2; val_offset:38400*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38400*FLEN/8, x3, x1, x4) + +inst_12835: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x3ff; +op3val:0xfe55; valaddr_reg:x2; val_offset:38403*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38403*FLEN/8, x3, x1, x4) + +inst_12836: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x3ff; +op3val:0x7c01; valaddr_reg:x2; val_offset:38406*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38406*FLEN/8, x3, x1, x4) + +inst_12837: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x3ff; +op3val:0xfd55; valaddr_reg:x2; val_offset:38409*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38409*FLEN/8, x3, x1, x4) + +inst_12838: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x3ff; +op3val:0x3c00; valaddr_reg:x2; val_offset:38412*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38412*FLEN/8, x3, x1, x4) + +inst_12839: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x3ff; +op3val:0xbc00; valaddr_reg:x2; val_offset:38415*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38415*FLEN/8, x3, x1, x4) + +inst_12840: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x83ff; +op3val:0x0; valaddr_reg:x2; val_offset:38418*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38418*FLEN/8, x3, x1, x4) + +inst_12841: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x83ff; +op3val:0x8000; valaddr_reg:x2; val_offset:38421*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38421*FLEN/8, x3, x1, x4) + +inst_12842: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x83ff; +op3val:0x1; valaddr_reg:x2; val_offset:38424*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38424*FLEN/8, x3, x1, x4) + +inst_12843: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x83ff; +op3val:0x8001; valaddr_reg:x2; val_offset:38427*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38427*FLEN/8, x3, x1, x4) + +inst_12844: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x83ff; +op3val:0x2; valaddr_reg:x2; val_offset:38430*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38430*FLEN/8, x3, x1, x4) + +inst_12845: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x83ff; +op3val:0x83fe; valaddr_reg:x2; val_offset:38433*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38433*FLEN/8, x3, x1, x4) + +inst_12846: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x83ff; +op3val:0x3ff; valaddr_reg:x2; val_offset:38436*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38436*FLEN/8, x3, x1, x4) + +inst_12847: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x83ff; +op3val:0x83ff; valaddr_reg:x2; val_offset:38439*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38439*FLEN/8, x3, x1, x4) + +inst_12848: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x83ff; +op3val:0x400; valaddr_reg:x2; val_offset:38442*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38442*FLEN/8, x3, x1, x4) + +inst_12849: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x83ff; +op3val:0x8400; valaddr_reg:x2; val_offset:38445*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38445*FLEN/8, x3, x1, x4) + +inst_12850: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x83ff; +op3val:0x401; valaddr_reg:x2; val_offset:38448*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38448*FLEN/8, x3, x1, x4) + +inst_12851: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x83ff; +op3val:0x8455; valaddr_reg:x2; val_offset:38451*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38451*FLEN/8, x3, x1, x4) + +inst_12852: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x83ff; +op3val:0x7bff; valaddr_reg:x2; val_offset:38454*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38454*FLEN/8, x3, x1, x4) + +inst_12853: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x83ff; +op3val:0xfbff; valaddr_reg:x2; val_offset:38457*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38457*FLEN/8, x3, x1, x4) + +inst_12854: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x83ff; +op3val:0x7c00; valaddr_reg:x2; val_offset:38460*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38460*FLEN/8, x3, x1, x4) + +inst_12855: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x83ff; +op3val:0xfc00; valaddr_reg:x2; val_offset:38463*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38463*FLEN/8, x3, x1, x4) + +inst_12856: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x83ff; +op3val:0x7e00; valaddr_reg:x2; val_offset:38466*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38466*FLEN/8, x3, x1, x4) + +inst_12857: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x83ff; +op3val:0xfe00; valaddr_reg:x2; val_offset:38469*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38469*FLEN/8, x3, x1, x4) + +inst_12858: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x83ff; +op3val:0x7e01; valaddr_reg:x2; val_offset:38472*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38472*FLEN/8, x3, x1, x4) + +inst_12859: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x83ff; +op3val:0xfe55; valaddr_reg:x2; val_offset:38475*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38475*FLEN/8, x3, x1, x4) + +inst_12860: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x83ff; +op3val:0x7c01; valaddr_reg:x2; val_offset:38478*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38478*FLEN/8, x3, x1, x4) + +inst_12861: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x83ff; +op3val:0xfd55; valaddr_reg:x2; val_offset:38481*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38481*FLEN/8, x3, x1, x4) + +inst_12862: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x83ff; +op3val:0x3c00; valaddr_reg:x2; val_offset:38484*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38484*FLEN/8, x3, x1, x4) + +inst_12863: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x83ff; +op3val:0xbc00; valaddr_reg:x2; val_offset:38487*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38487*FLEN/8, x3, x1, x4) + +inst_12864: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x400; +op3val:0x0; valaddr_reg:x2; val_offset:38490*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38490*FLEN/8, x3, x1, x4) + +inst_12865: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x400; +op3val:0x8000; valaddr_reg:x2; val_offset:38493*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38493*FLEN/8, x3, x1, x4) + +inst_12866: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x400; +op3val:0x1; valaddr_reg:x2; val_offset:38496*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38496*FLEN/8, x3, x1, x4) + +inst_12867: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x400; +op3val:0x8001; valaddr_reg:x2; val_offset:38499*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38499*FLEN/8, x3, x1, x4) + +inst_12868: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x400; +op3val:0x2; valaddr_reg:x2; val_offset:38502*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38502*FLEN/8, x3, x1, x4) + +inst_12869: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x400; +op3val:0x83fe; valaddr_reg:x2; val_offset:38505*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38505*FLEN/8, x3, x1, x4) + +inst_12870: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x400; +op3val:0x3ff; valaddr_reg:x2; val_offset:38508*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38508*FLEN/8, x3, x1, x4) + +inst_12871: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x400; +op3val:0x83ff; valaddr_reg:x2; val_offset:38511*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38511*FLEN/8, x3, x1, x4) + +inst_12872: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x400; +op3val:0x400; valaddr_reg:x2; val_offset:38514*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38514*FLEN/8, x3, x1, x4) + +inst_12873: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x400; +op3val:0x8400; valaddr_reg:x2; val_offset:38517*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38517*FLEN/8, x3, x1, x4) + +inst_12874: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x400; +op3val:0x401; valaddr_reg:x2; val_offset:38520*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38520*FLEN/8, x3, x1, x4) + +inst_12875: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x400; +op3val:0x8455; valaddr_reg:x2; val_offset:38523*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38523*FLEN/8, x3, x1, x4) + +inst_12876: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x400; +op3val:0x7bff; valaddr_reg:x2; val_offset:38526*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38526*FLEN/8, x3, x1, x4) + +inst_12877: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x400; +op3val:0xfbff; valaddr_reg:x2; val_offset:38529*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38529*FLEN/8, x3, x1, x4) + +inst_12878: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x400; +op3val:0x7c00; valaddr_reg:x2; val_offset:38532*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38532*FLEN/8, x3, x1, x4) + +inst_12879: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x400; +op3val:0xfc00; valaddr_reg:x2; val_offset:38535*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38535*FLEN/8, x3, x1, x4) + +inst_12880: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x400; +op3val:0x7e00; valaddr_reg:x2; val_offset:38538*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38538*FLEN/8, x3, x1, x4) + +inst_12881: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x400; +op3val:0xfe00; valaddr_reg:x2; val_offset:38541*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38541*FLEN/8, x3, x1, x4) + +inst_12882: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x400; +op3val:0x7e01; valaddr_reg:x2; val_offset:38544*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38544*FLEN/8, x3, x1, x4) + +inst_12883: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x400; +op3val:0xfe55; valaddr_reg:x2; val_offset:38547*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38547*FLEN/8, x3, x1, x4) + +inst_12884: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x400; +op3val:0x7c01; valaddr_reg:x2; val_offset:38550*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38550*FLEN/8, x3, x1, x4) + +inst_12885: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x400; +op3val:0xfd55; valaddr_reg:x2; val_offset:38553*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38553*FLEN/8, x3, x1, x4) + +inst_12886: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x400; +op3val:0x3c00; valaddr_reg:x2; val_offset:38556*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38556*FLEN/8, x3, x1, x4) + +inst_12887: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x400; +op3val:0xbc00; valaddr_reg:x2; val_offset:38559*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38559*FLEN/8, x3, x1, x4) + +inst_12888: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8400; +op3val:0x0; valaddr_reg:x2; val_offset:38562*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38562*FLEN/8, x3, x1, x4) + +inst_12889: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8400; +op3val:0x8000; valaddr_reg:x2; val_offset:38565*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38565*FLEN/8, x3, x1, x4) + +inst_12890: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8400; +op3val:0x1; valaddr_reg:x2; val_offset:38568*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38568*FLEN/8, x3, x1, x4) + +inst_12891: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8400; +op3val:0x8001; valaddr_reg:x2; val_offset:38571*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38571*FLEN/8, x3, x1, x4) + +inst_12892: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8400; +op3val:0x2; valaddr_reg:x2; val_offset:38574*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38574*FLEN/8, x3, x1, x4) + +inst_12893: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8400; +op3val:0x83fe; valaddr_reg:x2; val_offset:38577*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38577*FLEN/8, x3, x1, x4) + +inst_12894: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8400; +op3val:0x3ff; valaddr_reg:x2; val_offset:38580*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38580*FLEN/8, x3, x1, x4) + +inst_12895: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8400; +op3val:0x83ff; valaddr_reg:x2; val_offset:38583*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38583*FLEN/8, x3, x1, x4) + +inst_12896: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8400; +op3val:0x400; valaddr_reg:x2; val_offset:38586*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38586*FLEN/8, x3, x1, x4) + +inst_12897: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8400; +op3val:0x8400; valaddr_reg:x2; val_offset:38589*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38589*FLEN/8, x3, x1, x4) + +inst_12898: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8400; +op3val:0x401; valaddr_reg:x2; val_offset:38592*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38592*FLEN/8, x3, x1, x4) + +inst_12899: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8400; +op3val:0x8455; valaddr_reg:x2; val_offset:38595*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38595*FLEN/8, x3, x1, x4) + +inst_12900: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8400; +op3val:0x7bff; valaddr_reg:x2; val_offset:38598*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38598*FLEN/8, x3, x1, x4) + +inst_12901: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8400; +op3val:0xfbff; valaddr_reg:x2; val_offset:38601*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38601*FLEN/8, x3, x1, x4) + +inst_12902: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8400; +op3val:0x7c00; valaddr_reg:x2; val_offset:38604*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38604*FLEN/8, x3, x1, x4) + +inst_12903: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8400; +op3val:0xfc00; valaddr_reg:x2; val_offset:38607*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38607*FLEN/8, x3, x1, x4) + +inst_12904: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8400; +op3val:0x7e00; valaddr_reg:x2; val_offset:38610*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38610*FLEN/8, x3, x1, x4) + +inst_12905: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8400; +op3val:0xfe00; valaddr_reg:x2; val_offset:38613*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38613*FLEN/8, x3, x1, x4) + +inst_12906: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8400; +op3val:0x7e01; valaddr_reg:x2; val_offset:38616*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38616*FLEN/8, x3, x1, x4) + +inst_12907: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8400; +op3val:0xfe55; valaddr_reg:x2; val_offset:38619*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38619*FLEN/8, x3, x1, x4) + +inst_12908: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8400; +op3val:0x7c01; valaddr_reg:x2; val_offset:38622*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38622*FLEN/8, x3, x1, x4) + +inst_12909: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8400; +op3val:0xfd55; valaddr_reg:x2; val_offset:38625*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38625*FLEN/8, x3, x1, x4) + +inst_12910: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8400; +op3val:0x3c00; valaddr_reg:x2; val_offset:38628*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38628*FLEN/8, x3, x1, x4) + +inst_12911: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8400; +op3val:0xbc00; valaddr_reg:x2; val_offset:38631*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38631*FLEN/8, x3, x1, x4) + +inst_12912: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x401; +op3val:0x0; valaddr_reg:x2; val_offset:38634*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38634*FLEN/8, x3, x1, x4) + +inst_12913: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x401; +op3val:0x8000; valaddr_reg:x2; val_offset:38637*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38637*FLEN/8, x3, x1, x4) + +inst_12914: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x401; +op3val:0x1; valaddr_reg:x2; val_offset:38640*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38640*FLEN/8, x3, x1, x4) + +inst_12915: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x401; +op3val:0x8001; valaddr_reg:x2; val_offset:38643*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38643*FLEN/8, x3, x1, x4) + +inst_12916: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x401; +op3val:0x2; valaddr_reg:x2; val_offset:38646*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38646*FLEN/8, x3, x1, x4) + +inst_12917: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x401; +op3val:0x83fe; valaddr_reg:x2; val_offset:38649*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38649*FLEN/8, x3, x1, x4) + +inst_12918: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x401; +op3val:0x3ff; valaddr_reg:x2; val_offset:38652*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38652*FLEN/8, x3, x1, x4) + +inst_12919: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x401; +op3val:0x83ff; valaddr_reg:x2; val_offset:38655*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38655*FLEN/8, x3, x1, x4) + +inst_12920: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x401; +op3val:0x400; valaddr_reg:x2; val_offset:38658*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38658*FLEN/8, x3, x1, x4) + +inst_12921: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x401; +op3val:0x8400; valaddr_reg:x2; val_offset:38661*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38661*FLEN/8, x3, x1, x4) + +inst_12922: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x401; +op3val:0x401; valaddr_reg:x2; val_offset:38664*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38664*FLEN/8, x3, x1, x4) + +inst_12923: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x401; +op3val:0x8455; valaddr_reg:x2; val_offset:38667*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38667*FLEN/8, x3, x1, x4) + +inst_12924: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x401; +op3val:0x7bff; valaddr_reg:x2; val_offset:38670*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38670*FLEN/8, x3, x1, x4) + +inst_12925: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x401; +op3val:0xfbff; valaddr_reg:x2; val_offset:38673*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38673*FLEN/8, x3, x1, x4) + +inst_12926: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x401; +op3val:0x7c00; valaddr_reg:x2; val_offset:38676*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38676*FLEN/8, x3, x1, x4) + +inst_12927: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x401; +op3val:0xfc00; valaddr_reg:x2; val_offset:38679*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38679*FLEN/8, x3, x1, x4) + +inst_12928: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x401; +op3val:0x7e00; valaddr_reg:x2; val_offset:38682*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38682*FLEN/8, x3, x1, x4) + +inst_12929: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x401; +op3val:0xfe00; valaddr_reg:x2; val_offset:38685*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38685*FLEN/8, x3, x1, x4) + +inst_12930: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x401; +op3val:0x7e01; valaddr_reg:x2; val_offset:38688*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38688*FLEN/8, x3, x1, x4) + +inst_12931: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x401; +op3val:0xfe55; valaddr_reg:x2; val_offset:38691*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38691*FLEN/8, x3, x1, x4) + +inst_12932: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x401; +op3val:0x7c01; valaddr_reg:x2; val_offset:38694*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38694*FLEN/8, x3, x1, x4) + +inst_12933: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x401; +op3val:0xfd55; valaddr_reg:x2; val_offset:38697*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38697*FLEN/8, x3, x1, x4) + +inst_12934: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x401; +op3val:0x3c00; valaddr_reg:x2; val_offset:38700*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38700*FLEN/8, x3, x1, x4) + +inst_12935: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x401; +op3val:0xbc00; valaddr_reg:x2; val_offset:38703*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38703*FLEN/8, x3, x1, x4) + +inst_12936: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8455; +op3val:0x0; valaddr_reg:x2; val_offset:38706*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38706*FLEN/8, x3, x1, x4) + +inst_12937: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8455; +op3val:0x8000; valaddr_reg:x2; val_offset:38709*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38709*FLEN/8, x3, x1, x4) + +inst_12938: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8455; +op3val:0x1; valaddr_reg:x2; val_offset:38712*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38712*FLEN/8, x3, x1, x4) + +inst_12939: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8455; +op3val:0x8001; valaddr_reg:x2; val_offset:38715*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38715*FLEN/8, x3, x1, x4) + +inst_12940: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8455; +op3val:0x2; valaddr_reg:x2; val_offset:38718*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38718*FLEN/8, x3, x1, x4) + +inst_12941: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8455; +op3val:0x83fe; valaddr_reg:x2; val_offset:38721*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38721*FLEN/8, x3, x1, x4) + +inst_12942: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8455; +op3val:0x3ff; valaddr_reg:x2; val_offset:38724*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38724*FLEN/8, x3, x1, x4) + +inst_12943: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8455; +op3val:0x83ff; valaddr_reg:x2; val_offset:38727*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38727*FLEN/8, x3, x1, x4) + +inst_12944: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8455; +op3val:0x400; valaddr_reg:x2; val_offset:38730*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38730*FLEN/8, x3, x1, x4) + +inst_12945: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8455; +op3val:0x8400; valaddr_reg:x2; val_offset:38733*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38733*FLEN/8, x3, x1, x4) + +inst_12946: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8455; +op3val:0x401; valaddr_reg:x2; val_offset:38736*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38736*FLEN/8, x3, x1, x4) + +inst_12947: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8455; +op3val:0x8455; valaddr_reg:x2; val_offset:38739*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38739*FLEN/8, x3, x1, x4) + +inst_12948: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8455; +op3val:0x7bff; valaddr_reg:x2; val_offset:38742*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38742*FLEN/8, x3, x1, x4) + +inst_12949: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8455; +op3val:0xfbff; valaddr_reg:x2; val_offset:38745*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38745*FLEN/8, x3, x1, x4) + +inst_12950: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8455; +op3val:0x7c00; valaddr_reg:x2; val_offset:38748*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38748*FLEN/8, x3, x1, x4) + +inst_12951: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8455; +op3val:0xfc00; valaddr_reg:x2; val_offset:38751*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38751*FLEN/8, x3, x1, x4) + +inst_12952: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8455; +op3val:0x7e00; valaddr_reg:x2; val_offset:38754*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38754*FLEN/8, x3, x1, x4) + +inst_12953: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8455; +op3val:0xfe00; valaddr_reg:x2; val_offset:38757*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38757*FLEN/8, x3, x1, x4) + +inst_12954: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8455; +op3val:0x7e01; valaddr_reg:x2; val_offset:38760*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38760*FLEN/8, x3, x1, x4) + +inst_12955: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8455; +op3val:0xfe55; valaddr_reg:x2; val_offset:38763*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38763*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_102) + +inst_12956: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8455; +op3val:0x7c01; valaddr_reg:x2; val_offset:38766*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38766*FLEN/8, x3, x1, x4) + +inst_12957: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8455; +op3val:0xfd55; valaddr_reg:x2; val_offset:38769*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38769*FLEN/8, x3, x1, x4) + +inst_12958: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8455; +op3val:0x3c00; valaddr_reg:x2; val_offset:38772*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38772*FLEN/8, x3, x1, x4) + +inst_12959: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x8455; +op3val:0xbc00; valaddr_reg:x2; val_offset:38775*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38775*FLEN/8, x3, x1, x4) + +inst_12960: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7bff; +op3val:0x0; valaddr_reg:x2; val_offset:38778*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38778*FLEN/8, x3, x1, x4) + +inst_12961: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7bff; +op3val:0x8000; valaddr_reg:x2; val_offset:38781*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38781*FLEN/8, x3, x1, x4) + +inst_12962: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7bff; +op3val:0x1; valaddr_reg:x2; val_offset:38784*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38784*FLEN/8, x3, x1, x4) + +inst_12963: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7bff; +op3val:0x8001; valaddr_reg:x2; val_offset:38787*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38787*FLEN/8, x3, x1, x4) + +inst_12964: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7bff; +op3val:0x2; valaddr_reg:x2; val_offset:38790*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38790*FLEN/8, x3, x1, x4) + +inst_12965: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7bff; +op3val:0x83fe; valaddr_reg:x2; val_offset:38793*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38793*FLEN/8, x3, x1, x4) + +inst_12966: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7bff; +op3val:0x3ff; valaddr_reg:x2; val_offset:38796*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38796*FLEN/8, x3, x1, x4) + +inst_12967: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7bff; +op3val:0x83ff; valaddr_reg:x2; val_offset:38799*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38799*FLEN/8, x3, x1, x4) + +inst_12968: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7bff; +op3val:0x400; valaddr_reg:x2; val_offset:38802*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38802*FLEN/8, x3, x1, x4) + +inst_12969: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7bff; +op3val:0x8400; valaddr_reg:x2; val_offset:38805*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38805*FLEN/8, x3, x1, x4) + +inst_12970: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7bff; +op3val:0x401; valaddr_reg:x2; val_offset:38808*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38808*FLEN/8, x3, x1, x4) + +inst_12971: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7bff; +op3val:0x8455; valaddr_reg:x2; val_offset:38811*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38811*FLEN/8, x3, x1, x4) + +inst_12972: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7bff; +op3val:0x7bff; valaddr_reg:x2; val_offset:38814*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38814*FLEN/8, x3, x1, x4) + +inst_12973: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7bff; +op3val:0xfbff; valaddr_reg:x2; val_offset:38817*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38817*FLEN/8, x3, x1, x4) + +inst_12974: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7bff; +op3val:0x7c00; valaddr_reg:x2; val_offset:38820*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38820*FLEN/8, x3, x1, x4) + +inst_12975: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7bff; +op3val:0xfc00; valaddr_reg:x2; val_offset:38823*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38823*FLEN/8, x3, x1, x4) + +inst_12976: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7bff; +op3val:0x7e00; valaddr_reg:x2; val_offset:38826*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38826*FLEN/8, x3, x1, x4) + +inst_12977: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7bff; +op3val:0xfe00; valaddr_reg:x2; val_offset:38829*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38829*FLEN/8, x3, x1, x4) + +inst_12978: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7bff; +op3val:0x7e01; valaddr_reg:x2; val_offset:38832*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38832*FLEN/8, x3, x1, x4) + +inst_12979: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7bff; +op3val:0xfe55; valaddr_reg:x2; val_offset:38835*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38835*FLEN/8, x3, x1, x4) + +inst_12980: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7bff; +op3val:0x7c01; valaddr_reg:x2; val_offset:38838*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38838*FLEN/8, x3, x1, x4) + +inst_12981: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7bff; +op3val:0xfd55; valaddr_reg:x2; val_offset:38841*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38841*FLEN/8, x3, x1, x4) + +inst_12982: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7bff; +op3val:0x3c00; valaddr_reg:x2; val_offset:38844*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38844*FLEN/8, x3, x1, x4) + +inst_12983: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7bff; +op3val:0xbc00; valaddr_reg:x2; val_offset:38847*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38847*FLEN/8, x3, x1, x4) + +inst_12984: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfbff; +op3val:0x0; valaddr_reg:x2; val_offset:38850*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38850*FLEN/8, x3, x1, x4) + +inst_12985: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfbff; +op3val:0x8000; valaddr_reg:x2; val_offset:38853*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38853*FLEN/8, x3, x1, x4) + +inst_12986: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfbff; +op3val:0x1; valaddr_reg:x2; val_offset:38856*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38856*FLEN/8, x3, x1, x4) + +inst_12987: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfbff; +op3val:0x8001; valaddr_reg:x2; val_offset:38859*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38859*FLEN/8, x3, x1, x4) + +inst_12988: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfbff; +op3val:0x2; valaddr_reg:x2; val_offset:38862*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38862*FLEN/8, x3, x1, x4) + +inst_12989: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfbff; +op3val:0x83fe; valaddr_reg:x2; val_offset:38865*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38865*FLEN/8, x3, x1, x4) + +inst_12990: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfbff; +op3val:0x3ff; valaddr_reg:x2; val_offset:38868*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38868*FLEN/8, x3, x1, x4) + +inst_12991: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfbff; +op3val:0x83ff; valaddr_reg:x2; val_offset:38871*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38871*FLEN/8, x3, x1, x4) + +inst_12992: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfbff; +op3val:0x400; valaddr_reg:x2; val_offset:38874*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38874*FLEN/8, x3, x1, x4) + +inst_12993: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfbff; +op3val:0x8400; valaddr_reg:x2; val_offset:38877*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38877*FLEN/8, x3, x1, x4) + +inst_12994: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfbff; +op3val:0x401; valaddr_reg:x2; val_offset:38880*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38880*FLEN/8, x3, x1, x4) + +inst_12995: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfbff; +op3val:0x8455; valaddr_reg:x2; val_offset:38883*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38883*FLEN/8, x3, x1, x4) + +inst_12996: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfbff; +op3val:0x7bff; valaddr_reg:x2; val_offset:38886*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38886*FLEN/8, x3, x1, x4) + +inst_12997: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfbff; +op3val:0xfbff; valaddr_reg:x2; val_offset:38889*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38889*FLEN/8, x3, x1, x4) + +inst_12998: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfbff; +op3val:0x7c00; valaddr_reg:x2; val_offset:38892*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38892*FLEN/8, x3, x1, x4) + +inst_12999: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfbff; +op3val:0xfc00; valaddr_reg:x2; val_offset:38895*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38895*FLEN/8, x3, x1, x4) + +inst_13000: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfbff; +op3val:0x7e00; valaddr_reg:x2; val_offset:38898*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38898*FLEN/8, x3, x1, x4) + +inst_13001: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfbff; +op3val:0xfe00; valaddr_reg:x2; val_offset:38901*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38901*FLEN/8, x3, x1, x4) + +inst_13002: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfbff; +op3val:0x7e01; valaddr_reg:x2; val_offset:38904*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38904*FLEN/8, x3, x1, x4) + +inst_13003: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfbff; +op3val:0xfe55; valaddr_reg:x2; val_offset:38907*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38907*FLEN/8, x3, x1, x4) + +inst_13004: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfbff; +op3val:0x7c01; valaddr_reg:x2; val_offset:38910*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38910*FLEN/8, x3, x1, x4) + +inst_13005: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfbff; +op3val:0xfd55; valaddr_reg:x2; val_offset:38913*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38913*FLEN/8, x3, x1, x4) + +inst_13006: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfbff; +op3val:0x3c00; valaddr_reg:x2; val_offset:38916*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38916*FLEN/8, x3, x1, x4) + +inst_13007: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfbff; +op3val:0xbc00; valaddr_reg:x2; val_offset:38919*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38919*FLEN/8, x3, x1, x4) + +inst_13008: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7c00; +op3val:0x0; valaddr_reg:x2; val_offset:38922*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38922*FLEN/8, x3, x1, x4) + +inst_13009: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7c00; +op3val:0x8000; valaddr_reg:x2; val_offset:38925*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38925*FLEN/8, x3, x1, x4) + +inst_13010: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7c00; +op3val:0x1; valaddr_reg:x2; val_offset:38928*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38928*FLEN/8, x3, x1, x4) + +inst_13011: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7c00; +op3val:0x8001; valaddr_reg:x2; val_offset:38931*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38931*FLEN/8, x3, x1, x4) + +inst_13012: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7c00; +op3val:0x2; valaddr_reg:x2; val_offset:38934*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38934*FLEN/8, x3, x1, x4) + +inst_13013: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7c00; +op3val:0x83fe; valaddr_reg:x2; val_offset:38937*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38937*FLEN/8, x3, x1, x4) + +inst_13014: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7c00; +op3val:0x3ff; valaddr_reg:x2; val_offset:38940*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38940*FLEN/8, x3, x1, x4) + +inst_13015: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7c00; +op3val:0x83ff; valaddr_reg:x2; val_offset:38943*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38943*FLEN/8, x3, x1, x4) + +inst_13016: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7c00; +op3val:0x400; valaddr_reg:x2; val_offset:38946*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38946*FLEN/8, x3, x1, x4) + +inst_13017: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7c00; +op3val:0x8400; valaddr_reg:x2; val_offset:38949*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38949*FLEN/8, x3, x1, x4) + +inst_13018: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7c00; +op3val:0x401; valaddr_reg:x2; val_offset:38952*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38952*FLEN/8, x3, x1, x4) + +inst_13019: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7c00; +op3val:0x8455; valaddr_reg:x2; val_offset:38955*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38955*FLEN/8, x3, x1, x4) + +inst_13020: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7c00; +op3val:0x7bff; valaddr_reg:x2; val_offset:38958*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38958*FLEN/8, x3, x1, x4) + +inst_13021: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7c00; +op3val:0xfbff; valaddr_reg:x2; val_offset:38961*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38961*FLEN/8, x3, x1, x4) + +inst_13022: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7c00; +op3val:0x7c00; valaddr_reg:x2; val_offset:38964*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38964*FLEN/8, x3, x1, x4) + +inst_13023: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7c00; +op3val:0xfc00; valaddr_reg:x2; val_offset:38967*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38967*FLEN/8, x3, x1, x4) + +inst_13024: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7c00; +op3val:0x7e00; valaddr_reg:x2; val_offset:38970*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38970*FLEN/8, x3, x1, x4) + +inst_13025: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7c00; +op3val:0xfe00; valaddr_reg:x2; val_offset:38973*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38973*FLEN/8, x3, x1, x4) + +inst_13026: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7c00; +op3val:0x7e01; valaddr_reg:x2; val_offset:38976*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38976*FLEN/8, x3, x1, x4) + +inst_13027: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7c00; +op3val:0xfe55; valaddr_reg:x2; val_offset:38979*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38979*FLEN/8, x3, x1, x4) + +inst_13028: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7c00; +op3val:0x7c01; valaddr_reg:x2; val_offset:38982*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38982*FLEN/8, x3, x1, x4) + +inst_13029: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7c00; +op3val:0xfd55; valaddr_reg:x2; val_offset:38985*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38985*FLEN/8, x3, x1, x4) + +inst_13030: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7c00; +op3val:0x3c00; valaddr_reg:x2; val_offset:38988*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38988*FLEN/8, x3, x1, x4) + +inst_13031: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7c00; +op3val:0xbc00; valaddr_reg:x2; val_offset:38991*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38991*FLEN/8, x3, x1, x4) + +inst_13032: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfc00; +op3val:0x0; valaddr_reg:x2; val_offset:38994*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38994*FLEN/8, x3, x1, x4) + +inst_13033: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfc00; +op3val:0x8000; valaddr_reg:x2; val_offset:38997*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 38997*FLEN/8, x3, x1, x4) + +inst_13034: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfc00; +op3val:0x1; valaddr_reg:x2; val_offset:39000*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39000*FLEN/8, x3, x1, x4) + +inst_13035: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfc00; +op3val:0x8001; valaddr_reg:x2; val_offset:39003*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39003*FLEN/8, x3, x1, x4) + +inst_13036: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfc00; +op3val:0x2; valaddr_reg:x2; val_offset:39006*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39006*FLEN/8, x3, x1, x4) + +inst_13037: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfc00; +op3val:0x83fe; valaddr_reg:x2; val_offset:39009*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39009*FLEN/8, x3, x1, x4) + +inst_13038: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfc00; +op3val:0x3ff; valaddr_reg:x2; val_offset:39012*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39012*FLEN/8, x3, x1, x4) + +inst_13039: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfc00; +op3val:0x83ff; valaddr_reg:x2; val_offset:39015*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39015*FLEN/8, x3, x1, x4) + +inst_13040: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfc00; +op3val:0x400; valaddr_reg:x2; val_offset:39018*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39018*FLEN/8, x3, x1, x4) + +inst_13041: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfc00; +op3val:0x8400; valaddr_reg:x2; val_offset:39021*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39021*FLEN/8, x3, x1, x4) + +inst_13042: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfc00; +op3val:0x401; valaddr_reg:x2; val_offset:39024*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39024*FLEN/8, x3, x1, x4) + +inst_13043: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfc00; +op3val:0x8455; valaddr_reg:x2; val_offset:39027*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39027*FLEN/8, x3, x1, x4) + +inst_13044: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfc00; +op3val:0x7bff; valaddr_reg:x2; val_offset:39030*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39030*FLEN/8, x3, x1, x4) + +inst_13045: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfc00; +op3val:0xfbff; valaddr_reg:x2; val_offset:39033*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39033*FLEN/8, x3, x1, x4) + +inst_13046: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfc00; +op3val:0x7c00; valaddr_reg:x2; val_offset:39036*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39036*FLEN/8, x3, x1, x4) + +inst_13047: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfc00; +op3val:0xfc00; valaddr_reg:x2; val_offset:39039*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39039*FLEN/8, x3, x1, x4) + +inst_13048: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfc00; +op3val:0x7e00; valaddr_reg:x2; val_offset:39042*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39042*FLEN/8, x3, x1, x4) + +inst_13049: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfc00; +op3val:0xfe00; valaddr_reg:x2; val_offset:39045*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39045*FLEN/8, x3, x1, x4) + +inst_13050: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfc00; +op3val:0x7e01; valaddr_reg:x2; val_offset:39048*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39048*FLEN/8, x3, x1, x4) + +inst_13051: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfc00; +op3val:0xfe55; valaddr_reg:x2; val_offset:39051*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39051*FLEN/8, x3, x1, x4) + +inst_13052: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfc00; +op3val:0x7c01; valaddr_reg:x2; val_offset:39054*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39054*FLEN/8, x3, x1, x4) + +inst_13053: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfc00; +op3val:0xfd55; valaddr_reg:x2; val_offset:39057*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39057*FLEN/8, x3, x1, x4) + +inst_13054: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfc00; +op3val:0x3c00; valaddr_reg:x2; val_offset:39060*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39060*FLEN/8, x3, x1, x4) + +inst_13055: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfc00; +op3val:0xbc00; valaddr_reg:x2; val_offset:39063*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39063*FLEN/8, x3, x1, x4) + +inst_13056: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7e00; +op3val:0x0; valaddr_reg:x2; val_offset:39066*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39066*FLEN/8, x3, x1, x4) + +inst_13057: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7e00; +op3val:0x8000; valaddr_reg:x2; val_offset:39069*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39069*FLEN/8, x3, x1, x4) + +inst_13058: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7e00; +op3val:0x1; valaddr_reg:x2; val_offset:39072*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39072*FLEN/8, x3, x1, x4) + +inst_13059: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7e00; +op3val:0x8001; valaddr_reg:x2; val_offset:39075*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39075*FLEN/8, x3, x1, x4) + +inst_13060: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7e00; +op3val:0x2; valaddr_reg:x2; val_offset:39078*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39078*FLEN/8, x3, x1, x4) + +inst_13061: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7e00; +op3val:0x83fe; valaddr_reg:x2; val_offset:39081*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39081*FLEN/8, x3, x1, x4) + +inst_13062: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7e00; +op3val:0x3ff; valaddr_reg:x2; val_offset:39084*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39084*FLEN/8, x3, x1, x4) + +inst_13063: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7e00; +op3val:0x83ff; valaddr_reg:x2; val_offset:39087*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39087*FLEN/8, x3, x1, x4) + +inst_13064: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7e00; +op3val:0x400; valaddr_reg:x2; val_offset:39090*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39090*FLEN/8, x3, x1, x4) + +inst_13065: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7e00; +op3val:0x8400; valaddr_reg:x2; val_offset:39093*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39093*FLEN/8, x3, x1, x4) + +inst_13066: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7e00; +op3val:0x401; valaddr_reg:x2; val_offset:39096*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39096*FLEN/8, x3, x1, x4) + +inst_13067: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7e00; +op3val:0x8455; valaddr_reg:x2; val_offset:39099*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39099*FLEN/8, x3, x1, x4) + +inst_13068: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7e00; +op3val:0x7bff; valaddr_reg:x2; val_offset:39102*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39102*FLEN/8, x3, x1, x4) + +inst_13069: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7e00; +op3val:0xfbff; valaddr_reg:x2; val_offset:39105*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39105*FLEN/8, x3, x1, x4) + +inst_13070: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7e00; +op3val:0x7c00; valaddr_reg:x2; val_offset:39108*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39108*FLEN/8, x3, x1, x4) + +inst_13071: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7e00; +op3val:0xfc00; valaddr_reg:x2; val_offset:39111*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39111*FLEN/8, x3, x1, x4) + +inst_13072: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7e00; +op3val:0x7e00; valaddr_reg:x2; val_offset:39114*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39114*FLEN/8, x3, x1, x4) + +inst_13073: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7e00; +op3val:0xfe00; valaddr_reg:x2; val_offset:39117*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39117*FLEN/8, x3, x1, x4) + +inst_13074: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7e00; +op3val:0x7e01; valaddr_reg:x2; val_offset:39120*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39120*FLEN/8, x3, x1, x4) + +inst_13075: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7e00; +op3val:0xfe55; valaddr_reg:x2; val_offset:39123*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39123*FLEN/8, x3, x1, x4) + +inst_13076: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7e00; +op3val:0x7c01; valaddr_reg:x2; val_offset:39126*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39126*FLEN/8, x3, x1, x4) + +inst_13077: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7e00; +op3val:0xfd55; valaddr_reg:x2; val_offset:39129*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39129*FLEN/8, x3, x1, x4) + +inst_13078: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7e00; +op3val:0x3c00; valaddr_reg:x2; val_offset:39132*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39132*FLEN/8, x3, x1, x4) + +inst_13079: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7e00; +op3val:0xbc00; valaddr_reg:x2; val_offset:39135*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39135*FLEN/8, x3, x1, x4) + +inst_13080: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfe00; +op3val:0x0; valaddr_reg:x2; val_offset:39138*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39138*FLEN/8, x3, x1, x4) + +inst_13081: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfe00; +op3val:0x8000; valaddr_reg:x2; val_offset:39141*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39141*FLEN/8, x3, x1, x4) + +inst_13082: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfe00; +op3val:0x1; valaddr_reg:x2; val_offset:39144*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39144*FLEN/8, x3, x1, x4) + +inst_13083: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfe00; +op3val:0x8001; valaddr_reg:x2; val_offset:39147*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39147*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_103) + +inst_13084: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfe00; +op3val:0x2; valaddr_reg:x2; val_offset:39150*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39150*FLEN/8, x3, x1, x4) + +inst_13085: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfe00; +op3val:0x83fe; valaddr_reg:x2; val_offset:39153*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39153*FLEN/8, x3, x1, x4) + +inst_13086: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfe00; +op3val:0x3ff; valaddr_reg:x2; val_offset:39156*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39156*FLEN/8, x3, x1, x4) + +inst_13087: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfe00; +op3val:0x83ff; valaddr_reg:x2; val_offset:39159*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39159*FLEN/8, x3, x1, x4) + +inst_13088: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfe00; +op3val:0x400; valaddr_reg:x2; val_offset:39162*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39162*FLEN/8, x3, x1, x4) + +inst_13089: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfe00; +op3val:0x8400; valaddr_reg:x2; val_offset:39165*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39165*FLEN/8, x3, x1, x4) + +inst_13090: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfe00; +op3val:0x401; valaddr_reg:x2; val_offset:39168*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39168*FLEN/8, x3, x1, x4) + +inst_13091: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfe00; +op3val:0x8455; valaddr_reg:x2; val_offset:39171*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39171*FLEN/8, x3, x1, x4) + +inst_13092: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfe00; +op3val:0x7bff; valaddr_reg:x2; val_offset:39174*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39174*FLEN/8, x3, x1, x4) + +inst_13093: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfe00; +op3val:0xfbff; valaddr_reg:x2; val_offset:39177*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39177*FLEN/8, x3, x1, x4) + +inst_13094: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfe00; +op3val:0x7c00; valaddr_reg:x2; val_offset:39180*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39180*FLEN/8, x3, x1, x4) + +inst_13095: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfe00; +op3val:0xfc00; valaddr_reg:x2; val_offset:39183*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39183*FLEN/8, x3, x1, x4) + +inst_13096: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfe00; +op3val:0x7e00; valaddr_reg:x2; val_offset:39186*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39186*FLEN/8, x3, x1, x4) + +inst_13097: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfe00; +op3val:0xfe00; valaddr_reg:x2; val_offset:39189*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39189*FLEN/8, x3, x1, x4) + +inst_13098: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfe00; +op3val:0x7e01; valaddr_reg:x2; val_offset:39192*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39192*FLEN/8, x3, x1, x4) + +inst_13099: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfe00; +op3val:0xfe55; valaddr_reg:x2; val_offset:39195*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39195*FLEN/8, x3, x1, x4) + +inst_13100: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfe00; +op3val:0x7c01; valaddr_reg:x2; val_offset:39198*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39198*FLEN/8, x3, x1, x4) + +inst_13101: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfe00; +op3val:0xfd55; valaddr_reg:x2; val_offset:39201*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39201*FLEN/8, x3, x1, x4) + +inst_13102: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfe00; +op3val:0x3c00; valaddr_reg:x2; val_offset:39204*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39204*FLEN/8, x3, x1, x4) + +inst_13103: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfe00; +op3val:0xbc00; valaddr_reg:x2; val_offset:39207*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39207*FLEN/8, x3, x1, x4) + +inst_13104: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7e01; +op3val:0x0; valaddr_reg:x2; val_offset:39210*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39210*FLEN/8, x3, x1, x4) + +inst_13105: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7e01; +op3val:0x8000; valaddr_reg:x2; val_offset:39213*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39213*FLEN/8, x3, x1, x4) + +inst_13106: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7e01; +op3val:0x1; valaddr_reg:x2; val_offset:39216*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39216*FLEN/8, x3, x1, x4) + +inst_13107: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7e01; +op3val:0x8001; valaddr_reg:x2; val_offset:39219*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39219*FLEN/8, x3, x1, x4) + +inst_13108: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7e01; +op3val:0x2; valaddr_reg:x2; val_offset:39222*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39222*FLEN/8, x3, x1, x4) + +inst_13109: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7e01; +op3val:0x83fe; valaddr_reg:x2; val_offset:39225*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39225*FLEN/8, x3, x1, x4) + +inst_13110: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7e01; +op3val:0x3ff; valaddr_reg:x2; val_offset:39228*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39228*FLEN/8, x3, x1, x4) + +inst_13111: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7e01; +op3val:0x83ff; valaddr_reg:x2; val_offset:39231*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39231*FLEN/8, x3, x1, x4) + +inst_13112: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7e01; +op3val:0x400; valaddr_reg:x2; val_offset:39234*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39234*FLEN/8, x3, x1, x4) + +inst_13113: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7e01; +op3val:0x8400; valaddr_reg:x2; val_offset:39237*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39237*FLEN/8, x3, x1, x4) + +inst_13114: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7e01; +op3val:0x401; valaddr_reg:x2; val_offset:39240*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39240*FLEN/8, x3, x1, x4) + +inst_13115: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7e01; +op3val:0x8455; valaddr_reg:x2; val_offset:39243*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39243*FLEN/8, x3, x1, x4) + +inst_13116: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7e01; +op3val:0x7bff; valaddr_reg:x2; val_offset:39246*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39246*FLEN/8, x3, x1, x4) + +inst_13117: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7e01; +op3val:0xfbff; valaddr_reg:x2; val_offset:39249*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39249*FLEN/8, x3, x1, x4) + +inst_13118: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7e01; +op3val:0x7c00; valaddr_reg:x2; val_offset:39252*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39252*FLEN/8, x3, x1, x4) + +inst_13119: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7e01; +op3val:0xfc00; valaddr_reg:x2; val_offset:39255*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39255*FLEN/8, x3, x1, x4) + +inst_13120: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7e01; +op3val:0x7e00; valaddr_reg:x2; val_offset:39258*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39258*FLEN/8, x3, x1, x4) + +inst_13121: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7e01; +op3val:0xfe00; valaddr_reg:x2; val_offset:39261*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39261*FLEN/8, x3, x1, x4) + +inst_13122: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7e01; +op3val:0x7e01; valaddr_reg:x2; val_offset:39264*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39264*FLEN/8, x3, x1, x4) + +inst_13123: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7e01; +op3val:0xfe55; valaddr_reg:x2; val_offset:39267*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39267*FLEN/8, x3, x1, x4) + +inst_13124: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7e01; +op3val:0x7c01; valaddr_reg:x2; val_offset:39270*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39270*FLEN/8, x3, x1, x4) + +inst_13125: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7e01; +op3val:0xfd55; valaddr_reg:x2; val_offset:39273*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39273*FLEN/8, x3, x1, x4) + +inst_13126: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7e01; +op3val:0x3c00; valaddr_reg:x2; val_offset:39276*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39276*FLEN/8, x3, x1, x4) + +inst_13127: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7e01; +op3val:0xbc00; valaddr_reg:x2; val_offset:39279*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39279*FLEN/8, x3, x1, x4) + +inst_13128: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfe55; +op3val:0x0; valaddr_reg:x2; val_offset:39282*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39282*FLEN/8, x3, x1, x4) + +inst_13129: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfe55; +op3val:0x8000; valaddr_reg:x2; val_offset:39285*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39285*FLEN/8, x3, x1, x4) + +inst_13130: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfe55; +op3val:0x1; valaddr_reg:x2; val_offset:39288*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39288*FLEN/8, x3, x1, x4) + +inst_13131: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfe55; +op3val:0x8001; valaddr_reg:x2; val_offset:39291*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39291*FLEN/8, x3, x1, x4) + +inst_13132: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfe55; +op3val:0x2; valaddr_reg:x2; val_offset:39294*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39294*FLEN/8, x3, x1, x4) + +inst_13133: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfe55; +op3val:0x83fe; valaddr_reg:x2; val_offset:39297*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39297*FLEN/8, x3, x1, x4) + +inst_13134: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfe55; +op3val:0x3ff; valaddr_reg:x2; val_offset:39300*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39300*FLEN/8, x3, x1, x4) + +inst_13135: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfe55; +op3val:0x83ff; valaddr_reg:x2; val_offset:39303*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39303*FLEN/8, x3, x1, x4) + +inst_13136: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfe55; +op3val:0x400; valaddr_reg:x2; val_offset:39306*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39306*FLEN/8, x3, x1, x4) + +inst_13137: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfe55; +op3val:0x8400; valaddr_reg:x2; val_offset:39309*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39309*FLEN/8, x3, x1, x4) + +inst_13138: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfe55; +op3val:0x401; valaddr_reg:x2; val_offset:39312*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39312*FLEN/8, x3, x1, x4) + +inst_13139: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfe55; +op3val:0x8455; valaddr_reg:x2; val_offset:39315*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39315*FLEN/8, x3, x1, x4) + +inst_13140: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfe55; +op3val:0x7bff; valaddr_reg:x2; val_offset:39318*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39318*FLEN/8, x3, x1, x4) + +inst_13141: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfe55; +op3val:0xfbff; valaddr_reg:x2; val_offset:39321*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39321*FLEN/8, x3, x1, x4) + +inst_13142: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfe55; +op3val:0x7c00; valaddr_reg:x2; val_offset:39324*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39324*FLEN/8, x3, x1, x4) + +inst_13143: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfe55; +op3val:0xfc00; valaddr_reg:x2; val_offset:39327*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39327*FLEN/8, x3, x1, x4) + +inst_13144: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfe55; +op3val:0x7e00; valaddr_reg:x2; val_offset:39330*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39330*FLEN/8, x3, x1, x4) + +inst_13145: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfe55; +op3val:0xfe00; valaddr_reg:x2; val_offset:39333*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39333*FLEN/8, x3, x1, x4) + +inst_13146: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfe55; +op3val:0x7e01; valaddr_reg:x2; val_offset:39336*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39336*FLEN/8, x3, x1, x4) + +inst_13147: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfe55; +op3val:0xfe55; valaddr_reg:x2; val_offset:39339*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39339*FLEN/8, x3, x1, x4) + +inst_13148: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfe55; +op3val:0x7c01; valaddr_reg:x2; val_offset:39342*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39342*FLEN/8, x3, x1, x4) + +inst_13149: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfe55; +op3val:0xfd55; valaddr_reg:x2; val_offset:39345*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39345*FLEN/8, x3, x1, x4) + +inst_13150: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfe55; +op3val:0x3c00; valaddr_reg:x2; val_offset:39348*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39348*FLEN/8, x3, x1, x4) + +inst_13151: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfe55; +op3val:0xbc00; valaddr_reg:x2; val_offset:39351*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39351*FLEN/8, x3, x1, x4) + +inst_13152: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7c01; +op3val:0x0; valaddr_reg:x2; val_offset:39354*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39354*FLEN/8, x3, x1, x4) + +inst_13153: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7c01; +op3val:0x8000; valaddr_reg:x2; val_offset:39357*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39357*FLEN/8, x3, x1, x4) + +inst_13154: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7c01; +op3val:0x1; valaddr_reg:x2; val_offset:39360*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39360*FLEN/8, x3, x1, x4) + +inst_13155: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7c01; +op3val:0x8001; valaddr_reg:x2; val_offset:39363*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39363*FLEN/8, x3, x1, x4) + +inst_13156: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7c01; +op3val:0x2; valaddr_reg:x2; val_offset:39366*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39366*FLEN/8, x3, x1, x4) + +inst_13157: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7c01; +op3val:0x83fe; valaddr_reg:x2; val_offset:39369*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39369*FLEN/8, x3, x1, x4) + +inst_13158: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7c01; +op3val:0x3ff; valaddr_reg:x2; val_offset:39372*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39372*FLEN/8, x3, x1, x4) + +inst_13159: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7c01; +op3val:0x83ff; valaddr_reg:x2; val_offset:39375*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39375*FLEN/8, x3, x1, x4) + +inst_13160: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7c01; +op3val:0x400; valaddr_reg:x2; val_offset:39378*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39378*FLEN/8, x3, x1, x4) + +inst_13161: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7c01; +op3val:0x8400; valaddr_reg:x2; val_offset:39381*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39381*FLEN/8, x3, x1, x4) + +inst_13162: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7c01; +op3val:0x401; valaddr_reg:x2; val_offset:39384*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39384*FLEN/8, x3, x1, x4) + +inst_13163: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7c01; +op3val:0x8455; valaddr_reg:x2; val_offset:39387*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39387*FLEN/8, x3, x1, x4) + +inst_13164: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7c01; +op3val:0x7bff; valaddr_reg:x2; val_offset:39390*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39390*FLEN/8, x3, x1, x4) + +inst_13165: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7c01; +op3val:0xfbff; valaddr_reg:x2; val_offset:39393*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39393*FLEN/8, x3, x1, x4) + +inst_13166: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7c01; +op3val:0x7c00; valaddr_reg:x2; val_offset:39396*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39396*FLEN/8, x3, x1, x4) + +inst_13167: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7c01; +op3val:0xfc00; valaddr_reg:x2; val_offset:39399*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39399*FLEN/8, x3, x1, x4) + +inst_13168: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7c01; +op3val:0x7e00; valaddr_reg:x2; val_offset:39402*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39402*FLEN/8, x3, x1, x4) + +inst_13169: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7c01; +op3val:0xfe00; valaddr_reg:x2; val_offset:39405*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39405*FLEN/8, x3, x1, x4) + +inst_13170: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7c01; +op3val:0x7e01; valaddr_reg:x2; val_offset:39408*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39408*FLEN/8, x3, x1, x4) + +inst_13171: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7c01; +op3val:0xfe55; valaddr_reg:x2; val_offset:39411*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39411*FLEN/8, x3, x1, x4) + +inst_13172: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7c01; +op3val:0x7c01; valaddr_reg:x2; val_offset:39414*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39414*FLEN/8, x3, x1, x4) + +inst_13173: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7c01; +op3val:0xfd55; valaddr_reg:x2; val_offset:39417*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39417*FLEN/8, x3, x1, x4) + +inst_13174: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7c01; +op3val:0x3c00; valaddr_reg:x2; val_offset:39420*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39420*FLEN/8, x3, x1, x4) + +inst_13175: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x7c01; +op3val:0xbc00; valaddr_reg:x2; val_offset:39423*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39423*FLEN/8, x3, x1, x4) + +inst_13176: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfd55; +op3val:0x0; valaddr_reg:x2; val_offset:39426*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39426*FLEN/8, x3, x1, x4) + +inst_13177: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfd55; +op3val:0x8000; valaddr_reg:x2; val_offset:39429*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39429*FLEN/8, x3, x1, x4) + +inst_13178: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfd55; +op3val:0x1; valaddr_reg:x2; val_offset:39432*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39432*FLEN/8, x3, x1, x4) + +inst_13179: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfd55; +op3val:0x8001; valaddr_reg:x2; val_offset:39435*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39435*FLEN/8, x3, x1, x4) + +inst_13180: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfd55; +op3val:0x2; valaddr_reg:x2; val_offset:39438*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39438*FLEN/8, x3, x1, x4) + +inst_13181: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfd55; +op3val:0x83fe; valaddr_reg:x2; val_offset:39441*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39441*FLEN/8, x3, x1, x4) + +inst_13182: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfd55; +op3val:0x3ff; valaddr_reg:x2; val_offset:39444*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39444*FLEN/8, x3, x1, x4) + +inst_13183: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfd55; +op3val:0x83ff; valaddr_reg:x2; val_offset:39447*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39447*FLEN/8, x3, x1, x4) + +inst_13184: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfd55; +op3val:0x400; valaddr_reg:x2; val_offset:39450*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39450*FLEN/8, x3, x1, x4) + +inst_13185: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfd55; +op3val:0x8400; valaddr_reg:x2; val_offset:39453*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39453*FLEN/8, x3, x1, x4) + +inst_13186: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfd55; +op3val:0x401; valaddr_reg:x2; val_offset:39456*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39456*FLEN/8, x3, x1, x4) + +inst_13187: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfd55; +op3val:0x8455; valaddr_reg:x2; val_offset:39459*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39459*FLEN/8, x3, x1, x4) + +inst_13188: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfd55; +op3val:0x7bff; valaddr_reg:x2; val_offset:39462*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39462*FLEN/8, x3, x1, x4) + +inst_13189: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfd55; +op3val:0xfbff; valaddr_reg:x2; val_offset:39465*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39465*FLEN/8, x3, x1, x4) + +inst_13190: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfd55; +op3val:0x7c00; valaddr_reg:x2; val_offset:39468*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39468*FLEN/8, x3, x1, x4) + +inst_13191: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfd55; +op3val:0xfc00; valaddr_reg:x2; val_offset:39471*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39471*FLEN/8, x3, x1, x4) + +inst_13192: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfd55; +op3val:0x7e00; valaddr_reg:x2; val_offset:39474*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39474*FLEN/8, x3, x1, x4) + +inst_13193: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfd55; +op3val:0xfe00; valaddr_reg:x2; val_offset:39477*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39477*FLEN/8, x3, x1, x4) + +inst_13194: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfd55; +op3val:0x7e01; valaddr_reg:x2; val_offset:39480*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39480*FLEN/8, x3, x1, x4) + +inst_13195: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfd55; +op3val:0xfe55; valaddr_reg:x2; val_offset:39483*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39483*FLEN/8, x3, x1, x4) + +inst_13196: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfd55; +op3val:0x7c01; valaddr_reg:x2; val_offset:39486*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39486*FLEN/8, x3, x1, x4) + +inst_13197: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfd55; +op3val:0xfd55; valaddr_reg:x2; val_offset:39489*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39489*FLEN/8, x3, x1, x4) + +inst_13198: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfd55; +op3val:0x3c00; valaddr_reg:x2; val_offset:39492*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39492*FLEN/8, x3, x1, x4) + +inst_13199: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xfd55; +op3val:0xbc00; valaddr_reg:x2; val_offset:39495*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39495*FLEN/8, x3, x1, x4) + +inst_13200: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x3c00; +op3val:0x0; valaddr_reg:x2; val_offset:39498*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39498*FLEN/8, x3, x1, x4) + +inst_13201: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x3c00; +op3val:0x8000; valaddr_reg:x2; val_offset:39501*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39501*FLEN/8, x3, x1, x4) + +inst_13202: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x3c00; +op3val:0x1; valaddr_reg:x2; val_offset:39504*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39504*FLEN/8, x3, x1, x4) + +inst_13203: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x3c00; +op3val:0x8001; valaddr_reg:x2; val_offset:39507*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39507*FLEN/8, x3, x1, x4) + +inst_13204: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x3c00; +op3val:0x2; valaddr_reg:x2; val_offset:39510*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39510*FLEN/8, x3, x1, x4) + +inst_13205: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x3c00; +op3val:0x83fe; valaddr_reg:x2; val_offset:39513*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39513*FLEN/8, x3, x1, x4) + +inst_13206: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x3c00; +op3val:0x3ff; valaddr_reg:x2; val_offset:39516*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39516*FLEN/8, x3, x1, x4) + +inst_13207: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x3c00; +op3val:0x83ff; valaddr_reg:x2; val_offset:39519*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39519*FLEN/8, x3, x1, x4) + +inst_13208: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x3c00; +op3val:0x400; valaddr_reg:x2; val_offset:39522*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39522*FLEN/8, x3, x1, x4) + +inst_13209: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x3c00; +op3val:0x8400; valaddr_reg:x2; val_offset:39525*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39525*FLEN/8, x3, x1, x4) + +inst_13210: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x3c00; +op3val:0x401; valaddr_reg:x2; val_offset:39528*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39528*FLEN/8, x3, x1, x4) + +inst_13211: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x3c00; +op3val:0x8455; valaddr_reg:x2; val_offset:39531*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39531*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_104) + +inst_13212: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x3c00; +op3val:0x7bff; valaddr_reg:x2; val_offset:39534*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39534*FLEN/8, x3, x1, x4) + +inst_13213: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x3c00; +op3val:0xfbff; valaddr_reg:x2; val_offset:39537*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39537*FLEN/8, x3, x1, x4) + +inst_13214: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x3c00; +op3val:0x7c00; valaddr_reg:x2; val_offset:39540*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39540*FLEN/8, x3, x1, x4) + +inst_13215: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x3c00; +op3val:0xfc00; valaddr_reg:x2; val_offset:39543*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39543*FLEN/8, x3, x1, x4) + +inst_13216: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x3c00; +op3val:0x7e00; valaddr_reg:x2; val_offset:39546*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39546*FLEN/8, x3, x1, x4) + +inst_13217: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x3c00; +op3val:0xfe00; valaddr_reg:x2; val_offset:39549*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39549*FLEN/8, x3, x1, x4) + +inst_13218: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x3c00; +op3val:0x7e01; valaddr_reg:x2; val_offset:39552*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39552*FLEN/8, x3, x1, x4) + +inst_13219: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x3c00; +op3val:0xfe55; valaddr_reg:x2; val_offset:39555*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39555*FLEN/8, x3, x1, x4) + +inst_13220: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x3c00; +op3val:0x7c01; valaddr_reg:x2; val_offset:39558*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39558*FLEN/8, x3, x1, x4) + +inst_13221: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x3c00; +op3val:0xfd55; valaddr_reg:x2; val_offset:39561*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39561*FLEN/8, x3, x1, x4) + +inst_13222: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x3c00; +op3val:0x3c00; valaddr_reg:x2; val_offset:39564*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39564*FLEN/8, x3, x1, x4) + +inst_13223: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0x3c00; +op3val:0xbc00; valaddr_reg:x2; val_offset:39567*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39567*FLEN/8, x3, x1, x4) + +inst_13224: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xbc00; +op3val:0x0; valaddr_reg:x2; val_offset:39570*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39570*FLEN/8, x3, x1, x4) + +inst_13225: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xbc00; +op3val:0x8000; valaddr_reg:x2; val_offset:39573*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39573*FLEN/8, x3, x1, x4) + +inst_13226: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xbc00; +op3val:0x1; valaddr_reg:x2; val_offset:39576*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39576*FLEN/8, x3, x1, x4) + +inst_13227: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xbc00; +op3val:0x8001; valaddr_reg:x2; val_offset:39579*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39579*FLEN/8, x3, x1, x4) + +inst_13228: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xbc00; +op3val:0x2; valaddr_reg:x2; val_offset:39582*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39582*FLEN/8, x3, x1, x4) + +inst_13229: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xbc00; +op3val:0x83fe; valaddr_reg:x2; val_offset:39585*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39585*FLEN/8, x3, x1, x4) + +inst_13230: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xbc00; +op3val:0x3ff; valaddr_reg:x2; val_offset:39588*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39588*FLEN/8, x3, x1, x4) + +inst_13231: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xbc00; +op3val:0x83ff; valaddr_reg:x2; val_offset:39591*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39591*FLEN/8, x3, x1, x4) + +inst_13232: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xbc00; +op3val:0x400; valaddr_reg:x2; val_offset:39594*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39594*FLEN/8, x3, x1, x4) + +inst_13233: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xbc00; +op3val:0x8400; valaddr_reg:x2; val_offset:39597*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39597*FLEN/8, x3, x1, x4) + +inst_13234: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xbc00; +op3val:0x401; valaddr_reg:x2; val_offset:39600*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39600*FLEN/8, x3, x1, x4) + +inst_13235: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xbc00; +op3val:0x8455; valaddr_reg:x2; val_offset:39603*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39603*FLEN/8, x3, x1, x4) + +inst_13236: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xbc00; +op3val:0x7bff; valaddr_reg:x2; val_offset:39606*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39606*FLEN/8, x3, x1, x4) + +inst_13237: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xbc00; +op3val:0xfbff; valaddr_reg:x2; val_offset:39609*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39609*FLEN/8, x3, x1, x4) + +inst_13238: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xbc00; +op3val:0x7c00; valaddr_reg:x2; val_offset:39612*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39612*FLEN/8, x3, x1, x4) + +inst_13239: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xbc00; +op3val:0xfc00; valaddr_reg:x2; val_offset:39615*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39615*FLEN/8, x3, x1, x4) + +inst_13240: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xbc00; +op3val:0x7e00; valaddr_reg:x2; val_offset:39618*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39618*FLEN/8, x3, x1, x4) + +inst_13241: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xbc00; +op3val:0xfe00; valaddr_reg:x2; val_offset:39621*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39621*FLEN/8, x3, x1, x4) + +inst_13242: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xbc00; +op3val:0x7e01; valaddr_reg:x2; val_offset:39624*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39624*FLEN/8, x3, x1, x4) + +inst_13243: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xbc00; +op3val:0xfe55; valaddr_reg:x2; val_offset:39627*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39627*FLEN/8, x3, x1, x4) + +inst_13244: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xbc00; +op3val:0x7c01; valaddr_reg:x2; val_offset:39630*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39630*FLEN/8, x3, x1, x4) + +inst_13245: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xbc00; +op3val:0xfd55; valaddr_reg:x2; val_offset:39633*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39633*FLEN/8, x3, x1, x4) + +inst_13246: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xbc00; +op3val:0x3c00; valaddr_reg:x2; val_offset:39636*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39636*FLEN/8, x3, x1, x4) + +inst_13247: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c00; op2val:0xbc00; +op3val:0xbc00; valaddr_reg:x2; val_offset:39639*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39639*FLEN/8, x3, x1, x4) + +inst_13248: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x0; +op3val:0x0; valaddr_reg:x2; val_offset:39642*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39642*FLEN/8, x3, x1, x4) + +inst_13249: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x0; +op3val:0x8000; valaddr_reg:x2; val_offset:39645*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39645*FLEN/8, x3, x1, x4) + +inst_13250: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x0; +op3val:0x1; valaddr_reg:x2; val_offset:39648*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39648*FLEN/8, x3, x1, x4) + +inst_13251: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x0; +op3val:0x8001; valaddr_reg:x2; val_offset:39651*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39651*FLEN/8, x3, x1, x4) + +inst_13252: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x0; +op3val:0x2; valaddr_reg:x2; val_offset:39654*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39654*FLEN/8, x3, x1, x4) + +inst_13253: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x0; +op3val:0x83fe; valaddr_reg:x2; val_offset:39657*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39657*FLEN/8, x3, x1, x4) + +inst_13254: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x0; +op3val:0x3ff; valaddr_reg:x2; val_offset:39660*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39660*FLEN/8, x3, x1, x4) + +inst_13255: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x0; +op3val:0x83ff; valaddr_reg:x2; val_offset:39663*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39663*FLEN/8, x3, x1, x4) + +inst_13256: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x0; +op3val:0x400; valaddr_reg:x2; val_offset:39666*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39666*FLEN/8, x3, x1, x4) + +inst_13257: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x0; +op3val:0x8400; valaddr_reg:x2; val_offset:39669*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39669*FLEN/8, x3, x1, x4) + +inst_13258: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x0; +op3val:0x401; valaddr_reg:x2; val_offset:39672*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39672*FLEN/8, x3, x1, x4) + +inst_13259: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x0; +op3val:0x8455; valaddr_reg:x2; val_offset:39675*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39675*FLEN/8, x3, x1, x4) + +inst_13260: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x0; +op3val:0x7bff; valaddr_reg:x2; val_offset:39678*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39678*FLEN/8, x3, x1, x4) + +inst_13261: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x0; +op3val:0xfbff; valaddr_reg:x2; val_offset:39681*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39681*FLEN/8, x3, x1, x4) + +inst_13262: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x0; +op3val:0x7c00; valaddr_reg:x2; val_offset:39684*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39684*FLEN/8, x3, x1, x4) + +inst_13263: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x0; +op3val:0xfc00; valaddr_reg:x2; val_offset:39687*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39687*FLEN/8, x3, x1, x4) + +inst_13264: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x0; +op3val:0x7e00; valaddr_reg:x2; val_offset:39690*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39690*FLEN/8, x3, x1, x4) + +inst_13265: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x0; +op3val:0xfe00; valaddr_reg:x2; val_offset:39693*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39693*FLEN/8, x3, x1, x4) + +inst_13266: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x0; +op3val:0x7e01; valaddr_reg:x2; val_offset:39696*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39696*FLEN/8, x3, x1, x4) + +inst_13267: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x0; +op3val:0xfe55; valaddr_reg:x2; val_offset:39699*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39699*FLEN/8, x3, x1, x4) + +inst_13268: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x0; +op3val:0x7c01; valaddr_reg:x2; val_offset:39702*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39702*FLEN/8, x3, x1, x4) + +inst_13269: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x0; +op3val:0xfd55; valaddr_reg:x2; val_offset:39705*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39705*FLEN/8, x3, x1, x4) + +inst_13270: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x0; +op3val:0x3c00; valaddr_reg:x2; val_offset:39708*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39708*FLEN/8, x3, x1, x4) + +inst_13271: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x0; +op3val:0xbc00; valaddr_reg:x2; val_offset:39711*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39711*FLEN/8, x3, x1, x4) + +inst_13272: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8000; +op3val:0x0; valaddr_reg:x2; val_offset:39714*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39714*FLEN/8, x3, x1, x4) + +inst_13273: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8000; +op3val:0x8000; valaddr_reg:x2; val_offset:39717*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39717*FLEN/8, x3, x1, x4) + +inst_13274: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8000; +op3val:0x1; valaddr_reg:x2; val_offset:39720*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39720*FLEN/8, x3, x1, x4) + +inst_13275: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8000; +op3val:0x8001; valaddr_reg:x2; val_offset:39723*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39723*FLEN/8, x3, x1, x4) + +inst_13276: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8000; +op3val:0x2; valaddr_reg:x2; val_offset:39726*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39726*FLEN/8, x3, x1, x4) + +inst_13277: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8000; +op3val:0x83fe; valaddr_reg:x2; val_offset:39729*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39729*FLEN/8, x3, x1, x4) + +inst_13278: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8000; +op3val:0x3ff; valaddr_reg:x2; val_offset:39732*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39732*FLEN/8, x3, x1, x4) + +inst_13279: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8000; +op3val:0x83ff; valaddr_reg:x2; val_offset:39735*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39735*FLEN/8, x3, x1, x4) + +inst_13280: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8000; +op3val:0x400; valaddr_reg:x2; val_offset:39738*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39738*FLEN/8, x3, x1, x4) + +inst_13281: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8000; +op3val:0x8400; valaddr_reg:x2; val_offset:39741*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39741*FLEN/8, x3, x1, x4) + +inst_13282: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8000; +op3val:0x401; valaddr_reg:x2; val_offset:39744*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39744*FLEN/8, x3, x1, x4) + +inst_13283: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8000; +op3val:0x8455; valaddr_reg:x2; val_offset:39747*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39747*FLEN/8, x3, x1, x4) + +inst_13284: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x2; val_offset:39750*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39750*FLEN/8, x3, x1, x4) + +inst_13285: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x2; val_offset:39753*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39753*FLEN/8, x3, x1, x4) + +inst_13286: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8000; +op3val:0x7c00; valaddr_reg:x2; val_offset:39756*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39756*FLEN/8, x3, x1, x4) + +inst_13287: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8000; +op3val:0xfc00; valaddr_reg:x2; val_offset:39759*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39759*FLEN/8, x3, x1, x4) + +inst_13288: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8000; +op3val:0x7e00; valaddr_reg:x2; val_offset:39762*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39762*FLEN/8, x3, x1, x4) + +inst_13289: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8000; +op3val:0xfe00; valaddr_reg:x2; val_offset:39765*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39765*FLEN/8, x3, x1, x4) + +inst_13290: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8000; +op3val:0x7e01; valaddr_reg:x2; val_offset:39768*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39768*FLEN/8, x3, x1, x4) + +inst_13291: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8000; +op3val:0xfe55; valaddr_reg:x2; val_offset:39771*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39771*FLEN/8, x3, x1, x4) + +inst_13292: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8000; +op3val:0x7c01; valaddr_reg:x2; val_offset:39774*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39774*FLEN/8, x3, x1, x4) + +inst_13293: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8000; +op3val:0xfd55; valaddr_reg:x2; val_offset:39777*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39777*FLEN/8, x3, x1, x4) + +inst_13294: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8000; +op3val:0x3c00; valaddr_reg:x2; val_offset:39780*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39780*FLEN/8, x3, x1, x4) + +inst_13295: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8000; +op3val:0xbc00; valaddr_reg:x2; val_offset:39783*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39783*FLEN/8, x3, x1, x4) + +inst_13296: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x1; +op3val:0x0; valaddr_reg:x2; val_offset:39786*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39786*FLEN/8, x3, x1, x4) + +inst_13297: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x1; +op3val:0x8000; valaddr_reg:x2; val_offset:39789*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39789*FLEN/8, x3, x1, x4) + +inst_13298: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x1; +op3val:0x1; valaddr_reg:x2; val_offset:39792*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39792*FLEN/8, x3, x1, x4) + +inst_13299: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x1; +op3val:0x8001; valaddr_reg:x2; val_offset:39795*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39795*FLEN/8, x3, x1, x4) + +inst_13300: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x1; +op3val:0x2; valaddr_reg:x2; val_offset:39798*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39798*FLEN/8, x3, x1, x4) + +inst_13301: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x1; +op3val:0x83fe; valaddr_reg:x2; val_offset:39801*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39801*FLEN/8, x3, x1, x4) + +inst_13302: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x1; +op3val:0x3ff; valaddr_reg:x2; val_offset:39804*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39804*FLEN/8, x3, x1, x4) + +inst_13303: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x1; +op3val:0x83ff; valaddr_reg:x2; val_offset:39807*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39807*FLEN/8, x3, x1, x4) + +inst_13304: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x1; +op3val:0x400; valaddr_reg:x2; val_offset:39810*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39810*FLEN/8, x3, x1, x4) + +inst_13305: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x1; +op3val:0x8400; valaddr_reg:x2; val_offset:39813*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39813*FLEN/8, x3, x1, x4) + +inst_13306: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x1; +op3val:0x401; valaddr_reg:x2; val_offset:39816*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39816*FLEN/8, x3, x1, x4) + +inst_13307: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x1; +op3val:0x8455; valaddr_reg:x2; val_offset:39819*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39819*FLEN/8, x3, x1, x4) + +inst_13308: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x1; +op3val:0x7bff; valaddr_reg:x2; val_offset:39822*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39822*FLEN/8, x3, x1, x4) + +inst_13309: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x1; +op3val:0xfbff; valaddr_reg:x2; val_offset:39825*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39825*FLEN/8, x3, x1, x4) + +inst_13310: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x1; +op3val:0x7c00; valaddr_reg:x2; val_offset:39828*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39828*FLEN/8, x3, x1, x4) + +inst_13311: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x1; +op3val:0xfc00; valaddr_reg:x2; val_offset:39831*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39831*FLEN/8, x3, x1, x4) + +inst_13312: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x1; +op3val:0x7e00; valaddr_reg:x2; val_offset:39834*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39834*FLEN/8, x3, x1, x4) + +inst_13313: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x1; +op3val:0xfe00; valaddr_reg:x2; val_offset:39837*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39837*FLEN/8, x3, x1, x4) + +inst_13314: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x1; +op3val:0x7e01; valaddr_reg:x2; val_offset:39840*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39840*FLEN/8, x3, x1, x4) + +inst_13315: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x1; +op3val:0xfe55; valaddr_reg:x2; val_offset:39843*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39843*FLEN/8, x3, x1, x4) + +inst_13316: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x1; +op3val:0x7c01; valaddr_reg:x2; val_offset:39846*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39846*FLEN/8, x3, x1, x4) + +inst_13317: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x1; +op3val:0xfd55; valaddr_reg:x2; val_offset:39849*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39849*FLEN/8, x3, x1, x4) + +inst_13318: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x1; +op3val:0x3c00; valaddr_reg:x2; val_offset:39852*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39852*FLEN/8, x3, x1, x4) + +inst_13319: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x1; +op3val:0xbc00; valaddr_reg:x2; val_offset:39855*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39855*FLEN/8, x3, x1, x4) + +inst_13320: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8001; +op3val:0x0; valaddr_reg:x2; val_offset:39858*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39858*FLEN/8, x3, x1, x4) + +inst_13321: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8001; +op3val:0x8000; valaddr_reg:x2; val_offset:39861*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39861*FLEN/8, x3, x1, x4) + +inst_13322: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8001; +op3val:0x1; valaddr_reg:x2; val_offset:39864*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39864*FLEN/8, x3, x1, x4) + +inst_13323: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8001; +op3val:0x8001; valaddr_reg:x2; val_offset:39867*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39867*FLEN/8, x3, x1, x4) + +inst_13324: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8001; +op3val:0x2; valaddr_reg:x2; val_offset:39870*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39870*FLEN/8, x3, x1, x4) + +inst_13325: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8001; +op3val:0x83fe; valaddr_reg:x2; val_offset:39873*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39873*FLEN/8, x3, x1, x4) + +inst_13326: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8001; +op3val:0x3ff; valaddr_reg:x2; val_offset:39876*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39876*FLEN/8, x3, x1, x4) + +inst_13327: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8001; +op3val:0x83ff; valaddr_reg:x2; val_offset:39879*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39879*FLEN/8, x3, x1, x4) + +inst_13328: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8001; +op3val:0x400; valaddr_reg:x2; val_offset:39882*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39882*FLEN/8, x3, x1, x4) + +inst_13329: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8001; +op3val:0x8400; valaddr_reg:x2; val_offset:39885*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39885*FLEN/8, x3, x1, x4) + +inst_13330: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8001; +op3val:0x401; valaddr_reg:x2; val_offset:39888*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39888*FLEN/8, x3, x1, x4) + +inst_13331: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8001; +op3val:0x8455; valaddr_reg:x2; val_offset:39891*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39891*FLEN/8, x3, x1, x4) + +inst_13332: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8001; +op3val:0x7bff; valaddr_reg:x2; val_offset:39894*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39894*FLEN/8, x3, x1, x4) + +inst_13333: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8001; +op3val:0xfbff; valaddr_reg:x2; val_offset:39897*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39897*FLEN/8, x3, x1, x4) + +inst_13334: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8001; +op3val:0x7c00; valaddr_reg:x2; val_offset:39900*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39900*FLEN/8, x3, x1, x4) + +inst_13335: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8001; +op3val:0xfc00; valaddr_reg:x2; val_offset:39903*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39903*FLEN/8, x3, x1, x4) + +inst_13336: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8001; +op3val:0x7e00; valaddr_reg:x2; val_offset:39906*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39906*FLEN/8, x3, x1, x4) + +inst_13337: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8001; +op3val:0xfe00; valaddr_reg:x2; val_offset:39909*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39909*FLEN/8, x3, x1, x4) + +inst_13338: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8001; +op3val:0x7e01; valaddr_reg:x2; val_offset:39912*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39912*FLEN/8, x3, x1, x4) + +inst_13339: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8001; +op3val:0xfe55; valaddr_reg:x2; val_offset:39915*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39915*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_105) + +inst_13340: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8001; +op3val:0x7c01; valaddr_reg:x2; val_offset:39918*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39918*FLEN/8, x3, x1, x4) + +inst_13341: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8001; +op3val:0xfd55; valaddr_reg:x2; val_offset:39921*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39921*FLEN/8, x3, x1, x4) + +inst_13342: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8001; +op3val:0x3c00; valaddr_reg:x2; val_offset:39924*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39924*FLEN/8, x3, x1, x4) + +inst_13343: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8001; +op3val:0xbc00; valaddr_reg:x2; val_offset:39927*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39927*FLEN/8, x3, x1, x4) + +inst_13344: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x2; +op3val:0x0; valaddr_reg:x2; val_offset:39930*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39930*FLEN/8, x3, x1, x4) + +inst_13345: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x2; +op3val:0x8000; valaddr_reg:x2; val_offset:39933*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39933*FLEN/8, x3, x1, x4) + +inst_13346: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x2; +op3val:0x1; valaddr_reg:x2; val_offset:39936*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39936*FLEN/8, x3, x1, x4) + +inst_13347: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x2; +op3val:0x8001; valaddr_reg:x2; val_offset:39939*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39939*FLEN/8, x3, x1, x4) + +inst_13348: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x2; +op3val:0x2; valaddr_reg:x2; val_offset:39942*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39942*FLEN/8, x3, x1, x4) + +inst_13349: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x2; +op3val:0x83fe; valaddr_reg:x2; val_offset:39945*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39945*FLEN/8, x3, x1, x4) + +inst_13350: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x2; +op3val:0x3ff; valaddr_reg:x2; val_offset:39948*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39948*FLEN/8, x3, x1, x4) + +inst_13351: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x2; +op3val:0x83ff; valaddr_reg:x2; val_offset:39951*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39951*FLEN/8, x3, x1, x4) + +inst_13352: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x2; +op3val:0x400; valaddr_reg:x2; val_offset:39954*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39954*FLEN/8, x3, x1, x4) + +inst_13353: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x2; +op3val:0x8400; valaddr_reg:x2; val_offset:39957*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39957*FLEN/8, x3, x1, x4) + +inst_13354: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x2; +op3val:0x401; valaddr_reg:x2; val_offset:39960*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39960*FLEN/8, x3, x1, x4) + +inst_13355: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x2; +op3val:0x8455; valaddr_reg:x2; val_offset:39963*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39963*FLEN/8, x3, x1, x4) + +inst_13356: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x2; +op3val:0x7bff; valaddr_reg:x2; val_offset:39966*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39966*FLEN/8, x3, x1, x4) + +inst_13357: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x2; +op3val:0xfbff; valaddr_reg:x2; val_offset:39969*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39969*FLEN/8, x3, x1, x4) + +inst_13358: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x2; +op3val:0x7c00; valaddr_reg:x2; val_offset:39972*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39972*FLEN/8, x3, x1, x4) + +inst_13359: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x2; +op3val:0xfc00; valaddr_reg:x2; val_offset:39975*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39975*FLEN/8, x3, x1, x4) + +inst_13360: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x2; +op3val:0x7e00; valaddr_reg:x2; val_offset:39978*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39978*FLEN/8, x3, x1, x4) + +inst_13361: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x2; +op3val:0xfe00; valaddr_reg:x2; val_offset:39981*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39981*FLEN/8, x3, x1, x4) + +inst_13362: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x2; +op3val:0x7e01; valaddr_reg:x2; val_offset:39984*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39984*FLEN/8, x3, x1, x4) + +inst_13363: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x2; +op3val:0xfe55; valaddr_reg:x2; val_offset:39987*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39987*FLEN/8, x3, x1, x4) + +inst_13364: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x2; +op3val:0x7c01; valaddr_reg:x2; val_offset:39990*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39990*FLEN/8, x3, x1, x4) + +inst_13365: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x2; +op3val:0xfd55; valaddr_reg:x2; val_offset:39993*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39993*FLEN/8, x3, x1, x4) + +inst_13366: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x2; +op3val:0x3c00; valaddr_reg:x2; val_offset:39996*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39996*FLEN/8, x3, x1, x4) + +inst_13367: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x2; +op3val:0xbc00; valaddr_reg:x2; val_offset:39999*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39999*FLEN/8, x3, x1, x4) + +inst_13368: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x83fe; +op3val:0x0; valaddr_reg:x2; val_offset:40002*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40002*FLEN/8, x3, x1, x4) + +inst_13369: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x83fe; +op3val:0x8000; valaddr_reg:x2; val_offset:40005*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40005*FLEN/8, x3, x1, x4) + +inst_13370: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x83fe; +op3val:0x1; valaddr_reg:x2; val_offset:40008*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40008*FLEN/8, x3, x1, x4) + +inst_13371: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x83fe; +op3val:0x8001; valaddr_reg:x2; val_offset:40011*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40011*FLEN/8, x3, x1, x4) + +inst_13372: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x83fe; +op3val:0x2; valaddr_reg:x2; val_offset:40014*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40014*FLEN/8, x3, x1, x4) + +inst_13373: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x83fe; +op3val:0x83fe; valaddr_reg:x2; val_offset:40017*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40017*FLEN/8, x3, x1, x4) + +inst_13374: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x83fe; +op3val:0x3ff; valaddr_reg:x2; val_offset:40020*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40020*FLEN/8, x3, x1, x4) + +inst_13375: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x83fe; +op3val:0x83ff; valaddr_reg:x2; val_offset:40023*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40023*FLEN/8, x3, x1, x4) + +inst_13376: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x83fe; +op3val:0x400; valaddr_reg:x2; val_offset:40026*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40026*FLEN/8, x3, x1, x4) + +inst_13377: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x83fe; +op3val:0x8400; valaddr_reg:x2; val_offset:40029*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40029*FLEN/8, x3, x1, x4) + +inst_13378: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x83fe; +op3val:0x401; valaddr_reg:x2; val_offset:40032*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40032*FLEN/8, x3, x1, x4) + +inst_13379: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x83fe; +op3val:0x8455; valaddr_reg:x2; val_offset:40035*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40035*FLEN/8, x3, x1, x4) + +inst_13380: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x83fe; +op3val:0x7bff; valaddr_reg:x2; val_offset:40038*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40038*FLEN/8, x3, x1, x4) + +inst_13381: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x83fe; +op3val:0xfbff; valaddr_reg:x2; val_offset:40041*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40041*FLEN/8, x3, x1, x4) + +inst_13382: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x83fe; +op3val:0x7c00; valaddr_reg:x2; val_offset:40044*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40044*FLEN/8, x3, x1, x4) + +inst_13383: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x83fe; +op3val:0xfc00; valaddr_reg:x2; val_offset:40047*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40047*FLEN/8, x3, x1, x4) + +inst_13384: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x83fe; +op3val:0x7e00; valaddr_reg:x2; val_offset:40050*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40050*FLEN/8, x3, x1, x4) + +inst_13385: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x83fe; +op3val:0xfe00; valaddr_reg:x2; val_offset:40053*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40053*FLEN/8, x3, x1, x4) + +inst_13386: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x83fe; +op3val:0x7e01; valaddr_reg:x2; val_offset:40056*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40056*FLEN/8, x3, x1, x4) + +inst_13387: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x83fe; +op3val:0xfe55; valaddr_reg:x2; val_offset:40059*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40059*FLEN/8, x3, x1, x4) + +inst_13388: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x83fe; +op3val:0x7c01; valaddr_reg:x2; val_offset:40062*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40062*FLEN/8, x3, x1, x4) + +inst_13389: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x83fe; +op3val:0xfd55; valaddr_reg:x2; val_offset:40065*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40065*FLEN/8, x3, x1, x4) + +inst_13390: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x83fe; +op3val:0x3c00; valaddr_reg:x2; val_offset:40068*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40068*FLEN/8, x3, x1, x4) + +inst_13391: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x83fe; +op3val:0xbc00; valaddr_reg:x2; val_offset:40071*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40071*FLEN/8, x3, x1, x4) + +inst_13392: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x3ff; +op3val:0x0; valaddr_reg:x2; val_offset:40074*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40074*FLEN/8, x3, x1, x4) + +inst_13393: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x3ff; +op3val:0x8000; valaddr_reg:x2; val_offset:40077*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40077*FLEN/8, x3, x1, x4) + +inst_13394: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x3ff; +op3val:0x1; valaddr_reg:x2; val_offset:40080*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40080*FLEN/8, x3, x1, x4) + +inst_13395: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x3ff; +op3val:0x8001; valaddr_reg:x2; val_offset:40083*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40083*FLEN/8, x3, x1, x4) + +inst_13396: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x3ff; +op3val:0x2; valaddr_reg:x2; val_offset:40086*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40086*FLEN/8, x3, x1, x4) + +inst_13397: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x3ff; +op3val:0x83fe; valaddr_reg:x2; val_offset:40089*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40089*FLEN/8, x3, x1, x4) + +inst_13398: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x3ff; +op3val:0x3ff; valaddr_reg:x2; val_offset:40092*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40092*FLEN/8, x3, x1, x4) + +inst_13399: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x3ff; +op3val:0x83ff; valaddr_reg:x2; val_offset:40095*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40095*FLEN/8, x3, x1, x4) + +inst_13400: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x3ff; +op3val:0x400; valaddr_reg:x2; val_offset:40098*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40098*FLEN/8, x3, x1, x4) + +inst_13401: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x3ff; +op3val:0x8400; valaddr_reg:x2; val_offset:40101*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40101*FLEN/8, x3, x1, x4) + +inst_13402: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x3ff; +op3val:0x401; valaddr_reg:x2; val_offset:40104*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40104*FLEN/8, x3, x1, x4) + +inst_13403: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x3ff; +op3val:0x8455; valaddr_reg:x2; val_offset:40107*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40107*FLEN/8, x3, x1, x4) + +inst_13404: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x3ff; +op3val:0x7bff; valaddr_reg:x2; val_offset:40110*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40110*FLEN/8, x3, x1, x4) + +inst_13405: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x3ff; +op3val:0xfbff; valaddr_reg:x2; val_offset:40113*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40113*FLEN/8, x3, x1, x4) + +inst_13406: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x3ff; +op3val:0x7c00; valaddr_reg:x2; val_offset:40116*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40116*FLEN/8, x3, x1, x4) + +inst_13407: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x3ff; +op3val:0xfc00; valaddr_reg:x2; val_offset:40119*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40119*FLEN/8, x3, x1, x4) + +inst_13408: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x3ff; +op3val:0x7e00; valaddr_reg:x2; val_offset:40122*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40122*FLEN/8, x3, x1, x4) + +inst_13409: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x3ff; +op3val:0xfe00; valaddr_reg:x2; val_offset:40125*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40125*FLEN/8, x3, x1, x4) + +inst_13410: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x3ff; +op3val:0x7e01; valaddr_reg:x2; val_offset:40128*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40128*FLEN/8, x3, x1, x4) + +inst_13411: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x3ff; +op3val:0xfe55; valaddr_reg:x2; val_offset:40131*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40131*FLEN/8, x3, x1, x4) + +inst_13412: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x3ff; +op3val:0x7c01; valaddr_reg:x2; val_offset:40134*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40134*FLEN/8, x3, x1, x4) + +inst_13413: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x3ff; +op3val:0xfd55; valaddr_reg:x2; val_offset:40137*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40137*FLEN/8, x3, x1, x4) + +inst_13414: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x3ff; +op3val:0x3c00; valaddr_reg:x2; val_offset:40140*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40140*FLEN/8, x3, x1, x4) + +inst_13415: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x3ff; +op3val:0xbc00; valaddr_reg:x2; val_offset:40143*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40143*FLEN/8, x3, x1, x4) + +inst_13416: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x83ff; +op3val:0x0; valaddr_reg:x2; val_offset:40146*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40146*FLEN/8, x3, x1, x4) + +inst_13417: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x83ff; +op3val:0x8000; valaddr_reg:x2; val_offset:40149*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40149*FLEN/8, x3, x1, x4) + +inst_13418: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x83ff; +op3val:0x1; valaddr_reg:x2; val_offset:40152*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40152*FLEN/8, x3, x1, x4) + +inst_13419: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x83ff; +op3val:0x8001; valaddr_reg:x2; val_offset:40155*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40155*FLEN/8, x3, x1, x4) + +inst_13420: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x83ff; +op3val:0x2; valaddr_reg:x2; val_offset:40158*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40158*FLEN/8, x3, x1, x4) + +inst_13421: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x83ff; +op3val:0x83fe; valaddr_reg:x2; val_offset:40161*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40161*FLEN/8, x3, x1, x4) + +inst_13422: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x83ff; +op3val:0x3ff; valaddr_reg:x2; val_offset:40164*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40164*FLEN/8, x3, x1, x4) + +inst_13423: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x83ff; +op3val:0x83ff; valaddr_reg:x2; val_offset:40167*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40167*FLEN/8, x3, x1, x4) + +inst_13424: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x83ff; +op3val:0x400; valaddr_reg:x2; val_offset:40170*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40170*FLEN/8, x3, x1, x4) + +inst_13425: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x83ff; +op3val:0x8400; valaddr_reg:x2; val_offset:40173*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40173*FLEN/8, x3, x1, x4) + +inst_13426: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x83ff; +op3val:0x401; valaddr_reg:x2; val_offset:40176*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40176*FLEN/8, x3, x1, x4) + +inst_13427: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x83ff; +op3val:0x8455; valaddr_reg:x2; val_offset:40179*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40179*FLEN/8, x3, x1, x4) + +inst_13428: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x83ff; +op3val:0x7bff; valaddr_reg:x2; val_offset:40182*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40182*FLEN/8, x3, x1, x4) + +inst_13429: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x83ff; +op3val:0xfbff; valaddr_reg:x2; val_offset:40185*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40185*FLEN/8, x3, x1, x4) + +inst_13430: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x83ff; +op3val:0x7c00; valaddr_reg:x2; val_offset:40188*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40188*FLEN/8, x3, x1, x4) + +inst_13431: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x83ff; +op3val:0xfc00; valaddr_reg:x2; val_offset:40191*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40191*FLEN/8, x3, x1, x4) + +inst_13432: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x83ff; +op3val:0x7e00; valaddr_reg:x2; val_offset:40194*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40194*FLEN/8, x3, x1, x4) + +inst_13433: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x83ff; +op3val:0xfe00; valaddr_reg:x2; val_offset:40197*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40197*FLEN/8, x3, x1, x4) + +inst_13434: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x83ff; +op3val:0x7e01; valaddr_reg:x2; val_offset:40200*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40200*FLEN/8, x3, x1, x4) + +inst_13435: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x83ff; +op3val:0xfe55; valaddr_reg:x2; val_offset:40203*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40203*FLEN/8, x3, x1, x4) + +inst_13436: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x83ff; +op3val:0x7c01; valaddr_reg:x2; val_offset:40206*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40206*FLEN/8, x3, x1, x4) + +inst_13437: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x83ff; +op3val:0xfd55; valaddr_reg:x2; val_offset:40209*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40209*FLEN/8, x3, x1, x4) + +inst_13438: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x83ff; +op3val:0x3c00; valaddr_reg:x2; val_offset:40212*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40212*FLEN/8, x3, x1, x4) + +inst_13439: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x83ff; +op3val:0xbc00; valaddr_reg:x2; val_offset:40215*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40215*FLEN/8, x3, x1, x4) + +inst_13440: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x400; +op3val:0x0; valaddr_reg:x2; val_offset:40218*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40218*FLEN/8, x3, x1, x4) + +inst_13441: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x400; +op3val:0x8000; valaddr_reg:x2; val_offset:40221*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40221*FLEN/8, x3, x1, x4) + +inst_13442: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x400; +op3val:0x1; valaddr_reg:x2; val_offset:40224*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40224*FLEN/8, x3, x1, x4) + +inst_13443: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x400; +op3val:0x8001; valaddr_reg:x2; val_offset:40227*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40227*FLEN/8, x3, x1, x4) + +inst_13444: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x400; +op3val:0x2; valaddr_reg:x2; val_offset:40230*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40230*FLEN/8, x3, x1, x4) + +inst_13445: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x400; +op3val:0x83fe; valaddr_reg:x2; val_offset:40233*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40233*FLEN/8, x3, x1, x4) + +inst_13446: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x400; +op3val:0x3ff; valaddr_reg:x2; val_offset:40236*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40236*FLEN/8, x3, x1, x4) + +inst_13447: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x400; +op3val:0x83ff; valaddr_reg:x2; val_offset:40239*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40239*FLEN/8, x3, x1, x4) + +inst_13448: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x400; +op3val:0x400; valaddr_reg:x2; val_offset:40242*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40242*FLEN/8, x3, x1, x4) + +inst_13449: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x400; +op3val:0x8400; valaddr_reg:x2; val_offset:40245*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40245*FLEN/8, x3, x1, x4) + +inst_13450: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x400; +op3val:0x401; valaddr_reg:x2; val_offset:40248*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40248*FLEN/8, x3, x1, x4) + +inst_13451: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x400; +op3val:0x8455; valaddr_reg:x2; val_offset:40251*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40251*FLEN/8, x3, x1, x4) + +inst_13452: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x400; +op3val:0x7bff; valaddr_reg:x2; val_offset:40254*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40254*FLEN/8, x3, x1, x4) + +inst_13453: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x400; +op3val:0xfbff; valaddr_reg:x2; val_offset:40257*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40257*FLEN/8, x3, x1, x4) + +inst_13454: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x400; +op3val:0x7c00; valaddr_reg:x2; val_offset:40260*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40260*FLEN/8, x3, x1, x4) + +inst_13455: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x400; +op3val:0xfc00; valaddr_reg:x2; val_offset:40263*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40263*FLEN/8, x3, x1, x4) + +inst_13456: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x400; +op3val:0x7e00; valaddr_reg:x2; val_offset:40266*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40266*FLEN/8, x3, x1, x4) + +inst_13457: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x400; +op3val:0xfe00; valaddr_reg:x2; val_offset:40269*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40269*FLEN/8, x3, x1, x4) + +inst_13458: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x400; +op3val:0x7e01; valaddr_reg:x2; val_offset:40272*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40272*FLEN/8, x3, x1, x4) + +inst_13459: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x400; +op3val:0xfe55; valaddr_reg:x2; val_offset:40275*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40275*FLEN/8, x3, x1, x4) + +inst_13460: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x400; +op3val:0x7c01; valaddr_reg:x2; val_offset:40278*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40278*FLEN/8, x3, x1, x4) + +inst_13461: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x400; +op3val:0xfd55; valaddr_reg:x2; val_offset:40281*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40281*FLEN/8, x3, x1, x4) + +inst_13462: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x400; +op3val:0x3c00; valaddr_reg:x2; val_offset:40284*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40284*FLEN/8, x3, x1, x4) + +inst_13463: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x400; +op3val:0xbc00; valaddr_reg:x2; val_offset:40287*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40287*FLEN/8, x3, x1, x4) + +inst_13464: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8400; +op3val:0x0; valaddr_reg:x2; val_offset:40290*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40290*FLEN/8, x3, x1, x4) + +inst_13465: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8400; +op3val:0x8000; valaddr_reg:x2; val_offset:40293*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40293*FLEN/8, x3, x1, x4) + +inst_13466: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8400; +op3val:0x1; valaddr_reg:x2; val_offset:40296*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40296*FLEN/8, x3, x1, x4) + +inst_13467: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8400; +op3val:0x8001; valaddr_reg:x2; val_offset:40299*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40299*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_106) + +inst_13468: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8400; +op3val:0x2; valaddr_reg:x2; val_offset:40302*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40302*FLEN/8, x3, x1, x4) + +inst_13469: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8400; +op3val:0x83fe; valaddr_reg:x2; val_offset:40305*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40305*FLEN/8, x3, x1, x4) + +inst_13470: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8400; +op3val:0x3ff; valaddr_reg:x2; val_offset:40308*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40308*FLEN/8, x3, x1, x4) + +inst_13471: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8400; +op3val:0x83ff; valaddr_reg:x2; val_offset:40311*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40311*FLEN/8, x3, x1, x4) + +inst_13472: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8400; +op3val:0x400; valaddr_reg:x2; val_offset:40314*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40314*FLEN/8, x3, x1, x4) + +inst_13473: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8400; +op3val:0x8400; valaddr_reg:x2; val_offset:40317*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40317*FLEN/8, x3, x1, x4) + +inst_13474: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8400; +op3val:0x401; valaddr_reg:x2; val_offset:40320*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40320*FLEN/8, x3, x1, x4) + +inst_13475: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8400; +op3val:0x8455; valaddr_reg:x2; val_offset:40323*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40323*FLEN/8, x3, x1, x4) + +inst_13476: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8400; +op3val:0x7bff; valaddr_reg:x2; val_offset:40326*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40326*FLEN/8, x3, x1, x4) + +inst_13477: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8400; +op3val:0xfbff; valaddr_reg:x2; val_offset:40329*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40329*FLEN/8, x3, x1, x4) + +inst_13478: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8400; +op3val:0x7c00; valaddr_reg:x2; val_offset:40332*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40332*FLEN/8, x3, x1, x4) + +inst_13479: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8400; +op3val:0xfc00; valaddr_reg:x2; val_offset:40335*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40335*FLEN/8, x3, x1, x4) + +inst_13480: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8400; +op3val:0x7e00; valaddr_reg:x2; val_offset:40338*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40338*FLEN/8, x3, x1, x4) + +inst_13481: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8400; +op3val:0xfe00; valaddr_reg:x2; val_offset:40341*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40341*FLEN/8, x3, x1, x4) + +inst_13482: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8400; +op3val:0x7e01; valaddr_reg:x2; val_offset:40344*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40344*FLEN/8, x3, x1, x4) + +inst_13483: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8400; +op3val:0xfe55; valaddr_reg:x2; val_offset:40347*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40347*FLEN/8, x3, x1, x4) + +inst_13484: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8400; +op3val:0x7c01; valaddr_reg:x2; val_offset:40350*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40350*FLEN/8, x3, x1, x4) + +inst_13485: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8400; +op3val:0xfd55; valaddr_reg:x2; val_offset:40353*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40353*FLEN/8, x3, x1, x4) + +inst_13486: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8400; +op3val:0x3c00; valaddr_reg:x2; val_offset:40356*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40356*FLEN/8, x3, x1, x4) + +inst_13487: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8400; +op3val:0xbc00; valaddr_reg:x2; val_offset:40359*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40359*FLEN/8, x3, x1, x4) + +inst_13488: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x401; +op3val:0x0; valaddr_reg:x2; val_offset:40362*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40362*FLEN/8, x3, x1, x4) + +inst_13489: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x401; +op3val:0x8000; valaddr_reg:x2; val_offset:40365*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40365*FLEN/8, x3, x1, x4) + +inst_13490: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x401; +op3val:0x1; valaddr_reg:x2; val_offset:40368*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40368*FLEN/8, x3, x1, x4) + +inst_13491: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x401; +op3val:0x8001; valaddr_reg:x2; val_offset:40371*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40371*FLEN/8, x3, x1, x4) + +inst_13492: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x401; +op3val:0x2; valaddr_reg:x2; val_offset:40374*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40374*FLEN/8, x3, x1, x4) + +inst_13493: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x401; +op3val:0x83fe; valaddr_reg:x2; val_offset:40377*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40377*FLEN/8, x3, x1, x4) + +inst_13494: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x401; +op3val:0x3ff; valaddr_reg:x2; val_offset:40380*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40380*FLEN/8, x3, x1, x4) + +inst_13495: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x401; +op3val:0x83ff; valaddr_reg:x2; val_offset:40383*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40383*FLEN/8, x3, x1, x4) + +inst_13496: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x401; +op3val:0x400; valaddr_reg:x2; val_offset:40386*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40386*FLEN/8, x3, x1, x4) + +inst_13497: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x401; +op3val:0x8400; valaddr_reg:x2; val_offset:40389*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40389*FLEN/8, x3, x1, x4) + +inst_13498: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x401; +op3val:0x401; valaddr_reg:x2; val_offset:40392*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40392*FLEN/8, x3, x1, x4) + +inst_13499: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x401; +op3val:0x8455; valaddr_reg:x2; val_offset:40395*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40395*FLEN/8, x3, x1, x4) + +inst_13500: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x401; +op3val:0x7bff; valaddr_reg:x2; val_offset:40398*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40398*FLEN/8, x3, x1, x4) + +inst_13501: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x401; +op3val:0xfbff; valaddr_reg:x2; val_offset:40401*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40401*FLEN/8, x3, x1, x4) + +inst_13502: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x401; +op3val:0x7c00; valaddr_reg:x2; val_offset:40404*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40404*FLEN/8, x3, x1, x4) + +inst_13503: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x401; +op3val:0xfc00; valaddr_reg:x2; val_offset:40407*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40407*FLEN/8, x3, x1, x4) + +inst_13504: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x401; +op3val:0x7e00; valaddr_reg:x2; val_offset:40410*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40410*FLEN/8, x3, x1, x4) + +inst_13505: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x401; +op3val:0xfe00; valaddr_reg:x2; val_offset:40413*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40413*FLEN/8, x3, x1, x4) + +inst_13506: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x401; +op3val:0x7e01; valaddr_reg:x2; val_offset:40416*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40416*FLEN/8, x3, x1, x4) + +inst_13507: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x401; +op3val:0xfe55; valaddr_reg:x2; val_offset:40419*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40419*FLEN/8, x3, x1, x4) + +inst_13508: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x401; +op3val:0x7c01; valaddr_reg:x2; val_offset:40422*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40422*FLEN/8, x3, x1, x4) + +inst_13509: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x401; +op3val:0xfd55; valaddr_reg:x2; val_offset:40425*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40425*FLEN/8, x3, x1, x4) + +inst_13510: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x401; +op3val:0x3c00; valaddr_reg:x2; val_offset:40428*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40428*FLEN/8, x3, x1, x4) + +inst_13511: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x401; +op3val:0xbc00; valaddr_reg:x2; val_offset:40431*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40431*FLEN/8, x3, x1, x4) + +inst_13512: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8455; +op3val:0x0; valaddr_reg:x2; val_offset:40434*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40434*FLEN/8, x3, x1, x4) + +inst_13513: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8455; +op3val:0x8000; valaddr_reg:x2; val_offset:40437*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40437*FLEN/8, x3, x1, x4) + +inst_13514: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8455; +op3val:0x1; valaddr_reg:x2; val_offset:40440*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40440*FLEN/8, x3, x1, x4) + +inst_13515: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8455; +op3val:0x8001; valaddr_reg:x2; val_offset:40443*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40443*FLEN/8, x3, x1, x4) + +inst_13516: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8455; +op3val:0x2; valaddr_reg:x2; val_offset:40446*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40446*FLEN/8, x3, x1, x4) + +inst_13517: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8455; +op3val:0x83fe; valaddr_reg:x2; val_offset:40449*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40449*FLEN/8, x3, x1, x4) + +inst_13518: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8455; +op3val:0x3ff; valaddr_reg:x2; val_offset:40452*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40452*FLEN/8, x3, x1, x4) + +inst_13519: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8455; +op3val:0x83ff; valaddr_reg:x2; val_offset:40455*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40455*FLEN/8, x3, x1, x4) + +inst_13520: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8455; +op3val:0x400; valaddr_reg:x2; val_offset:40458*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40458*FLEN/8, x3, x1, x4) + +inst_13521: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8455; +op3val:0x8400; valaddr_reg:x2; val_offset:40461*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40461*FLEN/8, x3, x1, x4) + +inst_13522: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8455; +op3val:0x401; valaddr_reg:x2; val_offset:40464*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40464*FLEN/8, x3, x1, x4) + +inst_13523: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8455; +op3val:0x8455; valaddr_reg:x2; val_offset:40467*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40467*FLEN/8, x3, x1, x4) + +inst_13524: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8455; +op3val:0x7bff; valaddr_reg:x2; val_offset:40470*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40470*FLEN/8, x3, x1, x4) + +inst_13525: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8455; +op3val:0xfbff; valaddr_reg:x2; val_offset:40473*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40473*FLEN/8, x3, x1, x4) + +inst_13526: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8455; +op3val:0x7c00; valaddr_reg:x2; val_offset:40476*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40476*FLEN/8, x3, x1, x4) + +inst_13527: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8455; +op3val:0xfc00; valaddr_reg:x2; val_offset:40479*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40479*FLEN/8, x3, x1, x4) + +inst_13528: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8455; +op3val:0x7e00; valaddr_reg:x2; val_offset:40482*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40482*FLEN/8, x3, x1, x4) + +inst_13529: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8455; +op3val:0xfe00; valaddr_reg:x2; val_offset:40485*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40485*FLEN/8, x3, x1, x4) + +inst_13530: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8455; +op3val:0x7e01; valaddr_reg:x2; val_offset:40488*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40488*FLEN/8, x3, x1, x4) + +inst_13531: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8455; +op3val:0xfe55; valaddr_reg:x2; val_offset:40491*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40491*FLEN/8, x3, x1, x4) + +inst_13532: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8455; +op3val:0x7c01; valaddr_reg:x2; val_offset:40494*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40494*FLEN/8, x3, x1, x4) + +inst_13533: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8455; +op3val:0xfd55; valaddr_reg:x2; val_offset:40497*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40497*FLEN/8, x3, x1, x4) + +inst_13534: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8455; +op3val:0x3c00; valaddr_reg:x2; val_offset:40500*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40500*FLEN/8, x3, x1, x4) + +inst_13535: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x8455; +op3val:0xbc00; valaddr_reg:x2; val_offset:40503*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40503*FLEN/8, x3, x1, x4) + +inst_13536: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7bff; +op3val:0x0; valaddr_reg:x2; val_offset:40506*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40506*FLEN/8, x3, x1, x4) + +inst_13537: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7bff; +op3val:0x8000; valaddr_reg:x2; val_offset:40509*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40509*FLEN/8, x3, x1, x4) + +inst_13538: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7bff; +op3val:0x1; valaddr_reg:x2; val_offset:40512*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40512*FLEN/8, x3, x1, x4) + +inst_13539: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7bff; +op3val:0x8001; valaddr_reg:x2; val_offset:40515*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40515*FLEN/8, x3, x1, x4) + +inst_13540: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7bff; +op3val:0x2; valaddr_reg:x2; val_offset:40518*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40518*FLEN/8, x3, x1, x4) + +inst_13541: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7bff; +op3val:0x83fe; valaddr_reg:x2; val_offset:40521*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40521*FLEN/8, x3, x1, x4) + +inst_13542: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7bff; +op3val:0x3ff; valaddr_reg:x2; val_offset:40524*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40524*FLEN/8, x3, x1, x4) + +inst_13543: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7bff; +op3val:0x83ff; valaddr_reg:x2; val_offset:40527*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40527*FLEN/8, x3, x1, x4) + +inst_13544: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7bff; +op3val:0x400; valaddr_reg:x2; val_offset:40530*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40530*FLEN/8, x3, x1, x4) + +inst_13545: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7bff; +op3val:0x8400; valaddr_reg:x2; val_offset:40533*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40533*FLEN/8, x3, x1, x4) + +inst_13546: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7bff; +op3val:0x401; valaddr_reg:x2; val_offset:40536*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40536*FLEN/8, x3, x1, x4) + +inst_13547: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7bff; +op3val:0x8455; valaddr_reg:x2; val_offset:40539*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40539*FLEN/8, x3, x1, x4) + +inst_13548: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7bff; +op3val:0x7bff; valaddr_reg:x2; val_offset:40542*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40542*FLEN/8, x3, x1, x4) + +inst_13549: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7bff; +op3val:0xfbff; valaddr_reg:x2; val_offset:40545*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40545*FLEN/8, x3, x1, x4) + +inst_13550: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7bff; +op3val:0x7c00; valaddr_reg:x2; val_offset:40548*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40548*FLEN/8, x3, x1, x4) + +inst_13551: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7bff; +op3val:0xfc00; valaddr_reg:x2; val_offset:40551*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40551*FLEN/8, x3, x1, x4) + +inst_13552: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7bff; +op3val:0x7e00; valaddr_reg:x2; val_offset:40554*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40554*FLEN/8, x3, x1, x4) + +inst_13553: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7bff; +op3val:0xfe00; valaddr_reg:x2; val_offset:40557*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40557*FLEN/8, x3, x1, x4) + +inst_13554: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7bff; +op3val:0x7e01; valaddr_reg:x2; val_offset:40560*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40560*FLEN/8, x3, x1, x4) + +inst_13555: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7bff; +op3val:0xfe55; valaddr_reg:x2; val_offset:40563*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40563*FLEN/8, x3, x1, x4) + +inst_13556: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7bff; +op3val:0x7c01; valaddr_reg:x2; val_offset:40566*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40566*FLEN/8, x3, x1, x4) + +inst_13557: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7bff; +op3val:0xfd55; valaddr_reg:x2; val_offset:40569*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40569*FLEN/8, x3, x1, x4) + +inst_13558: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7bff; +op3val:0x3c00; valaddr_reg:x2; val_offset:40572*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40572*FLEN/8, x3, x1, x4) + +inst_13559: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7bff; +op3val:0xbc00; valaddr_reg:x2; val_offset:40575*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40575*FLEN/8, x3, x1, x4) + +inst_13560: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfbff; +op3val:0x0; valaddr_reg:x2; val_offset:40578*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40578*FLEN/8, x3, x1, x4) + +inst_13561: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfbff; +op3val:0x8000; valaddr_reg:x2; val_offset:40581*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40581*FLEN/8, x3, x1, x4) + +inst_13562: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfbff; +op3val:0x1; valaddr_reg:x2; val_offset:40584*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40584*FLEN/8, x3, x1, x4) + +inst_13563: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfbff; +op3val:0x8001; valaddr_reg:x2; val_offset:40587*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40587*FLEN/8, x3, x1, x4) + +inst_13564: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfbff; +op3val:0x2; valaddr_reg:x2; val_offset:40590*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40590*FLEN/8, x3, x1, x4) + +inst_13565: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfbff; +op3val:0x83fe; valaddr_reg:x2; val_offset:40593*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40593*FLEN/8, x3, x1, x4) + +inst_13566: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfbff; +op3val:0x3ff; valaddr_reg:x2; val_offset:40596*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40596*FLEN/8, x3, x1, x4) + +inst_13567: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfbff; +op3val:0x83ff; valaddr_reg:x2; val_offset:40599*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40599*FLEN/8, x3, x1, x4) + +inst_13568: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfbff; +op3val:0x400; valaddr_reg:x2; val_offset:40602*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40602*FLEN/8, x3, x1, x4) + +inst_13569: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfbff; +op3val:0x8400; valaddr_reg:x2; val_offset:40605*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40605*FLEN/8, x3, x1, x4) + +inst_13570: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfbff; +op3val:0x401; valaddr_reg:x2; val_offset:40608*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40608*FLEN/8, x3, x1, x4) + +inst_13571: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfbff; +op3val:0x8455; valaddr_reg:x2; val_offset:40611*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40611*FLEN/8, x3, x1, x4) + +inst_13572: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfbff; +op3val:0x7bff; valaddr_reg:x2; val_offset:40614*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40614*FLEN/8, x3, x1, x4) + +inst_13573: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfbff; +op3val:0xfbff; valaddr_reg:x2; val_offset:40617*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40617*FLEN/8, x3, x1, x4) + +inst_13574: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfbff; +op3val:0x7c00; valaddr_reg:x2; val_offset:40620*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40620*FLEN/8, x3, x1, x4) + +inst_13575: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfbff; +op3val:0xfc00; valaddr_reg:x2; val_offset:40623*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40623*FLEN/8, x3, x1, x4) + +inst_13576: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfbff; +op3val:0x7e00; valaddr_reg:x2; val_offset:40626*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40626*FLEN/8, x3, x1, x4) + +inst_13577: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfbff; +op3val:0xfe00; valaddr_reg:x2; val_offset:40629*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40629*FLEN/8, x3, x1, x4) + +inst_13578: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfbff; +op3val:0x7e01; valaddr_reg:x2; val_offset:40632*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40632*FLEN/8, x3, x1, x4) + +inst_13579: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfbff; +op3val:0xfe55; valaddr_reg:x2; val_offset:40635*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40635*FLEN/8, x3, x1, x4) + +inst_13580: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfbff; +op3val:0x7c01; valaddr_reg:x2; val_offset:40638*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40638*FLEN/8, x3, x1, x4) + +inst_13581: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfbff; +op3val:0xfd55; valaddr_reg:x2; val_offset:40641*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40641*FLEN/8, x3, x1, x4) + +inst_13582: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfbff; +op3val:0x3c00; valaddr_reg:x2; val_offset:40644*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40644*FLEN/8, x3, x1, x4) + +inst_13583: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfbff; +op3val:0xbc00; valaddr_reg:x2; val_offset:40647*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40647*FLEN/8, x3, x1, x4) + +inst_13584: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7c00; +op3val:0x0; valaddr_reg:x2; val_offset:40650*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40650*FLEN/8, x3, x1, x4) + +inst_13585: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7c00; +op3val:0x8000; valaddr_reg:x2; val_offset:40653*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40653*FLEN/8, x3, x1, x4) + +inst_13586: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7c00; +op3val:0x1; valaddr_reg:x2; val_offset:40656*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40656*FLEN/8, x3, x1, x4) + +inst_13587: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7c00; +op3val:0x8001; valaddr_reg:x2; val_offset:40659*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40659*FLEN/8, x3, x1, x4) + +inst_13588: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7c00; +op3val:0x2; valaddr_reg:x2; val_offset:40662*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40662*FLEN/8, x3, x1, x4) + +inst_13589: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7c00; +op3val:0x83fe; valaddr_reg:x2; val_offset:40665*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40665*FLEN/8, x3, x1, x4) + +inst_13590: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7c00; +op3val:0x3ff; valaddr_reg:x2; val_offset:40668*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40668*FLEN/8, x3, x1, x4) + +inst_13591: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7c00; +op3val:0x83ff; valaddr_reg:x2; val_offset:40671*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40671*FLEN/8, x3, x1, x4) + +inst_13592: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7c00; +op3val:0x400; valaddr_reg:x2; val_offset:40674*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40674*FLEN/8, x3, x1, x4) + +inst_13593: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7c00; +op3val:0x8400; valaddr_reg:x2; val_offset:40677*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40677*FLEN/8, x3, x1, x4) + +inst_13594: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7c00; +op3val:0x401; valaddr_reg:x2; val_offset:40680*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40680*FLEN/8, x3, x1, x4) + +inst_13595: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7c00; +op3val:0x8455; valaddr_reg:x2; val_offset:40683*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40683*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_107) + +inst_13596: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7c00; +op3val:0x7bff; valaddr_reg:x2; val_offset:40686*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40686*FLEN/8, x3, x1, x4) + +inst_13597: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7c00; +op3val:0xfbff; valaddr_reg:x2; val_offset:40689*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40689*FLEN/8, x3, x1, x4) + +inst_13598: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7c00; +op3val:0x7c00; valaddr_reg:x2; val_offset:40692*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40692*FLEN/8, x3, x1, x4) + +inst_13599: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7c00; +op3val:0xfc00; valaddr_reg:x2; val_offset:40695*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40695*FLEN/8, x3, x1, x4) + +inst_13600: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7c00; +op3val:0x7e00; valaddr_reg:x2; val_offset:40698*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40698*FLEN/8, x3, x1, x4) + +inst_13601: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7c00; +op3val:0xfe00; valaddr_reg:x2; val_offset:40701*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40701*FLEN/8, x3, x1, x4) + +inst_13602: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7c00; +op3val:0x7e01; valaddr_reg:x2; val_offset:40704*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40704*FLEN/8, x3, x1, x4) + +inst_13603: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7c00; +op3val:0xfe55; valaddr_reg:x2; val_offset:40707*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40707*FLEN/8, x3, x1, x4) + +inst_13604: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7c00; +op3val:0x7c01; valaddr_reg:x2; val_offset:40710*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40710*FLEN/8, x3, x1, x4) + +inst_13605: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7c00; +op3val:0xfd55; valaddr_reg:x2; val_offset:40713*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40713*FLEN/8, x3, x1, x4) + +inst_13606: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7c00; +op3val:0x3c00; valaddr_reg:x2; val_offset:40716*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40716*FLEN/8, x3, x1, x4) + +inst_13607: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7c00; +op3val:0xbc00; valaddr_reg:x2; val_offset:40719*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40719*FLEN/8, x3, x1, x4) + +inst_13608: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfc00; +op3val:0x0; valaddr_reg:x2; val_offset:40722*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40722*FLEN/8, x3, x1, x4) + +inst_13609: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfc00; +op3val:0x8000; valaddr_reg:x2; val_offset:40725*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40725*FLEN/8, x3, x1, x4) + +inst_13610: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfc00; +op3val:0x1; valaddr_reg:x2; val_offset:40728*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40728*FLEN/8, x3, x1, x4) + +inst_13611: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfc00; +op3val:0x8001; valaddr_reg:x2; val_offset:40731*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40731*FLEN/8, x3, x1, x4) + +inst_13612: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfc00; +op3val:0x2; valaddr_reg:x2; val_offset:40734*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40734*FLEN/8, x3, x1, x4) + +inst_13613: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfc00; +op3val:0x83fe; valaddr_reg:x2; val_offset:40737*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40737*FLEN/8, x3, x1, x4) + +inst_13614: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfc00; +op3val:0x3ff; valaddr_reg:x2; val_offset:40740*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40740*FLEN/8, x3, x1, x4) + +inst_13615: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfc00; +op3val:0x83ff; valaddr_reg:x2; val_offset:40743*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40743*FLEN/8, x3, x1, x4) + +inst_13616: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfc00; +op3val:0x400; valaddr_reg:x2; val_offset:40746*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40746*FLEN/8, x3, x1, x4) + +inst_13617: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfc00; +op3val:0x8400; valaddr_reg:x2; val_offset:40749*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40749*FLEN/8, x3, x1, x4) + +inst_13618: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfc00; +op3val:0x401; valaddr_reg:x2; val_offset:40752*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40752*FLEN/8, x3, x1, x4) + +inst_13619: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfc00; +op3val:0x8455; valaddr_reg:x2; val_offset:40755*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40755*FLEN/8, x3, x1, x4) + +inst_13620: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfc00; +op3val:0x7bff; valaddr_reg:x2; val_offset:40758*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40758*FLEN/8, x3, x1, x4) + +inst_13621: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfc00; +op3val:0xfbff; valaddr_reg:x2; val_offset:40761*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40761*FLEN/8, x3, x1, x4) + +inst_13622: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfc00; +op3val:0x7c00; valaddr_reg:x2; val_offset:40764*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40764*FLEN/8, x3, x1, x4) + +inst_13623: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfc00; +op3val:0xfc00; valaddr_reg:x2; val_offset:40767*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40767*FLEN/8, x3, x1, x4) + +inst_13624: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfc00; +op3val:0x7e00; valaddr_reg:x2; val_offset:40770*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40770*FLEN/8, x3, x1, x4) + +inst_13625: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfc00; +op3val:0xfe00; valaddr_reg:x2; val_offset:40773*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40773*FLEN/8, x3, x1, x4) + +inst_13626: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfc00; +op3val:0x7e01; valaddr_reg:x2; val_offset:40776*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40776*FLEN/8, x3, x1, x4) + +inst_13627: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfc00; +op3val:0xfe55; valaddr_reg:x2; val_offset:40779*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40779*FLEN/8, x3, x1, x4) + +inst_13628: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfc00; +op3val:0x7c01; valaddr_reg:x2; val_offset:40782*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40782*FLEN/8, x3, x1, x4) + +inst_13629: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfc00; +op3val:0xfd55; valaddr_reg:x2; val_offset:40785*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40785*FLEN/8, x3, x1, x4) + +inst_13630: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfc00; +op3val:0x3c00; valaddr_reg:x2; val_offset:40788*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40788*FLEN/8, x3, x1, x4) + +inst_13631: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfc00; +op3val:0xbc00; valaddr_reg:x2; val_offset:40791*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40791*FLEN/8, x3, x1, x4) + +inst_13632: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7e00; +op3val:0x0; valaddr_reg:x2; val_offset:40794*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40794*FLEN/8, x3, x1, x4) + +inst_13633: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7e00; +op3val:0x8000; valaddr_reg:x2; val_offset:40797*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40797*FLEN/8, x3, x1, x4) + +inst_13634: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7e00; +op3val:0x1; valaddr_reg:x2; val_offset:40800*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40800*FLEN/8, x3, x1, x4) + +inst_13635: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7e00; +op3val:0x8001; valaddr_reg:x2; val_offset:40803*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40803*FLEN/8, x3, x1, x4) + +inst_13636: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7e00; +op3val:0x2; valaddr_reg:x2; val_offset:40806*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40806*FLEN/8, x3, x1, x4) + +inst_13637: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7e00; +op3val:0x83fe; valaddr_reg:x2; val_offset:40809*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40809*FLEN/8, x3, x1, x4) + +inst_13638: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7e00; +op3val:0x3ff; valaddr_reg:x2; val_offset:40812*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40812*FLEN/8, x3, x1, x4) + +inst_13639: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7e00; +op3val:0x83ff; valaddr_reg:x2; val_offset:40815*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40815*FLEN/8, x3, x1, x4) + +inst_13640: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7e00; +op3val:0x400; valaddr_reg:x2; val_offset:40818*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40818*FLEN/8, x3, x1, x4) + +inst_13641: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7e00; +op3val:0x8400; valaddr_reg:x2; val_offset:40821*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40821*FLEN/8, x3, x1, x4) + +inst_13642: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7e00; +op3val:0x401; valaddr_reg:x2; val_offset:40824*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40824*FLEN/8, x3, x1, x4) + +inst_13643: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7e00; +op3val:0x8455; valaddr_reg:x2; val_offset:40827*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40827*FLEN/8, x3, x1, x4) + +inst_13644: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7e00; +op3val:0x7bff; valaddr_reg:x2; val_offset:40830*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40830*FLEN/8, x3, x1, x4) + +inst_13645: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7e00; +op3val:0xfbff; valaddr_reg:x2; val_offset:40833*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40833*FLEN/8, x3, x1, x4) + +inst_13646: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7e00; +op3val:0x7c00; valaddr_reg:x2; val_offset:40836*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40836*FLEN/8, x3, x1, x4) + +inst_13647: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7e00; +op3val:0xfc00; valaddr_reg:x2; val_offset:40839*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40839*FLEN/8, x3, x1, x4) + +inst_13648: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7e00; +op3val:0x7e00; valaddr_reg:x2; val_offset:40842*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40842*FLEN/8, x3, x1, x4) + +inst_13649: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7e00; +op3val:0xfe00; valaddr_reg:x2; val_offset:40845*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40845*FLEN/8, x3, x1, x4) + +inst_13650: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7e00; +op3val:0x7e01; valaddr_reg:x2; val_offset:40848*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40848*FLEN/8, x3, x1, x4) + +inst_13651: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7e00; +op3val:0xfe55; valaddr_reg:x2; val_offset:40851*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40851*FLEN/8, x3, x1, x4) + +inst_13652: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7e00; +op3val:0x7c01; valaddr_reg:x2; val_offset:40854*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40854*FLEN/8, x3, x1, x4) + +inst_13653: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7e00; +op3val:0xfd55; valaddr_reg:x2; val_offset:40857*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40857*FLEN/8, x3, x1, x4) + +inst_13654: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7e00; +op3val:0x3c00; valaddr_reg:x2; val_offset:40860*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40860*FLEN/8, x3, x1, x4) + +inst_13655: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7e00; +op3val:0xbc00; valaddr_reg:x2; val_offset:40863*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40863*FLEN/8, x3, x1, x4) + +inst_13656: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfe00; +op3val:0x0; valaddr_reg:x2; val_offset:40866*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40866*FLEN/8, x3, x1, x4) + +inst_13657: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfe00; +op3val:0x8000; valaddr_reg:x2; val_offset:40869*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40869*FLEN/8, x3, x1, x4) + +inst_13658: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfe00; +op3val:0x1; valaddr_reg:x2; val_offset:40872*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40872*FLEN/8, x3, x1, x4) + +inst_13659: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfe00; +op3val:0x8001; valaddr_reg:x2; val_offset:40875*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40875*FLEN/8, x3, x1, x4) + +inst_13660: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfe00; +op3val:0x2; valaddr_reg:x2; val_offset:40878*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40878*FLEN/8, x3, x1, x4) + +inst_13661: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfe00; +op3val:0x83fe; valaddr_reg:x2; val_offset:40881*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40881*FLEN/8, x3, x1, x4) + +inst_13662: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfe00; +op3val:0x3ff; valaddr_reg:x2; val_offset:40884*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40884*FLEN/8, x3, x1, x4) + +inst_13663: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfe00; +op3val:0x83ff; valaddr_reg:x2; val_offset:40887*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40887*FLEN/8, x3, x1, x4) + +inst_13664: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfe00; +op3val:0x400; valaddr_reg:x2; val_offset:40890*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40890*FLEN/8, x3, x1, x4) + +inst_13665: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfe00; +op3val:0x8400; valaddr_reg:x2; val_offset:40893*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40893*FLEN/8, x3, x1, x4) + +inst_13666: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfe00; +op3val:0x401; valaddr_reg:x2; val_offset:40896*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40896*FLEN/8, x3, x1, x4) + +inst_13667: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfe00; +op3val:0x8455; valaddr_reg:x2; val_offset:40899*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40899*FLEN/8, x3, x1, x4) + +inst_13668: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfe00; +op3val:0x7bff; valaddr_reg:x2; val_offset:40902*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40902*FLEN/8, x3, x1, x4) + +inst_13669: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfe00; +op3val:0xfbff; valaddr_reg:x2; val_offset:40905*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40905*FLEN/8, x3, x1, x4) + +inst_13670: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfe00; +op3val:0x7c00; valaddr_reg:x2; val_offset:40908*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40908*FLEN/8, x3, x1, x4) + +inst_13671: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfe00; +op3val:0xfc00; valaddr_reg:x2; val_offset:40911*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40911*FLEN/8, x3, x1, x4) + +inst_13672: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfe00; +op3val:0x7e00; valaddr_reg:x2; val_offset:40914*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40914*FLEN/8, x3, x1, x4) + +inst_13673: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfe00; +op3val:0xfe00; valaddr_reg:x2; val_offset:40917*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40917*FLEN/8, x3, x1, x4) + +inst_13674: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfe00; +op3val:0x7e01; valaddr_reg:x2; val_offset:40920*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40920*FLEN/8, x3, x1, x4) + +inst_13675: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfe00; +op3val:0xfe55; valaddr_reg:x2; val_offset:40923*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40923*FLEN/8, x3, x1, x4) + +inst_13676: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfe00; +op3val:0x7c01; valaddr_reg:x2; val_offset:40926*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40926*FLEN/8, x3, x1, x4) + +inst_13677: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfe00; +op3val:0xfd55; valaddr_reg:x2; val_offset:40929*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40929*FLEN/8, x3, x1, x4) + +inst_13678: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfe00; +op3val:0x3c00; valaddr_reg:x2; val_offset:40932*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40932*FLEN/8, x3, x1, x4) + +inst_13679: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfe00; +op3val:0xbc00; valaddr_reg:x2; val_offset:40935*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40935*FLEN/8, x3, x1, x4) + +inst_13680: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7e01; +op3val:0x0; valaddr_reg:x2; val_offset:40938*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40938*FLEN/8, x3, x1, x4) + +inst_13681: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7e01; +op3val:0x8000; valaddr_reg:x2; val_offset:40941*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40941*FLEN/8, x3, x1, x4) + +inst_13682: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7e01; +op3val:0x1; valaddr_reg:x2; val_offset:40944*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40944*FLEN/8, x3, x1, x4) + +inst_13683: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7e01; +op3val:0x8001; valaddr_reg:x2; val_offset:40947*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40947*FLEN/8, x3, x1, x4) + +inst_13684: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7e01; +op3val:0x2; valaddr_reg:x2; val_offset:40950*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40950*FLEN/8, x3, x1, x4) + +inst_13685: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7e01; +op3val:0x83fe; valaddr_reg:x2; val_offset:40953*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40953*FLEN/8, x3, x1, x4) + +inst_13686: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7e01; +op3val:0x3ff; valaddr_reg:x2; val_offset:40956*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40956*FLEN/8, x3, x1, x4) + +inst_13687: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7e01; +op3val:0x83ff; valaddr_reg:x2; val_offset:40959*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40959*FLEN/8, x3, x1, x4) + +inst_13688: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7e01; +op3val:0x400; valaddr_reg:x2; val_offset:40962*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40962*FLEN/8, x3, x1, x4) + +inst_13689: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7e01; +op3val:0x8400; valaddr_reg:x2; val_offset:40965*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40965*FLEN/8, x3, x1, x4) + +inst_13690: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7e01; +op3val:0x401; valaddr_reg:x2; val_offset:40968*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40968*FLEN/8, x3, x1, x4) + +inst_13691: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7e01; +op3val:0x8455; valaddr_reg:x2; val_offset:40971*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40971*FLEN/8, x3, x1, x4) + +inst_13692: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7e01; +op3val:0x7bff; valaddr_reg:x2; val_offset:40974*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40974*FLEN/8, x3, x1, x4) + +inst_13693: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7e01; +op3val:0xfbff; valaddr_reg:x2; val_offset:40977*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40977*FLEN/8, x3, x1, x4) + +inst_13694: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7e01; +op3val:0x7c00; valaddr_reg:x2; val_offset:40980*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40980*FLEN/8, x3, x1, x4) + +inst_13695: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7e01; +op3val:0xfc00; valaddr_reg:x2; val_offset:40983*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40983*FLEN/8, x3, x1, x4) + +inst_13696: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7e01; +op3val:0x7e00; valaddr_reg:x2; val_offset:40986*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40986*FLEN/8, x3, x1, x4) + +inst_13697: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7e01; +op3val:0xfe00; valaddr_reg:x2; val_offset:40989*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40989*FLEN/8, x3, x1, x4) + +inst_13698: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7e01; +op3val:0x7e01; valaddr_reg:x2; val_offset:40992*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40992*FLEN/8, x3, x1, x4) + +inst_13699: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7e01; +op3val:0xfe55; valaddr_reg:x2; val_offset:40995*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40995*FLEN/8, x3, x1, x4) + +inst_13700: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7e01; +op3val:0x7c01; valaddr_reg:x2; val_offset:40998*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 40998*FLEN/8, x3, x1, x4) + +inst_13701: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7e01; +op3val:0xfd55; valaddr_reg:x2; val_offset:41001*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41001*FLEN/8, x3, x1, x4) + +inst_13702: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7e01; +op3val:0x3c00; valaddr_reg:x2; val_offset:41004*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41004*FLEN/8, x3, x1, x4) + +inst_13703: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7e01; +op3val:0xbc00; valaddr_reg:x2; val_offset:41007*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41007*FLEN/8, x3, x1, x4) + +inst_13704: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfe55; +op3val:0x0; valaddr_reg:x2; val_offset:41010*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41010*FLEN/8, x3, x1, x4) + +inst_13705: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfe55; +op3val:0x8000; valaddr_reg:x2; val_offset:41013*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41013*FLEN/8, x3, x1, x4) + +inst_13706: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfe55; +op3val:0x1; valaddr_reg:x2; val_offset:41016*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41016*FLEN/8, x3, x1, x4) + +inst_13707: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfe55; +op3val:0x8001; valaddr_reg:x2; val_offset:41019*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41019*FLEN/8, x3, x1, x4) + +inst_13708: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfe55; +op3val:0x2; valaddr_reg:x2; val_offset:41022*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41022*FLEN/8, x3, x1, x4) + +inst_13709: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfe55; +op3val:0x83fe; valaddr_reg:x2; val_offset:41025*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41025*FLEN/8, x3, x1, x4) + +inst_13710: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfe55; +op3val:0x3ff; valaddr_reg:x2; val_offset:41028*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41028*FLEN/8, x3, x1, x4) + +inst_13711: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfe55; +op3val:0x83ff; valaddr_reg:x2; val_offset:41031*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41031*FLEN/8, x3, x1, x4) + +inst_13712: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfe55; +op3val:0x400; valaddr_reg:x2; val_offset:41034*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41034*FLEN/8, x3, x1, x4) + +inst_13713: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfe55; +op3val:0x8400; valaddr_reg:x2; val_offset:41037*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41037*FLEN/8, x3, x1, x4) + +inst_13714: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfe55; +op3val:0x401; valaddr_reg:x2; val_offset:41040*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41040*FLEN/8, x3, x1, x4) + +inst_13715: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfe55; +op3val:0x8455; valaddr_reg:x2; val_offset:41043*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41043*FLEN/8, x3, x1, x4) + +inst_13716: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfe55; +op3val:0x7bff; valaddr_reg:x2; val_offset:41046*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41046*FLEN/8, x3, x1, x4) + +inst_13717: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfe55; +op3val:0xfbff; valaddr_reg:x2; val_offset:41049*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41049*FLEN/8, x3, x1, x4) + +inst_13718: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfe55; +op3val:0x7c00; valaddr_reg:x2; val_offset:41052*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41052*FLEN/8, x3, x1, x4) + +inst_13719: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfe55; +op3val:0xfc00; valaddr_reg:x2; val_offset:41055*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41055*FLEN/8, x3, x1, x4) + +inst_13720: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfe55; +op3val:0x7e00; valaddr_reg:x2; val_offset:41058*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41058*FLEN/8, x3, x1, x4) + +inst_13721: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfe55; +op3val:0xfe00; valaddr_reg:x2; val_offset:41061*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41061*FLEN/8, x3, x1, x4) + +inst_13722: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfe55; +op3val:0x7e01; valaddr_reg:x2; val_offset:41064*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41064*FLEN/8, x3, x1, x4) + +inst_13723: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfe55; +op3val:0xfe55; valaddr_reg:x2; val_offset:41067*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41067*FLEN/8, x3, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_108) + +inst_13724: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfe55; +op3val:0x7c01; valaddr_reg:x2; val_offset:41070*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41070*FLEN/8, x3, x1, x4) + +inst_13725: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfe55; +op3val:0xfd55; valaddr_reg:x2; val_offset:41073*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41073*FLEN/8, x3, x1, x4) + +inst_13726: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfe55; +op3val:0x3c00; valaddr_reg:x2; val_offset:41076*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41076*FLEN/8, x3, x1, x4) + +inst_13727: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfe55; +op3val:0xbc00; valaddr_reg:x2; val_offset:41079*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41079*FLEN/8, x3, x1, x4) + +inst_13728: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7c01; +op3val:0x0; valaddr_reg:x2; val_offset:41082*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41082*FLEN/8, x3, x1, x4) + +inst_13729: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7c01; +op3val:0x8000; valaddr_reg:x2; val_offset:41085*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41085*FLEN/8, x3, x1, x4) + +inst_13730: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7c01; +op3val:0x1; valaddr_reg:x2; val_offset:41088*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41088*FLEN/8, x3, x1, x4) + +inst_13731: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7c01; +op3val:0x8001; valaddr_reg:x2; val_offset:41091*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41091*FLEN/8, x3, x1, x4) + +inst_13732: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7c01; +op3val:0x2; valaddr_reg:x2; val_offset:41094*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41094*FLEN/8, x3, x1, x4) + +inst_13733: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7c01; +op3val:0x83fe; valaddr_reg:x2; val_offset:41097*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41097*FLEN/8, x3, x1, x4) + +inst_13734: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7c01; +op3val:0x3ff; valaddr_reg:x2; val_offset:41100*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41100*FLEN/8, x3, x1, x4) + +inst_13735: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7c01; +op3val:0x83ff; valaddr_reg:x2; val_offset:41103*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41103*FLEN/8, x3, x1, x4) + +inst_13736: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7c01; +op3val:0x400; valaddr_reg:x2; val_offset:41106*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41106*FLEN/8, x3, x1, x4) + +inst_13737: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7c01; +op3val:0x8400; valaddr_reg:x2; val_offset:41109*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41109*FLEN/8, x3, x1, x4) + +inst_13738: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7c01; +op3val:0x401; valaddr_reg:x2; val_offset:41112*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41112*FLEN/8, x3, x1, x4) + +inst_13739: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7c01; +op3val:0x8455; valaddr_reg:x2; val_offset:41115*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41115*FLEN/8, x3, x1, x4) + +inst_13740: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7c01; +op3val:0x7bff; valaddr_reg:x2; val_offset:41118*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41118*FLEN/8, x3, x1, x4) + +inst_13741: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7c01; +op3val:0xfbff; valaddr_reg:x2; val_offset:41121*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41121*FLEN/8, x3, x1, x4) + +inst_13742: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7c01; +op3val:0x7c00; valaddr_reg:x2; val_offset:41124*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41124*FLEN/8, x3, x1, x4) + +inst_13743: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7c01; +op3val:0xfc00; valaddr_reg:x2; val_offset:41127*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41127*FLEN/8, x3, x1, x4) + +inst_13744: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7c01; +op3val:0x7e00; valaddr_reg:x2; val_offset:41130*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41130*FLEN/8, x3, x1, x4) + +inst_13745: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7c01; +op3val:0xfe00; valaddr_reg:x2; val_offset:41133*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41133*FLEN/8, x3, x1, x4) + +inst_13746: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7c01; +op3val:0x7e01; valaddr_reg:x2; val_offset:41136*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41136*FLEN/8, x3, x1, x4) + +inst_13747: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7c01; +op3val:0xfe55; valaddr_reg:x2; val_offset:41139*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41139*FLEN/8, x3, x1, x4) + +inst_13748: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7c01; +op3val:0x7c01; valaddr_reg:x2; val_offset:41142*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41142*FLEN/8, x3, x1, x4) + +inst_13749: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7c01; +op3val:0xfd55; valaddr_reg:x2; val_offset:41145*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41145*FLEN/8, x3, x1, x4) + +inst_13750: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7c01; +op3val:0x3c00; valaddr_reg:x2; val_offset:41148*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41148*FLEN/8, x3, x1, x4) + +inst_13751: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x7c01; +op3val:0xbc00; valaddr_reg:x2; val_offset:41151*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41151*FLEN/8, x3, x1, x4) + +inst_13752: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfd55; +op3val:0x0; valaddr_reg:x2; val_offset:41154*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41154*FLEN/8, x3, x1, x4) + +inst_13753: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfd55; +op3val:0x8000; valaddr_reg:x2; val_offset:41157*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41157*FLEN/8, x3, x1, x4) + +inst_13754: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfd55; +op3val:0x1; valaddr_reg:x2; val_offset:41160*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41160*FLEN/8, x3, x1, x4) + +inst_13755: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfd55; +op3val:0x8001; valaddr_reg:x2; val_offset:41163*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41163*FLEN/8, x3, x1, x4) + +inst_13756: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfd55; +op3val:0x2; valaddr_reg:x2; val_offset:41166*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41166*FLEN/8, x3, x1, x4) + +inst_13757: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfd55; +op3val:0x83fe; valaddr_reg:x2; val_offset:41169*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41169*FLEN/8, x3, x1, x4) + +inst_13758: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfd55; +op3val:0x3ff; valaddr_reg:x2; val_offset:41172*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41172*FLEN/8, x3, x1, x4) + +inst_13759: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfd55; +op3val:0x83ff; valaddr_reg:x2; val_offset:41175*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41175*FLEN/8, x3, x1, x4) + +inst_13760: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfd55; +op3val:0x400; valaddr_reg:x2; val_offset:41178*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41178*FLEN/8, x3, x1, x4) + +inst_13761: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfd55; +op3val:0x8400; valaddr_reg:x2; val_offset:41181*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41181*FLEN/8, x3, x1, x4) + +inst_13762: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfd55; +op3val:0x401; valaddr_reg:x2; val_offset:41184*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41184*FLEN/8, x3, x1, x4) + +inst_13763: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfd55; +op3val:0x8455; valaddr_reg:x2; val_offset:41187*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41187*FLEN/8, x3, x1, x4) + +inst_13764: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfd55; +op3val:0x7bff; valaddr_reg:x2; val_offset:41190*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41190*FLEN/8, x3, x1, x4) + +inst_13765: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfd55; +op3val:0xfbff; valaddr_reg:x2; val_offset:41193*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41193*FLEN/8, x3, x1, x4) + +inst_13766: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfd55; +op3val:0x7c00; valaddr_reg:x2; val_offset:41196*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41196*FLEN/8, x3, x1, x4) + +inst_13767: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfd55; +op3val:0xfc00; valaddr_reg:x2; val_offset:41199*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41199*FLEN/8, x3, x1, x4) + +inst_13768: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfd55; +op3val:0x7e00; valaddr_reg:x2; val_offset:41202*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41202*FLEN/8, x3, x1, x4) + +inst_13769: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfd55; +op3val:0xfe00; valaddr_reg:x2; val_offset:41205*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41205*FLEN/8, x3, x1, x4) + +inst_13770: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfd55; +op3val:0x7e01; valaddr_reg:x2; val_offset:41208*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41208*FLEN/8, x3, x1, x4) + +inst_13771: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfd55; +op3val:0xfe55; valaddr_reg:x2; val_offset:41211*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41211*FLEN/8, x3, x1, x4) + +inst_13772: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfd55; +op3val:0x7c01; valaddr_reg:x2; val_offset:41214*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41214*FLEN/8, x3, x1, x4) + +inst_13773: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfd55; +op3val:0xfd55; valaddr_reg:x2; val_offset:41217*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41217*FLEN/8, x3, x1, x4) + +inst_13774: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfd55; +op3val:0x3c00; valaddr_reg:x2; val_offset:41220*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41220*FLEN/8, x3, x1, x4) + +inst_13775: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xfd55; +op3val:0xbc00; valaddr_reg:x2; val_offset:41223*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41223*FLEN/8, x3, x1, x4) + +inst_13776: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x3c00; +op3val:0x0; valaddr_reg:x2; val_offset:41226*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41226*FLEN/8, x3, x1, x4) + +inst_13777: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x3c00; +op3val:0x8000; valaddr_reg:x2; val_offset:41229*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41229*FLEN/8, x3, x1, x4) + +inst_13778: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x3c00; +op3val:0x1; valaddr_reg:x2; val_offset:41232*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41232*FLEN/8, x3, x1, x4) + +inst_13779: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x3c00; +op3val:0x8001; valaddr_reg:x2; val_offset:41235*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41235*FLEN/8, x3, x1, x4) + +inst_13780: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x3c00; +op3val:0x2; valaddr_reg:x2; val_offset:41238*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41238*FLEN/8, x3, x1, x4) + +inst_13781: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x3c00; +op3val:0x83fe; valaddr_reg:x2; val_offset:41241*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41241*FLEN/8, x3, x1, x4) + +inst_13782: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x3c00; +op3val:0x3ff; valaddr_reg:x2; val_offset:41244*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41244*FLEN/8, x3, x1, x4) + +inst_13783: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x3c00; +op3val:0x83ff; valaddr_reg:x2; val_offset:41247*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41247*FLEN/8, x3, x1, x4) + +inst_13784: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x3c00; +op3val:0x400; valaddr_reg:x2; val_offset:41250*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41250*FLEN/8, x3, x1, x4) + +inst_13785: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x3c00; +op3val:0x8400; valaddr_reg:x2; val_offset:41253*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41253*FLEN/8, x3, x1, x4) + +inst_13786: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x3c00; +op3val:0x401; valaddr_reg:x2; val_offset:41256*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41256*FLEN/8, x3, x1, x4) + +inst_13787: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x3c00; +op3val:0x8455; valaddr_reg:x2; val_offset:41259*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41259*FLEN/8, x3, x1, x4) + +inst_13788: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x3c00; +op3val:0x7bff; valaddr_reg:x2; val_offset:41262*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41262*FLEN/8, x3, x1, x4) + +inst_13789: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x3c00; +op3val:0xfbff; valaddr_reg:x2; val_offset:41265*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41265*FLEN/8, x3, x1, x4) + +inst_13790: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x3c00; +op3val:0x7c00; valaddr_reg:x2; val_offset:41268*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41268*FLEN/8, x3, x1, x4) + +inst_13791: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x3c00; +op3val:0xfc00; valaddr_reg:x2; val_offset:41271*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41271*FLEN/8, x3, x1, x4) + +inst_13792: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x3c00; +op3val:0x7e00; valaddr_reg:x2; val_offset:41274*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41274*FLEN/8, x3, x1, x4) + +inst_13793: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x3c00; +op3val:0xfe00; valaddr_reg:x2; val_offset:41277*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41277*FLEN/8, x3, x1, x4) + +inst_13794: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x3c00; +op3val:0x7e01; valaddr_reg:x2; val_offset:41280*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41280*FLEN/8, x3, x1, x4) + +inst_13795: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x3c00; +op3val:0xfe55; valaddr_reg:x2; val_offset:41283*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41283*FLEN/8, x3, x1, x4) + +inst_13796: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x3c00; +op3val:0x7c01; valaddr_reg:x2; val_offset:41286*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41286*FLEN/8, x3, x1, x4) + +inst_13797: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x3c00; +op3val:0xfd55; valaddr_reg:x2; val_offset:41289*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41289*FLEN/8, x3, x1, x4) + +inst_13798: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x3c00; +op3val:0x3c00; valaddr_reg:x2; val_offset:41292*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41292*FLEN/8, x3, x1, x4) + +inst_13799: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0x3c00; +op3val:0xbc00; valaddr_reg:x2; val_offset:41295*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41295*FLEN/8, x3, x1, x4) + +inst_13800: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xbc00; +op3val:0x0; valaddr_reg:x2; val_offset:41298*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41298*FLEN/8, x3, x1, x4) + +inst_13801: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xbc00; +op3val:0x8000; valaddr_reg:x2; val_offset:41301*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41301*FLEN/8, x3, x1, x4) + +inst_13802: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xbc00; +op3val:0x1; valaddr_reg:x2; val_offset:41304*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41304*FLEN/8, x3, x1, x4) + +inst_13803: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xbc00; +op3val:0x8001; valaddr_reg:x2; val_offset:41307*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41307*FLEN/8, x3, x1, x4) + +inst_13804: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xbc00; +op3val:0x2; valaddr_reg:x2; val_offset:41310*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41310*FLEN/8, x3, x1, x4) + +inst_13805: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xbc00; +op3val:0x83fe; valaddr_reg:x2; val_offset:41313*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41313*FLEN/8, x3, x1, x4) + +inst_13806: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xbc00; +op3val:0x3ff; valaddr_reg:x2; val_offset:41316*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41316*FLEN/8, x3, x1, x4) + +inst_13807: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xbc00; +op3val:0x83ff; valaddr_reg:x2; val_offset:41319*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41319*FLEN/8, x3, x1, x4) + +inst_13808: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xbc00; +op3val:0x400; valaddr_reg:x2; val_offset:41322*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41322*FLEN/8, x3, x1, x4) + +inst_13809: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xbc00; +op3val:0x8400; valaddr_reg:x2; val_offset:41325*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41325*FLEN/8, x3, x1, x4) + +inst_13810: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xbc00; +op3val:0x401; valaddr_reg:x2; val_offset:41328*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41328*FLEN/8, x3, x1, x4) + +inst_13811: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xbc00; +op3val:0x8455; valaddr_reg:x2; val_offset:41331*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41331*FLEN/8, x3, x1, x4) + +inst_13812: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xbc00; +op3val:0x7bff; valaddr_reg:x2; val_offset:41334*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41334*FLEN/8, x3, x1, x4) + +inst_13813: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xbc00; +op3val:0xfbff; valaddr_reg:x2; val_offset:41337*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41337*FLEN/8, x3, x1, x4) + +inst_13814: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xbc00; +op3val:0x7c00; valaddr_reg:x2; val_offset:41340*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41340*FLEN/8, x3, x1, x4) + +inst_13815: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xbc00; +op3val:0xfc00; valaddr_reg:x2; val_offset:41343*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41343*FLEN/8, x3, x1, x4) + +inst_13816: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xbc00; +op3val:0x7e00; valaddr_reg:x2; val_offset:41346*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41346*FLEN/8, x3, x1, x4) + +inst_13817: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xbc00; +op3val:0xfe00; valaddr_reg:x2; val_offset:41349*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41349*FLEN/8, x3, x1, x4) + +inst_13818: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xbc00; +op3val:0x7e01; valaddr_reg:x2; val_offset:41352*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41352*FLEN/8, x3, x1, x4) + +inst_13819: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xbc00; +op3val:0xfe55; valaddr_reg:x2; val_offset:41355*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41355*FLEN/8, x3, x1, x4) + +inst_13820: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xbc00; +op3val:0x7c01; valaddr_reg:x2; val_offset:41358*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41358*FLEN/8, x3, x1, x4) + +inst_13821: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xbc00; +op3val:0xfd55; valaddr_reg:x2; val_offset:41361*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41361*FLEN/8, x3, x1, x4) + +inst_13822: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xbc00; +op3val:0x3c00; valaddr_reg:x2; val_offset:41364*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41364*FLEN/8, x3, x1, x4) + +inst_13823: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbc00; op2val:0xbc00; +op3val:0xbc00; valaddr_reg:x2; val_offset:41367*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41367*FLEN/8, x3, x1, x4) + +inst_13824: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x0; +op3val:0x8000; valaddr_reg:x2; val_offset:41370*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41370*FLEN/8, x3, x1, x4) + +inst_13825: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x0; +op3val:0x8001; valaddr_reg:x2; val_offset:41373*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41373*FLEN/8, x3, x1, x4) + +inst_13826: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x0; +op3val:0x83ff; valaddr_reg:x2; val_offset:41376*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41376*FLEN/8, x3, x1, x4) + +inst_13827: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x0; +op3val:0x400; valaddr_reg:x2; val_offset:41379*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41379*FLEN/8, x3, x1, x4) + +inst_13828: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x0; +op3val:0x8400; valaddr_reg:x2; val_offset:41382*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41382*FLEN/8, x3, x1, x4) + +inst_13829: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x0; +op3val:0x401; valaddr_reg:x2; val_offset:41385*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41385*FLEN/8, x3, x1, x4) + +inst_13830: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x0; +op3val:0x8455; valaddr_reg:x2; val_offset:41388*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41388*FLEN/8, x3, x1, x4) + +inst_13831: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x0; +op3val:0x7e00; valaddr_reg:x2; val_offset:41391*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41391*FLEN/8, x3, x1, x4) + +inst_13832: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x0; +op3val:0x7e01; valaddr_reg:x2; val_offset:41394*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41394*FLEN/8, x3, x1, x4) + +inst_13833: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x0; +op3val:0xbc00; valaddr_reg:x2; val_offset:41397*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41397*FLEN/8, x3, x1, x4) + +inst_13834: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8000; +op3val:0x2; valaddr_reg:x2; val_offset:41400*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41400*FLEN/8, x3, x1, x4) + +inst_13835: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x8000; +op3val:0x8400; valaddr_reg:x2; val_offset:41403*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 41403*FLEN/8, x3, x1, x4) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(1,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(2,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(1023,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(33877,16,FLEN) +test_dataset_1: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31744,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32256,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31745,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(15360,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(48128,16,FLEN) +test_dataset_2: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(2,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1023,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1024,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(33792,16,FLEN) +test_dataset_3: +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1,16,FLEN) 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+NAN_BOXED(64511,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33792,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x5_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x5_1: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_0: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_2: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_3: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_4: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_5: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_6: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_7: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_8: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_9: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_10: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_11: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_12: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_13: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_14: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_15: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_16: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_17: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_18: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_19: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_20: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_21: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_22: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_23: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_24: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_25: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_26: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_27: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_28: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_29: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_30: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_31: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_32: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_33: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_34: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_35: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_36: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_37: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_38: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_39: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_40: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_41: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_42: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_43: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_44: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_45: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_46: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_47: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_48: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_49: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_50: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_51: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_52: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_53: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_54: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_55: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_56: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_57: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_58: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_59: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_60: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_61: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_62: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_63: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_64: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_65: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_66: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_67: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_68: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_69: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_70: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_71: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_72: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_73: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_74: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_75: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_76: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_77: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_78: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_79: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_80: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_81: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_82: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_83: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_84: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_85: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_86: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_87: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_88: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_89: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_90: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_91: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_92: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_93: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_94: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_95: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_96: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_97: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_98: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_99: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_100: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_101: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_102: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_103: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_104: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_105: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_106: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_107: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_108: + .fill 224*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fmadd_b14-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fmadd_b14-01.S new file mode 100644 index 000000000..6019eaed5 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fmadd_b14-01.S @@ -0,0 +1,424 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 04:10:09 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fmadd.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fmadd.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fmadd_b14 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fmadd_b14) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x1,test_dataset_0) +RVTEST_SIGBASE(x9,signature_x9_1) + +inst_0: +// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==x10, rs2==x10, rs3==x1, rd==x16, +/* opcode: fmadd.h ; op1:x10; op2:x10; op3:x1; dest:x16; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x1; val_offset:0*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x16, x10, x10, x1, dyn, 0, 0, x1, 0*FLEN/8, x12, x9, x11) + +inst_1: +// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==x5, rs2==x27, rs3==x5, rd==x4, +/* opcode: fmadd.h ; op1:x5; op2:x27; op3:x5; dest:x4; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x1; val_offset:3*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x4, x5, x27, x5, dyn, 0, 0, x1, 3*FLEN/8, x12, x9, x11) + +inst_2: +// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==x2, rs2==x13, rs3==x21, rd==x2, +/* opcode: fmadd.h ; op1:x2; op2:x13; op3:x21; dest:x2; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x1; val_offset:6*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x2, x2, x13, x21, dyn, 0, 0, x1, 6*FLEN/8, x12, x9, x11) + +inst_3: +// rs1 == rs2 == rs3 != rd, rs1==x14, rs2==x14, rs3==x14, rd==x7, +/* opcode: fmadd.h ; op1:x14; op2:x14; op3:x14; dest:x7; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x1; val_offset:9*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x7, x14, x14, x14, dyn, 0, 0, x1, 9*FLEN/8, x12, x9, x11) + +inst_4: +// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==x26, rs2==x5, rs3==x30, rd==x30, +/* opcode: fmadd.h ; op1:x26; op2:x5; op3:x30; dest:x30; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x1; val_offset:12*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x30, x26, x5, x30, dyn, 0, 0, x1, 12*FLEN/8, x12, x9, x11) + +inst_5: +// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==x31, rs2==x21, rs3==x29, rd==x21, +/* opcode: fmadd.h ; op1:x31; op2:x21; op3:x29; dest:x21; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x1; val_offset:15*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x21, x31, x21, x29, dyn, 0, 0, x1, 15*FLEN/8, x12, x9, x11) + +inst_6: +// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==x13, rs2==x24, rs3==x8, rd==x25, +/* opcode: fmadd.h ; op1:x13; op2:x24; op3:x8; dest:x25; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x1; val_offset:18*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x25, x13, x24, x8, dyn, 0, 0, x1, 18*FLEN/8, x12, x9, x11) + +inst_7: +// rd == rs2 == rs3 != rs1, rs1==x16, rs2==x28, rs3==x28, rd==x28, +/* opcode: fmadd.h ; op1:x16; op2:x28; op3:x28; dest:x28; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x1; val_offset:21*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x28, x16, x28, x28, dyn, 0, 0, x1, 21*FLEN/8, x12, x9, x11) + +inst_8: +// rs1 == rd == rs3 != rs2, rs1==x6, rs2==x20, rs3==x6, rd==x6, +/* opcode: fmadd.h ; op1:x6; op2:x20; op3:x6; dest:x6; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x1; val_offset:24*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x6, x6, x20, x6, dyn, 0, 0, x1, 24*FLEN/8, x12, x9, x11) + +inst_9: +// rs1 == rs2 == rs3 == rd, rs1==x3, rs2==x3, rs3==x3, rd==x3, +/* opcode: fmadd.h ; op1:x3; op2:x3; op3:x3; dest:x3; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x1; val_offset:27*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x3, x3, x3, x3, dyn, 0, 0, x1, 27*FLEN/8, x12, x9, x11) + +inst_10: +// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==x8, rs2==x15, rs3==x15, rd==x17, +/* opcode: fmadd.h ; op1:x8; op2:x15; op3:x15; dest:x17; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x1; val_offset:30*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x17, x8, x15, x15, dyn, 0, 0, x1, 30*FLEN/8, x12, x9, x11) +RVTEST_VALBASEUPD(x2,test_dataset_1) + +inst_11: +// rs1 == rs2 == rd != rs3, rs1==x12, rs2==x12, rs3==x27, rd==x12, +/* opcode: fmadd.h ; op1:x12; op2:x12; op3:x27; dest:x12; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x2; val_offset:0*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x12, x12, x12, x27, dyn, 0, 0, x2, 0*FLEN/8, x8, x9, x11) + +inst_12: +// rs1==x27, rs2==x6, rs3==x31, rd==x10, +/* opcode: fmadd.h ; op1:x27; op2:x6; op3:x31; dest:x10; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x2; val_offset:3*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x10, x27, x6, x31, dyn, 0, 0, x2, 3*FLEN/8, x8, x9, x11) + +inst_13: +// rs1==x1, rs2==x22, rs3==x0, rd==x19, +/* opcode: fmadd.h ; op1:x1; op2:x22; op3:x0; dest:x19; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x2; val_offset:6*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x19, x1, x22, x0, dyn, 0, 0, x2, 6*FLEN/8, x8, x9, x11) +RVTEST_SIGBASE(x3,signature_x3_0) + +inst_14: +// rs1==x25, rs2==x26, rs3==x23, rd==x15, +/* opcode: fmadd.h ; op1:x25; op2:x26; op3:x23; dest:x15; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x2; val_offset:9*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x15, x25, x26, x23, dyn, 0, 0, x2, 9*FLEN/8, x8, x3, x4) + +inst_15: +// rs1==x22, rs2==x1, rs3==x12, rd==x20, +/* opcode: fmadd.h ; op1:x22; op2:x1; op3:x12; dest:x20; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x2; val_offset:12*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x20, x22, x1, x12, dyn, 0, 0, x2, 12*FLEN/8, x8, x3, x4) + +inst_16: +// rs1==x29, rs2==x0, rs3==x9, rd==x11, +/* opcode: fmadd.h ; op1:x29; op2:x0; op3:x9; dest:x11; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x2; val_offset:15*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x11, x29, x0, x9, dyn, 0, 0, x2, 15*FLEN/8, x8, x3, x4) + +inst_17: +// rs1==x28, rs2==x7, rs3==x13, rd==x1, +/* opcode: fmadd.h ; op1:x28; op2:x7; op3:x13; dest:x1; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x2; val_offset:18*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x1, x28, x7, x13, dyn, 0, 0, x2, 18*FLEN/8, x8, x3, x4) + +inst_18: +// rs1==x0, rs2==x18, rs3==x2, rd==x5, +/* opcode: fmadd.h ; op1:x0; op2:x18; op3:x2; dest:x5; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x2; val_offset:21*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x5, x0, x18, x2, dyn, 0, 0, x2, 21*FLEN/8, x8, x3, x4) + +inst_19: +// rs1==x20, rs2==x23, rs3==x4, rd==x29, +/* opcode: fmadd.h ; op1:x20; op2:x23; op3:x4; dest:x29; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x2; val_offset:24*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x29, x20, x23, x4, dyn, 0, 0, x2, 24*FLEN/8, x8, x3, x4) + +inst_20: +// rs1==x9, rs2==x16, rs3==x25, rd==x13, +/* opcode: fmadd.h ; op1:x9; op2:x16; op3:x25; dest:x13; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x2; val_offset:27*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x13, x9, x16, x25, dyn, 0, 0, x2, 27*FLEN/8, x8, x3, x4) + +inst_21: +// rs1==x18, rs2==x19, rs3==x10, rd==x14, +/* opcode: fmadd.h ; op1:x18; op2:x19; op3:x10; dest:x14; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x2; val_offset:30*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x14, x18, x19, x10, dyn, 0, 0, x2, 30*FLEN/8, x8, x3, x4) +RVTEST_VALBASEUPD(x5,test_dataset_2) + +inst_22: +// rs1==x7, rs2==x29, rs3==x20, rd==x8, +/* opcode: fmadd.h ; op1:x7; op2:x29; op3:x20; dest:x8; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x5; val_offset:0*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x8, x7, x29, x20, dyn, 0, 0, x5, 0*FLEN/8, x6, x3, x4) + +inst_23: +// rs1==x19, rs2==x30, rs3==x17, rd==x24, +/* opcode: fmadd.h ; op1:x19; op2:x30; op3:x17; dest:x24; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x5; val_offset:3*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x24, x19, x30, x17, dyn, 0, 0, x5, 3*FLEN/8, x6, x3, x4) + +inst_24: +// rs1==x24, rs2==x25, rs3==x16, rd==x22, +/* opcode: fmadd.h ; op1:x24; op2:x25; op3:x16; dest:x22; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x5; val_offset:6*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x22, x24, x25, x16, dyn, 0, 0, x5, 6*FLEN/8, x6, x3, x4) + +inst_25: +// rs1==x17, rs2==x9, rs3==x18, rd==x23, +/* opcode: fmadd.h ; op1:x17; op2:x9; op3:x18; dest:x23; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x5; val_offset:9*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x23, x17, x9, x18, dyn, 0, 0, x5, 9*FLEN/8, x6, x3, x4) + +inst_26: +// rs1==x21, rs2==x2, rs3==x7, rd==x31, +/* opcode: fmadd.h ; op1:x21; op2:x2; op3:x7; dest:x31; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x5; val_offset:12*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x21, x2, x7, dyn, 0, 0, x5, 12*FLEN/8, x6, x3, x4) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_27: +// rs1==x30, rs2==x8, rs3==x11, rd==x9, +/* opcode: fmadd.h ; op1:x30; op2:x8; op3:x11; dest:x9; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x5; val_offset:15*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x9, x30, x8, x11, dyn, 0, 0, x5, 15*FLEN/8, x6, x1, x2) + +inst_28: +// rs1==x11, rs2==x4, rs3==x26, rd==x18, +/* opcode: fmadd.h ; op1:x11; op2:x4; op3:x26; dest:x18; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x5; val_offset:18*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x18, x11, x4, x26, dyn, 0, 0, x5, 18*FLEN/8, x6, x1, x2) + +inst_29: +// rs1==x4, rs2==x31, rs3==x22, rd==x0, +/* opcode: fmadd.h ; op1:x4; op2:x31; op3:x22; dest:x0; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x5; val_offset:21*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x0, x4, x31, x22, dyn, 0, 0, x5, 21*FLEN/8, x6, x1, x2) + +inst_30: +// rs1==x15, rs2==x17, rs3==x19, rd==x26, +/* opcode: fmadd.h ; op1:x15; op2:x17; op3:x19; dest:x26; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x5; val_offset:24*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x26, x15, x17, x19, dyn, 0, 0, x5, 24*FLEN/8, x6, x1, x2) + +inst_31: +// rs1==x23, rs2==x11, rs3==x24, rd==x27, +/* opcode: fmadd.h ; op1:x23; op2:x11; op3:x24; dest:x27; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x5; val_offset:27*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x27, x23, x11, x24, dyn, 0, 0, x5, 27*FLEN/8, x6, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +test_dataset_1: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +test_dataset_2: +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x9_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x9_1: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x3_0: + .fill 26*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_0: + .fill 10*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fmadd_b16-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fmadd_b16-01.S new file mode 100644 index 000000000..b5e6b770c --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fmadd_b16-01.S @@ -0,0 +1,2221 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 04:10:09 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fmadd.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fmadd.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fmadd_b16 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fmadd_b16) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==x6, rs2==x6, rs3==x13, rd==x0,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x6; op2:x6; op3:x13; dest:x0; op1val:0x7ac0; op2val:0x7ac0; +op3val:0xfbff; valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn; +testreg:x14; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x0, x6, x6, x13, dyn, 0, 0, x3, 0*FLEN/8, x12, x1, x14) + +inst_1: +// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==x19, rs2==x2, rs3==x19, rd==x11,fs1 == 0 and fe1 == 0x1d and fm1 == 0x024 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x016 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x19; op2:x2; op3:x19; dest:x11; op1val:0x7424; op2val:0x7816; +op3val:0x7424; valaddr_reg:x3; val_offset:3*FLEN/8; rmval:dyn; +testreg:x14; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x11, x19, x2, x19, dyn, 0, 0, x3, 3*FLEN/8, x12, x1, x14) + +inst_2: +// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==x30, rs2==x9, rs3==x20, rd==x30,fs1 == 0 and fe1 == 0x1e and fm1 == 0x244 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0d9 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x9; op3:x20; dest:x30; op1val:0x7a44; op2val:0x74d9; +op3val:0xfbff; valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn; +testreg:x14; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x30, x30, x9, x20, dyn, 0, 0, x3, 6*FLEN/8, x12, x1, x14) + +inst_3: +// rs1 == rs2 == rs3 != rd, rs1==x21, rs2==x21, rs3==x21, rd==x16,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0aa and fs2 == 0 and fe2 == 0x1e and fm2 == 0x342 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x21; op2:x21; op3:x21; dest:x16; op1val:0x78aa; op2val:0x78aa; +op3val:0x78aa; valaddr_reg:x3; val_offset:9*FLEN/8; rmval:dyn; +testreg:x14; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x16, x21, x21, x21, dyn, 0, 0, x3, 9*FLEN/8, x12, x1, x14) + +inst_4: +// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==x9, rs2==x23, rs3==x7, rd==x7,fs1 == 0 and fe1 == 0x1d and fm1 == 0x081 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20b and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x9; op2:x23; op3:x7; dest:x7; op1val:0x7481; op2val:0x7a0b; +op3val:0xfbff; valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn; +testreg:x14; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x7, x9, x23, x7, dyn, 0, 0, x3, 12*FLEN/8, x12, x1, x14) + +inst_5: +// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==x20, rs2==x27, rs3==x25, rd==x27,fs1 == 0 and fe1 == 0x1d and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x346 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x20; op2:x27; op3:x25; dest:x27; op1val:0x7401; op2val:0x7b46; +op3val:0xfbff; valaddr_reg:x3; val_offset:15*FLEN/8; rmval:dyn; +testreg:x14; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x27, x20, x27, x25, dyn, 0, 0, x3, 15*FLEN/8, x12, x1, x14) + +inst_6: +// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==x23, rs2==x17, rs3==x22, rd==x4,fs1 == 0 and fe1 == 0x1e and fm1 == 0x27a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x336 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x23; op2:x17; op3:x22; dest:x4; op1val:0x7a7a; op2val:0x7b36; +op3val:0xfbff; valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn; +testreg:x14; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x4, x23, x17, x22, dyn, 0, 0, x3, 18*FLEN/8, x12, x1, x14) + +inst_7: +// rd == rs2 == rs3 != rs1, rs1==x5, rs2==x8, rs3==x8, rd==x8,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x32f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x5; op2:x8; op3:x8; dest:x8; op1val:0x79d5; op2val:0x7b2f; +op3val:0x7b2f; valaddr_reg:x3; val_offset:21*FLEN/8; rmval:dyn; +testreg:x14; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x8, x5, x8, x8, dyn, 0, 0, x3, 21*FLEN/8, x12, x1, x14) + +inst_8: +// rs1 == rd == rs3 != rs2, rs1==x10, rs2==x29, rs3==x10, rd==x10,fs1 == 0 and fe1 == 0x1d and fm1 == 0x38c and fs2 == 0 and fe2 == 0x1b and fm2 == 0x271 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x10; op2:x29; op3:x10; dest:x10; op1val:0x778c; op2val:0x6e71; +op3val:0x778c; valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn; +testreg:x14; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x10, x10, x29, x10, dyn, 0, 0, x3, 24*FLEN/8, x12, x1, x14) + +inst_9: +// rs1 == rs2 == rs3 == rd, rs1==x31, rs2==x31, rs3==x31, rd==x31,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x34c and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x31; op2:x31; op3:x31; dest:x31; op1val:0x78e2; op2val:0x78e2; +op3val:0x78e2; valaddr_reg:x3; val_offset:27*FLEN/8; rmval:dyn; +testreg:x14; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x31, x31, x31, dyn, 0, 0, x3, 27*FLEN/8, x12, x1, x14) + +inst_10: +// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==x25, rs2==x4, rs3==x4, rd==x24,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2eb and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x25; op2:x4; op3:x4; dest:x24; op1val:0x77a0; op2val:0x7aeb; +op3val:0x7aeb; valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn; +testreg:x14; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x24, x25, x4, x4, dyn, 0, 0, x3, 30*FLEN/8, x12, x1, x14) + +inst_11: +// rs1 == rs2 == rd != rs3, rs1==x18, rs2==x18, rs3==x17, rd==x18,fs1 == 0 and fe1 == 0x1e and fm1 == 0x26f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x063 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x18; op2:x18; op3:x17; dest:x18; op1val:0x7a6f; op2val:0x7a6f; +op3val:0xfbff; valaddr_reg:x3; val_offset:33*FLEN/8; rmval:dyn; +testreg:x14; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x18, x18, x18, x17, dyn, 0, 0, x3, 33*FLEN/8, x12, x1, x14) +RVTEST_VALBASEUPD(x7,test_dataset_1) + +inst_12: +// rs1==x16, rs2==x11, rs3==x27, rd==x2,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c1 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x260 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x16; op2:x11; op3:x27; dest:x2; op1val:0x79c1; op2val:0x7660; +op3val:0xfbff; valaddr_reg:x7; val_offset:0*FLEN/8; rmval:dyn; +testreg:x14; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x2, x16, x11, x27, dyn, 0, 0, x7, 0*FLEN/8, x18, x1, x14) + +inst_13: +// rs1==x4, rs2==x10, rs3==x5, rd==x6,fs1 == 0 and fe1 == 0x1e and fm1 == 0x157 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x0ad and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x4; op2:x10; op3:x5; dest:x6; op1val:0x7957; op2val:0x54ad; +op3val:0xfbff; valaddr_reg:x7; val_offset:3*FLEN/8; rmval:dyn; +testreg:x14; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x6, x4, x10, x5, dyn, 0, 0, x7, 3*FLEN/8, x18, x1, x14) + +inst_14: +// rs1==x12, rs2==x13, rs3==x0, rd==x3,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3cd and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x12; op2:x13; op3:x0; dest:x3; op1val:0x7aef; op2val:0x73cd; +op3val:0x0; valaddr_reg:x7; val_offset:6*FLEN/8; rmval:dyn; +testreg:x14; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x3, x12, x13, x0, dyn, 0, 0, x7, 6*FLEN/8, x18, x1, x14) +RVTEST_SIGBASE(x4,signature_x4_0) + +inst_15: +// rs1==x1, rs2==x22, rs3==x2, rd==x26,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f5 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x21c and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x1; op2:x22; op3:x2; dest:x26; op1val:0x7af5; op2val:0x721c; +op3val:0xfbff; valaddr_reg:x7; val_offset:9*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x26, x1, x22, x2, dyn, 0, 0, x7, 9*FLEN/8, x18, x4, x6) + +inst_16: +// rs1==x11, rs2==x30, rs3==x14, rd==x29,fs1 == 0 and fe1 == 0x1c and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3bc and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x11; op2:x30; op3:x14; dest:x29; op1val:0x73a1; op2val:0x7bbc; +op3val:0xfbff; valaddr_reg:x7; val_offset:12*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x29, x11, x30, x14, dyn, 0, 0, x7, 12*FLEN/8, x18, x4, x6) + +inst_17: +// rs1==x15, rs2==x26, rs3==x6, rd==x5,fs1 == 0 and fe1 == 0x1d and fm1 == 0x329 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x125 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x15; op2:x26; op3:x6; dest:x5; op1val:0x7729; op2val:0x6d25; +op3val:0xfbff; valaddr_reg:x7; val_offset:15*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x5, x15, x26, x6, dyn, 0, 0, x7, 15*FLEN/8, x18, x4, x6) + +inst_18: +// rs1==x17, rs2==x1, rs3==x18, rd==x23,fs1 == 0 and fe1 == 0x1e and fm1 == 0x00f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x375 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x17; op2:x1; op3:x18; dest:x23; op1val:0x780f; op2val:0x7b75; +op3val:0xfbff; valaddr_reg:x7; val_offset:18*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x23, x17, x1, x18, dyn, 0, 0, x7, 18*FLEN/8, x18, x4, x6) + +inst_19: +// rs1==x27, rs2==x24, rs3==x29, rd==x19,fs1 == 0 and fe1 == 0x1e and fm1 == 0x068 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1a6 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x27; op2:x24; op3:x29; dest:x19; op1val:0x7868; op2val:0x79a6; +op3val:0xfbff; valaddr_reg:x7; val_offset:21*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x19, x27, x24, x29, dyn, 0, 0, x7, 21*FLEN/8, x18, x4, x6) + +inst_20: +// rs1==x14, rs2==x12, rs3==x28, rd==x15,fs1 == 0 and fe1 == 0x1e and fm1 == 0x283 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x051 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x14; op2:x12; op3:x28; dest:x15; op1val:0x7a83; op2val:0x7851; +op3val:0xfbff; valaddr_reg:x7; val_offset:24*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x15, x14, x12, x28, dyn, 0, 0, x7, 24*FLEN/8, x18, x4, x6) + +inst_21: +// rs1==x8, rs2==x3, rs3==x9, rd==x13,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0b2 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x8; op2:x3; op3:x9; dest:x13; op1val:0x78d2; op2val:0x78b2; +op3val:0xfbff; valaddr_reg:x7; val_offset:27*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x13, x8, x3, x9, dyn, 0, 0, x7, 27*FLEN/8, x18, x4, x6) + +inst_22: +// rs1==x28, rs2==x5, rs3==x12, rd==x9,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c4 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x227 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x28; op2:x5; op3:x12; dest:x9; op1val:0x78c4; op2val:0x7627; +op3val:0xfbff; valaddr_reg:x7; val_offset:30*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x9, x28, x5, x12, dyn, 0, 0, x7, 30*FLEN/8, x18, x4, x6) +RVTEST_VALBASEUPD(x5,test_dataset_2) + +inst_23: +// rs1==x0, rs2==x28, rs3==x26, rd==x1,fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a4 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x20e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x0; op2:x28; op3:x26; dest:x1; op1val:0x0; op2val:0x720e; +op3val:0xfbff; valaddr_reg:x5; val_offset:0*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x1, x0, x28, x26, dyn, 0, 0, x5, 0*FLEN/8, x8, x4, x6) + +inst_24: +// rs1==x7, rs2==x15, rs3==x1, rd==x21,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x140 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x7; op2:x15; op3:x1; dest:x21; op1val:0x78e6; op2val:0x7940; +op3val:0xfbff; valaddr_reg:x5; val_offset:3*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x21, x7, x15, x1, dyn, 0, 0, x5, 3*FLEN/8, x8, x4, x6) + +inst_25: +// rs1==x24, rs2==x0, rs3==x23, rd==x25,fs1 == 0 and fe1 == 0x1b and fm1 == 0x1be and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x24; op2:x0; op3:x23; dest:x25; op1val:0x6dbe; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:6*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x25, x24, x0, x23, dyn, 0, 0, x5, 6*FLEN/8, x8, x4, x6) + +inst_26: +// rs1==x2, rs2==x14, rs3==x15, rd==x22,fs1 == 0 and fe1 == 0x1e and fm1 == 0x362 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2bc and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x2; op2:x14; op3:x15; dest:x22; op1val:0x7b62; op2val:0x7abc; +op3val:0xfbff; valaddr_reg:x5; val_offset:9*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x22, x2, x14, x15, dyn, 0, 0, x5, 9*FLEN/8, x8, x4, x6) + +inst_27: +// rs1==x29, rs2==x7, rs3==x30, rd==x28,fs1 == 0 and fe1 == 0x1e and fm1 == 0x361 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x052 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x29; op2:x7; op3:x30; dest:x28; op1val:0x7b61; op2val:0x7852; +op3val:0xfbff; valaddr_reg:x5; val_offset:12*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x28, x29, x7, x30, dyn, 0, 0, x5, 12*FLEN/8, x8, x4, x2) + +inst_28: +// rs1==x26, rs2==x20, rs3==x3, rd==x14,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a3 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x068 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x26; op2:x20; op3:x3; dest:x14; op1val:0x79a3; op2val:0x7468; +op3val:0xfbff; valaddr_reg:x5; val_offset:15*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x14, x26, x20, x3, dyn, 0, 0, x5, 15*FLEN/8, x8, x4, x2) +RVTEST_SIGBASE(x1,signature_x1_2) + +inst_29: +// rs1==x22, rs2==x25, rs3==x11, rd==x20,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ca and fs2 == 0 and fe2 == 0x1e and fm2 == 0x328 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x22; op2:x25; op3:x11; dest:x20; op1val:0x7aca; op2val:0x7b28; +op3val:0xfbff; valaddr_reg:x5; val_offset:18*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x20, x22, x25, x11, dyn, 0, 0, x5, 18*FLEN/8, x8, x1, x2) + +inst_30: +// rs1==x3, rs2==x19, rs3==x24, rd==x12,fs1 == 0 and fe1 == 0x1e and fm1 == 0x398 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0a2 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x3; op2:x19; op3:x24; dest:x12; op1val:0x7b98; op2val:0x78a2; +op3val:0xfbff; valaddr_reg:x5; val_offset:21*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x12, x3, x19, x24, dyn, 0, 0, x5, 21*FLEN/8, x8, x1, x2) + +inst_31: +// rs1==x13,fs1 == 0 and fe1 == 0x1e and fm1 == 0x147 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3f7 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x13; op2:x25; op3:x16; dest:x30; op1val:0x7947; op2val:0x7bf7; +op3val:0xfbff; valaddr_reg:x5; val_offset:24*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x30, x13, x25, x16, dyn, 0, 0, x5, 24*FLEN/8, x8, x1, x2) + +inst_32: +// rs2==x16,fs1 == 0 and fe1 == 0x1e and fm1 == 0x257 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x144 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x13; op2:x16; op3:x15; dest:x14; op1val:0x7a57; op2val:0x6d44; +op3val:0xfbff; valaddr_reg:x5; val_offset:27*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x14, x13, x16, x15, dyn, 0, 0, x5, 27*FLEN/8, x8, x1, x2) + +inst_33: +// rd==x17,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3c7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x109 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x10; op2:x26; op3:x4; dest:x17; op1val:0x77c7; op2val:0x7909; +op3val:0xfbff; valaddr_reg:x5; val_offset:30*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x17, x10, x26, x4, dyn, 0, 0, x5, 30*FLEN/8, x8, x1, x2) + +inst_34: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3c5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1d9 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73c5; op2val:0x79d9; +op3val:0xfbff; valaddr_reg:x5; val_offset:33*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 33*FLEN/8, x8, x1, x2) +RVTEST_VALBASEUPD(x3,test_dataset_3) + +inst_35: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x30d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x25a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x730d; op2val:0x7a5a; +op3val:0xfbff; valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_36: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x286 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x26f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a86; op2val:0x6e6f; +op3val:0xfbff; valaddr_reg:x3; val_offset:3*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_37: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x194 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x1c9 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7994; op2val:0x69c9; +op3val:0xfbff; valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_38: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x346 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x045 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b46; op2val:0x7845; +op3val:0xfbff; valaddr_reg:x3; val_offset:9*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_39: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x2d4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x113 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x66d4; op2val:0x7913; +op3val:0xfbff; valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_40: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09a and fs2 == 0 and fe2 == 0x1d and fm2 == 0x241 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x789a; op2val:0x7641; +op3val:0xfbff; valaddr_reg:x3; val_offset:15*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_41: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d7 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x0a7 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd7; op2val:0x68a7; +op3val:0xfbff; valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_42: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3af and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1ea and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7baf; op2val:0x71ea; +op3val:0xfbff; valaddr_reg:x3; val_offset:21*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_43: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2bc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x267 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72bc; op2val:0x7a67; +op3val:0xfbff; valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_44: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x1d4 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2ce and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x65d4; op2val:0x76ce; +op3val:0xfbff; valaddr_reg:x3; val_offset:27*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_45: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x028 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x310 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7428; op2val:0x7310; +op3val:0xfbff; valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_46: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x19a and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1c4 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x759a; op2val:0x71c4; +op3val:0xfbff; valaddr_reg:x3; val_offset:33*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 33*FLEN/8, x4, x1, x2) + +inst_47: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x109 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x274 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6909; op2val:0x6e74; +op3val:0xfbff; valaddr_reg:x3; val_offset:36*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 36*FLEN/8, x4, x1, x2) + +inst_48: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x260 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1bb and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7260; op2val:0x75bb; +op3val:0xfbff; valaddr_reg:x3; val_offset:39*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 39*FLEN/8, x4, x1, x2) + +inst_49: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x358 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ab4; op2val:0x7b58; +op3val:0xfbff; valaddr_reg:x3; val_offset:42*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 42*FLEN/8, x4, x1, x2) + +inst_50: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x160 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ba and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7960; op2val:0x7bba; +op3val:0xfbff; valaddr_reg:x3; val_offset:45*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 45*FLEN/8, x4, x1, x2) + +inst_51: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x168 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c2 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7968; op2val:0x7ac2; +op3val:0xfbff; valaddr_reg:x3; val_offset:48*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 48*FLEN/8, x4, x1, x2) + +inst_52: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0c5 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7402; op2val:0x78c5; +op3val:0xfbff; valaddr_reg:x3; val_offset:51*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 51*FLEN/8, x4, x1, x2) + +inst_53: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x197 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x38a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7197; op2val:0x778a; +op3val:0xfbff; valaddr_reg:x3; val_offset:54*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 54*FLEN/8, x4, x1, x2) + +inst_54: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x08c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x011 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x788c; op2val:0x7811; +op3val:0xfbff; valaddr_reg:x3; val_offset:57*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 57*FLEN/8, x4, x1, x2) + +inst_55: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1b6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b2 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75b6; op2val:0x7ab2; +op3val:0xfbff; valaddr_reg:x3; val_offset:60*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 60*FLEN/8, x4, x1, x2) + +inst_56: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x07b and fs2 == 0 and fe2 == 0x18 and fm2 == 0x25d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x787b; op2val:0x625d; +op3val:0xfbff; valaddr_reg:x3; val_offset:63*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 63*FLEN/8, x4, x1, x2) + +inst_57: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x15f and fs2 == 0 and fe2 == 0x1a and fm2 == 0x1d8 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x755f; op2val:0x69d8; +op3val:0xfbff; valaddr_reg:x3; val_offset:66*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 66*FLEN/8, x4, x1, x2) + +inst_58: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3ae and fs2 == 0 and fe2 == 0x1e and fm2 == 0x39f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73ae; op2val:0x7b9f; +op3val:0xfbff; valaddr_reg:x3; val_offset:69*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 69*FLEN/8, x4, x1, x2) + +inst_59: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x09a and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1be and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x749a; op2val:0x75be; +op3val:0xfbff; valaddr_reg:x3; val_offset:72*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 72*FLEN/8, x4, x1, x2) + +inst_60: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x111 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0f7 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7911; op2val:0x78f7; +op3val:0xfbff; valaddr_reg:x3; val_offset:75*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 75*FLEN/8, x4, x1, x2) + +inst_61: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x234 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2a0 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7634; op2val:0x76a0; +op3val:0xfbff; valaddr_reg:x3; val_offset:78*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 78*FLEN/8, x4, x1, x2) + +inst_62: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x23d and fs2 == 0 and fe2 == 0x1c and fm2 == 0x226 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x563d; op2val:0x7226; +op3val:0xfbff; valaddr_reg:x3; val_offset:81*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 81*FLEN/8, x4, x1, x2) + +inst_63: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3a8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x118 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73a8; op2val:0x7918; +op3val:0xfbff; valaddr_reg:x3; val_offset:84*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 84*FLEN/8, x4, x1, x2) + +inst_64: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x08b and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aff; op2val:0x788b; +op3val:0xfbff; valaddr_reg:x3; val_offset:87*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 87*FLEN/8, x4, x1, x2) + +inst_65: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x19c and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x766e; op2val:0x799c; +op3val:0xfbff; valaddr_reg:x3; val_offset:90*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 90*FLEN/8, x4, x1, x2) + +inst_66: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x14b and fs2 == 0 and fe2 == 0x1a and fm2 == 0x1fc and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x794b; op2val:0x69fc; +op3val:0xfbff; valaddr_reg:x3; val_offset:93*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 93*FLEN/8, x4, x1, x2) + +inst_67: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x10b and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7425; op2val:0x710b; +op3val:0xfbff; valaddr_reg:x3; val_offset:96*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 96*FLEN/8, x4, x1, x2) + +inst_68: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ca and fs2 == 0 and fe2 == 0x1e and fm2 == 0x07d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77ca; op2val:0x787d; +op3val:0xfbff; valaddr_reg:x3; val_offset:99*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 99*FLEN/8, x4, x1, x2) + +inst_69: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x311 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3e8 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b11; op2val:0x77e8; +op3val:0xfbff; valaddr_reg:x3; val_offset:102*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 102*FLEN/8, x4, x1, x2) + +inst_70: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x377 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x278 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7777; op2val:0x7a78; +op3val:0xfbff; valaddr_reg:x3; val_offset:105*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 105*FLEN/8, x4, x1, x2) + +inst_71: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x27f and fs2 == 0 and fe2 == 0x1c and fm2 == 0x203 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a7f; op2val:0x7203; +op3val:0xfbff; valaddr_reg:x3; val_offset:108*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 108*FLEN/8, x4, x1, x2) + +inst_72: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x10f and fs2 == 0 and fe2 == 0x1b and fm2 == 0x156 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x790f; op2val:0x6d56; +op3val:0xfbff; valaddr_reg:x3; val_offset:111*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 111*FLEN/8, x4, x1, x2) + +inst_73: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e4 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x26d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7be4; op2val:0x766d; +op3val:0xfbff; valaddr_reg:x3; val_offset:114*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 114*FLEN/8, x4, x1, x2) + +inst_74: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x10e and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2d4 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x750e; op2val:0x72d4; +op3val:0xfbff; valaddr_reg:x3; val_offset:117*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 117*FLEN/8, x4, x1, x2) + +inst_75: +// fs1 == 0 and fe1 == 0x16 and fm1 == 0x0d3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x294 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x58d3; op2val:0x7a94; +op3val:0xfbff; valaddr_reg:x3; val_offset:120*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 120*FLEN/8, x4, x1, x2) + +inst_76: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x241 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x39b and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e41; op2val:0x6f9b; +op3val:0xfbff; valaddr_reg:x3; val_offset:123*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 123*FLEN/8, x4, x1, x2) + +inst_77: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2fc and fs2 == 0 and fe2 == 0x1d and fm2 == 0x07a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7afc; op2val:0x747a; +op3val:0xfbff; valaddr_reg:x3; val_offset:126*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 126*FLEN/8, x4, x1, x2) + +inst_78: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x268 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2d4 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e68; op2val:0x7ad4; +op3val:0xfbff; valaddr_reg:x3; val_offset:129*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 129*FLEN/8, x4, x1, x2) + +inst_79: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x134 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x064 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d34; op2val:0x7464; +op3val:0xfbff; valaddr_reg:x3; val_offset:132*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 132*FLEN/8, x4, x1, x2) + +inst_80: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2e3 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a55; op2val:0x7ae3; +op3val:0xfbff; valaddr_reg:x3; val_offset:135*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 135*FLEN/8, x4, x1, x2) + +inst_81: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x134 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x782a; op2val:0x7934; +op3val:0xfbff; valaddr_reg:x3; val_offset:138*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 138*FLEN/8, x4, x1, x2) + +inst_82: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f8 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x073 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7af8; op2val:0x7473; +op3val:0xfbff; valaddr_reg:x3; val_offset:141*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 141*FLEN/8, x4, x1, x2) + +inst_83: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x133 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x172 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6933; op2val:0x7972; +op3val:0xfbff; valaddr_reg:x3; val_offset:144*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 144*FLEN/8, x4, x1, x2) + +inst_84: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x391 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x380 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b91; op2val:0x7b80; +op3val:0xfbff; valaddr_reg:x3; val_offset:147*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 147*FLEN/8, x4, x1, x2) + +inst_85: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x15f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1fd and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x695f; op2val:0x79fd; +op3val:0xfbff; valaddr_reg:x3; val_offset:150*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 150*FLEN/8, x4, x1, x2) + +inst_86: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x13d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1b2 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x793d; op2val:0x79b2; +op3val:0xfbff; valaddr_reg:x3; val_offset:153*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 153*FLEN/8, x4, x1, x2) + +inst_87: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x11e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1f4 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x791e; op2val:0x75f4; +op3val:0xfbff; valaddr_reg:x3; val_offset:156*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 156*FLEN/8, x4, x1, x2) + +inst_88: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2a5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0b1 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72a5; op2val:0x78b1; +op3val:0xfbff; valaddr_reg:x3; val_offset:159*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 159*FLEN/8, x4, x1, x2) + +inst_89: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0d4 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x154 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70d4; op2val:0x7554; +op3val:0xfbff; valaddr_reg:x3; val_offset:162*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 162*FLEN/8, x4, x1, x2) + +inst_90: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1be and fs2 == 0 and fe2 == 0x1d and fm2 == 0x168 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79be; op2val:0x7568; +op3val:0xfbff; valaddr_reg:x3; val_offset:165*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 165*FLEN/8, x4, x1, x2) + +inst_91: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x145 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x13d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6945; op2val:0x713d; +op3val:0xfbff; valaddr_reg:x3; val_offset:168*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 168*FLEN/8, x4, x1, x2) + +inst_92: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a1 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x250 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74a1; op2val:0x7650; +op3val:0xfbff; valaddr_reg:x3; val_offset:171*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 171*FLEN/8, x4, x1, x2) + +inst_93: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0b1 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3a5 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74b1; op2val:0x77a5; +op3val:0xfbff; valaddr_reg:x3; val_offset:174*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 174*FLEN/8, x4, x1, x2) + +inst_94: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x22c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1be and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6a2c; op2val:0x71be; +op3val:0xfbff; valaddr_reg:x3; val_offset:177*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 177*FLEN/8, x4, x1, x2) + +inst_95: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x088 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x272 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c88; op2val:0x7672; +op3val:0xfbff; valaddr_reg:x3; val_offset:180*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 180*FLEN/8, x4, x1, x2) + +inst_96: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a1 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x25b and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76a1; op2val:0x6e5b; +op3val:0xfbff; valaddr_reg:x3; val_offset:183*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 183*FLEN/8, x4, x1, x2) + +inst_97: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x394 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b9 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7794; op2val:0x7ab9; +op3val:0xfbff; valaddr_reg:x3; val_offset:186*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 186*FLEN/8, x4, x1, x2) + +inst_98: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x17e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3a9 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x757e; op2val:0x77a9; +op3val:0xfbff; valaddr_reg:x3; val_offset:189*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 189*FLEN/8, x4, x1, x2) + +inst_99: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2d2 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0d3 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76d2; op2val:0x74d3; +op3val:0xfbff; valaddr_reg:x3; val_offset:192*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 192*FLEN/8, x4, x1, x2) + +inst_100: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x326 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x35a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b26; op2val:0x7b5a; +op3val:0xfbff; valaddr_reg:x3; val_offset:195*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 195*FLEN/8, x4, x1, x2) + +inst_101: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ca and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7601; op2val:0x7bca; +op3val:0xfbff; valaddr_reg:x3; val_offset:198*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 198*FLEN/8, x4, x1, x2) + +inst_102: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x036 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x16a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c36; op2val:0x6d6a; +op3val:0xfbff; valaddr_reg:x3; val_offset:201*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 201*FLEN/8, x4, x1, x2) + +inst_103: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3d2 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x004 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6bd2; op2val:0x6004; +op3val:0xfbff; valaddr_reg:x3; val_offset:204*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 204*FLEN/8, x4, x1, x2) + +inst_104: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x026 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x32c and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7826; op2val:0x772c; +op3val:0xfbff; valaddr_reg:x3; val_offset:207*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 207*FLEN/8, x4, x1, x2) + +inst_105: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ad and fs2 == 0 and fe2 == 0x1e and fm2 == 0x16e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78ad; op2val:0x796e; +op3val:0xfbff; valaddr_reg:x3; val_offset:210*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 210*FLEN/8, x4, x1, x2) + +inst_106: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1e3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3e7 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75e3; op2val:0x7be7; +op3val:0xfbff; valaddr_reg:x3; val_offset:213*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 213*FLEN/8, x4, x1, x2) + +inst_107: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x236 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2e5 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a36; op2val:0x76e5; +op3val:0xfbff; valaddr_reg:x3; val_offset:216*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 216*FLEN/8, x4, x1, x2) + +inst_108: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x015 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2e7 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c15; op2val:0x7ae7; +op3val:0xfbff; valaddr_reg:x3; val_offset:219*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 219*FLEN/8, x4, x1, x2) + +inst_109: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x338 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x338 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b38; op2val:0x7738; +op3val:0xfbff; valaddr_reg:x3; val_offset:222*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 222*FLEN/8, x4, x1, x2) + +inst_110: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x39b and fs2 == 0 and fe2 == 0x1d and fm2 == 0x25d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f9b; op2val:0x765d; +op3val:0xfbff; valaddr_reg:x3; val_offset:225*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 225*FLEN/8, x4, x1, x2) + +inst_111: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x162 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x394 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6962; op2val:0x7b94; +op3val:0xfbff; valaddr_reg:x3; val_offset:228*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 228*FLEN/8, x4, x1, x2) + +inst_112: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0ae and fs2 == 0 and fe2 == 0x1c and fm2 == 0x254 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70ae; op2val:0x7254; +op3val:0xfbff; valaddr_reg:x3; val_offset:231*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 231*FLEN/8, x4, x1, x2) + +inst_113: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x05e and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0d7 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x785e; op2val:0x70d7; +op3val:0xfbff; valaddr_reg:x3; val_offset:234*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 234*FLEN/8, x4, x1, x2) + +inst_114: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3dc and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0bf and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bdc; op2val:0x70bf; +op3val:0xfbff; valaddr_reg:x3; val_offset:237*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 237*FLEN/8, x4, x1, x2) + +inst_115: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x16f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x304 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x796f; op2val:0x7b04; +op3val:0xfbff; valaddr_reg:x3; val_offset:240*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 240*FLEN/8, x4, x1, x2) + +inst_116: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x355 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x128 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b55; op2val:0x7528; +op3val:0xfbff; valaddr_reg:x3; val_offset:243*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 243*FLEN/8, x4, x1, x2) + +inst_117: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3f9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x15b and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77f9; op2val:0x795b; +op3val:0xfbff; valaddr_reg:x3; val_offset:246*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 246*FLEN/8, x4, x1, x2) + +inst_118: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e0 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e0; op2val:0x72ff; +op3val:0xfbff; valaddr_reg:x3; val_offset:249*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 249*FLEN/8, x4, x1, x2) + +inst_119: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x330 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bb2; op2val:0x7b30; +op3val:0xfbff; valaddr_reg:x3; val_offset:252*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 252*FLEN/8, x4, x1, x2) + +inst_120: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x089 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0be and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6889; op2val:0x70be; +op3val:0xfbff; valaddr_reg:x3; val_offset:255*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 255*FLEN/8, x4, x1, x2) + +inst_121: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x245 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2bc and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a45; op2val:0x7abc; +op3val:0xfbff; valaddr_reg:x3; val_offset:258*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 258*FLEN/8, x4, x1, x2) + +inst_122: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1be and fs2 == 0 and fe2 == 0x1e and fm2 == 0x274 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79be; op2val:0x7a74; +op3val:0xfbff; valaddr_reg:x3; val_offset:261*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 261*FLEN/8, x4, x1, x2) + +inst_123: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x16a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2f2 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d6a; op2val:0x7af2; +op3val:0xfbff; valaddr_reg:x3; val_offset:264*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 264*FLEN/8, x4, x1, x2) + +inst_124: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x333 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x132 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7333; op2val:0x6932; +op3val:0xfbff; valaddr_reg:x3; val_offset:267*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 267*FLEN/8, x4, x1, x2) + +inst_125: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2bf and fs2 == 0 and fe2 == 0x1d and fm2 == 0x149 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7abf; op2val:0x7549; +op3val:0xfbff; valaddr_reg:x3; val_offset:270*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 270*FLEN/8, x4, x1, x2) + +inst_126: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0c2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x13f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70c2; op2val:0x793f; +op3val:0xfbff; valaddr_reg:x3; val_offset:273*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 273*FLEN/8, x4, x1, x2) + +inst_127: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x009 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x334 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7809; op2val:0x7b34; +op3val:0xfbff; valaddr_reg:x3; val_offset:276*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 276*FLEN/8, x4, x1, x2) + +inst_128: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x096 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x16d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7896; op2val:0x796d; +op3val:0xfbff; valaddr_reg:x3; val_offset:279*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 279*FLEN/8, x4, x1, x2) + +inst_129: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3eb and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a0f; op2val:0x7beb; +op3val:0xfbff; valaddr_reg:x3; val_offset:282*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 282*FLEN/8, x4, x1, x2) + +inst_130: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x33e and fs2 == 0 and fe2 == 0x1c and fm2 == 0x297 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b3e; op2val:0x7297; +op3val:0xfbff; valaddr_reg:x3; val_offset:285*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 285*FLEN/8, x4, x1, x2) + +inst_131: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x29a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78c9; op2val:0x7a9a; +op3val:0xfbff; valaddr_reg:x3; val_offset:288*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 288*FLEN/8, x4, x1, x2) + +inst_132: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x253 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x236 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a53; op2val:0x7636; +op3val:0xfbff; valaddr_reg:x3; val_offset:291*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 291*FLEN/8, x4, x1, x2) + +inst_133: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ce and fs2 == 0 and fe2 == 0x1e and fm2 == 0x261 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ace; op2val:0x7a61; +op3val:0xfbff; valaddr_reg:x3; val_offset:294*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 294*FLEN/8, x4, x1, x2) + +inst_134: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x3e2 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1d1 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4be2; op2val:0x71d1; +op3val:0xfbff; valaddr_reg:x3; val_offset:297*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 297*FLEN/8, x4, x1, x2) + +inst_135: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x011 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x032 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7411; op2val:0x6c32; +op3val:0xfbff; valaddr_reg:x3; val_offset:300*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 300*FLEN/8, x4, x1, x2) + +inst_136: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x38a and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0d7 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b8a; op2val:0x74d7; +op3val:0xfbff; valaddr_reg:x3; val_offset:303*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 303*FLEN/8, x4, x1, x2) + +inst_137: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x27a and fs2 == 0 and fe2 == 0x1a and fm2 == 0x3f7 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a7a; op2val:0x6bf7; +op3val:0xfbff; valaddr_reg:x3; val_offset:306*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 306*FLEN/8, x4, x1, x2) + +inst_138: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x012 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x097 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7012; op2val:0x7497; +op3val:0xfbff; valaddr_reg:x3; val_offset:309*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 309*FLEN/8, x4, x1, x2) + +inst_139: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x31a and fs2 == 0 and fe2 == 0x1a and fm2 == 0x098 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6b1a; op2val:0x6898; +op3val:0xfbff; valaddr_reg:x3; val_offset:312*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 312*FLEN/8, x4, x1, x2) + +inst_140: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3dd and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2e7 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77dd; op2val:0x7ae7; +op3val:0xfbff; valaddr_reg:x3; val_offset:315*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 315*FLEN/8, x4, x1, x2) + +inst_141: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x162 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0d7 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7962; op2val:0x70d7; +op3val:0xfbff; valaddr_reg:x3; val_offset:318*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 318*FLEN/8, x4, x1, x2) + +inst_142: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x293 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0e4 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7693; op2val:0x78e4; +op3val:0xfbff; valaddr_reg:x3; val_offset:321*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 321*FLEN/8, x4, x1, x2) + +inst_143: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x204 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x387 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6a04; op2val:0x7787; +op3val:0xfbff; valaddr_reg:x3; val_offset:324*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 324*FLEN/8, x4, x1, x2) + +inst_144: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x027 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0ef and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6827; op2val:0x78ef; +op3val:0xfbff; valaddr_reg:x3; val_offset:327*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 327*FLEN/8, x4, x1, x2) + +inst_145: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2bc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x064 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ebc; op2val:0x7864; +op3val:0xfbff; valaddr_reg:x3; val_offset:330*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 330*FLEN/8, x4, x1, x2) + +inst_146: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x221 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x235 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7621; op2val:0x7a35; +op3val:0xfbff; valaddr_reg:x3; val_offset:333*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 333*FLEN/8, x4, x1, x2) + +inst_147: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0e0 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b0b; op2val:0x78e0; +op3val:0xfbff; valaddr_reg:x3; val_offset:336*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 336*FLEN/8, x4, x1, x2) + +inst_148: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x10e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x167 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x790e; op2val:0x7567; +op3val:0xfbff; valaddr_reg:x3; val_offset:339*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 339*FLEN/8, x4, x1, x2) + +inst_149: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x175 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0f9 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7975; op2val:0x78f9; +op3val:0xfbff; valaddr_reg:x3; val_offset:342*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 342*FLEN/8, x4, x1, x2) + +inst_150: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x010 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x34a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7010; op2val:0x7b4a; +op3val:0xfbff; valaddr_reg:x3; val_offset:345*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 345*FLEN/8, x4, x1, x2) + +inst_151: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x354 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2fa and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b54; op2val:0x7afa; +op3val:0xfbff; valaddr_reg:x3; val_offset:348*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 348*FLEN/8, x4, x1, x2) + +inst_152: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x27a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x026 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a7a; op2val:0x7826; +op3val:0xfbff; valaddr_reg:x3; val_offset:351*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 351*FLEN/8, x4, x1, x2) + +inst_153: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x20c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x240 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x720c; op2val:0x7a40; +op3val:0xfbff; valaddr_reg:x3; val_offset:354*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 354*FLEN/8, x4, x1, x2) + +inst_154: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20c and fs2 == 0 and fe2 == 0x1d and fm2 == 0x348 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a0c; op2val:0x7748; +op3val:0xfbff; valaddr_reg:x3; val_offset:357*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 357*FLEN/8, x4, x1, x2) + +inst_155: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0d1 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x1b6 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6cd1; op2val:0x69b6; +op3val:0xfbff; valaddr_reg:x3; val_offset:360*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 360*FLEN/8, x4, x1, x2) + +inst_156: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3c6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x334 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77c6; op2val:0x7b34; +op3val:0xfbff; valaddr_reg:x3; val_offset:363*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 363*FLEN/8, x4, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_3) + +inst_157: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x154 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x092 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7954; op2val:0x7892; +op3val:0xfbff; valaddr_reg:x3; val_offset:366*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 366*FLEN/8, x4, x1, x2) + +inst_158: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1fa and fs2 == 0 and fe2 == 0x1e and fm2 == 0x28d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dfa; op2val:0x7a8d; +op3val:0xfbff; valaddr_reg:x3; val_offset:369*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 369*FLEN/8, x4, x1, x2) + +inst_159: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x23b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x195 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a3b; op2val:0x7995; +op3val:0xfbff; valaddr_reg:x3; val_offset:372*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 372*FLEN/8, x4, x1, x2) + +inst_160: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0e1 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x341 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74e1; op2val:0x6f41; +op3val:0xfbff; valaddr_reg:x3; val_offset:375*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 375*FLEN/8, x4, x1, x2) + +inst_161: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x086 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x361 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7886; op2val:0x7b61; +op3val:0xfbff; valaddr_reg:x3; val_offset:378*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 378*FLEN/8, x4, x1, x2) + +inst_162: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a5 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x258 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76a5; op2val:0x6e58; +op3val:0xfbff; valaddr_reg:x3; val_offset:381*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 381*FLEN/8, x4, x1, x2) + +inst_163: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1df and fs2 == 0 and fe2 == 0x19 and fm2 == 0x3db and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79df; op2val:0x67db; +op3val:0xfbff; valaddr_reg:x3; val_offset:384*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 384*FLEN/8, x4, x1, x2) + +inst_164: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x17d and fs2 == 0 and fe2 == 0x19 and fm2 == 0x3b5 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x797d; op2val:0x67b5; +op3val:0xfbff; valaddr_reg:x3; val_offset:387*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 387*FLEN/8, x4, x1, x2) + +inst_165: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1c7 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bb1; op2val:0x79c7; +op3val:0xfbff; valaddr_reg:x3; val_offset:390*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 390*FLEN/8, x4, x1, x2) + +inst_166: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x07f and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1be and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c7f; op2val:0x75be; +op3val:0xfbff; valaddr_reg:x3; val_offset:393*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 393*FLEN/8, x4, x1, x2) + +inst_167: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x190 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x119 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7590; op2val:0x6119; +op3val:0xfbff; valaddr_reg:x3; val_offset:396*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 396*FLEN/8, x4, x1, x2) + +inst_168: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28c and fs2 == 0 and fe2 == 0x1b and fm2 == 0x082 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8c; op2val:0x6c82; +op3val:0xfbff; valaddr_reg:x3; val_offset:399*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 399*FLEN/8, x4, x1, x2) + +inst_169: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2a6 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x28c and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72a6; op2val:0x728c; +op3val:0xfbff; valaddr_reg:x3; val_offset:402*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 402*FLEN/8, x4, x1, x2) + +inst_170: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x380 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3e1 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b80; op2val:0x6fe1; +op3val:0xfbff; valaddr_reg:x3; val_offset:405*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 405*FLEN/8, x4, x1, x2) + +inst_171: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1e7 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x24e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75e7; op2val:0x664e; +op3val:0xfbff; valaddr_reg:x3; val_offset:408*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 408*FLEN/8, x4, x1, x2) + +inst_172: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2de and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1fb and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ade; op2val:0x71fb; +op3val:0xfbff; valaddr_reg:x3; val_offset:411*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 411*FLEN/8, x4, x1, x2) + +inst_173: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x182 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ab and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7582; op2val:0x7bab; +op3val:0xfbff; valaddr_reg:x3; val_offset:414*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 414*FLEN/8, x4, x1, x2) + +inst_174: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ba and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1cb and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bba; op2val:0x75cb; +op3val:0xfbff; valaddr_reg:x3; val_offset:417*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 417*FLEN/8, x4, x1, x2) + +inst_175: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ae and fs2 == 0 and fe2 == 0x1e and fm2 == 0x37e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74ae; op2val:0x7b7e; +op3val:0xfbff; valaddr_reg:x3; val_offset:420*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 420*FLEN/8, x4, x1, x2) + +inst_176: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x115 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1e2 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7915; op2val:0x71e2; +op3val:0xfbff; valaddr_reg:x3; val_offset:423*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 423*FLEN/8, x4, x1, x2) + +inst_177: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x28f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0a4 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e8f; op2val:0x78a4; +op3val:0xfbff; valaddr_reg:x3; val_offset:426*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 426*FLEN/8, x4, x1, x2) + +inst_178: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x38f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b2d; op2val:0x7b8f; +op3val:0xfbff; valaddr_reg:x3; val_offset:429*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 429*FLEN/8, x4, x1, x2) + +inst_179: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x10d and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3c4 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x750d; op2val:0x73c4; +op3val:0xfbff; valaddr_reg:x3; val_offset:432*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 432*FLEN/8, x4, x1, x2) + +inst_180: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a7 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2b6 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74a7; op2val:0x76b6; +op3val:0xfbff; valaddr_reg:x3; val_offset:435*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 435*FLEN/8, x4, x1, x2) + +inst_181: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x03a and fs2 == 0 and fe2 == 0x19 and fm2 == 0x142 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x703a; op2val:0x6542; +op3val:0xfbff; valaddr_reg:x3; val_offset:438*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 438*FLEN/8, x4, x1, x2) + +inst_182: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0ae and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2b8 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6cae; op2val:0x76b8; +op3val:0xfbff; valaddr_reg:x3; val_offset:441*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 441*FLEN/8, x4, x1, x2) + +inst_183: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ec and fs2 == 0 and fe2 == 0x1c and fm2 == 0x08d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79ec; op2val:0x708d; +op3val:0xfbff; valaddr_reg:x3; val_offset:444*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 444*FLEN/8, x4, x1, x2) + +inst_184: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x117 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x168 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7917; op2val:0x6d68; +op3val:0xfbff; valaddr_reg:x3; val_offset:447*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 447*FLEN/8, x4, x1, x2) + +inst_185: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1e7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x396 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75e7; op2val:0x7b96; +op3val:0xfbff; valaddr_reg:x3; val_offset:450*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 450*FLEN/8, x4, x1, x2) + +inst_186: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x288 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2ac and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7688; op2val:0x76ac; +op3val:0xfbff; valaddr_reg:x3; val_offset:453*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 453*FLEN/8, x4, x1, x2) + +inst_187: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x120 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x286 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7520; op2val:0x7286; +op3val:0xfbff; valaddr_reg:x3; val_offset:456*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 456*FLEN/8, x4, x1, x2) + +inst_188: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x387 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x399 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7787; op2val:0x7b99; +op3val:0xfbff; valaddr_reg:x3; val_offset:459*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 459*FLEN/8, x4, x1, x2) + +inst_189: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x06d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x076 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x746d; op2val:0x7876; +op3val:0xfbff; valaddr_reg:x3; val_offset:462*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 462*FLEN/8, x4, x1, x2) + +inst_190: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25c and fs2 == 0 and fe2 == 0x1d and fm2 == 0x322 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5c; op2val:0x7722; +op3val:0xfbff; valaddr_reg:x3; val_offset:465*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 465*FLEN/8, x4, x1, x2) + +inst_191: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x223 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2e7 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a23; op2val:0x76e7; +op3val:0xfbff; valaddr_reg:x3; val_offset:468*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 468*FLEN/8, x4, x1, x2) + +inst_192: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x340 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x37e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7740; op2val:0x7b7e; +op3val:0xfbff; valaddr_reg:x3; val_offset:471*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 471*FLEN/8, x4, x1, x2) + +inst_193: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x365 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x118 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7765; op2val:0x7918; +op3val:0xfbff; valaddr_reg:x3; val_offset:474*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 474*FLEN/8, x4, x1, x2) + +inst_194: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x283 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x38b and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7283; op2val:0x578b; +op3val:0xfbff; valaddr_reg:x3; val_offset:477*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 477*FLEN/8, x4, x1, x2) + +inst_195: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0f2 and fs2 == 0 and fe2 == 0x17 and fm2 == 0x3f5 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78f2; op2val:0x5ff5; +op3val:0xfbff; valaddr_reg:x3; val_offset:480*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 480*FLEN/8, x4, x1, x2) + +inst_196: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x225 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x107 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a25; op2val:0x7907; +op3val:0xfbff; valaddr_reg:x3; val_offset:483*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 483*FLEN/8, x4, x1, x2) + +inst_197: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1a5 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70ff; op2val:0x79a5; +op3val:0xfbff; valaddr_reg:x3; val_offset:486*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 486*FLEN/8, x4, x1, x2) + +inst_198: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x16c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x213 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x796c; op2val:0x7a13; +op3val:0xfbff; valaddr_reg:x3; val_offset:489*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 489*FLEN/8, x4, x1, x2) + +inst_199: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x217 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x07a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a17; op2val:0x747a; +op3val:0xfbff; valaddr_reg:x3; val_offset:492*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 492*FLEN/8, x4, x1, x2) + +inst_200: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ac0; op2val:0x7a0f; +op3val:0xfbff; valaddr_reg:x3; val_offset:495*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 495*FLEN/8, x4, x1, x2) + +inst_201: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x024 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x016 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7424; op2val:0x7816; +op3val:0xfbff; valaddr_reg:x3; val_offset:498*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 498*FLEN/8, x4, x1, x2) + +inst_202: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0aa and fs2 == 0 and fe2 == 0x1e and fm2 == 0x342 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78aa; op2val:0x7b42; +op3val:0xfbff; valaddr_reg:x3; val_offset:501*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 501*FLEN/8, x4, x1, x2) + +inst_203: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x32f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79d5; op2val:0x7b2f; +op3val:0xfbff; valaddr_reg:x3; val_offset:504*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 504*FLEN/8, x4, x1, x2) + +inst_204: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x38c and fs2 == 0 and fe2 == 0x1b and fm2 == 0x271 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x778c; op2val:0x6e71; +op3val:0xfbff; valaddr_reg:x3; val_offset:507*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 507*FLEN/8, x4, x1, x2) + +inst_205: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x34c and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e2; op2val:0x7b4c; +op3val:0xfbff; valaddr_reg:x3; val_offset:510*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 510*FLEN/8, x4, x1, x2) + +inst_206: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2eb and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77a0; op2val:0x7aeb; +op3val:0xfbff; valaddr_reg:x3; val_offset:513*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 513*FLEN/8, x4, x1, x2) + +inst_207: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x063 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a6f; op2val:0x7863; +op3val:0xfbff; valaddr_reg:x3; val_offset:516*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 516*FLEN/8, x4, x1, x2) + +inst_208: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3cd and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aef; op2val:0x73cd; +op3val:0xfbff; valaddr_reg:x3; val_offset:519*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 519*FLEN/8, x4, x1, x2) + +inst_209: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a4 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x20e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74a4; op2val:0x720e; +op3val:0xfbff; valaddr_reg:x3; val_offset:522*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 522*FLEN/8, x4, x1, x2) + +inst_210: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1be and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dbe; op2val:0x7a0e; +op3val:0xfbff; valaddr_reg:x3; val_offset:525*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 525*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(31424,32,FLEN) +NAN_BOXED(31424,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29732,32,FLEN) +NAN_BOXED(30742,32,FLEN) +NAN_BOXED(29732,16,FLEN) +NAN_BOXED(31300,32,FLEN) +NAN_BOXED(29913,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30890,32,FLEN) +NAN_BOXED(30890,32,FLEN) +NAN_BOXED(30890,16,FLEN) +NAN_BOXED(29825,32,FLEN) +NAN_BOXED(31243,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29697,32,FLEN) +NAN_BOXED(31558,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31354,32,FLEN) +NAN_BOXED(31542,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31189,32,FLEN) +NAN_BOXED(31535,32,FLEN) +NAN_BOXED(31535,16,FLEN) +NAN_BOXED(30604,32,FLEN) +NAN_BOXED(28273,32,FLEN) +NAN_BOXED(30604,16,FLEN) +NAN_BOXED(30946,32,FLEN) +NAN_BOXED(30946,32,FLEN) +NAN_BOXED(30946,16,FLEN) +NAN_BOXED(30624,32,FLEN) +NAN_BOXED(31467,32,FLEN) +NAN_BOXED(31467,16,FLEN) +NAN_BOXED(31343,32,FLEN) +NAN_BOXED(31343,32,FLEN) +NAN_BOXED(64511,16,FLEN) +test_dataset_1: +NAN_BOXED(31169,32,FLEN) +NAN_BOXED(30304,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31063,32,FLEN) +NAN_BOXED(21677,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31471,32,FLEN) +NAN_BOXED(29645,32,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31477,32,FLEN) +NAN_BOXED(29212,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29601,32,FLEN) +NAN_BOXED(31676,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30505,32,FLEN) +NAN_BOXED(27941,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30735,32,FLEN) +NAN_BOXED(31605,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30824,32,FLEN) +NAN_BOXED(31142,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31363,32,FLEN) +NAN_BOXED(30801,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30930,32,FLEN) +NAN_BOXED(30898,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30916,32,FLEN) +NAN_BOXED(30247,32,FLEN) +NAN_BOXED(64511,16,FLEN) +test_dataset_2: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(29198,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30950,32,FLEN) +NAN_BOXED(31040,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28094,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31586,32,FLEN) +NAN_BOXED(31420,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31585,32,FLEN) +NAN_BOXED(30802,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31139,32,FLEN) +NAN_BOXED(29800,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31434,32,FLEN) +NAN_BOXED(31528,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31640,32,FLEN) +NAN_BOXED(30882,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31047,32,FLEN) +NAN_BOXED(31735,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31319,32,FLEN) +NAN_BOXED(27972,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30663,32,FLEN) +NAN_BOXED(30985,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29637,32,FLEN) +NAN_BOXED(31193,32,FLEN) +NAN_BOXED(64511,16,FLEN) +test_dataset_3: +NAN_BOXED(29453,16,FLEN) +NAN_BOXED(31322,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31366,16,FLEN) +NAN_BOXED(28271,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31124,16,FLEN) +NAN_BOXED(27081,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31558,16,FLEN) +NAN_BOXED(30789,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(26324,16,FLEN) +NAN_BOXED(30995,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30874,16,FLEN) +NAN_BOXED(30273,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31703,16,FLEN) +NAN_BOXED(26791,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31663,16,FLEN) +NAN_BOXED(29162,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29372,16,FLEN) +NAN_BOXED(31335,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(26068,16,FLEN) +NAN_BOXED(30414,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29736,16,FLEN) +NAN_BOXED(29456,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30106,16,FLEN) +NAN_BOXED(29124,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(26889,16,FLEN) +NAN_BOXED(28276,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29280,16,FLEN) +NAN_BOXED(30139,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31412,16,FLEN) +NAN_BOXED(31576,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31072,16,FLEN) +NAN_BOXED(31674,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31080,16,FLEN) +NAN_BOXED(31426,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29698,16,FLEN) +NAN_BOXED(30917,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29079,16,FLEN) +NAN_BOXED(30602,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30860,16,FLEN) +NAN_BOXED(30737,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30134,16,FLEN) +NAN_BOXED(31410,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30843,16,FLEN) +NAN_BOXED(25181,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30047,16,FLEN) +NAN_BOXED(27096,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29614,16,FLEN) +NAN_BOXED(31647,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29850,16,FLEN) +NAN_BOXED(30142,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30993,16,FLEN) +NAN_BOXED(30967,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30260,16,FLEN) +NAN_BOXED(30368,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(22077,16,FLEN) +NAN_BOXED(29222,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29608,16,FLEN) +NAN_BOXED(31000,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31487,16,FLEN) +NAN_BOXED(30859,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30318,16,FLEN) +NAN_BOXED(31132,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31051,16,FLEN) +NAN_BOXED(27132,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29733,16,FLEN) +NAN_BOXED(28939,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30666,16,FLEN) +NAN_BOXED(30845,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31505,16,FLEN) +NAN_BOXED(30696,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30583,16,FLEN) +NAN_BOXED(31352,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31359,16,FLEN) +NAN_BOXED(29187,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30991,16,FLEN) +NAN_BOXED(27990,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31716,16,FLEN) +NAN_BOXED(30317,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29966,16,FLEN) +NAN_BOXED(29396,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(22739,16,FLEN) +NAN_BOXED(31380,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28225,16,FLEN) +NAN_BOXED(28571,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31484,16,FLEN) +NAN_BOXED(29818,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28264,16,FLEN) +NAN_BOXED(31444,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(27956,16,FLEN) +NAN_BOXED(29796,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31317,16,FLEN) +NAN_BOXED(31459,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30762,16,FLEN) +NAN_BOXED(31028,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31480,16,FLEN) +NAN_BOXED(29811,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(26931,16,FLEN) +NAN_BOXED(31090,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31633,16,FLEN) +NAN_BOXED(31616,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(26975,16,FLEN) +NAN_BOXED(31229,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31037,16,FLEN) +NAN_BOXED(31154,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31006,16,FLEN) +NAN_BOXED(30196,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29349,16,FLEN) +NAN_BOXED(30897,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28884,16,FLEN) +NAN_BOXED(30036,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31166,16,FLEN) +NAN_BOXED(30056,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(26949,16,FLEN) +NAN_BOXED(28989,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29857,16,FLEN) +NAN_BOXED(30288,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29873,16,FLEN) +NAN_BOXED(30629,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(27180,16,FLEN) +NAN_BOXED(29118,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(27784,16,FLEN) +NAN_BOXED(30322,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30369,16,FLEN) +NAN_BOXED(28251,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30612,16,FLEN) +NAN_BOXED(31417,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30078,16,FLEN) +NAN_BOXED(30633,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30418,16,FLEN) +NAN_BOXED(29907,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31526,16,FLEN) +NAN_BOXED(31578,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30209,16,FLEN) +NAN_BOXED(31690,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(27702,16,FLEN) +NAN_BOXED(28010,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(27602,16,FLEN) +NAN_BOXED(24580,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30758,16,FLEN) +NAN_BOXED(30508,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30893,16,FLEN) +NAN_BOXED(31086,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30179,16,FLEN) +NAN_BOXED(31719,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31286,16,FLEN) +NAN_BOXED(30437,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(27669,16,FLEN) +NAN_BOXED(31463,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31544,16,FLEN) +NAN_BOXED(30520,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28571,16,FLEN) +NAN_BOXED(30301,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(26978,16,FLEN) +NAN_BOXED(31636,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28846,16,FLEN) +NAN_BOXED(29268,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30814,16,FLEN) +NAN_BOXED(28887,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31708,16,FLEN) +NAN_BOXED(28863,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31087,16,FLEN) +NAN_BOXED(31492,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31573,16,FLEN) +NAN_BOXED(29992,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30713,16,FLEN) +NAN_BOXED(31067,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30944,16,FLEN) +NAN_BOXED(29439,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31666,16,FLEN) +NAN_BOXED(31536,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(26761,16,FLEN) +NAN_BOXED(28862,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31301,16,FLEN) +NAN_BOXED(31420,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31166,16,FLEN) +NAN_BOXED(31348,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28010,16,FLEN) +NAN_BOXED(31474,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29491,16,FLEN) +NAN_BOXED(26930,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31423,16,FLEN) +NAN_BOXED(30025,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28866,16,FLEN) +NAN_BOXED(31039,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30729,16,FLEN) +NAN_BOXED(31540,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30870,16,FLEN) +NAN_BOXED(31085,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31247,16,FLEN) +NAN_BOXED(31723,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31550,16,FLEN) +NAN_BOXED(29335,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30921,16,FLEN) +NAN_BOXED(31386,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31315,16,FLEN) +NAN_BOXED(30262,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31438,16,FLEN) +NAN_BOXED(31329,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(19426,16,FLEN) +NAN_BOXED(29137,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29713,16,FLEN) +NAN_BOXED(27698,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31626,16,FLEN) +NAN_BOXED(29911,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31354,16,FLEN) +NAN_BOXED(27639,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28690,16,FLEN) +NAN_BOXED(29847,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(27418,16,FLEN) +NAN_BOXED(26776,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30685,16,FLEN) +NAN_BOXED(31463,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31074,16,FLEN) +NAN_BOXED(28887,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30355,16,FLEN) +NAN_BOXED(30948,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(27140,16,FLEN) +NAN_BOXED(30599,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(26663,16,FLEN) +NAN_BOXED(30959,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28348,16,FLEN) +NAN_BOXED(30820,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30241,16,FLEN) +NAN_BOXED(31285,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31499,16,FLEN) +NAN_BOXED(30944,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30990,16,FLEN) +NAN_BOXED(30055,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31093,16,FLEN) +NAN_BOXED(30969,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28688,16,FLEN) +NAN_BOXED(31562,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31572,16,FLEN) +NAN_BOXED(31482,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31354,16,FLEN) +NAN_BOXED(30758,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29196,16,FLEN) +NAN_BOXED(31296,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31244,16,FLEN) +NAN_BOXED(30536,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(27857,16,FLEN) +NAN_BOXED(27062,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30662,16,FLEN) +NAN_BOXED(31540,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31060,16,FLEN) +NAN_BOXED(30866,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28154,16,FLEN) +NAN_BOXED(31373,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31291,16,FLEN) +NAN_BOXED(31125,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29921,16,FLEN) +NAN_BOXED(28481,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30854,16,FLEN) +NAN_BOXED(31585,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30373,16,FLEN) +NAN_BOXED(28248,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31199,16,FLEN) +NAN_BOXED(26587,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31101,16,FLEN) +NAN_BOXED(26549,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31665,16,FLEN) +NAN_BOXED(31175,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(27775,16,FLEN) +NAN_BOXED(30142,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30096,16,FLEN) +NAN_BOXED(24857,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31372,16,FLEN) +NAN_BOXED(27778,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29350,16,FLEN) +NAN_BOXED(29324,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31616,16,FLEN) +NAN_BOXED(28641,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30183,16,FLEN) +NAN_BOXED(26190,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31454,16,FLEN) +NAN_BOXED(29179,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30082,16,FLEN) +NAN_BOXED(31659,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31674,16,FLEN) +NAN_BOXED(30155,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29870,16,FLEN) +NAN_BOXED(31614,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30997,16,FLEN) +NAN_BOXED(29154,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28303,16,FLEN) +NAN_BOXED(30884,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31533,16,FLEN) +NAN_BOXED(31631,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29965,16,FLEN) +NAN_BOXED(29636,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29863,16,FLEN) +NAN_BOXED(30390,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28730,16,FLEN) +NAN_BOXED(25922,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(27822,16,FLEN) +NAN_BOXED(30392,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31212,16,FLEN) +NAN_BOXED(28813,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30999,16,FLEN) +NAN_BOXED(28008,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30183,16,FLEN) +NAN_BOXED(31638,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30344,16,FLEN) +NAN_BOXED(30380,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29984,16,FLEN) +NAN_BOXED(29318,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30599,16,FLEN) +NAN_BOXED(31641,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29805,16,FLEN) +NAN_BOXED(30838,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31324,16,FLEN) +NAN_BOXED(30498,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31267,16,FLEN) +NAN_BOXED(30439,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30528,16,FLEN) +NAN_BOXED(31614,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30565,16,FLEN) +NAN_BOXED(31000,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29315,16,FLEN) +NAN_BOXED(22411,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30962,16,FLEN) +NAN_BOXED(24565,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31269,16,FLEN) +NAN_BOXED(30983,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28927,16,FLEN) +NAN_BOXED(31141,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31084,16,FLEN) +NAN_BOXED(31251,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31255,16,FLEN) +NAN_BOXED(29818,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31424,16,FLEN) +NAN_BOXED(31247,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29732,16,FLEN) +NAN_BOXED(30742,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30890,16,FLEN) +NAN_BOXED(31554,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31189,16,FLEN) +NAN_BOXED(31535,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30604,16,FLEN) +NAN_BOXED(28273,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30946,16,FLEN) +NAN_BOXED(31564,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30624,16,FLEN) +NAN_BOXED(31467,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31343,16,FLEN) +NAN_BOXED(30819,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31471,16,FLEN) +NAN_BOXED(29645,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29860,16,FLEN) +NAN_BOXED(29198,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28094,16,FLEN) +NAN_BOXED(31246,16,FLEN) +NAN_BOXED(64511,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 30*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x4_0: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_2: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_3: + .fill 108*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fmadd_b17-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fmadd_b17-01.S new file mode 100644 index 000000000..b2d9d9052 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fmadd_b17-01.S @@ -0,0 +1,2219 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 04:10:09 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fmadd.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fmadd.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fmadd_b17 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fmadd_b17) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x11,test_dataset_0) +RVTEST_SIGBASE(x4,signature_x4_1) + +inst_0: +// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==x15, rs2==x15, rs3==x13, rd==x23,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x15; op2:x15; op3:x13; dest:x23; op1val:0x7ac0; op2val:0x7ac0; +op3val:0xfbff; valaddr_reg:x11; val_offset:0*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x23, x15, x15, x13, dyn, 0, 0, x11, 0*FLEN/8, x16, x4, x10) + +inst_1: +// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==x6, rs2==x8, rs3==x6, rd==x12,fs1 == 0 and fe1 == 0x1d and fm1 == 0x024 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x016 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x6; op2:x8; op3:x6; dest:x12; op1val:0x7424; op2val:0x7816; +op3val:0x7424; valaddr_reg:x11; val_offset:3*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x12, x6, x8, x6, dyn, 0, 0, x11, 3*FLEN/8, x16, x4, x10) + +inst_2: +// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==x28, rs2==x13, rs3==x10, rd==x28,fs1 == 0 and fe1 == 0x1e and fm1 == 0x244 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0d9 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x28; op2:x13; op3:x10; dest:x28; op1val:0x7a44; op2val:0x74d9; +op3val:0xfbff; valaddr_reg:x11; val_offset:6*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x28, x28, x13, x10, dyn, 0, 0, x11, 6*FLEN/8, x16, x4, x10) + +inst_3: +// rs1 == rs2 == rs3 != rd, rs1==x26, rs2==x26, rs3==x26, rd==x0,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0aa and fs2 == 0 and fe2 == 0x1e and fm2 == 0x342 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x26; op2:x26; op3:x26; dest:x0; op1val:0x78aa; op2val:0x78aa; +op3val:0x78aa; valaddr_reg:x11; val_offset:9*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x0, x26, x26, x26, dyn, 0, 0, x11, 9*FLEN/8, x16, x4, x10) + +inst_4: +// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==x31, rs2==x29, rs3==x7, rd==x7,fs1 == 0 and fe1 == 0x1d and fm1 == 0x081 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20b and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x31; op2:x29; op3:x7; dest:x7; op1val:0x7481; op2val:0x7a0b; +op3val:0xfbff; valaddr_reg:x11; val_offset:12*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x7, x31, x29, x7, dyn, 0, 0, x11, 12*FLEN/8, x16, x4, x10) + +inst_5: +// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==x22, rs2==x9, rs3==x11, rd==x9,fs1 == 0 and fe1 == 0x1d and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x346 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x22; op2:x9; op3:x11; dest:x9; op1val:0x7401; op2val:0x7b46; +op3val:0xfbff; valaddr_reg:x11; val_offset:15*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x9, x22, x9, x11, dyn, 0, 0, x11, 15*FLEN/8, x16, x4, x10) + +inst_6: +// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==x5, rs2==x6, rs3==x4, rd==x2,fs1 == 0 and fe1 == 0x1e and fm1 == 0x27a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x336 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x5; op2:x6; op3:x4; dest:x2; op1val:0x7a7a; op2val:0x7b36; +op3val:0xfbff; valaddr_reg:x11; val_offset:18*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x2, x5, x6, x4, dyn, 0, 0, x11, 18*FLEN/8, x16, x4, x10) + +inst_7: +// rd == rs2 == rs3 != rs1, rs1==x18, rs2==x14, rs3==x14, rd==x14,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x32f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x18; op2:x14; op3:x14; dest:x14; op1val:0x79d5; op2val:0x7b2f; +op3val:0x7b2f; valaddr_reg:x11; val_offset:21*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x14, x18, x14, x14, dyn, 0, 0, x11, 21*FLEN/8, x16, x4, x10) + +inst_8: +// rs1 == rd == rs3 != rs2, rs1==x3, rs2==x19, rs3==x3, rd==x3,fs1 == 0 and fe1 == 0x1d and fm1 == 0x38c and fs2 == 0 and fe2 == 0x1b and fm2 == 0x271 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x3; op2:x19; op3:x3; dest:x3; op1val:0x778c; op2val:0x6e71; +op3val:0x778c; valaddr_reg:x11; val_offset:24*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x3, x3, x19, x3, dyn, 0, 0, x11, 24*FLEN/8, x16, x4, x10) + +inst_9: +// rs1 == rs2 == rs3 == rd, rs1==x25, rs2==x25, rs3==x25, rd==x25,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x34c and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x25; op2:x25; op3:x25; dest:x25; op1val:0x78e2; op2val:0x78e2; +op3val:0x78e2; valaddr_reg:x11; val_offset:27*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x25, x25, x25, x25, dyn, 0, 0, x11, 27*FLEN/8, x16, x4, x10) + +inst_10: +// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==x14, rs2==x24, rs3==x24, rd==x1,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2eb and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x14; op2:x24; op3:x24; dest:x1; op1val:0x77a0; op2val:0x7aeb; +op3val:0x7aeb; valaddr_reg:x11; val_offset:30*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x1, x14, x24, x24, dyn, 0, 0, x11, 30*FLEN/8, x16, x4, x10) +RVTEST_VALBASEUPD(x3,test_dataset_1) + +inst_11: +// rs1 == rs2 == rd != rs3, rs1==x16, rs2==x16, rs3==x27, rd==x16,fs1 == 0 and fe1 == 0x1e and fm1 == 0x26f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x063 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x16; op2:x16; op3:x27; dest:x16; op1val:0x7a6f; op2val:0x7a6f; +op3val:0xfbff; valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x16, x16, x16, x27, dyn, 0, 0, x3, 0*FLEN/8, x8, x4, x10) + +inst_12: +// rs1==x30, rs2==x27, rs3==x31, rd==x22,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c1 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x260 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x27; op3:x31; dest:x22; op1val:0x79c1; op2val:0x7660; +op3val:0xfbff; valaddr_reg:x3; val_offset:3*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x22, x30, x27, x31, dyn, 0, 0, x3, 3*FLEN/8, x8, x4, x10) +RVTEST_SIGBASE(x6,signature_x6_0) + +inst_13: +// rs1==x10, rs2==x22, rs3==x20, rd==x24,fs1 == 0 and fe1 == 0x1e and fm1 == 0x157 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x0ad and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x10; op2:x22; op3:x20; dest:x24; op1val:0x7957; op2val:0x54ad; +op3val:0xfbff; valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x24, x10, x22, x20, dyn, 0, 0, x3, 6*FLEN/8, x8, x6, x9) + +inst_14: +// rs1==x11, rs2==x0, rs3==x30, rd==x19,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3cd and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x11; op2:x0; op3:x30; dest:x19; op1val:0x7aef; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:9*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x19, x11, x0, x30, dyn, 0, 0, x3, 9*FLEN/8, x8, x6, x9) + +inst_15: +// rs1==x19, rs2==x31, rs3==x5, rd==x21,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f5 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x21c and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x19; op2:x31; op3:x5; dest:x21; op1val:0x7af5; op2val:0x721c; +op3val:0xfbff; valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x21, x19, x31, x5, dyn, 0, 0, x3, 12*FLEN/8, x8, x6, x9) + +inst_16: +// rs1==x7, rs2==x30, rs3==x19, rd==x5,fs1 == 0 and fe1 == 0x1c and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3bc and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x7; op2:x30; op3:x19; dest:x5; op1val:0x73a1; op2val:0x7bbc; +op3val:0xfbff; valaddr_reg:x3; val_offset:15*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x5, x7, x30, x19, dyn, 0, 0, x3, 15*FLEN/8, x8, x6, x9) + +inst_17: +// rs1==x24, rs2==x18, rs3==x0, rd==x30,fs1 == 0 and fe1 == 0x1d and fm1 == 0x329 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x125 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x24; op2:x18; op3:x0; dest:x30; op1val:0x7729; op2val:0x6d25; +op3val:0x0; valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x30, x24, x18, x0, dyn, 0, 0, x3, 18*FLEN/8, x8, x6, x9) + +inst_18: +// rs1==x29, rs2==x17, rs3==x12, rd==x27,fs1 == 0 and fe1 == 0x1e and fm1 == 0x00f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x375 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x29; op2:x17; op3:x12; dest:x27; op1val:0x780f; op2val:0x7b75; +op3val:0xfbff; valaddr_reg:x3; val_offset:21*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x27, x29, x17, x12, dyn, 0, 0, x3, 21*FLEN/8, x8, x6, x9) + +inst_19: +// rs1==x4, rs2==x5, rs3==x29, rd==x26,fs1 == 0 and fe1 == 0x1e and fm1 == 0x068 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1a6 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x4; op2:x5; op3:x29; dest:x26; op1val:0x7868; op2val:0x79a6; +op3val:0xfbff; valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x26, x4, x5, x29, dyn, 0, 0, x3, 24*FLEN/8, x8, x6, x9) + +inst_20: +// rs1==x23, rs2==x7, rs3==x18, rd==x10,fs1 == 0 and fe1 == 0x1e and fm1 == 0x283 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x051 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x23; op2:x7; op3:x18; dest:x10; op1val:0x7a83; op2val:0x7851; +op3val:0xfbff; valaddr_reg:x3; val_offset:27*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x10, x23, x7, x18, dyn, 0, 0, x3, 27*FLEN/8, x8, x6, x9) + +inst_21: +// rs1==x13, rs2==x12, rs3==x2, rd==x18,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0b2 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x13; op2:x12; op3:x2; dest:x18; op1val:0x78d2; op2val:0x78b2; +op3val:0xfbff; valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x18, x13, x12, x2, dyn, 0, 0, x3, 30*FLEN/8, x8, x6, x9) + +inst_22: +// rs1==x12, rs2==x2, rs3==x15, rd==x17,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c4 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x227 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x12; op2:x2; op3:x15; dest:x17; op1val:0x78c4; op2val:0x7627; +op3val:0xfbff; valaddr_reg:x3; val_offset:33*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x17, x12, x2, x15, dyn, 0, 0, x3, 33*FLEN/8, x8, x6, x9) + +inst_23: +// rs1==x2, rs2==x4, rs3==x22, rd==x31,fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a4 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x20e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x2; op2:x4; op3:x22; dest:x31; op1val:0x74a4; op2val:0x720e; +op3val:0xfbff; valaddr_reg:x3; val_offset:36*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x2, x4, x22, dyn, 0, 0, x3, 36*FLEN/8, x8, x6, x9) + +inst_24: +// rs1==x1, rs2==x21, rs3==x8, rd==x20,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x140 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x1; op2:x21; op3:x8; dest:x20; op1val:0x78e6; op2val:0x7940; +op3val:0xfbff; valaddr_reg:x3; val_offset:39*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x20, x1, x21, x8, dyn, 0, 0, x3, 39*FLEN/8, x8, x6, x9) +RVTEST_VALBASEUPD(x5,test_dataset_2) + +inst_25: +// rs1==x20, rs2==x3, rs3==x28, rd==x13,fs1 == 0 and fe1 == 0x1b and fm1 == 0x1be and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x20; op2:x3; op3:x28; dest:x13; op1val:0x6dbe; op2val:0x7a0e; +op3val:0xfbff; valaddr_reg:x5; val_offset:0*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x13, x20, x3, x28, dyn, 0, 0, x5, 0*FLEN/8, x7, x6, x9) + +inst_26: +// rs1==x21, rs2==x1, rs3==x16, rd==x4,fs1 == 0 and fe1 == 0x1e and fm1 == 0x362 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2bc and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x21; op2:x1; op3:x16; dest:x4; op1val:0x7b62; op2val:0x7abc; +op3val:0xfbff; valaddr_reg:x5; val_offset:3*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x4, x21, x1, x16, dyn, 0, 0, x5, 3*FLEN/8, x7, x6, x9) + +inst_27: +// rs1==x17, rs2==x20, rs3==x9, rd==x8,fs1 == 0 and fe1 == 0x1e and fm1 == 0x361 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x052 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x17; op2:x20; op3:x9; dest:x8; op1val:0x7b61; op2val:0x7852; +op3val:0xfbff; valaddr_reg:x5; val_offset:6*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x8, x17, x20, x9, dyn, 0, 0, x5, 6*FLEN/8, x7, x6, x9) + +inst_28: +// rs1==x9, rs2==x11, rs3==x1, rd==x15,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a3 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x068 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x9; op2:x11; op3:x1; dest:x15; op1val:0x79a3; op2val:0x7468; +op3val:0xfbff; valaddr_reg:x5; val_offset:9*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x15, x9, x11, x1, dyn, 0, 0, x5, 9*FLEN/8, x7, x6, x2) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_29: +// rs1==x0, rs2==x10, rs3==x17, rd==x29,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ca and fs2 == 0 and fe2 == 0x1e and fm2 == 0x328 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x0; op2:x10; op3:x17; dest:x29; op1val:0x0; op2val:0x7b28; +op3val:0xfbff; valaddr_reg:x5; val_offset:12*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x29, x0, x10, x17, dyn, 0, 0, x5, 12*FLEN/8, x7, x1, x2) + +inst_30: +// rs1==x8, rs2==x28, rs3==x23, rd==x6,fs1 == 0 and fe1 == 0x1e and fm1 == 0x398 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0a2 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x8; op2:x28; op3:x23; dest:x6; op1val:0x7b98; op2val:0x78a2; +op3val:0xfbff; valaddr_reg:x5; val_offset:15*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x6, x8, x28, x23, dyn, 0, 0, x5, 15*FLEN/8, x7, x1, x2) + +inst_31: +// rs1==x27, rs2==x23, rs3==x21, rd==x11,fs1 == 0 and fe1 == 0x1e and fm1 == 0x147 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3f7 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x27; op2:x23; op3:x21; dest:x11; op1val:0x7947; op2val:0x7bf7; +op3val:0xfbff; valaddr_reg:x5; val_offset:18*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x11, x27, x23, x21, dyn, 0, 0, x5, 18*FLEN/8, x7, x1, x2) + +inst_32: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x257 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x144 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a57; op2val:0x6d44; +op3val:0xfbff; valaddr_reg:x5; val_offset:21*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 21*FLEN/8, x7, x1, x2) + +inst_33: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3c7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x109 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77c7; op2val:0x7909; +op3val:0xfbff; valaddr_reg:x5; val_offset:24*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 24*FLEN/8, x7, x1, x2) + +inst_34: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3c5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1d9 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73c5; op2val:0x79d9; +op3val:0xfbff; valaddr_reg:x5; val_offset:27*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 27*FLEN/8, x7, x1, x2) + +inst_35: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x30d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x25a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x730d; op2val:0x7a5a; +op3val:0xfbff; valaddr_reg:x5; val_offset:30*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 30*FLEN/8, x7, x1, x2) + +inst_36: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x286 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x26f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a86; op2val:0x6e6f; +op3val:0xfbff; valaddr_reg:x5; val_offset:33*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 33*FLEN/8, x7, x1, x2) + +inst_37: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x194 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x1c9 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7994; op2val:0x69c9; +op3val:0xfbff; valaddr_reg:x5; val_offset:36*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 36*FLEN/8, x7, x1, x2) + +inst_38: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x346 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x045 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b46; op2val:0x7845; +op3val:0xfbff; valaddr_reg:x5; val_offset:39*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 39*FLEN/8, x7, x1, x2) + +inst_39: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x2d4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x113 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x66d4; op2val:0x7913; +op3val:0xfbff; valaddr_reg:x5; val_offset:42*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 42*FLEN/8, x7, x1, x2) + +inst_40: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09a and fs2 == 0 and fe2 == 0x1d and fm2 == 0x241 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x789a; op2val:0x7641; +op3val:0xfbff; valaddr_reg:x5; val_offset:45*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 45*FLEN/8, x7, x1, x2) + +inst_41: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d7 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x0a7 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd7; op2val:0x68a7; +op3val:0xfbff; valaddr_reg:x5; val_offset:48*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 48*FLEN/8, x7, x1, x2) + +inst_42: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3af and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1ea and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7baf; op2val:0x71ea; +op3val:0xfbff; valaddr_reg:x5; val_offset:51*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 51*FLEN/8, x7, x1, x2) + +inst_43: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2bc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x267 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72bc; op2val:0x7a67; +op3val:0xfbff; valaddr_reg:x5; val_offset:54*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 54*FLEN/8, x7, x1, x2) + +inst_44: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x1d4 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2ce and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x65d4; op2val:0x76ce; +op3val:0xfbff; valaddr_reg:x5; val_offset:57*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 57*FLEN/8, x7, x1, x2) + +inst_45: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x028 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x310 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7428; op2val:0x7310; +op3val:0xfbff; valaddr_reg:x5; val_offset:60*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 60*FLEN/8, x7, x1, x2) + +inst_46: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x19a and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1c4 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x759a; op2val:0x71c4; +op3val:0xfbff; valaddr_reg:x5; val_offset:63*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 63*FLEN/8, x7, x1, x2) + +inst_47: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x109 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x274 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6909; op2val:0x6e74; +op3val:0xfbff; valaddr_reg:x5; val_offset:66*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 66*FLEN/8, x7, x1, x2) + +inst_48: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x260 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1bb and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7260; op2val:0x75bb; +op3val:0xfbff; valaddr_reg:x5; val_offset:69*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 69*FLEN/8, x7, x1, x2) + +inst_49: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x358 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ab4; op2val:0x7b58; +op3val:0xfbff; valaddr_reg:x5; val_offset:72*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 72*FLEN/8, x7, x1, x2) + +inst_50: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x160 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ba and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7960; op2val:0x7bba; +op3val:0xfbff; valaddr_reg:x5; val_offset:75*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 75*FLEN/8, x7, x1, x2) + +inst_51: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x168 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c2 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7968; op2val:0x7ac2; +op3val:0xfbff; valaddr_reg:x5; val_offset:78*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 78*FLEN/8, x7, x1, x2) + +inst_52: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0c5 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7402; op2val:0x78c5; +op3val:0xfbff; valaddr_reg:x5; val_offset:81*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 81*FLEN/8, x7, x1, x2) + +inst_53: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x197 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x38a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7197; op2val:0x778a; +op3val:0xfbff; valaddr_reg:x5; val_offset:84*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 84*FLEN/8, x7, x1, x2) + +inst_54: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x08c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x011 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x788c; op2val:0x7811; +op3val:0xfbff; valaddr_reg:x5; val_offset:87*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 87*FLEN/8, x7, x1, x2) + +inst_55: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1b6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b2 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75b6; op2val:0x7ab2; +op3val:0xfbff; valaddr_reg:x5; val_offset:90*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 90*FLEN/8, x7, x1, x2) + +inst_56: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x07b and fs2 == 0 and fe2 == 0x18 and fm2 == 0x25d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x787b; op2val:0x625d; +op3val:0xfbff; valaddr_reg:x5; val_offset:93*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 93*FLEN/8, x7, x1, x2) + +inst_57: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x15f and fs2 == 0 and fe2 == 0x1a and fm2 == 0x1d8 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x755f; op2val:0x69d8; +op3val:0xfbff; valaddr_reg:x5; val_offset:96*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 96*FLEN/8, x7, x1, x2) + +inst_58: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3ae and fs2 == 0 and fe2 == 0x1e and fm2 == 0x39f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73ae; op2val:0x7b9f; +op3val:0xfbff; valaddr_reg:x5; val_offset:99*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 99*FLEN/8, x7, x1, x2) + +inst_59: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x09a and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1be and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x749a; op2val:0x75be; +op3val:0xfbff; valaddr_reg:x5; val_offset:102*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 102*FLEN/8, x7, x1, x2) + +inst_60: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x111 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0f7 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7911; op2val:0x78f7; +op3val:0xfbff; valaddr_reg:x5; val_offset:105*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 105*FLEN/8, x7, x1, x2) + +inst_61: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x234 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2a0 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7634; op2val:0x76a0; +op3val:0xfbff; valaddr_reg:x5; val_offset:108*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 108*FLEN/8, x7, x1, x2) + +inst_62: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x23d and fs2 == 0 and fe2 == 0x1c and fm2 == 0x226 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x563d; op2val:0x7226; +op3val:0xfbff; valaddr_reg:x5; val_offset:111*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 111*FLEN/8, x7, x1, x2) + +inst_63: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3a8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x118 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73a8; op2val:0x7918; +op3val:0xfbff; valaddr_reg:x5; val_offset:114*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 114*FLEN/8, x7, x1, x2) + +inst_64: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x08b and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aff; op2val:0x788b; +op3val:0xfbff; valaddr_reg:x5; val_offset:117*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 117*FLEN/8, x7, x1, x2) + +inst_65: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x19c and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x766e; op2val:0x799c; +op3val:0xfbff; valaddr_reg:x5; val_offset:120*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 120*FLEN/8, x7, x1, x2) + +inst_66: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x14b and fs2 == 0 and fe2 == 0x1a and fm2 == 0x1fc and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x794b; op2val:0x69fc; +op3val:0xfbff; valaddr_reg:x5; val_offset:123*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 123*FLEN/8, x7, x1, x2) + +inst_67: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x10b and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7425; op2val:0x710b; +op3val:0xfbff; valaddr_reg:x5; val_offset:126*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 126*FLEN/8, x7, x1, x2) + +inst_68: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ca and fs2 == 0 and fe2 == 0x1e and fm2 == 0x07d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77ca; op2val:0x787d; +op3val:0xfbff; valaddr_reg:x5; val_offset:129*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 129*FLEN/8, x7, x1, x2) + +inst_69: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x311 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3e8 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b11; op2val:0x77e8; +op3val:0xfbff; valaddr_reg:x5; val_offset:132*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 132*FLEN/8, x7, x1, x2) + +inst_70: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x377 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x278 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7777; op2val:0x7a78; +op3val:0xfbff; valaddr_reg:x5; val_offset:135*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 135*FLEN/8, x7, x1, x2) + +inst_71: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x27f and fs2 == 0 and fe2 == 0x1c and fm2 == 0x203 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a7f; op2val:0x7203; +op3val:0xfbff; valaddr_reg:x5; val_offset:138*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 138*FLEN/8, x7, x1, x2) + +inst_72: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x10f and fs2 == 0 and fe2 == 0x1b and fm2 == 0x156 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x790f; op2val:0x6d56; +op3val:0xfbff; valaddr_reg:x5; val_offset:141*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 141*FLEN/8, x7, x1, x2) + +inst_73: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e4 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x26d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7be4; op2val:0x766d; +op3val:0xfbff; valaddr_reg:x5; val_offset:144*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 144*FLEN/8, x7, x1, x2) + +inst_74: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x10e and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2d4 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x750e; op2val:0x72d4; +op3val:0xfbff; valaddr_reg:x5; val_offset:147*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 147*FLEN/8, x7, x1, x2) + +inst_75: +// fs1 == 0 and fe1 == 0x16 and fm1 == 0x0d3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x294 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x58d3; op2val:0x7a94; +op3val:0xfbff; valaddr_reg:x5; val_offset:150*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 150*FLEN/8, x7, x1, x2) + +inst_76: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x241 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x39b and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e41; op2val:0x6f9b; +op3val:0xfbff; valaddr_reg:x5; val_offset:153*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 153*FLEN/8, x7, x1, x2) + +inst_77: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2fc and fs2 == 0 and fe2 == 0x1d and fm2 == 0x07a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7afc; op2val:0x747a; +op3val:0xfbff; valaddr_reg:x5; val_offset:156*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 156*FLEN/8, x7, x1, x2) + +inst_78: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x268 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2d4 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e68; op2val:0x7ad4; +op3val:0xfbff; valaddr_reg:x5; val_offset:159*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 159*FLEN/8, x7, x1, x2) + +inst_79: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x134 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x064 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d34; op2val:0x7464; +op3val:0xfbff; valaddr_reg:x5; val_offset:162*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 162*FLEN/8, x7, x1, x2) + +inst_80: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2e3 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a55; op2val:0x7ae3; +op3val:0xfbff; valaddr_reg:x5; val_offset:165*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 165*FLEN/8, x7, x1, x2) + +inst_81: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x134 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x782a; op2val:0x7934; +op3val:0xfbff; valaddr_reg:x5; val_offset:168*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 168*FLEN/8, x7, x1, x2) + +inst_82: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f8 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x073 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7af8; op2val:0x7473; +op3val:0xfbff; valaddr_reg:x5; val_offset:171*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 171*FLEN/8, x7, x1, x2) + +inst_83: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x133 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x172 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6933; op2val:0x7972; +op3val:0xfbff; valaddr_reg:x5; val_offset:174*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 174*FLEN/8, x7, x1, x2) + +inst_84: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x391 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x380 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b91; op2val:0x7b80; +op3val:0xfbff; valaddr_reg:x5; val_offset:177*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 177*FLEN/8, x7, x1, x2) + +inst_85: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x15f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1fd and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x695f; op2val:0x79fd; +op3val:0xfbff; valaddr_reg:x5; val_offset:180*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 180*FLEN/8, x7, x1, x2) + +inst_86: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x13d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1b2 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x793d; op2val:0x79b2; +op3val:0xfbff; valaddr_reg:x5; val_offset:183*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 183*FLEN/8, x7, x1, x2) + +inst_87: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x11e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1f4 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x791e; op2val:0x75f4; +op3val:0xfbff; valaddr_reg:x5; val_offset:186*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 186*FLEN/8, x7, x1, x2) + +inst_88: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2a5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0b1 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72a5; op2val:0x78b1; +op3val:0xfbff; valaddr_reg:x5; val_offset:189*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 189*FLEN/8, x7, x1, x2) + +inst_89: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0d4 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x154 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70d4; op2val:0x7554; +op3val:0xfbff; valaddr_reg:x5; val_offset:192*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 192*FLEN/8, x7, x1, x2) + +inst_90: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1be and fs2 == 0 and fe2 == 0x1d and fm2 == 0x168 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79be; op2val:0x7568; +op3val:0xfbff; valaddr_reg:x5; val_offset:195*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 195*FLEN/8, x7, x1, x2) + +inst_91: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x145 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x13d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6945; op2val:0x713d; +op3val:0xfbff; valaddr_reg:x5; val_offset:198*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 198*FLEN/8, x7, x1, x2) + +inst_92: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a1 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x250 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74a1; op2val:0x7650; +op3val:0xfbff; valaddr_reg:x5; val_offset:201*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 201*FLEN/8, x7, x1, x2) + +inst_93: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0b1 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3a5 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74b1; op2val:0x77a5; +op3val:0xfbff; valaddr_reg:x5; val_offset:204*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 204*FLEN/8, x7, x1, x2) + +inst_94: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x22c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1be and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6a2c; op2val:0x71be; +op3val:0xfbff; valaddr_reg:x5; val_offset:207*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 207*FLEN/8, x7, x1, x2) + +inst_95: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x088 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x272 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c88; op2val:0x7672; +op3val:0xfbff; valaddr_reg:x5; val_offset:210*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 210*FLEN/8, x7, x1, x2) + +inst_96: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a1 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x25b and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76a1; op2val:0x6e5b; +op3val:0xfbff; valaddr_reg:x5; val_offset:213*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 213*FLEN/8, x7, x1, x2) + +inst_97: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x394 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b9 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7794; op2val:0x7ab9; +op3val:0xfbff; valaddr_reg:x5; val_offset:216*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 216*FLEN/8, x7, x1, x2) + +inst_98: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x17e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3a9 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x757e; op2val:0x77a9; +op3val:0xfbff; valaddr_reg:x5; val_offset:219*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 219*FLEN/8, x7, x1, x2) + +inst_99: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2d2 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0d3 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76d2; op2val:0x74d3; +op3val:0xfbff; valaddr_reg:x5; val_offset:222*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 222*FLEN/8, x7, x1, x2) + +inst_100: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x326 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x35a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b26; op2val:0x7b5a; +op3val:0xfbff; valaddr_reg:x5; val_offset:225*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 225*FLEN/8, x7, x1, x2) + +inst_101: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ca and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7601; op2val:0x7bca; +op3val:0xfbff; valaddr_reg:x5; val_offset:228*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 228*FLEN/8, x7, x1, x2) + +inst_102: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x036 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x16a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c36; op2val:0x6d6a; +op3val:0xfbff; valaddr_reg:x5; val_offset:231*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 231*FLEN/8, x7, x1, x2) + +inst_103: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3d2 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x004 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6bd2; op2val:0x6004; +op3val:0xfbff; valaddr_reg:x5; val_offset:234*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 234*FLEN/8, x7, x1, x2) + +inst_104: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x026 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x32c and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7826; op2val:0x772c; +op3val:0xfbff; valaddr_reg:x5; val_offset:237*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 237*FLEN/8, x7, x1, x2) + +inst_105: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ad and fs2 == 0 and fe2 == 0x1e and fm2 == 0x16e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78ad; op2val:0x796e; +op3val:0xfbff; valaddr_reg:x5; val_offset:240*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 240*FLEN/8, x7, x1, x2) + +inst_106: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1e3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3e7 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75e3; op2val:0x7be7; +op3val:0xfbff; valaddr_reg:x5; val_offset:243*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 243*FLEN/8, x7, x1, x2) + +inst_107: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x236 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2e5 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a36; op2val:0x76e5; +op3val:0xfbff; valaddr_reg:x5; val_offset:246*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 246*FLEN/8, x7, x1, x2) + +inst_108: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x015 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2e7 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c15; op2val:0x7ae7; +op3val:0xfbff; valaddr_reg:x5; val_offset:249*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 249*FLEN/8, x7, x1, x2) + +inst_109: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x338 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x338 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b38; op2val:0x7738; +op3val:0xfbff; valaddr_reg:x5; val_offset:252*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 252*FLEN/8, x7, x1, x2) + +inst_110: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x39b and fs2 == 0 and fe2 == 0x1d and fm2 == 0x25d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f9b; op2val:0x765d; +op3val:0xfbff; valaddr_reg:x5; val_offset:255*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 255*FLEN/8, x7, x1, x2) + +inst_111: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x162 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x394 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6962; op2val:0x7b94; +op3val:0xfbff; valaddr_reg:x5; val_offset:258*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 258*FLEN/8, x7, x1, x2) + +inst_112: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0ae and fs2 == 0 and fe2 == 0x1c and fm2 == 0x254 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70ae; op2val:0x7254; +op3val:0xfbff; valaddr_reg:x5; val_offset:261*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 261*FLEN/8, x7, x1, x2) + +inst_113: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x05e and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0d7 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x785e; op2val:0x70d7; +op3val:0xfbff; valaddr_reg:x5; val_offset:264*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 264*FLEN/8, x7, x1, x2) + +inst_114: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3dc and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0bf and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bdc; op2val:0x70bf; +op3val:0xfbff; valaddr_reg:x5; val_offset:267*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 267*FLEN/8, x7, x1, x2) + +inst_115: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x16f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x304 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x796f; op2val:0x7b04; +op3val:0xfbff; valaddr_reg:x5; val_offset:270*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 270*FLEN/8, x7, x1, x2) + +inst_116: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x355 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x128 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b55; op2val:0x7528; +op3val:0xfbff; valaddr_reg:x5; val_offset:273*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 273*FLEN/8, x7, x1, x2) + +inst_117: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3f9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x15b and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77f9; op2val:0x795b; +op3val:0xfbff; valaddr_reg:x5; val_offset:276*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 276*FLEN/8, x7, x1, x2) + +inst_118: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e0 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e0; op2val:0x72ff; +op3val:0xfbff; valaddr_reg:x5; val_offset:279*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 279*FLEN/8, x7, x1, x2) + +inst_119: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x330 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bb2; op2val:0x7b30; +op3val:0xfbff; valaddr_reg:x5; val_offset:282*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 282*FLEN/8, x7, x1, x2) + +inst_120: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x089 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0be and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6889; op2val:0x70be; +op3val:0xfbff; valaddr_reg:x5; val_offset:285*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 285*FLEN/8, x7, x1, x2) + +inst_121: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x245 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2bc and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a45; op2val:0x7abc; +op3val:0xfbff; valaddr_reg:x5; val_offset:288*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 288*FLEN/8, x7, x1, x2) + +inst_122: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1be and fs2 == 0 and fe2 == 0x1e and fm2 == 0x274 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79be; op2val:0x7a74; +op3val:0xfbff; valaddr_reg:x5; val_offset:291*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 291*FLEN/8, x7, x1, x2) + +inst_123: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x16a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2f2 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d6a; op2val:0x7af2; +op3val:0xfbff; valaddr_reg:x5; val_offset:294*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 294*FLEN/8, x7, x1, x2) + +inst_124: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x333 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x132 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7333; op2val:0x6932; +op3val:0xfbff; valaddr_reg:x5; val_offset:297*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 297*FLEN/8, x7, x1, x2) + +inst_125: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2bf and fs2 == 0 and fe2 == 0x1d and fm2 == 0x149 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7abf; op2val:0x7549; +op3val:0xfbff; valaddr_reg:x5; val_offset:300*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 300*FLEN/8, x7, x1, x2) + +inst_126: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0c2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x13f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70c2; op2val:0x793f; +op3val:0xfbff; valaddr_reg:x5; val_offset:303*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 303*FLEN/8, x7, x1, x2) + +inst_127: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x009 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x334 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7809; op2val:0x7b34; +op3val:0xfbff; valaddr_reg:x5; val_offset:306*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 306*FLEN/8, x7, x1, x2) + +inst_128: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x096 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x16d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7896; op2val:0x796d; +op3val:0xfbff; valaddr_reg:x5; val_offset:309*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 309*FLEN/8, x7, x1, x2) + +inst_129: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3eb and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a0f; op2val:0x7beb; +op3val:0xfbff; valaddr_reg:x5; val_offset:312*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 312*FLEN/8, x7, x1, x2) + +inst_130: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x33e and fs2 == 0 and fe2 == 0x1c and fm2 == 0x297 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b3e; op2val:0x7297; +op3val:0xfbff; valaddr_reg:x5; val_offset:315*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 315*FLEN/8, x7, x1, x2) + +inst_131: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x29a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78c9; op2val:0x7a9a; +op3val:0xfbff; valaddr_reg:x5; val_offset:318*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 318*FLEN/8, x7, x1, x2) + +inst_132: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x253 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x236 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a53; op2val:0x7636; +op3val:0xfbff; valaddr_reg:x5; val_offset:321*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 321*FLEN/8, x7, x1, x2) + +inst_133: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ce and fs2 == 0 and fe2 == 0x1e and fm2 == 0x261 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ace; op2val:0x7a61; +op3val:0xfbff; valaddr_reg:x5; val_offset:324*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 324*FLEN/8, x7, x1, x2) + +inst_134: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x3e2 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1d1 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4be2; op2val:0x71d1; +op3val:0xfbff; valaddr_reg:x5; val_offset:327*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 327*FLEN/8, x7, x1, x2) + +inst_135: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x011 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x032 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7411; op2val:0x6c32; +op3val:0xfbff; valaddr_reg:x5; val_offset:330*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 330*FLEN/8, x7, x1, x2) + +inst_136: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x38a and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0d7 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b8a; op2val:0x74d7; +op3val:0xfbff; valaddr_reg:x5; val_offset:333*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 333*FLEN/8, x7, x1, x2) + +inst_137: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x27a and fs2 == 0 and fe2 == 0x1a and fm2 == 0x3f7 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a7a; op2val:0x6bf7; +op3val:0xfbff; valaddr_reg:x5; val_offset:336*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 336*FLEN/8, x7, x1, x2) + +inst_138: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x012 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x097 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7012; op2val:0x7497; +op3val:0xfbff; valaddr_reg:x5; val_offset:339*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 339*FLEN/8, x7, x1, x2) + +inst_139: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x31a and fs2 == 0 and fe2 == 0x1a and fm2 == 0x098 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6b1a; op2val:0x6898; +op3val:0xfbff; valaddr_reg:x5; val_offset:342*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 342*FLEN/8, x7, x1, x2) + +inst_140: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3dd and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2e7 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77dd; op2val:0x7ae7; +op3val:0xfbff; valaddr_reg:x5; val_offset:345*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 345*FLEN/8, x7, x1, x2) + +inst_141: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x162 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0d7 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7962; op2val:0x70d7; +op3val:0xfbff; valaddr_reg:x5; val_offset:348*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 348*FLEN/8, x7, x1, x2) + +inst_142: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x293 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0e4 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7693; op2val:0x78e4; +op3val:0xfbff; valaddr_reg:x5; val_offset:351*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 351*FLEN/8, x7, x1, x2) + +inst_143: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x204 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x387 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6a04; op2val:0x7787; +op3val:0xfbff; valaddr_reg:x5; val_offset:354*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 354*FLEN/8, x7, x1, x2) + +inst_144: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x027 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0ef and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6827; op2val:0x78ef; +op3val:0xfbff; valaddr_reg:x5; val_offset:357*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 357*FLEN/8, x7, x1, x2) + +inst_145: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2bc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x064 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ebc; op2val:0x7864; +op3val:0xfbff; valaddr_reg:x5; val_offset:360*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 360*FLEN/8, x7, x1, x2) + +inst_146: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x221 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x235 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7621; op2val:0x7a35; +op3val:0xfbff; valaddr_reg:x5; val_offset:363*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 363*FLEN/8, x7, x1, x2) + +inst_147: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0e0 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b0b; op2val:0x78e0; +op3val:0xfbff; valaddr_reg:x5; val_offset:366*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 366*FLEN/8, x7, x1, x2) + +inst_148: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x10e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x167 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x790e; op2val:0x7567; +op3val:0xfbff; valaddr_reg:x5; val_offset:369*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 369*FLEN/8, x7, x1, x2) + +inst_149: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x175 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0f9 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7975; op2val:0x78f9; +op3val:0xfbff; valaddr_reg:x5; val_offset:372*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 372*FLEN/8, x7, x1, x2) + +inst_150: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x010 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x34a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7010; op2val:0x7b4a; +op3val:0xfbff; valaddr_reg:x5; val_offset:375*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 375*FLEN/8, x7, x1, x2) + +inst_151: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x354 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2fa and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b54; op2val:0x7afa; +op3val:0xfbff; valaddr_reg:x5; val_offset:378*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 378*FLEN/8, x7, x1, x2) + +inst_152: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x27a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x026 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a7a; op2val:0x7826; +op3val:0xfbff; valaddr_reg:x5; val_offset:381*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 381*FLEN/8, x7, x1, x2) + +inst_153: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x20c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x240 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x720c; op2val:0x7a40; +op3val:0xfbff; valaddr_reg:x5; val_offset:384*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 384*FLEN/8, x7, x1, x2) + +inst_154: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20c and fs2 == 0 and fe2 == 0x1d and fm2 == 0x348 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a0c; op2val:0x7748; +op3val:0xfbff; valaddr_reg:x5; val_offset:387*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 387*FLEN/8, x7, x1, x2) + +inst_155: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0d1 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x1b6 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6cd1; op2val:0x69b6; +op3val:0xfbff; valaddr_reg:x5; val_offset:390*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 390*FLEN/8, x7, x1, x2) + +inst_156: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3c6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x334 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77c6; op2val:0x7b34; +op3val:0xfbff; valaddr_reg:x5; val_offset:393*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 393*FLEN/8, x7, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_157: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x154 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x092 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7954; op2val:0x7892; +op3val:0xfbff; valaddr_reg:x5; val_offset:396*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 396*FLEN/8, x7, x1, x2) + +inst_158: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1fa and fs2 == 0 and fe2 == 0x1e and fm2 == 0x28d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dfa; op2val:0x7a8d; +op3val:0xfbff; valaddr_reg:x5; val_offset:399*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 399*FLEN/8, x7, x1, x2) + +inst_159: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x23b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x195 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a3b; op2val:0x7995; +op3val:0xfbff; valaddr_reg:x5; val_offset:402*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 402*FLEN/8, x7, x1, x2) + +inst_160: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0e1 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x341 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74e1; op2val:0x6f41; +op3val:0xfbff; valaddr_reg:x5; val_offset:405*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 405*FLEN/8, x7, x1, x2) + +inst_161: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x086 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x361 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7886; op2val:0x7b61; +op3val:0xfbff; valaddr_reg:x5; val_offset:408*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 408*FLEN/8, x7, x1, x2) + +inst_162: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a5 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x258 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76a5; op2val:0x6e58; +op3val:0xfbff; valaddr_reg:x5; val_offset:411*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 411*FLEN/8, x7, x1, x2) + +inst_163: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1df and fs2 == 0 and fe2 == 0x19 and fm2 == 0x3db and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79df; op2val:0x67db; +op3val:0xfbff; valaddr_reg:x5; val_offset:414*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 414*FLEN/8, x7, x1, x2) + +inst_164: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x17d and fs2 == 0 and fe2 == 0x19 and fm2 == 0x3b5 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x797d; op2val:0x67b5; +op3val:0xfbff; valaddr_reg:x5; val_offset:417*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 417*FLEN/8, x7, x1, x2) + +inst_165: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1c7 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bb1; op2val:0x79c7; +op3val:0xfbff; valaddr_reg:x5; val_offset:420*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 420*FLEN/8, x7, x1, x2) + +inst_166: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x07f and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1be and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c7f; op2val:0x75be; +op3val:0xfbff; valaddr_reg:x5; val_offset:423*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 423*FLEN/8, x7, x1, x2) + +inst_167: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x190 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x119 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7590; op2val:0x6119; +op3val:0xfbff; valaddr_reg:x5; val_offset:426*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 426*FLEN/8, x7, x1, x2) + +inst_168: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28c and fs2 == 0 and fe2 == 0x1b and fm2 == 0x082 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8c; op2val:0x6c82; +op3val:0xfbff; valaddr_reg:x5; val_offset:429*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 429*FLEN/8, x7, x1, x2) + +inst_169: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2a6 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x28c and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72a6; op2val:0x728c; +op3val:0xfbff; valaddr_reg:x5; val_offset:432*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 432*FLEN/8, x7, x1, x2) + +inst_170: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x380 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3e1 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b80; op2val:0x6fe1; +op3val:0xfbff; valaddr_reg:x5; val_offset:435*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 435*FLEN/8, x7, x1, x2) + +inst_171: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1e7 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x24e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75e7; op2val:0x664e; +op3val:0xfbff; valaddr_reg:x5; val_offset:438*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 438*FLEN/8, x7, x1, x2) + +inst_172: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2de and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1fb and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ade; op2val:0x71fb; +op3val:0xfbff; valaddr_reg:x5; val_offset:441*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 441*FLEN/8, x7, x1, x2) + +inst_173: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x182 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ab and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7582; op2val:0x7bab; +op3val:0xfbff; valaddr_reg:x5; val_offset:444*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 444*FLEN/8, x7, x1, x2) + +inst_174: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ba and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1cb and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bba; op2val:0x75cb; +op3val:0xfbff; valaddr_reg:x5; val_offset:447*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 447*FLEN/8, x7, x1, x2) + +inst_175: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ae and fs2 == 0 and fe2 == 0x1e and fm2 == 0x37e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74ae; op2val:0x7b7e; +op3val:0xfbff; valaddr_reg:x5; val_offset:450*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 450*FLEN/8, x7, x1, x2) + +inst_176: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x115 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1e2 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7915; op2val:0x71e2; +op3val:0xfbff; valaddr_reg:x5; val_offset:453*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 453*FLEN/8, x7, x1, x2) + +inst_177: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x28f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0a4 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e8f; op2val:0x78a4; +op3val:0xfbff; valaddr_reg:x5; val_offset:456*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 456*FLEN/8, x7, x1, x2) + +inst_178: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x38f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b2d; op2val:0x7b8f; +op3val:0xfbff; valaddr_reg:x5; val_offset:459*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 459*FLEN/8, x7, x1, x2) + +inst_179: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x10d and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3c4 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x750d; op2val:0x73c4; +op3val:0xfbff; valaddr_reg:x5; val_offset:462*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 462*FLEN/8, x7, x1, x2) + +inst_180: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a7 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2b6 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74a7; op2val:0x76b6; +op3val:0xfbff; valaddr_reg:x5; val_offset:465*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 465*FLEN/8, x7, x1, x2) + +inst_181: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x03a and fs2 == 0 and fe2 == 0x19 and fm2 == 0x142 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x703a; op2val:0x6542; +op3val:0xfbff; valaddr_reg:x5; val_offset:468*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 468*FLEN/8, x7, x1, x2) + +inst_182: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0ae and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2b8 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6cae; op2val:0x76b8; +op3val:0xfbff; valaddr_reg:x5; val_offset:471*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 471*FLEN/8, x7, x1, x2) + +inst_183: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ec and fs2 == 0 and fe2 == 0x1c and fm2 == 0x08d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79ec; op2val:0x708d; +op3val:0xfbff; valaddr_reg:x5; val_offset:474*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 474*FLEN/8, x7, x1, x2) + +inst_184: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x117 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x168 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7917; op2val:0x6d68; +op3val:0xfbff; valaddr_reg:x5; val_offset:477*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 477*FLEN/8, x7, x1, x2) + +inst_185: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1e7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x396 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75e7; op2val:0x7b96; +op3val:0xfbff; valaddr_reg:x5; val_offset:480*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 480*FLEN/8, x7, x1, x2) + +inst_186: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x288 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2ac and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7688; op2val:0x76ac; +op3val:0xfbff; valaddr_reg:x5; val_offset:483*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 483*FLEN/8, x7, x1, x2) + +inst_187: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x120 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x286 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7520; op2val:0x7286; +op3val:0xfbff; valaddr_reg:x5; val_offset:486*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 486*FLEN/8, x7, x1, x2) + +inst_188: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x387 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x399 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7787; op2val:0x7b99; +op3val:0xfbff; valaddr_reg:x5; val_offset:489*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 489*FLEN/8, x7, x1, x2) + +inst_189: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x06d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x076 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x746d; op2val:0x7876; +op3val:0xfbff; valaddr_reg:x5; val_offset:492*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 492*FLEN/8, x7, x1, x2) + +inst_190: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25c and fs2 == 0 and fe2 == 0x1d and fm2 == 0x322 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5c; op2val:0x7722; +op3val:0xfbff; valaddr_reg:x5; val_offset:495*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 495*FLEN/8, x7, x1, x2) + +inst_191: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x223 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2e7 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a23; op2val:0x76e7; +op3val:0xfbff; valaddr_reg:x5; val_offset:498*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 498*FLEN/8, x7, x1, x2) + +inst_192: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x340 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x37e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7740; op2val:0x7b7e; +op3val:0xfbff; valaddr_reg:x5; val_offset:501*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 501*FLEN/8, x7, x1, x2) + +inst_193: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x365 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x118 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7765; op2val:0x7918; +op3val:0xfbff; valaddr_reg:x5; val_offset:504*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 504*FLEN/8, x7, x1, x2) + +inst_194: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x283 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x38b and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7283; op2val:0x578b; +op3val:0xfbff; valaddr_reg:x5; val_offset:507*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 507*FLEN/8, x7, x1, x2) + +inst_195: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0f2 and fs2 == 0 and fe2 == 0x17 and fm2 == 0x3f5 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78f2; op2val:0x5ff5; +op3val:0xfbff; valaddr_reg:x5; val_offset:510*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 510*FLEN/8, x7, x1, x2) + +inst_196: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x225 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x107 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a25; op2val:0x7907; +op3val:0xfbff; valaddr_reg:x5; val_offset:513*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 513*FLEN/8, x7, x1, x2) + +inst_197: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1a5 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70ff; op2val:0x79a5; +op3val:0xfbff; valaddr_reg:x5; val_offset:516*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 516*FLEN/8, x7, x1, x2) + +inst_198: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x16c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x213 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x796c; op2val:0x7a13; +op3val:0xfbff; valaddr_reg:x5; val_offset:519*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 519*FLEN/8, x7, x1, x2) + +inst_199: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x217 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x07a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a17; op2val:0x747a; +op3val:0xfbff; valaddr_reg:x5; val_offset:522*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 522*FLEN/8, x7, x1, x2) + +inst_200: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ac0; op2val:0x7a0f; +op3val:0xfbff; valaddr_reg:x5; val_offset:525*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 525*FLEN/8, x7, x1, x2) + +inst_201: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x024 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x016 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7424; op2val:0x7816; +op3val:0xfbff; valaddr_reg:x5; val_offset:528*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 528*FLEN/8, x7, x1, x2) + +inst_202: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0aa and fs2 == 0 and fe2 == 0x1e and fm2 == 0x342 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78aa; op2val:0x7b42; +op3val:0xfbff; valaddr_reg:x5; val_offset:531*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 531*FLEN/8, x7, x1, x2) + +inst_203: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x32f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79d5; op2val:0x7b2f; +op3val:0xfbff; valaddr_reg:x5; val_offset:534*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 534*FLEN/8, x7, x1, x2) + +inst_204: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x38c and fs2 == 0 and fe2 == 0x1b and fm2 == 0x271 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x778c; op2val:0x6e71; +op3val:0xfbff; valaddr_reg:x5; val_offset:537*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 537*FLEN/8, x7, x1, x2) + +inst_205: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x34c and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e2; op2val:0x7b4c; +op3val:0xfbff; valaddr_reg:x5; val_offset:540*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 540*FLEN/8, x7, x1, x2) + +inst_206: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2eb and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77a0; op2val:0x7aeb; +op3val:0xfbff; valaddr_reg:x5; val_offset:543*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 543*FLEN/8, x7, x1, x2) + +inst_207: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x063 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a6f; op2val:0x7863; +op3val:0xfbff; valaddr_reg:x5; val_offset:546*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 546*FLEN/8, x7, x1, x2) + +inst_208: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3cd and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aef; op2val:0x73cd; +op3val:0xfbff; valaddr_reg:x5; val_offset:549*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 549*FLEN/8, x7, x1, x2) + +inst_209: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x329 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x125 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7729; op2val:0x6d25; +op3val:0xfbff; valaddr_reg:x5; val_offset:552*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 552*FLEN/8, x7, x1, x2) + +inst_210: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ca and fs2 == 0 and fe2 == 0x1e and fm2 == 0x328 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aca; op2val:0x7b28; +op3val:0xfbff; valaddr_reg:x5; val_offset:555*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 555*FLEN/8, x7, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(31424,32,FLEN) +NAN_BOXED(31424,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29732,32,FLEN) +NAN_BOXED(30742,32,FLEN) +NAN_BOXED(29732,16,FLEN) +NAN_BOXED(31300,32,FLEN) +NAN_BOXED(29913,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30890,32,FLEN) +NAN_BOXED(30890,32,FLEN) +NAN_BOXED(30890,16,FLEN) +NAN_BOXED(29825,32,FLEN) +NAN_BOXED(31243,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29697,32,FLEN) +NAN_BOXED(31558,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31354,32,FLEN) +NAN_BOXED(31542,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31189,32,FLEN) +NAN_BOXED(31535,32,FLEN) +NAN_BOXED(31535,16,FLEN) +NAN_BOXED(30604,32,FLEN) +NAN_BOXED(28273,32,FLEN) +NAN_BOXED(30604,16,FLEN) +NAN_BOXED(30946,32,FLEN) +NAN_BOXED(30946,32,FLEN) +NAN_BOXED(30946,16,FLEN) +NAN_BOXED(30624,32,FLEN) +NAN_BOXED(31467,32,FLEN) +NAN_BOXED(31467,16,FLEN) +test_dataset_1: +NAN_BOXED(31343,32,FLEN) +NAN_BOXED(31343,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31169,32,FLEN) +NAN_BOXED(30304,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31063,32,FLEN) +NAN_BOXED(21677,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31471,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31477,32,FLEN) +NAN_BOXED(29212,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29601,32,FLEN) +NAN_BOXED(31676,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30505,32,FLEN) +NAN_BOXED(27941,32,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(30735,32,FLEN) +NAN_BOXED(31605,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30824,32,FLEN) +NAN_BOXED(31142,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31363,32,FLEN) +NAN_BOXED(30801,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30930,32,FLEN) +NAN_BOXED(30898,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30916,32,FLEN) +NAN_BOXED(30247,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29860,32,FLEN) +NAN_BOXED(29198,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30950,32,FLEN) +NAN_BOXED(31040,32,FLEN) +NAN_BOXED(64511,16,FLEN) +test_dataset_2: +NAN_BOXED(28094,16,FLEN) +NAN_BOXED(31246,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31586,16,FLEN) +NAN_BOXED(31420,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31585,16,FLEN) +NAN_BOXED(30802,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31139,16,FLEN) +NAN_BOXED(29800,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31528,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31640,16,FLEN) +NAN_BOXED(30882,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31047,16,FLEN) +NAN_BOXED(31735,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31319,16,FLEN) +NAN_BOXED(27972,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30663,16,FLEN) +NAN_BOXED(30985,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29637,16,FLEN) +NAN_BOXED(31193,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29453,16,FLEN) +NAN_BOXED(31322,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31366,16,FLEN) +NAN_BOXED(28271,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31124,16,FLEN) +NAN_BOXED(27081,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31558,16,FLEN) +NAN_BOXED(30789,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(26324,16,FLEN) +NAN_BOXED(30995,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30874,16,FLEN) +NAN_BOXED(30273,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31703,16,FLEN) +NAN_BOXED(26791,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31663,16,FLEN) +NAN_BOXED(29162,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29372,16,FLEN) +NAN_BOXED(31335,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(26068,16,FLEN) +NAN_BOXED(30414,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29736,16,FLEN) +NAN_BOXED(29456,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30106,16,FLEN) +NAN_BOXED(29124,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(26889,16,FLEN) +NAN_BOXED(28276,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29280,16,FLEN) +NAN_BOXED(30139,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31412,16,FLEN) +NAN_BOXED(31576,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31072,16,FLEN) +NAN_BOXED(31674,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31080,16,FLEN) +NAN_BOXED(31426,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29698,16,FLEN) +NAN_BOXED(30917,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29079,16,FLEN) +NAN_BOXED(30602,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30860,16,FLEN) +NAN_BOXED(30737,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30134,16,FLEN) +NAN_BOXED(31410,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30843,16,FLEN) +NAN_BOXED(25181,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30047,16,FLEN) +NAN_BOXED(27096,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29614,16,FLEN) +NAN_BOXED(31647,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29850,16,FLEN) +NAN_BOXED(30142,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30993,16,FLEN) +NAN_BOXED(30967,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30260,16,FLEN) +NAN_BOXED(30368,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(22077,16,FLEN) +NAN_BOXED(29222,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29608,16,FLEN) +NAN_BOXED(31000,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31487,16,FLEN) +NAN_BOXED(30859,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30318,16,FLEN) +NAN_BOXED(31132,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31051,16,FLEN) +NAN_BOXED(27132,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29733,16,FLEN) +NAN_BOXED(28939,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30666,16,FLEN) +NAN_BOXED(30845,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31505,16,FLEN) +NAN_BOXED(30696,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30583,16,FLEN) +NAN_BOXED(31352,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31359,16,FLEN) +NAN_BOXED(29187,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30991,16,FLEN) +NAN_BOXED(27990,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31716,16,FLEN) +NAN_BOXED(30317,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29966,16,FLEN) +NAN_BOXED(29396,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(22739,16,FLEN) +NAN_BOXED(31380,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28225,16,FLEN) +NAN_BOXED(28571,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31484,16,FLEN) +NAN_BOXED(29818,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28264,16,FLEN) +NAN_BOXED(31444,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(27956,16,FLEN) +NAN_BOXED(29796,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31317,16,FLEN) +NAN_BOXED(31459,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30762,16,FLEN) +NAN_BOXED(31028,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31480,16,FLEN) +NAN_BOXED(29811,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(26931,16,FLEN) +NAN_BOXED(31090,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31633,16,FLEN) +NAN_BOXED(31616,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(26975,16,FLEN) +NAN_BOXED(31229,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31037,16,FLEN) +NAN_BOXED(31154,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31006,16,FLEN) +NAN_BOXED(30196,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29349,16,FLEN) +NAN_BOXED(30897,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28884,16,FLEN) +NAN_BOXED(30036,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31166,16,FLEN) +NAN_BOXED(30056,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(26949,16,FLEN) +NAN_BOXED(28989,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29857,16,FLEN) +NAN_BOXED(30288,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29873,16,FLEN) +NAN_BOXED(30629,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(27180,16,FLEN) +NAN_BOXED(29118,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(27784,16,FLEN) +NAN_BOXED(30322,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30369,16,FLEN) +NAN_BOXED(28251,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30612,16,FLEN) +NAN_BOXED(31417,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30078,16,FLEN) +NAN_BOXED(30633,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30418,16,FLEN) +NAN_BOXED(29907,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31526,16,FLEN) +NAN_BOXED(31578,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30209,16,FLEN) +NAN_BOXED(31690,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(27702,16,FLEN) +NAN_BOXED(28010,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(27602,16,FLEN) +NAN_BOXED(24580,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30758,16,FLEN) +NAN_BOXED(30508,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30893,16,FLEN) +NAN_BOXED(31086,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30179,16,FLEN) +NAN_BOXED(31719,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31286,16,FLEN) +NAN_BOXED(30437,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(27669,16,FLEN) +NAN_BOXED(31463,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31544,16,FLEN) +NAN_BOXED(30520,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28571,16,FLEN) +NAN_BOXED(30301,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(26978,16,FLEN) +NAN_BOXED(31636,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28846,16,FLEN) +NAN_BOXED(29268,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30814,16,FLEN) +NAN_BOXED(28887,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31708,16,FLEN) +NAN_BOXED(28863,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31087,16,FLEN) +NAN_BOXED(31492,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31573,16,FLEN) +NAN_BOXED(29992,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30713,16,FLEN) +NAN_BOXED(31067,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30944,16,FLEN) +NAN_BOXED(29439,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31666,16,FLEN) +NAN_BOXED(31536,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(26761,16,FLEN) +NAN_BOXED(28862,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31301,16,FLEN) +NAN_BOXED(31420,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31166,16,FLEN) +NAN_BOXED(31348,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28010,16,FLEN) +NAN_BOXED(31474,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29491,16,FLEN) +NAN_BOXED(26930,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31423,16,FLEN) +NAN_BOXED(30025,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28866,16,FLEN) +NAN_BOXED(31039,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30729,16,FLEN) +NAN_BOXED(31540,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30870,16,FLEN) +NAN_BOXED(31085,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31247,16,FLEN) +NAN_BOXED(31723,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31550,16,FLEN) +NAN_BOXED(29335,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30921,16,FLEN) +NAN_BOXED(31386,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31315,16,FLEN) +NAN_BOXED(30262,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31438,16,FLEN) +NAN_BOXED(31329,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(19426,16,FLEN) +NAN_BOXED(29137,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29713,16,FLEN) +NAN_BOXED(27698,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31626,16,FLEN) +NAN_BOXED(29911,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31354,16,FLEN) +NAN_BOXED(27639,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28690,16,FLEN) +NAN_BOXED(29847,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(27418,16,FLEN) +NAN_BOXED(26776,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30685,16,FLEN) +NAN_BOXED(31463,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31074,16,FLEN) +NAN_BOXED(28887,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30355,16,FLEN) +NAN_BOXED(30948,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(27140,16,FLEN) +NAN_BOXED(30599,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(26663,16,FLEN) +NAN_BOXED(30959,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28348,16,FLEN) +NAN_BOXED(30820,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30241,16,FLEN) +NAN_BOXED(31285,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31499,16,FLEN) +NAN_BOXED(30944,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30990,16,FLEN) +NAN_BOXED(30055,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31093,16,FLEN) +NAN_BOXED(30969,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28688,16,FLEN) +NAN_BOXED(31562,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31572,16,FLEN) +NAN_BOXED(31482,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31354,16,FLEN) +NAN_BOXED(30758,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29196,16,FLEN) +NAN_BOXED(31296,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31244,16,FLEN) +NAN_BOXED(30536,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(27857,16,FLEN) +NAN_BOXED(27062,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30662,16,FLEN) +NAN_BOXED(31540,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31060,16,FLEN) +NAN_BOXED(30866,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28154,16,FLEN) +NAN_BOXED(31373,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31291,16,FLEN) +NAN_BOXED(31125,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29921,16,FLEN) +NAN_BOXED(28481,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30854,16,FLEN) +NAN_BOXED(31585,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30373,16,FLEN) +NAN_BOXED(28248,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31199,16,FLEN) +NAN_BOXED(26587,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31101,16,FLEN) +NAN_BOXED(26549,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31665,16,FLEN) +NAN_BOXED(31175,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(27775,16,FLEN) +NAN_BOXED(30142,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30096,16,FLEN) +NAN_BOXED(24857,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31372,16,FLEN) +NAN_BOXED(27778,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29350,16,FLEN) +NAN_BOXED(29324,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31616,16,FLEN) +NAN_BOXED(28641,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30183,16,FLEN) +NAN_BOXED(26190,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31454,16,FLEN) +NAN_BOXED(29179,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30082,16,FLEN) +NAN_BOXED(31659,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31674,16,FLEN) +NAN_BOXED(30155,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29870,16,FLEN) +NAN_BOXED(31614,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30997,16,FLEN) +NAN_BOXED(29154,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28303,16,FLEN) +NAN_BOXED(30884,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31533,16,FLEN) +NAN_BOXED(31631,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29965,16,FLEN) +NAN_BOXED(29636,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29863,16,FLEN) +NAN_BOXED(30390,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28730,16,FLEN) +NAN_BOXED(25922,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(27822,16,FLEN) +NAN_BOXED(30392,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31212,16,FLEN) +NAN_BOXED(28813,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30999,16,FLEN) +NAN_BOXED(28008,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30183,16,FLEN) +NAN_BOXED(31638,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30344,16,FLEN) +NAN_BOXED(30380,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29984,16,FLEN) +NAN_BOXED(29318,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30599,16,FLEN) +NAN_BOXED(31641,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29805,16,FLEN) +NAN_BOXED(30838,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31324,16,FLEN) +NAN_BOXED(30498,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31267,16,FLEN) +NAN_BOXED(30439,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30528,16,FLEN) +NAN_BOXED(31614,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30565,16,FLEN) +NAN_BOXED(31000,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29315,16,FLEN) +NAN_BOXED(22411,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30962,16,FLEN) +NAN_BOXED(24565,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31269,16,FLEN) +NAN_BOXED(30983,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28927,16,FLEN) +NAN_BOXED(31141,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31084,16,FLEN) +NAN_BOXED(31251,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31255,16,FLEN) +NAN_BOXED(29818,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31424,16,FLEN) +NAN_BOXED(31247,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29732,16,FLEN) +NAN_BOXED(30742,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30890,16,FLEN) +NAN_BOXED(31554,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31189,16,FLEN) +NAN_BOXED(31535,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30604,16,FLEN) +NAN_BOXED(28273,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30946,16,FLEN) +NAN_BOXED(31564,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30624,16,FLEN) +NAN_BOXED(31467,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31343,16,FLEN) +NAN_BOXED(30819,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31471,16,FLEN) +NAN_BOXED(29645,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30505,16,FLEN) +NAN_BOXED(27941,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31434,16,FLEN) +NAN_BOXED(31528,16,FLEN) +NAN_BOXED(64511,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x4_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x4_1: + .fill 26*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x6_0: + .fill 32*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_0: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 108*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fmadd_b18-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fmadd_b18-01.S new file mode 100644 index 000000000..e6ce08ddc --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fmadd_b18-01.S @@ -0,0 +1,3034 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 04:10:09 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fmadd.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fmadd.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fmadd_b18 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fmadd_b18) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x4,test_dataset_0) +RVTEST_SIGBASE(x3,signature_x3_1) + +inst_0: +// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==x2, rs2==x2, rs3==x24, rd==x11,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x2; op2:x2; op3:x24; dest:x11; op1val:0x7ac0; op2val:0x7ac0; +op3val:0x7bff; valaddr_reg:x4; val_offset:0*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x11, x2, x2, x24, dyn, 0, 0, x4, 0*FLEN/8, x12, x3, x10) + +inst_1: +// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==x5, rs2==x27, rs3==x5, rd==x20,fs1 == 0 and fe1 == 0x1e and fm1 == 0x20f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x5; op2:x27; op3:x5; dest:x20; op1val:0x7a0f; op2val:0x0; +op3val:0x7a0f; valaddr_reg:x4; val_offset:3*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x20, x5, x27, x5, dyn, 0, 0, x4, 3*FLEN/8, x12, x3, x10) + +inst_2: +// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==x21, rs2==x25, rs3==x16, rd==x21,fs1 == 0 and fe1 == 0x1d and fm1 == 0x2b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x21; op2:x25; op3:x16; dest:x21; op1val:0x76b9; op2val:0x0; +op3val:0x7bff; valaddr_reg:x4; val_offset:6*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x21, x21, x25, x16, dyn, 0, 0, x4, 6*FLEN/8, x12, x3, x10) + +inst_3: +// rs1 == rs2 == rs3 != rd, rs1==x14, rs2==x14, rs3==x14, rd==x0,fs1 == 0 and fe1 == 0x1d and fm1 == 0x024 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x14; op2:x14; op3:x14; dest:x0; op1val:0x7424; op2val:0x7424; +op3val:0x7424; valaddr_reg:x4; val_offset:9*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x0, x14, x14, x14, dyn, 0, 0, x4, 9*FLEN/8, x12, x3, x10) + +inst_4: +// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==x8, rs2==x20, rs3==x17, rd==x17,fs1 == 0 and fe1 == 0x1e and fm1 == 0x016 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x8; op2:x20; op3:x17; dest:x17; op1val:0x7816; op2val:0x0; +op3val:0x7bff; valaddr_reg:x4; val_offset:12*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x17, x8, x20, x17, dyn, 0, 0, x4, 12*FLEN/8, x12, x3, x10) + +inst_5: +// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==x1, rs2==x19, rs3==x13, rd==x19,fs1 == 0 and fe1 == 0x1d and fm1 == 0x279 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x1; op2:x19; op3:x13; dest:x19; op1val:0x7679; op2val:0x0; +op3val:0x7bff; valaddr_reg:x4; val_offset:15*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x19, x1, x19, x13, dyn, 0, 0, x4, 15*FLEN/8, x12, x3, x10) + +inst_6: +// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==x9, rs2==x13, rs3==x23, rd==x5,fs1 == 0 and fe1 == 0x1e and fm1 == 0x244 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x9; op2:x13; op3:x23; dest:x5; op1val:0x7a44; op2val:0x0; +op3val:0x7bff; valaddr_reg:x4; val_offset:18*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x5, x9, x13, x23, dyn, 0, 0, x4, 18*FLEN/8, x12, x3, x10) + +inst_7: +// rd == rs2 == rs3 != rs1, rs1==x29, rs2==x31, rs3==x31, rd==x31,fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x29; op2:x31; op3:x31; dest:x31; op1val:0x74d9; op2val:0x8000; +op3val:0x8000; valaddr_reg:x4; val_offset:21*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x29, x31, x31, dyn, 0, 0, x4, 21*FLEN/8, x12, x3, x10) + +inst_8: +// rs1 == rd == rs3 != rs2, rs1==x26, rs2==x6, rs3==x26, rd==x26,fs1 == 0 and fe1 == 0x1d and fm1 == 0x39f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x26; op2:x6; op3:x26; dest:x26; op1val:0x779f; op2val:0x8000; +op3val:0x779f; valaddr_reg:x4; val_offset:24*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x26, x26, x6, x26, dyn, 0, 0, x4, 24*FLEN/8, x12, x3, x10) + +inst_9: +// rs1 == rs2 == rs3 == rd, rs1==x28, rs2==x28, rs3==x28, rd==x28,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x28; op2:x28; op3:x28; dest:x28; op1val:0x78aa; op2val:0x78aa; +op3val:0x78aa; valaddr_reg:x4; val_offset:27*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x28, x28, x28, x28, dyn, 0, 0, x4, 27*FLEN/8, x12, x3, x10) + +inst_10: +// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==x17, rs2==x22, rs3==x22, rd==x8,fs1 == 0 and fe1 == 0x1e and fm1 == 0x342 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x17; op2:x22; op3:x22; dest:x8; op1val:0x7b42; op2val:0x8000; +op3val:0x8000; valaddr_reg:x4; val_offset:30*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x8, x17, x22, x22, dyn, 0, 0, x4, 30*FLEN/8, x12, x3, x10) + +inst_11: +// rs1 == rs2 == rd != rs3, rs1==x23, rs2==x23, rs3==x29, rd==x23,fs1 == 0 and fe1 == 0x1e and fm1 == 0x009 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x23; op2:x23; op3:x29; dest:x23; op1val:0x7809; op2val:0x7809; +op3val:0x7bff; valaddr_reg:x4; val_offset:33*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x23, x23, x23, x29, dyn, 0, 0, x4, 33*FLEN/8, x12, x3, x10) + +inst_12: +// rs1==x7, rs2==x1, rs3==x0, rd==x13,fs1 == 0 and fe1 == 0x1d and fm1 == 0x081 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x7; op2:x1; op3:x0; dest:x13; op1val:0x7481; op2val:0x8000; +op3val:0x0; valaddr_reg:x4; val_offset:36*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x13, x7, x1, x0, dyn, 0, 0, x4, 36*FLEN/8, x12, x3, x10) +RVTEST_VALBASEUPD(x13,test_dataset_1) + +inst_13: +// rs1==x20, rs2==x17, rs3==x27, rd==x4,fs1 == 0 and fe1 == 0x1e and fm1 == 0x20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x20; op2:x17; op3:x27; dest:x4; op1val:0x7a0b; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x13; val_offset:0*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x4, x20, x17, x27, dyn, 0, 0, x13, 0*FLEN/8, x14, x3, x10) + +inst_14: +// rs1==x25, rs2==x16, rs3==x18, rd==x7,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0f1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x25; op2:x16; op3:x18; dest:x7; op1val:0x78f1; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x13; val_offset:3*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x7, x25, x16, x18, dyn, 0, 0, x13, 3*FLEN/8, x14, x3, x10) + +inst_15: +// rs1==x15, rs2==x4, rs3==x21, rd==x6,fs1 == 0 and fe1 == 0x1d and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x15; op2:x4; op3:x21; dest:x6; op1val:0x7401; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x13; val_offset:6*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x6, x15, x4, x21, dyn, 0, 0, x13, 6*FLEN/8, x14, x3, x1) +RVTEST_SIGBASE(x2,signature_x2_0) + +inst_16: +// rs1==x30, rs2==x21, rs3==x20, rd==x27,fs1 == 0 and fe1 == 0x1e and fm1 == 0x346 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x21; op3:x20; dest:x27; op1val:0x7b46; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x13; val_offset:9*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x27, x30, x21, x20, dyn, 0, 0, x13, 9*FLEN/8, x14, x2, x1) + +inst_17: +// rs1==x22, rs2==x9, rs3==x12, rd==x29,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x22; op2:x9; op3:x12; dest:x29; op1val:0x7bdb; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x13; val_offset:12*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x29, x22, x9, x12, dyn, 0, 0, x13, 12*FLEN/8, x14, x2, x1) + +inst_18: +// rs1==x18, rs2==x7, rs3==x25, rd==x30,fs1 == 0 and fe1 == 0x1e and fm1 == 0x27a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x18; op2:x7; op3:x25; dest:x30; op1val:0x7a7a; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x13; val_offset:15*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x30, x18, x7, x25, dyn, 0, 0, x13, 15*FLEN/8, x14, x2, x1) + +inst_19: +// rs1==x24, rs2==x30, rs3==x7, rd==x12,fs1 == 0 and fe1 == 0x1e and fm1 == 0x336 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x24; op2:x30; op3:x7; dest:x12; op1val:0x7b36; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x13; val_offset:18*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x12, x24, x30, x7, dyn, 0, 0, x13, 18*FLEN/8, x14, x2, x1) + +inst_20: +// rs1==x12, rs2==x18, rs3==x10, rd==x15,fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x12; op2:x18; op3:x10; dest:x15; op1val:0x74f5; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x13; val_offset:21*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x15, x12, x18, x10, dyn, 0, 0, x13, 21*FLEN/8, x14, x2, x1) + +inst_21: +// rs1==x11, rs2==x5, rs3==x30, rd==x24,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x11; op2:x5; op3:x30; dest:x24; op1val:0x79d5; op2val:0x0; +op3val:0x7bff; valaddr_reg:x13; val_offset:24*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x24, x11, x5, x30, dyn, 0, 0, x13, 24*FLEN/8, x14, x2, x1) + +inst_22: +// rs1==x0, rs2==x8, rs3==x11, rd==x10,fs1 == 0 and fe1 == 0x1e and fm1 == 0x32f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x0; op2:x8; op3:x11; dest:x10; op1val:0x0; op2val:0x0; +op3val:0x7bff; valaddr_reg:x13; val_offset:27*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x10, x0, x8, x11, dyn, 0, 0, x13, 27*FLEN/8, x14, x2, x1) +RVTEST_VALBASEUPD(x5,test_dataset_2) + +inst_23: +// rs1==x13, rs2==x0, rs3==x19, rd==x25,fs1 == 0 and fe1 == 0x1e and fm1 == 0x178 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x13; op2:x0; op3:x19; dest:x25; op1val:0x7978; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:0*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x25, x13, x0, x19, dyn, 0, 0, x5, 0*FLEN/8, x7, x2, x1) + +inst_24: +// rs1==x10, rs2==x12, rs3==x4, rd==x9,fs1 == 0 and fe1 == 0x1d and fm1 == 0x38c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x10; op2:x12; op3:x4; dest:x9; op1val:0x778c; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:3*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x9, x10, x12, x4, dyn, 0, 0, x5, 3*FLEN/8, x7, x2, x1) + +inst_25: +// rs1==x4, rs2==x3, rs3==x6, rd==x14,fs1 == 0 and fe1 == 0x1b and fm1 == 0x271 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x4; op2:x3; op3:x6; dest:x14; op1val:0x6e71; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:6*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x14, x4, x3, x6, dyn, 0, 0, x5, 6*FLEN/8, x7, x2, x1) + +inst_26: +// rs1==x3, rs2==x26, rs3==x2, rd==x16,fs1 == 0 and fe1 == 0x1d and fm1 == 0x2f1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x3; op2:x26; op3:x2; dest:x16; op1val:0x76f1; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:9*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x16, x3, x26, x2, dyn, 0, 0, x5, 9*FLEN/8, x7, x2, x1) + +inst_27: +// rs1==x31, rs2==x24, rs3==x15, rd==x18,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x31; op2:x24; op3:x15; dest:x18; op1val:0x78e2; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:12*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x18, x31, x24, x15, dyn, 0, 0, x5, 12*FLEN/8, x7, x2, x1) + +inst_28: +// rs1==x16, rs2==x29, rs3==x1, rd==x22,fs1 == 0 and fe1 == 0x1e and fm1 == 0x34c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x16; op2:x29; op3:x1; dest:x22; op1val:0x7b4c; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:15*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x22, x16, x29, x1, dyn, 0, 0, x5, 15*FLEN/8, x7, x2, x4) + +inst_29: +// rs1==x19, rs2==x11, rs3==x3, rd==x1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ba and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x19; op2:x11; op3:x3; dest:x1; op1val:0x7bba; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:18*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x1, x19, x11, x3, dyn, 0, 0, x5, 18*FLEN/8, x7, x2, x4) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_30: +// rs1==x6, rs2==x15, rs3==x9, rd==x3,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x6; op2:x15; op3:x9; dest:x3; op1val:0x77a0; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:21*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x3, x6, x15, x9, dyn, 0, 0, x5, 21*FLEN/8, x7, x1, x4) + +inst_31: +// rs1==x27, rs2==x10, rs3==x8, rd==x2,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2eb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x27; op2:x10; op3:x8; dest:x2; op1val:0x7aeb; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:24*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x2, x27, x10, x8, dyn, 0, 0, x5, 24*FLEN/8, x7, x1, x4) + +inst_32: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x02a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x742a; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:27*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 27*FLEN/8, x7, x1, x4) + +inst_33: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a6f; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:30*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 30*FLEN/8, x7, x1, x4) + +inst_34: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x063 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7863; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:33*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 33*FLEN/8, x7, x1, x4) + +inst_35: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x331 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6331; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:36*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 36*FLEN/8, x7, x1, x4) + +inst_36: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79c1; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:39*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 39*FLEN/8, x7, x1, x4) + +inst_37: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x260 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7660; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:42*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 42*FLEN/8, x7, x1, x4) + +inst_38: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x298 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a98; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:45*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 45*FLEN/8, x7, x1, x4) + +inst_39: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x157 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7957; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:48*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 48*FLEN/8, x7, x1, x4) + +inst_40: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x0bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x54bd; op2val:0x8001; +op3val:0x7bff; valaddr_reg:x5; val_offset:51*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 51*FLEN/8, x7, x1, x4) + +inst_41: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3e4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77e4; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:54*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 54*FLEN/8, x7, x1, x4) + +inst_42: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aef; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:57*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 57*FLEN/8, x7, x1, x4) + +inst_43: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3cd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73cd; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:60*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 60*FLEN/8, x7, x1, x4) + +inst_44: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x133 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7533; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:63*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 63*FLEN/8, x7, x1, x4) + +inst_45: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7af5; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:66*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 66*FLEN/8, x7, x1, x4) + +inst_46: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x21c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x721c; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:69*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 69*FLEN/8, x7, x1, x4) + +inst_47: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x089 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7889; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:72*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 72*FLEN/8, x7, x1, x4) + +inst_48: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3a1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73a1; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:75*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 75*FLEN/8, x7, x1, x4) + +inst_49: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3bc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bbc; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:78*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 78*FLEN/8, x7, x1, x4) + +inst_50: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a6c; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:81*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 81*FLEN/8, x7, x1, x4) + +inst_51: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x32a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x772a; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:84*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 84*FLEN/8, x7, x1, x4) + +inst_52: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x125 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d25; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:87*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 87*FLEN/8, x7, x1, x4) + +inst_53: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x11e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x751e; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:90*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 90*FLEN/8, x7, x1, x4) + +inst_54: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x780f; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:93*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 93*FLEN/8, x7, x1, x4) + +inst_55: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x375 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b75; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:96*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 96*FLEN/8, x7, x1, x4) + +inst_56: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2fa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6efa; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:99*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 99*FLEN/8, x7, x1, x4) + +inst_57: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x068 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7868; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:102*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 102*FLEN/8, x7, x1, x4) + +inst_58: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79a6; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:105*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 105*FLEN/8, x7, x1, x4) + +inst_59: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x060 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7860; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:108*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 108*FLEN/8, x7, x1, x4) + +inst_60: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x283 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a83; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:111*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 111*FLEN/8, x7, x1, x4) + +inst_61: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x051 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7851; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:114*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 114*FLEN/8, x7, x1, x4) + +inst_62: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bb4; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:117*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 117*FLEN/8, x7, x1, x4) + +inst_63: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78d2; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:120*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 120*FLEN/8, x7, x1, x4) + +inst_64: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78b2; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:123*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 123*FLEN/8, x7, x1, x4) + +inst_65: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x771d; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:126*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 126*FLEN/8, x7, x1, x4) + +inst_66: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78c4; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:129*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 129*FLEN/8, x7, x1, x4) + +inst_67: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x227 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7627; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:132*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 132*FLEN/8, x7, x1, x4) + +inst_68: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x789a; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:135*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 135*FLEN/8, x7, x1, x4) + +inst_69: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74a4; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:138*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 138*FLEN/8, x7, x1, x4) + +inst_70: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x20e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x720e; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:141*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 141*FLEN/8, x7, x1, x4) + +inst_71: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1f9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71f9; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:144*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 144*FLEN/8, x7, x1, x4) + +inst_72: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e6; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:147*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 147*FLEN/8, x7, x1, x4) + +inst_73: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x140 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7940; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:150*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 150*FLEN/8, x7, x1, x4) + +inst_74: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x39e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x779e; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:153*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 153*FLEN/8, x7, x1, x4) + +inst_75: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1bf and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dbf; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:156*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 156*FLEN/8, x7, x1, x4) + +inst_76: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a0e; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:159*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 159*FLEN/8, x7, x1, x4) + +inst_77: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x302 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b02; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:162*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 162*FLEN/8, x7, x1, x4) + +inst_78: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x362 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b62; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:165*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 165*FLEN/8, x7, x1, x4) + +inst_79: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2bc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7abc; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:168*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 168*FLEN/8, x7, x1, x4) + +inst_80: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b2e; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:171*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 171*FLEN/8, x7, x1, x4) + +inst_81: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x361 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b61; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:174*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 174*FLEN/8, x7, x1, x4) + +inst_82: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x052 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7852; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:177*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 177*FLEN/8, x7, x1, x4) + +inst_83: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x242 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7642; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:180*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 180*FLEN/8, x7, x1, x4) + +inst_84: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79a3; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:183*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 183*FLEN/8, x7, x1, x4) + +inst_85: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x068 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7468; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:186*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 186*FLEN/8, x7, x1, x4) + +inst_86: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x27d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a7d; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:189*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 189*FLEN/8, x7, x1, x4) + +inst_87: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aca; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:192*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 192*FLEN/8, x7, x1, x4) + +inst_88: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x328 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b28; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:195*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 195*FLEN/8, x7, x1, x4) + +inst_89: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78b7; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:198*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 198*FLEN/8, x7, x1, x4) + +inst_90: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x398 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b98; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:201*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 201*FLEN/8, x7, x1, x4) + +inst_91: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78a2; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:204*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 204*FLEN/8, x7, x1, x4) + +inst_92: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x334 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7734; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:207*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 207*FLEN/8, x7, x1, x4) + +inst_93: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x147 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7947; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:210*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 210*FLEN/8, x7, x1, x4) + +inst_94: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bf7; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:213*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 213*FLEN/8, x7, x1, x4) + +inst_95: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x354 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b54; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:216*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 216*FLEN/8, x7, x1, x4) + +inst_96: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x257 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a57; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:219*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 219*FLEN/8, x7, x1, x4) + +inst_97: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x145 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d45; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:222*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 222*FLEN/8, x7, x1, x4) + +inst_98: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3c7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77c7; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:225*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 225*FLEN/8, x7, x1, x4) + +inst_99: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x109 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7909; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:228*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 228*FLEN/8, x7, x1, x4) + +inst_100: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ac1; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:231*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 231*FLEN/8, x7, x1, x4) + +inst_101: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3c6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73c6; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:234*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 234*FLEN/8, x7, x1, x4) + +inst_102: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79d9; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:237*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 237*FLEN/8, x7, x1, x4) + +inst_103: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x37e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f7e; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:240*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 240*FLEN/8, x7, x1, x4) + +inst_104: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x30d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x730d; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:243*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 243*FLEN/8, x7, x1, x4) + +inst_105: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5a; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:246*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 246*FLEN/8, x7, x1, x4) + +inst_106: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x151 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7551; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:249*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 249*FLEN/8, x7, x1, x4) + +inst_107: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x286 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a86; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:252*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 252*FLEN/8, x7, x1, x4) + +inst_108: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x26f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e6f; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:255*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 255*FLEN/8, x7, x1, x4) + +inst_109: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0ae and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70ae; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:258*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 258*FLEN/8, x7, x1, x4) + +inst_110: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x194 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7994; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:261*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 261*FLEN/8, x7, x1, x4) + +inst_111: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x1c9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x69c9; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:264*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 264*FLEN/8, x7, x1, x4) + +inst_112: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x096 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7896; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:267*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 267*FLEN/8, x7, x1, x4) + +inst_113: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x346 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b46; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:270*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 270*FLEN/8, x7, x1, x4) + +inst_114: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x045 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7845; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:273*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 273*FLEN/8, x7, x1, x4) + +inst_115: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x171 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7971; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:276*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 276*FLEN/8, x7, x1, x4) + +inst_116: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x2d5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x66d5; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:279*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 279*FLEN/8, x7, x1, x4) + +inst_117: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7913; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:282*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 282*FLEN/8, x7, x1, x4) + +inst_118: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78d9; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:285*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 285*FLEN/8, x7, x1, x4) + +inst_119: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x241 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7641; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:288*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 288*FLEN/8, x7, x1, x4) + +inst_120: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75eb; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:291*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 291*FLEN/8, x7, x1, x4) + +inst_121: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd7; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:294*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 294*FLEN/8, x7, x1, x4) + +inst_122: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x0a8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x68a8; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:297*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 297*FLEN/8, x7, x1, x4) + +inst_123: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x18a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x658a; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:300*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 300*FLEN/8, x7, x1, x4) + +inst_124: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3af and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7baf; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:303*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 303*FLEN/8, x7, x1, x4) + +inst_125: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1ea and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71ea; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:306*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 306*FLEN/8, x7, x1, x4) + +inst_126: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3ed and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6fed; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:309*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 309*FLEN/8, x7, x1, x4) + +inst_127: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2bc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72bc; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:312*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 312*FLEN/8, x7, x1, x4) + +inst_128: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x267 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a67; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:315*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 315*FLEN/8, x7, x1, x4) + +inst_129: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b7d; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:318*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 318*FLEN/8, x7, x1, x4) + +inst_130: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x1d5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x65d5; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:321*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 321*FLEN/8, x7, x1, x4) + +inst_131: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2ce and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76ce; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:324*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 324*FLEN/8, x7, x1, x4) + +inst_132: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x27e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e7e; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:327*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 327*FLEN/8, x7, x1, x4) + +inst_133: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x028 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7428; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:330*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 330*FLEN/8, x7, x1, x4) + +inst_134: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x310 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7310; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:333*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 333*FLEN/8, x7, x1, x4) + +inst_135: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x792c; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:336*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 336*FLEN/8, x7, x1, x4) + +inst_136: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x19a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x759a; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:339*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 339*FLEN/8, x7, x1, x4) + +inst_137: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1c4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71c4; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:342*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 342*FLEN/8, x7, x1, x4) + +inst_138: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x006 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7806; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:345*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 345*FLEN/8, x7, x1, x4) + +inst_139: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x10a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x690a; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:348*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 348*FLEN/8, x7, x1, x4) + +inst_140: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x274 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e74; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:351*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 351*FLEN/8, x7, x1, x4) + +inst_141: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7be6; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:354*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 354*FLEN/8, x7, x1, x4) + +inst_142: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x260 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7260; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:357*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 357*FLEN/8, x7, x1, x4) + +inst_143: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1bb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75bb; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:360*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 360*FLEN/8, x7, x1, x4) + +inst_144: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79d9; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:363*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 363*FLEN/8, x7, x1, x4) + +inst_145: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ab4; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:366*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 366*FLEN/8, x7, x1, x4) + +inst_146: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x358 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b58; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:369*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 369*FLEN/8, x7, x1, x4) + +inst_147: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x16b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x716b; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:372*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 372*FLEN/8, x7, x1, x4) + +inst_148: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x160 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7960; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:375*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 375*FLEN/8, x7, x1, x4) + +inst_149: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ba and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bba; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:378*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 378*FLEN/8, x7, x1, x4) + +inst_150: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x36d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6b6d; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:381*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 381*FLEN/8, x7, x1, x4) + +inst_151: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x168 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7968; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:384*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 384*FLEN/8, x7, x1, x4) + +inst_152: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ac2; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:387*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 387*FLEN/8, x7, x1, x4) + +inst_153: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x179 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7579; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:390*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 390*FLEN/8, x7, x1, x4) + +inst_154: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7402; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:393*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 393*FLEN/8, x7, x1, x4) + +inst_155: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78c5; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:396*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 396*FLEN/8, x7, x1, x4) + +inst_156: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x312 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7712; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:399*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 399*FLEN/8, x7, x1, x4) + +inst_157: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x197 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7197; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:402*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 402*FLEN/8, x7, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_158: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x38a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x778a; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:405*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 405*FLEN/8, x7, x1, x4) + +inst_159: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x28e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x768e; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:408*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 408*FLEN/8, x7, x1, x4) + +inst_160: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x08c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x788c; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:411*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 411*FLEN/8, x7, x1, x4) + +inst_161: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x011 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7811; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:414*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 414*FLEN/8, x7, x1, x4) + +inst_162: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0fb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74fb; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:417*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 417*FLEN/8, x7, x1, x4) + +inst_163: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75b6; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:420*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 420*FLEN/8, x7, x1, x4) + +inst_164: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ab2; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:423*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 423*FLEN/8, x7, x1, x4) + +inst_165: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x003 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7403; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:426*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 426*FLEN/8, x7, x1, x4) + +inst_166: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x07b and fs2 == 0 and fe2 == 0x06 and fm2 == 0x076 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x787b; op2val:0x1876; +op3val:0x7bff; valaddr_reg:x5; val_offset:429*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 429*FLEN/8, x7, x1, x4) + +inst_167: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x25f and fs2 == 0 and fe2 == 0x0b and fm2 == 0x247 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x625f; op2val:0x2e47; +op3val:0x7bff; valaddr_reg:x5; val_offset:432*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 432*FLEN/8, x7, x1, x4) + +inst_168: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ee and fs2 == 0 and fe2 == 0x05 and fm2 == 0x2be and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79ee; op2val:0x16be; +op3val:0x7bff; valaddr_reg:x5; val_offset:435*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 435*FLEN/8, x7, x1, x4) + +inst_169: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x15f and fs2 == 0 and fe2 == 0x06 and fm2 == 0x372 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x755f; op2val:0x1b72; +op3val:0x7bff; valaddr_reg:x5; val_offset:438*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 438*FLEN/8, x7, x1, x4) + +inst_170: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x1d9 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x2d6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x69d9; op2val:0x26d6; +op3val:0x7bff; valaddr_reg:x5; val_offset:441*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 441*FLEN/8, x7, x1, x4) + +inst_171: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x07d and fs2 == 0 and fe2 == 0x07 and fm2 == 0x073 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x747d; op2val:0x1c73; +op3val:0x7bff; valaddr_reg:x5; val_offset:444*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 444*FLEN/8, x7, x1, x4) + +inst_172: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3ae and fs2 == 0 and fe2 == 0x07 and fm2 == 0x135 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73ae; op2val:0x1d35; +op3val:0x7bff; valaddr_reg:x5; val_offset:447*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 447*FLEN/8, x7, x1, x4) + +inst_173: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x39f and fs2 == 1 and fe2 == 0x05 and fm2 == 0x13f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b9f; op2val:0x953f; +op3val:0x7bff; valaddr_reg:x5; val_offset:450*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 450*FLEN/8, x7, x1, x4) + +inst_174: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a2 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x319 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75a2; op2val:0x9b19; +op3val:0x7bff; valaddr_reg:x5; val_offset:453*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 453*FLEN/8, x7, x1, x4) + +inst_175: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x09a and fs2 == 1 and fe2 == 0x07 and fm2 == 0x058 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x749a; op2val:0x9c58; +op3val:0x7bff; valaddr_reg:x5; val_offset:456*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 456*FLEN/8, x7, x1, x4) + +inst_176: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1be and fs2 == 1 and fe2 == 0x06 and fm2 == 0x2f6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75be; op2val:0x9af6; +op3val:0x7bff; valaddr_reg:x5; val_offset:459*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 459*FLEN/8, x7, x1, x4) + +inst_177: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x392 and fs2 == 1 and fe2 == 0x05 and fm2 == 0x148 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b92; op2val:0x9548; +op3val:0x7bff; valaddr_reg:x5; val_offset:462*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 462*FLEN/8, x7, x1, x4) + +inst_178: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x111 and fs2 == 1 and fe2 == 0x05 and fm2 == 0x3e4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7911; op2val:0x97e4; +op3val:0x7bff; valaddr_reg:x5; val_offset:465*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 465*FLEN/8, x7, x1, x4) + +inst_179: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0f7 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x006 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78f7; op2val:0x9806; +op3val:0x7bff; valaddr_reg:x5; val_offset:468*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 468*FLEN/8, x7, x1, x4) + +inst_180: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b8 and fs2 == 1 and fe2 == 0x05 and fm2 == 0x2fd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79b8; op2val:0x96fd; +op3val:0x7bff; valaddr_reg:x5; val_offset:471*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 471*FLEN/8, x7, x1, x4) + +inst_181: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x234 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x272 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7634; op2val:0x9a72; +op3val:0x7bff; valaddr_reg:x5; val_offset:474*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 474*FLEN/8, x7, x1, x4) + +inst_182: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a0 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x209 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76a0; op2val:0x9a09; +op3val:0x7bff; valaddr_reg:x5; val_offset:477*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 477*FLEN/8, x7, x1, x4) + +inst_183: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x134 and fs2 == 1 and fe2 == 0x05 and fm2 == 0x3af and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7934; op2val:0x97af; +op3val:0x7bff; valaddr_reg:x5; val_offset:480*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 480*FLEN/8, x7, x1, x4) + +inst_184: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x24d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x258 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x564d; op2val:0xba58; +op3val:0x7bff; valaddr_reg:x5; val_offset:483*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 483*FLEN/8, x7, x1, x4) + +inst_185: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x226 and fs2 == 1 and fe2 == 0x07 and fm2 == 0x280 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7226; op2val:0x9e80; +op3val:0x7bff; valaddr_reg:x5; val_offset:486*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 486*FLEN/8, x7, x1, x4) + +inst_186: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x159 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x37a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7559; op2val:0x9b7a; +op3val:0x7bff; valaddr_reg:x5; val_offset:489*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 489*FLEN/8, x7, x1, x4) + +inst_187: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3a8 and fs2 == 0 and fe2 == 0x07 and fm2 == 0x139 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73a8; op2val:0x1d39; +op3val:0x7bff; valaddr_reg:x5; val_offset:492*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 492*FLEN/8, x7, x1, x4) + +inst_188: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x118 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x3d9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7918; op2val:0x17d9; +op3val:0x7bff; valaddr_reg:x5; val_offset:495*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 495*FLEN/8, x7, x1, x4) + +inst_189: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x20e and fs2 == 0 and fe2 == 0x06 and fm2 == 0x29b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x760e; op2val:0x1a9b; +op3val:0x7bff; valaddr_reg:x5; val_offset:498*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 498*FLEN/8, x7, x1, x4) + +inst_190: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ff and fs2 == 0 and fe2 == 0x05 and fm2 == 0x1b6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aff; op2val:0x15b6; +op3val:0x7bff; valaddr_reg:x5; val_offset:501*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 501*FLEN/8, x7, x1, x4) + +inst_191: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x08b and fs2 == 0 and fe2 == 0x06 and fm2 == 0x066 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x788b; op2val:0x1866; +op3val:0x7bff; valaddr_reg:x5; val_offset:504*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 504*FLEN/8, x7, x1, x4) + +inst_192: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a0 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x209 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76a0; op2val:0x1a09; +op3val:0x7bff; valaddr_reg:x5; val_offset:507*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 507*FLEN/8, x7, x1, x4) + +inst_193: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26e and fs2 == 0 and fe2 == 0x06 and fm2 == 0x237 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x766e; op2val:0x1a37; +op3val:0x7bff; valaddr_reg:x5; val_offset:510*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 510*FLEN/8, x7, x1, x4) + +inst_194: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x011 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x799c; op2val:0x11; +op3val:0x7bff; valaddr_reg:x5; val_offset:513*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 513*FLEN/8, x7, x1, x4) + +inst_195: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x01c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76b0; op2val:0x1c; +op3val:0x7bff; valaddr_reg:x5; val_offset:516*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 516*FLEN/8, x7, x1, x4) + +inst_196: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x14b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x012 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x794b; op2val:0x12; +op3val:0x7bff; valaddr_reg:x5; val_offset:519*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 519*FLEN/8, x7, x1, x4) + +inst_197: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x1fc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x100 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x69fc; op2val:0x100; +op3val:0x7bff; valaddr_reg:x5; val_offset:522*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 522*FLEN/8, x7, x1, x4) + +inst_198: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x01a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x771f; op2val:0x1a; +op3val:0x7bff; valaddr_reg:x5; val_offset:525*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 525*FLEN/8, x7, x1, x4) + +inst_199: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x02e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7425; op2val:0x2e; +op3val:0x7bff; valaddr_reg:x5; val_offset:528*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 528*FLEN/8, x7, x1, x4) + +inst_200: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x10b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x04c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x710b; op2val:0x4c; +op3val:0x7bff; valaddr_reg:x5; val_offset:531*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 531*FLEN/8, x7, x1, x4) + +inst_201: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x037 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x016 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7837; op2val:0x8016; +op3val:0x7bff; valaddr_reg:x5; val_offset:534*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 534*FLEN/8, x7, x1, x4) + +inst_202: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ca and fs2 == 1 and fe2 == 0x00 and fm2 == 0x018 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77ca; op2val:0x8018; +op3val:0x7bff; valaddr_reg:x5; val_offset:537*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 537*FLEN/8, x7, x1, x4) + +inst_203: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x07d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x015 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x787d; op2val:0x8015; +op3val:0x7bff; valaddr_reg:x5; val_offset:540*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 540*FLEN/8, x7, x1, x4) + +inst_204: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a0a; op2val:0x800f; +op3val:0x7bff; valaddr_reg:x5; val_offset:543*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 543*FLEN/8, x7, x1, x4) + +inst_205: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x311 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b11; op2val:0x800d; +op3val:0x7bff; valaddr_reg:x5; val_offset:546*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 546*FLEN/8, x7, x1, x4) + +inst_206: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3e8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x018 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77e8; op2val:0x8018; +op3val:0x7bff; valaddr_reg:x5; val_offset:549*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 549*FLEN/8, x7, x1, x4) + +inst_207: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0fd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x026 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74fd; op2val:0x8026; +op3val:0x7bff; valaddr_reg:x5; val_offset:552*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 552*FLEN/8, x7, x1, x4) + +inst_208: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x377 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x019 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7777; op2val:0x8019; +op3val:0x7bff; valaddr_reg:x5; val_offset:555*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 555*FLEN/8, x7, x1, x4) + +inst_209: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x278 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a78; op2val:0x800e; +op3val:0x7bff; valaddr_reg:x5; val_offset:558*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 558*FLEN/8, x7, x1, x4) + +inst_210: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aff; op2val:0x800d; +op3val:0x7bff; valaddr_reg:x5; val_offset:561*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 561*FLEN/8, x7, x1, x4) + +inst_211: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x27f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a7f; op2val:0x800e; +op3val:0x7bff; valaddr_reg:x5; val_offset:564*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 564*FLEN/8, x7, x1, x4) + +inst_212: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x203 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x03f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7203; op2val:0x803f; +op3val:0x7bff; valaddr_reg:x5; val_offset:567*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 567*FLEN/8, x7, x1, x4) + +inst_213: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3fd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bfd; op2val:0x800c; +op3val:0x7bff; valaddr_reg:x5; val_offset:570*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 570*FLEN/8, x7, x1, x4) + +inst_214: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x10f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x012 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x790f; op2val:0x8012; +op3val:0x7bff; valaddr_reg:x5; val_offset:573*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 573*FLEN/8, x7, x1, x4) + +inst_215: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x157 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x08f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d57; op2val:0x8f; +op3val:0x7bff; valaddr_reg:x5; val_offset:576*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 576*FLEN/8, x7, x1, x4) + +inst_216: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1cd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x010 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79cd; op2val:0x10; +op3val:0x7bff; valaddr_reg:x5; val_offset:579*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 579*FLEN/8, x7, x1, x4) + +inst_217: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7be4; op2val:0xc; +op3val:0x7bff; valaddr_reg:x5; val_offset:582*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 582*FLEN/8, x7, x1, x4) + +inst_218: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x01d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x766d; op2val:0x1d; +op3val:0x7bff; valaddr_reg:x5; val_offset:585*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 585*FLEN/8, x7, x1, x4) + +inst_219: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x16c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x011 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x796c; op2val:0x11; +op3val:0x7bff; valaddr_reg:x5; val_offset:588*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 588*FLEN/8, x7, x1, x4) + +inst_220: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x10e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x025 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x750e; op2val:0x25; +op3val:0x7bff; valaddr_reg:x5; val_offset:591*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 591*FLEN/8, x7, x1, x4) + +inst_221: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2d4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x038 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72d4; op2val:0x38; +op3val:0x7bff; valaddr_reg:x5; val_offset:594*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 594*FLEN/8, x7, x1, x4) + +inst_222: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1bc and fs2 == 0 and fe2 == 0x0f and fm2 == 0x193 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79bc; op2val:0x3d93; +op3val:0x7bff; valaddr_reg:x5; val_offset:597*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 597*FLEN/8, x7, x1, x4) + +inst_223: +// fs1 == 0 and fe1 == 0x16 and fm1 == 0x0db and fs2 == 1 and fe2 == 0x17 and fm2 == 0x295 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x58db; op2val:0xde95; +op3val:0x7bff; valaddr_reg:x5; val_offset:600*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 600*FLEN/8, x7, x1, x4) + +inst_224: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x294 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0dc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a94; op2val:0x3cdc; +op3val:0x7bff; valaddr_reg:x5; val_offset:603*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 603*FLEN/8, x7, x1, x4) + +inst_225: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x039 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x392 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7839; op2val:0xbf92; +op3val:0x7bff; valaddr_reg:x5; val_offset:606*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 606*FLEN/8, x7, x1, x4) + +inst_226: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x241 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x11c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e41; op2val:0x491c; +op3val:0x7bff; valaddr_reg:x5; val_offset:609*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 609*FLEN/8, x7, x1, x4) + +inst_227: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x39b and fs2 == 1 and fe2 == 0x12 and fm2 == 0x034 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f9b; op2val:0xc834; +op3val:0x7bff; valaddr_reg:x5; val_offset:612*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 612*FLEN/8, x7, x1, x4) + +inst_228: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x131 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x229 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7931; op2val:0x3e29; +op3val:0x7bff; valaddr_reg:x5; val_offset:615*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 615*FLEN/8, x7, x1, x4) + +inst_229: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2fc and fs2 == 1 and fe2 == 0x0f and fm2 == 0x094 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7afc; op2val:0xbc94; +op3val:0x7bff; valaddr_reg:x5; val_offset:618*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 618*FLEN/8, x7, x1, x4) + +inst_230: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x07a and fs2 == 0 and fe2 == 0x10 and fm2 == 0x324 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x747a; op2val:0x4324; +op3val:0x7bff; valaddr_reg:x5; val_offset:621*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 621*FLEN/8, x7, x1, x4) + +inst_231: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x016 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd3; op2val:0xbc16; +op3val:0x7bff; valaddr_reg:x5; val_offset:624*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 624*FLEN/8, x7, x1, x4) + +inst_232: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x268 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x0fd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e68; op2val:0x48fd; +op3val:0x7bff; valaddr_reg:x5; val_offset:627*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 627*FLEN/8, x7, x1, x4) + +inst_233: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0af and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ad4; op2val:0xbcaf; +op3val:0x7bff; valaddr_reg:x5; val_offset:630*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 630*FLEN/8, x7, x1, x4) + +inst_234: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x258 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x10a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7658; op2val:0x410a; +op3val:0x7bff; valaddr_reg:x5; val_offset:633*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 633*FLEN/8, x7, x1, x4) + +inst_235: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x134 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x225 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d34; op2val:0xca25; +op3val:0x7bff; valaddr_reg:x5; val_offset:636*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 636*FLEN/8, x7, x1, x4) + +inst_236: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x064 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x347 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7464; op2val:0x3747; +op3val:0x7bff; valaddr_reg:x5; val_offset:639*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 639*FLEN/8, x7, x1, x4) + +inst_237: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x33e and fs2 == 1 and fe2 == 0x0d and fm2 == 0x06a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x773e; op2val:0xb46a; +op3val:0x7bff; valaddr_reg:x5; val_offset:642*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 642*FLEN/8, x7, x1, x4) + +inst_238: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x255 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x10c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a55; op2val:0x350c; +op3val:0x7bff; valaddr_reg:x5; val_offset:645*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 645*FLEN/8, x7, x1, x4) + +inst_239: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e3 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0a4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ae3; op2val:0xb4a4; +op3val:0x7bff; valaddr_reg:x5; val_offset:648*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 648*FLEN/8, x7, x1, x4) + +inst_240: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x044 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x37e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7044; op2val:0x437e; +op3val:0x7bff; valaddr_reg:x5; val_offset:651*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 651*FLEN/8, x7, x1, x4) + +inst_241: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3ad and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x782a; op2val:0xbbad; +op3val:0x7bff; valaddr_reg:x5; val_offset:654*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 654*FLEN/8, x7, x1, x4) + +inst_242: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x134 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x225 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7934; op2val:0x3e25; +op3val:0x7bff; valaddr_reg:x5; val_offset:657*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 657*FLEN/8, x7, x1, x4) + +inst_243: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x18c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1c3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x758c; op2val:0xc1c3; +op3val:0x7bff; valaddr_reg:x5; val_offset:660*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 660*FLEN/8, x7, x1, x4) + +inst_244: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f8 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x096 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7af8; op2val:0x4096; +op3val:0x7bff; valaddr_reg:x5; val_offset:663*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 663*FLEN/8, x7, x1, x4) + +inst_245: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x073 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x32e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7473; op2val:0xc72e; +op3val:0x7bff; valaddr_reg:x5; val_offset:666*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 666*FLEN/8, x7, x1, x4) + +inst_246: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x0c1 and fs2 == 0 and fe2 == 0x16 and fm2 == 0x2b9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x64c1; op2val:0x5ab9; +op3val:0x7bff; valaddr_reg:x5; val_offset:669*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 669*FLEN/8, x7, x1, x4) + +inst_247: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x134 and fs2 == 1 and fe2 == 0x15 and fm2 == 0x225 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6934; op2val:0xd625; +op3val:0x7bff; valaddr_reg:x5; val_offset:672*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 672*FLEN/8, x7, x1, x4) + +inst_248: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x172 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x1df and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7972; op2val:0x49df; +op3val:0x7bff; valaddr_reg:x5; val_offset:675*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 675*FLEN/8, x7, x1, x4) + +inst_249: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x076 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x329 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7876; op2val:0xcb29; +op3val:0x7bff; valaddr_reg:x5; val_offset:678*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 678*FLEN/8, x7, x1, x4) + +inst_250: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x391 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b91; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:681*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 681*FLEN/8, x7, x1, x4) + +inst_251: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x380 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b80; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:684*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 684*FLEN/8, x7, x1, x4) + +inst_252: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x160 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6960; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:687*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 687*FLEN/8, x7, x1, x4) + +inst_253: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1fd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79fd; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:690*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 690*FLEN/8, x7, x1, x4) + +inst_254: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x799b; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:693*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 693*FLEN/8, x7, x1, x4) + +inst_255: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x13d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x793d; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:696*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 696*FLEN/8, x7, x1, x4) + +inst_256: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79b2; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:699*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 699*FLEN/8, x7, x1, x4) + +inst_257: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x337 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b37; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:702*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 702*FLEN/8, x7, x1, x4) + +inst_258: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x11e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x791e; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:705*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 705*FLEN/8, x7, x1, x4) + +inst_259: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1f4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75f4; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:708*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 708*FLEN/8, x7, x1, x4) + +inst_260: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x784d; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:711*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 711*FLEN/8, x7, x1, x4) + +inst_261: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2a5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72a5; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:714*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 714*FLEN/8, x7, x1, x4) + +inst_262: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78b1; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:717*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 717*FLEN/8, x7, x1, x4) + +inst_263: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x08f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x608f; op2val:0x1; +op3val:0x7bff; valaddr_reg:x5; val_offset:720*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 720*FLEN/8, x7, x1, x4) + +inst_264: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0d4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70d4; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:723*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 723*FLEN/8, x7, x1, x4) + +inst_265: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7555; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:726*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 726*FLEN/8, x7, x1, x4) + +inst_266: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x250 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a50; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:729*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 729*FLEN/8, x7, x1, x4) + +inst_267: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1be and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79be; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:732*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 732*FLEN/8, x7, x1, x4) + +inst_268: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x168 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7568; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:735*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 735*FLEN/8, x7, x1, x4) + +inst_269: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0f6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78f6; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:738*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 738*FLEN/8, x7, x1, x4) + +inst_270: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x145 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6945; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:741*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 741*FLEN/8, x7, x1, x4) + +inst_271: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x13d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x713d; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:744*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 744*FLEN/8, x7, x1, x4) + +inst_272: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd9; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:747*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 747*FLEN/8, x7, x1, x4) + +inst_273: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74a1; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:750*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 750*FLEN/8, x7, x1, x4) + +inst_274: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x250 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7650; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:753*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 753*FLEN/8, x7, x1, x4) + +inst_275: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x062 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7862; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:756*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 756*FLEN/8, x7, x1, x4) + +inst_276: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0b1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74b1; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:759*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 759*FLEN/8, x7, x1, x4) + +inst_277: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77a5; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:762*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 762*FLEN/8, x7, x1, x4) + +inst_278: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73aa; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:765*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 765*FLEN/8, x7, x1, x4) + +inst_279: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x22c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6a2c; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:768*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 768*FLEN/8, x7, x1, x4) + +inst_280: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1be and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71be; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:771*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 771*FLEN/8, x7, x1, x4) + +inst_281: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ac0; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:774*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 774*FLEN/8, x7, x1, x4) + +inst_282: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a0f; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:777*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 777*FLEN/8, x7, x1, x4) + +inst_283: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x024 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7424; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:780*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 780*FLEN/8, x7, x1, x4) + +inst_284: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74d9; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:783*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 783*FLEN/8, x7, x1, x4) + +inst_285: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x39f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x779f; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:786*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 786*FLEN/8, x7, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_2) + +inst_286: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78aa; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:789*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 789*FLEN/8, x7, x1, x4) + +inst_287: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x342 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b42; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:792*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 792*FLEN/8, x7, x1, x4) + +inst_288: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x009 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7809; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:795*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 795*FLEN/8, x7, x1, x4) + +inst_289: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x081 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7481; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:798*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 798*FLEN/8, x7, x1, x4) + +inst_290: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b2f; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:801*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 801*FLEN/8, x7, x1, x4) + +inst_291: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x178 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7978; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:804*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 804*FLEN/8, x7, x1, x4) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(31424,32,FLEN) +NAN_BOXED(31424,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(31247,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31247,32,FLEN) +NAN_BOXED(30393,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(29732,32,FLEN) +NAN_BOXED(29732,32,FLEN) +NAN_BOXED(29732,32,FLEN) +NAN_BOXED(30742,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(30329,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(31300,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(29913,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32768,32,FLEN) +NAN_BOXED(30623,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(30623,32,FLEN) +NAN_BOXED(30890,32,FLEN) +NAN_BOXED(30890,16,FLEN) +NAN_BOXED(30890,32,FLEN) +NAN_BOXED(31554,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32768,32,FLEN) +NAN_BOXED(30729,32,FLEN) +NAN_BOXED(30729,16,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(29825,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(0,32,FLEN) +test_dataset_1: +NAN_BOXED(31243,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(30961,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(29697,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(31558,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(31707,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(31354,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(31542,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(29941,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(31189,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31743,32,FLEN) +test_dataset_2: +NAN_BOXED(31096,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30604,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(28273,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30449,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30946,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31564,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31674,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30624,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31467,16,FLEN) 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+NAN_BOXED(29608,16,FLEN) +NAN_BOXED(7481,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31000,16,FLEN) +NAN_BOXED(6105,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30222,16,FLEN) +NAN_BOXED(6811,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31487,16,FLEN) +NAN_BOXED(5558,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30859,16,FLEN) +NAN_BOXED(6246,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30368,16,FLEN) +NAN_BOXED(6665,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30318,16,FLEN) +NAN_BOXED(6711,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31132,16,FLEN) +NAN_BOXED(17,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30384,16,FLEN) +NAN_BOXED(28,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31051,16,FLEN) +NAN_BOXED(18,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(27132,16,FLEN) +NAN_BOXED(256,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30495,16,FLEN) +NAN_BOXED(26,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29733,16,FLEN) +NAN_BOXED(46,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(28939,16,FLEN) +NAN_BOXED(76,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30775,16,FLEN) +NAN_BOXED(32790,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30666,16,FLEN) +NAN_BOXED(32792,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30845,16,FLEN) +NAN_BOXED(32789,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31242,16,FLEN) +NAN_BOXED(32783,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31505,16,FLEN) +NAN_BOXED(32781,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30696,16,FLEN) +NAN_BOXED(32792,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29949,16,FLEN) +NAN_BOXED(32806,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30583,16,FLEN) +NAN_BOXED(32793,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31352,16,FLEN) +NAN_BOXED(32782,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31487,16,FLEN) +NAN_BOXED(32781,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31359,16,FLEN) +NAN_BOXED(32782,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29187,16,FLEN) +NAN_BOXED(32831,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31741,16,FLEN) +NAN_BOXED(32780,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30991,16,FLEN) +NAN_BOXED(32786,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(27991,16,FLEN) +NAN_BOXED(143,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31181,16,FLEN) +NAN_BOXED(16,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31716,16,FLEN) +NAN_BOXED(12,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30317,16,FLEN) +NAN_BOXED(29,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31084,16,FLEN) +NAN_BOXED(17,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29966,16,FLEN) +NAN_BOXED(37,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29396,16,FLEN) +NAN_BOXED(56,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31164,16,FLEN) +NAN_BOXED(15763,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(22747,16,FLEN) +NAN_BOXED(56981,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31380,16,FLEN) +NAN_BOXED(15580,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30777,16,FLEN) +NAN_BOXED(49042,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(28225,16,FLEN) +NAN_BOXED(18716,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(28571,16,FLEN) +NAN_BOXED(51252,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31025,16,FLEN) +NAN_BOXED(15913,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31484,16,FLEN) +NAN_BOXED(48276,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29818,16,FLEN) +NAN_BOXED(17188,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31699,16,FLEN) +NAN_BOXED(48150,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(28264,16,FLEN) +NAN_BOXED(18685,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31444,16,FLEN) +NAN_BOXED(48303,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30296,16,FLEN) +NAN_BOXED(16650,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(27956,16,FLEN) +NAN_BOXED(51749,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29796,16,FLEN) +NAN_BOXED(14151,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30526,16,FLEN) +NAN_BOXED(46186,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31317,16,FLEN) +NAN_BOXED(13580,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31459,16,FLEN) +NAN_BOXED(46244,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(28740,16,FLEN) +NAN_BOXED(17278,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30762,16,FLEN) +NAN_BOXED(48045,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31028,16,FLEN) +NAN_BOXED(15909,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30092,16,FLEN) +NAN_BOXED(49603,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31480,16,FLEN) +NAN_BOXED(16534,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29811,16,FLEN) +NAN_BOXED(50990,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(25793,16,FLEN) +NAN_BOXED(23225,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(26932,16,FLEN) +NAN_BOXED(54821,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31090,16,FLEN) +NAN_BOXED(18911,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30838,16,FLEN) +NAN_BOXED(52009,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31633,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31616,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(26976,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31229,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31131,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31037,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31154,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31543,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31006,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30196,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30797,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29349,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30897,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(24719,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(28884,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30037,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31312,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31166,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30056,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30966,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(26949,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(28989,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31705,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29857,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30288,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30818,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29873,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30629,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29610,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(27180,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29118,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31424,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31247,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29732,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29913,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30623,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30890,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31554,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30729,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29825,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31535,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31096,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x3_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x3_1: + .fill 32*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_0: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_0: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_2: + .fill 12*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fmadd_b2-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fmadd_b2-01.S new file mode 100644 index 000000000..2018cf446 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fmadd_b2-01.S @@ -0,0 +1,1414 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 04:10:09 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fmadd.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fmadd.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fmadd_b2 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fmadd_b2) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x8,test_dataset_0) +RVTEST_SIGBASE(x3,signature_x3_1) + +inst_0: +// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==x26, rs2==x26, rs3==x14, rd==x10,fs1 == 0 and fe1 == 0x00 and fm1 == 0x050 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x266 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x021 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x26; op2:x26; op3:x14; dest:x10; op1val:0x50; op2val:0x50; +op3val:0x21; valaddr_reg:x8; val_offset:0*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x10, x26, x26, x14, dyn, 0, 0, x8, 0*FLEN/8, x13, x3, x4) + +inst_1: +// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==x20, rs2==x6, rs3==x20, rd==x27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x05f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x369 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x02e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x20; op2:x6; op3:x20; dest:x27; op1val:0x5f; op2val:0xb769; +op3val:0x5f; valaddr_reg:x8; val_offset:3*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x27, x20, x6, x20, dyn, 0, 0, x8, 3*FLEN/8, x13, x3, x4) + +inst_2: +// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==x24, rs2==x1, rs3==x3, rd==x24,fs1 == 0 and fe1 == 0x00 and fm1 == 0x059 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x017 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x05f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x24; op2:x1; op3:x3; dest:x24; op1val:0x59; op2val:0xbc17; +op3val:0x5f; valaddr_reg:x8; val_offset:6*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x24, x24, x1, x3, dyn, 0, 0, x8, 6*FLEN/8, x13, x3, x4) + +inst_3: +// rs1 == rs2 == rs3 != rd, rs1==x9, rs2==x9, rs3==x9, rd==x12,fs1 == 0 and fe1 == 0x00 and fm1 == 0x054 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1b6 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x044 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x9; op2:x9; op3:x9; dest:x12; op1val:0x54; op2val:0x54; +op3val:0x54; valaddr_reg:x8; val_offset:9*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x12, x9, x9, x9, dyn, 0, 0, x8, 9*FLEN/8, x13, x3, x4) + +inst_4: +// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==x2, rs2==x14, rs3==x5, rd==x5,fs1 == 0 and fe1 == 0x00 and fm1 == 0x004 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x180 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x03c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x2; op2:x14; op3:x5; dest:x5; op1val:0x4; op2val:0xc980; +op3val:0x3c; valaddr_reg:x8; val_offset:12*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x5, x2, x14, x5, dyn, 0, 0, x8, 12*FLEN/8, x13, x3, x4) + +inst_5: +// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==x29, rs2==x0, rs3==x24, rd==x0,fs1 == 0 and fe1 == 0x00 and fm1 == 0x020 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x280 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x054 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x29; op2:x0; op3:x24; dest:x0; op1val:0x20; op2val:0x0; +op3val:0x54; valaddr_reg:x8; val_offset:15*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x0, x29, x0, x24, dyn, 0, 0, x8, 15*FLEN/8, x13, x3, x4) + +inst_6: +// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==x6, rs2==x19, rs3==x21, rd==x20,fs1 == 0 and fe1 == 0x00 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x224 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x015 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x6; op2:x19; op3:x21; dest:x20; op1val:0x7; op2val:0x4624; +op3val:0x15; valaddr_reg:x8; val_offset:18*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x20, x6, x19, x21, dyn, 0, 0, x8, 18*FLEN/8, x13, x3, x4) + +inst_7: +// rd == rs2 == rs3 != rs1, rs1==x19, rs2==x15, rs3==x15, rd==x15,fs1 == 0 and fe1 == 0x00 and fm1 == 0x00f and fs2 == 0 and fe2 == 0x11 and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x030 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x19; op2:x15; op3:x15; dest:x15; op1val:0xf; op2val:0x4555; +op3val:0x4555; valaddr_reg:x8; val_offset:21*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x15, x19, x15, x15, dyn, 0, 0, x8, 21*FLEN/8, x13, x3, x4) + +inst_8: +// rs1 == rd == rs3 != rs2, rs1==x25, rs2==x28, rs3==x25, rd==x25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x03d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x358 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x020 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x25; op2:x28; op3:x25; dest:x25; op1val:0x3d; op2val:0x4358; +op3val:0x3d; valaddr_reg:x8; val_offset:24*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x25, x25, x28, x25, dyn, 0, 0, x8, 24*FLEN/8, x13, x3, x4) + +inst_9: +// rs1 == rs2 == rs3 == rd, rs1==x11, rs2==x11, rs3==x11, rd==x11,fs1 == 0 and fe1 == 0x00 and fm1 == 0x031 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x082 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x046 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x11; op2:x11; op3:x11; dest:x11; op1val:0x31; op2val:0x31; +op3val:0x31; valaddr_reg:x8; val_offset:27*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x11, x11, x11, x11, dyn, 0, 0, x8, 27*FLEN/8, x13, x3, x4) + +inst_10: +// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==x23, rs2==x10, rs3==x10, rd==x7,fs1 == 0 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 1 and fe2 == 0x11 and fm2 == 0x15b and fs3 == 0 and fe3 == 0x00 and fm3 == 0x04a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x23; op2:x10; op3:x10; dest:x7; op1val:0xe; op2val:0xc55b; +op3val:0xc55b; valaddr_reg:x8; val_offset:30*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x7, x23, x10, x10, dyn, 0, 0, x8, 30*FLEN/8, x13, x3, x4) + +inst_11: +// rs1 == rs2 == rd != rs3, rs1==x22, rs2==x22, rs3==x8, rd==x22,fs1 == 0 and fe1 == 0x00 and fm1 == 0x020 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x22; op2:x22; op3:x8; dest:x22; op1val:0x20; op2val:0x20; +op3val:0x2; valaddr_reg:x8; val_offset:33*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x22, x22, x22, x8, dyn, 0, 0, x8, 33*FLEN/8, x13, x3, x4) + +inst_12: +// rs1==x7, rs2==x31, rs3==x27, rd==x2,fs1 == 0 and fe1 == 0x00 and fm1 == 0x05e and fs2 == 1 and fe2 == 0x0d and fm2 == 0x172 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x01c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x7; op2:x31; op3:x27; dest:x2; op1val:0x5e; op2val:0xb572; +op3val:0x1c; valaddr_reg:x8; val_offset:36*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x2, x7, x31, x27, dyn, 0, 0, x8, 36*FLEN/8, x13, x3, x4) +RVTEST_VALBASEUPD(x9,test_dataset_1) + +inst_13: +// rs1==x8, rs2==x7, rs3==x31, rd==x1,fs1 == 0 and fe1 == 0x00 and fm1 == 0x035 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2a4 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x024 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x8; op2:x7; op3:x31; dest:x1; op1val:0x35; op2val:0xbaa4; +op3val:0x24; valaddr_reg:x9; val_offset:0*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x1, x8, x7, x31, dyn, 0, 0, x9, 0*FLEN/8, x10, x3, x4) + +inst_14: +// rs1==x18, rs2==x27, rs3==x12, rd==x30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x018 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0ca and fs3 == 0 and fe3 == 0x00 and fm3 == 0x063 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x18; op2:x27; op3:x12; dest:x30; op1val:0x18; op2val:0xc4ca; +op3val:0x63; valaddr_reg:x9; val_offset:3*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x30, x18, x27, x12, dyn, 0, 0, x9, 3*FLEN/8, x10, x3, x4) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_15: +// rs1==x13, rs2==x5, rs3==x6, rd==x18,fs1 == 0 and fe1 == 0x00 and fm1 == 0x032 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x03d and fs3 == 0 and fe3 == 0x00 and fm3 == 0x015 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x13; op2:x5; op3:x6; dest:x18; op1val:0x32; op2val:0xbc3d; +op3val:0x15; valaddr_reg:x9; val_offset:6*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x18, x13, x5, x6, dyn, 0, 0, x9, 6*FLEN/8, x10, x1, x7) + +inst_16: +// rs1==x21, rs2==x20, rs3==x17, rd==x26,fs1 == 0 and fe1 == 0x00 and fm1 == 0x062 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x20a and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x21; op2:x20; op3:x17; dest:x26; op1val:0x62; op2val:0xba0a; +op3val:0xa; valaddr_reg:x9; val_offset:9*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x26, x21, x20, x17, dyn, 0, 0, x9, 9*FLEN/8, x10, x1, x7) + +inst_17: +// rs1==x30, rs2==x12, rs3==x7, rd==x31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x012 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x1c7 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x050 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x12; op3:x7; dest:x31; op1val:0x12; op2val:0xc9c7; +op3val:0x50; valaddr_reg:x9; val_offset:12*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x12, x7, dyn, 0, 0, x9, 12*FLEN/8, x10, x1, x7) + +inst_18: +// rs1==x17, rs2==x8, rs3==x26, rd==x16,fs1 == 0 and fe1 == 0x00 and fm1 == 0x050 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3d3 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x039 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x17; op2:x8; op3:x26; dest:x16; op1val:0x50; op2val:0xc3d3; +op3val:0x39; valaddr_reg:x9; val_offset:15*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x16, x17, x8, x26, dyn, 0, 0, x9, 15*FLEN/8, x10, x1, x7) + +inst_19: +// rs1==x27, rs2==x29, rs3==x23, rd==x28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x011 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x3c7 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x011 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x27; op2:x29; op3:x23; dest:x28; op1val:0x11; op2val:0xcfc7; +op3val:0x11; valaddr_reg:x9; val_offset:18*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x28, x27, x29, x23, dyn, 0, 0, x9, 18*FLEN/8, x10, x1, x7) + +inst_20: +// rs1==x15, rs2==x16, rs3==x18, rd==x6,fs1 == 0 and fe1 == 0x0f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x15; op2:x16; op3:x18; dest:x6; op1val:0x3c01; op2val:0xf0; +op3val:0x3c01; valaddr_reg:x9; val_offset:21*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x6, x15, x16, x18, dyn, 0, 0, x9, 21*FLEN/8, x10, x1, x7) + +inst_21: +// rs1==x12, rs2==x18, rs3==x1, rd==x4,fs1 == 0 and fe1 == 0x0f and fm1 == 0x01b and fs2 == 1 and fe2 == 0x09 and fm2 == 0x255 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x01c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x12; op2:x18; op3:x1; dest:x4; op1val:0x3c1b; op2val:0xa655; +op3val:0x3c1c; valaddr_reg:x9; val_offset:24*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x4, x12, x18, x1, dyn, 0, 0, x9, 24*FLEN/8, x10, x1, x7) + +inst_22: +// rs1==x3, rs2==x21, rs3==x2, rd==x19,fs1 == 0 and fe1 == 0x0f and fm1 == 0x016 and fs2 == 1 and fe2 == 0x09 and fm2 == 0x067 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x016 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x3; op2:x21; op3:x2; dest:x19; op1val:0x3c16; op2val:0xa467; +op3val:0x3c16; valaddr_reg:x9; val_offset:27*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x19, x3, x21, x2, dyn, 0, 0, x9, 27*FLEN/8, x10, x1, x7) + +inst_23: +// rs1==x28, rs2==x4, rs3==x29, rd==x17,fs1 == 0 and fe1 == 0x0f and fm1 == 0x026 and fs2 == 1 and fe2 == 0x09 and fm2 == 0x3f4 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x029 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x28; op2:x4; op3:x29; dest:x17; op1val:0x3c26; op2val:0xa7f4; +op3val:0x3c29; valaddr_reg:x9; val_offset:30*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x17, x28, x4, x29, dyn, 0, 0, x9, 30*FLEN/8, x10, x1, x7) + +inst_24: +// rs1==x5, rs2==x2, rs3==x0, rd==x29,fs1 == 0 and fe1 == 0x0f and fm1 == 0x01a and fs2 == 1 and fe2 == 0x0a and fm2 == 0x295 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x046 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x5; op2:x2; op3:x0; dest:x29; op1val:0x3c1a; op2val:0xaa95; +op3val:0x0; valaddr_reg:x9; val_offset:33*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x29, x5, x2, x0, dyn, 0, 0, x9, 33*FLEN/8, x10, x1, x7) + +inst_25: +// rs1==x31, rs2==x23, rs3==x30, rd==x21,fs1 == 0 and fe1 == 0x0f and fm1 == 0x057 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x1a5 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x051 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x31; op2:x23; op3:x30; dest:x21; op1val:0x3c57; op2val:0xa9a5; +op3val:0x3c51; valaddr_reg:x9; val_offset:36*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x21, x31, x23, x30, dyn, 0, 0, x9, 36*FLEN/8, x10, x1, x7) +RVTEST_VALBASEUPD(x6,test_dataset_2) + +inst_26: +// rs1==x4, rs2==x17, rs3==x19, rd==x8,fs1 == 0 and fe1 == 0x0f and fm1 == 0x01b and fs2 == 0 and fe2 == 0x0a and fm2 == 0x0df and fs3 == 0 and fe3 == 0x0f and fm3 == 0x018 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x4; op2:x17; op3:x19; dest:x8; op1val:0x3c1b; op2val:0x28df; +op3val:0x3c18; valaddr_reg:x6; val_offset:0*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x8, x4, x17, x19, dyn, 0, 0, x6, 0*FLEN/8, x11, x1, x7) + +inst_27: +// rs1==x16, rs2==x30, rs3==x28, rd==x3,fs1 == 0 and fe1 == 0x0f and fm1 == 0x059 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x1dd and fs3 == 0 and fe3 == 0x0f and fm3 == 0x01a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x16; op2:x30; op3:x28; dest:x3; op1val:0x3c59; op2val:0x2ddd; +op3val:0x3c1a; valaddr_reg:x6; val_offset:3*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x3, x16, x30, x28, dyn, 0, 0, x6, 3*FLEN/8, x11, x1, x7) + +inst_28: +// rs1==x10, rs2==x24, rs3==x4, rd==x14,fs1 == 0 and fe1 == 0x0f and fm1 == 0x032 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x277 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x027 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x10; op2:x24; op3:x4; dest:x14; op1val:0x3c32; op2val:0x3277; +op3val:0x3c27; valaddr_reg:x6; val_offset:6*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x14, x10, x24, x4, dyn, 0, 0, x6, 6*FLEN/8, x11, x1, x7) +RVTEST_SIGBASE(x2,signature_x2_0) + +inst_29: +// rs1==x0, rs2==x25, rs3==x22, rd==x13,fs1 == 0 and fe1 == 0x0f and fm1 == 0x003 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x33e and fs3 == 0 and fe3 == 0x0f and fm3 == 0x02f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x0; op2:x25; op3:x22; dest:x13; op1val:0x0; op2val:0x373e; +op3val:0x3c2f; valaddr_reg:x6; val_offset:9*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x13, x0, x25, x22, dyn, 0, 0, x6, 9*FLEN/8, x11, x2, x5) + +inst_30: +// rs1==x1, rs2==x3, rs3==x16, rd==x9,fs1 == 0 and fe1 == 0x0f and fm1 == 0x036 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3af and fs3 == 0 and fe3 == 0x0f and fm3 == 0x016 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x1; op2:x3; op3:x16; dest:x9; op1val:0x3c36; op2val:0xbfaf; +op3val:0x3c16; valaddr_reg:x6; val_offset:12*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x9, x1, x3, x16, dyn, 0, 0, x6, 12*FLEN/8, x11, x2, x5) + +inst_31: +// rs1==x14,fs1 == 0 and fe1 == 0x0f and fm1 == 0x013 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x0f and fm3 == 0x022 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x14; op2:x13; op3:x18; dest:x3; op1val:0x3c13; op2val:0xbffe; +op3val:0x3c22; valaddr_reg:x6; val_offset:15*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x3, x14, x13, x18, dyn, 0, 0, x6, 15*FLEN/8, x11, x2, x5) + +inst_32: +// rs3==x13,fs1 == 0 and fe1 == 0x0f and fm1 == 0x009 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x00e and fs3 == 0 and fe3 == 0x0f and fm3 == 0x02b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x12; op2:x4; op3:x13; dest:x31; op1val:0x3c09; op2val:0xc00e; +op3val:0x3c2b; valaddr_reg:x6; val_offset:18*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x12, x4, x13, dyn, 0, 0, x6, 18*FLEN/8, x11, x2, x5) + +inst_33: +// rd==x23,fs1 == 0 and fe1 == 0x0f and fm1 == 0x027 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x003 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x04e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x25; op2:x31; op3:x7; dest:x23; op1val:0x3c27; op2val:0xc003; +op3val:0x3c4e; valaddr_reg:x6; val_offset:21*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x23, x25, x31, x7, dyn, 0, 0, x6, 21*FLEN/8, x11, x2, x5) + +inst_34: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x04c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x382 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c4c; op2val:0xbf82; +op3val:0x3c01; valaddr_reg:x6; val_offset:24*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 24*FLEN/8, x11, x2, x5) + +inst_35: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x04d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3df and fs3 == 0 and fe3 == 0x0f and fm3 == 0x057 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c4d; op2val:0xbfdf; +op3val:0x3c57; valaddr_reg:x6; val_offset:27*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 27*FLEN/8, x11, x2, x5) + +inst_36: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x05b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3bc and fs3 == 0 and fe3 == 0x0f and fm3 == 0x02c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c5b; op2val:0xbfbc; +op3val:0x3c2c; valaddr_reg:x6; val_offset:30*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 30*FLEN/8, x11, x2, x5) + +inst_37: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x009 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x04a and fs3 == 0 and fe3 == 0x0f and fm3 == 0x028 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c09; op2val:0xc04a; +op3val:0x3c28; valaddr_reg:x6; val_offset:33*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 33*FLEN/8, x11, x2, x5) + +inst_38: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x02e and fs2 == 1 and fe2 == 0x10 and fm2 == 0x061 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x028 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c2e; op2val:0xc061; +op3val:0x3c28; valaddr_reg:x6; val_offset:36*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 36*FLEN/8, x11, x2, x5) + +inst_39: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x03e and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0e1 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x05a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c3e; op2val:0xc0e1; +op3val:0x3c5a; valaddr_reg:x6; val_offset:39*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 39*FLEN/8, x11, x2, x5) + +inst_40: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x029 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x07c and fs3 == 0 and fe3 == 0x00 and fm3 == 0x018 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x29; op2val:0xb87c; +op3val:0x18; valaddr_reg:x6; val_offset:42*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 42*FLEN/8, x11, x2, x5) + +inst_41: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x37b and fs3 == 0 and fe3 == 0x00 and fm3 == 0x03d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3e; op2val:0xbb7b; +op3val:0x3d; valaddr_reg:x6; val_offset:45*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 45*FLEN/8, x11, x2, x5) + +inst_42: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x05b and fs2 == 1 and fe2 == 0x0c and fm2 == 0x254 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x017 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5b; op2val:0xb254; +op3val:0x17; valaddr_reg:x6; val_offset:48*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 48*FLEN/8, x11, x2, x5) + +inst_43: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x008 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x021 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8; op2val:0xc200; +op3val:0x21; valaddr_reg:x6; val_offset:51*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 51*FLEN/8, x11, x2, x5) + +inst_44: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x295 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x060 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3; op2val:0xce95; +op3val:0x60; valaddr_reg:x6; val_offset:54*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 54*FLEN/8, x11, x2, x5) + +inst_45: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x02e and fs2 == 1 and fe2 == 0x0d and fm2 == 0x29b and fs3 == 0 and fe3 == 0x00 and fm3 == 0x034 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e; op2val:0xb69b; +op3val:0x34; valaddr_reg:x6; val_offset:57*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 57*FLEN/8, x11, x2, x5) + +inst_46: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x047 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3; op2val:0xc000; +op3val:0x47; valaddr_reg:x6; val_offset:60*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 60*FLEN/8, x11, x2, x5) + +inst_47: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x036 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x212 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x02f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36; op2val:0x3e12; +op3val:0x2f; valaddr_reg:x6; val_offset:63*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 63*FLEN/8, x11, x2, x5) + +inst_48: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x031 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x36d and fs3 == 0 and fe3 == 0x00 and fm3 == 0x04b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31; op2val:0x436d; +op3val:0x4b; valaddr_reg:x6; val_offset:66*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 66*FLEN/8, x11, x2, x5) + +inst_49: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x16 and fm2 == 0x31c and fs3 == 0 and fe3 == 0x00 and fm3 == 0x03a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x5b1c; +op3val:0x3a; valaddr_reg:x6; val_offset:69*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 69*FLEN/8, x11, x2, x5) + +inst_50: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x006 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x3aa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x05b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6; op2val:0xcbaa; +op3val:0x5b; valaddr_reg:x6; val_offset:72*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 72*FLEN/8, x11, x2, x5) + +inst_51: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x018 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2ea and fs3 == 0 and fe3 == 0x00 and fm3 == 0x050 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x18; op2val:0xc2ea; +op3val:0x50; valaddr_reg:x6; val_offset:75*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 75*FLEN/8, x11, x2, x5) + +inst_52: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x01a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x276 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x010 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1a; op2val:0xba76; +op3val:0x10; valaddr_reg:x6; val_offset:78*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 78*FLEN/8, x11, x2, x5) + +inst_53: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x061 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2c3 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x020 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x61; op2val:0xb6c3; +op3val:0x20; valaddr_reg:x6; val_offset:81*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 81*FLEN/8, x11, x2, x5) + +inst_54: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x022 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x02d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c; op2val:0xbc22; +op3val:0x2d; valaddr_reg:x6; val_offset:84*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 84*FLEN/8, x11, x2, x5) + +inst_55: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x042 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0c9 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x02e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x42; op2val:0xbcc9; +op3val:0x2e; valaddr_reg:x6; val_offset:87*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 87*FLEN/8, x11, x2, x5) + +inst_56: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x044 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1c3 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x021 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x44; op2val:0xbdc3; +op3val:0x21; valaddr_reg:x6; val_offset:90*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 90*FLEN/8, x11, x2, x5) + +inst_57: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0c4 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c; op2val:0xc0c4; +op3val:0xe; valaddr_reg:x6; val_offset:93*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 93*FLEN/8, x11, x2, x5) + +inst_58: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x04c and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0a5 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x060 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c; op2val:0xc4a5; +op3val:0x60; valaddr_reg:x6; val_offset:96*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 96*FLEN/8, x11, x2, x5) + +inst_59: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x030 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x1bd and fs3 == 0 and fe3 == 0x00 and fm3 == 0x026 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30; op2val:0xc9bd; +op3val:0x26; valaddr_reg:x6; val_offset:99*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 99*FLEN/8, x11, x2, x5) + +inst_60: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x005 and fs2 == 0 and fe2 == 0x16 and fm2 == 0x209 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x038 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5; op2val:0x5a09; +op3val:0x38; valaddr_reg:x6; val_offset:102*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 102*FLEN/8, x11, x2, x5) + +inst_61: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00c and fs2 == 0 and fe2 == 0x15 and fm2 == 0x12d and fs3 == 0 and fe3 == 0x00 and fm3 == 0x01b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xc; op2val:0x552d; +op3val:0x1b; valaddr_reg:x6; val_offset:105*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 105*FLEN/8, x11, x2, x5) + +inst_62: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x02c and fs2 == 0 and fe2 == 0x13 and fm2 == 0x16a and fs3 == 0 and fe3 == 0x00 and fm3 == 0x042 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2c; op2val:0x4d6a; +op3val:0x42; valaddr_reg:x6; val_offset:108*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 108*FLEN/8, x11, x2, x5) + +inst_63: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x04f and fs2 == 0 and fe2 == 0x12 and fm2 == 0x220 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x02f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4f; op2val:0x4a20; +op3val:0x2f; valaddr_reg:x6; val_offset:111*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 111*FLEN/8, x11, x2, x5) + +inst_64: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x013 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x02c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x13; op2val:0x5255; +op3val:0x2c; valaddr_reg:x6; val_offset:114*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 114*FLEN/8, x11, x2, x5) + +inst_65: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x024 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x241 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x05a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x24; op2val:0x4e41; +op3val:0x5a; valaddr_reg:x6; val_offset:117*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 117*FLEN/8, x11, x2, x5) + +inst_66: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x046 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x2c3 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x46; op2val:0x4ac3; +op3val:0xc; valaddr_reg:x6; val_offset:120*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 120*FLEN/8, x11, x2, x5) + +inst_67: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x028 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x10b and fs3 == 0 and fe3 == 0x00 and fm3 == 0x058 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x28; op2val:0x4d0b; +op3val:0x58; valaddr_reg:x6; val_offset:123*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 123*FLEN/8, x11, x2, x5) + +inst_68: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x029 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x06e and fs3 == 0 and fe3 == 0x00 and fm3 == 0x028 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x29; op2val:0x4c6e; +op3val:0x28; valaddr_reg:x6; val_offset:126*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 126*FLEN/8, x11, x2, x5) + +inst_69: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x017 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x16f and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x17; op2val:0x4d6f; +op3val:0xb; valaddr_reg:x6; val_offset:129*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 129*FLEN/8, x11, x2, x5) + +inst_70: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x051 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x26e and fs3 == 0 and fe3 == 0x00 and fm3 == 0x014 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x51; op2val:0xca6e; +op3val:0x14; valaddr_reg:x6; val_offset:132*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 132*FLEN/8, x11, x2, x5) + +inst_71: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x05d and fs2 == 1 and fe2 == 0x12 and fm2 == 0x1f7 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x059 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5d; op2val:0xc9f7; +op3val:0x59; valaddr_reg:x6; val_offset:135*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 135*FLEN/8, x11, x2, x5) + +inst_72: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x028 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x2c1 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x03e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x28; op2val:0xcec1; +op3val:0x3e; valaddr_reg:x6; val_offset:138*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 138*FLEN/8, x11, x2, x5) + +inst_73: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x015 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x298 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x05d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x15; op2val:0xd298; +op3val:0x5d; valaddr_reg:x6; val_offset:141*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 141*FLEN/8, x11, x2, x5) + +inst_74: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x16 and fm2 == 0x08b and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7; op2val:0xd88b; +op3val:0xb; valaddr_reg:x6; val_offset:144*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 144*FLEN/8, x11, x2, x5) + +inst_75: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x04d and fs2 == 1 and fe2 == 0x12 and fm2 == 0x2e2 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x045 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4d; op2val:0xcae2; +op3val:0x45; valaddr_reg:x6; val_offset:147*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 147*FLEN/8, x11, x2, x5) + +inst_76: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x034 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x0a2 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x005 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34; op2val:0xcca2; +op3val:0x5; valaddr_reg:x6; val_offset:150*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 150*FLEN/8, x11, x2, x5) + +inst_77: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x01f and fs2 == 1 and fe2 == 0x13 and fm2 == 0x3fb and fs3 == 0 and fe3 == 0x00 and fm3 == 0x05f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1f; op2val:0xcffb; +op3val:0x5f; valaddr_reg:x6; val_offset:153*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 153*FLEN/8, x11, x2, x5) + +inst_78: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x04d and fs2 == 1 and fe2 == 0x12 and fm2 == 0x145 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x02d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4d; op2val:0xc945; +op3val:0x2d; valaddr_reg:x6; val_offset:156*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 156*FLEN/8, x11, x2, x5) + +inst_79: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x021 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x051 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x03b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x21; op2val:0xcc51; +op3val:0x3b; valaddr_reg:x6; val_offset:159*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 159*FLEN/8, x11, x2, x5) + +inst_80: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x054 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x21f and fs3 == 0 and fe3 == 0x01 and fm3 == 0x036 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x454; op2val:0xaa1f; +op3val:0x436; valaddr_reg:x6; val_offset:162*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 162*FLEN/8, x11, x2, x5) + +inst_81: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x013 and fs2 == 1 and fe2 == 0x07 and fm2 == 0x1e4 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x008 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x413; op2val:0x9de4; +op3val:0x408; valaddr_reg:x6; val_offset:165*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 165*FLEN/8, x11, x2, x5) + +inst_82: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x052 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x368 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x005 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x452; op2val:0x9368; +op3val:0x405; valaddr_reg:x6; val_offset:168*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 168*FLEN/8, x11, x2, x5) + +inst_83: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x040 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x01e and fs3 == 0 and fe3 == 0x01 and fm3 == 0x02b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x440; op2val:0xa81e; +op3val:0x42b; valaddr_reg:x6; val_offset:171*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 171*FLEN/8, x11, x2, x5) + +inst_84: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x01b and fs2 == 1 and fe2 == 0x04 and fm2 == 0x3cb and fs3 == 0 and fe3 == 0x01 and fm3 == 0x011 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x41b; op2val:0x93cb; +op3val:0x411; valaddr_reg:x6; val_offset:174*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 174*FLEN/8, x11, x2, x5) + +inst_85: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x05e and fs2 == 1 and fe2 == 0x0a and fm2 == 0x0b1 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x049 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x45e; op2val:0xa8b1; +op3val:0x449; valaddr_reg:x6; val_offset:177*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 177*FLEN/8, x11, x2, x5) + +inst_86: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x011 and fs2 == 1 and fe2 == 0x09 and fm2 == 0x02e and fs3 == 0 and fe3 == 0x01 and fm3 == 0x051 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x411; op2val:0xa42e; +op3val:0x451; valaddr_reg:x6; val_offset:180*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 180*FLEN/8, x11, x2, x5) + +inst_87: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x035 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2c6 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x00e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x435; op2val:0x2ec6; +op3val:0x40e; valaddr_reg:x6; val_offset:183*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 183*FLEN/8, x11, x2, x5) + +inst_88: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x016 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x21e and fs3 == 0 and fe3 == 0x01 and fm3 == 0x038 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x416; op2val:0x321e; +op3val:0x438; valaddr_reg:x6; val_offset:186*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 186*FLEN/8, x11, x2, x5) + +inst_89: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x030 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x357 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x014 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x430; op2val:0x3757; +op3val:0x414; valaddr_reg:x6; val_offset:189*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 189*FLEN/8, x11, x2, x5) + +inst_90: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x008 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x013 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x036 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x408; op2val:0xc013; +op3val:0x436; valaddr_reg:x6; val_offset:192*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 192*FLEN/8, x11, x2, x5) + +inst_91: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x026 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3ca and fs3 == 0 and fe3 == 0x01 and fm3 == 0x013 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x426; op2val:0xbfca; +op3val:0x413; valaddr_reg:x6; val_offset:195*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 195*FLEN/8, x11, x2, x5) + +inst_92: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x03b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3df and fs3 == 0 and fe3 == 0x01 and fm3 == 0x050 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x43b; op2val:0xbfdf; +op3val:0x450; valaddr_reg:x6; val_offset:198*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 198*FLEN/8, x11, x2, x5) + +inst_93: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x016 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x00f and fs3 == 0 and fe3 == 0x01 and fm3 == 0x043 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x416; op2val:0xc00f; +op3val:0x443; valaddr_reg:x6; val_offset:201*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 201*FLEN/8, x11, x2, x5) + +inst_94: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x03b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3db and fs3 == 0 and fe3 == 0x01 and fm3 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x43b; op2val:0xbfdb; +op3val:0x43f; valaddr_reg:x6; val_offset:204*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 204*FLEN/8, x11, x2, x5) + +inst_95: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x059 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3d0 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x05e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x459; op2val:0xbfd0; +op3val:0x45e; valaddr_reg:x6; val_offset:207*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 207*FLEN/8, x11, x2, x5) + +inst_96: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x029 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x015 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x03e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x429; op2val:0xc015; +op3val:0x43e; valaddr_reg:x6; val_offset:210*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 210*FLEN/8, x11, x2, x5) + +inst_97: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x024 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x02d and fs3 == 0 and fe3 == 0x01 and fm3 == 0x026 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x424; op2val:0xc02d; +op3val:0x426; valaddr_reg:x6; val_offset:213*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 213*FLEN/8, x11, x2, x5) + +inst_98: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x03d and fs2 == 1 and fe2 == 0x10 and fm2 == 0x057 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x034 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x43d; op2val:0xc057; +op3val:0x434; valaddr_reg:x6; val_offset:216*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 216*FLEN/8, x11, x2, x5) + +inst_99: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x013 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0f0 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x413; op2val:0xc0f0; +op3val:0x40f; valaddr_reg:x6; val_offset:219*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 219*FLEN/8, x11, x2, x5) + +inst_100: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x031 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x31a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x045 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7831; op2val:0x3b1a; +op3val:0x7845; valaddr_reg:x6; val_offset:222*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 222*FLEN/8, x11, x2, x5) + +inst_101: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x017 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x32e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x051 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7817; op2val:0x3b2e; +op3val:0x7851; valaddr_reg:x6; val_offset:225*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 225*FLEN/8, x11, x2, x5) + +inst_102: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x040 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x32b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x02c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7840; op2val:0x3b2b; +op3val:0x782c; valaddr_reg:x6; val_offset:228*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 228*FLEN/8, x11, x2, x5) + +inst_103: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x018 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3a8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7818; op2val:0x3ba8; +op3val:0x780c; valaddr_reg:x6; val_offset:231*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 231*FLEN/8, x11, x2, x5) + +inst_104: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x03f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x327 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x023 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x783f; op2val:0x3b27; +op3val:0x7823; valaddr_reg:x6; val_offset:234*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 234*FLEN/8, x11, x2, x5) + +inst_105: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x042 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2c0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x047 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7842; op2val:0x3ac0; +op3val:0x7847; valaddr_reg:x6; val_offset:237*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 237*FLEN/8, x11, x2, x5) + +inst_106: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x041 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2b3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x02f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7841; op2val:0x3ab3; +op3val:0x782f; valaddr_reg:x6; val_offset:240*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 240*FLEN/8, x11, x2, x5) + +inst_107: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x009 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x293 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x02e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7809; op2val:0x3a93; +op3val:0x782e; valaddr_reg:x6; val_offset:243*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 243*FLEN/8, x11, x2, x5) + +inst_108: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x059 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0f7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x04c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7859; op2val:0x38f7; +op3val:0x784c; valaddr_reg:x6; val_offset:246*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 246*FLEN/8, x11, x2, x5) + +inst_109: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x055 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x34c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x005 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7855; op2val:0x374c; +op3val:0x7805; valaddr_reg:x6; val_offset:249*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 249*FLEN/8, x11, x2, x5) + +inst_110: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x062 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x18b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x028 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7862; op2val:0xc18b; +op3val:0x7828; valaddr_reg:x6; val_offset:252*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 252*FLEN/8, x11, x2, x5) + +inst_111: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1dd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x048 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x782f; op2val:0xc1dd; +op3val:0x7848; valaddr_reg:x6; val_offset:255*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 255*FLEN/8, x11, x2, x5) + +inst_112: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x05b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1a7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x056 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x785b; op2val:0xc1a7; +op3val:0x7856; valaddr_reg:x6; val_offset:258*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 258*FLEN/8, x11, x2, x5) + +inst_113: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x024 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7824; op2val:0xc1e5; +op3val:0x783f; valaddr_reg:x6; val_offset:261*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 261*FLEN/8, x11, x2, x5) + +inst_114: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x022 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1f6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x063 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7822; op2val:0xc1f6; +op3val:0x7863; valaddr_reg:x6; val_offset:264*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 264*FLEN/8, x11, x2, x5) + +inst_115: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x059 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1a0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x05c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7859; op2val:0xc1a0; +op3val:0x785c; valaddr_reg:x6; val_offset:267*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 267*FLEN/8, x11, x2, x5) + +inst_116: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x026 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1be and fs3 == 0 and fe3 == 0x1e and fm3 == 0x02c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7826; op2val:0xc1be; +op3val:0x782c; valaddr_reg:x6; val_offset:270*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 270*FLEN/8, x11, x2, x5) + +inst_117: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x054 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x15a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x017 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7854; op2val:0xc15a; +op3val:0x7817; valaddr_reg:x6; val_offset:273*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 273*FLEN/8, x11, x2, x5) + +inst_118: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x120 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x784b; op2val:0xc120; +op3val:0x7802; valaddr_reg:x6; val_offset:276*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 276*FLEN/8, x11, x2, x5) + +inst_119: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x03d and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0d9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x047 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x783d; op2val:0xc0d9; +op3val:0x7847; valaddr_reg:x6; val_offset:279*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 279*FLEN/8, x11, x2, x5) + +inst_120: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x050 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x266 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x021 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x50; op2val:0xb666; +op3val:0x21; valaddr_reg:x6; val_offset:282*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 282*FLEN/8, x11, x2, x5) + +inst_121: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x05f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x369 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x02e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5f; op2val:0xb769; +op3val:0x2e; valaddr_reg:x6; val_offset:285*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 285*FLEN/8, x11, x2, x5) + +inst_122: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x054 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1b6 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x044 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x54; op2val:0xb9b6; +op3val:0x44; valaddr_reg:x6; val_offset:288*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 288*FLEN/8, x11, x2, x5) + +inst_123: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x020 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x280 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x054 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x20; op2val:0xbe80; +op3val:0x54; valaddr_reg:x6; val_offset:291*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 291*FLEN/8, x11, x2, x5) + +inst_124: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00f and fs2 == 0 and fe2 == 0x11 and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x030 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xf; op2val:0x4555; +op3val:0x30; valaddr_reg:x6; val_offset:294*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 294*FLEN/8, x11, x2, x5) + +inst_125: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x358 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x020 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3d; op2val:0x4358; +op3val:0x20; valaddr_reg:x6; val_offset:297*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 297*FLEN/8, x11, x2, x5) + +inst_126: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x031 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x082 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x046 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31; op2val:0x4882; +op3val:0x46; valaddr_reg:x6; val_offset:300*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 300*FLEN/8, x11, x2, x5) + +inst_127: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 1 and fe2 == 0x11 and fm2 == 0x15b and fs3 == 0 and fe3 == 0x00 and fm3 == 0x04a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xe; op2val:0xc55b; +op3val:0x4a; valaddr_reg:x6; val_offset:303*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 303*FLEN/8, x11, x2, x5) + +inst_128: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x020 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x20; op2val:0xb000; +op3val:0x2; valaddr_reg:x6; val_offset:306*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 306*FLEN/8, x11, x2, x5) + +inst_129: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x01a and fs2 == 1 and fe2 == 0x0a and fm2 == 0x295 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x046 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c1a; op2val:0xaa95; +op3val:0x3c46; valaddr_reg:x6; val_offset:309*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 309*FLEN/8, x11, x2, x5) + +inst_130: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x003 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x33e and fs3 == 0 and fe3 == 0x0f and fm3 == 0x02f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c03; op2val:0x373e; +op3val:0x3c2f; valaddr_reg:x6; val_offset:312*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 312*FLEN/8, x11, x2, x5) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(80,32,FLEN) +NAN_BOXED(80,16,FLEN) +NAN_BOXED(33,32,FLEN) +NAN_BOXED(95,32,FLEN) +NAN_BOXED(46953,16,FLEN) +NAN_BOXED(95,32,FLEN) +NAN_BOXED(89,32,FLEN) +NAN_BOXED(48151,16,FLEN) +NAN_BOXED(95,32,FLEN) +NAN_BOXED(84,32,FLEN) +NAN_BOXED(84,16,FLEN) +NAN_BOXED(84,32,FLEN) +NAN_BOXED(4,32,FLEN) +NAN_BOXED(51584,16,FLEN) +NAN_BOXED(60,32,FLEN) +NAN_BOXED(32,32,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(84,32,FLEN) +NAN_BOXED(7,32,FLEN) +NAN_BOXED(17956,32,FLEN) +NAN_BOXED(21,32,FLEN) +NAN_BOXED(15,32,FLEN) +NAN_BOXED(17749,32,FLEN) +NAN_BOXED(17749,32,FLEN) +NAN_BOXED(61,32,FLEN) +NAN_BOXED(17240,32,FLEN) +NAN_BOXED(61,32,FLEN) +NAN_BOXED(49,32,FLEN) +NAN_BOXED(49,32,FLEN) +NAN_BOXED(49,32,FLEN) +NAN_BOXED(14,32,FLEN) +NAN_BOXED(50523,16,FLEN) +NAN_BOXED(50523,32,FLEN) +NAN_BOXED(32,32,FLEN) +NAN_BOXED(32,16,FLEN) +NAN_BOXED(2,32,FLEN) +NAN_BOXED(94,32,FLEN) +NAN_BOXED(46450,16,FLEN) +NAN_BOXED(28,32,FLEN) +test_dataset_1: +NAN_BOXED(53,32,FLEN) +NAN_BOXED(47780,16,FLEN) +NAN_BOXED(36,32,FLEN) +NAN_BOXED(24,32,FLEN) +NAN_BOXED(50378,16,FLEN) +NAN_BOXED(99,32,FLEN) +NAN_BOXED(50,32,FLEN) +NAN_BOXED(48189,16,FLEN) +NAN_BOXED(21,32,FLEN) +NAN_BOXED(98,32,FLEN) +NAN_BOXED(47626,16,FLEN) +NAN_BOXED(10,32,FLEN) +NAN_BOXED(18,32,FLEN) +NAN_BOXED(51655,16,FLEN) +NAN_BOXED(80,32,FLEN) +NAN_BOXED(80,32,FLEN) +NAN_BOXED(50131,16,FLEN) +NAN_BOXED(57,32,FLEN) +NAN_BOXED(17,32,FLEN) +NAN_BOXED(53191,16,FLEN) +NAN_BOXED(17,32,FLEN) +NAN_BOXED(15361,32,FLEN) +NAN_BOXED(240,32,FLEN) +NAN_BOXED(15361,32,FLEN) +NAN_BOXED(15387,32,FLEN) +NAN_BOXED(42581,16,FLEN) +NAN_BOXED(15388,32,FLEN) +NAN_BOXED(15382,32,FLEN) +NAN_BOXED(42087,16,FLEN) +NAN_BOXED(15382,32,FLEN) +NAN_BOXED(15398,32,FLEN) +NAN_BOXED(42996,16,FLEN) +NAN_BOXED(15401,32,FLEN) +NAN_BOXED(15386,32,FLEN) +NAN_BOXED(43669,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(15447,32,FLEN) +NAN_BOXED(43429,16,FLEN) +NAN_BOXED(15441,32,FLEN) +test_dataset_2: +NAN_BOXED(15387,16,FLEN) +NAN_BOXED(10463,16,FLEN) +NAN_BOXED(15384,16,FLEN) +NAN_BOXED(15449,16,FLEN) +NAN_BOXED(11741,16,FLEN) +NAN_BOXED(15386,16,FLEN) +NAN_BOXED(15410,16,FLEN) +NAN_BOXED(12919,16,FLEN) +NAN_BOXED(15399,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(14142,16,FLEN) +NAN_BOXED(15407,16,FLEN) +NAN_BOXED(15414,16,FLEN) +NAN_BOXED(49071,16,FLEN) +NAN_BOXED(15382,16,FLEN) +NAN_BOXED(15379,16,FLEN) +NAN_BOXED(49150,16,FLEN) +NAN_BOXED(15394,16,FLEN) +NAN_BOXED(15369,16,FLEN) +NAN_BOXED(49166,16,FLEN) +NAN_BOXED(15403,16,FLEN) +NAN_BOXED(15399,16,FLEN) +NAN_BOXED(49155,16,FLEN) +NAN_BOXED(15438,16,FLEN) +NAN_BOXED(15436,16,FLEN) +NAN_BOXED(49026,16,FLEN) +NAN_BOXED(15361,16,FLEN) +NAN_BOXED(15437,16,FLEN) +NAN_BOXED(49119,16,FLEN) +NAN_BOXED(15447,16,FLEN) +NAN_BOXED(15451,16,FLEN) +NAN_BOXED(49084,16,FLEN) +NAN_BOXED(15404,16,FLEN) +NAN_BOXED(15369,16,FLEN) +NAN_BOXED(49226,16,FLEN) +NAN_BOXED(15400,16,FLEN) +NAN_BOXED(15406,16,FLEN) +NAN_BOXED(49249,16,FLEN) +NAN_BOXED(15400,16,FLEN) +NAN_BOXED(15422,16,FLEN) +NAN_BOXED(49377,16,FLEN) +NAN_BOXED(15450,16,FLEN) +NAN_BOXED(41,16,FLEN) +NAN_BOXED(47228,16,FLEN) +NAN_BOXED(24,16,FLEN) +NAN_BOXED(62,16,FLEN) +NAN_BOXED(47995,16,FLEN) +NAN_BOXED(61,16,FLEN) +NAN_BOXED(91,16,FLEN) +NAN_BOXED(45652,16,FLEN) +NAN_BOXED(23,16,FLEN) +NAN_BOXED(8,16,FLEN) +NAN_BOXED(49664,16,FLEN) +NAN_BOXED(33,16,FLEN) +NAN_BOXED(3,16,FLEN) +NAN_BOXED(52885,16,FLEN) +NAN_BOXED(96,16,FLEN) +NAN_BOXED(46,16,FLEN) +NAN_BOXED(46747,16,FLEN) +NAN_BOXED(52,16,FLEN) +NAN_BOXED(3,16,FLEN) +NAN_BOXED(49152,16,FLEN) +NAN_BOXED(71,16,FLEN) +NAN_BOXED(54,16,FLEN) +NAN_BOXED(15890,16,FLEN) +NAN_BOXED(47,16,FLEN) +NAN_BOXED(49,16,FLEN) +NAN_BOXED(17261,16,FLEN) +NAN_BOXED(75,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(23324,16,FLEN) +NAN_BOXED(58,16,FLEN) +NAN_BOXED(6,16,FLEN) +NAN_BOXED(52138,16,FLEN) +NAN_BOXED(91,16,FLEN) +NAN_BOXED(24,16,FLEN) +NAN_BOXED(49898,16,FLEN) +NAN_BOXED(80,16,FLEN) +NAN_BOXED(26,16,FLEN) +NAN_BOXED(47734,16,FLEN) +NAN_BOXED(16,16,FLEN) +NAN_BOXED(97,16,FLEN) +NAN_BOXED(46787,16,FLEN) +NAN_BOXED(32,16,FLEN) +NAN_BOXED(60,16,FLEN) +NAN_BOXED(48162,16,FLEN) +NAN_BOXED(45,16,FLEN) +NAN_BOXED(66,16,FLEN) +NAN_BOXED(48329,16,FLEN) +NAN_BOXED(46,16,FLEN) +NAN_BOXED(68,16,FLEN) +NAN_BOXED(48579,16,FLEN) +NAN_BOXED(33,16,FLEN) +NAN_BOXED(60,16,FLEN) +NAN_BOXED(49348,16,FLEN) +NAN_BOXED(14,16,FLEN) +NAN_BOXED(76,16,FLEN) +NAN_BOXED(50341,16,FLEN) +NAN_BOXED(96,16,FLEN) +NAN_BOXED(48,16,FLEN) +NAN_BOXED(51645,16,FLEN) +NAN_BOXED(38,16,FLEN) +NAN_BOXED(5,16,FLEN) +NAN_BOXED(23049,16,FLEN) +NAN_BOXED(56,16,FLEN) +NAN_BOXED(12,16,FLEN) +NAN_BOXED(21805,16,FLEN) +NAN_BOXED(27,16,FLEN) +NAN_BOXED(44,16,FLEN) +NAN_BOXED(19818,16,FLEN) +NAN_BOXED(66,16,FLEN) +NAN_BOXED(79,16,FLEN) +NAN_BOXED(18976,16,FLEN) +NAN_BOXED(47,16,FLEN) +NAN_BOXED(19,16,FLEN) +NAN_BOXED(21077,16,FLEN) +NAN_BOXED(44,16,FLEN) +NAN_BOXED(36,16,FLEN) +NAN_BOXED(20033,16,FLEN) +NAN_BOXED(90,16,FLEN) +NAN_BOXED(70,16,FLEN) +NAN_BOXED(19139,16,FLEN) +NAN_BOXED(12,16,FLEN) +NAN_BOXED(40,16,FLEN) +NAN_BOXED(19723,16,FLEN) +NAN_BOXED(88,16,FLEN) +NAN_BOXED(41,16,FLEN) +NAN_BOXED(19566,16,FLEN) +NAN_BOXED(40,16,FLEN) +NAN_BOXED(23,16,FLEN) +NAN_BOXED(19823,16,FLEN) +NAN_BOXED(11,16,FLEN) +NAN_BOXED(81,16,FLEN) +NAN_BOXED(51822,16,FLEN) +NAN_BOXED(20,16,FLEN) +NAN_BOXED(93,16,FLEN) +NAN_BOXED(51703,16,FLEN) +NAN_BOXED(89,16,FLEN) +NAN_BOXED(40,16,FLEN) +NAN_BOXED(52929,16,FLEN) +NAN_BOXED(62,16,FLEN) +NAN_BOXED(21,16,FLEN) +NAN_BOXED(53912,16,FLEN) +NAN_BOXED(93,16,FLEN) +NAN_BOXED(7,16,FLEN) +NAN_BOXED(55435,16,FLEN) +NAN_BOXED(11,16,FLEN) +NAN_BOXED(77,16,FLEN) +NAN_BOXED(51938,16,FLEN) +NAN_BOXED(69,16,FLEN) +NAN_BOXED(52,16,FLEN) +NAN_BOXED(52386,16,FLEN) +NAN_BOXED(5,16,FLEN) +NAN_BOXED(31,16,FLEN) +NAN_BOXED(53243,16,FLEN) +NAN_BOXED(95,16,FLEN) +NAN_BOXED(77,16,FLEN) +NAN_BOXED(51525,16,FLEN) +NAN_BOXED(45,16,FLEN) +NAN_BOXED(33,16,FLEN) +NAN_BOXED(52305,16,FLEN) +NAN_BOXED(59,16,FLEN) +NAN_BOXED(1108,16,FLEN) +NAN_BOXED(43551,16,FLEN) +NAN_BOXED(1078,16,FLEN) +NAN_BOXED(1043,16,FLEN) +NAN_BOXED(40420,16,FLEN) +NAN_BOXED(1032,16,FLEN) +NAN_BOXED(1106,16,FLEN) +NAN_BOXED(37736,16,FLEN) +NAN_BOXED(1029,16,FLEN) +NAN_BOXED(1088,16,FLEN) +NAN_BOXED(43038,16,FLEN) +NAN_BOXED(1067,16,FLEN) +NAN_BOXED(1051,16,FLEN) +NAN_BOXED(37835,16,FLEN) +NAN_BOXED(1041,16,FLEN) +NAN_BOXED(1118,16,FLEN) +NAN_BOXED(43185,16,FLEN) +NAN_BOXED(1097,16,FLEN) +NAN_BOXED(1041,16,FLEN) +NAN_BOXED(42030,16,FLEN) +NAN_BOXED(1105,16,FLEN) +NAN_BOXED(1077,16,FLEN) +NAN_BOXED(11974,16,FLEN) +NAN_BOXED(1038,16,FLEN) +NAN_BOXED(1046,16,FLEN) +NAN_BOXED(12830,16,FLEN) +NAN_BOXED(1080,16,FLEN) +NAN_BOXED(1072,16,FLEN) +NAN_BOXED(14167,16,FLEN) +NAN_BOXED(1044,16,FLEN) +NAN_BOXED(1032,16,FLEN) +NAN_BOXED(49171,16,FLEN) +NAN_BOXED(1078,16,FLEN) +NAN_BOXED(1062,16,FLEN) +NAN_BOXED(49098,16,FLEN) +NAN_BOXED(1043,16,FLEN) +NAN_BOXED(1083,16,FLEN) +NAN_BOXED(49119,16,FLEN) +NAN_BOXED(1104,16,FLEN) +NAN_BOXED(1046,16,FLEN) +NAN_BOXED(49167,16,FLEN) +NAN_BOXED(1091,16,FLEN) +NAN_BOXED(1083,16,FLEN) +NAN_BOXED(49115,16,FLEN) +NAN_BOXED(1087,16,FLEN) +NAN_BOXED(1113,16,FLEN) +NAN_BOXED(49104,16,FLEN) +NAN_BOXED(1118,16,FLEN) +NAN_BOXED(1065,16,FLEN) +NAN_BOXED(49173,16,FLEN) +NAN_BOXED(1086,16,FLEN) +NAN_BOXED(1060,16,FLEN) +NAN_BOXED(49197,16,FLEN) +NAN_BOXED(1062,16,FLEN) +NAN_BOXED(1085,16,FLEN) +NAN_BOXED(49239,16,FLEN) +NAN_BOXED(1076,16,FLEN) +NAN_BOXED(1043,16,FLEN) +NAN_BOXED(49392,16,FLEN) +NAN_BOXED(1039,16,FLEN) +NAN_BOXED(30769,16,FLEN) +NAN_BOXED(15130,16,FLEN) +NAN_BOXED(30789,16,FLEN) +NAN_BOXED(30743,16,FLEN) +NAN_BOXED(15150,16,FLEN) +NAN_BOXED(30801,16,FLEN) +NAN_BOXED(30784,16,FLEN) +NAN_BOXED(15147,16,FLEN) +NAN_BOXED(30764,16,FLEN) +NAN_BOXED(30744,16,FLEN) +NAN_BOXED(15272,16,FLEN) +NAN_BOXED(30732,16,FLEN) +NAN_BOXED(30783,16,FLEN) +NAN_BOXED(15143,16,FLEN) +NAN_BOXED(30755,16,FLEN) +NAN_BOXED(30786,16,FLEN) +NAN_BOXED(15040,16,FLEN) +NAN_BOXED(30791,16,FLEN) +NAN_BOXED(30785,16,FLEN) +NAN_BOXED(15027,16,FLEN) +NAN_BOXED(30767,16,FLEN) +NAN_BOXED(30729,16,FLEN) +NAN_BOXED(14995,16,FLEN) +NAN_BOXED(30766,16,FLEN) +NAN_BOXED(30809,16,FLEN) +NAN_BOXED(14583,16,FLEN) +NAN_BOXED(30796,16,FLEN) +NAN_BOXED(30805,16,FLEN) +NAN_BOXED(14156,16,FLEN) +NAN_BOXED(30725,16,FLEN) +NAN_BOXED(30818,16,FLEN) +NAN_BOXED(49547,16,FLEN) +NAN_BOXED(30760,16,FLEN) +NAN_BOXED(30767,16,FLEN) +NAN_BOXED(49629,16,FLEN) +NAN_BOXED(30792,16,FLEN) +NAN_BOXED(30811,16,FLEN) +NAN_BOXED(49575,16,FLEN) +NAN_BOXED(30806,16,FLEN) +NAN_BOXED(30756,16,FLEN) +NAN_BOXED(49637,16,FLEN) +NAN_BOXED(30783,16,FLEN) +NAN_BOXED(30754,16,FLEN) +NAN_BOXED(49654,16,FLEN) +NAN_BOXED(30819,16,FLEN) +NAN_BOXED(30809,16,FLEN) +NAN_BOXED(49568,16,FLEN) +NAN_BOXED(30812,16,FLEN) +NAN_BOXED(30758,16,FLEN) +NAN_BOXED(49598,16,FLEN) +NAN_BOXED(30764,16,FLEN) +NAN_BOXED(30804,16,FLEN) +NAN_BOXED(49498,16,FLEN) +NAN_BOXED(30743,16,FLEN) +NAN_BOXED(30795,16,FLEN) +NAN_BOXED(49440,16,FLEN) +NAN_BOXED(30722,16,FLEN) +NAN_BOXED(30781,16,FLEN) +NAN_BOXED(49369,16,FLEN) +NAN_BOXED(30791,16,FLEN) +NAN_BOXED(80,16,FLEN) +NAN_BOXED(46694,16,FLEN) +NAN_BOXED(33,16,FLEN) +NAN_BOXED(95,16,FLEN) +NAN_BOXED(46953,16,FLEN) +NAN_BOXED(46,16,FLEN) +NAN_BOXED(84,16,FLEN) +NAN_BOXED(47542,16,FLEN) +NAN_BOXED(68,16,FLEN) +NAN_BOXED(32,16,FLEN) +NAN_BOXED(48768,16,FLEN) +NAN_BOXED(84,16,FLEN) +NAN_BOXED(15,16,FLEN) +NAN_BOXED(17749,16,FLEN) +NAN_BOXED(48,16,FLEN) +NAN_BOXED(61,16,FLEN) +NAN_BOXED(17240,16,FLEN) +NAN_BOXED(32,16,FLEN) +NAN_BOXED(49,16,FLEN) +NAN_BOXED(18562,16,FLEN) +NAN_BOXED(70,16,FLEN) +NAN_BOXED(14,16,FLEN) +NAN_BOXED(50523,16,FLEN) +NAN_BOXED(74,16,FLEN) +NAN_BOXED(32,16,FLEN) +NAN_BOXED(45056,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(15386,16,FLEN) +NAN_BOXED(43669,16,FLEN) +NAN_BOXED(15430,16,FLEN) +NAN_BOXED(15363,16,FLEN) +NAN_BOXED(14142,16,FLEN) +NAN_BOXED(15407,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x3_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x3_1: + .fill 30*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_0: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_0: + .fill 204*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fmadd_b3-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fmadd_b3-01.S new file mode 100644 index 000000000..ea3ad4093 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fmadd_b3-01.S @@ -0,0 +1,11466 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 04:10:09 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fmadd.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fmadd.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fmadd_b3 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fmadd_b3) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x9,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==x27, rs2==x27, rs3==x1, rd==x11,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0c3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ee and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x27; op2:x27; op3:x1; dest:x11; op1val:0x78fb; op2val:0x78fb; +op3val:0x79ee; valaddr_reg:x9; val_offset:0*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x11, x27, x27, x1, dyn, 0, 0, x9, 0*FLEN/8, x13, x1, x4) + +inst_1: +// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==x14, rs2==x17, rs3==x14, rd==x24,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0c3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ee and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x14; op2:x17; op3:x14; dest:x24; op1val:0x78fb; op2val:0xbcc3; +op3val:0x78fb; valaddr_reg:x9; val_offset:3*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x24, x14, x17, x14, dyn, 32, 0, x9, 3*FLEN/8, x13, x1, x4) + +inst_2: +// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==x3, rs2==x25, rs3==x9, rd==x3,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0c3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ee and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x3; op2:x25; op3:x9; dest:x3; op1val:0x78fb; op2val:0xbcc3; +op3val:0x79ee; valaddr_reg:x9; val_offset:6*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x3, x3, x25, x9, dyn, 64, 0, x9, 6*FLEN/8, x13, x1, x4) + +inst_3: +// rs1 == rs2 == rs3 != rd, rs1==x18, rs2==x18, rs3==x18, rd==x12,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0c3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ee and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x18; op2:x18; op3:x18; dest:x12; op1val:0x78fb; op2val:0x78fb; +op3val:0x78fb; valaddr_reg:x9; val_offset:9*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x12, x18, x18, x18, dyn, 96, 0, x9, 9*FLEN/8, x13, x1, x4) + +inst_4: +// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==x5, rs2==x2, rs3==x7, rd==x7,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0c3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ee and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x5; op2:x2; op3:x7; dest:x7; op1val:0x78fb; op2val:0xbcc3; +op3val:0x79ee; valaddr_reg:x9; val_offset:12*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x7, x5, x2, x7, dyn, 128, 0, x9, 12*FLEN/8, x13, x1, x4) + +inst_5: +// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==x15, rs2==x26, rs3==x24, rd==x26,fs1 == 0 and fe1 == 0x1e and fm1 == 0x25b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0bd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x389 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x15; op2:x26; op3:x24; dest:x26; op1val:0x7a5b; op2val:0xbcbd; +op3val:0x7b89; valaddr_reg:x9; val_offset:15*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x26, x15, x26, x24, dyn, 0, 0, x9, 15*FLEN/8, x13, x1, x4) + +inst_6: +// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==x28, rs2==x12, rs3==x29, rd==x10,fs1 == 0 and fe1 == 0x1e and fm1 == 0x25b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0bd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x389 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x28; op2:x12; op3:x29; dest:x10; op1val:0x7a5b; op2val:0xbcbd; +op3val:0x7b89; valaddr_reg:x9; val_offset:18*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x10, x28, x12, x29, dyn, 32, 0, x9, 18*FLEN/8, x13, x1, x4) + +inst_7: +// rd == rs2 == rs3 != rs1, rs1==x23, rs2==x30, rs3==x30, rd==x30,fs1 == 0 and fe1 == 0x1e and fm1 == 0x25b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0bd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x389 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x23; op2:x30; op3:x30; dest:x30; op1val:0x7a5b; op2val:0xbcbd; +op3val:0xbcbd; valaddr_reg:x9; val_offset:21*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x30, x23, x30, x30, dyn, 64, 0, x9, 21*FLEN/8, x13, x1, x4) + +inst_8: +// rs1 == rd == rs3 != rs2, rs1==x6, rs2==x22, rs3==x6, rd==x6,fs1 == 0 and fe1 == 0x1e and fm1 == 0x25b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0bd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x389 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x6; op2:x22; op3:x6; dest:x6; op1val:0x7a5b; op2val:0xbcbd; +op3val:0x7a5b; valaddr_reg:x9; val_offset:24*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x6, x6, x22, x6, dyn, 96, 0, x9, 24*FLEN/8, x13, x1, x4) + +inst_9: +// rs1 == rs2 == rs3 == rd, rs1==x19, rs2==x19, rs3==x19, rd==x19,fs1 == 0 and fe1 == 0x1e and fm1 == 0x25b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0bd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x389 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x19; op2:x19; op3:x19; dest:x19; op1val:0x7a5b; op2val:0x7a5b; +op3val:0x7a5b; valaddr_reg:x9; val_offset:27*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x19, x19, x19, x19, dyn, 128, 0, x9, 27*FLEN/8, x13, x1, x4) + +inst_10: +// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==x8, rs2==x20, rs3==x20, rd==x22,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ea and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0fc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x360 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x8; op2:x20; op3:x20; dest:x22; op1val:0x79ea; op2val:0xbcfc; +op3val:0xbcfc; valaddr_reg:x9; val_offset:30*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x22, x8, x20, x20, dyn, 0, 0, x9, 30*FLEN/8, x13, x1, x4) +RVTEST_VALBASEUPD(x6,test_dataset_1) + +inst_11: +// rs1 == rs2 == rd != rs3, rs1==x29, rs2==x29, rs3==x23, rd==x29,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ea and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0fc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x360 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x29; op2:x29; op3:x23; dest:x29; op1val:0x79ea; op2val:0x79ea; +op3val:0x7b60; valaddr_reg:x6; val_offset:0*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x29, x29, x29, x23, dyn, 32, 0, x6, 0*FLEN/8, x10, x1, x4) + +inst_12: +// rs1==x4, rs2==x23, rs3==x28, rd==x8,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ea and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0fc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x360 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x4; op2:x23; op3:x28; dest:x8; op1val:0x79ea; op2val:0xbcfc; +op3val:0x7b60; valaddr_reg:x6; val_offset:3*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x8, x4, x23, x28, dyn, 64, 0, x6, 3*FLEN/8, x10, x1, x12) +RVTEST_SIGBASE(x3,signature_x3_0) + +inst_13: +// rs1==x21, rs2==x0, rs3==x3, rd==x17,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ea and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0fc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x360 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x21; op2:x0; op3:x3; dest:x17; op1val:0x79ea; op2val:0x0; +op3val:0x7b60; valaddr_reg:x6; val_offset:6*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x17, x21, x0, x3, dyn, 96, 0, x6, 6*FLEN/8, x10, x3, x12) + +inst_14: +// rs1==x16, rs2==x28, rs3==x2, rd==x5,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ea and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0fc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x360 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x16; op2:x28; op3:x2; dest:x5; op1val:0x79ea; op2val:0xbcfc; +op3val:0x7b60; valaddr_reg:x6; val_offset:9*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x5, x16, x28, x2, dyn, 128, 0, x6, 9*FLEN/8, x10, x3, x12) + +inst_15: +// rs1==x20, rs2==x8, rs3==x21, rd==x13,fs1 == 0 and fe1 == 0x19 and fm1 == 0x36c and fs2 == 1 and fe2 == 0x13 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x372 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x20; op2:x8; op3:x21; dest:x13; op1val:0x676c; op2val:0xcc02; +op3val:0x7772; valaddr_reg:x6; val_offset:12*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x13, x20, x8, x21, dyn, 0, 0, x6, 12*FLEN/8, x10, x3, x12) + +inst_16: +// rs1==x11, rs2==x14, rs3==x12, rd==x28,fs1 == 0 and fe1 == 0x19 and fm1 == 0x36c and fs2 == 1 and fe2 == 0x13 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x372 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x11; op2:x14; op3:x12; dest:x28; op1val:0x676c; op2val:0xcc02; +op3val:0x7772; valaddr_reg:x6; val_offset:15*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x28, x11, x14, x12, dyn, 32, 0, x6, 15*FLEN/8, x10, x3, x12) + +inst_17: +// rs1==x2, rs2==x16, rs3==x4, rd==x20,fs1 == 0 and fe1 == 0x19 and fm1 == 0x36c and fs2 == 1 and fe2 == 0x13 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x372 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x2; op2:x16; op3:x4; dest:x20; op1val:0x676c; op2val:0xcc02; +op3val:0x7772; valaddr_reg:x6; val_offset:18*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x20, x2, x16, x4, dyn, 64, 0, x6, 18*FLEN/8, x10, x3, x12) + +inst_18: +// rs1==x17, rs2==x21, rs3==x25, rd==x31,fs1 == 0 and fe1 == 0x19 and fm1 == 0x36c and fs2 == 1 and fe2 == 0x13 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x372 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x17; op2:x21; op3:x25; dest:x31; op1val:0x676c; op2val:0xcc02; +op3val:0x7772; valaddr_reg:x6; val_offset:21*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x17, x21, x25, dyn, 96, 0, x6, 21*FLEN/8, x10, x3, x12) + +inst_19: +// rs1==x30, rs2==x1, rs3==x31, rd==x16,fs1 == 0 and fe1 == 0x19 and fm1 == 0x36c and fs2 == 1 and fe2 == 0x13 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x372 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x1; op3:x31; dest:x16; op1val:0x676c; op2val:0xcc02; +op3val:0x7772; valaddr_reg:x6; val_offset:24*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x16, x30, x1, x31, dyn, 128, 0, x6, 24*FLEN/8, x10, x3, x12) + +inst_20: +// rs1==x31, rs2==x11, rs3==x17, rd==x0,fs1 == 0 and fe1 == 0x1e and fm1 == 0x38b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x180 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x130 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x31; op2:x11; op3:x17; dest:x0; op1val:0x7b8b; op2val:0xb980; +op3val:0x7930; valaddr_reg:x6; val_offset:27*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x0, x31, x11, x17, dyn, 0, 0, x6, 27*FLEN/8, x10, x3, x12) + +inst_21: +// rs1==x13, rs2==x9, rs3==x8, rd==x25,fs1 == 0 and fe1 == 0x1e and fm1 == 0x38b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x180 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x130 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x13; op2:x9; op3:x8; dest:x25; op1val:0x7b8b; op2val:0xb980; +op3val:0x7930; valaddr_reg:x6; val_offset:30*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x25, x13, x9, x8, dyn, 32, 0, x6, 30*FLEN/8, x10, x3, x12) + +inst_22: +// rs1==x22, rs2==x5, rs3==x13, rd==x27,fs1 == 0 and fe1 == 0x1e and fm1 == 0x38b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x180 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x130 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x22; op2:x5; op3:x13; dest:x27; op1val:0x7b8b; op2val:0xb980; +op3val:0x7930; valaddr_reg:x6; val_offset:33*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x27, x22, x5, x13, dyn, 64, 0, x6, 33*FLEN/8, x10, x3, x12) + +inst_23: +// rs1==x7, rs2==x31, rs3==x15, rd==x9,fs1 == 0 and fe1 == 0x1e and fm1 == 0x38b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x180 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x130 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x7; op2:x31; op3:x15; dest:x9; op1val:0x7b8b; op2val:0xb980; +op3val:0x7930; valaddr_reg:x6; val_offset:36*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x9, x7, x31, x15, dyn, 96, 0, x6, 36*FLEN/8, x10, x3, x12) +RVTEST_VALBASEUPD(x8,test_dataset_2) + +inst_24: +// rs1==x24, rs2==x10, rs3==x26, rd==x23,fs1 == 0 and fe1 == 0x1e and fm1 == 0x38b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x180 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x130 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x24; op2:x10; op3:x26; dest:x23; op1val:0x7b8b; op2val:0xb980; +op3val:0x7930; valaddr_reg:x8; val_offset:0*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x23, x24, x10, x26, dyn, 128, 0, x8, 0*FLEN/8, x11, x3, x12) + +inst_25: +// rs1==x25, rs2==x6, rs3==x27, rd==x18,fs1 == 0 and fe1 == 0x1e and fm1 == 0x334 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x005 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x33e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x25; op2:x6; op3:x27; dest:x18; op1val:0x7b34; op2val:0xb005; +op3val:0x6f3e; valaddr_reg:x8; val_offset:3*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x18, x25, x6, x27, dyn, 0, 0, x8, 3*FLEN/8, x11, x3, x12) + +inst_26: +// rs1==x9, rs2==x24, rs3==x16, rd==x14,fs1 == 0 and fe1 == 0x1e and fm1 == 0x334 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x005 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x33e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x9; op2:x24; op3:x16; dest:x14; op1val:0x7b34; op2val:0xb005; +op3val:0x6f3e; valaddr_reg:x8; val_offset:6*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x14, x9, x24, x16, dyn, 32, 0, x8, 6*FLEN/8, x11, x3, x6) + +inst_27: +// rs1==x26, rs2==x13, rs3==x10, rd==x15,fs1 == 0 and fe1 == 0x1e and fm1 == 0x334 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x005 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x33e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x26; op2:x13; op3:x10; dest:x15; op1val:0x7b34; op2val:0xb005; +op3val:0x6f3e; valaddr_reg:x8; val_offset:9*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x15, x26, x13, x10, dyn, 64, 0, x8, 9*FLEN/8, x11, x3, x6) +RVTEST_SIGBASE(x5,signature_x5_0) + +inst_28: +// rs1==x1, rs2==x15, rs3==x22, rd==x21,fs1 == 0 and fe1 == 0x1e and fm1 == 0x334 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x005 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x33e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x1; op2:x15; op3:x22; dest:x21; op1val:0x7b34; op2val:0xb005; +op3val:0x6f3e; valaddr_reg:x8; val_offset:12*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x21, x1, x15, x22, dyn, 96, 0, x8, 12*FLEN/8, x11, x5, x6) + +inst_29: +// rs1==x12, rs2==x7, rs3==x0, rd==x1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x334 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x005 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x33e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x12; op2:x7; op3:x0; dest:x1; op1val:0x7b34; op2val:0xb005; +op3val:0x0; valaddr_reg:x8; val_offset:15*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x1, x12, x7, x0, dyn, 128, 0, x8, 15*FLEN/8, x11, x5, x6) + +inst_30: +// rs1==x0, rs2==x3, rs3==x11, rd==x2,fs1 == 0 and fe1 == 0x1d and fm1 == 0x380 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x034 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3e3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x0; op2:x3; op3:x11; dest:x2; op1val:0x0; op2val:0xb834; +op3val:0x73e3; valaddr_reg:x8; val_offset:18*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x2, x0, x3, x11, dyn, 0, 0, x8, 18*FLEN/8, x11, x5, x6) + +inst_31: +// rs1==x10,fs1 == 0 and fe1 == 0x1d and fm1 == 0x380 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x034 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3e3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x10; op2:x26; op3:x30; dest:x13; op1val:0x7780; op2val:0xb834; +op3val:0x73e3; valaddr_reg:x8; val_offset:21*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x13, x10, x26, x30, dyn, 32, 0, x8, 21*FLEN/8, x11, x5, x6) + +inst_32: +// rs2==x4,fs1 == 0 and fe1 == 0x1d and fm1 == 0x380 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x034 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3e3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x31; op2:x4; op3:x14; dest:x17; op1val:0x7780; op2val:0xb834; +op3val:0x73e3; valaddr_reg:x8; val_offset:24*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x17, x31, x4, x14, dyn, 64, 0, x8, 24*FLEN/8, x11, x5, x6) + +inst_33: +// rs3==x5,fs1 == 0 and fe1 == 0x1d and fm1 == 0x380 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x034 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3e3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x7; op2:x28; op3:x5; dest:x12; op1val:0x7780; op2val:0xb834; +op3val:0x73e3; valaddr_reg:x8; val_offset:27*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x12, x7, x28, x5, dyn, 96, 0, x8, 27*FLEN/8, x11, x5, x6) + +inst_34: +// rd==x4,fs1 == 0 and fe1 == 0x1d and fm1 == 0x380 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x034 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3e3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x22; op2:x19; op3:x14; dest:x4; op1val:0x7780; op2val:0xb834; +op3val:0x73e3; valaddr_reg:x8; val_offset:30*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x4, x22, x19, x14, dyn, 128, 0, x8, 30*FLEN/8, x11, x5, x6) +RVTEST_VALBASEUPD(x1,test_dataset_3) + +inst_35: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x059 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x038 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x096 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7859; op2val:0xbc38; +op3val:0x7896; valaddr_reg:x1; val_offset:0*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 0*FLEN/8, x2, x5, x6) + +inst_36: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x059 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x038 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x096 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7859; op2val:0xbc38; +op3val:0x7896; valaddr_reg:x1; val_offset:3*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3*FLEN/8, x2, x5, x6) + +inst_37: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x059 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x038 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x096 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7859; op2val:0xbc38; +op3val:0x7896; valaddr_reg:x1; val_offset:6*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 6*FLEN/8, x2, x5, x6) + +inst_38: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x059 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x038 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x096 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7859; op2val:0xbc38; +op3val:0x7896; valaddr_reg:x1; val_offset:9*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 9*FLEN/8, x2, x5, x6) + +inst_39: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x059 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x038 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x096 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7859; op2val:0xbc38; +op3val:0x7896; valaddr_reg:x1; val_offset:12*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 12*FLEN/8, x2, x5, x6) + +inst_40: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x2b8 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x020 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2ee and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x62b8; op2val:0xcc20; +op3val:0x72ee; valaddr_reg:x1; val_offset:15*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 15*FLEN/8, x2, x5, x6) + +inst_41: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x2b8 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x020 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2ee and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x62b8; op2val:0xcc20; +op3val:0x72ee; valaddr_reg:x1; val_offset:18*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 18*FLEN/8, x2, x5, x6) + +inst_42: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x2b8 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x020 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2ee and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x62b8; op2val:0xcc20; +op3val:0x72ee; valaddr_reg:x1; val_offset:21*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 21*FLEN/8, x2, x5, x6) + +inst_43: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x2b8 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x020 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2ee and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x62b8; op2val:0xcc20; +op3val:0x72ee; valaddr_reg:x1; val_offset:24*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 24*FLEN/8, x2, x5, x6) + +inst_44: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x2b8 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x020 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2ee and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x62b8; op2val:0xcc20; +op3val:0x72ee; valaddr_reg:x1; val_offset:27*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 27*FLEN/8, x2, x5, x6) + +inst_45: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x078 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x28e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x353 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7478; op2val:0xc28e; +op3val:0x7b53; valaddr_reg:x1; val_offset:30*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 30*FLEN/8, x2, x5, x6) + +inst_46: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x078 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x28e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x353 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7478; op2val:0xc28e; +op3val:0x7b53; valaddr_reg:x1; val_offset:33*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 33*FLEN/8, x2, x5, x6) + +inst_47: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x078 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x28e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x353 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7478; op2val:0xc28e; +op3val:0x7b53; valaddr_reg:x1; val_offset:36*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 36*FLEN/8, x2, x5, x6) + +inst_48: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x078 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x28e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x353 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7478; op2val:0xc28e; +op3val:0x7b53; valaddr_reg:x1; val_offset:39*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 39*FLEN/8, x2, x5, x6) + +inst_49: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x078 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x28e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x353 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7478; op2val:0xc28e; +op3val:0x7b53; valaddr_reg:x1; val_offset:42*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 42*FLEN/8, x2, x5, x6) + +inst_50: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2ab and fs3 == 0 and fe3 == 0x1c and fm3 == 0x11a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a1f; op2val:0xb2ab; +op3val:0x711a; valaddr_reg:x1; val_offset:45*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 45*FLEN/8, x2, x5, x6) + +inst_51: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2ab and fs3 == 0 and fe3 == 0x1c and fm3 == 0x11a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a1f; op2val:0xb2ab; +op3val:0x711a; valaddr_reg:x1; val_offset:48*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 48*FLEN/8, x2, x5, x6) + +inst_52: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2ab and fs3 == 0 and fe3 == 0x1c and fm3 == 0x11a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a1f; op2val:0xb2ab; +op3val:0x711a; valaddr_reg:x1; val_offset:51*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 51*FLEN/8, x2, x5, x6) + +inst_53: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2ab and fs3 == 0 and fe3 == 0x1c and fm3 == 0x11a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a1f; op2val:0xb2ab; +op3val:0x711a; valaddr_reg:x1; val_offset:54*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 54*FLEN/8, x2, x5, x6) + +inst_54: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2ab and fs3 == 0 and fe3 == 0x1c and fm3 == 0x11a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a1f; op2val:0xb2ab; +op3val:0x711a; valaddr_reg:x1; val_offset:57*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 57*FLEN/8, x2, x5, x6) + +inst_55: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x192 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x070 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5f; op2val:0xb192; +op3val:0x7070; valaddr_reg:x1; val_offset:60*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 60*FLEN/8, x2, x5, x6) + +inst_56: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x192 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x070 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5f; op2val:0xb192; +op3val:0x7070; valaddr_reg:x1; val_offset:63*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 63*FLEN/8, x2, x5, x6) + +inst_57: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x192 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x070 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5f; op2val:0xb192; +op3val:0x7070; valaddr_reg:x1; val_offset:66*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 66*FLEN/8, x2, x5, x6) + +inst_58: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x192 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x070 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5f; op2val:0xb192; +op3val:0x7070; valaddr_reg:x1; val_offset:69*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 69*FLEN/8, x2, x5, x6) + +inst_59: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x192 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x070 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5f; op2val:0xb192; +op3val:0x7070; valaddr_reg:x1; val_offset:72*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 72*FLEN/8, x2, x5, x6) + +inst_60: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ef and fs2 == 1 and fe2 == 0x0c and fm2 == 0x291 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x00d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78ef; op2val:0xb291; +op3val:0x700d; valaddr_reg:x1; val_offset:75*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 75*FLEN/8, x2, x5, x6) + +inst_61: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ef and fs2 == 1 and fe2 == 0x0c and fm2 == 0x291 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x00d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78ef; op2val:0xb291; +op3val:0x700d; valaddr_reg:x1; val_offset:78*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 78*FLEN/8, x2, x5, x6) + +inst_62: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ef and fs2 == 1 and fe2 == 0x0c and fm2 == 0x291 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x00d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78ef; op2val:0xb291; +op3val:0x700d; valaddr_reg:x1; val_offset:81*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 81*FLEN/8, x2, x5, x6) + +inst_63: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ef and fs2 == 1 and fe2 == 0x0c and fm2 == 0x291 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x00d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78ef; op2val:0xb291; +op3val:0x700d; valaddr_reg:x1; val_offset:84*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 84*FLEN/8, x2, x5, x6) + +inst_64: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ef and fs2 == 1 and fe2 == 0x0c and fm2 == 0x291 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x00d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78ef; op2val:0xb291; +op3val:0x700d; valaddr_reg:x1; val_offset:87*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 87*FLEN/8, x2, x5, x6) + +inst_65: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x354 and fs2 == 1 and fe2 == 0x17 and fm2 == 0x39b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5754; op2val:0xdf9b; +op3val:0x7af7; valaddr_reg:x1; val_offset:90*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 90*FLEN/8, x2, x5, x6) + +inst_66: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x354 and fs2 == 1 and fe2 == 0x17 and fm2 == 0x39b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5754; op2val:0xdf9b; +op3val:0x7af7; valaddr_reg:x1; val_offset:93*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 93*FLEN/8, x2, x5, x6) + +inst_67: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x354 and fs2 == 1 and fe2 == 0x17 and fm2 == 0x39b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5754; op2val:0xdf9b; +op3val:0x7af7; valaddr_reg:x1; val_offset:96*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 96*FLEN/8, x2, x5, x6) + +inst_68: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x354 and fs2 == 1 and fe2 == 0x17 and fm2 == 0x39b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5754; op2val:0xdf9b; +op3val:0x7af7; valaddr_reg:x1; val_offset:99*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 99*FLEN/8, x2, x5, x6) + +inst_69: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x354 and fs2 == 1 and fe2 == 0x17 and fm2 == 0x39b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5754; op2val:0xdf9b; +op3val:0x7af7; valaddr_reg:x1; val_offset:102*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 102*FLEN/8, x2, x5, x6) + +inst_70: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2b3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x01d and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2e4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72b3; op2val:0xbc1d; +op3val:0x72e4; valaddr_reg:x1; val_offset:105*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 105*FLEN/8, x2, x5, x6) + +inst_71: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2b3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x01d and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2e4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72b3; op2val:0xbc1d; +op3val:0x72e4; valaddr_reg:x1; val_offset:108*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 108*FLEN/8, x2, x5, x6) + +inst_72: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2b3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x01d and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2e4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72b3; op2val:0xbc1d; +op3val:0x72e4; valaddr_reg:x1; val_offset:111*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 111*FLEN/8, x2, x5, x6) + +inst_73: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2b3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x01d and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2e4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72b3; op2val:0xbc1d; +op3val:0x72e4; valaddr_reg:x1; val_offset:114*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 114*FLEN/8, x2, x5, x6) + +inst_74: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2b3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x01d and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2e4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72b3; op2val:0xbc1d; +op3val:0x72e4; valaddr_reg:x1; val_offset:117*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 117*FLEN/8, x2, x5, x6) + +inst_75: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3db and fs2 == 1 and fe2 == 0x0e and fm2 == 0x31a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bdb; op2val:0xbb1a; +op3val:0x7af9; valaddr_reg:x1; val_offset:120*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 120*FLEN/8, x2, x5, x6) + +inst_76: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3db and fs2 == 1 and fe2 == 0x0e and fm2 == 0x31a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bdb; op2val:0xbb1a; +op3val:0x7af9; valaddr_reg:x1; val_offset:123*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 123*FLEN/8, x2, x5, x6) + +inst_77: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3db and fs2 == 1 and fe2 == 0x0e and fm2 == 0x31a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bdb; op2val:0xbb1a; +op3val:0x7af9; valaddr_reg:x1; val_offset:126*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 126*FLEN/8, x2, x5, x6) + +inst_78: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3db and fs2 == 1 and fe2 == 0x0e and fm2 == 0x31a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bdb; op2val:0xbb1a; +op3val:0x7af9; valaddr_reg:x1; val_offset:129*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 129*FLEN/8, x2, x5, x6) + +inst_79: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3db and fs2 == 1 and fe2 == 0x0e and fm2 == 0x31a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bdb; op2val:0xbb1a; +op3val:0x7af9; valaddr_reg:x1; val_offset:132*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 132*FLEN/8, x2, x5, x6) + +inst_80: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a0 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2a5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74a0; op2val:0xc2a5; +op3val:0x7bb0; valaddr_reg:x1; val_offset:135*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 135*FLEN/8, x2, x5, x6) + +inst_81: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a0 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2a5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74a0; op2val:0xc2a5; +op3val:0x7bb0; valaddr_reg:x1; val_offset:138*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 138*FLEN/8, x2, x5, x6) + +inst_82: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a0 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2a5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74a0; op2val:0xc2a5; +op3val:0x7bb0; valaddr_reg:x1; val_offset:141*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 141*FLEN/8, x2, x5, x6) + +inst_83: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a0 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2a5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74a0; op2val:0xc2a5; +op3val:0x7bb0; valaddr_reg:x1; val_offset:144*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 144*FLEN/8, x2, x5, x6) + +inst_84: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a0 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2a5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74a0; op2val:0xc2a5; +op3val:0x7bb0; valaddr_reg:x1; val_offset:147*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 147*FLEN/8, x2, x5, x6) + +inst_85: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x107 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x16b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x784f; op2val:0xbd07; +op3val:0x796b; valaddr_reg:x1; val_offset:150*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 150*FLEN/8, x2, x5, x6) + +inst_86: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x107 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x16b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x784f; op2val:0xbd07; +op3val:0x796b; valaddr_reg:x1; val_offset:153*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 153*FLEN/8, x2, x5, x6) + +inst_87: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x107 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x16b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x784f; op2val:0xbd07; +op3val:0x796b; valaddr_reg:x1; val_offset:156*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 156*FLEN/8, x2, x5, x6) + +inst_88: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x107 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x16b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x784f; op2val:0xbd07; +op3val:0x796b; valaddr_reg:x1; val_offset:159*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 159*FLEN/8, x2, x5, x6) + +inst_89: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x107 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x16b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x784f; op2val:0xbd07; +op3val:0x796b; valaddr_reg:x1; val_offset:162*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 162*FLEN/8, x2, x5, x6) + +inst_90: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x28c and fs2 == 1 and fe2 == 0x11 and fm2 == 0x098 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x386 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x728c; op2val:0xc498; +op3val:0x7b86; valaddr_reg:x1; val_offset:165*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 165*FLEN/8, x2, x5, x6) + +inst_91: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x28c and fs2 == 1 and fe2 == 0x11 and fm2 == 0x098 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x386 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x728c; op2val:0xc498; +op3val:0x7b86; valaddr_reg:x1; val_offset:168*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 168*FLEN/8, x2, x5, x6) + +inst_92: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x28c and fs2 == 1 and fe2 == 0x11 and fm2 == 0x098 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x386 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x728c; op2val:0xc498; +op3val:0x7b86; valaddr_reg:x1; val_offset:171*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 171*FLEN/8, x2, x5, x6) + +inst_93: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x28c and fs2 == 1 and fe2 == 0x11 and fm2 == 0x098 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x386 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x728c; op2val:0xc498; +op3val:0x7b86; valaddr_reg:x1; val_offset:174*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 174*FLEN/8, x2, x5, x6) + +inst_94: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x28c and fs2 == 1 and fe2 == 0x11 and fm2 == 0x098 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x386 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x728c; op2val:0xc498; +op3val:0x7b86; valaddr_reg:x1; val_offset:177*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 177*FLEN/8, x2, x5, x6) + +inst_95: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x185 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x199 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ba and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7985; op2val:0xbd99; +op3val:0x7bba; valaddr_reg:x1; val_offset:180*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 180*FLEN/8, x2, x5, x6) + +inst_96: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x185 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x199 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ba and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7985; op2val:0xbd99; +op3val:0x7bba; valaddr_reg:x1; val_offset:183*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 183*FLEN/8, x2, x5, x6) + +inst_97: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x185 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x199 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ba and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7985; op2val:0xbd99; +op3val:0x7bba; valaddr_reg:x1; val_offset:186*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 186*FLEN/8, x2, x5, x6) + +inst_98: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x185 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x199 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ba and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7985; op2val:0xbd99; +op3val:0x7bba; valaddr_reg:x1; val_offset:189*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 189*FLEN/8, x2, x5, x6) + +inst_99: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x185 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x199 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ba and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7985; op2val:0xbd99; +op3val:0x7bba; valaddr_reg:x1; val_offset:192*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 192*FLEN/8, x2, x5, x6) + +inst_100: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x325 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x159 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0c7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b25; op2val:0xb559; +op3val:0x74c7; valaddr_reg:x1; val_offset:195*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 195*FLEN/8, x2, x5, x6) + +inst_101: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x325 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x159 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0c7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b25; op2val:0xb559; +op3val:0x74c7; valaddr_reg:x1; val_offset:198*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 198*FLEN/8, x2, x5, x6) + +inst_102: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x325 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x159 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0c7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b25; op2val:0xb559; +op3val:0x74c7; valaddr_reg:x1; val_offset:201*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 201*FLEN/8, x2, x5, x6) + +inst_103: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x325 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x159 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0c7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b25; op2val:0xb559; +op3val:0x74c7; valaddr_reg:x1; val_offset:204*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 204*FLEN/8, x2, x5, x6) + +inst_104: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x325 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x159 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0c7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b25; op2val:0xb559; +op3val:0x74c7; valaddr_reg:x1; val_offset:207*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 207*FLEN/8, x2, x5, x6) + +inst_105: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c6 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x35a and fs3 == 0 and fe3 == 0x1c and fm3 == 0x14e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c6; op2val:0xb75a; +op3val:0x714e; valaddr_reg:x1; val_offset:210*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 210*FLEN/8, x2, x5, x6) + +inst_106: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c6 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x35a and fs3 == 0 and fe3 == 0x1c and fm3 == 0x14e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c6; op2val:0xb75a; +op3val:0x714e; valaddr_reg:x1; val_offset:213*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 213*FLEN/8, x2, x5, x6) + +inst_107: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c6 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x35a and fs3 == 0 and fe3 == 0x1c and fm3 == 0x14e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c6; op2val:0xb75a; +op3val:0x714e; valaddr_reg:x1; val_offset:216*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 216*FLEN/8, x2, x5, x6) + +inst_108: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c6 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x35a and fs3 == 0 and fe3 == 0x1c and fm3 == 0x14e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c6; op2val:0xb75a; +op3val:0x714e; valaddr_reg:x1; val_offset:219*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 219*FLEN/8, x2, x5, x6) + +inst_109: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c6 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x35a and fs3 == 0 and fe3 == 0x1c and fm3 == 0x14e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c6; op2val:0xb75a; +op3val:0x714e; valaddr_reg:x1; val_offset:222*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 222*FLEN/8, x2, x5, x6) + +inst_110: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0a9 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x327 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x02a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70a9; op2val:0xb727; +op3val:0x6c2a; valaddr_reg:x1; val_offset:225*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 225*FLEN/8, x2, x5, x6) + +inst_111: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0a9 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x327 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x02a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70a9; op2val:0xb727; +op3val:0x6c2a; valaddr_reg:x1; val_offset:228*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 228*FLEN/8, x2, x5, x6) + +inst_112: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0a9 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x327 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x02a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70a9; op2val:0xb727; +op3val:0x6c2a; valaddr_reg:x1; val_offset:231*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 231*FLEN/8, x2, x5, x6) + +inst_113: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0a9 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x327 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x02a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70a9; op2val:0xb727; +op3val:0x6c2a; valaddr_reg:x1; val_offset:234*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 234*FLEN/8, x2, x5, x6) + +inst_114: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0a9 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x327 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x02a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70a9; op2val:0xb727; +op3val:0x6c2a; valaddr_reg:x1; val_offset:237*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 237*FLEN/8, x2, x5, x6) + +inst_115: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d1 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0d2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74d1; op2val:0xc000; +op3val:0x78d2; valaddr_reg:x1; val_offset:240*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 240*FLEN/8, x2, x5, x6) + +inst_116: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d1 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0d2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74d1; op2val:0xc000; +op3val:0x78d2; valaddr_reg:x1; val_offset:243*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 243*FLEN/8, x2, x5, x6) + +inst_117: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d1 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0d2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74d1; op2val:0xc000; +op3val:0x78d2; valaddr_reg:x1; val_offset:246*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 246*FLEN/8, x2, x5, x6) + +inst_118: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d1 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0d2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74d1; op2val:0xc000; +op3val:0x78d2; valaddr_reg:x1; val_offset:249*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 249*FLEN/8, x2, x5, x6) + +inst_119: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d1 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0d2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74d1; op2val:0xc000; +op3val:0x78d2; valaddr_reg:x1; val_offset:252*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 252*FLEN/8, x2, x5, x6) + +inst_120: +// fs1 == 0 and fe1 == 0x16 and fm1 == 0x2f4 and fs2 == 1 and fe2 == 0x16 and fm2 == 0x23b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x16b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5af4; op2val:0xda3b; +op3val:0x796b; valaddr_reg:x1; val_offset:255*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 255*FLEN/8, x2, x5, x6) + +inst_121: +// fs1 == 0 and fe1 == 0x16 and fm1 == 0x2f4 and fs2 == 1 and fe2 == 0x16 and fm2 == 0x23b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x16b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5af4; op2val:0xda3b; +op3val:0x796b; valaddr_reg:x1; val_offset:258*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 258*FLEN/8, x2, x5, x6) + +inst_122: +// fs1 == 0 and fe1 == 0x16 and fm1 == 0x2f4 and fs2 == 1 and fe2 == 0x16 and fm2 == 0x23b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x16b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5af4; op2val:0xda3b; +op3val:0x796b; valaddr_reg:x1; val_offset:261*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 261*FLEN/8, x2, x5, x6) + +inst_123: +// fs1 == 0 and fe1 == 0x16 and fm1 == 0x2f4 and fs2 == 1 and fe2 == 0x16 and fm2 == 0x23b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x16b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5af4; op2val:0xda3b; +op3val:0x796b; valaddr_reg:x1; val_offset:264*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 264*FLEN/8, x2, x5, x6) + +inst_124: +// fs1 == 0 and fe1 == 0x16 and fm1 == 0x2f4 and fs2 == 1 and fe2 == 0x16 and fm2 == 0x23b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x16b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5af4; op2val:0xda3b; +op3val:0x796b; valaddr_reg:x1; val_offset:267*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 267*FLEN/8, x2, x5, x6) + +inst_125: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x167 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x356 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0f5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7567; op2val:0xbb56; +op3val:0x74f5; valaddr_reg:x1; val_offset:270*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 270*FLEN/8, x2, x5, x6) + +inst_126: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x167 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x356 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0f5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7567; op2val:0xbb56; +op3val:0x74f5; valaddr_reg:x1; val_offset:273*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 273*FLEN/8, x2, x5, x6) + +inst_127: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x167 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x356 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0f5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7567; op2val:0xbb56; +op3val:0x74f5; valaddr_reg:x1; val_offset:276*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 276*FLEN/8, x2, x5, x6) + +inst_128: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x167 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x356 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0f5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7567; op2val:0xbb56; +op3val:0x74f5; valaddr_reg:x1; val_offset:279*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 279*FLEN/8, x2, x5, x6) + +inst_129: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x167 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x356 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0f5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7567; op2val:0xbb56; +op3val:0x74f5; valaddr_reg:x1; val_offset:282*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 282*FLEN/8, x2, x5, x6) + +inst_130: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0b2 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3b0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8b; op2val:0xb8b2; +op3val:0x77b0; valaddr_reg:x1; val_offset:285*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 285*FLEN/8, x2, x5, x6) + +inst_131: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0b2 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3b0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8b; op2val:0xb8b2; +op3val:0x77b0; valaddr_reg:x1; val_offset:288*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 288*FLEN/8, x2, x5, x6) + +inst_132: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0b2 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3b0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8b; op2val:0xb8b2; +op3val:0x77b0; valaddr_reg:x1; val_offset:291*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 291*FLEN/8, x2, x5, x6) + +inst_133: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0b2 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3b0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8b; op2val:0xb8b2; +op3val:0x77b0; valaddr_reg:x1; val_offset:294*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 294*FLEN/8, x2, x5, x6) + +inst_134: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0b2 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3b0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8b; op2val:0xb8b2; +op3val:0x77b0; valaddr_reg:x1; val_offset:297*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 297*FLEN/8, x2, x5, x6) + +inst_135: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x10c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x218 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3b2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x750c; op2val:0xbe18; +op3val:0x77b2; valaddr_reg:x1; val_offset:300*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 300*FLEN/8, x2, x5, x6) + +inst_136: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x10c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x218 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3b2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x750c; op2val:0xbe18; +op3val:0x77b2; valaddr_reg:x1; val_offset:303*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 303*FLEN/8, x2, x5, x6) + +inst_137: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x10c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x218 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3b2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x750c; op2val:0xbe18; +op3val:0x77b2; valaddr_reg:x1; val_offset:306*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 306*FLEN/8, x2, x5, x6) + +inst_138: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x10c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x218 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3b2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x750c; op2val:0xbe18; +op3val:0x77b2; valaddr_reg:x1; val_offset:309*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 309*FLEN/8, x2, x5, x6) + +inst_139: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x10c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x218 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3b2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x750c; op2val:0xbe18; +op3val:0x77b2; valaddr_reg:x1; val_offset:312*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 312*FLEN/8, x2, x5, x6) + +inst_140: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a2 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x12d and fs3 == 0 and fe3 == 0x1a and fm3 == 0x34b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79a2; op2val:0xad2d; +op3val:0x6b4b; valaddr_reg:x1; val_offset:315*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 315*FLEN/8, x2, x5, x6) + +inst_141: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a2 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x12d and fs3 == 0 and fe3 == 0x1a and fm3 == 0x34b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79a2; op2val:0xad2d; +op3val:0x6b4b; valaddr_reg:x1; val_offset:318*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 318*FLEN/8, x2, x5, x6) + +inst_142: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a2 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x12d and fs3 == 0 and fe3 == 0x1a and fm3 == 0x34b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79a2; op2val:0xad2d; +op3val:0x6b4b; valaddr_reg:x1; val_offset:321*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 321*FLEN/8, x2, x5, x6) + +inst_143: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a2 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x12d and fs3 == 0 and fe3 == 0x1a and fm3 == 0x34b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79a2; op2val:0xad2d; +op3val:0x6b4b; valaddr_reg:x1; val_offset:324*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 324*FLEN/8, x2, x5, x6) + +inst_144: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a2 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x12d and fs3 == 0 and fe3 == 0x1a and fm3 == 0x34b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79a2; op2val:0xad2d; +op3val:0x6b4b; valaddr_reg:x1; val_offset:327*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 327*FLEN/8, x2, x5, x6) + +inst_145: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3cc and fs2 == 1 and fe2 == 0x09 and fm2 == 0x201 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x1da and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bcc; op2val:0xa601; +op3val:0x65da; valaddr_reg:x1; val_offset:330*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 330*FLEN/8, x2, x5, x6) + +inst_146: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3cc and fs2 == 1 and fe2 == 0x09 and fm2 == 0x201 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x1da and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bcc; op2val:0xa601; +op3val:0x65da; valaddr_reg:x1; val_offset:333*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 333*FLEN/8, x2, x5, x6) + +inst_147: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3cc and fs2 == 1 and fe2 == 0x09 and fm2 == 0x201 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x1da and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bcc; op2val:0xa601; +op3val:0x65da; valaddr_reg:x1; val_offset:336*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 336*FLEN/8, x2, x5, x6) + +inst_148: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3cc and fs2 == 1 and fe2 == 0x09 and fm2 == 0x201 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x1da and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bcc; op2val:0xa601; +op3val:0x65da; valaddr_reg:x1; val_offset:339*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 339*FLEN/8, x2, x5, x6) + +inst_149: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3cc and fs2 == 1 and fe2 == 0x09 and fm2 == 0x201 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x1da and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bcc; op2val:0xa601; +op3val:0x65da; valaddr_reg:x1; val_offset:342*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 342*FLEN/8, x2, x5, x6) + +inst_150: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x081 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2c1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79fe; op2val:0xbc81; +op3val:0x7ac1; valaddr_reg:x1; val_offset:345*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 345*FLEN/8, x2, x5, x6) + +inst_151: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x081 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2c1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79fe; op2val:0xbc81; +op3val:0x7ac1; valaddr_reg:x1; val_offset:348*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 348*FLEN/8, x2, x5, x6) + +inst_152: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x081 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2c1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79fe; op2val:0xbc81; +op3val:0x7ac1; valaddr_reg:x1; val_offset:351*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 351*FLEN/8, x2, x5, x6) + +inst_153: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x081 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2c1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79fe; op2val:0xbc81; +op3val:0x7ac1; valaddr_reg:x1; val_offset:354*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 354*FLEN/8, x2, x5, x6) + +inst_154: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x081 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2c1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79fe; op2val:0xbc81; +op3val:0x7ac1; valaddr_reg:x1; val_offset:357*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 357*FLEN/8, x2, x5, x6) + +inst_155: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x0a0 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x172 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x24c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x64a0; op2val:0xd172; +op3val:0x7a4c; valaddr_reg:x1; val_offset:360*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 360*FLEN/8, x2, x5, x6) +RVTEST_SIGBASE(x5,signature_x5_1) + +inst_156: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x0a0 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x172 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x24c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x64a0; op2val:0xd172; +op3val:0x7a4c; valaddr_reg:x1; val_offset:363*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 363*FLEN/8, x2, x5, x6) + +inst_157: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x0a0 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x172 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x24c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x64a0; op2val:0xd172; +op3val:0x7a4c; valaddr_reg:x1; val_offset:366*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 366*FLEN/8, x2, x5, x6) + +inst_158: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x0a0 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x172 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x24c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x64a0; op2val:0xd172; +op3val:0x7a4c; valaddr_reg:x1; val_offset:369*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 369*FLEN/8, x2, x5, x6) + +inst_159: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x0a0 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x172 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x24c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x64a0; op2val:0xd172; +op3val:0x7a4c; valaddr_reg:x1; val_offset:372*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 372*FLEN/8, x2, x5, x6) + +inst_160: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1db and fs2 == 1 and fe2 == 0x0f and fm2 == 0x251 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75db; op2val:0xbe51; +op3val:0x78a0; valaddr_reg:x1; val_offset:375*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 375*FLEN/8, x2, x5, x6) + +inst_161: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1db and fs2 == 1 and fe2 == 0x0f and fm2 == 0x251 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75db; op2val:0xbe51; +op3val:0x78a0; valaddr_reg:x1; val_offset:378*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 378*FLEN/8, x2, x5, x6) + +inst_162: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1db and fs2 == 1 and fe2 == 0x0f and fm2 == 0x251 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75db; op2val:0xbe51; +op3val:0x78a0; valaddr_reg:x1; val_offset:381*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 381*FLEN/8, x2, x5, x6) + +inst_163: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1db and fs2 == 1 and fe2 == 0x0f and fm2 == 0x251 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75db; op2val:0xbe51; +op3val:0x78a0; valaddr_reg:x1; val_offset:384*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 384*FLEN/8, x2, x5, x6) + +inst_164: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1db and fs2 == 1 and fe2 == 0x0f and fm2 == 0x251 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75db; op2val:0xbe51; +op3val:0x78a0; valaddr_reg:x1; val_offset:387*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 387*FLEN/8, x2, x5, x6) + +inst_165: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x0a7 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x123 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x1fa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x60a7; op2val:0xc523; +op3val:0x69fa; valaddr_reg:x1; val_offset:390*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 390*FLEN/8, x2, x5, x6) + +inst_166: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x0a7 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x123 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x1fa and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x60a7; op2val:0xc523; +op3val:0x69fa; valaddr_reg:x1; val_offset:393*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 393*FLEN/8, x2, x5, x6) + +inst_167: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x0a7 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x123 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x1fa and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x60a7; op2val:0xc523; +op3val:0x69fa; valaddr_reg:x1; val_offset:396*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 396*FLEN/8, x2, x5, x6) + +inst_168: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x0a7 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x123 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x1fa and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x60a7; op2val:0xc523; +op3val:0x69fa; valaddr_reg:x1; val_offset:399*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 399*FLEN/8, x2, x5, x6) + +inst_169: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x0a7 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x123 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x1fa and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x60a7; op2val:0xc523; +op3val:0x69fa; valaddr_reg:x1; val_offset:402*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 402*FLEN/8, x2, x5, x6) + +inst_170: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1c9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x147 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3a3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71c9; op2val:0xc547; +op3val:0x7ba3; valaddr_reg:x1; val_offset:405*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 405*FLEN/8, x2, x5, x6) + +inst_171: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1c9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x147 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3a3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71c9; op2val:0xc547; +op3val:0x7ba3; valaddr_reg:x1; val_offset:408*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 408*FLEN/8, x2, x5, x6) + +inst_172: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1c9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x147 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3a3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71c9; op2val:0xc547; +op3val:0x7ba3; valaddr_reg:x1; val_offset:411*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 411*FLEN/8, x2, x5, x6) + +inst_173: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1c9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x147 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3a3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71c9; op2val:0xc547; +op3val:0x7ba3; valaddr_reg:x1; val_offset:414*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 414*FLEN/8, x2, x5, x6) + +inst_174: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1c9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x147 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3a3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71c9; op2val:0xc547; +op3val:0x7ba3; valaddr_reg:x1; val_offset:417*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 417*FLEN/8, x2, x5, x6) + +inst_175: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x249 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3b0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x20b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7249; op2val:0xc3b0; +op3val:0x7a0b; valaddr_reg:x1; val_offset:420*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 420*FLEN/8, x2, x5, x6) + +inst_176: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x249 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3b0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x20b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7249; op2val:0xc3b0; +op3val:0x7a0b; valaddr_reg:x1; val_offset:423*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 423*FLEN/8, x2, x5, x6) + +inst_177: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x249 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3b0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x20b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7249; op2val:0xc3b0; +op3val:0x7a0b; valaddr_reg:x1; val_offset:426*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 426*FLEN/8, x2, x5, x6) + +inst_178: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x249 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3b0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x20b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7249; op2val:0xc3b0; +op3val:0x7a0b; valaddr_reg:x1; val_offset:429*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 429*FLEN/8, x2, x5, x6) + +inst_179: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x249 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3b0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x20b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7249; op2val:0xc3b0; +op3val:0x7a0b; valaddr_reg:x1; val_offset:432*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 432*FLEN/8, x2, x5, x6) + +inst_180: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x36f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x00d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x388 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b6f; op2val:0xbc0d; +op3val:0x7b88; valaddr_reg:x1; val_offset:435*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 435*FLEN/8, x2, x5, x6) + +inst_181: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x36f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x00d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x388 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b6f; op2val:0xbc0d; +op3val:0x7b88; valaddr_reg:x1; val_offset:438*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 438*FLEN/8, x2, x5, x6) + +inst_182: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x36f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x00d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x388 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b6f; op2val:0xbc0d; +op3val:0x7b88; valaddr_reg:x1; val_offset:441*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 441*FLEN/8, x2, x5, x6) + +inst_183: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x36f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x00d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x388 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b6f; op2val:0xbc0d; +op3val:0x7b88; valaddr_reg:x1; val_offset:444*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 444*FLEN/8, x2, x5, x6) + +inst_184: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x36f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x00d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x388 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b6f; op2val:0xbc0d; +op3val:0x7b88; valaddr_reg:x1; val_offset:447*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 447*FLEN/8, x2, x5, x6) + +inst_185: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x181 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x01e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1ac and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7581; op2val:0xbc1e; +op3val:0x75ac; valaddr_reg:x1; val_offset:450*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 450*FLEN/8, x2, x5, x6) + +inst_186: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x181 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x01e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1ac and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7581; op2val:0xbc1e; +op3val:0x75ac; valaddr_reg:x1; val_offset:453*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 453*FLEN/8, x2, x5, x6) + +inst_187: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x181 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x01e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1ac and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7581; op2val:0xbc1e; +op3val:0x75ac; valaddr_reg:x1; val_offset:456*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 456*FLEN/8, x2, x5, x6) + +inst_188: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x181 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x01e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1ac and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7581; op2val:0xbc1e; +op3val:0x75ac; valaddr_reg:x1; val_offset:459*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 459*FLEN/8, x2, x5, x6) + +inst_189: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x181 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x01e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1ac and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7581; op2val:0xbc1e; +op3val:0x75ac; valaddr_reg:x1; val_offset:462*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 462*FLEN/8, x2, x5, x6) + +inst_190: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x032 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1e9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x233 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7832; op2val:0xbde9; +op3val:0x7a33; valaddr_reg:x1; val_offset:465*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 465*FLEN/8, x2, x5, x6) + +inst_191: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x032 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1e9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x233 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7832; op2val:0xbde9; +op3val:0x7a33; valaddr_reg:x1; val_offset:468*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 468*FLEN/8, x2, x5, x6) + +inst_192: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x032 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1e9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x233 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7832; op2val:0xbde9; +op3val:0x7a33; valaddr_reg:x1; val_offset:471*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 471*FLEN/8, x2, x5, x6) + +inst_193: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x032 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1e9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x233 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7832; op2val:0xbde9; +op3val:0x7a33; valaddr_reg:x1; val_offset:474*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 474*FLEN/8, x2, x5, x6) + +inst_194: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x032 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1e9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x233 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7832; op2val:0xbde9; +op3val:0x7a33; valaddr_reg:x1; val_offset:477*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 477*FLEN/8, x2, x5, x6) + +inst_195: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2e9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2ec and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1fb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ee9; op2val:0xc6ec; +op3val:0x79fb; valaddr_reg:x1; val_offset:480*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 480*FLEN/8, x2, x5, x6) + +inst_196: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2e9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2ec and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1fb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ee9; op2val:0xc6ec; +op3val:0x79fb; valaddr_reg:x1; val_offset:483*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 483*FLEN/8, x2, x5, x6) + +inst_197: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2e9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2ec and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1fb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ee9; op2val:0xc6ec; +op3val:0x79fb; valaddr_reg:x1; val_offset:486*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 486*FLEN/8, x2, x5, x6) + +inst_198: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2e9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2ec and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1fb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ee9; op2val:0xc6ec; +op3val:0x79fb; valaddr_reg:x1; val_offset:489*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 489*FLEN/8, x2, x5, x6) + +inst_199: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2e9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2ec and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1fb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ee9; op2val:0xc6ec; +op3val:0x79fb; valaddr_reg:x1; val_offset:492*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 492*FLEN/8, x2, x5, x6) + +inst_200: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x050 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2df and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5f; op2val:0xbc50; +op3val:0x7adf; valaddr_reg:x1; val_offset:495*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 495*FLEN/8, x2, x5, x6) + +inst_201: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x050 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2df and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5f; op2val:0xbc50; +op3val:0x7adf; valaddr_reg:x1; val_offset:498*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 498*FLEN/8, x2, x5, x6) + +inst_202: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x050 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2df and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5f; op2val:0xbc50; +op3val:0x7adf; valaddr_reg:x1; val_offset:501*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 501*FLEN/8, x2, x5, x6) + +inst_203: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x050 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2df and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5f; op2val:0xbc50; +op3val:0x7adf; valaddr_reg:x1; val_offset:504*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 504*FLEN/8, x2, x5, x6) + +inst_204: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x050 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2df and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5f; op2val:0xbc50; +op3val:0x7adf; valaddr_reg:x1; val_offset:507*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 507*FLEN/8, x2, x5, x6) + +inst_205: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x0b0 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x273 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x390 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x68b0; op2val:0xce73; +op3val:0x7b90; valaddr_reg:x1; val_offset:510*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 510*FLEN/8, x2, x5, x6) + +inst_206: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x0b0 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x273 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x390 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x68b0; op2val:0xce73; +op3val:0x7b90; valaddr_reg:x1; val_offset:513*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 513*FLEN/8, x2, x5, x6) + +inst_207: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x0b0 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x273 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x390 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x68b0; op2val:0xce73; +op3val:0x7b90; valaddr_reg:x1; val_offset:516*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 516*FLEN/8, x2, x5, x6) + +inst_208: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x0b0 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x273 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x390 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x68b0; op2val:0xce73; +op3val:0x7b90; valaddr_reg:x1; val_offset:519*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 519*FLEN/8, x2, x5, x6) + +inst_209: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x0b0 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x273 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x390 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x68b0; op2val:0xce73; +op3val:0x7b90; valaddr_reg:x1; val_offset:522*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 522*FLEN/8, x2, x5, x6) + +inst_210: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1d5 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x379 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x173 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dd5; op2val:0xc379; +op3val:0x7573; valaddr_reg:x1; val_offset:525*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 525*FLEN/8, x2, x5, x6) + +inst_211: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1d5 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x379 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x173 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dd5; op2val:0xc379; +op3val:0x7573; valaddr_reg:x1; val_offset:528*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 528*FLEN/8, x2, x5, x6) + +inst_212: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1d5 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x379 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x173 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dd5; op2val:0xc379; +op3val:0x7573; valaddr_reg:x1; val_offset:531*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 531*FLEN/8, x2, x5, x6) + +inst_213: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1d5 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x379 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x173 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dd5; op2val:0xc379; +op3val:0x7573; valaddr_reg:x1; val_offset:534*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 534*FLEN/8, x2, x5, x6) + +inst_214: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1d5 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x379 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x173 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dd5; op2val:0xc379; +op3val:0x7573; valaddr_reg:x1; val_offset:537*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 537*FLEN/8, x2, x5, x6) + +inst_215: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e2 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x203 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x357 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e2; op2val:0xbe03; +op3val:0x7b57; valaddr_reg:x1; val_offset:540*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 540*FLEN/8, x2, x5, x6) + +inst_216: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e2 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x203 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x357 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e2; op2val:0xbe03; +op3val:0x7b57; valaddr_reg:x1; val_offset:543*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 543*FLEN/8, x2, x5, x6) + +inst_217: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e2 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x203 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x357 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e2; op2val:0xbe03; +op3val:0x7b57; valaddr_reg:x1; val_offset:546*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 546*FLEN/8, x2, x5, x6) + +inst_218: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e2 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x203 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x357 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e2; op2val:0xbe03; +op3val:0x7b57; valaddr_reg:x1; val_offset:549*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 549*FLEN/8, x2, x5, x6) + +inst_219: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e2 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x203 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x357 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e2; op2val:0xbe03; +op3val:0x7b57; valaddr_reg:x1; val_offset:552*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 552*FLEN/8, x2, x5, x6) + +inst_220: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x16f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x16f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x363 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x756f; op2val:0xc16f; +op3val:0x7b63; valaddr_reg:x1; val_offset:555*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 555*FLEN/8, x2, x5, x6) + +inst_221: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x16f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x16f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x363 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x756f; op2val:0xc16f; +op3val:0x7b63; valaddr_reg:x1; val_offset:558*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 558*FLEN/8, x2, x5, x6) + +inst_222: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x16f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x16f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x363 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x756f; op2val:0xc16f; +op3val:0x7b63; valaddr_reg:x1; val_offset:561*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 561*FLEN/8, x2, x5, x6) + +inst_223: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x16f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x16f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x363 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x756f; op2val:0xc16f; +op3val:0x7b63; valaddr_reg:x1; val_offset:564*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 564*FLEN/8, x2, x5, x6) + +inst_224: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x16f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x16f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x363 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x756f; op2val:0xc16f; +op3val:0x7b63; valaddr_reg:x1; val_offset:567*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 567*FLEN/8, x2, x5, x6) + +inst_225: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x05b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x095 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x785b; op2val:0xb895; +op3val:0x74ff; valaddr_reg:x1; val_offset:570*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 570*FLEN/8, x2, x5, x6) + +inst_226: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x05b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x095 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x785b; op2val:0xb895; +op3val:0x74ff; valaddr_reg:x1; val_offset:573*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 573*FLEN/8, x2, x5, x6) + +inst_227: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x05b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x095 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x785b; op2val:0xb895; +op3val:0x74ff; valaddr_reg:x1; val_offset:576*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 576*FLEN/8, x2, x5, x6) + +inst_228: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x05b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x095 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x785b; op2val:0xb895; +op3val:0x74ff; valaddr_reg:x1; val_offset:579*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 579*FLEN/8, x2, x5, x6) + +inst_229: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x05b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x095 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x785b; op2val:0xb895; +op3val:0x74ff; valaddr_reg:x1; val_offset:582*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 582*FLEN/8, x2, x5, x6) + +inst_230: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x111 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x07b and fs3 == 0 and fe3 == 0x1c and fm3 == 0x1ad and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7511; op2val:0xb87b; +op3val:0x71ad; valaddr_reg:x1; val_offset:585*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 585*FLEN/8, x2, x5, x6) + +inst_231: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x111 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x07b and fs3 == 0 and fe3 == 0x1c and fm3 == 0x1ad and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7511; op2val:0xb87b; +op3val:0x71ad; valaddr_reg:x1; val_offset:588*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 588*FLEN/8, x2, x5, x6) + +inst_232: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x111 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x07b and fs3 == 0 and fe3 == 0x1c and fm3 == 0x1ad and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7511; op2val:0xb87b; +op3val:0x71ad; valaddr_reg:x1; val_offset:591*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 591*FLEN/8, x2, x5, x6) + +inst_233: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x111 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x07b and fs3 == 0 and fe3 == 0x1c and fm3 == 0x1ad and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7511; op2val:0xb87b; +op3val:0x71ad; valaddr_reg:x1; val_offset:594*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 594*FLEN/8, x2, x5, x6) + +inst_234: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x111 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x07b and fs3 == 0 and fe3 == 0x1c and fm3 == 0x1ad and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7511; op2val:0xb87b; +op3val:0x71ad; valaddr_reg:x1; val_offset:597*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 597*FLEN/8, x2, x5, x6) + +inst_235: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x100 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x39d and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0c3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d00; op2val:0xbf9d; +op3val:0x70c3; valaddr_reg:x1; val_offset:600*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 600*FLEN/8, x2, x5, x6) + +inst_236: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x100 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x39d and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0c3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d00; op2val:0xbf9d; +op3val:0x70c3; valaddr_reg:x1; val_offset:603*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 603*FLEN/8, x2, x5, x6) + +inst_237: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x100 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x39d and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0c3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d00; op2val:0xbf9d; +op3val:0x70c3; valaddr_reg:x1; val_offset:606*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 606*FLEN/8, x2, x5, x6) + +inst_238: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x100 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x39d and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0c3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d00; op2val:0xbf9d; +op3val:0x70c3; valaddr_reg:x1; val_offset:609*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 609*FLEN/8, x2, x5, x6) + +inst_239: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x100 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x39d and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0c3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d00; op2val:0xbf9d; +op3val:0x70c3; valaddr_reg:x1; val_offset:612*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 612*FLEN/8, x2, x5, x6) + +inst_240: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x182 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1c8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7982; op2val:0xbdc8; +op3val:0x7bf8; valaddr_reg:x1; val_offset:615*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 615*FLEN/8, x2, x5, x6) + +inst_241: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x182 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1c8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3f8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7982; op2val:0xbdc8; +op3val:0x7bf8; valaddr_reg:x1; val_offset:618*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 618*FLEN/8, x2, x5, x6) + +inst_242: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x182 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1c8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3f8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7982; op2val:0xbdc8; +op3val:0x7bf8; valaddr_reg:x1; val_offset:621*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 621*FLEN/8, x2, x5, x6) + +inst_243: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x182 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1c8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3f8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7982; op2val:0xbdc8; +op3val:0x7bf8; valaddr_reg:x1; val_offset:624*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 624*FLEN/8, x2, x5, x6) + +inst_244: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x182 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1c8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3f8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7982; op2val:0xbdc8; +op3val:0x7bf8; valaddr_reg:x1; val_offset:627*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 627*FLEN/8, x2, x5, x6) + +inst_245: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x12a and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0cf and fs3 == 0 and fe3 == 0x1a and fm3 == 0x236 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x712a; op2val:0xb4cf; +op3val:0x6a36; valaddr_reg:x1; val_offset:630*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 630*FLEN/8, x2, x5, x6) + +inst_246: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x12a and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0cf and fs3 == 0 and fe3 == 0x1a and fm3 == 0x236 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x712a; op2val:0xb4cf; +op3val:0x6a36; valaddr_reg:x1; val_offset:633*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 633*FLEN/8, x2, x5, x6) + +inst_247: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x12a and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0cf and fs3 == 0 and fe3 == 0x1a and fm3 == 0x236 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x712a; op2val:0xb4cf; +op3val:0x6a36; valaddr_reg:x1; val_offset:636*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 636*FLEN/8, x2, x5, x6) + +inst_248: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x12a and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0cf and fs3 == 0 and fe3 == 0x1a and fm3 == 0x236 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x712a; op2val:0xb4cf; +op3val:0x6a36; valaddr_reg:x1; val_offset:639*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 639*FLEN/8, x2, x5, x6) + +inst_249: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x12a and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0cf and fs3 == 0 and fe3 == 0x1a and fm3 == 0x236 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x712a; op2val:0xb4cf; +op3val:0x6a36; valaddr_reg:x1; val_offset:642*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 642*FLEN/8, x2, x5, x6) + +inst_250: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x053 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x044 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7be3; op2val:0xb853; +op3val:0x7844; valaddr_reg:x1; val_offset:645*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 645*FLEN/8, x2, x5, x6) + +inst_251: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x053 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x044 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7be3; op2val:0xb853; +op3val:0x7844; valaddr_reg:x1; val_offset:648*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 648*FLEN/8, x2, x5, x6) + +inst_252: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x053 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x044 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7be3; op2val:0xb853; +op3val:0x7844; valaddr_reg:x1; val_offset:651*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 651*FLEN/8, x2, x5, x6) + +inst_253: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x053 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x044 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7be3; op2val:0xb853; +op3val:0x7844; valaddr_reg:x1; val_offset:654*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 654*FLEN/8, x2, x5, x6) + +inst_254: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x053 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x044 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7be3; op2val:0xb853; +op3val:0x7844; valaddr_reg:x1; val_offset:657*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 657*FLEN/8, x2, x5, x6) + +inst_255: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x27d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0ad and fs3 == 0 and fe3 == 0x1c and fm3 == 0x397 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x767d; op2val:0xb8ad; +op3val:0x7397; valaddr_reg:x1; val_offset:660*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 660*FLEN/8, x2, x5, x6) + +inst_256: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x27d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0ad and fs3 == 0 and fe3 == 0x1c and fm3 == 0x397 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x767d; op2val:0xb8ad; +op3val:0x7397; valaddr_reg:x1; val_offset:663*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 663*FLEN/8, x2, x5, x6) + +inst_257: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x27d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0ad and fs3 == 0 and fe3 == 0x1c and fm3 == 0x397 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x767d; op2val:0xb8ad; +op3val:0x7397; valaddr_reg:x1; val_offset:666*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 666*FLEN/8, x2, x5, x6) + +inst_258: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x27d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0ad and fs3 == 0 and fe3 == 0x1c and fm3 == 0x397 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x767d; op2val:0xb8ad; +op3val:0x7397; valaddr_reg:x1; val_offset:669*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 669*FLEN/8, x2, x5, x6) + +inst_259: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x27d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0ad and fs3 == 0 and fe3 == 0x1c and fm3 == 0x397 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x767d; op2val:0xb8ad; +op3val:0x7397; valaddr_reg:x1; val_offset:672*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 672*FLEN/8, x2, x5, x6) + +inst_260: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0bf and fs2 == 1 and fe2 == 0x0f and fm2 == 0x190 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x29b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78bf; op2val:0xbd90; +op3val:0x7a9b; valaddr_reg:x1; val_offset:675*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 675*FLEN/8, x2, x5, x6) + +inst_261: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0bf and fs2 == 1 and fe2 == 0x0f and fm2 == 0x190 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x29b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78bf; op2val:0xbd90; +op3val:0x7a9b; valaddr_reg:x1; val_offset:678*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 678*FLEN/8, x2, x5, x6) + +inst_262: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0bf and fs2 == 1 and fe2 == 0x0f and fm2 == 0x190 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x29b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78bf; op2val:0xbd90; +op3val:0x7a9b; valaddr_reg:x1; val_offset:681*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 681*FLEN/8, x2, x5, x6) + +inst_263: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0bf and fs2 == 1 and fe2 == 0x0f and fm2 == 0x190 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x29b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78bf; op2val:0xbd90; +op3val:0x7a9b; valaddr_reg:x1; val_offset:684*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 684*FLEN/8, x2, x5, x6) + +inst_264: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0bf and fs2 == 1 and fe2 == 0x0f and fm2 == 0x190 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x29b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78bf; op2val:0xbd90; +op3val:0x7a9b; valaddr_reg:x1; val_offset:687*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 687*FLEN/8, x2, x5, x6) + +inst_265: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x367 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2be and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7749; op2val:0xbb67; +op3val:0x76be; valaddr_reg:x1; val_offset:690*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 690*FLEN/8, x2, x5, x6) + +inst_266: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x367 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2be and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7749; op2val:0xbb67; +op3val:0x76be; valaddr_reg:x1; val_offset:693*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 693*FLEN/8, x2, x5, x6) + +inst_267: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x367 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2be and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7749; op2val:0xbb67; +op3val:0x76be; valaddr_reg:x1; val_offset:696*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 696*FLEN/8, x2, x5, x6) + +inst_268: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x367 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2be and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7749; op2val:0xbb67; +op3val:0x76be; valaddr_reg:x1; val_offset:699*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 699*FLEN/8, x2, x5, x6) + +inst_269: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x367 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2be and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7749; op2val:0xbb67; +op3val:0x76be; valaddr_reg:x1; val_offset:702*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 702*FLEN/8, x2, x5, x6) + +inst_270: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x320 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x01c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x353 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6b20; op2val:0xcc1c; +op3val:0x7b53; valaddr_reg:x1; val_offset:705*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 705*FLEN/8, x2, x5, x6) + +inst_271: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x320 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x01c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x353 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6b20; op2val:0xcc1c; +op3val:0x7b53; valaddr_reg:x1; val_offset:708*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 708*FLEN/8, x2, x5, x6) + +inst_272: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x320 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x01c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x353 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6b20; op2val:0xcc1c; +op3val:0x7b53; valaddr_reg:x1; val_offset:711*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 711*FLEN/8, x2, x5, x6) + +inst_273: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x320 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x01c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x353 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6b20; op2val:0xcc1c; +op3val:0x7b53; valaddr_reg:x1; val_offset:714*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 714*FLEN/8, x2, x5, x6) + +inst_274: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x320 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x01c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x353 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6b20; op2val:0xcc1c; +op3val:0x7b53; valaddr_reg:x1; val_offset:717*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 717*FLEN/8, x2, x5, x6) + +inst_275: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x030 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x389 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3e4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6830; op2val:0xcb89; +op3val:0x77e4; valaddr_reg:x1; val_offset:720*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 720*FLEN/8, x2, x5, x6) + +inst_276: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x030 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x389 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3e4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6830; op2val:0xcb89; +op3val:0x77e4; valaddr_reg:x1; val_offset:723*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 723*FLEN/8, x2, x5, x6) + +inst_277: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x030 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x389 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3e4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6830; op2val:0xcb89; +op3val:0x77e4; valaddr_reg:x1; val_offset:726*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 726*FLEN/8, x2, x5, x6) + +inst_278: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x030 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x389 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3e4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6830; op2val:0xcb89; +op3val:0x77e4; valaddr_reg:x1; val_offset:729*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 729*FLEN/8, x2, x5, x6) + +inst_279: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x030 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x389 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3e4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6830; op2val:0xcb89; +op3val:0x77e4; valaddr_reg:x1; val_offset:732*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 732*FLEN/8, x2, x5, x6) + +inst_280: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b4 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0fb and fs3 == 0 and fe3 == 0x1c and fm3 == 0x02d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ab4; op2val:0xb0fb; +op3val:0x702d; valaddr_reg:x1; val_offset:735*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 735*FLEN/8, x2, x5, x6) + +inst_281: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b4 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0fb and fs3 == 0 and fe3 == 0x1c and fm3 == 0x02d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ab4; op2val:0xb0fb; +op3val:0x702d; valaddr_reg:x1; val_offset:738*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 738*FLEN/8, x2, x5, x6) + +inst_282: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b4 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0fb and fs3 == 0 and fe3 == 0x1c and fm3 == 0x02d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ab4; op2val:0xb0fb; +op3val:0x702d; valaddr_reg:x1; val_offset:741*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 741*FLEN/8, x2, x5, x6) + +inst_283: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b4 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0fb and fs3 == 0 and fe3 == 0x1c and fm3 == 0x02d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ab4; op2val:0xb0fb; +op3val:0x702d; valaddr_reg:x1; val_offset:744*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 744*FLEN/8, x2, x5, x6) +RVTEST_SIGBASE(x5,signature_x5_2) + +inst_284: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b4 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0fb and fs3 == 0 and fe3 == 0x1c and fm3 == 0x02d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ab4; op2val:0xb0fb; +op3val:0x702d; valaddr_reg:x1; val_offset:747*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 747*FLEN/8, x2, x5, x6) + +inst_285: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d9 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x131 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x398 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79d9; op2val:0xbd31; +op3val:0x7b98; valaddr_reg:x1; val_offset:750*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 750*FLEN/8, x2, x5, x6) + +inst_286: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d9 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x131 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x398 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79d9; op2val:0xbd31; +op3val:0x7b98; valaddr_reg:x1; val_offset:753*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 753*FLEN/8, x2, x5, x6) + +inst_287: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d9 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x131 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x398 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79d9; op2val:0xbd31; +op3val:0x7b98; valaddr_reg:x1; val_offset:756*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 756*FLEN/8, x2, x5, x6) + +inst_288: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d9 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x131 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x398 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79d9; op2val:0xbd31; +op3val:0x7b98; valaddr_reg:x1; val_offset:759*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 759*FLEN/8, x2, x5, x6) + +inst_289: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d9 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x131 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x398 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79d9; op2val:0xbd31; +op3val:0x7b98; valaddr_reg:x1; val_offset:762*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 762*FLEN/8, x2, x5, x6) + +inst_290: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x10a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x100 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x24d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x790a; op2val:0xbd00; +op3val:0x7a4d; valaddr_reg:x1; val_offset:765*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 765*FLEN/8, x2, x5, x6) + +inst_291: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x10a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x100 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x24d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x790a; op2val:0xbd00; +op3val:0x7a4d; valaddr_reg:x1; val_offset:768*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 768*FLEN/8, x2, x5, x6) + +inst_292: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x10a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x100 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x24d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x790a; op2val:0xbd00; +op3val:0x7a4d; valaddr_reg:x1; val_offset:771*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 771*FLEN/8, x2, x5, x6) + +inst_293: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x10a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x100 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x24d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x790a; op2val:0xbd00; +op3val:0x7a4d; valaddr_reg:x1; val_offset:774*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 774*FLEN/8, x2, x5, x6) + +inst_294: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x10a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x100 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x24d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x790a; op2val:0xbd00; +op3val:0x7a4d; valaddr_reg:x1; val_offset:777*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 777*FLEN/8, x2, x5, x6) + +inst_295: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2d2 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x013 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2f3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ed2; op2val:0xc413; +op3val:0x76f3; valaddr_reg:x1; val_offset:780*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 780*FLEN/8, x2, x5, x6) + +inst_296: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2d2 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x013 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2f3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ed2; op2val:0xc413; +op3val:0x76f3; valaddr_reg:x1; val_offset:783*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 783*FLEN/8, x2, x5, x6) + +inst_297: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2d2 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x013 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2f3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ed2; op2val:0xc413; +op3val:0x76f3; valaddr_reg:x1; val_offset:786*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 786*FLEN/8, x2, x5, x6) + +inst_298: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2d2 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x013 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2f3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ed2; op2val:0xc413; +op3val:0x76f3; valaddr_reg:x1; val_offset:789*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 789*FLEN/8, x2, x5, x6) + +inst_299: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2d2 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x013 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2f3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ed2; op2val:0xc413; +op3val:0x76f3; valaddr_reg:x1; val_offset:792*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 792*FLEN/8, x2, x5, x6) + +inst_300: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0c6 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1a8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2c1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70c6; op2val:0xc5a8; +op3val:0x7ac1; valaddr_reg:x1; val_offset:795*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 795*FLEN/8, x2, x5, x6) + +inst_301: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0c6 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1a8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2c1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70c6; op2val:0xc5a8; +op3val:0x7ac1; valaddr_reg:x1; val_offset:798*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 798*FLEN/8, x2, x5, x6) + +inst_302: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0c6 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1a8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2c1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70c6; op2val:0xc5a8; +op3val:0x7ac1; valaddr_reg:x1; val_offset:801*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 801*FLEN/8, x2, x5, x6) + +inst_303: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0c6 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1a8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2c1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70c6; op2val:0xc5a8; +op3val:0x7ac1; valaddr_reg:x1; val_offset:804*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 804*FLEN/8, x2, x5, x6) + +inst_304: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0c6 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1a8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2c1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70c6; op2val:0xc5a8; +op3val:0x7ac1; valaddr_reg:x1; val_offset:807*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 807*FLEN/8, x2, x5, x6) + +inst_305: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0b7 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x225 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x33f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74b7; op2val:0xbe25; +op3val:0x773f; valaddr_reg:x1; val_offset:810*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 810*FLEN/8, x2, x5, x6) + +inst_306: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0b7 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x225 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x33f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74b7; op2val:0xbe25; +op3val:0x773f; valaddr_reg:x1; val_offset:813*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 813*FLEN/8, x2, x5, x6) + +inst_307: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0b7 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x225 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x33f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74b7; op2val:0xbe25; +op3val:0x773f; valaddr_reg:x1; val_offset:816*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 816*FLEN/8, x2, x5, x6) + +inst_308: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0b7 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x225 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x33f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74b7; op2val:0xbe25; +op3val:0x773f; valaddr_reg:x1; val_offset:819*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 819*FLEN/8, x2, x5, x6) + +inst_309: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0b7 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x225 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x33f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74b7; op2val:0xbe25; +op3val:0x773f; valaddr_reg:x1; val_offset:822*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 822*FLEN/8, x2, x5, x6) + +inst_310: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3fd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2d2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2d0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bfd; op2val:0xbad2; +op3val:0x7ad0; valaddr_reg:x1; val_offset:825*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 825*FLEN/8, x2, x5, x6) + +inst_311: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3fd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2d2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2d0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bfd; op2val:0xbad2; +op3val:0x7ad0; valaddr_reg:x1; val_offset:828*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 828*FLEN/8, x2, x5, x6) + +inst_312: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3fd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2d2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2d0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bfd; op2val:0xbad2; +op3val:0x7ad0; valaddr_reg:x1; val_offset:831*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 831*FLEN/8, x2, x5, x6) + +inst_313: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3fd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2d2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2d0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bfd; op2val:0xbad2; +op3val:0x7ad0; valaddr_reg:x1; val_offset:834*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 834*FLEN/8, x2, x5, x6) + +inst_314: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3fd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2d2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2d0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bfd; op2val:0xbad2; +op3val:0x7ad0; valaddr_reg:x1; val_offset:837*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 837*FLEN/8, x2, x5, x6) + +inst_315: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3cd and fs2 == 1 and fe2 == 0x0d and fm2 == 0x36f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x340 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bcd; op2val:0xb76f; +op3val:0x7740; valaddr_reg:x1; val_offset:840*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 840*FLEN/8, x2, x5, x6) + +inst_316: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3cd and fs2 == 1 and fe2 == 0x0d and fm2 == 0x36f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x340 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bcd; op2val:0xb76f; +op3val:0x7740; valaddr_reg:x1; val_offset:843*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 843*FLEN/8, x2, x5, x6) + +inst_317: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3cd and fs2 == 1 and fe2 == 0x0d and fm2 == 0x36f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x340 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bcd; op2val:0xb76f; +op3val:0x7740; valaddr_reg:x1; val_offset:846*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 846*FLEN/8, x2, x5, x6) + +inst_318: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3cd and fs2 == 1 and fe2 == 0x0d and fm2 == 0x36f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x340 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bcd; op2val:0xb76f; +op3val:0x7740; valaddr_reg:x1; val_offset:849*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 849*FLEN/8, x2, x5, x6) + +inst_319: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3cd and fs2 == 1 and fe2 == 0x0d and fm2 == 0x36f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x340 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bcd; op2val:0xb76f; +op3val:0x7740; valaddr_reg:x1; val_offset:852*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 852*FLEN/8, x2, x5, x6) + +inst_320: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ce and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1fa and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1d5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77ce; op2val:0xbdfa; +op3val:0x79d5; valaddr_reg:x1; val_offset:855*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 855*FLEN/8, x2, x5, x6) + +inst_321: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ce and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1fa and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1d5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77ce; op2val:0xbdfa; +op3val:0x79d5; valaddr_reg:x1; val_offset:858*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 858*FLEN/8, x2, x5, x6) + +inst_322: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ce and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1fa and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1d5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77ce; op2val:0xbdfa; +op3val:0x79d5; valaddr_reg:x1; val_offset:861*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 861*FLEN/8, x2, x5, x6) + +inst_323: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ce and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1fa and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1d5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77ce; op2val:0xbdfa; +op3val:0x79d5; valaddr_reg:x1; val_offset:864*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 864*FLEN/8, x2, x5, x6) + +inst_324: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ce and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1fa and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1d5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77ce; op2val:0xbdfa; +op3val:0x79d5; valaddr_reg:x1; val_offset:867*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 867*FLEN/8, x2, x5, x6) + +inst_325: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a9 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0dc and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77a9; op2val:0xb8dc; +op3val:0x74a7; valaddr_reg:x1; val_offset:870*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 870*FLEN/8, x2, x5, x6) + +inst_326: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a9 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0dc and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77a9; op2val:0xb8dc; +op3val:0x74a7; valaddr_reg:x1; val_offset:873*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 873*FLEN/8, x2, x5, x6) + +inst_327: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a9 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0dc and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77a9; op2val:0xb8dc; +op3val:0x74a7; valaddr_reg:x1; val_offset:876*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 876*FLEN/8, x2, x5, x6) + +inst_328: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a9 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0dc and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77a9; op2val:0xb8dc; +op3val:0x74a7; valaddr_reg:x1; val_offset:879*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 879*FLEN/8, x2, x5, x6) + +inst_329: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a9 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0dc and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77a9; op2val:0xb8dc; +op3val:0x74a7; valaddr_reg:x1; val_offset:882*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 882*FLEN/8, x2, x5, x6) + +inst_330: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x275 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1ce and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0af and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7675; op2val:0xb5ce; +op3val:0x70af; valaddr_reg:x1; val_offset:885*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 885*FLEN/8, x2, x5, x6) + +inst_331: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x275 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1ce and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0af and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7675; op2val:0xb5ce; +op3val:0x70af; valaddr_reg:x1; val_offset:888*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 888*FLEN/8, x2, x5, x6) + +inst_332: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x275 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1ce and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0af and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7675; op2val:0xb5ce; +op3val:0x70af; valaddr_reg:x1; val_offset:891*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 891*FLEN/8, x2, x5, x6) + +inst_333: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x275 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1ce and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0af and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7675; op2val:0xb5ce; +op3val:0x70af; valaddr_reg:x1; val_offset:894*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 894*FLEN/8, x2, x5, x6) + +inst_334: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x275 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1ce and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0af and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7675; op2val:0xb5ce; +op3val:0x70af; valaddr_reg:x1; val_offset:897*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 897*FLEN/8, x2, x5, x6) + +inst_335: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x207 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x13e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3e7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7607; op2val:0xc13e; +op3val:0x7be7; valaddr_reg:x1; val_offset:900*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 900*FLEN/8, x2, x5, x6) + +inst_336: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x207 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x13e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3e7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7607; op2val:0xc13e; +op3val:0x7be7; valaddr_reg:x1; val_offset:903*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 903*FLEN/8, x2, x5, x6) + +inst_337: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x207 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x13e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3e7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7607; op2val:0xc13e; +op3val:0x7be7; valaddr_reg:x1; val_offset:906*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 906*FLEN/8, x2, x5, x6) + +inst_338: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x207 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x13e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3e7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7607; op2val:0xc13e; +op3val:0x7be7; valaddr_reg:x1; val_offset:909*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 909*FLEN/8, x2, x5, x6) + +inst_339: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x207 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x13e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3e7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7607; op2val:0xc13e; +op3val:0x7be7; valaddr_reg:x1; val_offset:912*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 912*FLEN/8, x2, x5, x6) + +inst_340: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ac and fs2 == 1 and fe2 == 0x0e and fm2 == 0x139 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x103 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bac; op2val:0xb939; +op3val:0x7903; valaddr_reg:x1; val_offset:915*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 915*FLEN/8, x2, x5, x6) + +inst_341: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ac and fs2 == 1 and fe2 == 0x0e and fm2 == 0x139 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x103 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bac; op2val:0xb939; +op3val:0x7903; valaddr_reg:x1; val_offset:918*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 918*FLEN/8, x2, x5, x6) + +inst_342: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ac and fs2 == 1 and fe2 == 0x0e and fm2 == 0x139 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x103 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bac; op2val:0xb939; +op3val:0x7903; valaddr_reg:x1; val_offset:921*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 921*FLEN/8, x2, x5, x6) + +inst_343: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ac and fs2 == 1 and fe2 == 0x0e and fm2 == 0x139 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x103 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bac; op2val:0xb939; +op3val:0x7903; valaddr_reg:x1; val_offset:924*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 924*FLEN/8, x2, x5, x6) + +inst_344: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ac and fs2 == 1 and fe2 == 0x0e and fm2 == 0x139 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x103 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bac; op2val:0xb939; +op3val:0x7903; valaddr_reg:x1; val_offset:927*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 927*FLEN/8, x2, x5, x6) + +inst_345: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x16c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x169 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77fc; op2val:0xb96c; +op3val:0x7569; valaddr_reg:x1; val_offset:930*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 930*FLEN/8, x2, x5, x6) + +inst_346: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x16c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x169 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77fc; op2val:0xb96c; +op3val:0x7569; valaddr_reg:x1; val_offset:933*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 933*FLEN/8, x2, x5, x6) + +inst_347: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x16c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x169 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77fc; op2val:0xb96c; +op3val:0x7569; valaddr_reg:x1; val_offset:936*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 936*FLEN/8, x2, x5, x6) + +inst_348: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x16c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x169 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77fc; op2val:0xb96c; +op3val:0x7569; valaddr_reg:x1; val_offset:939*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 939*FLEN/8, x2, x5, x6) + +inst_349: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x16c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x169 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77fc; op2val:0xb96c; +op3val:0x7569; valaddr_reg:x1; val_offset:942*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 942*FLEN/8, x2, x5, x6) + +inst_350: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1b3 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x21b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x05a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6db3; op2val:0xc21b; +op3val:0x745a; valaddr_reg:x1; val_offset:945*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 945*FLEN/8, x2, x5, x6) + +inst_351: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1b3 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x21b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x05a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6db3; op2val:0xc21b; +op3val:0x745a; valaddr_reg:x1; val_offset:948*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 948*FLEN/8, x2, x5, x6) + +inst_352: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1b3 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x21b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x05a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6db3; op2val:0xc21b; +op3val:0x745a; valaddr_reg:x1; val_offset:951*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 951*FLEN/8, x2, x5, x6) + +inst_353: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1b3 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x21b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x05a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6db3; op2val:0xc21b; +op3val:0x745a; valaddr_reg:x1; val_offset:954*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 954*FLEN/8, x2, x5, x6) + +inst_354: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1b3 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x21b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x05a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6db3; op2val:0xc21b; +op3val:0x745a; valaddr_reg:x1; val_offset:957*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 957*FLEN/8, x2, x5, x6) + +inst_355: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x240 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x06f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ef and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a40; op2val:0xbc6f; +op3val:0x7aef; valaddr_reg:x1; val_offset:960*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 960*FLEN/8, x2, x5, x6) + +inst_356: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x240 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x06f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ef and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a40; op2val:0xbc6f; +op3val:0x7aef; valaddr_reg:x1; val_offset:963*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 963*FLEN/8, x2, x5, x6) + +inst_357: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x240 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x06f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ef and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a40; op2val:0xbc6f; +op3val:0x7aef; valaddr_reg:x1; val_offset:966*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 966*FLEN/8, x2, x5, x6) + +inst_358: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x240 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x06f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ef and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a40; op2val:0xbc6f; +op3val:0x7aef; valaddr_reg:x1; val_offset:969*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 969*FLEN/8, x2, x5, x6) + +inst_359: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x240 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x06f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ef and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a40; op2val:0xbc6f; +op3val:0x7aef; valaddr_reg:x1; val_offset:972*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 972*FLEN/8, x2, x5, x6) + +inst_360: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c7 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x059 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x248 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c7; op2val:0xc059; +op3val:0x7a48; valaddr_reg:x1; val_offset:975*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 975*FLEN/8, x2, x5, x6) + +inst_361: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c7 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x059 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x248 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c7; op2val:0xc059; +op3val:0x7a48; valaddr_reg:x1; val_offset:978*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 978*FLEN/8, x2, x5, x6) + +inst_362: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c7 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x059 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x248 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c7; op2val:0xc059; +op3val:0x7a48; valaddr_reg:x1; val_offset:981*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 981*FLEN/8, x2, x5, x6) + +inst_363: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c7 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x059 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x248 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c7; op2val:0xc059; +op3val:0x7a48; valaddr_reg:x1; val_offset:984*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 984*FLEN/8, x2, x5, x6) + +inst_364: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c7 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x059 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x248 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c7; op2val:0xc059; +op3val:0x7a48; valaddr_reg:x1; val_offset:987*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 987*FLEN/8, x2, x5, x6) + +inst_365: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x232 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x32b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x18d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a32; op2val:0xbb2b; +op3val:0x798d; valaddr_reg:x1; val_offset:990*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 990*FLEN/8, x2, x5, x6) + +inst_366: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x232 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x32b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x18d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a32; op2val:0xbb2b; +op3val:0x798d; valaddr_reg:x1; val_offset:993*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 993*FLEN/8, x2, x5, x6) + +inst_367: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x232 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x32b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x18d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a32; op2val:0xbb2b; +op3val:0x798d; valaddr_reg:x1; val_offset:996*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 996*FLEN/8, x2, x5, x6) + +inst_368: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x232 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x32b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x18d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a32; op2val:0xbb2b; +op3val:0x798d; valaddr_reg:x1; val_offset:999*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 999*FLEN/8, x2, x5, x6) + +inst_369: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x232 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x32b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x18d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a32; op2val:0xbb2b; +op3val:0x798d; valaddr_reg:x1; val_offset:1002*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1002*FLEN/8, x2, x5, x6) + +inst_370: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x14f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x093 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x212 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x794f; op2val:0xbc93; +op3val:0x7a12; valaddr_reg:x1; val_offset:1005*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1005*FLEN/8, x2, x5, x6) + +inst_371: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x14f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x093 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x212 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x794f; op2val:0xbc93; +op3val:0x7a12; valaddr_reg:x1; val_offset:1008*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1008*FLEN/8, x2, x5, x6) + +inst_372: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x14f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x093 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x212 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x794f; op2val:0xbc93; +op3val:0x7a12; valaddr_reg:x1; val_offset:1011*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1011*FLEN/8, x2, x5, x6) + +inst_373: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x14f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x093 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x212 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x794f; op2val:0xbc93; +op3val:0x7a12; valaddr_reg:x1; val_offset:1014*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1014*FLEN/8, x2, x5, x6) + +inst_374: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x14f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x093 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x212 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x794f; op2val:0xbc93; +op3val:0x7a12; valaddr_reg:x1; val_offset:1017*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1017*FLEN/8, x2, x5, x6) + +inst_375: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1cf and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3c0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75cf; op2val:0xbfc0; +op3val:0x79a2; valaddr_reg:x1; val_offset:1020*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1020*FLEN/8, x2, x5, x6) + +inst_376: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1cf and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3c0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75cf; op2val:0xbfc0; +op3val:0x79a2; valaddr_reg:x1; val_offset:1023*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1023*FLEN/8, x2, x5, x6) + +inst_377: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1cf and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3c0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75cf; op2val:0xbfc0; +op3val:0x79a2; valaddr_reg:x1; val_offset:1026*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1026*FLEN/8, x2, x5, x6) + +inst_378: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1cf and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3c0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75cf; op2val:0xbfc0; +op3val:0x79a2; valaddr_reg:x1; val_offset:1029*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1029*FLEN/8, x2, x5, x6) + +inst_379: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1cf and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3c0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75cf; op2val:0xbfc0; +op3val:0x79a2; valaddr_reg:x1; val_offset:1032*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1032*FLEN/8, x2, x5, x6) + +inst_380: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x07d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2ea and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3c4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x747d; op2val:0xbeea; +op3val:0x77c4; valaddr_reg:x1; val_offset:1035*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1035*FLEN/8, x2, x5, x6) + +inst_381: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x07d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2ea and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3c4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x747d; op2val:0xbeea; +op3val:0x77c4; valaddr_reg:x1; val_offset:1038*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1038*FLEN/8, x2, x5, x6) + +inst_382: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x07d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2ea and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3c4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x747d; op2val:0xbeea; +op3val:0x77c4; valaddr_reg:x1; val_offset:1041*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1041*FLEN/8, x2, x5, x6) + +inst_383: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x07d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2ea and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3c4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x747d; op2val:0xbeea; +op3val:0x77c4; valaddr_reg:x1; val_offset:1044*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1044*FLEN/8, x2, x5, x6) + +inst_384: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x07d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2ea and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3c4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x747d; op2val:0xbeea; +op3val:0x77c4; valaddr_reg:x1; val_offset:1047*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1047*FLEN/8, x2, x5, x6) + +inst_385: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x227 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x32e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x186 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a27; op2val:0xbb2e; +op3val:0x7986; valaddr_reg:x1; val_offset:1050*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1050*FLEN/8, x2, x5, x6) + +inst_386: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x227 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x32e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x186 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a27; op2val:0xbb2e; +op3val:0x7986; valaddr_reg:x1; val_offset:1053*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1053*FLEN/8, x2, x5, x6) + +inst_387: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x227 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x32e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x186 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a27; op2val:0xbb2e; +op3val:0x7986; valaddr_reg:x1; val_offset:1056*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1056*FLEN/8, x2, x5, x6) + +inst_388: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x227 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x32e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x186 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a27; op2val:0xbb2e; +op3val:0x7986; valaddr_reg:x1; val_offset:1059*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1059*FLEN/8, x2, x5, x6) + +inst_389: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x227 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x32e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x186 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a27; op2val:0xbb2e; +op3val:0x7986; valaddr_reg:x1; val_offset:1062*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1062*FLEN/8, x2, x5, x6) + +inst_390: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0b3 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x26f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x38f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74b3; op2val:0xc26f; +op3val:0x7b8f; valaddr_reg:x1; val_offset:1065*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1065*FLEN/8, x2, x5, x6) + +inst_391: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0b3 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x26f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x38f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74b3; op2val:0xc26f; +op3val:0x7b8f; valaddr_reg:x1; val_offset:1068*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1068*FLEN/8, x2, x5, x6) + +inst_392: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0b3 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x26f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x38f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74b3; op2val:0xc26f; +op3val:0x7b8f; valaddr_reg:x1; val_offset:1071*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1071*FLEN/8, x2, x5, x6) + +inst_393: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0b3 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x26f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x38f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74b3; op2val:0xc26f; +op3val:0x7b8f; valaddr_reg:x1; val_offset:1074*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1074*FLEN/8, x2, x5, x6) + +inst_394: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0b3 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x26f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x38f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74b3; op2val:0xc26f; +op3val:0x7b8f; valaddr_reg:x1; val_offset:1077*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1077*FLEN/8, x2, x5, x6) + +inst_395: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x131 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x326 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7931; op2val:0xbb26; +op3val:0x78a4; valaddr_reg:x1; val_offset:1080*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1080*FLEN/8, x2, x5, x6) + +inst_396: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x131 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x326 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7931; op2val:0xbb26; +op3val:0x78a4; valaddr_reg:x1; val_offset:1083*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1083*FLEN/8, x2, x5, x6) + +inst_397: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x131 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x326 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7931; op2val:0xbb26; +op3val:0x78a4; valaddr_reg:x1; val_offset:1086*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1086*FLEN/8, x2, x5, x6) + +inst_398: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x131 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x326 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7931; op2val:0xbb26; +op3val:0x78a4; valaddr_reg:x1; val_offset:1089*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1089*FLEN/8, x2, x5, x6) + +inst_399: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x131 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x326 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7931; op2val:0xbb26; +op3val:0x78a4; valaddr_reg:x1; val_offset:1092*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1092*FLEN/8, x2, x5, x6) + +inst_400: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x1ef and fs2 == 1 and fe2 == 0x14 and fm2 == 0x1e5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x05f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x61ef; op2val:0xd1e5; +op3val:0x785f; valaddr_reg:x1; val_offset:1095*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1095*FLEN/8, x2, x5, x6) + +inst_401: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x1ef and fs2 == 1 and fe2 == 0x14 and fm2 == 0x1e5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x05f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x61ef; op2val:0xd1e5; +op3val:0x785f; valaddr_reg:x1; val_offset:1098*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1098*FLEN/8, x2, x5, x6) + +inst_402: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x1ef and fs2 == 1 and fe2 == 0x14 and fm2 == 0x1e5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x05f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x61ef; op2val:0xd1e5; +op3val:0x785f; valaddr_reg:x1; val_offset:1101*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1101*FLEN/8, x2, x5, x6) + +inst_403: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x1ef and fs2 == 1 and fe2 == 0x14 and fm2 == 0x1e5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x05f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x61ef; op2val:0xd1e5; +op3val:0x785f; valaddr_reg:x1; val_offset:1104*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1104*FLEN/8, x2, x5, x6) + +inst_404: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x1ef and fs2 == 1 and fe2 == 0x14 and fm2 == 0x1e5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x05f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x61ef; op2val:0xd1e5; +op3val:0x785f; valaddr_reg:x1; val_offset:1107*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1107*FLEN/8, x2, x5, x6) + +inst_405: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x002 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x15b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x15e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7402; op2val:0xc15b; +op3val:0x795e; valaddr_reg:x1; val_offset:1110*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1110*FLEN/8, x2, x5, x6) + +inst_406: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x002 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x15b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x15e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7402; op2val:0xc15b; +op3val:0x795e; valaddr_reg:x1; val_offset:1113*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1113*FLEN/8, x2, x5, x6) + +inst_407: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x002 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x15b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x15e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7402; op2val:0xc15b; +op3val:0x795e; valaddr_reg:x1; val_offset:1116*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1116*FLEN/8, x2, x5, x6) + +inst_408: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x002 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x15b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x15e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7402; op2val:0xc15b; +op3val:0x795e; valaddr_reg:x1; val_offset:1119*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1119*FLEN/8, x2, x5, x6) + +inst_409: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x002 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x15b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x15e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7402; op2val:0xc15b; +op3val:0x795e; valaddr_reg:x1; val_offset:1122*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1122*FLEN/8, x2, x5, x6) + +inst_410: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x367 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x30e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x287 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7767; op2val:0xbf0e; +op3val:0x7a87; valaddr_reg:x1; val_offset:1125*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1125*FLEN/8, x2, x5, x6) + +inst_411: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x367 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x30e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x287 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7767; op2val:0xbf0e; +op3val:0x7a87; valaddr_reg:x1; val_offset:1128*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1128*FLEN/8, x2, x5, x6) +RVTEST_SIGBASE(x5,signature_x5_3) + +inst_412: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x367 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x30e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x287 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7767; op2val:0xbf0e; +op3val:0x7a87; valaddr_reg:x1; val_offset:1131*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1131*FLEN/8, x2, x5, x6) + +inst_413: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x367 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x30e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x287 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7767; op2val:0xbf0e; +op3val:0x7a87; valaddr_reg:x1; val_offset:1134*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1134*FLEN/8, x2, x5, x6) + +inst_414: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x367 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x30e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x287 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7767; op2val:0xbf0e; +op3val:0x7a87; valaddr_reg:x1; val_offset:1137*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1137*FLEN/8, x2, x5, x6) + +inst_415: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0ed and fs3 == 0 and fe3 == 0x1e and fm3 == 0x260 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x792d; op2val:0xbced; +op3val:0x7a60; valaddr_reg:x1; val_offset:1140*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1140*FLEN/8, x2, x5, x6) + +inst_416: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0ed and fs3 == 0 and fe3 == 0x1e and fm3 == 0x260 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x792d; op2val:0xbced; +op3val:0x7a60; valaddr_reg:x1; val_offset:1143*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1143*FLEN/8, x2, x5, x6) + +inst_417: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0ed and fs3 == 0 and fe3 == 0x1e and fm3 == 0x260 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x792d; op2val:0xbced; +op3val:0x7a60; valaddr_reg:x1; val_offset:1146*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1146*FLEN/8, x2, x5, x6) + +inst_418: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0ed and fs3 == 0 and fe3 == 0x1e and fm3 == 0x260 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x792d; op2val:0xbced; +op3val:0x7a60; valaddr_reg:x1; val_offset:1149*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1149*FLEN/8, x2, x5, x6) + +inst_419: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0ed and fs3 == 0 and fe3 == 0x1e and fm3 == 0x260 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x792d; op2val:0xbced; +op3val:0x7a60; valaddr_reg:x1; val_offset:1152*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1152*FLEN/8, x2, x5, x6) + +inst_420: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x190 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x367 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x126 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7590; op2val:0xbf67; +op3val:0x7926; valaddr_reg:x1; val_offset:1155*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1155*FLEN/8, x2, x5, x6) + +inst_421: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x190 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x367 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x126 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7590; op2val:0xbf67; +op3val:0x7926; valaddr_reg:x1; val_offset:1158*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1158*FLEN/8, x2, x5, x6) + +inst_422: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x190 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x367 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x126 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7590; op2val:0xbf67; +op3val:0x7926; valaddr_reg:x1; val_offset:1161*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1161*FLEN/8, x2, x5, x6) + +inst_423: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x190 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x367 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x126 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7590; op2val:0xbf67; +op3val:0x7926; valaddr_reg:x1; val_offset:1164*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1164*FLEN/8, x2, x5, x6) + +inst_424: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x190 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x367 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x126 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7590; op2val:0xbf67; +op3val:0x7926; valaddr_reg:x1; val_offset:1167*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1167*FLEN/8, x2, x5, x6) + +inst_425: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1e6 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x07d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x29f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79e6; op2val:0xbc7d; +op3val:0x7a9f; valaddr_reg:x1; val_offset:1170*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1170*FLEN/8, x2, x5, x6) + +inst_426: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1e6 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x07d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x29f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79e6; op2val:0xbc7d; +op3val:0x7a9f; valaddr_reg:x1; val_offset:1173*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1173*FLEN/8, x2, x5, x6) + +inst_427: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1e6 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x07d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x29f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79e6; op2val:0xbc7d; +op3val:0x7a9f; valaddr_reg:x1; val_offset:1176*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1176*FLEN/8, x2, x5, x6) + +inst_428: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1e6 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x07d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x29f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79e6; op2val:0xbc7d; +op3val:0x7a9f; valaddr_reg:x1; val_offset:1179*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1179*FLEN/8, x2, x5, x6) + +inst_429: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1e6 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x07d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x29f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79e6; op2val:0xbc7d; +op3val:0x7a9f; valaddr_reg:x1; val_offset:1182*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1182*FLEN/8, x2, x5, x6) + +inst_430: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x199 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0d0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2bd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7599; op2val:0xc0d0; +op3val:0x7abd; valaddr_reg:x1; val_offset:1185*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1185*FLEN/8, x2, x5, x6) + +inst_431: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x199 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0d0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2bd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7599; op2val:0xc0d0; +op3val:0x7abd; valaddr_reg:x1; val_offset:1188*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1188*FLEN/8, x2, x5, x6) + +inst_432: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x199 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0d0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2bd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7599; op2val:0xc0d0; +op3val:0x7abd; valaddr_reg:x1; val_offset:1191*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1191*FLEN/8, x2, x5, x6) + +inst_433: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x199 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0d0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2bd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7599; op2val:0xc0d0; +op3val:0x7abd; valaddr_reg:x1; val_offset:1194*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1194*FLEN/8, x2, x5, x6) + +inst_434: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x199 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0d0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2bd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7599; op2val:0xc0d0; +op3val:0x7abd; valaddr_reg:x1; val_offset:1197*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1197*FLEN/8, x2, x5, x6) + +inst_435: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x254 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x181 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7af4; op2val:0xba54; +op3val:0x7981; valaddr_reg:x1; val_offset:1200*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1200*FLEN/8, x2, x5, x6) + +inst_436: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x254 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x181 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7af4; op2val:0xba54; +op3val:0x7981; valaddr_reg:x1; val_offset:1203*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1203*FLEN/8, x2, x5, x6) + +inst_437: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x254 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x181 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7af4; op2val:0xba54; +op3val:0x7981; valaddr_reg:x1; val_offset:1206*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1206*FLEN/8, x2, x5, x6) + +inst_438: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x254 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x181 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7af4; op2val:0xba54; +op3val:0x7981; valaddr_reg:x1; val_offset:1209*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1209*FLEN/8, x2, x5, x6) + +inst_439: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x254 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x181 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7af4; op2val:0xba54; +op3val:0x7981; valaddr_reg:x1; val_offset:1212*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1212*FLEN/8, x2, x5, x6) + +inst_440: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ce and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3d6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3a5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bce; op2val:0xbbd6; +op3val:0x7ba5; valaddr_reg:x1; val_offset:1215*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1215*FLEN/8, x2, x5, x6) + +inst_441: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ce and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3d6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3a5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bce; op2val:0xbbd6; +op3val:0x7ba5; valaddr_reg:x1; val_offset:1218*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1218*FLEN/8, x2, x5, x6) + +inst_442: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ce and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3d6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3a5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bce; op2val:0xbbd6; +op3val:0x7ba5; valaddr_reg:x1; val_offset:1221*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1221*FLEN/8, x2, x5, x6) + +inst_443: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ce and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3d6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3a5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bce; op2val:0xbbd6; +op3val:0x7ba5; valaddr_reg:x1; val_offset:1224*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1224*FLEN/8, x2, x5, x6) + +inst_444: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ce and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3d6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3a5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bce; op2val:0xbbd6; +op3val:0x7ba5; valaddr_reg:x1; val_offset:1227*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1227*FLEN/8, x2, x5, x6) + +inst_445: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x024 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x016 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x03b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7824; op2val:0xbc16; +op3val:0x783b; valaddr_reg:x1; val_offset:1230*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1230*FLEN/8, x2, x5, x6) + +inst_446: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x024 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x016 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x03b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7824; op2val:0xbc16; +op3val:0x783b; valaddr_reg:x1; val_offset:1233*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1233*FLEN/8, x2, x5, x6) + +inst_447: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x024 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x016 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x03b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7824; op2val:0xbc16; +op3val:0x783b; valaddr_reg:x1; val_offset:1236*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1236*FLEN/8, x2, x5, x6) + +inst_448: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x024 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x016 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x03b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7824; op2val:0xbc16; +op3val:0x783b; valaddr_reg:x1; val_offset:1239*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1239*FLEN/8, x2, x5, x6) + +inst_449: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x024 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x016 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x03b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7824; op2val:0xbc16; +op3val:0x783b; valaddr_reg:x1; val_offset:1242*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1242*FLEN/8, x2, x5, x6) + +inst_450: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x150 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x108 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2b0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7150; op2val:0xc508; +op3val:0x7ab0; valaddr_reg:x1; val_offset:1245*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1245*FLEN/8, x2, x5, x6) + +inst_451: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x150 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x108 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2b0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7150; op2val:0xc508; +op3val:0x7ab0; valaddr_reg:x1; val_offset:1248*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1248*FLEN/8, x2, x5, x6) + +inst_452: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x150 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x108 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2b0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7150; op2val:0xc508; +op3val:0x7ab0; valaddr_reg:x1; val_offset:1251*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1251*FLEN/8, x2, x5, x6) + +inst_453: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x150 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x108 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2b0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7150; op2val:0xc508; +op3val:0x7ab0; valaddr_reg:x1; val_offset:1254*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1254*FLEN/8, x2, x5, x6) + +inst_454: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x150 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x108 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2b0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7150; op2val:0xc508; +op3val:0x7ab0; valaddr_reg:x1; val_offset:1257*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1257*FLEN/8, x2, x5, x6) + +inst_455: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x012 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3a1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b7e; op2val:0xb812; +op3val:0x77a1; valaddr_reg:x1; val_offset:1260*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1260*FLEN/8, x2, x5, x6) + +inst_456: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x012 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3a1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b7e; op2val:0xb812; +op3val:0x77a1; valaddr_reg:x1; val_offset:1263*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1263*FLEN/8, x2, x5, x6) + +inst_457: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x012 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3a1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b7e; op2val:0xb812; +op3val:0x77a1; valaddr_reg:x1; val_offset:1266*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1266*FLEN/8, x2, x5, x6) + +inst_458: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x012 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3a1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b7e; op2val:0xb812; +op3val:0x77a1; valaddr_reg:x1; val_offset:1269*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1269*FLEN/8, x2, x5, x6) + +inst_459: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x012 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3a1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b7e; op2val:0xb812; +op3val:0x77a1; valaddr_reg:x1; val_offset:1272*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1272*FLEN/8, x2, x5, x6) + +inst_460: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x187 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x029 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1c1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7987; op2val:0xbc29; +op3val:0x79c1; valaddr_reg:x1; val_offset:1275*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1275*FLEN/8, x2, x5, x6) + +inst_461: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x187 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x029 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1c1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7987; op2val:0xbc29; +op3val:0x79c1; valaddr_reg:x1; val_offset:1278*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1278*FLEN/8, x2, x5, x6) + +inst_462: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x187 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x029 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1c1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7987; op2val:0xbc29; +op3val:0x79c1; valaddr_reg:x1; val_offset:1281*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1281*FLEN/8, x2, x5, x6) + +inst_463: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x187 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x029 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1c1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7987; op2val:0xbc29; +op3val:0x79c1; valaddr_reg:x1; val_offset:1284*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1284*FLEN/8, x2, x5, x6) + +inst_464: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x187 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x029 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1c1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7987; op2val:0xbc29; +op3val:0x79c1; valaddr_reg:x1; val_offset:1287*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1287*FLEN/8, x2, x5, x6) + +inst_465: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d7 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x387 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x17f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79d7; op2val:0xb387; +op3val:0x717f; valaddr_reg:x1; val_offset:1290*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1290*FLEN/8, x2, x5, x6) + +inst_466: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d7 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x387 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x17f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79d7; op2val:0xb387; +op3val:0x717f; valaddr_reg:x1; val_offset:1293*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1293*FLEN/8, x2, x5, x6) + +inst_467: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d7 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x387 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x17f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79d7; op2val:0xb387; +op3val:0x717f; valaddr_reg:x1; val_offset:1296*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1296*FLEN/8, x2, x5, x6) + +inst_468: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d7 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x387 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x17f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79d7; op2val:0xb387; +op3val:0x717f; valaddr_reg:x1; val_offset:1299*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1299*FLEN/8, x2, x5, x6) + +inst_469: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d7 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x387 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x17f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79d7; op2val:0xb387; +op3val:0x717f; valaddr_reg:x1; val_offset:1302*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1302*FLEN/8, x2, x5, x6) + +inst_470: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x23d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1f4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a3d; op2val:0xb9f4; +op3val:0x78a5; valaddr_reg:x1; val_offset:1305*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1305*FLEN/8, x2, x5, x6) + +inst_471: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x23d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1f4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a3d; op2val:0xb9f4; +op3val:0x78a5; valaddr_reg:x1; val_offset:1308*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1308*FLEN/8, x2, x5, x6) + +inst_472: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x23d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1f4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a3d; op2val:0xb9f4; +op3val:0x78a5; valaddr_reg:x1; val_offset:1311*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1311*FLEN/8, x2, x5, x6) + +inst_473: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x23d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1f4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a3d; op2val:0xb9f4; +op3val:0x78a5; valaddr_reg:x1; val_offset:1314*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1314*FLEN/8, x2, x5, x6) + +inst_474: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x23d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1f4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a3d; op2val:0xb9f4; +op3val:0x78a5; valaddr_reg:x1; val_offset:1317*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1317*FLEN/8, x2, x5, x6) + +inst_475: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x152 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x10e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2ba and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7952; op2val:0xb90e; +op3val:0x76ba; valaddr_reg:x1; val_offset:1320*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1320*FLEN/8, x2, x5, x6) + +inst_476: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x152 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x10e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2ba and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7952; op2val:0xb90e; +op3val:0x76ba; valaddr_reg:x1; val_offset:1323*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1323*FLEN/8, x2, x5, x6) + +inst_477: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x152 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x10e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2ba and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7952; op2val:0xb90e; +op3val:0x76ba; valaddr_reg:x1; val_offset:1326*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1326*FLEN/8, x2, x5, x6) + +inst_478: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x152 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x10e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2ba and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7952; op2val:0xb90e; +op3val:0x76ba; valaddr_reg:x1; val_offset:1329*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1329*FLEN/8, x2, x5, x6) + +inst_479: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x152 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x10e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2ba and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7952; op2val:0xb90e; +op3val:0x76ba; valaddr_reg:x1; val_offset:1332*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1332*FLEN/8, x2, x5, x6) + +inst_480: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fc and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x231 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fc; op2val:0xbcf7; +op3val:0x7a31; valaddr_reg:x1; val_offset:1335*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1335*FLEN/8, x2, x5, x6) + +inst_481: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fc and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x231 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fc; op2val:0xbcf7; +op3val:0x7a31; valaddr_reg:x1; val_offset:1338*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1338*FLEN/8, x2, x5, x6) + +inst_482: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fc and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x231 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fc; op2val:0xbcf7; +op3val:0x7a31; valaddr_reg:x1; val_offset:1341*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1341*FLEN/8, x2, x5, x6) + +inst_483: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fc and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x231 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fc; op2val:0xbcf7; +op3val:0x7a31; valaddr_reg:x1; val_offset:1344*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1344*FLEN/8, x2, x5, x6) + +inst_484: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fc and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x231 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fc; op2val:0xbcf7; +op3val:0x7a31; valaddr_reg:x1; val_offset:1347*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1347*FLEN/8, x2, x5, x6) + +inst_485: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x117 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x086 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1c2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7917; op2val:0xbc86; +op3val:0x79c2; valaddr_reg:x1; val_offset:1350*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1350*FLEN/8, x2, x5, x6) + +inst_486: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x117 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x086 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1c2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7917; op2val:0xbc86; +op3val:0x79c2; valaddr_reg:x1; val_offset:1353*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1353*FLEN/8, x2, x5, x6) + +inst_487: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x117 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x086 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1c2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7917; op2val:0xbc86; +op3val:0x79c2; valaddr_reg:x1; val_offset:1356*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1356*FLEN/8, x2, x5, x6) + +inst_488: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x117 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x086 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1c2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7917; op2val:0xbc86; +op3val:0x79c2; valaddr_reg:x1; val_offset:1359*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1359*FLEN/8, x2, x5, x6) + +inst_489: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x117 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x086 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1c2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7917; op2val:0xbc86; +op3val:0x79c2; valaddr_reg:x1; val_offset:1362*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1362*FLEN/8, x2, x5, x6) + +inst_490: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x312 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1ca and fs3 == 0 and fe3 == 0x1c and fm3 == 0x11e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6712; op2val:0xc5ca; +op3val:0x711e; valaddr_reg:x1; val_offset:1365*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1365*FLEN/8, x2, x5, x6) + +inst_491: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x312 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1ca and fs3 == 0 and fe3 == 0x1c and fm3 == 0x11e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6712; op2val:0xc5ca; +op3val:0x711e; valaddr_reg:x1; val_offset:1368*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1368*FLEN/8, x2, x5, x6) + +inst_492: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x312 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1ca and fs3 == 0 and fe3 == 0x1c and fm3 == 0x11e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6712; op2val:0xc5ca; +op3val:0x711e; valaddr_reg:x1; val_offset:1371*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1371*FLEN/8, x2, x5, x6) + +inst_493: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x312 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1ca and fs3 == 0 and fe3 == 0x1c and fm3 == 0x11e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6712; op2val:0xc5ca; +op3val:0x711e; valaddr_reg:x1; val_offset:1374*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1374*FLEN/8, x2, x5, x6) + +inst_494: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x312 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1ca and fs3 == 0 and fe3 == 0x1c and fm3 == 0x11e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6712; op2val:0xc5ca; +op3val:0x711e; valaddr_reg:x1; val_offset:1377*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1377*FLEN/8, x2, x5, x6) + +inst_495: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x30d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1e5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x132 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x770d; op2val:0xbde5; +op3val:0x7932; valaddr_reg:x1; val_offset:1380*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1380*FLEN/8, x2, x5, x6) + +inst_496: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x30d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1e5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x132 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x770d; op2val:0xbde5; +op3val:0x7932; valaddr_reg:x1; val_offset:1383*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1383*FLEN/8, x2, x5, x6) + +inst_497: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x30d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1e5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x132 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x770d; op2val:0xbde5; +op3val:0x7932; valaddr_reg:x1; val_offset:1386*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1386*FLEN/8, x2, x5, x6) + +inst_498: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x30d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1e5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x132 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x770d; op2val:0xbde5; +op3val:0x7932; valaddr_reg:x1; val_offset:1389*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1389*FLEN/8, x2, x5, x6) + +inst_499: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x30d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1e5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x132 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x770d; op2val:0xbde5; +op3val:0x7932; valaddr_reg:x1; val_offset:1392*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1392*FLEN/8, x2, x5, x6) + +inst_500: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x301 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x243 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x17c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7301; op2val:0xc243; +op3val:0x797c; valaddr_reg:x1; val_offset:1395*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1395*FLEN/8, x2, x5, x6) + +inst_501: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x301 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x243 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x17c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7301; op2val:0xc243; +op3val:0x797c; valaddr_reg:x1; val_offset:1398*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1398*FLEN/8, x2, x5, x6) + +inst_502: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x301 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x243 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x17c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7301; op2val:0xc243; +op3val:0x797c; valaddr_reg:x1; val_offset:1401*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1401*FLEN/8, x2, x5, x6) + +inst_503: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x301 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x243 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x17c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7301; op2val:0xc243; +op3val:0x797c; valaddr_reg:x1; val_offset:1404*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1404*FLEN/8, x2, x5, x6) + +inst_504: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x301 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x243 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x17c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7301; op2val:0xc243; +op3val:0x797c; valaddr_reg:x1; val_offset:1407*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1407*FLEN/8, x2, x5, x6) + +inst_505: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x10b and fs2 == 1 and fe2 == 0x0b and fm2 == 0x03f and fs3 == 0 and fe3 == 0x1a and fm3 == 0x15b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x790b; op2val:0xac3f; +op3val:0x695b; valaddr_reg:x1; val_offset:1410*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1410*FLEN/8, x2, x5, x6) + +inst_506: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x10b and fs2 == 1 and fe2 == 0x0b and fm2 == 0x03f and fs3 == 0 and fe3 == 0x1a and fm3 == 0x15b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x790b; op2val:0xac3f; +op3val:0x695b; valaddr_reg:x1; val_offset:1413*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1413*FLEN/8, x2, x5, x6) + +inst_507: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x10b and fs2 == 1 and fe2 == 0x0b and fm2 == 0x03f and fs3 == 0 and fe3 == 0x1a and fm3 == 0x15b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x790b; op2val:0xac3f; +op3val:0x695b; valaddr_reg:x1; val_offset:1416*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1416*FLEN/8, x2, x5, x6) + +inst_508: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x10b and fs2 == 1 and fe2 == 0x0b and fm2 == 0x03f and fs3 == 0 and fe3 == 0x1a and fm3 == 0x15b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x790b; op2val:0xac3f; +op3val:0x695b; valaddr_reg:x1; val_offset:1419*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1419*FLEN/8, x2, x5, x6) + +inst_509: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x10b and fs2 == 1 and fe2 == 0x0b and fm2 == 0x03f and fs3 == 0 and fe3 == 0x1a and fm3 == 0x15b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x790b; op2val:0xac3f; +op3val:0x695b; valaddr_reg:x1; val_offset:1422*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1422*FLEN/8, x2, x5, x6) + +inst_510: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x38a and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3ad and fs3 == 0 and fe3 == 0x1c and fm3 == 0x33c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x778a; op2val:0xb7ad; +op3val:0x733c; valaddr_reg:x1; val_offset:1425*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1425*FLEN/8, x2, x5, x6) + +inst_511: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x38a and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3ad and fs3 == 0 and fe3 == 0x1c and fm3 == 0x33c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x778a; op2val:0xb7ad; +op3val:0x733c; valaddr_reg:x1; val_offset:1428*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1428*FLEN/8, x2, x5, x6) + +inst_512: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x38a and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3ad and fs3 == 0 and fe3 == 0x1c and fm3 == 0x33c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x778a; op2val:0xb7ad; +op3val:0x733c; valaddr_reg:x1; val_offset:1431*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1431*FLEN/8, x2, x5, x6) + +inst_513: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x38a and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3ad and fs3 == 0 and fe3 == 0x1c and fm3 == 0x33c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x778a; op2val:0xb7ad; +op3val:0x733c; valaddr_reg:x1; val_offset:1434*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1434*FLEN/8, x2, x5, x6) + +inst_514: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x38a and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3ad and fs3 == 0 and fe3 == 0x1c and fm3 == 0x33c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x778a; op2val:0xb7ad; +op3val:0x733c; valaddr_reg:x1; val_offset:1437*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1437*FLEN/8, x2, x5, x6) + +inst_515: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x2ed and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ee and fs3 == 0 and fe3 == 0x1c and fm3 == 0x045 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6aed; op2val:0xc0ee; +op3val:0x7045; valaddr_reg:x1; val_offset:1440*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1440*FLEN/8, x2, x5, x6) + +inst_516: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x2ed and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ee and fs3 == 0 and fe3 == 0x1c and fm3 == 0x045 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6aed; op2val:0xc0ee; +op3val:0x7045; valaddr_reg:x1; val_offset:1443*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1443*FLEN/8, x2, x5, x6) + +inst_517: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x2ed and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ee and fs3 == 0 and fe3 == 0x1c and fm3 == 0x045 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6aed; op2val:0xc0ee; +op3val:0x7045; valaddr_reg:x1; val_offset:1446*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1446*FLEN/8, x2, x5, x6) + +inst_518: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x2ed and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ee and fs3 == 0 and fe3 == 0x1c and fm3 == 0x045 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6aed; op2val:0xc0ee; +op3val:0x7045; valaddr_reg:x1; val_offset:1449*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1449*FLEN/8, x2, x5, x6) + +inst_519: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x2ed and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ee and fs3 == 0 and fe3 == 0x1c and fm3 == 0x045 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6aed; op2val:0xc0ee; +op3val:0x7045; valaddr_reg:x1; val_offset:1452*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1452*FLEN/8, x2, x5, x6) + +inst_520: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x113 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x093 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x1ce and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7513; op2val:0xb893; +op3val:0x71ce; valaddr_reg:x1; val_offset:1455*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1455*FLEN/8, x2, x5, x6) + +inst_521: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x113 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x093 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x1ce and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7513; op2val:0xb893; +op3val:0x71ce; valaddr_reg:x1; val_offset:1458*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1458*FLEN/8, x2, x5, x6) + +inst_522: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x113 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x093 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x1ce and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7513; op2val:0xb893; +op3val:0x71ce; valaddr_reg:x1; val_offset:1461*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1461*FLEN/8, x2, x5, x6) + +inst_523: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x113 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x093 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x1ce and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7513; op2val:0xb893; +op3val:0x71ce; valaddr_reg:x1; val_offset:1464*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1464*FLEN/8, x2, x5, x6) + +inst_524: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x113 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x093 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x1ce and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7513; op2val:0xb893; +op3val:0x71ce; valaddr_reg:x1; val_offset:1467*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1467*FLEN/8, x2, x5, x6) + +inst_525: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x22f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x1e7 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x090 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x722f; op2val:0xb1e7; +op3val:0x6890; valaddr_reg:x1; val_offset:1470*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1470*FLEN/8, x2, x5, x6) + +inst_526: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x22f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x1e7 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x090 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x722f; op2val:0xb1e7; +op3val:0x6890; valaddr_reg:x1; val_offset:1473*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1473*FLEN/8, x2, x5, x6) + +inst_527: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x22f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x1e7 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x090 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x722f; op2val:0xb1e7; +op3val:0x6890; valaddr_reg:x1; val_offset:1476*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1476*FLEN/8, x2, x5, x6) + +inst_528: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x22f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x1e7 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x090 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x722f; op2val:0xb1e7; +op3val:0x6890; valaddr_reg:x1; val_offset:1479*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1479*FLEN/8, x2, x5, x6) + +inst_529: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x22f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x1e7 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x090 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x722f; op2val:0xb1e7; +op3val:0x6890; valaddr_reg:x1; val_offset:1482*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1482*FLEN/8, x2, x5, x6) + +inst_530: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x371 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x289 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x214 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7771; op2val:0xba89; +op3val:0x7614; valaddr_reg:x1; val_offset:1485*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1485*FLEN/8, x2, x5, x6) + +inst_531: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x371 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x289 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x214 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7771; op2val:0xba89; +op3val:0x7614; valaddr_reg:x1; val_offset:1488*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1488*FLEN/8, x2, x5, x6) + +inst_532: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x371 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x289 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x214 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7771; op2val:0xba89; +op3val:0x7614; valaddr_reg:x1; val_offset:1491*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1491*FLEN/8, x2, x5, x6) + +inst_533: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x371 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x289 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x214 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7771; op2val:0xba89; +op3val:0x7614; valaddr_reg:x1; val_offset:1494*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1494*FLEN/8, x2, x5, x6) + +inst_534: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x371 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x289 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x214 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7771; op2val:0xba89; +op3val:0x7614; valaddr_reg:x1; val_offset:1497*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1497*FLEN/8, x2, x5, x6) + +inst_535: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0b8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e4; op2val:0xbbb7; +op3val:0x78b8; valaddr_reg:x1; val_offset:1500*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1500*FLEN/8, x2, x5, x6) + +inst_536: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0b8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e4; op2val:0xbbb7; +op3val:0x78b8; valaddr_reg:x1; val_offset:1503*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1503*FLEN/8, x2, x5, x6) + +inst_537: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0b8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e4; op2val:0xbbb7; +op3val:0x78b8; valaddr_reg:x1; val_offset:1506*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1506*FLEN/8, x2, x5, x6) + +inst_538: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0b8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e4; op2val:0xbbb7; +op3val:0x78b8; valaddr_reg:x1; val_offset:1509*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1509*FLEN/8, x2, x5, x6) + +inst_539: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0b8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e4; op2val:0xbbb7; +op3val:0x78b8; valaddr_reg:x1; val_offset:1512*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1512*FLEN/8, x2, x5, x6) +RVTEST_SIGBASE(x5,signature_x5_4) + +inst_540: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x398 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x338 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x739b; op2val:0xc398; +op3val:0x7b38; valaddr_reg:x1; val_offset:1515*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1515*FLEN/8, x2, x5, x6) + +inst_541: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x398 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x338 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x739b; op2val:0xc398; +op3val:0x7b38; valaddr_reg:x1; val_offset:1518*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1518*FLEN/8, x2, x5, x6) + +inst_542: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x398 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x338 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x739b; op2val:0xc398; +op3val:0x7b38; valaddr_reg:x1; val_offset:1521*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1521*FLEN/8, x2, x5, x6) + +inst_543: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x398 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x338 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x739b; op2val:0xc398; +op3val:0x7b38; valaddr_reg:x1; val_offset:1524*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1524*FLEN/8, x2, x5, x6) + +inst_544: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x398 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x338 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x739b; op2val:0xc398; +op3val:0x7b38; valaddr_reg:x1; val_offset:1527*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1527*FLEN/8, x2, x5, x6) + +inst_545: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x188 and fs2 == 1 and fe2 == 0x18 and fm2 == 0x0af and fs3 == 0 and fe3 == 0x1d and fm3 == 0x27b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5188; op2val:0xe0af; +op3val:0x767b; valaddr_reg:x1; val_offset:1530*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1530*FLEN/8, x2, x5, x6) + +inst_546: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x188 and fs2 == 1 and fe2 == 0x18 and fm2 == 0x0af and fs3 == 0 and fe3 == 0x1d and fm3 == 0x27b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5188; op2val:0xe0af; +op3val:0x767b; valaddr_reg:x1; val_offset:1533*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1533*FLEN/8, x2, x5, x6) + +inst_547: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x188 and fs2 == 1 and fe2 == 0x18 and fm2 == 0x0af and fs3 == 0 and fe3 == 0x1d and fm3 == 0x27b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5188; op2val:0xe0af; +op3val:0x767b; valaddr_reg:x1; val_offset:1536*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1536*FLEN/8, x2, x5, x6) + +inst_548: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x188 and fs2 == 1 and fe2 == 0x18 and fm2 == 0x0af and fs3 == 0 and fe3 == 0x1d and fm3 == 0x27b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5188; op2val:0xe0af; +op3val:0x767b; valaddr_reg:x1; val_offset:1539*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1539*FLEN/8, x2, x5, x6) + +inst_549: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x188 and fs2 == 1 and fe2 == 0x18 and fm2 == 0x0af and fs3 == 0 and fe3 == 0x1d and fm3 == 0x27b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5188; op2val:0xe0af; +op3val:0x767b; valaddr_reg:x1; val_offset:1542*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1542*FLEN/8, x2, x5, x6) + +inst_550: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x074 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1e3 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x28e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7474; op2val:0xbde3; +op3val:0x768e; valaddr_reg:x1; val_offset:1545*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1545*FLEN/8, x2, x5, x6) + +inst_551: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x074 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1e3 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x28e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7474; op2val:0xbde3; +op3val:0x768e; valaddr_reg:x1; val_offset:1548*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1548*FLEN/8, x2, x5, x6) + +inst_552: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x074 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1e3 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x28e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7474; op2val:0xbde3; +op3val:0x768e; valaddr_reg:x1; val_offset:1551*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1551*FLEN/8, x2, x5, x6) + +inst_553: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x074 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1e3 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x28e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7474; op2val:0xbde3; +op3val:0x768e; valaddr_reg:x1; val_offset:1554*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1554*FLEN/8, x2, x5, x6) + +inst_554: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x074 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1e3 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x28e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7474; op2val:0xbde3; +op3val:0x768e; valaddr_reg:x1; val_offset:1557*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1557*FLEN/8, x2, x5, x6) + +inst_555: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x35c and fs2 == 1 and fe2 == 0x11 and fm2 == 0x339 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f5c; op2val:0xc739; +op3val:0x7aa5; valaddr_reg:x1; val_offset:1560*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1560*FLEN/8, x2, x5, x6) + +inst_556: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x35c and fs2 == 1 and fe2 == 0x11 and fm2 == 0x339 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f5c; op2val:0xc739; +op3val:0x7aa5; valaddr_reg:x1; val_offset:1563*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1563*FLEN/8, x2, x5, x6) + +inst_557: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x35c and fs2 == 1 and fe2 == 0x11 and fm2 == 0x339 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f5c; op2val:0xc739; +op3val:0x7aa5; valaddr_reg:x1; val_offset:1566*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1566*FLEN/8, x2, x5, x6) + +inst_558: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x35c and fs2 == 1 and fe2 == 0x11 and fm2 == 0x339 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f5c; op2val:0xc739; +op3val:0x7aa5; valaddr_reg:x1; val_offset:1569*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1569*FLEN/8, x2, x5, x6) + +inst_559: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x35c and fs2 == 1 and fe2 == 0x11 and fm2 == 0x339 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f5c; op2val:0xc739; +op3val:0x7aa5; valaddr_reg:x1; val_offset:1572*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1572*FLEN/8, x2, x5, x6) + +inst_560: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1fa and fs2 == 1 and fe2 == 0x0b and fm2 == 0x22c and fs3 == 0 and fe3 == 0x1a and fm3 == 0x09d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75fa; op2val:0xae2c; +op3val:0x689d; valaddr_reg:x1; val_offset:1575*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1575*FLEN/8, x2, x5, x6) + +inst_561: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1fa and fs2 == 1 and fe2 == 0x0b and fm2 == 0x22c and fs3 == 0 and fe3 == 0x1a and fm3 == 0x09d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75fa; op2val:0xae2c; +op3val:0x689d; valaddr_reg:x1; val_offset:1578*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1578*FLEN/8, x2, x5, x6) + +inst_562: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1fa and fs2 == 1 and fe2 == 0x0b and fm2 == 0x22c and fs3 == 0 and fe3 == 0x1a and fm3 == 0x09d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75fa; op2val:0xae2c; +op3val:0x689d; valaddr_reg:x1; val_offset:1581*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1581*FLEN/8, x2, x5, x6) + +inst_563: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1fa and fs2 == 1 and fe2 == 0x0b and fm2 == 0x22c and fs3 == 0 and fe3 == 0x1a and fm3 == 0x09d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75fa; op2val:0xae2c; +op3val:0x689d; valaddr_reg:x1; val_offset:1584*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1584*FLEN/8, x2, x5, x6) + +inst_564: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1fa and fs2 == 1 and fe2 == 0x0b and fm2 == 0x22c and fs3 == 0 and fe3 == 0x1a and fm3 == 0x09d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75fa; op2val:0xae2c; +op3val:0x689d; valaddr_reg:x1; val_offset:1587*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1587*FLEN/8, x2, x5, x6) + +inst_565: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e7 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0f2 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x211 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e7; op2val:0xb0f2; +op3val:0x6e11; valaddr_reg:x1; val_offset:1590*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1590*FLEN/8, x2, x5, x6) + +inst_566: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e7 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0f2 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x211 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e7; op2val:0xb0f2; +op3val:0x6e11; valaddr_reg:x1; val_offset:1593*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1593*FLEN/8, x2, x5, x6) + +inst_567: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e7 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0f2 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x211 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e7; op2val:0xb0f2; +op3val:0x6e11; valaddr_reg:x1; val_offset:1596*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1596*FLEN/8, x2, x5, x6) + +inst_568: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e7 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0f2 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x211 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e7; op2val:0xb0f2; +op3val:0x6e11; valaddr_reg:x1; val_offset:1599*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1599*FLEN/8, x2, x5, x6) + +inst_569: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e7 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0f2 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x211 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e7; op2val:0xb0f2; +op3val:0x6e11; valaddr_reg:x1; val_offset:1602*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1602*FLEN/8, x2, x5, x6) + +inst_570: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x05c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0fa and fs3 == 0 and fe3 == 0x1d and fm3 == 0x16d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x785c; op2val:0xb8fa; +op3val:0x756d; valaddr_reg:x1; val_offset:1605*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1605*FLEN/8, x2, x5, x6) + +inst_571: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x05c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0fa and fs3 == 0 and fe3 == 0x1d and fm3 == 0x16d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x785c; op2val:0xb8fa; +op3val:0x756d; valaddr_reg:x1; val_offset:1608*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1608*FLEN/8, x2, x5, x6) + +inst_572: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x05c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0fa and fs3 == 0 and fe3 == 0x1d and fm3 == 0x16d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x785c; op2val:0xb8fa; +op3val:0x756d; valaddr_reg:x1; val_offset:1611*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1611*FLEN/8, x2, x5, x6) + +inst_573: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x05c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0fa and fs3 == 0 and fe3 == 0x1d and fm3 == 0x16d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x785c; op2val:0xb8fa; +op3val:0x756d; valaddr_reg:x1; val_offset:1614*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1614*FLEN/8, x2, x5, x6) + +inst_574: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x05c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0fa and fs3 == 0 and fe3 == 0x1d and fm3 == 0x16d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x785c; op2val:0xb8fa; +op3val:0x756d; valaddr_reg:x1; val_offset:1617*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1617*FLEN/8, x2, x5, x6) + +inst_575: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a5 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x299 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3a9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78a5; op2val:0xbe99; +op3val:0x7ba9; valaddr_reg:x1; val_offset:1620*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1620*FLEN/8, x2, x5, x6) + +inst_576: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a5 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x299 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3a9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78a5; op2val:0xbe99; +op3val:0x7ba9; valaddr_reg:x1; val_offset:1623*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1623*FLEN/8, x2, x5, x6) + +inst_577: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a5 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x299 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3a9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78a5; op2val:0xbe99; +op3val:0x7ba9; valaddr_reg:x1; val_offset:1626*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1626*FLEN/8, x2, x5, x6) + +inst_578: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a5 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x299 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3a9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78a5; op2val:0xbe99; +op3val:0x7ba9; valaddr_reg:x1; val_offset:1629*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1629*FLEN/8, x2, x5, x6) + +inst_579: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a5 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x299 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3a9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78a5; op2val:0xbe99; +op3val:0x7ba9; valaddr_reg:x1; val_offset:1632*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1632*FLEN/8, x2, x5, x6) + +inst_580: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x018 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2b3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8b; op2val:0xb818; +op3val:0x76b3; valaddr_reg:x1; val_offset:1635*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1635*FLEN/8, x2, x5, x6) + +inst_581: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x018 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2b3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8b; op2val:0xb818; +op3val:0x76b3; valaddr_reg:x1; val_offset:1638*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1638*FLEN/8, x2, x5, x6) + +inst_582: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x018 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2b3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8b; op2val:0xb818; +op3val:0x76b3; valaddr_reg:x1; val_offset:1641*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1641*FLEN/8, x2, x5, x6) + +inst_583: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x018 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2b3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8b; op2val:0xb818; +op3val:0x76b3; valaddr_reg:x1; val_offset:1644*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1644*FLEN/8, x2, x5, x6) + +inst_584: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x018 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2b3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8b; op2val:0xb818; +op3val:0x76b3; valaddr_reg:x1; val_offset:1647*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1647*FLEN/8, x2, x5, x6) + +inst_585: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x280 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x252 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x122 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a80; op2val:0xba52; +op3val:0x7922; valaddr_reg:x1; val_offset:1650*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1650*FLEN/8, x2, x5, x6) + +inst_586: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x280 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x252 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x122 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a80; op2val:0xba52; +op3val:0x7922; valaddr_reg:x1; val_offset:1653*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1653*FLEN/8, x2, x5, x6) + +inst_587: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x280 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x252 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x122 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a80; op2val:0xba52; +op3val:0x7922; valaddr_reg:x1; val_offset:1656*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1656*FLEN/8, x2, x5, x6) + +inst_588: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x280 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x252 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x122 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a80; op2val:0xba52; +op3val:0x7922; valaddr_reg:x1; val_offset:1659*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1659*FLEN/8, x2, x5, x6) + +inst_589: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x280 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x252 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x122 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a80; op2val:0xba52; +op3val:0x7922; valaddr_reg:x1; val_offset:1662*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1662*FLEN/8, x2, x5, x6) + +inst_590: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1e8 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x227 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x08b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75e8; op2val:0xb627; +op3val:0x708b; valaddr_reg:x1; val_offset:1665*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1665*FLEN/8, x2, x5, x6) + +inst_591: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1e8 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x227 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x08b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75e8; op2val:0xb627; +op3val:0x708b; valaddr_reg:x1; val_offset:1668*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1668*FLEN/8, x2, x5, x6) + +inst_592: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1e8 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x227 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x08b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75e8; op2val:0xb627; +op3val:0x708b; valaddr_reg:x1; val_offset:1671*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1671*FLEN/8, x2, x5, x6) + +inst_593: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1e8 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x227 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x08b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75e8; op2val:0xb627; +op3val:0x708b; valaddr_reg:x1; val_offset:1674*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1674*FLEN/8, x2, x5, x6) + +inst_594: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1e8 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x227 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x08b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75e8; op2val:0xb627; +op3val:0x708b; valaddr_reg:x1; val_offset:1677*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1677*FLEN/8, x2, x5, x6) + +inst_595: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x391 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x082 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78c3; op2val:0xbb91; +op3val:0x7882; valaddr_reg:x1; val_offset:1680*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1680*FLEN/8, x2, x5, x6) + +inst_596: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x391 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x082 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78c3; op2val:0xbb91; +op3val:0x7882; valaddr_reg:x1; val_offset:1683*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1683*FLEN/8, x2, x5, x6) + +inst_597: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x391 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x082 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78c3; op2val:0xbb91; +op3val:0x7882; valaddr_reg:x1; val_offset:1686*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1686*FLEN/8, x2, x5, x6) + +inst_598: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x391 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x082 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78c3; op2val:0xbb91; +op3val:0x7882; valaddr_reg:x1; val_offset:1689*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1689*FLEN/8, x2, x5, x6) + +inst_599: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x391 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x082 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78c3; op2val:0xbb91; +op3val:0x7882; valaddr_reg:x1; val_offset:1692*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1692*FLEN/8, x2, x5, x6) + +inst_600: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a7 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x00b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3bd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ba7; op2val:0xbc0b; +op3val:0x7bbd; valaddr_reg:x1; val_offset:1695*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1695*FLEN/8, x2, x5, x6) + +inst_601: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a7 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x00b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3bd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ba7; op2val:0xbc0b; +op3val:0x7bbd; valaddr_reg:x1; val_offset:1698*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1698*FLEN/8, x2, x5, x6) + +inst_602: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a7 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x00b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3bd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ba7; op2val:0xbc0b; +op3val:0x7bbd; valaddr_reg:x1; val_offset:1701*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1701*FLEN/8, x2, x5, x6) + +inst_603: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a7 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x00b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3bd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ba7; op2val:0xbc0b; +op3val:0x7bbd; valaddr_reg:x1; val_offset:1704*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1704*FLEN/8, x2, x5, x6) + +inst_604: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a7 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x00b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3bd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ba7; op2val:0xbc0b; +op3val:0x7bbd; valaddr_reg:x1; val_offset:1707*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1707*FLEN/8, x2, x5, x6) + +inst_605: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0dd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x09d and fs3 == 0 and fe3 == 0x1d and fm3 == 0x19d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78dd; op2val:0xb89d; +op3val:0x759d; valaddr_reg:x1; val_offset:1710*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1710*FLEN/8, x2, x5, x6) + +inst_606: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0dd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x09d and fs3 == 0 and fe3 == 0x1d and fm3 == 0x19d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78dd; op2val:0xb89d; +op3val:0x759d; valaddr_reg:x1; val_offset:1713*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1713*FLEN/8, x2, x5, x6) + +inst_607: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0dd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x09d and fs3 == 0 and fe3 == 0x1d and fm3 == 0x19d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78dd; op2val:0xb89d; +op3val:0x759d; valaddr_reg:x1; val_offset:1716*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1716*FLEN/8, x2, x5, x6) + +inst_608: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0dd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x09d and fs3 == 0 and fe3 == 0x1d and fm3 == 0x19d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78dd; op2val:0xb89d; +op3val:0x759d; valaddr_reg:x1; val_offset:1719*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1719*FLEN/8, x2, x5, x6) + +inst_609: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0dd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x09d and fs3 == 0 and fe3 == 0x1d and fm3 == 0x19d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78dd; op2val:0xb89d; +op3val:0x759d; valaddr_reg:x1; val_offset:1722*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1722*FLEN/8, x2, x5, x6) + +inst_610: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x324 and fs2 == 1 and fe2 == 0x05 and fm2 == 0x069 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x3e2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b24; op2val:0x9469; +op3val:0x53e2; valaddr_reg:x1; val_offset:1725*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1725*FLEN/8, x2, x5, x6) + +inst_611: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x324 and fs2 == 1 and fe2 == 0x05 and fm2 == 0x069 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x3e2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b24; op2val:0x9469; +op3val:0x53e2; valaddr_reg:x1; val_offset:1728*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1728*FLEN/8, x2, x5, x6) + +inst_612: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x324 and fs2 == 1 and fe2 == 0x05 and fm2 == 0x069 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x3e2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b24; op2val:0x9469; +op3val:0x53e2; valaddr_reg:x1; val_offset:1731*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1731*FLEN/8, x2, x5, x6) + +inst_613: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x324 and fs2 == 1 and fe2 == 0x05 and fm2 == 0x069 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x3e2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b24; op2val:0x9469; +op3val:0x53e2; valaddr_reg:x1; val_offset:1734*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1734*FLEN/8, x2, x5, x6) + +inst_614: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x324 and fs2 == 1 and fe2 == 0x05 and fm2 == 0x069 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x3e2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b24; op2val:0x9469; +op3val:0x53e2; valaddr_reg:x1; val_offset:1737*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1737*FLEN/8, x2, x5, x6) + +inst_615: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2e7 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x13e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x086 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ee7; op2val:0xc53e; +op3val:0x7886; valaddr_reg:x1; val_offset:1740*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1740*FLEN/8, x2, x5, x6) + +inst_616: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2e7 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x13e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x086 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ee7; op2val:0xc53e; +op3val:0x7886; valaddr_reg:x1; val_offset:1743*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1743*FLEN/8, x2, x5, x6) + +inst_617: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2e7 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x13e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x086 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ee7; op2val:0xc53e; +op3val:0x7886; valaddr_reg:x1; val_offset:1746*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1746*FLEN/8, x2, x5, x6) + +inst_618: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2e7 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x13e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x086 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ee7; op2val:0xc53e; +op3val:0x7886; valaddr_reg:x1; val_offset:1749*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1749*FLEN/8, x2, x5, x6) + +inst_619: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2e7 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x13e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x086 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ee7; op2val:0xc53e; +op3val:0x7886; valaddr_reg:x1; val_offset:1752*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1752*FLEN/8, x2, x5, x6) + +inst_620: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0eb and fs2 == 1 and fe2 == 0x0c and fm2 == 0x351 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x080 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78eb; op2val:0xb351; +op3val:0x7080; valaddr_reg:x1; val_offset:1755*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1755*FLEN/8, x2, x5, x6) + +inst_621: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0eb and fs2 == 1 and fe2 == 0x0c and fm2 == 0x351 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x080 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78eb; op2val:0xb351; +op3val:0x7080; valaddr_reg:x1; val_offset:1758*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1758*FLEN/8, x2, x5, x6) + +inst_622: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0eb and fs2 == 1 and fe2 == 0x0c and fm2 == 0x351 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x080 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78eb; op2val:0xb351; +op3val:0x7080; valaddr_reg:x1; val_offset:1761*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1761*FLEN/8, x2, x5, x6) + +inst_623: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0eb and fs2 == 1 and fe2 == 0x0c and fm2 == 0x351 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x080 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78eb; op2val:0xb351; +op3val:0x7080; valaddr_reg:x1; val_offset:1764*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1764*FLEN/8, x2, x5, x6) + +inst_624: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0eb and fs2 == 1 and fe2 == 0x0c and fm2 == 0x351 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x080 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78eb; op2val:0xb351; +op3val:0x7080; valaddr_reg:x1; val_offset:1767*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1767*FLEN/8, x2, x5, x6) + +inst_625: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x108 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1a9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x320 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7908; op2val:0xbda9; +op3val:0x7b20; valaddr_reg:x1; val_offset:1770*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1770*FLEN/8, x2, x5, x6) + +inst_626: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x108 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1a9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x320 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7908; op2val:0xbda9; +op3val:0x7b20; valaddr_reg:x1; val_offset:1773*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1773*FLEN/8, x2, x5, x6) + +inst_627: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x108 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1a9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x320 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7908; op2val:0xbda9; +op3val:0x7b20; valaddr_reg:x1; val_offset:1776*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1776*FLEN/8, x2, x5, x6) + +inst_628: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x108 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1a9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x320 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7908; op2val:0xbda9; +op3val:0x7b20; valaddr_reg:x1; val_offset:1779*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1779*FLEN/8, x2, x5, x6) + +inst_629: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x108 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1a9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x320 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7908; op2val:0xbda9; +op3val:0x7b20; valaddr_reg:x1; val_offset:1782*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1782*FLEN/8, x2, x5, x6) + +inst_630: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x202 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x098 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2e7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7602; op2val:0xbc98; +op3val:0x76e7; valaddr_reg:x1; val_offset:1785*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1785*FLEN/8, x2, x5, x6) + +inst_631: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x202 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x098 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2e7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7602; op2val:0xbc98; +op3val:0x76e7; valaddr_reg:x1; val_offset:1788*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1788*FLEN/8, x2, x5, x6) + +inst_632: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x202 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x098 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2e7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7602; op2val:0xbc98; +op3val:0x76e7; valaddr_reg:x1; val_offset:1791*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1791*FLEN/8, x2, x5, x6) + +inst_633: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x202 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x098 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2e7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7602; op2val:0xbc98; +op3val:0x76e7; valaddr_reg:x1; val_offset:1794*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1794*FLEN/8, x2, x5, x6) + +inst_634: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x202 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x098 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2e7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7602; op2val:0xbc98; +op3val:0x76e7; valaddr_reg:x1; val_offset:1797*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1797*FLEN/8, x2, x5, x6) + +inst_635: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x33d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x126 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x733d; op2val:0xbd26; +op3val:0x74a9; valaddr_reg:x1; val_offset:1800*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1800*FLEN/8, x2, x5, x6) + +inst_636: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x33d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x126 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x733d; op2val:0xbd26; +op3val:0x74a9; valaddr_reg:x1; val_offset:1803*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1803*FLEN/8, x2, x5, x6) + +inst_637: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x33d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x126 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x733d; op2val:0xbd26; +op3val:0x74a9; valaddr_reg:x1; val_offset:1806*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1806*FLEN/8, x2, x5, x6) + +inst_638: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x33d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x126 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x733d; op2val:0xbd26; +op3val:0x74a9; valaddr_reg:x1; val_offset:1809*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1809*FLEN/8, x2, x5, x6) + +inst_639: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x33d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x126 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x733d; op2val:0xbd26; +op3val:0x74a9; valaddr_reg:x1; val_offset:1812*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1812*FLEN/8, x2, x5, x6) + +inst_640: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c6 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x23f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x212 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bc6; op2val:0xb63f; +op3val:0x7612; valaddr_reg:x1; val_offset:1815*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1815*FLEN/8, x2, x5, x6) + +inst_641: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c6 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x23f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x212 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bc6; op2val:0xb63f; +op3val:0x7612; valaddr_reg:x1; val_offset:1818*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1818*FLEN/8, x2, x5, x6) + +inst_642: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c6 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x23f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x212 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bc6; op2val:0xb63f; +op3val:0x7612; valaddr_reg:x1; val_offset:1821*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1821*FLEN/8, x2, x5, x6) + +inst_643: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c6 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x23f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x212 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bc6; op2val:0xb63f; +op3val:0x7612; valaddr_reg:x1; val_offset:1824*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1824*FLEN/8, x2, x5, x6) + +inst_644: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c6 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x23f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x212 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bc6; op2val:0xb63f; +op3val:0x7612; valaddr_reg:x1; val_offset:1827*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1827*FLEN/8, x2, x5, x6) + +inst_645: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3af and fs2 == 1 and fe2 == 0x0e and fm2 == 0x39b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x34e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7baf; op2val:0xbb9b; +op3val:0x7b4e; valaddr_reg:x1; val_offset:1830*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1830*FLEN/8, x2, x5, x6) + +inst_646: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3af and fs2 == 1 and fe2 == 0x0e and fm2 == 0x39b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x34e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7baf; op2val:0xbb9b; +op3val:0x7b4e; valaddr_reg:x1; val_offset:1833*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1833*FLEN/8, x2, x5, x6) + +inst_647: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3af and fs2 == 1 and fe2 == 0x0e and fm2 == 0x39b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x34e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7baf; op2val:0xbb9b; +op3val:0x7b4e; valaddr_reg:x1; val_offset:1836*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1836*FLEN/8, x2, x5, x6) + +inst_648: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3af and fs2 == 1 and fe2 == 0x0e and fm2 == 0x39b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x34e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7baf; op2val:0xbb9b; +op3val:0x7b4e; valaddr_reg:x1; val_offset:1839*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1839*FLEN/8, x2, x5, x6) + +inst_649: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3af and fs2 == 1 and fe2 == 0x0e and fm2 == 0x39b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x34e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7baf; op2val:0xbb9b; +op3val:0x7b4e; valaddr_reg:x1; val_offset:1842*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1842*FLEN/8, x2, x5, x6) + +inst_650: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c3 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2fa and fs3 == 0 and fe3 == 0x1d and fm3 == 0x027 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78c3; op2val:0xb6fa; +op3val:0x7427; valaddr_reg:x1; val_offset:1845*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1845*FLEN/8, x2, x5, x6) + +inst_651: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c3 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2fa and fs3 == 0 and fe3 == 0x1d and fm3 == 0x027 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78c3; op2val:0xb6fa; +op3val:0x7427; valaddr_reg:x1; val_offset:1848*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1848*FLEN/8, x2, x5, x6) + +inst_652: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c3 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2fa and fs3 == 0 and fe3 == 0x1d and fm3 == 0x027 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78c3; op2val:0xb6fa; +op3val:0x7427; valaddr_reg:x1; val_offset:1851*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1851*FLEN/8, x2, x5, x6) + +inst_653: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c3 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2fa and fs3 == 0 and fe3 == 0x1d and fm3 == 0x027 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78c3; op2val:0xb6fa; +op3val:0x7427; valaddr_reg:x1; val_offset:1854*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1854*FLEN/8, x2, x5, x6) + +inst_654: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c3 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2fa and fs3 == 0 and fe3 == 0x1d and fm3 == 0x027 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78c3; op2val:0xb6fa; +op3val:0x7427; valaddr_reg:x1; val_offset:1857*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1857*FLEN/8, x2, x5, x6) + +inst_655: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x00c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3ef and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd8; op2val:0xb80c; +op3val:0x77ef; valaddr_reg:x1; val_offset:1860*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1860*FLEN/8, x2, x5, x6) + +inst_656: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x00c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3ef and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd8; op2val:0xb80c; +op3val:0x77ef; valaddr_reg:x1; val_offset:1863*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1863*FLEN/8, x2, x5, x6) + +inst_657: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x00c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3ef and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd8; op2val:0xb80c; +op3val:0x77ef; valaddr_reg:x1; val_offset:1866*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1866*FLEN/8, x2, x5, x6) + +inst_658: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x00c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3ef and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd8; op2val:0xb80c; +op3val:0x77ef; valaddr_reg:x1; val_offset:1869*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1869*FLEN/8, x2, x5, x6) + +inst_659: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x00c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3ef and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd8; op2val:0xb80c; +op3val:0x77ef; valaddr_reg:x1; val_offset:1872*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1872*FLEN/8, x2, x5, x6) + +inst_660: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x225 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x11a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76a5; op2val:0xba25; +op3val:0x751a; valaddr_reg:x1; val_offset:1875*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1875*FLEN/8, x2, x5, x6) + +inst_661: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x225 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x11a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76a5; op2val:0xba25; +op3val:0x751a; valaddr_reg:x1; val_offset:1878*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1878*FLEN/8, x2, x5, x6) + +inst_662: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x225 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x11a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76a5; op2val:0xba25; +op3val:0x751a; valaddr_reg:x1; val_offset:1881*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1881*FLEN/8, x2, x5, x6) + +inst_663: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x225 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x11a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76a5; op2val:0xba25; +op3val:0x751a; valaddr_reg:x1; val_offset:1884*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1884*FLEN/8, x2, x5, x6) + +inst_664: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x225 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x11a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76a5; op2val:0xba25; +op3val:0x751a; valaddr_reg:x1; val_offset:1887*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1887*FLEN/8, x2, x5, x6) + +inst_665: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3de and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3dd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bde; op2val:0xb7fe; +op3val:0x77dd; valaddr_reg:x1; val_offset:1890*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1890*FLEN/8, x2, x5, x6) + +inst_666: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3de and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3dd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bde; op2val:0xb7fe; +op3val:0x77dd; valaddr_reg:x1; val_offset:1893*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1893*FLEN/8, x2, x5, x6) + +inst_667: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3de and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3dd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bde; op2val:0xb7fe; +op3val:0x77dd; valaddr_reg:x1; val_offset:1896*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1896*FLEN/8, x2, x5, x6) +RVTEST_SIGBASE(x5,signature_x5_5) + +inst_668: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3de and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3dd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bde; op2val:0xb7fe; +op3val:0x77dd; valaddr_reg:x1; val_offset:1899*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1899*FLEN/8, x2, x5, x6) + +inst_669: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3de and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3dd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bde; op2val:0xb7fe; +op3val:0x77dd; valaddr_reg:x1; val_offset:1902*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1902*FLEN/8, x2, x5, x6) + +inst_670: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x094 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2a9 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3a0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7494; op2val:0xbea9; +op3val:0x77a0; valaddr_reg:x1; val_offset:1905*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1905*FLEN/8, x2, x5, x6) + +inst_671: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x094 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2a9 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3a0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7494; op2val:0xbea9; +op3val:0x77a0; valaddr_reg:x1; val_offset:1908*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1908*FLEN/8, x2, x5, x6) + +inst_672: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x094 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2a9 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3a0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7494; op2val:0xbea9; +op3val:0x77a0; valaddr_reg:x1; val_offset:1911*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1911*FLEN/8, x2, x5, x6) + +inst_673: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x094 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2a9 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3a0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7494; op2val:0xbea9; +op3val:0x77a0; valaddr_reg:x1; val_offset:1914*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1914*FLEN/8, x2, x5, x6) + +inst_674: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x094 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2a9 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3a0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7494; op2val:0xbea9; +op3val:0x77a0; valaddr_reg:x1; val_offset:1917*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1917*FLEN/8, x2, x5, x6) + +inst_675: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3cc and fs2 == 1 and fe2 == 0x11 and fm2 == 0x119 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6fcc; op2val:0xc519; +op3val:0x78f8; valaddr_reg:x1; val_offset:1920*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1920*FLEN/8, x2, x5, x6) + +inst_676: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3cc and fs2 == 1 and fe2 == 0x11 and fm2 == 0x119 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0f8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6fcc; op2val:0xc519; +op3val:0x78f8; valaddr_reg:x1; val_offset:1923*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1923*FLEN/8, x2, x5, x6) + +inst_677: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3cc and fs2 == 1 and fe2 == 0x11 and fm2 == 0x119 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0f8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6fcc; op2val:0xc519; +op3val:0x78f8; valaddr_reg:x1; val_offset:1926*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1926*FLEN/8, x2, x5, x6) + +inst_678: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3cc and fs2 == 1 and fe2 == 0x11 and fm2 == 0x119 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0f8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6fcc; op2val:0xc519; +op3val:0x78f8; valaddr_reg:x1; val_offset:1929*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1929*FLEN/8, x2, x5, x6) + +inst_679: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3cc and fs2 == 1 and fe2 == 0x11 and fm2 == 0x119 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0f8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6fcc; op2val:0xc519; +op3val:0x78f8; valaddr_reg:x1; val_offset:1932*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1932*FLEN/8, x2, x5, x6) + +inst_680: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x317 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x149 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0b0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7717; op2val:0xb949; +op3val:0x74b0; valaddr_reg:x1; val_offset:1935*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1935*FLEN/8, x2, x5, x6) + +inst_681: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x317 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x149 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0b0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7717; op2val:0xb949; +op3val:0x74b0; valaddr_reg:x1; val_offset:1938*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1938*FLEN/8, x2, x5, x6) + +inst_682: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x317 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x149 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0b0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7717; op2val:0xb949; +op3val:0x74b0; valaddr_reg:x1; val_offset:1941*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1941*FLEN/8, x2, x5, x6) + +inst_683: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x317 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x149 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0b0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7717; op2val:0xb949; +op3val:0x74b0; valaddr_reg:x1; val_offset:1944*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1944*FLEN/8, x2, x5, x6) + +inst_684: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x317 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x149 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0b0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7717; op2val:0xb949; +op3val:0x74b0; valaddr_reg:x1; val_offset:1947*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1947*FLEN/8, x2, x5, x6) + +inst_685: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x240 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x03b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x29c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a40; op2val:0xbc3b; +op3val:0x7a9c; valaddr_reg:x1; val_offset:1950*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1950*FLEN/8, x2, x5, x6) + +inst_686: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x240 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x03b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x29c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a40; op2val:0xbc3b; +op3val:0x7a9c; valaddr_reg:x1; val_offset:1953*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1953*FLEN/8, x2, x5, x6) + +inst_687: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x240 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x03b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x29c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a40; op2val:0xbc3b; +op3val:0x7a9c; valaddr_reg:x1; val_offset:1956*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1956*FLEN/8, x2, x5, x6) + +inst_688: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x240 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x03b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x29c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a40; op2val:0xbc3b; +op3val:0x7a9c; valaddr_reg:x1; val_offset:1959*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1959*FLEN/8, x2, x5, x6) + +inst_689: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x240 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x03b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x29c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a40; op2val:0xbc3b; +op3val:0x7a9c; valaddr_reg:x1; val_offset:1962*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1962*FLEN/8, x2, x5, x6) + +inst_690: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x2c3 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x109 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x042 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x62c3; op2val:0xd109; +op3val:0x7842; valaddr_reg:x1; val_offset:1965*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1965*FLEN/8, x2, x5, x6) + +inst_691: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x2c3 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x109 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x042 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x62c3; op2val:0xd109; +op3val:0x7842; valaddr_reg:x1; val_offset:1968*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1968*FLEN/8, x2, x5, x6) + +inst_692: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x2c3 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x109 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x042 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x62c3; op2val:0xd109; +op3val:0x7842; valaddr_reg:x1; val_offset:1971*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1971*FLEN/8, x2, x5, x6) + +inst_693: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x2c3 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x109 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x042 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x62c3; op2val:0xd109; +op3val:0x7842; valaddr_reg:x1; val_offset:1974*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1974*FLEN/8, x2, x5, x6) + +inst_694: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x2c3 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x109 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x042 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x62c3; op2val:0xd109; +op3val:0x7842; valaddr_reg:x1; val_offset:1977*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1977*FLEN/8, x2, x5, x6) + +inst_695: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x060 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2d4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x37a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7460; op2val:0xc2d4; +op3val:0x7b7a; valaddr_reg:x1; val_offset:1980*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1980*FLEN/8, x2, x5, x6) + +inst_696: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x060 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2d4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x37a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7460; op2val:0xc2d4; +op3val:0x7b7a; valaddr_reg:x1; val_offset:1983*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1983*FLEN/8, x2, x5, x6) + +inst_697: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x060 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2d4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x37a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7460; op2val:0xc2d4; +op3val:0x7b7a; valaddr_reg:x1; val_offset:1986*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1986*FLEN/8, x2, x5, x6) + +inst_698: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x060 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2d4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x37a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7460; op2val:0xc2d4; +op3val:0x7b7a; valaddr_reg:x1; val_offset:1989*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1989*FLEN/8, x2, x5, x6) + +inst_699: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x060 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2d4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x37a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7460; op2val:0xc2d4; +op3val:0x7b7a; valaddr_reg:x1; val_offset:1992*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1992*FLEN/8, x2, x5, x6) + +inst_700: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x240 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x106 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3db and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a40; op2val:0xb506; +op3val:0x73db; valaddr_reg:x1; val_offset:1995*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1995*FLEN/8, x2, x5, x6) + +inst_701: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x240 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x106 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3db and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a40; op2val:0xb506; +op3val:0x73db; valaddr_reg:x1; val_offset:1998*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1998*FLEN/8, x2, x5, x6) + +inst_702: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x240 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x106 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3db and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a40; op2val:0xb506; +op3val:0x73db; valaddr_reg:x1; val_offset:2001*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2001*FLEN/8, x2, x5, x6) + +inst_703: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x240 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x106 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3db and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a40; op2val:0xb506; +op3val:0x73db; valaddr_reg:x1; val_offset:2004*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2004*FLEN/8, x2, x5, x6) + +inst_704: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x240 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x106 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3db and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a40; op2val:0xb506; +op3val:0x73db; valaddr_reg:x1; val_offset:2007*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2007*FLEN/8, x2, x5, x6) + +inst_705: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x047 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0a0 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0f3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7447; op2val:0xb8a0; +op3val:0x70f3; valaddr_reg:x1; val_offset:2010*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2010*FLEN/8, x2, x5, x6) + +inst_706: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x047 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0a0 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0f3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7447; op2val:0xb8a0; +op3val:0x70f3; valaddr_reg:x1; val_offset:2013*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2013*FLEN/8, x2, x5, x6) + +inst_707: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x047 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0a0 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0f3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7447; op2val:0xb8a0; +op3val:0x70f3; valaddr_reg:x1; val_offset:2016*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2016*FLEN/8, x2, x5, x6) + +inst_708: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x047 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0a0 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0f3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7447; op2val:0xb8a0; +op3val:0x70f3; valaddr_reg:x1; val_offset:2019*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2019*FLEN/8, x2, x5, x6) + +inst_709: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x047 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0a0 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0f3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7447; op2val:0xb8a0; +op3val:0x70f3; valaddr_reg:x1; val_offset:2022*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2022*FLEN/8, x2, x5, x6) + +inst_710: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e8 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0be and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0b0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7be8; op2val:0xb4be; +op3val:0x74b0; valaddr_reg:x1; val_offset:2025*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2025*FLEN/8, x2, x5, x6) + +inst_711: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e8 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0be and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0b0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7be8; op2val:0xb4be; +op3val:0x74b0; valaddr_reg:x1; val_offset:2028*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2028*FLEN/8, x2, x5, x6) + +inst_712: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e8 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0be and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0b0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7be8; op2val:0xb4be; +op3val:0x74b0; valaddr_reg:x1; val_offset:2031*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2031*FLEN/8, x2, x5, x6) + +inst_713: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e8 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0be and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0b0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7be8; op2val:0xb4be; +op3val:0x74b0; valaddr_reg:x1; val_offset:2034*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2034*FLEN/8, x2, x5, x6) + +inst_714: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e8 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0be and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0b0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7be8; op2val:0xb4be; +op3val:0x74b0; valaddr_reg:x1; val_offset:2037*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2037*FLEN/8, x2, x5, x6) + +inst_715: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0dc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x23e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x397 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78dc; op2val:0xba3e; +op3val:0x7797; valaddr_reg:x1; val_offset:2040*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2040*FLEN/8, x2, x5, x6) + +inst_716: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0dc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x23e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x397 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78dc; op2val:0xba3e; +op3val:0x7797; valaddr_reg:x1; val_offset:2043*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2043*FLEN/8, x2, x5, x6) + +inst_717: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0dc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x23e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x397 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78dc; op2val:0xba3e; +op3val:0x7797; valaddr_reg:x1; val_offset:2046*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2046*FLEN/8, x2, x5, x6) + +inst_718: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0dc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x23e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x397 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78dc; op2val:0xba3e; +op3val:0x7797; valaddr_reg:x1; val_offset:2049*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2049*FLEN/8, x2, x5, x6) + +inst_719: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0dc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x23e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x397 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78dc; op2val:0xba3e; +op3val:0x7797; valaddr_reg:x1; val_offset:2052*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2052*FLEN/8, x2, x5, x6) + +inst_720: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x128 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x37d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0d4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7928; op2val:0xbb7d; +op3val:0x78d4; valaddr_reg:x1; val_offset:2055*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2055*FLEN/8, x2, x5, x6) + +inst_721: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x128 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x37d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0d4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7928; op2val:0xbb7d; +op3val:0x78d4; valaddr_reg:x1; val_offset:2058*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2058*FLEN/8, x2, x5, x6) + +inst_722: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x128 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x37d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0d4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7928; op2val:0xbb7d; +op3val:0x78d4; valaddr_reg:x1; val_offset:2061*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2061*FLEN/8, x2, x5, x6) + +inst_723: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x128 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x37d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0d4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7928; op2val:0xbb7d; +op3val:0x78d4; valaddr_reg:x1; val_offset:2064*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2064*FLEN/8, x2, x5, x6) + +inst_724: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x128 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x37d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0d4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7928; op2val:0xbb7d; +op3val:0x78d4; valaddr_reg:x1; val_offset:2067*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2067*FLEN/8, x2, x5, x6) + +inst_725: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f1 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x116 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x38f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f1; op2val:0xb116; +op3val:0x6f8f; valaddr_reg:x1; val_offset:2070*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2070*FLEN/8, x2, x5, x6) + +inst_726: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f1 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x116 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x38f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f1; op2val:0xb116; +op3val:0x6f8f; valaddr_reg:x1; val_offset:2073*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2073*FLEN/8, x2, x5, x6) + +inst_727: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f1 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x116 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x38f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f1; op2val:0xb116; +op3val:0x6f8f; valaddr_reg:x1; val_offset:2076*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2076*FLEN/8, x2, x5, x6) + +inst_728: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f1 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x116 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x38f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f1; op2val:0xb116; +op3val:0x6f8f; valaddr_reg:x1; val_offset:2079*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2079*FLEN/8, x2, x5, x6) + +inst_729: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f1 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x116 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x38f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f1; op2val:0xb116; +op3val:0x6f8f; valaddr_reg:x1; val_offset:2082*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2082*FLEN/8, x2, x5, x6) + +inst_730: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x214 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x253 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0cf and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a14; op2val:0xb653; +op3val:0x74cf; valaddr_reg:x1; val_offset:2085*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2085*FLEN/8, x2, x5, x6) + +inst_731: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x214 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x253 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0cf and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a14; op2val:0xb653; +op3val:0x74cf; valaddr_reg:x1; val_offset:2088*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2088*FLEN/8, x2, x5, x6) + +inst_732: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x214 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x253 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0cf and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a14; op2val:0xb653; +op3val:0x74cf; valaddr_reg:x1; val_offset:2091*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2091*FLEN/8, x2, x5, x6) + +inst_733: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x214 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x253 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0cf and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a14; op2val:0xb653; +op3val:0x74cf; valaddr_reg:x1; val_offset:2094*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2094*FLEN/8, x2, x5, x6) + +inst_734: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x214 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x253 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0cf and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a14; op2val:0xb653; +op3val:0x74cf; valaddr_reg:x1; val_offset:2097*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2097*FLEN/8, x2, x5, x6) + +inst_735: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x044 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x10a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x160 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7844; op2val:0xb90a; +op3val:0x7560; valaddr_reg:x1; val_offset:2100*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2100*FLEN/8, x2, x5, x6) + +inst_736: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x044 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x10a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x160 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7844; op2val:0xb90a; +op3val:0x7560; valaddr_reg:x1; val_offset:2103*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2103*FLEN/8, x2, x5, x6) + +inst_737: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x044 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x10a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x160 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7844; op2val:0xb90a; +op3val:0x7560; valaddr_reg:x1; val_offset:2106*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2106*FLEN/8, x2, x5, x6) + +inst_738: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x044 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x10a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x160 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7844; op2val:0xb90a; +op3val:0x7560; valaddr_reg:x1; val_offset:2109*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2109*FLEN/8, x2, x5, x6) + +inst_739: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x044 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x10a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x160 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7844; op2val:0xb90a; +op3val:0x7560; valaddr_reg:x1; val_offset:2112*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2112*FLEN/8, x2, x5, x6) + +inst_740: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0bf and fs2 == 1 and fe2 == 0x0f and fm2 == 0x323 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x03c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74bf; op2val:0xbf23; +op3val:0x783c; valaddr_reg:x1; val_offset:2115*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2115*FLEN/8, x2, x5, x6) + +inst_741: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0bf and fs2 == 1 and fe2 == 0x0f and fm2 == 0x323 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x03c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74bf; op2val:0xbf23; +op3val:0x783c; valaddr_reg:x1; val_offset:2118*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2118*FLEN/8, x2, x5, x6) + +inst_742: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0bf and fs2 == 1 and fe2 == 0x0f and fm2 == 0x323 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x03c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74bf; op2val:0xbf23; +op3val:0x783c; valaddr_reg:x1; val_offset:2121*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2121*FLEN/8, x2, x5, x6) + +inst_743: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0bf and fs2 == 1 and fe2 == 0x0f and fm2 == 0x323 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x03c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74bf; op2val:0xbf23; +op3val:0x783c; valaddr_reg:x1; val_offset:2124*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2124*FLEN/8, x2, x5, x6) + +inst_744: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0bf and fs2 == 1 and fe2 == 0x0f and fm2 == 0x323 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x03c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74bf; op2val:0xbf23; +op3val:0x783c; valaddr_reg:x1; val_offset:2127*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2127*FLEN/8, x2, x5, x6) + +inst_745: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x36d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x238 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1c6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x776d; op2val:0xba38; +op3val:0x75c6; valaddr_reg:x1; val_offset:2130*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2130*FLEN/8, x2, x5, x6) + +inst_746: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x36d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x238 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1c6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x776d; op2val:0xba38; +op3val:0x75c6; valaddr_reg:x1; val_offset:2133*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2133*FLEN/8, x2, x5, x6) + +inst_747: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x36d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x238 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1c6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x776d; op2val:0xba38; +op3val:0x75c6; valaddr_reg:x1; val_offset:2136*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2136*FLEN/8, x2, x5, x6) + +inst_748: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x36d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x238 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1c6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x776d; op2val:0xba38; +op3val:0x75c6; valaddr_reg:x1; val_offset:2139*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2139*FLEN/8, x2, x5, x6) + +inst_749: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x36d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x238 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1c6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x776d; op2val:0xba38; +op3val:0x75c6; valaddr_reg:x1; val_offset:2142*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2142*FLEN/8, x2, x5, x6) + +inst_750: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x258 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0b9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f5; op2val:0xba58; +op3val:0x78b9; valaddr_reg:x1; val_offset:2145*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2145*FLEN/8, x2, x5, x6) + +inst_751: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x258 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0b9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f5; op2val:0xba58; +op3val:0x78b9; valaddr_reg:x1; val_offset:2148*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2148*FLEN/8, x2, x5, x6) + +inst_752: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x258 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0b9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f5; op2val:0xba58; +op3val:0x78b9; valaddr_reg:x1; val_offset:2151*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2151*FLEN/8, x2, x5, x6) + +inst_753: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x258 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0b9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f5; op2val:0xba58; +op3val:0x78b9; valaddr_reg:x1; val_offset:2154*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2154*FLEN/8, x2, x5, x6) + +inst_754: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x258 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0b9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f5; op2val:0xba58; +op3val:0x78b9; valaddr_reg:x1; val_offset:2157*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2157*FLEN/8, x2, x5, x6) + +inst_755: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x0a9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2ed and fs3 == 0 and fe3 == 0x1d and fm3 == 0x009 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x68a9; op2val:0xc6ed; +op3val:0x7409; valaddr_reg:x1; val_offset:2160*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2160*FLEN/8, x2, x5, x6) + +inst_756: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x0a9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2ed and fs3 == 0 and fe3 == 0x1d and fm3 == 0x009 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x68a9; op2val:0xc6ed; +op3val:0x7409; valaddr_reg:x1; val_offset:2163*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2163*FLEN/8, x2, x5, x6) + +inst_757: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x0a9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2ed and fs3 == 0 and fe3 == 0x1d and fm3 == 0x009 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x68a9; op2val:0xc6ed; +op3val:0x7409; valaddr_reg:x1; val_offset:2166*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2166*FLEN/8, x2, x5, x6) + +inst_758: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x0a9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2ed and fs3 == 0 and fe3 == 0x1d and fm3 == 0x009 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x68a9; op2val:0xc6ed; +op3val:0x7409; valaddr_reg:x1; val_offset:2169*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2169*FLEN/8, x2, x5, x6) + +inst_759: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x0a9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2ed and fs3 == 0 and fe3 == 0x1d and fm3 == 0x009 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x68a9; op2val:0xc6ed; +op3val:0x7409; valaddr_reg:x1; val_offset:2172*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2172*FLEN/8, x2, x5, x6) + +inst_760: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x005 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x354 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7749; op2val:0xc005; +op3val:0x7b54; valaddr_reg:x1; val_offset:2175*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2175*FLEN/8, x2, x5, x6) + +inst_761: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x005 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x354 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7749; op2val:0xc005; +op3val:0x7b54; valaddr_reg:x1; val_offset:2178*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2178*FLEN/8, x2, x5, x6) + +inst_762: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x005 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x354 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7749; op2val:0xc005; +op3val:0x7b54; valaddr_reg:x1; val_offset:2181*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2181*FLEN/8, x2, x5, x6) + +inst_763: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x005 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x354 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7749; op2val:0xc005; +op3val:0x7b54; valaddr_reg:x1; val_offset:2184*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2184*FLEN/8, x2, x5, x6) + +inst_764: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x005 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x354 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7749; op2val:0xc005; +op3val:0x7b54; valaddr_reg:x1; val_offset:2187*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2187*FLEN/8, x2, x5, x6) + +inst_765: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x319 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0ea and fs3 == 0 and fe3 == 0x1e and fm3 == 0x05c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b19; op2val:0xb8ea; +op3val:0x785c; valaddr_reg:x1; val_offset:2190*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2190*FLEN/8, x2, x5, x6) + +inst_766: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x319 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0ea and fs3 == 0 and fe3 == 0x1e and fm3 == 0x05c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b19; op2val:0xb8ea; +op3val:0x785c; valaddr_reg:x1; val_offset:2193*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2193*FLEN/8, x2, x5, x6) + +inst_767: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x319 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0ea and fs3 == 0 and fe3 == 0x1e and fm3 == 0x05c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b19; op2val:0xb8ea; +op3val:0x785c; valaddr_reg:x1; val_offset:2196*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2196*FLEN/8, x2, x5, x6) + +inst_768: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x319 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0ea and fs3 == 0 and fe3 == 0x1e and fm3 == 0x05c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b19; op2val:0xb8ea; +op3val:0x785c; valaddr_reg:x1; val_offset:2199*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2199*FLEN/8, x2, x5, x6) + +inst_769: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x319 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0ea and fs3 == 0 and fe3 == 0x1e and fm3 == 0x05c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b19; op2val:0xb8ea; +op3val:0x785c; valaddr_reg:x1; val_offset:2202*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2202*FLEN/8, x2, x5, x6) + +inst_770: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x375 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x2ac and fs3 == 0 and fe3 == 0x1e and fm3 == 0x239 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6375; op2val:0xd2ac; +op3val:0x7a39; valaddr_reg:x1; val_offset:2205*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2205*FLEN/8, x2, x5, x6) + +inst_771: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x375 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x2ac and fs3 == 0 and fe3 == 0x1e and fm3 == 0x239 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6375; op2val:0xd2ac; +op3val:0x7a39; valaddr_reg:x1; val_offset:2208*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2208*FLEN/8, x2, x5, x6) + +inst_772: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x375 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x2ac and fs3 == 0 and fe3 == 0x1e and fm3 == 0x239 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6375; op2val:0xd2ac; +op3val:0x7a39; valaddr_reg:x1; val_offset:2211*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2211*FLEN/8, x2, x5, x6) + +inst_773: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x375 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x2ac and fs3 == 0 and fe3 == 0x1e and fm3 == 0x239 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6375; op2val:0xd2ac; +op3val:0x7a39; valaddr_reg:x1; val_offset:2214*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2214*FLEN/8, x2, x5, x6) + +inst_774: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x375 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x2ac and fs3 == 0 and fe3 == 0x1e and fm3 == 0x239 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6375; op2val:0xd2ac; +op3val:0x7a39; valaddr_reg:x1; val_offset:2217*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2217*FLEN/8, x2, x5, x6) + +inst_775: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2d7 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x162 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x09a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76d7; op2val:0xbd62; +op3val:0x789a; valaddr_reg:x1; val_offset:2220*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2220*FLEN/8, x2, x5, x6) + +inst_776: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2d7 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x162 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x09a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76d7; op2val:0xbd62; +op3val:0x789a; valaddr_reg:x1; val_offset:2223*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2223*FLEN/8, x2, x5, x6) + +inst_777: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2d7 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x162 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x09a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76d7; op2val:0xbd62; +op3val:0x789a; valaddr_reg:x1; val_offset:2226*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2226*FLEN/8, x2, x5, x6) + +inst_778: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2d7 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x162 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x09a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76d7; op2val:0xbd62; +op3val:0x789a; valaddr_reg:x1; val_offset:2229*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2229*FLEN/8, x2, x5, x6) + +inst_779: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2d7 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x162 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x09a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76d7; op2val:0xbd62; +op3val:0x789a; valaddr_reg:x1; val_offset:2232*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2232*FLEN/8, x2, x5, x6) + +inst_780: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a9 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x324 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x10e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79a9; op2val:0xbb24; +op3val:0x790e; valaddr_reg:x1; val_offset:2235*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2235*FLEN/8, x2, x5, x6) + +inst_781: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a9 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x324 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x10e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79a9; op2val:0xbb24; +op3val:0x790e; valaddr_reg:x1; val_offset:2238*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2238*FLEN/8, x2, x5, x6) + +inst_782: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a9 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x324 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x10e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79a9; op2val:0xbb24; +op3val:0x790e; valaddr_reg:x1; val_offset:2241*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2241*FLEN/8, x2, x5, x6) + +inst_783: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a9 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x324 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x10e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79a9; op2val:0xbb24; +op3val:0x790e; valaddr_reg:x1; val_offset:2244*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2244*FLEN/8, x2, x5, x6) + +inst_784: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a9 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x324 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x10e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79a9; op2val:0xbb24; +op3val:0x790e; valaddr_reg:x1; val_offset:2247*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2247*FLEN/8, x2, x5, x6) + +inst_785: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3b4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x391 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x34a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77b4; op2val:0xbf91; +op3val:0x7b4a; valaddr_reg:x1; val_offset:2250*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2250*FLEN/8, x2, x5, x6) + +inst_786: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3b4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x391 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x34a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77b4; op2val:0xbf91; +op3val:0x7b4a; valaddr_reg:x1; val_offset:2253*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2253*FLEN/8, x2, x5, x6) + +inst_787: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3b4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x391 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x34a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77b4; op2val:0xbf91; +op3val:0x7b4a; valaddr_reg:x1; val_offset:2256*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2256*FLEN/8, x2, x5, x6) + +inst_788: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3b4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x391 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x34a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77b4; op2val:0xbf91; +op3val:0x7b4a; valaddr_reg:x1; val_offset:2259*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2259*FLEN/8, x2, x5, x6) + +inst_789: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3b4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x391 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x34a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77b4; op2val:0xbf91; +op3val:0x7b4a; valaddr_reg:x1; val_offset:2262*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2262*FLEN/8, x2, x5, x6) + +inst_790: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x22a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x010 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x244 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x762a; op2val:0xbc10; +op3val:0x7644; valaddr_reg:x1; val_offset:2265*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2265*FLEN/8, x2, x5, x6) + +inst_791: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x22a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x010 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x244 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x762a; op2val:0xbc10; +op3val:0x7644; valaddr_reg:x1; val_offset:2268*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2268*FLEN/8, x2, x5, x6) + +inst_792: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x22a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x010 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x244 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x762a; op2val:0xbc10; +op3val:0x7644; valaddr_reg:x1; val_offset:2271*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2271*FLEN/8, x2, x5, x6) + +inst_793: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x22a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x010 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x244 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x762a; op2val:0xbc10; +op3val:0x7644; valaddr_reg:x1; val_offset:2274*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2274*FLEN/8, x2, x5, x6) + +inst_794: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x22a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x010 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x244 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x762a; op2val:0xbc10; +op3val:0x7644; valaddr_reg:x1; val_offset:2277*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2277*FLEN/8, x2, x5, x6) + +inst_795: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2cf and fs2 == 1 and fe2 == 0x0c and fm2 == 0x361 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x248 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7acf; op2val:0xb361; +op3val:0x7248; valaddr_reg:x1; val_offset:2280*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2280*FLEN/8, x2, x5, x6) +RVTEST_SIGBASE(x5,signature_x5_6) + +inst_796: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2cf and fs2 == 1 and fe2 == 0x0c and fm2 == 0x361 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x248 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7acf; op2val:0xb361; +op3val:0x7248; valaddr_reg:x1; val_offset:2283*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2283*FLEN/8, x2, x5, x6) + +inst_797: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2cf and fs2 == 1 and fe2 == 0x0c and fm2 == 0x361 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x248 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7acf; op2val:0xb361; +op3val:0x7248; valaddr_reg:x1; val_offset:2286*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2286*FLEN/8, x2, x5, x6) + +inst_798: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2cf and fs2 == 1 and fe2 == 0x0c and fm2 == 0x361 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x248 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7acf; op2val:0xb361; +op3val:0x7248; valaddr_reg:x1; val_offset:2289*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2289*FLEN/8, x2, x5, x6) + +inst_799: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2cf and fs2 == 1 and fe2 == 0x0c and fm2 == 0x361 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x248 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7acf; op2val:0xb361; +op3val:0x7248; valaddr_reg:x1; val_offset:2292*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2292*FLEN/8, x2, x5, x6) + +inst_800: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0bd and fs2 == 1 and fe2 == 0x10 and fm2 == 0x199 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74bd; op2val:0xc199; +op3val:0x7aa3; valaddr_reg:x1; val_offset:2295*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2295*FLEN/8, x2, x5, x6) + +inst_801: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0bd and fs2 == 1 and fe2 == 0x10 and fm2 == 0x199 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74bd; op2val:0xc199; +op3val:0x7aa3; valaddr_reg:x1; val_offset:2298*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2298*FLEN/8, x2, x5, x6) + +inst_802: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0bd and fs2 == 1 and fe2 == 0x10 and fm2 == 0x199 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74bd; op2val:0xc199; +op3val:0x7aa3; valaddr_reg:x1; val_offset:2301*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2301*FLEN/8, x2, x5, x6) + +inst_803: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0bd and fs2 == 1 and fe2 == 0x10 and fm2 == 0x199 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74bd; op2val:0xc199; +op3val:0x7aa3; valaddr_reg:x1; val_offset:2304*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2304*FLEN/8, x2, x5, x6) + +inst_804: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0bd and fs2 == 1 and fe2 == 0x10 and fm2 == 0x199 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74bd; op2val:0xc199; +op3val:0x7aa3; valaddr_reg:x1; val_offset:2307*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2307*FLEN/8, x2, x5, x6) + +inst_805: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x039 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x254 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2af and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c39; op2val:0xca54; +op3val:0x7aaf; valaddr_reg:x1; val_offset:2310*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2310*FLEN/8, x2, x5, x6) + +inst_806: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x039 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x254 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2af and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c39; op2val:0xca54; +op3val:0x7aaf; valaddr_reg:x1; val_offset:2313*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2313*FLEN/8, x2, x5, x6) + +inst_807: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x039 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x254 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2af and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c39; op2val:0xca54; +op3val:0x7aaf; valaddr_reg:x1; val_offset:2316*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2316*FLEN/8, x2, x5, x6) + +inst_808: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x039 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x254 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2af and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c39; op2val:0xca54; +op3val:0x7aaf; valaddr_reg:x1; val_offset:2319*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2319*FLEN/8, x2, x5, x6) + +inst_809: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x039 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x254 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2af and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c39; op2val:0xca54; +op3val:0x7aaf; valaddr_reg:x1; val_offset:2322*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2322*FLEN/8, x2, x5, x6) + +inst_810: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x18d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0fc and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2ec and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x798d; op2val:0xb8fc; +op3val:0x76ec; valaddr_reg:x1; val_offset:2325*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2325*FLEN/8, x2, x5, x6) + +inst_811: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x18d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0fc and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2ec and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x798d; op2val:0xb8fc; +op3val:0x76ec; valaddr_reg:x1; val_offset:2328*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2328*FLEN/8, x2, x5, x6) + +inst_812: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x18d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0fc and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2ec and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x798d; op2val:0xb8fc; +op3val:0x76ec; valaddr_reg:x1; val_offset:2331*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2331*FLEN/8, x2, x5, x6) + +inst_813: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x18d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0fc and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2ec and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x798d; op2val:0xb8fc; +op3val:0x76ec; valaddr_reg:x1; val_offset:2334*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2334*FLEN/8, x2, x5, x6) + +inst_814: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x18d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0fc and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2ec and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x798d; op2val:0xb8fc; +op3val:0x76ec; valaddr_reg:x1; val_offset:2337*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2337*FLEN/8, x2, x5, x6) + +inst_815: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x094 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x173 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x23e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7494; op2val:0xc173; +op3val:0x7a3e; valaddr_reg:x1; val_offset:2340*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2340*FLEN/8, x2, x5, x6) + +inst_816: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x094 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x173 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x23e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7494; op2val:0xc173; +op3val:0x7a3e; valaddr_reg:x1; val_offset:2343*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2343*FLEN/8, x2, x5, x6) + +inst_817: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x094 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x173 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x23e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7494; op2val:0xc173; +op3val:0x7a3e; valaddr_reg:x1; val_offset:2346*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2346*FLEN/8, x2, x5, x6) + +inst_818: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x094 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x173 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x23e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7494; op2val:0xc173; +op3val:0x7a3e; valaddr_reg:x1; val_offset:2349*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2349*FLEN/8, x2, x5, x6) + +inst_819: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x094 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x173 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x23e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7494; op2val:0xc173; +op3val:0x7a3e; valaddr_reg:x1; val_offset:2352*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2352*FLEN/8, x2, x5, x6) + +inst_820: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x348 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x103 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x090 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b48; op2val:0xb103; +op3val:0x7090; valaddr_reg:x1; val_offset:2355*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2355*FLEN/8, x2, x5, x6) + +inst_821: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x348 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x103 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x090 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b48; op2val:0xb103; +op3val:0x7090; valaddr_reg:x1; val_offset:2358*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2358*FLEN/8, x2, x5, x6) + +inst_822: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x348 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x103 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x090 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b48; op2val:0xb103; +op3val:0x7090; valaddr_reg:x1; val_offset:2361*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2361*FLEN/8, x2, x5, x6) + +inst_823: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x348 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x103 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x090 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b48; op2val:0xb103; +op3val:0x7090; valaddr_reg:x1; val_offset:2364*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2364*FLEN/8, x2, x5, x6) + +inst_824: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x348 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x103 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x090 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b48; op2val:0xb103; +op3val:0x7090; valaddr_reg:x1; val_offset:2367*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2367*FLEN/8, x2, x5, x6) + +inst_825: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a6 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x097 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x064 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77a6; op2val:0xbc97; +op3val:0x7864; valaddr_reg:x1; val_offset:2370*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2370*FLEN/8, x2, x5, x6) + +inst_826: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a6 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x097 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x064 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77a6; op2val:0xbc97; +op3val:0x7864; valaddr_reg:x1; val_offset:2373*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2373*FLEN/8, x2, x5, x6) + +inst_827: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a6 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x097 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x064 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77a6; op2val:0xbc97; +op3val:0x7864; valaddr_reg:x1; val_offset:2376*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2376*FLEN/8, x2, x5, x6) + +inst_828: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a6 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x097 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x064 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77a6; op2val:0xbc97; +op3val:0x7864; valaddr_reg:x1; val_offset:2379*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2379*FLEN/8, x2, x5, x6) + +inst_829: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a6 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x097 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x064 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77a6; op2val:0xbc97; +op3val:0x7864; valaddr_reg:x1; val_offset:2382*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2382*FLEN/8, x2, x5, x6) + +inst_830: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3f5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x151 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x14a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77f5; op2val:0xb951; +op3val:0x754a; valaddr_reg:x1; val_offset:2385*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2385*FLEN/8, x2, x5, x6) + +inst_831: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3f5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x151 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x14a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77f5; op2val:0xb951; +op3val:0x754a; valaddr_reg:x1; val_offset:2388*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2388*FLEN/8, x2, x5, x6) + +inst_832: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3f5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x151 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x14a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77f5; op2val:0xb951; +op3val:0x754a; valaddr_reg:x1; val_offset:2391*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2391*FLEN/8, x2, x5, x6) + +inst_833: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3f5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x151 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x14a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77f5; op2val:0xb951; +op3val:0x754a; valaddr_reg:x1; val_offset:2394*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2394*FLEN/8, x2, x5, x6) + +inst_834: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3f5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x151 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x14a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77f5; op2val:0xb951; +op3val:0x754a; valaddr_reg:x1; val_offset:2397*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2397*FLEN/8, x2, x5, x6) + +inst_835: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0e9 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3a1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0af and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70e9; op2val:0xc3a1; +op3val:0x78af; valaddr_reg:x1; val_offset:2400*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2400*FLEN/8, x2, x5, x6) + +inst_836: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0e9 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3a1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0af and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70e9; op2val:0xc3a1; +op3val:0x78af; valaddr_reg:x1; val_offset:2403*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2403*FLEN/8, x2, x5, x6) + +inst_837: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0e9 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3a1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0af and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70e9; op2val:0xc3a1; +op3val:0x78af; valaddr_reg:x1; val_offset:2406*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2406*FLEN/8, x2, x5, x6) + +inst_838: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0e9 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3a1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0af and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70e9; op2val:0xc3a1; +op3val:0x78af; valaddr_reg:x1; val_offset:2409*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2409*FLEN/8, x2, x5, x6) + +inst_839: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0e9 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3a1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0af and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70e9; op2val:0xc3a1; +op3val:0x78af; valaddr_reg:x1; val_offset:2412*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2412*FLEN/8, x2, x5, x6) + +inst_840: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x27d and fs2 == 1 and fe2 == 0x0b and fm2 == 0x151 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x060 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a7d; op2val:0xad51; +op3val:0x6c60; valaddr_reg:x1; val_offset:2415*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2415*FLEN/8, x2, x5, x6) + +inst_841: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x27d and fs2 == 1 and fe2 == 0x0b and fm2 == 0x151 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x060 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a7d; op2val:0xad51; +op3val:0x6c60; valaddr_reg:x1; val_offset:2418*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2418*FLEN/8, x2, x5, x6) + +inst_842: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x27d and fs2 == 1 and fe2 == 0x0b and fm2 == 0x151 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x060 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a7d; op2val:0xad51; +op3val:0x6c60; valaddr_reg:x1; val_offset:2421*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2421*FLEN/8, x2, x5, x6) + +inst_843: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x27d and fs2 == 1 and fe2 == 0x0b and fm2 == 0x151 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x060 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a7d; op2val:0xad51; +op3val:0x6c60; valaddr_reg:x1; val_offset:2424*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2424*FLEN/8, x2, x5, x6) + +inst_844: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x27d and fs2 == 1 and fe2 == 0x0b and fm2 == 0x151 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x060 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a7d; op2val:0xad51; +op3val:0x6c60; valaddr_reg:x1; val_offset:2427*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2427*FLEN/8, x2, x5, x6) + +inst_845: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x35b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x31e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x28d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x735b; op2val:0xc31e; +op3val:0x7a8d; valaddr_reg:x1; val_offset:2430*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2430*FLEN/8, x2, x5, x6) + +inst_846: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x35b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x31e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x28d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x735b; op2val:0xc31e; +op3val:0x7a8d; valaddr_reg:x1; val_offset:2433*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2433*FLEN/8, x2, x5, x6) + +inst_847: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x35b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x31e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x28d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x735b; op2val:0xc31e; +op3val:0x7a8d; valaddr_reg:x1; val_offset:2436*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2436*FLEN/8, x2, x5, x6) + +inst_848: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x35b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x31e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x28d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x735b; op2val:0xc31e; +op3val:0x7a8d; valaddr_reg:x1; val_offset:2439*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2439*FLEN/8, x2, x5, x6) + +inst_849: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x35b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x31e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x28d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x735b; op2val:0xc31e; +op3val:0x7a8d; valaddr_reg:x1; val_offset:2442*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2442*FLEN/8, x2, x5, x6) + +inst_850: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x254 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2b1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a54; op2val:0xbab1; +op3val:0x794e; valaddr_reg:x1; val_offset:2445*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2445*FLEN/8, x2, x5, x6) + +inst_851: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x254 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2b1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a54; op2val:0xbab1; +op3val:0x794e; valaddr_reg:x1; val_offset:2448*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2448*FLEN/8, x2, x5, x6) + +inst_852: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x254 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2b1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a54; op2val:0xbab1; +op3val:0x794e; valaddr_reg:x1; val_offset:2451*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2451*FLEN/8, x2, x5, x6) + +inst_853: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x254 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2b1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a54; op2val:0xbab1; +op3val:0x794e; valaddr_reg:x1; val_offset:2454*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2454*FLEN/8, x2, x5, x6) + +inst_854: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x254 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2b1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a54; op2val:0xbab1; +op3val:0x794e; valaddr_reg:x1; val_offset:2457*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2457*FLEN/8, x2, x5, x6) + +inst_855: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x28a and fs2 == 1 and fe2 == 0x13 and fm2 == 0x30e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1c7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x668a; op2val:0xcf0e; +op3val:0x79c7; valaddr_reg:x1; val_offset:2460*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2460*FLEN/8, x2, x5, x6) + +inst_856: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x28a and fs2 == 1 and fe2 == 0x13 and fm2 == 0x30e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1c7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x668a; op2val:0xcf0e; +op3val:0x79c7; valaddr_reg:x1; val_offset:2463*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2463*FLEN/8, x2, x5, x6) + +inst_857: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x28a and fs2 == 1 and fe2 == 0x13 and fm2 == 0x30e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1c7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x668a; op2val:0xcf0e; +op3val:0x79c7; valaddr_reg:x1; val_offset:2466*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2466*FLEN/8, x2, x5, x6) + +inst_858: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x28a and fs2 == 1 and fe2 == 0x13 and fm2 == 0x30e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1c7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x668a; op2val:0xcf0e; +op3val:0x79c7; valaddr_reg:x1; val_offset:2469*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2469*FLEN/8, x2, x5, x6) + +inst_859: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x28a and fs2 == 1 and fe2 == 0x13 and fm2 == 0x30e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1c7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x668a; op2val:0xcf0e; +op3val:0x79c7; valaddr_reg:x1; val_offset:2472*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2472*FLEN/8, x2, x5, x6) + +inst_860: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x013 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3fb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd3; op2val:0xbc13; +op3val:0x7bfb; valaddr_reg:x1; val_offset:2475*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2475*FLEN/8, x2, x5, x6) + +inst_861: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x013 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3fb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd3; op2val:0xbc13; +op3val:0x7bfb; valaddr_reg:x1; val_offset:2478*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2478*FLEN/8, x2, x5, x6) + +inst_862: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x013 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3fb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd3; op2val:0xbc13; +op3val:0x7bfb; valaddr_reg:x1; val_offset:2481*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2481*FLEN/8, x2, x5, x6) + +inst_863: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x013 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3fb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd3; op2val:0xbc13; +op3val:0x7bfb; valaddr_reg:x1; val_offset:2484*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2484*FLEN/8, x2, x5, x6) + +inst_864: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x013 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3fb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd3; op2val:0xbc13; +op3val:0x7bfb; valaddr_reg:x1; val_offset:2487*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2487*FLEN/8, x2, x5, x6) + +inst_865: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19b and fs2 == 1 and fe2 == 0x0b and fm2 == 0x05f and fs3 == 0 and fe3 == 0x1a and fm3 == 0x241 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x799b; op2val:0xac5f; +op3val:0x6a41; valaddr_reg:x1; val_offset:2490*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2490*FLEN/8, x2, x5, x6) + +inst_866: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19b and fs2 == 1 and fe2 == 0x0b and fm2 == 0x05f and fs3 == 0 and fe3 == 0x1a and fm3 == 0x241 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x799b; op2val:0xac5f; +op3val:0x6a41; valaddr_reg:x1; val_offset:2493*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2493*FLEN/8, x2, x5, x6) + +inst_867: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19b and fs2 == 1 and fe2 == 0x0b and fm2 == 0x05f and fs3 == 0 and fe3 == 0x1a and fm3 == 0x241 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x799b; op2val:0xac5f; +op3val:0x6a41; valaddr_reg:x1; val_offset:2496*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2496*FLEN/8, x2, x5, x6) + +inst_868: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19b and fs2 == 1 and fe2 == 0x0b and fm2 == 0x05f and fs3 == 0 and fe3 == 0x1a and fm3 == 0x241 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x799b; op2val:0xac5f; +op3val:0x6a41; valaddr_reg:x1; val_offset:2499*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2499*FLEN/8, x2, x5, x6) + +inst_869: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19b and fs2 == 1 and fe2 == 0x0b and fm2 == 0x05f and fs3 == 0 and fe3 == 0x1a and fm3 == 0x241 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x799b; op2val:0xac5f; +op3val:0x6a41; valaddr_reg:x1; val_offset:2502*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2502*FLEN/8, x2, x5, x6) + +inst_870: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2bb and fs2 == 1 and fe2 == 0x0d and fm2 == 0x025 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x303 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7abb; op2val:0xb425; +op3val:0x7303; valaddr_reg:x1; val_offset:2505*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2505*FLEN/8, x2, x5, x6) + +inst_871: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2bb and fs2 == 1 and fe2 == 0x0d and fm2 == 0x025 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x303 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7abb; op2val:0xb425; +op3val:0x7303; valaddr_reg:x1; val_offset:2508*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2508*FLEN/8, x2, x5, x6) + +inst_872: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2bb and fs2 == 1 and fe2 == 0x0d and fm2 == 0x025 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x303 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7abb; op2val:0xb425; +op3val:0x7303; valaddr_reg:x1; val_offset:2511*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2511*FLEN/8, x2, x5, x6) + +inst_873: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2bb and fs2 == 1 and fe2 == 0x0d and fm2 == 0x025 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x303 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7abb; op2val:0xb425; +op3val:0x7303; valaddr_reg:x1; val_offset:2514*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2514*FLEN/8, x2, x5, x6) + +inst_874: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2bb and fs2 == 1 and fe2 == 0x0d and fm2 == 0x025 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x303 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7abb; op2val:0xb425; +op3val:0x7303; valaddr_reg:x1; val_offset:2517*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2517*FLEN/8, x2, x5, x6) + +inst_875: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x129 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1e7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x39d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7929; op2val:0xbde7; +op3val:0x7b9d; valaddr_reg:x1; val_offset:2520*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2520*FLEN/8, x2, x5, x6) + +inst_876: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x129 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1e7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x39d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7929; op2val:0xbde7; +op3val:0x7b9d; valaddr_reg:x1; val_offset:2523*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2523*FLEN/8, x2, x5, x6) + +inst_877: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x129 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1e7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x39d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7929; op2val:0xbde7; +op3val:0x7b9d; valaddr_reg:x1; val_offset:2526*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2526*FLEN/8, x2, x5, x6) + +inst_878: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x129 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1e7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x39d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7929; op2val:0xbde7; +op3val:0x7b9d; valaddr_reg:x1; val_offset:2529*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2529*FLEN/8, x2, x5, x6) + +inst_879: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x129 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1e7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x39d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7929; op2val:0xbde7; +op3val:0x7b9d; valaddr_reg:x1; val_offset:2532*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2532*FLEN/8, x2, x5, x6) + +inst_880: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b2 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x217 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x04e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79b2; op2val:0xb217; +op3val:0x704e; valaddr_reg:x1; val_offset:2535*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2535*FLEN/8, x2, x5, x6) + +inst_881: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b2 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x217 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x04e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79b2; op2val:0xb217; +op3val:0x704e; valaddr_reg:x1; val_offset:2538*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2538*FLEN/8, x2, x5, x6) + +inst_882: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b2 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x217 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x04e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79b2; op2val:0xb217; +op3val:0x704e; valaddr_reg:x1; val_offset:2541*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2541*FLEN/8, x2, x5, x6) + +inst_883: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b2 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x217 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x04e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79b2; op2val:0xb217; +op3val:0x704e; valaddr_reg:x1; val_offset:2544*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2544*FLEN/8, x2, x5, x6) + +inst_884: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b2 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x217 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x04e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79b2; op2val:0xb217; +op3val:0x704e; valaddr_reg:x1; val_offset:2547*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2547*FLEN/8, x2, x5, x6) + +inst_885: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ad and fs2 == 1 and fe2 == 0x10 and fm2 == 0x248 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x357 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74ad; op2val:0xc248; +op3val:0x7b57; valaddr_reg:x1; val_offset:2550*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2550*FLEN/8, x2, x5, x6) + +inst_886: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ad and fs2 == 1 and fe2 == 0x10 and fm2 == 0x248 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x357 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74ad; op2val:0xc248; +op3val:0x7b57; valaddr_reg:x1; val_offset:2553*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2553*FLEN/8, x2, x5, x6) + +inst_887: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ad and fs2 == 1 and fe2 == 0x10 and fm2 == 0x248 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x357 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74ad; op2val:0xc248; +op3val:0x7b57; valaddr_reg:x1; val_offset:2556*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2556*FLEN/8, x2, x5, x6) + +inst_888: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ad and fs2 == 1 and fe2 == 0x10 and fm2 == 0x248 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x357 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74ad; op2val:0xc248; +op3val:0x7b57; valaddr_reg:x1; val_offset:2559*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2559*FLEN/8, x2, x5, x6) + +inst_889: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ad and fs2 == 1 and fe2 == 0x10 and fm2 == 0x248 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x357 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74ad; op2val:0xc248; +op3val:0x7b57; valaddr_reg:x1; val_offset:2562*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2562*FLEN/8, x2, x5, x6) + +inst_890: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0ca and fs2 == 1 and fe2 == 0x11 and fm2 == 0x015 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0e1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70ca; op2val:0xc415; +op3val:0x78e1; valaddr_reg:x1; val_offset:2565*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2565*FLEN/8, x2, x5, x6) + +inst_891: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0ca and fs2 == 1 and fe2 == 0x11 and fm2 == 0x015 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0e1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70ca; op2val:0xc415; +op3val:0x78e1; valaddr_reg:x1; val_offset:2568*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2568*FLEN/8, x2, x5, x6) + +inst_892: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0ca and fs2 == 1 and fe2 == 0x11 and fm2 == 0x015 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0e1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70ca; op2val:0xc415; +op3val:0x78e1; valaddr_reg:x1; val_offset:2571*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2571*FLEN/8, x2, x5, x6) + +inst_893: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0ca and fs2 == 1 and fe2 == 0x11 and fm2 == 0x015 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0e1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70ca; op2val:0xc415; +op3val:0x78e1; valaddr_reg:x1; val_offset:2574*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2574*FLEN/8, x2, x5, x6) + +inst_894: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0ca and fs2 == 1 and fe2 == 0x11 and fm2 == 0x015 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0e1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70ca; op2val:0xc415; +op3val:0x78e1; valaddr_reg:x1; val_offset:2577*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2577*FLEN/8, x2, x5, x6) + +inst_895: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x29e and fs2 == 1 and fe2 == 0x0d and fm2 == 0x244 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x127 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x769e; op2val:0xb644; +op3val:0x7127; valaddr_reg:x1; val_offset:2580*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2580*FLEN/8, x2, x5, x6) + +inst_896: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x29e and fs2 == 1 and fe2 == 0x0d and fm2 == 0x244 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x127 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x769e; op2val:0xb644; +op3val:0x7127; valaddr_reg:x1; val_offset:2583*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2583*FLEN/8, x2, x5, x6) + +inst_897: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x29e and fs2 == 1 and fe2 == 0x0d and fm2 == 0x244 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x127 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x769e; op2val:0xb644; +op3val:0x7127; valaddr_reg:x1; val_offset:2586*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2586*FLEN/8, x2, x5, x6) + +inst_898: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x29e and fs2 == 1 and fe2 == 0x0d and fm2 == 0x244 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x127 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x769e; op2val:0xb644; +op3val:0x7127; valaddr_reg:x1; val_offset:2589*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2589*FLEN/8, x2, x5, x6) + +inst_899: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x29e and fs2 == 1 and fe2 == 0x0d and fm2 == 0x244 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x127 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x769e; op2val:0xb644; +op3val:0x7127; valaddr_reg:x1; val_offset:2592*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2592*FLEN/8, x2, x5, x6) + +inst_900: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fa and fs2 == 1 and fe2 == 0x0b and fm2 == 0x094 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x193 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fa; op2val:0xac94; +op3val:0x6993; valaddr_reg:x1; val_offset:2595*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2595*FLEN/8, x2, x5, x6) + +inst_901: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fa and fs2 == 1 and fe2 == 0x0b and fm2 == 0x094 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x193 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fa; op2val:0xac94; +op3val:0x6993; valaddr_reg:x1; val_offset:2598*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2598*FLEN/8, x2, x5, x6) + +inst_902: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fa and fs2 == 1 and fe2 == 0x0b and fm2 == 0x094 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x193 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fa; op2val:0xac94; +op3val:0x6993; valaddr_reg:x1; val_offset:2601*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2601*FLEN/8, x2, x5, x6) + +inst_903: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fa and fs2 == 1 and fe2 == 0x0b and fm2 == 0x094 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x193 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fa; op2val:0xac94; +op3val:0x6993; valaddr_reg:x1; val_offset:2604*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2604*FLEN/8, x2, x5, x6) + +inst_904: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fa and fs2 == 1 and fe2 == 0x0b and fm2 == 0x094 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x193 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fa; op2val:0xac94; +op3val:0x6993; valaddr_reg:x1; val_offset:2607*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2607*FLEN/8, x2, x5, x6) + +inst_905: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2ec and fs2 == 1 and fe2 == 0x10 and fm2 == 0x306 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x210 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6eec; op2val:0xc306; +op3val:0x7610; valaddr_reg:x1; val_offset:2610*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2610*FLEN/8, x2, x5, x6) + +inst_906: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2ec and fs2 == 1 and fe2 == 0x10 and fm2 == 0x306 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x210 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6eec; op2val:0xc306; +op3val:0x7610; valaddr_reg:x1; val_offset:2613*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2613*FLEN/8, x2, x5, x6) + +inst_907: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2ec and fs2 == 1 and fe2 == 0x10 and fm2 == 0x306 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x210 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6eec; op2val:0xc306; +op3val:0x7610; valaddr_reg:x1; val_offset:2616*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2616*FLEN/8, x2, x5, x6) + +inst_908: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2ec and fs2 == 1 and fe2 == 0x10 and fm2 == 0x306 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x210 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6eec; op2val:0xc306; +op3val:0x7610; valaddr_reg:x1; val_offset:2619*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2619*FLEN/8, x2, x5, x6) + +inst_909: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2ec and fs2 == 1 and fe2 == 0x10 and fm2 == 0x306 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x210 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6eec; op2val:0xc306; +op3val:0x7610; valaddr_reg:x1; val_offset:2622*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2622*FLEN/8, x2, x5, x6) + +inst_910: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x09b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x281 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x35d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c9b; op2val:0xba81; +op3val:0x6b5d; valaddr_reg:x1; val_offset:2625*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2625*FLEN/8, x2, x5, x6) + +inst_911: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x09b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x281 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x35d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c9b; op2val:0xba81; +op3val:0x6b5d; valaddr_reg:x1; val_offset:2628*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2628*FLEN/8, x2, x5, x6) + +inst_912: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x09b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x281 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x35d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c9b; op2val:0xba81; +op3val:0x6b5d; valaddr_reg:x1; val_offset:2631*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2631*FLEN/8, x2, x5, x6) + +inst_913: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x09b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x281 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x35d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c9b; op2val:0xba81; +op3val:0x6b5d; valaddr_reg:x1; val_offset:2634*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2634*FLEN/8, x2, x5, x6) + +inst_914: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x09b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x281 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x35d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c9b; op2val:0xba81; +op3val:0x6b5d; valaddr_reg:x1; val_offset:2637*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2637*FLEN/8, x2, x5, x6) + +inst_915: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x099 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x12b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ef and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7899; op2val:0xbd2b; +op3val:0x79ef; valaddr_reg:x1; val_offset:2640*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2640*FLEN/8, x2, x5, x6) + +inst_916: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x099 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x12b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ef and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7899; op2val:0xbd2b; +op3val:0x79ef; valaddr_reg:x1; val_offset:2643*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2643*FLEN/8, x2, x5, x6) + +inst_917: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x099 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x12b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ef and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7899; op2val:0xbd2b; +op3val:0x79ef; valaddr_reg:x1; val_offset:2646*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2646*FLEN/8, x2, x5, x6) + +inst_918: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x099 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x12b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ef and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7899; op2val:0xbd2b; +op3val:0x79ef; valaddr_reg:x1; val_offset:2649*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2649*FLEN/8, x2, x5, x6) + +inst_919: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x099 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x12b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ef and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7899; op2val:0xbd2b; +op3val:0x79ef; valaddr_reg:x1; val_offset:2652*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2652*FLEN/8, x2, x5, x6) + +inst_920: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x306 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0ed and fs3 == 0 and fe3 == 0x1c and fm3 == 0x04c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b06; op2val:0xb0ed; +op3val:0x704c; valaddr_reg:x1; val_offset:2655*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2655*FLEN/8, x2, x5, x6) + +inst_921: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x306 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0ed and fs3 == 0 and fe3 == 0x1c and fm3 == 0x04c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b06; op2val:0xb0ed; +op3val:0x704c; valaddr_reg:x1; val_offset:2658*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2658*FLEN/8, x2, x5, x6) + +inst_922: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x306 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0ed and fs3 == 0 and fe3 == 0x1c and fm3 == 0x04c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b06; op2val:0xb0ed; +op3val:0x704c; valaddr_reg:x1; val_offset:2661*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2661*FLEN/8, x2, x5, x6) + +inst_923: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x306 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0ed and fs3 == 0 and fe3 == 0x1c and fm3 == 0x04c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b06; op2val:0xb0ed; +op3val:0x704c; valaddr_reg:x1; val_offset:2664*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2664*FLEN/8, x2, x5, x6) +RVTEST_SIGBASE(x5,signature_x5_7) + +inst_924: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x306 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0ed and fs3 == 0 and fe3 == 0x1c and fm3 == 0x04c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b06; op2val:0xb0ed; +op3val:0x704c; valaddr_reg:x1; val_offset:2667*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2667*FLEN/8, x2, x5, x6) + +inst_925: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1d9 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x107 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76e7; op2val:0xb9d9; +op3val:0x7507; valaddr_reg:x1; val_offset:2670*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2670*FLEN/8, x2, x5, x6) + +inst_926: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1d9 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x107 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76e7; op2val:0xb9d9; +op3val:0x7507; valaddr_reg:x1; val_offset:2673*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2673*FLEN/8, x2, x5, x6) + +inst_927: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1d9 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x107 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76e7; op2val:0xb9d9; +op3val:0x7507; valaddr_reg:x1; val_offset:2676*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2676*FLEN/8, x2, x5, x6) + +inst_928: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1d9 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x107 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76e7; op2val:0xb9d9; +op3val:0x7507; valaddr_reg:x1; val_offset:2679*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2679*FLEN/8, x2, x5, x6) + +inst_929: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1d9 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x107 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76e7; op2val:0xb9d9; +op3val:0x7507; valaddr_reg:x1; val_offset:2682*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2682*FLEN/8, x2, x5, x6) + +inst_930: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0cc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x289 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3d4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78cc; op2val:0xba89; +op3val:0x77d4; valaddr_reg:x1; val_offset:2685*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2685*FLEN/8, x2, x5, x6) + +inst_931: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0cc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x289 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3d4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78cc; op2val:0xba89; +op3val:0x77d4; valaddr_reg:x1; val_offset:2688*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2688*FLEN/8, x2, x5, x6) + +inst_932: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0cc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x289 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3d4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78cc; op2val:0xba89; +op3val:0x77d4; valaddr_reg:x1; val_offset:2691*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2691*FLEN/8, x2, x5, x6) + +inst_933: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0cc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x289 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3d4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78cc; op2val:0xba89; +op3val:0x77d4; valaddr_reg:x1; val_offset:2694*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2694*FLEN/8, x2, x5, x6) + +inst_934: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0cc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x289 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3d4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78cc; op2val:0xba89; +op3val:0x77d4; valaddr_reg:x1; val_offset:2697*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2697*FLEN/8, x2, x5, x6) + +inst_935: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x381 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x265 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b81; op2val:0xb665; +op3val:0x75fc; valaddr_reg:x1; val_offset:2700*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2700*FLEN/8, x2, x5, x6) + +inst_936: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x381 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x265 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1fc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b81; op2val:0xb665; +op3val:0x75fc; valaddr_reg:x1; val_offset:2703*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2703*FLEN/8, x2, x5, x6) + +inst_937: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x381 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x265 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1fc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b81; op2val:0xb665; +op3val:0x75fc; valaddr_reg:x1; val_offset:2706*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2706*FLEN/8, x2, x5, x6) + +inst_938: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x381 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x265 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1fc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b81; op2val:0xb665; +op3val:0x75fc; valaddr_reg:x1; val_offset:2709*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2709*FLEN/8, x2, x5, x6) + +inst_939: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x381 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x265 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1fc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b81; op2val:0xb665; +op3val:0x75fc; valaddr_reg:x1; val_offset:2712*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2712*FLEN/8, x2, x5, x6) + +inst_940: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x322 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x242 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x193 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6b22; op2val:0xca42; +op3val:0x7993; valaddr_reg:x1; val_offset:2715*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2715*FLEN/8, x2, x5, x6) + +inst_941: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x322 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x242 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x193 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6b22; op2val:0xca42; +op3val:0x7993; valaddr_reg:x1; val_offset:2718*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2718*FLEN/8, x2, x5, x6) + +inst_942: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x322 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x242 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x193 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6b22; op2val:0xca42; +op3val:0x7993; valaddr_reg:x1; val_offset:2721*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2721*FLEN/8, x2, x5, x6) + +inst_943: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x322 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x242 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x193 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6b22; op2val:0xca42; +op3val:0x7993; valaddr_reg:x1; val_offset:2724*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2724*FLEN/8, x2, x5, x6) + +inst_944: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x322 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x242 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x193 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6b22; op2val:0xca42; +op3val:0x7993; valaddr_reg:x1; val_offset:2727*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2727*FLEN/8, x2, x5, x6) + +inst_945: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0d5 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x02b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x10c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70d5; op2val:0xc42b; +op3val:0x790c; valaddr_reg:x1; val_offset:2730*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2730*FLEN/8, x2, x5, x6) + +inst_946: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0d5 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x02b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x10c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70d5; op2val:0xc42b; +op3val:0x790c; valaddr_reg:x1; val_offset:2733*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2733*FLEN/8, x2, x5, x6) + +inst_947: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0d5 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x02b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x10c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70d5; op2val:0xc42b; +op3val:0x790c; valaddr_reg:x1; val_offset:2736*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2736*FLEN/8, x2, x5, x6) + +inst_948: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0d5 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x02b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x10c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70d5; op2val:0xc42b; +op3val:0x790c; valaddr_reg:x1; val_offset:2739*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2739*FLEN/8, x2, x5, x6) + +inst_949: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0d5 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x02b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x10c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70d5; op2val:0xc42b; +op3val:0x790c; valaddr_reg:x1; val_offset:2742*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2742*FLEN/8, x2, x5, x6) + +inst_950: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x331 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x347 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x780b; op2val:0xbf31; +op3val:0x7b47; valaddr_reg:x1; val_offset:2745*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2745*FLEN/8, x2, x5, x6) + +inst_951: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x331 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x347 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x780b; op2val:0xbf31; +op3val:0x7b47; valaddr_reg:x1; val_offset:2748*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2748*FLEN/8, x2, x5, x6) + +inst_952: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x331 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x347 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x780b; op2val:0xbf31; +op3val:0x7b47; valaddr_reg:x1; val_offset:2751*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2751*FLEN/8, x2, x5, x6) + +inst_953: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x331 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x347 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x780b; op2val:0xbf31; +op3val:0x7b47; valaddr_reg:x1; val_offset:2754*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2754*FLEN/8, x2, x5, x6) + +inst_954: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x331 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x347 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x780b; op2val:0xbf31; +op3val:0x7b47; valaddr_reg:x1; val_offset:2757*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2757*FLEN/8, x2, x5, x6) + +inst_955: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x06f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x077 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0f6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x786f; op2val:0xbc77; +op3val:0x78f6; valaddr_reg:x1; val_offset:2760*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2760*FLEN/8, x2, x5, x6) + +inst_956: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x06f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x077 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0f6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x786f; op2val:0xbc77; +op3val:0x78f6; valaddr_reg:x1; val_offset:2763*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2763*FLEN/8, x2, x5, x6) + +inst_957: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x06f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x077 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0f6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x786f; op2val:0xbc77; +op3val:0x78f6; valaddr_reg:x1; val_offset:2766*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2766*FLEN/8, x2, x5, x6) + +inst_958: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x06f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x077 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0f6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x786f; op2val:0xbc77; +op3val:0x78f6; valaddr_reg:x1; val_offset:2769*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2769*FLEN/8, x2, x5, x6) + +inst_959: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x06f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x077 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0f6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x786f; op2val:0xbc77; +op3val:0x78f6; valaddr_reg:x1; val_offset:2772*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2772*FLEN/8, x2, x5, x6) + +inst_960: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x035 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x02f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x069 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7435; op2val:0xc02f; +op3val:0x7869; valaddr_reg:x1; val_offset:2775*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2775*FLEN/8, x2, x5, x6) + +inst_961: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x035 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x02f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x069 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7435; op2val:0xc02f; +op3val:0x7869; valaddr_reg:x1; val_offset:2778*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2778*FLEN/8, x2, x5, x6) + +inst_962: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x035 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x02f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x069 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7435; op2val:0xc02f; +op3val:0x7869; valaddr_reg:x1; val_offset:2781*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2781*FLEN/8, x2, x5, x6) + +inst_963: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x035 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x02f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x069 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7435; op2val:0xc02f; +op3val:0x7869; valaddr_reg:x1; val_offset:2784*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2784*FLEN/8, x2, x5, x6) + +inst_964: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x035 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x02f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x069 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7435; op2val:0xc02f; +op3val:0x7869; valaddr_reg:x1; val_offset:2787*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2787*FLEN/8, x2, x5, x6) + +inst_965: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x010 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7410; op2val:0xc1e5; +op3val:0x7a00; valaddr_reg:x1; val_offset:2790*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2790*FLEN/8, x2, x5, x6) + +inst_966: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x010 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x200 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7410; op2val:0xc1e5; +op3val:0x7a00; valaddr_reg:x1; val_offset:2793*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2793*FLEN/8, x2, x5, x6) + +inst_967: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x010 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x200 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7410; op2val:0xc1e5; +op3val:0x7a00; valaddr_reg:x1; val_offset:2796*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2796*FLEN/8, x2, x5, x6) + +inst_968: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x010 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x200 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7410; op2val:0xc1e5; +op3val:0x7a00; valaddr_reg:x1; val_offset:2799*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2799*FLEN/8, x2, x5, x6) + +inst_969: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x010 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x200 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7410; op2val:0xc1e5; +op3val:0x7a00; valaddr_reg:x1; val_offset:2802*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2802*FLEN/8, x2, x5, x6) + +inst_970: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x022 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x01c and fs3 == 0 and fe3 == 0x1c and fm3 == 0x047 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7822; op2val:0xb41c; +op3val:0x7047; valaddr_reg:x1; val_offset:2805*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2805*FLEN/8, x2, x5, x6) + +inst_971: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x022 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x01c and fs3 == 0 and fe3 == 0x1c and fm3 == 0x047 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7822; op2val:0xb41c; +op3val:0x7047; valaddr_reg:x1; val_offset:2808*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2808*FLEN/8, x2, x5, x6) + +inst_972: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x022 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x01c and fs3 == 0 and fe3 == 0x1c and fm3 == 0x047 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7822; op2val:0xb41c; +op3val:0x7047; valaddr_reg:x1; val_offset:2811*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2811*FLEN/8, x2, x5, x6) + +inst_973: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x022 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x01c and fs3 == 0 and fe3 == 0x1c and fm3 == 0x047 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7822; op2val:0xb41c; +op3val:0x7047; valaddr_reg:x1; val_offset:2814*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2814*FLEN/8, x2, x5, x6) + +inst_974: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x022 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x01c and fs3 == 0 and fe3 == 0x1c and fm3 == 0x047 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7822; op2val:0xb41c; +op3val:0x7047; valaddr_reg:x1; val_offset:2817*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2817*FLEN/8, x2, x5, x6) + +inst_975: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x37f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x251 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1ef and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x737f; op2val:0xbe51; +op3val:0x75ef; valaddr_reg:x1; val_offset:2820*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2820*FLEN/8, x2, x5, x6) + +inst_976: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x37f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x251 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1ef and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x737f; op2val:0xbe51; +op3val:0x75ef; valaddr_reg:x1; val_offset:2823*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2823*FLEN/8, x2, x5, x6) + +inst_977: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x37f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x251 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1ef and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x737f; op2val:0xbe51; +op3val:0x75ef; valaddr_reg:x1; val_offset:2826*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2826*FLEN/8, x2, x5, x6) + +inst_978: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x37f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x251 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1ef and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x737f; op2val:0xbe51; +op3val:0x75ef; valaddr_reg:x1; val_offset:2829*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2829*FLEN/8, x2, x5, x6) + +inst_979: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x37f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x251 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1ef and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x737f; op2val:0xbe51; +op3val:0x75ef; valaddr_reg:x1; val_offset:2832*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2832*FLEN/8, x2, x5, x6) + +inst_980: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1e4 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3c9 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x1bc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79e4; op2val:0xb3c9; +op3val:0x71bc; valaddr_reg:x1; val_offset:2835*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2835*FLEN/8, x2, x5, x6) + +inst_981: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1e4 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3c9 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x1bc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79e4; op2val:0xb3c9; +op3val:0x71bc; valaddr_reg:x1; val_offset:2838*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2838*FLEN/8, x2, x5, x6) + +inst_982: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1e4 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3c9 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x1bc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79e4; op2val:0xb3c9; +op3val:0x71bc; valaddr_reg:x1; val_offset:2841*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2841*FLEN/8, x2, x5, x6) + +inst_983: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1e4 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3c9 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x1bc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79e4; op2val:0xb3c9; +op3val:0x71bc; valaddr_reg:x1; val_offset:2844*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2844*FLEN/8, x2, x5, x6) + +inst_984: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1e4 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3c9 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x1bc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79e4; op2val:0xb3c9; +op3val:0x71bc; valaddr_reg:x1; val_offset:2847*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2847*FLEN/8, x2, x5, x6) + +inst_985: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x358 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x13c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79b4; op2val:0xbb58; +op3val:0x793c; valaddr_reg:x1; val_offset:2850*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2850*FLEN/8, x2, x5, x6) + +inst_986: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x358 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x13c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79b4; op2val:0xbb58; +op3val:0x793c; valaddr_reg:x1; val_offset:2853*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2853*FLEN/8, x2, x5, x6) + +inst_987: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x358 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x13c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79b4; op2val:0xbb58; +op3val:0x793c; valaddr_reg:x1; val_offset:2856*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2856*FLEN/8, x2, x5, x6) + +inst_988: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x358 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x13c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79b4; op2val:0xbb58; +op3val:0x793c; valaddr_reg:x1; val_offset:2859*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2859*FLEN/8, x2, x5, x6) + +inst_989: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x358 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x13c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79b4; op2val:0xbb58; +op3val:0x793c; valaddr_reg:x1; val_offset:2862*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2862*FLEN/8, x2, x5, x6) + +inst_990: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x174 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x3d5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x157 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d74; op2val:0xc7d5; +op3val:0x7957; valaddr_reg:x1; val_offset:2865*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2865*FLEN/8, x2, x5, x6) + +inst_991: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x174 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x3d5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x157 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d74; op2val:0xc7d5; +op3val:0x7957; valaddr_reg:x1; val_offset:2868*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2868*FLEN/8, x2, x5, x6) + +inst_992: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x174 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x3d5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x157 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d74; op2val:0xc7d5; +op3val:0x7957; valaddr_reg:x1; val_offset:2871*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2871*FLEN/8, x2, x5, x6) + +inst_993: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x174 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x3d5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x157 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d74; op2val:0xc7d5; +op3val:0x7957; valaddr_reg:x1; val_offset:2874*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2874*FLEN/8, x2, x5, x6) + +inst_994: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x174 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x3d5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x157 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d74; op2val:0xc7d5; +op3val:0x7957; valaddr_reg:x1; val_offset:2877*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2877*FLEN/8, x2, x5, x6) + +inst_995: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1d5 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x179 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x3fb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dd5; op2val:0xbd79; +op3val:0x6ffb; valaddr_reg:x1; val_offset:2880*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2880*FLEN/8, x2, x5, x6) + +inst_996: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1d5 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x179 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x3fb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dd5; op2val:0xbd79; +op3val:0x6ffb; valaddr_reg:x1; val_offset:2883*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2883*FLEN/8, x2, x5, x6) + +inst_997: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1d5 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x179 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x3fb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dd5; op2val:0xbd79; +op3val:0x6ffb; valaddr_reg:x1; val_offset:2886*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2886*FLEN/8, x2, x5, x6) + +inst_998: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1d5 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x179 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x3fb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dd5; op2val:0xbd79; +op3val:0x6ffb; valaddr_reg:x1; val_offset:2889*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2889*FLEN/8, x2, x5, x6) + +inst_999: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1d5 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x179 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x3fb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dd5; op2val:0xbd79; +op3val:0x6ffb; valaddr_reg:x1; val_offset:2892*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2892*FLEN/8, x2, x5, x6) + +inst_1000: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0bf and fs2 == 1 and fe2 == 0x0d and fm2 == 0x26d and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3a1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78bf; op2val:0xb66d; +op3val:0x73a1; valaddr_reg:x1; val_offset:2895*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2895*FLEN/8, x2, x5, x6) + +inst_1001: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0bf and fs2 == 1 and fe2 == 0x0d and fm2 == 0x26d and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3a1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78bf; op2val:0xb66d; +op3val:0x73a1; valaddr_reg:x1; val_offset:2898*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2898*FLEN/8, x2, x5, x6) + +inst_1002: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0bf and fs2 == 1 and fe2 == 0x0d and fm2 == 0x26d and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3a1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78bf; op2val:0xb66d; +op3val:0x73a1; valaddr_reg:x1; val_offset:2901*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2901*FLEN/8, x2, x5, x6) + +inst_1003: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0bf and fs2 == 1 and fe2 == 0x0d and fm2 == 0x26d and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3a1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78bf; op2val:0xb66d; +op3val:0x73a1; valaddr_reg:x1; val_offset:2904*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2904*FLEN/8, x2, x5, x6) + +inst_1004: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0bf and fs2 == 1 and fe2 == 0x0d and fm2 == 0x26d and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3a1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78bf; op2val:0xb66d; +op3val:0x73a1; valaddr_reg:x1; val_offset:2907*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2907*FLEN/8, x2, x5, x6) + +inst_1005: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x303 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x062 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3af and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b03; op2val:0xb862; +op3val:0x77af; valaddr_reg:x1; val_offset:2910*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2910*FLEN/8, x2, x5, x6) + +inst_1006: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x303 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x062 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3af and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b03; op2val:0xb862; +op3val:0x77af; valaddr_reg:x1; val_offset:2913*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2913*FLEN/8, x2, x5, x6) + +inst_1007: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x303 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x062 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3af and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b03; op2val:0xb862; +op3val:0x77af; valaddr_reg:x1; val_offset:2916*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2916*FLEN/8, x2, x5, x6) + +inst_1008: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x303 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x062 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3af and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b03; op2val:0xb862; +op3val:0x77af; valaddr_reg:x1; val_offset:2919*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2919*FLEN/8, x2, x5, x6) + +inst_1009: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x303 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x062 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3af and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b03; op2val:0xb862; +op3val:0x77af; valaddr_reg:x1; val_offset:2922*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2922*FLEN/8, x2, x5, x6) + +inst_1010: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x12b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ed and fs3 == 0 and fe3 == 0x1e and fm3 == 0x25e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x752b; op2val:0xc0ed; +op3val:0x7a5e; valaddr_reg:x1; val_offset:2925*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2925*FLEN/8, x2, x5, x6) + +inst_1011: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x12b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ed and fs3 == 0 and fe3 == 0x1e and fm3 == 0x25e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x752b; op2val:0xc0ed; +op3val:0x7a5e; valaddr_reg:x1; val_offset:2928*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2928*FLEN/8, x2, x5, x6) + +inst_1012: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x12b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ed and fs3 == 0 and fe3 == 0x1e and fm3 == 0x25e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x752b; op2val:0xc0ed; +op3val:0x7a5e; valaddr_reg:x1; val_offset:2931*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2931*FLEN/8, x2, x5, x6) + +inst_1013: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x12b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ed and fs3 == 0 and fe3 == 0x1e and fm3 == 0x25e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x752b; op2val:0xc0ed; +op3val:0x7a5e; valaddr_reg:x1; val_offset:2934*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2934*FLEN/8, x2, x5, x6) + +inst_1014: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x12b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ed and fs3 == 0 and fe3 == 0x1e and fm3 == 0x25e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x752b; op2val:0xc0ed; +op3val:0x7a5e; valaddr_reg:x1; val_offset:2937*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2937*FLEN/8, x2, x5, x6) + +inst_1015: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x38a and fs2 == 1 and fe2 == 0x13 and fm2 == 0x226 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1cc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x678a; op2val:0xce26; +op3val:0x79cc; valaddr_reg:x1; val_offset:2940*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2940*FLEN/8, x2, x5, x6) + +inst_1016: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x38a and fs2 == 1 and fe2 == 0x13 and fm2 == 0x226 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1cc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x678a; op2val:0xce26; +op3val:0x79cc; valaddr_reg:x1; val_offset:2943*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2943*FLEN/8, x2, x5, x6) + +inst_1017: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x38a and fs2 == 1 and fe2 == 0x13 and fm2 == 0x226 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1cc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x678a; op2val:0xce26; +op3val:0x79cc; valaddr_reg:x1; val_offset:2946*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2946*FLEN/8, x2, x5, x6) + +inst_1018: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x38a and fs2 == 1 and fe2 == 0x13 and fm2 == 0x226 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1cc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x678a; op2val:0xce26; +op3val:0x79cc; valaddr_reg:x1; val_offset:2949*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2949*FLEN/8, x2, x5, x6) + +inst_1019: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x38a and fs2 == 1 and fe2 == 0x13 and fm2 == 0x226 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1cc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x678a; op2val:0xce26; +op3val:0x79cc; valaddr_reg:x1; val_offset:2952*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2952*FLEN/8, x2, x5, x6) + +inst_1020: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x2dd and fs2 == 1 and fe2 == 0x10 and fm2 == 0x19e and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6add; op2val:0xc19e; +op3val:0x70d2; valaddr_reg:x1; val_offset:2955*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2955*FLEN/8, x2, x5, x6) + +inst_1021: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x2dd and fs2 == 1 and fe2 == 0x10 and fm2 == 0x19e and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6add; op2val:0xc19e; +op3val:0x70d2; valaddr_reg:x1; val_offset:2958*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2958*FLEN/8, x2, x5, x6) + +inst_1022: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x2dd and fs2 == 1 and fe2 == 0x10 and fm2 == 0x19e and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6add; op2val:0xc19e; +op3val:0x70d2; valaddr_reg:x1; val_offset:2961*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2961*FLEN/8, x2, x5, x6) + +inst_1023: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x2dd and fs2 == 1 and fe2 == 0x10 and fm2 == 0x19e and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6add; op2val:0xc19e; +op3val:0x70d2; valaddr_reg:x1; val_offset:2964*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2964*FLEN/8, x2, x5, x6) + +inst_1024: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x2dd and fs2 == 1 and fe2 == 0x10 and fm2 == 0x19e and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6add; op2val:0xc19e; +op3val:0x70d2; valaddr_reg:x1; val_offset:2967*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2967*FLEN/8, x2, x5, x6) + +inst_1025: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x39c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1b9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x172 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b9c; op2val:0xb9b9; +op3val:0x7972; valaddr_reg:x1; val_offset:2970*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2970*FLEN/8, x2, x5, x6) + +inst_1026: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x39c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1b9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x172 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b9c; op2val:0xb9b9; +op3val:0x7972; valaddr_reg:x1; val_offset:2973*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2973*FLEN/8, x2, x5, x6) + +inst_1027: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x39c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1b9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x172 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b9c; op2val:0xb9b9; +op3val:0x7972; valaddr_reg:x1; val_offset:2976*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2976*FLEN/8, x2, x5, x6) + +inst_1028: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x39c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1b9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x172 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b9c; op2val:0xb9b9; +op3val:0x7972; valaddr_reg:x1; val_offset:2979*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2979*FLEN/8, x2, x5, x6) + +inst_1029: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x39c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1b9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x172 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b9c; op2val:0xb9b9; +op3val:0x7972; valaddr_reg:x1; val_offset:2982*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2982*FLEN/8, x2, x5, x6) + +inst_1030: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x322 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x029 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x36d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7322; op2val:0xb829; +op3val:0x6f6d; valaddr_reg:x1; val_offset:2985*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2985*FLEN/8, x2, x5, x6) + +inst_1031: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x322 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x029 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x36d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7322; op2val:0xb829; +op3val:0x6f6d; valaddr_reg:x1; val_offset:2988*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2988*FLEN/8, x2, x5, x6) + +inst_1032: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x322 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x029 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x36d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7322; op2val:0xb829; +op3val:0x6f6d; valaddr_reg:x1; val_offset:2991*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2991*FLEN/8, x2, x5, x6) + +inst_1033: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x322 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x029 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x36d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7322; op2val:0xb829; +op3val:0x6f6d; valaddr_reg:x1; val_offset:2994*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2994*FLEN/8, x2, x5, x6) + +inst_1034: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x322 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x029 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x36d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7322; op2val:0xb829; +op3val:0x6f6d; valaddr_reg:x1; val_offset:2997*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2997*FLEN/8, x2, x5, x6) + +inst_1035: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x178 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x151 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bc7; op2val:0xb978; +op3val:0x7951; valaddr_reg:x1; val_offset:3000*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3000*FLEN/8, x2, x5, x6) + +inst_1036: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x178 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x151 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bc7; op2val:0xb978; +op3val:0x7951; valaddr_reg:x1; val_offset:3003*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3003*FLEN/8, x2, x5, x6) + +inst_1037: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x178 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x151 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bc7; op2val:0xb978; +op3val:0x7951; valaddr_reg:x1; val_offset:3006*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3006*FLEN/8, x2, x5, x6) + +inst_1038: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x178 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x151 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bc7; op2val:0xb978; +op3val:0x7951; valaddr_reg:x1; val_offset:3009*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3009*FLEN/8, x2, x5, x6) + +inst_1039: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x178 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x151 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bc7; op2val:0xb978; +op3val:0x7951; valaddr_reg:x1; val_offset:3012*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3012*FLEN/8, x2, x5, x6) + +inst_1040: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x173 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x078 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8f; op2val:0xb173; +op3val:0x7078; valaddr_reg:x1; val_offset:3015*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3015*FLEN/8, x2, x5, x6) + +inst_1041: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x173 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x078 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8f; op2val:0xb173; +op3val:0x7078; valaddr_reg:x1; val_offset:3018*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3018*FLEN/8, x2, x5, x6) + +inst_1042: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x173 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x078 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8f; op2val:0xb173; +op3val:0x7078; valaddr_reg:x1; val_offset:3021*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3021*FLEN/8, x2, x5, x6) + +inst_1043: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x173 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x078 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8f; op2val:0xb173; +op3val:0x7078; valaddr_reg:x1; val_offset:3024*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3024*FLEN/8, x2, x5, x6) + +inst_1044: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x173 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x078 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8f; op2val:0xb173; +op3val:0x7078; valaddr_reg:x1; val_offset:3027*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3027*FLEN/8, x2, x5, x6) + +inst_1045: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fe and fs2 == 1 and fe2 == 0x0e and fm2 == 0x089 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fe; op2val:0xb889; +op3val:0x75aa; valaddr_reg:x1; val_offset:3030*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3030*FLEN/8, x2, x5, x6) + +inst_1046: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fe and fs2 == 1 and fe2 == 0x0e and fm2 == 0x089 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1aa and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fe; op2val:0xb889; +op3val:0x75aa; valaddr_reg:x1; val_offset:3033*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3033*FLEN/8, x2, x5, x6) + +inst_1047: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fe and fs2 == 1 and fe2 == 0x0e and fm2 == 0x089 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1aa and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fe; op2val:0xb889; +op3val:0x75aa; valaddr_reg:x1; val_offset:3036*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3036*FLEN/8, x2, x5, x6) + +inst_1048: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fe and fs2 == 1 and fe2 == 0x0e and fm2 == 0x089 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1aa and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fe; op2val:0xb889; +op3val:0x75aa; valaddr_reg:x1; val_offset:3039*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3039*FLEN/8, x2, x5, x6) + +inst_1049: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fe and fs2 == 1 and fe2 == 0x0e and fm2 == 0x089 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1aa and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fe; op2val:0xb889; +op3val:0x75aa; valaddr_reg:x1; val_offset:3042*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3042*FLEN/8, x2, x5, x6) + +inst_1050: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x384 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1ac and fs3 == 0 and fe3 == 0x1d and fm3 == 0x154 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7384; op2val:0xbdac; +op3val:0x7554; valaddr_reg:x1; val_offset:3045*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3045*FLEN/8, x2, x5, x6) + +inst_1051: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x384 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1ac and fs3 == 0 and fe3 == 0x1d and fm3 == 0x154 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7384; op2val:0xbdac; +op3val:0x7554; valaddr_reg:x1; val_offset:3048*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3048*FLEN/8, x2, x5, x6) +RVTEST_SIGBASE(x5,signature_x5_8) + +inst_1052: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x384 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1ac and fs3 == 0 and fe3 == 0x1d and fm3 == 0x154 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7384; op2val:0xbdac; +op3val:0x7554; valaddr_reg:x1; val_offset:3051*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3051*FLEN/8, x2, x5, x6) + +inst_1053: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x384 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1ac and fs3 == 0 and fe3 == 0x1d and fm3 == 0x154 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7384; op2val:0xbdac; +op3val:0x7554; valaddr_reg:x1; val_offset:3054*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3054*FLEN/8, x2, x5, x6) + +inst_1054: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x384 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1ac and fs3 == 0 and fe3 == 0x1d and fm3 == 0x154 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7384; op2val:0xbdac; +op3val:0x7554; valaddr_reg:x1; val_offset:3057*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3057*FLEN/8, x2, x5, x6) + +inst_1055: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x08b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x193 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e8; op2val:0xb88b; +op3val:0x7593; valaddr_reg:x1; val_offset:3060*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3060*FLEN/8, x2, x5, x6) + +inst_1056: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x08b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x193 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e8; op2val:0xb88b; +op3val:0x7593; valaddr_reg:x1; val_offset:3063*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3063*FLEN/8, x2, x5, x6) + +inst_1057: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x08b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x193 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e8; op2val:0xb88b; +op3val:0x7593; valaddr_reg:x1; val_offset:3066*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3066*FLEN/8, x2, x5, x6) + +inst_1058: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x08b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x193 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e8; op2val:0xb88b; +op3val:0x7593; valaddr_reg:x1; val_offset:3069*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3069*FLEN/8, x2, x5, x6) + +inst_1059: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x08b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x193 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e8; op2val:0xb88b; +op3val:0x7593; valaddr_reg:x1; val_offset:3072*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3072*FLEN/8, x2, x5, x6) + +inst_1060: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x22b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1a8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x05d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x762b; op2val:0xb5a8; +op3val:0x705d; valaddr_reg:x1; val_offset:3075*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3075*FLEN/8, x2, x5, x6) + +inst_1061: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x22b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1a8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x05d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x762b; op2val:0xb5a8; +op3val:0x705d; valaddr_reg:x1; val_offset:3078*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3078*FLEN/8, x2, x5, x6) + +inst_1062: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x22b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1a8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x05d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x762b; op2val:0xb5a8; +op3val:0x705d; valaddr_reg:x1; val_offset:3081*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3081*FLEN/8, x2, x5, x6) + +inst_1063: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x22b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1a8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x05d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x762b; op2val:0xb5a8; +op3val:0x705d; valaddr_reg:x1; val_offset:3084*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3084*FLEN/8, x2, x5, x6) + +inst_1064: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x22b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1a8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x05d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x762b; op2val:0xb5a8; +op3val:0x705d; valaddr_reg:x1; val_offset:3087*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3087*FLEN/8, x2, x5, x6) + +inst_1065: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x23c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x12e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aa5; op2val:0xba3c; +op3val:0x792e; valaddr_reg:x1; val_offset:3090*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3090*FLEN/8, x2, x5, x6) + +inst_1066: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x23c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x12e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aa5; op2val:0xba3c; +op3val:0x792e; valaddr_reg:x1; val_offset:3093*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3093*FLEN/8, x2, x5, x6) + +inst_1067: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x23c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x12e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aa5; op2val:0xba3c; +op3val:0x792e; valaddr_reg:x1; val_offset:3096*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3096*FLEN/8, x2, x5, x6) + +inst_1068: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x23c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x12e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aa5; op2val:0xba3c; +op3val:0x792e; valaddr_reg:x1; val_offset:3099*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3099*FLEN/8, x2, x5, x6) + +inst_1069: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x23c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x12e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aa5; op2val:0xba3c; +op3val:0x792e; valaddr_reg:x1; val_offset:3102*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3102*FLEN/8, x2, x5, x6) + +inst_1070: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x04f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2ee and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a6e; op2val:0xb84f; +op3val:0x76ee; valaddr_reg:x1; val_offset:3105*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3105*FLEN/8, x2, x5, x6) + +inst_1071: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x04f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2ee and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a6e; op2val:0xb84f; +op3val:0x76ee; valaddr_reg:x1; val_offset:3108*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3108*FLEN/8, x2, x5, x6) + +inst_1072: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x04f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2ee and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a6e; op2val:0xb84f; +op3val:0x76ee; valaddr_reg:x1; val_offset:3111*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3111*FLEN/8, x2, x5, x6) + +inst_1073: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x04f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2ee and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a6e; op2val:0xb84f; +op3val:0x76ee; valaddr_reg:x1; val_offset:3114*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3114*FLEN/8, x2, x5, x6) + +inst_1074: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x04f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2ee and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a6e; op2val:0xb84f; +op3val:0x76ee; valaddr_reg:x1; val_offset:3117*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3117*FLEN/8, x2, x5, x6) + +inst_1075: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2cf and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0dc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x023 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7acf; op2val:0xb8dc; +op3val:0x7823; valaddr_reg:x1; val_offset:3120*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3120*FLEN/8, x2, x5, x6) + +inst_1076: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2cf and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0dc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x023 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7acf; op2val:0xb8dc; +op3val:0x7823; valaddr_reg:x1; val_offset:3123*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3123*FLEN/8, x2, x5, x6) + +inst_1077: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2cf and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0dc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x023 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7acf; op2val:0xb8dc; +op3val:0x7823; valaddr_reg:x1; val_offset:3126*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3126*FLEN/8, x2, x5, x6) + +inst_1078: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2cf and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0dc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x023 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7acf; op2val:0xb8dc; +op3val:0x7823; valaddr_reg:x1; val_offset:3129*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3129*FLEN/8, x2, x5, x6) + +inst_1079: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2cf and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0dc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x023 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7acf; op2val:0xb8dc; +op3val:0x7823; valaddr_reg:x1; val_offset:3132*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3132*FLEN/8, x2, x5, x6) + +inst_1080: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0bd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3bd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x095 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78bd; op2val:0xbbbd; +op3val:0x7895; valaddr_reg:x1; val_offset:3135*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3135*FLEN/8, x2, x5, x6) + +inst_1081: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0bd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3bd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x095 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78bd; op2val:0xbbbd; +op3val:0x7895; valaddr_reg:x1; val_offset:3138*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3138*FLEN/8, x2, x5, x6) + +inst_1082: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0bd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3bd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x095 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78bd; op2val:0xbbbd; +op3val:0x7895; valaddr_reg:x1; val_offset:3141*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3141*FLEN/8, x2, x5, x6) + +inst_1083: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0bd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3bd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x095 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78bd; op2val:0xbbbd; +op3val:0x7895; valaddr_reg:x1; val_offset:3144*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3144*FLEN/8, x2, x5, x6) + +inst_1084: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0bd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3bd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x095 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78bd; op2val:0xbbbd; +op3val:0x7895; valaddr_reg:x1; val_offset:3147*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3147*FLEN/8, x2, x5, x6) + +inst_1085: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1eb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x046 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x253 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79eb; op2val:0xb846; +op3val:0x7653; valaddr_reg:x1; val_offset:3150*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3150*FLEN/8, x2, x5, x6) + +inst_1086: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1eb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x046 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x253 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79eb; op2val:0xb846; +op3val:0x7653; valaddr_reg:x1; val_offset:3153*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3153*FLEN/8, x2, x5, x6) + +inst_1087: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1eb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x046 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x253 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79eb; op2val:0xb846; +op3val:0x7653; valaddr_reg:x1; val_offset:3156*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3156*FLEN/8, x2, x5, x6) + +inst_1088: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1eb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x046 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x253 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79eb; op2val:0xb846; +op3val:0x7653; valaddr_reg:x1; val_offset:3159*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3159*FLEN/8, x2, x5, x6) + +inst_1089: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1eb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x046 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x253 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79eb; op2val:0xb846; +op3val:0x7653; valaddr_reg:x1; val_offset:3162*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3162*FLEN/8, x2, x5, x6) + +inst_1090: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x234 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x178 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x03e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e34; op2val:0xb578; +op3val:0x683e; valaddr_reg:x1; val_offset:3165*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3165*FLEN/8, x2, x5, x6) + +inst_1091: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x234 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x178 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x03e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e34; op2val:0xb578; +op3val:0x683e; valaddr_reg:x1; val_offset:3168*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3168*FLEN/8, x2, x5, x6) + +inst_1092: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x234 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x178 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x03e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e34; op2val:0xb578; +op3val:0x683e; valaddr_reg:x1; val_offset:3171*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3171*FLEN/8, x2, x5, x6) + +inst_1093: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x234 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x178 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x03e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e34; op2val:0xb578; +op3val:0x683e; valaddr_reg:x1; val_offset:3174*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3174*FLEN/8, x2, x5, x6) + +inst_1094: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x234 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x178 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x03e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e34; op2val:0xb578; +op3val:0x683e; valaddr_reg:x1; val_offset:3177*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3177*FLEN/8, x2, x5, x6) + +inst_1095: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x279 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x23d and fs3 == 0 and fe3 == 0x1a and fm3 == 0x10c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7279; op2val:0xb23d; +op3val:0x690c; valaddr_reg:x1; val_offset:3180*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3180*FLEN/8, x2, x5, x6) + +inst_1096: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x279 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x23d and fs3 == 0 and fe3 == 0x1a and fm3 == 0x10c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7279; op2val:0xb23d; +op3val:0x690c; valaddr_reg:x1; val_offset:3183*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3183*FLEN/8, x2, x5, x6) + +inst_1097: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x279 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x23d and fs3 == 0 and fe3 == 0x1a and fm3 == 0x10c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7279; op2val:0xb23d; +op3val:0x690c; valaddr_reg:x1; val_offset:3186*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3186*FLEN/8, x2, x5, x6) + +inst_1098: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x279 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x23d and fs3 == 0 and fe3 == 0x1a and fm3 == 0x10c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7279; op2val:0xb23d; +op3val:0x690c; valaddr_reg:x1; val_offset:3189*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3189*FLEN/8, x2, x5, x6) + +inst_1099: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x279 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x23d and fs3 == 0 and fe3 == 0x1a and fm3 == 0x10c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7279; op2val:0xb23d; +op3val:0x690c; valaddr_reg:x1; val_offset:3192*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3192*FLEN/8, x2, x5, x6) + +inst_1100: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x31c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x053 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3b1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b1c; op2val:0xb853; +op3val:0x77b1; valaddr_reg:x1; val_offset:3195*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3195*FLEN/8, x2, x5, x6) + +inst_1101: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x31c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x053 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3b1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b1c; op2val:0xb853; +op3val:0x77b1; valaddr_reg:x1; val_offset:3198*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3198*FLEN/8, x2, x5, x6) + +inst_1102: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x31c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x053 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3b1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b1c; op2val:0xb853; +op3val:0x77b1; valaddr_reg:x1; val_offset:3201*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3201*FLEN/8, x2, x5, x6) + +inst_1103: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x31c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x053 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3b1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b1c; op2val:0xb853; +op3val:0x77b1; valaddr_reg:x1; val_offset:3204*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3204*FLEN/8, x2, x5, x6) + +inst_1104: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x31c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x053 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3b1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b1c; op2val:0xb853; +op3val:0x77b1; valaddr_reg:x1; val_offset:3207*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3207*FLEN/8, x2, x5, x6) + +inst_1105: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x214 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x0e5 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x373 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a14; op2val:0x90e5; +op3val:0x4f73; valaddr_reg:x1; val_offset:3210*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3210*FLEN/8, x2, x5, x6) + +inst_1106: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x214 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x0e5 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x373 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a14; op2val:0x90e5; +op3val:0x4f73; valaddr_reg:x1; val_offset:3213*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3213*FLEN/8, x2, x5, x6) + +inst_1107: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x214 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x0e5 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x373 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a14; op2val:0x90e5; +op3val:0x4f73; valaddr_reg:x1; val_offset:3216*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3216*FLEN/8, x2, x5, x6) + +inst_1108: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x214 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x0e5 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x373 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a14; op2val:0x90e5; +op3val:0x4f73; valaddr_reg:x1; val_offset:3219*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3219*FLEN/8, x2, x5, x6) + +inst_1109: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x214 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x0e5 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x373 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a14; op2val:0x90e5; +op3val:0x4f73; valaddr_reg:x1; val_offset:3222*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3222*FLEN/8, x2, x5, x6) + +inst_1110: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x384 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x391 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x31d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7784; op2val:0xbf91; +op3val:0x7b1d; valaddr_reg:x1; val_offset:3225*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3225*FLEN/8, x2, x5, x6) + +inst_1111: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x384 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x391 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x31d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7784; op2val:0xbf91; +op3val:0x7b1d; valaddr_reg:x1; val_offset:3228*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3228*FLEN/8, x2, x5, x6) + +inst_1112: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x384 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x391 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x31d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7784; op2val:0xbf91; +op3val:0x7b1d; valaddr_reg:x1; val_offset:3231*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3231*FLEN/8, x2, x5, x6) + +inst_1113: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x384 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x391 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x31d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7784; op2val:0xbf91; +op3val:0x7b1d; valaddr_reg:x1; val_offset:3234*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3234*FLEN/8, x2, x5, x6) + +inst_1114: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x384 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x391 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x31d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7784; op2val:0xbf91; +op3val:0x7b1d; valaddr_reg:x1; val_offset:3237*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3237*FLEN/8, x2, x5, x6) + +inst_1115: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0f4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x189 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2da and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78f4; op2val:0xb989; +op3val:0x76da; valaddr_reg:x1; val_offset:3240*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3240*FLEN/8, x2, x5, x6) + +inst_1116: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0f4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x189 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2da and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78f4; op2val:0xb989; +op3val:0x76da; valaddr_reg:x1; val_offset:3243*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3243*FLEN/8, x2, x5, x6) + +inst_1117: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0f4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x189 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2da and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78f4; op2val:0xb989; +op3val:0x76da; valaddr_reg:x1; val_offset:3246*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3246*FLEN/8, x2, x5, x6) + +inst_1118: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0f4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x189 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2da and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78f4; op2val:0xb989; +op3val:0x76da; valaddr_reg:x1; val_offset:3249*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3249*FLEN/8, x2, x5, x6) + +inst_1119: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0f4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x189 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2da and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78f4; op2val:0xb989; +op3val:0x76da; valaddr_reg:x1; val_offset:3252*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3252*FLEN/8, x2, x5, x6) + +inst_1120: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0c3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ee and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fb; op2val:0xbcc3; +op3val:0x79ee; valaddr_reg:x1; val_offset:3255*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3255*FLEN/8, x2, x5, x6) + +inst_1121: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0c3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ee and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fb; op2val:0xbcc3; +op3val:0x79ee; valaddr_reg:x1; val_offset:3258*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3258*FLEN/8, x2, x5, x6) + +inst_1122: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0c3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ee and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fb; op2val:0xbcc3; +op3val:0x79ee; valaddr_reg:x1; val_offset:3261*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3261*FLEN/8, x2, x5, x6) + +inst_1123: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0bd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x389 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5b; op2val:0xbcbd; +op3val:0x7b89; valaddr_reg:x1; val_offset:3264*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3264*FLEN/8, x2, x5, x6) + +inst_1124: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0bd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x389 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5b; op2val:0xbcbd; +op3val:0x7b89; valaddr_reg:x1; val_offset:3267*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3267*FLEN/8, x2, x5, x6) + +inst_1125: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0bd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x389 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5b; op2val:0xbcbd; +op3val:0x7b89; valaddr_reg:x1; val_offset:3270*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3270*FLEN/8, x2, x5, x6) + +inst_1126: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ea and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0fc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x360 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79ea; op2val:0xbcfc; +op3val:0x7b60; valaddr_reg:x1; val_offset:3273*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3273*FLEN/8, x2, x5, x6) + +inst_1127: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ea and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0fc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x360 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79ea; op2val:0xbcfc; +op3val:0x7b60; valaddr_reg:x1; val_offset:3276*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3276*FLEN/8, x2, x5, x6) + +inst_1128: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ea and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0fc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x360 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79ea; op2val:0xbcfc; +op3val:0x7b60; valaddr_reg:x1; val_offset:3279*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3279*FLEN/8, x2, x5, x6) + +inst_1129: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x38b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x180 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x130 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b8b; op2val:0xb980; +op3val:0x7930; valaddr_reg:x1; val_offset:3282*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3282*FLEN/8, x2, x5, x6) + +inst_1130: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x334 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x005 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x33e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b34; op2val:0xb005; +op3val:0x6f3e; valaddr_reg:x1; val_offset:3285*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3285*FLEN/8, x2, x5, x6) + +inst_1131: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x380 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x034 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3e3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7780; op2val:0xb834; +op3val:0x73e3; valaddr_reg:x1; val_offset:3288*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3288*FLEN/8, x2, x5, x6) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(30971,32,FLEN) +NAN_BOXED(30971,16,FLEN) +NAN_BOXED(31214,32,FLEN) +NAN_BOXED(30971,32,FLEN) +NAN_BOXED(48323,16,FLEN) +NAN_BOXED(30971,32,FLEN) +NAN_BOXED(30971,32,FLEN) +NAN_BOXED(48323,16,FLEN) +NAN_BOXED(31214,32,FLEN) +NAN_BOXED(30971,32,FLEN) +NAN_BOXED(30971,16,FLEN) +NAN_BOXED(30971,32,FLEN) +NAN_BOXED(30971,32,FLEN) +NAN_BOXED(48323,16,FLEN) +NAN_BOXED(31214,32,FLEN) +NAN_BOXED(31323,32,FLEN) +NAN_BOXED(48317,16,FLEN) +NAN_BOXED(31625,32,FLEN) +NAN_BOXED(31323,32,FLEN) +NAN_BOXED(48317,16,FLEN) +NAN_BOXED(31625,32,FLEN) +NAN_BOXED(31323,32,FLEN) +NAN_BOXED(48317,16,FLEN) +NAN_BOXED(48317,32,FLEN) +NAN_BOXED(31323,32,FLEN) +NAN_BOXED(48317,16,FLEN) +NAN_BOXED(31323,32,FLEN) +NAN_BOXED(31323,32,FLEN) +NAN_BOXED(31323,16,FLEN) +NAN_BOXED(31323,32,FLEN) +NAN_BOXED(31210,32,FLEN) +NAN_BOXED(48380,16,FLEN) +NAN_BOXED(48380,32,FLEN) +test_dataset_1: +NAN_BOXED(31210,32,FLEN) +NAN_BOXED(31210,16,FLEN) +NAN_BOXED(31584,32,FLEN) +NAN_BOXED(31210,32,FLEN) +NAN_BOXED(48380,16,FLEN) +NAN_BOXED(31584,32,FLEN) +NAN_BOXED(31210,32,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31584,32,FLEN) +NAN_BOXED(31210,32,FLEN) +NAN_BOXED(48380,16,FLEN) +NAN_BOXED(31584,32,FLEN) +NAN_BOXED(26476,32,FLEN) +NAN_BOXED(52226,16,FLEN) +NAN_BOXED(30578,32,FLEN) +NAN_BOXED(26476,32,FLEN) +NAN_BOXED(52226,16,FLEN) +NAN_BOXED(30578,32,FLEN) +NAN_BOXED(26476,32,FLEN) +NAN_BOXED(52226,16,FLEN) +NAN_BOXED(30578,32,FLEN) +NAN_BOXED(26476,32,FLEN) +NAN_BOXED(52226,16,FLEN) +NAN_BOXED(30578,32,FLEN) +NAN_BOXED(26476,32,FLEN) +NAN_BOXED(52226,16,FLEN) +NAN_BOXED(30578,32,FLEN) +NAN_BOXED(31627,32,FLEN) +NAN_BOXED(47488,16,FLEN) +NAN_BOXED(31024,32,FLEN) +NAN_BOXED(31627,32,FLEN) +NAN_BOXED(47488,16,FLEN) +NAN_BOXED(31024,32,FLEN) +NAN_BOXED(31627,32,FLEN) +NAN_BOXED(47488,16,FLEN) +NAN_BOXED(31024,32,FLEN) +NAN_BOXED(31627,32,FLEN) +NAN_BOXED(47488,16,FLEN) +NAN_BOXED(31024,32,FLEN) +test_dataset_2: +NAN_BOXED(31627,32,FLEN) +NAN_BOXED(47488,16,FLEN) +NAN_BOXED(31024,32,FLEN) +NAN_BOXED(31540,32,FLEN) +NAN_BOXED(45061,16,FLEN) +NAN_BOXED(28478,32,FLEN) +NAN_BOXED(31540,32,FLEN) +NAN_BOXED(45061,16,FLEN) +NAN_BOXED(28478,32,FLEN) +NAN_BOXED(31540,32,FLEN) +NAN_BOXED(45061,16,FLEN) +NAN_BOXED(28478,32,FLEN) +NAN_BOXED(31540,32,FLEN) +NAN_BOXED(45061,16,FLEN) +NAN_BOXED(28478,32,FLEN) +NAN_BOXED(31540,32,FLEN) +NAN_BOXED(45061,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(47156,16,FLEN) +NAN_BOXED(29667,32,FLEN) +NAN_BOXED(30592,32,FLEN) +NAN_BOXED(47156,16,FLEN) +NAN_BOXED(29667,32,FLEN) +NAN_BOXED(30592,32,FLEN) +NAN_BOXED(47156,16,FLEN) +NAN_BOXED(29667,32,FLEN) +NAN_BOXED(30592,32,FLEN) +NAN_BOXED(47156,16,FLEN) +NAN_BOXED(29667,32,FLEN) +NAN_BOXED(30592,32,FLEN) +NAN_BOXED(47156,16,FLEN) +NAN_BOXED(29667,32,FLEN) +test_dataset_3: +NAN_BOXED(30809,16,FLEN) +NAN_BOXED(48184,16,FLEN) +NAN_BOXED(30870,16,FLEN) +NAN_BOXED(30809,16,FLEN) +NAN_BOXED(48184,16,FLEN) +NAN_BOXED(30870,16,FLEN) +NAN_BOXED(30809,16,FLEN) +NAN_BOXED(48184,16,FLEN) +NAN_BOXED(30870,16,FLEN) +NAN_BOXED(30809,16,FLEN) +NAN_BOXED(48184,16,FLEN) +NAN_BOXED(30870,16,FLEN) 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+NAN_BOXED(31516,16,FLEN) +NAN_BOXED(47187,16,FLEN) +NAN_BOXED(30641,16,FLEN) +NAN_BOXED(31516,16,FLEN) +NAN_BOXED(47187,16,FLEN) +NAN_BOXED(30641,16,FLEN) +NAN_BOXED(31252,16,FLEN) +NAN_BOXED(37093,16,FLEN) +NAN_BOXED(20339,16,FLEN) +NAN_BOXED(31252,16,FLEN) +NAN_BOXED(37093,16,FLEN) +NAN_BOXED(20339,16,FLEN) +NAN_BOXED(31252,16,FLEN) +NAN_BOXED(37093,16,FLEN) +NAN_BOXED(20339,16,FLEN) +NAN_BOXED(31252,16,FLEN) +NAN_BOXED(37093,16,FLEN) +NAN_BOXED(20339,16,FLEN) +NAN_BOXED(31252,16,FLEN) +NAN_BOXED(37093,16,FLEN) +NAN_BOXED(20339,16,FLEN) +NAN_BOXED(30596,16,FLEN) +NAN_BOXED(49041,16,FLEN) +NAN_BOXED(31517,16,FLEN) +NAN_BOXED(30596,16,FLEN) +NAN_BOXED(49041,16,FLEN) +NAN_BOXED(31517,16,FLEN) +NAN_BOXED(30596,16,FLEN) +NAN_BOXED(49041,16,FLEN) +NAN_BOXED(31517,16,FLEN) +NAN_BOXED(30596,16,FLEN) +NAN_BOXED(49041,16,FLEN) +NAN_BOXED(31517,16,FLEN) +NAN_BOXED(30596,16,FLEN) +NAN_BOXED(49041,16,FLEN) +NAN_BOXED(31517,16,FLEN) +NAN_BOXED(30964,16,FLEN) +NAN_BOXED(47497,16,FLEN) +NAN_BOXED(30426,16,FLEN) +NAN_BOXED(30964,16,FLEN) +NAN_BOXED(47497,16,FLEN) +NAN_BOXED(30426,16,FLEN) +NAN_BOXED(30964,16,FLEN) +NAN_BOXED(47497,16,FLEN) +NAN_BOXED(30426,16,FLEN) +NAN_BOXED(30964,16,FLEN) +NAN_BOXED(47497,16,FLEN) +NAN_BOXED(30426,16,FLEN) +NAN_BOXED(30964,16,FLEN) +NAN_BOXED(47497,16,FLEN) +NAN_BOXED(30426,16,FLEN) +NAN_BOXED(30971,16,FLEN) +NAN_BOXED(48323,16,FLEN) +NAN_BOXED(31214,16,FLEN) +NAN_BOXED(30971,16,FLEN) +NAN_BOXED(48323,16,FLEN) +NAN_BOXED(31214,16,FLEN) +NAN_BOXED(30971,16,FLEN) +NAN_BOXED(48323,16,FLEN) +NAN_BOXED(31214,16,FLEN) +NAN_BOXED(31323,16,FLEN) +NAN_BOXED(48317,16,FLEN) +NAN_BOXED(31625,16,FLEN) +NAN_BOXED(31323,16,FLEN) +NAN_BOXED(48317,16,FLEN) +NAN_BOXED(31625,16,FLEN) +NAN_BOXED(31323,16,FLEN) +NAN_BOXED(48317,16,FLEN) +NAN_BOXED(31625,16,FLEN) +NAN_BOXED(31210,16,FLEN) +NAN_BOXED(48380,16,FLEN) +NAN_BOXED(31584,16,FLEN) +NAN_BOXED(31210,16,FLEN) +NAN_BOXED(48380,16,FLEN) +NAN_BOXED(31584,16,FLEN) +NAN_BOXED(31210,16,FLEN) +NAN_BOXED(48380,16,FLEN) +NAN_BOXED(31584,16,FLEN) +NAN_BOXED(31627,16,FLEN) +NAN_BOXED(47488,16,FLEN) +NAN_BOXED(31024,16,FLEN) +NAN_BOXED(31540,16,FLEN) +NAN_BOXED(45061,16,FLEN) +NAN_BOXED(28478,16,FLEN) +NAN_BOXED(30592,16,FLEN) +NAN_BOXED(47156,16,FLEN) +NAN_BOXED(29667,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 26*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x3_0: + .fill 30*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x5_0: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x5_1: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x5_2: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x5_3: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x5_4: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x5_5: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x5_6: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x5_7: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x5_8: + .fill 160*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fmadd_b4-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fmadd_b4-01.S new file mode 100644 index 000000000..fe0497f04 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fmadd_b4-01.S @@ -0,0 +1,1614 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 04:10:09 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fmadd.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fmadd.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fmadd_b4 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fmadd_b4) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x4,signature_x4_1) + +inst_0: +// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==x23, rs2==x23, rs3==x22, rd==x16,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fb and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2a1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ee and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x23; op2:x23; op3:x22; dest:x16; op1val:0x78fb; op2val:0x78fb; +op3val:0x79ee; valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x16, x23, x23, x22, dyn, 0, 0, x3, 0*FLEN/8, x20, x4, x9) + +inst_1: +// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==x31, rs2==x17, rs3==x31, rd==x7,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fb and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2a1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ee and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x31; op2:x17; op3:x31; dest:x7; op1val:0x78fb; op2val:0x36a1; +op3val:0x78fb; valaddr_reg:x3; val_offset:3*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x7, x31, x17, x31, dyn, 32, 0, x3, 3*FLEN/8, x20, x4, x9) + +inst_2: +// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==x30, rs2==x7, rs3==x14, rd==x30,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fb and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2a1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ee and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x7; op3:x14; dest:x30; op1val:0x78fb; op2val:0x36a1; +op3val:0x79ee; valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x30, x30, x7, x14, dyn, 64, 0, x3, 6*FLEN/8, x20, x4, x9) + +inst_3: +// rs1 == rs2 == rs3 != rd, rs1==x27, rs2==x27, rs3==x27, rd==x2,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fb and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2a1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ee and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x27; op2:x27; op3:x27; dest:x2; op1val:0x78fb; op2val:0x78fb; +op3val:0x78fb; valaddr_reg:x3; val_offset:9*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x2, x27, x27, x27, dyn, 96, 0, x3, 9*FLEN/8, x20, x4, x9) + +inst_4: +// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==x10, rs2==x24, rs3==x5, rd==x5,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fb and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2a1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ee and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x10; op2:x24; op3:x5; dest:x5; op1val:0x78fb; op2val:0x36a1; +op3val:0x79ee; valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x5, x10, x24, x5, dyn, 128, 0, x3, 12*FLEN/8, x20, x4, x9) + +inst_5: +// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==x13, rs2==x0, rs3==x10, rd==x0,fs1 == 0 and fe1 == 0x1e and fm1 == 0x25b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0e2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x389 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x13; op2:x0; op3:x10; dest:x0; op1val:0x7a5b; op2val:0x0; +op3val:0x7b89; valaddr_reg:x3; val_offset:15*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x0, x13, x0, x10, dyn, 0, 0, x3, 15*FLEN/8, x20, x4, x9) + +inst_6: +// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==x0, rs2==x8, rs3==x13, rd==x23,fs1 == 0 and fe1 == 0x1e and fm1 == 0x25b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0e2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x389 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x0; op2:x8; op3:x13; dest:x23; op1val:0x0; op2val:0xc0e2; +op3val:0x7b89; valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x23, x0, x8, x13, dyn, 32, 0, x3, 18*FLEN/8, x20, x4, x9) + +inst_7: +// rd == rs2 == rs3 != rs1, rs1==x6, rs2==x1, rs3==x1, rd==x1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x25b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0e2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x389 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x6; op2:x1; op3:x1; dest:x1; op1val:0x7a5b; op2val:0xc0e2; +op3val:0xc0e2; valaddr_reg:x3; val_offset:21*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x1, x6, x1, x1, dyn, 64, 0, x3, 21*FLEN/8, x20, x4, x9) + +inst_8: +// rs1 == rd == rs3 != rs2, rs1==x12, rs2==x11, rs3==x12, rd==x12,fs1 == 0 and fe1 == 0x1e and fm1 == 0x25b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0e2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x389 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x12; op2:x11; op3:x12; dest:x12; op1val:0x7a5b; op2val:0xc0e2; +op3val:0x7a5b; valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x12, x12, x11, x12, dyn, 96, 0, x3, 24*FLEN/8, x20, x4, x9) + +inst_9: +// rs1 == rs2 == rs3 == rd, rs1==x18, rs2==x18, rs3==x18, rd==x18,fs1 == 0 and fe1 == 0x1e and fm1 == 0x25b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0e2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x389 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x18; op2:x18; op3:x18; dest:x18; op1val:0x7a5b; op2val:0x7a5b; +op3val:0x7a5b; valaddr_reg:x3; val_offset:27*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x18, x18, x18, x18, dyn, 128, 0, x3, 27*FLEN/8, x20, x4, x9) + +inst_10: +// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==x25, rs2==x15, rs3==x15, rd==x19,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ea and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2b7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x360 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x25; op2:x15; op3:x15; dest:x19; op1val:0x79ea; op2val:0x2eb7; +op3val:0x2eb7; valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x19, x25, x15, x15, dyn, 0, 0, x3, 30*FLEN/8, x20, x4, x9) + +inst_11: +// rs1 == rs2 == rd != rs3, rs1==x14, rs2==x14, rs3==x30, rd==x14,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ea and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2b7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x360 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x14; op2:x14; op3:x30; dest:x14; op1val:0x79ea; op2val:0x79ea; +op3val:0x7b60; valaddr_reg:x3; val_offset:33*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x14, x14, x14, x30, dyn, 32, 0, x3, 33*FLEN/8, x20, x4, x9) +RVTEST_VALBASEUPD(x13,test_dataset_1) + +inst_12: +// rs1==x21, rs2==x5, rs3==x16, rd==x3,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ea and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2b7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x360 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x21; op2:x5; op3:x16; dest:x3; op1val:0x79ea; op2val:0x2eb7; +op3val:0x7b60; valaddr_reg:x13; val_offset:0*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x3, x21, x5, x16, dyn, 64, 0, x13, 0*FLEN/8, x14, x4, x9) + +inst_13: +// rs1==x11, rs2==x31, rs3==x21, rd==x6,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ea and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2b7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x360 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x11; op2:x31; op3:x21; dest:x6; op1val:0x79ea; op2val:0x2eb7; +op3val:0x7b60; valaddr_reg:x13; val_offset:3*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x6, x11, x31, x21, dyn, 96, 0, x13, 3*FLEN/8, x14, x4, x1) + +inst_14: +// rs1==x19, rs2==x28, rs3==x4, rd==x11,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ea and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2b7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x360 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x19; op2:x28; op3:x4; dest:x11; op1val:0x79ea; op2val:0x2eb7; +op3val:0x7b60; valaddr_reg:x13; val_offset:6*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x11, x19, x28, x4, dyn, 128, 0, x13, 6*FLEN/8, x14, x4, x1) +RVTEST_SIGBASE(x2,signature_x2_0) + +inst_15: +// rs1==x26, rs2==x25, rs3==x3, rd==x22,fs1 == 0 and fe1 == 0x19 and fm1 == 0x36c and fs2 == 1 and fe2 == 0x14 and fm2 == 0x250 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x372 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x26; op2:x25; op3:x3; dest:x22; op1val:0x676c; op2val:0xd250; +op3val:0x7772; valaddr_reg:x13; val_offset:9*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x22, x26, x25, x3, dyn, 0, 0, x13, 9*FLEN/8, x14, x2, x1) + +inst_16: +// rs1==x5, rs2==x12, rs3==x8, rd==x9,fs1 == 0 and fe1 == 0x19 and fm1 == 0x36c and fs2 == 1 and fe2 == 0x14 and fm2 == 0x250 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x372 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x5; op2:x12; op3:x8; dest:x9; op1val:0x676c; op2val:0xd250; +op3val:0x7772; valaddr_reg:x13; val_offset:12*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x9, x5, x12, x8, dyn, 32, 0, x13, 12*FLEN/8, x14, x2, x1) + +inst_17: +// rs1==x16, rs2==x20, rs3==x7, rd==x8,fs1 == 0 and fe1 == 0x19 and fm1 == 0x36c and fs2 == 1 and fe2 == 0x14 and fm2 == 0x250 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x372 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x16; op2:x20; op3:x7; dest:x8; op1val:0x676c; op2val:0xd250; +op3val:0x7772; valaddr_reg:x13; val_offset:15*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x8, x16, x20, x7, dyn, 64, 0, x13, 15*FLEN/8, x14, x2, x1) + +inst_18: +// rs1==x20, rs2==x4, rs3==x26, rd==x25,fs1 == 0 and fe1 == 0x19 and fm1 == 0x36c and fs2 == 1 and fe2 == 0x14 and fm2 == 0x250 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x372 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x20; op2:x4; op3:x26; dest:x25; op1val:0x676c; op2val:0xd250; +op3val:0x7772; valaddr_reg:x13; val_offset:18*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x25, x20, x4, x26, dyn, 96, 0, x13, 18*FLEN/8, x14, x2, x1) + +inst_19: +// rs1==x9, rs2==x16, rs3==x11, rd==x17,fs1 == 0 and fe1 == 0x19 and fm1 == 0x36c and fs2 == 1 and fe2 == 0x14 and fm2 == 0x250 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x372 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x9; op2:x16; op3:x11; dest:x17; op1val:0x676c; op2val:0xd250; +op3val:0x7772; valaddr_reg:x13; val_offset:21*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x17, x9, x16, x11, dyn, 128, 0, x13, 21*FLEN/8, x14, x2, x1) + +inst_20: +// rs1==x7, rs2==x29, rs3==x2, rd==x27,fs1 == 0 and fe1 == 0x1e and fm1 == 0x38b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1f4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x130 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x7; op2:x29; op3:x2; dest:x27; op1val:0x7b8b; op2val:0x35f4; +op3val:0x7930; valaddr_reg:x13; val_offset:24*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x27, x7, x29, x2, dyn, 0, 0, x13, 24*FLEN/8, x14, x2, x1) + +inst_21: +// rs1==x15, rs2==x6, rs3==x28, rd==x10,fs1 == 0 and fe1 == 0x1e and fm1 == 0x38b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1f4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x130 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x15; op2:x6; op3:x28; dest:x10; op1val:0x7b8b; op2val:0x35f4; +op3val:0x7930; valaddr_reg:x13; val_offset:27*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x10, x15, x6, x28, dyn, 32, 0, x13, 27*FLEN/8, x14, x2, x1) +RVTEST_VALBASEUPD(x6,test_dataset_2) + +inst_22: +// rs1==x24, rs2==x26, rs3==x6, rd==x21,fs1 == 0 and fe1 == 0x1e and fm1 == 0x38b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1f4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x130 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x24; op2:x26; op3:x6; dest:x21; op1val:0x7b8b; op2val:0x35f4; +op3val:0x7930; valaddr_reg:x6; val_offset:0*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x21, x24, x26, x6, dyn, 64, 0, x6, 0*FLEN/8, x7, x2, x1) + +inst_23: +// rs1==x29, rs2==x10, rs3==x9, rd==x31,fs1 == 0 and fe1 == 0x1e and fm1 == 0x38b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1f4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x130 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x29; op2:x10; op3:x9; dest:x31; op1val:0x7b8b; op2val:0x35f4; +op3val:0x7930; valaddr_reg:x6; val_offset:3*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x29, x10, x9, dyn, 96, 0, x6, 3*FLEN/8, x7, x2, x1) + +inst_24: +// rs1==x3, rs2==x19, rs3==x24, rd==x26,fs1 == 0 and fe1 == 0x1e and fm1 == 0x38b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1f4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x130 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x3; op2:x19; op3:x24; dest:x26; op1val:0x7b8b; op2val:0x35f4; +op3val:0x7930; valaddr_reg:x6; val_offset:6*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x26, x3, x19, x24, dyn, 128, 0, x6, 6*FLEN/8, x7, x2, x1) + +inst_25: +// rs1==x1, rs2==x3, rs3==x25, rd==x24,fs1 == 0 and fe1 == 0x1e and fm1 == 0x334 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f1 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x33e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x1; op2:x3; op3:x25; dest:x24; op1val:0x7b34; op2val:0xbcf1; +op3val:0x6f3e; valaddr_reg:x6; val_offset:9*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x24, x1, x3, x25, dyn, 0, 0, x6, 9*FLEN/8, x7, x2, x5) + +inst_26: +// rs1==x8, rs2==x30, rs3==x17, rd==x29,fs1 == 0 and fe1 == 0x1e and fm1 == 0x334 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f1 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x33e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x8; op2:x30; op3:x17; dest:x29; op1val:0x7b34; op2val:0xbcf1; +op3val:0x6f3e; valaddr_reg:x6; val_offset:12*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x29, x8, x30, x17, dyn, 32, 0, x6, 12*FLEN/8, x7, x2, x5) + +inst_27: +// rs1==x22, rs2==x13, rs3==x23, rd==x4,fs1 == 0 and fe1 == 0x1e and fm1 == 0x334 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f1 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x33e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x22; op2:x13; op3:x23; dest:x4; op1val:0x7b34; op2val:0xbcf1; +op3val:0x6f3e; valaddr_reg:x6; val_offset:15*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x4, x22, x13, x23, dyn, 64, 0, x6, 15*FLEN/8, x7, x2, x5) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_28: +// rs1==x17, rs2==x22, rs3==x20, rd==x15,fs1 == 0 and fe1 == 0x1e and fm1 == 0x334 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f1 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x33e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x17; op2:x22; op3:x20; dest:x15; op1val:0x7b34; op2val:0xbcf1; +op3val:0x6f3e; valaddr_reg:x6; val_offset:18*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x15, x17, x22, x20, dyn, 96, 0, x6, 18*FLEN/8, x7, x1, x5) + +inst_29: +// rs1==x4, rs2==x2, rs3==x19, rd==x28,fs1 == 0 and fe1 == 0x1e and fm1 == 0x334 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f1 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x33e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x4; op2:x2; op3:x19; dest:x28; op1val:0x7b34; op2val:0xbcf1; +op3val:0x6f3e; valaddr_reg:x6; val_offset:21*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x28, x4, x2, x19, dyn, 128, 0, x6, 21*FLEN/8, x7, x1, x5) + +inst_30: +// rs1==x2, rs2==x9, rs3==x0, rd==x20,fs1 == 0 and fe1 == 0x1d and fm1 == 0x380 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x26c and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3e3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x2; op2:x9; op3:x0; dest:x20; op1val:0x7780; op2val:0x3e6c; +op3val:0x0; valaddr_reg:x6; val_offset:24*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x20, x2, x9, x0, dyn, 0, 0, x6, 24*FLEN/8, x7, x1, x5) + +inst_31: +// rs1==x28, rs2==x21, rs3==x29, rd==x13,fs1 == 0 and fe1 == 0x1d and fm1 == 0x380 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x26c and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3e3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x28; op2:x21; op3:x29; dest:x13; op1val:0x7780; op2val:0x3e6c; +op3val:0x73e3; valaddr_reg:x6; val_offset:27*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x13, x28, x21, x29, dyn, 32, 0, x6, 27*FLEN/8, x7, x1, x5) + +inst_32: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x380 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x26c and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3e3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7780; op2val:0x3e6c; +op3val:0x73e3; valaddr_reg:x6; val_offset:30*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x6, 30*FLEN/8, x7, x1, x5) + +inst_33: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x380 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x26c and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3e3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7780; op2val:0x3e6c; +op3val:0x73e3; valaddr_reg:x6; val_offset:33*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x6, 33*FLEN/8, x7, x1, x5) + +inst_34: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x380 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x26c and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3e3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7780; op2val:0x3e6c; +op3val:0x73e3; valaddr_reg:x6; val_offset:36*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x6, 36*FLEN/8, x7, x1, x5) + +inst_35: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x059 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1c9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x096 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7859; op2val:0xc1c9; +op3val:0x7896; valaddr_reg:x6; val_offset:39*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 39*FLEN/8, x7, x1, x5) + +inst_36: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x059 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1c9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x096 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7859; op2val:0xc1c9; +op3val:0x7896; valaddr_reg:x6; val_offset:42*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x6, 42*FLEN/8, x7, x1, x5) + +inst_37: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x059 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1c9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x096 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7859; op2val:0xc1c9; +op3val:0x7896; valaddr_reg:x6; val_offset:45*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x6, 45*FLEN/8, x7, x1, x5) + +inst_38: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x059 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1c9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x096 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7859; op2val:0xc1c9; +op3val:0x7896; valaddr_reg:x6; val_offset:48*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x6, 48*FLEN/8, x7, x1, x5) + +inst_39: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x059 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1c9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x096 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7859; op2val:0xc1c9; +op3val:0x7896; valaddr_reg:x6; val_offset:51*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x6, 51*FLEN/8, x7, x1, x5) + +inst_40: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x2b8 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x375 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2ee and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x62b8; op2val:0x5375; +op3val:0x72ee; valaddr_reg:x6; val_offset:54*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 54*FLEN/8, x7, x1, x5) + +inst_41: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x2b8 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x375 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2ee and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x62b8; op2val:0x5375; +op3val:0x72ee; valaddr_reg:x6; val_offset:57*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x6, 57*FLEN/8, x7, x1, x5) + +inst_42: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x2b8 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x375 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2ee and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x62b8; op2val:0x5375; +op3val:0x72ee; valaddr_reg:x6; val_offset:60*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x6, 60*FLEN/8, x7, x1, x5) + +inst_43: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x2b8 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x375 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2ee and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x62b8; op2val:0x5375; +op3val:0x72ee; valaddr_reg:x6; val_offset:63*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x6, 63*FLEN/8, x7, x1, x5) + +inst_44: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x2b8 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x375 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2ee and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x62b8; op2val:0x5375; +op3val:0x72ee; valaddr_reg:x6; val_offset:66*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x6, 66*FLEN/8, x7, x1, x5) + +inst_45: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x078 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2db and fs3 == 0 and fe3 == 0x1e and fm3 == 0x353 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7478; op2val:0xc6db; +op3val:0x7b53; valaddr_reg:x6; val_offset:69*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 69*FLEN/8, x7, x1, x5) + +inst_46: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x078 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2db and fs3 == 0 and fe3 == 0x1e and fm3 == 0x353 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7478; op2val:0xc6db; +op3val:0x7b53; valaddr_reg:x6; val_offset:72*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x6, 72*FLEN/8, x7, x1, x5) + +inst_47: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x078 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2db and fs3 == 0 and fe3 == 0x1e and fm3 == 0x353 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7478; op2val:0xc6db; +op3val:0x7b53; valaddr_reg:x6; val_offset:75*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x6, 75*FLEN/8, x7, x1, x5) + +inst_48: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x078 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2db and fs3 == 0 and fe3 == 0x1e and fm3 == 0x353 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7478; op2val:0xc6db; +op3val:0x7b53; valaddr_reg:x6; val_offset:78*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x6, 78*FLEN/8, x7, x1, x5) + +inst_49: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x078 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2db and fs3 == 0 and fe3 == 0x1e and fm3 == 0x353 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7478; op2val:0xc6db; +op3val:0x7b53; valaddr_reg:x6; val_offset:81*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x6, 81*FLEN/8, x7, x1, x5) + +inst_50: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x063 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x11a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a1f; op2val:0x3c63; +op3val:0x711a; valaddr_reg:x6; val_offset:84*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 84*FLEN/8, x7, x1, x5) + +inst_51: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x063 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x11a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a1f; op2val:0x3c63; +op3val:0x711a; valaddr_reg:x6; val_offset:87*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x6, 87*FLEN/8, x7, x1, x5) + +inst_52: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x063 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x11a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a1f; op2val:0x3c63; +op3val:0x711a; valaddr_reg:x6; val_offset:90*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x6, 90*FLEN/8, x7, x1, x5) + +inst_53: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x063 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x11a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a1f; op2val:0x3c63; +op3val:0x711a; valaddr_reg:x6; val_offset:93*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x6, 93*FLEN/8, x7, x1, x5) + +inst_54: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x063 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x11a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a1f; op2val:0x3c63; +op3val:0x711a; valaddr_reg:x6; val_offset:96*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x6, 96*FLEN/8, x7, x1, x5) + +inst_55: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1b6 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x070 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5f; op2val:0xbdb6; +op3val:0x7070; valaddr_reg:x6; val_offset:99*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 99*FLEN/8, x7, x1, x5) + +inst_56: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1b6 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x070 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5f; op2val:0xbdb6; +op3val:0x7070; valaddr_reg:x6; val_offset:102*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x6, 102*FLEN/8, x7, x1, x5) + +inst_57: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1b6 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x070 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5f; op2val:0xbdb6; +op3val:0x7070; valaddr_reg:x6; val_offset:105*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x6, 105*FLEN/8, x7, x1, x5) + +inst_58: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1b6 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x070 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5f; op2val:0xbdb6; +op3val:0x7070; valaddr_reg:x6; val_offset:108*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x6, 108*FLEN/8, x7, x1, x5) + +inst_59: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1b6 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x070 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5f; op2val:0xbdb6; +op3val:0x7070; valaddr_reg:x6; val_offset:111*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x6, 111*FLEN/8, x7, x1, x5) + +inst_60: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ef and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1a8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x00d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78ef; op2val:0x3da8; +op3val:0x700d; valaddr_reg:x6; val_offset:114*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 114*FLEN/8, x7, x1, x5) + +inst_61: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ef and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1a8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x00d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78ef; op2val:0x3da8; +op3val:0x700d; valaddr_reg:x6; val_offset:117*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x6, 117*FLEN/8, x7, x1, x5) + +inst_62: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ef and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1a8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x00d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78ef; op2val:0x3da8; +op3val:0x700d; valaddr_reg:x6; val_offset:120*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x6, 120*FLEN/8, x7, x1, x5) + +inst_63: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ef and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1a8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x00d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78ef; op2val:0x3da8; +op3val:0x700d; valaddr_reg:x6; val_offset:123*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x6, 123*FLEN/8, x7, x1, x5) + +inst_64: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ef and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1a8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x00d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78ef; op2val:0x3da8; +op3val:0x700d; valaddr_reg:x6; val_offset:126*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x6, 126*FLEN/8, x7, x1, x5) + +inst_65: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x354 and fs2 == 1 and fe2 == 0x19 and fm2 == 0x015 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5754; op2val:0xe415; +op3val:0x7af7; valaddr_reg:x6; val_offset:129*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 129*FLEN/8, x7, x1, x5) + +inst_66: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x354 and fs2 == 1 and fe2 == 0x19 and fm2 == 0x015 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5754; op2val:0xe415; +op3val:0x7af7; valaddr_reg:x6; val_offset:132*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x6, 132*FLEN/8, x7, x1, x5) + +inst_67: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x354 and fs2 == 1 and fe2 == 0x19 and fm2 == 0x015 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5754; op2val:0xe415; +op3val:0x7af7; valaddr_reg:x6; val_offset:135*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x6, 135*FLEN/8, x7, x1, x5) + +inst_68: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x354 and fs2 == 1 and fe2 == 0x19 and fm2 == 0x015 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5754; op2val:0xe415; +op3val:0x7af7; valaddr_reg:x6; val_offset:138*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x6, 138*FLEN/8, x7, x1, x5) + +inst_69: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x354 and fs2 == 1 and fe2 == 0x19 and fm2 == 0x015 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5754; op2val:0xe415; +op3val:0x7af7; valaddr_reg:x6; val_offset:141*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x6, 141*FLEN/8, x7, x1, x5) + +inst_70: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2b3 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2e9 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2e4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72b3; op2val:0xb6e9; +op3val:0x72e4; valaddr_reg:x6; val_offset:144*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 144*FLEN/8, x7, x1, x5) + +inst_71: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2b3 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2e9 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2e4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72b3; op2val:0xb6e9; +op3val:0x72e4; valaddr_reg:x6; val_offset:147*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x6, 147*FLEN/8, x7, x1, x5) + +inst_72: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2b3 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2e9 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2e4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72b3; op2val:0xb6e9; +op3val:0x72e4; valaddr_reg:x6; val_offset:150*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x6, 150*FLEN/8, x7, x1, x5) + +inst_73: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2b3 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2e9 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2e4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72b3; op2val:0xb6e9; +op3val:0x72e4; valaddr_reg:x6; val_offset:153*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x6, 153*FLEN/8, x7, x1, x5) + +inst_74: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2b3 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2e9 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2e4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72b3; op2val:0xb6e9; +op3val:0x72e4; valaddr_reg:x6; val_offset:156*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x6, 156*FLEN/8, x7, x1, x5) + +inst_75: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3db and fs2 == 1 and fe2 == 0x0f and fm2 == 0x00f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bdb; op2val:0xbc0f; +op3val:0x7af9; valaddr_reg:x6; val_offset:159*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 159*FLEN/8, x7, x1, x5) + +inst_76: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3db and fs2 == 1 and fe2 == 0x0f and fm2 == 0x00f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bdb; op2val:0xbc0f; +op3val:0x7af9; valaddr_reg:x6; val_offset:162*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x6, 162*FLEN/8, x7, x1, x5) + +inst_77: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3db and fs2 == 1 and fe2 == 0x0f and fm2 == 0x00f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bdb; op2val:0xbc0f; +op3val:0x7af9; valaddr_reg:x6; val_offset:165*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x6, 165*FLEN/8, x7, x1, x5) + +inst_78: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3db and fs2 == 1 and fe2 == 0x0f and fm2 == 0x00f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bdb; op2val:0xbc0f; +op3val:0x7af9; valaddr_reg:x6; val_offset:168*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x6, 168*FLEN/8, x7, x1, x5) + +inst_79: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3db and fs2 == 1 and fe2 == 0x0f and fm2 == 0x00f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bdb; op2val:0xbc0f; +op3val:0x7af9; valaddr_reg:x6; val_offset:171*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x6, 171*FLEN/8, x7, x1, x5) + +inst_80: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a0 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0eb and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74a0; op2val:0xc0eb; +op3val:0x7bb0; valaddr_reg:x6; val_offset:174*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 174*FLEN/8, x7, x1, x5) + +inst_81: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a0 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0eb and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74a0; op2val:0xc0eb; +op3val:0x7bb0; valaddr_reg:x6; val_offset:177*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x6, 177*FLEN/8, x7, x1, x5) + +inst_82: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a0 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0eb and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74a0; op2val:0xc0eb; +op3val:0x7bb0; valaddr_reg:x6; val_offset:180*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x6, 180*FLEN/8, x7, x1, x5) + +inst_83: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a0 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0eb and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74a0; op2val:0xc0eb; +op3val:0x7bb0; valaddr_reg:x6; val_offset:183*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x6, 183*FLEN/8, x7, x1, x5) + +inst_84: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a0 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0eb and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74a0; op2val:0xc0eb; +op3val:0x7bb0; valaddr_reg:x6; val_offset:186*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x6, 186*FLEN/8, x7, x1, x5) + +inst_85: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x16b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x784f; op2val:0xbee1; +op3val:0x796b; valaddr_reg:x6; val_offset:189*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 189*FLEN/8, x7, x1, x5) + +inst_86: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x16b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x784f; op2val:0xbee1; +op3val:0x796b; valaddr_reg:x6; val_offset:192*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x6, 192*FLEN/8, x7, x1, x5) + +inst_87: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x16b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x784f; op2val:0xbee1; +op3val:0x796b; valaddr_reg:x6; val_offset:195*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x6, 195*FLEN/8, x7, x1, x5) + +inst_88: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x16b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x784f; op2val:0xbee1; +op3val:0x796b; valaddr_reg:x6; val_offset:198*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x6, 198*FLEN/8, x7, x1, x5) + +inst_89: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x16b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x784f; op2val:0xbee1; +op3val:0x796b; valaddr_reg:x6; val_offset:201*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x6, 201*FLEN/8, x7, x1, x5) + +inst_90: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x28c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x04e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x386 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x728c; op2val:0xc04e; +op3val:0x7b86; valaddr_reg:x6; val_offset:204*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 204*FLEN/8, x7, x1, x5) + +inst_91: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x28c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x04e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x386 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x728c; op2val:0xc04e; +op3val:0x7b86; valaddr_reg:x6; val_offset:207*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x6, 207*FLEN/8, x7, x1, x5) + +inst_92: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x28c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x04e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x386 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x728c; op2val:0xc04e; +op3val:0x7b86; valaddr_reg:x6; val_offset:210*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x6, 210*FLEN/8, x7, x1, x5) + +inst_93: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x28c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x04e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x386 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x728c; op2val:0xc04e; +op3val:0x7b86; valaddr_reg:x6; val_offset:213*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x6, 213*FLEN/8, x7, x1, x5) + +inst_94: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x28c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x04e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x386 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x728c; op2val:0xc04e; +op3val:0x7b86; valaddr_reg:x6; val_offset:216*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x6, 216*FLEN/8, x7, x1, x5) + +inst_95: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x185 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x03f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ba and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7985; op2val:0xc03f; +op3val:0x7bba; valaddr_reg:x6; val_offset:219*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 219*FLEN/8, x7, x1, x5) + +inst_96: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x185 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x03f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ba and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7985; op2val:0xc03f; +op3val:0x7bba; valaddr_reg:x6; val_offset:222*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x6, 222*FLEN/8, x7, x1, x5) + +inst_97: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x185 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x03f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ba and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7985; op2val:0xc03f; +op3val:0x7bba; valaddr_reg:x6; val_offset:225*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x6, 225*FLEN/8, x7, x1, x5) + +inst_98: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x185 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x03f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ba and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7985; op2val:0xc03f; +op3val:0x7bba; valaddr_reg:x6; val_offset:228*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x6, 228*FLEN/8, x7, x1, x5) + +inst_99: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x185 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x03f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ba and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7985; op2val:0xc03f; +op3val:0x7bba; valaddr_reg:x6; val_offset:231*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x6, 231*FLEN/8, x7, x1, x5) + +inst_100: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x325 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x246 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0c7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b25; op2val:0x3a46; +op3val:0x74c7; valaddr_reg:x6; val_offset:234*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 234*FLEN/8, x7, x1, x5) + +inst_101: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x325 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x246 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0c7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b25; op2val:0x3a46; +op3val:0x74c7; valaddr_reg:x6; val_offset:237*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x6, 237*FLEN/8, x7, x1, x5) + +inst_102: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x325 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x246 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0c7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b25; op2val:0x3a46; +op3val:0x74c7; valaddr_reg:x6; val_offset:240*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x6, 240*FLEN/8, x7, x1, x5) + +inst_103: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x325 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x246 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0c7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b25; op2val:0x3a46; +op3val:0x74c7; valaddr_reg:x6; val_offset:243*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x6, 243*FLEN/8, x7, x1, x5) + +inst_104: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x325 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x246 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0c7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b25; op2val:0x3a46; +op3val:0x74c7; valaddr_reg:x6; val_offset:246*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x6, 246*FLEN/8, x7, x1, x5) + +inst_105: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c6 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x274 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x14e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c6; op2val:0xc274; +op3val:0x714e; valaddr_reg:x6; val_offset:249*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 249*FLEN/8, x7, x1, x5) + +inst_106: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c6 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x274 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x14e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c6; op2val:0xc274; +op3val:0x714e; valaddr_reg:x6; val_offset:252*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x6, 252*FLEN/8, x7, x1, x5) + +inst_107: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c6 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x274 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x14e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c6; op2val:0xc274; +op3val:0x714e; valaddr_reg:x6; val_offset:255*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x6, 255*FLEN/8, x7, x1, x5) + +inst_108: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c6 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x274 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x14e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c6; op2val:0xc274; +op3val:0x714e; valaddr_reg:x6; val_offset:258*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x6, 258*FLEN/8, x7, x1, x5) + +inst_109: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c6 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x274 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x14e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c6; op2val:0xc274; +op3val:0x714e; valaddr_reg:x6; val_offset:261*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x6, 261*FLEN/8, x7, x1, x5) + +inst_110: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0a9 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x2a3 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x02a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70a9; op2val:0x4aa3; +op3val:0x6c2a; valaddr_reg:x6; val_offset:264*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 264*FLEN/8, x7, x1, x5) + +inst_111: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0a9 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x2a3 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x02a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70a9; op2val:0x4aa3; +op3val:0x6c2a; valaddr_reg:x6; val_offset:267*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x6, 267*FLEN/8, x7, x1, x5) + +inst_112: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0a9 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x2a3 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x02a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70a9; op2val:0x4aa3; +op3val:0x6c2a; valaddr_reg:x6; val_offset:270*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x6, 270*FLEN/8, x7, x1, x5) + +inst_113: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0a9 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x2a3 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x02a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70a9; op2val:0x4aa3; +op3val:0x6c2a; valaddr_reg:x6; val_offset:273*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x6, 273*FLEN/8, x7, x1, x5) + +inst_114: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0a9 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x2a3 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x02a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70a9; op2val:0x4aa3; +op3val:0x6c2a; valaddr_reg:x6; val_offset:276*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x6, 276*FLEN/8, x7, x1, x5) + +inst_115: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d1 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x051 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0d2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74d1; op2val:0xc851; +op3val:0x78d2; valaddr_reg:x6; val_offset:279*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 279*FLEN/8, x7, x1, x5) + +inst_116: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d1 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x051 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0d2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74d1; op2val:0xc851; +op3val:0x78d2; valaddr_reg:x6; val_offset:282*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x6, 282*FLEN/8, x7, x1, x5) + +inst_117: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d1 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x051 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0d2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74d1; op2val:0xc851; +op3val:0x78d2; valaddr_reg:x6; val_offset:285*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x6, 285*FLEN/8, x7, x1, x5) + +inst_118: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d1 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x051 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0d2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74d1; op2val:0xc851; +op3val:0x78d2; valaddr_reg:x6; val_offset:288*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x6, 288*FLEN/8, x7, x1, x5) + +inst_119: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d1 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x051 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0d2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74d1; op2val:0xc851; +op3val:0x78d2; valaddr_reg:x6; val_offset:291*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x6, 291*FLEN/8, x7, x1, x5) + +inst_120: +// fs1 == 0 and fe1 == 0x16 and fm1 == 0x2f4 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x3a3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x16b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5af4; op2val:0x63a3; +op3val:0x796b; valaddr_reg:x6; val_offset:294*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 294*FLEN/8, x7, x1, x5) + +inst_121: +// fs1 == 0 and fe1 == 0x16 and fm1 == 0x2f4 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x3a3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x16b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5af4; op2val:0x63a3; +op3val:0x796b; valaddr_reg:x6; val_offset:297*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x6, 297*FLEN/8, x7, x1, x5) + +inst_122: +// fs1 == 0 and fe1 == 0x16 and fm1 == 0x2f4 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x3a3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x16b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5af4; op2val:0x63a3; +op3val:0x796b; valaddr_reg:x6; val_offset:300*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x6, 300*FLEN/8, x7, x1, x5) + +inst_123: +// fs1 == 0 and fe1 == 0x16 and fm1 == 0x2f4 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x3a3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x16b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5af4; op2val:0x63a3; +op3val:0x796b; valaddr_reg:x6; val_offset:303*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x6, 303*FLEN/8, x7, x1, x5) + +inst_124: +// fs1 == 0 and fe1 == 0x16 and fm1 == 0x2f4 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x3a3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x16b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5af4; op2val:0x63a3; +op3val:0x796b; valaddr_reg:x6; val_offset:306*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x6, 306*FLEN/8, x7, x1, x5) + +inst_125: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x167 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x260 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0f5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7567; op2val:0xca60; +op3val:0x74f5; valaddr_reg:x6; val_offset:309*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 309*FLEN/8, x7, x1, x5) + +inst_126: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x167 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x260 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0f5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7567; op2val:0xca60; +op3val:0x74f5; valaddr_reg:x6; val_offset:312*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x6, 312*FLEN/8, x7, x1, x5) + +inst_127: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x167 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x260 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0f5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7567; op2val:0xca60; +op3val:0x74f5; valaddr_reg:x6; val_offset:315*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x6, 315*FLEN/8, x7, x1, x5) + +inst_128: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x167 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x260 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0f5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7567; op2val:0xca60; +op3val:0x74f5; valaddr_reg:x6; val_offset:318*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x6, 318*FLEN/8, x7, x1, x5) + +inst_129: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x167 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x260 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0f5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7567; op2val:0xca60; +op3val:0x74f5; valaddr_reg:x6; val_offset:321*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x6, 321*FLEN/8, x7, x1, x5) + +inst_130: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28b and fs2 == 0 and fe2 == 0x12 and fm2 == 0x097 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3b0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8b; op2val:0x4897; +op3val:0x77b0; valaddr_reg:x6; val_offset:324*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 324*FLEN/8, x7, x1, x5) + +inst_131: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28b and fs2 == 0 and fe2 == 0x12 and fm2 == 0x097 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3b0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8b; op2val:0x4897; +op3val:0x77b0; valaddr_reg:x6; val_offset:327*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x6, 327*FLEN/8, x7, x1, x5) + +inst_132: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28b and fs2 == 0 and fe2 == 0x12 and fm2 == 0x097 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3b0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8b; op2val:0x4897; +op3val:0x77b0; valaddr_reg:x6; val_offset:330*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x6, 330*FLEN/8, x7, x1, x5) + +inst_133: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28b and fs2 == 0 and fe2 == 0x12 and fm2 == 0x097 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3b0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8b; op2val:0x4897; +op3val:0x77b0; valaddr_reg:x6; val_offset:333*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x6, 333*FLEN/8, x7, x1, x5) + +inst_134: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28b and fs2 == 0 and fe2 == 0x12 and fm2 == 0x097 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3b0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8b; op2val:0x4897; +op3val:0x77b0; valaddr_reg:x6; val_offset:336*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x6, 336*FLEN/8, x7, x1, x5) + +inst_135: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x10c and fs2 == 1 and fe2 == 0x13 and fm2 == 0x2b6 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3b2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x750c; op2val:0xceb6; +op3val:0x77b2; valaddr_reg:x6; val_offset:339*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 339*FLEN/8, x7, x1, x5) + +inst_136: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x10c and fs2 == 1 and fe2 == 0x13 and fm2 == 0x2b6 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3b2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x750c; op2val:0xceb6; +op3val:0x77b2; valaddr_reg:x6; val_offset:342*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x6, 342*FLEN/8, x7, x1, x5) + +inst_137: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x10c and fs2 == 1 and fe2 == 0x13 and fm2 == 0x2b6 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3b2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x750c; op2val:0xceb6; +op3val:0x77b2; valaddr_reg:x6; val_offset:345*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x6, 345*FLEN/8, x7, x1, x5) + +inst_138: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x10c and fs2 == 1 and fe2 == 0x13 and fm2 == 0x2b6 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3b2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x750c; op2val:0xceb6; +op3val:0x77b2; valaddr_reg:x6; val_offset:348*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x6, 348*FLEN/8, x7, x1, x5) + +inst_139: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x10c and fs2 == 1 and fe2 == 0x13 and fm2 == 0x2b6 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3b2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x750c; op2val:0xceb6; +op3val:0x77b2; valaddr_reg:x6; val_offset:351*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x6, 351*FLEN/8, x7, x1, x5) + +inst_140: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fb and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2a1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ee and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fb; op2val:0x36a1; +op3val:0x79ee; valaddr_reg:x6; val_offset:354*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 354*FLEN/8, x7, x1, x5) + +inst_141: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fb and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2a1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ee and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fb; op2val:0x36a1; +op3val:0x79ee; valaddr_reg:x6; val_offset:357*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x6, 357*FLEN/8, x7, x1, x5) + +inst_142: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fb and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2a1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ee and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fb; op2val:0x36a1; +op3val:0x79ee; valaddr_reg:x6; val_offset:360*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x6, 360*FLEN/8, x7, x1, x5) + +inst_143: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0e2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x389 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5b; op2val:0xc0e2; +op3val:0x7b89; valaddr_reg:x6; val_offset:363*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 363*FLEN/8, x7, x1, x5) + +inst_144: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0e2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x389 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5b; op2val:0xc0e2; +op3val:0x7b89; valaddr_reg:x6; val_offset:366*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x6, 366*FLEN/8, x7, x1, x5) + +inst_145: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0e2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x389 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5b; op2val:0xc0e2; +op3val:0x7b89; valaddr_reg:x6; val_offset:369*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x6, 369*FLEN/8, x7, x1, x5) + +inst_146: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0e2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x389 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5b; op2val:0xc0e2; +op3val:0x7b89; valaddr_reg:x6; val_offset:372*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x6, 372*FLEN/8, x7, x1, x5) + +inst_147: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0e2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x389 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5b; op2val:0xc0e2; +op3val:0x7b89; valaddr_reg:x6; val_offset:375*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x6, 375*FLEN/8, x7, x1, x5) + +inst_148: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ea and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2b7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x360 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79ea; op2val:0x2eb7; +op3val:0x7b60; valaddr_reg:x6; val_offset:378*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 378*FLEN/8, x7, x1, x5) + +inst_149: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ea and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2b7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x360 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79ea; op2val:0x2eb7; +op3val:0x7b60; valaddr_reg:x6; val_offset:381*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x6, 381*FLEN/8, x7, x1, x5) + +inst_150: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x380 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x26c and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3e3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7780; op2val:0x3e6c; +op3val:0x73e3; valaddr_reg:x6; val_offset:384*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x6, 384*FLEN/8, x7, x1, x5) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(30971,32,FLEN) +NAN_BOXED(30971,32,FLEN) +NAN_BOXED(31214,32,FLEN) +NAN_BOXED(30971,32,FLEN) +NAN_BOXED(13985,32,FLEN) +NAN_BOXED(30971,32,FLEN) +NAN_BOXED(30971,32,FLEN) +NAN_BOXED(13985,32,FLEN) +NAN_BOXED(31214,32,FLEN) +NAN_BOXED(30971,32,FLEN) +NAN_BOXED(30971,32,FLEN) +NAN_BOXED(30971,32,FLEN) +NAN_BOXED(30971,32,FLEN) +NAN_BOXED(13985,32,FLEN) +NAN_BOXED(31214,32,FLEN) +NAN_BOXED(31323,32,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31625,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(49378,16,FLEN) +NAN_BOXED(31625,32,FLEN) +NAN_BOXED(31323,32,FLEN) +NAN_BOXED(49378,16,FLEN) +NAN_BOXED(49378,32,FLEN) +NAN_BOXED(31323,32,FLEN) +NAN_BOXED(49378,16,FLEN) +NAN_BOXED(31323,32,FLEN) +NAN_BOXED(31323,32,FLEN) +NAN_BOXED(31323,16,FLEN) +NAN_BOXED(31323,32,FLEN) +NAN_BOXED(31210,32,FLEN) +NAN_BOXED(11959,32,FLEN) +NAN_BOXED(11959,32,FLEN) +NAN_BOXED(31210,32,FLEN) +NAN_BOXED(31210,32,FLEN) +NAN_BOXED(31584,32,FLEN) +test_dataset_1: +NAN_BOXED(31210,32,FLEN) +NAN_BOXED(11959,32,FLEN) +NAN_BOXED(31584,32,FLEN) +NAN_BOXED(31210,32,FLEN) +NAN_BOXED(11959,32,FLEN) +NAN_BOXED(31584,32,FLEN) +NAN_BOXED(31210,32,FLEN) +NAN_BOXED(11959,32,FLEN) +NAN_BOXED(31584,32,FLEN) +NAN_BOXED(26476,32,FLEN) +NAN_BOXED(53840,16,FLEN) +NAN_BOXED(30578,32,FLEN) +NAN_BOXED(26476,32,FLEN) +NAN_BOXED(53840,16,FLEN) +NAN_BOXED(30578,32,FLEN) +NAN_BOXED(26476,32,FLEN) +NAN_BOXED(53840,16,FLEN) +NAN_BOXED(30578,32,FLEN) +NAN_BOXED(26476,32,FLEN) +NAN_BOXED(53840,16,FLEN) +NAN_BOXED(30578,32,FLEN) +NAN_BOXED(26476,32,FLEN) +NAN_BOXED(53840,16,FLEN) +NAN_BOXED(30578,32,FLEN) +NAN_BOXED(31627,32,FLEN) +NAN_BOXED(13812,32,FLEN) +NAN_BOXED(31024,32,FLEN) +NAN_BOXED(31627,32,FLEN) +NAN_BOXED(13812,32,FLEN) +NAN_BOXED(31024,32,FLEN) +test_dataset_2: +NAN_BOXED(31627,16,FLEN) +NAN_BOXED(13812,16,FLEN) +NAN_BOXED(31024,16,FLEN) +NAN_BOXED(31627,16,FLEN) +NAN_BOXED(13812,16,FLEN) +NAN_BOXED(31024,16,FLEN) +NAN_BOXED(31627,16,FLEN) +NAN_BOXED(13812,16,FLEN) +NAN_BOXED(31024,16,FLEN) +NAN_BOXED(31540,16,FLEN) +NAN_BOXED(48369,16,FLEN) +NAN_BOXED(28478,16,FLEN) +NAN_BOXED(31540,16,FLEN) +NAN_BOXED(48369,16,FLEN) +NAN_BOXED(28478,16,FLEN) +NAN_BOXED(31540,16,FLEN) +NAN_BOXED(48369,16,FLEN) +NAN_BOXED(28478,16,FLEN) +NAN_BOXED(31540,16,FLEN) +NAN_BOXED(48369,16,FLEN) +NAN_BOXED(28478,16,FLEN) +NAN_BOXED(31540,16,FLEN) +NAN_BOXED(48369,16,FLEN) +NAN_BOXED(28478,16,FLEN) +NAN_BOXED(30592,16,FLEN) +NAN_BOXED(15980,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(30592,16,FLEN) +NAN_BOXED(15980,16,FLEN) +NAN_BOXED(29667,16,FLEN) +NAN_BOXED(30592,16,FLEN) +NAN_BOXED(15980,16,FLEN) +NAN_BOXED(29667,16,FLEN) +NAN_BOXED(30592,16,FLEN) +NAN_BOXED(15980,16,FLEN) +NAN_BOXED(29667,16,FLEN) +NAN_BOXED(30592,16,FLEN) +NAN_BOXED(15980,16,FLEN) +NAN_BOXED(29667,16,FLEN) +NAN_BOXED(30809,16,FLEN) +NAN_BOXED(49609,16,FLEN) +NAN_BOXED(30870,16,FLEN) +NAN_BOXED(30809,16,FLEN) +NAN_BOXED(49609,16,FLEN) +NAN_BOXED(30870,16,FLEN) +NAN_BOXED(30809,16,FLEN) +NAN_BOXED(49609,16,FLEN) +NAN_BOXED(30870,16,FLEN) +NAN_BOXED(30809,16,FLEN) +NAN_BOXED(49609,16,FLEN) +NAN_BOXED(30870,16,FLEN) +NAN_BOXED(30809,16,FLEN) +NAN_BOXED(49609,16,FLEN) +NAN_BOXED(30870,16,FLEN) +NAN_BOXED(25272,16,FLEN) +NAN_BOXED(21365,16,FLEN) +NAN_BOXED(29422,16,FLEN) +NAN_BOXED(25272,16,FLEN) +NAN_BOXED(21365,16,FLEN) +NAN_BOXED(29422,16,FLEN) +NAN_BOXED(25272,16,FLEN) +NAN_BOXED(21365,16,FLEN) +NAN_BOXED(29422,16,FLEN) +NAN_BOXED(25272,16,FLEN) +NAN_BOXED(21365,16,FLEN) +NAN_BOXED(29422,16,FLEN) +NAN_BOXED(25272,16,FLEN) +NAN_BOXED(21365,16,FLEN) +NAN_BOXED(29422,16,FLEN) +NAN_BOXED(29816,16,FLEN) +NAN_BOXED(50907,16,FLEN) +NAN_BOXED(31571,16,FLEN) +NAN_BOXED(29816,16,FLEN) +NAN_BOXED(50907,16,FLEN) +NAN_BOXED(31571,16,FLEN) +NAN_BOXED(29816,16,FLEN) +NAN_BOXED(50907,16,FLEN) +NAN_BOXED(31571,16,FLEN) +NAN_BOXED(29816,16,FLEN) +NAN_BOXED(50907,16,FLEN) +NAN_BOXED(31571,16,FLEN) +NAN_BOXED(29816,16,FLEN) +NAN_BOXED(50907,16,FLEN) +NAN_BOXED(31571,16,FLEN) +NAN_BOXED(31263,16,FLEN) +NAN_BOXED(15459,16,FLEN) +NAN_BOXED(28954,16,FLEN) +NAN_BOXED(31263,16,FLEN) +NAN_BOXED(15459,16,FLEN) +NAN_BOXED(28954,16,FLEN) +NAN_BOXED(31263,16,FLEN) +NAN_BOXED(15459,16,FLEN) +NAN_BOXED(28954,16,FLEN) +NAN_BOXED(31263,16,FLEN) +NAN_BOXED(15459,16,FLEN) +NAN_BOXED(28954,16,FLEN) +NAN_BOXED(31263,16,FLEN) +NAN_BOXED(15459,16,FLEN) +NAN_BOXED(28954,16,FLEN) +NAN_BOXED(31327,16,FLEN) +NAN_BOXED(48566,16,FLEN) +NAN_BOXED(28784,16,FLEN) +NAN_BOXED(31327,16,FLEN) +NAN_BOXED(48566,16,FLEN) +NAN_BOXED(28784,16,FLEN) +NAN_BOXED(31327,16,FLEN) +NAN_BOXED(48566,16,FLEN) +NAN_BOXED(28784,16,FLEN) +NAN_BOXED(31327,16,FLEN) +NAN_BOXED(48566,16,FLEN) +NAN_BOXED(28784,16,FLEN) +NAN_BOXED(31327,16,FLEN) +NAN_BOXED(48566,16,FLEN) +NAN_BOXED(28784,16,FLEN) +NAN_BOXED(30959,16,FLEN) +NAN_BOXED(15784,16,FLEN) +NAN_BOXED(28685,16,FLEN) +NAN_BOXED(30959,16,FLEN) +NAN_BOXED(15784,16,FLEN) +NAN_BOXED(28685,16,FLEN) +NAN_BOXED(30959,16,FLEN) +NAN_BOXED(15784,16,FLEN) +NAN_BOXED(28685,16,FLEN) +NAN_BOXED(30959,16,FLEN) +NAN_BOXED(15784,16,FLEN) +NAN_BOXED(28685,16,FLEN) +NAN_BOXED(30959,16,FLEN) +NAN_BOXED(15784,16,FLEN) +NAN_BOXED(28685,16,FLEN) +NAN_BOXED(22356,16,FLEN) +NAN_BOXED(58389,16,FLEN) +NAN_BOXED(31479,16,FLEN) +NAN_BOXED(22356,16,FLEN) +NAN_BOXED(58389,16,FLEN) +NAN_BOXED(31479,16,FLEN) +NAN_BOXED(22356,16,FLEN) +NAN_BOXED(58389,16,FLEN) +NAN_BOXED(31479,16,FLEN) +NAN_BOXED(22356,16,FLEN) +NAN_BOXED(58389,16,FLEN) +NAN_BOXED(31479,16,FLEN) +NAN_BOXED(22356,16,FLEN) +NAN_BOXED(58389,16,FLEN) +NAN_BOXED(31479,16,FLEN) +NAN_BOXED(29363,16,FLEN) +NAN_BOXED(46825,16,FLEN) +NAN_BOXED(29412,16,FLEN) +NAN_BOXED(29363,16,FLEN) +NAN_BOXED(46825,16,FLEN) +NAN_BOXED(29412,16,FLEN) +NAN_BOXED(29363,16,FLEN) +NAN_BOXED(46825,16,FLEN) +NAN_BOXED(29412,16,FLEN) +NAN_BOXED(29363,16,FLEN) +NAN_BOXED(46825,16,FLEN) +NAN_BOXED(29412,16,FLEN) +NAN_BOXED(29363,16,FLEN) +NAN_BOXED(46825,16,FLEN) +NAN_BOXED(29412,16,FLEN) +NAN_BOXED(31707,16,FLEN) +NAN_BOXED(48143,16,FLEN) +NAN_BOXED(31481,16,FLEN) +NAN_BOXED(31707,16,FLEN) +NAN_BOXED(48143,16,FLEN) +NAN_BOXED(31481,16,FLEN) +NAN_BOXED(31707,16,FLEN) +NAN_BOXED(48143,16,FLEN) +NAN_BOXED(31481,16,FLEN) +NAN_BOXED(31707,16,FLEN) +NAN_BOXED(48143,16,FLEN) +NAN_BOXED(31481,16,FLEN) +NAN_BOXED(31707,16,FLEN) +NAN_BOXED(48143,16,FLEN) +NAN_BOXED(31481,16,FLEN) +NAN_BOXED(29856,16,FLEN) +NAN_BOXED(49387,16,FLEN) +NAN_BOXED(31664,16,FLEN) +NAN_BOXED(29856,16,FLEN) +NAN_BOXED(49387,16,FLEN) +NAN_BOXED(31664,16,FLEN) +NAN_BOXED(29856,16,FLEN) +NAN_BOXED(49387,16,FLEN) +NAN_BOXED(31664,16,FLEN) +NAN_BOXED(29856,16,FLEN) +NAN_BOXED(49387,16,FLEN) +NAN_BOXED(31664,16,FLEN) +NAN_BOXED(29856,16,FLEN) +NAN_BOXED(49387,16,FLEN) +NAN_BOXED(31664,16,FLEN) +NAN_BOXED(30799,16,FLEN) +NAN_BOXED(48865,16,FLEN) +NAN_BOXED(31083,16,FLEN) +NAN_BOXED(30799,16,FLEN) +NAN_BOXED(48865,16,FLEN) +NAN_BOXED(31083,16,FLEN) +NAN_BOXED(30799,16,FLEN) +NAN_BOXED(48865,16,FLEN) +NAN_BOXED(31083,16,FLEN) +NAN_BOXED(30799,16,FLEN) +NAN_BOXED(48865,16,FLEN) +NAN_BOXED(31083,16,FLEN) +NAN_BOXED(30799,16,FLEN) +NAN_BOXED(48865,16,FLEN) +NAN_BOXED(31083,16,FLEN) +NAN_BOXED(29324,16,FLEN) +NAN_BOXED(49230,16,FLEN) +NAN_BOXED(31622,16,FLEN) +NAN_BOXED(29324,16,FLEN) +NAN_BOXED(49230,16,FLEN) +NAN_BOXED(31622,16,FLEN) +NAN_BOXED(29324,16,FLEN) +NAN_BOXED(49230,16,FLEN) +NAN_BOXED(31622,16,FLEN) +NAN_BOXED(29324,16,FLEN) +NAN_BOXED(49230,16,FLEN) +NAN_BOXED(31622,16,FLEN) +NAN_BOXED(29324,16,FLEN) +NAN_BOXED(49230,16,FLEN) +NAN_BOXED(31622,16,FLEN) +NAN_BOXED(31109,16,FLEN) +NAN_BOXED(49215,16,FLEN) +NAN_BOXED(31674,16,FLEN) +NAN_BOXED(31109,16,FLEN) +NAN_BOXED(49215,16,FLEN) +NAN_BOXED(31674,16,FLEN) +NAN_BOXED(31109,16,FLEN) +NAN_BOXED(49215,16,FLEN) +NAN_BOXED(31674,16,FLEN) +NAN_BOXED(31109,16,FLEN) +NAN_BOXED(49215,16,FLEN) +NAN_BOXED(31674,16,FLEN) +NAN_BOXED(31109,16,FLEN) +NAN_BOXED(49215,16,FLEN) +NAN_BOXED(31674,16,FLEN) +NAN_BOXED(31525,16,FLEN) +NAN_BOXED(14918,16,FLEN) +NAN_BOXED(29895,16,FLEN) +NAN_BOXED(31525,16,FLEN) +NAN_BOXED(14918,16,FLEN) +NAN_BOXED(29895,16,FLEN) +NAN_BOXED(31525,16,FLEN) +NAN_BOXED(14918,16,FLEN) +NAN_BOXED(29895,16,FLEN) +NAN_BOXED(31525,16,FLEN) +NAN_BOXED(14918,16,FLEN) +NAN_BOXED(29895,16,FLEN) +NAN_BOXED(31525,16,FLEN) +NAN_BOXED(14918,16,FLEN) +NAN_BOXED(29895,16,FLEN) +NAN_BOXED(30150,16,FLEN) +NAN_BOXED(49780,16,FLEN) +NAN_BOXED(29006,16,FLEN) +NAN_BOXED(30150,16,FLEN) +NAN_BOXED(49780,16,FLEN) +NAN_BOXED(29006,16,FLEN) +NAN_BOXED(30150,16,FLEN) +NAN_BOXED(49780,16,FLEN) +NAN_BOXED(29006,16,FLEN) +NAN_BOXED(30150,16,FLEN) +NAN_BOXED(49780,16,FLEN) +NAN_BOXED(29006,16,FLEN) +NAN_BOXED(30150,16,FLEN) +NAN_BOXED(49780,16,FLEN) +NAN_BOXED(29006,16,FLEN) +NAN_BOXED(28841,16,FLEN) +NAN_BOXED(19107,16,FLEN) +NAN_BOXED(27690,16,FLEN) +NAN_BOXED(28841,16,FLEN) +NAN_BOXED(19107,16,FLEN) +NAN_BOXED(27690,16,FLEN) +NAN_BOXED(28841,16,FLEN) +NAN_BOXED(19107,16,FLEN) +NAN_BOXED(27690,16,FLEN) +NAN_BOXED(28841,16,FLEN) +NAN_BOXED(19107,16,FLEN) +NAN_BOXED(27690,16,FLEN) +NAN_BOXED(28841,16,FLEN) +NAN_BOXED(19107,16,FLEN) +NAN_BOXED(27690,16,FLEN) +NAN_BOXED(29905,16,FLEN) +NAN_BOXED(51281,16,FLEN) +NAN_BOXED(30930,16,FLEN) +NAN_BOXED(29905,16,FLEN) +NAN_BOXED(51281,16,FLEN) +NAN_BOXED(30930,16,FLEN) +NAN_BOXED(29905,16,FLEN) +NAN_BOXED(51281,16,FLEN) +NAN_BOXED(30930,16,FLEN) +NAN_BOXED(29905,16,FLEN) +NAN_BOXED(51281,16,FLEN) +NAN_BOXED(30930,16,FLEN) +NAN_BOXED(29905,16,FLEN) +NAN_BOXED(51281,16,FLEN) +NAN_BOXED(30930,16,FLEN) +NAN_BOXED(23284,16,FLEN) +NAN_BOXED(25507,16,FLEN) +NAN_BOXED(31083,16,FLEN) +NAN_BOXED(23284,16,FLEN) +NAN_BOXED(25507,16,FLEN) +NAN_BOXED(31083,16,FLEN) +NAN_BOXED(23284,16,FLEN) +NAN_BOXED(25507,16,FLEN) +NAN_BOXED(31083,16,FLEN) +NAN_BOXED(23284,16,FLEN) +NAN_BOXED(25507,16,FLEN) +NAN_BOXED(31083,16,FLEN) +NAN_BOXED(23284,16,FLEN) +NAN_BOXED(25507,16,FLEN) +NAN_BOXED(31083,16,FLEN) +NAN_BOXED(30055,16,FLEN) +NAN_BOXED(51808,16,FLEN) +NAN_BOXED(29941,16,FLEN) +NAN_BOXED(30055,16,FLEN) +NAN_BOXED(51808,16,FLEN) +NAN_BOXED(29941,16,FLEN) +NAN_BOXED(30055,16,FLEN) +NAN_BOXED(51808,16,FLEN) +NAN_BOXED(29941,16,FLEN) +NAN_BOXED(30055,16,FLEN) +NAN_BOXED(51808,16,FLEN) +NAN_BOXED(29941,16,FLEN) +NAN_BOXED(30055,16,FLEN) +NAN_BOXED(51808,16,FLEN) +NAN_BOXED(29941,16,FLEN) +NAN_BOXED(31371,16,FLEN) +NAN_BOXED(18583,16,FLEN) +NAN_BOXED(30640,16,FLEN) +NAN_BOXED(31371,16,FLEN) +NAN_BOXED(18583,16,FLEN) +NAN_BOXED(30640,16,FLEN) +NAN_BOXED(31371,16,FLEN) +NAN_BOXED(18583,16,FLEN) +NAN_BOXED(30640,16,FLEN) +NAN_BOXED(31371,16,FLEN) +NAN_BOXED(18583,16,FLEN) +NAN_BOXED(30640,16,FLEN) +NAN_BOXED(31371,16,FLEN) +NAN_BOXED(18583,16,FLEN) +NAN_BOXED(30640,16,FLEN) +NAN_BOXED(29964,16,FLEN) +NAN_BOXED(52918,16,FLEN) +NAN_BOXED(30642,16,FLEN) +NAN_BOXED(29964,16,FLEN) +NAN_BOXED(52918,16,FLEN) +NAN_BOXED(30642,16,FLEN) +NAN_BOXED(29964,16,FLEN) +NAN_BOXED(52918,16,FLEN) +NAN_BOXED(30642,16,FLEN) +NAN_BOXED(29964,16,FLEN) +NAN_BOXED(52918,16,FLEN) +NAN_BOXED(30642,16,FLEN) +NAN_BOXED(29964,16,FLEN) +NAN_BOXED(52918,16,FLEN) +NAN_BOXED(30642,16,FLEN) +NAN_BOXED(30971,16,FLEN) +NAN_BOXED(13985,16,FLEN) +NAN_BOXED(31214,16,FLEN) +NAN_BOXED(30971,16,FLEN) +NAN_BOXED(13985,16,FLEN) +NAN_BOXED(31214,16,FLEN) +NAN_BOXED(30971,16,FLEN) +NAN_BOXED(13985,16,FLEN) +NAN_BOXED(31214,16,FLEN) +NAN_BOXED(31323,16,FLEN) +NAN_BOXED(49378,16,FLEN) +NAN_BOXED(31625,16,FLEN) +NAN_BOXED(31323,16,FLEN) +NAN_BOXED(49378,16,FLEN) +NAN_BOXED(31625,16,FLEN) +NAN_BOXED(31323,16,FLEN) +NAN_BOXED(49378,16,FLEN) +NAN_BOXED(31625,16,FLEN) +NAN_BOXED(31323,16,FLEN) +NAN_BOXED(49378,16,FLEN) +NAN_BOXED(31625,16,FLEN) +NAN_BOXED(31323,16,FLEN) +NAN_BOXED(49378,16,FLEN) +NAN_BOXED(31625,16,FLEN) +NAN_BOXED(31210,16,FLEN) +NAN_BOXED(11959,16,FLEN) +NAN_BOXED(31584,16,FLEN) +NAN_BOXED(31210,16,FLEN) +NAN_BOXED(11959,16,FLEN) +NAN_BOXED(31584,16,FLEN) +NAN_BOXED(30592,16,FLEN) +NAN_BOXED(15980,16,FLEN) +NAN_BOXED(29667,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x4_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x4_1: + .fill 30*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_0: + .fill 26*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_0: + .fill 246*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fmadd_b5-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fmadd_b5-01.S new file mode 100644 index 000000000..5b4748220 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fmadd_b5-01.S @@ -0,0 +1,2411 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 04:10:09 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fmadd.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fmadd.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fmadd_b5 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fmadd_b5) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x14,test_dataset_0) +RVTEST_SIGBASE(x9,signature_x9_1) + +inst_0: +// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==x15, rs2==x15, rs3==x29, rd==x17,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0c3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ee and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x15; op2:x15; op3:x29; dest:x17; op1val:0x78fb; op2val:0x78fb; +op3val:0x79ee; valaddr_reg:x14; val_offset:0*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x17, x15, x15, x29, dyn, 0, 0, x14, 0*FLEN/8, x20, x9, x12) + +inst_1: +// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==x7, rs2==x13, rs3==x7, rd==x10,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0c3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ee and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x7; op2:x13; op3:x7; dest:x10; op1val:0x78fb; op2val:0xbcc3; +op3val:0x78fb; valaddr_reg:x14; val_offset:3*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x10, x7, x13, x7, dyn, 32, 0, x14, 3*FLEN/8, x20, x9, x12) + +inst_2: +// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==x25, rs2==x22, rs3==x31, rd==x25,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0c3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ee and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x25; op2:x22; op3:x31; dest:x25; op1val:0x78fb; op2val:0xbcc3; +op3val:0x79ee; valaddr_reg:x14; val_offset:6*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x25, x25, x22, x31, dyn, 64, 0, x14, 6*FLEN/8, x20, x9, x12) + +inst_3: +// rs1 == rs2 == rs3 != rd, rs1==x26, rs2==x26, rs3==x26, rd==x21,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0c3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ee and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x26; op2:x26; op3:x26; dest:x21; op1val:0x78fb; op2val:0x78fb; +op3val:0x78fb; valaddr_reg:x14; val_offset:9*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x21, x26, x26, x26, dyn, 96, 0, x14, 9*FLEN/8, x20, x9, x12) + +inst_4: +// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==x8, rs2==x27, rs3==x5, rd==x5,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0c3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ee and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x8; op2:x27; op3:x5; dest:x5; op1val:0x78fb; op2val:0xbcc3; +op3val:0x79ee; valaddr_reg:x14; val_offset:12*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x5, x8, x27, x5, dyn, 128, 0, x14, 12*FLEN/8, x20, x9, x12) + +inst_5: +// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==x31, rs2==x2, rs3==x22, rd==x2,fs1 == 0 and fe1 == 0x1e and fm1 == 0x25b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0bd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x389 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x31; op2:x2; op3:x22; dest:x2; op1val:0x7a5b; op2val:0xbcbd; +op3val:0x7b89; valaddr_reg:x14; val_offset:15*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x2, x31, x2, x22, dyn, 0, 0, x14, 15*FLEN/8, x20, x9, x12) + +inst_6: +// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==x16, rs2==x31, rs3==x28, rd==x7,fs1 == 0 and fe1 == 0x1e and fm1 == 0x25b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0bd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x389 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x16; op2:x31; op3:x28; dest:x7; op1val:0x7a5b; op2val:0xbcbd; +op3val:0x7b89; valaddr_reg:x14; val_offset:18*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x7, x16, x31, x28, dyn, 32, 0, x14, 18*FLEN/8, x20, x9, x12) + +inst_7: +// rd == rs2 == rs3 != rs1, rs1==x19, rs2==x6, rs3==x6, rd==x6,fs1 == 0 and fe1 == 0x1e and fm1 == 0x25b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0bd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x389 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x19; op2:x6; op3:x6; dest:x6; op1val:0x7a5b; op2val:0xbcbd; +op3val:0xbcbd; valaddr_reg:x14; val_offset:21*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x6, x19, x6, x6, dyn, 64, 0, x14, 21*FLEN/8, x20, x9, x12) + +inst_8: +// rs1 == rd == rs3 != rs2, rs1==x11, rs2==x5, rs3==x11, rd==x11,fs1 == 0 and fe1 == 0x1e and fm1 == 0x25b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0bd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x389 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x11; op2:x5; op3:x11; dest:x11; op1val:0x7a5b; op2val:0xbcbd; +op3val:0x7a5b; valaddr_reg:x14; val_offset:24*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x11, x11, x5, x11, dyn, 96, 0, x14, 24*FLEN/8, x20, x9, x12) + +inst_9: +// rs1 == rs2 == rs3 == rd, rs1==x24, rs2==x24, rs3==x24, rd==x24,fs1 == 0 and fe1 == 0x1e and fm1 == 0x25b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0bd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x389 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x24; op2:x24; op3:x24; dest:x24; op1val:0x7a5b; op2val:0x7a5b; +op3val:0x7a5b; valaddr_reg:x14; val_offset:27*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x24, x24, x24, x24, dyn, 128, 0, x14, 27*FLEN/8, x20, x9, x12) + +inst_10: +// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==x28, rs2==x1, rs3==x1, rd==x31,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ea and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0fc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x360 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x28; op2:x1; op3:x1; dest:x31; op1val:0x79ea; op2val:0xbcfc; +op3val:0xbcfc; valaddr_reg:x14; val_offset:30*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x28, x1, x1, dyn, 0, 0, x14, 30*FLEN/8, x20, x9, x12) + +inst_11: +// rs1 == rs2 == rd != rs3, rs1==x0, rs2==x0, rs3==x10, rd==x0,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ea and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0fc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x360 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x0; op2:x0; op3:x10; dest:x0; op1val:0x0; op2val:0x0; +op3val:0x7b60; valaddr_reg:x14; val_offset:33*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x0, x0, x0, x10, dyn, 32, 0, x14, 33*FLEN/8, x20, x9, x12) + +inst_12: +// rs1==x3, rs2==x4, rs3==x9, rd==x18,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ea and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0fc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x360 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x3; op2:x4; op3:x9; dest:x18; op1val:0x79ea; op2val:0xbcfc; +op3val:0x7b60; valaddr_reg:x14; val_offset:36*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x18, x3, x4, x9, dyn, 64, 0, x14, 36*FLEN/8, x20, x9, x12) +RVTEST_VALBASEUPD(x1,test_dataset_1) + +inst_13: +// rs1==x21, rs2==x29, rs3==x19, rd==x26,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ea and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0fc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x360 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x21; op2:x29; op3:x19; dest:x26; op1val:0x79ea; op2val:0xbcfc; +op3val:0x7b60; valaddr_reg:x1; val_offset:0*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x26, x21, x29, x19, dyn, 96, 0, x1, 0*FLEN/8, x6, x9, x4) +RVTEST_SIGBASE(x2,signature_x2_0) + +inst_14: +// rs1==x17, rs2==x30, rs3==x21, rd==x16,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ea and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0fc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x360 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x17; op2:x30; op3:x21; dest:x16; op1val:0x79ea; op2val:0xbcfc; +op3val:0x7b60; valaddr_reg:x1; val_offset:3*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x16, x17, x30, x21, dyn, 128, 0, x1, 3*FLEN/8, x6, x2, x4) + +inst_15: +// rs1==x20, rs2==x14, rs3==x8, rd==x30,fs1 == 0 and fe1 == 0x19 and fm1 == 0x36c and fs2 == 1 and fe2 == 0x13 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x372 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x20; op2:x14; op3:x8; dest:x30; op1val:0x676c; op2val:0xcc02; +op3val:0x7772; valaddr_reg:x1; val_offset:6*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x30, x20, x14, x8, dyn, 0, 0, x1, 6*FLEN/8, x6, x2, x4) + +inst_16: +// rs1==x27, rs2==x11, rs3==x14, rd==x8,fs1 == 0 and fe1 == 0x19 and fm1 == 0x36c and fs2 == 1 and fe2 == 0x13 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x372 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x27; op2:x11; op3:x14; dest:x8; op1val:0x676c; op2val:0xcc02; +op3val:0x7772; valaddr_reg:x1; val_offset:9*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x8, x27, x11, x14, dyn, 32, 0, x1, 9*FLEN/8, x6, x2, x4) + +inst_17: +// rs1==x10, rs2==x19, rs3==x25, rd==x9,fs1 == 0 and fe1 == 0x19 and fm1 == 0x36c and fs2 == 1 and fe2 == 0x13 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x372 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x10; op2:x19; op3:x25; dest:x9; op1val:0x676c; op2val:0xcc02; +op3val:0x7772; valaddr_reg:x1; val_offset:12*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x9, x10, x19, x25, dyn, 64, 0, x1, 12*FLEN/8, x6, x2, x4) + +inst_18: +// rs1==x14, rs2==x3, rs3==x16, rd==x13,fs1 == 0 and fe1 == 0x19 and fm1 == 0x36c and fs2 == 1 and fe2 == 0x13 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x372 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x14; op2:x3; op3:x16; dest:x13; op1val:0x676c; op2val:0xcc02; +op3val:0x7772; valaddr_reg:x1; val_offset:15*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x13, x14, x3, x16, dyn, 96, 0, x1, 15*FLEN/8, x6, x2, x4) + +inst_19: +// rs1==x12, rs2==x23, rs3==x2, rd==x27,fs1 == 0 and fe1 == 0x19 and fm1 == 0x36c and fs2 == 1 and fe2 == 0x13 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x372 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x12; op2:x23; op3:x2; dest:x27; op1val:0x676c; op2val:0xcc02; +op3val:0x7772; valaddr_reg:x1; val_offset:18*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x27, x12, x23, x2, dyn, 128, 0, x1, 18*FLEN/8, x6, x2, x4) + +inst_20: +// rs1==x5, rs2==x18, rs3==x13, rd==x28,fs1 == 0 and fe1 == 0x1e and fm1 == 0x38b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x180 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x130 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x5; op2:x18; op3:x13; dest:x28; op1val:0x7b8b; op2val:0xb980; +op3val:0x7930; valaddr_reg:x1; val_offset:21*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x28, x5, x18, x13, dyn, 0, 0, x1, 21*FLEN/8, x6, x2, x4) + +inst_21: +// rs1==x18, rs2==x9, rs3==x12, rd==x15,fs1 == 0 and fe1 == 0x1e and fm1 == 0x38b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x180 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x130 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x18; op2:x9; op3:x12; dest:x15; op1val:0x7b8b; op2val:0xb980; +op3val:0x7930; valaddr_reg:x1; val_offset:24*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x15, x18, x9, x12, dyn, 32, 0, x1, 24*FLEN/8, x6, x2, x4) +RVTEST_VALBASEUPD(x15,test_dataset_2) + +inst_22: +// rs1==x22, rs2==x25, rs3==x30, rd==x1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x38b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x180 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x130 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x22; op2:x25; op3:x30; dest:x1; op1val:0x7b8b; op2val:0xb980; +op3val:0x7930; valaddr_reg:x15; val_offset:0*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x1, x22, x25, x30, dyn, 64, 0, x15, 0*FLEN/8, x17, x2, x4) + +inst_23: +// rs1==x1, rs2==x12, rs3==x27, rd==x29,fs1 == 0 and fe1 == 0x1e and fm1 == 0x38b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x180 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x130 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x1; op2:x12; op3:x27; dest:x29; op1val:0x7b8b; op2val:0xb980; +op3val:0x7930; valaddr_reg:x15; val_offset:3*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x29, x1, x12, x27, dyn, 96, 0, x15, 3*FLEN/8, x17, x2, x11) + +inst_24: +// rs1==x30, rs2==x7, rs3==x3, rd==x19,fs1 == 0 and fe1 == 0x1e and fm1 == 0x38b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x180 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x130 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x7; op3:x3; dest:x19; op1val:0x7b8b; op2val:0xb980; +op3val:0x7930; valaddr_reg:x15; val_offset:6*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x19, x30, x7, x3, dyn, 128, 0, x15, 6*FLEN/8, x17, x2, x11) + +inst_25: +// rs1==x4, rs2==x20, rs3==x18, rd==x22,fs1 == 0 and fe1 == 0x1e and fm1 == 0x334 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x005 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x33e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x4; op2:x20; op3:x18; dest:x22; op1val:0x7b34; op2val:0xb005; +op3val:0x6f3e; valaddr_reg:x15; val_offset:9*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x22, x4, x20, x18, dyn, 0, 0, x15, 9*FLEN/8, x17, x2, x11) +RVTEST_SIGBASE(x5,signature_x5_0) + +inst_26: +// rs1==x6, rs2==x28, rs3==x20, rd==x12,fs1 == 0 and fe1 == 0x1e and fm1 == 0x334 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x005 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x33e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x6; op2:x28; op3:x20; dest:x12; op1val:0x7b34; op2val:0xb005; +op3val:0x6f3e; valaddr_reg:x15; val_offset:12*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x12, x6, x28, x20, dyn, 32, 0, x15, 12*FLEN/8, x17, x5, x11) + +inst_27: +// rs1==x13, rs2==x8, rs3==x0, rd==x4,fs1 == 0 and fe1 == 0x1e and fm1 == 0x334 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x005 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x33e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x13; op2:x8; op3:x0; dest:x4; op1val:0x7b34; op2val:0xb005; +op3val:0x0; valaddr_reg:x15; val_offset:15*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x4, x13, x8, x0, dyn, 64, 0, x15, 15*FLEN/8, x17, x5, x11) + +inst_28: +// rs1==x9, rs2==x16, rs3==x17, rd==x20,fs1 == 0 and fe1 == 0x1e and fm1 == 0x334 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x005 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x33e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x9; op2:x16; op3:x17; dest:x20; op1val:0x7b34; op2val:0xb005; +op3val:0x6f3e; valaddr_reg:x15; val_offset:18*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x20, x9, x16, x17, dyn, 96, 0, x15, 18*FLEN/8, x17, x5, x11) + +inst_29: +// rs1==x2, rs2==x10, rs3==x23, rd==x3,fs1 == 0 and fe1 == 0x1e and fm1 == 0x334 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x005 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x33e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x2; op2:x10; op3:x23; dest:x3; op1val:0x7b34; op2val:0xb005; +op3val:0x6f3e; valaddr_reg:x15; val_offset:21*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x3, x2, x10, x23, dyn, 128, 0, x15, 21*FLEN/8, x17, x5, x11) + +inst_30: +// rs1==x29, rs2==x21, rs3==x15, rd==x14,fs1 == 0 and fe1 == 0x1d and fm1 == 0x380 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x034 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3e3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x29; op2:x21; op3:x15; dest:x14; op1val:0x7780; op2val:0xb834; +op3val:0x73e3; valaddr_reg:x15; val_offset:24*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x14, x29, x21, x15, dyn, 0, 0, x15, 24*FLEN/8, x17, x5, x11) + +inst_31: +// rs1==x23,fs1 == 0 and fe1 == 0x1d and fm1 == 0x380 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x034 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3e3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x23; op2:x16; op3:x3; dest:x12; op1val:0x7780; op2val:0xb834; +op3val:0x73e3; valaddr_reg:x15; val_offset:27*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x12, x23, x16, x3, dyn, 32, 0, x15, 27*FLEN/8, x17, x5, x11) +RVTEST_VALBASEUPD(x2,test_dataset_3) + +inst_32: +// rs2==x17,fs1 == 0 and fe1 == 0x1d and fm1 == 0x380 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x034 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3e3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x24; op2:x17; op3:x0; dest:x1; op1val:0x7780; op2val:0xb834; +op3val:0x0; valaddr_reg:x2; val_offset:0*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x1, x24, x17, x0, dyn, 64, 0, x2, 0*FLEN/8, x4, x5, x11) + +inst_33: +// rs3==x4,fs1 == 0 and fe1 == 0x1d and fm1 == 0x380 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x034 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3e3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x21; op2:x3; op3:x4; dest:x31; op1val:0x7780; op2val:0xb834; +op3val:0x73e3; valaddr_reg:x2; val_offset:3*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x21, x3, x4, dyn, 96, 0, x2, 3*FLEN/8, x4, x5, x11) + +inst_34: +// rd==x23,fs1 == 0 and fe1 == 0x1d and fm1 == 0x380 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x034 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3e3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x17; op2:x8; op3:x18; dest:x23; op1val:0x7780; op2val:0xb834; +op3val:0x73e3; valaddr_reg:x2; val_offset:6*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x23, x17, x8, x18, dyn, 128, 0, x2, 6*FLEN/8, x4, x5, x1) + +inst_35: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x059 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x038 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x096 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7859; op2val:0xbc38; +op3val:0x7896; valaddr_reg:x2; val_offset:9*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9*FLEN/8, x4, x5, x1) + +inst_36: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x059 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x038 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x096 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7859; op2val:0xbc38; +op3val:0x7896; valaddr_reg:x2; val_offset:12*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x2, 12*FLEN/8, x4, x5, x1) + +inst_37: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x059 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x038 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x096 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7859; op2val:0xbc38; +op3val:0x7896; valaddr_reg:x2; val_offset:15*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x2, 15*FLEN/8, x4, x5, x1) + +inst_38: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x059 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x038 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x096 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7859; op2val:0xbc38; +op3val:0x7896; valaddr_reg:x2; val_offset:18*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 18*FLEN/8, x4, x5, x1) + +inst_39: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x059 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x038 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x096 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7859; op2val:0xbc38; +op3val:0x7896; valaddr_reg:x2; val_offset:21*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x2, 21*FLEN/8, x4, x5, x1) + +inst_40: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x2b8 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x020 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2ee and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x62b8; op2val:0xcc20; +op3val:0x72ee; valaddr_reg:x2; val_offset:24*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24*FLEN/8, x4, x5, x1) + +inst_41: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x2b8 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x020 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2ee and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x62b8; op2val:0xcc20; +op3val:0x72ee; valaddr_reg:x2; val_offset:27*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x2, 27*FLEN/8, x4, x5, x1) + +inst_42: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x2b8 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x020 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2ee and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x62b8; op2val:0xcc20; +op3val:0x72ee; valaddr_reg:x2; val_offset:30*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x2, 30*FLEN/8, x4, x5, x1) + +inst_43: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x2b8 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x020 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2ee and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x62b8; op2val:0xcc20; +op3val:0x72ee; valaddr_reg:x2; val_offset:33*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 33*FLEN/8, x4, x5, x1) + +inst_44: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x2b8 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x020 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2ee and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x62b8; op2val:0xcc20; +op3val:0x72ee; valaddr_reg:x2; val_offset:36*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x2, 36*FLEN/8, x4, x5, x1) + +inst_45: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x078 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x28e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x353 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7478; op2val:0xc28e; +op3val:0x7b53; valaddr_reg:x2; val_offset:39*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39*FLEN/8, x4, x5, x1) + +inst_46: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x078 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x28e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x353 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7478; op2val:0xc28e; +op3val:0x7b53; valaddr_reg:x2; val_offset:42*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x2, 42*FLEN/8, x4, x5, x1) + +inst_47: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x078 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x28e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x353 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7478; op2val:0xc28e; +op3val:0x7b53; valaddr_reg:x2; val_offset:45*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x2, 45*FLEN/8, x4, x5, x1) + +inst_48: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x078 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x28e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x353 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7478; op2val:0xc28e; +op3val:0x7b53; valaddr_reg:x2; val_offset:48*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 48*FLEN/8, x4, x5, x1) + +inst_49: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x078 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x28e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x353 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7478; op2val:0xc28e; +op3val:0x7b53; valaddr_reg:x2; val_offset:51*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x2, 51*FLEN/8, x4, x5, x1) + +inst_50: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2ab and fs3 == 0 and fe3 == 0x1c and fm3 == 0x11a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a1f; op2val:0xb2ab; +op3val:0x711a; valaddr_reg:x2; val_offset:54*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 54*FLEN/8, x4, x5, x1) + +inst_51: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2ab and fs3 == 0 and fe3 == 0x1c and fm3 == 0x11a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a1f; op2val:0xb2ab; +op3val:0x711a; valaddr_reg:x2; val_offset:57*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x2, 57*FLEN/8, x4, x5, x1) + +inst_52: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2ab and fs3 == 0 and fe3 == 0x1c and fm3 == 0x11a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a1f; op2val:0xb2ab; +op3val:0x711a; valaddr_reg:x2; val_offset:60*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x2, 60*FLEN/8, x4, x5, x1) + +inst_53: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2ab and fs3 == 0 and fe3 == 0x1c and fm3 == 0x11a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a1f; op2val:0xb2ab; +op3val:0x711a; valaddr_reg:x2; val_offset:63*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 63*FLEN/8, x4, x5, x1) + +inst_54: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2ab and fs3 == 0 and fe3 == 0x1c and fm3 == 0x11a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a1f; op2val:0xb2ab; +op3val:0x711a; valaddr_reg:x2; val_offset:66*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x2, 66*FLEN/8, x4, x5, x1) + +inst_55: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x192 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x070 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5f; op2val:0xb192; +op3val:0x7070; valaddr_reg:x2; val_offset:69*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 69*FLEN/8, x4, x5, x1) + +inst_56: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x192 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x070 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5f; op2val:0xb192; +op3val:0x7070; valaddr_reg:x2; val_offset:72*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x2, 72*FLEN/8, x4, x5, x1) + +inst_57: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x192 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x070 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5f; op2val:0xb192; +op3val:0x7070; valaddr_reg:x2; val_offset:75*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x2, 75*FLEN/8, x4, x5, x1) + +inst_58: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x192 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x070 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5f; op2val:0xb192; +op3val:0x7070; valaddr_reg:x2; val_offset:78*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 78*FLEN/8, x4, x5, x1) + +inst_59: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x192 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x070 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5f; op2val:0xb192; +op3val:0x7070; valaddr_reg:x2; val_offset:81*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x2, 81*FLEN/8, x4, x5, x1) + +inst_60: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ef and fs2 == 1 and fe2 == 0x0c and fm2 == 0x291 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x00d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78ef; op2val:0xb291; +op3val:0x700d; valaddr_reg:x2; val_offset:84*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 84*FLEN/8, x4, x5, x1) + +inst_61: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ef and fs2 == 1 and fe2 == 0x0c and fm2 == 0x291 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x00d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78ef; op2val:0xb291; +op3val:0x700d; valaddr_reg:x2; val_offset:87*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x2, 87*FLEN/8, x4, x5, x1) + +inst_62: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ef and fs2 == 1 and fe2 == 0x0c and fm2 == 0x291 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x00d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78ef; op2val:0xb291; +op3val:0x700d; valaddr_reg:x2; val_offset:90*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x2, 90*FLEN/8, x4, x5, x1) + +inst_63: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ef and fs2 == 1 and fe2 == 0x0c and fm2 == 0x291 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x00d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78ef; op2val:0xb291; +op3val:0x700d; valaddr_reg:x2; val_offset:93*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 93*FLEN/8, x4, x5, x1) + +inst_64: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ef and fs2 == 1 and fe2 == 0x0c and fm2 == 0x291 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x00d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78ef; op2val:0xb291; +op3val:0x700d; valaddr_reg:x2; val_offset:96*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x2, 96*FLEN/8, x4, x5, x1) + +inst_65: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x354 and fs2 == 1 and fe2 == 0x17 and fm2 == 0x39b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5754; op2val:0xdf9b; +op3val:0x7af7; valaddr_reg:x2; val_offset:99*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 99*FLEN/8, x4, x5, x1) + +inst_66: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x354 and fs2 == 1 and fe2 == 0x17 and fm2 == 0x39b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5754; op2val:0xdf9b; +op3val:0x7af7; valaddr_reg:x2; val_offset:102*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x2, 102*FLEN/8, x4, x5, x1) + +inst_67: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x354 and fs2 == 1 and fe2 == 0x17 and fm2 == 0x39b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5754; op2val:0xdf9b; +op3val:0x7af7; valaddr_reg:x2; val_offset:105*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x2, 105*FLEN/8, x4, x5, x1) + +inst_68: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x354 and fs2 == 1 and fe2 == 0x17 and fm2 == 0x39b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5754; op2val:0xdf9b; +op3val:0x7af7; valaddr_reg:x2; val_offset:108*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 108*FLEN/8, x4, x5, x1) + +inst_69: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x354 and fs2 == 1 and fe2 == 0x17 and fm2 == 0x39b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5754; op2val:0xdf9b; +op3val:0x7af7; valaddr_reg:x2; val_offset:111*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x2, 111*FLEN/8, x4, x5, x1) + +inst_70: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2b3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x01d and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2e4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72b3; op2val:0xbc1d; +op3val:0x72e4; valaddr_reg:x2; val_offset:114*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 114*FLEN/8, x4, x5, x1) + +inst_71: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2b3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x01d and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2e4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72b3; op2val:0xbc1d; +op3val:0x72e4; valaddr_reg:x2; val_offset:117*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x2, 117*FLEN/8, x4, x5, x1) + +inst_72: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2b3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x01d and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2e4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72b3; op2val:0xbc1d; +op3val:0x72e4; valaddr_reg:x2; val_offset:120*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x2, 120*FLEN/8, x4, x5, x1) + +inst_73: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2b3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x01d and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2e4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72b3; op2val:0xbc1d; +op3val:0x72e4; valaddr_reg:x2; val_offset:123*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 123*FLEN/8, x4, x5, x1) + +inst_74: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2b3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x01d and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2e4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72b3; op2val:0xbc1d; +op3val:0x72e4; valaddr_reg:x2; val_offset:126*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x2, 126*FLEN/8, x4, x5, x1) + +inst_75: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3db and fs2 == 1 and fe2 == 0x0e and fm2 == 0x31a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bdb; op2val:0xbb1a; +op3val:0x7af9; valaddr_reg:x2; val_offset:129*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 129*FLEN/8, x4, x5, x1) + +inst_76: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3db and fs2 == 1 and fe2 == 0x0e and fm2 == 0x31a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bdb; op2val:0xbb1a; +op3val:0x7af9; valaddr_reg:x2; val_offset:132*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x2, 132*FLEN/8, x4, x5, x1) + +inst_77: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3db and fs2 == 1 and fe2 == 0x0e and fm2 == 0x31a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bdb; op2val:0xbb1a; +op3val:0x7af9; valaddr_reg:x2; val_offset:135*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x2, 135*FLEN/8, x4, x5, x1) + +inst_78: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3db and fs2 == 1 and fe2 == 0x0e and fm2 == 0x31a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bdb; op2val:0xbb1a; +op3val:0x7af9; valaddr_reg:x2; val_offset:138*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 138*FLEN/8, x4, x5, x1) + +inst_79: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3db and fs2 == 1 and fe2 == 0x0e and fm2 == 0x31a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bdb; op2val:0xbb1a; +op3val:0x7af9; valaddr_reg:x2; val_offset:141*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x2, 141*FLEN/8, x4, x5, x1) + +inst_80: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a0 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2a5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74a0; op2val:0xc2a5; +op3val:0x7bb0; valaddr_reg:x2; val_offset:144*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 144*FLEN/8, x4, x5, x1) + +inst_81: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a0 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2a5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74a0; op2val:0xc2a5; +op3val:0x7bb0; valaddr_reg:x2; val_offset:147*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x2, 147*FLEN/8, x4, x5, x1) + +inst_82: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a0 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2a5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74a0; op2val:0xc2a5; +op3val:0x7bb0; valaddr_reg:x2; val_offset:150*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x2, 150*FLEN/8, x4, x5, x1) + +inst_83: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a0 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2a5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74a0; op2val:0xc2a5; +op3val:0x7bb0; valaddr_reg:x2; val_offset:153*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 153*FLEN/8, x4, x5, x1) + +inst_84: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a0 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2a5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74a0; op2val:0xc2a5; +op3val:0x7bb0; valaddr_reg:x2; val_offset:156*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x2, 156*FLEN/8, x4, x5, x1) + +inst_85: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x107 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x16b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x784f; op2val:0xbd07; +op3val:0x796b; valaddr_reg:x2; val_offset:159*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 159*FLEN/8, x4, x5, x1) + +inst_86: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x107 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x16b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x784f; op2val:0xbd07; +op3val:0x796b; valaddr_reg:x2; val_offset:162*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x2, 162*FLEN/8, x4, x5, x1) + +inst_87: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x107 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x16b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x784f; op2val:0xbd07; +op3val:0x796b; valaddr_reg:x2; val_offset:165*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x2, 165*FLEN/8, x4, x5, x1) + +inst_88: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x107 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x16b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x784f; op2val:0xbd07; +op3val:0x796b; valaddr_reg:x2; val_offset:168*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 168*FLEN/8, x4, x5, x1) + +inst_89: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x107 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x16b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x784f; op2val:0xbd07; +op3val:0x796b; valaddr_reg:x2; val_offset:171*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x2, 171*FLEN/8, x4, x5, x1) + +inst_90: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x28c and fs2 == 1 and fe2 == 0x11 and fm2 == 0x098 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x386 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x728c; op2val:0xc498; +op3val:0x7b86; valaddr_reg:x2; val_offset:174*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 174*FLEN/8, x4, x5, x1) + +inst_91: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x28c and fs2 == 1 and fe2 == 0x11 and fm2 == 0x098 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x386 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x728c; op2val:0xc498; +op3val:0x7b86; valaddr_reg:x2; val_offset:177*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x2, 177*FLEN/8, x4, x5, x1) + +inst_92: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x28c and fs2 == 1 and fe2 == 0x11 and fm2 == 0x098 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x386 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x728c; op2val:0xc498; +op3val:0x7b86; valaddr_reg:x2; val_offset:180*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x2, 180*FLEN/8, x4, x5, x1) + +inst_93: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x28c and fs2 == 1 and fe2 == 0x11 and fm2 == 0x098 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x386 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x728c; op2val:0xc498; +op3val:0x7b86; valaddr_reg:x2; val_offset:183*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 183*FLEN/8, x4, x5, x1) + +inst_94: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x28c and fs2 == 1 and fe2 == 0x11 and fm2 == 0x098 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x386 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x728c; op2val:0xc498; +op3val:0x7b86; valaddr_reg:x2; val_offset:186*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x2, 186*FLEN/8, x4, x5, x1) + +inst_95: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x185 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x199 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ba and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7985; op2val:0xbd99; +op3val:0x7bba; valaddr_reg:x2; val_offset:189*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 189*FLEN/8, x4, x5, x1) + +inst_96: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x185 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x199 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ba and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7985; op2val:0xbd99; +op3val:0x7bba; valaddr_reg:x2; val_offset:192*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x2, 192*FLEN/8, x4, x5, x1) + +inst_97: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x185 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x199 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ba and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7985; op2val:0xbd99; +op3val:0x7bba; valaddr_reg:x2; val_offset:195*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x2, 195*FLEN/8, x4, x5, x1) + +inst_98: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x185 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x199 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ba and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7985; op2val:0xbd99; +op3val:0x7bba; valaddr_reg:x2; val_offset:198*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 198*FLEN/8, x4, x5, x1) + +inst_99: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x185 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x199 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ba and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7985; op2val:0xbd99; +op3val:0x7bba; valaddr_reg:x2; val_offset:201*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x2, 201*FLEN/8, x4, x5, x1) + +inst_100: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x325 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x159 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0c7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b25; op2val:0xb559; +op3val:0x74c7; valaddr_reg:x2; val_offset:204*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 204*FLEN/8, x4, x5, x1) + +inst_101: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x325 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x159 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0c7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b25; op2val:0xb559; +op3val:0x74c7; valaddr_reg:x2; val_offset:207*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x2, 207*FLEN/8, x4, x5, x1) + +inst_102: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x325 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x159 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0c7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b25; op2val:0xb559; +op3val:0x74c7; valaddr_reg:x2; val_offset:210*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x2, 210*FLEN/8, x4, x5, x1) + +inst_103: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x325 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x159 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0c7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b25; op2val:0xb559; +op3val:0x74c7; valaddr_reg:x2; val_offset:213*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 213*FLEN/8, x4, x5, x1) + +inst_104: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x325 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x159 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0c7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b25; op2val:0xb559; +op3val:0x74c7; valaddr_reg:x2; val_offset:216*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x2, 216*FLEN/8, x4, x5, x1) + +inst_105: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c6 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x35a and fs3 == 0 and fe3 == 0x1c and fm3 == 0x14e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c6; op2val:0xb75a; +op3val:0x714e; valaddr_reg:x2; val_offset:219*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 219*FLEN/8, x4, x5, x1) + +inst_106: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c6 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x35a and fs3 == 0 and fe3 == 0x1c and fm3 == 0x14e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c6; op2val:0xb75a; +op3val:0x714e; valaddr_reg:x2; val_offset:222*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x2, 222*FLEN/8, x4, x5, x1) + +inst_107: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c6 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x35a and fs3 == 0 and fe3 == 0x1c and fm3 == 0x14e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c6; op2val:0xb75a; +op3val:0x714e; valaddr_reg:x2; val_offset:225*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x2, 225*FLEN/8, x4, x5, x1) + +inst_108: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c6 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x35a and fs3 == 0 and fe3 == 0x1c and fm3 == 0x14e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c6; op2val:0xb75a; +op3val:0x714e; valaddr_reg:x2; val_offset:228*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 228*FLEN/8, x4, x5, x1) + +inst_109: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c6 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x35a and fs3 == 0 and fe3 == 0x1c and fm3 == 0x14e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c6; op2val:0xb75a; +op3val:0x714e; valaddr_reg:x2; val_offset:231*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x2, 231*FLEN/8, x4, x5, x1) + +inst_110: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0a9 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x327 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x02a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70a9; op2val:0xb727; +op3val:0x6c2a; valaddr_reg:x2; val_offset:234*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 234*FLEN/8, x4, x5, x1) + +inst_111: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0a9 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x327 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x02a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70a9; op2val:0xb727; +op3val:0x6c2a; valaddr_reg:x2; val_offset:237*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x2, 237*FLEN/8, x4, x5, x1) + +inst_112: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0a9 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x327 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x02a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70a9; op2val:0xb727; +op3val:0x6c2a; valaddr_reg:x2; val_offset:240*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x2, 240*FLEN/8, x4, x5, x1) + +inst_113: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0a9 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x327 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x02a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70a9; op2val:0xb727; +op3val:0x6c2a; valaddr_reg:x2; val_offset:243*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 243*FLEN/8, x4, x5, x1) + +inst_114: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0a9 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x327 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x02a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70a9; op2val:0xb727; +op3val:0x6c2a; valaddr_reg:x2; val_offset:246*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x2, 246*FLEN/8, x4, x5, x1) + +inst_115: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d1 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0d2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74d1; op2val:0xc000; +op3val:0x78d2; valaddr_reg:x2; val_offset:249*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 249*FLEN/8, x4, x5, x1) + +inst_116: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d1 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0d2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74d1; op2val:0xc000; +op3val:0x78d2; valaddr_reg:x2; val_offset:252*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x2, 252*FLEN/8, x4, x5, x1) + +inst_117: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d1 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0d2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74d1; op2val:0xc000; +op3val:0x78d2; valaddr_reg:x2; val_offset:255*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x2, 255*FLEN/8, x4, x5, x1) + +inst_118: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d1 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0d2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74d1; op2val:0xc000; +op3val:0x78d2; valaddr_reg:x2; val_offset:258*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 258*FLEN/8, x4, x5, x1) + +inst_119: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d1 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0d2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74d1; op2val:0xc000; +op3val:0x78d2; valaddr_reg:x2; val_offset:261*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x2, 261*FLEN/8, x4, x5, x1) + +inst_120: +// fs1 == 0 and fe1 == 0x16 and fm1 == 0x2f4 and fs2 == 1 and fe2 == 0x16 and fm2 == 0x23b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x16b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5af4; op2val:0xda3b; +op3val:0x796b; valaddr_reg:x2; val_offset:264*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 264*FLEN/8, x4, x5, x1) + +inst_121: +// fs1 == 0 and fe1 == 0x16 and fm1 == 0x2f4 and fs2 == 1 and fe2 == 0x16 and fm2 == 0x23b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x16b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5af4; op2val:0xda3b; +op3val:0x796b; valaddr_reg:x2; val_offset:267*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x2, 267*FLEN/8, x4, x5, x1) + +inst_122: +// fs1 == 0 and fe1 == 0x16 and fm1 == 0x2f4 and fs2 == 1 and fe2 == 0x16 and fm2 == 0x23b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x16b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5af4; op2val:0xda3b; +op3val:0x796b; valaddr_reg:x2; val_offset:270*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x2, 270*FLEN/8, x4, x5, x1) + +inst_123: +// fs1 == 0 and fe1 == 0x16 and fm1 == 0x2f4 and fs2 == 1 and fe2 == 0x16 and fm2 == 0x23b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x16b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5af4; op2val:0xda3b; +op3val:0x796b; valaddr_reg:x2; val_offset:273*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 273*FLEN/8, x4, x5, x1) + +inst_124: +// fs1 == 0 and fe1 == 0x16 and fm1 == 0x2f4 and fs2 == 1 and fe2 == 0x16 and fm2 == 0x23b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x16b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5af4; op2val:0xda3b; +op3val:0x796b; valaddr_reg:x2; val_offset:276*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x2, 276*FLEN/8, x4, x5, x1) + +inst_125: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x167 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x356 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0f5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7567; op2val:0xbb56; +op3val:0x74f5; valaddr_reg:x2; val_offset:279*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 279*FLEN/8, x4, x5, x1) + +inst_126: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x167 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x356 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0f5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7567; op2val:0xbb56; +op3val:0x74f5; valaddr_reg:x2; val_offset:282*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x2, 282*FLEN/8, x4, x5, x1) + +inst_127: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x167 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x356 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0f5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7567; op2val:0xbb56; +op3val:0x74f5; valaddr_reg:x2; val_offset:285*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x2, 285*FLEN/8, x4, x5, x1) + +inst_128: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x167 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x356 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0f5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7567; op2val:0xbb56; +op3val:0x74f5; valaddr_reg:x2; val_offset:288*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 288*FLEN/8, x4, x5, x1) + +inst_129: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x167 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x356 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0f5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7567; op2val:0xbb56; +op3val:0x74f5; valaddr_reg:x2; val_offset:291*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x2, 291*FLEN/8, x4, x5, x1) + +inst_130: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0b2 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3b0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8b; op2val:0xb8b2; +op3val:0x77b0; valaddr_reg:x2; val_offset:294*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 294*FLEN/8, x4, x5, x1) + +inst_131: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0b2 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3b0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8b; op2val:0xb8b2; +op3val:0x77b0; valaddr_reg:x2; val_offset:297*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x2, 297*FLEN/8, x4, x5, x1) + +inst_132: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0b2 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3b0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8b; op2val:0xb8b2; +op3val:0x77b0; valaddr_reg:x2; val_offset:300*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x2, 300*FLEN/8, x4, x5, x1) + +inst_133: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0b2 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3b0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8b; op2val:0xb8b2; +op3val:0x77b0; valaddr_reg:x2; val_offset:303*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 303*FLEN/8, x4, x5, x1) + +inst_134: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0b2 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3b0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8b; op2val:0xb8b2; +op3val:0x77b0; valaddr_reg:x2; val_offset:306*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x2, 306*FLEN/8, x4, x5, x1) + +inst_135: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x10c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x218 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3b2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x750c; op2val:0xbe18; +op3val:0x77b2; valaddr_reg:x2; val_offset:309*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 309*FLEN/8, x4, x5, x1) + +inst_136: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x10c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x218 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3b2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x750c; op2val:0xbe18; +op3val:0x77b2; valaddr_reg:x2; val_offset:312*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x2, 312*FLEN/8, x4, x5, x1) + +inst_137: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x10c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x218 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3b2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x750c; op2val:0xbe18; +op3val:0x77b2; valaddr_reg:x2; val_offset:315*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x2, 315*FLEN/8, x4, x5, x1) + +inst_138: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x10c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x218 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3b2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x750c; op2val:0xbe18; +op3val:0x77b2; valaddr_reg:x2; val_offset:318*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 318*FLEN/8, x4, x5, x1) + +inst_139: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x10c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x218 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3b2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x750c; op2val:0xbe18; +op3val:0x77b2; valaddr_reg:x2; val_offset:321*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x2, 321*FLEN/8, x4, x5, x1) + +inst_140: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a2 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x12d and fs3 == 0 and fe3 == 0x1a and fm3 == 0x34b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79a2; op2val:0xad2d; +op3val:0x6b4b; valaddr_reg:x2; val_offset:324*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 324*FLEN/8, x4, x5, x1) + +inst_141: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a2 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x12d and fs3 == 0 and fe3 == 0x1a and fm3 == 0x34b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79a2; op2val:0xad2d; +op3val:0x6b4b; valaddr_reg:x2; val_offset:327*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x2, 327*FLEN/8, x4, x5, x1) + +inst_142: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a2 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x12d and fs3 == 0 and fe3 == 0x1a and fm3 == 0x34b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79a2; op2val:0xad2d; +op3val:0x6b4b; valaddr_reg:x2; val_offset:330*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x2, 330*FLEN/8, x4, x5, x1) + +inst_143: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a2 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x12d and fs3 == 0 and fe3 == 0x1a and fm3 == 0x34b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79a2; op2val:0xad2d; +op3val:0x6b4b; valaddr_reg:x2; val_offset:333*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 333*FLEN/8, x4, x5, x1) + +inst_144: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a2 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x12d and fs3 == 0 and fe3 == 0x1a and fm3 == 0x34b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79a2; op2val:0xad2d; +op3val:0x6b4b; valaddr_reg:x2; val_offset:336*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x2, 336*FLEN/8, x4, x5, x1) + +inst_145: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3cc and fs2 == 1 and fe2 == 0x09 and fm2 == 0x201 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x1da and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bcc; op2val:0xa601; +op3val:0x65da; valaddr_reg:x2; val_offset:339*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 339*FLEN/8, x4, x5, x1) + +inst_146: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3cc and fs2 == 1 and fe2 == 0x09 and fm2 == 0x201 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x1da and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bcc; op2val:0xa601; +op3val:0x65da; valaddr_reg:x2; val_offset:342*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x2, 342*FLEN/8, x4, x5, x1) + +inst_147: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3cc and fs2 == 1 and fe2 == 0x09 and fm2 == 0x201 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x1da and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bcc; op2val:0xa601; +op3val:0x65da; valaddr_reg:x2; val_offset:345*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x2, 345*FLEN/8, x4, x5, x1) + +inst_148: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3cc and fs2 == 1 and fe2 == 0x09 and fm2 == 0x201 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x1da and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bcc; op2val:0xa601; +op3val:0x65da; valaddr_reg:x2; val_offset:348*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 348*FLEN/8, x4, x5, x1) + +inst_149: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3cc and fs2 == 1 and fe2 == 0x09 and fm2 == 0x201 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x1da and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bcc; op2val:0xa601; +op3val:0x65da; valaddr_reg:x2; val_offset:351*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x2, 351*FLEN/8, x4, x5, x1) + +inst_150: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x081 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2c1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79fe; op2val:0xbc81; +op3val:0x7ac1; valaddr_reg:x2; val_offset:354*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 354*FLEN/8, x4, x5, x1) + +inst_151: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x081 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2c1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79fe; op2val:0xbc81; +op3val:0x7ac1; valaddr_reg:x2; val_offset:357*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x2, 357*FLEN/8, x4, x5, x1) + +inst_152: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x081 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2c1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79fe; op2val:0xbc81; +op3val:0x7ac1; valaddr_reg:x2; val_offset:360*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x2, 360*FLEN/8, x4, x5, x1) + +inst_153: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x081 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2c1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79fe; op2val:0xbc81; +op3val:0x7ac1; valaddr_reg:x2; val_offset:363*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 363*FLEN/8, x4, x5, x1) +RVTEST_SIGBASE(x5,signature_x5_1) + +inst_154: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x081 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2c1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79fe; op2val:0xbc81; +op3val:0x7ac1; valaddr_reg:x2; val_offset:366*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x2, 366*FLEN/8, x4, x5, x1) + +inst_155: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x0a0 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x172 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x24c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x64a0; op2val:0xd172; +op3val:0x7a4c; valaddr_reg:x2; val_offset:369*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 369*FLEN/8, x4, x5, x1) + +inst_156: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x0a0 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x172 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x24c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x64a0; op2val:0xd172; +op3val:0x7a4c; valaddr_reg:x2; val_offset:372*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x2, 372*FLEN/8, x4, x5, x1) + +inst_157: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x0a0 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x172 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x24c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x64a0; op2val:0xd172; +op3val:0x7a4c; valaddr_reg:x2; val_offset:375*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x2, 375*FLEN/8, x4, x5, x1) + +inst_158: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x0a0 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x172 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x24c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x64a0; op2val:0xd172; +op3val:0x7a4c; valaddr_reg:x2; val_offset:378*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 378*FLEN/8, x4, x5, x1) + +inst_159: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x0a0 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x172 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x24c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x64a0; op2val:0xd172; +op3val:0x7a4c; valaddr_reg:x2; val_offset:381*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x2, 381*FLEN/8, x4, x5, x1) + +inst_160: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1db and fs2 == 1 and fe2 == 0x0f and fm2 == 0x251 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75db; op2val:0xbe51; +op3val:0x78a0; valaddr_reg:x2; val_offset:384*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 384*FLEN/8, x4, x5, x1) + +inst_161: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1db and fs2 == 1 and fe2 == 0x0f and fm2 == 0x251 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75db; op2val:0xbe51; +op3val:0x78a0; valaddr_reg:x2; val_offset:387*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x2, 387*FLEN/8, x4, x5, x1) + +inst_162: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1db and fs2 == 1 and fe2 == 0x0f and fm2 == 0x251 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75db; op2val:0xbe51; +op3val:0x78a0; valaddr_reg:x2; val_offset:390*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x2, 390*FLEN/8, x4, x5, x1) + +inst_163: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1db and fs2 == 1 and fe2 == 0x0f and fm2 == 0x251 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75db; op2val:0xbe51; +op3val:0x78a0; valaddr_reg:x2; val_offset:393*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 393*FLEN/8, x4, x5, x1) + +inst_164: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1db and fs2 == 1 and fe2 == 0x0f and fm2 == 0x251 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75db; op2val:0xbe51; +op3val:0x78a0; valaddr_reg:x2; val_offset:396*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x2, 396*FLEN/8, x4, x5, x1) + +inst_165: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x0a7 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x123 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x1fa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x60a7; op2val:0xc523; +op3val:0x69fa; valaddr_reg:x2; val_offset:399*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 399*FLEN/8, x4, x5, x1) + +inst_166: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x0a7 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x123 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x1fa and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x60a7; op2val:0xc523; +op3val:0x69fa; valaddr_reg:x2; val_offset:402*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x2, 402*FLEN/8, x4, x5, x1) + +inst_167: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x0a7 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x123 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x1fa and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x60a7; op2val:0xc523; +op3val:0x69fa; valaddr_reg:x2; val_offset:405*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x2, 405*FLEN/8, x4, x5, x1) + +inst_168: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x0a7 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x123 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x1fa and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x60a7; op2val:0xc523; +op3val:0x69fa; valaddr_reg:x2; val_offset:408*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 408*FLEN/8, x4, x5, x1) + +inst_169: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x0a7 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x123 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x1fa and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x60a7; op2val:0xc523; +op3val:0x69fa; valaddr_reg:x2; val_offset:411*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x2, 411*FLEN/8, x4, x5, x1) + +inst_170: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1c9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x147 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3a3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71c9; op2val:0xc547; +op3val:0x7ba3; valaddr_reg:x2; val_offset:414*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 414*FLEN/8, x4, x5, x1) + +inst_171: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1c9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x147 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3a3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71c9; op2val:0xc547; +op3val:0x7ba3; valaddr_reg:x2; val_offset:417*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x2, 417*FLEN/8, x4, x5, x1) + +inst_172: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1c9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x147 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3a3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71c9; op2val:0xc547; +op3val:0x7ba3; valaddr_reg:x2; val_offset:420*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x2, 420*FLEN/8, x4, x5, x1) + +inst_173: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1c9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x147 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3a3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71c9; op2val:0xc547; +op3val:0x7ba3; valaddr_reg:x2; val_offset:423*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 423*FLEN/8, x4, x5, x1) + +inst_174: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1c9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x147 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3a3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71c9; op2val:0xc547; +op3val:0x7ba3; valaddr_reg:x2; val_offset:426*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x2, 426*FLEN/8, x4, x5, x1) + +inst_175: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x249 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3b0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x20b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7249; op2val:0xc3b0; +op3val:0x7a0b; valaddr_reg:x2; val_offset:429*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 429*FLEN/8, x4, x5, x1) + +inst_176: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x249 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3b0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x20b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7249; op2val:0xc3b0; +op3val:0x7a0b; valaddr_reg:x2; val_offset:432*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x2, 432*FLEN/8, x4, x5, x1) + +inst_177: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x249 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3b0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x20b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7249; op2val:0xc3b0; +op3val:0x7a0b; valaddr_reg:x2; val_offset:435*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x2, 435*FLEN/8, x4, x5, x1) + +inst_178: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x249 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3b0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x20b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7249; op2val:0xc3b0; +op3val:0x7a0b; valaddr_reg:x2; val_offset:438*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 438*FLEN/8, x4, x5, x1) + +inst_179: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x249 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3b0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x20b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7249; op2val:0xc3b0; +op3val:0x7a0b; valaddr_reg:x2; val_offset:441*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x2, 441*FLEN/8, x4, x5, x1) + +inst_180: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x36f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x00d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x388 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b6f; op2val:0xbc0d; +op3val:0x7b88; valaddr_reg:x2; val_offset:444*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 444*FLEN/8, x4, x5, x1) + +inst_181: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x36f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x00d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x388 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b6f; op2val:0xbc0d; +op3val:0x7b88; valaddr_reg:x2; val_offset:447*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x2, 447*FLEN/8, x4, x5, x1) + +inst_182: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x36f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x00d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x388 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b6f; op2val:0xbc0d; +op3val:0x7b88; valaddr_reg:x2; val_offset:450*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x2, 450*FLEN/8, x4, x5, x1) + +inst_183: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x36f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x00d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x388 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b6f; op2val:0xbc0d; +op3val:0x7b88; valaddr_reg:x2; val_offset:453*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 453*FLEN/8, x4, x5, x1) + +inst_184: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x36f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x00d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x388 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b6f; op2val:0xbc0d; +op3val:0x7b88; valaddr_reg:x2; val_offset:456*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x2, 456*FLEN/8, x4, x5, x1) + +inst_185: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x181 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x01e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1ac and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7581; op2val:0xbc1e; +op3val:0x75ac; valaddr_reg:x2; val_offset:459*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 459*FLEN/8, x4, x5, x1) + +inst_186: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x181 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x01e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1ac and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7581; op2val:0xbc1e; +op3val:0x75ac; valaddr_reg:x2; val_offset:462*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x2, 462*FLEN/8, x4, x5, x1) + +inst_187: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x181 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x01e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1ac and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7581; op2val:0xbc1e; +op3val:0x75ac; valaddr_reg:x2; val_offset:465*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x2, 465*FLEN/8, x4, x5, x1) + +inst_188: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x181 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x01e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1ac and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7581; op2val:0xbc1e; +op3val:0x75ac; valaddr_reg:x2; val_offset:468*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 468*FLEN/8, x4, x5, x1) + +inst_189: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x181 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x01e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1ac and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7581; op2val:0xbc1e; +op3val:0x75ac; valaddr_reg:x2; val_offset:471*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x2, 471*FLEN/8, x4, x5, x1) + +inst_190: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x032 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1e9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x233 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7832; op2val:0xbde9; +op3val:0x7a33; valaddr_reg:x2; val_offset:474*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 474*FLEN/8, x4, x5, x1) + +inst_191: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x032 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1e9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x233 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7832; op2val:0xbde9; +op3val:0x7a33; valaddr_reg:x2; val_offset:477*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x2, 477*FLEN/8, x4, x5, x1) + +inst_192: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x032 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1e9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x233 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7832; op2val:0xbde9; +op3val:0x7a33; valaddr_reg:x2; val_offset:480*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x2, 480*FLEN/8, x4, x5, x1) + +inst_193: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x032 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1e9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x233 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7832; op2val:0xbde9; +op3val:0x7a33; valaddr_reg:x2; val_offset:483*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 483*FLEN/8, x4, x5, x1) + +inst_194: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x032 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1e9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x233 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7832; op2val:0xbde9; +op3val:0x7a33; valaddr_reg:x2; val_offset:486*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x2, 486*FLEN/8, x4, x5, x1) + +inst_195: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2e9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2ec and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1fb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ee9; op2val:0xc6ec; +op3val:0x79fb; valaddr_reg:x2; val_offset:489*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 489*FLEN/8, x4, x5, x1) + +inst_196: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2e9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2ec and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1fb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ee9; op2val:0xc6ec; +op3val:0x79fb; valaddr_reg:x2; val_offset:492*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x2, 492*FLEN/8, x4, x5, x1) + +inst_197: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2e9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2ec and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1fb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ee9; op2val:0xc6ec; +op3val:0x79fb; valaddr_reg:x2; val_offset:495*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x2, 495*FLEN/8, x4, x5, x1) + +inst_198: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2e9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2ec and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1fb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ee9; op2val:0xc6ec; +op3val:0x79fb; valaddr_reg:x2; val_offset:498*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 498*FLEN/8, x4, x5, x1) + +inst_199: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2e9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2ec and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1fb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ee9; op2val:0xc6ec; +op3val:0x79fb; valaddr_reg:x2; val_offset:501*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x2, 501*FLEN/8, x4, x5, x1) + +inst_200: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x050 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2df and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5f; op2val:0xbc50; +op3val:0x7adf; valaddr_reg:x2; val_offset:504*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 504*FLEN/8, x4, x5, x1) + +inst_201: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x050 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2df and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5f; op2val:0xbc50; +op3val:0x7adf; valaddr_reg:x2; val_offset:507*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x2, 507*FLEN/8, x4, x5, x1) + +inst_202: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x050 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2df and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5f; op2val:0xbc50; +op3val:0x7adf; valaddr_reg:x2; val_offset:510*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x2, 510*FLEN/8, x4, x5, x1) + +inst_203: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x050 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2df and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5f; op2val:0xbc50; +op3val:0x7adf; valaddr_reg:x2; val_offset:513*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 513*FLEN/8, x4, x5, x1) + +inst_204: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x050 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2df and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5f; op2val:0xbc50; +op3val:0x7adf; valaddr_reg:x2; val_offset:516*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x2, 516*FLEN/8, x4, x5, x1) + +inst_205: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x0b0 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x273 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x390 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x68b0; op2val:0xce73; +op3val:0x7b90; valaddr_reg:x2; val_offset:519*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 519*FLEN/8, x4, x5, x1) + +inst_206: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x0b0 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x273 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x390 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x68b0; op2val:0xce73; +op3val:0x7b90; valaddr_reg:x2; val_offset:522*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x2, 522*FLEN/8, x4, x5, x1) + +inst_207: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x0b0 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x273 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x390 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x68b0; op2val:0xce73; +op3val:0x7b90; valaddr_reg:x2; val_offset:525*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x2, 525*FLEN/8, x4, x5, x1) + +inst_208: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x0b0 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x273 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x390 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x68b0; op2val:0xce73; +op3val:0x7b90; valaddr_reg:x2; val_offset:528*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 528*FLEN/8, x4, x5, x1) + +inst_209: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x0b0 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x273 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x390 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x68b0; op2val:0xce73; +op3val:0x7b90; valaddr_reg:x2; val_offset:531*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x2, 531*FLEN/8, x4, x5, x1) + +inst_210: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1d5 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x379 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x173 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dd5; op2val:0xc379; +op3val:0x7573; valaddr_reg:x2; val_offset:534*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 534*FLEN/8, x4, x5, x1) + +inst_211: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1d5 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x379 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x173 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dd5; op2val:0xc379; +op3val:0x7573; valaddr_reg:x2; val_offset:537*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x2, 537*FLEN/8, x4, x5, x1) + +inst_212: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1d5 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x379 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x173 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dd5; op2val:0xc379; +op3val:0x7573; valaddr_reg:x2; val_offset:540*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x2, 540*FLEN/8, x4, x5, x1) + +inst_213: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1d5 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x379 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x173 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dd5; op2val:0xc379; +op3val:0x7573; valaddr_reg:x2; val_offset:543*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 543*FLEN/8, x4, x5, x1) + +inst_214: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1d5 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x379 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x173 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dd5; op2val:0xc379; +op3val:0x7573; valaddr_reg:x2; val_offset:546*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x2, 546*FLEN/8, x4, x5, x1) + +inst_215: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e2 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x203 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x357 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e2; op2val:0xbe03; +op3val:0x7b57; valaddr_reg:x2; val_offset:549*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 549*FLEN/8, x4, x5, x1) + +inst_216: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e2 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x203 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x357 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e2; op2val:0xbe03; +op3val:0x7b57; valaddr_reg:x2; val_offset:552*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x2, 552*FLEN/8, x4, x5, x1) + +inst_217: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e2 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x203 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x357 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e2; op2val:0xbe03; +op3val:0x7b57; valaddr_reg:x2; val_offset:555*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x2, 555*FLEN/8, x4, x5, x1) + +inst_218: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e2 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x203 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x357 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e2; op2val:0xbe03; +op3val:0x7b57; valaddr_reg:x2; val_offset:558*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 558*FLEN/8, x4, x5, x1) + +inst_219: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e2 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x203 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x357 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e2; op2val:0xbe03; +op3val:0x7b57; valaddr_reg:x2; val_offset:561*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x2, 561*FLEN/8, x4, x5, x1) + +inst_220: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0c3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ee and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fb; op2val:0xbcc3; +op3val:0x79ee; valaddr_reg:x2; val_offset:564*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 564*FLEN/8, x4, x5, x1) + +inst_221: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0c3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ee and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fb; op2val:0xbcc3; +op3val:0x79ee; valaddr_reg:x2; val_offset:567*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x2, 567*FLEN/8, x4, x5, x1) + +inst_222: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0c3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ee and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fb; op2val:0xbcc3; +op3val:0x79ee; valaddr_reg:x2; val_offset:570*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 570*FLEN/8, x4, x5, x1) + +inst_223: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0bd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x389 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5b; op2val:0xbcbd; +op3val:0x7b89; valaddr_reg:x2; val_offset:573*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x2, 573*FLEN/8, x4, x5, x1) + +inst_224: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0bd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x389 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5b; op2val:0xbcbd; +op3val:0x7b89; valaddr_reg:x2; val_offset:576*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 576*FLEN/8, x4, x5, x1) + +inst_225: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0bd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x389 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5b; op2val:0xbcbd; +op3val:0x7b89; valaddr_reg:x2; val_offset:579*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x2, 579*FLEN/8, x4, x5, x1) + +inst_226: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ea and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0fc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x360 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79ea; op2val:0xbcfc; +op3val:0x7b60; valaddr_reg:x2; val_offset:582*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x2, 582*FLEN/8, x4, x5, x1) + +inst_227: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ea and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0fc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x360 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79ea; op2val:0xbcfc; +op3val:0x7b60; valaddr_reg:x2; val_offset:585*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x2, 585*FLEN/8, x4, x5, x1) + +inst_228: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x334 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x005 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x33e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b34; op2val:0xb005; +op3val:0x6f3e; valaddr_reg:x2; val_offset:588*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x2, 588*FLEN/8, x4, x5, x1) + +inst_229: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x380 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x034 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3e3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7780; op2val:0xb834; +op3val:0x73e3; valaddr_reg:x2; val_offset:591*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x2, 591*FLEN/8, x4, x5, x1) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(30971,32,FLEN) +NAN_BOXED(30971,16,FLEN) +NAN_BOXED(31214,32,FLEN) +NAN_BOXED(30971,32,FLEN) +NAN_BOXED(48323,16,FLEN) +NAN_BOXED(30971,32,FLEN) +NAN_BOXED(30971,32,FLEN) +NAN_BOXED(48323,16,FLEN) +NAN_BOXED(31214,32,FLEN) +NAN_BOXED(30971,32,FLEN) +NAN_BOXED(30971,16,FLEN) +NAN_BOXED(30971,32,FLEN) +NAN_BOXED(30971,32,FLEN) +NAN_BOXED(48323,16,FLEN) +NAN_BOXED(31214,32,FLEN) +NAN_BOXED(31323,32,FLEN) +NAN_BOXED(48317,16,FLEN) +NAN_BOXED(31625,32,FLEN) +NAN_BOXED(31323,32,FLEN) +NAN_BOXED(48317,16,FLEN) +NAN_BOXED(31625,32,FLEN) +NAN_BOXED(31323,32,FLEN) +NAN_BOXED(48317,16,FLEN) +NAN_BOXED(48317,32,FLEN) +NAN_BOXED(31323,32,FLEN) +NAN_BOXED(48317,16,FLEN) +NAN_BOXED(31323,32,FLEN) +NAN_BOXED(31323,32,FLEN) +NAN_BOXED(31323,16,FLEN) +NAN_BOXED(31323,32,FLEN) +NAN_BOXED(31210,32,FLEN) +NAN_BOXED(48380,16,FLEN) +NAN_BOXED(48380,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31584,32,FLEN) +NAN_BOXED(31210,32,FLEN) +NAN_BOXED(48380,16,FLEN) +NAN_BOXED(31584,32,FLEN) +test_dataset_1: +NAN_BOXED(31210,32,FLEN) +NAN_BOXED(48380,16,FLEN) +NAN_BOXED(31584,32,FLEN) +NAN_BOXED(31210,32,FLEN) +NAN_BOXED(48380,16,FLEN) +NAN_BOXED(31584,32,FLEN) +NAN_BOXED(26476,32,FLEN) +NAN_BOXED(52226,16,FLEN) +NAN_BOXED(30578,32,FLEN) +NAN_BOXED(26476,32,FLEN) +NAN_BOXED(52226,16,FLEN) +NAN_BOXED(30578,32,FLEN) +NAN_BOXED(26476,32,FLEN) +NAN_BOXED(52226,16,FLEN) +NAN_BOXED(30578,32,FLEN) +NAN_BOXED(26476,32,FLEN) +NAN_BOXED(52226,16,FLEN) +NAN_BOXED(30578,32,FLEN) +NAN_BOXED(26476,32,FLEN) +NAN_BOXED(52226,16,FLEN) +NAN_BOXED(30578,32,FLEN) +NAN_BOXED(31627,32,FLEN) +NAN_BOXED(47488,16,FLEN) +NAN_BOXED(31024,32,FLEN) +NAN_BOXED(31627,32,FLEN) +NAN_BOXED(47488,16,FLEN) +NAN_BOXED(31024,32,FLEN) +test_dataset_2: +NAN_BOXED(31627,32,FLEN) +NAN_BOXED(47488,16,FLEN) +NAN_BOXED(31024,32,FLEN) +NAN_BOXED(31627,32,FLEN) +NAN_BOXED(47488,16,FLEN) +NAN_BOXED(31024,32,FLEN) +NAN_BOXED(31627,32,FLEN) +NAN_BOXED(47488,16,FLEN) +NAN_BOXED(31024,32,FLEN) +NAN_BOXED(31540,32,FLEN) +NAN_BOXED(45061,16,FLEN) +NAN_BOXED(28478,32,FLEN) +NAN_BOXED(31540,32,FLEN) +NAN_BOXED(45061,16,FLEN) +NAN_BOXED(28478,32,FLEN) +NAN_BOXED(31540,32,FLEN) +NAN_BOXED(45061,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31540,32,FLEN) +NAN_BOXED(45061,16,FLEN) +NAN_BOXED(28478,32,FLEN) +NAN_BOXED(31540,32,FLEN) +NAN_BOXED(45061,16,FLEN) +NAN_BOXED(28478,32,FLEN) +NAN_BOXED(30592,32,FLEN) +NAN_BOXED(47156,16,FLEN) +NAN_BOXED(29667,32,FLEN) +NAN_BOXED(30592,32,FLEN) +NAN_BOXED(47156,16,FLEN) +NAN_BOXED(29667,32,FLEN) +test_dataset_3: +NAN_BOXED(30592,16,FLEN) +NAN_BOXED(47156,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(30592,16,FLEN) +NAN_BOXED(47156,16,FLEN) +NAN_BOXED(29667,16,FLEN) +NAN_BOXED(30592,16,FLEN) +NAN_BOXED(47156,16,FLEN) +NAN_BOXED(29667,16,FLEN) +NAN_BOXED(30809,16,FLEN) +NAN_BOXED(48184,16,FLEN) +NAN_BOXED(30870,16,FLEN) +NAN_BOXED(30809,16,FLEN) +NAN_BOXED(48184,16,FLEN) +NAN_BOXED(30870,16,FLEN) +NAN_BOXED(30809,16,FLEN) +NAN_BOXED(48184,16,FLEN) +NAN_BOXED(30870,16,FLEN) +NAN_BOXED(30809,16,FLEN) +NAN_BOXED(48184,16,FLEN) +NAN_BOXED(30870,16,FLEN) +NAN_BOXED(30809,16,FLEN) +NAN_BOXED(48184,16,FLEN) +NAN_BOXED(30870,16,FLEN) +NAN_BOXED(25272,16,FLEN) +NAN_BOXED(52256,16,FLEN) +NAN_BOXED(29422,16,FLEN) +NAN_BOXED(25272,16,FLEN) +NAN_BOXED(52256,16,FLEN) +NAN_BOXED(29422,16,FLEN) +NAN_BOXED(25272,16,FLEN) +NAN_BOXED(52256,16,FLEN) +NAN_BOXED(29422,16,FLEN) +NAN_BOXED(25272,16,FLEN) +NAN_BOXED(52256,16,FLEN) +NAN_BOXED(29422,16,FLEN) +NAN_BOXED(25272,16,FLEN) +NAN_BOXED(52256,16,FLEN) +NAN_BOXED(29422,16,FLEN) +NAN_BOXED(29816,16,FLEN) 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+NAN_BOXED(31214,16,FLEN) +NAN_BOXED(31323,16,FLEN) +NAN_BOXED(48317,16,FLEN) +NAN_BOXED(31625,16,FLEN) +NAN_BOXED(31323,16,FLEN) +NAN_BOXED(48317,16,FLEN) +NAN_BOXED(31625,16,FLEN) +NAN_BOXED(31323,16,FLEN) +NAN_BOXED(48317,16,FLEN) +NAN_BOXED(31625,16,FLEN) +NAN_BOXED(31210,16,FLEN) +NAN_BOXED(48380,16,FLEN) +NAN_BOXED(31584,16,FLEN) +NAN_BOXED(31210,16,FLEN) +NAN_BOXED(48380,16,FLEN) +NAN_BOXED(31584,16,FLEN) +NAN_BOXED(31540,16,FLEN) +NAN_BOXED(45061,16,FLEN) +NAN_BOXED(28478,16,FLEN) +NAN_BOXED(30592,16,FLEN) +NAN_BOXED(47156,16,FLEN) +NAN_BOXED(29667,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x9_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x9_1: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_0: + .fill 24*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x5_0: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x5_1: + .fill 152*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fmadd_b6-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fmadd_b6-01.S new file mode 100644 index 000000000..66c20d685 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fmadd_b6-01.S @@ -0,0 +1,464 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 04:10:09 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fmadd.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fmadd.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fmadd_b6 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fmadd_b6) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x6,test_dataset_0) +RVTEST_SIGBASE(x7,signature_x7_1) + +inst_0: +// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==x31, rs2==x31, rs3==x5, rd==x4,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x31; op2:x31; op3:x5; dest:x4; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x6; val_offset:0*FLEN/8; rmval:dyn; +testreg:x14; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x4, x31, x31, x5, dyn, 0, 0, x6, 0*FLEN/8, x19, x7, x14) + +inst_1: +// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==x25, rs2==x18, rs3==x25, rd==x12,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x25; op2:x18; op3:x25; dest:x12; op1val:0x0; op2val:0xfbff; +op3val:0x0; valaddr_reg:x6; val_offset:3*FLEN/8; rmval:dyn; +testreg:x14; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x12, x25, x18, x25, dyn, 32, 0, x6, 3*FLEN/8, x19, x7, x14) + +inst_2: +// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==x30, rs2==x23, rs3==x15, rd==x30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x23; op3:x15; dest:x30; op1val:0x0; op2val:0xfbff; +op3val:0x0; valaddr_reg:x6; val_offset:6*FLEN/8; rmval:dyn; +testreg:x14; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x30, x30, x23, x15, dyn, 64, 0, x6, 6*FLEN/8, x19, x7, x14) + +inst_3: +// rs1 == rs2 == rs3 != rd, rs1==x2, rs2==x2, rs3==x2, rd==x0,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x2; op2:x2; op3:x2; dest:x0; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x6; val_offset:9*FLEN/8; rmval:dyn; +testreg:x14; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x0, x2, x2, x2, dyn, 96, 0, x6, 9*FLEN/8, x19, x7, x14) + +inst_4: +// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==x17, rs2==x11, rs3==x31, rd==x31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x17; op2:x11; op3:x31; dest:x31; op1val:0x0; op2val:0xfbff; +op3val:0x0; valaddr_reg:x6; val_offset:12*FLEN/8; rmval:dyn; +testreg:x14; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x17, x11, x31, dyn, 128, 0, x6, 12*FLEN/8, x19, x7, x14) + +inst_5: +// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==x1, rs2==x27, rs3==x23, rd==x27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x1; op2:x27; op3:x23; dest:x27; op1val:0x0; op2val:0x7bff; +op3val:0x0; valaddr_reg:x6; val_offset:15*FLEN/8; rmval:dyn; +testreg:x14; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x27, x1, x27, x23, dyn, 0, 0, x6, 15*FLEN/8, x19, x7, x14) + +inst_6: +// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==x28, rs2==x12, rs3==x10, rd==x16,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x28; op2:x12; op3:x10; dest:x16; op1val:0x0; op2val:0x7bff; +op3val:0x0; valaddr_reg:x6; val_offset:18*FLEN/8; rmval:dyn; +testreg:x14; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x16, x28, x12, x10, dyn, 32, 0, x6, 18*FLEN/8, x19, x7, x14) + +inst_7: +// rd == rs2 == rs3 != rs1, rs1==x5, rs2==x8, rs3==x8, rd==x8,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x5; op2:x8; op3:x8; dest:x8; op1val:0x0; op2val:0x7bff; +op3val:0x7bff; valaddr_reg:x6; val_offset:21*FLEN/8; rmval:dyn; +testreg:x14; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x8, x5, x8, x8, dyn, 64, 0, x6, 21*FLEN/8, x19, x7, x14) + +inst_8: +// rs1 == rd == rs3 != rs2, rs1==x13, rs2==x21, rs3==x13, rd==x13,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x13; op2:x21; op3:x13; dest:x13; op1val:0x0; op2val:0x7bff; +op3val:0x0; valaddr_reg:x6; val_offset:24*FLEN/8; rmval:dyn; +testreg:x14; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x13, x13, x21, x13, dyn, 96, 0, x6, 24*FLEN/8, x19, x7, x14) + +inst_9: +// rs1 == rs2 == rs3 == rd, rs1==x9, rs2==x9, rs3==x9, rd==x9,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x9; op2:x9; op3:x9; dest:x9; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x6; val_offset:27*FLEN/8; rmval:dyn; +testreg:x14; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x9, x9, x9, x9, dyn, 128, 0, x6, 27*FLEN/8, x19, x7, x14) + +inst_10: +// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==x27, rs2==x30, rs3==x30, rd==x28, +/* opcode: fmadd.h ; op1:x27; op2:x30; op3:x30; dest:x28; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x6; val_offset:30*FLEN/8; rmval:dyn; +testreg:x14; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x28, x27, x30, x30, dyn, 0, 0, x6, 30*FLEN/8, x19, x7, x14) + +inst_11: +// rs1 == rs2 == rd != rs3, rs1==x26, rs2==x26, rs3==x6, rd==x26, +/* opcode: fmadd.h ; op1:x26; op2:x26; op3:x6; dest:x26; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x6; val_offset:33*FLEN/8; rmval:dyn; +testreg:x14; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x26, x26, x26, x6, dyn, 0, 0, x6, 33*FLEN/8, x19, x7, x14) + +inst_12: +// rs1==x12, rs2==x3, rs3==x19, rd==x25, +/* opcode: fmadd.h ; op1:x12; op2:x3; op3:x19; dest:x25; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x6; val_offset:36*FLEN/8; rmval:dyn; +testreg:x14; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x25, x12, x3, x19, dyn, 0, 0, x6, 36*FLEN/8, x19, x7, x14) + +inst_13: +// rs1==x15, rs2==x16, rs3==x3, rd==x10, +/* opcode: fmadd.h ; op1:x15; op2:x16; op3:x3; dest:x10; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x6; val_offset:39*FLEN/8; rmval:dyn; +testreg:x14; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x10, x15, x16, x3, dyn, 0, 0, x6, 39*FLEN/8, x19, x7, x14) +RVTEST_VALBASEUPD(x8,test_dataset_1) + +inst_14: +// rs1==x29, rs2==x6, rs3==x24, rd==x20, +/* opcode: fmadd.h ; op1:x29; op2:x6; op3:x24; dest:x20; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x8; val_offset:0*FLEN/8; rmval:dyn; +testreg:x14; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x20, x29, x6, x24, dyn, 0, 0, x8, 0*FLEN/8, x11, x7, x14) +RVTEST_SIGBASE(x9,signature_x9_0) + +inst_15: +// rs1==x0, rs2==x14, rs3==x27, rd==x1, +/* opcode: fmadd.h ; op1:x0; op2:x14; op3:x27; dest:x1; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x8; val_offset:3*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x1, x0, x14, x27, dyn, 0, 0, x8, 3*FLEN/8, x11, x9, x12) + +inst_16: +// rs1==x16, rs2==x0, rs3==x21, rd==x6, +/* opcode: fmadd.h ; op1:x16; op2:x0; op3:x21; dest:x6; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x8; val_offset:6*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x6, x16, x0, x21, dyn, 0, 0, x8, 6*FLEN/8, x11, x9, x12) + +inst_17: +// rs1==x10, rs2==x15, rs3==x1, rd==x19, +/* opcode: fmadd.h ; op1:x10; op2:x15; op3:x1; dest:x19; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x8; val_offset:9*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x19, x10, x15, x1, dyn, 0, 0, x8, 9*FLEN/8, x11, x9, x12) + +inst_18: +// rs1==x18, rs2==x10, rs3==x16, rd==x17, +/* opcode: fmadd.h ; op1:x18; op2:x10; op3:x16; dest:x17; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x8; val_offset:12*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x17, x18, x10, x16, dyn, 0, 0, x8, 12*FLEN/8, x11, x9, x12) + +inst_19: +// rs1==x22, rs2==x4, rs3==x12, rd==x7, +/* opcode: fmadd.h ; op1:x22; op2:x4; op3:x12; dest:x7; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x8; val_offset:15*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x7, x22, x4, x12, dyn, 0, 0, x8, 15*FLEN/8, x11, x9, x12) + +inst_20: +// rs1==x7, rs2==x19, rs3==x11, rd==x5, +/* opcode: fmadd.h ; op1:x7; op2:x19; op3:x11; dest:x5; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x8; val_offset:18*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x5, x7, x19, x11, dyn, 0, 0, x8, 18*FLEN/8, x11, x9, x12) + +inst_21: +// rs1==x23, rs2==x7, rs3==x4, rd==x14, +/* opcode: fmadd.h ; op1:x23; op2:x7; op3:x4; dest:x14; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x8; val_offset:21*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x14, x23, x7, x4, dyn, 0, 0, x8, 21*FLEN/8, x11, x9, x12) + +inst_22: +// rs1==x14, rs2==x28, rs3==x22, rd==x3, +/* opcode: fmadd.h ; op1:x14; op2:x28; op3:x22; dest:x3; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x8; val_offset:24*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x3, x14, x28, x22, dyn, 0, 0, x8, 24*FLEN/8, x11, x9, x12) + +inst_23: +// rs1==x24, rs2==x29, rs3==x20, rd==x21, +/* opcode: fmadd.h ; op1:x24; op2:x29; op3:x20; dest:x21; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x8; val_offset:27*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x21, x24, x29, x20, dyn, 0, 0, x8, 27*FLEN/8, x11, x9, x12) + +inst_24: +// rs1==x3, rs2==x25, rs3==x29, rd==x24, +/* opcode: fmadd.h ; op1:x3; op2:x25; op3:x29; dest:x24; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x8; val_offset:30*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x24, x3, x25, x29, dyn, 0, 0, x8, 30*FLEN/8, x11, x9, x12) + +inst_25: +// rs1==x21, rs2==x24, rs3==x0, rd==x2, +/* opcode: fmadd.h ; op1:x21; op2:x24; op3:x0; dest:x2; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x8; val_offset:33*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x2, x21, x24, x0, dyn, 0, 0, x8, 33*FLEN/8, x11, x9, x12) +RVTEST_VALBASEUPD(x7,test_dataset_2) + +inst_26: +// rs1==x6, rs2==x22, rs3==x17, rd==x15, +/* opcode: fmadd.h ; op1:x6; op2:x22; op3:x17; dest:x15; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x7; val_offset:0*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x15, x6, x22, x17, dyn, 0, 0, x7, 0*FLEN/8, x10, x9, x12) + +inst_27: +// rs1==x8, rs2==x13, rs3==x28, rd==x11, +/* opcode: fmadd.h ; op1:x8; op2:x13; op3:x28; dest:x11; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x7; val_offset:3*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x11, x8, x13, x28, dyn, 0, 0, x7, 3*FLEN/8, x10, x9, x12) + +inst_28: +// rs1==x4, rs2==x20, rs3==x18, rd==x22, +/* opcode: fmadd.h ; op1:x4; op2:x20; op3:x18; dest:x22; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x7; val_offset:6*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x22, x4, x20, x18, dyn, 0, 0, x7, 6*FLEN/8, x10, x9, x3) +RVTEST_SIGBASE(x2,signature_x2_0) + +inst_29: +// rs1==x20, rs2==x5, rs3==x14, rd==x18, +/* opcode: fmadd.h ; op1:x20; op2:x5; op3:x14; dest:x18; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x7; val_offset:9*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x18, x20, x5, x14, dyn, 0, 0, x7, 9*FLEN/8, x10, x2, x3) + +inst_30: +// rs1==x19, rs2==x1, rs3==x7, rd==x23, +/* opcode: fmadd.h ; op1:x19; op2:x1; op3:x7; dest:x23; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x7; val_offset:12*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x23, x19, x1, x7, dyn, 0, 0, x7, 12*FLEN/8, x10, x2, x3) + +inst_31: +// rs1==x11, rs2==x17, rs3==x26, rd==x29, +/* opcode: fmadd.h ; op1:x11; op2:x17; op3:x26; dest:x29; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x7; val_offset:15*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x29, x11, x17, x26, dyn, 0, 0, x7, 15*FLEN/8, x10, x2, x3) + +inst_32: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfbff; +op3val:0x0; valaddr_reg:x7; val_offset:18*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x7, 18*FLEN/8, x10, x2, x3) + +inst_33: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfbff; +op3val:0x0; valaddr_reg:x7; val_offset:21*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x7, 21*FLEN/8, x10, x2, x3) + +inst_34: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7bff; +op3val:0x0; valaddr_reg:x7; val_offset:24*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x7, 24*FLEN/8, x10, x2, x3) + +inst_35: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7bff; +op3val:0x0; valaddr_reg:x7; val_offset:27*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x7, 27*FLEN/8, x10, x2, x3) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +test_dataset_1: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +test_dataset_2: +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(0,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x7_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x7_1: + .fill 30*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x9_0: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_0: + .fill 14*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fmadd_b7-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fmadd_b7-01.S new file mode 100644 index 000000000..5eaf62cc7 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fmadd_b7-01.S @@ -0,0 +1,786 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 04:10:09 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fmadd.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fmadd.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fmadd_b7 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fmadd_b7) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x7,test_dataset_0) +RVTEST_SIGBASE(x2,signature_x2_1) + +inst_0: +// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==x19, rs2==x19, rs3==x7, rd==x4,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0c3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ee and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x19; op2:x19; op3:x7; dest:x4; op1val:0x78fb; op2val:0x78fb; +op3val:0x79ee; valaddr_reg:x7; val_offset:0*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x4, x19, x19, x7, dyn, 96, 0, x7, 0*FLEN/8, x11, x2, x3) + +inst_1: +// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==x28, rs2==x9, rs3==x28, rd==x27,fs1 == 0 and fe1 == 0x1e and fm1 == 0x25b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0bd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x389 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x28; op2:x9; op3:x28; dest:x27; op1val:0x7a5b; op2val:0xbcbd; +op3val:0x7a5b; valaddr_reg:x7; val_offset:3*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x27, x28, x9, x28, dyn, 96, 0, x7, 3*FLEN/8, x11, x2, x3) + +inst_2: +// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==x1, rs2==x5, rs3==x11, rd==x1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ea and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0fc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x360 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x1; op2:x5; op3:x11; dest:x1; op1val:0x79ea; op2val:0xbcfc; +op3val:0x7b60; valaddr_reg:x7; val_offset:6*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x1, x1, x5, x11, dyn, 96, 0, x7, 6*FLEN/8, x11, x2, x3) + +inst_3: +// rs1 == rs2 == rs3 != rd, rs1==x22, rs2==x22, rs3==x22, rd==x31,fs1 == 0 and fe1 == 0x19 and fm1 == 0x36c and fs2 == 1 and fe2 == 0x13 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x372 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x22; op2:x22; op3:x22; dest:x31; op1val:0x676c; op2val:0x676c; +op3val:0x676c; valaddr_reg:x7; val_offset:9*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x22, x22, x22, dyn, 96, 0, x7, 9*FLEN/8, x11, x2, x3) + +inst_4: +// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==x8, rs2==x15, rs3==x30, rd==x30,fs1 == 0 and fe1 == 0x1e and fm1 == 0x38b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x180 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x130 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x8; op2:x15; op3:x30; dest:x30; op1val:0x7b8b; op2val:0xb980; +op3val:0x7930; valaddr_reg:x7; val_offset:12*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x30, x8, x15, x30, dyn, 96, 0, x7, 12*FLEN/8, x11, x2, x3) + +inst_5: +// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==x31, rs2==x17, rs3==x5, rd==x17,fs1 == 0 and fe1 == 0x1e and fm1 == 0x334 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x005 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x33e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x31; op2:x17; op3:x5; dest:x17; op1val:0x7b34; op2val:0xb005; +op3val:0x6f3e; valaddr_reg:x7; val_offset:15*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x17, x31, x17, x5, dyn, 96, 0, x7, 15*FLEN/8, x11, x2, x3) + +inst_6: +// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==x26, rs2==x21, rs3==x25, rd==x6,fs1 == 0 and fe1 == 0x1d and fm1 == 0x380 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x034 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3e3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x26; op2:x21; op3:x25; dest:x6; op1val:0x7780; op2val:0xb834; +op3val:0x73e3; valaddr_reg:x7; val_offset:18*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x6, x26, x21, x25, dyn, 96, 0, x7, 18*FLEN/8, x11, x2, x3) + +inst_7: +// rd == rs2 == rs3 != rs1, rs1==x20, rs2==x10, rs3==x10, rd==x10,fs1 == 0 and fe1 == 0x1e and fm1 == 0x059 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x038 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x096 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x20; op2:x10; op3:x10; dest:x10; op1val:0x7859; op2val:0xbc38; +op3val:0xbc38; valaddr_reg:x7; val_offset:21*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x10, x20, x10, x10, dyn, 96, 0, x7, 21*FLEN/8, x11, x2, x3) + +inst_8: +// rs1 == rd == rs3 != rs2, rs1==x29, rs2==x23, rs3==x29, rd==x29,fs1 == 0 and fe1 == 0x18 and fm1 == 0x2b8 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x020 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2ee and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x29; op2:x23; op3:x29; dest:x29; op1val:0x62b8; op2val:0xcc20; +op3val:0x62b8; valaddr_reg:x7; val_offset:24*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x29, x29, x23, x29, dyn, 96, 0, x7, 24*FLEN/8, x11, x2, x3) + +inst_9: +// rs1 == rs2 == rs3 == rd, rs1==x12, rs2==x12, rs3==x12, rd==x12,fs1 == 0 and fe1 == 0x1d and fm1 == 0x078 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x28e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x353 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x12; op2:x12; op3:x12; dest:x12; op1val:0x7478; op2val:0x7478; +op3val:0x7478; valaddr_reg:x7; val_offset:27*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x12, x12, x12, x12, dyn, 96, 0, x7, 27*FLEN/8, x11, x2, x3) + +inst_10: +// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==x30, rs2==x18, rs3==x18, rd==x14,fs1 == 0 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2ab and fs3 == 0 and fe3 == 0x1c and fm3 == 0x11a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x18; op3:x18; dest:x14; op1val:0x7a1f; op2val:0xb2ab; +op3val:0xb2ab; valaddr_reg:x7; val_offset:30*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x14, x30, x18, x18, dyn, 96, 0, x7, 30*FLEN/8, x11, x2, x3) +RVTEST_VALBASEUPD(x14,test_dataset_1) + +inst_11: +// rs1 == rs2 == rd != rs3, rs1==x24, rs2==x24, rs3==x17, rd==x24,fs1 == 0 and fe1 == 0x1e and fm1 == 0x25f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x192 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x070 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x24; op2:x24; op3:x17; dest:x24; op1val:0x7a5f; op2val:0x7a5f; +op3val:0x7070; valaddr_reg:x14; val_offset:0*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x24, x24, x24, x17, dyn, 96, 0, x14, 0*FLEN/8, x17, x2, x3) + +inst_12: +// rs1==x7, rs2==x1, rs3==x20, rd==x8,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ef and fs2 == 1 and fe2 == 0x0c and fm2 == 0x291 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x00d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x7; op2:x1; op3:x20; dest:x8; op1val:0x78ef; op2val:0xb291; +op3val:0x700d; valaddr_reg:x14; val_offset:3*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x8, x7, x1, x20, dyn, 96, 0, x14, 3*FLEN/8, x17, x2, x12) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_13: +// rs1==x9, rs2==x13, rs3==x27, rd==x15,fs1 == 0 and fe1 == 0x15 and fm1 == 0x354 and fs2 == 1 and fe2 == 0x17 and fm2 == 0x39b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x9; op2:x13; op3:x27; dest:x15; op1val:0x5754; op2val:0xdf9b; +op3val:0x7af7; valaddr_reg:x14; val_offset:6*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x15, x9, x13, x27, dyn, 96, 0, x14, 6*FLEN/8, x17, x1, x12) + +inst_14: +// rs1==x21, rs2==x30, rs3==x6, rd==x5,fs1 == 0 and fe1 == 0x1c and fm1 == 0x2b3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x01d and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2e4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x21; op2:x30; op3:x6; dest:x5; op1val:0x72b3; op2val:0xbc1d; +op3val:0x72e4; valaddr_reg:x14; val_offset:9*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x5, x21, x30, x6, dyn, 96, 0, x14, 9*FLEN/8, x17, x1, x12) + +inst_15: +// rs1==x0, rs2==x26, rs3==x15, rd==x9,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3db and fs2 == 1 and fe2 == 0x0e and fm2 == 0x31a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x0; op2:x26; op3:x15; dest:x9; op1val:0x0; op2val:0xbb1a; +op3val:0x7af9; valaddr_reg:x14; val_offset:12*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x9, x0, x26, x15, dyn, 96, 0, x14, 12*FLEN/8, x17, x1, x12) + +inst_16: +// rs1==x27, rs2==x31, rs3==x9, rd==x3,fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a0 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2a5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x27; op2:x31; op3:x9; dest:x3; op1val:0x74a0; op2val:0xc2a5; +op3val:0x7bb0; valaddr_reg:x14; val_offset:15*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x3, x27, x31, x9, dyn, 96, 0, x14, 15*FLEN/8, x17, x1, x12) + +inst_17: +// rs1==x11, rs2==x3, rs3==x31, rd==x16,fs1 == 0 and fe1 == 0x1e and fm1 == 0x04f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x107 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x16b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x11; op2:x3; op3:x31; dest:x16; op1val:0x784f; op2val:0xbd07; +op3val:0x796b; valaddr_reg:x14; val_offset:18*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x16, x11, x3, x31, dyn, 96, 0, x14, 18*FLEN/8, x17, x1, x12) + +inst_18: +// rs1==x10, rs2==x7, rs3==x16, rd==x26,fs1 == 0 and fe1 == 0x1c and fm1 == 0x28c and fs2 == 1 and fe2 == 0x11 and fm2 == 0x098 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x386 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x10; op2:x7; op3:x16; dest:x26; op1val:0x728c; op2val:0xc498; +op3val:0x7b86; valaddr_reg:x14; val_offset:21*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x26, x10, x7, x16, dyn, 96, 0, x14, 21*FLEN/8, x17, x1, x12) + +inst_19: +// rs1==x6, rs2==x4, rs3==x19, rd==x23,fs1 == 0 and fe1 == 0x1e and fm1 == 0x185 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x199 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ba and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x6; op2:x4; op3:x19; dest:x23; op1val:0x7985; op2val:0xbd99; +op3val:0x7bba; valaddr_reg:x14; val_offset:24*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x23, x6, x4, x19, dyn, 96, 0, x14, 24*FLEN/8, x17, x1, x12) + +inst_20: +// rs1==x18, rs2==x11, rs3==x4, rd==x28,fs1 == 0 and fe1 == 0x1e and fm1 == 0x325 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x159 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0c7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x18; op2:x11; op3:x4; dest:x28; op1val:0x7b25; op2val:0xb559; +op3val:0x74c7; valaddr_reg:x14; val_offset:27*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x28, x18, x11, x4, dyn, 96, 0, x14, 27*FLEN/8, x17, x1, x12) +RVTEST_VALBASEUPD(x7,test_dataset_2) + +inst_21: +// rs1==x25, rs2==x16, rs3==x8, rd==x18,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c6 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x35a and fs3 == 0 and fe3 == 0x1c and fm3 == 0x14e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x25; op2:x16; op3:x8; dest:x18; op1val:0x75c6; op2val:0xb75a; +op3val:0x714e; valaddr_reg:x7; val_offset:0*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x18, x25, x16, x8, dyn, 96, 0, x7, 0*FLEN/8, x10, x1, x12) + +inst_22: +// rs1==x14, rs2==x27, rs3==x21, rd==x2,fs1 == 0 and fe1 == 0x1c and fm1 == 0x0a9 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x327 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x02a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x14; op2:x27; op3:x21; dest:x2; op1val:0x70a9; op2val:0xb727; +op3val:0x6c2a; valaddr_reg:x7; val_offset:3*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x2, x14, x27, x21, dyn, 96, 0, x7, 3*FLEN/8, x10, x1, x12) + +inst_23: +// rs1==x15, rs2==x29, rs3==x0, rd==x13,fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d1 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0d2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x15; op2:x29; op3:x0; dest:x13; op1val:0x74d1; op2val:0xc000; +op3val:0x0; valaddr_reg:x7; val_offset:6*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x13, x15, x29, x0, dyn, 96, 0, x7, 6*FLEN/8, x10, x1, x12) + +inst_24: +// rs1==x4, rs2==x2, rs3==x23, rd==x25,fs1 == 0 and fe1 == 0x16 and fm1 == 0x2f4 and fs2 == 1 and fe2 == 0x16 and fm2 == 0x23b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x16b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x4; op2:x2; op3:x23; dest:x25; op1val:0x5af4; op2val:0xda3b; +op3val:0x796b; valaddr_reg:x7; val_offset:9*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x25, x4, x2, x23, dyn, 96, 0, x7, 9*FLEN/8, x10, x1, x9) + +inst_25: +// rs1==x13, rs2==x6, rs3==x1, rd==x22,fs1 == 0 and fe1 == 0x1d and fm1 == 0x167 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x356 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0f5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x13; op2:x6; op3:x1; dest:x22; op1val:0x7567; op2val:0xbb56; +op3val:0x74f5; valaddr_reg:x7; val_offset:12*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x22, x13, x6, x1, dyn, 96, 0, x7, 12*FLEN/8, x10, x1, x9) + +inst_26: +// rs1==x16, rs2==x8, rs3==x24, rd==x19,fs1 == 0 and fe1 == 0x1e and fm1 == 0x28b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0b2 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3b0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x16; op2:x8; op3:x24; dest:x19; op1val:0x7a8b; op2val:0xb8b2; +op3val:0x77b0; valaddr_reg:x7; val_offset:15*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x19, x16, x8, x24, dyn, 96, 0, x7, 15*FLEN/8, x10, x1, x9) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_27: +// rs1==x5, rs2==x14, rs3==x13, rd==x21,fs1 == 0 and fe1 == 0x1d and fm1 == 0x10c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x218 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3b2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x5; op2:x14; op3:x13; dest:x21; op1val:0x750c; op2val:0xbe18; +op3val:0x77b2; valaddr_reg:x7; val_offset:18*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x21, x5, x14, x13, dyn, 96, 0, x7, 18*FLEN/8, x10, x1, x9) + +inst_28: +// rs1==x23, rs2==x0, rs3==x26, rd==x20,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a2 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x12d and fs3 == 0 and fe3 == 0x1a and fm3 == 0x34b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x23; op2:x0; op3:x26; dest:x20; op1val:0x79a2; op2val:0x0; +op3val:0x6b4b; valaddr_reg:x7; val_offset:21*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x20, x23, x0, x26, dyn, 96, 0, x7, 21*FLEN/8, x10, x1, x9) + +inst_29: +// rs1==x3, rs2==x28, rs3==x14, rd==x0,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3cc and fs2 == 1 and fe2 == 0x09 and fm2 == 0x201 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x1da and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x3; op2:x28; op3:x14; dest:x0; op1val:0x7bcc; op2val:0xa601; +op3val:0x65da; valaddr_reg:x7; val_offset:24*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x0, x3, x28, x14, dyn, 96, 0, x7, 24*FLEN/8, x10, x1, x9) + +inst_30: +// rs1==x17, rs2==x20, rs3==x2, rd==x11,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x081 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2c1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x17; op2:x20; op3:x2; dest:x11; op1val:0x79fe; op2val:0xbc81; +op3val:0x7ac1; valaddr_reg:x7; val_offset:27*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x11, x17, x20, x2, dyn, 96, 0, x7, 27*FLEN/8, x10, x1, x9) +RVTEST_VALBASEUPD(x3,test_dataset_3) + +inst_31: +// rs1==x2, rs2==x25, rs3==x3, rd==x7,fs1 == 0 and fe1 == 0x19 and fm1 == 0x0a0 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x172 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x24c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x2; op2:x25; op3:x3; dest:x7; op1val:0x64a0; op2val:0xd172; +op3val:0x7a4c; valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x7, x2, x25, x3, dyn, 96, 0, x3, 0*FLEN/8, x4, x1, x9) + +inst_32: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1db and fs2 == 1 and fe2 == 0x0f and fm2 == 0x251 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75db; op2val:0xbe51; +op3val:0x78a0; valaddr_reg:x3; val_offset:3*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x3, 3*FLEN/8, x4, x1, x9) + +inst_33: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x0a7 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x123 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x1fa and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x60a7; op2val:0xc523; +op3val:0x69fa; valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x3, 6*FLEN/8, x4, x1, x9) + +inst_34: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1c9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x147 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3a3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71c9; op2val:0xc547; +op3val:0x7ba3; valaddr_reg:x3; val_offset:9*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x3, 9*FLEN/8, x4, x1, x9) + +inst_35: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x249 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3b0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x20b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7249; op2val:0xc3b0; +op3val:0x7a0b; valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x3, 12*FLEN/8, x4, x1, x9) + +inst_36: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x36f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x00d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x388 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b6f; op2val:0xbc0d; +op3val:0x7b88; valaddr_reg:x3; val_offset:15*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x3, 15*FLEN/8, x4, x1, x9) + +inst_37: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x181 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x01e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1ac and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7581; op2val:0xbc1e; +op3val:0x75ac; valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x3, 18*FLEN/8, x4, x1, x9) + +inst_38: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x032 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1e9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x233 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7832; op2val:0xbde9; +op3val:0x7a33; valaddr_reg:x3; val_offset:21*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x3, 21*FLEN/8, x4, x1, x9) + +inst_39: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2e9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2ec and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1fb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ee9; op2val:0xc6ec; +op3val:0x79fb; valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x3, 24*FLEN/8, x4, x1, x9) + +inst_40: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x050 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2df and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5f; op2val:0xbc50; +op3val:0x7adf; valaddr_reg:x3; val_offset:27*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x3, 27*FLEN/8, x4, x1, x9) + +inst_41: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x0b0 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x273 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x390 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x68b0; op2val:0xce73; +op3val:0x7b90; valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x3, 30*FLEN/8, x4, x1, x9) + +inst_42: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1d5 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x373 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x173 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dd5; op2val:0xc373; +op3val:0x7573; valaddr_reg:x3; val_offset:33*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x3, 33*FLEN/8, x4, x1, x9) + +inst_43: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e2 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x357 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e2; op2val:0xbe01; +op3val:0x7b57; valaddr_reg:x3; val_offset:36*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x3, 36*FLEN/8, x4, x1, x9) + +inst_44: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x16f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x16e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x363 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x756f; op2val:0xc16e; +op3val:0x7b63; valaddr_reg:x3; val_offset:39*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x3, 39*FLEN/8, x4, x1, x9) + +inst_45: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x05b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x092 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x785b; op2val:0xb892; +op3val:0x74ff; valaddr_reg:x3; val_offset:42*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x3, 42*FLEN/8, x4, x1, x9) + +inst_46: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x111 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x075 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x1ad and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7511; op2val:0xb875; +op3val:0x71ad; valaddr_reg:x3; val_offset:45*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x3, 45*FLEN/8, x4, x1, x9) + +inst_47: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x100 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x390 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0c3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d00; op2val:0xbf90; +op3val:0x70c3; valaddr_reg:x3; val_offset:48*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x3, 48*FLEN/8, x4, x1, x9) + +inst_48: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x182 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1c7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3f8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7982; op2val:0xbdc7; +op3val:0x7bf8; valaddr_reg:x3; val_offset:51*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x3, 51*FLEN/8, x4, x1, x9) + +inst_49: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x12a and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0cf and fs3 == 0 and fe3 == 0x1a and fm3 == 0x236 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x712a; op2val:0xb4cf; +op3val:0x6a36; valaddr_reg:x3; val_offset:54*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x3, 54*FLEN/8, x4, x1, x9) + +inst_50: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x053 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x044 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7be3; op2val:0xb853; +op3val:0x7844; valaddr_reg:x3; val_offset:57*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x3, 57*FLEN/8, x4, x1, x9) + +inst_51: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x27d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0ad and fs3 == 0 and fe3 == 0x1c and fm3 == 0x397 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x767d; op2val:0xb8ad; +op3val:0x7397; valaddr_reg:x3; val_offset:60*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x3, 60*FLEN/8, x4, x1, x9) + +inst_52: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0bf and fs2 == 1 and fe2 == 0x0f and fm2 == 0x190 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x29b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78bf; op2val:0xbd90; +op3val:0x7a9b; valaddr_reg:x3; val_offset:63*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x3, 63*FLEN/8, x4, x1, x9) + +inst_53: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x367 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2be and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7749; op2val:0xbb67; +op3val:0x76be; valaddr_reg:x3; val_offset:66*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x3, 66*FLEN/8, x4, x1, x9) + +inst_54: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x320 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x01c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x353 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6b20; op2val:0xcc1c; +op3val:0x7b53; valaddr_reg:x3; val_offset:69*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x3, 69*FLEN/8, x4, x1, x9) + +inst_55: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x030 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x389 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3e4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6830; op2val:0xcb89; +op3val:0x77e4; valaddr_reg:x3; val_offset:72*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x3, 72*FLEN/8, x4, x1, x9) + +inst_56: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0c3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ee and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fb; op2val:0xbcc3; +op3val:0x79ee; valaddr_reg:x3; val_offset:75*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x3, 75*FLEN/8, x4, x1, x9) + +inst_57: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0bd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x389 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5b; op2val:0xbcbd; +op3val:0x7b89; valaddr_reg:x3; val_offset:78*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x3, 78*FLEN/8, x4, x1, x9) + +inst_58: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x36c and fs2 == 1 and fe2 == 0x13 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x372 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x676c; op2val:0xcc02; +op3val:0x7772; valaddr_reg:x3; val_offset:81*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x3, 81*FLEN/8, x4, x1, x9) + +inst_59: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x059 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x038 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x096 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7859; op2val:0xbc38; +op3val:0x7896; valaddr_reg:x3; val_offset:84*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x3, 84*FLEN/8, x4, x1, x9) + +inst_60: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x2b8 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x020 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2ee and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x62b8; op2val:0xcc20; +op3val:0x72ee; valaddr_reg:x3; val_offset:87*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x3, 87*FLEN/8, x4, x1, x9) + +inst_61: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x078 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x28e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x353 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7478; op2val:0xc28e; +op3val:0x7b53; valaddr_reg:x3; val_offset:90*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x3, 90*FLEN/8, x4, x1, x9) + +inst_62: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2ab and fs3 == 0 and fe3 == 0x1c and fm3 == 0x11a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a1f; op2val:0xb2ab; +op3val:0x711a; valaddr_reg:x3; val_offset:93*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x3, 93*FLEN/8, x4, x1, x9) + +inst_63: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x192 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x070 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5f; op2val:0xb192; +op3val:0x7070; valaddr_reg:x3; val_offset:96*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x3, 96*FLEN/8, x4, x1, x9) + +inst_64: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3db and fs2 == 1 and fe2 == 0x0e and fm2 == 0x31a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bdb; op2val:0xbb1a; +op3val:0x7af9; valaddr_reg:x3; val_offset:99*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x3, 99*FLEN/8, x4, x1, x9) + +inst_65: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d1 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0d2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74d1; op2val:0xc000; +op3val:0x78d2; valaddr_reg:x3; val_offset:102*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x3, 102*FLEN/8, x4, x1, x9) + +inst_66: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a2 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x12d and fs3 == 0 and fe3 == 0x1a and fm3 == 0x34b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79a2; op2val:0xad2d; +op3val:0x6b4b; valaddr_reg:x3; val_offset:105*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x3, 105*FLEN/8, x4, x1, x9) + +inst_67: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3cc and fs2 == 1 and fe2 == 0x09 and fm2 == 0x201 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x1da and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bcc; op2val:0xa601; +op3val:0x65da; valaddr_reg:x3; val_offset:108*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x3, 108*FLEN/8, x4, x1, x9) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(30971,32,FLEN) +NAN_BOXED(30971,16,FLEN) +NAN_BOXED(31214,32,FLEN) +NAN_BOXED(31323,32,FLEN) +NAN_BOXED(48317,16,FLEN) +NAN_BOXED(31323,32,FLEN) +NAN_BOXED(31210,32,FLEN) +NAN_BOXED(48380,16,FLEN) +NAN_BOXED(31584,32,FLEN) +NAN_BOXED(26476,32,FLEN) +NAN_BOXED(26476,16,FLEN) +NAN_BOXED(26476,32,FLEN) +NAN_BOXED(31627,32,FLEN) +NAN_BOXED(47488,16,FLEN) +NAN_BOXED(31024,32,FLEN) +NAN_BOXED(31540,32,FLEN) +NAN_BOXED(45061,16,FLEN) +NAN_BOXED(28478,32,FLEN) +NAN_BOXED(30592,32,FLEN) +NAN_BOXED(47156,16,FLEN) +NAN_BOXED(29667,32,FLEN) +NAN_BOXED(30809,32,FLEN) +NAN_BOXED(48184,16,FLEN) +NAN_BOXED(48184,32,FLEN) +NAN_BOXED(25272,32,FLEN) +NAN_BOXED(52256,16,FLEN) +NAN_BOXED(25272,32,FLEN) +NAN_BOXED(29816,32,FLEN) +NAN_BOXED(29816,16,FLEN) +NAN_BOXED(29816,32,FLEN) +NAN_BOXED(31263,32,FLEN) +NAN_BOXED(45739,16,FLEN) +NAN_BOXED(45739,32,FLEN) +test_dataset_1: +NAN_BOXED(31327,32,FLEN) +NAN_BOXED(31327,16,FLEN) +NAN_BOXED(28784,32,FLEN) +NAN_BOXED(30959,32,FLEN) +NAN_BOXED(45713,16,FLEN) +NAN_BOXED(28685,32,FLEN) +NAN_BOXED(22356,32,FLEN) +NAN_BOXED(57243,16,FLEN) +NAN_BOXED(31479,32,FLEN) +NAN_BOXED(29363,32,FLEN) +NAN_BOXED(48157,16,FLEN) +NAN_BOXED(29412,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(47898,16,FLEN) +NAN_BOXED(31481,32,FLEN) +NAN_BOXED(29856,32,FLEN) +NAN_BOXED(49829,16,FLEN) +NAN_BOXED(31664,32,FLEN) +NAN_BOXED(30799,32,FLEN) +NAN_BOXED(48391,16,FLEN) +NAN_BOXED(31083,32,FLEN) +NAN_BOXED(29324,32,FLEN) +NAN_BOXED(50328,16,FLEN) +NAN_BOXED(31622,32,FLEN) +NAN_BOXED(31109,32,FLEN) +NAN_BOXED(48537,16,FLEN) +NAN_BOXED(31674,32,FLEN) +NAN_BOXED(31525,32,FLEN) +NAN_BOXED(46425,16,FLEN) +NAN_BOXED(29895,32,FLEN) +test_dataset_2: +NAN_BOXED(30150,32,FLEN) +NAN_BOXED(46938,16,FLEN) +NAN_BOXED(29006,32,FLEN) +NAN_BOXED(28841,32,FLEN) +NAN_BOXED(46887,16,FLEN) +NAN_BOXED(27690,32,FLEN) +NAN_BOXED(29905,32,FLEN) +NAN_BOXED(49152,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(23284,32,FLEN) +NAN_BOXED(55867,16,FLEN) +NAN_BOXED(31083,32,FLEN) +NAN_BOXED(30055,32,FLEN) +NAN_BOXED(47958,16,FLEN) +NAN_BOXED(29941,32,FLEN) +NAN_BOXED(31371,32,FLEN) +NAN_BOXED(47282,16,FLEN) +NAN_BOXED(30640,32,FLEN) +NAN_BOXED(29964,32,FLEN) +NAN_BOXED(48664,16,FLEN) +NAN_BOXED(30642,32,FLEN) +NAN_BOXED(31138,32,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(27467,32,FLEN) +NAN_BOXED(31692,32,FLEN) +NAN_BOXED(42497,16,FLEN) +NAN_BOXED(26074,32,FLEN) +NAN_BOXED(31230,32,FLEN) +NAN_BOXED(48257,16,FLEN) +NAN_BOXED(31425,32,FLEN) +test_dataset_3: +NAN_BOXED(25760,16,FLEN) +NAN_BOXED(53618,16,FLEN) +NAN_BOXED(31308,16,FLEN) +NAN_BOXED(30171,16,FLEN) +NAN_BOXED(48721,16,FLEN) +NAN_BOXED(30880,16,FLEN) +NAN_BOXED(24743,16,FLEN) +NAN_BOXED(50467,16,FLEN) +NAN_BOXED(27130,16,FLEN) +NAN_BOXED(29129,16,FLEN) +NAN_BOXED(50503,16,FLEN) +NAN_BOXED(31651,16,FLEN) +NAN_BOXED(29257,16,FLEN) +NAN_BOXED(50096,16,FLEN) +NAN_BOXED(31243,16,FLEN) +NAN_BOXED(31599,16,FLEN) +NAN_BOXED(48141,16,FLEN) +NAN_BOXED(31624,16,FLEN) +NAN_BOXED(30081,16,FLEN) +NAN_BOXED(48158,16,FLEN) +NAN_BOXED(30124,16,FLEN) +NAN_BOXED(30770,16,FLEN) +NAN_BOXED(48617,16,FLEN) +NAN_BOXED(31283,16,FLEN) +NAN_BOXED(28393,16,FLEN) +NAN_BOXED(50924,16,FLEN) +NAN_BOXED(31227,16,FLEN) +NAN_BOXED(31327,16,FLEN) +NAN_BOXED(48208,16,FLEN) +NAN_BOXED(31455,16,FLEN) +NAN_BOXED(26800,16,FLEN) +NAN_BOXED(52851,16,FLEN) +NAN_BOXED(31632,16,FLEN) +NAN_BOXED(28117,16,FLEN) +NAN_BOXED(50035,16,FLEN) +NAN_BOXED(30067,16,FLEN) +NAN_BOXED(30946,16,FLEN) +NAN_BOXED(48641,16,FLEN) +NAN_BOXED(31575,16,FLEN) +NAN_BOXED(30063,16,FLEN) +NAN_BOXED(49518,16,FLEN) +NAN_BOXED(31587,16,FLEN) +NAN_BOXED(30811,16,FLEN) +NAN_BOXED(47250,16,FLEN) +NAN_BOXED(29951,16,FLEN) +NAN_BOXED(29969,16,FLEN) +NAN_BOXED(47221,16,FLEN) +NAN_BOXED(29101,16,FLEN) +NAN_BOXED(27904,16,FLEN) +NAN_BOXED(49040,16,FLEN) +NAN_BOXED(28867,16,FLEN) +NAN_BOXED(31106,16,FLEN) +NAN_BOXED(48583,16,FLEN) +NAN_BOXED(31736,16,FLEN) +NAN_BOXED(28970,16,FLEN) +NAN_BOXED(46287,16,FLEN) +NAN_BOXED(27190,16,FLEN) +NAN_BOXED(31715,16,FLEN) +NAN_BOXED(47187,16,FLEN) +NAN_BOXED(30788,16,FLEN) +NAN_BOXED(30333,16,FLEN) +NAN_BOXED(47277,16,FLEN) +NAN_BOXED(29591,16,FLEN) +NAN_BOXED(30911,16,FLEN) +NAN_BOXED(48528,16,FLEN) +NAN_BOXED(31387,16,FLEN) +NAN_BOXED(30537,16,FLEN) +NAN_BOXED(47975,16,FLEN) +NAN_BOXED(30398,16,FLEN) +NAN_BOXED(27424,16,FLEN) +NAN_BOXED(52252,16,FLEN) +NAN_BOXED(31571,16,FLEN) +NAN_BOXED(26672,16,FLEN) +NAN_BOXED(52105,16,FLEN) +NAN_BOXED(30692,16,FLEN) +NAN_BOXED(30971,16,FLEN) +NAN_BOXED(48323,16,FLEN) +NAN_BOXED(31214,16,FLEN) +NAN_BOXED(31323,16,FLEN) +NAN_BOXED(48317,16,FLEN) +NAN_BOXED(31625,16,FLEN) +NAN_BOXED(26476,16,FLEN) +NAN_BOXED(52226,16,FLEN) +NAN_BOXED(30578,16,FLEN) +NAN_BOXED(30809,16,FLEN) +NAN_BOXED(48184,16,FLEN) +NAN_BOXED(30870,16,FLEN) +NAN_BOXED(25272,16,FLEN) +NAN_BOXED(52256,16,FLEN) +NAN_BOXED(29422,16,FLEN) +NAN_BOXED(29816,16,FLEN) +NAN_BOXED(49806,16,FLEN) +NAN_BOXED(31571,16,FLEN) +NAN_BOXED(31263,16,FLEN) +NAN_BOXED(45739,16,FLEN) +NAN_BOXED(28954,16,FLEN) +NAN_BOXED(31327,16,FLEN) +NAN_BOXED(45458,16,FLEN) +NAN_BOXED(28784,16,FLEN) +NAN_BOXED(31707,16,FLEN) +NAN_BOXED(47898,16,FLEN) +NAN_BOXED(31481,16,FLEN) +NAN_BOXED(29905,16,FLEN) +NAN_BOXED(49152,16,FLEN) +NAN_BOXED(30930,16,FLEN) +NAN_BOXED(31138,16,FLEN) +NAN_BOXED(44333,16,FLEN) +NAN_BOXED(27467,16,FLEN) +NAN_BOXED(31692,16,FLEN) +NAN_BOXED(42497,16,FLEN) +NAN_BOXED(26074,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x2_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_1: + .fill 26*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_0: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 82*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fmadd_b8-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fmadd_b8-01.S new file mode 100644 index 000000000..b4cc4fa5e --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fmadd_b8-01.S @@ -0,0 +1,17074 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 04:10:09 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fmadd.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fmadd.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fmadd_b8 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fmadd_b8) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x15,test_dataset_0) +RVTEST_SIGBASE(x2,signature_x2_1) + +inst_0: +// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==x8, rs2==x8, rs3==x1, rd==x19,fs1 == 0 and fe1 == 0x0d and fm1 == 0x208 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x17a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x021 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x8; op2:x8; op3:x1; dest:x19; op1val:0x3608; op2val:0x3608; +op3val:0x3421; valaddr_reg:x15; val_offset:0*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x19, x8, x8, x1, dyn, 0, 0, x15, 0*FLEN/8, x24, x2, x11) + +inst_1: +// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==x22, rs2==x7, rs3==x22, rd==x13,fs1 == 0 and fe1 == 0x0d and fm1 == 0x208 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x17a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x021 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x22; op2:x7; op3:x22; dest:x13; op1val:0x3608; op2val:0xb97a; +op3val:0x3608; valaddr_reg:x15; val_offset:3*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x13, x22, x7, x22, dyn, 32, 0, x15, 3*FLEN/8, x24, x2, x11) + +inst_2: +// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==x9, rs2==x20, rs3==x29, rd==x9,fs1 == 0 and fe1 == 0x0d and fm1 == 0x208 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x17a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x021 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x9; op2:x20; op3:x29; dest:x9; op1val:0x3608; op2val:0xb97a; +op3val:0x3421; valaddr_reg:x15; val_offset:6*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x9, x9, x20, x29, dyn, 64, 0, x15, 6*FLEN/8, x24, x2, x11) + +inst_3: +// rs1 == rs2 == rs3 != rd, rs1==x17, rs2==x17, rs3==x17, rd==x18,fs1 == 0 and fe1 == 0x0d and fm1 == 0x208 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x17a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x021 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x17; op2:x17; op3:x17; dest:x18; op1val:0x3608; op2val:0x3608; +op3val:0x3608; valaddr_reg:x15; val_offset:9*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x18, x17, x17, x17, dyn, 96, 0, x15, 9*FLEN/8, x24, x2, x11) + +inst_4: +// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==x7, rs2==x29, rs3==x14, rd==x14,fs1 == 0 and fe1 == 0x0d and fm1 == 0x208 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x17a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x021 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x7; op2:x29; op3:x14; dest:x14; op1val:0x3608; op2val:0xb97a; +op3val:0x3421; valaddr_reg:x15; val_offset:12*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x14, x7, x29, x14, dyn, 128, 0, x15, 12*FLEN/8, x24, x2, x11) + +inst_5: +// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==x12, rs2==x1, rs3==x28, rd==x1,fs1 == 0 and fe1 == 0x0c and fm1 == 0x28d and fs2 == 1 and fe2 == 0x0d and fm2 == 0x07e and fs3 == 0 and fe3 == 0x0a and fm3 == 0x35d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x12; op2:x1; op3:x28; dest:x1; op1val:0x328d; op2val:0xb47e; +op3val:0x2b5d; valaddr_reg:x15; val_offset:15*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x1, x12, x1, x28, dyn, 0, 0, x15, 15*FLEN/8, x24, x2, x11) + +inst_6: +// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==x14, rs2==x28, rs3==x24, rd==x17,fs1 == 0 and fe1 == 0x0c and fm1 == 0x28d and fs2 == 1 and fe2 == 0x0d and fm2 == 0x07e and fs3 == 0 and fe3 == 0x0a and fm3 == 0x35d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x14; op2:x28; op3:x24; dest:x17; op1val:0x328d; op2val:0xb47e; +op3val:0x2b5d; valaddr_reg:x15; val_offset:18*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x17, x14, x28, x24, dyn, 32, 0, x15, 18*FLEN/8, x24, x2, x11) + +inst_7: +// rd == rs2 == rs3 != rs1, rs1==x6, rs2==x10, rs3==x10, rd==x10,fs1 == 0 and fe1 == 0x0c and fm1 == 0x28d and fs2 == 1 and fe2 == 0x0d and fm2 == 0x07e and fs3 == 0 and fe3 == 0x0a and fm3 == 0x35d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x6; op2:x10; op3:x10; dest:x10; op1val:0x328d; op2val:0xb47e; +op3val:0xb47e; valaddr_reg:x15; val_offset:21*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x10, x6, x10, x10, dyn, 64, 0, x15, 21*FLEN/8, x24, x2, x11) + +inst_8: +// rs1 == rd == rs3 != rs2, rs1==x31, rs2==x5, rs3==x31, rd==x31,fs1 == 0 and fe1 == 0x0c and fm1 == 0x28d and fs2 == 1 and fe2 == 0x0d and fm2 == 0x07e and fs3 == 0 and fe3 == 0x0a and fm3 == 0x35d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x31; op2:x5; op3:x31; dest:x31; op1val:0x328d; op2val:0xb47e; +op3val:0x328d; valaddr_reg:x15; val_offset:24*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x31, x5, x31, dyn, 96, 0, x15, 24*FLEN/8, x24, x2, x11) + +inst_9: +// rs1 == rs2 == rs3 == rd, rs1==x23, rs2==x23, rs3==x23, rd==x23,fs1 == 0 and fe1 == 0x0c and fm1 == 0x28d and fs2 == 1 and fe2 == 0x0d and fm2 == 0x07e and fs3 == 0 and fe3 == 0x0a and fm3 == 0x35d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x23; op2:x23; op3:x23; dest:x23; op1val:0x328d; op2val:0x328d; +op3val:0x328d; valaddr_reg:x15; val_offset:27*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x23, x23, x23, x23, dyn, 128, 0, x15, 27*FLEN/8, x24, x2, x11) + +inst_10: +// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==x0, rs2==x21, rs3==x21, rd==x5,fs1 == 0 and fe1 == 0x0d and fm1 == 0x029 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0c7 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x0; op2:x21; op3:x21; dest:x5; op1val:0x0; op2val:0xb4c7; +op3val:0xb4c7; valaddr_reg:x15; val_offset:30*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x5, x0, x21, x21, dyn, 0, 0, x15, 30*FLEN/8, x24, x2, x11) + +inst_11: +// rs1 == rs2 == rd != rs3, rs1==x30, rs2==x30, rs3==x7, rd==x30,fs1 == 0 and fe1 == 0x0d and fm1 == 0x029 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0c7 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0f8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x30; op3:x7; dest:x30; op1val:0x3429; op2val:0x3429; +op3val:0x2cf8; valaddr_reg:x15; val_offset:33*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x30, x30, x30, x7, dyn, 32, 0, x15, 33*FLEN/8, x24, x2, x11) + +inst_12: +// rs1==x4, rs2==x16, rs3==x11, rd==x3,fs1 == 0 and fe1 == 0x0d and fm1 == 0x029 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0c7 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0f8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x4; op2:x16; op3:x11; dest:x3; op1val:0x3429; op2val:0xb4c7; +op3val:0x2cf8; valaddr_reg:x15; val_offset:36*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x3, x4, x16, x11, dyn, 64, 0, x15, 36*FLEN/8, x24, x2, x11) +RVTEST_VALBASEUPD(x8,test_dataset_1) + +inst_13: +// rs1==x1, rs2==x24, rs3==x26, rd==x25,fs1 == 0 and fe1 == 0x0d and fm1 == 0x029 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0c7 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0f8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x1; op2:x24; op3:x26; dest:x25; op1val:0x3429; op2val:0xb4c7; +op3val:0x2cf8; valaddr_reg:x8; val_offset:0*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x25, x1, x24, x26, dyn, 96, 0, x8, 0*FLEN/8, x13, x2, x7) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_14: +// rs1==x28, rs2==x14, rs3==x15, rd==x2,fs1 == 0 and fe1 == 0x0d and fm1 == 0x029 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0c7 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0f8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x28; op2:x14; op3:x15; dest:x2; op1val:0x3429; op2val:0xb4c7; +op3val:0x2cf8; valaddr_reg:x8; val_offset:3*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x2, x28, x14, x15, dyn, 128, 0, x8, 3*FLEN/8, x13, x1, x7) + +inst_15: +// rs1==x16, rs2==x15, rs3==x27, rd==x28,fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x067 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x046 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x16; op2:x15; op3:x27; dest:x28; op1val:0x3bc4; op2val:0xb867; +op3val:0x3846; valaddr_reg:x8; val_offset:6*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x28, x16, x15, x27, dyn, 0, 0, x8, 6*FLEN/8, x13, x1, x7) + +inst_16: +// rs1==x29, rs2==x31, rs3==x3, rd==x21,fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x067 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x046 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x29; op2:x31; op3:x3; dest:x21; op1val:0x3bc4; op2val:0xb867; +op3val:0x3846; valaddr_reg:x8; val_offset:9*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x21, x29, x31, x3, dyn, 32, 0, x8, 9*FLEN/8, x13, x1, x7) + +inst_17: +// rs1==x11, rs2==x9, rs3==x20, rd==x4,fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x067 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x046 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x11; op2:x9; op3:x20; dest:x4; op1val:0x3bc4; op2val:0xb867; +op3val:0x3846; valaddr_reg:x8; val_offset:12*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x4, x11, x9, x20, dyn, 64, 0, x8, 12*FLEN/8, x13, x1, x7) + +inst_18: +// rs1==x20, rs2==x11, rs3==x4, rd==x0,fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x067 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x046 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x20; op2:x11; op3:x4; dest:x0; op1val:0x3bc4; op2val:0xb867; +op3val:0x3846; valaddr_reg:x8; val_offset:15*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x0, x20, x11, x4, dyn, 96, 0, x8, 15*FLEN/8, x13, x1, x7) + +inst_19: +// rs1==x3, rs2==x18, rs3==x8, rd==x29,fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x067 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x046 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x3; op2:x18; op3:x8; dest:x29; op1val:0x3bc4; op2val:0xb867; +op3val:0x3846; valaddr_reg:x8; val_offset:18*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x29, x3, x18, x8, dyn, 128, 0, x8, 18*FLEN/8, x13, x1, x7) + +inst_20: +// rs1==x15, rs2==x12, rs3==x18, rd==x24,fs1 == 0 and fe1 == 0x0a and fm1 == 0x340 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x232 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x19d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x15; op2:x12; op3:x18; dest:x24; op1val:0x2b40; op2val:0xc632; +op3val:0x359d; valaddr_reg:x8; val_offset:21*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x24, x15, x12, x18, dyn, 0, 0, x8, 21*FLEN/8, x13, x1, x7) + +inst_21: +// rs1==x26, rs2==x4, rs3==x30, rd==x12,fs1 == 0 and fe1 == 0x0a and fm1 == 0x340 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x232 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x19d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x26; op2:x4; op3:x30; dest:x12; op1val:0x2b40; op2val:0xc632; +op3val:0x359d; valaddr_reg:x8; val_offset:24*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x12, x26, x4, x30, dyn, 32, 0, x8, 24*FLEN/8, x13, x1, x7) + +inst_22: +// rs1==x5, rs2==x6, rs3==x9, rd==x16,fs1 == 0 and fe1 == 0x0a and fm1 == 0x340 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x232 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x19d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x5; op2:x6; op3:x9; dest:x16; op1val:0x2b40; op2val:0xc632; +op3val:0x359d; valaddr_reg:x8; val_offset:27*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x16, x5, x6, x9, dyn, 64, 0, x8, 27*FLEN/8, x13, x1, x7) + +inst_23: +// rs1==x10, rs2==x3, rs3==x25, rd==x27,fs1 == 0 and fe1 == 0x0a and fm1 == 0x340 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x232 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x19d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x10; op2:x3; op3:x25; dest:x27; op1val:0x2b40; op2val:0xc632; +op3val:0x359d; valaddr_reg:x8; val_offset:30*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x27, x10, x3, x25, dyn, 96, 0, x8, 30*FLEN/8, x13, x1, x7) +RVTEST_VALBASEUPD(x5,test_dataset_2) + +inst_24: +// rs1==x18, rs2==x26, rs3==x2, rd==x22,fs1 == 0 and fe1 == 0x0a and fm1 == 0x340 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x232 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x19d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x18; op2:x26; op3:x2; dest:x22; op1val:0x2b40; op2val:0xc632; +op3val:0x359d; valaddr_reg:x5; val_offset:0*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x22, x18, x26, x2, dyn, 128, 0, x5, 0*FLEN/8, x9, x1, x7) + +inst_25: +// rs1==x27, rs2==x25, rs3==x13, rd==x26,fs1 == 0 and fe1 == 0x0b and fm1 == 0x257 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x079 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x318 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x27; op2:x25; op3:x13; dest:x26; op1val:0x2e57; op2val:0xc879; +op3val:0x3b18; valaddr_reg:x5; val_offset:3*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x26, x27, x25, x13, dyn, 0, 0, x5, 3*FLEN/8, x9, x1, x7) + +inst_26: +// rs1==x24, rs2==x13, rs3==x6, rd==x11,fs1 == 0 and fe1 == 0x0b and fm1 == 0x257 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x079 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x318 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x24; op2:x13; op3:x6; dest:x11; op1val:0x2e57; op2val:0xc879; +op3val:0x3b18; valaddr_reg:x5; val_offset:6*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x11, x24, x13, x6, dyn, 32, 0, x5, 6*FLEN/8, x9, x1, x7) + +inst_27: +// rs1==x2, rs2==x22, rs3==x16, rd==x15,fs1 == 0 and fe1 == 0x0b and fm1 == 0x257 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x079 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x318 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x2; op2:x22; op3:x16; dest:x15; op1val:0x2e57; op2val:0xc879; +op3val:0x3b18; valaddr_reg:x5; val_offset:9*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x15, x2, x22, x16, dyn, 64, 0, x5, 9*FLEN/8, x9, x1, x4) + +inst_28: +// rs1==x13, rs2==x19, rs3==x5, rd==x20,fs1 == 0 and fe1 == 0x0b and fm1 == 0x257 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x079 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x318 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x13; op2:x19; op3:x5; dest:x20; op1val:0x2e57; op2val:0xc879; +op3val:0x3b18; valaddr_reg:x5; val_offset:12*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x20, x13, x19, x5, dyn, 96, 0, x5, 12*FLEN/8, x9, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_29: +// rs1==x25, rs2==x27, rs3==x0, rd==x8,fs1 == 0 and fe1 == 0x0b and fm1 == 0x257 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x079 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x318 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x25; op2:x27; op3:x0; dest:x8; op1val:0x2e57; op2val:0xc879; +op3val:0x0; valaddr_reg:x5; val_offset:15*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x8, x25, x27, x0, dyn, 128, 0, x5, 15*FLEN/8, x9, x1, x4) + +inst_30: +// rs1==x21, rs2==x2, rs3==x12, rd==x6,fs1 == 0 and fe1 == 0x0e and fm1 == 0x03f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1ad and fs3 == 0 and fe3 == 0x0e and fm3 == 0x207 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x21; op2:x2; op3:x12; dest:x6; op1val:0x383f; op2val:0xbdad; +op3val:0x3a07; valaddr_reg:x5; val_offset:18*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x6, x21, x2, x12, dyn, 0, 0, x5, 18*FLEN/8, x9, x1, x4) + +inst_31: +// rs1==x19,fs1 == 0 and fe1 == 0x0e and fm1 == 0x03f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1ad and fs3 == 0 and fe3 == 0x0e and fm3 == 0x207 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x19; op2:x25; op3:x5; dest:x27; op1val:0x383f; op2val:0xbdad; +op3val:0x3a07; valaddr_reg:x5; val_offset:21*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x27, x19, x25, x5, dyn, 32, 0, x5, 21*FLEN/8, x9, x1, x4) + +inst_32: +// rs2==x0,fs1 == 0 and fe1 == 0x0e and fm1 == 0x03f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1ad and fs3 == 0 and fe3 == 0x0e and fm3 == 0x207 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x26; op2:x0; op3:x17; dest:x13; op1val:0x383f; op2val:0x0; +op3val:0x3a07; valaddr_reg:x5; val_offset:24*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x13, x26, x0, x17, dyn, 64, 0, x5, 24*FLEN/8, x9, x1, x4) + +inst_33: +// rs3==x19,fs1 == 0 and fe1 == 0x0e and fm1 == 0x03f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1ad and fs3 == 0 and fe3 == 0x0e and fm3 == 0x207 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x7; op2:x25; op3:x19; dest:x23; op1val:0x383f; op2val:0xbdad; +op3val:0x3a07; valaddr_reg:x5; val_offset:27*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x23, x7, x25, x19, dyn, 96, 0, x5, 27*FLEN/8, x9, x1, x4) + +inst_34: +// rd==x7,fs1 == 0 and fe1 == 0x0e and fm1 == 0x03f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1ad and fs3 == 0 and fe3 == 0x0e and fm3 == 0x207 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x3; op3:x15; dest:x7; op1val:0x383f; op2val:0xbdad; +op3val:0x3a07; valaddr_reg:x5; val_offset:30*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x7, x30, x3, x15, dyn, 128, 0, x5, 30*FLEN/8, x9, x1, x4) + +inst_35: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x34c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x378 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2d1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x374c; op2val:0xbb78; +op3val:0x36d1; valaddr_reg:x5; val_offset:33*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 33*FLEN/8, x9, x1, x4) + +inst_36: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x34c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x378 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2d1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x374c; op2val:0xbb78; +op3val:0x36d1; valaddr_reg:x5; val_offset:36*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 36*FLEN/8, x9, x1, x4) + +inst_37: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x34c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x378 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2d1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x374c; op2val:0xbb78; +op3val:0x36d1; valaddr_reg:x5; val_offset:39*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 39*FLEN/8, x9, x1, x4) + +inst_38: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x34c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x378 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2d1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x374c; op2val:0xbb78; +op3val:0x36d1; valaddr_reg:x5; val_offset:42*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 42*FLEN/8, x9, x1, x4) + +inst_39: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x34c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x378 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2d1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x374c; op2val:0xbb78; +op3val:0x36d1; valaddr_reg:x5; val_offset:45*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 45*FLEN/8, x9, x1, x4) + +inst_40: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x259 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x244 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3be5; op2val:0xba59; +op3val:0x3a44; valaddr_reg:x5; val_offset:48*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 48*FLEN/8, x9, x1, x4) + +inst_41: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x259 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x244 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3be5; op2val:0xba59; +op3val:0x3a44; valaddr_reg:x5; val_offset:51*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 51*FLEN/8, x9, x1, x4) + +inst_42: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x259 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x244 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3be5; op2val:0xba59; +op3val:0x3a44; valaddr_reg:x5; val_offset:54*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 54*FLEN/8, x9, x1, x4) + +inst_43: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x259 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x244 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3be5; op2val:0xba59; +op3val:0x3a44; valaddr_reg:x5; val_offset:57*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 57*FLEN/8, x9, x1, x4) + +inst_44: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x259 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x244 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3be5; op2val:0xba59; +op3val:0x3a44; valaddr_reg:x5; val_offset:60*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 60*FLEN/8, x9, x1, x4) + +inst_45: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1c3 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x36e and fs3 == 0 and fe3 == 0x0b and fm3 == 0x15a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39c3; op2val:0xaf6e; +op3val:0x2d5a; valaddr_reg:x5; val_offset:63*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 63*FLEN/8, x9, x1, x4) + +inst_46: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1c3 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x36e and fs3 == 0 and fe3 == 0x0b and fm3 == 0x15a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39c3; op2val:0xaf6e; +op3val:0x2d5a; valaddr_reg:x5; val_offset:66*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 66*FLEN/8, x9, x1, x4) + +inst_47: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1c3 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x36e and fs3 == 0 and fe3 == 0x0b and fm3 == 0x15a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39c3; op2val:0xaf6e; +op3val:0x2d5a; valaddr_reg:x5; val_offset:69*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 69*FLEN/8, x9, x1, x4) + +inst_48: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1c3 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x36e and fs3 == 0 and fe3 == 0x0b and fm3 == 0x15a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39c3; op2val:0xaf6e; +op3val:0x2d5a; valaddr_reg:x5; val_offset:72*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 72*FLEN/8, x9, x1, x4) + +inst_49: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1c3 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x36e and fs3 == 0 and fe3 == 0x0b and fm3 == 0x15a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39c3; op2val:0xaf6e; +op3val:0x2d5a; valaddr_reg:x5; val_offset:75*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 75*FLEN/8, x9, x1, x4) + +inst_50: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x37f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x32c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x337f; op2val:0xc32c; +op3val:0x3ab9; valaddr_reg:x5; val_offset:78*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 78*FLEN/8, x9, x1, x4) + +inst_51: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x37f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x32c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x337f; op2val:0xc32c; +op3val:0x3ab9; valaddr_reg:x5; val_offset:81*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 81*FLEN/8, x9, x1, x4) + +inst_52: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x37f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x32c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x337f; op2val:0xc32c; +op3val:0x3ab9; valaddr_reg:x5; val_offset:84*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 84*FLEN/8, x9, x1, x4) + +inst_53: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x37f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x32c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x337f; op2val:0xc32c; +op3val:0x3ab9; valaddr_reg:x5; val_offset:87*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 87*FLEN/8, x9, x1, x4) + +inst_54: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x37f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x32c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x337f; op2val:0xc32c; +op3val:0x3ab9; valaddr_reg:x5; val_offset:90*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 90*FLEN/8, x9, x1, x4) + +inst_55: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x27d and fs2 == 1 and fe2 == 0x11 and fm2 == 0x03e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2e3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x327d; op2val:0xc43e; +op3val:0x3ae3; valaddr_reg:x5; val_offset:93*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 93*FLEN/8, x9, x1, x4) + +inst_56: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x27d and fs2 == 1 and fe2 == 0x11 and fm2 == 0x03e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2e3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x327d; op2val:0xc43e; +op3val:0x3ae3; valaddr_reg:x5; val_offset:96*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 96*FLEN/8, x9, x1, x4) + +inst_57: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x27d and fs2 == 1 and fe2 == 0x11 and fm2 == 0x03e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2e3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x327d; op2val:0xc43e; +op3val:0x3ae3; valaddr_reg:x5; val_offset:99*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 99*FLEN/8, x9, x1, x4) + +inst_58: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x27d and fs2 == 1 and fe2 == 0x11 and fm2 == 0x03e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2e3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x327d; op2val:0xc43e; +op3val:0x3ae3; valaddr_reg:x5; val_offset:102*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 102*FLEN/8, x9, x1, x4) + +inst_59: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x27d and fs2 == 1 and fe2 == 0x11 and fm2 == 0x03e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2e3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x327d; op2val:0xc43e; +op3val:0x3ae3; valaddr_reg:x5; val_offset:105*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 105*FLEN/8, x9, x1, x4) + +inst_60: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x21e and fs2 == 1 and fe2 == 0x10 and fm2 == 0x090 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x361e; op2val:0xc090; +op3val:0x3afc; valaddr_reg:x5; val_offset:108*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 108*FLEN/8, x9, x1, x4) + +inst_61: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x21e and fs2 == 1 and fe2 == 0x10 and fm2 == 0x090 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2fc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x361e; op2val:0xc090; +op3val:0x3afc; valaddr_reg:x5; val_offset:111*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 111*FLEN/8, x9, x1, x4) + +inst_62: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x21e and fs2 == 1 and fe2 == 0x10 and fm2 == 0x090 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2fc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x361e; op2val:0xc090; +op3val:0x3afc; valaddr_reg:x5; val_offset:114*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 114*FLEN/8, x9, x1, x4) + +inst_63: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x21e and fs2 == 1 and fe2 == 0x10 and fm2 == 0x090 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2fc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x361e; op2val:0xc090; +op3val:0x3afc; valaddr_reg:x5; val_offset:117*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 117*FLEN/8, x9, x1, x4) + +inst_64: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x21e and fs2 == 1 and fe2 == 0x10 and fm2 == 0x090 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2fc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x361e; op2val:0xc090; +op3val:0x3afc; valaddr_reg:x5; val_offset:120*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 120*FLEN/8, x9, x1, x4) + +inst_65: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x0c and fm2 == 0x01f and fs3 == 0 and fe3 == 0x0c and fm3 == 0x01d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bfc; op2val:0xb01f; +op3val:0x301d; valaddr_reg:x5; val_offset:123*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 123*FLEN/8, x9, x1, x4) + +inst_66: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x0c and fm2 == 0x01f and fs3 == 0 and fe3 == 0x0c and fm3 == 0x01d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bfc; op2val:0xb01f; +op3val:0x301d; valaddr_reg:x5; val_offset:126*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 126*FLEN/8, x9, x1, x4) + +inst_67: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x0c and fm2 == 0x01f and fs3 == 0 and fe3 == 0x0c and fm3 == 0x01d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bfc; op2val:0xb01f; +op3val:0x301d; valaddr_reg:x5; val_offset:129*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 129*FLEN/8, x9, x1, x4) + +inst_68: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x0c and fm2 == 0x01f and fs3 == 0 and fe3 == 0x0c and fm3 == 0x01d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bfc; op2val:0xb01f; +op3val:0x301d; valaddr_reg:x5; val_offset:132*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 132*FLEN/8, x9, x1, x4) + +inst_69: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x0c and fm2 == 0x01f and fs3 == 0 and fe3 == 0x0c and fm3 == 0x01d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bfc; op2val:0xb01f; +op3val:0x301d; valaddr_reg:x5; val_offset:135*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 135*FLEN/8, x9, x1, x4) + +inst_70: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x253 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3f0 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x246 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a53; op2val:0xbbf0; +op3val:0x3a46; valaddr_reg:x5; val_offset:138*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 138*FLEN/8, x9, x1, x4) + +inst_71: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x253 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3f0 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x246 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a53; op2val:0xbbf0; +op3val:0x3a46; valaddr_reg:x5; val_offset:141*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 141*FLEN/8, x9, x1, x4) + +inst_72: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x253 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3f0 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x246 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a53; op2val:0xbbf0; +op3val:0x3a46; valaddr_reg:x5; val_offset:144*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 144*FLEN/8, x9, x1, x4) + +inst_73: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x253 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3f0 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x246 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a53; op2val:0xbbf0; +op3val:0x3a46; valaddr_reg:x5; val_offset:147*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 147*FLEN/8, x9, x1, x4) + +inst_74: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x253 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3f0 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x246 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a53; op2val:0xbbf0; +op3val:0x3a46; valaddr_reg:x5; val_offset:150*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 150*FLEN/8, x9, x1, x4) + +inst_75: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x080 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x342 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x015 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2480; op2val:0xc742; +op3val:0x3015; valaddr_reg:x5; val_offset:153*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 153*FLEN/8, x9, x1, x4) + +inst_76: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x080 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x342 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x015 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2480; op2val:0xc742; +op3val:0x3015; valaddr_reg:x5; val_offset:156*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 156*FLEN/8, x9, x1, x4) + +inst_77: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x080 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x342 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x015 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2480; op2val:0xc742; +op3val:0x3015; valaddr_reg:x5; val_offset:159*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 159*FLEN/8, x9, x1, x4) + +inst_78: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x080 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x342 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x015 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2480; op2val:0xc742; +op3val:0x3015; valaddr_reg:x5; val_offset:162*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 162*FLEN/8, x9, x1, x4) + +inst_79: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x080 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x342 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x015 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2480; op2val:0xc742; +op3val:0x3015; valaddr_reg:x5; val_offset:165*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 165*FLEN/8, x9, x1, x4) + +inst_80: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1af and fs2 == 1 and fe2 == 0x0a and fm2 == 0x2f0 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x0ee and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39af; op2val:0xaaf0; +op3val:0x28ee; valaddr_reg:x5; val_offset:168*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 168*FLEN/8, x9, x1, x4) + +inst_81: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1af and fs2 == 1 and fe2 == 0x0a and fm2 == 0x2f0 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x0ee and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39af; op2val:0xaaf0; +op3val:0x28ee; valaddr_reg:x5; val_offset:171*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 171*FLEN/8, x9, x1, x4) + +inst_82: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1af and fs2 == 1 and fe2 == 0x0a and fm2 == 0x2f0 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x0ee and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39af; op2val:0xaaf0; +op3val:0x28ee; valaddr_reg:x5; val_offset:174*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 174*FLEN/8, x9, x1, x4) + +inst_83: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1af and fs2 == 1 and fe2 == 0x0a and fm2 == 0x2f0 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x0ee and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39af; op2val:0xaaf0; +op3val:0x28ee; valaddr_reg:x5; val_offset:177*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 177*FLEN/8, x9, x1, x4) + +inst_84: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1af and fs2 == 1 and fe2 == 0x0a and fm2 == 0x2f0 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x0ee and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39af; op2val:0xaaf0; +op3val:0x28ee; valaddr_reg:x5; val_offset:180*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 180*FLEN/8, x9, x1, x4) + +inst_85: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x35f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x197 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x127 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x375f; op2val:0xb997; +op3val:0x3527; valaddr_reg:x5; val_offset:183*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 183*FLEN/8, x9, x1, x4) + +inst_86: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x35f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x197 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x127 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x375f; op2val:0xb997; +op3val:0x3527; valaddr_reg:x5; val_offset:186*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 186*FLEN/8, x9, x1, x4) + +inst_87: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x35f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x197 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x127 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x375f; op2val:0xb997; +op3val:0x3527; valaddr_reg:x5; val_offset:189*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 189*FLEN/8, x9, x1, x4) + +inst_88: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x35f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x197 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x127 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x375f; op2val:0xb997; +op3val:0x3527; valaddr_reg:x5; val_offset:192*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 192*FLEN/8, x9, x1, x4) + +inst_89: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x35f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x197 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x127 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x375f; op2val:0xb997; +op3val:0x3527; valaddr_reg:x5; val_offset:195*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 195*FLEN/8, x9, x1, x4) + +inst_90: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x25c and fs2 == 1 and fe2 == 0x0b and fm2 == 0x0c0 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x38e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a5c; op2val:0xacc0; +op3val:0x2b8e; valaddr_reg:x5; val_offset:198*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 198*FLEN/8, x9, x1, x4) + +inst_91: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x25c and fs2 == 1 and fe2 == 0x0b and fm2 == 0x0c0 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x38e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a5c; op2val:0xacc0; +op3val:0x2b8e; valaddr_reg:x5; val_offset:201*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 201*FLEN/8, x9, x1, x4) + +inst_92: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x25c and fs2 == 1 and fe2 == 0x0b and fm2 == 0x0c0 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x38e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a5c; op2val:0xacc0; +op3val:0x2b8e; valaddr_reg:x5; val_offset:204*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 204*FLEN/8, x9, x1, x4) + +inst_93: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x25c and fs2 == 1 and fe2 == 0x0b and fm2 == 0x0c0 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x38e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a5c; op2val:0xacc0; +op3val:0x2b8e; valaddr_reg:x5; val_offset:207*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 207*FLEN/8, x9, x1, x4) + +inst_94: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x25c and fs2 == 1 and fe2 == 0x0b and fm2 == 0x0c0 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x38e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a5c; op2val:0xacc0; +op3val:0x2b8e; valaddr_reg:x5; val_offset:210*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 210*FLEN/8, x9, x1, x4) + +inst_95: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0f3 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x2ea and fs3 == 0 and fe3 == 0x0a and fm3 == 0x047 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34f3; op2val:0xaeea; +op3val:0x2847; valaddr_reg:x5; val_offset:213*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 213*FLEN/8, x9, x1, x4) + +inst_96: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0f3 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x2ea and fs3 == 0 and fe3 == 0x0a and fm3 == 0x047 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34f3; op2val:0xaeea; +op3val:0x2847; valaddr_reg:x5; val_offset:216*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 216*FLEN/8, x9, x1, x4) + +inst_97: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0f3 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x2ea and fs3 == 0 and fe3 == 0x0a and fm3 == 0x047 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34f3; op2val:0xaeea; +op3val:0x2847; valaddr_reg:x5; val_offset:219*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 219*FLEN/8, x9, x1, x4) + +inst_98: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0f3 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x2ea and fs3 == 0 and fe3 == 0x0a and fm3 == 0x047 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34f3; op2val:0xaeea; +op3val:0x2847; valaddr_reg:x5; val_offset:222*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 222*FLEN/8, x9, x1, x4) + +inst_99: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0f3 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x2ea and fs3 == 0 and fe3 == 0x0a and fm3 == 0x047 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34f3; op2val:0xaeea; +op3val:0x2847; valaddr_reg:x5; val_offset:225*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 225*FLEN/8, x9, x1, x4) + +inst_100: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2cc and fs2 == 1 and fe2 == 0x11 and fm2 == 0x299 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x19c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ecc; op2val:0xc699; +op3val:0x399c; valaddr_reg:x5; val_offset:228*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 228*FLEN/8, x9, x1, x4) + +inst_101: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2cc and fs2 == 1 and fe2 == 0x11 and fm2 == 0x299 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x19c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ecc; op2val:0xc699; +op3val:0x399c; valaddr_reg:x5; val_offset:231*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 231*FLEN/8, x9, x1, x4) + +inst_102: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2cc and fs2 == 1 and fe2 == 0x11 and fm2 == 0x299 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x19c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ecc; op2val:0xc699; +op3val:0x399c; valaddr_reg:x5; val_offset:234*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 234*FLEN/8, x9, x1, x4) + +inst_103: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2cc and fs2 == 1 and fe2 == 0x11 and fm2 == 0x299 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x19c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ecc; op2val:0xc699; +op3val:0x399c; valaddr_reg:x5; val_offset:237*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 237*FLEN/8, x9, x1, x4) + +inst_104: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2cc and fs2 == 1 and fe2 == 0x11 and fm2 == 0x299 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x19c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ecc; op2val:0xc699; +op3val:0x399c; valaddr_reg:x5; val_offset:240*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 240*FLEN/8, x9, x1, x4) + +inst_105: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x138 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ac and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x391c; op2val:0xbd38; +op3val:0x3aac; valaddr_reg:x5; val_offset:243*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 243*FLEN/8, x9, x1, x4) + +inst_106: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x138 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ac and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x391c; op2val:0xbd38; +op3val:0x3aac; valaddr_reg:x5; val_offset:246*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 246*FLEN/8, x9, x1, x4) + +inst_107: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x138 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ac and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x391c; op2val:0xbd38; +op3val:0x3aac; valaddr_reg:x5; val_offset:249*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 249*FLEN/8, x9, x1, x4) + +inst_108: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x138 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ac and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x391c; op2val:0xbd38; +op3val:0x3aac; valaddr_reg:x5; val_offset:252*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 252*FLEN/8, x9, x1, x4) + +inst_109: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x138 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ac and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x391c; op2val:0xbd38; +op3val:0x3aac; valaddr_reg:x5; val_offset:255*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 255*FLEN/8, x9, x1, x4) + +inst_110: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d5 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x060 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x37a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ad5; op2val:0xbc60; +op3val:0x3b7a; valaddr_reg:x5; val_offset:258*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 258*FLEN/8, x9, x1, x4) + +inst_111: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d5 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x060 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x37a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ad5; op2val:0xbc60; +op3val:0x3b7a; valaddr_reg:x5; val_offset:261*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 261*FLEN/8, x9, x1, x4) + +inst_112: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d5 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x060 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x37a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ad5; op2val:0xbc60; +op3val:0x3b7a; valaddr_reg:x5; val_offset:264*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 264*FLEN/8, x9, x1, x4) + +inst_113: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d5 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x060 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x37a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ad5; op2val:0xbc60; +op3val:0x3b7a; valaddr_reg:x5; val_offset:267*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 267*FLEN/8, x9, x1, x4) + +inst_114: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d5 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x060 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x37a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ad5; op2val:0xbc60; +op3val:0x3b7a; valaddr_reg:x5; val_offset:270*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 270*FLEN/8, x9, x1, x4) + +inst_115: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x196 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x08b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x259 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3996; op2val:0xb88b; +op3val:0x3659; valaddr_reg:x5; val_offset:273*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 273*FLEN/8, x9, x1, x4) + +inst_116: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x196 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x08b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x259 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3996; op2val:0xb88b; +op3val:0x3659; valaddr_reg:x5; val_offset:276*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 276*FLEN/8, x9, x1, x4) + +inst_117: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x196 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x08b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x259 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3996; op2val:0xb88b; +op3val:0x3659; valaddr_reg:x5; val_offset:279*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 279*FLEN/8, x9, x1, x4) + +inst_118: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x196 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x08b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x259 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3996; op2val:0xb88b; +op3val:0x3659; valaddr_reg:x5; val_offset:282*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 282*FLEN/8, x9, x1, x4) + +inst_119: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x196 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x08b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x259 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3996; op2val:0xb88b; +op3val:0x3659; valaddr_reg:x5; val_offset:285*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 285*FLEN/8, x9, x1, x4) + +inst_120: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f9 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x12b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x127 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bf9; op2val:0xb52b; +op3val:0x3527; valaddr_reg:x5; val_offset:288*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 288*FLEN/8, x9, x1, x4) + +inst_121: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f9 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x12b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x127 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bf9; op2val:0xb52b; +op3val:0x3527; valaddr_reg:x5; val_offset:291*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 291*FLEN/8, x9, x1, x4) + +inst_122: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f9 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x12b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x127 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bf9; op2val:0xb52b; +op3val:0x3527; valaddr_reg:x5; val_offset:294*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 294*FLEN/8, x9, x1, x4) + +inst_123: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f9 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x12b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x127 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bf9; op2val:0xb52b; +op3val:0x3527; valaddr_reg:x5; val_offset:297*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 297*FLEN/8, x9, x1, x4) + +inst_124: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f9 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x12b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x127 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bf9; op2val:0xb52b; +op3val:0x3527; valaddr_reg:x5; val_offset:300*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 300*FLEN/8, x9, x1, x4) + +inst_125: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x14b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x02b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x185 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x394b; op2val:0xbc2b; +op3val:0x3985; valaddr_reg:x5; val_offset:303*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 303*FLEN/8, x9, x1, x4) + +inst_126: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x14b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x02b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x185 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x394b; op2val:0xbc2b; +op3val:0x3985; valaddr_reg:x5; val_offset:306*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 306*FLEN/8, x9, x1, x4) + +inst_127: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x14b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x02b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x185 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x394b; op2val:0xbc2b; +op3val:0x3985; valaddr_reg:x5; val_offset:309*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 309*FLEN/8, x9, x1, x4) + +inst_128: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x14b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x02b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x185 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x394b; op2val:0xbc2b; +op3val:0x3985; valaddr_reg:x5; val_offset:312*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 312*FLEN/8, x9, x1, x4) + +inst_129: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x14b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x02b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x185 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x394b; op2val:0xbc2b; +op3val:0x3985; valaddr_reg:x5; val_offset:315*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 315*FLEN/8, x9, x1, x4) + +inst_130: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1ce and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1b8 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x027 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31ce; op2val:0xc1b8; +op3val:0x3827; valaddr_reg:x5; val_offset:318*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 318*FLEN/8, x9, x1, x4) + +inst_131: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1ce and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1b8 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x027 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31ce; op2val:0xc1b8; +op3val:0x3827; valaddr_reg:x5; val_offset:321*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 321*FLEN/8, x9, x1, x4) + +inst_132: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1ce and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1b8 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x027 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31ce; op2val:0xc1b8; +op3val:0x3827; valaddr_reg:x5; val_offset:324*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 324*FLEN/8, x9, x1, x4) + +inst_133: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1ce and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1b8 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x027 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31ce; op2val:0xc1b8; +op3val:0x3827; valaddr_reg:x5; val_offset:327*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 327*FLEN/8, x9, x1, x4) + +inst_134: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1ce and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1b8 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x027 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31ce; op2val:0xc1b8; +op3val:0x3827; valaddr_reg:x5; val_offset:330*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 330*FLEN/8, x9, x1, x4) + +inst_135: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x179 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x210 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x026 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3979; op2val:0xba10; +op3val:0x3826; valaddr_reg:x5; val_offset:333*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 333*FLEN/8, x9, x1, x4) + +inst_136: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x179 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x210 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x026 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3979; op2val:0xba10; +op3val:0x3826; valaddr_reg:x5; val_offset:336*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 336*FLEN/8, x9, x1, x4) + +inst_137: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x179 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x210 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x026 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3979; op2val:0xba10; +op3val:0x3826; valaddr_reg:x5; val_offset:339*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 339*FLEN/8, x9, x1, x4) + +inst_138: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x179 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x210 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x026 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3979; op2val:0xba10; +op3val:0x3826; valaddr_reg:x5; val_offset:342*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 342*FLEN/8, x9, x1, x4) + +inst_139: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x179 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x210 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x026 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3979; op2val:0xba10; +op3val:0x3826; valaddr_reg:x5; val_offset:345*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 345*FLEN/8, x9, x1, x4) + +inst_140: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0b9 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x262 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x38b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34b9; op2val:0xc262; +op3val:0x3b8b; valaddr_reg:x5; val_offset:348*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 348*FLEN/8, x9, x1, x4) + +inst_141: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0b9 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x262 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x38b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34b9; op2val:0xc262; +op3val:0x3b8b; valaddr_reg:x5; val_offset:351*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 351*FLEN/8, x9, x1, x4) + +inst_142: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0b9 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x262 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x38b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34b9; op2val:0xc262; +op3val:0x3b8b; valaddr_reg:x5; val_offset:354*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 354*FLEN/8, x9, x1, x4) + +inst_143: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0b9 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x262 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x38b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34b9; op2val:0xc262; +op3val:0x3b8b; valaddr_reg:x5; val_offset:357*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 357*FLEN/8, x9, x1, x4) + +inst_144: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0b9 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x262 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x38b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34b9; op2val:0xc262; +op3val:0x3b8b; valaddr_reg:x5; val_offset:360*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 360*FLEN/8, x9, x1, x4) + +inst_145: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x25f and fs2 == 1 and fe2 == 0x14 and fm2 == 0x0e7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3d1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x265f; op2val:0xd0e7; +op3val:0x3bd1; valaddr_reg:x5; val_offset:363*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 363*FLEN/8, x9, x1, x4) + +inst_146: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x25f and fs2 == 1 and fe2 == 0x14 and fm2 == 0x0e7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3d1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x265f; op2val:0xd0e7; +op3val:0x3bd1; valaddr_reg:x5; val_offset:366*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 366*FLEN/8, x9, x1, x4) + +inst_147: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x25f and fs2 == 1 and fe2 == 0x14 and fm2 == 0x0e7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3d1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x265f; op2val:0xd0e7; +op3val:0x3bd1; valaddr_reg:x5; val_offset:369*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 369*FLEN/8, x9, x1, x4) + +inst_148: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x25f and fs2 == 1 and fe2 == 0x14 and fm2 == 0x0e7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3d1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x265f; op2val:0xd0e7; +op3val:0x3bd1; valaddr_reg:x5; val_offset:372*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 372*FLEN/8, x9, x1, x4) + +inst_149: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x25f and fs2 == 1 and fe2 == 0x14 and fm2 == 0x0e7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3d1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x265f; op2val:0xd0e7; +op3val:0x3bd1; valaddr_reg:x5; val_offset:375*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 375*FLEN/8, x9, x1, x4) + +inst_150: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0f5 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x0f6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3400; op2val:0xb8f5; +op3val:0x30f6; valaddr_reg:x5; val_offset:378*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 378*FLEN/8, x9, x1, x4) + +inst_151: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0f5 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x0f6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3400; op2val:0xb8f5; +op3val:0x30f6; valaddr_reg:x5; val_offset:381*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 381*FLEN/8, x9, x1, x4) + +inst_152: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0f5 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x0f6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3400; op2val:0xb8f5; +op3val:0x30f6; valaddr_reg:x5; val_offset:384*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 384*FLEN/8, x9, x1, x4) + +inst_153: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0f5 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x0f6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3400; op2val:0xb8f5; +op3val:0x30f6; valaddr_reg:x5; val_offset:387*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 387*FLEN/8, x9, x1, x4) + +inst_154: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0f5 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x0f6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3400; op2val:0xb8f5; +op3val:0x30f6; valaddr_reg:x5; val_offset:390*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 390*FLEN/8, x9, x1, x4) + +inst_155: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3da and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2ea and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2ca and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bda; op2val:0xb2ea; +op3val:0x32ca; valaddr_reg:x5; val_offset:393*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 393*FLEN/8, x9, x1, x4) + +inst_156: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3da and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2ea and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2ca and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bda; op2val:0xb2ea; +op3val:0x32ca; valaddr_reg:x5; val_offset:396*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 396*FLEN/8, x9, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_2) + +inst_157: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3da and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2ea and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2ca and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bda; op2val:0xb2ea; +op3val:0x32ca; valaddr_reg:x5; val_offset:399*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 399*FLEN/8, x9, x1, x4) + +inst_158: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3da and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2ea and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2ca and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bda; op2val:0xb2ea; +op3val:0x32ca; valaddr_reg:x5; val_offset:402*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 402*FLEN/8, x9, x1, x4) + +inst_159: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3da and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2ea and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2ca and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bda; op2val:0xb2ea; +op3val:0x32ca; valaddr_reg:x5; val_offset:405*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 405*FLEN/8, x9, x1, x4) + +inst_160: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x112 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x151 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2be and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3912; op2val:0xb951; +op3val:0x36be; valaddr_reg:x5; val_offset:408*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 408*FLEN/8, x9, x1, x4) + +inst_161: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x112 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x151 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2be and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3912; op2val:0xb951; +op3val:0x36be; valaddr_reg:x5; val_offset:411*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 411*FLEN/8, x9, x1, x4) + +inst_162: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x112 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x151 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2be and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3912; op2val:0xb951; +op3val:0x36be; valaddr_reg:x5; val_offset:414*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 414*FLEN/8, x9, x1, x4) + +inst_163: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x112 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x151 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2be and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3912; op2val:0xb951; +op3val:0x36be; valaddr_reg:x5; val_offset:417*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 417*FLEN/8, x9, x1, x4) + +inst_164: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x112 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x151 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2be and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3912; op2val:0xb951; +op3val:0x36be; valaddr_reg:x5; val_offset:420*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 420*FLEN/8, x9, x1, x4) + +inst_165: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ed and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3a0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bed; op2val:0xbbb2; +op3val:0x3ba0; valaddr_reg:x5; val_offset:423*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 423*FLEN/8, x9, x1, x4) + +inst_166: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ed and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3a0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bed; op2val:0xbbb2; +op3val:0x3ba0; valaddr_reg:x5; val_offset:426*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 426*FLEN/8, x9, x1, x4) + +inst_167: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ed and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3a0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bed; op2val:0xbbb2; +op3val:0x3ba0; valaddr_reg:x5; val_offset:429*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 429*FLEN/8, x9, x1, x4) + +inst_168: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ed and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3a0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bed; op2val:0xbbb2; +op3val:0x3ba0; valaddr_reg:x5; val_offset:432*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 432*FLEN/8, x9, x1, x4) + +inst_169: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ed and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3a0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bed; op2val:0xbbb2; +op3val:0x3ba0; valaddr_reg:x5; val_offset:435*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 435*FLEN/8, x9, x1, x4) + +inst_170: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x28d and fs2 == 1 and fe2 == 0x0a and fm2 == 0x301 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x1bc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a8d; op2val:0xab01; +op3val:0x29bc; valaddr_reg:x5; val_offset:438*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 438*FLEN/8, x9, x1, x4) + +inst_171: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x28d and fs2 == 1 and fe2 == 0x0a and fm2 == 0x301 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x1bc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a8d; op2val:0xab01; +op3val:0x29bc; valaddr_reg:x5; val_offset:441*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 441*FLEN/8, x9, x1, x4) + +inst_172: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x28d and fs2 == 1 and fe2 == 0x0a and fm2 == 0x301 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x1bc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a8d; op2val:0xab01; +op3val:0x29bc; valaddr_reg:x5; val_offset:444*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 444*FLEN/8, x9, x1, x4) + +inst_173: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x28d and fs2 == 1 and fe2 == 0x0a and fm2 == 0x301 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x1bc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a8d; op2val:0xab01; +op3val:0x29bc; valaddr_reg:x5; val_offset:447*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 447*FLEN/8, x9, x1, x4) + +inst_174: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x28d and fs2 == 1 and fe2 == 0x0a and fm2 == 0x301 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x1bc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a8d; op2val:0xab01; +op3val:0x29bc; valaddr_reg:x5; val_offset:450*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 450*FLEN/8, x9, x1, x4) + +inst_175: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x26d and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0dd and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3d1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a6d; op2val:0xb4dd; +op3val:0x33d1; valaddr_reg:x5; val_offset:453*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 453*FLEN/8, x9, x1, x4) + +inst_176: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x26d and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0dd and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3d1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a6d; op2val:0xb4dd; +op3val:0x33d1; valaddr_reg:x5; val_offset:456*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 456*FLEN/8, x9, x1, x4) + +inst_177: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x26d and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0dd and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3d1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a6d; op2val:0xb4dd; +op3val:0x33d1; valaddr_reg:x5; val_offset:459*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 459*FLEN/8, x9, x1, x4) + +inst_178: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x26d and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0dd and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3d1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a6d; op2val:0xb4dd; +op3val:0x33d1; valaddr_reg:x5; val_offset:462*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 462*FLEN/8, x9, x1, x4) + +inst_179: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x26d and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0dd and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3d1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a6d; op2val:0xb4dd; +op3val:0x33d1; valaddr_reg:x5; val_offset:465*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 465*FLEN/8, x9, x1, x4) + +inst_180: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x080 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x297 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x36b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2c80; op2val:0xba97; +op3val:0x2b6b; valaddr_reg:x5; val_offset:468*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 468*FLEN/8, x9, x1, x4) + +inst_181: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x080 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x297 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x36b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2c80; op2val:0xba97; +op3val:0x2b6b; valaddr_reg:x5; val_offset:471*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 471*FLEN/8, x9, x1, x4) + +inst_182: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x080 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x297 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x36b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2c80; op2val:0xba97; +op3val:0x2b6b; valaddr_reg:x5; val_offset:474*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 474*FLEN/8, x9, x1, x4) + +inst_183: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x080 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x297 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x36b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2c80; op2val:0xba97; +op3val:0x2b6b; valaddr_reg:x5; val_offset:477*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 477*FLEN/8, x9, x1, x4) + +inst_184: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x080 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x297 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x36b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2c80; op2val:0xba97; +op3val:0x2b6b; valaddr_reg:x5; val_offset:480*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 480*FLEN/8, x9, x1, x4) + +inst_185: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x13e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3df and fs3 == 0 and fe3 == 0x0e and fm3 == 0x129 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x393e; op2val:0xbbdf; +op3val:0x3929; valaddr_reg:x5; val_offset:483*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 483*FLEN/8, x9, x1, x4) + +inst_186: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x13e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3df and fs3 == 0 and fe3 == 0x0e and fm3 == 0x129 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x393e; op2val:0xbbdf; +op3val:0x3929; valaddr_reg:x5; val_offset:486*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 486*FLEN/8, x9, x1, x4) + +inst_187: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x13e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3df and fs3 == 0 and fe3 == 0x0e and fm3 == 0x129 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x393e; op2val:0xbbdf; +op3val:0x3929; valaddr_reg:x5; val_offset:489*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 489*FLEN/8, x9, x1, x4) + +inst_188: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x13e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3df and fs3 == 0 and fe3 == 0x0e and fm3 == 0x129 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x393e; op2val:0xbbdf; +op3val:0x3929; valaddr_reg:x5; val_offset:492*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 492*FLEN/8, x9, x1, x4) + +inst_189: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x13e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3df and fs3 == 0 and fe3 == 0x0e and fm3 == 0x129 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x393e; op2val:0xbbdf; +op3val:0x3929; valaddr_reg:x5; val_offset:495*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 495*FLEN/8, x9, x1, x4) + +inst_190: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x39a and fs2 == 1 and fe2 == 0x0d and fm2 == 0x38d and fs3 == 0 and fe3 == 0x0c and fm3 == 0x32e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x379a; op2val:0xb78d; +op3val:0x332e; valaddr_reg:x5; val_offset:498*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 498*FLEN/8, x9, x1, x4) + +inst_191: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x39a and fs2 == 1 and fe2 == 0x0d and fm2 == 0x38d and fs3 == 0 and fe3 == 0x0c and fm3 == 0x32e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x379a; op2val:0xb78d; +op3val:0x332e; valaddr_reg:x5; val_offset:501*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 501*FLEN/8, x9, x1, x4) + +inst_192: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x39a and fs2 == 1 and fe2 == 0x0d and fm2 == 0x38d and fs3 == 0 and fe3 == 0x0c and fm3 == 0x32e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x379a; op2val:0xb78d; +op3val:0x332e; valaddr_reg:x5; val_offset:504*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 504*FLEN/8, x9, x1, x4) + +inst_193: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x39a and fs2 == 1 and fe2 == 0x0d and fm2 == 0x38d and fs3 == 0 and fe3 == 0x0c and fm3 == 0x32e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x379a; op2val:0xb78d; +op3val:0x332e; valaddr_reg:x5; val_offset:507*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 507*FLEN/8, x9, x1, x4) + +inst_194: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x39a and fs2 == 1 and fe2 == 0x0d and fm2 == 0x38d and fs3 == 0 and fe3 == 0x0c and fm3 == 0x32e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x379a; op2val:0xb78d; +op3val:0x332e; valaddr_reg:x5; val_offset:510*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 510*FLEN/8, x9, x1, x4) + +inst_195: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x322 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x083 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x006 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b22; op2val:0xb483; +op3val:0x3406; valaddr_reg:x5; val_offset:513*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 513*FLEN/8, x9, x1, x4) + +inst_196: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x322 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x083 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x006 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b22; op2val:0xb483; +op3val:0x3406; valaddr_reg:x5; val_offset:516*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 516*FLEN/8, x9, x1, x4) + +inst_197: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x322 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x083 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x006 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b22; op2val:0xb483; +op3val:0x3406; valaddr_reg:x5; val_offset:519*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 519*FLEN/8, x9, x1, x4) + +inst_198: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x322 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x083 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x006 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b22; op2val:0xb483; +op3val:0x3406; valaddr_reg:x5; val_offset:522*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 522*FLEN/8, x9, x1, x4) + +inst_199: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x322 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x083 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x006 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b22; op2val:0xb483; +op3val:0x3406; valaddr_reg:x5; val_offset:525*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 525*FLEN/8, x9, x1, x4) + +inst_200: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x27d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x189 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x07d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x327d; op2val:0xb989; +op3val:0x307d; valaddr_reg:x5; val_offset:528*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 528*FLEN/8, x9, x1, x4) + +inst_201: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x27d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x189 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x07d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x327d; op2val:0xb989; +op3val:0x307d; valaddr_reg:x5; val_offset:531*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 531*FLEN/8, x9, x1, x4) + +inst_202: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x27d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x189 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x07d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x327d; op2val:0xb989; +op3val:0x307d; valaddr_reg:x5; val_offset:534*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 534*FLEN/8, x9, x1, x4) + +inst_203: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x27d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x189 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x07d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x327d; op2val:0xb989; +op3val:0x307d; valaddr_reg:x5; val_offset:537*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 537*FLEN/8, x9, x1, x4) + +inst_204: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x27d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x189 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x07d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x327d; op2val:0xb989; +op3val:0x307d; valaddr_reg:x5; val_offset:540*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 540*FLEN/8, x9, x1, x4) + +inst_205: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b4 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x333 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x2f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bb4; op2val:0xab33; +op3val:0x2af0; valaddr_reg:x5; val_offset:543*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 543*FLEN/8, x9, x1, x4) + +inst_206: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b4 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x333 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x2f0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bb4; op2val:0xab33; +op3val:0x2af0; valaddr_reg:x5; val_offset:546*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 546*FLEN/8, x9, x1, x4) + +inst_207: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b4 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x333 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x2f0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bb4; op2val:0xab33; +op3val:0x2af0; valaddr_reg:x5; val_offset:549*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 549*FLEN/8, x9, x1, x4) + +inst_208: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b4 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x333 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x2f0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bb4; op2val:0xab33; +op3val:0x2af0; valaddr_reg:x5; val_offset:552*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 552*FLEN/8, x9, x1, x4) + +inst_209: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b4 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x333 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x2f0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bb4; op2val:0xab33; +op3val:0x2af0; valaddr_reg:x5; val_offset:555*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 555*FLEN/8, x9, x1, x4) + +inst_210: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x345 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1cd and fs3 == 0 and fe3 == 0x0e and fm3 == 0x146 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b45; op2val:0xb9cd; +op3val:0x3946; valaddr_reg:x5; val_offset:558*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 558*FLEN/8, x9, x1, x4) + +inst_211: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x345 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1cd and fs3 == 0 and fe3 == 0x0e and fm3 == 0x146 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b45; op2val:0xb9cd; +op3val:0x3946; valaddr_reg:x5; val_offset:561*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 561*FLEN/8, x9, x1, x4) + +inst_212: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x345 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1cd and fs3 == 0 and fe3 == 0x0e and fm3 == 0x146 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b45; op2val:0xb9cd; +op3val:0x3946; valaddr_reg:x5; val_offset:564*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 564*FLEN/8, x9, x1, x4) + +inst_213: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x345 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1cd and fs3 == 0 and fe3 == 0x0e and fm3 == 0x146 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b45; op2val:0xb9cd; +op3val:0x3946; valaddr_reg:x5; val_offset:567*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 567*FLEN/8, x9, x1, x4) + +inst_214: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x345 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1cd and fs3 == 0 and fe3 == 0x0e and fm3 == 0x146 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b45; op2val:0xb9cd; +op3val:0x3946; valaddr_reg:x5; val_offset:570*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 570*FLEN/8, x9, x1, x4) + +inst_215: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x23a and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2bb and fs3 == 0 and fe3 == 0x0b and fm3 == 0x13e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x363a; op2val:0xb2bb; +op3val:0x2d3e; valaddr_reg:x5; val_offset:573*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 573*FLEN/8, x9, x1, x4) + +inst_216: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x23a and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2bb and fs3 == 0 and fe3 == 0x0b and fm3 == 0x13e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x363a; op2val:0xb2bb; +op3val:0x2d3e; valaddr_reg:x5; val_offset:576*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 576*FLEN/8, x9, x1, x4) + +inst_217: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x23a and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2bb and fs3 == 0 and fe3 == 0x0b and fm3 == 0x13e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x363a; op2val:0xb2bb; +op3val:0x2d3e; valaddr_reg:x5; val_offset:579*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 579*FLEN/8, x9, x1, x4) + +inst_218: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x23a and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2bb and fs3 == 0 and fe3 == 0x0b and fm3 == 0x13e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x363a; op2val:0xb2bb; +op3val:0x2d3e; valaddr_reg:x5; val_offset:582*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 582*FLEN/8, x9, x1, x4) + +inst_219: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x23a and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2bb and fs3 == 0 and fe3 == 0x0b and fm3 == 0x13e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x363a; op2val:0xb2bb; +op3val:0x2d3e; valaddr_reg:x5; val_offset:585*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 585*FLEN/8, x9, x1, x4) + +inst_220: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x147 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x359 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0da and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3947; op2val:0xaf59; +op3val:0x2cda; valaddr_reg:x5; val_offset:588*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 588*FLEN/8, x9, x1, x4) + +inst_221: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x147 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x359 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0da and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3947; op2val:0xaf59; +op3val:0x2cda; valaddr_reg:x5; val_offset:591*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 591*FLEN/8, x9, x1, x4) + +inst_222: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x147 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x359 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0da and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3947; op2val:0xaf59; +op3val:0x2cda; valaddr_reg:x5; val_offset:594*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 594*FLEN/8, x9, x1, x4) + +inst_223: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x147 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x359 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0da and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3947; op2val:0xaf59; +op3val:0x2cda; valaddr_reg:x5; val_offset:597*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 597*FLEN/8, x9, x1, x4) + +inst_224: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x147 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x359 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0da and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3947; op2val:0xaf59; +op3val:0x2cda; valaddr_reg:x5; val_offset:600*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 600*FLEN/8, x9, x1, x4) + +inst_225: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x347 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x20b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x180 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3747; op2val:0xbe0b; +op3val:0x3980; valaddr_reg:x5; val_offset:603*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 603*FLEN/8, x9, x1, x4) + +inst_226: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x347 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x20b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x180 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3747; op2val:0xbe0b; +op3val:0x3980; valaddr_reg:x5; val_offset:606*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 606*FLEN/8, x9, x1, x4) + +inst_227: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x347 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x20b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x180 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3747; op2val:0xbe0b; +op3val:0x3980; valaddr_reg:x5; val_offset:609*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 609*FLEN/8, x9, x1, x4) + +inst_228: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x347 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x20b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x180 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3747; op2val:0xbe0b; +op3val:0x3980; valaddr_reg:x5; val_offset:612*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 612*FLEN/8, x9, x1, x4) + +inst_229: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x347 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x20b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x180 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3747; op2val:0xbe0b; +op3val:0x3980; valaddr_reg:x5; val_offset:615*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 615*FLEN/8, x9, x1, x4) + +inst_230: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x177 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0d0 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x294 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3977; op2val:0xbcd0; +op3val:0x3a94; valaddr_reg:x5; val_offset:618*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 618*FLEN/8, x9, x1, x4) + +inst_231: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x177 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0d0 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x294 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3977; op2val:0xbcd0; +op3val:0x3a94; valaddr_reg:x5; val_offset:621*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 621*FLEN/8, x9, x1, x4) + +inst_232: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x177 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0d0 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x294 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3977; op2val:0xbcd0; +op3val:0x3a94; valaddr_reg:x5; val_offset:624*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 624*FLEN/8, x9, x1, x4) + +inst_233: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x177 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0d0 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x294 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3977; op2val:0xbcd0; +op3val:0x3a94; valaddr_reg:x5; val_offset:627*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 627*FLEN/8, x9, x1, x4) + +inst_234: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x177 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0d0 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x294 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3977; op2val:0xbcd0; +op3val:0x3a94; valaddr_reg:x5; val_offset:630*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 630*FLEN/8, x9, x1, x4) + +inst_235: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x35f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x362 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2cf and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b5f; op2val:0xbb62; +op3val:0x3acf; valaddr_reg:x5; val_offset:633*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 633*FLEN/8, x9, x1, x4) + +inst_236: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x35f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x362 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2cf and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b5f; op2val:0xbb62; +op3val:0x3acf; valaddr_reg:x5; val_offset:636*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 636*FLEN/8, x9, x1, x4) + +inst_237: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x35f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x362 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2cf and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b5f; op2val:0xbb62; +op3val:0x3acf; valaddr_reg:x5; val_offset:639*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 639*FLEN/8, x9, x1, x4) + +inst_238: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x35f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x362 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2cf and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b5f; op2val:0xbb62; +op3val:0x3acf; valaddr_reg:x5; val_offset:642*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 642*FLEN/8, x9, x1, x4) + +inst_239: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x35f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x362 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2cf and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b5f; op2val:0xbb62; +op3val:0x3acf; valaddr_reg:x5; val_offset:645*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 645*FLEN/8, x9, x1, x4) + +inst_240: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0f9 and fs2 == 1 and fe2 == 0x08 and fm2 == 0x163 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x2d3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34f9; op2val:0xa163; +op3val:0x1ad3; valaddr_reg:x5; val_offset:648*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 648*FLEN/8, x9, x1, x4) + +inst_241: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0f9 and fs2 == 1 and fe2 == 0x08 and fm2 == 0x163 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x2d3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34f9; op2val:0xa163; +op3val:0x1ad3; valaddr_reg:x5; val_offset:651*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 651*FLEN/8, x9, x1, x4) + +inst_242: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0f9 and fs2 == 1 and fe2 == 0x08 and fm2 == 0x163 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x2d3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34f9; op2val:0xa163; +op3val:0x1ad3; valaddr_reg:x5; val_offset:654*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 654*FLEN/8, x9, x1, x4) + +inst_243: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0f9 and fs2 == 1 and fe2 == 0x08 and fm2 == 0x163 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x2d3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34f9; op2val:0xa163; +op3val:0x1ad3; valaddr_reg:x5; val_offset:657*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 657*FLEN/8, x9, x1, x4) + +inst_244: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0f9 and fs2 == 1 and fe2 == 0x08 and fm2 == 0x163 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x2d3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34f9; op2val:0xa163; +op3val:0x1ad3; valaddr_reg:x5; val_offset:660*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 660*FLEN/8, x9, x1, x4) + +inst_245: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b5 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x089 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x39c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ab5; op2val:0xbc89; +op3val:0x3b9c; valaddr_reg:x5; val_offset:663*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 663*FLEN/8, x9, x1, x4) + +inst_246: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b5 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x089 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x39c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ab5; op2val:0xbc89; +op3val:0x3b9c; valaddr_reg:x5; val_offset:666*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 666*FLEN/8, x9, x1, x4) + +inst_247: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b5 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x089 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x39c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ab5; op2val:0xbc89; +op3val:0x3b9c; valaddr_reg:x5; val_offset:669*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 669*FLEN/8, x9, x1, x4) + +inst_248: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b5 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x089 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x39c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ab5; op2val:0xbc89; +op3val:0x3b9c; valaddr_reg:x5; val_offset:672*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 672*FLEN/8, x9, x1, x4) + +inst_249: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b5 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x089 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x39c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ab5; op2val:0xbc89; +op3val:0x3b9c; valaddr_reg:x5; val_offset:675*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 675*FLEN/8, x9, x1, x4) + +inst_250: +// fs1 == 0 and fe1 == 0x08 and fm1 == 0x2d7 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x05d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x376 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x22d7; op2val:0xd05d; +op3val:0x3776; valaddr_reg:x5; val_offset:678*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 678*FLEN/8, x9, x1, x4) + +inst_251: +// fs1 == 0 and fe1 == 0x08 and fm1 == 0x2d7 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x05d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x376 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x22d7; op2val:0xd05d; +op3val:0x3776; valaddr_reg:x5; val_offset:681*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 681*FLEN/8, x9, x1, x4) + +inst_252: +// fs1 == 0 and fe1 == 0x08 and fm1 == 0x2d7 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x05d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x376 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x22d7; op2val:0xd05d; +op3val:0x3776; valaddr_reg:x5; val_offset:684*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 684*FLEN/8, x9, x1, x4) + +inst_253: +// fs1 == 0 and fe1 == 0x08 and fm1 == 0x2d7 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x05d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x376 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x22d7; op2val:0xd05d; +op3val:0x3776; valaddr_reg:x5; val_offset:687*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 687*FLEN/8, x9, x1, x4) + +inst_254: +// fs1 == 0 and fe1 == 0x08 and fm1 == 0x2d7 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x05d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x376 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x22d7; op2val:0xd05d; +op3val:0x3776; valaddr_reg:x5; val_offset:690*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 690*FLEN/8, x9, x1, x4) + +inst_255: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0c0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x122 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x219 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38c0; op2val:0xbd22; +op3val:0x3a19; valaddr_reg:x5; val_offset:693*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 693*FLEN/8, x9, x1, x4) + +inst_256: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0c0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x122 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x219 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38c0; op2val:0xbd22; +op3val:0x3a19; valaddr_reg:x5; val_offset:696*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 696*FLEN/8, x9, x1, x4) + +inst_257: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0c0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x122 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x219 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38c0; op2val:0xbd22; +op3val:0x3a19; valaddr_reg:x5; val_offset:699*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 699*FLEN/8, x9, x1, x4) + +inst_258: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0c0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x122 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x219 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38c0; op2val:0xbd22; +op3val:0x3a19; valaddr_reg:x5; val_offset:702*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 702*FLEN/8, x9, x1, x4) + +inst_259: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0c0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x122 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x219 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38c0; op2val:0xbd22; +op3val:0x3a19; valaddr_reg:x5; val_offset:705*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 705*FLEN/8, x9, x1, x4) + +inst_260: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x27f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2d8 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x18f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x367f; op2val:0xb6d8; +op3val:0x318f; valaddr_reg:x5; val_offset:708*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 708*FLEN/8, x9, x1, x4) + +inst_261: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x27f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2d8 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x18f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x367f; op2val:0xb6d8; +op3val:0x318f; valaddr_reg:x5; val_offset:711*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 711*FLEN/8, x9, x1, x4) + +inst_262: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x27f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2d8 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x18f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x367f; op2val:0xb6d8; +op3val:0x318f; valaddr_reg:x5; val_offset:714*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 714*FLEN/8, x9, x1, x4) + +inst_263: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x27f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2d8 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x18f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x367f; op2val:0xb6d8; +op3val:0x318f; valaddr_reg:x5; val_offset:717*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 717*FLEN/8, x9, x1, x4) + +inst_264: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x27f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2d8 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x18f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x367f; op2val:0xb6d8; +op3val:0x318f; valaddr_reg:x5; val_offset:720*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 720*FLEN/8, x9, x1, x4) + +inst_265: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x05a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x03f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0a0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x385a; op2val:0xbc3f; +op3val:0x38a0; valaddr_reg:x5; val_offset:723*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 723*FLEN/8, x9, x1, x4) + +inst_266: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x05a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x03f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0a0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x385a; op2val:0xbc3f; +op3val:0x38a0; valaddr_reg:x5; val_offset:726*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 726*FLEN/8, x9, x1, x4) + +inst_267: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x05a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x03f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0a0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x385a; op2val:0xbc3f; +op3val:0x38a0; valaddr_reg:x5; val_offset:729*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 729*FLEN/8, x9, x1, x4) + +inst_268: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x05a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x03f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0a0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x385a; op2val:0xbc3f; +op3val:0x38a0; valaddr_reg:x5; val_offset:732*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 732*FLEN/8, x9, x1, x4) + +inst_269: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x05a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x03f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0a0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x385a; op2val:0xbc3f; +op3val:0x38a0; valaddr_reg:x5; val_offset:735*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 735*FLEN/8, x9, x1, x4) + +inst_270: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x38d and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1b0 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x160 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b8d; op2val:0xadb0; +op3val:0x2d60; valaddr_reg:x5; val_offset:738*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 738*FLEN/8, x9, x1, x4) + +inst_271: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x38d and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1b0 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x160 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b8d; op2val:0xadb0; +op3val:0x2d60; valaddr_reg:x5; val_offset:741*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 741*FLEN/8, x9, x1, x4) + +inst_272: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x38d and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1b0 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x160 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b8d; op2val:0xadb0; +op3val:0x2d60; valaddr_reg:x5; val_offset:744*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 744*FLEN/8, x9, x1, x4) + +inst_273: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x38d and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1b0 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x160 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b8d; op2val:0xadb0; +op3val:0x2d60; valaddr_reg:x5; val_offset:747*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 747*FLEN/8, x9, x1, x4) + +inst_274: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x38d and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1b0 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x160 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b8d; op2val:0xadb0; +op3val:0x2d60; valaddr_reg:x5; val_offset:750*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 750*FLEN/8, x9, x1, x4) + +inst_275: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3bc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x030 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x00d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bbc; op2val:0xb830; +op3val:0x380d; valaddr_reg:x5; val_offset:753*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 753*FLEN/8, x9, x1, x4) + +inst_276: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3bc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x030 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x00d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bbc; op2val:0xb830; +op3val:0x380d; valaddr_reg:x5; val_offset:756*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 756*FLEN/8, x9, x1, x4) + +inst_277: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3bc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x030 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x00d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bbc; op2val:0xb830; +op3val:0x380d; valaddr_reg:x5; val_offset:759*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 759*FLEN/8, x9, x1, x4) + +inst_278: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3bc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x030 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x00d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bbc; op2val:0xb830; +op3val:0x380d; valaddr_reg:x5; val_offset:762*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 762*FLEN/8, x9, x1, x4) + +inst_279: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3bc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x030 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x00d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bbc; op2val:0xb830; +op3val:0x380d; valaddr_reg:x5; val_offset:765*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 765*FLEN/8, x9, x1, x4) + +inst_280: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x12c and fs2 == 1 and fe2 == 0x11 and fm2 == 0x161 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2f4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x312c; op2val:0xc561; +op3val:0x3af4; valaddr_reg:x5; val_offset:768*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 768*FLEN/8, x9, x1, x4) + +inst_281: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x12c and fs2 == 1 and fe2 == 0x11 and fm2 == 0x161 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2f4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x312c; op2val:0xc561; +op3val:0x3af4; valaddr_reg:x5; val_offset:771*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 771*FLEN/8, x9, x1, x4) + +inst_282: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x12c and fs2 == 1 and fe2 == 0x11 and fm2 == 0x161 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2f4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x312c; op2val:0xc561; +op3val:0x3af4; valaddr_reg:x5; val_offset:774*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 774*FLEN/8, x9, x1, x4) + +inst_283: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x12c and fs2 == 1 and fe2 == 0x11 and fm2 == 0x161 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2f4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x312c; op2val:0xc561; +op3val:0x3af4; valaddr_reg:x5; val_offset:777*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 777*FLEN/8, x9, x1, x4) + +inst_284: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x12c and fs2 == 1 and fe2 == 0x11 and fm2 == 0x161 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2f4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x312c; op2val:0xc561; +op3val:0x3af4; valaddr_reg:x5; val_offset:780*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 780*FLEN/8, x9, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_3) + +inst_285: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x04b and fs2 == 1 and fe2 == 0x0c and fm2 == 0x1fc and fs3 == 0 and fe3 == 0x0a and fm3 == 0x26e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x344b; op2val:0xb1fc; +op3val:0x2a6e; valaddr_reg:x5; val_offset:783*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 783*FLEN/8, x9, x1, x4) + +inst_286: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x04b and fs2 == 1 and fe2 == 0x0c and fm2 == 0x1fc and fs3 == 0 and fe3 == 0x0a and fm3 == 0x26e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x344b; op2val:0xb1fc; +op3val:0x2a6e; valaddr_reg:x5; val_offset:786*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 786*FLEN/8, x9, x1, x4) + +inst_287: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x04b and fs2 == 1 and fe2 == 0x0c and fm2 == 0x1fc and fs3 == 0 and fe3 == 0x0a and fm3 == 0x26e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x344b; op2val:0xb1fc; +op3val:0x2a6e; valaddr_reg:x5; val_offset:789*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 789*FLEN/8, x9, x1, x4) + +inst_288: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x04b and fs2 == 1 and fe2 == 0x0c and fm2 == 0x1fc and fs3 == 0 and fe3 == 0x0a and fm3 == 0x26e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x344b; op2val:0xb1fc; +op3val:0x2a6e; valaddr_reg:x5; val_offset:792*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 792*FLEN/8, x9, x1, x4) + +inst_289: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x04b and fs2 == 1 and fe2 == 0x0c and fm2 == 0x1fc and fs3 == 0 and fe3 == 0x0a and fm3 == 0x26e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x344b; op2val:0xb1fc; +op3val:0x2a6e; valaddr_reg:x5; val_offset:795*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 795*FLEN/8, x9, x1, x4) + +inst_290: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ea and fs2 == 1 and fe2 == 0x0e and fm2 == 0x096 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2c9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35ea; op2val:0xb896; +op3val:0x32c9; valaddr_reg:x5; val_offset:798*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 798*FLEN/8, x9, x1, x4) + +inst_291: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ea and fs2 == 1 and fe2 == 0x0e and fm2 == 0x096 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2c9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35ea; op2val:0xb896; +op3val:0x32c9; valaddr_reg:x5; val_offset:801*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 801*FLEN/8, x9, x1, x4) + +inst_292: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ea and fs2 == 1 and fe2 == 0x0e and fm2 == 0x096 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2c9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35ea; op2val:0xb896; +op3val:0x32c9; valaddr_reg:x5; val_offset:804*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 804*FLEN/8, x9, x1, x4) + +inst_293: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ea and fs2 == 1 and fe2 == 0x0e and fm2 == 0x096 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2c9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35ea; op2val:0xb896; +op3val:0x32c9; valaddr_reg:x5; val_offset:807*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 807*FLEN/8, x9, x1, x4) + +inst_294: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ea and fs2 == 1 and fe2 == 0x0e and fm2 == 0x096 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2c9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35ea; op2val:0xb896; +op3val:0x32c9; valaddr_reg:x5; val_offset:810*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 810*FLEN/8, x9, x1, x4) + +inst_295: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x325 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x110 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x086 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b25; op2val:0xb910; +op3val:0x3886; valaddr_reg:x5; val_offset:813*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 813*FLEN/8, x9, x1, x4) + +inst_296: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x325 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x110 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x086 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b25; op2val:0xb910; +op3val:0x3886; valaddr_reg:x5; val_offset:816*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 816*FLEN/8, x9, x1, x4) + +inst_297: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x325 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x110 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x086 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b25; op2val:0xb910; +op3val:0x3886; valaddr_reg:x5; val_offset:819*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 819*FLEN/8, x9, x1, x4) + +inst_298: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x325 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x110 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x086 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b25; op2val:0xb910; +op3val:0x3886; valaddr_reg:x5; val_offset:822*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 822*FLEN/8, x9, x1, x4) + +inst_299: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x325 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x110 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x086 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b25; op2val:0xb910; +op3val:0x3886; valaddr_reg:x5; val_offset:825*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 825*FLEN/8, x9, x1, x4) + +inst_300: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ce and fs2 == 1 and fe2 == 0x0c and fm2 == 0x1d6 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x0f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ace; op2val:0xb1d6; +op3val:0x30f8; valaddr_reg:x5; val_offset:828*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 828*FLEN/8, x9, x1, x4) + +inst_301: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ce and fs2 == 1 and fe2 == 0x0c and fm2 == 0x1d6 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x0f8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ace; op2val:0xb1d6; +op3val:0x30f8; valaddr_reg:x5; val_offset:831*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 831*FLEN/8, x9, x1, x4) + +inst_302: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ce and fs2 == 1 and fe2 == 0x0c and fm2 == 0x1d6 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x0f8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ace; op2val:0xb1d6; +op3val:0x30f8; valaddr_reg:x5; val_offset:834*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 834*FLEN/8, x9, x1, x4) + +inst_303: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ce and fs2 == 1 and fe2 == 0x0c and fm2 == 0x1d6 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x0f8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ace; op2val:0xb1d6; +op3val:0x30f8; valaddr_reg:x5; val_offset:837*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 837*FLEN/8, x9, x1, x4) + +inst_304: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ce and fs2 == 1 and fe2 == 0x0c and fm2 == 0x1d6 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x0f8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ace; op2val:0xb1d6; +op3val:0x30f8; valaddr_reg:x5; val_offset:840*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 840*FLEN/8, x9, x1, x4) + +inst_305: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x234 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x05f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39a4; op2val:0xba34; +op3val:0x385f; valaddr_reg:x5; val_offset:843*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 843*FLEN/8, x9, x1, x4) + +inst_306: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x234 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x05f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39a4; op2val:0xba34; +op3val:0x385f; valaddr_reg:x5; val_offset:846*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 846*FLEN/8, x9, x1, x4) + +inst_307: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x234 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x05f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39a4; op2val:0xba34; +op3val:0x385f; valaddr_reg:x5; val_offset:849*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 849*FLEN/8, x9, x1, x4) + +inst_308: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x234 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x05f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39a4; op2val:0xba34; +op3val:0x385f; valaddr_reg:x5; val_offset:852*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 852*FLEN/8, x9, x1, x4) + +inst_309: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x234 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x05f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39a4; op2val:0xba34; +op3val:0x385f; valaddr_reg:x5; val_offset:855*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 855*FLEN/8, x9, x1, x4) + +inst_310: +// fs1 == 0 and fe1 == 0x04 and fm1 == 0x23b and fs2 == 1 and fe2 == 0x16 and fm2 == 0x211 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x0ba and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x123b; op2val:0xda11; +op3val:0x30ba; valaddr_reg:x5; val_offset:858*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 858*FLEN/8, x9, x1, x4) + +inst_311: +// fs1 == 0 and fe1 == 0x04 and fm1 == 0x23b and fs2 == 1 and fe2 == 0x16 and fm2 == 0x211 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x0ba and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x123b; op2val:0xda11; +op3val:0x30ba; valaddr_reg:x5; val_offset:861*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 861*FLEN/8, x9, x1, x4) + +inst_312: +// fs1 == 0 and fe1 == 0x04 and fm1 == 0x23b and fs2 == 1 and fe2 == 0x16 and fm2 == 0x211 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x0ba and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x123b; op2val:0xda11; +op3val:0x30ba; valaddr_reg:x5; val_offset:864*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 864*FLEN/8, x9, x1, x4) + +inst_313: +// fs1 == 0 and fe1 == 0x04 and fm1 == 0x23b and fs2 == 1 and fe2 == 0x16 and fm2 == 0x211 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x0ba and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x123b; op2val:0xda11; +op3val:0x30ba; valaddr_reg:x5; val_offset:867*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 867*FLEN/8, x9, x1, x4) + +inst_314: +// fs1 == 0 and fe1 == 0x04 and fm1 == 0x23b and fs2 == 1 and fe2 == 0x16 and fm2 == 0x211 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x0ba and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x123b; op2val:0xda11; +op3val:0x30ba; valaddr_reg:x5; val_offset:870*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 870*FLEN/8, x9, x1, x4) + +inst_315: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x228 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x1ad and fs3 == 0 and fe3 == 0x0e and fm3 == 0x05f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2628; op2val:0xcdad; +op3val:0x385f; valaddr_reg:x5; val_offset:873*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 873*FLEN/8, x9, x1, x4) + +inst_316: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x228 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x1ad and fs3 == 0 and fe3 == 0x0e and fm3 == 0x05f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2628; op2val:0xcdad; +op3val:0x385f; valaddr_reg:x5; val_offset:876*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 876*FLEN/8, x9, x1, x4) + +inst_317: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x228 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x1ad and fs3 == 0 and fe3 == 0x0e and fm3 == 0x05f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2628; op2val:0xcdad; +op3val:0x385f; valaddr_reg:x5; val_offset:879*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 879*FLEN/8, x9, x1, x4) + +inst_318: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x228 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x1ad and fs3 == 0 and fe3 == 0x0e and fm3 == 0x05f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2628; op2val:0xcdad; +op3val:0x385f; valaddr_reg:x5; val_offset:882*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 882*FLEN/8, x9, x1, x4) + +inst_319: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x228 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x1ad and fs3 == 0 and fe3 == 0x0e and fm3 == 0x05f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2628; op2val:0xcdad; +op3val:0x385f; valaddr_reg:x5; val_offset:885*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 885*FLEN/8, x9, x1, x4) + +inst_320: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x018 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x03a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x054 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3818; op2val:0xb83a; +op3val:0x3454; valaddr_reg:x5; val_offset:888*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 888*FLEN/8, x9, x1, x4) + +inst_321: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x018 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x03a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x054 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3818; op2val:0xb83a; +op3val:0x3454; valaddr_reg:x5; val_offset:891*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 891*FLEN/8, x9, x1, x4) + +inst_322: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x018 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x03a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x054 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3818; op2val:0xb83a; +op3val:0x3454; valaddr_reg:x5; val_offset:894*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 894*FLEN/8, x9, x1, x4) + +inst_323: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x018 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x03a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x054 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3818; op2val:0xb83a; +op3val:0x3454; valaddr_reg:x5; val_offset:897*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 897*FLEN/8, x9, x1, x4) + +inst_324: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x018 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x03a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x054 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3818; op2val:0xb83a; +op3val:0x3454; valaddr_reg:x5; val_offset:900*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 900*FLEN/8, x9, x1, x4) + +inst_325: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x171 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ac and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x382a; op2val:0xbd71; +op3val:0x39ac; valaddr_reg:x5; val_offset:903*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 903*FLEN/8, x9, x1, x4) + +inst_326: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x171 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ac and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x382a; op2val:0xbd71; +op3val:0x39ac; valaddr_reg:x5; val_offset:906*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 906*FLEN/8, x9, x1, x4) + +inst_327: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x171 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ac and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x382a; op2val:0xbd71; +op3val:0x39ac; valaddr_reg:x5; val_offset:909*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 909*FLEN/8, x9, x1, x4) + +inst_328: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x171 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ac and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x382a; op2val:0xbd71; +op3val:0x39ac; valaddr_reg:x5; val_offset:912*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 912*FLEN/8, x9, x1, x4) + +inst_329: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x171 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ac and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x382a; op2val:0xbd71; +op3val:0x39ac; valaddr_reg:x5; val_offset:915*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 915*FLEN/8, x9, x1, x4) + +inst_330: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0c5 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1b9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2d3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38c5; op2val:0xbdb9; +op3val:0x3ad3; valaddr_reg:x5; val_offset:918*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 918*FLEN/8, x9, x1, x4) + +inst_331: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0c5 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1b9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2d3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38c5; op2val:0xbdb9; +op3val:0x3ad3; valaddr_reg:x5; val_offset:921*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 921*FLEN/8, x9, x1, x4) + +inst_332: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0c5 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1b9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2d3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38c5; op2val:0xbdb9; +op3val:0x3ad3; valaddr_reg:x5; val_offset:924*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 924*FLEN/8, x9, x1, x4) + +inst_333: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0c5 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1b9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2d3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38c5; op2val:0xbdb9; +op3val:0x3ad3; valaddr_reg:x5; val_offset:927*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 927*FLEN/8, x9, x1, x4) + +inst_334: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0c5 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1b9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2d3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38c5; op2val:0xbdb9; +op3val:0x3ad3; valaddr_reg:x5; val_offset:930*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 930*FLEN/8, x9, x1, x4) + +inst_335: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x09 and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x1f9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38fb; op2val:0xa4c5; +op3val:0x21f9; valaddr_reg:x5; val_offset:933*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 933*FLEN/8, x9, x1, x4) + +inst_336: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x09 and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x1f9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38fb; op2val:0xa4c5; +op3val:0x21f9; valaddr_reg:x5; val_offset:936*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 936*FLEN/8, x9, x1, x4) + +inst_337: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x09 and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x1f9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38fb; op2val:0xa4c5; +op3val:0x21f9; valaddr_reg:x5; val_offset:939*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 939*FLEN/8, x9, x1, x4) + +inst_338: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x09 and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x1f9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38fb; op2val:0xa4c5; +op3val:0x21f9; valaddr_reg:x5; val_offset:942*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 942*FLEN/8, x9, x1, x4) + +inst_339: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x09 and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x1f9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38fb; op2val:0xa4c5; +op3val:0x21f9; valaddr_reg:x5; val_offset:945*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 945*FLEN/8, x9, x1, x4) + +inst_340: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x126 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0a2 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2926; op2val:0xc8a2; +op3val:0x35f8; valaddr_reg:x5; val_offset:948*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 948*FLEN/8, x9, x1, x4) + +inst_341: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x126 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0a2 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1f8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2926; op2val:0xc8a2; +op3val:0x35f8; valaddr_reg:x5; val_offset:951*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 951*FLEN/8, x9, x1, x4) + +inst_342: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x126 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0a2 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1f8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2926; op2val:0xc8a2; +op3val:0x35f8; valaddr_reg:x5; val_offset:954*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 954*FLEN/8, x9, x1, x4) + +inst_343: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x126 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0a2 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1f8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2926; op2val:0xc8a2; +op3val:0x35f8; valaddr_reg:x5; val_offset:957*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 957*FLEN/8, x9, x1, x4) + +inst_344: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x126 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0a2 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1f8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2926; op2val:0xc8a2; +op3val:0x35f8; valaddr_reg:x5; val_offset:960*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 960*FLEN/8, x9, x1, x4) + +inst_345: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x148 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x14a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3801; op2val:0xbd48; +op3val:0x394a; valaddr_reg:x5; val_offset:963*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 963*FLEN/8, x9, x1, x4) + +inst_346: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x148 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x14a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3801; op2val:0xbd48; +op3val:0x394a; valaddr_reg:x5; val_offset:966*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 966*FLEN/8, x9, x1, x4) + +inst_347: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x148 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x14a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3801; op2val:0xbd48; +op3val:0x394a; valaddr_reg:x5; val_offset:969*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 969*FLEN/8, x9, x1, x4) + +inst_348: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x148 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x14a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3801; op2val:0xbd48; +op3val:0x394a; valaddr_reg:x5; val_offset:972*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 972*FLEN/8, x9, x1, x4) + +inst_349: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x148 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x14a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3801; op2val:0xbd48; +op3val:0x394a; valaddr_reg:x5; val_offset:975*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 975*FLEN/8, x9, x1, x4) + +inst_350: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x349 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x264 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1d2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b49; op2val:0xba64; +op3val:0x39d2; valaddr_reg:x5; val_offset:978*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 978*FLEN/8, x9, x1, x4) + +inst_351: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x349 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x264 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1d2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b49; op2val:0xba64; +op3val:0x39d2; valaddr_reg:x5; val_offset:981*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 981*FLEN/8, x9, x1, x4) + +inst_352: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x349 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x264 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1d2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b49; op2val:0xba64; +op3val:0x39d2; valaddr_reg:x5; val_offset:984*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 984*FLEN/8, x9, x1, x4) + +inst_353: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x349 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x264 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1d2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b49; op2val:0xba64; +op3val:0x39d2; valaddr_reg:x5; val_offset:987*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 987*FLEN/8, x9, x1, x4) + +inst_354: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x349 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x264 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1d2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b49; op2val:0xba64; +op3val:0x39d2; valaddr_reg:x5; val_offset:990*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 990*FLEN/8, x9, x1, x4) + +inst_355: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2fa and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0dd and fs3 == 0 and fe3 == 0x0c and fm3 == 0x03e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32fa; op2val:0xb8dd; +op3val:0x303e; valaddr_reg:x5; val_offset:993*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 993*FLEN/8, x9, x1, x4) + +inst_356: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2fa and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0dd and fs3 == 0 and fe3 == 0x0c and fm3 == 0x03e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32fa; op2val:0xb8dd; +op3val:0x303e; valaddr_reg:x5; val_offset:996*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 996*FLEN/8, x9, x1, x4) + +inst_357: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2fa and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0dd and fs3 == 0 and fe3 == 0x0c and fm3 == 0x03e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32fa; op2val:0xb8dd; +op3val:0x303e; valaddr_reg:x5; val_offset:999*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 999*FLEN/8, x9, x1, x4) + +inst_358: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2fa and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0dd and fs3 == 0 and fe3 == 0x0c and fm3 == 0x03e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32fa; op2val:0xb8dd; +op3val:0x303e; valaddr_reg:x5; val_offset:1002*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1002*FLEN/8, x9, x1, x4) + +inst_359: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2fa and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0dd and fs3 == 0 and fe3 == 0x0c and fm3 == 0x03e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32fa; op2val:0xb8dd; +op3val:0x303e; valaddr_reg:x5; val_offset:1005*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1005*FLEN/8, x9, x1, x4) + +inst_360: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x15c and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2d9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x391c; op2val:0xb55c; +op3val:0x32d9; valaddr_reg:x5; val_offset:1008*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1008*FLEN/8, x9, x1, x4) + +inst_361: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x15c and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2d9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x391c; op2val:0xb55c; +op3val:0x32d9; valaddr_reg:x5; val_offset:1011*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 1011*FLEN/8, x9, x1, x4) + +inst_362: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x15c and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2d9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x391c; op2val:0xb55c; +op3val:0x32d9; valaddr_reg:x5; val_offset:1014*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 1014*FLEN/8, x9, x1, x4) + +inst_363: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x15c and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2d9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x391c; op2val:0xb55c; +op3val:0x32d9; valaddr_reg:x5; val_offset:1017*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1017*FLEN/8, x9, x1, x4) + +inst_364: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x15c and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2d9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x391c; op2val:0xb55c; +op3val:0x32d9; valaddr_reg:x5; val_offset:1020*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1020*FLEN/8, x9, x1, x4) + +inst_365: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x334 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x16c and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0e3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3334; op2val:0xbd6c; +op3val:0x34e3; valaddr_reg:x5; val_offset:1023*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1023*FLEN/8, x9, x1, x4) + +inst_366: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x334 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x16c and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0e3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3334; op2val:0xbd6c; +op3val:0x34e3; valaddr_reg:x5; val_offset:1026*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 1026*FLEN/8, x9, x1, x4) + +inst_367: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x334 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x16c and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0e3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3334; op2val:0xbd6c; +op3val:0x34e3; valaddr_reg:x5; val_offset:1029*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 1029*FLEN/8, x9, x1, x4) + +inst_368: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x334 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x16c and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0e3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3334; op2val:0xbd6c; +op3val:0x34e3; valaddr_reg:x5; val_offset:1032*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1032*FLEN/8, x9, x1, x4) + +inst_369: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x334 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x16c and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0e3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3334; op2val:0xbd6c; +op3val:0x34e3; valaddr_reg:x5; val_offset:1035*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1035*FLEN/8, x9, x1, x4) + +inst_370: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x160 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1b8 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3b1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3560; op2val:0xb9b8; +op3val:0x33b1; valaddr_reg:x5; val_offset:1038*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1038*FLEN/8, x9, x1, x4) + +inst_371: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x160 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1b8 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3b1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3560; op2val:0xb9b8; +op3val:0x33b1; valaddr_reg:x5; val_offset:1041*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 1041*FLEN/8, x9, x1, x4) + +inst_372: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x160 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1b8 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3b1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3560; op2val:0xb9b8; +op3val:0x33b1; valaddr_reg:x5; val_offset:1044*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 1044*FLEN/8, x9, x1, x4) + +inst_373: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x160 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1b8 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3b1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3560; op2val:0xb9b8; +op3val:0x33b1; valaddr_reg:x5; val_offset:1047*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1047*FLEN/8, x9, x1, x4) + +inst_374: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x160 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1b8 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3b1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3560; op2val:0xb9b8; +op3val:0x33b1; valaddr_reg:x5; val_offset:1050*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1050*FLEN/8, x9, x1, x4) + +inst_375: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x117 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x36d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0ba and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3917; op2val:0xb76d; +op3val:0x34ba; valaddr_reg:x5; val_offset:1053*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1053*FLEN/8, x9, x1, x4) + +inst_376: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x117 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x36d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0ba and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3917; op2val:0xb76d; +op3val:0x34ba; valaddr_reg:x5; val_offset:1056*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 1056*FLEN/8, x9, x1, x4) + +inst_377: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x117 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x36d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0ba and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3917; op2val:0xb76d; +op3val:0x34ba; valaddr_reg:x5; val_offset:1059*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 1059*FLEN/8, x9, x1, x4) + +inst_378: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x117 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x36d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0ba and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3917; op2val:0xb76d; +op3val:0x34ba; valaddr_reg:x5; val_offset:1062*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1062*FLEN/8, x9, x1, x4) + +inst_379: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x117 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x36d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0ba and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3917; op2val:0xb76d; +op3val:0x34ba; valaddr_reg:x5; val_offset:1065*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1065*FLEN/8, x9, x1, x4) + +inst_380: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1c0 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1b8 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x01d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39c0; op2val:0xb9b8; +op3val:0x381d; valaddr_reg:x5; val_offset:1068*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1068*FLEN/8, x9, x1, x4) + +inst_381: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1c0 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1b8 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x01d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39c0; op2val:0xb9b8; +op3val:0x381d; valaddr_reg:x5; val_offset:1071*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 1071*FLEN/8, x9, x1, x4) + +inst_382: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1c0 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1b8 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x01d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39c0; op2val:0xb9b8; +op3val:0x381d; valaddr_reg:x5; val_offset:1074*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 1074*FLEN/8, x9, x1, x4) + +inst_383: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1c0 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1b8 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x01d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39c0; op2val:0xb9b8; +op3val:0x381d; valaddr_reg:x5; val_offset:1077*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1077*FLEN/8, x9, x1, x4) + +inst_384: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1c0 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1b8 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x01d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39c0; op2val:0xb9b8; +op3val:0x381d; valaddr_reg:x5; val_offset:1080*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1080*FLEN/8, x9, x1, x4) + +inst_385: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x35e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x15e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0f2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x335e; op2val:0xbd5e; +op3val:0x34f2; valaddr_reg:x5; val_offset:1083*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1083*FLEN/8, x9, x1, x4) + +inst_386: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x35e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x15e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0f2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x335e; op2val:0xbd5e; +op3val:0x34f2; valaddr_reg:x5; val_offset:1086*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 1086*FLEN/8, x9, x1, x4) + +inst_387: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x35e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x15e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0f2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x335e; op2val:0xbd5e; +op3val:0x34f2; valaddr_reg:x5; val_offset:1089*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 1089*FLEN/8, x9, x1, x4) + +inst_388: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x35e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x15e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0f2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x335e; op2val:0xbd5e; +op3val:0x34f2; valaddr_reg:x5; val_offset:1092*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1092*FLEN/8, x9, x1, x4) + +inst_389: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x35e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x15e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0f2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x335e; op2val:0xbd5e; +op3val:0x34f2; valaddr_reg:x5; val_offset:1095*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1095*FLEN/8, x9, x1, x4) + +inst_390: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a6 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x0ef and fs3 == 0 and fe3 == 0x0a and fm3 == 0x2fa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39a6; op2val:0xacef; +op3val:0x2afa; valaddr_reg:x5; val_offset:1098*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1098*FLEN/8, x9, x1, x4) + +inst_391: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a6 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x0ef and fs3 == 0 and fe3 == 0x0a and fm3 == 0x2fa and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39a6; op2val:0xacef; +op3val:0x2afa; valaddr_reg:x5; val_offset:1101*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 1101*FLEN/8, x9, x1, x4) + +inst_392: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a6 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x0ef and fs3 == 0 and fe3 == 0x0a and fm3 == 0x2fa and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39a6; op2val:0xacef; +op3val:0x2afa; valaddr_reg:x5; val_offset:1104*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 1104*FLEN/8, x9, x1, x4) + +inst_393: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a6 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x0ef and fs3 == 0 and fe3 == 0x0a and fm3 == 0x2fa and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39a6; op2val:0xacef; +op3val:0x2afa; valaddr_reg:x5; val_offset:1107*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1107*FLEN/8, x9, x1, x4) + +inst_394: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a6 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x0ef and fs3 == 0 and fe3 == 0x0a and fm3 == 0x2fa and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39a6; op2val:0xacef; +op3val:0x2afa; valaddr_reg:x5; val_offset:1110*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1110*FLEN/8, x9, x1, x4) + +inst_395: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x19b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0c9 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x359b; op2val:0xbcc9; +op3val:0x36b5; valaddr_reg:x5; val_offset:1113*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1113*FLEN/8, x9, x1, x4) + +inst_396: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x19b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0c9 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x359b; op2val:0xbcc9; +op3val:0x36b5; valaddr_reg:x5; val_offset:1116*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 1116*FLEN/8, x9, x1, x4) + +inst_397: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x19b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0c9 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x359b; op2val:0xbcc9; +op3val:0x36b5; valaddr_reg:x5; val_offset:1119*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 1119*FLEN/8, x9, x1, x4) + +inst_398: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x19b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0c9 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x359b; op2val:0xbcc9; +op3val:0x36b5; valaddr_reg:x5; val_offset:1122*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1122*FLEN/8, x9, x1, x4) + +inst_399: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x19b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0c9 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x359b; op2val:0xbcc9; +op3val:0x36b5; valaddr_reg:x5; val_offset:1125*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1125*FLEN/8, x9, x1, x4) + +inst_400: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e8 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x355 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x33f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3be8; op2val:0xb755; +op3val:0x373f; valaddr_reg:x5; val_offset:1128*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1128*FLEN/8, x9, x1, x4) + +inst_401: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e8 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x355 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x33f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3be8; op2val:0xb755; +op3val:0x373f; valaddr_reg:x5; val_offset:1131*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 1131*FLEN/8, x9, x1, x4) + +inst_402: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e8 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x355 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x33f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3be8; op2val:0xb755; +op3val:0x373f; valaddr_reg:x5; val_offset:1134*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 1134*FLEN/8, x9, x1, x4) + +inst_403: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e8 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x355 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x33f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3be8; op2val:0xb755; +op3val:0x373f; valaddr_reg:x5; val_offset:1137*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1137*FLEN/8, x9, x1, x4) + +inst_404: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e8 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x355 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x33f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3be8; op2val:0xb755; +op3val:0x373f; valaddr_reg:x5; val_offset:1140*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1140*FLEN/8, x9, x1, x4) + +inst_405: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fe and fs2 == 1 and fe2 == 0x0d and fm2 == 0x302 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x141 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39fe; op2val:0xb702; +op3val:0x3541; valaddr_reg:x5; val_offset:1143*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1143*FLEN/8, x9, x1, x4) + +inst_406: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fe and fs2 == 1 and fe2 == 0x0d and fm2 == 0x302 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x141 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39fe; op2val:0xb702; +op3val:0x3541; valaddr_reg:x5; val_offset:1146*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 1146*FLEN/8, x9, x1, x4) + +inst_407: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fe and fs2 == 1 and fe2 == 0x0d and fm2 == 0x302 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x141 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39fe; op2val:0xb702; +op3val:0x3541; valaddr_reg:x5; val_offset:1149*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 1149*FLEN/8, x9, x1, x4) + +inst_408: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fe and fs2 == 1 and fe2 == 0x0d and fm2 == 0x302 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x141 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39fe; op2val:0xb702; +op3val:0x3541; valaddr_reg:x5; val_offset:1152*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1152*FLEN/8, x9, x1, x4) + +inst_409: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fe and fs2 == 1 and fe2 == 0x0d and fm2 == 0x302 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x141 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39fe; op2val:0xb702; +op3val:0x3541; valaddr_reg:x5; val_offset:1155*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1155*FLEN/8, x9, x1, x4) + +inst_410: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x04b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x175 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1de and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x384b; op2val:0xb575; +op3val:0x31de; valaddr_reg:x5; val_offset:1158*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1158*FLEN/8, x9, x1, x4) + +inst_411: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x04b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x175 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1de and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x384b; op2val:0xb575; +op3val:0x31de; valaddr_reg:x5; val_offset:1161*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 1161*FLEN/8, x9, x1, x4) + +inst_412: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x04b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x175 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1de and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x384b; op2val:0xb575; +op3val:0x31de; valaddr_reg:x5; val_offset:1164*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 1164*FLEN/8, x9, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_4) + +inst_413: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x04b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x175 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1de and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x384b; op2val:0xb575; +op3val:0x31de; valaddr_reg:x5; val_offset:1167*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1167*FLEN/8, x9, x1, x4) + +inst_414: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x04b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x175 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1de and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x384b; op2val:0xb575; +op3val:0x31de; valaddr_reg:x5; val_offset:1170*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1170*FLEN/8, x9, x1, x4) + +inst_415: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x097 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x27a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35a4; op2val:0xb897; +op3val:0x327a; valaddr_reg:x5; val_offset:1173*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1173*FLEN/8, x9, x1, x4) + +inst_416: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x097 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x27a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35a4; op2val:0xb897; +op3val:0x327a; valaddr_reg:x5; val_offset:1176*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 1176*FLEN/8, x9, x1, x4) + +inst_417: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x097 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x27a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35a4; op2val:0xb897; +op3val:0x327a; valaddr_reg:x5; val_offset:1179*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 1179*FLEN/8, x9, x1, x4) + +inst_418: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x097 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x27a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35a4; op2val:0xb897; +op3val:0x327a; valaddr_reg:x5; val_offset:1182*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1182*FLEN/8, x9, x1, x4) + +inst_419: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x097 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x27a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35a4; op2val:0xb897; +op3val:0x327a; valaddr_reg:x5; val_offset:1185*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1185*FLEN/8, x9, x1, x4) + +inst_420: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x137 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x05d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1b2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3937; op2val:0xb85d; +op3val:0x35b2; valaddr_reg:x5; val_offset:1188*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1188*FLEN/8, x9, x1, x4) + +inst_421: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x137 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x05d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1b2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3937; op2val:0xb85d; +op3val:0x35b2; valaddr_reg:x5; val_offset:1191*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 1191*FLEN/8, x9, x1, x4) + +inst_422: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x137 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x05d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1b2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3937; op2val:0xb85d; +op3val:0x35b2; valaddr_reg:x5; val_offset:1194*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 1194*FLEN/8, x9, x1, x4) + +inst_423: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x137 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x05d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1b2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3937; op2val:0xb85d; +op3val:0x35b2; valaddr_reg:x5; val_offset:1197*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1197*FLEN/8, x9, x1, x4) + +inst_424: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x137 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x05d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1b2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3937; op2val:0xb85d; +op3val:0x35b2; valaddr_reg:x5; val_offset:1200*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1200*FLEN/8, x9, x1, x4) + +inst_425: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x031 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x13d and fs3 == 0 and fe3 == 0x0c and fm3 == 0x17f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3431; op2val:0xb93d; +op3val:0x317f; valaddr_reg:x5; val_offset:1203*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1203*FLEN/8, x9, x1, x4) + +inst_426: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x031 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x13d and fs3 == 0 and fe3 == 0x0c and fm3 == 0x17f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3431; op2val:0xb93d; +op3val:0x317f; valaddr_reg:x5; val_offset:1206*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 1206*FLEN/8, x9, x1, x4) + +inst_427: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x031 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x13d and fs3 == 0 and fe3 == 0x0c and fm3 == 0x17f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3431; op2val:0xb93d; +op3val:0x317f; valaddr_reg:x5; val_offset:1209*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 1209*FLEN/8, x9, x1, x4) + +inst_428: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x031 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x13d and fs3 == 0 and fe3 == 0x0c and fm3 == 0x17f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3431; op2val:0xb93d; +op3val:0x317f; valaddr_reg:x5; val_offset:1212*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1212*FLEN/8, x9, x1, x4) + +inst_429: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x031 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x13d and fs3 == 0 and fe3 == 0x0c and fm3 == 0x17f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3431; op2val:0xb93d; +op3val:0x317f; valaddr_reg:x5; val_offset:1215*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1215*FLEN/8, x9, x1, x4) + +inst_430: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x133 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3bc and fs3 == 0 and fe3 == 0x0c and fm3 == 0x107 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3933; op2val:0xb3bc; +op3val:0x3107; valaddr_reg:x5; val_offset:1218*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1218*FLEN/8, x9, x1, x4) + +inst_431: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x133 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3bc and fs3 == 0 and fe3 == 0x0c and fm3 == 0x107 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3933; op2val:0xb3bc; +op3val:0x3107; valaddr_reg:x5; val_offset:1221*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 1221*FLEN/8, x9, x1, x4) + +inst_432: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x133 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3bc and fs3 == 0 and fe3 == 0x0c and fm3 == 0x107 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3933; op2val:0xb3bc; +op3val:0x3107; valaddr_reg:x5; val_offset:1224*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 1224*FLEN/8, x9, x1, x4) + +inst_433: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x133 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3bc and fs3 == 0 and fe3 == 0x0c and fm3 == 0x107 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3933; op2val:0xb3bc; +op3val:0x3107; valaddr_reg:x5; val_offset:1227*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1227*FLEN/8, x9, x1, x4) + +inst_434: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x133 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3bc and fs3 == 0 and fe3 == 0x0c and fm3 == 0x107 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3933; op2val:0xb3bc; +op3val:0x3107; valaddr_reg:x5; val_offset:1230*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1230*FLEN/8, x9, x1, x4) + +inst_435: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x029 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ca and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3029; op2val:0xc0ca; +op3val:0x34fc; valaddr_reg:x5; val_offset:1233*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1233*FLEN/8, x9, x1, x4) + +inst_436: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x029 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ca and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0fc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3029; op2val:0xc0ca; +op3val:0x34fc; valaddr_reg:x5; val_offset:1236*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 1236*FLEN/8, x9, x1, x4) + +inst_437: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x029 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ca and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0fc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3029; op2val:0xc0ca; +op3val:0x34fc; valaddr_reg:x5; val_offset:1239*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 1239*FLEN/8, x9, x1, x4) + +inst_438: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x029 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ca and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0fc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3029; op2val:0xc0ca; +op3val:0x34fc; valaddr_reg:x5; val_offset:1242*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1242*FLEN/8, x9, x1, x4) + +inst_439: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x029 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ca and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0fc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3029; op2val:0xc0ca; +op3val:0x34fc; valaddr_reg:x5; val_offset:1245*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1245*FLEN/8, x9, x1, x4) + +inst_440: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x21f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x345 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x192 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x261f; op2val:0xbf45; +op3val:0x2992; valaddr_reg:x5; val_offset:1248*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1248*FLEN/8, x9, x1, x4) + +inst_441: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x21f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x345 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x192 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x261f; op2val:0xbf45; +op3val:0x2992; valaddr_reg:x5; val_offset:1251*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 1251*FLEN/8, x9, x1, x4) + +inst_442: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x21f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x345 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x192 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x261f; op2val:0xbf45; +op3val:0x2992; valaddr_reg:x5; val_offset:1254*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 1254*FLEN/8, x9, x1, x4) + +inst_443: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x21f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x345 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x192 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x261f; op2val:0xbf45; +op3val:0x2992; valaddr_reg:x5; val_offset:1257*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1257*FLEN/8, x9, x1, x4) + +inst_444: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x21f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x345 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x192 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x261f; op2val:0xbf45; +op3val:0x2992; valaddr_reg:x5; val_offset:1260*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1260*FLEN/8, x9, x1, x4) + +inst_445: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3b5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3d0 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x387 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37b5; op2val:0xbbd0; +op3val:0x3787; valaddr_reg:x5; val_offset:1263*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1263*FLEN/8, x9, x1, x4) + +inst_446: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3b5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3d0 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x387 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37b5; op2val:0xbbd0; +op3val:0x3787; valaddr_reg:x5; val_offset:1266*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 1266*FLEN/8, x9, x1, x4) + +inst_447: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3b5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3d0 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x387 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37b5; op2val:0xbbd0; +op3val:0x3787; valaddr_reg:x5; val_offset:1269*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 1269*FLEN/8, x9, x1, x4) + +inst_448: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3b5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3d0 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x387 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37b5; op2val:0xbbd0; +op3val:0x3787; valaddr_reg:x5; val_offset:1272*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1272*FLEN/8, x9, x1, x4) + +inst_449: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3b5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3d0 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x387 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37b5; op2val:0xbbd0; +op3val:0x3787; valaddr_reg:x5; val_offset:1275*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1275*FLEN/8, x9, x1, x4) + +inst_450: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ab and fs2 == 1 and fe2 == 0x0c and fm2 == 0x245 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x13a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aab; op2val:0xb245; +op3val:0x313a; valaddr_reg:x5; val_offset:1278*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1278*FLEN/8, x9, x1, x4) + +inst_451: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ab and fs2 == 1 and fe2 == 0x0c and fm2 == 0x245 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x13a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aab; op2val:0xb245; +op3val:0x313a; valaddr_reg:x5; val_offset:1281*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 1281*FLEN/8, x9, x1, x4) + +inst_452: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ab and fs2 == 1 and fe2 == 0x0c and fm2 == 0x245 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x13a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aab; op2val:0xb245; +op3val:0x313a; valaddr_reg:x5; val_offset:1284*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 1284*FLEN/8, x9, x1, x4) + +inst_453: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ab and fs2 == 1 and fe2 == 0x0c and fm2 == 0x245 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x13a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aab; op2val:0xb245; +op3val:0x313a; valaddr_reg:x5; val_offset:1287*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1287*FLEN/8, x9, x1, x4) + +inst_454: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ab and fs2 == 1 and fe2 == 0x0c and fm2 == 0x245 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x13a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aab; op2val:0xb245; +op3val:0x313a; valaddr_reg:x5; val_offset:1290*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1290*FLEN/8, x9, x1, x4) + +inst_455: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x002 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x02b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x02e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2c02; op2val:0xc82b; +op3val:0x382e; valaddr_reg:x5; val_offset:1293*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1293*FLEN/8, x9, x1, x4) + +inst_456: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x002 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x02b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x02e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2c02; op2val:0xc82b; +op3val:0x382e; valaddr_reg:x5; val_offset:1296*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 1296*FLEN/8, x9, x1, x4) + +inst_457: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x002 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x02b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x02e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2c02; op2val:0xc82b; +op3val:0x382e; valaddr_reg:x5; val_offset:1299*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 1299*FLEN/8, x9, x1, x4) + +inst_458: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x002 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x02b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x02e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2c02; op2val:0xc82b; +op3val:0x382e; valaddr_reg:x5; val_offset:1302*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1302*FLEN/8, x9, x1, x4) + +inst_459: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x002 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x02b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x02e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2c02; op2val:0xc82b; +op3val:0x382e; valaddr_reg:x5; val_offset:1305*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1305*FLEN/8, x9, x1, x4) + +inst_460: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x344 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x07c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34f0; op2val:0xbb44; +op3val:0x347c; valaddr_reg:x5; val_offset:1308*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1308*FLEN/8, x9, x1, x4) + +inst_461: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x344 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x07c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34f0; op2val:0xbb44; +op3val:0x347c; valaddr_reg:x5; val_offset:1311*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 1311*FLEN/8, x9, x1, x4) + +inst_462: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x344 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x07c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34f0; op2val:0xbb44; +op3val:0x347c; valaddr_reg:x5; val_offset:1314*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 1314*FLEN/8, x9, x1, x4) + +inst_463: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x344 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x07c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34f0; op2val:0xbb44; +op3val:0x347c; valaddr_reg:x5; val_offset:1317*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1317*FLEN/8, x9, x1, x4) + +inst_464: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x344 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x07c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34f0; op2val:0xbb44; +op3val:0x347c; valaddr_reg:x5; val_offset:1320*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1320*FLEN/8, x9, x1, x4) + +inst_465: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x050 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x224 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2a0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3450; op2val:0xc224; +op3val:0x3aa0; valaddr_reg:x5; val_offset:1323*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1323*FLEN/8, x9, x1, x4) + +inst_466: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x050 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x224 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2a0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3450; op2val:0xc224; +op3val:0x3aa0; valaddr_reg:x5; val_offset:1326*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 1326*FLEN/8, x9, x1, x4) + +inst_467: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x050 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x224 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2a0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3450; op2val:0xc224; +op3val:0x3aa0; valaddr_reg:x5; val_offset:1329*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 1329*FLEN/8, x9, x1, x4) + +inst_468: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x050 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x224 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2a0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3450; op2val:0xc224; +op3val:0x3aa0; valaddr_reg:x5; val_offset:1332*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1332*FLEN/8, x9, x1, x4) + +inst_469: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x050 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x224 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2a0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3450; op2val:0xc224; +op3val:0x3aa0; valaddr_reg:x5; val_offset:1335*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1335*FLEN/8, x9, x1, x4) + +inst_470: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x307 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3a1 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3307; op2val:0xbfa1; +op3val:0x36b4; valaddr_reg:x5; val_offset:1338*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1338*FLEN/8, x9, x1, x4) + +inst_471: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x307 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3a1 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3307; op2val:0xbfa1; +op3val:0x36b4; valaddr_reg:x5; val_offset:1341*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 1341*FLEN/8, x9, x1, x4) + +inst_472: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x307 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3a1 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3307; op2val:0xbfa1; +op3val:0x36b4; valaddr_reg:x5; val_offset:1344*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 1344*FLEN/8, x9, x1, x4) + +inst_473: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x307 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3a1 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3307; op2val:0xbfa1; +op3val:0x36b4; valaddr_reg:x5; val_offset:1347*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1347*FLEN/8, x9, x1, x4) + +inst_474: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x307 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3a1 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3307; op2val:0xbfa1; +op3val:0x36b4; valaddr_reg:x5; val_offset:1350*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1350*FLEN/8, x9, x1, x4) + +inst_475: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x159 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2ed and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0a2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3559; op2val:0xbeed; +op3val:0x38a2; valaddr_reg:x5; val_offset:1353*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1353*FLEN/8, x9, x1, x4) + +inst_476: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x159 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2ed and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0a2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3559; op2val:0xbeed; +op3val:0x38a2; valaddr_reg:x5; val_offset:1356*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 1356*FLEN/8, x9, x1, x4) + +inst_477: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x159 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2ed and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0a2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3559; op2val:0xbeed; +op3val:0x38a2; valaddr_reg:x5; val_offset:1359*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 1359*FLEN/8, x9, x1, x4) + +inst_478: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x159 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2ed and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0a2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3559; op2val:0xbeed; +op3val:0x38a2; valaddr_reg:x5; val_offset:1362*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1362*FLEN/8, x9, x1, x4) + +inst_479: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x159 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2ed and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0a2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3559; op2val:0xbeed; +op3val:0x38a2; valaddr_reg:x5; val_offset:1365*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1365*FLEN/8, x9, x1, x4) + +inst_480: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x205 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0ca and fs3 == 0 and fe3 == 0x0c and fm3 == 0x335 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3605; op2val:0xb8ca; +op3val:0x3335; valaddr_reg:x5; val_offset:1368*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1368*FLEN/8, x9, x1, x4) + +inst_481: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x205 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0ca and fs3 == 0 and fe3 == 0x0c and fm3 == 0x335 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3605; op2val:0xb8ca; +op3val:0x3335; valaddr_reg:x5; val_offset:1371*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 1371*FLEN/8, x9, x1, x4) + +inst_482: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x205 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0ca and fs3 == 0 and fe3 == 0x0c and fm3 == 0x335 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3605; op2val:0xb8ca; +op3val:0x3335; valaddr_reg:x5; val_offset:1374*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 1374*FLEN/8, x9, x1, x4) + +inst_483: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x205 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0ca and fs3 == 0 and fe3 == 0x0c and fm3 == 0x335 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3605; op2val:0xb8ca; +op3val:0x3335; valaddr_reg:x5; val_offset:1377*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1377*FLEN/8, x9, x1, x4) + +inst_484: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x205 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0ca and fs3 == 0 and fe3 == 0x0c and fm3 == 0x335 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3605; op2val:0xb8ca; +op3val:0x3335; valaddr_reg:x5; val_offset:1380*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1380*FLEN/8, x9, x1, x4) + +inst_485: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1cf and fs2 == 1 and fe2 == 0x0e and fm2 == 0x228 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x079 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35cf; op2val:0xba28; +op3val:0x3479; valaddr_reg:x5; val_offset:1383*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1383*FLEN/8, x9, x1, x4) + +inst_486: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1cf and fs2 == 1 and fe2 == 0x0e and fm2 == 0x228 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x079 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35cf; op2val:0xba28; +op3val:0x3479; valaddr_reg:x5; val_offset:1386*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 1386*FLEN/8, x9, x1, x4) + +inst_487: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1cf and fs2 == 1 and fe2 == 0x0e and fm2 == 0x228 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x079 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35cf; op2val:0xba28; +op3val:0x3479; valaddr_reg:x5; val_offset:1389*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 1389*FLEN/8, x9, x1, x4) + +inst_488: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1cf and fs2 == 1 and fe2 == 0x0e and fm2 == 0x228 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x079 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35cf; op2val:0xba28; +op3val:0x3479; valaddr_reg:x5; val_offset:1392*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1392*FLEN/8, x9, x1, x4) + +inst_489: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1cf and fs2 == 1 and fe2 == 0x0e and fm2 == 0x228 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x079 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35cf; op2val:0xba28; +op3val:0x3479; valaddr_reg:x5; val_offset:1395*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1395*FLEN/8, x9, x1, x4) + +inst_490: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2e9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bc7; op2val:0xbae9; +op3val:0x3ab8; valaddr_reg:x5; val_offset:1398*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1398*FLEN/8, x9, x1, x4) + +inst_491: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2e9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bc7; op2val:0xbae9; +op3val:0x3ab8; valaddr_reg:x5; val_offset:1401*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 1401*FLEN/8, x9, x1, x4) + +inst_492: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2e9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bc7; op2val:0xbae9; +op3val:0x3ab8; valaddr_reg:x5; val_offset:1404*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 1404*FLEN/8, x9, x1, x4) + +inst_493: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2e9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bc7; op2val:0xbae9; +op3val:0x3ab8; valaddr_reg:x5; val_offset:1407*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1407*FLEN/8, x9, x1, x4) + +inst_494: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2e9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bc7; op2val:0xbae9; +op3val:0x3ab8; valaddr_reg:x5; val_offset:1410*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1410*FLEN/8, x9, x1, x4) + +inst_495: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x078 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x101 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x199 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3878; op2val:0xb901; +op3val:0x3599; valaddr_reg:x5; val_offset:1413*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1413*FLEN/8, x9, x1, x4) + +inst_496: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x078 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x101 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x199 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3878; op2val:0xb901; +op3val:0x3599; valaddr_reg:x5; val_offset:1416*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 1416*FLEN/8, x9, x1, x4) + +inst_497: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x078 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x101 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x199 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3878; op2val:0xb901; +op3val:0x3599; valaddr_reg:x5; val_offset:1419*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 1419*FLEN/8, x9, x1, x4) + +inst_498: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x078 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x101 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x199 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3878; op2val:0xb901; +op3val:0x3599; valaddr_reg:x5; val_offset:1422*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1422*FLEN/8, x9, x1, x4) + +inst_499: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x078 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x101 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x199 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3878; op2val:0xb901; +op3val:0x3599; valaddr_reg:x5; val_offset:1425*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1425*FLEN/8, x9, x1, x4) + +inst_500: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x26f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x106 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a3f; op2val:0xb66f; +op3val:0x3506; valaddr_reg:x5; val_offset:1428*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1428*FLEN/8, x9, x1, x4) + +inst_501: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x26f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x106 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a3f; op2val:0xb66f; +op3val:0x3506; valaddr_reg:x5; val_offset:1431*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 1431*FLEN/8, x9, x1, x4) + +inst_502: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x26f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x106 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a3f; op2val:0xb66f; +op3val:0x3506; valaddr_reg:x5; val_offset:1434*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 1434*FLEN/8, x9, x1, x4) + +inst_503: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x26f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x106 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a3f; op2val:0xb66f; +op3val:0x3506; valaddr_reg:x5; val_offset:1437*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1437*FLEN/8, x9, x1, x4) + +inst_504: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x26f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x106 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a3f; op2val:0xb66f; +op3val:0x3506; valaddr_reg:x5; val_offset:1440*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1440*FLEN/8, x9, x1, x4) + +inst_505: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1e8 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x130 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35e8; op2val:0xc130; +op3val:0x3baa; valaddr_reg:x5; val_offset:1443*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1443*FLEN/8, x9, x1, x4) + +inst_506: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1e8 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x130 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3aa and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35e8; op2val:0xc130; +op3val:0x3baa; valaddr_reg:x5; val_offset:1446*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 1446*FLEN/8, x9, x1, x4) + +inst_507: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1e8 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x130 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3aa and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35e8; op2val:0xc130; +op3val:0x3baa; valaddr_reg:x5; val_offset:1449*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 1449*FLEN/8, x9, x1, x4) + +inst_508: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1e8 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x130 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3aa and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35e8; op2val:0xc130; +op3val:0x3baa; valaddr_reg:x5; val_offset:1452*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1452*FLEN/8, x9, x1, x4) + +inst_509: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1e8 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x130 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3aa and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35e8; op2val:0xc130; +op3val:0x3baa; valaddr_reg:x5; val_offset:1455*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1455*FLEN/8, x9, x1, x4) + +inst_510: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x03a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1db and fs3 == 0 and fe3 == 0x0e and fm3 == 0x230 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x383a; op2val:0xbddb; +op3val:0x3a30; valaddr_reg:x5; val_offset:1458*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1458*FLEN/8, x9, x1, x4) + +inst_511: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x03a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1db and fs3 == 0 and fe3 == 0x0e and fm3 == 0x230 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x383a; op2val:0xbddb; +op3val:0x3a30; valaddr_reg:x5; val_offset:1461*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 1461*FLEN/8, x9, x1, x4) + +inst_512: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x03a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1db and fs3 == 0 and fe3 == 0x0e and fm3 == 0x230 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x383a; op2val:0xbddb; +op3val:0x3a30; valaddr_reg:x5; val_offset:1464*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 1464*FLEN/8, x9, x1, x4) + +inst_513: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x03a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1db and fs3 == 0 and fe3 == 0x0e and fm3 == 0x230 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x383a; op2val:0xbddb; +op3val:0x3a30; valaddr_reg:x5; val_offset:1467*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1467*FLEN/8, x9, x1, x4) + +inst_514: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x03a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1db and fs3 == 0 and fe3 == 0x0e and fm3 == 0x230 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x383a; op2val:0xbddb; +op3val:0x3a30; valaddr_reg:x5; val_offset:1470*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1470*FLEN/8, x9, x1, x4) + +inst_515: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x391 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x354 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ee and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b91; op2val:0xbb54; +op3val:0x3aee; valaddr_reg:x5; val_offset:1473*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1473*FLEN/8, x9, x1, x4) + +inst_516: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x391 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x354 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ee and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b91; op2val:0xbb54; +op3val:0x3aee; valaddr_reg:x5; val_offset:1476*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 1476*FLEN/8, x9, x1, x4) + +inst_517: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x391 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x354 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ee and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b91; op2val:0xbb54; +op3val:0x3aee; valaddr_reg:x5; val_offset:1479*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 1479*FLEN/8, x9, x1, x4) + +inst_518: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x391 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x354 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ee and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b91; op2val:0xbb54; +op3val:0x3aee; valaddr_reg:x5; val_offset:1482*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1482*FLEN/8, x9, x1, x4) + +inst_519: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x391 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x354 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ee and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b91; op2val:0xbb54; +op3val:0x3aee; valaddr_reg:x5; val_offset:1485*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1485*FLEN/8, x9, x1, x4) + +inst_520: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x176 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0cb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x28c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3976; op2val:0xbccb; +op3val:0x3a8c; valaddr_reg:x5; val_offset:1488*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1488*FLEN/8, x9, x1, x4) + +inst_521: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x176 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0cb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x28c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3976; op2val:0xbccb; +op3val:0x3a8c; valaddr_reg:x5; val_offset:1491*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 1491*FLEN/8, x9, x1, x4) + +inst_522: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x176 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0cb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x28c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3976; op2val:0xbccb; +op3val:0x3a8c; valaddr_reg:x5; val_offset:1494*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 1494*FLEN/8, x9, x1, x4) + +inst_523: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x176 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0cb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x28c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3976; op2val:0xbccb; +op3val:0x3a8c; valaddr_reg:x5; val_offset:1497*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1497*FLEN/8, x9, x1, x4) + +inst_524: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x176 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0cb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x28c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3976; op2val:0xbccb; +op3val:0x3a8c; valaddr_reg:x5; val_offset:1500*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1500*FLEN/8, x9, x1, x4) + +inst_525: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x274 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0c8 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3b6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a74; op2val:0xbcc8; +op3val:0x3bb6; valaddr_reg:x5; val_offset:1503*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1503*FLEN/8, x9, x1, x4) + +inst_526: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x274 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0c8 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3b6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a74; op2val:0xbcc8; +op3val:0x3bb6; valaddr_reg:x5; val_offset:1506*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 1506*FLEN/8, x9, x1, x4) + +inst_527: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x274 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0c8 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3b6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a74; op2val:0xbcc8; +op3val:0x3bb6; valaddr_reg:x5; val_offset:1509*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 1509*FLEN/8, x9, x1, x4) + +inst_528: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x274 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0c8 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3b6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a74; op2val:0xbcc8; +op3val:0x3bb6; valaddr_reg:x5; val_offset:1512*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1512*FLEN/8, x9, x1, x4) + +inst_529: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x274 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0c8 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3b6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a74; op2val:0xbcc8; +op3val:0x3bb6; valaddr_reg:x5; val_offset:1515*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1515*FLEN/8, x9, x1, x4) + +inst_530: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x047 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0a2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0f5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3847; op2val:0xbca2; +op3val:0x38f5; valaddr_reg:x5; val_offset:1518*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1518*FLEN/8, x9, x1, x4) + +inst_531: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x047 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0a2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0f5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3847; op2val:0xbca2; +op3val:0x38f5; valaddr_reg:x5; val_offset:1521*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 1521*FLEN/8, x9, x1, x4) + +inst_532: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x047 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0a2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0f5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3847; op2val:0xbca2; +op3val:0x38f5; valaddr_reg:x5; val_offset:1524*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 1524*FLEN/8, x9, x1, x4) + +inst_533: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x047 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0a2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0f5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3847; op2val:0xbca2; +op3val:0x38f5; valaddr_reg:x5; val_offset:1527*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1527*FLEN/8, x9, x1, x4) + +inst_534: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x047 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0a2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0f5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3847; op2val:0xbca2; +op3val:0x38f5; valaddr_reg:x5; val_offset:1530*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1530*FLEN/8, x9, x1, x4) + +inst_535: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x236 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x038 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x28e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3636; op2val:0xbc38; +op3val:0x368e; valaddr_reg:x5; val_offset:1533*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1533*FLEN/8, x9, x1, x4) + +inst_536: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x236 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x038 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x28e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3636; op2val:0xbc38; +op3val:0x368e; valaddr_reg:x5; val_offset:1536*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 1536*FLEN/8, x9, x1, x4) + +inst_537: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x236 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x038 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x28e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3636; op2val:0xbc38; +op3val:0x368e; valaddr_reg:x5; val_offset:1539*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 1539*FLEN/8, x9, x1, x4) + +inst_538: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x236 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x038 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x28e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3636; op2val:0xbc38; +op3val:0x368e; valaddr_reg:x5; val_offset:1542*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1542*FLEN/8, x9, x1, x4) + +inst_539: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x236 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x038 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x28e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3636; op2val:0xbc38; +op3val:0x368e; valaddr_reg:x5; val_offset:1545*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1545*FLEN/8, x9, x1, x4) + +inst_540: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x218 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x010 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x232 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a18; op2val:0xb010; +op3val:0x2e32; valaddr_reg:x5; val_offset:1548*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1548*FLEN/8, x9, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_5) + +inst_541: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x218 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x010 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x232 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a18; op2val:0xb010; +op3val:0x2e32; valaddr_reg:x5; val_offset:1551*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 1551*FLEN/8, x9, x1, x4) + +inst_542: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x218 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x010 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x232 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a18; op2val:0xb010; +op3val:0x2e32; valaddr_reg:x5; val_offset:1554*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 1554*FLEN/8, x9, x1, x4) + +inst_543: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x218 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x010 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x232 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a18; op2val:0xb010; +op3val:0x2e32; valaddr_reg:x5; val_offset:1557*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1557*FLEN/8, x9, x1, x4) + +inst_544: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x218 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x010 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x232 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a18; op2val:0xb010; +op3val:0x2e32; valaddr_reg:x5; val_offset:1560*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1560*FLEN/8, x9, x1, x4) + +inst_545: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0c2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0c1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bfe; op2val:0xb8c2; +op3val:0x38c1; valaddr_reg:x5; val_offset:1563*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1563*FLEN/8, x9, x1, x4) + +inst_546: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0c2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0c1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bfe; op2val:0xb8c2; +op3val:0x38c1; valaddr_reg:x5; val_offset:1566*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 1566*FLEN/8, x9, x1, x4) + +inst_547: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0c2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0c1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bfe; op2val:0xb8c2; +op3val:0x38c1; valaddr_reg:x5; val_offset:1569*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 1569*FLEN/8, x9, x1, x4) + +inst_548: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0c2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0c1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bfe; op2val:0xb8c2; +op3val:0x38c1; valaddr_reg:x5; val_offset:1572*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1572*FLEN/8, x9, x1, x4) + +inst_549: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0c2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0c1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bfe; op2val:0xb8c2; +op3val:0x38c1; valaddr_reg:x5; val_offset:1575*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1575*FLEN/8, x9, x1, x4) + +inst_550: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1c5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x28a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0b8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39c5; op2val:0xba8a; +op3val:0x38b8; valaddr_reg:x5; val_offset:1578*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1578*FLEN/8, x9, x1, x4) + +inst_551: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1c5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x28a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0b8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39c5; op2val:0xba8a; +op3val:0x38b8; valaddr_reg:x5; val_offset:1581*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 1581*FLEN/8, x9, x1, x4) + +inst_552: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1c5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x28a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0b8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39c5; op2val:0xba8a; +op3val:0x38b8; valaddr_reg:x5; val_offset:1584*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 1584*FLEN/8, x9, x1, x4) + +inst_553: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1c5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x28a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0b8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39c5; op2val:0xba8a; +op3val:0x38b8; valaddr_reg:x5; val_offset:1587*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1587*FLEN/8, x9, x1, x4) + +inst_554: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1c5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x28a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0b8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39c5; op2val:0xba8a; +op3val:0x38b8; valaddr_reg:x5; val_offset:1590*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1590*FLEN/8, x9, x1, x4) + +inst_555: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x314 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x218 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x165 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b14; op2val:0xb218; +op3val:0x3165; valaddr_reg:x5; val_offset:1593*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1593*FLEN/8, x9, x1, x4) + +inst_556: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x314 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x218 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x165 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b14; op2val:0xb218; +op3val:0x3165; valaddr_reg:x5; val_offset:1596*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 1596*FLEN/8, x9, x1, x4) + +inst_557: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x314 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x218 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x165 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b14; op2val:0xb218; +op3val:0x3165; valaddr_reg:x5; val_offset:1599*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 1599*FLEN/8, x9, x1, x4) + +inst_558: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x314 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x218 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x165 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b14; op2val:0xb218; +op3val:0x3165; valaddr_reg:x5; val_offset:1602*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1602*FLEN/8, x9, x1, x4) + +inst_559: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x314 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x218 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x165 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b14; op2val:0xb218; +op3val:0x3165; valaddr_reg:x5; val_offset:1605*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1605*FLEN/8, x9, x1, x4) + +inst_560: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x102 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x228 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3b6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3902; op2val:0xbe28; +op3val:0x3bb6; valaddr_reg:x5; val_offset:1608*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1608*FLEN/8, x9, x1, x4) + +inst_561: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x102 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x228 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3b6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3902; op2val:0xbe28; +op3val:0x3bb6; valaddr_reg:x5; val_offset:1611*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 1611*FLEN/8, x9, x1, x4) + +inst_562: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x102 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x228 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3b6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3902; op2val:0xbe28; +op3val:0x3bb6; valaddr_reg:x5; val_offset:1614*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 1614*FLEN/8, x9, x1, x4) + +inst_563: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x102 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x228 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3b6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3902; op2val:0xbe28; +op3val:0x3bb6; valaddr_reg:x5; val_offset:1617*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1617*FLEN/8, x9, x1, x4) + +inst_564: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x102 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x228 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3b6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3902; op2val:0xbe28; +op3val:0x3bb6; valaddr_reg:x5; val_offset:1620*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1620*FLEN/8, x9, x1, x4) + +inst_565: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x22e and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0af and fs3 == 0 and fe3 == 0x0e and fm3 == 0x33d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x362e; op2val:0xc0af; +op3val:0x3b3d; valaddr_reg:x5; val_offset:1623*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1623*FLEN/8, x9, x1, x4) + +inst_566: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x22e and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0af and fs3 == 0 and fe3 == 0x0e and fm3 == 0x33d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x362e; op2val:0xc0af; +op3val:0x3b3d; valaddr_reg:x5; val_offset:1626*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 1626*FLEN/8, x9, x1, x4) + +inst_567: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x22e and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0af and fs3 == 0 and fe3 == 0x0e and fm3 == 0x33d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x362e; op2val:0xc0af; +op3val:0x3b3d; valaddr_reg:x5; val_offset:1629*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 1629*FLEN/8, x9, x1, x4) + +inst_568: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x22e and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0af and fs3 == 0 and fe3 == 0x0e and fm3 == 0x33d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x362e; op2val:0xc0af; +op3val:0x3b3d; valaddr_reg:x5; val_offset:1632*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1632*FLEN/8, x9, x1, x4) + +inst_569: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x22e and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0af and fs3 == 0 and fe3 == 0x0e and fm3 == 0x33d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x362e; op2val:0xc0af; +op3val:0x3b3d; valaddr_reg:x5; val_offset:1635*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1635*FLEN/8, x9, x1, x4) + +inst_570: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x346 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1cf and fs3 == 0 and fe3 == 0x0e and fm3 == 0x148 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3746; op2val:0xbdcf; +op3val:0x3948; valaddr_reg:x5; val_offset:1638*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1638*FLEN/8, x9, x1, x4) + +inst_571: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x346 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1cf and fs3 == 0 and fe3 == 0x0e and fm3 == 0x148 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3746; op2val:0xbdcf; +op3val:0x3948; valaddr_reg:x5; val_offset:1641*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 1641*FLEN/8, x9, x1, x4) + +inst_572: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x346 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1cf and fs3 == 0 and fe3 == 0x0e and fm3 == 0x148 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3746; op2val:0xbdcf; +op3val:0x3948; valaddr_reg:x5; val_offset:1644*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 1644*FLEN/8, x9, x1, x4) + +inst_573: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x346 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1cf and fs3 == 0 and fe3 == 0x0e and fm3 == 0x148 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3746; op2val:0xbdcf; +op3val:0x3948; valaddr_reg:x5; val_offset:1647*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1647*FLEN/8, x9, x1, x4) + +inst_574: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x346 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1cf and fs3 == 0 and fe3 == 0x0e and fm3 == 0x148 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3746; op2val:0xbdcf; +op3val:0x3948; valaddr_reg:x5; val_offset:1650*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1650*FLEN/8, x9, x1, x4) + +inst_575: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2b4 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x25d and fs3 == 0 and fe3 == 0x0a and fm3 == 0x157 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36b4; op2val:0xae5d; +op3val:0x2957; valaddr_reg:x5; val_offset:1653*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1653*FLEN/8, x9, x1, x4) + +inst_576: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2b4 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x25d and fs3 == 0 and fe3 == 0x0a and fm3 == 0x157 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36b4; op2val:0xae5d; +op3val:0x2957; valaddr_reg:x5; val_offset:1656*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 1656*FLEN/8, x9, x1, x4) + +inst_577: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2b4 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x25d and fs3 == 0 and fe3 == 0x0a and fm3 == 0x157 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36b4; op2val:0xae5d; +op3val:0x2957; valaddr_reg:x5; val_offset:1659*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 1659*FLEN/8, x9, x1, x4) + +inst_578: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2b4 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x25d and fs3 == 0 and fe3 == 0x0a and fm3 == 0x157 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36b4; op2val:0xae5d; +op3val:0x2957; valaddr_reg:x5; val_offset:1662*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1662*FLEN/8, x9, x1, x4) + +inst_579: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2b4 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x25d and fs3 == 0 and fe3 == 0x0a and fm3 == 0x157 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36b4; op2val:0xae5d; +op3val:0x2957; valaddr_reg:x5; val_offset:1665*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1665*FLEN/8, x9, x1, x4) + +inst_580: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1ce and fs2 == 1 and fe2 == 0x10 and fm2 == 0x266 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0a5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31ce; op2val:0xc266; +op3val:0x38a5; valaddr_reg:x5; val_offset:1668*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1668*FLEN/8, x9, x1, x4) + +inst_581: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1ce and fs2 == 1 and fe2 == 0x10 and fm2 == 0x266 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0a5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31ce; op2val:0xc266; +op3val:0x38a5; valaddr_reg:x5; val_offset:1671*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 1671*FLEN/8, x9, x1, x4) + +inst_582: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1ce and fs2 == 1 and fe2 == 0x10 and fm2 == 0x266 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0a5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31ce; op2val:0xc266; +op3val:0x38a5; valaddr_reg:x5; val_offset:1674*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 1674*FLEN/8, x9, x1, x4) + +inst_583: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1ce and fs2 == 1 and fe2 == 0x10 and fm2 == 0x266 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0a5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31ce; op2val:0xc266; +op3val:0x38a5; valaddr_reg:x5; val_offset:1677*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1677*FLEN/8, x9, x1, x4) + +inst_584: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1ce and fs2 == 1 and fe2 == 0x10 and fm2 == 0x266 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0a5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31ce; op2val:0xc266; +op3val:0x38a5; valaddr_reg:x5; val_offset:1680*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1680*FLEN/8, x9, x1, x4) + +inst_585: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1fc and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3a6 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1b9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31fc; op2val:0xbfa6; +op3val:0x35b9; valaddr_reg:x5; val_offset:1683*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1683*FLEN/8, x9, x1, x4) + +inst_586: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1fc and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3a6 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1b9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31fc; op2val:0xbfa6; +op3val:0x35b9; valaddr_reg:x5; val_offset:1686*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 1686*FLEN/8, x9, x1, x4) + +inst_587: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1fc and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3a6 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1b9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31fc; op2val:0xbfa6; +op3val:0x35b9; valaddr_reg:x5; val_offset:1689*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 1689*FLEN/8, x9, x1, x4) + +inst_588: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1fc and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3a6 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1b9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31fc; op2val:0xbfa6; +op3val:0x35b9; valaddr_reg:x5; val_offset:1692*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1692*FLEN/8, x9, x1, x4) + +inst_589: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1fc and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3a6 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1b9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31fc; op2val:0xbfa6; +op3val:0x35b9; valaddr_reg:x5; val_offset:1695*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1695*FLEN/8, x9, x1, x4) + +inst_590: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x10b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x171 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2dc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x390b; op2val:0xbd71; +op3val:0x3adc; valaddr_reg:x5; val_offset:1698*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1698*FLEN/8, x9, x1, x4) + +inst_591: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x10b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x171 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2dc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x390b; op2val:0xbd71; +op3val:0x3adc; valaddr_reg:x5; val_offset:1701*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 1701*FLEN/8, x9, x1, x4) + +inst_592: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x10b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x171 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2dc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x390b; op2val:0xbd71; +op3val:0x3adc; valaddr_reg:x5; val_offset:1704*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 1704*FLEN/8, x9, x1, x4) + +inst_593: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x10b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x171 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2dc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x390b; op2val:0xbd71; +op3val:0x3adc; valaddr_reg:x5; val_offset:1707*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1707*FLEN/8, x9, x1, x4) + +inst_594: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x10b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x171 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2dc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x390b; op2val:0xbd71; +op3val:0x3adc; valaddr_reg:x5; val_offset:1710*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1710*FLEN/8, x9, x1, x4) + +inst_595: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x277 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x051 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2fa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3677; op2val:0xbc51; +op3val:0x36fa; valaddr_reg:x5; val_offset:1713*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1713*FLEN/8, x9, x1, x4) + +inst_596: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x277 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x051 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2fa and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3677; op2val:0xbc51; +op3val:0x36fa; valaddr_reg:x5; val_offset:1716*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 1716*FLEN/8, x9, x1, x4) + +inst_597: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x277 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x051 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2fa and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3677; op2val:0xbc51; +op3val:0x36fa; valaddr_reg:x5; val_offset:1719*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 1719*FLEN/8, x9, x1, x4) + +inst_598: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x277 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x051 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2fa and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3677; op2val:0xbc51; +op3val:0x36fa; valaddr_reg:x5; val_offset:1722*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1722*FLEN/8, x9, x1, x4) + +inst_599: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x277 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x051 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2fa and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3677; op2val:0xbc51; +op3val:0x36fa; valaddr_reg:x5; val_offset:1725*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1725*FLEN/8, x9, x1, x4) + +inst_600: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x17b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1fa and fs3 == 0 and fe3 == 0x0a and fm3 == 0x019 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x297b; op2val:0xb9fa; +op3val:0x2819; valaddr_reg:x5; val_offset:1728*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1728*FLEN/8, x9, x1, x4) + +inst_601: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x17b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1fa and fs3 == 0 and fe3 == 0x0a and fm3 == 0x019 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x297b; op2val:0xb9fa; +op3val:0x2819; valaddr_reg:x5; val_offset:1731*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 1731*FLEN/8, x9, x1, x4) + +inst_602: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x17b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1fa and fs3 == 0 and fe3 == 0x0a and fm3 == 0x019 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x297b; op2val:0xb9fa; +op3val:0x2819; valaddr_reg:x5; val_offset:1734*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 1734*FLEN/8, x9, x1, x4) + +inst_603: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x17b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1fa and fs3 == 0 and fe3 == 0x0a and fm3 == 0x019 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x297b; op2val:0xb9fa; +op3val:0x2819; valaddr_reg:x5; val_offset:1737*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1737*FLEN/8, x9, x1, x4) + +inst_604: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x17b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1fa and fs3 == 0 and fe3 == 0x0a and fm3 == 0x019 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x297b; op2val:0xb9fa; +op3val:0x2819; valaddr_reg:x5; val_offset:1740*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1740*FLEN/8, x9, x1, x4) + +inst_605: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x243 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2a1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x130 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3643; op2val:0xbea1; +op3val:0x3930; valaddr_reg:x5; val_offset:1743*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1743*FLEN/8, x9, x1, x4) + +inst_606: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x243 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2a1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x130 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3643; op2val:0xbea1; +op3val:0x3930; valaddr_reg:x5; val_offset:1746*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 1746*FLEN/8, x9, x1, x4) + +inst_607: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x243 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2a1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x130 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3643; op2val:0xbea1; +op3val:0x3930; valaddr_reg:x5; val_offset:1749*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 1749*FLEN/8, x9, x1, x4) + +inst_608: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x243 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2a1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x130 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3643; op2val:0xbea1; +op3val:0x3930; valaddr_reg:x5; val_offset:1752*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1752*FLEN/8, x9, x1, x4) + +inst_609: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x243 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2a1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x130 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3643; op2val:0xbea1; +op3val:0x3930; valaddr_reg:x5; val_offset:1755*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1755*FLEN/8, x9, x1, x4) + +inst_610: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2d2 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0af and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ed2; op2val:0xc8af; +op3val:0x3bfe; valaddr_reg:x5; val_offset:1758*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1758*FLEN/8, x9, x1, x4) + +inst_611: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2d2 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0af and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3fe and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ed2; op2val:0xc8af; +op3val:0x3bfe; valaddr_reg:x5; val_offset:1761*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 1761*FLEN/8, x9, x1, x4) + +inst_612: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2d2 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0af and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3fe and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ed2; op2val:0xc8af; +op3val:0x3bfe; valaddr_reg:x5; val_offset:1764*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 1764*FLEN/8, x9, x1, x4) + +inst_613: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2d2 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0af and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3fe and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ed2; op2val:0xc8af; +op3val:0x3bfe; valaddr_reg:x5; val_offset:1767*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1767*FLEN/8, x9, x1, x4) + +inst_614: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2d2 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0af and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3fe and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ed2; op2val:0xc8af; +op3val:0x3bfe; valaddr_reg:x5; val_offset:1770*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1770*FLEN/8, x9, x1, x4) + +inst_615: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x322 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3c9 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2f2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b22; op2val:0xb7c9; +op3val:0x36f2; valaddr_reg:x5; val_offset:1773*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1773*FLEN/8, x9, x1, x4) + +inst_616: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x322 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3c9 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2f2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b22; op2val:0xb7c9; +op3val:0x36f2; valaddr_reg:x5; val_offset:1776*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 1776*FLEN/8, x9, x1, x4) + +inst_617: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x322 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3c9 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2f2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b22; op2val:0xb7c9; +op3val:0x36f2; valaddr_reg:x5; val_offset:1779*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 1779*FLEN/8, x9, x1, x4) + +inst_618: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x322 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3c9 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2f2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b22; op2val:0xb7c9; +op3val:0x36f2; valaddr_reg:x5; val_offset:1782*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1782*FLEN/8, x9, x1, x4) + +inst_619: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x322 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3c9 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2f2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b22; op2val:0xb7c9; +op3val:0x36f2; valaddr_reg:x5; val_offset:1785*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1785*FLEN/8, x9, x1, x4) + +inst_620: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x228 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x077 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2df and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3628; op2val:0xc077; +op3val:0x3adf; valaddr_reg:x5; val_offset:1788*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1788*FLEN/8, x9, x1, x4) + +inst_621: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x228 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x077 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2df and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3628; op2val:0xc077; +op3val:0x3adf; valaddr_reg:x5; val_offset:1791*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 1791*FLEN/8, x9, x1, x4) + +inst_622: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x228 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x077 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2df and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3628; op2val:0xc077; +op3val:0x3adf; valaddr_reg:x5; val_offset:1794*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 1794*FLEN/8, x9, x1, x4) + +inst_623: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x228 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x077 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2df and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3628; op2val:0xc077; +op3val:0x3adf; valaddr_reg:x5; val_offset:1797*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1797*FLEN/8, x9, x1, x4) + +inst_624: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x228 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x077 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2df and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3628; op2val:0xc077; +op3val:0x3adf; valaddr_reg:x5; val_offset:1800*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1800*FLEN/8, x9, x1, x4) + +inst_625: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ed and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0b1 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x2f5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35ed; op2val:0xb4b1; +op3val:0x2ef5; valaddr_reg:x5; val_offset:1803*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1803*FLEN/8, x9, x1, x4) + +inst_626: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ed and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0b1 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x2f5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35ed; op2val:0xb4b1; +op3val:0x2ef5; valaddr_reg:x5; val_offset:1806*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 1806*FLEN/8, x9, x1, x4) + +inst_627: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ed and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0b1 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x2f5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35ed; op2val:0xb4b1; +op3val:0x2ef5; valaddr_reg:x5; val_offset:1809*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 1809*FLEN/8, x9, x1, x4) + +inst_628: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ed and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0b1 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x2f5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35ed; op2val:0xb4b1; +op3val:0x2ef5; valaddr_reg:x5; val_offset:1812*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1812*FLEN/8, x9, x1, x4) + +inst_629: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ed and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0b1 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x2f5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35ed; op2val:0xb4b1; +op3val:0x2ef5; valaddr_reg:x5; val_offset:1815*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1815*FLEN/8, x9, x1, x4) + +inst_630: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0fe and fs2 == 1 and fe2 == 0x0e and fm2 == 0x348 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38fe; op2val:0xbb48; +op3val:0x388b; valaddr_reg:x5; val_offset:1818*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1818*FLEN/8, x9, x1, x4) + +inst_631: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0fe and fs2 == 1 and fe2 == 0x0e and fm2 == 0x348 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38fe; op2val:0xbb48; +op3val:0x388b; valaddr_reg:x5; val_offset:1821*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 1821*FLEN/8, x9, x1, x4) + +inst_632: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0fe and fs2 == 1 and fe2 == 0x0e and fm2 == 0x348 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38fe; op2val:0xbb48; +op3val:0x388b; valaddr_reg:x5; val_offset:1824*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 1824*FLEN/8, x9, x1, x4) + +inst_633: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0fe and fs2 == 1 and fe2 == 0x0e and fm2 == 0x348 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38fe; op2val:0xbb48; +op3val:0x388b; valaddr_reg:x5; val_offset:1827*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1827*FLEN/8, x9, x1, x4) + +inst_634: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0fe and fs2 == 1 and fe2 == 0x0e and fm2 == 0x348 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38fe; op2val:0xbb48; +op3val:0x388b; valaddr_reg:x5; val_offset:1830*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1830*FLEN/8, x9, x1, x4) + +inst_635: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x230 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x353 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ab and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a30; op2val:0xbb53; +op3val:0x39ab; valaddr_reg:x5; val_offset:1833*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1833*FLEN/8, x9, x1, x4) + +inst_636: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x230 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x353 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ab and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a30; op2val:0xbb53; +op3val:0x39ab; valaddr_reg:x5; val_offset:1836*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 1836*FLEN/8, x9, x1, x4) + +inst_637: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x230 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x353 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ab and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a30; op2val:0xbb53; +op3val:0x39ab; valaddr_reg:x5; val_offset:1839*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 1839*FLEN/8, x9, x1, x4) + +inst_638: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x230 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x353 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ab and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a30; op2val:0xbb53; +op3val:0x39ab; valaddr_reg:x5; val_offset:1842*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1842*FLEN/8, x9, x1, x4) + +inst_639: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x230 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x353 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ab and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a30; op2val:0xbb53; +op3val:0x39ab; valaddr_reg:x5; val_offset:1845*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1845*FLEN/8, x9, x1, x4) + +inst_640: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x311 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x19d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0f6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2711; op2val:0xcd9d; +op3val:0x38f6; valaddr_reg:x5; val_offset:1848*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1848*FLEN/8, x9, x1, x4) + +inst_641: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x311 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x19d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0f6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2711; op2val:0xcd9d; +op3val:0x38f6; valaddr_reg:x5; val_offset:1851*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 1851*FLEN/8, x9, x1, x4) + +inst_642: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x311 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x19d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0f6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2711; op2val:0xcd9d; +op3val:0x38f6; valaddr_reg:x5; val_offset:1854*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 1854*FLEN/8, x9, x1, x4) + +inst_643: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x311 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x19d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0f6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2711; op2val:0xcd9d; +op3val:0x38f6; valaddr_reg:x5; val_offset:1857*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1857*FLEN/8, x9, x1, x4) + +inst_644: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x311 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x19d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0f6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2711; op2val:0xcd9d; +op3val:0x38f6; valaddr_reg:x5; val_offset:1860*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1860*FLEN/8, x9, x1, x4) + +inst_645: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x10 and fm2 == 0x06e and fs3 == 0 and fe3 == 0x0b and fm3 == 0x186 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x28fb; op2val:0xc06e; +op3val:0x2d86; valaddr_reg:x5; val_offset:1863*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1863*FLEN/8, x9, x1, x4) + +inst_646: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x10 and fm2 == 0x06e and fs3 == 0 and fe3 == 0x0b and fm3 == 0x186 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x28fb; op2val:0xc06e; +op3val:0x2d86; valaddr_reg:x5; val_offset:1866*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 1866*FLEN/8, x9, x1, x4) + +inst_647: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x10 and fm2 == 0x06e and fs3 == 0 and fe3 == 0x0b and fm3 == 0x186 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x28fb; op2val:0xc06e; +op3val:0x2d86; valaddr_reg:x5; val_offset:1869*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 1869*FLEN/8, x9, x1, x4) + +inst_648: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x10 and fm2 == 0x06e and fs3 == 0 and fe3 == 0x0b and fm3 == 0x186 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x28fb; op2val:0xc06e; +op3val:0x2d86; valaddr_reg:x5; val_offset:1872*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1872*FLEN/8, x9, x1, x4) + +inst_649: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x10 and fm2 == 0x06e and fs3 == 0 and fe3 == 0x0b and fm3 == 0x186 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x28fb; op2val:0xc06e; +op3val:0x2d86; valaddr_reg:x5; val_offset:1875*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1875*FLEN/8, x9, x1, x4) + +inst_650: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x277 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x352 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1eb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3677; op2val:0xbf52; +op3val:0x39eb; valaddr_reg:x5; val_offset:1878*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1878*FLEN/8, x9, x1, x4) + +inst_651: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x277 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x352 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1eb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3677; op2val:0xbf52; +op3val:0x39eb; valaddr_reg:x5; val_offset:1881*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 1881*FLEN/8, x9, x1, x4) + +inst_652: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x277 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x352 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1eb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3677; op2val:0xbf52; +op3val:0x39eb; valaddr_reg:x5; val_offset:1884*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 1884*FLEN/8, x9, x1, x4) + +inst_653: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x277 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x352 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1eb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3677; op2val:0xbf52; +op3val:0x39eb; valaddr_reg:x5; val_offset:1887*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1887*FLEN/8, x9, x1, x4) + +inst_654: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x277 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x352 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1eb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3677; op2val:0xbf52; +op3val:0x39eb; valaddr_reg:x5; val_offset:1890*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1890*FLEN/8, x9, x1, x4) + +inst_655: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x0e2 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x299 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x24e2; op2val:0xce99; +op3val:0x3807; valaddr_reg:x5; val_offset:1893*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1893*FLEN/8, x9, x1, x4) + +inst_656: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x0e2 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x299 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x007 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x24e2; op2val:0xce99; +op3val:0x3807; valaddr_reg:x5; val_offset:1896*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 1896*FLEN/8, x9, x1, x4) + +inst_657: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x0e2 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x299 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x007 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x24e2; op2val:0xce99; +op3val:0x3807; valaddr_reg:x5; val_offset:1899*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 1899*FLEN/8, x9, x1, x4) + +inst_658: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x0e2 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x299 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x007 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x24e2; op2val:0xce99; +op3val:0x3807; valaddr_reg:x5; val_offset:1902*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1902*FLEN/8, x9, x1, x4) + +inst_659: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x0e2 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x299 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x007 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x24e2; op2val:0xce99; +op3val:0x3807; valaddr_reg:x5; val_offset:1905*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1905*FLEN/8, x9, x1, x4) + +inst_660: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ad and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0a8 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x172 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ad; op2val:0xbca8; +op3val:0x3972; valaddr_reg:x5; val_offset:1908*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1908*FLEN/8, x9, x1, x4) + +inst_661: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ad and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0a8 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x172 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ad; op2val:0xbca8; +op3val:0x3972; valaddr_reg:x5; val_offset:1911*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 1911*FLEN/8, x9, x1, x4) + +inst_662: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ad and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0a8 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x172 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ad; op2val:0xbca8; +op3val:0x3972; valaddr_reg:x5; val_offset:1914*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 1914*FLEN/8, x9, x1, x4) + +inst_663: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ad and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0a8 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x172 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ad; op2val:0xbca8; +op3val:0x3972; valaddr_reg:x5; val_offset:1917*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1917*FLEN/8, x9, x1, x4) + +inst_664: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ad and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0a8 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x172 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ad; op2val:0xbca8; +op3val:0x3972; valaddr_reg:x5; val_offset:1920*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1920*FLEN/8, x9, x1, x4) + +inst_665: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x00a and fs2 == 1 and fe2 == 0x14 and fm2 == 0x006 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x010 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x240a; op2val:0xd006; +op3val:0x3810; valaddr_reg:x5; val_offset:1923*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1923*FLEN/8, x9, x1, x4) + +inst_666: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x00a and fs2 == 1 and fe2 == 0x14 and fm2 == 0x006 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x010 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x240a; op2val:0xd006; +op3val:0x3810; valaddr_reg:x5; val_offset:1926*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 1926*FLEN/8, x9, x1, x4) + +inst_667: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x00a and fs2 == 1 and fe2 == 0x14 and fm2 == 0x006 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x010 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x240a; op2val:0xd006; +op3val:0x3810; valaddr_reg:x5; val_offset:1929*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 1929*FLEN/8, x9, x1, x4) + +inst_668: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x00a and fs2 == 1 and fe2 == 0x14 and fm2 == 0x006 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x010 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x240a; op2val:0xd006; +op3val:0x3810; valaddr_reg:x5; val_offset:1932*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1932*FLEN/8, x9, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_6) + +inst_669: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x00a and fs2 == 1 and fe2 == 0x14 and fm2 == 0x006 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x010 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x240a; op2val:0xd006; +op3val:0x3810; valaddr_reg:x5; val_offset:1935*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1935*FLEN/8, x9, x1, x4) + +inst_670: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1b5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1dd and fs3 == 0 and fe3 == 0x0e and fm3 == 0x02f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39b5; op2val:0xb9dd; +op3val:0x382f; valaddr_reg:x5; val_offset:1938*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1938*FLEN/8, x9, x1, x4) + +inst_671: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1b5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1dd and fs3 == 0 and fe3 == 0x0e and fm3 == 0x02f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39b5; op2val:0xb9dd; +op3val:0x382f; valaddr_reg:x5; val_offset:1941*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 1941*FLEN/8, x9, x1, x4) + +inst_672: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1b5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1dd and fs3 == 0 and fe3 == 0x0e and fm3 == 0x02f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39b5; op2val:0xb9dd; +op3val:0x382f; valaddr_reg:x5; val_offset:1944*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 1944*FLEN/8, x9, x1, x4) + +inst_673: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1b5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1dd and fs3 == 0 and fe3 == 0x0e and fm3 == 0x02f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39b5; op2val:0xb9dd; +op3val:0x382f; valaddr_reg:x5; val_offset:1947*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1947*FLEN/8, x9, x1, x4) + +inst_674: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1b5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1dd and fs3 == 0 and fe3 == 0x0e and fm3 == 0x02f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39b5; op2val:0xb9dd; +op3val:0x382f; valaddr_reg:x5; val_offset:1950*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1950*FLEN/8, x9, x1, x4) + +inst_675: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x306 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2e4 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x20d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b06; op2val:0xb6e4; +op3val:0x360d; valaddr_reg:x5; val_offset:1953*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1953*FLEN/8, x9, x1, x4) + +inst_676: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x306 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2e4 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x20d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b06; op2val:0xb6e4; +op3val:0x360d; valaddr_reg:x5; val_offset:1956*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 1956*FLEN/8, x9, x1, x4) + +inst_677: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x306 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2e4 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x20d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b06; op2val:0xb6e4; +op3val:0x360d; valaddr_reg:x5; val_offset:1959*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 1959*FLEN/8, x9, x1, x4) + +inst_678: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x306 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2e4 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x20d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b06; op2val:0xb6e4; +op3val:0x360d; valaddr_reg:x5; val_offset:1962*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1962*FLEN/8, x9, x1, x4) + +inst_679: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x306 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2e4 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x20d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b06; op2val:0xb6e4; +op3val:0x360d; valaddr_reg:x5; val_offset:1965*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1965*FLEN/8, x9, x1, x4) + +inst_680: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x073 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x114 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3873; op2val:0xbd14; +op3val:0x39a7; valaddr_reg:x5; val_offset:1968*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1968*FLEN/8, x9, x1, x4) + +inst_681: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x073 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x114 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3873; op2val:0xbd14; +op3val:0x39a7; valaddr_reg:x5; val_offset:1971*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 1971*FLEN/8, x9, x1, x4) + +inst_682: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x073 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x114 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3873; op2val:0xbd14; +op3val:0x39a7; valaddr_reg:x5; val_offset:1974*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 1974*FLEN/8, x9, x1, x4) + +inst_683: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x073 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x114 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3873; op2val:0xbd14; +op3val:0x39a7; valaddr_reg:x5; val_offset:1977*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1977*FLEN/8, x9, x1, x4) + +inst_684: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x073 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x114 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3873; op2val:0xbd14; +op3val:0x39a7; valaddr_reg:x5; val_offset:1980*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1980*FLEN/8, x9, x1, x4) + +inst_685: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2fc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x258 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x18b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32fc; op2val:0xba58; +op3val:0x318b; valaddr_reg:x5; val_offset:1983*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1983*FLEN/8, x9, x1, x4) + +inst_686: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2fc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x258 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x18b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32fc; op2val:0xba58; +op3val:0x318b; valaddr_reg:x5; val_offset:1986*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 1986*FLEN/8, x9, x1, x4) + +inst_687: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2fc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x258 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x18b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32fc; op2val:0xba58; +op3val:0x318b; valaddr_reg:x5; val_offset:1989*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 1989*FLEN/8, x9, x1, x4) + +inst_688: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2fc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x258 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x18b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32fc; op2val:0xba58; +op3val:0x318b; valaddr_reg:x5; val_offset:1992*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 1992*FLEN/8, x9, x1, x4) + +inst_689: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2fc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x258 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x18b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32fc; op2val:0xba58; +op3val:0x318b; valaddr_reg:x5; val_offset:1995*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 1995*FLEN/8, x9, x1, x4) + +inst_690: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e4 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x394 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x37a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3be4; op2val:0xb794; +op3val:0x377a; valaddr_reg:x5; val_offset:1998*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 1998*FLEN/8, x9, x1, x4) + +inst_691: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e4 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x394 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x37a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3be4; op2val:0xb794; +op3val:0x377a; valaddr_reg:x5; val_offset:2001*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2001*FLEN/8, x9, x1, x4) + +inst_692: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e4 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x394 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x37a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3be4; op2val:0xb794; +op3val:0x377a; valaddr_reg:x5; val_offset:2004*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2004*FLEN/8, x9, x1, x4) + +inst_693: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e4 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x394 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x37a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3be4; op2val:0xb794; +op3val:0x377a; valaddr_reg:x5; val_offset:2007*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2007*FLEN/8, x9, x1, x4) + +inst_694: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e4 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x394 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x37a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3be4; op2val:0xb794; +op3val:0x377a; valaddr_reg:x5; val_offset:2010*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 2010*FLEN/8, x9, x1, x4) + +inst_695: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1cf and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1b4 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x025 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39cf; op2val:0xadb4; +op3val:0x2c25; valaddr_reg:x5; val_offset:2013*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 2013*FLEN/8, x9, x1, x4) + +inst_696: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1cf and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1b4 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x025 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39cf; op2val:0xadb4; +op3val:0x2c25; valaddr_reg:x5; val_offset:2016*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2016*FLEN/8, x9, x1, x4) + +inst_697: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1cf and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1b4 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x025 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39cf; op2val:0xadb4; +op3val:0x2c25; valaddr_reg:x5; val_offset:2019*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2019*FLEN/8, x9, x1, x4) + +inst_698: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1cf and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1b4 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x025 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39cf; op2val:0xadb4; +op3val:0x2c25; valaddr_reg:x5; val_offset:2022*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2022*FLEN/8, x9, x1, x4) + +inst_699: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1cf and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1b4 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x025 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39cf; op2val:0xadb4; +op3val:0x2c25; valaddr_reg:x5; val_offset:2025*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 2025*FLEN/8, x9, x1, x4) + +inst_700: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2fb and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2ea and fs3 == 0 and fe3 == 0x0e and fm3 == 0x208 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32fb; op2val:0xc2ea; +op3val:0x3a08; valaddr_reg:x5; val_offset:2028*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 2028*FLEN/8, x9, x1, x4) + +inst_701: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2fb and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2ea and fs3 == 0 and fe3 == 0x0e and fm3 == 0x208 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32fb; op2val:0xc2ea; +op3val:0x3a08; valaddr_reg:x5; val_offset:2031*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2031*FLEN/8, x9, x1, x4) + +inst_702: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2fb and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2ea and fs3 == 0 and fe3 == 0x0e and fm3 == 0x208 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32fb; op2val:0xc2ea; +op3val:0x3a08; valaddr_reg:x5; val_offset:2034*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2034*FLEN/8, x9, x1, x4) + +inst_703: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2fb and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2ea and fs3 == 0 and fe3 == 0x0e and fm3 == 0x208 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32fb; op2val:0xc2ea; +op3val:0x3a08; valaddr_reg:x5; val_offset:2037*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2037*FLEN/8, x9, x1, x4) + +inst_704: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2fb and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2ea and fs3 == 0 and fe3 == 0x0e and fm3 == 0x208 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32fb; op2val:0xc2ea; +op3val:0x3a08; valaddr_reg:x5; val_offset:2040*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 2040*FLEN/8, x9, x1, x4) + +inst_705: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1db and fs2 == 1 and fe2 == 0x0f and fm2 == 0x09d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2c3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39db; op2val:0xbc9d; +op3val:0x3ac3; valaddr_reg:x5; val_offset:2043*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 2043*FLEN/8, x9, x1, x4) + +inst_706: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1db and fs2 == 1 and fe2 == 0x0f and fm2 == 0x09d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2c3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39db; op2val:0xbc9d; +op3val:0x3ac3; valaddr_reg:x5; val_offset:2046*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2046*FLEN/8, x9, x1, x4) + +inst_707: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1db and fs2 == 1 and fe2 == 0x0f and fm2 == 0x09d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2c3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39db; op2val:0xbc9d; +op3val:0x3ac3; valaddr_reg:x5; val_offset:2049*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2049*FLEN/8, x9, x1, x4) + +inst_708: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1db and fs2 == 1 and fe2 == 0x0f and fm2 == 0x09d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2c3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39db; op2val:0xbc9d; +op3val:0x3ac3; valaddr_reg:x5; val_offset:2052*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2052*FLEN/8, x9, x1, x4) + +inst_709: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1db and fs2 == 1 and fe2 == 0x0f and fm2 == 0x09d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2c3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39db; op2val:0xbc9d; +op3val:0x3ac3; valaddr_reg:x5; val_offset:2055*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 2055*FLEN/8, x9, x1, x4) + +inst_710: +// fs1 == 0 and fe1 == 0x08 and fm1 == 0x1c0 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x3dd and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x21c0; op2val:0xd3dd; +op3val:0x39a7; valaddr_reg:x5; val_offset:2058*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 2058*FLEN/8, x9, x1, x4) + +inst_711: +// fs1 == 0 and fe1 == 0x08 and fm1 == 0x1c0 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x3dd and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x21c0; op2val:0xd3dd; +op3val:0x39a7; valaddr_reg:x5; val_offset:2061*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2061*FLEN/8, x9, x1, x4) + +inst_712: +// fs1 == 0 and fe1 == 0x08 and fm1 == 0x1c0 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x3dd and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x21c0; op2val:0xd3dd; +op3val:0x39a7; valaddr_reg:x5; val_offset:2064*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2064*FLEN/8, x9, x1, x4) + +inst_713: +// fs1 == 0 and fe1 == 0x08 and fm1 == 0x1c0 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x3dd and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x21c0; op2val:0xd3dd; +op3val:0x39a7; valaddr_reg:x5; val_offset:2067*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2067*FLEN/8, x9, x1, x4) + +inst_714: +// fs1 == 0 and fe1 == 0x08 and fm1 == 0x1c0 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x3dd and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x21c0; op2val:0xd3dd; +op3val:0x39a7; valaddr_reg:x5; val_offset:2070*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 2070*FLEN/8, x9, x1, x4) + +inst_715: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x245 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x15c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x034 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3645; op2val:0xbd5c; +op3val:0x3834; valaddr_reg:x5; val_offset:2073*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 2073*FLEN/8, x9, x1, x4) + +inst_716: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x245 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x15c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x034 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3645; op2val:0xbd5c; +op3val:0x3834; valaddr_reg:x5; val_offset:2076*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2076*FLEN/8, x9, x1, x4) + +inst_717: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x245 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x15c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x034 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3645; op2val:0xbd5c; +op3val:0x3834; valaddr_reg:x5; val_offset:2079*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2079*FLEN/8, x9, x1, x4) + +inst_718: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x245 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x15c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x034 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3645; op2val:0xbd5c; +op3val:0x3834; valaddr_reg:x5; val_offset:2082*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2082*FLEN/8, x9, x1, x4) + +inst_719: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x245 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x15c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x034 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3645; op2val:0xbd5c; +op3val:0x3834; valaddr_reg:x5; val_offset:2085*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 2085*FLEN/8, x9, x1, x4) + +inst_720: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ae and fs2 == 1 and fe2 == 0x0f and fm2 == 0x076 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x256 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35ae; op2val:0xbc76; +op3val:0x3656; valaddr_reg:x5; val_offset:2088*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 2088*FLEN/8, x9, x1, x4) + +inst_721: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ae and fs2 == 1 and fe2 == 0x0f and fm2 == 0x076 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x256 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35ae; op2val:0xbc76; +op3val:0x3656; valaddr_reg:x5; val_offset:2091*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2091*FLEN/8, x9, x1, x4) + +inst_722: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ae and fs2 == 1 and fe2 == 0x0f and fm2 == 0x076 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x256 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35ae; op2val:0xbc76; +op3val:0x3656; valaddr_reg:x5; val_offset:2094*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2094*FLEN/8, x9, x1, x4) + +inst_723: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ae and fs2 == 1 and fe2 == 0x0f and fm2 == 0x076 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x256 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35ae; op2val:0xbc76; +op3val:0x3656; valaddr_reg:x5; val_offset:2097*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2097*FLEN/8, x9, x1, x4) + +inst_724: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ae and fs2 == 1 and fe2 == 0x0f and fm2 == 0x076 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x256 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35ae; op2val:0xbc76; +op3val:0x3656; valaddr_reg:x5; val_offset:2100*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 2100*FLEN/8, x9, x1, x4) + +inst_725: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x01a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2df and fs3 == 0 and fe3 == 0x0e and fm3 == 0x30d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x341a; op2val:0xc2df; +op3val:0x3b0d; valaddr_reg:x5; val_offset:2103*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 2103*FLEN/8, x9, x1, x4) + +inst_726: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x01a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2df and fs3 == 0 and fe3 == 0x0e and fm3 == 0x30d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x341a; op2val:0xc2df; +op3val:0x3b0d; valaddr_reg:x5; val_offset:2106*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2106*FLEN/8, x9, x1, x4) + +inst_727: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x01a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2df and fs3 == 0 and fe3 == 0x0e and fm3 == 0x30d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x341a; op2val:0xc2df; +op3val:0x3b0d; valaddr_reg:x5; val_offset:2109*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2109*FLEN/8, x9, x1, x4) + +inst_728: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x01a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2df and fs3 == 0 and fe3 == 0x0e and fm3 == 0x30d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x341a; op2val:0xc2df; +op3val:0x3b0d; valaddr_reg:x5; val_offset:2112*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2112*FLEN/8, x9, x1, x4) + +inst_729: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x01a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2df and fs3 == 0 and fe3 == 0x0e and fm3 == 0x30d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x341a; op2val:0xc2df; +op3val:0x3b0d; valaddr_reg:x5; val_offset:2115*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 2115*FLEN/8, x9, x1, x4) + +inst_730: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3ab and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1d5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x198 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x33ab; op2val:0xc1d5; +op3val:0x3998; valaddr_reg:x5; val_offset:2118*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 2118*FLEN/8, x9, x1, x4) + +inst_731: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3ab and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1d5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x198 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x33ab; op2val:0xc1d5; +op3val:0x3998; valaddr_reg:x5; val_offset:2121*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2121*FLEN/8, x9, x1, x4) + +inst_732: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3ab and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1d5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x198 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x33ab; op2val:0xc1d5; +op3val:0x3998; valaddr_reg:x5; val_offset:2124*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2124*FLEN/8, x9, x1, x4) + +inst_733: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3ab and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1d5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x198 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x33ab; op2val:0xc1d5; +op3val:0x3998; valaddr_reg:x5; val_offset:2127*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2127*FLEN/8, x9, x1, x4) + +inst_734: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3ab and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1d5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x198 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x33ab; op2val:0xc1d5; +op3val:0x3998; valaddr_reg:x5; val_offset:2130*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 2130*FLEN/8, x9, x1, x4) + +inst_735: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x376 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1b1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x14f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3776; op2val:0xbdb1; +op3val:0x394f; valaddr_reg:x5; val_offset:2133*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 2133*FLEN/8, x9, x1, x4) + +inst_736: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x376 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1b1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x14f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3776; op2val:0xbdb1; +op3val:0x394f; valaddr_reg:x5; val_offset:2136*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2136*FLEN/8, x9, x1, x4) + +inst_737: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x376 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1b1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x14f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3776; op2val:0xbdb1; +op3val:0x394f; valaddr_reg:x5; val_offset:2139*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2139*FLEN/8, x9, x1, x4) + +inst_738: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x376 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1b1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x14f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3776; op2val:0xbdb1; +op3val:0x394f; valaddr_reg:x5; val_offset:2142*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2142*FLEN/8, x9, x1, x4) + +inst_739: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x376 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1b1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x14f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3776; op2val:0xbdb1; +op3val:0x394f; valaddr_reg:x5; val_offset:2145*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 2145*FLEN/8, x9, x1, x4) + +inst_740: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a0 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x159 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x385 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39a0; op2val:0xb959; +op3val:0x3785; valaddr_reg:x5; val_offset:2148*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 2148*FLEN/8, x9, x1, x4) + +inst_741: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a0 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x159 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x385 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39a0; op2val:0xb959; +op3val:0x3785; valaddr_reg:x5; val_offset:2151*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2151*FLEN/8, x9, x1, x4) + +inst_742: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a0 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x159 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x385 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39a0; op2val:0xb959; +op3val:0x3785; valaddr_reg:x5; val_offset:2154*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2154*FLEN/8, x9, x1, x4) + +inst_743: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a0 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x159 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x385 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39a0; op2val:0xb959; +op3val:0x3785; valaddr_reg:x5; val_offset:2157*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2157*FLEN/8, x9, x1, x4) + +inst_744: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a0 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x159 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x385 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39a0; op2val:0xb959; +op3val:0x3785; valaddr_reg:x5; val_offset:2160*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 2160*FLEN/8, x9, x1, x4) + +inst_745: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x049 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x11c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3849; op2val:0xbcc5; +op3val:0x391c; valaddr_reg:x5; val_offset:2163*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 2163*FLEN/8, x9, x1, x4) + +inst_746: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x049 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x11c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3849; op2val:0xbcc5; +op3val:0x391c; valaddr_reg:x5; val_offset:2166*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2166*FLEN/8, x9, x1, x4) + +inst_747: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x049 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x11c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3849; op2val:0xbcc5; +op3val:0x391c; valaddr_reg:x5; val_offset:2169*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2169*FLEN/8, x9, x1, x4) + +inst_748: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x049 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x11c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3849; op2val:0xbcc5; +op3val:0x391c; valaddr_reg:x5; val_offset:2172*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2172*FLEN/8, x9, x1, x4) + +inst_749: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x049 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x11c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3849; op2val:0xbcc5; +op3val:0x391c; valaddr_reg:x5; val_offset:2175*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 2175*FLEN/8, x9, x1, x4) + +inst_750: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x014 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x26a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x28c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3414; op2val:0xbe6a; +op3val:0x368c; valaddr_reg:x5; val_offset:2178*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 2178*FLEN/8, x9, x1, x4) + +inst_751: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x014 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x26a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x28c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3414; op2val:0xbe6a; +op3val:0x368c; valaddr_reg:x5; val_offset:2181*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2181*FLEN/8, x9, x1, x4) + +inst_752: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x014 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x26a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x28c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3414; op2val:0xbe6a; +op3val:0x368c; valaddr_reg:x5; val_offset:2184*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2184*FLEN/8, x9, x1, x4) + +inst_753: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x014 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x26a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x28c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3414; op2val:0xbe6a; +op3val:0x368c; valaddr_reg:x5; val_offset:2187*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2187*FLEN/8, x9, x1, x4) + +inst_754: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x014 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x26a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x28c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3414; op2val:0xbe6a; +op3val:0x368c; valaddr_reg:x5; val_offset:2190*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 2190*FLEN/8, x9, x1, x4) + +inst_755: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x234 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1fb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bb5; op2val:0xba34; +op3val:0x39fb; valaddr_reg:x5; val_offset:2193*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 2193*FLEN/8, x9, x1, x4) + +inst_756: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x234 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1fb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bb5; op2val:0xba34; +op3val:0x39fb; valaddr_reg:x5; val_offset:2196*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2196*FLEN/8, x9, x1, x4) + +inst_757: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x234 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1fb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bb5; op2val:0xba34; +op3val:0x39fb; valaddr_reg:x5; val_offset:2199*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2199*FLEN/8, x9, x1, x4) + +inst_758: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x234 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1fb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bb5; op2val:0xba34; +op3val:0x39fb; valaddr_reg:x5; val_offset:2202*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2202*FLEN/8, x9, x1, x4) + +inst_759: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x234 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1fb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bb5; op2val:0xba34; +op3val:0x39fb; valaddr_reg:x5; val_offset:2205*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 2205*FLEN/8, x9, x1, x4) + +inst_760: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x05a and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0e7 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x157 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x385a; op2val:0xb0e7; +op3val:0x2d57; valaddr_reg:x5; val_offset:2208*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 2208*FLEN/8, x9, x1, x4) + +inst_761: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x05a and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0e7 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x157 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x385a; op2val:0xb0e7; +op3val:0x2d57; valaddr_reg:x5; val_offset:2211*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2211*FLEN/8, x9, x1, x4) + +inst_762: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x05a and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0e7 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x157 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x385a; op2val:0xb0e7; +op3val:0x2d57; valaddr_reg:x5; val_offset:2214*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2214*FLEN/8, x9, x1, x4) + +inst_763: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x05a and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0e7 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x157 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x385a; op2val:0xb0e7; +op3val:0x2d57; valaddr_reg:x5; val_offset:2217*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2217*FLEN/8, x9, x1, x4) + +inst_764: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x05a and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0e7 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x157 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x385a; op2val:0xb0e7; +op3val:0x2d57; valaddr_reg:x5; val_offset:2220*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 2220*FLEN/8, x9, x1, x4) + +inst_765: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x32c and fs2 == 1 and fe2 == 0x11 and fm2 == 0x00d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x345 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f2c; op2val:0xc40d; +op3val:0x3745; valaddr_reg:x5; val_offset:2223*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 2223*FLEN/8, x9, x1, x4) + +inst_766: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x32c and fs2 == 1 and fe2 == 0x11 and fm2 == 0x00d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x345 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f2c; op2val:0xc40d; +op3val:0x3745; valaddr_reg:x5; val_offset:2226*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2226*FLEN/8, x9, x1, x4) + +inst_767: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x32c and fs2 == 1 and fe2 == 0x11 and fm2 == 0x00d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x345 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f2c; op2val:0xc40d; +op3val:0x3745; valaddr_reg:x5; val_offset:2229*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2229*FLEN/8, x9, x1, x4) + +inst_768: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x32c and fs2 == 1 and fe2 == 0x11 and fm2 == 0x00d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x345 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f2c; op2val:0xc40d; +op3val:0x3745; valaddr_reg:x5; val_offset:2232*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2232*FLEN/8, x9, x1, x4) + +inst_769: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x32c and fs2 == 1 and fe2 == 0x11 and fm2 == 0x00d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x345 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f2c; op2val:0xc40d; +op3val:0x3745; valaddr_reg:x5; val_offset:2235*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 2235*FLEN/8, x9, x1, x4) + +inst_770: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e2 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x332 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x317 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3be2; op2val:0xb332; +op3val:0x3317; valaddr_reg:x5; val_offset:2238*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 2238*FLEN/8, x9, x1, x4) + +inst_771: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e2 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x332 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x317 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3be2; op2val:0xb332; +op3val:0x3317; valaddr_reg:x5; val_offset:2241*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2241*FLEN/8, x9, x1, x4) + +inst_772: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e2 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x332 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x317 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3be2; op2val:0xb332; +op3val:0x3317; valaddr_reg:x5; val_offset:2244*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2244*FLEN/8, x9, x1, x4) + +inst_773: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e2 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x332 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x317 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3be2; op2val:0xb332; +op3val:0x3317; valaddr_reg:x5; val_offset:2247*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2247*FLEN/8, x9, x1, x4) + +inst_774: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e2 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x332 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x317 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3be2; op2val:0xb332; +op3val:0x3317; valaddr_reg:x5; val_offset:2250*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 2250*FLEN/8, x9, x1, x4) + +inst_775: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x094 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1ee and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2ca and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3894; op2val:0xb9ee; +op3val:0x36ca; valaddr_reg:x5; val_offset:2253*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 2253*FLEN/8, x9, x1, x4) + +inst_776: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x094 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1ee and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2ca and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3894; op2val:0xb9ee; +op3val:0x36ca; valaddr_reg:x5; val_offset:2256*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2256*FLEN/8, x9, x1, x4) + +inst_777: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x094 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1ee and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2ca and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3894; op2val:0xb9ee; +op3val:0x36ca; valaddr_reg:x5; val_offset:2259*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2259*FLEN/8, x9, x1, x4) + +inst_778: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x094 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1ee and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2ca and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3894; op2val:0xb9ee; +op3val:0x36ca; valaddr_reg:x5; val_offset:2262*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2262*FLEN/8, x9, x1, x4) + +inst_779: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x094 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1ee and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2ca and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3894; op2val:0xb9ee; +op3val:0x36ca; valaddr_reg:x5; val_offset:2265*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 2265*FLEN/8, x9, x1, x4) + +inst_780: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ab and fs2 == 1 and fe2 == 0x0f and fm2 == 0x10a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1e2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34ab; op2val:0xbd0a; +op3val:0x35e2; valaddr_reg:x5; val_offset:2268*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 2268*FLEN/8, x9, x1, x4) + +inst_781: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ab and fs2 == 1 and fe2 == 0x0f and fm2 == 0x10a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1e2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34ab; op2val:0xbd0a; +op3val:0x35e2; valaddr_reg:x5; val_offset:2271*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2271*FLEN/8, x9, x1, x4) + +inst_782: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ab and fs2 == 1 and fe2 == 0x0f and fm2 == 0x10a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1e2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34ab; op2val:0xbd0a; +op3val:0x35e2; valaddr_reg:x5; val_offset:2274*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2274*FLEN/8, x9, x1, x4) + +inst_783: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ab and fs2 == 1 and fe2 == 0x0f and fm2 == 0x10a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1e2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34ab; op2val:0xbd0a; +op3val:0x35e2; valaddr_reg:x5; val_offset:2277*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2277*FLEN/8, x9, x1, x4) + +inst_784: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ab and fs2 == 1 and fe2 == 0x0f and fm2 == 0x10a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1e2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34ab; op2val:0xbd0a; +op3val:0x35e2; valaddr_reg:x5; val_offset:2280*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 2280*FLEN/8, x9, x1, x4) + +inst_785: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x025 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x173 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1a7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3825; op2val:0xb173; +op3val:0x2da7; valaddr_reg:x5; val_offset:2283*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 2283*FLEN/8, x9, x1, x4) + +inst_786: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x025 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x173 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1a7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3825; op2val:0xb173; +op3val:0x2da7; valaddr_reg:x5; val_offset:2286*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2286*FLEN/8, x9, x1, x4) + +inst_787: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x025 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x173 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1a7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3825; op2val:0xb173; +op3val:0x2da7; valaddr_reg:x5; val_offset:2289*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2289*FLEN/8, x9, x1, x4) + +inst_788: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x025 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x173 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1a7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3825; op2val:0xb173; +op3val:0x2da7; valaddr_reg:x5; val_offset:2292*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2292*FLEN/8, x9, x1, x4) + +inst_789: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x025 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x173 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1a7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3825; op2val:0xb173; +op3val:0x2da7; valaddr_reg:x5; val_offset:2295*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 2295*FLEN/8, x9, x1, x4) + +inst_790: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ea and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3ea and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0dd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ea; op2val:0xbbea; +op3val:0x38dd; valaddr_reg:x5; val_offset:2298*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 2298*FLEN/8, x9, x1, x4) + +inst_791: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ea and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3ea and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0dd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ea; op2val:0xbbea; +op3val:0x38dd; valaddr_reg:x5; val_offset:2301*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2301*FLEN/8, x9, x1, x4) + +inst_792: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ea and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3ea and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0dd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ea; op2val:0xbbea; +op3val:0x38dd; valaddr_reg:x5; val_offset:2304*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2304*FLEN/8, x9, x1, x4) + +inst_793: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ea and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3ea and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0dd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ea; op2val:0xbbea; +op3val:0x38dd; valaddr_reg:x5; val_offset:2307*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2307*FLEN/8, x9, x1, x4) + +inst_794: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ea and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3ea and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0dd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ea; op2val:0xbbea; +op3val:0x38dd; valaddr_reg:x5; val_offset:2310*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 2310*FLEN/8, x9, x1, x4) + +inst_795: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0bd and fs2 == 1 and fe2 == 0x11 and fm2 == 0x16c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x26d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30bd; op2val:0xc56c; +op3val:0x3a6d; valaddr_reg:x5; val_offset:2313*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 2313*FLEN/8, x9, x1, x4) + +inst_796: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0bd and fs2 == 1 and fe2 == 0x11 and fm2 == 0x16c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x26d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30bd; op2val:0xc56c; +op3val:0x3a6d; valaddr_reg:x5; val_offset:2316*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2316*FLEN/8, x9, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_7) + +inst_797: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0bd and fs2 == 1 and fe2 == 0x11 and fm2 == 0x16c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x26d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30bd; op2val:0xc56c; +op3val:0x3a6d; valaddr_reg:x5; val_offset:2319*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2319*FLEN/8, x9, x1, x4) + +inst_798: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0bd and fs2 == 1 and fe2 == 0x11 and fm2 == 0x16c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x26d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30bd; op2val:0xc56c; +op3val:0x3a6d; valaddr_reg:x5; val_offset:2322*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2322*FLEN/8, x9, x1, x4) + +inst_799: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0bd and fs2 == 1 and fe2 == 0x11 and fm2 == 0x16c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x26d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30bd; op2val:0xc56c; +op3val:0x3a6d; valaddr_reg:x5; val_offset:2325*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 2325*FLEN/8, x9, x1, x4) + +inst_800: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a0 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3ba and fs3 == 0 and fe3 == 0x0c and fm3 == 0x170 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39a0; op2val:0xb3ba; +op3val:0x3170; valaddr_reg:x5; val_offset:2328*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 2328*FLEN/8, x9, x1, x4) + +inst_801: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a0 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3ba and fs3 == 0 and fe3 == 0x0c and fm3 == 0x170 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39a0; op2val:0xb3ba; +op3val:0x3170; valaddr_reg:x5; val_offset:2331*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2331*FLEN/8, x9, x1, x4) + +inst_802: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a0 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3ba and fs3 == 0 and fe3 == 0x0c and fm3 == 0x170 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39a0; op2val:0xb3ba; +op3val:0x3170; valaddr_reg:x5; val_offset:2334*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2334*FLEN/8, x9, x1, x4) + +inst_803: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a0 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3ba and fs3 == 0 and fe3 == 0x0c and fm3 == 0x170 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39a0; op2val:0xb3ba; +op3val:0x3170; valaddr_reg:x5; val_offset:2337*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2337*FLEN/8, x9, x1, x4) + +inst_804: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a0 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3ba and fs3 == 0 and fe3 == 0x0c and fm3 == 0x170 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39a0; op2val:0xb3ba; +op3val:0x3170; valaddr_reg:x5; val_offset:2340*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 2340*FLEN/8, x9, x1, x4) + +inst_805: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x378 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x19b and fs3 == 0 and fe3 == 0x0c and fm3 == 0x13d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b78; op2val:0xb19b; +op3val:0x313d; valaddr_reg:x5; val_offset:2343*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 2343*FLEN/8, x9, x1, x4) + +inst_806: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x378 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x19b and fs3 == 0 and fe3 == 0x0c and fm3 == 0x13d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b78; op2val:0xb19b; +op3val:0x313d; valaddr_reg:x5; val_offset:2346*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2346*FLEN/8, x9, x1, x4) + +inst_807: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x378 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x19b and fs3 == 0 and fe3 == 0x0c and fm3 == 0x13d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b78; op2val:0xb19b; +op3val:0x313d; valaddr_reg:x5; val_offset:2349*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2349*FLEN/8, x9, x1, x4) + +inst_808: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x378 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x19b and fs3 == 0 and fe3 == 0x0c and fm3 == 0x13d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b78; op2val:0xb19b; +op3val:0x313d; valaddr_reg:x5; val_offset:2352*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2352*FLEN/8, x9, x1, x4) + +inst_809: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x378 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x19b and fs3 == 0 and fe3 == 0x0c and fm3 == 0x13d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b78; op2val:0xb19b; +op3val:0x313d; valaddr_reg:x5; val_offset:2355*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 2355*FLEN/8, x9, x1, x4) + +inst_810: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0e3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x36d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x089 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34e3; op2val:0xbf6d; +op3val:0x3889; valaddr_reg:x5; val_offset:2358*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 2358*FLEN/8, x9, x1, x4) + +inst_811: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0e3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x36d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x089 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34e3; op2val:0xbf6d; +op3val:0x3889; valaddr_reg:x5; val_offset:2361*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2361*FLEN/8, x9, x1, x4) + +inst_812: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0e3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x36d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x089 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34e3; op2val:0xbf6d; +op3val:0x3889; valaddr_reg:x5; val_offset:2364*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2364*FLEN/8, x9, x1, x4) + +inst_813: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0e3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x36d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x089 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34e3; op2val:0xbf6d; +op3val:0x3889; valaddr_reg:x5; val_offset:2367*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2367*FLEN/8, x9, x1, x4) + +inst_814: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0e3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x36d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x089 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34e3; op2val:0xbf6d; +op3val:0x3889; valaddr_reg:x5; val_offset:2370*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 2370*FLEN/8, x9, x1, x4) + +inst_815: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1b5 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0ea and fs3 == 0 and fe3 == 0x0c and fm3 == 0x304 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39b5; op2val:0xb4ea; +op3val:0x3304; valaddr_reg:x5; val_offset:2373*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 2373*FLEN/8, x9, x1, x4) + +inst_816: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1b5 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0ea and fs3 == 0 and fe3 == 0x0c and fm3 == 0x304 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39b5; op2val:0xb4ea; +op3val:0x3304; valaddr_reg:x5; val_offset:2376*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2376*FLEN/8, x9, x1, x4) + +inst_817: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1b5 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0ea and fs3 == 0 and fe3 == 0x0c and fm3 == 0x304 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39b5; op2val:0xb4ea; +op3val:0x3304; valaddr_reg:x5; val_offset:2379*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2379*FLEN/8, x9, x1, x4) + +inst_818: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1b5 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0ea and fs3 == 0 and fe3 == 0x0c and fm3 == 0x304 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39b5; op2val:0xb4ea; +op3val:0x3304; valaddr_reg:x5; val_offset:2382*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2382*FLEN/8, x9, x1, x4) + +inst_819: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1b5 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0ea and fs3 == 0 and fe3 == 0x0c and fm3 == 0x304 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39b5; op2val:0xb4ea; +op3val:0x3304; valaddr_reg:x5; val_offset:2385*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 2385*FLEN/8, x9, x1, x4) + +inst_820: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1b8 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0cb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2db and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2db8; op2val:0xc8cb; +op3val:0x3adb; valaddr_reg:x5; val_offset:2388*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 2388*FLEN/8, x9, x1, x4) + +inst_821: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1b8 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0cb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2db and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2db8; op2val:0xc8cb; +op3val:0x3adb; valaddr_reg:x5; val_offset:2391*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2391*FLEN/8, x9, x1, x4) + +inst_822: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1b8 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0cb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2db and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2db8; op2val:0xc8cb; +op3val:0x3adb; valaddr_reg:x5; val_offset:2394*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2394*FLEN/8, x9, x1, x4) + +inst_823: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1b8 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0cb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2db and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2db8; op2val:0xc8cb; +op3val:0x3adb; valaddr_reg:x5; val_offset:2397*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2397*FLEN/8, x9, x1, x4) + +inst_824: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1b8 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0cb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2db and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2db8; op2val:0xc8cb; +op3val:0x3adb; valaddr_reg:x5; val_offset:2400*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 2400*FLEN/8, x9, x1, x4) + +inst_825: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2ea and fs3 == 0 and fe3 == 0x0d and fm3 == 0x337 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x382c; op2val:0xbaea; +op3val:0x3737; valaddr_reg:x5; val_offset:2403*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 2403*FLEN/8, x9, x1, x4) + +inst_826: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2ea and fs3 == 0 and fe3 == 0x0d and fm3 == 0x337 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x382c; op2val:0xbaea; +op3val:0x3737; valaddr_reg:x5; val_offset:2406*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2406*FLEN/8, x9, x1, x4) + +inst_827: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2ea and fs3 == 0 and fe3 == 0x0d and fm3 == 0x337 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x382c; op2val:0xbaea; +op3val:0x3737; valaddr_reg:x5; val_offset:2409*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2409*FLEN/8, x9, x1, x4) + +inst_828: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2ea and fs3 == 0 and fe3 == 0x0d and fm3 == 0x337 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x382c; op2val:0xbaea; +op3val:0x3737; valaddr_reg:x5; val_offset:2412*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2412*FLEN/8, x9, x1, x4) + +inst_829: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2ea and fs3 == 0 and fe3 == 0x0d and fm3 == 0x337 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x382c; op2val:0xbaea; +op3val:0x3737; valaddr_reg:x5; val_offset:2415*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 2415*FLEN/8, x9, x1, x4) + +inst_830: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x004 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x154 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x15a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3804; op2val:0xbd54; +op3val:0x395a; valaddr_reg:x5; val_offset:2418*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 2418*FLEN/8, x9, x1, x4) + +inst_831: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x004 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x154 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x15a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3804; op2val:0xbd54; +op3val:0x395a; valaddr_reg:x5; val_offset:2421*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2421*FLEN/8, x9, x1, x4) + +inst_832: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x004 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x154 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x15a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3804; op2val:0xbd54; +op3val:0x395a; valaddr_reg:x5; val_offset:2424*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2424*FLEN/8, x9, x1, x4) + +inst_833: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x004 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x154 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x15a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3804; op2val:0xbd54; +op3val:0x395a; valaddr_reg:x5; val_offset:2427*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2427*FLEN/8, x9, x1, x4) + +inst_834: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x004 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x154 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x15a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3804; op2val:0xbd54; +op3val:0x395a; valaddr_reg:x5; val_offset:2430*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 2430*FLEN/8, x9, x1, x4) + +inst_835: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2c5 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3d3 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2a0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ac5; op2val:0xb7d3; +op3val:0x36a0; valaddr_reg:x5; val_offset:2433*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 2433*FLEN/8, x9, x1, x4) + +inst_836: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2c5 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3d3 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2a0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ac5; op2val:0xb7d3; +op3val:0x36a0; valaddr_reg:x5; val_offset:2436*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2436*FLEN/8, x9, x1, x4) + +inst_837: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2c5 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3d3 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2a0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ac5; op2val:0xb7d3; +op3val:0x36a0; valaddr_reg:x5; val_offset:2439*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2439*FLEN/8, x9, x1, x4) + +inst_838: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2c5 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3d3 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2a0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ac5; op2val:0xb7d3; +op3val:0x36a0; valaddr_reg:x5; val_offset:2442*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2442*FLEN/8, x9, x1, x4) + +inst_839: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2c5 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3d3 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2a0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ac5; op2val:0xb7d3; +op3val:0x36a0; valaddr_reg:x5; val_offset:2445*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 2445*FLEN/8, x9, x1, x4) + +inst_840: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x205 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0f2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x373 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3205; op2val:0xc4f2; +op3val:0x3b73; valaddr_reg:x5; val_offset:2448*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 2448*FLEN/8, x9, x1, x4) + +inst_841: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x205 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0f2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x373 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3205; op2val:0xc4f2; +op3val:0x3b73; valaddr_reg:x5; val_offset:2451*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2451*FLEN/8, x9, x1, x4) + +inst_842: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x205 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0f2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x373 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3205; op2val:0xc4f2; +op3val:0x3b73; valaddr_reg:x5; val_offset:2454*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2454*FLEN/8, x9, x1, x4) + +inst_843: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x205 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0f2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x373 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3205; op2val:0xc4f2; +op3val:0x3b73; valaddr_reg:x5; val_offset:2457*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2457*FLEN/8, x9, x1, x4) + +inst_844: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x205 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0f2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x373 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3205; op2val:0xc4f2; +op3val:0x3b73; valaddr_reg:x5; val_offset:2460*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 2460*FLEN/8, x9, x1, x4) + +inst_845: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x228 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x37f and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1c6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a28; op2val:0xb37f; +op3val:0x31c6; valaddr_reg:x5; val_offset:2463*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 2463*FLEN/8, x9, x1, x4) + +inst_846: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x228 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x37f and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1c6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a28; op2val:0xb37f; +op3val:0x31c6; valaddr_reg:x5; val_offset:2466*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2466*FLEN/8, x9, x1, x4) + +inst_847: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x228 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x37f and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1c6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a28; op2val:0xb37f; +op3val:0x31c6; valaddr_reg:x5; val_offset:2469*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2469*FLEN/8, x9, x1, x4) + +inst_848: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x228 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x37f and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1c6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a28; op2val:0xb37f; +op3val:0x31c6; valaddr_reg:x5; val_offset:2472*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2472*FLEN/8, x9, x1, x4) + +inst_849: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x228 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x37f and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1c6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a28; op2val:0xb37f; +op3val:0x31c6; valaddr_reg:x5; val_offset:2475*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 2475*FLEN/8, x9, x1, x4) + +inst_850: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2aa and fs2 == 1 and fe2 == 0x0f and fm2 == 0x275 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x162 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32aa; op2val:0xbe75; +op3val:0x3562; valaddr_reg:x5; val_offset:2478*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 2478*FLEN/8, x9, x1, x4) + +inst_851: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2aa and fs2 == 1 and fe2 == 0x0f and fm2 == 0x275 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x162 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32aa; op2val:0xbe75; +op3val:0x3562; valaddr_reg:x5; val_offset:2481*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2481*FLEN/8, x9, x1, x4) + +inst_852: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2aa and fs2 == 1 and fe2 == 0x0f and fm2 == 0x275 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x162 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32aa; op2val:0xbe75; +op3val:0x3562; valaddr_reg:x5; val_offset:2484*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2484*FLEN/8, x9, x1, x4) + +inst_853: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2aa and fs2 == 1 and fe2 == 0x0f and fm2 == 0x275 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x162 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32aa; op2val:0xbe75; +op3val:0x3562; valaddr_reg:x5; val_offset:2487*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2487*FLEN/8, x9, x1, x4) + +inst_854: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2aa and fs2 == 1 and fe2 == 0x0f and fm2 == 0x275 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x162 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32aa; op2val:0xbe75; +op3val:0x3562; valaddr_reg:x5; val_offset:2490*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 2490*FLEN/8, x9, x1, x4) + +inst_855: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3cb and fs2 == 1 and fe2 == 0x0d and fm2 == 0x08d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x070 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bcb; op2val:0xb48d; +op3val:0x3470; valaddr_reg:x5; val_offset:2493*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 2493*FLEN/8, x9, x1, x4) + +inst_856: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3cb and fs2 == 1 and fe2 == 0x0d and fm2 == 0x08d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x070 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bcb; op2val:0xb48d; +op3val:0x3470; valaddr_reg:x5; val_offset:2496*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2496*FLEN/8, x9, x1, x4) + +inst_857: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3cb and fs2 == 1 and fe2 == 0x0d and fm2 == 0x08d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x070 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bcb; op2val:0xb48d; +op3val:0x3470; valaddr_reg:x5; val_offset:2499*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2499*FLEN/8, x9, x1, x4) + +inst_858: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3cb and fs2 == 1 and fe2 == 0x0d and fm2 == 0x08d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x070 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bcb; op2val:0xb48d; +op3val:0x3470; valaddr_reg:x5; val_offset:2502*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2502*FLEN/8, x9, x1, x4) + +inst_859: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3cb and fs2 == 1 and fe2 == 0x0d and fm2 == 0x08d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x070 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bcb; op2val:0xb48d; +op3val:0x3470; valaddr_reg:x5; val_offset:2505*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 2505*FLEN/8, x9, x1, x4) + +inst_860: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x179 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x0fc and fs3 == 0 and fe3 == 0x05 and fm3 == 0x317 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2579; op2val:0xacfc; +op3val:0x1717; valaddr_reg:x5; val_offset:2508*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 2508*FLEN/8, x9, x1, x4) + +inst_861: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x179 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x0fc and fs3 == 0 and fe3 == 0x05 and fm3 == 0x317 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2579; op2val:0xacfc; +op3val:0x1717; valaddr_reg:x5; val_offset:2511*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2511*FLEN/8, x9, x1, x4) + +inst_862: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x179 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x0fc and fs3 == 0 and fe3 == 0x05 and fm3 == 0x317 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2579; op2val:0xacfc; +op3val:0x1717; valaddr_reg:x5; val_offset:2514*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2514*FLEN/8, x9, x1, x4) + +inst_863: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x179 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x0fc and fs3 == 0 and fe3 == 0x05 and fm3 == 0x317 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2579; op2val:0xacfc; +op3val:0x1717; valaddr_reg:x5; val_offset:2517*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2517*FLEN/8, x9, x1, x4) + +inst_864: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x179 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x0fc and fs3 == 0 and fe3 == 0x05 and fm3 == 0x317 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2579; op2val:0xacfc; +op3val:0x1717; valaddr_reg:x5; val_offset:2520*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 2520*FLEN/8, x9, x1, x4) + +inst_865: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0c7 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x25d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x39b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34c7; op2val:0xc25d; +op3val:0x3b9b; valaddr_reg:x5; val_offset:2523*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 2523*FLEN/8, x9, x1, x4) + +inst_866: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0c7 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x25d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x39b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34c7; op2val:0xc25d; +op3val:0x3b9b; valaddr_reg:x5; val_offset:2526*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2526*FLEN/8, x9, x1, x4) + +inst_867: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0c7 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x25d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x39b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34c7; op2val:0xc25d; +op3val:0x3b9b; valaddr_reg:x5; val_offset:2529*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2529*FLEN/8, x9, x1, x4) + +inst_868: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0c7 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x25d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x39b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34c7; op2val:0xc25d; +op3val:0x3b9b; valaddr_reg:x5; val_offset:2532*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2532*FLEN/8, x9, x1, x4) + +inst_869: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0c7 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x25d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x39b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34c7; op2val:0xc25d; +op3val:0x3b9b; valaddr_reg:x5; val_offset:2535*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 2535*FLEN/8, x9, x1, x4) + +inst_870: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x10e and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0f1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x23f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x310e; op2val:0xc4f1; +op3val:0x3a3f; valaddr_reg:x5; val_offset:2538*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 2538*FLEN/8, x9, x1, x4) + +inst_871: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x10e and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0f1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x23f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x310e; op2val:0xc4f1; +op3val:0x3a3f; valaddr_reg:x5; val_offset:2541*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2541*FLEN/8, x9, x1, x4) + +inst_872: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x10e and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0f1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x23f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x310e; op2val:0xc4f1; +op3val:0x3a3f; valaddr_reg:x5; val_offset:2544*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2544*FLEN/8, x9, x1, x4) + +inst_873: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x10e and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0f1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x23f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x310e; op2val:0xc4f1; +op3val:0x3a3f; valaddr_reg:x5; val_offset:2547*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2547*FLEN/8, x9, x1, x4) + +inst_874: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x10e and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0f1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x23f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x310e; op2val:0xc4f1; +op3val:0x3a3f; valaddr_reg:x5; val_offset:2550*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 2550*FLEN/8, x9, x1, x4) + +inst_875: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ab and fs2 == 1 and fe2 == 0x0c and fm2 == 0x050 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x21e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35ab; op2val:0xb050; +op3val:0x2a1e; valaddr_reg:x5; val_offset:2553*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 2553*FLEN/8, x9, x1, x4) + +inst_876: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ab and fs2 == 1 and fe2 == 0x0c and fm2 == 0x050 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x21e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35ab; op2val:0xb050; +op3val:0x2a1e; valaddr_reg:x5; val_offset:2556*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2556*FLEN/8, x9, x1, x4) + +inst_877: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ab and fs2 == 1 and fe2 == 0x0c and fm2 == 0x050 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x21e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35ab; op2val:0xb050; +op3val:0x2a1e; valaddr_reg:x5; val_offset:2559*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2559*FLEN/8, x9, x1, x4) + +inst_878: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ab and fs2 == 1 and fe2 == 0x0c and fm2 == 0x050 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x21e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35ab; op2val:0xb050; +op3val:0x2a1e; valaddr_reg:x5; val_offset:2562*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2562*FLEN/8, x9, x1, x4) + +inst_879: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ab and fs2 == 1 and fe2 == 0x0c and fm2 == 0x050 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x21e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35ab; op2val:0xb050; +op3val:0x2a1e; valaddr_reg:x5; val_offset:2565*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 2565*FLEN/8, x9, x1, x4) + +inst_880: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x09a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x204 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ec and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x349a; op2val:0xc204; +op3val:0x3aec; valaddr_reg:x5; val_offset:2568*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 2568*FLEN/8, x9, x1, x4) + +inst_881: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x09a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x204 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ec and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x349a; op2val:0xc204; +op3val:0x3aec; valaddr_reg:x5; val_offset:2571*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2571*FLEN/8, x9, x1, x4) + +inst_882: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x09a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x204 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ec and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x349a; op2val:0xc204; +op3val:0x3aec; valaddr_reg:x5; val_offset:2574*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2574*FLEN/8, x9, x1, x4) + +inst_883: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x09a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x204 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ec and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x349a; op2val:0xc204; +op3val:0x3aec; valaddr_reg:x5; val_offset:2577*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2577*FLEN/8, x9, x1, x4) + +inst_884: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x09a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x204 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ec and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x349a; op2val:0xc204; +op3val:0x3aec; valaddr_reg:x5; val_offset:2580*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 2580*FLEN/8, x9, x1, x4) + +inst_885: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a9 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x36a and fs3 == 0 and fe3 == 0x0b and fm3 == 0x140 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39a9; op2val:0xaf6a; +op3val:0x2d40; valaddr_reg:x5; val_offset:2583*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 2583*FLEN/8, x9, x1, x4) + +inst_886: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a9 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x36a and fs3 == 0 and fe3 == 0x0b and fm3 == 0x140 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39a9; op2val:0xaf6a; +op3val:0x2d40; valaddr_reg:x5; val_offset:2586*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2586*FLEN/8, x9, x1, x4) + +inst_887: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a9 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x36a and fs3 == 0 and fe3 == 0x0b and fm3 == 0x140 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39a9; op2val:0xaf6a; +op3val:0x2d40; valaddr_reg:x5; val_offset:2589*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2589*FLEN/8, x9, x1, x4) + +inst_888: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a9 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x36a and fs3 == 0 and fe3 == 0x0b and fm3 == 0x140 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39a9; op2val:0xaf6a; +op3val:0x2d40; valaddr_reg:x5; val_offset:2592*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2592*FLEN/8, x9, x1, x4) + +inst_889: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a9 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x36a and fs3 == 0 and fe3 == 0x0b and fm3 == 0x140 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39a9; op2val:0xaf6a; +op3val:0x2d40; valaddr_reg:x5; val_offset:2595*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 2595*FLEN/8, x9, x1, x4) + +inst_890: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2cd and fs2 == 1 and fe2 == 0x0d and fm2 == 0x353 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x23b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3acd; op2val:0xb753; +op3val:0x363b; valaddr_reg:x5; val_offset:2598*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 2598*FLEN/8, x9, x1, x4) + +inst_891: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2cd and fs2 == 1 and fe2 == 0x0d and fm2 == 0x353 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x23b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3acd; op2val:0xb753; +op3val:0x363b; valaddr_reg:x5; val_offset:2601*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2601*FLEN/8, x9, x1, x4) + +inst_892: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2cd and fs2 == 1 and fe2 == 0x0d and fm2 == 0x353 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x23b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3acd; op2val:0xb753; +op3val:0x363b; valaddr_reg:x5; val_offset:2604*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2604*FLEN/8, x9, x1, x4) + +inst_893: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2cd and fs2 == 1 and fe2 == 0x0d and fm2 == 0x353 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x23b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3acd; op2val:0xb753; +op3val:0x363b; valaddr_reg:x5; val_offset:2607*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2607*FLEN/8, x9, x1, x4) + +inst_894: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2cd and fs2 == 1 and fe2 == 0x0d and fm2 == 0x353 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x23b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3acd; op2val:0xb753; +op3val:0x363b; valaddr_reg:x5; val_offset:2610*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 2610*FLEN/8, x9, x1, x4) + +inst_895: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0b0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1b9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38b0; op2val:0xbdb9; +op3val:0x3ab5; valaddr_reg:x5; val_offset:2613*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 2613*FLEN/8, x9, x1, x4) + +inst_896: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0b0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1b9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38b0; op2val:0xbdb9; +op3val:0x3ab5; valaddr_reg:x5; val_offset:2616*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2616*FLEN/8, x9, x1, x4) + +inst_897: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0b0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1b9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38b0; op2val:0xbdb9; +op3val:0x3ab5; valaddr_reg:x5; val_offset:2619*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2619*FLEN/8, x9, x1, x4) + +inst_898: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0b0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1b9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38b0; op2val:0xbdb9; +op3val:0x3ab5; valaddr_reg:x5; val_offset:2622*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2622*FLEN/8, x9, x1, x4) + +inst_899: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0b0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1b9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38b0; op2val:0xbdb9; +op3val:0x3ab5; valaddr_reg:x5; val_offset:2625*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 2625*FLEN/8, x9, x1, x4) + +inst_900: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x20a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x110 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3a6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x360a; op2val:0xc110; +op3val:0x3ba6; valaddr_reg:x5; val_offset:2628*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 2628*FLEN/8, x9, x1, x4) + +inst_901: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x20a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x110 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3a6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x360a; op2val:0xc110; +op3val:0x3ba6; valaddr_reg:x5; val_offset:2631*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2631*FLEN/8, x9, x1, x4) + +inst_902: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x20a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x110 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3a6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x360a; op2val:0xc110; +op3val:0x3ba6; valaddr_reg:x5; val_offset:2634*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2634*FLEN/8, x9, x1, x4) + +inst_903: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x20a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x110 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3a6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x360a; op2val:0xc110; +op3val:0x3ba6; valaddr_reg:x5; val_offset:2637*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2637*FLEN/8, x9, x1, x4) + +inst_904: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x20a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x110 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3a6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x360a; op2val:0xc110; +op3val:0x3ba6; valaddr_reg:x5; val_offset:2640*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 2640*FLEN/8, x9, x1, x4) + +inst_905: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x322 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x191 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0f7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b22; op2val:0xb991; +op3val:0x38f7; valaddr_reg:x5; val_offset:2643*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 2643*FLEN/8, x9, x1, x4) + +inst_906: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x322 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x191 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0f7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b22; op2val:0xb991; +op3val:0x38f7; valaddr_reg:x5; val_offset:2646*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2646*FLEN/8, x9, x1, x4) + +inst_907: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x322 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x191 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0f7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b22; op2val:0xb991; +op3val:0x38f7; valaddr_reg:x5; val_offset:2649*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2649*FLEN/8, x9, x1, x4) + +inst_908: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x322 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x191 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0f7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b22; op2val:0xb991; +op3val:0x38f7; valaddr_reg:x5; val_offset:2652*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2652*FLEN/8, x9, x1, x4) + +inst_909: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x322 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x191 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0f7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b22; op2val:0xb991; +op3val:0x38f7; valaddr_reg:x5; val_offset:2655*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 2655*FLEN/8, x9, x1, x4) + +inst_910: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x00f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x38a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b6c; op2val:0xbc0f; +op3val:0x3b8a; valaddr_reg:x5; val_offset:2658*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 2658*FLEN/8, x9, x1, x4) + +inst_911: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x00f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x38a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b6c; op2val:0xbc0f; +op3val:0x3b8a; valaddr_reg:x5; val_offset:2661*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2661*FLEN/8, x9, x1, x4) + +inst_912: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x00f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x38a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b6c; op2val:0xbc0f; +op3val:0x3b8a; valaddr_reg:x5; val_offset:2664*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2664*FLEN/8, x9, x1, x4) + +inst_913: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x00f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x38a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b6c; op2val:0xbc0f; +op3val:0x3b8a; valaddr_reg:x5; val_offset:2667*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2667*FLEN/8, x9, x1, x4) + +inst_914: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x00f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x38a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b6c; op2val:0xbc0f; +op3val:0x3b8a; valaddr_reg:x5; val_offset:2670*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 2670*FLEN/8, x9, x1, x4) + +inst_915: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2cb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0da and fs3 == 0 and fe3 == 0x0d and fm3 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36cb; op2val:0xb8da; +op3val:0x341f; valaddr_reg:x5; val_offset:2673*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 2673*FLEN/8, x9, x1, x4) + +inst_916: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2cb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0da and fs3 == 0 and fe3 == 0x0d and fm3 == 0x01f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36cb; op2val:0xb8da; +op3val:0x341f; valaddr_reg:x5; val_offset:2676*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2676*FLEN/8, x9, x1, x4) + +inst_917: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2cb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0da and fs3 == 0 and fe3 == 0x0d and fm3 == 0x01f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36cb; op2val:0xb8da; +op3val:0x341f; valaddr_reg:x5; val_offset:2679*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2679*FLEN/8, x9, x1, x4) + +inst_918: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2cb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0da and fs3 == 0 and fe3 == 0x0d and fm3 == 0x01f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36cb; op2val:0xb8da; +op3val:0x341f; valaddr_reg:x5; val_offset:2682*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2682*FLEN/8, x9, x1, x4) + +inst_919: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2cb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0da and fs3 == 0 and fe3 == 0x0d and fm3 == 0x01f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36cb; op2val:0xb8da; +op3val:0x341f; valaddr_reg:x5; val_offset:2685*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 2685*FLEN/8, x9, x1, x4) + +inst_920: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3c8 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x31e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ec and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2fc8; op2val:0xc71e; +op3val:0x3aec; valaddr_reg:x5; val_offset:2688*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 2688*FLEN/8, x9, x1, x4) + +inst_921: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3c8 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x31e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ec and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2fc8; op2val:0xc71e; +op3val:0x3aec; valaddr_reg:x5; val_offset:2691*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2691*FLEN/8, x9, x1, x4) + +inst_922: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3c8 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x31e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ec and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2fc8; op2val:0xc71e; +op3val:0x3aec; valaddr_reg:x5; val_offset:2694*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2694*FLEN/8, x9, x1, x4) + +inst_923: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3c8 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x31e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ec and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2fc8; op2val:0xc71e; +op3val:0x3aec; valaddr_reg:x5; val_offset:2697*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2697*FLEN/8, x9, x1, x4) + +inst_924: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3c8 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x31e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ec and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2fc8; op2val:0xc71e; +op3val:0x3aec; valaddr_reg:x5; val_offset:2700*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 2700*FLEN/8, x9, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_8) + +inst_925: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x08b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0d2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x17b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x388b; op2val:0xbcd2; +op3val:0x397b; valaddr_reg:x5; val_offset:2703*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 2703*FLEN/8, x9, x1, x4) + +inst_926: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x08b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0d2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x17b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x388b; op2val:0xbcd2; +op3val:0x397b; valaddr_reg:x5; val_offset:2706*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2706*FLEN/8, x9, x1, x4) + +inst_927: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x08b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0d2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x17b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x388b; op2val:0xbcd2; +op3val:0x397b; valaddr_reg:x5; val_offset:2709*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2709*FLEN/8, x9, x1, x4) + +inst_928: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x08b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0d2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x17b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x388b; op2val:0xbcd2; +op3val:0x397b; valaddr_reg:x5; val_offset:2712*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2712*FLEN/8, x9, x1, x4) + +inst_929: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x08b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0d2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x17b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x388b; op2val:0xbcd2; +op3val:0x397b; valaddr_reg:x5; val_offset:2715*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 2715*FLEN/8, x9, x1, x4) + +inst_930: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x265 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x11b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x015 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3665; op2val:0xbd1b; +op3val:0x3815; valaddr_reg:x5; val_offset:2718*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 2718*FLEN/8, x9, x1, x4) + +inst_931: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x265 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x11b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x015 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3665; op2val:0xbd1b; +op3val:0x3815; valaddr_reg:x5; val_offset:2721*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2721*FLEN/8, x9, x1, x4) + +inst_932: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x265 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x11b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x015 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3665; op2val:0xbd1b; +op3val:0x3815; valaddr_reg:x5; val_offset:2724*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2724*FLEN/8, x9, x1, x4) + +inst_933: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x265 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x11b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x015 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3665; op2val:0xbd1b; +op3val:0x3815; valaddr_reg:x5; val_offset:2727*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2727*FLEN/8, x9, x1, x4) + +inst_934: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x265 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x11b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x015 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3665; op2val:0xbd1b; +op3val:0x3815; valaddr_reg:x5; val_offset:2730*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 2730*FLEN/8, x9, x1, x4) + +inst_935: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x115 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x101 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2be0; op2val:0xc915; +op3val:0x3901; valaddr_reg:x5; val_offset:2733*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 2733*FLEN/8, x9, x1, x4) + +inst_936: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x115 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x101 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2be0; op2val:0xc915; +op3val:0x3901; valaddr_reg:x5; val_offset:2736*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2736*FLEN/8, x9, x1, x4) + +inst_937: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x115 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x101 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2be0; op2val:0xc915; +op3val:0x3901; valaddr_reg:x5; val_offset:2739*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2739*FLEN/8, x9, x1, x4) + +inst_938: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x115 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x101 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2be0; op2val:0xc915; +op3val:0x3901; valaddr_reg:x5; val_offset:2742*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2742*FLEN/8, x9, x1, x4) + +inst_939: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x115 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x101 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2be0; op2val:0xc915; +op3val:0x3901; valaddr_reg:x5; val_offset:2745*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 2745*FLEN/8, x9, x1, x4) + +inst_940: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x38d and fs2 == 1 and fe2 == 0x0d and fm2 == 0x120 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0d8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b8d; op2val:0xb520; +op3val:0x34d8; valaddr_reg:x5; val_offset:2748*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 2748*FLEN/8, x9, x1, x4) + +inst_941: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x38d and fs2 == 1 and fe2 == 0x0d and fm2 == 0x120 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0d8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b8d; op2val:0xb520; +op3val:0x34d8; valaddr_reg:x5; val_offset:2751*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2751*FLEN/8, x9, x1, x4) + +inst_942: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x38d and fs2 == 1 and fe2 == 0x0d and fm2 == 0x120 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0d8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b8d; op2val:0xb520; +op3val:0x34d8; valaddr_reg:x5; val_offset:2754*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2754*FLEN/8, x9, x1, x4) + +inst_943: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x38d and fs2 == 1 and fe2 == 0x0d and fm2 == 0x120 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0d8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b8d; op2val:0xb520; +op3val:0x34d8; valaddr_reg:x5; val_offset:2757*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2757*FLEN/8, x9, x1, x4) + +inst_944: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x38d and fs2 == 1 and fe2 == 0x0d and fm2 == 0x120 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0d8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b8d; op2val:0xb520; +op3val:0x34d8; valaddr_reg:x5; val_offset:2760*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 2760*FLEN/8, x9, x1, x4) + +inst_945: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ca and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2f2 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1e6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aca; op2val:0xb6f2; +op3val:0x35e6; valaddr_reg:x5; val_offset:2763*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 2763*FLEN/8, x9, x1, x4) + +inst_946: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ca and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2f2 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1e6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aca; op2val:0xb6f2; +op3val:0x35e6; valaddr_reg:x5; val_offset:2766*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2766*FLEN/8, x9, x1, x4) + +inst_947: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ca and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2f2 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1e6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aca; op2val:0xb6f2; +op3val:0x35e6; valaddr_reg:x5; val_offset:2769*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2769*FLEN/8, x9, x1, x4) + +inst_948: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ca and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2f2 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1e6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aca; op2val:0xb6f2; +op3val:0x35e6; valaddr_reg:x5; val_offset:2772*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2772*FLEN/8, x9, x1, x4) + +inst_949: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ca and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2f2 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1e6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aca; op2val:0xb6f2; +op3val:0x35e6; valaddr_reg:x5; val_offset:2775*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 2775*FLEN/8, x9, x1, x4) + +inst_950: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3e8 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x1cc and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1bc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37e8; op2val:0xb1cc; +op3val:0x2dbc; valaddr_reg:x5; val_offset:2778*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 2778*FLEN/8, x9, x1, x4) + +inst_951: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3e8 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x1cc and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1bc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37e8; op2val:0xb1cc; +op3val:0x2dbc; valaddr_reg:x5; val_offset:2781*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2781*FLEN/8, x9, x1, x4) + +inst_952: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3e8 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x1cc and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1bc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37e8; op2val:0xb1cc; +op3val:0x2dbc; valaddr_reg:x5; val_offset:2784*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2784*FLEN/8, x9, x1, x4) + +inst_953: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3e8 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x1cc and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1bc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37e8; op2val:0xb1cc; +op3val:0x2dbc; valaddr_reg:x5; val_offset:2787*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2787*FLEN/8, x9, x1, x4) + +inst_954: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3e8 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x1cc and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1bc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37e8; op2val:0xb1cc; +op3val:0x2dbc; valaddr_reg:x5; val_offset:2790*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 2790*FLEN/8, x9, x1, x4) + +inst_955: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x31f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2d0 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x211 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x371f; op2val:0xbad0; +op3val:0x3611; valaddr_reg:x5; val_offset:2793*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 2793*FLEN/8, x9, x1, x4) + +inst_956: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x31f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2d0 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x211 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x371f; op2val:0xbad0; +op3val:0x3611; valaddr_reg:x5; val_offset:2796*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2796*FLEN/8, x9, x1, x4) + +inst_957: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x31f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2d0 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x211 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x371f; op2val:0xbad0; +op3val:0x3611; valaddr_reg:x5; val_offset:2799*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2799*FLEN/8, x9, x1, x4) + +inst_958: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x31f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2d0 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x211 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x371f; op2val:0xbad0; +op3val:0x3611; valaddr_reg:x5; val_offset:2802*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2802*FLEN/8, x9, x1, x4) + +inst_959: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x31f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2d0 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x211 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x371f; op2val:0xbad0; +op3val:0x3611; valaddr_reg:x5; val_offset:2805*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 2805*FLEN/8, x9, x1, x4) + +inst_960: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1e4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0de and fs3 == 0 and fe3 == 0x0d and fm3 == 0x32c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39e4; op2val:0xb8de; +op3val:0x372c; valaddr_reg:x5; val_offset:2808*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 2808*FLEN/8, x9, x1, x4) + +inst_961: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1e4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0de and fs3 == 0 and fe3 == 0x0d and fm3 == 0x32c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39e4; op2val:0xb8de; +op3val:0x372c; valaddr_reg:x5; val_offset:2811*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2811*FLEN/8, x9, x1, x4) + +inst_962: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1e4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0de and fs3 == 0 and fe3 == 0x0d and fm3 == 0x32c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39e4; op2val:0xb8de; +op3val:0x372c; valaddr_reg:x5; val_offset:2814*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2814*FLEN/8, x9, x1, x4) + +inst_963: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1e4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0de and fs3 == 0 and fe3 == 0x0d and fm3 == 0x32c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39e4; op2val:0xb8de; +op3val:0x372c; valaddr_reg:x5; val_offset:2817*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2817*FLEN/8, x9, x1, x4) + +inst_964: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1e4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0de and fs3 == 0 and fe3 == 0x0d and fm3 == 0x32c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39e4; op2val:0xb8de; +op3val:0x372c; valaddr_reg:x5; val_offset:2820*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 2820*FLEN/8, x9, x1, x4) + +inst_965: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1f7 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x159 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3fb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39f7; op2val:0xb559; +op3val:0x33fb; valaddr_reg:x5; val_offset:2823*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 2823*FLEN/8, x9, x1, x4) + +inst_966: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1f7 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x159 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3fb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39f7; op2val:0xb559; +op3val:0x33fb; valaddr_reg:x5; val_offset:2826*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2826*FLEN/8, x9, x1, x4) + +inst_967: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1f7 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x159 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3fb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39f7; op2val:0xb559; +op3val:0x33fb; valaddr_reg:x5; val_offset:2829*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2829*FLEN/8, x9, x1, x4) + +inst_968: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1f7 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x159 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3fb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39f7; op2val:0xb559; +op3val:0x33fb; valaddr_reg:x5; val_offset:2832*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2832*FLEN/8, x9, x1, x4) + +inst_969: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1f7 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x159 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3fb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39f7; op2val:0xb559; +op3val:0x33fb; valaddr_reg:x5; val_offset:2835*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 2835*FLEN/8, x9, x1, x4) + +inst_970: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ba and fs2 == 1 and fe2 == 0x0f and fm2 == 0x32c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ee and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37ba; op2val:0xbf2c; +op3val:0x3aee; valaddr_reg:x5; val_offset:2838*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 2838*FLEN/8, x9, x1, x4) + +inst_971: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ba and fs2 == 1 and fe2 == 0x0f and fm2 == 0x32c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ee and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37ba; op2val:0xbf2c; +op3val:0x3aee; valaddr_reg:x5; val_offset:2841*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2841*FLEN/8, x9, x1, x4) + +inst_972: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ba and fs2 == 1 and fe2 == 0x0f and fm2 == 0x32c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ee and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37ba; op2val:0xbf2c; +op3val:0x3aee; valaddr_reg:x5; val_offset:2844*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2844*FLEN/8, x9, x1, x4) + +inst_973: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ba and fs2 == 1 and fe2 == 0x0f and fm2 == 0x32c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ee and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37ba; op2val:0xbf2c; +op3val:0x3aee; valaddr_reg:x5; val_offset:2847*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2847*FLEN/8, x9, x1, x4) + +inst_974: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ba and fs2 == 1 and fe2 == 0x0f and fm2 == 0x32c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ee and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37ba; op2val:0xbf2c; +op3val:0x3aee; valaddr_reg:x5; val_offset:2850*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 2850*FLEN/8, x9, x1, x4) + +inst_975: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x21f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x291 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x107 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a1f; op2val:0xba91; +op3val:0x3907; valaddr_reg:x5; val_offset:2853*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 2853*FLEN/8, x9, x1, x4) + +inst_976: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x21f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x291 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x107 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a1f; op2val:0xba91; +op3val:0x3907; valaddr_reg:x5; val_offset:2856*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2856*FLEN/8, x9, x1, x4) + +inst_977: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x21f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x291 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x107 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a1f; op2val:0xba91; +op3val:0x3907; valaddr_reg:x5; val_offset:2859*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2859*FLEN/8, x9, x1, x4) + +inst_978: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x21f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x291 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x107 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a1f; op2val:0xba91; +op3val:0x3907; valaddr_reg:x5; val_offset:2862*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2862*FLEN/8, x9, x1, x4) + +inst_979: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x21f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x291 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x107 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a1f; op2val:0xba91; +op3val:0x3907; valaddr_reg:x5; val_offset:2865*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 2865*FLEN/8, x9, x1, x4) + +inst_980: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x036 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x23b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x290 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3436; op2val:0xc23b; +op3val:0x3a90; valaddr_reg:x5; val_offset:2868*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 2868*FLEN/8, x9, x1, x4) + +inst_981: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x036 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x23b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x290 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3436; op2val:0xc23b; +op3val:0x3a90; valaddr_reg:x5; val_offset:2871*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2871*FLEN/8, x9, x1, x4) + +inst_982: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x036 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x23b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x290 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3436; op2val:0xc23b; +op3val:0x3a90; valaddr_reg:x5; val_offset:2874*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2874*FLEN/8, x9, x1, x4) + +inst_983: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x036 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x23b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x290 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3436; op2val:0xc23b; +op3val:0x3a90; valaddr_reg:x5; val_offset:2877*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2877*FLEN/8, x9, x1, x4) + +inst_984: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x036 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x23b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x290 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3436; op2val:0xc23b; +op3val:0x3a90; valaddr_reg:x5; val_offset:2880*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 2880*FLEN/8, x9, x1, x4) + +inst_985: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x096 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0cf and fs3 == 0 and fe3 == 0x0d and fm3 == 0x185 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3496; op2val:0xbccf; +op3val:0x3585; valaddr_reg:x5; val_offset:2883*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 2883*FLEN/8, x9, x1, x4) + +inst_986: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x096 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0cf and fs3 == 0 and fe3 == 0x0d and fm3 == 0x185 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3496; op2val:0xbccf; +op3val:0x3585; valaddr_reg:x5; val_offset:2886*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2886*FLEN/8, x9, x1, x4) + +inst_987: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x096 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0cf and fs3 == 0 and fe3 == 0x0d and fm3 == 0x185 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3496; op2val:0xbccf; +op3val:0x3585; valaddr_reg:x5; val_offset:2889*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2889*FLEN/8, x9, x1, x4) + +inst_988: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x096 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0cf and fs3 == 0 and fe3 == 0x0d and fm3 == 0x185 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3496; op2val:0xbccf; +op3val:0x3585; valaddr_reg:x5; val_offset:2892*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2892*FLEN/8, x9, x1, x4) + +inst_989: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x096 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0cf and fs3 == 0 and fe3 == 0x0d and fm3 == 0x185 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3496; op2val:0xbccf; +op3val:0x3585; valaddr_reg:x5; val_offset:2895*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 2895*FLEN/8, x9, x1, x4) + +inst_990: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x351 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1ce and fs3 == 0 and fe3 == 0x0d and fm3 == 0x150 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b51; op2val:0xb5ce; +op3val:0x3550; valaddr_reg:x5; val_offset:2898*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 2898*FLEN/8, x9, x1, x4) + +inst_991: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x351 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1ce and fs3 == 0 and fe3 == 0x0d and fm3 == 0x150 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b51; op2val:0xb5ce; +op3val:0x3550; valaddr_reg:x5; val_offset:2901*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2901*FLEN/8, x9, x1, x4) + +inst_992: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x351 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1ce and fs3 == 0 and fe3 == 0x0d and fm3 == 0x150 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b51; op2val:0xb5ce; +op3val:0x3550; valaddr_reg:x5; val_offset:2904*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2904*FLEN/8, x9, x1, x4) + +inst_993: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x351 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1ce and fs3 == 0 and fe3 == 0x0d and fm3 == 0x150 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b51; op2val:0xb5ce; +op3val:0x3550; valaddr_reg:x5; val_offset:2907*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2907*FLEN/8, x9, x1, x4) + +inst_994: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x351 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1ce and fs3 == 0 and fe3 == 0x0d and fm3 == 0x150 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b51; op2val:0xb5ce; +op3val:0x3550; valaddr_reg:x5; val_offset:2910*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 2910*FLEN/8, x9, x1, x4) + +inst_995: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x345 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b45; op2val:0xbbb4; +op3val:0x3b00; valaddr_reg:x5; val_offset:2913*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 2913*FLEN/8, x9, x1, x4) + +inst_996: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x345 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x300 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b45; op2val:0xbbb4; +op3val:0x3b00; valaddr_reg:x5; val_offset:2916*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2916*FLEN/8, x9, x1, x4) + +inst_997: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x345 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x300 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b45; op2val:0xbbb4; +op3val:0x3b00; valaddr_reg:x5; val_offset:2919*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2919*FLEN/8, x9, x1, x4) + +inst_998: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x345 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x300 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b45; op2val:0xbbb4; +op3val:0x3b00; valaddr_reg:x5; val_offset:2922*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2922*FLEN/8, x9, x1, x4) + +inst_999: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x345 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x300 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b45; op2val:0xbbb4; +op3val:0x3b00; valaddr_reg:x5; val_offset:2925*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 2925*FLEN/8, x9, x1, x4) + +inst_1000: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x27f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x37f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x217 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x367f; op2val:0xbf7f; +op3val:0x3a17; valaddr_reg:x5; val_offset:2928*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 2928*FLEN/8, x9, x1, x4) + +inst_1001: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x27f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x37f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x217 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x367f; op2val:0xbf7f; +op3val:0x3a17; valaddr_reg:x5; val_offset:2931*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2931*FLEN/8, x9, x1, x4) + +inst_1002: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x27f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x37f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x217 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x367f; op2val:0xbf7f; +op3val:0x3a17; valaddr_reg:x5; val_offset:2934*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2934*FLEN/8, x9, x1, x4) + +inst_1003: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x27f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x37f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x217 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x367f; op2val:0xbf7f; +op3val:0x3a17; valaddr_reg:x5; val_offset:2937*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2937*FLEN/8, x9, x1, x4) + +inst_1004: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x27f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x37f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x217 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x367f; op2val:0xbf7f; +op3val:0x3a17; valaddr_reg:x5; val_offset:2940*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 2940*FLEN/8, x9, x1, x4) + +inst_1005: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3e1 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x038 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x028 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2fe1; op2val:0xc438; +op3val:0x3828; valaddr_reg:x5; val_offset:2943*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 2943*FLEN/8, x9, x1, x4) + +inst_1006: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3e1 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x038 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x028 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2fe1; op2val:0xc438; +op3val:0x3828; valaddr_reg:x5; val_offset:2946*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2946*FLEN/8, x9, x1, x4) + +inst_1007: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3e1 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x038 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x028 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2fe1; op2val:0xc438; +op3val:0x3828; valaddr_reg:x5; val_offset:2949*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2949*FLEN/8, x9, x1, x4) + +inst_1008: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3e1 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x038 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x028 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2fe1; op2val:0xc438; +op3val:0x3828; valaddr_reg:x5; val_offset:2952*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2952*FLEN/8, x9, x1, x4) + +inst_1009: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3e1 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x038 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x028 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2fe1; op2val:0xc438; +op3val:0x3828; valaddr_reg:x5; val_offset:2955*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 2955*FLEN/8, x9, x1, x4) + +inst_1010: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x169 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0cf and fs3 == 0 and fe3 == 0x0c and fm3 == 0x283 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3969; op2val:0xb4cf; +op3val:0x3283; valaddr_reg:x5; val_offset:2958*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 2958*FLEN/8, x9, x1, x4) + +inst_1011: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x169 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0cf and fs3 == 0 and fe3 == 0x0c and fm3 == 0x283 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3969; op2val:0xb4cf; +op3val:0x3283; valaddr_reg:x5; val_offset:2961*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2961*FLEN/8, x9, x1, x4) + +inst_1012: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x169 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0cf and fs3 == 0 and fe3 == 0x0c and fm3 == 0x283 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3969; op2val:0xb4cf; +op3val:0x3283; valaddr_reg:x5; val_offset:2964*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2964*FLEN/8, x9, x1, x4) + +inst_1013: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x169 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0cf and fs3 == 0 and fe3 == 0x0c and fm3 == 0x283 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3969; op2val:0xb4cf; +op3val:0x3283; valaddr_reg:x5; val_offset:2967*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2967*FLEN/8, x9, x1, x4) + +inst_1014: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x169 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0cf and fs3 == 0 and fe3 == 0x0c and fm3 == 0x283 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3969; op2val:0xb4cf; +op3val:0x3283; valaddr_reg:x5; val_offset:2970*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 2970*FLEN/8, x9, x1, x4) + +inst_1015: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c3 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x088 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x066 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bc3; op2val:0xb488; +op3val:0x3466; valaddr_reg:x5; val_offset:2973*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 2973*FLEN/8, x9, x1, x4) + +inst_1016: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c3 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x088 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x066 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bc3; op2val:0xb488; +op3val:0x3466; valaddr_reg:x5; val_offset:2976*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2976*FLEN/8, x9, x1, x4) + +inst_1017: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c3 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x088 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x066 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bc3; op2val:0xb488; +op3val:0x3466; valaddr_reg:x5; val_offset:2979*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2979*FLEN/8, x9, x1, x4) + +inst_1018: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c3 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x088 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x066 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bc3; op2val:0xb488; +op3val:0x3466; valaddr_reg:x5; val_offset:2982*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2982*FLEN/8, x9, x1, x4) + +inst_1019: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c3 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x088 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x066 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bc3; op2val:0xb488; +op3val:0x3466; valaddr_reg:x5; val_offset:2985*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 2985*FLEN/8, x9, x1, x4) + +inst_1020: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x392 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x32d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2cb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b92; op2val:0xbb2d; +op3val:0x3acb; valaddr_reg:x5; val_offset:2988*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 2988*FLEN/8, x9, x1, x4) + +inst_1021: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x392 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x32d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2cb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b92; op2val:0xbb2d; +op3val:0x3acb; valaddr_reg:x5; val_offset:2991*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 2991*FLEN/8, x9, x1, x4) + +inst_1022: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x392 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x32d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2cb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b92; op2val:0xbb2d; +op3val:0x3acb; valaddr_reg:x5; val_offset:2994*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 2994*FLEN/8, x9, x1, x4) + +inst_1023: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x392 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x32d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2cb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b92; op2val:0xbb2d; +op3val:0x3acb; valaddr_reg:x5; val_offset:2997*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 2997*FLEN/8, x9, x1, x4) + +inst_1024: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x392 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x32d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2cb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b92; op2val:0xbb2d; +op3val:0x3acb; valaddr_reg:x5; val_offset:3000*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3000*FLEN/8, x9, x1, x4) + +inst_1025: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x225 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2a3 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x11a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2a25; op2val:0xc6a3; +op3val:0x351a; valaddr_reg:x5; val_offset:3003*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3003*FLEN/8, x9, x1, x4) + +inst_1026: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x225 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2a3 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x11a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2a25; op2val:0xc6a3; +op3val:0x351a; valaddr_reg:x5; val_offset:3006*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3006*FLEN/8, x9, x1, x4) + +inst_1027: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x225 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2a3 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x11a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2a25; op2val:0xc6a3; +op3val:0x351a; valaddr_reg:x5; val_offset:3009*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3009*FLEN/8, x9, x1, x4) + +inst_1028: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x225 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2a3 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x11a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2a25; op2val:0xc6a3; +op3val:0x351a; valaddr_reg:x5; val_offset:3012*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 3012*FLEN/8, x9, x1, x4) + +inst_1029: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x225 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2a3 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x11a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2a25; op2val:0xc6a3; +op3val:0x351a; valaddr_reg:x5; val_offset:3015*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3015*FLEN/8, x9, x1, x4) + +inst_1030: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x237 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x08c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x312 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a37; op2val:0xbc8c; +op3val:0x3b12; valaddr_reg:x5; val_offset:3018*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3018*FLEN/8, x9, x1, x4) + +inst_1031: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x237 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x08c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x312 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a37; op2val:0xbc8c; +op3val:0x3b12; valaddr_reg:x5; val_offset:3021*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3021*FLEN/8, x9, x1, x4) + +inst_1032: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x237 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x08c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x312 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a37; op2val:0xbc8c; +op3val:0x3b12; valaddr_reg:x5; val_offset:3024*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3024*FLEN/8, x9, x1, x4) + +inst_1033: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x237 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x08c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x312 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a37; op2val:0xbc8c; +op3val:0x3b12; valaddr_reg:x5; val_offset:3027*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 3027*FLEN/8, x9, x1, x4) + +inst_1034: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x237 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x08c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x312 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a37; op2val:0xbc8c; +op3val:0x3b12; valaddr_reg:x5; val_offset:3030*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3030*FLEN/8, x9, x1, x4) + +inst_1035: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x301 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x21e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x15c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2701; op2val:0xca1e; +op3val:0x355c; valaddr_reg:x5; val_offset:3033*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3033*FLEN/8, x9, x1, x4) + +inst_1036: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x301 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x21e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x15c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2701; op2val:0xca1e; +op3val:0x355c; valaddr_reg:x5; val_offset:3036*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3036*FLEN/8, x9, x1, x4) + +inst_1037: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x301 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x21e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x15c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2701; op2val:0xca1e; +op3val:0x355c; valaddr_reg:x5; val_offset:3039*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3039*FLEN/8, x9, x1, x4) + +inst_1038: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x301 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x21e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x15c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2701; op2val:0xca1e; +op3val:0x355c; valaddr_reg:x5; val_offset:3042*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 3042*FLEN/8, x9, x1, x4) + +inst_1039: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x301 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x21e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x15c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2701; op2val:0xca1e; +op3val:0x355c; valaddr_reg:x5; val_offset:3045*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3045*FLEN/8, x9, x1, x4) + +inst_1040: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1be and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0cb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2e1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31be; op2val:0xc4cb; +op3val:0x3ae1; valaddr_reg:x5; val_offset:3048*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3048*FLEN/8, x9, x1, x4) + +inst_1041: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1be and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0cb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2e1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31be; op2val:0xc4cb; +op3val:0x3ae1; valaddr_reg:x5; val_offset:3051*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3051*FLEN/8, x9, x1, x4) + +inst_1042: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1be and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0cb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2e1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31be; op2val:0xc4cb; +op3val:0x3ae1; valaddr_reg:x5; val_offset:3054*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3054*FLEN/8, x9, x1, x4) + +inst_1043: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1be and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0cb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2e1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31be; op2val:0xc4cb; +op3val:0x3ae1; valaddr_reg:x5; val_offset:3057*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 3057*FLEN/8, x9, x1, x4) + +inst_1044: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1be and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0cb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2e1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31be; op2val:0xc4cb; +op3val:0x3ae1; valaddr_reg:x5; val_offset:3060*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3060*FLEN/8, x9, x1, x4) + +inst_1045: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2e1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x12a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3600; op2val:0xbee1; +op3val:0x392a; valaddr_reg:x5; val_offset:3063*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3063*FLEN/8, x9, x1, x4) + +inst_1046: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2e1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x12a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3600; op2val:0xbee1; +op3val:0x392a; valaddr_reg:x5; val_offset:3066*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3066*FLEN/8, x9, x1, x4) + +inst_1047: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2e1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x12a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3600; op2val:0xbee1; +op3val:0x392a; valaddr_reg:x5; val_offset:3069*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3069*FLEN/8, x9, x1, x4) + +inst_1048: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2e1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x12a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3600; op2val:0xbee1; +op3val:0x392a; valaddr_reg:x5; val_offset:3072*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 3072*FLEN/8, x9, x1, x4) + +inst_1049: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2e1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x12a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3600; op2val:0xbee1; +op3val:0x392a; valaddr_reg:x5; val_offset:3075*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3075*FLEN/8, x9, x1, x4) + +inst_1050: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x21e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2f8 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a1e; op2val:0xbaf8; +op3val:0x3955; valaddr_reg:x5; val_offset:3078*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3078*FLEN/8, x9, x1, x4) + +inst_1051: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x21e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2f8 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x155 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a1e; op2val:0xbaf8; +op3val:0x3955; valaddr_reg:x5; val_offset:3081*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3081*FLEN/8, x9, x1, x4) + +inst_1052: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x21e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2f8 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x155 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a1e; op2val:0xbaf8; +op3val:0x3955; valaddr_reg:x5; val_offset:3084*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3084*FLEN/8, x9, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_9) + +inst_1053: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x21e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2f8 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x155 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a1e; op2val:0xbaf8; +op3val:0x3955; valaddr_reg:x5; val_offset:3087*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 3087*FLEN/8, x9, x1, x4) + +inst_1054: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x21e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2f8 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x155 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a1e; op2val:0xbaf8; +op3val:0x3955; valaddr_reg:x5; val_offset:3090*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3090*FLEN/8, x9, x1, x4) + +inst_1055: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x22e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2be and fs3 == 0 and fe3 == 0x0e and fm3 == 0x135 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x362e; op2val:0xbebe; +op3val:0x3935; valaddr_reg:x5; val_offset:3093*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3093*FLEN/8, x9, x1, x4) + +inst_1056: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x22e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2be and fs3 == 0 and fe3 == 0x0e and fm3 == 0x135 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x362e; op2val:0xbebe; +op3val:0x3935; valaddr_reg:x5; val_offset:3096*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3096*FLEN/8, x9, x1, x4) + +inst_1057: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x22e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2be and fs3 == 0 and fe3 == 0x0e and fm3 == 0x135 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x362e; op2val:0xbebe; +op3val:0x3935; valaddr_reg:x5; val_offset:3099*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3099*FLEN/8, x9, x1, x4) + +inst_1058: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x22e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2be and fs3 == 0 and fe3 == 0x0e and fm3 == 0x135 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x362e; op2val:0xbebe; +op3val:0x3935; valaddr_reg:x5; val_offset:3102*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 3102*FLEN/8, x9, x1, x4) + +inst_1059: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x22e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2be and fs3 == 0 and fe3 == 0x0e and fm3 == 0x135 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x362e; op2val:0xbebe; +op3val:0x3935; valaddr_reg:x5; val_offset:3105*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3105*FLEN/8, x9, x1, x4) + +inst_1060: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ea and fs2 == 1 and fe2 == 0x0f and fm2 == 0x19f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2e8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ea; op2val:0xbd9f; +op3val:0x3ae8; valaddr_reg:x5; val_offset:3108*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3108*FLEN/8, x9, x1, x4) + +inst_1061: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ea and fs2 == 1 and fe2 == 0x0f and fm2 == 0x19f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2e8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ea; op2val:0xbd9f; +op3val:0x3ae8; valaddr_reg:x5; val_offset:3111*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3111*FLEN/8, x9, x1, x4) + +inst_1062: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ea and fs2 == 1 and fe2 == 0x0f and fm2 == 0x19f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2e8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ea; op2val:0xbd9f; +op3val:0x3ae8; valaddr_reg:x5; val_offset:3114*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3114*FLEN/8, x9, x1, x4) + +inst_1063: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ea and fs2 == 1 and fe2 == 0x0f and fm2 == 0x19f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2e8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ea; op2val:0xbd9f; +op3val:0x3ae8; valaddr_reg:x5; val_offset:3117*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 3117*FLEN/8, x9, x1, x4) + +inst_1064: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ea and fs2 == 1 and fe2 == 0x0f and fm2 == 0x19f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2e8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ea; op2val:0xbd9f; +op3val:0x3ae8; valaddr_reg:x5; val_offset:3120*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3120*FLEN/8, x9, x1, x4) + +inst_1065: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x168 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x02a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1a2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3168; op2val:0xc02a; +op3val:0x35a2; valaddr_reg:x5; val_offset:3123*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3123*FLEN/8, x9, x1, x4) + +inst_1066: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x168 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x02a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1a2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3168; op2val:0xc02a; +op3val:0x35a2; valaddr_reg:x5; val_offset:3126*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3126*FLEN/8, x9, x1, x4) + +inst_1067: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x168 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x02a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1a2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3168; op2val:0xc02a; +op3val:0x35a2; valaddr_reg:x5; val_offset:3129*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3129*FLEN/8, x9, x1, x4) + +inst_1068: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x168 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x02a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1a2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3168; op2val:0xc02a; +op3val:0x35a2; valaddr_reg:x5; val_offset:3132*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 3132*FLEN/8, x9, x1, x4) + +inst_1069: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x168 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x02a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1a2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3168; op2val:0xc02a; +op3val:0x35a2; valaddr_reg:x5; val_offset:3135*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3135*FLEN/8, x9, x1, x4) + +inst_1070: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x241 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1cb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x088 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3241; op2val:0xc1cb; +op3val:0x3888; valaddr_reg:x5; val_offset:3138*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3138*FLEN/8, x9, x1, x4) + +inst_1071: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x241 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1cb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x088 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3241; op2val:0xc1cb; +op3val:0x3888; valaddr_reg:x5; val_offset:3141*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3141*FLEN/8, x9, x1, x4) + +inst_1072: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x241 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1cb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x088 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3241; op2val:0xc1cb; +op3val:0x3888; valaddr_reg:x5; val_offset:3144*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3144*FLEN/8, x9, x1, x4) + +inst_1073: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x241 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1cb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x088 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3241; op2val:0xc1cb; +op3val:0x3888; valaddr_reg:x5; val_offset:3147*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 3147*FLEN/8, x9, x1, x4) + +inst_1074: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x241 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1cb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x088 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3241; op2val:0xc1cb; +op3val:0x3888; valaddr_reg:x5; val_offset:3150*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3150*FLEN/8, x9, x1, x4) + +inst_1075: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0c0 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x27f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3b8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30c0; op2val:0xc27f; +op3val:0x37b8; valaddr_reg:x5; val_offset:3153*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3153*FLEN/8, x9, x1, x4) + +inst_1076: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0c0 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x27f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3b8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30c0; op2val:0xc27f; +op3val:0x37b8; valaddr_reg:x5; val_offset:3156*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3156*FLEN/8, x9, x1, x4) + +inst_1077: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0c0 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x27f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3b8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30c0; op2val:0xc27f; +op3val:0x37b8; valaddr_reg:x5; val_offset:3159*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3159*FLEN/8, x9, x1, x4) + +inst_1078: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0c0 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x27f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3b8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30c0; op2val:0xc27f; +op3val:0x37b8; valaddr_reg:x5; val_offset:3162*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 3162*FLEN/8, x9, x1, x4) + +inst_1079: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0c0 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x27f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3b8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30c0; op2val:0xc27f; +op3val:0x37b8; valaddr_reg:x5; val_offset:3165*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3165*FLEN/8, x9, x1, x4) + +inst_1080: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x284 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x030 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2d4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3684; op2val:0xbc30; +op3val:0x36d4; valaddr_reg:x5; val_offset:3168*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3168*FLEN/8, x9, x1, x4) + +inst_1081: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x284 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x030 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2d4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3684; op2val:0xbc30; +op3val:0x36d4; valaddr_reg:x5; val_offset:3171*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3171*FLEN/8, x9, x1, x4) + +inst_1082: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x284 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x030 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2d4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3684; op2val:0xbc30; +op3val:0x36d4; valaddr_reg:x5; val_offset:3174*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3174*FLEN/8, x9, x1, x4) + +inst_1083: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x284 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x030 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2d4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3684; op2val:0xbc30; +op3val:0x36d4; valaddr_reg:x5; val_offset:3177*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 3177*FLEN/8, x9, x1, x4) + +inst_1084: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x284 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x030 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2d4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3684; op2val:0xbc30; +op3val:0x36d4; valaddr_reg:x5; val_offset:3180*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3180*FLEN/8, x9, x1, x4) + +inst_1085: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x028 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0a6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0d6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3428; op2val:0xc0a6; +op3val:0x38d6; valaddr_reg:x5; val_offset:3183*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3183*FLEN/8, x9, x1, x4) + +inst_1086: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x028 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0a6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0d6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3428; op2val:0xc0a6; +op3val:0x38d6; valaddr_reg:x5; val_offset:3186*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3186*FLEN/8, x9, x1, x4) + +inst_1087: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x028 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0a6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0d6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3428; op2val:0xc0a6; +op3val:0x38d6; valaddr_reg:x5; val_offset:3189*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3189*FLEN/8, x9, x1, x4) + +inst_1088: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x028 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0a6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0d6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3428; op2val:0xc0a6; +op3val:0x38d6; valaddr_reg:x5; val_offset:3192*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 3192*FLEN/8, x9, x1, x4) + +inst_1089: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x028 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0a6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0d6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3428; op2val:0xc0a6; +op3val:0x38d6; valaddr_reg:x5; val_offset:3195*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3195*FLEN/8, x9, x1, x4) + +inst_1090: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x339 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x048 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3bc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b39; op2val:0xbc48; +op3val:0x3bbc; valaddr_reg:x5; val_offset:3198*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3198*FLEN/8, x9, x1, x4) + +inst_1091: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x339 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x048 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3bc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b39; op2val:0xbc48; +op3val:0x3bbc; valaddr_reg:x5; val_offset:3201*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3201*FLEN/8, x9, x1, x4) + +inst_1092: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x339 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x048 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3bc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b39; op2val:0xbc48; +op3val:0x3bbc; valaddr_reg:x5; val_offset:3204*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3204*FLEN/8, x9, x1, x4) + +inst_1093: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x339 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x048 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3bc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b39; op2val:0xbc48; +op3val:0x3bbc; valaddr_reg:x5; val_offset:3207*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 3207*FLEN/8, x9, x1, x4) + +inst_1094: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x339 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x048 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3bc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b39; op2val:0xbc48; +op3val:0x3bbc; valaddr_reg:x5; val_offset:3210*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3210*FLEN/8, x9, x1, x4) + +inst_1095: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x261 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0d1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3af and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a61; op2val:0xbcd1; +op3val:0x3baf; valaddr_reg:x5; val_offset:3213*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3213*FLEN/8, x9, x1, x4) + +inst_1096: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x261 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0d1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3af and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a61; op2val:0xbcd1; +op3val:0x3baf; valaddr_reg:x5; val_offset:3216*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3216*FLEN/8, x9, x1, x4) + +inst_1097: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x261 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0d1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3af and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a61; op2val:0xbcd1; +op3val:0x3baf; valaddr_reg:x5; val_offset:3219*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3219*FLEN/8, x9, x1, x4) + +inst_1098: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x261 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0d1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3af and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a61; op2val:0xbcd1; +op3val:0x3baf; valaddr_reg:x5; val_offset:3222*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 3222*FLEN/8, x9, x1, x4) + +inst_1099: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x261 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0d1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3af and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a61; op2val:0xbcd1; +op3val:0x3baf; valaddr_reg:x5; val_offset:3225*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3225*FLEN/8, x9, x1, x4) + +inst_1100: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x317 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0af and fs3 == 0 and fe3 == 0x0e and fm3 == 0x026 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f17; op2val:0xc4af; +op3val:0x3826; valaddr_reg:x5; val_offset:3228*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3228*FLEN/8, x9, x1, x4) + +inst_1101: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x317 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0af and fs3 == 0 and fe3 == 0x0e and fm3 == 0x026 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f17; op2val:0xc4af; +op3val:0x3826; valaddr_reg:x5; val_offset:3231*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3231*FLEN/8, x9, x1, x4) + +inst_1102: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x317 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0af and fs3 == 0 and fe3 == 0x0e and fm3 == 0x026 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f17; op2val:0xc4af; +op3val:0x3826; valaddr_reg:x5; val_offset:3234*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3234*FLEN/8, x9, x1, x4) + +inst_1103: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x317 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0af and fs3 == 0 and fe3 == 0x0e and fm3 == 0x026 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f17; op2val:0xc4af; +op3val:0x3826; valaddr_reg:x5; val_offset:3237*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 3237*FLEN/8, x9, x1, x4) + +inst_1104: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x317 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0af and fs3 == 0 and fe3 == 0x0e and fm3 == 0x026 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f17; op2val:0xc4af; +op3val:0x3826; valaddr_reg:x5; val_offset:3240*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3240*FLEN/8, x9, x1, x4) + +inst_1105: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3ab and fs2 == 1 and fe2 == 0x11 and fm2 == 0x02b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x33ab; op2val:0xc42b; +op3val:0x3bff; valaddr_reg:x5; val_offset:3243*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3243*FLEN/8, x9, x1, x4) + +inst_1106: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3ab and fs2 == 1 and fe2 == 0x11 and fm2 == 0x02b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x33ab; op2val:0xc42b; +op3val:0x3bff; valaddr_reg:x5; val_offset:3246*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3246*FLEN/8, x9, x1, x4) + +inst_1107: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3ab and fs2 == 1 and fe2 == 0x11 and fm2 == 0x02b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x33ab; op2val:0xc42b; +op3val:0x3bff; valaddr_reg:x5; val_offset:3249*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3249*FLEN/8, x9, x1, x4) + +inst_1108: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3ab and fs2 == 1 and fe2 == 0x11 and fm2 == 0x02b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x33ab; op2val:0xc42b; +op3val:0x3bff; valaddr_reg:x5; val_offset:3252*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 3252*FLEN/8, x9, x1, x4) + +inst_1109: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3ab and fs2 == 1 and fe2 == 0x11 and fm2 == 0x02b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x33ab; op2val:0xc42b; +op3val:0x3bff; valaddr_reg:x5; val_offset:3255*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3255*FLEN/8, x9, x1, x4) + +inst_1110: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x03d and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2a8 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x30e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x383d; op2val:0xb2a8; +op3val:0x2f0e; valaddr_reg:x5; val_offset:3258*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3258*FLEN/8, x9, x1, x4) + +inst_1111: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x03d and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2a8 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x30e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x383d; op2val:0xb2a8; +op3val:0x2f0e; valaddr_reg:x5; val_offset:3261*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3261*FLEN/8, x9, x1, x4) + +inst_1112: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x03d and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2a8 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x30e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x383d; op2val:0xb2a8; +op3val:0x2f0e; valaddr_reg:x5; val_offset:3264*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3264*FLEN/8, x9, x1, x4) + +inst_1113: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x03d and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2a8 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x30e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x383d; op2val:0xb2a8; +op3val:0x2f0e; valaddr_reg:x5; val_offset:3267*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 3267*FLEN/8, x9, x1, x4) + +inst_1114: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x03d and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2a8 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x30e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x383d; op2val:0xb2a8; +op3val:0x2f0e; valaddr_reg:x5; val_offset:3270*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3270*FLEN/8, x9, x1, x4) + +inst_1115: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x216 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x092 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3616; op2val:0xbe01; +op3val:0x3892; valaddr_reg:x5; val_offset:3273*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3273*FLEN/8, x9, x1, x4) + +inst_1116: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x216 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x092 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3616; op2val:0xbe01; +op3val:0x3892; valaddr_reg:x5; val_offset:3276*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3276*FLEN/8, x9, x1, x4) + +inst_1117: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x216 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x092 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3616; op2val:0xbe01; +op3val:0x3892; valaddr_reg:x5; val_offset:3279*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3279*FLEN/8, x9, x1, x4) + +inst_1118: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x216 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x092 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3616; op2val:0xbe01; +op3val:0x3892; valaddr_reg:x5; val_offset:3282*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 3282*FLEN/8, x9, x1, x4) + +inst_1119: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x216 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x092 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3616; op2val:0xbe01; +op3val:0x3892; valaddr_reg:x5; val_offset:3285*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3285*FLEN/8, x9, x1, x4) + +inst_1120: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x046 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2bc and fs3 == 0 and fe3 == 0x0e and fm3 == 0x333 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3846; op2val:0xbebc; +op3val:0x3b33; valaddr_reg:x5; val_offset:3288*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3288*FLEN/8, x9, x1, x4) + +inst_1121: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x046 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2bc and fs3 == 0 and fe3 == 0x0e and fm3 == 0x333 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3846; op2val:0xbebc; +op3val:0x3b33; valaddr_reg:x5; val_offset:3291*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3291*FLEN/8, x9, x1, x4) + +inst_1122: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x046 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2bc and fs3 == 0 and fe3 == 0x0e and fm3 == 0x333 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3846; op2val:0xbebc; +op3val:0x3b33; valaddr_reg:x5; val_offset:3294*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3294*FLEN/8, x9, x1, x4) + +inst_1123: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x046 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2bc and fs3 == 0 and fe3 == 0x0e and fm3 == 0x333 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3846; op2val:0xbebc; +op3val:0x3b33; valaddr_reg:x5; val_offset:3297*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 3297*FLEN/8, x9, x1, x4) + +inst_1124: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x046 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2bc and fs3 == 0 and fe3 == 0x0e and fm3 == 0x333 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3846; op2val:0xbebc; +op3val:0x3b33; valaddr_reg:x5; val_offset:3300*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3300*FLEN/8, x9, x1, x4) + +inst_1125: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2c3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3f5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ba and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ac3; op2val:0xbbf5; +op3val:0x3aba; valaddr_reg:x5; val_offset:3303*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3303*FLEN/8, x9, x1, x4) + +inst_1126: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2c3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3f5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ba and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ac3; op2val:0xbbf5; +op3val:0x3aba; valaddr_reg:x5; val_offset:3306*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3306*FLEN/8, x9, x1, x4) + +inst_1127: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2c3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3f5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ba and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ac3; op2val:0xbbf5; +op3val:0x3aba; valaddr_reg:x5; val_offset:3309*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3309*FLEN/8, x9, x1, x4) + +inst_1128: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2c3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3f5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ba and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ac3; op2val:0xbbf5; +op3val:0x3aba; valaddr_reg:x5; val_offset:3312*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 3312*FLEN/8, x9, x1, x4) + +inst_1129: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2c3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3f5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ba and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ac3; op2val:0xbbf5; +op3val:0x3aba; valaddr_reg:x5; val_offset:3315*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3315*FLEN/8, x9, x1, x4) + +inst_1130: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x100 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3db and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0ea and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3900; op2val:0xbbdb; +op3val:0x38ea; valaddr_reg:x5; val_offset:3318*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3318*FLEN/8, x9, x1, x4) + +inst_1131: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x100 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3db and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0ea and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3900; op2val:0xbbdb; +op3val:0x38ea; valaddr_reg:x5; val_offset:3321*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3321*FLEN/8, x9, x1, x4) + +inst_1132: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x100 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3db and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0ea and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3900; op2val:0xbbdb; +op3val:0x38ea; valaddr_reg:x5; val_offset:3324*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3324*FLEN/8, x9, x1, x4) + +inst_1133: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x100 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3db and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0ea and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3900; op2val:0xbbdb; +op3val:0x38ea; valaddr_reg:x5; val_offset:3327*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 3327*FLEN/8, x9, x1, x4) + +inst_1134: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x100 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3db and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0ea and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3900; op2val:0xbbdb; +op3val:0x38ea; valaddr_reg:x5; val_offset:3330*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3330*FLEN/8, x9, x1, x4) + +inst_1135: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3a9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x314 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2c8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2fa9; op2val:0xc714; +op3val:0x3ac8; valaddr_reg:x5; val_offset:3333*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3333*FLEN/8, x9, x1, x4) + +inst_1136: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3a9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x314 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2c8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2fa9; op2val:0xc714; +op3val:0x3ac8; valaddr_reg:x5; val_offset:3336*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3336*FLEN/8, x9, x1, x4) + +inst_1137: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3a9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x314 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2c8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2fa9; op2val:0xc714; +op3val:0x3ac8; valaddr_reg:x5; val_offset:3339*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3339*FLEN/8, x9, x1, x4) + +inst_1138: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3a9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x314 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2c8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2fa9; op2val:0xc714; +op3val:0x3ac8; valaddr_reg:x5; val_offset:3342*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 3342*FLEN/8, x9, x1, x4) + +inst_1139: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3a9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x314 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2c8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2fa9; op2val:0xc714; +op3val:0x3ac8; valaddr_reg:x5; val_offset:3345*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3345*FLEN/8, x9, x1, x4) + +inst_1140: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1f7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3bf and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1c7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39f7; op2val:0xbbbf; +op3val:0x39c7; valaddr_reg:x5; val_offset:3348*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3348*FLEN/8, x9, x1, x4) + +inst_1141: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1f7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3bf and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1c7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39f7; op2val:0xbbbf; +op3val:0x39c7; valaddr_reg:x5; val_offset:3351*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3351*FLEN/8, x9, x1, x4) + +inst_1142: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1f7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3bf and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1c7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39f7; op2val:0xbbbf; +op3val:0x39c7; valaddr_reg:x5; val_offset:3354*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3354*FLEN/8, x9, x1, x4) + +inst_1143: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1f7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3bf and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1c7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39f7; op2val:0xbbbf; +op3val:0x39c7; valaddr_reg:x5; val_offset:3357*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 3357*FLEN/8, x9, x1, x4) + +inst_1144: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1f7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3bf and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1c7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39f7; op2val:0xbbbf; +op3val:0x39c7; valaddr_reg:x5; val_offset:3360*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3360*FLEN/8, x9, x1, x4) + +inst_1145: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2cd and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1b4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ab5; op2val:0xbacd; +op3val:0x39b4; valaddr_reg:x5; val_offset:3363*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3363*FLEN/8, x9, x1, x4) + +inst_1146: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2cd and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1b4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ab5; op2val:0xbacd; +op3val:0x39b4; valaddr_reg:x5; val_offset:3366*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3366*FLEN/8, x9, x1, x4) + +inst_1147: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2cd and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1b4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ab5; op2val:0xbacd; +op3val:0x39b4; valaddr_reg:x5; val_offset:3369*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3369*FLEN/8, x9, x1, x4) + +inst_1148: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2cd and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1b4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ab5; op2val:0xbacd; +op3val:0x39b4; valaddr_reg:x5; val_offset:3372*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 3372*FLEN/8, x9, x1, x4) + +inst_1149: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2cd and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1b4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ab5; op2val:0xbacd; +op3val:0x39b4; valaddr_reg:x5; val_offset:3375*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3375*FLEN/8, x9, x1, x4) + +inst_1150: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x21e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x16a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x024 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a1e; op2val:0xb96a; +op3val:0x3824; valaddr_reg:x5; val_offset:3378*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3378*FLEN/8, x9, x1, x4) + +inst_1151: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x21e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x16a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x024 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a1e; op2val:0xb96a; +op3val:0x3824; valaddr_reg:x5; val_offset:3381*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3381*FLEN/8, x9, x1, x4) + +inst_1152: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x21e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x16a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x024 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a1e; op2val:0xb96a; +op3val:0x3824; valaddr_reg:x5; val_offset:3384*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3384*FLEN/8, x9, x1, x4) + +inst_1153: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x21e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x16a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x024 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a1e; op2val:0xb96a; +op3val:0x3824; valaddr_reg:x5; val_offset:3387*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 3387*FLEN/8, x9, x1, x4) + +inst_1154: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x21e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x16a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x024 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a1e; op2val:0xb96a; +op3val:0x3824; valaddr_reg:x5; val_offset:3390*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3390*FLEN/8, x9, x1, x4) + +inst_1155: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3be and fs2 == 1 and fe2 == 0x0b and fm2 == 0x0fd and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0d5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bbe; op2val:0xacfd; +op3val:0x2cd5; valaddr_reg:x5; val_offset:3393*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3393*FLEN/8, x9, x1, x4) + +inst_1156: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3be and fs2 == 1 and fe2 == 0x0b and fm2 == 0x0fd and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0d5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bbe; op2val:0xacfd; +op3val:0x2cd5; valaddr_reg:x5; val_offset:3396*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3396*FLEN/8, x9, x1, x4) + +inst_1157: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3be and fs2 == 1 and fe2 == 0x0b and fm2 == 0x0fd and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0d5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bbe; op2val:0xacfd; +op3val:0x2cd5; valaddr_reg:x5; val_offset:3399*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3399*FLEN/8, x9, x1, x4) + +inst_1158: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3be and fs2 == 1 and fe2 == 0x0b and fm2 == 0x0fd and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0d5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bbe; op2val:0xacfd; +op3val:0x2cd5; valaddr_reg:x5; val_offset:3402*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 3402*FLEN/8, x9, x1, x4) + +inst_1159: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3be and fs2 == 1 and fe2 == 0x0b and fm2 == 0x0fd and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0d5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bbe; op2val:0xacfd; +op3val:0x2cd5; valaddr_reg:x5; val_offset:3405*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3405*FLEN/8, x9, x1, x4) + +inst_1160: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x10c and fs2 == 1 and fe2 == 0x0b and fm2 == 0x24b and fs3 == 0 and fe3 == 0x0a and fm3 == 0x3f3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x390c; op2val:0xae4b; +op3val:0x2bf3; valaddr_reg:x5; val_offset:3408*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3408*FLEN/8, x9, x1, x4) + +inst_1161: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x10c and fs2 == 1 and fe2 == 0x0b and fm2 == 0x24b and fs3 == 0 and fe3 == 0x0a and fm3 == 0x3f3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x390c; op2val:0xae4b; +op3val:0x2bf3; valaddr_reg:x5; val_offset:3411*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3411*FLEN/8, x9, x1, x4) + +inst_1162: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x10c and fs2 == 1 and fe2 == 0x0b and fm2 == 0x24b and fs3 == 0 and fe3 == 0x0a and fm3 == 0x3f3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x390c; op2val:0xae4b; +op3val:0x2bf3; valaddr_reg:x5; val_offset:3414*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3414*FLEN/8, x9, x1, x4) + +inst_1163: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x10c and fs2 == 1 and fe2 == 0x0b and fm2 == 0x24b and fs3 == 0 and fe3 == 0x0a and fm3 == 0x3f3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x390c; op2val:0xae4b; +op3val:0x2bf3; valaddr_reg:x5; val_offset:3417*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 3417*FLEN/8, x9, x1, x4) + +inst_1164: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x10c and fs2 == 1 and fe2 == 0x0b and fm2 == 0x24b and fs3 == 0 and fe3 == 0x0a and fm3 == 0x3f3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x390c; op2val:0xae4b; +op3val:0x2bf3; valaddr_reg:x5; val_offset:3420*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3420*FLEN/8, x9, x1, x4) + +inst_1165: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x02d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x138 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34ff; op2val:0xbc2d; +op3val:0x3538; valaddr_reg:x5; val_offset:3423*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3423*FLEN/8, x9, x1, x4) + +inst_1166: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x02d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x138 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34ff; op2val:0xbc2d; +op3val:0x3538; valaddr_reg:x5; val_offset:3426*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3426*FLEN/8, x9, x1, x4) + +inst_1167: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x02d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x138 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34ff; op2val:0xbc2d; +op3val:0x3538; valaddr_reg:x5; val_offset:3429*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3429*FLEN/8, x9, x1, x4) + +inst_1168: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x02d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x138 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34ff; op2val:0xbc2d; +op3val:0x3538; valaddr_reg:x5; val_offset:3432*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 3432*FLEN/8, x9, x1, x4) + +inst_1169: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x02d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x138 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34ff; op2val:0xbc2d; +op3val:0x3538; valaddr_reg:x5; val_offset:3435*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3435*FLEN/8, x9, x1, x4) + +inst_1170: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x039 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x29d and fs3 == 0 and fe3 == 0x0a and fm3 == 0x2ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3839; op2val:0xae9d; +op3val:0x2aff; valaddr_reg:x5; val_offset:3438*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3438*FLEN/8, x9, x1, x4) + +inst_1171: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x039 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x29d and fs3 == 0 and fe3 == 0x0a and fm3 == 0x2ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3839; op2val:0xae9d; +op3val:0x2aff; valaddr_reg:x5; val_offset:3441*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3441*FLEN/8, x9, x1, x4) + +inst_1172: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x039 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x29d and fs3 == 0 and fe3 == 0x0a and fm3 == 0x2ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3839; op2val:0xae9d; +op3val:0x2aff; valaddr_reg:x5; val_offset:3444*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3444*FLEN/8, x9, x1, x4) + +inst_1173: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x039 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x29d and fs3 == 0 and fe3 == 0x0a and fm3 == 0x2ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3839; op2val:0xae9d; +op3val:0x2aff; valaddr_reg:x5; val_offset:3447*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 3447*FLEN/8, x9, x1, x4) + +inst_1174: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x039 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x29d and fs3 == 0 and fe3 == 0x0a and fm3 == 0x2ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3839; op2val:0xae9d; +op3val:0x2aff; valaddr_reg:x5; val_offset:3450*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3450*FLEN/8, x9, x1, x4) + +inst_1175: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x30e and fs2 == 1 and fe2 == 0x0d and fm2 == 0x202 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x14d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b0e; op2val:0xb602; +op3val:0x354d; valaddr_reg:x5; val_offset:3453*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3453*FLEN/8, x9, x1, x4) + +inst_1176: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x30e and fs2 == 1 and fe2 == 0x0d and fm2 == 0x202 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x14d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b0e; op2val:0xb602; +op3val:0x354d; valaddr_reg:x5; val_offset:3456*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3456*FLEN/8, x9, x1, x4) + +inst_1177: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x30e and fs2 == 1 and fe2 == 0x0d and fm2 == 0x202 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x14d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b0e; op2val:0xb602; +op3val:0x354d; valaddr_reg:x5; val_offset:3459*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3459*FLEN/8, x9, x1, x4) + +inst_1178: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x30e and fs2 == 1 and fe2 == 0x0d and fm2 == 0x202 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x14d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b0e; op2val:0xb602; +op3val:0x354d; valaddr_reg:x5; val_offset:3462*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 3462*FLEN/8, x9, x1, x4) + +inst_1179: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x30e and fs2 == 1 and fe2 == 0x0d and fm2 == 0x202 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x14d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b0e; op2val:0xb602; +op3val:0x354d; valaddr_reg:x5; val_offset:3465*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3465*FLEN/8, x9, x1, x4) + +inst_1180: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ab and fs2 == 1 and fe2 == 0x0d and fm2 == 0x358 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x135 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39ab; op2val:0xb758; +op3val:0x3535; valaddr_reg:x5; val_offset:3468*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3468*FLEN/8, x9, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_10) + +inst_1181: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ab and fs2 == 1 and fe2 == 0x0d and fm2 == 0x358 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x135 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39ab; op2val:0xb758; +op3val:0x3535; valaddr_reg:x5; val_offset:3471*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3471*FLEN/8, x9, x1, x4) + +inst_1182: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ab and fs2 == 1 and fe2 == 0x0d and fm2 == 0x358 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x135 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39ab; op2val:0xb758; +op3val:0x3535; valaddr_reg:x5; val_offset:3474*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3474*FLEN/8, x9, x1, x4) + +inst_1183: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ab and fs2 == 1 and fe2 == 0x0d and fm2 == 0x358 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x135 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39ab; op2val:0xb758; +op3val:0x3535; valaddr_reg:x5; val_offset:3477*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 3477*FLEN/8, x9, x1, x4) + +inst_1184: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ab and fs2 == 1 and fe2 == 0x0d and fm2 == 0x358 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x135 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39ab; op2val:0xb758; +op3val:0x3535; valaddr_reg:x5; val_offset:3480*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3480*FLEN/8, x9, x1, x4) + +inst_1185: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x055 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x22e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3455; op2val:0xc22e; +op3val:0x3ab1; valaddr_reg:x5; val_offset:3483*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3483*FLEN/8, x9, x1, x4) + +inst_1186: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x055 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x22e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3455; op2val:0xc22e; +op3val:0x3ab1; valaddr_reg:x5; val_offset:3486*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3486*FLEN/8, x9, x1, x4) + +inst_1187: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x055 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x22e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3455; op2val:0xc22e; +op3val:0x3ab1; valaddr_reg:x5; val_offset:3489*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3489*FLEN/8, x9, x1, x4) + +inst_1188: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x055 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x22e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3455; op2val:0xc22e; +op3val:0x3ab1; valaddr_reg:x5; val_offset:3492*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 3492*FLEN/8, x9, x1, x4) + +inst_1189: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x055 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x22e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3455; op2val:0xc22e; +op3val:0x3ab1; valaddr_reg:x5; val_offset:3495*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3495*FLEN/8, x9, x1, x4) + +inst_1190: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x264 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0e1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3cc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a64; op2val:0xbce1; +op3val:0x3bcc; valaddr_reg:x5; val_offset:3498*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3498*FLEN/8, x9, x1, x4) + +inst_1191: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x264 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0e1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3cc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a64; op2val:0xbce1; +op3val:0x3bcc; valaddr_reg:x5; val_offset:3501*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3501*FLEN/8, x9, x1, x4) + +inst_1192: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x264 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0e1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3cc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a64; op2val:0xbce1; +op3val:0x3bcc; valaddr_reg:x5; val_offset:3504*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3504*FLEN/8, x9, x1, x4) + +inst_1193: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x264 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0e1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3cc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a64; op2val:0xbce1; +op3val:0x3bcc; valaddr_reg:x5; val_offset:3507*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 3507*FLEN/8, x9, x1, x4) + +inst_1194: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x264 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0e1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3cc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a64; op2val:0xbce1; +op3val:0x3bcc; valaddr_reg:x5; val_offset:3510*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3510*FLEN/8, x9, x1, x4) + +inst_1195: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x228 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0ca and fs3 == 0 and fe3 == 0x0e and fm3 == 0x35f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a28; op2val:0xbcca; +op3val:0x3b5f; valaddr_reg:x5; val_offset:3513*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3513*FLEN/8, x9, x1, x4) + +inst_1196: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x228 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0ca and fs3 == 0 and fe3 == 0x0e and fm3 == 0x35f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a28; op2val:0xbcca; +op3val:0x3b5f; valaddr_reg:x5; val_offset:3516*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3516*FLEN/8, x9, x1, x4) + +inst_1197: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x228 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0ca and fs3 == 0 and fe3 == 0x0e and fm3 == 0x35f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a28; op2val:0xbcca; +op3val:0x3b5f; valaddr_reg:x5; val_offset:3519*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3519*FLEN/8, x9, x1, x4) + +inst_1198: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x228 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0ca and fs3 == 0 and fe3 == 0x0e and fm3 == 0x35f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a28; op2val:0xbcca; +op3val:0x3b5f; valaddr_reg:x5; val_offset:3522*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 3522*FLEN/8, x9, x1, x4) + +inst_1199: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x228 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0ca and fs3 == 0 and fe3 == 0x0e and fm3 == 0x35f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a28; op2val:0xbcca; +op3val:0x3b5f; valaddr_reg:x5; val_offset:3525*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3525*FLEN/8, x9, x1, x4) + +inst_1200: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ca and fs2 == 1 and fe2 == 0x0a and fm2 == 0x1a4 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x2c7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ca; op2val:0xa9a4; +op3val:0x26c7; valaddr_reg:x5; val_offset:3528*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3528*FLEN/8, x9, x1, x4) + +inst_1201: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ca and fs2 == 1 and fe2 == 0x0a and fm2 == 0x1a4 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x2c7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ca; op2val:0xa9a4; +op3val:0x26c7; valaddr_reg:x5; val_offset:3531*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3531*FLEN/8, x9, x1, x4) + +inst_1202: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ca and fs2 == 1 and fe2 == 0x0a and fm2 == 0x1a4 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x2c7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ca; op2val:0xa9a4; +op3val:0x26c7; valaddr_reg:x5; val_offset:3534*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3534*FLEN/8, x9, x1, x4) + +inst_1203: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ca and fs2 == 1 and fe2 == 0x0a and fm2 == 0x1a4 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x2c7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ca; op2val:0xa9a4; +op3val:0x26c7; valaddr_reg:x5; val_offset:3537*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 3537*FLEN/8, x9, x1, x4) + +inst_1204: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ca and fs2 == 1 and fe2 == 0x0a and fm2 == 0x1a4 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x2c7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ca; op2val:0xa9a4; +op3val:0x26c7; valaddr_reg:x5; val_offset:3540*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3540*FLEN/8, x9, x1, x4) + +inst_1205: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x116 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x054 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x181 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3916; op2val:0xbc54; +op3val:0x3981; valaddr_reg:x5; val_offset:3543*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3543*FLEN/8, x9, x1, x4) + +inst_1206: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x116 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x054 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x181 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3916; op2val:0xbc54; +op3val:0x3981; valaddr_reg:x5; val_offset:3546*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3546*FLEN/8, x9, x1, x4) + +inst_1207: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x116 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x054 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x181 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3916; op2val:0xbc54; +op3val:0x3981; valaddr_reg:x5; val_offset:3549*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3549*FLEN/8, x9, x1, x4) + +inst_1208: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x116 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x054 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x181 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3916; op2val:0xbc54; +op3val:0x3981; valaddr_reg:x5; val_offset:3552*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 3552*FLEN/8, x9, x1, x4) + +inst_1209: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x116 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x054 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x181 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3916; op2val:0xbc54; +op3val:0x3981; valaddr_reg:x5; val_offset:3555*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3555*FLEN/8, x9, x1, x4) + +inst_1210: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x041 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x163 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1bc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3841; op2val:0xbd63; +op3val:0x39bc; valaddr_reg:x5; val_offset:3558*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3558*FLEN/8, x9, x1, x4) + +inst_1211: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x041 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x163 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1bc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3841; op2val:0xbd63; +op3val:0x39bc; valaddr_reg:x5; val_offset:3561*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3561*FLEN/8, x9, x1, x4) + +inst_1212: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x041 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x163 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1bc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3841; op2val:0xbd63; +op3val:0x39bc; valaddr_reg:x5; val_offset:3564*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3564*FLEN/8, x9, x1, x4) + +inst_1213: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x041 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x163 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1bc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3841; op2val:0xbd63; +op3val:0x39bc; valaddr_reg:x5; val_offset:3567*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 3567*FLEN/8, x9, x1, x4) + +inst_1214: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x041 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x163 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1bc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3841; op2val:0xbd63; +op3val:0x39bc; valaddr_reg:x5; val_offset:3570*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3570*FLEN/8, x9, x1, x4) + +inst_1215: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x048 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x036 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x083 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3448; op2val:0xbc36; +op3val:0x3483; valaddr_reg:x5; val_offset:3573*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3573*FLEN/8, x9, x1, x4) + +inst_1216: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x048 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x036 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x083 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3448; op2val:0xbc36; +op3val:0x3483; valaddr_reg:x5; val_offset:3576*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3576*FLEN/8, x9, x1, x4) + +inst_1217: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x048 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x036 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x083 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3448; op2val:0xbc36; +op3val:0x3483; valaddr_reg:x5; val_offset:3579*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3579*FLEN/8, x9, x1, x4) + +inst_1218: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x048 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x036 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x083 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3448; op2val:0xbc36; +op3val:0x3483; valaddr_reg:x5; val_offset:3582*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 3582*FLEN/8, x9, x1, x4) + +inst_1219: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x048 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x036 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x083 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3448; op2val:0xbc36; +op3val:0x3483; valaddr_reg:x5; val_offset:3585*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3585*FLEN/8, x9, x1, x4) + +inst_1220: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b1 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x342 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x213 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ab1; op2val:0xbb42; +op3val:0x3a13; valaddr_reg:x5; val_offset:3588*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3588*FLEN/8, x9, x1, x4) + +inst_1221: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b1 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x342 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x213 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ab1; op2val:0xbb42; +op3val:0x3a13; valaddr_reg:x5; val_offset:3591*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3591*FLEN/8, x9, x1, x4) + +inst_1222: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b1 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x342 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x213 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ab1; op2val:0xbb42; +op3val:0x3a13; valaddr_reg:x5; val_offset:3594*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3594*FLEN/8, x9, x1, x4) + +inst_1223: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b1 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x342 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x213 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ab1; op2val:0xbb42; +op3val:0x3a13; valaddr_reg:x5; val_offset:3597*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 3597*FLEN/8, x9, x1, x4) + +inst_1224: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b1 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x342 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x213 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ab1; op2val:0xbb42; +op3val:0x3a13; valaddr_reg:x5; val_offset:3600*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3600*FLEN/8, x9, x1, x4) + +inst_1225: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x13e and fs2 == 1 and fe2 == 0x0c and fm2 == 0x1cf and fs3 == 0 and fe3 == 0x0a and fm3 == 0x3a0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x353e; op2val:0xb1cf; +op3val:0x2ba0; valaddr_reg:x5; val_offset:3603*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3603*FLEN/8, x9, x1, x4) + +inst_1226: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x13e and fs2 == 1 and fe2 == 0x0c and fm2 == 0x1cf and fs3 == 0 and fe3 == 0x0a and fm3 == 0x3a0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x353e; op2val:0xb1cf; +op3val:0x2ba0; valaddr_reg:x5; val_offset:3606*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3606*FLEN/8, x9, x1, x4) + +inst_1227: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x13e and fs2 == 1 and fe2 == 0x0c and fm2 == 0x1cf and fs3 == 0 and fe3 == 0x0a and fm3 == 0x3a0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x353e; op2val:0xb1cf; +op3val:0x2ba0; valaddr_reg:x5; val_offset:3609*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3609*FLEN/8, x9, x1, x4) + +inst_1228: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x13e and fs2 == 1 and fe2 == 0x0c and fm2 == 0x1cf and fs3 == 0 and fe3 == 0x0a and fm3 == 0x3a0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x353e; op2val:0xb1cf; +op3val:0x2ba0; valaddr_reg:x5; val_offset:3612*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 3612*FLEN/8, x9, x1, x4) + +inst_1229: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x13e and fs2 == 1 and fe2 == 0x0c and fm2 == 0x1cf and fs3 == 0 and fe3 == 0x0a and fm3 == 0x3a0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x353e; op2val:0xb1cf; +op3val:0x2ba0; valaddr_reg:x5; val_offset:3615*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3615*FLEN/8, x9, x1, x4) + +inst_1230: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1aa and fs2 == 1 and fe2 == 0x0f and fm2 == 0x26e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35aa; op2val:0xbe6e; +op3val:0x388e; valaddr_reg:x5; val_offset:3618*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3618*FLEN/8, x9, x1, x4) + +inst_1231: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1aa and fs2 == 1 and fe2 == 0x0f and fm2 == 0x26e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35aa; op2val:0xbe6e; +op3val:0x388e; valaddr_reg:x5; val_offset:3621*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3621*FLEN/8, x9, x1, x4) + +inst_1232: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1aa and fs2 == 1 and fe2 == 0x0f and fm2 == 0x26e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35aa; op2val:0xbe6e; +op3val:0x388e; valaddr_reg:x5; val_offset:3624*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3624*FLEN/8, x9, x1, x4) + +inst_1233: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1aa and fs2 == 1 and fe2 == 0x0f and fm2 == 0x26e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35aa; op2val:0xbe6e; +op3val:0x388e; valaddr_reg:x5; val_offset:3627*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 3627*FLEN/8, x9, x1, x4) + +inst_1234: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1aa and fs2 == 1 and fe2 == 0x0f and fm2 == 0x26e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35aa; op2val:0xbe6e; +op3val:0x388e; valaddr_reg:x5; val_offset:3630*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3630*FLEN/8, x9, x1, x4) + +inst_1235: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x24e and fs2 == 1 and fe2 == 0x14 and fm2 == 0x10a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3f3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x264e; op2val:0xd10a; +op3val:0x3bf3; valaddr_reg:x5; val_offset:3633*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3633*FLEN/8, x9, x1, x4) + +inst_1236: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x24e and fs2 == 1 and fe2 == 0x14 and fm2 == 0x10a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3f3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x264e; op2val:0xd10a; +op3val:0x3bf3; valaddr_reg:x5; val_offset:3636*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3636*FLEN/8, x9, x1, x4) + +inst_1237: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x24e and fs2 == 1 and fe2 == 0x14 and fm2 == 0x10a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3f3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x264e; op2val:0xd10a; +op3val:0x3bf3; valaddr_reg:x5; val_offset:3639*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3639*FLEN/8, x9, x1, x4) + +inst_1238: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x24e and fs2 == 1 and fe2 == 0x14 and fm2 == 0x10a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3f3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x264e; op2val:0xd10a; +op3val:0x3bf3; valaddr_reg:x5; val_offset:3642*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 3642*FLEN/8, x9, x1, x4) + +inst_1239: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x24e and fs2 == 1 and fe2 == 0x14 and fm2 == 0x10a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3f3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x264e; op2val:0xd10a; +op3val:0x3bf3; valaddr_reg:x5; val_offset:3645*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3645*FLEN/8, x9, x1, x4) + +inst_1240: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x383 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x385 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x310 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b83; op2val:0xb385; +op3val:0x3310; valaddr_reg:x5; val_offset:3648*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3648*FLEN/8, x9, x1, x4) + +inst_1241: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x383 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x385 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x310 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b83; op2val:0xb385; +op3val:0x3310; valaddr_reg:x5; val_offset:3651*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3651*FLEN/8, x9, x1, x4) + +inst_1242: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x383 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x385 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x310 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b83; op2val:0xb385; +op3val:0x3310; valaddr_reg:x5; val_offset:3654*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3654*FLEN/8, x9, x1, x4) + +inst_1243: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x383 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x385 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x310 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b83; op2val:0xb385; +op3val:0x3310; valaddr_reg:x5; val_offset:3657*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 3657*FLEN/8, x9, x1, x4) + +inst_1244: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x383 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x385 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x310 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b83; op2val:0xb385; +op3val:0x3310; valaddr_reg:x5; val_offset:3660*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3660*FLEN/8, x9, x1, x4) + +inst_1245: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0b8 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x279 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3a3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38b8; op2val:0xbe79; +op3val:0x3ba3; valaddr_reg:x5; val_offset:3663*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3663*FLEN/8, x9, x1, x4) + +inst_1246: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0b8 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x279 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3a3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38b8; op2val:0xbe79; +op3val:0x3ba3; valaddr_reg:x5; val_offset:3666*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3666*FLEN/8, x9, x1, x4) + +inst_1247: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0b8 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x279 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3a3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38b8; op2val:0xbe79; +op3val:0x3ba3; valaddr_reg:x5; val_offset:3669*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3669*FLEN/8, x9, x1, x4) + +inst_1248: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0b8 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x279 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3a3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38b8; op2val:0xbe79; +op3val:0x3ba3; valaddr_reg:x5; val_offset:3672*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 3672*FLEN/8, x9, x1, x4) + +inst_1249: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0b8 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x279 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3a3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38b8; op2val:0xbe79; +op3val:0x3ba3; valaddr_reg:x5; val_offset:3675*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3675*FLEN/8, x9, x1, x4) + +inst_1250: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x339 and fs2 == 1 and fe2 == 0x09 and fm2 == 0x1e4 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x15b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3739; op2val:0xa5e4; +op3val:0x215b; valaddr_reg:x5; val_offset:3678*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3678*FLEN/8, x9, x1, x4) + +inst_1251: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x339 and fs2 == 1 and fe2 == 0x09 and fm2 == 0x1e4 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x15b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3739; op2val:0xa5e4; +op3val:0x215b; valaddr_reg:x5; val_offset:3681*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3681*FLEN/8, x9, x1, x4) + +inst_1252: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x339 and fs2 == 1 and fe2 == 0x09 and fm2 == 0x1e4 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x15b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3739; op2val:0xa5e4; +op3val:0x215b; valaddr_reg:x5; val_offset:3684*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3684*FLEN/8, x9, x1, x4) + +inst_1253: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x339 and fs2 == 1 and fe2 == 0x09 and fm2 == 0x1e4 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x15b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3739; op2val:0xa5e4; +op3val:0x215b; valaddr_reg:x5; val_offset:3687*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 3687*FLEN/8, x9, x1, x4) + +inst_1254: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x339 and fs2 == 1 and fe2 == 0x09 and fm2 == 0x1e4 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x15b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3739; op2val:0xa5e4; +op3val:0x215b; valaddr_reg:x5; val_offset:3690*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3690*FLEN/8, x9, x1, x4) + +inst_1255: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3b2 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x167 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x133 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37b2; op2val:0xbd67; +op3val:0x3933; valaddr_reg:x5; val_offset:3693*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3693*FLEN/8, x9, x1, x4) + +inst_1256: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3b2 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x167 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x133 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37b2; op2val:0xbd67; +op3val:0x3933; valaddr_reg:x5; val_offset:3696*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3696*FLEN/8, x9, x1, x4) + +inst_1257: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3b2 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x167 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x133 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37b2; op2val:0xbd67; +op3val:0x3933; valaddr_reg:x5; val_offset:3699*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3699*FLEN/8, x9, x1, x4) + +inst_1258: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3b2 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x167 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x133 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37b2; op2val:0xbd67; +op3val:0x3933; valaddr_reg:x5; val_offset:3702*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 3702*FLEN/8, x9, x1, x4) + +inst_1259: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3b2 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x167 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x133 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37b2; op2val:0xbd67; +op3val:0x3933; valaddr_reg:x5; val_offset:3705*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3705*FLEN/8, x9, x1, x4) + +inst_1260: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x2e9 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x03b and fs3 == 0 and fe3 == 0x11 and fm3 == 0x17c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x46e9; op2val:0x483b; +op3val:0x457c; valaddr_reg:x5; val_offset:3708*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3708*FLEN/8, x9, x1, x4) + +inst_1261: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x2e9 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x03b and fs3 == 0 and fe3 == 0x11 and fm3 == 0x17c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x46e9; op2val:0x483b; +op3val:0x457c; valaddr_reg:x5; val_offset:3711*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3711*FLEN/8, x9, x1, x4) + +inst_1262: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x2e9 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x03b and fs3 == 0 and fe3 == 0x11 and fm3 == 0x17c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x46e9; op2val:0x483b; +op3val:0x457c; valaddr_reg:x5; val_offset:3714*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3714*FLEN/8, x9, x1, x4) + +inst_1263: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x2e9 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x03b and fs3 == 0 and fe3 == 0x11 and fm3 == 0x17c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x46e9; op2val:0x483b; +op3val:0x457c; valaddr_reg:x5; val_offset:3717*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 3717*FLEN/8, x9, x1, x4) + +inst_1264: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x2e9 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x03b and fs3 == 0 and fe3 == 0x11 and fm3 == 0x17c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x46e9; op2val:0x483b; +op3val:0x457c; valaddr_reg:x5; val_offset:3720*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3720*FLEN/8, x9, x1, x4) + +inst_1265: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x334 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x073 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5334; op2val:0x3873; +op3val:0x4ffc; valaddr_reg:x5; val_offset:3723*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3723*FLEN/8, x9, x1, x4) + +inst_1266: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x334 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x073 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x3fc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5334; op2val:0x3873; +op3val:0x4ffc; valaddr_reg:x5; val_offset:3726*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3726*FLEN/8, x9, x1, x4) + +inst_1267: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x334 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x073 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x3fc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5334; op2val:0x3873; +op3val:0x4ffc; valaddr_reg:x5; val_offset:3729*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3729*FLEN/8, x9, x1, x4) + +inst_1268: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x334 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x073 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x3fc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5334; op2val:0x3873; +op3val:0x4ffc; valaddr_reg:x5; val_offset:3732*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 3732*FLEN/8, x9, x1, x4) + +inst_1269: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x334 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x073 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x3fc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5334; op2val:0x3873; +op3val:0x4ffc; valaddr_reg:x5; val_offset:3735*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3735*FLEN/8, x9, x1, x4) + +inst_1270: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x37e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3f4 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x063 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x537e; op2val:0x3bf4; +op3val:0x4463; valaddr_reg:x5; val_offset:3738*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3738*FLEN/8, x9, x1, x4) + +inst_1271: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x37e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3f4 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x063 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x537e; op2val:0x3bf4; +op3val:0x4463; valaddr_reg:x5; val_offset:3741*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3741*FLEN/8, x9, x1, x4) + +inst_1272: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x37e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3f4 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x063 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x537e; op2val:0x3bf4; +op3val:0x4463; valaddr_reg:x5; val_offset:3744*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3744*FLEN/8, x9, x1, x4) + +inst_1273: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x37e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3f4 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x063 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x537e; op2val:0x3bf4; +op3val:0x4463; valaddr_reg:x5; val_offset:3747*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 3747*FLEN/8, x9, x1, x4) + +inst_1274: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x37e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3f4 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x063 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x537e; op2val:0x3bf4; +op3val:0x4463; valaddr_reg:x5; val_offset:3750*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3750*FLEN/8, x9, x1, x4) + +inst_1275: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x015 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x352 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x02d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c15; op2val:0x4352; +op3val:0x442d; valaddr_reg:x5; val_offset:3753*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3753*FLEN/8, x9, x1, x4) + +inst_1276: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x015 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x352 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x02d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c15; op2val:0x4352; +op3val:0x442d; valaddr_reg:x5; val_offset:3756*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3756*FLEN/8, x9, x1, x4) + +inst_1277: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x015 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x352 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x02d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c15; op2val:0x4352; +op3val:0x442d; valaddr_reg:x5; val_offset:3759*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3759*FLEN/8, x9, x1, x4) + +inst_1278: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x015 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x352 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x02d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c15; op2val:0x4352; +op3val:0x442d; valaddr_reg:x5; val_offset:3762*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 3762*FLEN/8, x9, x1, x4) + +inst_1279: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x015 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x352 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x02d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c15; op2val:0x4352; +op3val:0x442d; valaddr_reg:x5; val_offset:3765*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3765*FLEN/8, x9, x1, x4) + +inst_1280: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x282 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x08c and fs3 == 0 and fe3 == 0x11 and fm3 == 0x0ca and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4e82; op2val:0x408c; +op3val:0x44ca; valaddr_reg:x5; val_offset:3768*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3768*FLEN/8, x9, x1, x4) + +inst_1281: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x282 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x08c and fs3 == 0 and fe3 == 0x11 and fm3 == 0x0ca and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4e82; op2val:0x408c; +op3val:0x44ca; valaddr_reg:x5; val_offset:3771*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3771*FLEN/8, x9, x1, x4) + +inst_1282: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x282 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x08c and fs3 == 0 and fe3 == 0x11 and fm3 == 0x0ca and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4e82; op2val:0x408c; +op3val:0x44ca; valaddr_reg:x5; val_offset:3774*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3774*FLEN/8, x9, x1, x4) + +inst_1283: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x282 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x08c and fs3 == 0 and fe3 == 0x11 and fm3 == 0x0ca and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4e82; op2val:0x408c; +op3val:0x44ca; valaddr_reg:x5; val_offset:3777*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 3777*FLEN/8, x9, x1, x4) + +inst_1284: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x282 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x08c and fs3 == 0 and fe3 == 0x11 and fm3 == 0x0ca and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4e82; op2val:0x408c; +op3val:0x44ca; valaddr_reg:x5; val_offset:3780*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3780*FLEN/8, x9, x1, x4) + +inst_1285: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x046 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x05e and fs3 == 0 and fe3 == 0x13 and fm3 == 0x2ab and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c46; op2val:0x405e; +op3val:0x4eab; valaddr_reg:x5; val_offset:3783*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3783*FLEN/8, x9, x1, x4) + +inst_1286: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x046 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x05e and fs3 == 0 and fe3 == 0x13 and fm3 == 0x2ab and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c46; op2val:0x405e; +op3val:0x4eab; valaddr_reg:x5; val_offset:3786*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3786*FLEN/8, x9, x1, x4) + +inst_1287: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x046 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x05e and fs3 == 0 and fe3 == 0x13 and fm3 == 0x2ab and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c46; op2val:0x405e; +op3val:0x4eab; valaddr_reg:x5; val_offset:3789*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3789*FLEN/8, x9, x1, x4) + +inst_1288: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x046 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x05e and fs3 == 0 and fe3 == 0x13 and fm3 == 0x2ab and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c46; op2val:0x405e; +op3val:0x4eab; valaddr_reg:x5; val_offset:3792*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 3792*FLEN/8, x9, x1, x4) + +inst_1289: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x046 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x05e and fs3 == 0 and fe3 == 0x13 and fm3 == 0x2ab and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c46; op2val:0x405e; +op3val:0x4eab; valaddr_reg:x5; val_offset:3795*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3795*FLEN/8, x9, x1, x4) + +inst_1290: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x111 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1e5 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x03c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4d11; op2val:0x41e5; +op3val:0x443c; valaddr_reg:x5; val_offset:3798*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3798*FLEN/8, x9, x1, x4) + +inst_1291: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x111 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1e5 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x03c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4d11; op2val:0x41e5; +op3val:0x443c; valaddr_reg:x5; val_offset:3801*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3801*FLEN/8, x9, x1, x4) + +inst_1292: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x111 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1e5 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x03c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4d11; op2val:0x41e5; +op3val:0x443c; valaddr_reg:x5; val_offset:3804*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3804*FLEN/8, x9, x1, x4) + +inst_1293: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x111 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1e5 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x03c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4d11; op2val:0x41e5; +op3val:0x443c; valaddr_reg:x5; val_offset:3807*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 3807*FLEN/8, x9, x1, x4) + +inst_1294: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x111 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1e5 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x03c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4d11; op2val:0x41e5; +op3val:0x443c; valaddr_reg:x5; val_offset:3810*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3810*FLEN/8, x9, x1, x4) + +inst_1295: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x2bd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x03e and fs3 == 0 and fe3 == 0x14 and fm3 == 0x3c7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x42bd; op2val:0x383e; +op3val:0x53c7; valaddr_reg:x5; val_offset:3813*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3813*FLEN/8, x9, x1, x4) + +inst_1296: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x2bd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x03e and fs3 == 0 and fe3 == 0x14 and fm3 == 0x3c7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x42bd; op2val:0x383e; +op3val:0x53c7; valaddr_reg:x5; val_offset:3816*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3816*FLEN/8, x9, x1, x4) + +inst_1297: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x2bd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x03e and fs3 == 0 and fe3 == 0x14 and fm3 == 0x3c7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x42bd; op2val:0x383e; +op3val:0x53c7; valaddr_reg:x5; val_offset:3819*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3819*FLEN/8, x9, x1, x4) + +inst_1298: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x2bd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x03e and fs3 == 0 and fe3 == 0x14 and fm3 == 0x3c7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x42bd; op2val:0x383e; +op3val:0x53c7; valaddr_reg:x5; val_offset:3822*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 3822*FLEN/8, x9, x1, x4) + +inst_1299: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x2bd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x03e and fs3 == 0 and fe3 == 0x14 and fm3 == 0x3c7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x42bd; op2val:0x383e; +op3val:0x53c7; valaddr_reg:x5; val_offset:3825*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3825*FLEN/8, x9, x1, x4) + +inst_1300: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x226 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x108 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x021 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4a26; op2val:0x4108; +op3val:0x5021; valaddr_reg:x5; val_offset:3828*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3828*FLEN/8, x9, x1, x4) + +inst_1301: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x226 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x108 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x021 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4a26; op2val:0x4108; +op3val:0x5021; valaddr_reg:x5; val_offset:3831*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3831*FLEN/8, x9, x1, x4) + +inst_1302: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x226 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x108 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x021 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4a26; op2val:0x4108; +op3val:0x5021; valaddr_reg:x5; val_offset:3834*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3834*FLEN/8, x9, x1, x4) + +inst_1303: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x226 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x108 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x021 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4a26; op2val:0x4108; +op3val:0x5021; valaddr_reg:x5; val_offset:3837*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 3837*FLEN/8, x9, x1, x4) + +inst_1304: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x226 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x108 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x021 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4a26; op2val:0x4108; +op3val:0x5021; valaddr_reg:x5; val_offset:3840*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3840*FLEN/8, x9, x1, x4) + +inst_1305: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x296 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x07b and fs3 == 0 and fe3 == 0x14 and fm3 == 0x04f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4e96; op2val:0x3c7b; +op3val:0x504f; valaddr_reg:x5; val_offset:3843*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3843*FLEN/8, x9, x1, x4) + +inst_1306: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x296 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x07b and fs3 == 0 and fe3 == 0x14 and fm3 == 0x04f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4e96; op2val:0x3c7b; +op3val:0x504f; valaddr_reg:x5; val_offset:3846*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3846*FLEN/8, x9, x1, x4) + +inst_1307: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x296 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x07b and fs3 == 0 and fe3 == 0x14 and fm3 == 0x04f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4e96; op2val:0x3c7b; +op3val:0x504f; valaddr_reg:x5; val_offset:3849*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3849*FLEN/8, x9, x1, x4) + +inst_1308: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x296 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x07b and fs3 == 0 and fe3 == 0x14 and fm3 == 0x04f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4e96; op2val:0x3c7b; +op3val:0x504f; valaddr_reg:x5; val_offset:3852*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 3852*FLEN/8, x9, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_11) + +inst_1309: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x296 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x07b and fs3 == 0 and fe3 == 0x14 and fm3 == 0x04f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4e96; op2val:0x3c7b; +op3val:0x504f; valaddr_reg:x5; val_offset:3855*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3855*FLEN/8, x9, x1, x4) + +inst_1310: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x250 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x2d8 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x131 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4650; op2val:0x46d8; +op3val:0x4d31; valaddr_reg:x5; val_offset:3858*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3858*FLEN/8, x9, x1, x4) + +inst_1311: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x250 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x2d8 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x131 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4650; op2val:0x46d8; +op3val:0x4d31; valaddr_reg:x5; val_offset:3861*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3861*FLEN/8, x9, x1, x4) + +inst_1312: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x250 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x2d8 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x131 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4650; op2val:0x46d8; +op3val:0x4d31; valaddr_reg:x5; val_offset:3864*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3864*FLEN/8, x9, x1, x4) + +inst_1313: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x250 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x2d8 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x131 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4650; op2val:0x46d8; +op3val:0x4d31; valaddr_reg:x5; val_offset:3867*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 3867*FLEN/8, x9, x1, x4) + +inst_1314: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x250 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x2d8 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x131 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4650; op2val:0x46d8; +op3val:0x4d31; valaddr_reg:x5; val_offset:3870*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3870*FLEN/8, x9, x1, x4) + +inst_1315: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x3cd and fs2 == 0 and fe2 == 0x10 and fm2 == 0x365 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x064 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x47cd; op2val:0x4365; +op3val:0x5064; valaddr_reg:x5; val_offset:3873*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3873*FLEN/8, x9, x1, x4) + +inst_1316: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x3cd and fs2 == 0 and fe2 == 0x10 and fm2 == 0x365 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x064 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x47cd; op2val:0x4365; +op3val:0x5064; valaddr_reg:x5; val_offset:3876*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3876*FLEN/8, x9, x1, x4) + +inst_1317: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x3cd and fs2 == 0 and fe2 == 0x10 and fm2 == 0x365 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x064 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x47cd; op2val:0x4365; +op3val:0x5064; valaddr_reg:x5; val_offset:3879*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3879*FLEN/8, x9, x1, x4) + +inst_1318: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x3cd and fs2 == 0 and fe2 == 0x10 and fm2 == 0x365 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x064 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x47cd; op2val:0x4365; +op3val:0x5064; valaddr_reg:x5; val_offset:3882*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 3882*FLEN/8, x9, x1, x4) + +inst_1319: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x3cd and fs2 == 0 and fe2 == 0x10 and fm2 == 0x365 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x064 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x47cd; op2val:0x4365; +op3val:0x5064; valaddr_reg:x5; val_offset:3885*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3885*FLEN/8, x9, x1, x4) + +inst_1320: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x361 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2db and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0d6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5361; op2val:0x36db; +op3val:0x50d6; valaddr_reg:x5; val_offset:3888*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3888*FLEN/8, x9, x1, x4) + +inst_1321: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x361 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2db and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0d6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5361; op2val:0x36db; +op3val:0x50d6; valaddr_reg:x5; val_offset:3891*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3891*FLEN/8, x9, x1, x4) + +inst_1322: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x361 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2db and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0d6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5361; op2val:0x36db; +op3val:0x50d6; valaddr_reg:x5; val_offset:3894*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3894*FLEN/8, x9, x1, x4) + +inst_1323: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x361 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2db and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0d6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5361; op2val:0x36db; +op3val:0x50d6; valaddr_reg:x5; val_offset:3897*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 3897*FLEN/8, x9, x1, x4) + +inst_1324: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x361 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2db and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0d6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5361; op2val:0x36db; +op3val:0x50d6; valaddr_reg:x5; val_offset:3900*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3900*FLEN/8, x9, x1, x4) + +inst_1325: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2df and fs2 == 0 and fe2 == 0x0e and fm2 == 0x333 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x341 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x52df; op2val:0x3b33; +op3val:0x4b41; valaddr_reg:x5; val_offset:3903*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3903*FLEN/8, x9, x1, x4) + +inst_1326: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2df and fs2 == 0 and fe2 == 0x0e and fm2 == 0x333 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x341 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x52df; op2val:0x3b33; +op3val:0x4b41; valaddr_reg:x5; val_offset:3906*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3906*FLEN/8, x9, x1, x4) + +inst_1327: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2df and fs2 == 0 and fe2 == 0x0e and fm2 == 0x333 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x341 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x52df; op2val:0x3b33; +op3val:0x4b41; valaddr_reg:x5; val_offset:3909*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3909*FLEN/8, x9, x1, x4) + +inst_1328: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2df and fs2 == 0 and fe2 == 0x0e and fm2 == 0x333 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x341 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x52df; op2val:0x3b33; +op3val:0x4b41; valaddr_reg:x5; val_offset:3912*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 3912*FLEN/8, x9, x1, x4) + +inst_1329: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2df and fs2 == 0 and fe2 == 0x0e and fm2 == 0x333 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x341 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x52df; op2val:0x3b33; +op3val:0x4b41; valaddr_reg:x5; val_offset:3915*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3915*FLEN/8, x9, x1, x4) + +inst_1330: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x031 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x2ea and fs3 == 0 and fe3 == 0x14 and fm3 == 0x05f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4031; op2val:0x4aea; +op3val:0x505f; valaddr_reg:x5; val_offset:3918*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3918*FLEN/8, x9, x1, x4) + +inst_1331: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x031 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x2ea and fs3 == 0 and fe3 == 0x14 and fm3 == 0x05f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4031; op2val:0x4aea; +op3val:0x505f; valaddr_reg:x5; val_offset:3921*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3921*FLEN/8, x9, x1, x4) + +inst_1332: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x031 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x2ea and fs3 == 0 and fe3 == 0x14 and fm3 == 0x05f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4031; op2val:0x4aea; +op3val:0x505f; valaddr_reg:x5; val_offset:3924*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3924*FLEN/8, x9, x1, x4) + +inst_1333: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x031 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x2ea and fs3 == 0 and fe3 == 0x14 and fm3 == 0x05f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4031; op2val:0x4aea; +op3val:0x505f; valaddr_reg:x5; val_offset:3927*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 3927*FLEN/8, x9, x1, x4) + +inst_1334: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x031 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x2ea and fs3 == 0 and fe3 == 0x14 and fm3 == 0x05f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4031; op2val:0x4aea; +op3val:0x505f; valaddr_reg:x5; val_offset:3930*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3930*FLEN/8, x9, x1, x4) + +inst_1335: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3e9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d3 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0a0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4fe9; op2val:0x3ad3; +op3val:0x50a0; valaddr_reg:x5; val_offset:3933*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3933*FLEN/8, x9, x1, x4) + +inst_1336: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3e9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d3 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0a0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4fe9; op2val:0x3ad3; +op3val:0x50a0; valaddr_reg:x5; val_offset:3936*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3936*FLEN/8, x9, x1, x4) + +inst_1337: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3e9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d3 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0a0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4fe9; op2val:0x3ad3; +op3val:0x50a0; valaddr_reg:x5; val_offset:3939*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3939*FLEN/8, x9, x1, x4) + +inst_1338: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3e9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d3 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0a0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4fe9; op2val:0x3ad3; +op3val:0x50a0; valaddr_reg:x5; val_offset:3942*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 3942*FLEN/8, x9, x1, x4) + +inst_1339: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3e9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d3 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0a0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4fe9; op2val:0x3ad3; +op3val:0x50a0; valaddr_reg:x5; val_offset:3945*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3945*FLEN/8, x9, x1, x4) + +inst_1340: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x22e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3a4 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x10c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4e2e; op2val:0x3ba4; +op3val:0x510c; valaddr_reg:x5; val_offset:3948*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3948*FLEN/8, x9, x1, x4) + +inst_1341: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x22e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3a4 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x10c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4e2e; op2val:0x3ba4; +op3val:0x510c; valaddr_reg:x5; val_offset:3951*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3951*FLEN/8, x9, x1, x4) + +inst_1342: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x22e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3a4 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x10c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4e2e; op2val:0x3ba4; +op3val:0x510c; valaddr_reg:x5; val_offset:3954*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3954*FLEN/8, x9, x1, x4) + +inst_1343: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x22e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3a4 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x10c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4e2e; op2val:0x3ba4; +op3val:0x510c; valaddr_reg:x5; val_offset:3957*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 3957*FLEN/8, x9, x1, x4) + +inst_1344: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x22e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3a4 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x10c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4e2e; op2val:0x3ba4; +op3val:0x510c; valaddr_reg:x5; val_offset:3960*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3960*FLEN/8, x9, x1, x4) + +inst_1345: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1d7 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x382 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x350 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x51d7; op2val:0x2f82; +op3val:0x5350; valaddr_reg:x5; val_offset:3963*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3963*FLEN/8, x9, x1, x4) + +inst_1346: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1d7 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x382 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x350 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x51d7; op2val:0x2f82; +op3val:0x5350; valaddr_reg:x5; val_offset:3966*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3966*FLEN/8, x9, x1, x4) + +inst_1347: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1d7 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x382 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x350 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x51d7; op2val:0x2f82; +op3val:0x5350; valaddr_reg:x5; val_offset:3969*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3969*FLEN/8, x9, x1, x4) + +inst_1348: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1d7 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x382 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x350 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x51d7; op2val:0x2f82; +op3val:0x5350; valaddr_reg:x5; val_offset:3972*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 3972*FLEN/8, x9, x1, x4) + +inst_1349: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1d7 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x382 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x350 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x51d7; op2val:0x2f82; +op3val:0x5350; valaddr_reg:x5; val_offset:3975*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3975*FLEN/8, x9, x1, x4) + +inst_1350: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x118 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2d0 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x352 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4d18; op2val:0x3ed0; +op3val:0x4f52; valaddr_reg:x5; val_offset:3978*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3978*FLEN/8, x9, x1, x4) + +inst_1351: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x118 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2d0 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x352 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4d18; op2val:0x3ed0; +op3val:0x4f52; valaddr_reg:x5; val_offset:3981*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3981*FLEN/8, x9, x1, x4) + +inst_1352: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x118 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2d0 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x352 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4d18; op2val:0x3ed0; +op3val:0x4f52; valaddr_reg:x5; val_offset:3984*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3984*FLEN/8, x9, x1, x4) + +inst_1353: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x118 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2d0 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x352 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4d18; op2val:0x3ed0; +op3val:0x4f52; valaddr_reg:x5; val_offset:3987*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 3987*FLEN/8, x9, x1, x4) + +inst_1354: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x118 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2d0 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x352 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4d18; op2val:0x3ed0; +op3val:0x4f52; valaddr_reg:x5; val_offset:3990*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 3990*FLEN/8, x9, x1, x4) + +inst_1355: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2a2 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x35e and fs3 == 0 and fe3 == 0x12 and fm3 == 0x38e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x52a2; op2val:0x3b5e; +op3val:0x4b8e; valaddr_reg:x5; val_offset:3993*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 3993*FLEN/8, x9, x1, x4) + +inst_1356: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2a2 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x35e and fs3 == 0 and fe3 == 0x12 and fm3 == 0x38e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x52a2; op2val:0x3b5e; +op3val:0x4b8e; valaddr_reg:x5; val_offset:3996*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 3996*FLEN/8, x9, x1, x4) + +inst_1357: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2a2 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x35e and fs3 == 0 and fe3 == 0x12 and fm3 == 0x38e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x52a2; op2val:0x3b5e; +op3val:0x4b8e; valaddr_reg:x5; val_offset:3999*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 3999*FLEN/8, x9, x1, x4) + +inst_1358: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2a2 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x35e and fs3 == 0 and fe3 == 0x12 and fm3 == 0x38e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x52a2; op2val:0x3b5e; +op3val:0x4b8e; valaddr_reg:x5; val_offset:4002*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4002*FLEN/8, x9, x1, x4) + +inst_1359: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2a2 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x35e and fs3 == 0 and fe3 == 0x12 and fm3 == 0x38e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x52a2; op2val:0x3b5e; +op3val:0x4b8e; valaddr_reg:x5; val_offset:4005*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4005*FLEN/8, x9, x1, x4) + +inst_1360: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x025 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x13b and fs3 == 0 and fe3 == 0x13 and fm3 == 0x129 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4825; op2val:0x453b; +op3val:0x4d29; valaddr_reg:x5; val_offset:4008*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 4008*FLEN/8, x9, x1, x4) + +inst_1361: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x025 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x13b and fs3 == 0 and fe3 == 0x13 and fm3 == 0x129 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4825; op2val:0x453b; +op3val:0x4d29; valaddr_reg:x5; val_offset:4011*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 4011*FLEN/8, x9, x1, x4) + +inst_1362: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x025 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x13b and fs3 == 0 and fe3 == 0x13 and fm3 == 0x129 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4825; op2val:0x453b; +op3val:0x4d29; valaddr_reg:x5; val_offset:4014*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 4014*FLEN/8, x9, x1, x4) + +inst_1363: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x025 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x13b and fs3 == 0 and fe3 == 0x13 and fm3 == 0x129 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4825; op2val:0x453b; +op3val:0x4d29; valaddr_reg:x5; val_offset:4017*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4017*FLEN/8, x9, x1, x4) + +inst_1364: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x025 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x13b and fs3 == 0 and fe3 == 0x13 and fm3 == 0x129 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4825; op2val:0x453b; +op3val:0x4d29; valaddr_reg:x5; val_offset:4020*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4020*FLEN/8, x9, x1, x4) + +inst_1365: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x285 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x065 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x235 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4685; op2val:0x4065; +op3val:0x5235; valaddr_reg:x5; val_offset:4023*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 4023*FLEN/8, x9, x1, x4) + +inst_1366: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x285 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x065 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x235 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4685; op2val:0x4065; +op3val:0x5235; valaddr_reg:x5; val_offset:4026*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 4026*FLEN/8, x9, x1, x4) + +inst_1367: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x285 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x065 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x235 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4685; op2val:0x4065; +op3val:0x5235; valaddr_reg:x5; val_offset:4029*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 4029*FLEN/8, x9, x1, x4) + +inst_1368: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x285 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x065 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x235 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4685; op2val:0x4065; +op3val:0x5235; valaddr_reg:x5; val_offset:4032*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4032*FLEN/8, x9, x1, x4) + +inst_1369: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x285 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x065 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x235 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4685; op2val:0x4065; +op3val:0x5235; valaddr_reg:x5; val_offset:4035*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4035*FLEN/8, x9, x1, x4) + +inst_1370: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x294 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x294 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x12d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5294; op2val:0x3a94; +op3val:0x4d2d; valaddr_reg:x5; val_offset:4038*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 4038*FLEN/8, x9, x1, x4) + +inst_1371: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x294 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x294 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x12d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5294; op2val:0x3a94; +op3val:0x4d2d; valaddr_reg:x5; val_offset:4041*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 4041*FLEN/8, x9, x1, x4) + +inst_1372: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x294 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x294 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x12d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5294; op2val:0x3a94; +op3val:0x4d2d; valaddr_reg:x5; val_offset:4044*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 4044*FLEN/8, x9, x1, x4) + +inst_1373: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x294 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x294 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x12d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5294; op2val:0x3a94; +op3val:0x4d2d; valaddr_reg:x5; val_offset:4047*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4047*FLEN/8, x9, x1, x4) + +inst_1374: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x294 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x294 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x12d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5294; op2val:0x3a94; +op3val:0x4d2d; valaddr_reg:x5; val_offset:4050*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4050*FLEN/8, x9, x1, x4) + +inst_1375: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x097 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x24d and fs3 == 0 and fe3 == 0x11 and fm3 == 0x22a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4897; op2val:0x464d; +op3val:0x462a; valaddr_reg:x5; val_offset:4053*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 4053*FLEN/8, x9, x1, x4) + +inst_1376: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x097 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x24d and fs3 == 0 and fe3 == 0x11 and fm3 == 0x22a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4897; op2val:0x464d; +op3val:0x462a; valaddr_reg:x5; val_offset:4056*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 4056*FLEN/8, x9, x1, x4) + +inst_1377: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x097 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x24d and fs3 == 0 and fe3 == 0x11 and fm3 == 0x22a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4897; op2val:0x464d; +op3val:0x462a; valaddr_reg:x5; val_offset:4059*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 4059*FLEN/8, x9, x1, x4) + +inst_1378: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x097 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x24d and fs3 == 0 and fe3 == 0x11 and fm3 == 0x22a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4897; op2val:0x464d; +op3val:0x462a; valaddr_reg:x5; val_offset:4062*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4062*FLEN/8, x9, x1, x4) + +inst_1379: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x097 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x24d and fs3 == 0 and fe3 == 0x11 and fm3 == 0x22a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4897; op2val:0x464d; +op3val:0x462a; valaddr_reg:x5; val_offset:4065*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4065*FLEN/8, x9, x1, x4) + +inst_1380: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x01b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x306 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x250 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c1b; op2val:0x4306; +op3val:0x4650; valaddr_reg:x5; val_offset:4068*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 4068*FLEN/8, x9, x1, x4) + +inst_1381: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x01b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x306 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x250 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c1b; op2val:0x4306; +op3val:0x4650; valaddr_reg:x5; val_offset:4071*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 4071*FLEN/8, x9, x1, x4) + +inst_1382: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x01b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x306 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x250 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c1b; op2val:0x4306; +op3val:0x4650; valaddr_reg:x5; val_offset:4074*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 4074*FLEN/8, x9, x1, x4) + +inst_1383: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x01b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x306 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x250 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c1b; op2val:0x4306; +op3val:0x4650; valaddr_reg:x5; val_offset:4077*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4077*FLEN/8, x9, x1, x4) + +inst_1384: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x01b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x306 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x250 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c1b; op2val:0x4306; +op3val:0x4650; valaddr_reg:x5; val_offset:4080*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4080*FLEN/8, x9, x1, x4) + +inst_1385: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x300 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x39c and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0ab and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4f00; op2val:0x3b9c; +op3val:0x50ab; valaddr_reg:x5; val_offset:4083*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 4083*FLEN/8, x9, x1, x4) + +inst_1386: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x300 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x39c and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0ab and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4f00; op2val:0x3b9c; +op3val:0x50ab; valaddr_reg:x5; val_offset:4086*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 4086*FLEN/8, x9, x1, x4) + +inst_1387: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x300 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x39c and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0ab and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4f00; op2val:0x3b9c; +op3val:0x50ab; valaddr_reg:x5; val_offset:4089*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 4089*FLEN/8, x9, x1, x4) + +inst_1388: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x300 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x39c and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0ab and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4f00; op2val:0x3b9c; +op3val:0x50ab; valaddr_reg:x5; val_offset:4092*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4092*FLEN/8, x9, x1, x4) + +inst_1389: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x300 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x39c and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0ab and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4f00; op2val:0x3b9c; +op3val:0x50ab; valaddr_reg:x5; val_offset:4095*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4095*FLEN/8, x9, x1, x4) + +inst_1390: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x01d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x32f and fs3 == 0 and fe3 == 0x11 and fm3 == 0x0df and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c1d; op2val:0x432f; +op3val:0x44df; valaddr_reg:x5; val_offset:4098*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 4098*FLEN/8, x9, x1, x4) + +inst_1391: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x01d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x32f and fs3 == 0 and fe3 == 0x11 and fm3 == 0x0df and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c1d; op2val:0x432f; +op3val:0x44df; valaddr_reg:x5; val_offset:4101*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 4101*FLEN/8, x9, x1, x4) + +inst_1392: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x01d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x32f and fs3 == 0 and fe3 == 0x11 and fm3 == 0x0df and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c1d; op2val:0x432f; +op3val:0x44df; valaddr_reg:x5; val_offset:4104*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 4104*FLEN/8, x9, x1, x4) + +inst_1393: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x01d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x32f and fs3 == 0 and fe3 == 0x11 and fm3 == 0x0df and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c1d; op2val:0x432f; +op3val:0x44df; valaddr_reg:x5; val_offset:4107*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4107*FLEN/8, x9, x1, x4) + +inst_1394: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x01d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x32f and fs3 == 0 and fe3 == 0x11 and fm3 == 0x0df and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c1d; op2val:0x432f; +op3val:0x44df; valaddr_reg:x5; val_offset:4110*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4110*FLEN/8, x9, x1, x4) + +inst_1395: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1a4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x150 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x006 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x51a4; op2val:0x3d50; +op3val:0x4406; valaddr_reg:x5; val_offset:4113*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 4113*FLEN/8, x9, x1, x4) + +inst_1396: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1a4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x150 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x006 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x51a4; op2val:0x3d50; +op3val:0x4406; valaddr_reg:x5; val_offset:4116*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 4116*FLEN/8, x9, x1, x4) + +inst_1397: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1a4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x150 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x006 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x51a4; op2val:0x3d50; +op3val:0x4406; valaddr_reg:x5; val_offset:4119*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 4119*FLEN/8, x9, x1, x4) + +inst_1398: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1a4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x150 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x006 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x51a4; op2val:0x3d50; +op3val:0x4406; valaddr_reg:x5; val_offset:4122*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4122*FLEN/8, x9, x1, x4) + +inst_1399: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1a4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x150 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x006 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x51a4; op2val:0x3d50; +op3val:0x4406; valaddr_reg:x5; val_offset:4125*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4125*FLEN/8, x9, x1, x4) + +inst_1400: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x2cb and fs2 == 0 and fe2 == 0x10 and fm2 == 0x29e and fs3 == 0 and fe3 == 0x13 and fm3 == 0x0c1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4acb; op2val:0x429e; +op3val:0x4cc1; valaddr_reg:x5; val_offset:4128*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 4128*FLEN/8, x9, x1, x4) + +inst_1401: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x2cb and fs2 == 0 and fe2 == 0x10 and fm2 == 0x29e and fs3 == 0 and fe3 == 0x13 and fm3 == 0x0c1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4acb; op2val:0x429e; +op3val:0x4cc1; valaddr_reg:x5; val_offset:4131*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 4131*FLEN/8, x9, x1, x4) + +inst_1402: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x2cb and fs2 == 0 and fe2 == 0x10 and fm2 == 0x29e and fs3 == 0 and fe3 == 0x13 and fm3 == 0x0c1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4acb; op2val:0x429e; +op3val:0x4cc1; valaddr_reg:x5; val_offset:4134*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 4134*FLEN/8, x9, x1, x4) + +inst_1403: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x2cb and fs2 == 0 and fe2 == 0x10 and fm2 == 0x29e and fs3 == 0 and fe3 == 0x13 and fm3 == 0x0c1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4acb; op2val:0x429e; +op3val:0x4cc1; valaddr_reg:x5; val_offset:4137*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4137*FLEN/8, x9, x1, x4) + +inst_1404: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x2cb and fs2 == 0 and fe2 == 0x10 and fm2 == 0x29e and fs3 == 0 and fe3 == 0x13 and fm3 == 0x0c1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4acb; op2val:0x429e; +op3val:0x4cc1; valaddr_reg:x5; val_offset:4140*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4140*FLEN/8, x9, x1, x4) + +inst_1405: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x223 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0a0 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x335 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4e23; op2val:0x40a0; +op3val:0x4735; valaddr_reg:x5; val_offset:4143*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 4143*FLEN/8, x9, x1, x4) + +inst_1406: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x223 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0a0 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x335 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4e23; op2val:0x40a0; +op3val:0x4735; valaddr_reg:x5; val_offset:4146*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 4146*FLEN/8, x9, x1, x4) + +inst_1407: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x223 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0a0 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x335 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4e23; op2val:0x40a0; +op3val:0x4735; valaddr_reg:x5; val_offset:4149*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 4149*FLEN/8, x9, x1, x4) + +inst_1408: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x223 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0a0 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x335 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4e23; op2val:0x40a0; +op3val:0x4735; valaddr_reg:x5; val_offset:4152*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4152*FLEN/8, x9, x1, x4) + +inst_1409: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x223 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0a0 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x335 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4e23; op2val:0x40a0; +op3val:0x4735; valaddr_reg:x5; val_offset:4155*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4155*FLEN/8, x9, x1, x4) + +inst_1410: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x2df and fs2 == 0 and fe2 == 0x0f and fm2 == 0x249 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x131 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4edf; op2val:0x3e49; +op3val:0x4d31; valaddr_reg:x5; val_offset:4158*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 4158*FLEN/8, x9, x1, x4) + +inst_1411: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x2df and fs2 == 0 and fe2 == 0x0f and fm2 == 0x249 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x131 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4edf; op2val:0x3e49; +op3val:0x4d31; valaddr_reg:x5; val_offset:4161*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 4161*FLEN/8, x9, x1, x4) + +inst_1412: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x2df and fs2 == 0 and fe2 == 0x0f and fm2 == 0x249 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x131 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4edf; op2val:0x3e49; +op3val:0x4d31; valaddr_reg:x5; val_offset:4164*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 4164*FLEN/8, x9, x1, x4) + +inst_1413: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x2df and fs2 == 0 and fe2 == 0x0f and fm2 == 0x249 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x131 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4edf; op2val:0x3e49; +op3val:0x4d31; valaddr_reg:x5; val_offset:4167*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4167*FLEN/8, x9, x1, x4) + +inst_1414: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x2df and fs2 == 0 and fe2 == 0x0f and fm2 == 0x249 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x131 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4edf; op2val:0x3e49; +op3val:0x4d31; valaddr_reg:x5; val_offset:4170*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4170*FLEN/8, x9, x1, x4) + +inst_1415: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x20c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x09f and fs3 == 0 and fe3 == 0x14 and fm3 == 0x081 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x520c; op2val:0x389f; +op3val:0x5081; valaddr_reg:x5; val_offset:4173*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 4173*FLEN/8, x9, x1, x4) + +inst_1416: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x20c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x09f and fs3 == 0 and fe3 == 0x14 and fm3 == 0x081 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x520c; op2val:0x389f; +op3val:0x5081; valaddr_reg:x5; val_offset:4176*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 4176*FLEN/8, x9, x1, x4) + +inst_1417: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x20c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x09f and fs3 == 0 and fe3 == 0x14 and fm3 == 0x081 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x520c; op2val:0x389f; +op3val:0x5081; valaddr_reg:x5; val_offset:4179*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 4179*FLEN/8, x9, x1, x4) + +inst_1418: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x20c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x09f and fs3 == 0 and fe3 == 0x14 and fm3 == 0x081 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x520c; op2val:0x389f; +op3val:0x5081; valaddr_reg:x5; val_offset:4182*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4182*FLEN/8, x9, x1, x4) + +inst_1419: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x20c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x09f and fs3 == 0 and fe3 == 0x14 and fm3 == 0x081 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x520c; op2val:0x389f; +op3val:0x5081; valaddr_reg:x5; val_offset:4185*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4185*FLEN/8, x9, x1, x4) + +inst_1420: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x32e and fs2 == 0 and fe2 == 0x0d and fm2 == 0x211 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x146 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x532e; op2val:0x3611; +op3val:0x5146; valaddr_reg:x5; val_offset:4188*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 4188*FLEN/8, x9, x1, x4) + +inst_1421: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x32e and fs2 == 0 and fe2 == 0x0d and fm2 == 0x211 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x146 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x532e; op2val:0x3611; +op3val:0x5146; valaddr_reg:x5; val_offset:4191*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 4191*FLEN/8, x9, x1, x4) + +inst_1422: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x32e and fs2 == 0 and fe2 == 0x0d and fm2 == 0x211 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x146 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x532e; op2val:0x3611; +op3val:0x5146; valaddr_reg:x5; val_offset:4194*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 4194*FLEN/8, x9, x1, x4) + +inst_1423: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x32e and fs2 == 0 and fe2 == 0x0d and fm2 == 0x211 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x146 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x532e; op2val:0x3611; +op3val:0x5146; valaddr_reg:x5; val_offset:4197*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4197*FLEN/8, x9, x1, x4) + +inst_1424: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x32e and fs2 == 0 and fe2 == 0x0d and fm2 == 0x211 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x146 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x532e; op2val:0x3611; +op3val:0x5146; valaddr_reg:x5; val_offset:4200*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4200*FLEN/8, x9, x1, x4) + +inst_1425: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x21b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x062 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0a6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x521b; op2val:0x3862; +op3val:0x50a6; valaddr_reg:x5; val_offset:4203*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 4203*FLEN/8, x9, x1, x4) + +inst_1426: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x21b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x062 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0a6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x521b; op2val:0x3862; +op3val:0x50a6; valaddr_reg:x5; val_offset:4206*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 4206*FLEN/8, x9, x1, x4) + +inst_1427: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x21b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x062 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0a6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x521b; op2val:0x3862; +op3val:0x50a6; valaddr_reg:x5; val_offset:4209*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 4209*FLEN/8, x9, x1, x4) + +inst_1428: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x21b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x062 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0a6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x521b; op2val:0x3862; +op3val:0x50a6; valaddr_reg:x5; val_offset:4212*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4212*FLEN/8, x9, x1, x4) + +inst_1429: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x21b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x062 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0a6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x521b; op2val:0x3862; +op3val:0x50a6; valaddr_reg:x5; val_offset:4215*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4215*FLEN/8, x9, x1, x4) + +inst_1430: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x337 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x266 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x28e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4f37; op2val:0x3666; +op3val:0x528e; valaddr_reg:x5; val_offset:4218*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 4218*FLEN/8, x9, x1, x4) + +inst_1431: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x337 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x266 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x28e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4f37; op2val:0x3666; +op3val:0x528e; valaddr_reg:x5; val_offset:4221*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 4221*FLEN/8, x9, x1, x4) + +inst_1432: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x337 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x266 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x28e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4f37; op2val:0x3666; +op3val:0x528e; valaddr_reg:x5; val_offset:4224*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 4224*FLEN/8, x9, x1, x4) + +inst_1433: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x337 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x266 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x28e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4f37; op2val:0x3666; +op3val:0x528e; valaddr_reg:x5; val_offset:4227*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4227*FLEN/8, x9, x1, x4) + +inst_1434: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x337 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x266 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x28e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4f37; op2val:0x3666; +op3val:0x528e; valaddr_reg:x5; val_offset:4230*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4230*FLEN/8, x9, x1, x4) + +inst_1435: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x149 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x04f and fs3 == 0 and fe3 == 0x14 and fm3 == 0x3a5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5149; op2val:0x2c4f; +op3val:0x53a5; valaddr_reg:x5; val_offset:4233*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 4233*FLEN/8, x9, x1, x4) + +inst_1436: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x149 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x04f and fs3 == 0 and fe3 == 0x14 and fm3 == 0x3a5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5149; op2val:0x2c4f; +op3val:0x53a5; valaddr_reg:x5; val_offset:4236*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 4236*FLEN/8, x9, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_12) + +inst_1437: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x149 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x04f and fs3 == 0 and fe3 == 0x14 and fm3 == 0x3a5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5149; op2val:0x2c4f; +op3val:0x53a5; valaddr_reg:x5; val_offset:4239*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 4239*FLEN/8, x9, x1, x4) + +inst_1438: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x149 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x04f and fs3 == 0 and fe3 == 0x14 and fm3 == 0x3a5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5149; op2val:0x2c4f; +op3val:0x53a5; valaddr_reg:x5; val_offset:4242*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4242*FLEN/8, x9, x1, x4) + +inst_1439: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x149 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x04f and fs3 == 0 and fe3 == 0x14 and fm3 == 0x3a5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5149; op2val:0x2c4f; +op3val:0x53a5; valaddr_reg:x5; val_offset:4245*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4245*FLEN/8, x9, x1, x4) + +inst_1440: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1db and fs2 == 0 and fe2 == 0x0d and fm2 == 0x26d and fs3 == 0 and fe3 == 0x14 and fm3 == 0x1a5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x51db; op2val:0x366d; +op3val:0x51a5; valaddr_reg:x5; val_offset:4248*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 4248*FLEN/8, x9, x1, x4) + +inst_1441: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1db and fs2 == 0 and fe2 == 0x0d and fm2 == 0x26d and fs3 == 0 and fe3 == 0x14 and fm3 == 0x1a5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x51db; op2val:0x366d; +op3val:0x51a5; valaddr_reg:x5; val_offset:4251*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 4251*FLEN/8, x9, x1, x4) + +inst_1442: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1db and fs2 == 0 and fe2 == 0x0d and fm2 == 0x26d and fs3 == 0 and fe3 == 0x14 and fm3 == 0x1a5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x51db; op2val:0x366d; +op3val:0x51a5; valaddr_reg:x5; val_offset:4254*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 4254*FLEN/8, x9, x1, x4) + +inst_1443: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1db and fs2 == 0 and fe2 == 0x0d and fm2 == 0x26d and fs3 == 0 and fe3 == 0x14 and fm3 == 0x1a5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x51db; op2val:0x366d; +op3val:0x51a5; valaddr_reg:x5; val_offset:4257*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4257*FLEN/8, x9, x1, x4) + +inst_1444: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1db and fs2 == 0 and fe2 == 0x0d and fm2 == 0x26d and fs3 == 0 and fe3 == 0x14 and fm3 == 0x1a5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x51db; op2val:0x366d; +op3val:0x51a5; valaddr_reg:x5; val_offset:4260*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4260*FLEN/8, x9, x1, x4) + +inst_1445: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x077 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x14d and fs3 == 0 and fe3 == 0x14 and fm3 == 0x285 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c77; op2val:0x394d; +op3val:0x5285; valaddr_reg:x5; val_offset:4263*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 4263*FLEN/8, x9, x1, x4) + +inst_1446: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x077 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x14d and fs3 == 0 and fe3 == 0x14 and fm3 == 0x285 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c77; op2val:0x394d; +op3val:0x5285; valaddr_reg:x5; val_offset:4266*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 4266*FLEN/8, x9, x1, x4) + +inst_1447: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x077 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x14d and fs3 == 0 and fe3 == 0x14 and fm3 == 0x285 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c77; op2val:0x394d; +op3val:0x5285; valaddr_reg:x5; val_offset:4269*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 4269*FLEN/8, x9, x1, x4) + +inst_1448: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x077 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x14d and fs3 == 0 and fe3 == 0x14 and fm3 == 0x285 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c77; op2val:0x394d; +op3val:0x5285; valaddr_reg:x5; val_offset:4272*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4272*FLEN/8, x9, x1, x4) + +inst_1449: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x077 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x14d and fs3 == 0 and fe3 == 0x14 and fm3 == 0x285 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c77; op2val:0x394d; +op3val:0x5285; valaddr_reg:x5; val_offset:4275*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4275*FLEN/8, x9, x1, x4) + +inst_1450: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x246 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x05e and fs3 == 0 and fe3 == 0x12 and fm3 == 0x09a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4e46; op2val:0x405e; +op3val:0x489a; valaddr_reg:x5; val_offset:4278*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 4278*FLEN/8, x9, x1, x4) + +inst_1451: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x246 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x05e and fs3 == 0 and fe3 == 0x12 and fm3 == 0x09a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4e46; op2val:0x405e; +op3val:0x489a; valaddr_reg:x5; val_offset:4281*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 4281*FLEN/8, x9, x1, x4) + +inst_1452: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x246 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x05e and fs3 == 0 and fe3 == 0x12 and fm3 == 0x09a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4e46; op2val:0x405e; +op3val:0x489a; valaddr_reg:x5; val_offset:4284*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 4284*FLEN/8, x9, x1, x4) + +inst_1453: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x246 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x05e and fs3 == 0 and fe3 == 0x12 and fm3 == 0x09a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4e46; op2val:0x405e; +op3val:0x489a; valaddr_reg:x5; val_offset:4287*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4287*FLEN/8, x9, x1, x4) + +inst_1454: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x246 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x05e and fs3 == 0 and fe3 == 0x12 and fm3 == 0x09a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4e46; op2val:0x405e; +op3val:0x489a; valaddr_reg:x5; val_offset:4290*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4290*FLEN/8, x9, x1, x4) + +inst_1455: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x127 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x113 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x1d6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4527; op2val:0x4913; +op3val:0x49d6; valaddr_reg:x5; val_offset:4293*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 4293*FLEN/8, x9, x1, x4) + +inst_1456: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x127 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x113 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x1d6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4527; op2val:0x4913; +op3val:0x49d6; valaddr_reg:x5; val_offset:4296*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 4296*FLEN/8, x9, x1, x4) + +inst_1457: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x127 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x113 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x1d6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4527; op2val:0x4913; +op3val:0x49d6; valaddr_reg:x5; val_offset:4299*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 4299*FLEN/8, x9, x1, x4) + +inst_1458: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x127 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x113 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x1d6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4527; op2val:0x4913; +op3val:0x49d6; valaddr_reg:x5; val_offset:4302*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4302*FLEN/8, x9, x1, x4) + +inst_1459: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x127 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x113 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x1d6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4527; op2val:0x4913; +op3val:0x49d6; valaddr_reg:x5; val_offset:4305*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4305*FLEN/8, x9, x1, x4) + +inst_1460: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x063 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0a7 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x172 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c63; op2val:0x3ca7; +op3val:0x5172; valaddr_reg:x5; val_offset:4308*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 4308*FLEN/8, x9, x1, x4) + +inst_1461: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x063 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0a7 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x172 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c63; op2val:0x3ca7; +op3val:0x5172; valaddr_reg:x5; val_offset:4311*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 4311*FLEN/8, x9, x1, x4) + +inst_1462: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x063 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0a7 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x172 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c63; op2val:0x3ca7; +op3val:0x5172; valaddr_reg:x5; val_offset:4314*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 4314*FLEN/8, x9, x1, x4) + +inst_1463: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x063 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0a7 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x172 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c63; op2val:0x3ca7; +op3val:0x5172; valaddr_reg:x5; val_offset:4317*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4317*FLEN/8, x9, x1, x4) + +inst_1464: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x063 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0a7 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x172 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c63; op2val:0x3ca7; +op3val:0x5172; valaddr_reg:x5; val_offset:4320*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4320*FLEN/8, x9, x1, x4) + +inst_1465: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x0bf and fs2 == 0 and fe2 == 0x10 and fm2 == 0x236 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4cbf; op2val:0x4236; +op3val:0x4500; valaddr_reg:x5; val_offset:4323*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 4323*FLEN/8, x9, x1, x4) + +inst_1466: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x0bf and fs2 == 0 and fe2 == 0x10 and fm2 == 0x236 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x100 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4cbf; op2val:0x4236; +op3val:0x4500; valaddr_reg:x5; val_offset:4326*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 4326*FLEN/8, x9, x1, x4) + +inst_1467: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x0bf and fs2 == 0 and fe2 == 0x10 and fm2 == 0x236 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x100 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4cbf; op2val:0x4236; +op3val:0x4500; valaddr_reg:x5; val_offset:4329*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 4329*FLEN/8, x9, x1, x4) + +inst_1468: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x0bf and fs2 == 0 and fe2 == 0x10 and fm2 == 0x236 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x100 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4cbf; op2val:0x4236; +op3val:0x4500; valaddr_reg:x5; val_offset:4332*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4332*FLEN/8, x9, x1, x4) + +inst_1469: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x0bf and fs2 == 0 and fe2 == 0x10 and fm2 == 0x236 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x100 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4cbf; op2val:0x4236; +op3val:0x4500; valaddr_reg:x5; val_offset:4335*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4335*FLEN/8, x9, x1, x4) + +inst_1470: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x029 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x298 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x35c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3429; op2val:0xbe98; +op3val:0x375c; valaddr_reg:x5; val_offset:4338*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 4338*FLEN/8, x9, x1, x4) + +inst_1471: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x029 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x298 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x35c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3429; op2val:0xbe98; +op3val:0x375c; valaddr_reg:x5; val_offset:4341*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 4341*FLEN/8, x9, x1, x4) + +inst_1472: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x029 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x298 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x35c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3429; op2val:0xbe98; +op3val:0x375c; valaddr_reg:x5; val_offset:4344*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 4344*FLEN/8, x9, x1, x4) + +inst_1473: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x029 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x298 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x35c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3429; op2val:0xbe98; +op3val:0x375c; valaddr_reg:x5; val_offset:4347*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4347*FLEN/8, x9, x1, x4) + +inst_1474: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x029 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x298 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x35c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3429; op2val:0xbe98; +op3val:0x375c; valaddr_reg:x5; val_offset:4350*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4350*FLEN/8, x9, x1, x4) + +inst_1475: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c9 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x38f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x39b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bc9; op2val:0xbb8f; +op3val:0x3b9b; valaddr_reg:x5; val_offset:4353*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 4353*FLEN/8, x9, x1, x4) + +inst_1476: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c9 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x38f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x39b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bc9; op2val:0xbb8f; +op3val:0x3b9b; valaddr_reg:x5; val_offset:4356*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 4356*FLEN/8, x9, x1, x4) + +inst_1477: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c9 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x38f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x39b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bc9; op2val:0xbb8f; +op3val:0x3b9b; valaddr_reg:x5; val_offset:4359*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 4359*FLEN/8, x9, x1, x4) + +inst_1478: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c9 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x38f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x39b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bc9; op2val:0xbb8f; +op3val:0x3b9b; valaddr_reg:x5; val_offset:4362*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4362*FLEN/8, x9, x1, x4) + +inst_1479: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c9 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x38f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x39b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bc9; op2val:0xbb8f; +op3val:0x3b9b; valaddr_reg:x5; val_offset:4365*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4365*FLEN/8, x9, x1, x4) + +inst_1480: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1b3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x13b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3afd; op2val:0xb9b3; +op3val:0x393b; valaddr_reg:x5; val_offset:4368*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 4368*FLEN/8, x9, x1, x4) + +inst_1481: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1b3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x13b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3afd; op2val:0xb9b3; +op3val:0x393b; valaddr_reg:x5; val_offset:4371*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 4371*FLEN/8, x9, x1, x4) + +inst_1482: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1b3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x13b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3afd; op2val:0xb9b3; +op3val:0x393b; valaddr_reg:x5; val_offset:4374*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 4374*FLEN/8, x9, x1, x4) + +inst_1483: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1b3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x13b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3afd; op2val:0xb9b3; +op3val:0x393b; valaddr_reg:x5; val_offset:4377*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4377*FLEN/8, x9, x1, x4) + +inst_1484: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1b3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x13b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3afd; op2val:0xb9b3; +op3val:0x393b; valaddr_reg:x5; val_offset:4380*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4380*FLEN/8, x9, x1, x4) + +inst_1485: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x158 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0b6 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x126 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3158; op2val:0xb4b6; +op3val:0x2d26; valaddr_reg:x5; val_offset:4383*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 4383*FLEN/8, x9, x1, x4) + +inst_1486: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x158 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0b6 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x126 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3158; op2val:0xb4b6; +op3val:0x2d26; valaddr_reg:x5; val_offset:4386*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 4386*FLEN/8, x9, x1, x4) + +inst_1487: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x158 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0b6 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x126 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3158; op2val:0xb4b6; +op3val:0x2d26; valaddr_reg:x5; val_offset:4389*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 4389*FLEN/8, x9, x1, x4) + +inst_1488: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x158 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0b6 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x126 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3158; op2val:0xb4b6; +op3val:0x2d26; valaddr_reg:x5; val_offset:4392*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4392*FLEN/8, x9, x1, x4) + +inst_1489: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x158 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0b6 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x126 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3158; op2val:0xb4b6; +op3val:0x2d26; valaddr_reg:x5; val_offset:4395*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4395*FLEN/8, x9, x1, x4) + +inst_1490: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x283 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x351 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x235 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3683; op2val:0xbf51; +op3val:0x3a35; valaddr_reg:x5; val_offset:4398*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 4398*FLEN/8, x9, x1, x4) + +inst_1491: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x283 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x351 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x235 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3683; op2val:0xbf51; +op3val:0x3a35; valaddr_reg:x5; val_offset:4401*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 4401*FLEN/8, x9, x1, x4) + +inst_1492: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x283 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x351 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x235 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3683; op2val:0xbf51; +op3val:0x3a35; valaddr_reg:x5; val_offset:4404*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 4404*FLEN/8, x9, x1, x4) + +inst_1493: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x283 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x351 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x235 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3683; op2val:0xbf51; +op3val:0x3a35; valaddr_reg:x5; val_offset:4407*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4407*FLEN/8, x9, x1, x4) + +inst_1494: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x283 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x351 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x235 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3683; op2val:0xbf51; +op3val:0x3a35; valaddr_reg:x5; val_offset:4410*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4410*FLEN/8, x9, x1, x4) + +inst_1495: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ad and fs2 == 1 and fe2 == 0x0f and fm2 == 0x03a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x130 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ad; op2val:0xbc3a; +op3val:0x3930; valaddr_reg:x5; val_offset:4413*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 4413*FLEN/8, x9, x1, x4) + +inst_1496: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ad and fs2 == 1 and fe2 == 0x0f and fm2 == 0x03a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x130 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ad; op2val:0xbc3a; +op3val:0x3930; valaddr_reg:x5; val_offset:4416*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 4416*FLEN/8, x9, x1, x4) + +inst_1497: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ad and fs2 == 1 and fe2 == 0x0f and fm2 == 0x03a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x130 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ad; op2val:0xbc3a; +op3val:0x3930; valaddr_reg:x5; val_offset:4419*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 4419*FLEN/8, x9, x1, x4) + +inst_1498: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ad and fs2 == 1 and fe2 == 0x0f and fm2 == 0x03a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x130 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ad; op2val:0xbc3a; +op3val:0x3930; valaddr_reg:x5; val_offset:4422*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4422*FLEN/8, x9, x1, x4) + +inst_1499: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ad and fs2 == 1 and fe2 == 0x0f and fm2 == 0x03a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x130 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ad; op2val:0xbc3a; +op3val:0x3930; valaddr_reg:x5; val_offset:4425*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4425*FLEN/8, x9, x1, x4) + +inst_1500: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x170 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1a0 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3e7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3970; op2val:0xbda0; +op3val:0x3be7; valaddr_reg:x5; val_offset:4428*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 4428*FLEN/8, x9, x1, x4) + +inst_1501: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x170 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1a0 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3e7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3970; op2val:0xbda0; +op3val:0x3be7; valaddr_reg:x5; val_offset:4431*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 4431*FLEN/8, x9, x1, x4) + +inst_1502: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x170 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1a0 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3e7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3970; op2val:0xbda0; +op3val:0x3be7; valaddr_reg:x5; val_offset:4434*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 4434*FLEN/8, x9, x1, x4) + +inst_1503: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x170 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1a0 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3e7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3970; op2val:0xbda0; +op3val:0x3be7; valaddr_reg:x5; val_offset:4437*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4437*FLEN/8, x9, x1, x4) + +inst_1504: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x170 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1a0 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3e7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3970; op2val:0xbda0; +op3val:0x3be7; valaddr_reg:x5; val_offset:4440*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4440*FLEN/8, x9, x1, x4) + +inst_1505: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2f1 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x22e and fs3 == 0 and fe3 == 0x0c and fm3 == 0x25d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36f1; op2val:0xb62e; +op3val:0x325d; valaddr_reg:x5; val_offset:4443*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 4443*FLEN/8, x9, x1, x4) + +inst_1506: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2f1 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x22e and fs3 == 0 and fe3 == 0x0c and fm3 == 0x25d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36f1; op2val:0xb62e; +op3val:0x325d; valaddr_reg:x5; val_offset:4446*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 4446*FLEN/8, x9, x1, x4) + +inst_1507: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2f1 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x22e and fs3 == 0 and fe3 == 0x0c and fm3 == 0x25d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36f1; op2val:0xb62e; +op3val:0x325d; valaddr_reg:x5; val_offset:4449*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 4449*FLEN/8, x9, x1, x4) + +inst_1508: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2f1 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x22e and fs3 == 0 and fe3 == 0x0c and fm3 == 0x25d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36f1; op2val:0xb62e; +op3val:0x325d; valaddr_reg:x5; val_offset:4452*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4452*FLEN/8, x9, x1, x4) + +inst_1509: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2f1 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x22e and fs3 == 0 and fe3 == 0x0c and fm3 == 0x25d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36f1; op2val:0xb62e; +op3val:0x325d; valaddr_reg:x5; val_offset:4455*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4455*FLEN/8, x9, x1, x4) + +inst_1510: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0bb and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1ec and fs3 == 0 and fe3 == 0x0e and fm3 == 0x342 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34bb; op2val:0xc1ec; +op3val:0x3b42; valaddr_reg:x5; val_offset:4458*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 4458*FLEN/8, x9, x1, x4) + +inst_1511: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0bb and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1ec and fs3 == 0 and fe3 == 0x0e and fm3 == 0x342 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34bb; op2val:0xc1ec; +op3val:0x3b42; valaddr_reg:x5; val_offset:4461*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 4461*FLEN/8, x9, x1, x4) + +inst_1512: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0bb and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1ec and fs3 == 0 and fe3 == 0x0e and fm3 == 0x342 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34bb; op2val:0xc1ec; +op3val:0x3b42; valaddr_reg:x5; val_offset:4464*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 4464*FLEN/8, x9, x1, x4) + +inst_1513: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0bb and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1ec and fs3 == 0 and fe3 == 0x0e and fm3 == 0x342 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34bb; op2val:0xc1ec; +op3val:0x3b42; valaddr_reg:x5; val_offset:4467*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4467*FLEN/8, x9, x1, x4) + +inst_1514: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0bb and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1ec and fs3 == 0 and fe3 == 0x0e and fm3 == 0x342 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34bb; op2val:0xc1ec; +op3val:0x3b42; valaddr_reg:x5; val_offset:4470*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4470*FLEN/8, x9, x1, x4) + +inst_1515: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3c7 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x29a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ac and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37c7; op2val:0xbe9a; +op3val:0x3aac; valaddr_reg:x5; val_offset:4473*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 4473*FLEN/8, x9, x1, x4) + +inst_1516: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3c7 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x29a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ac and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37c7; op2val:0xbe9a; +op3val:0x3aac; valaddr_reg:x5; val_offset:4476*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 4476*FLEN/8, x9, x1, x4) + +inst_1517: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3c7 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x29a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ac and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37c7; op2val:0xbe9a; +op3val:0x3aac; valaddr_reg:x5; val_offset:4479*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 4479*FLEN/8, x9, x1, x4) + +inst_1518: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3c7 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x29a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ac and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37c7; op2val:0xbe9a; +op3val:0x3aac; valaddr_reg:x5; val_offset:4482*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4482*FLEN/8, x9, x1, x4) + +inst_1519: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3c7 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x29a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ac and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37c7; op2val:0xbe9a; +op3val:0x3aac; valaddr_reg:x5; val_offset:4485*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4485*FLEN/8, x9, x1, x4) + +inst_1520: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x100 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2dc and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3500; op2val:0xbedc; +op3val:0x388a; valaddr_reg:x5; val_offset:4488*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 4488*FLEN/8, x9, x1, x4) + +inst_1521: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x100 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2dc and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3500; op2val:0xbedc; +op3val:0x388a; valaddr_reg:x5; val_offset:4491*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 4491*FLEN/8, x9, x1, x4) + +inst_1522: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x100 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2dc and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3500; op2val:0xbedc; +op3val:0x388a; valaddr_reg:x5; val_offset:4494*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 4494*FLEN/8, x9, x1, x4) + +inst_1523: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x100 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2dc and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3500; op2val:0xbedc; +op3val:0x388a; valaddr_reg:x5; val_offset:4497*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4497*FLEN/8, x9, x1, x4) + +inst_1524: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x100 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2dc and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3500; op2val:0xbedc; +op3val:0x388a; valaddr_reg:x5; val_offset:4500*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4500*FLEN/8, x9, x1, x4) + +inst_1525: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1cf and fs2 == 1 and fe2 == 0x10 and fm2 == 0x061 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x35c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2dcf; op2val:0xc061; +op3val:0x335c; valaddr_reg:x5; val_offset:4503*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 4503*FLEN/8, x9, x1, x4) + +inst_1526: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1cf and fs2 == 1 and fe2 == 0x10 and fm2 == 0x061 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x35c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2dcf; op2val:0xc061; +op3val:0x335c; valaddr_reg:x5; val_offset:4506*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 4506*FLEN/8, x9, x1, x4) + +inst_1527: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1cf and fs2 == 1 and fe2 == 0x10 and fm2 == 0x061 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x35c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2dcf; op2val:0xc061; +op3val:0x335c; valaddr_reg:x5; val_offset:4509*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 4509*FLEN/8, x9, x1, x4) + +inst_1528: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1cf and fs2 == 1 and fe2 == 0x10 and fm2 == 0x061 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x35c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2dcf; op2val:0xc061; +op3val:0x335c; valaddr_reg:x5; val_offset:4512*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4512*FLEN/8, x9, x1, x4) + +inst_1529: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1cf and fs2 == 1 and fe2 == 0x10 and fm2 == 0x061 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x35c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2dcf; op2val:0xc061; +op3val:0x335c; valaddr_reg:x5; val_offset:4515*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4515*FLEN/8, x9, x1, x4) + +inst_1530: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x315 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1fa and fs3 == 0 and fe3 == 0x0e and fm3 == 0x18a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b15; op2val:0xb9fa; +op3val:0x398a; valaddr_reg:x5; val_offset:4518*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 4518*FLEN/8, x9, x1, x4) + +inst_1531: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x315 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1fa and fs3 == 0 and fe3 == 0x0e and fm3 == 0x18a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b15; op2val:0xb9fa; +op3val:0x398a; valaddr_reg:x5; val_offset:4521*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 4521*FLEN/8, x9, x1, x4) + +inst_1532: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x315 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1fa and fs3 == 0 and fe3 == 0x0e and fm3 == 0x18a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b15; op2val:0xb9fa; +op3val:0x398a; valaddr_reg:x5; val_offset:4524*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 4524*FLEN/8, x9, x1, x4) + +inst_1533: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x315 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1fa and fs3 == 0 and fe3 == 0x0e and fm3 == 0x18a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b15; op2val:0xb9fa; +op3val:0x398a; valaddr_reg:x5; val_offset:4527*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4527*FLEN/8, x9, x1, x4) + +inst_1534: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x315 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1fa and fs3 == 0 and fe3 == 0x0e and fm3 == 0x18a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b15; op2val:0xb9fa; +op3val:0x398a; valaddr_reg:x5; val_offset:4530*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4530*FLEN/8, x9, x1, x4) + +inst_1535: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x345 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x098 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x06d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f45; op2val:0xc498; +op3val:0x386d; valaddr_reg:x5; val_offset:4533*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 4533*FLEN/8, x9, x1, x4) + +inst_1536: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x345 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x098 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x06d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f45; op2val:0xc498; +op3val:0x386d; valaddr_reg:x5; val_offset:4536*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 4536*FLEN/8, x9, x1, x4) + +inst_1537: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x345 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x098 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x06d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f45; op2val:0xc498; +op3val:0x386d; valaddr_reg:x5; val_offset:4539*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 4539*FLEN/8, x9, x1, x4) + +inst_1538: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x345 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x098 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x06d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f45; op2val:0xc498; +op3val:0x386d; valaddr_reg:x5; val_offset:4542*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4542*FLEN/8, x9, x1, x4) + +inst_1539: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x345 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x098 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x06d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f45; op2val:0xc498; +op3val:0x386d; valaddr_reg:x5; val_offset:4545*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4545*FLEN/8, x9, x1, x4) + +inst_1540: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0a2 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x378 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x094 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38a2; op2val:0xbb78; +op3val:0x3894; valaddr_reg:x5; val_offset:4548*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 4548*FLEN/8, x9, x1, x4) + +inst_1541: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0a2 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x378 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x094 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38a2; op2val:0xbb78; +op3val:0x3894; valaddr_reg:x5; val_offset:4551*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 4551*FLEN/8, x9, x1, x4) + +inst_1542: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0a2 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x378 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x094 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38a2; op2val:0xbb78; +op3val:0x3894; valaddr_reg:x5; val_offset:4554*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 4554*FLEN/8, x9, x1, x4) + +inst_1543: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0a2 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x378 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x094 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38a2; op2val:0xbb78; +op3val:0x3894; valaddr_reg:x5; val_offset:4557*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4557*FLEN/8, x9, x1, x4) + +inst_1544: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0a2 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x378 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x094 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38a2; op2val:0xbb78; +op3val:0x3894; valaddr_reg:x5; val_offset:4560*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4560*FLEN/8, x9, x1, x4) + +inst_1545: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x01a and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3b3 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1f3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x341a; op2val:0xb3b3; +op3val:0x2df3; valaddr_reg:x5; val_offset:4563*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 4563*FLEN/8, x9, x1, x4) + +inst_1546: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x01a and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3b3 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1f3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x341a; op2val:0xb3b3; +op3val:0x2df3; valaddr_reg:x5; val_offset:4566*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 4566*FLEN/8, x9, x1, x4) + +inst_1547: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x01a and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3b3 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1f3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x341a; op2val:0xb3b3; +op3val:0x2df3; valaddr_reg:x5; val_offset:4569*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 4569*FLEN/8, x9, x1, x4) + +inst_1548: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x01a and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3b3 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1f3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x341a; op2val:0xb3b3; +op3val:0x2df3; valaddr_reg:x5; val_offset:4572*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4572*FLEN/8, x9, x1, x4) + +inst_1549: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x01a and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3b3 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1f3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x341a; op2val:0xb3b3; +op3val:0x2df3; valaddr_reg:x5; val_offset:4575*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4575*FLEN/8, x9, x1, x4) + +inst_1550: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3be and fs2 == 1 and fe2 == 0x0a and fm2 == 0x3c5 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x3c3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37be; op2val:0xabc5; +op3val:0x2bc3; valaddr_reg:x5; val_offset:4578*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 4578*FLEN/8, x9, x1, x4) + +inst_1551: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3be and fs2 == 1 and fe2 == 0x0a and fm2 == 0x3c5 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x3c3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37be; op2val:0xabc5; +op3val:0x2bc3; valaddr_reg:x5; val_offset:4581*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 4581*FLEN/8, x9, x1, x4) + +inst_1552: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3be and fs2 == 1 and fe2 == 0x0a and fm2 == 0x3c5 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x3c3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37be; op2val:0xabc5; +op3val:0x2bc3; valaddr_reg:x5; val_offset:4584*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 4584*FLEN/8, x9, x1, x4) + +inst_1553: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3be and fs2 == 1 and fe2 == 0x0a and fm2 == 0x3c5 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x3c3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37be; op2val:0xabc5; +op3val:0x2bc3; valaddr_reg:x5; val_offset:4587*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4587*FLEN/8, x9, x1, x4) + +inst_1554: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3be and fs2 == 1 and fe2 == 0x0a and fm2 == 0x3c5 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x3c3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37be; op2val:0xabc5; +op3val:0x2bc3; valaddr_reg:x5; val_offset:4590*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4590*FLEN/8, x9, x1, x4) + +inst_1555: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2c3 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x01c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x332 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36c3; op2val:0xc01c; +op3val:0x3b32; valaddr_reg:x5; val_offset:4593*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 4593*FLEN/8, x9, x1, x4) + +inst_1556: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2c3 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x01c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x332 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36c3; op2val:0xc01c; +op3val:0x3b32; valaddr_reg:x5; val_offset:4596*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 4596*FLEN/8, x9, x1, x4) + +inst_1557: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2c3 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x01c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x332 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36c3; op2val:0xc01c; +op3val:0x3b32; valaddr_reg:x5; val_offset:4599*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 4599*FLEN/8, x9, x1, x4) + +inst_1558: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2c3 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x01c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x332 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36c3; op2val:0xc01c; +op3val:0x3b32; valaddr_reg:x5; val_offset:4602*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4602*FLEN/8, x9, x1, x4) + +inst_1559: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2c3 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x01c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x332 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36c3; op2val:0xc01c; +op3val:0x3b32; valaddr_reg:x5; val_offset:4605*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4605*FLEN/8, x9, x1, x4) + +inst_1560: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2c2 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x153 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0bf and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32c2; op2val:0xc153; +op3val:0x38bf; valaddr_reg:x5; val_offset:4608*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 4608*FLEN/8, x9, x1, x4) + +inst_1561: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2c2 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x153 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0bf and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32c2; op2val:0xc153; +op3val:0x38bf; valaddr_reg:x5; val_offset:4611*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 4611*FLEN/8, x9, x1, x4) + +inst_1562: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2c2 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x153 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0bf and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32c2; op2val:0xc153; +op3val:0x38bf; valaddr_reg:x5; val_offset:4614*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 4614*FLEN/8, x9, x1, x4) + +inst_1563: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2c2 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x153 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0bf and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32c2; op2val:0xc153; +op3val:0x38bf; valaddr_reg:x5; val_offset:4617*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4617*FLEN/8, x9, x1, x4) + +inst_1564: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2c2 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x153 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0bf and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32c2; op2val:0xc153; +op3val:0x38bf; valaddr_reg:x5; val_offset:4620*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4620*FLEN/8, x9, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_13) + +inst_1565: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x398 and fs2 == 1 and fe2 == 0x09 and fm2 == 0x1be and fs3 == 0 and fe3 == 0x0a and fm3 == 0x2ba and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b98; op2val:0xa5be; +op3val:0x2aba; valaddr_reg:x5; val_offset:4623*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 4623*FLEN/8, x9, x1, x4) + +inst_1566: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x398 and fs2 == 1 and fe2 == 0x09 and fm2 == 0x1be and fs3 == 0 and fe3 == 0x0a and fm3 == 0x2ba and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b98; op2val:0xa5be; +op3val:0x2aba; valaddr_reg:x5; val_offset:4626*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 4626*FLEN/8, x9, x1, x4) + +inst_1567: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x398 and fs2 == 1 and fe2 == 0x09 and fm2 == 0x1be and fs3 == 0 and fe3 == 0x0a and fm3 == 0x2ba and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b98; op2val:0xa5be; +op3val:0x2aba; valaddr_reg:x5; val_offset:4629*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 4629*FLEN/8, x9, x1, x4) + +inst_1568: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x398 and fs2 == 1 and fe2 == 0x09 and fm2 == 0x1be and fs3 == 0 and fe3 == 0x0a and fm3 == 0x2ba and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b98; op2val:0xa5be; +op3val:0x2aba; valaddr_reg:x5; val_offset:4632*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4632*FLEN/8, x9, x1, x4) + +inst_1569: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x398 and fs2 == 1 and fe2 == 0x09 and fm2 == 0x1be and fs3 == 0 and fe3 == 0x0a and fm3 == 0x2ba and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b98; op2val:0xa5be; +op3val:0x2aba; valaddr_reg:x5; val_offset:4635*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4635*FLEN/8, x9, x1, x4) + +inst_1570: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3be and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2c5 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x30e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bbe; op2val:0xb6c5; +op3val:0x370e; valaddr_reg:x5; val_offset:4638*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 4638*FLEN/8, x9, x1, x4) + +inst_1571: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3be and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2c5 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x30e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bbe; op2val:0xb6c5; +op3val:0x370e; valaddr_reg:x5; val_offset:4641*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 4641*FLEN/8, x9, x1, x4) + +inst_1572: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3be and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2c5 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x30e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bbe; op2val:0xb6c5; +op3val:0x370e; valaddr_reg:x5; val_offset:4644*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 4644*FLEN/8, x9, x1, x4) + +inst_1573: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3be and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2c5 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x30e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bbe; op2val:0xb6c5; +op3val:0x370e; valaddr_reg:x5; val_offset:4647*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4647*FLEN/8, x9, x1, x4) + +inst_1574: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3be and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2c5 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x30e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bbe; op2val:0xb6c5; +op3val:0x370e; valaddr_reg:x5; val_offset:4650*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4650*FLEN/8, x9, x1, x4) + +inst_1575: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x043 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2df and fs3 == 0 and fe3 == 0x0c and fm3 == 0x0aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3843; op2val:0xb2df; +op3val:0x30aa; valaddr_reg:x5; val_offset:4653*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 4653*FLEN/8, x9, x1, x4) + +inst_1576: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x043 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2df and fs3 == 0 and fe3 == 0x0c and fm3 == 0x0aa and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3843; op2val:0xb2df; +op3val:0x30aa; valaddr_reg:x5; val_offset:4656*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 4656*FLEN/8, x9, x1, x4) + +inst_1577: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x043 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2df and fs3 == 0 and fe3 == 0x0c and fm3 == 0x0aa and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3843; op2val:0xb2df; +op3val:0x30aa; valaddr_reg:x5; val_offset:4659*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 4659*FLEN/8, x9, x1, x4) + +inst_1578: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x043 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2df and fs3 == 0 and fe3 == 0x0c and fm3 == 0x0aa and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3843; op2val:0xb2df; +op3val:0x30aa; valaddr_reg:x5; val_offset:4662*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4662*FLEN/8, x9, x1, x4) + +inst_1579: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x043 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2df and fs3 == 0 and fe3 == 0x0c and fm3 == 0x0aa and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3843; op2val:0xb2df; +op3val:0x30aa; valaddr_reg:x5; val_offset:4665*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4665*FLEN/8, x9, x1, x4) + +inst_1580: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0f4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0e7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x254 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38f4; op2val:0xbce7; +op3val:0x3a54; valaddr_reg:x5; val_offset:4668*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 4668*FLEN/8, x9, x1, x4) + +inst_1581: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0f4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0e7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x254 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38f4; op2val:0xbce7; +op3val:0x3a54; valaddr_reg:x5; val_offset:4671*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 4671*FLEN/8, x9, x1, x4) + +inst_1582: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0f4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0e7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x254 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38f4; op2val:0xbce7; +op3val:0x3a54; valaddr_reg:x5; val_offset:4674*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 4674*FLEN/8, x9, x1, x4) + +inst_1583: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0f4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0e7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x254 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38f4; op2val:0xbce7; +op3val:0x3a54; valaddr_reg:x5; val_offset:4677*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4677*FLEN/8, x9, x1, x4) + +inst_1584: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0f4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0e7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x254 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38f4; op2val:0xbce7; +op3val:0x3a54; valaddr_reg:x5; val_offset:4680*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4680*FLEN/8, x9, x1, x4) + +inst_1585: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1da and fs2 == 1 and fe2 == 0x0f and fm2 == 0x03b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x270 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39da; op2val:0xbc3b; +op3val:0x3a70; valaddr_reg:x5; val_offset:4683*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 4683*FLEN/8, x9, x1, x4) + +inst_1586: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1da and fs2 == 1 and fe2 == 0x0f and fm2 == 0x03b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x270 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39da; op2val:0xbc3b; +op3val:0x3a70; valaddr_reg:x5; val_offset:4686*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 4686*FLEN/8, x9, x1, x4) + +inst_1587: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1da and fs2 == 1 and fe2 == 0x0f and fm2 == 0x03b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x270 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39da; op2val:0xbc3b; +op3val:0x3a70; valaddr_reg:x5; val_offset:4689*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 4689*FLEN/8, x9, x1, x4) + +inst_1588: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1da and fs2 == 1 and fe2 == 0x0f and fm2 == 0x03b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x270 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39da; op2val:0xbc3b; +op3val:0x3a70; valaddr_reg:x5; val_offset:4692*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4692*FLEN/8, x9, x1, x4) + +inst_1589: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1da and fs2 == 1 and fe2 == 0x0f and fm2 == 0x03b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x270 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39da; op2val:0xbc3b; +op3val:0x3a70; valaddr_reg:x5; val_offset:4695*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4695*FLEN/8, x9, x1, x4) + +inst_1590: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x348 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x179 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x13b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3748; op2val:0xbd79; +op3val:0x393b; valaddr_reg:x5; val_offset:4698*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 4698*FLEN/8, x9, x1, x4) + +inst_1591: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x348 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x179 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x13b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3748; op2val:0xbd79; +op3val:0x393b; valaddr_reg:x5; val_offset:4701*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 4701*FLEN/8, x9, x1, x4) + +inst_1592: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x348 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x179 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x13b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3748; op2val:0xbd79; +op3val:0x393b; valaddr_reg:x5; val_offset:4704*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 4704*FLEN/8, x9, x1, x4) + +inst_1593: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x348 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x179 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x13b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3748; op2val:0xbd79; +op3val:0x393b; valaddr_reg:x5; val_offset:4707*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4707*FLEN/8, x9, x1, x4) + +inst_1594: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x348 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x179 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x13b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3748; op2val:0xbd79; +op3val:0x393b; valaddr_reg:x5; val_offset:4710*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4710*FLEN/8, x9, x1, x4) + +inst_1595: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x05b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x165 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x220 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x345b; op2val:0xc165; +op3val:0x3a20; valaddr_reg:x5; val_offset:4713*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 4713*FLEN/8, x9, x1, x4) + +inst_1596: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x05b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x165 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x220 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x345b; op2val:0xc165; +op3val:0x3a20; valaddr_reg:x5; val_offset:4716*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 4716*FLEN/8, x9, x1, x4) + +inst_1597: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x05b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x165 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x220 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x345b; op2val:0xc165; +op3val:0x3a20; valaddr_reg:x5; val_offset:4719*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 4719*FLEN/8, x9, x1, x4) + +inst_1598: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x05b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x165 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x220 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x345b; op2val:0xc165; +op3val:0x3a20; valaddr_reg:x5; val_offset:4722*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4722*FLEN/8, x9, x1, x4) + +inst_1599: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x05b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x165 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x220 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x345b; op2val:0xc165; +op3val:0x3a20; valaddr_reg:x5; val_offset:4725*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4725*FLEN/8, x9, x1, x4) + +inst_1600: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x146 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x06b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x213 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3946; op2val:0xbc6b; +op3val:0x3a13; valaddr_reg:x5; val_offset:4728*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 4728*FLEN/8, x9, x1, x4) + +inst_1601: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x146 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x06b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x213 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3946; op2val:0xbc6b; +op3val:0x3a13; valaddr_reg:x5; val_offset:4731*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 4731*FLEN/8, x9, x1, x4) + +inst_1602: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x146 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x06b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x213 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3946; op2val:0xbc6b; +op3val:0x3a13; valaddr_reg:x5; val_offset:4734*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 4734*FLEN/8, x9, x1, x4) + +inst_1603: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x146 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x06b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x213 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3946; op2val:0xbc6b; +op3val:0x3a13; valaddr_reg:x5; val_offset:4737*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4737*FLEN/8, x9, x1, x4) + +inst_1604: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x146 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x06b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x213 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3946; op2val:0xbc6b; +op3val:0x3a13; valaddr_reg:x5; val_offset:4740*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4740*FLEN/8, x9, x1, x4) + +inst_1605: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x22e and fs2 == 1 and fe2 == 0x10 and fm2 == 0x269 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1f4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2a2e; op2val:0xc269; +op3val:0x31f4; valaddr_reg:x5; val_offset:4743*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 4743*FLEN/8, x9, x1, x4) + +inst_1606: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x22e and fs2 == 1 and fe2 == 0x10 and fm2 == 0x269 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1f4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2a2e; op2val:0xc269; +op3val:0x31f4; valaddr_reg:x5; val_offset:4746*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 4746*FLEN/8, x9, x1, x4) + +inst_1607: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x22e and fs2 == 1 and fe2 == 0x10 and fm2 == 0x269 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1f4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2a2e; op2val:0xc269; +op3val:0x31f4; valaddr_reg:x5; val_offset:4749*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 4749*FLEN/8, x9, x1, x4) + +inst_1608: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x22e and fs2 == 1 and fe2 == 0x10 and fm2 == 0x269 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1f4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2a2e; op2val:0xc269; +op3val:0x31f4; valaddr_reg:x5; val_offset:4752*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4752*FLEN/8, x9, x1, x4) + +inst_1609: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x22e and fs2 == 1 and fe2 == 0x10 and fm2 == 0x269 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1f4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2a2e; op2val:0xc269; +op3val:0x31f4; valaddr_reg:x5; val_offset:4755*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4755*FLEN/8, x9, x1, x4) + +inst_1610: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1a7 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x02f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x26b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31a7; op2val:0xc02f; +op3val:0x366b; valaddr_reg:x5; val_offset:4758*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 4758*FLEN/8, x9, x1, x4) + +inst_1611: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1a7 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x02f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x26b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31a7; op2val:0xc02f; +op3val:0x366b; valaddr_reg:x5; val_offset:4761*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 4761*FLEN/8, x9, x1, x4) + +inst_1612: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1a7 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x02f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x26b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31a7; op2val:0xc02f; +op3val:0x366b; valaddr_reg:x5; val_offset:4764*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 4764*FLEN/8, x9, x1, x4) + +inst_1613: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1a7 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x02f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x26b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31a7; op2val:0xc02f; +op3val:0x366b; valaddr_reg:x5; val_offset:4767*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4767*FLEN/8, x9, x1, x4) + +inst_1614: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1a7 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x02f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x26b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31a7; op2val:0xc02f; +op3val:0x366b; valaddr_reg:x5; val_offset:4770*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4770*FLEN/8, x9, x1, x4) + +inst_1615: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x16d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2e4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38e4; op2val:0xbd6d; +op3val:0x3ae4; valaddr_reg:x5; val_offset:4773*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 4773*FLEN/8, x9, x1, x4) + +inst_1616: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x16d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2e4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38e4; op2val:0xbd6d; +op3val:0x3ae4; valaddr_reg:x5; val_offset:4776*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 4776*FLEN/8, x9, x1, x4) + +inst_1617: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x16d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2e4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38e4; op2val:0xbd6d; +op3val:0x3ae4; valaddr_reg:x5; val_offset:4779*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 4779*FLEN/8, x9, x1, x4) + +inst_1618: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x16d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2e4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38e4; op2val:0xbd6d; +op3val:0x3ae4; valaddr_reg:x5; val_offset:4782*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4782*FLEN/8, x9, x1, x4) + +inst_1619: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x16d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2e4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38e4; op2val:0xbd6d; +op3val:0x3ae4; valaddr_reg:x5; val_offset:4785*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4785*FLEN/8, x9, x1, x4) + +inst_1620: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x237 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x115 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x033 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3237; op2val:0xc115; +op3val:0x3833; valaddr_reg:x5; val_offset:4788*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 4788*FLEN/8, x9, x1, x4) + +inst_1621: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x237 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x115 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x033 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3237; op2val:0xc115; +op3val:0x3833; valaddr_reg:x5; val_offset:4791*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 4791*FLEN/8, x9, x1, x4) + +inst_1622: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x237 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x115 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x033 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3237; op2val:0xc115; +op3val:0x3833; valaddr_reg:x5; val_offset:4794*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 4794*FLEN/8, x9, x1, x4) + +inst_1623: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x237 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x115 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x033 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3237; op2val:0xc115; +op3val:0x3833; valaddr_reg:x5; val_offset:4797*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4797*FLEN/8, x9, x1, x4) + +inst_1624: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x237 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x115 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x033 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3237; op2val:0xc115; +op3val:0x3833; valaddr_reg:x5; val_offset:4800*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4800*FLEN/8, x9, x1, x4) + +inst_1625: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2ae and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2af and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bb5; op2val:0xbaae; +op3val:0x3aaf; valaddr_reg:x5; val_offset:4803*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 4803*FLEN/8, x9, x1, x4) + +inst_1626: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2ae and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2af and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bb5; op2val:0xbaae; +op3val:0x3aaf; valaddr_reg:x5; val_offset:4806*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 4806*FLEN/8, x9, x1, x4) + +inst_1627: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2ae and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2af and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bb5; op2val:0xbaae; +op3val:0x3aaf; valaddr_reg:x5; val_offset:4809*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 4809*FLEN/8, x9, x1, x4) + +inst_1628: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2ae and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2af and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bb5; op2val:0xbaae; +op3val:0x3aaf; valaddr_reg:x5; val_offset:4812*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4812*FLEN/8, x9, x1, x4) + +inst_1629: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2ae and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2af and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bb5; op2val:0xbaae; +op3val:0x3aaf; valaddr_reg:x5; val_offset:4815*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4815*FLEN/8, x9, x1, x4) + +inst_1630: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x33c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0d6 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b3c; op2val:0xb4d6; +op3val:0x34e0; valaddr_reg:x5; val_offset:4818*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 4818*FLEN/8, x9, x1, x4) + +inst_1631: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x33c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0d6 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0e0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b3c; op2val:0xb4d6; +op3val:0x34e0; valaddr_reg:x5; val_offset:4821*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 4821*FLEN/8, x9, x1, x4) + +inst_1632: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x33c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0d6 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0e0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b3c; op2val:0xb4d6; +op3val:0x34e0; valaddr_reg:x5; val_offset:4824*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 4824*FLEN/8, x9, x1, x4) + +inst_1633: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x33c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0d6 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0e0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b3c; op2val:0xb4d6; +op3val:0x34e0; valaddr_reg:x5; val_offset:4827*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4827*FLEN/8, x9, x1, x4) + +inst_1634: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x33c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0d6 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0e0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b3c; op2val:0xb4d6; +op3val:0x34e0; valaddr_reg:x5; val_offset:4830*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4830*FLEN/8, x9, x1, x4) + +inst_1635: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x018 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x20f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x274 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3018; op2val:0xc60f; +op3val:0x3a74; valaddr_reg:x5; val_offset:4833*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 4833*FLEN/8, x9, x1, x4) + +inst_1636: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x018 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x20f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x274 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3018; op2val:0xc60f; +op3val:0x3a74; valaddr_reg:x5; val_offset:4836*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 4836*FLEN/8, x9, x1, x4) + +inst_1637: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x018 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x20f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x274 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3018; op2val:0xc60f; +op3val:0x3a74; valaddr_reg:x5; val_offset:4839*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 4839*FLEN/8, x9, x1, x4) + +inst_1638: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x018 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x20f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x274 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3018; op2val:0xc60f; +op3val:0x3a74; valaddr_reg:x5; val_offset:4842*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4842*FLEN/8, x9, x1, x4) + +inst_1639: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x018 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x20f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x274 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3018; op2val:0xc60f; +op3val:0x3a74; valaddr_reg:x5; val_offset:4845*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4845*FLEN/8, x9, x1, x4) + +inst_1640: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x34a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1bf and fs3 == 0 and fe3 == 0x0e and fm3 == 0x17d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x334a; op2val:0xc1bf; +op3val:0x397d; valaddr_reg:x5; val_offset:4848*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 4848*FLEN/8, x9, x1, x4) + +inst_1641: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x34a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1bf and fs3 == 0 and fe3 == 0x0e and fm3 == 0x17d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x334a; op2val:0xc1bf; +op3val:0x397d; valaddr_reg:x5; val_offset:4851*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 4851*FLEN/8, x9, x1, x4) + +inst_1642: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x34a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1bf and fs3 == 0 and fe3 == 0x0e and fm3 == 0x17d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x334a; op2val:0xc1bf; +op3val:0x397d; valaddr_reg:x5; val_offset:4854*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 4854*FLEN/8, x9, x1, x4) + +inst_1643: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x34a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1bf and fs3 == 0 and fe3 == 0x0e and fm3 == 0x17d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x334a; op2val:0xc1bf; +op3val:0x397d; valaddr_reg:x5; val_offset:4857*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4857*FLEN/8, x9, x1, x4) + +inst_1644: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x34a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1bf and fs3 == 0 and fe3 == 0x0e and fm3 == 0x17d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x334a; op2val:0xc1bf; +op3val:0x397d; valaddr_reg:x5; val_offset:4860*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4860*FLEN/8, x9, x1, x4) + +inst_1645: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x16a and fs2 == 1 and fe2 == 0x0d and fm2 == 0x244 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x13e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x356a; op2val:0xb644; +op3val:0x313e; valaddr_reg:x5; val_offset:4863*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 4863*FLEN/8, x9, x1, x4) + +inst_1646: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x16a and fs2 == 1 and fe2 == 0x0d and fm2 == 0x244 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x13e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x356a; op2val:0xb644; +op3val:0x313e; valaddr_reg:x5; val_offset:4866*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 4866*FLEN/8, x9, x1, x4) + +inst_1647: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x16a and fs2 == 1 and fe2 == 0x0d and fm2 == 0x244 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x13e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x356a; op2val:0xb644; +op3val:0x313e; valaddr_reg:x5; val_offset:4869*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 4869*FLEN/8, x9, x1, x4) + +inst_1648: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x16a and fs2 == 1 and fe2 == 0x0d and fm2 == 0x244 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x13e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x356a; op2val:0xb644; +op3val:0x313e; valaddr_reg:x5; val_offset:4872*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4872*FLEN/8, x9, x1, x4) + +inst_1649: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x16a and fs2 == 1 and fe2 == 0x0d and fm2 == 0x244 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x13e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x356a; op2val:0xb644; +op3val:0x313e; valaddr_reg:x5; val_offset:4875*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4875*FLEN/8, x9, x1, x4) + +inst_1650: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x257 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3ce and fs3 == 0 and fe3 == 0x0c and fm3 == 0x330 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3657; op2val:0xb7ce; +op3val:0x3330; valaddr_reg:x5; val_offset:4878*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 4878*FLEN/8, x9, x1, x4) + +inst_1651: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x257 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3ce and fs3 == 0 and fe3 == 0x0c and fm3 == 0x330 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3657; op2val:0xb7ce; +op3val:0x3330; valaddr_reg:x5; val_offset:4881*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 4881*FLEN/8, x9, x1, x4) + +inst_1652: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x257 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3ce and fs3 == 0 and fe3 == 0x0c and fm3 == 0x330 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3657; op2val:0xb7ce; +op3val:0x3330; valaddr_reg:x5; val_offset:4884*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 4884*FLEN/8, x9, x1, x4) + +inst_1653: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x257 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3ce and fs3 == 0 and fe3 == 0x0c and fm3 == 0x330 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3657; op2val:0xb7ce; +op3val:0x3330; valaddr_reg:x5; val_offset:4887*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4887*FLEN/8, x9, x1, x4) + +inst_1654: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x257 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3ce and fs3 == 0 and fe3 == 0x0c and fm3 == 0x330 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3657; op2val:0xb7ce; +op3val:0x3330; valaddr_reg:x5; val_offset:4890*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4890*FLEN/8, x9, x1, x4) + +inst_1655: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x115 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x209 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3eb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3915; op2val:0xbe09; +op3val:0x3beb; valaddr_reg:x5; val_offset:4893*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 4893*FLEN/8, x9, x1, x4) + +inst_1656: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x115 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x209 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3eb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3915; op2val:0xbe09; +op3val:0x3beb; valaddr_reg:x5; val_offset:4896*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 4896*FLEN/8, x9, x1, x4) + +inst_1657: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x115 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x209 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3eb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3915; op2val:0xbe09; +op3val:0x3beb; valaddr_reg:x5; val_offset:4899*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 4899*FLEN/8, x9, x1, x4) + +inst_1658: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x115 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x209 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3eb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3915; op2val:0xbe09; +op3val:0x3beb; valaddr_reg:x5; val_offset:4902*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4902*FLEN/8, x9, x1, x4) + +inst_1659: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x115 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x209 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3eb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3915; op2val:0xbe09; +op3val:0x3beb; valaddr_reg:x5; val_offset:4905*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4905*FLEN/8, x9, x1, x4) + +inst_1660: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x008 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x25a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2e8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3808; op2val:0xba5a; +op3val:0x36e8; valaddr_reg:x5; val_offset:4908*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 4908*FLEN/8, x9, x1, x4) + +inst_1661: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x008 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x25a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2e8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3808; op2val:0xba5a; +op3val:0x36e8; valaddr_reg:x5; val_offset:4911*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 4911*FLEN/8, x9, x1, x4) + +inst_1662: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x008 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x25a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2e8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3808; op2val:0xba5a; +op3val:0x36e8; valaddr_reg:x5; val_offset:4914*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 4914*FLEN/8, x9, x1, x4) + +inst_1663: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x008 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x25a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2e8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3808; op2val:0xba5a; +op3val:0x36e8; valaddr_reg:x5; val_offset:4917*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4917*FLEN/8, x9, x1, x4) + +inst_1664: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x008 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x25a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2e8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3808; op2val:0xba5a; +op3val:0x36e8; valaddr_reg:x5; val_offset:4920*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4920*FLEN/8, x9, x1, x4) + +inst_1665: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x291 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1c4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a91; op2val:0xb9c4; +op3val:0x38fc; valaddr_reg:x5; val_offset:4923*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 4923*FLEN/8, x9, x1, x4) + +inst_1666: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x291 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1c4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0fc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a91; op2val:0xb9c4; +op3val:0x38fc; valaddr_reg:x5; val_offset:4926*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 4926*FLEN/8, x9, x1, x4) + +inst_1667: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x291 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1c4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0fc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a91; op2val:0xb9c4; +op3val:0x38fc; valaddr_reg:x5; val_offset:4929*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 4929*FLEN/8, x9, x1, x4) + +inst_1668: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x291 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1c4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0fc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a91; op2val:0xb9c4; +op3val:0x38fc; valaddr_reg:x5; val_offset:4932*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4932*FLEN/8, x9, x1, x4) + +inst_1669: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x291 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1c4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0fc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a91; op2val:0xb9c4; +op3val:0x38fc; valaddr_reg:x5; val_offset:4935*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4935*FLEN/8, x9, x1, x4) + +inst_1670: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x18a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x171 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3ca and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x398a; op2val:0xbd71; +op3val:0x3bca; valaddr_reg:x5; val_offset:4938*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 4938*FLEN/8, x9, x1, x4) + +inst_1671: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x18a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x171 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3ca and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x398a; op2val:0xbd71; +op3val:0x3bca; valaddr_reg:x5; val_offset:4941*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 4941*FLEN/8, x9, x1, x4) + +inst_1672: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x18a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x171 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3ca and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x398a; op2val:0xbd71; +op3val:0x3bca; valaddr_reg:x5; val_offset:4944*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 4944*FLEN/8, x9, x1, x4) + +inst_1673: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x18a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x171 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3ca and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x398a; op2val:0xbd71; +op3val:0x3bca; valaddr_reg:x5; val_offset:4947*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4947*FLEN/8, x9, x1, x4) + +inst_1674: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x18a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x171 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3ca and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x398a; op2val:0xbd71; +op3val:0x3bca; valaddr_reg:x5; val_offset:4950*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4950*FLEN/8, x9, x1, x4) + +inst_1675: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x194 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2db and fs3 == 0 and fe3 == 0x0e and fm3 == 0x108 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3994; op2val:0xbadb; +op3val:0x3908; valaddr_reg:x5; val_offset:4953*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 4953*FLEN/8, x9, x1, x4) + +inst_1676: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x194 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2db and fs3 == 0 and fe3 == 0x0e and fm3 == 0x108 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3994; op2val:0xbadb; +op3val:0x3908; valaddr_reg:x5; val_offset:4956*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 4956*FLEN/8, x9, x1, x4) + +inst_1677: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x194 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2db and fs3 == 0 and fe3 == 0x0e and fm3 == 0x108 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3994; op2val:0xbadb; +op3val:0x3908; valaddr_reg:x5; val_offset:4959*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 4959*FLEN/8, x9, x1, x4) + +inst_1678: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x194 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2db and fs3 == 0 and fe3 == 0x0e and fm3 == 0x108 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3994; op2val:0xbadb; +op3val:0x3908; valaddr_reg:x5; val_offset:4962*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4962*FLEN/8, x9, x1, x4) + +inst_1679: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x194 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2db and fs3 == 0 and fe3 == 0x0e and fm3 == 0x108 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3994; op2val:0xbadb; +op3val:0x3908; valaddr_reg:x5; val_offset:4965*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4965*FLEN/8, x9, x1, x4) + +inst_1680: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x208 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x17a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x021 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3608; op2val:0xb97a; +op3val:0x3421; valaddr_reg:x5; val_offset:4968*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 4968*FLEN/8, x9, x1, x4) + +inst_1681: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x208 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x17a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x021 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3608; op2val:0xb97a; +op3val:0x3421; valaddr_reg:x5; val_offset:4971*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 4971*FLEN/8, x9, x1, x4) + +inst_1682: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x208 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x17a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x021 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3608; op2val:0xb97a; +op3val:0x3421; valaddr_reg:x5; val_offset:4974*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4974*FLEN/8, x9, x1, x4) + +inst_1683: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x28d and fs2 == 1 and fe2 == 0x0d and fm2 == 0x07e and fs3 == 0 and fe3 == 0x0a and fm3 == 0x35d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x328d; op2val:0xb47e; +op3val:0x2b5d; valaddr_reg:x5; val_offset:4977*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 4977*FLEN/8, x9, x1, x4) + +inst_1684: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x28d and fs2 == 1 and fe2 == 0x0d and fm2 == 0x07e and fs3 == 0 and fe3 == 0x0a and fm3 == 0x35d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x328d; op2val:0xb47e; +op3val:0x2b5d; valaddr_reg:x5; val_offset:4980*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4980*FLEN/8, x9, x1, x4) + +inst_1685: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x28d and fs2 == 1 and fe2 == 0x0d and fm2 == 0x07e and fs3 == 0 and fe3 == 0x0a and fm3 == 0x35d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x328d; op2val:0xb47e; +op3val:0x2b5d; valaddr_reg:x5; val_offset:4983*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4983*FLEN/8, x9, x1, x4) + +inst_1686: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x029 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0c7 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3429; op2val:0xb4c7; +op3val:0x2cf8; valaddr_reg:x5; val_offset:4986*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 4986*FLEN/8, x9, x1, x4) + +inst_1687: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x029 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0c7 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0f8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3429; op2val:0xb4c7; +op3val:0x2cf8; valaddr_reg:x5; val_offset:4989*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x5, 4989*FLEN/8, x9, x1, x4) + +inst_1688: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x067 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x046 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bc4; op2val:0xb867; +op3val:0x3846; valaddr_reg:x5; val_offset:4992*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x5, 4992*FLEN/8, x9, x1, x4) + +inst_1689: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x257 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x079 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x318 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e57; op2val:0xc879; +op3val:0x3b18; valaddr_reg:x5; val_offset:4995*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x5, 4995*FLEN/8, x9, x1, x4) + +inst_1690: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x03f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1ad and fs3 == 0 and fe3 == 0x0e and fm3 == 0x207 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x383f; op2val:0xbdad; +op3val:0x3a07; valaddr_reg:x5; val_offset:4998*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x5, 4998*FLEN/8, x9, x1, x4) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(13832,32,FLEN) +NAN_BOXED(13832,16,FLEN) +NAN_BOXED(13345,32,FLEN) +NAN_BOXED(13832,32,FLEN) +NAN_BOXED(47482,16,FLEN) +NAN_BOXED(13832,32,FLEN) +NAN_BOXED(13832,32,FLEN) +NAN_BOXED(47482,16,FLEN) +NAN_BOXED(13345,32,FLEN) +NAN_BOXED(13832,32,FLEN) +NAN_BOXED(13832,16,FLEN) +NAN_BOXED(13832,32,FLEN) +NAN_BOXED(13832,32,FLEN) +NAN_BOXED(47482,16,FLEN) +NAN_BOXED(13345,32,FLEN) +NAN_BOXED(12941,32,FLEN) +NAN_BOXED(46206,16,FLEN) +NAN_BOXED(11101,32,FLEN) +NAN_BOXED(12941,32,FLEN) +NAN_BOXED(46206,16,FLEN) +NAN_BOXED(11101,32,FLEN) +NAN_BOXED(12941,32,FLEN) +NAN_BOXED(46206,16,FLEN) +NAN_BOXED(46206,32,FLEN) +NAN_BOXED(12941,32,FLEN) +NAN_BOXED(46206,16,FLEN) +NAN_BOXED(12941,32,FLEN) +NAN_BOXED(12941,32,FLEN) +NAN_BOXED(12941,16,FLEN) +NAN_BOXED(12941,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(46279,16,FLEN) +NAN_BOXED(46279,32,FLEN) +NAN_BOXED(13353,32,FLEN) +NAN_BOXED(13353,16,FLEN) +NAN_BOXED(11512,32,FLEN) +NAN_BOXED(13353,32,FLEN) +NAN_BOXED(46279,16,FLEN) +NAN_BOXED(11512,32,FLEN) +test_dataset_1: +NAN_BOXED(13353,32,FLEN) +NAN_BOXED(46279,16,FLEN) +NAN_BOXED(11512,32,FLEN) +NAN_BOXED(13353,32,FLEN) +NAN_BOXED(46279,16,FLEN) +NAN_BOXED(11512,32,FLEN) +NAN_BOXED(15300,32,FLEN) +NAN_BOXED(47207,16,FLEN) +NAN_BOXED(14406,32,FLEN) +NAN_BOXED(15300,32,FLEN) +NAN_BOXED(47207,16,FLEN) +NAN_BOXED(14406,32,FLEN) +NAN_BOXED(15300,32,FLEN) +NAN_BOXED(47207,16,FLEN) +NAN_BOXED(14406,32,FLEN) +NAN_BOXED(15300,32,FLEN) +NAN_BOXED(47207,16,FLEN) +NAN_BOXED(14406,32,FLEN) +NAN_BOXED(15300,32,FLEN) +NAN_BOXED(47207,16,FLEN) +NAN_BOXED(14406,32,FLEN) +NAN_BOXED(11072,32,FLEN) +NAN_BOXED(50738,16,FLEN) +NAN_BOXED(13725,32,FLEN) +NAN_BOXED(11072,32,FLEN) +NAN_BOXED(50738,16,FLEN) +NAN_BOXED(13725,32,FLEN) +NAN_BOXED(11072,32,FLEN) +NAN_BOXED(50738,16,FLEN) +NAN_BOXED(13725,32,FLEN) +NAN_BOXED(11072,32,FLEN) +NAN_BOXED(50738,16,FLEN) +NAN_BOXED(13725,32,FLEN) +test_dataset_2: +NAN_BOXED(11072,16,FLEN) +NAN_BOXED(50738,16,FLEN) +NAN_BOXED(13725,16,FLEN) +NAN_BOXED(11863,16,FLEN) +NAN_BOXED(51321,16,FLEN) +NAN_BOXED(15128,16,FLEN) +NAN_BOXED(11863,16,FLEN) +NAN_BOXED(51321,16,FLEN) +NAN_BOXED(15128,16,FLEN) +NAN_BOXED(11863,16,FLEN) +NAN_BOXED(51321,16,FLEN) +NAN_BOXED(15128,16,FLEN) +NAN_BOXED(11863,16,FLEN) +NAN_BOXED(51321,16,FLEN) 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+signature_x1_9: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_10: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_11: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_12: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_13: + .fill 252*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fmax_b1-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fmax_b1-01.S new file mode 100644 index 000000000..e93aa3e44 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fmax_b1-01.S @@ -0,0 +1,5929 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 05:46:07 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fmax.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fmax.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fmax_b1 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fmax_b1) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x10,test_dataset_0) +RVTEST_SIGBASE(x6,signature_x6_1) + +inst_0: +// rs1 == rd != rs2, rs1==x21, rs2==x7, rd==x21,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x21; op2:x7; dest:x21; op1val:0x0; op2val:0x0; + valaddr_reg:x10; val_offset:0*FLEN/8; fcsr: 0; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP_NRM(fmax.h, x21, x21, x7, 0, 0, x10, 0*FLEN/8, x19, x6, x13) + +inst_1: +// rs1 == rs2 == rd, rs1==x20, rs2==x20, rd==x20,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x20; op2:x20; dest:x20; op1val:0x0; op2val:0x0; + valaddr_reg:x10; val_offset:2*FLEN/8; fcsr: 0; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP_NRM(fmax.h, x20, x20, x20, 0, 0, x10, 2*FLEN/8, x19, x6, x13) + +inst_2: +// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==x17, rs2==x16, rd==x22,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x17; op2:x16; dest:x22; op1val:0x0; op2val:0x1; + valaddr_reg:x10; val_offset:4*FLEN/8; fcsr: 0; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP_NRM(fmax.h, x22, x17, x16, 0, 0, x10, 4*FLEN/8, x19, x6, x13) + +inst_3: +// rs1 == rs2 != rd, rs1==x1, rs2==x1, rd==x18,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x1; op2:x1; dest:x18; op1val:0x0; op2val:0x0; + valaddr_reg:x10; val_offset:6*FLEN/8; fcsr: 0; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP_NRM(fmax.h, x18, x1, x1, 0, 0, x10, 6*FLEN/8, x19, x6, x13) + +inst_4: +// rs2 == rd != rs1, rs1==x31, rs2==x14, rd==x14,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x31; op2:x14; dest:x14; op1val:0x0; op2val:0x2; + valaddr_reg:x10; val_offset:8*FLEN/8; fcsr: 0; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP_NRM(fmax.h, x14, x31, x14, 0, 0, x10, 8*FLEN/8, x19, x6, x13) + +inst_5: +// rs1==x4, rs2==x26, rd==x17,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x4; op2:x26; dest:x17; op1val:0x0; op2val:0x83fe; + valaddr_reg:x10; val_offset:10*FLEN/8; fcsr: 0; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP_NRM(fmax.h, x17, x4, x26, 0, 0, x10, 10*FLEN/8, x19, x6, x13) + +inst_6: +// rs1==x3, rs2==x8, rd==x24,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x3; op2:x8; dest:x24; op1val:0x0; op2val:0x3ff; + valaddr_reg:x10; val_offset:12*FLEN/8; fcsr: 0; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP_NRM(fmax.h, x24, x3, x8, 0, 0, x10, 12*FLEN/8, x19, x6, x13) + +inst_7: +// rs1==x8, rs2==x9, rd==x12,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x8; op2:x9; dest:x12; op1val:0x0; op2val:0x83ff; + valaddr_reg:x10; val_offset:14*FLEN/8; fcsr: 0; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP_NRM(fmax.h, x12, x8, x9, 0, 0, x10, 14*FLEN/8, x19, x6, x13) + +inst_8: +// rs1==x26, rs2==x3, rd==x2,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x26; op2:x3; dest:x2; op1val:0x0; op2val:0x400; + valaddr_reg:x10; val_offset:16*FLEN/8; fcsr: 0; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP_NRM(fmax.h, x2, x26, x3, 0, 0, x10, 16*FLEN/8, x19, x6, x13) + +inst_9: +// rs1==x18, rs2==x28, rd==x9,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x18; op2:x28; dest:x9; op1val:0x0; op2val:0x8400; + valaddr_reg:x10; val_offset:18*FLEN/8; fcsr: 0; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP_NRM(fmax.h, x9, x18, x28, 0, 0, x10, 18*FLEN/8, x19, x6, x13) + +inst_10: +// rs1==x2, rs2==x15, rd==x11,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x2; op2:x15; dest:x11; op1val:0x0; op2val:0x401; + valaddr_reg:x10; val_offset:20*FLEN/8; fcsr: 0; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP_NRM(fmax.h, x11, x2, x15, 0, 0, x10, 20*FLEN/8, x19, x6, x13) + +inst_11: +// rs1==x9, rs2==x5, rd==x31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x9; op2:x5; dest:x31; op1val:0x0; op2val:0x8455; + valaddr_reg:x10; val_offset:22*FLEN/8; fcsr: 0; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x9, x5, 0, 0, x10, 22*FLEN/8, x19, x6, x13) + +inst_12: +// rs1==x22, rs2==x11, rd==x15,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x22; op2:x11; dest:x15; op1val:0x0; op2val:0x7bff; + valaddr_reg:x10; val_offset:24*FLEN/8; fcsr: 0; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP_NRM(fmax.h, x15, x22, x11, 0, 0, x10, 24*FLEN/8, x19, x6, x13) + +inst_13: +// rs1==x28, rs2==x18, rd==x1,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x28; op2:x18; dest:x1; op1val:0x0; op2val:0xfbff; + valaddr_reg:x10; val_offset:26*FLEN/8; fcsr: 0; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP_NRM(fmax.h, x1, x28, x18, 0, 0, x10, 26*FLEN/8, x19, x6, x13) + +inst_14: +// rs1==x30, rs2==x12, rd==x3,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x12; dest:x3; op1val:0x0; op2val:0x7c00; + valaddr_reg:x10; val_offset:28*FLEN/8; fcsr: 0; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP_NRM(fmax.h, x3, x30, x12, 0, 0, x10, 28*FLEN/8, x19, x6, x13) +RVTEST_VALBASEUPD(x9,test_dataset_1) + +inst_15: +// rs1==x0, rs2==x30, rd==x8,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x0; op2:x30; dest:x8; op1val:0x0; op2val:0xfc00; + valaddr_reg:x9; val_offset:0*FLEN/8; fcsr: 0; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP_NRM(fmax.h, x8, x0, x30, 0, 0, x9, 0*FLEN/8, x15, x6, x13) + +inst_16: +// rs1==x14, rs2==x10, rd==x23,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x14; op2:x10; dest:x23; op1val:0x0; op2val:0x7e00; + valaddr_reg:x9; val_offset:2*FLEN/8; fcsr: 0; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP_NRM(fmax.h, x23, x14, x10, 0, 0, x9, 2*FLEN/8, x15, x6, x13) + +inst_17: +// rs1==x5, rs2==x25, rd==x27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x5; op2:x25; dest:x27; op1val:0x0; op2val:0xfe00; + valaddr_reg:x9; val_offset:4*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x27, x5, x25, 0, 0, x9, 4*FLEN/8, x15, x6, x3) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_18: +// rs1==x12, rs2==x17, rd==x26,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x12; op2:x17; dest:x26; op1val:0x0; op2val:0x7e01; + valaddr_reg:x9; val_offset:6*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x26, x12, x17, 0, 0, x9, 6*FLEN/8, x15, x1, x3) + +inst_19: +// rs1==x16, rs2==x6, rd==x0,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x16; op2:x6; dest:x0; op1val:0x0; op2val:0xfe55; + valaddr_reg:x9; val_offset:8*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x0, x16, x6, 0, 0, x9, 8*FLEN/8, x15, x1, x3) + +inst_20: +// rs1==x13, rs2==x23, rd==x29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x13; op2:x23; dest:x29; op1val:0x0; op2val:0x7c01; + valaddr_reg:x9; val_offset:10*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x29, x13, x23, 0, 0, x9, 10*FLEN/8, x15, x1, x3) + +inst_21: +// rs1==x27, rs2==x29, rd==x19,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x27; op2:x29; dest:x19; op1val:0x0; op2val:0xfd55; + valaddr_reg:x9; val_offset:12*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x19, x27, x29, 0, 0, x9, 12*FLEN/8, x15, x1, x3) + +inst_22: +// rs1==x24, rs2==x0, rd==x28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x24; op2:x0; dest:x28; op1val:0x0; op2val:0x0; + valaddr_reg:x9; val_offset:14*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x28, x24, x0, 0, 0, x9, 14*FLEN/8, x15, x1, x3) + +inst_23: +// rs1==x11, rs2==x27, rd==x5,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x11; op2:x27; dest:x5; op1val:0x0; op2val:0xbc00; + valaddr_reg:x9; val_offset:16*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x5, x11, x27, 0, 0, x9, 16*FLEN/8, x15, x1, x3) + +inst_24: +// rs1==x7, rs2==x4, rd==x6,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x7; op2:x4; dest:x6; op1val:0x8000; op2val:0x0; + valaddr_reg:x9; val_offset:18*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x6, x7, x4, 0, 0, x9, 18*FLEN/8, x15, x1, x3) + +inst_25: +// rs1==x10, rs2==x24, rd==x16,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x10; op2:x24; dest:x16; op1val:0x8000; op2val:0x8000; + valaddr_reg:x9; val_offset:20*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x16, x10, x24, 0, 0, x9, 20*FLEN/8, x15, x1, x3) + +inst_26: +// rs1==x29, rs2==x2, rd==x30,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x29; op2:x2; dest:x30; op1val:0x8000; op2val:0x1; + valaddr_reg:x9; val_offset:22*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x30, x29, x2, 0, 0, x9, 22*FLEN/8, x15, x1, x3) + +inst_27: +// rs1==x23, rs2==x19, rd==x10,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x23; op2:x19; dest:x10; op1val:0x8000; op2val:0x8001; + valaddr_reg:x9; val_offset:24*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x10, x23, x19, 0, 0, x9, 24*FLEN/8, x15, x1, x3) + +inst_28: +// rs1==x25, rs2==x22, rd==x4,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x25; op2:x22; dest:x4; op1val:0x8000; op2val:0x2; + valaddr_reg:x9; val_offset:26*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x4, x25, x22, 0, 0, x9, 26*FLEN/8, x15, x1, x3) +RVTEST_VALBASEUPD(x2,test_dataset_2) + +inst_29: +// rs1==x15, rs2==x21, rd==x13,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x15; op2:x21; dest:x13; op1val:0x8000; op2val:0x83fe; + valaddr_reg:x2; val_offset:0*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x13, x15, x21, 0, 0, x2, 0*FLEN/8, x4, x1, x3) + +inst_30: +// rs1==x19, rs2==x13, rd==x7,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x19; op2:x13; dest:x7; op1val:0x8000; op2val:0x3ff; + valaddr_reg:x2; val_offset:2*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x7, x19, x13, 0, 0, x2, 2*FLEN/8, x4, x1, x3) + +inst_31: +// rs1==x6, rs2==x31, rd==x25,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x6; op2:x31; dest:x25; op1val:0x8000; op2val:0x83ff; + valaddr_reg:x2; val_offset:4*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x25, x6, x31, 0, 0, x2, 4*FLEN/8, x4, x1, x3) + +inst_32: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x400; + valaddr_reg:x2; val_offset:6*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 6*FLEN/8, x4, x1, x3) + +inst_33: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8400; + valaddr_reg:x2; val_offset:8*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 8*FLEN/8, x4, x1, x3) + +inst_34: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x401; + valaddr_reg:x2; val_offset:10*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 10*FLEN/8, x4, x1, x3) + +inst_35: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8455; + valaddr_reg:x2; val_offset:12*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 12*FLEN/8, x4, x1, x3) + +inst_36: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x7bff; + valaddr_reg:x2; val_offset:14*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 14*FLEN/8, x4, x1, x3) + +inst_37: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xfbff; + valaddr_reg:x2; val_offset:16*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 16*FLEN/8, x4, x1, x3) + +inst_38: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x7c00; + valaddr_reg:x2; val_offset:18*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 18*FLEN/8, x4, x1, x3) + +inst_39: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xfc00; + valaddr_reg:x2; val_offset:20*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 20*FLEN/8, x4, x1, x3) + +inst_40: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x7e00; + valaddr_reg:x2; val_offset:22*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 22*FLEN/8, x4, x1, x3) + +inst_41: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xfe00; + valaddr_reg:x2; val_offset:24*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 24*FLEN/8, x4, x1, x3) + +inst_42: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x7e01; + valaddr_reg:x2; val_offset:26*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 26*FLEN/8, x4, x1, x3) + +inst_43: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xfe55; + valaddr_reg:x2; val_offset:28*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 28*FLEN/8, x4, x1, x3) + +inst_44: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x7c01; + valaddr_reg:x2; val_offset:30*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 30*FLEN/8, x4, x1, x3) + +inst_45: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xfd55; + valaddr_reg:x2; val_offset:32*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 32*FLEN/8, x4, x1, x3) + +inst_46: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x3c00; + valaddr_reg:x2; val_offset:34*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 34*FLEN/8, x4, x1, x3) + +inst_47: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xbc00; + valaddr_reg:x2; val_offset:36*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 36*FLEN/8, x4, x1, x3) + +inst_48: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x0; + valaddr_reg:x2; val_offset:38*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 38*FLEN/8, x4, x1, x3) + +inst_49: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x8000; + valaddr_reg:x2; val_offset:40*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 40*FLEN/8, x4, x1, x3) + +inst_50: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x1; + valaddr_reg:x2; val_offset:42*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 42*FLEN/8, x4, x1, x3) + +inst_51: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x8001; + valaddr_reg:x2; val_offset:44*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 44*FLEN/8, x4, x1, x3) + +inst_52: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x2; + valaddr_reg:x2; val_offset:46*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 46*FLEN/8, x4, x1, x3) + +inst_53: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x83fe; + valaddr_reg:x2; val_offset:48*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 48*FLEN/8, x4, x1, x3) + +inst_54: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x3ff; + valaddr_reg:x2; val_offset:50*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 50*FLEN/8, x4, x1, x3) + +inst_55: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x83ff; + valaddr_reg:x2; val_offset:52*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 52*FLEN/8, x4, x1, x3) + +inst_56: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x400; + valaddr_reg:x2; val_offset:54*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 54*FLEN/8, x4, x1, x3) + +inst_57: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x8400; + valaddr_reg:x2; val_offset:56*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 56*FLEN/8, x4, x1, x3) + +inst_58: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x401; + valaddr_reg:x2; val_offset:58*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 58*FLEN/8, x4, x1, x3) + +inst_59: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x8455; + valaddr_reg:x2; val_offset:60*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 60*FLEN/8, x4, x1, x3) + +inst_60: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7bff; + valaddr_reg:x2; val_offset:62*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 62*FLEN/8, x4, x1, x3) + +inst_61: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xfbff; + valaddr_reg:x2; val_offset:64*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 64*FLEN/8, x4, x1, x3) + +inst_62: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7c00; + valaddr_reg:x2; val_offset:66*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 66*FLEN/8, x4, x1, x3) + +inst_63: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xfc00; + valaddr_reg:x2; val_offset:68*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 68*FLEN/8, x4, x1, x3) + +inst_64: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7e00; + valaddr_reg:x2; val_offset:70*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 70*FLEN/8, x4, x1, x3) + +inst_65: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xfe00; + valaddr_reg:x2; val_offset:72*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 72*FLEN/8, x4, x1, x3) + +inst_66: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7e01; + valaddr_reg:x2; val_offset:74*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 74*FLEN/8, x4, x1, x3) + +inst_67: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xfe55; + valaddr_reg:x2; val_offset:76*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 76*FLEN/8, x4, x1, x3) + +inst_68: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7c01; + valaddr_reg:x2; val_offset:78*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 78*FLEN/8, x4, x1, x3) + +inst_69: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xfd55; + valaddr_reg:x2; val_offset:80*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 80*FLEN/8, x4, x1, x3) + +inst_70: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x3c00; + valaddr_reg:x2; val_offset:82*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 82*FLEN/8, x4, x1, x3) + +inst_71: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xbc00; + valaddr_reg:x2; val_offset:84*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 84*FLEN/8, x4, x1, x3) + +inst_72: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x0; + valaddr_reg:x2; val_offset:86*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 86*FLEN/8, x4, x1, x3) + +inst_73: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8000; + valaddr_reg:x2; val_offset:88*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 88*FLEN/8, x4, x1, x3) + +inst_74: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x1; + valaddr_reg:x2; val_offset:90*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 90*FLEN/8, x4, x1, x3) + +inst_75: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8001; + valaddr_reg:x2; val_offset:92*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 92*FLEN/8, x4, x1, x3) + +inst_76: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x2; + valaddr_reg:x2; val_offset:94*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 94*FLEN/8, x4, x1, x3) + +inst_77: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x83fe; + valaddr_reg:x2; val_offset:96*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 96*FLEN/8, x4, x1, x3) + +inst_78: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x3ff; + valaddr_reg:x2; val_offset:98*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 98*FLEN/8, x4, x1, x3) + +inst_79: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x83ff; + valaddr_reg:x2; val_offset:100*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 100*FLEN/8, x4, x1, x3) + +inst_80: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x400; + valaddr_reg:x2; val_offset:102*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 102*FLEN/8, x4, x1, x3) + +inst_81: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8400; + valaddr_reg:x2; val_offset:104*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 104*FLEN/8, x4, x1, x3) + +inst_82: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x401; + valaddr_reg:x2; val_offset:106*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 106*FLEN/8, x4, x1, x3) + +inst_83: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8455; + valaddr_reg:x2; val_offset:108*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 108*FLEN/8, x4, x1, x3) + +inst_84: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x7bff; + valaddr_reg:x2; val_offset:110*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 110*FLEN/8, x4, x1, x3) + +inst_85: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xfbff; + valaddr_reg:x2; val_offset:112*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 112*FLEN/8, x4, x1, x3) + +inst_86: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x7c00; + valaddr_reg:x2; val_offset:114*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 114*FLEN/8, x4, x1, x3) + +inst_87: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xfc00; + valaddr_reg:x2; val_offset:116*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 116*FLEN/8, x4, x1, x3) + +inst_88: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x7e00; + valaddr_reg:x2; val_offset:118*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 118*FLEN/8, x4, x1, x3) + +inst_89: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xfe00; + valaddr_reg:x2; val_offset:120*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 120*FLEN/8, x4, x1, x3) + +inst_90: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x7e01; + valaddr_reg:x2; val_offset:122*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 122*FLEN/8, x4, x1, x3) + +inst_91: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xfe55; + valaddr_reg:x2; val_offset:124*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 124*FLEN/8, x4, x1, x3) + +inst_92: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x7c01; + valaddr_reg:x2; val_offset:126*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 126*FLEN/8, x4, x1, x3) + +inst_93: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xfd55; + valaddr_reg:x2; val_offset:128*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 128*FLEN/8, x4, x1, x3) + +inst_94: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x3c00; + valaddr_reg:x2; val_offset:130*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 130*FLEN/8, x4, x1, x3) + +inst_95: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xbc00; + valaddr_reg:x2; val_offset:132*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 132*FLEN/8, x4, x1, x3) + +inst_96: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x0; + valaddr_reg:x2; val_offset:134*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 134*FLEN/8, x4, x1, x3) + +inst_97: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x8000; + valaddr_reg:x2; val_offset:136*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 136*FLEN/8, x4, x1, x3) + +inst_98: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x1; + valaddr_reg:x2; val_offset:138*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 138*FLEN/8, x4, x1, x3) + +inst_99: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x8001; + valaddr_reg:x2; val_offset:140*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 140*FLEN/8, x4, x1, x3) + +inst_100: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x2; + valaddr_reg:x2; val_offset:142*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 142*FLEN/8, x4, x1, x3) + +inst_101: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x83fe; + valaddr_reg:x2; val_offset:144*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 144*FLEN/8, x4, x1, x3) + +inst_102: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x3ff; + valaddr_reg:x2; val_offset:146*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 146*FLEN/8, x4, x1, x3) + +inst_103: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x83ff; + valaddr_reg:x2; val_offset:148*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 148*FLEN/8, x4, x1, x3) + +inst_104: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x400; + valaddr_reg:x2; val_offset:150*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 150*FLEN/8, x4, x1, x3) + +inst_105: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x8400; + valaddr_reg:x2; val_offset:152*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 152*FLEN/8, x4, x1, x3) + +inst_106: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x401; + valaddr_reg:x2; val_offset:154*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 154*FLEN/8, x4, x1, x3) + +inst_107: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x8455; + valaddr_reg:x2; val_offset:156*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 156*FLEN/8, x4, x1, x3) + +inst_108: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x7bff; + valaddr_reg:x2; val_offset:158*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 158*FLEN/8, x4, x1, x3) + +inst_109: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xfbff; + valaddr_reg:x2; val_offset:160*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 160*FLEN/8, x4, x1, x3) + +inst_110: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x7c00; + valaddr_reg:x2; val_offset:162*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 162*FLEN/8, x4, x1, x3) + +inst_111: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xfc00; + valaddr_reg:x2; val_offset:164*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 164*FLEN/8, x4, x1, x3) + +inst_112: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x7e00; + valaddr_reg:x2; val_offset:166*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 166*FLEN/8, x4, x1, x3) + +inst_113: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xfe00; + valaddr_reg:x2; val_offset:168*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 168*FLEN/8, x4, x1, x3) + +inst_114: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x7e01; + valaddr_reg:x2; val_offset:170*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 170*FLEN/8, x4, x1, x3) + +inst_115: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xfe55; + valaddr_reg:x2; val_offset:172*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 172*FLEN/8, x4, x1, x3) + +inst_116: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x7c01; + valaddr_reg:x2; val_offset:174*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 174*FLEN/8, x4, x1, x3) + +inst_117: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xfd55; + valaddr_reg:x2; val_offset:176*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 176*FLEN/8, x4, x1, x3) + +inst_118: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x3c00; + valaddr_reg:x2; val_offset:178*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 178*FLEN/8, x4, x1, x3) + +inst_119: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xbc00; + valaddr_reg:x2; val_offset:180*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 180*FLEN/8, x4, x1, x3) + +inst_120: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x0; + valaddr_reg:x2; val_offset:182*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 182*FLEN/8, x4, x1, x3) + +inst_121: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x8000; + valaddr_reg:x2; val_offset:184*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 184*FLEN/8, x4, x1, x3) + +inst_122: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x1; + valaddr_reg:x2; val_offset:186*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 186*FLEN/8, x4, x1, x3) + +inst_123: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x8001; + valaddr_reg:x2; val_offset:188*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 188*FLEN/8, x4, x1, x3) + +inst_124: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x2; + valaddr_reg:x2; val_offset:190*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 190*FLEN/8, x4, x1, x3) + +inst_125: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x83fe; + valaddr_reg:x2; val_offset:192*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 192*FLEN/8, x4, x1, x3) + +inst_126: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x3ff; + valaddr_reg:x2; val_offset:194*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 194*FLEN/8, x4, x1, x3) + +inst_127: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x83ff; + valaddr_reg:x2; val_offset:196*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 196*FLEN/8, x4, x1, x3) + +inst_128: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x400; + valaddr_reg:x2; val_offset:198*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 198*FLEN/8, x4, x1, x3) + +inst_129: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x8400; + valaddr_reg:x2; val_offset:200*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 200*FLEN/8, x4, x1, x3) + +inst_130: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x401; + valaddr_reg:x2; val_offset:202*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 202*FLEN/8, x4, x1, x3) + +inst_131: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x8455; + valaddr_reg:x2; val_offset:204*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 204*FLEN/8, x4, x1, x3) + +inst_132: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x7bff; + valaddr_reg:x2; val_offset:206*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 206*FLEN/8, x4, x1, x3) + +inst_133: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xfbff; + valaddr_reg:x2; val_offset:208*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 208*FLEN/8, x4, x1, x3) + +inst_134: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x7c00; + valaddr_reg:x2; val_offset:210*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 210*FLEN/8, x4, x1, x3) + +inst_135: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xfc00; + valaddr_reg:x2; val_offset:212*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 212*FLEN/8, x4, x1, x3) + +inst_136: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x7e00; + valaddr_reg:x2; val_offset:214*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 214*FLEN/8, x4, x1, x3) + +inst_137: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xfe00; + valaddr_reg:x2; val_offset:216*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 216*FLEN/8, x4, x1, x3) + +inst_138: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x7e01; + valaddr_reg:x2; val_offset:218*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 218*FLEN/8, x4, x1, x3) + +inst_139: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xfe55; + valaddr_reg:x2; val_offset:220*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 220*FLEN/8, x4, x1, x3) + +inst_140: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x7c01; + valaddr_reg:x2; val_offset:222*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 222*FLEN/8, x4, x1, x3) + +inst_141: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xfd55; + valaddr_reg:x2; val_offset:224*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 224*FLEN/8, x4, x1, x3) + +inst_142: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x3c00; + valaddr_reg:x2; val_offset:226*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 226*FLEN/8, x4, x1, x3) + +inst_143: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xbc00; + valaddr_reg:x2; val_offset:228*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 228*FLEN/8, x4, x1, x3) + +inst_144: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x0; + valaddr_reg:x2; val_offset:230*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 230*FLEN/8, x4, x1, x3) + +inst_145: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x8000; + valaddr_reg:x2; val_offset:232*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 232*FLEN/8, x4, x1, x3) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_146: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x1; + valaddr_reg:x2; val_offset:234*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 234*FLEN/8, x4, x1, x3) + +inst_147: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x8001; + valaddr_reg:x2; val_offset:236*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 236*FLEN/8, x4, x1, x3) + +inst_148: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x2; + valaddr_reg:x2; val_offset:238*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 238*FLEN/8, x4, x1, x3) + +inst_149: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x83fe; + valaddr_reg:x2; val_offset:240*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 240*FLEN/8, x4, x1, x3) + +inst_150: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x3ff; + valaddr_reg:x2; val_offset:242*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 242*FLEN/8, x4, x1, x3) + +inst_151: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x83ff; + valaddr_reg:x2; val_offset:244*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 244*FLEN/8, x4, x1, x3) + +inst_152: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x400; + valaddr_reg:x2; val_offset:246*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 246*FLEN/8, x4, x1, x3) + +inst_153: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x8400; + valaddr_reg:x2; val_offset:248*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 248*FLEN/8, x4, x1, x3) + +inst_154: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x401; + valaddr_reg:x2; val_offset:250*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 250*FLEN/8, x4, x1, x3) + +inst_155: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x8455; + valaddr_reg:x2; val_offset:252*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 252*FLEN/8, x4, x1, x3) + +inst_156: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7bff; + valaddr_reg:x2; val_offset:254*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 254*FLEN/8, x4, x1, x3) + +inst_157: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xfbff; + valaddr_reg:x2; val_offset:256*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 256*FLEN/8, x4, x1, x3) + +inst_158: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7c00; + valaddr_reg:x2; val_offset:258*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 258*FLEN/8, x4, x1, x3) + +inst_159: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xfc00; + valaddr_reg:x2; val_offset:260*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 260*FLEN/8, x4, x1, x3) + +inst_160: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7e00; + valaddr_reg:x2; val_offset:262*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 262*FLEN/8, x4, x1, x3) + +inst_161: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xfe00; + valaddr_reg:x2; val_offset:264*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 264*FLEN/8, x4, x1, x3) + +inst_162: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7e01; + valaddr_reg:x2; val_offset:266*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 266*FLEN/8, x4, x1, x3) + +inst_163: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xfe55; + valaddr_reg:x2; val_offset:268*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 268*FLEN/8, x4, x1, x3) + +inst_164: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7c01; + valaddr_reg:x2; val_offset:270*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 270*FLEN/8, x4, x1, x3) + +inst_165: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xfd55; + valaddr_reg:x2; val_offset:272*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 272*FLEN/8, x4, x1, x3) + +inst_166: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x3c00; + valaddr_reg:x2; val_offset:274*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 274*FLEN/8, x4, x1, x3) + +inst_167: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xbc00; + valaddr_reg:x2; val_offset:276*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 276*FLEN/8, x4, x1, x3) + +inst_168: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x0; + valaddr_reg:x2; val_offset:278*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 278*FLEN/8, x4, x1, x3) + +inst_169: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8000; + valaddr_reg:x2; val_offset:280*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 280*FLEN/8, x4, x1, x3) + +inst_170: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x1; + valaddr_reg:x2; val_offset:282*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 282*FLEN/8, x4, x1, x3) + +inst_171: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8001; + valaddr_reg:x2; val_offset:284*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 284*FLEN/8, x4, x1, x3) + +inst_172: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x2; + valaddr_reg:x2; val_offset:286*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 286*FLEN/8, x4, x1, x3) + +inst_173: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x83fe; + valaddr_reg:x2; val_offset:288*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 288*FLEN/8, x4, x1, x3) + +inst_174: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x3ff; + valaddr_reg:x2; val_offset:290*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 290*FLEN/8, x4, x1, x3) + +inst_175: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x83ff; + valaddr_reg:x2; val_offset:292*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 292*FLEN/8, x4, x1, x3) + +inst_176: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x400; + valaddr_reg:x2; val_offset:294*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 294*FLEN/8, x4, x1, x3) + +inst_177: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8400; + valaddr_reg:x2; val_offset:296*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 296*FLEN/8, x4, x1, x3) + +inst_178: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x401; + valaddr_reg:x2; val_offset:298*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 298*FLEN/8, x4, x1, x3) + +inst_179: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8455; + valaddr_reg:x2; val_offset:300*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 300*FLEN/8, x4, x1, x3) + +inst_180: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x7bff; + valaddr_reg:x2; val_offset:302*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 302*FLEN/8, x4, x1, x3) + +inst_181: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xfbff; + valaddr_reg:x2; val_offset:304*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 304*FLEN/8, x4, x1, x3) + +inst_182: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x7c00; + valaddr_reg:x2; val_offset:306*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 306*FLEN/8, x4, x1, x3) + +inst_183: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xfc00; + valaddr_reg:x2; val_offset:308*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 308*FLEN/8, x4, x1, x3) + +inst_184: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x7e00; + valaddr_reg:x2; val_offset:310*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 310*FLEN/8, x4, x1, x3) + +inst_185: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xfe00; + valaddr_reg:x2; val_offset:312*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 312*FLEN/8, x4, x1, x3) + +inst_186: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x7e01; + valaddr_reg:x2; val_offset:314*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 314*FLEN/8, x4, x1, x3) + +inst_187: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xfe55; + valaddr_reg:x2; val_offset:316*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 316*FLEN/8, x4, x1, x3) + +inst_188: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x7c01; + valaddr_reg:x2; val_offset:318*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 318*FLEN/8, x4, x1, x3) + +inst_189: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xfd55; + valaddr_reg:x2; val_offset:320*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 320*FLEN/8, x4, x1, x3) + +inst_190: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x3c00; + valaddr_reg:x2; val_offset:322*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 322*FLEN/8, x4, x1, x3) + +inst_191: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xbc00; + valaddr_reg:x2; val_offset:324*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 324*FLEN/8, x4, x1, x3) + +inst_192: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x0; + valaddr_reg:x2; val_offset:326*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 326*FLEN/8, x4, x1, x3) + +inst_193: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x8000; + valaddr_reg:x2; val_offset:328*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 328*FLEN/8, x4, x1, x3) + +inst_194: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x1; + valaddr_reg:x2; val_offset:330*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 330*FLEN/8, x4, x1, x3) + +inst_195: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x8001; + valaddr_reg:x2; val_offset:332*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 332*FLEN/8, x4, x1, x3) + +inst_196: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x2; + valaddr_reg:x2; val_offset:334*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 334*FLEN/8, x4, x1, x3) + +inst_197: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x83fe; + valaddr_reg:x2; val_offset:336*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 336*FLEN/8, x4, x1, x3) + +inst_198: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x3ff; + valaddr_reg:x2; val_offset:338*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 338*FLEN/8, x4, x1, x3) + +inst_199: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x83ff; + valaddr_reg:x2; val_offset:340*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 340*FLEN/8, x4, x1, x3) + +inst_200: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x400; + valaddr_reg:x2; val_offset:342*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 342*FLEN/8, x4, x1, x3) + +inst_201: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x8400; + valaddr_reg:x2; val_offset:344*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 344*FLEN/8, x4, x1, x3) + +inst_202: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x401; + valaddr_reg:x2; val_offset:346*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 346*FLEN/8, x4, x1, x3) + +inst_203: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x8455; + valaddr_reg:x2; val_offset:348*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 348*FLEN/8, x4, x1, x3) + +inst_204: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7bff; + valaddr_reg:x2; val_offset:350*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 350*FLEN/8, x4, x1, x3) + +inst_205: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xfbff; + valaddr_reg:x2; val_offset:352*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 352*FLEN/8, x4, x1, x3) + +inst_206: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7c00; + valaddr_reg:x2; val_offset:354*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 354*FLEN/8, x4, x1, x3) + +inst_207: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xfc00; + valaddr_reg:x2; val_offset:356*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 356*FLEN/8, x4, x1, x3) + +inst_208: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7e00; + valaddr_reg:x2; val_offset:358*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 358*FLEN/8, x4, x1, x3) + +inst_209: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xfe00; + valaddr_reg:x2; val_offset:360*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 360*FLEN/8, x4, x1, x3) + +inst_210: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7e01; + valaddr_reg:x2; val_offset:362*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 362*FLEN/8, x4, x1, x3) + +inst_211: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xfe55; + valaddr_reg:x2; val_offset:364*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 364*FLEN/8, x4, x1, x3) + +inst_212: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7c01; + valaddr_reg:x2; val_offset:366*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 366*FLEN/8, x4, x1, x3) + +inst_213: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xfd55; + valaddr_reg:x2; val_offset:368*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 368*FLEN/8, x4, x1, x3) + +inst_214: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x3c00; + valaddr_reg:x2; val_offset:370*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 370*FLEN/8, x4, x1, x3) + +inst_215: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xbc00; + valaddr_reg:x2; val_offset:372*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 372*FLEN/8, x4, x1, x3) + +inst_216: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x0; + valaddr_reg:x2; val_offset:374*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 374*FLEN/8, x4, x1, x3) + +inst_217: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8000; + valaddr_reg:x2; val_offset:376*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 376*FLEN/8, x4, x1, x3) + +inst_218: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x1; + valaddr_reg:x2; val_offset:378*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 378*FLEN/8, x4, x1, x3) + +inst_219: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8001; + valaddr_reg:x2; val_offset:380*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 380*FLEN/8, x4, x1, x3) + +inst_220: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x2; + valaddr_reg:x2; val_offset:382*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 382*FLEN/8, x4, x1, x3) + +inst_221: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x83fe; + valaddr_reg:x2; val_offset:384*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 384*FLEN/8, x4, x1, x3) + +inst_222: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x3ff; + valaddr_reg:x2; val_offset:386*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 386*FLEN/8, x4, x1, x3) + +inst_223: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x83ff; + valaddr_reg:x2; val_offset:388*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 388*FLEN/8, x4, x1, x3) + +inst_224: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x400; + valaddr_reg:x2; val_offset:390*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 390*FLEN/8, x4, x1, x3) + +inst_225: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8400; + valaddr_reg:x2; val_offset:392*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 392*FLEN/8, x4, x1, x3) + +inst_226: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x401; + valaddr_reg:x2; val_offset:394*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 394*FLEN/8, x4, x1, x3) + +inst_227: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8455; + valaddr_reg:x2; val_offset:396*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 396*FLEN/8, x4, x1, x3) + +inst_228: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x7bff; + valaddr_reg:x2; val_offset:398*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 398*FLEN/8, x4, x1, x3) + +inst_229: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xfbff; + valaddr_reg:x2; val_offset:400*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 400*FLEN/8, x4, x1, x3) + +inst_230: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x7c00; + valaddr_reg:x2; val_offset:402*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 402*FLEN/8, x4, x1, x3) + +inst_231: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xfc00; + valaddr_reg:x2; val_offset:404*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 404*FLEN/8, x4, x1, x3) + +inst_232: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x7e00; + valaddr_reg:x2; val_offset:406*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 406*FLEN/8, x4, x1, x3) + +inst_233: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xfe00; + valaddr_reg:x2; val_offset:408*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 408*FLEN/8, x4, x1, x3) + +inst_234: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x7e01; + valaddr_reg:x2; val_offset:410*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 410*FLEN/8, x4, x1, x3) + +inst_235: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xfe55; + valaddr_reg:x2; val_offset:412*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 412*FLEN/8, x4, x1, x3) + +inst_236: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x7c01; + valaddr_reg:x2; val_offset:414*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 414*FLEN/8, x4, x1, x3) + +inst_237: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xfd55; + valaddr_reg:x2; val_offset:416*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 416*FLEN/8, x4, x1, x3) + +inst_238: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x3c00; + valaddr_reg:x2; val_offset:418*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 418*FLEN/8, x4, x1, x3) + +inst_239: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xbc00; + valaddr_reg:x2; val_offset:420*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 420*FLEN/8, x4, x1, x3) + +inst_240: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x0; + valaddr_reg:x2; val_offset:422*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 422*FLEN/8, x4, x1, x3) + +inst_241: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x8000; + valaddr_reg:x2; val_offset:424*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 424*FLEN/8, x4, x1, x3) + +inst_242: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x1; + valaddr_reg:x2; val_offset:426*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 426*FLEN/8, x4, x1, x3) + +inst_243: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x8001; + valaddr_reg:x2; val_offset:428*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 428*FLEN/8, x4, x1, x3) + +inst_244: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x2; + valaddr_reg:x2; val_offset:430*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 430*FLEN/8, x4, x1, x3) + +inst_245: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x83fe; + valaddr_reg:x2; val_offset:432*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 432*FLEN/8, x4, x1, x3) + +inst_246: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x3ff; + valaddr_reg:x2; val_offset:434*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 434*FLEN/8, x4, x1, x3) + +inst_247: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x83ff; + valaddr_reg:x2; val_offset:436*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 436*FLEN/8, x4, x1, x3) + +inst_248: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x400; + valaddr_reg:x2; val_offset:438*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 438*FLEN/8, x4, x1, x3) + +inst_249: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x8400; + valaddr_reg:x2; val_offset:440*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 440*FLEN/8, x4, x1, x3) + +inst_250: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x401; + valaddr_reg:x2; val_offset:442*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 442*FLEN/8, x4, x1, x3) + +inst_251: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x8455; + valaddr_reg:x2; val_offset:444*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 444*FLEN/8, x4, x1, x3) + +inst_252: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x7bff; + valaddr_reg:x2; val_offset:446*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 446*FLEN/8, x4, x1, x3) + +inst_253: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xfbff; + valaddr_reg:x2; val_offset:448*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 448*FLEN/8, x4, x1, x3) + +inst_254: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x7c00; + valaddr_reg:x2; val_offset:450*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 450*FLEN/8, x4, x1, x3) + +inst_255: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xfc00; + valaddr_reg:x2; val_offset:452*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 452*FLEN/8, x4, x1, x3) + +inst_256: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x7e00; + valaddr_reg:x2; val_offset:454*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 454*FLEN/8, x4, x1, x3) + +inst_257: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xfe00; + valaddr_reg:x2; val_offset:456*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 456*FLEN/8, x4, x1, x3) + +inst_258: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x7e01; + valaddr_reg:x2; val_offset:458*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 458*FLEN/8, x4, x1, x3) + +inst_259: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xfe55; + valaddr_reg:x2; val_offset:460*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 460*FLEN/8, x4, x1, x3) + +inst_260: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x7c01; + valaddr_reg:x2; val_offset:462*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 462*FLEN/8, x4, x1, x3) + +inst_261: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xfd55; + valaddr_reg:x2; val_offset:464*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 464*FLEN/8, x4, x1, x3) + +inst_262: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x3c00; + valaddr_reg:x2; val_offset:466*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 466*FLEN/8, x4, x1, x3) + +inst_263: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xbc00; + valaddr_reg:x2; val_offset:468*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 468*FLEN/8, x4, x1, x3) + +inst_264: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x0; + valaddr_reg:x2; val_offset:470*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 470*FLEN/8, x4, x1, x3) + +inst_265: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x8000; + valaddr_reg:x2; val_offset:472*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 472*FLEN/8, x4, x1, x3) + +inst_266: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x1; + valaddr_reg:x2; val_offset:474*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 474*FLEN/8, x4, x1, x3) + +inst_267: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x8001; + valaddr_reg:x2; val_offset:476*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 476*FLEN/8, x4, x1, x3) + +inst_268: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x2; + valaddr_reg:x2; val_offset:478*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 478*FLEN/8, x4, x1, x3) + +inst_269: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x83fe; + valaddr_reg:x2; val_offset:480*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 480*FLEN/8, x4, x1, x3) + +inst_270: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x3ff; + valaddr_reg:x2; val_offset:482*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 482*FLEN/8, x4, x1, x3) + +inst_271: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x83ff; + valaddr_reg:x2; val_offset:484*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 484*FLEN/8, x4, x1, x3) + +inst_272: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x400; + valaddr_reg:x2; val_offset:486*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 486*FLEN/8, x4, x1, x3) + +inst_273: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x8400; + valaddr_reg:x2; val_offset:488*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 488*FLEN/8, x4, x1, x3) +RVTEST_SIGBASE(x1,signature_x1_2) + +inst_274: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x401; + valaddr_reg:x2; val_offset:490*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 490*FLEN/8, x4, x1, x3) + +inst_275: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x8455; + valaddr_reg:x2; val_offset:492*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 492*FLEN/8, x4, x1, x3) + +inst_276: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x7bff; + valaddr_reg:x2; val_offset:494*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 494*FLEN/8, x4, x1, x3) + +inst_277: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xfbff; + valaddr_reg:x2; val_offset:496*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 496*FLEN/8, x4, x1, x3) + +inst_278: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x7c00; + valaddr_reg:x2; val_offset:498*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 498*FLEN/8, x4, x1, x3) + +inst_279: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xfc00; + valaddr_reg:x2; val_offset:500*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 500*FLEN/8, x4, x1, x3) + +inst_280: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x7e00; + valaddr_reg:x2; val_offset:502*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 502*FLEN/8, x4, x1, x3) + +inst_281: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xfe00; + valaddr_reg:x2; val_offset:504*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 504*FLEN/8, x4, x1, x3) + +inst_282: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x7e01; + valaddr_reg:x2; val_offset:506*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 506*FLEN/8, x4, x1, x3) + +inst_283: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xfe55; + valaddr_reg:x2; val_offset:508*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 508*FLEN/8, x4, x1, x3) + +inst_284: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x7c01; + valaddr_reg:x2; val_offset:510*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 510*FLEN/8, x4, x1, x3) + +inst_285: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xfd55; + valaddr_reg:x2; val_offset:512*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 512*FLEN/8, x4, x1, x3) + +inst_286: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x3c00; + valaddr_reg:x2; val_offset:514*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 514*FLEN/8, x4, x1, x3) + +inst_287: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xbc00; + valaddr_reg:x2; val_offset:516*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 516*FLEN/8, x4, x1, x3) + +inst_288: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x0; + valaddr_reg:x2; val_offset:518*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 518*FLEN/8, x4, x1, x3) + +inst_289: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8000; + valaddr_reg:x2; val_offset:520*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 520*FLEN/8, x4, x1, x3) + +inst_290: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x1; + valaddr_reg:x2; val_offset:522*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 522*FLEN/8, x4, x1, x3) + +inst_291: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8001; + valaddr_reg:x2; val_offset:524*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 524*FLEN/8, x4, x1, x3) + +inst_292: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x2; + valaddr_reg:x2; val_offset:526*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 526*FLEN/8, x4, x1, x3) + +inst_293: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x83fe; + valaddr_reg:x2; val_offset:528*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 528*FLEN/8, x4, x1, x3) + +inst_294: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x3ff; + valaddr_reg:x2; val_offset:530*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 530*FLEN/8, x4, x1, x3) + +inst_295: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x83ff; + valaddr_reg:x2; val_offset:532*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 532*FLEN/8, x4, x1, x3) + +inst_296: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x400; + valaddr_reg:x2; val_offset:534*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 534*FLEN/8, x4, x1, x3) + +inst_297: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8400; + valaddr_reg:x2; val_offset:536*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 536*FLEN/8, x4, x1, x3) + +inst_298: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x401; + valaddr_reg:x2; val_offset:538*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 538*FLEN/8, x4, x1, x3) + +inst_299: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8455; + valaddr_reg:x2; val_offset:540*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 540*FLEN/8, x4, x1, x3) + +inst_300: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7bff; + valaddr_reg:x2; val_offset:542*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 542*FLEN/8, x4, x1, x3) + +inst_301: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xfbff; + valaddr_reg:x2; val_offset:544*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 544*FLEN/8, x4, x1, x3) + +inst_302: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7c00; + valaddr_reg:x2; val_offset:546*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 546*FLEN/8, x4, x1, x3) + +inst_303: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xfc00; + valaddr_reg:x2; val_offset:548*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 548*FLEN/8, x4, x1, x3) + +inst_304: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7e00; + valaddr_reg:x2; val_offset:550*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 550*FLEN/8, x4, x1, x3) + +inst_305: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xfe00; + valaddr_reg:x2; val_offset:552*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 552*FLEN/8, x4, x1, x3) + +inst_306: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7e01; + valaddr_reg:x2; val_offset:554*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 554*FLEN/8, x4, x1, x3) + +inst_307: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xfe55; + valaddr_reg:x2; val_offset:556*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 556*FLEN/8, x4, x1, x3) + +inst_308: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7c01; + valaddr_reg:x2; val_offset:558*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 558*FLEN/8, x4, x1, x3) + +inst_309: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xfd55; + valaddr_reg:x2; val_offset:560*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 560*FLEN/8, x4, x1, x3) + +inst_310: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x3c00; + valaddr_reg:x2; val_offset:562*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 562*FLEN/8, x4, x1, x3) + +inst_311: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xbc00; + valaddr_reg:x2; val_offset:564*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 564*FLEN/8, x4, x1, x3) + +inst_312: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x0; + valaddr_reg:x2; val_offset:566*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 566*FLEN/8, x4, x1, x3) + +inst_313: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8000; + valaddr_reg:x2; val_offset:568*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 568*FLEN/8, x4, x1, x3) + +inst_314: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x1; + valaddr_reg:x2; val_offset:570*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 570*FLEN/8, x4, x1, x3) + +inst_315: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8001; + valaddr_reg:x2; val_offset:572*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 572*FLEN/8, x4, x1, x3) + +inst_316: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x2; + valaddr_reg:x2; val_offset:574*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 574*FLEN/8, x4, x1, x3) + +inst_317: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x83fe; + valaddr_reg:x2; val_offset:576*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 576*FLEN/8, x4, x1, x3) + +inst_318: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x3ff; + valaddr_reg:x2; val_offset:578*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 578*FLEN/8, x4, x1, x3) + +inst_319: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x83ff; + valaddr_reg:x2; val_offset:580*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 580*FLEN/8, x4, x1, x3) + +inst_320: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x400; + valaddr_reg:x2; val_offset:582*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 582*FLEN/8, x4, x1, x3) + +inst_321: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8400; + valaddr_reg:x2; val_offset:584*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 584*FLEN/8, x4, x1, x3) + +inst_322: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x401; + valaddr_reg:x2; val_offset:586*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 586*FLEN/8, x4, x1, x3) + +inst_323: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8455; + valaddr_reg:x2; val_offset:588*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 588*FLEN/8, x4, x1, x3) + +inst_324: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7bff; + valaddr_reg:x2; val_offset:590*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 590*FLEN/8, x4, x1, x3) + +inst_325: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfbff; + valaddr_reg:x2; val_offset:592*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 592*FLEN/8, x4, x1, x3) + +inst_326: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7c00; + valaddr_reg:x2; val_offset:594*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 594*FLEN/8, x4, x1, x3) + +inst_327: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfc00; + valaddr_reg:x2; val_offset:596*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 596*FLEN/8, x4, x1, x3) + +inst_328: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7e00; + valaddr_reg:x2; val_offset:598*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 598*FLEN/8, x4, x1, x3) + +inst_329: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfe00; + valaddr_reg:x2; val_offset:600*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 600*FLEN/8, x4, x1, x3) + +inst_330: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7e01; + valaddr_reg:x2; val_offset:602*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 602*FLEN/8, x4, x1, x3) + +inst_331: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfe55; + valaddr_reg:x2; val_offset:604*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 604*FLEN/8, x4, x1, x3) + +inst_332: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7c01; + valaddr_reg:x2; val_offset:606*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 606*FLEN/8, x4, x1, x3) + +inst_333: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfd55; + valaddr_reg:x2; val_offset:608*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 608*FLEN/8, x4, x1, x3) + +inst_334: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x3c00; + valaddr_reg:x2; val_offset:610*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 610*FLEN/8, x4, x1, x3) + +inst_335: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xbc00; + valaddr_reg:x2; val_offset:612*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 612*FLEN/8, x4, x1, x3) + +inst_336: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x0; + valaddr_reg:x2; val_offset:614*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 614*FLEN/8, x4, x1, x3) + +inst_337: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x8000; + valaddr_reg:x2; val_offset:616*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 616*FLEN/8, x4, x1, x3) + +inst_338: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x1; + valaddr_reg:x2; val_offset:618*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 618*FLEN/8, x4, x1, x3) + +inst_339: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x8001; + valaddr_reg:x2; val_offset:620*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 620*FLEN/8, x4, x1, x3) + +inst_340: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x2; + valaddr_reg:x2; val_offset:622*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 622*FLEN/8, x4, x1, x3) + +inst_341: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x83fe; + valaddr_reg:x2; val_offset:624*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 624*FLEN/8, x4, x1, x3) + +inst_342: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x3ff; + valaddr_reg:x2; val_offset:626*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 626*FLEN/8, x4, x1, x3) + +inst_343: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x83ff; + valaddr_reg:x2; val_offset:628*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 628*FLEN/8, x4, x1, x3) + +inst_344: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x400; + valaddr_reg:x2; val_offset:630*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 630*FLEN/8, x4, x1, x3) + +inst_345: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x8400; + valaddr_reg:x2; val_offset:632*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 632*FLEN/8, x4, x1, x3) + +inst_346: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x401; + valaddr_reg:x2; val_offset:634*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 634*FLEN/8, x4, x1, x3) + +inst_347: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x8455; + valaddr_reg:x2; val_offset:636*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 636*FLEN/8, x4, x1, x3) + +inst_348: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x7bff; + valaddr_reg:x2; val_offset:638*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 638*FLEN/8, x4, x1, x3) + +inst_349: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xfbff; + valaddr_reg:x2; val_offset:640*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 640*FLEN/8, x4, x1, x3) + +inst_350: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x7c00; + valaddr_reg:x2; val_offset:642*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 642*FLEN/8, x4, x1, x3) + +inst_351: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xfc00; + valaddr_reg:x2; val_offset:644*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 644*FLEN/8, x4, x1, x3) + +inst_352: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x7e00; + valaddr_reg:x2; val_offset:646*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 646*FLEN/8, x4, x1, x3) + +inst_353: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xfe00; + valaddr_reg:x2; val_offset:648*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 648*FLEN/8, x4, x1, x3) + +inst_354: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x7e01; + valaddr_reg:x2; val_offset:650*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 650*FLEN/8, x4, x1, x3) + +inst_355: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xfe55; + valaddr_reg:x2; val_offset:652*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 652*FLEN/8, x4, x1, x3) + +inst_356: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x7c01; + valaddr_reg:x2; val_offset:654*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 654*FLEN/8, x4, x1, x3) + +inst_357: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xfd55; + valaddr_reg:x2; val_offset:656*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 656*FLEN/8, x4, x1, x3) + +inst_358: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x3c00; + valaddr_reg:x2; val_offset:658*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 658*FLEN/8, x4, x1, x3) + +inst_359: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xbc00; + valaddr_reg:x2; val_offset:660*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 660*FLEN/8, x4, x1, x3) + +inst_360: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x0; + valaddr_reg:x2; val_offset:662*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 662*FLEN/8, x4, x1, x3) + +inst_361: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x8000; + valaddr_reg:x2; val_offset:664*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 664*FLEN/8, x4, x1, x3) + +inst_362: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x1; + valaddr_reg:x2; val_offset:666*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 666*FLEN/8, x4, x1, x3) + +inst_363: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x8001; + valaddr_reg:x2; val_offset:668*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 668*FLEN/8, x4, x1, x3) + +inst_364: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x2; + valaddr_reg:x2; val_offset:670*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 670*FLEN/8, x4, x1, x3) + +inst_365: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x83fe; + valaddr_reg:x2; val_offset:672*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 672*FLEN/8, x4, x1, x3) + +inst_366: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x3ff; + valaddr_reg:x2; val_offset:674*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 674*FLEN/8, x4, x1, x3) + +inst_367: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x83ff; + valaddr_reg:x2; val_offset:676*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 676*FLEN/8, x4, x1, x3) + +inst_368: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x400; + valaddr_reg:x2; val_offset:678*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 678*FLEN/8, x4, x1, x3) + +inst_369: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x8400; + valaddr_reg:x2; val_offset:680*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 680*FLEN/8, x4, x1, x3) + +inst_370: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x401; + valaddr_reg:x2; val_offset:682*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 682*FLEN/8, x4, x1, x3) + +inst_371: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x8455; + valaddr_reg:x2; val_offset:684*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 684*FLEN/8, x4, x1, x3) + +inst_372: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x7bff; + valaddr_reg:x2; val_offset:686*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 686*FLEN/8, x4, x1, x3) + +inst_373: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xfbff; + valaddr_reg:x2; val_offset:688*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 688*FLEN/8, x4, x1, x3) + +inst_374: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x7c00; + valaddr_reg:x2; val_offset:690*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 690*FLEN/8, x4, x1, x3) + +inst_375: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xfc00; + valaddr_reg:x2; val_offset:692*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 692*FLEN/8, x4, x1, x3) + +inst_376: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x7e00; + valaddr_reg:x2; val_offset:694*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 694*FLEN/8, x4, x1, x3) + +inst_377: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xfe00; + valaddr_reg:x2; val_offset:696*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 696*FLEN/8, x4, x1, x3) + +inst_378: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x7e01; + valaddr_reg:x2; val_offset:698*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 698*FLEN/8, x4, x1, x3) + +inst_379: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xfe55; + valaddr_reg:x2; val_offset:700*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 700*FLEN/8, x4, x1, x3) + +inst_380: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x7c01; + valaddr_reg:x2; val_offset:702*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 702*FLEN/8, x4, x1, x3) + +inst_381: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xfd55; + valaddr_reg:x2; val_offset:704*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 704*FLEN/8, x4, x1, x3) + +inst_382: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x3c00; + valaddr_reg:x2; val_offset:706*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 706*FLEN/8, x4, x1, x3) + +inst_383: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xbc00; + valaddr_reg:x2; val_offset:708*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 708*FLEN/8, x4, x1, x3) + +inst_384: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x0; + valaddr_reg:x2; val_offset:710*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 710*FLEN/8, x4, x1, x3) + +inst_385: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x8000; + valaddr_reg:x2; val_offset:712*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 712*FLEN/8, x4, x1, x3) + +inst_386: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x1; + valaddr_reg:x2; val_offset:714*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 714*FLEN/8, x4, x1, x3) + +inst_387: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x8001; + valaddr_reg:x2; val_offset:716*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 716*FLEN/8, x4, x1, x3) + +inst_388: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x2; + valaddr_reg:x2; val_offset:718*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 718*FLEN/8, x4, x1, x3) + +inst_389: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x83fe; + valaddr_reg:x2; val_offset:720*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 720*FLEN/8, x4, x1, x3) + +inst_390: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x3ff; + valaddr_reg:x2; val_offset:722*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 722*FLEN/8, x4, x1, x3) + +inst_391: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x83ff; + valaddr_reg:x2; val_offset:724*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 724*FLEN/8, x4, x1, x3) + +inst_392: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x400; + valaddr_reg:x2; val_offset:726*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 726*FLEN/8, x4, x1, x3) + +inst_393: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x8400; + valaddr_reg:x2; val_offset:728*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 728*FLEN/8, x4, x1, x3) + +inst_394: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x401; + valaddr_reg:x2; val_offset:730*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 730*FLEN/8, x4, x1, x3) + +inst_395: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x8455; + valaddr_reg:x2; val_offset:732*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 732*FLEN/8, x4, x1, x3) + +inst_396: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x7bff; + valaddr_reg:x2; val_offset:734*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 734*FLEN/8, x4, x1, x3) + +inst_397: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xfbff; + valaddr_reg:x2; val_offset:736*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 736*FLEN/8, x4, x1, x3) + +inst_398: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x7c00; + valaddr_reg:x2; val_offset:738*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 738*FLEN/8, x4, x1, x3) + +inst_399: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xfc00; + valaddr_reg:x2; val_offset:740*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 740*FLEN/8, x4, x1, x3) + +inst_400: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x7e00; + valaddr_reg:x2; val_offset:742*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 742*FLEN/8, x4, x1, x3) + +inst_401: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xfe00; + valaddr_reg:x2; val_offset:744*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 744*FLEN/8, x4, x1, x3) +RVTEST_SIGBASE(x1,signature_x1_3) + +inst_402: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x7e01; + valaddr_reg:x2; val_offset:746*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 746*FLEN/8, x4, x1, x3) + +inst_403: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xfe55; + valaddr_reg:x2; val_offset:748*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 748*FLEN/8, x4, x1, x3) + +inst_404: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x7c01; + valaddr_reg:x2; val_offset:750*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 750*FLEN/8, x4, x1, x3) + +inst_405: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xfd55; + valaddr_reg:x2; val_offset:752*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 752*FLEN/8, x4, x1, x3) + +inst_406: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x3c00; + valaddr_reg:x2; val_offset:754*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 754*FLEN/8, x4, x1, x3) + +inst_407: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xbc00; + valaddr_reg:x2; val_offset:756*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 756*FLEN/8, x4, x1, x3) + +inst_408: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x0; + valaddr_reg:x2; val_offset:758*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 758*FLEN/8, x4, x1, x3) + +inst_409: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x8000; + valaddr_reg:x2; val_offset:760*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 760*FLEN/8, x4, x1, x3) + +inst_410: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x1; + valaddr_reg:x2; val_offset:762*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 762*FLEN/8, x4, x1, x3) + +inst_411: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x8001; + valaddr_reg:x2; val_offset:764*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 764*FLEN/8, x4, x1, x3) + +inst_412: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x2; + valaddr_reg:x2; val_offset:766*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 766*FLEN/8, x4, x1, x3) + +inst_413: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x83fe; + valaddr_reg:x2; val_offset:768*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 768*FLEN/8, x4, x1, x3) + +inst_414: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x3ff; + valaddr_reg:x2; val_offset:770*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 770*FLEN/8, x4, x1, x3) + +inst_415: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x83ff; + valaddr_reg:x2; val_offset:772*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 772*FLEN/8, x4, x1, x3) + +inst_416: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x400; + valaddr_reg:x2; val_offset:774*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 774*FLEN/8, x4, x1, x3) + +inst_417: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x8400; + valaddr_reg:x2; val_offset:776*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 776*FLEN/8, x4, x1, x3) + +inst_418: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x401; + valaddr_reg:x2; val_offset:778*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 778*FLEN/8, x4, x1, x3) + +inst_419: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x8455; + valaddr_reg:x2; val_offset:780*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 780*FLEN/8, x4, x1, x3) + +inst_420: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x7bff; + valaddr_reg:x2; val_offset:782*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 782*FLEN/8, x4, x1, x3) + +inst_421: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xfbff; + valaddr_reg:x2; val_offset:784*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 784*FLEN/8, x4, x1, x3) + +inst_422: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x7c00; + valaddr_reg:x2; val_offset:786*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 786*FLEN/8, x4, x1, x3) + +inst_423: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xfc00; + valaddr_reg:x2; val_offset:788*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 788*FLEN/8, x4, x1, x3) + +inst_424: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x7e00; + valaddr_reg:x2; val_offset:790*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 790*FLEN/8, x4, x1, x3) + +inst_425: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xfe00; + valaddr_reg:x2; val_offset:792*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 792*FLEN/8, x4, x1, x3) + +inst_426: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x7e01; + valaddr_reg:x2; val_offset:794*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 794*FLEN/8, x4, x1, x3) + +inst_427: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xfe55; + valaddr_reg:x2; val_offset:796*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 796*FLEN/8, x4, x1, x3) + +inst_428: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x7c01; + valaddr_reg:x2; val_offset:798*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 798*FLEN/8, x4, x1, x3) + +inst_429: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xfd55; + valaddr_reg:x2; val_offset:800*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 800*FLEN/8, x4, x1, x3) + +inst_430: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x3c00; + valaddr_reg:x2; val_offset:802*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 802*FLEN/8, x4, x1, x3) + +inst_431: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xbc00; + valaddr_reg:x2; val_offset:804*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 804*FLEN/8, x4, x1, x3) + +inst_432: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x0; + valaddr_reg:x2; val_offset:806*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 806*FLEN/8, x4, x1, x3) + +inst_433: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x8000; + valaddr_reg:x2; val_offset:808*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 808*FLEN/8, x4, x1, x3) + +inst_434: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x1; + valaddr_reg:x2; val_offset:810*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 810*FLEN/8, x4, x1, x3) + +inst_435: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x8001; + valaddr_reg:x2; val_offset:812*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 812*FLEN/8, x4, x1, x3) + +inst_436: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x2; + valaddr_reg:x2; val_offset:814*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 814*FLEN/8, x4, x1, x3) + +inst_437: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x83fe; + valaddr_reg:x2; val_offset:816*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 816*FLEN/8, x4, x1, x3) + +inst_438: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x3ff; + valaddr_reg:x2; val_offset:818*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 818*FLEN/8, x4, x1, x3) + +inst_439: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x83ff; + valaddr_reg:x2; val_offset:820*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 820*FLEN/8, x4, x1, x3) + +inst_440: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x400; + valaddr_reg:x2; val_offset:822*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 822*FLEN/8, x4, x1, x3) + +inst_441: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x8400; + valaddr_reg:x2; val_offset:824*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 824*FLEN/8, x4, x1, x3) + +inst_442: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x401; + valaddr_reg:x2; val_offset:826*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 826*FLEN/8, x4, x1, x3) + +inst_443: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x8455; + valaddr_reg:x2; val_offset:828*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 828*FLEN/8, x4, x1, x3) + +inst_444: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x7bff; + valaddr_reg:x2; val_offset:830*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 830*FLEN/8, x4, x1, x3) + +inst_445: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xfbff; + valaddr_reg:x2; val_offset:832*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 832*FLEN/8, x4, x1, x3) + +inst_446: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x7c00; + valaddr_reg:x2; val_offset:834*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 834*FLEN/8, x4, x1, x3) + +inst_447: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xfc00; + valaddr_reg:x2; val_offset:836*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 836*FLEN/8, x4, x1, x3) + +inst_448: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x7e00; + valaddr_reg:x2; val_offset:838*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 838*FLEN/8, x4, x1, x3) + +inst_449: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xfe00; + valaddr_reg:x2; val_offset:840*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 840*FLEN/8, x4, x1, x3) + +inst_450: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x7e01; + valaddr_reg:x2; val_offset:842*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 842*FLEN/8, x4, x1, x3) + +inst_451: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xfe55; + valaddr_reg:x2; val_offset:844*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 844*FLEN/8, x4, x1, x3) + +inst_452: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x7c01; + valaddr_reg:x2; val_offset:846*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 846*FLEN/8, x4, x1, x3) + +inst_453: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xfd55; + valaddr_reg:x2; val_offset:848*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 848*FLEN/8, x4, x1, x3) + +inst_454: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x3c00; + valaddr_reg:x2; val_offset:850*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 850*FLEN/8, x4, x1, x3) + +inst_455: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xbc00; + valaddr_reg:x2; val_offset:852*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 852*FLEN/8, x4, x1, x3) + +inst_456: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x0; + valaddr_reg:x2; val_offset:854*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 854*FLEN/8, x4, x1, x3) + +inst_457: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x8000; + valaddr_reg:x2; val_offset:856*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 856*FLEN/8, x4, x1, x3) + +inst_458: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x1; + valaddr_reg:x2; val_offset:858*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 858*FLEN/8, x4, x1, x3) + +inst_459: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x8001; + valaddr_reg:x2; val_offset:860*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 860*FLEN/8, x4, x1, x3) + +inst_460: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x2; + valaddr_reg:x2; val_offset:862*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 862*FLEN/8, x4, x1, x3) + +inst_461: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x83fe; + valaddr_reg:x2; val_offset:864*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 864*FLEN/8, x4, x1, x3) + +inst_462: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x3ff; + valaddr_reg:x2; val_offset:866*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 866*FLEN/8, x4, x1, x3) + +inst_463: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x83ff; + valaddr_reg:x2; val_offset:868*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 868*FLEN/8, x4, x1, x3) + +inst_464: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x400; + valaddr_reg:x2; val_offset:870*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 870*FLEN/8, x4, x1, x3) + +inst_465: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x8400; + valaddr_reg:x2; val_offset:872*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 872*FLEN/8, x4, x1, x3) + +inst_466: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x401; + valaddr_reg:x2; val_offset:874*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 874*FLEN/8, x4, x1, x3) + +inst_467: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x8455; + valaddr_reg:x2; val_offset:876*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 876*FLEN/8, x4, x1, x3) + +inst_468: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x7bff; + valaddr_reg:x2; val_offset:878*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 878*FLEN/8, x4, x1, x3) + +inst_469: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xfbff; + valaddr_reg:x2; val_offset:880*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 880*FLEN/8, x4, x1, x3) + +inst_470: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x7c00; + valaddr_reg:x2; val_offset:882*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 882*FLEN/8, x4, x1, x3) + +inst_471: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xfc00; + valaddr_reg:x2; val_offset:884*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 884*FLEN/8, x4, x1, x3) + +inst_472: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x7e00; + valaddr_reg:x2; val_offset:886*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 886*FLEN/8, x4, x1, x3) + +inst_473: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xfe00; + valaddr_reg:x2; val_offset:888*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 888*FLEN/8, x4, x1, x3) + +inst_474: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x7e01; + valaddr_reg:x2; val_offset:890*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 890*FLEN/8, x4, x1, x3) + +inst_475: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xfe55; + valaddr_reg:x2; val_offset:892*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 892*FLEN/8, x4, x1, x3) + +inst_476: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x7c01; + valaddr_reg:x2; val_offset:894*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 894*FLEN/8, x4, x1, x3) + +inst_477: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xfd55; + valaddr_reg:x2; val_offset:896*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 896*FLEN/8, x4, x1, x3) + +inst_478: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x3c00; + valaddr_reg:x2; val_offset:898*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 898*FLEN/8, x4, x1, x3) + +inst_479: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xbc00; + valaddr_reg:x2; val_offset:900*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 900*FLEN/8, x4, x1, x3) + +inst_480: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x0; + valaddr_reg:x2; val_offset:902*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 902*FLEN/8, x4, x1, x3) + +inst_481: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x8000; + valaddr_reg:x2; val_offset:904*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 904*FLEN/8, x4, x1, x3) + +inst_482: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x1; + valaddr_reg:x2; val_offset:906*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 906*FLEN/8, x4, x1, x3) + +inst_483: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x8001; + valaddr_reg:x2; val_offset:908*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 908*FLEN/8, x4, x1, x3) + +inst_484: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x2; + valaddr_reg:x2; val_offset:910*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 910*FLEN/8, x4, x1, x3) + +inst_485: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x83fe; + valaddr_reg:x2; val_offset:912*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 912*FLEN/8, x4, x1, x3) + +inst_486: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x3ff; + valaddr_reg:x2; val_offset:914*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 914*FLEN/8, x4, x1, x3) + +inst_487: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x83ff; + valaddr_reg:x2; val_offset:916*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 916*FLEN/8, x4, x1, x3) + +inst_488: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x400; + valaddr_reg:x2; val_offset:918*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 918*FLEN/8, x4, x1, x3) + +inst_489: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x8400; + valaddr_reg:x2; val_offset:920*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 920*FLEN/8, x4, x1, x3) + +inst_490: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x401; + valaddr_reg:x2; val_offset:922*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 922*FLEN/8, x4, x1, x3) + +inst_491: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x8455; + valaddr_reg:x2; val_offset:924*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 924*FLEN/8, x4, x1, x3) + +inst_492: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x7bff; + valaddr_reg:x2; val_offset:926*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 926*FLEN/8, x4, x1, x3) + +inst_493: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xfbff; + valaddr_reg:x2; val_offset:928*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 928*FLEN/8, x4, x1, x3) + +inst_494: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x7c00; + valaddr_reg:x2; val_offset:930*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 930*FLEN/8, x4, x1, x3) + +inst_495: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xfc00; + valaddr_reg:x2; val_offset:932*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 932*FLEN/8, x4, x1, x3) + +inst_496: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x7e00; + valaddr_reg:x2; val_offset:934*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 934*FLEN/8, x4, x1, x3) + +inst_497: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xfe00; + valaddr_reg:x2; val_offset:936*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 936*FLEN/8, x4, x1, x3) + +inst_498: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x7e01; + valaddr_reg:x2; val_offset:938*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 938*FLEN/8, x4, x1, x3) + +inst_499: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xfe55; + valaddr_reg:x2; val_offset:940*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 940*FLEN/8, x4, x1, x3) + +inst_500: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x7c01; + valaddr_reg:x2; val_offset:942*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 942*FLEN/8, x4, x1, x3) + +inst_501: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xfd55; + valaddr_reg:x2; val_offset:944*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 944*FLEN/8, x4, x1, x3) + +inst_502: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x3c00; + valaddr_reg:x2; val_offset:946*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 946*FLEN/8, x4, x1, x3) + +inst_503: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xbc00; + valaddr_reg:x2; val_offset:948*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 948*FLEN/8, x4, x1, x3) + +inst_504: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x0; + valaddr_reg:x2; val_offset:950*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 950*FLEN/8, x4, x1, x3) + +inst_505: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x8000; + valaddr_reg:x2; val_offset:952*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 952*FLEN/8, x4, x1, x3) + +inst_506: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x1; + valaddr_reg:x2; val_offset:954*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 954*FLEN/8, x4, x1, x3) + +inst_507: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x8001; + valaddr_reg:x2; val_offset:956*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 956*FLEN/8, x4, x1, x3) + +inst_508: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x2; + valaddr_reg:x2; val_offset:958*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 958*FLEN/8, x4, x1, x3) + +inst_509: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x83fe; + valaddr_reg:x2; val_offset:960*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 960*FLEN/8, x4, x1, x3) + +inst_510: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x3ff; + valaddr_reg:x2; val_offset:962*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 962*FLEN/8, x4, x1, x3) + +inst_511: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x83ff; + valaddr_reg:x2; val_offset:964*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 964*FLEN/8, x4, x1, x3) + +inst_512: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x400; + valaddr_reg:x2; val_offset:966*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 966*FLEN/8, x4, x1, x3) + +inst_513: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x8400; + valaddr_reg:x2; val_offset:968*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 968*FLEN/8, x4, x1, x3) + +inst_514: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x401; + valaddr_reg:x2; val_offset:970*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 970*FLEN/8, x4, x1, x3) + +inst_515: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x8455; + valaddr_reg:x2; val_offset:972*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 972*FLEN/8, x4, x1, x3) + +inst_516: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x7bff; + valaddr_reg:x2; val_offset:974*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 974*FLEN/8, x4, x1, x3) + +inst_517: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xfbff; + valaddr_reg:x2; val_offset:976*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 976*FLEN/8, x4, x1, x3) + +inst_518: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x7c00; + valaddr_reg:x2; val_offset:978*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 978*FLEN/8, x4, x1, x3) + +inst_519: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xfc00; + valaddr_reg:x2; val_offset:980*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 980*FLEN/8, x4, x1, x3) + +inst_520: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x7e00; + valaddr_reg:x2; val_offset:982*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 982*FLEN/8, x4, x1, x3) + +inst_521: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xfe00; + valaddr_reg:x2; val_offset:984*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 984*FLEN/8, x4, x1, x3) + +inst_522: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x7e01; + valaddr_reg:x2; val_offset:986*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 986*FLEN/8, x4, x1, x3) + +inst_523: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xfe55; + valaddr_reg:x2; val_offset:988*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 988*FLEN/8, x4, x1, x3) + +inst_524: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x7c01; + valaddr_reg:x2; val_offset:990*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 990*FLEN/8, x4, x1, x3) + +inst_525: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xfd55; + valaddr_reg:x2; val_offset:992*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 992*FLEN/8, x4, x1, x3) + +inst_526: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x3c00; + valaddr_reg:x2; val_offset:994*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 994*FLEN/8, x4, x1, x3) + +inst_527: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xbc00; + valaddr_reg:x2; val_offset:996*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 996*FLEN/8, x4, x1, x3) + +inst_528: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x0; + valaddr_reg:x2; val_offset:998*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 998*FLEN/8, x4, x1, x3) + +inst_529: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x8000; + valaddr_reg:x2; val_offset:1000*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 1000*FLEN/8, x4, x1, x3) +RVTEST_SIGBASE(x1,signature_x1_4) + +inst_530: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x1; + valaddr_reg:x2; val_offset:1002*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 1002*FLEN/8, x4, x1, x3) + +inst_531: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x8001; + valaddr_reg:x2; val_offset:1004*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 1004*FLEN/8, x4, x1, x3) + +inst_532: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2; + valaddr_reg:x2; val_offset:1006*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 1006*FLEN/8, x4, x1, x3) + +inst_533: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x83fe; + valaddr_reg:x2; val_offset:1008*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 1008*FLEN/8, x4, x1, x3) + +inst_534: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3ff; + valaddr_reg:x2; val_offset:1010*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 1010*FLEN/8, x4, x1, x3) + +inst_535: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x83ff; + valaddr_reg:x2; val_offset:1012*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 1012*FLEN/8, x4, x1, x3) + +inst_536: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x400; + valaddr_reg:x2; val_offset:1014*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 1014*FLEN/8, x4, x1, x3) + +inst_537: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x8400; + valaddr_reg:x2; val_offset:1016*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 1016*FLEN/8, x4, x1, x3) + +inst_538: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x401; + valaddr_reg:x2; val_offset:1018*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 1018*FLEN/8, x4, x1, x3) + +inst_539: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x8455; + valaddr_reg:x2; val_offset:1020*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 1020*FLEN/8, x4, x1, x3) + +inst_540: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7bff; + valaddr_reg:x2; val_offset:1022*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 1022*FLEN/8, x4, x1, x3) + +inst_541: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xfbff; + valaddr_reg:x2; val_offset:1024*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 1024*FLEN/8, x4, x1, x3) + +inst_542: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7c00; + valaddr_reg:x2; val_offset:1026*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 1026*FLEN/8, x4, x1, x3) + +inst_543: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xfc00; + valaddr_reg:x2; val_offset:1028*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 1028*FLEN/8, x4, x1, x3) + +inst_544: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7e00; + valaddr_reg:x2; val_offset:1030*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 1030*FLEN/8, x4, x1, x3) + +inst_545: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xfe00; + valaddr_reg:x2; val_offset:1032*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 1032*FLEN/8, x4, x1, x3) + +inst_546: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7e01; + valaddr_reg:x2; val_offset:1034*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 1034*FLEN/8, x4, x1, x3) + +inst_547: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xfe55; + valaddr_reg:x2; val_offset:1036*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 1036*FLEN/8, x4, x1, x3) + +inst_548: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7c01; + valaddr_reg:x2; val_offset:1038*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 1038*FLEN/8, x4, x1, x3) + +inst_549: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xfd55; + valaddr_reg:x2; val_offset:1040*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 1040*FLEN/8, x4, x1, x3) + +inst_550: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3c00; + valaddr_reg:x2; val_offset:1042*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 1042*FLEN/8, x4, x1, x3) + +inst_551: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xbc00; + valaddr_reg:x2; val_offset:1044*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 1044*FLEN/8, x4, x1, x3) + +inst_552: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x0; + valaddr_reg:x2; val_offset:1046*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 1046*FLEN/8, x4, x1, x3) + +inst_553: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x8000; + valaddr_reg:x2; val_offset:1048*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 1048*FLEN/8, x4, x1, x3) + +inst_554: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x1; + valaddr_reg:x2; val_offset:1050*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 1050*FLEN/8, x4, x1, x3) + +inst_555: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x8001; + valaddr_reg:x2; val_offset:1052*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 1052*FLEN/8, x4, x1, x3) + +inst_556: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x2; + valaddr_reg:x2; val_offset:1054*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 1054*FLEN/8, x4, x1, x3) + +inst_557: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x83fe; + valaddr_reg:x2; val_offset:1056*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 1056*FLEN/8, x4, x1, x3) + +inst_558: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x3ff; + valaddr_reg:x2; val_offset:1058*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 1058*FLEN/8, x4, x1, x3) + +inst_559: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x83ff; + valaddr_reg:x2; val_offset:1060*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 1060*FLEN/8, x4, x1, x3) + +inst_560: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x400; + valaddr_reg:x2; val_offset:1062*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 1062*FLEN/8, x4, x1, x3) + +inst_561: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x8400; + valaddr_reg:x2; val_offset:1064*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 1064*FLEN/8, x4, x1, x3) + +inst_562: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x401; + valaddr_reg:x2; val_offset:1066*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 1066*FLEN/8, x4, x1, x3) + +inst_563: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x8455; + valaddr_reg:x2; val_offset:1068*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 1068*FLEN/8, x4, x1, x3) + +inst_564: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x7bff; + valaddr_reg:x2; val_offset:1070*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 1070*FLEN/8, x4, x1, x3) + +inst_565: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xfbff; + valaddr_reg:x2; val_offset:1072*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 1072*FLEN/8, x4, x1, x3) + +inst_566: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x7c00; + valaddr_reg:x2; val_offset:1074*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 1074*FLEN/8, x4, x1, x3) + +inst_567: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xfc00; + valaddr_reg:x2; val_offset:1076*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 1076*FLEN/8, x4, x1, x3) + +inst_568: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x7e00; + valaddr_reg:x2; val_offset:1078*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 1078*FLEN/8, x4, x1, x3) + +inst_569: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xfe00; + valaddr_reg:x2; val_offset:1080*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 1080*FLEN/8, x4, x1, x3) + +inst_570: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x7e01; + valaddr_reg:x2; val_offset:1082*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 1082*FLEN/8, x4, x1, x3) + +inst_571: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xfe55; + valaddr_reg:x2; val_offset:1084*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 1084*FLEN/8, x4, x1, x3) + +inst_572: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x7c01; + valaddr_reg:x2; val_offset:1086*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 1086*FLEN/8, x4, x1, x3) + +inst_573: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xfd55; + valaddr_reg:x2; val_offset:1088*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 1088*FLEN/8, x4, x1, x3) + +inst_574: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x3c00; + valaddr_reg:x2; val_offset:1090*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 1090*FLEN/8, x4, x1, x3) + +inst_575: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbc00; + valaddr_reg:x2; val_offset:1092*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 1092*FLEN/8, x4, x1, x3) + +inst_576: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x8000; + valaddr_reg:x2; val_offset:1094*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 1094*FLEN/8, x4, x1, x3) + +inst_577: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x8001; + valaddr_reg:x2; val_offset:1096*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 1096*FLEN/8, x4, x1, x3) + +inst_578: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xfc00; + valaddr_reg:x2; val_offset:1098*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 1098*FLEN/8, x4, x1, x3) + +inst_579: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xfe55; + valaddr_reg:x2; val_offset:1100*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 1100*FLEN/8, x4, x1, x3) + +inst_580: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x3c00; + valaddr_reg:x2; val_offset:1102*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x2, 1102*FLEN/8, x4, x1, x3) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(1,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(2,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(1023,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(1024,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(1025,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31744,32,FLEN) +test_dataset_1: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32256,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32257,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31745,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(2,32,FLEN) +test_dataset_2: +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(1023,16,FLEN) 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+NAN_BOXED(65024,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(15360,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x6_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x6_1: + .fill 36*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_0: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_2: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_3: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_4: + .fill 102*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fmax_b19-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fmax_b19-01.S new file mode 100644 index 000000000..029239579 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fmax_b19-01.S @@ -0,0 +1,10554 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 05:46:07 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fmax.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fmax.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fmax_b19 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fmax_b19) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x14,test_dataset_0) +RVTEST_SIGBASE(x3,signature_x3_1) + +inst_0: +// rs1 == rd != rs2, rs1==x2, rs2==x13, rd==x2,fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x2; op2:x13; dest:x2; op1val:0x704c; op2val:0x704c; + valaddr_reg:x14; val_offset:0*FLEN/8; fcsr: 0; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP_NRM(fmax.h, x2, x2, x13, 0, 0, x14, 0*FLEN/8, x16, x3, x10) + +inst_1: +// rs1 == rs2 == rd, rs1==x15, rs2==x15, rd==x15,fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3ec and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x15; op2:x15; dest:x15; op1val:0x704c; op2val:0x704c; + valaddr_reg:x14; val_offset:2*FLEN/8; fcsr: 0; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP_NRM(fmax.h, x15, x15, x15, 0, 0, x14, 2*FLEN/8, x16, x3, x10) + +inst_2: +// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==x24, rs2==x21, rd==x17,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1a and fm2 == 0x256 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x24; op2:x21; dest:x17; op1val:0x7bff; op2val:0x6a56; + valaddr_reg:x14; val_offset:4*FLEN/8; fcsr: 0; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP_NRM(fmax.h, x17, x24, x21, 0, 0, x14, 4*FLEN/8, x16, x3, x10) + +inst_3: +// rs1 == rs2 != rd, rs1==x8, rs2==x8, rd==x5,fs1 == 0 and fe1 == 0x1a and fm1 == 0x256 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x8; op2:x8; dest:x5; op1val:0x6a56; op2val:0x6a56; + valaddr_reg:x14; val_offset:6*FLEN/8; fcsr: 0; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP_NRM(fmax.h, x5, x8, x8, 0, 0, x14, 6*FLEN/8, x16, x3, x10) + +inst_4: +// rs2 == rd != rs1, rs1==x0, rs2==x26, rd==x26,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3ec and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x0; op2:x26; dest:x26; op1val:0x0; op2val:0x77ec; + valaddr_reg:x14; val_offset:8*FLEN/8; fcsr: 0; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP_NRM(fmax.h, x26, x0, x26, 0, 0, x14, 8*FLEN/8, x16, x3, x10) + +inst_5: +// rs1==x17, rs2==x6, rd==x4,fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x17; op2:x6; dest:x4; op1val:0x704c; op2val:0x7bff; + valaddr_reg:x14; val_offset:10*FLEN/8; fcsr: 0; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP_NRM(fmax.h, x4, x17, x6, 0, 0, x14, 10*FLEN/8, x16, x3, x10) + +inst_6: +// rs1==x18, rs2==x7, rd==x28,fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x1b and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x18; op2:x7; dest:x28; op1val:0x704c; op2val:0x6e01; + valaddr_reg:x14; val_offset:12*FLEN/8; fcsr: 0; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP_NRM(fmax.h, x28, x18, x7, 0, 0, x14, 12*FLEN/8, x16, x3, x10) + +inst_7: +// rs1==x26, rs2==x25, rd==x9,fs1 == 0 and fe1 == 0x1b and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x26; op2:x25; dest:x9; op1val:0x6e01; op2val:0x704c; + valaddr_reg:x14; val_offset:14*FLEN/8; fcsr: 0; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP_NRM(fmax.h, x9, x26, x25, 0, 0, x14, 14*FLEN/8, x16, x3, x10) + +inst_8: +// rs1==x9, rs2==x19, rd==x30,fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x218 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x9; op2:x19; dest:x30; op1val:0x704c; op2val:0x7a18; + valaddr_reg:x14; val_offset:16*FLEN/8; fcsr: 0; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP_NRM(fmax.h, x30, x9, x19, 0, 0, x14, 16*FLEN/8, x16, x3, x10) + +inst_9: +// rs1==x11, rs2==x12, rd==x19,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0e0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x11; op2:x12; dest:x19; op1val:0x7bff; op2val:0x6ce0; + valaddr_reg:x14; val_offset:18*FLEN/8; fcsr: 0; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP_NRM(fmax.h, x19, x11, x12, 0, 0, x14, 18*FLEN/8, x16, x3, x10) + +inst_10: +// rs1==x30, rs2==x18, rd==x24,fs1 == 0 and fe1 == 0x1b and fm1 == 0x0e0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x18; dest:x24; op1val:0x6ce0; op2val:0x7bff; + valaddr_reg:x14; val_offset:20*FLEN/8; fcsr: 0; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP_NRM(fmax.h, x24, x30, x18, 0, 0, x14, 20*FLEN/8, x16, x3, x10) + +inst_11: +// rs1==x6, rs2==x30, rd==x31,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x218 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x6; op2:x30; dest:x31; op1val:0x7bff; op2val:0x7a18; + valaddr_reg:x14; val_offset:22*FLEN/8; fcsr: 0; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x6, x30, 0, 0, x14, 22*FLEN/8, x16, x3, x10) + +inst_12: +// rs1==x20, rs2==x2, rd==x12,fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x351 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x20; op2:x2; dest:x12; op1val:0x704c; op2val:0x7351; + valaddr_reg:x14; val_offset:24*FLEN/8; fcsr: 0; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP_NRM(fmax.h, x12, x20, x2, 0, 0, x14, 24*FLEN/8, x16, x3, x10) + +inst_13: +// rs1==x22, rs2==x24, rd==x1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x19 and fm2 == 0x1da and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x22; op2:x24; dest:x1; op1val:0x7bff; op2val:0x65da; + valaddr_reg:x14; val_offset:26*FLEN/8; fcsr: 0; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP_NRM(fmax.h, x1, x22, x24, 0, 0, x14, 26*FLEN/8, x16, x3, x10) +RVTEST_VALBASEUPD(x9,test_dataset_1) + +inst_14: +// rs1==x12, rs2==x22, rd==x0,fs1 == 0 and fe1 == 0x19 and fm1 == 0x1da and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x12; op2:x22; dest:x0; op1val:0x65da; op2val:0x7bff; + valaddr_reg:x9; val_offset:0*FLEN/8; fcsr: 0; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP_NRM(fmax.h, x0, x12, x22, 0, 0, x9, 0*FLEN/8, x15, x3, x10) + +inst_15: +// rs1==x31, rs2==x11, rd==x6,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1c and fm2 == 0x351 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x31; op2:x11; dest:x6; op1val:0x7bff; op2val:0x7351; + valaddr_reg:x9; val_offset:2*FLEN/8; fcsr: 0; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP_NRM(fmax.h, x6, x31, x11, 0, 0, x9, 2*FLEN/8, x15, x3, x10) + +inst_16: +// rs1==x13, rs2==x20, rd==x8,fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0e1 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x13; op2:x20; dest:x8; op1val:0x704c; op2val:0xf0e1; + valaddr_reg:x9; val_offset:4*FLEN/8; fcsr: 0; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP_NRM(fmax.h, x8, x13, x20, 0, 0, x9, 4*FLEN/8, x15, x3, x10) + +inst_17: +// rs1==x27, rs2==x28, rd==x14,fs1 == 1 and fe1 == 0x1c and fm1 == 0x0e1 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x27; op2:x28; dest:x14; op1val:0xf0e1; op2val:0x704c; + valaddr_reg:x9; val_offset:6*FLEN/8; fcsr: 0; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP_NRM(fmax.h, x14, x27, x28, 0, 0, x9, 6*FLEN/8, x15, x3, x10) +RVTEST_SIGBASE(x2,signature_x2_0) + +inst_18: +// rs1==x5, rs2==x0, rd==x7,fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x066 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x5; op2:x0; dest:x7; op1val:0x704c; op2val:0x0; + valaddr_reg:x9; val_offset:8*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x7, x5, x0, 0, 0, x9, 8*FLEN/8, x15, x2, x6) + +inst_19: +// rs1==x16, rs2==x5, rd==x10,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1a and fm2 == 0x30b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x16; op2:x5; dest:x10; op1val:0x7bff; op2val:0xeb0b; + valaddr_reg:x9; val_offset:10*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x10, x16, x5, 0, 0, x9, 10*FLEN/8, x15, x2, x6) + +inst_20: +// rs1==x21, rs2==x14, rd==x29,fs1 == 1 and fe1 == 0x1a and fm1 == 0x30b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x21; op2:x14; dest:x29; op1val:0xeb0b; op2val:0x7bff; + valaddr_reg:x9; val_offset:12*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x29, x21, x14, 0, 0, x9, 12*FLEN/8, x15, x2, x6) + +inst_21: +// rs1==x7, rs2==x27, rd==x11,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x066 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x7; op2:x27; dest:x11; op1val:0x7bff; op2val:0xf866; + valaddr_reg:x9; val_offset:14*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x11, x7, x27, 0, 0, x9, 14*FLEN/8, x15, x2, x6) + +inst_22: +// rs1==x29, rs2==x31, rd==x23,fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3c4 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x29; op2:x31; dest:x23; op1val:0x704c; op2val:0xfbc4; + valaddr_reg:x9; val_offset:16*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x23, x29, x31, 0, 0, x9, 16*FLEN/8, x15, x2, x6) + +inst_23: +// rs1==x3, rs2==x10, rd==x21,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1b and fm2 == 0x237 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x3; op2:x10; dest:x21; op1val:0x7bff; op2val:0xee37; + valaddr_reg:x9; val_offset:18*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x21, x3, x10, 0, 0, x9, 18*FLEN/8, x15, x2, x6) + +inst_24: +// rs1==x25, rs2==x3, rd==x20,fs1 == 1 and fe1 == 0x1b and fm1 == 0x237 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x25; op2:x3; dest:x20; op1val:0xee37; op2val:0x7bff; + valaddr_reg:x9; val_offset:20*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x20, x25, x3, 0, 0, x9, 20*FLEN/8, x15, x2, x6) + +inst_25: +// rs1==x10, rs2==x4, rd==x22,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3c4 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x10; op2:x4; dest:x22; op1val:0x7bff; op2val:0xfbc4; + valaddr_reg:x9; val_offset:22*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x22, x10, x4, 0, 0, x9, 22*FLEN/8, x15, x2, x6) + +inst_26: +// rs1==x4, rs2==x1, rd==x25,fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x4; op2:x1; dest:x25; op1val:0x704c; op2val:0xfbfa; + valaddr_reg:x9; val_offset:24*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x25, x4, x1, 0, 0, x9, 24*FLEN/8, x15, x2, x6) + +inst_27: +// rs1==x19, rs2==x23, rd==x27,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1b and fm2 == 0x262 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x19; op2:x23; dest:x27; op1val:0x7bff; op2val:0xee62; + valaddr_reg:x9; val_offset:26*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x27, x19, x23, 0, 0, x9, 26*FLEN/8, x15, x2, x6) + +inst_28: +// rs1==x23, rs2==x17, rd==x16,fs1 == 1 and fe1 == 0x1b and fm1 == 0x262 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x23; op2:x17; dest:x16; op1val:0xee62; op2val:0x7bff; + valaddr_reg:x9; val_offset:28*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x16, x23, x17, 0, 0, x9, 28*FLEN/8, x15, x2, x6) +RVTEST_VALBASEUPD(x4,test_dataset_2) + +inst_29: +// rs1==x1, rs2==x16, rd==x18,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x1; op2:x16; dest:x18; op1val:0x7bff; op2val:0xfbfa; + valaddr_reg:x4; val_offset:0*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x18, x1, x16, 0, 0, x4, 0*FLEN/8, x5, x2, x6) + +inst_30: +// rs1==x28, rs2==x29, rd==x13,fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 1 and fe2 == 0x1a and fm2 == 0x300 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x28; op2:x29; dest:x13; op1val:0x704c; op2val:0xeb00; + valaddr_reg:x4; val_offset:2*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x13, x28, x29, 0, 0, x4, 2*FLEN/8, x5, x2, x6) + +inst_31: +// rs1==x14, rs2==x9, rd==x3,fs1 == 1 and fe1 == 0x1a and fm1 == 0x300 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x14; op2:x9; dest:x3; op1val:0xeb00; op2val:0x704c; + valaddr_reg:x4; val_offset:4*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x3, x14, x9, 0, 0, x4, 4*FLEN/8, x5, x2, x6) + +inst_32: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x704c; op2val:0x30d; + valaddr_reg:x4; val_offset:6*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 6*FLEN/8, x5, x2, x6) + +inst_33: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x1c4 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x08c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x5c4; op2val:0x6c8c; + valaddr_reg:x4; val_offset:8*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 8*FLEN/8, x5, x2, x6) + +inst_34: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x08c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1c4 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c8c; op2val:0x5c4; + valaddr_reg:x4; val_offset:10*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 10*FLEN/8, x5, x2, x6) + +inst_35: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x1c4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x5c4; op2val:0x30d; + valaddr_reg:x4; val_offset:12*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 12*FLEN/8, x5, x2, x6) + +inst_36: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1c4 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x704c; op2val:0x5c4; + valaddr_reg:x4; val_offset:14*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 14*FLEN/8, x5, x2, x6) + +inst_37: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x704c; op2val:0x29a; + valaddr_reg:x4; val_offset:16*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 16*FLEN/8, x5, x2, x6) + +inst_38: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x1c4 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x3c3 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x5c4; op2val:0x6bc3; + valaddr_reg:x4; val_offset:18*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 18*FLEN/8, x5, x2, x6) + +inst_39: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3c3 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1c4 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6bc3; op2val:0x5c4; + valaddr_reg:x4; val_offset:20*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 20*FLEN/8, x5, x2, x6) + +inst_40: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x1c4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x5c4; op2val:0x29a; + valaddr_reg:x4; val_offset:22*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 22*FLEN/8, x5, x2, x6) + +inst_41: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x704c; op2val:0x357; + valaddr_reg:x4; val_offset:24*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 24*FLEN/8, x5, x2, x6) + +inst_42: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x1c4 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x5c4; op2val:0x6cfa; + valaddr_reg:x4; val_offset:26*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 26*FLEN/8, x5, x2, x6) + +inst_43: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0fa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1c4 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6cfa; op2val:0x5c4; + valaddr_reg:x4; val_offset:28*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 28*FLEN/8, x5, x2, x6) + +inst_44: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x1c4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x5c4; op2val:0x357; + valaddr_reg:x4; val_offset:30*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 30*FLEN/8, x5, x2, x6) + +inst_45: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x704c; op2val:0x1c8; + valaddr_reg:x4; val_offset:32*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 32*FLEN/8, x5, x2, x6) + +inst_46: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x1c4 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x14f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x5c4; op2val:0x694f; + valaddr_reg:x4; val_offset:34*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 34*FLEN/8, x5, x2, x6) + +inst_47: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x14f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1c4 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x694f; op2val:0x5c4; + valaddr_reg:x4; val_offset:36*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 36*FLEN/8, x5, x2, x6) + +inst_48: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x1c4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x5c4; op2val:0x1c8; + valaddr_reg:x4; val_offset:38*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 38*FLEN/8, x5, x2, x6) + +inst_49: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x704c; op2val:0x39a; + valaddr_reg:x4; val_offset:40*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 40*FLEN/8, x5, x2, x6) + +inst_50: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x1c4 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x15e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x5c4; op2val:0x6d5e; + valaddr_reg:x4; val_offset:42*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 42*FLEN/8, x5, x2, x6) + +inst_51: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x15e and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1c4 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d5e; op2val:0x5c4; + valaddr_reg:x4; val_offset:44*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 44*FLEN/8, x5, x2, x6) + +inst_52: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x1c4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x5c4; op2val:0x39a; + valaddr_reg:x4; val_offset:46*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 46*FLEN/8, x5, x2, x6) + +inst_53: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x704c; op2val:0x82fa; + valaddr_reg:x4; val_offset:48*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 48*FLEN/8, x5, x2, x6) + +inst_54: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x1c4 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x06f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x5c4; op2val:0xec6f; + valaddr_reg:x4; val_offset:50*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 50*FLEN/8, x5, x2, x6) + +inst_55: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x06f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1c4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xec6f; op2val:0x5c4; + valaddr_reg:x4; val_offset:52*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 52*FLEN/8, x5, x2, x6) + +inst_56: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x1c4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x5c4; op2val:0x82fa; + valaddr_reg:x4; val_offset:54*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 54*FLEN/8, x5, x2, x6) + +inst_57: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x704c; op2val:0x80d8; + valaddr_reg:x4; val_offset:56*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 56*FLEN/8, x5, x2, x6) + +inst_58: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x1c4 and fs2 == 1 and fe2 == 0x19 and fm2 == 0x10d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x5c4; op2val:0xe50d; + valaddr_reg:x4; val_offset:58*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 58*FLEN/8, x5, x2, x6) + +inst_59: +// fs1 == 1 and fe1 == 0x19 and fm1 == 0x10d and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1c4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xe50d; op2val:0x5c4; + valaddr_reg:x4; val_offset:60*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 60*FLEN/8, x5, x2, x6) + +inst_60: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x1c4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x5c4; op2val:0x80d8; + valaddr_reg:x4; val_offset:62*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 62*FLEN/8, x5, x2, x6) + +inst_61: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x704c; op2val:0x8244; + valaddr_reg:x4; val_offset:64*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 64*FLEN/8, x5, x2, x6) + +inst_62: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x1c4 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x2c2 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x5c4; op2val:0xeac2; + valaddr_reg:x4; val_offset:66*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 66*FLEN/8, x5, x2, x6) + +inst_63: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x2c2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1c4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xeac2; op2val:0x5c4; + valaddr_reg:x4; val_offset:68*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 68*FLEN/8, x5, x2, x6) + +inst_64: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x1c4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x5c4; op2val:0x8244; + valaddr_reg:x4; val_offset:70*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 70*FLEN/8, x5, x2, x6) + +inst_65: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x704c; op2val:0x811d; + valaddr_reg:x4; val_offset:72*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 72*FLEN/8, x5, x2, x6) + +inst_66: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x1c4 and fs2 == 1 and fe2 == 0x19 and fm2 == 0x2a6 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x5c4; op2val:0xe6a6; + valaddr_reg:x4; val_offset:74*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 74*FLEN/8, x5, x2, x6) + +inst_67: +// fs1 == 1 and fe1 == 0x19 and fm1 == 0x2a6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1c4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xe6a6; op2val:0x5c4; + valaddr_reg:x4; val_offset:76*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 76*FLEN/8, x5, x2, x6) + +inst_68: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x1c4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x5c4; op2val:0x811d; + valaddr_reg:x4; val_offset:78*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 78*FLEN/8, x5, x2, x6) + +inst_69: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3df and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x704c; op2val:0x83df; + valaddr_reg:x4; val_offset:80*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 80*FLEN/8, x5, x2, x6) + +inst_70: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x1c4 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x1c5 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x5c4; op2val:0xedc5; + valaddr_reg:x4; val_offset:82*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 82*FLEN/8, x5, x2, x6) + +inst_71: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x1c5 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1c4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xedc5; op2val:0x5c4; + valaddr_reg:x4; val_offset:84*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 84*FLEN/8, x5, x2, x6) + +inst_72: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x1c4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3df and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x5c4; op2val:0x83df; + valaddr_reg:x4; val_offset:86*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 86*FLEN/8, x5, x2, x6) + +inst_73: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x704c; op2val:0xf0; + valaddr_reg:x4; val_offset:88*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 88*FLEN/8, x5, x2, x6) + +inst_74: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x066 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x4866; op2val:0xf0; + valaddr_reg:x4; val_offset:90*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 90*FLEN/8, x5, x2, x6) + +inst_75: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x066 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x4866; + valaddr_reg:x4; val_offset:92*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 92*FLEN/8, x5, x2, x6) + +inst_76: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x12 and fm2 == 0x066 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x704c; op2val:0x4866; + valaddr_reg:x4; val_offset:94*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 94*FLEN/8, x5, x2, x6) + +inst_77: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ec and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x77ec; op2val:0x704c; + valaddr_reg:x4; val_offset:96*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 96*FLEN/8, x5, x2, x6) + +inst_78: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x256 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6a56; op2val:0x704c; + valaddr_reg:x4; val_offset:98*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 98*FLEN/8, x5, x2, x6) + +inst_79: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ec and fs2 == 0 and fe2 == 0x1a and fm2 == 0x256 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x77ec; op2val:0x6a56; + valaddr_reg:x4; val_offset:100*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 100*FLEN/8, x5, x2, x6) + +inst_80: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ec and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3ec and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x77ec; op2val:0x77ec; + valaddr_reg:x4; val_offset:102*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 102*FLEN/8, x5, x2, x6) + +inst_81: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ec and fs2 == 0 and fe2 == 0x1b and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x77ec; op2val:0x6e01; + valaddr_reg:x4; val_offset:104*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 104*FLEN/8, x5, x2, x6) + +inst_82: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x256 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x381 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6a56; op2val:0x7b81; + valaddr_reg:x4; val_offset:106*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 106*FLEN/8, x5, x2, x6) + +inst_83: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x381 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x256 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b81; op2val:0x6a56; + valaddr_reg:x4; val_offset:108*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 108*FLEN/8, x5, x2, x6) + +inst_84: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x256 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6a56; op2val:0x6e01; + valaddr_reg:x4; val_offset:110*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 110*FLEN/8, x5, x2, x6) + +inst_85: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ec and fs2 == 0 and fe2 == 0x1e and fm2 == 0x218 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x77ec; op2val:0x7a18; + valaddr_reg:x4; val_offset:112*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 112*FLEN/8, x5, x2, x6) + +inst_86: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x218 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3ec and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a18; op2val:0x77ec; + valaddr_reg:x4; val_offset:114*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 114*FLEN/8, x5, x2, x6) + +inst_87: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ec and fs2 == 0 and fe2 == 0x1c and fm2 == 0x351 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x77ec; op2val:0x7351; + valaddr_reg:x4; val_offset:116*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 116*FLEN/8, x5, x2, x6) + +inst_88: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x351 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3ec and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7351; op2val:0x77ec; + valaddr_reg:x4; val_offset:118*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 118*FLEN/8, x5, x2, x6) + +inst_89: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ec and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0e1 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x77ec; op2val:0xf0e1; + valaddr_reg:x4; val_offset:120*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 120*FLEN/8, x5, x2, x6) + +inst_90: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x256 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6a56; op2val:0xfbff; + valaddr_reg:x4; val_offset:122*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 122*FLEN/8, x5, x2, x6) + +inst_91: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1a and fm2 == 0x256 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x6a56; + valaddr_reg:x4; val_offset:124*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 124*FLEN/8, x5, x2, x6) + +inst_92: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x256 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0e1 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6a56; op2val:0xf0e1; + valaddr_reg:x4; val_offset:126*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 126*FLEN/8, x5, x2, x6) + +inst_93: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ec and fs2 == 1 and fe2 == 0x1e and fm2 == 0x066 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x77ec; op2val:0xf866; + valaddr_reg:x4; val_offset:128*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 128*FLEN/8, x5, x2, x6) + +inst_94: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x066 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3ec and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf866; op2val:0x77ec; + valaddr_reg:x4; val_offset:130*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 130*FLEN/8, x5, x2, x6) + +inst_95: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ec and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3c4 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x77ec; op2val:0xfbc4; + valaddr_reg:x4; val_offset:132*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 132*FLEN/8, x5, x2, x6) + +inst_96: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3c4 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3ec and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbc4; op2val:0x77ec; + valaddr_reg:x4; val_offset:134*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 134*FLEN/8, x5, x2, x6) + +inst_97: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ec and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x77ec; op2val:0xfbfa; + valaddr_reg:x4; val_offset:136*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 136*FLEN/8, x5, x2, x6) + +inst_98: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3fa and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3ec and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbfa; op2val:0x77ec; + valaddr_reg:x4; val_offset:138*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 138*FLEN/8, x5, x2, x6) + +inst_99: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ec and fs2 == 1 and fe2 == 0x1a and fm2 == 0x300 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x77ec; op2val:0xeb00; + valaddr_reg:x4; val_offset:140*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 140*FLEN/8, x5, x2, x6) + +inst_100: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x256 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x060 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6a56; op2val:0xf860; + valaddr_reg:x4; val_offset:142*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 142*FLEN/8, x5, x2, x6) + +inst_101: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x060 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x256 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf860; op2val:0x6a56; + valaddr_reg:x4; val_offset:144*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 144*FLEN/8, x5, x2, x6) + +inst_102: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x256 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x300 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6a56; op2val:0xeb00; + valaddr_reg:x4; val_offset:146*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 146*FLEN/8, x5, x2, x6) + +inst_103: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ec and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x77ec; op2val:0x30d; + valaddr_reg:x4; val_offset:148*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 148*FLEN/8, x5, x2, x6) + +inst_104: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x220 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1af and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x220; op2val:0x79af; + valaddr_reg:x4; val_offset:150*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 150*FLEN/8, x5, x2, x6) + +inst_105: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1af and fs2 == 0 and fe2 == 0x00 and fm2 == 0x220 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x79af; op2val:0x220; + valaddr_reg:x4; val_offset:152*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 152*FLEN/8, x5, x2, x6) + +inst_106: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x220 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x220; op2val:0x30d; + valaddr_reg:x4; val_offset:154*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 154*FLEN/8, x5, x2, x6) + +inst_107: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ec and fs2 == 0 and fe2 == 0x00 and fm2 == 0x220 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x77ec; op2val:0x220; + valaddr_reg:x4; val_offset:156*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 156*FLEN/8, x5, x2, x6) + +inst_108: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ec and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x77ec; op2val:0x29a; + valaddr_reg:x4; val_offset:158*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 158*FLEN/8, x5, x2, x6) + +inst_109: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x220 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0da and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x220; op2val:0x78da; + valaddr_reg:x4; val_offset:160*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 160*FLEN/8, x5, x2, x6) + +inst_110: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0da and fs2 == 0 and fe2 == 0x00 and fm2 == 0x220 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x78da; op2val:0x220; + valaddr_reg:x4; val_offset:162*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 162*FLEN/8, x5, x2, x6) + +inst_111: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x220 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x220; op2val:0x29a; + valaddr_reg:x4; val_offset:164*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 164*FLEN/8, x5, x2, x6) + +inst_112: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ec and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x77ec; op2val:0x357; + valaddr_reg:x4; val_offset:166*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 166*FLEN/8, x5, x2, x6) + +inst_113: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x220 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x238 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x220; op2val:0x7a38; + valaddr_reg:x4; val_offset:168*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 168*FLEN/8, x5, x2, x6) + +inst_114: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x238 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x220 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a38; op2val:0x220; + valaddr_reg:x4; val_offset:170*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 170*FLEN/8, x5, x2, x6) + +inst_115: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x220 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x220; op2val:0x357; + valaddr_reg:x4; val_offset:172*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 172*FLEN/8, x5, x2, x6) + +inst_116: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ec and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x77ec; op2val:0x1c8; + valaddr_reg:x4; val_offset:174*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 174*FLEN/8, x5, x2, x6) + +inst_117: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x220 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2a3 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x220; op2val:0x76a3; + valaddr_reg:x4; val_offset:176*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 176*FLEN/8, x5, x2, x6) + +inst_118: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x220 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x76a3; op2val:0x220; + valaddr_reg:x4; val_offset:178*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 178*FLEN/8, x5, x2, x6) + +inst_119: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x220 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x220; op2val:0x1c8; + valaddr_reg:x4; val_offset:180*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 180*FLEN/8, x5, x2, x6) + +inst_120: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ec and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x77ec; op2val:0x39a; + valaddr_reg:x4; val_offset:182*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 182*FLEN/8, x5, x2, x6) + +inst_121: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x220 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b5 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x220; op2val:0x7ab5; + valaddr_reg:x4; val_offset:184*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 184*FLEN/8, x5, x2, x6) + +inst_122: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x220 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab5; op2val:0x220; + valaddr_reg:x4; val_offset:186*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 186*FLEN/8, x5, x2, x6) + +inst_123: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x220 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x220; op2val:0x39a; + valaddr_reg:x4; val_offset:188*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 188*FLEN/8, x5, x2, x6) + +inst_124: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ec and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x77ec; op2val:0x82fa; + valaddr_reg:x4; val_offset:190*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 190*FLEN/8, x5, x2, x6) + +inst_125: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x220 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x18b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x220; op2val:0xf98b; + valaddr_reg:x4; val_offset:192*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 192*FLEN/8, x5, x2, x6) + +inst_126: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x18b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x220 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf98b; op2val:0x220; + valaddr_reg:x4; val_offset:194*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 194*FLEN/8, x5, x2, x6) + +inst_127: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x220 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x220; op2val:0x82fa; + valaddr_reg:x4; val_offset:196*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 196*FLEN/8, x5, x2, x6) + +inst_128: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ec and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x77ec; op2val:0x80d8; + valaddr_reg:x4; val_offset:198*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 198*FLEN/8, x5, x2, x6) + +inst_129: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x220 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x250 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x220; op2val:0xf250; + valaddr_reg:x4; val_offset:200*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 200*FLEN/8, x5, x2, x6) + +inst_130: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x250 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x220 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf250; op2val:0x220; + valaddr_reg:x4; val_offset:202*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 202*FLEN/8, x5, x2, x6) + +inst_131: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x220 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x220; op2val:0x80d8; + valaddr_reg:x4; val_offset:204*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 204*FLEN/8, x5, x2, x6) + +inst_132: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ec and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x77ec; op2val:0x8244; + valaddr_reg:x4; val_offset:206*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 206*FLEN/8, x5, x2, x6) + +inst_133: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x220 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x039 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x220; op2val:0xf839; + valaddr_reg:x4; val_offset:208*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 208*FLEN/8, x5, x2, x6) + +inst_134: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x039 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x220 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf839; op2val:0x220; + valaddr_reg:x4; val_offset:210*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 210*FLEN/8, x5, x2, x6) + +inst_135: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x220 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x220; op2val:0x8244; + valaddr_reg:x4; val_offset:212*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 212*FLEN/8, x5, x2, x6) + +inst_136: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ec and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x77ec; op2val:0x811d; + valaddr_reg:x4; val_offset:214*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 214*FLEN/8, x5, x2, x6) + +inst_137: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x220 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x027 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x220; op2val:0xf427; + valaddr_reg:x4; val_offset:216*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 216*FLEN/8, x5, x2, x6) + +inst_138: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x027 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x220 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf427; op2val:0x220; + valaddr_reg:x4; val_offset:218*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 218*FLEN/8, x5, x2, x6) + +inst_139: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x220 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x220; op2val:0x811d; + valaddr_reg:x4; val_offset:220*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 220*FLEN/8, x5, x2, x6) + +inst_140: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ec and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3df and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x77ec; op2val:0x83df; + valaddr_reg:x4; val_offset:222*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 222*FLEN/8, x5, x2, x6) + +inst_141: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x220 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x337 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x220; op2val:0xfb37; + valaddr_reg:x4; val_offset:224*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 224*FLEN/8, x5, x2, x6) + +inst_142: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x337 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x220 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb37; op2val:0x220; + valaddr_reg:x4; val_offset:226*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 226*FLEN/8, x5, x2, x6) + +inst_143: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x220 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3df and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x220; op2val:0x83df; + valaddr_reg:x4; val_offset:228*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 228*FLEN/8, x5, x2, x6) + +inst_144: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ec and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x77ec; op2val:0xf0; + valaddr_reg:x4; val_offset:230*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 230*FLEN/8, x5, x2, x6) + +inst_145: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x27d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x427d; op2val:0xf0; + valaddr_reg:x4; val_offset:232*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 232*FLEN/8, x5, x2, x6) +RVTEST_SIGBASE(x2,signature_x2_1) + +inst_146: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x27d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x427d; + valaddr_reg:x4; val_offset:234*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 234*FLEN/8, x5, x2, x6) + +inst_147: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ec and fs2 == 0 and fe2 == 0x10 and fm2 == 0x27d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x77ec; op2val:0x427d; + valaddr_reg:x4; val_offset:236*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 236*FLEN/8, x5, x2, x6) + +inst_148: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e01; op2val:0x6e01; + valaddr_reg:x4; val_offset:238*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 238*FLEN/8, x5, x2, x6) + +inst_149: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3ec and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e01; op2val:0x77ec; + valaddr_reg:x4; val_offset:240*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 240*FLEN/8, x5, x2, x6) + +inst_150: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x381 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3ec and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b81; op2val:0x77ec; + valaddr_reg:x4; val_offset:242*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 242*FLEN/8, x5, x2, x6) + +inst_151: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x381 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e01; op2val:0x7b81; + valaddr_reg:x4; val_offset:244*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 244*FLEN/8, x5, x2, x6) + +inst_152: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x218 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e01; op2val:0x7a18; + valaddr_reg:x4; val_offset:246*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 246*FLEN/8, x5, x2, x6) + +inst_153: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x381 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0e0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b81; op2val:0x6ce0; + valaddr_reg:x4; val_offset:248*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 248*FLEN/8, x5, x2, x6) + +inst_154: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0e0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x381 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ce0; op2val:0x7b81; + valaddr_reg:x4; val_offset:250*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 250*FLEN/8, x5, x2, x6) + +inst_155: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x381 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x218 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b81; op2val:0x7a18; + valaddr_reg:x4; val_offset:252*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 252*FLEN/8, x5, x2, x6) + +inst_156: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x351 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e01; op2val:0x7351; + valaddr_reg:x4; val_offset:254*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 254*FLEN/8, x5, x2, x6) + +inst_157: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x381 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x1da and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b81; op2val:0x65da; + valaddr_reg:x4; val_offset:256*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 256*FLEN/8, x5, x2, x6) + +inst_158: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x1da and fs2 == 0 and fe2 == 0x1e and fm2 == 0x381 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x65da; op2val:0x7b81; + valaddr_reg:x4; val_offset:258*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 258*FLEN/8, x5, x2, x6) + +inst_159: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x381 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x351 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b81; op2val:0x7351; + valaddr_reg:x4; val_offset:260*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 260*FLEN/8, x5, x2, x6) + +inst_160: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0e1 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e01; op2val:0xf0e1; + valaddr_reg:x4; val_offset:262*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 262*FLEN/8, x5, x2, x6) + +inst_161: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x0e1 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0e1; op2val:0x6e01; + valaddr_reg:x4; val_offset:264*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 264*FLEN/8, x5, x2, x6) + +inst_162: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x066 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e01; op2val:0xf866; + valaddr_reg:x4; val_offset:266*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 266*FLEN/8, x5, x2, x6) + +inst_163: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x381 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x30b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b81; op2val:0xeb0b; + valaddr_reg:x4; val_offset:268*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 268*FLEN/8, x5, x2, x6) + +inst_164: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x30b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x381 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xeb0b; op2val:0x7b81; + valaddr_reg:x4; val_offset:270*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 270*FLEN/8, x5, x2, x6) + +inst_165: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x381 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x066 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b81; op2val:0xf866; + valaddr_reg:x4; val_offset:272*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 272*FLEN/8, x5, x2, x6) + +inst_166: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3c4 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e01; op2val:0xfbc4; + valaddr_reg:x4; val_offset:274*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 274*FLEN/8, x5, x2, x6) + +inst_167: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x381 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x237 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b81; op2val:0xee37; + valaddr_reg:x4; val_offset:276*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 276*FLEN/8, x5, x2, x6) + +inst_168: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x237 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x381 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xee37; op2val:0x7b81; + valaddr_reg:x4; val_offset:278*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 278*FLEN/8, x5, x2, x6) + +inst_169: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x381 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3c4 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b81; op2val:0xfbc4; + valaddr_reg:x4; val_offset:280*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 280*FLEN/8, x5, x2, x6) + +inst_170: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e01; op2val:0xfbfa; + valaddr_reg:x4; val_offset:282*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 282*FLEN/8, x5, x2, x6) + +inst_171: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x381 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x262 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b81; op2val:0xee62; + valaddr_reg:x4; val_offset:284*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 284*FLEN/8, x5, x2, x6) + +inst_172: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x262 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x381 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xee62; op2val:0x7b81; + valaddr_reg:x4; val_offset:286*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 286*FLEN/8, x5, x2, x6) + +inst_173: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x381 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b81; op2val:0xfbfa; + valaddr_reg:x4; val_offset:288*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 288*FLEN/8, x5, x2, x6) + +inst_174: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x300 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e01; op2val:0xeb00; + valaddr_reg:x4; val_offset:290*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 290*FLEN/8, x5, x2, x6) + +inst_175: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x300 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xeb00; op2val:0x6e01; + valaddr_reg:x4; val_offset:292*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 292*FLEN/8, x5, x2, x6) + +inst_176: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e01; op2val:0x30d; + valaddr_reg:x4; val_offset:294*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 294*FLEN/8, x5, x2, x6) + +inst_177: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x08c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x407; op2val:0x6c8c; + valaddr_reg:x4; val_offset:296*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 296*FLEN/8, x5, x2, x6) + +inst_178: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x08c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x007 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c8c; op2val:0x407; + valaddr_reg:x4; val_offset:298*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 298*FLEN/8, x5, x2, x6) + +inst_179: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x407; op2val:0x30d; + valaddr_reg:x4; val_offset:300*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 300*FLEN/8, x5, x2, x6) + +inst_180: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x007 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e01; op2val:0x407; + valaddr_reg:x4; val_offset:302*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 302*FLEN/8, x5, x2, x6) + +inst_181: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e01; op2val:0x29a; + valaddr_reg:x4; val_offset:304*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 304*FLEN/8, x5, x2, x6) + +inst_182: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x3c3 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x407; op2val:0x6bc3; + valaddr_reg:x4; val_offset:306*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 306*FLEN/8, x5, x2, x6) + +inst_183: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3c3 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x007 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6bc3; op2val:0x407; + valaddr_reg:x4; val_offset:308*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 308*FLEN/8, x5, x2, x6) + +inst_184: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x407; op2val:0x29a; + valaddr_reg:x4; val_offset:310*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 310*FLEN/8, x5, x2, x6) + +inst_185: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e01; op2val:0x357; + valaddr_reg:x4; val_offset:312*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 312*FLEN/8, x5, x2, x6) + +inst_186: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x407; op2val:0x6cfa; + valaddr_reg:x4; val_offset:314*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 314*FLEN/8, x5, x2, x6) + +inst_187: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0fa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x007 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6cfa; op2val:0x407; + valaddr_reg:x4; val_offset:316*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 316*FLEN/8, x5, x2, x6) + +inst_188: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x407; op2val:0x357; + valaddr_reg:x4; val_offset:318*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 318*FLEN/8, x5, x2, x6) + +inst_189: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e01; op2val:0x1c8; + valaddr_reg:x4; val_offset:320*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 320*FLEN/8, x5, x2, x6) + +inst_190: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x14f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x407; op2val:0x694f; + valaddr_reg:x4; val_offset:322*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 322*FLEN/8, x5, x2, x6) + +inst_191: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x14f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x007 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x694f; op2val:0x407; + valaddr_reg:x4; val_offset:324*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 324*FLEN/8, x5, x2, x6) + +inst_192: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x407; op2val:0x1c8; + valaddr_reg:x4; val_offset:326*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 326*FLEN/8, x5, x2, x6) + +inst_193: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e01; op2val:0x39a; + valaddr_reg:x4; val_offset:328*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 328*FLEN/8, x5, x2, x6) + +inst_194: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x15e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x407; op2val:0x6d5e; + valaddr_reg:x4; val_offset:330*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 330*FLEN/8, x5, x2, x6) + +inst_195: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x15e and fs2 == 0 and fe2 == 0x01 and fm2 == 0x007 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d5e; op2val:0x407; + valaddr_reg:x4; val_offset:332*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 332*FLEN/8, x5, x2, x6) + +inst_196: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x407; op2val:0x39a; + valaddr_reg:x4; val_offset:334*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 334*FLEN/8, x5, x2, x6) + +inst_197: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e01; op2val:0x82fa; + valaddr_reg:x4; val_offset:336*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 336*FLEN/8, x5, x2, x6) + +inst_198: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x06f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x407; op2val:0xec6f; + valaddr_reg:x4; val_offset:338*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 338*FLEN/8, x5, x2, x6) + +inst_199: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x06f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x007 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xec6f; op2val:0x407; + valaddr_reg:x4; val_offset:340*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 340*FLEN/8, x5, x2, x6) + +inst_200: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x407; op2val:0x82fa; + valaddr_reg:x4; val_offset:342*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 342*FLEN/8, x5, x2, x6) + +inst_201: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e01; op2val:0x80d8; + valaddr_reg:x4; val_offset:344*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 344*FLEN/8, x5, x2, x6) + +inst_202: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x19 and fm2 == 0x10d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x407; op2val:0xe50d; + valaddr_reg:x4; val_offset:346*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 346*FLEN/8, x5, x2, x6) + +inst_203: +// fs1 == 1 and fe1 == 0x19 and fm1 == 0x10d and fs2 == 0 and fe2 == 0x01 and fm2 == 0x007 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xe50d; op2val:0x407; + valaddr_reg:x4; val_offset:348*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 348*FLEN/8, x5, x2, x6) + +inst_204: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x407; op2val:0x80d8; + valaddr_reg:x4; val_offset:350*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 350*FLEN/8, x5, x2, x6) + +inst_205: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e01; op2val:0x8244; + valaddr_reg:x4; val_offset:352*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 352*FLEN/8, x5, x2, x6) + +inst_206: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x2c2 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x407; op2val:0xeac2; + valaddr_reg:x4; val_offset:354*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 354*FLEN/8, x5, x2, x6) + +inst_207: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x2c2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x007 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xeac2; op2val:0x407; + valaddr_reg:x4; val_offset:356*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 356*FLEN/8, x5, x2, x6) + +inst_208: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x407; op2val:0x8244; + valaddr_reg:x4; val_offset:358*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 358*FLEN/8, x5, x2, x6) + +inst_209: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e01; op2val:0x811d; + valaddr_reg:x4; val_offset:360*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 360*FLEN/8, x5, x2, x6) + +inst_210: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x19 and fm2 == 0x2a6 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x407; op2val:0xe6a6; + valaddr_reg:x4; val_offset:362*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 362*FLEN/8, x5, x2, x6) + +inst_211: +// fs1 == 1 and fe1 == 0x19 and fm1 == 0x2a6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x007 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xe6a6; op2val:0x407; + valaddr_reg:x4; val_offset:364*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 364*FLEN/8, x5, x2, x6) + +inst_212: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x407; op2val:0x811d; + valaddr_reg:x4; val_offset:366*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 366*FLEN/8, x5, x2, x6) + +inst_213: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3df and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e01; op2val:0x83df; + valaddr_reg:x4; val_offset:368*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 368*FLEN/8, x5, x2, x6) + +inst_214: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x1c5 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x407; op2val:0xedc5; + valaddr_reg:x4; val_offset:370*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 370*FLEN/8, x5, x2, x6) + +inst_215: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x1c5 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x007 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xedc5; op2val:0x407; + valaddr_reg:x4; val_offset:372*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 372*FLEN/8, x5, x2, x6) + +inst_216: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3df and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x407; op2val:0x83df; + valaddr_reg:x4; val_offset:374*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 374*FLEN/8, x5, x2, x6) + +inst_217: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e01; op2val:0xf0; + valaddr_reg:x4; val_offset:376*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 376*FLEN/8, x5, x2, x6) + +inst_218: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x226 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x4626; op2val:0xf0; + valaddr_reg:x4; val_offset:378*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 378*FLEN/8, x5, x2, x6) + +inst_219: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x226 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x4626; + valaddr_reg:x4; val_offset:380*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 380*FLEN/8, x5, x2, x6) + +inst_220: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x201 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x226 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e01; op2val:0x4626; + valaddr_reg:x4; val_offset:382*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 382*FLEN/8, x5, x2, x6) + +inst_221: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x218 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a18; op2val:0x704c; + valaddr_reg:x4; val_offset:384*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 384*FLEN/8, x5, x2, x6) + +inst_222: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0e0 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ce0; op2val:0x704c; + valaddr_reg:x4; val_offset:386*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 386*FLEN/8, x5, x2, x6) + +inst_223: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x218 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0e0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a18; op2val:0x6ce0; + valaddr_reg:x4; val_offset:388*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 388*FLEN/8, x5, x2, x6) + +inst_224: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x218 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x218 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a18; op2val:0x7a18; + valaddr_reg:x4; val_offset:390*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 390*FLEN/8, x5, x2, x6) + +inst_225: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x218 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a18; op2val:0x6e01; + valaddr_reg:x4; val_offset:392*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 392*FLEN/8, x5, x2, x6) + +inst_226: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0e0 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ce0; op2val:0x6e01; + valaddr_reg:x4; val_offset:394*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 394*FLEN/8, x5, x2, x6) + +inst_227: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x218 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x351 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a18; op2val:0x7351; + valaddr_reg:x4; val_offset:396*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 396*FLEN/8, x5, x2, x6) + +inst_228: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x351 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x218 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7351; op2val:0x7a18; + valaddr_reg:x4; val_offset:398*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 398*FLEN/8, x5, x2, x6) + +inst_229: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x218 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0e1 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a18; op2val:0xf0e1; + valaddr_reg:x4; val_offset:400*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 400*FLEN/8, x5, x2, x6) + +inst_230: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0e0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ce0; op2val:0xfbff; + valaddr_reg:x4; val_offset:402*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 402*FLEN/8, x5, x2, x6) + +inst_231: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0e0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x6ce0; + valaddr_reg:x4; val_offset:404*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 404*FLEN/8, x5, x2, x6) + +inst_232: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0e0 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0e1 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ce0; op2val:0xf0e1; + valaddr_reg:x4; val_offset:406*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 406*FLEN/8, x5, x2, x6) + +inst_233: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x218 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x066 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a18; op2val:0xf866; + valaddr_reg:x4; val_offset:408*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 408*FLEN/8, x5, x2, x6) + +inst_234: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x066 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x218 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf866; op2val:0x7a18; + valaddr_reg:x4; val_offset:410*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 410*FLEN/8, x5, x2, x6) + +inst_235: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x218 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3c4 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a18; op2val:0xfbc4; + valaddr_reg:x4; val_offset:412*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 412*FLEN/8, x5, x2, x6) + +inst_236: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3c4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x218 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbc4; op2val:0x7a18; + valaddr_reg:x4; val_offset:414*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 414*FLEN/8, x5, x2, x6) + +inst_237: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x218 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a18; op2val:0xfbfa; + valaddr_reg:x4; val_offset:416*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 416*FLEN/8, x5, x2, x6) + +inst_238: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3fa and fs2 == 0 and fe2 == 0x1e and fm2 == 0x218 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbfa; op2val:0x7a18; + valaddr_reg:x4; val_offset:418*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 418*FLEN/8, x5, x2, x6) + +inst_239: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x218 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x300 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a18; op2val:0xeb00; + valaddr_reg:x4; val_offset:420*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 420*FLEN/8, x5, x2, x6) + +inst_240: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0e0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x060 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ce0; op2val:0xf860; + valaddr_reg:x4; val_offset:422*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 422*FLEN/8, x5, x2, x6) + +inst_241: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x060 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0e0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf860; op2val:0x6ce0; + valaddr_reg:x4; val_offset:424*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 424*FLEN/8, x5, x2, x6) + +inst_242: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0e0 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x300 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ce0; op2val:0xeb00; + valaddr_reg:x4; val_offset:426*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 426*FLEN/8, x5, x2, x6) + +inst_243: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x218 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a18; op2val:0x30d; + valaddr_reg:x4; val_offset:428*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 428*FLEN/8, x5, x2, x6) + +inst_244: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x345 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1af and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x345; op2val:0x79af; + valaddr_reg:x4; val_offset:430*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 430*FLEN/8, x5, x2, x6) + +inst_245: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1af and fs2 == 0 and fe2 == 0x00 and fm2 == 0x345 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x79af; op2val:0x345; + valaddr_reg:x4; val_offset:432*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 432*FLEN/8, x5, x2, x6) + +inst_246: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x345 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x345; op2val:0x30d; + valaddr_reg:x4; val_offset:434*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 434*FLEN/8, x5, x2, x6) + +inst_247: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x218 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x345 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a18; op2val:0x345; + valaddr_reg:x4; val_offset:436*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 436*FLEN/8, x5, x2, x6) + +inst_248: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x218 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a18; op2val:0x29a; + valaddr_reg:x4; val_offset:438*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 438*FLEN/8, x5, x2, x6) + +inst_249: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x345 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0da and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x345; op2val:0x78da; + valaddr_reg:x4; val_offset:440*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 440*FLEN/8, x5, x2, x6) + +inst_250: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0da and fs2 == 0 and fe2 == 0x00 and fm2 == 0x345 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x78da; op2val:0x345; + valaddr_reg:x4; val_offset:442*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 442*FLEN/8, x5, x2, x6) + +inst_251: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x345 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x345; op2val:0x29a; + valaddr_reg:x4; val_offset:444*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 444*FLEN/8, x5, x2, x6) + +inst_252: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x218 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a18; op2val:0x357; + valaddr_reg:x4; val_offset:446*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 446*FLEN/8, x5, x2, x6) + +inst_253: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x345 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x238 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x345; op2val:0x7a38; + valaddr_reg:x4; val_offset:448*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 448*FLEN/8, x5, x2, x6) + +inst_254: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x238 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x345 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a38; op2val:0x345; + valaddr_reg:x4; val_offset:450*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 450*FLEN/8, x5, x2, x6) + +inst_255: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x345 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x345; op2val:0x357; + valaddr_reg:x4; val_offset:452*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 452*FLEN/8, x5, x2, x6) + +inst_256: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x218 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a18; op2val:0x1c8; + valaddr_reg:x4; val_offset:454*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 454*FLEN/8, x5, x2, x6) + +inst_257: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x345 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2a3 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x345; op2val:0x76a3; + valaddr_reg:x4; val_offset:456*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 456*FLEN/8, x5, x2, x6) + +inst_258: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x345 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x76a3; op2val:0x345; + valaddr_reg:x4; val_offset:458*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 458*FLEN/8, x5, x2, x6) + +inst_259: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x345 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x345; op2val:0x1c8; + valaddr_reg:x4; val_offset:460*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 460*FLEN/8, x5, x2, x6) + +inst_260: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x218 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a18; op2val:0x39a; + valaddr_reg:x4; val_offset:462*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 462*FLEN/8, x5, x2, x6) + +inst_261: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x345 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b5 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x345; op2val:0x7ab5; + valaddr_reg:x4; val_offset:464*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 464*FLEN/8, x5, x2, x6) + +inst_262: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x345 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab5; op2val:0x345; + valaddr_reg:x4; val_offset:466*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 466*FLEN/8, x5, x2, x6) + +inst_263: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x345 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x345; op2val:0x39a; + valaddr_reg:x4; val_offset:468*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 468*FLEN/8, x5, x2, x6) + +inst_264: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x218 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a18; op2val:0x82fa; + valaddr_reg:x4; val_offset:470*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 470*FLEN/8, x5, x2, x6) + +inst_265: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x345 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x18b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x345; op2val:0xf98b; + valaddr_reg:x4; val_offset:472*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 472*FLEN/8, x5, x2, x6) + +inst_266: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x18b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x345 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf98b; op2val:0x345; + valaddr_reg:x4; val_offset:474*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 474*FLEN/8, x5, x2, x6) + +inst_267: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x345 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x345; op2val:0x82fa; + valaddr_reg:x4; val_offset:476*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 476*FLEN/8, x5, x2, x6) + +inst_268: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x218 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a18; op2val:0x80d8; + valaddr_reg:x4; val_offset:478*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 478*FLEN/8, x5, x2, x6) + +inst_269: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x345 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x250 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x345; op2val:0xf250; + valaddr_reg:x4; val_offset:480*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 480*FLEN/8, x5, x2, x6) + +inst_270: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x250 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x345 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf250; op2val:0x345; + valaddr_reg:x4; val_offset:482*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 482*FLEN/8, x5, x2, x6) + +inst_271: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x345 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x345; op2val:0x80d8; + valaddr_reg:x4; val_offset:484*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 484*FLEN/8, x5, x2, x6) + +inst_272: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x218 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a18; op2val:0x8244; + valaddr_reg:x4; val_offset:486*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 486*FLEN/8, x5, x2, x6) + +inst_273: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x345 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x039 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x345; op2val:0xf839; + valaddr_reg:x4; val_offset:488*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 488*FLEN/8, x5, x2, x6) +RVTEST_SIGBASE(x2,signature_x2_2) + +inst_274: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x039 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x345 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf839; op2val:0x345; + valaddr_reg:x4; val_offset:490*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 490*FLEN/8, x5, x2, x6) + +inst_275: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x345 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x345; op2val:0x8244; + valaddr_reg:x4; val_offset:492*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 492*FLEN/8, x5, x2, x6) + +inst_276: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x218 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a18; op2val:0x811d; + valaddr_reg:x4; val_offset:494*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 494*FLEN/8, x5, x2, x6) + +inst_277: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x345 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x027 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x345; op2val:0xf427; + valaddr_reg:x4; val_offset:496*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 496*FLEN/8, x5, x2, x6) + +inst_278: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x027 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x345 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf427; op2val:0x345; + valaddr_reg:x4; val_offset:498*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 498*FLEN/8, x5, x2, x6) + +inst_279: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x345 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x345; op2val:0x811d; + valaddr_reg:x4; val_offset:500*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 500*FLEN/8, x5, x2, x6) + +inst_280: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x218 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3df and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a18; op2val:0x83df; + valaddr_reg:x4; val_offset:502*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 502*FLEN/8, x5, x2, x6) + +inst_281: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x345 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x337 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x345; op2val:0xfb37; + valaddr_reg:x4; val_offset:504*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 504*FLEN/8, x5, x2, x6) + +inst_282: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x337 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x345 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb37; op2val:0x345; + valaddr_reg:x4; val_offset:506*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 506*FLEN/8, x5, x2, x6) + +inst_283: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x345 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3df and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x345; op2val:0x83df; + valaddr_reg:x4; val_offset:508*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 508*FLEN/8, x5, x2, x6) + +inst_284: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x218 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a18; op2val:0xf0; + valaddr_reg:x4; val_offset:510*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 510*FLEN/8, x5, x2, x6) + +inst_285: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x0fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x44fe; op2val:0xf0; + valaddr_reg:x4; val_offset:512*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 512*FLEN/8, x5, x2, x6) + +inst_286: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x44fe; + valaddr_reg:x4; val_offset:514*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 514*FLEN/8, x5, x2, x6) + +inst_287: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x218 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a18; op2val:0x44fe; + valaddr_reg:x4; val_offset:516*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 516*FLEN/8, x5, x2, x6) + +inst_288: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x351 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7351; op2val:0x704c; + valaddr_reg:x4; val_offset:518*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 518*FLEN/8, x5, x2, x6) + +inst_289: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x1da and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x65da; op2val:0x704c; + valaddr_reg:x4; val_offset:520*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 520*FLEN/8, x5, x2, x6) + +inst_290: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x351 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x1da and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7351; op2val:0x65da; + valaddr_reg:x4; val_offset:522*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 522*FLEN/8, x5, x2, x6) + +inst_291: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x351 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x351 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7351; op2val:0x7351; + valaddr_reg:x4; val_offset:524*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 524*FLEN/8, x5, x2, x6) + +inst_292: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x351 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7351; op2val:0x6e01; + valaddr_reg:x4; val_offset:526*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 526*FLEN/8, x5, x2, x6) + +inst_293: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x1da and fs2 == 0 and fe2 == 0x1b and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x65da; op2val:0x6e01; + valaddr_reg:x4; val_offset:528*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 528*FLEN/8, x5, x2, x6) + +inst_294: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x351 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0e1 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7351; op2val:0xf0e1; + valaddr_reg:x4; val_offset:530*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 530*FLEN/8, x5, x2, x6) + +inst_295: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x1da and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x65da; op2val:0xfbff; + valaddr_reg:x4; val_offset:532*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 532*FLEN/8, x5, x2, x6) + +inst_296: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x19 and fm2 == 0x1da and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x65da; + valaddr_reg:x4; val_offset:534*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 534*FLEN/8, x5, x2, x6) + +inst_297: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x1da and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0e1 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x65da; op2val:0xf0e1; + valaddr_reg:x4; val_offset:536*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 536*FLEN/8, x5, x2, x6) + +inst_298: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x351 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x066 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7351; op2val:0xf866; + valaddr_reg:x4; val_offset:538*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 538*FLEN/8, x5, x2, x6) + +inst_299: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x066 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x351 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf866; op2val:0x7351; + valaddr_reg:x4; val_offset:540*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 540*FLEN/8, x5, x2, x6) + +inst_300: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x351 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3c4 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7351; op2val:0xfbc4; + valaddr_reg:x4; val_offset:542*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 542*FLEN/8, x5, x2, x6) + +inst_301: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3c4 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x351 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbc4; op2val:0x7351; + valaddr_reg:x4; val_offset:544*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 544*FLEN/8, x5, x2, x6) + +inst_302: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x351 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7351; op2val:0xfbfa; + valaddr_reg:x4; val_offset:546*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 546*FLEN/8, x5, x2, x6) + +inst_303: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3fa and fs2 == 0 and fe2 == 0x1c and fm2 == 0x351 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbfa; op2val:0x7351; + valaddr_reg:x4; val_offset:548*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 548*FLEN/8, x5, x2, x6) + +inst_304: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x351 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x300 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7351; op2val:0xeb00; + valaddr_reg:x4; val_offset:550*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 550*FLEN/8, x5, x2, x6) + +inst_305: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x1da and fs2 == 1 and fe2 == 0x1e and fm2 == 0x060 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x65da; op2val:0xf860; + valaddr_reg:x4; val_offset:552*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 552*FLEN/8, x5, x2, x6) + +inst_306: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x060 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x1da and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf860; op2val:0x65da; + valaddr_reg:x4; val_offset:554*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 554*FLEN/8, x5, x2, x6) + +inst_307: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x1da and fs2 == 1 and fe2 == 0x1a and fm2 == 0x300 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x65da; op2val:0xeb00; + valaddr_reg:x4; val_offset:556*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 556*FLEN/8, x5, x2, x6) + +inst_308: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x351 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7351; op2val:0x30d; + valaddr_reg:x4; val_offset:558*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 558*FLEN/8, x5, x2, x6) + +inst_309: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0fb and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1af and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb; op2val:0x79af; + valaddr_reg:x4; val_offset:560*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 560*FLEN/8, x5, x2, x6) + +inst_310: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1af and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0fb and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x79af; op2val:0xfb; + valaddr_reg:x4; val_offset:562*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 562*FLEN/8, x5, x2, x6) + +inst_311: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0fb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb; op2val:0x30d; + valaddr_reg:x4; val_offset:564*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 564*FLEN/8, x5, x2, x6) + +inst_312: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x351 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0fb and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7351; op2val:0xfb; + valaddr_reg:x4; val_offset:566*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 566*FLEN/8, x5, x2, x6) + +inst_313: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x351 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7351; op2val:0x29a; + valaddr_reg:x4; val_offset:568*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 568*FLEN/8, x5, x2, x6) + +inst_314: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0fb and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0da and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb; op2val:0x78da; + valaddr_reg:x4; val_offset:570*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 570*FLEN/8, x5, x2, x6) + +inst_315: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0da and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0fb and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x78da; op2val:0xfb; + valaddr_reg:x4; val_offset:572*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 572*FLEN/8, x5, x2, x6) + +inst_316: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0fb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb; op2val:0x29a; + valaddr_reg:x4; val_offset:574*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 574*FLEN/8, x5, x2, x6) + +inst_317: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x351 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7351; op2val:0x357; + valaddr_reg:x4; val_offset:576*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 576*FLEN/8, x5, x2, x6) + +inst_318: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0fb and fs2 == 0 and fe2 == 0x1e and fm2 == 0x238 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb; op2val:0x7a38; + valaddr_reg:x4; val_offset:578*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 578*FLEN/8, x5, x2, x6) + +inst_319: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x238 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0fb and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a38; op2val:0xfb; + valaddr_reg:x4; val_offset:580*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 580*FLEN/8, x5, x2, x6) + +inst_320: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0fb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb; op2val:0x357; + valaddr_reg:x4; val_offset:582*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 582*FLEN/8, x5, x2, x6) + +inst_321: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x351 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7351; op2val:0x1c8; + valaddr_reg:x4; val_offset:584*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 584*FLEN/8, x5, x2, x6) + +inst_322: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0fb and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2a3 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb; op2val:0x76a3; + valaddr_reg:x4; val_offset:586*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 586*FLEN/8, x5, x2, x6) + +inst_323: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0fb and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x76a3; op2val:0xfb; + valaddr_reg:x4; val_offset:588*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 588*FLEN/8, x5, x2, x6) + +inst_324: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0fb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb; op2val:0x1c8; + valaddr_reg:x4; val_offset:590*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 590*FLEN/8, x5, x2, x6) + +inst_325: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x351 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7351; op2val:0x39a; + valaddr_reg:x4; val_offset:592*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 592*FLEN/8, x5, x2, x6) + +inst_326: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0fb and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b5 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb; op2val:0x7ab5; + valaddr_reg:x4; val_offset:594*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 594*FLEN/8, x5, x2, x6) + +inst_327: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0fb and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab5; op2val:0xfb; + valaddr_reg:x4; val_offset:596*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 596*FLEN/8, x5, x2, x6) + +inst_328: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0fb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb; op2val:0x39a; + valaddr_reg:x4; val_offset:598*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 598*FLEN/8, x5, x2, x6) + +inst_329: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x351 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7351; op2val:0x82fa; + valaddr_reg:x4; val_offset:600*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 600*FLEN/8, x5, x2, x6) + +inst_330: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x1e and fm2 == 0x18b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb; op2val:0xf98b; + valaddr_reg:x4; val_offset:602*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 602*FLEN/8, x5, x2, x6) + +inst_331: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x18b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0fb and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf98b; op2val:0xfb; + valaddr_reg:x4; val_offset:604*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 604*FLEN/8, x5, x2, x6) + +inst_332: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb; op2val:0x82fa; + valaddr_reg:x4; val_offset:606*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 606*FLEN/8, x5, x2, x6) + +inst_333: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x351 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7351; op2val:0x80d8; + valaddr_reg:x4; val_offset:608*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 608*FLEN/8, x5, x2, x6) + +inst_334: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x1c and fm2 == 0x250 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb; op2val:0xf250; + valaddr_reg:x4; val_offset:610*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 610*FLEN/8, x5, x2, x6) + +inst_335: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x250 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0fb and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf250; op2val:0xfb; + valaddr_reg:x4; val_offset:612*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 612*FLEN/8, x5, x2, x6) + +inst_336: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb; op2val:0x80d8; + valaddr_reg:x4; val_offset:614*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 614*FLEN/8, x5, x2, x6) + +inst_337: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x351 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7351; op2val:0x8244; + valaddr_reg:x4; val_offset:616*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 616*FLEN/8, x5, x2, x6) + +inst_338: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x1e and fm2 == 0x039 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb; op2val:0xf839; + valaddr_reg:x4; val_offset:618*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 618*FLEN/8, x5, x2, x6) + +inst_339: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x039 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0fb and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf839; op2val:0xfb; + valaddr_reg:x4; val_offset:620*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 620*FLEN/8, x5, x2, x6) + +inst_340: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb; op2val:0x8244; + valaddr_reg:x4; val_offset:622*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 622*FLEN/8, x5, x2, x6) + +inst_341: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x351 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7351; op2val:0x811d; + valaddr_reg:x4; val_offset:624*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 624*FLEN/8, x5, x2, x6) + +inst_342: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x1d and fm2 == 0x027 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb; op2val:0xf427; + valaddr_reg:x4; val_offset:626*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 626*FLEN/8, x5, x2, x6) + +inst_343: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x027 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0fb and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf427; op2val:0xfb; + valaddr_reg:x4; val_offset:628*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 628*FLEN/8, x5, x2, x6) + +inst_344: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb; op2val:0x811d; + valaddr_reg:x4; val_offset:630*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 630*FLEN/8, x5, x2, x6) + +inst_345: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x351 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3df and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7351; op2val:0x83df; + valaddr_reg:x4; val_offset:632*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 632*FLEN/8, x5, x2, x6) + +inst_346: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x1e and fm2 == 0x337 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb; op2val:0xfb37; + valaddr_reg:x4; val_offset:634*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 634*FLEN/8, x5, x2, x6) + +inst_347: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x337 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0fb and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb37; op2val:0xfb; + valaddr_reg:x4; val_offset:636*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 636*FLEN/8, x5, x2, x6) + +inst_348: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3df and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb; op2val:0x83df; + valaddr_reg:x4; val_offset:638*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 638*FLEN/8, x5, x2, x6) + +inst_349: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x351 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7351; op2val:0xf0; + valaddr_reg:x4; val_offset:640*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 640*FLEN/8, x5, x2, x6) + +inst_350: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x1fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x3dfe; op2val:0xf0; + valaddr_reg:x4; val_offset:642*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 642*FLEN/8, x5, x2, x6) + +inst_351: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x3dfe; + valaddr_reg:x4; val_offset:644*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 644*FLEN/8, x5, x2, x6) + +inst_352: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x351 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7351; op2val:0x3dfe; + valaddr_reg:x4; val_offset:646*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 646*FLEN/8, x5, x2, x6) + +inst_353: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x0e1 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0e1 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0e1; op2val:0xf0e1; + valaddr_reg:x4; val_offset:648*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 648*FLEN/8, x5, x2, x6) + +inst_354: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x0e1 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3ec and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0e1; op2val:0x77ec; + valaddr_reg:x4; val_offset:650*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 650*FLEN/8, x5, x2, x6) + +inst_355: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3ec and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x77ec; + valaddr_reg:x4; val_offset:652*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 652*FLEN/8, x5, x2, x6) + +inst_356: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x0e1 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0e1; op2val:0xfbff; + valaddr_reg:x4; val_offset:654*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 654*FLEN/8, x5, x2, x6) + +inst_357: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x0e1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x218 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0e1; op2val:0x7a18; + valaddr_reg:x4; val_offset:656*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 656*FLEN/8, x5, x2, x6) + +inst_358: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x218 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7a18; + valaddr_reg:x4; val_offset:658*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 658*FLEN/8, x5, x2, x6) + +inst_359: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x0e1 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x351 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0e1; op2val:0x7351; + valaddr_reg:x4; val_offset:660*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 660*FLEN/8, x5, x2, x6) + +inst_360: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1c and fm2 == 0x351 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7351; + valaddr_reg:x4; val_offset:662*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 662*FLEN/8, x5, x2, x6) + +inst_361: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x0e1 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x066 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0e1; op2val:0xf866; + valaddr_reg:x4; val_offset:664*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 664*FLEN/8, x5, x2, x6) + +inst_362: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1a and fm2 == 0x30b and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xeb0b; + valaddr_reg:x4; val_offset:666*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 666*FLEN/8, x5, x2, x6) + +inst_363: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x30b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xeb0b; op2val:0xfbff; + valaddr_reg:x4; val_offset:668*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 668*FLEN/8, x5, x2, x6) + +inst_364: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x066 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf866; + valaddr_reg:x4; val_offset:670*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 670*FLEN/8, x5, x2, x6) + +inst_365: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x0e1 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3c4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0e1; op2val:0xfbc4; + valaddr_reg:x4; val_offset:672*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 672*FLEN/8, x5, x2, x6) + +inst_366: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1b and fm2 == 0x237 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xee37; + valaddr_reg:x4; val_offset:674*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 674*FLEN/8, x5, x2, x6) + +inst_367: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x237 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xee37; op2val:0xfbff; + valaddr_reg:x4; val_offset:676*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 676*FLEN/8, x5, x2, x6) + +inst_368: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3c4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfbc4; + valaddr_reg:x4; val_offset:678*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 678*FLEN/8, x5, x2, x6) + +inst_369: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x0e1 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0e1; op2val:0xfbfa; + valaddr_reg:x4; val_offset:680*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 680*FLEN/8, x5, x2, x6) + +inst_370: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1b and fm2 == 0x262 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xee62; + valaddr_reg:x4; val_offset:682*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 682*FLEN/8, x5, x2, x6) + +inst_371: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x262 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xee62; op2val:0xfbff; + valaddr_reg:x4; val_offset:684*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 684*FLEN/8, x5, x2, x6) + +inst_372: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfbfa; + valaddr_reg:x4; val_offset:686*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 686*FLEN/8, x5, x2, x6) + +inst_373: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x0e1 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x300 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0e1; op2val:0xeb00; + valaddr_reg:x4; val_offset:688*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 688*FLEN/8, x5, x2, x6) + +inst_374: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x300 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0e1 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xeb00; op2val:0xf0e1; + valaddr_reg:x4; val_offset:690*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 690*FLEN/8, x5, x2, x6) + +inst_375: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x0e1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0e1; op2val:0x30d; + valaddr_reg:x4; val_offset:692*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 692*FLEN/8, x5, x2, x6) + +inst_376: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x28c and fs2 == 0 and fe2 == 0x1b and fm2 == 0x08c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x868c; op2val:0x6c8c; + valaddr_reg:x4; val_offset:694*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 694*FLEN/8, x5, x2, x6) + +inst_377: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x08c and fs2 == 1 and fe2 == 0x01 and fm2 == 0x28c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c8c; op2val:0x868c; + valaddr_reg:x4; val_offset:696*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 696*FLEN/8, x5, x2, x6) + +inst_378: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x28c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x868c; op2val:0x30d; + valaddr_reg:x4; val_offset:698*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 698*FLEN/8, x5, x2, x6) + +inst_379: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x0e1 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x28c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0e1; op2val:0x868c; + valaddr_reg:x4; val_offset:700*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 700*FLEN/8, x5, x2, x6) + +inst_380: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x0e1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0e1; op2val:0x29a; + valaddr_reg:x4; val_offset:702*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 702*FLEN/8, x5, x2, x6) + +inst_381: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x28c and fs2 == 0 and fe2 == 0x1a and fm2 == 0x3c3 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x868c; op2val:0x6bc3; + valaddr_reg:x4; val_offset:704*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 704*FLEN/8, x5, x2, x6) + +inst_382: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3c3 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x28c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6bc3; op2val:0x868c; + valaddr_reg:x4; val_offset:706*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 706*FLEN/8, x5, x2, x6) + +inst_383: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x28c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x868c; op2val:0x29a; + valaddr_reg:x4; val_offset:708*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 708*FLEN/8, x5, x2, x6) + +inst_384: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x0e1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0e1; op2val:0x357; + valaddr_reg:x4; val_offset:710*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 710*FLEN/8, x5, x2, x6) + +inst_385: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x28c and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x868c; op2val:0x6cfa; + valaddr_reg:x4; val_offset:712*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 712*FLEN/8, x5, x2, x6) + +inst_386: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0fa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x28c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6cfa; op2val:0x868c; + valaddr_reg:x4; val_offset:714*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 714*FLEN/8, x5, x2, x6) + +inst_387: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x28c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x868c; op2val:0x357; + valaddr_reg:x4; val_offset:716*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 716*FLEN/8, x5, x2, x6) + +inst_388: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x0e1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0e1; op2val:0x1c8; + valaddr_reg:x4; val_offset:718*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 718*FLEN/8, x5, x2, x6) + +inst_389: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x28c and fs2 == 0 and fe2 == 0x1a and fm2 == 0x14f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x868c; op2val:0x694f; + valaddr_reg:x4; val_offset:720*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 720*FLEN/8, x5, x2, x6) + +inst_390: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x14f and fs2 == 1 and fe2 == 0x01 and fm2 == 0x28c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x694f; op2val:0x868c; + valaddr_reg:x4; val_offset:722*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 722*FLEN/8, x5, x2, x6) + +inst_391: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x28c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x868c; op2val:0x1c8; + valaddr_reg:x4; val_offset:724*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 724*FLEN/8, x5, x2, x6) + +inst_392: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x0e1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0e1; op2val:0x39a; + valaddr_reg:x4; val_offset:726*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 726*FLEN/8, x5, x2, x6) + +inst_393: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x28c and fs2 == 0 and fe2 == 0x1b and fm2 == 0x15e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x868c; op2val:0x6d5e; + valaddr_reg:x4; val_offset:728*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 728*FLEN/8, x5, x2, x6) + +inst_394: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x15e and fs2 == 1 and fe2 == 0x01 and fm2 == 0x28c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d5e; op2val:0x868c; + valaddr_reg:x4; val_offset:730*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 730*FLEN/8, x5, x2, x6) + +inst_395: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x28c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x868c; op2val:0x39a; + valaddr_reg:x4; val_offset:732*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 732*FLEN/8, x5, x2, x6) + +inst_396: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x0e1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0e1; op2val:0x82fa; + valaddr_reg:x4; val_offset:734*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 734*FLEN/8, x5, x2, x6) + +inst_397: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x28c and fs2 == 1 and fe2 == 0x1b and fm2 == 0x06f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x868c; op2val:0xec6f; + valaddr_reg:x4; val_offset:736*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 736*FLEN/8, x5, x2, x6) + +inst_398: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x06f and fs2 == 1 and fe2 == 0x01 and fm2 == 0x28c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xec6f; op2val:0x868c; + valaddr_reg:x4; val_offset:738*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 738*FLEN/8, x5, x2, x6) + +inst_399: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x28c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x868c; op2val:0x82fa; + valaddr_reg:x4; val_offset:740*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 740*FLEN/8, x5, x2, x6) + +inst_400: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x0e1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d8 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0e1; op2val:0x80d8; + valaddr_reg:x4; val_offset:742*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 742*FLEN/8, x5, x2, x6) + +inst_401: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x28c and fs2 == 1 and fe2 == 0x19 and fm2 == 0x10d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x868c; op2val:0xe50d; + valaddr_reg:x4; val_offset:744*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 744*FLEN/8, x5, x2, x6) +RVTEST_SIGBASE(x2,signature_x2_3) + +inst_402: +// fs1 == 1 and fe1 == 0x19 and fm1 == 0x10d and fs2 == 1 and fe2 == 0x01 and fm2 == 0x28c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xe50d; op2val:0x868c; + valaddr_reg:x4; val_offset:746*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 746*FLEN/8, x5, x2, x6) + +inst_403: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x28c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d8 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x868c; op2val:0x80d8; + valaddr_reg:x4; val_offset:748*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 748*FLEN/8, x5, x2, x6) + +inst_404: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x0e1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0e1; op2val:0x8244; + valaddr_reg:x4; val_offset:750*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 750*FLEN/8, x5, x2, x6) + +inst_405: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x28c and fs2 == 1 and fe2 == 0x1a and fm2 == 0x2c2 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x868c; op2val:0xeac2; + valaddr_reg:x4; val_offset:752*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 752*FLEN/8, x5, x2, x6) + +inst_406: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x2c2 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x28c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xeac2; op2val:0x868c; + valaddr_reg:x4; val_offset:754*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 754*FLEN/8, x5, x2, x6) + +inst_407: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x28c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x868c; op2val:0x8244; + valaddr_reg:x4; val_offset:756*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 756*FLEN/8, x5, x2, x6) + +inst_408: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x0e1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0e1; op2val:0x811d; + valaddr_reg:x4; val_offset:758*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 758*FLEN/8, x5, x2, x6) + +inst_409: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x28c and fs2 == 1 and fe2 == 0x19 and fm2 == 0x2a6 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x868c; op2val:0xe6a6; + valaddr_reg:x4; val_offset:760*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 760*FLEN/8, x5, x2, x6) + +inst_410: +// fs1 == 1 and fe1 == 0x19 and fm1 == 0x2a6 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x28c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xe6a6; op2val:0x868c; + valaddr_reg:x4; val_offset:762*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 762*FLEN/8, x5, x2, x6) + +inst_411: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x28c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x868c; op2val:0x811d; + valaddr_reg:x4; val_offset:764*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 764*FLEN/8, x5, x2, x6) + +inst_412: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x0e1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3df and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0e1; op2val:0x83df; + valaddr_reg:x4; val_offset:766*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 766*FLEN/8, x5, x2, x6) + +inst_413: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x28c and fs2 == 1 and fe2 == 0x1b and fm2 == 0x1c5 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x868c; op2val:0xedc5; + valaddr_reg:x4; val_offset:768*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 768*FLEN/8, x5, x2, x6) + +inst_414: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x1c5 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x28c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xedc5; op2val:0x868c; + valaddr_reg:x4; val_offset:770*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 770*FLEN/8, x5, x2, x6) + +inst_415: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x28c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3df and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x868c; op2val:0x83df; + valaddr_reg:x4; val_offset:772*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 772*FLEN/8, x5, x2, x6) + +inst_416: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x0e1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0e1; op2val:0xf0; + valaddr_reg:x4; val_offset:774*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 774*FLEN/8, x5, x2, x6) + +inst_417: +// fs1 == 1 and fe1 == 0x12 and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xc8ff; op2val:0xf0; + valaddr_reg:x4; val_offset:776*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 776*FLEN/8, x5, x2, x6) + +inst_418: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xc8ff; + valaddr_reg:x4; val_offset:778*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 778*FLEN/8, x5, x2, x6) + +inst_419: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x0e1 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0e1; op2val:0xc8ff; + valaddr_reg:x4; val_offset:780*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 780*FLEN/8, x5, x2, x6) + +inst_420: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x066 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf866; op2val:0x704c; + valaddr_reg:x4; val_offset:782*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 782*FLEN/8, x5, x2, x6) + +inst_421: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x30b and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xeb0b; op2val:0x704c; + valaddr_reg:x4; val_offset:784*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 784*FLEN/8, x5, x2, x6) + +inst_422: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x066 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x30b and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf866; op2val:0xeb0b; + valaddr_reg:x4; val_offset:786*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 786*FLEN/8, x5, x2, x6) + +inst_423: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x066 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x066 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf866; op2val:0xf866; + valaddr_reg:x4; val_offset:788*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 788*FLEN/8, x5, x2, x6) + +inst_424: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x066 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf866; op2val:0x6e01; + valaddr_reg:x4; val_offset:790*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 790*FLEN/8, x5, x2, x6) + +inst_425: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x30b and fs2 == 0 and fe2 == 0x1b and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xeb0b; op2val:0x6e01; + valaddr_reg:x4; val_offset:792*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 792*FLEN/8, x5, x2, x6) + +inst_426: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x066 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0e1 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf866; op2val:0xf0e1; + valaddr_reg:x4; val_offset:794*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 794*FLEN/8, x5, x2, x6) + +inst_427: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x30b and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0e1 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xeb0b; op2val:0xf0e1; + valaddr_reg:x4; val_offset:796*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 796*FLEN/8, x5, x2, x6) + +inst_428: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x066 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3c4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf866; op2val:0xfbc4; + valaddr_reg:x4; val_offset:798*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 798*FLEN/8, x5, x2, x6) + +inst_429: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3c4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x066 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbc4; op2val:0xf866; + valaddr_reg:x4; val_offset:800*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 800*FLEN/8, x5, x2, x6) + +inst_430: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x066 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf866; op2val:0xfbfa; + valaddr_reg:x4; val_offset:802*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 802*FLEN/8, x5, x2, x6) + +inst_431: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3fa and fs2 == 1 and fe2 == 0x1e and fm2 == 0x066 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbfa; op2val:0xf866; + valaddr_reg:x4; val_offset:804*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 804*FLEN/8, x5, x2, x6) + +inst_432: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x066 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x300 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf866; op2val:0xeb00; + valaddr_reg:x4; val_offset:806*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 806*FLEN/8, x5, x2, x6) + +inst_433: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x30b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x060 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xeb0b; op2val:0xf860; + valaddr_reg:x4; val_offset:808*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 808*FLEN/8, x5, x2, x6) + +inst_434: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x060 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x30b and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf860; op2val:0xeb0b; + valaddr_reg:x4; val_offset:810*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 810*FLEN/8, x5, x2, x6) + +inst_435: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x30b and fs2 == 1 and fe2 == 0x1a and fm2 == 0x300 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xeb0b; op2val:0xeb00; + valaddr_reg:x4; val_offset:812*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 812*FLEN/8, x5, x2, x6) + +inst_436: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x066 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf866; op2val:0x30d; + valaddr_reg:x4; val_offset:814*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 814*FLEN/8, x5, x2, x6) + +inst_437: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x25d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1af and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x825d; op2val:0x79af; + valaddr_reg:x4; val_offset:816*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 816*FLEN/8, x5, x2, x6) + +inst_438: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1af and fs2 == 1 and fe2 == 0x00 and fm2 == 0x25d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x79af; op2val:0x825d; + valaddr_reg:x4; val_offset:818*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 818*FLEN/8, x5, x2, x6) + +inst_439: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x25d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x825d; op2val:0x30d; + valaddr_reg:x4; val_offset:820*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 820*FLEN/8, x5, x2, x6) + +inst_440: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x066 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x25d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf866; op2val:0x825d; + valaddr_reg:x4; val_offset:822*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 822*FLEN/8, x5, x2, x6) + +inst_441: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x066 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf866; op2val:0x29a; + valaddr_reg:x4; val_offset:824*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 824*FLEN/8, x5, x2, x6) + +inst_442: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x25d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0da and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x825d; op2val:0x78da; + valaddr_reg:x4; val_offset:826*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 826*FLEN/8, x5, x2, x6) + +inst_443: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0da and fs2 == 1 and fe2 == 0x00 and fm2 == 0x25d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x78da; op2val:0x825d; + valaddr_reg:x4; val_offset:828*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 828*FLEN/8, x5, x2, x6) + +inst_444: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x25d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x825d; op2val:0x29a; + valaddr_reg:x4; val_offset:830*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 830*FLEN/8, x5, x2, x6) + +inst_445: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x066 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf866; op2val:0x357; + valaddr_reg:x4; val_offset:832*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 832*FLEN/8, x5, x2, x6) + +inst_446: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x25d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x238 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x825d; op2val:0x7a38; + valaddr_reg:x4; val_offset:834*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 834*FLEN/8, x5, x2, x6) + +inst_447: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x238 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x25d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a38; op2val:0x825d; + valaddr_reg:x4; val_offset:836*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 836*FLEN/8, x5, x2, x6) + +inst_448: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x25d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x825d; op2val:0x357; + valaddr_reg:x4; val_offset:838*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 838*FLEN/8, x5, x2, x6) + +inst_449: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x066 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf866; op2val:0x1c8; + valaddr_reg:x4; val_offset:840*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 840*FLEN/8, x5, x2, x6) + +inst_450: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x25d and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2a3 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x825d; op2val:0x76a3; + valaddr_reg:x4; val_offset:842*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 842*FLEN/8, x5, x2, x6) + +inst_451: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x25d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x76a3; op2val:0x825d; + valaddr_reg:x4; val_offset:844*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 844*FLEN/8, x5, x2, x6) + +inst_452: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x25d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x825d; op2val:0x1c8; + valaddr_reg:x4; val_offset:846*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 846*FLEN/8, x5, x2, x6) + +inst_453: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x066 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf866; op2val:0x39a; + valaddr_reg:x4; val_offset:848*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 848*FLEN/8, x5, x2, x6) + +inst_454: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x25d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b5 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x825d; op2val:0x7ab5; + valaddr_reg:x4; val_offset:850*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 850*FLEN/8, x5, x2, x6) + +inst_455: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x25d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab5; op2val:0x825d; + valaddr_reg:x4; val_offset:852*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 852*FLEN/8, x5, x2, x6) + +inst_456: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x25d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x825d; op2val:0x39a; + valaddr_reg:x4; val_offset:854*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 854*FLEN/8, x5, x2, x6) + +inst_457: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x066 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf866; op2val:0x82fa; + valaddr_reg:x4; val_offset:856*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 856*FLEN/8, x5, x2, x6) + +inst_458: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x25d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x18b and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x825d; op2val:0xf98b; + valaddr_reg:x4; val_offset:858*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 858*FLEN/8, x5, x2, x6) + +inst_459: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x18b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x25d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf98b; op2val:0x825d; + valaddr_reg:x4; val_offset:860*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 860*FLEN/8, x5, x2, x6) + +inst_460: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x25d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x825d; op2val:0x82fa; + valaddr_reg:x4; val_offset:862*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 862*FLEN/8, x5, x2, x6) + +inst_461: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x066 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d8 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf866; op2val:0x80d8; + valaddr_reg:x4; val_offset:864*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 864*FLEN/8, x5, x2, x6) + +inst_462: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x25d and fs2 == 1 and fe2 == 0x1c and fm2 == 0x250 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x825d; op2val:0xf250; + valaddr_reg:x4; val_offset:866*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 866*FLEN/8, x5, x2, x6) + +inst_463: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x250 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x25d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf250; op2val:0x825d; + valaddr_reg:x4; val_offset:868*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 868*FLEN/8, x5, x2, x6) + +inst_464: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x25d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d8 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x825d; op2val:0x80d8; + valaddr_reg:x4; val_offset:870*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 870*FLEN/8, x5, x2, x6) + +inst_465: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x066 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf866; op2val:0x8244; + valaddr_reg:x4; val_offset:872*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 872*FLEN/8, x5, x2, x6) + +inst_466: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x25d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x039 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x825d; op2val:0xf839; + valaddr_reg:x4; val_offset:874*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 874*FLEN/8, x5, x2, x6) + +inst_467: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x039 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x25d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf839; op2val:0x825d; + valaddr_reg:x4; val_offset:876*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 876*FLEN/8, x5, x2, x6) + +inst_468: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x25d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x825d; op2val:0x8244; + valaddr_reg:x4; val_offset:878*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 878*FLEN/8, x5, x2, x6) + +inst_469: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x066 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf866; op2val:0x811d; + valaddr_reg:x4; val_offset:880*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 880*FLEN/8, x5, x2, x6) + +inst_470: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x25d and fs2 == 1 and fe2 == 0x1d and fm2 == 0x027 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x825d; op2val:0xf427; + valaddr_reg:x4; val_offset:882*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 882*FLEN/8, x5, x2, x6) + +inst_471: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x027 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x25d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf427; op2val:0x825d; + valaddr_reg:x4; val_offset:884*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 884*FLEN/8, x5, x2, x6) + +inst_472: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x25d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x825d; op2val:0x811d; + valaddr_reg:x4; val_offset:886*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 886*FLEN/8, x5, x2, x6) + +inst_473: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x066 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3df and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf866; op2val:0x83df; + valaddr_reg:x4; val_offset:888*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 888*FLEN/8, x5, x2, x6) + +inst_474: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x25d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x337 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x825d; op2val:0xfb37; + valaddr_reg:x4; val_offset:890*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 890*FLEN/8, x5, x2, x6) + +inst_475: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x337 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x25d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb37; op2val:0x825d; + valaddr_reg:x4; val_offset:892*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 892*FLEN/8, x5, x2, x6) + +inst_476: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x25d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3df and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x825d; op2val:0x83df; + valaddr_reg:x4; val_offset:894*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 894*FLEN/8, x5, x2, x6) + +inst_477: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x066 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf866; op2val:0xf0; + valaddr_reg:x4; val_offset:896*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 896*FLEN/8, x5, x2, x6) + +inst_478: +// fs1 == 1 and fe1 == 0x10 and fm1 == 0x336 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xc336; op2val:0xf0; + valaddr_reg:x4; val_offset:898*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 898*FLEN/8, x5, x2, x6) + +inst_479: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x336 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xc336; + valaddr_reg:x4; val_offset:900*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 900*FLEN/8, x5, x2, x6) + +inst_480: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x066 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x336 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf866; op2val:0xc336; + valaddr_reg:x4; val_offset:902*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 902*FLEN/8, x5, x2, x6) + +inst_481: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3c4 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbc4; op2val:0x704c; + valaddr_reg:x4; val_offset:904*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 904*FLEN/8, x5, x2, x6) + +inst_482: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x237 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xee37; op2val:0x704c; + valaddr_reg:x4; val_offset:906*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 906*FLEN/8, x5, x2, x6) + +inst_483: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3c4 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x237 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbc4; op2val:0xee37; + valaddr_reg:x4; val_offset:908*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 908*FLEN/8, x5, x2, x6) + +inst_484: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3c4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3c4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbc4; op2val:0xfbc4; + valaddr_reg:x4; val_offset:910*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 910*FLEN/8, x5, x2, x6) + +inst_485: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3c4 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbc4; op2val:0x6e01; + valaddr_reg:x4; val_offset:912*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 912*FLEN/8, x5, x2, x6) + +inst_486: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x237 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xee37; op2val:0x6e01; + valaddr_reg:x4; val_offset:914*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 914*FLEN/8, x5, x2, x6) + +inst_487: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3c4 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0e1 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbc4; op2val:0xf0e1; + valaddr_reg:x4; val_offset:916*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 916*FLEN/8, x5, x2, x6) + +inst_488: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x237 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0e1 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xee37; op2val:0xf0e1; + valaddr_reg:x4; val_offset:918*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 918*FLEN/8, x5, x2, x6) + +inst_489: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3c4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbc4; op2val:0xfbfa; + valaddr_reg:x4; val_offset:920*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 920*FLEN/8, x5, x2, x6) + +inst_490: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3fa and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3c4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbfa; op2val:0xfbc4; + valaddr_reg:x4; val_offset:922*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 922*FLEN/8, x5, x2, x6) + +inst_491: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3c4 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x300 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbc4; op2val:0xeb00; + valaddr_reg:x4; val_offset:924*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 924*FLEN/8, x5, x2, x6) + +inst_492: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x237 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x060 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xee37; op2val:0xf860; + valaddr_reg:x4; val_offset:926*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 926*FLEN/8, x5, x2, x6) + +inst_493: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x060 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x237 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf860; op2val:0xee37; + valaddr_reg:x4; val_offset:928*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 928*FLEN/8, x5, x2, x6) + +inst_494: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x237 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x300 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xee37; op2val:0xeb00; + valaddr_reg:x4; val_offset:930*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 930*FLEN/8, x5, x2, x6) + +inst_495: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3c4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbc4; op2val:0x30d; + valaddr_reg:x4; val_offset:932*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 932*FLEN/8, x5, x2, x6) + +inst_496: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x02b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1af and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x842b; op2val:0x79af; + valaddr_reg:x4; val_offset:934*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 934*FLEN/8, x5, x2, x6) + +inst_497: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1af and fs2 == 1 and fe2 == 0x01 and fm2 == 0x02b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x79af; op2val:0x842b; + valaddr_reg:x4; val_offset:936*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 936*FLEN/8, x5, x2, x6) + +inst_498: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x02b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x842b; op2val:0x30d; + valaddr_reg:x4; val_offset:938*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 938*FLEN/8, x5, x2, x6) + +inst_499: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3c4 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x02b and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbc4; op2val:0x842b; + valaddr_reg:x4; val_offset:940*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 940*FLEN/8, x5, x2, x6) + +inst_500: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3c4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbc4; op2val:0x29a; + valaddr_reg:x4; val_offset:942*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 942*FLEN/8, x5, x2, x6) + +inst_501: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x02b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0da and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x842b; op2val:0x78da; + valaddr_reg:x4; val_offset:944*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 944*FLEN/8, x5, x2, x6) + +inst_502: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0da and fs2 == 1 and fe2 == 0x01 and fm2 == 0x02b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x78da; op2val:0x842b; + valaddr_reg:x4; val_offset:946*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 946*FLEN/8, x5, x2, x6) + +inst_503: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x02b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x842b; op2val:0x29a; + valaddr_reg:x4; val_offset:948*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 948*FLEN/8, x5, x2, x6) + +inst_504: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3c4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbc4; op2val:0x357; + valaddr_reg:x4; val_offset:950*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 950*FLEN/8, x5, x2, x6) + +inst_505: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x02b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x238 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x842b; op2val:0x7a38; + valaddr_reg:x4; val_offset:952*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 952*FLEN/8, x5, x2, x6) + +inst_506: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x238 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x02b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a38; op2val:0x842b; + valaddr_reg:x4; val_offset:954*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 954*FLEN/8, x5, x2, x6) + +inst_507: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x02b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x842b; op2val:0x357; + valaddr_reg:x4; val_offset:956*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 956*FLEN/8, x5, x2, x6) + +inst_508: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3c4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbc4; op2val:0x1c8; + valaddr_reg:x4; val_offset:958*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 958*FLEN/8, x5, x2, x6) + +inst_509: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x02b and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2a3 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x842b; op2val:0x76a3; + valaddr_reg:x4; val_offset:960*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 960*FLEN/8, x5, x2, x6) + +inst_510: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a3 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x02b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x76a3; op2val:0x842b; + valaddr_reg:x4; val_offset:962*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 962*FLEN/8, x5, x2, x6) + +inst_511: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x02b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x842b; op2val:0x1c8; + valaddr_reg:x4; val_offset:964*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 964*FLEN/8, x5, x2, x6) + +inst_512: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3c4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbc4; op2val:0x39a; + valaddr_reg:x4; val_offset:966*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 966*FLEN/8, x5, x2, x6) + +inst_513: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x02b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b5 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x842b; op2val:0x7ab5; + valaddr_reg:x4; val_offset:968*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 968*FLEN/8, x5, x2, x6) + +inst_514: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b5 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x02b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab5; op2val:0x842b; + valaddr_reg:x4; val_offset:970*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 970*FLEN/8, x5, x2, x6) + +inst_515: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x02b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x842b; op2val:0x39a; + valaddr_reg:x4; val_offset:972*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 972*FLEN/8, x5, x2, x6) + +inst_516: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3c4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbc4; op2val:0x82fa; + valaddr_reg:x4; val_offset:974*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 974*FLEN/8, x5, x2, x6) + +inst_517: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x02b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x18b and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x842b; op2val:0xf98b; + valaddr_reg:x4; val_offset:976*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 976*FLEN/8, x5, x2, x6) + +inst_518: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x18b and fs2 == 1 and fe2 == 0x01 and fm2 == 0x02b and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf98b; op2val:0x842b; + valaddr_reg:x4; val_offset:978*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 978*FLEN/8, x5, x2, x6) + +inst_519: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x02b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x842b; op2val:0x82fa; + valaddr_reg:x4; val_offset:980*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 980*FLEN/8, x5, x2, x6) + +inst_520: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3c4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d8 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbc4; op2val:0x80d8; + valaddr_reg:x4; val_offset:982*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 982*FLEN/8, x5, x2, x6) + +inst_521: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x02b and fs2 == 1 and fe2 == 0x1c and fm2 == 0x250 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x842b; op2val:0xf250; + valaddr_reg:x4; val_offset:984*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 984*FLEN/8, x5, x2, x6) + +inst_522: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x250 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x02b and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf250; op2val:0x842b; + valaddr_reg:x4; val_offset:986*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 986*FLEN/8, x5, x2, x6) + +inst_523: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x02b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d8 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x842b; op2val:0x80d8; + valaddr_reg:x4; val_offset:988*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 988*FLEN/8, x5, x2, x6) + +inst_524: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3c4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbc4; op2val:0x8244; + valaddr_reg:x4; val_offset:990*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 990*FLEN/8, x5, x2, x6) + +inst_525: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x02b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x039 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x842b; op2val:0xf839; + valaddr_reg:x4; val_offset:992*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 992*FLEN/8, x5, x2, x6) + +inst_526: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x039 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x02b and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf839; op2val:0x842b; + valaddr_reg:x4; val_offset:994*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 994*FLEN/8, x5, x2, x6) + +inst_527: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x02b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x842b; op2val:0x8244; + valaddr_reg:x4; val_offset:996*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 996*FLEN/8, x5, x2, x6) + +inst_528: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3c4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbc4; op2val:0x811d; + valaddr_reg:x4; val_offset:998*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 998*FLEN/8, x5, x2, x6) + +inst_529: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x02b and fs2 == 1 and fe2 == 0x1d and fm2 == 0x027 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x842b; op2val:0xf427; + valaddr_reg:x4; val_offset:1000*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1000*FLEN/8, x5, x2, x6) +RVTEST_SIGBASE(x2,signature_x2_4) + +inst_530: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x027 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x02b and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf427; op2val:0x842b; + valaddr_reg:x4; val_offset:1002*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1002*FLEN/8, x5, x2, x6) + +inst_531: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x02b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x842b; op2val:0x811d; + valaddr_reg:x4; val_offset:1004*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1004*FLEN/8, x5, x2, x6) + +inst_532: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3c4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3df and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbc4; op2val:0x83df; + valaddr_reg:x4; val_offset:1006*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1006*FLEN/8, x5, x2, x6) + +inst_533: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x02b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x337 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x842b; op2val:0xfb37; + valaddr_reg:x4; val_offset:1008*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1008*FLEN/8, x5, x2, x6) + +inst_534: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x337 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x02b and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb37; op2val:0x842b; + valaddr_reg:x4; val_offset:1010*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1010*FLEN/8, x5, x2, x6) + +inst_535: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x02b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3df and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x842b; op2val:0x83df; + valaddr_reg:x4; val_offset:1012*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1012*FLEN/8, x5, x2, x6) + +inst_536: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3c4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbc4; op2val:0xf0; + valaddr_reg:x4; val_offset:1014*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1014*FLEN/8, x5, x2, x6) + +inst_537: +// fs1 == 1 and fe1 == 0x11 and fm1 == 0x25d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xc65d; op2val:0xf0; + valaddr_reg:x4; val_offset:1016*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1016*FLEN/8, x5, x2, x6) + +inst_538: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x25d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xc65d; + valaddr_reg:x4; val_offset:1018*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1018*FLEN/8, x5, x2, x6) + +inst_539: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3c4 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x25d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbc4; op2val:0xc65d; + valaddr_reg:x4; val_offset:1020*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1020*FLEN/8, x5, x2, x6) + +inst_540: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3fa and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbfa; op2val:0x704c; + valaddr_reg:x4; val_offset:1022*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1022*FLEN/8, x5, x2, x6) + +inst_541: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x262 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xee62; op2val:0x704c; + valaddr_reg:x4; val_offset:1024*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1024*FLEN/8, x5, x2, x6) + +inst_542: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3fa and fs2 == 1 and fe2 == 0x1b and fm2 == 0x262 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbfa; op2val:0xee62; + valaddr_reg:x4; val_offset:1026*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1026*FLEN/8, x5, x2, x6) + +inst_543: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3fa and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbfa; op2val:0xfbfa; + valaddr_reg:x4; val_offset:1028*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1028*FLEN/8, x5, x2, x6) + +inst_544: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3fa and fs2 == 0 and fe2 == 0x1b and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbfa; op2val:0x6e01; + valaddr_reg:x4; val_offset:1030*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1030*FLEN/8, x5, x2, x6) + +inst_545: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x262 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xee62; op2val:0x6e01; + valaddr_reg:x4; val_offset:1032*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1032*FLEN/8, x5, x2, x6) + +inst_546: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3fa and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0e1 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbfa; op2val:0xf0e1; + valaddr_reg:x4; val_offset:1034*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1034*FLEN/8, x5, x2, x6) + +inst_547: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x262 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0e1 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xee62; op2val:0xf0e1; + valaddr_reg:x4; val_offset:1036*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1036*FLEN/8, x5, x2, x6) + +inst_548: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3fa and fs2 == 1 and fe2 == 0x1a and fm2 == 0x300 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbfa; op2val:0xeb00; + valaddr_reg:x4; val_offset:1038*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1038*FLEN/8, x5, x2, x6) + +inst_549: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x262 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x060 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xee62; op2val:0xf860; + valaddr_reg:x4; val_offset:1040*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1040*FLEN/8, x5, x2, x6) + +inst_550: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x060 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x262 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf860; op2val:0xee62; + valaddr_reg:x4; val_offset:1042*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1042*FLEN/8, x5, x2, x6) + +inst_551: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x262 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x300 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xee62; op2val:0xeb00; + valaddr_reg:x4; val_offset:1044*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1044*FLEN/8, x5, x2, x6) + +inst_552: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3fa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbfa; op2val:0x30d; + valaddr_reg:x4; val_offset:1046*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1046*FLEN/8, x5, x2, x6) + +inst_553: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x048 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1af and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8448; op2val:0x79af; + valaddr_reg:x4; val_offset:1048*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1048*FLEN/8, x5, x2, x6) + +inst_554: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1af and fs2 == 1 and fe2 == 0x01 and fm2 == 0x048 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x79af; op2val:0x8448; + valaddr_reg:x4; val_offset:1050*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1050*FLEN/8, x5, x2, x6) + +inst_555: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x048 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8448; op2val:0x30d; + valaddr_reg:x4; val_offset:1052*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1052*FLEN/8, x5, x2, x6) + +inst_556: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3fa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x048 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbfa; op2val:0x8448; + valaddr_reg:x4; val_offset:1054*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1054*FLEN/8, x5, x2, x6) + +inst_557: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3fa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbfa; op2val:0x29a; + valaddr_reg:x4; val_offset:1056*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1056*FLEN/8, x5, x2, x6) + +inst_558: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x048 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0da and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8448; op2val:0x78da; + valaddr_reg:x4; val_offset:1058*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1058*FLEN/8, x5, x2, x6) + +inst_559: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0da and fs2 == 1 and fe2 == 0x01 and fm2 == 0x048 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x78da; op2val:0x8448; + valaddr_reg:x4; val_offset:1060*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1060*FLEN/8, x5, x2, x6) + +inst_560: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x048 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8448; op2val:0x29a; + valaddr_reg:x4; val_offset:1062*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1062*FLEN/8, x5, x2, x6) + +inst_561: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3fa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbfa; op2val:0x357; + valaddr_reg:x4; val_offset:1064*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1064*FLEN/8, x5, x2, x6) + +inst_562: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x048 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x238 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8448; op2val:0x7a38; + valaddr_reg:x4; val_offset:1066*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1066*FLEN/8, x5, x2, x6) + +inst_563: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x238 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x048 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a38; op2val:0x8448; + valaddr_reg:x4; val_offset:1068*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1068*FLEN/8, x5, x2, x6) + +inst_564: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x048 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8448; op2val:0x357; + valaddr_reg:x4; val_offset:1070*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1070*FLEN/8, x5, x2, x6) + +inst_565: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3fa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbfa; op2val:0x1c8; + valaddr_reg:x4; val_offset:1072*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1072*FLEN/8, x5, x2, x6) + +inst_566: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x048 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2a3 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8448; op2val:0x76a3; + valaddr_reg:x4; val_offset:1074*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1074*FLEN/8, x5, x2, x6) + +inst_567: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a3 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x048 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x76a3; op2val:0x8448; + valaddr_reg:x4; val_offset:1076*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1076*FLEN/8, x5, x2, x6) + +inst_568: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x048 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8448; op2val:0x1c8; + valaddr_reg:x4; val_offset:1078*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1078*FLEN/8, x5, x2, x6) + +inst_569: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3fa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbfa; op2val:0x39a; + valaddr_reg:x4; val_offset:1080*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1080*FLEN/8, x5, x2, x6) + +inst_570: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x048 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b5 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8448; op2val:0x7ab5; + valaddr_reg:x4; val_offset:1082*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1082*FLEN/8, x5, x2, x6) + +inst_571: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b5 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x048 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab5; op2val:0x8448; + valaddr_reg:x4; val_offset:1084*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1084*FLEN/8, x5, x2, x6) + +inst_572: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x048 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8448; op2val:0x39a; + valaddr_reg:x4; val_offset:1086*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1086*FLEN/8, x5, x2, x6) + +inst_573: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3fa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbfa; op2val:0x82fa; + valaddr_reg:x4; val_offset:1088*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1088*FLEN/8, x5, x2, x6) + +inst_574: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x048 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x18b and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8448; op2val:0xf98b; + valaddr_reg:x4; val_offset:1090*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1090*FLEN/8, x5, x2, x6) + +inst_575: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x18b and fs2 == 1 and fe2 == 0x01 and fm2 == 0x048 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf98b; op2val:0x8448; + valaddr_reg:x4; val_offset:1092*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1092*FLEN/8, x5, x2, x6) + +inst_576: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x048 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8448; op2val:0x82fa; + valaddr_reg:x4; val_offset:1094*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1094*FLEN/8, x5, x2, x6) + +inst_577: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3fa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d8 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbfa; op2val:0x80d8; + valaddr_reg:x4; val_offset:1096*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1096*FLEN/8, x5, x2, x6) + +inst_578: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x048 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x250 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8448; op2val:0xf250; + valaddr_reg:x4; val_offset:1098*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1098*FLEN/8, x5, x2, x6) + +inst_579: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x250 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x048 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf250; op2val:0x8448; + valaddr_reg:x4; val_offset:1100*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1100*FLEN/8, x5, x2, x6) + +inst_580: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x048 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d8 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8448; op2val:0x80d8; + valaddr_reg:x4; val_offset:1102*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1102*FLEN/8, x5, x2, x6) + +inst_581: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3fa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbfa; op2val:0x8244; + valaddr_reg:x4; val_offset:1104*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1104*FLEN/8, x5, x2, x6) + +inst_582: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x048 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x039 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8448; op2val:0xf839; + valaddr_reg:x4; val_offset:1106*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1106*FLEN/8, x5, x2, x6) + +inst_583: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x039 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x048 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf839; op2val:0x8448; + valaddr_reg:x4; val_offset:1108*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1108*FLEN/8, x5, x2, x6) + +inst_584: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x048 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8448; op2val:0x8244; + valaddr_reg:x4; val_offset:1110*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1110*FLEN/8, x5, x2, x6) + +inst_585: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3fa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbfa; op2val:0x811d; + valaddr_reg:x4; val_offset:1112*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1112*FLEN/8, x5, x2, x6) + +inst_586: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x048 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x027 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8448; op2val:0xf427; + valaddr_reg:x4; val_offset:1114*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1114*FLEN/8, x5, x2, x6) + +inst_587: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x027 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x048 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf427; op2val:0x8448; + valaddr_reg:x4; val_offset:1116*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1116*FLEN/8, x5, x2, x6) + +inst_588: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x048 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8448; op2val:0x811d; + valaddr_reg:x4; val_offset:1118*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1118*FLEN/8, x5, x2, x6) + +inst_589: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3fa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3df and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbfa; op2val:0x83df; + valaddr_reg:x4; val_offset:1120*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1120*FLEN/8, x5, x2, x6) + +inst_590: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x048 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x337 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8448; op2val:0xfb37; + valaddr_reg:x4; val_offset:1122*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1122*FLEN/8, x5, x2, x6) + +inst_591: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x337 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x048 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb37; op2val:0x8448; + valaddr_reg:x4; val_offset:1124*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1124*FLEN/8, x5, x2, x6) + +inst_592: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x048 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3df and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8448; op2val:0x83df; + valaddr_reg:x4; val_offset:1126*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1126*FLEN/8, x5, x2, x6) + +inst_593: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3fa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbfa; op2val:0xf0; + valaddr_reg:x4; val_offset:1128*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1128*FLEN/8, x5, x2, x6) + +inst_594: +// fs1 == 1 and fe1 == 0x11 and fm1 == 0x289 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xc689; op2val:0xf0; + valaddr_reg:x4; val_offset:1130*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1130*FLEN/8, x5, x2, x6) + +inst_595: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x289 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xc689; + valaddr_reg:x4; val_offset:1132*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1132*FLEN/8, x5, x2, x6) + +inst_596: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3fa and fs2 == 1 and fe2 == 0x11 and fm2 == 0x289 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbfa; op2val:0xc689; + valaddr_reg:x4; val_offset:1134*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1134*FLEN/8, x5, x2, x6) + +inst_597: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x300 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x300 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xeb00; op2val:0xeb00; + valaddr_reg:x4; val_offset:1136*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1136*FLEN/8, x5, x2, x6) + +inst_598: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x300 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3ec and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xeb00; op2val:0x77ec; + valaddr_reg:x4; val_offset:1138*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1138*FLEN/8, x5, x2, x6) + +inst_599: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x060 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3ec and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf860; op2val:0x77ec; + valaddr_reg:x4; val_offset:1140*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1140*FLEN/8, x5, x2, x6) + +inst_600: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x300 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x060 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xeb00; op2val:0xf860; + valaddr_reg:x4; val_offset:1142*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1142*FLEN/8, x5, x2, x6) + +inst_601: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x300 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x218 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xeb00; op2val:0x7a18; + valaddr_reg:x4; val_offset:1144*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1144*FLEN/8, x5, x2, x6) + +inst_602: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x060 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x218 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf860; op2val:0x7a18; + valaddr_reg:x4; val_offset:1146*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1146*FLEN/8, x5, x2, x6) + +inst_603: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x300 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x351 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xeb00; op2val:0x7351; + valaddr_reg:x4; val_offset:1148*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1148*FLEN/8, x5, x2, x6) + +inst_604: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x060 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x351 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf860; op2val:0x7351; + valaddr_reg:x4; val_offset:1150*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1150*FLEN/8, x5, x2, x6) + +inst_605: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x300 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x066 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xeb00; op2val:0xf866; + valaddr_reg:x4; val_offset:1152*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1152*FLEN/8, x5, x2, x6) + +inst_606: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x060 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x066 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf860; op2val:0xf866; + valaddr_reg:x4; val_offset:1154*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1154*FLEN/8, x5, x2, x6) + +inst_607: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x300 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3c4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xeb00; op2val:0xfbc4; + valaddr_reg:x4; val_offset:1156*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1156*FLEN/8, x5, x2, x6) + +inst_608: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x060 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3c4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf860; op2val:0xfbc4; + valaddr_reg:x4; val_offset:1158*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1158*FLEN/8, x5, x2, x6) + +inst_609: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x300 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xeb00; op2val:0xfbfa; + valaddr_reg:x4; val_offset:1160*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1160*FLEN/8, x5, x2, x6) + +inst_610: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x060 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf860; op2val:0xfbfa; + valaddr_reg:x4; val_offset:1162*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1162*FLEN/8, x5, x2, x6) + +inst_611: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x300 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xeb00; op2val:0x30d; + valaddr_reg:x4; val_offset:1164*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1164*FLEN/8, x5, x2, x6) + +inst_612: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x259 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x08c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8259; op2val:0x6c8c; + valaddr_reg:x4; val_offset:1166*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1166*FLEN/8, x5, x2, x6) + +inst_613: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x08c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x259 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c8c; op2val:0x8259; + valaddr_reg:x4; val_offset:1168*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1168*FLEN/8, x5, x2, x6) + +inst_614: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x259 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8259; op2val:0x30d; + valaddr_reg:x4; val_offset:1170*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1170*FLEN/8, x5, x2, x6) + +inst_615: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x300 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x259 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xeb00; op2val:0x8259; + valaddr_reg:x4; val_offset:1172*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1172*FLEN/8, x5, x2, x6) + +inst_616: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x300 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xeb00; op2val:0x29a; + valaddr_reg:x4; val_offset:1174*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1174*FLEN/8, x5, x2, x6) + +inst_617: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x259 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x3c3 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8259; op2val:0x6bc3; + valaddr_reg:x4; val_offset:1176*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1176*FLEN/8, x5, x2, x6) + +inst_618: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3c3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x259 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6bc3; op2val:0x8259; + valaddr_reg:x4; val_offset:1178*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1178*FLEN/8, x5, x2, x6) + +inst_619: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x259 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8259; op2val:0x29a; + valaddr_reg:x4; val_offset:1180*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1180*FLEN/8, x5, x2, x6) + +inst_620: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x300 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xeb00; op2val:0x357; + valaddr_reg:x4; val_offset:1182*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1182*FLEN/8, x5, x2, x6) + +inst_621: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x259 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8259; op2val:0x6cfa; + valaddr_reg:x4; val_offset:1184*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1184*FLEN/8, x5, x2, x6) + +inst_622: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0fa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x259 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6cfa; op2val:0x8259; + valaddr_reg:x4; val_offset:1186*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1186*FLEN/8, x5, x2, x6) + +inst_623: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x259 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8259; op2val:0x357; + valaddr_reg:x4; val_offset:1188*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1188*FLEN/8, x5, x2, x6) + +inst_624: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x300 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xeb00; op2val:0x1c8; + valaddr_reg:x4; val_offset:1190*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1190*FLEN/8, x5, x2, x6) + +inst_625: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x259 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x14f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8259; op2val:0x694f; + valaddr_reg:x4; val_offset:1192*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1192*FLEN/8, x5, x2, x6) + +inst_626: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x14f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x259 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x694f; op2val:0x8259; + valaddr_reg:x4; val_offset:1194*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1194*FLEN/8, x5, x2, x6) + +inst_627: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x259 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8259; op2val:0x1c8; + valaddr_reg:x4; val_offset:1196*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1196*FLEN/8, x5, x2, x6) + +inst_628: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x300 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xeb00; op2val:0x39a; + valaddr_reg:x4; val_offset:1198*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1198*FLEN/8, x5, x2, x6) + +inst_629: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x259 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x15e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8259; op2val:0x6d5e; + valaddr_reg:x4; val_offset:1200*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1200*FLEN/8, x5, x2, x6) + +inst_630: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x15e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x259 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d5e; op2val:0x8259; + valaddr_reg:x4; val_offset:1202*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1202*FLEN/8, x5, x2, x6) + +inst_631: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x259 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8259; op2val:0x39a; + valaddr_reg:x4; val_offset:1204*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1204*FLEN/8, x5, x2, x6) + +inst_632: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x300 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xeb00; op2val:0x82fa; + valaddr_reg:x4; val_offset:1206*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1206*FLEN/8, x5, x2, x6) + +inst_633: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x259 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x06f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8259; op2val:0xec6f; + valaddr_reg:x4; val_offset:1208*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1208*FLEN/8, x5, x2, x6) + +inst_634: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x06f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x259 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xec6f; op2val:0x8259; + valaddr_reg:x4; val_offset:1210*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1210*FLEN/8, x5, x2, x6) + +inst_635: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x259 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8259; op2val:0x82fa; + valaddr_reg:x4; val_offset:1212*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1212*FLEN/8, x5, x2, x6) + +inst_636: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x300 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d8 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xeb00; op2val:0x80d8; + valaddr_reg:x4; val_offset:1214*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1214*FLEN/8, x5, x2, x6) + +inst_637: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x259 and fs2 == 1 and fe2 == 0x19 and fm2 == 0x10d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8259; op2val:0xe50d; + valaddr_reg:x4; val_offset:1216*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1216*FLEN/8, x5, x2, x6) + +inst_638: +// fs1 == 1 and fe1 == 0x19 and fm1 == 0x10d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x259 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xe50d; op2val:0x8259; + valaddr_reg:x4; val_offset:1218*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1218*FLEN/8, x5, x2, x6) + +inst_639: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x259 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d8 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8259; op2val:0x80d8; + valaddr_reg:x4; val_offset:1220*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1220*FLEN/8, x5, x2, x6) + +inst_640: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x300 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xeb00; op2val:0x8244; + valaddr_reg:x4; val_offset:1222*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1222*FLEN/8, x5, x2, x6) + +inst_641: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x259 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x2c2 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8259; op2val:0xeac2; + valaddr_reg:x4; val_offset:1224*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1224*FLEN/8, x5, x2, x6) + +inst_642: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x2c2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x259 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xeac2; op2val:0x8259; + valaddr_reg:x4; val_offset:1226*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1226*FLEN/8, x5, x2, x6) + +inst_643: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x259 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8259; op2val:0x8244; + valaddr_reg:x4; val_offset:1228*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1228*FLEN/8, x5, x2, x6) + +inst_644: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x300 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xeb00; op2val:0x811d; + valaddr_reg:x4; val_offset:1230*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1230*FLEN/8, x5, x2, x6) + +inst_645: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x259 and fs2 == 1 and fe2 == 0x19 and fm2 == 0x2a6 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8259; op2val:0xe6a6; + valaddr_reg:x4; val_offset:1232*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1232*FLEN/8, x5, x2, x6) + +inst_646: +// fs1 == 1 and fe1 == 0x19 and fm1 == 0x2a6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x259 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xe6a6; op2val:0x8259; + valaddr_reg:x4; val_offset:1234*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1234*FLEN/8, x5, x2, x6) + +inst_647: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x259 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8259; op2val:0x811d; + valaddr_reg:x4; val_offset:1236*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1236*FLEN/8, x5, x2, x6) + +inst_648: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x300 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3df and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xeb00; op2val:0x83df; + valaddr_reg:x4; val_offset:1238*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1238*FLEN/8, x5, x2, x6) + +inst_649: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x259 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x1c5 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8259; op2val:0xedc5; + valaddr_reg:x4; val_offset:1240*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1240*FLEN/8, x5, x2, x6) + +inst_650: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x1c5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x259 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xedc5; op2val:0x8259; + valaddr_reg:x4; val_offset:1242*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1242*FLEN/8, x5, x2, x6) + +inst_651: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x259 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3df and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8259; op2val:0x83df; + valaddr_reg:x4; val_offset:1244*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1244*FLEN/8, x5, x2, x6) + +inst_652: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x300 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xeb00; op2val:0xf0; + valaddr_reg:x4; val_offset:1246*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1246*FLEN/8, x5, x2, x6) + +inst_653: +// fs1 == 1 and fe1 == 0x10 and fm1 == 0x32b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xc32b; op2val:0xf0; + valaddr_reg:x4; val_offset:1248*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1248*FLEN/8, x5, x2, x6) + +inst_654: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x32b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xc32b; + valaddr_reg:x4; val_offset:1250*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1250*FLEN/8, x5, x2, x6) + +inst_655: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x300 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x32b and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xeb00; op2val:0xc32b; + valaddr_reg:x4; val_offset:1252*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1252*FLEN/8, x5, x2, x6) + +inst_656: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30d and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x30d; op2val:0x704c; + valaddr_reg:x4; val_offset:1254*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1254*FLEN/8, x5, x2, x6) + +inst_657: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x08c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c8c; op2val:0x704c; + valaddr_reg:x4; val_offset:1256*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1256*FLEN/8, x5, x2, x6) +RVTEST_SIGBASE(x2,signature_x2_5) + +inst_658: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30d and fs2 == 0 and fe2 == 0x1b and fm2 == 0x08c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x30d; op2val:0x6c8c; + valaddr_reg:x4; val_offset:1258*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1258*FLEN/8, x5, x2, x6) + +inst_659: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x30d; op2val:0x30d; + valaddr_reg:x4; val_offset:1260*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1260*FLEN/8, x5, x2, x6) + +inst_660: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30d and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3ec and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x30d; op2val:0x77ec; + valaddr_reg:x4; val_offset:1262*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1262*FLEN/8, x5, x2, x6) + +inst_661: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1af and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3ec and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x79af; op2val:0x77ec; + valaddr_reg:x4; val_offset:1264*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1264*FLEN/8, x5, x2, x6) + +inst_662: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1af and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x30d; op2val:0x79af; + valaddr_reg:x4; val_offset:1266*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1266*FLEN/8, x5, x2, x6) + +inst_663: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30d and fs2 == 0 and fe2 == 0x1b and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x30d; op2val:0x6e01; + valaddr_reg:x4; val_offset:1268*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1268*FLEN/8, x5, x2, x6) + +inst_664: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x08c and fs2 == 0 and fe2 == 0x1b and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c8c; op2val:0x6e01; + valaddr_reg:x4; val_offset:1270*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1270*FLEN/8, x5, x2, x6) + +inst_665: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x218 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x30d; op2val:0x7a18; + valaddr_reg:x4; val_offset:1272*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1272*FLEN/8, x5, x2, x6) + +inst_666: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1af and fs2 == 0 and fe2 == 0x1e and fm2 == 0x218 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x79af; op2val:0x7a18; + valaddr_reg:x4; val_offset:1274*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1274*FLEN/8, x5, x2, x6) + +inst_667: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30d and fs2 == 0 and fe2 == 0x1c and fm2 == 0x351 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x30d; op2val:0x7351; + valaddr_reg:x4; val_offset:1276*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1276*FLEN/8, x5, x2, x6) + +inst_668: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1af and fs2 == 0 and fe2 == 0x1c and fm2 == 0x351 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x79af; op2val:0x7351; + valaddr_reg:x4; val_offset:1278*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1278*FLEN/8, x5, x2, x6) + +inst_669: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30d and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0e1 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x30d; op2val:0xf0e1; + valaddr_reg:x4; val_offset:1280*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1280*FLEN/8, x5, x2, x6) + +inst_670: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x08c and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0e1 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c8c; op2val:0xf0e1; + valaddr_reg:x4; val_offset:1282*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1282*FLEN/8, x5, x2, x6) + +inst_671: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x066 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x30d; op2val:0xf866; + valaddr_reg:x4; val_offset:1284*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1284*FLEN/8, x5, x2, x6) + +inst_672: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1af and fs2 == 1 and fe2 == 0x1e and fm2 == 0x066 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x79af; op2val:0xf866; + valaddr_reg:x4; val_offset:1286*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1286*FLEN/8, x5, x2, x6) + +inst_673: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3c4 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x30d; op2val:0xfbc4; + valaddr_reg:x4; val_offset:1288*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1288*FLEN/8, x5, x2, x6) + +inst_674: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1af and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3c4 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x79af; op2val:0xfbc4; + valaddr_reg:x4; val_offset:1290*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1290*FLEN/8, x5, x2, x6) + +inst_675: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x30d; op2val:0xfbfa; + valaddr_reg:x4; val_offset:1292*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1292*FLEN/8, x5, x2, x6) + +inst_676: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1af and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x79af; op2val:0xfbfa; + valaddr_reg:x4; val_offset:1294*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1294*FLEN/8, x5, x2, x6) + +inst_677: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30d and fs2 == 1 and fe2 == 0x1a and fm2 == 0x300 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x30d; op2val:0xeb00; + valaddr_reg:x4; val_offset:1296*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1296*FLEN/8, x5, x2, x6) + +inst_678: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x08c and fs2 == 1 and fe2 == 0x1a and fm2 == 0x300 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c8c; op2val:0xeb00; + valaddr_reg:x4; val_offset:1298*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1298*FLEN/8, x5, x2, x6) + +inst_679: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x30d; op2val:0x29a; + valaddr_reg:x4; val_offset:1300*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1300*FLEN/8, x5, x2, x6) + +inst_680: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x29a; op2val:0x30d; + valaddr_reg:x4; val_offset:1302*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1302*FLEN/8, x5, x2, x6) + +inst_681: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x30d; op2val:0x357; + valaddr_reg:x4; val_offset:1304*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1304*FLEN/8, x5, x2, x6) + +inst_682: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x357; op2val:0x30d; + valaddr_reg:x4; val_offset:1306*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1306*FLEN/8, x5, x2, x6) + +inst_683: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x30d; op2val:0x1c8; + valaddr_reg:x4; val_offset:1308*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1308*FLEN/8, x5, x2, x6) + +inst_684: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x1c8; op2val:0x30d; + valaddr_reg:x4; val_offset:1310*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1310*FLEN/8, x5, x2, x6) + +inst_685: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x30d; op2val:0x39a; + valaddr_reg:x4; val_offset:1312*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1312*FLEN/8, x5, x2, x6) + +inst_686: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x39a; op2val:0x30d; + valaddr_reg:x4; val_offset:1314*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1314*FLEN/8, x5, x2, x6) + +inst_687: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x30d; op2val:0x82fa; + valaddr_reg:x4; val_offset:1316*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1316*FLEN/8, x5, x2, x6) + +inst_688: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x82fa; op2val:0x30d; + valaddr_reg:x4; val_offset:1318*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1318*FLEN/8, x5, x2, x6) + +inst_689: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x30d; op2val:0x80d8; + valaddr_reg:x4; val_offset:1320*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1320*FLEN/8, x5, x2, x6) + +inst_690: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x80d8; op2val:0x30d; + valaddr_reg:x4; val_offset:1322*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1322*FLEN/8, x5, x2, x6) + +inst_691: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x30d; op2val:0x8244; + valaddr_reg:x4; val_offset:1324*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1324*FLEN/8, x5, x2, x6) + +inst_692: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8244; op2val:0x30d; + valaddr_reg:x4; val_offset:1326*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1326*FLEN/8, x5, x2, x6) + +inst_693: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x30d; op2val:0x811d; + valaddr_reg:x4; val_offset:1328*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1328*FLEN/8, x5, x2, x6) + +inst_694: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x811d; op2val:0x30d; + valaddr_reg:x4; val_offset:1330*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1330*FLEN/8, x5, x2, x6) + +inst_695: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3df and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x30d; op2val:0x83df; + valaddr_reg:x4; val_offset:1332*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1332*FLEN/8, x5, x2, x6) + +inst_696: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3df and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83df; op2val:0x30d; + valaddr_reg:x4; val_offset:1334*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1334*FLEN/8, x5, x2, x6) + +inst_697: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x30d; op2val:0xf0; + valaddr_reg:x4; val_offset:1336*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1336*FLEN/8, x5, x2, x6) + +inst_698: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x0a8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x44a8; op2val:0xf0; + valaddr_reg:x4; val_offset:1338*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1338*FLEN/8, x5, x2, x6) + +inst_699: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0a8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x44a8; + valaddr_reg:x4; val_offset:1340*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1340*FLEN/8, x5, x2, x6) + +inst_700: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30d and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0a8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x30d; op2val:0x44a8; + valaddr_reg:x4; val_offset:1342*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1342*FLEN/8, x5, x2, x6) + +inst_701: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29a and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x29a; op2val:0x704c; + valaddr_reg:x4; val_offset:1344*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1344*FLEN/8, x5, x2, x6) + +inst_702: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3c3 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6bc3; op2val:0x704c; + valaddr_reg:x4; val_offset:1346*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1346*FLEN/8, x5, x2, x6) + +inst_703: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29a and fs2 == 0 and fe2 == 0x1a and fm2 == 0x3c3 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x29a; op2val:0x6bc3; + valaddr_reg:x4; val_offset:1348*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1348*FLEN/8, x5, x2, x6) + +inst_704: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x29a; op2val:0x29a; + valaddr_reg:x4; val_offset:1350*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1350*FLEN/8, x5, x2, x6) + +inst_705: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29a and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3ec and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x29a; op2val:0x77ec; + valaddr_reg:x4; val_offset:1352*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1352*FLEN/8, x5, x2, x6) + +inst_706: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0da and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3ec and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x78da; op2val:0x77ec; + valaddr_reg:x4; val_offset:1354*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1354*FLEN/8, x5, x2, x6) + +inst_707: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0da and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x29a; op2val:0x78da; + valaddr_reg:x4; val_offset:1356*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1356*FLEN/8, x5, x2, x6) + +inst_708: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29a and fs2 == 0 and fe2 == 0x1b and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x29a; op2val:0x6e01; + valaddr_reg:x4; val_offset:1358*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1358*FLEN/8, x5, x2, x6) + +inst_709: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3c3 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6bc3; op2val:0x6e01; + valaddr_reg:x4; val_offset:1360*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1360*FLEN/8, x5, x2, x6) + +inst_710: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x218 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x29a; op2val:0x7a18; + valaddr_reg:x4; val_offset:1362*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1362*FLEN/8, x5, x2, x6) + +inst_711: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0da and fs2 == 0 and fe2 == 0x1e and fm2 == 0x218 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x78da; op2val:0x7a18; + valaddr_reg:x4; val_offset:1364*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1364*FLEN/8, x5, x2, x6) + +inst_712: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29a and fs2 == 0 and fe2 == 0x1c and fm2 == 0x351 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x29a; op2val:0x7351; + valaddr_reg:x4; val_offset:1366*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1366*FLEN/8, x5, x2, x6) + +inst_713: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0da and fs2 == 0 and fe2 == 0x1c and fm2 == 0x351 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x78da; op2val:0x7351; + valaddr_reg:x4; val_offset:1368*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1368*FLEN/8, x5, x2, x6) + +inst_714: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29a and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0e1 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x29a; op2val:0xf0e1; + valaddr_reg:x4; val_offset:1370*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1370*FLEN/8, x5, x2, x6) + +inst_715: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3c3 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0e1 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6bc3; op2val:0xf0e1; + valaddr_reg:x4; val_offset:1372*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1372*FLEN/8, x5, x2, x6) + +inst_716: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x066 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x29a; op2val:0xf866; + valaddr_reg:x4; val_offset:1374*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1374*FLEN/8, x5, x2, x6) + +inst_717: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0da and fs2 == 1 and fe2 == 0x1e and fm2 == 0x066 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x78da; op2val:0xf866; + valaddr_reg:x4; val_offset:1376*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1376*FLEN/8, x5, x2, x6) + +inst_718: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3c4 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x29a; op2val:0xfbc4; + valaddr_reg:x4; val_offset:1378*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1378*FLEN/8, x5, x2, x6) + +inst_719: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0da and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3c4 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x78da; op2val:0xfbc4; + valaddr_reg:x4; val_offset:1380*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1380*FLEN/8, x5, x2, x6) + +inst_720: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x29a; op2val:0xfbfa; + valaddr_reg:x4; val_offset:1382*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1382*FLEN/8, x5, x2, x6) + +inst_721: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0da and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x78da; op2val:0xfbfa; + valaddr_reg:x4; val_offset:1384*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1384*FLEN/8, x5, x2, x6) + +inst_722: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29a and fs2 == 1 and fe2 == 0x1a and fm2 == 0x300 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x29a; op2val:0xeb00; + valaddr_reg:x4; val_offset:1386*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1386*FLEN/8, x5, x2, x6) + +inst_723: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3c3 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x300 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6bc3; op2val:0xeb00; + valaddr_reg:x4; val_offset:1388*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1388*FLEN/8, x5, x2, x6) + +inst_724: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x29a; op2val:0x357; + valaddr_reg:x4; val_offset:1390*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1390*FLEN/8, x5, x2, x6) + +inst_725: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x357; op2val:0x29a; + valaddr_reg:x4; val_offset:1392*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1392*FLEN/8, x5, x2, x6) + +inst_726: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x29a; op2val:0x1c8; + valaddr_reg:x4; val_offset:1394*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1394*FLEN/8, x5, x2, x6) + +inst_727: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x1c8; op2val:0x29a; + valaddr_reg:x4; val_offset:1396*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1396*FLEN/8, x5, x2, x6) + +inst_728: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x29a; op2val:0x39a; + valaddr_reg:x4; val_offset:1398*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1398*FLEN/8, x5, x2, x6) + +inst_729: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x39a; op2val:0x29a; + valaddr_reg:x4; val_offset:1400*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1400*FLEN/8, x5, x2, x6) + +inst_730: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x29a; op2val:0x82fa; + valaddr_reg:x4; val_offset:1402*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1402*FLEN/8, x5, x2, x6) + +inst_731: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x82fa; op2val:0x29a; + valaddr_reg:x4; val_offset:1404*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1404*FLEN/8, x5, x2, x6) + +inst_732: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x29a; op2val:0x80d8; + valaddr_reg:x4; val_offset:1406*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1406*FLEN/8, x5, x2, x6) + +inst_733: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x80d8; op2val:0x29a; + valaddr_reg:x4; val_offset:1408*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1408*FLEN/8, x5, x2, x6) + +inst_734: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x29a; op2val:0x8244; + valaddr_reg:x4; val_offset:1410*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1410*FLEN/8, x5, x2, x6) + +inst_735: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8244; op2val:0x29a; + valaddr_reg:x4; val_offset:1412*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1412*FLEN/8, x5, x2, x6) + +inst_736: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x29a; op2val:0x811d; + valaddr_reg:x4; val_offset:1414*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1414*FLEN/8, x5, x2, x6) + +inst_737: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x811d; op2val:0x29a; + valaddr_reg:x4; val_offset:1416*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1416*FLEN/8, x5, x2, x6) + +inst_738: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3df and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x29a; op2val:0x83df; + valaddr_reg:x4; val_offset:1418*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1418*FLEN/8, x5, x2, x6) + +inst_739: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3df and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83df; op2val:0x29a; + valaddr_reg:x4; val_offset:1420*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1420*FLEN/8, x5, x2, x6) + +inst_740: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x29a; op2val:0xf0; + valaddr_reg:x4; val_offset:1422*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1422*FLEN/8, x5, x2, x6) + +inst_741: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x3f3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x43f3; op2val:0xf0; + valaddr_reg:x4; val_offset:1424*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1424*FLEN/8, x5, x2, x6) + +inst_742: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3f3 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x43f3; + valaddr_reg:x4; val_offset:1426*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1426*FLEN/8, x5, x2, x6) + +inst_743: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29a and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3f3 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x29a; op2val:0x43f3; + valaddr_reg:x4; val_offset:1428*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1428*FLEN/8, x5, x2, x6) + +inst_744: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x357; op2val:0x704c; + valaddr_reg:x4; val_offset:1430*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1430*FLEN/8, x5, x2, x6) + +inst_745: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0fa and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6cfa; op2val:0x704c; + valaddr_reg:x4; val_offset:1432*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1432*FLEN/8, x5, x2, x6) + +inst_746: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x357; op2val:0x6cfa; + valaddr_reg:x4; val_offset:1434*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1434*FLEN/8, x5, x2, x6) + +inst_747: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x357; op2val:0x357; + valaddr_reg:x4; val_offset:1436*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1436*FLEN/8, x5, x2, x6) + +inst_748: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3ec and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x357; op2val:0x77ec; + valaddr_reg:x4; val_offset:1438*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1438*FLEN/8, x5, x2, x6) + +inst_749: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x238 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3ec and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a38; op2val:0x77ec; + valaddr_reg:x4; val_offset:1440*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1440*FLEN/8, x5, x2, x6) + +inst_750: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x238 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x357; op2val:0x7a38; + valaddr_reg:x4; val_offset:1442*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1442*FLEN/8, x5, x2, x6) + +inst_751: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x357; op2val:0x6e01; + valaddr_reg:x4; val_offset:1444*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1444*FLEN/8, x5, x2, x6) + +inst_752: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0fa and fs2 == 0 and fe2 == 0x1b and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6cfa; op2val:0x6e01; + valaddr_reg:x4; val_offset:1446*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1446*FLEN/8, x5, x2, x6) + +inst_753: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x218 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x357; op2val:0x7a18; + valaddr_reg:x4; val_offset:1448*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1448*FLEN/8, x5, x2, x6) + +inst_754: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x238 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x218 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a38; op2val:0x7a18; + valaddr_reg:x4; val_offset:1450*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1450*FLEN/8, x5, x2, x6) + +inst_755: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x351 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x357; op2val:0x7351; + valaddr_reg:x4; val_offset:1452*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1452*FLEN/8, x5, x2, x6) + +inst_756: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x238 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x351 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a38; op2val:0x7351; + valaddr_reg:x4; val_offset:1454*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1454*FLEN/8, x5, x2, x6) + +inst_757: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0e1 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x357; op2val:0xf0e1; + valaddr_reg:x4; val_offset:1456*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1456*FLEN/8, x5, x2, x6) + +inst_758: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0fa and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0e1 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6cfa; op2val:0xf0e1; + valaddr_reg:x4; val_offset:1458*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1458*FLEN/8, x5, x2, x6) + +inst_759: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x066 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x357; op2val:0xf866; + valaddr_reg:x4; val_offset:1460*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1460*FLEN/8, x5, x2, x6) + +inst_760: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x238 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x066 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a38; op2val:0xf866; + valaddr_reg:x4; val_offset:1462*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1462*FLEN/8, x5, x2, x6) + +inst_761: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3c4 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x357; op2val:0xfbc4; + valaddr_reg:x4; val_offset:1464*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1464*FLEN/8, x5, x2, x6) + +inst_762: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x238 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3c4 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a38; op2val:0xfbc4; + valaddr_reg:x4; val_offset:1466*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1466*FLEN/8, x5, x2, x6) + +inst_763: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x357; op2val:0xfbfa; + valaddr_reg:x4; val_offset:1468*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1468*FLEN/8, x5, x2, x6) + +inst_764: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x238 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a38; op2val:0xfbfa; + valaddr_reg:x4; val_offset:1470*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1470*FLEN/8, x5, x2, x6) + +inst_765: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x300 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x357; op2val:0xeb00; + valaddr_reg:x4; val_offset:1472*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1472*FLEN/8, x5, x2, x6) + +inst_766: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0fa and fs2 == 1 and fe2 == 0x1a and fm2 == 0x300 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6cfa; op2val:0xeb00; + valaddr_reg:x4; val_offset:1474*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1474*FLEN/8, x5, x2, x6) + +inst_767: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x357; op2val:0x1c8; + valaddr_reg:x4; val_offset:1476*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1476*FLEN/8, x5, x2, x6) + +inst_768: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x1c8; op2val:0x357; + valaddr_reg:x4; val_offset:1478*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1478*FLEN/8, x5, x2, x6) + +inst_769: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x357; op2val:0x39a; + valaddr_reg:x4; val_offset:1480*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1480*FLEN/8, x5, x2, x6) + +inst_770: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x39a; op2val:0x357; + valaddr_reg:x4; val_offset:1482*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1482*FLEN/8, x5, x2, x6) + +inst_771: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x357; op2val:0x82fa; + valaddr_reg:x4; val_offset:1484*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1484*FLEN/8, x5, x2, x6) + +inst_772: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x82fa; op2val:0x357; + valaddr_reg:x4; val_offset:1486*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1486*FLEN/8, x5, x2, x6) + +inst_773: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x357; op2val:0x80d8; + valaddr_reg:x4; val_offset:1488*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1488*FLEN/8, x5, x2, x6) + +inst_774: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x80d8; op2val:0x357; + valaddr_reg:x4; val_offset:1490*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1490*FLEN/8, x5, x2, x6) + +inst_775: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x357; op2val:0x8244; + valaddr_reg:x4; val_offset:1492*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1492*FLEN/8, x5, x2, x6) + +inst_776: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8244; op2val:0x357; + valaddr_reg:x4; val_offset:1494*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1494*FLEN/8, x5, x2, x6) + +inst_777: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x357; op2val:0x811d; + valaddr_reg:x4; val_offset:1496*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1496*FLEN/8, x5, x2, x6) + +inst_778: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x811d; op2val:0x357; + valaddr_reg:x4; val_offset:1498*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1498*FLEN/8, x5, x2, x6) + +inst_779: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3df and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x357; op2val:0x83df; + valaddr_reg:x4; val_offset:1500*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1500*FLEN/8, x5, x2, x6) + +inst_780: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3df and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83df; op2val:0x357; + valaddr_reg:x4; val_offset:1502*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1502*FLEN/8, x5, x2, x6) + +inst_781: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x357; op2val:0xf0; + valaddr_reg:x4; val_offset:1504*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1504*FLEN/8, x5, x2, x6) + +inst_782: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x118 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x4518; op2val:0xf0; + valaddr_reg:x4; val_offset:1506*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1506*FLEN/8, x5, x2, x6) + +inst_783: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x118 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x4518; + valaddr_reg:x4; val_offset:1508*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1508*FLEN/8, x5, x2, x6) + +inst_784: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x118 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x357; op2val:0x4518; + valaddr_reg:x4; val_offset:1510*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1510*FLEN/8, x5, x2, x6) + +inst_785: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x1c8; op2val:0x704c; + valaddr_reg:x4; val_offset:1512*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1512*FLEN/8, x5, x2, x6) +RVTEST_SIGBASE(x2,signature_x2_6) + +inst_786: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x14f and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x694f; op2val:0x704c; + valaddr_reg:x4; val_offset:1514*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1514*FLEN/8, x5, x2, x6) + +inst_787: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x14f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x1c8; op2val:0x694f; + valaddr_reg:x4; val_offset:1516*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1516*FLEN/8, x5, x2, x6) + +inst_788: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x1c8; op2val:0x1c8; + valaddr_reg:x4; val_offset:1518*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1518*FLEN/8, x5, x2, x6) + +inst_789: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3ec and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x1c8; op2val:0x77ec; + valaddr_reg:x4; val_offset:1520*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1520*FLEN/8, x5, x2, x6) + +inst_790: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a3 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3ec and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x76a3; op2val:0x77ec; + valaddr_reg:x4; val_offset:1522*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1522*FLEN/8, x5, x2, x6) + +inst_791: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2a3 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x1c8; op2val:0x76a3; + valaddr_reg:x4; val_offset:1524*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1524*FLEN/8, x5, x2, x6) + +inst_792: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x1c8; op2val:0x6e01; + valaddr_reg:x4; val_offset:1526*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1526*FLEN/8, x5, x2, x6) + +inst_793: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x14f and fs2 == 0 and fe2 == 0x1b and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x694f; op2val:0x6e01; + valaddr_reg:x4; val_offset:1528*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1528*FLEN/8, x5, x2, x6) + +inst_794: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x218 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x1c8; op2val:0x7a18; + valaddr_reg:x4; val_offset:1530*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1530*FLEN/8, x5, x2, x6) + +inst_795: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x218 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x76a3; op2val:0x7a18; + valaddr_reg:x4; val_offset:1532*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1532*FLEN/8, x5, x2, x6) + +inst_796: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x351 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x1c8; op2val:0x7351; + valaddr_reg:x4; val_offset:1534*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1534*FLEN/8, x5, x2, x6) + +inst_797: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a3 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x351 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x76a3; op2val:0x7351; + valaddr_reg:x4; val_offset:1536*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1536*FLEN/8, x5, x2, x6) + +inst_798: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0e1 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x1c8; op2val:0xf0e1; + valaddr_reg:x4; val_offset:1538*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1538*FLEN/8, x5, x2, x6) + +inst_799: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x14f and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0e1 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x694f; op2val:0xf0e1; + valaddr_reg:x4; val_offset:1540*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1540*FLEN/8, x5, x2, x6) + +inst_800: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x066 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x1c8; op2val:0xf866; + valaddr_reg:x4; val_offset:1542*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1542*FLEN/8, x5, x2, x6) + +inst_801: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x066 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x76a3; op2val:0xf866; + valaddr_reg:x4; val_offset:1544*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1544*FLEN/8, x5, x2, x6) + +inst_802: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3c4 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x1c8; op2val:0xfbc4; + valaddr_reg:x4; val_offset:1546*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1546*FLEN/8, x5, x2, x6) + +inst_803: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3c4 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x76a3; op2val:0xfbc4; + valaddr_reg:x4; val_offset:1548*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1548*FLEN/8, x5, x2, x6) + +inst_804: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x1c8; op2val:0xfbfa; + valaddr_reg:x4; val_offset:1550*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1550*FLEN/8, x5, x2, x6) + +inst_805: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x76a3; op2val:0xfbfa; + valaddr_reg:x4; val_offset:1552*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1552*FLEN/8, x5, x2, x6) + +inst_806: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x300 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x1c8; op2val:0xeb00; + valaddr_reg:x4; val_offset:1554*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1554*FLEN/8, x5, x2, x6) + +inst_807: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x14f and fs2 == 1 and fe2 == 0x1a and fm2 == 0x300 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x694f; op2val:0xeb00; + valaddr_reg:x4; val_offset:1556*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1556*FLEN/8, x5, x2, x6) + +inst_808: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x1c8; op2val:0x39a; + valaddr_reg:x4; val_offset:1558*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1558*FLEN/8, x5, x2, x6) + +inst_809: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x39a; op2val:0x1c8; + valaddr_reg:x4; val_offset:1560*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1560*FLEN/8, x5, x2, x6) + +inst_810: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x1c8; op2val:0x82fa; + valaddr_reg:x4; val_offset:1562*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1562*FLEN/8, x5, x2, x6) + +inst_811: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x82fa; op2val:0x1c8; + valaddr_reg:x4; val_offset:1564*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1564*FLEN/8, x5, x2, x6) + +inst_812: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x1c8; op2val:0x80d8; + valaddr_reg:x4; val_offset:1566*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1566*FLEN/8, x5, x2, x6) + +inst_813: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x80d8; op2val:0x1c8; + valaddr_reg:x4; val_offset:1568*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1568*FLEN/8, x5, x2, x6) + +inst_814: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x1c8; op2val:0x8244; + valaddr_reg:x4; val_offset:1570*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1570*FLEN/8, x5, x2, x6) + +inst_815: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8244; op2val:0x1c8; + valaddr_reg:x4; val_offset:1572*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1572*FLEN/8, x5, x2, x6) + +inst_816: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x1c8; op2val:0x811d; + valaddr_reg:x4; val_offset:1574*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1574*FLEN/8, x5, x2, x6) + +inst_817: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x811d; op2val:0x1c8; + valaddr_reg:x4; val_offset:1576*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1576*FLEN/8, x5, x2, x6) + +inst_818: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3df and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x1c8; op2val:0x83df; + valaddr_reg:x4; val_offset:1578*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1578*FLEN/8, x5, x2, x6) + +inst_819: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3df and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83df; op2val:0x1c8; + valaddr_reg:x4; val_offset:1580*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1580*FLEN/8, x5, x2, x6) + +inst_820: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x1c8; op2val:0xf0; + valaddr_reg:x4; val_offset:1582*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1582*FLEN/8, x5, x2, x6) + +inst_821: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x170 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x4170; op2val:0xf0; + valaddr_reg:x4; val_offset:1584*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1584*FLEN/8, x5, x2, x6) + +inst_822: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x170 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x4170; + valaddr_reg:x4; val_offset:1586*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1586*FLEN/8, x5, x2, x6) + +inst_823: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x170 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x1c8; op2val:0x4170; + valaddr_reg:x4; val_offset:1588*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1588*FLEN/8, x5, x2, x6) + +inst_824: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39a and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x39a; op2val:0x704c; + valaddr_reg:x4; val_offset:1590*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1590*FLEN/8, x5, x2, x6) + +inst_825: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x15e and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d5e; op2val:0x704c; + valaddr_reg:x4; val_offset:1592*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1592*FLEN/8, x5, x2, x6) + +inst_826: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39a and fs2 == 0 and fe2 == 0x1b and fm2 == 0x15e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x39a; op2val:0x6d5e; + valaddr_reg:x4; val_offset:1594*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1594*FLEN/8, x5, x2, x6) + +inst_827: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x39a; op2val:0x39a; + valaddr_reg:x4; val_offset:1596*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1596*FLEN/8, x5, x2, x6) + +inst_828: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39a and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3ec and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x39a; op2val:0x77ec; + valaddr_reg:x4; val_offset:1598*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1598*FLEN/8, x5, x2, x6) + +inst_829: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b5 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3ec and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab5; op2val:0x77ec; + valaddr_reg:x4; val_offset:1600*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1600*FLEN/8, x5, x2, x6) + +inst_830: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b5 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x39a; op2val:0x7ab5; + valaddr_reg:x4; val_offset:1602*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1602*FLEN/8, x5, x2, x6) + +inst_831: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39a and fs2 == 0 and fe2 == 0x1b and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x39a; op2val:0x6e01; + valaddr_reg:x4; val_offset:1604*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1604*FLEN/8, x5, x2, x6) + +inst_832: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x15e and fs2 == 0 and fe2 == 0x1b and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d5e; op2val:0x6e01; + valaddr_reg:x4; val_offset:1606*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1606*FLEN/8, x5, x2, x6) + +inst_833: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x218 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x39a; op2val:0x7a18; + valaddr_reg:x4; val_offset:1608*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1608*FLEN/8, x5, x2, x6) + +inst_834: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x218 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab5; op2val:0x7a18; + valaddr_reg:x4; val_offset:1610*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1610*FLEN/8, x5, x2, x6) + +inst_835: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39a and fs2 == 0 and fe2 == 0x1c and fm2 == 0x351 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x39a; op2val:0x7351; + valaddr_reg:x4; val_offset:1612*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1612*FLEN/8, x5, x2, x6) + +inst_836: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b5 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x351 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab5; op2val:0x7351; + valaddr_reg:x4; val_offset:1614*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1614*FLEN/8, x5, x2, x6) + +inst_837: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39a and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0e1 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x39a; op2val:0xf0e1; + valaddr_reg:x4; val_offset:1616*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1616*FLEN/8, x5, x2, x6) + +inst_838: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x15e and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0e1 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d5e; op2val:0xf0e1; + valaddr_reg:x4; val_offset:1618*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1618*FLEN/8, x5, x2, x6) + +inst_839: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x066 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x39a; op2val:0xf866; + valaddr_reg:x4; val_offset:1620*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1620*FLEN/8, x5, x2, x6) + +inst_840: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b5 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x066 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab5; op2val:0xf866; + valaddr_reg:x4; val_offset:1622*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1622*FLEN/8, x5, x2, x6) + +inst_841: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3c4 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x39a; op2val:0xfbc4; + valaddr_reg:x4; val_offset:1624*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1624*FLEN/8, x5, x2, x6) + +inst_842: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b5 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3c4 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab5; op2val:0xfbc4; + valaddr_reg:x4; val_offset:1626*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1626*FLEN/8, x5, x2, x6) + +inst_843: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x39a; op2val:0xfbfa; + valaddr_reg:x4; val_offset:1628*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1628*FLEN/8, x5, x2, x6) + +inst_844: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b5 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab5; op2val:0xfbfa; + valaddr_reg:x4; val_offset:1630*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1630*FLEN/8, x5, x2, x6) + +inst_845: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39a and fs2 == 1 and fe2 == 0x1a and fm2 == 0x300 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x39a; op2val:0xeb00; + valaddr_reg:x4; val_offset:1632*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1632*FLEN/8, x5, x2, x6) + +inst_846: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x15e and fs2 == 1 and fe2 == 0x1a and fm2 == 0x300 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d5e; op2val:0xeb00; + valaddr_reg:x4; val_offset:1634*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1634*FLEN/8, x5, x2, x6) + +inst_847: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x39a; op2val:0x82fa; + valaddr_reg:x4; val_offset:1636*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1636*FLEN/8, x5, x2, x6) + +inst_848: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x82fa; op2val:0x39a; + valaddr_reg:x4; val_offset:1638*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1638*FLEN/8, x5, x2, x6) + +inst_849: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x39a; op2val:0x80d8; + valaddr_reg:x4; val_offset:1640*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1640*FLEN/8, x5, x2, x6) + +inst_850: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x80d8; op2val:0x39a; + valaddr_reg:x4; val_offset:1642*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1642*FLEN/8, x5, x2, x6) + +inst_851: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x39a; op2val:0x8244; + valaddr_reg:x4; val_offset:1644*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1644*FLEN/8, x5, x2, x6) + +inst_852: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8244; op2val:0x39a; + valaddr_reg:x4; val_offset:1646*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1646*FLEN/8, x5, x2, x6) + +inst_853: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x39a; op2val:0x811d; + valaddr_reg:x4; val_offset:1648*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1648*FLEN/8, x5, x2, x6) + +inst_854: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x811d; op2val:0x39a; + valaddr_reg:x4; val_offset:1650*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1650*FLEN/8, x5, x2, x6) + +inst_855: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3df and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x39a; op2val:0x83df; + valaddr_reg:x4; val_offset:1652*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1652*FLEN/8, x5, x2, x6) + +inst_856: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3df and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83df; op2val:0x39a; + valaddr_reg:x4; val_offset:1654*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1654*FLEN/8, x5, x2, x6) + +inst_857: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x39a; op2val:0xf0; + valaddr_reg:x4; val_offset:1656*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1656*FLEN/8, x5, x2, x6) + +inst_858: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x17f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x457f; op2val:0xf0; + valaddr_reg:x4; val_offset:1658*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1658*FLEN/8, x5, x2, x6) + +inst_859: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x17f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x457f; + valaddr_reg:x4; val_offset:1660*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1660*FLEN/8, x5, x2, x6) + +inst_860: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39a and fs2 == 0 and fe2 == 0x11 and fm2 == 0x17f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x39a; op2val:0x457f; + valaddr_reg:x4; val_offset:1662*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1662*FLEN/8, x5, x2, x6) + +inst_861: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fa and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x82fa; op2val:0x704c; + valaddr_reg:x4; val_offset:1664*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1664*FLEN/8, x5, x2, x6) + +inst_862: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x06f and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xec6f; op2val:0x704c; + valaddr_reg:x4; val_offset:1666*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1666*FLEN/8, x5, x2, x6) + +inst_863: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fa and fs2 == 1 and fe2 == 0x1b and fm2 == 0x06f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x82fa; op2val:0xec6f; + valaddr_reg:x4; val_offset:1668*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1668*FLEN/8, x5, x2, x6) + +inst_864: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x82fa; op2val:0x82fa; + valaddr_reg:x4; val_offset:1670*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1670*FLEN/8, x5, x2, x6) + +inst_865: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fa and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3ec and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x82fa; op2val:0x77ec; + valaddr_reg:x4; val_offset:1672*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1672*FLEN/8, x5, x2, x6) + +inst_866: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x18b and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3ec and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf98b; op2val:0x77ec; + valaddr_reg:x4; val_offset:1674*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1674*FLEN/8, x5, x2, x6) + +inst_867: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fa and fs2 == 1 and fe2 == 0x1e and fm2 == 0x18b and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x82fa; op2val:0xf98b; + valaddr_reg:x4; val_offset:1676*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1676*FLEN/8, x5, x2, x6) + +inst_868: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fa and fs2 == 0 and fe2 == 0x1b and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x82fa; op2val:0x6e01; + valaddr_reg:x4; val_offset:1678*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1678*FLEN/8, x5, x2, x6) + +inst_869: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x06f and fs2 == 0 and fe2 == 0x1b and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xec6f; op2val:0x6e01; + valaddr_reg:x4; val_offset:1680*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1680*FLEN/8, x5, x2, x6) + +inst_870: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fa and fs2 == 0 and fe2 == 0x1e and fm2 == 0x218 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x82fa; op2val:0x7a18; + valaddr_reg:x4; val_offset:1682*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1682*FLEN/8, x5, x2, x6) + +inst_871: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x18b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x218 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf98b; op2val:0x7a18; + valaddr_reg:x4; val_offset:1684*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1684*FLEN/8, x5, x2, x6) + +inst_872: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fa and fs2 == 0 and fe2 == 0x1c and fm2 == 0x351 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x82fa; op2val:0x7351; + valaddr_reg:x4; val_offset:1686*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1686*FLEN/8, x5, x2, x6) + +inst_873: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x18b and fs2 == 0 and fe2 == 0x1c and fm2 == 0x351 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf98b; op2val:0x7351; + valaddr_reg:x4; val_offset:1688*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1688*FLEN/8, x5, x2, x6) + +inst_874: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fa and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0e1 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x82fa; op2val:0xf0e1; + valaddr_reg:x4; val_offset:1690*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1690*FLEN/8, x5, x2, x6) + +inst_875: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x06f and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0e1 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xec6f; op2val:0xf0e1; + valaddr_reg:x4; val_offset:1692*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1692*FLEN/8, x5, x2, x6) + +inst_876: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fa and fs2 == 1 and fe2 == 0x1e and fm2 == 0x066 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x82fa; op2val:0xf866; + valaddr_reg:x4; val_offset:1694*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1694*FLEN/8, x5, x2, x6) + +inst_877: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x18b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x066 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf98b; op2val:0xf866; + valaddr_reg:x4; val_offset:1696*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1696*FLEN/8, x5, x2, x6) + +inst_878: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fa and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3c4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x82fa; op2val:0xfbc4; + valaddr_reg:x4; val_offset:1698*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1698*FLEN/8, x5, x2, x6) + +inst_879: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x18b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3c4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf98b; op2val:0xfbc4; + valaddr_reg:x4; val_offset:1700*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1700*FLEN/8, x5, x2, x6) + +inst_880: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fa and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x82fa; op2val:0xfbfa; + valaddr_reg:x4; val_offset:1702*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1702*FLEN/8, x5, x2, x6) + +inst_881: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x18b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf98b; op2val:0xfbfa; + valaddr_reg:x4; val_offset:1704*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1704*FLEN/8, x5, x2, x6) + +inst_882: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fa and fs2 == 1 and fe2 == 0x1a and fm2 == 0x300 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x82fa; op2val:0xeb00; + valaddr_reg:x4; val_offset:1706*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1706*FLEN/8, x5, x2, x6) + +inst_883: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x06f and fs2 == 1 and fe2 == 0x1a and fm2 == 0x300 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xec6f; op2val:0xeb00; + valaddr_reg:x4; val_offset:1708*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1708*FLEN/8, x5, x2, x6) + +inst_884: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d8 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x82fa; op2val:0x80d8; + valaddr_reg:x4; val_offset:1710*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1710*FLEN/8, x5, x2, x6) + +inst_885: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x80d8; op2val:0x82fa; + valaddr_reg:x4; val_offset:1712*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1712*FLEN/8, x5, x2, x6) + +inst_886: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x82fa; op2val:0x8244; + valaddr_reg:x4; val_offset:1714*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1714*FLEN/8, x5, x2, x6) + +inst_887: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8244; op2val:0x82fa; + valaddr_reg:x4; val_offset:1716*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1716*FLEN/8, x5, x2, x6) + +inst_888: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x82fa; op2val:0x811d; + valaddr_reg:x4; val_offset:1718*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1718*FLEN/8, x5, x2, x6) + +inst_889: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x811d; op2val:0x82fa; + valaddr_reg:x4; val_offset:1720*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1720*FLEN/8, x5, x2, x6) + +inst_890: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3df and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x82fa; op2val:0x83df; + valaddr_reg:x4; val_offset:1722*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1722*FLEN/8, x5, x2, x6) + +inst_891: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3df and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83df; op2val:0x82fa; + valaddr_reg:x4; val_offset:1724*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1724*FLEN/8, x5, x2, x6) + +inst_892: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x82fa; op2val:0xf0; + valaddr_reg:x4; val_offset:1726*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1726*FLEN/8, x5, x2, x6) + +inst_893: +// fs1 == 1 and fe1 == 0x11 and fm1 == 0x08b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xc48b; op2val:0xf0; + valaddr_reg:x4; val_offset:1728*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1728*FLEN/8, x5, x2, x6) + +inst_894: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x08b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xc48b; + valaddr_reg:x4; val_offset:1730*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1730*FLEN/8, x5, x2, x6) + +inst_895: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fa and fs2 == 1 and fe2 == 0x11 and fm2 == 0x08b and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x82fa; op2val:0xc48b; + valaddr_reg:x4; val_offset:1732*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1732*FLEN/8, x5, x2, x6) + +inst_896: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d8 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x80d8; op2val:0x704c; + valaddr_reg:x4; val_offset:1734*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1734*FLEN/8, x5, x2, x6) + +inst_897: +// fs1 == 1 and fe1 == 0x19 and fm1 == 0x10d and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xe50d; op2val:0x704c; + valaddr_reg:x4; val_offset:1736*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1736*FLEN/8, x5, x2, x6) + +inst_898: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d8 and fs2 == 1 and fe2 == 0x19 and fm2 == 0x10d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x80d8; op2val:0xe50d; + valaddr_reg:x4; val_offset:1738*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1738*FLEN/8, x5, x2, x6) + +inst_899: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d8 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x80d8; op2val:0x80d8; + valaddr_reg:x4; val_offset:1740*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1740*FLEN/8, x5, x2, x6) + +inst_900: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d8 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3ec and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x80d8; op2val:0x77ec; + valaddr_reg:x4; val_offset:1742*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1742*FLEN/8, x5, x2, x6) + +inst_901: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x250 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3ec and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf250; op2val:0x77ec; + valaddr_reg:x4; val_offset:1744*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1744*FLEN/8, x5, x2, x6) + +inst_902: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d8 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x250 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x80d8; op2val:0xf250; + valaddr_reg:x4; val_offset:1746*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1746*FLEN/8, x5, x2, x6) + +inst_903: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d8 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x80d8; op2val:0x6e01; + valaddr_reg:x4; val_offset:1748*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1748*FLEN/8, x5, x2, x6) + +inst_904: +// fs1 == 1 and fe1 == 0x19 and fm1 == 0x10d and fs2 == 0 and fe2 == 0x1b and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xe50d; op2val:0x6e01; + valaddr_reg:x4; val_offset:1750*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1750*FLEN/8, x5, x2, x6) + +inst_905: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x218 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x80d8; op2val:0x7a18; + valaddr_reg:x4; val_offset:1752*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1752*FLEN/8, x5, x2, x6) + +inst_906: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x250 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x218 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf250; op2val:0x7a18; + valaddr_reg:x4; val_offset:1754*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1754*FLEN/8, x5, x2, x6) + +inst_907: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d8 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x351 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x80d8; op2val:0x7351; + valaddr_reg:x4; val_offset:1756*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1756*FLEN/8, x5, x2, x6) + +inst_908: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x250 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x351 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf250; op2val:0x7351; + valaddr_reg:x4; val_offset:1758*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1758*FLEN/8, x5, x2, x6) + +inst_909: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d8 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0e1 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x80d8; op2val:0xf0e1; + valaddr_reg:x4; val_offset:1760*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1760*FLEN/8, x5, x2, x6) + +inst_910: +// fs1 == 1 and fe1 == 0x19 and fm1 == 0x10d and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0e1 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xe50d; op2val:0xf0e1; + valaddr_reg:x4; val_offset:1762*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1762*FLEN/8, x5, x2, x6) + +inst_911: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d8 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x066 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x80d8; op2val:0xf866; + valaddr_reg:x4; val_offset:1764*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1764*FLEN/8, x5, x2, x6) + +inst_912: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x250 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x066 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf250; op2val:0xf866; + valaddr_reg:x4; val_offset:1766*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1766*FLEN/8, x5, x2, x6) + +inst_913: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d8 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3c4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x80d8; op2val:0xfbc4; + valaddr_reg:x4; val_offset:1768*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1768*FLEN/8, x5, x2, x6) +RVTEST_SIGBASE(x2,signature_x2_7) + +inst_914: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x250 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3c4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf250; op2val:0xfbc4; + valaddr_reg:x4; val_offset:1770*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1770*FLEN/8, x5, x2, x6) + +inst_915: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d8 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x80d8; op2val:0xfbfa; + valaddr_reg:x4; val_offset:1772*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1772*FLEN/8, x5, x2, x6) + +inst_916: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x250 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf250; op2val:0xfbfa; + valaddr_reg:x4; val_offset:1774*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1774*FLEN/8, x5, x2, x6) + +inst_917: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d8 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x300 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x80d8; op2val:0xeb00; + valaddr_reg:x4; val_offset:1776*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1776*FLEN/8, x5, x2, x6) + +inst_918: +// fs1 == 1 and fe1 == 0x19 and fm1 == 0x10d and fs2 == 1 and fe2 == 0x1a and fm2 == 0x300 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xe50d; op2val:0xeb00; + valaddr_reg:x4; val_offset:1778*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1778*FLEN/8, x5, x2, x6) + +inst_919: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x80d8; op2val:0x8244; + valaddr_reg:x4; val_offset:1780*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1780*FLEN/8, x5, x2, x6) + +inst_920: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d8 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8244; op2val:0x80d8; + valaddr_reg:x4; val_offset:1782*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1782*FLEN/8, x5, x2, x6) + +inst_921: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x80d8; op2val:0x811d; + valaddr_reg:x4; val_offset:1784*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1784*FLEN/8, x5, x2, x6) + +inst_922: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d8 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x811d; op2val:0x80d8; + valaddr_reg:x4; val_offset:1786*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1786*FLEN/8, x5, x2, x6) + +inst_923: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3df and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x80d8; op2val:0x83df; + valaddr_reg:x4; val_offset:1788*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1788*FLEN/8, x5, x2, x6) + +inst_924: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3df and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d8 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83df; op2val:0x80d8; + valaddr_reg:x4; val_offset:1790*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1790*FLEN/8, x5, x2, x6) + +inst_925: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x80d8; op2val:0xf0; + valaddr_reg:x4; val_offset:1792*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1792*FLEN/8, x5, x2, x6) + +inst_926: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x12c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xbd2c; op2val:0xf0; + valaddr_reg:x4; val_offset:1794*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1794*FLEN/8, x5, x2, x6) + +inst_927: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x12c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xbd2c; + valaddr_reg:x4; val_offset:1796*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1796*FLEN/8, x5, x2, x6) + +inst_928: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d8 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x12c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x80d8; op2val:0xbd2c; + valaddr_reg:x4; val_offset:1798*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1798*FLEN/8, x5, x2, x6) + +inst_929: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8244; op2val:0x704c; + valaddr_reg:x4; val_offset:1800*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1800*FLEN/8, x5, x2, x6) + +inst_930: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x2c2 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xeac2; op2val:0x704c; + valaddr_reg:x4; val_offset:1802*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1802*FLEN/8, x5, x2, x6) + +inst_931: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x2c2 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8244; op2val:0xeac2; + valaddr_reg:x4; val_offset:1804*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1804*FLEN/8, x5, x2, x6) + +inst_932: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8244; op2val:0x8244; + valaddr_reg:x4; val_offset:1806*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1806*FLEN/8, x5, x2, x6) + +inst_933: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3ec and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8244; op2val:0x77ec; + valaddr_reg:x4; val_offset:1808*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1808*FLEN/8, x5, x2, x6) + +inst_934: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x039 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3ec and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf839; op2val:0x77ec; + valaddr_reg:x4; val_offset:1810*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1810*FLEN/8, x5, x2, x6) + +inst_935: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x039 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8244; op2val:0xf839; + valaddr_reg:x4; val_offset:1812*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1812*FLEN/8, x5, x2, x6) + +inst_936: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8244; op2val:0x6e01; + valaddr_reg:x4; val_offset:1814*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1814*FLEN/8, x5, x2, x6) + +inst_937: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x2c2 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xeac2; op2val:0x6e01; + valaddr_reg:x4; val_offset:1816*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1816*FLEN/8, x5, x2, x6) + +inst_938: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x218 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8244; op2val:0x7a18; + valaddr_reg:x4; val_offset:1818*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1818*FLEN/8, x5, x2, x6) + +inst_939: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x039 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x218 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf839; op2val:0x7a18; + valaddr_reg:x4; val_offset:1820*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1820*FLEN/8, x5, x2, x6) + +inst_940: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x351 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8244; op2val:0x7351; + valaddr_reg:x4; val_offset:1822*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1822*FLEN/8, x5, x2, x6) + +inst_941: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x039 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x351 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf839; op2val:0x7351; + valaddr_reg:x4; val_offset:1824*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1824*FLEN/8, x5, x2, x6) + +inst_942: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0e1 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8244; op2val:0xf0e1; + valaddr_reg:x4; val_offset:1826*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1826*FLEN/8, x5, x2, x6) + +inst_943: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x2c2 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0e1 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xeac2; op2val:0xf0e1; + valaddr_reg:x4; val_offset:1828*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1828*FLEN/8, x5, x2, x6) + +inst_944: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x066 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8244; op2val:0xf866; + valaddr_reg:x4; val_offset:1830*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1830*FLEN/8, x5, x2, x6) + +inst_945: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x039 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x066 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf839; op2val:0xf866; + valaddr_reg:x4; val_offset:1832*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1832*FLEN/8, x5, x2, x6) + +inst_946: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3c4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8244; op2val:0xfbc4; + valaddr_reg:x4; val_offset:1834*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1834*FLEN/8, x5, x2, x6) + +inst_947: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x039 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3c4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf839; op2val:0xfbc4; + valaddr_reg:x4; val_offset:1836*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1836*FLEN/8, x5, x2, x6) + +inst_948: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8244; op2val:0xfbfa; + valaddr_reg:x4; val_offset:1838*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1838*FLEN/8, x5, x2, x6) + +inst_949: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x039 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf839; op2val:0xfbfa; + valaddr_reg:x4; val_offset:1840*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1840*FLEN/8, x5, x2, x6) + +inst_950: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x300 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8244; op2val:0xeb00; + valaddr_reg:x4; val_offset:1842*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1842*FLEN/8, x5, x2, x6) + +inst_951: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x2c2 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x300 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xeac2; op2val:0xeb00; + valaddr_reg:x4; val_offset:1844*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1844*FLEN/8, x5, x2, x6) + +inst_952: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8244; op2val:0x811d; + valaddr_reg:x4; val_offset:1846*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1846*FLEN/8, x5, x2, x6) + +inst_953: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x811d; op2val:0x8244; + valaddr_reg:x4; val_offset:1848*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1848*FLEN/8, x5, x2, x6) + +inst_954: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3df and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8244; op2val:0x83df; + valaddr_reg:x4; val_offset:1850*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1850*FLEN/8, x5, x2, x6) + +inst_955: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3df and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83df; op2val:0x8244; + valaddr_reg:x4; val_offset:1852*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1852*FLEN/8, x5, x2, x6) + +inst_956: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8244; op2val:0xf0; + valaddr_reg:x4; val_offset:1854*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1854*FLEN/8, x5, x2, x6) + +inst_957: +// fs1 == 1 and fe1 == 0x10 and fm1 == 0x2ec and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xc2ec; op2val:0xf0; + valaddr_reg:x4; val_offset:1856*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1856*FLEN/8, x5, x2, x6) + +inst_958: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2ec and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xc2ec; + valaddr_reg:x4; val_offset:1858*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1858*FLEN/8, x5, x2, x6) + +inst_959: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2ec and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x8244; op2val:0xc2ec; + valaddr_reg:x4; val_offset:1860*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1860*FLEN/8, x5, x2, x6) + +inst_960: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x811d; op2val:0x704c; + valaddr_reg:x4; val_offset:1862*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1862*FLEN/8, x5, x2, x6) + +inst_961: +// fs1 == 1 and fe1 == 0x19 and fm1 == 0x2a6 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xe6a6; op2val:0x704c; + valaddr_reg:x4; val_offset:1864*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1864*FLEN/8, x5, x2, x6) + +inst_962: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d and fs2 == 1 and fe2 == 0x19 and fm2 == 0x2a6 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x811d; op2val:0xe6a6; + valaddr_reg:x4; val_offset:1866*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1866*FLEN/8, x5, x2, x6) + +inst_963: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x811d; op2val:0x811d; + valaddr_reg:x4; val_offset:1868*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1868*FLEN/8, x5, x2, x6) + +inst_964: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3ec and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x811d; op2val:0x77ec; + valaddr_reg:x4; val_offset:1870*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1870*FLEN/8, x5, x2, x6) + +inst_965: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x027 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3ec and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf427; op2val:0x77ec; + valaddr_reg:x4; val_offset:1872*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1872*FLEN/8, x5, x2, x6) + +inst_966: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d and fs2 == 1 and fe2 == 0x1d and fm2 == 0x027 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x811d; op2val:0xf427; + valaddr_reg:x4; val_offset:1874*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1874*FLEN/8, x5, x2, x6) + +inst_967: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d and fs2 == 0 and fe2 == 0x1b and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x811d; op2val:0x6e01; + valaddr_reg:x4; val_offset:1876*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1876*FLEN/8, x5, x2, x6) + +inst_968: +// fs1 == 1 and fe1 == 0x19 and fm1 == 0x2a6 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xe6a6; op2val:0x6e01; + valaddr_reg:x4; val_offset:1878*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1878*FLEN/8, x5, x2, x6) + +inst_969: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x218 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x811d; op2val:0x7a18; + valaddr_reg:x4; val_offset:1880*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1880*FLEN/8, x5, x2, x6) + +inst_970: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x027 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x218 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf427; op2val:0x7a18; + valaddr_reg:x4; val_offset:1882*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1882*FLEN/8, x5, x2, x6) + +inst_971: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d and fs2 == 0 and fe2 == 0x1c and fm2 == 0x351 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x811d; op2val:0x7351; + valaddr_reg:x4; val_offset:1884*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1884*FLEN/8, x5, x2, x6) + +inst_972: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x027 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x351 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf427; op2val:0x7351; + valaddr_reg:x4; val_offset:1886*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1886*FLEN/8, x5, x2, x6) + +inst_973: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0e1 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x811d; op2val:0xf0e1; + valaddr_reg:x4; val_offset:1888*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1888*FLEN/8, x5, x2, x6) + +inst_974: +// fs1 == 1 and fe1 == 0x19 and fm1 == 0x2a6 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0e1 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xe6a6; op2val:0xf0e1; + valaddr_reg:x4; val_offset:1890*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1890*FLEN/8, x5, x2, x6) + +inst_975: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x066 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x811d; op2val:0xf866; + valaddr_reg:x4; val_offset:1892*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1892*FLEN/8, x5, x2, x6) + +inst_976: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x027 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x066 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf427; op2val:0xf866; + valaddr_reg:x4; val_offset:1894*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1894*FLEN/8, x5, x2, x6) + +inst_977: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3c4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x811d; op2val:0xfbc4; + valaddr_reg:x4; val_offset:1896*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1896*FLEN/8, x5, x2, x6) + +inst_978: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x027 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3c4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf427; op2val:0xfbc4; + valaddr_reg:x4; val_offset:1898*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1898*FLEN/8, x5, x2, x6) + +inst_979: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x811d; op2val:0xfbfa; + valaddr_reg:x4; val_offset:1900*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1900*FLEN/8, x5, x2, x6) + +inst_980: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x027 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf427; op2val:0xfbfa; + valaddr_reg:x4; val_offset:1902*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1902*FLEN/8, x5, x2, x6) + +inst_981: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d and fs2 == 1 and fe2 == 0x1a and fm2 == 0x300 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x811d; op2val:0xeb00; + valaddr_reg:x4; val_offset:1904*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1904*FLEN/8, x5, x2, x6) + +inst_982: +// fs1 == 1 and fe1 == 0x19 and fm1 == 0x2a6 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x300 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xe6a6; op2val:0xeb00; + valaddr_reg:x4; val_offset:1906*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1906*FLEN/8, x5, x2, x6) + +inst_983: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3df and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x811d; op2val:0x83df; + valaddr_reg:x4; val_offset:1908*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1908*FLEN/8, x5, x2, x6) + +inst_984: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3df and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83df; op2val:0x811d; + valaddr_reg:x4; val_offset:1910*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1910*FLEN/8, x5, x2, x6) + +inst_985: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x811d; op2val:0xf0; + valaddr_reg:x4; val_offset:1912*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1912*FLEN/8, x5, x2, x6) + +inst_986: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x2cf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xbecf; op2val:0xf0; + valaddr_reg:x4; val_offset:1914*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1914*FLEN/8, x5, x2, x6) + +inst_987: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2cf and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xbecf; + valaddr_reg:x4; val_offset:1916*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1916*FLEN/8, x5, x2, x6) + +inst_988: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2cf and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x811d; op2val:0xbecf; + valaddr_reg:x4; val_offset:1918*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1918*FLEN/8, x5, x2, x6) + +inst_989: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3df and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83df; op2val:0x704c; + valaddr_reg:x4; val_offset:1920*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1920*FLEN/8, x5, x2, x6) + +inst_990: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x1c5 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xedc5; op2val:0x704c; + valaddr_reg:x4; val_offset:1922*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1922*FLEN/8, x5, x2, x6) + +inst_991: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3df and fs2 == 1 and fe2 == 0x1b and fm2 == 0x1c5 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83df; op2val:0xedc5; + valaddr_reg:x4; val_offset:1924*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1924*FLEN/8, x5, x2, x6) + +inst_992: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3df and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3df and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83df; op2val:0x83df; + valaddr_reg:x4; val_offset:1926*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1926*FLEN/8, x5, x2, x6) + +inst_993: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3df and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3ec and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83df; op2val:0x77ec; + valaddr_reg:x4; val_offset:1928*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1928*FLEN/8, x5, x2, x6) + +inst_994: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x337 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3ec and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb37; op2val:0x77ec; + valaddr_reg:x4; val_offset:1930*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1930*FLEN/8, x5, x2, x6) + +inst_995: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3df and fs2 == 1 and fe2 == 0x1e and fm2 == 0x337 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83df; op2val:0xfb37; + valaddr_reg:x4; val_offset:1932*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1932*FLEN/8, x5, x2, x6) + +inst_996: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3df and fs2 == 0 and fe2 == 0x1b and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83df; op2val:0x6e01; + valaddr_reg:x4; val_offset:1934*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1934*FLEN/8, x5, x2, x6) + +inst_997: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x1c5 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xedc5; op2val:0x6e01; + valaddr_reg:x4; val_offset:1936*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1936*FLEN/8, x5, x2, x6) + +inst_998: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3df and fs2 == 0 and fe2 == 0x1e and fm2 == 0x218 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83df; op2val:0x7a18; + valaddr_reg:x4; val_offset:1938*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1938*FLEN/8, x5, x2, x6) + +inst_999: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x337 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x218 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb37; op2val:0x7a18; + valaddr_reg:x4; val_offset:1940*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1940*FLEN/8, x5, x2, x6) + +inst_1000: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3df and fs2 == 0 and fe2 == 0x1c and fm2 == 0x351 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83df; op2val:0x7351; + valaddr_reg:x4; val_offset:1942*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1942*FLEN/8, x5, x2, x6) + +inst_1001: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x337 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x351 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb37; op2val:0x7351; + valaddr_reg:x4; val_offset:1944*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1944*FLEN/8, x5, x2, x6) + +inst_1002: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3df and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0e1 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83df; op2val:0xf0e1; + valaddr_reg:x4; val_offset:1946*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1946*FLEN/8, x5, x2, x6) + +inst_1003: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x1c5 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0e1 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xedc5; op2val:0xf0e1; + valaddr_reg:x4; val_offset:1948*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1948*FLEN/8, x5, x2, x6) + +inst_1004: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3df and fs2 == 1 and fe2 == 0x1e and fm2 == 0x066 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83df; op2val:0xf866; + valaddr_reg:x4; val_offset:1950*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1950*FLEN/8, x5, x2, x6) + +inst_1005: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x337 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x066 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb37; op2val:0xf866; + valaddr_reg:x4; val_offset:1952*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1952*FLEN/8, x5, x2, x6) + +inst_1006: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3df and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3c4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83df; op2val:0xfbc4; + valaddr_reg:x4; val_offset:1954*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1954*FLEN/8, x5, x2, x6) + +inst_1007: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x337 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3c4 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb37; op2val:0xfbc4; + valaddr_reg:x4; val_offset:1956*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1956*FLEN/8, x5, x2, x6) + +inst_1008: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3df and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83df; op2val:0xfbfa; + valaddr_reg:x4; val_offset:1958*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1958*FLEN/8, x5, x2, x6) + +inst_1009: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x337 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb37; op2val:0xfbfa; + valaddr_reg:x4; val_offset:1960*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1960*FLEN/8, x5, x2, x6) + +inst_1010: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3df and fs2 == 1 and fe2 == 0x1a and fm2 == 0x300 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83df; op2val:0xeb00; + valaddr_reg:x4; val_offset:1962*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1962*FLEN/8, x5, x2, x6) + +inst_1011: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x1c5 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x300 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xedc5; op2val:0xeb00; + valaddr_reg:x4; val_offset:1964*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1964*FLEN/8, x5, x2, x6) + +inst_1012: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3df and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83df; op2val:0xf0; + valaddr_reg:x4; val_offset:1966*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1966*FLEN/8, x5, x2, x6) + +inst_1013: +// fs1 == 1 and fe1 == 0x11 and fm1 == 0x1e9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xc5e9; op2val:0xf0; + valaddr_reg:x4; val_offset:1968*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1968*FLEN/8, x5, x2, x6) + +inst_1014: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1e9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xc5e9; + valaddr_reg:x4; val_offset:1970*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1970*FLEN/8, x5, x2, x6) + +inst_1015: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3df and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1e9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x83df; op2val:0xc5e9; + valaddr_reg:x4; val_offset:1972*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1972*FLEN/8, x5, x2, x6) + +inst_1016: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x704c; + valaddr_reg:x4; val_offset:1974*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1974*FLEN/8, x5, x2, x6) + +inst_1017: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xf0; + valaddr_reg:x4; val_offset:1976*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1976*FLEN/8, x5, x2, x6) + +inst_1018: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3ec and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x77ec; + valaddr_reg:x4; val_offset:1978*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1978*FLEN/8, x5, x2, x6) + +inst_1019: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x6e01; + valaddr_reg:x4; val_offset:1980*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1980*FLEN/8, x5, x2, x6) + +inst_1020: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x218 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x7a18; + valaddr_reg:x4; val_offset:1982*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1982*FLEN/8, x5, x2, x6) + +inst_1021: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x351 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x7351; + valaddr_reg:x4; val_offset:1984*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1984*FLEN/8, x5, x2, x6) + +inst_1022: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0e1 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xf0e1; + valaddr_reg:x4; val_offset:1986*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1986*FLEN/8, x5, x2, x6) + +inst_1023: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x066 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xf866; + valaddr_reg:x4; val_offset:1988*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1988*FLEN/8, x5, x2, x6) + +inst_1024: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3c4 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xfbc4; + valaddr_reg:x4; val_offset:1990*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1990*FLEN/8, x5, x2, x6) + +inst_1025: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xfbfa; + valaddr_reg:x4; val_offset:1992*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1992*FLEN/8, x5, x2, x6) + +inst_1026: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x300 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xeb00; + valaddr_reg:x4; val_offset:1994*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1994*FLEN/8, x5, x2, x6) + +inst_1027: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x30d; + valaddr_reg:x4; val_offset:1996*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1996*FLEN/8, x5, x2, x6) + +inst_1028: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x29a; + valaddr_reg:x4; val_offset:1998*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 1998*FLEN/8, x5, x2, x6) + +inst_1029: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x357; + valaddr_reg:x4; val_offset:2000*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 2000*FLEN/8, x5, x2, x6) + +inst_1030: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x1c8; + valaddr_reg:x4; val_offset:2002*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 2002*FLEN/8, x5, x2, x6) + +inst_1031: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x39a; + valaddr_reg:x4; val_offset:2004*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 2004*FLEN/8, x5, x2, x6) + +inst_1032: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fa and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x82fa; + valaddr_reg:x4; val_offset:2006*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 2006*FLEN/8, x5, x2, x6) + +inst_1033: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d8 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x80d8; + valaddr_reg:x4; val_offset:2008*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 2008*FLEN/8, x5, x2, x6) + +inst_1034: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x8244; + valaddr_reg:x4; val_offset:2010*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 2010*FLEN/8, x5, x2, x6) + +inst_1035: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x811d; + valaddr_reg:x4; val_offset:2012*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 2012*FLEN/8, x5, x2, x6) + +inst_1036: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3df and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x83df; + valaddr_reg:x4; val_offset:2014*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 2014*FLEN/8, x5, x2, x6) + +inst_1037: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3ec and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x704c; op2val:0x77ec; + valaddr_reg:x4; val_offset:2016*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 2016*FLEN/8, x5, x2, x6) + +inst_1038: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x256 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x6a56; op2val:0x7bff; + valaddr_reg:x4; val_offset:2018*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 2018*FLEN/8, x5, x2, x6) + +inst_1039: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3ec and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x77ec; + valaddr_reg:x4; val_offset:2020*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 2020*FLEN/8, x5, x2, x6) + +inst_1040: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x1da and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x65da; op2val:0x7bff; + valaddr_reg:x4; val_offset:2022*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 2022*FLEN/8, x5, x2, x6) + +inst_1041: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x066 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmax.h ; op1:x30; op2:x29; dest:x31; op1val:0x704c; op2val:0xf866; + valaddr_reg:x4; val_offset:2024*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmax.h, x31, x30, x29, 0, 0, x4, 2024*FLEN/8, x5, x2, x6) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(28748,32,FLEN) +NAN_BOXED(28748,32,FLEN) +NAN_BOXED(28748,32,FLEN) +NAN_BOXED(28748,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(27222,32,FLEN) +NAN_BOXED(27222,32,FLEN) +NAN_BOXED(27222,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(30700,32,FLEN) +NAN_BOXED(28748,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(28748,32,FLEN) +NAN_BOXED(28161,32,FLEN) +NAN_BOXED(28161,32,FLEN) +NAN_BOXED(28748,32,FLEN) +NAN_BOXED(28748,32,FLEN) +NAN_BOXED(31256,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(27872,32,FLEN) +NAN_BOXED(27872,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(31256,32,FLEN) +NAN_BOXED(28748,32,FLEN) +NAN_BOXED(29521,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(26074,32,FLEN) +test_dataset_1: +NAN_BOXED(26074,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(29521,32,FLEN) +NAN_BOXED(28748,32,FLEN) +NAN_BOXED(61665,16,FLEN) +NAN_BOXED(61665,16,FLEN) +NAN_BOXED(28748,32,FLEN) +NAN_BOXED(28748,32,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(60171,16,FLEN) +NAN_BOXED(60171,16,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(63590,16,FLEN) +NAN_BOXED(28748,32,FLEN) +NAN_BOXED(64452,16,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(60983,16,FLEN) +NAN_BOXED(60983,16,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(64452,16,FLEN) +NAN_BOXED(28748,32,FLEN) +NAN_BOXED(64506,16,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(61026,16,FLEN) +NAN_BOXED(61026,16,FLEN) +NAN_BOXED(31743,32,FLEN) +test_dataset_2: +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(64506,16,FLEN) +NAN_BOXED(28748,16,FLEN) +NAN_BOXED(60160,16,FLEN) +NAN_BOXED(60160,16,FLEN) +NAN_BOXED(28748,16,FLEN) +NAN_BOXED(28748,16,FLEN) +NAN_BOXED(781,16,FLEN) +NAN_BOXED(1476,16,FLEN) +NAN_BOXED(27788,16,FLEN) +NAN_BOXED(27788,16,FLEN) +NAN_BOXED(1476,16,FLEN) +NAN_BOXED(1476,16,FLEN) +NAN_BOXED(781,16,FLEN) +NAN_BOXED(28748,16,FLEN) +NAN_BOXED(1476,16,FLEN) +NAN_BOXED(28748,16,FLEN) +NAN_BOXED(666,16,FLEN) +NAN_BOXED(1476,16,FLEN) +NAN_BOXED(27587,16,FLEN) +NAN_BOXED(27587,16,FLEN) +NAN_BOXED(1476,16,FLEN) +NAN_BOXED(1476,16,FLEN) +NAN_BOXED(666,16,FLEN) +NAN_BOXED(28748,16,FLEN) +NAN_BOXED(855,16,FLEN) +NAN_BOXED(1476,16,FLEN) +NAN_BOXED(27898,16,FLEN) +NAN_BOXED(27898,16,FLEN) +NAN_BOXED(1476,16,FLEN) +NAN_BOXED(1476,16,FLEN) +NAN_BOXED(855,16,FLEN) +NAN_BOXED(28748,16,FLEN) +NAN_BOXED(456,16,FLEN) +NAN_BOXED(1476,16,FLEN) +NAN_BOXED(26959,16,FLEN) +NAN_BOXED(26959,16,FLEN) +NAN_BOXED(1476,16,FLEN) +NAN_BOXED(1476,16,FLEN) +NAN_BOXED(456,16,FLEN) +NAN_BOXED(28748,16,FLEN) +NAN_BOXED(922,16,FLEN) +NAN_BOXED(1476,16,FLEN) +NAN_BOXED(27998,16,FLEN) +NAN_BOXED(27998,16,FLEN) +NAN_BOXED(1476,16,FLEN) +NAN_BOXED(1476,16,FLEN) +NAN_BOXED(922,16,FLEN) +NAN_BOXED(28748,16,FLEN) +NAN_BOXED(33530,16,FLEN) +NAN_BOXED(1476,16,FLEN) +NAN_BOXED(60527,16,FLEN) +NAN_BOXED(60527,16,FLEN) +NAN_BOXED(1476,16,FLEN) +NAN_BOXED(1476,16,FLEN) +NAN_BOXED(33530,16,FLEN) +NAN_BOXED(28748,16,FLEN) +NAN_BOXED(32984,16,FLEN) +NAN_BOXED(1476,16,FLEN) +NAN_BOXED(58637,16,FLEN) +NAN_BOXED(58637,16,FLEN) +NAN_BOXED(1476,16,FLEN) +NAN_BOXED(1476,16,FLEN) +NAN_BOXED(32984,16,FLEN) +NAN_BOXED(28748,16,FLEN) +NAN_BOXED(33348,16,FLEN) +NAN_BOXED(1476,16,FLEN) +NAN_BOXED(60098,16,FLEN) +NAN_BOXED(60098,16,FLEN) +NAN_BOXED(1476,16,FLEN) +NAN_BOXED(1476,16,FLEN) +NAN_BOXED(33348,16,FLEN) +NAN_BOXED(28748,16,FLEN) +NAN_BOXED(33053,16,FLEN) +NAN_BOXED(1476,16,FLEN) +NAN_BOXED(59046,16,FLEN) +NAN_BOXED(59046,16,FLEN) +NAN_BOXED(1476,16,FLEN) +NAN_BOXED(1476,16,FLEN) +NAN_BOXED(33053,16,FLEN) +NAN_BOXED(28748,16,FLEN) +NAN_BOXED(33759,16,FLEN) +NAN_BOXED(1476,16,FLEN) +NAN_BOXED(60869,16,FLEN) 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+NAN_BOXED(31256,16,FLEN) +NAN_BOXED(33759,16,FLEN) +NAN_BOXED(29521,16,FLEN) +NAN_BOXED(64311,16,FLEN) +NAN_BOXED(29521,16,FLEN) +NAN_BOXED(33759,16,FLEN) +NAN_BOXED(61665,16,FLEN) +NAN_BOXED(60869,16,FLEN) +NAN_BOXED(61665,16,FLEN) +NAN_BOXED(33759,16,FLEN) +NAN_BOXED(63590,16,FLEN) +NAN_BOXED(64311,16,FLEN) +NAN_BOXED(63590,16,FLEN) +NAN_BOXED(33759,16,FLEN) +NAN_BOXED(64452,16,FLEN) +NAN_BOXED(64311,16,FLEN) +NAN_BOXED(64452,16,FLEN) +NAN_BOXED(33759,16,FLEN) +NAN_BOXED(64506,16,FLEN) +NAN_BOXED(64311,16,FLEN) +NAN_BOXED(64506,16,FLEN) +NAN_BOXED(33759,16,FLEN) +NAN_BOXED(60160,16,FLEN) +NAN_BOXED(60869,16,FLEN) +NAN_BOXED(60160,16,FLEN) +NAN_BOXED(33759,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(50665,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(50665,16,FLEN) +NAN_BOXED(33759,16,FLEN) +NAN_BOXED(50665,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(28748,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(30700,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(28161,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(31256,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(29521,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(61665,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(63590,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(64452,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(64506,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(60160,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(781,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(666,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(855,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(456,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(922,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(33530,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(32984,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(33348,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(33053,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(33759,16,FLEN) +NAN_BOXED(28748,16,FLEN) +NAN_BOXED(30700,16,FLEN) +NAN_BOXED(27222,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30700,16,FLEN) +NAN_BOXED(26074,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(28748,16,FLEN) +NAN_BOXED(63590,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x3_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x3_1: + .fill 36*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_0: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_1: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_2: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_3: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_4: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_5: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_6: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_7: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fmin_b1-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fmin_b1-01.S new file mode 100644 index 000000000..a7b8468a7 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fmin_b1-01.S @@ -0,0 +1,5929 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 05:46:50 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fmin.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fmin.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fmin_b1 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fmin_b1) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x7,signature_x7_1) + +inst_0: +// rs1 == rs2 == rd, rs1==x26, rs2==x26, rd==x26,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x26; op2:x26; dest:x26; op1val:0x0; op2val:0x0; + valaddr_reg:x3; val_offset:0*FLEN/8; fcsr: 0; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP_NRM(fmin.h, x26, x26, x26, 0, 0, x3, 0*FLEN/8, x9, x7, x13) + +inst_1: +// rs1 == rd != rs2, rs1==x20, rs2==x0, rd==x20,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x20; op2:x0; dest:x20; op1val:0x0; op2val:0x0; + valaddr_reg:x3; val_offset:2*FLEN/8; fcsr: 0; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP_NRM(fmin.h, x20, x20, x0, 0, 0, x3, 2*FLEN/8, x9, x7, x13) + +inst_2: +// rs2 == rd != rs1, rs1==x25, rs2==x8, rd==x8,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x25; op2:x8; dest:x8; op1val:0x0; op2val:0x1; + valaddr_reg:x3; val_offset:4*FLEN/8; fcsr: 0; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP_NRM(fmin.h, x8, x25, x8, 0, 0, x3, 4*FLEN/8, x9, x7, x13) + +inst_3: +// rs1 == rs2 != rd, rs1==x27, rs2==x27, rd==x15,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x27; op2:x27; dest:x15; op1val:0x0; op2val:0x0; + valaddr_reg:x3; val_offset:6*FLEN/8; fcsr: 0; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP_NRM(fmin.h, x15, x27, x27, 0, 0, x3, 6*FLEN/8, x9, x7, x13) + +inst_4: +// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==x21, rs2==x12, rd==x31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x21; op2:x12; dest:x31; op1val:0x0; op2val:0x2; + valaddr_reg:x3; val_offset:8*FLEN/8; fcsr: 0; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x21, x12, 0, 0, x3, 8*FLEN/8, x9, x7, x13) + +inst_5: +// rs1==x5, rs2==x2, rd==x16,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x5; op2:x2; dest:x16; op1val:0x0; op2val:0x83fe; + valaddr_reg:x3; val_offset:10*FLEN/8; fcsr: 0; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP_NRM(fmin.h, x16, x5, x2, 0, 0, x3, 10*FLEN/8, x9, x7, x13) + +inst_6: +// rs1==x2, rs2==x11, rd==x0,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x2; op2:x11; dest:x0; op1val:0x0; op2val:0x3ff; + valaddr_reg:x3; val_offset:12*FLEN/8; fcsr: 0; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP_NRM(fmin.h, x0, x2, x11, 0, 0, x3, 12*FLEN/8, x9, x7, x13) + +inst_7: +// rs1==x15, rs2==x22, rd==x11,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x15; op2:x22; dest:x11; op1val:0x0; op2val:0x83ff; + valaddr_reg:x3; val_offset:14*FLEN/8; fcsr: 0; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP_NRM(fmin.h, x11, x15, x22, 0, 0, x3, 14*FLEN/8, x9, x7, x13) + +inst_8: +// rs1==x24, rs2==x4, rd==x10,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x24; op2:x4; dest:x10; op1val:0x0; op2val:0x400; + valaddr_reg:x3; val_offset:16*FLEN/8; fcsr: 0; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP_NRM(fmin.h, x10, x24, x4, 0, 0, x3, 16*FLEN/8, x9, x7, x13) + +inst_9: +// rs1==x0, rs2==x31, rd==x22,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x0; op2:x31; dest:x22; op1val:0x0; op2val:0x8400; + valaddr_reg:x3; val_offset:18*FLEN/8; fcsr: 0; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP_NRM(fmin.h, x22, x0, x31, 0, 0, x3, 18*FLEN/8, x9, x7, x13) + +inst_10: +// rs1==x8, rs2==x23, rd==x12,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x8; op2:x23; dest:x12; op1val:0x0; op2val:0x401; + valaddr_reg:x3; val_offset:20*FLEN/8; fcsr: 0; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP_NRM(fmin.h, x12, x8, x23, 0, 0, x3, 20*FLEN/8, x9, x7, x13) + +inst_11: +// rs1==x22, rs2==x29, rd==x28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x22; op2:x29; dest:x28; op1val:0x0; op2val:0x8455; + valaddr_reg:x3; val_offset:22*FLEN/8; fcsr: 0; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP_NRM(fmin.h, x28, x22, x29, 0, 0, x3, 22*FLEN/8, x9, x7, x13) + +inst_12: +// rs1==x6, rs2==x1, rd==x18,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x6; op2:x1; dest:x18; op1val:0x0; op2val:0x7bff; + valaddr_reg:x3; val_offset:24*FLEN/8; fcsr: 0; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP_NRM(fmin.h, x18, x6, x1, 0, 0, x3, 24*FLEN/8, x9, x7, x13) +RVTEST_VALBASEUPD(x2,test_dataset_1) + +inst_13: +// rs1==x9, rs2==x6, rd==x25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x9; op2:x6; dest:x25; op1val:0x0; op2val:0xfbff; + valaddr_reg:x2; val_offset:0*FLEN/8; fcsr: 0; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP_NRM(fmin.h, x25, x9, x6, 0, 0, x2, 0*FLEN/8, x15, x7, x13) + +inst_14: +// rs1==x28, rs2==x20, rd==x29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x28; op2:x20; dest:x29; op1val:0x0; op2val:0x7c00; + valaddr_reg:x2; val_offset:2*FLEN/8; fcsr: 0; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP_NRM(fmin.h, x29, x28, x20, 0, 0, x2, 2*FLEN/8, x15, x7, x13) + +inst_15: +// rs1==x23, rs2==x10, rd==x3,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x23; op2:x10; dest:x3; op1val:0x0; op2val:0xfc00; + valaddr_reg:x2; val_offset:4*FLEN/8; fcsr: 0; + correctval:??; testreg:x13 +*/ +TEST_FPRR_OP_NRM(fmin.h, x3, x23, x10, 0, 0, x2, 4*FLEN/8, x15, x7, x13) + +inst_16: +// rs1==x16, rs2==x18, rd==x6,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x16; op2:x18; dest:x6; op1val:0x0; op2val:0x7e00; + valaddr_reg:x2; val_offset:6*FLEN/8; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP_NRM(fmin.h, x6, x16, x18, 0, 0, x2, 6*FLEN/8, x15, x7, x8) + +inst_17: +// rs1==x12, rs2==x14, rd==x19,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x12; op2:x14; dest:x19; op1val:0x0; op2val:0xfe00; + valaddr_reg:x2; val_offset:8*FLEN/8; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP_NRM(fmin.h, x19, x12, x14, 0, 0, x2, 8*FLEN/8, x15, x7, x8) +RVTEST_SIGBASE(x6,signature_x6_0) + +inst_18: +// rs1==x13, rs2==x30, rd==x7,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x13; op2:x30; dest:x7; op1val:0x0; op2val:0x7e01; + valaddr_reg:x2; val_offset:10*FLEN/8; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP_NRM(fmin.h, x7, x13, x30, 0, 0, x2, 10*FLEN/8, x15, x6, x8) + +inst_19: +// rs1==x11, rs2==x5, rd==x1,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x11; op2:x5; dest:x1; op1val:0x0; op2val:0xfe55; + valaddr_reg:x2; val_offset:12*FLEN/8; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP_NRM(fmin.h, x1, x11, x5, 0, 0, x2, 12*FLEN/8, x15, x6, x8) + +inst_20: +// rs1==x10, rs2==x19, rd==x17,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x10; op2:x19; dest:x17; op1val:0x0; op2val:0x7c01; + valaddr_reg:x2; val_offset:14*FLEN/8; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP_NRM(fmin.h, x17, x10, x19, 0, 0, x2, 14*FLEN/8, x15, x6, x8) + +inst_21: +// rs1==x3, rs2==x28, rd==x4,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x3; op2:x28; dest:x4; op1val:0x0; op2val:0xfd55; + valaddr_reg:x2; val_offset:16*FLEN/8; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP_NRM(fmin.h, x4, x3, x28, 0, 0, x2, 16*FLEN/8, x15, x6, x8) + +inst_22: +// rs1==x31, rs2==x24, rd==x14,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x31; op2:x24; dest:x14; op1val:0x0; op2val:0x3c00; + valaddr_reg:x2; val_offset:18*FLEN/8; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP_NRM(fmin.h, x14, x31, x24, 0, 0, x2, 18*FLEN/8, x15, x6, x8) +RVTEST_VALBASEUPD(x10,test_dataset_2) + +inst_23: +// rs1==x18, rs2==x15, rd==x23,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x18; op2:x15; dest:x23; op1val:0x0; op2val:0xbc00; + valaddr_reg:x10; val_offset:0*FLEN/8; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP_NRM(fmin.h, x23, x18, x15, 0, 0, x10, 0*FLEN/8, x11, x6, x8) + +inst_24: +// rs1==x17, rs2==x25, rd==x2,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x17; op2:x25; dest:x2; op1val:0x8000; op2val:0x0; + valaddr_reg:x10; val_offset:2*FLEN/8; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP_NRM(fmin.h, x2, x17, x25, 0, 0, x10, 2*FLEN/8, x11, x6, x8) + +inst_25: +// rs1==x30, rs2==x17, rd==x21,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x17; dest:x21; op1val:0x8000; op2val:0x8000; + valaddr_reg:x10; val_offset:4*FLEN/8; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP_NRM(fmin.h, x21, x30, x17, 0, 0, x10, 4*FLEN/8, x11, x6, x8) + +inst_26: +// rs1==x19, rs2==x9, rd==x13,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x19; op2:x9; dest:x13; op1val:0x8000; op2val:0x1; + valaddr_reg:x10; val_offset:6*FLEN/8; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP_NRM(fmin.h, x13, x19, x9, 0, 0, x10, 6*FLEN/8, x11, x6, x8) + +inst_27: +// rs1==x7, rs2==x16, rd==x24,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x7; op2:x16; dest:x24; op1val:0x8000; op2val:0x8001; + valaddr_reg:x10; val_offset:8*FLEN/8; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP_NRM(fmin.h, x24, x7, x16, 0, 0, x10, 8*FLEN/8, x11, x6, x8) + +inst_28: +// rs1==x14, rs2==x7, rd==x27,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x14; op2:x7; dest:x27; op1val:0x8000; op2val:0x2; + valaddr_reg:x10; val_offset:10*FLEN/8; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP_NRM(fmin.h, x27, x14, x7, 0, 0, x10, 10*FLEN/8, x11, x6, x8) + +inst_29: +// rs1==x29, rs2==x13, rd==x9,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x29; op2:x13; dest:x9; op1val:0x8000; op2val:0x83fe; + valaddr_reg:x10; val_offset:12*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x9, x29, x13, 0, 0, x10, 12*FLEN/8, x11, x6, x2) + +inst_30: +// rs1==x1, rs2==x21, rd==x5,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x1; op2:x21; dest:x5; op1val:0x8000; op2val:0x3ff; + valaddr_reg:x10; val_offset:14*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x5, x1, x21, 0, 0, x10, 14*FLEN/8, x11, x6, x2) + +inst_31: +// rs1==x4, rs2==x3, rd==x30,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x4; op2:x3; dest:x30; op1val:0x8000; op2val:0x83ff; + valaddr_reg:x10; val_offset:16*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x30, x4, x3, 0, 0, x10, 16*FLEN/8, x11, x6, x2) + +inst_32: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x400; + valaddr_reg:x10; val_offset:18*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 18*FLEN/8, x11, x6, x2) + +inst_33: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8400; + valaddr_reg:x10; val_offset:20*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 20*FLEN/8, x11, x6, x2) + +inst_34: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x401; + valaddr_reg:x10; val_offset:22*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 22*FLEN/8, x11, x6, x2) + +inst_35: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8455; + valaddr_reg:x10; val_offset:24*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 24*FLEN/8, x11, x6, x2) + +inst_36: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x7bff; + valaddr_reg:x10; val_offset:26*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 26*FLEN/8, x11, x6, x2) + +inst_37: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xfbff; + valaddr_reg:x10; val_offset:28*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 28*FLEN/8, x11, x6, x2) + +inst_38: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x7c00; + valaddr_reg:x10; val_offset:30*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 30*FLEN/8, x11, x6, x2) + +inst_39: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xfc00; + valaddr_reg:x10; val_offset:32*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 32*FLEN/8, x11, x6, x2) + +inst_40: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x7e00; + valaddr_reg:x10; val_offset:34*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 34*FLEN/8, x11, x6, x2) + +inst_41: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xfe00; + valaddr_reg:x10; val_offset:36*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 36*FLEN/8, x11, x6, x2) + +inst_42: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x7e01; + valaddr_reg:x10; val_offset:38*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 38*FLEN/8, x11, x6, x2) + +inst_43: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xfe55; + valaddr_reg:x10; val_offset:40*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 40*FLEN/8, x11, x6, x2) + +inst_44: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x7c01; + valaddr_reg:x10; val_offset:42*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 42*FLEN/8, x11, x6, x2) + +inst_45: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xfd55; + valaddr_reg:x10; val_offset:44*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 44*FLEN/8, x11, x6, x2) + +inst_46: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x3c00; + valaddr_reg:x10; val_offset:46*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 46*FLEN/8, x11, x6, x2) + +inst_47: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xbc00; + valaddr_reg:x10; val_offset:48*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 48*FLEN/8, x11, x6, x2) + +inst_48: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x0; + valaddr_reg:x10; val_offset:50*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 50*FLEN/8, x11, x6, x2) + +inst_49: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x8000; + valaddr_reg:x10; val_offset:52*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 52*FLEN/8, x11, x6, x2) + +inst_50: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x1; + valaddr_reg:x10; val_offset:54*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 54*FLEN/8, x11, x6, x2) + +inst_51: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x8001; + valaddr_reg:x10; val_offset:56*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 56*FLEN/8, x11, x6, x2) + +inst_52: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x2; + valaddr_reg:x10; val_offset:58*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 58*FLEN/8, x11, x6, x2) + +inst_53: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x83fe; + valaddr_reg:x10; val_offset:60*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 60*FLEN/8, x11, x6, x2) + +inst_54: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x3ff; + valaddr_reg:x10; val_offset:62*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 62*FLEN/8, x11, x6, x2) + +inst_55: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x83ff; + valaddr_reg:x10; val_offset:64*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 64*FLEN/8, x11, x6, x2) + +inst_56: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x400; + valaddr_reg:x10; val_offset:66*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 66*FLEN/8, x11, x6, x2) + +inst_57: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x8400; + valaddr_reg:x10; val_offset:68*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 68*FLEN/8, x11, x6, x2) + +inst_58: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x401; + valaddr_reg:x10; val_offset:70*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 70*FLEN/8, x11, x6, x2) + +inst_59: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x8455; + valaddr_reg:x10; val_offset:72*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 72*FLEN/8, x11, x6, x2) + +inst_60: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7bff; + valaddr_reg:x10; val_offset:74*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 74*FLEN/8, x11, x6, x2) + +inst_61: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xfbff; + valaddr_reg:x10; val_offset:76*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 76*FLEN/8, x11, x6, x2) + +inst_62: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7c00; + valaddr_reg:x10; val_offset:78*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 78*FLEN/8, x11, x6, x2) + +inst_63: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xfc00; + valaddr_reg:x10; val_offset:80*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 80*FLEN/8, x11, x6, x2) + +inst_64: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7e00; + valaddr_reg:x10; val_offset:82*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 82*FLEN/8, x11, x6, x2) + +inst_65: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xfe00; + valaddr_reg:x10; val_offset:84*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 84*FLEN/8, x11, x6, x2) + +inst_66: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7e01; + valaddr_reg:x10; val_offset:86*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 86*FLEN/8, x11, x6, x2) + +inst_67: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xfe55; + valaddr_reg:x10; val_offset:88*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 88*FLEN/8, x11, x6, x2) + +inst_68: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7c01; + valaddr_reg:x10; val_offset:90*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 90*FLEN/8, x11, x6, x2) + +inst_69: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xfd55; + valaddr_reg:x10; val_offset:92*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 92*FLEN/8, x11, x6, x2) + +inst_70: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x3c00; + valaddr_reg:x10; val_offset:94*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 94*FLEN/8, x11, x6, x2) + +inst_71: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xbc00; + valaddr_reg:x10; val_offset:96*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 96*FLEN/8, x11, x6, x2) + +inst_72: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x0; + valaddr_reg:x10; val_offset:98*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 98*FLEN/8, x11, x6, x2) + +inst_73: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8000; + valaddr_reg:x10; val_offset:100*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 100*FLEN/8, x11, x6, x2) + +inst_74: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x1; + valaddr_reg:x10; val_offset:102*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 102*FLEN/8, x11, x6, x2) + +inst_75: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8001; + valaddr_reg:x10; val_offset:104*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 104*FLEN/8, x11, x6, x2) + +inst_76: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x2; + valaddr_reg:x10; val_offset:106*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 106*FLEN/8, x11, x6, x2) + +inst_77: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x83fe; + valaddr_reg:x10; val_offset:108*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 108*FLEN/8, x11, x6, x2) + +inst_78: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x3ff; + valaddr_reg:x10; val_offset:110*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 110*FLEN/8, x11, x6, x2) + +inst_79: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x83ff; + valaddr_reg:x10; val_offset:112*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 112*FLEN/8, x11, x6, x2) + +inst_80: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x400; + valaddr_reg:x10; val_offset:114*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 114*FLEN/8, x11, x6, x2) + +inst_81: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8400; + valaddr_reg:x10; val_offset:116*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 116*FLEN/8, x11, x6, x2) + +inst_82: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x401; + valaddr_reg:x10; val_offset:118*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 118*FLEN/8, x11, x6, x2) + +inst_83: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8455; + valaddr_reg:x10; val_offset:120*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 120*FLEN/8, x11, x6, x2) + +inst_84: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x7bff; + valaddr_reg:x10; val_offset:122*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 122*FLEN/8, x11, x6, x2) + +inst_85: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xfbff; + valaddr_reg:x10; val_offset:124*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 124*FLEN/8, x11, x6, x2) + +inst_86: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x7c00; + valaddr_reg:x10; val_offset:126*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 126*FLEN/8, x11, x6, x2) + +inst_87: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xfc00; + valaddr_reg:x10; val_offset:128*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 128*FLEN/8, x11, x6, x2) + +inst_88: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x7e00; + valaddr_reg:x10; val_offset:130*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 130*FLEN/8, x11, x6, x2) + +inst_89: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xfe00; + valaddr_reg:x10; val_offset:132*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 132*FLEN/8, x11, x6, x2) + +inst_90: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x7e01; + valaddr_reg:x10; val_offset:134*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 134*FLEN/8, x11, x6, x2) + +inst_91: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xfe55; + valaddr_reg:x10; val_offset:136*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 136*FLEN/8, x11, x6, x2) + +inst_92: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x7c01; + valaddr_reg:x10; val_offset:138*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 138*FLEN/8, x11, x6, x2) + +inst_93: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xfd55; + valaddr_reg:x10; val_offset:140*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 140*FLEN/8, x11, x6, x2) + +inst_94: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x3c00; + valaddr_reg:x10; val_offset:142*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 142*FLEN/8, x11, x6, x2) + +inst_95: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xbc00; + valaddr_reg:x10; val_offset:144*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 144*FLEN/8, x11, x6, x2) + +inst_96: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x0; + valaddr_reg:x10; val_offset:146*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 146*FLEN/8, x11, x6, x2) + +inst_97: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x8000; + valaddr_reg:x10; val_offset:148*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 148*FLEN/8, x11, x6, x2) + +inst_98: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x1; + valaddr_reg:x10; val_offset:150*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 150*FLEN/8, x11, x6, x2) + +inst_99: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x8001; + valaddr_reg:x10; val_offset:152*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 152*FLEN/8, x11, x6, x2) + +inst_100: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x2; + valaddr_reg:x10; val_offset:154*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 154*FLEN/8, x11, x6, x2) + +inst_101: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x83fe; + valaddr_reg:x10; val_offset:156*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 156*FLEN/8, x11, x6, x2) + +inst_102: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x3ff; + valaddr_reg:x10; val_offset:158*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 158*FLEN/8, x11, x6, x2) + +inst_103: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x83ff; + valaddr_reg:x10; val_offset:160*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 160*FLEN/8, x11, x6, x2) + +inst_104: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x400; + valaddr_reg:x10; val_offset:162*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 162*FLEN/8, x11, x6, x2) + +inst_105: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x8400; + valaddr_reg:x10; val_offset:164*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 164*FLEN/8, x11, x6, x2) + +inst_106: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x401; + valaddr_reg:x10; val_offset:166*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 166*FLEN/8, x11, x6, x2) + +inst_107: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x8455; + valaddr_reg:x10; val_offset:168*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 168*FLEN/8, x11, x6, x2) + +inst_108: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x7bff; + valaddr_reg:x10; val_offset:170*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 170*FLEN/8, x11, x6, x2) + +inst_109: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xfbff; + valaddr_reg:x10; val_offset:172*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 172*FLEN/8, x11, x6, x2) + +inst_110: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x7c00; + valaddr_reg:x10; val_offset:174*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 174*FLEN/8, x11, x6, x2) + +inst_111: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xfc00; + valaddr_reg:x10; val_offset:176*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 176*FLEN/8, x11, x6, x2) + +inst_112: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x7e00; + valaddr_reg:x10; val_offset:178*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 178*FLEN/8, x11, x6, x2) + +inst_113: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xfe00; + valaddr_reg:x10; val_offset:180*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 180*FLEN/8, x11, x6, x2) + +inst_114: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x7e01; + valaddr_reg:x10; val_offset:182*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 182*FLEN/8, x11, x6, x2) + +inst_115: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xfe55; + valaddr_reg:x10; val_offset:184*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 184*FLEN/8, x11, x6, x2) + +inst_116: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x7c01; + valaddr_reg:x10; val_offset:186*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 186*FLEN/8, x11, x6, x2) + +inst_117: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xfd55; + valaddr_reg:x10; val_offset:188*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 188*FLEN/8, x11, x6, x2) + +inst_118: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x3c00; + valaddr_reg:x10; val_offset:190*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 190*FLEN/8, x11, x6, x2) + +inst_119: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xbc00; + valaddr_reg:x10; val_offset:192*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 192*FLEN/8, x11, x6, x2) + +inst_120: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x0; + valaddr_reg:x10; val_offset:194*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 194*FLEN/8, x11, x6, x2) + +inst_121: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x8000; + valaddr_reg:x10; val_offset:196*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 196*FLEN/8, x11, x6, x2) + +inst_122: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x1; + valaddr_reg:x10; val_offset:198*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 198*FLEN/8, x11, x6, x2) + +inst_123: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x8001; + valaddr_reg:x10; val_offset:200*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 200*FLEN/8, x11, x6, x2) + +inst_124: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x2; + valaddr_reg:x10; val_offset:202*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 202*FLEN/8, x11, x6, x2) + +inst_125: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x83fe; + valaddr_reg:x10; val_offset:204*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 204*FLEN/8, x11, x6, x2) + +inst_126: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x3ff; + valaddr_reg:x10; val_offset:206*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 206*FLEN/8, x11, x6, x2) + +inst_127: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x83ff; + valaddr_reg:x10; val_offset:208*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 208*FLEN/8, x11, x6, x2) + +inst_128: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x400; + valaddr_reg:x10; val_offset:210*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 210*FLEN/8, x11, x6, x2) + +inst_129: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x8400; + valaddr_reg:x10; val_offset:212*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 212*FLEN/8, x11, x6, x2) + +inst_130: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x401; + valaddr_reg:x10; val_offset:214*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 214*FLEN/8, x11, x6, x2) + +inst_131: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x8455; + valaddr_reg:x10; val_offset:216*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 216*FLEN/8, x11, x6, x2) + +inst_132: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x7bff; + valaddr_reg:x10; val_offset:218*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 218*FLEN/8, x11, x6, x2) + +inst_133: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xfbff; + valaddr_reg:x10; val_offset:220*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 220*FLEN/8, x11, x6, x2) + +inst_134: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x7c00; + valaddr_reg:x10; val_offset:222*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 222*FLEN/8, x11, x6, x2) + +inst_135: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xfc00; + valaddr_reg:x10; val_offset:224*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 224*FLEN/8, x11, x6, x2) + +inst_136: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x7e00; + valaddr_reg:x10; val_offset:226*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 226*FLEN/8, x11, x6, x2) + +inst_137: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xfe00; + valaddr_reg:x10; val_offset:228*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 228*FLEN/8, x11, x6, x2) + +inst_138: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x7e01; + valaddr_reg:x10; val_offset:230*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 230*FLEN/8, x11, x6, x2) + +inst_139: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xfe55; + valaddr_reg:x10; val_offset:232*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 232*FLEN/8, x11, x6, x2) + +inst_140: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x7c01; + valaddr_reg:x10; val_offset:234*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 234*FLEN/8, x11, x6, x2) + +inst_141: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xfd55; + valaddr_reg:x10; val_offset:236*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 236*FLEN/8, x11, x6, x2) + +inst_142: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x3c00; + valaddr_reg:x10; val_offset:238*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 238*FLEN/8, x11, x6, x2) + +inst_143: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xbc00; + valaddr_reg:x10; val_offset:240*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 240*FLEN/8, x11, x6, x2) + +inst_144: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x0; + valaddr_reg:x10; val_offset:242*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 242*FLEN/8, x11, x6, x2) + +inst_145: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x8000; + valaddr_reg:x10; val_offset:244*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 244*FLEN/8, x11, x6, x2) +RVTEST_SIGBASE(x6,signature_x6_1) + +inst_146: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x1; + valaddr_reg:x10; val_offset:246*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 246*FLEN/8, x11, x6, x2) + +inst_147: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x8001; + valaddr_reg:x10; val_offset:248*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 248*FLEN/8, x11, x6, x2) + +inst_148: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x2; + valaddr_reg:x10; val_offset:250*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 250*FLEN/8, x11, x6, x2) + +inst_149: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x83fe; + valaddr_reg:x10; val_offset:252*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 252*FLEN/8, x11, x6, x2) + +inst_150: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x3ff; + valaddr_reg:x10; val_offset:254*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 254*FLEN/8, x11, x6, x2) + +inst_151: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x83ff; + valaddr_reg:x10; val_offset:256*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 256*FLEN/8, x11, x6, x2) + +inst_152: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x400; + valaddr_reg:x10; val_offset:258*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 258*FLEN/8, x11, x6, x2) + +inst_153: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x8400; + valaddr_reg:x10; val_offset:260*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 260*FLEN/8, x11, x6, x2) + +inst_154: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x401; + valaddr_reg:x10; val_offset:262*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 262*FLEN/8, x11, x6, x2) + +inst_155: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x8455; + valaddr_reg:x10; val_offset:264*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 264*FLEN/8, x11, x6, x2) + +inst_156: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7bff; + valaddr_reg:x10; val_offset:266*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 266*FLEN/8, x11, x6, x2) + +inst_157: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xfbff; + valaddr_reg:x10; val_offset:268*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 268*FLEN/8, x11, x6, x2) + +inst_158: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7c00; + valaddr_reg:x10; val_offset:270*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 270*FLEN/8, x11, x6, x2) + +inst_159: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xfc00; + valaddr_reg:x10; val_offset:272*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 272*FLEN/8, x11, x6, x2) + +inst_160: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7e00; + valaddr_reg:x10; val_offset:274*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 274*FLEN/8, x11, x6, x2) + +inst_161: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xfe00; + valaddr_reg:x10; val_offset:276*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 276*FLEN/8, x11, x6, x2) + +inst_162: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7e01; + valaddr_reg:x10; val_offset:278*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 278*FLEN/8, x11, x6, x2) + +inst_163: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xfe55; + valaddr_reg:x10; val_offset:280*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 280*FLEN/8, x11, x6, x2) + +inst_164: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7c01; + valaddr_reg:x10; val_offset:282*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 282*FLEN/8, x11, x6, x2) + +inst_165: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xfd55; + valaddr_reg:x10; val_offset:284*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 284*FLEN/8, x11, x6, x2) + +inst_166: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x3c00; + valaddr_reg:x10; val_offset:286*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 286*FLEN/8, x11, x6, x2) + +inst_167: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xbc00; + valaddr_reg:x10; val_offset:288*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 288*FLEN/8, x11, x6, x2) + +inst_168: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x0; + valaddr_reg:x10; val_offset:290*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 290*FLEN/8, x11, x6, x2) + +inst_169: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8000; + valaddr_reg:x10; val_offset:292*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 292*FLEN/8, x11, x6, x2) + +inst_170: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x1; + valaddr_reg:x10; val_offset:294*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 294*FLEN/8, x11, x6, x2) + +inst_171: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8001; + valaddr_reg:x10; val_offset:296*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 296*FLEN/8, x11, x6, x2) + +inst_172: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x2; + valaddr_reg:x10; val_offset:298*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 298*FLEN/8, x11, x6, x2) + +inst_173: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x83fe; + valaddr_reg:x10; val_offset:300*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 300*FLEN/8, x11, x6, x2) + +inst_174: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x3ff; + valaddr_reg:x10; val_offset:302*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 302*FLEN/8, x11, x6, x2) + +inst_175: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x83ff; + valaddr_reg:x10; val_offset:304*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 304*FLEN/8, x11, x6, x2) + +inst_176: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x400; + valaddr_reg:x10; val_offset:306*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 306*FLEN/8, x11, x6, x2) + +inst_177: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8400; + valaddr_reg:x10; val_offset:308*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 308*FLEN/8, x11, x6, x2) + +inst_178: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x401; + valaddr_reg:x10; val_offset:310*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 310*FLEN/8, x11, x6, x2) + +inst_179: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8455; + valaddr_reg:x10; val_offset:312*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 312*FLEN/8, x11, x6, x2) + +inst_180: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x7bff; + valaddr_reg:x10; val_offset:314*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 314*FLEN/8, x11, x6, x2) + +inst_181: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xfbff; + valaddr_reg:x10; val_offset:316*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 316*FLEN/8, x11, x6, x2) + +inst_182: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x7c00; + valaddr_reg:x10; val_offset:318*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 318*FLEN/8, x11, x6, x2) + +inst_183: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xfc00; + valaddr_reg:x10; val_offset:320*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 320*FLEN/8, x11, x6, x2) + +inst_184: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x7e00; + valaddr_reg:x10; val_offset:322*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 322*FLEN/8, x11, x6, x2) + +inst_185: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xfe00; + valaddr_reg:x10; val_offset:324*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 324*FLEN/8, x11, x6, x2) + +inst_186: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x7e01; + valaddr_reg:x10; val_offset:326*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 326*FLEN/8, x11, x6, x2) + +inst_187: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xfe55; + valaddr_reg:x10; val_offset:328*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 328*FLEN/8, x11, x6, x2) + +inst_188: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x7c01; + valaddr_reg:x10; val_offset:330*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 330*FLEN/8, x11, x6, x2) + +inst_189: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xfd55; + valaddr_reg:x10; val_offset:332*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 332*FLEN/8, x11, x6, x2) + +inst_190: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x3c00; + valaddr_reg:x10; val_offset:334*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 334*FLEN/8, x11, x6, x2) + +inst_191: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xbc00; + valaddr_reg:x10; val_offset:336*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 336*FLEN/8, x11, x6, x2) + +inst_192: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x0; + valaddr_reg:x10; val_offset:338*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 338*FLEN/8, x11, x6, x2) + +inst_193: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x8000; + valaddr_reg:x10; val_offset:340*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 340*FLEN/8, x11, x6, x2) + +inst_194: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x1; + valaddr_reg:x10; val_offset:342*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 342*FLEN/8, x11, x6, x2) + +inst_195: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x8001; + valaddr_reg:x10; val_offset:344*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 344*FLEN/8, x11, x6, x2) + +inst_196: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x2; + valaddr_reg:x10; val_offset:346*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 346*FLEN/8, x11, x6, x2) + +inst_197: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x83fe; + valaddr_reg:x10; val_offset:348*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 348*FLEN/8, x11, x6, x2) + +inst_198: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x3ff; + valaddr_reg:x10; val_offset:350*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 350*FLEN/8, x11, x6, x2) + +inst_199: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x83ff; + valaddr_reg:x10; val_offset:352*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 352*FLEN/8, x11, x6, x2) + +inst_200: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x400; + valaddr_reg:x10; val_offset:354*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 354*FLEN/8, x11, x6, x2) + +inst_201: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x8400; + valaddr_reg:x10; val_offset:356*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 356*FLEN/8, x11, x6, x2) + +inst_202: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x401; + valaddr_reg:x10; val_offset:358*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 358*FLEN/8, x11, x6, x2) + +inst_203: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x8455; + valaddr_reg:x10; val_offset:360*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 360*FLEN/8, x11, x6, x2) + +inst_204: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7bff; + valaddr_reg:x10; val_offset:362*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 362*FLEN/8, x11, x6, x2) + +inst_205: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xfbff; + valaddr_reg:x10; val_offset:364*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 364*FLEN/8, x11, x6, x2) + +inst_206: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7c00; + valaddr_reg:x10; val_offset:366*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 366*FLEN/8, x11, x6, x2) + +inst_207: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xfc00; + valaddr_reg:x10; val_offset:368*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 368*FLEN/8, x11, x6, x2) + +inst_208: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7e00; + valaddr_reg:x10; val_offset:370*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 370*FLEN/8, x11, x6, x2) + +inst_209: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xfe00; + valaddr_reg:x10; val_offset:372*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 372*FLEN/8, x11, x6, x2) + +inst_210: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7e01; + valaddr_reg:x10; val_offset:374*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 374*FLEN/8, x11, x6, x2) + +inst_211: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xfe55; + valaddr_reg:x10; val_offset:376*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 376*FLEN/8, x11, x6, x2) + +inst_212: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7c01; + valaddr_reg:x10; val_offset:378*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 378*FLEN/8, x11, x6, x2) + +inst_213: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xfd55; + valaddr_reg:x10; val_offset:380*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 380*FLEN/8, x11, x6, x2) + +inst_214: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x3c00; + valaddr_reg:x10; val_offset:382*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 382*FLEN/8, x11, x6, x2) + +inst_215: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xbc00; + valaddr_reg:x10; val_offset:384*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 384*FLEN/8, x11, x6, x2) + +inst_216: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x0; + valaddr_reg:x10; val_offset:386*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 386*FLEN/8, x11, x6, x2) + +inst_217: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8000; + valaddr_reg:x10; val_offset:388*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 388*FLEN/8, x11, x6, x2) + +inst_218: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x1; + valaddr_reg:x10; val_offset:390*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 390*FLEN/8, x11, x6, x2) + +inst_219: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8001; + valaddr_reg:x10; val_offset:392*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 392*FLEN/8, x11, x6, x2) + +inst_220: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x2; + valaddr_reg:x10; val_offset:394*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 394*FLEN/8, x11, x6, x2) + +inst_221: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x83fe; + valaddr_reg:x10; val_offset:396*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 396*FLEN/8, x11, x6, x2) + +inst_222: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x3ff; + valaddr_reg:x10; val_offset:398*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 398*FLEN/8, x11, x6, x2) + +inst_223: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x83ff; + valaddr_reg:x10; val_offset:400*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 400*FLEN/8, x11, x6, x2) + +inst_224: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x400; + valaddr_reg:x10; val_offset:402*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 402*FLEN/8, x11, x6, x2) + +inst_225: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8400; + valaddr_reg:x10; val_offset:404*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 404*FLEN/8, x11, x6, x2) + +inst_226: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x401; + valaddr_reg:x10; val_offset:406*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 406*FLEN/8, x11, x6, x2) + +inst_227: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8455; + valaddr_reg:x10; val_offset:408*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 408*FLEN/8, x11, x6, x2) + +inst_228: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x7bff; + valaddr_reg:x10; val_offset:410*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 410*FLEN/8, x11, x6, x2) + +inst_229: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xfbff; + valaddr_reg:x10; val_offset:412*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 412*FLEN/8, x11, x6, x2) + +inst_230: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x7c00; + valaddr_reg:x10; val_offset:414*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 414*FLEN/8, x11, x6, x2) + +inst_231: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xfc00; + valaddr_reg:x10; val_offset:416*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 416*FLEN/8, x11, x6, x2) + +inst_232: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x7e00; + valaddr_reg:x10; val_offset:418*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 418*FLEN/8, x11, x6, x2) + +inst_233: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xfe00; + valaddr_reg:x10; val_offset:420*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 420*FLEN/8, x11, x6, x2) + +inst_234: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x7e01; + valaddr_reg:x10; val_offset:422*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 422*FLEN/8, x11, x6, x2) + +inst_235: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xfe55; + valaddr_reg:x10; val_offset:424*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 424*FLEN/8, x11, x6, x2) + +inst_236: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x7c01; + valaddr_reg:x10; val_offset:426*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 426*FLEN/8, x11, x6, x2) + +inst_237: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xfd55; + valaddr_reg:x10; val_offset:428*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 428*FLEN/8, x11, x6, x2) + +inst_238: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x3c00; + valaddr_reg:x10; val_offset:430*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 430*FLEN/8, x11, x6, x2) + +inst_239: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xbc00; + valaddr_reg:x10; val_offset:432*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 432*FLEN/8, x11, x6, x2) + +inst_240: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x0; + valaddr_reg:x10; val_offset:434*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 434*FLEN/8, x11, x6, x2) + +inst_241: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x8000; + valaddr_reg:x10; val_offset:436*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 436*FLEN/8, x11, x6, x2) + +inst_242: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x1; + valaddr_reg:x10; val_offset:438*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 438*FLEN/8, x11, x6, x2) + +inst_243: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x8001; + valaddr_reg:x10; val_offset:440*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 440*FLEN/8, x11, x6, x2) + +inst_244: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x2; + valaddr_reg:x10; val_offset:442*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 442*FLEN/8, x11, x6, x2) + +inst_245: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x83fe; + valaddr_reg:x10; val_offset:444*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 444*FLEN/8, x11, x6, x2) + +inst_246: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x3ff; + valaddr_reg:x10; val_offset:446*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 446*FLEN/8, x11, x6, x2) + +inst_247: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x83ff; + valaddr_reg:x10; val_offset:448*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 448*FLEN/8, x11, x6, x2) + +inst_248: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x400; + valaddr_reg:x10; val_offset:450*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 450*FLEN/8, x11, x6, x2) + +inst_249: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x8400; + valaddr_reg:x10; val_offset:452*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 452*FLEN/8, x11, x6, x2) + +inst_250: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x401; + valaddr_reg:x10; val_offset:454*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 454*FLEN/8, x11, x6, x2) + +inst_251: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x8455; + valaddr_reg:x10; val_offset:456*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 456*FLEN/8, x11, x6, x2) + +inst_252: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x7bff; + valaddr_reg:x10; val_offset:458*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 458*FLEN/8, x11, x6, x2) + +inst_253: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xfbff; + valaddr_reg:x10; val_offset:460*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 460*FLEN/8, x11, x6, x2) + +inst_254: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x7c00; + valaddr_reg:x10; val_offset:462*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 462*FLEN/8, x11, x6, x2) + +inst_255: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xfc00; + valaddr_reg:x10; val_offset:464*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 464*FLEN/8, x11, x6, x2) + +inst_256: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x7e00; + valaddr_reg:x10; val_offset:466*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 466*FLEN/8, x11, x6, x2) + +inst_257: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xfe00; + valaddr_reg:x10; val_offset:468*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 468*FLEN/8, x11, x6, x2) + +inst_258: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x7e01; + valaddr_reg:x10; val_offset:470*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 470*FLEN/8, x11, x6, x2) + +inst_259: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xfe55; + valaddr_reg:x10; val_offset:472*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 472*FLEN/8, x11, x6, x2) + +inst_260: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x7c01; + valaddr_reg:x10; val_offset:474*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 474*FLEN/8, x11, x6, x2) + +inst_261: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xfd55; + valaddr_reg:x10; val_offset:476*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 476*FLEN/8, x11, x6, x2) + +inst_262: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x3c00; + valaddr_reg:x10; val_offset:478*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 478*FLEN/8, x11, x6, x2) + +inst_263: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xbc00; + valaddr_reg:x10; val_offset:480*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 480*FLEN/8, x11, x6, x2) + +inst_264: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x0; + valaddr_reg:x10; val_offset:482*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 482*FLEN/8, x11, x6, x2) + +inst_265: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x8000; + valaddr_reg:x10; val_offset:484*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 484*FLEN/8, x11, x6, x2) + +inst_266: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x1; + valaddr_reg:x10; val_offset:486*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 486*FLEN/8, x11, x6, x2) + +inst_267: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x8001; + valaddr_reg:x10; val_offset:488*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 488*FLEN/8, x11, x6, x2) + +inst_268: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x2; + valaddr_reg:x10; val_offset:490*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 490*FLEN/8, x11, x6, x2) + +inst_269: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x83fe; + valaddr_reg:x10; val_offset:492*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 492*FLEN/8, x11, x6, x2) + +inst_270: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x3ff; + valaddr_reg:x10; val_offset:494*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 494*FLEN/8, x11, x6, x2) + +inst_271: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x83ff; + valaddr_reg:x10; val_offset:496*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 496*FLEN/8, x11, x6, x2) + +inst_272: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x400; + valaddr_reg:x10; val_offset:498*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 498*FLEN/8, x11, x6, x2) + +inst_273: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x8400; + valaddr_reg:x10; val_offset:500*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 500*FLEN/8, x11, x6, x2) +RVTEST_SIGBASE(x6,signature_x6_2) + +inst_274: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x401; + valaddr_reg:x10; val_offset:502*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 502*FLEN/8, x11, x6, x2) + +inst_275: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x8455; + valaddr_reg:x10; val_offset:504*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 504*FLEN/8, x11, x6, x2) + +inst_276: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x7bff; + valaddr_reg:x10; val_offset:506*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 506*FLEN/8, x11, x6, x2) + +inst_277: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xfbff; + valaddr_reg:x10; val_offset:508*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 508*FLEN/8, x11, x6, x2) + +inst_278: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x7c00; + valaddr_reg:x10; val_offset:510*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 510*FLEN/8, x11, x6, x2) + +inst_279: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xfc00; + valaddr_reg:x10; val_offset:512*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 512*FLEN/8, x11, x6, x2) + +inst_280: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x7e00; + valaddr_reg:x10; val_offset:514*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 514*FLEN/8, x11, x6, x2) + +inst_281: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xfe00; + valaddr_reg:x10; val_offset:516*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 516*FLEN/8, x11, x6, x2) + +inst_282: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x7e01; + valaddr_reg:x10; val_offset:518*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 518*FLEN/8, x11, x6, x2) + +inst_283: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xfe55; + valaddr_reg:x10; val_offset:520*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 520*FLEN/8, x11, x6, x2) + +inst_284: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x7c01; + valaddr_reg:x10; val_offset:522*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 522*FLEN/8, x11, x6, x2) + +inst_285: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xfd55; + valaddr_reg:x10; val_offset:524*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 524*FLEN/8, x11, x6, x2) + +inst_286: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x3c00; + valaddr_reg:x10; val_offset:526*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 526*FLEN/8, x11, x6, x2) + +inst_287: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xbc00; + valaddr_reg:x10; val_offset:528*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 528*FLEN/8, x11, x6, x2) + +inst_288: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x0; + valaddr_reg:x10; val_offset:530*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 530*FLEN/8, x11, x6, x2) + +inst_289: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8000; + valaddr_reg:x10; val_offset:532*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 532*FLEN/8, x11, x6, x2) + +inst_290: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x1; + valaddr_reg:x10; val_offset:534*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 534*FLEN/8, x11, x6, x2) + +inst_291: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8001; + valaddr_reg:x10; val_offset:536*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 536*FLEN/8, x11, x6, x2) + +inst_292: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x2; + valaddr_reg:x10; val_offset:538*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 538*FLEN/8, x11, x6, x2) + +inst_293: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x83fe; + valaddr_reg:x10; val_offset:540*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 540*FLEN/8, x11, x6, x2) + +inst_294: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x3ff; + valaddr_reg:x10; val_offset:542*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 542*FLEN/8, x11, x6, x2) + +inst_295: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x83ff; + valaddr_reg:x10; val_offset:544*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 544*FLEN/8, x11, x6, x2) + +inst_296: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x400; + valaddr_reg:x10; val_offset:546*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 546*FLEN/8, x11, x6, x2) + +inst_297: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8400; + valaddr_reg:x10; val_offset:548*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 548*FLEN/8, x11, x6, x2) + +inst_298: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x401; + valaddr_reg:x10; val_offset:550*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 550*FLEN/8, x11, x6, x2) + +inst_299: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8455; + valaddr_reg:x10; val_offset:552*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 552*FLEN/8, x11, x6, x2) + +inst_300: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7bff; + valaddr_reg:x10; val_offset:554*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 554*FLEN/8, x11, x6, x2) + +inst_301: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xfbff; + valaddr_reg:x10; val_offset:556*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 556*FLEN/8, x11, x6, x2) + +inst_302: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7c00; + valaddr_reg:x10; val_offset:558*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 558*FLEN/8, x11, x6, x2) + +inst_303: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xfc00; + valaddr_reg:x10; val_offset:560*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 560*FLEN/8, x11, x6, x2) + +inst_304: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7e00; + valaddr_reg:x10; val_offset:562*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 562*FLEN/8, x11, x6, x2) + +inst_305: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xfe00; + valaddr_reg:x10; val_offset:564*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 564*FLEN/8, x11, x6, x2) + +inst_306: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7e01; + valaddr_reg:x10; val_offset:566*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 566*FLEN/8, x11, x6, x2) + +inst_307: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xfe55; + valaddr_reg:x10; val_offset:568*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 568*FLEN/8, x11, x6, x2) + +inst_308: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7c01; + valaddr_reg:x10; val_offset:570*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 570*FLEN/8, x11, x6, x2) + +inst_309: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xfd55; + valaddr_reg:x10; val_offset:572*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 572*FLEN/8, x11, x6, x2) + +inst_310: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x3c00; + valaddr_reg:x10; val_offset:574*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 574*FLEN/8, x11, x6, x2) + +inst_311: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xbc00; + valaddr_reg:x10; val_offset:576*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 576*FLEN/8, x11, x6, x2) + +inst_312: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x0; + valaddr_reg:x10; val_offset:578*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 578*FLEN/8, x11, x6, x2) + +inst_313: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8000; + valaddr_reg:x10; val_offset:580*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 580*FLEN/8, x11, x6, x2) + +inst_314: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x1; + valaddr_reg:x10; val_offset:582*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 582*FLEN/8, x11, x6, x2) + +inst_315: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8001; + valaddr_reg:x10; val_offset:584*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 584*FLEN/8, x11, x6, x2) + +inst_316: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x2; + valaddr_reg:x10; val_offset:586*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 586*FLEN/8, x11, x6, x2) + +inst_317: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x83fe; + valaddr_reg:x10; val_offset:588*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 588*FLEN/8, x11, x6, x2) + +inst_318: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x3ff; + valaddr_reg:x10; val_offset:590*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 590*FLEN/8, x11, x6, x2) + +inst_319: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x83ff; + valaddr_reg:x10; val_offset:592*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 592*FLEN/8, x11, x6, x2) + +inst_320: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x400; + valaddr_reg:x10; val_offset:594*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 594*FLEN/8, x11, x6, x2) + +inst_321: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8400; + valaddr_reg:x10; val_offset:596*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 596*FLEN/8, x11, x6, x2) + +inst_322: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x401; + valaddr_reg:x10; val_offset:598*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 598*FLEN/8, x11, x6, x2) + +inst_323: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8455; + valaddr_reg:x10; val_offset:600*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 600*FLEN/8, x11, x6, x2) + +inst_324: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7bff; + valaddr_reg:x10; val_offset:602*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 602*FLEN/8, x11, x6, x2) + +inst_325: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfbff; + valaddr_reg:x10; val_offset:604*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 604*FLEN/8, x11, x6, x2) + +inst_326: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7c00; + valaddr_reg:x10; val_offset:606*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 606*FLEN/8, x11, x6, x2) + +inst_327: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfc00; + valaddr_reg:x10; val_offset:608*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 608*FLEN/8, x11, x6, x2) + +inst_328: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7e00; + valaddr_reg:x10; val_offset:610*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 610*FLEN/8, x11, x6, x2) + +inst_329: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfe00; + valaddr_reg:x10; val_offset:612*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 612*FLEN/8, x11, x6, x2) + +inst_330: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7e01; + valaddr_reg:x10; val_offset:614*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 614*FLEN/8, x11, x6, x2) + +inst_331: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfe55; + valaddr_reg:x10; val_offset:616*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 616*FLEN/8, x11, x6, x2) + +inst_332: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7c01; + valaddr_reg:x10; val_offset:618*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 618*FLEN/8, x11, x6, x2) + +inst_333: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfd55; + valaddr_reg:x10; val_offset:620*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 620*FLEN/8, x11, x6, x2) + +inst_334: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x3c00; + valaddr_reg:x10; val_offset:622*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 622*FLEN/8, x11, x6, x2) + +inst_335: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xbc00; + valaddr_reg:x10; val_offset:624*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 624*FLEN/8, x11, x6, x2) + +inst_336: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x0; + valaddr_reg:x10; val_offset:626*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 626*FLEN/8, x11, x6, x2) + +inst_337: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x8000; + valaddr_reg:x10; val_offset:628*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 628*FLEN/8, x11, x6, x2) + +inst_338: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x1; + valaddr_reg:x10; val_offset:630*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 630*FLEN/8, x11, x6, x2) + +inst_339: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x8001; + valaddr_reg:x10; val_offset:632*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 632*FLEN/8, x11, x6, x2) + +inst_340: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x2; + valaddr_reg:x10; val_offset:634*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 634*FLEN/8, x11, x6, x2) + +inst_341: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x83fe; + valaddr_reg:x10; val_offset:636*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 636*FLEN/8, x11, x6, x2) + +inst_342: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x3ff; + valaddr_reg:x10; val_offset:638*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 638*FLEN/8, x11, x6, x2) + +inst_343: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x83ff; + valaddr_reg:x10; val_offset:640*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 640*FLEN/8, x11, x6, x2) + +inst_344: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x400; + valaddr_reg:x10; val_offset:642*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 642*FLEN/8, x11, x6, x2) + +inst_345: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x8400; + valaddr_reg:x10; val_offset:644*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 644*FLEN/8, x11, x6, x2) + +inst_346: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x401; + valaddr_reg:x10; val_offset:646*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 646*FLEN/8, x11, x6, x2) + +inst_347: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x8455; + valaddr_reg:x10; val_offset:648*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 648*FLEN/8, x11, x6, x2) + +inst_348: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x7bff; + valaddr_reg:x10; val_offset:650*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 650*FLEN/8, x11, x6, x2) + +inst_349: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xfbff; + valaddr_reg:x10; val_offset:652*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 652*FLEN/8, x11, x6, x2) + +inst_350: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x7c00; + valaddr_reg:x10; val_offset:654*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 654*FLEN/8, x11, x6, x2) + +inst_351: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xfc00; + valaddr_reg:x10; val_offset:656*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 656*FLEN/8, x11, x6, x2) + +inst_352: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x7e00; + valaddr_reg:x10; val_offset:658*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 658*FLEN/8, x11, x6, x2) + +inst_353: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xfe00; + valaddr_reg:x10; val_offset:660*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 660*FLEN/8, x11, x6, x2) + +inst_354: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x7e01; + valaddr_reg:x10; val_offset:662*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 662*FLEN/8, x11, x6, x2) + +inst_355: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xfe55; + valaddr_reg:x10; val_offset:664*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 664*FLEN/8, x11, x6, x2) + +inst_356: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x7c01; + valaddr_reg:x10; val_offset:666*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 666*FLEN/8, x11, x6, x2) + +inst_357: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xfd55; + valaddr_reg:x10; val_offset:668*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 668*FLEN/8, x11, x6, x2) + +inst_358: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x3c00; + valaddr_reg:x10; val_offset:670*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 670*FLEN/8, x11, x6, x2) + +inst_359: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xbc00; + valaddr_reg:x10; val_offset:672*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 672*FLEN/8, x11, x6, x2) + +inst_360: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x0; + valaddr_reg:x10; val_offset:674*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 674*FLEN/8, x11, x6, x2) + +inst_361: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x8000; + valaddr_reg:x10; val_offset:676*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 676*FLEN/8, x11, x6, x2) + +inst_362: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x1; + valaddr_reg:x10; val_offset:678*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 678*FLEN/8, x11, x6, x2) + +inst_363: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x8001; + valaddr_reg:x10; val_offset:680*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 680*FLEN/8, x11, x6, x2) + +inst_364: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x2; + valaddr_reg:x10; val_offset:682*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 682*FLEN/8, x11, x6, x2) + +inst_365: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x83fe; + valaddr_reg:x10; val_offset:684*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 684*FLEN/8, x11, x6, x2) + +inst_366: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x3ff; + valaddr_reg:x10; val_offset:686*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 686*FLEN/8, x11, x6, x2) + +inst_367: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x83ff; + valaddr_reg:x10; val_offset:688*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 688*FLEN/8, x11, x6, x2) + +inst_368: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x400; + valaddr_reg:x10; val_offset:690*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 690*FLEN/8, x11, x6, x2) + +inst_369: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x8400; + valaddr_reg:x10; val_offset:692*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 692*FLEN/8, x11, x6, x2) + +inst_370: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x401; + valaddr_reg:x10; val_offset:694*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 694*FLEN/8, x11, x6, x2) + +inst_371: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x8455; + valaddr_reg:x10; val_offset:696*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 696*FLEN/8, x11, x6, x2) + +inst_372: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x7bff; + valaddr_reg:x10; val_offset:698*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 698*FLEN/8, x11, x6, x2) + +inst_373: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xfbff; + valaddr_reg:x10; val_offset:700*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 700*FLEN/8, x11, x6, x2) + +inst_374: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x7c00; + valaddr_reg:x10; val_offset:702*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 702*FLEN/8, x11, x6, x2) + +inst_375: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xfc00; + valaddr_reg:x10; val_offset:704*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 704*FLEN/8, x11, x6, x2) + +inst_376: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x7e00; + valaddr_reg:x10; val_offset:706*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 706*FLEN/8, x11, x6, x2) + +inst_377: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xfe00; + valaddr_reg:x10; val_offset:708*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 708*FLEN/8, x11, x6, x2) + +inst_378: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x7e01; + valaddr_reg:x10; val_offset:710*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 710*FLEN/8, x11, x6, x2) + +inst_379: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xfe55; + valaddr_reg:x10; val_offset:712*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 712*FLEN/8, x11, x6, x2) + +inst_380: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x7c01; + valaddr_reg:x10; val_offset:714*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 714*FLEN/8, x11, x6, x2) + +inst_381: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xfd55; + valaddr_reg:x10; val_offset:716*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 716*FLEN/8, x11, x6, x2) + +inst_382: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x3c00; + valaddr_reg:x10; val_offset:718*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 718*FLEN/8, x11, x6, x2) + +inst_383: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xbc00; + valaddr_reg:x10; val_offset:720*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 720*FLEN/8, x11, x6, x2) + +inst_384: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x0; + valaddr_reg:x10; val_offset:722*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 722*FLEN/8, x11, x6, x2) + +inst_385: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x8000; + valaddr_reg:x10; val_offset:724*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 724*FLEN/8, x11, x6, x2) + +inst_386: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x1; + valaddr_reg:x10; val_offset:726*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 726*FLEN/8, x11, x6, x2) + +inst_387: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x8001; + valaddr_reg:x10; val_offset:728*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 728*FLEN/8, x11, x6, x2) + +inst_388: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x2; + valaddr_reg:x10; val_offset:730*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 730*FLEN/8, x11, x6, x2) + +inst_389: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x83fe; + valaddr_reg:x10; val_offset:732*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 732*FLEN/8, x11, x6, x2) + +inst_390: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x3ff; + valaddr_reg:x10; val_offset:734*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 734*FLEN/8, x11, x6, x2) + +inst_391: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x83ff; + valaddr_reg:x10; val_offset:736*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 736*FLEN/8, x11, x6, x2) + +inst_392: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x400; + valaddr_reg:x10; val_offset:738*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 738*FLEN/8, x11, x6, x2) + +inst_393: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x8400; + valaddr_reg:x10; val_offset:740*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 740*FLEN/8, x11, x6, x2) + +inst_394: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x401; + valaddr_reg:x10; val_offset:742*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 742*FLEN/8, x11, x6, x2) + +inst_395: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x8455; + valaddr_reg:x10; val_offset:744*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 744*FLEN/8, x11, x6, x2) + +inst_396: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x7bff; + valaddr_reg:x10; val_offset:746*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 746*FLEN/8, x11, x6, x2) + +inst_397: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xfbff; + valaddr_reg:x10; val_offset:748*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 748*FLEN/8, x11, x6, x2) + +inst_398: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x7c00; + valaddr_reg:x10; val_offset:750*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 750*FLEN/8, x11, x6, x2) + +inst_399: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xfc00; + valaddr_reg:x10; val_offset:752*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 752*FLEN/8, x11, x6, x2) + +inst_400: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x7e00; + valaddr_reg:x10; val_offset:754*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 754*FLEN/8, x11, x6, x2) + +inst_401: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xfe00; + valaddr_reg:x10; val_offset:756*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 756*FLEN/8, x11, x6, x2) +RVTEST_SIGBASE(x6,signature_x6_3) + +inst_402: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x7e01; + valaddr_reg:x10; val_offset:758*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 758*FLEN/8, x11, x6, x2) + +inst_403: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xfe55; + valaddr_reg:x10; val_offset:760*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 760*FLEN/8, x11, x6, x2) + +inst_404: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x7c01; + valaddr_reg:x10; val_offset:762*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 762*FLEN/8, x11, x6, x2) + +inst_405: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xfd55; + valaddr_reg:x10; val_offset:764*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 764*FLEN/8, x11, x6, x2) + +inst_406: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x3c00; + valaddr_reg:x10; val_offset:766*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 766*FLEN/8, x11, x6, x2) + +inst_407: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xbc00; + valaddr_reg:x10; val_offset:768*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 768*FLEN/8, x11, x6, x2) + +inst_408: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x0; + valaddr_reg:x10; val_offset:770*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 770*FLEN/8, x11, x6, x2) + +inst_409: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x8000; + valaddr_reg:x10; val_offset:772*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 772*FLEN/8, x11, x6, x2) + +inst_410: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x1; + valaddr_reg:x10; val_offset:774*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 774*FLEN/8, x11, x6, x2) + +inst_411: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x8001; + valaddr_reg:x10; val_offset:776*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 776*FLEN/8, x11, x6, x2) + +inst_412: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x2; + valaddr_reg:x10; val_offset:778*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 778*FLEN/8, x11, x6, x2) + +inst_413: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x83fe; + valaddr_reg:x10; val_offset:780*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 780*FLEN/8, x11, x6, x2) + +inst_414: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x3ff; + valaddr_reg:x10; val_offset:782*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 782*FLEN/8, x11, x6, x2) + +inst_415: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x83ff; + valaddr_reg:x10; val_offset:784*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 784*FLEN/8, x11, x6, x2) + +inst_416: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x400; + valaddr_reg:x10; val_offset:786*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 786*FLEN/8, x11, x6, x2) + +inst_417: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x8400; + valaddr_reg:x10; val_offset:788*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 788*FLEN/8, x11, x6, x2) + +inst_418: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x401; + valaddr_reg:x10; val_offset:790*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 790*FLEN/8, x11, x6, x2) + +inst_419: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x8455; + valaddr_reg:x10; val_offset:792*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 792*FLEN/8, x11, x6, x2) + +inst_420: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x7bff; + valaddr_reg:x10; val_offset:794*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 794*FLEN/8, x11, x6, x2) + +inst_421: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xfbff; + valaddr_reg:x10; val_offset:796*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 796*FLEN/8, x11, x6, x2) + +inst_422: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x7c00; + valaddr_reg:x10; val_offset:798*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 798*FLEN/8, x11, x6, x2) + +inst_423: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xfc00; + valaddr_reg:x10; val_offset:800*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 800*FLEN/8, x11, x6, x2) + +inst_424: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x7e00; + valaddr_reg:x10; val_offset:802*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 802*FLEN/8, x11, x6, x2) + +inst_425: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xfe00; + valaddr_reg:x10; val_offset:804*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 804*FLEN/8, x11, x6, x2) + +inst_426: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x7e01; + valaddr_reg:x10; val_offset:806*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 806*FLEN/8, x11, x6, x2) + +inst_427: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xfe55; + valaddr_reg:x10; val_offset:808*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 808*FLEN/8, x11, x6, x2) + +inst_428: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x7c01; + valaddr_reg:x10; val_offset:810*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 810*FLEN/8, x11, x6, x2) + +inst_429: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xfd55; + valaddr_reg:x10; val_offset:812*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 812*FLEN/8, x11, x6, x2) + +inst_430: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x3c00; + valaddr_reg:x10; val_offset:814*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 814*FLEN/8, x11, x6, x2) + +inst_431: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xbc00; + valaddr_reg:x10; val_offset:816*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 816*FLEN/8, x11, x6, x2) + +inst_432: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x0; + valaddr_reg:x10; val_offset:818*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 818*FLEN/8, x11, x6, x2) + +inst_433: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x8000; + valaddr_reg:x10; val_offset:820*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 820*FLEN/8, x11, x6, x2) + +inst_434: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x1; + valaddr_reg:x10; val_offset:822*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 822*FLEN/8, x11, x6, x2) + +inst_435: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x8001; + valaddr_reg:x10; val_offset:824*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 824*FLEN/8, x11, x6, x2) + +inst_436: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x2; + valaddr_reg:x10; val_offset:826*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 826*FLEN/8, x11, x6, x2) + +inst_437: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x83fe; + valaddr_reg:x10; val_offset:828*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 828*FLEN/8, x11, x6, x2) + +inst_438: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x3ff; + valaddr_reg:x10; val_offset:830*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 830*FLEN/8, x11, x6, x2) + +inst_439: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x83ff; + valaddr_reg:x10; val_offset:832*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 832*FLEN/8, x11, x6, x2) + +inst_440: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x400; + valaddr_reg:x10; val_offset:834*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 834*FLEN/8, x11, x6, x2) + +inst_441: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x8400; + valaddr_reg:x10; val_offset:836*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 836*FLEN/8, x11, x6, x2) + +inst_442: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x401; + valaddr_reg:x10; val_offset:838*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 838*FLEN/8, x11, x6, x2) + +inst_443: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x8455; + valaddr_reg:x10; val_offset:840*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 840*FLEN/8, x11, x6, x2) + +inst_444: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x7bff; + valaddr_reg:x10; val_offset:842*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 842*FLEN/8, x11, x6, x2) + +inst_445: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xfbff; + valaddr_reg:x10; val_offset:844*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 844*FLEN/8, x11, x6, x2) + +inst_446: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x7c00; + valaddr_reg:x10; val_offset:846*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 846*FLEN/8, x11, x6, x2) + +inst_447: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xfc00; + valaddr_reg:x10; val_offset:848*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 848*FLEN/8, x11, x6, x2) + +inst_448: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x7e00; + valaddr_reg:x10; val_offset:850*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 850*FLEN/8, x11, x6, x2) + +inst_449: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xfe00; + valaddr_reg:x10; val_offset:852*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 852*FLEN/8, x11, x6, x2) + +inst_450: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x7e01; + valaddr_reg:x10; val_offset:854*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 854*FLEN/8, x11, x6, x2) + +inst_451: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xfe55; + valaddr_reg:x10; val_offset:856*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 856*FLEN/8, x11, x6, x2) + +inst_452: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x7c01; + valaddr_reg:x10; val_offset:858*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 858*FLEN/8, x11, x6, x2) + +inst_453: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xfd55; + valaddr_reg:x10; val_offset:860*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 860*FLEN/8, x11, x6, x2) + +inst_454: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x3c00; + valaddr_reg:x10; val_offset:862*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 862*FLEN/8, x11, x6, x2) + +inst_455: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xbc00; + valaddr_reg:x10; val_offset:864*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 864*FLEN/8, x11, x6, x2) + +inst_456: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x0; + valaddr_reg:x10; val_offset:866*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 866*FLEN/8, x11, x6, x2) + +inst_457: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x8000; + valaddr_reg:x10; val_offset:868*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 868*FLEN/8, x11, x6, x2) + +inst_458: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x1; + valaddr_reg:x10; val_offset:870*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 870*FLEN/8, x11, x6, x2) + +inst_459: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x8001; + valaddr_reg:x10; val_offset:872*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 872*FLEN/8, x11, x6, x2) + +inst_460: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x2; + valaddr_reg:x10; val_offset:874*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 874*FLEN/8, x11, x6, x2) + +inst_461: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x83fe; + valaddr_reg:x10; val_offset:876*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 876*FLEN/8, x11, x6, x2) + +inst_462: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x3ff; + valaddr_reg:x10; val_offset:878*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 878*FLEN/8, x11, x6, x2) + +inst_463: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x83ff; + valaddr_reg:x10; val_offset:880*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 880*FLEN/8, x11, x6, x2) + +inst_464: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x400; + valaddr_reg:x10; val_offset:882*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 882*FLEN/8, x11, x6, x2) + +inst_465: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x8400; + valaddr_reg:x10; val_offset:884*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 884*FLEN/8, x11, x6, x2) + +inst_466: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x401; + valaddr_reg:x10; val_offset:886*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 886*FLEN/8, x11, x6, x2) + +inst_467: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x8455; + valaddr_reg:x10; val_offset:888*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 888*FLEN/8, x11, x6, x2) + +inst_468: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x7bff; + valaddr_reg:x10; val_offset:890*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 890*FLEN/8, x11, x6, x2) + +inst_469: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xfbff; + valaddr_reg:x10; val_offset:892*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 892*FLEN/8, x11, x6, x2) + +inst_470: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x7c00; + valaddr_reg:x10; val_offset:894*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 894*FLEN/8, x11, x6, x2) + +inst_471: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xfc00; + valaddr_reg:x10; val_offset:896*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 896*FLEN/8, x11, x6, x2) + +inst_472: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x7e00; + valaddr_reg:x10; val_offset:898*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 898*FLEN/8, x11, x6, x2) + +inst_473: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xfe00; + valaddr_reg:x10; val_offset:900*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 900*FLEN/8, x11, x6, x2) + +inst_474: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x7e01; + valaddr_reg:x10; val_offset:902*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 902*FLEN/8, x11, x6, x2) + +inst_475: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xfe55; + valaddr_reg:x10; val_offset:904*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 904*FLEN/8, x11, x6, x2) + +inst_476: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x7c01; + valaddr_reg:x10; val_offset:906*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 906*FLEN/8, x11, x6, x2) + +inst_477: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xfd55; + valaddr_reg:x10; val_offset:908*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 908*FLEN/8, x11, x6, x2) + +inst_478: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x3c00; + valaddr_reg:x10; val_offset:910*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 910*FLEN/8, x11, x6, x2) + +inst_479: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xbc00; + valaddr_reg:x10; val_offset:912*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 912*FLEN/8, x11, x6, x2) + +inst_480: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x0; + valaddr_reg:x10; val_offset:914*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 914*FLEN/8, x11, x6, x2) + +inst_481: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x8000; + valaddr_reg:x10; val_offset:916*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 916*FLEN/8, x11, x6, x2) + +inst_482: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x1; + valaddr_reg:x10; val_offset:918*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 918*FLEN/8, x11, x6, x2) + +inst_483: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x8001; + valaddr_reg:x10; val_offset:920*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 920*FLEN/8, x11, x6, x2) + +inst_484: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x2; + valaddr_reg:x10; val_offset:922*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 922*FLEN/8, x11, x6, x2) + +inst_485: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x83fe; + valaddr_reg:x10; val_offset:924*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 924*FLEN/8, x11, x6, x2) + +inst_486: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x3ff; + valaddr_reg:x10; val_offset:926*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 926*FLEN/8, x11, x6, x2) + +inst_487: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x83ff; + valaddr_reg:x10; val_offset:928*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 928*FLEN/8, x11, x6, x2) + +inst_488: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x400; + valaddr_reg:x10; val_offset:930*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 930*FLEN/8, x11, x6, x2) + +inst_489: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x8400; + valaddr_reg:x10; val_offset:932*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 932*FLEN/8, x11, x6, x2) + +inst_490: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x401; + valaddr_reg:x10; val_offset:934*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 934*FLEN/8, x11, x6, x2) + +inst_491: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x8455; + valaddr_reg:x10; val_offset:936*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 936*FLEN/8, x11, x6, x2) + +inst_492: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x7bff; + valaddr_reg:x10; val_offset:938*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 938*FLEN/8, x11, x6, x2) + +inst_493: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xfbff; + valaddr_reg:x10; val_offset:940*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 940*FLEN/8, x11, x6, x2) + +inst_494: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x7c00; + valaddr_reg:x10; val_offset:942*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 942*FLEN/8, x11, x6, x2) + +inst_495: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xfc00; + valaddr_reg:x10; val_offset:944*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 944*FLEN/8, x11, x6, x2) + +inst_496: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x7e00; + valaddr_reg:x10; val_offset:946*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 946*FLEN/8, x11, x6, x2) + +inst_497: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xfe00; + valaddr_reg:x10; val_offset:948*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 948*FLEN/8, x11, x6, x2) + +inst_498: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x7e01; + valaddr_reg:x10; val_offset:950*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 950*FLEN/8, x11, x6, x2) + +inst_499: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xfe55; + valaddr_reg:x10; val_offset:952*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 952*FLEN/8, x11, x6, x2) + +inst_500: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x7c01; + valaddr_reg:x10; val_offset:954*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 954*FLEN/8, x11, x6, x2) + +inst_501: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xfd55; + valaddr_reg:x10; val_offset:956*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 956*FLEN/8, x11, x6, x2) + +inst_502: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x3c00; + valaddr_reg:x10; val_offset:958*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 958*FLEN/8, x11, x6, x2) + +inst_503: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xbc00; + valaddr_reg:x10; val_offset:960*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 960*FLEN/8, x11, x6, x2) + +inst_504: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x0; + valaddr_reg:x10; val_offset:962*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 962*FLEN/8, x11, x6, x2) + +inst_505: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x8000; + valaddr_reg:x10; val_offset:964*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 964*FLEN/8, x11, x6, x2) + +inst_506: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x1; + valaddr_reg:x10; val_offset:966*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 966*FLEN/8, x11, x6, x2) + +inst_507: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x8001; + valaddr_reg:x10; val_offset:968*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 968*FLEN/8, x11, x6, x2) + +inst_508: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x2; + valaddr_reg:x10; val_offset:970*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 970*FLEN/8, x11, x6, x2) + +inst_509: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x83fe; + valaddr_reg:x10; val_offset:972*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 972*FLEN/8, x11, x6, x2) + +inst_510: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x3ff; + valaddr_reg:x10; val_offset:974*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 974*FLEN/8, x11, x6, x2) + +inst_511: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x83ff; + valaddr_reg:x10; val_offset:976*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 976*FLEN/8, x11, x6, x2) + +inst_512: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x400; + valaddr_reg:x10; val_offset:978*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 978*FLEN/8, x11, x6, x2) + +inst_513: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x8400; + valaddr_reg:x10; val_offset:980*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 980*FLEN/8, x11, x6, x2) + +inst_514: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x401; + valaddr_reg:x10; val_offset:982*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 982*FLEN/8, x11, x6, x2) + +inst_515: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x8455; + valaddr_reg:x10; val_offset:984*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 984*FLEN/8, x11, x6, x2) + +inst_516: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x7bff; + valaddr_reg:x10; val_offset:986*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 986*FLEN/8, x11, x6, x2) + +inst_517: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xfbff; + valaddr_reg:x10; val_offset:988*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 988*FLEN/8, x11, x6, x2) + +inst_518: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x7c00; + valaddr_reg:x10; val_offset:990*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 990*FLEN/8, x11, x6, x2) + +inst_519: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xfc00; + valaddr_reg:x10; val_offset:992*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 992*FLEN/8, x11, x6, x2) + +inst_520: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x7e00; + valaddr_reg:x10; val_offset:994*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 994*FLEN/8, x11, x6, x2) + +inst_521: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xfe00; + valaddr_reg:x10; val_offset:996*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 996*FLEN/8, x11, x6, x2) + +inst_522: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x7e01; + valaddr_reg:x10; val_offset:998*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 998*FLEN/8, x11, x6, x2) + +inst_523: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xfe55; + valaddr_reg:x10; val_offset:1000*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 1000*FLEN/8, x11, x6, x2) + +inst_524: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x7c01; + valaddr_reg:x10; val_offset:1002*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 1002*FLEN/8, x11, x6, x2) + +inst_525: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xfd55; + valaddr_reg:x10; val_offset:1004*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 1004*FLEN/8, x11, x6, x2) + +inst_526: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x3c00; + valaddr_reg:x10; val_offset:1006*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 1006*FLEN/8, x11, x6, x2) + +inst_527: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xbc00; + valaddr_reg:x10; val_offset:1008*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 1008*FLEN/8, x11, x6, x2) + +inst_528: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x0; + valaddr_reg:x10; val_offset:1010*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 1010*FLEN/8, x11, x6, x2) + +inst_529: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x8000; + valaddr_reg:x10; val_offset:1012*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 1012*FLEN/8, x11, x6, x2) +RVTEST_SIGBASE(x6,signature_x6_4) + +inst_530: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x1; + valaddr_reg:x10; val_offset:1014*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 1014*FLEN/8, x11, x6, x2) + +inst_531: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x8001; + valaddr_reg:x10; val_offset:1016*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 1016*FLEN/8, x11, x6, x2) + +inst_532: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2; + valaddr_reg:x10; val_offset:1018*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 1018*FLEN/8, x11, x6, x2) + +inst_533: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x83fe; + valaddr_reg:x10; val_offset:1020*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 1020*FLEN/8, x11, x6, x2) + +inst_534: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3ff; + valaddr_reg:x10; val_offset:1022*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 1022*FLEN/8, x11, x6, x2) + +inst_535: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x83ff; + valaddr_reg:x10; val_offset:1024*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 1024*FLEN/8, x11, x6, x2) + +inst_536: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x400; + valaddr_reg:x10; val_offset:1026*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 1026*FLEN/8, x11, x6, x2) + +inst_537: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x8400; + valaddr_reg:x10; val_offset:1028*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 1028*FLEN/8, x11, x6, x2) + +inst_538: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x401; + valaddr_reg:x10; val_offset:1030*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 1030*FLEN/8, x11, x6, x2) + +inst_539: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x8455; + valaddr_reg:x10; val_offset:1032*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 1032*FLEN/8, x11, x6, x2) + +inst_540: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7bff; + valaddr_reg:x10; val_offset:1034*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 1034*FLEN/8, x11, x6, x2) + +inst_541: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xfbff; + valaddr_reg:x10; val_offset:1036*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 1036*FLEN/8, x11, x6, x2) + +inst_542: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7c00; + valaddr_reg:x10; val_offset:1038*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 1038*FLEN/8, x11, x6, x2) + +inst_543: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xfc00; + valaddr_reg:x10; val_offset:1040*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 1040*FLEN/8, x11, x6, x2) + +inst_544: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7e00; + valaddr_reg:x10; val_offset:1042*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 1042*FLEN/8, x11, x6, x2) + +inst_545: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xfe00; + valaddr_reg:x10; val_offset:1044*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 1044*FLEN/8, x11, x6, x2) + +inst_546: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7e01; + valaddr_reg:x10; val_offset:1046*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 1046*FLEN/8, x11, x6, x2) + +inst_547: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xfe55; + valaddr_reg:x10; val_offset:1048*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 1048*FLEN/8, x11, x6, x2) + +inst_548: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7c01; + valaddr_reg:x10; val_offset:1050*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 1050*FLEN/8, x11, x6, x2) + +inst_549: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xfd55; + valaddr_reg:x10; val_offset:1052*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 1052*FLEN/8, x11, x6, x2) + +inst_550: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3c00; + valaddr_reg:x10; val_offset:1054*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 1054*FLEN/8, x11, x6, x2) + +inst_551: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xbc00; + valaddr_reg:x10; val_offset:1056*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 1056*FLEN/8, x11, x6, x2) + +inst_552: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x0; + valaddr_reg:x10; val_offset:1058*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 1058*FLEN/8, x11, x6, x2) + +inst_553: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x8000; + valaddr_reg:x10; val_offset:1060*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 1060*FLEN/8, x11, x6, x2) + +inst_554: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x1; + valaddr_reg:x10; val_offset:1062*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 1062*FLEN/8, x11, x6, x2) + +inst_555: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x8001; + valaddr_reg:x10; val_offset:1064*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 1064*FLEN/8, x11, x6, x2) + +inst_556: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x2; + valaddr_reg:x10; val_offset:1066*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 1066*FLEN/8, x11, x6, x2) + +inst_557: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x83fe; + valaddr_reg:x10; val_offset:1068*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 1068*FLEN/8, x11, x6, x2) + +inst_558: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x3ff; + valaddr_reg:x10; val_offset:1070*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 1070*FLEN/8, x11, x6, x2) + +inst_559: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x83ff; + valaddr_reg:x10; val_offset:1072*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 1072*FLEN/8, x11, x6, x2) + +inst_560: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x400; + valaddr_reg:x10; val_offset:1074*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 1074*FLEN/8, x11, x6, x2) + +inst_561: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x8400; + valaddr_reg:x10; val_offset:1076*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 1076*FLEN/8, x11, x6, x2) + +inst_562: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x401; + valaddr_reg:x10; val_offset:1078*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 1078*FLEN/8, x11, x6, x2) + +inst_563: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x8455; + valaddr_reg:x10; val_offset:1080*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 1080*FLEN/8, x11, x6, x2) + +inst_564: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x7bff; + valaddr_reg:x10; val_offset:1082*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 1082*FLEN/8, x11, x6, x2) + +inst_565: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xfbff; + valaddr_reg:x10; val_offset:1084*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 1084*FLEN/8, x11, x6, x2) + +inst_566: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x7c00; + valaddr_reg:x10; val_offset:1086*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 1086*FLEN/8, x11, x6, x2) + +inst_567: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xfc00; + valaddr_reg:x10; val_offset:1088*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 1088*FLEN/8, x11, x6, x2) + +inst_568: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x7e00; + valaddr_reg:x10; val_offset:1090*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 1090*FLEN/8, x11, x6, x2) + +inst_569: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xfe00; + valaddr_reg:x10; val_offset:1092*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 1092*FLEN/8, x11, x6, x2) + +inst_570: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x7e01; + valaddr_reg:x10; val_offset:1094*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 1094*FLEN/8, x11, x6, x2) + +inst_571: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xfe55; + valaddr_reg:x10; val_offset:1096*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 1096*FLEN/8, x11, x6, x2) + +inst_572: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x7c01; + valaddr_reg:x10; val_offset:1098*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 1098*FLEN/8, x11, x6, x2) + +inst_573: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xfd55; + valaddr_reg:x10; val_offset:1100*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 1100*FLEN/8, x11, x6, x2) + +inst_574: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x3c00; + valaddr_reg:x10; val_offset:1102*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 1102*FLEN/8, x11, x6, x2) + +inst_575: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbc00; + valaddr_reg:x10; val_offset:1104*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 1104*FLEN/8, x11, x6, x2) + +inst_576: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x0; + valaddr_reg:x10; val_offset:1106*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 1106*FLEN/8, x11, x6, x2) + +inst_577: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x8000; + valaddr_reg:x10; val_offset:1108*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 1108*FLEN/8, x11, x6, x2) + +inst_578: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x8001; + valaddr_reg:x10; val_offset:1110*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 1110*FLEN/8, x11, x6, x2) + +inst_579: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x3ff; + valaddr_reg:x10; val_offset:1112*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 1112*FLEN/8, x11, x6, x2) + +inst_580: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x8400; + valaddr_reg:x10; val_offset:1114*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x10, 1114*FLEN/8, x11, x6, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(1,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(2,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(1023,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(1024,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(1025,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31743,32,FLEN) +test_dataset_1: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31744,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32256,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32257,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31745,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(15360,32,FLEN) +test_dataset_2: +NAN_BOXED(0,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32257,16,FLEN) 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+NAN_BOXED(15360,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(33792,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x7_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x7_1: + .fill 36*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x6_0: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x6_1: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x6_2: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x6_3: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x6_4: + .fill 102*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fmin_b19-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fmin_b19-01.S new file mode 100644 index 000000000..feb0d80f5 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fmin_b19-01.S @@ -0,0 +1,10469 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 05:46:50 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fmin.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fmin.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fmin_b19 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fmin_b19) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x11,test_dataset_0) +RVTEST_SIGBASE(x8,signature_x8_1) + +inst_0: +// rs1 == rs2 == rd, rs1==x24, rs2==x24, rd==x24,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x24; op2:x24; dest:x24; op1val:0x7ac0; op2val:0x7ac0; + valaddr_reg:x11; val_offset:0*FLEN/8; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP_NRM(fmin.h, x24, x24, x24, 0, 0, x11, 0*FLEN/8, x20, x8, x9) + +inst_1: +// rs1 == rd != rs2, rs1==x0, rs2==x23, rd==x0,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x016 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x0; op2:x23; dest:x0; op1val:0x0; op2val:0x7816; + valaddr_reg:x11; val_offset:2*FLEN/8; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP_NRM(fmin.h, x0, x0, x23, 0, 0, x11, 2*FLEN/8, x20, x8, x9) + +inst_2: +// rs2 == rd != rs1, rs1==x28, rs2==x26, rd==x26,fs1 == 0 and fe1 == 0x1e and fm1 == 0x016 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x28; op2:x26; dest:x26; op1val:0x7816; op2val:0x7ac0; + valaddr_reg:x11; val_offset:4*FLEN/8; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP_NRM(fmin.h, x26, x28, x26, 0, 0, x11, 4*FLEN/8, x20, x8, x9) + +inst_3: +// rs1 == rs2 != rd, rs1==x13, rs2==x13, rd==x2,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x39f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x13; op2:x13; dest:x2; op1val:0x7ac0; op2val:0x7ac0; + valaddr_reg:x11; val_offset:6*FLEN/8; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP_NRM(fmin.h, x2, x13, x13, 0, 0, x11, 6*FLEN/8, x20, x8, x9) + +inst_4: +// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==x16, rs2==x17, rd==x28,fs1 == 0 and fe1 == 0x1d and fm1 == 0x39f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x16; op2:x17; dest:x28; op1val:0x779f; op2val:0x7ac0; + valaddr_reg:x11; val_offset:8*FLEN/8; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP_NRM(fmin.h, x28, x16, x17, 0, 0, x11, 8*FLEN/8, x20, x8, x9) + +inst_5: +// rs1==x27, rs2==x21, rd==x4,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x081 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x27; op2:x21; dest:x4; op1val:0x7ac0; op2val:0x7481; + valaddr_reg:x11; val_offset:10*FLEN/8; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP_NRM(fmin.h, x4, x27, x21, 0, 0, x11, 10*FLEN/8, x20, x8, x9) + +inst_6: +// rs1==x1, rs2==x7, rd==x30,fs1 == 0 and fe1 == 0x1d and fm1 == 0x081 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x1; op2:x7; dest:x30; op1val:0x7481; op2val:0x7ac0; + valaddr_reg:x11; val_offset:12*FLEN/8; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP_NRM(fmin.h, x30, x1, x7, 0, 0, x11, 12*FLEN/8, x20, x8, x9) + +inst_7: +// rs1==x7, rs2==x10, rd==x19,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x346 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x7; op2:x10; dest:x19; op1val:0x7ac0; op2val:0x7b46; + valaddr_reg:x11; val_offset:14*FLEN/8; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP_NRM(fmin.h, x19, x7, x10, 0, 0, x11, 14*FLEN/8, x20, x8, x9) + +inst_8: +// rs1==x21, rs2==x12, rd==x15,fs1 == 0 and fe1 == 0x1e and fm1 == 0x346 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x21; op2:x12; dest:x15; op1val:0x7b46; op2val:0x7ac0; + valaddr_reg:x11; val_offset:16*FLEN/8; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP_NRM(fmin.h, x15, x21, x12, 0, 0, x11, 16*FLEN/8, x20, x8, x9) + +inst_9: +// rs1==x12, rs2==x15, rd==x18,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3bd and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x12; op2:x15; dest:x18; op1val:0x7ac0; op2val:0xf3bd; + valaddr_reg:x11; val_offset:18*FLEN/8; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP_NRM(fmin.h, x18, x12, x15, 0, 0, x11, 18*FLEN/8, x20, x8, x9) + +inst_10: +// rs1==x30, rs2==x22, rd==x21,fs1 == 1 and fe1 == 0x1c and fm1 == 0x3bd and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x22; dest:x21; op1val:0xf3bd; op2val:0x7ac0; + valaddr_reg:x11; val_offset:20*FLEN/8; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP_NRM(fmin.h, x21, x30, x22, 0, 0, x11, 20*FLEN/8, x20, x8, x9) + +inst_11: +// rs1==x14, rs2==x3, rd==x27,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0c2 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x14; op2:x3; dest:x27; op1val:0x7ac0; op2val:0xf8c2; + valaddr_reg:x11; val_offset:22*FLEN/8; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP_NRM(fmin.h, x27, x14, x3, 0, 0, x11, 22*FLEN/8, x20, x8, x9) + +inst_12: +// rs1==x5, rs2==x27, rd==x6,fs1 == 1 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x5; op2:x27; dest:x6; op1val:0xf8c2; op2val:0x7ac0; + valaddr_reg:x11; val_offset:24*FLEN/8; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP_NRM(fmin.h, x6, x5, x27, 0, 0, x11, 24*FLEN/8, x20, x8, x9) +RVTEST_VALBASEUPD(x12,test_dataset_1) + +inst_13: +// rs1==x17, rs2==x11, rd==x22,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2a9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x17; op2:x11; dest:x22; op1val:0x7ac0; op2val:0xf6a9; + valaddr_reg:x12; val_offset:0*FLEN/8; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP_NRM(fmin.h, x22, x17, x11, 0, 0, x12, 0*FLEN/8, x18, x8, x9) + +inst_14: +// rs1==x26, rs2==x2, rd==x20,fs1 == 1 and fe1 == 0x1d and fm1 == 0x2a9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x26; op2:x2; dest:x20; op1val:0xf6a9; op2val:0x7ac0; + valaddr_reg:x12; val_offset:2*FLEN/8; fcsr: 0; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP_NRM(fmin.h, x20, x26, x2, 0, 0, x12, 2*FLEN/8, x18, x8, x10) +RVTEST_SIGBASE(x21,signature_x21_0) + +inst_15: +// rs1==x19, rs2==x31, rd==x7,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3cf and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x19; op2:x31; dest:x7; op1val:0x7ac0; op2val:0xf3cf; + valaddr_reg:x12; val_offset:4*FLEN/8; fcsr: 0; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP_NRM(fmin.h, x7, x19, x31, 0, 0, x12, 4*FLEN/8, x18, x21, x10) + +inst_16: +// rs1==x15, rs2==x1, rd==x8,fs1 == 1 and fe1 == 0x1c and fm1 == 0x3cf and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x15; op2:x1; dest:x8; op1val:0xf3cf; op2val:0x7ac0; + valaddr_reg:x12; val_offset:6*FLEN/8; fcsr: 0; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP_NRM(fmin.h, x8, x15, x1, 0, 0, x12, 6*FLEN/8, x18, x21, x10) + +inst_17: +// rs1==x8, rs2==x14, rd==x1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 1 and fe2 == 0x19 and fm2 == 0x068 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x8; op2:x14; dest:x1; op1val:0x7ac0; op2val:0xe468; + valaddr_reg:x12; val_offset:8*FLEN/8; fcsr: 0; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP_NRM(fmin.h, x1, x8, x14, 0, 0, x12, 8*FLEN/8, x18, x21, x10) + +inst_18: +// rs1==x6, rs2==x20, rd==x3,fs1 == 0 and fe1 == 0x1b and fm1 == 0x166 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x182 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x6; op2:x20; dest:x3; op1val:0x6d66; op2val:0xf182; + valaddr_reg:x12; val_offset:10*FLEN/8; fcsr: 0; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP_NRM(fmin.h, x3, x6, x20, 0, 0, x12, 10*FLEN/8, x18, x21, x10) + +inst_19: +// rs1==x9, rs2==x30, rd==x25,fs1 == 1 and fe1 == 0x1c and fm1 == 0x182 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x166 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x9; op2:x30; dest:x25; op1val:0xf182; op2val:0x6d66; + valaddr_reg:x12; val_offset:12*FLEN/8; fcsr: 0; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP_NRM(fmin.h, x25, x9, x30, 0, 0, x12, 12*FLEN/8, x18, x21, x10) + +inst_20: +// rs1==x25, rs2==x4, rd==x16,fs1 == 0 and fe1 == 0x1b and fm1 == 0x166 and fs2 == 1 and fe2 == 0x19 and fm2 == 0x068 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x25; op2:x4; dest:x16; op1val:0x6d66; op2val:0xe468; + valaddr_reg:x12; val_offset:14*FLEN/8; fcsr: 0; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP_NRM(fmin.h, x16, x25, x4, 0, 0, x12, 14*FLEN/8, x18, x21, x10) + +inst_21: +// rs1==x31, rs2==x29, rd==x9,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x166 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x31; op2:x29; dest:x9; op1val:0x7ac0; op2val:0x6d66; + valaddr_reg:x12; val_offset:16*FLEN/8; fcsr: 0; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP_NRM(fmin.h, x9, x31, x29, 0, 0, x12, 16*FLEN/8, x18, x21, x10) + +inst_22: +// rs1==x22, rs2==x6, rd==x29,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1ae and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x22; op2:x6; dest:x29; op1val:0x7ac0; op2val:0x1ae; + valaddr_reg:x12; val_offset:18*FLEN/8; fcsr: 0; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP_NRM(fmin.h, x29, x22, x6, 0, 0, x12, 18*FLEN/8, x18, x21, x10) + +inst_23: +// rs1==x11, rs2==x5, rd==x13,fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a0 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x244 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x11; op2:x5; dest:x13; op1val:0x3a0; op2val:0x7644; + valaddr_reg:x12; val_offset:20*FLEN/8; fcsr: 0; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP_NRM(fmin.h, x13, x11, x5, 0, 0, x12, 20*FLEN/8, x18, x21, x10) +RVTEST_VALBASEUPD(x7,test_dataset_2) + +inst_24: +// rs1==x20, rs2==x18, rd==x23,fs1 == 0 and fe1 == 0x1d and fm1 == 0x244 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x20; op2:x18; dest:x23; op1val:0x7644; op2val:0x3a0; + valaddr_reg:x7; val_offset:0*FLEN/8; fcsr: 0; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP_NRM(fmin.h, x23, x20, x18, 0, 0, x7, 0*FLEN/8, x13, x21, x10) + +inst_25: +// rs1==x18, rs2==x19, rd==x17,fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1ae and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x18; op2:x19; dest:x17; op1val:0x3a0; op2val:0x1ae; + valaddr_reg:x7; val_offset:2*FLEN/8; fcsr: 0; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP_NRM(fmin.h, x17, x18, x19, 0, 0, x7, 2*FLEN/8, x13, x21, x10) + +inst_26: +// rs1==x29, rs2==x25, rd==x12,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x29; op2:x25; dest:x12; op1val:0x7ac0; op2val:0x3a0; + valaddr_reg:x7; val_offset:4*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x12, x29, x25, 0, 0, x7, 4*FLEN/8, x13, x21, x6) + +inst_27: +// rs1==x3, rs2==x9, rd==x14,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x322 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x3; op2:x9; dest:x14; op1val:0x7ac0; op2val:0x322; + valaddr_reg:x7; val_offset:6*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x14, x3, x9, 0, 0, x7, 6*FLEN/8, x13, x21, x6) + +inst_28: +// rs1==x2, rs2==x8, rd==x31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1d5 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x2; op2:x8; dest:x31; op1val:0x3a0; op2val:0x79d5; + valaddr_reg:x7; val_offset:8*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x2, x8, 0, 0, x7, 8*FLEN/8, x13, x21, x6) + +inst_29: +// rs1==x23, rs2==x0, rd==x5,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x23; op2:x0; dest:x5; op1val:0x79d5; op2val:0x0; + valaddr_reg:x7; val_offset:10*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x5, x23, x0, 0, 0, x7, 10*FLEN/8, x13, x21, x6) + +inst_30: +// rs1==x10, rs2==x28, rd==x11,fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x322 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x10; op2:x28; dest:x11; op1val:0x3a0; op2val:0x322; + valaddr_reg:x7; val_offset:12*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x11, x10, x28, 0, 0, x7, 12*FLEN/8, x13, x21, x6) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_31: +// rs1==x4, rs2==x16, rd==x10,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x4; op2:x16; dest:x10; op1val:0x7ac0; op2val:0x3a1; + valaddr_reg:x7; val_offset:14*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x10, x4, x16, 0, 0, x7, 14*FLEN/8, x13, x1, x6) + +inst_32: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c2 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a0; op2val:0x7ac2; + valaddr_reg:x7; val_offset:16*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 16*FLEN/8, x13, x1, x6) + +inst_33: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ac2; op2val:0x3a0; + valaddr_reg:x7; val_offset:18*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 18*FLEN/8, x13, x1, x6) + +inst_34: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a0; op2val:0x3a1; + valaddr_reg:x7; val_offset:20*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 20*FLEN/8, x13, x1, x6) + +inst_35: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x278 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ac0; op2val:0x278; + valaddr_reg:x7; val_offset:22*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 22*FLEN/8, x13, x1, x6) + +inst_36: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x09b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a0; op2val:0x789b; + valaddr_reg:x7; val_offset:24*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 24*FLEN/8, x13, x1, x6) + +inst_37: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x789b; op2val:0x3a0; + valaddr_reg:x7; val_offset:26*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 26*FLEN/8, x13, x1, x6) + +inst_38: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x278 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a0; op2val:0x278; + valaddr_reg:x7; val_offset:28*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 28*FLEN/8, x13, x1, x6) + +inst_39: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ac0; op2val:0x33d; + valaddr_reg:x7; val_offset:30*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 30*FLEN/8, x13, x1, x6) + +inst_40: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x208 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a0; op2val:0x7a08; + valaddr_reg:x7; val_offset:32*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 32*FLEN/8, x13, x1, x6) + +inst_41: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x208 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a08; op2val:0x3a0; + valaddr_reg:x7; val_offset:34*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 34*FLEN/8, x13, x1, x6) + +inst_42: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a0; op2val:0x33d; + valaddr_reg:x7; val_offset:36*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 36*FLEN/8, x13, x1, x6) + +inst_43: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ac0; op2val:0x82f6; + valaddr_reg:x7; val_offset:38*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 38*FLEN/8, x13, x1, x6) + +inst_44: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x184 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a0; op2val:0xf984; + valaddr_reg:x7; val_offset:40*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 40*FLEN/8, x13, x1, x6) + +inst_45: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x184 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf984; op2val:0x3a0; + valaddr_reg:x7; val_offset:42*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 42*FLEN/8, x13, x1, x6) + +inst_46: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a0; op2val:0x82f6; + valaddr_reg:x7; val_offset:44*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 44*FLEN/8, x13, x1, x6) + +inst_47: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ac0; op2val:0x82c9; + valaddr_reg:x7; val_offset:46*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 46*FLEN/8, x13, x1, x6) + +inst_48: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x130 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a0; op2val:0xf930; + valaddr_reg:x7; val_offset:48*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 48*FLEN/8, x13, x1, x6) + +inst_49: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x130 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf930; op2val:0x3a0; + valaddr_reg:x7; val_offset:50*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 50*FLEN/8, x13, x1, x6) + +inst_50: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a0; op2val:0x82c9; + valaddr_reg:x7; val_offset:52*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 52*FLEN/8, x13, x1, x6) + +inst_51: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ac0; op2val:0x81fb; + valaddr_reg:x7; val_offset:54*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 54*FLEN/8, x13, x1, x6) + +inst_52: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a0 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x361 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a0; op2val:0xf761; + valaddr_reg:x7; val_offset:56*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 56*FLEN/8, x13, x1, x6) + +inst_53: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x361 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf761; op2val:0x3a0; + valaddr_reg:x7; val_offset:58*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 58*FLEN/8, x13, x1, x6) + +inst_54: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a0; op2val:0x81fb; + valaddr_reg:x7; val_offset:60*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 60*FLEN/8, x13, x1, x6) + +inst_55: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ac0; op2val:0x82fe; + valaddr_reg:x7; val_offset:62*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 62*FLEN/8, x13, x1, x6) + +inst_56: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x194 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a0; op2val:0xf994; + valaddr_reg:x7; val_offset:64*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 64*FLEN/8, x13, x1, x6) + +inst_57: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x194 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf994; op2val:0x3a0; + valaddr_reg:x7; val_offset:66*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 66*FLEN/8, x13, x1, x6) + +inst_58: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a0; op2val:0x82fe; + valaddr_reg:x7; val_offset:68*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 68*FLEN/8, x13, x1, x6) + +inst_59: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x064 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ac0; op2val:0x8064; + valaddr_reg:x7; val_offset:70*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 70*FLEN/8, x13, x1, x6) + +inst_60: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x05c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x359 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x5c; op2val:0xfb59; + valaddr_reg:x7; val_offset:72*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 72*FLEN/8, x13, x1, x6) + +inst_61: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x359 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x05c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb59; op2val:0x5c; + valaddr_reg:x7; val_offset:74*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 74*FLEN/8, x13, x1, x6) + +inst_62: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x05c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x064 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x5c; op2val:0x8064; + valaddr_reg:x7; val_offset:76*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 76*FLEN/8, x13, x1, x6) + +inst_63: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x05c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ac0; op2val:0x5c; + valaddr_reg:x7; val_offset:78*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 78*FLEN/8, x13, x1, x6) + +inst_64: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ac0; op2val:0xf0; + valaddr_reg:x7; val_offset:80*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 80*FLEN/8, x13, x1, x6) + +inst_65: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x188 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x4588; op2val:0xf0; + valaddr_reg:x7; val_offset:82*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 82*FLEN/8, x13, x1, x6) + +inst_66: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x188 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x4588; + valaddr_reg:x7; val_offset:84*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 84*FLEN/8, x13, x1, x6) + +inst_67: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x188 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ac0; op2val:0x4588; + valaddr_reg:x7; val_offset:86*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 86*FLEN/8, x13, x1, x6) + +inst_68: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x016 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x016 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7816; op2val:0x7816; + valaddr_reg:x7; val_offset:88*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 88*FLEN/8, x13, x1, x6) + +inst_69: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x016 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x39f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7816; op2val:0x779f; + valaddr_reg:x7; val_offset:90*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 90*FLEN/8, x13, x1, x6) + +inst_70: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x39f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x016 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x779f; op2val:0x7816; + valaddr_reg:x7; val_offset:92*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 92*FLEN/8, x13, x1, x6) + +inst_71: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x016 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x081 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7816; op2val:0x7481; + valaddr_reg:x7; val_offset:94*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 94*FLEN/8, x13, x1, x6) + +inst_72: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x081 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x016 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7481; op2val:0x7816; + valaddr_reg:x7; val_offset:96*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 96*FLEN/8, x13, x1, x6) + +inst_73: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x016 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x346 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7816; op2val:0x7b46; + valaddr_reg:x7; val_offset:98*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 98*FLEN/8, x13, x1, x6) + +inst_74: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x346 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x016 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b46; op2val:0x7816; + valaddr_reg:x7; val_offset:100*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 100*FLEN/8, x13, x1, x6) + +inst_75: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x016 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3bd and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7816; op2val:0xf3bd; + valaddr_reg:x7; val_offset:102*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 102*FLEN/8, x13, x1, x6) + +inst_76: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3bd and fs2 == 0 and fe2 == 0x1e and fm2 == 0x016 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3bd; op2val:0x7816; + valaddr_reg:x7; val_offset:104*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 104*FLEN/8, x13, x1, x6) + +inst_77: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x016 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0c2 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7816; op2val:0xf8c2; + valaddr_reg:x7; val_offset:106*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 106*FLEN/8, x13, x1, x6) + +inst_78: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x016 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf8c2; op2val:0x7816; + valaddr_reg:x7; val_offset:108*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 108*FLEN/8, x13, x1, x6) + +inst_79: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x016 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2a9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7816; op2val:0xf6a9; + valaddr_reg:x7; val_offset:110*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 110*FLEN/8, x13, x1, x6) + +inst_80: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x2a9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x016 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf6a9; op2val:0x7816; + valaddr_reg:x7; val_offset:112*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 112*FLEN/8, x13, x1, x6) + +inst_81: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x016 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3cf and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7816; op2val:0xf3cf; + valaddr_reg:x7; val_offset:114*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 114*FLEN/8, x13, x1, x6) + +inst_82: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3cf and fs2 == 0 and fe2 == 0x1e and fm2 == 0x016 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3cf; op2val:0x7816; + valaddr_reg:x7; val_offset:116*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 116*FLEN/8, x13, x1, x6) + +inst_83: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x016 and fs2 == 1 and fe2 == 0x19 and fm2 == 0x068 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7816; op2val:0xe468; + valaddr_reg:x7; val_offset:118*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 118*FLEN/8, x13, x1, x6) + +inst_84: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x28a and fs2 == 1 and fe2 == 0x1c and fm2 == 0x182 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x6a8a; op2val:0xf182; + valaddr_reg:x7; val_offset:120*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 120*FLEN/8, x13, x1, x6) + +inst_85: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x182 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x28a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf182; op2val:0x6a8a; + valaddr_reg:x7; val_offset:122*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 122*FLEN/8, x13, x1, x6) + +inst_86: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x28a and fs2 == 1 and fe2 == 0x19 and fm2 == 0x068 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x6a8a; op2val:0xe468; + valaddr_reg:x7; val_offset:124*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 124*FLEN/8, x13, x1, x6) + +inst_87: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x016 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x28a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7816; op2val:0x6a8a; + valaddr_reg:x7; val_offset:126*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 126*FLEN/8, x13, x1, x6) + +inst_88: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x016 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1ae and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7816; op2val:0x1ae; + valaddr_reg:x7; val_offset:128*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 128*FLEN/8, x13, x1, x6) + +inst_89: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x231 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x244 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x231; op2val:0x7644; + valaddr_reg:x7; val_offset:130*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 130*FLEN/8, x13, x1, x6) + +inst_90: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x244 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x231 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7644; op2val:0x231; + valaddr_reg:x7; val_offset:132*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 132*FLEN/8, x13, x1, x6) + +inst_91: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x231 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1ae and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x231; op2val:0x1ae; + valaddr_reg:x7; val_offset:134*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 134*FLEN/8, x13, x1, x6) + +inst_92: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x016 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x231 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7816; op2val:0x231; + valaddr_reg:x7; val_offset:136*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 136*FLEN/8, x13, x1, x6) + +inst_93: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x016 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x322 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7816; op2val:0x322; + valaddr_reg:x7; val_offset:138*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 138*FLEN/8, x13, x1, x6) + +inst_94: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x231 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1d5 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x231; op2val:0x79d5; + valaddr_reg:x7; val_offset:140*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 140*FLEN/8, x13, x1, x6) + +inst_95: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x231 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x79d5; op2val:0x231; + valaddr_reg:x7; val_offset:142*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 142*FLEN/8, x13, x1, x6) + +inst_96: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x231 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x322 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x231; op2val:0x322; + valaddr_reg:x7; val_offset:144*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 144*FLEN/8, x13, x1, x6) + +inst_97: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x016 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7816; op2val:0x3a1; + valaddr_reg:x7; val_offset:146*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 146*FLEN/8, x13, x1, x6) + +inst_98: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x231 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c2 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x231; op2val:0x7ac2; + valaddr_reg:x7; val_offset:148*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 148*FLEN/8, x13, x1, x6) + +inst_99: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x231 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ac2; op2val:0x231; + valaddr_reg:x7; val_offset:150*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 150*FLEN/8, x13, x1, x6) + +inst_100: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x231 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x231; op2val:0x3a1; + valaddr_reg:x7; val_offset:152*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 152*FLEN/8, x13, x1, x6) + +inst_101: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x016 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x278 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7816; op2val:0x278; + valaddr_reg:x7; val_offset:154*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 154*FLEN/8, x13, x1, x6) + +inst_102: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x231 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x09b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x231; op2val:0x789b; + valaddr_reg:x7; val_offset:156*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 156*FLEN/8, x13, x1, x6) + +inst_103: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x231 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x789b; op2val:0x231; + valaddr_reg:x7; val_offset:158*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 158*FLEN/8, x13, x1, x6) + +inst_104: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x231 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x278 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x231; op2val:0x278; + valaddr_reg:x7; val_offset:160*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 160*FLEN/8, x13, x1, x6) + +inst_105: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x016 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7816; op2val:0x33d; + valaddr_reg:x7; val_offset:162*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 162*FLEN/8, x13, x1, x6) + +inst_106: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x231 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x208 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x231; op2val:0x7a08; + valaddr_reg:x7; val_offset:164*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 164*FLEN/8, x13, x1, x6) + +inst_107: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x208 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x231 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a08; op2val:0x231; + valaddr_reg:x7; val_offset:166*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 166*FLEN/8, x13, x1, x6) + +inst_108: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x231 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x231; op2val:0x33d; + valaddr_reg:x7; val_offset:168*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 168*FLEN/8, x13, x1, x6) + +inst_109: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x016 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7816; op2val:0x82f6; + valaddr_reg:x7; val_offset:170*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 170*FLEN/8, x13, x1, x6) + +inst_110: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x231 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x184 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x231; op2val:0xf984; + valaddr_reg:x7; val_offset:172*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 172*FLEN/8, x13, x1, x6) + +inst_111: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x184 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x231 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf984; op2val:0x231; + valaddr_reg:x7; val_offset:174*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 174*FLEN/8, x13, x1, x6) + +inst_112: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x231 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x231; op2val:0x82f6; + valaddr_reg:x7; val_offset:176*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 176*FLEN/8, x13, x1, x6) + +inst_113: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x016 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7816; op2val:0x82c9; + valaddr_reg:x7; val_offset:178*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 178*FLEN/8, x13, x1, x6) + +inst_114: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x231 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x130 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x231; op2val:0xf930; + valaddr_reg:x7; val_offset:180*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 180*FLEN/8, x13, x1, x6) + +inst_115: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x130 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x231 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf930; op2val:0x231; + valaddr_reg:x7; val_offset:182*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 182*FLEN/8, x13, x1, x6) + +inst_116: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x231 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x231; op2val:0x82c9; + valaddr_reg:x7; val_offset:184*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 184*FLEN/8, x13, x1, x6) + +inst_117: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x016 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7816; op2val:0x81fb; + valaddr_reg:x7; val_offset:186*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 186*FLEN/8, x13, x1, x6) + +inst_118: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x231 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x361 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x231; op2val:0xf761; + valaddr_reg:x7; val_offset:188*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 188*FLEN/8, x13, x1, x6) + +inst_119: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x361 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x231 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf761; op2val:0x231; + valaddr_reg:x7; val_offset:190*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 190*FLEN/8, x13, x1, x6) + +inst_120: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x231 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x231; op2val:0x81fb; + valaddr_reg:x7; val_offset:192*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 192*FLEN/8, x13, x1, x6) + +inst_121: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x016 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7816; op2val:0x82fe; + valaddr_reg:x7; val_offset:194*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 194*FLEN/8, x13, x1, x6) + +inst_122: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x231 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x194 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x231; op2val:0xf994; + valaddr_reg:x7; val_offset:196*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 196*FLEN/8, x13, x1, x6) + +inst_123: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x194 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x231 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf994; op2val:0x231; + valaddr_reg:x7; val_offset:198*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 198*FLEN/8, x13, x1, x6) + +inst_124: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x231 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x231; op2val:0x82fe; + valaddr_reg:x7; val_offset:200*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 200*FLEN/8, x13, x1, x6) + +inst_125: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x016 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x064 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7816; op2val:0x8064; + valaddr_reg:x7; val_offset:202*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 202*FLEN/8, x13, x1, x6) + +inst_126: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x038 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x359 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x38; op2val:0xfb59; + valaddr_reg:x7; val_offset:204*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 204*FLEN/8, x13, x1, x6) + +inst_127: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x359 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb59; op2val:0x38; + valaddr_reg:x7; val_offset:206*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 206*FLEN/8, x13, x1, x6) + +inst_128: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x038 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x064 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x38; op2val:0x8064; + valaddr_reg:x7; val_offset:208*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 208*FLEN/8, x13, x1, x6) + +inst_129: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x016 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x038 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7816; op2val:0x38; + valaddr_reg:x7; val_offset:210*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 210*FLEN/8, x13, x1, x6) + +inst_130: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x016 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7816; op2val:0xf0; + valaddr_reg:x7; val_offset:212*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 212*FLEN/8, x13, x1, x6) + +inst_131: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x2b2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x42b2; op2val:0xf0; + valaddr_reg:x7; val_offset:214*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 214*FLEN/8, x13, x1, x6) + +inst_132: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x2b2 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x42b2; + valaddr_reg:x7; val_offset:216*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 216*FLEN/8, x13, x1, x6) + +inst_133: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x016 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x2b2 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7816; op2val:0x42b2; + valaddr_reg:x7; val_offset:218*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 218*FLEN/8, x13, x1, x6) + +inst_134: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x39f and fs2 == 0 and fe2 == 0x1d and fm2 == 0x39f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x779f; op2val:0x779f; + valaddr_reg:x7; val_offset:220*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 220*FLEN/8, x13, x1, x6) + +inst_135: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x39f and fs2 == 0 and fe2 == 0x1d and fm2 == 0x081 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x779f; op2val:0x7481; + valaddr_reg:x7; val_offset:222*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 222*FLEN/8, x13, x1, x6) + +inst_136: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x081 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x39f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7481; op2val:0x779f; + valaddr_reg:x7; val_offset:224*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 224*FLEN/8, x13, x1, x6) + +inst_137: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x39f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x346 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x779f; op2val:0x7b46; + valaddr_reg:x7; val_offset:226*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 226*FLEN/8, x13, x1, x6) + +inst_138: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x346 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x39f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b46; op2val:0x779f; + valaddr_reg:x7; val_offset:228*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 228*FLEN/8, x13, x1, x6) + +inst_139: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x39f and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3bd and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x779f; op2val:0xf3bd; + valaddr_reg:x7; val_offset:230*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 230*FLEN/8, x13, x1, x6) + +inst_140: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3bd and fs2 == 0 and fe2 == 0x1d and fm2 == 0x39f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3bd; op2val:0x779f; + valaddr_reg:x7; val_offset:232*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 232*FLEN/8, x13, x1, x6) + +inst_141: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x39f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0c2 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x779f; op2val:0xf8c2; + valaddr_reg:x7; val_offset:234*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 234*FLEN/8, x13, x1, x6) + +inst_142: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x39f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf8c2; op2val:0x779f; + valaddr_reg:x7; val_offset:236*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 236*FLEN/8, x13, x1, x6) + +inst_143: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x39f and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2a9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x779f; op2val:0xf6a9; + valaddr_reg:x7; val_offset:238*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 238*FLEN/8, x13, x1, x6) + +inst_144: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x2a9 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x39f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf6a9; op2val:0x779f; + valaddr_reg:x7; val_offset:240*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 240*FLEN/8, x13, x1, x6) + +inst_145: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x39f and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3cf and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x779f; op2val:0xf3cf; + valaddr_reg:x7; val_offset:242*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 242*FLEN/8, x13, x1, x6) + +inst_146: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3cf and fs2 == 0 and fe2 == 0x1d and fm2 == 0x39f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3cf; op2val:0x779f; + valaddr_reg:x7; val_offset:244*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 244*FLEN/8, x13, x1, x6) + +inst_147: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x39f and fs2 == 1 and fe2 == 0x19 and fm2 == 0x068 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x779f; op2val:0xe468; + valaddr_reg:x7; val_offset:246*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 246*FLEN/8, x13, x1, x6) + +inst_148: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x218 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x182 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x6a18; op2val:0xf182; + valaddr_reg:x7; val_offset:248*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 248*FLEN/8, x13, x1, x6) + +inst_149: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x182 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x218 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf182; op2val:0x6a18; + valaddr_reg:x7; val_offset:250*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 250*FLEN/8, x13, x1, x6) + +inst_150: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x218 and fs2 == 1 and fe2 == 0x19 and fm2 == 0x068 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x6a18; op2val:0xe468; + valaddr_reg:x7; val_offset:252*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 252*FLEN/8, x13, x1, x6) + +inst_151: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x39f and fs2 == 0 and fe2 == 0x1a and fm2 == 0x218 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x779f; op2val:0x6a18; + valaddr_reg:x7; val_offset:254*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 254*FLEN/8, x13, x1, x6) + +inst_152: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x39f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1ae and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x779f; op2val:0x1ae; + valaddr_reg:x7; val_offset:256*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 256*FLEN/8, x13, x1, x6) + +inst_153: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x20b and fs2 == 0 and fe2 == 0x1d and fm2 == 0x244 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x20b; op2val:0x7644; + valaddr_reg:x7; val_offset:258*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 258*FLEN/8, x13, x1, x6) + +inst_154: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x244 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x20b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7644; op2val:0x20b; + valaddr_reg:x7; val_offset:260*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 260*FLEN/8, x13, x1, x6) + +inst_155: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x20b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1ae and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x20b; op2val:0x1ae; + valaddr_reg:x7; val_offset:262*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 262*FLEN/8, x13, x1, x6) + +inst_156: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x39f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x20b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x779f; op2val:0x20b; + valaddr_reg:x7; val_offset:264*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 264*FLEN/8, x13, x1, x6) + +inst_157: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x39f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x322 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x779f; op2val:0x322; + valaddr_reg:x7; val_offset:266*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 266*FLEN/8, x13, x1, x6) + +inst_158: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x20b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1d5 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x20b; op2val:0x79d5; + valaddr_reg:x7; val_offset:268*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 268*FLEN/8, x13, x1, x6) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_159: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x20b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x79d5; op2val:0x20b; + valaddr_reg:x7; val_offset:270*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 270*FLEN/8, x13, x1, x6) + +inst_160: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x20b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x322 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x20b; op2val:0x322; + valaddr_reg:x7; val_offset:272*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 272*FLEN/8, x13, x1, x6) + +inst_161: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x39f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x779f; op2val:0x3a1; + valaddr_reg:x7; val_offset:274*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 274*FLEN/8, x13, x1, x6) + +inst_162: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x20b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c2 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x20b; op2val:0x7ac2; + valaddr_reg:x7; val_offset:276*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 276*FLEN/8, x13, x1, x6) + +inst_163: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x20b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ac2; op2val:0x20b; + valaddr_reg:x7; val_offset:278*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 278*FLEN/8, x13, x1, x6) + +inst_164: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x20b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x20b; op2val:0x3a1; + valaddr_reg:x7; val_offset:280*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 280*FLEN/8, x13, x1, x6) + +inst_165: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x39f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x278 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x779f; op2val:0x278; + valaddr_reg:x7; val_offset:282*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 282*FLEN/8, x13, x1, x6) + +inst_166: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x20b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x09b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x20b; op2val:0x789b; + valaddr_reg:x7; val_offset:284*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 284*FLEN/8, x13, x1, x6) + +inst_167: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x20b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x789b; op2val:0x20b; + valaddr_reg:x7; val_offset:286*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 286*FLEN/8, x13, x1, x6) + +inst_168: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x20b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x278 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x20b; op2val:0x278; + valaddr_reg:x7; val_offset:288*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 288*FLEN/8, x13, x1, x6) + +inst_169: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x39f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x779f; op2val:0x33d; + valaddr_reg:x7; val_offset:290*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 290*FLEN/8, x13, x1, x6) + +inst_170: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x20b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x208 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x20b; op2val:0x7a08; + valaddr_reg:x7; val_offset:292*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 292*FLEN/8, x13, x1, x6) + +inst_171: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x208 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x20b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a08; op2val:0x20b; + valaddr_reg:x7; val_offset:294*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 294*FLEN/8, x13, x1, x6) + +inst_172: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x20b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x20b; op2val:0x33d; + valaddr_reg:x7; val_offset:296*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 296*FLEN/8, x13, x1, x6) + +inst_173: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x39f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x779f; op2val:0x82f6; + valaddr_reg:x7; val_offset:298*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 298*FLEN/8, x13, x1, x6) + +inst_174: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x20b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x184 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x20b; op2val:0xf984; + valaddr_reg:x7; val_offset:300*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 300*FLEN/8, x13, x1, x6) + +inst_175: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x184 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x20b and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf984; op2val:0x20b; + valaddr_reg:x7; val_offset:302*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 302*FLEN/8, x13, x1, x6) + +inst_176: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x20b; op2val:0x82f6; + valaddr_reg:x7; val_offset:304*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 304*FLEN/8, x13, x1, x6) + +inst_177: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x39f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x779f; op2val:0x82c9; + valaddr_reg:x7; val_offset:306*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 306*FLEN/8, x13, x1, x6) + +inst_178: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x20b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x130 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x20b; op2val:0xf930; + valaddr_reg:x7; val_offset:308*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 308*FLEN/8, x13, x1, x6) + +inst_179: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x130 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x20b and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf930; op2val:0x20b; + valaddr_reg:x7; val_offset:310*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 310*FLEN/8, x13, x1, x6) + +inst_180: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x20b; op2val:0x82c9; + valaddr_reg:x7; val_offset:312*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 312*FLEN/8, x13, x1, x6) + +inst_181: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x39f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x779f; op2val:0x81fb; + valaddr_reg:x7; val_offset:314*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 314*FLEN/8, x13, x1, x6) + +inst_182: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x20b and fs2 == 1 and fe2 == 0x1d and fm2 == 0x361 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x20b; op2val:0xf761; + valaddr_reg:x7; val_offset:316*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 316*FLEN/8, x13, x1, x6) + +inst_183: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x361 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x20b and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf761; op2val:0x20b; + valaddr_reg:x7; val_offset:318*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 318*FLEN/8, x13, x1, x6) + +inst_184: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x20b; op2val:0x81fb; + valaddr_reg:x7; val_offset:320*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 320*FLEN/8, x13, x1, x6) + +inst_185: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x39f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x779f; op2val:0x82fe; + valaddr_reg:x7; val_offset:322*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 322*FLEN/8, x13, x1, x6) + +inst_186: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x20b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x194 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x20b; op2val:0xf994; + valaddr_reg:x7; val_offset:324*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 324*FLEN/8, x13, x1, x6) + +inst_187: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x194 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x20b and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf994; op2val:0x20b; + valaddr_reg:x7; val_offset:326*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 326*FLEN/8, x13, x1, x6) + +inst_188: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x20b; op2val:0x82fe; + valaddr_reg:x7; val_offset:328*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 328*FLEN/8, x13, x1, x6) + +inst_189: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x39f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x064 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x779f; op2val:0x8064; + valaddr_reg:x7; val_offset:330*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 330*FLEN/8, x13, x1, x6) + +inst_190: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x034 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x359 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x34; op2val:0xfb59; + valaddr_reg:x7; val_offset:332*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 332*FLEN/8, x13, x1, x6) + +inst_191: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x359 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x034 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb59; op2val:0x34; + valaddr_reg:x7; val_offset:334*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 334*FLEN/8, x13, x1, x6) + +inst_192: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x034 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x064 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x34; op2val:0x8064; + valaddr_reg:x7; val_offset:336*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 336*FLEN/8, x13, x1, x6) + +inst_193: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x39f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x034 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x779f; op2val:0x34; + valaddr_reg:x7; val_offset:338*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 338*FLEN/8, x13, x1, x6) + +inst_194: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x39f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x779f; op2val:0xf0; + valaddr_reg:x7; val_offset:340*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 340*FLEN/8, x13, x1, x6) + +inst_195: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x23e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x423e; op2val:0xf0; + valaddr_reg:x7; val_offset:342*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 342*FLEN/8, x13, x1, x6) + +inst_196: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x23e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x423e; + valaddr_reg:x7; val_offset:344*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 344*FLEN/8, x13, x1, x6) + +inst_197: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x39f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x23e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x779f; op2val:0x423e; + valaddr_reg:x7; val_offset:346*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 346*FLEN/8, x13, x1, x6) + +inst_198: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x081 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x081 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7481; op2val:0x7481; + valaddr_reg:x7; val_offset:348*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 348*FLEN/8, x13, x1, x6) + +inst_199: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x081 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x346 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7481; op2val:0x7b46; + valaddr_reg:x7; val_offset:350*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 350*FLEN/8, x13, x1, x6) + +inst_200: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x346 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x081 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b46; op2val:0x7481; + valaddr_reg:x7; val_offset:352*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 352*FLEN/8, x13, x1, x6) + +inst_201: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x081 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3bd and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7481; op2val:0xf3bd; + valaddr_reg:x7; val_offset:354*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 354*FLEN/8, x13, x1, x6) + +inst_202: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3bd and fs2 == 0 and fe2 == 0x1d and fm2 == 0x081 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3bd; op2val:0x7481; + valaddr_reg:x7; val_offset:356*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 356*FLEN/8, x13, x1, x6) + +inst_203: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x081 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0c2 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7481; op2val:0xf8c2; + valaddr_reg:x7; val_offset:358*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 358*FLEN/8, x13, x1, x6) + +inst_204: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x081 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf8c2; op2val:0x7481; + valaddr_reg:x7; val_offset:360*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 360*FLEN/8, x13, x1, x6) + +inst_205: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x081 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2a9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7481; op2val:0xf6a9; + valaddr_reg:x7; val_offset:362*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 362*FLEN/8, x13, x1, x6) + +inst_206: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x2a9 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x081 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf6a9; op2val:0x7481; + valaddr_reg:x7; val_offset:364*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 364*FLEN/8, x13, x1, x6) + +inst_207: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x081 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3cf and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7481; op2val:0xf3cf; + valaddr_reg:x7; val_offset:366*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 366*FLEN/8, x13, x1, x6) + +inst_208: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3cf and fs2 == 0 and fe2 == 0x1d and fm2 == 0x081 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3cf; op2val:0x7481; + valaddr_reg:x7; val_offset:368*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 368*FLEN/8, x13, x1, x6) + +inst_209: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x081 and fs2 == 1 and fe2 == 0x19 and fm2 == 0x068 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7481; op2val:0xe468; + valaddr_reg:x7; val_offset:370*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 370*FLEN/8, x13, x1, x6) + +inst_210: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x336 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x182 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x6736; op2val:0xf182; + valaddr_reg:x7; val_offset:372*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 372*FLEN/8, x13, x1, x6) + +inst_211: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x182 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x336 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf182; op2val:0x6736; + valaddr_reg:x7; val_offset:374*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 374*FLEN/8, x13, x1, x6) + +inst_212: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x336 and fs2 == 1 and fe2 == 0x19 and fm2 == 0x068 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x6736; op2val:0xe468; + valaddr_reg:x7; val_offset:376*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 376*FLEN/8, x13, x1, x6) + +inst_213: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x081 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x336 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7481; op2val:0x6736; + valaddr_reg:x7; val_offset:378*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 378*FLEN/8, x13, x1, x6) + +inst_214: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x081 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1ae and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7481; op2val:0x1ae; + valaddr_reg:x7; val_offset:380*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 380*FLEN/8, x13, x1, x6) + +inst_215: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x135 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x244 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x135; op2val:0x7644; + valaddr_reg:x7; val_offset:382*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 382*FLEN/8, x13, x1, x6) + +inst_216: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x244 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x135 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7644; op2val:0x135; + valaddr_reg:x7; val_offset:384*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 384*FLEN/8, x13, x1, x6) + +inst_217: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x135 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1ae and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x135; op2val:0x1ae; + valaddr_reg:x7; val_offset:386*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 386*FLEN/8, x13, x1, x6) + +inst_218: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x081 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x135 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7481; op2val:0x135; + valaddr_reg:x7; val_offset:388*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 388*FLEN/8, x13, x1, x6) + +inst_219: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x081 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x322 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7481; op2val:0x322; + valaddr_reg:x7; val_offset:390*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 390*FLEN/8, x13, x1, x6) + +inst_220: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x135 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1d5 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x135; op2val:0x79d5; + valaddr_reg:x7; val_offset:392*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 392*FLEN/8, x13, x1, x6) + +inst_221: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x135 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x79d5; op2val:0x135; + valaddr_reg:x7; val_offset:394*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 394*FLEN/8, x13, x1, x6) + +inst_222: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x135 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x322 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x135; op2val:0x322; + valaddr_reg:x7; val_offset:396*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 396*FLEN/8, x13, x1, x6) + +inst_223: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x081 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7481; op2val:0x3a1; + valaddr_reg:x7; val_offset:398*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 398*FLEN/8, x13, x1, x6) + +inst_224: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x135 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c2 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x135; op2val:0x7ac2; + valaddr_reg:x7; val_offset:400*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 400*FLEN/8, x13, x1, x6) + +inst_225: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x135 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ac2; op2val:0x135; + valaddr_reg:x7; val_offset:402*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 402*FLEN/8, x13, x1, x6) + +inst_226: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x135 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x135; op2val:0x3a1; + valaddr_reg:x7; val_offset:404*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 404*FLEN/8, x13, x1, x6) + +inst_227: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x081 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x278 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7481; op2val:0x278; + valaddr_reg:x7; val_offset:406*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 406*FLEN/8, x13, x1, x6) + +inst_228: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x135 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x09b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x135; op2val:0x789b; + valaddr_reg:x7; val_offset:408*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 408*FLEN/8, x13, x1, x6) + +inst_229: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x135 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x789b; op2val:0x135; + valaddr_reg:x7; val_offset:410*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 410*FLEN/8, x13, x1, x6) + +inst_230: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x135 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x278 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x135; op2val:0x278; + valaddr_reg:x7; val_offset:412*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 412*FLEN/8, x13, x1, x6) + +inst_231: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x081 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7481; op2val:0x33d; + valaddr_reg:x7; val_offset:414*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 414*FLEN/8, x13, x1, x6) + +inst_232: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x135 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x208 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x135; op2val:0x7a08; + valaddr_reg:x7; val_offset:416*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 416*FLEN/8, x13, x1, x6) + +inst_233: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x208 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x135 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a08; op2val:0x135; + valaddr_reg:x7; val_offset:418*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 418*FLEN/8, x13, x1, x6) + +inst_234: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x135 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x135; op2val:0x33d; + valaddr_reg:x7; val_offset:420*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 420*FLEN/8, x13, x1, x6) + +inst_235: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x081 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7481; op2val:0x82f6; + valaddr_reg:x7; val_offset:422*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 422*FLEN/8, x13, x1, x6) + +inst_236: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x135 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x184 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x135; op2val:0xf984; + valaddr_reg:x7; val_offset:424*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 424*FLEN/8, x13, x1, x6) + +inst_237: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x184 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x135 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf984; op2val:0x135; + valaddr_reg:x7; val_offset:426*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 426*FLEN/8, x13, x1, x6) + +inst_238: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x135 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x135; op2val:0x82f6; + valaddr_reg:x7; val_offset:428*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 428*FLEN/8, x13, x1, x6) + +inst_239: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x081 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7481; op2val:0x82c9; + valaddr_reg:x7; val_offset:430*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 430*FLEN/8, x13, x1, x6) + +inst_240: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x135 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x130 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x135; op2val:0xf930; + valaddr_reg:x7; val_offset:432*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 432*FLEN/8, x13, x1, x6) + +inst_241: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x130 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x135 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf930; op2val:0x135; + valaddr_reg:x7; val_offset:434*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 434*FLEN/8, x13, x1, x6) + +inst_242: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x135 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x135; op2val:0x82c9; + valaddr_reg:x7; val_offset:436*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 436*FLEN/8, x13, x1, x6) + +inst_243: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x081 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7481; op2val:0x81fb; + valaddr_reg:x7; val_offset:438*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 438*FLEN/8, x13, x1, x6) + +inst_244: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x135 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x361 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x135; op2val:0xf761; + valaddr_reg:x7; val_offset:440*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 440*FLEN/8, x13, x1, x6) + +inst_245: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x361 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x135 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf761; op2val:0x135; + valaddr_reg:x7; val_offset:442*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 442*FLEN/8, x13, x1, x6) + +inst_246: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x135 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x135; op2val:0x81fb; + valaddr_reg:x7; val_offset:444*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 444*FLEN/8, x13, x1, x6) + +inst_247: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x081 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7481; op2val:0x82fe; + valaddr_reg:x7; val_offset:446*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 446*FLEN/8, x13, x1, x6) + +inst_248: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x135 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x194 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x135; op2val:0xf994; + valaddr_reg:x7; val_offset:448*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 448*FLEN/8, x13, x1, x6) + +inst_249: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x194 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x135 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf994; op2val:0x135; + valaddr_reg:x7; val_offset:450*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 450*FLEN/8, x13, x1, x6) + +inst_250: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x135 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x135; op2val:0x82fe; + valaddr_reg:x7; val_offset:452*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 452*FLEN/8, x13, x1, x6) + +inst_251: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x081 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x064 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7481; op2val:0x8064; + valaddr_reg:x7; val_offset:454*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 454*FLEN/8, x13, x1, x6) + +inst_252: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x01e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x359 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x1e; op2val:0xfb59; + valaddr_reg:x7; val_offset:456*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 456*FLEN/8, x13, x1, x6) + +inst_253: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x359 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x01e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb59; op2val:0x1e; + valaddr_reg:x7; val_offset:458*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 458*FLEN/8, x13, x1, x6) + +inst_254: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x01e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x064 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x1e; op2val:0x8064; + valaddr_reg:x7; val_offset:460*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 460*FLEN/8, x13, x1, x6) + +inst_255: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x081 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x01e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7481; op2val:0x1e; + valaddr_reg:x7; val_offset:462*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 462*FLEN/8, x13, x1, x6) + +inst_256: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x081 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7481; op2val:0xf0; + valaddr_reg:x7; val_offset:464*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 464*FLEN/8, x13, x1, x6) + +inst_257: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x362 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3f62; op2val:0xf0; + valaddr_reg:x7; val_offset:466*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 466*FLEN/8, x13, x1, x6) + +inst_258: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x362 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x3f62; + valaddr_reg:x7; val_offset:468*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 468*FLEN/8, x13, x1, x6) + +inst_259: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x081 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x362 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7481; op2val:0x3f62; + valaddr_reg:x7; val_offset:470*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 470*FLEN/8, x13, x1, x6) + +inst_260: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x346 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x346 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b46; op2val:0x7b46; + valaddr_reg:x7; val_offset:472*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 472*FLEN/8, x13, x1, x6) + +inst_261: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x346 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3bd and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b46; op2val:0xf3bd; + valaddr_reg:x7; val_offset:474*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 474*FLEN/8, x13, x1, x6) + +inst_262: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3bd and fs2 == 0 and fe2 == 0x1e and fm2 == 0x346 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3bd; op2val:0x7b46; + valaddr_reg:x7; val_offset:476*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 476*FLEN/8, x13, x1, x6) + +inst_263: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x346 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0c2 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b46; op2val:0xf8c2; + valaddr_reg:x7; val_offset:478*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 478*FLEN/8, x13, x1, x6) + +inst_264: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x346 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf8c2; op2val:0x7b46; + valaddr_reg:x7; val_offset:480*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 480*FLEN/8, x13, x1, x6) + +inst_265: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x346 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2a9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b46; op2val:0xf6a9; + valaddr_reg:x7; val_offset:482*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 482*FLEN/8, x13, x1, x6) + +inst_266: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x2a9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x346 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf6a9; op2val:0x7b46; + valaddr_reg:x7; val_offset:484*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 484*FLEN/8, x13, x1, x6) + +inst_267: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x346 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3cf and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b46; op2val:0xf3cf; + valaddr_reg:x7; val_offset:486*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 486*FLEN/8, x13, x1, x6) + +inst_268: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3cf and fs2 == 0 and fe2 == 0x1e and fm2 == 0x346 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3cf; op2val:0x7b46; + valaddr_reg:x7; val_offset:488*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 488*FLEN/8, x13, x1, x6) + +inst_269: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x346 and fs2 == 1 and fe2 == 0x19 and fm2 == 0x068 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b46; op2val:0xe468; + valaddr_reg:x7; val_offset:490*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 490*FLEN/8, x13, x1, x6) + +inst_270: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1d1 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x182 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x6dd1; op2val:0xf182; + valaddr_reg:x7; val_offset:492*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 492*FLEN/8, x13, x1, x6) + +inst_271: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x182 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x1d1 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf182; op2val:0x6dd1; + valaddr_reg:x7; val_offset:494*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 494*FLEN/8, x13, x1, x6) + +inst_272: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1d1 and fs2 == 1 and fe2 == 0x19 and fm2 == 0x068 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x6dd1; op2val:0xe468; + valaddr_reg:x7; val_offset:496*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 496*FLEN/8, x13, x1, x6) + +inst_273: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x346 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x1d1 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b46; op2val:0x6dd1; + valaddr_reg:x7; val_offset:498*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 498*FLEN/8, x13, x1, x6) + +inst_274: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x346 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1ae and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b46; op2val:0x1ae; + valaddr_reg:x7; val_offset:500*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 500*FLEN/8, x13, x1, x6) + +inst_275: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3e7 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x244 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3e7; op2val:0x7644; + valaddr_reg:x7; val_offset:502*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 502*FLEN/8, x13, x1, x6) + +inst_276: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x244 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3e7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7644; op2val:0x3e7; + valaddr_reg:x7; val_offset:504*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 504*FLEN/8, x13, x1, x6) + +inst_277: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3e7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1ae and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3e7; op2val:0x1ae; + valaddr_reg:x7; val_offset:506*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 506*FLEN/8, x13, x1, x6) + +inst_278: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x346 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3e7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b46; op2val:0x3e7; + valaddr_reg:x7; val_offset:508*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 508*FLEN/8, x13, x1, x6) + +inst_279: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x346 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x322 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b46; op2val:0x322; + valaddr_reg:x7; val_offset:510*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 510*FLEN/8, x13, x1, x6) + +inst_280: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3e7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1d5 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3e7; op2val:0x79d5; + valaddr_reg:x7; val_offset:512*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 512*FLEN/8, x13, x1, x6) + +inst_281: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3e7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x79d5; op2val:0x3e7; + valaddr_reg:x7; val_offset:514*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 514*FLEN/8, x13, x1, x6) + +inst_282: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3e7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x322 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3e7; op2val:0x322; + valaddr_reg:x7; val_offset:516*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 516*FLEN/8, x13, x1, x6) + +inst_283: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x346 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b46; op2val:0x3a1; + valaddr_reg:x7; val_offset:518*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 518*FLEN/8, x13, x1, x6) + +inst_284: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3e7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c2 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3e7; op2val:0x7ac2; + valaddr_reg:x7; val_offset:520*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 520*FLEN/8, x13, x1, x6) + +inst_285: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3e7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ac2; op2val:0x3e7; + valaddr_reg:x7; val_offset:522*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 522*FLEN/8, x13, x1, x6) + +inst_286: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3e7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3e7; op2val:0x3a1; + valaddr_reg:x7; val_offset:524*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 524*FLEN/8, x13, x1, x6) +RVTEST_SIGBASE(x1,signature_x1_2) + +inst_287: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x346 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x278 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b46; op2val:0x278; + valaddr_reg:x7; val_offset:526*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 526*FLEN/8, x13, x1, x6) + +inst_288: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3e7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x09b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3e7; op2val:0x789b; + valaddr_reg:x7; val_offset:528*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 528*FLEN/8, x13, x1, x6) + +inst_289: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3e7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x789b; op2val:0x3e7; + valaddr_reg:x7; val_offset:530*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 530*FLEN/8, x13, x1, x6) + +inst_290: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3e7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x278 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3e7; op2val:0x278; + valaddr_reg:x7; val_offset:532*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 532*FLEN/8, x13, x1, x6) + +inst_291: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x346 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b46; op2val:0x33d; + valaddr_reg:x7; val_offset:534*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 534*FLEN/8, x13, x1, x6) + +inst_292: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3e7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x208 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3e7; op2val:0x7a08; + valaddr_reg:x7; val_offset:536*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 536*FLEN/8, x13, x1, x6) + +inst_293: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x208 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3e7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a08; op2val:0x3e7; + valaddr_reg:x7; val_offset:538*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 538*FLEN/8, x13, x1, x6) + +inst_294: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3e7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3e7; op2val:0x33d; + valaddr_reg:x7; val_offset:540*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 540*FLEN/8, x13, x1, x6) + +inst_295: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x346 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b46; op2val:0x82f6; + valaddr_reg:x7; val_offset:542*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 542*FLEN/8, x13, x1, x6) + +inst_296: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3e7 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x184 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3e7; op2val:0xf984; + valaddr_reg:x7; val_offset:544*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 544*FLEN/8, x13, x1, x6) + +inst_297: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x184 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3e7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf984; op2val:0x3e7; + valaddr_reg:x7; val_offset:546*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 546*FLEN/8, x13, x1, x6) + +inst_298: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3e7; op2val:0x82f6; + valaddr_reg:x7; val_offset:548*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 548*FLEN/8, x13, x1, x6) + +inst_299: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x346 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b46; op2val:0x82c9; + valaddr_reg:x7; val_offset:550*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 550*FLEN/8, x13, x1, x6) + +inst_300: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3e7 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x130 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3e7; op2val:0xf930; + valaddr_reg:x7; val_offset:552*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 552*FLEN/8, x13, x1, x6) + +inst_301: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x130 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3e7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf930; op2val:0x3e7; + valaddr_reg:x7; val_offset:554*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 554*FLEN/8, x13, x1, x6) + +inst_302: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3e7; op2val:0x82c9; + valaddr_reg:x7; val_offset:556*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 556*FLEN/8, x13, x1, x6) + +inst_303: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x346 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b46; op2val:0x81fb; + valaddr_reg:x7; val_offset:558*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 558*FLEN/8, x13, x1, x6) + +inst_304: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3e7 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x361 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3e7; op2val:0xf761; + valaddr_reg:x7; val_offset:560*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 560*FLEN/8, x13, x1, x6) + +inst_305: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x361 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3e7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf761; op2val:0x3e7; + valaddr_reg:x7; val_offset:562*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 562*FLEN/8, x13, x1, x6) + +inst_306: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3e7; op2val:0x81fb; + valaddr_reg:x7; val_offset:564*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 564*FLEN/8, x13, x1, x6) + +inst_307: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x346 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b46; op2val:0x82fe; + valaddr_reg:x7; val_offset:566*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 566*FLEN/8, x13, x1, x6) + +inst_308: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3e7 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x194 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3e7; op2val:0xf994; + valaddr_reg:x7; val_offset:568*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 568*FLEN/8, x13, x1, x6) + +inst_309: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x194 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3e7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf994; op2val:0x3e7; + valaddr_reg:x7; val_offset:570*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 570*FLEN/8, x13, x1, x6) + +inst_310: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3e7; op2val:0x82fe; + valaddr_reg:x7; val_offset:572*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 572*FLEN/8, x13, x1, x6) + +inst_311: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x346 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x064 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b46; op2val:0x8064; + valaddr_reg:x7; val_offset:574*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 574*FLEN/8, x13, x1, x6) + +inst_312: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x063 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x359 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x63; op2val:0xfb59; + valaddr_reg:x7; val_offset:576*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 576*FLEN/8, x13, x1, x6) + +inst_313: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x359 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x063 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb59; op2val:0x63; + valaddr_reg:x7; val_offset:578*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 578*FLEN/8, x13, x1, x6) + +inst_314: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x063 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x064 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x63; op2val:0x8064; + valaddr_reg:x7; val_offset:580*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 580*FLEN/8, x13, x1, x6) + +inst_315: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x346 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x063 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b46; op2val:0x63; + valaddr_reg:x7; val_offset:582*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 582*FLEN/8, x13, x1, x6) + +inst_316: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x346 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b46; op2val:0xf0; + valaddr_reg:x7; val_offset:584*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 584*FLEN/8, x13, x1, x6) + +inst_317: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x1f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x45f5; op2val:0xf0; + valaddr_reg:x7; val_offset:586*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 586*FLEN/8, x13, x1, x6) + +inst_318: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1f5 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x45f5; + valaddr_reg:x7; val_offset:588*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 588*FLEN/8, x13, x1, x6) + +inst_319: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x346 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1f5 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b46; op2val:0x45f5; + valaddr_reg:x7; val_offset:590*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 590*FLEN/8, x13, x1, x6) + +inst_320: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3bd and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3bd and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3bd; op2val:0xf3bd; + valaddr_reg:x7; val_offset:592*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 592*FLEN/8, x13, x1, x6) + +inst_321: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3bd and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0c2 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3bd; op2val:0xf8c2; + valaddr_reg:x7; val_offset:594*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 594*FLEN/8, x13, x1, x6) + +inst_322: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3bd and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf8c2; op2val:0xf3bd; + valaddr_reg:x7; val_offset:596*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 596*FLEN/8, x13, x1, x6) + +inst_323: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3bd and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2a9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3bd; op2val:0xf6a9; + valaddr_reg:x7; val_offset:598*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 598*FLEN/8, x13, x1, x6) + +inst_324: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x2a9 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3bd and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf6a9; op2val:0xf3bd; + valaddr_reg:x7; val_offset:600*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 600*FLEN/8, x13, x1, x6) + +inst_325: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3bd and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3cf and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3bd; op2val:0xf3cf; + valaddr_reg:x7; val_offset:602*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 602*FLEN/8, x13, x1, x6) + +inst_326: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3cf and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3bd and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3cf; op2val:0xf3bd; + valaddr_reg:x7; val_offset:604*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 604*FLEN/8, x13, x1, x6) + +inst_327: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3bd and fs2 == 1 and fe2 == 0x19 and fm2 == 0x068 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3bd; op2val:0xe468; + valaddr_reg:x7; val_offset:606*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 606*FLEN/8, x13, x1, x6) + +inst_328: +// fs1 == 1 and fe1 == 0x19 and fm1 == 0x231 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x182 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xe631; op2val:0xf182; + valaddr_reg:x7; val_offset:608*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 608*FLEN/8, x13, x1, x6) + +inst_329: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x182 and fs2 == 1 and fe2 == 0x19 and fm2 == 0x231 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf182; op2val:0xe631; + valaddr_reg:x7; val_offset:610*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 610*FLEN/8, x13, x1, x6) + +inst_330: +// fs1 == 1 and fe1 == 0x19 and fm1 == 0x231 and fs2 == 1 and fe2 == 0x19 and fm2 == 0x068 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xe631; op2val:0xe468; + valaddr_reg:x7; val_offset:612*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 612*FLEN/8, x13, x1, x6) + +inst_331: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3bd and fs2 == 1 and fe2 == 0x19 and fm2 == 0x231 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3bd; op2val:0xe631; + valaddr_reg:x7; val_offset:614*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 614*FLEN/8, x13, x1, x6) + +inst_332: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3bd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1ae and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3bd; op2val:0x1ae; + valaddr_reg:x7; val_offset:616*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 616*FLEN/8, x13, x1, x6) + +inst_333: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x10a and fs2 == 0 and fe2 == 0x1d and fm2 == 0x244 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x810a; op2val:0x7644; + valaddr_reg:x7; val_offset:618*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 618*FLEN/8, x13, x1, x6) + +inst_334: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x244 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x10a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7644; op2val:0x810a; + valaddr_reg:x7; val_offset:620*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 620*FLEN/8, x13, x1, x6) + +inst_335: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x10a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1ae and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x810a; op2val:0x1ae; + valaddr_reg:x7; val_offset:622*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 622*FLEN/8, x13, x1, x6) + +inst_336: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x10a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3bd; op2val:0x810a; + valaddr_reg:x7; val_offset:624*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 624*FLEN/8, x13, x1, x6) + +inst_337: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3bd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x322 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3bd; op2val:0x322; + valaddr_reg:x7; val_offset:626*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 626*FLEN/8, x13, x1, x6) + +inst_338: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x10a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1d5 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x810a; op2val:0x79d5; + valaddr_reg:x7; val_offset:628*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 628*FLEN/8, x13, x1, x6) + +inst_339: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x10a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x79d5; op2val:0x810a; + valaddr_reg:x7; val_offset:630*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 630*FLEN/8, x13, x1, x6) + +inst_340: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x10a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x322 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x810a; op2val:0x322; + valaddr_reg:x7; val_offset:632*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 632*FLEN/8, x13, x1, x6) + +inst_341: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3bd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3bd; op2val:0x3a1; + valaddr_reg:x7; val_offset:634*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 634*FLEN/8, x13, x1, x6) + +inst_342: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x10a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c2 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x810a; op2val:0x7ac2; + valaddr_reg:x7; val_offset:636*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 636*FLEN/8, x13, x1, x6) + +inst_343: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x10a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ac2; op2val:0x810a; + valaddr_reg:x7; val_offset:638*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 638*FLEN/8, x13, x1, x6) + +inst_344: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x10a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x810a; op2val:0x3a1; + valaddr_reg:x7; val_offset:640*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 640*FLEN/8, x13, x1, x6) + +inst_345: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3bd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x278 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3bd; op2val:0x278; + valaddr_reg:x7; val_offset:642*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 642*FLEN/8, x13, x1, x6) + +inst_346: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x10a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x09b and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x810a; op2val:0x789b; + valaddr_reg:x7; val_offset:644*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 644*FLEN/8, x13, x1, x6) + +inst_347: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x10a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x789b; op2val:0x810a; + valaddr_reg:x7; val_offset:646*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 646*FLEN/8, x13, x1, x6) + +inst_348: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x10a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x278 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x810a; op2val:0x278; + valaddr_reg:x7; val_offset:648*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 648*FLEN/8, x13, x1, x6) + +inst_349: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3bd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3bd; op2val:0x33d; + valaddr_reg:x7; val_offset:650*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 650*FLEN/8, x13, x1, x6) + +inst_350: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x10a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x208 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x810a; op2val:0x7a08; + valaddr_reg:x7; val_offset:652*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 652*FLEN/8, x13, x1, x6) + +inst_351: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x208 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x10a and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a08; op2val:0x810a; + valaddr_reg:x7; val_offset:654*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 654*FLEN/8, x13, x1, x6) + +inst_352: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x10a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x810a; op2val:0x33d; + valaddr_reg:x7; val_offset:656*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 656*FLEN/8, x13, x1, x6) + +inst_353: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3bd; op2val:0x82f6; + valaddr_reg:x7; val_offset:658*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 658*FLEN/8, x13, x1, x6) + +inst_354: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x10a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x184 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x810a; op2val:0xf984; + valaddr_reg:x7; val_offset:660*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 660*FLEN/8, x13, x1, x6) + +inst_355: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x184 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x10a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf984; op2val:0x810a; + valaddr_reg:x7; val_offset:662*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 662*FLEN/8, x13, x1, x6) + +inst_356: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x10a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x810a; op2val:0x82f6; + valaddr_reg:x7; val_offset:664*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 664*FLEN/8, x13, x1, x6) + +inst_357: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3bd; op2val:0x82c9; + valaddr_reg:x7; val_offset:666*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 666*FLEN/8, x13, x1, x6) + +inst_358: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x10a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x130 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x810a; op2val:0xf930; + valaddr_reg:x7; val_offset:668*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 668*FLEN/8, x13, x1, x6) + +inst_359: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x130 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x10a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf930; op2val:0x810a; + valaddr_reg:x7; val_offset:670*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 670*FLEN/8, x13, x1, x6) + +inst_360: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x10a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x810a; op2val:0x82c9; + valaddr_reg:x7; val_offset:672*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 672*FLEN/8, x13, x1, x6) + +inst_361: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3bd; op2val:0x81fb; + valaddr_reg:x7; val_offset:674*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 674*FLEN/8, x13, x1, x6) + +inst_362: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x10a and fs2 == 1 and fe2 == 0x1d and fm2 == 0x361 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x810a; op2val:0xf761; + valaddr_reg:x7; val_offset:676*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 676*FLEN/8, x13, x1, x6) + +inst_363: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x361 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x10a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf761; op2val:0x810a; + valaddr_reg:x7; val_offset:678*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 678*FLEN/8, x13, x1, x6) + +inst_364: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x10a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x810a; op2val:0x81fb; + valaddr_reg:x7; val_offset:680*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 680*FLEN/8, x13, x1, x6) + +inst_365: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3bd; op2val:0x82fe; + valaddr_reg:x7; val_offset:682*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 682*FLEN/8, x13, x1, x6) + +inst_366: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x10a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x194 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x810a; op2val:0xf994; + valaddr_reg:x7; val_offset:684*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 684*FLEN/8, x13, x1, x6) + +inst_367: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x194 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x10a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf994; op2val:0x810a; + valaddr_reg:x7; val_offset:686*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 686*FLEN/8, x13, x1, x6) + +inst_368: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x10a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x810a; op2val:0x82fe; + valaddr_reg:x7; val_offset:688*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 688*FLEN/8, x13, x1, x6) + +inst_369: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x064 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3bd; op2val:0x8064; + valaddr_reg:x7; val_offset:690*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 690*FLEN/8, x13, x1, x6) + +inst_370: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x01a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x359 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x801a; op2val:0xfb59; + valaddr_reg:x7; val_offset:692*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 692*FLEN/8, x13, x1, x6) + +inst_371: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x359 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x01a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb59; op2val:0x801a; + valaddr_reg:x7; val_offset:694*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 694*FLEN/8, x13, x1, x6) + +inst_372: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x01a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x064 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x801a; op2val:0x8064; + valaddr_reg:x7; val_offset:696*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 696*FLEN/8, x13, x1, x6) + +inst_373: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x01a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3bd; op2val:0x801a; + valaddr_reg:x7; val_offset:698*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 698*FLEN/8, x13, x1, x6) + +inst_374: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3bd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3bd; op2val:0xf0; + valaddr_reg:x7; val_offset:700*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 700*FLEN/8, x13, x1, x6) + +inst_375: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x257 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xbe57; op2val:0xf0; + valaddr_reg:x7; val_offset:702*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 702*FLEN/8, x13, x1, x6) + +inst_376: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x257 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xbe57; + valaddr_reg:x7; val_offset:704*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 704*FLEN/8, x13, x1, x6) + +inst_377: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3bd and fs2 == 1 and fe2 == 0x0f and fm2 == 0x257 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3bd; op2val:0xbe57; + valaddr_reg:x7; val_offset:706*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 706*FLEN/8, x13, x1, x6) + +inst_378: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0c2 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf8c2; op2val:0xf8c2; + valaddr_reg:x7; val_offset:708*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 708*FLEN/8, x13, x1, x6) + +inst_379: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2a9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf8c2; op2val:0xf6a9; + valaddr_reg:x7; val_offset:710*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 710*FLEN/8, x13, x1, x6) + +inst_380: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x2a9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0c2 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf6a9; op2val:0xf8c2; + valaddr_reg:x7; val_offset:712*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 712*FLEN/8, x13, x1, x6) + +inst_381: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3cf and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf8c2; op2val:0xf3cf; + valaddr_reg:x7; val_offset:714*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 714*FLEN/8, x13, x1, x6) + +inst_382: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3cf and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0c2 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3cf; op2val:0xf8c2; + valaddr_reg:x7; val_offset:716*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 716*FLEN/8, x13, x1, x6) + +inst_383: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 1 and fe2 == 0x19 and fm2 == 0x068 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf8c2; op2val:0xe468; + valaddr_reg:x7; val_offset:718*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 718*FLEN/8, x13, x1, x6) + +inst_384: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x39c and fs2 == 1 and fe2 == 0x1c and fm2 == 0x182 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xeb9c; op2val:0xf182; + valaddr_reg:x7; val_offset:720*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 720*FLEN/8, x13, x1, x6) + +inst_385: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x182 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x39c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf182; op2val:0xeb9c; + valaddr_reg:x7; val_offset:722*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 722*FLEN/8, x13, x1, x6) + +inst_386: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x39c and fs2 == 1 and fe2 == 0x19 and fm2 == 0x068 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xeb9c; op2val:0xe468; + valaddr_reg:x7; val_offset:724*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 724*FLEN/8, x13, x1, x6) + +inst_387: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x39c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf8c2; op2val:0xeb9c; + valaddr_reg:x7; val_offset:726*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 726*FLEN/8, x13, x1, x6) + +inst_388: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1ae and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf8c2; op2val:0x1ae; + valaddr_reg:x7; val_offset:728*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 728*FLEN/8, x13, x1, x6) + +inst_389: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x28d and fs2 == 0 and fe2 == 0x1d and fm2 == 0x244 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x828d; op2val:0x7644; + valaddr_reg:x7; val_offset:730*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 730*FLEN/8, x13, x1, x6) + +inst_390: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x244 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x28d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7644; op2val:0x828d; + valaddr_reg:x7; val_offset:732*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 732*FLEN/8, x13, x1, x6) + +inst_391: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x28d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1ae and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x828d; op2val:0x1ae; + valaddr_reg:x7; val_offset:734*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 734*FLEN/8, x13, x1, x6) + +inst_392: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x28d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf8c2; op2val:0x828d; + valaddr_reg:x7; val_offset:736*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 736*FLEN/8, x13, x1, x6) + +inst_393: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x322 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf8c2; op2val:0x322; + valaddr_reg:x7; val_offset:738*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 738*FLEN/8, x13, x1, x6) + +inst_394: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x28d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1d5 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x828d; op2val:0x79d5; + valaddr_reg:x7; val_offset:740*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 740*FLEN/8, x13, x1, x6) + +inst_395: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x28d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x79d5; op2val:0x828d; + valaddr_reg:x7; val_offset:742*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 742*FLEN/8, x13, x1, x6) + +inst_396: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x28d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x322 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x828d; op2val:0x322; + valaddr_reg:x7; val_offset:744*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 744*FLEN/8, x13, x1, x6) + +inst_397: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf8c2; op2val:0x3a1; + valaddr_reg:x7; val_offset:746*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 746*FLEN/8, x13, x1, x6) + +inst_398: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x28d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c2 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x828d; op2val:0x7ac2; + valaddr_reg:x7; val_offset:748*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 748*FLEN/8, x13, x1, x6) + +inst_399: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x28d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ac2; op2val:0x828d; + valaddr_reg:x7; val_offset:750*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 750*FLEN/8, x13, x1, x6) + +inst_400: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x28d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x828d; op2val:0x3a1; + valaddr_reg:x7; val_offset:752*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 752*FLEN/8, x13, x1, x6) + +inst_401: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x278 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf8c2; op2val:0x278; + valaddr_reg:x7; val_offset:754*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 754*FLEN/8, x13, x1, x6) + +inst_402: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x28d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x09b and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x828d; op2val:0x789b; + valaddr_reg:x7; val_offset:756*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 756*FLEN/8, x13, x1, x6) + +inst_403: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x28d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x789b; op2val:0x828d; + valaddr_reg:x7; val_offset:758*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 758*FLEN/8, x13, x1, x6) + +inst_404: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x28d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x278 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x828d; op2val:0x278; + valaddr_reg:x7; val_offset:760*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 760*FLEN/8, x13, x1, x6) + +inst_405: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf8c2; op2val:0x33d; + valaddr_reg:x7; val_offset:762*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 762*FLEN/8, x13, x1, x6) + +inst_406: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x28d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x208 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x828d; op2val:0x7a08; + valaddr_reg:x7; val_offset:764*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 764*FLEN/8, x13, x1, x6) + +inst_407: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x208 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x28d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a08; op2val:0x828d; + valaddr_reg:x7; val_offset:766*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 766*FLEN/8, x13, x1, x6) + +inst_408: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x28d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x828d; op2val:0x33d; + valaddr_reg:x7; val_offset:768*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 768*FLEN/8, x13, x1, x6) + +inst_409: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf8c2; op2val:0x82f6; + valaddr_reg:x7; val_offset:770*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 770*FLEN/8, x13, x1, x6) + +inst_410: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x28d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x184 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x828d; op2val:0xf984; + valaddr_reg:x7; val_offset:772*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 772*FLEN/8, x13, x1, x6) + +inst_411: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x184 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x28d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf984; op2val:0x828d; + valaddr_reg:x7; val_offset:774*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 774*FLEN/8, x13, x1, x6) + +inst_412: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x28d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x828d; op2val:0x82f6; + valaddr_reg:x7; val_offset:776*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 776*FLEN/8, x13, x1, x6) + +inst_413: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf8c2; op2val:0x82c9; + valaddr_reg:x7; val_offset:778*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 778*FLEN/8, x13, x1, x6) + +inst_414: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x28d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x130 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x828d; op2val:0xf930; + valaddr_reg:x7; val_offset:780*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 780*FLEN/8, x13, x1, x6) +RVTEST_SIGBASE(x1,signature_x1_3) + +inst_415: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x130 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x28d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf930; op2val:0x828d; + valaddr_reg:x7; val_offset:782*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 782*FLEN/8, x13, x1, x6) + +inst_416: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x28d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x828d; op2val:0x82c9; + valaddr_reg:x7; val_offset:784*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 784*FLEN/8, x13, x1, x6) + +inst_417: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf8c2; op2val:0x81fb; + valaddr_reg:x7; val_offset:786*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 786*FLEN/8, x13, x1, x6) + +inst_418: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x28d and fs2 == 1 and fe2 == 0x1d and fm2 == 0x361 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x828d; op2val:0xf761; + valaddr_reg:x7; val_offset:788*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 788*FLEN/8, x13, x1, x6) + +inst_419: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x361 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x28d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf761; op2val:0x828d; + valaddr_reg:x7; val_offset:790*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 790*FLEN/8, x13, x1, x6) + +inst_420: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x28d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x828d; op2val:0x81fb; + valaddr_reg:x7; val_offset:792*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 792*FLEN/8, x13, x1, x6) + +inst_421: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf8c2; op2val:0x82fe; + valaddr_reg:x7; val_offset:794*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 794*FLEN/8, x13, x1, x6) + +inst_422: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x28d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x194 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x828d; op2val:0xf994; + valaddr_reg:x7; val_offset:796*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 796*FLEN/8, x13, x1, x6) + +inst_423: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x194 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x28d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf994; op2val:0x828d; + valaddr_reg:x7; val_offset:798*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 798*FLEN/8, x13, x1, x6) + +inst_424: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x28d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x828d; op2val:0x82fe; + valaddr_reg:x7; val_offset:800*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 800*FLEN/8, x13, x1, x6) + +inst_425: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x064 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf8c2; op2val:0x8064; + valaddr_reg:x7; val_offset:802*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 802*FLEN/8, x13, x1, x6) + +inst_426: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x041 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x359 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8041; op2val:0xfb59; + valaddr_reg:x7; val_offset:804*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 804*FLEN/8, x13, x1, x6) + +inst_427: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x359 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x041 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb59; op2val:0x8041; + valaddr_reg:x7; val_offset:806*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 806*FLEN/8, x13, x1, x6) + +inst_428: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x041 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x064 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8041; op2val:0x8064; + valaddr_reg:x7; val_offset:808*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 808*FLEN/8, x13, x1, x6) + +inst_429: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x041 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf8c2; op2val:0x8041; + valaddr_reg:x7; val_offset:810*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 810*FLEN/8, x13, x1, x6) + +inst_430: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf8c2; op2val:0xf0; + valaddr_reg:x7; val_offset:812*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 812*FLEN/8, x13, x1, x6) + +inst_431: +// fs1 == 1 and fe1 == 0x10 and fm1 == 0x3cb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xc3cb; op2val:0xf0; + valaddr_reg:x7; val_offset:814*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 814*FLEN/8, x13, x1, x6) + +inst_432: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3cb and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xc3cb; + valaddr_reg:x7; val_offset:816*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 816*FLEN/8, x13, x1, x6) + +inst_433: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3cb and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf8c2; op2val:0xc3cb; + valaddr_reg:x7; val_offset:818*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 818*FLEN/8, x13, x1, x6) + +inst_434: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x2a9 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2a9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf6a9; op2val:0xf6a9; + valaddr_reg:x7; val_offset:820*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 820*FLEN/8, x13, x1, x6) + +inst_435: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x2a9 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3cf and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf6a9; op2val:0xf3cf; + valaddr_reg:x7; val_offset:822*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 822*FLEN/8, x13, x1, x6) + +inst_436: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3cf and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2a9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3cf; op2val:0xf6a9; + valaddr_reg:x7; val_offset:824*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 824*FLEN/8, x13, x1, x6) + +inst_437: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x2a9 and fs2 == 1 and fe2 == 0x19 and fm2 == 0x068 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf6a9; op2val:0xe468; + valaddr_reg:x7; val_offset:826*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 826*FLEN/8, x13, x1, x6) + +inst_438: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x154 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x182 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xe954; op2val:0xf182; + valaddr_reg:x7; val_offset:828*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 828*FLEN/8, x13, x1, x6) + +inst_439: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x182 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x154 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf182; op2val:0xe954; + valaddr_reg:x7; val_offset:830*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 830*FLEN/8, x13, x1, x6) + +inst_440: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x154 and fs2 == 1 and fe2 == 0x19 and fm2 == 0x068 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xe954; op2val:0xe468; + valaddr_reg:x7; val_offset:832*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 832*FLEN/8, x13, x1, x6) + +inst_441: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x2a9 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x154 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf6a9; op2val:0xe954; + valaddr_reg:x7; val_offset:834*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 834*FLEN/8, x13, x1, x6) + +inst_442: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x2a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1ae and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf6a9; op2val:0x1ae; + valaddr_reg:x7; val_offset:836*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 836*FLEN/8, x13, x1, x6) + +inst_443: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1c9 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x244 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x81c9; op2val:0x7644; + valaddr_reg:x7; val_offset:838*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 838*FLEN/8, x13, x1, x6) + +inst_444: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x244 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1c9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7644; op2val:0x81c9; + valaddr_reg:x7; val_offset:840*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 840*FLEN/8, x13, x1, x6) + +inst_445: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1c9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1ae and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x81c9; op2val:0x1ae; + valaddr_reg:x7; val_offset:842*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 842*FLEN/8, x13, x1, x6) + +inst_446: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x2a9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1c9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf6a9; op2val:0x81c9; + valaddr_reg:x7; val_offset:844*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 844*FLEN/8, x13, x1, x6) + +inst_447: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x2a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x322 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf6a9; op2val:0x322; + valaddr_reg:x7; val_offset:846*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 846*FLEN/8, x13, x1, x6) + +inst_448: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1c9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1d5 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x81c9; op2val:0x79d5; + valaddr_reg:x7; val_offset:848*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 848*FLEN/8, x13, x1, x6) + +inst_449: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1c9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x79d5; op2val:0x81c9; + valaddr_reg:x7; val_offset:850*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 850*FLEN/8, x13, x1, x6) + +inst_450: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1c9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x322 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x81c9; op2val:0x322; + valaddr_reg:x7; val_offset:852*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 852*FLEN/8, x13, x1, x6) + +inst_451: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x2a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf6a9; op2val:0x3a1; + valaddr_reg:x7; val_offset:854*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 854*FLEN/8, x13, x1, x6) + +inst_452: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1c9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c2 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x81c9; op2val:0x7ac2; + valaddr_reg:x7; val_offset:856*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 856*FLEN/8, x13, x1, x6) + +inst_453: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1c9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ac2; op2val:0x81c9; + valaddr_reg:x7; val_offset:858*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 858*FLEN/8, x13, x1, x6) + +inst_454: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1c9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x81c9; op2val:0x3a1; + valaddr_reg:x7; val_offset:860*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 860*FLEN/8, x13, x1, x6) + +inst_455: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x2a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x278 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf6a9; op2val:0x278; + valaddr_reg:x7; val_offset:862*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 862*FLEN/8, x13, x1, x6) + +inst_456: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1c9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x09b and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x81c9; op2val:0x789b; + valaddr_reg:x7; val_offset:864*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 864*FLEN/8, x13, x1, x6) + +inst_457: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1c9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x789b; op2val:0x81c9; + valaddr_reg:x7; val_offset:866*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 866*FLEN/8, x13, x1, x6) + +inst_458: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1c9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x278 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x81c9; op2val:0x278; + valaddr_reg:x7; val_offset:868*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 868*FLEN/8, x13, x1, x6) + +inst_459: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x2a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf6a9; op2val:0x33d; + valaddr_reg:x7; val_offset:870*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 870*FLEN/8, x13, x1, x6) + +inst_460: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1c9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x208 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x81c9; op2val:0x7a08; + valaddr_reg:x7; val_offset:872*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 872*FLEN/8, x13, x1, x6) + +inst_461: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x208 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1c9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a08; op2val:0x81c9; + valaddr_reg:x7; val_offset:874*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 874*FLEN/8, x13, x1, x6) + +inst_462: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1c9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x81c9; op2val:0x33d; + valaddr_reg:x7; val_offset:876*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 876*FLEN/8, x13, x1, x6) + +inst_463: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x2a9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf6a9; op2val:0x82f6; + valaddr_reg:x7; val_offset:878*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 878*FLEN/8, x13, x1, x6) + +inst_464: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1c9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x184 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x81c9; op2val:0xf984; + valaddr_reg:x7; val_offset:880*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 880*FLEN/8, x13, x1, x6) + +inst_465: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x184 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1c9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf984; op2val:0x81c9; + valaddr_reg:x7; val_offset:882*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 882*FLEN/8, x13, x1, x6) + +inst_466: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x81c9; op2val:0x82f6; + valaddr_reg:x7; val_offset:884*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 884*FLEN/8, x13, x1, x6) + +inst_467: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x2a9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf6a9; op2val:0x82c9; + valaddr_reg:x7; val_offset:886*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 886*FLEN/8, x13, x1, x6) + +inst_468: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1c9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x130 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x81c9; op2val:0xf930; + valaddr_reg:x7; val_offset:888*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 888*FLEN/8, x13, x1, x6) + +inst_469: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x130 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1c9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf930; op2val:0x81c9; + valaddr_reg:x7; val_offset:890*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 890*FLEN/8, x13, x1, x6) + +inst_470: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x81c9; op2val:0x82c9; + valaddr_reg:x7; val_offset:892*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 892*FLEN/8, x13, x1, x6) + +inst_471: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x2a9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf6a9; op2val:0x81fb; + valaddr_reg:x7; val_offset:894*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 894*FLEN/8, x13, x1, x6) + +inst_472: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1c9 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x361 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x81c9; op2val:0xf761; + valaddr_reg:x7; val_offset:896*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 896*FLEN/8, x13, x1, x6) + +inst_473: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x361 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1c9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf761; op2val:0x81c9; + valaddr_reg:x7; val_offset:898*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 898*FLEN/8, x13, x1, x6) + +inst_474: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x81c9; op2val:0x81fb; + valaddr_reg:x7; val_offset:900*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 900*FLEN/8, x13, x1, x6) + +inst_475: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x2a9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf6a9; op2val:0x82fe; + valaddr_reg:x7; val_offset:902*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 902*FLEN/8, x13, x1, x6) + +inst_476: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1c9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x194 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x81c9; op2val:0xf994; + valaddr_reg:x7; val_offset:904*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 904*FLEN/8, x13, x1, x6) + +inst_477: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x194 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1c9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf994; op2val:0x81c9; + valaddr_reg:x7; val_offset:906*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 906*FLEN/8, x13, x1, x6) + +inst_478: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x81c9; op2val:0x82fe; + valaddr_reg:x7; val_offset:908*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 908*FLEN/8, x13, x1, x6) + +inst_479: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x2a9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x064 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf6a9; op2val:0x8064; + valaddr_reg:x7; val_offset:910*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 910*FLEN/8, x13, x1, x6) + +inst_480: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x02d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x359 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x802d; op2val:0xfb59; + valaddr_reg:x7; val_offset:912*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 912*FLEN/8, x13, x1, x6) + +inst_481: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x359 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x02d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb59; op2val:0x802d; + valaddr_reg:x7; val_offset:914*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 914*FLEN/8, x13, x1, x6) + +inst_482: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x02d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x064 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x802d; op2val:0x8064; + valaddr_reg:x7; val_offset:916*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 916*FLEN/8, x13, x1, x6) + +inst_483: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x2a9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x02d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf6a9; op2val:0x802d; + valaddr_reg:x7; val_offset:918*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 918*FLEN/8, x13, x1, x6) + +inst_484: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x2a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf6a9; op2val:0xf0; + valaddr_reg:x7; val_offset:920*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 920*FLEN/8, x13, x1, x6) + +inst_485: +// fs1 == 1 and fe1 == 0x10 and fm1 == 0x175 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xc175; op2val:0xf0; + valaddr_reg:x7; val_offset:922*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 922*FLEN/8, x13, x1, x6) + +inst_486: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x175 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xc175; + valaddr_reg:x7; val_offset:924*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 924*FLEN/8, x13, x1, x6) + +inst_487: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x2a9 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x175 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf6a9; op2val:0xc175; + valaddr_reg:x7; val_offset:926*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 926*FLEN/8, x13, x1, x6) + +inst_488: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3cf and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3cf and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3cf; op2val:0xf3cf; + valaddr_reg:x7; val_offset:928*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 928*FLEN/8, x13, x1, x6) + +inst_489: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3cf and fs2 == 1 and fe2 == 0x19 and fm2 == 0x068 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3cf; op2val:0xe468; + valaddr_reg:x7; val_offset:930*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 930*FLEN/8, x13, x1, x6) + +inst_490: +// fs1 == 1 and fe1 == 0x19 and fm1 == 0x23f and fs2 == 1 and fe2 == 0x1c and fm2 == 0x182 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xe63f; op2val:0xf182; + valaddr_reg:x7; val_offset:932*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 932*FLEN/8, x13, x1, x6) + +inst_491: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x182 and fs2 == 1 and fe2 == 0x19 and fm2 == 0x23f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf182; op2val:0xe63f; + valaddr_reg:x7; val_offset:934*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 934*FLEN/8, x13, x1, x6) + +inst_492: +// fs1 == 1 and fe1 == 0x19 and fm1 == 0x23f and fs2 == 1 and fe2 == 0x19 and fm2 == 0x068 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xe63f; op2val:0xe468; + valaddr_reg:x7; val_offset:936*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 936*FLEN/8, x13, x1, x6) + +inst_493: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3cf and fs2 == 1 and fe2 == 0x19 and fm2 == 0x23f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3cf; op2val:0xe63f; + valaddr_reg:x7; val_offset:938*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 938*FLEN/8, x13, x1, x6) + +inst_494: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3cf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1ae and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3cf; op2val:0x1ae; + valaddr_reg:x7; val_offset:940*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 940*FLEN/8, x13, x1, x6) + +inst_495: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x10c and fs2 == 0 and fe2 == 0x1d and fm2 == 0x244 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x810c; op2val:0x7644; + valaddr_reg:x7; val_offset:942*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 942*FLEN/8, x13, x1, x6) + +inst_496: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x244 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x10c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7644; op2val:0x810c; + valaddr_reg:x7; val_offset:944*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 944*FLEN/8, x13, x1, x6) + +inst_497: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x10c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1ae and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x810c; op2val:0x1ae; + valaddr_reg:x7; val_offset:946*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 946*FLEN/8, x13, x1, x6) + +inst_498: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3cf and fs2 == 1 and fe2 == 0x00 and fm2 == 0x10c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3cf; op2val:0x810c; + valaddr_reg:x7; val_offset:948*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 948*FLEN/8, x13, x1, x6) + +inst_499: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3cf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x322 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3cf; op2val:0x322; + valaddr_reg:x7; val_offset:950*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 950*FLEN/8, x13, x1, x6) + +inst_500: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x10c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1d5 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x810c; op2val:0x79d5; + valaddr_reg:x7; val_offset:952*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 952*FLEN/8, x13, x1, x6) + +inst_501: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x10c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x79d5; op2val:0x810c; + valaddr_reg:x7; val_offset:954*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 954*FLEN/8, x13, x1, x6) + +inst_502: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x10c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x322 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x810c; op2val:0x322; + valaddr_reg:x7; val_offset:956*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 956*FLEN/8, x13, x1, x6) + +inst_503: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3cf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3cf; op2val:0x3a1; + valaddr_reg:x7; val_offset:958*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 958*FLEN/8, x13, x1, x6) + +inst_504: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x10c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c2 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x810c; op2val:0x7ac2; + valaddr_reg:x7; val_offset:960*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 960*FLEN/8, x13, x1, x6) + +inst_505: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x10c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ac2; op2val:0x810c; + valaddr_reg:x7; val_offset:962*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 962*FLEN/8, x13, x1, x6) + +inst_506: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x10c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x810c; op2val:0x3a1; + valaddr_reg:x7; val_offset:964*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 964*FLEN/8, x13, x1, x6) + +inst_507: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3cf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x278 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3cf; op2val:0x278; + valaddr_reg:x7; val_offset:966*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 966*FLEN/8, x13, x1, x6) + +inst_508: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x10c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x09b and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x810c; op2val:0x789b; + valaddr_reg:x7; val_offset:968*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 968*FLEN/8, x13, x1, x6) + +inst_509: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x10c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x789b; op2val:0x810c; + valaddr_reg:x7; val_offset:970*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 970*FLEN/8, x13, x1, x6) + +inst_510: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x10c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x278 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x810c; op2val:0x278; + valaddr_reg:x7; val_offset:972*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 972*FLEN/8, x13, x1, x6) + +inst_511: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3cf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3cf; op2val:0x33d; + valaddr_reg:x7; val_offset:974*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 974*FLEN/8, x13, x1, x6) + +inst_512: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x10c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x208 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x810c; op2val:0x7a08; + valaddr_reg:x7; val_offset:976*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 976*FLEN/8, x13, x1, x6) + +inst_513: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x208 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x10c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a08; op2val:0x810c; + valaddr_reg:x7; val_offset:978*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 978*FLEN/8, x13, x1, x6) + +inst_514: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x10c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x810c; op2val:0x33d; + valaddr_reg:x7; val_offset:980*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 980*FLEN/8, x13, x1, x6) + +inst_515: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3cf and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3cf; op2val:0x82f6; + valaddr_reg:x7; val_offset:982*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 982*FLEN/8, x13, x1, x6) + +inst_516: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x10c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x184 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x810c; op2val:0xf984; + valaddr_reg:x7; val_offset:984*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 984*FLEN/8, x13, x1, x6) + +inst_517: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x184 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x10c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf984; op2val:0x810c; + valaddr_reg:x7; val_offset:986*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 986*FLEN/8, x13, x1, x6) + +inst_518: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x10c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x810c; op2val:0x82f6; + valaddr_reg:x7; val_offset:988*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 988*FLEN/8, x13, x1, x6) + +inst_519: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3cf and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3cf; op2val:0x82c9; + valaddr_reg:x7; val_offset:990*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 990*FLEN/8, x13, x1, x6) + +inst_520: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x10c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x130 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x810c; op2val:0xf930; + valaddr_reg:x7; val_offset:992*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 992*FLEN/8, x13, x1, x6) + +inst_521: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x130 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x10c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf930; op2val:0x810c; + valaddr_reg:x7; val_offset:994*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 994*FLEN/8, x13, x1, x6) + +inst_522: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x10c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x810c; op2val:0x82c9; + valaddr_reg:x7; val_offset:996*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 996*FLEN/8, x13, x1, x6) + +inst_523: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3cf and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3cf; op2val:0x81fb; + valaddr_reg:x7; val_offset:998*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 998*FLEN/8, x13, x1, x6) + +inst_524: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x10c and fs2 == 1 and fe2 == 0x1d and fm2 == 0x361 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x810c; op2val:0xf761; + valaddr_reg:x7; val_offset:1000*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1000*FLEN/8, x13, x1, x6) + +inst_525: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x361 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x10c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf761; op2val:0x810c; + valaddr_reg:x7; val_offset:1002*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1002*FLEN/8, x13, x1, x6) + +inst_526: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x10c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x810c; op2val:0x81fb; + valaddr_reg:x7; val_offset:1004*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1004*FLEN/8, x13, x1, x6) + +inst_527: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3cf and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3cf; op2val:0x82fe; + valaddr_reg:x7; val_offset:1006*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1006*FLEN/8, x13, x1, x6) + +inst_528: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x10c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x194 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x810c; op2val:0xf994; + valaddr_reg:x7; val_offset:1008*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1008*FLEN/8, x13, x1, x6) + +inst_529: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x194 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x10c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf994; op2val:0x810c; + valaddr_reg:x7; val_offset:1010*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1010*FLEN/8, x13, x1, x6) + +inst_530: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x10c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x810c; op2val:0x82fe; + valaddr_reg:x7; val_offset:1012*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1012*FLEN/8, x13, x1, x6) + +inst_531: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3cf and fs2 == 1 and fe2 == 0x00 and fm2 == 0x064 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3cf; op2val:0x8064; + valaddr_reg:x7; val_offset:1014*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1014*FLEN/8, x13, x1, x6) + +inst_532: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3cf and fs2 == 1 and fe2 == 0x00 and fm2 == 0x01a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3cf; op2val:0x801a; + valaddr_reg:x7; val_offset:1016*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1016*FLEN/8, x13, x1, x6) + +inst_533: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3cf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3cf; op2val:0xf0; + valaddr_reg:x7; val_offset:1018*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1018*FLEN/8, x13, x1, x6) + +inst_534: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x266 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xbe66; op2val:0xf0; + valaddr_reg:x7; val_offset:1020*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1020*FLEN/8, x13, x1, x6) + +inst_535: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x266 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xbe66; + valaddr_reg:x7; val_offset:1022*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1022*FLEN/8, x13, x1, x6) + +inst_536: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3cf and fs2 == 1 and fe2 == 0x0f and fm2 == 0x266 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3cf; op2val:0xbe66; + valaddr_reg:x7; val_offset:1024*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1024*FLEN/8, x13, x1, x6) + +inst_537: +// fs1 == 1 and fe1 == 0x19 and fm1 == 0x068 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xe468; op2val:0x7ac0; + valaddr_reg:x7; val_offset:1026*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1026*FLEN/8, x13, x1, x6) + +inst_538: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x182 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf182; op2val:0x7ac0; + valaddr_reg:x7; val_offset:1028*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1028*FLEN/8, x13, x1, x6) + +inst_539: +// fs1 == 1 and fe1 == 0x19 and fm1 == 0x068 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x182 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xe468; op2val:0xf182; + valaddr_reg:x7; val_offset:1030*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1030*FLEN/8, x13, x1, x6) + +inst_540: +// fs1 == 1 and fe1 == 0x19 and fm1 == 0x068 and fs2 == 1 and fe2 == 0x19 and fm2 == 0x068 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xe468; op2val:0xe468; + valaddr_reg:x7; val_offset:1032*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1032*FLEN/8, x13, x1, x6) + +inst_541: +// fs1 == 1 and fe1 == 0x19 and fm1 == 0x068 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x016 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xe468; op2val:0x7816; + valaddr_reg:x7; val_offset:1034*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1034*FLEN/8, x13, x1, x6) + +inst_542: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x182 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x016 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf182; op2val:0x7816; + valaddr_reg:x7; val_offset:1036*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1036*FLEN/8, x13, x1, x6) +RVTEST_SIGBASE(x1,signature_x1_4) + +inst_543: +// fs1 == 1 and fe1 == 0x19 and fm1 == 0x068 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x39f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xe468; op2val:0x779f; + valaddr_reg:x7; val_offset:1038*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1038*FLEN/8, x13, x1, x6) + +inst_544: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x182 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x39f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf182; op2val:0x779f; + valaddr_reg:x7; val_offset:1040*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1040*FLEN/8, x13, x1, x6) + +inst_545: +// fs1 == 1 and fe1 == 0x19 and fm1 == 0x068 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x081 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xe468; op2val:0x7481; + valaddr_reg:x7; val_offset:1042*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1042*FLEN/8, x13, x1, x6) + +inst_546: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x182 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x081 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf182; op2val:0x7481; + valaddr_reg:x7; val_offset:1044*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1044*FLEN/8, x13, x1, x6) + +inst_547: +// fs1 == 1 and fe1 == 0x19 and fm1 == 0x068 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x346 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xe468; op2val:0x7b46; + valaddr_reg:x7; val_offset:1046*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1046*FLEN/8, x13, x1, x6) + +inst_548: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x182 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x346 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf182; op2val:0x7b46; + valaddr_reg:x7; val_offset:1048*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1048*FLEN/8, x13, x1, x6) + +inst_549: +// fs1 == 1 and fe1 == 0x19 and fm1 == 0x068 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3bd and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xe468; op2val:0xf3bd; + valaddr_reg:x7; val_offset:1050*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1050*FLEN/8, x13, x1, x6) + +inst_550: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x182 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3bd and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf182; op2val:0xf3bd; + valaddr_reg:x7; val_offset:1052*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1052*FLEN/8, x13, x1, x6) + +inst_551: +// fs1 == 1 and fe1 == 0x19 and fm1 == 0x068 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0c2 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xe468; op2val:0xf8c2; + valaddr_reg:x7; val_offset:1054*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1054*FLEN/8, x13, x1, x6) + +inst_552: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x182 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0c2 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf182; op2val:0xf8c2; + valaddr_reg:x7; val_offset:1056*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1056*FLEN/8, x13, x1, x6) + +inst_553: +// fs1 == 1 and fe1 == 0x19 and fm1 == 0x068 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2a9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xe468; op2val:0xf6a9; + valaddr_reg:x7; val_offset:1058*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1058*FLEN/8, x13, x1, x6) + +inst_554: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x182 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2a9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf182; op2val:0xf6a9; + valaddr_reg:x7; val_offset:1060*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1060*FLEN/8, x13, x1, x6) + +inst_555: +// fs1 == 1 and fe1 == 0x19 and fm1 == 0x068 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3cf and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xe468; op2val:0xf3cf; + valaddr_reg:x7; val_offset:1062*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1062*FLEN/8, x13, x1, x6) + +inst_556: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x182 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3cf and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf182; op2val:0xf3cf; + valaddr_reg:x7; val_offset:1064*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1064*FLEN/8, x13, x1, x6) + +inst_557: +// fs1 == 1 and fe1 == 0x19 and fm1 == 0x068 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1ae and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xe468; op2val:0x1ae; + valaddr_reg:x7; val_offset:1066*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1066*FLEN/8, x13, x1, x6) + +inst_558: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0bd and fs2 == 0 and fe2 == 0x1a and fm2 == 0x103 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x80bd; op2val:0x6903; + valaddr_reg:x7; val_offset:1068*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1068*FLEN/8, x13, x1, x6) + +inst_559: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x103 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0bd and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x6903; op2val:0x80bd; + valaddr_reg:x7; val_offset:1070*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1070*FLEN/8, x13, x1, x6) + +inst_560: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0bd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1ae and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x80bd; op2val:0x1ae; + valaddr_reg:x7; val_offset:1072*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1072*FLEN/8, x13, x1, x6) + +inst_561: +// fs1 == 1 and fe1 == 0x19 and fm1 == 0x068 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0bd and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xe468; op2val:0x80bd; + valaddr_reg:x7; val_offset:1074*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1074*FLEN/8, x13, x1, x6) + +inst_562: +// fs1 == 1 and fe1 == 0x19 and fm1 == 0x068 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x322 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xe468; op2val:0x322; + valaddr_reg:x7; val_offset:1076*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1076*FLEN/8, x13, x1, x6) + +inst_563: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0bd and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0ab and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x80bd; op2val:0x6cab; + valaddr_reg:x7; val_offset:1078*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1078*FLEN/8, x13, x1, x6) + +inst_564: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0ab and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0bd and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x6cab; op2val:0x80bd; + valaddr_reg:x7; val_offset:1080*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1080*FLEN/8, x13, x1, x6) + +inst_565: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0bd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x322 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x80bd; op2val:0x322; + valaddr_reg:x7; val_offset:1082*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1082*FLEN/8, x13, x1, x6) + +inst_566: +// fs1 == 1 and fe1 == 0x19 and fm1 == 0x068 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xe468; op2val:0x3a1; + valaddr_reg:x7; val_offset:1084*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1084*FLEN/8, x13, x1, x6) + +inst_567: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0bd and fs2 == 0 and fe2 == 0x1b and fm2 == 0x168 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x80bd; op2val:0x6d68; + valaddr_reg:x7; val_offset:1086*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1086*FLEN/8, x13, x1, x6) + +inst_568: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x168 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0bd and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d68; op2val:0x80bd; + valaddr_reg:x7; val_offset:1088*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1088*FLEN/8, x13, x1, x6) + +inst_569: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0bd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x80bd; op2val:0x3a1; + valaddr_reg:x7; val_offset:1090*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1090*FLEN/8, x13, x1, x6) + +inst_570: +// fs1 == 1 and fe1 == 0x19 and fm1 == 0x068 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x278 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xe468; op2val:0x278; + valaddr_reg:x7; val_offset:1092*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1092*FLEN/8, x13, x1, x6) + +inst_571: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0bd and fs2 == 0 and fe2 == 0x1a and fm2 == 0x35e and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x80bd; op2val:0x6b5e; + valaddr_reg:x7; val_offset:1094*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1094*FLEN/8, x13, x1, x6) + +inst_572: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x35e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0bd and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x6b5e; op2val:0x80bd; + valaddr_reg:x7; val_offset:1096*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1096*FLEN/8, x13, x1, x6) + +inst_573: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0bd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x278 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x80bd; op2val:0x278; + valaddr_reg:x7; val_offset:1098*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1098*FLEN/8, x13, x1, x6) + +inst_574: +// fs1 == 1 and fe1 == 0x19 and fm1 == 0x068 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xe468; op2val:0x33d; + valaddr_reg:x7; val_offset:1100*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1100*FLEN/8, x13, x1, x6) + +inst_575: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0bd and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0d3 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x80bd; op2val:0x6cd3; + valaddr_reg:x7; val_offset:1102*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1102*FLEN/8, x13, x1, x6) + +inst_576: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0d3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0bd and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x6cd3; op2val:0x80bd; + valaddr_reg:x7; val_offset:1104*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1104*FLEN/8, x13, x1, x6) + +inst_577: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0bd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x80bd; op2val:0x33d; + valaddr_reg:x7; val_offset:1106*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1106*FLEN/8, x13, x1, x6) + +inst_578: +// fs1 == 1 and fe1 == 0x19 and fm1 == 0x068 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xe468; op2val:0x82f6; + valaddr_reg:x7; val_offset:1108*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1108*FLEN/8, x13, x1, x6) + +inst_579: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0bd and fs2 == 1 and fe2 == 0x1b and fm2 == 0x06a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x80bd; op2val:0xec6a; + valaddr_reg:x7; val_offset:1110*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1110*FLEN/8, x13, x1, x6) + +inst_580: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x06a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0bd and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xec6a; op2val:0x80bd; + valaddr_reg:x7; val_offset:1112*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1112*FLEN/8, x13, x1, x6) + +inst_581: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x80bd; op2val:0x82f6; + valaddr_reg:x7; val_offset:1114*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1114*FLEN/8, x13, x1, x6) + +inst_582: +// fs1 == 1 and fe1 == 0x19 and fm1 == 0x068 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xe468; op2val:0x82c9; + valaddr_reg:x7; val_offset:1116*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1116*FLEN/8, x13, x1, x6) + +inst_583: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0bd and fs2 == 1 and fe2 == 0x1b and fm2 == 0x026 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x80bd; op2val:0xec26; + valaddr_reg:x7; val_offset:1118*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1118*FLEN/8, x13, x1, x6) + +inst_584: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x026 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0bd and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xec26; op2val:0x80bd; + valaddr_reg:x7; val_offset:1120*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1120*FLEN/8, x13, x1, x6) + +inst_585: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x80bd; op2val:0x82c9; + valaddr_reg:x7; val_offset:1122*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1122*FLEN/8, x13, x1, x6) + +inst_586: +// fs1 == 1 and fe1 == 0x19 and fm1 == 0x068 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xe468; op2val:0x81fb; + valaddr_reg:x7; val_offset:1124*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1124*FLEN/8, x13, x1, x6) + +inst_587: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0bd and fs2 == 1 and fe2 == 0x1a and fm2 == 0x1e7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x80bd; op2val:0xe9e7; + valaddr_reg:x7; val_offset:1126*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1126*FLEN/8, x13, x1, x6) + +inst_588: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x1e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0bd and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xe9e7; op2val:0x80bd; + valaddr_reg:x7; val_offset:1128*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1128*FLEN/8, x13, x1, x6) + +inst_589: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x80bd; op2val:0x81fb; + valaddr_reg:x7; val_offset:1130*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1130*FLEN/8, x13, x1, x6) + +inst_590: +// fs1 == 1 and fe1 == 0x19 and fm1 == 0x068 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xe468; op2val:0x82fe; + valaddr_reg:x7; val_offset:1132*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1132*FLEN/8, x13, x1, x6) + +inst_591: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0bd and fs2 == 1 and fe2 == 0x1b and fm2 == 0x076 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x80bd; op2val:0xec76; + valaddr_reg:x7; val_offset:1134*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1134*FLEN/8, x13, x1, x6) + +inst_592: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x076 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0bd and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xec76; op2val:0x80bd; + valaddr_reg:x7; val_offset:1136*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1136*FLEN/8, x13, x1, x6) + +inst_593: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x80bd; op2val:0x82fe; + valaddr_reg:x7; val_offset:1138*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1138*FLEN/8, x13, x1, x6) + +inst_594: +// fs1 == 1 and fe1 == 0x19 and fm1 == 0x068 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x064 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xe468; op2val:0x8064; + valaddr_reg:x7; val_offset:1140*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1140*FLEN/8, x13, x1, x6) + +inst_595: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x012 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x1e0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8012; op2val:0xede0; + valaddr_reg:x7; val_offset:1142*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1142*FLEN/8, x13, x1, x6) + +inst_596: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x1e0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x012 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xede0; op2val:0x8012; + valaddr_reg:x7; val_offset:1144*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1144*FLEN/8, x13, x1, x6) + +inst_597: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x012 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x064 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8012; op2val:0x8064; + valaddr_reg:x7; val_offset:1146*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1146*FLEN/8, x13, x1, x6) + +inst_598: +// fs1 == 1 and fe1 == 0x19 and fm1 == 0x068 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x012 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xe468; op2val:0x8012; + valaddr_reg:x7; val_offset:1148*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1148*FLEN/8, x13, x1, x6) + +inst_599: +// fs1 == 1 and fe1 == 0x19 and fm1 == 0x068 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xe468; op2val:0xf0; + valaddr_reg:x7; val_offset:1150*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1150*FLEN/8, x13, x1, x6) + +inst_600: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x083 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc83; op2val:0xf0; + valaddr_reg:x7; val_offset:1152*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1152*FLEN/8, x13, x1, x6) + +inst_601: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x083 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xbc83; + valaddr_reg:x7; val_offset:1154*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1154*FLEN/8, x13, x1, x6) + +inst_602: +// fs1 == 1 and fe1 == 0x19 and fm1 == 0x068 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x083 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xe468; op2val:0xbc83; + valaddr_reg:x7; val_offset:1156*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1156*FLEN/8, x13, x1, x6) + +inst_603: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1ae and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x1ae; op2val:0x7ac0; + valaddr_reg:x7; val_offset:1158*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1158*FLEN/8, x13, x1, x6) + +inst_604: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x244 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7644; op2val:0x7ac0; + valaddr_reg:x7; val_offset:1160*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1160*FLEN/8, x13, x1, x6) + +inst_605: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1ae and fs2 == 0 and fe2 == 0x1d and fm2 == 0x244 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x1ae; op2val:0x7644; + valaddr_reg:x7; val_offset:1162*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1162*FLEN/8, x13, x1, x6) + +inst_606: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1ae and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1ae and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x1ae; op2val:0x1ae; + valaddr_reg:x7; val_offset:1164*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1164*FLEN/8, x13, x1, x6) + +inst_607: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1ae and fs2 == 0 and fe2 == 0x1e and fm2 == 0x016 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x1ae; op2val:0x7816; + valaddr_reg:x7; val_offset:1166*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1166*FLEN/8, x13, x1, x6) + +inst_608: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x244 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x016 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7644; op2val:0x7816; + valaddr_reg:x7; val_offset:1168*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1168*FLEN/8, x13, x1, x6) + +inst_609: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1ae and fs2 == 0 and fe2 == 0x1d and fm2 == 0x39f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x1ae; op2val:0x779f; + valaddr_reg:x7; val_offset:1170*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1170*FLEN/8, x13, x1, x6) + +inst_610: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x244 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x39f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7644; op2val:0x779f; + valaddr_reg:x7; val_offset:1172*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1172*FLEN/8, x13, x1, x6) + +inst_611: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1ae and fs2 == 0 and fe2 == 0x1d and fm2 == 0x081 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x1ae; op2val:0x7481; + valaddr_reg:x7; val_offset:1174*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1174*FLEN/8, x13, x1, x6) + +inst_612: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x244 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x081 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7644; op2val:0x7481; + valaddr_reg:x7; val_offset:1176*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1176*FLEN/8, x13, x1, x6) + +inst_613: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1ae and fs2 == 0 and fe2 == 0x1e and fm2 == 0x346 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x1ae; op2val:0x7b46; + valaddr_reg:x7; val_offset:1178*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1178*FLEN/8, x13, x1, x6) + +inst_614: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x244 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x346 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7644; op2val:0x7b46; + valaddr_reg:x7; val_offset:1180*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1180*FLEN/8, x13, x1, x6) + +inst_615: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1ae and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3bd and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x1ae; op2val:0xf3bd; + valaddr_reg:x7; val_offset:1182*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1182*FLEN/8, x13, x1, x6) + +inst_616: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x244 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3bd and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7644; op2val:0xf3bd; + valaddr_reg:x7; val_offset:1184*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1184*FLEN/8, x13, x1, x6) + +inst_617: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1ae and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0c2 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x1ae; op2val:0xf8c2; + valaddr_reg:x7; val_offset:1186*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1186*FLEN/8, x13, x1, x6) + +inst_618: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x244 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0c2 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7644; op2val:0xf8c2; + valaddr_reg:x7; val_offset:1188*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1188*FLEN/8, x13, x1, x6) + +inst_619: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1ae and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2a9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x1ae; op2val:0xf6a9; + valaddr_reg:x7; val_offset:1190*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1190*FLEN/8, x13, x1, x6) + +inst_620: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x244 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2a9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7644; op2val:0xf6a9; + valaddr_reg:x7; val_offset:1192*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1192*FLEN/8, x13, x1, x6) + +inst_621: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1ae and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3cf and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x1ae; op2val:0xf3cf; + valaddr_reg:x7; val_offset:1194*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1194*FLEN/8, x13, x1, x6) + +inst_622: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x244 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3cf and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7644; op2val:0xf3cf; + valaddr_reg:x7; val_offset:1196*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1196*FLEN/8, x13, x1, x6) + +inst_623: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1ae and fs2 == 1 and fe2 == 0x19 and fm2 == 0x068 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x1ae; op2val:0xe468; + valaddr_reg:x7; val_offset:1198*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1198*FLEN/8, x13, x1, x6) + +inst_624: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x103 and fs2 == 1 and fe2 == 0x19 and fm2 == 0x068 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x6903; op2val:0xe468; + valaddr_reg:x7; val_offset:1200*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1200*FLEN/8, x13, x1, x6) + +inst_625: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1ae and fs2 == 0 and fe2 == 0x1a and fm2 == 0x103 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x1ae; op2val:0x6903; + valaddr_reg:x7; val_offset:1202*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1202*FLEN/8, x13, x1, x6) + +inst_626: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1ae and fs2 == 0 and fe2 == 0x00 and fm2 == 0x322 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x1ae; op2val:0x322; + valaddr_reg:x7; val_offset:1204*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1204*FLEN/8, x13, x1, x6) + +inst_627: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x322 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1ae and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x322; op2val:0x1ae; + valaddr_reg:x7; val_offset:1206*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1206*FLEN/8, x13, x1, x6) + +inst_628: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1ae and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x1ae; op2val:0x3a1; + valaddr_reg:x7; val_offset:1208*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1208*FLEN/8, x13, x1, x6) + +inst_629: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1ae and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a1; op2val:0x1ae; + valaddr_reg:x7; val_offset:1210*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1210*FLEN/8, x13, x1, x6) + +inst_630: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1ae and fs2 == 0 and fe2 == 0x00 and fm2 == 0x278 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x1ae; op2val:0x278; + valaddr_reg:x7; val_offset:1212*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1212*FLEN/8, x13, x1, x6) + +inst_631: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x278 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1ae and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x278; op2val:0x1ae; + valaddr_reg:x7; val_offset:1214*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1214*FLEN/8, x13, x1, x6) + +inst_632: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1ae and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x1ae; op2val:0x33d; + valaddr_reg:x7; val_offset:1216*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1216*FLEN/8, x13, x1, x6) + +inst_633: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1ae and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x33d; op2val:0x1ae; + valaddr_reg:x7; val_offset:1218*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1218*FLEN/8, x13, x1, x6) + +inst_634: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1ae and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x1ae; op2val:0x82f6; + valaddr_reg:x7; val_offset:1220*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1220*FLEN/8, x13, x1, x6) + +inst_635: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1ae and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82f6; op2val:0x1ae; + valaddr_reg:x7; val_offset:1222*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1222*FLEN/8, x13, x1, x6) + +inst_636: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1ae and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x1ae; op2val:0x82c9; + valaddr_reg:x7; val_offset:1224*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1224*FLEN/8, x13, x1, x6) + +inst_637: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1ae and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82c9; op2val:0x1ae; + valaddr_reg:x7; val_offset:1226*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1226*FLEN/8, x13, x1, x6) + +inst_638: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1ae and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x1ae; op2val:0x81fb; + valaddr_reg:x7; val_offset:1228*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1228*FLEN/8, x13, x1, x6) + +inst_639: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1ae and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x81fb; op2val:0x1ae; + valaddr_reg:x7; val_offset:1230*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1230*FLEN/8, x13, x1, x6) + +inst_640: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1ae and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x1ae; op2val:0x82fe; + valaddr_reg:x7; val_offset:1232*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1232*FLEN/8, x13, x1, x6) + +inst_641: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1ae and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82fe; op2val:0x1ae; + valaddr_reg:x7; val_offset:1234*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1234*FLEN/8, x13, x1, x6) + +inst_642: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1ae and fs2 == 1 and fe2 == 0x00 and fm2 == 0x064 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x1ae; op2val:0x8064; + valaddr_reg:x7; val_offset:1236*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1236*FLEN/8, x13, x1, x6) + +inst_643: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x02b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3f1 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b; op2val:0x83f1; + valaddr_reg:x7; val_offset:1238*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1238*FLEN/8, x13, x1, x6) + +inst_644: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3f1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x02b and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x83f1; op2val:0x2b; + valaddr_reg:x7; val_offset:1240*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1240*FLEN/8, x13, x1, x6) + +inst_645: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x02b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x064 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b; op2val:0x8064; + valaddr_reg:x7; val_offset:1242*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1242*FLEN/8, x13, x1, x6) + +inst_646: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1ae and fs2 == 0 and fe2 == 0x00 and fm2 == 0x02b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x1ae; op2val:0x2b; + valaddr_reg:x7; val_offset:1244*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1244*FLEN/8, x13, x1, x6) + +inst_647: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1ae and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x1ae; op2val:0xf0; + valaddr_reg:x7; val_offset:1246*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1246*FLEN/8, x13, x1, x6) + +inst_648: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x122 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x4122; op2val:0xf0; + valaddr_reg:x7; val_offset:1248*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1248*FLEN/8, x13, x1, x6) + +inst_649: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x122 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x4122; + valaddr_reg:x7; val_offset:1250*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1250*FLEN/8, x13, x1, x6) + +inst_650: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1ae and fs2 == 0 and fe2 == 0x10 and fm2 == 0x122 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x1ae; op2val:0x4122; + valaddr_reg:x7; val_offset:1252*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1252*FLEN/8, x13, x1, x6) + +inst_651: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x322 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x322; op2val:0x7ac0; + valaddr_reg:x7; val_offset:1254*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1254*FLEN/8, x13, x1, x6) + +inst_652: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x79d5; op2val:0x7ac0; + valaddr_reg:x7; val_offset:1256*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1256*FLEN/8, x13, x1, x6) + +inst_653: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x322 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1d5 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x322; op2val:0x79d5; + valaddr_reg:x7; val_offset:1258*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1258*FLEN/8, x13, x1, x6) + +inst_654: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x322 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x322 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x322; op2val:0x322; + valaddr_reg:x7; val_offset:1260*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1260*FLEN/8, x13, x1, x6) + +inst_655: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x322 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x016 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x322; op2val:0x7816; + valaddr_reg:x7; val_offset:1262*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1262*FLEN/8, x13, x1, x6) + +inst_656: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x016 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x79d5; op2val:0x7816; + valaddr_reg:x7; val_offset:1264*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1264*FLEN/8, x13, x1, x6) + +inst_657: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x322 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x39f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x322; op2val:0x779f; + valaddr_reg:x7; val_offset:1266*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1266*FLEN/8, x13, x1, x6) + +inst_658: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x39f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x79d5; op2val:0x779f; + valaddr_reg:x7; val_offset:1268*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1268*FLEN/8, x13, x1, x6) + +inst_659: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x322 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x081 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x322; op2val:0x7481; + valaddr_reg:x7; val_offset:1270*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1270*FLEN/8, x13, x1, x6) + +inst_660: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x081 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x79d5; op2val:0x7481; + valaddr_reg:x7; val_offset:1272*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1272*FLEN/8, x13, x1, x6) + +inst_661: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x322 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x346 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x322; op2val:0x7b46; + valaddr_reg:x7; val_offset:1274*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1274*FLEN/8, x13, x1, x6) + +inst_662: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x346 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x79d5; op2val:0x7b46; + valaddr_reg:x7; val_offset:1276*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1276*FLEN/8, x13, x1, x6) + +inst_663: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x322 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3bd and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x322; op2val:0xf3bd; + valaddr_reg:x7; val_offset:1278*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1278*FLEN/8, x13, x1, x6) + +inst_664: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3bd and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x79d5; op2val:0xf3bd; + valaddr_reg:x7; val_offset:1280*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1280*FLEN/8, x13, x1, x6) + +inst_665: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x322 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0c2 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x322; op2val:0xf8c2; + valaddr_reg:x7; val_offset:1282*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1282*FLEN/8, x13, x1, x6) + +inst_666: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0c2 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x79d5; op2val:0xf8c2; + valaddr_reg:x7; val_offset:1284*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1284*FLEN/8, x13, x1, x6) + +inst_667: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x322 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2a9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x322; op2val:0xf6a9; + valaddr_reg:x7; val_offset:1286*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1286*FLEN/8, x13, x1, x6) + +inst_668: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2a9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x79d5; op2val:0xf6a9; + valaddr_reg:x7; val_offset:1288*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1288*FLEN/8, x13, x1, x6) + +inst_669: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x322 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3cf and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x322; op2val:0xf3cf; + valaddr_reg:x7; val_offset:1290*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1290*FLEN/8, x13, x1, x6) + +inst_670: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3cf and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x79d5; op2val:0xf3cf; + valaddr_reg:x7; val_offset:1292*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1292*FLEN/8, x13, x1, x6) +RVTEST_SIGBASE(x1,signature_x1_5) + +inst_671: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x322 and fs2 == 1 and fe2 == 0x19 and fm2 == 0x068 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x322; op2val:0xe468; + valaddr_reg:x7; val_offset:1294*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1294*FLEN/8, x13, x1, x6) + +inst_672: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0ab and fs2 == 1 and fe2 == 0x19 and fm2 == 0x068 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x6cab; op2val:0xe468; + valaddr_reg:x7; val_offset:1296*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1296*FLEN/8, x13, x1, x6) + +inst_673: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x322 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0ab and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x322; op2val:0x6cab; + valaddr_reg:x7; val_offset:1298*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1298*FLEN/8, x13, x1, x6) + +inst_674: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x322 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x322; op2val:0x3a1; + valaddr_reg:x7; val_offset:1300*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1300*FLEN/8, x13, x1, x6) + +inst_675: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x322 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a1; op2val:0x322; + valaddr_reg:x7; val_offset:1302*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1302*FLEN/8, x13, x1, x6) + +inst_676: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x322 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x278 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x322; op2val:0x278; + valaddr_reg:x7; val_offset:1304*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1304*FLEN/8, x13, x1, x6) + +inst_677: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x278 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x322 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x278; op2val:0x322; + valaddr_reg:x7; val_offset:1306*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1306*FLEN/8, x13, x1, x6) + +inst_678: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x322 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x322; op2val:0x33d; + valaddr_reg:x7; val_offset:1308*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1308*FLEN/8, x13, x1, x6) + +inst_679: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x322 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x33d; op2val:0x322; + valaddr_reg:x7; val_offset:1310*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1310*FLEN/8, x13, x1, x6) + +inst_680: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x322 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x322; op2val:0x82f6; + valaddr_reg:x7; val_offset:1312*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1312*FLEN/8, x13, x1, x6) + +inst_681: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x322 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82f6; op2val:0x322; + valaddr_reg:x7; val_offset:1314*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1314*FLEN/8, x13, x1, x6) + +inst_682: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x322 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x322; op2val:0x82c9; + valaddr_reg:x7; val_offset:1316*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1316*FLEN/8, x13, x1, x6) + +inst_683: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x322 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82c9; op2val:0x322; + valaddr_reg:x7; val_offset:1318*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1318*FLEN/8, x13, x1, x6) + +inst_684: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x322 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x322; op2val:0x81fb; + valaddr_reg:x7; val_offset:1320*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1320*FLEN/8, x13, x1, x6) + +inst_685: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x322 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x81fb; op2val:0x322; + valaddr_reg:x7; val_offset:1322*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1322*FLEN/8, x13, x1, x6) + +inst_686: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x322 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x322; op2val:0x82fe; + valaddr_reg:x7; val_offset:1324*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1324*FLEN/8, x13, x1, x6) + +inst_687: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x322 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82fe; op2val:0x322; + valaddr_reg:x7; val_offset:1326*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1326*FLEN/8, x13, x1, x6) + +inst_688: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x322 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x064 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x322; op2val:0x8064; + valaddr_reg:x7; val_offset:1328*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1328*FLEN/8, x13, x1, x6) + +inst_689: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x050 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3f1 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x50; op2val:0x83f1; + valaddr_reg:x7; val_offset:1330*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1330*FLEN/8, x13, x1, x6) + +inst_690: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3f1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x050 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x83f1; op2val:0x50; + valaddr_reg:x7; val_offset:1332*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1332*FLEN/8, x13, x1, x6) + +inst_691: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x050 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x064 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x50; op2val:0x8064; + valaddr_reg:x7; val_offset:1334*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1334*FLEN/8, x13, x1, x6) + +inst_692: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x322 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x050 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x322; op2val:0x50; + valaddr_reg:x7; val_offset:1336*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1336*FLEN/8, x13, x1, x6) + +inst_693: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x322 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x322; op2val:0xf0; + valaddr_reg:x7; val_offset:1338*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1338*FLEN/8, x13, x1, x6) + +inst_694: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x0c7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x44c7; op2val:0xf0; + valaddr_reg:x7; val_offset:1340*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1340*FLEN/8, x13, x1, x6) + +inst_695: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0c7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x44c7; + valaddr_reg:x7; val_offset:1342*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1342*FLEN/8, x13, x1, x6) + +inst_696: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x322 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0c7 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x322; op2val:0x44c7; + valaddr_reg:x7; val_offset:1344*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1344*FLEN/8, x13, x1, x6) + +inst_697: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a1; op2val:0x7ac0; + valaddr_reg:x7; val_offset:1346*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1346*FLEN/8, x13, x1, x6) + +inst_698: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ac2; op2val:0x7ac0; + valaddr_reg:x7; val_offset:1348*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1348*FLEN/8, x13, x1, x6) + +inst_699: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c2 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a1; op2val:0x7ac2; + valaddr_reg:x7; val_offset:1350*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1350*FLEN/8, x13, x1, x6) + +inst_700: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a1; op2val:0x3a1; + valaddr_reg:x7; val_offset:1352*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1352*FLEN/8, x13, x1, x6) + +inst_701: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x016 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a1; op2val:0x7816; + valaddr_reg:x7; val_offset:1354*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1354*FLEN/8, x13, x1, x6) + +inst_702: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x016 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ac2; op2val:0x7816; + valaddr_reg:x7; val_offset:1356*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1356*FLEN/8, x13, x1, x6) + +inst_703: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x39f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a1; op2val:0x779f; + valaddr_reg:x7; val_offset:1358*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1358*FLEN/8, x13, x1, x6) + +inst_704: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c2 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x39f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ac2; op2val:0x779f; + valaddr_reg:x7; val_offset:1360*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1360*FLEN/8, x13, x1, x6) + +inst_705: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x081 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a1; op2val:0x7481; + valaddr_reg:x7; val_offset:1362*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1362*FLEN/8, x13, x1, x6) + +inst_706: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c2 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x081 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ac2; op2val:0x7481; + valaddr_reg:x7; val_offset:1364*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1364*FLEN/8, x13, x1, x6) + +inst_707: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x346 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a1; op2val:0x7b46; + valaddr_reg:x7; val_offset:1366*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1366*FLEN/8, x13, x1, x6) + +inst_708: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x346 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ac2; op2val:0x7b46; + valaddr_reg:x7; val_offset:1368*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1368*FLEN/8, x13, x1, x6) + +inst_709: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3bd and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a1; op2val:0xf3bd; + valaddr_reg:x7; val_offset:1370*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1370*FLEN/8, x13, x1, x6) + +inst_710: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c2 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3bd and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ac2; op2val:0xf3bd; + valaddr_reg:x7; val_offset:1372*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1372*FLEN/8, x13, x1, x6) + +inst_711: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0c2 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a1; op2val:0xf8c2; + valaddr_reg:x7; val_offset:1374*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1374*FLEN/8, x13, x1, x6) + +inst_712: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c2 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0c2 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ac2; op2val:0xf8c2; + valaddr_reg:x7; val_offset:1376*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1376*FLEN/8, x13, x1, x6) + +inst_713: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2a9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a1; op2val:0xf6a9; + valaddr_reg:x7; val_offset:1378*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1378*FLEN/8, x13, x1, x6) + +inst_714: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c2 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2a9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ac2; op2val:0xf6a9; + valaddr_reg:x7; val_offset:1380*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1380*FLEN/8, x13, x1, x6) + +inst_715: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3cf and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a1; op2val:0xf3cf; + valaddr_reg:x7; val_offset:1382*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1382*FLEN/8, x13, x1, x6) + +inst_716: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c2 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3cf and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ac2; op2val:0xf3cf; + valaddr_reg:x7; val_offset:1384*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1384*FLEN/8, x13, x1, x6) + +inst_717: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1 and fs2 == 1 and fe2 == 0x19 and fm2 == 0x068 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a1; op2val:0xe468; + valaddr_reg:x7; val_offset:1386*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1386*FLEN/8, x13, x1, x6) + +inst_718: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x168 and fs2 == 1 and fe2 == 0x19 and fm2 == 0x068 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d68; op2val:0xe468; + valaddr_reg:x7; val_offset:1388*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1388*FLEN/8, x13, x1, x6) + +inst_719: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x168 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a1; op2val:0x6d68; + valaddr_reg:x7; val_offset:1390*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1390*FLEN/8, x13, x1, x6) + +inst_720: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x278 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a1; op2val:0x278; + valaddr_reg:x7; val_offset:1392*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1392*FLEN/8, x13, x1, x6) + +inst_721: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x278 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x278; op2val:0x3a1; + valaddr_reg:x7; val_offset:1394*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1394*FLEN/8, x13, x1, x6) + +inst_722: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a1; op2val:0x33d; + valaddr_reg:x7; val_offset:1396*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1396*FLEN/8, x13, x1, x6) + +inst_723: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x33d; op2val:0x3a1; + valaddr_reg:x7; val_offset:1398*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1398*FLEN/8, x13, x1, x6) + +inst_724: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a1; op2val:0x82f6; + valaddr_reg:x7; val_offset:1400*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1400*FLEN/8, x13, x1, x6) + +inst_725: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82f6; op2val:0x3a1; + valaddr_reg:x7; val_offset:1402*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1402*FLEN/8, x13, x1, x6) + +inst_726: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a1; op2val:0x82c9; + valaddr_reg:x7; val_offset:1404*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1404*FLEN/8, x13, x1, x6) + +inst_727: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82c9; op2val:0x3a1; + valaddr_reg:x7; val_offset:1406*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1406*FLEN/8, x13, x1, x6) + +inst_728: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a1; op2val:0x81fb; + valaddr_reg:x7; val_offset:1408*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1408*FLEN/8, x13, x1, x6) + +inst_729: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x81fb; op2val:0x3a1; + valaddr_reg:x7; val_offset:1410*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1410*FLEN/8, x13, x1, x6) + +inst_730: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a1; op2val:0x82fe; + valaddr_reg:x7; val_offset:1412*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1412*FLEN/8, x13, x1, x6) + +inst_731: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82fe; op2val:0x3a1; + valaddr_reg:x7; val_offset:1414*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1414*FLEN/8, x13, x1, x6) + +inst_732: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x064 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a1; op2val:0x8064; + valaddr_reg:x7; val_offset:1416*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1416*FLEN/8, x13, x1, x6) + +inst_733: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x05c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3f1 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x5c; op2val:0x83f1; + valaddr_reg:x7; val_offset:1418*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1418*FLEN/8, x13, x1, x6) + +inst_734: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3f1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x05c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x83f1; op2val:0x5c; + valaddr_reg:x7; val_offset:1420*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1420*FLEN/8, x13, x1, x6) + +inst_735: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x05c and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a1; op2val:0x5c; + valaddr_reg:x7; val_offset:1422*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1422*FLEN/8, x13, x1, x6) + +inst_736: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a1; op2val:0xf0; + valaddr_reg:x7; val_offset:1424*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1424*FLEN/8, x13, x1, x6) + +inst_737: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x189 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x4589; op2val:0xf0; + valaddr_reg:x7; val_offset:1426*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1426*FLEN/8, x13, x1, x6) + +inst_738: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x189 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x4589; + valaddr_reg:x7; val_offset:1428*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1428*FLEN/8, x13, x1, x6) + +inst_739: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x189 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a1; op2val:0x4589; + valaddr_reg:x7; val_offset:1430*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1430*FLEN/8, x13, x1, x6) + +inst_740: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x278 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x278; op2val:0x7ac0; + valaddr_reg:x7; val_offset:1432*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1432*FLEN/8, x13, x1, x6) + +inst_741: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x789b; op2val:0x7ac0; + valaddr_reg:x7; val_offset:1434*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1434*FLEN/8, x13, x1, x6) + +inst_742: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x278 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x09b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x278; op2val:0x789b; + valaddr_reg:x7; val_offset:1436*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1436*FLEN/8, x13, x1, x6) + +inst_743: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x278 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x278 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x278; op2val:0x278; + valaddr_reg:x7; val_offset:1438*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1438*FLEN/8, x13, x1, x6) + +inst_744: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x278 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x016 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x278; op2val:0x7816; + valaddr_reg:x7; val_offset:1440*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1440*FLEN/8, x13, x1, x6) + +inst_745: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x016 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x789b; op2val:0x7816; + valaddr_reg:x7; val_offset:1442*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1442*FLEN/8, x13, x1, x6) + +inst_746: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x278 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x39f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x278; op2val:0x779f; + valaddr_reg:x7; val_offset:1444*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1444*FLEN/8, x13, x1, x6) + +inst_747: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09b and fs2 == 0 and fe2 == 0x1d and fm2 == 0x39f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x789b; op2val:0x779f; + valaddr_reg:x7; val_offset:1446*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1446*FLEN/8, x13, x1, x6) + +inst_748: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x278 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x081 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x278; op2val:0x7481; + valaddr_reg:x7; val_offset:1448*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1448*FLEN/8, x13, x1, x6) + +inst_749: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09b and fs2 == 0 and fe2 == 0x1d and fm2 == 0x081 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x789b; op2val:0x7481; + valaddr_reg:x7; val_offset:1450*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1450*FLEN/8, x13, x1, x6) + +inst_750: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x278 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x346 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x278; op2val:0x7b46; + valaddr_reg:x7; val_offset:1452*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1452*FLEN/8, x13, x1, x6) + +inst_751: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x346 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x789b; op2val:0x7b46; + valaddr_reg:x7; val_offset:1454*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1454*FLEN/8, x13, x1, x6) + +inst_752: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x278 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3bd and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x278; op2val:0xf3bd; + valaddr_reg:x7; val_offset:1456*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1456*FLEN/8, x13, x1, x6) + +inst_753: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09b and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3bd and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x789b; op2val:0xf3bd; + valaddr_reg:x7; val_offset:1458*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1458*FLEN/8, x13, x1, x6) + +inst_754: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x278 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0c2 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x278; op2val:0xf8c2; + valaddr_reg:x7; val_offset:1460*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1460*FLEN/8, x13, x1, x6) + +inst_755: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09b and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0c2 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x789b; op2val:0xf8c2; + valaddr_reg:x7; val_offset:1462*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1462*FLEN/8, x13, x1, x6) + +inst_756: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x278 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2a9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x278; op2val:0xf6a9; + valaddr_reg:x7; val_offset:1464*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1464*FLEN/8, x13, x1, x6) + +inst_757: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09b and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2a9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x789b; op2val:0xf6a9; + valaddr_reg:x7; val_offset:1466*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1466*FLEN/8, x13, x1, x6) + +inst_758: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x278 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3cf and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x278; op2val:0xf3cf; + valaddr_reg:x7; val_offset:1468*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1468*FLEN/8, x13, x1, x6) + +inst_759: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09b and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3cf and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x789b; op2val:0xf3cf; + valaddr_reg:x7; val_offset:1470*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1470*FLEN/8, x13, x1, x6) + +inst_760: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x278 and fs2 == 1 and fe2 == 0x19 and fm2 == 0x068 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x278; op2val:0xe468; + valaddr_reg:x7; val_offset:1472*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1472*FLEN/8, x13, x1, x6) + +inst_761: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x35e and fs2 == 1 and fe2 == 0x19 and fm2 == 0x068 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x6b5e; op2val:0xe468; + valaddr_reg:x7; val_offset:1474*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1474*FLEN/8, x13, x1, x6) + +inst_762: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x278 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x35e and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x278; op2val:0x6b5e; + valaddr_reg:x7; val_offset:1476*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1476*FLEN/8, x13, x1, x6) + +inst_763: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x278 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x278; op2val:0x33d; + valaddr_reg:x7; val_offset:1478*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1478*FLEN/8, x13, x1, x6) + +inst_764: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x278 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x33d; op2val:0x278; + valaddr_reg:x7; val_offset:1480*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1480*FLEN/8, x13, x1, x6) + +inst_765: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x278 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x278; op2val:0x82f6; + valaddr_reg:x7; val_offset:1482*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1482*FLEN/8, x13, x1, x6) + +inst_766: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x278 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82f6; op2val:0x278; + valaddr_reg:x7; val_offset:1484*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1484*FLEN/8, x13, x1, x6) + +inst_767: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x278 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x278; op2val:0x82c9; + valaddr_reg:x7; val_offset:1486*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1486*FLEN/8, x13, x1, x6) + +inst_768: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x278 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82c9; op2val:0x278; + valaddr_reg:x7; val_offset:1488*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1488*FLEN/8, x13, x1, x6) + +inst_769: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x278 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x278; op2val:0x81fb; + valaddr_reg:x7; val_offset:1490*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1490*FLEN/8, x13, x1, x6) + +inst_770: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x278 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x81fb; op2val:0x278; + valaddr_reg:x7; val_offset:1492*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1492*FLEN/8, x13, x1, x6) + +inst_771: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x278 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x278; op2val:0x82fe; + valaddr_reg:x7; val_offset:1494*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1494*FLEN/8, x13, x1, x6) + +inst_772: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x278 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82fe; op2val:0x278; + valaddr_reg:x7; val_offset:1496*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1496*FLEN/8, x13, x1, x6) + +inst_773: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x278 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x064 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x278; op2val:0x8064; + valaddr_reg:x7; val_offset:1498*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1498*FLEN/8, x13, x1, x6) + +inst_774: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3f1 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3f; op2val:0x83f1; + valaddr_reg:x7; val_offset:1500*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1500*FLEN/8, x13, x1, x6) + +inst_775: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3f1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x83f1; op2val:0x3f; + valaddr_reg:x7; val_offset:1502*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1502*FLEN/8, x13, x1, x6) + +inst_776: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x064 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x3f; op2val:0x8064; + valaddr_reg:x7; val_offset:1504*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1504*FLEN/8, x13, x1, x6) + +inst_777: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x278 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x278; op2val:0x3f; + valaddr_reg:x7; val_offset:1506*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1506*FLEN/8, x13, x1, x6) + +inst_778: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x278 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x278; op2val:0xf0; + valaddr_reg:x7; val_offset:1508*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1508*FLEN/8, x13, x1, x6) + +inst_779: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x38b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x438b; op2val:0xf0; + valaddr_reg:x7; val_offset:1510*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1510*FLEN/8, x13, x1, x6) + +inst_780: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x38b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x438b; + valaddr_reg:x7; val_offset:1512*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1512*FLEN/8, x13, x1, x6) + +inst_781: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x278 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x38b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x278; op2val:0x438b; + valaddr_reg:x7; val_offset:1514*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1514*FLEN/8, x13, x1, x6) + +inst_782: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x33d; op2val:0x7ac0; + valaddr_reg:x7; val_offset:1516*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1516*FLEN/8, x13, x1, x6) + +inst_783: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x208 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a08; op2val:0x7ac0; + valaddr_reg:x7; val_offset:1518*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1518*FLEN/8, x13, x1, x6) + +inst_784: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x208 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x33d; op2val:0x7a08; + valaddr_reg:x7; val_offset:1520*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1520*FLEN/8, x13, x1, x6) + +inst_785: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x33d; op2val:0x33d; + valaddr_reg:x7; val_offset:1522*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1522*FLEN/8, x13, x1, x6) + +inst_786: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x016 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x33d; op2val:0x7816; + valaddr_reg:x7; val_offset:1524*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1524*FLEN/8, x13, x1, x6) + +inst_787: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x208 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x016 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a08; op2val:0x7816; + valaddr_reg:x7; val_offset:1526*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1526*FLEN/8, x13, x1, x6) + +inst_788: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33d and fs2 == 0 and fe2 == 0x1d and fm2 == 0x39f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x33d; op2val:0x779f; + valaddr_reg:x7; val_offset:1528*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1528*FLEN/8, x13, x1, x6) + +inst_789: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x208 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x39f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a08; op2val:0x779f; + valaddr_reg:x7; val_offset:1530*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1530*FLEN/8, x13, x1, x6) + +inst_790: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33d and fs2 == 0 and fe2 == 0x1d and fm2 == 0x081 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x33d; op2val:0x7481; + valaddr_reg:x7; val_offset:1532*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1532*FLEN/8, x13, x1, x6) + +inst_791: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x208 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x081 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a08; op2val:0x7481; + valaddr_reg:x7; val_offset:1534*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1534*FLEN/8, x13, x1, x6) + +inst_792: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x346 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x33d; op2val:0x7b46; + valaddr_reg:x7; val_offset:1536*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1536*FLEN/8, x13, x1, x6) + +inst_793: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x208 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x346 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a08; op2val:0x7b46; + valaddr_reg:x7; val_offset:1538*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1538*FLEN/8, x13, x1, x6) + +inst_794: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33d and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3bd and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x33d; op2val:0xf3bd; + valaddr_reg:x7; val_offset:1540*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1540*FLEN/8, x13, x1, x6) + +inst_795: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x208 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3bd and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a08; op2val:0xf3bd; + valaddr_reg:x7; val_offset:1542*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1542*FLEN/8, x13, x1, x6) + +inst_796: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0c2 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x33d; op2val:0xf8c2; + valaddr_reg:x7; val_offset:1544*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1544*FLEN/8, x13, x1, x6) + +inst_797: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x208 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0c2 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a08; op2val:0xf8c2; + valaddr_reg:x7; val_offset:1546*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1546*FLEN/8, x13, x1, x6) + +inst_798: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33d and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2a9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x33d; op2val:0xf6a9; + valaddr_reg:x7; val_offset:1548*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1548*FLEN/8, x13, x1, x6) +RVTEST_SIGBASE(x1,signature_x1_6) + +inst_799: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x208 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2a9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a08; op2val:0xf6a9; + valaddr_reg:x7; val_offset:1550*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1550*FLEN/8, x13, x1, x6) + +inst_800: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33d and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3cf and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x33d; op2val:0xf3cf; + valaddr_reg:x7; val_offset:1552*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1552*FLEN/8, x13, x1, x6) + +inst_801: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x208 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3cf and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a08; op2val:0xf3cf; + valaddr_reg:x7; val_offset:1554*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1554*FLEN/8, x13, x1, x6) + +inst_802: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33d and fs2 == 1 and fe2 == 0x19 and fm2 == 0x068 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x33d; op2val:0xe468; + valaddr_reg:x7; val_offset:1556*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1556*FLEN/8, x13, x1, x6) + +inst_803: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0d3 and fs2 == 1 and fe2 == 0x19 and fm2 == 0x068 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x6cd3; op2val:0xe468; + valaddr_reg:x7; val_offset:1558*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1558*FLEN/8, x13, x1, x6) + +inst_804: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33d and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0d3 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x33d; op2val:0x6cd3; + valaddr_reg:x7; val_offset:1560*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1560*FLEN/8, x13, x1, x6) + +inst_805: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x33d; op2val:0x82f6; + valaddr_reg:x7; val_offset:1562*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1562*FLEN/8, x13, x1, x6) + +inst_806: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82f6; op2val:0x33d; + valaddr_reg:x7; val_offset:1564*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1564*FLEN/8, x13, x1, x6) + +inst_807: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x33d; op2val:0x82c9; + valaddr_reg:x7; val_offset:1566*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1566*FLEN/8, x13, x1, x6) + +inst_808: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82c9; op2val:0x33d; + valaddr_reg:x7; val_offset:1568*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1568*FLEN/8, x13, x1, x6) + +inst_809: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x33d; op2val:0x81fb; + valaddr_reg:x7; val_offset:1570*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1570*FLEN/8, x13, x1, x6) + +inst_810: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x81fb; op2val:0x33d; + valaddr_reg:x7; val_offset:1572*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1572*FLEN/8, x13, x1, x6) + +inst_811: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x33d; op2val:0x82fe; + valaddr_reg:x7; val_offset:1574*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1574*FLEN/8, x13, x1, x6) + +inst_812: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82fe; op2val:0x33d; + valaddr_reg:x7; val_offset:1576*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1576*FLEN/8, x13, x1, x6) + +inst_813: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x064 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x33d; op2val:0x8064; + valaddr_reg:x7; val_offset:1578*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1578*FLEN/8, x13, x1, x6) + +inst_814: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x052 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3f1 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x52; op2val:0x83f1; + valaddr_reg:x7; val_offset:1580*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1580*FLEN/8, x13, x1, x6) + +inst_815: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3f1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x052 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x83f1; op2val:0x52; + valaddr_reg:x7; val_offset:1582*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1582*FLEN/8, x13, x1, x6) + +inst_816: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x052 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x064 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x52; op2val:0x8064; + valaddr_reg:x7; val_offset:1584*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1584*FLEN/8, x13, x1, x6) + +inst_817: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x052 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x33d; op2val:0x52; + valaddr_reg:x7; val_offset:1586*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1586*FLEN/8, x13, x1, x6) + +inst_818: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x33d; op2val:0xf0; + valaddr_reg:x7; val_offset:1588*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1588*FLEN/8, x13, x1, x6) + +inst_819: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x0f1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x44f1; op2val:0xf0; + valaddr_reg:x7; val_offset:1590*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1590*FLEN/8, x13, x1, x6) + +inst_820: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0f1 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x44f1; + valaddr_reg:x7; val_offset:1592*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1592*FLEN/8, x13, x1, x6) + +inst_821: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33d and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0f1 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x33d; op2val:0x44f1; + valaddr_reg:x7; val_offset:1594*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1594*FLEN/8, x13, x1, x6) + +inst_822: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82f6; op2val:0x7ac0; + valaddr_reg:x7; val_offset:1596*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1596*FLEN/8, x13, x1, x6) + +inst_823: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x184 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf984; op2val:0x7ac0; + valaddr_reg:x7; val_offset:1598*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1598*FLEN/8, x13, x1, x6) + +inst_824: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x184 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82f6; op2val:0xf984; + valaddr_reg:x7; val_offset:1600*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1600*FLEN/8, x13, x1, x6) + +inst_825: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82f6; op2val:0x82f6; + valaddr_reg:x7; val_offset:1602*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1602*FLEN/8, x13, x1, x6) + +inst_826: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x016 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82f6; op2val:0x7816; + valaddr_reg:x7; val_offset:1604*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1604*FLEN/8, x13, x1, x6) + +inst_827: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x184 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x016 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf984; op2val:0x7816; + valaddr_reg:x7; val_offset:1606*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1606*FLEN/8, x13, x1, x6) + +inst_828: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x39f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82f6; op2val:0x779f; + valaddr_reg:x7; val_offset:1608*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1608*FLEN/8, x13, x1, x6) + +inst_829: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x184 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x39f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf984; op2val:0x779f; + valaddr_reg:x7; val_offset:1610*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1610*FLEN/8, x13, x1, x6) + +inst_830: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x081 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82f6; op2val:0x7481; + valaddr_reg:x7; val_offset:1612*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1612*FLEN/8, x13, x1, x6) + +inst_831: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x184 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x081 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf984; op2val:0x7481; + valaddr_reg:x7; val_offset:1614*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1614*FLEN/8, x13, x1, x6) + +inst_832: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x346 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82f6; op2val:0x7b46; + valaddr_reg:x7; val_offset:1616*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1616*FLEN/8, x13, x1, x6) + +inst_833: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x184 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x346 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf984; op2val:0x7b46; + valaddr_reg:x7; val_offset:1618*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1618*FLEN/8, x13, x1, x6) + +inst_834: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3bd and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82f6; op2val:0xf3bd; + valaddr_reg:x7; val_offset:1620*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1620*FLEN/8, x13, x1, x6) + +inst_835: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x184 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3bd and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf984; op2val:0xf3bd; + valaddr_reg:x7; val_offset:1622*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1622*FLEN/8, x13, x1, x6) + +inst_836: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0c2 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82f6; op2val:0xf8c2; + valaddr_reg:x7; val_offset:1624*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1624*FLEN/8, x13, x1, x6) + +inst_837: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x184 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0c2 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf984; op2val:0xf8c2; + valaddr_reg:x7; val_offset:1626*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1626*FLEN/8, x13, x1, x6) + +inst_838: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2a9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82f6; op2val:0xf6a9; + valaddr_reg:x7; val_offset:1628*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1628*FLEN/8, x13, x1, x6) + +inst_839: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x184 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2a9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf984; op2val:0xf6a9; + valaddr_reg:x7; val_offset:1630*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1630*FLEN/8, x13, x1, x6) + +inst_840: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3cf and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82f6; op2val:0xf3cf; + valaddr_reg:x7; val_offset:1632*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1632*FLEN/8, x13, x1, x6) + +inst_841: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x184 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3cf and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf984; op2val:0xf3cf; + valaddr_reg:x7; val_offset:1634*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1634*FLEN/8, x13, x1, x6) + +inst_842: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6 and fs2 == 1 and fe2 == 0x19 and fm2 == 0x068 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82f6; op2val:0xe468; + valaddr_reg:x7; val_offset:1636*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1636*FLEN/8, x13, x1, x6) + +inst_843: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x06a and fs2 == 1 and fe2 == 0x19 and fm2 == 0x068 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xec6a; op2val:0xe468; + valaddr_reg:x7; val_offset:1638*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1638*FLEN/8, x13, x1, x6) + +inst_844: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x06a and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82f6; op2val:0xec6a; + valaddr_reg:x7; val_offset:1640*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1640*FLEN/8, x13, x1, x6) + +inst_845: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82f6; op2val:0x82c9; + valaddr_reg:x7; val_offset:1642*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1642*FLEN/8, x13, x1, x6) + +inst_846: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82c9; op2val:0x82f6; + valaddr_reg:x7; val_offset:1644*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1644*FLEN/8, x13, x1, x6) + +inst_847: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82f6; op2val:0x81fb; + valaddr_reg:x7; val_offset:1646*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1646*FLEN/8, x13, x1, x6) + +inst_848: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x81fb; op2val:0x82f6; + valaddr_reg:x7; val_offset:1648*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1648*FLEN/8, x13, x1, x6) + +inst_849: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82f6; op2val:0x82fe; + valaddr_reg:x7; val_offset:1650*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1650*FLEN/8, x13, x1, x6) + +inst_850: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82fe; op2val:0x82f6; + valaddr_reg:x7; val_offset:1652*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1652*FLEN/8, x13, x1, x6) + +inst_851: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x064 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82f6; op2val:0x8064; + valaddr_reg:x7; val_offset:1654*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1654*FLEN/8, x13, x1, x6) + +inst_852: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x04b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3f1 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x804b; op2val:0x83f1; + valaddr_reg:x7; val_offset:1656*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1656*FLEN/8, x13, x1, x6) + +inst_853: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3f1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x04b and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x83f1; op2val:0x804b; + valaddr_reg:x7; val_offset:1658*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1658*FLEN/8, x13, x1, x6) + +inst_854: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x04b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x064 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x804b; op2val:0x8064; + valaddr_reg:x7; val_offset:1660*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1660*FLEN/8, x13, x1, x6) + +inst_855: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x04b and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82f6; op2val:0x804b; + valaddr_reg:x7; val_offset:1662*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1662*FLEN/8, x13, x1, x6) + +inst_856: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82f6; op2val:0xf0; + valaddr_reg:x7; val_offset:1664*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1664*FLEN/8, x13, x1, x6) + +inst_857: +// fs1 == 1 and fe1 == 0x11 and fm1 == 0x085 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xc485; op2val:0xf0; + valaddr_reg:x7; val_offset:1666*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1666*FLEN/8, x13, x1, x6) + +inst_858: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x085 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xc485; + valaddr_reg:x7; val_offset:1668*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1668*FLEN/8, x13, x1, x6) + +inst_859: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x085 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82f6; op2val:0xc485; + valaddr_reg:x7; val_offset:1670*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1670*FLEN/8, x13, x1, x6) + +inst_860: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82c9; op2val:0x7ac0; + valaddr_reg:x7; val_offset:1672*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1672*FLEN/8, x13, x1, x6) + +inst_861: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x130 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf930; op2val:0x7ac0; + valaddr_reg:x7; val_offset:1674*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1674*FLEN/8, x13, x1, x6) + +inst_862: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x130 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82c9; op2val:0xf930; + valaddr_reg:x7; val_offset:1676*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1676*FLEN/8, x13, x1, x6) + +inst_863: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82c9; op2val:0x82c9; + valaddr_reg:x7; val_offset:1678*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1678*FLEN/8, x13, x1, x6) + +inst_864: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x016 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82c9; op2val:0x7816; + valaddr_reg:x7; val_offset:1680*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1680*FLEN/8, x13, x1, x6) + +inst_865: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x130 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x016 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf930; op2val:0x7816; + valaddr_reg:x7; val_offset:1682*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1682*FLEN/8, x13, x1, x6) + +inst_866: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x39f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82c9; op2val:0x779f; + valaddr_reg:x7; val_offset:1684*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1684*FLEN/8, x13, x1, x6) + +inst_867: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x130 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x39f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf930; op2val:0x779f; + valaddr_reg:x7; val_offset:1686*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1686*FLEN/8, x13, x1, x6) + +inst_868: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x081 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82c9; op2val:0x7481; + valaddr_reg:x7; val_offset:1688*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1688*FLEN/8, x13, x1, x6) + +inst_869: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x130 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x081 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf930; op2val:0x7481; + valaddr_reg:x7; val_offset:1690*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1690*FLEN/8, x13, x1, x6) + +inst_870: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x346 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82c9; op2val:0x7b46; + valaddr_reg:x7; val_offset:1692*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1692*FLEN/8, x13, x1, x6) + +inst_871: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x130 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x346 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf930; op2val:0x7b46; + valaddr_reg:x7; val_offset:1694*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1694*FLEN/8, x13, x1, x6) + +inst_872: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3bd and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82c9; op2val:0xf3bd; + valaddr_reg:x7; val_offset:1696*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1696*FLEN/8, x13, x1, x6) + +inst_873: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x130 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3bd and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf930; op2val:0xf3bd; + valaddr_reg:x7; val_offset:1698*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1698*FLEN/8, x13, x1, x6) + +inst_874: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0c2 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82c9; op2val:0xf8c2; + valaddr_reg:x7; val_offset:1700*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1700*FLEN/8, x13, x1, x6) + +inst_875: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x130 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0c2 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf930; op2val:0xf8c2; + valaddr_reg:x7; val_offset:1702*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1702*FLEN/8, x13, x1, x6) + +inst_876: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2a9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82c9; op2val:0xf6a9; + valaddr_reg:x7; val_offset:1704*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1704*FLEN/8, x13, x1, x6) + +inst_877: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x130 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2a9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf930; op2val:0xf6a9; + valaddr_reg:x7; val_offset:1706*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1706*FLEN/8, x13, x1, x6) + +inst_878: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3cf and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82c9; op2val:0xf3cf; + valaddr_reg:x7; val_offset:1708*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1708*FLEN/8, x13, x1, x6) + +inst_879: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x130 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3cf and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf930; op2val:0xf3cf; + valaddr_reg:x7; val_offset:1710*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1710*FLEN/8, x13, x1, x6) + +inst_880: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9 and fs2 == 1 and fe2 == 0x19 and fm2 == 0x068 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82c9; op2val:0xe468; + valaddr_reg:x7; val_offset:1712*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1712*FLEN/8, x13, x1, x6) + +inst_881: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x026 and fs2 == 1 and fe2 == 0x19 and fm2 == 0x068 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xec26; op2val:0xe468; + valaddr_reg:x7; val_offset:1714*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1714*FLEN/8, x13, x1, x6) + +inst_882: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x026 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82c9; op2val:0xec26; + valaddr_reg:x7; val_offset:1716*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1716*FLEN/8, x13, x1, x6) + +inst_883: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82c9; op2val:0x81fb; + valaddr_reg:x7; val_offset:1718*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1718*FLEN/8, x13, x1, x6) + +inst_884: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x81fb; op2val:0x82c9; + valaddr_reg:x7; val_offset:1720*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1720*FLEN/8, x13, x1, x6) + +inst_885: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82c9; op2val:0x82fe; + valaddr_reg:x7; val_offset:1722*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1722*FLEN/8, x13, x1, x6) + +inst_886: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82fe; op2val:0x82c9; + valaddr_reg:x7; val_offset:1724*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1724*FLEN/8, x13, x1, x6) + +inst_887: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x064 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82c9; op2val:0x8064; + valaddr_reg:x7; val_offset:1726*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1726*FLEN/8, x13, x1, x6) + +inst_888: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3f1 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8047; op2val:0x83f1; + valaddr_reg:x7; val_offset:1728*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1728*FLEN/8, x13, x1, x6) + +inst_889: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3f1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x047 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x83f1; op2val:0x8047; + valaddr_reg:x7; val_offset:1730*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1730*FLEN/8, x13, x1, x6) + +inst_890: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x064 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8047; op2val:0x8064; + valaddr_reg:x7; val_offset:1732*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1732*FLEN/8, x13, x1, x6) + +inst_891: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x047 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82c9; op2val:0x8047; + valaddr_reg:x7; val_offset:1734*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1734*FLEN/8, x13, x1, x6) + +inst_892: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82c9; op2val:0xf0; + valaddr_reg:x7; val_offset:1736*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1736*FLEN/8, x13, x1, x6) + +inst_893: +// fs1 == 1 and fe1 == 0x11 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xc43f; op2val:0xf0; + valaddr_reg:x7; val_offset:1738*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1738*FLEN/8, x13, x1, x6) + +inst_894: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x03f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xc43f; + valaddr_reg:x7; val_offset:1740*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1740*FLEN/8, x13, x1, x6) + +inst_895: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x03f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82c9; op2val:0xc43f; + valaddr_reg:x7; val_offset:1742*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1742*FLEN/8, x13, x1, x6) + +inst_896: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x81fb; op2val:0x7ac0; + valaddr_reg:x7; val_offset:1744*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1744*FLEN/8, x13, x1, x6) + +inst_897: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x361 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf761; op2val:0x7ac0; + valaddr_reg:x7; val_offset:1746*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1746*FLEN/8, x13, x1, x6) + +inst_898: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb and fs2 == 1 and fe2 == 0x1d and fm2 == 0x361 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x81fb; op2val:0xf761; + valaddr_reg:x7; val_offset:1748*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1748*FLEN/8, x13, x1, x6) + +inst_899: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x81fb; op2val:0x81fb; + valaddr_reg:x7; val_offset:1750*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1750*FLEN/8, x13, x1, x6) + +inst_900: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb and fs2 == 0 and fe2 == 0x1e and fm2 == 0x016 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x81fb; op2val:0x7816; + valaddr_reg:x7; val_offset:1752*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1752*FLEN/8, x13, x1, x6) + +inst_901: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x361 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x016 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf761; op2val:0x7816; + valaddr_reg:x7; val_offset:1754*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1754*FLEN/8, x13, x1, x6) + +inst_902: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb and fs2 == 0 and fe2 == 0x1d and fm2 == 0x39f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x81fb; op2val:0x779f; + valaddr_reg:x7; val_offset:1756*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1756*FLEN/8, x13, x1, x6) + +inst_903: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x361 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x39f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf761; op2val:0x779f; + valaddr_reg:x7; val_offset:1758*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1758*FLEN/8, x13, x1, x6) + +inst_904: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb and fs2 == 0 and fe2 == 0x1d and fm2 == 0x081 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x81fb; op2val:0x7481; + valaddr_reg:x7; val_offset:1760*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1760*FLEN/8, x13, x1, x6) + +inst_905: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x361 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x081 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf761; op2val:0x7481; + valaddr_reg:x7; val_offset:1762*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1762*FLEN/8, x13, x1, x6) + +inst_906: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb and fs2 == 0 and fe2 == 0x1e and fm2 == 0x346 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x81fb; op2val:0x7b46; + valaddr_reg:x7; val_offset:1764*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1764*FLEN/8, x13, x1, x6) + +inst_907: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x361 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x346 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf761; op2val:0x7b46; + valaddr_reg:x7; val_offset:1766*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1766*FLEN/8, x13, x1, x6) + +inst_908: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3bd and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x81fb; op2val:0xf3bd; + valaddr_reg:x7; val_offset:1768*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1768*FLEN/8, x13, x1, x6) + +inst_909: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x361 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3bd and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf761; op2val:0xf3bd; + valaddr_reg:x7; val_offset:1770*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1770*FLEN/8, x13, x1, x6) + +inst_910: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0c2 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x81fb; op2val:0xf8c2; + valaddr_reg:x7; val_offset:1772*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1772*FLEN/8, x13, x1, x6) + +inst_911: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x361 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0c2 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf761; op2val:0xf8c2; + valaddr_reg:x7; val_offset:1774*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1774*FLEN/8, x13, x1, x6) + +inst_912: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2a9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x81fb; op2val:0xf6a9; + valaddr_reg:x7; val_offset:1776*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1776*FLEN/8, x13, x1, x6) + +inst_913: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x361 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2a9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf761; op2val:0xf6a9; + valaddr_reg:x7; val_offset:1778*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1778*FLEN/8, x13, x1, x6) + +inst_914: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3cf and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x81fb; op2val:0xf3cf; + valaddr_reg:x7; val_offset:1780*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1780*FLEN/8, x13, x1, x6) + +inst_915: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x361 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3cf and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf761; op2val:0xf3cf; + valaddr_reg:x7; val_offset:1782*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1782*FLEN/8, x13, x1, x6) + +inst_916: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb and fs2 == 1 and fe2 == 0x19 and fm2 == 0x068 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x81fb; op2val:0xe468; + valaddr_reg:x7; val_offset:1784*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1784*FLEN/8, x13, x1, x6) + +inst_917: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x1e7 and fs2 == 1 and fe2 == 0x19 and fm2 == 0x068 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xe9e7; op2val:0xe468; + valaddr_reg:x7; val_offset:1786*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1786*FLEN/8, x13, x1, x6) + +inst_918: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb and fs2 == 1 and fe2 == 0x1a and fm2 == 0x1e7 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x81fb; op2val:0xe9e7; + valaddr_reg:x7; val_offset:1788*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1788*FLEN/8, x13, x1, x6) + +inst_919: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x81fb; op2val:0x82fe; + valaddr_reg:x7; val_offset:1790*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1790*FLEN/8, x13, x1, x6) + +inst_920: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82fe; op2val:0x81fb; + valaddr_reg:x7; val_offset:1792*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1792*FLEN/8, x13, x1, x6) + +inst_921: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x064 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x81fb; op2val:0x8064; + valaddr_reg:x7; val_offset:1794*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1794*FLEN/8, x13, x1, x6) + +inst_922: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x032 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3f1 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8032; op2val:0x83f1; + valaddr_reg:x7; val_offset:1796*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1796*FLEN/8, x13, x1, x6) + +inst_923: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3f1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x032 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x83f1; op2val:0x8032; + valaddr_reg:x7; val_offset:1798*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1798*FLEN/8, x13, x1, x6) + +inst_924: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x032 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x064 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8032; op2val:0x8064; + valaddr_reg:x7; val_offset:1800*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1800*FLEN/8, x13, x1, x6) + +inst_925: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x032 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x81fb; op2val:0x8032; + valaddr_reg:x7; val_offset:1802*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1802*FLEN/8, x13, x1, x6) + +inst_926: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x81fb; op2val:0xf0; + valaddr_reg:x7; val_offset:1804*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1804*FLEN/8, x13, x1, x6) +RVTEST_SIGBASE(x1,signature_x1_7) + +inst_927: +// fs1 == 1 and fe1 == 0x10 and fm1 == 0x20b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xc20b; op2val:0xf0; + valaddr_reg:x7; val_offset:1806*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1806*FLEN/8, x13, x1, x6) + +inst_928: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x20b and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xc20b; + valaddr_reg:x7; val_offset:1808*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1808*FLEN/8, x13, x1, x6) + +inst_929: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb and fs2 == 1 and fe2 == 0x10 and fm2 == 0x20b and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x81fb; op2val:0xc20b; + valaddr_reg:x7; val_offset:1810*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1810*FLEN/8, x13, x1, x6) + +inst_930: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82fe; op2val:0x7ac0; + valaddr_reg:x7; val_offset:1812*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1812*FLEN/8, x13, x1, x6) + +inst_931: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x194 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf994; op2val:0x7ac0; + valaddr_reg:x7; val_offset:1814*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1814*FLEN/8, x13, x1, x6) + +inst_932: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x194 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82fe; op2val:0xf994; + valaddr_reg:x7; val_offset:1816*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1816*FLEN/8, x13, x1, x6) + +inst_933: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82fe; op2val:0x82fe; + valaddr_reg:x7; val_offset:1818*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1818*FLEN/8, x13, x1, x6) + +inst_934: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x016 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82fe; op2val:0x7816; + valaddr_reg:x7; val_offset:1820*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1820*FLEN/8, x13, x1, x6) + +inst_935: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x194 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x016 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf994; op2val:0x7816; + valaddr_reg:x7; val_offset:1822*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1822*FLEN/8, x13, x1, x6) + +inst_936: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fe and fs2 == 0 and fe2 == 0x1d and fm2 == 0x39f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82fe; op2val:0x779f; + valaddr_reg:x7; val_offset:1824*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1824*FLEN/8, x13, x1, x6) + +inst_937: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x194 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x39f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf994; op2val:0x779f; + valaddr_reg:x7; val_offset:1826*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1826*FLEN/8, x13, x1, x6) + +inst_938: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fe and fs2 == 0 and fe2 == 0x1d and fm2 == 0x081 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82fe; op2val:0x7481; + valaddr_reg:x7; val_offset:1828*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1828*FLEN/8, x13, x1, x6) + +inst_939: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x194 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x081 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf994; op2val:0x7481; + valaddr_reg:x7; val_offset:1830*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1830*FLEN/8, x13, x1, x6) + +inst_940: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x346 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82fe; op2val:0x7b46; + valaddr_reg:x7; val_offset:1832*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1832*FLEN/8, x13, x1, x6) + +inst_941: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x194 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x346 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf994; op2val:0x7b46; + valaddr_reg:x7; val_offset:1834*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1834*FLEN/8, x13, x1, x6) + +inst_942: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fe and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3bd and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82fe; op2val:0xf3bd; + valaddr_reg:x7; val_offset:1836*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1836*FLEN/8, x13, x1, x6) + +inst_943: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x194 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3bd and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf994; op2val:0xf3bd; + valaddr_reg:x7; val_offset:1838*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1838*FLEN/8, x13, x1, x6) + +inst_944: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0c2 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82fe; op2val:0xf8c2; + valaddr_reg:x7; val_offset:1840*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1840*FLEN/8, x13, x1, x6) + +inst_945: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x194 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0c2 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf994; op2val:0xf8c2; + valaddr_reg:x7; val_offset:1842*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1842*FLEN/8, x13, x1, x6) + +inst_946: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fe and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2a9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82fe; op2val:0xf6a9; + valaddr_reg:x7; val_offset:1844*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1844*FLEN/8, x13, x1, x6) + +inst_947: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x194 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2a9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf994; op2val:0xf6a9; + valaddr_reg:x7; val_offset:1846*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1846*FLEN/8, x13, x1, x6) + +inst_948: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fe and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3cf and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82fe; op2val:0xf3cf; + valaddr_reg:x7; val_offset:1848*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1848*FLEN/8, x13, x1, x6) + +inst_949: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x194 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3cf and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf994; op2val:0xf3cf; + valaddr_reg:x7; val_offset:1850*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1850*FLEN/8, x13, x1, x6) + +inst_950: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fe and fs2 == 1 and fe2 == 0x19 and fm2 == 0x068 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82fe; op2val:0xe468; + valaddr_reg:x7; val_offset:1852*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1852*FLEN/8, x13, x1, x6) + +inst_951: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x076 and fs2 == 1 and fe2 == 0x19 and fm2 == 0x068 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xec76; op2val:0xe468; + valaddr_reg:x7; val_offset:1854*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1854*FLEN/8, x13, x1, x6) + +inst_952: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fe and fs2 == 1 and fe2 == 0x1b and fm2 == 0x076 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82fe; op2val:0xec76; + valaddr_reg:x7; val_offset:1856*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1856*FLEN/8, x13, x1, x6) + +inst_953: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x064 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82fe; op2val:0x8064; + valaddr_reg:x7; val_offset:1858*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1858*FLEN/8, x13, x1, x6) + +inst_954: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x04c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3f1 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x804c; op2val:0x83f1; + valaddr_reg:x7; val_offset:1860*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1860*FLEN/8, x13, x1, x6) + +inst_955: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3f1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x04c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x83f1; op2val:0x804c; + valaddr_reg:x7; val_offset:1862*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1862*FLEN/8, x13, x1, x6) + +inst_956: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x04c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x064 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x804c; op2val:0x8064; + valaddr_reg:x7; val_offset:1864*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1864*FLEN/8, x13, x1, x6) + +inst_957: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x04c and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82fe; op2val:0x804c; + valaddr_reg:x7; val_offset:1866*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1866*FLEN/8, x13, x1, x6) + +inst_958: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82fe; op2val:0xf0; + valaddr_reg:x7; val_offset:1868*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1868*FLEN/8, x13, x1, x6) + +inst_959: +// fs1 == 1 and fe1 == 0x11 and fm1 == 0x092 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xc492; op2val:0xf0; + valaddr_reg:x7; val_offset:1870*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1870*FLEN/8, x13, x1, x6) + +inst_960: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x092 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xc492; + valaddr_reg:x7; val_offset:1872*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1872*FLEN/8, x13, x1, x6) + +inst_961: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fe and fs2 == 1 and fe2 == 0x11 and fm2 == 0x092 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x82fe; op2val:0xc492; + valaddr_reg:x7; val_offset:1874*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1874*FLEN/8, x13, x1, x6) + +inst_962: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x064 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8064; op2val:0x7ac0; + valaddr_reg:x7; val_offset:1876*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1876*FLEN/8, x13, x1, x6) + +inst_963: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x359 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb59; op2val:0x7ac0; + valaddr_reg:x7; val_offset:1878*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1878*FLEN/8, x13, x1, x6) + +inst_964: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x064 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x359 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8064; op2val:0xfb59; + valaddr_reg:x7; val_offset:1880*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1880*FLEN/8, x13, x1, x6) + +inst_965: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x064 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x064 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8064; op2val:0x8064; + valaddr_reg:x7; val_offset:1882*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1882*FLEN/8, x13, x1, x6) + +inst_966: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x064 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x016 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8064; op2val:0x7816; + valaddr_reg:x7; val_offset:1884*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1884*FLEN/8, x13, x1, x6) + +inst_967: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x359 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x016 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb59; op2val:0x7816; + valaddr_reg:x7; val_offset:1886*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1886*FLEN/8, x13, x1, x6) + +inst_968: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x064 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x39f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8064; op2val:0x779f; + valaddr_reg:x7; val_offset:1888*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1888*FLEN/8, x13, x1, x6) + +inst_969: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x359 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x39f and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb59; op2val:0x779f; + valaddr_reg:x7; val_offset:1890*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1890*FLEN/8, x13, x1, x6) + +inst_970: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x064 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x081 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8064; op2val:0x7481; + valaddr_reg:x7; val_offset:1892*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1892*FLEN/8, x13, x1, x6) + +inst_971: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x359 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x081 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb59; op2val:0x7481; + valaddr_reg:x7; val_offset:1894*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1894*FLEN/8, x13, x1, x6) + +inst_972: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x064 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x346 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8064; op2val:0x7b46; + valaddr_reg:x7; val_offset:1896*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1896*FLEN/8, x13, x1, x6) + +inst_973: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x359 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x346 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb59; op2val:0x7b46; + valaddr_reg:x7; val_offset:1898*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1898*FLEN/8, x13, x1, x6) + +inst_974: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x064 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3bd and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8064; op2val:0xf3bd; + valaddr_reg:x7; val_offset:1900*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1900*FLEN/8, x13, x1, x6) + +inst_975: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x359 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3bd and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb59; op2val:0xf3bd; + valaddr_reg:x7; val_offset:1902*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1902*FLEN/8, x13, x1, x6) + +inst_976: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x064 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0c2 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8064; op2val:0xf8c2; + valaddr_reg:x7; val_offset:1904*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1904*FLEN/8, x13, x1, x6) + +inst_977: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x359 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0c2 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb59; op2val:0xf8c2; + valaddr_reg:x7; val_offset:1906*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1906*FLEN/8, x13, x1, x6) + +inst_978: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x064 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2a9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8064; op2val:0xf6a9; + valaddr_reg:x7; val_offset:1908*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1908*FLEN/8, x13, x1, x6) + +inst_979: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x359 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2a9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb59; op2val:0xf6a9; + valaddr_reg:x7; val_offset:1910*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1910*FLEN/8, x13, x1, x6) + +inst_980: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x064 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3cf and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8064; op2val:0xf3cf; + valaddr_reg:x7; val_offset:1912*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1912*FLEN/8, x13, x1, x6) + +inst_981: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x359 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3cf and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb59; op2val:0xf3cf; + valaddr_reg:x7; val_offset:1914*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1914*FLEN/8, x13, x1, x6) + +inst_982: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x064 and fs2 == 1 and fe2 == 0x19 and fm2 == 0x068 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8064; op2val:0xe468; + valaddr_reg:x7; val_offset:1916*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1916*FLEN/8, x13, x1, x6) + +inst_983: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x1e0 and fs2 == 1 and fe2 == 0x19 and fm2 == 0x068 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xede0; op2val:0xe468; + valaddr_reg:x7; val_offset:1918*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1918*FLEN/8, x13, x1, x6) + +inst_984: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x064 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x1e0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8064; op2val:0xede0; + valaddr_reg:x7; val_offset:1920*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1920*FLEN/8, x13, x1, x6) + +inst_985: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x064 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1ae and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8064; op2val:0x1ae; + valaddr_reg:x7; val_offset:1922*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1922*FLEN/8, x13, x1, x6) + +inst_986: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3f1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1ae and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x83f1; op2val:0x1ae; + valaddr_reg:x7; val_offset:1924*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1924*FLEN/8, x13, x1, x6) + +inst_987: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x064 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3f1 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8064; op2val:0x83f1; + valaddr_reg:x7; val_offset:1926*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1926*FLEN/8, x13, x1, x6) + +inst_988: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x064 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x322 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8064; op2val:0x322; + valaddr_reg:x7; val_offset:1928*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1928*FLEN/8, x13, x1, x6) + +inst_989: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3f1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x322 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x83f1; op2val:0x322; + valaddr_reg:x7; val_offset:1930*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1930*FLEN/8, x13, x1, x6) + +inst_990: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x064 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8064; op2val:0x3a1; + valaddr_reg:x7; val_offset:1932*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1932*FLEN/8, x13, x1, x6) + +inst_991: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3f1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x83f1; op2val:0x3a1; + valaddr_reg:x7; val_offset:1934*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1934*FLEN/8, x13, x1, x6) + +inst_992: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x064 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x278 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8064; op2val:0x278; + valaddr_reg:x7; val_offset:1936*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1936*FLEN/8, x13, x1, x6) + +inst_993: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3f1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x278 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x83f1; op2val:0x278; + valaddr_reg:x7; val_offset:1938*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1938*FLEN/8, x13, x1, x6) + +inst_994: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x064 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8064; op2val:0x33d; + valaddr_reg:x7; val_offset:1940*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1940*FLEN/8, x13, x1, x6) + +inst_995: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3f1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33d and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x83f1; op2val:0x33d; + valaddr_reg:x7; val_offset:1942*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1942*FLEN/8, x13, x1, x6) + +inst_996: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x064 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8064; op2val:0x82f6; + valaddr_reg:x7; val_offset:1944*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1944*FLEN/8, x13, x1, x6) + +inst_997: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3f1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x83f1; op2val:0x82f6; + valaddr_reg:x7; val_offset:1946*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1946*FLEN/8, x13, x1, x6) + +inst_998: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x064 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8064; op2val:0x82c9; + valaddr_reg:x7; val_offset:1948*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1948*FLEN/8, x13, x1, x6) + +inst_999: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3f1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x83f1; op2val:0x82c9; + valaddr_reg:x7; val_offset:1950*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1950*FLEN/8, x13, x1, x6) + +inst_1000: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x064 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8064; op2val:0x81fb; + valaddr_reg:x7; val_offset:1952*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1952*FLEN/8, x13, x1, x6) + +inst_1001: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3f1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x83f1; op2val:0x81fb; + valaddr_reg:x7; val_offset:1954*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1954*FLEN/8, x13, x1, x6) + +inst_1002: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x064 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8064; op2val:0x82fe; + valaddr_reg:x7; val_offset:1956*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1956*FLEN/8, x13, x1, x6) + +inst_1003: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3f1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x83f1; op2val:0x82fe; + valaddr_reg:x7; val_offset:1958*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1958*FLEN/8, x13, x1, x6) + +inst_1004: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x064 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8064; op2val:0xf0; + valaddr_reg:x7; val_offset:1960*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1960*FLEN/8, x13, x1, x6) + +inst_1005: +// fs1 == 1 and fe1 == 0x11 and fm1 == 0x205 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xc605; op2val:0xf0; + valaddr_reg:x7; val_offset:1962*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1962*FLEN/8, x13, x1, x6) + +inst_1006: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x205 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xc605; + valaddr_reg:x7; val_offset:1964*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1964*FLEN/8, x13, x1, x6) + +inst_1007: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x064 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x205 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x8064; op2val:0xc605; + valaddr_reg:x7; val_offset:1966*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1966*FLEN/8, x13, x1, x6) + +inst_1008: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x7ac0; + valaddr_reg:x7; val_offset:1968*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1968*FLEN/8, x13, x1, x6) + +inst_1009: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xf0; + valaddr_reg:x7; val_offset:1970*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1970*FLEN/8, x13, x1, x6) + +inst_1010: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x016 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x7816; + valaddr_reg:x7; val_offset:1972*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1972*FLEN/8, x13, x1, x6) + +inst_1011: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x39f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x779f; + valaddr_reg:x7; val_offset:1974*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1974*FLEN/8, x13, x1, x6) + +inst_1012: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x081 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x7481; + valaddr_reg:x7; val_offset:1976*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1976*FLEN/8, x13, x1, x6) + +inst_1013: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x346 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x7b46; + valaddr_reg:x7; val_offset:1978*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1978*FLEN/8, x13, x1, x6) + +inst_1014: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3bd and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xf3bd; + valaddr_reg:x7; val_offset:1980*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1980*FLEN/8, x13, x1, x6) + +inst_1015: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0c2 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xf8c2; + valaddr_reg:x7; val_offset:1982*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1982*FLEN/8, x13, x1, x6) + +inst_1016: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2a9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xf6a9; + valaddr_reg:x7; val_offset:1984*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1984*FLEN/8, x13, x1, x6) + +inst_1017: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3cf and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xf3cf; + valaddr_reg:x7; val_offset:1986*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1986*FLEN/8, x13, x1, x6) + +inst_1018: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x19 and fm2 == 0x068 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0xe468; + valaddr_reg:x7; val_offset:1988*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1988*FLEN/8, x13, x1, x6) + +inst_1019: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1ae and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x1ae; + valaddr_reg:x7; val_offset:1990*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1990*FLEN/8, x13, x1, x6) + +inst_1020: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x322 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x322; + valaddr_reg:x7; val_offset:1992*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1992*FLEN/8, x13, x1, x6) + +inst_1021: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x3a1; + valaddr_reg:x7; val_offset:1994*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1994*FLEN/8, x13, x1, x6) + +inst_1022: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x278 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x278; + valaddr_reg:x7; val_offset:1996*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1996*FLEN/8, x13, x1, x6) + +inst_1023: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33d and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x33d; + valaddr_reg:x7; val_offset:1998*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 1998*FLEN/8, x13, x1, x6) + +inst_1024: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x82f6; + valaddr_reg:x7; val_offset:2000*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 2000*FLEN/8, x13, x1, x6) + +inst_1025: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x82c9; + valaddr_reg:x7; val_offset:2002*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 2002*FLEN/8, x13, x1, x6) + +inst_1026: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x81fb; + valaddr_reg:x7; val_offset:2004*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 2004*FLEN/8, x13, x1, x6) + +inst_1027: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x82fe; + valaddr_reg:x7; val_offset:2006*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 2006*FLEN/8, x13, x1, x6) + +inst_1028: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x064 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0; op2val:0x8064; + valaddr_reg:x7; val_offset:2008*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 2008*FLEN/8, x13, x1, x6) + +inst_1029: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ac0; op2val:0x7ac0; + valaddr_reg:x7; val_offset:2010*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 2010*FLEN/8, x13, x1, x6) + +inst_1030: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x016 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ac0; op2val:0x7816; + valaddr_reg:x7; val_offset:2012*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 2012*FLEN/8, x13, x1, x6) + +inst_1031: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x39f and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ac0; op2val:0x779f; + valaddr_reg:x7; val_offset:2014*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 2014*FLEN/8, x13, x1, x6) + +inst_1032: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a0 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmin.h ; op1:x30; op2:x29; dest:x31; op1val:0x79d5; op2val:0x3a0; + valaddr_reg:x7; val_offset:2016*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fmin.h, x31, x30, x29, 0, 0, x7, 2016*FLEN/8, x13, x1, x6) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(31424,32,FLEN) +NAN_BOXED(31424,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(30742,32,FLEN) +NAN_BOXED(30742,32,FLEN) +NAN_BOXED(31424,32,FLEN) +NAN_BOXED(31424,32,FLEN) +NAN_BOXED(31424,32,FLEN) +NAN_BOXED(30623,32,FLEN) +NAN_BOXED(31424,32,FLEN) +NAN_BOXED(31424,32,FLEN) +NAN_BOXED(29825,32,FLEN) +NAN_BOXED(29825,32,FLEN) +NAN_BOXED(31424,32,FLEN) +NAN_BOXED(31424,32,FLEN) +NAN_BOXED(31558,32,FLEN) +NAN_BOXED(31558,32,FLEN) +NAN_BOXED(31424,32,FLEN) +NAN_BOXED(31424,32,FLEN) +NAN_BOXED(62397,16,FLEN) +NAN_BOXED(62397,16,FLEN) +NAN_BOXED(31424,32,FLEN) +NAN_BOXED(31424,32,FLEN) +NAN_BOXED(63682,16,FLEN) +NAN_BOXED(63682,16,FLEN) +NAN_BOXED(31424,32,FLEN) +test_dataset_1: +NAN_BOXED(31424,32,FLEN) +NAN_BOXED(63145,16,FLEN) +NAN_BOXED(63145,16,FLEN) +NAN_BOXED(31424,32,FLEN) +NAN_BOXED(31424,32,FLEN) +NAN_BOXED(62415,16,FLEN) +NAN_BOXED(62415,16,FLEN) +NAN_BOXED(31424,32,FLEN) +NAN_BOXED(31424,32,FLEN) +NAN_BOXED(58472,16,FLEN) +NAN_BOXED(28006,32,FLEN) +NAN_BOXED(61826,16,FLEN) +NAN_BOXED(61826,16,FLEN) +NAN_BOXED(28006,32,FLEN) +NAN_BOXED(28006,32,FLEN) +NAN_BOXED(58472,16,FLEN) +NAN_BOXED(31424,32,FLEN) +NAN_BOXED(28006,32,FLEN) +NAN_BOXED(31424,32,FLEN) +NAN_BOXED(430,32,FLEN) +NAN_BOXED(928,32,FLEN) +NAN_BOXED(30276,32,FLEN) +test_dataset_2: +NAN_BOXED(30276,16,FLEN) +NAN_BOXED(928,16,FLEN) +NAN_BOXED(928,16,FLEN) +NAN_BOXED(430,16,FLEN) +NAN_BOXED(31424,16,FLEN) +NAN_BOXED(928,16,FLEN) +NAN_BOXED(31424,16,FLEN) +NAN_BOXED(802,16,FLEN) +NAN_BOXED(928,16,FLEN) +NAN_BOXED(31189,16,FLEN) +NAN_BOXED(31189,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(928,16,FLEN) +NAN_BOXED(802,16,FLEN) +NAN_BOXED(31424,16,FLEN) +NAN_BOXED(929,16,FLEN) +NAN_BOXED(928,16,FLEN) +NAN_BOXED(31426,16,FLEN) +NAN_BOXED(31426,16,FLEN) +NAN_BOXED(928,16,FLEN) +NAN_BOXED(928,16,FLEN) +NAN_BOXED(929,16,FLEN) +NAN_BOXED(31424,16,FLEN) +NAN_BOXED(632,16,FLEN) +NAN_BOXED(928,16,FLEN) +NAN_BOXED(30875,16,FLEN) +NAN_BOXED(30875,16,FLEN) +NAN_BOXED(928,16,FLEN) +NAN_BOXED(928,16,FLEN) +NAN_BOXED(632,16,FLEN) +NAN_BOXED(31424,16,FLEN) +NAN_BOXED(829,16,FLEN) +NAN_BOXED(928,16,FLEN) +NAN_BOXED(31240,16,FLEN) +NAN_BOXED(31240,16,FLEN) +NAN_BOXED(928,16,FLEN) +NAN_BOXED(928,16,FLEN) +NAN_BOXED(829,16,FLEN) +NAN_BOXED(31424,16,FLEN) +NAN_BOXED(33526,16,FLEN) +NAN_BOXED(928,16,FLEN) +NAN_BOXED(63876,16,FLEN) +NAN_BOXED(63876,16,FLEN) +NAN_BOXED(928,16,FLEN) +NAN_BOXED(928,16,FLEN) +NAN_BOXED(33526,16,FLEN) +NAN_BOXED(31424,16,FLEN) +NAN_BOXED(33481,16,FLEN) +NAN_BOXED(928,16,FLEN) +NAN_BOXED(63792,16,FLEN) +NAN_BOXED(63792,16,FLEN) +NAN_BOXED(928,16,FLEN) +NAN_BOXED(928,16,FLEN) +NAN_BOXED(33481,16,FLEN) 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+NAN_BOXED(32868,16,FLEN) +NAN_BOXED(31424,16,FLEN) +NAN_BOXED(64345,16,FLEN) +NAN_BOXED(31424,16,FLEN) +NAN_BOXED(32868,16,FLEN) +NAN_BOXED(64345,16,FLEN) +NAN_BOXED(32868,16,FLEN) +NAN_BOXED(32868,16,FLEN) +NAN_BOXED(32868,16,FLEN) +NAN_BOXED(30742,16,FLEN) +NAN_BOXED(64345,16,FLEN) +NAN_BOXED(30742,16,FLEN) +NAN_BOXED(32868,16,FLEN) +NAN_BOXED(30623,16,FLEN) +NAN_BOXED(64345,16,FLEN) +NAN_BOXED(30623,16,FLEN) +NAN_BOXED(32868,16,FLEN) +NAN_BOXED(29825,16,FLEN) +NAN_BOXED(64345,16,FLEN) +NAN_BOXED(29825,16,FLEN) +NAN_BOXED(32868,16,FLEN) +NAN_BOXED(31558,16,FLEN) +NAN_BOXED(64345,16,FLEN) +NAN_BOXED(31558,16,FLEN) +NAN_BOXED(32868,16,FLEN) +NAN_BOXED(62397,16,FLEN) +NAN_BOXED(64345,16,FLEN) +NAN_BOXED(62397,16,FLEN) +NAN_BOXED(32868,16,FLEN) +NAN_BOXED(63682,16,FLEN) +NAN_BOXED(64345,16,FLEN) +NAN_BOXED(63682,16,FLEN) +NAN_BOXED(32868,16,FLEN) +NAN_BOXED(63145,16,FLEN) +NAN_BOXED(64345,16,FLEN) +NAN_BOXED(63145,16,FLEN) +NAN_BOXED(32868,16,FLEN) +NAN_BOXED(62415,16,FLEN) +NAN_BOXED(64345,16,FLEN) +NAN_BOXED(62415,16,FLEN) +NAN_BOXED(32868,16,FLEN) +NAN_BOXED(58472,16,FLEN) +NAN_BOXED(60896,16,FLEN) +NAN_BOXED(58472,16,FLEN) +NAN_BOXED(32868,16,FLEN) +NAN_BOXED(60896,16,FLEN) +NAN_BOXED(32868,16,FLEN) +NAN_BOXED(430,16,FLEN) +NAN_BOXED(33777,16,FLEN) +NAN_BOXED(430,16,FLEN) +NAN_BOXED(32868,16,FLEN) +NAN_BOXED(33777,16,FLEN) +NAN_BOXED(32868,16,FLEN) +NAN_BOXED(802,16,FLEN) +NAN_BOXED(33777,16,FLEN) +NAN_BOXED(802,16,FLEN) +NAN_BOXED(32868,16,FLEN) +NAN_BOXED(929,16,FLEN) +NAN_BOXED(33777,16,FLEN) +NAN_BOXED(929,16,FLEN) +NAN_BOXED(32868,16,FLEN) +NAN_BOXED(632,16,FLEN) +NAN_BOXED(33777,16,FLEN) +NAN_BOXED(632,16,FLEN) +NAN_BOXED(32868,16,FLEN) +NAN_BOXED(829,16,FLEN) +NAN_BOXED(33777,16,FLEN) +NAN_BOXED(829,16,FLEN) +NAN_BOXED(32868,16,FLEN) +NAN_BOXED(33526,16,FLEN) +NAN_BOXED(33777,16,FLEN) +NAN_BOXED(33526,16,FLEN) +NAN_BOXED(32868,16,FLEN) +NAN_BOXED(33481,16,FLEN) +NAN_BOXED(33777,16,FLEN) +NAN_BOXED(33481,16,FLEN) +NAN_BOXED(32868,16,FLEN) +NAN_BOXED(33275,16,FLEN) +NAN_BOXED(33777,16,FLEN) +NAN_BOXED(33275,16,FLEN) +NAN_BOXED(32868,16,FLEN) +NAN_BOXED(33534,16,FLEN) +NAN_BOXED(33777,16,FLEN) +NAN_BOXED(33534,16,FLEN) +NAN_BOXED(32868,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(50693,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(50693,16,FLEN) +NAN_BOXED(32868,16,FLEN) +NAN_BOXED(50693,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(31424,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(30742,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(30623,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(29825,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(31558,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(62397,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(63682,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(63145,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(62415,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(58472,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(430,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(802,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(929,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(632,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(829,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(33526,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(33481,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(33275,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(33534,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(32868,16,FLEN) +NAN_BOXED(31424,16,FLEN) +NAN_BOXED(31424,16,FLEN) +NAN_BOXED(31424,16,FLEN) +NAN_BOXED(30742,16,FLEN) +NAN_BOXED(31424,16,FLEN) +NAN_BOXED(30623,16,FLEN) +NAN_BOXED(31189,16,FLEN) +NAN_BOXED(928,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x8_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x8_1: + .fill 30*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x21_0: + .fill 32*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_0: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_2: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_3: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_4: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_5: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_6: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_7: + .fill 212*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fmsub_b14-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fmsub_b14-01.S new file mode 100644 index 000000000..9b39ad3d5 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fmsub_b14-01.S @@ -0,0 +1,424 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 05:33:17 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fmsub.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fmsub.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fmsub_b14 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fmsub_b14) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x1,test_dataset_0) +RVTEST_SIGBASE(x4,signature_x4_1) + +inst_0: +// rs1 == rs2 == rs3 != rd, rs1==x0, rs2==x0, rs3==x0, rd==x20, +/* opcode: fmsub.h ; op1:x0; op2:x0; op3:x0; dest:x20; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x1; val_offset:0*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x20, x0, x0, x0, dyn, 0, 0, x1, 0*FLEN/8, x6, x4, x7) + +inst_1: +// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==x27, rs2==x11, rs3==x25, rd==x19, +/* opcode: fmsub.h ; op1:x27; op2:x11; op3:x25; dest:x19; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x1; val_offset:3*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x19, x27, x11, x25, dyn, 0, 0, x1, 3*FLEN/8, x6, x4, x7) + +inst_2: +// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==x18, rs2==x18, rs3==x20, rd==x8, +/* opcode: fmsub.h ; op1:x18; op2:x18; op3:x20; dest:x8; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x1; val_offset:6*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x8, x18, x18, x20, dyn, 0, 0, x1, 6*FLEN/8, x6, x4, x7) + +inst_3: +// rd == rs2 == rs3 != rs1, rs1==x30, rs2==x16, rs3==x16, rd==x16, +/* opcode: fmsub.h ; op1:x30; op2:x16; op3:x16; dest:x16; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x1; val_offset:9*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x16, x30, x16, x16, dyn, 0, 0, x1, 9*FLEN/8, x6, x4, x7) + +inst_4: +// rs1 == rs2 == rs3 == rd, rs1==x9, rs2==x9, rs3==x9, rd==x9, +/* opcode: fmsub.h ; op1:x9; op2:x9; op3:x9; dest:x9; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x1; val_offset:12*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x9, x9, x9, x9, dyn, 0, 0, x1, 12*FLEN/8, x6, x4, x7) + +inst_5: +// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==x25, rs2==x12, rs3==x8, rd==x12, +/* opcode: fmsub.h ; op1:x25; op2:x12; op3:x8; dest:x12; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x1; val_offset:15*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x12, x25, x12, x8, dyn, 0, 0, x1, 15*FLEN/8, x6, x4, x7) + +inst_6: +// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==x10, rs2==x21, rs3==x11, rd==x11, +/* opcode: fmsub.h ; op1:x10; op2:x21; op3:x11; dest:x11; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x1; val_offset:18*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x11, x10, x21, x11, dyn, 0, 0, x1, 18*FLEN/8, x6, x4, x7) + +inst_7: +// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==x23, rs2==x17, rs3==x6, rd==x23, +/* opcode: fmsub.h ; op1:x23; op2:x17; op3:x6; dest:x23; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x1; val_offset:21*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x23, x23, x17, x6, dyn, 0, 0, x1, 21*FLEN/8, x6, x4, x7) + +inst_8: +// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==x20, rs2==x22, rs3==x22, rd==x28, +/* opcode: fmsub.h ; op1:x20; op2:x22; op3:x22; dest:x28; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x1; val_offset:24*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x28, x20, x22, x22, dyn, 0, 0, x1, 24*FLEN/8, x6, x4, x7) + +inst_9: +// rs1 == rs2 == rd != rs3, rs1==x5, rs2==x5, rs3==x18, rd==x5, +/* opcode: fmsub.h ; op1:x5; op2:x5; op3:x18; dest:x5; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x1; val_offset:27*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x5, x5, x5, x18, dyn, 0, 0, x1, 27*FLEN/8, x6, x4, x7) + +inst_10: +// rs1 == rd == rs3 != rs2, rs1==x3, rs2==x2, rs3==x3, rd==x3, +/* opcode: fmsub.h ; op1:x3; op2:x2; op3:x3; dest:x3; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x1; val_offset:30*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x3, x3, x2, x3, dyn, 0, 0, x1, 30*FLEN/8, x6, x4, x7) + +inst_11: +// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==x15, rs2==x31, rs3==x15, rd==x21, +/* opcode: fmsub.h ; op1:x15; op2:x31; op3:x15; dest:x21; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x1; val_offset:33*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x21, x15, x31, x15, dyn, 0, 0, x1, 33*FLEN/8, x6, x4, x7) +RVTEST_VALBASEUPD(x5,test_dataset_1) + +inst_12: +// rs1==x21, rs2==x1, rs3==x31, rd==x2, +/* opcode: fmsub.h ; op1:x21; op2:x1; op3:x31; dest:x2; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x5; val_offset:0*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x2, x21, x1, x31, dyn, 0, 0, x5, 0*FLEN/8, x9, x4, x7) + +inst_13: +// rs1==x6, rs2==x8, rs3==x26, rd==x29, +/* opcode: fmsub.h ; op1:x6; op2:x8; op3:x26; dest:x29; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x5; val_offset:3*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x29, x6, x8, x26, dyn, 0, 0, x5, 3*FLEN/8, x9, x4, x7) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_14: +// rs1==x31, rs2==x6, rs3==x1, rd==x26, +/* opcode: fmsub.h ; op1:x31; op2:x6; op3:x1; dest:x26; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x5; val_offset:6*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x26, x31, x6, x1, dyn, 0, 0, x5, 6*FLEN/8, x9, x1, x3) + +inst_15: +// rs1==x17, rs2==x23, rs3==x7, rd==x14, +/* opcode: fmsub.h ; op1:x17; op2:x23; op3:x7; dest:x14; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x5; val_offset:9*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x14, x17, x23, x7, dyn, 0, 0, x5, 9*FLEN/8, x9, x1, x3) + +inst_16: +// rs1==x22, rs2==x19, rs3==x29, rd==x13, +/* opcode: fmsub.h ; op1:x22; op2:x19; op3:x29; dest:x13; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x5; val_offset:12*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x13, x22, x19, x29, dyn, 0, 0, x5, 12*FLEN/8, x9, x1, x3) + +inst_17: +// rs1==x2, rs2==x20, rs3==x17, rd==x25, +/* opcode: fmsub.h ; op1:x2; op2:x20; op3:x17; dest:x25; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x5; val_offset:15*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x25, x2, x20, x17, dyn, 0, 0, x5, 15*FLEN/8, x9, x1, x3) + +inst_18: +// rs1==x14, rs2==x26, rs3==x24, rd==x22, +/* opcode: fmsub.h ; op1:x14; op2:x26; op3:x24; dest:x22; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x5; val_offset:18*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x22, x14, x26, x24, dyn, 0, 0, x5, 18*FLEN/8, x9, x1, x3) + +inst_19: +// rs1==x11, rs2==x7, rs3==x13, rd==x17, +/* opcode: fmsub.h ; op1:x11; op2:x7; op3:x13; dest:x17; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x5; val_offset:21*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x17, x11, x7, x13, dyn, 0, 0, x5, 21*FLEN/8, x9, x1, x3) + +inst_20: +// rs1==x16, rs2==x30, rs3==x5, rd==x0, +/* opcode: fmsub.h ; op1:x16; op2:x30; op3:x5; dest:x0; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x5; val_offset:24*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x0, x16, x30, x5, dyn, 0, 0, x5, 24*FLEN/8, x9, x1, x3) + +inst_21: +// rs1==x8, rs2==x4, rs3==x21, rd==x31, +/* opcode: fmsub.h ; op1:x8; op2:x4; op3:x21; dest:x31; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x5; val_offset:27*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x8, x4, x21, dyn, 0, 0, x5, 27*FLEN/8, x9, x1, x3) + +inst_22: +// rs1==x19, rs2==x10, rs3==x4, rd==x30, +/* opcode: fmsub.h ; op1:x19; op2:x10; op3:x4; dest:x30; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x5; val_offset:30*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x30, x19, x10, x4, dyn, 0, 0, x5, 30*FLEN/8, x9, x1, x3) + +inst_23: +// rs1==x28, rs2==x15, rs3==x19, rd==x6, +/* opcode: fmsub.h ; op1:x28; op2:x15; op3:x19; dest:x6; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x5; val_offset:33*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x6, x28, x15, x19, dyn, 0, 0, x5, 33*FLEN/8, x9, x1, x3) +RVTEST_VALBASEUPD(x6,test_dataset_2) + +inst_24: +// rs1==x13, rs2==x29, rs3==x27, rd==x15, +/* opcode: fmsub.h ; op1:x13; op2:x29; op3:x27; dest:x15; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x6; val_offset:0*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x15, x13, x29, x27, dyn, 0, 0, x6, 0*FLEN/8, x8, x1, x3) + +inst_25: +// rs1==x24, rs2==x25, rs3==x10, rd==x27, +/* opcode: fmsub.h ; op1:x24; op2:x25; op3:x10; dest:x27; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x6; val_offset:3*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x27, x24, x25, x10, dyn, 0, 0, x6, 3*FLEN/8, x8, x1, x3) + +inst_26: +// rs1==x7, rs2==x27, rs3==x2, rd==x10, +/* opcode: fmsub.h ; op1:x7; op2:x27; op3:x2; dest:x10; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x6; val_offset:6*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x10, x7, x27, x2, dyn, 0, 0, x6, 6*FLEN/8, x8, x1, x5) + +inst_27: +// rs1==x26, rs2==x14, rs3==x12, rd==x4, +/* opcode: fmsub.h ; op1:x26; op2:x14; op3:x12; dest:x4; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x6; val_offset:9*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x4, x26, x14, x12, dyn, 0, 0, x6, 9*FLEN/8, x8, x1, x5) + +inst_28: +// rs1==x29, rs2==x28, rs3==x30, rd==x24, +/* opcode: fmsub.h ; op1:x29; op2:x28; op3:x30; dest:x24; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x6; val_offset:12*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x24, x29, x28, x30, dyn, 0, 0, x6, 12*FLEN/8, x8, x1, x5) + +inst_29: +// rs1==x4, rs2==x3, rs3==x28, rd==x18, +/* opcode: fmsub.h ; op1:x4; op2:x3; op3:x28; dest:x18; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x6; val_offset:15*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x18, x4, x3, x28, dyn, 0, 0, x6, 15*FLEN/8, x8, x1, x5) +RVTEST_SIGBASE(x2,signature_x2_0) + +inst_30: +// rs1==x1, rs2==x13, rs3==x23, rd==x7, +/* opcode: fmsub.h ; op1:x1; op2:x13; op3:x23; dest:x7; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x6; val_offset:18*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x7, x1, x13, x23, dyn, 0, 0, x6, 18*FLEN/8, x8, x2, x5) + +inst_31: +// rs1==x12, rs2==x24, rs3==x14, rd==x1, +/* opcode: fmsub.h ; op1:x12; op2:x24; op3:x14; dest:x1; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x6; val_offset:21*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x1, x12, x24, x14, dyn, 0, 0, x6, 21*FLEN/8, x8, x2, x5) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +test_dataset_1: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +test_dataset_2: +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x4_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x4_1: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_0: + .fill 32*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_0: + .fill 4*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fmsub_b16-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fmsub_b16-01.S new file mode 100644 index 000000000..45d14dcaa --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fmsub_b16-01.S @@ -0,0 +1,2229 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 05:33:17 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fmsub.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fmsub.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fmsub_b16 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fmsub_b16) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x6,test_dataset_0) +RVTEST_SIGBASE(x2,signature_x2_1) + +inst_0: +// rs1 == rs2 == rs3 != rd, rs1==x19, rs2==x19, rs3==x19, rd==x14,fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x19; op2:x19; op3:x19; dest:x14; op1val:0x704c; op2val:0x704c; +op3val:0x704c; valaddr_reg:x6; val_offset:0*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x14, x19, x19, x19, dyn, 0, 0, x6, 0*FLEN/8, x8, x2, x3) + +inst_1: +// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==x11, rs2==x5, rs3==x13, rd==x16,fs1 == 0 and fe1 == 0x1d and fm1 == 0x014 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3ec and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x11; op2:x5; op3:x13; dest:x16; op1val:0x7414; op2val:0x77ec; +op3val:0x7bff; valaddr_reg:x6; val_offset:3*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x16, x11, x5, x13, dyn, 0, 0, x6, 3*FLEN/8, x8, x2, x3) + +inst_2: +// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==x30, rs2==x30, rs3==x17, rd==x25,fs1 == 0 and fe1 == 0x1e and fm1 == 0x135 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x24e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x30; op3:x17; dest:x25; op1val:0x7935; op2val:0x7935; +op3val:0x7bff; valaddr_reg:x6; val_offset:6*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x25, x30, x30, x17, dyn, 0, 0, x6, 6*FLEN/8, x8, x2, x3) + +inst_3: +// rd == rs2 == rs3 != rs1, rs1==x10, rs2==x1, rs3==x1, rd==x1,fs1 == 0 and fe1 == 0x19 and fm1 == 0x340 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ae and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x10; op2:x1; op3:x1; dest:x1; op1val:0x6740; op2val:0x7aae; +op3val:0x7aae; valaddr_reg:x6; val_offset:9*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x1, x10, x1, x1, dyn, 0, 0, x6, 9*FLEN/8, x8, x2, x3) + +inst_4: +// rs1 == rs2 == rs3 == rd, rs1==x7, rs2==x7, rs3==x7, rd==x7,fs1 == 0 and fe1 == 0x1e and fm1 == 0x218 and fs2 == 0 and fe2 == 0x16 and fm2 == 0x04f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x7; op2:x7; op3:x7; dest:x7; op1val:0x7a18; op2val:0x7a18; +op3val:0x7a18; valaddr_reg:x6; val_offset:12*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x7, x7, x7, x7, dyn, 0, 0, x6, 12*FLEN/8, x8, x2, x3) + +inst_5: +// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==x25, rs2==x27, rs3==x24, rd==x27,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c4 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x351 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x25; op2:x27; op3:x24; dest:x27; op1val:0x79c4; op2val:0x7351; +op3val:0x7bff; valaddr_reg:x6; val_offset:15*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x27, x25, x27, x24, dyn, 0, 0, x6, 15*FLEN/8, x8, x2, x3) + +inst_6: +// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==x9, rs2==x29, rs3==x23, rd==x23,fs1 == 0 and fe1 == 0x1e and fm1 == 0x335 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x3d3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x9; op2:x29; op3:x23; dest:x23; op1val:0x7b35; op2val:0x67d3; +op3val:0x7bff; valaddr_reg:x6; val_offset:18*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x23, x9, x29, x23, dyn, 0, 0, x6, 18*FLEN/8, x8, x2, x3) + +inst_7: +// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==x31, rs2==x0, rs3==x22, rd==x31,fs1 == 0 and fe1 == 0x1e and fm1 == 0x054 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x382 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x31; op2:x0; op3:x22; dest:x31; op1val:0x7854; op2val:0x0; +op3val:0x7bff; valaddr_reg:x6; val_offset:21*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x31, x0, x22, dyn, 0, 0, x6, 21*FLEN/8, x8, x2, x3) + +inst_8: +// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==x13, rs2==x16, rs3==x16, rd==x20,fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ed and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2c0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x13; op2:x16; op3:x16; dest:x20; op1val:0x72ed; op2val:0x76c0; +op3val:0x76c0; valaddr_reg:x6; val_offset:24*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x20, x13, x16, x16, dyn, 0, 0, x6, 24*FLEN/8, x8, x2, x3) + +inst_9: +// rs1 == rs2 == rd != rs3, rs1==x24, rs2==x24, rs3==x9, rd==x24,fs1 == 0 and fe1 == 0x1c and fm1 == 0x317 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x300 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x24; op2:x24; op3:x9; dest:x24; op1val:0x7317; op2val:0x7317; +op3val:0x7bff; valaddr_reg:x6; val_offset:27*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x24, x24, x24, x9, dyn, 0, 0, x6, 27*FLEN/8, x8, x2, x3) + +inst_10: +// rs1 == rd == rs3 != rs2, rs1==x4, rs2==x26, rs3==x4, rd==x4,fs1 == 0 and fe1 == 0x1c and fm1 == 0x374 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x362 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x4; op2:x26; op3:x4; dest:x4; op1val:0x7374; op2val:0x7362; +op3val:0x7374; valaddr_reg:x6; val_offset:30*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x4, x4, x26, x4, dyn, 0, 0, x6, 30*FLEN/8, x8, x2, x3) + +inst_11: +// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==x29, rs2==x28, rs3==x29, rd==x17,fs1 == 0 and fe1 == 0x1d and fm1 == 0x359 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0a2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x29; op2:x28; op3:x29; dest:x17; op1val:0x7759; op2val:0x74a2; +op3val:0x7759; valaddr_reg:x6; val_offset:33*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x17, x29, x28, x29, dyn, 0, 0, x6, 33*FLEN/8, x8, x2, x3) +RVTEST_VALBASEUPD(x7,test_dataset_1) + +inst_12: +// rs1==x22, rs2==x6, rs3==x27, rd==x19,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x073 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x22; op2:x6; op3:x27; dest:x19; op1val:0x7ab2; op2val:0x7873; +op3val:0x7bff; valaddr_reg:x7; val_offset:0*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x19, x22, x6, x27, dyn, 0, 0, x7, 0*FLEN/8, x9, x2, x3) + +inst_13: +// rs1==x0, rs2==x20, rs3==x15, rd==x28,fs1 == 0 and fe1 == 0x1c and fm1 == 0x1f2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ef and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x0; op2:x20; op3:x15; dest:x28; op1val:0x0; op2val:0x7bef; +op3val:0x7bff; valaddr_reg:x7; val_offset:3*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x28, x0, x20, x15, dyn, 0, 0, x7, 3*FLEN/8, x9, x2, x4) + +inst_14: +// rs1==x21, rs2==x18, rs3==x14, rd==x12,fs1 == 0 and fe1 == 0x1b and fm1 == 0x3bb and fs2 == 0 and fe2 == 0x1d and fm2 == 0x152 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x21; op2:x18; op3:x14; dest:x12; op1val:0x6fbb; op2val:0x7552; +op3val:0x7bff; valaddr_reg:x7; val_offset:6*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x12, x21, x18, x14, dyn, 0, 0, x7, 6*FLEN/8, x9, x2, x4) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_15: +// rs1==x12, rs2==x21, rs3==x20, rd==x18,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1af and fs2 == 0 and fe2 == 0x1e and fm2 == 0x37c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x12; op2:x21; op3:x20; dest:x18; op1val:0x79af; op2val:0x7b7c; +op3val:0x7bff; valaddr_reg:x7; val_offset:9*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x18, x12, x21, x20, dyn, 0, 0, x7, 9*FLEN/8, x9, x1, x4) + +inst_16: +// rs1==x18, rs2==x3, rs3==x12, rd==x6,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x15c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x18; op2:x3; op3:x12; dest:x6; op1val:0x7aa3; op2val:0x795c; +op3val:0x7bff; valaddr_reg:x7; val_offset:12*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x6, x18, x3, x12, dyn, 0, 0, x7, 12*FLEN/8, x9, x1, x4) + +inst_17: +// rs1==x17, rs2==x23, rs3==x26, rd==x3,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x30e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x17; op2:x23; op3:x26; dest:x3; op1val:0x78b2; op2val:0x7b0e; +op3val:0x7bff; valaddr_reg:x7; val_offset:15*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x3, x17, x23, x26, dyn, 0, 0, x7, 15*FLEN/8, x9, x1, x4) + +inst_18: +// rs1==x28, rs2==x17, rs3==x6, rd==x30,fs1 == 0 and fe1 == 0x1e and fm1 == 0x00a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0b5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x28; op2:x17; op3:x6; dest:x30; op1val:0x780a; op2val:0x78b5; +op3val:0x7bff; valaddr_reg:x7; val_offset:18*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x30, x28, x17, x6, dyn, 0, 0, x7, 18*FLEN/8, x9, x1, x4) + +inst_19: +// rs1==x14, rs2==x2, rs3==x10, rd==x5,fs1 == 0 and fe1 == 0x1c and fm1 == 0x3c3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x260 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x14; op2:x2; op3:x10; dest:x5; op1val:0x73c3; op2val:0x7a60; +op3val:0x7bff; valaddr_reg:x7; val_offset:21*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x5, x14, x2, x10, dyn, 0, 0, x7, 21*FLEN/8, x9, x1, x4) + +inst_20: +// rs1==x6, rs2==x12, rs3==x8, rd==x15,fs1 == 0 and fe1 == 0x1c and fm1 == 0x188 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x063 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x6; op2:x12; op3:x8; dest:x15; op1val:0x7188; op2val:0x7863; +op3val:0x7bff; valaddr_reg:x7; val_offset:24*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x15, x6, x12, x8, dyn, 0, 0, x7, 24*FLEN/8, x9, x1, x4) + +inst_21: +// rs1==x16, rs2==x13, rs3==x31, rd==x21,fs1 == 0 and fe1 == 0x1e and fm1 == 0x164 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x16; op2:x13; op3:x31; dest:x21; op1val:0x7964; op2val:0x75fe; +op3val:0x7bff; valaddr_reg:x7; val_offset:27*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x21, x16, x13, x31, dyn, 0, 0, x7, 27*FLEN/8, x9, x1, x4) + +inst_22: +// rs1==x27, rs2==x8, rs3==x25, rd==x26,fs1 == 0 and fe1 == 0x1e and fm1 == 0x010 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x239 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x27; op2:x8; op3:x25; dest:x26; op1val:0x7810; op2val:0x7a39; +op3val:0x7bff; valaddr_reg:x7; val_offset:30*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x26, x27, x8, x25, dyn, 0, 0, x7, 30*FLEN/8, x9, x1, x4) + +inst_23: +// rs1==x26, rs2==x22, rs3==x30, rd==x0,fs1 == 0 and fe1 == 0x1d and fm1 == 0x249 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3d4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x26; op2:x22; op3:x30; dest:x0; op1val:0x7649; op2val:0x77d4; +op3val:0x7bff; valaddr_reg:x7; val_offset:33*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x0, x26, x22, x30, dyn, 0, 0, x7, 33*FLEN/8, x9, x1, x4) + +inst_24: +// rs1==x8, rs2==x31, rs3==x3, rd==x29,fs1 == 0 and fe1 == 0x1a and fm1 == 0x190 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x19f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x8; op2:x31; op3:x3; dest:x29; op1val:0x6990; op2val:0x799f; +op3val:0x7bff; valaddr_reg:x7; val_offset:36*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x29, x8, x31, x3, dyn, 0, 0, x7, 36*FLEN/8, x9, x1, x4) +RVTEST_VALBASEUPD(x7,test_dataset_2) + +inst_25: +// rs1==x15, rs2==x14, rs3==x0, rd==x10,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0be and fs2 == 0 and fe2 == 0x1d and fm2 == 0x24b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x15; op2:x14; op3:x0; dest:x10; op1val:0x78be; op2val:0x764b; +op3val:0x0; valaddr_reg:x7; val_offset:0*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x10, x15, x14, x0, dyn, 0, 0, x7, 0*FLEN/8, x12, x1, x4) + +inst_26: +// rs1==x20, rs2==x25, rs3==x2, rd==x13,fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3da and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x20; op2:x25; op3:x2; dest:x13; op1val:0x7804; op2val:0x7bda; +op3val:0x7bff; valaddr_reg:x7; val_offset:3*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x13, x20, x25, x2, dyn, 0, 0, x7, 3*FLEN/8, x12, x1, x4) + +inst_27: +// rs1==x5, rs2==x10, rs3==x18, rd==x2,fs1 == 0 and fe1 == 0x1e and fm1 == 0x050 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x5; op2:x10; op3:x18; dest:x2; op1val:0x7850; op2val:0x7ae1; +op3val:0x7bff; valaddr_reg:x7; val_offset:6*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x2, x5, x10, x18, dyn, 0, 0, x7, 6*FLEN/8, x12, x1, x6) + +inst_28: +// rs1==x2, rs2==x15, rs3==x11, rd==x9,fs1 == 0 and fe1 == 0x1e and fm1 == 0x01b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x39d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x2; op2:x15; op3:x11; dest:x9; op1val:0x781b; op2val:0x7b9d; +op3val:0x7bff; valaddr_reg:x7; val_offset:9*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x9, x2, x15, x11, dyn, 0, 0, x7, 9*FLEN/8, x12, x1, x6) +RVTEST_SIGBASE(x2,signature_x2_2) + +inst_29: +// rs1==x3, rs2==x4, rs3==x5, rd==x11,fs1 == 0 and fe1 == 0x1d and fm1 == 0x357 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x04e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x3; op2:x4; op3:x5; dest:x11; op1val:0x7757; op2val:0x744e; +op3val:0x7bff; valaddr_reg:x7; val_offset:12*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x11, x3, x4, x5, dyn, 0, 0, x7, 12*FLEN/8, x12, x2, x6) + +inst_30: +// rs1==x1, rs2==x11, rs3==x21, rd==x22,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a7 and fs2 == 0 and fe2 == 0x17 and fm2 == 0x1d7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x1; op2:x11; op3:x21; dest:x22; op1val:0x7ba7; op2val:0x5dd7; +op3val:0x7bff; valaddr_reg:x7; val_offset:15*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x22, x1, x11, x21, dyn, 0, 0, x7, 15*FLEN/8, x12, x2, x6) + +inst_31: +// rs1==x23, rs2==x9, rs3==x28, rd==x8,fs1 == 0 and fe1 == 0x1e and fm1 == 0x28f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x316 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x23; op2:x9; op3:x28; dest:x8; op1val:0x7a8f; op2val:0x7b16; +op3val:0x7bff; valaddr_reg:x7; val_offset:18*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x8, x23, x9, x28, dyn, 0, 0, x7, 18*FLEN/8, x12, x2, x6) + +inst_32: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x278 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x025 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a78; op2val:0x7825; +op3val:0x7bff; valaddr_reg:x7; val_offset:21*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 21*FLEN/8, x12, x2, x6) + +inst_33: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2d0 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x32e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76d0; op2val:0x6b2e; +op3val:0x7bff; valaddr_reg:x7; val_offset:24*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 24*FLEN/8, x12, x2, x6) + +inst_34: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x08e and fs2 == 0 and fe2 == 0x1c and fm2 == 0x264 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x788e; op2val:0x7264; +op3val:0x7bff; valaddr_reg:x7; val_offset:27*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 27*FLEN/8, x12, x2, x6) + +inst_35: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3c1 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1b4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77c1; op2val:0x75b4; +op3val:0x7bff; valaddr_reg:x7; val_offset:30*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 30*FLEN/8, x12, x2, x6) + +inst_36: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0fc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x784e; op2val:0x78fc; +op3val:0x7bff; valaddr_reg:x7; val_offset:33*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 33*FLEN/8, x12, x2, x6) + +inst_37: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x353 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x328 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7753; op2val:0x6728; +op3val:0x7bff; valaddr_reg:x7; val_offset:36*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 36*FLEN/8, x12, x2, x6) + +inst_38: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1ab and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0ac and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71ab; op2val:0x78ac; +op3val:0x7bff; valaddr_reg:x7; val_offset:39*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 39*FLEN/8, x12, x2, x6) + +inst_39: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x262 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x25f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a62; op2val:0x7a5f; +op3val:0x7bff; valaddr_reg:x7; val_offset:42*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 42*FLEN/8, x12, x2, x6) + +inst_40: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x015 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2bb and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7415; op2val:0x7abb; +op3val:0x7bff; valaddr_reg:x7; val_offset:45*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 45*FLEN/8, x12, x2, x6) + +inst_41: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x153 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x045 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d53; op2val:0x6445; +op3val:0x7bff; valaddr_reg:x7; val_offset:48*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 48*FLEN/8, x12, x2, x6) + +inst_42: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20a and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3fb and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a0a; op2val:0x73fb; +op3val:0x7bff; valaddr_reg:x7; val_offset:51*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 51*FLEN/8, x12, x2, x6) + +inst_43: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fe and fs2 == 0 and fe2 == 0x1d and fm2 == 0x182 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fe; op2val:0x7582; +op3val:0x7bff; valaddr_reg:x7; val_offset:54*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 54*FLEN/8, x12, x2, x6) + +inst_44: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x11b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x037 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x711b; op2val:0x7837; +op3val:0x7bff; valaddr_reg:x7; val_offset:57*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 57*FLEN/8, x12, x2, x6) + +inst_45: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x05d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1b0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x745d; op2val:0x79b0; +op3val:0x7bff; valaddr_reg:x7; val_offset:60*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 60*FLEN/8, x12, x2, x6) + +inst_46: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x126 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x393 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7526; op2val:0x7793; +op3val:0x7bff; valaddr_reg:x7; val_offset:63*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 63*FLEN/8, x12, x2, x6) + +inst_47: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x22e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2bb and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x762e; op2val:0x76bb; +op3val:0x7bff; valaddr_reg:x7; val_offset:66*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 66*FLEN/8, x12, x2, x6) + +inst_48: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2f5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x331 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ef5; op2val:0x7b31; +op3val:0x7bff; valaddr_reg:x7; val_offset:69*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 69*FLEN/8, x12, x2, x6) + +inst_49: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0d7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72b0; op2val:0x78d7; +op3val:0x7bff; valaddr_reg:x7; val_offset:72*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 72*FLEN/8, x12, x2, x6) + +inst_50: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x153 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x092 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6553; op2val:0x6492; +op3val:0x7bff; valaddr_reg:x7; val_offset:75*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 75*FLEN/8, x12, x2, x6) + +inst_51: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1bf and fs2 == 0 and fe2 == 0x1c and fm2 == 0x11f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79bf; op2val:0x711f; +op3val:0x7bff; valaddr_reg:x7; val_offset:78*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 78*FLEN/8, x12, x2, x6) + +inst_52: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x16c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x05b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x796c; op2val:0x785b; +op3val:0x7bff; valaddr_reg:x7; val_offset:81*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 81*FLEN/8, x12, x2, x6) + +inst_53: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3cd and fs2 == 0 and fe2 == 0x1e and fm2 == 0x261 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bcd; op2val:0x7a61; +op3val:0x7bff; valaddr_reg:x7; val_offset:84*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 84*FLEN/8, x12, x2, x6) + +inst_54: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x323 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x12f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7323; op2val:0x792f; +op3val:0x7bff; valaddr_reg:x7; val_offset:87*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 87*FLEN/8, x12, x2, x6) + +inst_55: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09a and fs2 == 0 and fe2 == 0x1d and fm2 == 0x123 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x789a; op2val:0x7523; +op3val:0x7bff; valaddr_reg:x7; val_offset:90*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 90*FLEN/8, x12, x2, x6) + +inst_56: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x385 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0c6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6b85; op2val:0x74c6; +op3val:0x7bff; valaddr_reg:x7; val_offset:93*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 93*FLEN/8, x12, x2, x6) + +inst_57: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x300 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0e6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b00; op2val:0x74e6; +op3val:0x7bff; valaddr_reg:x7; val_offset:96*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 96*FLEN/8, x12, x2, x6) + +inst_58: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x382 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74f6; op2val:0x7b82; +op3val:0x7bff; valaddr_reg:x7; val_offset:99*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 99*FLEN/8, x12, x2, x6) + +inst_59: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a7 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x009 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76a7; op2val:0x7409; +op3val:0x7bff; valaddr_reg:x7; val_offset:102*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 102*FLEN/8, x12, x2, x6) + +inst_60: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x306 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x0d9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b06; op2val:0x68d9; +op3val:0x7bff; valaddr_reg:x7; val_offset:105*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 105*FLEN/8, x12, x2, x6) + +inst_61: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x08f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bb1; op2val:0x788f; +op3val:0x7bff; valaddr_reg:x7; val_offset:108*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 108*FLEN/8, x12, x2, x6) + +inst_62: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3c9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7af0; op2val:0x7bc9; +op3val:0x7bff; valaddr_reg:x7; val_offset:111*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 111*FLEN/8, x12, x2, x6) + +inst_63: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x011 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x20b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7811; op2val:0x760b; +op3val:0x7bff; valaddr_reg:x7; val_offset:114*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 114*FLEN/8, x12, x2, x6) + +inst_64: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x294 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x163 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7294; op2val:0x7963; +op3val:0x7bff; valaddr_reg:x7; val_offset:117*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 117*FLEN/8, x12, x2, x6) + +inst_65: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x235 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2ae and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7235; op2val:0x6eae; +op3val:0x7bff; valaddr_reg:x7; val_offset:120*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 120*FLEN/8, x12, x2, x6) + +inst_66: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0bc and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74bc; op2val:0x77fe; +op3val:0x7bff; valaddr_reg:x7; val_offset:123*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 123*FLEN/8, x12, x2, x6) + +inst_67: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x331 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7af8; op2val:0x7b31; +op3val:0x7bff; valaddr_reg:x7; val_offset:126*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 126*FLEN/8, x12, x2, x6) + +inst_68: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x26c and fs2 == 0 and fe2 == 0x1d and fm2 == 0x13d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x726c; op2val:0x753d; +op3val:0x7bff; valaddr_reg:x7; val_offset:129*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 129*FLEN/8, x12, x2, x6) + +inst_69: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x242 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x16c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a42; op2val:0x756c; +op3val:0x7bff; valaddr_reg:x7; val_offset:132*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 132*FLEN/8, x12, x2, x6) + +inst_70: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x164 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7964; op2val:0x7ab2; +op3val:0x7bff; valaddr_reg:x7; val_offset:135*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 135*FLEN/8, x12, x2, x6) + +inst_71: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x17f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x30e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x757f; op2val:0x7b0e; +op3val:0x7bff; valaddr_reg:x7; val_offset:138*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 138*FLEN/8, x12, x2, x6) + +inst_72: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3bf and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77bf; op2val:0x7be1; +op3val:0x7bff; valaddr_reg:x7; val_offset:141*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 141*FLEN/8, x12, x2, x6) + +inst_73: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1cd and fs2 == 0 and fe2 == 0x1b and fm2 == 0x16a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79cd; op2val:0x6d6a; +op3val:0x7bff; valaddr_reg:x7; val_offset:144*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 144*FLEN/8, x12, x2, x6) + +inst_74: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x348 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2cf and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b48; op2val:0x72cf; +op3val:0x7bff; valaddr_reg:x7; val_offset:147*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 147*FLEN/8, x12, x2, x6) + +inst_75: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0cc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78cc; op2val:0x7ab9; +op3val:0x7bff; valaddr_reg:x7; val_offset:150*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 150*FLEN/8, x12, x2, x6) + +inst_76: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x171 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0a8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7571; op2val:0x74a8; +op3val:0x7bff; valaddr_reg:x7; val_offset:153*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 153*FLEN/8, x12, x2, x6) + +inst_77: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3a1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78d4; op2val:0x7ba1; +op3val:0x7bff; valaddr_reg:x7; val_offset:156*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 156*FLEN/8, x12, x2, x6) + +inst_78: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x054 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x068 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7054; op2val:0x7868; +op3val:0x7bff; valaddr_reg:x7; val_offset:159*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 159*FLEN/8, x12, x2, x6) + +inst_79: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x101 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0ae and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6901; op2val:0x6cae; +op3val:0x7bff; valaddr_reg:x7; val_offset:162*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 162*FLEN/8, x12, x2, x6) + +inst_80: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x24d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x29f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a4d; op2val:0x7a9f; +op3val:0x7bff; valaddr_reg:x7; val_offset:165*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 165*FLEN/8, x12, x2, x6) + +inst_81: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0eb and fs2 == 0 and fe2 == 0x1e and fm2 == 0x240 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78eb; op2val:0x7a40; +op3val:0x7bff; valaddr_reg:x7; val_offset:168*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 168*FLEN/8, x12, x2, x6) + +inst_82: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x090 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x327 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7890; op2val:0x7327; +op3val:0x7bff; valaddr_reg:x7; val_offset:171*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 171*FLEN/8, x12, x2, x6) + +inst_83: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x043 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x31f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7443; op2val:0x7b1f; +op3val:0x7bff; valaddr_reg:x7; val_offset:174*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 174*FLEN/8, x12, x2, x6) + +inst_84: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x365 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x352 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b65; op2val:0x7752; +op3val:0x7bff; valaddr_reg:x7; val_offset:177*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 177*FLEN/8, x12, x2, x6) + +inst_85: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x24b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x29e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a4b; op2val:0x7a9e; +op3val:0x7bff; valaddr_reg:x7; val_offset:180*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 180*FLEN/8, x12, x2, x6) + +inst_86: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15c and fs2 == 0 and fe2 == 0x1b and fm2 == 0x1dd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x795c; op2val:0x6ddd; +op3val:0x7bff; valaddr_reg:x7; val_offset:183*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 183*FLEN/8, x12, x2, x6) + +inst_87: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x313 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x11e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b13; op2val:0x691e; +op3val:0x7bff; valaddr_reg:x7; val_offset:186*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 186*FLEN/8, x12, x2, x6) + +inst_88: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e6 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2bb and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7be6; op2val:0x76bb; +op3val:0x7bff; valaddr_reg:x7; val_offset:189*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 189*FLEN/8, x12, x2, x6) + +inst_89: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x15a and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3b8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x715a; op2val:0x73b8; +op3val:0x7bff; valaddr_reg:x7; val_offset:192*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 192*FLEN/8, x12, x2, x6) + +inst_90: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x294 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x348 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e94; op2val:0x7b48; +op3val:0x7bff; valaddr_reg:x7; val_offset:195*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 195*FLEN/8, x12, x2, x6) + +inst_91: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x345 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bc2; op2val:0x7b45; +op3val:0x7bff; valaddr_reg:x7; val_offset:198*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 198*FLEN/8, x12, x2, x6) + +inst_92: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x00d and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3a0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x740d; op2val:0x77a0; +op3val:0x7bff; valaddr_reg:x7; val_offset:201*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 201*FLEN/8, x12, x2, x6) + +inst_93: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x136 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x111 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7936; op2val:0x6911; +op3val:0x7bff; valaddr_reg:x7; val_offset:204*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 204*FLEN/8, x12, x2, x6) + +inst_94: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3db and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0b9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bdb; op2val:0x74b9; +op3val:0x7bff; valaddr_reg:x7; val_offset:207*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 207*FLEN/8, x12, x2, x6) + +inst_95: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x331 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x102 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7731; op2val:0x7502; +op3val:0x7bff; valaddr_reg:x7; val_offset:210*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 210*FLEN/8, x12, x2, x6) + +inst_96: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x34d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3c1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b4d; op2val:0x7bc1; +op3val:0x7bff; valaddr_reg:x7; val_offset:213*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 213*FLEN/8, x12, x2, x6) + +inst_97: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x31f and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2e2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f1f; op2val:0x72e2; +op3val:0x7bff; valaddr_reg:x7; val_offset:216*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 216*FLEN/8, x12, x2, x6) + +inst_98: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x057 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd5; op2val:0x7857; +op3val:0x7bff; valaddr_reg:x7; val_offset:219*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 219*FLEN/8, x12, x2, x6) + +inst_99: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x14a and fs2 == 0 and fe2 == 0x1d and fm2 == 0x024 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x794a; op2val:0x7424; +op3val:0x7bff; valaddr_reg:x7; val_offset:222*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 222*FLEN/8, x12, x2, x6) + +inst_100: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ea and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74ea; op2val:0x73e1; +op3val:0x7bff; valaddr_reg:x7; val_offset:225*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 225*FLEN/8, x12, x2, x6) + +inst_101: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x07d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3dc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x747d; op2val:0x7bdc; +op3val:0x7bff; valaddr_reg:x7; val_offset:228*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 228*FLEN/8, x12, x2, x6) + +inst_102: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x136 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x125 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7936; op2val:0x7925; +op3val:0x7bff; valaddr_reg:x7; val_offset:231*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 231*FLEN/8, x12, x2, x6) + +inst_103: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x23e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0e7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x763e; op2val:0x74e7; +op3val:0x7bff; valaddr_reg:x7; val_offset:234*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 234*FLEN/8, x12, x2, x6) + +inst_104: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x110 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7510; op2val:0x7ac6; +op3val:0x7bff; valaddr_reg:x7; val_offset:237*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 237*FLEN/8, x12, x2, x6) + +inst_105: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d7 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x158 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74d7; op2val:0x7558; +op3val:0x7bff; valaddr_reg:x7; val_offset:240*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 240*FLEN/8, x12, x2, x6) + +inst_106: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0c3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78a1; op2val:0x78c3; +op3val:0x7bff; valaddr_reg:x7; val_offset:243*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 243*FLEN/8, x12, x2, x6) + +inst_107: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x136 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3cb and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6536; op2val:0x73cb; +op3val:0x7bff; valaddr_reg:x7; val_offset:246*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 246*FLEN/8, x12, x2, x6) + +inst_108: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x068 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x089 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7868; op2val:0x6c89; +op3val:0x7bff; valaddr_reg:x7; val_offset:249*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 249*FLEN/8, x12, x2, x6) + +inst_109: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x114 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0a6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7914; op2val:0x74a6; +op3val:0x7bff; valaddr_reg:x7; val_offset:252*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 252*FLEN/8, x12, x2, x6) + +inst_110: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3e3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2e5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77e3; op2val:0x7ae5; +op3val:0x7bff; valaddr_reg:x7; val_offset:255*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 255*FLEN/8, x12, x2, x6) + +inst_111: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x25b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7802; op2val:0x7a5b; +op3val:0x7bff; valaddr_reg:x7; val_offset:258*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 258*FLEN/8, x12, x2, x6) + +inst_112: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x397 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x18a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b97; op2val:0x718a; +op3val:0x7bff; valaddr_reg:x7; val_offset:261*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 261*FLEN/8, x12, x2, x6) + +inst_113: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x291 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7be0; op2val:0x7a91; +op3val:0x7bff; valaddr_reg:x7; val_offset:264*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 264*FLEN/8, x12, x2, x6) + +inst_114: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2d6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x01c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ed6; op2val:0x781c; +op3val:0x7bff; valaddr_reg:x7; val_offset:267*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 267*FLEN/8, x12, x2, x6) + +inst_115: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0b1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x325 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74b1; op2val:0x7b25; +op3val:0x7bff; valaddr_reg:x7; val_offset:270*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 270*FLEN/8, x12, x2, x6) + +inst_116: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x347 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x010 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b47; op2val:0x6810; +op3val:0x7bff; valaddr_reg:x7; val_offset:273*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 273*FLEN/8, x12, x2, x6) + +inst_117: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x338 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x26d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b38; op2val:0x7a6d; +op3val:0x7bff; valaddr_reg:x7; val_offset:276*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 276*FLEN/8, x12, x2, x6) + +inst_118: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1f7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ab8; op2val:0x79f7; +op3val:0x7bff; valaddr_reg:x7; val_offset:279*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 279*FLEN/8, x12, x2, x6) + +inst_119: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1b2 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2eb and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71b2; op2val:0x76eb; +op3val:0x7bff; valaddr_reg:x7; val_offset:282*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 282*FLEN/8, x12, x2, x6) + +inst_120: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x156 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79b7; op2val:0x7956; +op3val:0x7bff; valaddr_reg:x7; val_offset:285*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 285*FLEN/8, x12, x2, x6) + +inst_121: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x01e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3b4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c1e; op2val:0x7bb4; +op3val:0x7bff; valaddr_reg:x7; val_offset:288*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 288*FLEN/8, x12, x2, x6) + +inst_122: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x064 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x054 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7864; op2val:0x7854; +op3val:0x7bff; valaddr_reg:x7; val_offset:291*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 291*FLEN/8, x12, x2, x6) + +inst_123: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x33f and fs2 == 0 and fe2 == 0x1d and fm2 == 0x254 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x773f; op2val:0x7654; +op3val:0x7bff; valaddr_reg:x7; val_offset:294*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 294*FLEN/8, x12, x2, x6) + +inst_124: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x020 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x23e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7420; op2val:0x663e; +op3val:0x7bff; valaddr_reg:x7; val_offset:297*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 297*FLEN/8, x12, x2, x6) + +inst_125: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x090 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76a9; op2val:0x7890; +op3val:0x7bff; valaddr_reg:x7; val_offset:300*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 300*FLEN/8, x12, x2, x6) + +inst_126: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ad and fs2 == 0 and fe2 == 0x1c and fm2 == 0x06c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75ad; op2val:0x706c; +op3val:0x7bff; valaddr_reg:x7; val_offset:303*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 303*FLEN/8, x12, x2, x6) + +inst_127: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x024 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2a0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7424; op2val:0x7aa0; +op3val:0x7bff; valaddr_reg:x7; val_offset:306*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 306*FLEN/8, x12, x2, x6) + +inst_128: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0e5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x766a; op2val:0x78e5; +op3val:0x7bff; valaddr_reg:x7; val_offset:309*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 309*FLEN/8, x12, x2, x6) + +inst_129: +// fs1 == 0 and fe1 == 0x17 and fm1 == 0x3a7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x03a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5fa7; op2val:0x783a; +op3val:0x7bff; valaddr_reg:x7; val_offset:312*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 312*FLEN/8, x12, x2, x6) + +inst_130: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x130 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x302 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7930; op2val:0x7702; +op3val:0x7bff; valaddr_reg:x7; val_offset:315*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 315*FLEN/8, x12, x2, x6) + +inst_131: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d9 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79d9; op2val:0x739f; +op3val:0x7bff; valaddr_reg:x7; val_offset:318*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 318*FLEN/8, x12, x2, x6) + +inst_132: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a8 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x332 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77a8; op2val:0x7332; +op3val:0x7bff; valaddr_reg:x7; val_offset:321*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 321*FLEN/8, x12, x2, x6) + +inst_133: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x07b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x340 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x787b; op2val:0x7b40; +op3val:0x7bff; valaddr_reg:x7; val_offset:324*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 324*FLEN/8, x12, x2, x6) + +inst_134: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x066 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x12b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7466; op2val:0x792b; +op3val:0x7bff; valaddr_reg:x7; val_offset:327*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 327*FLEN/8, x12, x2, x6) + +inst_135: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x093 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x017 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c93; op2val:0x7817; +op3val:0x7bff; valaddr_reg:x7; val_offset:330*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 330*FLEN/8, x12, x2, x6) + +inst_136: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x119 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x220 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7119; op2val:0x7a20; +op3val:0x7bff; valaddr_reg:x7; val_offset:333*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 333*FLEN/8, x12, x2, x6) + +inst_137: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0fc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x189 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74fc; op2val:0x7989; +op3val:0x7bff; valaddr_reg:x7; val_offset:336*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 336*FLEN/8, x12, x2, x6) + +inst_138: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1f1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x19b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75f1; op2val:0x799b; +op3val:0x7bff; valaddr_reg:x7; val_offset:339*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 339*FLEN/8, x12, x2, x6) + +inst_139: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2d8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78c1; op2val:0x7ad8; +op3val:0x7bff; valaddr_reg:x7; val_offset:342*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 342*FLEN/8, x12, x2, x6) + +inst_140: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ad and fs2 == 0 and fe2 == 0x1e and fm2 == 0x091 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bad; op2val:0x7891; +op3val:0x7bff; valaddr_reg:x7; val_offset:345*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 345*FLEN/8, x12, x2, x6) + +inst_141: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2f5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7401; op2val:0x72f5; +op3val:0x7bff; valaddr_reg:x7; val_offset:348*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 348*FLEN/8, x12, x2, x6) + +inst_142: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20f and fs2 == 0 and fe2 == 0x1a and fm2 == 0x2ab and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a0f; op2val:0x6aab; +op3val:0x7bff; valaddr_reg:x7; val_offset:351*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 351*FLEN/8, x12, x2, x6) + +inst_143: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1bc and fs2 == 0 and fe2 == 0x1d and fm2 == 0x190 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79bc; op2val:0x7590; +op3val:0x7bff; valaddr_reg:x7; val_offset:354*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 354*FLEN/8, x12, x2, x6) + +inst_144: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x145 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1d6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7145; op2val:0x79d6; +op3val:0x7bff; valaddr_reg:x7; val_offset:357*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 357*FLEN/8, x12, x2, x6) + +inst_145: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x275 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd8; op2val:0x7a75; +op3val:0x7bff; valaddr_reg:x7; val_offset:360*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 360*FLEN/8, x12, x2, x6) + +inst_146: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x047 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x34c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7447; op2val:0x7b4c; +op3val:0x7bff; valaddr_reg:x7; val_offset:363*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 363*FLEN/8, x12, x2, x6) + +inst_147: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x073 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x233 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7073; op2val:0x7a33; +op3val:0x7bff; valaddr_reg:x7; val_offset:366*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 366*FLEN/8, x12, x2, x6) + +inst_148: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x146 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x199 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7946; op2val:0x7999; +op3val:0x7bff; valaddr_reg:x7; val_offset:369*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 369*FLEN/8, x12, x2, x6) + +inst_149: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x364 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3c4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b64; op2val:0x7bc4; +op3val:0x7bff; valaddr_reg:x7; val_offset:372*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 372*FLEN/8, x12, x2, x6) + +inst_150: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26b and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2ec and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a6b; op2val:0x76ec; +op3val:0x7bff; valaddr_reg:x7; val_offset:375*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 375*FLEN/8, x12, x2, x6) + +inst_151: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x134 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x00a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7534; op2val:0x700a; +op3val:0x7bff; valaddr_reg:x7; val_offset:378*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 378*FLEN/8, x12, x2, x6) + +inst_152: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ab and fs2 == 0 and fe2 == 0x1b and fm2 == 0x39f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bab; op2val:0x6f9f; +op3val:0x7bff; valaddr_reg:x7; val_offset:381*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 381*FLEN/8, x12, x2, x6) + +inst_153: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x287 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x38d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7687; op2val:0x6f8d; +op3val:0x7bff; valaddr_reg:x7; val_offset:384*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 384*FLEN/8, x12, x2, x6) + +inst_154: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73f0; op2val:0x79fe; +op3val:0x7bff; valaddr_reg:x7; val_offset:387*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 387*FLEN/8, x12, x2, x6) + +inst_155: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x212 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x304 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7212; op2val:0x7704; +op3val:0x7bff; valaddr_reg:x7; val_offset:390*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 390*FLEN/8, x12, x2, x6) + +inst_156: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x104 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0d7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7904; op2val:0x78d7; +op3val:0x7bff; valaddr_reg:x7; val_offset:393*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 393*FLEN/8, x12, x2, x6) +RVTEST_SIGBASE(x2,signature_x2_3) + +inst_157: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x29b and fs2 == 0 and fe2 == 0x1d and fm2 == 0x08d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x729b; op2val:0x748d; +op3val:0x7bff; valaddr_reg:x7; val_offset:396*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 396*FLEN/8, x12, x2, x6) + +inst_158: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x05e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0af and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x745e; op2val:0x78af; +op3val:0x7bff; valaddr_reg:x7; val_offset:399*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 399*FLEN/8, x12, x2, x6) + +inst_159: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x177 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x253 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7977; op2val:0x7a53; +op3val:0x7bff; valaddr_reg:x7; val_offset:402*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 402*FLEN/8, x12, x2, x6) + +inst_160: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x05c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bc8; op2val:0x785c; +op3val:0x7bff; valaddr_reg:x7; val_offset:405*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 405*FLEN/8, x12, x2, x6) + +inst_161: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x226 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ad7; op2val:0x7a26; +op3val:0x7bff; valaddr_reg:x7; val_offset:408*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 408*FLEN/8, x12, x2, x6) + +inst_162: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x221 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x08a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7621; op2val:0x748a; +op3val:0x7bff; valaddr_reg:x7; val_offset:411*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 411*FLEN/8, x12, x2, x6) + +inst_163: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x275 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x38d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a75; op2val:0x6f8d; +op3val:0x7bff; valaddr_reg:x7; val_offset:414*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 414*FLEN/8, x12, x2, x6) + +inst_164: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x05c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3b7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x785c; op2val:0x7bb7; +op3val:0x7bff; valaddr_reg:x7; val_offset:417*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 417*FLEN/8, x12, x2, x6) + +inst_165: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c8 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x05e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bc8; op2val:0x705e; +op3val:0x7bff; valaddr_reg:x7; val_offset:420*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 420*FLEN/8, x12, x2, x6) + +inst_166: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x094 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0fa and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7894; op2val:0x74fa; +op3val:0x7bff; valaddr_reg:x7; val_offset:423*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 423*FLEN/8, x12, x2, x6) + +inst_167: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1b4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x039 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75b4; op2val:0x7839; +op3val:0x7bff; valaddr_reg:x7; val_offset:426*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 426*FLEN/8, x12, x2, x6) + +inst_168: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x312 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x330 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7712; op2val:0x7730; +op3val:0x7bff; valaddr_reg:x7; val_offset:429*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 429*FLEN/8, x12, x2, x6) + +inst_169: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x263 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x242 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7663; op2val:0x7a42; +op3val:0x7bff; valaddr_reg:x7; val_offset:432*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 432*FLEN/8, x12, x2, x6) + +inst_170: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3df and fs2 == 0 and fe2 == 0x1e and fm2 == 0x12d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77df; op2val:0x792d; +op3val:0x7bff; valaddr_reg:x7; val_offset:435*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 435*FLEN/8, x12, x2, x6) + +inst_171: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x285 and fs2 == 0 and fe2 == 0x16 and fm2 == 0x3ee and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7285; op2val:0x5bee; +op3val:0x7bff; valaddr_reg:x7; val_offset:438*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 438*FLEN/8, x12, x2, x6) + +inst_172: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x30c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78c8; op2val:0x7b0c; +op3val:0x7bff; valaddr_reg:x7; val_offset:441*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 441*FLEN/8, x12, x2, x6) + +inst_173: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x015 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3e4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7815; op2val:0x7be4; +op3val:0x7bff; valaddr_reg:x7; val_offset:444*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 444*FLEN/8, x12, x2, x6) + +inst_174: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ac and fs2 == 0 and fe2 == 0x1d and fm2 == 0x28a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aac; op2val:0x768a; +op3val:0x7bff; valaddr_reg:x7; val_offset:447*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 447*FLEN/8, x12, x2, x6) + +inst_175: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e5 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0e2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7be5; op2val:0x74e2; +op3val:0x7bff; valaddr_reg:x7; val_offset:450*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 450*FLEN/8, x12, x2, x6) + +inst_176: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0f5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x03e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78f5; op2val:0x783e; +op3val:0x7bff; valaddr_reg:x7; val_offset:453*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 453*FLEN/8, x12, x2, x6) + +inst_177: +// fs1 == 0 and fe1 == 0x16 and fm1 == 0x334 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x239 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5b34; op2val:0x7639; +op3val:0x7bff; valaddr_reg:x7; val_offset:456*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 456*FLEN/8, x12, x2, x6) + +inst_178: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x27b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2e2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x767b; op2val:0x7ae2; +op3val:0x7bff; valaddr_reg:x7; val_offset:459*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 459*FLEN/8, x12, x2, x6) + +inst_179: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1de and fs2 == 0 and fe2 == 0x1e and fm2 == 0x32e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79de; op2val:0x7b2e; +op3val:0x7bff; valaddr_reg:x7; val_offset:462*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 462*FLEN/8, x12, x2, x6) + +inst_180: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3e1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1f6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77e1; op2val:0x79f6; +op3val:0x7bff; valaddr_reg:x7; val_offset:465*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 465*FLEN/8, x12, x2, x6) + +inst_181: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x108 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x792f; op2val:0x7908; +op3val:0x7bff; valaddr_reg:x7; val_offset:468*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 468*FLEN/8, x12, x2, x6) + +inst_182: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x108 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x111 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7908; op2val:0x7911; +op3val:0x7bff; valaddr_reg:x7; val_offset:471*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 471*FLEN/8, x12, x2, x6) + +inst_183: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x241 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a41; op2val:0x7ac4; +op3val:0x7bff; valaddr_reg:x7; val_offset:474*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 474*FLEN/8, x12, x2, x6) + +inst_184: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x284 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0d7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a84; op2val:0x78d7; +op3val:0x7bff; valaddr_reg:x7; val_offset:477*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 477*FLEN/8, x12, x2, x6) + +inst_185: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x03b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1a9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x743b; op2val:0x79a9; +op3val:0x7bff; valaddr_reg:x7; val_offset:480*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 480*FLEN/8, x12, x2, x6) + +inst_186: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x05a and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0dd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x785a; op2val:0x70dd; +op3val:0x7bff; valaddr_reg:x7; val_offset:483*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 483*FLEN/8, x12, x2, x6) + +inst_187: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3bf and fs2 == 0 and fe2 == 0x1d and fm2 == 0x378 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77bf; op2val:0x7778; +op3val:0x7bff; valaddr_reg:x7; val_offset:486*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 486*FLEN/8, x12, x2, x6) + +inst_188: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x014 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1f4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7814; op2val:0x79f4; +op3val:0x7bff; valaddr_reg:x7; val_offset:489*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 489*FLEN/8, x12, x2, x6) + +inst_189: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ae and fs2 == 0 and fe2 == 0x1e and fm2 == 0x140 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75ae; op2val:0x7940; +op3val:0x7bff; valaddr_reg:x7; val_offset:492*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 492*FLEN/8, x12, x2, x6) + +inst_190: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x390 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x780e; op2val:0x7b90; +op3val:0x7bff; valaddr_reg:x7; val_offset:495*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 495*FLEN/8, x12, x2, x6) + +inst_191: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x182 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x766d; op2val:0x7982; +op3val:0x7bff; valaddr_reg:x7; val_offset:498*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 498*FLEN/8, x12, x2, x6) + +inst_192: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2a4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72ae; op2val:0x72a4; +op3val:0x7bff; valaddr_reg:x7; val_offset:501*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 501*FLEN/8, x12, x2, x6) + +inst_193: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x04d and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0ca and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x744d; op2val:0x6cca; +op3val:0x7bff; valaddr_reg:x7; val_offset:504*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 504*FLEN/8, x12, x2, x6) + +inst_194: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1e3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x782e; op2val:0x75e3; +op3val:0x7bff; valaddr_reg:x7; val_offset:507*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 507*FLEN/8, x12, x2, x6) + +inst_195: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1e4 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x164 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79e4; op2val:0x7164; +op3val:0x7bff; valaddr_reg:x7; val_offset:510*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 510*FLEN/8, x12, x2, x6) + +inst_196: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x284 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79b4; op2val:0x7a84; +op3val:0x7bff; valaddr_reg:x7; val_offset:513*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 513*FLEN/8, x12, x2, x6) + +inst_197: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0df and fs2 == 0 and fe2 == 0x1c and fm2 == 0x36c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78df; op2val:0x736c; +op3val:0x7bff; valaddr_reg:x7; val_offset:516*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 516*FLEN/8, x12, x2, x6) + +inst_198: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x183 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x250 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7183; op2val:0x7a50; +op3val:0x7bff; valaddr_reg:x7; val_offset:519*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 519*FLEN/8, x12, x2, x6) + +inst_199: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x145 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x31c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7545; op2val:0x731c; +op3val:0x7bff; valaddr_reg:x7; val_offset:522*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 522*FLEN/8, x12, x2, x6) + +inst_200: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x704c; op2val:0x7ac6; +op3val:0x7bff; valaddr_reg:x7; val_offset:525*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 525*FLEN/8, x12, x2, x6) + +inst_201: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x135 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x24e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7935; op2val:0x7a4e; +op3val:0x7bff; valaddr_reg:x7; val_offset:528*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 528*FLEN/8, x12, x2, x6) + +inst_202: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x340 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ae and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6740; op2val:0x7aae; +op3val:0x7bff; valaddr_reg:x7; val_offset:531*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 531*FLEN/8, x12, x2, x6) + +inst_203: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x218 and fs2 == 0 and fe2 == 0x16 and fm2 == 0x04f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a18; op2val:0x584f; +op3val:0x7bff; valaddr_reg:x7; val_offset:534*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 534*FLEN/8, x12, x2, x6) + +inst_204: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x054 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x382 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7854; op2val:0x7b82; +op3val:0x7bff; valaddr_reg:x7; val_offset:537*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 537*FLEN/8, x12, x2, x6) + +inst_205: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ed and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2c0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72ed; op2val:0x76c0; +op3val:0x7bff; valaddr_reg:x7; val_offset:540*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 540*FLEN/8, x12, x2, x6) + +inst_206: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x317 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x300 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7317; op2val:0x7700; +op3val:0x7bff; valaddr_reg:x7; val_offset:543*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 543*FLEN/8, x12, x2, x6) + +inst_207: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x374 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x362 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7374; op2val:0x7362; +op3val:0x7bff; valaddr_reg:x7; val_offset:546*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 546*FLEN/8, x12, x2, x6) + +inst_208: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x359 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0a2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7759; op2val:0x74a2; +op3val:0x7bff; valaddr_reg:x7; val_offset:549*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 549*FLEN/8, x12, x2, x6) + +inst_209: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1f2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ef and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71f2; op2val:0x7bef; +op3val:0x7bff; valaddr_reg:x7; val_offset:552*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 552*FLEN/8, x12, x2, x6) + +inst_210: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x249 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3d4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7649; op2val:0x77d4; +op3val:0x7bff; valaddr_reg:x7; val_offset:555*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 555*FLEN/8, x12, x2, x6) + +inst_211: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0be and fs2 == 0 and fe2 == 0x1d and fm2 == 0x24b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78be; op2val:0x764b; +op3val:0x7bff; valaddr_reg:x7; val_offset:558*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 558*FLEN/8, x12, x2, x6) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(28748,32,FLEN) +NAN_BOXED(28748,32,FLEN) +NAN_BOXED(28748,32,FLEN) +NAN_BOXED(29716,32,FLEN) +NAN_BOXED(30700,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(31029,32,FLEN) +NAN_BOXED(31029,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(26432,32,FLEN) +NAN_BOXED(31406,32,FLEN) +NAN_BOXED(31406,32,FLEN) +NAN_BOXED(31256,32,FLEN) +NAN_BOXED(31256,32,FLEN) +NAN_BOXED(31256,32,FLEN) +NAN_BOXED(31172,32,FLEN) +NAN_BOXED(29521,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(31541,32,FLEN) +NAN_BOXED(26579,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(30804,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(29421,32,FLEN) +NAN_BOXED(30400,32,FLEN) +NAN_BOXED(30400,32,FLEN) +NAN_BOXED(29463,32,FLEN) +NAN_BOXED(29463,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(29556,32,FLEN) +NAN_BOXED(29538,32,FLEN) +NAN_BOXED(29556,32,FLEN) +NAN_BOXED(30553,32,FLEN) +NAN_BOXED(29858,32,FLEN) +NAN_BOXED(30553,32,FLEN) +test_dataset_1: +NAN_BOXED(31410,32,FLEN) +NAN_BOXED(30835,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31727,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(28603,32,FLEN) +NAN_BOXED(30034,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(31151,32,FLEN) +NAN_BOXED(31612,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(31395,32,FLEN) +NAN_BOXED(31068,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(30898,32,FLEN) +NAN_BOXED(31502,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(30730,32,FLEN) +NAN_BOXED(30901,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(29635,32,FLEN) +NAN_BOXED(31328,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(29064,32,FLEN) +NAN_BOXED(30819,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(31076,32,FLEN) +NAN_BOXED(30206,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(30736,32,FLEN) +NAN_BOXED(31289,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(30281,32,FLEN) +NAN_BOXED(30676,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(27024,32,FLEN) +NAN_BOXED(31135,32,FLEN) +NAN_BOXED(31743,32,FLEN) +test_dataset_2: +NAN_BOXED(30910,16,FLEN) +NAN_BOXED(30283,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(30724,16,FLEN) +NAN_BOXED(31706,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30800,16,FLEN) +NAN_BOXED(31457,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30747,16,FLEN) +NAN_BOXED(31645,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30551,16,FLEN) +NAN_BOXED(29774,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31655,16,FLEN) +NAN_BOXED(24023,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31375,16,FLEN) +NAN_BOXED(31510,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31352,16,FLEN) +NAN_BOXED(30757,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30416,16,FLEN) +NAN_BOXED(27438,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30862,16,FLEN) +NAN_BOXED(29284,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30657,16,FLEN) +NAN_BOXED(30132,16,FLEN) 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+NAN_BOXED(31430,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31029,16,FLEN) +NAN_BOXED(31310,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(26432,16,FLEN) +NAN_BOXED(31406,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31256,16,FLEN) +NAN_BOXED(22607,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30804,16,FLEN) +NAN_BOXED(31618,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29421,16,FLEN) +NAN_BOXED(30400,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29463,16,FLEN) +NAN_BOXED(30464,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29556,16,FLEN) +NAN_BOXED(29538,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30553,16,FLEN) +NAN_BOXED(29858,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29170,16,FLEN) +NAN_BOXED(31727,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30281,16,FLEN) +NAN_BOXED(30676,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30910,16,FLEN) +NAN_BOXED(30283,16,FLEN) +NAN_BOXED(31743,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x2_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_1: + .fill 30*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_0: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_2: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_3: + .fill 110*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fmsub_b17-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fmsub_b17-01.S new file mode 100644 index 000000000..2b7aaab19 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fmsub_b17-01.S @@ -0,0 +1,2209 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 05:33:17 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fmsub.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fmsub.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fmsub_b17 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fmsub_b17) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rs2 == rs3 != rd, rs1==x27, rs2==x27, rs3==x27, rd==x22,fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x27; op2:x27; op3:x27; dest:x22; op1val:0x704c; op2val:0x704c; +op3val:0x704c; valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x22, x27, x27, x27, dyn, 0, 0, x3, 0*FLEN/8, x15, x1, x2) + +inst_1: +// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==x23, rs2==x17, rs3==x5, rd==x20,fs1 == 0 and fe1 == 0x1d and fm1 == 0x014 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3ec and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x23; op2:x17; op3:x5; dest:x20; op1val:0x7414; op2val:0x77ec; +op3val:0x7bff; valaddr_reg:x3; val_offset:3*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x20, x23, x17, x5, dyn, 0, 0, x3, 3*FLEN/8, x15, x1, x2) + +inst_2: +// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==x20, rs2==x20, rs3==x12, rd==x17,fs1 == 0 and fe1 == 0x1e and fm1 == 0x135 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x24e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x20; op2:x20; op3:x12; dest:x17; op1val:0x7935; op2val:0x7935; +op3val:0x7bff; valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x17, x20, x20, x12, dyn, 0, 0, x3, 6*FLEN/8, x15, x1, x2) + +inst_3: +// rd == rs2 == rs3 != rs1, rs1==x17, rs2==x8, rs3==x8, rd==x8,fs1 == 0 and fe1 == 0x19 and fm1 == 0x340 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ae and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x17; op2:x8; op3:x8; dest:x8; op1val:0x6740; op2val:0x7aae; +op3val:0x7aae; valaddr_reg:x3; val_offset:9*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x8, x17, x8, x8, dyn, 0, 0, x3, 9*FLEN/8, x15, x1, x2) + +inst_4: +// rs1 == rs2 == rs3 == rd, rs1==x28, rs2==x28, rs3==x28, rd==x28,fs1 == 0 and fe1 == 0x1e and fm1 == 0x218 and fs2 == 0 and fe2 == 0x16 and fm2 == 0x04f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x28; op2:x28; op3:x28; dest:x28; op1val:0x7a18; op2val:0x7a18; +op3val:0x7a18; valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x28, x28, x28, x28, dyn, 0, 0, x3, 12*FLEN/8, x15, x1, x2) + +inst_5: +// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==x26, rs2==x12, rs3==x30, rd==x12,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c4 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x351 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x26; op2:x12; op3:x30; dest:x12; op1val:0x79c4; op2val:0x7351; +op3val:0x7bff; valaddr_reg:x3; val_offset:15*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x12, x26, x12, x30, dyn, 0, 0, x3, 15*FLEN/8, x15, x1, x2) + +inst_6: +// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==x19, rs2==x29, rs3==x24, rd==x24,fs1 == 0 and fe1 == 0x1e and fm1 == 0x335 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x3d3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x19; op2:x29; op3:x24; dest:x24; op1val:0x7b35; op2val:0x67d3; +op3val:0x7bff; valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x24, x19, x29, x24, dyn, 0, 0, x3, 18*FLEN/8, x15, x1, x2) + +inst_7: +// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==x9, rs2==x4, rs3==x11, rd==x9,fs1 == 0 and fe1 == 0x1e and fm1 == 0x054 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x382 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x9; op2:x4; op3:x11; dest:x9; op1val:0x7854; op2val:0x7b82; +op3val:0x7bff; valaddr_reg:x3; val_offset:21*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x9, x9, x4, x11, dyn, 0, 0, x3, 21*FLEN/8, x15, x1, x2) + +inst_8: +// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==x4, rs2==x16, rs3==x16, rd==x11,fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ed and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2c0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x4; op2:x16; op3:x16; dest:x11; op1val:0x72ed; op2val:0x76c0; +op3val:0x76c0; valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x11, x4, x16, x16, dyn, 0, 0, x3, 24*FLEN/8, x15, x1, x2) + +inst_9: +// rs1 == rs2 == rd != rs3, rs1==x0, rs2==x0, rs3==x25, rd==x0,fs1 == 0 and fe1 == 0x1c and fm1 == 0x317 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x300 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x0; op2:x0; op3:x25; dest:x0; op1val:0x0; op2val:0x0; +op3val:0x7bff; valaddr_reg:x3; val_offset:27*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x0, x0, x0, x25, dyn, 0, 0, x3, 27*FLEN/8, x15, x1, x2) + +inst_10: +// rs1 == rd == rs3 != rs2, rs1==x14, rs2==x7, rs3==x14, rd==x14,fs1 == 0 and fe1 == 0x1c and fm1 == 0x374 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x362 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x14; op2:x7; op3:x14; dest:x14; op1val:0x7374; op2val:0x7362; +op3val:0x7374; valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x14, x14, x7, x14, dyn, 0, 0, x3, 30*FLEN/8, x15, x1, x2) + +inst_11: +// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==x6, rs2==x11, rs3==x6, rd==x16,fs1 == 0 and fe1 == 0x1d and fm1 == 0x359 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0a2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x6; op2:x11; op3:x6; dest:x16; op1val:0x7759; op2val:0x74a2; +op3val:0x7759; valaddr_reg:x3; val_offset:33*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x16, x6, x11, x6, dyn, 0, 0, x3, 33*FLEN/8, x15, x1, x2) + +inst_12: +// rs1==x13, rs2==x10, rs3==x15, rd==x26,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x073 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x13; op2:x10; op3:x15; dest:x26; op1val:0x7ab2; op2val:0x7873; +op3val:0x7bff; valaddr_reg:x3; val_offset:36*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x26, x13, x10, x15, dyn, 0, 0, x3, 36*FLEN/8, x15, x1, x2) + +inst_13: +// rs1==x18, rs2==x30, rs3==x20, rd==x5,fs1 == 0 and fe1 == 0x1c and fm1 == 0x1f2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ef and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x18; op2:x30; op3:x20; dest:x5; op1val:0x71f2; op2val:0x7bef; +op3val:0x7bff; valaddr_reg:x3; val_offset:39*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x5, x18, x30, x20, dyn, 0, 0, x3, 39*FLEN/8, x15, x1, x2) +RVTEST_VALBASEUPD(x11,test_dataset_1) + +inst_14: +// rs1==x29, rs2==x24, rs3==x13, rd==x25,fs1 == 0 and fe1 == 0x1b and fm1 == 0x3bb and fs2 == 0 and fe2 == 0x1d and fm2 == 0x152 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x29; op2:x24; op3:x13; dest:x25; op1val:0x6fbb; op2val:0x7552; +op3val:0x7bff; valaddr_reg:x11; val_offset:0*FLEN/8; rmval:dyn; +testreg:x17; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x25, x29, x24, x13, dyn, 0, 0, x11, 0*FLEN/8, x12, x1, x17) +RVTEST_SIGBASE(x5,signature_x5_0) + +inst_15: +// rs1==x10, rs2==x26, rs3==x21, rd==x3,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1af and fs2 == 0 and fe2 == 0x1e and fm2 == 0x37c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x10; op2:x26; op3:x21; dest:x3; op1val:0x79af; op2val:0x7b7c; +op3val:0x7bff; valaddr_reg:x11; val_offset:3*FLEN/8; rmval:dyn; +testreg:x17; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x3, x10, x26, x21, dyn, 0, 0, x11, 3*FLEN/8, x12, x5, x17) + +inst_16: +// rs1==x30, rs2==x21, rs3==x23, rd==x15,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x15c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x21; op3:x23; dest:x15; op1val:0x7aa3; op2val:0x795c; +op3val:0x7bff; valaddr_reg:x11; val_offset:6*FLEN/8; rmval:dyn; +testreg:x17; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x15, x30, x21, x23, dyn, 0, 0, x11, 6*FLEN/8, x12, x5, x17) + +inst_17: +// rs1==x15, rs2==x14, rs3==x19, rd==x18,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x30e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x15; op2:x14; op3:x19; dest:x18; op1val:0x78b2; op2val:0x7b0e; +op3val:0x7bff; valaddr_reg:x11; val_offset:9*FLEN/8; rmval:dyn; +testreg:x17; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x18, x15, x14, x19, dyn, 0, 0, x11, 9*FLEN/8, x12, x5, x17) + +inst_18: +// rs1==x16, rs2==x3, rs3==x17, rd==x2,fs1 == 0 and fe1 == 0x1e and fm1 == 0x00a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0b5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x16; op2:x3; op3:x17; dest:x2; op1val:0x780a; op2val:0x78b5; +op3val:0x7bff; valaddr_reg:x11; val_offset:12*FLEN/8; rmval:dyn; +testreg:x17; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x2, x16, x3, x17, dyn, 0, 0, x11, 12*FLEN/8, x12, x5, x17) + +inst_19: +// rs1==x1, rs2==x6, rs3==x2, rd==x13,fs1 == 0 and fe1 == 0x1c and fm1 == 0x3c3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x260 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x1; op2:x6; op3:x2; dest:x13; op1val:0x73c3; op2val:0x7a60; +op3val:0x7bff; valaddr_reg:x11; val_offset:15*FLEN/8; rmval:dyn; +testreg:x17; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x13, x1, x6, x2, dyn, 0, 0, x11, 15*FLEN/8, x12, x5, x17) + +inst_20: +// rs1==x8, rs2==x9, rs3==x10, rd==x30,fs1 == 0 and fe1 == 0x1c and fm1 == 0x188 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x063 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x8; op2:x9; op3:x10; dest:x30; op1val:0x7188; op2val:0x7863; +op3val:0x7bff; valaddr_reg:x11; val_offset:18*FLEN/8; rmval:dyn; +testreg:x17; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x30, x8, x9, x10, dyn, 0, 0, x11, 18*FLEN/8, x12, x5, x17) + +inst_21: +// rs1==x7, rs2==x18, rs3==x4, rd==x6,fs1 == 0 and fe1 == 0x1e and fm1 == 0x164 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x7; op2:x18; op3:x4; dest:x6; op1val:0x7964; op2val:0x75fe; +op3val:0x7bff; valaddr_reg:x11; val_offset:21*FLEN/8; rmval:dyn; +testreg:x17; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x6, x7, x18, x4, dyn, 0, 0, x11, 21*FLEN/8, x12, x5, x17) + +inst_22: +// rs1==x2, rs2==x15, rs3==x18, rd==x21,fs1 == 0 and fe1 == 0x1e and fm1 == 0x010 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x239 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x2; op2:x15; op3:x18; dest:x21; op1val:0x7810; op2val:0x7a39; +op3val:0x7bff; valaddr_reg:x11; val_offset:24*FLEN/8; rmval:dyn; +testreg:x17; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x21, x2, x15, x18, dyn, 0, 0, x11, 24*FLEN/8, x12, x5, x17) + +inst_23: +// rs1==x25, rs2==x13, rs3==x31, rd==x7,fs1 == 0 and fe1 == 0x1d and fm1 == 0x249 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3d4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x25; op2:x13; op3:x31; dest:x7; op1val:0x7649; op2val:0x77d4; +op3val:0x7bff; valaddr_reg:x11; val_offset:27*FLEN/8; rmval:dyn; +testreg:x17; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x7, x25, x13, x31, dyn, 0, 0, x11, 27*FLEN/8, x12, x5, x17) + +inst_24: +// rs1==x31, rs2==x25, rs3==x29, rd==x23,fs1 == 0 and fe1 == 0x1a and fm1 == 0x190 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x19f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x31; op2:x25; op3:x29; dest:x23; op1val:0x6990; op2val:0x799f; +op3val:0x7bff; valaddr_reg:x11; val_offset:30*FLEN/8; rmval:dyn; +testreg:x17; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x23, x31, x25, x29, dyn, 0, 0, x11, 30*FLEN/8, x12, x5, x17) + +inst_25: +// rs1==x21, rs2==x23, rs3==x3, rd==x4,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0be and fs2 == 0 and fe2 == 0x1d and fm2 == 0x24b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x21; op2:x23; op3:x3; dest:x4; op1val:0x78be; op2val:0x764b; +op3val:0x7bff; valaddr_reg:x11; val_offset:33*FLEN/8; rmval:dyn; +testreg:x17; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x4, x21, x23, x3, dyn, 0, 0, x11, 33*FLEN/8, x12, x5, x17) +RVTEST_VALBASEUPD(x7,test_dataset_2) + +inst_26: +// rs1==x11, rs2==x31, rs3==x9, rd==x29,fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3da and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x11; op2:x31; op3:x9; dest:x29; op1val:0x7804; op2val:0x7bda; +op3val:0x7bff; valaddr_reg:x7; val_offset:0*FLEN/8; rmval:dyn; +testreg:x17; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x29, x11, x31, x9, dyn, 0, 0, x7, 0*FLEN/8, x8, x5, x17) + +inst_27: +// rs1==x12, rs2==x19, rs3==x0, rd==x31,fs1 == 0 and fe1 == 0x1e and fm1 == 0x050 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x12; op2:x19; op3:x0; dest:x31; op1val:0x7850; op2val:0x7ae1; +op3val:0x0; valaddr_reg:x7; val_offset:3*FLEN/8; rmval:dyn; +testreg:x17; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x12, x19, x0, dyn, 0, 0, x7, 3*FLEN/8, x8, x5, x17) + +inst_28: +// rs1==x3, rs2==x2, rs3==x26, rd==x10,fs1 == 0 and fe1 == 0x1e and fm1 == 0x01b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x39d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x3; op2:x2; op3:x26; dest:x10; op1val:0x781b; op2val:0x7b9d; +op3val:0x7bff; valaddr_reg:x7; val_offset:6*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x10, x3, x2, x26, dyn, 0, 0, x7, 6*FLEN/8, x8, x5, x6) + +inst_29: +// rs1==x22, rs2==x1, rs3==x7, rd==x27,fs1 == 0 and fe1 == 0x1d and fm1 == 0x357 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x04e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x22; op2:x1; op3:x7; dest:x27; op1val:0x7757; op2val:0x744e; +op3val:0x7bff; valaddr_reg:x7; val_offset:9*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x27, x22, x1, x7, dyn, 0, 0, x7, 9*FLEN/8, x8, x5, x6) +RVTEST_SIGBASE(x2,signature_x2_0) + +inst_30: +// rs1==x24, rs2==x5, rs3==x22, rd==x19,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a7 and fs2 == 0 and fe2 == 0x17 and fm2 == 0x1d7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x24; op2:x5; op3:x22; dest:x19; op1val:0x7ba7; op2val:0x5dd7; +op3val:0x7bff; valaddr_reg:x7; val_offset:12*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x19, x24, x5, x22, dyn, 0, 0, x7, 12*FLEN/8, x8, x2, x6) + +inst_31: +// rs1==x5,fs1 == 0 and fe1 == 0x1e and fm1 == 0x28f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x316 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x5; op2:x13; op3:x28; dest:x24; op1val:0x7a8f; op2val:0x7b16; +op3val:0x7bff; valaddr_reg:x7; val_offset:15*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x24, x5, x13, x28, dyn, 0, 0, x7, 15*FLEN/8, x8, x2, x6) + +inst_32: +// rs2==x22,fs1 == 0 and fe1 == 0x1e and fm1 == 0x278 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x025 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x23; op2:x22; op3:x21; dest:x26; op1val:0x7a78; op2val:0x7825; +op3val:0x7bff; valaddr_reg:x7; val_offset:18*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x26, x23, x22, x21, dyn, 0, 0, x7, 18*FLEN/8, x8, x2, x6) + +inst_33: +// rs3==x1,fs1 == 0 and fe1 == 0x1d and fm1 == 0x2d0 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x32e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x4; op2:x29; op3:x1; dest:x23; op1val:0x76d0; op2val:0x6b2e; +op3val:0x7bff; valaddr_reg:x7; val_offset:21*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x23, x4, x29, x1, dyn, 0, 0, x7, 21*FLEN/8, x8, x2, x6) + +inst_34: +// rd==x1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x08e and fs2 == 0 and fe2 == 0x1c and fm2 == 0x264 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x11; op2:x0; op3:x26; dest:x1; op1val:0x788e; op2val:0x0; +op3val:0x7bff; valaddr_reg:x7; val_offset:24*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x1, x11, x0, x26, dyn, 0, 0, x7, 24*FLEN/8, x8, x2, x6) + +inst_35: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3c1 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1b4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77c1; op2val:0x75b4; +op3val:0x7bff; valaddr_reg:x7; val_offset:27*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 27*FLEN/8, x8, x2, x6) + +inst_36: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0fc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x784e; op2val:0x78fc; +op3val:0x7bff; valaddr_reg:x7; val_offset:30*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 30*FLEN/8, x8, x2, x6) + +inst_37: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x353 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x328 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7753; op2val:0x6728; +op3val:0x7bff; valaddr_reg:x7; val_offset:33*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 33*FLEN/8, x8, x2, x6) + +inst_38: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1ab and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0ac and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71ab; op2val:0x78ac; +op3val:0x7bff; valaddr_reg:x7; val_offset:36*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 36*FLEN/8, x8, x2, x6) + +inst_39: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x262 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x25f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a62; op2val:0x7a5f; +op3val:0x7bff; valaddr_reg:x7; val_offset:39*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 39*FLEN/8, x8, x2, x6) + +inst_40: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x015 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2bb and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7415; op2val:0x7abb; +op3val:0x7bff; valaddr_reg:x7; val_offset:42*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 42*FLEN/8, x8, x2, x6) + +inst_41: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x153 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x045 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d53; op2val:0x6445; +op3val:0x7bff; valaddr_reg:x7; val_offset:45*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 45*FLEN/8, x8, x2, x6) + +inst_42: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20a and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3fb and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a0a; op2val:0x73fb; +op3val:0x7bff; valaddr_reg:x7; val_offset:48*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 48*FLEN/8, x8, x2, x6) + +inst_43: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fe and fs2 == 0 and fe2 == 0x1d and fm2 == 0x182 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fe; op2val:0x7582; +op3val:0x7bff; valaddr_reg:x7; val_offset:51*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 51*FLEN/8, x8, x2, x6) + +inst_44: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x11b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x037 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x711b; op2val:0x7837; +op3val:0x7bff; valaddr_reg:x7; val_offset:54*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 54*FLEN/8, x8, x2, x6) + +inst_45: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x05d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1b0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x745d; op2val:0x79b0; +op3val:0x7bff; valaddr_reg:x7; val_offset:57*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 57*FLEN/8, x8, x2, x6) + +inst_46: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x126 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x393 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7526; op2val:0x7793; +op3val:0x7bff; valaddr_reg:x7; val_offset:60*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 60*FLEN/8, x8, x2, x6) + +inst_47: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x22e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2bb and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x762e; op2val:0x76bb; +op3val:0x7bff; valaddr_reg:x7; val_offset:63*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 63*FLEN/8, x8, x2, x6) + +inst_48: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2f5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x331 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ef5; op2val:0x7b31; +op3val:0x7bff; valaddr_reg:x7; val_offset:66*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 66*FLEN/8, x8, x2, x6) + +inst_49: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0d7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72b0; op2val:0x78d7; +op3val:0x7bff; valaddr_reg:x7; val_offset:69*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 69*FLEN/8, x8, x2, x6) + +inst_50: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x153 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x092 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6553; op2val:0x6492; +op3val:0x7bff; valaddr_reg:x7; val_offset:72*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 72*FLEN/8, x8, x2, x6) + +inst_51: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1bf and fs2 == 0 and fe2 == 0x1c and fm2 == 0x11f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79bf; op2val:0x711f; +op3val:0x7bff; valaddr_reg:x7; val_offset:75*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 75*FLEN/8, x8, x2, x6) + +inst_52: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x16c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x05b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x796c; op2val:0x785b; +op3val:0x7bff; valaddr_reg:x7; val_offset:78*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 78*FLEN/8, x8, x2, x6) + +inst_53: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3cd and fs2 == 0 and fe2 == 0x1e and fm2 == 0x261 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bcd; op2val:0x7a61; +op3val:0x7bff; valaddr_reg:x7; val_offset:81*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 81*FLEN/8, x8, x2, x6) + +inst_54: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x323 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x12f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7323; op2val:0x792f; +op3val:0x7bff; valaddr_reg:x7; val_offset:84*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 84*FLEN/8, x8, x2, x6) + +inst_55: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09a and fs2 == 0 and fe2 == 0x1d and fm2 == 0x123 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x789a; op2val:0x7523; +op3val:0x7bff; valaddr_reg:x7; val_offset:87*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 87*FLEN/8, x8, x2, x6) + +inst_56: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x385 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0c6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6b85; op2val:0x74c6; +op3val:0x7bff; valaddr_reg:x7; val_offset:90*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 90*FLEN/8, x8, x2, x6) + +inst_57: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x300 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0e6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b00; op2val:0x74e6; +op3val:0x7bff; valaddr_reg:x7; val_offset:93*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 93*FLEN/8, x8, x2, x6) + +inst_58: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x382 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74f6; op2val:0x7b82; +op3val:0x7bff; valaddr_reg:x7; val_offset:96*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 96*FLEN/8, x8, x2, x6) + +inst_59: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a7 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x009 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76a7; op2val:0x7409; +op3val:0x7bff; valaddr_reg:x7; val_offset:99*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 99*FLEN/8, x8, x2, x6) + +inst_60: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x306 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x0d9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b06; op2val:0x68d9; +op3val:0x7bff; valaddr_reg:x7; val_offset:102*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 102*FLEN/8, x8, x2, x6) + +inst_61: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x08f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bb1; op2val:0x788f; +op3val:0x7bff; valaddr_reg:x7; val_offset:105*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 105*FLEN/8, x8, x2, x6) + +inst_62: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3c9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7af0; op2val:0x7bc9; +op3val:0x7bff; valaddr_reg:x7; val_offset:108*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 108*FLEN/8, x8, x2, x6) + +inst_63: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x011 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x20b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7811; op2val:0x760b; +op3val:0x7bff; valaddr_reg:x7; val_offset:111*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 111*FLEN/8, x8, x2, x6) + +inst_64: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x294 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x163 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7294; op2val:0x7963; +op3val:0x7bff; valaddr_reg:x7; val_offset:114*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 114*FLEN/8, x8, x2, x6) + +inst_65: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x235 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2ae and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7235; op2val:0x6eae; +op3val:0x7bff; valaddr_reg:x7; val_offset:117*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 117*FLEN/8, x8, x2, x6) + +inst_66: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0bc and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74bc; op2val:0x77fe; +op3val:0x7bff; valaddr_reg:x7; val_offset:120*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 120*FLEN/8, x8, x2, x6) + +inst_67: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x331 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7af8; op2val:0x7b31; +op3val:0x7bff; valaddr_reg:x7; val_offset:123*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 123*FLEN/8, x8, x2, x6) + +inst_68: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x26c and fs2 == 0 and fe2 == 0x1d and fm2 == 0x13d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x726c; op2val:0x753d; +op3val:0x7bff; valaddr_reg:x7; val_offset:126*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 126*FLEN/8, x8, x2, x6) + +inst_69: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x242 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x16c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a42; op2val:0x756c; +op3val:0x7bff; valaddr_reg:x7; val_offset:129*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 129*FLEN/8, x8, x2, x6) + +inst_70: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x164 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7964; op2val:0x7ab2; +op3val:0x7bff; valaddr_reg:x7; val_offset:132*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 132*FLEN/8, x8, x2, x6) + +inst_71: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x17f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x30e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x757f; op2val:0x7b0e; +op3val:0x7bff; valaddr_reg:x7; val_offset:135*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 135*FLEN/8, x8, x2, x6) + +inst_72: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3bf and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77bf; op2val:0x7be1; +op3val:0x7bff; valaddr_reg:x7; val_offset:138*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 138*FLEN/8, x8, x2, x6) + +inst_73: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1cd and fs2 == 0 and fe2 == 0x1b and fm2 == 0x16a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79cd; op2val:0x6d6a; +op3val:0x7bff; valaddr_reg:x7; val_offset:141*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 141*FLEN/8, x8, x2, x6) + +inst_74: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x348 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2cf and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b48; op2val:0x72cf; +op3val:0x7bff; valaddr_reg:x7; val_offset:144*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 144*FLEN/8, x8, x2, x6) + +inst_75: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0cc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78cc; op2val:0x7ab9; +op3val:0x7bff; valaddr_reg:x7; val_offset:147*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 147*FLEN/8, x8, x2, x6) + +inst_76: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x171 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0a8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7571; op2val:0x74a8; +op3val:0x7bff; valaddr_reg:x7; val_offset:150*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 150*FLEN/8, x8, x2, x6) + +inst_77: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3a1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78d4; op2val:0x7ba1; +op3val:0x7bff; valaddr_reg:x7; val_offset:153*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 153*FLEN/8, x8, x2, x6) + +inst_78: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x054 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x068 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7054; op2val:0x7868; +op3val:0x7bff; valaddr_reg:x7; val_offset:156*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 156*FLEN/8, x8, x2, x6) + +inst_79: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x101 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0ae and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6901; op2val:0x6cae; +op3val:0x7bff; valaddr_reg:x7; val_offset:159*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 159*FLEN/8, x8, x2, x6) + +inst_80: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x24d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x29f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a4d; op2val:0x7a9f; +op3val:0x7bff; valaddr_reg:x7; val_offset:162*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 162*FLEN/8, x8, x2, x6) + +inst_81: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0eb and fs2 == 0 and fe2 == 0x1e and fm2 == 0x240 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78eb; op2val:0x7a40; +op3val:0x7bff; valaddr_reg:x7; val_offset:165*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 165*FLEN/8, x8, x2, x6) + +inst_82: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x090 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x327 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7890; op2val:0x7327; +op3val:0x7bff; valaddr_reg:x7; val_offset:168*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 168*FLEN/8, x8, x2, x6) + +inst_83: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x043 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x31f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7443; op2val:0x7b1f; +op3val:0x7bff; valaddr_reg:x7; val_offset:171*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 171*FLEN/8, x8, x2, x6) + +inst_84: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x365 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x352 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b65; op2val:0x7752; +op3val:0x7bff; valaddr_reg:x7; val_offset:174*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 174*FLEN/8, x8, x2, x6) + +inst_85: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x24b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x29e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a4b; op2val:0x7a9e; +op3val:0x7bff; valaddr_reg:x7; val_offset:177*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 177*FLEN/8, x8, x2, x6) + +inst_86: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15c and fs2 == 0 and fe2 == 0x1b and fm2 == 0x1dd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x795c; op2val:0x6ddd; +op3val:0x7bff; valaddr_reg:x7; val_offset:180*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 180*FLEN/8, x8, x2, x6) + +inst_87: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x313 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x11e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b13; op2val:0x691e; +op3val:0x7bff; valaddr_reg:x7; val_offset:183*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 183*FLEN/8, x8, x2, x6) + +inst_88: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e6 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2bb and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7be6; op2val:0x76bb; +op3val:0x7bff; valaddr_reg:x7; val_offset:186*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 186*FLEN/8, x8, x2, x6) + +inst_89: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x15a and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3b8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x715a; op2val:0x73b8; +op3val:0x7bff; valaddr_reg:x7; val_offset:189*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 189*FLEN/8, x8, x2, x6) + +inst_90: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x294 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x348 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e94; op2val:0x7b48; +op3val:0x7bff; valaddr_reg:x7; val_offset:192*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 192*FLEN/8, x8, x2, x6) + +inst_91: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x345 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bc2; op2val:0x7b45; +op3val:0x7bff; valaddr_reg:x7; val_offset:195*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 195*FLEN/8, x8, x2, x6) + +inst_92: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x00d and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3a0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x740d; op2val:0x77a0; +op3val:0x7bff; valaddr_reg:x7; val_offset:198*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 198*FLEN/8, x8, x2, x6) + +inst_93: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x136 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x111 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7936; op2val:0x6911; +op3val:0x7bff; valaddr_reg:x7; val_offset:201*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 201*FLEN/8, x8, x2, x6) + +inst_94: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3db and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0b9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bdb; op2val:0x74b9; +op3val:0x7bff; valaddr_reg:x7; val_offset:204*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 204*FLEN/8, x8, x2, x6) + +inst_95: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x331 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x102 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7731; op2val:0x7502; +op3val:0x7bff; valaddr_reg:x7; val_offset:207*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 207*FLEN/8, x8, x2, x6) + +inst_96: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x34d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3c1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b4d; op2val:0x7bc1; +op3val:0x7bff; valaddr_reg:x7; val_offset:210*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 210*FLEN/8, x8, x2, x6) + +inst_97: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x31f and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2e2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f1f; op2val:0x72e2; +op3val:0x7bff; valaddr_reg:x7; val_offset:213*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 213*FLEN/8, x8, x2, x6) + +inst_98: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x057 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd5; op2val:0x7857; +op3val:0x7bff; valaddr_reg:x7; val_offset:216*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 216*FLEN/8, x8, x2, x6) + +inst_99: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x14a and fs2 == 0 and fe2 == 0x1d and fm2 == 0x024 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x794a; op2val:0x7424; +op3val:0x7bff; valaddr_reg:x7; val_offset:219*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 219*FLEN/8, x8, x2, x6) + +inst_100: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ea and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74ea; op2val:0x73e1; +op3val:0x7bff; valaddr_reg:x7; val_offset:222*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 222*FLEN/8, x8, x2, x6) + +inst_101: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x07d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3dc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x747d; op2val:0x7bdc; +op3val:0x7bff; valaddr_reg:x7; val_offset:225*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 225*FLEN/8, x8, x2, x6) + +inst_102: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x136 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x125 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7936; op2val:0x7925; +op3val:0x7bff; valaddr_reg:x7; val_offset:228*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 228*FLEN/8, x8, x2, x6) + +inst_103: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x23e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0e7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x763e; op2val:0x74e7; +op3val:0x7bff; valaddr_reg:x7; val_offset:231*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 231*FLEN/8, x8, x2, x6) + +inst_104: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x110 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7510; op2val:0x7ac6; +op3val:0x7bff; valaddr_reg:x7; val_offset:234*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 234*FLEN/8, x8, x2, x6) + +inst_105: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d7 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x158 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74d7; op2val:0x7558; +op3val:0x7bff; valaddr_reg:x7; val_offset:237*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 237*FLEN/8, x8, x2, x6) + +inst_106: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0c3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78a1; op2val:0x78c3; +op3val:0x7bff; valaddr_reg:x7; val_offset:240*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 240*FLEN/8, x8, x2, x6) + +inst_107: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x136 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3cb and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6536; op2val:0x73cb; +op3val:0x7bff; valaddr_reg:x7; val_offset:243*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 243*FLEN/8, x8, x2, x6) + +inst_108: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x068 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x089 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7868; op2val:0x6c89; +op3val:0x7bff; valaddr_reg:x7; val_offset:246*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 246*FLEN/8, x8, x2, x6) + +inst_109: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x114 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0a6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7914; op2val:0x74a6; +op3val:0x7bff; valaddr_reg:x7; val_offset:249*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 249*FLEN/8, x8, x2, x6) + +inst_110: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3e3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2e5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77e3; op2val:0x7ae5; +op3val:0x7bff; valaddr_reg:x7; val_offset:252*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 252*FLEN/8, x8, x2, x6) + +inst_111: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x25b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7802; op2val:0x7a5b; +op3val:0x7bff; valaddr_reg:x7; val_offset:255*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 255*FLEN/8, x8, x2, x6) + +inst_112: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x397 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x18a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b97; op2val:0x718a; +op3val:0x7bff; valaddr_reg:x7; val_offset:258*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 258*FLEN/8, x8, x2, x6) + +inst_113: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x291 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7be0; op2val:0x7a91; +op3val:0x7bff; valaddr_reg:x7; val_offset:261*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 261*FLEN/8, x8, x2, x6) + +inst_114: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2d6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x01c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ed6; op2val:0x781c; +op3val:0x7bff; valaddr_reg:x7; val_offset:264*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 264*FLEN/8, x8, x2, x6) + +inst_115: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0b1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x325 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74b1; op2val:0x7b25; +op3val:0x7bff; valaddr_reg:x7; val_offset:267*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 267*FLEN/8, x8, x2, x6) + +inst_116: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x347 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x010 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b47; op2val:0x6810; +op3val:0x7bff; valaddr_reg:x7; val_offset:270*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 270*FLEN/8, x8, x2, x6) + +inst_117: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x338 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x26d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b38; op2val:0x7a6d; +op3val:0x7bff; valaddr_reg:x7; val_offset:273*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 273*FLEN/8, x8, x2, x6) + +inst_118: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1f7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ab8; op2val:0x79f7; +op3val:0x7bff; valaddr_reg:x7; val_offset:276*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 276*FLEN/8, x8, x2, x6) + +inst_119: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1b2 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2eb and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71b2; op2val:0x76eb; +op3val:0x7bff; valaddr_reg:x7; val_offset:279*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 279*FLEN/8, x8, x2, x6) + +inst_120: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x156 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79b7; op2val:0x7956; +op3val:0x7bff; valaddr_reg:x7; val_offset:282*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 282*FLEN/8, x8, x2, x6) + +inst_121: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x01e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3b4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c1e; op2val:0x7bb4; +op3val:0x7bff; valaddr_reg:x7; val_offset:285*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 285*FLEN/8, x8, x2, x6) + +inst_122: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x064 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x054 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7864; op2val:0x7854; +op3val:0x7bff; valaddr_reg:x7; val_offset:288*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 288*FLEN/8, x8, x2, x6) + +inst_123: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x33f and fs2 == 0 and fe2 == 0x1d and fm2 == 0x254 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x773f; op2val:0x7654; +op3val:0x7bff; valaddr_reg:x7; val_offset:291*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 291*FLEN/8, x8, x2, x6) + +inst_124: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x020 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x23e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7420; op2val:0x663e; +op3val:0x7bff; valaddr_reg:x7; val_offset:294*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 294*FLEN/8, x8, x2, x6) + +inst_125: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x090 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76a9; op2val:0x7890; +op3val:0x7bff; valaddr_reg:x7; val_offset:297*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 297*FLEN/8, x8, x2, x6) + +inst_126: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ad and fs2 == 0 and fe2 == 0x1c and fm2 == 0x06c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75ad; op2val:0x706c; +op3val:0x7bff; valaddr_reg:x7; val_offset:300*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 300*FLEN/8, x8, x2, x6) + +inst_127: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x024 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2a0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7424; op2val:0x7aa0; +op3val:0x7bff; valaddr_reg:x7; val_offset:303*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 303*FLEN/8, x8, x2, x6) + +inst_128: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0e5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x766a; op2val:0x78e5; +op3val:0x7bff; valaddr_reg:x7; val_offset:306*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 306*FLEN/8, x8, x2, x6) + +inst_129: +// fs1 == 0 and fe1 == 0x17 and fm1 == 0x3a7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x03a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5fa7; op2val:0x783a; +op3val:0x7bff; valaddr_reg:x7; val_offset:309*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 309*FLEN/8, x8, x2, x6) + +inst_130: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x130 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x302 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7930; op2val:0x7702; +op3val:0x7bff; valaddr_reg:x7; val_offset:312*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 312*FLEN/8, x8, x2, x6) + +inst_131: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d9 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79d9; op2val:0x739f; +op3val:0x7bff; valaddr_reg:x7; val_offset:315*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 315*FLEN/8, x8, x2, x6) + +inst_132: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a8 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x332 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77a8; op2val:0x7332; +op3val:0x7bff; valaddr_reg:x7; val_offset:318*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 318*FLEN/8, x8, x2, x6) + +inst_133: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x07b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x340 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x787b; op2val:0x7b40; +op3val:0x7bff; valaddr_reg:x7; val_offset:321*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 321*FLEN/8, x8, x2, x6) + +inst_134: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x066 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x12b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7466; op2val:0x792b; +op3val:0x7bff; valaddr_reg:x7; val_offset:324*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 324*FLEN/8, x8, x2, x6) + +inst_135: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x093 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x017 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c93; op2val:0x7817; +op3val:0x7bff; valaddr_reg:x7; val_offset:327*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 327*FLEN/8, x8, x2, x6) + +inst_136: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x119 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x220 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7119; op2val:0x7a20; +op3val:0x7bff; valaddr_reg:x7; val_offset:330*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 330*FLEN/8, x8, x2, x6) + +inst_137: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0fc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x189 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74fc; op2val:0x7989; +op3val:0x7bff; valaddr_reg:x7; val_offset:333*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 333*FLEN/8, x8, x2, x6) + +inst_138: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1f1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x19b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75f1; op2val:0x799b; +op3val:0x7bff; valaddr_reg:x7; val_offset:336*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 336*FLEN/8, x8, x2, x6) + +inst_139: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2d8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78c1; op2val:0x7ad8; +op3val:0x7bff; valaddr_reg:x7; val_offset:339*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 339*FLEN/8, x8, x2, x6) + +inst_140: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ad and fs2 == 0 and fe2 == 0x1e and fm2 == 0x091 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bad; op2val:0x7891; +op3val:0x7bff; valaddr_reg:x7; val_offset:342*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 342*FLEN/8, x8, x2, x6) + +inst_141: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2f5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7401; op2val:0x72f5; +op3val:0x7bff; valaddr_reg:x7; val_offset:345*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 345*FLEN/8, x8, x2, x6) + +inst_142: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20f and fs2 == 0 and fe2 == 0x1a and fm2 == 0x2ab and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a0f; op2val:0x6aab; +op3val:0x7bff; valaddr_reg:x7; val_offset:348*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 348*FLEN/8, x8, x2, x6) + +inst_143: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1bc and fs2 == 0 and fe2 == 0x1d and fm2 == 0x190 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79bc; op2val:0x7590; +op3val:0x7bff; valaddr_reg:x7; val_offset:351*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 351*FLEN/8, x8, x2, x6) + +inst_144: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x145 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1d6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7145; op2val:0x79d6; +op3val:0x7bff; valaddr_reg:x7; val_offset:354*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 354*FLEN/8, x8, x2, x6) + +inst_145: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x275 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd8; op2val:0x7a75; +op3val:0x7bff; valaddr_reg:x7; val_offset:357*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 357*FLEN/8, x8, x2, x6) + +inst_146: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x047 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x34c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7447; op2val:0x7b4c; +op3val:0x7bff; valaddr_reg:x7; val_offset:360*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 360*FLEN/8, x8, x2, x6) + +inst_147: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x073 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x233 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7073; op2val:0x7a33; +op3val:0x7bff; valaddr_reg:x7; val_offset:363*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 363*FLEN/8, x8, x2, x6) + +inst_148: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x146 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x199 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7946; op2val:0x7999; +op3val:0x7bff; valaddr_reg:x7; val_offset:366*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 366*FLEN/8, x8, x2, x6) + +inst_149: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x364 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3c4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b64; op2val:0x7bc4; +op3val:0x7bff; valaddr_reg:x7; val_offset:369*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 369*FLEN/8, x8, x2, x6) + +inst_150: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26b and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2ec and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a6b; op2val:0x76ec; +op3val:0x7bff; valaddr_reg:x7; val_offset:372*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 372*FLEN/8, x8, x2, x6) + +inst_151: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x134 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x00a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7534; op2val:0x700a; +op3val:0x7bff; valaddr_reg:x7; val_offset:375*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 375*FLEN/8, x8, x2, x6) + +inst_152: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ab and fs2 == 0 and fe2 == 0x1b and fm2 == 0x39f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bab; op2val:0x6f9f; +op3val:0x7bff; valaddr_reg:x7; val_offset:378*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 378*FLEN/8, x8, x2, x6) + +inst_153: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x287 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x38d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7687; op2val:0x6f8d; +op3val:0x7bff; valaddr_reg:x7; val_offset:381*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 381*FLEN/8, x8, x2, x6) + +inst_154: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73f0; op2val:0x79fe; +op3val:0x7bff; valaddr_reg:x7; val_offset:384*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 384*FLEN/8, x8, x2, x6) + +inst_155: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x212 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x304 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7212; op2val:0x7704; +op3val:0x7bff; valaddr_reg:x7; val_offset:387*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 387*FLEN/8, x8, x2, x6) + +inst_156: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x104 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0d7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7904; op2val:0x78d7; +op3val:0x7bff; valaddr_reg:x7; val_offset:390*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 390*FLEN/8, x8, x2, x6) + +inst_157: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x29b and fs2 == 0 and fe2 == 0x1d and fm2 == 0x08d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x729b; op2val:0x748d; +op3val:0x7bff; valaddr_reg:x7; val_offset:393*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 393*FLEN/8, x8, x2, x6) +RVTEST_SIGBASE(x2,signature_x2_1) + +inst_158: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x05e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0af and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x745e; op2val:0x78af; +op3val:0x7bff; valaddr_reg:x7; val_offset:396*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 396*FLEN/8, x8, x2, x6) + +inst_159: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x177 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x253 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7977; op2val:0x7a53; +op3val:0x7bff; valaddr_reg:x7; val_offset:399*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 399*FLEN/8, x8, x2, x6) + +inst_160: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x05c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bc8; op2val:0x785c; +op3val:0x7bff; valaddr_reg:x7; val_offset:402*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 402*FLEN/8, x8, x2, x6) + +inst_161: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x226 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ad7; op2val:0x7a26; +op3val:0x7bff; valaddr_reg:x7; val_offset:405*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 405*FLEN/8, x8, x2, x6) + +inst_162: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x221 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x08a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7621; op2val:0x748a; +op3val:0x7bff; valaddr_reg:x7; val_offset:408*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 408*FLEN/8, x8, x2, x6) + +inst_163: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x275 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x38d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a75; op2val:0x6f8d; +op3val:0x7bff; valaddr_reg:x7; val_offset:411*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 411*FLEN/8, x8, x2, x6) + +inst_164: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x05c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3b7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x785c; op2val:0x7bb7; +op3val:0x7bff; valaddr_reg:x7; val_offset:414*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 414*FLEN/8, x8, x2, x6) + +inst_165: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c8 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x05e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bc8; op2val:0x705e; +op3val:0x7bff; valaddr_reg:x7; val_offset:417*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 417*FLEN/8, x8, x2, x6) + +inst_166: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x094 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0fa and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7894; op2val:0x74fa; +op3val:0x7bff; valaddr_reg:x7; val_offset:420*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 420*FLEN/8, x8, x2, x6) + +inst_167: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1b4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x039 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75b4; op2val:0x7839; +op3val:0x7bff; valaddr_reg:x7; val_offset:423*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 423*FLEN/8, x8, x2, x6) + +inst_168: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x312 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x330 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7712; op2val:0x7730; +op3val:0x7bff; valaddr_reg:x7; val_offset:426*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 426*FLEN/8, x8, x2, x6) + +inst_169: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x263 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x242 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7663; op2val:0x7a42; +op3val:0x7bff; valaddr_reg:x7; val_offset:429*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 429*FLEN/8, x8, x2, x6) + +inst_170: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3df and fs2 == 0 and fe2 == 0x1e and fm2 == 0x12d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77df; op2val:0x792d; +op3val:0x7bff; valaddr_reg:x7; val_offset:432*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 432*FLEN/8, x8, x2, x6) + +inst_171: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x285 and fs2 == 0 and fe2 == 0x16 and fm2 == 0x3ee and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7285; op2val:0x5bee; +op3val:0x7bff; valaddr_reg:x7; val_offset:435*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 435*FLEN/8, x8, x2, x6) + +inst_172: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x30c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78c8; op2val:0x7b0c; +op3val:0x7bff; valaddr_reg:x7; val_offset:438*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 438*FLEN/8, x8, x2, x6) + +inst_173: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x015 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3e4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7815; op2val:0x7be4; +op3val:0x7bff; valaddr_reg:x7; val_offset:441*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 441*FLEN/8, x8, x2, x6) + +inst_174: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ac and fs2 == 0 and fe2 == 0x1d and fm2 == 0x28a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aac; op2val:0x768a; +op3val:0x7bff; valaddr_reg:x7; val_offset:444*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 444*FLEN/8, x8, x2, x6) + +inst_175: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e5 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0e2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7be5; op2val:0x74e2; +op3val:0x7bff; valaddr_reg:x7; val_offset:447*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 447*FLEN/8, x8, x2, x6) + +inst_176: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0f5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x03e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78f5; op2val:0x783e; +op3val:0x7bff; valaddr_reg:x7; val_offset:450*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 450*FLEN/8, x8, x2, x6) + +inst_177: +// fs1 == 0 and fe1 == 0x16 and fm1 == 0x334 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x239 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5b34; op2val:0x7639; +op3val:0x7bff; valaddr_reg:x7; val_offset:453*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 453*FLEN/8, x8, x2, x6) + +inst_178: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x27b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2e2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x767b; op2val:0x7ae2; +op3val:0x7bff; valaddr_reg:x7; val_offset:456*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 456*FLEN/8, x8, x2, x6) + +inst_179: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1de and fs2 == 0 and fe2 == 0x1e and fm2 == 0x32e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79de; op2val:0x7b2e; +op3val:0x7bff; valaddr_reg:x7; val_offset:459*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 459*FLEN/8, x8, x2, x6) + +inst_180: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3e1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1f6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77e1; op2val:0x79f6; +op3val:0x7bff; valaddr_reg:x7; val_offset:462*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 462*FLEN/8, x8, x2, x6) + +inst_181: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x108 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x792f; op2val:0x7908; +op3val:0x7bff; valaddr_reg:x7; val_offset:465*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 465*FLEN/8, x8, x2, x6) + +inst_182: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x108 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x111 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7908; op2val:0x7911; +op3val:0x7bff; valaddr_reg:x7; val_offset:468*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 468*FLEN/8, x8, x2, x6) + +inst_183: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x241 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a41; op2val:0x7ac4; +op3val:0x7bff; valaddr_reg:x7; val_offset:471*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 471*FLEN/8, x8, x2, x6) + +inst_184: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x284 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0d7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a84; op2val:0x78d7; +op3val:0x7bff; valaddr_reg:x7; val_offset:474*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 474*FLEN/8, x8, x2, x6) + +inst_185: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x03b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1a9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x743b; op2val:0x79a9; +op3val:0x7bff; valaddr_reg:x7; val_offset:477*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 477*FLEN/8, x8, x2, x6) + +inst_186: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x05a and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0dd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x785a; op2val:0x70dd; +op3val:0x7bff; valaddr_reg:x7; val_offset:480*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 480*FLEN/8, x8, x2, x6) + +inst_187: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3bf and fs2 == 0 and fe2 == 0x1d and fm2 == 0x378 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77bf; op2val:0x7778; +op3val:0x7bff; valaddr_reg:x7; val_offset:483*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 483*FLEN/8, x8, x2, x6) + +inst_188: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x014 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1f4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7814; op2val:0x79f4; +op3val:0x7bff; valaddr_reg:x7; val_offset:486*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 486*FLEN/8, x8, x2, x6) + +inst_189: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ae and fs2 == 0 and fe2 == 0x1e and fm2 == 0x140 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75ae; op2val:0x7940; +op3val:0x7bff; valaddr_reg:x7; val_offset:489*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 489*FLEN/8, x8, x2, x6) + +inst_190: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x390 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x780e; op2val:0x7b90; +op3val:0x7bff; valaddr_reg:x7; val_offset:492*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 492*FLEN/8, x8, x2, x6) + +inst_191: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x182 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x766d; op2val:0x7982; +op3val:0x7bff; valaddr_reg:x7; val_offset:495*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 495*FLEN/8, x8, x2, x6) + +inst_192: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2a4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72ae; op2val:0x72a4; +op3val:0x7bff; valaddr_reg:x7; val_offset:498*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 498*FLEN/8, x8, x2, x6) + +inst_193: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x04d and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0ca and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x744d; op2val:0x6cca; +op3val:0x7bff; valaddr_reg:x7; val_offset:501*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 501*FLEN/8, x8, x2, x6) + +inst_194: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1e3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x782e; op2val:0x75e3; +op3val:0x7bff; valaddr_reg:x7; val_offset:504*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 504*FLEN/8, x8, x2, x6) + +inst_195: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1e4 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x164 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79e4; op2val:0x7164; +op3val:0x7bff; valaddr_reg:x7; val_offset:507*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 507*FLEN/8, x8, x2, x6) + +inst_196: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x284 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79b4; op2val:0x7a84; +op3val:0x7bff; valaddr_reg:x7; val_offset:510*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 510*FLEN/8, x8, x2, x6) + +inst_197: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0df and fs2 == 0 and fe2 == 0x1c and fm2 == 0x36c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78df; op2val:0x736c; +op3val:0x7bff; valaddr_reg:x7; val_offset:513*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 513*FLEN/8, x8, x2, x6) + +inst_198: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x183 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x250 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7183; op2val:0x7a50; +op3val:0x7bff; valaddr_reg:x7; val_offset:516*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 516*FLEN/8, x8, x2, x6) + +inst_199: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x145 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x31c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7545; op2val:0x731c; +op3val:0x7bff; valaddr_reg:x7; val_offset:519*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 519*FLEN/8, x8, x2, x6) + +inst_200: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x704c; op2val:0x7ac6; +op3val:0x7bff; valaddr_reg:x7; val_offset:522*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 522*FLEN/8, x8, x2, x6) + +inst_201: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x135 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x24e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7935; op2val:0x7a4e; +op3val:0x7bff; valaddr_reg:x7; val_offset:525*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 525*FLEN/8, x8, x2, x6) + +inst_202: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x340 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ae and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6740; op2val:0x7aae; +op3val:0x7bff; valaddr_reg:x7; val_offset:528*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 528*FLEN/8, x8, x2, x6) + +inst_203: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x218 and fs2 == 0 and fe2 == 0x16 and fm2 == 0x04f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a18; op2val:0x584f; +op3val:0x7bff; valaddr_reg:x7; val_offset:531*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 531*FLEN/8, x8, x2, x6) + +inst_204: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ed and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2c0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72ed; op2val:0x76c0; +op3val:0x7bff; valaddr_reg:x7; val_offset:534*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 534*FLEN/8, x8, x2, x6) + +inst_205: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x317 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x300 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7317; op2val:0x7700; +op3val:0x7bff; valaddr_reg:x7; val_offset:537*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 537*FLEN/8, x8, x2, x6) + +inst_206: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x374 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x362 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7374; op2val:0x7362; +op3val:0x7bff; valaddr_reg:x7; val_offset:540*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 540*FLEN/8, x8, x2, x6) + +inst_207: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x359 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0a2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7759; op2val:0x74a2; +op3val:0x7bff; valaddr_reg:x7; val_offset:543*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 543*FLEN/8, x8, x2, x6) + +inst_208: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x050 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7850; op2val:0x7ae1; +op3val:0x7bff; valaddr_reg:x7; val_offset:546*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 546*FLEN/8, x8, x2, x6) + +inst_209: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x08e and fs2 == 0 and fe2 == 0x1c and fm2 == 0x264 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x788e; op2val:0x7264; +op3val:0x7bff; valaddr_reg:x7; val_offset:549*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x7, 549*FLEN/8, x8, x2, x6) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(28748,32,FLEN) +NAN_BOXED(28748,32,FLEN) +NAN_BOXED(28748,32,FLEN) +NAN_BOXED(29716,32,FLEN) +NAN_BOXED(30700,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(31029,32,FLEN) +NAN_BOXED(31029,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(26432,32,FLEN) +NAN_BOXED(31406,32,FLEN) +NAN_BOXED(31406,32,FLEN) +NAN_BOXED(31256,32,FLEN) +NAN_BOXED(31256,32,FLEN) +NAN_BOXED(31256,32,FLEN) +NAN_BOXED(31172,32,FLEN) +NAN_BOXED(29521,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(31541,32,FLEN) +NAN_BOXED(26579,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(30804,32,FLEN) +NAN_BOXED(31618,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(29421,32,FLEN) +NAN_BOXED(30400,32,FLEN) +NAN_BOXED(30400,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(29556,32,FLEN) +NAN_BOXED(29538,32,FLEN) +NAN_BOXED(29556,32,FLEN) +NAN_BOXED(30553,32,FLEN) +NAN_BOXED(29858,32,FLEN) +NAN_BOXED(30553,32,FLEN) +NAN_BOXED(31410,32,FLEN) +NAN_BOXED(30835,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(29170,32,FLEN) +NAN_BOXED(31727,32,FLEN) +NAN_BOXED(31743,32,FLEN) +test_dataset_1: +NAN_BOXED(28603,32,FLEN) +NAN_BOXED(30034,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(31151,32,FLEN) +NAN_BOXED(31612,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(31395,32,FLEN) +NAN_BOXED(31068,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(30898,32,FLEN) +NAN_BOXED(31502,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(30730,32,FLEN) +NAN_BOXED(30901,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(29635,32,FLEN) +NAN_BOXED(31328,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(29064,32,FLEN) +NAN_BOXED(30819,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(31076,32,FLEN) +NAN_BOXED(30206,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(30736,32,FLEN) +NAN_BOXED(31289,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(30281,32,FLEN) +NAN_BOXED(30676,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(27024,32,FLEN) +NAN_BOXED(31135,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(30910,32,FLEN) +NAN_BOXED(30283,32,FLEN) +NAN_BOXED(31743,32,FLEN) +test_dataset_2: +NAN_BOXED(30724,16,FLEN) +NAN_BOXED(31706,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30800,16,FLEN) +NAN_BOXED(31457,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(30747,16,FLEN) +NAN_BOXED(31645,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30551,16,FLEN) +NAN_BOXED(29774,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31655,16,FLEN) +NAN_BOXED(24023,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31375,16,FLEN) +NAN_BOXED(31510,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31352,16,FLEN) +NAN_BOXED(30757,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30416,16,FLEN) +NAN_BOXED(27438,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30862,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30657,16,FLEN) +NAN_BOXED(30132,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30798,16,FLEN) +NAN_BOXED(30972,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30547,16,FLEN) +NAN_BOXED(26408,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29099,16,FLEN) +NAN_BOXED(30892,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31330,16,FLEN) +NAN_BOXED(31327,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29717,16,FLEN) +NAN_BOXED(31419,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(27987,16,FLEN) +NAN_BOXED(25669,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31242,16,FLEN) +NAN_BOXED(29691,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30974,16,FLEN) +NAN_BOXED(30082,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(28955,16,FLEN) +NAN_BOXED(30775,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29789,16,FLEN) +NAN_BOXED(31152,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29990,16,FLEN) +NAN_BOXED(30611,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30254,16,FLEN) +NAN_BOXED(30395,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(28405,16,FLEN) +NAN_BOXED(31537,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29360,16,FLEN) +NAN_BOXED(30935,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(25939,16,FLEN) +NAN_BOXED(25746,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31167,16,FLEN) +NAN_BOXED(28959,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31084,16,FLEN) +NAN_BOXED(30811,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31693,16,FLEN) +NAN_BOXED(31329,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29475,16,FLEN) +NAN_BOXED(31023,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30874,16,FLEN) +NAN_BOXED(29987,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(27525,16,FLEN) +NAN_BOXED(29894,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31488,16,FLEN) +NAN_BOXED(29926,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29942,16,FLEN) +NAN_BOXED(31618,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30375,16,FLEN) +NAN_BOXED(29705,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31494,16,FLEN) +NAN_BOXED(26841,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31665,16,FLEN) +NAN_BOXED(30863,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31472,16,FLEN) +NAN_BOXED(31689,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30737,16,FLEN) +NAN_BOXED(30219,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29332,16,FLEN) +NAN_BOXED(31075,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29237,16,FLEN) +NAN_BOXED(28334,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29884,16,FLEN) +NAN_BOXED(30718,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31480,16,FLEN) +NAN_BOXED(31537,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29292,16,FLEN) +NAN_BOXED(30013,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31298,16,FLEN) +NAN_BOXED(30060,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31076,16,FLEN) +NAN_BOXED(31410,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30079,16,FLEN) +NAN_BOXED(31502,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30655,16,FLEN) +NAN_BOXED(31713,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31181,16,FLEN) +NAN_BOXED(28010,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31560,16,FLEN) +NAN_BOXED(29391,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30924,16,FLEN) +NAN_BOXED(31417,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30065,16,FLEN) +NAN_BOXED(29864,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30932,16,FLEN) +NAN_BOXED(31649,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(28756,16,FLEN) +NAN_BOXED(30824,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(26881,16,FLEN) +NAN_BOXED(27822,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31309,16,FLEN) +NAN_BOXED(31391,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30955,16,FLEN) +NAN_BOXED(31296,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30864,16,FLEN) +NAN_BOXED(29479,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29763,16,FLEN) +NAN_BOXED(31519,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31589,16,FLEN) +NAN_BOXED(30546,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31307,16,FLEN) +NAN_BOXED(31390,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31068,16,FLEN) +NAN_BOXED(28125,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31507,16,FLEN) +NAN_BOXED(26910,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31718,16,FLEN) +NAN_BOXED(30395,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29018,16,FLEN) +NAN_BOXED(29624,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(28308,16,FLEN) +NAN_BOXED(31560,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31682,16,FLEN) +NAN_BOXED(31557,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29709,16,FLEN) +NAN_BOXED(30624,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31030,16,FLEN) +NAN_BOXED(26897,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31707,16,FLEN) +NAN_BOXED(29881,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30513,16,FLEN) +NAN_BOXED(29954,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31565,16,FLEN) +NAN_BOXED(31681,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(28447,16,FLEN) +NAN_BOXED(29410,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31701,16,FLEN) +NAN_BOXED(30807,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31050,16,FLEN) +NAN_BOXED(29732,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29930,16,FLEN) +NAN_BOXED(29665,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29821,16,FLEN) +NAN_BOXED(31708,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31030,16,FLEN) +NAN_BOXED(31013,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30270,16,FLEN) +NAN_BOXED(29927,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29968,16,FLEN) +NAN_BOXED(31430,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29911,16,FLEN) +NAN_BOXED(30040,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30881,16,FLEN) +NAN_BOXED(30915,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(25910,16,FLEN) +NAN_BOXED(29643,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30824,16,FLEN) +NAN_BOXED(27785,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30996,16,FLEN) +NAN_BOXED(29862,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30691,16,FLEN) +NAN_BOXED(31461,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30722,16,FLEN) +NAN_BOXED(31323,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31639,16,FLEN) +NAN_BOXED(29066,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31712,16,FLEN) +NAN_BOXED(31377,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(28374,16,FLEN) +NAN_BOXED(30748,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29873,16,FLEN) +NAN_BOXED(31525,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31559,16,FLEN) +NAN_BOXED(26640,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31544,16,FLEN) +NAN_BOXED(31341,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31416,16,FLEN) +NAN_BOXED(31223,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29106,16,FLEN) +NAN_BOXED(30443,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31159,16,FLEN) +NAN_BOXED(31062,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(27678,16,FLEN) +NAN_BOXED(31668,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30820,16,FLEN) +NAN_BOXED(30804,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30527,16,FLEN) +NAN_BOXED(30292,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29728,16,FLEN) +NAN_BOXED(26174,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30377,16,FLEN) +NAN_BOXED(30864,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30125,16,FLEN) +NAN_BOXED(28780,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29732,16,FLEN) +NAN_BOXED(31392,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30314,16,FLEN) +NAN_BOXED(30949,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(24487,16,FLEN) +NAN_BOXED(30778,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31024,16,FLEN) +NAN_BOXED(30466,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31193,16,FLEN) +NAN_BOXED(29599,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30632,16,FLEN) +NAN_BOXED(29490,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30843,16,FLEN) +NAN_BOXED(31552,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29798,16,FLEN) +NAN_BOXED(31019,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(27795,16,FLEN) +NAN_BOXED(30743,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(28953,16,FLEN) +NAN_BOXED(31264,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29948,16,FLEN) +NAN_BOXED(31113,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30193,16,FLEN) +NAN_BOXED(31131,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30913,16,FLEN) +NAN_BOXED(31448,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31661,16,FLEN) +NAN_BOXED(30865,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29697,16,FLEN) +NAN_BOXED(29429,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31247,16,FLEN) +NAN_BOXED(27307,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31164,16,FLEN) +NAN_BOXED(30096,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(28997,16,FLEN) +NAN_BOXED(31190,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31704,16,FLEN) +NAN_BOXED(31349,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29767,16,FLEN) +NAN_BOXED(31564,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(28787,16,FLEN) +NAN_BOXED(31283,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31046,16,FLEN) +NAN_BOXED(31129,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31588,16,FLEN) +NAN_BOXED(31684,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31339,16,FLEN) +NAN_BOXED(30444,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30004,16,FLEN) +NAN_BOXED(28682,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31659,16,FLEN) +NAN_BOXED(28575,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30343,16,FLEN) +NAN_BOXED(28557,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29680,16,FLEN) +NAN_BOXED(31230,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29202,16,FLEN) +NAN_BOXED(30468,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30980,16,FLEN) +NAN_BOXED(30935,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29339,16,FLEN) +NAN_BOXED(29837,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29790,16,FLEN) +NAN_BOXED(30895,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31095,16,FLEN) +NAN_BOXED(31315,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31688,16,FLEN) +NAN_BOXED(30812,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31447,16,FLEN) +NAN_BOXED(31270,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30241,16,FLEN) +NAN_BOXED(29834,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31349,16,FLEN) +NAN_BOXED(28557,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30812,16,FLEN) +NAN_BOXED(31671,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31688,16,FLEN) +NAN_BOXED(28766,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30868,16,FLEN) +NAN_BOXED(29946,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30132,16,FLEN) +NAN_BOXED(30777,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30482,16,FLEN) +NAN_BOXED(30512,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30307,16,FLEN) +NAN_BOXED(31298,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30687,16,FLEN) +NAN_BOXED(31021,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29317,16,FLEN) +NAN_BOXED(23534,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30920,16,FLEN) +NAN_BOXED(31500,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30741,16,FLEN) +NAN_BOXED(31716,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31404,16,FLEN) +NAN_BOXED(30346,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31717,16,FLEN) +NAN_BOXED(29922,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30965,16,FLEN) +NAN_BOXED(30782,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(23348,16,FLEN) +NAN_BOXED(30265,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30331,16,FLEN) +NAN_BOXED(31458,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31198,16,FLEN) +NAN_BOXED(31534,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30689,16,FLEN) +NAN_BOXED(31222,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31023,16,FLEN) +NAN_BOXED(30984,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30984,16,FLEN) +NAN_BOXED(30993,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31297,16,FLEN) +NAN_BOXED(31428,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31364,16,FLEN) +NAN_BOXED(30935,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29755,16,FLEN) +NAN_BOXED(31145,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30810,16,FLEN) +NAN_BOXED(28893,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30655,16,FLEN) +NAN_BOXED(30584,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30740,16,FLEN) +NAN_BOXED(31220,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30126,16,FLEN) +NAN_BOXED(31040,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30734,16,FLEN) +NAN_BOXED(31632,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30317,16,FLEN) +NAN_BOXED(31106,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29358,16,FLEN) +NAN_BOXED(29348,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29773,16,FLEN) +NAN_BOXED(27850,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30766,16,FLEN) +NAN_BOXED(30179,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31204,16,FLEN) +NAN_BOXED(29028,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31156,16,FLEN) +NAN_BOXED(31364,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30943,16,FLEN) +NAN_BOXED(29548,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29059,16,FLEN) +NAN_BOXED(31312,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30021,16,FLEN) +NAN_BOXED(29468,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(28748,16,FLEN) +NAN_BOXED(31430,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31029,16,FLEN) +NAN_BOXED(31310,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(26432,16,FLEN) +NAN_BOXED(31406,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31256,16,FLEN) +NAN_BOXED(22607,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29421,16,FLEN) +NAN_BOXED(30400,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29463,16,FLEN) +NAN_BOXED(30464,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29556,16,FLEN) +NAN_BOXED(29538,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30553,16,FLEN) +NAN_BOXED(29858,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30800,16,FLEN) +NAN_BOXED(31457,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30862,16,FLEN) +NAN_BOXED(29284,16,FLEN) +NAN_BOXED(31743,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 30*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x5_0: + .fill 30*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_0: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_1: + .fill 104*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fmsub_b18-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fmsub_b18-01.S new file mode 100644 index 000000000..1e16eb902 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fmsub_b18-01.S @@ -0,0 +1,3029 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 05:33:17 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fmsub.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fmsub.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fmsub_b18 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fmsub_b18) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x9,test_dataset_0) +RVTEST_SIGBASE(x2,signature_x2_1) + +inst_0: +// rs1 == rs2 == rs3 != rd, rs1==x0, rs2==x0, rs3==x0, rd==x28,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x0; op2:x0; op3:x0; dest:x28; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x9; val_offset:0*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x28, x0, x0, x0, dyn, 0, 0, x9, 0*FLEN/8, x15, x2, x3) + +inst_1: +// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==x30, rs2==x14, rs3==x25, rd==x26,fs1 == 0 and fe1 == 0x1e and fm1 == 0x394 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x14; op3:x25; dest:x26; op1val:0x7b94; op2val:0x0; +op3val:0xfbff; valaddr_reg:x9; val_offset:3*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x26, x30, x14, x25, dyn, 0, 0, x9, 3*FLEN/8, x15, x2, x3) + +inst_2: +// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==x21, rs2==x21, rs3==x17, rd==x14,fs1 == 0 and fe1 == 0x1a and fm1 == 0x33c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x21; op2:x21; op3:x17; dest:x14; op1val:0x6b3c; op2val:0x6b3c; +op3val:0xfbff; valaddr_reg:x9; val_offset:6*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x14, x21, x21, x17, dyn, 0, 0, x9, 6*FLEN/8, x15, x2, x3) + +inst_3: +// rd == rs2 == rs3 != rs1, rs1==x11, rs2==x20, rs3==x20, rd==x20,fs1 == 0 and fe1 == 0x1b and fm1 == 0x16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x11; op2:x20; op3:x20; dest:x20; op1val:0x6d6e; op2val:0x0; +op3val:0x0; valaddr_reg:x9; val_offset:9*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x20, x11, x20, x20, dyn, 0, 0, x9, 9*FLEN/8, x15, x2, x3) + +inst_4: +// rs1 == rs2 == rs3 == rd, rs1==x7, rs2==x7, rs3==x7, rd==x7,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x7; op2:x7; op3:x7; dest:x7; op1val:0x7aae; op2val:0x7aae; +op3val:0x7aae; valaddr_reg:x9; val_offset:12*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x7, x7, x7, x7, dyn, 0, 0, x9, 12*FLEN/8, x15, x2, x3) + +inst_5: +// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==x20, rs2==x16, rs3==x27, rd==x16,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1e2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x20; op2:x16; op3:x27; dest:x16; op1val:0x79e2; op2val:0x0; +op3val:0xfbff; valaddr_reg:x9; val_offset:15*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x16, x20, x16, x27, dyn, 0, 0, x9, 15*FLEN/8, x15, x2, x3) + +inst_6: +// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==x14, rs2==x18, rs3==x1, rd==x1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x15a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x14; op2:x18; op3:x1; dest:x1; op1val:0x795a; op2val:0x0; +op3val:0xfbff; valaddr_reg:x9; val_offset:18*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x1, x14, x18, x1, dyn, 0, 0, x9, 18*FLEN/8, x15, x2, x3) + +inst_7: +// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==x13, rs2==x4, rs3==x23, rd==x13,fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ed and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x13; op2:x4; op3:x23; dest:x13; op1val:0x74ed; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x9; val_offset:21*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x13, x13, x4, x23, dyn, 0, 0, x9, 21*FLEN/8, x15, x2, x3) + +inst_8: +// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==x1, rs2==x10, rs3==x10, rd==x5,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x1; op2:x10; op3:x10; dest:x5; op1val:0x78d8; op2val:0x8000; +op3val:0x8000; valaddr_reg:x9; val_offset:24*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x5, x1, x10, x10, dyn, 0, 0, x9, 24*FLEN/8, x15, x2, x3) + +inst_9: +// rs1 == rs2 == rd != rs3, rs1==x6, rs2==x6, rs3==x9, rd==x6,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0da and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x6; op2:x6; op3:x9; dest:x6; op1val:0x78da; op2val:0x78da; +op3val:0xfbff; valaddr_reg:x9; val_offset:27*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x6, x6, x6, x9, dyn, 0, 0, x9, 27*FLEN/8, x15, x2, x3) + +inst_10: +// rs1 == rd == rs3 != rs2, rs1==x4, rs2==x23, rs3==x4, rd==x4,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x4; op2:x23; op3:x4; dest:x4; op1val:0x78a5; op2val:0x8000; +op3val:0x78a5; valaddr_reg:x9; val_offset:30*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x4, x4, x23, x4, dyn, 0, 0, x9, 30*FLEN/8, x15, x2, x3) + +inst_11: +// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==x28, rs2==x8, rs3==x28, rd==x30,fs1 == 0 and fe1 == 0x1c and fm1 == 0x110 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x28; op2:x8; op3:x28; dest:x30; op1val:0x7110; op2val:0x8000; +op3val:0x7110; valaddr_reg:x9; val_offset:33*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x30, x28, x8, x28, dyn, 0, 0, x9, 33*FLEN/8, x15, x2, x3) + +inst_12: +// rs1==x17, rs2==x22, rs3==x12, rd==x21,fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x17; op2:x22; op3:x12; dest:x21; op1val:0x76e3; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x9; val_offset:36*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x21, x17, x22, x12, dyn, 0, 0, x9, 36*FLEN/8, x15, x2, x3) + +inst_13: +// rs1==x22, rs2==x19, rs3==x6, rd==x10,fs1 == 0 and fe1 == 0x1d and fm1 == 0x24b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x22; op2:x19; op3:x6; dest:x10; op1val:0x764b; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x9; val_offset:39*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x10, x22, x19, x6, dyn, 0, 0, x9, 39*FLEN/8, x15, x2, x3) + +inst_14: +// rs1==x5, rs2==x1, rs3==x26, rd==x23,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x5; op2:x1; op3:x26; dest:x23; op1val:0x79c8; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x9; val_offset:42*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x23, x5, x1, x26, dyn, 0, 0, x9, 42*FLEN/8, x15, x2, x3) + +inst_15: +// rs1==x25, rs2==x12, rs3==x22, rd==x31,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x25; op2:x12; op3:x22; dest:x31; op1val:0x7bf4; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x9; val_offset:45*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x25, x12, x22, dyn, 0, 0, x9, 45*FLEN/8, x15, x2, x3) +RVTEST_VALBASEUPD(x6,test_dataset_1) + +inst_16: +// rs1==x26, rs2==x9, rs3==x24, rd==x19,fs1 == 0 and fe1 == 0x1e and fm1 == 0x397 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x26; op2:x9; op3:x24; dest:x19; op1val:0x7b97; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x6; val_offset:0*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x19, x26, x9, x24, dyn, 0, 0, x6, 0*FLEN/8, x7, x2, x4) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_17: +// rs1==x29, rs2==x3, rs3==x2, rd==x0,fs1 == 0 and fe1 == 0x1e and fm1 == 0x059 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x29; op2:x3; op3:x2; dest:x0; op1val:0x7859; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x6; val_offset:3*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x0, x29, x3, x2, dyn, 0, 0, x6, 3*FLEN/8, x7, x1, x4) + +inst_18: +// rs1==x23, rs2==x28, rs3==x8, rd==x22,fs1 == 0 and fe1 == 0x1d and fm1 == 0x31d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x23; op2:x28; op3:x8; dest:x22; op1val:0x771d; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x6; val_offset:6*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x22, x23, x28, x8, dyn, 0, 0, x6, 6*FLEN/8, x7, x1, x4) + +inst_19: +// rs1==x24, rs2==x13, rs3==x31, rd==x8,fs1 == 0 and fe1 == 0x1d and fm1 == 0x04a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x24; op2:x13; op3:x31; dest:x8; op1val:0x744a; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x6; val_offset:9*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x8, x24, x13, x31, dyn, 0, 0, x6, 9*FLEN/8, x7, x1, x4) + +inst_20: +// rs1==x27, rs2==x5, rs3==x15, rd==x24,fs1 == 0 and fe1 == 0x1a and fm1 == 0x099 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x27; op2:x5; op3:x15; dest:x24; op1val:0x6899; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x6; val_offset:12*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x24, x27, x5, x15, dyn, 0, 0, x6, 12*FLEN/8, x7, x1, x4) + +inst_21: +// rs1==x31, rs2==x24, rs3==x30, rd==x15,fs1 == 0 and fe1 == 0x19 and fm1 == 0x306 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x31; op2:x24; op3:x30; dest:x15; op1val:0x6706; op2val:0x0; +op3val:0xfbff; valaddr_reg:x6; val_offset:15*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x15, x31, x24, x30, dyn, 0, 0, x6, 15*FLEN/8, x7, x1, x4) + +inst_22: +// rs1==x15, rs2==x26, rs3==x19, rd==x2,fs1 == 0 and fe1 == 0x1d and fm1 == 0x36f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x15; op2:x26; op3:x19; dest:x2; op1val:0x776f; op2val:0x0; +op3val:0xfbff; valaddr_reg:x6; val_offset:18*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x2, x15, x26, x19, dyn, 0, 0, x6, 18*FLEN/8, x7, x1, x4) + +inst_23: +// rs1==x19, rs2==x11, rs3==x21, rd==x18,fs1 == 0 and fe1 == 0x1d and fm1 == 0x117 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x19; op2:x11; op3:x21; dest:x18; op1val:0x7517; op2val:0x0; +op3val:0xfbff; valaddr_reg:x6; val_offset:21*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x18, x19, x11, x21, dyn, 0, 0, x6, 21*FLEN/8, x7, x1, x4) + +inst_24: +// rs1==x3, rs2==x31, rs3==x14, rd==x17,fs1 == 0 and fe1 == 0x1d and fm1 == 0x213 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x3; op2:x31; op3:x14; dest:x17; op1val:0x7613; op2val:0x0; +op3val:0xfbff; valaddr_reg:x6; val_offset:24*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x17, x3, x31, x14, dyn, 0, 0, x6, 24*FLEN/8, x7, x1, x4) + +inst_25: +// rs1==x2, rs2==x25, rs3==x3, rd==x27,fs1 == 0 and fe1 == 0x1e and fm1 == 0x321 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x2; op2:x25; op3:x3; dest:x27; op1val:0x7b21; op2val:0x0; +op3val:0xfbff; valaddr_reg:x6; val_offset:27*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x27, x2, x25, x3, dyn, 0, 0, x6, 27*FLEN/8, x7, x1, x4) + +inst_26: +// rs1==x18, rs2==x29, rs3==x11, rd==x3,fs1 == 0 and fe1 == 0x1e and fm1 == 0x034 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x18; op2:x29; op3:x11; dest:x3; op1val:0x7834; op2val:0x0; +op3val:0xfbff; valaddr_reg:x6; val_offset:30*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x3, x18, x29, x11, dyn, 0, 0, x6, 30*FLEN/8, x7, x1, x4) + +inst_27: +// rs1==x16, rs2==x2, rs3==x29, rd==x25,fs1 == 0 and fe1 == 0x1e and fm1 == 0x07b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x16; op2:x2; op3:x29; dest:x25; op1val:0x787b; op2val:0x0; +op3val:0xfbff; valaddr_reg:x6; val_offset:33*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x25, x16, x2, x29, dyn, 0, 0, x6, 33*FLEN/8, x7, x1, x4) + +inst_28: +// rs1==x8, rs2==x30, rs3==x13, rd==x9,fs1 == 0 and fe1 == 0x1c and fm1 == 0x38d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x8; op2:x30; op3:x13; dest:x9; op1val:0x738d; op2val:0x0; +op3val:0xfbff; valaddr_reg:x6; val_offset:36*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x9, x8, x30, x13, dyn, 0, 0, x6, 36*FLEN/8, x7, x1, x4) +RVTEST_VALBASEUPD(x3,test_dataset_2) + +inst_29: +// rs1==x9, rs2==x17, rs3==x16, rd==x12,fs1 == 0 and fe1 == 0x19 and fm1 == 0x21b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x9; op2:x17; op3:x16; dest:x12; op1val:0x661b; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x12, x9, x17, x16, dyn, 0, 0, x3, 0*FLEN/8, x5, x1, x4) + +inst_30: +// rs1==x10, rs2==x15, rs3==x5, rd==x11,fs1 == 0 and fe1 == 0x1d and fm1 == 0x133 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x10; op2:x15; op3:x5; dest:x11; op1val:0x7533; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:3*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x11, x10, x15, x5, dyn, 0, 0, x3, 3*FLEN/8, x5, x1, x4) + +inst_31: +// rs1==x12, rs2==x27, rs3==x18, rd==x29,fs1 == 0 and fe1 == 0x1c and fm1 == 0x05f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x12; op2:x27; op3:x18; dest:x29; op1val:0x705f; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x29, x12, x27, x18, dyn, 0, 0, x3, 6*FLEN/8, x5, x1, x2) + +inst_32: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x014 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7814; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:9*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 9*FLEN/8, x5, x1, x2) + +inst_33: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bfc; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 12*FLEN/8, x5, x1, x2) + +inst_34: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x164 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7964; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:15*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 15*FLEN/8, x5, x1, x2) + +inst_35: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71d1; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 18*FLEN/8, x5, x1, x2) + +inst_36: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x325 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b25; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:21*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 21*FLEN/8, x5, x1, x2) + +inst_37: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5e; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 24*FLEN/8, x5, x1, x2) + +inst_38: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1df and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79df; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:27*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 27*FLEN/8, x5, x1, x2) + +inst_39: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x33f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b3f; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 30*FLEN/8, x5, x1, x2) + +inst_40: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x219 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a19; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:33*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 33*FLEN/8, x5, x1, x2) + +inst_41: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x250 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a50; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:36*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 36*FLEN/8, x5, x1, x2) + +inst_42: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75a8; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:39*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 39*FLEN/8, x5, x1, x2) + +inst_43: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd8; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:42*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 42*FLEN/8, x5, x1, x2) + +inst_44: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bb1; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:45*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 45*FLEN/8, x5, x1, x2) + +inst_45: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x127 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7127; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:48*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 48*FLEN/8, x5, x1, x2) + +inst_46: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x207 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a07; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:51*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 51*FLEN/8, x5, x1, x2) + +inst_47: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79b7; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:54*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 54*FLEN/8, x5, x1, x2) + +inst_48: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x361 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7761; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:57*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 57*FLEN/8, x5, x1, x2) + +inst_49: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x03d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x783d; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:60*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 60*FLEN/8, x5, x1, x2) + +inst_50: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77d6; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:63*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 63*FLEN/8, x5, x1, x2) + +inst_51: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x365 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b65; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:66*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 66*FLEN/8, x5, x1, x2) + +inst_52: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7801; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:69*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 69*FLEN/8, x5, x1, x2) + +inst_53: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aa6; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:72*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 72*FLEN/8, x5, x1, x2) + +inst_54: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75a9; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:75*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 75*FLEN/8, x5, x1, x2) + +inst_55: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b0f; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:78*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 78*FLEN/8, x5, x1, x2) + +inst_56: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x331 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b31; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:81*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 81*FLEN/8, x5, x1, x2) + +inst_57: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x35f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x775f; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:84*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 84*FLEN/8, x5, x1, x2) + +inst_58: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x08a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x788a; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:87*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 87*FLEN/8, x5, x1, x2) + +inst_59: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x35b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b5b; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:90*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 90*FLEN/8, x5, x1, x2) + +inst_60: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79c9; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:93*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 93*FLEN/8, x5, x1, x2) + +inst_61: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3c8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77c8; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:96*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 96*FLEN/8, x5, x1, x2) + +inst_62: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x318 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7318; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:99*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 99*FLEN/8, x5, x1, x2) + +inst_63: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x131 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7531; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:102*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 102*FLEN/8, x5, x1, x2) + +inst_64: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x198 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7998; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:105*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 105*FLEN/8, x5, x1, x2) + +inst_65: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x14f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x714f; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:108*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 108*FLEN/8, x5, x1, x2) + +inst_66: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x342 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b42; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:111*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 111*FLEN/8, x5, x1, x2) + +inst_67: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x049 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7449; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:114*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 114*FLEN/8, x5, x1, x2) + +inst_68: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x349 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b49; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:117*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 117*FLEN/8, x5, x1, x2) + +inst_69: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74f3; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:120*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 120*FLEN/8, x5, x1, x2) + +inst_70: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ba7; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:123*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 123*FLEN/8, x5, x1, x2) + +inst_71: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79a5; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:126*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 126*FLEN/8, x5, x1, x2) + +inst_72: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x008 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7808; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:129*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 129*FLEN/8, x5, x1, x2) + +inst_73: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x023 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7823; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:132*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 132*FLEN/8, x5, x1, x2) + +inst_74: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x135 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7935; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:135*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 135*FLEN/8, x5, x1, x2) + +inst_75: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78b3; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:138*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 138*FLEN/8, x5, x1, x2) + +inst_76: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74fc; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:141*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 141*FLEN/8, x5, x1, x2) + +inst_77: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2a5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72a5; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:144*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 144*FLEN/8, x5, x1, x2) + +inst_78: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x017 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7817; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:147*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 147*FLEN/8, x5, x1, x2) + +inst_79: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x378 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b78; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:150*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 150*FLEN/8, x5, x1, x2) + +inst_80: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fb; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:153*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 153*FLEN/8, x5, x1, x2) + +inst_81: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0d2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6cd2; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:156*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 156*FLEN/8, x5, x1, x2) + +inst_82: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8f; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:159*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 159*FLEN/8, x5, x1, x2) + +inst_83: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ce and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79ce; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:162*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 162*FLEN/8, x5, x1, x2) + +inst_84: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x341 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b41; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:165*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 165*FLEN/8, x5, x1, x2) + +inst_85: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x21f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x721f; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:168*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 168*FLEN/8, x5, x1, x2) + +inst_86: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f4; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:171*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 171*FLEN/8, x5, x1, x2) + +inst_87: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x384 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6b84; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:174*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 174*FLEN/8, x5, x1, x2) + +inst_88: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x138 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7938; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:177*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 177*FLEN/8, x5, x1, x2) + +inst_89: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x05e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x745e; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:180*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 180*FLEN/8, x5, x1, x2) + +inst_90: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x33f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x733f; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:183*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 183*FLEN/8, x5, x1, x2) + +inst_91: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x300 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b00; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:186*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 186*FLEN/8, x5, x1, x2) + +inst_92: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2cc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ecc; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:189*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 189*FLEN/8, x5, x1, x2) + +inst_93: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x782d; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:192*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 192*FLEN/8, x5, x1, x2) + +inst_94: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ad4; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:195*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 195*FLEN/8, x5, x1, x2) + +inst_95: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3d4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73d4; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:198*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 198*FLEN/8, x5, x1, x2) + +inst_96: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72bb; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:201*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 201*FLEN/8, x5, x1, x2) + +inst_97: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b0a; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:204*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 204*FLEN/8, x5, x1, x2) + +inst_98: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2c3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76c3; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:207*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 207*FLEN/8, x5, x1, x2) + +inst_99: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79bb; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:210*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 210*FLEN/8, x5, x1, x2) + +inst_100: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x014 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6814; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:213*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 213*FLEN/8, x5, x1, x2) + +inst_101: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1cb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75cb; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:216*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 216*FLEN/8, x5, x1, x2) + +inst_102: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x17f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x717f; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:219*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 219*FLEN/8, x5, x1, x2) + +inst_103: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x161 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7961; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:222*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 222*FLEN/8, x5, x1, x2) + +inst_104: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x14d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d4d; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:225*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 225*FLEN/8, x5, x1, x2) + +inst_105: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ba1; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:228*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 228*FLEN/8, x5, x1, x2) + +inst_106: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x27d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x667d; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:231*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 231*FLEN/8, x5, x1, x2) + +inst_107: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79d5; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:234*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 234*FLEN/8, x5, x1, x2) + +inst_108: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x16a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x656a; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:237*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 237*FLEN/8, x5, x1, x2) + +inst_109: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x016 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7416; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:240*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 240*FLEN/8, x5, x1, x2) + +inst_110: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x280 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a80; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:243*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 243*FLEN/8, x5, x1, x2) + +inst_111: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x106 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7106; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:246*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 246*FLEN/8, x5, x1, x2) + +inst_112: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1e0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71e0; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:249*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 249*FLEN/8, x5, x1, x2) + +inst_113: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x187 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7987; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:252*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 252*FLEN/8, x5, x1, x2) + +inst_114: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x22a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x762a; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:255*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 255*FLEN/8, x5, x1, x2) + +inst_115: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x186 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6986; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:258*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 258*FLEN/8, x5, x1, x2) + +inst_116: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bea; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:261*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 261*FLEN/8, x5, x1, x2) + +inst_117: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0d7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70d7; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:264*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 264*FLEN/8, x5, x1, x2) + +inst_118: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x0a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x68a4; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:267*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 267*FLEN/8, x5, x1, x2) + +inst_119: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x181 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7581; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:270*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 270*FLEN/8, x5, x1, x2) + +inst_120: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78eb; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:273*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 273*FLEN/8, x5, x1, x2) + +inst_121: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ef and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79ef; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:276*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 276*FLEN/8, x5, x1, x2) + +inst_122: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x33c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f3c; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:279*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 279*FLEN/8, x5, x1, x2) + +inst_123: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x164 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7564; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:282*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 282*FLEN/8, x5, x1, x2) + +inst_124: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x3e3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x67e3; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:285*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 285*FLEN/8, x5, x1, x2) + +inst_125: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x32c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x772c; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:288*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 288*FLEN/8, x5, x1, x2) + +inst_126: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a1f; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:291*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 291*FLEN/8, x5, x1, x2) + +inst_127: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ea and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79ea; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:294*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 294*FLEN/8, x5, x1, x2) + +inst_128: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x336 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b36; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:297*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 297*FLEN/8, x5, x1, x2) + +inst_129: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a0a; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:300*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 300*FLEN/8, x5, x1, x2) + +inst_130: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ae5; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:303*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 303*FLEN/8, x5, x1, x2) + +inst_131: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79a3; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:306*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 306*FLEN/8, x5, x1, x2) + +inst_132: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x38f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x778f; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:309*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 309*FLEN/8, x5, x1, x2) + +inst_133: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x336 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7336; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:312*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 312*FLEN/8, x5, x1, x2) + +inst_134: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x148 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7948; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:315*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 315*FLEN/8, x5, x1, x2) + +inst_135: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x10e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x750e; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:318*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 318*FLEN/8, x5, x1, x2) + +inst_136: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x287 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e87; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:321*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 321*FLEN/8, x5, x1, x2) + +inst_137: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x329 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7729; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:324*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 324*FLEN/8, x5, x1, x2) + +inst_138: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7afe; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:327*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 327*FLEN/8, x5, x1, x2) + +inst_139: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x014 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7014; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:330*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 330*FLEN/8, x5, x1, x2) + +inst_140: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ad and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78ad; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:333*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 333*FLEN/8, x5, x1, x2) + +inst_141: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x248 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7648; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:336*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 336*FLEN/8, x5, x1, x2) + +inst_142: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x01d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x781d; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:339*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 339*FLEN/8, x5, x1, x2) + +inst_143: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x099 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7099; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:342*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 342*FLEN/8, x5, x1, x2) + +inst_144: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ac and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bac; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:345*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 345*FLEN/8, x5, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_145: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x024 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7424; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:348*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 348*FLEN/8, x5, x1, x2) + +inst_146: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78d8; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:351*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 351*FLEN/8, x5, x1, x2) + +inst_147: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76b6; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:354*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 354*FLEN/8, x5, x1, x2) + +inst_148: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x09e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x649e; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:357*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 357*FLEN/8, x5, x1, x2) + +inst_149: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x076 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7876; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:360*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 360*FLEN/8, x5, x1, x2) + +inst_150: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x07f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x707f; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:363*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 363*FLEN/8, x5, x1, x2) + +inst_151: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x344 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6b44; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:366*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 366*FLEN/8, x5, x1, x2) + +inst_152: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x04b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x684b; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:369*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 369*FLEN/8, x5, x1, x2) + +inst_153: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x222 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e22; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:372*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 372*FLEN/8, x5, x1, x2) + +inst_154: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x114 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7914; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:375*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 375*FLEN/8, x5, x1, x2) + +inst_155: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x010 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7810; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:378*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 378*FLEN/8, x5, x1, x2) + +inst_156: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3dd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bdd; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:381*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 381*FLEN/8, x5, x1, x2) + +inst_157: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x378 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b78; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:384*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 384*FLEN/8, x5, x1, x2) + +inst_158: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bf3; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:387*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 387*FLEN/8, x5, x1, x2) + +inst_159: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x36f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x736f; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:390*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 390*FLEN/8, x5, x1, x2) + +inst_160: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x771c; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:393*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 393*FLEN/8, x5, x1, x2) + +inst_161: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7402; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:396*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 396*FLEN/8, x5, x1, x2) + +inst_162: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ba and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78ba; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:399*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 399*FLEN/8, x5, x1, x2) + +inst_163: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fd; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:402*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 402*FLEN/8, x5, x1, x2) + +inst_164: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x266 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a66; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:405*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 405*FLEN/8, x5, x1, x2) + +inst_165: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ac and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79ac; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:408*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 408*FLEN/8, x5, x1, x2) + +inst_166: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x01a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x741a; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:411*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 411*FLEN/8, x5, x1, x2) + +inst_167: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2c3 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x1e9 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76c3; op2val:0x19e9; +op3val:0xfbff; valaddr_reg:x3; val_offset:414*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 414*FLEN/8, x5, x1, x2) + +inst_168: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x035 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x0c0 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7835; op2val:0x18c0; +op3val:0xfbff; valaddr_reg:x3; val_offset:417*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 417*FLEN/8, x5, x1, x2) + +inst_169: +// fs1 == 0 and fe1 == 0x17 and fm1 == 0x0f4 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x009 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5cf4; op2val:0x3409; +op3val:0xfbff; valaddr_reg:x3; val_offset:420*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 420*FLEN/8, x5, x1, x2) + +inst_170: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x08b and fs2 == 0 and fe2 == 0x0a and fm2 == 0x066 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x688b; op2val:0x2866; +op3val:0xfbff; valaddr_reg:x3; val_offset:423*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 423*FLEN/8, x5, x1, x2) + +inst_171: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x289 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x21e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7689; op2val:0x1a1e; +op3val:0xfbff; valaddr_reg:x3; val_offset:426*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 426*FLEN/8, x5, x1, x2) + +inst_172: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x31c and fs2 == 0 and fe2 == 0x08 and fm2 == 0x19f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f1c; op2val:0x219f; +op3val:0xfbff; valaddr_reg:x3; val_offset:429*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 429*FLEN/8, x5, x1, x2) + +inst_173: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c9 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x2e9 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79c9; op2val:0x16e9; +op3val:0xfbff; valaddr_reg:x3; val_offset:432*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 432*FLEN/8, x5, x1, x2) + +inst_174: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3b4 and fs2 == 1 and fe2 == 0x07 and fm2 == 0x131 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73b4; op2val:0x9d31; +op3val:0xfbff; valaddr_reg:x3; val_offset:435*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 435*FLEN/8, x5, x1, x2) + +inst_175: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x262 and fs2 == 1 and fe2 == 0x08 and fm2 == 0x244 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e62; op2val:0xa244; +op3val:0xfbff; valaddr_reg:x3; val_offset:438*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 438*FLEN/8, x5, x1, x2) + +inst_176: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1d0 and fs2 == 1 and fe2 == 0x07 and fm2 == 0x2e1 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71d0; op2val:0x9ee1; +op3val:0xfbff; valaddr_reg:x3; val_offset:441*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 441*FLEN/8, x5, x1, x2) + +inst_177: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x367 and fs2 == 1 and fe2 == 0x07 and fm2 == 0x166 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7367; op2val:0x9d66; +op3val:0xfbff; valaddr_reg:x3; val_offset:444*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 444*FLEN/8, x5, x1, x2) + +inst_178: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2f3 and fs2 == 1 and fe2 == 0x07 and fm2 == 0x1c0 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72f3; op2val:0x9dc0; +op3val:0xfbff; valaddr_reg:x3; val_offset:447*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 447*FLEN/8, x5, x1, x2) + +inst_179: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x029 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x0cd and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7829; op2val:0x98cd; +op3val:0xfbff; valaddr_reg:x3; val_offset:450*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 450*FLEN/8, x5, x1, x2) + +inst_180: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x36d and fs2 == 1 and fe2 == 0x06 and fm2 == 0x162 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x776d; op2val:0x9962; +op3val:0xfbff; valaddr_reg:x3; val_offset:453*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 453*FLEN/8, x5, x1, x2) + +inst_181: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f4 and fs2 == 1 and fe2 == 0x07 and fm2 == 0x009 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74f4; op2val:0x9c09; +op3val:0xfbff; valaddr_reg:x3; val_offset:456*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 456*FLEN/8, x5, x1, x2) + +inst_182: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x121 and fs2 == 1 and fe2 == 0x05 and fm2 == 0x3cb and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7921; op2val:0x97cb; +op3val:0xfbff; valaddr_reg:x3; val_offset:459*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 459*FLEN/8, x5, x1, x2) + +inst_183: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2cb and fs2 == 1 and fe2 == 0x07 and fm2 == 0x1e2 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72cb; op2val:0x9de2; +op3val:0xfbff; valaddr_reg:x3; val_offset:462*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 462*FLEN/8, x5, x1, x2) + +inst_184: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x33f and fs2 == 1 and fe2 == 0x05 and fm2 == 0x184 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b3f; op2val:0x9584; +op3val:0xfbff; valaddr_reg:x3; val_offset:465*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 465*FLEN/8, x5, x1, x2) + +inst_185: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b3 and fs2 == 1 and fe2 == 0x05 and fm2 == 0x131 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bb3; op2val:0x9531; +op3val:0xfbff; valaddr_reg:x3; val_offset:468*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 468*FLEN/8, x5, x1, x2) + +inst_186: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d4 and fs2 == 1 and fe2 == 0x05 and fm2 == 0x2dc and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79d4; op2val:0x96dc; +op3val:0xfbff; valaddr_reg:x3; val_offset:471*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 471*FLEN/8, x5, x1, x2) + +inst_187: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x06 and fm2 == 0x1c4 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76ef; op2val:0x99c4; +op3val:0xfbff; valaddr_reg:x3; val_offset:474*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 474*FLEN/8, x5, x1, x2) + +inst_188: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x017 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x0e3 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7817; op2val:0x18e3; +op3val:0xfbff; valaddr_reg:x3; val_offset:477*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 477*FLEN/8, x5, x1, x2) + +inst_189: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a5 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x04d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78a5; op2val:0x184d; +op3val:0xfbff; valaddr_reg:x3; val_offset:480*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 480*FLEN/8, x5, x1, x2) + +inst_190: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x28e and fs2 == 0 and fe2 == 0x09 and fm2 == 0x219 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6a8e; op2val:0x2619; +op3val:0xfbff; valaddr_reg:x3; val_offset:483*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 483*FLEN/8, x5, x1, x2) + +inst_191: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2af and fs2 == 0 and fe2 == 0x06 and fm2 == 0x1fb and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76af; op2val:0x19fb; +op3val:0xfbff; valaddr_reg:x3; val_offset:486*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 486*FLEN/8, x5, x1, x2) + +inst_192: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x032 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x0c3 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7832; op2val:0x18c3; +op3val:0xfbff; valaddr_reg:x3; val_offset:489*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 489*FLEN/8, x5, x1, x2) + +inst_193: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1cb and fs2 == 0 and fe2 == 0x07 and fm2 == 0x2e6 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71cb; op2val:0x1ee6; +op3val:0xfbff; valaddr_reg:x3; val_offset:492*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 492*FLEN/8, x5, x1, x2) + +inst_194: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x200 and fs2 == 0 and fe2 == 0x08 and fm2 == 0x2aa and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e00; op2val:0x22aa; +op3val:0xfbff; valaddr_reg:x3; val_offset:495*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 495*FLEN/8, x5, x1, x2) + +inst_195: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a6b; op2val:0xe; +op3val:0xfbff; valaddr_reg:x3; val_offset:498*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 498*FLEN/8, x5, x1, x2) + +inst_196: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x020 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75db; op2val:0x20; +op3val:0xfbff; valaddr_reg:x3; val_offset:501*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 501*FLEN/8, x5, x1, x2) + +inst_197: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x026 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x017 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7826; op2val:0x17; +op3val:0xfbff; valaddr_reg:x3; val_offset:504*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 504*FLEN/8, x5, x1, x2) + +inst_198: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x35e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b5e; op2val:0xd; +op3val:0xfbff; valaddr_reg:x3; val_offset:507*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 507*FLEN/8, x5, x1, x2) + +inst_199: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x013 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e1; op2val:0x13; +op3val:0xfbff; valaddr_reg:x3; val_offset:510*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 510*FLEN/8, x5, x1, x2) + +inst_200: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x029 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74a1; op2val:0x29; +op3val:0xfbff; valaddr_reg:x3; val_offset:513*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 513*FLEN/8, x5, x1, x2) + +inst_201: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00c and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bdd; op2val:0xc; +op3val:0xfbff; valaddr_reg:x3; val_offset:516*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 516*FLEN/8, x5, x1, x2) + +inst_202: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1f3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x020 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75f3; op2val:0x8020; +op3val:0xfbff; valaddr_reg:x3; val_offset:519*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 519*FLEN/8, x5, x1, x2) + +inst_203: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x0e1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x275 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x64e1; op2val:0x8275; +op3val:0xfbff; valaddr_reg:x3; val_offset:522*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 522*FLEN/8, x5, x1, x2) + +inst_204: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x17a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x011 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x797a; op2val:0x8011; +op3val:0xfbff; valaddr_reg:x3; val_offset:525*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 525*FLEN/8, x5, x1, x2) + +inst_205: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x278 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x076 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e78; op2val:0x8076; +op3val:0xfbff; valaddr_reg:x3; val_offset:528*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 528*FLEN/8, x5, x1, x2) + +inst_206: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0e4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x027 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74e4; op2val:0x8027; +op3val:0xfbff; valaddr_reg:x3; val_offset:531*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 531*FLEN/8, x5, x1, x2) + +inst_207: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ab8; op2val:0x800e; +op3val:0xfbff; valaddr_reg:x3; val_offset:534*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 534*FLEN/8, x5, x1, x2) + +inst_208: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x160 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x011 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7960; op2val:0x8011; +op3val:0xfbff; valaddr_reg:x3; val_offset:537*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 537*FLEN/8, x5, x1, x2) + +inst_209: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x006 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fa and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6406; op2val:0x82fa; +op3val:0xfbff; valaddr_reg:x3; val_offset:540*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 540*FLEN/8, x5, x1, x2) + +inst_210: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x338 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x01a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7738; op2val:0x801a; +op3val:0xfbff; valaddr_reg:x3; val_offset:543*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 543*FLEN/8, x5, x1, x2) + +inst_211: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x291 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x01d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7691; op2val:0x801d; +op3val:0xfbff; valaddr_reg:x3; val_offset:546*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 546*FLEN/8, x5, x1, x2) + +inst_212: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3c5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x018 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77c5; op2val:0x8018; +op3val:0xfbff; valaddr_reg:x3; val_offset:549*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 549*FLEN/8, x5, x1, x2) + +inst_213: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2a9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x039 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72a9; op2val:0x8039; +op3val:0xfbff; valaddr_reg:x3; val_offset:552*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 552*FLEN/8, x5, x1, x2) + +inst_214: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x014 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78b5; op2val:0x8014; +op3val:0xfbff; valaddr_reg:x3; val_offset:555*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 555*FLEN/8, x5, x1, x2) + +inst_215: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0b8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a2 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6cb8; op2val:0x80a2; +op3val:0xfbff; valaddr_reg:x3; val_offset:558*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 558*FLEN/8, x5, x1, x2) + +inst_216: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x08c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x02a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x748c; op2val:0x2a; +op3val:0xfbff; valaddr_reg:x3; val_offset:561*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 561*FLEN/8, x5, x1, x2) + +inst_217: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1f6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x020 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75f6; op2val:0x20; +op3val:0xfbff; valaddr_reg:x3; val_offset:564*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 564*FLEN/8, x5, x1, x2) + +inst_218: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00c and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b7a; op2val:0xc; +op3val:0xfbff; valaddr_reg:x3; val_offset:567*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 567*FLEN/8, x5, x1, x2) + +inst_219: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0e5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x09c and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ce5; op2val:0x9c; +op3val:0xfbff; valaddr_reg:x3; val_offset:570*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 570*FLEN/8, x5, x1, x2) + +inst_220: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x209 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a09; op2val:0xf; +op3val:0xfbff; valaddr_reg:x3; val_offset:573*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 573*FLEN/8, x5, x1, x2) + +inst_221: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x227 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7227; op2val:0x3e; +op3val:0xfbff; valaddr_reg:x3; val_offset:576*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 576*FLEN/8, x5, x1, x2) + +inst_222: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x091 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x015 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7891; op2val:0x15; +op3val:0xfbff; valaddr_reg:x3; val_offset:579*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 579*FLEN/8, x5, x1, x2) + +inst_223: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x243 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x11a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7643; op2val:0x411a; +op3val:0xfbff; valaddr_reg:x3; val_offset:582*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 582*FLEN/8, x5, x1, x2) + +inst_224: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x368 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x051 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7768; op2val:0xc051; +op3val:0xfbff; valaddr_reg:x3; val_offset:585*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 585*FLEN/8, x5, x1, x2) + +inst_225: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x206 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x14e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a06; op2val:0x3d4e; +op3val:0xfbff; valaddr_reg:x3; val_offset:588*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 588*FLEN/8, x5, x1, x2) + +inst_226: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x251 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x110 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7651; op2val:0xc110; +op3val:0xfbff; valaddr_reg:x3; val_offset:591*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 591*FLEN/8, x5, x1, x2) + +inst_227: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3c9 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x01b and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6fc9; op2val:0x481b; +op3val:0xfbff; valaddr_reg:x3; val_offset:594*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 594*FLEN/8, x5, x1, x2) + +inst_228: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3ca and fs2 == 1 and fe2 == 0x12 and fm2 == 0x01b and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6fca; op2val:0xc81b; +op3val:0xfbff; valaddr_reg:x3; val_offset:597*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 597*FLEN/8, x5, x1, x2) + +inst_229: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x126 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x235 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d26; op2val:0x4a35; +op3val:0xfbff; valaddr_reg:x3; val_offset:600*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 600*FLEN/8, x5, x1, x2) + +inst_230: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2cc and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0b4 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7acc; op2val:0xbcb4; +op3val:0xfbff; valaddr_reg:x3; val_offset:603*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 603*FLEN/8, x5, x1, x2) + +inst_231: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x120 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x23d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7920; op2val:0x3e3d; +op3val:0xfbff; valaddr_reg:x3; val_offset:606*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 606*FLEN/8, x5, x1, x2) + +inst_232: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ac and fs2 == 1 and fe2 == 0x0f and fm2 == 0x02b and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bac; op2val:0xbc2b; +op3val:0xfbff; valaddr_reg:x3; val_offset:609*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 609*FLEN/8, x5, x1, x2) + +inst_233: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x189 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1c6 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7989; op2val:0x3dc6; +op3val:0xfbff; valaddr_reg:x3; val_offset:612*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 612*FLEN/8, x5, x1, x2) + +inst_234: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x250 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x110 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6650; op2val:0xd110; +op3val:0xfbff; valaddr_reg:x3; val_offset:615*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 615*FLEN/8, x5, x1, x2) + +inst_235: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x145 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x211 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7945; op2val:0x3e11; +op3val:0xfbff; valaddr_reg:x3; val_offset:618*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 618*FLEN/8, x5, x1, x2) + +inst_236: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x236 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x125 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a36; op2val:0xbd25; +op3val:0xfbff; valaddr_reg:x3; val_offset:621*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 621*FLEN/8, x5, x1, x2) + +inst_237: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c9 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x187 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79c9; op2val:0x3187; +op3val:0xfbff; valaddr_reg:x3; val_offset:624*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 624*FLEN/8, x5, x1, x2) + +inst_238: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3f6 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x004 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77f6; op2val:0xb404; +op3val:0xfbff; valaddr_reg:x3; val_offset:627*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 627*FLEN/8, x5, x1, x2) + +inst_239: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1b7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x197 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75b7; op2val:0x3997; +op3val:0xfbff; valaddr_reg:x3; val_offset:630*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 630*FLEN/8, x5, x1, x2) + +inst_240: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x34f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x060 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x774f; op2val:0xb860; +op3val:0xfbff; valaddr_reg:x3; val_offset:633*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 633*FLEN/8, x5, x1, x2) + +inst_241: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x262 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x102 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a62; op2val:0x3902; +op3val:0xfbff; valaddr_reg:x3; val_offset:636*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 636*FLEN/8, x5, x1, x2) + +inst_242: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x04d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x36f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x744d; op2val:0xbf6f; +op3val:0xfbff; valaddr_reg:x3; val_offset:639*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 639*FLEN/8, x5, x1, x2) + +inst_243: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x035 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x399 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7835; op2val:0x3f99; +op3val:0xfbff; valaddr_reg:x3; val_offset:642*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 642*FLEN/8, x5, x1, x2) + +inst_244: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a3 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x030 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77a3; op2val:0xc030; +op3val:0xfbff; valaddr_reg:x3; val_offset:645*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 645*FLEN/8, x5, x1, x2) + +inst_245: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a2 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x030 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ba2; op2val:0x4030; +op3val:0xfbff; valaddr_reg:x3; val_offset:648*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 648*FLEN/8, x5, x1, x2) + +inst_246: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26e and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0f9 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a6e; op2val:0xc0f9; +op3val:0xfbff; valaddr_reg:x3; val_offset:651*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 651*FLEN/8, x5, x1, x2) + +inst_247: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x373 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x04a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b73; op2val:0x444a; +op3val:0xfbff; valaddr_reg:x3; val_offset:654*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 654*FLEN/8, x5, x1, x2) + +inst_248: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2af and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0c8 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aaf; op2val:0xc4c8; +op3val:0xfbff; valaddr_reg:x3; val_offset:657*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 657*FLEN/8, x5, x1, x2) + +inst_249: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0be and fs2 == 0 and fe2 == 0x13 and fm2 == 0x2bd and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74be; op2val:0x4ebd; +op3val:0xfbff; valaddr_reg:x3; val_offset:660*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 660*FLEN/8, x5, x1, x2) + +inst_250: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x368 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x051 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7368; op2val:0xd051; +op3val:0xfbff; valaddr_reg:x3; val_offset:663*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 663*FLEN/8, x5, x1, x2) + +inst_251: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77d1; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:666*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 666*FLEN/8, x5, x1, x2) + +inst_252: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x026 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7426; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:669*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 669*FLEN/8, x5, x1, x2) + +inst_253: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2d6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76d6; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:672*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 672*FLEN/8, x5, x1, x2) + +inst_254: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x796e; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:675*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 675*FLEN/8, x5, x1, x2) + +inst_255: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x358 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b58; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:678*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 678*FLEN/8, x5, x1, x2) + +inst_256: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0af and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78af; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:681*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 681*FLEN/8, x5, x1, x2) + +inst_257: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8a; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:684*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 684*FLEN/8, x5, x1, x2) + +inst_258: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x223 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e23; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:687*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 687*FLEN/8, x5, x1, x2) + +inst_259: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75b1; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:690*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 690*FLEN/8, x5, x1, x2) + +inst_260: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3fa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bfa; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:693*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 693*FLEN/8, x5, x1, x2) + +inst_261: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0af and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70af; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:696*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 696*FLEN/8, x5, x1, x2) + +inst_262: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76aa; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:699*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 699*FLEN/8, x5, x1, x2) + +inst_263: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x046 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c46; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:702*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 702*FLEN/8, x5, x1, x2) + +inst_264: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x183 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d83; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:705*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 705*FLEN/8, x5, x1, x2) + +inst_265: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x329 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b29; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:708*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 708*FLEN/8, x5, x1, x2) + +inst_266: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7be7; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:711*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 711*FLEN/8, x5, x1, x2) + +inst_267: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x792e; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:714*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 714*FLEN/8, x5, x1, x2) + +inst_268: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x01c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x701c; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:717*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 717*FLEN/8, x5, x1, x2) + +inst_269: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74bd; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:720*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 720*FLEN/8, x5, x1, x2) + +inst_270: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x369 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7369; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:723*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 723*FLEN/8, x5, x1, x2) + +inst_271: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x795c; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:726*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 726*FLEN/8, x5, x1, x2) + +inst_272: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x172 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7972; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:729*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 729*FLEN/8, x5, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_2) + +inst_273: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x304 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7704; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:732*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 732*FLEN/8, x5, x1, x2) + +inst_274: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x030 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7830; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:735*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 735*FLEN/8, x5, x1, x2) + +inst_275: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x32b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f2b; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:738*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 738*FLEN/8, x5, x1, x2) + +inst_276: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x053 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7853; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:741*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 741*FLEN/8, x5, x1, x2) + +inst_277: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x398 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b98; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:744*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 744*FLEN/8, x5, x1, x2) + +inst_278: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a0b; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:747*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 747*FLEN/8, x5, x1, x2) + +inst_279: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x226 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e26; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:750*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 750*FLEN/8, x5, x1, x2) + +inst_280: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x021 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7821; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:753*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 753*FLEN/8, x5, x1, x2) + +inst_281: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79b8; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:756*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 756*FLEN/8, x5, x1, x2) + +inst_282: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x01d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x741d; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:759*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 759*FLEN/8, x5, x1, x2) + +inst_283: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ba5; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:762*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 762*FLEN/8, x5, x1, x2) + +inst_284: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x33c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6b3c; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:765*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 765*FLEN/8, x5, x1, x2) + +inst_285: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d6e; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:768*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 768*FLEN/8, x5, x1, x2) + +inst_286: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aae; op2val:0x0; +op3val:0xfbff; valaddr_reg:x3; val_offset:771*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 771*FLEN/8, x5, x1, x2) + +inst_287: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78d8; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:774*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 774*FLEN/8, x5, x1, x2) + +inst_288: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0da and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78da; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:777*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 777*FLEN/8, x5, x1, x2) + +inst_289: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78a5; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:780*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 780*FLEN/8, x5, x1, x2) + +inst_290: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x110 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7110; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:783*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 783*FLEN/8, x5, x1, x2) + +inst_291: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x059 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7859; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x3; val_offset:786*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 786*FLEN/8, x5, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31636,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(27452,32,FLEN) +NAN_BOXED(27452,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28014,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31406,32,FLEN) +NAN_BOXED(31406,32,FLEN) +NAN_BOXED(31406,16,FLEN) +NAN_BOXED(31202,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31066,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29933,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30936,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(30938,32,FLEN) +NAN_BOXED(30938,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30885,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(30885,16,FLEN) +NAN_BOXED(28944,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(28944,16,FLEN) +NAN_BOXED(30435,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30283,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31176,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31732,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +test_dataset_1: +NAN_BOXED(31639,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30809,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30493,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29770,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) 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+NAN_BOXED(64511,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x2_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_1: + .fill 34*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_0: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_2: + .fill 38*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fmsub_b2-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fmsub_b2-01.S new file mode 100644 index 000000000..9bfc20462 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fmsub_b2-01.S @@ -0,0 +1,1406 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 05:33:17 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fmsub.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fmsub.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fmsub_b2 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fmsub_b2) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x10,test_dataset_0) +RVTEST_SIGBASE(x13,signature_x13_1) + +inst_0: +// rs1 == rs2 == rs3 != rd, rs1==x19, rs2==x19, rs3==x19, rd==x23,fs1 == 0 and fe1 == 0x00 and fm1 == 0x02a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x014 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x19; op2:x19; op3:x19; dest:x23; op1val:0x2a; op2val:0x2a; +op3val:0x2a; valaddr_reg:x10; val_offset:0*FLEN/8; rmval:dyn; +testreg:x15; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x23, x19, x19, x19, dyn, 0, 0, x10, 0*FLEN/8, x12, x13, x15) + +inst_1: +// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==x4, rs2==x21, rs3==x17, rd==x24,fs1 == 0 and fe1 == 0x00 and fm1 == 0x033 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2be and fs3 == 0 and fe3 == 0x00 and fm3 == 0x054 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x4; op2:x21; op3:x17; dest:x24; op1val:0x33; op2val:0x3ebe; +op3val:0x54; valaddr_reg:x10; val_offset:3*FLEN/8; rmval:dyn; +testreg:x15; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x24, x4, x21, x17, dyn, 0, 0, x10, 3*FLEN/8, x12, x13, x15) + +inst_2: +// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==x0, rs2==x0, rs3==x23, rd==x8,fs1 == 0 and fe1 == 0x00 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x0; op2:x0; op3:x23; dest:x8; op1val:0x0; op2val:0x0; +op3val:0xa; valaddr_reg:x10; val_offset:6*FLEN/8; rmval:dyn; +testreg:x15; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x8, x0, x0, x23, dyn, 0, 0, x10, 6*FLEN/8, x12, x13, x15) + +inst_3: +// rd == rs2 == rs3 != rs1, rs1==x25, rs2==x3, rs3==x3, rd==x3,fs1 == 0 and fe1 == 0x00 and fm1 == 0x045 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0de and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x25; op2:x3; op3:x3; dest:x3; op1val:0x45; op2val:0x34de; +op3val:0x34de; valaddr_reg:x10; val_offset:9*FLEN/8; rmval:dyn; +testreg:x15; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x3, x25, x3, x3, dyn, 0, 0, x10, 9*FLEN/8, x12, x13, x15) + +inst_4: +// rs1 == rs2 == rs3 == rd, rs1==x11, rs2==x11, rs3==x11, rd==x11,fs1 == 0 and fe1 == 0x00 and fm1 == 0x02f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3be and fs3 == 0 and fe3 == 0x00 and fm3 == 0x04b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x11; op2:x11; op3:x11; dest:x11; op1val:0x2f; op2val:0x2f; +op3val:0x2f; valaddr_reg:x10; val_offset:12*FLEN/8; rmval:dyn; +testreg:x15; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x11, x11, x11, x11, dyn, 0, 0, x10, 12*FLEN/8, x12, x13, x15) + +inst_5: +// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==x1, rs2==x29, rs3==x0, rd==x29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x008 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x210 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x041 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x1; op2:x29; op3:x0; dest:x29; op1val:0x8; op2val:0x4a10; +op3val:0x0; valaddr_reg:x10; val_offset:15*FLEN/8; rmval:dyn; +testreg:x15; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x29, x1, x29, x0, dyn, 0, 0, x10, 15*FLEN/8, x12, x13, x15) + +inst_6: +// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==x31, rs2==x17, rs3==x4, rd==x4,fs1 == 0 and fe1 == 0x00 and fm1 == 0x01c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0ed and fs3 == 0 and fe3 == 0x00 and fm3 == 0x005 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x31; op2:x17; op3:x4; dest:x4; op1val:0x1c; op2val:0x40ed; +op3val:0x5; valaddr_reg:x10; val_offset:18*FLEN/8; rmval:dyn; +testreg:x15; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x4, x31, x17, x4, dyn, 0, 0, x10, 18*FLEN/8, x12, x13, x15) + +inst_7: +// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==x6, rs2==x7, rs3==x26, rd==x6,fs1 == 0 and fe1 == 0x00 and fm1 == 0x00c and fs2 == 0 and fe2 == 0x12 and fm2 == 0x3aa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x038 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x6; op2:x7; op3:x26; dest:x6; op1val:0xc; op2val:0x4baa; +op3val:0x38; valaddr_reg:x10; val_offset:21*FLEN/8; rmval:dyn; +testreg:x15; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x6, x6, x7, x26, dyn, 0, 0, x10, 21*FLEN/8, x12, x13, x15) + +inst_8: +// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==x9, rs2==x27, rs3==x27, rd==x5,fs1 == 0 and fe1 == 0x00 and fm1 == 0x036 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0e8 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x009 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x9; op2:x27; op3:x27; dest:x5; op1val:0x36; op2val:0x44e8; +op3val:0x44e8; valaddr_reg:x10; val_offset:24*FLEN/8; rmval:dyn; +testreg:x15; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x5, x9, x27, x27, dyn, 0, 0, x10, 24*FLEN/8, x12, x13, x15) + +inst_9: +// rs1 == rs2 == rd != rs3, rs1==x2, rs2==x2, rs3==x16, rd==x2,fs1 == 0 and fe1 == 0x00 and fm1 == 0x01f and fs2 == 0 and fe2 == 0x13 and fm2 == 0x039 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x2; op2:x2; op3:x16; dest:x2; op1val:0x1f; op2val:0x1f; +op3val:0xc; valaddr_reg:x10; val_offset:27*FLEN/8; rmval:dyn; +testreg:x15; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x2, x2, x2, x16, dyn, 0, 0, x10, 27*FLEN/8, x12, x13, x15) + +inst_10: +// rs1 == rd == rs3 != rs2, rs1==x30, rs2==x9, rs3==x30, rd==x30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x047 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x215 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x037 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x9; op3:x30; dest:x30; op1val:0x47; op2val:0x3a15; +op3val:0x47; valaddr_reg:x10; val_offset:30*FLEN/8; rmval:dyn; +testreg:x15; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x30, x30, x9, x30, dyn, 0, 0, x10, 30*FLEN/8, x12, x13, x15) + +inst_11: +// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==x21, rs2==x16, rs3==x21, rd==x20,fs1 == 0 and fe1 == 0x00 and fm1 == 0x008 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x070 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x049 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x21; op2:x16; op3:x21; dest:x20; op1val:0x8; op2val:0x4870; +op3val:0x8; valaddr_reg:x10; val_offset:33*FLEN/8; rmval:dyn; +testreg:x15; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x20, x21, x16, x21, dyn, 0, 0, x10, 33*FLEN/8, x12, x13, x15) +RVTEST_VALBASEUPD(x9,test_dataset_1) + +inst_12: +// rs1==x12, rs2==x5, rs3==x14, rd==x25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x010 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x240 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x01d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x12; op2:x5; op3:x14; dest:x25; op1val:0x10; op2val:0x3e40; +op3val:0x1d; valaddr_reg:x9; val_offset:0*FLEN/8; rmval:dyn; +testreg:x15; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x25, x12, x5, x14, dyn, 0, 0, x9, 0*FLEN/8, x11, x13, x15) + +inst_13: +// rs1==x3, rs2==x10, rs3==x15, rd==x14,fs1 == 0 and fe1 == 0x00 and fm1 == 0x051 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x335 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x051 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x3; op2:x10; op3:x15; dest:x14; op1val:0x51; op2val:0x3b35; +op3val:0x51; valaddr_reg:x9; val_offset:3*FLEN/8; rmval:dyn; +testreg:x15; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x14, x3, x10, x15, dyn, 0, 0, x9, 3*FLEN/8, x11, x13, x15) +RVTEST_SIGBASE(x2,signature_x2_0) + +inst_14: +// rs1==x14, rs2==x4, rs3==x20, rd==x31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x04b and fs2 == 1 and fe2 == 0x0b and fm2 == 0x2d3 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x008 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x14; op2:x4; op3:x20; dest:x31; op1val:0x4b; op2val:0xaed3; +op3val:0x8; valaddr_reg:x9; val_offset:6*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x14, x4, x20, dyn, 0, 0, x9, 6*FLEN/8, x11, x2, x3) + +inst_15: +// rs1==x10, rs2==x23, rs3==x7, rd==x1,fs1 == 0 and fe1 == 0x00 and fm1 == 0x04a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0a6 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x04b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x10; op2:x23; op3:x7; dest:x1; op1val:0x4a; op2val:0x38a6; +op3val:0x4b; valaddr_reg:x9; val_offset:9*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x1, x10, x23, x7, dyn, 0, 0, x9, 9*FLEN/8, x11, x2, x3) + +inst_16: +// rs1==x5, rs2==x22, rs3==x8, rd==x15,fs1 == 0 and fe1 == 0x00 and fm1 == 0x033 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x078 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x5; op2:x22; op3:x8; dest:x15; op1val:0x33; op2val:0xbc78; +op3val:0x7; valaddr_reg:x9; val_offset:12*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x15, x5, x22, x8, dyn, 0, 0, x9, 12*FLEN/8, x11, x2, x3) + +inst_17: +// rs1==x13, rs2==x15, rs3==x10, rd==x16,fs1 == 0 and fe1 == 0x00 and fm1 == 0x01d and fs2 == 1 and fe2 == 0x11 and fm2 == 0x034 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x006 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x13; op2:x15; op3:x10; dest:x16; op1val:0x1d; op2val:0xc434; +op3val:0x6; valaddr_reg:x9; val_offset:15*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x16, x13, x15, x10, dyn, 0, 0, x9, 15*FLEN/8, x11, x2, x3) + +inst_18: +// rs1==x28, rs2==x1, rs3==x2, rd==x26,fs1 == 0 and fe1 == 0x00 and fm1 == 0x048 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x29c and fs3 == 0 and fe3 == 0x00 and fm3 == 0x012 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x28; op2:x1; op3:x2; dest:x26; op1val:0x48; op2val:0xc29c; +op3val:0x12; valaddr_reg:x9; val_offset:18*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x26, x28, x1, x2, dyn, 0, 0, x9, 18*FLEN/8, x11, x2, x3) + +inst_19: +// rs1==x7, rs2==x14, rs3==x12, rd==x17,fs1 == 0 and fe1 == 0x00 and fm1 == 0x026 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x206 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x036 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x7; op2:x14; op3:x12; dest:x17; op1val:0x26; op2val:0xca06; +op3val:0x36; valaddr_reg:x9; val_offset:21*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x17, x7, x14, x12, dyn, 0, 0, x9, 21*FLEN/8, x11, x2, x3) + +inst_20: +// rs1==x27, rs2==x30, rs3==x18, rd==x12,fs1 == 0 and fe1 == 0x0f and fm1 == 0x013 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x010 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x046 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x27; op2:x30; op3:x18; dest:x12; op1val:0x3c13; op2val:0x4010; +op3val:0x3c46; valaddr_reg:x9; val_offset:24*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x12, x27, x30, x18, dyn, 0, 0, x9, 24*FLEN/8, x11, x2, x3) + +inst_21: +// rs1==x22, rs2==x13, rs3==x25, rd==x18,fs1 == 0 and fe1 == 0x0f and fm1 == 0x010 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x015 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x04a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x22; op2:x13; op3:x25; dest:x18; op1val:0x3c10; op2val:0x4015; +op3val:0x3c4a; valaddr_reg:x9; val_offset:27*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x18, x22, x13, x25, dyn, 0, 0, x9, 27*FLEN/8, x11, x2, x3) + +inst_22: +// rs1==x8, rs2==x6, rs3==x22, rd==x10,fs1 == 0 and fe1 == 0x0f and fm1 == 0x028 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3fc and fs3 == 0 and fe3 == 0x0f and fm3 == 0x048 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x8; op2:x6; op3:x22; dest:x10; op1val:0x3c28; op2val:0x3ffc; +op3val:0x3c48; valaddr_reg:x9; val_offset:30*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x10, x8, x6, x22, dyn, 0, 0, x9, 30*FLEN/8, x11, x2, x3) +RVTEST_VALBASEUPD(x4,test_dataset_2) + +inst_23: +// rs1==x29, rs2==x28, rs3==x9, rd==x27,fs1 == 0 and fe1 == 0x0f and fm1 == 0x058 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x37b and fs3 == 0 and fe3 == 0x0f and fm3 == 0x018 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x29; op2:x28; op3:x9; dest:x27; op1val:0x3c58; op2val:0x3f7b; +op3val:0x3c18; valaddr_reg:x4; val_offset:0*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x27, x29, x28, x9, dyn, 0, 0, x4, 0*FLEN/8, x5, x2, x3) + +inst_24: +// rs1==x23, rs2==x26, rs3==x13, rd==x9,fs1 == 0 and fe1 == 0x0f and fm1 == 0x00e and fs2 == 0 and fe2 == 0x10 and fm2 == 0x01f and fs3 == 0 and fe3 == 0x0f and fm3 == 0x04b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x23; op2:x26; op3:x13; dest:x9; op1val:0x3c0e; op2val:0x401f; +op3val:0x3c4b; valaddr_reg:x4; val_offset:3*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x9, x23, x26, x13, dyn, 0, 0, x4, 3*FLEN/8, x5, x2, x3) + +inst_25: +// rs1==x18, rs2==x12, rs3==x29, rd==x22,fs1 == 0 and fe1 == 0x0f and fm1 == 0x04a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3e0 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x052 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x18; op2:x12; op3:x29; dest:x22; op1val:0x3c4a; op2val:0x3fe0; +op3val:0x3c52; valaddr_reg:x4; val_offset:6*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x22, x18, x12, x29, dyn, 0, 0, x4, 6*FLEN/8, x5, x2, x3) + +inst_26: +// rs1==x17, rs2==x24, rs3==x6, rd==x7,fs1 == 0 and fe1 == 0x0f and fm1 == 0x019 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x01e and fs3 == 0 and fe3 == 0x0f and fm3 == 0x030 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x17; op2:x24; op3:x6; dest:x7; op1val:0x3c19; op2val:0x401e; +op3val:0x3c30; valaddr_reg:x4; val_offset:9*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x7, x17, x24, x6, dyn, 0, 0, x4, 9*FLEN/8, x5, x2, x3) + +inst_27: +// rs1==x16, rs2==x25, rs3==x28, rd==x21,fs1 == 0 and fe1 == 0x0f and fm1 == 0x00d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x047 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x16; op2:x25; op3:x28; dest:x21; op1val:0x3c0d; op2val:0x4055; +op3val:0x3c47; valaddr_reg:x4; val_offset:12*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x21, x16, x25, x28, dyn, 0, 0, x4, 12*FLEN/8, x5, x2, x3) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_28: +// rs1==x15, rs2==x31, rs3==x1, rd==x13,fs1 == 0 and fe1 == 0x0f and fm1 == 0x05c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x025 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x009 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x15; op2:x31; op3:x1; dest:x13; op1val:0x3c5c; op2val:0x4025; +op3val:0x3c09; valaddr_reg:x4; val_offset:15*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x13, x15, x31, x1, dyn, 0, 0, x4, 15*FLEN/8, x5, x1, x3) + +inst_29: +// rs1==x26, rs2==x20, rs3==x31, rd==x0,fs1 == 0 and fe1 == 0x0f and fm1 == 0x049 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0ae and fs3 == 0 and fe3 == 0x0f and fm3 == 0x008 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x26; op2:x20; op3:x31; dest:x0; op1val:0x3c49; op2val:0x40ae; +op3val:0x3c08; valaddr_reg:x4; val_offset:18*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x0, x26, x20, x31, dyn, 0, 0, x4, 18*FLEN/8, x5, x1, x3) + +inst_30: +// rs1==x20, rs2==x18, rs3==x24, rd==x19,fs1 == 0 and fe1 == 0x0f and fm1 == 0x050 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x207 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x01b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x20; op2:x18; op3:x24; dest:x19; op1val:0x3c50; op2val:0x2607; +op3val:0x3c1b; valaddr_reg:x4; val_offset:21*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x19, x20, x18, x24, dyn, 0, 0, x4, 21*FLEN/8, x5, x1, x3) + +inst_31: +// rs1==x24, rs2==x8, rs3==x5, rd==x28,fs1 == 0 and fe1 == 0x0f and fm1 == 0x040 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x10f and fs3 == 0 and fe3 == 0x0f and fm3 == 0x058 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x24; op2:x8; op3:x5; dest:x28; op1val:0x3c40; op2val:0x2d0f; +op3val:0x3c58; valaddr_reg:x4; val_offset:24*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x28, x24, x8, x5, dyn, 0, 0, x4, 24*FLEN/8, x5, x1, x3) +RVTEST_VALBASEUPD(x2,test_dataset_3) + +inst_32: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x045 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x1f8 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x037 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c45; op2val:0x29f8; +op3val:0x3c37; valaddr_reg:x2; val_offset:0*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 0*FLEN/8, x4, x1, x3) + +inst_33: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x029 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x23f and fs3 == 0 and fe3 == 0x0f and fm3 == 0x03c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c29; op2val:0x2a3f; +op3val:0x3c3c; valaddr_reg:x2; val_offset:3*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 3*FLEN/8, x4, x1, x3) + +inst_34: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x04b and fs2 == 0 and fe2 == 0x0a and fm2 == 0x102 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x03b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c4b; op2val:0x2902; +op3val:0x3c3b; valaddr_reg:x2; val_offset:6*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 6*FLEN/8, x4, x1, x3) + +inst_35: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x02f and fs2 == 0 and fe2 == 0x07 and fm2 == 0x2b1 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x027 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c2f; op2val:0x1eb1; +op3val:0x3c27; valaddr_reg:x2; val_offset:9*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 9*FLEN/8, x4, x1, x3) + +inst_36: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x020 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x0d9 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x018 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c20; op2val:0xa8d9; +op3val:0x3c18; valaddr_reg:x2; val_offset:12*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 12*FLEN/8, x4, x1, x3) + +inst_37: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x05a and fs2 == 1 and fe2 == 0x0b and fm2 == 0x183 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x020 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c5a; op2val:0xad83; +op3val:0x3c20; valaddr_reg:x2; val_offset:15*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 15*FLEN/8, x4, x1, x3) + +inst_38: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x00b and fs2 == 1 and fe2 == 0x0c and fm2 == 0x1a0 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x04a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c0b; op2val:0xb1a0; +op3val:0x3c4a; valaddr_reg:x2; val_offset:18*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 18*FLEN/8, x4, x1, x3) + +inst_39: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x027 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2ae and fs3 == 0 and fe3 == 0x0f and fm3 == 0x044 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c27; op2val:0xb6ae; +op3val:0x3c44; valaddr_reg:x2; val_offset:21*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 21*FLEN/8, x4, x1, x3) + +inst_40: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x040 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1a0 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x02c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x40; op2val:0x39a0; +op3val:0x2c; valaddr_reg:x2; val_offset:24*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24*FLEN/8, x4, x1, x3) + +inst_41: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x05e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x131 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x03a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5e; op2val:0x3931; +op3val:0x3a; valaddr_reg:x2; val_offset:27*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 27*FLEN/8, x4, x1, x3) + +inst_42: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x025 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x07c and fs3 == 0 and fe3 == 0x00 and fm3 == 0x04e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x25; op2val:0x407c; +op3val:0x4e; valaddr_reg:x2; val_offset:30*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 30*FLEN/8, x4, x1, x3) + +inst_43: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00a and fs2 == 0 and fe2 == 0x10 and fm2 == 0x100 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x010 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xa; op2val:0x4100; +op3val:0x10; valaddr_reg:x2; val_offset:33*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 33*FLEN/8, x4, x1, x3) + +inst_44: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x042 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x04d and fs3 == 0 and fe3 == 0x00 and fm3 == 0x036 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x42; op2val:0x3c4d; +op3val:0x36; valaddr_reg:x2; val_offset:36*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 36*FLEN/8, x4, x1, x3) + +inst_45: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x016 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1e8 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x061 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x16; op2val:0x45e8; +op3val:0x61; valaddr_reg:x2; val_offset:39*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39*FLEN/8, x4, x1, x3) + +inst_46: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x02c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3ba and fs3 == 0 and fe3 == 0x00 and fm3 == 0x014 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2c; op2val:0x3fba; +op3val:0x14; valaddr_reg:x2; val_offset:42*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 42*FLEN/8, x4, x1, x3) + +inst_47: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1cf and fs3 == 0 and fe3 == 0x00 and fm3 == 0x036 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f; op2val:0x41cf; +op3val:0x36; valaddr_reg:x2; val_offset:45*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 45*FLEN/8, x4, x1, x3) + +inst_48: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x006 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x325 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x056 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6; op2val:0x5325; +op3val:0x56; valaddr_reg:x2; val_offset:48*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 48*FLEN/8, x4, x1, x3) + +inst_49: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00a and fs2 == 0 and fe2 == 0x14 and fm2 == 0x3a3 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x062 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xa; op2val:0x53a3; +op3val:0x62; valaddr_reg:x2; val_offset:51*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 51*FLEN/8, x4, x1, x3) + +inst_50: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x048 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x00e and fs3 == 0 and fe3 == 0x00 and fm3 == 0x04a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x48; op2val:0x3c0e; +op3val:0x4a; valaddr_reg:x2; val_offset:54*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 54*FLEN/8, x4, x1, x3) + +inst_51: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x029 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x02c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x29; op2val:0x3c00; +op3val:0x2c; valaddr_reg:x2; val_offset:57*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 57*FLEN/8, x4, x1, x3) + +inst_52: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x059 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x330 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x02d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x59; op2val:0x3730; +op3val:0x2d; valaddr_reg:x2; val_offset:60*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 60*FLEN/8, x4, x1, x3) + +inst_53: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x04d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1b6 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x040 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4d; op2val:0x39b6; +op3val:0x40; valaddr_reg:x2; val_offset:63*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 63*FLEN/8, x4, x1, x3) + +inst_54: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x04b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x07a and fs3 == 0 and fe3 == 0x00 and fm3 == 0x03b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4b; op2val:0x387a; +op3val:0x3b; valaddr_reg:x2; val_offset:66*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 66*FLEN/8, x4, x1, x3) + +inst_55: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x009 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0aa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x9; op2val:0xc0aa; +op3val:0xc; valaddr_reg:x2; val_offset:69*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 69*FLEN/8, x4, x1, x3) + +inst_56: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x023 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x350 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x03d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x23; op2val:0xaf50; +op3val:0x3d; valaddr_reg:x2; val_offset:72*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 72*FLEN/8, x4, x1, x3) + +inst_57: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x05a and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3a4 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x056 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5a; op2val:0xb7a4; +op3val:0x56; valaddr_reg:x2; val_offset:75*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 75*FLEN/8, x4, x1, x3) + +inst_58: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x009 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x2ea and fs3 == 0 and fe3 == 0x00 and fm3 == 0x008 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x9; op2val:0xceea; +op3val:0x8; valaddr_reg:x2; val_offset:78*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 78*FLEN/8, x4, x1, x3) + +inst_59: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x05e and fs2 == 1 and fe2 == 0x11 and fm2 == 0x080 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x05a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5e; op2val:0xc480; +op3val:0x5a; valaddr_reg:x2; val_offset:81*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 81*FLEN/8, x4, x1, x3) + +inst_60: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x028 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x2e8 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x053 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x28; op2val:0x4ee8; +op3val:0x53; valaddr_reg:x2; val_offset:84*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 84*FLEN/8, x4, x1, x3) + +inst_61: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x04a and fs2 == 0 and fe2 == 0x12 and fm2 == 0x37e and fs3 == 0 and fe3 == 0x00 and fm3 == 0x058 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4a; op2val:0x4b7e; +op3val:0x58; valaddr_reg:x2; val_offset:87*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 87*FLEN/8, x4, x1, x3) + +inst_62: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03a and fs2 == 0 and fe2 == 0x13 and fm2 == 0x08d and fs3 == 0 and fe3 == 0x00 and fm3 == 0x025 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a; op2val:0x4c8d; +op3val:0x25; valaddr_reg:x2; val_offset:90*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 90*FLEN/8, x4, x1, x3) + +inst_63: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x05c and fs2 == 0 and fe2 == 0x12 and fm2 == 0x1c9 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x032 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5c; op2val:0x49c9; +op3val:0x32; valaddr_reg:x2; val_offset:93*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 93*FLEN/8, x4, x1, x3) + +inst_64: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x056 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x21d and fs3 == 0 and fe3 == 0x00 and fm3 == 0x02d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x56; op2val:0x4a1d; +op3val:0x2d; valaddr_reg:x2; val_offset:96*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 96*FLEN/8, x4, x1, x3) + +inst_65: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x003 and fs2 == 0 and fe2 == 0x17 and fm2 == 0x179 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x03c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3; op2val:0x5d79; +op3val:0x3c; valaddr_reg:x2; val_offset:99*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 99*FLEN/8, x4, x1, x3) + +inst_66: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x02e and fs2 == 0 and fe2 == 0x13 and fm2 == 0x154 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x016 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e; op2val:0x4d54; +op3val:0x16; valaddr_reg:x2; val_offset:102*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 102*FLEN/8, x4, x1, x3) + +inst_67: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x04f and fs2 == 0 and fe2 == 0x12 and fm2 == 0x1c2 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4f; op2val:0x49c2; +op3val:0xf; valaddr_reg:x2; val_offset:105*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 105*FLEN/8, x4, x1, x3) + +inst_68: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x040 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x20e and fs3 == 0 and fe3 == 0x00 and fm3 == 0x008 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x40; op2val:0x4a0e; +op3val:0x8; valaddr_reg:x2; val_offset:108*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 108*FLEN/8, x4, x1, x3) + +inst_69: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x01c and fs2 == 0 and fe2 == 0x13 and fm2 == 0x172 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x063 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1c; op2val:0x4d72; +op3val:0x63; valaddr_reg:x2; val_offset:111*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 111*FLEN/8, x4, x1, x3) + +inst_70: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x025 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x2ca and fs3 == 0 and fe3 == 0x00 and fm3 == 0x011 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x25; op2val:0xceca; +op3val:0x11; valaddr_reg:x2; val_offset:114*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 114*FLEN/8, x4, x1, x3) + +inst_71: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x05f and fs2 == 1 and fe2 == 0x12 and fm2 == 0x134 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x020 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5f; op2val:0xc934; +op3val:0x20; valaddr_reg:x2; val_offset:117*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 117*FLEN/8, x4, x1, x3) + +inst_72: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x033 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x0be and fs3 == 0 and fe3 == 0x00 and fm3 == 0x033 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x33; op2val:0xccbe; +op3val:0x33; valaddr_reg:x2; val_offset:120*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 120*FLEN/8, x4, x1, x3) + +inst_73: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x040 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x3d8 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x40; op2val:0xcbd8; +op3val:0xb; valaddr_reg:x2; val_offset:123*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 123*FLEN/8, x4, x1, x3) + +inst_74: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x016 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x164 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x03a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x16; op2val:0xd164; +op3val:0x3a; valaddr_reg:x2; val_offset:126*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 126*FLEN/8, x4, x1, x3) + +inst_75: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x034 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x06c and fs3 == 0 and fe3 == 0x00 and fm3 == 0x047 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34; op2val:0xcc6c; +op3val:0x47; valaddr_reg:x2; val_offset:129*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 129*FLEN/8, x4, x1, x3) + +inst_76: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x024 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x288 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x012 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x24; op2val:0xce88; +op3val:0x12; valaddr_reg:x2; val_offset:132*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 132*FLEN/8, x4, x1, x3) + +inst_77: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x038 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x35b and fs3 == 0 and fe3 == 0x00 and fm3 == 0x047 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38; op2val:0xcb5b; +op3val:0x47; valaddr_reg:x2; val_offset:135*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 135*FLEN/8, x4, x1, x3) + +inst_78: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x024 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x0b1 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x05b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x24; op2val:0xccb1; +op3val:0x5b; valaddr_reg:x2; val_offset:138*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 138*FLEN/8, x4, x1, x3) + +inst_79: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x036 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x04e and fs3 == 0 and fe3 == 0x00 and fm3 == 0x02e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36; op2val:0xc84e; +op3val:0x2e; valaddr_reg:x2; val_offset:141*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 141*FLEN/8, x4, x1, x3) + +inst_80: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x058 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x38b and fs3 == 0 and fe3 == 0x01 and fm3 == 0x031 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x458; op2val:0x3f8b; +op3val:0x431; valaddr_reg:x2; val_offset:144*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 144*FLEN/8, x4, x1, x3) + +inst_81: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x01e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3db and fs3 == 0 and fe3 == 0x01 and fm3 == 0x014 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x41e; op2val:0x3fdb; +op3val:0x414; valaddr_reg:x2; val_offset:147*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 147*FLEN/8, x4, x1, x3) + +inst_82: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x00b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x017 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x40b; op2val:0x4002; +op3val:0x417; valaddr_reg:x2; val_offset:150*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 150*FLEN/8, x4, x1, x3) + +inst_83: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x014 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x01e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x414; op2val:0x3ffe; +op3val:0x41e; valaddr_reg:x2; val_offset:153*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 153*FLEN/8, x4, x1, x3) + +inst_84: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x38d and fs3 == 0 and fe3 == 0x01 and fm3 == 0x01e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x455; op2val:0x3f8d; +op3val:0x41e; valaddr_reg:x2; val_offset:156*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 156*FLEN/8, x4, x1, x3) + +inst_85: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x02d and fs3 == 0 and fe3 == 0x01 and fm3 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x402; op2val:0x402d; +op3val:0x43f; valaddr_reg:x2; val_offset:159*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 159*FLEN/8, x4, x1, x3) + +inst_86: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x04c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3c4 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x018 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x44c; op2val:0x3fc4; +op3val:0x418; valaddr_reg:x2; val_offset:162*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 162*FLEN/8, x4, x1, x3) + +inst_87: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x022 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x02e and fs3 == 0 and fe3 == 0x01 and fm3 == 0x025 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x422; op2val:0x402e; +op3val:0x425; valaddr_reg:x2; val_offset:165*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 165*FLEN/8, x4, x1, x3) + +inst_88: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x088 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x013 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0x4088; +op3val:0x413; valaddr_reg:x2; val_offset:168*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 168*FLEN/8, x4, x1, x3) + +inst_89: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x036 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0e0 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x045 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x436; op2val:0x40e0; +op3val:0x445; valaddr_reg:x2; val_offset:171*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 171*FLEN/8, x4, x1, x3) + +inst_90: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x030 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x0a8 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x04f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x430; op2val:0x2ca8; +op3val:0x44f; valaddr_reg:x2; val_offset:174*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 174*FLEN/8, x4, x1, x3) + +inst_91: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x049 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x08c and fs3 == 0 and fe3 == 0x01 and fm3 == 0x029 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x449; op2val:0x288c; +op3val:0x429; valaddr_reg:x2; val_offset:177*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 177*FLEN/8, x4, x1, x3) + +inst_92: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x011 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x139 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x059 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x411; op2val:0x2d39; +op3val:0x459; valaddr_reg:x2; val_offset:180*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 180*FLEN/8, x4, x1, x3) + +inst_93: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x042 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x03a and fs3 == 0 and fe3 == 0x01 and fm3 == 0x050 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x442; op2val:0x2c3a; +op3val:0x450; valaddr_reg:x2; val_offset:183*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 183*FLEN/8, x4, x1, x3) + +inst_94: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x054 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x019 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x057 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x454; op2val:0x2c19; +op3val:0x457; valaddr_reg:x2; val_offset:186*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 186*FLEN/8, x4, x1, x3) + +inst_95: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x05f and fs2 == 1 and fe2 == 0x09 and fm2 == 0x1b8 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x45f; op2val:0xa5b8; +op3val:0x407; valaddr_reg:x2; val_offset:189*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 189*FLEN/8, x4, x1, x3) + +inst_96: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x03b and fs2 == 0 and fe2 == 0x09 and fm2 == 0x1ac and fs3 == 0 and fe3 == 0x01 and fm3 == 0x058 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x43b; op2val:0x25ac; +op3val:0x458; valaddr_reg:x2; val_offset:192*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 192*FLEN/8, x4, x1, x3) + +inst_97: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x048 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x07f and fs3 == 0 and fe3 == 0x01 and fm3 == 0x033 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x448; op2val:0xac7f; +op3val:0x433; valaddr_reg:x2; val_offset:195*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 195*FLEN/8, x4, x1, x3) + +inst_98: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x033 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x212 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x034 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x433; op2val:0xb212; +op3val:0x434; valaddr_reg:x2; val_offset:198*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 198*FLEN/8, x4, x1, x3) + +inst_99: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x033 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x369 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x00e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x433; op2val:0xb769; +op3val:0x40e; valaddr_reg:x2; val_offset:201*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 201*FLEN/8, x4, x1, x3) + +inst_100: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x03e and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1ce and fs3 == 0 and fe3 == 0x1e and fm3 == 0x052 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x783e; op2val:0x41ce; +op3val:0x7852; valaddr_reg:x2; val_offset:204*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 204*FLEN/8, x4, x1, x3) + +inst_101: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x034 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1b8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x008 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7834; op2val:0x41b8; +op3val:0x7808; valaddr_reg:x2; val_offset:207*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 207*FLEN/8, x4, x1, x3) + +inst_102: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x019 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1dd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x009 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7819; op2val:0x41dd; +op3val:0x7809; valaddr_reg:x2; val_offset:210*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 210*FLEN/8, x4, x1, x3) + +inst_103: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x01b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1ef and fs3 == 0 and fe3 == 0x1e and fm3 == 0x039 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x781b; op2val:0x41ef; +op3val:0x7839; valaddr_reg:x2; val_offset:213*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 213*FLEN/8, x4, x1, x3) + +inst_104: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x015 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1e0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7815; op2val:0x41e0; +op3val:0x780f; valaddr_reg:x2; val_offset:216*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 216*FLEN/8, x4, x1, x3) + +inst_105: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1d5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x04d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x782c; op2val:0x41d5; +op3val:0x784d; valaddr_reg:x2; val_offset:219*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 219*FLEN/8, x4, x1, x3) + +inst_106: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x007 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1dc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7807; op2val:0x41dc; +op3val:0x780e; valaddr_reg:x2; val_offset:222*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 222*FLEN/8, x4, x1, x3) + +inst_107: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1e2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x049 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7801; op2val:0x41e2; +op3val:0x7849; valaddr_reg:x2; val_offset:225*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 225*FLEN/8, x4, x1, x3) + +inst_108: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x014 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x186 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x045 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7814; op2val:0x4186; +op3val:0x7845; valaddr_reg:x2; val_offset:228*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 228*FLEN/8, x4, x1, x3) + +inst_109: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x106 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x02f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x780d; op2val:0x4106; +op3val:0x782f; valaddr_reg:x2; val_offset:231*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 231*FLEN/8, x4, x1, x3) + +inst_110: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x362 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x004 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x784f; op2val:0xbb62; +op3val:0x7804; valaddr_reg:x2; val_offset:234*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 234*FLEN/8, x4, x1, x3) + +inst_111: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x01b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x780a; op2val:0xbbb0; +op3val:0x781b; valaddr_reg:x2; val_offset:237*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 237*FLEN/8, x4, x1, x3) + +inst_112: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x309 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x031 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x784f; op2val:0xbb09; +op3val:0x7831; valaddr_reg:x2; val_offset:240*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 240*FLEN/8, x4, x1, x3) + +inst_113: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x014 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x326 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x052 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7814; op2val:0xbb26; +op3val:0x7852; valaddr_reg:x2; val_offset:243*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 243*FLEN/8, x4, x1, x3) + +inst_114: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x021 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x347 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x02d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7821; op2val:0xbb47; +op3val:0x782d; valaddr_reg:x2; val_offset:246*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 246*FLEN/8, x4, x1, x3) + +inst_115: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2da and fs3 == 0 and fe3 == 0x1e and fm3 == 0x02f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x784e; op2val:0xbada; +op3val:0x782f; valaddr_reg:x2; val_offset:249*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 249*FLEN/8, x4, x1, x3) + +inst_116: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x03d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2f3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x010 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x783d; op2val:0xbaf3; +op3val:0x7810; valaddr_reg:x2; val_offset:252*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 252*FLEN/8, x4, x1, x3) + +inst_117: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x267 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x780f; op2val:0xba67; +op3val:0x783f; valaddr_reg:x2; val_offset:255*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 255*FLEN/8, x4, x1, x3) + +inst_118: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x03c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x133 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x03e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x783c; op2val:0xb933; +op3val:0x783e; valaddr_reg:x2; val_offset:258*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 258*FLEN/8, x4, x1, x3) + +inst_119: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x03e and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2f0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x028 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x783e; op2val:0xb6f0; +op3val:0x7828; valaddr_reg:x2; val_offset:261*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 261*FLEN/8, x4, x1, x3) + +inst_120: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x02a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x014 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2a; op2val:0x3800; +op3val:0x14; valaddr_reg:x2; val_offset:264*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 264*FLEN/8, x4, x1, x3) + +inst_121: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7; op2val:0x4000; +op3val:0xa; valaddr_reg:x2; val_offset:267*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 267*FLEN/8, x4, x1, x3) + +inst_122: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x045 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0de and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x45; op2val:0x34de; +op3val:0xd; valaddr_reg:x2; val_offset:270*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 270*FLEN/8, x4, x1, x3) + +inst_123: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x02f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3be and fs3 == 0 and fe3 == 0x00 and fm3 == 0x04b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f; op2val:0x3fbe; +op3val:0x4b; valaddr_reg:x2; val_offset:273*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 273*FLEN/8, x4, x1, x3) + +inst_124: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x008 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x210 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x041 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8; op2val:0x4a10; +op3val:0x41; valaddr_reg:x2; val_offset:276*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 276*FLEN/8, x4, x1, x3) + +inst_125: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x036 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0e8 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x009 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36; op2val:0x44e8; +op3val:0x9; valaddr_reg:x2; val_offset:279*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 279*FLEN/8, x4, x1, x3) + +inst_126: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x01f and fs2 == 0 and fe2 == 0x13 and fm2 == 0x039 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1f; op2val:0x4c39; +op3val:0xc; valaddr_reg:x2; val_offset:282*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 282*FLEN/8, x4, x1, x3) + +inst_127: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x047 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x215 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x037 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x47; op2val:0x3a15; +op3val:0x37; valaddr_reg:x2; val_offset:285*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 285*FLEN/8, x4, x1, x3) + +inst_128: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x008 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x070 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x049 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x8; op2val:0x4870; +op3val:0x49; valaddr_reg:x2; val_offset:288*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 288*FLEN/8, x4, x1, x3) + +inst_129: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x049 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0ae and fs3 == 0 and fe3 == 0x0f and fm3 == 0x008 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c49; op2val:0x40ae; +op3val:0x3c08; valaddr_reg:x2; val_offset:291*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 291*FLEN/8, x4, x1, x3) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(42,32,FLEN) +NAN_BOXED(42,32,FLEN) +NAN_BOXED(42,32,FLEN) +NAN_BOXED(51,32,FLEN) +NAN_BOXED(16062,32,FLEN) +NAN_BOXED(84,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(10,32,FLEN) +NAN_BOXED(69,32,FLEN) +NAN_BOXED(13534,32,FLEN) +NAN_BOXED(13534,32,FLEN) +NAN_BOXED(47,32,FLEN) +NAN_BOXED(47,32,FLEN) +NAN_BOXED(47,32,FLEN) +NAN_BOXED(8,32,FLEN) +NAN_BOXED(18960,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(28,32,FLEN) +NAN_BOXED(16621,32,FLEN) +NAN_BOXED(5,32,FLEN) +NAN_BOXED(12,32,FLEN) +NAN_BOXED(19370,32,FLEN) +NAN_BOXED(56,32,FLEN) +NAN_BOXED(54,32,FLEN) +NAN_BOXED(17640,32,FLEN) +NAN_BOXED(17640,32,FLEN) +NAN_BOXED(31,32,FLEN) +NAN_BOXED(31,32,FLEN) +NAN_BOXED(12,32,FLEN) +NAN_BOXED(71,32,FLEN) +NAN_BOXED(14869,32,FLEN) +NAN_BOXED(71,32,FLEN) +NAN_BOXED(8,32,FLEN) +NAN_BOXED(18544,32,FLEN) +NAN_BOXED(8,32,FLEN) +test_dataset_1: +NAN_BOXED(16,32,FLEN) +NAN_BOXED(15936,32,FLEN) +NAN_BOXED(29,32,FLEN) +NAN_BOXED(81,32,FLEN) +NAN_BOXED(15157,32,FLEN) +NAN_BOXED(81,32,FLEN) +NAN_BOXED(75,32,FLEN) +NAN_BOXED(44755,16,FLEN) +NAN_BOXED(8,32,FLEN) +NAN_BOXED(74,32,FLEN) +NAN_BOXED(14502,32,FLEN) +NAN_BOXED(75,32,FLEN) +NAN_BOXED(51,32,FLEN) +NAN_BOXED(48248,16,FLEN) +NAN_BOXED(7,32,FLEN) +NAN_BOXED(29,32,FLEN) +NAN_BOXED(50228,16,FLEN) +NAN_BOXED(6,32,FLEN) +NAN_BOXED(72,32,FLEN) +NAN_BOXED(49820,16,FLEN) +NAN_BOXED(18,32,FLEN) +NAN_BOXED(38,32,FLEN) +NAN_BOXED(51718,16,FLEN) +NAN_BOXED(54,32,FLEN) +NAN_BOXED(15379,32,FLEN) +NAN_BOXED(16400,32,FLEN) +NAN_BOXED(15430,32,FLEN) +NAN_BOXED(15376,32,FLEN) +NAN_BOXED(16405,32,FLEN) +NAN_BOXED(15434,32,FLEN) +NAN_BOXED(15400,32,FLEN) +NAN_BOXED(16380,32,FLEN) +NAN_BOXED(15432,32,FLEN) +test_dataset_2: +NAN_BOXED(15448,32,FLEN) +NAN_BOXED(16251,32,FLEN) +NAN_BOXED(15384,32,FLEN) +NAN_BOXED(15374,32,FLEN) +NAN_BOXED(16415,32,FLEN) +NAN_BOXED(15435,32,FLEN) +NAN_BOXED(15434,32,FLEN) +NAN_BOXED(16352,32,FLEN) +NAN_BOXED(15442,32,FLEN) +NAN_BOXED(15385,32,FLEN) +NAN_BOXED(16414,32,FLEN) +NAN_BOXED(15408,32,FLEN) +NAN_BOXED(15373,32,FLEN) +NAN_BOXED(16469,32,FLEN) +NAN_BOXED(15431,32,FLEN) +NAN_BOXED(15452,32,FLEN) +NAN_BOXED(16421,32,FLEN) +NAN_BOXED(15369,32,FLEN) +NAN_BOXED(15433,32,FLEN) +NAN_BOXED(16558,32,FLEN) +NAN_BOXED(15368,32,FLEN) +NAN_BOXED(15440,32,FLEN) +NAN_BOXED(9735,32,FLEN) +NAN_BOXED(15387,32,FLEN) +NAN_BOXED(15424,32,FLEN) +NAN_BOXED(11535,32,FLEN) +NAN_BOXED(15448,32,FLEN) +test_dataset_3: +NAN_BOXED(15429,16,FLEN) +NAN_BOXED(10744,16,FLEN) +NAN_BOXED(15415,16,FLEN) +NAN_BOXED(15401,16,FLEN) +NAN_BOXED(10815,16,FLEN) +NAN_BOXED(15420,16,FLEN) +NAN_BOXED(15435,16,FLEN) +NAN_BOXED(10498,16,FLEN) +NAN_BOXED(15419,16,FLEN) +NAN_BOXED(15407,16,FLEN) +NAN_BOXED(7857,16,FLEN) +NAN_BOXED(15399,16,FLEN) +NAN_BOXED(15392,16,FLEN) +NAN_BOXED(43225,16,FLEN) +NAN_BOXED(15384,16,FLEN) +NAN_BOXED(15450,16,FLEN) +NAN_BOXED(44419,16,FLEN) +NAN_BOXED(15392,16,FLEN) +NAN_BOXED(15371,16,FLEN) +NAN_BOXED(45472,16,FLEN) +NAN_BOXED(15434,16,FLEN) +NAN_BOXED(15399,16,FLEN) +NAN_BOXED(46766,16,FLEN) +NAN_BOXED(15428,16,FLEN) +NAN_BOXED(64,16,FLEN) +NAN_BOXED(14752,16,FLEN) +NAN_BOXED(44,16,FLEN) +NAN_BOXED(94,16,FLEN) +NAN_BOXED(14641,16,FLEN) +NAN_BOXED(58,16,FLEN) +NAN_BOXED(37,16,FLEN) +NAN_BOXED(16508,16,FLEN) +NAN_BOXED(78,16,FLEN) +NAN_BOXED(10,16,FLEN) +NAN_BOXED(16640,16,FLEN) +NAN_BOXED(16,16,FLEN) +NAN_BOXED(66,16,FLEN) +NAN_BOXED(15437,16,FLEN) +NAN_BOXED(54,16,FLEN) +NAN_BOXED(22,16,FLEN) +NAN_BOXED(17896,16,FLEN) +NAN_BOXED(97,16,FLEN) +NAN_BOXED(44,16,FLEN) +NAN_BOXED(16314,16,FLEN) +NAN_BOXED(20,16,FLEN) +NAN_BOXED(63,16,FLEN) +NAN_BOXED(16847,16,FLEN) +NAN_BOXED(54,16,FLEN) +NAN_BOXED(6,16,FLEN) +NAN_BOXED(21285,16,FLEN) +NAN_BOXED(86,16,FLEN) +NAN_BOXED(10,16,FLEN) +NAN_BOXED(21411,16,FLEN) +NAN_BOXED(98,16,FLEN) +NAN_BOXED(72,16,FLEN) +NAN_BOXED(15374,16,FLEN) +NAN_BOXED(74,16,FLEN) +NAN_BOXED(41,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(44,16,FLEN) +NAN_BOXED(89,16,FLEN) +NAN_BOXED(14128,16,FLEN) +NAN_BOXED(45,16,FLEN) +NAN_BOXED(77,16,FLEN) +NAN_BOXED(14774,16,FLEN) +NAN_BOXED(64,16,FLEN) +NAN_BOXED(75,16,FLEN) +NAN_BOXED(14458,16,FLEN) +NAN_BOXED(59,16,FLEN) +NAN_BOXED(9,16,FLEN) +NAN_BOXED(49322,16,FLEN) +NAN_BOXED(12,16,FLEN) +NAN_BOXED(35,16,FLEN) +NAN_BOXED(44880,16,FLEN) +NAN_BOXED(61,16,FLEN) +NAN_BOXED(90,16,FLEN) +NAN_BOXED(47012,16,FLEN) +NAN_BOXED(86,16,FLEN) +NAN_BOXED(9,16,FLEN) +NAN_BOXED(52970,16,FLEN) +NAN_BOXED(8,16,FLEN) +NAN_BOXED(94,16,FLEN) +NAN_BOXED(50304,16,FLEN) +NAN_BOXED(90,16,FLEN) +NAN_BOXED(40,16,FLEN) +NAN_BOXED(20200,16,FLEN) +NAN_BOXED(83,16,FLEN) +NAN_BOXED(74,16,FLEN) +NAN_BOXED(19326,16,FLEN) +NAN_BOXED(88,16,FLEN) +NAN_BOXED(58,16,FLEN) +NAN_BOXED(19597,16,FLEN) +NAN_BOXED(37,16,FLEN) +NAN_BOXED(92,16,FLEN) +NAN_BOXED(18889,16,FLEN) +NAN_BOXED(50,16,FLEN) +NAN_BOXED(86,16,FLEN) +NAN_BOXED(18973,16,FLEN) +NAN_BOXED(45,16,FLEN) +NAN_BOXED(3,16,FLEN) +NAN_BOXED(23929,16,FLEN) +NAN_BOXED(60,16,FLEN) +NAN_BOXED(46,16,FLEN) +NAN_BOXED(19796,16,FLEN) +NAN_BOXED(22,16,FLEN) +NAN_BOXED(79,16,FLEN) +NAN_BOXED(18882,16,FLEN) +NAN_BOXED(15,16,FLEN) +NAN_BOXED(64,16,FLEN) +NAN_BOXED(18958,16,FLEN) +NAN_BOXED(8,16,FLEN) +NAN_BOXED(28,16,FLEN) +NAN_BOXED(19826,16,FLEN) +NAN_BOXED(99,16,FLEN) +NAN_BOXED(37,16,FLEN) +NAN_BOXED(52938,16,FLEN) +NAN_BOXED(17,16,FLEN) +NAN_BOXED(95,16,FLEN) +NAN_BOXED(51508,16,FLEN) +NAN_BOXED(32,16,FLEN) +NAN_BOXED(51,16,FLEN) +NAN_BOXED(52414,16,FLEN) +NAN_BOXED(51,16,FLEN) +NAN_BOXED(64,16,FLEN) +NAN_BOXED(52184,16,FLEN) +NAN_BOXED(11,16,FLEN) +NAN_BOXED(22,16,FLEN) +NAN_BOXED(53604,16,FLEN) +NAN_BOXED(58,16,FLEN) +NAN_BOXED(52,16,FLEN) +NAN_BOXED(52332,16,FLEN) +NAN_BOXED(71,16,FLEN) +NAN_BOXED(36,16,FLEN) +NAN_BOXED(52872,16,FLEN) +NAN_BOXED(18,16,FLEN) +NAN_BOXED(56,16,FLEN) +NAN_BOXED(52059,16,FLEN) +NAN_BOXED(71,16,FLEN) +NAN_BOXED(36,16,FLEN) +NAN_BOXED(52401,16,FLEN) +NAN_BOXED(91,16,FLEN) +NAN_BOXED(54,16,FLEN) +NAN_BOXED(51278,16,FLEN) +NAN_BOXED(46,16,FLEN) +NAN_BOXED(1112,16,FLEN) +NAN_BOXED(16267,16,FLEN) +NAN_BOXED(1073,16,FLEN) +NAN_BOXED(1054,16,FLEN) +NAN_BOXED(16347,16,FLEN) +NAN_BOXED(1044,16,FLEN) +NAN_BOXED(1035,16,FLEN) +NAN_BOXED(16386,16,FLEN) +NAN_BOXED(1047,16,FLEN) +NAN_BOXED(1044,16,FLEN) +NAN_BOXED(16382,16,FLEN) +NAN_BOXED(1054,16,FLEN) +NAN_BOXED(1109,16,FLEN) +NAN_BOXED(16269,16,FLEN) +NAN_BOXED(1054,16,FLEN) +NAN_BOXED(1026,16,FLEN) +NAN_BOXED(16429,16,FLEN) +NAN_BOXED(1087,16,FLEN) +NAN_BOXED(1100,16,FLEN) +NAN_BOXED(16324,16,FLEN) +NAN_BOXED(1048,16,FLEN) +NAN_BOXED(1058,16,FLEN) +NAN_BOXED(16430,16,FLEN) +NAN_BOXED(1061,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(16520,16,FLEN) +NAN_BOXED(1043,16,FLEN) +NAN_BOXED(1078,16,FLEN) +NAN_BOXED(16608,16,FLEN) +NAN_BOXED(1093,16,FLEN) +NAN_BOXED(1072,16,FLEN) +NAN_BOXED(11432,16,FLEN) +NAN_BOXED(1103,16,FLEN) +NAN_BOXED(1097,16,FLEN) +NAN_BOXED(10380,16,FLEN) +NAN_BOXED(1065,16,FLEN) +NAN_BOXED(1041,16,FLEN) +NAN_BOXED(11577,16,FLEN) +NAN_BOXED(1113,16,FLEN) +NAN_BOXED(1090,16,FLEN) +NAN_BOXED(11322,16,FLEN) +NAN_BOXED(1104,16,FLEN) +NAN_BOXED(1108,16,FLEN) +NAN_BOXED(11289,16,FLEN) +NAN_BOXED(1111,16,FLEN) +NAN_BOXED(1119,16,FLEN) +NAN_BOXED(42424,16,FLEN) +NAN_BOXED(1031,16,FLEN) +NAN_BOXED(1083,16,FLEN) +NAN_BOXED(9644,16,FLEN) +NAN_BOXED(1112,16,FLEN) +NAN_BOXED(1096,16,FLEN) +NAN_BOXED(44159,16,FLEN) +NAN_BOXED(1075,16,FLEN) +NAN_BOXED(1075,16,FLEN) +NAN_BOXED(45586,16,FLEN) +NAN_BOXED(1076,16,FLEN) +NAN_BOXED(1075,16,FLEN) +NAN_BOXED(46953,16,FLEN) +NAN_BOXED(1038,16,FLEN) +NAN_BOXED(30782,16,FLEN) +NAN_BOXED(16846,16,FLEN) +NAN_BOXED(30802,16,FLEN) +NAN_BOXED(30772,16,FLEN) +NAN_BOXED(16824,16,FLEN) +NAN_BOXED(30728,16,FLEN) +NAN_BOXED(30745,16,FLEN) +NAN_BOXED(16861,16,FLEN) +NAN_BOXED(30729,16,FLEN) +NAN_BOXED(30747,16,FLEN) +NAN_BOXED(16879,16,FLEN) +NAN_BOXED(30777,16,FLEN) +NAN_BOXED(30741,16,FLEN) +NAN_BOXED(16864,16,FLEN) +NAN_BOXED(30735,16,FLEN) +NAN_BOXED(30764,16,FLEN) +NAN_BOXED(16853,16,FLEN) +NAN_BOXED(30797,16,FLEN) +NAN_BOXED(30727,16,FLEN) +NAN_BOXED(16860,16,FLEN) +NAN_BOXED(30734,16,FLEN) +NAN_BOXED(30721,16,FLEN) +NAN_BOXED(16866,16,FLEN) +NAN_BOXED(30793,16,FLEN) +NAN_BOXED(30740,16,FLEN) +NAN_BOXED(16774,16,FLEN) +NAN_BOXED(30789,16,FLEN) +NAN_BOXED(30733,16,FLEN) +NAN_BOXED(16646,16,FLEN) +NAN_BOXED(30767,16,FLEN) +NAN_BOXED(30799,16,FLEN) +NAN_BOXED(47970,16,FLEN) +NAN_BOXED(30724,16,FLEN) +NAN_BOXED(30730,16,FLEN) +NAN_BOXED(48048,16,FLEN) +NAN_BOXED(30747,16,FLEN) +NAN_BOXED(30799,16,FLEN) +NAN_BOXED(47881,16,FLEN) +NAN_BOXED(30769,16,FLEN) +NAN_BOXED(30740,16,FLEN) +NAN_BOXED(47910,16,FLEN) +NAN_BOXED(30802,16,FLEN) +NAN_BOXED(30753,16,FLEN) +NAN_BOXED(47943,16,FLEN) +NAN_BOXED(30765,16,FLEN) +NAN_BOXED(30798,16,FLEN) +NAN_BOXED(47834,16,FLEN) +NAN_BOXED(30767,16,FLEN) +NAN_BOXED(30781,16,FLEN) +NAN_BOXED(47859,16,FLEN) +NAN_BOXED(30736,16,FLEN) +NAN_BOXED(30735,16,FLEN) +NAN_BOXED(47719,16,FLEN) +NAN_BOXED(30783,16,FLEN) +NAN_BOXED(30780,16,FLEN) +NAN_BOXED(47411,16,FLEN) +NAN_BOXED(30782,16,FLEN) +NAN_BOXED(30782,16,FLEN) +NAN_BOXED(46832,16,FLEN) +NAN_BOXED(30760,16,FLEN) +NAN_BOXED(42,16,FLEN) +NAN_BOXED(14336,16,FLEN) +NAN_BOXED(20,16,FLEN) +NAN_BOXED(7,16,FLEN) +NAN_BOXED(16384,16,FLEN) +NAN_BOXED(10,16,FLEN) +NAN_BOXED(69,16,FLEN) +NAN_BOXED(13534,16,FLEN) +NAN_BOXED(13,16,FLEN) +NAN_BOXED(47,16,FLEN) +NAN_BOXED(16318,16,FLEN) +NAN_BOXED(75,16,FLEN) +NAN_BOXED(8,16,FLEN) +NAN_BOXED(18960,16,FLEN) +NAN_BOXED(65,16,FLEN) +NAN_BOXED(54,16,FLEN) +NAN_BOXED(17640,16,FLEN) +NAN_BOXED(9,16,FLEN) +NAN_BOXED(31,16,FLEN) +NAN_BOXED(19513,16,FLEN) +NAN_BOXED(12,16,FLEN) +NAN_BOXED(71,16,FLEN) +NAN_BOXED(14869,16,FLEN) +NAN_BOXED(55,16,FLEN) +NAN_BOXED(8,16,FLEN) +NAN_BOXED(18544,16,FLEN) +NAN_BOXED(73,16,FLEN) +NAN_BOXED(15433,16,FLEN) +NAN_BOXED(16558,16,FLEN) +NAN_BOXED(15368,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x13_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x13_1: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_0: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_0: + .fill 204*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fmsub_b3-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fmsub_b3-01.S new file mode 100644 index 000000000..4a4a1b3d1 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fmsub_b3-01.S @@ -0,0 +1,11436 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 05:33:17 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fmsub.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fmsub.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fmsub_b3 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fmsub_b3) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x4,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rs2 == rs3 != rd, rs1==x22, rs2==x22, rs3==x22, rd==x13,fs1 == 0 and fe1 == 0x1d and fm1 == 0x12d and fs2 == 0 and fe2 == 0x0d and fm2 == 0x374 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x22; op2:x22; op3:x22; dest:x13; op1val:0x752d; op2val:0x752d; +op3val:0x752d; valaddr_reg:x4; val_offset:0*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x13, x22, x22, x22, dyn, 0, 0, x4, 0*FLEN/8, x8, x1, x3) + +inst_1: +// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==x7, rs2==x30, rs3==x25, rd==x20,fs1 == 0 and fe1 == 0x1d and fm1 == 0x12d and fs2 == 0 and fe2 == 0x0d and fm2 == 0x374 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x7; op2:x30; op3:x25; dest:x20; op1val:0x752d; op2val:0x3774; +op3val:0x70d3; valaddr_reg:x4; val_offset:3*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x20, x7, x30, x25, dyn, 32, 0, x4, 3*FLEN/8, x8, x1, x3) + +inst_2: +// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==x18, rs2==x18, rs3==x30, rd==x11,fs1 == 0 and fe1 == 0x1d and fm1 == 0x12d and fs2 == 0 and fe2 == 0x0d and fm2 == 0x374 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x18; op2:x18; op3:x30; dest:x11; op1val:0x752d; op2val:0x752d; +op3val:0x70d3; valaddr_reg:x4; val_offset:6*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x11, x18, x18, x30, dyn, 64, 0, x4, 6*FLEN/8, x8, x1, x3) + +inst_3: +// rd == rs2 == rs3 != rs1, rs1==x23, rs2==x10, rs3==x10, rd==x10,fs1 == 0 and fe1 == 0x1d and fm1 == 0x12d and fs2 == 0 and fe2 == 0x0d and fm2 == 0x374 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x23; op2:x10; op3:x10; dest:x10; op1val:0x752d; op2val:0x3774; +op3val:0x3774; valaddr_reg:x4; val_offset:9*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x10, x23, x10, x10, dyn, 96, 0, x4, 9*FLEN/8, x8, x1, x3) + +inst_4: +// rs1 == rs2 == rs3 == rd, rs1==x29, rs2==x29, rs3==x29, rd==x29,fs1 == 0 and fe1 == 0x1d and fm1 == 0x12d and fs2 == 0 and fe2 == 0x0d and fm2 == 0x374 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x29; op2:x29; op3:x29; dest:x29; op1val:0x752d; op2val:0x752d; +op3val:0x752d; valaddr_reg:x4; val_offset:12*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x29, x29, x29, x29, dyn, 128, 0, x4, 12*FLEN/8, x8, x1, x3) + +inst_5: +// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==x12, rs2==x16, rs3==x9, rd==x16,fs1 == 0 and fe1 == 0x1e and fm1 == 0x134 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x31f and fs3 == 0 and fe3 == 0x1b and fm3 == 0x0a2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x12; op2:x16; op3:x9; dest:x16; op1val:0x7934; op2val:0x2f1f; +op3val:0x6ca2; valaddr_reg:x4; val_offset:15*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x16, x12, x16, x9, dyn, 0, 0, x4, 15*FLEN/8, x8, x1, x3) + +inst_6: +// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==x15, rs2==x19, rs3==x26, rd==x26,fs1 == 0 and fe1 == 0x1e and fm1 == 0x134 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x31f and fs3 == 0 and fe3 == 0x1b and fm3 == 0x0a2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x15; op2:x19; op3:x26; dest:x26; op1val:0x7934; op2val:0x2f1f; +op3val:0x6ca2; valaddr_reg:x4; val_offset:18*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x26, x15, x19, x26, dyn, 32, 0, x4, 18*FLEN/8, x8, x1, x3) + +inst_7: +// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==x27, rs2==x23, rs3==x3, rd==x27,fs1 == 0 and fe1 == 0x1e and fm1 == 0x134 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x31f and fs3 == 0 and fe3 == 0x1b and fm3 == 0x0a2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x27; op2:x23; op3:x3; dest:x27; op1val:0x7934; op2val:0x2f1f; +op3val:0x6ca2; valaddr_reg:x4; val_offset:21*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x27, x27, x23, x3, dyn, 64, 0, x4, 21*FLEN/8, x8, x1, x3) + +inst_8: +// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==x16, rs2==x12, rs3==x12, rd==x24,fs1 == 0 and fe1 == 0x1e and fm1 == 0x134 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x31f and fs3 == 0 and fe3 == 0x1b and fm3 == 0x0a2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x16; op2:x12; op3:x12; dest:x24; op1val:0x7934; op2val:0x2f1f; +op3val:0x2f1f; valaddr_reg:x4; val_offset:24*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x24, x16, x12, x12, dyn, 96, 0, x4, 24*FLEN/8, x8, x1, x3) + +inst_9: +// rs1 == rs2 == rd != rs3, rs1==x5, rs2==x5, rs3==x8, rd==x5,fs1 == 0 and fe1 == 0x1e and fm1 == 0x134 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x31f and fs3 == 0 and fe3 == 0x1b and fm3 == 0x0a2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x5; op2:x5; op3:x8; dest:x5; op1val:0x7934; op2val:0x7934; +op3val:0x6ca2; valaddr_reg:x4; val_offset:27*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x5, x5, x5, x8, dyn, 128, 0, x4, 27*FLEN/8, x8, x1, x3) + +inst_10: +// rs1 == rd == rs3 != rs2, rs1==x0, rs2==x6, rs3==x0, rd==x0,fs1 == 0 and fe1 == 0x1e and fm1 == 0x048 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x175 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1d9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x0; op2:x6; op3:x0; dest:x0; op1val:0x0; op2val:0x3975; +op3val:0x0; valaddr_reg:x4; val_offset:30*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x0, x0, x6, x0, dyn, 0, 0, x4, 30*FLEN/8, x8, x1, x3) + +inst_11: +// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==x17, rs2==x25, rs3==x17, rd==x2,fs1 == 0 and fe1 == 0x1e and fm1 == 0x048 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x175 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1d9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x17; op2:x25; op3:x17; dest:x2; op1val:0x7848; op2val:0x3975; +op3val:0x7848; valaddr_reg:x4; val_offset:33*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x2, x17, x25, x17, dyn, 32, 0, x4, 33*FLEN/8, x8, x1, x3) +RVTEST_VALBASEUPD(x13,test_dataset_1) + +inst_12: +// rs1==x21, rs2==x0, rs3==x1, rd==x8,fs1 == 0 and fe1 == 0x1e and fm1 == 0x048 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x175 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1d9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x21; op2:x0; op3:x1; dest:x8; op1val:0x7848; op2val:0x0; +op3val:0x75d9; valaddr_reg:x13; val_offset:0*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x8, x21, x0, x1, dyn, 64, 0, x13, 0*FLEN/8, x16, x1, x3) + +inst_13: +// rs1==x10, rs2==x7, rs3==x14, rd==x3,fs1 == 0 and fe1 == 0x1e and fm1 == 0x048 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x175 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1d9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x10; op2:x7; op3:x14; dest:x3; op1val:0x7848; op2val:0x3975; +op3val:0x75d9; valaddr_reg:x13; val_offset:3*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x3, x10, x7, x14, dyn, 96, 0, x13, 3*FLEN/8, x16, x1, x12) +RVTEST_SIGBASE(x5,signature_x5_0) + +inst_14: +// rs1==x2, rs2==x21, rs3==x31, rd==x7,fs1 == 0 and fe1 == 0x1e and fm1 == 0x048 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x175 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1d9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x2; op2:x21; op3:x31; dest:x7; op1val:0x7848; op2val:0x3975; +op3val:0x75d9; valaddr_reg:x13; val_offset:6*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x7, x2, x21, x31, dyn, 128, 0, x13, 6*FLEN/8, x16, x5, x12) + +inst_15: +// rs1==x3, rs2==x14, rs3==x5, rd==x18,fs1 == 0 and fe1 == 0x1a and fm1 == 0x36c and fs2 == 0 and fe2 == 0x12 and fm2 == 0x05f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x3; op2:x14; op3:x5; dest:x18; op1val:0x6b6c; op2val:0x485f; +op3val:0x780e; valaddr_reg:x13; val_offset:9*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x18, x3, x14, x5, dyn, 0, 0, x13, 9*FLEN/8, x16, x5, x12) + +inst_16: +// rs1==x11, rs2==x31, rs3==x20, rd==x17,fs1 == 0 and fe1 == 0x1a and fm1 == 0x36c and fs2 == 0 and fe2 == 0x12 and fm2 == 0x05f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x11; op2:x31; op3:x20; dest:x17; op1val:0x6b6c; op2val:0x485f; +op3val:0x780e; valaddr_reg:x13; val_offset:12*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x17, x11, x31, x20, dyn, 32, 0, x13, 12*FLEN/8, x16, x5, x12) + +inst_17: +// rs1==x4, rs2==x8, rs3==x13, rd==x19,fs1 == 0 and fe1 == 0x1a and fm1 == 0x36c and fs2 == 0 and fe2 == 0x12 and fm2 == 0x05f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x4; op2:x8; op3:x13; dest:x19; op1val:0x6b6c; op2val:0x485f; +op3val:0x780e; valaddr_reg:x13; val_offset:15*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x19, x4, x8, x13, dyn, 64, 0, x13, 15*FLEN/8, x16, x5, x12) + +inst_18: +// rs1==x24, rs2==x9, rs3==x7, rd==x30,fs1 == 0 and fe1 == 0x1a and fm1 == 0x36c and fs2 == 0 and fe2 == 0x12 and fm2 == 0x05f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x24; op2:x9; op3:x7; dest:x30; op1val:0x6b6c; op2val:0x485f; +op3val:0x780e; valaddr_reg:x13; val_offset:18*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x30, x24, x9, x7, dyn, 96, 0, x13, 18*FLEN/8, x16, x5, x12) + +inst_19: +// rs1==x6, rs2==x11, rs3==x24, rd==x14,fs1 == 0 and fe1 == 0x1a and fm1 == 0x36c and fs2 == 0 and fe2 == 0x12 and fm2 == 0x05f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x6; op2:x11; op3:x24; dest:x14; op1val:0x6b6c; op2val:0x485f; +op3val:0x780e; valaddr_reg:x13; val_offset:21*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x14, x6, x11, x24, dyn, 128, 0, x13, 21*FLEN/8, x16, x5, x12) + +inst_20: +// rs1==x20, rs2==x4, rs3==x11, rd==x9,fs1 == 0 and fe1 == 0x1a and fm1 == 0x0cc and fs2 == 0 and fe2 == 0x12 and fm2 == 0x1c7 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2ef and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x20; op2:x4; op3:x11; dest:x9; op1val:0x68cc; op2val:0x49c7; +op3val:0x76ef; valaddr_reg:x13; val_offset:24*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x9, x20, x4, x11, dyn, 0, 0, x13, 24*FLEN/8, x16, x5, x12) + +inst_21: +// rs1==x25, rs2==x2, rs3==x4, rd==x1,fs1 == 0 and fe1 == 0x1a and fm1 == 0x0cc and fs2 == 0 and fe2 == 0x12 and fm2 == 0x1c7 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2ef and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x25; op2:x2; op3:x4; dest:x1; op1val:0x68cc; op2val:0x49c7; +op3val:0x76ef; valaddr_reg:x13; val_offset:27*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x1, x25, x2, x4, dyn, 32, 0, x13, 27*FLEN/8, x16, x5, x12) + +inst_22: +// rs1==x28, rs2==x20, rs3==x18, rd==x15,fs1 == 0 and fe1 == 0x1a and fm1 == 0x0cc and fs2 == 0 and fe2 == 0x12 and fm2 == 0x1c7 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2ef and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x28; op2:x20; op3:x18; dest:x15; op1val:0x68cc; op2val:0x49c7; +op3val:0x76ef; valaddr_reg:x13; val_offset:30*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x15, x28, x20, x18, dyn, 64, 0, x13, 30*FLEN/8, x16, x5, x12) +RVTEST_VALBASEUPD(x10,test_dataset_2) + +inst_23: +// rs1==x13, rs2==x28, rs3==x19, rd==x31,fs1 == 0 and fe1 == 0x1a and fm1 == 0x0cc and fs2 == 0 and fe2 == 0x12 and fm2 == 0x1c7 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2ef and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x13; op2:x28; op3:x19; dest:x31; op1val:0x68cc; op2val:0x49c7; +op3val:0x76ef; valaddr_reg:x10; val_offset:0*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x13, x28, x19, dyn, 96, 0, x10, 0*FLEN/8, x11, x5, x12) + +inst_24: +// rs1==x19, rs2==x26, rs3==x27, rd==x23,fs1 == 0 and fe1 == 0x1a and fm1 == 0x0cc and fs2 == 0 and fe2 == 0x12 and fm2 == 0x1c7 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2ef and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x19; op2:x26; op3:x27; dest:x23; op1val:0x68cc; op2val:0x49c7; +op3val:0x76ef; valaddr_reg:x10; val_offset:3*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x23, x19, x26, x27, dyn, 128, 0, x10, 3*FLEN/8, x11, x5, x12) + +inst_25: +// rs1==x8, rs2==x13, rs3==x15, rd==x28,fs1 == 0 and fe1 == 0x1b and fm1 == 0x078 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x131 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x1cd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x8; op2:x13; op3:x15; dest:x28; op1val:0x6c78; op2val:0x3d31; +op3val:0x6dcd; valaddr_reg:x10; val_offset:6*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x28, x8, x13, x15, dyn, 0, 0, x10, 6*FLEN/8, x11, x5, x7) + +inst_26: +// rs1==x30, rs2==x3, rs3==x23, rd==x22,fs1 == 0 and fe1 == 0x1b and fm1 == 0x078 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x131 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x1cd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x3; op3:x23; dest:x22; op1val:0x6c78; op2val:0x3d31; +op3val:0x6dcd; valaddr_reg:x10; val_offset:9*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x22, x30, x3, x23, dyn, 32, 0, x10, 9*FLEN/8, x11, x5, x7) +RVTEST_SIGBASE(x2,signature_x2_0) + +inst_27: +// rs1==x31, rs2==x15, rs3==x28, rd==x6,fs1 == 0 and fe1 == 0x1b and fm1 == 0x078 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x131 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x1cd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x31; op2:x15; op3:x28; dest:x6; op1val:0x6c78; op2val:0x3d31; +op3val:0x6dcd; valaddr_reg:x10; val_offset:12*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x6, x31, x15, x28, dyn, 64, 0, x10, 12*FLEN/8, x11, x2, x7) + +inst_28: +// rs1==x26, rs2==x1, rs3==x6, rd==x21,fs1 == 0 and fe1 == 0x1b and fm1 == 0x078 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x131 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x1cd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x26; op2:x1; op3:x6; dest:x21; op1val:0x6c78; op2val:0x3d31; +op3val:0x6dcd; valaddr_reg:x10; val_offset:15*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x21, x26, x1, x6, dyn, 96, 0, x10, 15*FLEN/8, x11, x2, x7) + +inst_29: +// rs1==x1, rs2==x17, rs3==x16, rd==x25,fs1 == 0 and fe1 == 0x1b and fm1 == 0x078 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x131 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x1cd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x1; op2:x17; op3:x16; dest:x25; op1val:0x6c78; op2val:0x3d31; +op3val:0x6dcd; valaddr_reg:x10; val_offset:18*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x25, x1, x17, x16, dyn, 128, 0, x10, 18*FLEN/8, x11, x2, x7) + +inst_30: +// rs1==x9, rs2==x27, rs3==x2, rd==x4,fs1 == 0 and fe1 == 0x1d and fm1 == 0x2ca and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3ca and fs3 == 0 and fe3 == 0x1e and fm3 == 0x29c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x9; op2:x27; op3:x2; dest:x4; op1val:0x76ca; op2val:0x3fca; +op3val:0x7a9c; valaddr_reg:x10; val_offset:21*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x4, x9, x27, x2, dyn, 0, 0, x10, 21*FLEN/8, x11, x2, x7) + +inst_31: +// rs1==x14, rs2==x24, rs3==x21, rd==x12,fs1 == 0 and fe1 == 0x1d and fm1 == 0x2ca and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3ca and fs3 == 0 and fe3 == 0x1e and fm3 == 0x29c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x14; op2:x24; op3:x21; dest:x12; op1val:0x76ca; op2val:0x3fca; +op3val:0x7a9c; valaddr_reg:x10; val_offset:24*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x12, x14, x24, x21, dyn, 32, 0, x10, 24*FLEN/8, x11, x2, x7) +RVTEST_VALBASEUPD(x1,test_dataset_3) + +inst_32: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2ca and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3ca and fs3 == 0 and fe3 == 0x1e and fm3 == 0x29c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76ca; op2val:0x3fca; +op3val:0x7a9c; valaddr_reg:x1; val_offset:0*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 0*FLEN/8, x3, x2, x7) + +inst_33: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2ca and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3ca and fs3 == 0 and fe3 == 0x1e and fm3 == 0x29c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76ca; op2val:0x3fca; +op3val:0x7a9c; valaddr_reg:x1; val_offset:3*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3*FLEN/8, x3, x2, x7) + +inst_34: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2ca and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3ca and fs3 == 0 and fe3 == 0x1e and fm3 == 0x29c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76ca; op2val:0x3fca; +op3val:0x7a9c; valaddr_reg:x1; val_offset:6*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 6*FLEN/8, x3, x2, x7) + +inst_35: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3eb and fs2 == 0 and fe2 == 0x0f and fm2 == 0x336 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x323 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6feb; op2val:0x3f36; +op3val:0x7323; valaddr_reg:x1; val_offset:9*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 9*FLEN/8, x3, x2, x7) + +inst_36: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3eb and fs2 == 0 and fe2 == 0x0f and fm2 == 0x336 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x323 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6feb; op2val:0x3f36; +op3val:0x7323; valaddr_reg:x1; val_offset:12*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 12*FLEN/8, x3, x2, x7) + +inst_37: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3eb and fs2 == 0 and fe2 == 0x0f and fm2 == 0x336 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x323 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6feb; op2val:0x3f36; +op3val:0x7323; valaddr_reg:x1; val_offset:15*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 15*FLEN/8, x3, x2, x7) + +inst_38: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3eb and fs2 == 0 and fe2 == 0x0f and fm2 == 0x336 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x323 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6feb; op2val:0x3f36; +op3val:0x7323; valaddr_reg:x1; val_offset:18*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 18*FLEN/8, x3, x2, x7) + +inst_39: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3eb and fs2 == 0 and fe2 == 0x0f and fm2 == 0x336 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x323 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6feb; op2val:0x3f36; +op3val:0x7323; valaddr_reg:x1; val_offset:21*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 21*FLEN/8, x3, x2, x7) + +inst_40: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x104 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x20a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x393 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7904; op2val:0x3e0a; +op3val:0x7b93; valaddr_reg:x1; val_offset:24*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 24*FLEN/8, x3, x2, x7) + +inst_41: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x104 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x20a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x393 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7904; op2val:0x3e0a; +op3val:0x7b93; valaddr_reg:x1; val_offset:27*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 27*FLEN/8, x3, x2, x7) + +inst_42: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x104 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x20a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x393 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7904; op2val:0x3e0a; +op3val:0x7b93; valaddr_reg:x1; val_offset:30*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 30*FLEN/8, x3, x2, x7) + +inst_43: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x104 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x20a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x393 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7904; op2val:0x3e0a; +op3val:0x7b93; valaddr_reg:x1; val_offset:33*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 33*FLEN/8, x3, x2, x7) + +inst_44: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x104 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x20a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x393 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7904; op2val:0x3e0a; +op3val:0x7b93; valaddr_reg:x1; val_offset:36*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 36*FLEN/8, x3, x2, x7) + +inst_45: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x17f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x258 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x789d; op2val:0x397f; +op3val:0x7658; valaddr_reg:x1; val_offset:39*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 39*FLEN/8, x3, x2, x7) + +inst_46: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x17f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x258 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x789d; op2val:0x397f; +op3val:0x7658; valaddr_reg:x1; val_offset:42*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 42*FLEN/8, x3, x2, x7) + +inst_47: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x17f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x258 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x789d; op2val:0x397f; +op3val:0x7658; valaddr_reg:x1; val_offset:45*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 45*FLEN/8, x3, x2, x7) + +inst_48: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x17f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x258 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x789d; op2val:0x397f; +op3val:0x7658; valaddr_reg:x1; val_offset:48*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 48*FLEN/8, x3, x2, x7) + +inst_49: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x17f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x258 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x789d; op2val:0x397f; +op3val:0x7658; valaddr_reg:x1; val_offset:51*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 51*FLEN/8, x3, x2, x7) + +inst_50: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ce and fs2 == 0 and fe2 == 0x0a and fm2 == 0x21c and fs3 == 0 and fe3 == 0x1a and fm3 == 0x1f6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bce; op2val:0x2a1c; +op3val:0x69f6; valaddr_reg:x1; val_offset:54*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 54*FLEN/8, x3, x2, x7) + +inst_51: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ce and fs2 == 0 and fe2 == 0x0a and fm2 == 0x21c and fs3 == 0 and fe3 == 0x1a and fm3 == 0x1f6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bce; op2val:0x2a1c; +op3val:0x69f6; valaddr_reg:x1; val_offset:57*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 57*FLEN/8, x3, x2, x7) + +inst_52: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ce and fs2 == 0 and fe2 == 0x0a and fm2 == 0x21c and fs3 == 0 and fe3 == 0x1a and fm3 == 0x1f6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bce; op2val:0x2a1c; +op3val:0x69f6; valaddr_reg:x1; val_offset:60*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 60*FLEN/8, x3, x2, x7) + +inst_53: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ce and fs2 == 0 and fe2 == 0x0a and fm2 == 0x21c and fs3 == 0 and fe3 == 0x1a and fm3 == 0x1f6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bce; op2val:0x2a1c; +op3val:0x69f6; valaddr_reg:x1; val_offset:63*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 63*FLEN/8, x3, x2, x7) + +inst_54: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ce and fs2 == 0 and fe2 == 0x0a and fm2 == 0x21c and fs3 == 0 and fe3 == 0x1a and fm3 == 0x1f6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bce; op2val:0x2a1c; +op3val:0x69f6; valaddr_reg:x1; val_offset:66*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 66*FLEN/8, x3, x2, x7) + +inst_55: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2dd and fs2 == 0 and fe2 == 0x0d and fm2 == 0x165 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7add; op2val:0x3565; +op3val:0x74a1; valaddr_reg:x1; val_offset:69*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 69*FLEN/8, x3, x2, x7) + +inst_56: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2dd and fs2 == 0 and fe2 == 0x0d and fm2 == 0x165 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7add; op2val:0x3565; +op3val:0x74a1; valaddr_reg:x1; val_offset:72*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 72*FLEN/8, x3, x2, x7) + +inst_57: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2dd and fs2 == 0 and fe2 == 0x0d and fm2 == 0x165 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7add; op2val:0x3565; +op3val:0x74a1; valaddr_reg:x1; val_offset:75*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 75*FLEN/8, x3, x2, x7) + +inst_58: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2dd and fs2 == 0 and fe2 == 0x0d and fm2 == 0x165 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7add; op2val:0x3565; +op3val:0x74a1; valaddr_reg:x1; val_offset:78*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 78*FLEN/8, x3, x2, x7) + +inst_59: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2dd and fs2 == 0 and fe2 == 0x0d and fm2 == 0x165 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7add; op2val:0x3565; +op3val:0x74a1; valaddr_reg:x1; val_offset:81*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 81*FLEN/8, x3, x2, x7) + +inst_60: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x09d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x288 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x389 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x709d; op2val:0x3a88; +op3val:0x6f89; valaddr_reg:x1; val_offset:84*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 84*FLEN/8, x3, x2, x7) + +inst_61: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x09d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x288 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x389 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x709d; op2val:0x3a88; +op3val:0x6f89; valaddr_reg:x1; val_offset:87*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 87*FLEN/8, x3, x2, x7) + +inst_62: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x09d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x288 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x389 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x709d; op2val:0x3a88; +op3val:0x6f89; valaddr_reg:x1; val_offset:90*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 90*FLEN/8, x3, x2, x7) + +inst_63: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x09d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x288 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x389 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x709d; op2val:0x3a88; +op3val:0x6f89; valaddr_reg:x1; val_offset:93*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 93*FLEN/8, x3, x2, x7) + +inst_64: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x09d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x288 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x389 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x709d; op2val:0x3a88; +op3val:0x6f89; valaddr_reg:x1; val_offset:96*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 96*FLEN/8, x3, x2, x7) + +inst_65: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ee and fs2 == 0 and fe2 == 0x10 and fm2 == 0x14a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x286 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74ee; op2val:0x414a; +op3val:0x7a86; valaddr_reg:x1; val_offset:99*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 99*FLEN/8, x3, x2, x7) + +inst_66: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ee and fs2 == 0 and fe2 == 0x10 and fm2 == 0x14a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x286 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74ee; op2val:0x414a; +op3val:0x7a86; valaddr_reg:x1; val_offset:102*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 102*FLEN/8, x3, x2, x7) + +inst_67: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ee and fs2 == 0 and fe2 == 0x10 and fm2 == 0x14a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x286 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74ee; op2val:0x414a; +op3val:0x7a86; valaddr_reg:x1; val_offset:105*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 105*FLEN/8, x3, x2, x7) + +inst_68: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ee and fs2 == 0 and fe2 == 0x10 and fm2 == 0x14a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x286 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74ee; op2val:0x414a; +op3val:0x7a86; valaddr_reg:x1; val_offset:108*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 108*FLEN/8, x3, x2, x7) + +inst_69: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ee and fs2 == 0 and fe2 == 0x10 and fm2 == 0x14a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x286 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74ee; op2val:0x414a; +op3val:0x7a86; valaddr_reg:x1; val_offset:111*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 111*FLEN/8, x3, x2, x7) + +inst_70: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x26f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71c7; op2val:0x426f; +op3val:0x78a6; valaddr_reg:x1; val_offset:114*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 114*FLEN/8, x3, x2, x7) + +inst_71: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x26f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71c7; op2val:0x426f; +op3val:0x78a6; valaddr_reg:x1; val_offset:117*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 117*FLEN/8, x3, x2, x7) + +inst_72: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x26f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71c7; op2val:0x426f; +op3val:0x78a6; valaddr_reg:x1; val_offset:120*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 120*FLEN/8, x3, x2, x7) + +inst_73: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x26f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71c7; op2val:0x426f; +op3val:0x78a6; valaddr_reg:x1; val_offset:123*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 123*FLEN/8, x3, x2, x7) + +inst_74: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x26f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71c7; op2val:0x426f; +op3val:0x78a6; valaddr_reg:x1; val_offset:126*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 126*FLEN/8, x3, x2, x7) + +inst_75: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x11b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0a9 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1f4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x791b; op2val:0x38a9; +op3val:0x75f4; valaddr_reg:x1; val_offset:129*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 129*FLEN/8, x3, x2, x7) + +inst_76: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x11b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0a9 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1f4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x791b; op2val:0x38a9; +op3val:0x75f4; valaddr_reg:x1; val_offset:132*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 132*FLEN/8, x3, x2, x7) + +inst_77: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x11b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0a9 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1f4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x791b; op2val:0x38a9; +op3val:0x75f4; valaddr_reg:x1; val_offset:135*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 135*FLEN/8, x3, x2, x7) + +inst_78: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x11b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0a9 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1f4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x791b; op2val:0x38a9; +op3val:0x75f4; valaddr_reg:x1; val_offset:138*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 138*FLEN/8, x3, x2, x7) + +inst_79: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x11b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0a9 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1f4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x791b; op2val:0x38a9; +op3val:0x75f4; valaddr_reg:x1; val_offset:141*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 141*FLEN/8, x3, x2, x7) + +inst_80: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x061 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x356 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x004 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7861; op2val:0x2f56; +op3val:0x6c04; valaddr_reg:x1; val_offset:144*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 144*FLEN/8, x3, x2, x7) + +inst_81: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x061 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x356 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x004 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7861; op2val:0x2f56; +op3val:0x6c04; valaddr_reg:x1; val_offset:147*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 147*FLEN/8, x3, x2, x7) + +inst_82: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x061 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x356 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x004 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7861; op2val:0x2f56; +op3val:0x6c04; valaddr_reg:x1; val_offset:150*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 150*FLEN/8, x3, x2, x7) + +inst_83: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x061 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x356 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x004 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7861; op2val:0x2f56; +op3val:0x6c04; valaddr_reg:x1; val_offset:153*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 153*FLEN/8, x3, x2, x7) + +inst_84: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x061 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x356 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x004 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7861; op2val:0x2f56; +op3val:0x6c04; valaddr_reg:x1; val_offset:156*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 156*FLEN/8, x3, x2, x7) + +inst_85: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3a0 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x2e8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x296 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ba0; op2val:0x42e8; +op3val:0x7296; valaddr_reg:x1; val_offset:159*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 159*FLEN/8, x3, x2, x7) + +inst_86: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3a0 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x2e8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x296 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ba0; op2val:0x42e8; +op3val:0x7296; valaddr_reg:x1; val_offset:162*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 162*FLEN/8, x3, x2, x7) + +inst_87: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3a0 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x2e8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x296 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ba0; op2val:0x42e8; +op3val:0x7296; valaddr_reg:x1; val_offset:165*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 165*FLEN/8, x3, x2, x7) + +inst_88: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3a0 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x2e8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x296 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ba0; op2val:0x42e8; +op3val:0x7296; valaddr_reg:x1; val_offset:168*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 168*FLEN/8, x3, x2, x7) + +inst_89: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3a0 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x2e8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x296 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ba0; op2val:0x42e8; +op3val:0x7296; valaddr_reg:x1; val_offset:171*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 171*FLEN/8, x3, x2, x7) + +inst_90: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x170 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x107 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2d6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7970; op2val:0x3907; +op3val:0x76d6; valaddr_reg:x1; val_offset:174*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 174*FLEN/8, x3, x2, x7) + +inst_91: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x170 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x107 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2d6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7970; op2val:0x3907; +op3val:0x76d6; valaddr_reg:x1; val_offset:177*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 177*FLEN/8, x3, x2, x7) + +inst_92: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x170 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x107 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2d6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7970; op2val:0x3907; +op3val:0x76d6; valaddr_reg:x1; val_offset:180*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 180*FLEN/8, x3, x2, x7) + +inst_93: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x170 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x107 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2d6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7970; op2val:0x3907; +op3val:0x76d6; valaddr_reg:x1; val_offset:183*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 183*FLEN/8, x3, x2, x7) + +inst_94: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x170 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x107 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2d6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7970; op2val:0x3907; +op3val:0x76d6; valaddr_reg:x1; val_offset:186*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 186*FLEN/8, x3, x2, x7) + +inst_95: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x106 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x374 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0ae and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7506; op2val:0x3f74; +op3val:0x78ae; valaddr_reg:x1; val_offset:189*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 189*FLEN/8, x3, x2, x7) + +inst_96: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x106 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x374 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0ae and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7506; op2val:0x3f74; +op3val:0x78ae; valaddr_reg:x1; val_offset:192*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 192*FLEN/8, x3, x2, x7) + +inst_97: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x106 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x374 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0ae and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7506; op2val:0x3f74; +op3val:0x78ae; valaddr_reg:x1; val_offset:195*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 195*FLEN/8, x3, x2, x7) + +inst_98: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x106 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x374 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0ae and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7506; op2val:0x3f74; +op3val:0x78ae; valaddr_reg:x1; val_offset:198*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 198*FLEN/8, x3, x2, x7) + +inst_99: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x106 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x374 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0ae and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7506; op2val:0x3f74; +op3val:0x78ae; valaddr_reg:x1; val_offset:201*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 201*FLEN/8, x3, x2, x7) + +inst_100: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x33f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x14a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0cb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x773f; op2val:0x394a; +op3val:0x74cb; valaddr_reg:x1; val_offset:204*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 204*FLEN/8, x3, x2, x7) + +inst_101: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x33f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x14a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0cb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x773f; op2val:0x394a; +op3val:0x74cb; valaddr_reg:x1; val_offset:207*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 207*FLEN/8, x3, x2, x7) + +inst_102: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x33f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x14a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0cb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x773f; op2val:0x394a; +op3val:0x74cb; valaddr_reg:x1; val_offset:210*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 210*FLEN/8, x3, x2, x7) + +inst_103: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x33f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x14a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0cb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x773f; op2val:0x394a; +op3val:0x74cb; valaddr_reg:x1; val_offset:213*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 213*FLEN/8, x3, x2, x7) + +inst_104: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x33f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x14a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0cb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x773f; op2val:0x394a; +op3val:0x74cb; valaddr_reg:x1; val_offset:216*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 216*FLEN/8, x3, x2, x7) + +inst_105: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x30a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x196 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5a; op2val:0x3b0a; +op3val:0x7996; valaddr_reg:x1; val_offset:219*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 219*FLEN/8, x3, x2, x7) + +inst_106: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x30a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x196 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5a; op2val:0x3b0a; +op3val:0x7996; valaddr_reg:x1; val_offset:222*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 222*FLEN/8, x3, x2, x7) + +inst_107: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x30a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x196 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5a; op2val:0x3b0a; +op3val:0x7996; valaddr_reg:x1; val_offset:225*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 225*FLEN/8, x3, x2, x7) + +inst_108: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x30a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x196 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5a; op2val:0x3b0a; +op3val:0x7996; valaddr_reg:x1; val_offset:228*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 228*FLEN/8, x3, x2, x7) + +inst_109: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x30a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x196 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5a; op2val:0x3b0a; +op3val:0x7996; valaddr_reg:x1; val_offset:231*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 231*FLEN/8, x3, x2, x7) + +inst_110: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3ce and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0b4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x097 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73ce; op2val:0x40b4; +op3val:0x7897; valaddr_reg:x1; val_offset:234*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 234*FLEN/8, x3, x2, x7) + +inst_111: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3ce and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0b4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x097 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73ce; op2val:0x40b4; +op3val:0x7897; valaddr_reg:x1; val_offset:237*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 237*FLEN/8, x3, x2, x7) + +inst_112: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3ce and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0b4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x097 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73ce; op2val:0x40b4; +op3val:0x7897; valaddr_reg:x1; val_offset:240*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 240*FLEN/8, x3, x2, x7) + +inst_113: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3ce and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0b4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x097 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73ce; op2val:0x40b4; +op3val:0x7897; valaddr_reg:x1; val_offset:243*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 243*FLEN/8, x3, x2, x7) + +inst_114: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3ce and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0b4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x097 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73ce; op2val:0x40b4; +op3val:0x7897; valaddr_reg:x1; val_offset:246*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 246*FLEN/8, x3, x2, x7) + +inst_115: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x033 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2aa and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7833; op2val:0x3eaa; +op3val:0x7aff; valaddr_reg:x1; val_offset:249*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 249*FLEN/8, x3, x2, x7) + +inst_116: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x033 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2aa and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7833; op2val:0x3eaa; +op3val:0x7aff; valaddr_reg:x1; val_offset:252*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 252*FLEN/8, x3, x2, x7) + +inst_117: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x033 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2aa and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7833; op2val:0x3eaa; +op3val:0x7aff; valaddr_reg:x1; val_offset:255*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 255*FLEN/8, x3, x2, x7) + +inst_118: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x033 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2aa and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7833; op2val:0x3eaa; +op3val:0x7aff; valaddr_reg:x1; val_offset:258*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 258*FLEN/8, x3, x2, x7) + +inst_119: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x033 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2aa and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7833; op2val:0x3eaa; +op3val:0x7aff; valaddr_reg:x1; val_offset:261*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 261*FLEN/8, x3, x2, x7) + +inst_120: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x250 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x09a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79d5; op2val:0x3650; +op3val:0x749a; valaddr_reg:x1; val_offset:264*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 264*FLEN/8, x3, x2, x7) + +inst_121: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x250 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x09a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79d5; op2val:0x3650; +op3val:0x749a; valaddr_reg:x1; val_offset:267*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 267*FLEN/8, x3, x2, x7) + +inst_122: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x250 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x09a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79d5; op2val:0x3650; +op3val:0x749a; valaddr_reg:x1; val_offset:270*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 270*FLEN/8, x3, x2, x7) + +inst_123: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x250 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x09a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79d5; op2val:0x3650; +op3val:0x749a; valaddr_reg:x1; val_offset:273*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 273*FLEN/8, x3, x2, x7) + +inst_124: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x250 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x09a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79d5; op2val:0x3650; +op3val:0x749a; valaddr_reg:x1; val_offset:276*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 276*FLEN/8, x3, x2, x7) + +inst_125: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3b5 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x38d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd6; op2val:0x2fb5; +op3val:0x6f8d; valaddr_reg:x1; val_offset:279*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 279*FLEN/8, x3, x2, x7) + +inst_126: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3b5 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x38d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd6; op2val:0x2fb5; +op3val:0x6f8d; valaddr_reg:x1; val_offset:282*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 282*FLEN/8, x3, x2, x7) + +inst_127: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3b5 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x38d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd6; op2val:0x2fb5; +op3val:0x6f8d; valaddr_reg:x1; val_offset:285*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 285*FLEN/8, x3, x2, x7) + +inst_128: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3b5 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x38d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd6; op2val:0x2fb5; +op3val:0x6f8d; valaddr_reg:x1; val_offset:288*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 288*FLEN/8, x3, x2, x7) + +inst_129: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3b5 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x38d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd6; op2val:0x2fb5; +op3val:0x6f8d; valaddr_reg:x1; val_offset:291*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 291*FLEN/8, x3, x2, x7) + +inst_130: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2af and fs2 == 0 and fe2 == 0x0f and fm2 == 0x33e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x20d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76af; op2val:0x3f3e; +op3val:0x7a0d; valaddr_reg:x1; val_offset:294*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 294*FLEN/8, x3, x2, x7) + +inst_131: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2af and fs2 == 0 and fe2 == 0x0f and fm2 == 0x33e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x20d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76af; op2val:0x3f3e; +op3val:0x7a0d; valaddr_reg:x1; val_offset:297*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 297*FLEN/8, x3, x2, x7) + +inst_132: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2af and fs2 == 0 and fe2 == 0x0f and fm2 == 0x33e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x20d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76af; op2val:0x3f3e; +op3val:0x7a0d; valaddr_reg:x1; val_offset:300*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 300*FLEN/8, x3, x2, x7) + +inst_133: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2af and fs2 == 0 and fe2 == 0x0f and fm2 == 0x33e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x20d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76af; op2val:0x3f3e; +op3val:0x7a0d; valaddr_reg:x1; val_offset:303*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 303*FLEN/8, x3, x2, x7) + +inst_134: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2af and fs2 == 0 and fe2 == 0x0f and fm2 == 0x33e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x20d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76af; op2val:0x3f3e; +op3val:0x7a0d; valaddr_reg:x1; val_offset:306*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 306*FLEN/8, x3, x2, x7) + +inst_135: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0dc and fs2 == 0 and fe2 == 0x10 and fm2 == 0x26f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3d1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70dc; op2val:0x426f; +op3val:0x77d1; valaddr_reg:x1; val_offset:309*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 309*FLEN/8, x3, x2, x7) + +inst_136: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0dc and fs2 == 0 and fe2 == 0x10 and fm2 == 0x26f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3d1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70dc; op2val:0x426f; +op3val:0x77d1; valaddr_reg:x1; val_offset:312*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 312*FLEN/8, x3, x2, x7) + +inst_137: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0dc and fs2 == 0 and fe2 == 0x10 and fm2 == 0x26f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3d1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70dc; op2val:0x426f; +op3val:0x77d1; valaddr_reg:x1; val_offset:315*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 315*FLEN/8, x3, x2, x7) + +inst_138: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0dc and fs2 == 0 and fe2 == 0x10 and fm2 == 0x26f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3d1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70dc; op2val:0x426f; +op3val:0x77d1; valaddr_reg:x1; val_offset:318*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 318*FLEN/8, x3, x2, x7) + +inst_139: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0dc and fs2 == 0 and fe2 == 0x10 and fm2 == 0x26f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3d1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70dc; op2val:0x426f; +op3val:0x77d1; valaddr_reg:x1; val_offset:321*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 321*FLEN/8, x3, x2, x7) + +inst_140: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x104 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x042 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x157 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6904; op2val:0x4c42; +op3val:0x7957; valaddr_reg:x1; val_offset:324*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 324*FLEN/8, x3, x2, x7) + +inst_141: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x104 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x042 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x157 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6904; op2val:0x4c42; +op3val:0x7957; valaddr_reg:x1; val_offset:327*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 327*FLEN/8, x3, x2, x7) + +inst_142: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x104 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x042 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x157 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6904; op2val:0x4c42; +op3val:0x7957; valaddr_reg:x1; val_offset:330*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 330*FLEN/8, x3, x2, x7) + +inst_143: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x104 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x042 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x157 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6904; op2val:0x4c42; +op3val:0x7957; valaddr_reg:x1; val_offset:333*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 333*FLEN/8, x3, x2, x7) + +inst_144: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x104 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x042 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x157 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6904; op2val:0x4c42; +op3val:0x7957; valaddr_reg:x1; val_offset:336*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 336*FLEN/8, x3, x2, x7) + +inst_145: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x21d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x094 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a1d; op2val:0x39fe; +op3val:0x7894; valaddr_reg:x1; val_offset:339*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 339*FLEN/8, x3, x2, x7) + +inst_146: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x21d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x094 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a1d; op2val:0x39fe; +op3val:0x7894; valaddr_reg:x1; val_offset:342*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 342*FLEN/8, x3, x2, x7) + +inst_147: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x21d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x094 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a1d; op2val:0x39fe; +op3val:0x7894; valaddr_reg:x1; val_offset:345*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 345*FLEN/8, x3, x2, x7) + +inst_148: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x21d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x094 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a1d; op2val:0x39fe; +op3val:0x7894; valaddr_reg:x1; val_offset:348*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 348*FLEN/8, x3, x2, x7) + +inst_149: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x21d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x094 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a1d; op2val:0x39fe; +op3val:0x7894; valaddr_reg:x1; val_offset:351*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 351*FLEN/8, x3, x2, x7) + +inst_150: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x300 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1bb and fs3 == 0 and fe3 == 0x1d and fm3 == 0x104 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b00; op2val:0x35bb; +op3val:0x7504; valaddr_reg:x1; val_offset:354*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 354*FLEN/8, x3, x2, x7) + +inst_151: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x300 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1bb and fs3 == 0 and fe3 == 0x1d and fm3 == 0x104 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b00; op2val:0x35bb; +op3val:0x7504; valaddr_reg:x1; val_offset:357*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 357*FLEN/8, x3, x2, x7) + +inst_152: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x300 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1bb and fs3 == 0 and fe3 == 0x1d and fm3 == 0x104 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b00; op2val:0x35bb; +op3val:0x7504; valaddr_reg:x1; val_offset:360*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 360*FLEN/8, x3, x2, x7) + +inst_153: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x300 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1bb and fs3 == 0 and fe3 == 0x1d and fm3 == 0x104 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b00; op2val:0x35bb; +op3val:0x7504; valaddr_reg:x1; val_offset:363*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 363*FLEN/8, x3, x2, x7) + +inst_154: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x300 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1bb and fs3 == 0 and fe3 == 0x1d and fm3 == 0x104 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b00; op2val:0x35bb; +op3val:0x7504; valaddr_reg:x1; val_offset:366*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 366*FLEN/8, x3, x2, x7) +RVTEST_SIGBASE(x2,signature_x2_1) + +inst_155: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x18f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x798f; op2val:0x3ad6; +op3val:0x78c0; valaddr_reg:x1; val_offset:369*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 369*FLEN/8, x3, x2, x7) + +inst_156: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x18f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0c0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x798f; op2val:0x3ad6; +op3val:0x78c0; valaddr_reg:x1; val_offset:372*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 372*FLEN/8, x3, x2, x7) + +inst_157: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x18f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0c0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x798f; op2val:0x3ad6; +op3val:0x78c0; valaddr_reg:x1; val_offset:375*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 375*FLEN/8, x3, x2, x7) + +inst_158: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x18f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0c0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x798f; op2val:0x3ad6; +op3val:0x78c0; valaddr_reg:x1; val_offset:378*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 378*FLEN/8, x3, x2, x7) + +inst_159: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x18f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0c0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x798f; op2val:0x3ad6; +op3val:0x78c0; valaddr_reg:x1; val_offset:381*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 381*FLEN/8, x3, x2, x7) + +inst_160: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x24b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x34b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78a3; op2val:0x3a4b; +op3val:0x774b; valaddr_reg:x1; val_offset:384*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 384*FLEN/8, x3, x2, x7) + +inst_161: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x24b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x34b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78a3; op2val:0x3a4b; +op3val:0x774b; valaddr_reg:x1; val_offset:387*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 387*FLEN/8, x3, x2, x7) + +inst_162: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x24b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x34b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78a3; op2val:0x3a4b; +op3val:0x774b; valaddr_reg:x1; val_offset:390*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 390*FLEN/8, x3, x2, x7) + +inst_163: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x24b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x34b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78a3; op2val:0x3a4b; +op3val:0x774b; valaddr_reg:x1; val_offset:393*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 393*FLEN/8, x3, x2, x7) + +inst_164: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x24b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x34b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78a3; op2val:0x3a4b; +op3val:0x774b; valaddr_reg:x1; val_offset:396*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 396*FLEN/8, x3, x2, x7) + +inst_165: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x07f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x38d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ab7; op2val:0x3c7f; +op3val:0x7b8d; valaddr_reg:x1; val_offset:399*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 399*FLEN/8, x3, x2, x7) + +inst_166: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x07f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x38d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ab7; op2val:0x3c7f; +op3val:0x7b8d; valaddr_reg:x1; val_offset:402*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 402*FLEN/8, x3, x2, x7) + +inst_167: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x07f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x38d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ab7; op2val:0x3c7f; +op3val:0x7b8d; valaddr_reg:x1; val_offset:405*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 405*FLEN/8, x3, x2, x7) + +inst_168: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x07f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x38d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ab7; op2val:0x3c7f; +op3val:0x7b8d; valaddr_reg:x1; val_offset:408*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 408*FLEN/8, x3, x2, x7) + +inst_169: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x07f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x38d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ab7; op2val:0x3c7f; +op3val:0x7b8d; valaddr_reg:x1; val_offset:411*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 411*FLEN/8, x3, x2, x7) + +inst_170: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x394 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x19a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7794; op2val:0x3d9a; +op3val:0x794f; valaddr_reg:x1; val_offset:414*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 414*FLEN/8, x3, x2, x7) + +inst_171: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x394 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x19a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7794; op2val:0x3d9a; +op3val:0x794f; valaddr_reg:x1; val_offset:417*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 417*FLEN/8, x3, x2, x7) + +inst_172: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x394 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x19a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7794; op2val:0x3d9a; +op3val:0x794f; valaddr_reg:x1; val_offset:420*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 420*FLEN/8, x3, x2, x7) + +inst_173: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x394 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x19a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7794; op2val:0x3d9a; +op3val:0x794f; valaddr_reg:x1; val_offset:423*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 423*FLEN/8, x3, x2, x7) + +inst_174: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x394 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x19a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7794; op2val:0x3d9a; +op3val:0x794f; valaddr_reg:x1; val_offset:426*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 426*FLEN/8, x3, x2, x7) + +inst_175: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3c3 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x1c7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x19b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6bc3; op2val:0x49c7; +op3val:0x799b; valaddr_reg:x1; val_offset:429*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 429*FLEN/8, x3, x2, x7) + +inst_176: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3c3 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x1c7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x19b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6bc3; op2val:0x49c7; +op3val:0x799b; valaddr_reg:x1; val_offset:432*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 432*FLEN/8, x3, x2, x7) + +inst_177: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3c3 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x1c7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x19b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6bc3; op2val:0x49c7; +op3val:0x799b; valaddr_reg:x1; val_offset:435*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 435*FLEN/8, x3, x2, x7) + +inst_178: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3c3 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x1c7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x19b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6bc3; op2val:0x49c7; +op3val:0x799b; valaddr_reg:x1; val_offset:438*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 438*FLEN/8, x3, x2, x7) + +inst_179: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3c3 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x1c7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x19b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6bc3; op2val:0x49c7; +op3val:0x799b; valaddr_reg:x1; val_offset:441*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 441*FLEN/8, x3, x2, x7) + +inst_180: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x223 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x792c; op2val:0x3e23; +op3val:0x7bf0; valaddr_reg:x1; val_offset:444*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 444*FLEN/8, x3, x2, x7) + +inst_181: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x223 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3f0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x792c; op2val:0x3e23; +op3val:0x7bf0; valaddr_reg:x1; val_offset:447*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 447*FLEN/8, x3, x2, x7) + +inst_182: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x223 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3f0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x792c; op2val:0x3e23; +op3val:0x7bf0; valaddr_reg:x1; val_offset:450*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 450*FLEN/8, x3, x2, x7) + +inst_183: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x223 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3f0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x792c; op2val:0x3e23; +op3val:0x7bf0; valaddr_reg:x1; val_offset:453*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 453*FLEN/8, x3, x2, x7) + +inst_184: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x223 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3f0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x792c; op2val:0x3e23; +op3val:0x7bf0; valaddr_reg:x1; val_offset:456*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 456*FLEN/8, x3, x2, x7) + +inst_185: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x292 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x18a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x08d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a92; op2val:0x358a; +op3val:0x748d; valaddr_reg:x1; val_offset:459*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 459*FLEN/8, x3, x2, x7) + +inst_186: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x292 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x18a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x08d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a92; op2val:0x358a; +op3val:0x748d; valaddr_reg:x1; val_offset:462*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 462*FLEN/8, x3, x2, x7) + +inst_187: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x292 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x18a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x08d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a92; op2val:0x358a; +op3val:0x748d; valaddr_reg:x1; val_offset:465*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 465*FLEN/8, x3, x2, x7) + +inst_188: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x292 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x18a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x08d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a92; op2val:0x358a; +op3val:0x748d; valaddr_reg:x1; val_offset:468*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 468*FLEN/8, x3, x2, x7) + +inst_189: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x292 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x18a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x08d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a92; op2val:0x358a; +op3val:0x748d; valaddr_reg:x1; val_offset:471*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 471*FLEN/8, x3, x2, x7) + +inst_190: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x22b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2ee and fs3 == 0 and fe3 == 0x1e and fm3 == 0x158 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x762b; op2val:0x3eee; +op3val:0x7958; valaddr_reg:x1; val_offset:474*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 474*FLEN/8, x3, x2, x7) + +inst_191: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x22b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2ee and fs3 == 0 and fe3 == 0x1e and fm3 == 0x158 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x762b; op2val:0x3eee; +op3val:0x7958; valaddr_reg:x1; val_offset:477*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 477*FLEN/8, x3, x2, x7) + +inst_192: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x22b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2ee and fs3 == 0 and fe3 == 0x1e and fm3 == 0x158 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x762b; op2val:0x3eee; +op3val:0x7958; valaddr_reg:x1; val_offset:480*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 480*FLEN/8, x3, x2, x7) + +inst_193: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x22b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2ee and fs3 == 0 and fe3 == 0x1e and fm3 == 0x158 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x762b; op2val:0x3eee; +op3val:0x7958; valaddr_reg:x1; val_offset:483*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 483*FLEN/8, x3, x2, x7) + +inst_194: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x22b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2ee and fs3 == 0 and fe3 == 0x1e and fm3 == 0x158 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x762b; op2val:0x3eee; +op3val:0x7958; valaddr_reg:x1; val_offset:486*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 486*FLEN/8, x3, x2, x7) + +inst_195: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x1c6 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x11c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x362 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x65c6; op2val:0x4d1c; +op3val:0x7762; valaddr_reg:x1; val_offset:489*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 489*FLEN/8, x3, x2, x7) + +inst_196: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x1c6 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x11c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x362 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x65c6; op2val:0x4d1c; +op3val:0x7762; valaddr_reg:x1; val_offset:492*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 492*FLEN/8, x3, x2, x7) + +inst_197: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x1c6 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x11c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x362 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x65c6; op2val:0x4d1c; +op3val:0x7762; valaddr_reg:x1; val_offset:495*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 495*FLEN/8, x3, x2, x7) + +inst_198: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x1c6 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x11c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x362 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x65c6; op2val:0x4d1c; +op3val:0x7762; valaddr_reg:x1; val_offset:498*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 498*FLEN/8, x3, x2, x7) + +inst_199: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x1c6 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x11c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x362 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x65c6; op2val:0x4d1c; +op3val:0x7762; valaddr_reg:x1; val_offset:501*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 501*FLEN/8, x3, x2, x7) + +inst_200: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x160 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x193 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x37d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7160; op2val:0x3993; +op3val:0x6f7d; valaddr_reg:x1; val_offset:504*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 504*FLEN/8, x3, x2, x7) + +inst_201: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x160 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x193 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x37d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7160; op2val:0x3993; +op3val:0x6f7d; valaddr_reg:x1; val_offset:507*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 507*FLEN/8, x3, x2, x7) + +inst_202: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x160 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x193 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x37d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7160; op2val:0x3993; +op3val:0x6f7d; valaddr_reg:x1; val_offset:510*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 510*FLEN/8, x3, x2, x7) + +inst_203: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x160 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x193 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x37d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7160; op2val:0x3993; +op3val:0x6f7d; valaddr_reg:x1; val_offset:513*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 513*FLEN/8, x3, x2, x7) + +inst_204: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x160 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x193 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x37d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7160; op2val:0x3993; +op3val:0x6f7d; valaddr_reg:x1; val_offset:516*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 516*FLEN/8, x3, x2, x7) + +inst_205: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x38b and fs2 == 0 and fe2 == 0x12 and fm2 == 0x283 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x224 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6b8b; op2val:0x4a83; +op3val:0x7a24; valaddr_reg:x1; val_offset:519*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 519*FLEN/8, x3, x2, x7) + +inst_206: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x38b and fs2 == 0 and fe2 == 0x12 and fm2 == 0x283 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x224 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6b8b; op2val:0x4a83; +op3val:0x7a24; valaddr_reg:x1; val_offset:522*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 522*FLEN/8, x3, x2, x7) + +inst_207: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x38b and fs2 == 0 and fe2 == 0x12 and fm2 == 0x283 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x224 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6b8b; op2val:0x4a83; +op3val:0x7a24; valaddr_reg:x1; val_offset:525*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 525*FLEN/8, x3, x2, x7) + +inst_208: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x38b and fs2 == 0 and fe2 == 0x12 and fm2 == 0x283 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x224 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6b8b; op2val:0x4a83; +op3val:0x7a24; valaddr_reg:x1; val_offset:528*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 528*FLEN/8, x3, x2, x7) + +inst_209: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x38b and fs2 == 0 and fe2 == 0x12 and fm2 == 0x283 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x224 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6b8b; op2val:0x4a83; +op3val:0x7a24; valaddr_reg:x1; val_offset:531*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 531*FLEN/8, x3, x2, x7) + +inst_210: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x023 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3a8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3eb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7023; op2val:0x3fa8; +op3val:0x73eb; valaddr_reg:x1; val_offset:534*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 534*FLEN/8, x3, x2, x7) + +inst_211: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x023 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3a8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3eb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7023; op2val:0x3fa8; +op3val:0x73eb; valaddr_reg:x1; val_offset:537*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 537*FLEN/8, x3, x2, x7) + +inst_212: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x023 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3a8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3eb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7023; op2val:0x3fa8; +op3val:0x73eb; valaddr_reg:x1; val_offset:540*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 540*FLEN/8, x3, x2, x7) + +inst_213: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x023 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3a8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3eb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7023; op2val:0x3fa8; +op3val:0x73eb; valaddr_reg:x1; val_offset:543*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 543*FLEN/8, x3, x2, x7) + +inst_214: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x023 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3a8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3eb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7023; op2val:0x3fa8; +op3val:0x73eb; valaddr_reg:x1; val_offset:546*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 546*FLEN/8, x3, x2, x7) + +inst_215: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x240 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x075 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7640; op2val:0x4075; +op3val:0x7af7; valaddr_reg:x1; val_offset:549*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 549*FLEN/8, x3, x2, x7) + +inst_216: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x240 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x075 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7640; op2val:0x4075; +op3val:0x7af7; valaddr_reg:x1; val_offset:552*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 552*FLEN/8, x3, x2, x7) + +inst_217: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x240 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x075 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7640; op2val:0x4075; +op3val:0x7af7; valaddr_reg:x1; val_offset:555*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 555*FLEN/8, x3, x2, x7) + +inst_218: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x240 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x075 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7640; op2val:0x4075; +op3val:0x7af7; valaddr_reg:x1; val_offset:558*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 558*FLEN/8, x3, x2, x7) + +inst_219: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x240 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x075 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7640; op2val:0x4075; +op3val:0x7af7; valaddr_reg:x1; val_offset:561*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 561*FLEN/8, x3, x2, x7) + +inst_220: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x127 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x192 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x32f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d27; op2val:0x4592; +op3val:0x772f; valaddr_reg:x1; val_offset:564*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 564*FLEN/8, x3, x2, x7) + +inst_221: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x127 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x192 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x32f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d27; op2val:0x4592; +op3val:0x772f; valaddr_reg:x1; val_offset:567*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 567*FLEN/8, x3, x2, x7) + +inst_222: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x127 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x192 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x32f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d27; op2val:0x4592; +op3val:0x772f; valaddr_reg:x1; val_offset:570*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 570*FLEN/8, x3, x2, x7) + +inst_223: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x127 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x192 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x32f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d27; op2val:0x4592; +op3val:0x772f; valaddr_reg:x1; val_offset:573*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 573*FLEN/8, x3, x2, x7) + +inst_224: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x127 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x192 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x32f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d27; op2val:0x4592; +op3val:0x772f; valaddr_reg:x1; val_offset:576*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 576*FLEN/8, x3, x2, x7) + +inst_225: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x064 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x26e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x310 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7864; op2val:0x3e6e; +op3val:0x7b10; valaddr_reg:x1; val_offset:579*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 579*FLEN/8, x3, x2, x7) + +inst_226: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x064 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x26e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x310 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7864; op2val:0x3e6e; +op3val:0x7b10; valaddr_reg:x1; val_offset:582*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 582*FLEN/8, x3, x2, x7) + +inst_227: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x064 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x26e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x310 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7864; op2val:0x3e6e; +op3val:0x7b10; valaddr_reg:x1; val_offset:585*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 585*FLEN/8, x3, x2, x7) + +inst_228: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x064 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x26e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x310 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7864; op2val:0x3e6e; +op3val:0x7b10; valaddr_reg:x1; val_offset:588*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 588*FLEN/8, x3, x2, x7) + +inst_229: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x064 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x26e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x310 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7864; op2val:0x3e6e; +op3val:0x7b10; valaddr_reg:x1; val_offset:591*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 591*FLEN/8, x3, x2, x7) + +inst_230: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x037 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2e8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8d; op2val:0x3c37; +op3val:0x7ae8; valaddr_reg:x1; val_offset:594*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 594*FLEN/8, x3, x2, x7) + +inst_231: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x037 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2e8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8d; op2val:0x3c37; +op3val:0x7ae8; valaddr_reg:x1; val_offset:597*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 597*FLEN/8, x3, x2, x7) + +inst_232: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x037 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2e8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8d; op2val:0x3c37; +op3val:0x7ae8; valaddr_reg:x1; val_offset:600*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 600*FLEN/8, x3, x2, x7) + +inst_233: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x037 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2e8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8d; op2val:0x3c37; +op3val:0x7ae8; valaddr_reg:x1; val_offset:603*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 603*FLEN/8, x3, x2, x7) + +inst_234: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x037 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2e8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8d; op2val:0x3c37; +op3val:0x7ae8; valaddr_reg:x1; val_offset:606*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 606*FLEN/8, x3, x2, x7) + +inst_235: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x073 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1f7 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2a4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7473; op2val:0x3df7; +op3val:0x76a4; valaddr_reg:x1; val_offset:609*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 609*FLEN/8, x3, x2, x7) + +inst_236: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x073 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1f7 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2a4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7473; op2val:0x3df7; +op3val:0x76a4; valaddr_reg:x1; val_offset:612*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 612*FLEN/8, x3, x2, x7) + +inst_237: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x073 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1f7 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2a4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7473; op2val:0x3df7; +op3val:0x76a4; valaddr_reg:x1; val_offset:615*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 615*FLEN/8, x3, x2, x7) + +inst_238: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x073 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1f7 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2a4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7473; op2val:0x3df7; +op3val:0x76a4; valaddr_reg:x1; val_offset:618*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 618*FLEN/8, x3, x2, x7) + +inst_239: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x073 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1f7 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2a4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7473; op2val:0x3df7; +op3val:0x76a4; valaddr_reg:x1; val_offset:621*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 621*FLEN/8, x3, x2, x7) + +inst_240: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1bc and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0ed and fs3 == 0 and fe3 == 0x1e and fm3 == 0x311 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75bc; op2val:0x40ed; +op3val:0x7b11; valaddr_reg:x1; val_offset:624*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 624*FLEN/8, x3, x2, x7) + +inst_241: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1bc and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0ed and fs3 == 0 and fe3 == 0x1e and fm3 == 0x311 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75bc; op2val:0x40ed; +op3val:0x7b11; valaddr_reg:x1; val_offset:627*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 627*FLEN/8, x3, x2, x7) + +inst_242: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1bc and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0ed and fs3 == 0 and fe3 == 0x1e and fm3 == 0x311 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75bc; op2val:0x40ed; +op3val:0x7b11; valaddr_reg:x1; val_offset:630*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 630*FLEN/8, x3, x2, x7) + +inst_243: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1bc and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0ed and fs3 == 0 and fe3 == 0x1e and fm3 == 0x311 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75bc; op2val:0x40ed; +op3val:0x7b11; valaddr_reg:x1; val_offset:633*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 633*FLEN/8, x3, x2, x7) + +inst_244: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1bc and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0ed and fs3 == 0 and fe3 == 0x1e and fm3 == 0x311 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75bc; op2val:0x40ed; +op3val:0x7b11; valaddr_reg:x1; val_offset:636*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 636*FLEN/8, x3, x2, x7) + +inst_245: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a8 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x10b and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ba8; op2val:0x310b; +op3val:0x70d3; valaddr_reg:x1; val_offset:639*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 639*FLEN/8, x3, x2, x7) + +inst_246: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a8 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x10b and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ba8; op2val:0x310b; +op3val:0x70d3; valaddr_reg:x1; val_offset:642*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 642*FLEN/8, x3, x2, x7) + +inst_247: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a8 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x10b and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ba8; op2val:0x310b; +op3val:0x70d3; valaddr_reg:x1; val_offset:645*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 645*FLEN/8, x3, x2, x7) + +inst_248: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a8 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x10b and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ba8; op2val:0x310b; +op3val:0x70d3; valaddr_reg:x1; val_offset:648*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 648*FLEN/8, x3, x2, x7) + +inst_249: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a8 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x10b and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ba8; op2val:0x310b; +op3val:0x70d3; valaddr_reg:x1; val_offset:651*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 651*FLEN/8, x3, x2, x7) + +inst_250: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1a2 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x143 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x36b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71a2; op2val:0x3d43; +op3val:0x736b; valaddr_reg:x1; val_offset:654*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 654*FLEN/8, x3, x2, x7) + +inst_251: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1a2 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x143 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x36b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71a2; op2val:0x3d43; +op3val:0x736b; valaddr_reg:x1; val_offset:657*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 657*FLEN/8, x3, x2, x7) + +inst_252: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1a2 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x143 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x36b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71a2; op2val:0x3d43; +op3val:0x736b; valaddr_reg:x1; val_offset:660*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 660*FLEN/8, x3, x2, x7) + +inst_253: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1a2 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x143 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x36b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71a2; op2val:0x3d43; +op3val:0x736b; valaddr_reg:x1; val_offset:663*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 663*FLEN/8, x3, x2, x7) + +inst_254: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1a2 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x143 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x36b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71a2; op2val:0x3d43; +op3val:0x736b; valaddr_reg:x1; val_offset:666*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 666*FLEN/8, x3, x2, x7) + +inst_255: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x376 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x028 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3c1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7376; op2val:0x4028; +op3val:0x77c1; valaddr_reg:x1; val_offset:669*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 669*FLEN/8, x3, x2, x7) + +inst_256: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x376 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x028 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3c1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7376; op2val:0x4028; +op3val:0x77c1; valaddr_reg:x1; val_offset:672*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 672*FLEN/8, x3, x2, x7) + +inst_257: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x376 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x028 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3c1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7376; op2val:0x4028; +op3val:0x77c1; valaddr_reg:x1; val_offset:675*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 675*FLEN/8, x3, x2, x7) + +inst_258: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x376 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x028 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3c1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7376; op2val:0x4028; +op3val:0x77c1; valaddr_reg:x1; val_offset:678*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 678*FLEN/8, x3, x2, x7) + +inst_259: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x376 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x028 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3c1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7376; op2val:0x4028; +op3val:0x77c1; valaddr_reg:x1; val_offset:681*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 681*FLEN/8, x3, x2, x7) + +inst_260: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b5 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x322 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x033 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78b5; op2val:0x3722; +op3val:0x7433; valaddr_reg:x1; val_offset:684*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 684*FLEN/8, x3, x2, x7) + +inst_261: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b5 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x322 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x033 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78b5; op2val:0x3722; +op3val:0x7433; valaddr_reg:x1; val_offset:687*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 687*FLEN/8, x3, x2, x7) + +inst_262: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b5 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x322 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x033 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78b5; op2val:0x3722; +op3val:0x7433; valaddr_reg:x1; val_offset:690*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 690*FLEN/8, x3, x2, x7) + +inst_263: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b5 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x322 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x033 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78b5; op2val:0x3722; +op3val:0x7433; valaddr_reg:x1; val_offset:693*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 693*FLEN/8, x3, x2, x7) + +inst_264: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b5 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x322 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x033 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78b5; op2val:0x3722; +op3val:0x7433; valaddr_reg:x1; val_offset:696*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 696*FLEN/8, x3, x2, x7) + +inst_265: +// fs1 == 0 and fe1 == 0x17 and fm1 == 0x034 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x25f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2b3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5c34; op2val:0x565f; +op3val:0x76b3; valaddr_reg:x1; val_offset:699*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 699*FLEN/8, x3, x2, x7) + +inst_266: +// fs1 == 0 and fe1 == 0x17 and fm1 == 0x034 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x25f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2b3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5c34; op2val:0x565f; +op3val:0x76b3; valaddr_reg:x1; val_offset:702*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 702*FLEN/8, x3, x2, x7) + +inst_267: +// fs1 == 0 and fe1 == 0x17 and fm1 == 0x034 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x25f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2b3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5c34; op2val:0x565f; +op3val:0x76b3; valaddr_reg:x1; val_offset:705*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 705*FLEN/8, x3, x2, x7) + +inst_268: +// fs1 == 0 and fe1 == 0x17 and fm1 == 0x034 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x25f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2b3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5c34; op2val:0x565f; +op3val:0x76b3; valaddr_reg:x1; val_offset:708*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 708*FLEN/8, x3, x2, x7) + +inst_269: +// fs1 == 0 and fe1 == 0x17 and fm1 == 0x034 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x25f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2b3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5c34; op2val:0x565f; +op3val:0x76b3; valaddr_reg:x1; val_offset:711*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 711*FLEN/8, x3, x2, x7) + +inst_270: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1e7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x222 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x087 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75e7; op2val:0x3e22; +op3val:0x7887; valaddr_reg:x1; val_offset:714*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 714*FLEN/8, x3, x2, x7) + +inst_271: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1e7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x222 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x087 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75e7; op2val:0x3e22; +op3val:0x7887; valaddr_reg:x1; val_offset:717*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 717*FLEN/8, x3, x2, x7) + +inst_272: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1e7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x222 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x087 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75e7; op2val:0x3e22; +op3val:0x7887; valaddr_reg:x1; val_offset:720*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 720*FLEN/8, x3, x2, x7) + +inst_273: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1e7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x222 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x087 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75e7; op2val:0x3e22; +op3val:0x7887; valaddr_reg:x1; val_offset:723*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 723*FLEN/8, x3, x2, x7) + +inst_274: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1e7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x222 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x087 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75e7; op2val:0x3e22; +op3val:0x7887; valaddr_reg:x1; val_offset:726*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 726*FLEN/8, x3, x2, x7) + +inst_275: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x39e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1cb and fs3 == 0 and fe3 == 0x1e and fm3 == 0x185 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b9e; op2val:0x39cb; +op3val:0x7985; valaddr_reg:x1; val_offset:729*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 729*FLEN/8, x3, x2, x7) + +inst_276: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x39e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1cb and fs3 == 0 and fe3 == 0x1e and fm3 == 0x185 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b9e; op2val:0x39cb; +op3val:0x7985; valaddr_reg:x1; val_offset:732*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 732*FLEN/8, x3, x2, x7) + +inst_277: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x39e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1cb and fs3 == 0 and fe3 == 0x1e and fm3 == 0x185 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b9e; op2val:0x39cb; +op3val:0x7985; valaddr_reg:x1; val_offset:735*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 735*FLEN/8, x3, x2, x7) + +inst_278: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x39e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1cb and fs3 == 0 and fe3 == 0x1e and fm3 == 0x185 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b9e; op2val:0x39cb; +op3val:0x7985; valaddr_reg:x1; val_offset:738*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 738*FLEN/8, x3, x2, x7) + +inst_279: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x39e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1cb and fs3 == 0 and fe3 == 0x1e and fm3 == 0x185 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b9e; op2val:0x39cb; +op3val:0x7985; valaddr_reg:x1; val_offset:741*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 741*FLEN/8, x3, x2, x7) + +inst_280: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x01f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ca and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x781f; op2val:0x3cca; +op3val:0x78f0; valaddr_reg:x1; val_offset:744*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 744*FLEN/8, x3, x2, x7) + +inst_281: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x01f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ca and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0f0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x781f; op2val:0x3cca; +op3val:0x78f0; valaddr_reg:x1; val_offset:747*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 747*FLEN/8, x3, x2, x7) + +inst_282: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x01f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ca and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0f0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x781f; op2val:0x3cca; +op3val:0x78f0; valaddr_reg:x1; val_offset:750*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 750*FLEN/8, x3, x2, x7) +RVTEST_SIGBASE(x2,signature_x2_2) + +inst_283: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x01f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ca and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0f0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x781f; op2val:0x3cca; +op3val:0x78f0; valaddr_reg:x1; val_offset:753*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 753*FLEN/8, x3, x2, x7) + +inst_284: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x01f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ca and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0f0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x781f; op2val:0x3cca; +op3val:0x78f0; valaddr_reg:x1; val_offset:756*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 756*FLEN/8, x3, x2, x7) + +inst_285: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x168 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x11c and fs3 == 0 and fe3 == 0x1a and fm3 == 0x2e8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7968; op2val:0x2d1c; +op3val:0x6ae8; valaddr_reg:x1; val_offset:759*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 759*FLEN/8, x3, x2, x7) + +inst_286: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x168 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x11c and fs3 == 0 and fe3 == 0x1a and fm3 == 0x2e8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7968; op2val:0x2d1c; +op3val:0x6ae8; valaddr_reg:x1; val_offset:762*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 762*FLEN/8, x3, x2, x7) + +inst_287: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x168 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x11c and fs3 == 0 and fe3 == 0x1a and fm3 == 0x2e8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7968; op2val:0x2d1c; +op3val:0x6ae8; valaddr_reg:x1; val_offset:765*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 765*FLEN/8, x3, x2, x7) + +inst_288: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x168 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x11c and fs3 == 0 and fe3 == 0x1a and fm3 == 0x2e8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7968; op2val:0x2d1c; +op3val:0x6ae8; valaddr_reg:x1; val_offset:768*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 768*FLEN/8, x3, x2, x7) + +inst_289: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x168 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x11c and fs3 == 0 and fe3 == 0x1a and fm3 == 0x2e8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7968; op2val:0x2d1c; +op3val:0x6ae8; valaddr_reg:x1; val_offset:771*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 771*FLEN/8, x3, x2, x7) + +inst_290: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x331 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ef and fs3 == 0 and fe3 == 0x1e and fm3 == 0x23c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b31; op2val:0x3aef; +op3val:0x7a3c; valaddr_reg:x1; val_offset:774*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 774*FLEN/8, x3, x2, x7) + +inst_291: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x331 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ef and fs3 == 0 and fe3 == 0x1e and fm3 == 0x23c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b31; op2val:0x3aef; +op3val:0x7a3c; valaddr_reg:x1; val_offset:777*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 777*FLEN/8, x3, x2, x7) + +inst_292: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x331 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ef and fs3 == 0 and fe3 == 0x1e and fm3 == 0x23c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b31; op2val:0x3aef; +op3val:0x7a3c; valaddr_reg:x1; val_offset:780*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 780*FLEN/8, x3, x2, x7) + +inst_293: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x331 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ef and fs3 == 0 and fe3 == 0x1e and fm3 == 0x23c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b31; op2val:0x3aef; +op3val:0x7a3c; valaddr_reg:x1; val_offset:783*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 783*FLEN/8, x3, x2, x7) + +inst_294: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x331 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ef and fs3 == 0 and fe3 == 0x1e and fm3 == 0x23c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b31; op2val:0x3aef; +op3val:0x7a3c; valaddr_reg:x1; val_offset:786*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 786*FLEN/8, x3, x2, x7) + +inst_295: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2fe and fs2 == 0 and fe2 == 0x0e and fm2 == 0x34c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x261 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7afe; op2val:0x3b4c; +op3val:0x7a61; valaddr_reg:x1; val_offset:789*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 789*FLEN/8, x3, x2, x7) + +inst_296: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2fe and fs2 == 0 and fe2 == 0x0e and fm2 == 0x34c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x261 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7afe; op2val:0x3b4c; +op3val:0x7a61; valaddr_reg:x1; val_offset:792*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 792*FLEN/8, x3, x2, x7) + +inst_297: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2fe and fs2 == 0 and fe2 == 0x0e and fm2 == 0x34c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x261 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7afe; op2val:0x3b4c; +op3val:0x7a61; valaddr_reg:x1; val_offset:795*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 795*FLEN/8, x3, x2, x7) + +inst_298: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2fe and fs2 == 0 and fe2 == 0x0e and fm2 == 0x34c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x261 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7afe; op2val:0x3b4c; +op3val:0x7a61; valaddr_reg:x1; val_offset:798*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 798*FLEN/8, x3, x2, x7) + +inst_299: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2fe and fs2 == 0 and fe2 == 0x0e and fm2 == 0x34c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x261 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7afe; op2val:0x3b4c; +op3val:0x7a61; valaddr_reg:x1; val_offset:801*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 801*FLEN/8, x3, x2, x7) + +inst_300: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x246 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x011 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x261 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7646; op2val:0x3c11; +op3val:0x7661; valaddr_reg:x1; val_offset:804*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 804*FLEN/8, x3, x2, x7) + +inst_301: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x246 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x011 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x261 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7646; op2val:0x3c11; +op3val:0x7661; valaddr_reg:x1; val_offset:807*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 807*FLEN/8, x3, x2, x7) + +inst_302: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x246 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x011 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x261 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7646; op2val:0x3c11; +op3val:0x7661; valaddr_reg:x1; val_offset:810*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 810*FLEN/8, x3, x2, x7) + +inst_303: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x246 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x011 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x261 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7646; op2val:0x3c11; +op3val:0x7661; valaddr_reg:x1; val_offset:813*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 813*FLEN/8, x3, x2, x7) + +inst_304: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x246 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x011 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x261 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7646; op2val:0x3c11; +op3val:0x7661; valaddr_reg:x1; val_offset:816*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 816*FLEN/8, x3, x2, x7) + +inst_305: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x29f and fs2 == 0 and fe2 == 0x11 and fm2 == 0x220 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x112 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e9f; op2val:0x4620; +op3val:0x7912; valaddr_reg:x1; val_offset:819*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 819*FLEN/8, x3, x2, x7) + +inst_306: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x29f and fs2 == 0 and fe2 == 0x11 and fm2 == 0x220 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x112 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e9f; op2val:0x4620; +op3val:0x7912; valaddr_reg:x1; val_offset:822*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 822*FLEN/8, x3, x2, x7) + +inst_307: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x29f and fs2 == 0 and fe2 == 0x11 and fm2 == 0x220 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x112 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e9f; op2val:0x4620; +op3val:0x7912; valaddr_reg:x1; val_offset:825*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 825*FLEN/8, x3, x2, x7) + +inst_308: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x29f and fs2 == 0 and fe2 == 0x11 and fm2 == 0x220 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x112 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e9f; op2val:0x4620; +op3val:0x7912; valaddr_reg:x1; val_offset:828*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 828*FLEN/8, x3, x2, x7) + +inst_309: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x29f and fs2 == 0 and fe2 == 0x11 and fm2 == 0x220 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x112 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e9f; op2val:0x4620; +op3val:0x7912; valaddr_reg:x1; val_offset:831*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 831*FLEN/8, x3, x2, x7) + +inst_310: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3f7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x053 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x04f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6bf7; op2val:0x3c53; +op3val:0x6c4f; valaddr_reg:x1; val_offset:834*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 834*FLEN/8, x3, x2, x7) + +inst_311: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3f7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x053 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x04f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6bf7; op2val:0x3c53; +op3val:0x6c4f; valaddr_reg:x1; val_offset:837*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 837*FLEN/8, x3, x2, x7) + +inst_312: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3f7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x053 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x04f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6bf7; op2val:0x3c53; +op3val:0x6c4f; valaddr_reg:x1; val_offset:840*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 840*FLEN/8, x3, x2, x7) + +inst_313: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3f7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x053 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x04f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6bf7; op2val:0x3c53; +op3val:0x6c4f; valaddr_reg:x1; val_offset:843*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 843*FLEN/8, x3, x2, x7) + +inst_314: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3f7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x053 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x04f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6bf7; op2val:0x3c53; +op3val:0x6c4f; valaddr_reg:x1; val_offset:846*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 846*FLEN/8, x3, x2, x7) + +inst_315: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ad and fs2 == 0 and fe2 == 0x0e and fm2 == 0x238 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x131 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72ad; op2val:0x3a38; +op3val:0x7131; valaddr_reg:x1; val_offset:849*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 849*FLEN/8, x3, x2, x7) + +inst_316: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ad and fs2 == 0 and fe2 == 0x0e and fm2 == 0x238 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x131 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72ad; op2val:0x3a38; +op3val:0x7131; valaddr_reg:x1; val_offset:852*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 852*FLEN/8, x3, x2, x7) + +inst_317: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ad and fs2 == 0 and fe2 == 0x0e and fm2 == 0x238 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x131 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72ad; op2val:0x3a38; +op3val:0x7131; valaddr_reg:x1; val_offset:855*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 855*FLEN/8, x3, x2, x7) + +inst_318: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ad and fs2 == 0 and fe2 == 0x0e and fm2 == 0x238 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x131 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72ad; op2val:0x3a38; +op3val:0x7131; valaddr_reg:x1; val_offset:858*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 858*FLEN/8, x3, x2, x7) + +inst_319: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ad and fs2 == 0 and fe2 == 0x0e and fm2 == 0x238 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x131 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72ad; op2val:0x3a38; +op3val:0x7131; valaddr_reg:x1; val_offset:861*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 861*FLEN/8, x3, x2, x7) + +inst_320: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x170 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0f2 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x2ba and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7570; op2val:0x30f2; +op3val:0x6aba; valaddr_reg:x1; val_offset:864*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 864*FLEN/8, x3, x2, x7) + +inst_321: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x170 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0f2 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x2ba and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7570; op2val:0x30f2; +op3val:0x6aba; valaddr_reg:x1; val_offset:867*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 867*FLEN/8, x3, x2, x7) + +inst_322: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x170 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0f2 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x2ba and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7570; op2val:0x30f2; +op3val:0x6aba; valaddr_reg:x1; val_offset:870*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 870*FLEN/8, x3, x2, x7) + +inst_323: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x170 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0f2 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x2ba and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7570; op2val:0x30f2; +op3val:0x6aba; valaddr_reg:x1; val_offset:873*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 873*FLEN/8, x3, x2, x7) + +inst_324: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x170 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0f2 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x2ba and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7570; op2val:0x30f2; +op3val:0x6aba; valaddr_reg:x1; val_offset:876*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 876*FLEN/8, x3, x2, x7) + +inst_325: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x011 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x0c1 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c11; op2val:0x60c1; +op3val:0x70d6; valaddr_reg:x1; val_offset:879*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 879*FLEN/8, x3, x2, x7) + +inst_326: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x011 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x0c1 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c11; op2val:0x60c1; +op3val:0x70d6; valaddr_reg:x1; val_offset:882*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 882*FLEN/8, x3, x2, x7) + +inst_327: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x011 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x0c1 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c11; op2val:0x60c1; +op3val:0x70d6; valaddr_reg:x1; val_offset:885*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 885*FLEN/8, x3, x2, x7) + +inst_328: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x011 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x0c1 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c11; op2val:0x60c1; +op3val:0x70d6; valaddr_reg:x1; val_offset:888*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 888*FLEN/8, x3, x2, x7) + +inst_329: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x011 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x0c1 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c11; op2val:0x60c1; +op3val:0x70d6; valaddr_reg:x1; val_offset:891*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 891*FLEN/8, x3, x2, x7) + +inst_330: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x27d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x32a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1d0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e7d; op2val:0x432a; +op3val:0x75d0; valaddr_reg:x1; val_offset:894*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 894*FLEN/8, x3, x2, x7) + +inst_331: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x27d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x32a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1d0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e7d; op2val:0x432a; +op3val:0x75d0; valaddr_reg:x1; val_offset:897*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 897*FLEN/8, x3, x2, x7) + +inst_332: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x27d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x32a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1d0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e7d; op2val:0x432a; +op3val:0x75d0; valaddr_reg:x1; val_offset:900*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 900*FLEN/8, x3, x2, x7) + +inst_333: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x27d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x32a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1d0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e7d; op2val:0x432a; +op3val:0x75d0; valaddr_reg:x1; val_offset:903*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 903*FLEN/8, x3, x2, x7) + +inst_334: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x27d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x32a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1d0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e7d; op2val:0x432a; +op3val:0x75d0; valaddr_reg:x1; val_offset:906*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 906*FLEN/8, x3, x2, x7) + +inst_335: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x287 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x048 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2fd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6687; op2val:0x5048; +op3val:0x7afd; valaddr_reg:x1; val_offset:909*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 909*FLEN/8, x3, x2, x7) + +inst_336: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x287 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x048 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2fd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6687; op2val:0x5048; +op3val:0x7afd; valaddr_reg:x1; val_offset:912*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 912*FLEN/8, x3, x2, x7) + +inst_337: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x287 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x048 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2fd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6687; op2val:0x5048; +op3val:0x7afd; valaddr_reg:x1; val_offset:915*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 915*FLEN/8, x3, x2, x7) + +inst_338: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x287 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x048 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2fd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6687; op2val:0x5048; +op3val:0x7afd; valaddr_reg:x1; val_offset:918*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 918*FLEN/8, x3, x2, x7) + +inst_339: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x287 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x048 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2fd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6687; op2val:0x5048; +op3val:0x7afd; valaddr_reg:x1; val_offset:921*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 921*FLEN/8, x3, x2, x7) + +inst_340: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e9 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3bd and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e9; op2val:0x33bd; +op3val:0x70c0; valaddr_reg:x1; val_offset:924*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 924*FLEN/8, x3, x2, x7) + +inst_341: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e9 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3bd and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0c0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e9; op2val:0x33bd; +op3val:0x70c0; valaddr_reg:x1; val_offset:927*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 927*FLEN/8, x3, x2, x7) + +inst_342: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e9 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3bd and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0c0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e9; op2val:0x33bd; +op3val:0x70c0; valaddr_reg:x1; val_offset:930*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 930*FLEN/8, x3, x2, x7) + +inst_343: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e9 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3bd and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0c0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e9; op2val:0x33bd; +op3val:0x70c0; valaddr_reg:x1; val_offset:933*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 933*FLEN/8, x3, x2, x7) + +inst_344: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e9 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3bd and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0c0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e9; op2val:0x33bd; +op3val:0x70c0; valaddr_reg:x1; val_offset:936*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 936*FLEN/8, x3, x2, x7) + +inst_345: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x008 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x182 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x18e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7408; op2val:0x3d82; +op3val:0x758e; valaddr_reg:x1; val_offset:939*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 939*FLEN/8, x3, x2, x7) + +inst_346: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x008 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x182 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x18e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7408; op2val:0x3d82; +op3val:0x758e; valaddr_reg:x1; val_offset:942*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 942*FLEN/8, x3, x2, x7) + +inst_347: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x008 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x182 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x18e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7408; op2val:0x3d82; +op3val:0x758e; valaddr_reg:x1; val_offset:945*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 945*FLEN/8, x3, x2, x7) + +inst_348: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x008 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x182 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x18e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7408; op2val:0x3d82; +op3val:0x758e; valaddr_reg:x1; val_offset:948*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 948*FLEN/8, x3, x2, x7) + +inst_349: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x008 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x182 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x18e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7408; op2val:0x3d82; +op3val:0x758e; valaddr_reg:x1; val_offset:951*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 951*FLEN/8, x3, x2, x7) + +inst_350: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1d2 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x165 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x3db and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75d2; op2val:0x3565; +op3val:0x6fdb; valaddr_reg:x1; val_offset:954*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 954*FLEN/8, x3, x2, x7) + +inst_351: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1d2 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x165 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x3db and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75d2; op2val:0x3565; +op3val:0x6fdb; valaddr_reg:x1; val_offset:957*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 957*FLEN/8, x3, x2, x7) + +inst_352: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1d2 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x165 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x3db and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75d2; op2val:0x3565; +op3val:0x6fdb; valaddr_reg:x1; val_offset:960*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 960*FLEN/8, x3, x2, x7) + +inst_353: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1d2 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x165 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x3db and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75d2; op2val:0x3565; +op3val:0x6fdb; valaddr_reg:x1; val_offset:963*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 963*FLEN/8, x3, x2, x7) + +inst_354: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1d2 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x165 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x3db and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75d2; op2val:0x3565; +op3val:0x6fdb; valaddr_reg:x1; val_offset:966*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 966*FLEN/8, x3, x2, x7) + +inst_355: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c9 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ad and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ac9; op2val:0x3cad; +op3val:0x7bf0; valaddr_reg:x1; val_offset:969*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 969*FLEN/8, x3, x2, x7) + +inst_356: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c9 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ad and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3f0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ac9; op2val:0x3cad; +op3val:0x7bf0; valaddr_reg:x1; val_offset:972*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 972*FLEN/8, x3, x2, x7) + +inst_357: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c9 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ad and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3f0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ac9; op2val:0x3cad; +op3val:0x7bf0; valaddr_reg:x1; val_offset:975*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 975*FLEN/8, x3, x2, x7) + +inst_358: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c9 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ad and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3f0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ac9; op2val:0x3cad; +op3val:0x7bf0; valaddr_reg:x1; val_offset:978*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 978*FLEN/8, x3, x2, x7) + +inst_359: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c9 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ad and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3f0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ac9; op2val:0x3cad; +op3val:0x7bf0; valaddr_reg:x1; val_offset:981*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 981*FLEN/8, x3, x2, x7) + +inst_360: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x373 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x027 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3bc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7773; op2val:0x3c27; +op3val:0x77bc; valaddr_reg:x1; val_offset:984*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 984*FLEN/8, x3, x2, x7) + +inst_361: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x373 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x027 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3bc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7773; op2val:0x3c27; +op3val:0x77bc; valaddr_reg:x1; val_offset:987*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 987*FLEN/8, x3, x2, x7) + +inst_362: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x373 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x027 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3bc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7773; op2val:0x3c27; +op3val:0x77bc; valaddr_reg:x1; val_offset:990*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 990*FLEN/8, x3, x2, x7) + +inst_363: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x373 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x027 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3bc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7773; op2val:0x3c27; +op3val:0x77bc; valaddr_reg:x1; val_offset:993*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 993*FLEN/8, x3, x2, x7) + +inst_364: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x373 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x027 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3bc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7773; op2val:0x3c27; +op3val:0x77bc; valaddr_reg:x1; val_offset:996*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 996*FLEN/8, x3, x2, x7) + +inst_365: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x17e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0c2 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x289 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d7e; op2val:0x3cc2; +op3val:0x6e89; valaddr_reg:x1; val_offset:999*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 999*FLEN/8, x3, x2, x7) + +inst_366: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x17e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0c2 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x289 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d7e; op2val:0x3cc2; +op3val:0x6e89; valaddr_reg:x1; val_offset:1002*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1002*FLEN/8, x3, x2, x7) + +inst_367: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x17e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0c2 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x289 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d7e; op2val:0x3cc2; +op3val:0x6e89; valaddr_reg:x1; val_offset:1005*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1005*FLEN/8, x3, x2, x7) + +inst_368: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x17e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0c2 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x289 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d7e; op2val:0x3cc2; +op3val:0x6e89; valaddr_reg:x1; val_offset:1008*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1008*FLEN/8, x3, x2, x7) + +inst_369: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x17e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0c2 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x289 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d7e; op2val:0x3cc2; +op3val:0x6e89; valaddr_reg:x1; val_offset:1011*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1011*FLEN/8, x3, x2, x7) + +inst_370: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x17a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x22e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x03b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x757a; op2val:0x3a2e; +op3val:0x743b; valaddr_reg:x1; val_offset:1014*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1014*FLEN/8, x3, x2, x7) + +inst_371: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x17a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x22e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x03b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x757a; op2val:0x3a2e; +op3val:0x743b; valaddr_reg:x1; val_offset:1017*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1017*FLEN/8, x3, x2, x7) + +inst_372: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x17a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x22e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x03b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x757a; op2val:0x3a2e; +op3val:0x743b; valaddr_reg:x1; val_offset:1020*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1020*FLEN/8, x3, x2, x7) + +inst_373: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x17a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x22e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x03b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x757a; op2val:0x3a2e; +op3val:0x743b; valaddr_reg:x1; val_offset:1023*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1023*FLEN/8, x3, x2, x7) + +inst_374: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x17a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x22e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x03b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x757a; op2val:0x3a2e; +op3val:0x743b; valaddr_reg:x1; val_offset:1026*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1026*FLEN/8, x3, x2, x7) + +inst_375: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a0 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x23b and fs3 == 0 and fe3 == 0x1c and fm3 == 0x129 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aa0; op2val:0x323b; +op3val:0x7129; valaddr_reg:x1; val_offset:1029*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1029*FLEN/8, x3, x2, x7) + +inst_376: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a0 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x23b and fs3 == 0 and fe3 == 0x1c and fm3 == 0x129 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aa0; op2val:0x323b; +op3val:0x7129; valaddr_reg:x1; val_offset:1032*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1032*FLEN/8, x3, x2, x7) + +inst_377: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a0 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x23b and fs3 == 0 and fe3 == 0x1c and fm3 == 0x129 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aa0; op2val:0x323b; +op3val:0x7129; valaddr_reg:x1; val_offset:1035*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1035*FLEN/8, x3, x2, x7) + +inst_378: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a0 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x23b and fs3 == 0 and fe3 == 0x1c and fm3 == 0x129 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aa0; op2val:0x323b; +op3val:0x7129; valaddr_reg:x1; val_offset:1038*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1038*FLEN/8, x3, x2, x7) + +inst_379: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a0 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x23b and fs3 == 0 and fe3 == 0x1c and fm3 == 0x129 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aa0; op2val:0x323b; +op3val:0x7129; valaddr_reg:x1; val_offset:1041*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1041*FLEN/8, x3, x2, x7) + +inst_380: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x1e9 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x124 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x39a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x65e9; op2val:0x5124; +op3val:0x7b9a; valaddr_reg:x1; val_offset:1044*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1044*FLEN/8, x3, x2, x7) + +inst_381: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x1e9 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x124 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x39a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x65e9; op2val:0x5124; +op3val:0x7b9a; valaddr_reg:x1; val_offset:1047*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1047*FLEN/8, x3, x2, x7) + +inst_382: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x1e9 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x124 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x39a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x65e9; op2val:0x5124; +op3val:0x7b9a; valaddr_reg:x1; val_offset:1050*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1050*FLEN/8, x3, x2, x7) + +inst_383: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x1e9 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x124 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x39a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x65e9; op2val:0x5124; +op3val:0x7b9a; valaddr_reg:x1; val_offset:1053*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1053*FLEN/8, x3, x2, x7) + +inst_384: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x1e9 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x124 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x39a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x65e9; op2val:0x5124; +op3val:0x7b9a; valaddr_reg:x1; val_offset:1056*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1056*FLEN/8, x3, x2, x7) + +inst_385: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x039 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x070 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0b0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7839; op2val:0x3470; +op3val:0x70b0; valaddr_reg:x1; val_offset:1059*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1059*FLEN/8, x3, x2, x7) + +inst_386: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x039 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x070 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0b0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7839; op2val:0x3470; +op3val:0x70b0; valaddr_reg:x1; val_offset:1062*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1062*FLEN/8, x3, x2, x7) + +inst_387: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x039 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x070 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0b0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7839; op2val:0x3470; +op3val:0x70b0; valaddr_reg:x1; val_offset:1065*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1065*FLEN/8, x3, x2, x7) + +inst_388: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x039 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x070 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0b0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7839; op2val:0x3470; +op3val:0x70b0; valaddr_reg:x1; val_offset:1068*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1068*FLEN/8, x3, x2, x7) + +inst_389: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x039 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x070 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0b0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7839; op2val:0x3470; +op3val:0x70b0; valaddr_reg:x1; val_offset:1071*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1071*FLEN/8, x3, x2, x7) + +inst_390: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x057 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x260 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x2ec and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7857; op2val:0x2a60; +op3val:0x66ec; valaddr_reg:x1; val_offset:1074*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1074*FLEN/8, x3, x2, x7) + +inst_391: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x057 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x260 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x2ec and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7857; op2val:0x2a60; +op3val:0x66ec; valaddr_reg:x1; val_offset:1077*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1077*FLEN/8, x3, x2, x7) + +inst_392: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x057 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x260 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x2ec and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7857; op2val:0x2a60; +op3val:0x66ec; valaddr_reg:x1; val_offset:1080*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1080*FLEN/8, x3, x2, x7) + +inst_393: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x057 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x260 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x2ec and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7857; op2val:0x2a60; +op3val:0x66ec; valaddr_reg:x1; val_offset:1083*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1083*FLEN/8, x3, x2, x7) + +inst_394: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x057 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x260 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x2ec and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7857; op2val:0x2a60; +op3val:0x66ec; valaddr_reg:x1; val_offset:1086*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1086*FLEN/8, x3, x2, x7) + +inst_395: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x039 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x369 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3d2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7839; op2val:0x3f69; +op3val:0x7bd2; valaddr_reg:x1; val_offset:1089*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1089*FLEN/8, x3, x2, x7) + +inst_396: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x039 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x369 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3d2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7839; op2val:0x3f69; +op3val:0x7bd2; valaddr_reg:x1; val_offset:1092*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1092*FLEN/8, x3, x2, x7) + +inst_397: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x039 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x369 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3d2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7839; op2val:0x3f69; +op3val:0x7bd2; valaddr_reg:x1; val_offset:1095*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1095*FLEN/8, x3, x2, x7) + +inst_398: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x039 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x369 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3d2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7839; op2val:0x3f69; +op3val:0x7bd2; valaddr_reg:x1; val_offset:1098*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1098*FLEN/8, x3, x2, x7) + +inst_399: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x039 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x369 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3d2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7839; op2val:0x3f69; +op3val:0x7bd2; valaddr_reg:x1; val_offset:1101*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1101*FLEN/8, x3, x2, x7) + +inst_400: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x273 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x191 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ae7; op2val:0x3a73; +op3val:0x7991; valaddr_reg:x1; val_offset:1104*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1104*FLEN/8, x3, x2, x7) + +inst_401: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x273 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x191 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ae7; op2val:0x3a73; +op3val:0x7991; valaddr_reg:x1; val_offset:1107*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1107*FLEN/8, x3, x2, x7) + +inst_402: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x273 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x191 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ae7; op2val:0x3a73; +op3val:0x7991; valaddr_reg:x1; val_offset:1110*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1110*FLEN/8, x3, x2, x7) + +inst_403: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x273 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x191 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ae7; op2val:0x3a73; +op3val:0x7991; valaddr_reg:x1; val_offset:1113*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1113*FLEN/8, x3, x2, x7) + +inst_404: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x273 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x191 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ae7; op2val:0x3a73; +op3val:0x7991; valaddr_reg:x1; val_offset:1116*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1116*FLEN/8, x3, x2, x7) + +inst_405: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x02d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x19e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1dd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x742d; op2val:0x3d9e; +op3val:0x75dd; valaddr_reg:x1; val_offset:1119*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1119*FLEN/8, x3, x2, x7) + +inst_406: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x02d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x19e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1dd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x742d; op2val:0x3d9e; +op3val:0x75dd; valaddr_reg:x1; val_offset:1122*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1122*FLEN/8, x3, x2, x7) + +inst_407: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x02d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x19e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1dd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x742d; op2val:0x3d9e; +op3val:0x75dd; valaddr_reg:x1; val_offset:1125*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1125*FLEN/8, x3, x2, x7) + +inst_408: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x02d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x19e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1dd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x742d; op2val:0x3d9e; +op3val:0x75dd; valaddr_reg:x1; val_offset:1128*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1128*FLEN/8, x3, x2, x7) + +inst_409: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x02d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x19e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1dd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x742d; op2val:0x3d9e; +op3val:0x75dd; valaddr_reg:x1; val_offset:1131*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1131*FLEN/8, x3, x2, x7) + +inst_410: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x157 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x09e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x22c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7157; op2val:0x449e; +op3val:0x7a2c; valaddr_reg:x1; val_offset:1134*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1134*FLEN/8, x3, x2, x7) +RVTEST_SIGBASE(x2,signature_x2_3) + +inst_411: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x157 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x09e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x22c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7157; op2val:0x449e; +op3val:0x7a2c; valaddr_reg:x1; val_offset:1137*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1137*FLEN/8, x3, x2, x7) + +inst_412: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x157 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x09e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x22c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7157; op2val:0x449e; +op3val:0x7a2c; valaddr_reg:x1; val_offset:1140*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1140*FLEN/8, x3, x2, x7) + +inst_413: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x157 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x09e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x22c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7157; op2val:0x449e; +op3val:0x7a2c; valaddr_reg:x1; val_offset:1143*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1143*FLEN/8, x3, x2, x7) + +inst_414: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x157 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x09e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x22c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7157; op2val:0x449e; +op3val:0x7a2c; valaddr_reg:x1; val_offset:1146*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1146*FLEN/8, x3, x2, x7) + +inst_415: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x042 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1d9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x23a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7842; op2val:0x3dd9; +op3val:0x7a3a; valaddr_reg:x1; val_offset:1149*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1149*FLEN/8, x3, x2, x7) + +inst_416: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x042 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1d9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x23a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7842; op2val:0x3dd9; +op3val:0x7a3a; valaddr_reg:x1; val_offset:1152*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1152*FLEN/8, x3, x2, x7) + +inst_417: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x042 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1d9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x23a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7842; op2val:0x3dd9; +op3val:0x7a3a; valaddr_reg:x1; val_offset:1155*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1155*FLEN/8, x3, x2, x7) + +inst_418: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x042 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1d9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x23a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7842; op2val:0x3dd9; +op3val:0x7a3a; valaddr_reg:x1; val_offset:1158*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1158*FLEN/8, x3, x2, x7) + +inst_419: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x042 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1d9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x23a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7842; op2val:0x3dd9; +op3val:0x7a3a; valaddr_reg:x1; val_offset:1161*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1161*FLEN/8, x3, x2, x7) + +inst_420: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x145 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x169 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x322 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7545; op2val:0x3969; +op3val:0x7322; valaddr_reg:x1; val_offset:1164*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1164*FLEN/8, x3, x2, x7) + +inst_421: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x145 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x169 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x322 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7545; op2val:0x3969; +op3val:0x7322; valaddr_reg:x1; val_offset:1167*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1167*FLEN/8, x3, x2, x7) + +inst_422: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x145 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x169 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x322 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7545; op2val:0x3969; +op3val:0x7322; valaddr_reg:x1; val_offset:1170*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1170*FLEN/8, x3, x2, x7) + +inst_423: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x145 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x169 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x322 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7545; op2val:0x3969; +op3val:0x7322; valaddr_reg:x1; val_offset:1173*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1173*FLEN/8, x3, x2, x7) + +inst_424: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x145 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x169 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x322 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7545; op2val:0x3969; +op3val:0x7322; valaddr_reg:x1; val_offset:1176*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1176*FLEN/8, x3, x2, x7) + +inst_425: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x27d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0da and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a7d; op2val:0x3cda; +op3val:0x7be0; valaddr_reg:x1; val_offset:1179*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1179*FLEN/8, x3, x2, x7) + +inst_426: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x27d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0da and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3e0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a7d; op2val:0x3cda; +op3val:0x7be0; valaddr_reg:x1; val_offset:1182*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1182*FLEN/8, x3, x2, x7) + +inst_427: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x27d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0da and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3e0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a7d; op2val:0x3cda; +op3val:0x7be0; valaddr_reg:x1; val_offset:1185*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1185*FLEN/8, x3, x2, x7) + +inst_428: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x27d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0da and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3e0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a7d; op2val:0x3cda; +op3val:0x7be0; valaddr_reg:x1; val_offset:1188*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1188*FLEN/8, x3, x2, x7) + +inst_429: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x27d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0da and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3e0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a7d; op2val:0x3cda; +op3val:0x7be0; valaddr_reg:x1; val_offset:1191*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1191*FLEN/8, x3, x2, x7) + +inst_430: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d1 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x390 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x272 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ad1; op2val:0x3b90; +op3val:0x7a72; valaddr_reg:x1; val_offset:1194*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1194*FLEN/8, x3, x2, x7) + +inst_431: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d1 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x390 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x272 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ad1; op2val:0x3b90; +op3val:0x7a72; valaddr_reg:x1; val_offset:1197*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1197*FLEN/8, x3, x2, x7) + +inst_432: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d1 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x390 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x272 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ad1; op2val:0x3b90; +op3val:0x7a72; valaddr_reg:x1; val_offset:1200*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1200*FLEN/8, x3, x2, x7) + +inst_433: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d1 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x390 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x272 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ad1; op2val:0x3b90; +op3val:0x7a72; valaddr_reg:x1; val_offset:1203*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1203*FLEN/8, x3, x2, x7) + +inst_434: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d1 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x390 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x272 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ad1; op2val:0x3b90; +op3val:0x7a72; valaddr_reg:x1; val_offset:1206*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1206*FLEN/8, x3, x2, x7) + +inst_435: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x33b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ea and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8b; op2val:0x3b3b; +op3val:0x79ea; valaddr_reg:x1; val_offset:1209*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1209*FLEN/8, x3, x2, x7) + +inst_436: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x33b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ea and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8b; op2val:0x3b3b; +op3val:0x79ea; valaddr_reg:x1; val_offset:1212*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1212*FLEN/8, x3, x2, x7) + +inst_437: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x33b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ea and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8b; op2val:0x3b3b; +op3val:0x79ea; valaddr_reg:x1; val_offset:1215*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1215*FLEN/8, x3, x2, x7) + +inst_438: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x33b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ea and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8b; op2val:0x3b3b; +op3val:0x79ea; valaddr_reg:x1; val_offset:1218*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1218*FLEN/8, x3, x2, x7) + +inst_439: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x33b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ea and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8b; op2val:0x3b3b; +op3val:0x79ea; valaddr_reg:x1; val_offset:1221*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1221*FLEN/8, x3, x2, x7) + +inst_440: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x340 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x090 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x023 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7340; op2val:0x4090; +op3val:0x7823; valaddr_reg:x1; val_offset:1224*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1224*FLEN/8, x3, x2, x7) + +inst_441: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x340 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x090 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x023 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7340; op2val:0x4090; +op3val:0x7823; valaddr_reg:x1; val_offset:1227*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1227*FLEN/8, x3, x2, x7) + +inst_442: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x340 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x090 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x023 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7340; op2val:0x4090; +op3val:0x7823; valaddr_reg:x1; val_offset:1230*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1230*FLEN/8, x3, x2, x7) + +inst_443: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x340 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x090 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x023 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7340; op2val:0x4090; +op3val:0x7823; valaddr_reg:x1; val_offset:1233*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1233*FLEN/8, x3, x2, x7) + +inst_444: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x340 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x090 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x023 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7340; op2val:0x4090; +op3val:0x7823; valaddr_reg:x1; val_offset:1236*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1236*FLEN/8, x3, x2, x7) + +inst_445: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1af and fs2 == 0 and fe2 == 0x0b and fm2 == 0x138 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x36b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75af; op2val:0x2d38; +op3val:0x676b; valaddr_reg:x1; val_offset:1239*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1239*FLEN/8, x3, x2, x7) + +inst_446: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1af and fs2 == 0 and fe2 == 0x0b and fm2 == 0x138 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x36b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75af; op2val:0x2d38; +op3val:0x676b; valaddr_reg:x1; val_offset:1242*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1242*FLEN/8, x3, x2, x7) + +inst_447: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1af and fs2 == 0 and fe2 == 0x0b and fm2 == 0x138 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x36b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75af; op2val:0x2d38; +op3val:0x676b; valaddr_reg:x1; val_offset:1245*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1245*FLEN/8, x3, x2, x7) + +inst_448: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1af and fs2 == 0 and fe2 == 0x0b and fm2 == 0x138 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x36b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75af; op2val:0x2d38; +op3val:0x676b; valaddr_reg:x1; val_offset:1248*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1248*FLEN/8, x3, x2, x7) + +inst_449: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1af and fs2 == 0 and fe2 == 0x0b and fm2 == 0x138 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x36b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75af; op2val:0x2d38; +op3val:0x676b; valaddr_reg:x1; val_offset:1251*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1251*FLEN/8, x3, x2, x7) + +inst_450: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x326 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x0ff and fs3 == 0 and fe3 == 0x1d and fm3 == 0x077 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6726; op2val:0x48ff; +op3val:0x7477; valaddr_reg:x1; val_offset:1254*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1254*FLEN/8, x3, x2, x7) + +inst_451: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x326 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x0ff and fs3 == 0 and fe3 == 0x1d and fm3 == 0x077 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6726; op2val:0x48ff; +op3val:0x7477; valaddr_reg:x1; val_offset:1257*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1257*FLEN/8, x3, x2, x7) + +inst_452: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x326 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x0ff and fs3 == 0 and fe3 == 0x1d and fm3 == 0x077 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6726; op2val:0x48ff; +op3val:0x7477; valaddr_reg:x1; val_offset:1260*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1260*FLEN/8, x3, x2, x7) + +inst_453: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x326 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x0ff and fs3 == 0 and fe3 == 0x1d and fm3 == 0x077 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6726; op2val:0x48ff; +op3val:0x7477; valaddr_reg:x1; val_offset:1263*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1263*FLEN/8, x3, x2, x7) + +inst_454: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x326 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x0ff and fs3 == 0 and fe3 == 0x1d and fm3 == 0x077 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6726; op2val:0x48ff; +op3val:0x7477; valaddr_reg:x1; val_offset:1266*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1266*FLEN/8, x3, x2, x7) + +inst_455: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x158 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x189 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7425; op2val:0x4158; +op3val:0x7989; valaddr_reg:x1; val_offset:1269*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1269*FLEN/8, x3, x2, x7) + +inst_456: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x158 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x189 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7425; op2val:0x4158; +op3val:0x7989; valaddr_reg:x1; val_offset:1272*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1272*FLEN/8, x3, x2, x7) + +inst_457: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x158 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x189 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7425; op2val:0x4158; +op3val:0x7989; valaddr_reg:x1; val_offset:1275*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1275*FLEN/8, x3, x2, x7) + +inst_458: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x158 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x189 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7425; op2val:0x4158; +op3val:0x7989; valaddr_reg:x1; val_offset:1278*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1278*FLEN/8, x3, x2, x7) + +inst_459: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x158 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x189 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7425; op2val:0x4158; +op3val:0x7989; valaddr_reg:x1; val_offset:1281*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1281*FLEN/8, x3, x2, x7) + +inst_460: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x37b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x326 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ba5; op2val:0x377b; +op3val:0x7726; valaddr_reg:x1; val_offset:1284*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1284*FLEN/8, x3, x2, x7) + +inst_461: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x37b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x326 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ba5; op2val:0x377b; +op3val:0x7726; valaddr_reg:x1; val_offset:1287*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1287*FLEN/8, x3, x2, x7) + +inst_462: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x37b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x326 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ba5; op2val:0x377b; +op3val:0x7726; valaddr_reg:x1; val_offset:1290*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1290*FLEN/8, x3, x2, x7) + +inst_463: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x37b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x326 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ba5; op2val:0x377b; +op3val:0x7726; valaddr_reg:x1; val_offset:1293*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1293*FLEN/8, x3, x2, x7) + +inst_464: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x37b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x326 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ba5; op2val:0x377b; +op3val:0x7726; valaddr_reg:x1; val_offset:1296*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1296*FLEN/8, x3, x2, x7) + +inst_465: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x037 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3e6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b7e; op2val:0x3c37; +op3val:0x7be6; valaddr_reg:x1; val_offset:1299*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1299*FLEN/8, x3, x2, x7) + +inst_466: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x037 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3e6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b7e; op2val:0x3c37; +op3val:0x7be6; valaddr_reg:x1; val_offset:1302*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1302*FLEN/8, x3, x2, x7) + +inst_467: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x037 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3e6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b7e; op2val:0x3c37; +op3val:0x7be6; valaddr_reg:x1; val_offset:1305*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1305*FLEN/8, x3, x2, x7) + +inst_468: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x037 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3e6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b7e; op2val:0x3c37; +op3val:0x7be6; valaddr_reg:x1; val_offset:1308*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1308*FLEN/8, x3, x2, x7) + +inst_469: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x037 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3e6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b7e; op2val:0x3c37; +op3val:0x7be6; valaddr_reg:x1; val_offset:1311*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1311*FLEN/8, x3, x2, x7) + +inst_470: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a2 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x21b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1d4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ba2; op2val:0x361b; +op3val:0x75d4; valaddr_reg:x1; val_offset:1314*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1314*FLEN/8, x3, x2, x7) + +inst_471: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a2 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x21b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1d4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ba2; op2val:0x361b; +op3val:0x75d4; valaddr_reg:x1; val_offset:1317*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1317*FLEN/8, x3, x2, x7) + +inst_472: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a2 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x21b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1d4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ba2; op2val:0x361b; +op3val:0x75d4; valaddr_reg:x1; val_offset:1320*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1320*FLEN/8, x3, x2, x7) + +inst_473: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a2 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x21b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1d4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ba2; op2val:0x361b; +op3val:0x75d4; valaddr_reg:x1; val_offset:1323*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1323*FLEN/8, x3, x2, x7) + +inst_474: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a2 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x21b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1d4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ba2; op2val:0x361b; +op3val:0x75d4; valaddr_reg:x1; val_offset:1326*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1326*FLEN/8, x3, x2, x7) + +inst_475: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x30d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x01d and fs3 == 0 and fe3 == 0x1c and fm3 == 0x341 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x730d; op2val:0x3c1d; +op3val:0x7341; valaddr_reg:x1; val_offset:1329*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1329*FLEN/8, x3, x2, x7) + +inst_476: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x30d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x01d and fs3 == 0 and fe3 == 0x1c and fm3 == 0x341 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x730d; op2val:0x3c1d; +op3val:0x7341; valaddr_reg:x1; val_offset:1332*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1332*FLEN/8, x3, x2, x7) + +inst_477: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x30d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x01d and fs3 == 0 and fe3 == 0x1c and fm3 == 0x341 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x730d; op2val:0x3c1d; +op3val:0x7341; valaddr_reg:x1; val_offset:1335*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1335*FLEN/8, x3, x2, x7) + +inst_478: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x30d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x01d and fs3 == 0 and fe3 == 0x1c and fm3 == 0x341 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x730d; op2val:0x3c1d; +op3val:0x7341; valaddr_reg:x1; val_offset:1338*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1338*FLEN/8, x3, x2, x7) + +inst_479: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x30d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x01d and fs3 == 0 and fe3 == 0x1c and fm3 == 0x341 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x730d; op2val:0x3c1d; +op3val:0x7341; valaddr_reg:x1; val_offset:1341*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1341*FLEN/8, x3, x2, x7) + +inst_480: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x24a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x027 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x289 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x724a; op2val:0x3c27; +op3val:0x7289; valaddr_reg:x1; val_offset:1344*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1344*FLEN/8, x3, x2, x7) + +inst_481: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x24a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x027 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x289 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x724a; op2val:0x3c27; +op3val:0x7289; valaddr_reg:x1; val_offset:1347*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1347*FLEN/8, x3, x2, x7) + +inst_482: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x24a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x027 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x289 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x724a; op2val:0x3c27; +op3val:0x7289; valaddr_reg:x1; val_offset:1350*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1350*FLEN/8, x3, x2, x7) + +inst_483: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x24a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x027 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x289 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x724a; op2val:0x3c27; +op3val:0x7289; valaddr_reg:x1; val_offset:1353*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1353*FLEN/8, x3, x2, x7) + +inst_484: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x24a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x027 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x289 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x724a; op2val:0x3c27; +op3val:0x7289; valaddr_reg:x1; val_offset:1356*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1356*FLEN/8, x3, x2, x7) + +inst_485: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fd and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1c5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x332 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fd; op2val:0x3dc5; +op3val:0x7b32; valaddr_reg:x1; val_offset:1359*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1359*FLEN/8, x3, x2, x7) + +inst_486: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fd and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1c5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x332 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fd; op2val:0x3dc5; +op3val:0x7b32; valaddr_reg:x1; val_offset:1362*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1362*FLEN/8, x3, x2, x7) + +inst_487: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fd and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1c5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x332 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fd; op2val:0x3dc5; +op3val:0x7b32; valaddr_reg:x1; val_offset:1365*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1365*FLEN/8, x3, x2, x7) + +inst_488: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fd and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1c5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x332 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fd; op2val:0x3dc5; +op3val:0x7b32; valaddr_reg:x1; val_offset:1368*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1368*FLEN/8, x3, x2, x7) + +inst_489: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fd and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1c5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x332 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fd; op2val:0x3dc5; +op3val:0x7b32; valaddr_reg:x1; val_offset:1371*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1371*FLEN/8, x3, x2, x7) + +inst_490: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x090 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ab8; op2val:0x3890; +op3val:0x77aa; valaddr_reg:x1; val_offset:1374*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1374*FLEN/8, x3, x2, x7) + +inst_491: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x090 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3aa and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ab8; op2val:0x3890; +op3val:0x77aa; valaddr_reg:x1; val_offset:1377*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1377*FLEN/8, x3, x2, x7) + +inst_492: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x090 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3aa and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ab8; op2val:0x3890; +op3val:0x77aa; valaddr_reg:x1; val_offset:1380*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1380*FLEN/8, x3, x2, x7) + +inst_493: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x090 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3aa and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ab8; op2val:0x3890; +op3val:0x77aa; valaddr_reg:x1; val_offset:1383*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1383*FLEN/8, x3, x2, x7) + +inst_494: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x090 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3aa and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ab8; op2val:0x3890; +op3val:0x77aa; valaddr_reg:x1; val_offset:1386*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1386*FLEN/8, x3, x2, x7) + +inst_495: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x138 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0e5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x264 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7938; op2val:0x3ce5; +op3val:0x7a64; valaddr_reg:x1; val_offset:1389*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1389*FLEN/8, x3, x2, x7) + +inst_496: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x138 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0e5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x264 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7938; op2val:0x3ce5; +op3val:0x7a64; valaddr_reg:x1; val_offset:1392*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1392*FLEN/8, x3, x2, x7) + +inst_497: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x138 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0e5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x264 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7938; op2val:0x3ce5; +op3val:0x7a64; valaddr_reg:x1; val_offset:1395*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1395*FLEN/8, x3, x2, x7) + +inst_498: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x138 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0e5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x264 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7938; op2val:0x3ce5; +op3val:0x7a64; valaddr_reg:x1; val_offset:1398*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1398*FLEN/8, x3, x2, x7) + +inst_499: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x138 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0e5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x264 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7938; op2val:0x3ce5; +op3val:0x7a64; valaddr_reg:x1; val_offset:1401*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1401*FLEN/8, x3, x2, x7) + +inst_500: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x16c and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3ca and fs3 == 0 and fe3 == 0x1e and fm3 == 0x148 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d6c; op2val:0x47ca; +op3val:0x7948; valaddr_reg:x1; val_offset:1404*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1404*FLEN/8, x3, x2, x7) + +inst_501: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x16c and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3ca and fs3 == 0 and fe3 == 0x1e and fm3 == 0x148 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d6c; op2val:0x47ca; +op3val:0x7948; valaddr_reg:x1; val_offset:1407*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1407*FLEN/8, x3, x2, x7) + +inst_502: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x16c and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3ca and fs3 == 0 and fe3 == 0x1e and fm3 == 0x148 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d6c; op2val:0x47ca; +op3val:0x7948; valaddr_reg:x1; val_offset:1410*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1410*FLEN/8, x3, x2, x7) + +inst_503: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x16c and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3ca and fs3 == 0 and fe3 == 0x1e and fm3 == 0x148 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d6c; op2val:0x47ca; +op3val:0x7948; valaddr_reg:x1; val_offset:1413*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1413*FLEN/8, x3, x2, x7) + +inst_504: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x16c and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3ca and fs3 == 0 and fe3 == 0x1e and fm3 == 0x148 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d6c; op2val:0x47ca; +op3val:0x7948; valaddr_reg:x1; val_offset:1416*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1416*FLEN/8, x3, x2, x7) + +inst_505: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x346 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x241 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b46; op2val:0x3ae1; +op3val:0x7a41; valaddr_reg:x1; val_offset:1419*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1419*FLEN/8, x3, x2, x7) + +inst_506: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x346 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x241 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b46; op2val:0x3ae1; +op3val:0x7a41; valaddr_reg:x1; val_offset:1422*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1422*FLEN/8, x3, x2, x7) + +inst_507: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x346 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x241 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b46; op2val:0x3ae1; +op3val:0x7a41; valaddr_reg:x1; val_offset:1425*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1425*FLEN/8, x3, x2, x7) + +inst_508: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x346 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x241 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b46; op2val:0x3ae1; +op3val:0x7a41; valaddr_reg:x1; val_offset:1428*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1428*FLEN/8, x3, x2, x7) + +inst_509: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x346 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x241 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b46; op2val:0x3ae1; +op3val:0x7a41; valaddr_reg:x1; val_offset:1431*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1431*FLEN/8, x3, x2, x7) + +inst_510: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x0e and fm2 == 0x119 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3a5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79ff; op2val:0x3919; +op3val:0x77a5; valaddr_reg:x1; val_offset:1434*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1434*FLEN/8, x3, x2, x7) + +inst_511: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x0e and fm2 == 0x119 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3a5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79ff; op2val:0x3919; +op3val:0x77a5; valaddr_reg:x1; val_offset:1437*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1437*FLEN/8, x3, x2, x7) + +inst_512: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x0e and fm2 == 0x119 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3a5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79ff; op2val:0x3919; +op3val:0x77a5; valaddr_reg:x1; val_offset:1440*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1440*FLEN/8, x3, x2, x7) + +inst_513: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x0e and fm2 == 0x119 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3a5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79ff; op2val:0x3919; +op3val:0x77a5; valaddr_reg:x1; val_offset:1443*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1443*FLEN/8, x3, x2, x7) + +inst_514: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x0e and fm2 == 0x119 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3a5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79ff; op2val:0x3919; +op3val:0x77a5; valaddr_reg:x1; val_offset:1446*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1446*FLEN/8, x3, x2, x7) + +inst_515: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1b5 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x06b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x24f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71b5; op2val:0x446b; +op3val:0x7a4f; valaddr_reg:x1; val_offset:1449*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1449*FLEN/8, x3, x2, x7) + +inst_516: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1b5 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x06b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x24f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71b5; op2val:0x446b; +op3val:0x7a4f; valaddr_reg:x1; val_offset:1452*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1452*FLEN/8, x3, x2, x7) + +inst_517: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1b5 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x06b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x24f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71b5; op2val:0x446b; +op3val:0x7a4f; valaddr_reg:x1; val_offset:1455*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1455*FLEN/8, x3, x2, x7) + +inst_518: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1b5 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x06b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x24f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71b5; op2val:0x446b; +op3val:0x7a4f; valaddr_reg:x1; val_offset:1458*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1458*FLEN/8, x3, x2, x7) + +inst_519: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1b5 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x06b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x24f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71b5; op2val:0x446b; +op3val:0x7a4f; valaddr_reg:x1; val_offset:1461*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1461*FLEN/8, x3, x2, x7) + +inst_520: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x151 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0d1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x267 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7551; op2val:0x40d1; +op3val:0x7a67; valaddr_reg:x1; val_offset:1464*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1464*FLEN/8, x3, x2, x7) + +inst_521: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x151 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0d1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x267 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7551; op2val:0x40d1; +op3val:0x7a67; valaddr_reg:x1; val_offset:1467*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1467*FLEN/8, x3, x2, x7) + +inst_522: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x151 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0d1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x267 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7551; op2val:0x40d1; +op3val:0x7a67; valaddr_reg:x1; val_offset:1470*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1470*FLEN/8, x3, x2, x7) + +inst_523: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x151 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0d1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x267 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7551; op2val:0x40d1; +op3val:0x7a67; valaddr_reg:x1; val_offset:1473*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1473*FLEN/8, x3, x2, x7) + +inst_524: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x151 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0d1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x267 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7551; op2val:0x40d1; +op3val:0x7a67; valaddr_reg:x1; val_offset:1476*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1476*FLEN/8, x3, x2, x7) + +inst_525: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c4 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x284 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x254 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bc4; op2val:0x3684; +op3val:0x7654; valaddr_reg:x1; val_offset:1479*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1479*FLEN/8, x3, x2, x7) + +inst_526: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c4 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x284 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x254 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bc4; op2val:0x3684; +op3val:0x7654; valaddr_reg:x1; val_offset:1482*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1482*FLEN/8, x3, x2, x7) + +inst_527: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c4 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x284 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x254 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bc4; op2val:0x3684; +op3val:0x7654; valaddr_reg:x1; val_offset:1485*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1485*FLEN/8, x3, x2, x7) + +inst_528: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c4 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x284 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x254 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bc4; op2val:0x3684; +op3val:0x7654; valaddr_reg:x1; val_offset:1488*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1488*FLEN/8, x3, x2, x7) + +inst_529: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c4 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x284 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x254 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bc4; op2val:0x3684; +op3val:0x7654; valaddr_reg:x1; val_offset:1491*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1491*FLEN/8, x3, x2, x7) + +inst_530: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0b7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x392 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x766b; op2val:0x40b7; +op3val:0x7b92; valaddr_reg:x1; val_offset:1494*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1494*FLEN/8, x3, x2, x7) + +inst_531: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0b7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x392 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x766b; op2val:0x40b7; +op3val:0x7b92; valaddr_reg:x1; val_offset:1497*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1497*FLEN/8, x3, x2, x7) + +inst_532: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0b7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x392 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x766b; op2val:0x40b7; +op3val:0x7b92; valaddr_reg:x1; val_offset:1500*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1500*FLEN/8, x3, x2, x7) + +inst_533: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0b7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x392 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x766b; op2val:0x40b7; +op3val:0x7b92; valaddr_reg:x1; val_offset:1503*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1503*FLEN/8, x3, x2, x7) + +inst_534: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0b7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x392 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x766b; op2val:0x40b7; +op3val:0x7b92; valaddr_reg:x1; val_offset:1506*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1506*FLEN/8, x3, x2, x7) + +inst_535: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1cb and fs2 == 0 and fe2 == 0x0c and fm2 == 0x381 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x170 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79cb; op2val:0x3381; +op3val:0x7170; valaddr_reg:x1; val_offset:1509*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1509*FLEN/8, x3, x2, x7) + +inst_536: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1cb and fs2 == 0 and fe2 == 0x0c and fm2 == 0x381 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x170 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79cb; op2val:0x3381; +op3val:0x7170; valaddr_reg:x1; val_offset:1512*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1512*FLEN/8, x3, x2, x7) + +inst_537: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1cb and fs2 == 0 and fe2 == 0x0c and fm2 == 0x381 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x170 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79cb; op2val:0x3381; +op3val:0x7170; valaddr_reg:x1; val_offset:1515*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1515*FLEN/8, x3, x2, x7) + +inst_538: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1cb and fs2 == 0 and fe2 == 0x0c and fm2 == 0x381 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x170 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79cb; op2val:0x3381; +op3val:0x7170; valaddr_reg:x1; val_offset:1518*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1518*FLEN/8, x3, x2, x7) +RVTEST_SIGBASE(x2,signature_x2_4) + +inst_539: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1cb and fs2 == 0 and fe2 == 0x0c and fm2 == 0x381 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x170 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79cb; op2val:0x3381; +op3val:0x7170; valaddr_reg:x1; val_offset:1521*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1521*FLEN/8, x3, x2, x7) + +inst_540: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x010 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0c2 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7010; op2val:0x3cc2; +op3val:0x70d5; valaddr_reg:x1; val_offset:1524*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1524*FLEN/8, x3, x2, x7) + +inst_541: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x010 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0c2 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7010; op2val:0x3cc2; +op3val:0x70d5; valaddr_reg:x1; val_offset:1527*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1527*FLEN/8, x3, x2, x7) + +inst_542: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x010 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0c2 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7010; op2val:0x3cc2; +op3val:0x70d5; valaddr_reg:x1; val_offset:1530*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1530*FLEN/8, x3, x2, x7) + +inst_543: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x010 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0c2 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7010; op2val:0x3cc2; +op3val:0x70d5; valaddr_reg:x1; val_offset:1533*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1533*FLEN/8, x3, x2, x7) + +inst_544: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x010 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0c2 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7010; op2val:0x3cc2; +op3val:0x70d5; valaddr_reg:x1; val_offset:1536*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1536*FLEN/8, x3, x2, x7) + +inst_545: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x33c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x321 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x272 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b3c; op2val:0x3b21; +op3val:0x7a72; valaddr_reg:x1; val_offset:1539*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1539*FLEN/8, x3, x2, x7) + +inst_546: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x33c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x321 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x272 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b3c; op2val:0x3b21; +op3val:0x7a72; valaddr_reg:x1; val_offset:1542*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1542*FLEN/8, x3, x2, x7) + +inst_547: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x33c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x321 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x272 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b3c; op2val:0x3b21; +op3val:0x7a72; valaddr_reg:x1; val_offset:1545*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1545*FLEN/8, x3, x2, x7) + +inst_548: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x33c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x321 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x272 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b3c; op2val:0x3b21; +op3val:0x7a72; valaddr_reg:x1; val_offset:1548*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1548*FLEN/8, x3, x2, x7) + +inst_549: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x33c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x321 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x272 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b3c; op2val:0x3b21; +op3val:0x7a72; valaddr_reg:x1; val_offset:1551*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1551*FLEN/8, x3, x2, x7) + +inst_550: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0ac and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1a7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x29b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70ac; op2val:0x45a7; +op3val:0x7a9b; valaddr_reg:x1; val_offset:1554*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1554*FLEN/8, x3, x2, x7) + +inst_551: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0ac and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1a7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x29b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70ac; op2val:0x45a7; +op3val:0x7a9b; valaddr_reg:x1; val_offset:1557*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1557*FLEN/8, x3, x2, x7) + +inst_552: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0ac and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1a7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x29b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70ac; op2val:0x45a7; +op3val:0x7a9b; valaddr_reg:x1; val_offset:1560*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1560*FLEN/8, x3, x2, x7) + +inst_553: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0ac and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1a7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x29b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70ac; op2val:0x45a7; +op3val:0x7a9b; valaddr_reg:x1; val_offset:1563*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1563*FLEN/8, x3, x2, x7) + +inst_554: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0ac and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1a7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x29b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70ac; op2val:0x45a7; +op3val:0x7a9b; valaddr_reg:x1; val_offset:1566*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1566*FLEN/8, x3, x2, x7) + +inst_555: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x15d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x141 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd6; op2val:0x395d; +op3val:0x7941; valaddr_reg:x1; val_offset:1569*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1569*FLEN/8, x3, x2, x7) + +inst_556: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x15d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x141 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd6; op2val:0x395d; +op3val:0x7941; valaddr_reg:x1; val_offset:1572*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1572*FLEN/8, x3, x2, x7) + +inst_557: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x15d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x141 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd6; op2val:0x395d; +op3val:0x7941; valaddr_reg:x1; val_offset:1575*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1575*FLEN/8, x3, x2, x7) + +inst_558: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x15d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x141 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd6; op2val:0x395d; +op3val:0x7941; valaddr_reg:x1; val_offset:1578*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1578*FLEN/8, x3, x2, x7) + +inst_559: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x15d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x141 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd6; op2val:0x395d; +op3val:0x7941; valaddr_reg:x1; val_offset:1581*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1581*FLEN/8, x3, x2, x7) + +inst_560: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x19a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x243 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x063 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x759a; op2val:0x3e43; +op3val:0x7863; valaddr_reg:x1; val_offset:1584*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1584*FLEN/8, x3, x2, x7) + +inst_561: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x19a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x243 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x063 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x759a; op2val:0x3e43; +op3val:0x7863; valaddr_reg:x1; val_offset:1587*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1587*FLEN/8, x3, x2, x7) + +inst_562: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x19a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x243 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x063 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x759a; op2val:0x3e43; +op3val:0x7863; valaddr_reg:x1; val_offset:1590*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1590*FLEN/8, x3, x2, x7) + +inst_563: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x19a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x243 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x063 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x759a; op2val:0x3e43; +op3val:0x7863; valaddr_reg:x1; val_offset:1593*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1593*FLEN/8, x3, x2, x7) + +inst_564: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x19a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x243 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x063 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x759a; op2val:0x3e43; +op3val:0x7863; valaddr_reg:x1; val_offset:1596*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1596*FLEN/8, x3, x2, x7) + +inst_565: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x030 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2f7 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x34b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7030; op2val:0x2ef7; +op3val:0x634b; valaddr_reg:x1; val_offset:1599*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1599*FLEN/8, x3, x2, x7) + +inst_566: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x030 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2f7 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x34b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7030; op2val:0x2ef7; +op3val:0x634b; valaddr_reg:x1; val_offset:1602*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1602*FLEN/8, x3, x2, x7) + +inst_567: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x030 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2f7 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x34b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7030; op2val:0x2ef7; +op3val:0x634b; valaddr_reg:x1; val_offset:1605*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1605*FLEN/8, x3, x2, x7) + +inst_568: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x030 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2f7 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x34b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7030; op2val:0x2ef7; +op3val:0x634b; valaddr_reg:x1; val_offset:1608*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1608*FLEN/8, x3, x2, x7) + +inst_569: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x030 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2f7 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x34b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7030; op2val:0x2ef7; +op3val:0x634b; valaddr_reg:x1; val_offset:1611*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1611*FLEN/8, x3, x2, x7) + +inst_570: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x15a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x131 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bc3; op2val:0x395a; +op3val:0x7931; valaddr_reg:x1; val_offset:1614*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1614*FLEN/8, x3, x2, x7) + +inst_571: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x15a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x131 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bc3; op2val:0x395a; +op3val:0x7931; valaddr_reg:x1; val_offset:1617*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1617*FLEN/8, x3, x2, x7) + +inst_572: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x15a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x131 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bc3; op2val:0x395a; +op3val:0x7931; valaddr_reg:x1; val_offset:1620*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1620*FLEN/8, x3, x2, x7) + +inst_573: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x15a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x131 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bc3; op2val:0x395a; +op3val:0x7931; valaddr_reg:x1; val_offset:1623*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1623*FLEN/8, x3, x2, x7) + +inst_574: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x15a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x131 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bc3; op2val:0x395a; +op3val:0x7931; valaddr_reg:x1; val_offset:1626*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1626*FLEN/8, x3, x2, x7) + +inst_575: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x035 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x317 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x377 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7835; op2val:0x3f17; +op3val:0x7b77; valaddr_reg:x1; val_offset:1629*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1629*FLEN/8, x3, x2, x7) + +inst_576: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x035 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x317 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x377 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7835; op2val:0x3f17; +op3val:0x7b77; valaddr_reg:x1; val_offset:1632*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1632*FLEN/8, x3, x2, x7) + +inst_577: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x035 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x317 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x377 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7835; op2val:0x3f17; +op3val:0x7b77; valaddr_reg:x1; val_offset:1635*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1635*FLEN/8, x3, x2, x7) + +inst_578: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x035 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x317 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x377 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7835; op2val:0x3f17; +op3val:0x7b77; valaddr_reg:x1; val_offset:1638*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1638*FLEN/8, x3, x2, x7) + +inst_579: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x035 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x317 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x377 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7835; op2val:0x3f17; +op3val:0x7b77; valaddr_reg:x1; val_offset:1641*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1641*FLEN/8, x3, x2, x7) + +inst_580: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2f0 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x004 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76f0; op2val:0x4004; +op3val:0x7af8; valaddr_reg:x1; val_offset:1644*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1644*FLEN/8, x3, x2, x7) + +inst_581: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2f0 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x004 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76f0; op2val:0x4004; +op3val:0x7af8; valaddr_reg:x1; val_offset:1647*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1647*FLEN/8, x3, x2, x7) + +inst_582: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2f0 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x004 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76f0; op2val:0x4004; +op3val:0x7af8; valaddr_reg:x1; val_offset:1650*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1650*FLEN/8, x3, x2, x7) + +inst_583: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2f0 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x004 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76f0; op2val:0x4004; +op3val:0x7af8; valaddr_reg:x1; val_offset:1653*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1653*FLEN/8, x3, x2, x7) + +inst_584: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2f0 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x004 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76f0; op2val:0x4004; +op3val:0x7af8; valaddr_reg:x1; val_offset:1656*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1656*FLEN/8, x3, x2, x7) + +inst_585: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x29b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x016 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a9b; op2val:0x3416; +op3val:0x72c0; valaddr_reg:x1; val_offset:1659*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1659*FLEN/8, x3, x2, x7) + +inst_586: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x29b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x016 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2c0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a9b; op2val:0x3416; +op3val:0x72c0; valaddr_reg:x1; val_offset:1662*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1662*FLEN/8, x3, x2, x7) + +inst_587: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x29b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x016 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2c0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a9b; op2val:0x3416; +op3val:0x72c0; valaddr_reg:x1; val_offset:1665*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1665*FLEN/8, x3, x2, x7) + +inst_588: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x29b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x016 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2c0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a9b; op2val:0x3416; +op3val:0x72c0; valaddr_reg:x1; val_offset:1668*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1668*FLEN/8, x3, x2, x7) + +inst_589: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x29b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x016 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2c0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a9b; op2val:0x3416; +op3val:0x72c0; valaddr_reg:x1; val_offset:1671*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1671*FLEN/8, x3, x2, x7) + +inst_590: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x007 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0a7 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0af and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7407; op2val:0x3ca7; +op3val:0x74af; valaddr_reg:x1; val_offset:1674*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1674*FLEN/8, x3, x2, x7) + +inst_591: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x007 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0a7 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0af and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7407; op2val:0x3ca7; +op3val:0x74af; valaddr_reg:x1; val_offset:1677*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1677*FLEN/8, x3, x2, x7) + +inst_592: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x007 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0a7 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0af and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7407; op2val:0x3ca7; +op3val:0x74af; valaddr_reg:x1; val_offset:1680*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1680*FLEN/8, x3, x2, x7) + +inst_593: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x007 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0a7 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0af and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7407; op2val:0x3ca7; +op3val:0x74af; valaddr_reg:x1; val_offset:1683*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1683*FLEN/8, x3, x2, x7) + +inst_594: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x007 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0a7 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0af and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7407; op2val:0x3ca7; +op3val:0x74af; valaddr_reg:x1; val_offset:1686*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1686*FLEN/8, x3, x2, x7) + +inst_595: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3b1 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0e0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0b0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73b1; op2val:0x40e0; +op3val:0x78b0; valaddr_reg:x1; val_offset:1689*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1689*FLEN/8, x3, x2, x7) + +inst_596: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3b1 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0e0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0b0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73b1; op2val:0x40e0; +op3val:0x78b0; valaddr_reg:x1; val_offset:1692*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1692*FLEN/8, x3, x2, x7) + +inst_597: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3b1 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0e0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0b0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73b1; op2val:0x40e0; +op3val:0x78b0; valaddr_reg:x1; val_offset:1695*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1695*FLEN/8, x3, x2, x7) + +inst_598: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3b1 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0e0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0b0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73b1; op2val:0x40e0; +op3val:0x78b0; valaddr_reg:x1; val_offset:1698*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1698*FLEN/8, x3, x2, x7) + +inst_599: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3b1 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0e0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0b0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73b1; op2val:0x40e0; +op3val:0x78b0; valaddr_reg:x1; val_offset:1701*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1701*FLEN/8, x3, x2, x7) + +inst_600: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x276 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2b3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7425; op2val:0x3e76; +op3val:0x76b3; valaddr_reg:x1; val_offset:1704*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1704*FLEN/8, x3, x2, x7) + +inst_601: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x276 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2b3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7425; op2val:0x3e76; +op3val:0x76b3; valaddr_reg:x1; val_offset:1707*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1707*FLEN/8, x3, x2, x7) + +inst_602: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x276 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2b3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7425; op2val:0x3e76; +op3val:0x76b3; valaddr_reg:x1; val_offset:1710*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1710*FLEN/8, x3, x2, x7) + +inst_603: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x276 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2b3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7425; op2val:0x3e76; +op3val:0x76b3; valaddr_reg:x1; val_offset:1713*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1713*FLEN/8, x3, x2, x7) + +inst_604: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x276 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2b3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7425; op2val:0x3e76; +op3val:0x76b3; valaddr_reg:x1; val_offset:1716*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1716*FLEN/8, x3, x2, x7) + +inst_605: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x031 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x2f1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x346 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7031; op2val:0x46f1; +op3val:0x7b46; valaddr_reg:x1; val_offset:1719*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1719*FLEN/8, x3, x2, x7) + +inst_606: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x031 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x2f1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x346 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7031; op2val:0x46f1; +op3val:0x7b46; valaddr_reg:x1; val_offset:1722*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1722*FLEN/8, x3, x2, x7) + +inst_607: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x031 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x2f1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x346 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7031; op2val:0x46f1; +op3val:0x7b46; valaddr_reg:x1; val_offset:1725*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1725*FLEN/8, x3, x2, x7) + +inst_608: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x031 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x2f1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x346 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7031; op2val:0x46f1; +op3val:0x7b46; valaddr_reg:x1; val_offset:1728*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1728*FLEN/8, x3, x2, x7) + +inst_609: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x031 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x2f1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x346 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7031; op2val:0x46f1; +op3val:0x7b46; valaddr_reg:x1; val_offset:1731*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1731*FLEN/8, x3, x2, x7) + +inst_610: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x12e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x353 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75a8; op2val:0x3d2e; +op3val:0x7753; valaddr_reg:x1; val_offset:1734*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1734*FLEN/8, x3, x2, x7) + +inst_611: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x12e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x353 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75a8; op2val:0x3d2e; +op3val:0x7753; valaddr_reg:x1; val_offset:1737*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1737*FLEN/8, x3, x2, x7) + +inst_612: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x12e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x353 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75a8; op2val:0x3d2e; +op3val:0x7753; valaddr_reg:x1; val_offset:1740*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1740*FLEN/8, x3, x2, x7) + +inst_613: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x12e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x353 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75a8; op2val:0x3d2e; +op3val:0x7753; valaddr_reg:x1; val_offset:1743*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1743*FLEN/8, x3, x2, x7) + +inst_614: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x12e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x353 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75a8; op2val:0x3d2e; +op3val:0x7753; valaddr_reg:x1; val_offset:1746*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1746*FLEN/8, x3, x2, x7) + +inst_615: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0aa and fs2 == 0 and fe2 == 0x0f and fm2 == 0x233 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x33b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78aa; op2val:0x3e33; +op3val:0x7b3b; valaddr_reg:x1; val_offset:1749*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1749*FLEN/8, x3, x2, x7) + +inst_616: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0aa and fs2 == 0 and fe2 == 0x0f and fm2 == 0x233 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x33b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78aa; op2val:0x3e33; +op3val:0x7b3b; valaddr_reg:x1; val_offset:1752*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1752*FLEN/8, x3, x2, x7) + +inst_617: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0aa and fs2 == 0 and fe2 == 0x0f and fm2 == 0x233 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x33b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78aa; op2val:0x3e33; +op3val:0x7b3b; valaddr_reg:x1; val_offset:1755*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1755*FLEN/8, x3, x2, x7) + +inst_618: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0aa and fs2 == 0 and fe2 == 0x0f and fm2 == 0x233 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x33b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78aa; op2val:0x3e33; +op3val:0x7b3b; valaddr_reg:x1; val_offset:1758*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1758*FLEN/8, x3, x2, x7) + +inst_619: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0aa and fs2 == 0 and fe2 == 0x0f and fm2 == 0x233 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x33b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78aa; op2val:0x3e33; +op3val:0x7b3b; valaddr_reg:x1; val_offset:1761*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1761*FLEN/8, x3, x2, x7) + +inst_620: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2ba and fs2 == 0 and fe2 == 0x10 and fm2 == 0x05d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x356 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76ba; op2val:0x405d; +op3val:0x7b56; valaddr_reg:x1; val_offset:1764*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1764*FLEN/8, x3, x2, x7) + +inst_621: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2ba and fs2 == 0 and fe2 == 0x10 and fm2 == 0x05d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x356 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76ba; op2val:0x405d; +op3val:0x7b56; valaddr_reg:x1; val_offset:1767*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1767*FLEN/8, x3, x2, x7) + +inst_622: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2ba and fs2 == 0 and fe2 == 0x10 and fm2 == 0x05d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x356 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76ba; op2val:0x405d; +op3val:0x7b56; valaddr_reg:x1; val_offset:1770*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1770*FLEN/8, x3, x2, x7) + +inst_623: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2ba and fs2 == 0 and fe2 == 0x10 and fm2 == 0x05d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x356 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76ba; op2val:0x405d; +op3val:0x7b56; valaddr_reg:x1; val_offset:1773*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1773*FLEN/8, x3, x2, x7) + +inst_624: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2ba and fs2 == 0 and fe2 == 0x10 and fm2 == 0x05d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x356 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76ba; op2val:0x405d; +op3val:0x7b56; valaddr_reg:x1; val_offset:1776*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1776*FLEN/8, x3, x2, x7) + +inst_625: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x03d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x040 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7802; op2val:0x3c3d; +op3val:0x7840; valaddr_reg:x1; val_offset:1779*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1779*FLEN/8, x3, x2, x7) + +inst_626: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x03d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x040 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7802; op2val:0x3c3d; +op3val:0x7840; valaddr_reg:x1; val_offset:1782*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1782*FLEN/8, x3, x2, x7) + +inst_627: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x03d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x040 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7802; op2val:0x3c3d; +op3val:0x7840; valaddr_reg:x1; val_offset:1785*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1785*FLEN/8, x3, x2, x7) + +inst_628: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x03d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x040 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7802; op2val:0x3c3d; +op3val:0x7840; valaddr_reg:x1; val_offset:1788*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1788*FLEN/8, x3, x2, x7) + +inst_629: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x03d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x040 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7802; op2val:0x3c3d; +op3val:0x7840; valaddr_reg:x1; val_offset:1791*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1791*FLEN/8, x3, x2, x7) + +inst_630: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 0 and fe2 == 0x0a and fm2 == 0x093 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x0ca and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x782f; op2val:0x2893; +op3val:0x64ca; valaddr_reg:x1; val_offset:1794*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1794*FLEN/8, x3, x2, x7) + +inst_631: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 0 and fe2 == 0x0a and fm2 == 0x093 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x0ca and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x782f; op2val:0x2893; +op3val:0x64ca; valaddr_reg:x1; val_offset:1797*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1797*FLEN/8, x3, x2, x7) + +inst_632: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 0 and fe2 == 0x0a and fm2 == 0x093 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x0ca and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x782f; op2val:0x2893; +op3val:0x64ca; valaddr_reg:x1; val_offset:1800*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1800*FLEN/8, x3, x2, x7) + +inst_633: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 0 and fe2 == 0x0a and fm2 == 0x093 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x0ca and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x782f; op2val:0x2893; +op3val:0x64ca; valaddr_reg:x1; val_offset:1803*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1803*FLEN/8, x3, x2, x7) + +inst_634: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 0 and fe2 == 0x0a and fm2 == 0x093 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x0ca and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x782f; op2val:0x2893; +op3val:0x64ca; valaddr_reg:x1; val_offset:1806*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1806*FLEN/8, x3, x2, x7) + +inst_635: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x309 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2a8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x1db and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7709; op2val:0x36a8; +op3val:0x71db; valaddr_reg:x1; val_offset:1809*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1809*FLEN/8, x3, x2, x7) + +inst_636: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x309 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2a8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x1db and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7709; op2val:0x36a8; +op3val:0x71db; valaddr_reg:x1; val_offset:1812*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1812*FLEN/8, x3, x2, x7) + +inst_637: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x309 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2a8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x1db and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7709; op2val:0x36a8; +op3val:0x71db; valaddr_reg:x1; val_offset:1815*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1815*FLEN/8, x3, x2, x7) + +inst_638: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x309 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2a8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x1db and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7709; op2val:0x36a8; +op3val:0x71db; valaddr_reg:x1; val_offset:1818*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1818*FLEN/8, x3, x2, x7) + +inst_639: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x309 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2a8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x1db and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7709; op2val:0x36a8; +op3val:0x71db; valaddr_reg:x1; val_offset:1821*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1821*FLEN/8, x3, x2, x7) + +inst_640: +// fs1 == 0 and fe1 == 0x17 and fm1 == 0x00a and fs2 == 0 and fe2 == 0x16 and fm2 == 0x253 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x263 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5c0a; op2val:0x5a53; +op3val:0x7a63; valaddr_reg:x1; val_offset:1824*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1824*FLEN/8, x3, x2, x7) + +inst_641: +// fs1 == 0 and fe1 == 0x17 and fm1 == 0x00a and fs2 == 0 and fe2 == 0x16 and fm2 == 0x253 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x263 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5c0a; op2val:0x5a53; +op3val:0x7a63; valaddr_reg:x1; val_offset:1827*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1827*FLEN/8, x3, x2, x7) + +inst_642: +// fs1 == 0 and fe1 == 0x17 and fm1 == 0x00a and fs2 == 0 and fe2 == 0x16 and fm2 == 0x253 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x263 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5c0a; op2val:0x5a53; +op3val:0x7a63; valaddr_reg:x1; val_offset:1830*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1830*FLEN/8, x3, x2, x7) + +inst_643: +// fs1 == 0 and fe1 == 0x17 and fm1 == 0x00a and fs2 == 0 and fe2 == 0x16 and fm2 == 0x253 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x263 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5c0a; op2val:0x5a53; +op3val:0x7a63; valaddr_reg:x1; val_offset:1833*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1833*FLEN/8, x3, x2, x7) + +inst_644: +// fs1 == 0 and fe1 == 0x17 and fm1 == 0x00a and fs2 == 0 and fe2 == 0x16 and fm2 == 0x253 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x263 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5c0a; op2val:0x5a53; +op3val:0x7a63; valaddr_reg:x1; val_offset:1836*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1836*FLEN/8, x3, x2, x7) + +inst_645: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x183 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x17e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x392 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7183; op2val:0x417e; +op3val:0x7792; valaddr_reg:x1; val_offset:1839*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1839*FLEN/8, x3, x2, x7) + +inst_646: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x183 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x17e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x392 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7183; op2val:0x417e; +op3val:0x7792; valaddr_reg:x1; val_offset:1842*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1842*FLEN/8, x3, x2, x7) + +inst_647: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x183 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x17e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x392 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7183; op2val:0x417e; +op3val:0x7792; valaddr_reg:x1; val_offset:1845*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1845*FLEN/8, x3, x2, x7) + +inst_648: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x183 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x17e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x392 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7183; op2val:0x417e; +op3val:0x7792; valaddr_reg:x1; val_offset:1848*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1848*FLEN/8, x3, x2, x7) + +inst_649: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x183 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x17e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x392 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7183; op2val:0x417e; +op3val:0x7792; valaddr_reg:x1; val_offset:1851*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1851*FLEN/8, x3, x2, x7) + +inst_650: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1cc and fs2 == 0 and fe2 == 0x0e and fm2 == 0x223 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x073 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79cc; op2val:0x3a23; +op3val:0x7873; valaddr_reg:x1; val_offset:1854*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1854*FLEN/8, x3, x2, x7) + +inst_651: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1cc and fs2 == 0 and fe2 == 0x0e and fm2 == 0x223 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x073 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79cc; op2val:0x3a23; +op3val:0x7873; valaddr_reg:x1; val_offset:1857*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1857*FLEN/8, x3, x2, x7) + +inst_652: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1cc and fs2 == 0 and fe2 == 0x0e and fm2 == 0x223 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x073 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79cc; op2val:0x3a23; +op3val:0x7873; valaddr_reg:x1; val_offset:1860*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1860*FLEN/8, x3, x2, x7) + +inst_653: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1cc and fs2 == 0 and fe2 == 0x0e and fm2 == 0x223 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x073 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79cc; op2val:0x3a23; +op3val:0x7873; valaddr_reg:x1; val_offset:1863*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1863*FLEN/8, x3, x2, x7) + +inst_654: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1cc and fs2 == 0 and fe2 == 0x0e and fm2 == 0x223 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x073 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79cc; op2val:0x3a23; +op3val:0x7873; valaddr_reg:x1; val_offset:1866*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1866*FLEN/8, x3, x2, x7) + +inst_655: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x136 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x25c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x025 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7536; op2val:0x3e5c; +op3val:0x7825; valaddr_reg:x1; val_offset:1869*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1869*FLEN/8, x3, x2, x7) + +inst_656: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x136 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x25c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x025 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7536; op2val:0x3e5c; +op3val:0x7825; valaddr_reg:x1; val_offset:1872*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1872*FLEN/8, x3, x2, x7) + +inst_657: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x136 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x25c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x025 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7536; op2val:0x3e5c; +op3val:0x7825; valaddr_reg:x1; val_offset:1875*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1875*FLEN/8, x3, x2, x7) + +inst_658: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x136 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x25c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x025 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7536; op2val:0x3e5c; +op3val:0x7825; valaddr_reg:x1; val_offset:1878*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1878*FLEN/8, x3, x2, x7) + +inst_659: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x136 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x25c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x025 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7536; op2val:0x3e5c; +op3val:0x7825; valaddr_reg:x1; val_offset:1881*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1881*FLEN/8, x3, x2, x7) + +inst_660: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x071 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1a5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x245 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7871; op2val:0x3da5; +op3val:0x7a45; valaddr_reg:x1; val_offset:1884*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1884*FLEN/8, x3, x2, x7) + +inst_661: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x071 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1a5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x245 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7871; op2val:0x3da5; +op3val:0x7a45; valaddr_reg:x1; val_offset:1887*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1887*FLEN/8, x3, x2, x7) + +inst_662: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x071 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1a5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x245 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7871; op2val:0x3da5; +op3val:0x7a45; valaddr_reg:x1; val_offset:1890*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1890*FLEN/8, x3, x2, x7) + +inst_663: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x071 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1a5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x245 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7871; op2val:0x3da5; +op3val:0x7a45; valaddr_reg:x1; val_offset:1893*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1893*FLEN/8, x3, x2, x7) + +inst_664: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x071 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1a5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x245 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7871; op2val:0x3da5; +op3val:0x7a45; valaddr_reg:x1; val_offset:1896*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1896*FLEN/8, x3, x2, x7) + +inst_665: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2c9 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x147 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x07a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ec9; op2val:0x4547; +op3val:0x787a; valaddr_reg:x1; val_offset:1899*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1899*FLEN/8, x3, x2, x7) + +inst_666: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2c9 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x147 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x07a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ec9; op2val:0x4547; +op3val:0x787a; valaddr_reg:x1; val_offset:1902*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1902*FLEN/8, x3, x2, x7) +RVTEST_SIGBASE(x2,signature_x2_5) + +inst_667: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2c9 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x147 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x07a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ec9; op2val:0x4547; +op3val:0x787a; valaddr_reg:x1; val_offset:1905*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1905*FLEN/8, x3, x2, x7) + +inst_668: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2c9 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x147 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x07a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ec9; op2val:0x4547; +op3val:0x787a; valaddr_reg:x1; val_offset:1908*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1908*FLEN/8, x3, x2, x7) + +inst_669: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2c9 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x147 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x07a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ec9; op2val:0x4547; +op3val:0x787a; valaddr_reg:x1; val_offset:1911*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1911*FLEN/8, x3, x2, x7) + +inst_670: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3f2 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x075 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x06d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73f2; op2val:0x3c75; +op3val:0x746d; valaddr_reg:x1; val_offset:1914*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1914*FLEN/8, x3, x2, x7) + +inst_671: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3f2 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x075 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x06d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73f2; op2val:0x3c75; +op3val:0x746d; valaddr_reg:x1; val_offset:1917*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1917*FLEN/8, x3, x2, x7) + +inst_672: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3f2 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x075 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x06d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73f2; op2val:0x3c75; +op3val:0x746d; valaddr_reg:x1; val_offset:1920*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1920*FLEN/8, x3, x2, x7) + +inst_673: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3f2 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x075 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x06d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73f2; op2val:0x3c75; +op3val:0x746d; valaddr_reg:x1; val_offset:1923*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1923*FLEN/8, x3, x2, x7) + +inst_674: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3f2 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x075 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x06d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73f2; op2val:0x3c75; +op3val:0x746d; valaddr_reg:x1; val_offset:1926*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1926*FLEN/8, x3, x2, x7) + +inst_675: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x22c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x142 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a2c; op2val:0x3942; +op3val:0x780f; valaddr_reg:x1; val_offset:1929*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1929*FLEN/8, x3, x2, x7) + +inst_676: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x22c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x142 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a2c; op2val:0x3942; +op3val:0x780f; valaddr_reg:x1; val_offset:1932*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1932*FLEN/8, x3, x2, x7) + +inst_677: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x22c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x142 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a2c; op2val:0x3942; +op3val:0x780f; valaddr_reg:x1; val_offset:1935*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1935*FLEN/8, x3, x2, x7) + +inst_678: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x22c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x142 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a2c; op2val:0x3942; +op3val:0x780f; valaddr_reg:x1; val_offset:1938*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1938*FLEN/8, x3, x2, x7) + +inst_679: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x22c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x142 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a2c; op2val:0x3942; +op3val:0x780f; valaddr_reg:x1; val_offset:1941*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1941*FLEN/8, x3, x2, x7) + +inst_680: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x07d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x169 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x213 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x787d; op2val:0x3d69; +op3val:0x7a13; valaddr_reg:x1; val_offset:1944*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1944*FLEN/8, x3, x2, x7) + +inst_681: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x07d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x169 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x213 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x787d; op2val:0x3d69; +op3val:0x7a13; valaddr_reg:x1; val_offset:1947*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1947*FLEN/8, x3, x2, x7) + +inst_682: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x07d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x169 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x213 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x787d; op2val:0x3d69; +op3val:0x7a13; valaddr_reg:x1; val_offset:1950*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1950*FLEN/8, x3, x2, x7) + +inst_683: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x07d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x169 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x213 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x787d; op2val:0x3d69; +op3val:0x7a13; valaddr_reg:x1; val_offset:1953*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1953*FLEN/8, x3, x2, x7) + +inst_684: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x07d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x169 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x213 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x787d; op2val:0x3d69; +op3val:0x7a13; valaddr_reg:x1; val_offset:1956*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1956*FLEN/8, x3, x2, x7) + +inst_685: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x34b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3c5 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x316 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b4b; op2val:0x37c5; +op3val:0x7716; valaddr_reg:x1; val_offset:1959*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1959*FLEN/8, x3, x2, x7) + +inst_686: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x34b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3c5 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x316 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b4b; op2val:0x37c5; +op3val:0x7716; valaddr_reg:x1; val_offset:1962*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1962*FLEN/8, x3, x2, x7) + +inst_687: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x34b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3c5 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x316 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b4b; op2val:0x37c5; +op3val:0x7716; valaddr_reg:x1; val_offset:1965*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1965*FLEN/8, x3, x2, x7) + +inst_688: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x34b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3c5 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x316 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b4b; op2val:0x37c5; +op3val:0x7716; valaddr_reg:x1; val_offset:1968*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1968*FLEN/8, x3, x2, x7) + +inst_689: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x34b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3c5 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x316 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b4b; op2val:0x37c5; +op3val:0x7716; valaddr_reg:x1; val_offset:1971*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1971*FLEN/8, x3, x2, x7) + +inst_690: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x29a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e5; op2val:0x3a9a; +op3val:0x780a; valaddr_reg:x1; val_offset:1974*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1974*FLEN/8, x3, x2, x7) + +inst_691: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x29a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e5; op2val:0x3a9a; +op3val:0x780a; valaddr_reg:x1; val_offset:1977*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1977*FLEN/8, x3, x2, x7) + +inst_692: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x29a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e5; op2val:0x3a9a; +op3val:0x780a; valaddr_reg:x1; val_offset:1980*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1980*FLEN/8, x3, x2, x7) + +inst_693: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x29a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e5; op2val:0x3a9a; +op3val:0x780a; valaddr_reg:x1; val_offset:1983*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1983*FLEN/8, x3, x2, x7) + +inst_694: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x29a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e5; op2val:0x3a9a; +op3val:0x780a; valaddr_reg:x1; val_offset:1986*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1986*FLEN/8, x3, x2, x7) + +inst_695: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x018 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x169 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x18a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7818; op2val:0x3d69; +op3val:0x798a; valaddr_reg:x1; val_offset:1989*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1989*FLEN/8, x3, x2, x7) + +inst_696: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x018 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x169 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x18a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7818; op2val:0x3d69; +op3val:0x798a; valaddr_reg:x1; val_offset:1992*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1992*FLEN/8, x3, x2, x7) + +inst_697: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x018 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x169 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x18a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7818; op2val:0x3d69; +op3val:0x798a; valaddr_reg:x1; val_offset:1995*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1995*FLEN/8, x3, x2, x7) + +inst_698: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x018 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x169 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x18a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7818; op2val:0x3d69; +op3val:0x798a; valaddr_reg:x1; val_offset:1998*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1998*FLEN/8, x3, x2, x7) + +inst_699: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x018 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x169 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x18a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7818; op2val:0x3d69; +op3val:0x798a; valaddr_reg:x1; val_offset:2001*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2001*FLEN/8, x3, x2, x7) + +inst_700: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x33b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0b7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x043 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x773b; op2val:0x3cb7; +op3val:0x7843; valaddr_reg:x1; val_offset:2004*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2004*FLEN/8, x3, x2, x7) + +inst_701: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x33b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0b7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x043 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x773b; op2val:0x3cb7; +op3val:0x7843; valaddr_reg:x1; val_offset:2007*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2007*FLEN/8, x3, x2, x7) + +inst_702: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x33b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0b7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x043 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x773b; op2val:0x3cb7; +op3val:0x7843; valaddr_reg:x1; val_offset:2010*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2010*FLEN/8, x3, x2, x7) + +inst_703: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x33b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0b7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x043 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x773b; op2val:0x3cb7; +op3val:0x7843; valaddr_reg:x1; val_offset:2013*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2013*FLEN/8, x3, x2, x7) + +inst_704: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x33b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0b7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x043 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x773b; op2val:0x3cb7; +op3val:0x7843; valaddr_reg:x1; val_offset:2016*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2016*FLEN/8, x3, x2, x7) + +inst_705: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3e0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x387 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77a5; op2val:0x3fe0; +op3val:0x7b87; valaddr_reg:x1; val_offset:2019*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2019*FLEN/8, x3, x2, x7) + +inst_706: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3e0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x387 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77a5; op2val:0x3fe0; +op3val:0x7b87; valaddr_reg:x1; val_offset:2022*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2022*FLEN/8, x3, x2, x7) + +inst_707: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3e0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x387 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77a5; op2val:0x3fe0; +op3val:0x7b87; valaddr_reg:x1; val_offset:2025*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2025*FLEN/8, x3, x2, x7) + +inst_708: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3e0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x387 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77a5; op2val:0x3fe0; +op3val:0x7b87; valaddr_reg:x1; val_offset:2028*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2028*FLEN/8, x3, x2, x7) + +inst_709: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3e0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x387 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77a5; op2val:0x3fe0; +op3val:0x7b87; valaddr_reg:x1; val_offset:2031*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2031*FLEN/8, x3, x2, x7) + +inst_710: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x197 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x103 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x302 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7997; op2val:0x3d03; +op3val:0x7b02; valaddr_reg:x1; val_offset:2034*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2034*FLEN/8, x3, x2, x7) + +inst_711: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x197 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x103 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x302 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7997; op2val:0x3d03; +op3val:0x7b02; valaddr_reg:x1; val_offset:2037*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2037*FLEN/8, x3, x2, x7) + +inst_712: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x197 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x103 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x302 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7997; op2val:0x3d03; +op3val:0x7b02; valaddr_reg:x1; val_offset:2040*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2040*FLEN/8, x3, x2, x7) + +inst_713: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x197 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x103 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x302 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7997; op2val:0x3d03; +op3val:0x7b02; valaddr_reg:x1; val_offset:2043*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2043*FLEN/8, x3, x2, x7) + +inst_714: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x197 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x103 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x302 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7997; op2val:0x3d03; +op3val:0x7b02; valaddr_reg:x1; val_offset:2046*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2046*FLEN/8, x3, x2, x7) + +inst_715: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x388 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x068 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x026 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b88; op2val:0x3468; +op3val:0x7426; valaddr_reg:x1; val_offset:2049*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2049*FLEN/8, x3, x2, x7) + +inst_716: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x388 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x068 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x026 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b88; op2val:0x3468; +op3val:0x7426; valaddr_reg:x1; val_offset:2052*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2052*FLEN/8, x3, x2, x7) + +inst_717: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x388 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x068 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x026 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b88; op2val:0x3468; +op3val:0x7426; valaddr_reg:x1; val_offset:2055*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2055*FLEN/8, x3, x2, x7) + +inst_718: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x388 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x068 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x026 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b88; op2val:0x3468; +op3val:0x7426; valaddr_reg:x1; val_offset:2058*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2058*FLEN/8, x3, x2, x7) + +inst_719: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x388 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x068 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x026 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b88; op2val:0x3468; +op3val:0x7426; valaddr_reg:x1; val_offset:2061*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2061*FLEN/8, x3, x2, x7) + +inst_720: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x079 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2be and fs3 == 0 and fe3 == 0x1e and fm3 == 0x38a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7879; op2val:0x3ebe; +op3val:0x7b8a; valaddr_reg:x1; val_offset:2064*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2064*FLEN/8, x3, x2, x7) + +inst_721: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x079 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2be and fs3 == 0 and fe3 == 0x1e and fm3 == 0x38a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7879; op2val:0x3ebe; +op3val:0x7b8a; valaddr_reg:x1; val_offset:2067*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2067*FLEN/8, x3, x2, x7) + +inst_722: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x079 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2be and fs3 == 0 and fe3 == 0x1e and fm3 == 0x38a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7879; op2val:0x3ebe; +op3val:0x7b8a; valaddr_reg:x1; val_offset:2070*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2070*FLEN/8, x3, x2, x7) + +inst_723: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x079 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2be and fs3 == 0 and fe3 == 0x1e and fm3 == 0x38a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7879; op2val:0x3ebe; +op3val:0x7b8a; valaddr_reg:x1; val_offset:2073*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2073*FLEN/8, x3, x2, x7) + +inst_724: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x079 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2be and fs3 == 0 and fe3 == 0x1e and fm3 == 0x38a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7879; op2val:0x3ebe; +op3val:0x7b8a; valaddr_reg:x1; val_offset:2076*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2076*FLEN/8, x3, x2, x7) + +inst_725: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b7 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x139 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x062 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ab7; op2val:0x3139; +op3val:0x7062; valaddr_reg:x1; val_offset:2079*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2079*FLEN/8, x3, x2, x7) + +inst_726: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b7 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x139 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x062 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ab7; op2val:0x3139; +op3val:0x7062; valaddr_reg:x1; val_offset:2082*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2082*FLEN/8, x3, x2, x7) + +inst_727: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b7 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x139 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x062 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ab7; op2val:0x3139; +op3val:0x7062; valaddr_reg:x1; val_offset:2085*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2085*FLEN/8, x3, x2, x7) + +inst_728: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b7 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x139 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x062 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ab7; op2val:0x3139; +op3val:0x7062; valaddr_reg:x1; val_offset:2088*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2088*FLEN/8, x3, x2, x7) + +inst_729: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b7 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x139 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x062 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ab7; op2val:0x3139; +op3val:0x7062; valaddr_reg:x1; val_offset:2091*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2091*FLEN/8, x3, x2, x7) + +inst_730: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3c7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x345 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x312 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6fc7; op2val:0x4345; +op3val:0x7712; valaddr_reg:x1; val_offset:2094*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2094*FLEN/8, x3, x2, x7) + +inst_731: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3c7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x345 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x312 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6fc7; op2val:0x4345; +op3val:0x7712; valaddr_reg:x1; val_offset:2097*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2097*FLEN/8, x3, x2, x7) + +inst_732: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3c7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x345 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x312 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6fc7; op2val:0x4345; +op3val:0x7712; valaddr_reg:x1; val_offset:2100*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2100*FLEN/8, x3, x2, x7) + +inst_733: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3c7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x345 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x312 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6fc7; op2val:0x4345; +op3val:0x7712; valaddr_reg:x1; val_offset:2103*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2103*FLEN/8, x3, x2, x7) + +inst_734: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3c7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x345 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x312 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6fc7; op2val:0x4345; +op3val:0x7712; valaddr_reg:x1; val_offset:2106*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2106*FLEN/8, x3, x2, x7) + +inst_735: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0a4 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x2a2 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3b2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ca4; op2val:0x42a2; +op3val:0x73b2; valaddr_reg:x1; val_offset:2109*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2109*FLEN/8, x3, x2, x7) + +inst_736: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0a4 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x2a2 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3b2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ca4; op2val:0x42a2; +op3val:0x73b2; valaddr_reg:x1; val_offset:2112*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2112*FLEN/8, x3, x2, x7) + +inst_737: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0a4 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x2a2 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3b2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ca4; op2val:0x42a2; +op3val:0x73b2; valaddr_reg:x1; val_offset:2115*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2115*FLEN/8, x3, x2, x7) + +inst_738: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0a4 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x2a2 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3b2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ca4; op2val:0x42a2; +op3val:0x73b2; valaddr_reg:x1; val_offset:2118*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2118*FLEN/8, x3, x2, x7) + +inst_739: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0a4 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x2a2 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3b2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ca4; op2val:0x42a2; +op3val:0x73b2; valaddr_reg:x1; val_offset:2121*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2121*FLEN/8, x3, x2, x7) + +inst_740: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0ad and fs2 == 0 and fe2 == 0x12 and fm2 == 0x093 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x15a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6cad; op2val:0x4893; +op3val:0x795a; valaddr_reg:x1; val_offset:2124*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2124*FLEN/8, x3, x2, x7) + +inst_741: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0ad and fs2 == 0 and fe2 == 0x12 and fm2 == 0x093 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x15a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6cad; op2val:0x4893; +op3val:0x795a; valaddr_reg:x1; val_offset:2127*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2127*FLEN/8, x3, x2, x7) + +inst_742: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0ad and fs2 == 0 and fe2 == 0x12 and fm2 == 0x093 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x15a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6cad; op2val:0x4893; +op3val:0x795a; valaddr_reg:x1; val_offset:2130*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2130*FLEN/8, x3, x2, x7) + +inst_743: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0ad and fs2 == 0 and fe2 == 0x12 and fm2 == 0x093 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x15a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6cad; op2val:0x4893; +op3val:0x795a; valaddr_reg:x1; val_offset:2133*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2133*FLEN/8, x3, x2, x7) + +inst_744: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0ad and fs2 == 0 and fe2 == 0x12 and fm2 == 0x093 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x15a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6cad; op2val:0x4893; +op3val:0x795a; valaddr_reg:x1; val_offset:2136*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2136*FLEN/8, x3, x2, x7) + +inst_745: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x244 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x093 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x32c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a44; op2val:0x3c93; +op3val:0x7b2c; valaddr_reg:x1; val_offset:2139*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2139*FLEN/8, x3, x2, x7) + +inst_746: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x244 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x093 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x32c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a44; op2val:0x3c93; +op3val:0x7b2c; valaddr_reg:x1; val_offset:2142*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2142*FLEN/8, x3, x2, x7) + +inst_747: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x244 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x093 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x32c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a44; op2val:0x3c93; +op3val:0x7b2c; valaddr_reg:x1; val_offset:2145*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2145*FLEN/8, x3, x2, x7) + +inst_748: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x244 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x093 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x32c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a44; op2val:0x3c93; +op3val:0x7b2c; valaddr_reg:x1; val_offset:2148*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2148*FLEN/8, x3, x2, x7) + +inst_749: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x244 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x093 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x32c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a44; op2val:0x3c93; +op3val:0x7b2c; valaddr_reg:x1; val_offset:2151*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2151*FLEN/8, x3, x2, x7) + +inst_750: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0a2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1b9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70f0; op2val:0x44a2; +op3val:0x79b9; valaddr_reg:x1; val_offset:2154*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2154*FLEN/8, x3, x2, x7) + +inst_751: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0a2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1b9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70f0; op2val:0x44a2; +op3val:0x79b9; valaddr_reg:x1; val_offset:2157*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2157*FLEN/8, x3, x2, x7) + +inst_752: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0a2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1b9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70f0; op2val:0x44a2; +op3val:0x79b9; valaddr_reg:x1; val_offset:2160*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2160*FLEN/8, x3, x2, x7) + +inst_753: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0a2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1b9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70f0; op2val:0x44a2; +op3val:0x79b9; valaddr_reg:x1; val_offset:2163*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2163*FLEN/8, x3, x2, x7) + +inst_754: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0a2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1b9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70f0; op2val:0x44a2; +op3val:0x79b9; valaddr_reg:x1; val_offset:2166*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2166*FLEN/8, x3, x2, x7) + +inst_755: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x147 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2ee and fs3 == 0 and fe3 == 0x1c and fm3 == 0x092 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7947; op2val:0x32ee; +op3val:0x7092; valaddr_reg:x1; val_offset:2169*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2169*FLEN/8, x3, x2, x7) + +inst_756: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x147 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2ee and fs3 == 0 and fe3 == 0x1c and fm3 == 0x092 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7947; op2val:0x32ee; +op3val:0x7092; valaddr_reg:x1; val_offset:2172*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2172*FLEN/8, x3, x2, x7) + +inst_757: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x147 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2ee and fs3 == 0 and fe3 == 0x1c and fm3 == 0x092 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7947; op2val:0x32ee; +op3val:0x7092; valaddr_reg:x1; val_offset:2175*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2175*FLEN/8, x3, x2, x7) + +inst_758: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x147 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2ee and fs3 == 0 and fe3 == 0x1c and fm3 == 0x092 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7947; op2val:0x32ee; +op3val:0x7092; valaddr_reg:x1; val_offset:2178*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2178*FLEN/8, x3, x2, x7) + +inst_759: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x147 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2ee and fs3 == 0 and fe3 == 0x1c and fm3 == 0x092 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7947; op2val:0x32ee; +op3val:0x7092; valaddr_reg:x1; val_offset:2181*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2181*FLEN/8, x3, x2, x7) + +inst_760: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x062 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3bc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b0f; op2val:0x3c62; +op3val:0x7bbc; valaddr_reg:x1; val_offset:2184*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2184*FLEN/8, x3, x2, x7) + +inst_761: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x062 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3bc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b0f; op2val:0x3c62; +op3val:0x7bbc; valaddr_reg:x1; val_offset:2187*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2187*FLEN/8, x3, x2, x7) + +inst_762: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x062 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3bc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b0f; op2val:0x3c62; +op3val:0x7bbc; valaddr_reg:x1; val_offset:2190*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2190*FLEN/8, x3, x2, x7) + +inst_763: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x062 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3bc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b0f; op2val:0x3c62; +op3val:0x7bbc; valaddr_reg:x1; val_offset:2193*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2193*FLEN/8, x3, x2, x7) + +inst_764: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x062 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3bc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b0f; op2val:0x3c62; +op3val:0x7bbc; valaddr_reg:x1; val_offset:2196*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2196*FLEN/8, x3, x2, x7) + +inst_765: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x306 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x056 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x39d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7306; op2val:0x4456; +op3val:0x7b9d; valaddr_reg:x1; val_offset:2199*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2199*FLEN/8, x3, x2, x7) + +inst_766: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x306 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x056 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x39d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7306; op2val:0x4456; +op3val:0x7b9d; valaddr_reg:x1; val_offset:2202*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2202*FLEN/8, x3, x2, x7) + +inst_767: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x306 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x056 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x39d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7306; op2val:0x4456; +op3val:0x7b9d; valaddr_reg:x1; val_offset:2205*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2205*FLEN/8, x3, x2, x7) + +inst_768: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x306 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x056 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x39d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7306; op2val:0x4456; +op3val:0x7b9d; valaddr_reg:x1; val_offset:2208*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2208*FLEN/8, x3, x2, x7) + +inst_769: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x306 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x056 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x39d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7306; op2val:0x4456; +op3val:0x7b9d; valaddr_reg:x1; val_offset:2211*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2211*FLEN/8, x3, x2, x7) + +inst_770: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x25e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0e4 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3ca and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x765e; op2val:0x3ce4; +op3val:0x77ca; valaddr_reg:x1; val_offset:2214*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2214*FLEN/8, x3, x2, x7) + +inst_771: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x25e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0e4 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3ca and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x765e; op2val:0x3ce4; +op3val:0x77ca; valaddr_reg:x1; val_offset:2217*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2217*FLEN/8, x3, x2, x7) + +inst_772: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x25e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0e4 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3ca and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x765e; op2val:0x3ce4; +op3val:0x77ca; valaddr_reg:x1; val_offset:2220*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2220*FLEN/8, x3, x2, x7) + +inst_773: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x25e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0e4 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3ca and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x765e; op2val:0x3ce4; +op3val:0x77ca; valaddr_reg:x1; val_offset:2223*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2223*FLEN/8, x3, x2, x7) + +inst_774: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x25e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0e4 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3ca and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x765e; op2val:0x3ce4; +op3val:0x77ca; valaddr_reg:x1; val_offset:2226*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2226*FLEN/8, x3, x2, x7) + +inst_775: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ea and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ba and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bea; op2val:0x3aba; +op3val:0x7aa8; valaddr_reg:x1; val_offset:2229*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2229*FLEN/8, x3, x2, x7) + +inst_776: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ea and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ba and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bea; op2val:0x3aba; +op3val:0x7aa8; valaddr_reg:x1; val_offset:2232*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2232*FLEN/8, x3, x2, x7) + +inst_777: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ea and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ba and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bea; op2val:0x3aba; +op3val:0x7aa8; valaddr_reg:x1; val_offset:2235*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2235*FLEN/8, x3, x2, x7) + +inst_778: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ea and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ba and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bea; op2val:0x3aba; +op3val:0x7aa8; valaddr_reg:x1; val_offset:2238*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2238*FLEN/8, x3, x2, x7) + +inst_779: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ea and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ba and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bea; op2val:0x3aba; +op3val:0x7aa8; valaddr_reg:x1; val_offset:2241*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2241*FLEN/8, x3, x2, x7) + +inst_780: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x12a and fs2 == 0 and fe2 == 0x10 and fm2 == 0x158 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2e6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x712a; op2val:0x4158; +op3val:0x76e6; valaddr_reg:x1; val_offset:2244*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2244*FLEN/8, x3, x2, x7) + +inst_781: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x12a and fs2 == 0 and fe2 == 0x10 and fm2 == 0x158 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2e6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x712a; op2val:0x4158; +op3val:0x76e6; valaddr_reg:x1; val_offset:2247*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2247*FLEN/8, x3, x2, x7) + +inst_782: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x12a and fs2 == 0 and fe2 == 0x10 and fm2 == 0x158 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2e6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x712a; op2val:0x4158; +op3val:0x76e6; valaddr_reg:x1; val_offset:2250*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2250*FLEN/8, x3, x2, x7) + +inst_783: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x12a and fs2 == 0 and fe2 == 0x10 and fm2 == 0x158 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2e6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x712a; op2val:0x4158; +op3val:0x76e6; valaddr_reg:x1; val_offset:2253*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2253*FLEN/8, x3, x2, x7) + +inst_784: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x12a and fs2 == 0 and fe2 == 0x10 and fm2 == 0x158 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2e6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x712a; op2val:0x4158; +op3val:0x76e6; valaddr_reg:x1; val_offset:2256*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2256*FLEN/8, x3, x2, x7) + +inst_785: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x01f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x143 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x16c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x781f; op2val:0x3943; +op3val:0x756c; valaddr_reg:x1; val_offset:2259*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2259*FLEN/8, x3, x2, x7) + +inst_786: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x01f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x143 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x16c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x781f; op2val:0x3943; +op3val:0x756c; valaddr_reg:x1; val_offset:2262*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2262*FLEN/8, x3, x2, x7) + +inst_787: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x01f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x143 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x16c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x781f; op2val:0x3943; +op3val:0x756c; valaddr_reg:x1; val_offset:2265*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2265*FLEN/8, x3, x2, x7) + +inst_788: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x01f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x143 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x16c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x781f; op2val:0x3943; +op3val:0x756c; valaddr_reg:x1; val_offset:2268*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2268*FLEN/8, x3, x2, x7) + +inst_789: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x01f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x143 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x16c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x781f; op2val:0x3943; +op3val:0x756c; valaddr_reg:x1; val_offset:2271*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2271*FLEN/8, x3, x2, x7) + +inst_790: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x242 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x282 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x118 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7242; op2val:0x3e82; +op3val:0x7518; valaddr_reg:x1; val_offset:2274*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2274*FLEN/8, x3, x2, x7) + +inst_791: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x242 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x282 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x118 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7242; op2val:0x3e82; +op3val:0x7518; valaddr_reg:x1; val_offset:2277*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2277*FLEN/8, x3, x2, x7) + +inst_792: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x242 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x282 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x118 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7242; op2val:0x3e82; +op3val:0x7518; valaddr_reg:x1; val_offset:2280*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2280*FLEN/8, x3, x2, x7) + +inst_793: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x242 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x282 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x118 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7242; op2val:0x3e82; +op3val:0x7518; valaddr_reg:x1; val_offset:2283*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2283*FLEN/8, x3, x2, x7) + +inst_794: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x242 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x282 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x118 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7242; op2val:0x3e82; +op3val:0x7518; valaddr_reg:x1; val_offset:2286*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2286*FLEN/8, x3, x2, x7) +RVTEST_SIGBASE(x2,signature_x2_6) + +inst_795: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c6 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x2e9 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x0fd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79c6; op2val:0x26e9; +op3val:0x64fd; valaddr_reg:x1; val_offset:2289*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2289*FLEN/8, x3, x2, x7) + +inst_796: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c6 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x2e9 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x0fd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79c6; op2val:0x26e9; +op3val:0x64fd; valaddr_reg:x1; val_offset:2292*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2292*FLEN/8, x3, x2, x7) + +inst_797: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c6 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x2e9 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x0fd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79c6; op2val:0x26e9; +op3val:0x64fd; valaddr_reg:x1; val_offset:2295*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2295*FLEN/8, x3, x2, x7) + +inst_798: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c6 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x2e9 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x0fd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79c6; op2val:0x26e9; +op3val:0x64fd; valaddr_reg:x1; val_offset:2298*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2298*FLEN/8, x3, x2, x7) + +inst_799: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c6 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x2e9 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x0fd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79c6; op2val:0x26e9; +op3val:0x64fd; valaddr_reg:x1; val_offset:2301*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2301*FLEN/8, x3, x2, x7) + +inst_800: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x06e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x25c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x30b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x786e; op2val:0x3a5c; +op3val:0x770b; valaddr_reg:x1; val_offset:2304*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2304*FLEN/8, x3, x2, x7) + +inst_801: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x06e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x25c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x30b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x786e; op2val:0x3a5c; +op3val:0x770b; valaddr_reg:x1; val_offset:2307*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2307*FLEN/8, x3, x2, x7) + +inst_802: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x06e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x25c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x30b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x786e; op2val:0x3a5c; +op3val:0x770b; valaddr_reg:x1; val_offset:2310*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2310*FLEN/8, x3, x2, x7) + +inst_803: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x06e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x25c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x30b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x786e; op2val:0x3a5c; +op3val:0x770b; valaddr_reg:x1; val_offset:2313*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2313*FLEN/8, x3, x2, x7) + +inst_804: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x06e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x25c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x30b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x786e; op2val:0x3a5c; +op3val:0x770b; valaddr_reg:x1; val_offset:2316*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2316*FLEN/8, x3, x2, x7) + +inst_805: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x0a1 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x094 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x14d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x64a1; op2val:0x4c94; +op3val:0x754d; valaddr_reg:x1; val_offset:2319*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2319*FLEN/8, x3, x2, x7) + +inst_806: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x0a1 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x094 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x14d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x64a1; op2val:0x4c94; +op3val:0x754d; valaddr_reg:x1; val_offset:2322*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2322*FLEN/8, x3, x2, x7) + +inst_807: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x0a1 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x094 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x14d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x64a1; op2val:0x4c94; +op3val:0x754d; valaddr_reg:x1; val_offset:2325*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2325*FLEN/8, x3, x2, x7) + +inst_808: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x0a1 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x094 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x14d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x64a1; op2val:0x4c94; +op3val:0x754d; valaddr_reg:x1; val_offset:2328*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2328*FLEN/8, x3, x2, x7) + +inst_809: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x0a1 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x094 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x14d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x64a1; op2val:0x4c94; +op3val:0x754d; valaddr_reg:x1; val_offset:2331*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2331*FLEN/8, x3, x2, x7) + +inst_810: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x291 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x018 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fd; op2val:0x3a91; +op3val:0x7818; valaddr_reg:x1; val_offset:2334*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2334*FLEN/8, x3, x2, x7) + +inst_811: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x291 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x018 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fd; op2val:0x3a91; +op3val:0x7818; valaddr_reg:x1; val_offset:2337*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2337*FLEN/8, x3, x2, x7) + +inst_812: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x291 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x018 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fd; op2val:0x3a91; +op3val:0x7818; valaddr_reg:x1; val_offset:2340*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2340*FLEN/8, x3, x2, x7) + +inst_813: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x291 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x018 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fd; op2val:0x3a91; +op3val:0x7818; valaddr_reg:x1; val_offset:2343*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2343*FLEN/8, x3, x2, x7) + +inst_814: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x291 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x018 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fd; op2val:0x3a91; +op3val:0x7818; valaddr_reg:x1; val_offset:2346*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2346*FLEN/8, x3, x2, x7) + +inst_815: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x01d and fs2 == 0 and fe2 == 0x12 and fm2 == 0x3a8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c1d; op2val:0x4ba8; +op3val:0x7be0; valaddr_reg:x1; val_offset:2349*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2349*FLEN/8, x3, x2, x7) + +inst_816: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x01d and fs2 == 0 and fe2 == 0x12 and fm2 == 0x3a8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3e0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c1d; op2val:0x4ba8; +op3val:0x7be0; valaddr_reg:x1; val_offset:2352*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2352*FLEN/8, x3, x2, x7) + +inst_817: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x01d and fs2 == 0 and fe2 == 0x12 and fm2 == 0x3a8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3e0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c1d; op2val:0x4ba8; +op3val:0x7be0; valaddr_reg:x1; val_offset:2355*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2355*FLEN/8, x3, x2, x7) + +inst_818: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x01d and fs2 == 0 and fe2 == 0x12 and fm2 == 0x3a8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3e0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c1d; op2val:0x4ba8; +op3val:0x7be0; valaddr_reg:x1; val_offset:2358*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2358*FLEN/8, x3, x2, x7) + +inst_819: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x01d and fs2 == 0 and fe2 == 0x12 and fm2 == 0x3a8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3e0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c1d; op2val:0x4ba8; +op3val:0x7be0; valaddr_reg:x1; val_offset:2361*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2361*FLEN/8, x3, x2, x7) + +inst_820: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x24d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ee and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3c5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a4d; op2val:0x3cee; +op3val:0x7bc5; valaddr_reg:x1; val_offset:2364*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2364*FLEN/8, x3, x2, x7) + +inst_821: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x24d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ee and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3c5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a4d; op2val:0x3cee; +op3val:0x7bc5; valaddr_reg:x1; val_offset:2367*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2367*FLEN/8, x3, x2, x7) + +inst_822: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x24d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ee and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3c5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a4d; op2val:0x3cee; +op3val:0x7bc5; valaddr_reg:x1; val_offset:2370*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2370*FLEN/8, x3, x2, x7) + +inst_823: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x24d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ee and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3c5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a4d; op2val:0x3cee; +op3val:0x7bc5; valaddr_reg:x1; val_offset:2373*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2373*FLEN/8, x3, x2, x7) + +inst_824: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x24d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ee and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3c5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a4d; op2val:0x3cee; +op3val:0x7bc5; valaddr_reg:x1; val_offset:2376*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2376*FLEN/8, x3, x2, x7) + +inst_825: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2b4 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x111 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6eb4; op2val:0x4111; +op3val:0x743f; valaddr_reg:x1; val_offset:2379*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2379*FLEN/8, x3, x2, x7) + +inst_826: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2b4 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x111 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x03f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6eb4; op2val:0x4111; +op3val:0x743f; valaddr_reg:x1; val_offset:2382*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2382*FLEN/8, x3, x2, x7) + +inst_827: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2b4 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x111 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x03f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6eb4; op2val:0x4111; +op3val:0x743f; valaddr_reg:x1; val_offset:2385*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2385*FLEN/8, x3, x2, x7) + +inst_828: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2b4 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x111 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x03f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6eb4; op2val:0x4111; +op3val:0x743f; valaddr_reg:x1; val_offset:2388*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2388*FLEN/8, x3, x2, x7) + +inst_829: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2b4 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x111 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x03f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6eb4; op2val:0x4111; +op3val:0x743f; valaddr_reg:x1; val_offset:2391*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2391*FLEN/8, x3, x2, x7) + +inst_830: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x111 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x0ea and fs3 == 0 and fe3 == 0x1e and fm3 == 0x23a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6911; op2val:0x4cea; +op3val:0x7a3a; valaddr_reg:x1; val_offset:2394*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2394*FLEN/8, x3, x2, x7) + +inst_831: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x111 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x0ea and fs3 == 0 and fe3 == 0x1e and fm3 == 0x23a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6911; op2val:0x4cea; +op3val:0x7a3a; valaddr_reg:x1; val_offset:2397*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2397*FLEN/8, x3, x2, x7) + +inst_832: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x111 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x0ea and fs3 == 0 and fe3 == 0x1e and fm3 == 0x23a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6911; op2val:0x4cea; +op3val:0x7a3a; valaddr_reg:x1; val_offset:2400*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2400*FLEN/8, x3, x2, x7) + +inst_833: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x111 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x0ea and fs3 == 0 and fe3 == 0x1e and fm3 == 0x23a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6911; op2val:0x4cea; +op3val:0x7a3a; valaddr_reg:x1; val_offset:2403*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2403*FLEN/8, x3, x2, x7) + +inst_834: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x111 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x0ea and fs3 == 0 and fe3 == 0x1e and fm3 == 0x23a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6911; op2val:0x4cea; +op3val:0x7a3a; valaddr_reg:x1; val_offset:2406*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2406*FLEN/8, x3, x2, x7) + +inst_835: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x053 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3aa and fs3 == 0 and fe3 == 0x1c and fm3 == 0x024 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7453; op2val:0x37aa; +op3val:0x7024; valaddr_reg:x1; val_offset:2409*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2409*FLEN/8, x3, x2, x7) + +inst_836: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x053 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3aa and fs3 == 0 and fe3 == 0x1c and fm3 == 0x024 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7453; op2val:0x37aa; +op3val:0x7024; valaddr_reg:x1; val_offset:2412*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2412*FLEN/8, x3, x2, x7) + +inst_837: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x053 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3aa and fs3 == 0 and fe3 == 0x1c and fm3 == 0x024 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7453; op2val:0x37aa; +op3val:0x7024; valaddr_reg:x1; val_offset:2415*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2415*FLEN/8, x3, x2, x7) + +inst_838: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x053 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3aa and fs3 == 0 and fe3 == 0x1c and fm3 == 0x024 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7453; op2val:0x37aa; +op3val:0x7024; valaddr_reg:x1; val_offset:2418*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2418*FLEN/8, x3, x2, x7) + +inst_839: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x053 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3aa and fs3 == 0 and fe3 == 0x1c and fm3 == 0x024 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7453; op2val:0x37aa; +op3val:0x7024; valaddr_reg:x1; val_offset:2421*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2421*FLEN/8, x3, x2, x7) + +inst_840: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x052 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x349 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76c0; op2val:0x4052; +op3val:0x7b49; valaddr_reg:x1; val_offset:2424*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2424*FLEN/8, x3, x2, x7) + +inst_841: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x052 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x349 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76c0; op2val:0x4052; +op3val:0x7b49; valaddr_reg:x1; val_offset:2427*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2427*FLEN/8, x3, x2, x7) + +inst_842: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x052 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x349 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76c0; op2val:0x4052; +op3val:0x7b49; valaddr_reg:x1; val_offset:2430*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2430*FLEN/8, x3, x2, x7) + +inst_843: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x052 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x349 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76c0; op2val:0x4052; +op3val:0x7b49; valaddr_reg:x1; val_offset:2433*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2433*FLEN/8, x3, x2, x7) + +inst_844: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x052 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x349 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76c0; op2val:0x4052; +op3val:0x7b49; valaddr_reg:x1; val_offset:2436*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2436*FLEN/8, x3, x2, x7) + +inst_845: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28c and fs2 == 0 and fe2 == 0x0d and fm2 == 0x112 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x022 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8c; op2val:0x3512; +op3val:0x7422; valaddr_reg:x1; val_offset:2439*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2439*FLEN/8, x3, x2, x7) + +inst_846: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28c and fs2 == 0 and fe2 == 0x0d and fm2 == 0x112 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x022 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8c; op2val:0x3512; +op3val:0x7422; valaddr_reg:x1; val_offset:2442*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2442*FLEN/8, x3, x2, x7) + +inst_847: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28c and fs2 == 0 and fe2 == 0x0d and fm2 == 0x112 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x022 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8c; op2val:0x3512; +op3val:0x7422; valaddr_reg:x1; val_offset:2445*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2445*FLEN/8, x3, x2, x7) + +inst_848: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28c and fs2 == 0 and fe2 == 0x0d and fm2 == 0x112 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x022 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8c; op2val:0x3512; +op3val:0x7422; valaddr_reg:x1; val_offset:2448*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2448*FLEN/8, x3, x2, x7) + +inst_849: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28c and fs2 == 0 and fe2 == 0x0d and fm2 == 0x112 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x022 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8c; op2val:0x3512; +op3val:0x7422; valaddr_reg:x1; val_offset:2451*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2451*FLEN/8, x3, x2, x7) + +inst_850: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0c7 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x228 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x359 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70c7; op2val:0x4628; +op3val:0x7b59; valaddr_reg:x1; val_offset:2454*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2454*FLEN/8, x3, x2, x7) + +inst_851: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0c7 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x228 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x359 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70c7; op2val:0x4628; +op3val:0x7b59; valaddr_reg:x1; val_offset:2457*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2457*FLEN/8, x3, x2, x7) + +inst_852: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0c7 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x228 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x359 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70c7; op2val:0x4628; +op3val:0x7b59; valaddr_reg:x1; val_offset:2460*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2460*FLEN/8, x3, x2, x7) + +inst_853: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0c7 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x228 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x359 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70c7; op2val:0x4628; +op3val:0x7b59; valaddr_reg:x1; val_offset:2463*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2463*FLEN/8, x3, x2, x7) + +inst_854: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0c7 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x228 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x359 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70c7; op2val:0x4628; +op3val:0x7b59; valaddr_reg:x1; val_offset:2466*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2466*FLEN/8, x3, x2, x7) + +inst_855: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x090 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ea and fs3 == 0 and fe3 == 0x1e and fm3 == 0x199 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7890; op2val:0x3cea; +op3val:0x7999; valaddr_reg:x1; val_offset:2469*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2469*FLEN/8, x3, x2, x7) + +inst_856: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x090 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ea and fs3 == 0 and fe3 == 0x1e and fm3 == 0x199 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7890; op2val:0x3cea; +op3val:0x7999; valaddr_reg:x1; val_offset:2472*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2472*FLEN/8, x3, x2, x7) + +inst_857: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x090 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ea and fs3 == 0 and fe3 == 0x1e and fm3 == 0x199 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7890; op2val:0x3cea; +op3val:0x7999; valaddr_reg:x1; val_offset:2475*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2475*FLEN/8, x3, x2, x7) + +inst_858: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x090 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ea and fs3 == 0 and fe3 == 0x1e and fm3 == 0x199 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7890; op2val:0x3cea; +op3val:0x7999; valaddr_reg:x1; val_offset:2478*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2478*FLEN/8, x3, x2, x7) + +inst_859: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x090 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ea and fs3 == 0 and fe3 == 0x1e and fm3 == 0x199 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7890; op2val:0x3cea; +op3val:0x7999; valaddr_reg:x1; val_offset:2481*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2481*FLEN/8, x3, x2, x7) + +inst_860: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1b9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x13b and fs3 == 0 and fe3 == 0x1a and fm3 == 0x35c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6db9; op2val:0x393b; +op3val:0x6b5c; valaddr_reg:x1; val_offset:2484*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2484*FLEN/8, x3, x2, x7) + +inst_861: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1b9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x13b and fs3 == 0 and fe3 == 0x1a and fm3 == 0x35c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6db9; op2val:0x393b; +op3val:0x6b5c; valaddr_reg:x1; val_offset:2487*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2487*FLEN/8, x3, x2, x7) + +inst_862: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1b9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x13b and fs3 == 0 and fe3 == 0x1a and fm3 == 0x35c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6db9; op2val:0x393b; +op3val:0x6b5c; valaddr_reg:x1; val_offset:2490*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2490*FLEN/8, x3, x2, x7) + +inst_863: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1b9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x13b and fs3 == 0 and fe3 == 0x1a and fm3 == 0x35c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6db9; op2val:0x393b; +op3val:0x6b5c; valaddr_reg:x1; val_offset:2493*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2493*FLEN/8, x3, x2, x7) + +inst_864: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1b9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x13b and fs3 == 0 and fe3 == 0x1a and fm3 == 0x35c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6db9; op2val:0x393b; +op3val:0x6b5c; valaddr_reg:x1; val_offset:2496*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2496*FLEN/8, x3, x2, x7) + +inst_865: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x180 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0f4 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2cd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7980; op2val:0x38f4; +op3val:0x76cd; valaddr_reg:x1; val_offset:2499*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2499*FLEN/8, x3, x2, x7) + +inst_866: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x180 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0f4 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2cd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7980; op2val:0x38f4; +op3val:0x76cd; valaddr_reg:x1; val_offset:2502*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2502*FLEN/8, x3, x2, x7) + +inst_867: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x180 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0f4 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2cd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7980; op2val:0x38f4; +op3val:0x76cd; valaddr_reg:x1; val_offset:2505*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2505*FLEN/8, x3, x2, x7) + +inst_868: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x180 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0f4 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2cd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7980; op2val:0x38f4; +op3val:0x76cd; valaddr_reg:x1; val_offset:2508*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2508*FLEN/8, x3, x2, x7) + +inst_869: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x180 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0f4 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2cd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7980; op2val:0x38f4; +op3val:0x76cd; valaddr_reg:x1; val_offset:2511*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2511*FLEN/8, x3, x2, x7) + +inst_870: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0a2 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x27c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ca2; op2val:0x4a7c; +op3val:0x7b80; valaddr_reg:x1; val_offset:2514*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2514*FLEN/8, x3, x2, x7) + +inst_871: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0a2 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x27c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x380 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ca2; op2val:0x4a7c; +op3val:0x7b80; valaddr_reg:x1; val_offset:2517*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2517*FLEN/8, x3, x2, x7) + +inst_872: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0a2 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x27c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x380 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ca2; op2val:0x4a7c; +op3val:0x7b80; valaddr_reg:x1; val_offset:2520*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2520*FLEN/8, x3, x2, x7) + +inst_873: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0a2 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x27c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x380 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ca2; op2val:0x4a7c; +op3val:0x7b80; valaddr_reg:x1; val_offset:2523*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2523*FLEN/8, x3, x2, x7) + +inst_874: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0a2 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x27c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x380 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ca2; op2val:0x4a7c; +op3val:0x7b80; valaddr_reg:x1; val_offset:2526*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2526*FLEN/8, x3, x2, x7) + +inst_875: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x112 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x10c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x268 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7912; op2val:0x3d0c; +op3val:0x7a68; valaddr_reg:x1; val_offset:2529*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2529*FLEN/8, x3, x2, x7) + +inst_876: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x112 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x10c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x268 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7912; op2val:0x3d0c; +op3val:0x7a68; valaddr_reg:x1; val_offset:2532*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2532*FLEN/8, x3, x2, x7) + +inst_877: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x112 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x10c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x268 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7912; op2val:0x3d0c; +op3val:0x7a68; valaddr_reg:x1; val_offset:2535*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2535*FLEN/8, x3, x2, x7) + +inst_878: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x112 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x10c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x268 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7912; op2val:0x3d0c; +op3val:0x7a68; valaddr_reg:x1; val_offset:2538*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2538*FLEN/8, x3, x2, x7) + +inst_879: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x112 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x10c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x268 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7912; op2val:0x3d0c; +op3val:0x7a68; valaddr_reg:x1; val_offset:2541*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2541*FLEN/8, x3, x2, x7) + +inst_880: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x15b and fs2 == 0 and fe2 == 0x12 and fm2 == 0x11b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2d8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d5b; op2val:0x491b; +op3val:0x7ad8; valaddr_reg:x1; val_offset:2544*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2544*FLEN/8, x3, x2, x7) + +inst_881: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x15b and fs2 == 0 and fe2 == 0x12 and fm2 == 0x11b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2d8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d5b; op2val:0x491b; +op3val:0x7ad8; valaddr_reg:x1; val_offset:2547*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2547*FLEN/8, x3, x2, x7) + +inst_882: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x15b and fs2 == 0 and fe2 == 0x12 and fm2 == 0x11b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2d8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d5b; op2val:0x491b; +op3val:0x7ad8; valaddr_reg:x1; val_offset:2550*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2550*FLEN/8, x3, x2, x7) + +inst_883: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x15b and fs2 == 0 and fe2 == 0x12 and fm2 == 0x11b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2d8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d5b; op2val:0x491b; +op3val:0x7ad8; valaddr_reg:x1; val_offset:2553*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2553*FLEN/8, x3, x2, x7) + +inst_884: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x15b and fs2 == 0 and fe2 == 0x12 and fm2 == 0x11b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2d8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d5b; op2val:0x491b; +op3val:0x7ad8; valaddr_reg:x1; val_offset:2556*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2556*FLEN/8, x3, x2, x7) + +inst_885: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x043 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x277 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2e6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c43; op2val:0x4a77; +op3val:0x7ae6; valaddr_reg:x1; val_offset:2559*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2559*FLEN/8, x3, x2, x7) + +inst_886: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x043 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x277 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2e6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c43; op2val:0x4a77; +op3val:0x7ae6; valaddr_reg:x1; val_offset:2562*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2562*FLEN/8, x3, x2, x7) + +inst_887: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x043 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x277 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2e6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c43; op2val:0x4a77; +op3val:0x7ae6; valaddr_reg:x1; val_offset:2565*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2565*FLEN/8, x3, x2, x7) + +inst_888: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x043 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x277 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2e6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c43; op2val:0x4a77; +op3val:0x7ae6; valaddr_reg:x1; val_offset:2568*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2568*FLEN/8, x3, x2, x7) + +inst_889: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x043 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x277 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2e6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c43; op2val:0x4a77; +op3val:0x7ae6; valaddr_reg:x1; val_offset:2571*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2571*FLEN/8, x3, x2, x7) + +inst_890: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x341 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1f6 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x16c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7741; op2val:0x39f6; +op3val:0x756c; valaddr_reg:x1; val_offset:2574*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2574*FLEN/8, x3, x2, x7) + +inst_891: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x341 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1f6 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x16c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7741; op2val:0x39f6; +op3val:0x756c; valaddr_reg:x1; val_offset:2577*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2577*FLEN/8, x3, x2, x7) + +inst_892: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x341 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1f6 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x16c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7741; op2val:0x39f6; +op3val:0x756c; valaddr_reg:x1; val_offset:2580*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2580*FLEN/8, x3, x2, x7) + +inst_893: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x341 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1f6 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x16c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7741; op2val:0x39f6; +op3val:0x756c; valaddr_reg:x1; val_offset:2583*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2583*FLEN/8, x3, x2, x7) + +inst_894: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x341 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1f6 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x16c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7741; op2val:0x39f6; +op3val:0x756c; valaddr_reg:x1; val_offset:2586*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2586*FLEN/8, x3, x2, x7) + +inst_895: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x06c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2b1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x368 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x786c; op2val:0x3eb1; +op3val:0x7b68; valaddr_reg:x1; val_offset:2589*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2589*FLEN/8, x3, x2, x7) + +inst_896: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x06c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2b1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x368 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x786c; op2val:0x3eb1; +op3val:0x7b68; valaddr_reg:x1; val_offset:2592*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2592*FLEN/8, x3, x2, x7) + +inst_897: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x06c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2b1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x368 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x786c; op2val:0x3eb1; +op3val:0x7b68; valaddr_reg:x1; val_offset:2595*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2595*FLEN/8, x3, x2, x7) + +inst_898: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x06c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2b1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x368 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x786c; op2val:0x3eb1; +op3val:0x7b68; valaddr_reg:x1; val_offset:2598*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2598*FLEN/8, x3, x2, x7) + +inst_899: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x06c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2b1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x368 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x786c; op2val:0x3eb1; +op3val:0x7b68; valaddr_reg:x1; val_offset:2601*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2601*FLEN/8, x3, x2, x7) + +inst_900: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x048 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3a9 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x022 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7448; op2val:0x37a9; +op3val:0x7022; valaddr_reg:x1; val_offset:2604*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2604*FLEN/8, x3, x2, x7) + +inst_901: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x048 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3a9 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x022 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7448; op2val:0x37a9; +op3val:0x7022; valaddr_reg:x1; val_offset:2607*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2607*FLEN/8, x3, x2, x7) + +inst_902: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x048 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3a9 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x022 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7448; op2val:0x37a9; +op3val:0x7022; valaddr_reg:x1; val_offset:2610*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2610*FLEN/8, x3, x2, x7) + +inst_903: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x048 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3a9 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x022 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7448; op2val:0x37a9; +op3val:0x7022; valaddr_reg:x1; val_offset:2613*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2613*FLEN/8, x3, x2, x7) + +inst_904: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x048 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3a9 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x022 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7448; op2val:0x37a9; +op3val:0x7022; valaddr_reg:x1; val_offset:2616*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2616*FLEN/8, x3, x2, x7) + +inst_905: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x036 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x335 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3a0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7836; op2val:0x3735; +op3val:0x73a0; valaddr_reg:x1; val_offset:2619*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2619*FLEN/8, x3, x2, x7) + +inst_906: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x036 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x335 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3a0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7836; op2val:0x3735; +op3val:0x73a0; valaddr_reg:x1; val_offset:2622*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2622*FLEN/8, x3, x2, x7) + +inst_907: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x036 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x335 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3a0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7836; op2val:0x3735; +op3val:0x73a0; valaddr_reg:x1; val_offset:2625*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2625*FLEN/8, x3, x2, x7) + +inst_908: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x036 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x335 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3a0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7836; op2val:0x3735; +op3val:0x73a0; valaddr_reg:x1; val_offset:2628*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2628*FLEN/8, x3, x2, x7) + +inst_909: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x036 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x335 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3a0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7836; op2val:0x3735; +op3val:0x73a0; valaddr_reg:x1; val_offset:2631*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2631*FLEN/8, x3, x2, x7) + +inst_910: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x300 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1dd and fs3 == 0 and fe3 == 0x1c and fm3 == 0x12a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f00; op2val:0x3ddd; +op3val:0x712a; valaddr_reg:x1; val_offset:2634*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2634*FLEN/8, x3, x2, x7) + +inst_911: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x300 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1dd and fs3 == 0 and fe3 == 0x1c and fm3 == 0x12a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f00; op2val:0x3ddd; +op3val:0x712a; valaddr_reg:x1; val_offset:2637*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2637*FLEN/8, x3, x2, x7) + +inst_912: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x300 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1dd and fs3 == 0 and fe3 == 0x1c and fm3 == 0x12a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f00; op2val:0x3ddd; +op3val:0x712a; valaddr_reg:x1; val_offset:2640*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2640*FLEN/8, x3, x2, x7) + +inst_913: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x300 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1dd and fs3 == 0 and fe3 == 0x1c and fm3 == 0x12a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f00; op2val:0x3ddd; +op3val:0x712a; valaddr_reg:x1; val_offset:2643*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2643*FLEN/8, x3, x2, x7) + +inst_914: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x300 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1dd and fs3 == 0 and fe3 == 0x1c and fm3 == 0x12a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f00; op2val:0x3ddd; +op3val:0x712a; valaddr_reg:x1; val_offset:2646*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2646*FLEN/8, x3, x2, x7) + +inst_915: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x272 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3f8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x274 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6a72; op2val:0x43f8; +op3val:0x7274; valaddr_reg:x1; val_offset:2649*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2649*FLEN/8, x3, x2, x7) + +inst_916: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x272 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3f8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x274 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6a72; op2val:0x43f8; +op3val:0x7274; valaddr_reg:x1; val_offset:2652*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2652*FLEN/8, x3, x2, x7) + +inst_917: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x272 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3f8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x274 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6a72; op2val:0x43f8; +op3val:0x7274; valaddr_reg:x1; val_offset:2655*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2655*FLEN/8, x3, x2, x7) + +inst_918: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x272 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3f8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x274 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6a72; op2val:0x43f8; +op3val:0x7274; valaddr_reg:x1; val_offset:2658*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2658*FLEN/8, x3, x2, x7) + +inst_919: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x272 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3f8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x274 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6a72; op2val:0x43f8; +op3val:0x7274; valaddr_reg:x1; val_offset:2661*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2661*FLEN/8, x3, x2, x7) + +inst_920: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0fd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3cb and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74fd; op2val:0x3bcb; +op3val:0x74e0; valaddr_reg:x1; val_offset:2664*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2664*FLEN/8, x3, x2, x7) + +inst_921: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0fd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3cb and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0e0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74fd; op2val:0x3bcb; +op3val:0x74e0; valaddr_reg:x1; val_offset:2667*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2667*FLEN/8, x3, x2, x7) + +inst_922: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0fd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3cb and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0e0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74fd; op2val:0x3bcb; +op3val:0x74e0; valaddr_reg:x1; val_offset:2670*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2670*FLEN/8, x3, x2, x7) +RVTEST_SIGBASE(x2,signature_x2_7) + +inst_923: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0fd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3cb and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0e0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74fd; op2val:0x3bcb; +op3val:0x74e0; valaddr_reg:x1; val_offset:2673*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2673*FLEN/8, x3, x2, x7) + +inst_924: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0fd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3cb and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0e0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74fd; op2val:0x3bcb; +op3val:0x74e0; valaddr_reg:x1; val_offset:2676*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2676*FLEN/8, x3, x2, x7) + +inst_925: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x212 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x216 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a12; op2val:0x3616; +op3val:0x74a3; valaddr_reg:x1; val_offset:2679*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2679*FLEN/8, x3, x2, x7) + +inst_926: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x212 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x216 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a12; op2val:0x3616; +op3val:0x74a3; valaddr_reg:x1; val_offset:2682*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2682*FLEN/8, x3, x2, x7) + +inst_927: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x212 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x216 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a12; op2val:0x3616; +op3val:0x74a3; valaddr_reg:x1; val_offset:2685*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2685*FLEN/8, x3, x2, x7) + +inst_928: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x212 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x216 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a12; op2val:0x3616; +op3val:0x74a3; valaddr_reg:x1; val_offset:2688*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2688*FLEN/8, x3, x2, x7) + +inst_929: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x212 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x216 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a12; op2val:0x3616; +op3val:0x74a3; valaddr_reg:x1; val_offset:2691*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2691*FLEN/8, x3, x2, x7) + +inst_930: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1a9 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x1b0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77ff; op2val:0x35a9; +op3val:0x71b0; valaddr_reg:x1; val_offset:2694*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2694*FLEN/8, x3, x2, x7) + +inst_931: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1a9 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x1b0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77ff; op2val:0x35a9; +op3val:0x71b0; valaddr_reg:x1; val_offset:2697*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2697*FLEN/8, x3, x2, x7) + +inst_932: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1a9 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x1b0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77ff; op2val:0x35a9; +op3val:0x71b0; valaddr_reg:x1; val_offset:2700*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2700*FLEN/8, x3, x2, x7) + +inst_933: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1a9 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x1b0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77ff; op2val:0x35a9; +op3val:0x71b0; valaddr_reg:x1; val_offset:2703*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2703*FLEN/8, x3, x2, x7) + +inst_934: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1a9 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x1b0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77ff; op2val:0x35a9; +op3val:0x71b0; valaddr_reg:x1; val_offset:2706*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2706*FLEN/8, x3, x2, x7) + +inst_935: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x18c and fs2 == 0 and fe2 == 0x0a and fm2 == 0x258 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x0a6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x758c; op2val:0x2a58; +op3val:0x64a6; valaddr_reg:x1; val_offset:2709*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2709*FLEN/8, x3, x2, x7) + +inst_936: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x18c and fs2 == 0 and fe2 == 0x0a and fm2 == 0x258 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x0a6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x758c; op2val:0x2a58; +op3val:0x64a6; valaddr_reg:x1; val_offset:2712*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2712*FLEN/8, x3, x2, x7) + +inst_937: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x18c and fs2 == 0 and fe2 == 0x0a and fm2 == 0x258 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x0a6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x758c; op2val:0x2a58; +op3val:0x64a6; valaddr_reg:x1; val_offset:2715*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2715*FLEN/8, x3, x2, x7) + +inst_938: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x18c and fs2 == 0 and fe2 == 0x0a and fm2 == 0x258 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x0a6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x758c; op2val:0x2a58; +op3val:0x64a6; valaddr_reg:x1; val_offset:2718*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2718*FLEN/8, x3, x2, x7) + +inst_939: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x18c and fs2 == 0 and fe2 == 0x0a and fm2 == 0x258 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x0a6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x758c; op2val:0x2a58; +op3val:0x64a6; valaddr_reg:x1; val_offset:2721*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2721*FLEN/8, x3, x2, x7) + +inst_940: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x359 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x3dc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7401; op2val:0x2b59; +op3val:0x63dc; valaddr_reg:x1; val_offset:2724*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2724*FLEN/8, x3, x2, x7) + +inst_941: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x359 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x3dc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7401; op2val:0x2b59; +op3val:0x63dc; valaddr_reg:x1; val_offset:2727*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2727*FLEN/8, x3, x2, x7) + +inst_942: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x359 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x3dc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7401; op2val:0x2b59; +op3val:0x63dc; valaddr_reg:x1; val_offset:2730*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2730*FLEN/8, x3, x2, x7) + +inst_943: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x359 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x3dc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7401; op2val:0x2b59; +op3val:0x63dc; valaddr_reg:x1; val_offset:2733*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2733*FLEN/8, x3, x2, x7) + +inst_944: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x359 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x3dc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7401; op2val:0x2b59; +op3val:0x63dc; valaddr_reg:x1; val_offset:2736*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2736*FLEN/8, x3, x2, x7) + +inst_945: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1dc and fs2 == 0 and fe2 == 0x0e and fm2 == 0x206 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x068 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79dc; op2val:0x3a06; +op3val:0x7868; valaddr_reg:x1; val_offset:2739*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2739*FLEN/8, x3, x2, x7) + +inst_946: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1dc and fs2 == 0 and fe2 == 0x0e and fm2 == 0x206 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x068 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79dc; op2val:0x3a06; +op3val:0x7868; valaddr_reg:x1; val_offset:2742*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2742*FLEN/8, x3, x2, x7) + +inst_947: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1dc and fs2 == 0 and fe2 == 0x0e and fm2 == 0x206 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x068 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79dc; op2val:0x3a06; +op3val:0x7868; valaddr_reg:x1; val_offset:2745*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2745*FLEN/8, x3, x2, x7) + +inst_948: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1dc and fs2 == 0 and fe2 == 0x0e and fm2 == 0x206 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x068 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79dc; op2val:0x3a06; +op3val:0x7868; valaddr_reg:x1; val_offset:2748*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2748*FLEN/8, x3, x2, x7) + +inst_949: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1dc and fs2 == 0 and fe2 == 0x0e and fm2 == 0x206 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x068 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79dc; op2val:0x3a06; +op3val:0x7868; valaddr_reg:x1; val_offset:2751*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2751*FLEN/8, x3, x2, x7) + +inst_950: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x20f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x105 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x397 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x720f; op2val:0x4105; +op3val:0x7797; valaddr_reg:x1; val_offset:2754*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2754*FLEN/8, x3, x2, x7) + +inst_951: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x20f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x105 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x397 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x720f; op2val:0x4105; +op3val:0x7797; valaddr_reg:x1; val_offset:2757*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2757*FLEN/8, x3, x2, x7) + +inst_952: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x20f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x105 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x397 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x720f; op2val:0x4105; +op3val:0x7797; valaddr_reg:x1; val_offset:2760*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2760*FLEN/8, x3, x2, x7) + +inst_953: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x20f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x105 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x397 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x720f; op2val:0x4105; +op3val:0x7797; valaddr_reg:x1; val_offset:2763*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2763*FLEN/8, x3, x2, x7) + +inst_954: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x20f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x105 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x397 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x720f; op2val:0x4105; +op3val:0x7797; valaddr_reg:x1; val_offset:2766*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2766*FLEN/8, x3, x2, x7) + +inst_955: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x379 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x358 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x2cc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b79; op2val:0x2f58; +op3val:0x6ecc; valaddr_reg:x1; val_offset:2769*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2769*FLEN/8, x3, x2, x7) + +inst_956: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x379 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x358 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x2cc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b79; op2val:0x2f58; +op3val:0x6ecc; valaddr_reg:x1; val_offset:2772*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2772*FLEN/8, x3, x2, x7) + +inst_957: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x379 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x358 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x2cc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b79; op2val:0x2f58; +op3val:0x6ecc; valaddr_reg:x1; val_offset:2775*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2775*FLEN/8, x3, x2, x7) + +inst_958: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x379 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x358 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x2cc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b79; op2val:0x2f58; +op3val:0x6ecc; valaddr_reg:x1; val_offset:2778*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2778*FLEN/8, x3, x2, x7) + +inst_959: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x379 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x358 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x2cc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b79; op2val:0x2f58; +op3val:0x6ecc; valaddr_reg:x1; val_offset:2781*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2781*FLEN/8, x3, x2, x7) + +inst_960: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x03b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2e9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8c; op2val:0x383b; +op3val:0x76e9; valaddr_reg:x1; val_offset:2784*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2784*FLEN/8, x3, x2, x7) + +inst_961: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x03b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2e9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8c; op2val:0x383b; +op3val:0x76e9; valaddr_reg:x1; val_offset:2787*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2787*FLEN/8, x3, x2, x7) + +inst_962: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x03b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2e9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8c; op2val:0x383b; +op3val:0x76e9; valaddr_reg:x1; val_offset:2790*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2790*FLEN/8, x3, x2, x7) + +inst_963: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x03b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2e9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8c; op2val:0x383b; +op3val:0x76e9; valaddr_reg:x1; val_offset:2793*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2793*FLEN/8, x3, x2, x7) + +inst_964: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x03b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2e9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8c; op2val:0x383b; +op3val:0x76e9; valaddr_reg:x1; val_offset:2796*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2796*FLEN/8, x3, x2, x7) + +inst_965: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ea and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2c0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ac and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77ea; op2val:0x3ec0; +op3val:0x7aac; valaddr_reg:x1; val_offset:2799*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2799*FLEN/8, x3, x2, x7) + +inst_966: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ea and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2c0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ac and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77ea; op2val:0x3ec0; +op3val:0x7aac; valaddr_reg:x1; val_offset:2802*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2802*FLEN/8, x3, x2, x7) + +inst_967: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ea and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2c0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ac and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77ea; op2val:0x3ec0; +op3val:0x7aac; valaddr_reg:x1; val_offset:2805*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2805*FLEN/8, x3, x2, x7) + +inst_968: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ea and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2c0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ac and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77ea; op2val:0x3ec0; +op3val:0x7aac; valaddr_reg:x1; val_offset:2808*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2808*FLEN/8, x3, x2, x7) + +inst_969: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ea and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2c0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ac and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77ea; op2val:0x3ec0; +op3val:0x7aac; valaddr_reg:x1; val_offset:2811*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2811*FLEN/8, x3, x2, x7) + +inst_970: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x249 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x12a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7649; op2val:0x3d2a; +op3val:0x780d; valaddr_reg:x1; val_offset:2814*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2814*FLEN/8, x3, x2, x7) + +inst_971: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x249 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x12a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7649; op2val:0x3d2a; +op3val:0x780d; valaddr_reg:x1; val_offset:2817*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2817*FLEN/8, x3, x2, x7) + +inst_972: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x249 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x12a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7649; op2val:0x3d2a; +op3val:0x780d; valaddr_reg:x1; val_offset:2820*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2820*FLEN/8, x3, x2, x7) + +inst_973: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x249 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x12a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7649; op2val:0x3d2a; +op3val:0x780d; valaddr_reg:x1; val_offset:2823*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2823*FLEN/8, x3, x2, x7) + +inst_974: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x249 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x12a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7649; op2val:0x3d2a; +op3val:0x780d; valaddr_reg:x1; val_offset:2826*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2826*FLEN/8, x3, x2, x7) + +inst_975: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x17f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1b8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3db and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x797f; op2val:0x3db8; +op3val:0x7bdb; valaddr_reg:x1; val_offset:2829*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2829*FLEN/8, x3, x2, x7) + +inst_976: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x17f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1b8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3db and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x797f; op2val:0x3db8; +op3val:0x7bdb; valaddr_reg:x1; val_offset:2832*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2832*FLEN/8, x3, x2, x7) + +inst_977: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x17f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1b8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3db and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x797f; op2val:0x3db8; +op3val:0x7bdb; valaddr_reg:x1; val_offset:2835*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2835*FLEN/8, x3, x2, x7) + +inst_978: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x17f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1b8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3db and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x797f; op2val:0x3db8; +op3val:0x7bdb; valaddr_reg:x1; val_offset:2838*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2838*FLEN/8, x3, x2, x7) + +inst_979: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x17f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1b8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3db and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x797f; op2val:0x3db8; +op3val:0x7bdb; valaddr_reg:x1; val_offset:2841*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2841*FLEN/8, x3, x2, x7) + +inst_980: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x17b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0db and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x757b; op2val:0x40db; +op3val:0x7aa7; valaddr_reg:x1; val_offset:2844*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2844*FLEN/8, x3, x2, x7) + +inst_981: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x17b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0db and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x757b; op2val:0x40db; +op3val:0x7aa7; valaddr_reg:x1; val_offset:2847*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2847*FLEN/8, x3, x2, x7) + +inst_982: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x17b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0db and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x757b; op2val:0x40db; +op3val:0x7aa7; valaddr_reg:x1; val_offset:2850*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2850*FLEN/8, x3, x2, x7) + +inst_983: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x17b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0db and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x757b; op2val:0x40db; +op3val:0x7aa7; valaddr_reg:x1; val_offset:2853*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2853*FLEN/8, x3, x2, x7) + +inst_984: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x17b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0db and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x757b; op2val:0x40db; +op3val:0x7aa7; valaddr_reg:x1; val_offset:2856*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2856*FLEN/8, x3, x2, x7) + +inst_985: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x332 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x115 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79a6; op2val:0x3b32; +op3val:0x7915; valaddr_reg:x1; val_offset:2859*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2859*FLEN/8, x3, x2, x7) + +inst_986: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x332 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x115 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79a6; op2val:0x3b32; +op3val:0x7915; valaddr_reg:x1; val_offset:2862*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2862*FLEN/8, x3, x2, x7) + +inst_987: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x332 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x115 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79a6; op2val:0x3b32; +op3val:0x7915; valaddr_reg:x1; val_offset:2865*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2865*FLEN/8, x3, x2, x7) + +inst_988: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x332 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x115 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79a6; op2val:0x3b32; +op3val:0x7915; valaddr_reg:x1; val_offset:2868*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2868*FLEN/8, x3, x2, x7) + +inst_989: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x332 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x115 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79a6; op2val:0x3b32; +op3val:0x7915; valaddr_reg:x1; val_offset:2871*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2871*FLEN/8, x3, x2, x7) + +inst_990: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x278 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2de and fs3 == 0 and fe3 == 0x1d and fm3 == 0x18e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7678; op2val:0x3ade; +op3val:0x758e; valaddr_reg:x1; val_offset:2874*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2874*FLEN/8, x3, x2, x7) + +inst_991: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x278 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2de and fs3 == 0 and fe3 == 0x1d and fm3 == 0x18e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7678; op2val:0x3ade; +op3val:0x758e; valaddr_reg:x1; val_offset:2877*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2877*FLEN/8, x3, x2, x7) + +inst_992: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x278 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2de and fs3 == 0 and fe3 == 0x1d and fm3 == 0x18e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7678; op2val:0x3ade; +op3val:0x758e; valaddr_reg:x1; val_offset:2880*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2880*FLEN/8, x3, x2, x7) + +inst_993: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x278 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2de and fs3 == 0 and fe3 == 0x1d and fm3 == 0x18e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7678; op2val:0x3ade; +op3val:0x758e; valaddr_reg:x1; val_offset:2883*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2883*FLEN/8, x3, x2, x7) + +inst_994: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x278 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2de and fs3 == 0 and fe3 == 0x1d and fm3 == 0x18e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7678; op2val:0x3ade; +op3val:0x758e; valaddr_reg:x1; val_offset:2886*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2886*FLEN/8, x3, x2, x7) + +inst_995: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x2f5 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x027 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6af5; op2val:0x40c5; +op3val:0x7027; valaddr_reg:x1; val_offset:2889*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2889*FLEN/8, x3, x2, x7) + +inst_996: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x2f5 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x027 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6af5; op2val:0x40c5; +op3val:0x7027; valaddr_reg:x1; val_offset:2892*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2892*FLEN/8, x3, x2, x7) + +inst_997: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x2f5 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x027 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6af5; op2val:0x40c5; +op3val:0x7027; valaddr_reg:x1; val_offset:2895*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2895*FLEN/8, x3, x2, x7) + +inst_998: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x2f5 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x027 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6af5; op2val:0x40c5; +op3val:0x7027; valaddr_reg:x1; val_offset:2898*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2898*FLEN/8, x3, x2, x7) + +inst_999: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x2f5 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x027 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6af5; op2val:0x40c5; +op3val:0x7027; valaddr_reg:x1; val_offset:2901*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2901*FLEN/8, x3, x2, x7) + +inst_1000: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x086 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x13c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ec and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c86; op2val:0x493c; +op3val:0x79ec; valaddr_reg:x1; val_offset:2904*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2904*FLEN/8, x3, x2, x7) + +inst_1001: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x086 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x13c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ec and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c86; op2val:0x493c; +op3val:0x79ec; valaddr_reg:x1; val_offset:2907*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2907*FLEN/8, x3, x2, x7) + +inst_1002: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x086 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x13c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ec and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c86; op2val:0x493c; +op3val:0x79ec; valaddr_reg:x1; val_offset:2910*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2910*FLEN/8, x3, x2, x7) + +inst_1003: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x086 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x13c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ec and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c86; op2val:0x493c; +op3val:0x79ec; valaddr_reg:x1; val_offset:2913*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2913*FLEN/8, x3, x2, x7) + +inst_1004: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x086 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x13c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ec and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c86; op2val:0x493c; +op3val:0x79ec; valaddr_reg:x1; val_offset:2916*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2916*FLEN/8, x3, x2, x7) + +inst_1005: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x016 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x11c and fs3 == 0 and fe3 == 0x1c and fm3 == 0x138 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7416; op2val:0x391c; +op3val:0x7138; valaddr_reg:x1; val_offset:2919*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2919*FLEN/8, x3, x2, x7) + +inst_1006: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x016 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x11c and fs3 == 0 and fe3 == 0x1c and fm3 == 0x138 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7416; op2val:0x391c; +op3val:0x7138; valaddr_reg:x1; val_offset:2922*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2922*FLEN/8, x3, x2, x7) + +inst_1007: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x016 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x11c and fs3 == 0 and fe3 == 0x1c and fm3 == 0x138 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7416; op2val:0x391c; +op3val:0x7138; valaddr_reg:x1; val_offset:2925*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2925*FLEN/8, x3, x2, x7) + +inst_1008: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x016 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x11c and fs3 == 0 and fe3 == 0x1c and fm3 == 0x138 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7416; op2val:0x391c; +op3val:0x7138; valaddr_reg:x1; val_offset:2928*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2928*FLEN/8, x3, x2, x7) + +inst_1009: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x016 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x11c and fs3 == 0 and fe3 == 0x1c and fm3 == 0x138 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7416; op2val:0x391c; +op3val:0x7138; valaddr_reg:x1; val_offset:2931*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2931*FLEN/8, x3, x2, x7) + +inst_1010: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x167 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x0fa and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ba and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d67; op2val:0x48fa; +op3val:0x7aba; valaddr_reg:x1; val_offset:2934*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2934*FLEN/8, x3, x2, x7) + +inst_1011: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x167 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x0fa and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ba and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d67; op2val:0x48fa; +op3val:0x7aba; valaddr_reg:x1; val_offset:2937*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2937*FLEN/8, x3, x2, x7) + +inst_1012: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x167 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x0fa and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ba and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d67; op2val:0x48fa; +op3val:0x7aba; valaddr_reg:x1; val_offset:2940*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2940*FLEN/8, x3, x2, x7) + +inst_1013: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x167 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x0fa and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ba and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d67; op2val:0x48fa; +op3val:0x7aba; valaddr_reg:x1; val_offset:2943*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2943*FLEN/8, x3, x2, x7) + +inst_1014: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x167 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x0fa and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ba and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d67; op2val:0x48fa; +op3val:0x7aba; valaddr_reg:x1; val_offset:2946*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2946*FLEN/8, x3, x2, x7) + +inst_1015: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x229 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x15c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7af5; op2val:0x3a29; +op3val:0x795c; valaddr_reg:x1; val_offset:2949*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2949*FLEN/8, x3, x2, x7) + +inst_1016: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x229 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x15c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7af5; op2val:0x3a29; +op3val:0x795c; valaddr_reg:x1; val_offset:2952*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2952*FLEN/8, x3, x2, x7) + +inst_1017: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x229 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x15c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7af5; op2val:0x3a29; +op3val:0x795c; valaddr_reg:x1; val_offset:2955*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2955*FLEN/8, x3, x2, x7) + +inst_1018: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x229 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x15c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7af5; op2val:0x3a29; +op3val:0x795c; valaddr_reg:x1; val_offset:2958*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2958*FLEN/8, x3, x2, x7) + +inst_1019: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x229 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x15c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7af5; op2val:0x3a29; +op3val:0x795c; valaddr_reg:x1; val_offset:2961*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2961*FLEN/8, x3, x2, x7) + +inst_1020: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x082 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2df and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3bf and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7482; op2val:0x3adf; +op3val:0x73bf; valaddr_reg:x1; val_offset:2964*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2964*FLEN/8, x3, x2, x7) + +inst_1021: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x082 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2df and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3bf and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7482; op2val:0x3adf; +op3val:0x73bf; valaddr_reg:x1; val_offset:2967*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2967*FLEN/8, x3, x2, x7) + +inst_1022: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x082 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2df and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3bf and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7482; op2val:0x3adf; +op3val:0x73bf; valaddr_reg:x1; val_offset:2970*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2970*FLEN/8, x3, x2, x7) + +inst_1023: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x082 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2df and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3bf and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7482; op2val:0x3adf; +op3val:0x73bf; valaddr_reg:x1; val_offset:2973*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2973*FLEN/8, x3, x2, x7) + +inst_1024: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x082 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2df and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3bf and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7482; op2val:0x3adf; +op3val:0x73bf; valaddr_reg:x1; val_offset:2976*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2976*FLEN/8, x3, x2, x7) + +inst_1025: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0af and fs2 == 0 and fe2 == 0x0f and fm2 == 0x245 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x359 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74af; op2val:0x3e45; +op3val:0x7759; valaddr_reg:x1; val_offset:2979*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2979*FLEN/8, x3, x2, x7) + +inst_1026: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0af and fs2 == 0 and fe2 == 0x0f and fm2 == 0x245 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x359 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74af; op2val:0x3e45; +op3val:0x7759; valaddr_reg:x1; val_offset:2982*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2982*FLEN/8, x3, x2, x7) + +inst_1027: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0af and fs2 == 0 and fe2 == 0x0f and fm2 == 0x245 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x359 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74af; op2val:0x3e45; +op3val:0x7759; valaddr_reg:x1; val_offset:2985*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2985*FLEN/8, x3, x2, x7) + +inst_1028: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0af and fs2 == 0 and fe2 == 0x0f and fm2 == 0x245 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x359 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74af; op2val:0x3e45; +op3val:0x7759; valaddr_reg:x1; val_offset:2988*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2988*FLEN/8, x3, x2, x7) + +inst_1029: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0af and fs2 == 0 and fe2 == 0x0f and fm2 == 0x245 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x359 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74af; op2val:0x3e45; +op3val:0x7759; valaddr_reg:x1; val_offset:2991*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2991*FLEN/8, x3, x2, x7) + +inst_1030: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x109 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1a8 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x321 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7109; op2val:0x41a8; +op3val:0x7721; valaddr_reg:x1; val_offset:2994*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2994*FLEN/8, x3, x2, x7) + +inst_1031: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x109 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1a8 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x321 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7109; op2val:0x41a8; +op3val:0x7721; valaddr_reg:x1; val_offset:2997*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2997*FLEN/8, x3, x2, x7) + +inst_1032: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x109 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1a8 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x321 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7109; op2val:0x41a8; +op3val:0x7721; valaddr_reg:x1; val_offset:3000*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3000*FLEN/8, x3, x2, x7) + +inst_1033: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x109 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1a8 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x321 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7109; op2val:0x41a8; +op3val:0x7721; valaddr_reg:x1; val_offset:3003*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3003*FLEN/8, x3, x2, x7) + +inst_1034: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x109 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1a8 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x321 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7109; op2val:0x41a8; +op3val:0x7721; valaddr_reg:x1; val_offset:3006*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3006*FLEN/8, x3, x2, x7) + +inst_1035: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x035 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x34e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7435; op2val:0x434e; +op3val:0x7bb0; valaddr_reg:x1; val_offset:3009*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3009*FLEN/8, x3, x2, x7) + +inst_1036: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x035 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x34e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7435; op2val:0x434e; +op3val:0x7bb0; valaddr_reg:x1; val_offset:3012*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3012*FLEN/8, x3, x2, x7) + +inst_1037: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x035 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x34e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7435; op2val:0x434e; +op3val:0x7bb0; valaddr_reg:x1; val_offset:3015*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3015*FLEN/8, x3, x2, x7) + +inst_1038: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x035 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x34e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7435; op2val:0x434e; +op3val:0x7bb0; valaddr_reg:x1; val_offset:3018*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3018*FLEN/8, x3, x2, x7) + +inst_1039: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x035 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x34e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7435; op2val:0x434e; +op3val:0x7bb0; valaddr_reg:x1; val_offset:3021*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3021*FLEN/8, x3, x2, x7) + +inst_1040: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x07f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x05f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bc6; op2val:0x387f; +op3val:0x785f; valaddr_reg:x1; val_offset:3024*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3024*FLEN/8, x3, x2, x7) + +inst_1041: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x07f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x05f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bc6; op2val:0x387f; +op3val:0x785f; valaddr_reg:x1; val_offset:3027*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3027*FLEN/8, x3, x2, x7) + +inst_1042: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x07f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x05f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bc6; op2val:0x387f; +op3val:0x785f; valaddr_reg:x1; val_offset:3030*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3030*FLEN/8, x3, x2, x7) + +inst_1043: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x07f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x05f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bc6; op2val:0x387f; +op3val:0x785f; valaddr_reg:x1; val_offset:3033*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3033*FLEN/8, x3, x2, x7) + +inst_1044: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x07f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x05f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bc6; op2val:0x387f; +op3val:0x785f; valaddr_reg:x1; val_offset:3036*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3036*FLEN/8, x3, x2, x7) + +inst_1045: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3d1 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3e6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73d1; op2val:0x43e6; +op3val:0x7bb8; valaddr_reg:x1; val_offset:3039*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3039*FLEN/8, x3, x2, x7) + +inst_1046: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3d1 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3e6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73d1; op2val:0x43e6; +op3val:0x7bb8; valaddr_reg:x1; val_offset:3042*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3042*FLEN/8, x3, x2, x7) + +inst_1047: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3d1 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3e6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73d1; op2val:0x43e6; +op3val:0x7bb8; valaddr_reg:x1; val_offset:3045*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3045*FLEN/8, x3, x2, x7) + +inst_1048: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3d1 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3e6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73d1; op2val:0x43e6; +op3val:0x7bb8; valaddr_reg:x1; val_offset:3048*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3048*FLEN/8, x3, x2, x7) + +inst_1049: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3d1 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3e6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73d1; op2val:0x43e6; +op3val:0x7bb8; valaddr_reg:x1; val_offset:3051*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3051*FLEN/8, x3, x2, x7) + +inst_1050: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f3 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x09b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1b3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74f3; op2val:0x3c9b; +op3val:0x75b3; valaddr_reg:x1; val_offset:3054*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3054*FLEN/8, x3, x2, x7) +RVTEST_SIGBASE(x2,signature_x2_8) + +inst_1051: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f3 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x09b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1b3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74f3; op2val:0x3c9b; +op3val:0x75b3; valaddr_reg:x1; val_offset:3057*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3057*FLEN/8, x3, x2, x7) + +inst_1052: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f3 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x09b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1b3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74f3; op2val:0x3c9b; +op3val:0x75b3; valaddr_reg:x1; val_offset:3060*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3060*FLEN/8, x3, x2, x7) + +inst_1053: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f3 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x09b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1b3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74f3; op2val:0x3c9b; +op3val:0x75b3; valaddr_reg:x1; val_offset:3063*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3063*FLEN/8, x3, x2, x7) + +inst_1054: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f3 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x09b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1b3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74f3; op2val:0x3c9b; +op3val:0x75b3; valaddr_reg:x1; val_offset:3066*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3066*FLEN/8, x3, x2, x7) + +inst_1055: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x070 and fs2 == 0 and fe2 == 0x17 and fm2 == 0x180 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x21a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5470; op2val:0x5d80; +op3val:0x761a; valaddr_reg:x1; val_offset:3069*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3069*FLEN/8, x3, x2, x7) + +inst_1056: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x070 and fs2 == 0 and fe2 == 0x17 and fm2 == 0x180 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x21a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5470; op2val:0x5d80; +op3val:0x761a; valaddr_reg:x1; val_offset:3072*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3072*FLEN/8, x3, x2, x7) + +inst_1057: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x070 and fs2 == 0 and fe2 == 0x17 and fm2 == 0x180 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x21a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5470; op2val:0x5d80; +op3val:0x761a; valaddr_reg:x1; val_offset:3075*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3075*FLEN/8, x3, x2, x7) + +inst_1058: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x070 and fs2 == 0 and fe2 == 0x17 and fm2 == 0x180 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x21a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5470; op2val:0x5d80; +op3val:0x761a; valaddr_reg:x1; val_offset:3078*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3078*FLEN/8, x3, x2, x7) + +inst_1059: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x070 and fs2 == 0 and fe2 == 0x17 and fm2 == 0x180 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x21a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5470; op2val:0x5d80; +op3val:0x761a; valaddr_reg:x1; val_offset:3081*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3081*FLEN/8, x3, x2, x7) + +inst_1060: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x397 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x03c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x005 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7797; op2val:0x3c3c; +op3val:0x7805; valaddr_reg:x1; val_offset:3084*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3084*FLEN/8, x3, x2, x7) + +inst_1061: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x397 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x03c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x005 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7797; op2val:0x3c3c; +op3val:0x7805; valaddr_reg:x1; val_offset:3087*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3087*FLEN/8, x3, x2, x7) + +inst_1062: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x397 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x03c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x005 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7797; op2val:0x3c3c; +op3val:0x7805; valaddr_reg:x1; val_offset:3090*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3090*FLEN/8, x3, x2, x7) + +inst_1063: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x397 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x03c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x005 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7797; op2val:0x3c3c; +op3val:0x7805; valaddr_reg:x1; val_offset:3093*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3093*FLEN/8, x3, x2, x7) + +inst_1064: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x397 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x03c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x005 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7797; op2val:0x3c3c; +op3val:0x7805; valaddr_reg:x1; val_offset:3096*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3096*FLEN/8, x3, x2, x7) + +inst_1065: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x26d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x105 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x009 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x726d; op2val:0x4105; +op3val:0x7809; valaddr_reg:x1; val_offset:3099*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3099*FLEN/8, x3, x2, x7) + +inst_1066: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x26d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x105 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x009 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x726d; op2val:0x4105; +op3val:0x7809; valaddr_reg:x1; val_offset:3102*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3102*FLEN/8, x3, x2, x7) + +inst_1067: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x26d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x105 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x009 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x726d; op2val:0x4105; +op3val:0x7809; valaddr_reg:x1; val_offset:3105*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3105*FLEN/8, x3, x2, x7) + +inst_1068: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x26d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x105 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x009 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x726d; op2val:0x4105; +op3val:0x7809; valaddr_reg:x1; val_offset:3108*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3108*FLEN/8, x3, x2, x7) + +inst_1069: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x26d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x105 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x009 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x726d; op2val:0x4105; +op3val:0x7809; valaddr_reg:x1; val_offset:3111*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3111*FLEN/8, x3, x2, x7) + +inst_1070: +// fs1 == 0 and fe1 == 0x17 and fm1 == 0x115 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x2a6 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x039 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5d15; op2val:0x52a6; +op3val:0x7439; valaddr_reg:x1; val_offset:3114*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3114*FLEN/8, x3, x2, x7) + +inst_1071: +// fs1 == 0 and fe1 == 0x17 and fm1 == 0x115 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x2a6 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x039 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5d15; op2val:0x52a6; +op3val:0x7439; valaddr_reg:x1; val_offset:3117*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3117*FLEN/8, x3, x2, x7) + +inst_1072: +// fs1 == 0 and fe1 == 0x17 and fm1 == 0x115 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x2a6 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x039 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5d15; op2val:0x52a6; +op3val:0x7439; valaddr_reg:x1; val_offset:3120*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3120*FLEN/8, x3, x2, x7) + +inst_1073: +// fs1 == 0 and fe1 == 0x17 and fm1 == 0x115 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x2a6 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x039 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5d15; op2val:0x52a6; +op3val:0x7439; valaddr_reg:x1; val_offset:3123*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3123*FLEN/8, x3, x2, x7) + +inst_1074: +// fs1 == 0 and fe1 == 0x17 and fm1 == 0x115 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x2a6 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x039 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5d15; op2val:0x52a6; +op3val:0x7439; valaddr_reg:x1; val_offset:3126*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3126*FLEN/8, x3, x2, x7) + +inst_1075: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1be and fs2 == 0 and fe2 == 0x11 and fm2 == 0x073 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x263 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dbe; op2val:0x4473; +op3val:0x7663; valaddr_reg:x1; val_offset:3129*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3129*FLEN/8, x3, x2, x7) + +inst_1076: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1be and fs2 == 0 and fe2 == 0x11 and fm2 == 0x073 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x263 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dbe; op2val:0x4473; +op3val:0x7663; valaddr_reg:x1; val_offset:3132*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3132*FLEN/8, x3, x2, x7) + +inst_1077: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1be and fs2 == 0 and fe2 == 0x11 and fm2 == 0x073 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x263 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dbe; op2val:0x4473; +op3val:0x7663; valaddr_reg:x1; val_offset:3135*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3135*FLEN/8, x3, x2, x7) + +inst_1078: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1be and fs2 == 0 and fe2 == 0x11 and fm2 == 0x073 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x263 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dbe; op2val:0x4473; +op3val:0x7663; valaddr_reg:x1; val_offset:3138*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3138*FLEN/8, x3, x2, x7) + +inst_1079: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1be and fs2 == 0 and fe2 == 0x11 and fm2 == 0x073 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x263 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dbe; op2val:0x4473; +op3val:0x7663; valaddr_reg:x1; val_offset:3141*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3141*FLEN/8, x3, x2, x7) + +inst_1080: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x155 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x051 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x1c2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6955; op2val:0x3851; +op3val:0x65c2; valaddr_reg:x1; val_offset:3144*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3144*FLEN/8, x3, x2, x7) + +inst_1081: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x155 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x051 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x1c2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6955; op2val:0x3851; +op3val:0x65c2; valaddr_reg:x1; val_offset:3147*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3147*FLEN/8, x3, x2, x7) + +inst_1082: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x155 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x051 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x1c2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6955; op2val:0x3851; +op3val:0x65c2; valaddr_reg:x1; val_offset:3150*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3150*FLEN/8, x3, x2, x7) + +inst_1083: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x155 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x051 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x1c2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6955; op2val:0x3851; +op3val:0x65c2; valaddr_reg:x1; val_offset:3153*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3153*FLEN/8, x3, x2, x7) + +inst_1084: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x155 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x051 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x1c2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6955; op2val:0x3851; +op3val:0x65c2; valaddr_reg:x1; val_offset:3156*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3156*FLEN/8, x3, x2, x7) + +inst_1085: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0dd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x21f and fs3 == 0 and fe3 == 0x1c and fm3 == 0x372 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74dd; op2val:0x3a1f; +op3val:0x7372; valaddr_reg:x1; val_offset:3159*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3159*FLEN/8, x3, x2, x7) + +inst_1086: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0dd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x21f and fs3 == 0 and fe3 == 0x1c and fm3 == 0x372 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74dd; op2val:0x3a1f; +op3val:0x7372; valaddr_reg:x1; val_offset:3162*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3162*FLEN/8, x3, x2, x7) + +inst_1087: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0dd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x21f and fs3 == 0 and fe3 == 0x1c and fm3 == 0x372 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74dd; op2val:0x3a1f; +op3val:0x7372; valaddr_reg:x1; val_offset:3165*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3165*FLEN/8, x3, x2, x7) + +inst_1088: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0dd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x21f and fs3 == 0 and fe3 == 0x1c and fm3 == 0x372 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74dd; op2val:0x3a1f; +op3val:0x7372; valaddr_reg:x1; val_offset:3168*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3168*FLEN/8, x3, x2, x7) + +inst_1089: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0dd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x21f and fs3 == 0 and fe3 == 0x1c and fm3 == 0x372 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74dd; op2val:0x3a1f; +op3val:0x7372; valaddr_reg:x1; val_offset:3171*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3171*FLEN/8, x3, x2, x7) + +inst_1090: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ae and fs2 == 0 and fe2 == 0x0e and fm2 == 0x33a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x03b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78ae; op2val:0x3b3a; +op3val:0x783b; valaddr_reg:x1; val_offset:3174*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3174*FLEN/8, x3, x2, x7) + +inst_1091: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ae and fs2 == 0 and fe2 == 0x0e and fm2 == 0x33a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x03b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78ae; op2val:0x3b3a; +op3val:0x783b; valaddr_reg:x1; val_offset:3177*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3177*FLEN/8, x3, x2, x7) + +inst_1092: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ae and fs2 == 0 and fe2 == 0x0e and fm2 == 0x33a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x03b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78ae; op2val:0x3b3a; +op3val:0x783b; valaddr_reg:x1; val_offset:3180*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3180*FLEN/8, x3, x2, x7) + +inst_1093: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ae and fs2 == 0 and fe2 == 0x0e and fm2 == 0x33a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x03b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78ae; op2val:0x3b3a; +op3val:0x783b; valaddr_reg:x1; val_offset:3183*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3183*FLEN/8, x3, x2, x7) + +inst_1094: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ae and fs2 == 0 and fe2 == 0x0e and fm2 == 0x33a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x03b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78ae; op2val:0x3b3a; +op3val:0x783b; valaddr_reg:x1; val_offset:3186*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3186*FLEN/8, x3, x2, x7) + +inst_1095: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x302 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x142 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a00; op2val:0x3b02; +op3val:0x7942; valaddr_reg:x1; val_offset:3189*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3189*FLEN/8, x3, x2, x7) + +inst_1096: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x302 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x142 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a00; op2val:0x3b02; +op3val:0x7942; valaddr_reg:x1; val_offset:3192*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3192*FLEN/8, x3, x2, x7) + +inst_1097: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x302 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x142 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a00; op2val:0x3b02; +op3val:0x7942; valaddr_reg:x1; val_offset:3195*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3195*FLEN/8, x3, x2, x7) + +inst_1098: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x302 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x142 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a00; op2val:0x3b02; +op3val:0x7942; valaddr_reg:x1; val_offset:3198*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3198*FLEN/8, x3, x2, x7) + +inst_1099: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x302 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x142 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a00; op2val:0x3b02; +op3val:0x7942; valaddr_reg:x1; val_offset:3201*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3201*FLEN/8, x3, x2, x7) + +inst_1100: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b9 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0e9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x307 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79b9; op2val:0x3ce9; +op3val:0x7b07; valaddr_reg:x1; val_offset:3204*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3204*FLEN/8, x3, x2, x7) + +inst_1101: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b9 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0e9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x307 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79b9; op2val:0x3ce9; +op3val:0x7b07; valaddr_reg:x1; val_offset:3207*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3207*FLEN/8, x3, x2, x7) + +inst_1102: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b9 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0e9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x307 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79b9; op2val:0x3ce9; +op3val:0x7b07; valaddr_reg:x1; val_offset:3210*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3210*FLEN/8, x3, x2, x7) + +inst_1103: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b9 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0e9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x307 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79b9; op2val:0x3ce9; +op3val:0x7b07; valaddr_reg:x1; val_offset:3213*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3213*FLEN/8, x3, x2, x7) + +inst_1104: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b9 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0e9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x307 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79b9; op2val:0x3ce9; +op3val:0x7b07; valaddr_reg:x1; val_offset:3216*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3216*FLEN/8, x3, x2, x7) + +inst_1105: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x23a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2b2 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x137 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x763a; op2val:0x3ab2; +op3val:0x7537; valaddr_reg:x1; val_offset:3219*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3219*FLEN/8, x3, x2, x7) + +inst_1106: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x23a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2b2 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x137 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x763a; op2val:0x3ab2; +op3val:0x7537; valaddr_reg:x1; val_offset:3222*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3222*FLEN/8, x3, x2, x7) + +inst_1107: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x23a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2b2 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x137 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x763a; op2val:0x3ab2; +op3val:0x7537; valaddr_reg:x1; val_offset:3225*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3225*FLEN/8, x3, x2, x7) + +inst_1108: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x23a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2b2 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x137 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x763a; op2val:0x3ab2; +op3val:0x7537; valaddr_reg:x1; val_offset:3228*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3228*FLEN/8, x3, x2, x7) + +inst_1109: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x23a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2b2 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x137 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x763a; op2val:0x3ab2; +op3val:0x7537; valaddr_reg:x1; val_offset:3231*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3231*FLEN/8, x3, x2, x7) + +inst_1110: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3df and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0db and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0c7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bdf; op2val:0x30db; +op3val:0x70c7; valaddr_reg:x1; val_offset:3234*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3234*FLEN/8, x3, x2, x7) + +inst_1111: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3df and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0db and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0c7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bdf; op2val:0x30db; +op3val:0x70c7; valaddr_reg:x1; val_offset:3237*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3237*FLEN/8, x3, x2, x7) + +inst_1112: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3df and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0db and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0c7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bdf; op2val:0x30db; +op3val:0x70c7; valaddr_reg:x1; val_offset:3240*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3240*FLEN/8, x3, x2, x7) + +inst_1113: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3df and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0db and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0c7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bdf; op2val:0x30db; +op3val:0x70c7; valaddr_reg:x1; val_offset:3243*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3243*FLEN/8, x3, x2, x7) + +inst_1114: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3df and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0db and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0c7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bdf; op2val:0x30db; +op3val:0x70c7; valaddr_reg:x1; val_offset:3246*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3246*FLEN/8, x3, x2, x7) + +inst_1115: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ca and fs2 == 0 and fe2 == 0x0e and fm2 == 0x31b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x124 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79ca; op2val:0x3b1b; +op3val:0x7924; valaddr_reg:x1; val_offset:3249*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3249*FLEN/8, x3, x2, x7) + +inst_1116: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ca and fs2 == 0 and fe2 == 0x0e and fm2 == 0x31b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x124 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79ca; op2val:0x3b1b; +op3val:0x7924; valaddr_reg:x1; val_offset:3252*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3252*FLEN/8, x3, x2, x7) + +inst_1117: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ca and fs2 == 0 and fe2 == 0x0e and fm2 == 0x31b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x124 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79ca; op2val:0x3b1b; +op3val:0x7924; valaddr_reg:x1; val_offset:3255*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3255*FLEN/8, x3, x2, x7) + +inst_1118: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ca and fs2 == 0 and fe2 == 0x0e and fm2 == 0x31b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x124 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79ca; op2val:0x3b1b; +op3val:0x7924; valaddr_reg:x1; val_offset:3258*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3258*FLEN/8, x3, x2, x7) + +inst_1119: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ca and fs2 == 0 and fe2 == 0x0e and fm2 == 0x31b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x124 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79ca; op2val:0x3b1b; +op3val:0x7924; valaddr_reg:x1; val_offset:3261*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3261*FLEN/8, x3, x2, x7) + +inst_1120: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x12d and fs2 == 0 and fe2 == 0x0d and fm2 == 0x374 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x752d; op2val:0x3774; +op3val:0x70d3; valaddr_reg:x1; val_offset:3264*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3264*FLEN/8, x3, x2, x7) + +inst_1121: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x12d and fs2 == 0 and fe2 == 0x0d and fm2 == 0x374 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x752d; op2val:0x3774; +op3val:0x70d3; valaddr_reg:x1; val_offset:3267*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3267*FLEN/8, x3, x2, x7) + +inst_1122: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x12d and fs2 == 0 and fe2 == 0x0d and fm2 == 0x374 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x752d; op2val:0x3774; +op3val:0x70d3; valaddr_reg:x1; val_offset:3270*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3270*FLEN/8, x3, x2, x7) + +inst_1123: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x12d and fs2 == 0 and fe2 == 0x0d and fm2 == 0x374 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x752d; op2val:0x3774; +op3val:0x70d3; valaddr_reg:x1; val_offset:3273*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3273*FLEN/8, x3, x2, x7) + +inst_1124: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x134 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x31f and fs3 == 0 and fe3 == 0x1b and fm3 == 0x0a2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7934; op2val:0x2f1f; +op3val:0x6ca2; valaddr_reg:x1; val_offset:3276*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3276*FLEN/8, x3, x2, x7) + +inst_1125: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x134 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x31f and fs3 == 0 and fe3 == 0x1b and fm3 == 0x0a2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7934; op2val:0x2f1f; +op3val:0x6ca2; valaddr_reg:x1; val_offset:3279*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3279*FLEN/8, x3, x2, x7) + +inst_1126: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x048 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x175 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1d9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7848; op2val:0x3975; +op3val:0x75d9; valaddr_reg:x1; val_offset:3282*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3282*FLEN/8, x3, x2, x7) + +inst_1127: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x048 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x175 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1d9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7848; op2val:0x3975; +op3val:0x75d9; valaddr_reg:x1; val_offset:3285*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3285*FLEN/8, x3, x2, x7) + +inst_1128: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x048 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x175 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1d9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7848; op2val:0x3975; +op3val:0x75d9; valaddr_reg:x1; val_offset:3288*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3288*FLEN/8, x3, x2, x7) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(29997,32,FLEN) +NAN_BOXED(29997,32,FLEN) +NAN_BOXED(29997,32,FLEN) +NAN_BOXED(29997,32,FLEN) +NAN_BOXED(14196,32,FLEN) +NAN_BOXED(28883,32,FLEN) +NAN_BOXED(29997,32,FLEN) +NAN_BOXED(29997,32,FLEN) +NAN_BOXED(28883,32,FLEN) +NAN_BOXED(29997,32,FLEN) +NAN_BOXED(14196,32,FLEN) +NAN_BOXED(14196,32,FLEN) +NAN_BOXED(29997,32,FLEN) +NAN_BOXED(29997,32,FLEN) +NAN_BOXED(29997,32,FLEN) +NAN_BOXED(31028,32,FLEN) +NAN_BOXED(12063,32,FLEN) +NAN_BOXED(27810,32,FLEN) +NAN_BOXED(31028,32,FLEN) +NAN_BOXED(12063,32,FLEN) +NAN_BOXED(27810,32,FLEN) +NAN_BOXED(31028,32,FLEN) +NAN_BOXED(12063,32,FLEN) +NAN_BOXED(27810,32,FLEN) +NAN_BOXED(31028,32,FLEN) +NAN_BOXED(12063,32,FLEN) +NAN_BOXED(12063,32,FLEN) +NAN_BOXED(31028,32,FLEN) +NAN_BOXED(31028,32,FLEN) +NAN_BOXED(27810,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(14709,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(30792,32,FLEN) +NAN_BOXED(14709,32,FLEN) +NAN_BOXED(30792,32,FLEN) +test_dataset_1: +NAN_BOXED(30792,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(30169,32,FLEN) +NAN_BOXED(30792,32,FLEN) +NAN_BOXED(14709,32,FLEN) +NAN_BOXED(30169,32,FLEN) +NAN_BOXED(30792,32,FLEN) +NAN_BOXED(14709,32,FLEN) +NAN_BOXED(30169,32,FLEN) +NAN_BOXED(27500,32,FLEN) +NAN_BOXED(18527,32,FLEN) +NAN_BOXED(30734,32,FLEN) +NAN_BOXED(27500,32,FLEN) +NAN_BOXED(18527,32,FLEN) +NAN_BOXED(30734,32,FLEN) +NAN_BOXED(27500,32,FLEN) +NAN_BOXED(18527,32,FLEN) +NAN_BOXED(30734,32,FLEN) +NAN_BOXED(27500,32,FLEN) +NAN_BOXED(18527,32,FLEN) +NAN_BOXED(30734,32,FLEN) +NAN_BOXED(27500,32,FLEN) +NAN_BOXED(18527,32,FLEN) +NAN_BOXED(30734,32,FLEN) +NAN_BOXED(26828,32,FLEN) +NAN_BOXED(18887,32,FLEN) +NAN_BOXED(30447,32,FLEN) +NAN_BOXED(26828,32,FLEN) +NAN_BOXED(18887,32,FLEN) +NAN_BOXED(30447,32,FLEN) +NAN_BOXED(26828,32,FLEN) +NAN_BOXED(18887,32,FLEN) +NAN_BOXED(30447,32,FLEN) +test_dataset_2: +NAN_BOXED(26828,32,FLEN) +NAN_BOXED(18887,32,FLEN) +NAN_BOXED(30447,32,FLEN) +NAN_BOXED(26828,32,FLEN) +NAN_BOXED(18887,32,FLEN) +NAN_BOXED(30447,32,FLEN) +NAN_BOXED(27768,32,FLEN) +NAN_BOXED(15665,32,FLEN) +NAN_BOXED(28109,32,FLEN) +NAN_BOXED(27768,32,FLEN) +NAN_BOXED(15665,32,FLEN) +NAN_BOXED(28109,32,FLEN) +NAN_BOXED(27768,32,FLEN) +NAN_BOXED(15665,32,FLEN) +NAN_BOXED(28109,32,FLEN) +NAN_BOXED(27768,32,FLEN) +NAN_BOXED(15665,32,FLEN) +NAN_BOXED(28109,32,FLEN) +NAN_BOXED(27768,32,FLEN) +NAN_BOXED(15665,32,FLEN) +NAN_BOXED(28109,32,FLEN) +NAN_BOXED(30410,32,FLEN) +NAN_BOXED(16330,32,FLEN) +NAN_BOXED(31388,32,FLEN) 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+NAN_BOXED(30779,16,FLEN) +NAN_BOXED(31232,16,FLEN) +NAN_BOXED(15106,16,FLEN) +NAN_BOXED(31042,16,FLEN) +NAN_BOXED(31232,16,FLEN) +NAN_BOXED(15106,16,FLEN) +NAN_BOXED(31042,16,FLEN) +NAN_BOXED(31232,16,FLEN) +NAN_BOXED(15106,16,FLEN) +NAN_BOXED(31042,16,FLEN) +NAN_BOXED(31232,16,FLEN) +NAN_BOXED(15106,16,FLEN) +NAN_BOXED(31042,16,FLEN) +NAN_BOXED(31232,16,FLEN) +NAN_BOXED(15106,16,FLEN) +NAN_BOXED(31042,16,FLEN) +NAN_BOXED(31161,16,FLEN) +NAN_BOXED(15593,16,FLEN) +NAN_BOXED(31495,16,FLEN) +NAN_BOXED(31161,16,FLEN) +NAN_BOXED(15593,16,FLEN) +NAN_BOXED(31495,16,FLEN) +NAN_BOXED(31161,16,FLEN) +NAN_BOXED(15593,16,FLEN) +NAN_BOXED(31495,16,FLEN) +NAN_BOXED(31161,16,FLEN) +NAN_BOXED(15593,16,FLEN) +NAN_BOXED(31495,16,FLEN) +NAN_BOXED(31161,16,FLEN) +NAN_BOXED(15593,16,FLEN) +NAN_BOXED(31495,16,FLEN) +NAN_BOXED(30266,16,FLEN) +NAN_BOXED(15026,16,FLEN) +NAN_BOXED(30007,16,FLEN) +NAN_BOXED(30266,16,FLEN) +NAN_BOXED(15026,16,FLEN) +NAN_BOXED(30007,16,FLEN) +NAN_BOXED(30266,16,FLEN) +NAN_BOXED(15026,16,FLEN) +NAN_BOXED(30007,16,FLEN) +NAN_BOXED(30266,16,FLEN) +NAN_BOXED(15026,16,FLEN) +NAN_BOXED(30007,16,FLEN) +NAN_BOXED(30266,16,FLEN) +NAN_BOXED(15026,16,FLEN) +NAN_BOXED(30007,16,FLEN) +NAN_BOXED(31711,16,FLEN) +NAN_BOXED(12507,16,FLEN) +NAN_BOXED(28871,16,FLEN) +NAN_BOXED(31711,16,FLEN) +NAN_BOXED(12507,16,FLEN) +NAN_BOXED(28871,16,FLEN) +NAN_BOXED(31711,16,FLEN) +NAN_BOXED(12507,16,FLEN) +NAN_BOXED(28871,16,FLEN) +NAN_BOXED(31711,16,FLEN) +NAN_BOXED(12507,16,FLEN) +NAN_BOXED(28871,16,FLEN) +NAN_BOXED(31711,16,FLEN) +NAN_BOXED(12507,16,FLEN) +NAN_BOXED(28871,16,FLEN) +NAN_BOXED(31178,16,FLEN) +NAN_BOXED(15131,16,FLEN) +NAN_BOXED(31012,16,FLEN) +NAN_BOXED(31178,16,FLEN) +NAN_BOXED(15131,16,FLEN) +NAN_BOXED(31012,16,FLEN) +NAN_BOXED(31178,16,FLEN) +NAN_BOXED(15131,16,FLEN) +NAN_BOXED(31012,16,FLEN) +NAN_BOXED(31178,16,FLEN) +NAN_BOXED(15131,16,FLEN) +NAN_BOXED(31012,16,FLEN) +NAN_BOXED(31178,16,FLEN) +NAN_BOXED(15131,16,FLEN) +NAN_BOXED(31012,16,FLEN) +NAN_BOXED(29997,16,FLEN) +NAN_BOXED(14196,16,FLEN) +NAN_BOXED(28883,16,FLEN) +NAN_BOXED(29997,16,FLEN) +NAN_BOXED(14196,16,FLEN) +NAN_BOXED(28883,16,FLEN) +NAN_BOXED(29997,16,FLEN) +NAN_BOXED(14196,16,FLEN) +NAN_BOXED(28883,16,FLEN) +NAN_BOXED(29997,16,FLEN) +NAN_BOXED(14196,16,FLEN) +NAN_BOXED(28883,16,FLEN) +NAN_BOXED(31028,16,FLEN) +NAN_BOXED(12063,16,FLEN) +NAN_BOXED(27810,16,FLEN) +NAN_BOXED(31028,16,FLEN) +NAN_BOXED(12063,16,FLEN) +NAN_BOXED(27810,16,FLEN) +NAN_BOXED(30792,16,FLEN) +NAN_BOXED(14709,16,FLEN) +NAN_BOXED(30169,16,FLEN) +NAN_BOXED(30792,16,FLEN) +NAN_BOXED(14709,16,FLEN) +NAN_BOXED(30169,16,FLEN) +NAN_BOXED(30792,16,FLEN) +NAN_BOXED(14709,16,FLEN) +NAN_BOXED(30169,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x5_0: + .fill 26*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_0: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_1: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_2: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_3: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_4: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_5: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_6: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_7: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_8: + .fill 156*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fmsub_b4-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fmsub_b4-01.S new file mode 100644 index 000000000..b7a541ed9 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fmsub_b4-01.S @@ -0,0 +1,1624 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 05:33:17 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fmsub.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fmsub.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fmsub_b4 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fmsub_b4) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x5,test_dataset_0) +RVTEST_SIGBASE(x6,signature_x6_1) + +inst_0: +// rs1 == rs2 == rs3 != rd, rs1==x13, rs2==x13, rs3==x13, rd==x27,fs1 == 0 and fe1 == 0x1d and fm1 == 0x12d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x31b and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x13; op2:x13; op3:x13; dest:x27; op1val:0x752d; op2val:0x752d; +op3val:0x752d; valaddr_reg:x5; val_offset:0*FLEN/8; rmval:dyn; +testreg:x18; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x27, x13, x13, x13, dyn, 0, 0, x5, 0*FLEN/8, x16, x6, x18) + +inst_1: +// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==x30, rs2==x19, rs3==x18, rd==x25,fs1 == 0 and fe1 == 0x1d and fm1 == 0x12d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x31b and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x19; op3:x18; dest:x25; op1val:0x752d; op2val:0x431b; +op3val:0x70d3; valaddr_reg:x5; val_offset:3*FLEN/8; rmval:dyn; +testreg:x18; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x25, x30, x19, x18, dyn, 32, 0, x5, 3*FLEN/8, x16, x6, x18) + +inst_2: +// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==x12, rs2==x12, rs3==x6, rd==x10,fs1 == 0 and fe1 == 0x1d and fm1 == 0x12d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x31b and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x12; op2:x12; op3:x6; dest:x10; op1val:0x752d; op2val:0x752d; +op3val:0x70d3; valaddr_reg:x5; val_offset:6*FLEN/8; rmval:dyn; +testreg:x18; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x10, x12, x12, x6, dyn, 64, 0, x5, 6*FLEN/8, x16, x6, x18) + +inst_3: +// rd == rs2 == rs3 != rs1, rs1==x29, rs2==x7, rs3==x7, rd==x7,fs1 == 0 and fe1 == 0x1d and fm1 == 0x12d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x31b and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x29; op2:x7; op3:x7; dest:x7; op1val:0x752d; op2val:0x431b; +op3val:0x431b; valaddr_reg:x5; val_offset:9*FLEN/8; rmval:dyn; +testreg:x18; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x7, x29, x7, x7, dyn, 96, 0, x5, 9*FLEN/8, x16, x6, x18) + +inst_4: +// rs1 == rs2 == rs3 == rd, rs1==x8, rs2==x8, rs3==x8, rd==x8,fs1 == 0 and fe1 == 0x1d and fm1 == 0x12d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x31b and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x8; op2:x8; op3:x8; dest:x8; op1val:0x752d; op2val:0x752d; +op3val:0x752d; valaddr_reg:x5; val_offset:12*FLEN/8; rmval:dyn; +testreg:x18; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x8, x8, x8, x8, dyn, 128, 0, x5, 12*FLEN/8, x16, x6, x18) + +inst_5: +// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==x20, rs2==x3, rs3==x17, rd==x3,fs1 == 0 and fe1 == 0x1e and fm1 == 0x134 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1b3 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x0a2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x20; op2:x3; op3:x17; dest:x3; op1val:0x7934; op2val:0xbdb3; +op3val:0x6ca2; valaddr_reg:x5; val_offset:15*FLEN/8; rmval:dyn; +testreg:x18; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x3, x20, x3, x17, dyn, 0, 0, x5, 15*FLEN/8, x16, x6, x18) + +inst_6: +// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==x25, rs2==x2, rs3==x31, rd==x31,fs1 == 0 and fe1 == 0x1e and fm1 == 0x134 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1b3 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x0a2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x25; op2:x2; op3:x31; dest:x31; op1val:0x7934; op2val:0xbdb3; +op3val:0x6ca2; valaddr_reg:x5; val_offset:18*FLEN/8; rmval:dyn; +testreg:x18; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x25, x2, x31, dyn, 32, 0, x5, 18*FLEN/8, x16, x6, x18) + +inst_7: +// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==x14, rs2==x17, rs3==x1, rd==x14,fs1 == 0 and fe1 == 0x1e and fm1 == 0x134 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1b3 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x0a2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x14; op2:x17; op3:x1; dest:x14; op1val:0x7934; op2val:0xbdb3; +op3val:0x6ca2; valaddr_reg:x5; val_offset:21*FLEN/8; rmval:dyn; +testreg:x18; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x14, x14, x17, x1, dyn, 64, 0, x5, 21*FLEN/8, x16, x6, x18) + +inst_8: +// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==x4, rs2==x14, rs3==x14, rd==x19,fs1 == 0 and fe1 == 0x1e and fm1 == 0x134 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1b3 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x0a2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x4; op2:x14; op3:x14; dest:x19; op1val:0x7934; op2val:0xbdb3; +op3val:0xbdb3; valaddr_reg:x5; val_offset:24*FLEN/8; rmval:dyn; +testreg:x18; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x19, x4, x14, x14, dyn, 96, 0, x5, 24*FLEN/8, x16, x6, x18) + +inst_9: +// rs1 == rs2 == rd != rs3, rs1==x11, rs2==x11, rs3==x15, rd==x11,fs1 == 0 and fe1 == 0x1e and fm1 == 0x134 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1b3 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x0a2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x11; op2:x11; op3:x15; dest:x11; op1val:0x7934; op2val:0x7934; +op3val:0x6ca2; valaddr_reg:x5; val_offset:27*FLEN/8; rmval:dyn; +testreg:x18; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x11, x11, x11, x15, dyn, 128, 0, x5, 27*FLEN/8, x16, x6, x18) + +inst_10: +// rs1 == rd == rs3 != rs2, rs1==x9, rs2==x25, rs3==x9, rd==x9,fs1 == 0 and fe1 == 0x1e and fm1 == 0x048 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x118 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1d9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x9; op2:x25; op3:x9; dest:x9; op1val:0x7848; op2val:0x4118; +op3val:0x7848; valaddr_reg:x5; val_offset:30*FLEN/8; rmval:dyn; +testreg:x18; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x9, x9, x25, x9, dyn, 0, 0, x5, 30*FLEN/8, x16, x6, x18) + +inst_11: +// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==x2, rs2==x15, rs3==x2, rd==x1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x048 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x118 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1d9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x2; op2:x15; op3:x2; dest:x1; op1val:0x7848; op2val:0x4118; +op3val:0x7848; valaddr_reg:x5; val_offset:33*FLEN/8; rmval:dyn; +testreg:x18; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x1, x2, x15, x2, dyn, 32, 0, x5, 33*FLEN/8, x16, x6, x18) + +inst_12: +// rs1==x3, rs2==x22, rs3==x26, rd==x15,fs1 == 0 and fe1 == 0x1e and fm1 == 0x048 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x118 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1d9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x3; op2:x22; op3:x26; dest:x15; op1val:0x7848; op2val:0x4118; +op3val:0x75d9; valaddr_reg:x5; val_offset:36*FLEN/8; rmval:dyn; +testreg:x18; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x15, x3, x22, x26, dyn, 64, 0, x5, 36*FLEN/8, x16, x6, x18) +RVTEST_VALBASEUPD(x8,test_dataset_1) + +inst_13: +// rs1==x7, rs2==x30, rs3==x3, rd==x22,fs1 == 0 and fe1 == 0x1e and fm1 == 0x048 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x118 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1d9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x7; op2:x30; op3:x3; dest:x22; op1val:0x7848; op2val:0x4118; +op3val:0x75d9; valaddr_reg:x8; val_offset:0*FLEN/8; rmval:dyn; +testreg:x18; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x22, x7, x30, x3, dyn, 96, 0, x8, 0*FLEN/8, x9, x6, x18) + +inst_14: +// rs1==x22, rs2==x5, rs3==x19, rd==x20,fs1 == 0 and fe1 == 0x1e and fm1 == 0x048 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x118 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1d9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x22; op2:x5; op3:x19; dest:x20; op1val:0x7848; op2val:0x4118; +op3val:0x75d9; valaddr_reg:x8; val_offset:3*FLEN/8; rmval:dyn; +testreg:x18; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x20, x22, x5, x19, dyn, 128, 0, x8, 3*FLEN/8, x9, x6, x18) + +inst_15: +// rs1==x21, rs2==x20, rs3==x28, rd==x16,fs1 == 0 and fe1 == 0x1a and fm1 == 0x36c and fs2 == 1 and fe2 == 0x12 and fm2 == 0x03e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x21; op2:x20; op3:x28; dest:x16; op1val:0x6b6c; op2val:0xc83e; +op3val:0x780e; valaddr_reg:x8; val_offset:6*FLEN/8; rmval:dyn; +testreg:x18; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x16, x21, x20, x28, dyn, 0, 0, x8, 6*FLEN/8, x9, x6, x18) +RVTEST_SIGBASE(x3,signature_x3_0) + +inst_16: +// rs1==x24, rs2==x6, rs3==x16, rd==x29,fs1 == 0 and fe1 == 0x1a and fm1 == 0x36c and fs2 == 1 and fe2 == 0x12 and fm2 == 0x03e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x24; op2:x6; op3:x16; dest:x29; op1val:0x6b6c; op2val:0xc83e; +op3val:0x780e; valaddr_reg:x8; val_offset:9*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x29, x24, x6, x16, dyn, 32, 0, x8, 9*FLEN/8, x9, x3, x7) + +inst_17: +// rs1==x18, rs2==x10, rs3==x27, rd==x0,fs1 == 0 and fe1 == 0x1a and fm1 == 0x36c and fs2 == 1 and fe2 == 0x12 and fm2 == 0x03e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x18; op2:x10; op3:x27; dest:x0; op1val:0x6b6c; op2val:0xc83e; +op3val:0x780e; valaddr_reg:x8; val_offset:12*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x0, x18, x10, x27, dyn, 64, 0, x8, 12*FLEN/8, x9, x3, x7) + +inst_18: +// rs1==x19, rs2==x24, rs3==x10, rd==x26,fs1 == 0 and fe1 == 0x1a and fm1 == 0x36c and fs2 == 1 and fe2 == 0x12 and fm2 == 0x03e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x19; op2:x24; op3:x10; dest:x26; op1val:0x6b6c; op2val:0xc83e; +op3val:0x780e; valaddr_reg:x8; val_offset:15*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x26, x19, x24, x10, dyn, 96, 0, x8, 15*FLEN/8, x9, x3, x7) + +inst_19: +// rs1==x15, rs2==x26, rs3==x24, rd==x12,fs1 == 0 and fe1 == 0x1a and fm1 == 0x36c and fs2 == 1 and fe2 == 0x12 and fm2 == 0x03e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x15; op2:x26; op3:x24; dest:x12; op1val:0x6b6c; op2val:0xc83e; +op3val:0x780e; valaddr_reg:x8; val_offset:18*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x12, x15, x26, x24, dyn, 128, 0, x8, 18*FLEN/8, x9, x3, x7) + +inst_20: +// rs1==x10, rs2==x27, rs3==x25, rd==x30,fs1 == 0 and fe1 == 0x1a and fm1 == 0x0cc and fs2 == 0 and fe2 == 0x14 and fm2 == 0x0c7 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2ef and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x10; op2:x27; op3:x25; dest:x30; op1val:0x68cc; op2val:0x50c7; +op3val:0x76ef; valaddr_reg:x8; val_offset:21*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x30, x10, x27, x25, dyn, 0, 0, x8, 21*FLEN/8, x9, x3, x7) + +inst_21: +// rs1==x6, rs2==x23, rs3==x20, rd==x2,fs1 == 0 and fe1 == 0x1a and fm1 == 0x0cc and fs2 == 0 and fe2 == 0x14 and fm2 == 0x0c7 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2ef and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x6; op2:x23; op3:x20; dest:x2; op1val:0x68cc; op2val:0x50c7; +op3val:0x76ef; valaddr_reg:x8; val_offset:24*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x2, x6, x23, x20, dyn, 32, 0, x8, 24*FLEN/8, x9, x3, x7) + +inst_22: +// rs1==x0, rs2==x4, rs3==x23, rd==x6,fs1 == 0 and fe1 == 0x1a and fm1 == 0x0cc and fs2 == 0 and fe2 == 0x14 and fm2 == 0x0c7 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2ef and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x0; op2:x4; op3:x23; dest:x6; op1val:0x0; op2val:0x50c7; +op3val:0x76ef; valaddr_reg:x8; val_offset:27*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x6, x0, x4, x23, dyn, 64, 0, x8, 27*FLEN/8, x9, x3, x7) + +inst_23: +// rs1==x31, rs2==x29, rs3==x12, rd==x28,fs1 == 0 and fe1 == 0x1a and fm1 == 0x0cc and fs2 == 0 and fe2 == 0x14 and fm2 == 0x0c7 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2ef and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x31; op2:x29; op3:x12; dest:x28; op1val:0x68cc; op2val:0x50c7; +op3val:0x76ef; valaddr_reg:x8; val_offset:30*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x28, x31, x29, x12, dyn, 96, 0, x8, 30*FLEN/8, x9, x3, x7) + +inst_24: +// rs1==x27, rs2==x16, rs3==x29, rd==x18,fs1 == 0 and fe1 == 0x1a and fm1 == 0x0cc and fs2 == 0 and fe2 == 0x14 and fm2 == 0x0c7 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2ef and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x27; op2:x16; op3:x29; dest:x18; op1val:0x68cc; op2val:0x50c7; +op3val:0x76ef; valaddr_reg:x8; val_offset:33*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x18, x27, x16, x29, dyn, 128, 0, x8, 33*FLEN/8, x9, x3, x7) + +inst_25: +// rs1==x16, rs2==x21, rs3==x11, rd==x23,fs1 == 0 and fe1 == 0x1b and fm1 == 0x078 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x281 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x1cd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x16; op2:x21; op3:x11; dest:x23; op1val:0x6c78; op2val:0xca81; +op3val:0x6dcd; valaddr_reg:x8; val_offset:36*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x23, x16, x21, x11, dyn, 0, 0, x8, 36*FLEN/8, x9, x3, x7) + +inst_26: +// rs1==x1, rs2==x18, rs3==x5, rd==x13,fs1 == 0 and fe1 == 0x1b and fm1 == 0x078 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x281 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x1cd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x1; op2:x18; op3:x5; dest:x13; op1val:0x6c78; op2val:0xca81; +op3val:0x6dcd; valaddr_reg:x8; val_offset:39*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x13, x1, x18, x5, dyn, 32, 0, x8, 39*FLEN/8, x9, x3, x7) +RVTEST_VALBASEUPD(x2,test_dataset_2) + +inst_27: +// rs1==x5, rs2==x31, rs3==x22, rd==x21,fs1 == 0 and fe1 == 0x1b and fm1 == 0x078 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x281 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x1cd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x5; op2:x31; op3:x22; dest:x21; op1val:0x6c78; op2val:0xca81; +op3val:0x6dcd; valaddr_reg:x2; val_offset:0*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x21, x5, x31, x22, dyn, 64, 0, x2, 0*FLEN/8, x6, x3, x7) + +inst_28: +// rs1==x23, rs2==x0, rs3==x30, rd==x4,fs1 == 0 and fe1 == 0x1b and fm1 == 0x078 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x281 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x1cd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x23; op2:x0; op3:x30; dest:x4; op1val:0x6c78; op2val:0x0; +op3val:0x6dcd; valaddr_reg:x2; val_offset:3*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x4, x23, x0, x30, dyn, 96, 0, x2, 3*FLEN/8, x6, x3, x7) + +inst_29: +// rs1==x28, rs2==x1, rs3==x21, rd==x17,fs1 == 0 and fe1 == 0x1b and fm1 == 0x078 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x281 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x1cd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x28; op2:x1; op3:x21; dest:x17; op1val:0x6c78; op2val:0xca81; +op3val:0x6dcd; valaddr_reg:x2; val_offset:6*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x17, x28, x1, x21, dyn, 128, 0, x2, 6*FLEN/8, x6, x3, x7) + +inst_30: +// rs1==x17, rs2==x28, rs3==x4, rd==x5,fs1 == 0 and fe1 == 0x1d and fm1 == 0x2ca and fs2 == 0 and fe2 == 0x11 and fm2 == 0x04d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x29c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x17; op2:x28; op3:x4; dest:x5; op1val:0x76ca; op2val:0x444d; +op3val:0x7a9c; valaddr_reg:x2; val_offset:9*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x5, x17, x28, x4, dyn, 0, 0, x2, 9*FLEN/8, x6, x3, x7) + +inst_31: +// rs1==x26, rs2==x9, rs3==x0, rd==x24,fs1 == 0 and fe1 == 0x1d and fm1 == 0x2ca and fs2 == 0 and fe2 == 0x11 and fm2 == 0x04d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x29c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x26; op2:x9; op3:x0; dest:x24; op1val:0x76ca; op2val:0x444d; +op3val:0x0; valaddr_reg:x2; val_offset:12*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x24, x26, x9, x0, dyn, 32, 0, x2, 12*FLEN/8, x6, x3, x7) + +inst_32: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2ca and fs2 == 0 and fe2 == 0x11 and fm2 == 0x04d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x29c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76ca; op2val:0x444d; +op3val:0x7a9c; valaddr_reg:x2; val_offset:15*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x2, 15*FLEN/8, x6, x3, x7) + +inst_33: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2ca and fs2 == 0 and fe2 == 0x11 and fm2 == 0x04d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x29c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76ca; op2val:0x444d; +op3val:0x7a9c; valaddr_reg:x2; val_offset:18*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 18*FLEN/8, x6, x3, x7) + +inst_34: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2ca and fs2 == 0 and fe2 == 0x11 and fm2 == 0x04d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x29c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76ca; op2val:0x444d; +op3val:0x7a9c; valaddr_reg:x2; val_offset:21*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x2, 21*FLEN/8, x6, x3, x7) + +inst_35: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3eb and fs2 == 1 and fe2 == 0x11 and fm2 == 0x246 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x323 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6feb; op2val:0xc646; +op3val:0x7323; valaddr_reg:x2; val_offset:24*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 24*FLEN/8, x6, x3, x7) + +inst_36: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3eb and fs2 == 1 and fe2 == 0x11 and fm2 == 0x246 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x323 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6feb; op2val:0xc646; +op3val:0x7323; valaddr_reg:x2; val_offset:27*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x2, 27*FLEN/8, x6, x3, x7) + +inst_37: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3eb and fs2 == 1 and fe2 == 0x11 and fm2 == 0x246 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x323 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6feb; op2val:0xc646; +op3val:0x7323; valaddr_reg:x2; val_offset:30*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x2, 30*FLEN/8, x6, x3, x7) + +inst_38: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3eb and fs2 == 1 and fe2 == 0x11 and fm2 == 0x246 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x323 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6feb; op2val:0xc646; +op3val:0x7323; valaddr_reg:x2; val_offset:33*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 33*FLEN/8, x6, x3, x7) + +inst_39: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3eb and fs2 == 1 and fe2 == 0x11 and fm2 == 0x246 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x323 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6feb; op2val:0xc646; +op3val:0x7323; valaddr_reg:x2; val_offset:36*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x2, 36*FLEN/8, x6, x3, x7) + +inst_40: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x104 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x235 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x393 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7904; op2val:0x4235; +op3val:0x7b93; valaddr_reg:x2; val_offset:39*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 39*FLEN/8, x6, x3, x7) + +inst_41: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x104 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x235 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x393 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7904; op2val:0x4235; +op3val:0x7b93; valaddr_reg:x2; val_offset:42*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x2, 42*FLEN/8, x6, x3, x7) + +inst_42: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x104 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x235 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x393 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7904; op2val:0x4235; +op3val:0x7b93; valaddr_reg:x2; val_offset:45*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x2, 45*FLEN/8, x6, x3, x7) + +inst_43: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x104 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x235 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x393 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7904; op2val:0x4235; +op3val:0x7b93; valaddr_reg:x2; val_offset:48*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 48*FLEN/8, x6, x3, x7) + +inst_44: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x104 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x235 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x393 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7904; op2val:0x4235; +op3val:0x7b93; valaddr_reg:x2; val_offset:51*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x2, 51*FLEN/8, x6, x3, x7) + +inst_45: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x02e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x258 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x789d; op2val:0xbc2e; +op3val:0x7658; valaddr_reg:x2; val_offset:54*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 54*FLEN/8, x6, x3, x7) + +inst_46: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x02e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x258 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x789d; op2val:0xbc2e; +op3val:0x7658; valaddr_reg:x2; val_offset:57*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x2, 57*FLEN/8, x6, x3, x7) + +inst_47: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x02e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x258 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x789d; op2val:0xbc2e; +op3val:0x7658; valaddr_reg:x2; val_offset:60*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x2, 60*FLEN/8, x6, x3, x7) + +inst_48: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x02e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x258 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x789d; op2val:0xbc2e; +op3val:0x7658; valaddr_reg:x2; val_offset:63*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 63*FLEN/8, x6, x3, x7) + +inst_49: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x02e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x258 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x789d; op2val:0xbc2e; +op3val:0x7658; valaddr_reg:x2; val_offset:66*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x2, 66*FLEN/8, x6, x3, x7) + +inst_50: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ce and fs2 == 0 and fe2 == 0x0f and fm2 == 0x049 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x1f6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bce; op2val:0x3c49; +op3val:0x69f6; valaddr_reg:x2; val_offset:69*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 69*FLEN/8, x6, x3, x7) + +inst_51: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ce and fs2 == 0 and fe2 == 0x0f and fm2 == 0x049 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x1f6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bce; op2val:0x3c49; +op3val:0x69f6; valaddr_reg:x2; val_offset:72*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x2, 72*FLEN/8, x6, x3, x7) + +inst_52: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ce and fs2 == 0 and fe2 == 0x0f and fm2 == 0x049 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x1f6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bce; op2val:0x3c49; +op3val:0x69f6; valaddr_reg:x2; val_offset:75*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x2, 75*FLEN/8, x6, x3, x7) + +inst_53: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ce and fs2 == 0 and fe2 == 0x0f and fm2 == 0x049 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x1f6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bce; op2val:0x3c49; +op3val:0x69f6; valaddr_reg:x2; val_offset:78*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 78*FLEN/8, x6, x3, x7) + +inst_54: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ce and fs2 == 0 and fe2 == 0x0f and fm2 == 0x049 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x1f6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bce; op2val:0x3c49; +op3val:0x69f6; valaddr_reg:x2; val_offset:81*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x2, 81*FLEN/8, x6, x3, x7) + +inst_55: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2dd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x29e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7add; op2val:0xba9e; +op3val:0x74a1; valaddr_reg:x2; val_offset:84*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 84*FLEN/8, x6, x3, x7) + +inst_56: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2dd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x29e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7add; op2val:0xba9e; +op3val:0x74a1; valaddr_reg:x2; val_offset:87*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x2, 87*FLEN/8, x6, x3, x7) + +inst_57: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2dd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x29e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7add; op2val:0xba9e; +op3val:0x74a1; valaddr_reg:x2; val_offset:90*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x2, 90*FLEN/8, x6, x3, x7) + +inst_58: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2dd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x29e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7add; op2val:0xba9e; +op3val:0x74a1; valaddr_reg:x2; val_offset:93*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 93*FLEN/8, x6, x3, x7) + +inst_59: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2dd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x29e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7add; op2val:0xba9e; +op3val:0x74a1; valaddr_reg:x2; val_offset:96*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x2, 96*FLEN/8, x6, x3, x7) + +inst_60: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x09d and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3bf and fs3 == 0 and fe3 == 0x1b and fm3 == 0x389 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x709d; op2val:0x47bf; +op3val:0x6f89; valaddr_reg:x2; val_offset:99*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 99*FLEN/8, x6, x3, x7) + +inst_61: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x09d and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3bf and fs3 == 0 and fe3 == 0x1b and fm3 == 0x389 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x709d; op2val:0x47bf; +op3val:0x6f89; valaddr_reg:x2; val_offset:102*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x2, 102*FLEN/8, x6, x3, x7) + +inst_62: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x09d and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3bf and fs3 == 0 and fe3 == 0x1b and fm3 == 0x389 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x709d; op2val:0x47bf; +op3val:0x6f89; valaddr_reg:x2; val_offset:105*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x2, 105*FLEN/8, x6, x3, x7) + +inst_63: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x09d and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3bf and fs3 == 0 and fe3 == 0x1b and fm3 == 0x389 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x709d; op2val:0x47bf; +op3val:0x6f89; valaddr_reg:x2; val_offset:108*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 108*FLEN/8, x6, x3, x7) + +inst_64: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x09d and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3bf and fs3 == 0 and fe3 == 0x1b and fm3 == 0x389 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x709d; op2val:0x47bf; +op3val:0x6f89; valaddr_reg:x2; val_offset:111*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x2, 111*FLEN/8, x6, x3, x7) + +inst_65: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ee and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0c4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x286 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74ee; op2val:0xb8c4; +op3val:0x7a86; valaddr_reg:x2; val_offset:114*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 114*FLEN/8, x6, x3, x7) + +inst_66: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ee and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0c4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x286 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74ee; op2val:0xb8c4; +op3val:0x7a86; valaddr_reg:x2; val_offset:117*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x2, 117*FLEN/8, x6, x3, x7) + +inst_67: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ee and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0c4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x286 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74ee; op2val:0xb8c4; +op3val:0x7a86; valaddr_reg:x2; val_offset:120*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x2, 120*FLEN/8, x6, x3, x7) + +inst_68: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ee and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0c4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x286 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74ee; op2val:0xb8c4; +op3val:0x7a86; valaddr_reg:x2; val_offset:123*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 123*FLEN/8, x6, x3, x7) + +inst_69: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ee and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0c4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x286 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74ee; op2val:0xb8c4; +op3val:0x7a86; valaddr_reg:x2; val_offset:126*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x2, 126*FLEN/8, x6, x3, x7) + +inst_70: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3d1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71c7; op2val:0x43d1; +op3val:0x78a6; valaddr_reg:x2; val_offset:129*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 129*FLEN/8, x6, x3, x7) + +inst_71: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3d1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71c7; op2val:0x43d1; +op3val:0x78a6; valaddr_reg:x2; val_offset:132*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x2, 132*FLEN/8, x6, x3, x7) + +inst_72: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3d1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71c7; op2val:0x43d1; +op3val:0x78a6; valaddr_reg:x2; val_offset:135*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x2, 135*FLEN/8, x6, x3, x7) + +inst_73: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3d1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71c7; op2val:0x43d1; +op3val:0x78a6; valaddr_reg:x2; val_offset:138*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 138*FLEN/8, x6, x3, x7) + +inst_74: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3d1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71c7; op2val:0x43d1; +op3val:0x78a6; valaddr_reg:x2; val_offset:141*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x2, 141*FLEN/8, x6, x3, x7) + +inst_75: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x11b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x232 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1f4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x791b; op2val:0x3632; +op3val:0x75f4; valaddr_reg:x2; val_offset:144*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 144*FLEN/8, x6, x3, x7) + +inst_76: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x11b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x232 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1f4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x791b; op2val:0x3632; +op3val:0x75f4; valaddr_reg:x2; val_offset:147*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x2, 147*FLEN/8, x6, x3, x7) + +inst_77: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x11b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x232 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1f4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x791b; op2val:0x3632; +op3val:0x75f4; valaddr_reg:x2; val_offset:150*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x2, 150*FLEN/8, x6, x3, x7) + +inst_78: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x11b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x232 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1f4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x791b; op2val:0x3632; +op3val:0x75f4; valaddr_reg:x2; val_offset:153*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 153*FLEN/8, x6, x3, x7) + +inst_79: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x11b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x232 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1f4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x791b; op2val:0x3632; +op3val:0x75f4; valaddr_reg:x2; val_offset:156*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x2, 156*FLEN/8, x6, x3, x7) + +inst_80: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x061 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x091 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x004 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7861; op2val:0x3891; +op3val:0x6c04; valaddr_reg:x2; val_offset:159*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 159*FLEN/8, x6, x3, x7) + +inst_81: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x061 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x091 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x004 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7861; op2val:0x3891; +op3val:0x6c04; valaddr_reg:x2; val_offset:162*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x2, 162*FLEN/8, x6, x3, x7) + +inst_82: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x061 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x091 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x004 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7861; op2val:0x3891; +op3val:0x6c04; valaddr_reg:x2; val_offset:165*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x2, 165*FLEN/8, x6, x3, x7) + +inst_83: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x061 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x091 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x004 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7861; op2val:0x3891; +op3val:0x6c04; valaddr_reg:x2; val_offset:168*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 168*FLEN/8, x6, x3, x7) + +inst_84: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x061 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x091 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x004 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7861; op2val:0x3891; +op3val:0x6c04; valaddr_reg:x2; val_offset:171*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x2, 171*FLEN/8, x6, x3, x7) + +inst_85: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3a0 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1e8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x296 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ba0; op2val:0xb9e8; +op3val:0x7296; valaddr_reg:x2; val_offset:174*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 174*FLEN/8, x6, x3, x7) + +inst_86: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3a0 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1e8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x296 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ba0; op2val:0xb9e8; +op3val:0x7296; valaddr_reg:x2; val_offset:177*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x2, 177*FLEN/8, x6, x3, x7) + +inst_87: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3a0 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1e8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x296 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ba0; op2val:0xb9e8; +op3val:0x7296; valaddr_reg:x2; val_offset:180*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x2, 180*FLEN/8, x6, x3, x7) + +inst_88: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3a0 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1e8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x296 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ba0; op2val:0xb9e8; +op3val:0x7296; valaddr_reg:x2; val_offset:183*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 183*FLEN/8, x6, x3, x7) + +inst_89: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3a0 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1e8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x296 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ba0; op2val:0xb9e8; +op3val:0x7296; valaddr_reg:x2; val_offset:186*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x2, 186*FLEN/8, x6, x3, x7) + +inst_90: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x170 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x174 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2d6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7970; op2val:0x3d74; +op3val:0x76d6; valaddr_reg:x2; val_offset:189*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 189*FLEN/8, x6, x3, x7) + +inst_91: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x170 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x174 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2d6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7970; op2val:0x3d74; +op3val:0x76d6; valaddr_reg:x2; val_offset:192*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x2, 192*FLEN/8, x6, x3, x7) + +inst_92: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x170 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x174 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2d6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7970; op2val:0x3d74; +op3val:0x76d6; valaddr_reg:x2; val_offset:195*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x2, 195*FLEN/8, x6, x3, x7) + +inst_93: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x170 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x174 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2d6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7970; op2val:0x3d74; +op3val:0x76d6; valaddr_reg:x2; val_offset:198*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 198*FLEN/8, x6, x3, x7) + +inst_94: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x170 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x174 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2d6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7970; op2val:0x3d74; +op3val:0x76d6; valaddr_reg:x2; val_offset:201*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x2, 201*FLEN/8, x6, x3, x7) + +inst_95: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x106 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x05b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0ae and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7506; op2val:0x345b; +op3val:0x78ae; valaddr_reg:x2; val_offset:204*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 204*FLEN/8, x6, x3, x7) + +inst_96: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x106 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x05b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0ae and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7506; op2val:0x345b; +op3val:0x78ae; valaddr_reg:x2; val_offset:207*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x2, 207*FLEN/8, x6, x3, x7) + +inst_97: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x106 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x05b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0ae and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7506; op2val:0x345b; +op3val:0x78ae; valaddr_reg:x2; val_offset:210*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x2, 210*FLEN/8, x6, x3, x7) + +inst_98: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x106 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x05b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0ae and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7506; op2val:0x345b; +op3val:0x78ae; valaddr_reg:x2; val_offset:213*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 213*FLEN/8, x6, x3, x7) + +inst_99: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x106 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x05b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0ae and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7506; op2val:0x345b; +op3val:0x78ae; valaddr_reg:x2; val_offset:216*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x2, 216*FLEN/8, x6, x3, x7) + +inst_100: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x33f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1bc and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0cb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x773f; op2val:0x41bc; +op3val:0x74cb; valaddr_reg:x2; val_offset:219*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 219*FLEN/8, x6, x3, x7) + +inst_101: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x33f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1bc and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0cb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x773f; op2val:0x41bc; +op3val:0x74cb; valaddr_reg:x2; val_offset:222*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x2, 222*FLEN/8, x6, x3, x7) + +inst_102: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x33f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1bc and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0cb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x773f; op2val:0x41bc; +op3val:0x74cb; valaddr_reg:x2; val_offset:225*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x2, 225*FLEN/8, x6, x3, x7) + +inst_103: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x33f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1bc and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0cb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x773f; op2val:0x41bc; +op3val:0x74cb; valaddr_reg:x2; val_offset:228*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 228*FLEN/8, x6, x3, x7) + +inst_104: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x33f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1bc and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0cb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x773f; op2val:0x41bc; +op3val:0x74cb; valaddr_reg:x2; val_offset:231*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x2, 231*FLEN/8, x6, x3, x7) + +inst_105: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25a and fs2 == 1 and fe2 == 0x0d and fm2 == 0x210 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x196 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5a; op2val:0xb610; +op3val:0x7996; valaddr_reg:x2; val_offset:234*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 234*FLEN/8, x6, x3, x7) + +inst_106: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25a and fs2 == 1 and fe2 == 0x0d and fm2 == 0x210 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x196 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5a; op2val:0xb610; +op3val:0x7996; valaddr_reg:x2; val_offset:237*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x2, 237*FLEN/8, x6, x3, x7) + +inst_107: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25a and fs2 == 1 and fe2 == 0x0d and fm2 == 0x210 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x196 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5a; op2val:0xb610; +op3val:0x7996; valaddr_reg:x2; val_offset:240*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x2, 240*FLEN/8, x6, x3, x7) + +inst_108: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25a and fs2 == 1 and fe2 == 0x0d and fm2 == 0x210 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x196 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5a; op2val:0xb610; +op3val:0x7996; valaddr_reg:x2; val_offset:243*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 243*FLEN/8, x6, x3, x7) + +inst_109: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25a and fs2 == 1 and fe2 == 0x0d and fm2 == 0x210 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x196 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5a; op2val:0xb610; +op3val:0x7996; valaddr_reg:x2; val_offset:246*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x2, 246*FLEN/8, x6, x3, x7) + +inst_110: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3ce and fs2 == 0 and fe2 == 0x12 and fm2 == 0x145 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x097 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73ce; op2val:0x4945; +op3val:0x7897; valaddr_reg:x2; val_offset:249*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 249*FLEN/8, x6, x3, x7) + +inst_111: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3ce and fs2 == 0 and fe2 == 0x12 and fm2 == 0x145 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x097 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73ce; op2val:0x4945; +op3val:0x7897; valaddr_reg:x2; val_offset:252*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x2, 252*FLEN/8, x6, x3, x7) + +inst_112: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3ce and fs2 == 0 and fe2 == 0x12 and fm2 == 0x145 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x097 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73ce; op2val:0x4945; +op3val:0x7897; valaddr_reg:x2; val_offset:255*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x2, 255*FLEN/8, x6, x3, x7) + +inst_113: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3ce and fs2 == 0 and fe2 == 0x12 and fm2 == 0x145 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x097 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73ce; op2val:0x4945; +op3val:0x7897; valaddr_reg:x2; val_offset:258*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 258*FLEN/8, x6, x3, x7) + +inst_114: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3ce and fs2 == 0 and fe2 == 0x12 and fm2 == 0x145 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x097 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73ce; op2val:0x4945; +op3val:0x7897; valaddr_reg:x2; val_offset:261*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x2, 261*FLEN/8, x6, x3, x7) + +inst_115: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x033 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x048 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7833; op2val:0xc048; +op3val:0x7aff; valaddr_reg:x2; val_offset:264*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 264*FLEN/8, x6, x3, x7) + +inst_116: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x033 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x048 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7833; op2val:0xc048; +op3val:0x7aff; valaddr_reg:x2; val_offset:267*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x2, 267*FLEN/8, x6, x3, x7) + +inst_117: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x033 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x048 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7833; op2val:0xc048; +op3val:0x7aff; valaddr_reg:x2; val_offset:270*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x2, 270*FLEN/8, x6, x3, x7) + +inst_118: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x033 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x048 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7833; op2val:0xc048; +op3val:0x7aff; valaddr_reg:x2; val_offset:273*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 273*FLEN/8, x6, x3, x7) + +inst_119: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x033 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x048 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7833; op2val:0xc048; +op3val:0x7aff; valaddr_reg:x2; val_offset:276*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x2, 276*FLEN/8, x6, x3, x7) + +inst_120: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1e0 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x09a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79d5; op2val:0x45e0; +op3val:0x749a; valaddr_reg:x2; val_offset:279*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 279*FLEN/8, x6, x3, x7) + +inst_121: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1e0 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x09a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79d5; op2val:0x45e0; +op3val:0x749a; valaddr_reg:x2; val_offset:282*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x2, 282*FLEN/8, x6, x3, x7) + +inst_122: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1e0 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x09a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79d5; op2val:0x45e0; +op3val:0x749a; valaddr_reg:x2; val_offset:285*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x2, 285*FLEN/8, x6, x3, x7) + +inst_123: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1e0 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x09a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79d5; op2val:0x45e0; +op3val:0x749a; valaddr_reg:x2; val_offset:288*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 288*FLEN/8, x6, x3, x7) + +inst_124: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1e0 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x09a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79d5; op2val:0x45e0; +op3val:0x749a; valaddr_reg:x2; val_offset:291*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x2, 291*FLEN/8, x6, x3, x7) + +inst_125: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d6 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3eb and fs3 == 0 and fe3 == 0x1b and fm3 == 0x38d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd6; op2val:0xc3eb; +op3val:0x6f8d; valaddr_reg:x2; val_offset:294*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 294*FLEN/8, x6, x3, x7) + +inst_126: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d6 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3eb and fs3 == 0 and fe3 == 0x1b and fm3 == 0x38d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd6; op2val:0xc3eb; +op3val:0x6f8d; valaddr_reg:x2; val_offset:297*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x2, 297*FLEN/8, x6, x3, x7) + +inst_127: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d6 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3eb and fs3 == 0 and fe3 == 0x1b and fm3 == 0x38d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd6; op2val:0xc3eb; +op3val:0x6f8d; valaddr_reg:x2; val_offset:300*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x2, 300*FLEN/8, x6, x3, x7) + +inst_128: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d6 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3eb and fs3 == 0 and fe3 == 0x1b and fm3 == 0x38d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd6; op2val:0xc3eb; +op3val:0x6f8d; valaddr_reg:x2; val_offset:303*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 303*FLEN/8, x6, x3, x7) + +inst_129: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d6 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3eb and fs3 == 0 and fe3 == 0x1b and fm3 == 0x38d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd6; op2val:0xc3eb; +op3val:0x6f8d; valaddr_reg:x2; val_offset:306*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x2, 306*FLEN/8, x6, x3, x7) + +inst_130: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2af and fs2 == 0 and fe2 == 0x13 and fm2 == 0x13c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x20d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76af; op2val:0x4d3c; +op3val:0x7a0d; valaddr_reg:x2; val_offset:309*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 309*FLEN/8, x6, x3, x7) + +inst_131: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2af and fs2 == 0 and fe2 == 0x13 and fm2 == 0x13c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x20d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76af; op2val:0x4d3c; +op3val:0x7a0d; valaddr_reg:x2; val_offset:312*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x2, 312*FLEN/8, x6, x3, x7) + +inst_132: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2af and fs2 == 0 and fe2 == 0x13 and fm2 == 0x13c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x20d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76af; op2val:0x4d3c; +op3val:0x7a0d; valaddr_reg:x2; val_offset:315*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x2, 315*FLEN/8, x6, x3, x7) + +inst_133: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2af and fs2 == 0 and fe2 == 0x13 and fm2 == 0x13c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x20d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76af; op2val:0x4d3c; +op3val:0x7a0d; valaddr_reg:x2; val_offset:318*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 318*FLEN/8, x6, x3, x7) + +inst_134: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2af and fs2 == 0 and fe2 == 0x13 and fm2 == 0x13c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x20d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76af; op2val:0x4d3c; +op3val:0x7a0d; valaddr_reg:x2; val_offset:321*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x2, 321*FLEN/8, x6, x3, x7) + +inst_135: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0dc and fs2 == 1 and fe2 == 0x14 and fm2 == 0x22d and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3d1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70dc; op2val:0xd22d; +op3val:0x77d1; valaddr_reg:x2; val_offset:324*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 324*FLEN/8, x6, x3, x7) + +inst_136: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0dc and fs2 == 1 and fe2 == 0x14 and fm2 == 0x22d and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3d1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70dc; op2val:0xd22d; +op3val:0x77d1; valaddr_reg:x2; val_offset:327*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x2, 327*FLEN/8, x6, x3, x7) + +inst_137: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0dc and fs2 == 1 and fe2 == 0x14 and fm2 == 0x22d and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3d1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70dc; op2val:0xd22d; +op3val:0x77d1; valaddr_reg:x2; val_offset:330*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x2, 330*FLEN/8, x6, x3, x7) + +inst_138: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0dc and fs2 == 1 and fe2 == 0x14 and fm2 == 0x22d and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3d1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70dc; op2val:0xd22d; +op3val:0x77d1; valaddr_reg:x2; val_offset:333*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 333*FLEN/8, x6, x3, x7) + +inst_139: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0dc and fs2 == 1 and fe2 == 0x14 and fm2 == 0x22d and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3d1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70dc; op2val:0xd22d; +op3val:0x77d1; valaddr_reg:x2; val_offset:336*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x2, 336*FLEN/8, x6, x3, x7) + +inst_140: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x12d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x31b and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x752d; op2val:0x431b; +op3val:0x70d3; valaddr_reg:x2; val_offset:339*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 339*FLEN/8, x6, x3, x7) + +inst_141: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x12d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x31b and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x752d; op2val:0x431b; +op3val:0x70d3; valaddr_reg:x2; val_offset:342*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x2, 342*FLEN/8, x6, x3, x7) + +inst_142: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x12d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x31b and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x752d; op2val:0x431b; +op3val:0x70d3; valaddr_reg:x2; val_offset:345*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 345*FLEN/8, x6, x3, x7) + +inst_143: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x12d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x31b and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x752d; op2val:0x431b; +op3val:0x70d3; valaddr_reg:x2; val_offset:348*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x2, 348*FLEN/8, x6, x3, x7) +RVTEST_SIGBASE(x3,signature_x3_1) + +inst_144: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x134 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1b3 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x0a2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7934; op2val:0xbdb3; +op3val:0x6ca2; valaddr_reg:x2; val_offset:351*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 351*FLEN/8, x6, x3, x7) + +inst_145: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x134 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1b3 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x0a2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7934; op2val:0xbdb3; +op3val:0x6ca2; valaddr_reg:x2; val_offset:354*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x2, 354*FLEN/8, x6, x3, x7) + +inst_146: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x048 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x118 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1d9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7848; op2val:0x4118; +op3val:0x75d9; valaddr_reg:x2; val_offset:357*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x2, 357*FLEN/8, x6, x3, x7) + +inst_147: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x048 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x118 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1d9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7848; op2val:0x4118; +op3val:0x75d9; valaddr_reg:x2; val_offset:360*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x2, 360*FLEN/8, x6, x3, x7) + +inst_148: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x36c and fs2 == 1 and fe2 == 0x12 and fm2 == 0x03e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6b6c; op2val:0xc83e; +op3val:0x780e; valaddr_reg:x2; val_offset:363*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x2, 363*FLEN/8, x6, x3, x7) + +inst_149: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x0cc and fs2 == 0 and fe2 == 0x14 and fm2 == 0x0c7 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2ef and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x68cc; op2val:0x50c7; +op3val:0x76ef; valaddr_reg:x2; val_offset:366*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x2, 366*FLEN/8, x6, x3, x7) + +inst_150: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x078 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x281 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x1cd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c78; op2val:0xca81; +op3val:0x6dcd; valaddr_reg:x2; val_offset:369*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 369*FLEN/8, x6, x3, x7) + +inst_151: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2ca and fs2 == 0 and fe2 == 0x11 and fm2 == 0x04d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x29c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76ca; op2val:0x444d; +op3val:0x7a9c; valaddr_reg:x2; val_offset:372*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x2, 372*FLEN/8, x6, x3, x7) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(29997,32,FLEN) +NAN_BOXED(29997,32,FLEN) +NAN_BOXED(29997,32,FLEN) +NAN_BOXED(29997,32,FLEN) +NAN_BOXED(17179,32,FLEN) +NAN_BOXED(28883,32,FLEN) +NAN_BOXED(29997,32,FLEN) +NAN_BOXED(29997,32,FLEN) +NAN_BOXED(28883,32,FLEN) +NAN_BOXED(29997,32,FLEN) +NAN_BOXED(17179,32,FLEN) +NAN_BOXED(17179,32,FLEN) +NAN_BOXED(29997,32,FLEN) +NAN_BOXED(29997,32,FLEN) +NAN_BOXED(29997,32,FLEN) +NAN_BOXED(31028,32,FLEN) +NAN_BOXED(48563,16,FLEN) +NAN_BOXED(27810,32,FLEN) +NAN_BOXED(31028,32,FLEN) +NAN_BOXED(48563,16,FLEN) +NAN_BOXED(27810,32,FLEN) +NAN_BOXED(31028,32,FLEN) +NAN_BOXED(48563,16,FLEN) +NAN_BOXED(27810,32,FLEN) +NAN_BOXED(31028,32,FLEN) +NAN_BOXED(48563,16,FLEN) +NAN_BOXED(48563,32,FLEN) +NAN_BOXED(31028,32,FLEN) +NAN_BOXED(31028,16,FLEN) +NAN_BOXED(27810,32,FLEN) +NAN_BOXED(30792,32,FLEN) +NAN_BOXED(16664,32,FLEN) +NAN_BOXED(30792,32,FLEN) +NAN_BOXED(30792,32,FLEN) +NAN_BOXED(16664,32,FLEN) +NAN_BOXED(30792,32,FLEN) +NAN_BOXED(30792,32,FLEN) +NAN_BOXED(16664,32,FLEN) +NAN_BOXED(30169,32,FLEN) +test_dataset_1: +NAN_BOXED(30792,32,FLEN) +NAN_BOXED(16664,32,FLEN) +NAN_BOXED(30169,32,FLEN) +NAN_BOXED(30792,32,FLEN) +NAN_BOXED(16664,32,FLEN) +NAN_BOXED(30169,32,FLEN) +NAN_BOXED(27500,32,FLEN) +NAN_BOXED(51262,16,FLEN) +NAN_BOXED(30734,32,FLEN) +NAN_BOXED(27500,32,FLEN) +NAN_BOXED(51262,16,FLEN) +NAN_BOXED(30734,32,FLEN) +NAN_BOXED(27500,32,FLEN) +NAN_BOXED(51262,16,FLEN) +NAN_BOXED(30734,32,FLEN) +NAN_BOXED(27500,32,FLEN) +NAN_BOXED(51262,16,FLEN) +NAN_BOXED(30734,32,FLEN) +NAN_BOXED(27500,32,FLEN) +NAN_BOXED(51262,16,FLEN) +NAN_BOXED(30734,32,FLEN) +NAN_BOXED(26828,32,FLEN) +NAN_BOXED(20679,32,FLEN) +NAN_BOXED(30447,32,FLEN) +NAN_BOXED(26828,32,FLEN) +NAN_BOXED(20679,32,FLEN) +NAN_BOXED(30447,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(20679,32,FLEN) +NAN_BOXED(30447,32,FLEN) +NAN_BOXED(26828,32,FLEN) +NAN_BOXED(20679,32,FLEN) +NAN_BOXED(30447,32,FLEN) +NAN_BOXED(26828,32,FLEN) +NAN_BOXED(20679,32,FLEN) +NAN_BOXED(30447,32,FLEN) +NAN_BOXED(27768,32,FLEN) +NAN_BOXED(51841,16,FLEN) +NAN_BOXED(28109,32,FLEN) +NAN_BOXED(27768,32,FLEN) +NAN_BOXED(51841,16,FLEN) +NAN_BOXED(28109,32,FLEN) +test_dataset_2: +NAN_BOXED(27768,16,FLEN) +NAN_BOXED(51841,16,FLEN) +NAN_BOXED(28109,16,FLEN) +NAN_BOXED(27768,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(28109,16,FLEN) +NAN_BOXED(27768,16,FLEN) +NAN_BOXED(51841,16,FLEN) +NAN_BOXED(28109,16,FLEN) +NAN_BOXED(30410,16,FLEN) +NAN_BOXED(17485,16,FLEN) +NAN_BOXED(31388,16,FLEN) +NAN_BOXED(30410,16,FLEN) +NAN_BOXED(17485,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(30410,16,FLEN) +NAN_BOXED(17485,16,FLEN) +NAN_BOXED(31388,16,FLEN) +NAN_BOXED(30410,16,FLEN) +NAN_BOXED(17485,16,FLEN) +NAN_BOXED(31388,16,FLEN) +NAN_BOXED(30410,16,FLEN) +NAN_BOXED(17485,16,FLEN) +NAN_BOXED(31388,16,FLEN) +NAN_BOXED(28651,16,FLEN) +NAN_BOXED(50758,16,FLEN) +NAN_BOXED(29475,16,FLEN) +NAN_BOXED(28651,16,FLEN) +NAN_BOXED(50758,16,FLEN) +NAN_BOXED(29475,16,FLEN) +NAN_BOXED(28651,16,FLEN) +NAN_BOXED(50758,16,FLEN) +NAN_BOXED(29475,16,FLEN) +NAN_BOXED(28651,16,FLEN) +NAN_BOXED(50758,16,FLEN) +NAN_BOXED(29475,16,FLEN) +NAN_BOXED(28651,16,FLEN) +NAN_BOXED(50758,16,FLEN) +NAN_BOXED(29475,16,FLEN) +NAN_BOXED(30980,16,FLEN) +NAN_BOXED(16949,16,FLEN) +NAN_BOXED(31635,16,FLEN) +NAN_BOXED(30980,16,FLEN) +NAN_BOXED(16949,16,FLEN) +NAN_BOXED(31635,16,FLEN) +NAN_BOXED(30980,16,FLEN) +NAN_BOXED(16949,16,FLEN) +NAN_BOXED(31635,16,FLEN) +NAN_BOXED(30980,16,FLEN) +NAN_BOXED(16949,16,FLEN) +NAN_BOXED(31635,16,FLEN) +NAN_BOXED(30980,16,FLEN) +NAN_BOXED(16949,16,FLEN) +NAN_BOXED(31635,16,FLEN) +NAN_BOXED(30877,16,FLEN) +NAN_BOXED(48174,16,FLEN) +NAN_BOXED(30296,16,FLEN) +NAN_BOXED(30877,16,FLEN) +NAN_BOXED(48174,16,FLEN) +NAN_BOXED(30296,16,FLEN) +NAN_BOXED(30877,16,FLEN) +NAN_BOXED(48174,16,FLEN) +NAN_BOXED(30296,16,FLEN) +NAN_BOXED(30877,16,FLEN) +NAN_BOXED(48174,16,FLEN) +NAN_BOXED(30296,16,FLEN) +NAN_BOXED(30877,16,FLEN) +NAN_BOXED(48174,16,FLEN) +NAN_BOXED(30296,16,FLEN) +NAN_BOXED(31694,16,FLEN) +NAN_BOXED(15433,16,FLEN) +NAN_BOXED(27126,16,FLEN) +NAN_BOXED(31694,16,FLEN) +NAN_BOXED(15433,16,FLEN) +NAN_BOXED(27126,16,FLEN) +NAN_BOXED(31694,16,FLEN) +NAN_BOXED(15433,16,FLEN) +NAN_BOXED(27126,16,FLEN) +NAN_BOXED(31694,16,FLEN) +NAN_BOXED(15433,16,FLEN) +NAN_BOXED(27126,16,FLEN) +NAN_BOXED(31694,16,FLEN) +NAN_BOXED(15433,16,FLEN) +NAN_BOXED(27126,16,FLEN) +NAN_BOXED(31453,16,FLEN) +NAN_BOXED(47774,16,FLEN) +NAN_BOXED(29857,16,FLEN) +NAN_BOXED(31453,16,FLEN) +NAN_BOXED(47774,16,FLEN) +NAN_BOXED(29857,16,FLEN) +NAN_BOXED(31453,16,FLEN) +NAN_BOXED(47774,16,FLEN) +NAN_BOXED(29857,16,FLEN) +NAN_BOXED(31453,16,FLEN) +NAN_BOXED(47774,16,FLEN) +NAN_BOXED(29857,16,FLEN) +NAN_BOXED(31453,16,FLEN) +NAN_BOXED(47774,16,FLEN) +NAN_BOXED(29857,16,FLEN) +NAN_BOXED(28829,16,FLEN) +NAN_BOXED(18367,16,FLEN) +NAN_BOXED(28553,16,FLEN) +NAN_BOXED(28829,16,FLEN) +NAN_BOXED(18367,16,FLEN) +NAN_BOXED(28553,16,FLEN) +NAN_BOXED(28829,16,FLEN) +NAN_BOXED(18367,16,FLEN) +NAN_BOXED(28553,16,FLEN) +NAN_BOXED(28829,16,FLEN) +NAN_BOXED(18367,16,FLEN) +NAN_BOXED(28553,16,FLEN) +NAN_BOXED(28829,16,FLEN) +NAN_BOXED(18367,16,FLEN) +NAN_BOXED(28553,16,FLEN) +NAN_BOXED(29934,16,FLEN) +NAN_BOXED(47300,16,FLEN) +NAN_BOXED(31366,16,FLEN) +NAN_BOXED(29934,16,FLEN) +NAN_BOXED(47300,16,FLEN) +NAN_BOXED(31366,16,FLEN) +NAN_BOXED(29934,16,FLEN) +NAN_BOXED(47300,16,FLEN) +NAN_BOXED(31366,16,FLEN) +NAN_BOXED(29934,16,FLEN) +NAN_BOXED(47300,16,FLEN) +NAN_BOXED(31366,16,FLEN) +NAN_BOXED(29934,16,FLEN) +NAN_BOXED(47300,16,FLEN) +NAN_BOXED(31366,16,FLEN) +NAN_BOXED(29127,16,FLEN) +NAN_BOXED(17361,16,FLEN) +NAN_BOXED(30886,16,FLEN) +NAN_BOXED(29127,16,FLEN) +NAN_BOXED(17361,16,FLEN) +NAN_BOXED(30886,16,FLEN) +NAN_BOXED(29127,16,FLEN) +NAN_BOXED(17361,16,FLEN) +NAN_BOXED(30886,16,FLEN) +NAN_BOXED(29127,16,FLEN) +NAN_BOXED(17361,16,FLEN) +NAN_BOXED(30886,16,FLEN) +NAN_BOXED(29127,16,FLEN) +NAN_BOXED(17361,16,FLEN) +NAN_BOXED(30886,16,FLEN) +NAN_BOXED(31003,16,FLEN) +NAN_BOXED(13874,16,FLEN) +NAN_BOXED(30196,16,FLEN) +NAN_BOXED(31003,16,FLEN) +NAN_BOXED(13874,16,FLEN) +NAN_BOXED(30196,16,FLEN) +NAN_BOXED(31003,16,FLEN) +NAN_BOXED(13874,16,FLEN) +NAN_BOXED(30196,16,FLEN) +NAN_BOXED(31003,16,FLEN) +NAN_BOXED(13874,16,FLEN) +NAN_BOXED(30196,16,FLEN) +NAN_BOXED(31003,16,FLEN) +NAN_BOXED(13874,16,FLEN) +NAN_BOXED(30196,16,FLEN) +NAN_BOXED(30817,16,FLEN) +NAN_BOXED(14481,16,FLEN) +NAN_BOXED(27652,16,FLEN) +NAN_BOXED(30817,16,FLEN) +NAN_BOXED(14481,16,FLEN) +NAN_BOXED(27652,16,FLEN) +NAN_BOXED(30817,16,FLEN) +NAN_BOXED(14481,16,FLEN) +NAN_BOXED(27652,16,FLEN) +NAN_BOXED(30817,16,FLEN) +NAN_BOXED(14481,16,FLEN) +NAN_BOXED(27652,16,FLEN) +NAN_BOXED(30817,16,FLEN) +NAN_BOXED(14481,16,FLEN) +NAN_BOXED(27652,16,FLEN) +NAN_BOXED(27552,16,FLEN) +NAN_BOXED(47592,16,FLEN) +NAN_BOXED(29334,16,FLEN) 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+NAN_BOXED(20679,16,FLEN) +NAN_BOXED(30447,16,FLEN) +NAN_BOXED(27768,16,FLEN) +NAN_BOXED(51841,16,FLEN) +NAN_BOXED(28109,16,FLEN) +NAN_BOXED(30410,16,FLEN) +NAN_BOXED(17485,16,FLEN) +NAN_BOXED(31388,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x6_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x6_1: + .fill 32*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x3_0: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x3_1: + .fill 16*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fmsub_b5-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fmsub_b5-01.S new file mode 100644 index 000000000..1e0e6e153 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fmsub_b5-01.S @@ -0,0 +1,2421 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 05:33:17 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fmsub.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fmsub.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fmsub_b5 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fmsub_b5) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x11,test_dataset_0) +RVTEST_SIGBASE(x4,signature_x4_1) + +inst_0: +// rs1 == rs2 == rs3 != rd, rs1==x9, rs2==x9, rs3==x9, rd==x20,fs1 == 0 and fe1 == 0x1d and fm1 == 0x12d and fs2 == 0 and fe2 == 0x0d and fm2 == 0x374 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x9; op2:x9; op3:x9; dest:x20; op1val:0x752d; op2val:0x752d; +op3val:0x752d; valaddr_reg:x11; val_offset:0*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x20, x9, x9, x9, dyn, 0, 0, x11, 0*FLEN/8, x13, x4, x7) + +inst_1: +// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==x26, rs2==x24, rs3==x11, rd==x16,fs1 == 0 and fe1 == 0x1d and fm1 == 0x12d and fs2 == 0 and fe2 == 0x0d and fm2 == 0x374 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x26; op2:x24; op3:x11; dest:x16; op1val:0x752d; op2val:0x3774; +op3val:0x70d3; valaddr_reg:x11; val_offset:3*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x16, x26, x24, x11, dyn, 32, 0, x11, 3*FLEN/8, x13, x4, x7) + +inst_2: +// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==x10, rs2==x10, rs3==x8, rd==x5,fs1 == 0 and fe1 == 0x1d and fm1 == 0x12d and fs2 == 0 and fe2 == 0x0d and fm2 == 0x374 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x10; op2:x10; op3:x8; dest:x5; op1val:0x752d; op2val:0x752d; +op3val:0x70d3; valaddr_reg:x11; val_offset:6*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x5, x10, x10, x8, dyn, 64, 0, x11, 6*FLEN/8, x13, x4, x7) + +inst_3: +// rd == rs2 == rs3 != rs1, rs1==x1, rs2==x25, rs3==x25, rd==x25,fs1 == 0 and fe1 == 0x1d and fm1 == 0x12d and fs2 == 0 and fe2 == 0x0d and fm2 == 0x374 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x1; op2:x25; op3:x25; dest:x25; op1val:0x752d; op2val:0x3774; +op3val:0x3774; valaddr_reg:x11; val_offset:9*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x25, x1, x25, x25, dyn, 96, 0, x11, 9*FLEN/8, x13, x4, x7) + +inst_4: +// rs1 == rs2 == rs3 == rd, rs1==x2, rs2==x2, rs3==x2, rd==x2,fs1 == 0 and fe1 == 0x1d and fm1 == 0x12d and fs2 == 0 and fe2 == 0x0d and fm2 == 0x374 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x2; op2:x2; op3:x2; dest:x2; op1val:0x752d; op2val:0x752d; +op3val:0x752d; valaddr_reg:x11; val_offset:12*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x2, x2, x2, x2, dyn, 128, 0, x11, 12*FLEN/8, x13, x4, x7) + +inst_5: +// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==x8, rs2==x0, rs3==x27, rd==x0,fs1 == 0 and fe1 == 0x1e and fm1 == 0x134 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x31f and fs3 == 0 and fe3 == 0x1b and fm3 == 0x0a2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x8; op2:x0; op3:x27; dest:x0; op1val:0x7934; op2val:0x0; +op3val:0x6ca2; valaddr_reg:x11; val_offset:15*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x0, x8, x0, x27, dyn, 0, 0, x11, 15*FLEN/8, x13, x4, x7) + +inst_6: +// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==x17, rs2==x22, rs3==x30, rd==x30,fs1 == 0 and fe1 == 0x1e and fm1 == 0x134 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x31f and fs3 == 0 and fe3 == 0x1b and fm3 == 0x0a2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x17; op2:x22; op3:x30; dest:x30; op1val:0x7934; op2val:0x2f1f; +op3val:0x6ca2; valaddr_reg:x11; val_offset:18*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x30, x17, x22, x30, dyn, 32, 0, x11, 18*FLEN/8, x13, x4, x7) + +inst_7: +// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==x6, rs2==x29, rs3==x3, rd==x6,fs1 == 0 and fe1 == 0x1e and fm1 == 0x134 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x31f and fs3 == 0 and fe3 == 0x1b and fm3 == 0x0a2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x6; op2:x29; op3:x3; dest:x6; op1val:0x7934; op2val:0x2f1f; +op3val:0x6ca2; valaddr_reg:x11; val_offset:21*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x6, x6, x29, x3, dyn, 64, 0, x11, 21*FLEN/8, x13, x4, x7) + +inst_8: +// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==x15, rs2==x18, rs3==x18, rd==x27,fs1 == 0 and fe1 == 0x1e and fm1 == 0x134 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x31f and fs3 == 0 and fe3 == 0x1b and fm3 == 0x0a2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x15; op2:x18; op3:x18; dest:x27; op1val:0x7934; op2val:0x2f1f; +op3val:0x2f1f; valaddr_reg:x11; val_offset:24*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x27, x15, x18, x18, dyn, 96, 0, x11, 24*FLEN/8, x13, x4, x7) + +inst_9: +// rs1 == rs2 == rd != rs3, rs1==x3, rs2==x3, rs3==x19, rd==x3,fs1 == 0 and fe1 == 0x1e and fm1 == 0x134 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x31f and fs3 == 0 and fe3 == 0x1b and fm3 == 0x0a2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x3; op2:x3; op3:x19; dest:x3; op1val:0x7934; op2val:0x7934; +op3val:0x6ca2; valaddr_reg:x11; val_offset:27*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x3, x3, x3, x19, dyn, 128, 0, x11, 27*FLEN/8, x13, x4, x7) + +inst_10: +// rs1 == rd == rs3 != rs2, rs1==x12, rs2==x30, rs3==x12, rd==x12,fs1 == 0 and fe1 == 0x1e and fm1 == 0x048 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x175 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1d9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x12; op2:x30; op3:x12; dest:x12; op1val:0x7848; op2val:0x3975; +op3val:0x7848; valaddr_reg:x11; val_offset:30*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x12, x12, x30, x12, dyn, 0, 0, x11, 30*FLEN/8, x13, x4, x7) + +inst_11: +// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==x23, rs2==x31, rs3==x23, rd==x14,fs1 == 0 and fe1 == 0x1e and fm1 == 0x048 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x175 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1d9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x23; op2:x31; op3:x23; dest:x14; op1val:0x7848; op2val:0x3975; +op3val:0x7848; valaddr_reg:x11; val_offset:33*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x14, x23, x31, x23, dyn, 32, 0, x11, 33*FLEN/8, x13, x4, x7) +RVTEST_VALBASEUPD(x12,test_dataset_1) + +inst_12: +// rs1==x7, rs2==x8, rs3==x26, rd==x13,fs1 == 0 and fe1 == 0x1e and fm1 == 0x048 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x175 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1d9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x7; op2:x8; op3:x26; dest:x13; op1val:0x7848; op2val:0x3975; +op3val:0x75d9; valaddr_reg:x12; val_offset:0*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x13, x7, x8, x26, dyn, 64, 0, x12, 0*FLEN/8, x14, x4, x3) +RVTEST_SIGBASE(x2,signature_x2_0) + +inst_13: +// rs1==x20, rs2==x13, rs3==x4, rd==x22,fs1 == 0 and fe1 == 0x1e and fm1 == 0x048 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x175 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1d9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x20; op2:x13; op3:x4; dest:x22; op1val:0x7848; op2val:0x3975; +op3val:0x75d9; valaddr_reg:x12; val_offset:3*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x22, x20, x13, x4, dyn, 96, 0, x12, 3*FLEN/8, x14, x2, x3) + +inst_14: +// rs1==x0, rs2==x20, rs3==x28, rd==x26,fs1 == 0 and fe1 == 0x1e and fm1 == 0x048 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x175 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1d9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x0; op2:x20; op3:x28; dest:x26; op1val:0x0; op2val:0x3975; +op3val:0x75d9; valaddr_reg:x12; val_offset:6*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x26, x0, x20, x28, dyn, 128, 0, x12, 6*FLEN/8, x14, x2, x3) + +inst_15: +// rs1==x21, rs2==x17, rs3==x13, rd==x4,fs1 == 0 and fe1 == 0x1a and fm1 == 0x36c and fs2 == 0 and fe2 == 0x12 and fm2 == 0x05f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x21; op2:x17; op3:x13; dest:x4; op1val:0x6b6c; op2val:0x485f; +op3val:0x780e; valaddr_reg:x12; val_offset:9*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x4, x21, x17, x13, dyn, 0, 0, x12, 9*FLEN/8, x14, x2, x3) + +inst_16: +// rs1==x31, rs2==x23, rs3==x7, rd==x9,fs1 == 0 and fe1 == 0x1a and fm1 == 0x36c and fs2 == 0 and fe2 == 0x12 and fm2 == 0x05f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x31; op2:x23; op3:x7; dest:x9; op1val:0x6b6c; op2val:0x485f; +op3val:0x780e; valaddr_reg:x12; val_offset:12*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x9, x31, x23, x7, dyn, 32, 0, x12, 12*FLEN/8, x14, x2, x3) + +inst_17: +// rs1==x11, rs2==x21, rs3==x10, rd==x23,fs1 == 0 and fe1 == 0x1a and fm1 == 0x36c and fs2 == 0 and fe2 == 0x12 and fm2 == 0x05f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x11; op2:x21; op3:x10; dest:x23; op1val:0x6b6c; op2val:0x485f; +op3val:0x780e; valaddr_reg:x12; val_offset:15*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x23, x11, x21, x10, dyn, 64, 0, x12, 15*FLEN/8, x14, x2, x3) + +inst_18: +// rs1==x28, rs2==x16, rs3==x31, rd==x8,fs1 == 0 and fe1 == 0x1a and fm1 == 0x36c and fs2 == 0 and fe2 == 0x12 and fm2 == 0x05f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x28; op2:x16; op3:x31; dest:x8; op1val:0x6b6c; op2val:0x485f; +op3val:0x780e; valaddr_reg:x12; val_offset:18*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x8, x28, x16, x31, dyn, 96, 0, x12, 18*FLEN/8, x14, x2, x3) + +inst_19: +// rs1==x4, rs2==x28, rs3==x0, rd==x10,fs1 == 0 and fe1 == 0x1a and fm1 == 0x36c and fs2 == 0 and fe2 == 0x12 and fm2 == 0x05f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x4; op2:x28; op3:x0; dest:x10; op1val:0x6b6c; op2val:0x485f; +op3val:0x0; valaddr_reg:x12; val_offset:21*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x10, x4, x28, x0, dyn, 128, 0, x12, 21*FLEN/8, x14, x2, x3) + +inst_20: +// rs1==x13, rs2==x1, rs3==x20, rd==x29,fs1 == 0 and fe1 == 0x1a and fm1 == 0x0cc and fs2 == 0 and fe2 == 0x12 and fm2 == 0x1c7 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2ef and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x13; op2:x1; op3:x20; dest:x29; op1val:0x68cc; op2val:0x49c7; +op3val:0x76ef; valaddr_reg:x12; val_offset:24*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x29, x13, x1, x20, dyn, 0, 0, x12, 24*FLEN/8, x14, x2, x3) + +inst_21: +// rs1==x27, rs2==x26, rs3==x6, rd==x11,fs1 == 0 and fe1 == 0x1a and fm1 == 0x0cc and fs2 == 0 and fe2 == 0x12 and fm2 == 0x1c7 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2ef and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x27; op2:x26; op3:x6; dest:x11; op1val:0x68cc; op2val:0x49c7; +op3val:0x76ef; valaddr_reg:x12; val_offset:27*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x11, x27, x26, x6, dyn, 32, 0, x12, 27*FLEN/8, x14, x2, x3) + +inst_22: +// rs1==x5, rs2==x11, rs3==x1, rd==x19,fs1 == 0 and fe1 == 0x1a and fm1 == 0x0cc and fs2 == 0 and fe2 == 0x12 and fm2 == 0x1c7 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2ef and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x5; op2:x11; op3:x1; dest:x19; op1val:0x68cc; op2val:0x49c7; +op3val:0x76ef; valaddr_reg:x12; val_offset:30*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x19, x5, x11, x1, dyn, 64, 0, x12, 30*FLEN/8, x14, x2, x3) + +inst_23: +// rs1==x18, rs2==x6, rs3==x21, rd==x31,fs1 == 0 and fe1 == 0x1a and fm1 == 0x0cc and fs2 == 0 and fe2 == 0x12 and fm2 == 0x1c7 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2ef and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x18; op2:x6; op3:x21; dest:x31; op1val:0x68cc; op2val:0x49c7; +op3val:0x76ef; valaddr_reg:x12; val_offset:33*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x18, x6, x21, dyn, 96, 0, x12, 33*FLEN/8, x14, x2, x3) +RVTEST_VALBASEUPD(x9,test_dataset_2) + +inst_24: +// rs1==x14, rs2==x12, rs3==x29, rd==x15,fs1 == 0 and fe1 == 0x1a and fm1 == 0x0cc and fs2 == 0 and fe2 == 0x12 and fm2 == 0x1c7 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2ef and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x14; op2:x12; op3:x29; dest:x15; op1val:0x68cc; op2val:0x49c7; +op3val:0x76ef; valaddr_reg:x9; val_offset:0*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x15, x14, x12, x29, dyn, 128, 0, x9, 0*FLEN/8, x11, x2, x3) +RVTEST_SIGBASE(x2,signature_x2_1) + +inst_25: +// rs1==x24, rs2==x19, rs3==x15, rd==x17,fs1 == 0 and fe1 == 0x1b and fm1 == 0x078 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x131 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x1cd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x24; op2:x19; op3:x15; dest:x17; op1val:0x6c78; op2val:0x3d31; +op3val:0x6dcd; valaddr_reg:x9; val_offset:3*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x17, x24, x19, x15, dyn, 0, 0, x9, 3*FLEN/8, x11, x2, x3) + +inst_26: +// rs1==x19, rs2==x14, rs3==x5, rd==x18,fs1 == 0 and fe1 == 0x1b and fm1 == 0x078 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x131 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x1cd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x19; op2:x14; op3:x5; dest:x18; op1val:0x6c78; op2val:0x3d31; +op3val:0x6dcd; valaddr_reg:x9; val_offset:6*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x18, x19, x14, x5, dyn, 32, 0, x9, 6*FLEN/8, x11, x2, x3) + +inst_27: +// rs1==x29, rs2==x7, rs3==x14, rd==x1,fs1 == 0 and fe1 == 0x1b and fm1 == 0x078 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x131 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x1cd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x29; op2:x7; op3:x14; dest:x1; op1val:0x6c78; op2val:0x3d31; +op3val:0x6dcd; valaddr_reg:x9; val_offset:9*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x1, x29, x7, x14, dyn, 64, 0, x9, 9*FLEN/8, x11, x2, x3) + +inst_28: +// rs1==x16, rs2==x15, rs3==x24, rd==x21,fs1 == 0 and fe1 == 0x1b and fm1 == 0x078 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x131 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x1cd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x16; op2:x15; op3:x24; dest:x21; op1val:0x6c78; op2val:0x3d31; +op3val:0x6dcd; valaddr_reg:x9; val_offset:12*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x21, x16, x15, x24, dyn, 96, 0, x9, 12*FLEN/8, x11, x2, x3) + +inst_29: +// rs1==x25, rs2==x4, rs3==x17, rd==x7,fs1 == 0 and fe1 == 0x1b and fm1 == 0x078 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x131 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x1cd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x25; op2:x4; op3:x17; dest:x7; op1val:0x6c78; op2val:0x3d31; +op3val:0x6dcd; valaddr_reg:x9; val_offset:15*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x7, x25, x4, x17, dyn, 128, 0, x9, 15*FLEN/8, x11, x2, x3) + +inst_30: +// rs1==x30, rs2==x27, rs3==x16, rd==x28,fs1 == 0 and fe1 == 0x1d and fm1 == 0x2ca and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3ca and fs3 == 0 and fe3 == 0x1e and fm3 == 0x29c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x27; op3:x16; dest:x28; op1val:0x76ca; op2val:0x3fca; +op3val:0x7a9c; valaddr_reg:x9; val_offset:18*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x28, x30, x27, x16, dyn, 0, 0, x9, 18*FLEN/8, x11, x2, x3) + +inst_31: +// rs1==x22,fs1 == 0 and fe1 == 0x1d and fm1 == 0x2ca and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3ca and fs3 == 0 and fe3 == 0x1e and fm3 == 0x29c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x22; op2:x10; op3:x4; dest:x16; op1val:0x76ca; op2val:0x3fca; +op3val:0x7a9c; valaddr_reg:x9; val_offset:21*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x16, x22, x10, x4, dyn, 32, 0, x9, 21*FLEN/8, x11, x2, x3) + +inst_32: +// rs2==x5,fs1 == 0 and fe1 == 0x1d and fm1 == 0x2ca and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3ca and fs3 == 0 and fe3 == 0x1e and fm3 == 0x29c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x24; op2:x5; op3:x4; dest:x20; op1val:0x76ca; op2val:0x3fca; +op3val:0x7a9c; valaddr_reg:x9; val_offset:24*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x20, x24, x5, x4, dyn, 64, 0, x9, 24*FLEN/8, x11, x2, x3) + +inst_33: +// rs3==x22,fs1 == 0 and fe1 == 0x1d and fm1 == 0x2ca and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3ca and fs3 == 0 and fe3 == 0x1e and fm3 == 0x29c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x8; op2:x6; op3:x22; dest:x25; op1val:0x76ca; op2val:0x3fca; +op3val:0x7a9c; valaddr_reg:x9; val_offset:27*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x25, x8, x6, x22, dyn, 96, 0, x9, 27*FLEN/8, x11, x2, x3) +RVTEST_VALBASEUPD(x1,test_dataset_3) + +inst_34: +// rd==x24,fs1 == 0 and fe1 == 0x1d and fm1 == 0x2ca and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3ca and fs3 == 0 and fe3 == 0x1e and fm3 == 0x29c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x15; op2:x21; op3:x26; dest:x24; op1val:0x76ca; op2val:0x3fca; +op3val:0x7a9c; valaddr_reg:x1; val_offset:0*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x24, x15, x21, x26, dyn, 128, 0, x1, 0*FLEN/8, x4, x2, x3) + +inst_35: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3eb and fs2 == 0 and fe2 == 0x0f and fm2 == 0x336 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x323 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6feb; op2val:0x3f36; +op3val:0x7323; valaddr_reg:x1; val_offset:3*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3*FLEN/8, x4, x2, x3) + +inst_36: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3eb and fs2 == 0 and fe2 == 0x0f and fm2 == 0x336 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x323 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6feb; op2val:0x3f36; +op3val:0x7323; valaddr_reg:x1; val_offset:6*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 6*FLEN/8, x4, x2, x3) + +inst_37: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3eb and fs2 == 0 and fe2 == 0x0f and fm2 == 0x336 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x323 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6feb; op2val:0x3f36; +op3val:0x7323; valaddr_reg:x1; val_offset:9*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 9*FLEN/8, x4, x2, x3) + +inst_38: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3eb and fs2 == 0 and fe2 == 0x0f and fm2 == 0x336 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x323 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6feb; op2val:0x3f36; +op3val:0x7323; valaddr_reg:x1; val_offset:12*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 12*FLEN/8, x4, x2, x3) + +inst_39: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3eb and fs2 == 0 and fe2 == 0x0f and fm2 == 0x336 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x323 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6feb; op2val:0x3f36; +op3val:0x7323; valaddr_reg:x1; val_offset:15*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 15*FLEN/8, x4, x2, x3) + +inst_40: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x104 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x20a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x393 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7904; op2val:0x3e0a; +op3val:0x7b93; valaddr_reg:x1; val_offset:18*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 18*FLEN/8, x4, x2, x3) + +inst_41: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x104 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x20a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x393 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7904; op2val:0x3e0a; +op3val:0x7b93; valaddr_reg:x1; val_offset:21*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 21*FLEN/8, x4, x2, x3) + +inst_42: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x104 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x20a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x393 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7904; op2val:0x3e0a; +op3val:0x7b93; valaddr_reg:x1; val_offset:24*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 24*FLEN/8, x4, x2, x3) + +inst_43: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x104 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x20a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x393 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7904; op2val:0x3e0a; +op3val:0x7b93; valaddr_reg:x1; val_offset:27*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 27*FLEN/8, x4, x2, x3) + +inst_44: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x104 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x20a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x393 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7904; op2val:0x3e0a; +op3val:0x7b93; valaddr_reg:x1; val_offset:30*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 30*FLEN/8, x4, x2, x3) + +inst_45: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x17f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x258 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x789d; op2val:0x397f; +op3val:0x7658; valaddr_reg:x1; val_offset:33*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 33*FLEN/8, x4, x2, x3) + +inst_46: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x17f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x258 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x789d; op2val:0x397f; +op3val:0x7658; valaddr_reg:x1; val_offset:36*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 36*FLEN/8, x4, x2, x3) + +inst_47: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x17f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x258 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x789d; op2val:0x397f; +op3val:0x7658; valaddr_reg:x1; val_offset:39*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 39*FLEN/8, x4, x2, x3) + +inst_48: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x17f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x258 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x789d; op2val:0x397f; +op3val:0x7658; valaddr_reg:x1; val_offset:42*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 42*FLEN/8, x4, x2, x3) + +inst_49: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x17f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x258 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x789d; op2val:0x397f; +op3val:0x7658; valaddr_reg:x1; val_offset:45*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 45*FLEN/8, x4, x2, x3) + +inst_50: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ce and fs2 == 0 and fe2 == 0x0a and fm2 == 0x21c and fs3 == 0 and fe3 == 0x1a and fm3 == 0x1f6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bce; op2val:0x2a1c; +op3val:0x69f6; valaddr_reg:x1; val_offset:48*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 48*FLEN/8, x4, x2, x3) + +inst_51: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ce and fs2 == 0 and fe2 == 0x0a and fm2 == 0x21c and fs3 == 0 and fe3 == 0x1a and fm3 == 0x1f6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bce; op2val:0x2a1c; +op3val:0x69f6; valaddr_reg:x1; val_offset:51*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 51*FLEN/8, x4, x2, x3) + +inst_52: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ce and fs2 == 0 and fe2 == 0x0a and fm2 == 0x21c and fs3 == 0 and fe3 == 0x1a and fm3 == 0x1f6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bce; op2val:0x2a1c; +op3val:0x69f6; valaddr_reg:x1; val_offset:54*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 54*FLEN/8, x4, x2, x3) + +inst_53: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ce and fs2 == 0 and fe2 == 0x0a and fm2 == 0x21c and fs3 == 0 and fe3 == 0x1a and fm3 == 0x1f6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bce; op2val:0x2a1c; +op3val:0x69f6; valaddr_reg:x1; val_offset:57*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 57*FLEN/8, x4, x2, x3) + +inst_54: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ce and fs2 == 0 and fe2 == 0x0a and fm2 == 0x21c and fs3 == 0 and fe3 == 0x1a and fm3 == 0x1f6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bce; op2val:0x2a1c; +op3val:0x69f6; valaddr_reg:x1; val_offset:60*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 60*FLEN/8, x4, x2, x3) + +inst_55: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2dd and fs2 == 0 and fe2 == 0x0d and fm2 == 0x165 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7add; op2val:0x3565; +op3val:0x74a1; valaddr_reg:x1; val_offset:63*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 63*FLEN/8, x4, x2, x3) + +inst_56: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2dd and fs2 == 0 and fe2 == 0x0d and fm2 == 0x165 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7add; op2val:0x3565; +op3val:0x74a1; valaddr_reg:x1; val_offset:66*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 66*FLEN/8, x4, x2, x3) + +inst_57: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2dd and fs2 == 0 and fe2 == 0x0d and fm2 == 0x165 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7add; op2val:0x3565; +op3val:0x74a1; valaddr_reg:x1; val_offset:69*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 69*FLEN/8, x4, x2, x3) + +inst_58: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2dd and fs2 == 0 and fe2 == 0x0d and fm2 == 0x165 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7add; op2val:0x3565; +op3val:0x74a1; valaddr_reg:x1; val_offset:72*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 72*FLEN/8, x4, x2, x3) + +inst_59: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2dd and fs2 == 0 and fe2 == 0x0d and fm2 == 0x165 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7add; op2val:0x3565; +op3val:0x74a1; valaddr_reg:x1; val_offset:75*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 75*FLEN/8, x4, x2, x3) + +inst_60: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x09d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x288 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x389 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x709d; op2val:0x3a88; +op3val:0x6f89; valaddr_reg:x1; val_offset:78*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 78*FLEN/8, x4, x2, x3) + +inst_61: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x09d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x288 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x389 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x709d; op2val:0x3a88; +op3val:0x6f89; valaddr_reg:x1; val_offset:81*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 81*FLEN/8, x4, x2, x3) + +inst_62: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x09d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x288 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x389 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x709d; op2val:0x3a88; +op3val:0x6f89; valaddr_reg:x1; val_offset:84*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 84*FLEN/8, x4, x2, x3) + +inst_63: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x09d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x288 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x389 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x709d; op2val:0x3a88; +op3val:0x6f89; valaddr_reg:x1; val_offset:87*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 87*FLEN/8, x4, x2, x3) + +inst_64: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x09d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x288 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x389 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x709d; op2val:0x3a88; +op3val:0x6f89; valaddr_reg:x1; val_offset:90*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 90*FLEN/8, x4, x2, x3) + +inst_65: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ee and fs2 == 0 and fe2 == 0x10 and fm2 == 0x14a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x286 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74ee; op2val:0x414a; +op3val:0x7a86; valaddr_reg:x1; val_offset:93*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 93*FLEN/8, x4, x2, x3) + +inst_66: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ee and fs2 == 0 and fe2 == 0x10 and fm2 == 0x14a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x286 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74ee; op2val:0x414a; +op3val:0x7a86; valaddr_reg:x1; val_offset:96*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 96*FLEN/8, x4, x2, x3) + +inst_67: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ee and fs2 == 0 and fe2 == 0x10 and fm2 == 0x14a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x286 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74ee; op2val:0x414a; +op3val:0x7a86; valaddr_reg:x1; val_offset:99*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 99*FLEN/8, x4, x2, x3) + +inst_68: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ee and fs2 == 0 and fe2 == 0x10 and fm2 == 0x14a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x286 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74ee; op2val:0x414a; +op3val:0x7a86; valaddr_reg:x1; val_offset:102*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 102*FLEN/8, x4, x2, x3) + +inst_69: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ee and fs2 == 0 and fe2 == 0x10 and fm2 == 0x14a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x286 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74ee; op2val:0x414a; +op3val:0x7a86; valaddr_reg:x1; val_offset:105*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 105*FLEN/8, x4, x2, x3) + +inst_70: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x26f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71c7; op2val:0x426f; +op3val:0x78a6; valaddr_reg:x1; val_offset:108*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 108*FLEN/8, x4, x2, x3) + +inst_71: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x26f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71c7; op2val:0x426f; +op3val:0x78a6; valaddr_reg:x1; val_offset:111*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 111*FLEN/8, x4, x2, x3) + +inst_72: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x26f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71c7; op2val:0x426f; +op3val:0x78a6; valaddr_reg:x1; val_offset:114*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 114*FLEN/8, x4, x2, x3) + +inst_73: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x26f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71c7; op2val:0x426f; +op3val:0x78a6; valaddr_reg:x1; val_offset:117*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 117*FLEN/8, x4, x2, x3) + +inst_74: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x26f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71c7; op2val:0x426f; +op3val:0x78a6; valaddr_reg:x1; val_offset:120*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 120*FLEN/8, x4, x2, x3) + +inst_75: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x11b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0a9 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1f4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x791b; op2val:0x38a9; +op3val:0x75f4; valaddr_reg:x1; val_offset:123*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 123*FLEN/8, x4, x2, x3) + +inst_76: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x11b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0a9 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1f4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x791b; op2val:0x38a9; +op3val:0x75f4; valaddr_reg:x1; val_offset:126*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 126*FLEN/8, x4, x2, x3) + +inst_77: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x11b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0a9 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1f4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x791b; op2val:0x38a9; +op3val:0x75f4; valaddr_reg:x1; val_offset:129*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 129*FLEN/8, x4, x2, x3) + +inst_78: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x11b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0a9 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1f4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x791b; op2val:0x38a9; +op3val:0x75f4; valaddr_reg:x1; val_offset:132*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 132*FLEN/8, x4, x2, x3) + +inst_79: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x11b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0a9 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1f4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x791b; op2val:0x38a9; +op3val:0x75f4; valaddr_reg:x1; val_offset:135*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 135*FLEN/8, x4, x2, x3) + +inst_80: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x061 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x356 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x004 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7861; op2val:0x2f56; +op3val:0x6c04; valaddr_reg:x1; val_offset:138*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 138*FLEN/8, x4, x2, x3) + +inst_81: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x061 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x356 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x004 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7861; op2val:0x2f56; +op3val:0x6c04; valaddr_reg:x1; val_offset:141*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 141*FLEN/8, x4, x2, x3) + +inst_82: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x061 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x356 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x004 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7861; op2val:0x2f56; +op3val:0x6c04; valaddr_reg:x1; val_offset:144*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 144*FLEN/8, x4, x2, x3) + +inst_83: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x061 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x356 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x004 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7861; op2val:0x2f56; +op3val:0x6c04; valaddr_reg:x1; val_offset:147*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 147*FLEN/8, x4, x2, x3) + +inst_84: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x061 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x356 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x004 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7861; op2val:0x2f56; +op3val:0x6c04; valaddr_reg:x1; val_offset:150*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 150*FLEN/8, x4, x2, x3) + +inst_85: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3a0 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x2e8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x296 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ba0; op2val:0x42e8; +op3val:0x7296; valaddr_reg:x1; val_offset:153*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 153*FLEN/8, x4, x2, x3) + +inst_86: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3a0 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x2e8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x296 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ba0; op2val:0x42e8; +op3val:0x7296; valaddr_reg:x1; val_offset:156*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 156*FLEN/8, x4, x2, x3) + +inst_87: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3a0 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x2e8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x296 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ba0; op2val:0x42e8; +op3val:0x7296; valaddr_reg:x1; val_offset:159*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 159*FLEN/8, x4, x2, x3) + +inst_88: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3a0 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x2e8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x296 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ba0; op2val:0x42e8; +op3val:0x7296; valaddr_reg:x1; val_offset:162*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 162*FLEN/8, x4, x2, x3) + +inst_89: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3a0 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x2e8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x296 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ba0; op2val:0x42e8; +op3val:0x7296; valaddr_reg:x1; val_offset:165*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 165*FLEN/8, x4, x2, x3) + +inst_90: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x170 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x107 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2d6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7970; op2val:0x3907; +op3val:0x76d6; valaddr_reg:x1; val_offset:168*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 168*FLEN/8, x4, x2, x3) + +inst_91: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x170 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x107 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2d6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7970; op2val:0x3907; +op3val:0x76d6; valaddr_reg:x1; val_offset:171*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 171*FLEN/8, x4, x2, x3) + +inst_92: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x170 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x107 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2d6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7970; op2val:0x3907; +op3val:0x76d6; valaddr_reg:x1; val_offset:174*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 174*FLEN/8, x4, x2, x3) + +inst_93: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x170 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x107 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2d6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7970; op2val:0x3907; +op3val:0x76d6; valaddr_reg:x1; val_offset:177*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 177*FLEN/8, x4, x2, x3) + +inst_94: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x170 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x107 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2d6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7970; op2val:0x3907; +op3val:0x76d6; valaddr_reg:x1; val_offset:180*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 180*FLEN/8, x4, x2, x3) + +inst_95: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x106 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x374 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0ae and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7506; op2val:0x3f74; +op3val:0x78ae; valaddr_reg:x1; val_offset:183*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 183*FLEN/8, x4, x2, x3) + +inst_96: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x106 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x374 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0ae and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7506; op2val:0x3f74; +op3val:0x78ae; valaddr_reg:x1; val_offset:186*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 186*FLEN/8, x4, x2, x3) + +inst_97: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x106 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x374 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0ae and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7506; op2val:0x3f74; +op3val:0x78ae; valaddr_reg:x1; val_offset:189*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 189*FLEN/8, x4, x2, x3) + +inst_98: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x106 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x374 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0ae and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7506; op2val:0x3f74; +op3val:0x78ae; valaddr_reg:x1; val_offset:192*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 192*FLEN/8, x4, x2, x3) + +inst_99: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x106 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x374 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0ae and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7506; op2val:0x3f74; +op3val:0x78ae; valaddr_reg:x1; val_offset:195*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 195*FLEN/8, x4, x2, x3) + +inst_100: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x33f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x14a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0cb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x773f; op2val:0x394a; +op3val:0x74cb; valaddr_reg:x1; val_offset:198*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 198*FLEN/8, x4, x2, x3) + +inst_101: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x33f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x14a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0cb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x773f; op2val:0x394a; +op3val:0x74cb; valaddr_reg:x1; val_offset:201*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 201*FLEN/8, x4, x2, x3) + +inst_102: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x33f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x14a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0cb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x773f; op2val:0x394a; +op3val:0x74cb; valaddr_reg:x1; val_offset:204*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 204*FLEN/8, x4, x2, x3) + +inst_103: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x33f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x14a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0cb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x773f; op2val:0x394a; +op3val:0x74cb; valaddr_reg:x1; val_offset:207*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 207*FLEN/8, x4, x2, x3) + +inst_104: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x33f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x14a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0cb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x773f; op2val:0x394a; +op3val:0x74cb; valaddr_reg:x1; val_offset:210*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 210*FLEN/8, x4, x2, x3) + +inst_105: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x30a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x196 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5a; op2val:0x3b0a; +op3val:0x7996; valaddr_reg:x1; val_offset:213*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 213*FLEN/8, x4, x2, x3) + +inst_106: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x30a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x196 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5a; op2val:0x3b0a; +op3val:0x7996; valaddr_reg:x1; val_offset:216*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 216*FLEN/8, x4, x2, x3) + +inst_107: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x30a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x196 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5a; op2val:0x3b0a; +op3val:0x7996; valaddr_reg:x1; val_offset:219*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 219*FLEN/8, x4, x2, x3) + +inst_108: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x30a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x196 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5a; op2val:0x3b0a; +op3val:0x7996; valaddr_reg:x1; val_offset:222*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 222*FLEN/8, x4, x2, x3) + +inst_109: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x30a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x196 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5a; op2val:0x3b0a; +op3val:0x7996; valaddr_reg:x1; val_offset:225*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 225*FLEN/8, x4, x2, x3) + +inst_110: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3ce and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0b4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x097 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73ce; op2val:0x40b4; +op3val:0x7897; valaddr_reg:x1; val_offset:228*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 228*FLEN/8, x4, x2, x3) + +inst_111: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3ce and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0b4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x097 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73ce; op2val:0x40b4; +op3val:0x7897; valaddr_reg:x1; val_offset:231*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 231*FLEN/8, x4, x2, x3) + +inst_112: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3ce and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0b4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x097 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73ce; op2val:0x40b4; +op3val:0x7897; valaddr_reg:x1; val_offset:234*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 234*FLEN/8, x4, x2, x3) + +inst_113: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3ce and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0b4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x097 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73ce; op2val:0x40b4; +op3val:0x7897; valaddr_reg:x1; val_offset:237*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 237*FLEN/8, x4, x2, x3) + +inst_114: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3ce and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0b4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x097 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73ce; op2val:0x40b4; +op3val:0x7897; valaddr_reg:x1; val_offset:240*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 240*FLEN/8, x4, x2, x3) + +inst_115: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x033 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2aa and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7833; op2val:0x3eaa; +op3val:0x7aff; valaddr_reg:x1; val_offset:243*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 243*FLEN/8, x4, x2, x3) + +inst_116: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x033 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2aa and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7833; op2val:0x3eaa; +op3val:0x7aff; valaddr_reg:x1; val_offset:246*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 246*FLEN/8, x4, x2, x3) + +inst_117: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x033 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2aa and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7833; op2val:0x3eaa; +op3val:0x7aff; valaddr_reg:x1; val_offset:249*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 249*FLEN/8, x4, x2, x3) + +inst_118: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x033 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2aa and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7833; op2val:0x3eaa; +op3val:0x7aff; valaddr_reg:x1; val_offset:252*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 252*FLEN/8, x4, x2, x3) + +inst_119: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x033 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2aa and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7833; op2val:0x3eaa; +op3val:0x7aff; valaddr_reg:x1; val_offset:255*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 255*FLEN/8, x4, x2, x3) + +inst_120: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x250 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x09a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79d5; op2val:0x3650; +op3val:0x749a; valaddr_reg:x1; val_offset:258*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 258*FLEN/8, x4, x2, x3) + +inst_121: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x250 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x09a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79d5; op2val:0x3650; +op3val:0x749a; valaddr_reg:x1; val_offset:261*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 261*FLEN/8, x4, x2, x3) + +inst_122: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x250 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x09a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79d5; op2val:0x3650; +op3val:0x749a; valaddr_reg:x1; val_offset:264*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 264*FLEN/8, x4, x2, x3) + +inst_123: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x250 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x09a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79d5; op2val:0x3650; +op3val:0x749a; valaddr_reg:x1; val_offset:267*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 267*FLEN/8, x4, x2, x3) + +inst_124: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x250 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x09a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79d5; op2val:0x3650; +op3val:0x749a; valaddr_reg:x1; val_offset:270*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 270*FLEN/8, x4, x2, x3) + +inst_125: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3b5 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x38d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd6; op2val:0x2fb5; +op3val:0x6f8d; valaddr_reg:x1; val_offset:273*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 273*FLEN/8, x4, x2, x3) + +inst_126: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3b5 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x38d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd6; op2val:0x2fb5; +op3val:0x6f8d; valaddr_reg:x1; val_offset:276*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 276*FLEN/8, x4, x2, x3) + +inst_127: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3b5 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x38d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd6; op2val:0x2fb5; +op3val:0x6f8d; valaddr_reg:x1; val_offset:279*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 279*FLEN/8, x4, x2, x3) + +inst_128: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3b5 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x38d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd6; op2val:0x2fb5; +op3val:0x6f8d; valaddr_reg:x1; val_offset:282*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 282*FLEN/8, x4, x2, x3) + +inst_129: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3b5 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x38d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd6; op2val:0x2fb5; +op3val:0x6f8d; valaddr_reg:x1; val_offset:285*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 285*FLEN/8, x4, x2, x3) + +inst_130: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2af and fs2 == 0 and fe2 == 0x0f and fm2 == 0x33e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x20d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76af; op2val:0x3f3e; +op3val:0x7a0d; valaddr_reg:x1; val_offset:288*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 288*FLEN/8, x4, x2, x3) + +inst_131: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2af and fs2 == 0 and fe2 == 0x0f and fm2 == 0x33e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x20d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76af; op2val:0x3f3e; +op3val:0x7a0d; valaddr_reg:x1; val_offset:291*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 291*FLEN/8, x4, x2, x3) + +inst_132: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2af and fs2 == 0 and fe2 == 0x0f and fm2 == 0x33e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x20d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76af; op2val:0x3f3e; +op3val:0x7a0d; valaddr_reg:x1; val_offset:294*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 294*FLEN/8, x4, x2, x3) + +inst_133: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2af and fs2 == 0 and fe2 == 0x0f and fm2 == 0x33e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x20d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76af; op2val:0x3f3e; +op3val:0x7a0d; valaddr_reg:x1; val_offset:297*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 297*FLEN/8, x4, x2, x3) + +inst_134: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2af and fs2 == 0 and fe2 == 0x0f and fm2 == 0x33e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x20d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76af; op2val:0x3f3e; +op3val:0x7a0d; valaddr_reg:x1; val_offset:300*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 300*FLEN/8, x4, x2, x3) + +inst_135: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0dc and fs2 == 0 and fe2 == 0x10 and fm2 == 0x26f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3d1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70dc; op2val:0x426f; +op3val:0x77d1; valaddr_reg:x1; val_offset:303*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 303*FLEN/8, x4, x2, x3) + +inst_136: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0dc and fs2 == 0 and fe2 == 0x10 and fm2 == 0x26f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3d1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70dc; op2val:0x426f; +op3val:0x77d1; valaddr_reg:x1; val_offset:306*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 306*FLEN/8, x4, x2, x3) + +inst_137: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0dc and fs2 == 0 and fe2 == 0x10 and fm2 == 0x26f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3d1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70dc; op2val:0x426f; +op3val:0x77d1; valaddr_reg:x1; val_offset:309*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 309*FLEN/8, x4, x2, x3) + +inst_138: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0dc and fs2 == 0 and fe2 == 0x10 and fm2 == 0x26f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3d1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70dc; op2val:0x426f; +op3val:0x77d1; valaddr_reg:x1; val_offset:312*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 312*FLEN/8, x4, x2, x3) + +inst_139: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0dc and fs2 == 0 and fe2 == 0x10 and fm2 == 0x26f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3d1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70dc; op2val:0x426f; +op3val:0x77d1; valaddr_reg:x1; val_offset:315*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 315*FLEN/8, x4, x2, x3) + +inst_140: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x104 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x042 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x157 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6904; op2val:0x4c42; +op3val:0x7957; valaddr_reg:x1; val_offset:318*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 318*FLEN/8, x4, x2, x3) + +inst_141: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x104 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x042 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x157 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6904; op2val:0x4c42; +op3val:0x7957; valaddr_reg:x1; val_offset:321*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 321*FLEN/8, x4, x2, x3) + +inst_142: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x104 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x042 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x157 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6904; op2val:0x4c42; +op3val:0x7957; valaddr_reg:x1; val_offset:324*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 324*FLEN/8, x4, x2, x3) + +inst_143: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x104 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x042 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x157 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6904; op2val:0x4c42; +op3val:0x7957; valaddr_reg:x1; val_offset:327*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 327*FLEN/8, x4, x2, x3) + +inst_144: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x104 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x042 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x157 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6904; op2val:0x4c42; +op3val:0x7957; valaddr_reg:x1; val_offset:330*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 330*FLEN/8, x4, x2, x3) + +inst_145: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x21d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x094 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a1d; op2val:0x39fe; +op3val:0x7894; valaddr_reg:x1; val_offset:333*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 333*FLEN/8, x4, x2, x3) + +inst_146: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x21d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x094 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a1d; op2val:0x39fe; +op3val:0x7894; valaddr_reg:x1; val_offset:336*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 336*FLEN/8, x4, x2, x3) + +inst_147: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x21d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x094 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a1d; op2val:0x39fe; +op3val:0x7894; valaddr_reg:x1; val_offset:339*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 339*FLEN/8, x4, x2, x3) + +inst_148: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x21d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x094 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a1d; op2val:0x39fe; +op3val:0x7894; valaddr_reg:x1; val_offset:342*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 342*FLEN/8, x4, x2, x3) + +inst_149: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x21d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x094 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a1d; op2val:0x39fe; +op3val:0x7894; valaddr_reg:x1; val_offset:345*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 345*FLEN/8, x4, x2, x3) + +inst_150: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x300 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1bb and fs3 == 0 and fe3 == 0x1d and fm3 == 0x104 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b00; op2val:0x35bb; +op3val:0x7504; valaddr_reg:x1; val_offset:348*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 348*FLEN/8, x4, x2, x3) + +inst_151: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x300 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1bb and fs3 == 0 and fe3 == 0x1d and fm3 == 0x104 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b00; op2val:0x35bb; +op3val:0x7504; valaddr_reg:x1; val_offset:351*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 351*FLEN/8, x4, x2, x3) + +inst_152: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x300 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1bb and fs3 == 0 and fe3 == 0x1d and fm3 == 0x104 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b00; op2val:0x35bb; +op3val:0x7504; valaddr_reg:x1; val_offset:354*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 354*FLEN/8, x4, x2, x3) +RVTEST_SIGBASE(x2,signature_x2_2) + +inst_153: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x300 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1bb and fs3 == 0 and fe3 == 0x1d and fm3 == 0x104 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b00; op2val:0x35bb; +op3val:0x7504; valaddr_reg:x1; val_offset:357*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 357*FLEN/8, x4, x2, x3) + +inst_154: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x300 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1bb and fs3 == 0 and fe3 == 0x1d and fm3 == 0x104 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b00; op2val:0x35bb; +op3val:0x7504; valaddr_reg:x1; val_offset:360*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 360*FLEN/8, x4, x2, x3) + +inst_155: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x18f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x798f; op2val:0x3ad6; +op3val:0x78c0; valaddr_reg:x1; val_offset:363*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 363*FLEN/8, x4, x2, x3) + +inst_156: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x18f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0c0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x798f; op2val:0x3ad6; +op3val:0x78c0; valaddr_reg:x1; val_offset:366*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 366*FLEN/8, x4, x2, x3) + +inst_157: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x18f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0c0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x798f; op2val:0x3ad6; +op3val:0x78c0; valaddr_reg:x1; val_offset:369*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 369*FLEN/8, x4, x2, x3) + +inst_158: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x18f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0c0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x798f; op2val:0x3ad6; +op3val:0x78c0; valaddr_reg:x1; val_offset:372*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 372*FLEN/8, x4, x2, x3) + +inst_159: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x18f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0c0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x798f; op2val:0x3ad6; +op3val:0x78c0; valaddr_reg:x1; val_offset:375*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 375*FLEN/8, x4, x2, x3) + +inst_160: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x24b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x34b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78a3; op2val:0x3a4b; +op3val:0x774b; valaddr_reg:x1; val_offset:378*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 378*FLEN/8, x4, x2, x3) + +inst_161: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x24b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x34b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78a3; op2val:0x3a4b; +op3val:0x774b; valaddr_reg:x1; val_offset:381*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 381*FLEN/8, x4, x2, x3) + +inst_162: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x24b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x34b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78a3; op2val:0x3a4b; +op3val:0x774b; valaddr_reg:x1; val_offset:384*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 384*FLEN/8, x4, x2, x3) + +inst_163: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x24b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x34b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78a3; op2val:0x3a4b; +op3val:0x774b; valaddr_reg:x1; val_offset:387*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 387*FLEN/8, x4, x2, x3) + +inst_164: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x24b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x34b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78a3; op2val:0x3a4b; +op3val:0x774b; valaddr_reg:x1; val_offset:390*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 390*FLEN/8, x4, x2, x3) + +inst_165: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x07f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x38d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ab7; op2val:0x3c7f; +op3val:0x7b8d; valaddr_reg:x1; val_offset:393*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 393*FLEN/8, x4, x2, x3) + +inst_166: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x07f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x38d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ab7; op2val:0x3c7f; +op3val:0x7b8d; valaddr_reg:x1; val_offset:396*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 396*FLEN/8, x4, x2, x3) + +inst_167: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x07f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x38d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ab7; op2val:0x3c7f; +op3val:0x7b8d; valaddr_reg:x1; val_offset:399*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 399*FLEN/8, x4, x2, x3) + +inst_168: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x07f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x38d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ab7; op2val:0x3c7f; +op3val:0x7b8d; valaddr_reg:x1; val_offset:402*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 402*FLEN/8, x4, x2, x3) + +inst_169: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x07f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x38d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ab7; op2val:0x3c7f; +op3val:0x7b8d; valaddr_reg:x1; val_offset:405*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 405*FLEN/8, x4, x2, x3) + +inst_170: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x394 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x19a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7794; op2val:0x3d9a; +op3val:0x794f; valaddr_reg:x1; val_offset:408*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 408*FLEN/8, x4, x2, x3) + +inst_171: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x394 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x19a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7794; op2val:0x3d9a; +op3val:0x794f; valaddr_reg:x1; val_offset:411*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 411*FLEN/8, x4, x2, x3) + +inst_172: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x394 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x19a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7794; op2val:0x3d9a; +op3val:0x794f; valaddr_reg:x1; val_offset:414*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 414*FLEN/8, x4, x2, x3) + +inst_173: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x394 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x19a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7794; op2val:0x3d9a; +op3val:0x794f; valaddr_reg:x1; val_offset:417*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 417*FLEN/8, x4, x2, x3) + +inst_174: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x394 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x19a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7794; op2val:0x3d9a; +op3val:0x794f; valaddr_reg:x1; val_offset:420*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 420*FLEN/8, x4, x2, x3) + +inst_175: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3c3 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x1c7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x19b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6bc3; op2val:0x49c7; +op3val:0x799b; valaddr_reg:x1; val_offset:423*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 423*FLEN/8, x4, x2, x3) + +inst_176: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3c3 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x1c7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x19b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6bc3; op2val:0x49c7; +op3val:0x799b; valaddr_reg:x1; val_offset:426*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 426*FLEN/8, x4, x2, x3) + +inst_177: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3c3 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x1c7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x19b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6bc3; op2val:0x49c7; +op3val:0x799b; valaddr_reg:x1; val_offset:429*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 429*FLEN/8, x4, x2, x3) + +inst_178: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3c3 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x1c7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x19b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6bc3; op2val:0x49c7; +op3val:0x799b; valaddr_reg:x1; val_offset:432*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 432*FLEN/8, x4, x2, x3) + +inst_179: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3c3 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x1c7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x19b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6bc3; op2val:0x49c7; +op3val:0x799b; valaddr_reg:x1; val_offset:435*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 435*FLEN/8, x4, x2, x3) + +inst_180: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x223 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x792c; op2val:0x3e23; +op3val:0x7bf0; valaddr_reg:x1; val_offset:438*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 438*FLEN/8, x4, x2, x3) + +inst_181: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x223 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3f0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x792c; op2val:0x3e23; +op3val:0x7bf0; valaddr_reg:x1; val_offset:441*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 441*FLEN/8, x4, x2, x3) + +inst_182: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x223 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3f0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x792c; op2val:0x3e23; +op3val:0x7bf0; valaddr_reg:x1; val_offset:444*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 444*FLEN/8, x4, x2, x3) + +inst_183: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x223 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3f0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x792c; op2val:0x3e23; +op3val:0x7bf0; valaddr_reg:x1; val_offset:447*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 447*FLEN/8, x4, x2, x3) + +inst_184: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x223 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3f0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x792c; op2val:0x3e23; +op3val:0x7bf0; valaddr_reg:x1; val_offset:450*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 450*FLEN/8, x4, x2, x3) + +inst_185: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x292 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x18a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x08d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a92; op2val:0x358a; +op3val:0x748d; valaddr_reg:x1; val_offset:453*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 453*FLEN/8, x4, x2, x3) + +inst_186: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x292 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x18a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x08d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a92; op2val:0x358a; +op3val:0x748d; valaddr_reg:x1; val_offset:456*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 456*FLEN/8, x4, x2, x3) + +inst_187: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x292 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x18a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x08d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a92; op2val:0x358a; +op3val:0x748d; valaddr_reg:x1; val_offset:459*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 459*FLEN/8, x4, x2, x3) + +inst_188: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x292 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x18a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x08d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a92; op2val:0x358a; +op3val:0x748d; valaddr_reg:x1; val_offset:462*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 462*FLEN/8, x4, x2, x3) + +inst_189: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x292 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x18a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x08d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a92; op2val:0x358a; +op3val:0x748d; valaddr_reg:x1; val_offset:465*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 465*FLEN/8, x4, x2, x3) + +inst_190: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x22b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2ee and fs3 == 0 and fe3 == 0x1e and fm3 == 0x158 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x762b; op2val:0x3eee; +op3val:0x7958; valaddr_reg:x1; val_offset:468*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 468*FLEN/8, x4, x2, x3) + +inst_191: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x22b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2ee and fs3 == 0 and fe3 == 0x1e and fm3 == 0x158 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x762b; op2val:0x3eee; +op3val:0x7958; valaddr_reg:x1; val_offset:471*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 471*FLEN/8, x4, x2, x3) + +inst_192: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x22b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2ee and fs3 == 0 and fe3 == 0x1e and fm3 == 0x158 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x762b; op2val:0x3eee; +op3val:0x7958; valaddr_reg:x1; val_offset:474*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 474*FLEN/8, x4, x2, x3) + +inst_193: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x22b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2ee and fs3 == 0 and fe3 == 0x1e and fm3 == 0x158 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x762b; op2val:0x3eee; +op3val:0x7958; valaddr_reg:x1; val_offset:477*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 477*FLEN/8, x4, x2, x3) + +inst_194: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x22b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2ee and fs3 == 0 and fe3 == 0x1e and fm3 == 0x158 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x762b; op2val:0x3eee; +op3val:0x7958; valaddr_reg:x1; val_offset:480*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 480*FLEN/8, x4, x2, x3) + +inst_195: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x1c6 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x11c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x362 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x65c6; op2val:0x4d1c; +op3val:0x7762; valaddr_reg:x1; val_offset:483*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 483*FLEN/8, x4, x2, x3) + +inst_196: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x1c6 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x11c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x362 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x65c6; op2val:0x4d1c; +op3val:0x7762; valaddr_reg:x1; val_offset:486*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 486*FLEN/8, x4, x2, x3) + +inst_197: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x1c6 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x11c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x362 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x65c6; op2val:0x4d1c; +op3val:0x7762; valaddr_reg:x1; val_offset:489*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 489*FLEN/8, x4, x2, x3) + +inst_198: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x1c6 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x11c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x362 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x65c6; op2val:0x4d1c; +op3val:0x7762; valaddr_reg:x1; val_offset:492*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 492*FLEN/8, x4, x2, x3) + +inst_199: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x1c6 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x11c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x362 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x65c6; op2val:0x4d1c; +op3val:0x7762; valaddr_reg:x1; val_offset:495*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 495*FLEN/8, x4, x2, x3) + +inst_200: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x160 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x193 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x37d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7160; op2val:0x3993; +op3val:0x6f7d; valaddr_reg:x1; val_offset:498*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 498*FLEN/8, x4, x2, x3) + +inst_201: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x160 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x193 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x37d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7160; op2val:0x3993; +op3val:0x6f7d; valaddr_reg:x1; val_offset:501*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 501*FLEN/8, x4, x2, x3) + +inst_202: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x160 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x193 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x37d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7160; op2val:0x3993; +op3val:0x6f7d; valaddr_reg:x1; val_offset:504*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 504*FLEN/8, x4, x2, x3) + +inst_203: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x160 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x193 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x37d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7160; op2val:0x3993; +op3val:0x6f7d; valaddr_reg:x1; val_offset:507*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 507*FLEN/8, x4, x2, x3) + +inst_204: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x160 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x193 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x37d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7160; op2val:0x3993; +op3val:0x6f7d; valaddr_reg:x1; val_offset:510*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 510*FLEN/8, x4, x2, x3) + +inst_205: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x38b and fs2 == 0 and fe2 == 0x12 and fm2 == 0x283 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x224 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6b8b; op2val:0x4a83; +op3val:0x7a24; valaddr_reg:x1; val_offset:513*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 513*FLEN/8, x4, x2, x3) + +inst_206: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x38b and fs2 == 0 and fe2 == 0x12 and fm2 == 0x283 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x224 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6b8b; op2val:0x4a83; +op3val:0x7a24; valaddr_reg:x1; val_offset:516*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 516*FLEN/8, x4, x2, x3) + +inst_207: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x38b and fs2 == 0 and fe2 == 0x12 and fm2 == 0x283 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x224 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6b8b; op2val:0x4a83; +op3val:0x7a24; valaddr_reg:x1; val_offset:519*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 519*FLEN/8, x4, x2, x3) + +inst_208: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x38b and fs2 == 0 and fe2 == 0x12 and fm2 == 0x283 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x224 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6b8b; op2val:0x4a83; +op3val:0x7a24; valaddr_reg:x1; val_offset:522*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 522*FLEN/8, x4, x2, x3) + +inst_209: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x38b and fs2 == 0 and fe2 == 0x12 and fm2 == 0x283 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x224 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6b8b; op2val:0x4a83; +op3val:0x7a24; valaddr_reg:x1; val_offset:525*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 525*FLEN/8, x4, x2, x3) + +inst_210: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x023 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3a8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3eb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7023; op2val:0x3fa8; +op3val:0x73eb; valaddr_reg:x1; val_offset:528*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 528*FLEN/8, x4, x2, x3) + +inst_211: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x023 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3a8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3eb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7023; op2val:0x3fa8; +op3val:0x73eb; valaddr_reg:x1; val_offset:531*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 531*FLEN/8, x4, x2, x3) + +inst_212: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x023 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3a8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3eb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7023; op2val:0x3fa8; +op3val:0x73eb; valaddr_reg:x1; val_offset:534*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 534*FLEN/8, x4, x2, x3) + +inst_213: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x023 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3a8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3eb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7023; op2val:0x3fa8; +op3val:0x73eb; valaddr_reg:x1; val_offset:537*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 537*FLEN/8, x4, x2, x3) + +inst_214: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x023 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3a8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3eb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7023; op2val:0x3fa8; +op3val:0x73eb; valaddr_reg:x1; val_offset:540*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 540*FLEN/8, x4, x2, x3) + +inst_215: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x240 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x075 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7640; op2val:0x4075; +op3val:0x7af7; valaddr_reg:x1; val_offset:543*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 543*FLEN/8, x4, x2, x3) + +inst_216: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x240 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x075 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7640; op2val:0x4075; +op3val:0x7af7; valaddr_reg:x1; val_offset:546*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 546*FLEN/8, x4, x2, x3) + +inst_217: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x240 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x075 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7640; op2val:0x4075; +op3val:0x7af7; valaddr_reg:x1; val_offset:549*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 549*FLEN/8, x4, x2, x3) + +inst_218: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x240 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x075 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7640; op2val:0x4075; +op3val:0x7af7; valaddr_reg:x1; val_offset:552*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 552*FLEN/8, x4, x2, x3) + +inst_219: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x240 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x075 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7640; op2val:0x4075; +op3val:0x7af7; valaddr_reg:x1; val_offset:555*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 555*FLEN/8, x4, x2, x3) + +inst_220: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x12d and fs2 == 0 and fe2 == 0x0d and fm2 == 0x374 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x752d; op2val:0x3774; +op3val:0x70d3; valaddr_reg:x1; val_offset:558*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 558*FLEN/8, x4, x2, x3) + +inst_221: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x12d and fs2 == 0 and fe2 == 0x0d and fm2 == 0x374 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x752d; op2val:0x3774; +op3val:0x70d3; valaddr_reg:x1; val_offset:561*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 561*FLEN/8, x4, x2, x3) + +inst_222: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x12d and fs2 == 0 and fe2 == 0x0d and fm2 == 0x374 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x752d; op2val:0x3774; +op3val:0x70d3; valaddr_reg:x1; val_offset:564*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 564*FLEN/8, x4, x2, x3) + +inst_223: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x12d and fs2 == 0 and fe2 == 0x0d and fm2 == 0x374 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x752d; op2val:0x3774; +op3val:0x70d3; valaddr_reg:x1; val_offset:567*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 567*FLEN/8, x4, x2, x3) + +inst_224: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x134 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x31f and fs3 == 0 and fe3 == 0x1b and fm3 == 0x0a2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7934; op2val:0x2f1f; +op3val:0x6ca2; valaddr_reg:x1; val_offset:570*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 570*FLEN/8, x4, x2, x3) + +inst_225: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x134 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x31f and fs3 == 0 and fe3 == 0x1b and fm3 == 0x0a2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7934; op2val:0x2f1f; +op3val:0x6ca2; valaddr_reg:x1; val_offset:573*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 573*FLEN/8, x4, x2, x3) + +inst_226: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x134 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x31f and fs3 == 0 and fe3 == 0x1b and fm3 == 0x0a2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7934; op2val:0x2f1f; +op3val:0x6ca2; valaddr_reg:x1; val_offset:576*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 576*FLEN/8, x4, x2, x3) + +inst_227: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x048 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x175 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1d9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7848; op2val:0x3975; +op3val:0x75d9; valaddr_reg:x1; val_offset:579*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 579*FLEN/8, x4, x2, x3) + +inst_228: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x048 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x175 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1d9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7848; op2val:0x3975; +op3val:0x75d9; valaddr_reg:x1; val_offset:582*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 582*FLEN/8, x4, x2, x3) + +inst_229: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x048 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x175 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1d9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7848; op2val:0x3975; +op3val:0x75d9; valaddr_reg:x1; val_offset:585*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 585*FLEN/8, x4, x2, x3) + +inst_230: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x36c and fs2 == 0 and fe2 == 0x12 and fm2 == 0x05f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6b6c; op2val:0x485f; +op3val:0x780e; valaddr_reg:x1; val_offset:588*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 588*FLEN/8, x4, x2, x3) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(29997,32,FLEN) +NAN_BOXED(29997,32,FLEN) +NAN_BOXED(29997,32,FLEN) +NAN_BOXED(29997,32,FLEN) +NAN_BOXED(14196,32,FLEN) +NAN_BOXED(28883,32,FLEN) +NAN_BOXED(29997,32,FLEN) +NAN_BOXED(29997,32,FLEN) +NAN_BOXED(28883,32,FLEN) +NAN_BOXED(29997,32,FLEN) +NAN_BOXED(14196,32,FLEN) +NAN_BOXED(14196,32,FLEN) +NAN_BOXED(29997,32,FLEN) +NAN_BOXED(29997,32,FLEN) +NAN_BOXED(29997,32,FLEN) +NAN_BOXED(31028,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(27810,32,FLEN) +NAN_BOXED(31028,32,FLEN) +NAN_BOXED(12063,32,FLEN) +NAN_BOXED(27810,32,FLEN) +NAN_BOXED(31028,32,FLEN) +NAN_BOXED(12063,32,FLEN) +NAN_BOXED(27810,32,FLEN) +NAN_BOXED(31028,32,FLEN) +NAN_BOXED(12063,32,FLEN) +NAN_BOXED(12063,32,FLEN) +NAN_BOXED(31028,32,FLEN) +NAN_BOXED(31028,32,FLEN) +NAN_BOXED(27810,32,FLEN) +NAN_BOXED(30792,32,FLEN) +NAN_BOXED(14709,32,FLEN) +NAN_BOXED(30792,32,FLEN) +NAN_BOXED(30792,32,FLEN) +NAN_BOXED(14709,32,FLEN) +NAN_BOXED(30792,32,FLEN) +test_dataset_1: +NAN_BOXED(30792,32,FLEN) +NAN_BOXED(14709,32,FLEN) +NAN_BOXED(30169,32,FLEN) +NAN_BOXED(30792,32,FLEN) +NAN_BOXED(14709,32,FLEN) +NAN_BOXED(30169,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(14709,32,FLEN) +NAN_BOXED(30169,32,FLEN) +NAN_BOXED(27500,32,FLEN) +NAN_BOXED(18527,32,FLEN) +NAN_BOXED(30734,32,FLEN) +NAN_BOXED(27500,32,FLEN) +NAN_BOXED(18527,32,FLEN) +NAN_BOXED(30734,32,FLEN) +NAN_BOXED(27500,32,FLEN) +NAN_BOXED(18527,32,FLEN) +NAN_BOXED(30734,32,FLEN) +NAN_BOXED(27500,32,FLEN) +NAN_BOXED(18527,32,FLEN) +NAN_BOXED(30734,32,FLEN) +NAN_BOXED(27500,32,FLEN) +NAN_BOXED(18527,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(26828,32,FLEN) +NAN_BOXED(18887,32,FLEN) +NAN_BOXED(30447,32,FLEN) +NAN_BOXED(26828,32,FLEN) +NAN_BOXED(18887,32,FLEN) +NAN_BOXED(30447,32,FLEN) +NAN_BOXED(26828,32,FLEN) +NAN_BOXED(18887,32,FLEN) +NAN_BOXED(30447,32,FLEN) +NAN_BOXED(26828,32,FLEN) +NAN_BOXED(18887,32,FLEN) +NAN_BOXED(30447,32,FLEN) +test_dataset_2: +NAN_BOXED(26828,32,FLEN) +NAN_BOXED(18887,32,FLEN) +NAN_BOXED(30447,32,FLEN) +NAN_BOXED(27768,32,FLEN) +NAN_BOXED(15665,32,FLEN) +NAN_BOXED(28109,32,FLEN) +NAN_BOXED(27768,32,FLEN) +NAN_BOXED(15665,32,FLEN) +NAN_BOXED(28109,32,FLEN) +NAN_BOXED(27768,32,FLEN) +NAN_BOXED(15665,32,FLEN) +NAN_BOXED(28109,32,FLEN) +NAN_BOXED(27768,32,FLEN) +NAN_BOXED(15665,32,FLEN) +NAN_BOXED(28109,32,FLEN) +NAN_BOXED(27768,32,FLEN) +NAN_BOXED(15665,32,FLEN) +NAN_BOXED(28109,32,FLEN) +NAN_BOXED(30410,32,FLEN) +NAN_BOXED(16330,32,FLEN) +NAN_BOXED(31388,32,FLEN) +NAN_BOXED(30410,32,FLEN) +NAN_BOXED(16330,32,FLEN) +NAN_BOXED(31388,32,FLEN) +NAN_BOXED(30410,32,FLEN) +NAN_BOXED(16330,32,FLEN) +NAN_BOXED(31388,32,FLEN) +NAN_BOXED(30410,32,FLEN) +NAN_BOXED(16330,32,FLEN) +NAN_BOXED(31388,32,FLEN) +test_dataset_3: +NAN_BOXED(30410,16,FLEN) +NAN_BOXED(16330,16,FLEN) +NAN_BOXED(31388,16,FLEN) +NAN_BOXED(28651,16,FLEN) +NAN_BOXED(16182,16,FLEN) +NAN_BOXED(29475,16,FLEN) +NAN_BOXED(28651,16,FLEN) +NAN_BOXED(16182,16,FLEN) +NAN_BOXED(29475,16,FLEN) +NAN_BOXED(28651,16,FLEN) +NAN_BOXED(16182,16,FLEN) +NAN_BOXED(29475,16,FLEN) +NAN_BOXED(28651,16,FLEN) +NAN_BOXED(16182,16,FLEN) +NAN_BOXED(29475,16,FLEN) +NAN_BOXED(28651,16,FLEN) +NAN_BOXED(16182,16,FLEN) +NAN_BOXED(29475,16,FLEN) +NAN_BOXED(30980,16,FLEN) +NAN_BOXED(15882,16,FLEN) +NAN_BOXED(31635,16,FLEN) +NAN_BOXED(30980,16,FLEN) +NAN_BOXED(15882,16,FLEN) +NAN_BOXED(31635,16,FLEN) +NAN_BOXED(30980,16,FLEN) +NAN_BOXED(15882,16,FLEN) +NAN_BOXED(31635,16,FLEN) +NAN_BOXED(30980,16,FLEN) +NAN_BOXED(15882,16,FLEN) +NAN_BOXED(31635,16,FLEN) +NAN_BOXED(30980,16,FLEN) +NAN_BOXED(15882,16,FLEN) +NAN_BOXED(31635,16,FLEN) +NAN_BOXED(30877,16,FLEN) +NAN_BOXED(14719,16,FLEN) +NAN_BOXED(30296,16,FLEN) +NAN_BOXED(30877,16,FLEN) +NAN_BOXED(14719,16,FLEN) +NAN_BOXED(30296,16,FLEN) +NAN_BOXED(30877,16,FLEN) +NAN_BOXED(14719,16,FLEN) +NAN_BOXED(30296,16,FLEN) +NAN_BOXED(30877,16,FLEN) +NAN_BOXED(14719,16,FLEN) +NAN_BOXED(30296,16,FLEN) +NAN_BOXED(30877,16,FLEN) +NAN_BOXED(14719,16,FLEN) +NAN_BOXED(30296,16,FLEN) +NAN_BOXED(31694,16,FLEN) +NAN_BOXED(10780,16,FLEN) +NAN_BOXED(27126,16,FLEN) +NAN_BOXED(31694,16,FLEN) +NAN_BOXED(10780,16,FLEN) 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+NAN_BOXED(16501,16,FLEN) +NAN_BOXED(31479,16,FLEN) +NAN_BOXED(30272,16,FLEN) +NAN_BOXED(16501,16,FLEN) +NAN_BOXED(31479,16,FLEN) +NAN_BOXED(30272,16,FLEN) +NAN_BOXED(16501,16,FLEN) +NAN_BOXED(31479,16,FLEN) +NAN_BOXED(30272,16,FLEN) +NAN_BOXED(16501,16,FLEN) +NAN_BOXED(31479,16,FLEN) +NAN_BOXED(29997,16,FLEN) +NAN_BOXED(14196,16,FLEN) +NAN_BOXED(28883,16,FLEN) +NAN_BOXED(29997,16,FLEN) +NAN_BOXED(14196,16,FLEN) +NAN_BOXED(28883,16,FLEN) +NAN_BOXED(29997,16,FLEN) +NAN_BOXED(14196,16,FLEN) +NAN_BOXED(28883,16,FLEN) +NAN_BOXED(29997,16,FLEN) +NAN_BOXED(14196,16,FLEN) +NAN_BOXED(28883,16,FLEN) +NAN_BOXED(31028,16,FLEN) +NAN_BOXED(12063,16,FLEN) +NAN_BOXED(27810,16,FLEN) +NAN_BOXED(31028,16,FLEN) +NAN_BOXED(12063,16,FLEN) +NAN_BOXED(27810,16,FLEN) +NAN_BOXED(31028,16,FLEN) +NAN_BOXED(12063,16,FLEN) +NAN_BOXED(27810,16,FLEN) +NAN_BOXED(30792,16,FLEN) +NAN_BOXED(14709,16,FLEN) +NAN_BOXED(30169,16,FLEN) +NAN_BOXED(30792,16,FLEN) +NAN_BOXED(14709,16,FLEN) +NAN_BOXED(30169,16,FLEN) +NAN_BOXED(30792,16,FLEN) +NAN_BOXED(14709,16,FLEN) +NAN_BOXED(30169,16,FLEN) +NAN_BOXED(27500,16,FLEN) +NAN_BOXED(18527,16,FLEN) +NAN_BOXED(30734,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x4_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x4_1: + .fill 26*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_0: + .fill 24*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_1: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_2: + .fill 156*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fmsub_b6-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fmsub_b6-01.S new file mode 100644 index 000000000..2f14a18d8 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fmsub_b6-01.S @@ -0,0 +1,484 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 05:33:17 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fmsub.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fmsub.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fmsub_b6 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fmsub_b6) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x7,test_dataset_0) +RVTEST_SIGBASE(x4,signature_x4_1) + +inst_0: +// rs1 == rs2 == rs3 != rd, rs1==x22, rs2==x22, rs3==x22, rd==x30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x22; op2:x22; op3:x22; dest:x30; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x7; val_offset:0*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x30, x22, x22, x22, dyn, 0, 0, x7, 0*FLEN/8, x10, x4, x5) + +inst_1: +// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==x25, rs2==x3, rs3==x7, rd==x24,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x25; op2:x3; op3:x7; dest:x24; op1val:0x0; op2val:0xfbff; +op3val:0x0; valaddr_reg:x7; val_offset:3*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x24, x25, x3, x7, dyn, 32, 0, x7, 3*FLEN/8, x10, x4, x5) + +inst_2: +// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==x8, rs2==x8, rs3==x10, rd==x23,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x8; op2:x8; op3:x10; dest:x23; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x7; val_offset:6*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x23, x8, x8, x10, dyn, 64, 0, x7, 6*FLEN/8, x10, x4, x5) + +inst_3: +// rd == rs2 == rs3 != rs1, rs1==x0, rs2==x6, rs3==x6, rd==x6,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x0; op2:x6; op3:x6; dest:x6; op1val:0x0; op2val:0xfbff; +op3val:0xfbff; valaddr_reg:x7; val_offset:9*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x6, x0, x6, x6, dyn, 96, 0, x7, 9*FLEN/8, x10, x4, x5) + +inst_4: +// rs1 == rs2 == rs3 == rd, rs1==x21, rs2==x21, rs3==x21, rd==x21,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x21; op2:x21; op3:x21; dest:x21; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x7; val_offset:12*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x21, x21, x21, x21, dyn, 128, 0, x7, 12*FLEN/8, x10, x4, x5) + +inst_5: +// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==x11, rs2==x17, rs3==x31, rd==x17,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x11; op2:x17; op3:x31; dest:x17; op1val:0x0; op2val:0x7bff; +op3val:0x0; valaddr_reg:x7; val_offset:15*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x17, x11, x17, x31, dyn, 0, 0, x7, 15*FLEN/8, x10, x4, x5) + +inst_6: +// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==x17, rs2==x28, rs3==x15, rd==x15,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x17; op2:x28; op3:x15; dest:x15; op1val:0x0; op2val:0x7bff; +op3val:0x0; valaddr_reg:x7; val_offset:18*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x15, x17, x28, x15, dyn, 32, 0, x7, 18*FLEN/8, x10, x4, x5) + +inst_7: +// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==x26, rs2==x13, rs3==x30, rd==x26,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x26; op2:x13; op3:x30; dest:x26; op1val:0x0; op2val:0x7bff; +op3val:0x0; valaddr_reg:x7; val_offset:21*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x26, x26, x13, x30, dyn, 64, 0, x7, 21*FLEN/8, x10, x4, x5) + +inst_8: +// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==x9, rs2==x16, rs3==x16, rd==x2,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x9; op2:x16; op3:x16; dest:x2; op1val:0x0; op2val:0x7bff; +op3val:0x7bff; valaddr_reg:x7; val_offset:24*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x2, x9, x16, x16, dyn, 96, 0, x7, 24*FLEN/8, x10, x4, x5) + +inst_9: +// rs1 == rs2 == rd != rs3, rs1==x14, rs2==x14, rs3==x11, rd==x14,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x14; op2:x14; op3:x11; dest:x14; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x7; val_offset:27*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x14, x14, x14, x11, dyn, 128, 0, x7, 27*FLEN/8, x10, x4, x5) + +inst_10: +// rs1 == rd == rs3 != rs2, rs1==x29, rs2==x27, rs3==x29, rd==x29, +/* opcode: fmsub.h ; op1:x29; op2:x27; op3:x29; dest:x29; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x7; val_offset:30*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x29, x29, x27, x29, dyn, 0, 0, x7, 30*FLEN/8, x10, x4, x5) + +inst_11: +// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==x19, rs2==x0, rs3==x19, rd==x1, +/* opcode: fmsub.h ; op1:x19; op2:x0; op3:x19; dest:x1; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x7; val_offset:33*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x1, x19, x0, x19, dyn, 0, 0, x7, 33*FLEN/8, x10, x4, x5) +RVTEST_VALBASEUPD(x8,test_dataset_1) + +inst_12: +// rs1==x3, rs2==x25, rs3==x18, rd==x7, +/* opcode: fmsub.h ; op1:x3; op2:x25; op3:x18; dest:x7; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x8; val_offset:0*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x7, x3, x25, x18, dyn, 0, 0, x8, 0*FLEN/8, x14, x4, x5) + +inst_13: +// rs1==x18, rs2==x12, rs3==x24, rd==x31, +/* opcode: fmsub.h ; op1:x18; op2:x12; op3:x24; dest:x31; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x8; val_offset:3*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x18, x12, x24, dyn, 0, 0, x8, 3*FLEN/8, x14, x4, x6) +RVTEST_SIGBASE(x3,signature_x3_0) + +inst_14: +// rs1==x27, rs2==x31, rs3==x8, rd==x22, +/* opcode: fmsub.h ; op1:x27; op2:x31; op3:x8; dest:x22; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x8; val_offset:6*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x22, x27, x31, x8, dyn, 0, 0, x8, 6*FLEN/8, x14, x3, x6) + +inst_15: +// rs1==x30, rs2==x10, rs3==x0, rd==x18, +/* opcode: fmsub.h ; op1:x30; op2:x10; op3:x0; dest:x18; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x8; val_offset:9*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x18, x30, x10, x0, dyn, 0, 0, x8, 9*FLEN/8, x14, x3, x6) + +inst_16: +// rs1==x15, rs2==x5, rs3==x28, rd==x4, +/* opcode: fmsub.h ; op1:x15; op2:x5; op3:x28; dest:x4; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x8; val_offset:12*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x4, x15, x5, x28, dyn, 0, 0, x8, 12*FLEN/8, x14, x3, x6) + +inst_17: +// rs1==x28, rs2==x20, rs3==x5, rd==x25, +/* opcode: fmsub.h ; op1:x28; op2:x20; op3:x5; dest:x25; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x8; val_offset:15*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x25, x28, x20, x5, dyn, 0, 0, x8, 15*FLEN/8, x14, x3, x6) + +inst_18: +// rs1==x10, rs2==x9, rs3==x13, rd==x19, +/* opcode: fmsub.h ; op1:x10; op2:x9; op3:x13; dest:x19; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x8; val_offset:18*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x19, x10, x9, x13, dyn, 0, 0, x8, 18*FLEN/8, x14, x3, x6) + +inst_19: +// rs1==x20, rs2==x15, rs3==x4, rd==x12, +/* opcode: fmsub.h ; op1:x20; op2:x15; op3:x4; dest:x12; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x8; val_offset:21*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x12, x20, x15, x4, dyn, 0, 0, x8, 21*FLEN/8, x14, x3, x6) + +inst_20: +// rs1==x1, rs2==x18, rs3==x9, rd==x13, +/* opcode: fmsub.h ; op1:x1; op2:x18; op3:x9; dest:x13; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x8; val_offset:24*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x13, x1, x18, x9, dyn, 0, 0, x8, 24*FLEN/8, x14, x3, x6) + +inst_21: +// rs1==x24, rs2==x4, rs3==x12, rd==x20, +/* opcode: fmsub.h ; op1:x24; op2:x4; op3:x12; dest:x20; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x8; val_offset:27*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x20, x24, x4, x12, dyn, 0, 0, x8, 27*FLEN/8, x14, x3, x6) + +inst_22: +// rs1==x31, rs2==x24, rs3==x25, rd==x11, +/* opcode: fmsub.h ; op1:x31; op2:x24; op3:x25; dest:x11; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x8; val_offset:30*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x11, x31, x24, x25, dyn, 0, 0, x8, 30*FLEN/8, x14, x3, x6) + +inst_23: +// rs1==x4, rs2==x1, rs3==x2, rd==x9, +/* opcode: fmsub.h ; op1:x4; op2:x1; op3:x2; dest:x9; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x8; val_offset:33*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x9, x4, x1, x2, dyn, 0, 0, x8, 33*FLEN/8, x14, x3, x6) + +inst_24: +// rs1==x12, rs2==x7, rs3==x17, rd==x16, +/* opcode: fmsub.h ; op1:x12; op2:x7; op3:x17; dest:x16; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x8; val_offset:36*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x16, x12, x7, x17, dyn, 0, 0, x8, 36*FLEN/8, x14, x3, x6) + +inst_25: +// rs1==x13, rs2==x19, rs3==x23, rd==x10, +/* opcode: fmsub.h ; op1:x13; op2:x19; op3:x23; dest:x10; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x8; val_offset:39*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x10, x13, x19, x23, dyn, 0, 0, x8, 39*FLEN/8, x14, x3, x6) + +inst_26: +// rs1==x16, rs2==x11, rs3==x14, rd==x28, +/* opcode: fmsub.h ; op1:x16; op2:x11; op3:x14; dest:x28; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x8; val_offset:42*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x28, x16, x11, x14, dyn, 0, 0, x8, 42*FLEN/8, x14, x3, x6) + +inst_27: +// rs1==x2, rs2==x26, rs3==x27, rd==x5, +/* opcode: fmsub.h ; op1:x2; op2:x26; op3:x27; dest:x5; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x8; val_offset:45*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x5, x2, x26, x27, dyn, 0, 0, x8, 45*FLEN/8, x14, x3, x6) +RVTEST_VALBASEUPD(x4,test_dataset_2) + +inst_28: +// rs1==x7, rs2==x2, rs3==x26, rd==x8, +/* opcode: fmsub.h ; op1:x7; op2:x2; op3:x26; dest:x8; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x4; val_offset:0*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x8, x7, x2, x26, dyn, 0, 0, x4, 0*FLEN/8, x9, x3, x6) + +inst_29: +// rs1==x5, rs2==x23, rs3==x1, rd==x0, +/* opcode: fmsub.h ; op1:x5; op2:x23; op3:x1; dest:x0; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x4; val_offset:3*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x0, x5, x23, x1, dyn, 0, 0, x4, 3*FLEN/8, x9, x3, x2) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_30: +// rs1==x23, rs2==x29, rs3==x3, rd==x27, +/* opcode: fmsub.h ; op1:x23; op2:x29; op3:x3; dest:x27; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x4; val_offset:6*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x27, x23, x29, x3, dyn, 0, 0, x4, 6*FLEN/8, x9, x1, x2) + +inst_31: +// rs1==x6, rs2==x30, rs3==x20, rd==x3, +/* opcode: fmsub.h ; op1:x6; op2:x30; op3:x20; dest:x3; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x4; val_offset:9*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x3, x6, x30, x20, dyn, 0, 0, x4, 9*FLEN/8, x9, x1, x2) + +inst_32: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfbff; +op3val:0x0; valaddr_reg:x4; val_offset:12*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x4, 12*FLEN/8, x9, x1, x2) + +inst_33: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfbff; +op3val:0x0; valaddr_reg:x4; val_offset:15*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x4, 15*FLEN/8, x9, x1, x2) + +inst_34: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfbff; +op3val:0x0; valaddr_reg:x4; val_offset:18*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x4, 18*FLEN/8, x9, x1, x2) + +inst_35: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfbff; +op3val:0x0; valaddr_reg:x4; val_offset:21*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x4, 21*FLEN/8, x9, x1, x2) + +inst_36: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7bff; +op3val:0x0; valaddr_reg:x4; val_offset:24*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x4, 24*FLEN/8, x9, x1, x2) + +inst_37: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7bff; +op3val:0x0; valaddr_reg:x4; val_offset:27*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x4, 27*FLEN/8, x9, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(64511,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +test_dataset_1: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +test_dataset_2: +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(0,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x4_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x4_1: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x3_0: + .fill 32*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_0: + .fill 16*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fmsub_b7-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fmsub_b7-01.S new file mode 100644 index 000000000..546aa2399 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fmsub_b7-01.S @@ -0,0 +1,784 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 05:33:17 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fmsub.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fmsub.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fmsub_b7 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fmsub_b7) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x6,test_dataset_0) +RVTEST_SIGBASE(x4,signature_x4_1) + +inst_0: +// rs1 == rs2 == rs3 != rd, rs1==x18, rs2==x18, rs3==x18, rd==x23,fs1 == 0 and fe1 == 0x1d and fm1 == 0x12d and fs2 == 0 and fe2 == 0x0d and fm2 == 0x374 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x18; op2:x18; op3:x18; dest:x23; op1val:0x752d; op2val:0x752d; +op3val:0x752d; valaddr_reg:x6; val_offset:0*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x23, x18, x18, x18, dyn, 96, 0, x6, 0*FLEN/8, x9, x4, x5) + +inst_1: +// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==x27, rs2==x29, rs3==x21, rd==x19,fs1 == 0 and fe1 == 0x1e and fm1 == 0x134 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x31f and fs3 == 0 and fe3 == 0x1b and fm3 == 0x0a2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x27; op2:x29; op3:x21; dest:x19; op1val:0x7934; op2val:0x2f1f; +op3val:0x6ca2; valaddr_reg:x6; val_offset:3*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x19, x27, x29, x21, dyn, 96, 0, x6, 3*FLEN/8, x9, x4, x5) + +inst_2: +// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==x2, rs2==x2, rs3==x14, rd==x27,fs1 == 0 and fe1 == 0x1e and fm1 == 0x048 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x175 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1d9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x2; op2:x2; op3:x14; dest:x27; op1val:0x7848; op2val:0x7848; +op3val:0x75d9; valaddr_reg:x6; val_offset:6*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x27, x2, x2, x14, dyn, 96, 0, x6, 6*FLEN/8, x9, x4, x5) + +inst_3: +// rd == rs2 == rs3 != rs1, rs1==x31, rs2==x12, rs3==x12, rd==x12,fs1 == 0 and fe1 == 0x1a and fm1 == 0x36c and fs2 == 0 and fe2 == 0x12 and fm2 == 0x05f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x31; op2:x12; op3:x12; dest:x12; op1val:0x6b6c; op2val:0x485f; +op3val:0x485f; valaddr_reg:x6; val_offset:9*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x12, x31, x12, x12, dyn, 96, 0, x6, 9*FLEN/8, x9, x4, x5) + +inst_4: +// rs1 == rs2 == rs3 == rd, rs1==x10, rs2==x10, rs3==x10, rd==x10,fs1 == 0 and fe1 == 0x1a and fm1 == 0x0cc and fs2 == 0 and fe2 == 0x12 and fm2 == 0x1c7 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2ef and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x10; op2:x10; op3:x10; dest:x10; op1val:0x68cc; op2val:0x68cc; +op3val:0x68cc; valaddr_reg:x6; val_offset:12*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x10, x10, x10, x10, dyn, 96, 0, x6, 12*FLEN/8, x9, x4, x5) + +inst_5: +// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==x1, rs2==x13, rs3==x26, rd==x13,fs1 == 0 and fe1 == 0x1b and fm1 == 0x078 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x131 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x1cd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x1; op2:x13; op3:x26; dest:x13; op1val:0x6c78; op2val:0x3d31; +op3val:0x6dcd; valaddr_reg:x6; val_offset:15*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x13, x1, x13, x26, dyn, 96, 0, x6, 15*FLEN/8, x9, x4, x5) + +inst_6: +// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==x19, rs2==x28, rs3==x25, rd==x25,fs1 == 0 and fe1 == 0x1d and fm1 == 0x2ca and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3ca and fs3 == 0 and fe3 == 0x1e and fm3 == 0x29c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x19; op2:x28; op3:x25; dest:x25; op1val:0x76ca; op2val:0x3fca; +op3val:0x7a9c; valaddr_reg:x6; val_offset:18*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x25, x19, x28, x25, dyn, 96, 0, x6, 18*FLEN/8, x9, x4, x5) + +inst_7: +// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==x14, rs2==x7, rs3==x17, rd==x14,fs1 == 0 and fe1 == 0x1b and fm1 == 0x3eb and fs2 == 0 and fe2 == 0x0f and fm2 == 0x336 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x323 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x14; op2:x7; op3:x17; dest:x14; op1val:0x6feb; op2val:0x3f36; +op3val:0x7323; valaddr_reg:x6; val_offset:21*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x14, x14, x7, x17, dyn, 96, 0, x6, 21*FLEN/8, x9, x4, x5) + +inst_8: +// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==x23, rs2==x15, rs3==x15, rd==x18,fs1 == 0 and fe1 == 0x1e and fm1 == 0x104 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x20a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x393 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x23; op2:x15; op3:x15; dest:x18; op1val:0x7904; op2val:0x3e0a; +op3val:0x3e0a; valaddr_reg:x6; val_offset:24*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x18, x23, x15, x15, dyn, 96, 0, x6, 24*FLEN/8, x9, x4, x5) + +inst_9: +// rs1 == rs2 == rd != rs3, rs1==x8, rs2==x8, rs3==x24, rd==x8,fs1 == 0 and fe1 == 0x1e and fm1 == 0x09d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x17f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x258 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x8; op2:x8; op3:x24; dest:x8; op1val:0x789d; op2val:0x789d; +op3val:0x7658; valaddr_reg:x6; val_offset:27*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x8, x8, x8, x24, dyn, 96, 0, x6, 27*FLEN/8, x9, x4, x5) + +inst_10: +// rs1 == rd == rs3 != rs2, rs1==x29, rs2==x17, rs3==x29, rd==x29,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ce and fs2 == 0 and fe2 == 0x0a and fm2 == 0x21c and fs3 == 0 and fe3 == 0x1a and fm3 == 0x1f6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x29; op2:x17; op3:x29; dest:x29; op1val:0x7bce; op2val:0x2a1c; +op3val:0x7bce; valaddr_reg:x6; val_offset:30*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x29, x29, x17, x29, dyn, 96, 0, x6, 30*FLEN/8, x9, x4, x5) + +inst_11: +// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==x11, rs2==x1, rs3==x11, rd==x3,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2dd and fs2 == 0 and fe2 == 0x0d and fm2 == 0x165 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x11; op2:x1; op3:x11; dest:x3; op1val:0x7add; op2val:0x3565; +op3val:0x7add; valaddr_reg:x6; val_offset:33*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x3, x11, x1, x11, dyn, 96, 0, x6, 33*FLEN/8, x9, x4, x5) + +inst_12: +// rs1==x21, rs2==x24, rs3==x8, rd==x26,fs1 == 0 and fe1 == 0x1c and fm1 == 0x09d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x288 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x389 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x21; op2:x24; op3:x8; dest:x26; op1val:0x709d; op2val:0x3a88; +op3val:0x6f89; valaddr_reg:x6; val_offset:36*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x26, x21, x24, x8, dyn, 96, 0, x6, 36*FLEN/8, x9, x4, x5) +RVTEST_VALBASEUPD(x10,test_dataset_1) + +inst_13: +// rs1==x7, rs2==x9, rs3==x4, rd==x17,fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ee and fs2 == 0 and fe2 == 0x10 and fm2 == 0x14a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x286 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x7; op2:x9; op3:x4; dest:x17; op1val:0x74ee; op2val:0x414a; +op3val:0x7a86; valaddr_reg:x10; val_offset:0*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x17, x7, x9, x4, dyn, 96, 0, x10, 0*FLEN/8, x12, x4, x5) + +inst_14: +// rs1==x13, rs2==x22, rs3==x0, rd==x30,fs1 == 0 and fe1 == 0x1c and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x26f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x13; op2:x22; op3:x0; dest:x30; op1val:0x71c7; op2val:0x426f; +op3val:0x0; valaddr_reg:x10; val_offset:3*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x30, x13, x22, x0, dyn, 96, 0, x10, 3*FLEN/8, x12, x4, x2) +RVTEST_SIGBASE(x8,signature_x8_0) + +inst_15: +// rs1==x6, rs2==x26, rs3==x3, rd==x11,fs1 == 0 and fe1 == 0x1e and fm1 == 0x11b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0a9 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1f4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x6; op2:x26; op3:x3; dest:x11; op1val:0x791b; op2val:0x38a9; +op3val:0x75f4; valaddr_reg:x10; val_offset:6*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x11, x6, x26, x3, dyn, 96, 0, x10, 6*FLEN/8, x12, x8, x2) + +inst_16: +// rs1==x20, rs2==x31, rs3==x30, rd==x1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x061 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x356 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x004 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x20; op2:x31; op3:x30; dest:x1; op1val:0x7861; op2val:0x2f56; +op3val:0x6c04; valaddr_reg:x10; val_offset:9*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x1, x20, x31, x30, dyn, 96, 0, x10, 9*FLEN/8, x12, x8, x2) + +inst_17: +// rs1==x24, rs2==x30, rs3==x7, rd==x28,fs1 == 0 and fe1 == 0x1a and fm1 == 0x3a0 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x2e8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x296 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x24; op2:x30; op3:x7; dest:x28; op1val:0x6ba0; op2val:0x42e8; +op3val:0x7296; valaddr_reg:x10; val_offset:12*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x28, x24, x30, x7, dyn, 96, 0, x10, 12*FLEN/8, x12, x8, x2) + +inst_18: +// rs1==x5, rs2==x14, rs3==x23, rd==x20,fs1 == 0 and fe1 == 0x1e and fm1 == 0x170 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x107 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2d6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x5; op2:x14; op3:x23; dest:x20; op1val:0x7970; op2val:0x3907; +op3val:0x76d6; valaddr_reg:x10; val_offset:15*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x20, x5, x14, x23, dyn, 96, 0, x10, 15*FLEN/8, x12, x8, x2) + +inst_19: +// rs1==x28, rs2==x3, rs3==x5, rd==x22,fs1 == 0 and fe1 == 0x1d and fm1 == 0x106 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x374 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0ae and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x28; op2:x3; op3:x5; dest:x22; op1val:0x7506; op2val:0x3f74; +op3val:0x78ae; valaddr_reg:x10; val_offset:18*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x22, x28, x3, x5, dyn, 96, 0, x10, 18*FLEN/8, x12, x8, x2) + +inst_20: +// rs1==x30, rs2==x23, rs3==x19, rd==x24,fs1 == 0 and fe1 == 0x1d and fm1 == 0x33f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x14a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0cb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x23; op3:x19; dest:x24; op1val:0x773f; op2val:0x394a; +op3val:0x74cb; valaddr_reg:x10; val_offset:21*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x24, x30, x23, x19, dyn, 96, 0, x10, 21*FLEN/8, x12, x8, x2) + +inst_21: +// rs1==x3, rs2==x20, rs3==x1, rd==x31,fs1 == 0 and fe1 == 0x1e and fm1 == 0x25a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x30a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x196 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x3; op2:x20; op3:x1; dest:x31; op1val:0x7a5a; op2val:0x3b0a; +op3val:0x7996; valaddr_reg:x10; val_offset:24*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x3, x20, x1, dyn, 96, 0, x10, 24*FLEN/8, x12, x8, x2) + +inst_22: +// rs1==x26, rs2==x5, rs3==x2, rd==x7,fs1 == 0 and fe1 == 0x1c and fm1 == 0x3ce and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0b4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x097 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x26; op2:x5; op3:x2; dest:x7; op1val:0x73ce; op2val:0x40b4; +op3val:0x7897; valaddr_reg:x10; val_offset:27*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x7, x26, x5, x2, dyn, 96, 0, x10, 27*FLEN/8, x12, x8, x2) + +inst_23: +// rs1==x25, rs2==x6, rs3==x13, rd==x15,fs1 == 0 and fe1 == 0x1e and fm1 == 0x033 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2aa and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x25; op2:x6; op3:x13; dest:x15; op1val:0x7833; op2val:0x3eaa; +op3val:0x7aff; valaddr_reg:x10; val_offset:30*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x15, x25, x6, x13, dyn, 96, 0, x10, 30*FLEN/8, x12, x8, x2) + +inst_24: +// rs1==x0, rs2==x27, rs3==x22, rd==x9,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x250 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x09a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x0; op2:x27; op3:x22; dest:x9; op1val:0x0; op2val:0x3650; +op3val:0x749a; valaddr_reg:x10; val_offset:33*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x9, x0, x27, x22, dyn, 96, 0, x10, 33*FLEN/8, x12, x8, x2) +RVTEST_VALBASEUPD(x7,test_dataset_2) + +inst_25: +// rs1==x12, rs2==x19, rs3==x16, rd==x4,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3b5 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x38d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x12; op2:x19; op3:x16; dest:x4; op1val:0x7bd6; op2val:0x2fb5; +op3val:0x6f8d; valaddr_reg:x7; val_offset:0*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x4, x12, x19, x16, dyn, 96, 0, x7, 0*FLEN/8, x10, x8, x2) + +inst_26: +// rs1==x22, rs2==x0, rs3==x28, rd==x5,fs1 == 0 and fe1 == 0x1d and fm1 == 0x2af and fs2 == 0 and fe2 == 0x0f and fm2 == 0x33e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x20d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x22; op2:x0; op3:x28; dest:x5; op1val:0x76af; op2val:0x0; +op3val:0x7a0d; valaddr_reg:x7; val_offset:3*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x5, x22, x0, x28, dyn, 96, 0, x7, 3*FLEN/8, x10, x8, x2) + +inst_27: +// rs1==x15, rs2==x16, rs3==x27, rd==x0,fs1 == 0 and fe1 == 0x1c and fm1 == 0x0dc and fs2 == 0 and fe2 == 0x10 and fm2 == 0x26f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3d1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x15; op2:x16; op3:x27; dest:x0; op1val:0x70dc; op2val:0x426f; +op3val:0x77d1; valaddr_reg:x7; val_offset:6*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x0, x15, x16, x27, dyn, 96, 0, x7, 6*FLEN/8, x10, x8, x2) + +inst_28: +// rs1==x9, rs2==x11, rs3==x6, rd==x21,fs1 == 0 and fe1 == 0x1a and fm1 == 0x104 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x042 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x157 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x9; op2:x11; op3:x6; dest:x21; op1val:0x6904; op2val:0x4c42; +op3val:0x7957; valaddr_reg:x7; val_offset:9*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x21, x9, x11, x6, dyn, 96, 0, x7, 9*FLEN/8, x10, x8, x3) + +inst_29: +// rs1==x17, rs2==x21, rs3==x9, rd==x2,fs1 == 0 and fe1 == 0x1e and fm1 == 0x21d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x094 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x17; op2:x21; op3:x9; dest:x2; op1val:0x7a1d; op2val:0x39fe; +op3val:0x7894; valaddr_reg:x7; val_offset:12*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x2, x17, x21, x9, dyn, 96, 0, x7, 12*FLEN/8, x10, x8, x3) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_30: +// rs1==x16, rs2==x25, rs3==x20, rd==x6,fs1 == 0 and fe1 == 0x1e and fm1 == 0x300 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1bb and fs3 == 0 and fe3 == 0x1d and fm3 == 0x104 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x16; op2:x25; op3:x20; dest:x6; op1val:0x7b00; op2val:0x35bb; +op3val:0x7504; valaddr_reg:x7; val_offset:15*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x6, x16, x25, x20, dyn, 96, 0, x7, 15*FLEN/8, x10, x1, x3) + +inst_31: +// rs1==x4,fs1 == 0 and fe1 == 0x1e and fm1 == 0x18f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0c0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x4; op2:x29; op3:x18; dest:x13; op1val:0x798f; op2val:0x3ad6; +op3val:0x78c0; valaddr_reg:x7; val_offset:18*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x13, x4, x29, x18, dyn, 96, 0, x7, 18*FLEN/8, x10, x1, x3) + +inst_32: +// rs2==x4,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x24b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x34b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x25; op2:x4; op3:x26; dest:x6; op1val:0x78a3; op2val:0x3a4b; +op3val:0x774b; valaddr_reg:x7; val_offset:21*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x6, x25, x4, x26, dyn, 96, 0, x7, 21*FLEN/8, x10, x1, x3) + +inst_33: +// rs3==x31,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x07f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x38d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x18; op2:x5; op3:x31; dest:x30; op1val:0x7ab7; op2val:0x3c7f; +op3val:0x7b8d; valaddr_reg:x7; val_offset:24*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x30, x18, x5, x31, dyn, 96, 0, x7, 24*FLEN/8, x10, x1, x3) + +inst_34: +// rd==x16,fs1 == 0 and fe1 == 0x1d and fm1 == 0x394 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x19a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x21; op2:x28; op3:x9; dest:x16; op1val:0x7794; op2val:0x3d9a; +op3val:0x794f; valaddr_reg:x7; val_offset:27*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x16, x21, x28, x9, dyn, 96, 0, x7, 27*FLEN/8, x10, x1, x3) + +inst_35: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3c3 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x1c7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x19b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6bc3; op2val:0x49c7; +op3val:0x799b; valaddr_reg:x7; val_offset:30*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x7, 30*FLEN/8, x10, x1, x3) + +inst_36: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x223 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3f0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x792c; op2val:0x3e23; +op3val:0x7bf0; valaddr_reg:x7; val_offset:33*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x7, 33*FLEN/8, x10, x1, x3) + +inst_37: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x292 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x18a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x08d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a92; op2val:0x358a; +op3val:0x748d; valaddr_reg:x7; val_offset:36*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x7, 36*FLEN/8, x10, x1, x3) + +inst_38: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x22b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2ee and fs3 == 0 and fe3 == 0x1e and fm3 == 0x158 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x762b; op2val:0x3eee; +op3val:0x7958; valaddr_reg:x7; val_offset:39*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x7, 39*FLEN/8, x10, x1, x3) + +inst_39: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x1c6 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x11c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x362 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x65c6; op2val:0x4d1c; +op3val:0x7762; valaddr_reg:x7; val_offset:42*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x7, 42*FLEN/8, x10, x1, x3) + +inst_40: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x160 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x193 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x37d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7160; op2val:0x3993; +op3val:0x6f7d; valaddr_reg:x7; val_offset:45*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x7, 45*FLEN/8, x10, x1, x3) + +inst_41: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x38b and fs2 == 0 and fe2 == 0x12 and fm2 == 0x283 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x224 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6b8b; op2val:0x4a83; +op3val:0x7a24; valaddr_reg:x7; val_offset:48*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x7, 48*FLEN/8, x10, x1, x3) + +inst_42: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x023 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3b0 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3eb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7023; op2val:0x3fb0; +op3val:0x73eb; valaddr_reg:x7; val_offset:51*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x7, 51*FLEN/8, x10, x1, x3) + +inst_43: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x240 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x076 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7640; op2val:0x4076; +op3val:0x7af7; valaddr_reg:x7; val_offset:54*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x7, 54*FLEN/8, x10, x1, x3) + +inst_44: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x127 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x195 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x32f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d27; op2val:0x4595; +op3val:0x772f; valaddr_reg:x7; val_offset:57*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x7, 57*FLEN/8, x10, x1, x3) + +inst_45: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x064 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x270 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x310 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7864; op2val:0x3e70; +op3val:0x7b10; valaddr_reg:x7; val_offset:60*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x7, 60*FLEN/8, x10, x1, x3) + +inst_46: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x039 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2e8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8d; op2val:0x3c39; +op3val:0x7ae8; valaddr_reg:x7; val_offset:63*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x7, 63*FLEN/8, x10, x1, x3) + +inst_47: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x073 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1fa and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2a4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7473; op2val:0x3dfa; +op3val:0x76a4; valaddr_reg:x7; val_offset:66*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x7, 66*FLEN/8, x10, x1, x3) + +inst_48: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1bc and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0ef and fs3 == 0 and fe3 == 0x1e and fm3 == 0x311 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75bc; op2val:0x40ef; +op3val:0x7b11; valaddr_reg:x7; val_offset:69*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x7, 69*FLEN/8, x10, x1, x3) + +inst_49: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a8 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x10b and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ba8; op2val:0x310b; +op3val:0x70d3; valaddr_reg:x7; val_offset:72*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x7, 72*FLEN/8, x10, x1, x3) + +inst_50: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1a2 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x143 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x36b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71a2; op2val:0x3d43; +op3val:0x736b; valaddr_reg:x7; val_offset:75*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x7, 75*FLEN/8, x10, x1, x3) + +inst_51: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x376 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x028 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3c1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7376; op2val:0x4028; +op3val:0x77c1; valaddr_reg:x7; val_offset:78*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x7, 78*FLEN/8, x10, x1, x3) + +inst_52: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b5 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x322 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x033 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78b5; op2val:0x3722; +op3val:0x7433; valaddr_reg:x7; val_offset:81*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x7, 81*FLEN/8, x10, x1, x3) + +inst_53: +// fs1 == 0 and fe1 == 0x17 and fm1 == 0x034 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x25f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2b3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5c34; op2val:0x565f; +op3val:0x76b3; valaddr_reg:x7; val_offset:84*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x7, 84*FLEN/8, x10, x1, x3) + +inst_54: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1e7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x222 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x087 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75e7; op2val:0x3e22; +op3val:0x7887; valaddr_reg:x7; val_offset:87*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x7, 87*FLEN/8, x10, x1, x3) + +inst_55: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x39e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1cb and fs3 == 0 and fe3 == 0x1e and fm3 == 0x185 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b9e; op2val:0x39cb; +op3val:0x7985; valaddr_reg:x7; val_offset:90*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x7, 90*FLEN/8, x10, x1, x3) + +inst_56: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x12d and fs2 == 0 and fe2 == 0x0d and fm2 == 0x374 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x752d; op2val:0x3774; +op3val:0x70d3; valaddr_reg:x7; val_offset:93*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x7, 93*FLEN/8, x10, x1, x3) + +inst_57: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x048 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x175 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1d9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7848; op2val:0x3975; +op3val:0x75d9; valaddr_reg:x7; val_offset:96*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x7, 96*FLEN/8, x10, x1, x3) + +inst_58: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x36c and fs2 == 0 and fe2 == 0x12 and fm2 == 0x05f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6b6c; op2val:0x485f; +op3val:0x780e; valaddr_reg:x7; val_offset:99*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x7, 99*FLEN/8, x10, x1, x3) + +inst_59: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x0cc and fs2 == 0 and fe2 == 0x12 and fm2 == 0x1c7 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2ef and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x68cc; op2val:0x49c7; +op3val:0x76ef; valaddr_reg:x7; val_offset:102*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x7, 102*FLEN/8, x10, x1, x3) + +inst_60: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x104 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x20a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x393 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7904; op2val:0x3e0a; +op3val:0x7b93; valaddr_reg:x7; val_offset:105*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x7, 105*FLEN/8, x10, x1, x3) + +inst_61: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x17f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x258 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x789d; op2val:0x397f; +op3val:0x7658; valaddr_reg:x7; val_offset:108*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x7, 108*FLEN/8, x10, x1, x3) + +inst_62: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ce and fs2 == 0 and fe2 == 0x0a and fm2 == 0x21c and fs3 == 0 and fe3 == 0x1a and fm3 == 0x1f6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bce; op2val:0x2a1c; +op3val:0x69f6; valaddr_reg:x7; val_offset:111*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x7, 111*FLEN/8, x10, x1, x3) + +inst_63: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2dd and fs2 == 0 and fe2 == 0x0d and fm2 == 0x165 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7add; op2val:0x3565; +op3val:0x74a1; valaddr_reg:x7; val_offset:114*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x7, 114*FLEN/8, x10, x1, x3) + +inst_64: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x26f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71c7; op2val:0x426f; +op3val:0x78a6; valaddr_reg:x7; val_offset:117*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x7, 117*FLEN/8, x10, x1, x3) + +inst_65: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x250 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x09a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79d5; op2val:0x3650; +op3val:0x749a; valaddr_reg:x7; val_offset:120*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x7, 120*FLEN/8, x10, x1, x3) + +inst_66: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2af and fs2 == 0 and fe2 == 0x0f and fm2 == 0x33e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x20d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76af; op2val:0x3f3e; +op3val:0x7a0d; valaddr_reg:x7; val_offset:123*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x7, 123*FLEN/8, x10, x1, x3) + +inst_67: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0dc and fs2 == 0 and fe2 == 0x10 and fm2 == 0x26f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3d1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70dc; op2val:0x426f; +op3val:0x77d1; valaddr_reg:x7; val_offset:126*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x7, 126*FLEN/8, x10, x1, x3) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(29997,32,FLEN) +NAN_BOXED(29997,32,FLEN) +NAN_BOXED(29997,32,FLEN) +NAN_BOXED(31028,32,FLEN) +NAN_BOXED(12063,32,FLEN) +NAN_BOXED(27810,32,FLEN) +NAN_BOXED(30792,32,FLEN) +NAN_BOXED(30792,32,FLEN) +NAN_BOXED(30169,32,FLEN) +NAN_BOXED(27500,32,FLEN) +NAN_BOXED(18527,32,FLEN) +NAN_BOXED(18527,32,FLEN) +NAN_BOXED(26828,32,FLEN) +NAN_BOXED(26828,32,FLEN) +NAN_BOXED(26828,32,FLEN) +NAN_BOXED(27768,32,FLEN) +NAN_BOXED(15665,32,FLEN) +NAN_BOXED(28109,32,FLEN) +NAN_BOXED(30410,32,FLEN) +NAN_BOXED(16330,32,FLEN) +NAN_BOXED(31388,32,FLEN) +NAN_BOXED(28651,32,FLEN) +NAN_BOXED(16182,32,FLEN) +NAN_BOXED(29475,32,FLEN) +NAN_BOXED(30980,32,FLEN) +NAN_BOXED(15882,32,FLEN) +NAN_BOXED(15882,32,FLEN) +NAN_BOXED(30877,32,FLEN) +NAN_BOXED(30877,32,FLEN) +NAN_BOXED(30296,32,FLEN) +NAN_BOXED(31694,32,FLEN) +NAN_BOXED(10780,32,FLEN) +NAN_BOXED(31694,32,FLEN) +NAN_BOXED(31453,32,FLEN) +NAN_BOXED(13669,32,FLEN) +NAN_BOXED(31453,32,FLEN) +NAN_BOXED(28829,32,FLEN) +NAN_BOXED(14984,32,FLEN) +NAN_BOXED(28553,32,FLEN) +test_dataset_1: +NAN_BOXED(29934,32,FLEN) +NAN_BOXED(16714,32,FLEN) +NAN_BOXED(31366,32,FLEN) +NAN_BOXED(29127,32,FLEN) +NAN_BOXED(17007,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31003,32,FLEN) +NAN_BOXED(14505,32,FLEN) +NAN_BOXED(30196,32,FLEN) +NAN_BOXED(30817,32,FLEN) +NAN_BOXED(12118,32,FLEN) +NAN_BOXED(27652,32,FLEN) +NAN_BOXED(27552,32,FLEN) +NAN_BOXED(17128,32,FLEN) +NAN_BOXED(29334,32,FLEN) +NAN_BOXED(31088,32,FLEN) +NAN_BOXED(14599,32,FLEN) +NAN_BOXED(30422,32,FLEN) +NAN_BOXED(29958,32,FLEN) +NAN_BOXED(16244,32,FLEN) +NAN_BOXED(30894,32,FLEN) +NAN_BOXED(30527,32,FLEN) +NAN_BOXED(14666,32,FLEN) +NAN_BOXED(29899,32,FLEN) +NAN_BOXED(31322,32,FLEN) +NAN_BOXED(15114,32,FLEN) +NAN_BOXED(31126,32,FLEN) +NAN_BOXED(29646,32,FLEN) +NAN_BOXED(16564,32,FLEN) +NAN_BOXED(30871,32,FLEN) +NAN_BOXED(30771,32,FLEN) +NAN_BOXED(16042,32,FLEN) +NAN_BOXED(31487,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(13904,32,FLEN) +NAN_BOXED(29850,32,FLEN) +test_dataset_2: +NAN_BOXED(31702,16,FLEN) +NAN_BOXED(12213,16,FLEN) +NAN_BOXED(28557,16,FLEN) +NAN_BOXED(30383,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31245,16,FLEN) +NAN_BOXED(28892,16,FLEN) +NAN_BOXED(17007,16,FLEN) +NAN_BOXED(30673,16,FLEN) +NAN_BOXED(26884,16,FLEN) +NAN_BOXED(19522,16,FLEN) +NAN_BOXED(31063,16,FLEN) +NAN_BOXED(31261,16,FLEN) +NAN_BOXED(14846,16,FLEN) +NAN_BOXED(30868,16,FLEN) +NAN_BOXED(31488,16,FLEN) +NAN_BOXED(13755,16,FLEN) +NAN_BOXED(29956,16,FLEN) +NAN_BOXED(31119,16,FLEN) +NAN_BOXED(15062,16,FLEN) +NAN_BOXED(30912,16,FLEN) +NAN_BOXED(30883,16,FLEN) +NAN_BOXED(14923,16,FLEN) +NAN_BOXED(30539,16,FLEN) +NAN_BOXED(31415,16,FLEN) +NAN_BOXED(15487,16,FLEN) +NAN_BOXED(31629,16,FLEN) +NAN_BOXED(30612,16,FLEN) +NAN_BOXED(15770,16,FLEN) +NAN_BOXED(31055,16,FLEN) +NAN_BOXED(27587,16,FLEN) +NAN_BOXED(18887,16,FLEN) +NAN_BOXED(31131,16,FLEN) +NAN_BOXED(31020,16,FLEN) +NAN_BOXED(15907,16,FLEN) +NAN_BOXED(31728,16,FLEN) +NAN_BOXED(31378,16,FLEN) +NAN_BOXED(13706,16,FLEN) +NAN_BOXED(29837,16,FLEN) +NAN_BOXED(30251,16,FLEN) +NAN_BOXED(16110,16,FLEN) +NAN_BOXED(31064,16,FLEN) +NAN_BOXED(26054,16,FLEN) +NAN_BOXED(19740,16,FLEN) +NAN_BOXED(30562,16,FLEN) +NAN_BOXED(29024,16,FLEN) +NAN_BOXED(14739,16,FLEN) +NAN_BOXED(28541,16,FLEN) +NAN_BOXED(27531,16,FLEN) +NAN_BOXED(19075,16,FLEN) +NAN_BOXED(31268,16,FLEN) +NAN_BOXED(28707,16,FLEN) +NAN_BOXED(16304,16,FLEN) +NAN_BOXED(29675,16,FLEN) +NAN_BOXED(30272,16,FLEN) +NAN_BOXED(16502,16,FLEN) +NAN_BOXED(31479,16,FLEN) +NAN_BOXED(27943,16,FLEN) +NAN_BOXED(17813,16,FLEN) +NAN_BOXED(30511,16,FLEN) +NAN_BOXED(30820,16,FLEN) +NAN_BOXED(15984,16,FLEN) +NAN_BOXED(31504,16,FLEN) +NAN_BOXED(31373,16,FLEN) +NAN_BOXED(15417,16,FLEN) +NAN_BOXED(31464,16,FLEN) +NAN_BOXED(29811,16,FLEN) +NAN_BOXED(15866,16,FLEN) +NAN_BOXED(30372,16,FLEN) +NAN_BOXED(30140,16,FLEN) +NAN_BOXED(16623,16,FLEN) +NAN_BOXED(31505,16,FLEN) +NAN_BOXED(31656,16,FLEN) +NAN_BOXED(12555,16,FLEN) +NAN_BOXED(28883,16,FLEN) +NAN_BOXED(29090,16,FLEN) +NAN_BOXED(15683,16,FLEN) +NAN_BOXED(29547,16,FLEN) +NAN_BOXED(29558,16,FLEN) +NAN_BOXED(16424,16,FLEN) +NAN_BOXED(30657,16,FLEN) +NAN_BOXED(30901,16,FLEN) +NAN_BOXED(14114,16,FLEN) +NAN_BOXED(29747,16,FLEN) +NAN_BOXED(23604,16,FLEN) +NAN_BOXED(22111,16,FLEN) +NAN_BOXED(30387,16,FLEN) +NAN_BOXED(30183,16,FLEN) +NAN_BOXED(15906,16,FLEN) +NAN_BOXED(30855,16,FLEN) +NAN_BOXED(31646,16,FLEN) +NAN_BOXED(14795,16,FLEN) +NAN_BOXED(31109,16,FLEN) +NAN_BOXED(29997,16,FLEN) +NAN_BOXED(14196,16,FLEN) +NAN_BOXED(28883,16,FLEN) +NAN_BOXED(30792,16,FLEN) +NAN_BOXED(14709,16,FLEN) +NAN_BOXED(30169,16,FLEN) +NAN_BOXED(27500,16,FLEN) +NAN_BOXED(18527,16,FLEN) +NAN_BOXED(30734,16,FLEN) +NAN_BOXED(26828,16,FLEN) +NAN_BOXED(18887,16,FLEN) +NAN_BOXED(30447,16,FLEN) +NAN_BOXED(30980,16,FLEN) +NAN_BOXED(15882,16,FLEN) +NAN_BOXED(31635,16,FLEN) +NAN_BOXED(30877,16,FLEN) +NAN_BOXED(14719,16,FLEN) +NAN_BOXED(30296,16,FLEN) +NAN_BOXED(31694,16,FLEN) +NAN_BOXED(10780,16,FLEN) +NAN_BOXED(27126,16,FLEN) +NAN_BOXED(31453,16,FLEN) +NAN_BOXED(13669,16,FLEN) +NAN_BOXED(29857,16,FLEN) +NAN_BOXED(29127,16,FLEN) +NAN_BOXED(17007,16,FLEN) +NAN_BOXED(30886,16,FLEN) +NAN_BOXED(31189,16,FLEN) +NAN_BOXED(13904,16,FLEN) +NAN_BOXED(29850,16,FLEN) +NAN_BOXED(30383,16,FLEN) +NAN_BOXED(16190,16,FLEN) +NAN_BOXED(31245,16,FLEN) +NAN_BOXED(28892,16,FLEN) +NAN_BOXED(17007,16,FLEN) +NAN_BOXED(30673,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x4_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x4_1: + .fill 30*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x8_0: + .fill 30*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_0: + .fill 76*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fmsub_b8-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fmsub_b8-01.S new file mode 100644 index 000000000..12a86b3dd --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fmsub_b8-01.S @@ -0,0 +1,17086 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 05:33:17 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fmsub.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fmsub.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fmsub_b8 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fmsub_b8) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x5,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rs2 == rs3 != rd, rs1==x11, rs2==x11, rs3==x11, rd==x27,fs1 == 0 and fe1 == 0x0e and fm1 == 0x168 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x105 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2cb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x11; op2:x11; op3:x11; dest:x27; op1val:0x3968; op2val:0x3968; +op3val:0x3968; valaddr_reg:x5; val_offset:0*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x27, x11, x11, x11, dyn, 0, 0, x5, 0*FLEN/8, x17, x1, x3) + +inst_1: +// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==x10, rs2==x13, rs3==x17, rd==x25,fs1 == 0 and fe1 == 0x0e and fm1 == 0x168 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x105 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2cb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x10; op2:x13; op3:x17; dest:x25; op1val:0x3968; op2val:0x3d05; +op3val:0x3acb; valaddr_reg:x5; val_offset:3*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x25, x10, x13, x17, dyn, 32, 0, x5, 3*FLEN/8, x17, x1, x3) + +inst_2: +// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==x14, rs2==x14, rs3==x1, rd==x23,fs1 == 0 and fe1 == 0x0e and fm1 == 0x168 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x105 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2cb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x14; op2:x14; op3:x1; dest:x23; op1val:0x3968; op2val:0x3968; +op3val:0x3acb; valaddr_reg:x5; val_offset:6*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x23, x14, x14, x1, dyn, 64, 0, x5, 6*FLEN/8, x17, x1, x3) + +inst_3: +// rd == rs2 == rs3 != rs1, rs1==x22, rs2==x26, rs3==x26, rd==x26,fs1 == 0 and fe1 == 0x0e and fm1 == 0x168 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x105 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2cb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x22; op2:x26; op3:x26; dest:x26; op1val:0x3968; op2val:0x3d05; +op3val:0x3d05; valaddr_reg:x5; val_offset:9*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x26, x22, x26, x26, dyn, 96, 0, x5, 9*FLEN/8, x17, x1, x3) + +inst_4: +// rs1 == rs2 == rs3 == rd, rs1==x4, rs2==x4, rs3==x4, rd==x4,fs1 == 0 and fe1 == 0x0e and fm1 == 0x168 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x105 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2cb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x4; op2:x4; op3:x4; dest:x4; op1val:0x3968; op2val:0x3968; +op3val:0x3968; valaddr_reg:x5; val_offset:12*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x4, x4, x4, x4, dyn, 128, 0, x5, 12*FLEN/8, x17, x1, x3) + +inst_5: +// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==x20, rs2==x9, rs3==x3, rd==x9,fs1 == 0 and fe1 == 0x0d and fm1 == 0x195 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x150 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x36b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x20; op2:x9; op3:x3; dest:x9; op1val:0x3595; op2val:0x4150; +op3val:0x3b6b; valaddr_reg:x5; val_offset:15*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x9, x20, x9, x3, dyn, 0, 0, x5, 15*FLEN/8, x17, x1, x3) + +inst_6: +// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==x13, rs2==x21, rs3==x6, rd==x6,fs1 == 0 and fe1 == 0x0d and fm1 == 0x195 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x150 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x36b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x13; op2:x21; op3:x6; dest:x6; op1val:0x3595; op2val:0x4150; +op3val:0x3b6b; valaddr_reg:x5; val_offset:18*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x6, x13, x21, x6, dyn, 32, 0, x5, 18*FLEN/8, x17, x1, x3) + +inst_7: +// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==x18, rs2==x2, rs3==x23, rd==x18,fs1 == 0 and fe1 == 0x0d and fm1 == 0x195 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x150 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x36b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x18; op2:x2; op3:x23; dest:x18; op1val:0x3595; op2val:0x4150; +op3val:0x3b6b; valaddr_reg:x5; val_offset:21*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x18, x18, x2, x23, dyn, 64, 0, x5, 21*FLEN/8, x17, x1, x3) + +inst_8: +// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==x21, rs2==x15, rs3==x15, rd==x12,fs1 == 0 and fe1 == 0x0d and fm1 == 0x195 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x150 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x36b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x21; op2:x15; op3:x15; dest:x12; op1val:0x3595; op2val:0x4150; +op3val:0x4150; valaddr_reg:x5; val_offset:24*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x12, x21, x15, x15, dyn, 96, 0, x5, 24*FLEN/8, x17, x1, x3) + +inst_9: +// rs1 == rs2 == rd != rs3, rs1==x24, rs2==x24, rs3==x19, rd==x24,fs1 == 0 and fe1 == 0x0d and fm1 == 0x195 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x150 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x36b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x24; op2:x24; op3:x19; dest:x24; op1val:0x3595; op2val:0x3595; +op3val:0x3b6b; valaddr_reg:x5; val_offset:27*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x24, x24, x24, x19, dyn, 128, 0, x5, 27*FLEN/8, x17, x1, x3) + +inst_10: +// rs1 == rd == rs3 != rs2, rs1==x16, rs2==x8, rs3==x16, rd==x16,fs1 == 0 and fe1 == 0x0d and fm1 == 0x36d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x177 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x113 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x16; op2:x8; op3:x16; dest:x16; op1val:0x376d; op2val:0x3d77; +op3val:0x376d; valaddr_reg:x5; val_offset:30*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x16, x16, x8, x16, dyn, 0, 0, x5, 30*FLEN/8, x17, x1, x3) + +inst_11: +// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==x7, rs2==x10, rs3==x7, rd==x11,fs1 == 0 and fe1 == 0x0d and fm1 == 0x36d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x177 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x113 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x7; op2:x10; op3:x7; dest:x11; op1val:0x376d; op2val:0x3d77; +op3val:0x376d; valaddr_reg:x5; val_offset:33*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x11, x7, x10, x7, dyn, 32, 0, x5, 33*FLEN/8, x17, x1, x3) +RVTEST_VALBASEUPD(x12,test_dataset_1) + +inst_12: +// rs1==x25, rs2==x27, rs3==x24, rd==x29,fs1 == 0 and fe1 == 0x0d and fm1 == 0x36d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x177 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x113 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x25; op2:x27; op3:x24; dest:x29; op1val:0x376d; op2val:0x3d77; +op3val:0x3913; valaddr_reg:x12; val_offset:0*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x29, x25, x27, x24, dyn, 64, 0, x12, 0*FLEN/8, x13, x1, x3) + +inst_13: +// rs1==x27, rs2==x17, rs3==x29, rd==x19,fs1 == 0 and fe1 == 0x0d and fm1 == 0x36d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x177 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x113 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x27; op2:x17; op3:x29; dest:x19; op1val:0x376d; op2val:0x3d77; +op3val:0x3913; valaddr_reg:x12; val_offset:3*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x19, x27, x17, x29, dyn, 96, 0, x12, 3*FLEN/8, x13, x1, x3) +RVTEST_SIGBASE(x4,signature_x4_0) + +inst_14: +// rs1==x6, rs2==x23, rs3==x14, rd==x2,fs1 == 0 and fe1 == 0x0d and fm1 == 0x36d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x177 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x113 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x6; op2:x23; op3:x14; dest:x2; op1val:0x376d; op2val:0x3d77; +op3val:0x3913; valaddr_reg:x12; val_offset:6*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x2, x6, x23, x14, dyn, 128, 0, x12, 6*FLEN/8, x13, x4, x11) + +inst_15: +// rs1==x1, rs2==x31, rs3==x8, rd==x3,fs1 == 0 and fe1 == 0x0e and fm1 == 0x389 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x02e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3e1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x1; op2:x31; op3:x8; dest:x3; op1val:0x3b89; op2val:0x382e; +op3val:0x37e1; valaddr_reg:x12; val_offset:9*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x3, x1, x31, x8, dyn, 0, 0, x12, 9*FLEN/8, x13, x4, x11) + +inst_16: +// rs1==x26, rs2==x6, rs3==x0, rd==x31,fs1 == 0 and fe1 == 0x0e and fm1 == 0x389 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x02e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3e1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x26; op2:x6; op3:x0; dest:x31; op1val:0x3b89; op2val:0x382e; +op3val:0x0; valaddr_reg:x12; val_offset:12*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x26, x6, x0, dyn, 32, 0, x12, 12*FLEN/8, x13, x4, x11) + +inst_17: +// rs1==x8, rs2==x0, rs3==x30, rd==x20,fs1 == 0 and fe1 == 0x0e and fm1 == 0x389 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x02e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3e1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x8; op2:x0; op3:x30; dest:x20; op1val:0x3b89; op2val:0x0; +op3val:0x37e1; valaddr_reg:x12; val_offset:15*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x20, x8, x0, x30, dyn, 64, 0, x12, 15*FLEN/8, x13, x4, x11) + +inst_18: +// rs1==x15, rs2==x28, rs3==x2, rd==x17,fs1 == 0 and fe1 == 0x0e and fm1 == 0x389 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x02e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3e1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x15; op2:x28; op3:x2; dest:x17; op1val:0x3b89; op2val:0x382e; +op3val:0x37e1; valaddr_reg:x12; val_offset:18*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x17, x15, x28, x2, dyn, 96, 0, x12, 18*FLEN/8, x13, x4, x11) + +inst_19: +// rs1==x9, rs2==x30, rs3==x18, rd==x10,fs1 == 0 and fe1 == 0x0e and fm1 == 0x389 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x02e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3e1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x9; op2:x30; op3:x18; dest:x10; op1val:0x3b89; op2val:0x382e; +op3val:0x37e1; valaddr_reg:x12; val_offset:21*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x10, x9, x30, x18, dyn, 128, 0, x12, 21*FLEN/8, x13, x4, x11) + +inst_20: +// rs1==x3, rs2==x7, rs3==x12, rd==x5,fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0b5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x087 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x3; op2:x7; op3:x12; dest:x5; op1val:0x3bb3; op2val:0x38b5; +op3val:0x3887; valaddr_reg:x12; val_offset:24*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x5, x3, x7, x12, dyn, 0, 0, x12, 24*FLEN/8, x13, x4, x11) + +inst_21: +// rs1==x19, rs2==x29, rs3==x25, rd==x0,fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0b5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x087 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x19; op2:x29; op3:x25; dest:x0; op1val:0x3bb3; op2val:0x38b5; +op3val:0x3887; valaddr_reg:x12; val_offset:27*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x0, x19, x29, x25, dyn, 32, 0, x12, 27*FLEN/8, x13, x4, x11) + +inst_22: +// rs1==x30, rs2==x22, rs3==x27, rd==x21,fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0b5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x087 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x22; op3:x27; dest:x21; op1val:0x3bb3; op2val:0x38b5; +op3val:0x3887; valaddr_reg:x12; val_offset:30*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x21, x30, x22, x27, dyn, 64, 0, x12, 30*FLEN/8, x13, x4, x11) +RVTEST_VALBASEUPD(x3,test_dataset_2) + +inst_23: +// rs1==x29, rs2==x16, rs3==x9, rd==x15,fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0b5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x087 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x29; op2:x16; op3:x9; dest:x15; op1val:0x3bb3; op2val:0x38b5; +op3val:0x3887; valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x15, x29, x16, x9, dyn, 96, 0, x3, 0*FLEN/8, x9, x4, x11) + +inst_24: +// rs1==x2, rs2==x25, rs3==x13, rd==x14,fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0b5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x087 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x2; op2:x25; op3:x13; dest:x14; op1val:0x3bb3; op2val:0x38b5; +op3val:0x3887; valaddr_reg:x3; val_offset:3*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x14, x2, x25, x13, dyn, 128, 0, x3, 3*FLEN/8, x9, x4, x11) + +inst_25: +// rs1==x0, rs2==x5, rs3==x21, rd==x30,fs1 == 0 and fe1 == 0x0e and fm1 == 0x370 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3d2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x346 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x0; op2:x5; op3:x21; dest:x30; op1val:0x0; op2val:0x3bd2; +op3val:0x3b46; valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x30, x0, x5, x21, dyn, 0, 0, x3, 6*FLEN/8, x9, x4, x6) + +inst_26: +// rs1==x31, rs2==x19, rs3==x5, rd==x28,fs1 == 0 and fe1 == 0x0e and fm1 == 0x370 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3d2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x346 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x31; op2:x19; op3:x5; dest:x28; op1val:0x3b70; op2val:0x3bd2; +op3val:0x3b46; valaddr_reg:x3; val_offset:9*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x28, x31, x19, x5, dyn, 32, 0, x3, 9*FLEN/8, x9, x4, x6) + +inst_27: +// rs1==x5, rs2==x1, rs3==x31, rd==x13,fs1 == 0 and fe1 == 0x0e and fm1 == 0x370 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3d2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x346 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x5; op2:x1; op3:x31; dest:x13; op1val:0x3b70; op2val:0x3bd2; +op3val:0x3b46; valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x13, x5, x1, x31, dyn, 64, 0, x3, 12*FLEN/8, x9, x4, x6) +RVTEST_SIGBASE(x2,signature_x2_0) + +inst_28: +// rs1==x12, rs2==x18, rs3==x22, rd==x1,fs1 == 0 and fe1 == 0x0e and fm1 == 0x370 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3d2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x346 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x12; op2:x18; op3:x22; dest:x1; op1val:0x3b70; op2val:0x3bd2; +op3val:0x3b46; valaddr_reg:x3; val_offset:15*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x1, x12, x18, x22, dyn, 96, 0, x3, 15*FLEN/8, x9, x2, x6) + +inst_29: +// rs1==x23, rs2==x20, rs3==x10, rd==x8,fs1 == 0 and fe1 == 0x0e and fm1 == 0x370 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3d2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x346 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x23; op2:x20; op3:x10; dest:x8; op1val:0x3b70; op2val:0x3bd2; +op3val:0x3b46; valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x8, x23, x20, x10, dyn, 128, 0, x3, 18*FLEN/8, x9, x2, x6) + +inst_30: +// rs1==x17, rs2==x12, rs3==x20, rd==x7,fs1 == 0 and fe1 == 0x0e and fm1 == 0x09a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0d0 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x18a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x17; op2:x12; op3:x20; dest:x7; op1val:0x389a; op2val:0x34d0; +op3val:0x318a; valaddr_reg:x3; val_offset:21*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x7, x17, x12, x20, dyn, 0, 0, x3, 21*FLEN/8, x9, x2, x6) + +inst_31: +// rs1==x28,fs1 == 0 and fe1 == 0x0e and fm1 == 0x09a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0d0 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x18a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x28; op2:x21; op3:x10; dest:x18; op1val:0x389a; op2val:0x34d0; +op3val:0x318a; valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x18, x28, x21, x10, dyn, 32, 0, x3, 24*FLEN/8, x9, x2, x6) +RVTEST_VALBASEUPD(x1,test_dataset_3) + +inst_32: +// rs2==x3,fs1 == 0 and fe1 == 0x0e and fm1 == 0x09a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0d0 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x18a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x20; op2:x3; op3:x10; dest:x11; op1val:0x389a; op2val:0x34d0; +op3val:0x318a; valaddr_reg:x1; val_offset:0*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x11, x20, x3, x10, dyn, 64, 0, x1, 0*FLEN/8, x4, x2, x6) + +inst_33: +// rs3==x28,fs1 == 0 and fe1 == 0x0e and fm1 == 0x09a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0d0 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x18a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x16; op2:x31; op3:x28; dest:x13; op1val:0x389a; op2val:0x34d0; +op3val:0x318a; valaddr_reg:x1; val_offset:3*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x13, x16, x31, x28, dyn, 96, 0, x1, 3*FLEN/8, x4, x2, x6) + +inst_34: +// rd==x22,fs1 == 0 and fe1 == 0x0e and fm1 == 0x09a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0d0 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x18a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x24; op2:x25; op3:x17; dest:x22; op1val:0x389a; op2val:0x34d0; +op3val:0x318a; valaddr_reg:x1; val_offset:6*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x22, x24, x25, x17, dyn, 128, 0, x1, 6*FLEN/8, x4, x2, x6) + +inst_35: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x302 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x317 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x236 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b02; op2val:0x3b17; +op3val:0x3a36; valaddr_reg:x1; val_offset:9*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 9*FLEN/8, x4, x2, x6) + +inst_36: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x302 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x317 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x236 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b02; op2val:0x3b17; +op3val:0x3a36; valaddr_reg:x1; val_offset:12*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 12*FLEN/8, x4, x2, x6) + +inst_37: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x302 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x317 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x236 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b02; op2val:0x3b17; +op3val:0x3a36; valaddr_reg:x1; val_offset:15*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 15*FLEN/8, x4, x2, x6) + +inst_38: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x302 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x317 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x236 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b02; op2val:0x3b17; +op3val:0x3a36; valaddr_reg:x1; val_offset:18*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 18*FLEN/8, x4, x2, x6) + +inst_39: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x302 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x317 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x236 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b02; op2val:0x3b17; +op3val:0x3a36; valaddr_reg:x1; val_offset:21*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 21*FLEN/8, x4, x2, x6) + +inst_40: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1f6 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x07d and fs3 == 0 and fe3 == 0x0a and fm3 == 0x2b1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35f6; op2val:0x307d; +op3val:0x2ab1; valaddr_reg:x1; val_offset:24*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 24*FLEN/8, x4, x2, x6) + +inst_41: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1f6 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x07d and fs3 == 0 and fe3 == 0x0a and fm3 == 0x2b1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35f6; op2val:0x307d; +op3val:0x2ab1; valaddr_reg:x1; val_offset:27*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 27*FLEN/8, x4, x2, x6) + +inst_42: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1f6 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x07d and fs3 == 0 and fe3 == 0x0a and fm3 == 0x2b1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35f6; op2val:0x307d; +op3val:0x2ab1; valaddr_reg:x1; val_offset:30*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 30*FLEN/8, x4, x2, x6) + +inst_43: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1f6 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x07d and fs3 == 0 and fe3 == 0x0a and fm3 == 0x2b1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35f6; op2val:0x307d; +op3val:0x2ab1; valaddr_reg:x1; val_offset:33*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 33*FLEN/8, x4, x2, x6) + +inst_44: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1f6 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x07d and fs3 == 0 and fe3 == 0x0a and fm3 == 0x2b1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35f6; op2val:0x307d; +op3val:0x2ab1; valaddr_reg:x1; val_offset:36*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 36*FLEN/8, x4, x2, x6) + +inst_45: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2c4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1b4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0d3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36c4; op2val:0x3db4; +op3val:0x38d3; valaddr_reg:x1; val_offset:39*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 39*FLEN/8, x4, x2, x6) + +inst_46: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2c4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1b4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0d3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36c4; op2val:0x3db4; +op3val:0x38d3; valaddr_reg:x1; val_offset:42*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 42*FLEN/8, x4, x2, x6) + +inst_47: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2c4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1b4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0d3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36c4; op2val:0x3db4; +op3val:0x38d3; valaddr_reg:x1; val_offset:45*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 45*FLEN/8, x4, x2, x6) + +inst_48: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2c4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1b4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0d3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36c4; op2val:0x3db4; +op3val:0x38d3; valaddr_reg:x1; val_offset:48*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 48*FLEN/8, x4, x2, x6) + +inst_49: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2c4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1b4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0d3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36c4; op2val:0x3db4; +op3val:0x38d3; valaddr_reg:x1; val_offset:51*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 51*FLEN/8, x4, x2, x6) + +inst_50: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x214 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x104 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3a0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2614; op2val:0x5104; +op3val:0x3ba0; valaddr_reg:x1; val_offset:54*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 54*FLEN/8, x4, x2, x6) + +inst_51: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x214 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x104 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3a0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2614; op2val:0x5104; +op3val:0x3ba0; valaddr_reg:x1; val_offset:57*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 57*FLEN/8, x4, x2, x6) + +inst_52: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x214 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x104 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3a0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2614; op2val:0x5104; +op3val:0x3ba0; valaddr_reg:x1; val_offset:60*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 60*FLEN/8, x4, x2, x6) + +inst_53: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x214 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x104 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3a0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2614; op2val:0x5104; +op3val:0x3ba0; valaddr_reg:x1; val_offset:63*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 63*FLEN/8, x4, x2, x6) + +inst_54: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x214 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x104 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3a0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2614; op2val:0x5104; +op3val:0x3ba0; valaddr_reg:x1; val_offset:66*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 66*FLEN/8, x4, x2, x6) + +inst_55: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x087 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x104 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ae and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3087; op2val:0x4504; +op3val:0x39ae; valaddr_reg:x1; val_offset:69*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 69*FLEN/8, x4, x2, x6) + +inst_56: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x087 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x104 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ae and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3087; op2val:0x4504; +op3val:0x39ae; valaddr_reg:x1; val_offset:72*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 72*FLEN/8, x4, x2, x6) + +inst_57: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x087 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x104 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ae and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3087; op2val:0x4504; +op3val:0x39ae; valaddr_reg:x1; val_offset:75*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 75*FLEN/8, x4, x2, x6) + +inst_58: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x087 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x104 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ae and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3087; op2val:0x4504; +op3val:0x39ae; valaddr_reg:x1; val_offset:78*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 78*FLEN/8, x4, x2, x6) + +inst_59: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x087 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x104 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ae and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3087; op2val:0x4504; +op3val:0x39ae; valaddr_reg:x1; val_offset:81*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 81*FLEN/8, x4, x2, x6) + +inst_60: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x01f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x30e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ad8; op2val:0x3c1f; +op3val:0x3b0e; valaddr_reg:x1; val_offset:84*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 84*FLEN/8, x4, x2, x6) + +inst_61: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x01f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x30e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ad8; op2val:0x3c1f; +op3val:0x3b0e; valaddr_reg:x1; val_offset:87*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 87*FLEN/8, x4, x2, x6) + +inst_62: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x01f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x30e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ad8; op2val:0x3c1f; +op3val:0x3b0e; valaddr_reg:x1; val_offset:90*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 90*FLEN/8, x4, x2, x6) + +inst_63: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x01f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x30e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ad8; op2val:0x3c1f; +op3val:0x3b0e; valaddr_reg:x1; val_offset:93*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 93*FLEN/8, x4, x2, x6) + +inst_64: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x01f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x30e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ad8; op2val:0x3c1f; +op3val:0x3b0e; valaddr_reg:x1; val_offset:96*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 96*FLEN/8, x4, x2, x6) + +inst_65: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x188 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x041 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1e2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3988; op2val:0x3441; +op3val:0x31e2; valaddr_reg:x1; val_offset:99*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 99*FLEN/8, x4, x2, x6) + +inst_66: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x188 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x041 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1e2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3988; op2val:0x3441; +op3val:0x31e2; valaddr_reg:x1; val_offset:102*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 102*FLEN/8, x4, x2, x6) + +inst_67: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x188 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x041 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1e2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3988; op2val:0x3441; +op3val:0x31e2; valaddr_reg:x1; val_offset:105*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 105*FLEN/8, x4, x2, x6) + +inst_68: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x188 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x041 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1e2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3988; op2val:0x3441; +op3val:0x31e2; valaddr_reg:x1; val_offset:108*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 108*FLEN/8, x4, x2, x6) + +inst_69: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x188 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x041 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1e2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3988; op2val:0x3441; +op3val:0x31e2; valaddr_reg:x1; val_offset:111*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 111*FLEN/8, x4, x2, x6) + +inst_70: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x28d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x015 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a8d; op2val:0x3815; +op3val:0x36b1; valaddr_reg:x1; val_offset:114*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 114*FLEN/8, x4, x2, x6) + +inst_71: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x28d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x015 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a8d; op2val:0x3815; +op3val:0x36b1; valaddr_reg:x1; val_offset:117*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 117*FLEN/8, x4, x2, x6) + +inst_72: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x28d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x015 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a8d; op2val:0x3815; +op3val:0x36b1; valaddr_reg:x1; val_offset:120*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 120*FLEN/8, x4, x2, x6) + +inst_73: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x28d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x015 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a8d; op2val:0x3815; +op3val:0x36b1; valaddr_reg:x1; val_offset:123*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 123*FLEN/8, x4, x2, x6) + +inst_74: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x28d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x015 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a8d; op2val:0x3815; +op3val:0x36b1; valaddr_reg:x1; val_offset:126*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 126*FLEN/8, x4, x2, x6) + +inst_75: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2f3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x105 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35c7; op2val:0x3ef3; +op3val:0x3905; valaddr_reg:x1; val_offset:129*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 129*FLEN/8, x4, x2, x6) + +inst_76: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2f3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x105 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35c7; op2val:0x3ef3; +op3val:0x3905; valaddr_reg:x1; val_offset:132*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 132*FLEN/8, x4, x2, x6) + +inst_77: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2f3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x105 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35c7; op2val:0x3ef3; +op3val:0x3905; valaddr_reg:x1; val_offset:135*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 135*FLEN/8, x4, x2, x6) + +inst_78: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2f3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x105 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35c7; op2val:0x3ef3; +op3val:0x3905; valaddr_reg:x1; val_offset:138*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 138*FLEN/8, x4, x2, x6) + +inst_79: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2f3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x105 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35c7; op2val:0x3ef3; +op3val:0x3905; valaddr_reg:x1; val_offset:141*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 141*FLEN/8, x4, x2, x6) + +inst_80: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x33c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x025 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x37f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x373c; op2val:0x4025; +op3val:0x3b7f; valaddr_reg:x1; val_offset:144*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 144*FLEN/8, x4, x2, x6) + +inst_81: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x33c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x025 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x37f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x373c; op2val:0x4025; +op3val:0x3b7f; valaddr_reg:x1; val_offset:147*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 147*FLEN/8, x4, x2, x6) + +inst_82: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x33c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x025 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x37f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x373c; op2val:0x4025; +op3val:0x3b7f; valaddr_reg:x1; val_offset:150*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 150*FLEN/8, x4, x2, x6) + +inst_83: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x33c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x025 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x37f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x373c; op2val:0x4025; +op3val:0x3b7f; valaddr_reg:x1; val_offset:153*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 153*FLEN/8, x4, x2, x6) + +inst_84: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x33c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x025 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x37f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x373c; op2val:0x4025; +op3val:0x3b7f; valaddr_reg:x1; val_offset:156*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 156*FLEN/8, x4, x2, x6) + +inst_85: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x385 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2c1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x25a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b85; op2val:0x3ac1; +op3val:0x3a5a; valaddr_reg:x1; val_offset:159*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 159*FLEN/8, x4, x2, x6) + +inst_86: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x385 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2c1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x25a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b85; op2val:0x3ac1; +op3val:0x3a5a; valaddr_reg:x1; val_offset:162*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 162*FLEN/8, x4, x2, x6) + +inst_87: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x385 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2c1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x25a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b85; op2val:0x3ac1; +op3val:0x3a5a; valaddr_reg:x1; val_offset:165*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 165*FLEN/8, x4, x2, x6) + +inst_88: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x385 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2c1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x25a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b85; op2val:0x3ac1; +op3val:0x3a5a; valaddr_reg:x1; val_offset:168*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 168*FLEN/8, x4, x2, x6) + +inst_89: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x385 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2c1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x25a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b85; op2val:0x3ac1; +op3val:0x3a5a; valaddr_reg:x1; val_offset:171*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 171*FLEN/8, x4, x2, x6) + +inst_90: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x11d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x329 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x094 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x351d; op2val:0x3f29; +op3val:0x3894; valaddr_reg:x1; val_offset:174*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 174*FLEN/8, x4, x2, x6) + +inst_91: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x11d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x329 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x094 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x351d; op2val:0x3f29; +op3val:0x3894; valaddr_reg:x1; val_offset:177*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 177*FLEN/8, x4, x2, x6) + +inst_92: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x11d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x329 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x094 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x351d; op2val:0x3f29; +op3val:0x3894; valaddr_reg:x1; val_offset:180*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 180*FLEN/8, x4, x2, x6) + +inst_93: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x11d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x329 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x094 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x351d; op2val:0x3f29; +op3val:0x3894; valaddr_reg:x1; val_offset:183*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 183*FLEN/8, x4, x2, x6) + +inst_94: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x11d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x329 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x094 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x351d; op2val:0x3f29; +op3val:0x3894; valaddr_reg:x1; val_offset:186*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 186*FLEN/8, x4, x2, x6) + +inst_95: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x17c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0d5 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2a1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x397c; op2val:0x38d5; +op3val:0x36a1; valaddr_reg:x1; val_offset:189*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 189*FLEN/8, x4, x2, x6) + +inst_96: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x17c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0d5 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2a1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x397c; op2val:0x38d5; +op3val:0x36a1; valaddr_reg:x1; val_offset:192*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 192*FLEN/8, x4, x2, x6) + +inst_97: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x17c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0d5 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2a1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x397c; op2val:0x38d5; +op3val:0x36a1; valaddr_reg:x1; val_offset:195*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 195*FLEN/8, x4, x2, x6) + +inst_98: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x17c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0d5 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2a1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x397c; op2val:0x38d5; +op3val:0x36a1; valaddr_reg:x1; val_offset:198*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 198*FLEN/8, x4, x2, x6) + +inst_99: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x17c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0d5 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2a1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x397c; op2val:0x38d5; +op3val:0x36a1; valaddr_reg:x1; val_offset:201*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 201*FLEN/8, x4, x2, x6) + +inst_100: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x05f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x11f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x19a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x385f; op2val:0x3d1f; +op3val:0x399a; valaddr_reg:x1; val_offset:204*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 204*FLEN/8, x4, x2, x6) + +inst_101: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x05f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x11f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x19a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x385f; op2val:0x3d1f; +op3val:0x399a; valaddr_reg:x1; val_offset:207*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 207*FLEN/8, x4, x2, x6) + +inst_102: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x05f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x11f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x19a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x385f; op2val:0x3d1f; +op3val:0x399a; valaddr_reg:x1; val_offset:210*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 210*FLEN/8, x4, x2, x6) + +inst_103: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x05f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x11f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x19a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x385f; op2val:0x3d1f; +op3val:0x399a; valaddr_reg:x1; val_offset:213*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 213*FLEN/8, x4, x2, x6) + +inst_104: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x05f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x11f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x19a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x385f; op2val:0x3d1f; +op3val:0x399a; valaddr_reg:x1; val_offset:216*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 216*FLEN/8, x4, x2, x6) + +inst_105: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x294 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1db and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0d0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3294; op2val:0x3ddb; +op3val:0x34d0; valaddr_reg:x1; val_offset:219*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 219*FLEN/8, x4, x2, x6) + +inst_106: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x294 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1db and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0d0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3294; op2val:0x3ddb; +op3val:0x34d0; valaddr_reg:x1; val_offset:222*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 222*FLEN/8, x4, x2, x6) + +inst_107: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x294 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1db and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0d0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3294; op2val:0x3ddb; +op3val:0x34d0; valaddr_reg:x1; val_offset:225*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 225*FLEN/8, x4, x2, x6) + +inst_108: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x294 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1db and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0d0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3294; op2val:0x3ddb; +op3val:0x34d0; valaddr_reg:x1; val_offset:228*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 228*FLEN/8, x4, x2, x6) + +inst_109: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x294 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1db and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0d0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3294; op2val:0x3ddb; +op3val:0x34d0; valaddr_reg:x1; val_offset:231*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 231*FLEN/8, x4, x2, x6) + +inst_110: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x20c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x081 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2cf and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a0c; op2val:0x3881; +op3val:0x36cf; valaddr_reg:x1; val_offset:234*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 234*FLEN/8, x4, x2, x6) + +inst_111: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x20c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x081 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2cf and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a0c; op2val:0x3881; +op3val:0x36cf; valaddr_reg:x1; val_offset:237*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 237*FLEN/8, x4, x2, x6) + +inst_112: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x20c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x081 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2cf and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a0c; op2val:0x3881; +op3val:0x36cf; valaddr_reg:x1; val_offset:240*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 240*FLEN/8, x4, x2, x6) + +inst_113: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x20c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x081 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2cf and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a0c; op2val:0x3881; +op3val:0x36cf; valaddr_reg:x1; val_offset:243*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 243*FLEN/8, x4, x2, x6) + +inst_114: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x20c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x081 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2cf and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a0c; op2val:0x3881; +op3val:0x36cf; valaddr_reg:x1; val_offset:246*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 246*FLEN/8, x4, x2, x6) + +inst_115: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x398 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x035 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x3fd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3798; op2val:0x3435; +op3val:0x2ffd; valaddr_reg:x1; val_offset:249*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 249*FLEN/8, x4, x2, x6) + +inst_116: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x398 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x035 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x3fd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3798; op2val:0x3435; +op3val:0x2ffd; valaddr_reg:x1; val_offset:252*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 252*FLEN/8, x4, x2, x6) + +inst_117: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x398 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x035 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x3fd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3798; op2val:0x3435; +op3val:0x2ffd; valaddr_reg:x1; val_offset:255*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 255*FLEN/8, x4, x2, x6) + +inst_118: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x398 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x035 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x3fd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3798; op2val:0x3435; +op3val:0x2ffd; valaddr_reg:x1; val_offset:258*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 258*FLEN/8, x4, x2, x6) + +inst_119: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x398 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x035 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x3fd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3798; op2val:0x3435; +op3val:0x2ffd; valaddr_reg:x1; val_offset:261*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 261*FLEN/8, x4, x2, x6) + +inst_120: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x054 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x143 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1b2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3454; op2val:0x4143; +op3val:0x39b2; valaddr_reg:x1; val_offset:264*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 264*FLEN/8, x4, x2, x6) + +inst_121: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x054 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x143 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1b2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3454; op2val:0x4143; +op3val:0x39b2; valaddr_reg:x1; val_offset:267*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 267*FLEN/8, x4, x2, x6) + +inst_122: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x054 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x143 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1b2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3454; op2val:0x4143; +op3val:0x39b2; valaddr_reg:x1; val_offset:270*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 270*FLEN/8, x4, x2, x6) + +inst_123: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x054 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x143 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1b2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3454; op2val:0x4143; +op3val:0x39b2; valaddr_reg:x1; val_offset:273*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 273*FLEN/8, x4, x2, x6) + +inst_124: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x054 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x143 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1b2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3454; op2val:0x4143; +op3val:0x39b2; valaddr_reg:x1; val_offset:276*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 276*FLEN/8, x4, x2, x6) + +inst_125: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x113 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x18f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x30e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2513; op2val:0x518f; +op3val:0x3b0e; valaddr_reg:x1; val_offset:279*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 279*FLEN/8, x4, x2, x6) + +inst_126: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x113 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x18f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x30e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2513; op2val:0x518f; +op3val:0x3b0e; valaddr_reg:x1; val_offset:282*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 282*FLEN/8, x4, x2, x6) + +inst_127: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x113 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x18f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x30e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2513; op2val:0x518f; +op3val:0x3b0e; valaddr_reg:x1; val_offset:285*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 285*FLEN/8, x4, x2, x6) + +inst_128: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x113 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x18f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x30e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2513; op2val:0x518f; +op3val:0x3b0e; valaddr_reg:x1; val_offset:288*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 288*FLEN/8, x4, x2, x6) + +inst_129: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x113 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x18f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x30e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2513; op2val:0x518f; +op3val:0x3b0e; valaddr_reg:x1; val_offset:291*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 291*FLEN/8, x4, x2, x6) + +inst_130: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0a7 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2ad and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3c5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38a7; op2val:0x36ad; +op3val:0x33c5; valaddr_reg:x1; val_offset:294*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 294*FLEN/8, x4, x2, x6) + +inst_131: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0a7 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2ad and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3c5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38a7; op2val:0x36ad; +op3val:0x33c5; valaddr_reg:x1; val_offset:297*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 297*FLEN/8, x4, x2, x6) + +inst_132: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0a7 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2ad and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3c5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38a7; op2val:0x36ad; +op3val:0x33c5; valaddr_reg:x1; val_offset:300*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 300*FLEN/8, x4, x2, x6) + +inst_133: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0a7 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2ad and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3c5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38a7; op2val:0x36ad; +op3val:0x33c5; valaddr_reg:x1; val_offset:303*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 303*FLEN/8, x4, x2, x6) + +inst_134: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0a7 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2ad and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3c5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38a7; op2val:0x36ad; +op3val:0x33c5; valaddr_reg:x1; val_offset:306*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 306*FLEN/8, x4, x2, x6) + +inst_135: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2c8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0d2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x016 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ac8; op2val:0x38d2; +op3val:0x3816; valaddr_reg:x1; val_offset:309*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 309*FLEN/8, x4, x2, x6) + +inst_136: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2c8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0d2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x016 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ac8; op2val:0x38d2; +op3val:0x3816; valaddr_reg:x1; val_offset:312*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 312*FLEN/8, x4, x2, x6) + +inst_137: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2c8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0d2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x016 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ac8; op2val:0x38d2; +op3val:0x3816; valaddr_reg:x1; val_offset:315*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 315*FLEN/8, x4, x2, x6) + +inst_138: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2c8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0d2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x016 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ac8; op2val:0x38d2; +op3val:0x3816; valaddr_reg:x1; val_offset:318*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 318*FLEN/8, x4, x2, x6) + +inst_139: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2c8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0d2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x016 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ac8; op2val:0x38d2; +op3val:0x3816; valaddr_reg:x1; val_offset:321*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 321*FLEN/8, x4, x2, x6) + +inst_140: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3af and fs2 == 0 and fe2 == 0x0d and fm2 == 0x186 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x14e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3baf; op2val:0x3586; +op3val:0x354e; valaddr_reg:x1; val_offset:324*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 324*FLEN/8, x4, x2, x6) + +inst_141: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3af and fs2 == 0 and fe2 == 0x0d and fm2 == 0x186 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x14e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3baf; op2val:0x3586; +op3val:0x354e; valaddr_reg:x1; val_offset:327*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 327*FLEN/8, x4, x2, x6) + +inst_142: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3af and fs2 == 0 and fe2 == 0x0d and fm2 == 0x186 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x14e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3baf; op2val:0x3586; +op3val:0x354e; valaddr_reg:x1; val_offset:330*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 330*FLEN/8, x4, x2, x6) + +inst_143: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3af and fs2 == 0 and fe2 == 0x0d and fm2 == 0x186 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x14e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3baf; op2val:0x3586; +op3val:0x354e; valaddr_reg:x1; val_offset:333*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 333*FLEN/8, x4, x2, x6) + +inst_144: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3af and fs2 == 0 and fe2 == 0x0d and fm2 == 0x186 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x14e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3baf; op2val:0x3586; +op3val:0x354e; valaddr_reg:x1; val_offset:336*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 336*FLEN/8, x4, x2, x6) + +inst_145: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x388 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x341 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2d4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3388; op2val:0x3f41; +op3val:0x36d4; valaddr_reg:x1; val_offset:339*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 339*FLEN/8, x4, x2, x6) + +inst_146: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x388 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x341 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2d4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3388; op2val:0x3f41; +op3val:0x36d4; valaddr_reg:x1; val_offset:342*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 342*FLEN/8, x4, x2, x6) + +inst_147: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x388 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x341 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2d4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3388; op2val:0x3f41; +op3val:0x36d4; valaddr_reg:x1; val_offset:345*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 345*FLEN/8, x4, x2, x6) + +inst_148: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x388 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x341 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2d4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3388; op2val:0x3f41; +op3val:0x36d4; valaddr_reg:x1; val_offset:348*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 348*FLEN/8, x4, x2, x6) + +inst_149: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x388 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x341 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2d4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3388; op2val:0x3f41; +op3val:0x36d4; valaddr_reg:x1; val_offset:351*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 351*FLEN/8, x4, x2, x6) + +inst_150: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x182 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x17d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ff8; op2val:0x4582; +op3val:0x397d; valaddr_reg:x1; val_offset:354*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 354*FLEN/8, x4, x2, x6) + +inst_151: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x182 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x17d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ff8; op2val:0x4582; +op3val:0x397d; valaddr_reg:x1; val_offset:357*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 357*FLEN/8, x4, x2, x6) + +inst_152: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x182 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x17d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ff8; op2val:0x4582; +op3val:0x397d; valaddr_reg:x1; val_offset:360*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 360*FLEN/8, x4, x2, x6) + +inst_153: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x182 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x17d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ff8; op2val:0x4582; +op3val:0x397d; valaddr_reg:x1; val_offset:363*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 363*FLEN/8, x4, x2, x6) + +inst_154: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x182 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x17d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ff8; op2val:0x4582; +op3val:0x397d; valaddr_reg:x1; val_offset:366*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 366*FLEN/8, x4, x2, x6) + +inst_155: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0e0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x153 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x27d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34e0; op2val:0x3d53; +op3val:0x367d; valaddr_reg:x1; val_offset:369*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 369*FLEN/8, x4, x2, x6) +RVTEST_SIGBASE(x2,signature_x2_1) + +inst_156: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0e0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x153 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x27d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34e0; op2val:0x3d53; +op3val:0x367d; valaddr_reg:x1; val_offset:372*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 372*FLEN/8, x4, x2, x6) + +inst_157: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0e0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x153 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x27d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34e0; op2val:0x3d53; +op3val:0x367d; valaddr_reg:x1; val_offset:375*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 375*FLEN/8, x4, x2, x6) + +inst_158: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0e0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x153 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x27d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34e0; op2val:0x3d53; +op3val:0x367d; valaddr_reg:x1; val_offset:378*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 378*FLEN/8, x4, x2, x6) + +inst_159: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0e0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x153 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x27d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34e0; op2val:0x3d53; +op3val:0x367d; valaddr_reg:x1; val_offset:381*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 381*FLEN/8, x4, x2, x6) + +inst_160: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2b8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x12d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x059 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36b8; op2val:0x3d2d; +op3val:0x3859; valaddr_reg:x1; val_offset:384*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 384*FLEN/8, x4, x2, x6) + +inst_161: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2b8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x12d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x059 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36b8; op2val:0x3d2d; +op3val:0x3859; valaddr_reg:x1; val_offset:387*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 387*FLEN/8, x4, x2, x6) + +inst_162: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2b8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x12d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x059 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36b8; op2val:0x3d2d; +op3val:0x3859; valaddr_reg:x1; val_offset:390*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 390*FLEN/8, x4, x2, x6) + +inst_163: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2b8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x12d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x059 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36b8; op2val:0x3d2d; +op3val:0x3859; valaddr_reg:x1; val_offset:393*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 393*FLEN/8, x4, x2, x6) + +inst_164: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2b8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x12d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x059 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36b8; op2val:0x3d2d; +op3val:0x3859; valaddr_reg:x1; val_offset:396*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 396*FLEN/8, x4, x2, x6) + +inst_165: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x11e and fs2 == 0 and fe2 == 0x0d and fm2 == 0x187 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x314 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x311e; op2val:0x3587; +op3val:0x2b14; valaddr_reg:x1; val_offset:399*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 399*FLEN/8, x4, x2, x6) + +inst_166: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x11e and fs2 == 0 and fe2 == 0x0d and fm2 == 0x187 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x314 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x311e; op2val:0x3587; +op3val:0x2b14; valaddr_reg:x1; val_offset:402*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 402*FLEN/8, x4, x2, x6) + +inst_167: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x11e and fs2 == 0 and fe2 == 0x0d and fm2 == 0x187 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x314 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x311e; op2val:0x3587; +op3val:0x2b14; valaddr_reg:x1; val_offset:405*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 405*FLEN/8, x4, x2, x6) + +inst_168: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x11e and fs2 == 0 and fe2 == 0x0d and fm2 == 0x187 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x314 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x311e; op2val:0x3587; +op3val:0x2b14; valaddr_reg:x1; val_offset:408*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 408*FLEN/8, x4, x2, x6) + +inst_169: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x11e and fs2 == 0 and fe2 == 0x0d and fm2 == 0x187 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x314 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x311e; op2val:0x3587; +op3val:0x2b14; valaddr_reg:x1; val_offset:411*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 411*FLEN/8, x4, x2, x6) + +inst_170: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x035 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x11b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x15f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3835; op2val:0x391b; +op3val:0x355f; valaddr_reg:x1; val_offset:414*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 414*FLEN/8, x4, x2, x6) + +inst_171: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x035 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x11b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x15f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3835; op2val:0x391b; +op3val:0x355f; valaddr_reg:x1; val_offset:417*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 417*FLEN/8, x4, x2, x6) + +inst_172: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x035 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x11b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x15f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3835; op2val:0x391b; +op3val:0x355f; valaddr_reg:x1; val_offset:420*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 420*FLEN/8, x4, x2, x6) + +inst_173: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x035 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x11b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x15f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3835; op2val:0x391b; +op3val:0x355f; valaddr_reg:x1; val_offset:423*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 423*FLEN/8, x4, x2, x6) + +inst_174: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x035 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x11b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x15f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3835; op2val:0x391b; +op3val:0x355f; valaddr_reg:x1; val_offset:426*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 426*FLEN/8, x4, x2, x6) + +inst_175: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x383 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x115 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0c6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b83; op2val:0x3515; +op3val:0x34c6; valaddr_reg:x1; val_offset:429*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 429*FLEN/8, x4, x2, x6) + +inst_176: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x383 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x115 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0c6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b83; op2val:0x3515; +op3val:0x34c6; valaddr_reg:x1; val_offset:432*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 432*FLEN/8, x4, x2, x6) + +inst_177: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x383 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x115 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0c6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b83; op2val:0x3515; +op3val:0x34c6; valaddr_reg:x1; val_offset:435*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 435*FLEN/8, x4, x2, x6) + +inst_178: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x383 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x115 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0c6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b83; op2val:0x3515; +op3val:0x34c6; valaddr_reg:x1; val_offset:438*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 438*FLEN/8, x4, x2, x6) + +inst_179: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x383 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x115 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0c6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b83; op2val:0x3515; +op3val:0x34c6; valaddr_reg:x1; val_offset:441*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 441*FLEN/8, x4, x2, x6) + +inst_180: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a5 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x102 and fs3 == 0 and fe3 == 0x07 and fm3 == 0x311 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35a5; op2val:0x2502; +op3val:0x1f11; valaddr_reg:x1; val_offset:444*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 444*FLEN/8, x4, x2, x6) + +inst_181: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a5 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x102 and fs3 == 0 and fe3 == 0x07 and fm3 == 0x311 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35a5; op2val:0x2502; +op3val:0x1f11; valaddr_reg:x1; val_offset:447*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 447*FLEN/8, x4, x2, x6) + +inst_182: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a5 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x102 and fs3 == 0 and fe3 == 0x07 and fm3 == 0x311 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35a5; op2val:0x2502; +op3val:0x1f11; valaddr_reg:x1; val_offset:450*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 450*FLEN/8, x4, x2, x6) + +inst_183: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a5 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x102 and fs3 == 0 and fe3 == 0x07 and fm3 == 0x311 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35a5; op2val:0x2502; +op3val:0x1f11; valaddr_reg:x1; val_offset:453*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 453*FLEN/8, x4, x2, x6) + +inst_184: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a5 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x102 and fs3 == 0 and fe3 == 0x07 and fm3 == 0x311 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35a5; op2val:0x2502; +op3val:0x1f11; valaddr_reg:x1; val_offset:456*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 456*FLEN/8, x4, x2, x6) + +inst_185: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1b2 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x004 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1b9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31b2; op2val:0x4404; +op3val:0x39b9; valaddr_reg:x1; val_offset:459*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 459*FLEN/8, x4, x2, x6) + +inst_186: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1b2 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x004 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1b9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31b2; op2val:0x4404; +op3val:0x39b9; valaddr_reg:x1; val_offset:462*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 462*FLEN/8, x4, x2, x6) + +inst_187: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1b2 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x004 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1b9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31b2; op2val:0x4404; +op3val:0x39b9; valaddr_reg:x1; val_offset:465*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 465*FLEN/8, x4, x2, x6) + +inst_188: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1b2 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x004 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1b9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31b2; op2val:0x4404; +op3val:0x39b9; valaddr_reg:x1; val_offset:468*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 468*FLEN/8, x4, x2, x6) + +inst_189: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1b2 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x004 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1b9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31b2; op2val:0x4404; +op3val:0x39b9; valaddr_reg:x1; val_offset:471*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 471*FLEN/8, x4, x2, x6) + +inst_190: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x050 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x14d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38e9; op2val:0x3850; +op3val:0x354d; valaddr_reg:x1; val_offset:474*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 474*FLEN/8, x4, x2, x6) + +inst_191: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x050 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x14d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38e9; op2val:0x3850; +op3val:0x354d; valaddr_reg:x1; val_offset:477*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 477*FLEN/8, x4, x2, x6) + +inst_192: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x050 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x14d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38e9; op2val:0x3850; +op3val:0x354d; valaddr_reg:x1; val_offset:480*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 480*FLEN/8, x4, x2, x6) + +inst_193: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x050 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x14d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38e9; op2val:0x3850; +op3val:0x354d; valaddr_reg:x1; val_offset:483*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 483*FLEN/8, x4, x2, x6) + +inst_194: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x050 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x14d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38e9; op2val:0x3850; +op3val:0x354d; valaddr_reg:x1; val_offset:486*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 486*FLEN/8, x4, x2, x6) + +inst_195: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d1 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x067 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x04e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bd1; op2val:0x3867; +op3val:0x384e; valaddr_reg:x1; val_offset:489*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 489*FLEN/8, x4, x2, x6) + +inst_196: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d1 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x067 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x04e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bd1; op2val:0x3867; +op3val:0x384e; valaddr_reg:x1; val_offset:492*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 492*FLEN/8, x4, x2, x6) + +inst_197: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d1 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x067 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x04e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bd1; op2val:0x3867; +op3val:0x384e; valaddr_reg:x1; val_offset:495*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 495*FLEN/8, x4, x2, x6) + +inst_198: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d1 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x067 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x04e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bd1; op2val:0x3867; +op3val:0x384e; valaddr_reg:x1; val_offset:498*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 498*FLEN/8, x4, x2, x6) + +inst_199: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d1 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x067 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x04e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bd1; op2val:0x3867; +op3val:0x384e; valaddr_reg:x1; val_offset:501*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 501*FLEN/8, x4, x2, x6) + +inst_200: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2a7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x03e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x310 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aa7; op2val:0x3c3e; +op3val:0x3b10; valaddr_reg:x1; val_offset:504*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 504*FLEN/8, x4, x2, x6) + +inst_201: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2a7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x03e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x310 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aa7; op2val:0x3c3e; +op3val:0x3b10; valaddr_reg:x1; val_offset:507*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 507*FLEN/8, x4, x2, x6) + +inst_202: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2a7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x03e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x310 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aa7; op2val:0x3c3e; +op3val:0x3b10; valaddr_reg:x1; val_offset:510*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 510*FLEN/8, x4, x2, x6) + +inst_203: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2a7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x03e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x310 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aa7; op2val:0x3c3e; +op3val:0x3b10; valaddr_reg:x1; val_offset:513*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 513*FLEN/8, x4, x2, x6) + +inst_204: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2a7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x03e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x310 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aa7; op2val:0x3c3e; +op3val:0x3b10; valaddr_reg:x1; val_offset:516*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 516*FLEN/8, x4, x2, x6) + +inst_205: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x387 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3e1 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x36a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b87; op2val:0x33e1; +op3val:0x336a; valaddr_reg:x1; val_offset:519*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 519*FLEN/8, x4, x2, x6) + +inst_206: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x387 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3e1 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x36a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b87; op2val:0x33e1; +op3val:0x336a; valaddr_reg:x1; val_offset:522*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 522*FLEN/8, x4, x2, x6) + +inst_207: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x387 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3e1 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x36a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b87; op2val:0x33e1; +op3val:0x336a; valaddr_reg:x1; val_offset:525*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 525*FLEN/8, x4, x2, x6) + +inst_208: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x387 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3e1 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x36a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b87; op2val:0x33e1; +op3val:0x336a; valaddr_reg:x1; val_offset:528*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 528*FLEN/8, x4, x2, x6) + +inst_209: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x387 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3e1 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x36a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b87; op2val:0x33e1; +op3val:0x336a; valaddr_reg:x1; val_offset:531*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 531*FLEN/8, x4, x2, x6) + +inst_210: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2f7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2e9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x204 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3af7; op2val:0x3ae9; +op3val:0x3a04; valaddr_reg:x1; val_offset:534*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 534*FLEN/8, x4, x2, x6) + +inst_211: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2f7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2e9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x204 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3af7; op2val:0x3ae9; +op3val:0x3a04; valaddr_reg:x1; val_offset:537*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 537*FLEN/8, x4, x2, x6) + +inst_212: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2f7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2e9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x204 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3af7; op2val:0x3ae9; +op3val:0x3a04; valaddr_reg:x1; val_offset:540*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 540*FLEN/8, x4, x2, x6) + +inst_213: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2f7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2e9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x204 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3af7; op2val:0x3ae9; +op3val:0x3a04; valaddr_reg:x1; val_offset:543*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 543*FLEN/8, x4, x2, x6) + +inst_214: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2f7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2e9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x204 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3af7; op2val:0x3ae9; +op3val:0x3a04; valaddr_reg:x1; val_offset:546*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 546*FLEN/8, x4, x2, x6) + +inst_215: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0df and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2c2 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x01d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38df; op2val:0x32c2; +op3val:0x301d; valaddr_reg:x1; val_offset:549*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 549*FLEN/8, x4, x2, x6) + +inst_216: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0df and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2c2 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x01d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38df; op2val:0x32c2; +op3val:0x301d; valaddr_reg:x1; val_offset:552*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 552*FLEN/8, x4, x2, x6) + +inst_217: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0df and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2c2 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x01d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38df; op2val:0x32c2; +op3val:0x301d; valaddr_reg:x1; val_offset:555*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 555*FLEN/8, x4, x2, x6) + +inst_218: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0df and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2c2 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x01d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38df; op2val:0x32c2; +op3val:0x301d; valaddr_reg:x1; val_offset:558*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 558*FLEN/8, x4, x2, x6) + +inst_219: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0df and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2c2 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x01d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38df; op2val:0x32c2; +op3val:0x301d; valaddr_reg:x1; val_offset:561*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 561*FLEN/8, x4, x2, x6) + +inst_220: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x35a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0cb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x068 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b5a; op2val:0x38cb; +op3val:0x3868; valaddr_reg:x1; val_offset:564*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 564*FLEN/8, x4, x2, x6) + +inst_221: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x35a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0cb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x068 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b5a; op2val:0x38cb; +op3val:0x3868; valaddr_reg:x1; val_offset:567*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 567*FLEN/8, x4, x2, x6) + +inst_222: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x35a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0cb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x068 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b5a; op2val:0x38cb; +op3val:0x3868; valaddr_reg:x1; val_offset:570*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 570*FLEN/8, x4, x2, x6) + +inst_223: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x35a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0cb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x068 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b5a; op2val:0x38cb; +op3val:0x3868; valaddr_reg:x1; val_offset:573*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 573*FLEN/8, x4, x2, x6) + +inst_224: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x35a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0cb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x068 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b5a; op2val:0x38cb; +op3val:0x3868; valaddr_reg:x1; val_offset:576*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 576*FLEN/8, x4, x2, x6) + +inst_225: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x335 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x025 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x377 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3735; op2val:0x3425; +op3val:0x2f77; valaddr_reg:x1; val_offset:579*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 579*FLEN/8, x4, x2, x6) + +inst_226: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x335 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x025 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x377 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3735; op2val:0x3425; +op3val:0x2f77; valaddr_reg:x1; val_offset:582*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 582*FLEN/8, x4, x2, x6) + +inst_227: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x335 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x025 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x377 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3735; op2val:0x3425; +op3val:0x2f77; valaddr_reg:x1; val_offset:585*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 585*FLEN/8, x4, x2, x6) + +inst_228: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x335 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x025 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x377 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3735; op2val:0x3425; +op3val:0x2f77; valaddr_reg:x1; val_offset:588*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 588*FLEN/8, x4, x2, x6) + +inst_229: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x335 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x025 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x377 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3735; op2val:0x3425; +op3val:0x2f77; valaddr_reg:x1; val_offset:591*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 591*FLEN/8, x4, x2, x6) + +inst_230: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1c8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x206 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x05a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31c8; op2val:0x3a06; +op3val:0x305a; valaddr_reg:x1; val_offset:594*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 594*FLEN/8, x4, x2, x6) + +inst_231: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1c8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x206 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x05a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31c8; op2val:0x3a06; +op3val:0x305a; valaddr_reg:x1; val_offset:597*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 597*FLEN/8, x4, x2, x6) + +inst_232: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1c8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x206 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x05a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31c8; op2val:0x3a06; +op3val:0x305a; valaddr_reg:x1; val_offset:600*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 600*FLEN/8, x4, x2, x6) + +inst_233: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1c8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x206 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x05a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31c8; op2val:0x3a06; +op3val:0x305a; valaddr_reg:x1; val_offset:603*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 603*FLEN/8, x4, x2, x6) + +inst_234: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1c8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x206 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x05a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31c8; op2val:0x3a06; +op3val:0x305a; valaddr_reg:x1; val_offset:606*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 606*FLEN/8, x4, x2, x6) + +inst_235: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1c5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x27b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0ad and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39c5; op2val:0x3a7b; +op3val:0x38ad; valaddr_reg:x1; val_offset:609*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 609*FLEN/8, x4, x2, x6) + +inst_236: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1c5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x27b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0ad and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39c5; op2val:0x3a7b; +op3val:0x38ad; valaddr_reg:x1; val_offset:612*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 612*FLEN/8, x4, x2, x6) + +inst_237: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1c5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x27b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0ad and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39c5; op2val:0x3a7b; +op3val:0x38ad; valaddr_reg:x1; val_offset:615*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 615*FLEN/8, x4, x2, x6) + +inst_238: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1c5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x27b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0ad and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39c5; op2val:0x3a7b; +op3val:0x38ad; valaddr_reg:x1; val_offset:618*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 618*FLEN/8, x4, x2, x6) + +inst_239: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1c5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x27b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0ad and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39c5; op2val:0x3a7b; +op3val:0x38ad; valaddr_reg:x1; val_offset:621*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 621*FLEN/8, x4, x2, x6) + +inst_240: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x121 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1c8 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x36a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3921; op2val:0x31c8; +op3val:0x2f6a; valaddr_reg:x1; val_offset:624*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 624*FLEN/8, x4, x2, x6) + +inst_241: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x121 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1c8 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x36a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3921; op2val:0x31c8; +op3val:0x2f6a; valaddr_reg:x1; val_offset:627*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 627*FLEN/8, x4, x2, x6) + +inst_242: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x121 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1c8 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x36a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3921; op2val:0x31c8; +op3val:0x2f6a; valaddr_reg:x1; val_offset:630*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 630*FLEN/8, x4, x2, x6) + +inst_243: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x121 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1c8 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x36a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3921; op2val:0x31c8; +op3val:0x2f6a; valaddr_reg:x1; val_offset:633*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 633*FLEN/8, x4, x2, x6) + +inst_244: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x121 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1c8 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x36a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3921; op2val:0x31c8; +op3val:0x2f6a; valaddr_reg:x1; val_offset:636*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 636*FLEN/8, x4, x2, x6) + +inst_245: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x16a and fs2 == 0 and fe2 == 0x13 and fm2 == 0x103 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ca and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x296a; op2val:0x4d03; +op3val:0x3aca; valaddr_reg:x1; val_offset:639*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 639*FLEN/8, x4, x2, x6) + +inst_246: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x16a and fs2 == 0 and fe2 == 0x13 and fm2 == 0x103 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ca and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x296a; op2val:0x4d03; +op3val:0x3aca; valaddr_reg:x1; val_offset:642*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 642*FLEN/8, x4, x2, x6) + +inst_247: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x16a and fs2 == 0 and fe2 == 0x13 and fm2 == 0x103 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ca and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x296a; op2val:0x4d03; +op3val:0x3aca; valaddr_reg:x1; val_offset:645*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 645*FLEN/8, x4, x2, x6) + +inst_248: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x16a and fs2 == 0 and fe2 == 0x13 and fm2 == 0x103 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ca and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x296a; op2val:0x4d03; +op3val:0x3aca; valaddr_reg:x1; val_offset:648*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 648*FLEN/8, x4, x2, x6) + +inst_249: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x16a and fs2 == 0 and fe2 == 0x13 and fm2 == 0x103 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ca and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x296a; op2val:0x4d03; +op3val:0x3aca; valaddr_reg:x1; val_offset:651*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 651*FLEN/8, x4, x2, x6) + +inst_250: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x297 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x375 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x224 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a97; op2val:0x3b75; +op3val:0x3a24; valaddr_reg:x1; val_offset:654*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 654*FLEN/8, x4, x2, x6) + +inst_251: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x297 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x375 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x224 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a97; op2val:0x3b75; +op3val:0x3a24; valaddr_reg:x1; val_offset:657*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 657*FLEN/8, x4, x2, x6) + +inst_252: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x297 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x375 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x224 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a97; op2val:0x3b75; +op3val:0x3a24; valaddr_reg:x1; val_offset:660*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 660*FLEN/8, x4, x2, x6) + +inst_253: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x297 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x375 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x224 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a97; op2val:0x3b75; +op3val:0x3a24; valaddr_reg:x1; val_offset:663*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 663*FLEN/8, x4, x2, x6) + +inst_254: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x297 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x375 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x224 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a97; op2val:0x3b75; +op3val:0x3a24; valaddr_reg:x1; val_offset:666*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 666*FLEN/8, x4, x2, x6) + +inst_255: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x222 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x160 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x01e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a22; op2val:0x3960; +op3val:0x381e; valaddr_reg:x1; val_offset:669*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 669*FLEN/8, x4, x2, x6) + +inst_256: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x222 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x160 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x01e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a22; op2val:0x3960; +op3val:0x381e; valaddr_reg:x1; val_offset:672*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 672*FLEN/8, x4, x2, x6) + +inst_257: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x222 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x160 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x01e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a22; op2val:0x3960; +op3val:0x381e; valaddr_reg:x1; val_offset:675*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 675*FLEN/8, x4, x2, x6) + +inst_258: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x222 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x160 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x01e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a22; op2val:0x3960; +op3val:0x381e; valaddr_reg:x1; val_offset:678*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 678*FLEN/8, x4, x2, x6) + +inst_259: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x222 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x160 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x01e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a22; op2val:0x3960; +op3val:0x381e; valaddr_reg:x1; val_offset:681*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 681*FLEN/8, x4, x2, x6) + +inst_260: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x293 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x32d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3693; op2val:0x3f2d; +op3val:0x39e5; valaddr_reg:x1; val_offset:684*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 684*FLEN/8, x4, x2, x6) + +inst_261: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x293 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x32d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3693; op2val:0x3f2d; +op3val:0x39e5; valaddr_reg:x1; val_offset:687*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 687*FLEN/8, x4, x2, x6) + +inst_262: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x293 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x32d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3693; op2val:0x3f2d; +op3val:0x39e5; valaddr_reg:x1; val_offset:690*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 690*FLEN/8, x4, x2, x6) + +inst_263: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x293 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x32d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3693; op2val:0x3f2d; +op3val:0x39e5; valaddr_reg:x1; val_offset:693*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 693*FLEN/8, x4, x2, x6) + +inst_264: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x293 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x32d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3693; op2val:0x3f2d; +op3val:0x39e5; valaddr_reg:x1; val_offset:696*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 696*FLEN/8, x4, x2, x6) + +inst_265: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0ab and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0a6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bf7; op2val:0x38ab; +op3val:0x38a6; valaddr_reg:x1; val_offset:699*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 699*FLEN/8, x4, x2, x6) + +inst_266: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0ab and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0a6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bf7; op2val:0x38ab; +op3val:0x38a6; valaddr_reg:x1; val_offset:702*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 702*FLEN/8, x4, x2, x6) + +inst_267: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0ab and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0a6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bf7; op2val:0x38ab; +op3val:0x38a6; valaddr_reg:x1; val_offset:705*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 705*FLEN/8, x4, x2, x6) + +inst_268: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0ab and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0a6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bf7; op2val:0x38ab; +op3val:0x38a6; valaddr_reg:x1; val_offset:708*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 708*FLEN/8, x4, x2, x6) + +inst_269: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0ab and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0a6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bf7; op2val:0x38ab; +op3val:0x38a6; valaddr_reg:x1; val_offset:711*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 711*FLEN/8, x4, x2, x6) + +inst_270: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x10b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x180 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x390b; op2val:0x3980; +op3val:0x36f0; valaddr_reg:x1; val_offset:714*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 714*FLEN/8, x4, x2, x6) + +inst_271: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x10b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x180 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2f0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x390b; op2val:0x3980; +op3val:0x36f0; valaddr_reg:x1; val_offset:717*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 717*FLEN/8, x4, x2, x6) + +inst_272: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x10b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x180 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2f0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x390b; op2val:0x3980; +op3val:0x36f0; valaddr_reg:x1; val_offset:720*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 720*FLEN/8, x4, x2, x6) + +inst_273: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x10b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x180 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2f0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x390b; op2val:0x3980; +op3val:0x36f0; valaddr_reg:x1; val_offset:723*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 723*FLEN/8, x4, x2, x6) + +inst_274: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x10b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x180 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2f0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x390b; op2val:0x3980; +op3val:0x36f0; valaddr_reg:x1; val_offset:726*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 726*FLEN/8, x4, x2, x6) + +inst_275: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x202 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x297 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0f3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2a02; op2val:0x4697; +op3val:0x34f3; valaddr_reg:x1; val_offset:729*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 729*FLEN/8, x4, x2, x6) + +inst_276: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x202 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x297 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0f3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2a02; op2val:0x4697; +op3val:0x34f3; valaddr_reg:x1; val_offset:732*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 732*FLEN/8, x4, x2, x6) + +inst_277: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x202 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x297 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0f3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2a02; op2val:0x4697; +op3val:0x34f3; valaddr_reg:x1; val_offset:735*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 735*FLEN/8, x4, x2, x6) + +inst_278: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x202 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x297 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0f3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2a02; op2val:0x4697; +op3val:0x34f3; valaddr_reg:x1; val_offset:738*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 738*FLEN/8, x4, x2, x6) + +inst_279: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x202 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x297 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0f3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2a02; op2val:0x4697; +op3val:0x34f3; valaddr_reg:x1; val_offset:741*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 741*FLEN/8, x4, x2, x6) + +inst_280: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x250 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x21e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37c0; op2val:0x3a50; +op3val:0x361e; valaddr_reg:x1; val_offset:744*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 744*FLEN/8, x4, x2, x6) + +inst_281: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x250 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x21e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37c0; op2val:0x3a50; +op3val:0x361e; valaddr_reg:x1; val_offset:747*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 747*FLEN/8, x4, x2, x6) + +inst_282: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x250 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x21e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37c0; op2val:0x3a50; +op3val:0x361e; valaddr_reg:x1; val_offset:750*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 750*FLEN/8, x4, x2, x6) + +inst_283: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x250 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x21e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37c0; op2val:0x3a50; +op3val:0x361e; valaddr_reg:x1; val_offset:753*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 753*FLEN/8, x4, x2, x6) +RVTEST_SIGBASE(x2,signature_x2_2) + +inst_284: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x250 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x21e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37c0; op2val:0x3a50; +op3val:0x361e; valaddr_reg:x1; val_offset:756*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 756*FLEN/8, x4, x2, x6) + +inst_285: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x12e and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1d7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x391 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x352e; op2val:0x41d7; +op3val:0x3b91; valaddr_reg:x1; val_offset:759*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 759*FLEN/8, x4, x2, x6) + +inst_286: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x12e and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1d7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x391 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x352e; op2val:0x41d7; +op3val:0x3b91; valaddr_reg:x1; val_offset:762*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 762*FLEN/8, x4, x2, x6) + +inst_287: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x12e and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1d7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x391 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x352e; op2val:0x41d7; +op3val:0x3b91; valaddr_reg:x1; val_offset:765*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 765*FLEN/8, x4, x2, x6) + +inst_288: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x12e and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1d7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x391 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x352e; op2val:0x41d7; +op3val:0x3b91; valaddr_reg:x1; val_offset:768*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 768*FLEN/8, x4, x2, x6) + +inst_289: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x12e and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1d7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x391 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x352e; op2val:0x41d7; +op3val:0x3b91; valaddr_reg:x1; val_offset:771*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 771*FLEN/8, x4, x2, x6) + +inst_290: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x26e and fs2 == 0 and fe2 == 0x10 and fm2 == 0x061 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x30a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e6e; op2val:0x4061; +op3val:0x330a; valaddr_reg:x1; val_offset:774*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 774*FLEN/8, x4, x2, x6) + +inst_291: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x26e and fs2 == 0 and fe2 == 0x10 and fm2 == 0x061 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x30a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e6e; op2val:0x4061; +op3val:0x330a; valaddr_reg:x1; val_offset:777*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 777*FLEN/8, x4, x2, x6) + +inst_292: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x26e and fs2 == 0 and fe2 == 0x10 and fm2 == 0x061 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x30a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e6e; op2val:0x4061; +op3val:0x330a; valaddr_reg:x1; val_offset:780*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 780*FLEN/8, x4, x2, x6) + +inst_293: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x26e and fs2 == 0 and fe2 == 0x10 and fm2 == 0x061 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x30a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e6e; op2val:0x4061; +op3val:0x330a; valaddr_reg:x1; val_offset:783*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 783*FLEN/8, x4, x2, x6) + +inst_294: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x26e and fs2 == 0 and fe2 == 0x10 and fm2 == 0x061 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x30a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e6e; op2val:0x4061; +op3val:0x330a; valaddr_reg:x1; val_offset:786*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 786*FLEN/8, x4, x2, x6) + +inst_295: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x004 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x271 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x278 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3004; op2val:0x3e71; +op3val:0x3278; valaddr_reg:x1; val_offset:789*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 789*FLEN/8, x4, x2, x6) + +inst_296: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x004 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x271 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x278 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3004; op2val:0x3e71; +op3val:0x3278; valaddr_reg:x1; val_offset:792*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 792*FLEN/8, x4, x2, x6) + +inst_297: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x004 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x271 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x278 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3004; op2val:0x3e71; +op3val:0x3278; valaddr_reg:x1; val_offset:795*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 795*FLEN/8, x4, x2, x6) + +inst_298: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x004 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x271 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x278 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3004; op2val:0x3e71; +op3val:0x3278; valaddr_reg:x1; val_offset:798*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 798*FLEN/8, x4, x2, x6) + +inst_299: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x004 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x271 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x278 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3004; op2val:0x3e71; +op3val:0x3278; valaddr_reg:x1; val_offset:801*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 801*FLEN/8, x4, x2, x6) + +inst_300: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0dc and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3e9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0ce and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38dc; op2val:0x3be9; +op3val:0x38ce; valaddr_reg:x1; val_offset:804*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 804*FLEN/8, x4, x2, x6) + +inst_301: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0dc and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3e9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0ce and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38dc; op2val:0x3be9; +op3val:0x38ce; valaddr_reg:x1; val_offset:807*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 807*FLEN/8, x4, x2, x6) + +inst_302: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0dc and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3e9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0ce and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38dc; op2val:0x3be9; +op3val:0x38ce; valaddr_reg:x1; val_offset:810*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 810*FLEN/8, x4, x2, x6) + +inst_303: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0dc and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3e9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0ce and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38dc; op2val:0x3be9; +op3val:0x38ce; valaddr_reg:x1; val_offset:813*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 813*FLEN/8, x4, x2, x6) + +inst_304: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0dc and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3e9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0ce and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38dc; op2val:0x3be9; +op3val:0x38ce; valaddr_reg:x1; val_offset:816*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 816*FLEN/8, x4, x2, x6) + +inst_305: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x32b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x287 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1da and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b2b; op2val:0x3687; +op3val:0x35da; valaddr_reg:x1; val_offset:819*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 819*FLEN/8, x4, x2, x6) + +inst_306: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x32b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x287 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1da and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b2b; op2val:0x3687; +op3val:0x35da; valaddr_reg:x1; val_offset:822*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 822*FLEN/8, x4, x2, x6) + +inst_307: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x32b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x287 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1da and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b2b; op2val:0x3687; +op3val:0x35da; valaddr_reg:x1; val_offset:825*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 825*FLEN/8, x4, x2, x6) + +inst_308: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x32b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x287 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1da and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b2b; op2val:0x3687; +op3val:0x35da; valaddr_reg:x1; val_offset:828*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 828*FLEN/8, x4, x2, x6) + +inst_309: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x32b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x287 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1da and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b2b; op2val:0x3687; +op3val:0x35da; valaddr_reg:x1; val_offset:831*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 831*FLEN/8, x4, x2, x6) + +inst_310: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x380 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3f4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x376 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b80; op2val:0x3bf4; +op3val:0x3b76; valaddr_reg:x1; val_offset:834*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 834*FLEN/8, x4, x2, x6) + +inst_311: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x380 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3f4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x376 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b80; op2val:0x3bf4; +op3val:0x3b76; valaddr_reg:x1; val_offset:837*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 837*FLEN/8, x4, x2, x6) + +inst_312: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x380 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3f4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x376 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b80; op2val:0x3bf4; +op3val:0x3b76; valaddr_reg:x1; val_offset:840*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 840*FLEN/8, x4, x2, x6) + +inst_313: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x380 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3f4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x376 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b80; op2val:0x3bf4; +op3val:0x3b76; valaddr_reg:x1; val_offset:843*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 843*FLEN/8, x4, x2, x6) + +inst_314: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x380 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3f4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x376 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b80; op2val:0x3bf4; +op3val:0x3b76; valaddr_reg:x1; val_offset:846*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 846*FLEN/8, x4, x2, x6) + +inst_315: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x254 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x03c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a54; op2val:0x3c3c; +op3val:0x3ab3; valaddr_reg:x1; val_offset:849*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 849*FLEN/8, x4, x2, x6) + +inst_316: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x254 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x03c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a54; op2val:0x3c3c; +op3val:0x3ab3; valaddr_reg:x1; val_offset:852*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 852*FLEN/8, x4, x2, x6) + +inst_317: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x254 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x03c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a54; op2val:0x3c3c; +op3val:0x3ab3; valaddr_reg:x1; val_offset:855*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 855*FLEN/8, x4, x2, x6) + +inst_318: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x254 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x03c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a54; op2val:0x3c3c; +op3val:0x3ab3; valaddr_reg:x1; val_offset:858*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 858*FLEN/8, x4, x2, x6) + +inst_319: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x254 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x03c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a54; op2val:0x3c3c; +op3val:0x3ab3; valaddr_reg:x1; val_offset:861*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 861*FLEN/8, x4, x2, x6) + +inst_320: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x147 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1be and fs3 == 0 and fe3 == 0x0e and fm3 == 0x394 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3947; op2val:0x3dbe; +op3val:0x3b94; valaddr_reg:x1; val_offset:864*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 864*FLEN/8, x4, x2, x6) + +inst_321: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x147 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1be and fs3 == 0 and fe3 == 0x0e and fm3 == 0x394 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3947; op2val:0x3dbe; +op3val:0x3b94; valaddr_reg:x1; val_offset:867*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 867*FLEN/8, x4, x2, x6) + +inst_322: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x147 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1be and fs3 == 0 and fe3 == 0x0e and fm3 == 0x394 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3947; op2val:0x3dbe; +op3val:0x3b94; valaddr_reg:x1; val_offset:870*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 870*FLEN/8, x4, x2, x6) + +inst_323: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x147 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1be and fs3 == 0 and fe3 == 0x0e and fm3 == 0x394 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3947; op2val:0x3dbe; +op3val:0x3b94; valaddr_reg:x1; val_offset:873*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 873*FLEN/8, x4, x2, x6) + +inst_324: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x147 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1be and fs3 == 0 and fe3 == 0x0e and fm3 == 0x394 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3947; op2val:0x3dbe; +op3val:0x3b94; valaddr_reg:x1; val_offset:876*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 876*FLEN/8, x4, x2, x6) + +inst_325: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ca and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ca and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bff; op2val:0x3aca; +op3val:0x3aca; valaddr_reg:x1; val_offset:879*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 879*FLEN/8, x4, x2, x6) + +inst_326: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ca and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ca and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bff; op2val:0x3aca; +op3val:0x3aca; valaddr_reg:x1; val_offset:882*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 882*FLEN/8, x4, x2, x6) + +inst_327: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ca and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ca and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bff; op2val:0x3aca; +op3val:0x3aca; valaddr_reg:x1; val_offset:885*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 885*FLEN/8, x4, x2, x6) + +inst_328: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ca and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ca and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bff; op2val:0x3aca; +op3val:0x3aca; valaddr_reg:x1; val_offset:888*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 888*FLEN/8, x4, x2, x6) + +inst_329: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ca and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ca and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bff; op2val:0x3aca; +op3val:0x3aca; valaddr_reg:x1; val_offset:891*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 891*FLEN/8, x4, x2, x6) + +inst_330: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x330 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1aa and fs3 == 0 and fe3 == 0x0e and fm3 == 0x117 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b30; op2val:0x39aa; +op3val:0x3917; valaddr_reg:x1; val_offset:894*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 894*FLEN/8, x4, x2, x6) + +inst_331: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x330 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1aa and fs3 == 0 and fe3 == 0x0e and fm3 == 0x117 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b30; op2val:0x39aa; +op3val:0x3917; valaddr_reg:x1; val_offset:897*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 897*FLEN/8, x4, x2, x6) + +inst_332: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x330 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1aa and fs3 == 0 and fe3 == 0x0e and fm3 == 0x117 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b30; op2val:0x39aa; +op3val:0x3917; valaddr_reg:x1; val_offset:900*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 900*FLEN/8, x4, x2, x6) + +inst_333: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x330 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1aa and fs3 == 0 and fe3 == 0x0e and fm3 == 0x117 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b30; op2val:0x39aa; +op3val:0x3917; valaddr_reg:x1; val_offset:903*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 903*FLEN/8, x4, x2, x6) + +inst_334: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x330 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1aa and fs3 == 0 and fe3 == 0x0e and fm3 == 0x117 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b30; op2val:0x39aa; +op3val:0x3917; valaddr_reg:x1; val_offset:906*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 906*FLEN/8, x4, x2, x6) + +inst_335: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3cb and fs2 == 0 and fe2 == 0x0c and fm2 == 0x021 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x005 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bcb; op2val:0x3021; +op3val:0x3005; valaddr_reg:x1; val_offset:909*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 909*FLEN/8, x4, x2, x6) + +inst_336: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3cb and fs2 == 0 and fe2 == 0x0c and fm2 == 0x021 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x005 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bcb; op2val:0x3021; +op3val:0x3005; valaddr_reg:x1; val_offset:912*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 912*FLEN/8, x4, x2, x6) + +inst_337: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3cb and fs2 == 0 and fe2 == 0x0c and fm2 == 0x021 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x005 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bcb; op2val:0x3021; +op3val:0x3005; valaddr_reg:x1; val_offset:915*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 915*FLEN/8, x4, x2, x6) + +inst_338: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3cb and fs2 == 0 and fe2 == 0x0c and fm2 == 0x021 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x005 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bcb; op2val:0x3021; +op3val:0x3005; valaddr_reg:x1; val_offset:918*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 918*FLEN/8, x4, x2, x6) + +inst_339: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3cb and fs2 == 0 and fe2 == 0x0c and fm2 == 0x021 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x005 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bcb; op2val:0x3021; +op3val:0x3005; valaddr_reg:x1; val_offset:921*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 921*FLEN/8, x4, x2, x6) + +inst_340: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x22c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x069 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2cf and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x362c; op2val:0x4069; +op3val:0x3acf; valaddr_reg:x1; val_offset:924*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 924*FLEN/8, x4, x2, x6) + +inst_341: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x22c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x069 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2cf and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x362c; op2val:0x4069; +op3val:0x3acf; valaddr_reg:x1; val_offset:927*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 927*FLEN/8, x4, x2, x6) + +inst_342: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x22c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x069 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2cf and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x362c; op2val:0x4069; +op3val:0x3acf; valaddr_reg:x1; val_offset:930*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 930*FLEN/8, x4, x2, x6) + +inst_343: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x22c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x069 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2cf and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x362c; op2val:0x4069; +op3val:0x3acf; valaddr_reg:x1; val_offset:933*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 933*FLEN/8, x4, x2, x6) + +inst_344: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x22c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x069 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2cf and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x362c; op2val:0x4069; +op3val:0x3acf; valaddr_reg:x1; val_offset:936*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 936*FLEN/8, x4, x2, x6) + +inst_345: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2fb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x138 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39fb; op2val:0x3afb; +op3val:0x3938; valaddr_reg:x1; val_offset:939*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 939*FLEN/8, x4, x2, x6) + +inst_346: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2fb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x138 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39fb; op2val:0x3afb; +op3val:0x3938; valaddr_reg:x1; val_offset:942*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 942*FLEN/8, x4, x2, x6) + +inst_347: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2fb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x138 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39fb; op2val:0x3afb; +op3val:0x3938; valaddr_reg:x1; val_offset:945*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 945*FLEN/8, x4, x2, x6) + +inst_348: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2fb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x138 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39fb; op2val:0x3afb; +op3val:0x3938; valaddr_reg:x1; val_offset:948*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 948*FLEN/8, x4, x2, x6) + +inst_349: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2fb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x138 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39fb; op2val:0x3afb; +op3val:0x3938; valaddr_reg:x1; val_offset:951*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 951*FLEN/8, x4, x2, x6) + +inst_350: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x116 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x184 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x304 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3916; op2val:0x3d84; +op3val:0x3b04; valaddr_reg:x1; val_offset:954*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 954*FLEN/8, x4, x2, x6) + +inst_351: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x116 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x184 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x304 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3916; op2val:0x3d84; +op3val:0x3b04; valaddr_reg:x1; val_offset:957*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 957*FLEN/8, x4, x2, x6) + +inst_352: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x116 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x184 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x304 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3916; op2val:0x3d84; +op3val:0x3b04; valaddr_reg:x1; val_offset:960*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 960*FLEN/8, x4, x2, x6) + +inst_353: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x116 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x184 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x304 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3916; op2val:0x3d84; +op3val:0x3b04; valaddr_reg:x1; val_offset:963*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 963*FLEN/8, x4, x2, x6) + +inst_354: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x116 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x184 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x304 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3916; op2val:0x3d84; +op3val:0x3b04; valaddr_reg:x1; val_offset:966*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 966*FLEN/8, x4, x2, x6) + +inst_355: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0d5 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x1f1 and fs3 == 0 and fe3 == 0x07 and fm3 == 0x31f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30d5; op2val:0x29f1; +op3val:0x1f1f; valaddr_reg:x1; val_offset:969*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 969*FLEN/8, x4, x2, x6) + +inst_356: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0d5 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x1f1 and fs3 == 0 and fe3 == 0x07 and fm3 == 0x31f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30d5; op2val:0x29f1; +op3val:0x1f1f; valaddr_reg:x1; val_offset:972*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 972*FLEN/8, x4, x2, x6) + +inst_357: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0d5 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x1f1 and fs3 == 0 and fe3 == 0x07 and fm3 == 0x31f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30d5; op2val:0x29f1; +op3val:0x1f1f; valaddr_reg:x1; val_offset:975*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 975*FLEN/8, x4, x2, x6) + +inst_358: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0d5 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x1f1 and fs3 == 0 and fe3 == 0x07 and fm3 == 0x31f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30d5; op2val:0x29f1; +op3val:0x1f1f; valaddr_reg:x1; val_offset:978*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 978*FLEN/8, x4, x2, x6) + +inst_359: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0d5 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x1f1 and fs3 == 0 and fe3 == 0x07 and fm3 == 0x31f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30d5; op2val:0x29f1; +op3val:0x1f1f; valaddr_reg:x1; val_offset:981*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 981*FLEN/8, x4, x2, x6) + +inst_360: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x045 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3bb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x021 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3845; op2val:0x3bbb; +op3val:0x3821; valaddr_reg:x1; val_offset:984*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 984*FLEN/8, x4, x2, x6) + +inst_361: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x045 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3bb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x021 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3845; op2val:0x3bbb; +op3val:0x3821; valaddr_reg:x1; val_offset:987*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 987*FLEN/8, x4, x2, x6) + +inst_362: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x045 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3bb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x021 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3845; op2val:0x3bbb; +op3val:0x3821; valaddr_reg:x1; val_offset:990*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 990*FLEN/8, x4, x2, x6) + +inst_363: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x045 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3bb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x021 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3845; op2val:0x3bbb; +op3val:0x3821; valaddr_reg:x1; val_offset:993*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 993*FLEN/8, x4, x2, x6) + +inst_364: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x045 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3bb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x021 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3845; op2val:0x3bbb; +op3val:0x3821; valaddr_reg:x1; val_offset:996*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 996*FLEN/8, x4, x2, x6) + +inst_365: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x350 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3db and fs3 == 0 and fe3 == 0x0e and fm3 == 0x32e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b50; op2val:0x3bdb; +op3val:0x3b2e; valaddr_reg:x1; val_offset:999*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 999*FLEN/8, x4, x2, x6) + +inst_366: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x350 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3db and fs3 == 0 and fe3 == 0x0e and fm3 == 0x32e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b50; op2val:0x3bdb; +op3val:0x3b2e; valaddr_reg:x1; val_offset:1002*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1002*FLEN/8, x4, x2, x6) + +inst_367: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x350 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3db and fs3 == 0 and fe3 == 0x0e and fm3 == 0x32e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b50; op2val:0x3bdb; +op3val:0x3b2e; valaddr_reg:x1; val_offset:1005*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1005*FLEN/8, x4, x2, x6) + +inst_368: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x350 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3db and fs3 == 0 and fe3 == 0x0e and fm3 == 0x32e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b50; op2val:0x3bdb; +op3val:0x3b2e; valaddr_reg:x1; val_offset:1008*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1008*FLEN/8, x4, x2, x6) + +inst_369: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x350 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3db and fs3 == 0 and fe3 == 0x0e and fm3 == 0x32e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b50; op2val:0x3bdb; +op3val:0x3b2e; valaddr_reg:x1; val_offset:1011*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1011*FLEN/8, x4, x2, x6) + +inst_370: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x142 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x079 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3942; op2val:0x3c79; +op3val:0x39e1; valaddr_reg:x1; val_offset:1014*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1014*FLEN/8, x4, x2, x6) + +inst_371: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x142 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x079 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3942; op2val:0x3c79; +op3val:0x39e1; valaddr_reg:x1; val_offset:1017*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1017*FLEN/8, x4, x2, x6) + +inst_372: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x142 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x079 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3942; op2val:0x3c79; +op3val:0x39e1; valaddr_reg:x1; val_offset:1020*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1020*FLEN/8, x4, x2, x6) + +inst_373: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x142 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x079 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3942; op2val:0x3c79; +op3val:0x39e1; valaddr_reg:x1; val_offset:1023*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1023*FLEN/8, x4, x2, x6) + +inst_374: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x142 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x079 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3942; op2val:0x3c79; +op3val:0x39e1; valaddr_reg:x1; val_offset:1026*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1026*FLEN/8, x4, x2, x6) + +inst_375: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x17a and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0e6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x317a; op2val:0x44e6; +op3val:0x3ab5; valaddr_reg:x1; val_offset:1029*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1029*FLEN/8, x4, x2, x6) + +inst_376: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x17a and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0e6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x317a; op2val:0x44e6; +op3val:0x3ab5; valaddr_reg:x1; val_offset:1032*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1032*FLEN/8, x4, x2, x6) + +inst_377: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x17a and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0e6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x317a; op2val:0x44e6; +op3val:0x3ab5; valaddr_reg:x1; val_offset:1035*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1035*FLEN/8, x4, x2, x6) + +inst_378: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x17a and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0e6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x317a; op2val:0x44e6; +op3val:0x3ab5; valaddr_reg:x1; val_offset:1038*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1038*FLEN/8, x4, x2, x6) + +inst_379: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x17a and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0e6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x317a; op2val:0x44e6; +op3val:0x3ab5; valaddr_reg:x1; val_offset:1041*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1041*FLEN/8, x4, x2, x6) + +inst_380: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d0 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x270 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x248 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bd0; op2val:0x2a70; +op3val:0x2a48; valaddr_reg:x1; val_offset:1044*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1044*FLEN/8, x4, x2, x6) + +inst_381: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d0 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x270 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x248 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bd0; op2val:0x2a70; +op3val:0x2a48; valaddr_reg:x1; val_offset:1047*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1047*FLEN/8, x4, x2, x6) + +inst_382: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d0 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x270 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x248 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bd0; op2val:0x2a70; +op3val:0x2a48; valaddr_reg:x1; val_offset:1050*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1050*FLEN/8, x4, x2, x6) + +inst_383: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d0 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x270 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x248 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bd0; op2val:0x2a70; +op3val:0x2a48; valaddr_reg:x1; val_offset:1053*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1053*FLEN/8, x4, x2, x6) + +inst_384: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d0 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x270 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x248 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bd0; op2val:0x2a70; +op3val:0x2a48; valaddr_reg:x1; val_offset:1056*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1056*FLEN/8, x4, x2, x6) + +inst_385: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x38c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x33c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2d3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x378c; op2val:0x3f3c; +op3val:0x3ad3; valaddr_reg:x1; val_offset:1059*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1059*FLEN/8, x4, x2, x6) + +inst_386: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x38c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x33c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2d3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x378c; op2val:0x3f3c; +op3val:0x3ad3; valaddr_reg:x1; val_offset:1062*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1062*FLEN/8, x4, x2, x6) + +inst_387: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x38c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x33c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2d3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x378c; op2val:0x3f3c; +op3val:0x3ad3; valaddr_reg:x1; val_offset:1065*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1065*FLEN/8, x4, x2, x6) + +inst_388: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x38c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x33c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2d3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x378c; op2val:0x3f3c; +op3val:0x3ad3; valaddr_reg:x1; val_offset:1068*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1068*FLEN/8, x4, x2, x6) + +inst_389: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x38c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x33c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2d3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x378c; op2val:0x3f3c; +op3val:0x3ad3; valaddr_reg:x1; val_offset:1071*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1071*FLEN/8, x4, x2, x6) + +inst_390: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x34f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x042 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3c8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x374f; op2val:0x4042; +op3val:0x3bc8; valaddr_reg:x1; val_offset:1074*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1074*FLEN/8, x4, x2, x6) + +inst_391: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x34f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x042 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3c8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x374f; op2val:0x4042; +op3val:0x3bc8; valaddr_reg:x1; val_offset:1077*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1077*FLEN/8, x4, x2, x6) + +inst_392: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x34f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x042 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3c8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x374f; op2val:0x4042; +op3val:0x3bc8; valaddr_reg:x1; val_offset:1080*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1080*FLEN/8, x4, x2, x6) + +inst_393: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x34f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x042 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3c8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x374f; op2val:0x4042; +op3val:0x3bc8; valaddr_reg:x1; val_offset:1083*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1083*FLEN/8, x4, x2, x6) + +inst_394: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x34f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x042 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3c8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x374f; op2val:0x4042; +op3val:0x3bc8; valaddr_reg:x1; val_offset:1086*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1086*FLEN/8, x4, x2, x6) + +inst_395: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x38c and fs2 == 0 and fe2 == 0x0a and fm2 == 0x1dd and fs3 == 0 and fe3 == 0x09 and fm3 == 0x184 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x378c; op2val:0x29dd; +op3val:0x2584; valaddr_reg:x1; val_offset:1089*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1089*FLEN/8, x4, x2, x6) + +inst_396: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x38c and fs2 == 0 and fe2 == 0x0a and fm2 == 0x1dd and fs3 == 0 and fe3 == 0x09 and fm3 == 0x184 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x378c; op2val:0x29dd; +op3val:0x2584; valaddr_reg:x1; val_offset:1092*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1092*FLEN/8, x4, x2, x6) + +inst_397: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x38c and fs2 == 0 and fe2 == 0x0a and fm2 == 0x1dd and fs3 == 0 and fe3 == 0x09 and fm3 == 0x184 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x378c; op2val:0x29dd; +op3val:0x2584; valaddr_reg:x1; val_offset:1095*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1095*FLEN/8, x4, x2, x6) + +inst_398: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x38c and fs2 == 0 and fe2 == 0x0a and fm2 == 0x1dd and fs3 == 0 and fe3 == 0x09 and fm3 == 0x184 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x378c; op2val:0x29dd; +op3val:0x2584; valaddr_reg:x1; val_offset:1098*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1098*FLEN/8, x4, x2, x6) + +inst_399: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x38c and fs2 == 0 and fe2 == 0x0a and fm2 == 0x1dd and fs3 == 0 and fe3 == 0x09 and fm3 == 0x184 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x378c; op2val:0x29dd; +op3val:0x2584; valaddr_reg:x1; val_offset:1101*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1101*FLEN/8, x4, x2, x6) + +inst_400: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x060 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x072 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0dc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3060; op2val:0x4072; +op3val:0x34dc; valaddr_reg:x1; val_offset:1104*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1104*FLEN/8, x4, x2, x6) + +inst_401: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x060 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x072 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0dc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3060; op2val:0x4072; +op3val:0x34dc; valaddr_reg:x1; val_offset:1107*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1107*FLEN/8, x4, x2, x6) + +inst_402: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x060 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x072 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0dc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3060; op2val:0x4072; +op3val:0x34dc; valaddr_reg:x1; val_offset:1110*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1110*FLEN/8, x4, x2, x6) + +inst_403: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x060 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x072 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0dc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3060; op2val:0x4072; +op3val:0x34dc; valaddr_reg:x1; val_offset:1113*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1113*FLEN/8, x4, x2, x6) + +inst_404: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x060 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x072 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0dc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3060; op2val:0x4072; +op3val:0x34dc; valaddr_reg:x1; val_offset:1116*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1116*FLEN/8, x4, x2, x6) + +inst_405: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1e9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2db and fs3 == 0 and fe3 == 0x0e and fm3 == 0x111 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39e9; op2val:0x3adb; +op3val:0x3911; valaddr_reg:x1; val_offset:1119*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1119*FLEN/8, x4, x2, x6) + +inst_406: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1e9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2db and fs3 == 0 and fe3 == 0x0e and fm3 == 0x111 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39e9; op2val:0x3adb; +op3val:0x3911; valaddr_reg:x1; val_offset:1122*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1122*FLEN/8, x4, x2, x6) + +inst_407: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1e9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2db and fs3 == 0 and fe3 == 0x0e and fm3 == 0x111 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39e9; op2val:0x3adb; +op3val:0x3911; valaddr_reg:x1; val_offset:1125*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1125*FLEN/8, x4, x2, x6) + +inst_408: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1e9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2db and fs3 == 0 and fe3 == 0x0e and fm3 == 0x111 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39e9; op2val:0x3adb; +op3val:0x3911; valaddr_reg:x1; val_offset:1128*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1128*FLEN/8, x4, x2, x6) + +inst_409: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1e9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2db and fs3 == 0 and fe3 == 0x0e and fm3 == 0x111 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39e9; op2val:0x3adb; +op3val:0x3911; valaddr_reg:x1; val_offset:1131*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1131*FLEN/8, x4, x2, x6) + +inst_410: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2a9 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x061 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x34c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aa9; op2val:0x3461; +op3val:0x334c; valaddr_reg:x1; val_offset:1134*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1134*FLEN/8, x4, x2, x6) + +inst_411: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2a9 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x061 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x34c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aa9; op2val:0x3461; +op3val:0x334c; valaddr_reg:x1; val_offset:1137*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1137*FLEN/8, x4, x2, x6) +RVTEST_SIGBASE(x2,signature_x2_3) + +inst_412: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2a9 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x061 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x34c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aa9; op2val:0x3461; +op3val:0x334c; valaddr_reg:x1; val_offset:1140*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1140*FLEN/8, x4, x2, x6) + +inst_413: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2a9 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x061 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x34c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aa9; op2val:0x3461; +op3val:0x334c; valaddr_reg:x1; val_offset:1143*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1143*FLEN/8, x4, x2, x6) + +inst_414: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2a9 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x061 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x34c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aa9; op2val:0x3461; +op3val:0x334c; valaddr_reg:x1; val_offset:1146*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1146*FLEN/8, x4, x2, x6) + +inst_415: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x37a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x391 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x312 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x377a; op2val:0x3791; +op3val:0x3312; valaddr_reg:x1; val_offset:1149*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1149*FLEN/8, x4, x2, x6) + +inst_416: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x37a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x391 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x312 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x377a; op2val:0x3791; +op3val:0x3312; valaddr_reg:x1; val_offset:1152*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1152*FLEN/8, x4, x2, x6) + +inst_417: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x37a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x391 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x312 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x377a; op2val:0x3791; +op3val:0x3312; valaddr_reg:x1; val_offset:1155*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1155*FLEN/8, x4, x2, x6) + +inst_418: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x37a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x391 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x312 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x377a; op2val:0x3791; +op3val:0x3312; valaddr_reg:x1; val_offset:1158*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1158*FLEN/8, x4, x2, x6) + +inst_419: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x37a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x391 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x312 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x377a; op2val:0x3791; +op3val:0x3312; valaddr_reg:x1; val_offset:1161*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1161*FLEN/8, x4, x2, x6) + +inst_420: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x15c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0a2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x237 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x395c; op2val:0x3ca2; +op3val:0x3a37; valaddr_reg:x1; val_offset:1164*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1164*FLEN/8, x4, x2, x6) + +inst_421: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x15c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0a2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x237 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x395c; op2val:0x3ca2; +op3val:0x3a37; valaddr_reg:x1; val_offset:1167*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1167*FLEN/8, x4, x2, x6) + +inst_422: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x15c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0a2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x237 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x395c; op2val:0x3ca2; +op3val:0x3a37; valaddr_reg:x1; val_offset:1170*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1170*FLEN/8, x4, x2, x6) + +inst_423: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x15c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0a2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x237 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x395c; op2val:0x3ca2; +op3val:0x3a37; valaddr_reg:x1; val_offset:1173*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1173*FLEN/8, x4, x2, x6) + +inst_424: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x15c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0a2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x237 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x395c; op2val:0x3ca2; +op3val:0x3a37; valaddr_reg:x1; val_offset:1176*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1176*FLEN/8, x4, x2, x6) + +inst_425: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x208 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x125 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x3bd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3208; op2val:0x2d25; +op3val:0x23bd; valaddr_reg:x1; val_offset:1179*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1179*FLEN/8, x4, x2, x6) + +inst_426: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x208 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x125 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x3bd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3208; op2val:0x2d25; +op3val:0x23bd; valaddr_reg:x1; val_offset:1182*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1182*FLEN/8, x4, x2, x6) + +inst_427: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x208 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x125 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x3bd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3208; op2val:0x2d25; +op3val:0x23bd; valaddr_reg:x1; val_offset:1185*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1185*FLEN/8, x4, x2, x6) + +inst_428: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x208 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x125 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x3bd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3208; op2val:0x2d25; +op3val:0x23bd; valaddr_reg:x1; val_offset:1188*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1188*FLEN/8, x4, x2, x6) + +inst_429: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x208 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x125 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x3bd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3208; op2val:0x2d25; +op3val:0x23bd; valaddr_reg:x1; val_offset:1191*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1191*FLEN/8, x4, x2, x6) + +inst_430: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0b7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x143 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x234 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30b7; op2val:0x3d43; +op3val:0x3234; valaddr_reg:x1; val_offset:1194*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1194*FLEN/8, x4, x2, x6) + +inst_431: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0b7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x143 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x234 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30b7; op2val:0x3d43; +op3val:0x3234; valaddr_reg:x1; val_offset:1197*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1197*FLEN/8, x4, x2, x6) + +inst_432: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0b7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x143 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x234 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30b7; op2val:0x3d43; +op3val:0x3234; valaddr_reg:x1; val_offset:1200*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1200*FLEN/8, x4, x2, x6) + +inst_433: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0b7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x143 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x234 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30b7; op2val:0x3d43; +op3val:0x3234; valaddr_reg:x1; val_offset:1203*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1203*FLEN/8, x4, x2, x6) + +inst_434: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0b7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x143 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x234 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30b7; op2val:0x3d43; +op3val:0x3234; valaddr_reg:x1; val_offset:1206*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1206*FLEN/8, x4, x2, x6) + +inst_435: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1d0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1ba and fs3 == 0 and fe3 == 0x0d and fm3 == 0x029 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31d0; op2val:0x3dba; +op3val:0x3429; valaddr_reg:x1; val_offset:1209*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1209*FLEN/8, x4, x2, x6) + +inst_436: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1d0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1ba and fs3 == 0 and fe3 == 0x0d and fm3 == 0x029 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31d0; op2val:0x3dba; +op3val:0x3429; valaddr_reg:x1; val_offset:1212*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1212*FLEN/8, x4, x2, x6) + +inst_437: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1d0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1ba and fs3 == 0 and fe3 == 0x0d and fm3 == 0x029 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31d0; op2val:0x3dba; +op3val:0x3429; valaddr_reg:x1; val_offset:1215*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1215*FLEN/8, x4, x2, x6) + +inst_438: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1d0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1ba and fs3 == 0 and fe3 == 0x0d and fm3 == 0x029 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31d0; op2val:0x3dba; +op3val:0x3429; valaddr_reg:x1; val_offset:1218*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1218*FLEN/8, x4, x2, x6) + +inst_439: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1d0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1ba and fs3 == 0 and fe3 == 0x0d and fm3 == 0x029 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31d0; op2val:0x3dba; +op3val:0x3429; valaddr_reg:x1; val_offset:1221*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1221*FLEN/8, x4, x2, x6) + +inst_440: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x22f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0fd and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3b7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a2f; op2val:0x38fd; +op3val:0x37b7; valaddr_reg:x1; val_offset:1224*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1224*FLEN/8, x4, x2, x6) + +inst_441: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x22f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0fd and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3b7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a2f; op2val:0x38fd; +op3val:0x37b7; valaddr_reg:x1; val_offset:1227*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1227*FLEN/8, x4, x2, x6) + +inst_442: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x22f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0fd and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3b7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a2f; op2val:0x38fd; +op3val:0x37b7; valaddr_reg:x1; val_offset:1230*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1230*FLEN/8, x4, x2, x6) + +inst_443: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x22f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0fd and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3b7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a2f; op2val:0x38fd; +op3val:0x37b7; valaddr_reg:x1; val_offset:1233*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1233*FLEN/8, x4, x2, x6) + +inst_444: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x22f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0fd and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3b7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a2f; op2val:0x38fd; +op3val:0x37b7; valaddr_reg:x1; val_offset:1236*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1236*FLEN/8, x4, x2, x6) + +inst_445: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x127 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x206 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3c4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3927; op2val:0x3e06; +op3val:0x3bc4; valaddr_reg:x1; val_offset:1239*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1239*FLEN/8, x4, x2, x6) + +inst_446: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x127 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x206 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3c4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3927; op2val:0x3e06; +op3val:0x3bc4; valaddr_reg:x1; val_offset:1242*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1242*FLEN/8, x4, x2, x6) + +inst_447: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x127 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x206 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3c4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3927; op2val:0x3e06; +op3val:0x3bc4; valaddr_reg:x1; val_offset:1245*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1245*FLEN/8, x4, x2, x6) + +inst_448: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x127 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x206 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3c4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3927; op2val:0x3e06; +op3val:0x3bc4; valaddr_reg:x1; val_offset:1248*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1248*FLEN/8, x4, x2, x6) + +inst_449: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x127 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x206 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3c4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3927; op2val:0x3e06; +op3val:0x3bc4; valaddr_reg:x1; val_offset:1251*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1251*FLEN/8, x4, x2, x6) + +inst_450: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1ee and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1c3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bc6; op2val:0x39ee; +op3val:0x39c3; valaddr_reg:x1; val_offset:1254*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1254*FLEN/8, x4, x2, x6) + +inst_451: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1ee and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1c3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bc6; op2val:0x39ee; +op3val:0x39c3; valaddr_reg:x1; val_offset:1257*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1257*FLEN/8, x4, x2, x6) + +inst_452: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1ee and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1c3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bc6; op2val:0x39ee; +op3val:0x39c3; valaddr_reg:x1; val_offset:1260*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1260*FLEN/8, x4, x2, x6) + +inst_453: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1ee and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1c3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bc6; op2val:0x39ee; +op3val:0x39c3; valaddr_reg:x1; val_offset:1263*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1263*FLEN/8, x4, x2, x6) + +inst_454: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1ee and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1c3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bc6; op2val:0x39ee; +op3val:0x39c3; valaddr_reg:x1; val_offset:1266*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1266*FLEN/8, x4, x2, x6) + +inst_455: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ed and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2a4 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0eb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39ed; op2val:0x36a4; +op3val:0x34eb; valaddr_reg:x1; val_offset:1269*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1269*FLEN/8, x4, x2, x6) + +inst_456: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ed and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2a4 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0eb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39ed; op2val:0x36a4; +op3val:0x34eb; valaddr_reg:x1; val_offset:1272*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1272*FLEN/8, x4, x2, x6) + +inst_457: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ed and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2a4 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0eb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39ed; op2val:0x36a4; +op3val:0x34eb; valaddr_reg:x1; val_offset:1275*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1275*FLEN/8, x4, x2, x6) + +inst_458: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ed and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2a4 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0eb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39ed; op2val:0x36a4; +op3val:0x34eb; valaddr_reg:x1; val_offset:1278*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1278*FLEN/8, x4, x2, x6) + +inst_459: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ed and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2a4 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0eb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39ed; op2val:0x36a4; +op3val:0x34eb; valaddr_reg:x1; val_offset:1281*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1281*FLEN/8, x4, x2, x6) + +inst_460: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x192 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x259 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x06c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2992; op2val:0x4a59; +op3val:0x386c; valaddr_reg:x1; val_offset:1284*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1284*FLEN/8, x4, x2, x6) + +inst_461: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x192 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x259 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x06c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2992; op2val:0x4a59; +op3val:0x386c; valaddr_reg:x1; val_offset:1287*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1287*FLEN/8, x4, x2, x6) + +inst_462: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x192 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x259 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x06c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2992; op2val:0x4a59; +op3val:0x386c; valaddr_reg:x1; val_offset:1290*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1290*FLEN/8, x4, x2, x6) + +inst_463: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x192 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x259 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x06c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2992; op2val:0x4a59; +op3val:0x386c; valaddr_reg:x1; val_offset:1293*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1293*FLEN/8, x4, x2, x6) + +inst_464: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x192 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x259 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x06c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2992; op2val:0x4a59; +op3val:0x386c; valaddr_reg:x1; val_offset:1296*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1296*FLEN/8, x4, x2, x6) + +inst_465: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x008 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x21d and fs3 == 0 and fe3 == 0x08 and fm3 == 0x225 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2c08; op2val:0x321d; +op3val:0x2225; valaddr_reg:x1; val_offset:1299*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1299*FLEN/8, x4, x2, x6) + +inst_466: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x008 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x21d and fs3 == 0 and fe3 == 0x08 and fm3 == 0x225 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2c08; op2val:0x321d; +op3val:0x2225; valaddr_reg:x1; val_offset:1302*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1302*FLEN/8, x4, x2, x6) + +inst_467: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x008 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x21d and fs3 == 0 and fe3 == 0x08 and fm3 == 0x225 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2c08; op2val:0x321d; +op3val:0x2225; valaddr_reg:x1; val_offset:1305*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1305*FLEN/8, x4, x2, x6) + +inst_468: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x008 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x21d and fs3 == 0 and fe3 == 0x08 and fm3 == 0x225 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2c08; op2val:0x321d; +op3val:0x2225; valaddr_reg:x1; val_offset:1308*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1308*FLEN/8, x4, x2, x6) + +inst_469: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x008 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x21d and fs3 == 0 and fe3 == 0x08 and fm3 == 0x225 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2c08; op2val:0x321d; +op3val:0x2225; valaddr_reg:x1; val_offset:1311*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1311*FLEN/8, x4, x2, x6) + +inst_470: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x1c3 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x30d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x115 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x29c3; op2val:0x4b0d; +op3val:0x3915; valaddr_reg:x1; val_offset:1314*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1314*FLEN/8, x4, x2, x6) + +inst_471: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x1c3 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x30d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x115 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x29c3; op2val:0x4b0d; +op3val:0x3915; valaddr_reg:x1; val_offset:1317*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1317*FLEN/8, x4, x2, x6) + +inst_472: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x1c3 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x30d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x115 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x29c3; op2val:0x4b0d; +op3val:0x3915; valaddr_reg:x1; val_offset:1320*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1320*FLEN/8, x4, x2, x6) + +inst_473: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x1c3 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x30d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x115 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x29c3; op2val:0x4b0d; +op3val:0x3915; valaddr_reg:x1; val_offset:1323*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1323*FLEN/8, x4, x2, x6) + +inst_474: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x1c3 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x30d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x115 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x29c3; op2val:0x4b0d; +op3val:0x3915; valaddr_reg:x1; val_offset:1326*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1326*FLEN/8, x4, x2, x6) + +inst_475: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3ef and fs3 == 0 and fe3 == 0x0e and fm3 == 0x22f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a3c; op2val:0x3bef; +op3val:0x3a2f; valaddr_reg:x1; val_offset:1329*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1329*FLEN/8, x4, x2, x6) + +inst_476: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3ef and fs3 == 0 and fe3 == 0x0e and fm3 == 0x22f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a3c; op2val:0x3bef; +op3val:0x3a2f; valaddr_reg:x1; val_offset:1332*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1332*FLEN/8, x4, x2, x6) + +inst_477: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3ef and fs3 == 0 and fe3 == 0x0e and fm3 == 0x22f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a3c; op2val:0x3bef; +op3val:0x3a2f; valaddr_reg:x1; val_offset:1335*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1335*FLEN/8, x4, x2, x6) + +inst_478: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3ef and fs3 == 0 and fe3 == 0x0e and fm3 == 0x22f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a3c; op2val:0x3bef; +op3val:0x3a2f; valaddr_reg:x1; val_offset:1338*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1338*FLEN/8, x4, x2, x6) + +inst_479: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3ef and fs3 == 0 and fe3 == 0x0e and fm3 == 0x22f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a3c; op2val:0x3bef; +op3val:0x3a2f; valaddr_reg:x1; val_offset:1341*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1341*FLEN/8, x4, x2, x6) + +inst_480: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x26d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3ec and fs3 == 0 and fe3 == 0x0e and fm3 == 0x25d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a6d; op2val:0x3bec; +op3val:0x3a5d; valaddr_reg:x1; val_offset:1344*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1344*FLEN/8, x4, x2, x6) + +inst_481: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x26d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3ec and fs3 == 0 and fe3 == 0x0e and fm3 == 0x25d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a6d; op2val:0x3bec; +op3val:0x3a5d; valaddr_reg:x1; val_offset:1347*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1347*FLEN/8, x4, x2, x6) + +inst_482: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x26d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3ec and fs3 == 0 and fe3 == 0x0e and fm3 == 0x25d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a6d; op2val:0x3bec; +op3val:0x3a5d; valaddr_reg:x1; val_offset:1350*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1350*FLEN/8, x4, x2, x6) + +inst_483: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x26d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3ec and fs3 == 0 and fe3 == 0x0e and fm3 == 0x25d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a6d; op2val:0x3bec; +op3val:0x3a5d; valaddr_reg:x1; val_offset:1353*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1353*FLEN/8, x4, x2, x6) + +inst_484: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x26d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3ec and fs3 == 0 and fe3 == 0x0e and fm3 == 0x25d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a6d; op2val:0x3bec; +op3val:0x3a5d; valaddr_reg:x1; val_offset:1356*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1356*FLEN/8, x4, x2, x6) + +inst_485: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x203 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x03e and fs3 == 0 and fe3 == 0x0b and fm3 == 0x261 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3603; op2val:0x343e; +op3val:0x2e61; valaddr_reg:x1; val_offset:1359*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1359*FLEN/8, x4, x2, x6) + +inst_486: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x203 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x03e and fs3 == 0 and fe3 == 0x0b and fm3 == 0x261 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3603; op2val:0x343e; +op3val:0x2e61; valaddr_reg:x1; val_offset:1362*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1362*FLEN/8, x4, x2, x6) + +inst_487: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x203 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x03e and fs3 == 0 and fe3 == 0x0b and fm3 == 0x261 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3603; op2val:0x343e; +op3val:0x2e61; valaddr_reg:x1; val_offset:1365*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1365*FLEN/8, x4, x2, x6) + +inst_488: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x203 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x03e and fs3 == 0 and fe3 == 0x0b and fm3 == 0x261 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3603; op2val:0x343e; +op3val:0x2e61; valaddr_reg:x1; val_offset:1368*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1368*FLEN/8, x4, x2, x6) + +inst_489: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x203 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x03e and fs3 == 0 and fe3 == 0x0b and fm3 == 0x261 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3603; op2val:0x343e; +op3val:0x2e61; valaddr_reg:x1; val_offset:1371*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1371*FLEN/8, x4, x2, x6) + +inst_490: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x11b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x286 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x02a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x311b; op2val:0x4286; +op3val:0x382a; valaddr_reg:x1; val_offset:1374*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1374*FLEN/8, x4, x2, x6) + +inst_491: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x11b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x286 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x02a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x311b; op2val:0x4286; +op3val:0x382a; valaddr_reg:x1; val_offset:1377*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1377*FLEN/8, x4, x2, x6) + +inst_492: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x11b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x286 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x02a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x311b; op2val:0x4286; +op3val:0x382a; valaddr_reg:x1; val_offset:1380*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1380*FLEN/8, x4, x2, x6) + +inst_493: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x11b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x286 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x02a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x311b; op2val:0x4286; +op3val:0x382a; valaddr_reg:x1; val_offset:1383*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1383*FLEN/8, x4, x2, x6) + +inst_494: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x11b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x286 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x02a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x311b; op2val:0x4286; +op3val:0x382a; valaddr_reg:x1; val_offset:1386*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1386*FLEN/8, x4, x2, x6) + +inst_495: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x18d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x09e and fs3 == 0 and fe3 == 0x0c and fm3 == 0x269 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x358d; op2val:0x389e; +op3val:0x3269; valaddr_reg:x1; val_offset:1389*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1389*FLEN/8, x4, x2, x6) + +inst_496: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x18d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x09e and fs3 == 0 and fe3 == 0x0c and fm3 == 0x269 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x358d; op2val:0x389e; +op3val:0x3269; valaddr_reg:x1; val_offset:1392*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1392*FLEN/8, x4, x2, x6) + +inst_497: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x18d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x09e and fs3 == 0 and fe3 == 0x0c and fm3 == 0x269 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x358d; op2val:0x389e; +op3val:0x3269; valaddr_reg:x1; val_offset:1395*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1395*FLEN/8, x4, x2, x6) + +inst_498: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x18d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x09e and fs3 == 0 and fe3 == 0x0c and fm3 == 0x269 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x358d; op2val:0x389e; +op3val:0x3269; valaddr_reg:x1; val_offset:1398*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1398*FLEN/8, x4, x2, x6) + +inst_499: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x18d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x09e and fs3 == 0 and fe3 == 0x0c and fm3 == 0x269 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x358d; op2val:0x389e; +op3val:0x3269; valaddr_reg:x1; val_offset:1401*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1401*FLEN/8, x4, x2, x6) + +inst_500: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x352 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1ef and fs3 == 0 and fe3 == 0x0d and fm3 == 0x16e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b52; op2val:0x35ef; +op3val:0x356e; valaddr_reg:x1; val_offset:1404*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1404*FLEN/8, x4, x2, x6) + +inst_501: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x352 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1ef and fs3 == 0 and fe3 == 0x0d and fm3 == 0x16e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b52; op2val:0x35ef; +op3val:0x356e; valaddr_reg:x1; val_offset:1407*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1407*FLEN/8, x4, x2, x6) + +inst_502: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x352 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1ef and fs3 == 0 and fe3 == 0x0d and fm3 == 0x16e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b52; op2val:0x35ef; +op3val:0x356e; valaddr_reg:x1; val_offset:1410*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1410*FLEN/8, x4, x2, x6) + +inst_503: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x352 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1ef and fs3 == 0 and fe3 == 0x0d and fm3 == 0x16e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b52; op2val:0x35ef; +op3val:0x356e; valaddr_reg:x1; val_offset:1413*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1413*FLEN/8, x4, x2, x6) + +inst_504: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x352 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1ef and fs3 == 0 and fe3 == 0x0d and fm3 == 0x16e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b52; op2val:0x35ef; +op3val:0x356e; valaddr_reg:x1; val_offset:1416*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1416*FLEN/8, x4, x2, x6) + +inst_505: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1c6 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0d3 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2f7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2dc6; op2val:0x40d3; +op3val:0x32f7; valaddr_reg:x1; val_offset:1419*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1419*FLEN/8, x4, x2, x6) + +inst_506: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1c6 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0d3 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2f7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2dc6; op2val:0x40d3; +op3val:0x32f7; valaddr_reg:x1; val_offset:1422*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1422*FLEN/8, x4, x2, x6) + +inst_507: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1c6 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0d3 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2f7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2dc6; op2val:0x40d3; +op3val:0x32f7; valaddr_reg:x1; val_offset:1425*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1425*FLEN/8, x4, x2, x6) + +inst_508: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1c6 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0d3 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2f7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2dc6; op2val:0x40d3; +op3val:0x32f7; valaddr_reg:x1; val_offset:1428*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1428*FLEN/8, x4, x2, x6) + +inst_509: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1c6 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0d3 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2f7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2dc6; op2val:0x40d3; +op3val:0x32f7; valaddr_reg:x1; val_offset:1431*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1431*FLEN/8, x4, x2, x6) + +inst_510: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x10 and fm2 == 0x02d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x02d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x33ff; op2val:0x402d; +op3val:0x382d; valaddr_reg:x1; val_offset:1434*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1434*FLEN/8, x4, x2, x6) + +inst_511: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x10 and fm2 == 0x02d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x02d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x33ff; op2val:0x402d; +op3val:0x382d; valaddr_reg:x1; val_offset:1437*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1437*FLEN/8, x4, x2, x6) + +inst_512: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x10 and fm2 == 0x02d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x02d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x33ff; op2val:0x402d; +op3val:0x382d; valaddr_reg:x1; val_offset:1440*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1440*FLEN/8, x4, x2, x6) + +inst_513: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x10 and fm2 == 0x02d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x02d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x33ff; op2val:0x402d; +op3val:0x382d; valaddr_reg:x1; val_offset:1443*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1443*FLEN/8, x4, x2, x6) + +inst_514: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x10 and fm2 == 0x02d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x02d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x33ff; op2val:0x402d; +op3val:0x382d; valaddr_reg:x1; val_offset:1446*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1446*FLEN/8, x4, x2, x6) + +inst_515: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x292 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x01b and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2bf and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a92; op2val:0x341b; +op3val:0x32bf; valaddr_reg:x1; val_offset:1449*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1449*FLEN/8, x4, x2, x6) + +inst_516: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x292 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x01b and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2bf and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a92; op2val:0x341b; +op3val:0x32bf; valaddr_reg:x1; val_offset:1452*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1452*FLEN/8, x4, x2, x6) + +inst_517: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x292 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x01b and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2bf and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a92; op2val:0x341b; +op3val:0x32bf; valaddr_reg:x1; val_offset:1455*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1455*FLEN/8, x4, x2, x6) + +inst_518: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x292 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x01b and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2bf and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a92; op2val:0x341b; +op3val:0x32bf; valaddr_reg:x1; val_offset:1458*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1458*FLEN/8, x4, x2, x6) + +inst_519: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x292 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x01b and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2bf and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a92; op2val:0x341b; +op3val:0x32bf; valaddr_reg:x1; val_offset:1461*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1461*FLEN/8, x4, x2, x6) + +inst_520: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x157 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0c6 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x25f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3957; op2val:0x34c6; +op3val:0x325f; valaddr_reg:x1; val_offset:1464*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1464*FLEN/8, x4, x2, x6) + +inst_521: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x157 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0c6 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x25f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3957; op2val:0x34c6; +op3val:0x325f; valaddr_reg:x1; val_offset:1467*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1467*FLEN/8, x4, x2, x6) + +inst_522: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x157 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0c6 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x25f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3957; op2val:0x34c6; +op3val:0x325f; valaddr_reg:x1; val_offset:1470*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1470*FLEN/8, x4, x2, x6) + +inst_523: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x157 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0c6 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x25f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3957; op2val:0x34c6; +op3val:0x325f; valaddr_reg:x1; val_offset:1473*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1473*FLEN/8, x4, x2, x6) + +inst_524: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x157 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0c6 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x25f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3957; op2val:0x34c6; +op3val:0x325f; valaddr_reg:x1; val_offset:1476*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1476*FLEN/8, x4, x2, x6) + +inst_525: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x344 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x152 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0d5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2744; op2val:0x4d52; +op3val:0x38d5; valaddr_reg:x1; val_offset:1479*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1479*FLEN/8, x4, x2, x6) + +inst_526: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x344 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x152 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0d5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2744; op2val:0x4d52; +op3val:0x38d5; valaddr_reg:x1; val_offset:1482*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1482*FLEN/8, x4, x2, x6) + +inst_527: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x344 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x152 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0d5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2744; op2val:0x4d52; +op3val:0x38d5; valaddr_reg:x1; val_offset:1485*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1485*FLEN/8, x4, x2, x6) + +inst_528: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x344 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x152 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0d5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2744; op2val:0x4d52; +op3val:0x38d5; valaddr_reg:x1; val_offset:1488*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1488*FLEN/8, x4, x2, x6) + +inst_529: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x344 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x152 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0d5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2744; op2val:0x4d52; +op3val:0x38d5; valaddr_reg:x1; val_offset:1491*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1491*FLEN/8, x4, x2, x6) + +inst_530: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0c9 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x1b2 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x2d0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38c9; op2val:0x2db2; +op3val:0x2ad0; valaddr_reg:x1; val_offset:1494*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1494*FLEN/8, x4, x2, x6) + +inst_531: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0c9 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x1b2 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x2d0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38c9; op2val:0x2db2; +op3val:0x2ad0; valaddr_reg:x1; val_offset:1497*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1497*FLEN/8, x4, x2, x6) + +inst_532: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0c9 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x1b2 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x2d0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38c9; op2val:0x2db2; +op3val:0x2ad0; valaddr_reg:x1; val_offset:1500*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1500*FLEN/8, x4, x2, x6) + +inst_533: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0c9 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x1b2 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x2d0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38c9; op2val:0x2db2; +op3val:0x2ad0; valaddr_reg:x1; val_offset:1503*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1503*FLEN/8, x4, x2, x6) + +inst_534: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0c9 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x1b2 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x2d0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38c9; op2val:0x2db2; +op3val:0x2ad0; valaddr_reg:x1; val_offset:1506*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1506*FLEN/8, x4, x2, x6) + +inst_535: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x067 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x208 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2a3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3467; op2val:0x4208; +op3val:0x3aa3; valaddr_reg:x1; val_offset:1509*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1509*FLEN/8, x4, x2, x6) + +inst_536: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x067 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x208 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2a3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3467; op2val:0x4208; +op3val:0x3aa3; valaddr_reg:x1; val_offset:1512*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1512*FLEN/8, x4, x2, x6) + +inst_537: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x067 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x208 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2a3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3467; op2val:0x4208; +op3val:0x3aa3; valaddr_reg:x1; val_offset:1515*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1515*FLEN/8, x4, x2, x6) + +inst_538: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x067 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x208 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2a3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3467; op2val:0x4208; +op3val:0x3aa3; valaddr_reg:x1; val_offset:1518*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1518*FLEN/8, x4, x2, x6) + +inst_539: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x067 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x208 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2a3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3467; op2val:0x4208; +op3val:0x3aa3; valaddr_reg:x1; val_offset:1521*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1521*FLEN/8, x4, x2, x6) +RVTEST_SIGBASE(x2,signature_x2_4) + +inst_540: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3c7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ca and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3afb; op2val:0x3bc7; +op3val:0x3aca; valaddr_reg:x1; val_offset:1524*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1524*FLEN/8, x4, x2, x6) + +inst_541: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3c7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ca and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3afb; op2val:0x3bc7; +op3val:0x3aca; valaddr_reg:x1; val_offset:1527*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1527*FLEN/8, x4, x2, x6) + +inst_542: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3c7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ca and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3afb; op2val:0x3bc7; +op3val:0x3aca; valaddr_reg:x1; val_offset:1530*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1530*FLEN/8, x4, x2, x6) + +inst_543: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3c7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ca and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3afb; op2val:0x3bc7; +op3val:0x3aca; valaddr_reg:x1; val_offset:1533*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1533*FLEN/8, x4, x2, x6) + +inst_544: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3c7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ca and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3afb; op2val:0x3bc7; +op3val:0x3aca; valaddr_reg:x1; val_offset:1536*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1536*FLEN/8, x4, x2, x6) + +inst_545: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x217 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x011 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x231 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e17; op2val:0x4011; +op3val:0x3231; valaddr_reg:x1; val_offset:1539*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1539*FLEN/8, x4, x2, x6) + +inst_546: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x217 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x011 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x231 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e17; op2val:0x4011; +op3val:0x3231; valaddr_reg:x1; val_offset:1542*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1542*FLEN/8, x4, x2, x6) + +inst_547: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x217 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x011 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x231 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e17; op2val:0x4011; +op3val:0x3231; valaddr_reg:x1; val_offset:1545*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1545*FLEN/8, x4, x2, x6) + +inst_548: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x217 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x011 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x231 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e17; op2val:0x4011; +op3val:0x3231; valaddr_reg:x1; val_offset:1548*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1548*FLEN/8, x4, x2, x6) + +inst_549: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x217 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x011 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x231 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e17; op2val:0x4011; +op3val:0x3231; valaddr_reg:x1; val_offset:1551*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1551*FLEN/8, x4, x2, x6) + +inst_550: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d4 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x281 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x18d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ad4; op2val:0x3281; +op3val:0x318d; valaddr_reg:x1; val_offset:1554*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1554*FLEN/8, x4, x2, x6) + +inst_551: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d4 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x281 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x18d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ad4; op2val:0x3281; +op3val:0x318d; valaddr_reg:x1; val_offset:1557*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1557*FLEN/8, x4, x2, x6) + +inst_552: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d4 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x281 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x18d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ad4; op2val:0x3281; +op3val:0x318d; valaddr_reg:x1; val_offset:1560*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1560*FLEN/8, x4, x2, x6) + +inst_553: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d4 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x281 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x18d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ad4; op2val:0x3281; +op3val:0x318d; valaddr_reg:x1; val_offset:1563*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1563*FLEN/8, x4, x2, x6) + +inst_554: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d4 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x281 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x18d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ad4; op2val:0x3281; +op3val:0x318d; valaddr_reg:x1; val_offset:1566*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1566*FLEN/8, x4, x2, x6) + +inst_555: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x10d and fs2 == 0 and fe2 == 0x13 and fm2 == 0x057 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x17b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x250d; op2val:0x4c57; +op3val:0x357b; valaddr_reg:x1; val_offset:1569*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1569*FLEN/8, x4, x2, x6) + +inst_556: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x10d and fs2 == 0 and fe2 == 0x13 and fm2 == 0x057 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x17b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x250d; op2val:0x4c57; +op3val:0x357b; valaddr_reg:x1; val_offset:1572*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1572*FLEN/8, x4, x2, x6) + +inst_557: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x10d and fs2 == 0 and fe2 == 0x13 and fm2 == 0x057 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x17b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x250d; op2val:0x4c57; +op3val:0x357b; valaddr_reg:x1; val_offset:1575*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1575*FLEN/8, x4, x2, x6) + +inst_558: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x10d and fs2 == 0 and fe2 == 0x13 and fm2 == 0x057 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x17b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x250d; op2val:0x4c57; +op3val:0x357b; valaddr_reg:x1; val_offset:1578*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1578*FLEN/8, x4, x2, x6) + +inst_559: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x10d and fs2 == 0 and fe2 == 0x13 and fm2 == 0x057 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x17b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x250d; op2val:0x4c57; +op3val:0x357b; valaddr_reg:x1; val_offset:1581*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1581*FLEN/8, x4, x2, x6) + +inst_560: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x132 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x18f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x338 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3932; op2val:0x398f; +op3val:0x3738; valaddr_reg:x1; val_offset:1584*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1584*FLEN/8, x4, x2, x6) + +inst_561: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x132 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x18f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x338 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3932; op2val:0x398f; +op3val:0x3738; valaddr_reg:x1; val_offset:1587*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1587*FLEN/8, x4, x2, x6) + +inst_562: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x132 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x18f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x338 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3932; op2val:0x398f; +op3val:0x3738; valaddr_reg:x1; val_offset:1590*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1590*FLEN/8, x4, x2, x6) + +inst_563: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x132 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x18f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x338 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3932; op2val:0x398f; +op3val:0x3738; valaddr_reg:x1; val_offset:1593*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1593*FLEN/8, x4, x2, x6) + +inst_564: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x132 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x18f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x338 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3932; op2val:0x398f; +op3val:0x3738; valaddr_reg:x1; val_offset:1596*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1596*FLEN/8, x4, x2, x6) + +inst_565: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2f3 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x089 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3e2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3af3; op2val:0x3c89; +op3val:0x3be2; valaddr_reg:x1; val_offset:1599*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1599*FLEN/8, x4, x2, x6) + +inst_566: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2f3 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x089 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3e2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3af3; op2val:0x3c89; +op3val:0x3be2; valaddr_reg:x1; val_offset:1602*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1602*FLEN/8, x4, x2, x6) + +inst_567: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2f3 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x089 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3e2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3af3; op2val:0x3c89; +op3val:0x3be2; valaddr_reg:x1; val_offset:1605*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1605*FLEN/8, x4, x2, x6) + +inst_568: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2f3 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x089 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3e2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3af3; op2val:0x3c89; +op3val:0x3be2; valaddr_reg:x1; val_offset:1608*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1608*FLEN/8, x4, x2, x6) + +inst_569: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2f3 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x089 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3e2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3af3; op2val:0x3c89; +op3val:0x3be2; valaddr_reg:x1; val_offset:1611*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1611*FLEN/8, x4, x2, x6) + +inst_570: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x376 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x202 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x19b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2776; op2val:0x4a02; +op3val:0x359b; valaddr_reg:x1; val_offset:1614*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1614*FLEN/8, x4, x2, x6) + +inst_571: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x376 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x202 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x19b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2776; op2val:0x4a02; +op3val:0x359b; valaddr_reg:x1; val_offset:1617*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1617*FLEN/8, x4, x2, x6) + +inst_572: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x376 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x202 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x19b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2776; op2val:0x4a02; +op3val:0x359b; valaddr_reg:x1; val_offset:1620*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1620*FLEN/8, x4, x2, x6) + +inst_573: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x376 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x202 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x19b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2776; op2val:0x4a02; +op3val:0x359b; valaddr_reg:x1; val_offset:1623*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1623*FLEN/8, x4, x2, x6) + +inst_574: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x376 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x202 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x19b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2776; op2val:0x4a02; +op3val:0x359b; valaddr_reg:x1; val_offset:1626*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1626*FLEN/8, x4, x2, x6) + +inst_575: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x393 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x07d and fs3 == 0 and fe3 == 0x0b and fm3 == 0x040 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3793; op2val:0x307d; +op3val:0x2c40; valaddr_reg:x1; val_offset:1629*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1629*FLEN/8, x4, x2, x6) + +inst_576: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x393 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x07d and fs3 == 0 and fe3 == 0x0b and fm3 == 0x040 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3793; op2val:0x307d; +op3val:0x2c40; valaddr_reg:x1; val_offset:1632*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1632*FLEN/8, x4, x2, x6) + +inst_577: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x393 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x07d and fs3 == 0 and fe3 == 0x0b and fm3 == 0x040 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3793; op2val:0x307d; +op3val:0x2c40; valaddr_reg:x1; val_offset:1635*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1635*FLEN/8, x4, x2, x6) + +inst_578: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x393 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x07d and fs3 == 0 and fe3 == 0x0b and fm3 == 0x040 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3793; op2val:0x307d; +op3val:0x2c40; valaddr_reg:x1; val_offset:1638*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1638*FLEN/8, x4, x2, x6) + +inst_579: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x393 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x07d and fs3 == 0 and fe3 == 0x0b and fm3 == 0x040 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3793; op2val:0x307d; +op3val:0x2c40; valaddr_reg:x1; val_offset:1641*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1641*FLEN/8, x4, x2, x6) + +inst_580: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x087 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x340 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x01a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3887; op2val:0x3340; +op3val:0x301a; valaddr_reg:x1; val_offset:1644*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1644*FLEN/8, x4, x2, x6) + +inst_581: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x087 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x340 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x01a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3887; op2val:0x3340; +op3val:0x301a; valaddr_reg:x1; val_offset:1647*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1647*FLEN/8, x4, x2, x6) + +inst_582: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x087 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x340 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x01a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3887; op2val:0x3340; +op3val:0x301a; valaddr_reg:x1; val_offset:1650*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1650*FLEN/8, x4, x2, x6) + +inst_583: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x087 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x340 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x01a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3887; op2val:0x3340; +op3val:0x301a; valaddr_reg:x1; val_offset:1653*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1653*FLEN/8, x4, x2, x6) + +inst_584: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x087 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x340 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x01a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3887; op2val:0x3340; +op3val:0x301a; valaddr_reg:x1; val_offset:1656*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1656*FLEN/8, x4, x2, x6) + +inst_585: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x190 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x089 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x24f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3190; op2val:0x4489; +op3val:0x3a4f; valaddr_reg:x1; val_offset:1659*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1659*FLEN/8, x4, x2, x6) + +inst_586: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x190 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x089 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x24f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3190; op2val:0x4489; +op3val:0x3a4f; valaddr_reg:x1; val_offset:1662*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1662*FLEN/8, x4, x2, x6) + +inst_587: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x190 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x089 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x24f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3190; op2val:0x4489; +op3val:0x3a4f; valaddr_reg:x1; val_offset:1665*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1665*FLEN/8, x4, x2, x6) + +inst_588: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x190 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x089 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x24f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3190; op2val:0x4489; +op3val:0x3a4f; valaddr_reg:x1; val_offset:1668*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1668*FLEN/8, x4, x2, x6) + +inst_589: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x190 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x089 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x24f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3190; op2val:0x4489; +op3val:0x3a4f; valaddr_reg:x1; val_offset:1671*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1671*FLEN/8, x4, x2, x6) + +inst_590: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fc and fs2 == 0 and fe2 == 0x0e and fm2 == 0x38f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39fc; op2val:0x3b8f; +op3val:0x39a8; valaddr_reg:x1; val_offset:1674*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1674*FLEN/8, x4, x2, x6) + +inst_591: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fc and fs2 == 0 and fe2 == 0x0e and fm2 == 0x38f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39fc; op2val:0x3b8f; +op3val:0x39a8; valaddr_reg:x1; val_offset:1677*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1677*FLEN/8, x4, x2, x6) + +inst_592: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fc and fs2 == 0 and fe2 == 0x0e and fm2 == 0x38f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39fc; op2val:0x3b8f; +op3val:0x39a8; valaddr_reg:x1; val_offset:1680*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1680*FLEN/8, x4, x2, x6) + +inst_593: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fc and fs2 == 0 and fe2 == 0x0e and fm2 == 0x38f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39fc; op2val:0x3b8f; +op3val:0x39a8; valaddr_reg:x1; val_offset:1683*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1683*FLEN/8, x4, x2, x6) + +inst_594: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fc and fs2 == 0 and fe2 == 0x0e and fm2 == 0x38f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39fc; op2val:0x3b8f; +op3val:0x39a8; valaddr_reg:x1; val_offset:1686*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1686*FLEN/8, x4, x2, x6) + +inst_595: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x213 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x05b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x29e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a13; op2val:0x385b; +op3val:0x369e; valaddr_reg:x1; val_offset:1689*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1689*FLEN/8, x4, x2, x6) + +inst_596: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x213 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x05b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x29e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a13; op2val:0x385b; +op3val:0x369e; valaddr_reg:x1; val_offset:1692*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1692*FLEN/8, x4, x2, x6) + +inst_597: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x213 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x05b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x29e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a13; op2val:0x385b; +op3val:0x369e; valaddr_reg:x1; val_offset:1695*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1695*FLEN/8, x4, x2, x6) + +inst_598: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x213 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x05b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x29e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a13; op2val:0x385b; +op3val:0x369e; valaddr_reg:x1; val_offset:1698*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1698*FLEN/8, x4, x2, x6) + +inst_599: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x213 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x05b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x29e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a13; op2val:0x385b; +op3val:0x369e; valaddr_reg:x1; val_offset:1701*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1701*FLEN/8, x4, x2, x6) + +inst_600: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ec and fs2 == 0 and fe2 == 0x0e and fm2 == 0x246 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0a5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39ec; op2val:0x3a46; +op3val:0x38a5; valaddr_reg:x1; val_offset:1704*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1704*FLEN/8, x4, x2, x6) + +inst_601: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ec and fs2 == 0 and fe2 == 0x0e and fm2 == 0x246 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0a5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39ec; op2val:0x3a46; +op3val:0x38a5; valaddr_reg:x1; val_offset:1707*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1707*FLEN/8, x4, x2, x6) + +inst_602: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ec and fs2 == 0 and fe2 == 0x0e and fm2 == 0x246 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0a5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39ec; op2val:0x3a46; +op3val:0x38a5; valaddr_reg:x1; val_offset:1710*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1710*FLEN/8, x4, x2, x6) + +inst_603: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ec and fs2 == 0 and fe2 == 0x0e and fm2 == 0x246 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0a5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39ec; op2val:0x3a46; +op3val:0x38a5; valaddr_reg:x1; val_offset:1713*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1713*FLEN/8, x4, x2, x6) + +inst_604: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ec and fs2 == 0 and fe2 == 0x0e and fm2 == 0x246 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0a5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39ec; op2val:0x3a46; +op3val:0x38a5; valaddr_reg:x1; val_offset:1716*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1716*FLEN/8, x4, x2, x6) + +inst_605: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2f3 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2a2 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1c2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3af3; op2val:0x2ea2; +op3val:0x2dc2; valaddr_reg:x1; val_offset:1719*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1719*FLEN/8, x4, x2, x6) + +inst_606: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2f3 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2a2 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1c2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3af3; op2val:0x2ea2; +op3val:0x2dc2; valaddr_reg:x1; val_offset:1722*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1722*FLEN/8, x4, x2, x6) + +inst_607: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2f3 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2a2 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1c2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3af3; op2val:0x2ea2; +op3val:0x2dc2; valaddr_reg:x1; val_offset:1725*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1725*FLEN/8, x4, x2, x6) + +inst_608: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2f3 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2a2 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1c2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3af3; op2val:0x2ea2; +op3val:0x2dc2; valaddr_reg:x1; val_offset:1728*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1728*FLEN/8, x4, x2, x6) + +inst_609: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2f3 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2a2 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1c2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3af3; op2val:0x2ea2; +op3val:0x2dc2; valaddr_reg:x1; val_offset:1731*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1731*FLEN/8, x4, x2, x6) + +inst_610: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x12b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2b5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x392b; op2val:0x3ab5; +op3val:0x3855; valaddr_reg:x1; val_offset:1734*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1734*FLEN/8, x4, x2, x6) + +inst_611: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x12b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2b5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x055 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x392b; op2val:0x3ab5; +op3val:0x3855; valaddr_reg:x1; val_offset:1737*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1737*FLEN/8, x4, x2, x6) + +inst_612: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x12b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2b5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x055 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x392b; op2val:0x3ab5; +op3val:0x3855; valaddr_reg:x1; val_offset:1740*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1740*FLEN/8, x4, x2, x6) + +inst_613: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x12b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2b5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x055 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x392b; op2val:0x3ab5; +op3val:0x3855; valaddr_reg:x1; val_offset:1743*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1743*FLEN/8, x4, x2, x6) + +inst_614: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x12b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2b5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x055 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x392b; op2val:0x3ab5; +op3val:0x3855; valaddr_reg:x1; val_offset:1746*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1746*FLEN/8, x4, x2, x6) + +inst_615: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2aa and fs2 == 0 and fe2 == 0x0c and fm2 == 0x35b and fs3 == 0 and fe3 == 0x0b and fm3 == 0x220 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36aa; op2val:0x335b; +op3val:0x2e20; valaddr_reg:x1; val_offset:1749*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1749*FLEN/8, x4, x2, x6) + +inst_616: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2aa and fs2 == 0 and fe2 == 0x0c and fm2 == 0x35b and fs3 == 0 and fe3 == 0x0b and fm3 == 0x220 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36aa; op2val:0x335b; +op3val:0x2e20; valaddr_reg:x1; val_offset:1752*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1752*FLEN/8, x4, x2, x6) + +inst_617: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2aa and fs2 == 0 and fe2 == 0x0c and fm2 == 0x35b and fs3 == 0 and fe3 == 0x0b and fm3 == 0x220 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36aa; op2val:0x335b; +op3val:0x2e20; valaddr_reg:x1; val_offset:1755*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1755*FLEN/8, x4, x2, x6) + +inst_618: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2aa and fs2 == 0 and fe2 == 0x0c and fm2 == 0x35b and fs3 == 0 and fe3 == 0x0b and fm3 == 0x220 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36aa; op2val:0x335b; +op3val:0x2e20; valaddr_reg:x1; val_offset:1758*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1758*FLEN/8, x4, x2, x6) + +inst_619: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2aa and fs2 == 0 and fe2 == 0x0c and fm2 == 0x35b and fs3 == 0 and fe3 == 0x0b and fm3 == 0x220 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36aa; op2val:0x335b; +op3val:0x2e20; valaddr_reg:x1; val_offset:1761*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1761*FLEN/8, x4, x2, x6) + +inst_620: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0a2 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x08c and fs3 == 0 and fe3 == 0x0b and fm3 == 0x144 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38a2; op2val:0x308c; +op3val:0x2d44; valaddr_reg:x1; val_offset:1764*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1764*FLEN/8, x4, x2, x6) + +inst_621: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0a2 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x08c and fs3 == 0 and fe3 == 0x0b and fm3 == 0x144 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38a2; op2val:0x308c; +op3val:0x2d44; valaddr_reg:x1; val_offset:1767*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1767*FLEN/8, x4, x2, x6) + +inst_622: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0a2 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x08c and fs3 == 0 and fe3 == 0x0b and fm3 == 0x144 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38a2; op2val:0x308c; +op3val:0x2d44; valaddr_reg:x1; val_offset:1770*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1770*FLEN/8, x4, x2, x6) + +inst_623: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0a2 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x08c and fs3 == 0 and fe3 == 0x0b and fm3 == 0x144 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38a2; op2val:0x308c; +op3val:0x2d44; valaddr_reg:x1; val_offset:1773*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1773*FLEN/8, x4, x2, x6) + +inst_624: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0a2 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x08c and fs3 == 0 and fe3 == 0x0b and fm3 == 0x144 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38a2; op2val:0x308c; +op3val:0x2d44; valaddr_reg:x1; val_offset:1776*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1776*FLEN/8, x4, x2, x6) + +inst_625: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3f9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x384 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x37d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37f9; op2val:0x3b84; +op3val:0x377d; valaddr_reg:x1; val_offset:1779*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1779*FLEN/8, x4, x2, x6) + +inst_626: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3f9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x384 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x37d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37f9; op2val:0x3b84; +op3val:0x377d; valaddr_reg:x1; val_offset:1782*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1782*FLEN/8, x4, x2, x6) + +inst_627: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3f9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x384 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x37d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37f9; op2val:0x3b84; +op3val:0x377d; valaddr_reg:x1; val_offset:1785*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1785*FLEN/8, x4, x2, x6) + +inst_628: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3f9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x384 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x37d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37f9; op2val:0x3b84; +op3val:0x377d; valaddr_reg:x1; val_offset:1788*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1788*FLEN/8, x4, x2, x6) + +inst_629: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3f9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x384 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x37d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37f9; op2val:0x3b84; +op3val:0x377d; valaddr_reg:x1; val_offset:1791*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1791*FLEN/8, x4, x2, x6) + +inst_630: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x39f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x01e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3d9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x379f; op2val:0x401e; +op3val:0x3bd9; valaddr_reg:x1; val_offset:1794*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1794*FLEN/8, x4, x2, x6) + +inst_631: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x39f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x01e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3d9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x379f; op2val:0x401e; +op3val:0x3bd9; valaddr_reg:x1; val_offset:1797*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1797*FLEN/8, x4, x2, x6) + +inst_632: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x39f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x01e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3d9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x379f; op2val:0x401e; +op3val:0x3bd9; valaddr_reg:x1; val_offset:1800*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1800*FLEN/8, x4, x2, x6) + +inst_633: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x39f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x01e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3d9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x379f; op2val:0x401e; +op3val:0x3bd9; valaddr_reg:x1; val_offset:1803*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1803*FLEN/8, x4, x2, x6) + +inst_634: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x39f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x01e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3d9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x379f; op2val:0x401e; +op3val:0x3bd9; valaddr_reg:x1; val_offset:1806*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1806*FLEN/8, x4, x2, x6) + +inst_635: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x07a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1d6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x289 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x387a; op2val:0x3dd6; +op3val:0x3a89; valaddr_reg:x1; val_offset:1809*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1809*FLEN/8, x4, x2, x6) + +inst_636: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x07a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1d6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x289 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x387a; op2val:0x3dd6; +op3val:0x3a89; valaddr_reg:x1; val_offset:1812*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1812*FLEN/8, x4, x2, x6) + +inst_637: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x07a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1d6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x289 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x387a; op2val:0x3dd6; +op3val:0x3a89; valaddr_reg:x1; val_offset:1815*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1815*FLEN/8, x4, x2, x6) + +inst_638: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x07a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1d6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x289 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x387a; op2val:0x3dd6; +op3val:0x3a89; valaddr_reg:x1; val_offset:1818*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1818*FLEN/8, x4, x2, x6) + +inst_639: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x07a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1d6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x289 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x387a; op2val:0x3dd6; +op3val:0x3a89; valaddr_reg:x1; val_offset:1821*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1821*FLEN/8, x4, x2, x6) + +inst_640: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f7 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x274 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x26d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bf7; op2val:0x3274; +op3val:0x326d; valaddr_reg:x1; val_offset:1824*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1824*FLEN/8, x4, x2, x6) + +inst_641: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f7 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x274 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x26d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bf7; op2val:0x3274; +op3val:0x326d; valaddr_reg:x1; val_offset:1827*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1827*FLEN/8, x4, x2, x6) + +inst_642: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f7 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x274 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x26d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bf7; op2val:0x3274; +op3val:0x326d; valaddr_reg:x1; val_offset:1830*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1830*FLEN/8, x4, x2, x6) + +inst_643: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f7 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x274 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x26d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bf7; op2val:0x3274; +op3val:0x326d; valaddr_reg:x1; val_offset:1833*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1833*FLEN/8, x4, x2, x6) + +inst_644: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f7 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x274 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x26d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bf7; op2val:0x3274; +op3val:0x326d; valaddr_reg:x1; val_offset:1836*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1836*FLEN/8, x4, x2, x6) + +inst_645: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x29f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x117 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x036 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a9f; op2val:0x3917; +op3val:0x3836; valaddr_reg:x1; val_offset:1839*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1839*FLEN/8, x4, x2, x6) + +inst_646: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x29f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x117 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x036 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a9f; op2val:0x3917; +op3val:0x3836; valaddr_reg:x1; val_offset:1842*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1842*FLEN/8, x4, x2, x6) + +inst_647: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x29f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x117 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x036 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a9f; op2val:0x3917; +op3val:0x3836; valaddr_reg:x1; val_offset:1845*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1845*FLEN/8, x4, x2, x6) + +inst_648: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x29f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x117 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x036 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a9f; op2val:0x3917; +op3val:0x3836; valaddr_reg:x1; val_offset:1848*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1848*FLEN/8, x4, x2, x6) + +inst_649: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x29f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x117 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x036 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a9f; op2val:0x3917; +op3val:0x3836; valaddr_reg:x1; val_offset:1851*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1851*FLEN/8, x4, x2, x6) + +inst_650: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x065 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x274 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x318 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3465; op2val:0x3e74; +op3val:0x3718; valaddr_reg:x1; val_offset:1854*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1854*FLEN/8, x4, x2, x6) + +inst_651: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x065 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x274 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x318 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3465; op2val:0x3e74; +op3val:0x3718; valaddr_reg:x1; val_offset:1857*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1857*FLEN/8, x4, x2, x6) + +inst_652: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x065 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x274 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x318 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3465; op2val:0x3e74; +op3val:0x3718; valaddr_reg:x1; val_offset:1860*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1860*FLEN/8, x4, x2, x6) + +inst_653: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x065 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x274 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x318 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3465; op2val:0x3e74; +op3val:0x3718; valaddr_reg:x1; val_offset:1863*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1863*FLEN/8, x4, x2, x6) + +inst_654: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x065 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x274 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x318 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3465; op2val:0x3e74; +op3val:0x3718; valaddr_reg:x1; val_offset:1866*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1866*FLEN/8, x4, x2, x6) + +inst_655: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x164 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1b7 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3b4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3964; op2val:0x39b7; +op3val:0x37b4; valaddr_reg:x1; val_offset:1869*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1869*FLEN/8, x4, x2, x6) + +inst_656: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x164 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1b7 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3b4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3964; op2val:0x39b7; +op3val:0x37b4; valaddr_reg:x1; val_offset:1872*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1872*FLEN/8, x4, x2, x6) + +inst_657: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x164 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1b7 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3b4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3964; op2val:0x39b7; +op3val:0x37b4; valaddr_reg:x1; val_offset:1875*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1875*FLEN/8, x4, x2, x6) + +inst_658: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x164 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1b7 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3b4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3964; op2val:0x39b7; +op3val:0x37b4; valaddr_reg:x1; val_offset:1878*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1878*FLEN/8, x4, x2, x6) + +inst_659: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x164 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1b7 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3b4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3964; op2val:0x39b7; +op3val:0x37b4; valaddr_reg:x1; val_offset:1881*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1881*FLEN/8, x4, x2, x6) + +inst_660: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x31d and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3c4 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2e7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x371d; op2val:0x37c4; +op3val:0x32e7; valaddr_reg:x1; val_offset:1884*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1884*FLEN/8, x4, x2, x6) + +inst_661: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x31d and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3c4 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2e7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x371d; op2val:0x37c4; +op3val:0x32e7; valaddr_reg:x1; val_offset:1887*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1887*FLEN/8, x4, x2, x6) + +inst_662: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x31d and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3c4 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2e7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x371d; op2val:0x37c4; +op3val:0x32e7; valaddr_reg:x1; val_offset:1890*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1890*FLEN/8, x4, x2, x6) + +inst_663: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x31d and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3c4 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2e7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x371d; op2val:0x37c4; +op3val:0x32e7; valaddr_reg:x1; val_offset:1893*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1893*FLEN/8, x4, x2, x6) + +inst_664: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x31d and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3c4 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2e7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x371d; op2val:0x37c4; +op3val:0x32e7; valaddr_reg:x1; val_offset:1896*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1896*FLEN/8, x4, x2, x6) + +inst_665: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x326 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3df and fs3 == 0 and fe3 == 0x0d and fm3 == 0x309 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b26; op2val:0x37df; +op3val:0x3709; valaddr_reg:x1; val_offset:1899*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1899*FLEN/8, x4, x2, x6) + +inst_666: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x326 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3df and fs3 == 0 and fe3 == 0x0d and fm3 == 0x309 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b26; op2val:0x37df; +op3val:0x3709; valaddr_reg:x1; val_offset:1902*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1902*FLEN/8, x4, x2, x6) + +inst_667: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x326 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3df and fs3 == 0 and fe3 == 0x0d and fm3 == 0x309 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b26; op2val:0x37df; +op3val:0x3709; valaddr_reg:x1; val_offset:1905*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1905*FLEN/8, x4, x2, x6) +RVTEST_SIGBASE(x2,signature_x2_5) + +inst_668: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x326 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3df and fs3 == 0 and fe3 == 0x0d and fm3 == 0x309 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b26; op2val:0x37df; +op3val:0x3709; valaddr_reg:x1; val_offset:1908*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1908*FLEN/8, x4, x2, x6) + +inst_669: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x326 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3df and fs3 == 0 and fe3 == 0x0d and fm3 == 0x309 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b26; op2val:0x37df; +op3val:0x3709; valaddr_reg:x1; val_offset:1911*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1911*FLEN/8, x4, x2, x6) + +inst_670: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x203 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3b2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1c8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a03; op2val:0x3bb2; +op3val:0x39c8; valaddr_reg:x1; val_offset:1914*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1914*FLEN/8, x4, x2, x6) + +inst_671: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x203 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3b2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1c8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a03; op2val:0x3bb2; +op3val:0x39c8; valaddr_reg:x1; val_offset:1917*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1917*FLEN/8, x4, x2, x6) + +inst_672: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x203 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3b2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1c8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a03; op2val:0x3bb2; +op3val:0x39c8; valaddr_reg:x1; val_offset:1920*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1920*FLEN/8, x4, x2, x6) + +inst_673: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x203 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3b2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1c8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a03; op2val:0x3bb2; +op3val:0x39c8; valaddr_reg:x1; val_offset:1923*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1923*FLEN/8, x4, x2, x6) + +inst_674: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x203 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3b2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1c8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a03; op2val:0x3bb2; +op3val:0x39c8; valaddr_reg:x1; val_offset:1926*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1926*FLEN/8, x4, x2, x6) + +inst_675: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x34a and fs2 == 0 and fe2 == 0x10 and fm2 == 0x052 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x334a; op2val:0x4052; +op3val:0x37e0; valaddr_reg:x1; val_offset:1929*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1929*FLEN/8, x4, x2, x6) + +inst_676: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x34a and fs2 == 0 and fe2 == 0x10 and fm2 == 0x052 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3e0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x334a; op2val:0x4052; +op3val:0x37e0; valaddr_reg:x1; val_offset:1932*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1932*FLEN/8, x4, x2, x6) + +inst_677: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x34a and fs2 == 0 and fe2 == 0x10 and fm2 == 0x052 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3e0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x334a; op2val:0x4052; +op3val:0x37e0; valaddr_reg:x1; val_offset:1935*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1935*FLEN/8, x4, x2, x6) + +inst_678: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x34a and fs2 == 0 and fe2 == 0x10 and fm2 == 0x052 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3e0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x334a; op2val:0x4052; +op3val:0x37e0; valaddr_reg:x1; val_offset:1938*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1938*FLEN/8, x4, x2, x6) + +inst_679: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x34a and fs2 == 0 and fe2 == 0x10 and fm2 == 0x052 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3e0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x334a; op2val:0x4052; +op3val:0x37e0; valaddr_reg:x1; val_offset:1941*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1941*FLEN/8, x4, x2, x6) + +inst_680: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x303 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x061 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3ae and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3703; op2val:0x3861; +op3val:0x33ae; valaddr_reg:x1; val_offset:1944*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1944*FLEN/8, x4, x2, x6) + +inst_681: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x303 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x061 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3ae and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3703; op2val:0x3861; +op3val:0x33ae; valaddr_reg:x1; val_offset:1947*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1947*FLEN/8, x4, x2, x6) + +inst_682: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x303 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x061 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3ae and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3703; op2val:0x3861; +op3val:0x33ae; valaddr_reg:x1; val_offset:1950*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1950*FLEN/8, x4, x2, x6) + +inst_683: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x303 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x061 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3ae and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3703; op2val:0x3861; +op3val:0x33ae; valaddr_reg:x1; val_offset:1953*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1953*FLEN/8, x4, x2, x6) + +inst_684: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x303 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x061 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3ae and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3703; op2val:0x3861; +op3val:0x33ae; valaddr_reg:x1; val_offset:1956*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1956*FLEN/8, x4, x2, x6) + +inst_685: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x19a and fs2 == 0 and fe2 == 0x11 and fm2 == 0x25b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x074 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2d9a; op2val:0x465b; +op3val:0x3874; valaddr_reg:x1; val_offset:1959*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1959*FLEN/8, x4, x2, x6) + +inst_686: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x19a and fs2 == 0 and fe2 == 0x11 and fm2 == 0x25b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x074 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2d9a; op2val:0x465b; +op3val:0x3874; valaddr_reg:x1; val_offset:1962*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1962*FLEN/8, x4, x2, x6) + +inst_687: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x19a and fs2 == 0 and fe2 == 0x11 and fm2 == 0x25b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x074 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2d9a; op2val:0x465b; +op3val:0x3874; valaddr_reg:x1; val_offset:1965*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1965*FLEN/8, x4, x2, x6) + +inst_688: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x19a and fs2 == 0 and fe2 == 0x11 and fm2 == 0x25b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x074 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2d9a; op2val:0x465b; +op3val:0x3874; valaddr_reg:x1; val_offset:1968*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1968*FLEN/8, x4, x2, x6) + +inst_689: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x19a and fs2 == 0 and fe2 == 0x11 and fm2 == 0x25b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x074 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2d9a; op2val:0x465b; +op3val:0x3874; valaddr_reg:x1; val_offset:1971*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1971*FLEN/8, x4, x2, x6) + +inst_690: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x233 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x11a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3e9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3633; op2val:0x3d1a; +op3val:0x37e9; valaddr_reg:x1; val_offset:1974*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1974*FLEN/8, x4, x2, x6) + +inst_691: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x233 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x11a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3e9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3633; op2val:0x3d1a; +op3val:0x37e9; valaddr_reg:x1; val_offset:1977*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1977*FLEN/8, x4, x2, x6) + +inst_692: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x233 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x11a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3e9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3633; op2val:0x3d1a; +op3val:0x37e9; valaddr_reg:x1; val_offset:1980*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1980*FLEN/8, x4, x2, x6) + +inst_693: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x233 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x11a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3e9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3633; op2val:0x3d1a; +op3val:0x37e9; valaddr_reg:x1; val_offset:1983*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1983*FLEN/8, x4, x2, x6) + +inst_694: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x233 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x11a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3e9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3633; op2val:0x3d1a; +op3val:0x37e9; valaddr_reg:x1; val_offset:1986*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1986*FLEN/8, x4, x2, x6) + +inst_695: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ce and fs2 == 0 and fe2 == 0x0e and fm2 == 0x10a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0ea and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37ce; op2val:0x390a; +op3val:0x34ea; valaddr_reg:x1; val_offset:1989*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1989*FLEN/8, x4, x2, x6) + +inst_696: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ce and fs2 == 0 and fe2 == 0x0e and fm2 == 0x10a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0ea and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37ce; op2val:0x390a; +op3val:0x34ea; valaddr_reg:x1; val_offset:1992*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1992*FLEN/8, x4, x2, x6) + +inst_697: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ce and fs2 == 0 and fe2 == 0x0e and fm2 == 0x10a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0ea and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37ce; op2val:0x390a; +op3val:0x34ea; valaddr_reg:x1; val_offset:1995*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1995*FLEN/8, x4, x2, x6) + +inst_698: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ce and fs2 == 0 and fe2 == 0x0e and fm2 == 0x10a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0ea and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37ce; op2val:0x390a; +op3val:0x34ea; valaddr_reg:x1; val_offset:1998*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1998*FLEN/8, x4, x2, x6) + +inst_699: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ce and fs2 == 0 and fe2 == 0x0e and fm2 == 0x10a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0ea and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37ce; op2val:0x390a; +op3val:0x34ea; valaddr_reg:x1; val_offset:2001*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2001*FLEN/8, x4, x2, x6) + +inst_700: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x061 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d1 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x377 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3861; op2val:0x3ad1; +op3val:0x3777; valaddr_reg:x1; val_offset:2004*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2004*FLEN/8, x4, x2, x6) + +inst_701: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x061 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d1 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x377 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3861; op2val:0x3ad1; +op3val:0x3777; valaddr_reg:x1; val_offset:2007*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2007*FLEN/8, x4, x2, x6) + +inst_702: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x061 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d1 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x377 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3861; op2val:0x3ad1; +op3val:0x3777; valaddr_reg:x1; val_offset:2010*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2010*FLEN/8, x4, x2, x6) + +inst_703: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x061 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d1 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x377 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3861; op2val:0x3ad1; +op3val:0x3777; valaddr_reg:x1; val_offset:2013*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2013*FLEN/8, x4, x2, x6) + +inst_704: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x061 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d1 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x377 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3861; op2val:0x3ad1; +op3val:0x3777; valaddr_reg:x1; val_offset:2016*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2016*FLEN/8, x4, x2, x6) + +inst_705: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02d and fs2 == 0 and fe2 == 0x0b and fm2 == 0x32f and fs3 == 0 and fe3 == 0x0a and fm3 == 0x37e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x382d; op2val:0x2f2f; +op3val:0x2b7e; valaddr_reg:x1; val_offset:2019*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2019*FLEN/8, x4, x2, x6) + +inst_706: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02d and fs2 == 0 and fe2 == 0x0b and fm2 == 0x32f and fs3 == 0 and fe3 == 0x0a and fm3 == 0x37e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x382d; op2val:0x2f2f; +op3val:0x2b7e; valaddr_reg:x1; val_offset:2022*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2022*FLEN/8, x4, x2, x6) + +inst_707: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02d and fs2 == 0 and fe2 == 0x0b and fm2 == 0x32f and fs3 == 0 and fe3 == 0x0a and fm3 == 0x37e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x382d; op2val:0x2f2f; +op3val:0x2b7e; valaddr_reg:x1; val_offset:2025*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2025*FLEN/8, x4, x2, x6) + +inst_708: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02d and fs2 == 0 and fe2 == 0x0b and fm2 == 0x32f and fs3 == 0 and fe3 == 0x0a and fm3 == 0x37e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x382d; op2val:0x2f2f; +op3val:0x2b7e; valaddr_reg:x1; val_offset:2028*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2028*FLEN/8, x4, x2, x6) + +inst_709: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02d and fs2 == 0 and fe2 == 0x0b and fm2 == 0x32f and fs3 == 0 and fe3 == 0x0a and fm3 == 0x37e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x382d; op2val:0x2f2f; +op3val:0x2b7e; valaddr_reg:x1; val_offset:2031*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2031*FLEN/8, x4, x2, x6) + +inst_710: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0d0 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x292 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x3e7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34d0; op2val:0x3692; +op3val:0x2fe7; valaddr_reg:x1; val_offset:2034*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2034*FLEN/8, x4, x2, x6) + +inst_711: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0d0 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x292 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x3e7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34d0; op2val:0x3692; +op3val:0x2fe7; valaddr_reg:x1; val_offset:2037*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2037*FLEN/8, x4, x2, x6) + +inst_712: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0d0 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x292 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x3e7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34d0; op2val:0x3692; +op3val:0x2fe7; valaddr_reg:x1; val_offset:2040*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2040*FLEN/8, x4, x2, x6) + +inst_713: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0d0 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x292 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x3e7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34d0; op2val:0x3692; +op3val:0x2fe7; valaddr_reg:x1; val_offset:2043*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2043*FLEN/8, x4, x2, x6) + +inst_714: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0d0 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x292 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x3e7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34d0; op2val:0x3692; +op3val:0x2fe7; valaddr_reg:x1; val_offset:2046*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2046*FLEN/8, x4, x2, x6) + +inst_715: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x368 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x265 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ec and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2b68; op2val:0x4a65; +op3val:0x39ec; valaddr_reg:x1; val_offset:2049*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2049*FLEN/8, x4, x2, x6) + +inst_716: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x368 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x265 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ec and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2b68; op2val:0x4a65; +op3val:0x39ec; valaddr_reg:x1; val_offset:2052*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2052*FLEN/8, x4, x2, x6) + +inst_717: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x368 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x265 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ec and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2b68; op2val:0x4a65; +op3val:0x39ec; valaddr_reg:x1; val_offset:2055*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2055*FLEN/8, x4, x2, x6) + +inst_718: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x368 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x265 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ec and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2b68; op2val:0x4a65; +op3val:0x39ec; valaddr_reg:x1; val_offset:2058*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2058*FLEN/8, x4, x2, x6) + +inst_719: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x368 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x265 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ec and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2b68; op2val:0x4a65; +op3val:0x39ec; valaddr_reg:x1; val_offset:2061*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2061*FLEN/8, x4, x2, x6) + +inst_720: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x30c and fs2 == 0 and fe2 == 0x0c and fm2 == 0x021 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x344 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x370c; op2val:0x3021; +op3val:0x2b44; valaddr_reg:x1; val_offset:2064*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2064*FLEN/8, x4, x2, x6) + +inst_721: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x30c and fs2 == 0 and fe2 == 0x0c and fm2 == 0x021 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x344 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x370c; op2val:0x3021; +op3val:0x2b44; valaddr_reg:x1; val_offset:2067*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2067*FLEN/8, x4, x2, x6) + +inst_722: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x30c and fs2 == 0 and fe2 == 0x0c and fm2 == 0x021 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x344 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x370c; op2val:0x3021; +op3val:0x2b44; valaddr_reg:x1; val_offset:2070*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2070*FLEN/8, x4, x2, x6) + +inst_723: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x30c and fs2 == 0 and fe2 == 0x0c and fm2 == 0x021 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x344 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x370c; op2val:0x3021; +op3val:0x2b44; valaddr_reg:x1; val_offset:2073*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2073*FLEN/8, x4, x2, x6) + +inst_724: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x30c and fs2 == 0 and fe2 == 0x0c and fm2 == 0x021 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x344 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x370c; op2val:0x3021; +op3val:0x2b44; valaddr_reg:x1; val_offset:2076*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2076*FLEN/8, x4, x2, x6) + +inst_725: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x11f and fs2 == 0 and fe2 == 0x11 and fm2 == 0x164 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2e7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x311f; op2val:0x4564; +op3val:0x3ae7; valaddr_reg:x1; val_offset:2079*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2079*FLEN/8, x4, x2, x6) + +inst_726: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x11f and fs2 == 0 and fe2 == 0x11 and fm2 == 0x164 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2e7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x311f; op2val:0x4564; +op3val:0x3ae7; valaddr_reg:x1; val_offset:2082*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2082*FLEN/8, x4, x2, x6) + +inst_727: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x11f and fs2 == 0 and fe2 == 0x11 and fm2 == 0x164 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2e7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x311f; op2val:0x4564; +op3val:0x3ae7; valaddr_reg:x1; val_offset:2085*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2085*FLEN/8, x4, x2, x6) + +inst_728: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x11f and fs2 == 0 and fe2 == 0x11 and fm2 == 0x164 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2e7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x311f; op2val:0x4564; +op3val:0x3ae7; valaddr_reg:x1; val_offset:2088*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2088*FLEN/8, x4, x2, x6) + +inst_729: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x11f and fs2 == 0 and fe2 == 0x11 and fm2 == 0x164 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2e7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x311f; op2val:0x4564; +op3val:0x3ae7; valaddr_reg:x1; val_offset:2091*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2091*FLEN/8, x4, x2, x6) + +inst_730: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x306 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x114 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x076 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b06; op2val:0x3914; +op3val:0x3876; valaddr_reg:x1; val_offset:2094*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2094*FLEN/8, x4, x2, x6) + +inst_731: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x306 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x114 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x076 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b06; op2val:0x3914; +op3val:0x3876; valaddr_reg:x1; val_offset:2097*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2097*FLEN/8, x4, x2, x6) + +inst_732: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x306 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x114 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x076 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b06; op2val:0x3914; +op3val:0x3876; valaddr_reg:x1; val_offset:2100*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2100*FLEN/8, x4, x2, x6) + +inst_733: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x306 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x114 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x076 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b06; op2val:0x3914; +op3val:0x3876; valaddr_reg:x1; val_offset:2103*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2103*FLEN/8, x4, x2, x6) + +inst_734: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x306 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x114 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x076 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b06; op2val:0x3914; +op3val:0x3876; valaddr_reg:x1; val_offset:2106*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2106*FLEN/8, x4, x2, x6) + +inst_735: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x28c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x213 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b6b; op2val:0x3a8c; +op3val:0x3a13; valaddr_reg:x1; val_offset:2109*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2109*FLEN/8, x4, x2, x6) + +inst_736: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x28c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x213 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b6b; op2val:0x3a8c; +op3val:0x3a13; valaddr_reg:x1; val_offset:2112*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2112*FLEN/8, x4, x2, x6) + +inst_737: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x28c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x213 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b6b; op2val:0x3a8c; +op3val:0x3a13; valaddr_reg:x1; val_offset:2115*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2115*FLEN/8, x4, x2, x6) + +inst_738: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x28c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x213 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b6b; op2val:0x3a8c; +op3val:0x3a13; valaddr_reg:x1; val_offset:2118*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2118*FLEN/8, x4, x2, x6) + +inst_739: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x28c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x213 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b6b; op2val:0x3a8c; +op3val:0x3a13; valaddr_reg:x1; val_offset:2121*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2121*FLEN/8, x4, x2, x6) + +inst_740: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1b5 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x14a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b6a; op2val:0x35b5; +op3val:0x354a; valaddr_reg:x1; val_offset:2124*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2124*FLEN/8, x4, x2, x6) + +inst_741: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1b5 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x14a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b6a; op2val:0x35b5; +op3val:0x354a; valaddr_reg:x1; val_offset:2127*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2127*FLEN/8, x4, x2, x6) + +inst_742: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1b5 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x14a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b6a; op2val:0x35b5; +op3val:0x354a; valaddr_reg:x1; val_offset:2130*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2130*FLEN/8, x4, x2, x6) + +inst_743: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1b5 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x14a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b6a; op2val:0x35b5; +op3val:0x354a; valaddr_reg:x1; val_offset:2133*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2133*FLEN/8, x4, x2, x6) + +inst_744: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1b5 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x14a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b6a; op2val:0x35b5; +op3val:0x354a; valaddr_reg:x1; val_offset:2136*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2136*FLEN/8, x4, x2, x6) + +inst_745: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2ea and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3a1 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x298 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32ea; op2val:0x37a1; +op3val:0x2e98; valaddr_reg:x1; val_offset:2139*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2139*FLEN/8, x4, x2, x6) + +inst_746: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2ea and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3a1 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x298 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32ea; op2val:0x37a1; +op3val:0x2e98; valaddr_reg:x1; val_offset:2142*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2142*FLEN/8, x4, x2, x6) + +inst_747: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2ea and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3a1 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x298 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32ea; op2val:0x37a1; +op3val:0x2e98; valaddr_reg:x1; val_offset:2145*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2145*FLEN/8, x4, x2, x6) + +inst_748: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2ea and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3a1 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x298 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32ea; op2val:0x37a1; +op3val:0x2e98; valaddr_reg:x1; val_offset:2148*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2148*FLEN/8, x4, x2, x6) + +inst_749: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2ea and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3a1 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x298 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32ea; op2val:0x37a1; +op3val:0x2e98; valaddr_reg:x1; val_offset:2151*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2151*FLEN/8, x4, x2, x6) + +inst_750: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2c3 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x15f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x08a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ac3; op2val:0x355f; +op3val:0x348a; valaddr_reg:x1; val_offset:2154*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2154*FLEN/8, x4, x2, x6) + +inst_751: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2c3 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x15f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x08a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ac3; op2val:0x355f; +op3val:0x348a; valaddr_reg:x1; val_offset:2157*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2157*FLEN/8, x4, x2, x6) + +inst_752: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2c3 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x15f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x08a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ac3; op2val:0x355f; +op3val:0x348a; valaddr_reg:x1; val_offset:2160*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2160*FLEN/8, x4, x2, x6) + +inst_753: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2c3 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x15f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x08a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ac3; op2val:0x355f; +op3val:0x348a; valaddr_reg:x1; val_offset:2163*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2163*FLEN/8, x4, x2, x6) + +inst_754: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2c3 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x15f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x08a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ac3; op2val:0x355f; +op3val:0x348a; valaddr_reg:x1; val_offset:2166*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2166*FLEN/8, x4, x2, x6) + +inst_755: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x16f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x10b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2db and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x356f; op2val:0x410b; +op3val:0x3adb; valaddr_reg:x1; val_offset:2169*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2169*FLEN/8, x4, x2, x6) + +inst_756: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x16f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x10b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2db and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x356f; op2val:0x410b; +op3val:0x3adb; valaddr_reg:x1; val_offset:2172*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2172*FLEN/8, x4, x2, x6) + +inst_757: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x16f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x10b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2db and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x356f; op2val:0x410b; +op3val:0x3adb; valaddr_reg:x1; val_offset:2175*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2175*FLEN/8, x4, x2, x6) + +inst_758: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x16f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x10b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2db and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x356f; op2val:0x410b; +op3val:0x3adb; valaddr_reg:x1; val_offset:2178*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2178*FLEN/8, x4, x2, x6) + +inst_759: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x16f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x10b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2db and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x356f; op2val:0x410b; +op3val:0x3adb; valaddr_reg:x1; val_offset:2181*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2181*FLEN/8, x4, x2, x6) + +inst_760: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x380 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x072 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x029 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f80; op2val:0x3472; +op3val:0x2829; valaddr_reg:x1; val_offset:2184*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2184*FLEN/8, x4, x2, x6) + +inst_761: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x380 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x072 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x029 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f80; op2val:0x3472; +op3val:0x2829; valaddr_reg:x1; val_offset:2187*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2187*FLEN/8, x4, x2, x6) + +inst_762: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x380 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x072 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x029 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f80; op2val:0x3472; +op3val:0x2829; valaddr_reg:x1; val_offset:2190*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2190*FLEN/8, x4, x2, x6) + +inst_763: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x380 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x072 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x029 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f80; op2val:0x3472; +op3val:0x2829; valaddr_reg:x1; val_offset:2193*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2193*FLEN/8, x4, x2, x6) + +inst_764: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x380 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x072 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x029 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f80; op2val:0x3472; +op3val:0x2829; valaddr_reg:x1; val_offset:2196*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2196*FLEN/8, x4, x2, x6) + +inst_765: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23e and fs2 == 0 and fe2 == 0x0a and fm2 == 0x3cf and fs3 == 0 and fe3 == 0x0a and fm3 == 0x216 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a3e; op2val:0x2bcf; +op3val:0x2a16; valaddr_reg:x1; val_offset:2199*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2199*FLEN/8, x4, x2, x6) + +inst_766: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23e and fs2 == 0 and fe2 == 0x0a and fm2 == 0x3cf and fs3 == 0 and fe3 == 0x0a and fm3 == 0x216 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a3e; op2val:0x2bcf; +op3val:0x2a16; valaddr_reg:x1; val_offset:2202*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2202*FLEN/8, x4, x2, x6) + +inst_767: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23e and fs2 == 0 and fe2 == 0x0a and fm2 == 0x3cf and fs3 == 0 and fe3 == 0x0a and fm3 == 0x216 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a3e; op2val:0x2bcf; +op3val:0x2a16; valaddr_reg:x1; val_offset:2205*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2205*FLEN/8, x4, x2, x6) + +inst_768: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23e and fs2 == 0 and fe2 == 0x0a and fm2 == 0x3cf and fs3 == 0 and fe3 == 0x0a and fm3 == 0x216 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a3e; op2val:0x2bcf; +op3val:0x2a16; valaddr_reg:x1; val_offset:2208*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2208*FLEN/8, x4, x2, x6) + +inst_769: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23e and fs2 == 0 and fe2 == 0x0a and fm2 == 0x3cf and fs3 == 0 and fe3 == 0x0a and fm3 == 0x216 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a3e; op2val:0x2bcf; +op3val:0x2a16; valaddr_reg:x1; val_offset:2211*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2211*FLEN/8, x4, x2, x6) + +inst_770: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d0 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x01a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38d0; op2val:0x3ad1; +op3val:0x381a; valaddr_reg:x1; val_offset:2214*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2214*FLEN/8, x4, x2, x6) + +inst_771: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d0 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x01a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38d0; op2val:0x3ad1; +op3val:0x381a; valaddr_reg:x1; val_offset:2217*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2217*FLEN/8, x4, x2, x6) + +inst_772: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d0 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x01a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38d0; op2val:0x3ad1; +op3val:0x381a; valaddr_reg:x1; val_offset:2220*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2220*FLEN/8, x4, x2, x6) + +inst_773: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d0 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x01a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38d0; op2val:0x3ad1; +op3val:0x381a; valaddr_reg:x1; val_offset:2223*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2223*FLEN/8, x4, x2, x6) + +inst_774: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d0 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x01a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38d0; op2val:0x3ad1; +op3val:0x381a; valaddr_reg:x1; val_offset:2226*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2226*FLEN/8, x4, x2, x6) + +inst_775: +// fs1 == 0 and fe1 == 0x08 and fm1 == 0x137 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x01d and fs3 == 0 and fe3 == 0x0c and fm3 == 0x15d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2137; op2val:0x4c1d; +op3val:0x315d; valaddr_reg:x1; val_offset:2229*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2229*FLEN/8, x4, x2, x6) + +inst_776: +// fs1 == 0 and fe1 == 0x08 and fm1 == 0x137 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x01d and fs3 == 0 and fe3 == 0x0c and fm3 == 0x15d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2137; op2val:0x4c1d; +op3val:0x315d; valaddr_reg:x1; val_offset:2232*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2232*FLEN/8, x4, x2, x6) + +inst_777: +// fs1 == 0 and fe1 == 0x08 and fm1 == 0x137 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x01d and fs3 == 0 and fe3 == 0x0c and fm3 == 0x15d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2137; op2val:0x4c1d; +op3val:0x315d; valaddr_reg:x1; val_offset:2235*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2235*FLEN/8, x4, x2, x6) + +inst_778: +// fs1 == 0 and fe1 == 0x08 and fm1 == 0x137 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x01d and fs3 == 0 and fe3 == 0x0c and fm3 == 0x15d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2137; op2val:0x4c1d; +op3val:0x315d; valaddr_reg:x1; val_offset:2238*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2238*FLEN/8, x4, x2, x6) + +inst_779: +// fs1 == 0 and fe1 == 0x08 and fm1 == 0x137 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x01d and fs3 == 0 and fe3 == 0x0c and fm3 == 0x15d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2137; op2val:0x4c1d; +op3val:0x315d; valaddr_reg:x1; val_offset:2241*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2241*FLEN/8, x4, x2, x6) + +inst_780: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x16c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ab5; op2val:0x396c; +op3val:0x388c; valaddr_reg:x1; val_offset:2244*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2244*FLEN/8, x4, x2, x6) + +inst_781: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x16c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ab5; op2val:0x396c; +op3val:0x388c; valaddr_reg:x1; val_offset:2247*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2247*FLEN/8, x4, x2, x6) + +inst_782: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x16c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ab5; op2val:0x396c; +op3val:0x388c; valaddr_reg:x1; val_offset:2250*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2250*FLEN/8, x4, x2, x6) + +inst_783: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x16c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ab5; op2val:0x396c; +op3val:0x388c; valaddr_reg:x1; val_offset:2253*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2253*FLEN/8, x4, x2, x6) + +inst_784: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x16c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ab5; op2val:0x396c; +op3val:0x388c; valaddr_reg:x1; val_offset:2256*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2256*FLEN/8, x4, x2, x6) + +inst_785: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x175 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x149 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37c0; op2val:0x3d75; +op3val:0x3949; valaddr_reg:x1; val_offset:2259*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2259*FLEN/8, x4, x2, x6) + +inst_786: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x175 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x149 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37c0; op2val:0x3d75; +op3val:0x3949; valaddr_reg:x1; val_offset:2262*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2262*FLEN/8, x4, x2, x6) + +inst_787: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x175 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x149 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37c0; op2val:0x3d75; +op3val:0x3949; valaddr_reg:x1; val_offset:2265*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2265*FLEN/8, x4, x2, x6) + +inst_788: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x175 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x149 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37c0; op2val:0x3d75; +op3val:0x3949; valaddr_reg:x1; val_offset:2268*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2268*FLEN/8, x4, x2, x6) + +inst_789: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x175 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x149 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37c0; op2val:0x3d75; +op3val:0x3949; valaddr_reg:x1; val_offset:2271*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2271*FLEN/8, x4, x2, x6) + +inst_790: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x26f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2c7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x173 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a6f; op2val:0x3ac7; +op3val:0x3973; valaddr_reg:x1; val_offset:2274*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2274*FLEN/8, x4, x2, x6) + +inst_791: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x26f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2c7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x173 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a6f; op2val:0x3ac7; +op3val:0x3973; valaddr_reg:x1; val_offset:2277*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2277*FLEN/8, x4, x2, x6) + +inst_792: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x26f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2c7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x173 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a6f; op2val:0x3ac7; +op3val:0x3973; valaddr_reg:x1; val_offset:2280*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2280*FLEN/8, x4, x2, x6) + +inst_793: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x26f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2c7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x173 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a6f; op2val:0x3ac7; +op3val:0x3973; valaddr_reg:x1; val_offset:2283*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2283*FLEN/8, x4, x2, x6) + +inst_794: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x26f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2c7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x173 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a6f; op2val:0x3ac7; +op3val:0x3973; valaddr_reg:x1; val_offset:2286*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2286*FLEN/8, x4, x2, x6) + +inst_795: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x072 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x30e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3d8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3472; op2val:0x430e; +op3val:0x3bd8; valaddr_reg:x1; val_offset:2289*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2289*FLEN/8, x4, x2, x6) +RVTEST_SIGBASE(x2,signature_x2_6) + +inst_796: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x072 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x30e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3d8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3472; op2val:0x430e; +op3val:0x3bd8; valaddr_reg:x1; val_offset:2292*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2292*FLEN/8, x4, x2, x6) + +inst_797: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x072 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x30e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3d8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3472; op2val:0x430e; +op3val:0x3bd8; valaddr_reg:x1; val_offset:2295*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2295*FLEN/8, x4, x2, x6) + +inst_798: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x072 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x30e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3d8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3472; op2val:0x430e; +op3val:0x3bd8; valaddr_reg:x1; val_offset:2298*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2298*FLEN/8, x4, x2, x6) + +inst_799: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x072 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x30e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3d8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3472; op2val:0x430e; +op3val:0x3bd8; valaddr_reg:x1; val_offset:2301*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2301*FLEN/8, x4, x2, x6) + +inst_800: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x322 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x104 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x079 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3722; op2val:0x3d04; +op3val:0x3879; valaddr_reg:x1; val_offset:2304*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2304*FLEN/8, x4, x2, x6) + +inst_801: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x322 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x104 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x079 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3722; op2val:0x3d04; +op3val:0x3879; valaddr_reg:x1; val_offset:2307*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2307*FLEN/8, x4, x2, x6) + +inst_802: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x322 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x104 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x079 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3722; op2val:0x3d04; +op3val:0x3879; valaddr_reg:x1; val_offset:2310*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2310*FLEN/8, x4, x2, x6) + +inst_803: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x322 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x104 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x079 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3722; op2val:0x3d04; +op3val:0x3879; valaddr_reg:x1; val_offset:2313*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2313*FLEN/8, x4, x2, x6) + +inst_804: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x322 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x104 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x079 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3722; op2val:0x3d04; +op3val:0x3879; valaddr_reg:x1; val_offset:2316*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2316*FLEN/8, x4, x2, x6) + +inst_805: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3da and fs2 == 0 and fe2 == 0x0e and fm2 == 0x172 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x159 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bda; op2val:0x3972; +op3val:0x3959; valaddr_reg:x1; val_offset:2319*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2319*FLEN/8, x4, x2, x6) + +inst_806: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3da and fs2 == 0 and fe2 == 0x0e and fm2 == 0x172 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x159 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bda; op2val:0x3972; +op3val:0x3959; valaddr_reg:x1; val_offset:2322*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2322*FLEN/8, x4, x2, x6) + +inst_807: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3da and fs2 == 0 and fe2 == 0x0e and fm2 == 0x172 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x159 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bda; op2val:0x3972; +op3val:0x3959; valaddr_reg:x1; val_offset:2325*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2325*FLEN/8, x4, x2, x6) + +inst_808: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3da and fs2 == 0 and fe2 == 0x0e and fm2 == 0x172 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x159 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bda; op2val:0x3972; +op3val:0x3959; valaddr_reg:x1; val_offset:2328*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2328*FLEN/8, x4, x2, x6) + +inst_809: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3da and fs2 == 0 and fe2 == 0x0e and fm2 == 0x172 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x159 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bda; op2val:0x3972; +op3val:0x3959; valaddr_reg:x1; val_offset:2331*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2331*FLEN/8, x4, x2, x6) + +inst_810: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x204 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x130 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3cd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3604; op2val:0x3d30; +op3val:0x37cd; valaddr_reg:x1; val_offset:2334*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2334*FLEN/8, x4, x2, x6) + +inst_811: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x204 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x130 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3cd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3604; op2val:0x3d30; +op3val:0x37cd; valaddr_reg:x1; val_offset:2337*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2337*FLEN/8, x4, x2, x6) + +inst_812: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x204 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x130 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3cd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3604; op2val:0x3d30; +op3val:0x37cd; valaddr_reg:x1; val_offset:2340*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2340*FLEN/8, x4, x2, x6) + +inst_813: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x204 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x130 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3cd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3604; op2val:0x3d30; +op3val:0x37cd; valaddr_reg:x1; val_offset:2343*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2343*FLEN/8, x4, x2, x6) + +inst_814: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x204 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x130 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3cd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3604; op2val:0x3d30; +op3val:0x37cd; valaddr_reg:x1; val_offset:2346*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2346*FLEN/8, x4, x2, x6) + +inst_815: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x37c and fs2 == 0 and fe2 == 0x09 and fm2 == 0x01d and fs3 == 0 and fe3 == 0x08 and fm3 == 0x3ab and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b7c; op2val:0x241d; +op3val:0x23ab; valaddr_reg:x1; val_offset:2349*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2349*FLEN/8, x4, x2, x6) + +inst_816: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x37c and fs2 == 0 and fe2 == 0x09 and fm2 == 0x01d and fs3 == 0 and fe3 == 0x08 and fm3 == 0x3ab and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b7c; op2val:0x241d; +op3val:0x23ab; valaddr_reg:x1; val_offset:2352*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2352*FLEN/8, x4, x2, x6) + +inst_817: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x37c and fs2 == 0 and fe2 == 0x09 and fm2 == 0x01d and fs3 == 0 and fe3 == 0x08 and fm3 == 0x3ab and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b7c; op2val:0x241d; +op3val:0x23ab; valaddr_reg:x1; val_offset:2355*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2355*FLEN/8, x4, x2, x6) + +inst_818: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x37c and fs2 == 0 and fe2 == 0x09 and fm2 == 0x01d and fs3 == 0 and fe3 == 0x08 and fm3 == 0x3ab and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b7c; op2val:0x241d; +op3val:0x23ab; valaddr_reg:x1; val_offset:2358*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2358*FLEN/8, x4, x2, x6) + +inst_819: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x37c and fs2 == 0 and fe2 == 0x09 and fm2 == 0x01d and fs3 == 0 and fe3 == 0x08 and fm3 == 0x3ab and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b7c; op2val:0x241d; +op3val:0x23ab; valaddr_reg:x1; val_offset:2361*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2361*FLEN/8, x4, x2, x6) + +inst_820: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2c6 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x04c and fs3 == 0 and fe3 == 0x09 and fm3 == 0x342 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32c6; op2val:0x304c; +op3val:0x2742; valaddr_reg:x1; val_offset:2364*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2364*FLEN/8, x4, x2, x6) + +inst_821: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2c6 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x04c and fs3 == 0 and fe3 == 0x09 and fm3 == 0x342 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32c6; op2val:0x304c; +op3val:0x2742; valaddr_reg:x1; val_offset:2367*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2367*FLEN/8, x4, x2, x6) + +inst_822: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2c6 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x04c and fs3 == 0 and fe3 == 0x09 and fm3 == 0x342 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32c6; op2val:0x304c; +op3val:0x2742; valaddr_reg:x1; val_offset:2370*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2370*FLEN/8, x4, x2, x6) + +inst_823: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2c6 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x04c and fs3 == 0 and fe3 == 0x09 and fm3 == 0x342 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32c6; op2val:0x304c; +op3val:0x2742; valaddr_reg:x1; val_offset:2373*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2373*FLEN/8, x4, x2, x6) + +inst_824: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2c6 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x04c and fs3 == 0 and fe3 == 0x09 and fm3 == 0x342 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32c6; op2val:0x304c; +op3val:0x2742; valaddr_reg:x1; val_offset:2376*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2376*FLEN/8, x4, x2, x6) + +inst_825: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x329 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x290 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b29; op2val:0x3a90; +op3val:0x39e0; valaddr_reg:x1; val_offset:2379*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2379*FLEN/8, x4, x2, x6) + +inst_826: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x329 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x290 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b29; op2val:0x3a90; +op3val:0x39e0; valaddr_reg:x1; val_offset:2382*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2382*FLEN/8, x4, x2, x6) + +inst_827: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x329 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x290 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b29; op2val:0x3a90; +op3val:0x39e0; valaddr_reg:x1; val_offset:2385*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2385*FLEN/8, x4, x2, x6) + +inst_828: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x329 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x290 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b29; op2val:0x3a90; +op3val:0x39e0; valaddr_reg:x1; val_offset:2388*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2388*FLEN/8, x4, x2, x6) + +inst_829: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x329 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x290 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b29; op2val:0x3a90; +op3val:0x39e0; valaddr_reg:x1; val_offset:2391*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2391*FLEN/8, x4, x2, x6) + +inst_830: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ae and fs2 == 0 and fe2 == 0x0c and fm2 == 0x35e and fs3 == 0 and fe3 == 0x0c and fm3 == 0x312 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bae; op2val:0x335e; +op3val:0x3312; valaddr_reg:x1; val_offset:2394*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2394*FLEN/8, x4, x2, x6) + +inst_831: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ae and fs2 == 0 and fe2 == 0x0c and fm2 == 0x35e and fs3 == 0 and fe3 == 0x0c and fm3 == 0x312 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bae; op2val:0x335e; +op3val:0x3312; valaddr_reg:x1; val_offset:2397*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2397*FLEN/8, x4, x2, x6) + +inst_832: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ae and fs2 == 0 and fe2 == 0x0c and fm2 == 0x35e and fs3 == 0 and fe3 == 0x0c and fm3 == 0x312 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bae; op2val:0x335e; +op3val:0x3312; valaddr_reg:x1; val_offset:2400*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2400*FLEN/8, x4, x2, x6) + +inst_833: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ae and fs2 == 0 and fe2 == 0x0c and fm2 == 0x35e and fs3 == 0 and fe3 == 0x0c and fm3 == 0x312 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bae; op2val:0x335e; +op3val:0x3312; valaddr_reg:x1; val_offset:2403*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2403*FLEN/8, x4, x2, x6) + +inst_834: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ae and fs2 == 0 and fe2 == 0x0c and fm2 == 0x35e and fs3 == 0 and fe3 == 0x0c and fm3 == 0x312 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bae; op2val:0x335e; +op3val:0x3312; valaddr_reg:x1; val_offset:2406*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2406*FLEN/8, x4, x2, x6) + +inst_835: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1d6 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2f6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39d6; op2val:0x3cc5; +op3val:0x3af6; valaddr_reg:x1; val_offset:2409*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2409*FLEN/8, x4, x2, x6) + +inst_836: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1d6 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2f6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39d6; op2val:0x3cc5; +op3val:0x3af6; valaddr_reg:x1; val_offset:2412*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2412*FLEN/8, x4, x2, x6) + +inst_837: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1d6 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2f6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39d6; op2val:0x3cc5; +op3val:0x3af6; valaddr_reg:x1; val_offset:2415*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2415*FLEN/8, x4, x2, x6) + +inst_838: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1d6 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2f6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39d6; op2val:0x3cc5; +op3val:0x3af6; valaddr_reg:x1; val_offset:2418*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2418*FLEN/8, x4, x2, x6) + +inst_839: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1d6 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2f6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39d6; op2val:0x3cc5; +op3val:0x3af6; valaddr_reg:x1; val_offset:2421*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2421*FLEN/8, x4, x2, x6) + +inst_840: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x09f and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0e9 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1ac and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x389f; op2val:0x30e9; +op3val:0x2dac; valaddr_reg:x1; val_offset:2424*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2424*FLEN/8, x4, x2, x6) + +inst_841: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x09f and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0e9 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1ac and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x389f; op2val:0x30e9; +op3val:0x2dac; valaddr_reg:x1; val_offset:2427*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2427*FLEN/8, x4, x2, x6) + +inst_842: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x09f and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0e9 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1ac and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x389f; op2val:0x30e9; +op3val:0x2dac; valaddr_reg:x1; val_offset:2430*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2430*FLEN/8, x4, x2, x6) + +inst_843: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x09f and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0e9 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1ac and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x389f; op2val:0x30e9; +op3val:0x2dac; valaddr_reg:x1; val_offset:2433*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2433*FLEN/8, x4, x2, x6) + +inst_844: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x09f and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0e9 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1ac and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x389f; op2val:0x30e9; +op3val:0x2dac; valaddr_reg:x1; val_offset:2436*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2436*FLEN/8, x4, x2, x6) + +inst_845: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1cb and fs2 == 0 and fe2 == 0x11 and fm2 == 0x018 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ee and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31cb; op2val:0x4418; +op3val:0x39ee; valaddr_reg:x1; val_offset:2439*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2439*FLEN/8, x4, x2, x6) + +inst_846: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1cb and fs2 == 0 and fe2 == 0x11 and fm2 == 0x018 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ee and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31cb; op2val:0x4418; +op3val:0x39ee; valaddr_reg:x1; val_offset:2442*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2442*FLEN/8, x4, x2, x6) + +inst_847: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1cb and fs2 == 0 and fe2 == 0x11 and fm2 == 0x018 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ee and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31cb; op2val:0x4418; +op3val:0x39ee; valaddr_reg:x1; val_offset:2445*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2445*FLEN/8, x4, x2, x6) + +inst_848: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1cb and fs2 == 0 and fe2 == 0x11 and fm2 == 0x018 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ee and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31cb; op2val:0x4418; +op3val:0x39ee; valaddr_reg:x1; val_offset:2448*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2448*FLEN/8, x4, x2, x6) + +inst_849: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1cb and fs2 == 0 and fe2 == 0x11 and fm2 == 0x018 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ee and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31cb; op2val:0x4418; +op3val:0x39ee; valaddr_reg:x1; val_offset:2451*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2451*FLEN/8, x4, x2, x6) + +inst_850: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ce and fs2 == 0 and fe2 == 0x0b and fm2 == 0x217 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x12d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ace; op2val:0x2e17; +op3val:0x2d2d; valaddr_reg:x1; val_offset:2454*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2454*FLEN/8, x4, x2, x6) + +inst_851: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ce and fs2 == 0 and fe2 == 0x0b and fm2 == 0x217 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x12d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ace; op2val:0x2e17; +op3val:0x2d2d; valaddr_reg:x1; val_offset:2457*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2457*FLEN/8, x4, x2, x6) + +inst_852: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ce and fs2 == 0 and fe2 == 0x0b and fm2 == 0x217 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x12d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ace; op2val:0x2e17; +op3val:0x2d2d; valaddr_reg:x1; val_offset:2460*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2460*FLEN/8, x4, x2, x6) + +inst_853: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ce and fs2 == 0 and fe2 == 0x0b and fm2 == 0x217 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x12d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ace; op2val:0x2e17; +op3val:0x2d2d; valaddr_reg:x1; val_offset:2463*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2463*FLEN/8, x4, x2, x6) + +inst_854: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ce and fs2 == 0 and fe2 == 0x0b and fm2 == 0x217 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x12d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ace; op2val:0x2e17; +op3val:0x2d2d; valaddr_reg:x1; val_offset:2466*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2466*FLEN/8, x4, x2, x6) + +inst_855: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2de and fs2 == 0 and fe2 == 0x0e and fm2 == 0x195 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0cb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36de; op2val:0x3995; +op3val:0x34cb; valaddr_reg:x1; val_offset:2469*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2469*FLEN/8, x4, x2, x6) + +inst_856: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2de and fs2 == 0 and fe2 == 0x0e and fm2 == 0x195 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0cb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36de; op2val:0x3995; +op3val:0x34cb; valaddr_reg:x1; val_offset:2472*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2472*FLEN/8, x4, x2, x6) + +inst_857: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2de and fs2 == 0 and fe2 == 0x0e and fm2 == 0x195 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0cb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36de; op2val:0x3995; +op3val:0x34cb; valaddr_reg:x1; val_offset:2475*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2475*FLEN/8, x4, x2, x6) + +inst_858: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2de and fs2 == 0 and fe2 == 0x0e and fm2 == 0x195 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0cb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36de; op2val:0x3995; +op3val:0x34cb; valaddr_reg:x1; val_offset:2478*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2478*FLEN/8, x4, x2, x6) + +inst_859: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2de and fs2 == 0 and fe2 == 0x0e and fm2 == 0x195 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0cb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36de; op2val:0x3995; +op3val:0x34cb; valaddr_reg:x1; val_offset:2481*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2481*FLEN/8, x4, x2, x6) + +inst_860: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x348 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x023 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x38a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b48; op2val:0x3c23; +op3val:0x3b8a; valaddr_reg:x1; val_offset:2484*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2484*FLEN/8, x4, x2, x6) + +inst_861: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x348 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x023 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x38a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b48; op2val:0x3c23; +op3val:0x3b8a; valaddr_reg:x1; val_offset:2487*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2487*FLEN/8, x4, x2, x6) + +inst_862: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x348 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x023 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x38a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b48; op2val:0x3c23; +op3val:0x3b8a; valaddr_reg:x1; val_offset:2490*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2490*FLEN/8, x4, x2, x6) + +inst_863: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x348 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x023 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x38a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b48; op2val:0x3c23; +op3val:0x3b8a; valaddr_reg:x1; val_offset:2493*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2493*FLEN/8, x4, x2, x6) + +inst_864: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x348 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x023 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x38a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b48; op2val:0x3c23; +op3val:0x3b8a; valaddr_reg:x1; val_offset:2496*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2496*FLEN/8, x4, x2, x6) + +inst_865: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0fd and fs2 == 0 and fe2 == 0x0f and fm2 == 0x35f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x099 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34fd; op2val:0x3f5f; +op3val:0x3899; valaddr_reg:x1; val_offset:2499*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2499*FLEN/8, x4, x2, x6) + +inst_866: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0fd and fs2 == 0 and fe2 == 0x0f and fm2 == 0x35f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x099 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34fd; op2val:0x3f5f; +op3val:0x3899; valaddr_reg:x1; val_offset:2502*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2502*FLEN/8, x4, x2, x6) + +inst_867: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0fd and fs2 == 0 and fe2 == 0x0f and fm2 == 0x35f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x099 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34fd; op2val:0x3f5f; +op3val:0x3899; valaddr_reg:x1; val_offset:2505*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2505*FLEN/8, x4, x2, x6) + +inst_868: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0fd and fs2 == 0 and fe2 == 0x0f and fm2 == 0x35f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x099 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34fd; op2val:0x3f5f; +op3val:0x3899; valaddr_reg:x1; val_offset:2508*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2508*FLEN/8, x4, x2, x6) + +inst_869: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0fd and fs2 == 0 and fe2 == 0x0f and fm2 == 0x35f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x099 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34fd; op2val:0x3f5f; +op3val:0x3899; valaddr_reg:x1; val_offset:2511*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2511*FLEN/8, x4, x2, x6) + +inst_870: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36b and fs2 == 0 and fe2 == 0x0b and fm2 == 0x043 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x3e6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b6b; op2val:0x2c43; +op3val:0x2be6; valaddr_reg:x1; val_offset:2514*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2514*FLEN/8, x4, x2, x6) + +inst_871: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36b and fs2 == 0 and fe2 == 0x0b and fm2 == 0x043 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x3e6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b6b; op2val:0x2c43; +op3val:0x2be6; valaddr_reg:x1; val_offset:2517*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2517*FLEN/8, x4, x2, x6) + +inst_872: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36b and fs2 == 0 and fe2 == 0x0b and fm2 == 0x043 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x3e6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b6b; op2val:0x2c43; +op3val:0x2be6; valaddr_reg:x1; val_offset:2520*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2520*FLEN/8, x4, x2, x6) + +inst_873: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36b and fs2 == 0 and fe2 == 0x0b and fm2 == 0x043 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x3e6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b6b; op2val:0x2c43; +op3val:0x2be6; valaddr_reg:x1; val_offset:2523*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2523*FLEN/8, x4, x2, x6) + +inst_874: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36b and fs2 == 0 and fe2 == 0x0b and fm2 == 0x043 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x3e6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b6b; op2val:0x2c43; +op3val:0x2be6; valaddr_reg:x1; val_offset:2526*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2526*FLEN/8, x4, x2, x6) + +inst_875: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1d9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x057 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x259 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35d9; op2val:0x3857; +op3val:0x3259; valaddr_reg:x1; val_offset:2529*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2529*FLEN/8, x4, x2, x6) + +inst_876: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1d9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x057 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x259 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35d9; op2val:0x3857; +op3val:0x3259; valaddr_reg:x1; val_offset:2532*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2532*FLEN/8, x4, x2, x6) + +inst_877: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1d9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x057 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x259 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35d9; op2val:0x3857; +op3val:0x3259; valaddr_reg:x1; val_offset:2535*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2535*FLEN/8, x4, x2, x6) + +inst_878: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1d9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x057 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x259 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35d9; op2val:0x3857; +op3val:0x3259; valaddr_reg:x1; val_offset:2538*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2538*FLEN/8, x4, x2, x6) + +inst_879: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1d9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x057 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x259 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35d9; op2val:0x3857; +op3val:0x3259; valaddr_reg:x1; val_offset:2541*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2541*FLEN/8, x4, x2, x6) + +inst_880: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x354 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x106 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x09a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b54; op2val:0x3106; +op3val:0x309a; valaddr_reg:x1; val_offset:2544*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2544*FLEN/8, x4, x2, x6) + +inst_881: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x354 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x106 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x09a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b54; op2val:0x3106; +op3val:0x309a; valaddr_reg:x1; val_offset:2547*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2547*FLEN/8, x4, x2, x6) + +inst_882: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x354 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x106 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x09a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b54; op2val:0x3106; +op3val:0x309a; valaddr_reg:x1; val_offset:2550*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2550*FLEN/8, x4, x2, x6) + +inst_883: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x354 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x106 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x09a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b54; op2val:0x3106; +op3val:0x309a; valaddr_reg:x1; val_offset:2553*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2553*FLEN/8, x4, x2, x6) + +inst_884: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x354 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x106 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x09a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b54; op2val:0x3106; +op3val:0x309a; valaddr_reg:x1; val_offset:2556*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2556*FLEN/8, x4, x2, x6) + +inst_885: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x377 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0b5 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x064 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b77; op2val:0x30b5; +op3val:0x3064; valaddr_reg:x1; val_offset:2559*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2559*FLEN/8, x4, x2, x6) + +inst_886: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x377 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0b5 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x064 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b77; op2val:0x30b5; +op3val:0x3064; valaddr_reg:x1; val_offset:2562*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2562*FLEN/8, x4, x2, x6) + +inst_887: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x377 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0b5 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x064 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b77; op2val:0x30b5; +op3val:0x3064; valaddr_reg:x1; val_offset:2565*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2565*FLEN/8, x4, x2, x6) + +inst_888: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x377 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0b5 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x064 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b77; op2val:0x30b5; +op3val:0x3064; valaddr_reg:x1; val_offset:2568*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2568*FLEN/8, x4, x2, x6) + +inst_889: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x377 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0b5 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x064 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b77; op2val:0x30b5; +op3val:0x3064; valaddr_reg:x1; val_offset:2571*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2571*FLEN/8, x4, x2, x6) + +inst_890: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x05e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0d6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x149 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x385e; op2val:0x3cd6; +op3val:0x3949; valaddr_reg:x1; val_offset:2574*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2574*FLEN/8, x4, x2, x6) + +inst_891: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x05e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0d6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x149 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x385e; op2val:0x3cd6; +op3val:0x3949; valaddr_reg:x1; val_offset:2577*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2577*FLEN/8, x4, x2, x6) + +inst_892: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x05e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0d6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x149 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x385e; op2val:0x3cd6; +op3val:0x3949; valaddr_reg:x1; val_offset:2580*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2580*FLEN/8, x4, x2, x6) + +inst_893: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x05e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0d6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x149 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x385e; op2val:0x3cd6; +op3val:0x3949; valaddr_reg:x1; val_offset:2583*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2583*FLEN/8, x4, x2, x6) + +inst_894: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x05e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0d6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x149 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x385e; op2val:0x3cd6; +op3val:0x3949; valaddr_reg:x1; val_offset:2586*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2586*FLEN/8, x4, x2, x6) + +inst_895: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x326 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x142 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0b2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3726; op2val:0x3142; +op3val:0x2cb2; valaddr_reg:x1; val_offset:2589*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2589*FLEN/8, x4, x2, x6) + +inst_896: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x326 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x142 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0b2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3726; op2val:0x3142; +op3val:0x2cb2; valaddr_reg:x1; val_offset:2592*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2592*FLEN/8, x4, x2, x6) + +inst_897: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x326 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x142 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0b2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3726; op2val:0x3142; +op3val:0x2cb2; valaddr_reg:x1; val_offset:2595*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2595*FLEN/8, x4, x2, x6) + +inst_898: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x326 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x142 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0b2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3726; op2val:0x3142; +op3val:0x2cb2; valaddr_reg:x1; val_offset:2598*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2598*FLEN/8, x4, x2, x6) + +inst_899: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x326 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x142 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0b2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3726; op2val:0x3142; +op3val:0x2cb2; valaddr_reg:x1; val_offset:2601*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2601*FLEN/8, x4, x2, x6) + +inst_900: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1db and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0c1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2f7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39db; op2val:0x3cc1; +op3val:0x3af7; valaddr_reg:x1; val_offset:2604*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2604*FLEN/8, x4, x2, x6) + +inst_901: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1db and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0c1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2f7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39db; op2val:0x3cc1; +op3val:0x3af7; valaddr_reg:x1; val_offset:2607*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2607*FLEN/8, x4, x2, x6) + +inst_902: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1db and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0c1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2f7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39db; op2val:0x3cc1; +op3val:0x3af7; valaddr_reg:x1; val_offset:2610*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2610*FLEN/8, x4, x2, x6) + +inst_903: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1db and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0c1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2f7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39db; op2val:0x3cc1; +op3val:0x3af7; valaddr_reg:x1; val_offset:2613*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2613*FLEN/8, x4, x2, x6) + +inst_904: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1db and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0c1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2f7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39db; op2val:0x3cc1; +op3val:0x3af7; valaddr_reg:x1; val_offset:2616*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2616*FLEN/8, x4, x2, x6) + +inst_905: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x391 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x270 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x217 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3791; op2val:0x3e70; +op3val:0x3a17; valaddr_reg:x1; val_offset:2619*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2619*FLEN/8, x4, x2, x6) + +inst_906: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x391 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x270 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x217 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3791; op2val:0x3e70; +op3val:0x3a17; valaddr_reg:x1; val_offset:2622*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2622*FLEN/8, x4, x2, x6) + +inst_907: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x391 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x270 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x217 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3791; op2val:0x3e70; +op3val:0x3a17; valaddr_reg:x1; val_offset:2625*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2625*FLEN/8, x4, x2, x6) + +inst_908: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x391 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x270 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x217 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3791; op2val:0x3e70; +op3val:0x3a17; valaddr_reg:x1; val_offset:2628*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2628*FLEN/8, x4, x2, x6) + +inst_909: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x391 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x270 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x217 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3791; op2val:0x3e70; +op3val:0x3a17; valaddr_reg:x1; val_offset:2631*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2631*FLEN/8, x4, x2, x6) + +inst_910: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x388 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b1f; op2val:0x3b88; +op3val:0x3ab5; valaddr_reg:x1; val_offset:2634*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2634*FLEN/8, x4, x2, x6) + +inst_911: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x388 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b1f; op2val:0x3b88; +op3val:0x3ab5; valaddr_reg:x1; val_offset:2637*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2637*FLEN/8, x4, x2, x6) + +inst_912: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x388 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b1f; op2val:0x3b88; +op3val:0x3ab5; valaddr_reg:x1; val_offset:2640*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2640*FLEN/8, x4, x2, x6) + +inst_913: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x388 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b1f; op2val:0x3b88; +op3val:0x3ab5; valaddr_reg:x1; val_offset:2643*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2643*FLEN/8, x4, x2, x6) + +inst_914: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x388 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b1f; op2val:0x3b88; +op3val:0x3ab5; valaddr_reg:x1; val_offset:2646*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2646*FLEN/8, x4, x2, x6) + +inst_915: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x398 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2b9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x262 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b98; op2val:0x3ab9; +op3val:0x3a62; valaddr_reg:x1; val_offset:2649*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2649*FLEN/8, x4, x2, x6) + +inst_916: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x398 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2b9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x262 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b98; op2val:0x3ab9; +op3val:0x3a62; valaddr_reg:x1; val_offset:2652*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2652*FLEN/8, x4, x2, x6) + +inst_917: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x398 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2b9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x262 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b98; op2val:0x3ab9; +op3val:0x3a62; valaddr_reg:x1; val_offset:2655*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2655*FLEN/8, x4, x2, x6) + +inst_918: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x398 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2b9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x262 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b98; op2val:0x3ab9; +op3val:0x3a62; valaddr_reg:x1; val_offset:2658*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2658*FLEN/8, x4, x2, x6) + +inst_919: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x398 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2b9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x262 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b98; op2val:0x3ab9; +op3val:0x3a62; valaddr_reg:x1; val_offset:2661*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2661*FLEN/8, x4, x2, x6) + +inst_920: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x181 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x00a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x18f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3981; op2val:0x3c0a; +op3val:0x398f; valaddr_reg:x1; val_offset:2664*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2664*FLEN/8, x4, x2, x6) + +inst_921: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x181 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x00a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x18f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3981; op2val:0x3c0a; +op3val:0x398f; valaddr_reg:x1; val_offset:2667*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2667*FLEN/8, x4, x2, x6) + +inst_922: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x181 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x00a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x18f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3981; op2val:0x3c0a; +op3val:0x398f; valaddr_reg:x1; val_offset:2670*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2670*FLEN/8, x4, x2, x6) + +inst_923: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x181 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x00a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x18f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3981; op2val:0x3c0a; +op3val:0x398f; valaddr_reg:x1; val_offset:2673*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2673*FLEN/8, x4, x2, x6) +RVTEST_SIGBASE(x2,signature_x2_7) + +inst_924: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x181 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x00a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x18f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3981; op2val:0x3c0a; +op3val:0x398f; valaddr_reg:x1; val_offset:2676*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2676*FLEN/8, x4, x2, x6) + +inst_925: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3b2 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1e7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ae and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x33b2; op2val:0x41e7; +op3val:0x39ae; valaddr_reg:x1; val_offset:2679*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2679*FLEN/8, x4, x2, x6) + +inst_926: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3b2 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1e7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ae and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x33b2; op2val:0x41e7; +op3val:0x39ae; valaddr_reg:x1; val_offset:2682*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2682*FLEN/8, x4, x2, x6) + +inst_927: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3b2 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1e7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ae and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x33b2; op2val:0x41e7; +op3val:0x39ae; valaddr_reg:x1; val_offset:2685*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2685*FLEN/8, x4, x2, x6) + +inst_928: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3b2 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1e7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ae and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x33b2; op2val:0x41e7; +op3val:0x39ae; valaddr_reg:x1; val_offset:2688*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2688*FLEN/8, x4, x2, x6) + +inst_929: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3b2 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1e7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ae and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x33b2; op2val:0x41e7; +op3val:0x39ae; valaddr_reg:x1; val_offset:2691*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2691*FLEN/8, x4, x2, x6) + +inst_930: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x294 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x293 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37ff; op2val:0x3e94; +op3val:0x3a93; valaddr_reg:x1; val_offset:2694*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2694*FLEN/8, x4, x2, x6) + +inst_931: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x294 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x293 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37ff; op2val:0x3e94; +op3val:0x3a93; valaddr_reg:x1; val_offset:2697*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2697*FLEN/8, x4, x2, x6) + +inst_932: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x294 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x293 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37ff; op2val:0x3e94; +op3val:0x3a93; valaddr_reg:x1; val_offset:2700*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2700*FLEN/8, x4, x2, x6) + +inst_933: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x294 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x293 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37ff; op2val:0x3e94; +op3val:0x3a93; valaddr_reg:x1; val_offset:2703*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2703*FLEN/8, x4, x2, x6) + +inst_934: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x294 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x293 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37ff; op2val:0x3e94; +op3val:0x3a93; valaddr_reg:x1; val_offset:2706*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2706*FLEN/8, x4, x2, x6) + +inst_935: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x139 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x203 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3da and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3939; op2val:0x3e03; +op3val:0x3bda; valaddr_reg:x1; val_offset:2709*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2709*FLEN/8, x4, x2, x6) + +inst_936: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x139 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x203 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3da and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3939; op2val:0x3e03; +op3val:0x3bda; valaddr_reg:x1; val_offset:2712*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2712*FLEN/8, x4, x2, x6) + +inst_937: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x139 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x203 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3da and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3939; op2val:0x3e03; +op3val:0x3bda; valaddr_reg:x1; val_offset:2715*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2715*FLEN/8, x4, x2, x6) + +inst_938: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x139 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x203 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3da and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3939; op2val:0x3e03; +op3val:0x3bda; valaddr_reg:x1; val_offset:2718*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2718*FLEN/8, x4, x2, x6) + +inst_939: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x139 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x203 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3da and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3939; op2val:0x3e03; +op3val:0x3bda; valaddr_reg:x1; val_offset:2721*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2721*FLEN/8, x4, x2, x6) + +inst_940: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x141 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39ff; op2val:0x3d41; +op3val:0x3be0; valaddr_reg:x1; val_offset:2724*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2724*FLEN/8, x4, x2, x6) + +inst_941: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x141 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3e0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39ff; op2val:0x3d41; +op3val:0x3be0; valaddr_reg:x1; val_offset:2727*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2727*FLEN/8, x4, x2, x6) + +inst_942: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x141 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3e0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39ff; op2val:0x3d41; +op3val:0x3be0; valaddr_reg:x1; val_offset:2730*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2730*FLEN/8, x4, x2, x6) + +inst_943: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x141 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3e0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39ff; op2val:0x3d41; +op3val:0x3be0; valaddr_reg:x1; val_offset:2733*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2733*FLEN/8, x4, x2, x6) + +inst_944: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x141 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3e0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39ff; op2val:0x3d41; +op3val:0x3be0; valaddr_reg:x1; val_offset:2736*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2736*FLEN/8, x4, x2, x6) + +inst_945: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x045 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2ba and fs3 == 0 and fe3 == 0x0d and fm3 == 0x32f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3445; op2val:0x3eba; +op3val:0x372f; valaddr_reg:x1; val_offset:2739*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2739*FLEN/8, x4, x2, x6) + +inst_946: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x045 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2ba and fs3 == 0 and fe3 == 0x0d and fm3 == 0x32f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3445; op2val:0x3eba; +op3val:0x372f; valaddr_reg:x1; val_offset:2742*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2742*FLEN/8, x4, x2, x6) + +inst_947: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x045 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2ba and fs3 == 0 and fe3 == 0x0d and fm3 == 0x32f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3445; op2val:0x3eba; +op3val:0x372f; valaddr_reg:x1; val_offset:2745*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2745*FLEN/8, x4, x2, x6) + +inst_948: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x045 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2ba and fs3 == 0 and fe3 == 0x0d and fm3 == 0x32f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3445; op2val:0x3eba; +op3val:0x372f; valaddr_reg:x1; val_offset:2748*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2748*FLEN/8, x4, x2, x6) + +inst_949: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x045 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2ba and fs3 == 0 and fe3 == 0x0d and fm3 == 0x32f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3445; op2val:0x3eba; +op3val:0x372f; valaddr_reg:x1; val_offset:2751*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2751*FLEN/8, x4, x2, x6) + +inst_950: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x27c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x12f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x033 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a7c; op2val:0x392f; +op3val:0x3833; valaddr_reg:x1; val_offset:2754*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2754*FLEN/8, x4, x2, x6) + +inst_951: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x27c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x12f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x033 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a7c; op2val:0x392f; +op3val:0x3833; valaddr_reg:x1; val_offset:2757*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2757*FLEN/8, x4, x2, x6) + +inst_952: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x27c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x12f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x033 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a7c; op2val:0x392f; +op3val:0x3833; valaddr_reg:x1; val_offset:2760*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2760*FLEN/8, x4, x2, x6) + +inst_953: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x27c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x12f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x033 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a7c; op2val:0x392f; +op3val:0x3833; valaddr_reg:x1; val_offset:2763*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2763*FLEN/8, x4, x2, x6) + +inst_954: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x27c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x12f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x033 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a7c; op2val:0x392f; +op3val:0x3833; valaddr_reg:x1; val_offset:2766*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2766*FLEN/8, x4, x2, x6) + +inst_955: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x02f and fs2 == 0 and fe2 == 0x12 and fm2 == 0x2d4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x326 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2c2f; op2val:0x4ad4; +op3val:0x3b26; valaddr_reg:x1; val_offset:2769*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2769*FLEN/8, x4, x2, x6) + +inst_956: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x02f and fs2 == 0 and fe2 == 0x12 and fm2 == 0x2d4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x326 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2c2f; op2val:0x4ad4; +op3val:0x3b26; valaddr_reg:x1; val_offset:2772*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2772*FLEN/8, x4, x2, x6) + +inst_957: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x02f and fs2 == 0 and fe2 == 0x12 and fm2 == 0x2d4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x326 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2c2f; op2val:0x4ad4; +op3val:0x3b26; valaddr_reg:x1; val_offset:2775*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2775*FLEN/8, x4, x2, x6) + +inst_958: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x02f and fs2 == 0 and fe2 == 0x12 and fm2 == 0x2d4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x326 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2c2f; op2val:0x4ad4; +op3val:0x3b26; valaddr_reg:x1; val_offset:2778*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2778*FLEN/8, x4, x2, x6) + +inst_959: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x02f and fs2 == 0 and fe2 == 0x12 and fm2 == 0x2d4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x326 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2c2f; op2val:0x4ad4; +op3val:0x3b26; valaddr_reg:x1; val_offset:2781*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2781*FLEN/8, x4, x2, x6) + +inst_960: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1cb and fs2 == 0 and fe2 == 0x10 and fm2 == 0x245 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31cb; op2val:0x4245; +op3val:0x388a; valaddr_reg:x1; val_offset:2784*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2784*FLEN/8, x4, x2, x6) + +inst_961: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1cb and fs2 == 0 and fe2 == 0x10 and fm2 == 0x245 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31cb; op2val:0x4245; +op3val:0x388a; valaddr_reg:x1; val_offset:2787*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2787*FLEN/8, x4, x2, x6) + +inst_962: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1cb and fs2 == 0 and fe2 == 0x10 and fm2 == 0x245 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31cb; op2val:0x4245; +op3val:0x388a; valaddr_reg:x1; val_offset:2790*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2790*FLEN/8, x4, x2, x6) + +inst_963: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1cb and fs2 == 0 and fe2 == 0x10 and fm2 == 0x245 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31cb; op2val:0x4245; +op3val:0x388a; valaddr_reg:x1; val_offset:2793*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2793*FLEN/8, x4, x2, x6) + +inst_964: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1cb and fs2 == 0 and fe2 == 0x10 and fm2 == 0x245 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31cb; op2val:0x4245; +op3val:0x388a; valaddr_reg:x1; val_offset:2796*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2796*FLEN/8, x4, x2, x6) + +inst_965: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x00a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x13e and fs3 == 0 and fe3 == 0x0c and fm3 == 0x14b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x380a; op2val:0x353e; +op3val:0x314b; valaddr_reg:x1; val_offset:2799*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2799*FLEN/8, x4, x2, x6) + +inst_966: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x00a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x13e and fs3 == 0 and fe3 == 0x0c and fm3 == 0x14b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x380a; op2val:0x353e; +op3val:0x314b; valaddr_reg:x1; val_offset:2802*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2802*FLEN/8, x4, x2, x6) + +inst_967: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x00a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x13e and fs3 == 0 and fe3 == 0x0c and fm3 == 0x14b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x380a; op2val:0x353e; +op3val:0x314b; valaddr_reg:x1; val_offset:2805*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2805*FLEN/8, x4, x2, x6) + +inst_968: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x00a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x13e and fs3 == 0 and fe3 == 0x0c and fm3 == 0x14b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x380a; op2val:0x353e; +op3val:0x314b; valaddr_reg:x1; val_offset:2808*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2808*FLEN/8, x4, x2, x6) + +inst_969: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x00a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x13e and fs3 == 0 and fe3 == 0x0c and fm3 == 0x14b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x380a; op2val:0x353e; +op3val:0x314b; valaddr_reg:x1; val_offset:2811*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2811*FLEN/8, x4, x2, x6) + +inst_970: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0db and fs2 == 0 and fe2 == 0x0e and fm2 == 0x280 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3e4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38db; op2val:0x3a80; +op3val:0x37e4; valaddr_reg:x1; val_offset:2814*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2814*FLEN/8, x4, x2, x6) + +inst_971: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0db and fs2 == 0 and fe2 == 0x0e and fm2 == 0x280 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3e4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38db; op2val:0x3a80; +op3val:0x37e4; valaddr_reg:x1; val_offset:2817*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2817*FLEN/8, x4, x2, x6) + +inst_972: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0db and fs2 == 0 and fe2 == 0x0e and fm2 == 0x280 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3e4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38db; op2val:0x3a80; +op3val:0x37e4; valaddr_reg:x1; val_offset:2820*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2820*FLEN/8, x4, x2, x6) + +inst_973: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0db and fs2 == 0 and fe2 == 0x0e and fm2 == 0x280 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3e4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38db; op2val:0x3a80; +op3val:0x37e4; valaddr_reg:x1; val_offset:2823*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2823*FLEN/8, x4, x2, x6) + +inst_974: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0db and fs2 == 0 and fe2 == 0x0e and fm2 == 0x280 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3e4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38db; op2val:0x3a80; +op3val:0x37e4; valaddr_reg:x1; val_offset:2826*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2826*FLEN/8, x4, x2, x6) + +inst_975: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x0a and fm2 == 0x340 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x083 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34ff; op2val:0x2b40; +op3val:0x2483; valaddr_reg:x1; val_offset:2829*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2829*FLEN/8, x4, x2, x6) + +inst_976: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x0a and fm2 == 0x340 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x083 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34ff; op2val:0x2b40; +op3val:0x2483; valaddr_reg:x1; val_offset:2832*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2832*FLEN/8, x4, x2, x6) + +inst_977: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x0a and fm2 == 0x340 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x083 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34ff; op2val:0x2b40; +op3val:0x2483; valaddr_reg:x1; val_offset:2835*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2835*FLEN/8, x4, x2, x6) + +inst_978: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x0a and fm2 == 0x340 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x083 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34ff; op2val:0x2b40; +op3val:0x2483; valaddr_reg:x1; val_offset:2838*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2838*FLEN/8, x4, x2, x6) + +inst_979: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x0a and fm2 == 0x340 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x083 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34ff; op2val:0x2b40; +op3val:0x2483; valaddr_reg:x1; val_offset:2841*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2841*FLEN/8, x4, x2, x6) + +inst_980: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x142 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x015 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x15e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3942; op2val:0x3415; +op3val:0x315e; valaddr_reg:x1; val_offset:2844*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2844*FLEN/8, x4, x2, x6) + +inst_981: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x142 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x015 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x15e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3942; op2val:0x3415; +op3val:0x315e; valaddr_reg:x1; val_offset:2847*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2847*FLEN/8, x4, x2, x6) + +inst_982: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x142 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x015 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x15e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3942; op2val:0x3415; +op3val:0x315e; valaddr_reg:x1; val_offset:2850*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2850*FLEN/8, x4, x2, x6) + +inst_983: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x142 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x015 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x15e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3942; op2val:0x3415; +op3val:0x315e; valaddr_reg:x1; val_offset:2853*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2853*FLEN/8, x4, x2, x6) + +inst_984: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x142 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x015 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x15e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3942; op2val:0x3415; +op3val:0x315e; valaddr_reg:x1; val_offset:2856*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2856*FLEN/8, x4, x2, x6) + +inst_985: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0b1 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0f7 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1d3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34b1; op2val:0x3cf7; +op3val:0x35d3; valaddr_reg:x1; val_offset:2859*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2859*FLEN/8, x4, x2, x6) + +inst_986: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0b1 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0f7 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1d3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34b1; op2val:0x3cf7; +op3val:0x35d3; valaddr_reg:x1; val_offset:2862*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2862*FLEN/8, x4, x2, x6) + +inst_987: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0b1 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0f7 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1d3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34b1; op2val:0x3cf7; +op3val:0x35d3; valaddr_reg:x1; val_offset:2865*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2865*FLEN/8, x4, x2, x6) + +inst_988: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0b1 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0f7 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1d3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34b1; op2val:0x3cf7; +op3val:0x35d3; valaddr_reg:x1; val_offset:2868*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2868*FLEN/8, x4, x2, x6) + +inst_989: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0b1 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0f7 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1d3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34b1; op2val:0x3cf7; +op3val:0x35d3; valaddr_reg:x1; val_offset:2871*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2871*FLEN/8, x4, x2, x6) + +inst_990: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0c3 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x062 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x138 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38c3; op2val:0x3c62; +op3val:0x3938; valaddr_reg:x1; val_offset:2874*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2874*FLEN/8, x4, x2, x6) + +inst_991: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0c3 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x062 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x138 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38c3; op2val:0x3c62; +op3val:0x3938; valaddr_reg:x1; val_offset:2877*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2877*FLEN/8, x4, x2, x6) + +inst_992: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0c3 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x062 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x138 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38c3; op2val:0x3c62; +op3val:0x3938; valaddr_reg:x1; val_offset:2880*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2880*FLEN/8, x4, x2, x6) + +inst_993: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0c3 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x062 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x138 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38c3; op2val:0x3c62; +op3val:0x3938; valaddr_reg:x1; val_offset:2883*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2883*FLEN/8, x4, x2, x6) + +inst_994: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0c3 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x062 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x138 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38c3; op2val:0x3c62; +op3val:0x3938; valaddr_reg:x1; val_offset:2886*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2886*FLEN/8, x4, x2, x6) + +inst_995: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x390 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x35c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2f6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b90; op2val:0x3b5c; +op3val:0x3af6; valaddr_reg:x1; val_offset:2889*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2889*FLEN/8, x4, x2, x6) + +inst_996: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x390 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x35c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2f6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b90; op2val:0x3b5c; +op3val:0x3af6; valaddr_reg:x1; val_offset:2892*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2892*FLEN/8, x4, x2, x6) + +inst_997: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x390 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x35c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2f6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b90; op2val:0x3b5c; +op3val:0x3af6; valaddr_reg:x1; val_offset:2895*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2895*FLEN/8, x4, x2, x6) + +inst_998: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x390 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x35c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2f6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b90; op2val:0x3b5c; +op3val:0x3af6; valaddr_reg:x1; val_offset:2898*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2898*FLEN/8, x4, x2, x6) + +inst_999: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x390 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x35c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2f6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b90; op2val:0x3b5c; +op3val:0x3af6; valaddr_reg:x1; val_offset:2901*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2901*FLEN/8, x4, x2, x6) + +inst_1000: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36f and fs2 == 0 and fe2 == 0x0d and fm2 == 0x076 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x025 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b6f; op2val:0x3476; +op3val:0x3425; valaddr_reg:x1; val_offset:2904*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2904*FLEN/8, x4, x2, x6) + +inst_1001: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36f and fs2 == 0 and fe2 == 0x0d and fm2 == 0x076 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x025 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b6f; op2val:0x3476; +op3val:0x3425; valaddr_reg:x1; val_offset:2907*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2907*FLEN/8, x4, x2, x6) + +inst_1002: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36f and fs2 == 0 and fe2 == 0x0d and fm2 == 0x076 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x025 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b6f; op2val:0x3476; +op3val:0x3425; valaddr_reg:x1; val_offset:2910*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2910*FLEN/8, x4, x2, x6) + +inst_1003: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36f and fs2 == 0 and fe2 == 0x0d and fm2 == 0x076 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x025 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b6f; op2val:0x3476; +op3val:0x3425; valaddr_reg:x1; val_offset:2913*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2913*FLEN/8, x4, x2, x6) + +inst_1004: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36f and fs2 == 0 and fe2 == 0x0d and fm2 == 0x076 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x025 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b6f; op2val:0x3476; +op3val:0x3425; valaddr_reg:x1; val_offset:2916*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2916*FLEN/8, x4, x2, x6) + +inst_1005: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1f4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x07f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39f4; op2val:0x3c7f; +op3val:0x3ab1; valaddr_reg:x1; val_offset:2919*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2919*FLEN/8, x4, x2, x6) + +inst_1006: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1f4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x07f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39f4; op2val:0x3c7f; +op3val:0x3ab1; valaddr_reg:x1; val_offset:2922*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2922*FLEN/8, x4, x2, x6) + +inst_1007: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1f4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x07f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39f4; op2val:0x3c7f; +op3val:0x3ab1; valaddr_reg:x1; val_offset:2925*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2925*FLEN/8, x4, x2, x6) + +inst_1008: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1f4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x07f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39f4; op2val:0x3c7f; +op3val:0x3ab1; valaddr_reg:x1; val_offset:2928*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2928*FLEN/8, x4, x2, x6) + +inst_1009: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1f4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x07f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39f4; op2val:0x3c7f; +op3val:0x3ab1; valaddr_reg:x1; val_offset:2931*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2931*FLEN/8, x4, x2, x6) + +inst_1010: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x352 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x18d and fs3 == 0 and fe3 == 0x0c and fm3 == 0x114 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b52; op2val:0x318d; +op3val:0x3114; valaddr_reg:x1; val_offset:2934*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2934*FLEN/8, x4, x2, x6) + +inst_1011: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x352 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x18d and fs3 == 0 and fe3 == 0x0c and fm3 == 0x114 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b52; op2val:0x318d; +op3val:0x3114; valaddr_reg:x1; val_offset:2937*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2937*FLEN/8, x4, x2, x6) + +inst_1012: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x352 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x18d and fs3 == 0 and fe3 == 0x0c and fm3 == 0x114 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b52; op2val:0x318d; +op3val:0x3114; valaddr_reg:x1; val_offset:2940*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2940*FLEN/8, x4, x2, x6) + +inst_1013: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x352 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x18d and fs3 == 0 and fe3 == 0x0c and fm3 == 0x114 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b52; op2val:0x318d; +op3val:0x3114; valaddr_reg:x1; val_offset:2943*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2943*FLEN/8, x4, x2, x6) + +inst_1014: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x352 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x18d and fs3 == 0 and fe3 == 0x0c and fm3 == 0x114 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b52; op2val:0x318d; +op3val:0x3114; valaddr_reg:x1; val_offset:2946*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2946*FLEN/8, x4, x2, x6) + +inst_1015: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x025 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x116 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x145 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3025; op2val:0x4116; +op3val:0x3545; valaddr_reg:x1; val_offset:2949*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2949*FLEN/8, x4, x2, x6) + +inst_1016: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x025 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x116 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x145 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3025; op2val:0x4116; +op3val:0x3545; valaddr_reg:x1; val_offset:2952*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2952*FLEN/8, x4, x2, x6) + +inst_1017: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x025 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x116 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x145 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3025; op2val:0x4116; +op3val:0x3545; valaddr_reg:x1; val_offset:2955*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2955*FLEN/8, x4, x2, x6) + +inst_1018: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x025 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x116 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x145 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3025; op2val:0x4116; +op3val:0x3545; valaddr_reg:x1; val_offset:2958*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2958*FLEN/8, x4, x2, x6) + +inst_1019: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x025 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x116 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x145 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3025; op2val:0x4116; +op3val:0x3545; valaddr_reg:x1; val_offset:2961*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2961*FLEN/8, x4, x2, x6) + +inst_1020: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1be and fs2 == 0 and fe2 == 0x0f and fm2 == 0x038 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x20f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39be; op2val:0x3c38; +op3val:0x3a0f; valaddr_reg:x1; val_offset:2964*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2964*FLEN/8, x4, x2, x6) + +inst_1021: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1be and fs2 == 0 and fe2 == 0x0f and fm2 == 0x038 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x20f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39be; op2val:0x3c38; +op3val:0x3a0f; valaddr_reg:x1; val_offset:2967*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2967*FLEN/8, x4, x2, x6) + +inst_1022: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1be and fs2 == 0 and fe2 == 0x0f and fm2 == 0x038 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x20f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39be; op2val:0x3c38; +op3val:0x3a0f; valaddr_reg:x1; val_offset:2970*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2970*FLEN/8, x4, x2, x6) + +inst_1023: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1be and fs2 == 0 and fe2 == 0x0f and fm2 == 0x038 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x20f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39be; op2val:0x3c38; +op3val:0x3a0f; valaddr_reg:x1; val_offset:2973*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2973*FLEN/8, x4, x2, x6) + +inst_1024: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1be and fs2 == 0 and fe2 == 0x0f and fm2 == 0x038 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x20f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39be; op2val:0x3c38; +op3val:0x3a0f; valaddr_reg:x1; val_offset:2976*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2976*FLEN/8, x4, x2, x6) + +inst_1025: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x21e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x053 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39a7; op2val:0x3a1e; +op3val:0x3853; valaddr_reg:x1; val_offset:2979*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2979*FLEN/8, x4, x2, x6) + +inst_1026: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x21e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x053 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39a7; op2val:0x3a1e; +op3val:0x3853; valaddr_reg:x1; val_offset:2982*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2982*FLEN/8, x4, x2, x6) + +inst_1027: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x21e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x053 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39a7; op2val:0x3a1e; +op3val:0x3853; valaddr_reg:x1; val_offset:2985*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2985*FLEN/8, x4, x2, x6) + +inst_1028: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x21e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x053 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39a7; op2val:0x3a1e; +op3val:0x3853; valaddr_reg:x1; val_offset:2988*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2988*FLEN/8, x4, x2, x6) + +inst_1029: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x21e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x053 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39a7; op2val:0x3a1e; +op3val:0x3853; valaddr_reg:x1; val_offset:2991*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2991*FLEN/8, x4, x2, x6) + +inst_1030: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2bd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x143 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x06f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3abd; op2val:0x3943; +op3val:0x386f; valaddr_reg:x1; val_offset:2994*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2994*FLEN/8, x4, x2, x6) + +inst_1031: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2bd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x143 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x06f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3abd; op2val:0x3943; +op3val:0x386f; valaddr_reg:x1; val_offset:2997*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2997*FLEN/8, x4, x2, x6) + +inst_1032: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2bd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x143 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x06f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3abd; op2val:0x3943; +op3val:0x386f; valaddr_reg:x1; val_offset:3000*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3000*FLEN/8, x4, x2, x6) + +inst_1033: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2bd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x143 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x06f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3abd; op2val:0x3943; +op3val:0x386f; valaddr_reg:x1; val_offset:3003*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3003*FLEN/8, x4, x2, x6) + +inst_1034: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2bd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x143 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x06f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3abd; op2val:0x3943; +op3val:0x386f; valaddr_reg:x1; val_offset:3006*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3006*FLEN/8, x4, x2, x6) + +inst_1035: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1e4 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x2a9 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x0e6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39e4; op2val:0x2aa9; +op3val:0x28e6; valaddr_reg:x1; val_offset:3009*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3009*FLEN/8, x4, x2, x6) + +inst_1036: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1e4 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x2a9 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x0e6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39e4; op2val:0x2aa9; +op3val:0x28e6; valaddr_reg:x1; val_offset:3012*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3012*FLEN/8, x4, x2, x6) + +inst_1037: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1e4 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x2a9 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x0e6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39e4; op2val:0x2aa9; +op3val:0x28e6; valaddr_reg:x1; val_offset:3015*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3015*FLEN/8, x4, x2, x6) + +inst_1038: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1e4 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x2a9 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x0e6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39e4; op2val:0x2aa9; +op3val:0x28e6; valaddr_reg:x1; val_offset:3018*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3018*FLEN/8, x4, x2, x6) + +inst_1039: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1e4 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x2a9 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x0e6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39e4; op2val:0x2aa9; +op3val:0x28e6; valaddr_reg:x1; val_offset:3021*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3021*FLEN/8, x4, x2, x6) + +inst_1040: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x306 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x020 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x33f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2706; op2val:0x4c20; +op3val:0x373f; valaddr_reg:x1; val_offset:3024*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3024*FLEN/8, x4, x2, x6) + +inst_1041: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x306 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x020 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x33f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2706; op2val:0x4c20; +op3val:0x373f; valaddr_reg:x1; val_offset:3027*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3027*FLEN/8, x4, x2, x6) + +inst_1042: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x306 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x020 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x33f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2706; op2val:0x4c20; +op3val:0x373f; valaddr_reg:x1; val_offset:3030*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3030*FLEN/8, x4, x2, x6) + +inst_1043: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x306 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x020 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x33f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2706; op2val:0x4c20; +op3val:0x373f; valaddr_reg:x1; val_offset:3033*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3033*FLEN/8, x4, x2, x6) + +inst_1044: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x306 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x020 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x33f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2706; op2val:0x4c20; +op3val:0x373f; valaddr_reg:x1; val_offset:3036*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3036*FLEN/8, x4, x2, x6) + +inst_1045: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x20b and fs2 == 0 and fe2 == 0x0a and fm2 == 0x1d6 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x067 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a0b; op2val:0x29d6; +op3val:0x2867; valaddr_reg:x1; val_offset:3039*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3039*FLEN/8, x4, x2, x6) + +inst_1046: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x20b and fs2 == 0 and fe2 == 0x0a and fm2 == 0x1d6 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x067 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a0b; op2val:0x29d6; +op3val:0x2867; valaddr_reg:x1; val_offset:3042*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3042*FLEN/8, x4, x2, x6) + +inst_1047: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x20b and fs2 == 0 and fe2 == 0x0a and fm2 == 0x1d6 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x067 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a0b; op2val:0x29d6; +op3val:0x2867; valaddr_reg:x1; val_offset:3045*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3045*FLEN/8, x4, x2, x6) + +inst_1048: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x20b and fs2 == 0 and fe2 == 0x0a and fm2 == 0x1d6 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x067 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a0b; op2val:0x29d6; +op3val:0x2867; valaddr_reg:x1; val_offset:3048*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3048*FLEN/8, x4, x2, x6) + +inst_1049: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x20b and fs2 == 0 and fe2 == 0x0a and fm2 == 0x1d6 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x067 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a0b; op2val:0x29d6; +op3val:0x2867; valaddr_reg:x1; val_offset:3051*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3051*FLEN/8, x4, x2, x6) + +inst_1050: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x186 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x374 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x125 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3986; op2val:0x3b74; +op3val:0x3925; valaddr_reg:x1; val_offset:3054*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3054*FLEN/8, x4, x2, x6) + +inst_1051: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x186 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x374 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x125 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3986; op2val:0x3b74; +op3val:0x3925; valaddr_reg:x1; val_offset:3057*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3057*FLEN/8, x4, x2, x6) +RVTEST_SIGBASE(x2,signature_x2_8) + +inst_1052: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x186 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x374 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x125 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3986; op2val:0x3b74; +op3val:0x3925; valaddr_reg:x1; val_offset:3060*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3060*FLEN/8, x4, x2, x6) + +inst_1053: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x186 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x374 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x125 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3986; op2val:0x3b74; +op3val:0x3925; valaddr_reg:x1; val_offset:3063*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3063*FLEN/8, x4, x2, x6) + +inst_1054: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x186 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x374 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x125 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3986; op2val:0x3b74; +op3val:0x3925; valaddr_reg:x1; val_offset:3066*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3066*FLEN/8, x4, x2, x6) + +inst_1055: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3fd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0f3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0f2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bfd; op2val:0x38f3; +op3val:0x38f2; valaddr_reg:x1; val_offset:3069*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3069*FLEN/8, x4, x2, x6) + +inst_1056: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3fd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0f3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0f2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bfd; op2val:0x38f3; +op3val:0x38f2; valaddr_reg:x1; val_offset:3072*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3072*FLEN/8, x4, x2, x6) + +inst_1057: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3fd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0f3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0f2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bfd; op2val:0x38f3; +op3val:0x38f2; valaddr_reg:x1; val_offset:3075*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3075*FLEN/8, x4, x2, x6) + +inst_1058: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3fd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0f3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0f2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bfd; op2val:0x38f3; +op3val:0x38f2; valaddr_reg:x1; val_offset:3078*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3078*FLEN/8, x4, x2, x6) + +inst_1059: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3fd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0f3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0f2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bfd; op2val:0x38f3; +op3val:0x38f2; valaddr_reg:x1; val_offset:3081*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3081*FLEN/8, x4, x2, x6) + +inst_1060: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x033 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x392 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3f4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3833; op2val:0x3b92; +op3val:0x37f4; valaddr_reg:x1; val_offset:3084*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3084*FLEN/8, x4, x2, x6) + +inst_1061: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x033 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x392 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3f4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3833; op2val:0x3b92; +op3val:0x37f4; valaddr_reg:x1; val_offset:3087*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3087*FLEN/8, x4, x2, x6) + +inst_1062: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x033 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x392 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3f4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3833; op2val:0x3b92; +op3val:0x37f4; valaddr_reg:x1; val_offset:3090*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3090*FLEN/8, x4, x2, x6) + +inst_1063: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x033 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x392 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3f4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3833; op2val:0x3b92; +op3val:0x37f4; valaddr_reg:x1; val_offset:3093*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3093*FLEN/8, x4, x2, x6) + +inst_1064: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x033 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x392 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3f4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3833; op2val:0x3b92; +op3val:0x37f4; valaddr_reg:x1; val_offset:3096*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3096*FLEN/8, x4, x2, x6) + +inst_1065: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x264 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0f5 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3ec and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a64; op2val:0x38f5; +op3val:0x37ec; valaddr_reg:x1; val_offset:3099*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3099*FLEN/8, x4, x2, x6) + +inst_1066: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x264 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0f5 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3ec and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a64; op2val:0x38f5; +op3val:0x37ec; valaddr_reg:x1; val_offset:3102*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3102*FLEN/8, x4, x2, x6) + +inst_1067: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x264 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0f5 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3ec and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a64; op2val:0x38f5; +op3val:0x37ec; valaddr_reg:x1; val_offset:3105*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3105*FLEN/8, x4, x2, x6) + +inst_1068: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x264 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0f5 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3ec and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a64; op2val:0x38f5; +op3val:0x37ec; valaddr_reg:x1; val_offset:3108*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3108*FLEN/8, x4, x2, x6) + +inst_1069: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x264 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0f5 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3ec and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a64; op2val:0x38f5; +op3val:0x37ec; valaddr_reg:x1; val_offset:3111*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3111*FLEN/8, x4, x2, x6) + +inst_1070: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1ea and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bf5; op2val:0x39ea; +op3val:0x39e3; valaddr_reg:x1; val_offset:3114*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3114*FLEN/8, x4, x2, x6) + +inst_1071: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1ea and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bf5; op2val:0x39ea; +op3val:0x39e3; valaddr_reg:x1; val_offset:3117*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3117*FLEN/8, x4, x2, x6) + +inst_1072: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1ea and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bf5; op2val:0x39ea; +op3val:0x39e3; valaddr_reg:x1; val_offset:3120*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3120*FLEN/8, x4, x2, x6) + +inst_1073: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1ea and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bf5; op2val:0x39ea; +op3val:0x39e3; valaddr_reg:x1; val_offset:3123*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3123*FLEN/8, x4, x2, x6) + +inst_1074: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1ea and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bf5; op2val:0x39ea; +op3val:0x39e3; valaddr_reg:x1; val_offset:3126*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3126*FLEN/8, x4, x2, x6) + +inst_1075: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x348 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x147 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0cd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b48; op2val:0x3947; +op3val:0x38cd; valaddr_reg:x1; val_offset:3129*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3129*FLEN/8, x4, x2, x6) + +inst_1076: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x348 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x147 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0cd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b48; op2val:0x3947; +op3val:0x38cd; valaddr_reg:x1; val_offset:3132*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3132*FLEN/8, x4, x2, x6) + +inst_1077: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x348 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x147 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0cd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b48; op2val:0x3947; +op3val:0x38cd; valaddr_reg:x1; val_offset:3135*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3135*FLEN/8, x4, x2, x6) + +inst_1078: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x348 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x147 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0cd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b48; op2val:0x3947; +op3val:0x38cd; valaddr_reg:x1; val_offset:3138*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3138*FLEN/8, x4, x2, x6) + +inst_1079: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x348 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x147 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0cd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b48; op2val:0x3947; +op3val:0x38cd; valaddr_reg:x1; val_offset:3141*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3141*FLEN/8, x4, x2, x6) + +inst_1080: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3aa and fs2 == 0 and fe2 == 0x0f and fm2 == 0x014 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3d1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3baa; op2val:0x3c14; +op3val:0x3bd1; valaddr_reg:x1; val_offset:3144*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3144*FLEN/8, x4, x2, x6) + +inst_1081: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3aa and fs2 == 0 and fe2 == 0x0f and fm2 == 0x014 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3d1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3baa; op2val:0x3c14; +op3val:0x3bd1; valaddr_reg:x1; val_offset:3147*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3147*FLEN/8, x4, x2, x6) + +inst_1082: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3aa and fs2 == 0 and fe2 == 0x0f and fm2 == 0x014 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3d1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3baa; op2val:0x3c14; +op3val:0x3bd1; valaddr_reg:x1; val_offset:3150*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3150*FLEN/8, x4, x2, x6) + +inst_1083: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3aa and fs2 == 0 and fe2 == 0x0f and fm2 == 0x014 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3d1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3baa; op2val:0x3c14; +op3val:0x3bd1; valaddr_reg:x1; val_offset:3153*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3153*FLEN/8, x4, x2, x6) + +inst_1084: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3aa and fs2 == 0 and fe2 == 0x0f and fm2 == 0x014 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3d1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3baa; op2val:0x3c14; +op3val:0x3bd1; valaddr_reg:x1; val_offset:3156*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3156*FLEN/8, x4, x2, x6) + +inst_1085: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x190 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x069 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x223 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3990; op2val:0x3c69; +op3val:0x3a23; valaddr_reg:x1; val_offset:3159*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3159*FLEN/8, x4, x2, x6) + +inst_1086: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x190 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x069 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x223 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3990; op2val:0x3c69; +op3val:0x3a23; valaddr_reg:x1; val_offset:3162*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3162*FLEN/8, x4, x2, x6) + +inst_1087: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x190 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x069 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x223 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3990; op2val:0x3c69; +op3val:0x3a23; valaddr_reg:x1; val_offset:3165*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3165*FLEN/8, x4, x2, x6) + +inst_1088: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x190 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x069 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x223 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3990; op2val:0x3c69; +op3val:0x3a23; valaddr_reg:x1; val_offset:3168*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3168*FLEN/8, x4, x2, x6) + +inst_1089: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x190 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x069 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x223 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3990; op2val:0x3c69; +op3val:0x3a23; valaddr_reg:x1; val_offset:3171*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3171*FLEN/8, x4, x2, x6) + +inst_1090: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2a1 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x08b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x388 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36a1; op2val:0x3c8b; +op3val:0x3788; valaddr_reg:x1; val_offset:3174*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3174*FLEN/8, x4, x2, x6) + +inst_1091: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2a1 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x08b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x388 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36a1; op2val:0x3c8b; +op3val:0x3788; valaddr_reg:x1; val_offset:3177*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3177*FLEN/8, x4, x2, x6) + +inst_1092: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2a1 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x08b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x388 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36a1; op2val:0x3c8b; +op3val:0x3788; valaddr_reg:x1; val_offset:3180*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3180*FLEN/8, x4, x2, x6) + +inst_1093: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2a1 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x08b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x388 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36a1; op2val:0x3c8b; +op3val:0x3788; valaddr_reg:x1; val_offset:3183*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3183*FLEN/8, x4, x2, x6) + +inst_1094: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2a1 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x08b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x388 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36a1; op2val:0x3c8b; +op3val:0x3788; valaddr_reg:x1; val_offset:3186*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3186*FLEN/8, x4, x2, x6) + +inst_1095: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x0f and fm2 == 0x17d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x17a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x33fc; op2val:0x3d7d; +op3val:0x357a; valaddr_reg:x1; val_offset:3189*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3189*FLEN/8, x4, x2, x6) + +inst_1096: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x0f and fm2 == 0x17d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x17a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x33fc; op2val:0x3d7d; +op3val:0x357a; valaddr_reg:x1; val_offset:3192*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3192*FLEN/8, x4, x2, x6) + +inst_1097: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x0f and fm2 == 0x17d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x17a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x33fc; op2val:0x3d7d; +op3val:0x357a; valaddr_reg:x1; val_offset:3195*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3195*FLEN/8, x4, x2, x6) + +inst_1098: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x0f and fm2 == 0x17d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x17a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x33fc; op2val:0x3d7d; +op3val:0x357a; valaddr_reg:x1; val_offset:3198*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3198*FLEN/8, x4, x2, x6) + +inst_1099: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x0f and fm2 == 0x17d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x17a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x33fc; op2val:0x3d7d; +op3val:0x357a; valaddr_reg:x1; val_offset:3201*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3201*FLEN/8, x4, x2, x6) + +inst_1100: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x08b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2d1 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x3be and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x348b; op2val:0x36d1; +op3val:0x2fbe; valaddr_reg:x1; val_offset:3204*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3204*FLEN/8, x4, x2, x6) + +inst_1101: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x08b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2d1 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x3be and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x348b; op2val:0x36d1; +op3val:0x2fbe; valaddr_reg:x1; val_offset:3207*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3207*FLEN/8, x4, x2, x6) + +inst_1102: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x08b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2d1 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x3be and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x348b; op2val:0x36d1; +op3val:0x2fbe; valaddr_reg:x1; val_offset:3210*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3210*FLEN/8, x4, x2, x6) + +inst_1103: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x08b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2d1 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x3be and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x348b; op2val:0x36d1; +op3val:0x2fbe; valaddr_reg:x1; val_offset:3213*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3213*FLEN/8, x4, x2, x6) + +inst_1104: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x08b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2d1 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x3be and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x348b; op2val:0x36d1; +op3val:0x2fbe; valaddr_reg:x1; val_offset:3216*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3216*FLEN/8, x4, x2, x6) + +inst_1105: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e2 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x06a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x164 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38e2; op2val:0x3c6a; +op3val:0x3964; valaddr_reg:x1; val_offset:3219*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3219*FLEN/8, x4, x2, x6) + +inst_1106: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e2 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x06a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x164 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38e2; op2val:0x3c6a; +op3val:0x3964; valaddr_reg:x1; val_offset:3222*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3222*FLEN/8, x4, x2, x6) + +inst_1107: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e2 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x06a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x164 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38e2; op2val:0x3c6a; +op3val:0x3964; valaddr_reg:x1; val_offset:3225*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3225*FLEN/8, x4, x2, x6) + +inst_1108: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e2 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x06a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x164 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38e2; op2val:0x3c6a; +op3val:0x3964; valaddr_reg:x1; val_offset:3228*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3228*FLEN/8, x4, x2, x6) + +inst_1109: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e2 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x06a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x164 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38e2; op2val:0x3c6a; +op3val:0x3964; valaddr_reg:x1; val_offset:3231*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3231*FLEN/8, x4, x2, x6) + +inst_1110: +// fs1 == 0 and fe1 == 0x08 and fm1 == 0x3da and fs2 == 0 and fe2 == 0x14 and fm2 == 0x2ee and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2cd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x23da; op2val:0x52ee; +op3val:0x3acd; valaddr_reg:x1; val_offset:3234*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3234*FLEN/8, x4, x2, x6) + +inst_1111: +// fs1 == 0 and fe1 == 0x08 and fm1 == 0x3da and fs2 == 0 and fe2 == 0x14 and fm2 == 0x2ee and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2cd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x23da; op2val:0x52ee; +op3val:0x3acd; valaddr_reg:x1; val_offset:3237*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3237*FLEN/8, x4, x2, x6) + +inst_1112: +// fs1 == 0 and fe1 == 0x08 and fm1 == 0x3da and fs2 == 0 and fe2 == 0x14 and fm2 == 0x2ee and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2cd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x23da; op2val:0x52ee; +op3val:0x3acd; valaddr_reg:x1; val_offset:3240*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3240*FLEN/8, x4, x2, x6) + +inst_1113: +// fs1 == 0 and fe1 == 0x08 and fm1 == 0x3da and fs2 == 0 and fe2 == 0x14 and fm2 == 0x2ee and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2cd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x23da; op2val:0x52ee; +op3val:0x3acd; valaddr_reg:x1; val_offset:3243*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3243*FLEN/8, x4, x2, x6) + +inst_1114: +// fs1 == 0 and fe1 == 0x08 and fm1 == 0x3da and fs2 == 0 and fe2 == 0x14 and fm2 == 0x2ee and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2cd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x23da; op2val:0x52ee; +op3val:0x3acd; valaddr_reg:x1; val_offset:3246*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3246*FLEN/8, x4, x2, x6) + +inst_1115: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x06a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x12c and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1b5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x346a; op2val:0x3d2c; +op3val:0x35b5; valaddr_reg:x1; val_offset:3249*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3249*FLEN/8, x4, x2, x6) + +inst_1116: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x06a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x12c and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1b5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x346a; op2val:0x3d2c; +op3val:0x35b5; valaddr_reg:x1; val_offset:3252*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3252*FLEN/8, x4, x2, x6) + +inst_1117: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x06a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x12c and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1b5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x346a; op2val:0x3d2c; +op3val:0x35b5; valaddr_reg:x1; val_offset:3255*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3255*FLEN/8, x4, x2, x6) + +inst_1118: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x06a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x12c and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1b5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x346a; op2val:0x3d2c; +op3val:0x35b5; valaddr_reg:x1; val_offset:3258*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3258*FLEN/8, x4, x2, x6) + +inst_1119: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x06a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x12c and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1b5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x346a; op2val:0x3d2c; +op3val:0x35b5; valaddr_reg:x1; val_offset:3261*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3261*FLEN/8, x4, x2, x6) + +inst_1120: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3a6 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x184 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x145 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ba6; op2val:0x3184; +op3val:0x3145; valaddr_reg:x1; val_offset:3264*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3264*FLEN/8, x4, x2, x6) + +inst_1121: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3a6 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x184 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x145 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ba6; op2val:0x3184; +op3val:0x3145; valaddr_reg:x1; val_offset:3267*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3267*FLEN/8, x4, x2, x6) + +inst_1122: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3a6 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x184 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x145 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ba6; op2val:0x3184; +op3val:0x3145; valaddr_reg:x1; val_offset:3270*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3270*FLEN/8, x4, x2, x6) + +inst_1123: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3a6 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x184 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x145 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ba6; op2val:0x3184; +op3val:0x3145; valaddr_reg:x1; val_offset:3273*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3273*FLEN/8, x4, x2, x6) + +inst_1124: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3a6 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x184 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x145 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ba6; op2val:0x3184; +op3val:0x3145; valaddr_reg:x1; val_offset:3276*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3276*FLEN/8, x4, x2, x6) + +inst_1125: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2eb and fs2 == 0 and fe2 == 0x10 and fm2 == 0x2e5 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1f6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2eeb; op2val:0x42e5; +op3val:0x35f6; valaddr_reg:x1; val_offset:3279*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3279*FLEN/8, x4, x2, x6) + +inst_1126: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2eb and fs2 == 0 and fe2 == 0x10 and fm2 == 0x2e5 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1f6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2eeb; op2val:0x42e5; +op3val:0x35f6; valaddr_reg:x1; val_offset:3282*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3282*FLEN/8, x4, x2, x6) + +inst_1127: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2eb and fs2 == 0 and fe2 == 0x10 and fm2 == 0x2e5 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1f6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2eeb; op2val:0x42e5; +op3val:0x35f6; valaddr_reg:x1; val_offset:3285*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3285*FLEN/8, x4, x2, x6) + +inst_1128: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2eb and fs2 == 0 and fe2 == 0x10 and fm2 == 0x2e5 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1f6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2eeb; op2val:0x42e5; +op3val:0x35f6; valaddr_reg:x1; val_offset:3288*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3288*FLEN/8, x4, x2, x6) + +inst_1129: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2eb and fs2 == 0 and fe2 == 0x10 and fm2 == 0x2e5 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1f6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2eeb; op2val:0x42e5; +op3val:0x35f6; valaddr_reg:x1; val_offset:3291*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3291*FLEN/8, x4, x2, x6) + +inst_1130: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x042 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1a5 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x202 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3442; op2val:0x39a5; +op3val:0x3202; valaddr_reg:x1; val_offset:3294*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3294*FLEN/8, x4, x2, x6) + +inst_1131: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x042 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1a5 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x202 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3442; op2val:0x39a5; +op3val:0x3202; valaddr_reg:x1; val_offset:3297*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3297*FLEN/8, x4, x2, x6) + +inst_1132: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x042 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1a5 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x202 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3442; op2val:0x39a5; +op3val:0x3202; valaddr_reg:x1; val_offset:3300*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3300*FLEN/8, x4, x2, x6) + +inst_1133: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x042 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1a5 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x202 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3442; op2val:0x39a5; +op3val:0x3202; valaddr_reg:x1; val_offset:3303*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3303*FLEN/8, x4, x2, x6) + +inst_1134: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x042 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1a5 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x202 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3442; op2val:0x39a5; +op3val:0x3202; valaddr_reg:x1; val_offset:3306*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3306*FLEN/8, x4, x2, x6) + +inst_1135: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2e2 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x06d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x39e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ae2; op2val:0x386d; +op3val:0x379e; valaddr_reg:x1; val_offset:3309*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3309*FLEN/8, x4, x2, x6) + +inst_1136: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2e2 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x06d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x39e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ae2; op2val:0x386d; +op3val:0x379e; valaddr_reg:x1; val_offset:3312*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3312*FLEN/8, x4, x2, x6) + +inst_1137: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2e2 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x06d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x39e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ae2; op2val:0x386d; +op3val:0x379e; valaddr_reg:x1; val_offset:3315*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3315*FLEN/8, x4, x2, x6) + +inst_1138: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2e2 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x06d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x39e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ae2; op2val:0x386d; +op3val:0x379e; valaddr_reg:x1; val_offset:3318*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3318*FLEN/8, x4, x2, x6) + +inst_1139: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2e2 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x06d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x39e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ae2; op2val:0x386d; +op3val:0x379e; valaddr_reg:x1; val_offset:3321*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3321*FLEN/8, x4, x2, x6) + +inst_1140: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ee and fs2 == 0 and fe2 == 0x0d and fm2 == 0x155 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x148 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37ee; op2val:0x3555; +op3val:0x3148; valaddr_reg:x1; val_offset:3324*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3324*FLEN/8, x4, x2, x6) + +inst_1141: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ee and fs2 == 0 and fe2 == 0x0d and fm2 == 0x155 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x148 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37ee; op2val:0x3555; +op3val:0x3148; valaddr_reg:x1; val_offset:3327*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3327*FLEN/8, x4, x2, x6) + +inst_1142: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ee and fs2 == 0 and fe2 == 0x0d and fm2 == 0x155 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x148 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37ee; op2val:0x3555; +op3val:0x3148; valaddr_reg:x1; val_offset:3330*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3330*FLEN/8, x4, x2, x6) + +inst_1143: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ee and fs2 == 0 and fe2 == 0x0d and fm2 == 0x155 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x148 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37ee; op2val:0x3555; +op3val:0x3148; valaddr_reg:x1; val_offset:3333*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3333*FLEN/8, x4, x2, x6) + +inst_1144: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ee and fs2 == 0 and fe2 == 0x0d and fm2 == 0x155 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x148 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37ee; op2val:0x3555; +op3val:0x3148; valaddr_reg:x1; val_offset:3336*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3336*FLEN/8, x4, x2, x6) + +inst_1145: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x240 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x31c and fs3 == 0 and fe3 == 0x0c and fm3 == 0x18e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3240; op2val:0x3b1c; +op3val:0x318e; valaddr_reg:x1; val_offset:3339*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3339*FLEN/8, x4, x2, x6) + +inst_1146: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x240 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x31c and fs3 == 0 and fe3 == 0x0c and fm3 == 0x18e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3240; op2val:0x3b1c; +op3val:0x318e; valaddr_reg:x1; val_offset:3342*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3342*FLEN/8, x4, x2, x6) + +inst_1147: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x240 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x31c and fs3 == 0 and fe3 == 0x0c and fm3 == 0x18e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3240; op2val:0x3b1c; +op3val:0x318e; valaddr_reg:x1; val_offset:3345*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3345*FLEN/8, x4, x2, x6) + +inst_1148: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x240 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x31c and fs3 == 0 and fe3 == 0x0c and fm3 == 0x18e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3240; op2val:0x3b1c; +op3val:0x318e; valaddr_reg:x1; val_offset:3348*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3348*FLEN/8, x4, x2, x6) + +inst_1149: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x240 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x31c and fs3 == 0 and fe3 == 0x0c and fm3 == 0x18e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3240; op2val:0x3b1c; +op3val:0x318e; valaddr_reg:x1; val_offset:3351*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3351*FLEN/8, x4, x2, x6) + +inst_1150: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2a7 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x020 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x2dc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36a7; op2val:0x3420; +op3val:0x2edc; valaddr_reg:x1; val_offset:3354*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3354*FLEN/8, x4, x2, x6) + +inst_1151: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2a7 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x020 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x2dc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36a7; op2val:0x3420; +op3val:0x2edc; valaddr_reg:x1; val_offset:3357*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3357*FLEN/8, x4, x2, x6) + +inst_1152: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2a7 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x020 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x2dc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36a7; op2val:0x3420; +op3val:0x2edc; valaddr_reg:x1; val_offset:3360*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3360*FLEN/8, x4, x2, x6) + +inst_1153: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2a7 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x020 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x2dc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36a7; op2val:0x3420; +op3val:0x2edc; valaddr_reg:x1; val_offset:3363*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3363*FLEN/8, x4, x2, x6) + +inst_1154: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2a7 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x020 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x2dc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36a7; op2val:0x3420; +op3val:0x2edc; valaddr_reg:x1; val_offset:3366*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3366*FLEN/8, x4, x2, x6) + +inst_1155: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x113 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3bd and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0e8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3513; op2val:0x3bbd; +op3val:0x34e8; valaddr_reg:x1; val_offset:3369*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3369*FLEN/8, x4, x2, x6) + +inst_1156: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x113 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3bd and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0e8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3513; op2val:0x3bbd; +op3val:0x34e8; valaddr_reg:x1; val_offset:3372*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3372*FLEN/8, x4, x2, x6) + +inst_1157: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x113 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3bd and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0e8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3513; op2val:0x3bbd; +op3val:0x34e8; valaddr_reg:x1; val_offset:3375*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3375*FLEN/8, x4, x2, x6) + +inst_1158: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x113 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3bd and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0e8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3513; op2val:0x3bbd; +op3val:0x34e8; valaddr_reg:x1; val_offset:3378*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3378*FLEN/8, x4, x2, x6) + +inst_1159: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x113 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3bd and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0e8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3513; op2val:0x3bbd; +op3val:0x34e8; valaddr_reg:x1; val_offset:3381*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3381*FLEN/8, x4, x2, x6) + +inst_1160: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x229 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x108 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a29; op2val:0x3d08; +op3val:0x3bc0; valaddr_reg:x1; val_offset:3384*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3384*FLEN/8, x4, x2, x6) + +inst_1161: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x229 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x108 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3c0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a29; op2val:0x3d08; +op3val:0x3bc0; valaddr_reg:x1; val_offset:3387*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3387*FLEN/8, x4, x2, x6) + +inst_1162: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x229 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x108 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3c0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a29; op2val:0x3d08; +op3val:0x3bc0; valaddr_reg:x1; val_offset:3390*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3390*FLEN/8, x4, x2, x6) + +inst_1163: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x229 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x108 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3c0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a29; op2val:0x3d08; +op3val:0x3bc0; valaddr_reg:x1; val_offset:3393*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3393*FLEN/8, x4, x2, x6) + +inst_1164: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x229 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x108 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3c0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a29; op2val:0x3d08; +op3val:0x3bc0; valaddr_reg:x1; val_offset:3396*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3396*FLEN/8, x4, x2, x6) + +inst_1165: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ef and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1e6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x11d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aef; op2val:0x39e6; +op3val:0x391d; valaddr_reg:x1; val_offset:3399*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3399*FLEN/8, x4, x2, x6) + +inst_1166: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ef and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1e6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x11d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aef; op2val:0x39e6; +op3val:0x391d; valaddr_reg:x1; val_offset:3402*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3402*FLEN/8, x4, x2, x6) + +inst_1167: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ef and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1e6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x11d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aef; op2val:0x39e6; +op3val:0x391d; valaddr_reg:x1; val_offset:3405*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3405*FLEN/8, x4, x2, x6) + +inst_1168: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ef and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1e6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x11d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aef; op2val:0x39e6; +op3val:0x391d; valaddr_reg:x1; val_offset:3408*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3408*FLEN/8, x4, x2, x6) + +inst_1169: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ef and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1e6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x11d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aef; op2val:0x39e6; +op3val:0x391d; valaddr_reg:x1; val_offset:3411*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3411*FLEN/8, x4, x2, x6) + +inst_1170: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x329 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1df and fs3 == 0 and fe3 == 0x0c and fm3 == 0x141 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b29; op2val:0x31df; +op3val:0x3141; valaddr_reg:x1; val_offset:3414*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3414*FLEN/8, x4, x2, x6) + +inst_1171: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x329 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1df and fs3 == 0 and fe3 == 0x0c and fm3 == 0x141 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b29; op2val:0x31df; +op3val:0x3141; valaddr_reg:x1; val_offset:3417*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3417*FLEN/8, x4, x2, x6) + +inst_1172: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x329 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1df and fs3 == 0 and fe3 == 0x0c and fm3 == 0x141 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b29; op2val:0x31df; +op3val:0x3141; valaddr_reg:x1; val_offset:3420*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3420*FLEN/8, x4, x2, x6) + +inst_1173: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x329 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1df and fs3 == 0 and fe3 == 0x0c and fm3 == 0x141 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b29; op2val:0x31df; +op3val:0x3141; valaddr_reg:x1; val_offset:3423*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3423*FLEN/8, x4, x2, x6) + +inst_1174: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x329 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1df and fs3 == 0 and fe3 == 0x0c and fm3 == 0x141 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b29; op2val:0x31df; +op3val:0x3141; valaddr_reg:x1; val_offset:3426*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3426*FLEN/8, x4, x2, x6) + +inst_1175: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x310 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2bf and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1f4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3710; op2val:0x3abf; +op3val:0x35f4; valaddr_reg:x1; val_offset:3429*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3429*FLEN/8, x4, x2, x6) + +inst_1176: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x310 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2bf and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1f4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3710; op2val:0x3abf; +op3val:0x35f4; valaddr_reg:x1; val_offset:3432*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3432*FLEN/8, x4, x2, x6) + +inst_1177: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x310 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2bf and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1f4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3710; op2val:0x3abf; +op3val:0x35f4; valaddr_reg:x1; val_offset:3435*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3435*FLEN/8, x4, x2, x6) + +inst_1178: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x310 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2bf and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1f4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3710; op2val:0x3abf; +op3val:0x35f4; valaddr_reg:x1; val_offset:3438*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3438*FLEN/8, x4, x2, x6) + +inst_1179: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x310 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2bf and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1f4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3710; op2val:0x3abf; +op3val:0x35f4; valaddr_reg:x1; val_offset:3441*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3441*FLEN/8, x4, x2, x6) +RVTEST_SIGBASE(x2,signature_x2_9) + +inst_1180: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1fb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d6 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x11c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35fb; op2val:0x3ad6; +op3val:0x351c; valaddr_reg:x1; val_offset:3444*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3444*FLEN/8, x4, x2, x6) + +inst_1181: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1fb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d6 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x11c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35fb; op2val:0x3ad6; +op3val:0x351c; valaddr_reg:x1; val_offset:3447*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3447*FLEN/8, x4, x2, x6) + +inst_1182: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1fb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d6 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x11c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35fb; op2val:0x3ad6; +op3val:0x351c; valaddr_reg:x1; val_offset:3450*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3450*FLEN/8, x4, x2, x6) + +inst_1183: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1fb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d6 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x11c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35fb; op2val:0x3ad6; +op3val:0x351c; valaddr_reg:x1; val_offset:3453*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3453*FLEN/8, x4, x2, x6) + +inst_1184: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1fb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d6 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x11c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35fb; op2val:0x3ad6; +op3val:0x351c; valaddr_reg:x1; val_offset:3456*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3456*FLEN/8, x4, x2, x6) + +inst_1185: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x015 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3ce and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3f9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3815; op2val:0x3fce; +op3val:0x3bf9; valaddr_reg:x1; val_offset:3459*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3459*FLEN/8, x4, x2, x6) + +inst_1186: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x015 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3ce and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3f9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3815; op2val:0x3fce; +op3val:0x3bf9; valaddr_reg:x1; val_offset:3462*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3462*FLEN/8, x4, x2, x6) + +inst_1187: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x015 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3ce and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3f9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3815; op2val:0x3fce; +op3val:0x3bf9; valaddr_reg:x1; val_offset:3465*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3465*FLEN/8, x4, x2, x6) + +inst_1188: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x015 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3ce and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3f9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3815; op2val:0x3fce; +op3val:0x3bf9; valaddr_reg:x1; val_offset:3468*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3468*FLEN/8, x4, x2, x6) + +inst_1189: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x015 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3ce and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3f9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3815; op2val:0x3fce; +op3val:0x3bf9; valaddr_reg:x1; val_offset:3471*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3471*FLEN/8, x4, x2, x6) + +inst_1190: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x279 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0fa and fs3 == 0 and fe3 == 0x0d and fm3 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3279; op2val:0x3cfa; +op3val:0x3407; valaddr_reg:x1; val_offset:3474*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3474*FLEN/8, x4, x2, x6) + +inst_1191: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x279 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0fa and fs3 == 0 and fe3 == 0x0d and fm3 == 0x007 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3279; op2val:0x3cfa; +op3val:0x3407; valaddr_reg:x1; val_offset:3477*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3477*FLEN/8, x4, x2, x6) + +inst_1192: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x279 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0fa and fs3 == 0 and fe3 == 0x0d and fm3 == 0x007 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3279; op2val:0x3cfa; +op3val:0x3407; valaddr_reg:x1; val_offset:3480*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3480*FLEN/8, x4, x2, x6) + +inst_1193: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x279 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0fa and fs3 == 0 and fe3 == 0x0d and fm3 == 0x007 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3279; op2val:0x3cfa; +op3val:0x3407; valaddr_reg:x1; val_offset:3483*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3483*FLEN/8, x4, x2, x6) + +inst_1194: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x279 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0fa and fs3 == 0 and fe3 == 0x0d and fm3 == 0x007 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3279; op2val:0x3cfa; +op3val:0x3407; valaddr_reg:x1; val_offset:3486*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3486*FLEN/8, x4, x2, x6) + +inst_1195: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3f3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x37b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x36f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37f3; op2val:0x3b7b; +op3val:0x376f; valaddr_reg:x1; val_offset:3489*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3489*FLEN/8, x4, x2, x6) + +inst_1196: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3f3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x37b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x36f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37f3; op2val:0x3b7b; +op3val:0x376f; valaddr_reg:x1; val_offset:3492*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3492*FLEN/8, x4, x2, x6) + +inst_1197: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3f3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x37b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x36f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37f3; op2val:0x3b7b; +op3val:0x376f; valaddr_reg:x1; val_offset:3495*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3495*FLEN/8, x4, x2, x6) + +inst_1198: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3f3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x37b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x36f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37f3; op2val:0x3b7b; +op3val:0x376f; valaddr_reg:x1; val_offset:3498*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3498*FLEN/8, x4, x2, x6) + +inst_1199: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3f3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x37b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x36f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37f3; op2val:0x3b7b; +op3val:0x376f; valaddr_reg:x1; val_offset:3501*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3501*FLEN/8, x4, x2, x6) + +inst_1200: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x173 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x17b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x378 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3573; op2val:0x417b; +op3val:0x3b78; valaddr_reg:x1; val_offset:3504*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3504*FLEN/8, x4, x2, x6) + +inst_1201: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x173 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x17b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x378 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3573; op2val:0x417b; +op3val:0x3b78; valaddr_reg:x1; val_offset:3507*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3507*FLEN/8, x4, x2, x6) + +inst_1202: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x173 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x17b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x378 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3573; op2val:0x417b; +op3val:0x3b78; valaddr_reg:x1; val_offset:3510*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3510*FLEN/8, x4, x2, x6) + +inst_1203: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x173 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x17b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x378 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3573; op2val:0x417b; +op3val:0x3b78; valaddr_reg:x1; val_offset:3513*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3513*FLEN/8, x4, x2, x6) + +inst_1204: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x173 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x17b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x378 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3573; op2val:0x417b; +op3val:0x3b78; valaddr_reg:x1; val_offset:3516*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3516*FLEN/8, x4, x2, x6) + +inst_1205: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x036 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1ae and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1fb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3436; op2val:0x41ae; +op3val:0x39fb; valaddr_reg:x1; val_offset:3519*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3519*FLEN/8, x4, x2, x6) + +inst_1206: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x036 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1ae and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1fb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3436; op2val:0x41ae; +op3val:0x39fb; valaddr_reg:x1; val_offset:3522*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3522*FLEN/8, x4, x2, x6) + +inst_1207: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x036 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1ae and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1fb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3436; op2val:0x41ae; +op3val:0x39fb; valaddr_reg:x1; val_offset:3525*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3525*FLEN/8, x4, x2, x6) + +inst_1208: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x036 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1ae and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1fb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3436; op2val:0x41ae; +op3val:0x39fb; valaddr_reg:x1; val_offset:3528*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3528*FLEN/8, x4, x2, x6) + +inst_1209: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x036 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1ae and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1fb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3436; op2val:0x41ae; +op3val:0x39fb; valaddr_reg:x1; val_offset:3531*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3531*FLEN/8, x4, x2, x6) + +inst_1210: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x367 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x259 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b67; op2val:0x3a59; +op3val:0x39e0; valaddr_reg:x1; val_offset:3534*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3534*FLEN/8, x4, x2, x6) + +inst_1211: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x367 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x259 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b67; op2val:0x3a59; +op3val:0x39e0; valaddr_reg:x1; val_offset:3537*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3537*FLEN/8, x4, x2, x6) + +inst_1212: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x367 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x259 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b67; op2val:0x3a59; +op3val:0x39e0; valaddr_reg:x1; val_offset:3540*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3540*FLEN/8, x4, x2, x6) + +inst_1213: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x367 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x259 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b67; op2val:0x3a59; +op3val:0x39e0; valaddr_reg:x1; val_offset:3543*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3543*FLEN/8, x4, x2, x6) + +inst_1214: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x367 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x259 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b67; op2val:0x3a59; +op3val:0x39e0; valaddr_reg:x1; val_offset:3546*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3546*FLEN/8, x4, x2, x6) + +inst_1215: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x054 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1df and fs3 == 0 and fe3 == 0x0e and fm3 == 0x25b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3454; op2val:0x41df; +op3val:0x3a5b; valaddr_reg:x1; val_offset:3549*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3549*FLEN/8, x4, x2, x6) + +inst_1216: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x054 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1df and fs3 == 0 and fe3 == 0x0e and fm3 == 0x25b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3454; op2val:0x41df; +op3val:0x3a5b; valaddr_reg:x1; val_offset:3552*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3552*FLEN/8, x4, x2, x6) + +inst_1217: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x054 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1df and fs3 == 0 and fe3 == 0x0e and fm3 == 0x25b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3454; op2val:0x41df; +op3val:0x3a5b; valaddr_reg:x1; val_offset:3555*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3555*FLEN/8, x4, x2, x6) + +inst_1218: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x054 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1df and fs3 == 0 and fe3 == 0x0e and fm3 == 0x25b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3454; op2val:0x41df; +op3val:0x3a5b; valaddr_reg:x1; val_offset:3558*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3558*FLEN/8, x4, x2, x6) + +inst_1219: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x054 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1df and fs3 == 0 and fe3 == 0x0e and fm3 == 0x25b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3454; op2val:0x41df; +op3val:0x3a5b; valaddr_reg:x1; val_offset:3561*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3561*FLEN/8, x4, x2, x6) + +inst_1220: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x029 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x200 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x23a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3429; op2val:0x2e00; +op3val:0x263a; valaddr_reg:x1; val_offset:3564*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3564*FLEN/8, x4, x2, x6) + +inst_1221: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x029 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x200 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x23a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3429; op2val:0x2e00; +op3val:0x263a; valaddr_reg:x1; val_offset:3567*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3567*FLEN/8, x4, x2, x6) + +inst_1222: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x029 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x200 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x23a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3429; op2val:0x2e00; +op3val:0x263a; valaddr_reg:x1; val_offset:3570*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3570*FLEN/8, x4, x2, x6) + +inst_1223: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x029 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x200 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x23a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3429; op2val:0x2e00; +op3val:0x263a; valaddr_reg:x1; val_offset:3573*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3573*FLEN/8, x4, x2, x6) + +inst_1224: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x029 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x200 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x23a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3429; op2val:0x2e00; +op3val:0x263a; valaddr_reg:x1; val_offset:3576*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3576*FLEN/8, x4, x2, x6) + +inst_1225: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x00c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0e1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x380c; op2val:0x3ce1; +op3val:0x38f0; valaddr_reg:x1; val_offset:3579*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3579*FLEN/8, x4, x2, x6) + +inst_1226: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x00c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0e1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0f0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x380c; op2val:0x3ce1; +op3val:0x38f0; valaddr_reg:x1; val_offset:3582*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3582*FLEN/8, x4, x2, x6) + +inst_1227: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x00c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0e1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0f0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x380c; op2val:0x3ce1; +op3val:0x38f0; valaddr_reg:x1; val_offset:3585*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3585*FLEN/8, x4, x2, x6) + +inst_1228: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x00c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0e1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0f0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x380c; op2val:0x3ce1; +op3val:0x38f0; valaddr_reg:x1; val_offset:3588*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3588*FLEN/8, x4, x2, x6) + +inst_1229: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x00c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0e1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0f0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x380c; op2val:0x3ce1; +op3val:0x38f0; valaddr_reg:x1; val_offset:3591*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3591*FLEN/8, x4, x2, x6) + +inst_1230: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0db and fs3 == 0 and fe3 == 0x0d and fm3 == 0x10f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x382b; op2val:0x38db; +op3val:0x350f; valaddr_reg:x1; val_offset:3594*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3594*FLEN/8, x4, x2, x6) + +inst_1231: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0db and fs3 == 0 and fe3 == 0x0d and fm3 == 0x10f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x382b; op2val:0x38db; +op3val:0x350f; valaddr_reg:x1; val_offset:3597*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3597*FLEN/8, x4, x2, x6) + +inst_1232: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0db and fs3 == 0 and fe3 == 0x0d and fm3 == 0x10f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x382b; op2val:0x38db; +op3val:0x350f; valaddr_reg:x1; val_offset:3600*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3600*FLEN/8, x4, x2, x6) + +inst_1233: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0db and fs3 == 0 and fe3 == 0x0d and fm3 == 0x10f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x382b; op2val:0x38db; +op3val:0x350f; valaddr_reg:x1; val_offset:3603*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3603*FLEN/8, x4, x2, x6) + +inst_1234: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0db and fs3 == 0 and fe3 == 0x0d and fm3 == 0x10f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x382b; op2val:0x38db; +op3val:0x350f; valaddr_reg:x1; val_offset:3606*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3606*FLEN/8, x4, x2, x6) + +inst_1235: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x375 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x293 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x221 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3375; op2val:0x3e93; +op3val:0x3621; valaddr_reg:x1; val_offset:3609*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3609*FLEN/8, x4, x2, x6) + +inst_1236: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x375 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x293 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x221 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3375; op2val:0x3e93; +op3val:0x3621; valaddr_reg:x1; val_offset:3612*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3612*FLEN/8, x4, x2, x6) + +inst_1237: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x375 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x293 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x221 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3375; op2val:0x3e93; +op3val:0x3621; valaddr_reg:x1; val_offset:3615*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3615*FLEN/8, x4, x2, x6) + +inst_1238: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x375 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x293 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x221 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3375; op2val:0x3e93; +op3val:0x3621; valaddr_reg:x1; val_offset:3618*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3618*FLEN/8, x4, x2, x6) + +inst_1239: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x375 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x293 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x221 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3375; op2val:0x3e93; +op3val:0x3621; valaddr_reg:x1; val_offset:3621*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3621*FLEN/8, x4, x2, x6) + +inst_1240: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1b7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x12a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x361 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35b7; op2val:0x412a; +op3val:0x3b61; valaddr_reg:x1; val_offset:3624*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3624*FLEN/8, x4, x2, x6) + +inst_1241: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1b7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x12a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x361 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35b7; op2val:0x412a; +op3val:0x3b61; valaddr_reg:x1; val_offset:3627*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3627*FLEN/8, x4, x2, x6) + +inst_1242: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1b7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x12a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x361 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35b7; op2val:0x412a; +op3val:0x3b61; valaddr_reg:x1; val_offset:3630*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3630*FLEN/8, x4, x2, x6) + +inst_1243: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1b7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x12a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x361 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35b7; op2val:0x412a; +op3val:0x3b61; valaddr_reg:x1; val_offset:3633*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3633*FLEN/8, x4, x2, x6) + +inst_1244: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1b7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x12a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x361 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35b7; op2val:0x412a; +op3val:0x3b61; valaddr_reg:x1; val_offset:3636*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3636*FLEN/8, x4, x2, x6) + +inst_1245: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d2 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x300 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1f7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ad2; op2val:0x3b00; +op3val:0x39f7; valaddr_reg:x1; val_offset:3639*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3639*FLEN/8, x4, x2, x6) + +inst_1246: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d2 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x300 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1f7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ad2; op2val:0x3b00; +op3val:0x39f7; valaddr_reg:x1; val_offset:3642*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3642*FLEN/8, x4, x2, x6) + +inst_1247: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d2 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x300 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1f7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ad2; op2val:0x3b00; +op3val:0x39f7; valaddr_reg:x1; val_offset:3645*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3645*FLEN/8, x4, x2, x6) + +inst_1248: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d2 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x300 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1f7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ad2; op2val:0x3b00; +op3val:0x39f7; valaddr_reg:x1; val_offset:3648*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3648*FLEN/8, x4, x2, x6) + +inst_1249: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d2 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x300 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1f7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ad2; op2val:0x3b00; +op3val:0x39f7; valaddr_reg:x1; val_offset:3651*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3651*FLEN/8, x4, x2, x6) + +inst_1250: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x01b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x16a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x190 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x341b; op2val:0x416a; +op3val:0x3990; valaddr_reg:x1; val_offset:3654*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3654*FLEN/8, x4, x2, x6) + +inst_1251: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x01b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x16a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x190 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x341b; op2val:0x416a; +op3val:0x3990; valaddr_reg:x1; val_offset:3657*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3657*FLEN/8, x4, x2, x6) + +inst_1252: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x01b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x16a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x190 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x341b; op2val:0x416a; +op3val:0x3990; valaddr_reg:x1; val_offset:3660*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3660*FLEN/8, x4, x2, x6) + +inst_1253: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x01b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x16a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x190 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x341b; op2val:0x416a; +op3val:0x3990; valaddr_reg:x1; val_offset:3663*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3663*FLEN/8, x4, x2, x6) + +inst_1254: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x01b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x16a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x190 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x341b; op2val:0x416a; +op3val:0x3990; valaddr_reg:x1; val_offset:3666*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3666*FLEN/8, x4, x2, x6) + +inst_1255: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2ea and fs2 == 0 and fe2 == 0x10 and fm2 == 0x091 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3e6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36ea; op2val:0x4091; +op3val:0x3be6; valaddr_reg:x1; val_offset:3669*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3669*FLEN/8, x4, x2, x6) + +inst_1256: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2ea and fs2 == 0 and fe2 == 0x10 and fm2 == 0x091 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3e6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36ea; op2val:0x4091; +op3val:0x3be6; valaddr_reg:x1; val_offset:3672*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3672*FLEN/8, x4, x2, x6) + +inst_1257: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2ea and fs2 == 0 and fe2 == 0x10 and fm2 == 0x091 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3e6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36ea; op2val:0x4091; +op3val:0x3be6; valaddr_reg:x1; val_offset:3675*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3675*FLEN/8, x4, x2, x6) + +inst_1258: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2ea and fs2 == 0 and fe2 == 0x10 and fm2 == 0x091 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3e6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36ea; op2val:0x4091; +op3val:0x3be6; valaddr_reg:x1; val_offset:3678*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3678*FLEN/8, x4, x2, x6) + +inst_1259: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2ea and fs2 == 0 and fe2 == 0x10 and fm2 == 0x091 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3e6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36ea; op2val:0x4091; +op3val:0x3be6; valaddr_reg:x1; val_offset:3681*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3681*FLEN/8, x4, x2, x6) + +inst_1260: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x0d2 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x03f and fs3 == 0 and fe3 == 0x13 and fm3 == 0x07b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x44d2; op2val:0x4c3f; +op3val:0x4c7b; valaddr_reg:x1; val_offset:3684*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3684*FLEN/8, x4, x2, x6) + +inst_1261: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x0d2 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x03f and fs3 == 0 and fe3 == 0x13 and fm3 == 0x07b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x44d2; op2val:0x4c3f; +op3val:0x4c7b; valaddr_reg:x1; val_offset:3687*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3687*FLEN/8, x4, x2, x6) + +inst_1262: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x0d2 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x03f and fs3 == 0 and fe3 == 0x13 and fm3 == 0x07b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x44d2; op2val:0x4c3f; +op3val:0x4c7b; valaddr_reg:x1; val_offset:3690*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3690*FLEN/8, x4, x2, x6) + +inst_1263: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x0d2 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x03f and fs3 == 0 and fe3 == 0x13 and fm3 == 0x07b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x44d2; op2val:0x4c3f; +op3val:0x4c7b; valaddr_reg:x1; val_offset:3693*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3693*FLEN/8, x4, x2, x6) + +inst_1264: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x0d2 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x03f and fs3 == 0 and fe3 == 0x13 and fm3 == 0x07b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x44d2; op2val:0x4c3f; +op3val:0x4c7b; valaddr_reg:x1; val_offset:3696*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3696*FLEN/8, x4, x2, x6) + +inst_1265: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x16a and fs2 == 0 and fe2 == 0x10 and fm2 == 0x103 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x193 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x516a; op2val:0x4103; +op3val:0x5193; valaddr_reg:x1; val_offset:3699*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3699*FLEN/8, x4, x2, x6) + +inst_1266: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x16a and fs2 == 0 and fe2 == 0x10 and fm2 == 0x103 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x193 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x516a; op2val:0x4103; +op3val:0x5193; valaddr_reg:x1; val_offset:3702*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3702*FLEN/8, x4, x2, x6) + +inst_1267: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x16a and fs2 == 0 and fe2 == 0x10 and fm2 == 0x103 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x193 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x516a; op2val:0x4103; +op3val:0x5193; valaddr_reg:x1; val_offset:3705*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3705*FLEN/8, x4, x2, x6) + +inst_1268: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x16a and fs2 == 0 and fe2 == 0x10 and fm2 == 0x103 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x193 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x516a; op2val:0x4103; +op3val:0x5193; valaddr_reg:x1; val_offset:3708*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3708*FLEN/8, x4, x2, x6) + +inst_1269: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x16a and fs2 == 0 and fe2 == 0x10 and fm2 == 0x103 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x193 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x516a; op2val:0x4103; +op3val:0x5193; valaddr_reg:x1; val_offset:3711*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3711*FLEN/8, x4, x2, x6) + +inst_1270: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x172 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3a6 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x0d4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5172; op2val:0x3fa6; +op3val:0x4cd4; valaddr_reg:x1; val_offset:3714*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3714*FLEN/8, x4, x2, x6) + +inst_1271: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x172 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3a6 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x0d4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5172; op2val:0x3fa6; +op3val:0x4cd4; valaddr_reg:x1; val_offset:3717*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3717*FLEN/8, x4, x2, x6) + +inst_1272: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x172 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3a6 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x0d4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5172; op2val:0x3fa6; +op3val:0x4cd4; valaddr_reg:x1; val_offset:3720*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3720*FLEN/8, x4, x2, x6) + +inst_1273: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x172 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3a6 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x0d4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5172; op2val:0x3fa6; +op3val:0x4cd4; valaddr_reg:x1; val_offset:3723*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3723*FLEN/8, x4, x2, x6) + +inst_1274: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x172 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3a6 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x0d4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5172; op2val:0x3fa6; +op3val:0x4cd4; valaddr_reg:x1; val_offset:3726*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3726*FLEN/8, x4, x2, x6) + +inst_1275: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x031 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x19f and fs3 == 0 and fe3 == 0x13 and fm3 == 0x391 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5031; op2val:0x419f; +op3val:0x4f91; valaddr_reg:x1; val_offset:3729*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3729*FLEN/8, x4, x2, x6) + +inst_1276: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x031 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x19f and fs3 == 0 and fe3 == 0x13 and fm3 == 0x391 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5031; op2val:0x419f; +op3val:0x4f91; valaddr_reg:x1; val_offset:3732*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3732*FLEN/8, x4, x2, x6) + +inst_1277: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x031 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x19f and fs3 == 0 and fe3 == 0x13 and fm3 == 0x391 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5031; op2val:0x419f; +op3val:0x4f91; valaddr_reg:x1; val_offset:3735*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3735*FLEN/8, x4, x2, x6) + +inst_1278: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x031 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x19f and fs3 == 0 and fe3 == 0x13 and fm3 == 0x391 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5031; op2val:0x419f; +op3val:0x4f91; valaddr_reg:x1; val_offset:3738*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3738*FLEN/8, x4, x2, x6) + +inst_1279: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x031 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x19f and fs3 == 0 and fe3 == 0x13 and fm3 == 0x391 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5031; op2val:0x419f; +op3val:0x4f91; valaddr_reg:x1; val_offset:3741*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3741*FLEN/8, x4, x2, x6) + +inst_1280: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x398 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x03b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4f98; op2val:0x40c5; +op3val:0x483b; valaddr_reg:x1; val_offset:3744*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3744*FLEN/8, x4, x2, x6) + +inst_1281: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x398 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x03b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4f98; op2val:0x40c5; +op3val:0x483b; valaddr_reg:x1; val_offset:3747*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3747*FLEN/8, x4, x2, x6) + +inst_1282: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x398 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x03b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4f98; op2val:0x40c5; +op3val:0x483b; valaddr_reg:x1; val_offset:3750*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3750*FLEN/8, x4, x2, x6) + +inst_1283: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x398 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x03b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4f98; op2val:0x40c5; +op3val:0x483b; valaddr_reg:x1; val_offset:3753*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3753*FLEN/8, x4, x2, x6) + +inst_1284: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x398 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x03b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4f98; op2val:0x40c5; +op3val:0x483b; valaddr_reg:x1; val_offset:3756*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3756*FLEN/8, x4, x2, x6) + +inst_1285: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x329 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x169 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x2c6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5329; op2val:0x3d69; +op3val:0x4ac6; valaddr_reg:x1; val_offset:3759*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3759*FLEN/8, x4, x2, x6) + +inst_1286: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x329 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x169 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x2c6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5329; op2val:0x3d69; +op3val:0x4ac6; valaddr_reg:x1; val_offset:3762*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3762*FLEN/8, x4, x2, x6) + +inst_1287: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x329 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x169 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x2c6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5329; op2val:0x3d69; +op3val:0x4ac6; valaddr_reg:x1; val_offset:3765*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3765*FLEN/8, x4, x2, x6) + +inst_1288: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x329 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x169 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x2c6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5329; op2val:0x3d69; +op3val:0x4ac6; valaddr_reg:x1; val_offset:3768*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3768*FLEN/8, x4, x2, x6) + +inst_1289: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x329 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x169 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x2c6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5329; op2val:0x3d69; +op3val:0x4ac6; valaddr_reg:x1; val_offset:3771*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3771*FLEN/8, x4, x2, x6) + +inst_1290: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3d4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3eb and fs3 == 0 and fe3 == 0x14 and fm3 == 0x37f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x53d4; op2val:0x3feb; +op3val:0x537f; valaddr_reg:x1; val_offset:3774*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3774*FLEN/8, x4, x2, x6) + +inst_1291: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3d4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3eb and fs3 == 0 and fe3 == 0x14 and fm3 == 0x37f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x53d4; op2val:0x3feb; +op3val:0x537f; valaddr_reg:x1; val_offset:3777*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3777*FLEN/8, x4, x2, x6) + +inst_1292: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3d4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3eb and fs3 == 0 and fe3 == 0x14 and fm3 == 0x37f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x53d4; op2val:0x3feb; +op3val:0x537f; valaddr_reg:x1; val_offset:3780*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3780*FLEN/8, x4, x2, x6) + +inst_1293: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3d4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3eb and fs3 == 0 and fe3 == 0x14 and fm3 == 0x37f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x53d4; op2val:0x3feb; +op3val:0x537f; valaddr_reg:x1; val_offset:3783*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3783*FLEN/8, x4, x2, x6) + +inst_1294: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3d4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3eb and fs3 == 0 and fe3 == 0x14 and fm3 == 0x37f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x53d4; op2val:0x3feb; +op3val:0x537f; valaddr_reg:x1; val_offset:3786*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3786*FLEN/8, x4, x2, x6) + +inst_1295: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x034 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x195 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x37a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4034; op2val:0x5195; +op3val:0x4f7a; valaddr_reg:x1; val_offset:3789*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3789*FLEN/8, x4, x2, x6) + +inst_1296: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x034 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x195 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x37a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4034; op2val:0x5195; +op3val:0x4f7a; valaddr_reg:x1; val_offset:3792*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3792*FLEN/8, x4, x2, x6) + +inst_1297: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x034 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x195 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x37a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4034; op2val:0x5195; +op3val:0x4f7a; valaddr_reg:x1; val_offset:3795*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3795*FLEN/8, x4, x2, x6) + +inst_1298: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x034 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x195 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x37a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4034; op2val:0x5195; +op3val:0x4f7a; valaddr_reg:x1; val_offset:3798*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3798*FLEN/8, x4, x2, x6) + +inst_1299: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x034 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x195 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x37a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4034; op2val:0x5195; +op3val:0x4f7a; valaddr_reg:x1; val_offset:3801*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3801*FLEN/8, x4, x2, x6) + +inst_1300: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x295 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0c9 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5295; op2val:0x40c9; +op3val:0x53c0; valaddr_reg:x1; val_offset:3804*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3804*FLEN/8, x4, x2, x6) + +inst_1301: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x295 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0c9 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x3c0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5295; op2val:0x40c9; +op3val:0x53c0; valaddr_reg:x1; val_offset:3807*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3807*FLEN/8, x4, x2, x6) + +inst_1302: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x295 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0c9 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x3c0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5295; op2val:0x40c9; +op3val:0x53c0; valaddr_reg:x1; val_offset:3810*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3810*FLEN/8, x4, x2, x6) + +inst_1303: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x295 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0c9 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x3c0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5295; op2val:0x40c9; +op3val:0x53c0; valaddr_reg:x1; val_offset:3813*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3813*FLEN/8, x4, x2, x6) + +inst_1304: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x295 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0c9 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x3c0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5295; op2val:0x40c9; +op3val:0x53c0; valaddr_reg:x1; val_offset:3816*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3816*FLEN/8, x4, x2, x6) + +inst_1305: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x354 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x196 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x07b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4f54; op2val:0x4196; +op3val:0x4c7b; valaddr_reg:x1; val_offset:3819*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3819*FLEN/8, x4, x2, x6) + +inst_1306: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x354 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x196 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x07b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4f54; op2val:0x4196; +op3val:0x4c7b; valaddr_reg:x1; val_offset:3822*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3822*FLEN/8, x4, x2, x6) + +inst_1307: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x354 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x196 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x07b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4f54; op2val:0x4196; +op3val:0x4c7b; valaddr_reg:x1; val_offset:3825*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3825*FLEN/8, x4, x2, x6) +RVTEST_SIGBASE(x2,signature_x2_10) + +inst_1308: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x354 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x196 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x07b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4f54; op2val:0x4196; +op3val:0x4c7b; valaddr_reg:x1; val_offset:3828*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3828*FLEN/8, x4, x2, x6) + +inst_1309: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x354 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x196 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x07b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4f54; op2val:0x4196; +op3val:0x4c7b; valaddr_reg:x1; val_offset:3831*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3831*FLEN/8, x4, x2, x6) + +inst_1310: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x31c and fs2 == 0 and fe2 == 0x12 and fm2 == 0x061 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x392 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4b1c; op2val:0x4861; +op3val:0x5392; valaddr_reg:x1; val_offset:3834*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3834*FLEN/8, x4, x2, x6) + +inst_1311: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x31c and fs2 == 0 and fe2 == 0x12 and fm2 == 0x061 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x392 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4b1c; op2val:0x4861; +op3val:0x5392; valaddr_reg:x1; val_offset:3837*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3837*FLEN/8, x4, x2, x6) + +inst_1312: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x31c and fs2 == 0 and fe2 == 0x12 and fm2 == 0x061 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x392 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4b1c; op2val:0x4861; +op3val:0x5392; valaddr_reg:x1; val_offset:3840*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3840*FLEN/8, x4, x2, x6) + +inst_1313: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x31c and fs2 == 0 and fe2 == 0x12 and fm2 == 0x061 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x392 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4b1c; op2val:0x4861; +op3val:0x5392; valaddr_reg:x1; val_offset:3843*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3843*FLEN/8, x4, x2, x6) + +inst_1314: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x31c and fs2 == 0 and fe2 == 0x12 and fm2 == 0x061 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x392 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4b1c; op2val:0x4861; +op3val:0x5392; valaddr_reg:x1; val_offset:3846*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3846*FLEN/8, x4, x2, x6) + +inst_1315: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x323 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x31e and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0b4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4b23; op2val:0x471e; +op3val:0x50b4; valaddr_reg:x1; val_offset:3849*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3849*FLEN/8, x4, x2, x6) + +inst_1316: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x323 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x31e and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0b4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4b23; op2val:0x471e; +op3val:0x50b4; valaddr_reg:x1; val_offset:3852*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3852*FLEN/8, x4, x2, x6) + +inst_1317: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x323 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x31e and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0b4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4b23; op2val:0x471e; +op3val:0x50b4; valaddr_reg:x1; val_offset:3855*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3855*FLEN/8, x4, x2, x6) + +inst_1318: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x323 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x31e and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0b4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4b23; op2val:0x471e; +op3val:0x50b4; valaddr_reg:x1; val_offset:3858*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3858*FLEN/8, x4, x2, x6) + +inst_1319: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x323 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x31e and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0b4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4b23; op2val:0x471e; +op3val:0x50b4; valaddr_reg:x1; val_offset:3861*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3861*FLEN/8, x4, x2, x6) + +inst_1320: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x0f7 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x0ef and fs3 == 0 and fe3 == 0x14 and fm3 == 0x040 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x48f7; op2val:0x48ef; +op3val:0x5040; valaddr_reg:x1; val_offset:3864*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3864*FLEN/8, x4, x2, x6) + +inst_1321: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x0f7 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x0ef and fs3 == 0 and fe3 == 0x14 and fm3 == 0x040 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x48f7; op2val:0x48ef; +op3val:0x5040; valaddr_reg:x1; val_offset:3867*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3867*FLEN/8, x4, x2, x6) + +inst_1322: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x0f7 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x0ef and fs3 == 0 and fe3 == 0x14 and fm3 == 0x040 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x48f7; op2val:0x48ef; +op3val:0x5040; valaddr_reg:x1; val_offset:3870*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3870*FLEN/8, x4, x2, x6) + +inst_1323: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x0f7 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x0ef and fs3 == 0 and fe3 == 0x14 and fm3 == 0x040 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x48f7; op2val:0x48ef; +op3val:0x5040; valaddr_reg:x1; val_offset:3873*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3873*FLEN/8, x4, x2, x6) + +inst_1324: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x0f7 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x0ef and fs3 == 0 and fe3 == 0x14 and fm3 == 0x040 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x48f7; op2val:0x48ef; +op3val:0x5040; valaddr_reg:x1; val_offset:3876*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3876*FLEN/8, x4, x2, x6) + +inst_1325: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ce and fs3 == 0 and fe3 == 0x12 and fm3 == 0x0ad and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x53a1; op2val:0x3cce; +op3val:0x48ad; valaddr_reg:x1; val_offset:3879*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3879*FLEN/8, x4, x2, x6) + +inst_1326: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ce and fs3 == 0 and fe3 == 0x12 and fm3 == 0x0ad and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x53a1; op2val:0x3cce; +op3val:0x48ad; valaddr_reg:x1; val_offset:3882*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3882*FLEN/8, x4, x2, x6) + +inst_1327: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ce and fs3 == 0 and fe3 == 0x12 and fm3 == 0x0ad and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x53a1; op2val:0x3cce; +op3val:0x48ad; valaddr_reg:x1; val_offset:3885*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3885*FLEN/8, x4, x2, x6) + +inst_1328: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ce and fs3 == 0 and fe3 == 0x12 and fm3 == 0x0ad and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x53a1; op2val:0x3cce; +op3val:0x48ad; valaddr_reg:x1; val_offset:3888*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3888*FLEN/8, x4, x2, x6) + +inst_1329: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ce and fs3 == 0 and fe3 == 0x12 and fm3 == 0x0ad and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x53a1; op2val:0x3cce; +op3val:0x48ad; valaddr_reg:x1; val_offset:3891*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3891*FLEN/8, x4, x2, x6) + +inst_1330: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x295 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x35e and fs3 == 0 and fe3 == 0x14 and fm3 == 0x021 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5295; op2val:0x3f5e; +op3val:0x5021; valaddr_reg:x1; val_offset:3894*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3894*FLEN/8, x4, x2, x6) + +inst_1331: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x295 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x35e and fs3 == 0 and fe3 == 0x14 and fm3 == 0x021 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5295; op2val:0x3f5e; +op3val:0x5021; valaddr_reg:x1; val_offset:3897*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3897*FLEN/8, x4, x2, x6) + +inst_1332: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x295 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x35e and fs3 == 0 and fe3 == 0x14 and fm3 == 0x021 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5295; op2val:0x3f5e; +op3val:0x5021; valaddr_reg:x1; val_offset:3900*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3900*FLEN/8, x4, x2, x6) + +inst_1333: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x295 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x35e and fs3 == 0 and fe3 == 0x14 and fm3 == 0x021 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5295; op2val:0x3f5e; +op3val:0x5021; valaddr_reg:x1; val_offset:3903*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3903*FLEN/8, x4, x2, x6) + +inst_1334: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x295 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x35e and fs3 == 0 and fe3 == 0x14 and fm3 == 0x021 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5295; op2val:0x3f5e; +op3val:0x5021; valaddr_reg:x1; val_offset:3906*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3906*FLEN/8, x4, x2, x6) + +inst_1335: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x31c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3b0 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x1aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x531c; op2val:0x3fb0; +op3val:0x51aa; valaddr_reg:x1; val_offset:3909*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3909*FLEN/8, x4, x2, x6) + +inst_1336: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x31c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3b0 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x1aa and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x531c; op2val:0x3fb0; +op3val:0x51aa; valaddr_reg:x1; val_offset:3912*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3912*FLEN/8, x4, x2, x6) + +inst_1337: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x31c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3b0 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x1aa and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x531c; op2val:0x3fb0; +op3val:0x51aa; valaddr_reg:x1; val_offset:3915*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3915*FLEN/8, x4, x2, x6) + +inst_1338: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x31c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3b0 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x1aa and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x531c; op2val:0x3fb0; +op3val:0x51aa; valaddr_reg:x1; val_offset:3918*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3918*FLEN/8, x4, x2, x6) + +inst_1339: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x31c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3b0 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x1aa and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x531c; op2val:0x3fb0; +op3val:0x51aa; valaddr_reg:x1; val_offset:3921*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3921*FLEN/8, x4, x2, x6) + +inst_1340: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x3c9 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3cd and fs3 == 0 and fe3 == 0x14 and fm3 == 0x331 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4bc9; op2val:0x47cd; +op3val:0x5331; valaddr_reg:x1; val_offset:3924*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3924*FLEN/8, x4, x2, x6) + +inst_1341: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x3c9 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3cd and fs3 == 0 and fe3 == 0x14 and fm3 == 0x331 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4bc9; op2val:0x47cd; +op3val:0x5331; valaddr_reg:x1; val_offset:3927*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3927*FLEN/8, x4, x2, x6) + +inst_1342: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x3c9 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3cd and fs3 == 0 and fe3 == 0x14 and fm3 == 0x331 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4bc9; op2val:0x47cd; +op3val:0x5331; valaddr_reg:x1; val_offset:3930*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3930*FLEN/8, x4, x2, x6) + +inst_1343: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x3c9 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3cd and fs3 == 0 and fe3 == 0x14 and fm3 == 0x331 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4bc9; op2val:0x47cd; +op3val:0x5331; valaddr_reg:x1; val_offset:3933*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3933*FLEN/8, x4, x2, x6) + +inst_1344: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x3c9 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3cd and fs3 == 0 and fe3 == 0x14 and fm3 == 0x331 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4bc9; op2val:0x47cd; +op3val:0x5331; valaddr_reg:x1; val_offset:3936*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3936*FLEN/8, x4, x2, x6) + +inst_1345: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3e8 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x035 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x121 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4fe8; op2val:0x4035; +op3val:0x4121; valaddr_reg:x1; val_offset:3939*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3939*FLEN/8, x4, x2, x6) + +inst_1346: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3e8 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x035 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x121 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4fe8; op2val:0x4035; +op3val:0x4121; valaddr_reg:x1; val_offset:3942*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3942*FLEN/8, x4, x2, x6) + +inst_1347: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3e8 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x035 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x121 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4fe8; op2val:0x4035; +op3val:0x4121; valaddr_reg:x1; val_offset:3945*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3945*FLEN/8, x4, x2, x6) + +inst_1348: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3e8 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x035 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x121 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4fe8; op2val:0x4035; +op3val:0x4121; valaddr_reg:x1; val_offset:3948*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3948*FLEN/8, x4, x2, x6) + +inst_1349: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3e8 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x035 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x121 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4fe8; op2val:0x4035; +op3val:0x4121; valaddr_reg:x1; val_offset:3951*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3951*FLEN/8, x4, x2, x6) + +inst_1350: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x0e7 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x0e4 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ce7; op2val:0x54e4; +op3val:0x4ffe; valaddr_reg:x1; val_offset:3954*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3954*FLEN/8, x4, x2, x6) + +inst_1351: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x0e7 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x0e4 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x3fe and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ce7; op2val:0x54e4; +op3val:0x4ffe; valaddr_reg:x1; val_offset:3957*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3957*FLEN/8, x4, x2, x6) + +inst_1352: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x0e7 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x0e4 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x3fe and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ce7; op2val:0x54e4; +op3val:0x4ffe; valaddr_reg:x1; val_offset:3960*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3960*FLEN/8, x4, x2, x6) + +inst_1353: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x0e7 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x0e4 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x3fe and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ce7; op2val:0x54e4; +op3val:0x4ffe; valaddr_reg:x1; val_offset:3963*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3963*FLEN/8, x4, x2, x6) + +inst_1354: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x0e7 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x0e4 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x3fe and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ce7; op2val:0x54e4; +op3val:0x4ffe; valaddr_reg:x1; val_offset:3966*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3966*FLEN/8, x4, x2, x6) + +inst_1355: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x359 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1b7 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x101 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4f59; op2val:0x41b7; +op3val:0x4d01; valaddr_reg:x1; val_offset:3969*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3969*FLEN/8, x4, x2, x6) + +inst_1356: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x359 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1b7 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x101 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4f59; op2val:0x41b7; +op3val:0x4d01; valaddr_reg:x1; val_offset:3972*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3972*FLEN/8, x4, x2, x6) + +inst_1357: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x359 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1b7 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x101 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4f59; op2val:0x41b7; +op3val:0x4d01; valaddr_reg:x1; val_offset:3975*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3975*FLEN/8, x4, x2, x6) + +inst_1358: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x359 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1b7 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x101 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4f59; op2val:0x41b7; +op3val:0x4d01; valaddr_reg:x1; val_offset:3978*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3978*FLEN/8, x4, x2, x6) + +inst_1359: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x359 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1b7 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x101 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4f59; op2val:0x41b7; +op3val:0x4d01; valaddr_reg:x1; val_offset:3981*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3981*FLEN/8, x4, x2, x6) + +inst_1360: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x0ee and fs2 == 0 and fe2 == 0x12 and fm2 == 0x064 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x1ab and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x48ee; op2val:0x4864; +op3val:0x4dab; valaddr_reg:x1; val_offset:3984*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3984*FLEN/8, x4, x2, x6) + +inst_1361: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x0ee and fs2 == 0 and fe2 == 0x12 and fm2 == 0x064 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x1ab and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x48ee; op2val:0x4864; +op3val:0x4dab; valaddr_reg:x1; val_offset:3987*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3987*FLEN/8, x4, x2, x6) + +inst_1362: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x0ee and fs2 == 0 and fe2 == 0x12 and fm2 == 0x064 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x1ab and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x48ee; op2val:0x4864; +op3val:0x4dab; valaddr_reg:x1; val_offset:3990*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3990*FLEN/8, x4, x2, x6) + +inst_1363: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x0ee and fs2 == 0 and fe2 == 0x12 and fm2 == 0x064 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x1ab and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x48ee; op2val:0x4864; +op3val:0x4dab; valaddr_reg:x1; val_offset:3993*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3993*FLEN/8, x4, x2, x6) + +inst_1364: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x0ee and fs2 == 0 and fe2 == 0x12 and fm2 == 0x064 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x1ab and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x48ee; op2val:0x4864; +op3val:0x4dab; valaddr_reg:x1; val_offset:3996*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3996*FLEN/8, x4, x2, x6) + +inst_1365: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x13a and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1a3 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x2be and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4d3a; op2val:0x45a3; +op3val:0x52be; valaddr_reg:x1; val_offset:3999*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3999*FLEN/8, x4, x2, x6) + +inst_1366: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x13a and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1a3 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x2be and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4d3a; op2val:0x45a3; +op3val:0x52be; valaddr_reg:x1; val_offset:4002*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 4002*FLEN/8, x4, x2, x6) + +inst_1367: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x13a and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1a3 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x2be and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4d3a; op2val:0x45a3; +op3val:0x52be; valaddr_reg:x1; val_offset:4005*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 4005*FLEN/8, x4, x2, x6) + +inst_1368: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x13a and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1a3 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x2be and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4d3a; op2val:0x45a3; +op3val:0x52be; valaddr_reg:x1; val_offset:4008*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 4008*FLEN/8, x4, x2, x6) + +inst_1369: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x13a and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1a3 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x2be and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4d3a; op2val:0x45a3; +op3val:0x52be; valaddr_reg:x1; val_offset:4011*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 4011*FLEN/8, x4, x2, x6) + +inst_1370: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x070 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x253 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x209 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c70; op2val:0x5653; +op3val:0x5209; valaddr_reg:x1; val_offset:4014*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 4014*FLEN/8, x4, x2, x6) + +inst_1371: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x070 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x253 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x209 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c70; op2val:0x5653; +op3val:0x5209; valaddr_reg:x1; val_offset:4017*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 4017*FLEN/8, x4, x2, x6) + +inst_1372: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x070 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x253 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x209 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c70; op2val:0x5653; +op3val:0x5209; valaddr_reg:x1; val_offset:4020*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 4020*FLEN/8, x4, x2, x6) + +inst_1373: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x070 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x253 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x209 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c70; op2val:0x5653; +op3val:0x5209; valaddr_reg:x1; val_offset:4023*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 4023*FLEN/8, x4, x2, x6) + +inst_1374: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x070 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x253 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x209 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c70; op2val:0x5653; +op3val:0x5209; valaddr_reg:x1; val_offset:4026*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 4026*FLEN/8, x4, x2, x6) + +inst_1375: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2bb and fs2 == 0 and fe2 == 0x0f and fm2 == 0x163 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x048 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x52bb; op2val:0x3d63; +op3val:0x4848; valaddr_reg:x1; val_offset:4029*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 4029*FLEN/8, x4, x2, x6) + +inst_1376: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2bb and fs2 == 0 and fe2 == 0x0f and fm2 == 0x163 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x048 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x52bb; op2val:0x3d63; +op3val:0x4848; valaddr_reg:x1; val_offset:4032*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 4032*FLEN/8, x4, x2, x6) + +inst_1377: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2bb and fs2 == 0 and fe2 == 0x0f and fm2 == 0x163 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x048 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x52bb; op2val:0x3d63; +op3val:0x4848; valaddr_reg:x1; val_offset:4035*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 4035*FLEN/8, x4, x2, x6) + +inst_1378: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2bb and fs2 == 0 and fe2 == 0x0f and fm2 == 0x163 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x048 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x52bb; op2val:0x3d63; +op3val:0x4848; valaddr_reg:x1; val_offset:4038*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 4038*FLEN/8, x4, x2, x6) + +inst_1379: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2bb and fs2 == 0 and fe2 == 0x0f and fm2 == 0x163 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x048 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x52bb; op2val:0x3d63; +op3val:0x4848; valaddr_reg:x1; val_offset:4041*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 4041*FLEN/8, x4, x2, x6) + +inst_1380: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x36b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x368 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x1bd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x536b; op2val:0x3f68; +op3val:0x51bd; valaddr_reg:x1; val_offset:4044*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 4044*FLEN/8, x4, x2, x6) + +inst_1381: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x36b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x368 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x1bd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x536b; op2val:0x3f68; +op3val:0x51bd; valaddr_reg:x1; val_offset:4047*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 4047*FLEN/8, x4, x2, x6) + +inst_1382: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x36b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x368 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x1bd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x536b; op2val:0x3f68; +op3val:0x51bd; valaddr_reg:x1; val_offset:4050*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 4050*FLEN/8, x4, x2, x6) + +inst_1383: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x36b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x368 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x1bd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x536b; op2val:0x3f68; +op3val:0x51bd; valaddr_reg:x1; val_offset:4053*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 4053*FLEN/8, x4, x2, x6) + +inst_1384: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x36b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x368 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x1bd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x536b; op2val:0x3f68; +op3val:0x51bd; valaddr_reg:x1; val_offset:4056*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 4056*FLEN/8, x4, x2, x6) + +inst_1385: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x339 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1c3 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x0d0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5339; op2val:0x3dc3; +op3val:0x4cd0; valaddr_reg:x1; val_offset:4059*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 4059*FLEN/8, x4, x2, x6) + +inst_1386: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x339 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1c3 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x0d0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5339; op2val:0x3dc3; +op3val:0x4cd0; valaddr_reg:x1; val_offset:4062*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 4062*FLEN/8, x4, x2, x6) + +inst_1387: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x339 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1c3 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x0d0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5339; op2val:0x3dc3; +op3val:0x4cd0; valaddr_reg:x1; val_offset:4065*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 4065*FLEN/8, x4, x2, x6) + +inst_1388: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x339 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1c3 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x0d0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5339; op2val:0x3dc3; +op3val:0x4cd0; valaddr_reg:x1; val_offset:4068*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 4068*FLEN/8, x4, x2, x6) + +inst_1389: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x339 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1c3 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x0d0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5339; op2val:0x3dc3; +op3val:0x4cd0; valaddr_reg:x1; val_offset:4071*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 4071*FLEN/8, x4, x2, x6) + +inst_1390: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x21d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x357 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x270 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4e1d; op2val:0x4357; +op3val:0x4e70; valaddr_reg:x1; val_offset:4074*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 4074*FLEN/8, x4, x2, x6) + +inst_1391: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x21d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x357 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x270 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4e1d; op2val:0x4357; +op3val:0x4e70; valaddr_reg:x1; val_offset:4077*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 4077*FLEN/8, x4, x2, x6) + +inst_1392: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x21d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x357 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x270 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4e1d; op2val:0x4357; +op3val:0x4e70; valaddr_reg:x1; val_offset:4080*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 4080*FLEN/8, x4, x2, x6) + +inst_1393: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x21d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x357 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x270 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4e1d; op2val:0x4357; +op3val:0x4e70; valaddr_reg:x1; val_offset:4083*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 4083*FLEN/8, x4, x2, x6) + +inst_1394: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x21d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x357 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x270 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4e1d; op2val:0x4357; +op3val:0x4e70; valaddr_reg:x1; val_offset:4086*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 4086*FLEN/8, x4, x2, x6) + +inst_1395: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x263 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0c4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x53fe; op2val:0x3e63; +op3val:0x50c4; valaddr_reg:x1; val_offset:4089*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 4089*FLEN/8, x4, x2, x6) + +inst_1396: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x263 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0c4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x53fe; op2val:0x3e63; +op3val:0x50c4; valaddr_reg:x1; val_offset:4092*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 4092*FLEN/8, x4, x2, x6) + +inst_1397: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x263 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0c4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x53fe; op2val:0x3e63; +op3val:0x50c4; valaddr_reg:x1; val_offset:4095*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 4095*FLEN/8, x4, x2, x6) + +inst_1398: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x263 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0c4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x53fe; op2val:0x3e63; +op3val:0x50c4; valaddr_reg:x1; val_offset:4098*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 4098*FLEN/8, x4, x2, x6) + +inst_1399: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x263 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0c4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x53fe; op2val:0x3e63; +op3val:0x50c4; valaddr_reg:x1; val_offset:4101*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 4101*FLEN/8, x4, x2, x6) + +inst_1400: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x1ee and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3c0 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x2fd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4dee; op2val:0x43c0; +op3val:0x4efd; valaddr_reg:x1; val_offset:4104*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 4104*FLEN/8, x4, x2, x6) + +inst_1401: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x1ee and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3c0 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x2fd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4dee; op2val:0x43c0; +op3val:0x4efd; valaddr_reg:x1; val_offset:4107*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 4107*FLEN/8, x4, x2, x6) + +inst_1402: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x1ee and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3c0 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x2fd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4dee; op2val:0x43c0; +op3val:0x4efd; valaddr_reg:x1; val_offset:4110*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 4110*FLEN/8, x4, x2, x6) + +inst_1403: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x1ee and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3c0 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x2fd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4dee; op2val:0x43c0; +op3val:0x4efd; valaddr_reg:x1; val_offset:4113*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 4113*FLEN/8, x4, x2, x6) + +inst_1404: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x1ee and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3c0 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x2fd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4dee; op2val:0x43c0; +op3val:0x4efd; valaddr_reg:x1; val_offset:4116*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 4116*FLEN/8, x4, x2, x6) + +inst_1405: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x095 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x36c and fs3 == 0 and fe3 == 0x11 and fm3 == 0x00a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c95; op2val:0x436c; +op3val:0x440a; valaddr_reg:x1; val_offset:4119*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 4119*FLEN/8, x4, x2, x6) + +inst_1406: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x095 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x36c and fs3 == 0 and fe3 == 0x11 and fm3 == 0x00a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c95; op2val:0x436c; +op3val:0x440a; valaddr_reg:x1; val_offset:4122*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 4122*FLEN/8, x4, x2, x6) + +inst_1407: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x095 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x36c and fs3 == 0 and fe3 == 0x11 and fm3 == 0x00a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c95; op2val:0x436c; +op3val:0x440a; valaddr_reg:x1; val_offset:4125*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 4125*FLEN/8, x4, x2, x6) + +inst_1408: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x095 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x36c and fs3 == 0 and fe3 == 0x11 and fm3 == 0x00a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c95; op2val:0x436c; +op3val:0x440a; valaddr_reg:x1; val_offset:4128*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 4128*FLEN/8, x4, x2, x6) + +inst_1409: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x095 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x36c and fs3 == 0 and fe3 == 0x11 and fm3 == 0x00a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c95; op2val:0x436c; +op3val:0x440a; valaddr_reg:x1; val_offset:4131*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 4131*FLEN/8, x4, x2, x6) + +inst_1410: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x368 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x3ef and fs3 == 0 and fe3 == 0x14 and fm3 == 0x2b2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4768; op2val:0x4bef; +op3val:0x52b2; valaddr_reg:x1; val_offset:4134*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 4134*FLEN/8, x4, x2, x6) + +inst_1411: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x368 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x3ef and fs3 == 0 and fe3 == 0x14 and fm3 == 0x2b2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4768; op2val:0x4bef; +op3val:0x52b2; valaddr_reg:x1; val_offset:4137*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 4137*FLEN/8, x4, x2, x6) + +inst_1412: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x368 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x3ef and fs3 == 0 and fe3 == 0x14 and fm3 == 0x2b2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4768; op2val:0x4bef; +op3val:0x52b2; valaddr_reg:x1; val_offset:4140*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 4140*FLEN/8, x4, x2, x6) + +inst_1413: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x368 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x3ef and fs3 == 0 and fe3 == 0x14 and fm3 == 0x2b2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4768; op2val:0x4bef; +op3val:0x52b2; valaddr_reg:x1; val_offset:4143*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 4143*FLEN/8, x4, x2, x6) + +inst_1414: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x368 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x3ef and fs3 == 0 and fe3 == 0x14 and fm3 == 0x2b2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4768; op2val:0x4bef; +op3val:0x52b2; valaddr_reg:x1; val_offset:4146*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 4146*FLEN/8, x4, x2, x6) + +inst_1415: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x0bf and fs2 == 0 and fe2 == 0x11 and fm2 == 0x286 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x37e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4cbf; op2val:0x4686; +op3val:0x537e; valaddr_reg:x1; val_offset:4149*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 4149*FLEN/8, x4, x2, x6) + +inst_1416: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x0bf and fs2 == 0 and fe2 == 0x11 and fm2 == 0x286 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x37e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4cbf; op2val:0x4686; +op3val:0x537e; valaddr_reg:x1; val_offset:4152*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 4152*FLEN/8, x4, x2, x6) + +inst_1417: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x0bf and fs2 == 0 and fe2 == 0x11 and fm2 == 0x286 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x37e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4cbf; op2val:0x4686; +op3val:0x537e; valaddr_reg:x1; val_offset:4155*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 4155*FLEN/8, x4, x2, x6) + +inst_1418: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x0bf and fs2 == 0 and fe2 == 0x11 and fm2 == 0x286 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x37e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4cbf; op2val:0x4686; +op3val:0x537e; valaddr_reg:x1; val_offset:4158*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 4158*FLEN/8, x4, x2, x6) + +inst_1419: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x0bf and fs2 == 0 and fe2 == 0x11 and fm2 == 0x286 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x37e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4cbf; op2val:0x4686; +op3val:0x537e; valaddr_reg:x1; val_offset:4161*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 4161*FLEN/8, x4, x2, x6) + +inst_1420: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x02d and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0e4 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x06f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c2d; op2val:0x44e4; +op3val:0x4c6f; valaddr_reg:x1; val_offset:4164*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 4164*FLEN/8, x4, x2, x6) + +inst_1421: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x02d and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0e4 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x06f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c2d; op2val:0x44e4; +op3val:0x4c6f; valaddr_reg:x1; val_offset:4167*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 4167*FLEN/8, x4, x2, x6) + +inst_1422: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x02d and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0e4 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x06f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c2d; op2val:0x44e4; +op3val:0x4c6f; valaddr_reg:x1; val_offset:4170*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 4170*FLEN/8, x4, x2, x6) + +inst_1423: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x02d and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0e4 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x06f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c2d; op2val:0x44e4; +op3val:0x4c6f; valaddr_reg:x1; val_offset:4173*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 4173*FLEN/8, x4, x2, x6) + +inst_1424: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x02d and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0e4 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x06f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c2d; op2val:0x44e4; +op3val:0x4c6f; valaddr_reg:x1; val_offset:4176*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 4176*FLEN/8, x4, x2, x6) + +inst_1425: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x026 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0a3 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x27b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5026; op2val:0x40a3; +op3val:0x4a7b; valaddr_reg:x1; val_offset:4179*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 4179*FLEN/8, x4, x2, x6) + +inst_1426: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x026 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0a3 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x27b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5026; op2val:0x40a3; +op3val:0x4a7b; valaddr_reg:x1; val_offset:4182*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 4182*FLEN/8, x4, x2, x6) + +inst_1427: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x026 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0a3 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x27b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5026; op2val:0x40a3; +op3val:0x4a7b; valaddr_reg:x1; val_offset:4185*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 4185*FLEN/8, x4, x2, x6) + +inst_1428: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x026 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0a3 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x27b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5026; op2val:0x40a3; +op3val:0x4a7b; valaddr_reg:x1; val_offset:4188*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 4188*FLEN/8, x4, x2, x6) + +inst_1429: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x026 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0a3 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x27b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5026; op2val:0x40a3; +op3val:0x4a7b; valaddr_reg:x1; val_offset:4191*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 4191*FLEN/8, x4, x2, x6) + +inst_1430: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x221 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x11b and fs3 == 0 and fe3 == 0x14 and fm3 == 0x3a7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4e21; op2val:0x451b; +op3val:0x53a7; valaddr_reg:x1; val_offset:4194*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 4194*FLEN/8, x4, x2, x6) + +inst_1431: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x221 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x11b and fs3 == 0 and fe3 == 0x14 and fm3 == 0x3a7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4e21; op2val:0x451b; +op3val:0x53a7; valaddr_reg:x1; val_offset:4197*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 4197*FLEN/8, x4, x2, x6) + +inst_1432: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x221 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x11b and fs3 == 0 and fe3 == 0x14 and fm3 == 0x3a7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4e21; op2val:0x451b; +op3val:0x53a7; valaddr_reg:x1; val_offset:4200*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 4200*FLEN/8, x4, x2, x6) + +inst_1433: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x221 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x11b and fs3 == 0 and fe3 == 0x14 and fm3 == 0x3a7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4e21; op2val:0x451b; +op3val:0x53a7; valaddr_reg:x1; val_offset:4203*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 4203*FLEN/8, x4, x2, x6) + +inst_1434: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x221 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x11b and fs3 == 0 and fe3 == 0x14 and fm3 == 0x3a7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4e21; op2val:0x451b; +op3val:0x53a7; valaddr_reg:x1; val_offset:4206*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 4206*FLEN/8, x4, x2, x6) + +inst_1435: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x316 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x018 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x285 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5316; op2val:0x4018; +op3val:0x5285; valaddr_reg:x1; val_offset:4209*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 4209*FLEN/8, x4, x2, x6) +RVTEST_SIGBASE(x2,signature_x2_11) + +inst_1436: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x316 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x018 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x285 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5316; op2val:0x4018; +op3val:0x5285; valaddr_reg:x1; val_offset:4212*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 4212*FLEN/8, x4, x2, x6) + +inst_1437: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x316 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x018 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x285 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5316; op2val:0x4018; +op3val:0x5285; valaddr_reg:x1; val_offset:4215*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 4215*FLEN/8, x4, x2, x6) + +inst_1438: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x316 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x018 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x285 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5316; op2val:0x4018; +op3val:0x5285; valaddr_reg:x1; val_offset:4218*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 4218*FLEN/8, x4, x2, x6) + +inst_1439: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x316 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x018 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x285 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5316; op2val:0x4018; +op3val:0x5285; valaddr_reg:x1; val_offset:4221*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 4221*FLEN/8, x4, x2, x6) + +inst_1440: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x118 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x203 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x351 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5118; op2val:0x4203; +op3val:0x5351; valaddr_reg:x1; val_offset:4224*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 4224*FLEN/8, x4, x2, x6) + +inst_1441: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x118 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x203 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x351 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5118; op2val:0x4203; +op3val:0x5351; valaddr_reg:x1; val_offset:4227*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 4227*FLEN/8, x4, x2, x6) + +inst_1442: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x118 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x203 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x351 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5118; op2val:0x4203; +op3val:0x5351; valaddr_reg:x1; val_offset:4230*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 4230*FLEN/8, x4, x2, x6) + +inst_1443: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x118 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x203 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x351 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5118; op2val:0x4203; +op3val:0x5351; valaddr_reg:x1; val_offset:4233*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 4233*FLEN/8, x4, x2, x6) + +inst_1444: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x118 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x203 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x351 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5118; op2val:0x4203; +op3val:0x5351; valaddr_reg:x1; val_offset:4236*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 4236*FLEN/8, x4, x2, x6) + +inst_1445: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x388 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x29c and fs3 == 0 and fe3 == 0x14 and fm3 == 0x073 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5388; op2val:0x3e9c; +op3val:0x5073; valaddr_reg:x1; val_offset:4239*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 4239*FLEN/8, x4, x2, x6) + +inst_1446: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x388 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x29c and fs3 == 0 and fe3 == 0x14 and fm3 == 0x073 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5388; op2val:0x3e9c; +op3val:0x5073; valaddr_reg:x1; val_offset:4242*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 4242*FLEN/8, x4, x2, x6) + +inst_1447: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x388 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x29c and fs3 == 0 and fe3 == 0x14 and fm3 == 0x073 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5388; op2val:0x3e9c; +op3val:0x5073; valaddr_reg:x1; val_offset:4245*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 4245*FLEN/8, x4, x2, x6) + +inst_1448: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x388 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x29c and fs3 == 0 and fe3 == 0x14 and fm3 == 0x073 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5388; op2val:0x3e9c; +op3val:0x5073; valaddr_reg:x1; val_offset:4248*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 4248*FLEN/8, x4, x2, x6) + +inst_1449: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x388 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x29c and fs3 == 0 and fe3 == 0x14 and fm3 == 0x073 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5388; op2val:0x3e9c; +op3val:0x5073; valaddr_reg:x1; val_offset:4251*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 4251*FLEN/8, x4, x2, x6) + +inst_1450: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1ca and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1e1 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x01e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x51ca; op2val:0x3de1; +op3val:0x441e; valaddr_reg:x1; val_offset:4254*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 4254*FLEN/8, x4, x2, x6) + +inst_1451: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1ca and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1e1 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x01e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x51ca; op2val:0x3de1; +op3val:0x441e; valaddr_reg:x1; val_offset:4257*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 4257*FLEN/8, x4, x2, x6) + +inst_1452: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1ca and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1e1 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x01e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x51ca; op2val:0x3de1; +op3val:0x441e; valaddr_reg:x1; val_offset:4260*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 4260*FLEN/8, x4, x2, x6) + +inst_1453: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1ca and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1e1 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x01e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x51ca; op2val:0x3de1; +op3val:0x441e; valaddr_reg:x1; val_offset:4263*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 4263*FLEN/8, x4, x2, x6) + +inst_1454: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1ca and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1e1 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x01e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x51ca; op2val:0x3de1; +op3val:0x441e; valaddr_reg:x1; val_offset:4266*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 4266*FLEN/8, x4, x2, x6) + +inst_1455: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1e4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3ed and fs3 == 0 and fe3 == 0x13 and fm3 == 0x35a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x51e4; op2val:0x3fed; +op3val:0x4f5a; valaddr_reg:x1; val_offset:4269*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 4269*FLEN/8, x4, x2, x6) + +inst_1456: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1e4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3ed and fs3 == 0 and fe3 == 0x13 and fm3 == 0x35a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x51e4; op2val:0x3fed; +op3val:0x4f5a; valaddr_reg:x1; val_offset:4272*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 4272*FLEN/8, x4, x2, x6) + +inst_1457: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1e4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3ed and fs3 == 0 and fe3 == 0x13 and fm3 == 0x35a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x51e4; op2val:0x3fed; +op3val:0x4f5a; valaddr_reg:x1; val_offset:4275*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 4275*FLEN/8, x4, x2, x6) + +inst_1458: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1e4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3ed and fs3 == 0 and fe3 == 0x13 and fm3 == 0x35a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x51e4; op2val:0x3fed; +op3val:0x4f5a; valaddr_reg:x1; val_offset:4278*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 4278*FLEN/8, x4, x2, x6) + +inst_1459: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1e4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3ed and fs3 == 0 and fe3 == 0x13 and fm3 == 0x35a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x51e4; op2val:0x3fed; +op3val:0x4f5a; valaddr_reg:x1; val_offset:4281*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 4281*FLEN/8, x4, x2, x6) + +inst_1460: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x20d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x05c and fs3 == 0 and fe3 == 0x14 and fm3 == 0x133 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x520d; op2val:0x405c; +op3val:0x5133; valaddr_reg:x1; val_offset:4284*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 4284*FLEN/8, x4, x2, x6) + +inst_1461: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x20d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x05c and fs3 == 0 and fe3 == 0x14 and fm3 == 0x133 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x520d; op2val:0x405c; +op3val:0x5133; valaddr_reg:x1; val_offset:4287*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 4287*FLEN/8, x4, x2, x6) + +inst_1462: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x20d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x05c and fs3 == 0 and fe3 == 0x14 and fm3 == 0x133 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x520d; op2val:0x405c; +op3val:0x5133; valaddr_reg:x1; val_offset:4290*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 4290*FLEN/8, x4, x2, x6) + +inst_1463: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x20d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x05c and fs3 == 0 and fe3 == 0x14 and fm3 == 0x133 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x520d; op2val:0x405c; +op3val:0x5133; valaddr_reg:x1; val_offset:4293*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 4293*FLEN/8, x4, x2, x6) + +inst_1464: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x20d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x05c and fs3 == 0 and fe3 == 0x14 and fm3 == 0x133 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x520d; op2val:0x405c; +op3val:0x5133; valaddr_reg:x1; val_offset:4296*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 4296*FLEN/8, x4, x2, x6) + +inst_1465: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x0c2 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x327 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x016 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4cc2; op2val:0x4327; +op3val:0x4416; valaddr_reg:x1; val_offset:4299*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 4299*FLEN/8, x4, x2, x6) + +inst_1466: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x0c2 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x327 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x016 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4cc2; op2val:0x4327; +op3val:0x4416; valaddr_reg:x1; val_offset:4302*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 4302*FLEN/8, x4, x2, x6) + +inst_1467: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x0c2 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x327 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x016 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4cc2; op2val:0x4327; +op3val:0x4416; valaddr_reg:x1; val_offset:4305*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 4305*FLEN/8, x4, x2, x6) + +inst_1468: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x0c2 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x327 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x016 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4cc2; op2val:0x4327; +op3val:0x4416; valaddr_reg:x1; val_offset:4308*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 4308*FLEN/8, x4, x2, x6) + +inst_1469: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x0c2 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x327 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x016 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4cc2; op2val:0x4327; +op3val:0x4416; valaddr_reg:x1; val_offset:4311*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 4311*FLEN/8, x4, x2, x6) + +inst_1470: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x28a and fs2 == 0 and fe2 == 0x12 and fm2 == 0x071 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x303 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e8a; op2val:0x4871; +op3val:0x3b03; valaddr_reg:x1; val_offset:4314*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 4314*FLEN/8, x4, x2, x6) + +inst_1471: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x28a and fs2 == 0 and fe2 == 0x12 and fm2 == 0x071 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x303 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e8a; op2val:0x4871; +op3val:0x3b03; valaddr_reg:x1; val_offset:4317*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 4317*FLEN/8, x4, x2, x6) + +inst_1472: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x28a and fs2 == 0 and fe2 == 0x12 and fm2 == 0x071 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x303 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e8a; op2val:0x4871; +op3val:0x3b03; valaddr_reg:x1; val_offset:4320*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 4320*FLEN/8, x4, x2, x6) + +inst_1473: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x28a and fs2 == 0 and fe2 == 0x12 and fm2 == 0x071 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x303 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e8a; op2val:0x4871; +op3val:0x3b03; valaddr_reg:x1; val_offset:4323*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 4323*FLEN/8, x4, x2, x6) + +inst_1474: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x28a and fs2 == 0 and fe2 == 0x12 and fm2 == 0x071 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x303 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e8a; op2val:0x4871; +op3val:0x3b03; valaddr_reg:x1; val_offset:4326*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 4326*FLEN/8, x4, x2, x6) + +inst_1475: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x057 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x125 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x156 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3857; op2val:0x3d25; +op3val:0x3956; valaddr_reg:x1; val_offset:4329*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 4329*FLEN/8, x4, x2, x6) + +inst_1476: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x057 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x125 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x156 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3857; op2val:0x3d25; +op3val:0x3956; valaddr_reg:x1; val_offset:4332*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 4332*FLEN/8, x4, x2, x6) + +inst_1477: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x057 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x125 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x156 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3857; op2val:0x3d25; +op3val:0x3956; valaddr_reg:x1; val_offset:4335*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 4335*FLEN/8, x4, x2, x6) + +inst_1478: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x057 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x125 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x156 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3857; op2val:0x3d25; +op3val:0x3956; valaddr_reg:x1; val_offset:4338*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 4338*FLEN/8, x4, x2, x6) + +inst_1479: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x057 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x125 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x156 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3857; op2val:0x3d25; +op3val:0x3956; valaddr_reg:x1; val_offset:4341*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 4341*FLEN/8, x4, x2, x6) + +inst_1480: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1b1 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x317 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x08b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39b1; op2val:0x3717; +op3val:0x348b; valaddr_reg:x1; val_offset:4344*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 4344*FLEN/8, x4, x2, x6) + +inst_1481: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1b1 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x317 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x08b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39b1; op2val:0x3717; +op3val:0x348b; valaddr_reg:x1; val_offset:4347*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 4347*FLEN/8, x4, x2, x6) + +inst_1482: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1b1 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x317 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x08b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39b1; op2val:0x3717; +op3val:0x348b; valaddr_reg:x1; val_offset:4350*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 4350*FLEN/8, x4, x2, x6) + +inst_1483: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1b1 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x317 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x08b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39b1; op2val:0x3717; +op3val:0x348b; valaddr_reg:x1; val_offset:4353*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 4353*FLEN/8, x4, x2, x6) + +inst_1484: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1b1 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x317 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x08b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39b1; op2val:0x3717; +op3val:0x348b; valaddr_reg:x1; val_offset:4356*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 4356*FLEN/8, x4, x2, x6) + +inst_1485: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2f0 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x32f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1fb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2af0; op2val:0x4b2f; +op3val:0x39fb; valaddr_reg:x1; val_offset:4359*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 4359*FLEN/8, x4, x2, x6) + +inst_1486: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2f0 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x32f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1fb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2af0; op2val:0x4b2f; +op3val:0x39fb; valaddr_reg:x1; val_offset:4362*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 4362*FLEN/8, x4, x2, x6) + +inst_1487: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2f0 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x32f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1fb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2af0; op2val:0x4b2f; +op3val:0x39fb; valaddr_reg:x1; val_offset:4365*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 4365*FLEN/8, x4, x2, x6) + +inst_1488: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2f0 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x32f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1fb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2af0; op2val:0x4b2f; +op3val:0x39fb; valaddr_reg:x1; val_offset:4368*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 4368*FLEN/8, x4, x2, x6) + +inst_1489: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2f0 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x32f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1fb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2af0; op2val:0x4b2f; +op3val:0x39fb; valaddr_reg:x1; val_offset:4371*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 4371*FLEN/8, x4, x2, x6) + +inst_1490: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x00f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ab and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35d5; op2val:0x400f; +op3val:0x39ab; valaddr_reg:x1; val_offset:4374*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 4374*FLEN/8, x4, x2, x6) + +inst_1491: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x00f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ab and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35d5; op2val:0x400f; +op3val:0x39ab; valaddr_reg:x1; val_offset:4377*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 4377*FLEN/8, x4, x2, x6) + +inst_1492: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x00f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ab and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35d5; op2val:0x400f; +op3val:0x39ab; valaddr_reg:x1; val_offset:4380*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 4380*FLEN/8, x4, x2, x6) + +inst_1493: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x00f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ab and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35d5; op2val:0x400f; +op3val:0x39ab; valaddr_reg:x1; val_offset:4383*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 4383*FLEN/8, x4, x2, x6) + +inst_1494: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x00f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ab and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35d5; op2val:0x400f; +op3val:0x39ab; valaddr_reg:x1; val_offset:4386*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 4386*FLEN/8, x4, x2, x6) + +inst_1495: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x35c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1a4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0f1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x375c; op2val:0x3da4; +op3val:0x38f1; valaddr_reg:x1; val_offset:4389*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 4389*FLEN/8, x4, x2, x6) + +inst_1496: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x35c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1a4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0f1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x375c; op2val:0x3da4; +op3val:0x38f1; valaddr_reg:x1; val_offset:4392*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 4392*FLEN/8, x4, x2, x6) + +inst_1497: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x35c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1a4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0f1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x375c; op2val:0x3da4; +op3val:0x38f1; valaddr_reg:x1; val_offset:4395*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 4395*FLEN/8, x4, x2, x6) + +inst_1498: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x35c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1a4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0f1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x375c; op2val:0x3da4; +op3val:0x38f1; valaddr_reg:x1; val_offset:4398*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 4398*FLEN/8, x4, x2, x6) + +inst_1499: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x35c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1a4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0f1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x375c; op2val:0x3da4; +op3val:0x38f1; valaddr_reg:x1; val_offset:4401*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 4401*FLEN/8, x4, x2, x6) + +inst_1500: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x02c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2bf and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ab4; op2val:0x3c2c; +op3val:0x3abf; valaddr_reg:x1; val_offset:4404*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 4404*FLEN/8, x4, x2, x6) + +inst_1501: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x02c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2bf and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ab4; op2val:0x3c2c; +op3val:0x3abf; valaddr_reg:x1; val_offset:4407*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 4407*FLEN/8, x4, x2, x6) + +inst_1502: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x02c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2bf and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ab4; op2val:0x3c2c; +op3val:0x3abf; valaddr_reg:x1; val_offset:4410*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 4410*FLEN/8, x4, x2, x6) + +inst_1503: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x02c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2bf and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ab4; op2val:0x3c2c; +op3val:0x3abf; valaddr_reg:x1; val_offset:4413*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 4413*FLEN/8, x4, x2, x6) + +inst_1504: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x02c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2bf and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ab4; op2val:0x3c2c; +op3val:0x3abf; valaddr_reg:x1; val_offset:4416*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 4416*FLEN/8, x4, x2, x6) + +inst_1505: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x263 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x227 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x3d4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a63; op2val:0x3227; +op3val:0x2fd4; valaddr_reg:x1; val_offset:4419*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 4419*FLEN/8, x4, x2, x6) + +inst_1506: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x263 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x227 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x3d4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a63; op2val:0x3227; +op3val:0x2fd4; valaddr_reg:x1; val_offset:4422*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 4422*FLEN/8, x4, x2, x6) + +inst_1507: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x263 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x227 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x3d4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a63; op2val:0x3227; +op3val:0x2fd4; valaddr_reg:x1; val_offset:4425*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 4425*FLEN/8, x4, x2, x6) + +inst_1508: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x263 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x227 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x3d4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a63; op2val:0x3227; +op3val:0x2fd4; valaddr_reg:x1; val_offset:4428*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 4428*FLEN/8, x4, x2, x6) + +inst_1509: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x263 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x227 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x3d4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a63; op2val:0x3227; +op3val:0x2fd4; valaddr_reg:x1; val_offset:4431*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 4431*FLEN/8, x4, x2, x6) + +inst_1510: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x025 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x24f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x24b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3825; op2val:0x3e4f; +op3val:0x3a4b; valaddr_reg:x1; val_offset:4434*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 4434*FLEN/8, x4, x2, x6) + +inst_1511: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x025 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x24f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x24b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3825; op2val:0x3e4f; +op3val:0x3a4b; valaddr_reg:x1; val_offset:4437*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 4437*FLEN/8, x4, x2, x6) + +inst_1512: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x025 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x24f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x24b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3825; op2val:0x3e4f; +op3val:0x3a4b; valaddr_reg:x1; val_offset:4440*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 4440*FLEN/8, x4, x2, x6) + +inst_1513: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x025 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x24f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x24b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3825; op2val:0x3e4f; +op3val:0x3a4b; valaddr_reg:x1; val_offset:4443*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 4443*FLEN/8, x4, x2, x6) + +inst_1514: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x025 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x24f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x24b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3825; op2val:0x3e4f; +op3val:0x3a4b; valaddr_reg:x1; val_offset:4446*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 4446*FLEN/8, x4, x2, x6) + +inst_1515: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3cf and fs2 == 0 and fe2 == 0x0e and fm2 == 0x052 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x070 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2fcf; op2val:0x3852; +op3val:0x2870; valaddr_reg:x1; val_offset:4449*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 4449*FLEN/8, x4, x2, x6) + +inst_1516: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3cf and fs2 == 0 and fe2 == 0x0e and fm2 == 0x052 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x070 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2fcf; op2val:0x3852; +op3val:0x2870; valaddr_reg:x1; val_offset:4452*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 4452*FLEN/8, x4, x2, x6) + +inst_1517: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3cf and fs2 == 0 and fe2 == 0x0e and fm2 == 0x052 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x070 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2fcf; op2val:0x3852; +op3val:0x2870; valaddr_reg:x1; val_offset:4455*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 4455*FLEN/8, x4, x2, x6) + +inst_1518: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3cf and fs2 == 0 and fe2 == 0x0e and fm2 == 0x052 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x070 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2fcf; op2val:0x3852; +op3val:0x2870; valaddr_reg:x1; val_offset:4458*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 4458*FLEN/8, x4, x2, x6) + +inst_1519: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3cf and fs2 == 0 and fe2 == 0x0e and fm2 == 0x052 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x070 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2fcf; op2val:0x3852; +op3val:0x2870; valaddr_reg:x1; val_offset:4461*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 4461*FLEN/8, x4, x2, x6) + +inst_1520: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x083 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x25a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2eb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3883; op2val:0x3e5a; +op3val:0x3aeb; valaddr_reg:x1; val_offset:4464*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 4464*FLEN/8, x4, x2, x6) + +inst_1521: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x083 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x25a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2eb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3883; op2val:0x3e5a; +op3val:0x3aeb; valaddr_reg:x1; val_offset:4467*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 4467*FLEN/8, x4, x2, x6) + +inst_1522: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x083 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x25a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2eb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3883; op2val:0x3e5a; +op3val:0x3aeb; valaddr_reg:x1; val_offset:4470*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 4470*FLEN/8, x4, x2, x6) + +inst_1523: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x083 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x25a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2eb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3883; op2val:0x3e5a; +op3val:0x3aeb; valaddr_reg:x1; val_offset:4473*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 4473*FLEN/8, x4, x2, x6) + +inst_1524: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x083 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x25a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2eb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3883; op2val:0x3e5a; +op3val:0x3aeb; valaddr_reg:x1; val_offset:4476*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 4476*FLEN/8, x4, x2, x6) + +inst_1525: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x282 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0a3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x34c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a82; op2val:0x3ca3; +op3val:0x3b4c; valaddr_reg:x1; val_offset:4479*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 4479*FLEN/8, x4, x2, x6) + +inst_1526: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x282 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0a3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x34c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a82; op2val:0x3ca3; +op3val:0x3b4c; valaddr_reg:x1; val_offset:4482*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 4482*FLEN/8, x4, x2, x6) + +inst_1527: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x282 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0a3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x34c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a82; op2val:0x3ca3; +op3val:0x3b4c; valaddr_reg:x1; val_offset:4485*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 4485*FLEN/8, x4, x2, x6) + +inst_1528: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x282 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0a3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x34c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a82; op2val:0x3ca3; +op3val:0x3b4c; valaddr_reg:x1; val_offset:4488*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 4488*FLEN/8, x4, x2, x6) + +inst_1529: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x282 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0a3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x34c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a82; op2val:0x3ca3; +op3val:0x3b4c; valaddr_reg:x1; val_offset:4491*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 4491*FLEN/8, x4, x2, x6) + +inst_1530: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x159 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1a3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x34b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3959; op2val:0x3da3; +op3val:0x3b4b; valaddr_reg:x1; val_offset:4494*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 4494*FLEN/8, x4, x2, x6) + +inst_1531: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x159 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1a3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x34b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3959; op2val:0x3da3; +op3val:0x3b4b; valaddr_reg:x1; val_offset:4497*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 4497*FLEN/8, x4, x2, x6) + +inst_1532: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x159 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1a3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x34b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3959; op2val:0x3da3; +op3val:0x3b4b; valaddr_reg:x1; val_offset:4500*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 4500*FLEN/8, x4, x2, x6) + +inst_1533: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x159 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1a3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x34b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3959; op2val:0x3da3; +op3val:0x3b4b; valaddr_reg:x1; val_offset:4503*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 4503*FLEN/8, x4, x2, x6) + +inst_1534: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x159 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1a3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x34b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3959; op2val:0x3da3; +op3val:0x3b4b; valaddr_reg:x1; val_offset:4506*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 4506*FLEN/8, x4, x2, x6) + +inst_1535: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x225 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x010 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a25; op2val:0x3c10; +op3val:0x39ff; valaddr_reg:x1; val_offset:4509*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 4509*FLEN/8, x4, x2, x6) + +inst_1536: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x225 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x010 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a25; op2val:0x3c10; +op3val:0x39ff; valaddr_reg:x1; val_offset:4512*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 4512*FLEN/8, x4, x2, x6) + +inst_1537: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x225 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x010 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a25; op2val:0x3c10; +op3val:0x39ff; valaddr_reg:x1; val_offset:4515*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 4515*FLEN/8, x4, x2, x6) + +inst_1538: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x225 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x010 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a25; op2val:0x3c10; +op3val:0x39ff; valaddr_reg:x1; val_offset:4518*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 4518*FLEN/8, x4, x2, x6) + +inst_1539: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x225 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x010 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a25; op2val:0x3c10; +op3val:0x39ff; valaddr_reg:x1; val_offset:4521*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 4521*FLEN/8, x4, x2, x6) + +inst_1540: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x32b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x221 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x07e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x372b; op2val:0x3621; +op3val:0x307e; valaddr_reg:x1; val_offset:4524*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 4524*FLEN/8, x4, x2, x6) + +inst_1541: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x32b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x221 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x07e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x372b; op2val:0x3621; +op3val:0x307e; valaddr_reg:x1; val_offset:4527*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 4527*FLEN/8, x4, x2, x6) + +inst_1542: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x32b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x221 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x07e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x372b; op2val:0x3621; +op3val:0x307e; valaddr_reg:x1; val_offset:4530*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 4530*FLEN/8, x4, x2, x6) + +inst_1543: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x32b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x221 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x07e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x372b; op2val:0x3621; +op3val:0x307e; valaddr_reg:x1; val_offset:4533*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 4533*FLEN/8, x4, x2, x6) + +inst_1544: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x32b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x221 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x07e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x372b; op2val:0x3621; +op3val:0x307e; valaddr_reg:x1; val_offset:4536*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 4536*FLEN/8, x4, x2, x6) + +inst_1545: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x061 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x09c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0cd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3461; op2val:0x409c; +op3val:0x38cd; valaddr_reg:x1; val_offset:4539*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 4539*FLEN/8, x4, x2, x6) + +inst_1546: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x061 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x09c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0cd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3461; op2val:0x409c; +op3val:0x38cd; valaddr_reg:x1; val_offset:4542*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 4542*FLEN/8, x4, x2, x6) + +inst_1547: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x061 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x09c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0cd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3461; op2val:0x409c; +op3val:0x38cd; valaddr_reg:x1; val_offset:4545*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 4545*FLEN/8, x4, x2, x6) + +inst_1548: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x061 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x09c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0cd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3461; op2val:0x409c; +op3val:0x38cd; valaddr_reg:x1; val_offset:4548*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 4548*FLEN/8, x4, x2, x6) + +inst_1549: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x061 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x09c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0cd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3461; op2val:0x409c; +op3val:0x38cd; valaddr_reg:x1; val_offset:4551*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 4551*FLEN/8, x4, x2, x6) + +inst_1550: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ca and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2fd and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ca; op2val:0x3afd; +op3val:0x37e0; valaddr_reg:x1; val_offset:4554*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 4554*FLEN/8, x4, x2, x6) + +inst_1551: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ca and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2fd and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3e0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ca; op2val:0x3afd; +op3val:0x37e0; valaddr_reg:x1; val_offset:4557*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 4557*FLEN/8, x4, x2, x6) + +inst_1552: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ca and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2fd and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3e0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ca; op2val:0x3afd; +op3val:0x37e0; valaddr_reg:x1; val_offset:4560*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 4560*FLEN/8, x4, x2, x6) + +inst_1553: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ca and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2fd and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3e0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ca; op2val:0x3afd; +op3val:0x37e0; valaddr_reg:x1; val_offset:4563*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 4563*FLEN/8, x4, x2, x6) + +inst_1554: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ca and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2fd and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3e0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ca; op2val:0x3afd; +op3val:0x37e0; valaddr_reg:x1; val_offset:4566*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 4566*FLEN/8, x4, x2, x6) + +inst_1555: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x114 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x06e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x161 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3914; op2val:0x3c6e; +op3val:0x3961; valaddr_reg:x1; val_offset:4569*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 4569*FLEN/8, x4, x2, x6) + +inst_1556: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x114 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x06e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x161 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3914; op2val:0x3c6e; +op3val:0x3961; valaddr_reg:x1; val_offset:4572*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 4572*FLEN/8, x4, x2, x6) + +inst_1557: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x114 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x06e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x161 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3914; op2val:0x3c6e; +op3val:0x3961; valaddr_reg:x1; val_offset:4575*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 4575*FLEN/8, x4, x2, x6) + +inst_1558: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x114 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x06e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x161 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3914; op2val:0x3c6e; +op3val:0x3961; valaddr_reg:x1; val_offset:4578*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 4578*FLEN/8, x4, x2, x6) + +inst_1559: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x114 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x06e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x161 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3914; op2val:0x3c6e; +op3val:0x3961; valaddr_reg:x1; val_offset:4581*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 4581*FLEN/8, x4, x2, x6) + +inst_1560: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x384 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x27d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1d9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b84; op2val:0x3a7d; +op3val:0x39d9; valaddr_reg:x1; val_offset:4584*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 4584*FLEN/8, x4, x2, x6) + +inst_1561: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x384 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x27d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1d9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b84; op2val:0x3a7d; +op3val:0x39d9; valaddr_reg:x1; val_offset:4587*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 4587*FLEN/8, x4, x2, x6) + +inst_1562: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x384 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x27d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1d9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b84; op2val:0x3a7d; +op3val:0x39d9; valaddr_reg:x1; val_offset:4590*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 4590*FLEN/8, x4, x2, x6) + +inst_1563: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x384 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x27d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1d9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b84; op2val:0x3a7d; +op3val:0x39d9; valaddr_reg:x1; val_offset:4593*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 4593*FLEN/8, x4, x2, x6) +RVTEST_SIGBASE(x2,signature_x2_12) + +inst_1564: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x384 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x27d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1d9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b84; op2val:0x3a7d; +op3val:0x39d9; valaddr_reg:x1; val_offset:4596*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 4596*FLEN/8, x4, x2, x6) + +inst_1565: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x344 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x306 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2c00; op2val:0x4b44; +op3val:0x3b06; valaddr_reg:x1; val_offset:4599*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 4599*FLEN/8, x4, x2, x6) + +inst_1566: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x344 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x306 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2c00; op2val:0x4b44; +op3val:0x3b06; valaddr_reg:x1; val_offset:4602*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 4602*FLEN/8, x4, x2, x6) + +inst_1567: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x344 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x306 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2c00; op2val:0x4b44; +op3val:0x3b06; valaddr_reg:x1; val_offset:4605*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 4605*FLEN/8, x4, x2, x6) + +inst_1568: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x344 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x306 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2c00; op2val:0x4b44; +op3val:0x3b06; valaddr_reg:x1; val_offset:4608*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 4608*FLEN/8, x4, x2, x6) + +inst_1569: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x344 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x306 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2c00; op2val:0x4b44; +op3val:0x3b06; valaddr_reg:x1; val_offset:4611*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 4611*FLEN/8, x4, x2, x6) + +inst_1570: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x019 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x294 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x23d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3819; op2val:0x3a94; +op3val:0x363d; valaddr_reg:x1; val_offset:4614*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 4614*FLEN/8, x4, x2, x6) + +inst_1571: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x019 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x294 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x23d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3819; op2val:0x3a94; +op3val:0x363d; valaddr_reg:x1; val_offset:4617*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 4617*FLEN/8, x4, x2, x6) + +inst_1572: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x019 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x294 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x23d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3819; op2val:0x3a94; +op3val:0x363d; valaddr_reg:x1; val_offset:4620*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 4620*FLEN/8, x4, x2, x6) + +inst_1573: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x019 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x294 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x23d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3819; op2val:0x3a94; +op3val:0x363d; valaddr_reg:x1; val_offset:4623*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 4623*FLEN/8, x4, x2, x6) + +inst_1574: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x019 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x294 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x23d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3819; op2val:0x3a94; +op3val:0x363d; valaddr_reg:x1; val_offset:4626*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 4626*FLEN/8, x4, x2, x6) + +inst_1575: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x140 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x102 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x253 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3140; op2val:0x4502; +op3val:0x3a53; valaddr_reg:x1; val_offset:4629*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 4629*FLEN/8, x4, x2, x6) + +inst_1576: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x140 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x102 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x253 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3140; op2val:0x4502; +op3val:0x3a53; valaddr_reg:x1; val_offset:4632*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 4632*FLEN/8, x4, x2, x6) + +inst_1577: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x140 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x102 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x253 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3140; op2val:0x4502; +op3val:0x3a53; valaddr_reg:x1; val_offset:4635*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 4635*FLEN/8, x4, x2, x6) + +inst_1578: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x140 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x102 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x253 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3140; op2val:0x4502; +op3val:0x3a53; valaddr_reg:x1; val_offset:4638*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 4638*FLEN/8, x4, x2, x6) + +inst_1579: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x140 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x102 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x253 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3140; op2val:0x4502; +op3val:0x3a53; valaddr_reg:x1; val_offset:4641*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 4641*FLEN/8, x4, x2, x6) + +inst_1580: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1e6 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x049 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x213 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39e6; op2val:0x3c49; +op3val:0x3a13; valaddr_reg:x1; val_offset:4644*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 4644*FLEN/8, x4, x2, x6) + +inst_1581: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1e6 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x049 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x213 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39e6; op2val:0x3c49; +op3val:0x3a13; valaddr_reg:x1; val_offset:4647*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 4647*FLEN/8, x4, x2, x6) + +inst_1582: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1e6 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x049 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x213 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39e6; op2val:0x3c49; +op3val:0x3a13; valaddr_reg:x1; val_offset:4650*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 4650*FLEN/8, x4, x2, x6) + +inst_1583: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1e6 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x049 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x213 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39e6; op2val:0x3c49; +op3val:0x3a13; valaddr_reg:x1; val_offset:4653*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 4653*FLEN/8, x4, x2, x6) + +inst_1584: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1e6 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x049 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x213 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39e6; op2val:0x3c49; +op3val:0x3a13; valaddr_reg:x1; val_offset:4656*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 4656*FLEN/8, x4, x2, x6) + +inst_1585: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3d3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38e6; op2val:0x3bd3; +op3val:0x388b; valaddr_reg:x1; val_offset:4659*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 4659*FLEN/8, x4, x2, x6) + +inst_1586: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3d3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38e6; op2val:0x3bd3; +op3val:0x388b; valaddr_reg:x1; val_offset:4662*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 4662*FLEN/8, x4, x2, x6) + +inst_1587: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3d3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38e6; op2val:0x3bd3; +op3val:0x388b; valaddr_reg:x1; val_offset:4665*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 4665*FLEN/8, x4, x2, x6) + +inst_1588: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3d3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38e6; op2val:0x3bd3; +op3val:0x388b; valaddr_reg:x1; val_offset:4668*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 4668*FLEN/8, x4, x2, x6) + +inst_1589: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3d3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38e6; op2val:0x3bd3; +op3val:0x388b; valaddr_reg:x1; val_offset:4671*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 4671*FLEN/8, x4, x2, x6) + +inst_1590: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0db and fs2 == 0 and fe2 == 0x10 and fm2 == 0x183 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1b0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2cdb; op2val:0x4183; +op3val:0x31b0; valaddr_reg:x1; val_offset:4674*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 4674*FLEN/8, x4, x2, x6) + +inst_1591: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0db and fs2 == 0 and fe2 == 0x10 and fm2 == 0x183 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1b0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2cdb; op2val:0x4183; +op3val:0x31b0; valaddr_reg:x1; val_offset:4677*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 4677*FLEN/8, x4, x2, x6) + +inst_1592: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0db and fs2 == 0 and fe2 == 0x10 and fm2 == 0x183 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1b0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2cdb; op2val:0x4183; +op3val:0x31b0; valaddr_reg:x1; val_offset:4680*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 4680*FLEN/8, x4, x2, x6) + +inst_1593: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0db and fs2 == 0 and fe2 == 0x10 and fm2 == 0x183 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1b0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2cdb; op2val:0x4183; +op3val:0x31b0; valaddr_reg:x1; val_offset:4683*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 4683*FLEN/8, x4, x2, x6) + +inst_1594: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0db and fs2 == 0 and fe2 == 0x10 and fm2 == 0x183 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1b0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2cdb; op2val:0x4183; +op3val:0x31b0; valaddr_reg:x1; val_offset:4686*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 4686*FLEN/8, x4, x2, x6) + +inst_1595: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x28a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3d4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30f0; op2val:0x468a; +op3val:0x3bd4; valaddr_reg:x1; val_offset:4689*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 4689*FLEN/8, x4, x2, x6) + +inst_1596: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x28a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3d4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30f0; op2val:0x468a; +op3val:0x3bd4; valaddr_reg:x1; val_offset:4692*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 4692*FLEN/8, x4, x2, x6) + +inst_1597: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x28a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3d4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30f0; op2val:0x468a; +op3val:0x3bd4; valaddr_reg:x1; val_offset:4695*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 4695*FLEN/8, x4, x2, x6) + +inst_1598: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x28a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3d4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30f0; op2val:0x468a; +op3val:0x3bd4; valaddr_reg:x1; val_offset:4698*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 4698*FLEN/8, x4, x2, x6) + +inst_1599: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0f0 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x28a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3d4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30f0; op2val:0x468a; +op3val:0x3bd4; valaddr_reg:x1; val_offset:4701*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 4701*FLEN/8, x4, x2, x6) + +inst_1600: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1ae and fs3 == 0 and fe3 == 0x0d and fm3 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bc0; op2val:0x35ae; +op3val:0x3500; valaddr_reg:x1; val_offset:4704*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 4704*FLEN/8, x4, x2, x6) + +inst_1601: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1ae and fs3 == 0 and fe3 == 0x0d and fm3 == 0x100 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bc0; op2val:0x35ae; +op3val:0x3500; valaddr_reg:x1; val_offset:4707*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 4707*FLEN/8, x4, x2, x6) + +inst_1602: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1ae and fs3 == 0 and fe3 == 0x0d and fm3 == 0x100 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bc0; op2val:0x35ae; +op3val:0x3500; valaddr_reg:x1; val_offset:4710*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 4710*FLEN/8, x4, x2, x6) + +inst_1603: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1ae and fs3 == 0 and fe3 == 0x0d and fm3 == 0x100 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bc0; op2val:0x35ae; +op3val:0x3500; valaddr_reg:x1; val_offset:4713*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 4713*FLEN/8, x4, x2, x6) + +inst_1604: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1ae and fs3 == 0 and fe3 == 0x0d and fm3 == 0x100 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bc0; op2val:0x35ae; +op3val:0x3500; valaddr_reg:x1; val_offset:4716*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 4716*FLEN/8, x4, x2, x6) + +inst_1605: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x03b and fs2 == 0 and fe2 == 0x11 and fm2 == 0x054 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x303b; op2val:0x4454; +op3val:0x3855; valaddr_reg:x1; val_offset:4719*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 4719*FLEN/8, x4, x2, x6) + +inst_1606: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x03b and fs2 == 0 and fe2 == 0x11 and fm2 == 0x054 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x055 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x303b; op2val:0x4454; +op3val:0x3855; valaddr_reg:x1; val_offset:4722*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 4722*FLEN/8, x4, x2, x6) + +inst_1607: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x03b and fs2 == 0 and fe2 == 0x11 and fm2 == 0x054 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x055 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x303b; op2val:0x4454; +op3val:0x3855; valaddr_reg:x1; val_offset:4725*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 4725*FLEN/8, x4, x2, x6) + +inst_1608: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x03b and fs2 == 0 and fe2 == 0x11 and fm2 == 0x054 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x055 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x303b; op2val:0x4454; +op3val:0x3855; valaddr_reg:x1; val_offset:4728*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 4728*FLEN/8, x4, x2, x6) + +inst_1609: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x03b and fs2 == 0 and fe2 == 0x11 and fm2 == 0x054 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x055 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x303b; op2val:0x4454; +op3val:0x3855; valaddr_reg:x1; val_offset:4731*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 4731*FLEN/8, x4, x2, x6) + +inst_1610: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2e6 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0c8 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36e6; op2val:0x40c8; +op3val:0x3bff; valaddr_reg:x1; val_offset:4734*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 4734*FLEN/8, x4, x2, x6) + +inst_1611: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2e6 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0c8 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36e6; op2val:0x40c8; +op3val:0x3bff; valaddr_reg:x1; val_offset:4737*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 4737*FLEN/8, x4, x2, x6) + +inst_1612: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2e6 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0c8 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36e6; op2val:0x40c8; +op3val:0x3bff; valaddr_reg:x1; val_offset:4740*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 4740*FLEN/8, x4, x2, x6) + +inst_1613: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2e6 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0c8 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36e6; op2val:0x40c8; +op3val:0x3bff; valaddr_reg:x1; val_offset:4743*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 4743*FLEN/8, x4, x2, x6) + +inst_1614: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2e6 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0c8 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36e6; op2val:0x40c8; +op3val:0x3bff; valaddr_reg:x1; val_offset:4746*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 4746*FLEN/8, x4, x2, x6) + +inst_1615: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0f7 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2e0 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x289 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38f7; op2val:0x32e0; +op3val:0x2e89; valaddr_reg:x1; val_offset:4749*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 4749*FLEN/8, x4, x2, x6) + +inst_1616: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0f7 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2e0 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x289 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38f7; op2val:0x32e0; +op3val:0x2e89; valaddr_reg:x1; val_offset:4752*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 4752*FLEN/8, x4, x2, x6) + +inst_1617: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0f7 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2e0 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x289 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38f7; op2val:0x32e0; +op3val:0x2e89; valaddr_reg:x1; val_offset:4755*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 4755*FLEN/8, x4, x2, x6) + +inst_1618: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0f7 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2e0 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x289 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38f7; op2val:0x32e0; +op3val:0x2e89; valaddr_reg:x1; val_offset:4758*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 4758*FLEN/8, x4, x2, x6) + +inst_1619: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0f7 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2e0 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x289 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38f7; op2val:0x32e0; +op3val:0x2e89; valaddr_reg:x1; val_offset:4761*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 4761*FLEN/8, x4, x2, x6) + +inst_1620: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x268 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x00b and fs3 == 0 and fe3 == 0x0c and fm3 == 0x17b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3268; op2val:0x3c0b; +op3val:0x317b; valaddr_reg:x1; val_offset:4764*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 4764*FLEN/8, x4, x2, x6) + +inst_1621: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x268 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x00b and fs3 == 0 and fe3 == 0x0c and fm3 == 0x17b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3268; op2val:0x3c0b; +op3val:0x317b; valaddr_reg:x1; val_offset:4767*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 4767*FLEN/8, x4, x2, x6) + +inst_1622: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x268 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x00b and fs3 == 0 and fe3 == 0x0c and fm3 == 0x17b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3268; op2val:0x3c0b; +op3val:0x317b; valaddr_reg:x1; val_offset:4770*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 4770*FLEN/8, x4, x2, x6) + +inst_1623: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x268 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x00b and fs3 == 0 and fe3 == 0x0c and fm3 == 0x17b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3268; op2val:0x3c0b; +op3val:0x317b; valaddr_reg:x1; val_offset:4773*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 4773*FLEN/8, x4, x2, x6) + +inst_1624: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x268 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x00b and fs3 == 0 and fe3 == 0x0c and fm3 == 0x17b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3268; op2val:0x3c0b; +op3val:0x317b; valaddr_reg:x1; val_offset:4776*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 4776*FLEN/8, x4, x2, x6) + +inst_1625: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x371 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x2cc and fs3 == 0 and fe3 == 0x0e and fm3 == 0x213 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2b71; op2val:0x4acc; +op3val:0x3a13; valaddr_reg:x1; val_offset:4779*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 4779*FLEN/8, x4, x2, x6) + +inst_1626: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x371 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x2cc and fs3 == 0 and fe3 == 0x0e and fm3 == 0x213 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2b71; op2val:0x4acc; +op3val:0x3a13; valaddr_reg:x1; val_offset:4782*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 4782*FLEN/8, x4, x2, x6) + +inst_1627: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x371 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x2cc and fs3 == 0 and fe3 == 0x0e and fm3 == 0x213 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2b71; op2val:0x4acc; +op3val:0x3a13; valaddr_reg:x1; val_offset:4785*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 4785*FLEN/8, x4, x2, x6) + +inst_1628: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x371 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x2cc and fs3 == 0 and fe3 == 0x0e and fm3 == 0x213 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2b71; op2val:0x4acc; +op3val:0x3a13; valaddr_reg:x1; val_offset:4788*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 4788*FLEN/8, x4, x2, x6) + +inst_1629: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x371 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x2cc and fs3 == 0 and fe3 == 0x0e and fm3 == 0x213 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2b71; op2val:0x4acc; +op3val:0x3a13; valaddr_reg:x1; val_offset:4791*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 4791*FLEN/8, x4, x2, x6) + +inst_1630: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x327 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3e3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2cd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b27; op2val:0x3be3; +op3val:0x3acd; valaddr_reg:x1; val_offset:4794*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 4794*FLEN/8, x4, x2, x6) + +inst_1631: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x327 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3e3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2cd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b27; op2val:0x3be3; +op3val:0x3acd; valaddr_reg:x1; val_offset:4797*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 4797*FLEN/8, x4, x2, x6) + +inst_1632: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x327 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3e3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2cd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b27; op2val:0x3be3; +op3val:0x3acd; valaddr_reg:x1; val_offset:4800*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 4800*FLEN/8, x4, x2, x6) + +inst_1633: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x327 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3e3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2cd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b27; op2val:0x3be3; +op3val:0x3acd; valaddr_reg:x1; val_offset:4803*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 4803*FLEN/8, x4, x2, x6) + +inst_1634: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x327 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3e3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2cd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b27; op2val:0x3be3; +op3val:0x3acd; valaddr_reg:x1; val_offset:4806*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 4806*FLEN/8, x4, x2, x6) + +inst_1635: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3e7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x16d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37e7; op2val:0x3a00; +op3val:0x356d; valaddr_reg:x1; val_offset:4809*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 4809*FLEN/8, x4, x2, x6) + +inst_1636: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3e7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x16d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37e7; op2val:0x3a00; +op3val:0x356d; valaddr_reg:x1; val_offset:4812*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 4812*FLEN/8, x4, x2, x6) + +inst_1637: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3e7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x16d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37e7; op2val:0x3a00; +op3val:0x356d; valaddr_reg:x1; val_offset:4815*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 4815*FLEN/8, x4, x2, x6) + +inst_1638: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3e7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x16d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37e7; op2val:0x3a00; +op3val:0x356d; valaddr_reg:x1; val_offset:4818*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 4818*FLEN/8, x4, x2, x6) + +inst_1639: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3e7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x16d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37e7; op2val:0x3a00; +op3val:0x356d; valaddr_reg:x1; val_offset:4821*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 4821*FLEN/8, x4, x2, x6) + +inst_1640: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1a0 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x38d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0d0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2da0; op2val:0x438d; +op3val:0x34d0; valaddr_reg:x1; val_offset:4824*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 4824*FLEN/8, x4, x2, x6) + +inst_1641: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1a0 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x38d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0d0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2da0; op2val:0x438d; +op3val:0x34d0; valaddr_reg:x1; val_offset:4827*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 4827*FLEN/8, x4, x2, x6) + +inst_1642: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1a0 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x38d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0d0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2da0; op2val:0x438d; +op3val:0x34d0; valaddr_reg:x1; val_offset:4830*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 4830*FLEN/8, x4, x2, x6) + +inst_1643: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1a0 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x38d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0d0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2da0; op2val:0x438d; +op3val:0x34d0; valaddr_reg:x1; val_offset:4833*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 4833*FLEN/8, x4, x2, x6) + +inst_1644: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1a0 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x38d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0d0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2da0; op2val:0x438d; +op3val:0x34d0; valaddr_reg:x1; val_offset:4836*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 4836*FLEN/8, x4, x2, x6) + +inst_1645: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1f7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x23a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x025 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35f7; op2val:0x3a3a; +op3val:0x3425; valaddr_reg:x1; val_offset:4839*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 4839*FLEN/8, x4, x2, x6) + +inst_1646: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1f7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x23a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x025 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35f7; op2val:0x3a3a; +op3val:0x3425; valaddr_reg:x1; val_offset:4842*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 4842*FLEN/8, x4, x2, x6) + +inst_1647: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1f7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x23a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x025 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35f7; op2val:0x3a3a; +op3val:0x3425; valaddr_reg:x1; val_offset:4845*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 4845*FLEN/8, x4, x2, x6) + +inst_1648: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1f7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x23a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x025 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35f7; op2val:0x3a3a; +op3val:0x3425; valaddr_reg:x1; val_offset:4848*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 4848*FLEN/8, x4, x2, x6) + +inst_1649: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1f7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x23a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x025 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35f7; op2val:0x3a3a; +op3val:0x3425; valaddr_reg:x1; val_offset:4851*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 4851*FLEN/8, x4, x2, x6) + +inst_1650: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x074 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x323 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x373 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3874; op2val:0x3b23; +op3val:0x3773; valaddr_reg:x1; val_offset:4854*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 4854*FLEN/8, x4, x2, x6) + +inst_1651: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x074 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x323 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x373 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3874; op2val:0x3b23; +op3val:0x3773; valaddr_reg:x1; val_offset:4857*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 4857*FLEN/8, x4, x2, x6) + +inst_1652: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x074 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x323 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x373 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3874; op2val:0x3b23; +op3val:0x3773; valaddr_reg:x1; val_offset:4860*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 4860*FLEN/8, x4, x2, x6) + +inst_1653: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x074 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x323 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x373 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3874; op2val:0x3b23; +op3val:0x3773; valaddr_reg:x1; val_offset:4863*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 4863*FLEN/8, x4, x2, x6) + +inst_1654: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x074 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x323 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x373 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3874; op2val:0x3b23; +op3val:0x3773; valaddr_reg:x1; val_offset:4866*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 4866*FLEN/8, x4, x2, x6) + +inst_1655: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b1 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x08c and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3bf and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bb1; op2val:0x348c; +op3val:0x33bf; valaddr_reg:x1; val_offset:4869*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 4869*FLEN/8, x4, x2, x6) + +inst_1656: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b1 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x08c and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3bf and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bb1; op2val:0x348c; +op3val:0x33bf; valaddr_reg:x1; val_offset:4872*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 4872*FLEN/8, x4, x2, x6) + +inst_1657: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b1 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x08c and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3bf and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bb1; op2val:0x348c; +op3val:0x33bf; valaddr_reg:x1; val_offset:4875*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 4875*FLEN/8, x4, x2, x6) + +inst_1658: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b1 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x08c and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3bf and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bb1; op2val:0x348c; +op3val:0x33bf; valaddr_reg:x1; val_offset:4878*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 4878*FLEN/8, x4, x2, x6) + +inst_1659: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b1 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x08c and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3bf and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bb1; op2val:0x348c; +op3val:0x33bf; valaddr_reg:x1; val_offset:4881*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 4881*FLEN/8, x4, x2, x6) + +inst_1660: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x232 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1c9 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x2f7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a32; op2val:0x31c9; +op3val:0x2ef7; valaddr_reg:x1; val_offset:4884*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 4884*FLEN/8, x4, x2, x6) + +inst_1661: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x232 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1c9 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x2f7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a32; op2val:0x31c9; +op3val:0x2ef7; valaddr_reg:x1; val_offset:4887*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 4887*FLEN/8, x4, x2, x6) + +inst_1662: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x232 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1c9 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x2f7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a32; op2val:0x31c9; +op3val:0x2ef7; valaddr_reg:x1; val_offset:4890*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 4890*FLEN/8, x4, x2, x6) + +inst_1663: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x232 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1c9 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x2f7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a32; op2val:0x31c9; +op3val:0x2ef7; valaddr_reg:x1; val_offset:4893*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 4893*FLEN/8, x4, x2, x6) + +inst_1664: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x232 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1c9 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x2f7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a32; op2val:0x31c9; +op3val:0x2ef7; valaddr_reg:x1; val_offset:4896*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 4896*FLEN/8, x4, x2, x6) + +inst_1665: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3de and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35fe; op2val:0x3fde; +op3val:0x39a5; valaddr_reg:x1; val_offset:4899*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 4899*FLEN/8, x4, x2, x6) + +inst_1666: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3de and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35fe; op2val:0x3fde; +op3val:0x39a5; valaddr_reg:x1; val_offset:4902*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 4902*FLEN/8, x4, x2, x6) + +inst_1667: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3de and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35fe; op2val:0x3fde; +op3val:0x39a5; valaddr_reg:x1; val_offset:4905*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 4905*FLEN/8, x4, x2, x6) + +inst_1668: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3de and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35fe; op2val:0x3fde; +op3val:0x39a5; valaddr_reg:x1; val_offset:4908*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 4908*FLEN/8, x4, x2, x6) + +inst_1669: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3de and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35fe; op2val:0x3fde; +op3val:0x39a5; valaddr_reg:x1; val_offset:4911*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 4911*FLEN/8, x4, x2, x6) + +inst_1670: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x302 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x330 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x20c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b02; op2val:0x3b30; +op3val:0x3a0c; valaddr_reg:x1; val_offset:4914*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 4914*FLEN/8, x4, x2, x6) + +inst_1671: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x302 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x330 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x20c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b02; op2val:0x3b30; +op3val:0x3a0c; valaddr_reg:x1; val_offset:4917*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 4917*FLEN/8, x4, x2, x6) + +inst_1672: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x302 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x330 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x20c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b02; op2val:0x3b30; +op3val:0x3a0c; valaddr_reg:x1; val_offset:4920*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 4920*FLEN/8, x4, x2, x6) + +inst_1673: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x302 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x330 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x20c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b02; op2val:0x3b30; +op3val:0x3a0c; valaddr_reg:x1; val_offset:4923*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 4923*FLEN/8, x4, x2, x6) + +inst_1674: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x302 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x330 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x20c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b02; op2val:0x3b30; +op3val:0x3a0c; valaddr_reg:x1; val_offset:4926*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 4926*FLEN/8, x4, x2, x6) + +inst_1675: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x223 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x364 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x12c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3623; op2val:0x3b64; +op3val:0x352c; valaddr_reg:x1; val_offset:4929*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 4929*FLEN/8, x4, x2, x6) + +inst_1676: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x223 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x364 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x12c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3623; op2val:0x3b64; +op3val:0x352c; valaddr_reg:x1; val_offset:4932*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 4932*FLEN/8, x4, x2, x6) + +inst_1677: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x223 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x364 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x12c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3623; op2val:0x3b64; +op3val:0x352c; valaddr_reg:x1; val_offset:4935*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 4935*FLEN/8, x4, x2, x6) + +inst_1678: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x223 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x364 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x12c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3623; op2val:0x3b64; +op3val:0x352c; valaddr_reg:x1; val_offset:4938*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 4938*FLEN/8, x4, x2, x6) + +inst_1679: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x223 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x364 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x12c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3623; op2val:0x3b64; +op3val:0x352c; valaddr_reg:x1; val_offset:4941*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 4941*FLEN/8, x4, x2, x6) + +inst_1680: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x168 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x105 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2cb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3968; op2val:0x3d05; +op3val:0x3acb; valaddr_reg:x1; val_offset:4944*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 4944*FLEN/8, x4, x2, x6) + +inst_1681: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x168 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x105 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2cb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3968; op2val:0x3d05; +op3val:0x3acb; valaddr_reg:x1; val_offset:4947*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 4947*FLEN/8, x4, x2, x6) + +inst_1682: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x168 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x105 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2cb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3968; op2val:0x3d05; +op3val:0x3acb; valaddr_reg:x1; val_offset:4950*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 4950*FLEN/8, x4, x2, x6) + +inst_1683: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x168 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x105 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2cb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3968; op2val:0x3d05; +op3val:0x3acb; valaddr_reg:x1; val_offset:4953*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 4953*FLEN/8, x4, x2, x6) + +inst_1684: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x195 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x150 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x36b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3595; op2val:0x4150; +op3val:0x3b6b; valaddr_reg:x1; val_offset:4956*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 4956*FLEN/8, x4, x2, x6) + +inst_1685: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x195 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x150 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x36b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3595; op2val:0x4150; +op3val:0x3b6b; valaddr_reg:x1; val_offset:4959*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 4959*FLEN/8, x4, x2, x6) + +inst_1686: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x36d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x177 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x113 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x376d; op2val:0x3d77; +op3val:0x3913; valaddr_reg:x1; val_offset:4962*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 4962*FLEN/8, x4, x2, x6) + +inst_1687: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x36d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x177 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x113 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x376d; op2val:0x3d77; +op3val:0x3913; valaddr_reg:x1; val_offset:4965*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 4965*FLEN/8, x4, x2, x6) + +inst_1688: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x389 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x02e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3e1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b89; op2val:0x382e; +op3val:0x37e1; valaddr_reg:x1; val_offset:4968*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 4968*FLEN/8, x4, x2, x6) + +inst_1689: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x389 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x02e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3e1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b89; op2val:0x382e; +op3val:0x37e1; valaddr_reg:x1; val_offset:4971*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x1, 4971*FLEN/8, x4, x2, x6) + +inst_1690: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0b5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x087 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bb3; op2val:0x38b5; +op3val:0x3887; valaddr_reg:x1; val_offset:4974*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 4974*FLEN/8, x4, x2, x6) + +inst_1691: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x370 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3d2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x346 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b70; op2val:0x3bd2; +op3val:0x3b46; valaddr_reg:x1; val_offset:4977*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 4977*FLEN/8, x4, x2, x6) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(14696,32,FLEN) +NAN_BOXED(14696,32,FLEN) +NAN_BOXED(14696,32,FLEN) +NAN_BOXED(14696,32,FLEN) +NAN_BOXED(15621,32,FLEN) +NAN_BOXED(15051,32,FLEN) +NAN_BOXED(14696,32,FLEN) +NAN_BOXED(14696,32,FLEN) +NAN_BOXED(15051,32,FLEN) +NAN_BOXED(14696,32,FLEN) +NAN_BOXED(15621,32,FLEN) +NAN_BOXED(15621,32,FLEN) +NAN_BOXED(14696,32,FLEN) +NAN_BOXED(14696,32,FLEN) +NAN_BOXED(14696,32,FLEN) +NAN_BOXED(13717,32,FLEN) +NAN_BOXED(16720,32,FLEN) +NAN_BOXED(15211,32,FLEN) +NAN_BOXED(13717,32,FLEN) +NAN_BOXED(16720,32,FLEN) +NAN_BOXED(15211,32,FLEN) +NAN_BOXED(13717,32,FLEN) +NAN_BOXED(16720,32,FLEN) +NAN_BOXED(15211,32,FLEN) +NAN_BOXED(13717,32,FLEN) +NAN_BOXED(16720,32,FLEN) +NAN_BOXED(16720,32,FLEN) +NAN_BOXED(13717,32,FLEN) +NAN_BOXED(13717,32,FLEN) +NAN_BOXED(15211,32,FLEN) +NAN_BOXED(14189,32,FLEN) +NAN_BOXED(15735,32,FLEN) +NAN_BOXED(14189,32,FLEN) +NAN_BOXED(14189,32,FLEN) +NAN_BOXED(15735,32,FLEN) +NAN_BOXED(14189,32,FLEN) +test_dataset_1: +NAN_BOXED(14189,32,FLEN) +NAN_BOXED(15735,32,FLEN) +NAN_BOXED(14611,32,FLEN) +NAN_BOXED(14189,32,FLEN) +NAN_BOXED(15735,32,FLEN) +NAN_BOXED(14611,32,FLEN) +NAN_BOXED(14189,32,FLEN) +NAN_BOXED(15735,32,FLEN) +NAN_BOXED(14611,32,FLEN) +NAN_BOXED(15241,32,FLEN) +NAN_BOXED(14382,32,FLEN) +NAN_BOXED(14305,32,FLEN) +NAN_BOXED(15241,32,FLEN) +NAN_BOXED(14382,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(15241,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(14305,32,FLEN) +NAN_BOXED(15241,32,FLEN) +NAN_BOXED(14382,32,FLEN) +NAN_BOXED(14305,32,FLEN) +NAN_BOXED(15241,32,FLEN) +NAN_BOXED(14382,32,FLEN) +NAN_BOXED(14305,32,FLEN) +NAN_BOXED(15283,32,FLEN) +NAN_BOXED(14517,32,FLEN) +NAN_BOXED(14471,32,FLEN) +NAN_BOXED(15283,32,FLEN) +NAN_BOXED(14517,32,FLEN) +NAN_BOXED(14471,32,FLEN) +NAN_BOXED(15283,32,FLEN) +NAN_BOXED(14517,32,FLEN) +NAN_BOXED(14471,32,FLEN) +test_dataset_2: +NAN_BOXED(15283,32,FLEN) +NAN_BOXED(14517,32,FLEN) +NAN_BOXED(14471,32,FLEN) +NAN_BOXED(15283,32,FLEN) +NAN_BOXED(14517,32,FLEN) +NAN_BOXED(14471,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(15314,32,FLEN) +NAN_BOXED(15174,32,FLEN) +NAN_BOXED(15216,32,FLEN) +NAN_BOXED(15314,32,FLEN) +NAN_BOXED(15174,32,FLEN) +NAN_BOXED(15216,32,FLEN) +NAN_BOXED(15314,32,FLEN) +NAN_BOXED(15174,32,FLEN) +NAN_BOXED(15216,32,FLEN) +NAN_BOXED(15314,32,FLEN) +NAN_BOXED(15174,32,FLEN) +NAN_BOXED(15216,32,FLEN) +NAN_BOXED(15314,32,FLEN) +NAN_BOXED(15174,32,FLEN) +NAN_BOXED(14490,32,FLEN) +NAN_BOXED(13520,32,FLEN) +NAN_BOXED(12682,32,FLEN) +NAN_BOXED(14490,32,FLEN) +NAN_BOXED(13520,32,FLEN) +NAN_BOXED(12682,32,FLEN) +test_dataset_3: +NAN_BOXED(14490,16,FLEN) +NAN_BOXED(13520,16,FLEN) +NAN_BOXED(12682,16,FLEN) +NAN_BOXED(14490,16,FLEN) +NAN_BOXED(13520,16,FLEN) +NAN_BOXED(12682,16,FLEN) +NAN_BOXED(14490,16,FLEN) +NAN_BOXED(13520,16,FLEN) +NAN_BOXED(12682,16,FLEN) +NAN_BOXED(15106,16,FLEN) +NAN_BOXED(15127,16,FLEN) +NAN_BOXED(14902,16,FLEN) +NAN_BOXED(15106,16,FLEN) +NAN_BOXED(15127,16,FLEN) +NAN_BOXED(14902,16,FLEN) +NAN_BOXED(15106,16,FLEN) +NAN_BOXED(15127,16,FLEN) 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+NAN_BOXED(16720,16,FLEN) +NAN_BOXED(15211,16,FLEN) +NAN_BOXED(13717,16,FLEN) +NAN_BOXED(16720,16,FLEN) +NAN_BOXED(15211,16,FLEN) +NAN_BOXED(14189,16,FLEN) +NAN_BOXED(15735,16,FLEN) +NAN_BOXED(14611,16,FLEN) +NAN_BOXED(14189,16,FLEN) +NAN_BOXED(15735,16,FLEN) +NAN_BOXED(14611,16,FLEN) +NAN_BOXED(15241,16,FLEN) +NAN_BOXED(14382,16,FLEN) +NAN_BOXED(14305,16,FLEN) +NAN_BOXED(15241,16,FLEN) +NAN_BOXED(14382,16,FLEN) +NAN_BOXED(14305,16,FLEN) +NAN_BOXED(15283,16,FLEN) +NAN_BOXED(14517,16,FLEN) +NAN_BOXED(14471,16,FLEN) +NAN_BOXED(15216,16,FLEN) +NAN_BOXED(15314,16,FLEN) +NAN_BOXED(15174,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x4_0: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_0: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_1: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_2: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_3: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_4: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_5: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_6: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_7: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_8: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_9: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_10: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_11: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_12: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fmul_b1-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fmul_b1-01.S new file mode 100644 index 000000000..55bc8bd01 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fmul_b1-01.S @@ -0,0 +1,5934 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 04:50:26 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fmul.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fmul.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fmul_b1 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fmul_b1) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x13,test_dataset_0) +RVTEST_SIGBASE(x3,signature_x3_1) + +inst_0: +// rs1 == rd != rs2, rs1==x18, rs2==x9, rd==x18,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x18; op2:x9; dest:x18; op1val:0x0; op2val:0x0; + valaddr_reg:x13; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fmul.h, x18, x18, x9, dyn, 0, 0, x13, 0*FLEN/8, x17, x3, x4) + +inst_1: +// rs1 == rs2 == rd, rs1==x31, rs2==x31, rd==x31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x31; op2:x31; dest:x31; op1val:0x0; op2val:0x0; + valaddr_reg:x13; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fmul.h, x31, x31, x31, dyn, 0, 0, x13, 2*FLEN/8, x17, x3, x4) + +inst_2: +// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==x9, rs2==x30, rd==x28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x9; op2:x30; dest:x28; op1val:0x0; op2val:0x1; + valaddr_reg:x13; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fmul.h, x28, x9, x30, dyn, 0, 0, x13, 4*FLEN/8, x17, x3, x4) + +inst_3: +// rs1 == rs2 != rd, rs1==x21, rs2==x21, rd==x12,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x21; op2:x21; dest:x12; op1val:0x0; op2val:0x0; + valaddr_reg:x13; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fmul.h, x12, x21, x21, dyn, 0, 0, x13, 6*FLEN/8, x17, x3, x4) + +inst_4: +// rs2 == rd != rs1, rs1==x1, rs2==x14, rd==x14,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x1; op2:x14; dest:x14; op1val:0x0; op2val:0x2; + valaddr_reg:x13; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fmul.h, x14, x1, x14, dyn, 0, 0, x13, 8*FLEN/8, x17, x3, x4) + +inst_5: +// rs1==x6, rs2==x1, rd==x10,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x6; op2:x1; dest:x10; op1val:0x0; op2val:0x83fe; + valaddr_reg:x13; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fmul.h, x10, x6, x1, dyn, 0, 0, x13, 10*FLEN/8, x17, x3, x4) + +inst_6: +// rs1==x22, rs2==x0, rd==x16,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x22; op2:x0; dest:x16; op1val:0x0; op2val:0x0; + valaddr_reg:x13; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fmul.h, x16, x22, x0, dyn, 0, 0, x13, 12*FLEN/8, x17, x3, x4) + +inst_7: +// rs1==x29, rs2==x15, rd==x8,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x29; op2:x15; dest:x8; op1val:0x0; op2val:0x83ff; + valaddr_reg:x13; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fmul.h, x8, x29, x15, dyn, 0, 0, x13, 14*FLEN/8, x17, x3, x4) + +inst_8: +// rs1==x7, rs2==x20, rd==x29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x7; op2:x20; dest:x29; op1val:0x0; op2val:0x400; + valaddr_reg:x13; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fmul.h, x29, x7, x20, dyn, 0, 0, x13, 16*FLEN/8, x17, x3, x4) + +inst_9: +// rs1==x12, rs2==x29, rd==x15,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x12; op2:x29; dest:x15; op1val:0x0; op2val:0x8400; + valaddr_reg:x13; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fmul.h, x15, x12, x29, dyn, 0, 0, x13, 18*FLEN/8, x17, x3, x4) + +inst_10: +// rs1==x30, rs2==x6, rd==x19,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x6; dest:x19; op1val:0x0; op2val:0x401; + valaddr_reg:x13; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fmul.h, x19, x30, x6, dyn, 0, 0, x13, 20*FLEN/8, x17, x3, x4) + +inst_11: +// rs1==x28, rs2==x25, rd==x23,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x28; op2:x25; dest:x23; op1val:0x0; op2val:0x8455; + valaddr_reg:x13; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fmul.h, x23, x28, x25, dyn, 0, 0, x13, 22*FLEN/8, x17, x3, x4) + +inst_12: +// rs1==x14, rs2==x11, rd==x0,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x14; op2:x11; dest:x0; op1val:0x0; op2val:0x7bff; + valaddr_reg:x13; val_offset:24*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fmul.h, x0, x14, x11, dyn, 0, 0, x13, 24*FLEN/8, x17, x3, x4) + +inst_13: +// rs1==x2, rs2==x28, rd==x5,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x2; op2:x28; dest:x5; op1val:0x0; op2val:0xfbff; + valaddr_reg:x13; val_offset:26*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fmul.h, x5, x2, x28, dyn, 0, 0, x13, 26*FLEN/8, x17, x3, x4) +RVTEST_VALBASEUPD(x2,test_dataset_1) + +inst_14: +// rs1==x16, rs2==x17, rd==x7,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x16; op2:x17; dest:x7; op1val:0x0; op2val:0x7c00; + valaddr_reg:x2; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4 +*/ +TEST_FPRR_OP(fmul.h, x7, x16, x17, dyn, 0, 0, x2, 0*FLEN/8, x6, x3, x4) + +inst_15: +// rs1==x17, rs2==x19, rd==x27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x17; op2:x19; dest:x27; op1val:0x0; op2val:0xfc00; + valaddr_reg:x2; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x28 +*/ +TEST_FPRR_OP(fmul.h, x27, x17, x19, dyn, 0, 0, x2, 2*FLEN/8, x6, x3, x28) +RVTEST_SIGBASE(x14,signature_x14_0) + +inst_16: +// rs1==x26, rs2==x10, rd==x21,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x26; op2:x10; dest:x21; op1val:0x0; op2val:0x7e00; + valaddr_reg:x2; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x28 +*/ +TEST_FPRR_OP(fmul.h, x21, x26, x10, dyn, 0, 0, x2, 4*FLEN/8, x6, x14, x28) + +inst_17: +// rs1==x23, rs2==x22, rd==x24,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x23; op2:x22; dest:x24; op1val:0x0; op2val:0xfe00; + valaddr_reg:x2; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x28 +*/ +TEST_FPRR_OP(fmul.h, x24, x23, x22, dyn, 0, 0, x2, 6*FLEN/8, x6, x14, x28) + +inst_18: +// rs1==x24, rs2==x16, rd==x4,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x24; op2:x16; dest:x4; op1val:0x0; op2val:0x7e01; + valaddr_reg:x2; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x28 +*/ +TEST_FPRR_OP(fmul.h, x4, x24, x16, dyn, 0, 0, x2, 8*FLEN/8, x6, x14, x28) + +inst_19: +// rs1==x8, rs2==x13, rd==x26,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x8; op2:x13; dest:x26; op1val:0x0; op2val:0xfe55; + valaddr_reg:x2; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x28 +*/ +TEST_FPRR_OP(fmul.h, x26, x8, x13, dyn, 0, 0, x2, 10*FLEN/8, x6, x14, x28) + +inst_20: +// rs1==x20, rs2==x8, rd==x25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x20; op2:x8; dest:x25; op1val:0x0; op2val:0x7c01; + valaddr_reg:x2; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x28 +*/ +TEST_FPRR_OP(fmul.h, x25, x20, x8, dyn, 0, 0, x2, 12*FLEN/8, x6, x14, x28) + +inst_21: +// rs1==x5, rs2==x26, rd==x3,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x5; op2:x26; dest:x3; op1val:0x0; op2val:0xfd55; + valaddr_reg:x2; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x28 +*/ +TEST_FPRR_OP(fmul.h, x3, x5, x26, dyn, 0, 0, x2, 14*FLEN/8, x6, x14, x28) + +inst_22: +// rs1==x10, rs2==x24, rd==x22,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x10; op2:x24; dest:x22; op1val:0x0; op2val:0x3c00; + valaddr_reg:x2; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x28 +*/ +TEST_FPRR_OP(fmul.h, x22, x10, x24, dyn, 0, 0, x2, 16*FLEN/8, x6, x14, x28) + +inst_23: +// rs1==x3, rs2==x23, rd==x9,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x3; op2:x23; dest:x9; op1val:0x0; op2val:0xbc00; + valaddr_reg:x2; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x28 +*/ +TEST_FPRR_OP(fmul.h, x9, x3, x23, dyn, 0, 0, x2, 18*FLEN/8, x6, x14, x28) + +inst_24: +// rs1==x4, rs2==x12, rd==x30,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x4; op2:x12; dest:x30; op1val:0x8000; op2val:0x0; + valaddr_reg:x2; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x28 +*/ +TEST_FPRR_OP(fmul.h, x30, x4, x12, dyn, 0, 0, x2, 20*FLEN/8, x6, x14, x28) + +inst_25: +// rs1==x11, rs2==x4, rd==x20,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x11; op2:x4; dest:x20; op1val:0x8000; op2val:0x8000; + valaddr_reg:x2; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x28 +*/ +TEST_FPRR_OP(fmul.h, x20, x11, x4, dyn, 0, 0, x2, 22*FLEN/8, x6, x14, x28) + +inst_26: +// rs1==x0, rs2==x27, rd==x1,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x0; op2:x27; dest:x1; op1val:0x0; op2val:0x1; + valaddr_reg:x2; val_offset:24*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x28 +*/ +TEST_FPRR_OP(fmul.h, x1, x0, x27, dyn, 0, 0, x2, 24*FLEN/8, x6, x14, x28) +RVTEST_VALBASEUPD(x4,test_dataset_2) + +inst_27: +// rs1==x19, rs2==x7, rd==x13,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x19; op2:x7; dest:x13; op1val:0x8000; op2val:0x8001; + valaddr_reg:x4; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x28 +*/ +TEST_FPRR_OP(fmul.h, x13, x19, x7, dyn, 0, 0, x4, 0*FLEN/8, x8, x14, x28) + +inst_28: +// rs1==x25, rs2==x3, rd==x6,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x25; op2:x3; dest:x6; op1val:0x8000; op2val:0x2; + valaddr_reg:x4; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x28 +*/ +TEST_FPRR_OP(fmul.h, x6, x25, x3, dyn, 0, 0, x4, 2*FLEN/8, x8, x14, x28) + +inst_29: +// rs1==x15, rs2==x18, rd==x2,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x15; op2:x18; dest:x2; op1val:0x8000; op2val:0x83fe; + valaddr_reg:x4; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x28 +*/ +TEST_FPRR_OP(fmul.h, x2, x15, x18, dyn, 0, 0, x4, 4*FLEN/8, x8, x14, x28) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_30: +// rs1==x13, rs2==x5, rd==x11,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x13; op2:x5; dest:x11; op1val:0x8000; op2val:0x3ff; + valaddr_reg:x4; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x11, x13, x5, dyn, 0, 0, x4, 6*FLEN/8, x8, x1, x3) + +inst_31: +// rs1==x27, rs2==x2, rd==x17,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x27; op2:x2; dest:x17; op1val:0x8000; op2val:0x83ff; + valaddr_reg:x4; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x17, x27, x2, dyn, 0, 0, x4, 8*FLEN/8, x8, x1, x3) + +inst_32: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x400; + valaddr_reg:x4; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 10*FLEN/8, x8, x1, x3) + +inst_33: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8400; + valaddr_reg:x4; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 12*FLEN/8, x8, x1, x3) + +inst_34: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x401; + valaddr_reg:x4; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 14*FLEN/8, x8, x1, x3) + +inst_35: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8455; + valaddr_reg:x4; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 16*FLEN/8, x8, x1, x3) + +inst_36: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x7bff; + valaddr_reg:x4; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 18*FLEN/8, x8, x1, x3) + +inst_37: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xfbff; + valaddr_reg:x4; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 20*FLEN/8, x8, x1, x3) + +inst_38: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x7c00; + valaddr_reg:x4; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 22*FLEN/8, x8, x1, x3) + +inst_39: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xfc00; + valaddr_reg:x4; val_offset:24*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 24*FLEN/8, x8, x1, x3) + +inst_40: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x7e00; + valaddr_reg:x4; val_offset:26*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 26*FLEN/8, x8, x1, x3) + +inst_41: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xfe00; + valaddr_reg:x4; val_offset:28*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 28*FLEN/8, x8, x1, x3) + +inst_42: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x7e01; + valaddr_reg:x4; val_offset:30*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 30*FLEN/8, x8, x1, x3) + +inst_43: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xfe55; + valaddr_reg:x4; val_offset:32*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 32*FLEN/8, x8, x1, x3) + +inst_44: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x7c01; + valaddr_reg:x4; val_offset:34*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 34*FLEN/8, x8, x1, x3) + +inst_45: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xfd55; + valaddr_reg:x4; val_offset:36*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 36*FLEN/8, x8, x1, x3) + +inst_46: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x3c00; + valaddr_reg:x4; val_offset:38*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 38*FLEN/8, x8, x1, x3) + +inst_47: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xbc00; + valaddr_reg:x4; val_offset:40*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 40*FLEN/8, x8, x1, x3) + +inst_48: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x0; + valaddr_reg:x4; val_offset:42*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 42*FLEN/8, x8, x1, x3) + +inst_49: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x8000; + valaddr_reg:x4; val_offset:44*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 44*FLEN/8, x8, x1, x3) + +inst_50: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x1; + valaddr_reg:x4; val_offset:46*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 46*FLEN/8, x8, x1, x3) + +inst_51: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x8001; + valaddr_reg:x4; val_offset:48*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 48*FLEN/8, x8, x1, x3) + +inst_52: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x2; + valaddr_reg:x4; val_offset:50*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 50*FLEN/8, x8, x1, x3) + +inst_53: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x83fe; + valaddr_reg:x4; val_offset:52*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 52*FLEN/8, x8, x1, x3) + +inst_54: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x3ff; + valaddr_reg:x4; val_offset:54*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 54*FLEN/8, x8, x1, x3) + +inst_55: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x83ff; + valaddr_reg:x4; val_offset:56*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 56*FLEN/8, x8, x1, x3) + +inst_56: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x400; + valaddr_reg:x4; val_offset:58*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 58*FLEN/8, x8, x1, x3) + +inst_57: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x8400; + valaddr_reg:x4; val_offset:60*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 60*FLEN/8, x8, x1, x3) + +inst_58: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x401; + valaddr_reg:x4; val_offset:62*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 62*FLEN/8, x8, x1, x3) + +inst_59: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x8455; + valaddr_reg:x4; val_offset:64*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 64*FLEN/8, x8, x1, x3) + +inst_60: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7bff; + valaddr_reg:x4; val_offset:66*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 66*FLEN/8, x8, x1, x3) + +inst_61: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xfbff; + valaddr_reg:x4; val_offset:68*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 68*FLEN/8, x8, x1, x3) + +inst_62: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7c00; + valaddr_reg:x4; val_offset:70*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 70*FLEN/8, x8, x1, x3) + +inst_63: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xfc00; + valaddr_reg:x4; val_offset:72*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 72*FLEN/8, x8, x1, x3) + +inst_64: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7e00; + valaddr_reg:x4; val_offset:74*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 74*FLEN/8, x8, x1, x3) + +inst_65: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xfe00; + valaddr_reg:x4; val_offset:76*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 76*FLEN/8, x8, x1, x3) + +inst_66: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7e01; + valaddr_reg:x4; val_offset:78*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 78*FLEN/8, x8, x1, x3) + +inst_67: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xfe55; + valaddr_reg:x4; val_offset:80*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 80*FLEN/8, x8, x1, x3) + +inst_68: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7c01; + valaddr_reg:x4; val_offset:82*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 82*FLEN/8, x8, x1, x3) + +inst_69: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xfd55; + valaddr_reg:x4; val_offset:84*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 84*FLEN/8, x8, x1, x3) + +inst_70: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x3c00; + valaddr_reg:x4; val_offset:86*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 86*FLEN/8, x8, x1, x3) + +inst_71: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xbc00; + valaddr_reg:x4; val_offset:88*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 88*FLEN/8, x8, x1, x3) + +inst_72: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x0; + valaddr_reg:x4; val_offset:90*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 90*FLEN/8, x8, x1, x3) + +inst_73: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8000; + valaddr_reg:x4; val_offset:92*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 92*FLEN/8, x8, x1, x3) + +inst_74: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x1; + valaddr_reg:x4; val_offset:94*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 94*FLEN/8, x8, x1, x3) + +inst_75: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8001; + valaddr_reg:x4; val_offset:96*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 96*FLEN/8, x8, x1, x3) + +inst_76: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x2; + valaddr_reg:x4; val_offset:98*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 98*FLEN/8, x8, x1, x3) + +inst_77: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x83fe; + valaddr_reg:x4; val_offset:100*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 100*FLEN/8, x8, x1, x3) + +inst_78: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x3ff; + valaddr_reg:x4; val_offset:102*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 102*FLEN/8, x8, x1, x3) + +inst_79: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x83ff; + valaddr_reg:x4; val_offset:104*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 104*FLEN/8, x8, x1, x3) + +inst_80: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x400; + valaddr_reg:x4; val_offset:106*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 106*FLEN/8, x8, x1, x3) + +inst_81: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8400; + valaddr_reg:x4; val_offset:108*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 108*FLEN/8, x8, x1, x3) + +inst_82: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x401; + valaddr_reg:x4; val_offset:110*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 110*FLEN/8, x8, x1, x3) + +inst_83: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8455; + valaddr_reg:x4; val_offset:112*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 112*FLEN/8, x8, x1, x3) + +inst_84: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x7bff; + valaddr_reg:x4; val_offset:114*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 114*FLEN/8, x8, x1, x3) + +inst_85: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xfbff; + valaddr_reg:x4; val_offset:116*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 116*FLEN/8, x8, x1, x3) + +inst_86: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x7c00; + valaddr_reg:x4; val_offset:118*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 118*FLEN/8, x8, x1, x3) + +inst_87: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xfc00; + valaddr_reg:x4; val_offset:120*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 120*FLEN/8, x8, x1, x3) + +inst_88: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x7e00; + valaddr_reg:x4; val_offset:122*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 122*FLEN/8, x8, x1, x3) + +inst_89: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xfe00; + valaddr_reg:x4; val_offset:124*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 124*FLEN/8, x8, x1, x3) + +inst_90: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x7e01; + valaddr_reg:x4; val_offset:126*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 126*FLEN/8, x8, x1, x3) + +inst_91: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xfe55; + valaddr_reg:x4; val_offset:128*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 128*FLEN/8, x8, x1, x3) + +inst_92: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x7c01; + valaddr_reg:x4; val_offset:130*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 130*FLEN/8, x8, x1, x3) + +inst_93: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xfd55; + valaddr_reg:x4; val_offset:132*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 132*FLEN/8, x8, x1, x3) + +inst_94: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x3c00; + valaddr_reg:x4; val_offset:134*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 134*FLEN/8, x8, x1, x3) + +inst_95: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xbc00; + valaddr_reg:x4; val_offset:136*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 136*FLEN/8, x8, x1, x3) + +inst_96: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x0; + valaddr_reg:x4; val_offset:138*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 138*FLEN/8, x8, x1, x3) + +inst_97: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x8000; + valaddr_reg:x4; val_offset:140*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 140*FLEN/8, x8, x1, x3) + +inst_98: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x1; + valaddr_reg:x4; val_offset:142*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 142*FLEN/8, x8, x1, x3) + +inst_99: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x8001; + valaddr_reg:x4; val_offset:144*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 144*FLEN/8, x8, x1, x3) + +inst_100: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x2; + valaddr_reg:x4; val_offset:146*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 146*FLEN/8, x8, x1, x3) + +inst_101: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x83fe; + valaddr_reg:x4; val_offset:148*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 148*FLEN/8, x8, x1, x3) + +inst_102: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x3ff; + valaddr_reg:x4; val_offset:150*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 150*FLEN/8, x8, x1, x3) + +inst_103: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x83ff; + valaddr_reg:x4; val_offset:152*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 152*FLEN/8, x8, x1, x3) + +inst_104: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x400; + valaddr_reg:x4; val_offset:154*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 154*FLEN/8, x8, x1, x3) + +inst_105: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x8400; + valaddr_reg:x4; val_offset:156*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 156*FLEN/8, x8, x1, x3) + +inst_106: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x401; + valaddr_reg:x4; val_offset:158*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 158*FLEN/8, x8, x1, x3) + +inst_107: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x8455; + valaddr_reg:x4; val_offset:160*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 160*FLEN/8, x8, x1, x3) + +inst_108: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x7bff; + valaddr_reg:x4; val_offset:162*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 162*FLEN/8, x8, x1, x3) + +inst_109: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xfbff; + valaddr_reg:x4; val_offset:164*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 164*FLEN/8, x8, x1, x3) + +inst_110: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x7c00; + valaddr_reg:x4; val_offset:166*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 166*FLEN/8, x8, x1, x3) + +inst_111: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xfc00; + valaddr_reg:x4; val_offset:168*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 168*FLEN/8, x8, x1, x3) + +inst_112: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x7e00; + valaddr_reg:x4; val_offset:170*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 170*FLEN/8, x8, x1, x3) + +inst_113: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xfe00; + valaddr_reg:x4; val_offset:172*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 172*FLEN/8, x8, x1, x3) + +inst_114: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x7e01; + valaddr_reg:x4; val_offset:174*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 174*FLEN/8, x8, x1, x3) + +inst_115: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xfe55; + valaddr_reg:x4; val_offset:176*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 176*FLEN/8, x8, x1, x3) + +inst_116: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x7c01; + valaddr_reg:x4; val_offset:178*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 178*FLEN/8, x8, x1, x3) + +inst_117: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xfd55; + valaddr_reg:x4; val_offset:180*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 180*FLEN/8, x8, x1, x3) + +inst_118: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x3c00; + valaddr_reg:x4; val_offset:182*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 182*FLEN/8, x8, x1, x3) + +inst_119: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xbc00; + valaddr_reg:x4; val_offset:184*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 184*FLEN/8, x8, x1, x3) + +inst_120: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x0; + valaddr_reg:x4; val_offset:186*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 186*FLEN/8, x8, x1, x3) + +inst_121: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x8000; + valaddr_reg:x4; val_offset:188*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 188*FLEN/8, x8, x1, x3) + +inst_122: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x1; + valaddr_reg:x4; val_offset:190*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 190*FLEN/8, x8, x1, x3) + +inst_123: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x8001; + valaddr_reg:x4; val_offset:192*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 192*FLEN/8, x8, x1, x3) + +inst_124: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x2; + valaddr_reg:x4; val_offset:194*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 194*FLEN/8, x8, x1, x3) + +inst_125: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x83fe; + valaddr_reg:x4; val_offset:196*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 196*FLEN/8, x8, x1, x3) + +inst_126: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x3ff; + valaddr_reg:x4; val_offset:198*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 198*FLEN/8, x8, x1, x3) + +inst_127: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x83ff; + valaddr_reg:x4; val_offset:200*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 200*FLEN/8, x8, x1, x3) + +inst_128: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x400; + valaddr_reg:x4; val_offset:202*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 202*FLEN/8, x8, x1, x3) + +inst_129: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x8400; + valaddr_reg:x4; val_offset:204*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 204*FLEN/8, x8, x1, x3) + +inst_130: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x401; + valaddr_reg:x4; val_offset:206*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 206*FLEN/8, x8, x1, x3) + +inst_131: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x8455; + valaddr_reg:x4; val_offset:208*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 208*FLEN/8, x8, x1, x3) + +inst_132: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x7bff; + valaddr_reg:x4; val_offset:210*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 210*FLEN/8, x8, x1, x3) + +inst_133: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xfbff; + valaddr_reg:x4; val_offset:212*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 212*FLEN/8, x8, x1, x3) + +inst_134: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x7c00; + valaddr_reg:x4; val_offset:214*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 214*FLEN/8, x8, x1, x3) + +inst_135: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xfc00; + valaddr_reg:x4; val_offset:216*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 216*FLEN/8, x8, x1, x3) + +inst_136: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x7e00; + valaddr_reg:x4; val_offset:218*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 218*FLEN/8, x8, x1, x3) + +inst_137: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xfe00; + valaddr_reg:x4; val_offset:220*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 220*FLEN/8, x8, x1, x3) + +inst_138: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x7e01; + valaddr_reg:x4; val_offset:222*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 222*FLEN/8, x8, x1, x3) + +inst_139: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xfe55; + valaddr_reg:x4; val_offset:224*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 224*FLEN/8, x8, x1, x3) + +inst_140: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x7c01; + valaddr_reg:x4; val_offset:226*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 226*FLEN/8, x8, x1, x3) + +inst_141: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xfd55; + valaddr_reg:x4; val_offset:228*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 228*FLEN/8, x8, x1, x3) + +inst_142: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x3c00; + valaddr_reg:x4; val_offset:230*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 230*FLEN/8, x8, x1, x3) + +inst_143: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xbc00; + valaddr_reg:x4; val_offset:232*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 232*FLEN/8, x8, x1, x3) + +inst_144: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x0; + valaddr_reg:x4; val_offset:234*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 234*FLEN/8, x8, x1, x3) + +inst_145: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x8000; + valaddr_reg:x4; val_offset:236*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 236*FLEN/8, x8, x1, x3) + +inst_146: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x1; + valaddr_reg:x4; val_offset:238*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 238*FLEN/8, x8, x1, x3) + +inst_147: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x8001; + valaddr_reg:x4; val_offset:240*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 240*FLEN/8, x8, x1, x3) + +inst_148: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x2; + valaddr_reg:x4; val_offset:242*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 242*FLEN/8, x8, x1, x3) + +inst_149: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x83fe; + valaddr_reg:x4; val_offset:244*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 244*FLEN/8, x8, x1, x3) + +inst_150: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x3ff; + valaddr_reg:x4; val_offset:246*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 246*FLEN/8, x8, x1, x3) + +inst_151: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x83ff; + valaddr_reg:x4; val_offset:248*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 248*FLEN/8, x8, x1, x3) + +inst_152: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x400; + valaddr_reg:x4; val_offset:250*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 250*FLEN/8, x8, x1, x3) + +inst_153: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x8400; + valaddr_reg:x4; val_offset:252*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 252*FLEN/8, x8, x1, x3) + +inst_154: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x401; + valaddr_reg:x4; val_offset:254*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 254*FLEN/8, x8, x1, x3) + +inst_155: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x8455; + valaddr_reg:x4; val_offset:256*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 256*FLEN/8, x8, x1, x3) + +inst_156: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7bff; + valaddr_reg:x4; val_offset:258*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 258*FLEN/8, x8, x1, x3) + +inst_157: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xfbff; + valaddr_reg:x4; val_offset:260*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 260*FLEN/8, x8, x1, x3) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_158: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7c00; + valaddr_reg:x4; val_offset:262*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 262*FLEN/8, x8, x1, x3) + +inst_159: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xfc00; + valaddr_reg:x4; val_offset:264*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 264*FLEN/8, x8, x1, x3) + +inst_160: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7e00; + valaddr_reg:x4; val_offset:266*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 266*FLEN/8, x8, x1, x3) + +inst_161: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xfe00; + valaddr_reg:x4; val_offset:268*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 268*FLEN/8, x8, x1, x3) + +inst_162: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7e01; + valaddr_reg:x4; val_offset:270*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 270*FLEN/8, x8, x1, x3) + +inst_163: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xfe55; + valaddr_reg:x4; val_offset:272*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 272*FLEN/8, x8, x1, x3) + +inst_164: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7c01; + valaddr_reg:x4; val_offset:274*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 274*FLEN/8, x8, x1, x3) + +inst_165: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xfd55; + valaddr_reg:x4; val_offset:276*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 276*FLEN/8, x8, x1, x3) + +inst_166: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x3c00; + valaddr_reg:x4; val_offset:278*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 278*FLEN/8, x8, x1, x3) + +inst_167: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xbc00; + valaddr_reg:x4; val_offset:280*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 280*FLEN/8, x8, x1, x3) + +inst_168: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x0; + valaddr_reg:x4; val_offset:282*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 282*FLEN/8, x8, x1, x3) + +inst_169: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8000; + valaddr_reg:x4; val_offset:284*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 284*FLEN/8, x8, x1, x3) + +inst_170: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x1; + valaddr_reg:x4; val_offset:286*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 286*FLEN/8, x8, x1, x3) + +inst_171: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8001; + valaddr_reg:x4; val_offset:288*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 288*FLEN/8, x8, x1, x3) + +inst_172: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x2; + valaddr_reg:x4; val_offset:290*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 290*FLEN/8, x8, x1, x3) + +inst_173: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x83fe; + valaddr_reg:x4; val_offset:292*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 292*FLEN/8, x8, x1, x3) + +inst_174: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x3ff; + valaddr_reg:x4; val_offset:294*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 294*FLEN/8, x8, x1, x3) + +inst_175: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x83ff; + valaddr_reg:x4; val_offset:296*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 296*FLEN/8, x8, x1, x3) + +inst_176: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x400; + valaddr_reg:x4; val_offset:298*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 298*FLEN/8, x8, x1, x3) + +inst_177: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8400; + valaddr_reg:x4; val_offset:300*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 300*FLEN/8, x8, x1, x3) + +inst_178: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x401; + valaddr_reg:x4; val_offset:302*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 302*FLEN/8, x8, x1, x3) + +inst_179: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8455; + valaddr_reg:x4; val_offset:304*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 304*FLEN/8, x8, x1, x3) + +inst_180: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x7bff; + valaddr_reg:x4; val_offset:306*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 306*FLEN/8, x8, x1, x3) + +inst_181: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xfbff; + valaddr_reg:x4; val_offset:308*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 308*FLEN/8, x8, x1, x3) + +inst_182: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x7c00; + valaddr_reg:x4; val_offset:310*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 310*FLEN/8, x8, x1, x3) + +inst_183: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xfc00; + valaddr_reg:x4; val_offset:312*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 312*FLEN/8, x8, x1, x3) + +inst_184: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x7e00; + valaddr_reg:x4; val_offset:314*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 314*FLEN/8, x8, x1, x3) + +inst_185: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xfe00; + valaddr_reg:x4; val_offset:316*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 316*FLEN/8, x8, x1, x3) + +inst_186: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x7e01; + valaddr_reg:x4; val_offset:318*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 318*FLEN/8, x8, x1, x3) + +inst_187: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xfe55; + valaddr_reg:x4; val_offset:320*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 320*FLEN/8, x8, x1, x3) + +inst_188: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x7c01; + valaddr_reg:x4; val_offset:322*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 322*FLEN/8, x8, x1, x3) + +inst_189: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xfd55; + valaddr_reg:x4; val_offset:324*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 324*FLEN/8, x8, x1, x3) + +inst_190: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x3c00; + valaddr_reg:x4; val_offset:326*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 326*FLEN/8, x8, x1, x3) + +inst_191: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xbc00; + valaddr_reg:x4; val_offset:328*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 328*FLEN/8, x8, x1, x3) + +inst_192: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x0; + valaddr_reg:x4; val_offset:330*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 330*FLEN/8, x8, x1, x3) + +inst_193: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x8000; + valaddr_reg:x4; val_offset:332*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 332*FLEN/8, x8, x1, x3) + +inst_194: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x1; + valaddr_reg:x4; val_offset:334*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 334*FLEN/8, x8, x1, x3) + +inst_195: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x8001; + valaddr_reg:x4; val_offset:336*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 336*FLEN/8, x8, x1, x3) + +inst_196: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x2; + valaddr_reg:x4; val_offset:338*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 338*FLEN/8, x8, x1, x3) + +inst_197: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x83fe; + valaddr_reg:x4; val_offset:340*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 340*FLEN/8, x8, x1, x3) + +inst_198: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x3ff; + valaddr_reg:x4; val_offset:342*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 342*FLEN/8, x8, x1, x3) + +inst_199: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x83ff; + valaddr_reg:x4; val_offset:344*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 344*FLEN/8, x8, x1, x3) + +inst_200: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x400; + valaddr_reg:x4; val_offset:346*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 346*FLEN/8, x8, x1, x3) + +inst_201: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x8400; + valaddr_reg:x4; val_offset:348*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 348*FLEN/8, x8, x1, x3) + +inst_202: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x401; + valaddr_reg:x4; val_offset:350*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 350*FLEN/8, x8, x1, x3) + +inst_203: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x8455; + valaddr_reg:x4; val_offset:352*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 352*FLEN/8, x8, x1, x3) + +inst_204: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7bff; + valaddr_reg:x4; val_offset:354*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 354*FLEN/8, x8, x1, x3) + +inst_205: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xfbff; + valaddr_reg:x4; val_offset:356*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 356*FLEN/8, x8, x1, x3) + +inst_206: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7c00; + valaddr_reg:x4; val_offset:358*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 358*FLEN/8, x8, x1, x3) + +inst_207: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xfc00; + valaddr_reg:x4; val_offset:360*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 360*FLEN/8, x8, x1, x3) + +inst_208: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7e00; + valaddr_reg:x4; val_offset:362*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 362*FLEN/8, x8, x1, x3) + +inst_209: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xfe00; + valaddr_reg:x4; val_offset:364*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 364*FLEN/8, x8, x1, x3) + +inst_210: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7e01; + valaddr_reg:x4; val_offset:366*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 366*FLEN/8, x8, x1, x3) + +inst_211: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xfe55; + valaddr_reg:x4; val_offset:368*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 368*FLEN/8, x8, x1, x3) + +inst_212: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7c01; + valaddr_reg:x4; val_offset:370*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 370*FLEN/8, x8, x1, x3) + +inst_213: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xfd55; + valaddr_reg:x4; val_offset:372*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 372*FLEN/8, x8, x1, x3) + +inst_214: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x3c00; + valaddr_reg:x4; val_offset:374*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 374*FLEN/8, x8, x1, x3) + +inst_215: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xbc00; + valaddr_reg:x4; val_offset:376*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 376*FLEN/8, x8, x1, x3) + +inst_216: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x0; + valaddr_reg:x4; val_offset:378*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 378*FLEN/8, x8, x1, x3) + +inst_217: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8000; + valaddr_reg:x4; val_offset:380*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 380*FLEN/8, x8, x1, x3) + +inst_218: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x1; + valaddr_reg:x4; val_offset:382*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 382*FLEN/8, x8, x1, x3) + +inst_219: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8001; + valaddr_reg:x4; val_offset:384*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 384*FLEN/8, x8, x1, x3) + +inst_220: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x2; + valaddr_reg:x4; val_offset:386*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 386*FLEN/8, x8, x1, x3) + +inst_221: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x83fe; + valaddr_reg:x4; val_offset:388*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 388*FLEN/8, x8, x1, x3) + +inst_222: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x3ff; + valaddr_reg:x4; val_offset:390*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 390*FLEN/8, x8, x1, x3) + +inst_223: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x83ff; + valaddr_reg:x4; val_offset:392*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 392*FLEN/8, x8, x1, x3) + +inst_224: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x400; + valaddr_reg:x4; val_offset:394*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 394*FLEN/8, x8, x1, x3) + +inst_225: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8400; + valaddr_reg:x4; val_offset:396*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 396*FLEN/8, x8, x1, x3) + +inst_226: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x401; + valaddr_reg:x4; val_offset:398*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 398*FLEN/8, x8, x1, x3) + +inst_227: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8455; + valaddr_reg:x4; val_offset:400*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 400*FLEN/8, x8, x1, x3) + +inst_228: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x7bff; + valaddr_reg:x4; val_offset:402*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 402*FLEN/8, x8, x1, x3) + +inst_229: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xfbff; + valaddr_reg:x4; val_offset:404*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 404*FLEN/8, x8, x1, x3) + +inst_230: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x7c00; + valaddr_reg:x4; val_offset:406*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 406*FLEN/8, x8, x1, x3) + +inst_231: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xfc00; + valaddr_reg:x4; val_offset:408*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 408*FLEN/8, x8, x1, x3) + +inst_232: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x7e00; + valaddr_reg:x4; val_offset:410*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 410*FLEN/8, x8, x1, x3) + +inst_233: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xfe00; + valaddr_reg:x4; val_offset:412*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 412*FLEN/8, x8, x1, x3) + +inst_234: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x7e01; + valaddr_reg:x4; val_offset:414*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 414*FLEN/8, x8, x1, x3) + +inst_235: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xfe55; + valaddr_reg:x4; val_offset:416*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 416*FLEN/8, x8, x1, x3) + +inst_236: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x7c01; + valaddr_reg:x4; val_offset:418*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 418*FLEN/8, x8, x1, x3) + +inst_237: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xfd55; + valaddr_reg:x4; val_offset:420*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 420*FLEN/8, x8, x1, x3) + +inst_238: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x3c00; + valaddr_reg:x4; val_offset:422*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 422*FLEN/8, x8, x1, x3) + +inst_239: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xbc00; + valaddr_reg:x4; val_offset:424*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 424*FLEN/8, x8, x1, x3) + +inst_240: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x0; + valaddr_reg:x4; val_offset:426*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 426*FLEN/8, x8, x1, x3) + +inst_241: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x8000; + valaddr_reg:x4; val_offset:428*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 428*FLEN/8, x8, x1, x3) + +inst_242: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x1; + valaddr_reg:x4; val_offset:430*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 430*FLEN/8, x8, x1, x3) + +inst_243: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x8001; + valaddr_reg:x4; val_offset:432*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 432*FLEN/8, x8, x1, x3) + +inst_244: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x2; + valaddr_reg:x4; val_offset:434*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 434*FLEN/8, x8, x1, x3) + +inst_245: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x83fe; + valaddr_reg:x4; val_offset:436*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 436*FLEN/8, x8, x1, x3) + +inst_246: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x3ff; + valaddr_reg:x4; val_offset:438*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 438*FLEN/8, x8, x1, x3) + +inst_247: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x83ff; + valaddr_reg:x4; val_offset:440*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 440*FLEN/8, x8, x1, x3) + +inst_248: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x400; + valaddr_reg:x4; val_offset:442*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 442*FLEN/8, x8, x1, x3) + +inst_249: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x8400; + valaddr_reg:x4; val_offset:444*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 444*FLEN/8, x8, x1, x3) + +inst_250: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x401; + valaddr_reg:x4; val_offset:446*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 446*FLEN/8, x8, x1, x3) + +inst_251: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x8455; + valaddr_reg:x4; val_offset:448*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 448*FLEN/8, x8, x1, x3) + +inst_252: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x7bff; + valaddr_reg:x4; val_offset:450*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 450*FLEN/8, x8, x1, x3) + +inst_253: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xfbff; + valaddr_reg:x4; val_offset:452*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 452*FLEN/8, x8, x1, x3) + +inst_254: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x7c00; + valaddr_reg:x4; val_offset:454*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 454*FLEN/8, x8, x1, x3) + +inst_255: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xfc00; + valaddr_reg:x4; val_offset:456*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 456*FLEN/8, x8, x1, x3) + +inst_256: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x7e00; + valaddr_reg:x4; val_offset:458*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 458*FLEN/8, x8, x1, x3) + +inst_257: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xfe00; + valaddr_reg:x4; val_offset:460*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 460*FLEN/8, x8, x1, x3) + +inst_258: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x7e01; + valaddr_reg:x4; val_offset:462*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 462*FLEN/8, x8, x1, x3) + +inst_259: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xfe55; + valaddr_reg:x4; val_offset:464*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 464*FLEN/8, x8, x1, x3) + +inst_260: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x7c01; + valaddr_reg:x4; val_offset:466*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 466*FLEN/8, x8, x1, x3) + +inst_261: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xfd55; + valaddr_reg:x4; val_offset:468*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 468*FLEN/8, x8, x1, x3) + +inst_262: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x3c00; + valaddr_reg:x4; val_offset:470*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 470*FLEN/8, x8, x1, x3) + +inst_263: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xbc00; + valaddr_reg:x4; val_offset:472*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 472*FLEN/8, x8, x1, x3) + +inst_264: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x0; + valaddr_reg:x4; val_offset:474*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 474*FLEN/8, x8, x1, x3) + +inst_265: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x8000; + valaddr_reg:x4; val_offset:476*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 476*FLEN/8, x8, x1, x3) + +inst_266: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x1; + valaddr_reg:x4; val_offset:478*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 478*FLEN/8, x8, x1, x3) + +inst_267: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x8001; + valaddr_reg:x4; val_offset:480*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 480*FLEN/8, x8, x1, x3) + +inst_268: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x2; + valaddr_reg:x4; val_offset:482*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 482*FLEN/8, x8, x1, x3) + +inst_269: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x83fe; + valaddr_reg:x4; val_offset:484*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 484*FLEN/8, x8, x1, x3) + +inst_270: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x3ff; + valaddr_reg:x4; val_offset:486*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 486*FLEN/8, x8, x1, x3) + +inst_271: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x83ff; + valaddr_reg:x4; val_offset:488*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 488*FLEN/8, x8, x1, x3) + +inst_272: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x400; + valaddr_reg:x4; val_offset:490*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 490*FLEN/8, x8, x1, x3) + +inst_273: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x8400; + valaddr_reg:x4; val_offset:492*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 492*FLEN/8, x8, x1, x3) + +inst_274: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x401; + valaddr_reg:x4; val_offset:494*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 494*FLEN/8, x8, x1, x3) + +inst_275: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x8455; + valaddr_reg:x4; val_offset:496*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 496*FLEN/8, x8, x1, x3) + +inst_276: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x7bff; + valaddr_reg:x4; val_offset:498*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 498*FLEN/8, x8, x1, x3) + +inst_277: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xfbff; + valaddr_reg:x4; val_offset:500*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 500*FLEN/8, x8, x1, x3) + +inst_278: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x7c00; + valaddr_reg:x4; val_offset:502*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 502*FLEN/8, x8, x1, x3) + +inst_279: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xfc00; + valaddr_reg:x4; val_offset:504*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 504*FLEN/8, x8, x1, x3) + +inst_280: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x7e00; + valaddr_reg:x4; val_offset:506*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 506*FLEN/8, x8, x1, x3) + +inst_281: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xfe00; + valaddr_reg:x4; val_offset:508*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 508*FLEN/8, x8, x1, x3) + +inst_282: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x7e01; + valaddr_reg:x4; val_offset:510*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 510*FLEN/8, x8, x1, x3) + +inst_283: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xfe55; + valaddr_reg:x4; val_offset:512*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 512*FLEN/8, x8, x1, x3) + +inst_284: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x7c01; + valaddr_reg:x4; val_offset:514*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 514*FLEN/8, x8, x1, x3) + +inst_285: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xfd55; + valaddr_reg:x4; val_offset:516*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 516*FLEN/8, x8, x1, x3) +RVTEST_SIGBASE(x1,signature_x1_2) + +inst_286: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x3c00; + valaddr_reg:x4; val_offset:518*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 518*FLEN/8, x8, x1, x3) + +inst_287: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xbc00; + valaddr_reg:x4; val_offset:520*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 520*FLEN/8, x8, x1, x3) + +inst_288: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x0; + valaddr_reg:x4; val_offset:522*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 522*FLEN/8, x8, x1, x3) + +inst_289: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8000; + valaddr_reg:x4; val_offset:524*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 524*FLEN/8, x8, x1, x3) + +inst_290: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x1; + valaddr_reg:x4; val_offset:526*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 526*FLEN/8, x8, x1, x3) + +inst_291: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8001; + valaddr_reg:x4; val_offset:528*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 528*FLEN/8, x8, x1, x3) + +inst_292: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x2; + valaddr_reg:x4; val_offset:530*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 530*FLEN/8, x8, x1, x3) + +inst_293: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x83fe; + valaddr_reg:x4; val_offset:532*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 532*FLEN/8, x8, x1, x3) + +inst_294: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x3ff; + valaddr_reg:x4; val_offset:534*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 534*FLEN/8, x8, x1, x3) + +inst_295: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x83ff; + valaddr_reg:x4; val_offset:536*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 536*FLEN/8, x8, x1, x3) + +inst_296: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x400; + valaddr_reg:x4; val_offset:538*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 538*FLEN/8, x8, x1, x3) + +inst_297: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8400; + valaddr_reg:x4; val_offset:540*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 540*FLEN/8, x8, x1, x3) + +inst_298: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x401; + valaddr_reg:x4; val_offset:542*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 542*FLEN/8, x8, x1, x3) + +inst_299: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8455; + valaddr_reg:x4; val_offset:544*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 544*FLEN/8, x8, x1, x3) + +inst_300: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7bff; + valaddr_reg:x4; val_offset:546*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 546*FLEN/8, x8, x1, x3) + +inst_301: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xfbff; + valaddr_reg:x4; val_offset:548*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 548*FLEN/8, x8, x1, x3) + +inst_302: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7c00; + valaddr_reg:x4; val_offset:550*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 550*FLEN/8, x8, x1, x3) + +inst_303: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xfc00; + valaddr_reg:x4; val_offset:552*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 552*FLEN/8, x8, x1, x3) + +inst_304: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7e00; + valaddr_reg:x4; val_offset:554*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 554*FLEN/8, x8, x1, x3) + +inst_305: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xfe00; + valaddr_reg:x4; val_offset:556*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 556*FLEN/8, x8, x1, x3) + +inst_306: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7e01; + valaddr_reg:x4; val_offset:558*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 558*FLEN/8, x8, x1, x3) + +inst_307: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xfe55; + valaddr_reg:x4; val_offset:560*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 560*FLEN/8, x8, x1, x3) + +inst_308: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7c01; + valaddr_reg:x4; val_offset:562*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 562*FLEN/8, x8, x1, x3) + +inst_309: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xfd55; + valaddr_reg:x4; val_offset:564*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 564*FLEN/8, x8, x1, x3) + +inst_310: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x3c00; + valaddr_reg:x4; val_offset:566*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 566*FLEN/8, x8, x1, x3) + +inst_311: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xbc00; + valaddr_reg:x4; val_offset:568*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 568*FLEN/8, x8, x1, x3) + +inst_312: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x0; + valaddr_reg:x4; val_offset:570*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 570*FLEN/8, x8, x1, x3) + +inst_313: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8000; + valaddr_reg:x4; val_offset:572*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 572*FLEN/8, x8, x1, x3) + +inst_314: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x1; + valaddr_reg:x4; val_offset:574*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 574*FLEN/8, x8, x1, x3) + +inst_315: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8001; + valaddr_reg:x4; val_offset:576*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 576*FLEN/8, x8, x1, x3) + +inst_316: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x2; + valaddr_reg:x4; val_offset:578*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 578*FLEN/8, x8, x1, x3) + +inst_317: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x83fe; + valaddr_reg:x4; val_offset:580*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 580*FLEN/8, x8, x1, x3) + +inst_318: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x3ff; + valaddr_reg:x4; val_offset:582*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 582*FLEN/8, x8, x1, x3) + +inst_319: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x83ff; + valaddr_reg:x4; val_offset:584*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 584*FLEN/8, x8, x1, x3) + +inst_320: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x400; + valaddr_reg:x4; val_offset:586*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 586*FLEN/8, x8, x1, x3) + +inst_321: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8400; + valaddr_reg:x4; val_offset:588*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 588*FLEN/8, x8, x1, x3) + +inst_322: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x401; + valaddr_reg:x4; val_offset:590*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 590*FLEN/8, x8, x1, x3) + +inst_323: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8455; + valaddr_reg:x4; val_offset:592*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 592*FLEN/8, x8, x1, x3) + +inst_324: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7bff; + valaddr_reg:x4; val_offset:594*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 594*FLEN/8, x8, x1, x3) + +inst_325: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfbff; + valaddr_reg:x4; val_offset:596*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 596*FLEN/8, x8, x1, x3) + +inst_326: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7c00; + valaddr_reg:x4; val_offset:598*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 598*FLEN/8, x8, x1, x3) + +inst_327: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfc00; + valaddr_reg:x4; val_offset:600*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 600*FLEN/8, x8, x1, x3) + +inst_328: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7e00; + valaddr_reg:x4; val_offset:602*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 602*FLEN/8, x8, x1, x3) + +inst_329: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfe00; + valaddr_reg:x4; val_offset:604*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 604*FLEN/8, x8, x1, x3) + +inst_330: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7e01; + valaddr_reg:x4; val_offset:606*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 606*FLEN/8, x8, x1, x3) + +inst_331: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfe55; + valaddr_reg:x4; val_offset:608*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 608*FLEN/8, x8, x1, x3) + +inst_332: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7c01; + valaddr_reg:x4; val_offset:610*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 610*FLEN/8, x8, x1, x3) + +inst_333: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfd55; + valaddr_reg:x4; val_offset:612*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 612*FLEN/8, x8, x1, x3) + +inst_334: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x3c00; + valaddr_reg:x4; val_offset:614*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 614*FLEN/8, x8, x1, x3) + +inst_335: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xbc00; + valaddr_reg:x4; val_offset:616*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 616*FLEN/8, x8, x1, x3) + +inst_336: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x0; + valaddr_reg:x4; val_offset:618*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 618*FLEN/8, x8, x1, x3) + +inst_337: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x8000; + valaddr_reg:x4; val_offset:620*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 620*FLEN/8, x8, x1, x3) + +inst_338: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x1; + valaddr_reg:x4; val_offset:622*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 622*FLEN/8, x8, x1, x3) + +inst_339: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x8001; + valaddr_reg:x4; val_offset:624*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 624*FLEN/8, x8, x1, x3) + +inst_340: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x2; + valaddr_reg:x4; val_offset:626*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 626*FLEN/8, x8, x1, x3) + +inst_341: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x83fe; + valaddr_reg:x4; val_offset:628*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 628*FLEN/8, x8, x1, x3) + +inst_342: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x3ff; + valaddr_reg:x4; val_offset:630*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 630*FLEN/8, x8, x1, x3) + +inst_343: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x83ff; + valaddr_reg:x4; val_offset:632*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 632*FLEN/8, x8, x1, x3) + +inst_344: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x400; + valaddr_reg:x4; val_offset:634*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 634*FLEN/8, x8, x1, x3) + +inst_345: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x8400; + valaddr_reg:x4; val_offset:636*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 636*FLEN/8, x8, x1, x3) + +inst_346: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x401; + valaddr_reg:x4; val_offset:638*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 638*FLEN/8, x8, x1, x3) + +inst_347: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x8455; + valaddr_reg:x4; val_offset:640*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 640*FLEN/8, x8, x1, x3) + +inst_348: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x7bff; + valaddr_reg:x4; val_offset:642*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 642*FLEN/8, x8, x1, x3) + +inst_349: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xfbff; + valaddr_reg:x4; val_offset:644*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 644*FLEN/8, x8, x1, x3) + +inst_350: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x7c00; + valaddr_reg:x4; val_offset:646*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 646*FLEN/8, x8, x1, x3) + +inst_351: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xfc00; + valaddr_reg:x4; val_offset:648*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 648*FLEN/8, x8, x1, x3) + +inst_352: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x7e00; + valaddr_reg:x4; val_offset:650*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 650*FLEN/8, x8, x1, x3) + +inst_353: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xfe00; + valaddr_reg:x4; val_offset:652*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 652*FLEN/8, x8, x1, x3) + +inst_354: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x7e01; + valaddr_reg:x4; val_offset:654*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 654*FLEN/8, x8, x1, x3) + +inst_355: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xfe55; + valaddr_reg:x4; val_offset:656*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 656*FLEN/8, x8, x1, x3) + +inst_356: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x7c01; + valaddr_reg:x4; val_offset:658*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 658*FLEN/8, x8, x1, x3) + +inst_357: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xfd55; + valaddr_reg:x4; val_offset:660*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 660*FLEN/8, x8, x1, x3) + +inst_358: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x3c00; + valaddr_reg:x4; val_offset:662*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 662*FLEN/8, x8, x1, x3) + +inst_359: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xbc00; + valaddr_reg:x4; val_offset:664*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 664*FLEN/8, x8, x1, x3) + +inst_360: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x0; + valaddr_reg:x4; val_offset:666*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 666*FLEN/8, x8, x1, x3) + +inst_361: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x8000; + valaddr_reg:x4; val_offset:668*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 668*FLEN/8, x8, x1, x3) + +inst_362: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x1; + valaddr_reg:x4; val_offset:670*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 670*FLEN/8, x8, x1, x3) + +inst_363: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x8001; + valaddr_reg:x4; val_offset:672*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 672*FLEN/8, x8, x1, x3) + +inst_364: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x2; + valaddr_reg:x4; val_offset:674*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 674*FLEN/8, x8, x1, x3) + +inst_365: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x83fe; + valaddr_reg:x4; val_offset:676*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 676*FLEN/8, x8, x1, x3) + +inst_366: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x3ff; + valaddr_reg:x4; val_offset:678*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 678*FLEN/8, x8, x1, x3) + +inst_367: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x83ff; + valaddr_reg:x4; val_offset:680*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 680*FLEN/8, x8, x1, x3) + +inst_368: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x400; + valaddr_reg:x4; val_offset:682*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 682*FLEN/8, x8, x1, x3) + +inst_369: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x8400; + valaddr_reg:x4; val_offset:684*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 684*FLEN/8, x8, x1, x3) + +inst_370: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x401; + valaddr_reg:x4; val_offset:686*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 686*FLEN/8, x8, x1, x3) + +inst_371: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x8455; + valaddr_reg:x4; val_offset:688*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 688*FLEN/8, x8, x1, x3) + +inst_372: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x7bff; + valaddr_reg:x4; val_offset:690*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 690*FLEN/8, x8, x1, x3) + +inst_373: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xfbff; + valaddr_reg:x4; val_offset:692*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 692*FLEN/8, x8, x1, x3) + +inst_374: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x7c00; + valaddr_reg:x4; val_offset:694*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 694*FLEN/8, x8, x1, x3) + +inst_375: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xfc00; + valaddr_reg:x4; val_offset:696*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 696*FLEN/8, x8, x1, x3) + +inst_376: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x7e00; + valaddr_reg:x4; val_offset:698*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 698*FLEN/8, x8, x1, x3) + +inst_377: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xfe00; + valaddr_reg:x4; val_offset:700*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 700*FLEN/8, x8, x1, x3) + +inst_378: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x7e01; + valaddr_reg:x4; val_offset:702*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 702*FLEN/8, x8, x1, x3) + +inst_379: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xfe55; + valaddr_reg:x4; val_offset:704*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 704*FLEN/8, x8, x1, x3) + +inst_380: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x7c01; + valaddr_reg:x4; val_offset:706*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 706*FLEN/8, x8, x1, x3) + +inst_381: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xfd55; + valaddr_reg:x4; val_offset:708*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 708*FLEN/8, x8, x1, x3) + +inst_382: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x3c00; + valaddr_reg:x4; val_offset:710*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 710*FLEN/8, x8, x1, x3) + +inst_383: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xbc00; + valaddr_reg:x4; val_offset:712*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 712*FLEN/8, x8, x1, x3) + +inst_384: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x0; + valaddr_reg:x4; val_offset:714*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 714*FLEN/8, x8, x1, x3) + +inst_385: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x8000; + valaddr_reg:x4; val_offset:716*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 716*FLEN/8, x8, x1, x3) + +inst_386: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x1; + valaddr_reg:x4; val_offset:718*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 718*FLEN/8, x8, x1, x3) + +inst_387: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x8001; + valaddr_reg:x4; val_offset:720*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 720*FLEN/8, x8, x1, x3) + +inst_388: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x2; + valaddr_reg:x4; val_offset:722*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 722*FLEN/8, x8, x1, x3) + +inst_389: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x83fe; + valaddr_reg:x4; val_offset:724*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 724*FLEN/8, x8, x1, x3) + +inst_390: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x3ff; + valaddr_reg:x4; val_offset:726*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 726*FLEN/8, x8, x1, x3) + +inst_391: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x83ff; + valaddr_reg:x4; val_offset:728*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 728*FLEN/8, x8, x1, x3) + +inst_392: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x400; + valaddr_reg:x4; val_offset:730*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 730*FLEN/8, x8, x1, x3) + +inst_393: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x8400; + valaddr_reg:x4; val_offset:732*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 732*FLEN/8, x8, x1, x3) + +inst_394: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x401; + valaddr_reg:x4; val_offset:734*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 734*FLEN/8, x8, x1, x3) + +inst_395: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x8455; + valaddr_reg:x4; val_offset:736*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 736*FLEN/8, x8, x1, x3) + +inst_396: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x7bff; + valaddr_reg:x4; val_offset:738*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 738*FLEN/8, x8, x1, x3) + +inst_397: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xfbff; + valaddr_reg:x4; val_offset:740*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 740*FLEN/8, x8, x1, x3) + +inst_398: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x7c00; + valaddr_reg:x4; val_offset:742*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 742*FLEN/8, x8, x1, x3) + +inst_399: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xfc00; + valaddr_reg:x4; val_offset:744*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 744*FLEN/8, x8, x1, x3) + +inst_400: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x7e00; + valaddr_reg:x4; val_offset:746*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 746*FLEN/8, x8, x1, x3) + +inst_401: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xfe00; + valaddr_reg:x4; val_offset:748*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 748*FLEN/8, x8, x1, x3) + +inst_402: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x7e01; + valaddr_reg:x4; val_offset:750*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 750*FLEN/8, x8, x1, x3) + +inst_403: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xfe55; + valaddr_reg:x4; val_offset:752*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 752*FLEN/8, x8, x1, x3) + +inst_404: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x7c01; + valaddr_reg:x4; val_offset:754*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 754*FLEN/8, x8, x1, x3) + +inst_405: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xfd55; + valaddr_reg:x4; val_offset:756*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 756*FLEN/8, x8, x1, x3) + +inst_406: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x3c00; + valaddr_reg:x4; val_offset:758*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 758*FLEN/8, x8, x1, x3) + +inst_407: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xbc00; + valaddr_reg:x4; val_offset:760*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 760*FLEN/8, x8, x1, x3) + +inst_408: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x0; + valaddr_reg:x4; val_offset:762*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 762*FLEN/8, x8, x1, x3) + +inst_409: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x8000; + valaddr_reg:x4; val_offset:764*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 764*FLEN/8, x8, x1, x3) + +inst_410: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x1; + valaddr_reg:x4; val_offset:766*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 766*FLEN/8, x8, x1, x3) + +inst_411: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x8001; + valaddr_reg:x4; val_offset:768*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 768*FLEN/8, x8, x1, x3) + +inst_412: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x2; + valaddr_reg:x4; val_offset:770*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 770*FLEN/8, x8, x1, x3) + +inst_413: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x83fe; + valaddr_reg:x4; val_offset:772*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 772*FLEN/8, x8, x1, x3) +RVTEST_SIGBASE(x1,signature_x1_3) + +inst_414: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x3ff; + valaddr_reg:x4; val_offset:774*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 774*FLEN/8, x8, x1, x3) + +inst_415: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x83ff; + valaddr_reg:x4; val_offset:776*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 776*FLEN/8, x8, x1, x3) + +inst_416: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x400; + valaddr_reg:x4; val_offset:778*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 778*FLEN/8, x8, x1, x3) + +inst_417: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x8400; + valaddr_reg:x4; val_offset:780*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 780*FLEN/8, x8, x1, x3) + +inst_418: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x401; + valaddr_reg:x4; val_offset:782*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 782*FLEN/8, x8, x1, x3) + +inst_419: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x8455; + valaddr_reg:x4; val_offset:784*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 784*FLEN/8, x8, x1, x3) + +inst_420: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x7bff; + valaddr_reg:x4; val_offset:786*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 786*FLEN/8, x8, x1, x3) + +inst_421: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xfbff; + valaddr_reg:x4; val_offset:788*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 788*FLEN/8, x8, x1, x3) + +inst_422: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x7c00; + valaddr_reg:x4; val_offset:790*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 790*FLEN/8, x8, x1, x3) + +inst_423: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xfc00; + valaddr_reg:x4; val_offset:792*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 792*FLEN/8, x8, x1, x3) + +inst_424: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x7e00; + valaddr_reg:x4; val_offset:794*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 794*FLEN/8, x8, x1, x3) + +inst_425: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xfe00; + valaddr_reg:x4; val_offset:796*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 796*FLEN/8, x8, x1, x3) + +inst_426: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x7e01; + valaddr_reg:x4; val_offset:798*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 798*FLEN/8, x8, x1, x3) + +inst_427: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xfe55; + valaddr_reg:x4; val_offset:800*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 800*FLEN/8, x8, x1, x3) + +inst_428: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x7c01; + valaddr_reg:x4; val_offset:802*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 802*FLEN/8, x8, x1, x3) + +inst_429: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xfd55; + valaddr_reg:x4; val_offset:804*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 804*FLEN/8, x8, x1, x3) + +inst_430: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x3c00; + valaddr_reg:x4; val_offset:806*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 806*FLEN/8, x8, x1, x3) + +inst_431: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xbc00; + valaddr_reg:x4; val_offset:808*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 808*FLEN/8, x8, x1, x3) + +inst_432: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x0; + valaddr_reg:x4; val_offset:810*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 810*FLEN/8, x8, x1, x3) + +inst_433: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x8000; + valaddr_reg:x4; val_offset:812*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 812*FLEN/8, x8, x1, x3) + +inst_434: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x1; + valaddr_reg:x4; val_offset:814*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 814*FLEN/8, x8, x1, x3) + +inst_435: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x8001; + valaddr_reg:x4; val_offset:816*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 816*FLEN/8, x8, x1, x3) + +inst_436: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x2; + valaddr_reg:x4; val_offset:818*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 818*FLEN/8, x8, x1, x3) + +inst_437: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x83fe; + valaddr_reg:x4; val_offset:820*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 820*FLEN/8, x8, x1, x3) + +inst_438: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x3ff; + valaddr_reg:x4; val_offset:822*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 822*FLEN/8, x8, x1, x3) + +inst_439: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x83ff; + valaddr_reg:x4; val_offset:824*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 824*FLEN/8, x8, x1, x3) + +inst_440: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x400; + valaddr_reg:x4; val_offset:826*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 826*FLEN/8, x8, x1, x3) + +inst_441: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x8400; + valaddr_reg:x4; val_offset:828*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 828*FLEN/8, x8, x1, x3) + +inst_442: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x401; + valaddr_reg:x4; val_offset:830*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 830*FLEN/8, x8, x1, x3) + +inst_443: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x8455; + valaddr_reg:x4; val_offset:832*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 832*FLEN/8, x8, x1, x3) + +inst_444: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x7bff; + valaddr_reg:x4; val_offset:834*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 834*FLEN/8, x8, x1, x3) + +inst_445: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xfbff; + valaddr_reg:x4; val_offset:836*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 836*FLEN/8, x8, x1, x3) + +inst_446: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x7c00; + valaddr_reg:x4; val_offset:838*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 838*FLEN/8, x8, x1, x3) + +inst_447: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xfc00; + valaddr_reg:x4; val_offset:840*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 840*FLEN/8, x8, x1, x3) + +inst_448: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x7e00; + valaddr_reg:x4; val_offset:842*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 842*FLEN/8, x8, x1, x3) + +inst_449: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xfe00; + valaddr_reg:x4; val_offset:844*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 844*FLEN/8, x8, x1, x3) + +inst_450: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x7e01; + valaddr_reg:x4; val_offset:846*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 846*FLEN/8, x8, x1, x3) + +inst_451: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xfe55; + valaddr_reg:x4; val_offset:848*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 848*FLEN/8, x8, x1, x3) + +inst_452: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x7c01; + valaddr_reg:x4; val_offset:850*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 850*FLEN/8, x8, x1, x3) + +inst_453: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xfd55; + valaddr_reg:x4; val_offset:852*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 852*FLEN/8, x8, x1, x3) + +inst_454: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x3c00; + valaddr_reg:x4; val_offset:854*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 854*FLEN/8, x8, x1, x3) + +inst_455: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xbc00; + valaddr_reg:x4; val_offset:856*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 856*FLEN/8, x8, x1, x3) + +inst_456: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x0; + valaddr_reg:x4; val_offset:858*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 858*FLEN/8, x8, x1, x3) + +inst_457: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x8000; + valaddr_reg:x4; val_offset:860*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 860*FLEN/8, x8, x1, x3) + +inst_458: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x1; + valaddr_reg:x4; val_offset:862*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 862*FLEN/8, x8, x1, x3) + +inst_459: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x8001; + valaddr_reg:x4; val_offset:864*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 864*FLEN/8, x8, x1, x3) + +inst_460: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x2; + valaddr_reg:x4; val_offset:866*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 866*FLEN/8, x8, x1, x3) + +inst_461: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x83fe; + valaddr_reg:x4; val_offset:868*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 868*FLEN/8, x8, x1, x3) + +inst_462: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x3ff; + valaddr_reg:x4; val_offset:870*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 870*FLEN/8, x8, x1, x3) + +inst_463: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x83ff; + valaddr_reg:x4; val_offset:872*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 872*FLEN/8, x8, x1, x3) + +inst_464: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x400; + valaddr_reg:x4; val_offset:874*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 874*FLEN/8, x8, x1, x3) + +inst_465: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x8400; + valaddr_reg:x4; val_offset:876*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 876*FLEN/8, x8, x1, x3) + +inst_466: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x401; + valaddr_reg:x4; val_offset:878*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 878*FLEN/8, x8, x1, x3) + +inst_467: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x8455; + valaddr_reg:x4; val_offset:880*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 880*FLEN/8, x8, x1, x3) + +inst_468: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x7bff; + valaddr_reg:x4; val_offset:882*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 882*FLEN/8, x8, x1, x3) + +inst_469: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xfbff; + valaddr_reg:x4; val_offset:884*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 884*FLEN/8, x8, x1, x3) + +inst_470: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x7c00; + valaddr_reg:x4; val_offset:886*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 886*FLEN/8, x8, x1, x3) + +inst_471: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xfc00; + valaddr_reg:x4; val_offset:888*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 888*FLEN/8, x8, x1, x3) + +inst_472: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x7e00; + valaddr_reg:x4; val_offset:890*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 890*FLEN/8, x8, x1, x3) + +inst_473: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xfe00; + valaddr_reg:x4; val_offset:892*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 892*FLEN/8, x8, x1, x3) + +inst_474: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x7e01; + valaddr_reg:x4; val_offset:894*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 894*FLEN/8, x8, x1, x3) + +inst_475: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xfe55; + valaddr_reg:x4; val_offset:896*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 896*FLEN/8, x8, x1, x3) + +inst_476: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x7c01; + valaddr_reg:x4; val_offset:898*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 898*FLEN/8, x8, x1, x3) + +inst_477: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xfd55; + valaddr_reg:x4; val_offset:900*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 900*FLEN/8, x8, x1, x3) + +inst_478: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x3c00; + valaddr_reg:x4; val_offset:902*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 902*FLEN/8, x8, x1, x3) + +inst_479: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xbc00; + valaddr_reg:x4; val_offset:904*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 904*FLEN/8, x8, x1, x3) + +inst_480: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x0; + valaddr_reg:x4; val_offset:906*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 906*FLEN/8, x8, x1, x3) + +inst_481: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x8000; + valaddr_reg:x4; val_offset:908*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 908*FLEN/8, x8, x1, x3) + +inst_482: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x1; + valaddr_reg:x4; val_offset:910*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 910*FLEN/8, x8, x1, x3) + +inst_483: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x8001; + valaddr_reg:x4; val_offset:912*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 912*FLEN/8, x8, x1, x3) + +inst_484: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x2; + valaddr_reg:x4; val_offset:914*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 914*FLEN/8, x8, x1, x3) + +inst_485: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x83fe; + valaddr_reg:x4; val_offset:916*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 916*FLEN/8, x8, x1, x3) + +inst_486: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x3ff; + valaddr_reg:x4; val_offset:918*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 918*FLEN/8, x8, x1, x3) + +inst_487: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x83ff; + valaddr_reg:x4; val_offset:920*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 920*FLEN/8, x8, x1, x3) + +inst_488: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x400; + valaddr_reg:x4; val_offset:922*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 922*FLEN/8, x8, x1, x3) + +inst_489: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x8400; + valaddr_reg:x4; val_offset:924*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 924*FLEN/8, x8, x1, x3) + +inst_490: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x401; + valaddr_reg:x4; val_offset:926*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 926*FLEN/8, x8, x1, x3) + +inst_491: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x8455; + valaddr_reg:x4; val_offset:928*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 928*FLEN/8, x8, x1, x3) + +inst_492: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x7bff; + valaddr_reg:x4; val_offset:930*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 930*FLEN/8, x8, x1, x3) + +inst_493: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xfbff; + valaddr_reg:x4; val_offset:932*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 932*FLEN/8, x8, x1, x3) + +inst_494: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x7c00; + valaddr_reg:x4; val_offset:934*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 934*FLEN/8, x8, x1, x3) + +inst_495: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xfc00; + valaddr_reg:x4; val_offset:936*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 936*FLEN/8, x8, x1, x3) + +inst_496: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x7e00; + valaddr_reg:x4; val_offset:938*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 938*FLEN/8, x8, x1, x3) + +inst_497: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xfe00; + valaddr_reg:x4; val_offset:940*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 940*FLEN/8, x8, x1, x3) + +inst_498: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x7e01; + valaddr_reg:x4; val_offset:942*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 942*FLEN/8, x8, x1, x3) + +inst_499: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xfe55; + valaddr_reg:x4; val_offset:944*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 944*FLEN/8, x8, x1, x3) + +inst_500: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x7c01; + valaddr_reg:x4; val_offset:946*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 946*FLEN/8, x8, x1, x3) + +inst_501: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xfd55; + valaddr_reg:x4; val_offset:948*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 948*FLEN/8, x8, x1, x3) + +inst_502: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x3c00; + valaddr_reg:x4; val_offset:950*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 950*FLEN/8, x8, x1, x3) + +inst_503: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xbc00; + valaddr_reg:x4; val_offset:952*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 952*FLEN/8, x8, x1, x3) + +inst_504: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x0; + valaddr_reg:x4; val_offset:954*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 954*FLEN/8, x8, x1, x3) + +inst_505: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x8000; + valaddr_reg:x4; val_offset:956*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 956*FLEN/8, x8, x1, x3) + +inst_506: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x1; + valaddr_reg:x4; val_offset:958*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 958*FLEN/8, x8, x1, x3) + +inst_507: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x8001; + valaddr_reg:x4; val_offset:960*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 960*FLEN/8, x8, x1, x3) + +inst_508: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x2; + valaddr_reg:x4; val_offset:962*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 962*FLEN/8, x8, x1, x3) + +inst_509: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x83fe; + valaddr_reg:x4; val_offset:964*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 964*FLEN/8, x8, x1, x3) + +inst_510: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x3ff; + valaddr_reg:x4; val_offset:966*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 966*FLEN/8, x8, x1, x3) + +inst_511: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x83ff; + valaddr_reg:x4; val_offset:968*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 968*FLEN/8, x8, x1, x3) + +inst_512: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x400; + valaddr_reg:x4; val_offset:970*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 970*FLEN/8, x8, x1, x3) + +inst_513: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x8400; + valaddr_reg:x4; val_offset:972*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 972*FLEN/8, x8, x1, x3) + +inst_514: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x401; + valaddr_reg:x4; val_offset:974*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 974*FLEN/8, x8, x1, x3) + +inst_515: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x8455; + valaddr_reg:x4; val_offset:976*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 976*FLEN/8, x8, x1, x3) + +inst_516: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x7bff; + valaddr_reg:x4; val_offset:978*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 978*FLEN/8, x8, x1, x3) + +inst_517: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xfbff; + valaddr_reg:x4; val_offset:980*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 980*FLEN/8, x8, x1, x3) + +inst_518: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x7c00; + valaddr_reg:x4; val_offset:982*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 982*FLEN/8, x8, x1, x3) + +inst_519: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xfc00; + valaddr_reg:x4; val_offset:984*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 984*FLEN/8, x8, x1, x3) + +inst_520: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x7e00; + valaddr_reg:x4; val_offset:986*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 986*FLEN/8, x8, x1, x3) + +inst_521: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xfe00; + valaddr_reg:x4; val_offset:988*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 988*FLEN/8, x8, x1, x3) + +inst_522: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x7e01; + valaddr_reg:x4; val_offset:990*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 990*FLEN/8, x8, x1, x3) + +inst_523: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xfe55; + valaddr_reg:x4; val_offset:992*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 992*FLEN/8, x8, x1, x3) + +inst_524: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x7c01; + valaddr_reg:x4; val_offset:994*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 994*FLEN/8, x8, x1, x3) + +inst_525: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xfd55; + valaddr_reg:x4; val_offset:996*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 996*FLEN/8, x8, x1, x3) + +inst_526: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x3c00; + valaddr_reg:x4; val_offset:998*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 998*FLEN/8, x8, x1, x3) + +inst_527: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xbc00; + valaddr_reg:x4; val_offset:1000*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1000*FLEN/8, x8, x1, x3) + +inst_528: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x0; + valaddr_reg:x4; val_offset:1002*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1002*FLEN/8, x8, x1, x3) + +inst_529: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x8000; + valaddr_reg:x4; val_offset:1004*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1004*FLEN/8, x8, x1, x3) + +inst_530: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x1; + valaddr_reg:x4; val_offset:1006*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1006*FLEN/8, x8, x1, x3) + +inst_531: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x8001; + valaddr_reg:x4; val_offset:1008*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1008*FLEN/8, x8, x1, x3) + +inst_532: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2; + valaddr_reg:x4; val_offset:1010*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1010*FLEN/8, x8, x1, x3) + +inst_533: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x83fe; + valaddr_reg:x4; val_offset:1012*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1012*FLEN/8, x8, x1, x3) + +inst_534: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3ff; + valaddr_reg:x4; val_offset:1014*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1014*FLEN/8, x8, x1, x3) + +inst_535: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x83ff; + valaddr_reg:x4; val_offset:1016*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1016*FLEN/8, x8, x1, x3) + +inst_536: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x400; + valaddr_reg:x4; val_offset:1018*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1018*FLEN/8, x8, x1, x3) + +inst_537: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x8400; + valaddr_reg:x4; val_offset:1020*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1020*FLEN/8, x8, x1, x3) + +inst_538: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x401; + valaddr_reg:x4; val_offset:1022*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1022*FLEN/8, x8, x1, x3) + +inst_539: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x8455; + valaddr_reg:x4; val_offset:1024*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1024*FLEN/8, x8, x1, x3) + +inst_540: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7bff; + valaddr_reg:x4; val_offset:1026*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1026*FLEN/8, x8, x1, x3) + +inst_541: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xfbff; + valaddr_reg:x4; val_offset:1028*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1028*FLEN/8, x8, x1, x3) +RVTEST_SIGBASE(x1,signature_x1_4) + +inst_542: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7c00; + valaddr_reg:x4; val_offset:1030*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1030*FLEN/8, x8, x1, x3) + +inst_543: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xfc00; + valaddr_reg:x4; val_offset:1032*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1032*FLEN/8, x8, x1, x3) + +inst_544: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7e00; + valaddr_reg:x4; val_offset:1034*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1034*FLEN/8, x8, x1, x3) + +inst_545: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xfe00; + valaddr_reg:x4; val_offset:1036*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1036*FLEN/8, x8, x1, x3) + +inst_546: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7e01; + valaddr_reg:x4; val_offset:1038*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1038*FLEN/8, x8, x1, x3) + +inst_547: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xfe55; + valaddr_reg:x4; val_offset:1040*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1040*FLEN/8, x8, x1, x3) + +inst_548: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7c01; + valaddr_reg:x4; val_offset:1042*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1042*FLEN/8, x8, x1, x3) + +inst_549: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xfd55; + valaddr_reg:x4; val_offset:1044*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1044*FLEN/8, x8, x1, x3) + +inst_550: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3c00; + valaddr_reg:x4; val_offset:1046*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1046*FLEN/8, x8, x1, x3) + +inst_551: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xbc00; + valaddr_reg:x4; val_offset:1048*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1048*FLEN/8, x8, x1, x3) + +inst_552: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x0; + valaddr_reg:x4; val_offset:1050*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1050*FLEN/8, x8, x1, x3) + +inst_553: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x8000; + valaddr_reg:x4; val_offset:1052*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1052*FLEN/8, x8, x1, x3) + +inst_554: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x1; + valaddr_reg:x4; val_offset:1054*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1054*FLEN/8, x8, x1, x3) + +inst_555: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x8001; + valaddr_reg:x4; val_offset:1056*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1056*FLEN/8, x8, x1, x3) + +inst_556: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x2; + valaddr_reg:x4; val_offset:1058*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1058*FLEN/8, x8, x1, x3) + +inst_557: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x83fe; + valaddr_reg:x4; val_offset:1060*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1060*FLEN/8, x8, x1, x3) + +inst_558: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x3ff; + valaddr_reg:x4; val_offset:1062*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1062*FLEN/8, x8, x1, x3) + +inst_559: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x83ff; + valaddr_reg:x4; val_offset:1064*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1064*FLEN/8, x8, x1, x3) + +inst_560: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x400; + valaddr_reg:x4; val_offset:1066*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1066*FLEN/8, x8, x1, x3) + +inst_561: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x8400; + valaddr_reg:x4; val_offset:1068*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1068*FLEN/8, x8, x1, x3) + +inst_562: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x401; + valaddr_reg:x4; val_offset:1070*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1070*FLEN/8, x8, x1, x3) + +inst_563: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x8455; + valaddr_reg:x4; val_offset:1072*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1072*FLEN/8, x8, x1, x3) + +inst_564: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x7bff; + valaddr_reg:x4; val_offset:1074*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1074*FLEN/8, x8, x1, x3) + +inst_565: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xfbff; + valaddr_reg:x4; val_offset:1076*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1076*FLEN/8, x8, x1, x3) + +inst_566: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x7c00; + valaddr_reg:x4; val_offset:1078*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1078*FLEN/8, x8, x1, x3) + +inst_567: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xfc00; + valaddr_reg:x4; val_offset:1080*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1080*FLEN/8, x8, x1, x3) + +inst_568: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x7e00; + valaddr_reg:x4; val_offset:1082*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1082*FLEN/8, x8, x1, x3) + +inst_569: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xfe00; + valaddr_reg:x4; val_offset:1084*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1084*FLEN/8, x8, x1, x3) + +inst_570: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x7e01; + valaddr_reg:x4; val_offset:1086*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1086*FLEN/8, x8, x1, x3) + +inst_571: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xfe55; + valaddr_reg:x4; val_offset:1088*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1088*FLEN/8, x8, x1, x3) + +inst_572: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x7c01; + valaddr_reg:x4; val_offset:1090*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1090*FLEN/8, x8, x1, x3) + +inst_573: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xfd55; + valaddr_reg:x4; val_offset:1092*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1092*FLEN/8, x8, x1, x3) + +inst_574: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x3c00; + valaddr_reg:x4; val_offset:1094*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1094*FLEN/8, x8, x1, x3) + +inst_575: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbc00; + valaddr_reg:x4; val_offset:1096*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1096*FLEN/8, x8, x1, x3) + +inst_576: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x8000; + valaddr_reg:x4; val_offset:1098*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1098*FLEN/8, x8, x1, x3) + +inst_577: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x8001; + valaddr_reg:x4; val_offset:1100*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1100*FLEN/8, x8, x1, x3) + +inst_578: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x3ff; + valaddr_reg:x4; val_offset:1102*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1102*FLEN/8, x8, x1, x3) + +inst_579: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x7bff; + valaddr_reg:x4; val_offset:1104*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1104*FLEN/8, x8, x1, x3) + +inst_580: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x1; + valaddr_reg:x4; val_offset:1106*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1106*FLEN/8, x8, x1, x3) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(1,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(2,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(1024,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(1025,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64511,16,FLEN) +test_dataset_1: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31744,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32256,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32257,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31745,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(15360,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1,32,FLEN) +test_dataset_2: +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(2,16,FLEN) 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78*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fmul_b2-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fmul_b2-01.S new file mode 100644 index 000000000..6fe588bdc --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fmul_b2-01.S @@ -0,0 +1,1326 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 04:50:26 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fmul.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fmul.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fmul_b2 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fmul_b2) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x9,test_dataset_0) +RVTEST_SIGBASE(x4,signature_x4_1) + +inst_0: +// rs1 == rd != rs2, rs1==x10, rs2==x12, rd==x10,fs1 == 0 and fe1 == 0x00 and fm1 == 0x008 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x006 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x10; op2:x12; dest:x10; op1val:0x8; op2val:0x3006; + valaddr_reg:x9; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fmul.h, x10, x10, x12, dyn, 0, 0, x9, 0*FLEN/8, x11, x4, x5) + +inst_1: +// rs1 == rs2 == rd, rs1==x0, rs2==x0, rd==x0,fs1 == 0 and fe1 == 0x00 and fm1 == 0x00b and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1d1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x0; op2:x0; dest:x0; op1val:0x0; op2val:0x0; + valaddr_reg:x9; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fmul.h, x0, x0, x0, dyn, 0, 0, x9, 2*FLEN/8, x11, x4, x5) + +inst_2: +// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==x29, rs2==x30, rd==x19,fs1 == 0 and fe1 == 0x00 and fm1 == 0x016 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1d1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x29; op2:x30; dest:x19; op1val:0x16; op2val:0x31d1; + valaddr_reg:x9; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fmul.h, x19, x29, x30, dyn, 0, 0, x9, 4*FLEN/8, x11, x4, x5) + +inst_3: +// rs1 == rs2 != rd, rs1==x24, rs2==x24, rd==x14,fs1 == 0 and fe1 == 0x00 and fm1 == 0x056 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x1f4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x24; op2:x24; dest:x14; op1val:0x56; op2val:0x56; + valaddr_reg:x9; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fmul.h, x14, x24, x24, dyn, 0, 0, x9, 6*FLEN/8, x11, x4, x5) + +inst_4: +// rs2 == rd != rs1, rs1==x26, rs2==x15, rd==x15,fs1 == 0 and fe1 == 0x00 and fm1 == 0x021 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3c1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x26; op2:x15; dest:x15; op1val:0x21; op2val:0x37c1; + valaddr_reg:x9; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fmul.h, x15, x26, x15, dyn, 0, 0, x9, 8*FLEN/8, x11, x4, x5) + +inst_5: +// rs1==x2, rs2==x13, rd==x27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x01c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x092 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x2; op2:x13; dest:x27; op1val:0x1c; op2val:0x3c92; + valaddr_reg:x9; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fmul.h, x27, x2, x13, dyn, 0, 0, x9, 10*FLEN/8, x11, x4, x5) + +inst_6: +// rs1==x28, rs2==x21, rd==x25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x005 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x266 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x28; op2:x21; dest:x25; op1val:0x5; op2val:0x4a66; + valaddr_reg:x9; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fmul.h, x25, x28, x21, dyn, 0, 0, x9, 12*FLEN/8, x11, x4, x5) + +inst_7: +// rs1==x12, rs2==x22, rd==x29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x058 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1d1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x12; op2:x22; dest:x29; op1val:0x58; op2val:0x3dd1; + valaddr_reg:x9; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fmul.h, x29, x12, x22, dyn, 0, 0, x9, 14*FLEN/8, x11, x4, x5) + +inst_8: +// rs1==x21, rs2==x20, rd==x1,fs1 == 0 and fe1 == 0x00 and fm1 == 0x038 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x092 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x21; op2:x20; dest:x1; op1val:0x38; op2val:0x4492; + valaddr_reg:x9; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fmul.h, x1, x21, x20, dyn, 0, 0, x9, 16*FLEN/8, x11, x4, x5) + +inst_9: +// rs1==x7, rs2==x17, rd==x12,fs1 == 0 and fe1 == 0x00 and fm1 == 0x033 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x105 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x7; op2:x17; dest:x12; op1val:0x33; op2val:0x4905; + valaddr_reg:x9; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fmul.h, x12, x7, x17, dyn, 0, 0, x9, 18*FLEN/8, x11, x4, x5) + +inst_10: +// rs1==x15, rs2==x8, rd==x26,fs1 == 0 and fe1 == 0x00 and fm1 == 0x042 and fs2 == 1 and fe2 == 0x08 and fm2 == 0x3cf and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x15; op2:x8; dest:x26; op1val:0x42; op2val:0xa3cf; + valaddr_reg:x9; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fmul.h, x26, x15, x8, dyn, 0, 0, x9, 20*FLEN/8, x11, x4, x5) + +inst_11: +// rs1==x30, rs2==x19, rd==x28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x046 and fs2 == 1 and fe2 == 0x09 and fm2 == 0x350 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x19; dest:x28; op1val:0x46; op2val:0xa750; + valaddr_reg:x9; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fmul.h, x28, x30, x19, dyn, 0, 0, x9, 22*FLEN/8, x11, x4, x5) + +inst_12: +// rs1==x16, rs2==x3, rd==x6,fs1 == 0 and fe1 == 0x00 and fm1 == 0x041 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x16; op2:x3; dest:x6; op1val:0x41; op2val:0xabe0; + valaddr_reg:x9; val_offset:24*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fmul.h, x6, x16, x3, dyn, 0, 0, x9, 24*FLEN/8, x11, x4, x5) +RVTEST_VALBASEUPD(x17,test_dataset_1) + +inst_13: +// rs1==x18, rs2==x31, rd==x9,fs1 == 0 and fe1 == 0x00 and fm1 == 0x005 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x266 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x18; op2:x31; dest:x9; op1val:0x5; op2val:0xbe66; + valaddr_reg:x17; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fmul.h, x9, x18, x31, dyn, 0, 0, x17, 0*FLEN/8, x19, x4, x5) +RVTEST_SIGBASE(x12,signature_x12_0) + +inst_14: +// rs1==x6, rs2==x25, rd==x7,fs1 == 0 and fe1 == 0x00 and fm1 == 0x02f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x172 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x6; op2:x25; dest:x7; op1val:0x2f; op2val:0xb572; + valaddr_reg:x17; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x15 +*/ +TEST_FPRR_OP(fmul.h, x7, x6, x25, dyn, 0, 0, x17, 2*FLEN/8, x19, x12, x15) + +inst_15: +// rs1==x5, rs2==x28, rd==x22,fs1 == 0 and fe1 == 0x00 and fm1 == 0x029 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x23e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x5; op2:x28; dest:x22; op1val:0x29; op2val:0xba3e; + valaddr_reg:x17; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x15 +*/ +TEST_FPRR_OP(fmul.h, x22, x5, x28, dyn, 0, 0, x17, 4*FLEN/8, x19, x12, x15) + +inst_16: +// rs1==x22, rs2==x1, rd==x8,fs1 == 0 and fe1 == 0x00 and fm1 == 0x037 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0a7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x22; op2:x1; dest:x8; op1val:0x37; op2val:0xbca7; + valaddr_reg:x17; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x15 +*/ +TEST_FPRR_OP(fmul.h, x8, x22, x1, dyn, 0, 0, x17, 6*FLEN/8, x19, x12, x15) + +inst_17: +// rs1==x27, rs2==x16, rd==x5,fs1 == 0 and fe1 == 0x00 and fm1 == 0x016 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1d1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x27; op2:x16; dest:x5; op1val:0x16; op2val:0xc5d1; + valaddr_reg:x17; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x15 +*/ +TEST_FPRR_OP(fmul.h, x5, x27, x16, dyn, 0, 0, x17, 8*FLEN/8, x19, x12, x15) + +inst_18: +// rs1==x20, rs2==x14, rd==x31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x017 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x190 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x20; op2:x14; dest:x31; op1val:0x17; op2val:0xc990; + valaddr_reg:x17; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x15 +*/ +TEST_FPRR_OP(fmul.h, x31, x20, x14, dyn, 0, 0, x17, 10*FLEN/8, x19, x12, x15) + +inst_19: +// rs1==x4, rs2==x29, rd==x18,fs1 == 0 and fe1 == 0x00 and fm1 == 0x01e and fs2 == 1 and fe2 == 0x13 and fm2 == 0x044 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x4; op2:x29; dest:x18; op1val:0x1e; op2val:0xcc44; + valaddr_reg:x17; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x15 +*/ +TEST_FPRR_OP(fmul.h, x18, x4, x29, dyn, 0, 0, x17, 12*FLEN/8, x19, x12, x15) + +inst_20: +// rs1==x3, rs2==x2, rd==x24,fs1 == 0 and fe1 == 0x0f and fm1 == 0x017 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3d4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x3; op2:x2; dest:x24; op1val:0x3c17; op2val:0x3bd4; + valaddr_reg:x17; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x15 +*/ +TEST_FPRR_OP(fmul.h, x24, x3, x2, dyn, 0, 0, x17, 14*FLEN/8, x19, x12, x15) + +inst_21: +// rs1==x23, rs2==x10, rd==x4,fs1 == 0 and fe1 == 0x0f and fm1 == 0x017 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3d6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x23; op2:x10; dest:x4; op1val:0x3c17; op2val:0x3bd6; + valaddr_reg:x17; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x15 +*/ +TEST_FPRR_OP(fmul.h, x4, x23, x10, dyn, 0, 0, x17, 16*FLEN/8, x19, x12, x15) + +inst_22: +// rs1==x13, rs2==x9, rd==x11,fs1 == 0 and fe1 == 0x0f and fm1 == 0x042 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x38b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x13; op2:x9; dest:x11; op1val:0x3c42; op2val:0x3b8b; + valaddr_reg:x17; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x15 +*/ +TEST_FPRR_OP(fmul.h, x11, x13, x9, dyn, 0, 0, x17, 18*FLEN/8, x19, x12, x15) +RVTEST_VALBASEUPD(x10,test_dataset_2) + +inst_23: +// rs1==x8, rs2==x23, rd==x30,fs1 == 0 and fe1 == 0x0f and fm1 == 0x02f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3b5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x8; op2:x23; dest:x30; op1val:0x3c2f; op2val:0x3bb5; + valaddr_reg:x10; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x15 +*/ +TEST_FPRR_OP(fmul.h, x30, x8, x23, dyn, 0, 0, x10, 0*FLEN/8, x22, x12, x15) + +inst_24: +// rs1==x11, rs2==x26, rd==x3,fs1 == 0 and fe1 == 0x0f and fm1 == 0x057 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x37d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x11; op2:x26; dest:x3; op1val:0x3c57; op2val:0x3b7d; + valaddr_reg:x10; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x3, x11, x26, dyn, 0, 0, x10, 2*FLEN/8, x22, x12, x8) +RVTEST_SIGBASE(x3,signature_x3_0) + +inst_25: +// rs1==x1, rs2==x11, rd==x17,fs1 == 0 and fe1 == 0x0f and fm1 == 0x018 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x1; op2:x11; dest:x17; op1val:0x3c18; op2val:0x3c07; + valaddr_reg:x10; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x17, x1, x11, dyn, 0, 0, x10, 4*FLEN/8, x22, x3, x8) + +inst_26: +// rs1==x14, rs2==x4, rd==x21,fs1 == 0 and fe1 == 0x0f and fm1 == 0x036 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x009 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x14; op2:x4; dest:x21; op1val:0x3c36; op2val:0x3c09; + valaddr_reg:x10; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x21, x14, x4, dyn, 0, 0, x10, 6*FLEN/8, x22, x3, x8) + +inst_27: +// rs1==x17, rs2==x18, rd==x2,fs1 == 0 and fe1 == 0x0f and fm1 == 0x044 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x038 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x17; op2:x18; dest:x2; op1val:0x3c44; op2val:0x3c38; + valaddr_reg:x10; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x2, x17, x18, dyn, 0, 0, x10, 8*FLEN/8, x22, x3, x8) + +inst_28: +// rs1==x31, rs2==x5, rd==x16,fs1 == 0 and fe1 == 0x0f and fm1 == 0x02f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0c7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x31; op2:x5; dest:x16; op1val:0x3c2f; op2val:0x3cc7; + valaddr_reg:x10; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x16, x31, x5, dyn, 0, 0, x10, 10*FLEN/8, x22, x3, x8) + +inst_29: +// rs1==x19, rs2==x27, rd==x23,fs1 == 0 and fe1 == 0x0f and fm1 == 0x02e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1bd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x19; op2:x27; dest:x23; op1val:0x3c2e; op2val:0x3dbd; + valaddr_reg:x10; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x23, x19, x27, dyn, 0, 0, x10, 12*FLEN/8, x22, x3, x8) + +inst_30: +// rs1==x9, rs2==x6, rd==x13,fs1 == 0 and fe1 == 0x0f and fm1 == 0x03a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x394 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x9; op2:x6; dest:x13; op1val:0x3c3a; op2val:0xbb94; + valaddr_reg:x10; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x13, x9, x6, dyn, 0, 0, x10, 14*FLEN/8, x22, x3, x8) + +inst_31: +// rs1==x25, rs2==x7, rd==x20,fs1 == 0 and fe1 == 0x0f and fm1 == 0x061 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x352 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x25; op2:x7; dest:x20; op1val:0x3c61; op2val:0xbb52; + valaddr_reg:x10; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x20, x25, x7, dyn, 0, 0, x10, 16*FLEN/8, x22, x3, x8) +RVTEST_VALBASEUPD(x1,test_dataset_3) + +inst_32: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x05c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x35e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c5c; op2val:0xbb5e; + valaddr_reg:x1; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 0*FLEN/8, x2, x3, x8) + +inst_33: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x03c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x39d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c3c; op2val:0xbb9d; + valaddr_reg:x1; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2*FLEN/8, x2, x3, x8) + +inst_34: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x044 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x39e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c44; op2val:0xbb9e; + valaddr_reg:x1; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 4*FLEN/8, x2, x3, x8) + +inst_35: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x03f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3c5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c3f; op2val:0xbbc5; + valaddr_reg:x1; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 6*FLEN/8, x2, x3, x8) + +inst_36: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x040 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c40; op2val:0xbc00; + valaddr_reg:x1; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 8*FLEN/8, x2, x3, x8) + +inst_37: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x042 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x03a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c42; op2val:0xbc3a; + valaddr_reg:x1; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 10*FLEN/8, x2, x3, x8) + +inst_38: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x055 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x09d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c55; op2val:0xbc9d; + valaddr_reg:x1; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 12*FLEN/8, x2, x3, x8) + +inst_39: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x03c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c3c; op2val:0xbdaa; + valaddr_reg:x1; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 14*FLEN/8, x2, x3, x8) + +inst_40: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x049 and fs2 == 0 and fe2 == 0x08 and fm2 == 0x30f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x49; op2val:0x230f; + valaddr_reg:x1; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 16*FLEN/8, x2, x3, x8) + +inst_41: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x048 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x48; op2val:0x2955; + valaddr_reg:x1; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 18*FLEN/8, x2, x3, x8) + +inst_42: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03b and fs2 == 0 and fe2 == 0x0b and fm2 == 0x16c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b; op2val:0x2d6c; + valaddr_reg:x1; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 20*FLEN/8, x2, x3, x8) + +inst_43: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2c6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x55; op2val:0x2ec6; + valaddr_reg:x1; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 22*FLEN/8, x2, x3, x8) + +inst_44: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x02a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x279 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2a; op2val:0x3679; + valaddr_reg:x1; val_offset:24*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 24*FLEN/8, x2, x3, x8) + +inst_45: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x016 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x16; op2val:0x3e00; + valaddr_reg:x1; val_offset:26*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 26*FLEN/8, x2, x3, x8) + +inst_46: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x023 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x36d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x23; op2val:0x3f6d; + valaddr_reg:x1; val_offset:28*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 28*FLEN/8, x2, x3, x8) + +inst_47: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03e and fs2 == 0 and fe2 == 0x10 and fm2 == 0x029 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3e; op2val:0x4029; + valaddr_reg:x1; val_offset:30*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 30*FLEN/8, x2, x3, x8) + +inst_48: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x027 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x296 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x27; op2val:0x4696; + valaddr_reg:x1; val_offset:32*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 32*FLEN/8, x2, x3, x8) + +inst_49: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x041 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3e4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x41; op2val:0x47e4; + valaddr_reg:x1; val_offset:34*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 34*FLEN/8, x2, x3, x8) + +inst_50: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x043 and fs2 == 1 and fe2 == 0x08 and fm2 == 0x3b1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x43; op2val:0xa3b1; + valaddr_reg:x1; val_offset:36*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 36*FLEN/8, x2, x3, x8) + +inst_51: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x054 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x092 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x54; op2val:0xa892; + valaddr_reg:x1; val_offset:38*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 38*FLEN/8, x2, x3, x8) + +inst_52: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x04c and fs2 == 1 and fe2 == 0x0b and fm2 == 0x035 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x4c; op2val:0xac35; + valaddr_reg:x1; val_offset:40*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 40*FLEN/8, x2, x3, x8) + +inst_53: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x028 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x333 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x28; op2val:0xb333; + valaddr_reg:x1; val_offset:42*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 42*FLEN/8, x2, x3, x8) + +inst_54: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x01b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x109 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x1b; op2val:0xb909; + valaddr_reg:x1; val_offset:44*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 44*FLEN/8, x2, x3, x8) + +inst_55: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x042 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x42; op2val:0xb800; + valaddr_reg:x1; val_offset:46*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 46*FLEN/8, x2, x3, x8) + +inst_56: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x058 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1e8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x58; op2val:0xb9e8; + valaddr_reg:x1; val_offset:48*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 48*FLEN/8, x2, x3, x8) + +inst_57: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00a and fs2 == 1 and fe2 == 0x12 and fm2 == 0x273 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xa; op2val:0xca73; + valaddr_reg:x1; val_offset:50*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 50*FLEN/8, x2, x3, x8) + +inst_58: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x05d and fs2 == 1 and fe2 == 0x10 and fm2 == 0x186 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x5d; op2val:0xc186; + valaddr_reg:x1; val_offset:52*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 52*FLEN/8, x2, x3, x8) + +inst_59: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x019 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x121 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x19; op2val:0xcd21; + valaddr_reg:x1; val_offset:54*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 54*FLEN/8, x2, x3, x8) + +inst_60: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 0 and fe2 == 0x15 and fm2 == 0x090 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xe; op2val:0x5490; + valaddr_reg:x1; val_offset:56*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 56*FLEN/8, x2, x3, x8) + +inst_61: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x04a and fs2 == 0 and fe2 == 0x12 and fm2 == 0x2e6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x4a; op2val:0x4ae6; + valaddr_reg:x1; val_offset:58*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 58*FLEN/8, x2, x3, x8) + +inst_62: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x16 and fm2 == 0x08c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7; op2val:0x588c; + valaddr_reg:x1; val_offset:60*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 60*FLEN/8, x2, x3, x8) + +inst_63: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x04c and fs2 == 0 and fe2 == 0x12 and fm2 == 0x2ad and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x4c; op2val:0x4aad; + valaddr_reg:x1; val_offset:62*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 62*FLEN/8, x2, x3, x8) + +inst_64: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x058 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x1b8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x58; op2val:0x49b8; + valaddr_reg:x1; val_offset:64*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 64*FLEN/8, x2, x3, x8) + +inst_65: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x061 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x11b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x61; op2val:0x491b; + valaddr_reg:x1; val_offset:66*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 66*FLEN/8, x2, x3, x8) + +inst_66: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x012 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x2a8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x12; op2val:0x52a8; + valaddr_reg:x1; val_offset:68*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 68*FLEN/8, x2, x3, x8) + +inst_67: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x020 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x2fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x20; op2val:0x4efe; + valaddr_reg:x1; val_offset:70*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 70*FLEN/8, x2, x3, x8) + +inst_68: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x008 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x1fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8; op2val:0x55fe; + valaddr_reg:x1; val_offset:72*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 72*FLEN/8, x2, x3, x8) + +inst_69: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x05c and fs2 == 0 and fe2 == 0x11 and fm2 == 0x18d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x5c; op2val:0x458d; + valaddr_reg:x1; val_offset:74*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 74*FLEN/8, x2, x3, x8) + +inst_70: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x005 and fs2 == 1 and fe2 == 0x16 and fm2 == 0x263 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x5; op2val:0xda63; + valaddr_reg:x1; val_offset:76*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 76*FLEN/8, x2, x3, x8) + +inst_71: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x02f and fs2 == 1 and fe2 == 0x13 and fm2 == 0x16e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2f; op2val:0xcd6e; + valaddr_reg:x1; val_offset:78*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 78*FLEN/8, x2, x3, x8) + +inst_72: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x017 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x189 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x17; op2val:0xd189; + valaddr_reg:x1; val_offset:80*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 80*FLEN/8, x2, x3, x8) + +inst_73: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x057 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x1d5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x57; op2val:0xc9d5; + valaddr_reg:x1; val_offset:82*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 82*FLEN/8, x2, x3, x8) + +inst_74: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00b and fs2 == 1 and fe2 == 0x15 and fm2 == 0x1b8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xb; op2val:0xd5b8; + valaddr_reg:x1; val_offset:84*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 84*FLEN/8, x2, x3, x8) + +inst_75: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x009 and fs2 == 1 and fe2 == 0x15 and fm2 == 0x2e1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x9; op2val:0xd6e1; + valaddr_reg:x1; val_offset:86*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 86*FLEN/8, x2, x3, x8) + +inst_76: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x006 and fs2 == 1 and fe2 == 0x16 and fm2 == 0x0fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6; op2val:0xd8fe; + valaddr_reg:x1; val_offset:88*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 88*FLEN/8, x2, x3, x8) + +inst_77: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x17 and fm2 == 0x0a9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3; op2val:0xdca9; + valaddr_reg:x1; val_offset:90*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 90*FLEN/8, x2, x3, x8) + +inst_78: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x021 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x1cf and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x21; op2val:0xcdcf; + valaddr_reg:x1; val_offset:92*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 92*FLEN/8, x2, x3, x8) + +inst_79: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x015 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x215 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x15; op2val:0xce15; + valaddr_reg:x1; val_offset:94*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 94*FLEN/8, x2, x3, x8) + +inst_80: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x018 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3d3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x418; op2val:0x3bd3; + valaddr_reg:x1; val_offset:96*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 96*FLEN/8, x2, x3, x8) + +inst_81: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x059 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x35f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x459; op2val:0x3b5f; + valaddr_reg:x1; val_offset:98*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 98*FLEN/8, x2, x3, x8) + +inst_82: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x032 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3a8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x432; op2val:0x3ba8; + valaddr_reg:x1; val_offset:100*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 100*FLEN/8, x2, x3, x8) + +inst_83: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x006 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x406; op2val:0x3c01; + valaddr_reg:x1; val_offset:102*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 102*FLEN/8, x2, x3, x8) + +inst_84: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x014 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x414; op2val:0x3bf8; + valaddr_reg:x1; val_offset:104*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 104*FLEN/8, x2, x3, x8) + +inst_85: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x01e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x3c1e; + valaddr_reg:x1; val_offset:106*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 106*FLEN/8, x2, x3, x8) + +inst_86: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x04f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3e4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x44f; op2val:0x3be4; + valaddr_reg:x1; val_offset:108*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 108*FLEN/8, x2, x3, x8) + +inst_87: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x060 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x01d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x460; op2val:0x3c1d; + valaddr_reg:x1; val_offset:110*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 110*FLEN/8, x2, x3, x8) + +inst_88: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x00f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ed and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x40f; op2val:0x3ced; + valaddr_reg:x1; val_offset:112*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 112*FLEN/8, x2, x3, x8) + +inst_89: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x02c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x42c; op2val:0x3dc0; + valaddr_reg:x1; val_offset:114*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 114*FLEN/8, x2, x3, x8) + +inst_90: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x004 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3fa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x404; op2val:0xbbfa; + valaddr_reg:x1; val_offset:116*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 116*FLEN/8, x2, x3, x8) + +inst_91: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x03a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x396 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x43a; op2val:0xbb96; + valaddr_reg:x1; val_offset:118*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 118*FLEN/8, x2, x3, x8) + +inst_92: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x063 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x352 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x463; op2val:0xbb52; + valaddr_reg:x1; val_offset:120*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 120*FLEN/8, x2, x3, x8) + +inst_93: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x05f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x360 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x45f; op2val:0xbb60; + valaddr_reg:x1; val_offset:122*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 122*FLEN/8, x2, x3, x8) + +inst_94: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x022 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3dd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x422; op2val:0xbbdd; + valaddr_reg:x1; val_offset:124*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 124*FLEN/8, x2, x3, x8) + +inst_95: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x034 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3d9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x434; op2val:0xbbd9; + valaddr_reg:x1; val_offset:126*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 126*FLEN/8, x2, x3, x8) + +inst_96: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x05b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3ce and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x45b; op2val:0xbbce; + valaddr_reg:x1; val_offset:128*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 128*FLEN/8, x2, x3, x8) + +inst_97: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x03d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x43d; op2val:0xbc3f; + valaddr_reg:x1; val_offset:130*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 130*FLEN/8, x2, x3, x8) + +inst_98: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x00c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x40c; op2val:0xbcf1; + valaddr_reg:x1; val_offset:132*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 132*FLEN/8, x2, x3, x8) + +inst_99: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x058 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x186 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x458; op2val:0xbd86; + valaddr_reg:x1; val_offset:134*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 134*FLEN/8, x2, x3, x8) + +inst_100: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3e2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x780e; op2val:0x3fe2; + valaddr_reg:x1; val_offset:136*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 136*FLEN/8, x2, x3, x8) + +inst_101: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x03a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x38f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x783a; op2val:0x3f8f; + valaddr_reg:x1; val_offset:138*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 138*FLEN/8, x2, x3, x8) + +inst_102: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x043 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x37d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7843; op2val:0x3f7d; + valaddr_reg:x1; val_offset:140*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 140*FLEN/8, x2, x3, x8) + +inst_103: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x033 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x396 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7833; op2val:0x3f96; + valaddr_reg:x1; val_offset:142*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 142*FLEN/8, x2, x3, x8) + +inst_104: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x042 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x374 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7842; op2val:0x3f74; + valaddr_reg:x1; val_offset:144*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 144*FLEN/8, x2, x3, x8) + +inst_105: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x013 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3ba and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7813; op2val:0x3fba; + valaddr_reg:x1; val_offset:146*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 146*FLEN/8, x2, x3, x8) + +inst_106: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x022 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x37f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7822; op2val:0x3f7f; + valaddr_reg:x1; val_offset:148*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 148*FLEN/8, x2, x3, x8) + +inst_107: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2f7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x784e; op2val:0x3ef7; + valaddr_reg:x1; val_offset:150*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 150*FLEN/8, x2, x3, x8) + +inst_108: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x054 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x277 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7854; op2val:0x3e77; + valaddr_reg:x1; val_offset:152*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 152*FLEN/8, x2, x3, x8) + +inst_109: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x05a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x182 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x785a; op2val:0x3d82; + valaddr_reg:x1; val_offset:154*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 154*FLEN/8, x2, x3, x8) + +inst_110: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x012 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3da and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7812; op2val:0xbfda; + valaddr_reg:x1; val_offset:156*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 156*FLEN/8, x2, x3, x8) + +inst_111: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x008 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3ed and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7808; op2val:0xbfed; + valaddr_reg:x1; val_offset:158*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 158*FLEN/8, x2, x3, x8) + +inst_112: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x005 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3f1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7805; op2val:0xbff1; + valaddr_reg:x1; val_offset:160*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 160*FLEN/8, x2, x3, x8) + +inst_113: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x015 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3ce and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7815; op2val:0xbfce; + valaddr_reg:x1; val_offset:162*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 162*FLEN/8, x2, x3, x8) + +inst_114: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3d5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x780d; op2val:0xbfd5; + valaddr_reg:x1; val_offset:164*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 164*FLEN/8, x2, x3, x8) + +inst_115: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x052 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x349 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7852; op2val:0xbf49; + valaddr_reg:x1; val_offset:166*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 166*FLEN/8, x2, x3, x8) + +inst_116: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x042 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x346 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7842; op2val:0xbf46; + valaddr_reg:x1; val_offset:168*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 168*FLEN/8, x2, x3, x8) + +inst_117: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x005 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x375 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7805; op2val:0xbf75; + valaddr_reg:x1; val_offset:170*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 170*FLEN/8, x2, x3, x8) + +inst_118: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x01e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2cc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x781e; op2val:0xbecc; + valaddr_reg:x1; val_offset:172*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 172*FLEN/8, x2, x3, x8) + +inst_119: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x039 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1ae and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7839; op2val:0xbdae; + valaddr_reg:x1; val_offset:174*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 174*FLEN/8, x2, x3, x8) + +inst_120: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00b and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1d1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xb; op2val:0x31d1; + valaddr_reg:x1; val_offset:176*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 176*FLEN/8, x2, x3, x8) + +inst_121: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x056 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x1f4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x56; op2val:0x2df4; + valaddr_reg:x1; val_offset:178*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 178*FLEN/8, x2, x3, x8) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(8,32,FLEN) +NAN_BOXED(12294,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(22,32,FLEN) +NAN_BOXED(12753,32,FLEN) +NAN_BOXED(86,32,FLEN) +NAN_BOXED(86,32,FLEN) +NAN_BOXED(33,32,FLEN) +NAN_BOXED(14273,32,FLEN) +NAN_BOXED(28,32,FLEN) +NAN_BOXED(15506,32,FLEN) +NAN_BOXED(5,32,FLEN) +NAN_BOXED(19046,32,FLEN) +NAN_BOXED(88,32,FLEN) +NAN_BOXED(15825,32,FLEN) +NAN_BOXED(56,32,FLEN) +NAN_BOXED(17554,32,FLEN) +NAN_BOXED(51,32,FLEN) +NAN_BOXED(18693,32,FLEN) +NAN_BOXED(66,32,FLEN) +NAN_BOXED(41935,16,FLEN) +NAN_BOXED(70,32,FLEN) +NAN_BOXED(42832,16,FLEN) +NAN_BOXED(65,32,FLEN) +NAN_BOXED(44000,16,FLEN) +test_dataset_1: +NAN_BOXED(5,32,FLEN) +NAN_BOXED(48742,16,FLEN) +NAN_BOXED(47,32,FLEN) +NAN_BOXED(46450,16,FLEN) +NAN_BOXED(41,32,FLEN) +NAN_BOXED(47678,16,FLEN) +NAN_BOXED(55,32,FLEN) +NAN_BOXED(48295,16,FLEN) +NAN_BOXED(22,32,FLEN) +NAN_BOXED(50641,16,FLEN) +NAN_BOXED(23,32,FLEN) +NAN_BOXED(51600,16,FLEN) +NAN_BOXED(30,32,FLEN) +NAN_BOXED(52292,16,FLEN) +NAN_BOXED(15383,32,FLEN) +NAN_BOXED(15316,32,FLEN) +NAN_BOXED(15383,32,FLEN) +NAN_BOXED(15318,32,FLEN) +NAN_BOXED(15426,32,FLEN) +NAN_BOXED(15243,32,FLEN) +test_dataset_2: +NAN_BOXED(15407,32,FLEN) +NAN_BOXED(15285,32,FLEN) +NAN_BOXED(15447,32,FLEN) +NAN_BOXED(15229,32,FLEN) +NAN_BOXED(15384,32,FLEN) +NAN_BOXED(15367,32,FLEN) +NAN_BOXED(15414,32,FLEN) +NAN_BOXED(15369,32,FLEN) +NAN_BOXED(15428,32,FLEN) +NAN_BOXED(15416,32,FLEN) +NAN_BOXED(15407,32,FLEN) +NAN_BOXED(15559,32,FLEN) +NAN_BOXED(15406,32,FLEN) +NAN_BOXED(15805,32,FLEN) +NAN_BOXED(15418,32,FLEN) +NAN_BOXED(48020,16,FLEN) +NAN_BOXED(15457,32,FLEN) +NAN_BOXED(47954,16,FLEN) +test_dataset_3: +NAN_BOXED(15452,16,FLEN) +NAN_BOXED(47966,16,FLEN) +NAN_BOXED(15420,16,FLEN) +NAN_BOXED(48029,16,FLEN) +NAN_BOXED(15428,16,FLEN) +NAN_BOXED(48030,16,FLEN) +NAN_BOXED(15423,16,FLEN) +NAN_BOXED(48069,16,FLEN) +NAN_BOXED(15424,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(15426,16,FLEN) +NAN_BOXED(48186,16,FLEN) +NAN_BOXED(15445,16,FLEN) +NAN_BOXED(48285,16,FLEN) +NAN_BOXED(15420,16,FLEN) +NAN_BOXED(48554,16,FLEN) +NAN_BOXED(73,16,FLEN) +NAN_BOXED(8975,16,FLEN) +NAN_BOXED(72,16,FLEN) +NAN_BOXED(10581,16,FLEN) +NAN_BOXED(59,16,FLEN) +NAN_BOXED(11628,16,FLEN) +NAN_BOXED(85,16,FLEN) +NAN_BOXED(11974,16,FLEN) +NAN_BOXED(42,16,FLEN) +NAN_BOXED(13945,16,FLEN) +NAN_BOXED(22,16,FLEN) +NAN_BOXED(15872,16,FLEN) +NAN_BOXED(35,16,FLEN) +NAN_BOXED(16237,16,FLEN) +NAN_BOXED(62,16,FLEN) +NAN_BOXED(16425,16,FLEN) +NAN_BOXED(39,16,FLEN) +NAN_BOXED(18070,16,FLEN) +NAN_BOXED(65,16,FLEN) +NAN_BOXED(18404,16,FLEN) +NAN_BOXED(67,16,FLEN) +NAN_BOXED(41905,16,FLEN) +NAN_BOXED(84,16,FLEN) +NAN_BOXED(43154,16,FLEN) +NAN_BOXED(76,16,FLEN) +NAN_BOXED(44085,16,FLEN) +NAN_BOXED(40,16,FLEN) +NAN_BOXED(45875,16,FLEN) +NAN_BOXED(27,16,FLEN) +NAN_BOXED(47369,16,FLEN) +NAN_BOXED(66,16,FLEN) +NAN_BOXED(47104,16,FLEN) +NAN_BOXED(88,16,FLEN) +NAN_BOXED(47592,16,FLEN) +NAN_BOXED(10,16,FLEN) +NAN_BOXED(51827,16,FLEN) +NAN_BOXED(93,16,FLEN) +NAN_BOXED(49542,16,FLEN) +NAN_BOXED(25,16,FLEN) +NAN_BOXED(52513,16,FLEN) +NAN_BOXED(14,16,FLEN) +NAN_BOXED(21648,16,FLEN) +NAN_BOXED(74,16,FLEN) +NAN_BOXED(19174,16,FLEN) +NAN_BOXED(7,16,FLEN) +NAN_BOXED(22668,16,FLEN) +NAN_BOXED(76,16,FLEN) +NAN_BOXED(19117,16,FLEN) +NAN_BOXED(88,16,FLEN) +NAN_BOXED(18872,16,FLEN) +NAN_BOXED(97,16,FLEN) +NAN_BOXED(18715,16,FLEN) +NAN_BOXED(18,16,FLEN) +NAN_BOXED(21160,16,FLEN) +NAN_BOXED(32,16,FLEN) +NAN_BOXED(20222,16,FLEN) +NAN_BOXED(8,16,FLEN) +NAN_BOXED(22014,16,FLEN) +NAN_BOXED(92,16,FLEN) +NAN_BOXED(17805,16,FLEN) +NAN_BOXED(5,16,FLEN) +NAN_BOXED(55907,16,FLEN) +NAN_BOXED(47,16,FLEN) +NAN_BOXED(52590,16,FLEN) +NAN_BOXED(23,16,FLEN) +NAN_BOXED(53641,16,FLEN) +NAN_BOXED(87,16,FLEN) +NAN_BOXED(51669,16,FLEN) +NAN_BOXED(11,16,FLEN) +NAN_BOXED(54712,16,FLEN) +NAN_BOXED(9,16,FLEN) +NAN_BOXED(55009,16,FLEN) +NAN_BOXED(6,16,FLEN) +NAN_BOXED(55550,16,FLEN) +NAN_BOXED(3,16,FLEN) +NAN_BOXED(56489,16,FLEN) +NAN_BOXED(33,16,FLEN) +NAN_BOXED(52687,16,FLEN) +NAN_BOXED(21,16,FLEN) +NAN_BOXED(52757,16,FLEN) +NAN_BOXED(1048,16,FLEN) +NAN_BOXED(15315,16,FLEN) +NAN_BOXED(1113,16,FLEN) +NAN_BOXED(15199,16,FLEN) +NAN_BOXED(1074,16,FLEN) +NAN_BOXED(15272,16,FLEN) +NAN_BOXED(1030,16,FLEN) +NAN_BOXED(15361,16,FLEN) +NAN_BOXED(1044,16,FLEN) +NAN_BOXED(15352,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(15390,16,FLEN) +NAN_BOXED(1103,16,FLEN) +NAN_BOXED(15332,16,FLEN) +NAN_BOXED(1120,16,FLEN) +NAN_BOXED(15389,16,FLEN) +NAN_BOXED(1039,16,FLEN) +NAN_BOXED(15597,16,FLEN) +NAN_BOXED(1068,16,FLEN) +NAN_BOXED(15808,16,FLEN) +NAN_BOXED(1028,16,FLEN) +NAN_BOXED(48122,16,FLEN) +NAN_BOXED(1082,16,FLEN) +NAN_BOXED(48022,16,FLEN) +NAN_BOXED(1123,16,FLEN) +NAN_BOXED(47954,16,FLEN) +NAN_BOXED(1119,16,FLEN) +NAN_BOXED(47968,16,FLEN) +NAN_BOXED(1058,16,FLEN) +NAN_BOXED(48093,16,FLEN) +NAN_BOXED(1076,16,FLEN) +NAN_BOXED(48089,16,FLEN) +NAN_BOXED(1115,16,FLEN) +NAN_BOXED(48078,16,FLEN) +NAN_BOXED(1085,16,FLEN) +NAN_BOXED(48191,16,FLEN) +NAN_BOXED(1036,16,FLEN) +NAN_BOXED(48369,16,FLEN) +NAN_BOXED(1112,16,FLEN) +NAN_BOXED(48518,16,FLEN) +NAN_BOXED(30734,16,FLEN) +NAN_BOXED(16354,16,FLEN) +NAN_BOXED(30778,16,FLEN) +NAN_BOXED(16271,16,FLEN) +NAN_BOXED(30787,16,FLEN) +NAN_BOXED(16253,16,FLEN) +NAN_BOXED(30771,16,FLEN) +NAN_BOXED(16278,16,FLEN) +NAN_BOXED(30786,16,FLEN) +NAN_BOXED(16244,16,FLEN) +NAN_BOXED(30739,16,FLEN) +NAN_BOXED(16314,16,FLEN) +NAN_BOXED(30754,16,FLEN) +NAN_BOXED(16255,16,FLEN) +NAN_BOXED(30798,16,FLEN) +NAN_BOXED(16119,16,FLEN) +NAN_BOXED(30804,16,FLEN) +NAN_BOXED(15991,16,FLEN) +NAN_BOXED(30810,16,FLEN) +NAN_BOXED(15746,16,FLEN) +NAN_BOXED(30738,16,FLEN) +NAN_BOXED(49114,16,FLEN) +NAN_BOXED(30728,16,FLEN) +NAN_BOXED(49133,16,FLEN) +NAN_BOXED(30725,16,FLEN) +NAN_BOXED(49137,16,FLEN) +NAN_BOXED(30741,16,FLEN) +NAN_BOXED(49102,16,FLEN) +NAN_BOXED(30733,16,FLEN) +NAN_BOXED(49109,16,FLEN) +NAN_BOXED(30802,16,FLEN) +NAN_BOXED(48969,16,FLEN) +NAN_BOXED(30786,16,FLEN) +NAN_BOXED(48966,16,FLEN) +NAN_BOXED(30725,16,FLEN) +NAN_BOXED(49013,16,FLEN) +NAN_BOXED(30750,16,FLEN) +NAN_BOXED(48844,16,FLEN) +NAN_BOXED(30777,16,FLEN) +NAN_BOXED(48558,16,FLEN) +NAN_BOXED(11,16,FLEN) +NAN_BOXED(12753,16,FLEN) +NAN_BOXED(86,16,FLEN) +NAN_BOXED(11764,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x4_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x4_1: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x12_0: + .fill 22*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x3_0: + .fill 194*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fmul_b3-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fmul_b3-01.S new file mode 100644 index 000000000..2d2265901 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fmul_b3-01.S @@ -0,0 +1,11244 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 04:50:26 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fmul.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fmul.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fmul_b3 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fmul_b3) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x7,test_dataset_0) +RVTEST_SIGBASE(x2,signature_x2_1) + +inst_0: +// rs1 == rd != rs2, rs1==x20, rs2==x11, rd==x20,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x20; op2:x11; dest:x20; op1val:0x7ba5; op2val:0x0; + valaddr_reg:x7; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x20, x20, x11, dyn, 0, 0, x7, 0*FLEN/8, x10, x2, x3) + +inst_1: +// rs1 == rs2 == rd, rs1==x22, rs2==x22, rd==x22,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x22; op2:x22; dest:x22; op1val:0x7ba5; op2val:0x7ba5; + valaddr_reg:x7; val_offset:2*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x22, x22, x22, dyn, 32, 0, x7, 2*FLEN/8, x10, x2, x3) + +inst_2: +// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==x19, rs2==x4, rd==x16,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x19; op2:x4; dest:x16; op1val:0x7ba5; op2val:0x0; + valaddr_reg:x7; val_offset:4*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x16, x19, x4, dyn, 64, 0, x7, 4*FLEN/8, x10, x2, x3) + +inst_3: +// rs1 == rs2 != rd, rs1==x6, rs2==x6, rd==x5,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x6; op2:x6; dest:x5; op1val:0x7ba5; op2val:0x7ba5; + valaddr_reg:x7; val_offset:6*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x5, x6, x6, dyn, 96, 0, x7, 6*FLEN/8, x10, x2, x3) + +inst_4: +// rs2 == rd != rs1, rs1==x26, rs2==x14, rd==x14,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x26; op2:x14; dest:x14; op1val:0x7ba5; op2val:0x0; + valaddr_reg:x7; val_offset:8*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x14, x26, x14, dyn, 128, 0, x7, 8*FLEN/8, x10, x2, x3) + +inst_5: +// rs1==x21, rs2==x31, rd==x27,fs1 == 0 and fe1 == 0x1a and fm1 == 0x33c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x21; op2:x31; dest:x27; op1val:0x6b3c; op2val:0x0; + valaddr_reg:x7; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x27, x21, x31, dyn, 0, 0, x7, 10*FLEN/8, x10, x2, x3) + +inst_6: +// rs1==x8, rs2==x25, rd==x24,fs1 == 0 and fe1 == 0x1a and fm1 == 0x33c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x8; op2:x25; dest:x24; op1val:0x6b3c; op2val:0x0; + valaddr_reg:x7; val_offset:12*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x24, x8, x25, dyn, 32, 0, x7, 12*FLEN/8, x10, x2, x3) + +inst_7: +// rs1==x9, rs2==x5, rd==x30,fs1 == 0 and fe1 == 0x1a and fm1 == 0x33c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x9; op2:x5; dest:x30; op1val:0x6b3c; op2val:0x0; + valaddr_reg:x7; val_offset:14*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x30, x9, x5, dyn, 64, 0, x7, 14*FLEN/8, x10, x2, x3) + +inst_8: +// rs1==x13, rs2==x16, rd==x28,fs1 == 0 and fe1 == 0x1a and fm1 == 0x33c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x13; op2:x16; dest:x28; op1val:0x6b3c; op2val:0x0; + valaddr_reg:x7; val_offset:16*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x28, x13, x16, dyn, 96, 0, x7, 16*FLEN/8, x10, x2, x3) + +inst_9: +// rs1==x14, rs2==x24, rd==x26,fs1 == 0 and fe1 == 0x1a and fm1 == 0x33c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x14; op2:x24; dest:x26; op1val:0x6b3c; op2val:0x0; + valaddr_reg:x7; val_offset:18*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x26, x14, x24, dyn, 128, 0, x7, 18*FLEN/8, x10, x2, x3) + +inst_10: +// rs1==x15, rs2==x8, rd==x13,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x15; op2:x8; dest:x13; op1val:0x7aae; op2val:0x0; + valaddr_reg:x7; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x13, x15, x8, dyn, 0, 0, x7, 20*FLEN/8, x10, x2, x3) + +inst_11: +// rs1==x1, rs2==x19, rd==x17,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x1; op2:x19; dest:x17; op1val:0x7aae; op2val:0x0; + valaddr_reg:x7; val_offset:22*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x17, x1, x19, dyn, 32, 0, x7, 22*FLEN/8, x10, x2, x3) +RVTEST_VALBASEUPD(x5,test_dataset_1) + +inst_12: +// rs1==x0, rs2==x12, rd==x19,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x0; op2:x12; dest:x19; op1val:0x0; op2val:0x0; + valaddr_reg:x5; val_offset:0*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x19, x0, x12, dyn, 64, 0, x5, 0*FLEN/8, x8, x2, x3) + +inst_13: +// rs1==x28, rs2==x20, rd==x9,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x28; op2:x20; dest:x9; op1val:0x7aae; op2val:0x0; + valaddr_reg:x5; val_offset:2*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x9, x28, x20, dyn, 96, 0, x5, 2*FLEN/8, x8, x2, x3) + +inst_14: +// rs1==x25, rs2==x23, rd==x29,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x25; op2:x23; dest:x29; op1val:0x7aae; op2val:0x0; + valaddr_reg:x5; val_offset:4*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x29, x25, x23, dyn, 128, 0, x5, 4*FLEN/8, x8, x2, x3) +RVTEST_SIGBASE(x14,signature_x14_0) + +inst_15: +// rs1==x30, rs2==x2, rd==x11,fs1 == 0 and fe1 == 0x1e and fm1 == 0x15a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x2; dest:x11; op1val:0x795a; op2val:0x0; + valaddr_reg:x5; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x19 +*/ +TEST_FPRR_OP(fmul.h, x11, x30, x2, dyn, 0, 0, x5, 6*FLEN/8, x8, x14, x19) + +inst_16: +// rs1==x17, rs2==x30, rd==x3,fs1 == 0 and fe1 == 0x1e and fm1 == 0x15a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x17; op2:x30; dest:x3; op1val:0x795a; op2val:0x0; + valaddr_reg:x5; val_offset:8*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x19 +*/ +TEST_FPRR_OP(fmul.h, x3, x17, x30, dyn, 32, 0, x5, 8*FLEN/8, x8, x14, x19) + +inst_17: +// rs1==x16, rs2==x7, rd==x4,fs1 == 0 and fe1 == 0x1e and fm1 == 0x15a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x16; op2:x7; dest:x4; op1val:0x795a; op2val:0x0; + valaddr_reg:x5; val_offset:10*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x19 +*/ +TEST_FPRR_OP(fmul.h, x4, x16, x7, dyn, 64, 0, x5, 10*FLEN/8, x8, x14, x19) + +inst_18: +// rs1==x4, rs2==x28, rd==x0,fs1 == 0 and fe1 == 0x1e and fm1 == 0x15a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x4; op2:x28; dest:x0; op1val:0x795a; op2val:0x0; + valaddr_reg:x5; val_offset:12*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x19 +*/ +TEST_FPRR_OP(fmul.h, x0, x4, x28, dyn, 96, 0, x5, 12*FLEN/8, x8, x14, x19) + +inst_19: +// rs1==x31, rs2==x29, rd==x10,fs1 == 0 and fe1 == 0x1e and fm1 == 0x15a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x31; op2:x29; dest:x10; op1val:0x795a; op2val:0x0; + valaddr_reg:x5; val_offset:14*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x19 +*/ +TEST_FPRR_OP(fmul.h, x10, x31, x29, dyn, 128, 0, x5, 14*FLEN/8, x8, x14, x19) + +inst_20: +// rs1==x7, rs2==x18, rd==x15,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x7; op2:x18; dest:x15; op1val:0x78d8; op2val:0x0; + valaddr_reg:x5; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x19 +*/ +TEST_FPRR_OP(fmul.h, x15, x7, x18, dyn, 0, 0, x5, 16*FLEN/8, x8, x14, x19) + +inst_21: +// rs1==x2, rs2==x9, rd==x23,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x2; op2:x9; dest:x23; op1val:0x78d8; op2val:0x0; + valaddr_reg:x5; val_offset:18*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x19 +*/ +TEST_FPRR_OP(fmul.h, x23, x2, x9, dyn, 32, 0, x5, 18*FLEN/8, x8, x14, x19) + +inst_22: +// rs1==x10, rs2==x17, rd==x12,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x10; op2:x17; dest:x12; op1val:0x78d8; op2val:0x0; + valaddr_reg:x5; val_offset:20*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x19 +*/ +TEST_FPRR_OP(fmul.h, x12, x10, x17, dyn, 64, 0, x5, 20*FLEN/8, x8, x14, x19) + +inst_23: +// rs1==x12, rs2==x26, rd==x1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x12; op2:x26; dest:x1; op1val:0x78d8; op2val:0x0; + valaddr_reg:x5; val_offset:22*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x19 +*/ +TEST_FPRR_OP(fmul.h, x1, x12, x26, dyn, 96, 0, x5, 22*FLEN/8, x8, x14, x19) + +inst_24: +// rs1==x29, rs2==x21, rd==x6,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x29; op2:x21; dest:x6; op1val:0x78d8; op2val:0x0; + valaddr_reg:x5; val_offset:24*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x19 +*/ +TEST_FPRR_OP(fmul.h, x6, x29, x21, dyn, 128, 0, x5, 24*FLEN/8, x8, x14, x19) +RVTEST_VALBASEUPD(x4,test_dataset_2) + +inst_25: +// rs1==x11, rs2==x13, rd==x8,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x11; op2:x13; dest:x8; op1val:0x78a5; op2val:0x0; + valaddr_reg:x4; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x19 +*/ +TEST_FPRR_OP(fmul.h, x8, x11, x13, dyn, 0, 0, x4, 0*FLEN/8, x6, x14, x19) + +inst_26: +// rs1==x3, rs2==x27, rd==x2,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x3; op2:x27; dest:x2; op1val:0x78a5; op2val:0x0; + valaddr_reg:x4; val_offset:2*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x19 +*/ +TEST_FPRR_OP(fmul.h, x2, x3, x27, dyn, 32, 0, x4, 2*FLEN/8, x6, x14, x19) + +inst_27: +// rs1==x5, rs2==x1, rd==x25,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x5; op2:x1; dest:x25; op1val:0x78a5; op2val:0x0; + valaddr_reg:x4; val_offset:4*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x19 +*/ +TEST_FPRR_OP(fmul.h, x25, x5, x1, dyn, 64, 0, x4, 4*FLEN/8, x6, x14, x19) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_28: +// rs1==x27, rs2==x3, rd==x31,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x27; op2:x3; dest:x31; op1val:0x78a5; op2val:0x0; + valaddr_reg:x4; val_offset:6*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x27, x3, dyn, 96, 0, x4, 6*FLEN/8, x6, x1, x2) + +inst_29: +// rs1==x23, rs2==x10, rd==x18,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x23; op2:x10; dest:x18; op1val:0x78a5; op2val:0x0; + valaddr_reg:x4; val_offset:8*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x18, x23, x10, dyn, 128, 0, x4, 8*FLEN/8, x6, x1, x2) + +inst_30: +// rs1==x24, rs2==x15, rd==x7,fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x24; op2:x15; dest:x7; op1val:0x76e3; op2val:0x0; + valaddr_reg:x4; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x7, x24, x15, dyn, 0, 0, x4, 10*FLEN/8, x6, x1, x2) + +inst_31: +// rs1==x18, rs2==x0, rd==x21,fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x18; op2:x0; dest:x21; op1val:0x76e3; op2val:0x0; + valaddr_reg:x4; val_offset:12*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x21, x18, x0, dyn, 32, 0, x4, 12*FLEN/8, x6, x1, x2) + +inst_32: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x76e3; op2val:0x0; + valaddr_reg:x4; val_offset:14*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 14*FLEN/8, x6, x1, x2) + +inst_33: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x76e3; op2val:0x0; + valaddr_reg:x4; val_offset:16*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 16*FLEN/8, x6, x1, x2) + +inst_34: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x76e3; op2val:0x0; + valaddr_reg:x4; val_offset:18*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 18*FLEN/8, x6, x1, x2) + +inst_35: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c8; op2val:0x8000; + valaddr_reg:x4; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 20*FLEN/8, x6, x1, x2) + +inst_36: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c8; op2val:0x8000; + valaddr_reg:x4; val_offset:22*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 22*FLEN/8, x6, x1, x2) + +inst_37: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c8; op2val:0x8000; + valaddr_reg:x4; val_offset:24*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 24*FLEN/8, x6, x1, x2) + +inst_38: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c8; op2val:0x8000; + valaddr_reg:x4; val_offset:26*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 26*FLEN/8, x6, x1, x2) + +inst_39: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c8; op2val:0x8000; + valaddr_reg:x4; val_offset:28*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 28*FLEN/8, x6, x1, x2) + +inst_40: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x397 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b97; op2val:0x8000; + valaddr_reg:x4; val_offset:30*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 30*FLEN/8, x6, x1, x2) + +inst_41: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x397 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b97; op2val:0x8000; + valaddr_reg:x4; val_offset:32*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 32*FLEN/8, x6, x1, x2) + +inst_42: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x397 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b97; op2val:0x8000; + valaddr_reg:x4; val_offset:34*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 34*FLEN/8, x6, x1, x2) + +inst_43: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x397 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b97; op2val:0x8000; + valaddr_reg:x4; val_offset:36*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 36*FLEN/8, x6, x1, x2) + +inst_44: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x397 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b97; op2val:0x8000; + valaddr_reg:x4; val_offset:38*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 38*FLEN/8, x6, x1, x2) + +inst_45: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x771d; op2val:0x8000; + valaddr_reg:x4; val_offset:40*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 40*FLEN/8, x6, x1, x2) + +inst_46: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x771d; op2val:0x8000; + valaddr_reg:x4; val_offset:42*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 42*FLEN/8, x6, x1, x2) + +inst_47: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x771d; op2val:0x8000; + valaddr_reg:x4; val_offset:44*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 44*FLEN/8, x6, x1, x2) + +inst_48: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x771d; op2val:0x8000; + valaddr_reg:x4; val_offset:46*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 46*FLEN/8, x6, x1, x2) + +inst_49: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x771d; op2val:0x8000; + valaddr_reg:x4; val_offset:48*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 48*FLEN/8, x6, x1, x2) + +inst_50: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x099 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6899; op2val:0x8000; + valaddr_reg:x4; val_offset:50*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 50*FLEN/8, x6, x1, x2) + +inst_51: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x099 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6899; op2val:0x8000; + valaddr_reg:x4; val_offset:52*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 52*FLEN/8, x6, x1, x2) + +inst_52: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x099 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6899; op2val:0x8000; + valaddr_reg:x4; val_offset:54*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 54*FLEN/8, x6, x1, x2) + +inst_53: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x099 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6899; op2val:0x8000; + valaddr_reg:x4; val_offset:56*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 56*FLEN/8, x6, x1, x2) + +inst_54: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x099 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6899; op2val:0x8000; + valaddr_reg:x4; val_offset:58*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 58*FLEN/8, x6, x1, x2) + +inst_55: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x36f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x776f; op2val:0x8000; + valaddr_reg:x4; val_offset:60*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 60*FLEN/8, x6, x1, x2) + +inst_56: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x36f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x776f; op2val:0x8000; + valaddr_reg:x4; val_offset:62*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 62*FLEN/8, x6, x1, x2) + +inst_57: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x36f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x776f; op2val:0x8000; + valaddr_reg:x4; val_offset:64*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 64*FLEN/8, x6, x1, x2) + +inst_58: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x36f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x776f; op2val:0x8000; + valaddr_reg:x4; val_offset:66*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 66*FLEN/8, x6, x1, x2) + +inst_59: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x36f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x776f; op2val:0x8000; + valaddr_reg:x4; val_offset:68*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 68*FLEN/8, x6, x1, x2) + +inst_60: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x213 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7613; op2val:0x8000; + valaddr_reg:x4; val_offset:70*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 70*FLEN/8, x6, x1, x2) + +inst_61: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x213 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7613; op2val:0x8000; + valaddr_reg:x4; val_offset:72*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 72*FLEN/8, x6, x1, x2) + +inst_62: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x213 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7613; op2val:0x8000; + valaddr_reg:x4; val_offset:74*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 74*FLEN/8, x6, x1, x2) + +inst_63: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x213 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7613; op2val:0x8000; + valaddr_reg:x4; val_offset:76*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 76*FLEN/8, x6, x1, x2) + +inst_64: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x213 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7613; op2val:0x8000; + valaddr_reg:x4; val_offset:78*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 78*FLEN/8, x6, x1, x2) + +inst_65: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x034 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7834; op2val:0x8000; + valaddr_reg:x4; val_offset:80*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 80*FLEN/8, x6, x1, x2) + +inst_66: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x034 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7834; op2val:0x8000; + valaddr_reg:x4; val_offset:82*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 82*FLEN/8, x6, x1, x2) + +inst_67: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x034 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7834; op2val:0x8000; + valaddr_reg:x4; val_offset:84*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 84*FLEN/8, x6, x1, x2) + +inst_68: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x034 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7834; op2val:0x8000; + valaddr_reg:x4; val_offset:86*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 86*FLEN/8, x6, x1, x2) + +inst_69: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x034 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7834; op2val:0x8000; + valaddr_reg:x4; val_offset:88*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 88*FLEN/8, x6, x1, x2) + +inst_70: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x38d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x738d; op2val:0x8000; + valaddr_reg:x4; val_offset:90*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 90*FLEN/8, x6, x1, x2) + +inst_71: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x38d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x738d; op2val:0x8000; + valaddr_reg:x4; val_offset:92*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 92*FLEN/8, x6, x1, x2) + +inst_72: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x38d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x738d; op2val:0x8000; + valaddr_reg:x4; val_offset:94*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 94*FLEN/8, x6, x1, x2) + +inst_73: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x38d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x738d; op2val:0x8000; + valaddr_reg:x4; val_offset:96*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 96*FLEN/8, x6, x1, x2) + +inst_74: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x38d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x738d; op2val:0x8000; + valaddr_reg:x4; val_offset:98*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 98*FLEN/8, x6, x1, x2) + +inst_75: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x133 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7533; op2val:0x8000; + valaddr_reg:x4; val_offset:100*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 100*FLEN/8, x6, x1, x2) + +inst_76: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x133 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7533; op2val:0x8000; + valaddr_reg:x4; val_offset:102*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 102*FLEN/8, x6, x1, x2) + +inst_77: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x133 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7533; op2val:0x8000; + valaddr_reg:x4; val_offset:104*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 104*FLEN/8, x6, x1, x2) + +inst_78: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x133 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7533; op2val:0x8000; + valaddr_reg:x4; val_offset:106*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 106*FLEN/8, x6, x1, x2) + +inst_79: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x133 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7533; op2val:0x8000; + valaddr_reg:x4; val_offset:108*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 108*FLEN/8, x6, x1, x2) + +inst_80: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x014 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7814; op2val:0x8000; + valaddr_reg:x4; val_offset:110*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 110*FLEN/8, x6, x1, x2) + +inst_81: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x014 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7814; op2val:0x8000; + valaddr_reg:x4; val_offset:112*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 112*FLEN/8, x6, x1, x2) + +inst_82: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x014 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7814; op2val:0x8000; + valaddr_reg:x4; val_offset:114*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 114*FLEN/8, x6, x1, x2) + +inst_83: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x014 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7814; op2val:0x8000; + valaddr_reg:x4; val_offset:116*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 116*FLEN/8, x6, x1, x2) + +inst_84: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x014 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7814; op2val:0x8000; + valaddr_reg:x4; val_offset:118*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 118*FLEN/8, x6, x1, x2) + +inst_85: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x164 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7964; op2val:0x8000; + valaddr_reg:x4; val_offset:120*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 120*FLEN/8, x6, x1, x2) + +inst_86: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x164 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7964; op2val:0x8000; + valaddr_reg:x4; val_offset:122*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 122*FLEN/8, x6, x1, x2) + +inst_87: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x164 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7964; op2val:0x8000; + valaddr_reg:x4; val_offset:124*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 124*FLEN/8, x6, x1, x2) + +inst_88: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x164 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7964; op2val:0x8000; + valaddr_reg:x4; val_offset:126*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 126*FLEN/8, x6, x1, x2) + +inst_89: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x164 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7964; op2val:0x8000; + valaddr_reg:x4; val_offset:128*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 128*FLEN/8, x6, x1, x2) + +inst_90: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x325 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b25; op2val:0x8000; + valaddr_reg:x4; val_offset:130*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 130*FLEN/8, x6, x1, x2) + +inst_91: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x325 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b25; op2val:0x8000; + valaddr_reg:x4; val_offset:132*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 132*FLEN/8, x6, x1, x2) + +inst_92: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x325 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b25; op2val:0x8000; + valaddr_reg:x4; val_offset:134*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 134*FLEN/8, x6, x1, x2) + +inst_93: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x325 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b25; op2val:0x8000; + valaddr_reg:x4; val_offset:136*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 136*FLEN/8, x6, x1, x2) + +inst_94: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x325 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b25; op2val:0x8000; + valaddr_reg:x4; val_offset:138*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 138*FLEN/8, x6, x1, x2) + +inst_95: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1df and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79df; op2val:0x8000; + valaddr_reg:x4; val_offset:140*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 140*FLEN/8, x6, x1, x2) + +inst_96: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1df and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79df; op2val:0x8000; + valaddr_reg:x4; val_offset:142*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 142*FLEN/8, x6, x1, x2) + +inst_97: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1df and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79df; op2val:0x8000; + valaddr_reg:x4; val_offset:144*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 144*FLEN/8, x6, x1, x2) + +inst_98: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1df and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79df; op2val:0x8000; + valaddr_reg:x4; val_offset:146*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 146*FLEN/8, x6, x1, x2) + +inst_99: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1df and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79df; op2val:0x8000; + valaddr_reg:x4; val_offset:148*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 148*FLEN/8, x6, x1, x2) + +inst_100: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x219 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a19; op2val:0x8000; + valaddr_reg:x4; val_offset:150*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 150*FLEN/8, x6, x1, x2) + +inst_101: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x219 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a19; op2val:0x8000; + valaddr_reg:x4; val_offset:152*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 152*FLEN/8, x6, x1, x2) + +inst_102: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x219 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a19; op2val:0x8000; + valaddr_reg:x4; val_offset:154*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 154*FLEN/8, x6, x1, x2) + +inst_103: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x219 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a19; op2val:0x8000; + valaddr_reg:x4; val_offset:156*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 156*FLEN/8, x6, x1, x2) + +inst_104: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x219 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a19; op2val:0x8000; + valaddr_reg:x4; val_offset:158*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 158*FLEN/8, x6, x1, x2) + +inst_105: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x75a8; op2val:0x0; + valaddr_reg:x4; val_offset:160*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 160*FLEN/8, x6, x1, x2) + +inst_106: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x75a8; op2val:0x0; + valaddr_reg:x4; val_offset:162*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 162*FLEN/8, x6, x1, x2) + +inst_107: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x75a8; op2val:0x0; + valaddr_reg:x4; val_offset:164*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 164*FLEN/8, x6, x1, x2) + +inst_108: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x75a8; op2val:0x0; + valaddr_reg:x4; val_offset:166*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 166*FLEN/8, x6, x1, x2) + +inst_109: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x75a8; op2val:0x0; + valaddr_reg:x4; val_offset:168*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 168*FLEN/8, x6, x1, x2) + +inst_110: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb1; op2val:0x0; + valaddr_reg:x4; val_offset:170*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 170*FLEN/8, x6, x1, x2) + +inst_111: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb1; op2val:0x0; + valaddr_reg:x4; val_offset:172*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 172*FLEN/8, x6, x1, x2) + +inst_112: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb1; op2val:0x0; + valaddr_reg:x4; val_offset:174*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 174*FLEN/8, x6, x1, x2) + +inst_113: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb1; op2val:0x0; + valaddr_reg:x4; val_offset:176*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 176*FLEN/8, x6, x1, x2) + +inst_114: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb1; op2val:0x0; + valaddr_reg:x4; val_offset:178*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 178*FLEN/8, x6, x1, x2) + +inst_115: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x207 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a07; op2val:0x0; + valaddr_reg:x4; val_offset:180*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 180*FLEN/8, x6, x1, x2) + +inst_116: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x207 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a07; op2val:0x0; + valaddr_reg:x4; val_offset:182*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 182*FLEN/8, x6, x1, x2) + +inst_117: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x207 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a07; op2val:0x0; + valaddr_reg:x4; val_offset:184*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 184*FLEN/8, x6, x1, x2) + +inst_118: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x207 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a07; op2val:0x0; + valaddr_reg:x4; val_offset:186*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 186*FLEN/8, x6, x1, x2) + +inst_119: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x207 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a07; op2val:0x0; + valaddr_reg:x4; val_offset:188*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 188*FLEN/8, x6, x1, x2) + +inst_120: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x361 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7761; op2val:0x0; + valaddr_reg:x4; val_offset:190*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 190*FLEN/8, x6, x1, x2) + +inst_121: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x361 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7761; op2val:0x0; + valaddr_reg:x4; val_offset:192*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 192*FLEN/8, x6, x1, x2) + +inst_122: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x361 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7761; op2val:0x0; + valaddr_reg:x4; val_offset:194*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 194*FLEN/8, x6, x1, x2) + +inst_123: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x361 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7761; op2val:0x0; + valaddr_reg:x4; val_offset:196*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 196*FLEN/8, x6, x1, x2) + +inst_124: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x361 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7761; op2val:0x0; + valaddr_reg:x4; val_offset:198*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 198*FLEN/8, x6, x1, x2) + +inst_125: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x77d6; op2val:0x0; + valaddr_reg:x4; val_offset:200*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 200*FLEN/8, x6, x1, x2) + +inst_126: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x77d6; op2val:0x0; + valaddr_reg:x4; val_offset:202*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 202*FLEN/8, x6, x1, x2) + +inst_127: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x77d6; op2val:0x0; + valaddr_reg:x4; val_offset:204*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 204*FLEN/8, x6, x1, x2) + +inst_128: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x77d6; op2val:0x0; + valaddr_reg:x4; val_offset:206*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 206*FLEN/8, x6, x1, x2) + +inst_129: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x77d6; op2val:0x0; + valaddr_reg:x4; val_offset:208*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 208*FLEN/8, x6, x1, x2) + +inst_130: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7801; op2val:0x0; + valaddr_reg:x4; val_offset:210*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 210*FLEN/8, x6, x1, x2) + +inst_131: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7801; op2val:0x0; + valaddr_reg:x4; val_offset:212*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 212*FLEN/8, x6, x1, x2) + +inst_132: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7801; op2val:0x0; + valaddr_reg:x4; val_offset:214*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 214*FLEN/8, x6, x1, x2) + +inst_133: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7801; op2val:0x0; + valaddr_reg:x4; val_offset:216*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 216*FLEN/8, x6, x1, x2) + +inst_134: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7801; op2val:0x0; + valaddr_reg:x4; val_offset:218*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 218*FLEN/8, x6, x1, x2) + +inst_135: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x75a9; op2val:0x0; + valaddr_reg:x4; val_offset:220*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 220*FLEN/8, x6, x1, x2) + +inst_136: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x75a9; op2val:0x0; + valaddr_reg:x4; val_offset:222*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 222*FLEN/8, x6, x1, x2) + +inst_137: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x75a9; op2val:0x0; + valaddr_reg:x4; val_offset:224*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 224*FLEN/8, x6, x1, x2) + +inst_138: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x75a9; op2val:0x0; + valaddr_reg:x4; val_offset:226*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 226*FLEN/8, x6, x1, x2) + +inst_139: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x75a9; op2val:0x0; + valaddr_reg:x4; val_offset:228*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 228*FLEN/8, x6, x1, x2) + +inst_140: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x331 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b31; op2val:0x0; + valaddr_reg:x4; val_offset:230*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 230*FLEN/8, x6, x1, x2) + +inst_141: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x331 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b31; op2val:0x0; + valaddr_reg:x4; val_offset:232*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 232*FLEN/8, x6, x1, x2) + +inst_142: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x331 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b31; op2val:0x0; + valaddr_reg:x4; val_offset:234*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 234*FLEN/8, x6, x1, x2) + +inst_143: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x331 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b31; op2val:0x0; + valaddr_reg:x4; val_offset:236*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 236*FLEN/8, x6, x1, x2) + +inst_144: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x331 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b31; op2val:0x0; + valaddr_reg:x4; val_offset:238*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 238*FLEN/8, x6, x1, x2) + +inst_145: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x08a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x788a; op2val:0x0; + valaddr_reg:x4; val_offset:240*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 240*FLEN/8, x6, x1, x2) + +inst_146: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x08a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x788a; op2val:0x0; + valaddr_reg:x4; val_offset:242*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 242*FLEN/8, x6, x1, x2) + +inst_147: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x08a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x788a; op2val:0x0; + valaddr_reg:x4; val_offset:244*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 244*FLEN/8, x6, x1, x2) + +inst_148: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x08a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x788a; op2val:0x0; + valaddr_reg:x4; val_offset:246*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 246*FLEN/8, x6, x1, x2) + +inst_149: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x08a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x788a; op2val:0x0; + valaddr_reg:x4; val_offset:248*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 248*FLEN/8, x6, x1, x2) + +inst_150: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c9; op2val:0x0; + valaddr_reg:x4; val_offset:250*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 250*FLEN/8, x6, x1, x2) + +inst_151: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c9; op2val:0x0; + valaddr_reg:x4; val_offset:252*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 252*FLEN/8, x6, x1, x2) + +inst_152: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c9; op2val:0x0; + valaddr_reg:x4; val_offset:254*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 254*FLEN/8, x6, x1, x2) + +inst_153: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c9; op2val:0x0; + valaddr_reg:x4; val_offset:256*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 256*FLEN/8, x6, x1, x2) + +inst_154: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c9; op2val:0x0; + valaddr_reg:x4; val_offset:258*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 258*FLEN/8, x6, x1, x2) + +inst_155: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x318 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7318; op2val:0x0; + valaddr_reg:x4; val_offset:260*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 260*FLEN/8, x6, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_156: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x318 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7318; op2val:0x0; + valaddr_reg:x4; val_offset:262*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 262*FLEN/8, x6, x1, x2) + +inst_157: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x318 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7318; op2val:0x0; + valaddr_reg:x4; val_offset:264*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 264*FLEN/8, x6, x1, x2) + +inst_158: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x318 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7318; op2val:0x0; + valaddr_reg:x4; val_offset:266*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 266*FLEN/8, x6, x1, x2) + +inst_159: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x318 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7318; op2val:0x0; + valaddr_reg:x4; val_offset:268*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 268*FLEN/8, x6, x1, x2) + +inst_160: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x198 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7998; op2val:0x0; + valaddr_reg:x4; val_offset:270*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 270*FLEN/8, x6, x1, x2) + +inst_161: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x198 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7998; op2val:0x0; + valaddr_reg:x4; val_offset:272*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 272*FLEN/8, x6, x1, x2) + +inst_162: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x198 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7998; op2val:0x0; + valaddr_reg:x4; val_offset:274*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 274*FLEN/8, x6, x1, x2) + +inst_163: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x198 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7998; op2val:0x0; + valaddr_reg:x4; val_offset:276*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 276*FLEN/8, x6, x1, x2) + +inst_164: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x198 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7998; op2val:0x0; + valaddr_reg:x4; val_offset:278*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 278*FLEN/8, x6, x1, x2) + +inst_165: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x342 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b42; op2val:0x0; + valaddr_reg:x4; val_offset:280*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 280*FLEN/8, x6, x1, x2) + +inst_166: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x342 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b42; op2val:0x0; + valaddr_reg:x4; val_offset:282*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 282*FLEN/8, x6, x1, x2) + +inst_167: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x342 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b42; op2val:0x0; + valaddr_reg:x4; val_offset:284*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 284*FLEN/8, x6, x1, x2) + +inst_168: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x342 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b42; op2val:0x0; + valaddr_reg:x4; val_offset:286*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 286*FLEN/8, x6, x1, x2) + +inst_169: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x342 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b42; op2val:0x0; + valaddr_reg:x4; val_offset:288*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 288*FLEN/8, x6, x1, x2) + +inst_170: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x349 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b49; op2val:0x0; + valaddr_reg:x4; val_offset:290*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 290*FLEN/8, x6, x1, x2) + +inst_171: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x349 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b49; op2val:0x0; + valaddr_reg:x4; val_offset:292*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 292*FLEN/8, x6, x1, x2) + +inst_172: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x349 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b49; op2val:0x0; + valaddr_reg:x4; val_offset:294*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 294*FLEN/8, x6, x1, x2) + +inst_173: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x349 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b49; op2val:0x0; + valaddr_reg:x4; val_offset:296*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 296*FLEN/8, x6, x1, x2) + +inst_174: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x349 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b49; op2val:0x0; + valaddr_reg:x4; val_offset:298*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 298*FLEN/8, x6, x1, x2) + +inst_175: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba7; op2val:0x8000; + valaddr_reg:x4; val_offset:300*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 300*FLEN/8, x6, x1, x2) + +inst_176: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba7; op2val:0x8000; + valaddr_reg:x4; val_offset:302*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 302*FLEN/8, x6, x1, x2) + +inst_177: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba7; op2val:0x8000; + valaddr_reg:x4; val_offset:304*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 304*FLEN/8, x6, x1, x2) + +inst_178: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba7; op2val:0x8000; + valaddr_reg:x4; val_offset:306*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 306*FLEN/8, x6, x1, x2) + +inst_179: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba7; op2val:0x8000; + valaddr_reg:x4; val_offset:308*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 308*FLEN/8, x6, x1, x2) + +inst_180: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x008 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7808; op2val:0x8000; + valaddr_reg:x4; val_offset:310*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 310*FLEN/8, x6, x1, x2) + +inst_181: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x008 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7808; op2val:0x8000; + valaddr_reg:x4; val_offset:312*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 312*FLEN/8, x6, x1, x2) + +inst_182: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x008 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7808; op2val:0x8000; + valaddr_reg:x4; val_offset:314*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 314*FLEN/8, x6, x1, x2) + +inst_183: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x008 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7808; op2val:0x8000; + valaddr_reg:x4; val_offset:316*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 316*FLEN/8, x6, x1, x2) + +inst_184: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x008 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7808; op2val:0x8000; + valaddr_reg:x4; val_offset:318*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 318*FLEN/8, x6, x1, x2) + +inst_185: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x135 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7935; op2val:0x8000; + valaddr_reg:x4; val_offset:320*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 320*FLEN/8, x6, x1, x2) + +inst_186: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x135 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7935; op2val:0x8000; + valaddr_reg:x4; val_offset:322*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 322*FLEN/8, x6, x1, x2) + +inst_187: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x135 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7935; op2val:0x8000; + valaddr_reg:x4; val_offset:324*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 324*FLEN/8, x6, x1, x2) + +inst_188: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x135 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7935; op2val:0x8000; + valaddr_reg:x4; val_offset:326*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 326*FLEN/8, x6, x1, x2) + +inst_189: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x135 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7935; op2val:0x8000; + valaddr_reg:x4; val_offset:328*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 328*FLEN/8, x6, x1, x2) + +inst_190: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x74fc; op2val:0x8000; + valaddr_reg:x4; val_offset:330*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 330*FLEN/8, x6, x1, x2) + +inst_191: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x74fc; op2val:0x8000; + valaddr_reg:x4; val_offset:332*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 332*FLEN/8, x6, x1, x2) + +inst_192: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x74fc; op2val:0x8000; + valaddr_reg:x4; val_offset:334*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 334*FLEN/8, x6, x1, x2) + +inst_193: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x74fc; op2val:0x8000; + valaddr_reg:x4; val_offset:336*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 336*FLEN/8, x6, x1, x2) + +inst_194: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x74fc; op2val:0x8000; + valaddr_reg:x4; val_offset:338*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 338*FLEN/8, x6, x1, x2) + +inst_195: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x017 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7817; op2val:0x8000; + valaddr_reg:x4; val_offset:340*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 340*FLEN/8, x6, x1, x2) + +inst_196: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x017 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7817; op2val:0x8000; + valaddr_reg:x4; val_offset:342*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 342*FLEN/8, x6, x1, x2) + +inst_197: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x017 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7817; op2val:0x8000; + valaddr_reg:x4; val_offset:344*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 344*FLEN/8, x6, x1, x2) + +inst_198: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x017 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7817; op2val:0x8000; + valaddr_reg:x4; val_offset:346*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 346*FLEN/8, x6, x1, x2) + +inst_199: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x017 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7817; op2val:0x8000; + valaddr_reg:x4; val_offset:348*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 348*FLEN/8, x6, x1, x2) + +inst_200: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x78fb; op2val:0x8000; + valaddr_reg:x4; val_offset:350*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 350*FLEN/8, x6, x1, x2) + +inst_201: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x78fb; op2val:0x8000; + valaddr_reg:x4; val_offset:352*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 352*FLEN/8, x6, x1, x2) + +inst_202: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x78fb; op2val:0x8000; + valaddr_reg:x4; val_offset:354*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 354*FLEN/8, x6, x1, x2) + +inst_203: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x78fb; op2val:0x8000; + valaddr_reg:x4; val_offset:356*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 356*FLEN/8, x6, x1, x2) + +inst_204: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x78fb; op2val:0x8000; + valaddr_reg:x4; val_offset:358*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 358*FLEN/8, x6, x1, x2) + +inst_205: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a8f; op2val:0x8000; + valaddr_reg:x4; val_offset:360*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 360*FLEN/8, x6, x1, x2) + +inst_206: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a8f; op2val:0x8000; + valaddr_reg:x4; val_offset:362*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 362*FLEN/8, x6, x1, x2) + +inst_207: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a8f; op2val:0x8000; + valaddr_reg:x4; val_offset:364*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 364*FLEN/8, x6, x1, x2) + +inst_208: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a8f; op2val:0x8000; + valaddr_reg:x4; val_offset:366*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 366*FLEN/8, x6, x1, x2) + +inst_209: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a8f; op2val:0x8000; + valaddr_reg:x4; val_offset:368*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 368*FLEN/8, x6, x1, x2) + +inst_210: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x341 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b41; op2val:0x8000; + valaddr_reg:x4; val_offset:370*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 370*FLEN/8, x6, x1, x2) + +inst_211: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x341 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b41; op2val:0x8000; + valaddr_reg:x4; val_offset:372*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 372*FLEN/8, x6, x1, x2) + +inst_212: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x341 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b41; op2val:0x8000; + valaddr_reg:x4; val_offset:374*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 374*FLEN/8, x6, x1, x2) + +inst_213: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x341 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b41; op2val:0x8000; + valaddr_reg:x4; val_offset:376*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 376*FLEN/8, x6, x1, x2) + +inst_214: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x341 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b41; op2val:0x8000; + valaddr_reg:x4; val_offset:378*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 378*FLEN/8, x6, x1, x2) + +inst_215: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79f4; op2val:0x8000; + valaddr_reg:x4; val_offset:380*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 380*FLEN/8, x6, x1, x2) + +inst_216: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79f4; op2val:0x8000; + valaddr_reg:x4; val_offset:382*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 382*FLEN/8, x6, x1, x2) + +inst_217: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79f4; op2val:0x8000; + valaddr_reg:x4; val_offset:384*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 384*FLEN/8, x6, x1, x2) + +inst_218: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79f4; op2val:0x8000; + valaddr_reg:x4; val_offset:386*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 386*FLEN/8, x6, x1, x2) + +inst_219: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79f4; op2val:0x8000; + valaddr_reg:x4; val_offset:388*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 388*FLEN/8, x6, x1, x2) + +inst_220: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x138 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7938; op2val:0x8000; + valaddr_reg:x4; val_offset:390*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 390*FLEN/8, x6, x1, x2) + +inst_221: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x138 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7938; op2val:0x8000; + valaddr_reg:x4; val_offset:392*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 392*FLEN/8, x6, x1, x2) + +inst_222: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x138 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7938; op2val:0x8000; + valaddr_reg:x4; val_offset:394*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 394*FLEN/8, x6, x1, x2) + +inst_223: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x138 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7938; op2val:0x8000; + valaddr_reg:x4; val_offset:396*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 396*FLEN/8, x6, x1, x2) + +inst_224: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x138 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7938; op2val:0x8000; + valaddr_reg:x4; val_offset:398*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 398*FLEN/8, x6, x1, x2) + +inst_225: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x33f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x733f; op2val:0x8000; + valaddr_reg:x4; val_offset:400*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 400*FLEN/8, x6, x1, x2) + +inst_226: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x33f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x733f; op2val:0x8000; + valaddr_reg:x4; val_offset:402*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 402*FLEN/8, x6, x1, x2) + +inst_227: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x33f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x733f; op2val:0x8000; + valaddr_reg:x4; val_offset:404*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 404*FLEN/8, x6, x1, x2) + +inst_228: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x33f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x733f; op2val:0x8000; + valaddr_reg:x4; val_offset:406*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 406*FLEN/8, x6, x1, x2) + +inst_229: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x33f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x733f; op2val:0x8000; + valaddr_reg:x4; val_offset:408*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 408*FLEN/8, x6, x1, x2) + +inst_230: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2cc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ecc; op2val:0x8000; + valaddr_reg:x4; val_offset:410*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 410*FLEN/8, x6, x1, x2) + +inst_231: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2cc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ecc; op2val:0x8000; + valaddr_reg:x4; val_offset:412*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 412*FLEN/8, x6, x1, x2) + +inst_232: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2cc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ecc; op2val:0x8000; + valaddr_reg:x4; val_offset:414*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 414*FLEN/8, x6, x1, x2) + +inst_233: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2cc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ecc; op2val:0x8000; + valaddr_reg:x4; val_offset:416*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 416*FLEN/8, x6, x1, x2) + +inst_234: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2cc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ecc; op2val:0x8000; + valaddr_reg:x4; val_offset:418*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 418*FLEN/8, x6, x1, x2) + +inst_235: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ad4; op2val:0x8000; + valaddr_reg:x4; val_offset:420*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 420*FLEN/8, x6, x1, x2) + +inst_236: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ad4; op2val:0x8000; + valaddr_reg:x4; val_offset:422*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 422*FLEN/8, x6, x1, x2) + +inst_237: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ad4; op2val:0x8000; + valaddr_reg:x4; val_offset:424*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 424*FLEN/8, x6, x1, x2) + +inst_238: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ad4; op2val:0x8000; + valaddr_reg:x4; val_offset:426*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 426*FLEN/8, x6, x1, x2) + +inst_239: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ad4; op2val:0x8000; + valaddr_reg:x4; val_offset:428*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 428*FLEN/8, x6, x1, x2) + +inst_240: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x72bb; op2val:0x8000; + valaddr_reg:x4; val_offset:430*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 430*FLEN/8, x6, x1, x2) + +inst_241: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x72bb; op2val:0x8000; + valaddr_reg:x4; val_offset:432*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 432*FLEN/8, x6, x1, x2) + +inst_242: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x72bb; op2val:0x8000; + valaddr_reg:x4; val_offset:434*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 434*FLEN/8, x6, x1, x2) + +inst_243: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x72bb; op2val:0x8000; + valaddr_reg:x4; val_offset:436*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 436*FLEN/8, x6, x1, x2) + +inst_244: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x72bb; op2val:0x8000; + valaddr_reg:x4; val_offset:438*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 438*FLEN/8, x6, x1, x2) + +inst_245: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2c3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x76c3; op2val:0x0; + valaddr_reg:x4; val_offset:440*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 440*FLEN/8, x6, x1, x2) + +inst_246: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2c3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x76c3; op2val:0x0; + valaddr_reg:x4; val_offset:442*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 442*FLEN/8, x6, x1, x2) + +inst_247: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2c3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x76c3; op2val:0x0; + valaddr_reg:x4; val_offset:444*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 444*FLEN/8, x6, x1, x2) + +inst_248: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2c3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x76c3; op2val:0x0; + valaddr_reg:x4; val_offset:446*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 446*FLEN/8, x6, x1, x2) + +inst_249: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2c3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x76c3; op2val:0x0; + valaddr_reg:x4; val_offset:448*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 448*FLEN/8, x6, x1, x2) + +inst_250: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x014 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6814; op2val:0x0; + valaddr_reg:x4; val_offset:450*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 450*FLEN/8, x6, x1, x2) + +inst_251: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x014 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6814; op2val:0x0; + valaddr_reg:x4; val_offset:452*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 452*FLEN/8, x6, x1, x2) + +inst_252: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x014 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6814; op2val:0x0; + valaddr_reg:x4; val_offset:454*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 454*FLEN/8, x6, x1, x2) + +inst_253: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x014 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6814; op2val:0x0; + valaddr_reg:x4; val_offset:456*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 456*FLEN/8, x6, x1, x2) + +inst_254: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x014 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6814; op2val:0x0; + valaddr_reg:x4; val_offset:458*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 458*FLEN/8, x6, x1, x2) + +inst_255: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x17f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x717f; op2val:0x0; + valaddr_reg:x4; val_offset:460*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 460*FLEN/8, x6, x1, x2) + +inst_256: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x17f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x717f; op2val:0x0; + valaddr_reg:x4; val_offset:462*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 462*FLEN/8, x6, x1, x2) + +inst_257: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x17f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x717f; op2val:0x0; + valaddr_reg:x4; val_offset:464*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 464*FLEN/8, x6, x1, x2) + +inst_258: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x17f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x717f; op2val:0x0; + valaddr_reg:x4; val_offset:466*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 466*FLEN/8, x6, x1, x2) + +inst_259: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x17f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x717f; op2val:0x0; + valaddr_reg:x4; val_offset:468*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 468*FLEN/8, x6, x1, x2) + +inst_260: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x14d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d4d; op2val:0x0; + valaddr_reg:x4; val_offset:470*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 470*FLEN/8, x6, x1, x2) + +inst_261: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x14d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d4d; op2val:0x0; + valaddr_reg:x4; val_offset:472*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 472*FLEN/8, x6, x1, x2) + +inst_262: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x14d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d4d; op2val:0x0; + valaddr_reg:x4; val_offset:474*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 474*FLEN/8, x6, x1, x2) + +inst_263: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x14d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d4d; op2val:0x0; + valaddr_reg:x4; val_offset:476*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 476*FLEN/8, x6, x1, x2) + +inst_264: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x14d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d4d; op2val:0x0; + valaddr_reg:x4; val_offset:478*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 478*FLEN/8, x6, x1, x2) + +inst_265: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x27d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x667d; op2val:0x0; + valaddr_reg:x4; val_offset:480*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 480*FLEN/8, x6, x1, x2) + +inst_266: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x27d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x667d; op2val:0x0; + valaddr_reg:x4; val_offset:482*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 482*FLEN/8, x6, x1, x2) + +inst_267: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x27d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x667d; op2val:0x0; + valaddr_reg:x4; val_offset:484*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 484*FLEN/8, x6, x1, x2) + +inst_268: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x27d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x667d; op2val:0x0; + valaddr_reg:x4; val_offset:486*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 486*FLEN/8, x6, x1, x2) + +inst_269: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x27d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x667d; op2val:0x0; + valaddr_reg:x4; val_offset:488*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 488*FLEN/8, x6, x1, x2) + +inst_270: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x16a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x656a; op2val:0x0; + valaddr_reg:x4; val_offset:490*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 490*FLEN/8, x6, x1, x2) + +inst_271: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x16a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x656a; op2val:0x0; + valaddr_reg:x4; val_offset:492*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 492*FLEN/8, x6, x1, x2) + +inst_272: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x16a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x656a; op2val:0x0; + valaddr_reg:x4; val_offset:494*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 494*FLEN/8, x6, x1, x2) + +inst_273: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x16a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x656a; op2val:0x0; + valaddr_reg:x4; val_offset:496*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 496*FLEN/8, x6, x1, x2) + +inst_274: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x16a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x656a; op2val:0x0; + valaddr_reg:x4; val_offset:498*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 498*FLEN/8, x6, x1, x2) + +inst_275: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x280 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a80; op2val:0x0; + valaddr_reg:x4; val_offset:500*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 500*FLEN/8, x6, x1, x2) + +inst_276: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x280 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a80; op2val:0x0; + valaddr_reg:x4; val_offset:502*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 502*FLEN/8, x6, x1, x2) + +inst_277: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x280 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a80; op2val:0x0; + valaddr_reg:x4; val_offset:504*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 504*FLEN/8, x6, x1, x2) + +inst_278: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x280 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a80; op2val:0x0; + valaddr_reg:x4; val_offset:506*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 506*FLEN/8, x6, x1, x2) + +inst_279: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x280 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a80; op2val:0x0; + valaddr_reg:x4; val_offset:508*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 508*FLEN/8, x6, x1, x2) + +inst_280: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1e0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x71e0; op2val:0x0; + valaddr_reg:x4; val_offset:510*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 510*FLEN/8, x6, x1, x2) + +inst_281: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1e0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x71e0; op2val:0x0; + valaddr_reg:x4; val_offset:512*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 512*FLEN/8, x6, x1, x2) + +inst_282: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1e0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x71e0; op2val:0x0; + valaddr_reg:x4; val_offset:514*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 514*FLEN/8, x6, x1, x2) + +inst_283: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1e0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x71e0; op2val:0x0; + valaddr_reg:x4; val_offset:516*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 516*FLEN/8, x6, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_2) + +inst_284: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1e0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x71e0; op2val:0x0; + valaddr_reg:x4; val_offset:518*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 518*FLEN/8, x6, x1, x2) + +inst_285: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x22a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x762a; op2val:0x0; + valaddr_reg:x4; val_offset:520*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 520*FLEN/8, x6, x1, x2) + +inst_286: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x22a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x762a; op2val:0x0; + valaddr_reg:x4; val_offset:522*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 522*FLEN/8, x6, x1, x2) + +inst_287: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x22a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x762a; op2val:0x0; + valaddr_reg:x4; val_offset:524*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 524*FLEN/8, x6, x1, x2) + +inst_288: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x22a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x762a; op2val:0x0; + valaddr_reg:x4; val_offset:526*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 526*FLEN/8, x6, x1, x2) + +inst_289: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x22a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x762a; op2val:0x0; + valaddr_reg:x4; val_offset:528*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 528*FLEN/8, x6, x1, x2) + +inst_290: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bea; op2val:0x0; + valaddr_reg:x4; val_offset:530*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 530*FLEN/8, x6, x1, x2) + +inst_291: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bea; op2val:0x0; + valaddr_reg:x4; val_offset:532*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 532*FLEN/8, x6, x1, x2) + +inst_292: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bea; op2val:0x0; + valaddr_reg:x4; val_offset:534*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 534*FLEN/8, x6, x1, x2) + +inst_293: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bea; op2val:0x0; + valaddr_reg:x4; val_offset:536*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 536*FLEN/8, x6, x1, x2) + +inst_294: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bea; op2val:0x0; + valaddr_reg:x4; val_offset:538*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 538*FLEN/8, x6, x1, x2) + +inst_295: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x0a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x68a4; op2val:0x0; + valaddr_reg:x4; val_offset:540*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 540*FLEN/8, x6, x1, x2) + +inst_296: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x0a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x68a4; op2val:0x0; + valaddr_reg:x4; val_offset:542*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 542*FLEN/8, x6, x1, x2) + +inst_297: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x0a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x68a4; op2val:0x0; + valaddr_reg:x4; val_offset:544*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 544*FLEN/8, x6, x1, x2) + +inst_298: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x0a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x68a4; op2val:0x0; + valaddr_reg:x4; val_offset:546*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 546*FLEN/8, x6, x1, x2) + +inst_299: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x0a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x68a4; op2val:0x0; + valaddr_reg:x4; val_offset:548*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 548*FLEN/8, x6, x1, x2) + +inst_300: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0eb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x78eb; op2val:0x0; + valaddr_reg:x4; val_offset:550*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 550*FLEN/8, x6, x1, x2) + +inst_301: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0eb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x78eb; op2val:0x0; + valaddr_reg:x4; val_offset:552*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 552*FLEN/8, x6, x1, x2) + +inst_302: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0eb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x78eb; op2val:0x0; + valaddr_reg:x4; val_offset:554*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 554*FLEN/8, x6, x1, x2) + +inst_303: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0eb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x78eb; op2val:0x0; + valaddr_reg:x4; val_offset:556*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 556*FLEN/8, x6, x1, x2) + +inst_304: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0eb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x78eb; op2val:0x0; + valaddr_reg:x4; val_offset:558*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 558*FLEN/8, x6, x1, x2) + +inst_305: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x33c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f3c; op2val:0x0; + valaddr_reg:x4; val_offset:560*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 560*FLEN/8, x6, x1, x2) + +inst_306: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x33c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f3c; op2val:0x0; + valaddr_reg:x4; val_offset:562*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 562*FLEN/8, x6, x1, x2) + +inst_307: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x33c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f3c; op2val:0x0; + valaddr_reg:x4; val_offset:564*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 564*FLEN/8, x6, x1, x2) + +inst_308: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x33c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f3c; op2val:0x0; + valaddr_reg:x4; val_offset:566*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 566*FLEN/8, x6, x1, x2) + +inst_309: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x33c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f3c; op2val:0x0; + valaddr_reg:x4; val_offset:568*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 568*FLEN/8, x6, x1, x2) + +inst_310: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x3e3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x67e3; op2val:0x0; + valaddr_reg:x4; val_offset:570*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 570*FLEN/8, x6, x1, x2) + +inst_311: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x3e3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x67e3; op2val:0x0; + valaddr_reg:x4; val_offset:572*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 572*FLEN/8, x6, x1, x2) + +inst_312: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x3e3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x67e3; op2val:0x0; + valaddr_reg:x4; val_offset:574*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 574*FLEN/8, x6, x1, x2) + +inst_313: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x3e3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x67e3; op2val:0x0; + valaddr_reg:x4; val_offset:576*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 576*FLEN/8, x6, x1, x2) + +inst_314: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x3e3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x67e3; op2val:0x0; + valaddr_reg:x4; val_offset:578*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 578*FLEN/8, x6, x1, x2) + +inst_315: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a1f; op2val:0x8000; + valaddr_reg:x4; val_offset:580*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 580*FLEN/8, x6, x1, x2) + +inst_316: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a1f; op2val:0x8000; + valaddr_reg:x4; val_offset:582*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 582*FLEN/8, x6, x1, x2) + +inst_317: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a1f; op2val:0x8000; + valaddr_reg:x4; val_offset:584*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 584*FLEN/8, x6, x1, x2) + +inst_318: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a1f; op2val:0x8000; + valaddr_reg:x4; val_offset:586*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 586*FLEN/8, x6, x1, x2) + +inst_319: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a1f; op2val:0x8000; + valaddr_reg:x4; val_offset:588*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 588*FLEN/8, x6, x1, x2) + +inst_320: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x336 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b36; op2val:0x8000; + valaddr_reg:x4; val_offset:590*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 590*FLEN/8, x6, x1, x2) + +inst_321: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x336 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b36; op2val:0x8000; + valaddr_reg:x4; val_offset:592*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 592*FLEN/8, x6, x1, x2) + +inst_322: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x336 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b36; op2val:0x8000; + valaddr_reg:x4; val_offset:594*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 594*FLEN/8, x6, x1, x2) + +inst_323: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x336 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b36; op2val:0x8000; + valaddr_reg:x4; val_offset:596*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 596*FLEN/8, x6, x1, x2) + +inst_324: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x336 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b36; op2val:0x8000; + valaddr_reg:x4; val_offset:598*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 598*FLEN/8, x6, x1, x2) + +inst_325: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ae5; op2val:0x8000; + valaddr_reg:x4; val_offset:600*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 600*FLEN/8, x6, x1, x2) + +inst_326: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ae5; op2val:0x8000; + valaddr_reg:x4; val_offset:602*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 602*FLEN/8, x6, x1, x2) + +inst_327: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ae5; op2val:0x8000; + valaddr_reg:x4; val_offset:604*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 604*FLEN/8, x6, x1, x2) + +inst_328: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ae5; op2val:0x8000; + valaddr_reg:x4; val_offset:606*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 606*FLEN/8, x6, x1, x2) + +inst_329: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ae5; op2val:0x8000; + valaddr_reg:x4; val_offset:608*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 608*FLEN/8, x6, x1, x2) + +inst_330: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x38f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x778f; op2val:0x8000; + valaddr_reg:x4; val_offset:610*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 610*FLEN/8, x6, x1, x2) + +inst_331: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x38f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x778f; op2val:0x8000; + valaddr_reg:x4; val_offset:612*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 612*FLEN/8, x6, x1, x2) + +inst_332: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x38f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x778f; op2val:0x8000; + valaddr_reg:x4; val_offset:614*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 614*FLEN/8, x6, x1, x2) + +inst_333: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x38f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x778f; op2val:0x8000; + valaddr_reg:x4; val_offset:616*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 616*FLEN/8, x6, x1, x2) + +inst_334: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x38f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x778f; op2val:0x8000; + valaddr_reg:x4; val_offset:618*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 618*FLEN/8, x6, x1, x2) + +inst_335: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x148 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7948; op2val:0x8000; + valaddr_reg:x4; val_offset:620*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 620*FLEN/8, x6, x1, x2) + +inst_336: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x148 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7948; op2val:0x8000; + valaddr_reg:x4; val_offset:622*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 622*FLEN/8, x6, x1, x2) + +inst_337: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x148 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7948; op2val:0x8000; + valaddr_reg:x4; val_offset:624*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 624*FLEN/8, x6, x1, x2) + +inst_338: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x148 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7948; op2val:0x8000; + valaddr_reg:x4; val_offset:626*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 626*FLEN/8, x6, x1, x2) + +inst_339: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x148 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7948; op2val:0x8000; + valaddr_reg:x4; val_offset:628*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 628*FLEN/8, x6, x1, x2) + +inst_340: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x287 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e87; op2val:0x8000; + valaddr_reg:x4; val_offset:630*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 630*FLEN/8, x6, x1, x2) + +inst_341: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x287 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e87; op2val:0x8000; + valaddr_reg:x4; val_offset:632*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 632*FLEN/8, x6, x1, x2) + +inst_342: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x287 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e87; op2val:0x8000; + valaddr_reg:x4; val_offset:634*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 634*FLEN/8, x6, x1, x2) + +inst_343: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x287 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e87; op2val:0x8000; + valaddr_reg:x4; val_offset:636*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 636*FLEN/8, x6, x1, x2) + +inst_344: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x287 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e87; op2val:0x8000; + valaddr_reg:x4; val_offset:638*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 638*FLEN/8, x6, x1, x2) + +inst_345: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7afe; op2val:0x8000; + valaddr_reg:x4; val_offset:640*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 640*FLEN/8, x6, x1, x2) + +inst_346: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7afe; op2val:0x8000; + valaddr_reg:x4; val_offset:642*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 642*FLEN/8, x6, x1, x2) + +inst_347: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7afe; op2val:0x8000; + valaddr_reg:x4; val_offset:644*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 644*FLEN/8, x6, x1, x2) + +inst_348: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7afe; op2val:0x8000; + valaddr_reg:x4; val_offset:646*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 646*FLEN/8, x6, x1, x2) + +inst_349: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7afe; op2val:0x8000; + valaddr_reg:x4; val_offset:648*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 648*FLEN/8, x6, x1, x2) + +inst_350: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ad and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x78ad; op2val:0x8000; + valaddr_reg:x4; val_offset:650*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 650*FLEN/8, x6, x1, x2) + +inst_351: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ad and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x78ad; op2val:0x8000; + valaddr_reg:x4; val_offset:652*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 652*FLEN/8, x6, x1, x2) + +inst_352: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ad and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x78ad; op2val:0x8000; + valaddr_reg:x4; val_offset:654*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 654*FLEN/8, x6, x1, x2) + +inst_353: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ad and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x78ad; op2val:0x8000; + valaddr_reg:x4; val_offset:656*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 656*FLEN/8, x6, x1, x2) + +inst_354: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ad and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x78ad; op2val:0x8000; + valaddr_reg:x4; val_offset:658*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 658*FLEN/8, x6, x1, x2) + +inst_355: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x01d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x781d; op2val:0x8000; + valaddr_reg:x4; val_offset:660*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 660*FLEN/8, x6, x1, x2) + +inst_356: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x01d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x781d; op2val:0x8000; + valaddr_reg:x4; val_offset:662*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 662*FLEN/8, x6, x1, x2) + +inst_357: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x01d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x781d; op2val:0x8000; + valaddr_reg:x4; val_offset:664*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 664*FLEN/8, x6, x1, x2) + +inst_358: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x01d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x781d; op2val:0x8000; + valaddr_reg:x4; val_offset:666*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 666*FLEN/8, x6, x1, x2) + +inst_359: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x01d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x781d; op2val:0x8000; + valaddr_reg:x4; val_offset:668*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 668*FLEN/8, x6, x1, x2) + +inst_360: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ac and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bac; op2val:0x8000; + valaddr_reg:x4; val_offset:670*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 670*FLEN/8, x6, x1, x2) + +inst_361: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ac and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bac; op2val:0x8000; + valaddr_reg:x4; val_offset:672*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 672*FLEN/8, x6, x1, x2) + +inst_362: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ac and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bac; op2val:0x8000; + valaddr_reg:x4; val_offset:674*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 674*FLEN/8, x6, x1, x2) + +inst_363: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ac and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bac; op2val:0x8000; + valaddr_reg:x4; val_offset:676*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 676*FLEN/8, x6, x1, x2) + +inst_364: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ac and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bac; op2val:0x8000; + valaddr_reg:x4; val_offset:678*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 678*FLEN/8, x6, x1, x2) + +inst_365: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x78d8; op2val:0x8000; + valaddr_reg:x4; val_offset:680*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 680*FLEN/8, x6, x1, x2) + +inst_366: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x78d8; op2val:0x8000; + valaddr_reg:x4; val_offset:682*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 682*FLEN/8, x6, x1, x2) + +inst_367: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x78d8; op2val:0x8000; + valaddr_reg:x4; val_offset:684*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 684*FLEN/8, x6, x1, x2) + +inst_368: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x78d8; op2val:0x8000; + valaddr_reg:x4; val_offset:686*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 686*FLEN/8, x6, x1, x2) + +inst_369: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x78d8; op2val:0x8000; + valaddr_reg:x4; val_offset:688*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 688*FLEN/8, x6, x1, x2) + +inst_370: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x09e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x649e; op2val:0x8000; + valaddr_reg:x4; val_offset:690*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 690*FLEN/8, x6, x1, x2) + +inst_371: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x09e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x649e; op2val:0x8000; + valaddr_reg:x4; val_offset:692*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 692*FLEN/8, x6, x1, x2) + +inst_372: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x09e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x649e; op2val:0x8000; + valaddr_reg:x4; val_offset:694*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 694*FLEN/8, x6, x1, x2) + +inst_373: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x09e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x649e; op2val:0x8000; + valaddr_reg:x4; val_offset:696*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 696*FLEN/8, x6, x1, x2) + +inst_374: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x09e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x649e; op2val:0x8000; + valaddr_reg:x4; val_offset:698*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 698*FLEN/8, x6, x1, x2) + +inst_375: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x07f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x707f; op2val:0x8000; + valaddr_reg:x4; val_offset:700*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 700*FLEN/8, x6, x1, x2) + +inst_376: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x07f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x707f; op2val:0x8000; + valaddr_reg:x4; val_offset:702*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 702*FLEN/8, x6, x1, x2) + +inst_377: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x07f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x707f; op2val:0x8000; + valaddr_reg:x4; val_offset:704*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 704*FLEN/8, x6, x1, x2) + +inst_378: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x07f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x707f; op2val:0x8000; + valaddr_reg:x4; val_offset:706*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 706*FLEN/8, x6, x1, x2) + +inst_379: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x07f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x707f; op2val:0x8000; + valaddr_reg:x4; val_offset:708*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 708*FLEN/8, x6, x1, x2) + +inst_380: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x04b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x684b; op2val:0x8000; + valaddr_reg:x4; val_offset:710*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 710*FLEN/8, x6, x1, x2) + +inst_381: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x04b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x684b; op2val:0x8000; + valaddr_reg:x4; val_offset:712*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 712*FLEN/8, x6, x1, x2) + +inst_382: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x04b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x684b; op2val:0x8000; + valaddr_reg:x4; val_offset:714*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 714*FLEN/8, x6, x1, x2) + +inst_383: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x04b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x684b; op2val:0x8000; + valaddr_reg:x4; val_offset:716*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 716*FLEN/8, x6, x1, x2) + +inst_384: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x04b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x684b; op2val:0x8000; + valaddr_reg:x4; val_offset:718*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 718*FLEN/8, x6, x1, x2) + +inst_385: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x222 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e22; op2val:0x0; + valaddr_reg:x4; val_offset:720*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 720*FLEN/8, x6, x1, x2) + +inst_386: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x222 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e22; op2val:0x0; + valaddr_reg:x4; val_offset:722*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 722*FLEN/8, x6, x1, x2) + +inst_387: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x222 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e22; op2val:0x0; + valaddr_reg:x4; val_offset:724*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 724*FLEN/8, x6, x1, x2) + +inst_388: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x222 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e22; op2val:0x0; + valaddr_reg:x4; val_offset:726*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 726*FLEN/8, x6, x1, x2) + +inst_389: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x222 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e22; op2val:0x0; + valaddr_reg:x4; val_offset:728*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 728*FLEN/8, x6, x1, x2) + +inst_390: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x010 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7810; op2val:0x0; + valaddr_reg:x4; val_offset:730*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 730*FLEN/8, x6, x1, x2) + +inst_391: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x010 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7810; op2val:0x0; + valaddr_reg:x4; val_offset:732*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 732*FLEN/8, x6, x1, x2) + +inst_392: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x010 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7810; op2val:0x0; + valaddr_reg:x4; val_offset:734*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 734*FLEN/8, x6, x1, x2) + +inst_393: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x010 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7810; op2val:0x0; + valaddr_reg:x4; val_offset:736*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 736*FLEN/8, x6, x1, x2) + +inst_394: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x010 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7810; op2val:0x0; + valaddr_reg:x4; val_offset:738*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 738*FLEN/8, x6, x1, x2) + +inst_395: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x378 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b78; op2val:0x0; + valaddr_reg:x4; val_offset:740*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 740*FLEN/8, x6, x1, x2) + +inst_396: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x378 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b78; op2val:0x0; + valaddr_reg:x4; val_offset:742*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 742*FLEN/8, x6, x1, x2) + +inst_397: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x378 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b78; op2val:0x0; + valaddr_reg:x4; val_offset:744*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 744*FLEN/8, x6, x1, x2) + +inst_398: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x378 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b78; op2val:0x0; + valaddr_reg:x4; val_offset:746*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 746*FLEN/8, x6, x1, x2) + +inst_399: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x378 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b78; op2val:0x0; + valaddr_reg:x4; val_offset:748*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 748*FLEN/8, x6, x1, x2) + +inst_400: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x36f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x736f; op2val:0x0; + valaddr_reg:x4; val_offset:750*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 750*FLEN/8, x6, x1, x2) + +inst_401: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x36f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x736f; op2val:0x0; + valaddr_reg:x4; val_offset:752*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 752*FLEN/8, x6, x1, x2) + +inst_402: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x36f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x736f; op2val:0x0; + valaddr_reg:x4; val_offset:754*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 754*FLEN/8, x6, x1, x2) + +inst_403: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x36f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x736f; op2val:0x0; + valaddr_reg:x4; val_offset:756*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 756*FLEN/8, x6, x1, x2) + +inst_404: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x36f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x736f; op2val:0x0; + valaddr_reg:x4; val_offset:758*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 758*FLEN/8, x6, x1, x2) + +inst_405: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7402; op2val:0x0; + valaddr_reg:x4; val_offset:760*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 760*FLEN/8, x6, x1, x2) + +inst_406: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7402; op2val:0x0; + valaddr_reg:x4; val_offset:762*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 762*FLEN/8, x6, x1, x2) + +inst_407: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7402; op2val:0x0; + valaddr_reg:x4; val_offset:764*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 764*FLEN/8, x6, x1, x2) + +inst_408: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7402; op2val:0x0; + valaddr_reg:x4; val_offset:766*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 766*FLEN/8, x6, x1, x2) + +inst_409: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7402; op2val:0x0; + valaddr_reg:x4; val_offset:768*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 768*FLEN/8, x6, x1, x2) + +inst_410: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x78fd; op2val:0x0; + valaddr_reg:x4; val_offset:770*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 770*FLEN/8, x6, x1, x2) + +inst_411: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x78fd; op2val:0x0; + valaddr_reg:x4; val_offset:772*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 772*FLEN/8, x6, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_3) + +inst_412: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x78fd; op2val:0x0; + valaddr_reg:x4; val_offset:774*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 774*FLEN/8, x6, x1, x2) + +inst_413: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x78fd; op2val:0x0; + valaddr_reg:x4; val_offset:776*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 776*FLEN/8, x6, x1, x2) + +inst_414: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x78fd; op2val:0x0; + valaddr_reg:x4; val_offset:778*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 778*FLEN/8, x6, x1, x2) + +inst_415: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ac and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79ac; op2val:0x0; + valaddr_reg:x4; val_offset:780*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 780*FLEN/8, x6, x1, x2) + +inst_416: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ac and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79ac; op2val:0x0; + valaddr_reg:x4; val_offset:782*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 782*FLEN/8, x6, x1, x2) + +inst_417: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ac and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79ac; op2val:0x0; + valaddr_reg:x4; val_offset:784*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 784*FLEN/8, x6, x1, x2) + +inst_418: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ac and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79ac; op2val:0x0; + valaddr_reg:x4; val_offset:786*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 786*FLEN/8, x6, x1, x2) + +inst_419: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ac and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79ac; op2val:0x0; + valaddr_reg:x4; val_offset:788*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 788*FLEN/8, x6, x1, x2) + +inst_420: +// fs1 == 0 and fe1 == 0x17 and fm1 == 0x0f4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x5cf4; op2val:0x3; + valaddr_reg:x4; val_offset:790*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 790*FLEN/8, x6, x1, x2) + +inst_421: +// fs1 == 0 and fe1 == 0x17 and fm1 == 0x0f4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x003 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x5cf4; op2val:0x3; + valaddr_reg:x4; val_offset:792*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 792*FLEN/8, x6, x1, x2) + +inst_422: +// fs1 == 0 and fe1 == 0x17 and fm1 == 0x0f4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x003 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x5cf4; op2val:0x3; + valaddr_reg:x4; val_offset:794*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 794*FLEN/8, x6, x1, x2) + +inst_423: +// fs1 == 0 and fe1 == 0x17 and fm1 == 0x0f4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x003 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x5cf4; op2val:0x3; + valaddr_reg:x4; val_offset:796*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 796*FLEN/8, x6, x1, x2) + +inst_424: +// fs1 == 0 and fe1 == 0x17 and fm1 == 0x0f4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x003 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x5cf4; op2val:0x3; + valaddr_reg:x4; val_offset:798*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 798*FLEN/8, x6, x1, x2) + +inst_425: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x289 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7689; op2val:0x0; + valaddr_reg:x4; val_offset:800*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 800*FLEN/8, x6, x1, x2) + +inst_426: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x289 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7689; op2val:0x0; + valaddr_reg:x4; val_offset:802*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 802*FLEN/8, x6, x1, x2) + +inst_427: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x289 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7689; op2val:0x0; + valaddr_reg:x4; val_offset:804*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 804*FLEN/8, x6, x1, x2) + +inst_428: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x289 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7689; op2val:0x0; + valaddr_reg:x4; val_offset:806*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 806*FLEN/8, x6, x1, x2) + +inst_429: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x289 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7689; op2val:0x0; + valaddr_reg:x4; val_offset:808*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 808*FLEN/8, x6, x1, x2) + +inst_430: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x262 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e62; op2val:0x0; + valaddr_reg:x4; val_offset:810*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 810*FLEN/8, x6, x1, x2) + +inst_431: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x262 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e62; op2val:0x0; + valaddr_reg:x4; val_offset:812*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 812*FLEN/8, x6, x1, x2) + +inst_432: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x262 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e62; op2val:0x0; + valaddr_reg:x4; val_offset:814*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 814*FLEN/8, x6, x1, x2) + +inst_433: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x262 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e62; op2val:0x0; + valaddr_reg:x4; val_offset:816*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 816*FLEN/8, x6, x1, x2) + +inst_434: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x262 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e62; op2val:0x0; + valaddr_reg:x4; val_offset:818*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 818*FLEN/8, x6, x1, x2) + +inst_435: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x367 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7367; op2val:0x0; + valaddr_reg:x4; val_offset:820*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 820*FLEN/8, x6, x1, x2) + +inst_436: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x367 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7367; op2val:0x0; + valaddr_reg:x4; val_offset:822*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 822*FLEN/8, x6, x1, x2) + +inst_437: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x367 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7367; op2val:0x0; + valaddr_reg:x4; val_offset:824*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 824*FLEN/8, x6, x1, x2) + +inst_438: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x367 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7367; op2val:0x0; + valaddr_reg:x4; val_offset:826*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 826*FLEN/8, x6, x1, x2) + +inst_439: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x367 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7367; op2val:0x0; + valaddr_reg:x4; val_offset:828*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 828*FLEN/8, x6, x1, x2) + +inst_440: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7829; op2val:0x0; + valaddr_reg:x4; val_offset:830*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 830*FLEN/8, x6, x1, x2) + +inst_441: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7829; op2val:0x0; + valaddr_reg:x4; val_offset:832*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 832*FLEN/8, x6, x1, x2) + +inst_442: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7829; op2val:0x0; + valaddr_reg:x4; val_offset:834*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 834*FLEN/8, x6, x1, x2) + +inst_443: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7829; op2val:0x0; + valaddr_reg:x4; val_offset:836*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 836*FLEN/8, x6, x1, x2) + +inst_444: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7829; op2val:0x0; + valaddr_reg:x4; val_offset:838*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 838*FLEN/8, x6, x1, x2) + +inst_445: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x74f4; op2val:0x8000; + valaddr_reg:x4; val_offset:840*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 840*FLEN/8, x6, x1, x2) + +inst_446: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x74f4; op2val:0x8000; + valaddr_reg:x4; val_offset:842*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 842*FLEN/8, x6, x1, x2) + +inst_447: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x74f4; op2val:0x8000; + valaddr_reg:x4; val_offset:844*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 844*FLEN/8, x6, x1, x2) + +inst_448: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x74f4; op2val:0x8000; + valaddr_reg:x4; val_offset:846*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 846*FLEN/8, x6, x1, x2) + +inst_449: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x74f4; op2val:0x8000; + valaddr_reg:x4; val_offset:848*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 848*FLEN/8, x6, x1, x2) + +inst_450: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2cb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x72cb; op2val:0x8000; + valaddr_reg:x4; val_offset:850*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 850*FLEN/8, x6, x1, x2) + +inst_451: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2cb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x72cb; op2val:0x8000; + valaddr_reg:x4; val_offset:852*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 852*FLEN/8, x6, x1, x2) + +inst_452: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2cb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x72cb; op2val:0x8000; + valaddr_reg:x4; val_offset:854*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 854*FLEN/8, x6, x1, x2) + +inst_453: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2cb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x72cb; op2val:0x8000; + valaddr_reg:x4; val_offset:856*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 856*FLEN/8, x6, x1, x2) + +inst_454: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2cb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x72cb; op2val:0x8000; + valaddr_reg:x4; val_offset:858*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 858*FLEN/8, x6, x1, x2) + +inst_455: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb3; op2val:0x8000; + valaddr_reg:x4; val_offset:860*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 860*FLEN/8, x6, x1, x2) + +inst_456: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb3; op2val:0x8000; + valaddr_reg:x4; val_offset:862*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 862*FLEN/8, x6, x1, x2) + +inst_457: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb3; op2val:0x8000; + valaddr_reg:x4; val_offset:864*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 864*FLEN/8, x6, x1, x2) + +inst_458: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb3; op2val:0x8000; + valaddr_reg:x4; val_offset:866*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 866*FLEN/8, x6, x1, x2) + +inst_459: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb3; op2val:0x8000; + valaddr_reg:x4; val_offset:868*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 868*FLEN/8, x6, x1, x2) + +inst_460: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x76ef; op2val:0x8000; + valaddr_reg:x4; val_offset:870*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 870*FLEN/8, x6, x1, x2) + +inst_461: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x76ef; op2val:0x8000; + valaddr_reg:x4; val_offset:872*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 872*FLEN/8, x6, x1, x2) + +inst_462: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x76ef; op2val:0x8000; + valaddr_reg:x4; val_offset:874*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 874*FLEN/8, x6, x1, x2) + +inst_463: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x76ef; op2val:0x8000; + valaddr_reg:x4; val_offset:876*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 876*FLEN/8, x6, x1, x2) + +inst_464: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x76ef; op2val:0x8000; + valaddr_reg:x4; val_offset:878*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 878*FLEN/8, x6, x1, x2) + +inst_465: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x78a5; op2val:0x8000; + valaddr_reg:x4; val_offset:880*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 880*FLEN/8, x6, x1, x2) + +inst_466: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x78a5; op2val:0x8000; + valaddr_reg:x4; val_offset:882*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 882*FLEN/8, x6, x1, x2) + +inst_467: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x78a5; op2val:0x8000; + valaddr_reg:x4; val_offset:884*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 884*FLEN/8, x6, x1, x2) + +inst_468: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x78a5; op2val:0x8000; + valaddr_reg:x4; val_offset:886*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 886*FLEN/8, x6, x1, x2) + +inst_469: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x78a5; op2val:0x8000; + valaddr_reg:x4; val_offset:888*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 888*FLEN/8, x6, x1, x2) + +inst_470: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2af and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x76af; op2val:0x8000; + valaddr_reg:x4; val_offset:890*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 890*FLEN/8, x6, x1, x2) + +inst_471: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2af and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x76af; op2val:0x8000; + valaddr_reg:x4; val_offset:892*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 892*FLEN/8, x6, x1, x2) + +inst_472: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2af and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x76af; op2val:0x8000; + valaddr_reg:x4; val_offset:894*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 894*FLEN/8, x6, x1, x2) + +inst_473: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2af and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x76af; op2val:0x8000; + valaddr_reg:x4; val_offset:896*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 896*FLEN/8, x6, x1, x2) + +inst_474: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2af and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x76af; op2val:0x8000; + valaddr_reg:x4; val_offset:898*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 898*FLEN/8, x6, x1, x2) + +inst_475: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1cb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x71cb; op2val:0x8000; + valaddr_reg:x4; val_offset:900*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 900*FLEN/8, x6, x1, x2) + +inst_476: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1cb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x71cb; op2val:0x8000; + valaddr_reg:x4; val_offset:902*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 902*FLEN/8, x6, x1, x2) + +inst_477: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1cb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x71cb; op2val:0x8000; + valaddr_reg:x4; val_offset:904*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 904*FLEN/8, x6, x1, x2) + +inst_478: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1cb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x71cb; op2val:0x8000; + valaddr_reg:x4; val_offset:906*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 906*FLEN/8, x6, x1, x2) + +inst_479: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1cb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x71cb; op2val:0x8000; + valaddr_reg:x4; val_offset:908*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 908*FLEN/8, x6, x1, x2) + +inst_480: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a6b; op2val:0x8000; + valaddr_reg:x4; val_offset:910*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 910*FLEN/8, x6, x1, x2) + +inst_481: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a6b; op2val:0x8000; + valaddr_reg:x4; val_offset:912*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 912*FLEN/8, x6, x1, x2) + +inst_482: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a6b; op2val:0x8000; + valaddr_reg:x4; val_offset:914*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 914*FLEN/8, x6, x1, x2) + +inst_483: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a6b; op2val:0x8000; + valaddr_reg:x4; val_offset:916*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 916*FLEN/8, x6, x1, x2) + +inst_484: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a6b; op2val:0x8000; + valaddr_reg:x4; val_offset:918*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 918*FLEN/8, x6, x1, x2) + +inst_485: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x026 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7826; op2val:0x8000; + valaddr_reg:x4; val_offset:920*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 920*FLEN/8, x6, x1, x2) + +inst_486: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x026 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7826; op2val:0x8000; + valaddr_reg:x4; val_offset:922*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 922*FLEN/8, x6, x1, x2) + +inst_487: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x026 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7826; op2val:0x8000; + valaddr_reg:x4; val_offset:924*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 924*FLEN/8, x6, x1, x2) + +inst_488: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x026 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7826; op2val:0x8000; + valaddr_reg:x4; val_offset:926*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 926*FLEN/8, x6, x1, x2) + +inst_489: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x026 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7826; op2val:0x8000; + valaddr_reg:x4; val_offset:928*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 928*FLEN/8, x6, x1, x2) + +inst_490: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x78e1; op2val:0x8000; + valaddr_reg:x4; val_offset:930*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 930*FLEN/8, x6, x1, x2) + +inst_491: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x78e1; op2val:0x8000; + valaddr_reg:x4; val_offset:932*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 932*FLEN/8, x6, x1, x2) + +inst_492: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x78e1; op2val:0x8000; + valaddr_reg:x4; val_offset:934*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 934*FLEN/8, x6, x1, x2) + +inst_493: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x78e1; op2val:0x8000; + valaddr_reg:x4; val_offset:936*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 936*FLEN/8, x6, x1, x2) + +inst_494: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x78e1; op2val:0x8000; + valaddr_reg:x4; val_offset:938*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 938*FLEN/8, x6, x1, x2) + +inst_495: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3dd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bdd; op2val:0x8000; + valaddr_reg:x4; val_offset:940*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 940*FLEN/8, x6, x1, x2) + +inst_496: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3dd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bdd; op2val:0x8000; + valaddr_reg:x4; val_offset:942*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 942*FLEN/8, x6, x1, x2) + +inst_497: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3dd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bdd; op2val:0x8000; + valaddr_reg:x4; val_offset:944*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 944*FLEN/8, x6, x1, x2) + +inst_498: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3dd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bdd; op2val:0x8000; + valaddr_reg:x4; val_offset:946*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 946*FLEN/8, x6, x1, x2) + +inst_499: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3dd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bdd; op2val:0x8000; + valaddr_reg:x4; val_offset:948*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 948*FLEN/8, x6, x1, x2) + +inst_500: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x0e1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x64e1; op2val:0x8000; + valaddr_reg:x4; val_offset:950*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 950*FLEN/8, x6, x1, x2) + +inst_501: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x0e1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x64e1; op2val:0x8000; + valaddr_reg:x4; val_offset:952*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 952*FLEN/8, x6, x1, x2) + +inst_502: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x0e1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x64e1; op2val:0x8000; + valaddr_reg:x4; val_offset:954*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 954*FLEN/8, x6, x1, x2) + +inst_503: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x0e1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x64e1; op2val:0x8000; + valaddr_reg:x4; val_offset:956*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 956*FLEN/8, x6, x1, x2) + +inst_504: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x0e1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x64e1; op2val:0x8000; + valaddr_reg:x4; val_offset:958*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 958*FLEN/8, x6, x1, x2) + +inst_505: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x278 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e78; op2val:0x8000; + valaddr_reg:x4; val_offset:960*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 960*FLEN/8, x6, x1, x2) + +inst_506: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x278 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e78; op2val:0x8000; + valaddr_reg:x4; val_offset:962*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 962*FLEN/8, x6, x1, x2) + +inst_507: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x278 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e78; op2val:0x8000; + valaddr_reg:x4; val_offset:964*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 964*FLEN/8, x6, x1, x2) + +inst_508: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x278 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e78; op2val:0x8000; + valaddr_reg:x4; val_offset:966*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 966*FLEN/8, x6, x1, x2) + +inst_509: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x278 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e78; op2val:0x8000; + valaddr_reg:x4; val_offset:968*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 968*FLEN/8, x6, x1, x2) + +inst_510: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab8; op2val:0x8000; + valaddr_reg:x4; val_offset:970*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 970*FLEN/8, x6, x1, x2) + +inst_511: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab8; op2val:0x8000; + valaddr_reg:x4; val_offset:972*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 972*FLEN/8, x6, x1, x2) + +inst_512: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab8; op2val:0x8000; + valaddr_reg:x4; val_offset:974*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 974*FLEN/8, x6, x1, x2) + +inst_513: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab8; op2val:0x8000; + valaddr_reg:x4; val_offset:976*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 976*FLEN/8, x6, x1, x2) + +inst_514: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab8; op2val:0x8000; + valaddr_reg:x4; val_offset:978*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 978*FLEN/8, x6, x1, x2) + +inst_515: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x006 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6406; op2val:0x0; + valaddr_reg:x4; val_offset:980*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 980*FLEN/8, x6, x1, x2) + +inst_516: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x006 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6406; op2val:0x0; + valaddr_reg:x4; val_offset:982*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 982*FLEN/8, x6, x1, x2) + +inst_517: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x006 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6406; op2val:0x0; + valaddr_reg:x4; val_offset:984*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 984*FLEN/8, x6, x1, x2) + +inst_518: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x006 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6406; op2val:0x0; + valaddr_reg:x4; val_offset:986*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 986*FLEN/8, x6, x1, x2) + +inst_519: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x006 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6406; op2val:0x0; + valaddr_reg:x4; val_offset:988*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 988*FLEN/8, x6, x1, x2) + +inst_520: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x291 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7691; op2val:0x0; + valaddr_reg:x4; val_offset:990*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 990*FLEN/8, x6, x1, x2) + +inst_521: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x291 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7691; op2val:0x0; + valaddr_reg:x4; val_offset:992*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 992*FLEN/8, x6, x1, x2) + +inst_522: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x291 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7691; op2val:0x0; + valaddr_reg:x4; val_offset:994*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 994*FLEN/8, x6, x1, x2) + +inst_523: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x291 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7691; op2val:0x0; + valaddr_reg:x4; val_offset:996*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 996*FLEN/8, x6, x1, x2) + +inst_524: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x291 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7691; op2val:0x0; + valaddr_reg:x4; val_offset:998*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 998*FLEN/8, x6, x1, x2) + +inst_525: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x72a9; op2val:0x0; + valaddr_reg:x4; val_offset:1000*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1000*FLEN/8, x6, x1, x2) + +inst_526: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x72a9; op2val:0x0; + valaddr_reg:x4; val_offset:1002*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1002*FLEN/8, x6, x1, x2) + +inst_527: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x72a9; op2val:0x0; + valaddr_reg:x4; val_offset:1004*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1004*FLEN/8, x6, x1, x2) + +inst_528: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x72a9; op2val:0x0; + valaddr_reg:x4; val_offset:1006*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1006*FLEN/8, x6, x1, x2) + +inst_529: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x72a9; op2val:0x0; + valaddr_reg:x4; val_offset:1008*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1008*FLEN/8, x6, x1, x2) + +inst_530: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0b8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6cb8; op2val:0x0; + valaddr_reg:x4; val_offset:1010*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1010*FLEN/8, x6, x1, x2) + +inst_531: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0b8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6cb8; op2val:0x0; + valaddr_reg:x4; val_offset:1012*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1012*FLEN/8, x6, x1, x2) + +inst_532: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0b8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6cb8; op2val:0x0; + valaddr_reg:x4; val_offset:1014*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1014*FLEN/8, x6, x1, x2) + +inst_533: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0b8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6cb8; op2val:0x0; + valaddr_reg:x4; val_offset:1016*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1016*FLEN/8, x6, x1, x2) + +inst_534: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0b8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6cb8; op2val:0x0; + valaddr_reg:x4; val_offset:1018*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1018*FLEN/8, x6, x1, x2) + +inst_535: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1f6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x75f6; op2val:0x0; + valaddr_reg:x4; val_offset:1020*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1020*FLEN/8, x6, x1, x2) + +inst_536: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1f6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x75f6; op2val:0x0; + valaddr_reg:x4; val_offset:1022*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1022*FLEN/8, x6, x1, x2) + +inst_537: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1f6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x75f6; op2val:0x0; + valaddr_reg:x4; val_offset:1024*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1024*FLEN/8, x6, x1, x2) + +inst_538: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1f6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x75f6; op2val:0x0; + valaddr_reg:x4; val_offset:1026*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1026*FLEN/8, x6, x1, x2) + +inst_539: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1f6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x75f6; op2val:0x0; + valaddr_reg:x4; val_offset:1028*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1028*FLEN/8, x6, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_4) + +inst_540: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0e5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ce5; op2val:0x0; + valaddr_reg:x4; val_offset:1030*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1030*FLEN/8, x6, x1, x2) + +inst_541: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0e5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ce5; op2val:0x0; + valaddr_reg:x4; val_offset:1032*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1032*FLEN/8, x6, x1, x2) + +inst_542: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0e5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ce5; op2val:0x0; + valaddr_reg:x4; val_offset:1034*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1034*FLEN/8, x6, x1, x2) + +inst_543: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0e5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ce5; op2val:0x0; + valaddr_reg:x4; val_offset:1036*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1036*FLEN/8, x6, x1, x2) + +inst_544: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0e5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ce5; op2val:0x0; + valaddr_reg:x4; val_offset:1038*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1038*FLEN/8, x6, x1, x2) + +inst_545: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x227 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7227; op2val:0x0; + valaddr_reg:x4; val_offset:1040*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1040*FLEN/8, x6, x1, x2) + +inst_546: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x227 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7227; op2val:0x0; + valaddr_reg:x4; val_offset:1042*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1042*FLEN/8, x6, x1, x2) + +inst_547: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x227 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7227; op2val:0x0; + valaddr_reg:x4; val_offset:1044*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1044*FLEN/8, x6, x1, x2) + +inst_548: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x227 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7227; op2val:0x0; + valaddr_reg:x4; val_offset:1046*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1046*FLEN/8, x6, x1, x2) + +inst_549: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x227 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7227; op2val:0x0; + valaddr_reg:x4; val_offset:1048*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1048*FLEN/8, x6, x1, x2) + +inst_550: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x243 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7643; op2val:0x0; + valaddr_reg:x4; val_offset:1050*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1050*FLEN/8, x6, x1, x2) + +inst_551: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x243 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7643; op2val:0x0; + valaddr_reg:x4; val_offset:1052*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1052*FLEN/8, x6, x1, x2) + +inst_552: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x243 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7643; op2val:0x0; + valaddr_reg:x4; val_offset:1054*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1054*FLEN/8, x6, x1, x2) + +inst_553: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x243 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7643; op2val:0x0; + valaddr_reg:x4; val_offset:1056*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1056*FLEN/8, x6, x1, x2) + +inst_554: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x243 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7643; op2val:0x0; + valaddr_reg:x4; val_offset:1058*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1058*FLEN/8, x6, x1, x2) + +inst_555: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x206 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a06; op2val:0x0; + valaddr_reg:x4; val_offset:1060*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1060*FLEN/8, x6, x1, x2) + +inst_556: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x206 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a06; op2val:0x0; + valaddr_reg:x4; val_offset:1062*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1062*FLEN/8, x6, x1, x2) + +inst_557: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x206 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a06; op2val:0x0; + valaddr_reg:x4; val_offset:1064*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1064*FLEN/8, x6, x1, x2) + +inst_558: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x206 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a06; op2val:0x0; + valaddr_reg:x4; val_offset:1066*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1066*FLEN/8, x6, x1, x2) + +inst_559: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x206 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a06; op2val:0x0; + valaddr_reg:x4; val_offset:1068*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1068*FLEN/8, x6, x1, x2) + +inst_560: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3c9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6fc9; op2val:0x0; + valaddr_reg:x4; val_offset:1070*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1070*FLEN/8, x6, x1, x2) + +inst_561: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3c9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6fc9; op2val:0x0; + valaddr_reg:x4; val_offset:1072*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1072*FLEN/8, x6, x1, x2) + +inst_562: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3c9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6fc9; op2val:0x0; + valaddr_reg:x4; val_offset:1074*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1074*FLEN/8, x6, x1, x2) + +inst_563: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3c9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6fc9; op2val:0x0; + valaddr_reg:x4; val_offset:1076*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1076*FLEN/8, x6, x1, x2) + +inst_564: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3c9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6fc9; op2val:0x0; + valaddr_reg:x4; val_offset:1078*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1078*FLEN/8, x6, x1, x2) + +inst_565: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x126 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d26; op2val:0x0; + valaddr_reg:x4; val_offset:1080*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1080*FLEN/8, x6, x1, x2) + +inst_566: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x126 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d26; op2val:0x0; + valaddr_reg:x4; val_offset:1082*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1082*FLEN/8, x6, x1, x2) + +inst_567: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x126 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d26; op2val:0x0; + valaddr_reg:x4; val_offset:1084*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1084*FLEN/8, x6, x1, x2) + +inst_568: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x126 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d26; op2val:0x0; + valaddr_reg:x4; val_offset:1086*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1086*FLEN/8, x6, x1, x2) + +inst_569: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x126 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d26; op2val:0x0; + valaddr_reg:x4; val_offset:1088*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1088*FLEN/8, x6, x1, x2) + +inst_570: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x120 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7920; op2val:0x0; + valaddr_reg:x4; val_offset:1090*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1090*FLEN/8, x6, x1, x2) + +inst_571: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x120 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7920; op2val:0x0; + valaddr_reg:x4; val_offset:1092*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1092*FLEN/8, x6, x1, x2) + +inst_572: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x120 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7920; op2val:0x0; + valaddr_reg:x4; val_offset:1094*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1094*FLEN/8, x6, x1, x2) + +inst_573: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x120 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7920; op2val:0x0; + valaddr_reg:x4; val_offset:1096*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1096*FLEN/8, x6, x1, x2) + +inst_574: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x120 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7920; op2val:0x0; + valaddr_reg:x4; val_offset:1098*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1098*FLEN/8, x6, x1, x2) + +inst_575: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x189 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7989; op2val:0x0; + valaddr_reg:x4; val_offset:1100*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1100*FLEN/8, x6, x1, x2) + +inst_576: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x189 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7989; op2val:0x0; + valaddr_reg:x4; val_offset:1102*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1102*FLEN/8, x6, x1, x2) + +inst_577: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x189 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7989; op2val:0x0; + valaddr_reg:x4; val_offset:1104*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1104*FLEN/8, x6, x1, x2) + +inst_578: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x189 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7989; op2val:0x0; + valaddr_reg:x4; val_offset:1106*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1106*FLEN/8, x6, x1, x2) + +inst_579: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x189 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7989; op2val:0x0; + valaddr_reg:x4; val_offset:1108*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1108*FLEN/8, x6, x1, x2) + +inst_580: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x145 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7945; op2val:0x0; + valaddr_reg:x4; val_offset:1110*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1110*FLEN/8, x6, x1, x2) + +inst_581: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x145 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7945; op2val:0x0; + valaddr_reg:x4; val_offset:1112*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1112*FLEN/8, x6, x1, x2) + +inst_582: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x145 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7945; op2val:0x0; + valaddr_reg:x4; val_offset:1114*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1114*FLEN/8, x6, x1, x2) + +inst_583: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x145 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7945; op2val:0x0; + valaddr_reg:x4; val_offset:1116*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1116*FLEN/8, x6, x1, x2) + +inst_584: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x145 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7945; op2val:0x0; + valaddr_reg:x4; val_offset:1118*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1118*FLEN/8, x6, x1, x2) + +inst_585: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c9; op2val:0x8000; + valaddr_reg:x4; val_offset:1120*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1120*FLEN/8, x6, x1, x2) + +inst_586: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c9; op2val:0x8000; + valaddr_reg:x4; val_offset:1122*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1122*FLEN/8, x6, x1, x2) + +inst_587: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c9; op2val:0x8000; + valaddr_reg:x4; val_offset:1124*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1124*FLEN/8, x6, x1, x2) + +inst_588: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c9; op2val:0x8000; + valaddr_reg:x4; val_offset:1126*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1126*FLEN/8, x6, x1, x2) + +inst_589: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c9; op2val:0x8000; + valaddr_reg:x4; val_offset:1128*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1128*FLEN/8, x6, x1, x2) + +inst_590: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1b7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x75b7; op2val:0x8000; + valaddr_reg:x4; val_offset:1130*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1130*FLEN/8, x6, x1, x2) + +inst_591: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1b7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x75b7; op2val:0x8000; + valaddr_reg:x4; val_offset:1132*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1132*FLEN/8, x6, x1, x2) + +inst_592: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1b7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x75b7; op2val:0x8000; + valaddr_reg:x4; val_offset:1134*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1134*FLEN/8, x6, x1, x2) + +inst_593: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1b7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x75b7; op2val:0x8000; + valaddr_reg:x4; val_offset:1136*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1136*FLEN/8, x6, x1, x2) + +inst_594: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1b7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x75b7; op2val:0x8000; + valaddr_reg:x4; val_offset:1138*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1138*FLEN/8, x6, x1, x2) + +inst_595: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x262 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a62; op2val:0x8000; + valaddr_reg:x4; val_offset:1140*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1140*FLEN/8, x6, x1, x2) + +inst_596: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x262 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a62; op2val:0x8000; + valaddr_reg:x4; val_offset:1142*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1142*FLEN/8, x6, x1, x2) + +inst_597: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x262 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a62; op2val:0x8000; + valaddr_reg:x4; val_offset:1144*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1144*FLEN/8, x6, x1, x2) + +inst_598: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x262 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a62; op2val:0x8000; + valaddr_reg:x4; val_offset:1146*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1146*FLEN/8, x6, x1, x2) + +inst_599: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x262 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a62; op2val:0x8000; + valaddr_reg:x4; val_offset:1148*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1148*FLEN/8, x6, x1, x2) + +inst_600: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x035 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7835; op2val:0x8000; + valaddr_reg:x4; val_offset:1150*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1150*FLEN/8, x6, x1, x2) + +inst_601: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x035 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7835; op2val:0x8000; + valaddr_reg:x4; val_offset:1152*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1152*FLEN/8, x6, x1, x2) + +inst_602: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x035 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7835; op2val:0x8000; + valaddr_reg:x4; val_offset:1154*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1154*FLEN/8, x6, x1, x2) + +inst_603: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x035 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7835; op2val:0x8000; + valaddr_reg:x4; val_offset:1156*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1156*FLEN/8, x6, x1, x2) + +inst_604: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x035 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7835; op2val:0x8000; + valaddr_reg:x4; val_offset:1158*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1158*FLEN/8, x6, x1, x2) + +inst_605: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba2; op2val:0x8000; + valaddr_reg:x4; val_offset:1160*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1160*FLEN/8, x6, x1, x2) + +inst_606: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba2; op2val:0x8000; + valaddr_reg:x4; val_offset:1162*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1162*FLEN/8, x6, x1, x2) + +inst_607: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba2; op2val:0x8000; + valaddr_reg:x4; val_offset:1164*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1164*FLEN/8, x6, x1, x2) + +inst_608: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba2; op2val:0x8000; + valaddr_reg:x4; val_offset:1166*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1166*FLEN/8, x6, x1, x2) + +inst_609: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba2; op2val:0x8000; + valaddr_reg:x4; val_offset:1168*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1168*FLEN/8, x6, x1, x2) + +inst_610: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x373 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b73; op2val:0x8000; + valaddr_reg:x4; val_offset:1170*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1170*FLEN/8, x6, x1, x2) + +inst_611: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x373 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b73; op2val:0x8000; + valaddr_reg:x4; val_offset:1172*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1172*FLEN/8, x6, x1, x2) + +inst_612: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x373 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b73; op2val:0x8000; + valaddr_reg:x4; val_offset:1174*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1174*FLEN/8, x6, x1, x2) + +inst_613: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x373 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b73; op2val:0x8000; + valaddr_reg:x4; val_offset:1176*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1176*FLEN/8, x6, x1, x2) + +inst_614: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x373 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b73; op2val:0x8000; + valaddr_reg:x4; val_offset:1178*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1178*FLEN/8, x6, x1, x2) + +inst_615: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0be and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x74be; op2val:0x8000; + valaddr_reg:x4; val_offset:1180*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1180*FLEN/8, x6, x1, x2) + +inst_616: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0be and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x74be; op2val:0x8000; + valaddr_reg:x4; val_offset:1182*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1182*FLEN/8, x6, x1, x2) + +inst_617: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0be and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x74be; op2val:0x8000; + valaddr_reg:x4; val_offset:1184*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1184*FLEN/8, x6, x1, x2) + +inst_618: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0be and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x74be; op2val:0x8000; + valaddr_reg:x4; val_offset:1186*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1186*FLEN/8, x6, x1, x2) + +inst_619: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0be and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x74be; op2val:0x8000; + valaddr_reg:x4; val_offset:1188*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1188*FLEN/8, x6, x1, x2) + +inst_620: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x77d1; op2val:0x8000; + valaddr_reg:x4; val_offset:1190*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1190*FLEN/8, x6, x1, x2) + +inst_621: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x77d1; op2val:0x8000; + valaddr_reg:x4; val_offset:1192*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1192*FLEN/8, x6, x1, x2) + +inst_622: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x77d1; op2val:0x8000; + valaddr_reg:x4; val_offset:1194*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1194*FLEN/8, x6, x1, x2) + +inst_623: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x77d1; op2val:0x8000; + valaddr_reg:x4; val_offset:1196*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1196*FLEN/8, x6, x1, x2) + +inst_624: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x77d1; op2val:0x8000; + valaddr_reg:x4; val_offset:1198*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1198*FLEN/8, x6, x1, x2) + +inst_625: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2d6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x76d6; op2val:0x8000; + valaddr_reg:x4; val_offset:1200*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1200*FLEN/8, x6, x1, x2) + +inst_626: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2d6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x76d6; op2val:0x8000; + valaddr_reg:x4; val_offset:1202*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1202*FLEN/8, x6, x1, x2) + +inst_627: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2d6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x76d6; op2val:0x8000; + valaddr_reg:x4; val_offset:1204*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1204*FLEN/8, x6, x1, x2) + +inst_628: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2d6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x76d6; op2val:0x8000; + valaddr_reg:x4; val_offset:1206*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1206*FLEN/8, x6, x1, x2) + +inst_629: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2d6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x76d6; op2val:0x8000; + valaddr_reg:x4; val_offset:1208*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1208*FLEN/8, x6, x1, x2) + +inst_630: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x358 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b58; op2val:0x8000; + valaddr_reg:x4; val_offset:1210*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1210*FLEN/8, x6, x1, x2) + +inst_631: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x358 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b58; op2val:0x8000; + valaddr_reg:x4; val_offset:1212*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1212*FLEN/8, x6, x1, x2) + +inst_632: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x358 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b58; op2val:0x8000; + valaddr_reg:x4; val_offset:1214*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1214*FLEN/8, x6, x1, x2) + +inst_633: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x358 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b58; op2val:0x8000; + valaddr_reg:x4; val_offset:1216*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1216*FLEN/8, x6, x1, x2) + +inst_634: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x358 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b58; op2val:0x8000; + valaddr_reg:x4; val_offset:1218*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1218*FLEN/8, x6, x1, x2) + +inst_635: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a8a; op2val:0x8000; + valaddr_reg:x4; val_offset:1220*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1220*FLEN/8, x6, x1, x2) + +inst_636: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a8a; op2val:0x8000; + valaddr_reg:x4; val_offset:1222*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1222*FLEN/8, x6, x1, x2) + +inst_637: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a8a; op2val:0x8000; + valaddr_reg:x4; val_offset:1224*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1224*FLEN/8, x6, x1, x2) + +inst_638: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a8a; op2val:0x8000; + valaddr_reg:x4; val_offset:1226*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1226*FLEN/8, x6, x1, x2) + +inst_639: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a8a; op2val:0x8000; + valaddr_reg:x4; val_offset:1228*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1228*FLEN/8, x6, x1, x2) + +inst_640: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1b1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x75b1; op2val:0x8000; + valaddr_reg:x4; val_offset:1230*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1230*FLEN/8, x6, x1, x2) + +inst_641: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1b1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x75b1; op2val:0x8000; + valaddr_reg:x4; val_offset:1232*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1232*FLEN/8, x6, x1, x2) + +inst_642: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1b1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x75b1; op2val:0x8000; + valaddr_reg:x4; val_offset:1234*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1234*FLEN/8, x6, x1, x2) + +inst_643: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1b1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x75b1; op2val:0x8000; + valaddr_reg:x4; val_offset:1236*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1236*FLEN/8, x6, x1, x2) + +inst_644: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1b1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x75b1; op2val:0x8000; + valaddr_reg:x4; val_offset:1238*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1238*FLEN/8, x6, x1, x2) + +inst_645: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0af and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x70af; op2val:0x8000; + valaddr_reg:x4; val_offset:1240*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1240*FLEN/8, x6, x1, x2) + +inst_646: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0af and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x70af; op2val:0x8000; + valaddr_reg:x4; val_offset:1242*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1242*FLEN/8, x6, x1, x2) + +inst_647: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0af and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x70af; op2val:0x8000; + valaddr_reg:x4; val_offset:1244*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1244*FLEN/8, x6, x1, x2) + +inst_648: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0af and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x70af; op2val:0x8000; + valaddr_reg:x4; val_offset:1246*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1246*FLEN/8, x6, x1, x2) + +inst_649: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0af and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x70af; op2val:0x8000; + valaddr_reg:x4; val_offset:1248*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1248*FLEN/8, x6, x1, x2) + +inst_650: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x046 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c46; op2val:0x8000; + valaddr_reg:x4; val_offset:1250*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1250*FLEN/8, x6, x1, x2) + +inst_651: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x046 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c46; op2val:0x8000; + valaddr_reg:x4; val_offset:1252*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1252*FLEN/8, x6, x1, x2) + +inst_652: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x046 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c46; op2val:0x8000; + valaddr_reg:x4; val_offset:1254*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1254*FLEN/8, x6, x1, x2) + +inst_653: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x046 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c46; op2val:0x8000; + valaddr_reg:x4; val_offset:1256*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1256*FLEN/8, x6, x1, x2) + +inst_654: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x046 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c46; op2val:0x8000; + valaddr_reg:x4; val_offset:1258*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1258*FLEN/8, x6, x1, x2) + +inst_655: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x329 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b29; op2val:0x0; + valaddr_reg:x4; val_offset:1260*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1260*FLEN/8, x6, x1, x2) + +inst_656: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x329 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b29; op2val:0x0; + valaddr_reg:x4; val_offset:1262*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1262*FLEN/8, x6, x1, x2) + +inst_657: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x329 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b29; op2val:0x0; + valaddr_reg:x4; val_offset:1264*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1264*FLEN/8, x6, x1, x2) + +inst_658: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x329 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b29; op2val:0x0; + valaddr_reg:x4; val_offset:1266*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1266*FLEN/8, x6, x1, x2) + +inst_659: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x329 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b29; op2val:0x0; + valaddr_reg:x4; val_offset:1268*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1268*FLEN/8, x6, x1, x2) + +inst_660: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x792e; op2val:0x0; + valaddr_reg:x4; val_offset:1270*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1270*FLEN/8, x6, x1, x2) + +inst_661: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x792e; op2val:0x0; + valaddr_reg:x4; val_offset:1272*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1272*FLEN/8, x6, x1, x2) + +inst_662: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x792e; op2val:0x0; + valaddr_reg:x4; val_offset:1274*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1274*FLEN/8, x6, x1, x2) + +inst_663: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x792e; op2val:0x0; + valaddr_reg:x4; val_offset:1276*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1276*FLEN/8, x6, x1, x2) + +inst_664: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x792e; op2val:0x0; + valaddr_reg:x4; val_offset:1278*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1278*FLEN/8, x6, x1, x2) + +inst_665: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0bd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x74bd; op2val:0x0; + valaddr_reg:x4; val_offset:1280*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1280*FLEN/8, x6, x1, x2) + +inst_666: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0bd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x74bd; op2val:0x0; + valaddr_reg:x4; val_offset:1282*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1282*FLEN/8, x6, x1, x2) + +inst_667: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0bd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x74bd; op2val:0x0; + valaddr_reg:x4; val_offset:1284*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1284*FLEN/8, x6, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_5) + +inst_668: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0bd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x74bd; op2val:0x0; + valaddr_reg:x4; val_offset:1286*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1286*FLEN/8, x6, x1, x2) + +inst_669: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0bd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x74bd; op2val:0x0; + valaddr_reg:x4; val_offset:1288*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1288*FLEN/8, x6, x1, x2) + +inst_670: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x795c; op2val:0x0; + valaddr_reg:x4; val_offset:1290*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1290*FLEN/8, x6, x1, x2) + +inst_671: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x795c; op2val:0x0; + valaddr_reg:x4; val_offset:1292*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1292*FLEN/8, x6, x1, x2) + +inst_672: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x795c; op2val:0x0; + valaddr_reg:x4; val_offset:1294*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1294*FLEN/8, x6, x1, x2) + +inst_673: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x795c; op2val:0x0; + valaddr_reg:x4; val_offset:1296*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1296*FLEN/8, x6, x1, x2) + +inst_674: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x795c; op2val:0x0; + valaddr_reg:x4; val_offset:1298*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1298*FLEN/8, x6, x1, x2) + +inst_675: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x304 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7704; op2val:0x0; + valaddr_reg:x4; val_offset:1300*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1300*FLEN/8, x6, x1, x2) + +inst_676: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x304 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7704; op2val:0x0; + valaddr_reg:x4; val_offset:1302*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1302*FLEN/8, x6, x1, x2) + +inst_677: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x304 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7704; op2val:0x0; + valaddr_reg:x4; val_offset:1304*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1304*FLEN/8, x6, x1, x2) + +inst_678: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x304 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7704; op2val:0x0; + valaddr_reg:x4; val_offset:1306*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1306*FLEN/8, x6, x1, x2) + +inst_679: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x304 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7704; op2val:0x0; + valaddr_reg:x4; val_offset:1308*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1308*FLEN/8, x6, x1, x2) + +inst_680: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x32b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f2b; op2val:0x0; + valaddr_reg:x4; val_offset:1310*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1310*FLEN/8, x6, x1, x2) + +inst_681: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x32b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f2b; op2val:0x0; + valaddr_reg:x4; val_offset:1312*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1312*FLEN/8, x6, x1, x2) + +inst_682: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x32b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f2b; op2val:0x0; + valaddr_reg:x4; val_offset:1314*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1314*FLEN/8, x6, x1, x2) + +inst_683: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x32b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f2b; op2val:0x0; + valaddr_reg:x4; val_offset:1316*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1316*FLEN/8, x6, x1, x2) + +inst_684: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x32b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f2b; op2val:0x0; + valaddr_reg:x4; val_offset:1318*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1318*FLEN/8, x6, x1, x2) + +inst_685: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x398 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b98; op2val:0x0; + valaddr_reg:x4; val_offset:1320*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1320*FLEN/8, x6, x1, x2) + +inst_686: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x398 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b98; op2val:0x0; + valaddr_reg:x4; val_offset:1322*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1322*FLEN/8, x6, x1, x2) + +inst_687: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x398 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b98; op2val:0x0; + valaddr_reg:x4; val_offset:1324*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1324*FLEN/8, x6, x1, x2) + +inst_688: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x398 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b98; op2val:0x0; + valaddr_reg:x4; val_offset:1326*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1326*FLEN/8, x6, x1, x2) + +inst_689: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x398 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b98; op2val:0x0; + valaddr_reg:x4; val_offset:1328*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1328*FLEN/8, x6, x1, x2) + +inst_690: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x226 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e26; op2val:0x0; + valaddr_reg:x4; val_offset:1330*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1330*FLEN/8, x6, x1, x2) + +inst_691: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x226 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e26; op2val:0x0; + valaddr_reg:x4; val_offset:1332*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1332*FLEN/8, x6, x1, x2) + +inst_692: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x226 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e26; op2val:0x0; + valaddr_reg:x4; val_offset:1334*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1334*FLEN/8, x6, x1, x2) + +inst_693: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x226 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e26; op2val:0x0; + valaddr_reg:x4; val_offset:1336*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1336*FLEN/8, x6, x1, x2) + +inst_694: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x226 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e26; op2val:0x0; + valaddr_reg:x4; val_offset:1338*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1338*FLEN/8, x6, x1, x2) + +inst_695: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b8; op2val:0x0; + valaddr_reg:x4; val_offset:1340*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1340*FLEN/8, x6, x1, x2) + +inst_696: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b8; op2val:0x0; + valaddr_reg:x4; val_offset:1342*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1342*FLEN/8, x6, x1, x2) + +inst_697: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b8; op2val:0x0; + valaddr_reg:x4; val_offset:1344*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1344*FLEN/8, x6, x1, x2) + +inst_698: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b8; op2val:0x0; + valaddr_reg:x4; val_offset:1346*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1346*FLEN/8, x6, x1, x2) + +inst_699: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b8; op2val:0x0; + valaddr_reg:x4; val_offset:1348*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1348*FLEN/8, x6, x1, x2) + +inst_700: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x327 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b27; op2val:0x0; + valaddr_reg:x4; val_offset:1350*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1350*FLEN/8, x6, x1, x2) + +inst_701: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x327 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b27; op2val:0x0; + valaddr_reg:x4; val_offset:1352*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1352*FLEN/8, x6, x1, x2) + +inst_702: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x327 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b27; op2val:0x0; + valaddr_reg:x4; val_offset:1354*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1354*FLEN/8, x6, x1, x2) + +inst_703: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x327 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b27; op2val:0x0; + valaddr_reg:x4; val_offset:1356*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1356*FLEN/8, x6, x1, x2) + +inst_704: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x327 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b27; op2val:0x0; + valaddr_reg:x4; val_offset:1358*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1358*FLEN/8, x6, x1, x2) + +inst_705: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x799f; op2val:0x0; + valaddr_reg:x4; val_offset:1360*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1360*FLEN/8, x6, x1, x2) + +inst_706: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x799f; op2val:0x0; + valaddr_reg:x4; val_offset:1362*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1362*FLEN/8, x6, x1, x2) + +inst_707: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x799f; op2val:0x0; + valaddr_reg:x4; val_offset:1364*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1364*FLEN/8, x6, x1, x2) + +inst_708: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x799f; op2val:0x0; + valaddr_reg:x4; val_offset:1366*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1366*FLEN/8, x6, x1, x2) + +inst_709: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x799f; op2val:0x0; + valaddr_reg:x4; val_offset:1368*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1368*FLEN/8, x6, x1, x2) + +inst_710: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bf5; op2val:0x0; + valaddr_reg:x4; val_offset:1370*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1370*FLEN/8, x6, x1, x2) + +inst_711: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bf5; op2val:0x0; + valaddr_reg:x4; val_offset:1372*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1372*FLEN/8, x6, x1, x2) + +inst_712: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bf5; op2val:0x0; + valaddr_reg:x4; val_offset:1374*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1374*FLEN/8, x6, x1, x2) + +inst_713: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bf5; op2val:0x0; + valaddr_reg:x4; val_offset:1376*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1376*FLEN/8, x6, x1, x2) + +inst_714: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bf5; op2val:0x0; + valaddr_reg:x4; val_offset:1378*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1378*FLEN/8, x6, x1, x2) + +inst_715: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x095 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7895; op2val:0x0; + valaddr_reg:x4; val_offset:1380*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1380*FLEN/8, x6, x1, x2) + +inst_716: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x095 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7895; op2val:0x0; + valaddr_reg:x4; val_offset:1382*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1382*FLEN/8, x6, x1, x2) + +inst_717: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x095 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7895; op2val:0x0; + valaddr_reg:x4; val_offset:1384*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1384*FLEN/8, x6, x1, x2) + +inst_718: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x095 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7895; op2val:0x0; + valaddr_reg:x4; val_offset:1386*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1386*FLEN/8, x6, x1, x2) + +inst_719: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x095 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7895; op2val:0x0; + valaddr_reg:x4; val_offset:1388*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1388*FLEN/8, x6, x1, x2) + +inst_720: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x30e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x770e; op2val:0x0; + valaddr_reg:x4; val_offset:1390*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1390*FLEN/8, x6, x1, x2) + +inst_721: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x30e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x770e; op2val:0x0; + valaddr_reg:x4; val_offset:1392*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1392*FLEN/8, x6, x1, x2) + +inst_722: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x30e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x770e; op2val:0x0; + valaddr_reg:x4; val_offset:1394*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1394*FLEN/8, x6, x1, x2) + +inst_723: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x30e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x770e; op2val:0x0; + valaddr_reg:x4; val_offset:1396*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1396*FLEN/8, x6, x1, x2) + +inst_724: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x30e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x770e; op2val:0x0; + valaddr_reg:x4; val_offset:1398*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1398*FLEN/8, x6, x1, x2) + +inst_725: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x78c2; op2val:0x8000; + valaddr_reg:x4; val_offset:1400*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1400*FLEN/8, x6, x1, x2) + +inst_726: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x78c2; op2val:0x8000; + valaddr_reg:x4; val_offset:1402*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1402*FLEN/8, x6, x1, x2) + +inst_727: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x78c2; op2val:0x8000; + valaddr_reg:x4; val_offset:1404*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1404*FLEN/8, x6, x1, x2) + +inst_728: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x78c2; op2val:0x8000; + valaddr_reg:x4; val_offset:1406*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1406*FLEN/8, x6, x1, x2) + +inst_729: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x78c2; op2val:0x8000; + valaddr_reg:x4; val_offset:1408*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1408*FLEN/8, x6, x1, x2) + +inst_730: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1c5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x71c5; op2val:0x8000; + valaddr_reg:x4; val_offset:1410*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1410*FLEN/8, x6, x1, x2) + +inst_731: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1c5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x71c5; op2val:0x8000; + valaddr_reg:x4; val_offset:1412*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1412*FLEN/8, x6, x1, x2) + +inst_732: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1c5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x71c5; op2val:0x8000; + valaddr_reg:x4; val_offset:1414*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1414*FLEN/8, x6, x1, x2) + +inst_733: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1c5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x71c5; op2val:0x8000; + valaddr_reg:x4; val_offset:1416*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1416*FLEN/8, x6, x1, x2) + +inst_734: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1c5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x71c5; op2val:0x8000; + valaddr_reg:x4; val_offset:1418*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1418*FLEN/8, x6, x1, x2) + +inst_735: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3b7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x77b7; op2val:0x8000; + valaddr_reg:x4; val_offset:1420*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1420*FLEN/8, x6, x1, x2) + +inst_736: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3b7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x77b7; op2val:0x8000; + valaddr_reg:x4; val_offset:1422*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1422*FLEN/8, x6, x1, x2) + +inst_737: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3b7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x77b7; op2val:0x8000; + valaddr_reg:x4; val_offset:1424*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1424*FLEN/8, x6, x1, x2) + +inst_738: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3b7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x77b7; op2val:0x8000; + valaddr_reg:x4; val_offset:1426*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1426*FLEN/8, x6, x1, x2) + +inst_739: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3b7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x77b7; op2val:0x8000; + valaddr_reg:x4; val_offset:1428*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1428*FLEN/8, x6, x1, x2) + +inst_740: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ae and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79ae; op2val:0x8000; + valaddr_reg:x4; val_offset:1430*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1430*FLEN/8, x6, x1, x2) + +inst_741: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ae and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79ae; op2val:0x8000; + valaddr_reg:x4; val_offset:1432*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1432*FLEN/8, x6, x1, x2) + +inst_742: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ae and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79ae; op2val:0x8000; + valaddr_reg:x4; val_offset:1434*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1434*FLEN/8, x6, x1, x2) + +inst_743: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ae and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79ae; op2val:0x8000; + valaddr_reg:x4; val_offset:1436*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1436*FLEN/8, x6, x1, x2) + +inst_744: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ae and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79ae; op2val:0x8000; + valaddr_reg:x4; val_offset:1438*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1438*FLEN/8, x6, x1, x2) + +inst_745: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79a3; op2val:0x8000; + valaddr_reg:x4; val_offset:1440*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1440*FLEN/8, x6, x1, x2) + +inst_746: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79a3; op2val:0x8000; + valaddr_reg:x4; val_offset:1442*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1442*FLEN/8, x6, x1, x2) + +inst_747: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79a3; op2val:0x8000; + valaddr_reg:x4; val_offset:1444*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1444*FLEN/8, x6, x1, x2) + +inst_748: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79a3; op2val:0x8000; + valaddr_reg:x4; val_offset:1446*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1446*FLEN/8, x6, x1, x2) + +inst_749: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79a3; op2val:0x8000; + valaddr_reg:x4; val_offset:1448*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1448*FLEN/8, x6, x1, x2) + +inst_750: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb1; op2val:0x8000; + valaddr_reg:x4; val_offset:1450*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1450*FLEN/8, x6, x1, x2) + +inst_751: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb1; op2val:0x8000; + valaddr_reg:x4; val_offset:1452*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1452*FLEN/8, x6, x1, x2) + +inst_752: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb1; op2val:0x8000; + valaddr_reg:x4; val_offset:1454*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1454*FLEN/8, x6, x1, x2) + +inst_753: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb1; op2val:0x8000; + valaddr_reg:x4; val_offset:1456*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1456*FLEN/8, x6, x1, x2) + +inst_754: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb1; op2val:0x8000; + valaddr_reg:x4; val_offset:1458*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1458*FLEN/8, x6, x1, x2) + +inst_755: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79f6; op2val:0x8000; + valaddr_reg:x4; val_offset:1460*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1460*FLEN/8, x6, x1, x2) + +inst_756: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79f6; op2val:0x8000; + valaddr_reg:x4; val_offset:1462*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1462*FLEN/8, x6, x1, x2) + +inst_757: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79f6; op2val:0x8000; + valaddr_reg:x4; val_offset:1464*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1464*FLEN/8, x6, x1, x2) + +inst_758: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79f6; op2val:0x8000; + valaddr_reg:x4; val_offset:1466*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1466*FLEN/8, x6, x1, x2) + +inst_759: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79f6; op2val:0x8000; + valaddr_reg:x4; val_offset:1468*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1468*FLEN/8, x6, x1, x2) + +inst_760: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x217 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a17; op2val:0x8000; + valaddr_reg:x4; val_offset:1470*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1470*FLEN/8, x6, x1, x2) + +inst_761: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x217 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a17; op2val:0x8000; + valaddr_reg:x4; val_offset:1472*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1472*FLEN/8, x6, x1, x2) + +inst_762: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x217 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a17; op2val:0x8000; + valaddr_reg:x4; val_offset:1474*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1474*FLEN/8, x6, x1, x2) + +inst_763: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x217 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a17; op2val:0x8000; + valaddr_reg:x4; val_offset:1476*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1476*FLEN/8, x6, x1, x2) + +inst_764: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x217 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a17; op2val:0x8000; + valaddr_reg:x4; val_offset:1478*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1478*FLEN/8, x6, x1, x2) + +inst_765: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x332 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7332; op2val:0x8000; + valaddr_reg:x4; val_offset:1480*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1480*FLEN/8, x6, x1, x2) + +inst_766: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x332 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7332; op2val:0x8000; + valaddr_reg:x4; val_offset:1482*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1482*FLEN/8, x6, x1, x2) + +inst_767: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x332 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7332; op2val:0x8000; + valaddr_reg:x4; val_offset:1484*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1484*FLEN/8, x6, x1, x2) + +inst_768: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x332 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7332; op2val:0x8000; + valaddr_reg:x4; val_offset:1486*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1486*FLEN/8, x6, x1, x2) + +inst_769: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x332 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7332; op2val:0x8000; + valaddr_reg:x4; val_offset:1488*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1488*FLEN/8, x6, x1, x2) + +inst_770: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x270 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7670; op2val:0x8000; + valaddr_reg:x4; val_offset:1490*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1490*FLEN/8, x6, x1, x2) + +inst_771: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x270 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7670; op2val:0x8000; + valaddr_reg:x4; val_offset:1492*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1492*FLEN/8, x6, x1, x2) + +inst_772: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x270 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7670; op2val:0x8000; + valaddr_reg:x4; val_offset:1494*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1494*FLEN/8, x6, x1, x2) + +inst_773: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x270 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7670; op2val:0x8000; + valaddr_reg:x4; val_offset:1496*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1496*FLEN/8, x6, x1, x2) + +inst_774: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x270 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7670; op2val:0x8000; + valaddr_reg:x4; val_offset:1498*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1498*FLEN/8, x6, x1, x2) + +inst_775: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bd0; op2val:0x8000; + valaddr_reg:x4; val_offset:1500*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1500*FLEN/8, x6, x1, x2) + +inst_776: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bd0; op2val:0x8000; + valaddr_reg:x4; val_offset:1502*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1502*FLEN/8, x6, x1, x2) + +inst_777: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bd0; op2val:0x8000; + valaddr_reg:x4; val_offset:1504*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1504*FLEN/8, x6, x1, x2) + +inst_778: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bd0; op2val:0x8000; + valaddr_reg:x4; val_offset:1506*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1506*FLEN/8, x6, x1, x2) + +inst_779: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bd0; op2val:0x8000; + valaddr_reg:x4; val_offset:1508*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1508*FLEN/8, x6, x1, x2) + +inst_780: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x1f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x61f2; op2val:0x8001; + valaddr_reg:x4; val_offset:1510*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1510*FLEN/8, x6, x1, x2) + +inst_781: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x1f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x61f2; op2val:0x8001; + valaddr_reg:x4; val_offset:1512*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1512*FLEN/8, x6, x1, x2) + +inst_782: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x1f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x61f2; op2val:0x8001; + valaddr_reg:x4; val_offset:1514*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1514*FLEN/8, x6, x1, x2) + +inst_783: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x1f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x61f2; op2val:0x8001; + valaddr_reg:x4; val_offset:1516*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1516*FLEN/8, x6, x1, x2) + +inst_784: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x1f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x61f2; op2val:0x8001; + valaddr_reg:x4; val_offset:1518*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1518*FLEN/8, x6, x1, x2) + +inst_785: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b0; op2val:0x8000; + valaddr_reg:x4; val_offset:1520*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1520*FLEN/8, x6, x1, x2) + +inst_786: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b0; op2val:0x8000; + valaddr_reg:x4; val_offset:1522*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1522*FLEN/8, x6, x1, x2) + +inst_787: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b0; op2val:0x8000; + valaddr_reg:x4; val_offset:1524*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1524*FLEN/8, x6, x1, x2) + +inst_788: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b0; op2val:0x8000; + valaddr_reg:x4; val_offset:1526*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1526*FLEN/8, x6, x1, x2) + +inst_789: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b0; op2val:0x8000; + valaddr_reg:x4; val_offset:1528*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1528*FLEN/8, x6, x1, x2) + +inst_790: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x132 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7932; op2val:0x8000; + valaddr_reg:x4; val_offset:1530*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1530*FLEN/8, x6, x1, x2) + +inst_791: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x132 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7932; op2val:0x8000; + valaddr_reg:x4; val_offset:1532*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1532*FLEN/8, x6, x1, x2) + +inst_792: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x132 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7932; op2val:0x8000; + valaddr_reg:x4; val_offset:1534*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1534*FLEN/8, x6, x1, x2) + +inst_793: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x132 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7932; op2val:0x8000; + valaddr_reg:x4; val_offset:1536*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1536*FLEN/8, x6, x1, x2) + +inst_794: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x132 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7932; op2val:0x8000; + valaddr_reg:x4; val_offset:1538*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1538*FLEN/8, x6, x1, x2) + +inst_795: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x063 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6463; op2val:0x1; + valaddr_reg:x4; val_offset:1540*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1540*FLEN/8, x6, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_6) + +inst_796: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x063 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6463; op2val:0x1; + valaddr_reg:x4; val_offset:1542*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1542*FLEN/8, x6, x1, x2) + +inst_797: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x063 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6463; op2val:0x1; + valaddr_reg:x4; val_offset:1544*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1544*FLEN/8, x6, x1, x2) + +inst_798: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x063 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6463; op2val:0x1; + valaddr_reg:x4; val_offset:1546*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1546*FLEN/8, x6, x1, x2) + +inst_799: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x063 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6463; op2val:0x1; + valaddr_reg:x4; val_offset:1548*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1548*FLEN/8, x6, x1, x2) + +inst_800: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79d5; op2val:0x0; + valaddr_reg:x4; val_offset:1550*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1550*FLEN/8, x6, x1, x2) + +inst_801: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79d5; op2val:0x0; + valaddr_reg:x4; val_offset:1552*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1552*FLEN/8, x6, x1, x2) + +inst_802: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79d5; op2val:0x0; + valaddr_reg:x4; val_offset:1554*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1554*FLEN/8, x6, x1, x2) + +inst_803: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79d5; op2val:0x0; + valaddr_reg:x4; val_offset:1556*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1556*FLEN/8, x6, x1, x2) + +inst_804: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79d5; op2val:0x0; + valaddr_reg:x4; val_offset:1558*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1558*FLEN/8, x6, x1, x2) + +inst_805: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x33d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b3d; op2val:0x0; + valaddr_reg:x4; val_offset:1560*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1560*FLEN/8, x6, x1, x2) + +inst_806: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x33d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b3d; op2val:0x0; + valaddr_reg:x4; val_offset:1562*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1562*FLEN/8, x6, x1, x2) + +inst_807: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x33d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b3d; op2val:0x0; + valaddr_reg:x4; val_offset:1564*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1564*FLEN/8, x6, x1, x2) + +inst_808: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x33d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b3d; op2val:0x0; + valaddr_reg:x4; val_offset:1566*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1566*FLEN/8, x6, x1, x2) + +inst_809: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x33d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b3d; op2val:0x0; + valaddr_reg:x4; val_offset:1568*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1568*FLEN/8, x6, x1, x2) + +inst_810: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x26d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e6d; op2val:0x0; + valaddr_reg:x4; val_offset:1570*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1570*FLEN/8, x6, x1, x2) + +inst_811: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x26d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e6d; op2val:0x0; + valaddr_reg:x4; val_offset:1572*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1572*FLEN/8, x6, x1, x2) + +inst_812: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x26d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e6d; op2val:0x0; + valaddr_reg:x4; val_offset:1574*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1574*FLEN/8, x6, x1, x2) + +inst_813: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x26d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e6d; op2val:0x0; + valaddr_reg:x4; val_offset:1576*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1576*FLEN/8, x6, x1, x2) + +inst_814: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x26d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e6d; op2val:0x0; + valaddr_reg:x4; val_offset:1578*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1578*FLEN/8, x6, x1, x2) + +inst_815: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x222 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a22; op2val:0x0; + valaddr_reg:x4; val_offset:1580*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1580*FLEN/8, x6, x1, x2) + +inst_816: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x222 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a22; op2val:0x0; + valaddr_reg:x4; val_offset:1582*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1582*FLEN/8, x6, x1, x2) + +inst_817: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x222 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a22; op2val:0x0; + valaddr_reg:x4; val_offset:1584*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1584*FLEN/8, x6, x1, x2) + +inst_818: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x222 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a22; op2val:0x0; + valaddr_reg:x4; val_offset:1586*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1586*FLEN/8, x6, x1, x2) + +inst_819: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x222 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a22; op2val:0x0; + valaddr_reg:x4; val_offset:1588*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1588*FLEN/8, x6, x1, x2) + +inst_820: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79f3; op2val:0x0; + valaddr_reg:x4; val_offset:1590*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1590*FLEN/8, x6, x1, x2) + +inst_821: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79f3; op2val:0x0; + valaddr_reg:x4; val_offset:1592*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1592*FLEN/8, x6, x1, x2) + +inst_822: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79f3; op2val:0x0; + valaddr_reg:x4; val_offset:1594*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1594*FLEN/8, x6, x1, x2) + +inst_823: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79f3; op2val:0x0; + valaddr_reg:x4; val_offset:1596*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1596*FLEN/8, x6, x1, x2) + +inst_824: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79f3; op2val:0x0; + valaddr_reg:x4; val_offset:1598*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1598*FLEN/8, x6, x1, x2) + +inst_825: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x220 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7220; op2val:0x0; + valaddr_reg:x4; val_offset:1600*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1600*FLEN/8, x6, x1, x2) + +inst_826: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x220 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7220; op2val:0x0; + valaddr_reg:x4; val_offset:1602*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1602*FLEN/8, x6, x1, x2) + +inst_827: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x220 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7220; op2val:0x0; + valaddr_reg:x4; val_offset:1604*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1604*FLEN/8, x6, x1, x2) + +inst_828: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x220 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7220; op2val:0x0; + valaddr_reg:x4; val_offset:1606*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1606*FLEN/8, x6, x1, x2) + +inst_829: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x220 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7220; op2val:0x0; + valaddr_reg:x4; val_offset:1608*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1608*FLEN/8, x6, x1, x2) + +inst_830: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x069 and fs2 == 0 and fe2 == 0x07 and fm2 == 0x341 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7069; op2val:0x1f41; + valaddr_reg:x4; val_offset:1610*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1610*FLEN/8, x6, x1, x2) + +inst_831: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x069 and fs2 == 0 and fe2 == 0x07 and fm2 == 0x341 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7069; op2val:0x1f41; + valaddr_reg:x4; val_offset:1612*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1612*FLEN/8, x6, x1, x2) + +inst_832: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x069 and fs2 == 0 and fe2 == 0x07 and fm2 == 0x341 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7069; op2val:0x1f41; + valaddr_reg:x4; val_offset:1614*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1614*FLEN/8, x6, x1, x2) + +inst_833: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x069 and fs2 == 0 and fe2 == 0x07 and fm2 == 0x341 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7069; op2val:0x1f41; + valaddr_reg:x4; val_offset:1616*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1616*FLEN/8, x6, x1, x2) + +inst_834: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x069 and fs2 == 0 and fe2 == 0x07 and fm2 == 0x341 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7069; op2val:0x1f41; + valaddr_reg:x4; val_offset:1618*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1618*FLEN/8, x6, x1, x2) + +inst_835: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2f2 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x09b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x76f2; op2val:0x189b; + valaddr_reg:x4; val_offset:1620*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1620*FLEN/8, x6, x1, x2) + +inst_836: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2f2 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x09b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x76f2; op2val:0x189b; + valaddr_reg:x4; val_offset:1622*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1622*FLEN/8, x6, x1, x2) + +inst_837: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2f2 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x09b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x76f2; op2val:0x189b; + valaddr_reg:x4; val_offset:1624*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1624*FLEN/8, x6, x1, x2) + +inst_838: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2f2 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x09b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x76f2; op2val:0x189b; + valaddr_reg:x4; val_offset:1626*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1626*FLEN/8, x6, x1, x2) + +inst_839: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2f2 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x09b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x76f2; op2val:0x189b; + valaddr_reg:x4; val_offset:1628*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1628*FLEN/8, x6, x1, x2) + +inst_840: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x086 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x311 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7886; op2val:0x1711; + valaddr_reg:x4; val_offset:1630*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1630*FLEN/8, x6, x1, x2) + +inst_841: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x086 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x311 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7886; op2val:0x1711; + valaddr_reg:x4; val_offset:1632*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1632*FLEN/8, x6, x1, x2) + +inst_842: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x086 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x311 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7886; op2val:0x1711; + valaddr_reg:x4; val_offset:1634*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1634*FLEN/8, x6, x1, x2) + +inst_843: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x086 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x311 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7886; op2val:0x1711; + valaddr_reg:x4; val_offset:1636*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1636*FLEN/8, x6, x1, x2) + +inst_844: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x086 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x311 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7886; op2val:0x1711; + valaddr_reg:x4; val_offset:1638*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1638*FLEN/8, x6, x1, x2) + +inst_845: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x28e and fs2 == 0 and fe2 == 0x07 and fm2 == 0x0e1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x728e; op2val:0x1ce1; + valaddr_reg:x4; val_offset:1640*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1640*FLEN/8, x6, x1, x2) + +inst_846: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x28e and fs2 == 0 and fe2 == 0x07 and fm2 == 0x0e1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x728e; op2val:0x1ce1; + valaddr_reg:x4; val_offset:1642*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1642*FLEN/8, x6, x1, x2) + +inst_847: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x28e and fs2 == 0 and fe2 == 0x07 and fm2 == 0x0e1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x728e; op2val:0x1ce1; + valaddr_reg:x4; val_offset:1644*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1644*FLEN/8, x6, x1, x2) + +inst_848: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x28e and fs2 == 0 and fe2 == 0x07 and fm2 == 0x0e1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x728e; op2val:0x1ce1; + valaddr_reg:x4; val_offset:1646*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1646*FLEN/8, x6, x1, x2) + +inst_849: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x28e and fs2 == 0 and fe2 == 0x07 and fm2 == 0x0e1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x728e; op2val:0x1ce1; + valaddr_reg:x4; val_offset:1648*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1648*FLEN/8, x6, x1, x2) + +inst_850: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0a8 and fs2 == 0 and fe2 == 0x08 and fm2 == 0x2de and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ca8; op2val:0x22de; + valaddr_reg:x4; val_offset:1650*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1650*FLEN/8, x6, x1, x2) + +inst_851: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0a8 and fs2 == 0 and fe2 == 0x08 and fm2 == 0x2de and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ca8; op2val:0x22de; + valaddr_reg:x4; val_offset:1652*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1652*FLEN/8, x6, x1, x2) + +inst_852: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0a8 and fs2 == 0 and fe2 == 0x08 and fm2 == 0x2de and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ca8; op2val:0x22de; + valaddr_reg:x4; val_offset:1654*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1654*FLEN/8, x6, x1, x2) + +inst_853: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0a8 and fs2 == 0 and fe2 == 0x08 and fm2 == 0x2de and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ca8; op2val:0x22de; + valaddr_reg:x4; val_offset:1656*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1656*FLEN/8, x6, x1, x2) + +inst_854: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0a8 and fs2 == 0 and fe2 == 0x08 and fm2 == 0x2de and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ca8; op2val:0x22de; + valaddr_reg:x4; val_offset:1658*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1658*FLEN/8, x6, x1, x2) + +inst_855: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3c3 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x77c3; op2val:0x181f; + valaddr_reg:x4; val_offset:1660*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1660*FLEN/8, x6, x1, x2) + +inst_856: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3c3 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x01f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x77c3; op2val:0x181f; + valaddr_reg:x4; val_offset:1662*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1662*FLEN/8, x6, x1, x2) + +inst_857: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3c3 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x01f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x77c3; op2val:0x181f; + valaddr_reg:x4; val_offset:1664*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1664*FLEN/8, x6, x1, x2) + +inst_858: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3c3 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x01f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x77c3; op2val:0x181f; + valaddr_reg:x4; val_offset:1666*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1666*FLEN/8, x6, x1, x2) + +inst_859: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3c3 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x01f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x77c3; op2val:0x181f; + valaddr_reg:x4; val_offset:1668*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1668*FLEN/8, x6, x1, x2) + +inst_860: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x143 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x214 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7943; op2val:0x1614; + valaddr_reg:x4; val_offset:1670*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1670*FLEN/8, x6, x1, x2) + +inst_861: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x143 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x214 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7943; op2val:0x1614; + valaddr_reg:x4; val_offset:1672*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1672*FLEN/8, x6, x1, x2) + +inst_862: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x143 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x214 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7943; op2val:0x1614; + valaddr_reg:x4; val_offset:1674*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1674*FLEN/8, x6, x1, x2) + +inst_863: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x143 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x214 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7943; op2val:0x1614; + valaddr_reg:x4; val_offset:1676*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1676*FLEN/8, x6, x1, x2) + +inst_864: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x143 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x214 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7943; op2val:0x1614; + valaddr_reg:x4; val_offset:1678*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1678*FLEN/8, x6, x1, x2) + +inst_865: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3c1 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x020 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x77c1; op2val:0x9820; + valaddr_reg:x4; val_offset:1680*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1680*FLEN/8, x6, x1, x2) + +inst_866: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3c1 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x020 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x77c1; op2val:0x9820; + valaddr_reg:x4; val_offset:1682*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1682*FLEN/8, x6, x1, x2) + +inst_867: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3c1 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x020 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x77c1; op2val:0x9820; + valaddr_reg:x4; val_offset:1684*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1684*FLEN/8, x6, x1, x2) + +inst_868: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3c1 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x020 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x77c1; op2val:0x9820; + valaddr_reg:x4; val_offset:1686*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1686*FLEN/8, x6, x1, x2) + +inst_869: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3c1 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x020 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x77c1; op2val:0x9820; + valaddr_reg:x4; val_offset:1688*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1688*FLEN/8, x6, x1, x2) + +inst_870: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x15b and fs2 == 1 and fe2 == 0x06 and fm2 == 0x1f9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x755b; op2val:0x99f9; + valaddr_reg:x4; val_offset:1690*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1690*FLEN/8, x6, x1, x2) + +inst_871: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x15b and fs2 == 1 and fe2 == 0x06 and fm2 == 0x1f9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x755b; op2val:0x99f9; + valaddr_reg:x4; val_offset:1692*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1692*FLEN/8, x6, x1, x2) + +inst_872: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x15b and fs2 == 1 and fe2 == 0x06 and fm2 == 0x1f9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x755b; op2val:0x99f9; + valaddr_reg:x4; val_offset:1694*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1694*FLEN/8, x6, x1, x2) + +inst_873: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x15b and fs2 == 1 and fe2 == 0x06 and fm2 == 0x1f9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x755b; op2val:0x99f9; + valaddr_reg:x4; val_offset:1696*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1696*FLEN/8, x6, x1, x2) + +inst_874: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x15b and fs2 == 1 and fe2 == 0x06 and fm2 == 0x1f9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x755b; op2val:0x99f9; + valaddr_reg:x4; val_offset:1698*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1698*FLEN/8, x6, x1, x2) + +inst_875: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x005 and fs2 == 1 and fe2 == 0x05 and fm2 == 0x3f5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7805; op2val:0x97f5; + valaddr_reg:x4; val_offset:1700*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1700*FLEN/8, x6, x1, x2) + +inst_876: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x005 and fs2 == 1 and fe2 == 0x05 and fm2 == 0x3f5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7805; op2val:0x97f5; + valaddr_reg:x4; val_offset:1702*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1702*FLEN/8, x6, x1, x2) + +inst_877: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x005 and fs2 == 1 and fe2 == 0x05 and fm2 == 0x3f5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7805; op2val:0x97f5; + valaddr_reg:x4; val_offset:1704*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1704*FLEN/8, x6, x1, x2) + +inst_878: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x005 and fs2 == 1 and fe2 == 0x05 and fm2 == 0x3f5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7805; op2val:0x97f5; + valaddr_reg:x4; val_offset:1706*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1706*FLEN/8, x6, x1, x2) + +inst_879: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x005 and fs2 == 1 and fe2 == 0x05 and fm2 == 0x3f5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7805; op2val:0x97f5; + valaddr_reg:x4; val_offset:1708*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1708*FLEN/8, x6, x1, x2) + +inst_880: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x11b and fs2 == 1 and fe2 == 0x08 and fm2 == 0x244 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d1b; op2val:0xa244; + valaddr_reg:x4; val_offset:1710*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1710*FLEN/8, x6, x1, x2) + +inst_881: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x11b and fs2 == 1 and fe2 == 0x08 and fm2 == 0x244 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d1b; op2val:0xa244; + valaddr_reg:x4; val_offset:1712*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1712*FLEN/8, x6, x1, x2) + +inst_882: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x11b and fs2 == 1 and fe2 == 0x08 and fm2 == 0x244 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d1b; op2val:0xa244; + valaddr_reg:x4; val_offset:1714*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1714*FLEN/8, x6, x1, x2) + +inst_883: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x11b and fs2 == 1 and fe2 == 0x08 and fm2 == 0x244 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d1b; op2val:0xa244; + valaddr_reg:x4; val_offset:1716*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1716*FLEN/8, x6, x1, x2) + +inst_884: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x11b and fs2 == 1 and fe2 == 0x08 and fm2 == 0x244 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d1b; op2val:0xa244; + valaddr_reg:x4; val_offset:1718*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1718*FLEN/8, x6, x1, x2) + +inst_885: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x18e and fs2 == 1 and fe2 == 0x07 and fm2 == 0x1c2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x718e; op2val:0x9dc2; + valaddr_reg:x4; val_offset:1720*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1720*FLEN/8, x6, x1, x2) + +inst_886: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x18e and fs2 == 1 and fe2 == 0x07 and fm2 == 0x1c2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x718e; op2val:0x9dc2; + valaddr_reg:x4; val_offset:1722*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1722*FLEN/8, x6, x1, x2) + +inst_887: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x18e and fs2 == 1 and fe2 == 0x07 and fm2 == 0x1c2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x718e; op2val:0x9dc2; + valaddr_reg:x4; val_offset:1724*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1724*FLEN/8, x6, x1, x2) + +inst_888: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x18e and fs2 == 1 and fe2 == 0x07 and fm2 == 0x1c2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x718e; op2val:0x9dc2; + valaddr_reg:x4; val_offset:1726*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1726*FLEN/8, x6, x1, x2) + +inst_889: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x18e and fs2 == 1 and fe2 == 0x07 and fm2 == 0x1c2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x718e; op2val:0x9dc2; + valaddr_reg:x4; val_offset:1728*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1728*FLEN/8, x6, x1, x2) + +inst_890: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x245 and fs2 == 1 and fe2 == 0x05 and fm2 == 0x11a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a45; op2val:0x951a; + valaddr_reg:x4; val_offset:1730*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1730*FLEN/8, x6, x1, x2) + +inst_891: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x245 and fs2 == 1 and fe2 == 0x05 and fm2 == 0x11a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a45; op2val:0x951a; + valaddr_reg:x4; val_offset:1732*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1732*FLEN/8, x6, x1, x2) + +inst_892: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x245 and fs2 == 1 and fe2 == 0x05 and fm2 == 0x11a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a45; op2val:0x951a; + valaddr_reg:x4; val_offset:1734*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1734*FLEN/8, x6, x1, x2) + +inst_893: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x245 and fs2 == 1 and fe2 == 0x05 and fm2 == 0x11a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a45; op2val:0x951a; + valaddr_reg:x4; val_offset:1736*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1736*FLEN/8, x6, x1, x2) + +inst_894: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x245 and fs2 == 1 and fe2 == 0x05 and fm2 == 0x11a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a45; op2val:0x951a; + valaddr_reg:x4; val_offset:1738*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1738*FLEN/8, x6, x1, x2) + +inst_895: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x165 and fs2 == 1 and fe2 == 0x05 and fm2 == 0x1ed and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7965; op2val:0x95ed; + valaddr_reg:x4; val_offset:1740*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1740*FLEN/8, x6, x1, x2) + +inst_896: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x165 and fs2 == 1 and fe2 == 0x05 and fm2 == 0x1ed and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7965; op2val:0x95ed; + valaddr_reg:x4; val_offset:1742*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1742*FLEN/8, x6, x1, x2) + +inst_897: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x165 and fs2 == 1 and fe2 == 0x05 and fm2 == 0x1ed and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7965; op2val:0x95ed; + valaddr_reg:x4; val_offset:1744*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1744*FLEN/8, x6, x1, x2) + +inst_898: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x165 and fs2 == 1 and fe2 == 0x05 and fm2 == 0x1ed and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7965; op2val:0x95ed; + valaddr_reg:x4; val_offset:1746*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1746*FLEN/8, x6, x1, x2) + +inst_899: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x165 and fs2 == 1 and fe2 == 0x05 and fm2 == 0x1ed and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7965; op2val:0x95ed; + valaddr_reg:x4; val_offset:1748*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1748*FLEN/8, x6, x1, x2) + +inst_900: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e8 and fs2 == 1 and fe2 == 0x05 and fm2 == 0x0a1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ae8; op2val:0x94a1; + valaddr_reg:x4; val_offset:1750*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1750*FLEN/8, x6, x1, x2) + +inst_901: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e8 and fs2 == 1 and fe2 == 0x05 and fm2 == 0x0a1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ae8; op2val:0x94a1; + valaddr_reg:x4; val_offset:1752*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1752*FLEN/8, x6, x1, x2) + +inst_902: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e8 and fs2 == 1 and fe2 == 0x05 and fm2 == 0x0a1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ae8; op2val:0x94a1; + valaddr_reg:x4; val_offset:1754*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1754*FLEN/8, x6, x1, x2) + +inst_903: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e8 and fs2 == 1 and fe2 == 0x05 and fm2 == 0x0a1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ae8; op2val:0x94a1; + valaddr_reg:x4; val_offset:1756*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1756*FLEN/8, x6, x1, x2) + +inst_904: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e8 and fs2 == 1 and fe2 == 0x05 and fm2 == 0x0a1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ae8; op2val:0x94a1; + valaddr_reg:x4; val_offset:1758*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1758*FLEN/8, x6, x1, x2) + +inst_905: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x133 and fs2 == 1 and fe2 == 0x07 and fm2 == 0x227 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7133; op2val:0x9e27; + valaddr_reg:x4; val_offset:1760*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1760*FLEN/8, x6, x1, x2) + +inst_906: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x133 and fs2 == 1 and fe2 == 0x07 and fm2 == 0x227 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7133; op2val:0x9e27; + valaddr_reg:x4; val_offset:1762*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1762*FLEN/8, x6, x1, x2) + +inst_907: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x133 and fs2 == 1 and fe2 == 0x07 and fm2 == 0x227 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7133; op2val:0x9e27; + valaddr_reg:x4; val_offset:1764*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1764*FLEN/8, x6, x1, x2) + +inst_908: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x133 and fs2 == 1 and fe2 == 0x07 and fm2 == 0x227 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7133; op2val:0x9e27; + valaddr_reg:x4; val_offset:1766*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1766*FLEN/8, x6, x1, x2) + +inst_909: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x133 and fs2 == 1 and fe2 == 0x07 and fm2 == 0x227 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7133; op2val:0x9e27; + valaddr_reg:x4; val_offset:1768*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1768*FLEN/8, x6, x1, x2) + +inst_910: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x36e and fs2 == 1 and fe2 == 0x06 and fm2 == 0x04e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x776e; op2val:0x984e; + valaddr_reg:x4; val_offset:1770*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1770*FLEN/8, x6, x1, x2) + +inst_911: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x36e and fs2 == 1 and fe2 == 0x06 and fm2 == 0x04e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x776e; op2val:0x984e; + valaddr_reg:x4; val_offset:1772*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1772*FLEN/8, x6, x1, x2) + +inst_912: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x36e and fs2 == 1 and fe2 == 0x06 and fm2 == 0x04e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x776e; op2val:0x984e; + valaddr_reg:x4; val_offset:1774*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1774*FLEN/8, x6, x1, x2) + +inst_913: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x36e and fs2 == 1 and fe2 == 0x06 and fm2 == 0x04e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x776e; op2val:0x984e; + valaddr_reg:x4; val_offset:1776*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1776*FLEN/8, x6, x1, x2) + +inst_914: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x36e and fs2 == 1 and fe2 == 0x06 and fm2 == 0x04e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x776e; op2val:0x984e; + valaddr_reg:x4; val_offset:1778*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1778*FLEN/8, x6, x1, x2) + +inst_915: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x154 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6154; op2val:0xae00; + valaddr_reg:x4; val_offset:1780*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1780*FLEN/8, x6, x1, x2) + +inst_916: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x154 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x200 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6154; op2val:0xae00; + valaddr_reg:x4; val_offset:1782*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1782*FLEN/8, x6, x1, x2) + +inst_917: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x154 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x200 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6154; op2val:0xae00; + valaddr_reg:x4; val_offset:1784*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1784*FLEN/8, x6, x1, x2) + +inst_918: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x154 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x200 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6154; op2val:0xae00; + valaddr_reg:x4; val_offset:1786*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1786*FLEN/8, x6, x1, x2) + +inst_919: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x154 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x200 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6154; op2val:0xae00; + valaddr_reg:x4; val_offset:1788*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1788*FLEN/8, x6, x1, x2) + +inst_920: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3bb and fs2 == 1 and fe2 == 0x05 and fm2 == 0x023 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bbb; op2val:0x9423; + valaddr_reg:x4; val_offset:1790*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1790*FLEN/8, x6, x1, x2) + +inst_921: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3bb and fs2 == 1 and fe2 == 0x05 and fm2 == 0x023 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bbb; op2val:0x9423; + valaddr_reg:x4; val_offset:1792*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1792*FLEN/8, x6, x1, x2) + +inst_922: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3bb and fs2 == 1 and fe2 == 0x05 and fm2 == 0x023 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bbb; op2val:0x9423; + valaddr_reg:x4; val_offset:1794*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1794*FLEN/8, x6, x1, x2) + +inst_923: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3bb and fs2 == 1 and fe2 == 0x05 and fm2 == 0x023 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bbb; op2val:0x9423; + valaddr_reg:x4; val_offset:1796*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1796*FLEN/8, x6, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_7) + +inst_924: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3bb and fs2 == 1 and fe2 == 0x05 and fm2 == 0x023 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bbb; op2val:0x9423; + valaddr_reg:x4; val_offset:1798*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1798*FLEN/8, x6, x1, x2) + +inst_925: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04d and fs2 == 1 and fe2 == 0x05 and fm2 == 0x370 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x784d; op2val:0x9770; + valaddr_reg:x4; val_offset:1800*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1800*FLEN/8, x6, x1, x2) + +inst_926: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04d and fs2 == 1 and fe2 == 0x05 and fm2 == 0x370 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x784d; op2val:0x9770; + valaddr_reg:x4; val_offset:1802*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1802*FLEN/8, x6, x1, x2) + +inst_927: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04d and fs2 == 1 and fe2 == 0x05 and fm2 == 0x370 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x784d; op2val:0x9770; + valaddr_reg:x4; val_offset:1804*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1804*FLEN/8, x6, x1, x2) + +inst_928: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04d and fs2 == 1 and fe2 == 0x05 and fm2 == 0x370 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x784d; op2val:0x9770; + valaddr_reg:x4; val_offset:1806*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1806*FLEN/8, x6, x1, x2) + +inst_929: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04d and fs2 == 1 and fe2 == 0x05 and fm2 == 0x370 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x784d; op2val:0x9770; + valaddr_reg:x4; val_offset:1808*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1808*FLEN/8, x6, x1, x2) + +inst_930: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x314 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x084 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7714; op2val:0x9884; + valaddr_reg:x4; val_offset:1810*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1810*FLEN/8, x6, x1, x2) + +inst_931: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x314 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x084 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7714; op2val:0x9884; + valaddr_reg:x4; val_offset:1812*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1812*FLEN/8, x6, x1, x2) + +inst_932: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x314 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x084 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7714; op2val:0x9884; + valaddr_reg:x4; val_offset:1814*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1814*FLEN/8, x6, x1, x2) + +inst_933: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x314 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x084 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7714; op2val:0x9884; + valaddr_reg:x4; val_offset:1816*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1816*FLEN/8, x6, x1, x2) + +inst_934: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x314 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x084 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7714; op2val:0x9884; + valaddr_reg:x4; val_offset:1818*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1818*FLEN/8, x6, x1, x2) + +inst_935: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ee and fs2 == 0 and fe2 == 0x06 and fm2 == 0x27c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x74ee; op2val:0x1a7c; + valaddr_reg:x4; val_offset:1820*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1820*FLEN/8, x6, x1, x2) + +inst_936: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ee and fs2 == 0 and fe2 == 0x06 and fm2 == 0x27c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x74ee; op2val:0x1a7c; + valaddr_reg:x4; val_offset:1822*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1822*FLEN/8, x6, x1, x2) + +inst_937: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ee and fs2 == 0 and fe2 == 0x06 and fm2 == 0x27c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x74ee; op2val:0x1a7c; + valaddr_reg:x4; val_offset:1824*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1824*FLEN/8, x6, x1, x2) + +inst_938: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ee and fs2 == 0 and fe2 == 0x06 and fm2 == 0x27c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x74ee; op2val:0x1a7c; + valaddr_reg:x4; val_offset:1826*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1826*FLEN/8, x6, x1, x2) + +inst_939: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ee and fs2 == 0 and fe2 == 0x06 and fm2 == 0x27c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x74ee; op2val:0x1a7c; + valaddr_reg:x4; val_offset:1828*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1828*FLEN/8, x6, x1, x2) + +inst_940: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3bc and fs2 == 0 and fe2 == 0x06 and fm2 == 0x022 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x77bc; op2val:0x1822; + valaddr_reg:x4; val_offset:1830*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1830*FLEN/8, x6, x1, x2) + +inst_941: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3bc and fs2 == 0 and fe2 == 0x06 and fm2 == 0x022 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x77bc; op2val:0x1822; + valaddr_reg:x4; val_offset:1832*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1832*FLEN/8, x6, x1, x2) + +inst_942: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3bc and fs2 == 0 and fe2 == 0x06 and fm2 == 0x022 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x77bc; op2val:0x1822; + valaddr_reg:x4; val_offset:1834*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1834*FLEN/8, x6, x1, x2) + +inst_943: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3bc and fs2 == 0 and fe2 == 0x06 and fm2 == 0x022 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x77bc; op2val:0x1822; + valaddr_reg:x4; val_offset:1836*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1836*FLEN/8, x6, x1, x2) + +inst_944: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3bc and fs2 == 0 and fe2 == 0x06 and fm2 == 0x022 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x77bc; op2val:0x1822; + valaddr_reg:x4; val_offset:1838*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1838*FLEN/8, x6, x1, x2) + +inst_945: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x350 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x060 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b50; op2val:0x1460; + valaddr_reg:x4; val_offset:1840*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1840*FLEN/8, x6, x1, x2) + +inst_946: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x350 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x060 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b50; op2val:0x1460; + valaddr_reg:x4; val_offset:1842*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1842*FLEN/8, x6, x1, x2) + +inst_947: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x350 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x060 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b50; op2val:0x1460; + valaddr_reg:x4; val_offset:1844*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1844*FLEN/8, x6, x1, x2) + +inst_948: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x350 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x060 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b50; op2val:0x1460; + valaddr_reg:x4; val_offset:1846*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1846*FLEN/8, x6, x1, x2) + +inst_949: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x350 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x060 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b50; op2val:0x1460; + valaddr_reg:x4; val_offset:1848*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1848*FLEN/8, x6, x1, x2) + +inst_950: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x297 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x0da and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a97; op2val:0x14da; + valaddr_reg:x4; val_offset:1850*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1850*FLEN/8, x6, x1, x2) + +inst_951: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x297 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x0da and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a97; op2val:0x14da; + valaddr_reg:x4; val_offset:1852*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1852*FLEN/8, x6, x1, x2) + +inst_952: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x297 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x0da and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a97; op2val:0x14da; + valaddr_reg:x4; val_offset:1854*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1854*FLEN/8, x6, x1, x2) + +inst_953: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x297 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x0da and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a97; op2val:0x14da; + valaddr_reg:x4; val_offset:1856*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1856*FLEN/8, x6, x1, x2) + +inst_954: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x297 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x0da and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a97; op2val:0x14da; + valaddr_reg:x4; val_offset:1858*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1858*FLEN/8, x6, x1, x2) + +inst_955: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12b and fs2 == 0 and fe2 == 0x05 and fm2 == 0x231 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x792b; op2val:0x1631; + valaddr_reg:x4; val_offset:1860*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1860*FLEN/8, x6, x1, x2) + +inst_956: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12b and fs2 == 0 and fe2 == 0x05 and fm2 == 0x231 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x792b; op2val:0x1631; + valaddr_reg:x4; val_offset:1862*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1862*FLEN/8, x6, x1, x2) + +inst_957: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12b and fs2 == 0 and fe2 == 0x05 and fm2 == 0x231 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x792b; op2val:0x1631; + valaddr_reg:x4; val_offset:1864*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1864*FLEN/8, x6, x1, x2) + +inst_958: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12b and fs2 == 0 and fe2 == 0x05 and fm2 == 0x231 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x792b; op2val:0x1631; + valaddr_reg:x4; val_offset:1866*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1866*FLEN/8, x6, x1, x2) + +inst_959: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12b and fs2 == 0 and fe2 == 0x05 and fm2 == 0x231 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x792b; op2val:0x1631; + valaddr_reg:x4; val_offset:1868*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1868*FLEN/8, x6, x1, x2) + +inst_960: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x139 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x21f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7939; op2val:0x161f; + valaddr_reg:x4; val_offset:1870*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1870*FLEN/8, x6, x1, x2) + +inst_961: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x139 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x21f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7939; op2val:0x161f; + valaddr_reg:x4; val_offset:1872*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1872*FLEN/8, x6, x1, x2) + +inst_962: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x139 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x21f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7939; op2val:0x161f; + valaddr_reg:x4; val_offset:1874*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1874*FLEN/8, x6, x1, x2) + +inst_963: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x139 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x21f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7939; op2val:0x161f; + valaddr_reg:x4; val_offset:1876*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1876*FLEN/8, x6, x1, x2) + +inst_964: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x139 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x21f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7939; op2val:0x161f; + valaddr_reg:x4; val_offset:1878*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1878*FLEN/8, x6, x1, x2) + +inst_965: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b8 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x0c2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab8; op2val:0x14c2; + valaddr_reg:x4; val_offset:1880*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1880*FLEN/8, x6, x1, x2) + +inst_966: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b8 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x0c2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab8; op2val:0x14c2; + valaddr_reg:x4; val_offset:1882*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1882*FLEN/8, x6, x1, x2) + +inst_967: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b8 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x0c2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab8; op2val:0x14c2; + valaddr_reg:x4; val_offset:1884*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1884*FLEN/8, x6, x1, x2) + +inst_968: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b8 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x0c2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab8; op2val:0x14c2; + valaddr_reg:x4; val_offset:1886*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1886*FLEN/8, x6, x1, x2) + +inst_969: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b8 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x0c2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab8; op2val:0x14c2; + valaddr_reg:x4; val_offset:1888*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1888*FLEN/8, x6, x1, x2) + +inst_970: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x110 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7910; op2val:0xc; + valaddr_reg:x4; val_offset:1890*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1890*FLEN/8, x6, x1, x2) + +inst_971: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x110 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7910; op2val:0xc; + valaddr_reg:x4; val_offset:1892*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1892*FLEN/8, x6, x1, x2) + +inst_972: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x110 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7910; op2val:0xc; + valaddr_reg:x4; val_offset:1894*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1894*FLEN/8, x6, x1, x2) + +inst_973: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x110 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7910; op2val:0xc; + valaddr_reg:x4; val_offset:1896*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1896*FLEN/8, x6, x1, x2) + +inst_974: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x110 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7910; op2val:0xc; + valaddr_reg:x4; val_offset:1898*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1898*FLEN/8, x6, x1, x2) + +inst_975: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x03d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x783d; op2val:0xf; + valaddr_reg:x4; val_offset:1900*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1900*FLEN/8, x6, x1, x2) + +inst_976: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x03d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x783d; op2val:0xf; + valaddr_reg:x4; val_offset:1902*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1902*FLEN/8, x6, x1, x2) + +inst_977: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x03d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x783d; op2val:0xf; + valaddr_reg:x4; val_offset:1904*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1904*FLEN/8, x6, x1, x2) + +inst_978: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x03d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x783d; op2val:0xf; + valaddr_reg:x4; val_offset:1906*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1906*FLEN/8, x6, x1, x2) + +inst_979: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x03d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x783d; op2val:0xf; + valaddr_reg:x4; val_offset:1908*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1908*FLEN/8, x6, x1, x2) + +inst_980: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x261 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a61; op2val:0xa; + valaddr_reg:x4; val_offset:1910*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1910*FLEN/8, x6, x1, x2) + +inst_981: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x261 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a61; op2val:0xa; + valaddr_reg:x4; val_offset:1912*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1912*FLEN/8, x6, x1, x2) + +inst_982: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x261 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a61; op2val:0xa; + valaddr_reg:x4; val_offset:1914*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1914*FLEN/8, x6, x1, x2) + +inst_983: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x261 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a61; op2val:0xa; + valaddr_reg:x4; val_offset:1916*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1916*FLEN/8, x6, x1, x2) + +inst_984: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x261 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a61; op2val:0xa; + valaddr_reg:x4; val_offset:1918*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1918*FLEN/8, x6, x1, x2) + +inst_985: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x019 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x74ed; op2val:0x19; + valaddr_reg:x4; val_offset:1920*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1920*FLEN/8, x6, x1, x2) + +inst_986: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x019 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x74ed; op2val:0x19; + valaddr_reg:x4; val_offset:1922*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1922*FLEN/8, x6, x1, x2) + +inst_987: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x019 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x74ed; op2val:0x19; + valaddr_reg:x4; val_offset:1924*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1924*FLEN/8, x6, x1, x2) + +inst_988: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x019 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x74ed; op2val:0x19; + valaddr_reg:x4; val_offset:1926*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1926*FLEN/8, x6, x1, x2) + +inst_989: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x019 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x74ed; op2val:0x19; + valaddr_reg:x4; val_offset:1928*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1928*FLEN/8, x6, x1, x2) + +inst_990: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x351 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x011 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7751; op2val:0x11; + valaddr_reg:x4; val_offset:1930*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1930*FLEN/8, x6, x1, x2) + +inst_991: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x351 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x011 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7751; op2val:0x11; + valaddr_reg:x4; val_offset:1932*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1932*FLEN/8, x6, x1, x2) + +inst_992: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x351 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x011 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7751; op2val:0x11; + valaddr_reg:x4; val_offset:1934*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1934*FLEN/8, x6, x1, x2) + +inst_993: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x351 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x011 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7751; op2val:0x11; + valaddr_reg:x4; val_offset:1936*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1936*FLEN/8, x6, x1, x2) + +inst_994: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x351 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x011 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7751; op2val:0x11; + valaddr_reg:x4; val_offset:1938*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1938*FLEN/8, x6, x1, x2) + +inst_995: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x070 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x01c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7470; op2val:0x1c; + valaddr_reg:x4; val_offset:1940*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1940*FLEN/8, x6, x1, x2) + +inst_996: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x070 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x01c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7470; op2val:0x1c; + valaddr_reg:x4; val_offset:1942*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1942*FLEN/8, x6, x1, x2) + +inst_997: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x070 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x01c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7470; op2val:0x1c; + valaddr_reg:x4; val_offset:1944*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1944*FLEN/8, x6, x1, x2) + +inst_998: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x070 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x01c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7470; op2val:0x1c; + valaddr_reg:x4; val_offset:1946*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1946*FLEN/8, x6, x1, x2) + +inst_999: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x070 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x01c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7470; op2val:0x1c; + valaddr_reg:x4; val_offset:1948*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1948*FLEN/8, x6, x1, x2) + +inst_1000: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x329 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x047 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f29; op2val:0x47; + valaddr_reg:x4; val_offset:1950*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1950*FLEN/8, x6, x1, x2) + +inst_1001: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x329 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x047 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f29; op2val:0x47; + valaddr_reg:x4; val_offset:1952*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1952*FLEN/8, x6, x1, x2) + +inst_1002: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x329 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x047 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f29; op2val:0x47; + valaddr_reg:x4; val_offset:1954*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1954*FLEN/8, x6, x1, x2) + +inst_1003: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x329 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x047 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f29; op2val:0x47; + valaddr_reg:x4; val_offset:1956*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1956*FLEN/8, x6, x1, x2) + +inst_1004: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x329 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x047 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f29; op2val:0x47; + valaddr_reg:x4; val_offset:1958*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1958*FLEN/8, x6, x1, x2) + +inst_1005: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x210 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x015 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7610; op2val:0x8015; + valaddr_reg:x4; val_offset:1960*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1960*FLEN/8, x6, x1, x2) + +inst_1006: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x210 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x015 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7610; op2val:0x8015; + valaddr_reg:x4; val_offset:1962*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1962*FLEN/8, x6, x1, x2) + +inst_1007: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x210 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x015 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7610; op2val:0x8015; + valaddr_reg:x4; val_offset:1964*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1964*FLEN/8, x6, x1, x2) + +inst_1008: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x210 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x015 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7610; op2val:0x8015; + valaddr_reg:x4; val_offset:1966*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1966*FLEN/8, x6, x1, x2) + +inst_1009: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x210 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x015 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7610; op2val:0x8015; + valaddr_reg:x4; val_offset:1968*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1968*FLEN/8, x6, x1, x2) + +inst_1010: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x117 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x019 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7517; op2val:0x8019; + valaddr_reg:x4; val_offset:1970*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1970*FLEN/8, x6, x1, x2) + +inst_1011: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x117 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x019 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7517; op2val:0x8019; + valaddr_reg:x4; val_offset:1972*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1972*FLEN/8, x6, x1, x2) + +inst_1012: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x117 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x019 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7517; op2val:0x8019; + valaddr_reg:x4; val_offset:1974*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1974*FLEN/8, x6, x1, x2) + +inst_1013: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x117 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x019 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7517; op2val:0x8019; + valaddr_reg:x4; val_offset:1976*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1976*FLEN/8, x6, x1, x2) + +inst_1014: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x117 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x019 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7517; op2val:0x8019; + valaddr_reg:x4; val_offset:1978*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1978*FLEN/8, x6, x1, x2) + +inst_1015: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x350 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x011 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7750; op2val:0x8011; + valaddr_reg:x4; val_offset:1980*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1980*FLEN/8, x6, x1, x2) + +inst_1016: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x350 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x011 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7750; op2val:0x8011; + valaddr_reg:x4; val_offset:1982*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1982*FLEN/8, x6, x1, x2) + +inst_1017: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x350 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x011 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7750; op2val:0x8011; + valaddr_reg:x4; val_offset:1984*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1984*FLEN/8, x6, x1, x2) + +inst_1018: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x350 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x011 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7750; op2val:0x8011; + valaddr_reg:x4; val_offset:1986*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1986*FLEN/8, x6, x1, x2) + +inst_1019: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x350 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x011 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7750; op2val:0x8011; + valaddr_reg:x4; val_offset:1988*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1988*FLEN/8, x6, x1, x2) + +inst_1020: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x311 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x012 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7711; op2val:0x8012; + valaddr_reg:x4; val_offset:1990*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 1990*FLEN/8, x6, x1, x2) + +inst_1021: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x311 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x012 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7711; op2val:0x8012; + valaddr_reg:x4; val_offset:1992*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 1992*FLEN/8, x6, x1, x2) + +inst_1022: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x311 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x012 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7711; op2val:0x8012; + valaddr_reg:x4; val_offset:1994*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 1994*FLEN/8, x6, x1, x2) + +inst_1023: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x311 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x012 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7711; op2val:0x8012; + valaddr_reg:x4; val_offset:1996*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 1996*FLEN/8, x6, x1, x2) + +inst_1024: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x311 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x012 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7711; op2val:0x8012; + valaddr_reg:x4; val_offset:1998*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 1998*FLEN/8, x6, x1, x2) + +inst_1025: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x327 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x008 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b27; op2val:0x8008; + valaddr_reg:x4; val_offset:2000*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 2000*FLEN/8, x6, x1, x2) + +inst_1026: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x327 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x008 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b27; op2val:0x8008; + valaddr_reg:x4; val_offset:2002*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 2002*FLEN/8, x6, x1, x2) + +inst_1027: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x327 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x008 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b27; op2val:0x8008; + valaddr_reg:x4; val_offset:2004*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 2004*FLEN/8, x6, x1, x2) + +inst_1028: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x327 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x008 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b27; op2val:0x8008; + valaddr_reg:x4; val_offset:2006*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 2006*FLEN/8, x6, x1, x2) + +inst_1029: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x327 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x008 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b27; op2val:0x8008; + valaddr_reg:x4; val_offset:2008*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 2008*FLEN/8, x6, x1, x2) + +inst_1030: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x36e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x008 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b6e; op2val:0x8008; + valaddr_reg:x4; val_offset:2010*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 2010*FLEN/8, x6, x1, x2) + +inst_1031: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x36e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x008 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b6e; op2val:0x8008; + valaddr_reg:x4; val_offset:2012*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 2012*FLEN/8, x6, x1, x2) + +inst_1032: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x36e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x008 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b6e; op2val:0x8008; + valaddr_reg:x4; val_offset:2014*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 2014*FLEN/8, x6, x1, x2) + +inst_1033: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x36e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x008 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b6e; op2val:0x8008; + valaddr_reg:x4; val_offset:2016*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 2016*FLEN/8, x6, x1, x2) + +inst_1034: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x36e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x008 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b6e; op2val:0x8008; + valaddr_reg:x4; val_offset:2018*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 2018*FLEN/8, x6, x1, x2) + +inst_1035: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x25e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x050 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e5e; op2val:0x8050; + valaddr_reg:x4; val_offset:2020*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 2020*FLEN/8, x6, x1, x2) + +inst_1036: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x25e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x050 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e5e; op2val:0x8050; + valaddr_reg:x4; val_offset:2022*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 2022*FLEN/8, x6, x1, x2) + +inst_1037: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x25e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x050 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e5e; op2val:0x8050; + valaddr_reg:x4; val_offset:2024*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 2024*FLEN/8, x6, x1, x2) + +inst_1038: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x25e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x050 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e5e; op2val:0x8050; + valaddr_reg:x4; val_offset:2026*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 2026*FLEN/8, x6, x1, x2) + +inst_1039: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x25e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x050 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e5e; op2val:0x8050; + valaddr_reg:x4; val_offset:2028*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 2028*FLEN/8, x6, x1, x2) + +inst_1040: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x210 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x02a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7210; op2val:0x802a; + valaddr_reg:x4; val_offset:2030*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 2030*FLEN/8, x6, x1, x2) + +inst_1041: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x210 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x02a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7210; op2val:0x802a; + valaddr_reg:x4; val_offset:2032*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 2032*FLEN/8, x6, x1, x2) + +inst_1042: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x210 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x02a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7210; op2val:0x802a; + valaddr_reg:x4; val_offset:2034*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 2034*FLEN/8, x6, x1, x2) + +inst_1043: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x210 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x02a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7210; op2val:0x802a; + valaddr_reg:x4; val_offset:2036*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 2036*FLEN/8, x6, x1, x2) + +inst_1044: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x210 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x02a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7210; op2val:0x802a; + valaddr_reg:x4; val_offset:2038*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 2038*FLEN/8, x6, x1, x2) + +inst_1045: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1fa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x015 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x75fa; op2val:0x8015; + valaddr_reg:x4; val_offset:2040*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 2040*FLEN/8, x6, x1, x2) + +inst_1046: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1fa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x015 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x75fa; op2val:0x8015; + valaddr_reg:x4; val_offset:2042*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 2042*FLEN/8, x6, x1, x2) + +inst_1047: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1fa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x015 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x75fa; op2val:0x8015; + valaddr_reg:x4; val_offset:2044*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 2044*FLEN/8, x6, x1, x2) + +inst_1048: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1fa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x015 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x75fa; op2val:0x8015; + valaddr_reg:x4; val_offset:2046*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 2046*FLEN/8, x6, x1, x2) + +inst_1049: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1fa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x015 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x75fa; op2val:0x8015; + valaddr_reg:x4; val_offset:2048*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 2048*FLEN/8, x6, x1, x2) + +inst_1050: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a5b; op2val:0x800a; + valaddr_reg:x4; val_offset:2050*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 2050*FLEN/8, x6, x1, x2) + +inst_1051: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a5b; op2val:0x800a; + valaddr_reg:x4; val_offset:2052*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 2052*FLEN/8, x6, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_8) + +inst_1052: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a5b; op2val:0x800a; + valaddr_reg:x4; val_offset:2054*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 2054*FLEN/8, x6, x1, x2) + +inst_1053: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a5b; op2val:0x800a; + valaddr_reg:x4; val_offset:2056*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 2056*FLEN/8, x6, x1, x2) + +inst_1054: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a5b; op2val:0x800a; + valaddr_reg:x4; val_offset:2058*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 2058*FLEN/8, x6, x1, x2) + +inst_1055: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x277 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x009 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a77; op2val:0x8009; + valaddr_reg:x4; val_offset:2060*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 2060*FLEN/8, x6, x1, x2) + +inst_1056: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x277 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x009 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a77; op2val:0x8009; + valaddr_reg:x4; val_offset:2062*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 2062*FLEN/8, x6, x1, x2) + +inst_1057: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x277 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x009 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a77; op2val:0x8009; + valaddr_reg:x4; val_offset:2064*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 2064*FLEN/8, x6, x1, x2) + +inst_1058: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x277 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x009 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a77; op2val:0x8009; + valaddr_reg:x4; val_offset:2066*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 2066*FLEN/8, x6, x1, x2) + +inst_1059: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x277 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x009 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a77; op2val:0x8009; + valaddr_reg:x4; val_offset:2068*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 2068*FLEN/8, x6, x1, x2) + +inst_1060: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x266 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x013 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7666; op2val:0x8013; + valaddr_reg:x4; val_offset:2070*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 2070*FLEN/8, x6, x1, x2) + +inst_1061: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x266 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x013 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7666; op2val:0x8013; + valaddr_reg:x4; val_offset:2072*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 2072*FLEN/8, x6, x1, x2) + +inst_1062: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x266 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x013 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7666; op2val:0x8013; + valaddr_reg:x4; val_offset:2074*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 2074*FLEN/8, x6, x1, x2) + +inst_1063: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x266 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x013 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7666; op2val:0x8013; + valaddr_reg:x4; val_offset:2076*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 2076*FLEN/8, x6, x1, x2) + +inst_1064: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x266 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x013 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7666; op2val:0x8013; + valaddr_reg:x4; val_offset:2078*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 2078*FLEN/8, x6, x1, x2) + +inst_1065: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x179 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x017 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7579; op2val:0x8017; + valaddr_reg:x4; val_offset:2080*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 2080*FLEN/8, x6, x1, x2) + +inst_1066: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x179 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x017 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7579; op2val:0x8017; + valaddr_reg:x4; val_offset:2082*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 2082*FLEN/8, x6, x1, x2) + +inst_1067: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x179 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x017 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7579; op2val:0x8017; + valaddr_reg:x4; val_offset:2084*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 2084*FLEN/8, x6, x1, x2) + +inst_1068: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x179 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x017 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7579; op2val:0x8017; + valaddr_reg:x4; val_offset:2086*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 2086*FLEN/8, x6, x1, x2) + +inst_1069: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x179 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x017 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7579; op2val:0x8017; + valaddr_reg:x4; val_offset:2088*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 2088*FLEN/8, x6, x1, x2) + +inst_1070: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x367 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x008 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b67; op2val:0x8; + valaddr_reg:x4; val_offset:2090*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 2090*FLEN/8, x6, x1, x2) + +inst_1071: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x367 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x008 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b67; op2val:0x8; + valaddr_reg:x4; val_offset:2092*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 2092*FLEN/8, x6, x1, x2) + +inst_1072: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x367 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x008 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b67; op2val:0x8; + valaddr_reg:x4; val_offset:2094*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 2094*FLEN/8, x6, x1, x2) + +inst_1073: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x367 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x008 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b67; op2val:0x8; + valaddr_reg:x4; val_offset:2096*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 2096*FLEN/8, x6, x1, x2) + +inst_1074: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x367 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x008 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b67; op2val:0x8; + valaddr_reg:x4; val_offset:2098*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 2098*FLEN/8, x6, x1, x2) + +inst_1075: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x184 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7984; op2val:0xb; + valaddr_reg:x4; val_offset:2100*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 2100*FLEN/8, x6, x1, x2) + +inst_1076: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x184 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7984; op2val:0xb; + valaddr_reg:x4; val_offset:2102*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 2102*FLEN/8, x6, x1, x2) + +inst_1077: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x184 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7984; op2val:0xb; + valaddr_reg:x4; val_offset:2104*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 2104*FLEN/8, x6, x1, x2) + +inst_1078: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x184 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7984; op2val:0xb; + valaddr_reg:x4; val_offset:2106*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 2106*FLEN/8, x6, x1, x2) + +inst_1079: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x184 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7984; op2val:0xb; + valaddr_reg:x4; val_offset:2108*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 2108*FLEN/8, x6, x1, x2) + +inst_1080: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79f0; op2val:0xa; + valaddr_reg:x4; val_offset:2110*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 2110*FLEN/8, x6, x1, x2) + +inst_1081: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79f0; op2val:0xa; + valaddr_reg:x4; val_offset:2112*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 2112*FLEN/8, x6, x1, x2) + +inst_1082: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79f0; op2val:0xa; + valaddr_reg:x4; val_offset:2114*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 2114*FLEN/8, x6, x1, x2) + +inst_1083: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79f0; op2val:0xa; + valaddr_reg:x4; val_offset:2116*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 2116*FLEN/8, x6, x1, x2) + +inst_1084: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79f0; op2val:0xa; + valaddr_reg:x4; val_offset:2118*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 2118*FLEN/8, x6, x1, x2) + +inst_1085: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x009 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7af3; op2val:0x9; + valaddr_reg:x4; val_offset:2120*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 2120*FLEN/8, x6, x1, x2) + +inst_1086: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x009 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7af3; op2val:0x9; + valaddr_reg:x4; val_offset:2122*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 2122*FLEN/8, x6, x1, x2) + +inst_1087: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x009 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7af3; op2val:0x9; + valaddr_reg:x4; val_offset:2124*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 2124*FLEN/8, x6, x1, x2) + +inst_1088: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x009 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7af3; op2val:0x9; + valaddr_reg:x4; val_offset:2126*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 2126*FLEN/8, x6, x1, x2) + +inst_1089: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x009 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7af3; op2val:0x9; + valaddr_reg:x4; val_offset:2128*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 2128*FLEN/8, x6, x1, x2) + +inst_1090: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x206 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a06; op2val:0xa; + valaddr_reg:x4; val_offset:2130*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 2130*FLEN/8, x6, x1, x2) + +inst_1091: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x206 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a06; op2val:0xa; + valaddr_reg:x4; val_offset:2132*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 2132*FLEN/8, x6, x1, x2) + +inst_1092: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x206 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a06; op2val:0xa; + valaddr_reg:x4; val_offset:2134*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 2134*FLEN/8, x6, x1, x2) + +inst_1093: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x206 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a06; op2val:0xa; + valaddr_reg:x4; val_offset:2136*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 2136*FLEN/8, x6, x1, x2) + +inst_1094: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x206 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a06; op2val:0xa; + valaddr_reg:x4; val_offset:2138*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 2138*FLEN/8, x6, x1, x2) + +inst_1095: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x01b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x74a9; op2val:0x1b; + valaddr_reg:x4; val_offset:2140*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 2140*FLEN/8, x6, x1, x2) + +inst_1096: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x01b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x74a9; op2val:0x1b; + valaddr_reg:x4; val_offset:2142*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 2142*FLEN/8, x6, x1, x2) + +inst_1097: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x01b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x74a9; op2val:0x1b; + valaddr_reg:x4; val_offset:2144*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 2144*FLEN/8, x6, x1, x2) + +inst_1098: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x01b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x74a9; op2val:0x1b; + valaddr_reg:x4; val_offset:2146*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 2146*FLEN/8, x6, x1, x2) + +inst_1099: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x01b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x74a9; op2val:0x1b; + valaddr_reg:x4; val_offset:2148*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 2148*FLEN/8, x6, x1, x2) + +inst_1100: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x795c; op2val:0xb; + valaddr_reg:x4; val_offset:2150*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 2150*FLEN/8, x6, x1, x2) + +inst_1101: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x795c; op2val:0xb; + valaddr_reg:x4; val_offset:2152*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 2152*FLEN/8, x6, x1, x2) + +inst_1102: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x795c; op2val:0xb; + valaddr_reg:x4; val_offset:2154*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 2154*FLEN/8, x6, x1, x2) + +inst_1103: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x795c; op2val:0xb; + valaddr_reg:x4; val_offset:2156*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 2156*FLEN/8, x6, x1, x2) + +inst_1104: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x795c; op2val:0xb; + valaddr_reg:x4; val_offset:2158*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 2158*FLEN/8, x6, x1, x2) + +inst_1105: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba5; op2val:0x0; + valaddr_reg:x4; val_offset:2160*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 2160*FLEN/8, x6, x1, x2) + +inst_1106: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba5; op2val:0x0; + valaddr_reg:x4; val_offset:2162*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 2162*FLEN/8, x6, x1, x2) + +inst_1107: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aae; op2val:0x0; + valaddr_reg:x4; val_offset:2164*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 2164*FLEN/8, x6, x1, x2) + +inst_1108: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x795a; op2val:0x0; + valaddr_reg:x4; val_offset:2166*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 2166*FLEN/8, x6, x1, x2) + +inst_1109: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x76e3; op2val:0x0; + valaddr_reg:x4; val_offset:2168*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 2168*FLEN/8, x6, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(27452,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(27452,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(27452,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(27452,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(27452,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31406,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31406,32,FLEN) +NAN_BOXED(0,32,FLEN) +test_dataset_1: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31406,32,FLEN) +NAN_BOXED(0,32,FLEN) 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0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_1: + .fill 30*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x14_0: + .fill 26*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_0: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_2: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_3: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_4: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_5: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_6: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_7: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_8: + .fill 116*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fmul_b4-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fmul_b4-01.S new file mode 100644 index 000000000..fc56bd77a --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fmul_b4-01.S @@ -0,0 +1,1549 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 04:50:26 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fmul.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fmul.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fmul_b4 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fmul_b4) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x10,test_dataset_0) +RVTEST_SIGBASE(x2,signature_x2_1) + +inst_0: +// rs1 == rd != rs2, rs1==x1, rs2==x17, rd==x1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x02f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x1; op2:x17; dest:x1; op1val:0x7ba5; op2val:0x3c2f; + valaddr_reg:x10; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x15 +*/ +TEST_FPRR_OP(fmul.h, x1, x1, x17, dyn, 0, 0, x10, 0*FLEN/8, x11, x2, x15) + +inst_1: +// rs1 == rs2 == rd, rs1==x5, rs2==x5, rd==x5,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x02f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x5; op2:x5; dest:x5; op1val:0x7ba5; op2val:0x7ba5; + valaddr_reg:x10; val_offset:2*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x15 +*/ +TEST_FPRR_OP(fmul.h, x5, x5, x5, dyn, 32, 0, x10, 2*FLEN/8, x11, x2, x15) + +inst_2: +// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==x24, rs2==x23, rd==x29,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x02f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x24; op2:x23; dest:x29; op1val:0x7ba5; op2val:0x3c2f; + valaddr_reg:x10; val_offset:4*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x15 +*/ +TEST_FPRR_OP(fmul.h, x29, x24, x23, dyn, 64, 0, x10, 4*FLEN/8, x11, x2, x15) + +inst_3: +// rs1 == rs2 != rd, rs1==x19, rs2==x19, rd==x4,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x02f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x19; op2:x19; dest:x4; op1val:0x7ba5; op2val:0x7ba5; + valaddr_reg:x10; val_offset:6*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x15 +*/ +TEST_FPRR_OP(fmul.h, x4, x19, x19, dyn, 96, 0, x10, 6*FLEN/8, x11, x2, x15) + +inst_4: +// rs2 == rd != rs1, rs1==x23, rs2==x13, rd==x13,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x02f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x23; op2:x13; dest:x13; op1val:0x7ba5; op2val:0x3c2f; + valaddr_reg:x10; val_offset:8*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x15 +*/ +TEST_FPRR_OP(fmul.h, x13, x23, x13, dyn, 128, 0, x10, 8*FLEN/8, x11, x2, x15) + +inst_5: +// rs1==x9, rs2==x12, rd==x3,fs1 == 0 and fe1 == 0x1a and fm1 == 0x33c and fs2 == 1 and fe2 == 0x13 and fm2 == 0x06b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x9; op2:x12; dest:x3; op1val:0x6b3c; op2val:0xcc6b; + valaddr_reg:x10; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x15 +*/ +TEST_FPRR_OP(fmul.h, x3, x9, x12, dyn, 0, 0, x10, 10*FLEN/8, x11, x2, x15) + +inst_6: +// rs1==x3, rs2==x6, rd==x25,fs1 == 0 and fe1 == 0x1a and fm1 == 0x33c and fs2 == 1 and fe2 == 0x13 and fm2 == 0x06b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x3; op2:x6; dest:x25; op1val:0x6b3c; op2val:0xcc6b; + valaddr_reg:x10; val_offset:12*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x15 +*/ +TEST_FPRR_OP(fmul.h, x25, x3, x6, dyn, 32, 0, x10, 12*FLEN/8, x11, x2, x15) + +inst_7: +// rs1==x27, rs2==x28, rd==x24,fs1 == 0 and fe1 == 0x1a and fm1 == 0x33c and fs2 == 1 and fe2 == 0x13 and fm2 == 0x06b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x27; op2:x28; dest:x24; op1val:0x6b3c; op2val:0xcc6b; + valaddr_reg:x10; val_offset:14*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x15 +*/ +TEST_FPRR_OP(fmul.h, x24, x27, x28, dyn, 64, 0, x10, 14*FLEN/8, x11, x2, x15) + +inst_8: +// rs1==x14, rs2==x4, rd==x0,fs1 == 0 and fe1 == 0x1a and fm1 == 0x33c and fs2 == 1 and fe2 == 0x13 and fm2 == 0x06b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x14; op2:x4; dest:x0; op1val:0x6b3c; op2val:0xcc6b; + valaddr_reg:x10; val_offset:16*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x15 +*/ +TEST_FPRR_OP(fmul.h, x0, x14, x4, dyn, 96, 0, x10, 16*FLEN/8, x11, x2, x15) + +inst_9: +// rs1==x26, rs2==x25, rd==x28,fs1 == 0 and fe1 == 0x1a and fm1 == 0x33c and fs2 == 1 and fe2 == 0x13 and fm2 == 0x06b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x26; op2:x25; dest:x28; op1val:0x6b3c; op2val:0xcc6b; + valaddr_reg:x10; val_offset:18*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x15 +*/ +TEST_FPRR_OP(fmul.h, x28, x26, x25, dyn, 128, 0, x10, 18*FLEN/8, x11, x2, x15) + +inst_10: +// rs1==x13, rs2==x30, rd==x12,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0c9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x13; op2:x30; dest:x12; op1val:0x7aae; op2val:0x3cc9; + valaddr_reg:x10; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x15 +*/ +TEST_FPRR_OP(fmul.h, x12, x13, x30, dyn, 0, 0, x10, 20*FLEN/8, x11, x2, x15) + +inst_11: +// rs1==x8, rs2==x31, rd==x7,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0c9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x8; op2:x31; dest:x7; op1val:0x7aae; op2val:0x3cc9; + valaddr_reg:x10; val_offset:22*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x15 +*/ +TEST_FPRR_OP(fmul.h, x7, x8, x31, dyn, 32, 0, x10, 22*FLEN/8, x11, x2, x15) + +inst_12: +// rs1==x30, rs2==x27, rd==x17,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0c9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x27; dest:x17; op1val:0x7aae; op2val:0x3cc9; + valaddr_reg:x10; val_offset:24*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x15 +*/ +TEST_FPRR_OP(fmul.h, x17, x30, x27, dyn, 64, 0, x10, 24*FLEN/8, x11, x2, x15) + +inst_13: +// rs1==x31, rs2==x16, rd==x27,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0c9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x31; op2:x16; dest:x27; op1val:0x7aae; op2val:0x3cc9; + valaddr_reg:x10; val_offset:26*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x15 +*/ +TEST_FPRR_OP(fmul.h, x27, x31, x16, dyn, 96, 0, x10, 26*FLEN/8, x11, x2, x15) +RVTEST_VALBASEUPD(x5,test_dataset_1) + +inst_14: +// rs1==x25, rs2==x3, rd==x11,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0c9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x25; op2:x3; dest:x11; op1val:0x7aae; op2val:0x3cc9; + valaddr_reg:x5; val_offset:0*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x15 +*/ +TEST_FPRR_OP(fmul.h, x11, x25, x3, dyn, 128, 0, x5, 0*FLEN/8, x7, x2, x15) + +inst_15: +// rs1==x4, rs2==x1, rd==x10,fs1 == 0 and fe1 == 0x1e and fm1 == 0x15a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x4; op2:x1; dest:x10; op1val:0x795a; op2val:0xbdf8; + valaddr_reg:x5; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x15 +*/ +TEST_FPRR_OP(fmul.h, x10, x4, x1, dyn, 0, 0, x5, 2*FLEN/8, x7, x2, x15) + +inst_16: +// rs1==x28, rs2==x10, rd==x21,fs1 == 0 and fe1 == 0x1e and fm1 == 0x15a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1f8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x28; op2:x10; dest:x21; op1val:0x795a; op2val:0xbdf8; + valaddr_reg:x5; val_offset:4*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x21, x28, x10, dyn, 32, 0, x5, 4*FLEN/8, x7, x2, x3) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_17: +// rs1==x22, rs2==x2, rd==x16,fs1 == 0 and fe1 == 0x1e and fm1 == 0x15a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1f8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x22; op2:x2; dest:x16; op1val:0x795a; op2val:0xbdf8; + valaddr_reg:x5; val_offset:6*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x16, x22, x2, dyn, 64, 0, x5, 6*FLEN/8, x7, x1, x3) + +inst_18: +// rs1==x6, rs2==x22, rd==x26,fs1 == 0 and fe1 == 0x1e and fm1 == 0x15a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1f8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x6; op2:x22; dest:x26; op1val:0x795a; op2val:0xbdf8; + valaddr_reg:x5; val_offset:8*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x26, x6, x22, dyn, 96, 0, x5, 8*FLEN/8, x7, x1, x3) + +inst_19: +// rs1==x16, rs2==x21, rd==x22,fs1 == 0 and fe1 == 0x1e and fm1 == 0x15a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1f8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x16; op2:x21; dest:x22; op1val:0x795a; op2val:0xbdf8; + valaddr_reg:x5; val_offset:10*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x22, x16, x21, dyn, 128, 0, x5, 10*FLEN/8, x7, x1, x3) + +inst_20: +// rs1==x18, rs2==x14, rd==x30,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x299 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x18; op2:x14; dest:x30; op1val:0x78d8; op2val:0x3e99; + valaddr_reg:x5; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x30, x18, x14, dyn, 0, 0, x5, 12*FLEN/8, x7, x1, x3) + +inst_21: +// rs1==x2, rs2==x18, rd==x6,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x299 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x2; op2:x18; dest:x6; op1val:0x78d8; op2val:0x3e99; + valaddr_reg:x5; val_offset:14*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x6, x2, x18, dyn, 32, 0, x5, 14*FLEN/8, x7, x1, x3) + +inst_22: +// rs1==x0, rs2==x9, rd==x18,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x299 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x0; op2:x9; dest:x18; op1val:0x0; op2val:0x3e99; + valaddr_reg:x5; val_offset:16*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x18, x0, x9, dyn, 64, 0, x5, 16*FLEN/8, x7, x1, x3) + +inst_23: +// rs1==x12, rs2==x24, rd==x31,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x299 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x12; op2:x24; dest:x31; op1val:0x78d8; op2val:0x3e99; + valaddr_reg:x5; val_offset:18*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x12, x24, dyn, 96, 0, x5, 18*FLEN/8, x7, x1, x3) + +inst_24: +// rs1==x29, rs2==x20, rd==x23,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x299 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x29; op2:x20; dest:x23; op1val:0x78d8; op2val:0x3e99; + valaddr_reg:x5; val_offset:20*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x23, x29, x20, dyn, 128, 0, x5, 20*FLEN/8, x7, x1, x3) + +inst_25: +// rs1==x20, rs2==x8, rd==x15,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a5 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2e1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x20; op2:x8; dest:x15; op1val:0x78a5; op2val:0xbee1; + valaddr_reg:x5; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x15, x20, x8, dyn, 0, 0, x5, 22*FLEN/8, x7, x1, x3) +RVTEST_VALBASEUPD(x4,test_dataset_2) + +inst_26: +// rs1==x10, rs2==x15, rd==x20,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a5 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2e1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x10; op2:x15; dest:x20; op1val:0x78a5; op2val:0xbee1; + valaddr_reg:x4; val_offset:0*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x20, x10, x15, dyn, 32, 0, x4, 0*FLEN/8, x5, x1, x3) + +inst_27: +// rs1==x17, rs2==x11, rd==x9,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a5 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2e1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x17; op2:x11; dest:x9; op1val:0x78a5; op2val:0xbee1; + valaddr_reg:x4; val_offset:2*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x9, x17, x11, dyn, 64, 0, x4, 2*FLEN/8, x5, x1, x3) + +inst_28: +// rs1==x11, rs2==x29, rd==x2,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a5 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2e1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x11; op2:x29; dest:x2; op1val:0x78a5; op2val:0xbee1; + valaddr_reg:x4; val_offset:4*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x2, x11, x29, dyn, 96, 0, x4, 4*FLEN/8, x5, x1, x3) + +inst_29: +// rs1==x21, rs2==x0, rd==x8,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a5 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2e1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x21; op2:x0; dest:x8; op1val:0x78a5; op2val:0x0; + valaddr_reg:x4; val_offset:6*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x8, x21, x0, dyn, 128, 0, x4, 6*FLEN/8, x5, x1, x3) + +inst_30: +// rs1==x15, rs2==x7, rd==x14,fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0a4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x15; op2:x7; dest:x14; op1val:0x76e3; op2val:0x40a4; + valaddr_reg:x4; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x14, x15, x7, dyn, 0, 0, x4, 8*FLEN/8, x5, x1, x3) + +inst_31: +// rs1==x7, rs2==x26, rd==x19,fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0a4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x7; op2:x26; dest:x19; op1val:0x76e3; op2val:0x40a4; + valaddr_reg:x4; val_offset:10*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x19, x7, x26, dyn, 32, 0, x4, 10*FLEN/8, x5, x1, x3) + +inst_32: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0a4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x76e3; op2val:0x40a4; + valaddr_reg:x4; val_offset:12*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 12*FLEN/8, x5, x1, x3) + +inst_33: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0a4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x76e3; op2val:0x40a4; + valaddr_reg:x4; val_offset:14*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 14*FLEN/8, x5, x1, x3) + +inst_34: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0a4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x76e3; op2val:0x40a4; + valaddr_reg:x4; val_offset:16*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 16*FLEN/8, x5, x1, x3) + +inst_35: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c8 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x188 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c8; op2val:0xbd88; + valaddr_reg:x4; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 18*FLEN/8, x5, x1, x3) + +inst_36: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c8 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x188 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c8; op2val:0xbd88; + valaddr_reg:x4; val_offset:20*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 20*FLEN/8, x5, x1, x3) + +inst_37: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c8 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x188 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c8; op2val:0xbd88; + valaddr_reg:x4; val_offset:22*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 22*FLEN/8, x5, x1, x3) + +inst_38: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c8 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x188 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c8; op2val:0xbd88; + valaddr_reg:x4; val_offset:24*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 24*FLEN/8, x5, x1, x3) + +inst_39: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c8 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x188 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c8; op2val:0xbd88; + valaddr_reg:x4; val_offset:26*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 26*FLEN/8, x5, x1, x3) + +inst_40: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x397 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x036 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b97; op2val:0x3c36; + valaddr_reg:x4; val_offset:28*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 28*FLEN/8, x5, x1, x3) + +inst_41: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x397 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x036 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b97; op2val:0x3c36; + valaddr_reg:x4; val_offset:30*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 30*FLEN/8, x5, x1, x3) + +inst_42: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x397 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x036 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b97; op2val:0x3c36; + valaddr_reg:x4; val_offset:32*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 32*FLEN/8, x5, x1, x3) + +inst_43: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x397 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x036 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b97; op2val:0x3c36; + valaddr_reg:x4; val_offset:34*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 34*FLEN/8, x5, x1, x3) + +inst_44: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x397 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x036 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b97; op2val:0x3c36; + valaddr_reg:x4; val_offset:36*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 36*FLEN/8, x5, x1, x3) + +inst_45: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31d and fs2 == 1 and fe2 == 0x10 and fm2 == 0x07e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x771d; op2val:0xc07e; + valaddr_reg:x4; val_offset:38*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 38*FLEN/8, x5, x1, x3) + +inst_46: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31d and fs2 == 1 and fe2 == 0x10 and fm2 == 0x07e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x771d; op2val:0xc07e; + valaddr_reg:x4; val_offset:40*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 40*FLEN/8, x5, x1, x3) + +inst_47: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31d and fs2 == 1 and fe2 == 0x10 and fm2 == 0x07e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x771d; op2val:0xc07e; + valaddr_reg:x4; val_offset:42*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 42*FLEN/8, x5, x1, x3) + +inst_48: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31d and fs2 == 1 and fe2 == 0x10 and fm2 == 0x07e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x771d; op2val:0xc07e; + valaddr_reg:x4; val_offset:44*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 44*FLEN/8, x5, x1, x3) + +inst_49: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31d and fs2 == 1 and fe2 == 0x10 and fm2 == 0x07e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x771d; op2val:0xc07e; + valaddr_reg:x4; val_offset:46*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 46*FLEN/8, x5, x1, x3) + +inst_50: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x099 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x2f4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6899; op2val:0x4ef4; + valaddr_reg:x4; val_offset:48*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 48*FLEN/8, x5, x1, x3) + +inst_51: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x099 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x2f4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6899; op2val:0x4ef4; + valaddr_reg:x4; val_offset:50*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 50*FLEN/8, x5, x1, x3) + +inst_52: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x099 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x2f4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6899; op2val:0x4ef4; + valaddr_reg:x4; val_offset:52*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 52*FLEN/8, x5, x1, x3) + +inst_53: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x099 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x2f4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6899; op2val:0x4ef4; + valaddr_reg:x4; val_offset:54*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 54*FLEN/8, x5, x1, x3) + +inst_54: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x099 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x2f4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6899; op2val:0x4ef4; + valaddr_reg:x4; val_offset:56*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 56*FLEN/8, x5, x1, x3) + +inst_55: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x36f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x04d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x776f; op2val:0xc04d; + valaddr_reg:x4; val_offset:58*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 58*FLEN/8, x5, x1, x3) + +inst_56: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x36f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x04d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x776f; op2val:0xc04d; + valaddr_reg:x4; val_offset:60*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 60*FLEN/8, x5, x1, x3) + +inst_57: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x36f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x04d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x776f; op2val:0xc04d; + valaddr_reg:x4; val_offset:62*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 62*FLEN/8, x5, x1, x3) + +inst_58: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x36f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x04d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x776f; op2val:0xc04d; + valaddr_reg:x4; val_offset:64*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 64*FLEN/8, x5, x1, x3) + +inst_59: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x36f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x04d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x776f; op2val:0xc04d; + valaddr_reg:x4; val_offset:66*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 66*FLEN/8, x5, x1, x3) + +inst_60: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x213 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x143 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7613; op2val:0x4143; + valaddr_reg:x4; val_offset:68*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 68*FLEN/8, x5, x1, x3) + +inst_61: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x213 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x143 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7613; op2val:0x4143; + valaddr_reg:x4; val_offset:70*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 70*FLEN/8, x5, x1, x3) + +inst_62: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x213 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x143 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7613; op2val:0x4143; + valaddr_reg:x4; val_offset:72*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 72*FLEN/8, x5, x1, x3) + +inst_63: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x213 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x143 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7613; op2val:0x4143; + valaddr_reg:x4; val_offset:74*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 74*FLEN/8, x5, x1, x3) + +inst_64: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x213 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x143 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7613; op2val:0x4143; + valaddr_reg:x4; val_offset:76*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 76*FLEN/8, x5, x1, x3) + +inst_65: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x034 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x39b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7834; op2val:0xbf9b; + valaddr_reg:x4; val_offset:78*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 78*FLEN/8, x5, x1, x3) + +inst_66: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x034 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x39b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7834; op2val:0xbf9b; + valaddr_reg:x4; val_offset:80*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 80*FLEN/8, x5, x1, x3) + +inst_67: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x034 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x39b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7834; op2val:0xbf9b; + valaddr_reg:x4; val_offset:82*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 82*FLEN/8, x5, x1, x3) + +inst_68: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x034 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x39b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7834; op2val:0xbf9b; + valaddr_reg:x4; val_offset:84*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 84*FLEN/8, x5, x1, x3) + +inst_69: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x034 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x39b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7834; op2val:0xbf9b; + valaddr_reg:x4; val_offset:86*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 86*FLEN/8, x5, x1, x3) + +inst_70: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x38d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x03c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x738d; op2val:0x383c; + valaddr_reg:x4; val_offset:88*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 88*FLEN/8, x5, x1, x3) + +inst_71: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x38d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x03c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x738d; op2val:0x383c; + valaddr_reg:x4; val_offset:90*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 90*FLEN/8, x5, x1, x3) + +inst_72: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x38d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x03c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x738d; op2val:0x383c; + valaddr_reg:x4; val_offset:92*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 92*FLEN/8, x5, x1, x3) + +inst_73: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x38d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x03c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x738d; op2val:0x383c; + valaddr_reg:x4; val_offset:94*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 94*FLEN/8, x5, x1, x3) + +inst_74: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x38d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x03c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x738d; op2val:0x383c; + valaddr_reg:x4; val_offset:96*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 96*FLEN/8, x5, x1, x3) + +inst_75: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x133 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x226 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7533; op2val:0xb626; + valaddr_reg:x4; val_offset:98*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 98*FLEN/8, x5, x1, x3) + +inst_76: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x133 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x226 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7533; op2val:0xb626; + valaddr_reg:x4; val_offset:100*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 100*FLEN/8, x5, x1, x3) + +inst_77: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x133 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x226 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7533; op2val:0xb626; + valaddr_reg:x4; val_offset:102*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 102*FLEN/8, x5, x1, x3) + +inst_78: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x133 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x226 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7533; op2val:0xb626; + valaddr_reg:x4; val_offset:104*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 104*FLEN/8, x5, x1, x3) + +inst_79: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x133 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x226 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7533; op2val:0xb626; + valaddr_reg:x4; val_offset:106*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 106*FLEN/8, x5, x1, x3) + +inst_80: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x014 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3d6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7814; op2val:0x37d6; + valaddr_reg:x4; val_offset:108*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 108*FLEN/8, x5, x1, x3) + +inst_81: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x014 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3d6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7814; op2val:0x37d6; + valaddr_reg:x4; val_offset:110*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 110*FLEN/8, x5, x1, x3) + +inst_82: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x014 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3d6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7814; op2val:0x37d6; + valaddr_reg:x4; val_offset:112*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 112*FLEN/8, x5, x1, x3) + +inst_83: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x014 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3d6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7814; op2val:0x37d6; + valaddr_reg:x4; val_offset:114*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 114*FLEN/8, x5, x1, x3) + +inst_84: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x014 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3d6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7814; op2val:0x37d6; + valaddr_reg:x4; val_offset:116*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 116*FLEN/8, x5, x1, x3) + +inst_85: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x164 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1ee and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7964; op2val:0xb5ee; + valaddr_reg:x4; val_offset:118*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 118*FLEN/8, x5, x1, x3) + +inst_86: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x164 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1ee and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7964; op2val:0xb5ee; + valaddr_reg:x4; val_offset:120*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 120*FLEN/8, x5, x1, x3) + +inst_87: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x164 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1ee and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7964; op2val:0xb5ee; + valaddr_reg:x4; val_offset:122*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 122*FLEN/8, x5, x1, x3) + +inst_88: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x164 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1ee and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7964; op2val:0xb5ee; + valaddr_reg:x4; val_offset:124*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 124*FLEN/8, x5, x1, x3) + +inst_89: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x164 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1ee and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7964; op2val:0xb5ee; + valaddr_reg:x4; val_offset:126*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 126*FLEN/8, x5, x1, x3) + +inst_90: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x325 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x079 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b25; op2val:0x3879; + valaddr_reg:x4; val_offset:128*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 128*FLEN/8, x5, x1, x3) + +inst_91: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x325 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x079 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b25; op2val:0x3879; + valaddr_reg:x4; val_offset:130*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 130*FLEN/8, x5, x1, x3) + +inst_92: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x325 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x079 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b25; op2val:0x3879; + valaddr_reg:x4; val_offset:132*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 132*FLEN/8, x5, x1, x3) + +inst_93: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x325 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x079 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b25; op2val:0x3879; + valaddr_reg:x4; val_offset:134*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 134*FLEN/8, x5, x1, x3) + +inst_94: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x325 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x079 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b25; op2val:0x3879; + valaddr_reg:x4; val_offset:136*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 136*FLEN/8, x5, x1, x3) + +inst_95: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1df and fs2 == 1 and fe2 == 0x0e and fm2 == 0x172 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79df; op2val:0xb972; + valaddr_reg:x4; val_offset:138*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 138*FLEN/8, x5, x1, x3) + +inst_96: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1df and fs2 == 1 and fe2 == 0x0e and fm2 == 0x172 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79df; op2val:0xb972; + valaddr_reg:x4; val_offset:140*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 140*FLEN/8, x5, x1, x3) + +inst_97: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1df and fs2 == 1 and fe2 == 0x0e and fm2 == 0x172 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79df; op2val:0xb972; + valaddr_reg:x4; val_offset:142*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 142*FLEN/8, x5, x1, x3) + +inst_98: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1df and fs2 == 1 and fe2 == 0x0e and fm2 == 0x172 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79df; op2val:0xb972; + valaddr_reg:x4; val_offset:144*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 144*FLEN/8, x5, x1, x3) + +inst_99: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1df and fs2 == 1 and fe2 == 0x0e and fm2 == 0x172 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79df; op2val:0xb972; + valaddr_reg:x4; val_offset:146*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 146*FLEN/8, x5, x1, x3) + +inst_100: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x219 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x13e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a19; op2val:0x3d3e; + valaddr_reg:x4; val_offset:148*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 148*FLEN/8, x5, x1, x3) + +inst_101: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x219 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x13e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a19; op2val:0x3d3e; + valaddr_reg:x4; val_offset:150*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 150*FLEN/8, x5, x1, x3) + +inst_102: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x219 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x13e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a19; op2val:0x3d3e; + valaddr_reg:x4; val_offset:152*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 152*FLEN/8, x5, x1, x3) + +inst_103: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x219 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x13e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a19; op2val:0x3d3e; + valaddr_reg:x4; val_offset:154*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 154*FLEN/8, x5, x1, x3) + +inst_104: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x219 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x13e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a19; op2val:0x3d3e; + valaddr_reg:x4; val_offset:156*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 156*FLEN/8, x5, x1, x3) + +inst_105: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a8 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1a7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x75a8; op2val:0xc1a7; + valaddr_reg:x4; val_offset:158*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 158*FLEN/8, x5, x1, x3) + +inst_106: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a8 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1a7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x75a8; op2val:0xc1a7; + valaddr_reg:x4; val_offset:160*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 160*FLEN/8, x5, x1, x3) + +inst_107: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a8 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1a7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x75a8; op2val:0xc1a7; + valaddr_reg:x4; val_offset:162*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 162*FLEN/8, x5, x1, x3) + +inst_108: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a8 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1a7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x75a8; op2val:0xc1a7; + valaddr_reg:x4; val_offset:164*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 164*FLEN/8, x5, x1, x3) + +inst_109: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a8 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1a7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x75a8; op2val:0xc1a7; + valaddr_reg:x4; val_offset:166*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 166*FLEN/8, x5, x1, x3) + +inst_110: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b1 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x028 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb1; op2val:0x4028; + valaddr_reg:x4; val_offset:168*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 168*FLEN/8, x5, x1, x3) + +inst_111: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b1 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x028 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb1; op2val:0x4028; + valaddr_reg:x4; val_offset:170*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 170*FLEN/8, x5, x1, x3) + +inst_112: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b1 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x028 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb1; op2val:0x4028; + valaddr_reg:x4; val_offset:172*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 172*FLEN/8, x5, x1, x3) + +inst_113: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b1 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x028 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb1; op2val:0x4028; + valaddr_reg:x4; val_offset:174*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 174*FLEN/8, x5, x1, x3) + +inst_114: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b1 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x028 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb1; op2val:0x4028; + valaddr_reg:x4; val_offset:176*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 176*FLEN/8, x5, x1, x3) + +inst_115: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x207 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x14e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a07; op2val:0xc14e; + valaddr_reg:x4; val_offset:178*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 178*FLEN/8, x5, x1, x3) + +inst_116: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x207 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x14e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a07; op2val:0xc14e; + valaddr_reg:x4; val_offset:180*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 180*FLEN/8, x5, x1, x3) + +inst_117: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x207 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x14e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a07; op2val:0xc14e; + valaddr_reg:x4; val_offset:182*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 182*FLEN/8, x5, x1, x3) + +inst_118: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x207 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x14e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a07; op2val:0xc14e; + valaddr_reg:x4; val_offset:184*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 184*FLEN/8, x5, x1, x3) + +inst_119: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x207 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x14e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a07; op2val:0xc14e; + valaddr_reg:x4; val_offset:186*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 186*FLEN/8, x5, x1, x3) + +inst_120: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x361 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7761; op2val:0x4855; + valaddr_reg:x4; val_offset:188*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 188*FLEN/8, x5, x1, x3) + +inst_121: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x361 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x055 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7761; op2val:0x4855; + valaddr_reg:x4; val_offset:190*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 190*FLEN/8, x5, x1, x3) + +inst_122: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x361 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x055 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7761; op2val:0x4855; + valaddr_reg:x4; val_offset:192*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 192*FLEN/8, x5, x1, x3) + +inst_123: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x361 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x055 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7761; op2val:0x4855; + valaddr_reg:x4; val_offset:194*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 194*FLEN/8, x5, x1, x3) + +inst_124: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x361 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x055 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7761; op2val:0x4855; + valaddr_reg:x4; val_offset:196*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 196*FLEN/8, x5, x1, x3) + +inst_125: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d6 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x014 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x77d6; op2val:0xc814; + valaddr_reg:x4; val_offset:198*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 198*FLEN/8, x5, x1, x3) + +inst_126: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d6 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x014 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x77d6; op2val:0xc814; + valaddr_reg:x4; val_offset:200*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 200*FLEN/8, x5, x1, x3) + +inst_127: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d6 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x014 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x77d6; op2val:0xc814; + valaddr_reg:x4; val_offset:202*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 202*FLEN/8, x5, x1, x3) + +inst_128: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d6 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x014 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x77d6; op2val:0xc814; + valaddr_reg:x4; val_offset:204*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 204*FLEN/8, x5, x1, x3) + +inst_129: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d6 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x014 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x77d6; op2val:0xc814; + valaddr_reg:x4; val_offset:206*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 206*FLEN/8, x5, x1, x3) + +inst_130: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7801; op2val:0x4bfc; + valaddr_reg:x4; val_offset:208*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 208*FLEN/8, x5, x1, x3) + +inst_131: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x3fc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7801; op2val:0x4bfc; + valaddr_reg:x4; val_offset:210*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 210*FLEN/8, x5, x1, x3) + +inst_132: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x3fc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7801; op2val:0x4bfc; + valaddr_reg:x4; val_offset:212*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 212*FLEN/8, x5, x1, x3) + +inst_133: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x3fc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7801; op2val:0x4bfc; + valaddr_reg:x4; val_offset:214*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 214*FLEN/8, x5, x1, x3) + +inst_134: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x3fc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7801; op2val:0x4bfc; + valaddr_reg:x4; val_offset:216*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 216*FLEN/8, x5, x1, x3) + +inst_135: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a9 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x1a6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x75a9; op2val:0xcda6; + valaddr_reg:x4; val_offset:218*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 218*FLEN/8, x5, x1, x3) + +inst_136: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a9 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x1a6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x75a9; op2val:0xcda6; + valaddr_reg:x4; val_offset:220*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 220*FLEN/8, x5, x1, x3) + +inst_137: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a9 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x1a6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x75a9; op2val:0xcda6; + valaddr_reg:x4; val_offset:222*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 222*FLEN/8, x5, x1, x3) + +inst_138: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a9 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x1a6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x75a9; op2val:0xcda6; + valaddr_reg:x4; val_offset:224*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 224*FLEN/8, x5, x1, x3) + +inst_139: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a9 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x1a6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x75a9; op2val:0xcda6; + valaddr_reg:x4; val_offset:226*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 226*FLEN/8, x5, x1, x3) + +inst_140: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x02f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba5; op2val:0x3c2f; + valaddr_reg:x4; val_offset:228*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 228*FLEN/8, x5, x1, x3) + +inst_141: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x02f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba5; op2val:0x3c2f; + valaddr_reg:x4; val_offset:230*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 230*FLEN/8, x5, x1, x3) + +inst_142: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x33c and fs2 == 1 and fe2 == 0x13 and fm2 == 0x06b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6b3c; op2val:0xcc6b; + valaddr_reg:x4; val_offset:232*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 232*FLEN/8, x5, x1, x3) + +inst_143: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x299 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x78d8; op2val:0x3e99; + valaddr_reg:x4; val_offset:234*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 234*FLEN/8, x5, x1, x3) + +inst_144: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a5 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2e1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x78a5; op2val:0xbee1; + valaddr_reg:x4; val_offset:236*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 236*FLEN/8, x5, x1, x3) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(15407,32,FLEN) +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(15407,32,FLEN) +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(15407,32,FLEN) +NAN_BOXED(27452,32,FLEN) +NAN_BOXED(52331,16,FLEN) +NAN_BOXED(27452,32,FLEN) +NAN_BOXED(52331,16,FLEN) +NAN_BOXED(27452,32,FLEN) +NAN_BOXED(52331,16,FLEN) +NAN_BOXED(27452,32,FLEN) +NAN_BOXED(52331,16,FLEN) +NAN_BOXED(27452,32,FLEN) +NAN_BOXED(52331,16,FLEN) +NAN_BOXED(31406,32,FLEN) +NAN_BOXED(15561,32,FLEN) +NAN_BOXED(31406,32,FLEN) +NAN_BOXED(15561,32,FLEN) +NAN_BOXED(31406,32,FLEN) +NAN_BOXED(15561,32,FLEN) +NAN_BOXED(31406,32,FLEN) +NAN_BOXED(15561,32,FLEN) +test_dataset_1: +NAN_BOXED(31406,32,FLEN) +NAN_BOXED(15561,32,FLEN) +NAN_BOXED(31066,32,FLEN) +NAN_BOXED(48632,16,FLEN) +NAN_BOXED(31066,32,FLEN) +NAN_BOXED(48632,16,FLEN) +NAN_BOXED(31066,32,FLEN) +NAN_BOXED(48632,16,FLEN) +NAN_BOXED(31066,32,FLEN) +NAN_BOXED(48632,16,FLEN) +NAN_BOXED(31066,32,FLEN) +NAN_BOXED(48632,16,FLEN) +NAN_BOXED(30936,32,FLEN) +NAN_BOXED(16025,32,FLEN) +NAN_BOXED(30936,32,FLEN) +NAN_BOXED(16025,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(16025,32,FLEN) +NAN_BOXED(30936,32,FLEN) +NAN_BOXED(16025,32,FLEN) +NAN_BOXED(30936,32,FLEN) +NAN_BOXED(16025,32,FLEN) +NAN_BOXED(30885,32,FLEN) +NAN_BOXED(48865,16,FLEN) +test_dataset_2: +NAN_BOXED(30885,16,FLEN) +NAN_BOXED(48865,16,FLEN) +NAN_BOXED(30885,16,FLEN) +NAN_BOXED(48865,16,FLEN) +NAN_BOXED(30885,16,FLEN) +NAN_BOXED(48865,16,FLEN) +NAN_BOXED(30885,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(30435,16,FLEN) +NAN_BOXED(16548,16,FLEN) +NAN_BOXED(30435,16,FLEN) +NAN_BOXED(16548,16,FLEN) +NAN_BOXED(30435,16,FLEN) +NAN_BOXED(16548,16,FLEN) +NAN_BOXED(30435,16,FLEN) +NAN_BOXED(16548,16,FLEN) +NAN_BOXED(30435,16,FLEN) +NAN_BOXED(16548,16,FLEN) +NAN_BOXED(31176,16,FLEN) +NAN_BOXED(48520,16,FLEN) +NAN_BOXED(31176,16,FLEN) +NAN_BOXED(48520,16,FLEN) +NAN_BOXED(31176,16,FLEN) +NAN_BOXED(48520,16,FLEN) +NAN_BOXED(31176,16,FLEN) +NAN_BOXED(48520,16,FLEN) +NAN_BOXED(31176,16,FLEN) +NAN_BOXED(48520,16,FLEN) +NAN_BOXED(31639,16,FLEN) +NAN_BOXED(15414,16,FLEN) +NAN_BOXED(31639,16,FLEN) +NAN_BOXED(15414,16,FLEN) +NAN_BOXED(31639,16,FLEN) +NAN_BOXED(15414,16,FLEN) +NAN_BOXED(31639,16,FLEN) +NAN_BOXED(15414,16,FLEN) +NAN_BOXED(31639,16,FLEN) +NAN_BOXED(15414,16,FLEN) +NAN_BOXED(30493,16,FLEN) +NAN_BOXED(49278,16,FLEN) +NAN_BOXED(30493,16,FLEN) +NAN_BOXED(49278,16,FLEN) +NAN_BOXED(30493,16,FLEN) +NAN_BOXED(49278,16,FLEN) +NAN_BOXED(30493,16,FLEN) +NAN_BOXED(49278,16,FLEN) +NAN_BOXED(30493,16,FLEN) +NAN_BOXED(49278,16,FLEN) +NAN_BOXED(26777,16,FLEN) +NAN_BOXED(20212,16,FLEN) +NAN_BOXED(26777,16,FLEN) +NAN_BOXED(20212,16,FLEN) +NAN_BOXED(26777,16,FLEN) +NAN_BOXED(20212,16,FLEN) +NAN_BOXED(26777,16,FLEN) +NAN_BOXED(20212,16,FLEN) +NAN_BOXED(26777,16,FLEN) +NAN_BOXED(20212,16,FLEN) +NAN_BOXED(30575,16,FLEN) +NAN_BOXED(49229,16,FLEN) +NAN_BOXED(30575,16,FLEN) +NAN_BOXED(49229,16,FLEN) +NAN_BOXED(30575,16,FLEN) +NAN_BOXED(49229,16,FLEN) +NAN_BOXED(30575,16,FLEN) +NAN_BOXED(49229,16,FLEN) +NAN_BOXED(30575,16,FLEN) +NAN_BOXED(49229,16,FLEN) +NAN_BOXED(30227,16,FLEN) +NAN_BOXED(16707,16,FLEN) +NAN_BOXED(30227,16,FLEN) +NAN_BOXED(16707,16,FLEN) +NAN_BOXED(30227,16,FLEN) +NAN_BOXED(16707,16,FLEN) +NAN_BOXED(30227,16,FLEN) +NAN_BOXED(16707,16,FLEN) +NAN_BOXED(30227,16,FLEN) +NAN_BOXED(16707,16,FLEN) +NAN_BOXED(30772,16,FLEN) +NAN_BOXED(49051,16,FLEN) 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+NAN_BOXED(27452,16,FLEN) +NAN_BOXED(52331,16,FLEN) +NAN_BOXED(30936,16,FLEN) +NAN_BOXED(16025,16,FLEN) +NAN_BOXED(30885,16,FLEN) +NAN_BOXED(48865,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x2_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_1: + .fill 34*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_0: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fmul_b5-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fmul_b5-01.S new file mode 100644 index 000000000..8e5c2f029 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fmul_b5-01.S @@ -0,0 +1,2349 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 04:50:26 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fmul.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fmul.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fmul_b5 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fmul_b5) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x13,test_dataset_0) +RVTEST_SIGBASE(x4,signature_x4_1) + +inst_0: +// rs1 == rd != rs2, rs1==x0, rs2==x20, rd==x0,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x0; op2:x20; dest:x0; op1val:0x0; op2val:0x0; + valaddr_reg:x13; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fmul.h, x0, x0, x20, dyn, 0, 0, x13, 0*FLEN/8, x15, x4, x9) + +inst_1: +// rs1 == rs2 == rd, rs1==x1, rs2==x1, rd==x1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x1; op2:x1; dest:x1; op1val:0x7ba5; op2val:0x7ba5; + valaddr_reg:x13; val_offset:2*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fmul.h, x1, x1, x1, dyn, 32, 0, x13, 2*FLEN/8, x15, x4, x9) + +inst_2: +// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==x7, rs2==x6, rd==x26,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x7; op2:x6; dest:x26; op1val:0x7ba5; op2val:0x0; + valaddr_reg:x13; val_offset:4*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fmul.h, x26, x7, x6, dyn, 64, 0, x13, 4*FLEN/8, x15, x4, x9) + +inst_3: +// rs1 == rs2 != rd, rs1==x2, rs2==x2, rd==x21,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x2; op2:x2; dest:x21; op1val:0x7ba5; op2val:0x7ba5; + valaddr_reg:x13; val_offset:6*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fmul.h, x21, x2, x2, dyn, 96, 0, x13, 6*FLEN/8, x15, x4, x9) + +inst_4: +// rs2 == rd != rs1, rs1==x3, rs2==x30, rd==x30,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x3; op2:x30; dest:x30; op1val:0x7ba5; op2val:0x0; + valaddr_reg:x13; val_offset:8*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fmul.h, x30, x3, x30, dyn, 128, 0, x13, 8*FLEN/8, x15, x4, x9) + +inst_5: +// rs1==x20, rs2==x5, rd==x25,fs1 == 0 and fe1 == 0x1a and fm1 == 0x33c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x20; op2:x5; dest:x25; op1val:0x6b3c; op2val:0x0; + valaddr_reg:x13; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fmul.h, x25, x20, x5, dyn, 0, 0, x13, 10*FLEN/8, x15, x4, x9) + +inst_6: +// rs1==x21, rs2==x31, rd==x20,fs1 == 0 and fe1 == 0x1a and fm1 == 0x33c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x21; op2:x31; dest:x20; op1val:0x6b3c; op2val:0x0; + valaddr_reg:x13; val_offset:12*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fmul.h, x20, x21, x31, dyn, 32, 0, x13, 12*FLEN/8, x15, x4, x9) + +inst_7: +// rs1==x26, rs2==x3, rd==x22,fs1 == 0 and fe1 == 0x1a and fm1 == 0x33c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x26; op2:x3; dest:x22; op1val:0x6b3c; op2val:0x0; + valaddr_reg:x13; val_offset:14*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fmul.h, x22, x26, x3, dyn, 64, 0, x13, 14*FLEN/8, x15, x4, x9) + +inst_8: +// rs1==x5, rs2==x8, rd==x28,fs1 == 0 and fe1 == 0x1a and fm1 == 0x33c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x5; op2:x8; dest:x28; op1val:0x6b3c; op2val:0x0; + valaddr_reg:x13; val_offset:16*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fmul.h, x28, x5, x8, dyn, 96, 0, x13, 16*FLEN/8, x15, x4, x9) + +inst_9: +// rs1==x23, rs2==x16, rd==x7,fs1 == 0 and fe1 == 0x1a and fm1 == 0x33c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x23; op2:x16; dest:x7; op1val:0x6b3c; op2val:0x0; + valaddr_reg:x13; val_offset:18*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fmul.h, x7, x23, x16, dyn, 128, 0, x13, 18*FLEN/8, x15, x4, x9) + +inst_10: +// rs1==x10, rs2==x7, rd==x24,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x10; op2:x7; dest:x24; op1val:0x7aae; op2val:0x0; + valaddr_reg:x13; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fmul.h, x24, x10, x7, dyn, 0, 0, x13, 20*FLEN/8, x15, x4, x9) + +inst_11: +// rs1==x6, rs2==x24, rd==x29,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x6; op2:x24; dest:x29; op1val:0x7aae; op2val:0x0; + valaddr_reg:x13; val_offset:22*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fmul.h, x29, x6, x24, dyn, 32, 0, x13, 22*FLEN/8, x15, x4, x9) + +inst_12: +// rs1==x16, rs2==x18, rd==x14,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x16; op2:x18; dest:x14; op1val:0x7aae; op2val:0x0; + valaddr_reg:x13; val_offset:24*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fmul.h, x14, x16, x18, dyn, 64, 0, x13, 24*FLEN/8, x15, x4, x9) + +inst_13: +// rs1==x22, rs2==x11, rd==x12,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x22; op2:x11; dest:x12; op1val:0x7aae; op2val:0x0; + valaddr_reg:x13; val_offset:26*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fmul.h, x12, x22, x11, dyn, 96, 0, x13, 26*FLEN/8, x15, x4, x9) +RVTEST_VALBASEUPD(x3,test_dataset_1) + +inst_14: +// rs1==x25, rs2==x28, rd==x13,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x25; op2:x28; dest:x13; op1val:0x7aae; op2val:0x0; + valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x9 +*/ +TEST_FPRR_OP(fmul.h, x13, x25, x28, dyn, 128, 0, x3, 0*FLEN/8, x7, x4, x9) + +inst_15: +// rs1==x31, rs2==x12, rd==x10,fs1 == 0 and fe1 == 0x1e and fm1 == 0x15a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x31; op2:x12; dest:x10; op1val:0x795a; op2val:0x0; + valaddr_reg:x3; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fmul.h, x10, x31, x12, dyn, 0, 0, x3, 2*FLEN/8, x7, x4, x6) + +inst_16: +// rs1==x8, rs2==x23, rd==x17,fs1 == 0 and fe1 == 0x1e and fm1 == 0x15a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x8; op2:x23; dest:x17; op1val:0x795a; op2val:0x0; + valaddr_reg:x3; val_offset:4*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fmul.h, x17, x8, x23, dyn, 32, 0, x3, 4*FLEN/8, x7, x4, x6) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_17: +// rs1==x18, rs2==x26, rd==x5,fs1 == 0 and fe1 == 0x1e and fm1 == 0x15a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x18; op2:x26; dest:x5; op1val:0x795a; op2val:0x0; + valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fmul.h, x5, x18, x26, dyn, 64, 0, x3, 6*FLEN/8, x7, x1, x6) + +inst_18: +// rs1==x24, rs2==x9, rd==x19,fs1 == 0 and fe1 == 0x1e and fm1 == 0x15a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x24; op2:x9; dest:x19; op1val:0x795a; op2val:0x0; + valaddr_reg:x3; val_offset:8*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fmul.h, x19, x24, x9, dyn, 96, 0, x3, 8*FLEN/8, x7, x1, x6) + +inst_19: +// rs1==x4, rs2==x25, rd==x11,fs1 == 0 and fe1 == 0x1e and fm1 == 0x15a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x4; op2:x25; dest:x11; op1val:0x795a; op2val:0x0; + valaddr_reg:x3; val_offset:10*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fmul.h, x11, x4, x25, dyn, 128, 0, x3, 10*FLEN/8, x7, x1, x6) + +inst_20: +// rs1==x28, rs2==x29, rd==x4,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x28; op2:x29; dest:x4; op1val:0x78d8; op2val:0x0; + valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fmul.h, x4, x28, x29, dyn, 0, 0, x3, 12*FLEN/8, x7, x1, x6) + +inst_21: +// rs1==x9, rs2==x4, rd==x31,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x9; op2:x4; dest:x31; op1val:0x78d8; op2val:0x0; + valaddr_reg:x3; val_offset:14*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fmul.h, x31, x9, x4, dyn, 32, 0, x3, 14*FLEN/8, x7, x1, x6) + +inst_22: +// rs1==x14, rs2==x10, rd==x27,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x14; op2:x10; dest:x27; op1val:0x78d8; op2val:0x0; + valaddr_reg:x3; val_offset:16*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fmul.h, x27, x14, x10, dyn, 64, 0, x3, 16*FLEN/8, x7, x1, x6) + +inst_23: +// rs1==x19, rs2==x21, rd==x9,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x19; op2:x21; dest:x9; op1val:0x78d8; op2val:0x0; + valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fmul.h, x9, x19, x21, dyn, 96, 0, x3, 18*FLEN/8, x7, x1, x6) + +inst_24: +// rs1==x27, rs2==x0, rd==x2,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x27; op2:x0; dest:x2; op1val:0x78d8; op2val:0x0; + valaddr_reg:x3; val_offset:20*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fmul.h, x2, x27, x0, dyn, 128, 0, x3, 20*FLEN/8, x7, x1, x6) + +inst_25: +// rs1==x11, rs2==x27, rd==x16,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x11; op2:x27; dest:x16; op1val:0x78a5; op2val:0x0; + valaddr_reg:x3; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fmul.h, x16, x11, x27, dyn, 0, 0, x3, 22*FLEN/8, x7, x1, x6) +RVTEST_VALBASEUPD(x4,test_dataset_2) + +inst_26: +// rs1==x13, rs2==x14, rd==x23,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x13; op2:x14; dest:x23; op1val:0x78a5; op2val:0x0; + valaddr_reg:x4; val_offset:0*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fmul.h, x23, x13, x14, dyn, 32, 0, x4, 0*FLEN/8, x5, x1, x6) + +inst_27: +// rs1==x29, rs2==x17, rd==x15,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x29; op2:x17; dest:x15; op1val:0x78a5; op2val:0x0; + valaddr_reg:x4; val_offset:2*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fmul.h, x15, x29, x17, dyn, 64, 0, x4, 2*FLEN/8, x5, x1, x6) + +inst_28: +// rs1==x12, rs2==x15, rd==x3,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x12; op2:x15; dest:x3; op1val:0x78a5; op2val:0x0; + valaddr_reg:x4; val_offset:4*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fmul.h, x3, x12, x15, dyn, 96, 0, x4, 4*FLEN/8, x5, x1, x6) + +inst_29: +// rs1==x30, rs2==x19, rd==x6,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x19; dest:x6; op1val:0x78a5; op2val:0x0; + valaddr_reg:x4; val_offset:6*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x6, x30, x19, dyn, 128, 0, x4, 6*FLEN/8, x5, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_30: +// rs1==x15, rs2==x22, rd==x8,fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x15; op2:x22; dest:x8; op1val:0x76e3; op2val:0x0; + valaddr_reg:x4; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x8, x15, x22, dyn, 0, 0, x4, 8*FLEN/8, x5, x1, x2) + +inst_31: +// rs1==x17, rs2==x13, rd==x18,fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x17; op2:x13; dest:x18; op1val:0x76e3; op2val:0x0; + valaddr_reg:x4; val_offset:10*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x18, x17, x13, dyn, 32, 0, x4, 10*FLEN/8, x5, x1, x2) + +inst_32: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x76e3; op2val:0x0; + valaddr_reg:x4; val_offset:12*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 12*FLEN/8, x5, x1, x2) + +inst_33: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x76e3; op2val:0x0; + valaddr_reg:x4; val_offset:14*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 14*FLEN/8, x5, x1, x2) + +inst_34: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x76e3; op2val:0x0; + valaddr_reg:x4; val_offset:16*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 16*FLEN/8, x5, x1, x2) + +inst_35: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c8; op2val:0x0; + valaddr_reg:x4; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 18*FLEN/8, x5, x1, x2) + +inst_36: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c8; op2val:0x0; + valaddr_reg:x4; val_offset:20*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 20*FLEN/8, x5, x1, x2) + +inst_37: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c8; op2val:0x0; + valaddr_reg:x4; val_offset:22*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 22*FLEN/8, x5, x1, x2) + +inst_38: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c8; op2val:0x0; + valaddr_reg:x4; val_offset:24*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 24*FLEN/8, x5, x1, x2) + +inst_39: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c8; op2val:0x0; + valaddr_reg:x4; val_offset:26*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 26*FLEN/8, x5, x1, x2) + +inst_40: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x397 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b97; op2val:0x0; + valaddr_reg:x4; val_offset:28*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 28*FLEN/8, x5, x1, x2) + +inst_41: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x397 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b97; op2val:0x0; + valaddr_reg:x4; val_offset:30*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 30*FLEN/8, x5, x1, x2) + +inst_42: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x397 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b97; op2val:0x0; + valaddr_reg:x4; val_offset:32*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 32*FLEN/8, x5, x1, x2) + +inst_43: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x397 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b97; op2val:0x0; + valaddr_reg:x4; val_offset:34*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 34*FLEN/8, x5, x1, x2) + +inst_44: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x397 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b97; op2val:0x0; + valaddr_reg:x4; val_offset:36*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 36*FLEN/8, x5, x1, x2) + +inst_45: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x771d; op2val:0x0; + valaddr_reg:x4; val_offset:38*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 38*FLEN/8, x5, x1, x2) + +inst_46: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x771d; op2val:0x0; + valaddr_reg:x4; val_offset:40*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 40*FLEN/8, x5, x1, x2) + +inst_47: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x771d; op2val:0x0; + valaddr_reg:x4; val_offset:42*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 42*FLEN/8, x5, x1, x2) + +inst_48: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x771d; op2val:0x0; + valaddr_reg:x4; val_offset:44*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 44*FLEN/8, x5, x1, x2) + +inst_49: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x771d; op2val:0x0; + valaddr_reg:x4; val_offset:46*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 46*FLEN/8, x5, x1, x2) + +inst_50: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x099 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6899; op2val:0x0; + valaddr_reg:x4; val_offset:48*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 48*FLEN/8, x5, x1, x2) + +inst_51: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x099 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6899; op2val:0x0; + valaddr_reg:x4; val_offset:50*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 50*FLEN/8, x5, x1, x2) + +inst_52: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x099 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6899; op2val:0x0; + valaddr_reg:x4; val_offset:52*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 52*FLEN/8, x5, x1, x2) + +inst_53: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x099 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6899; op2val:0x0; + valaddr_reg:x4; val_offset:54*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 54*FLEN/8, x5, x1, x2) + +inst_54: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x099 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6899; op2val:0x0; + valaddr_reg:x4; val_offset:56*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 56*FLEN/8, x5, x1, x2) + +inst_55: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x36f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x776f; op2val:0x0; + valaddr_reg:x4; val_offset:58*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 58*FLEN/8, x5, x1, x2) + +inst_56: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x36f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x776f; op2val:0x0; + valaddr_reg:x4; val_offset:60*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 60*FLEN/8, x5, x1, x2) + +inst_57: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x36f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x776f; op2val:0x0; + valaddr_reg:x4; val_offset:62*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 62*FLEN/8, x5, x1, x2) + +inst_58: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x36f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x776f; op2val:0x0; + valaddr_reg:x4; val_offset:64*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 64*FLEN/8, x5, x1, x2) + +inst_59: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x36f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x776f; op2val:0x0; + valaddr_reg:x4; val_offset:66*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 66*FLEN/8, x5, x1, x2) + +inst_60: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x213 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7613; op2val:0x0; + valaddr_reg:x4; val_offset:68*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 68*FLEN/8, x5, x1, x2) + +inst_61: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x213 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7613; op2val:0x0; + valaddr_reg:x4; val_offset:70*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 70*FLEN/8, x5, x1, x2) + +inst_62: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x213 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7613; op2val:0x0; + valaddr_reg:x4; val_offset:72*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 72*FLEN/8, x5, x1, x2) + +inst_63: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x213 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7613; op2val:0x0; + valaddr_reg:x4; val_offset:74*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 74*FLEN/8, x5, x1, x2) + +inst_64: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x213 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7613; op2val:0x0; + valaddr_reg:x4; val_offset:76*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 76*FLEN/8, x5, x1, x2) + +inst_65: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x034 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7834; op2val:0x0; + valaddr_reg:x4; val_offset:78*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 78*FLEN/8, x5, x1, x2) + +inst_66: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x034 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7834; op2val:0x0; + valaddr_reg:x4; val_offset:80*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 80*FLEN/8, x5, x1, x2) + +inst_67: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x034 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7834; op2val:0x0; + valaddr_reg:x4; val_offset:82*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 82*FLEN/8, x5, x1, x2) + +inst_68: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x034 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7834; op2val:0x0; + valaddr_reg:x4; val_offset:84*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 84*FLEN/8, x5, x1, x2) + +inst_69: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x034 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7834; op2val:0x0; + valaddr_reg:x4; val_offset:86*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 86*FLEN/8, x5, x1, x2) + +inst_70: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x38d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x738d; op2val:0x0; + valaddr_reg:x4; val_offset:88*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 88*FLEN/8, x5, x1, x2) + +inst_71: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x38d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x738d; op2val:0x0; + valaddr_reg:x4; val_offset:90*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 90*FLEN/8, x5, x1, x2) + +inst_72: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x38d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x738d; op2val:0x0; + valaddr_reg:x4; val_offset:92*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 92*FLEN/8, x5, x1, x2) + +inst_73: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x38d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x738d; op2val:0x0; + valaddr_reg:x4; val_offset:94*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 94*FLEN/8, x5, x1, x2) + +inst_74: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x38d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x738d; op2val:0x0; + valaddr_reg:x4; val_offset:96*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 96*FLEN/8, x5, x1, x2) + +inst_75: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x133 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7533; op2val:0x0; + valaddr_reg:x4; val_offset:98*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 98*FLEN/8, x5, x1, x2) + +inst_76: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x133 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7533; op2val:0x0; + valaddr_reg:x4; val_offset:100*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 100*FLEN/8, x5, x1, x2) + +inst_77: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x133 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7533; op2val:0x0; + valaddr_reg:x4; val_offset:102*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 102*FLEN/8, x5, x1, x2) + +inst_78: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x133 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7533; op2val:0x0; + valaddr_reg:x4; val_offset:104*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 104*FLEN/8, x5, x1, x2) + +inst_79: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x133 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7533; op2val:0x0; + valaddr_reg:x4; val_offset:106*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 106*FLEN/8, x5, x1, x2) + +inst_80: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x014 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7814; op2val:0x0; + valaddr_reg:x4; val_offset:108*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 108*FLEN/8, x5, x1, x2) + +inst_81: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x014 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7814; op2val:0x0; + valaddr_reg:x4; val_offset:110*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 110*FLEN/8, x5, x1, x2) + +inst_82: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x014 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7814; op2val:0x0; + valaddr_reg:x4; val_offset:112*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 112*FLEN/8, x5, x1, x2) + +inst_83: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x014 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7814; op2val:0x0; + valaddr_reg:x4; val_offset:114*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 114*FLEN/8, x5, x1, x2) + +inst_84: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x014 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7814; op2val:0x0; + valaddr_reg:x4; val_offset:116*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 116*FLEN/8, x5, x1, x2) + +inst_85: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x164 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7964; op2val:0x0; + valaddr_reg:x4; val_offset:118*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 118*FLEN/8, x5, x1, x2) + +inst_86: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x164 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7964; op2val:0x0; + valaddr_reg:x4; val_offset:120*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 120*FLEN/8, x5, x1, x2) + +inst_87: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x164 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7964; op2val:0x0; + valaddr_reg:x4; val_offset:122*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 122*FLEN/8, x5, x1, x2) + +inst_88: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x164 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7964; op2val:0x0; + valaddr_reg:x4; val_offset:124*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 124*FLEN/8, x5, x1, x2) + +inst_89: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x164 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7964; op2val:0x0; + valaddr_reg:x4; val_offset:126*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 126*FLEN/8, x5, x1, x2) + +inst_90: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x325 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b25; op2val:0x0; + valaddr_reg:x4; val_offset:128*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 128*FLEN/8, x5, x1, x2) + +inst_91: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x325 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b25; op2val:0x0; + valaddr_reg:x4; val_offset:130*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 130*FLEN/8, x5, x1, x2) + +inst_92: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x325 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b25; op2val:0x0; + valaddr_reg:x4; val_offset:132*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 132*FLEN/8, x5, x1, x2) + +inst_93: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x325 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b25; op2val:0x0; + valaddr_reg:x4; val_offset:134*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 134*FLEN/8, x5, x1, x2) + +inst_94: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x325 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b25; op2val:0x0; + valaddr_reg:x4; val_offset:136*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 136*FLEN/8, x5, x1, x2) + +inst_95: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1df and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79df; op2val:0x0; + valaddr_reg:x4; val_offset:138*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 138*FLEN/8, x5, x1, x2) + +inst_96: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1df and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79df; op2val:0x0; + valaddr_reg:x4; val_offset:140*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 140*FLEN/8, x5, x1, x2) + +inst_97: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1df and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79df; op2val:0x0; + valaddr_reg:x4; val_offset:142*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 142*FLEN/8, x5, x1, x2) + +inst_98: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1df and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79df; op2val:0x0; + valaddr_reg:x4; val_offset:144*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 144*FLEN/8, x5, x1, x2) + +inst_99: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1df and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79df; op2val:0x0; + valaddr_reg:x4; val_offset:146*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 146*FLEN/8, x5, x1, x2) + +inst_100: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x219 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a19; op2val:0x0; + valaddr_reg:x4; val_offset:148*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 148*FLEN/8, x5, x1, x2) + +inst_101: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x219 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a19; op2val:0x0; + valaddr_reg:x4; val_offset:150*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 150*FLEN/8, x5, x1, x2) + +inst_102: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x219 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a19; op2val:0x0; + valaddr_reg:x4; val_offset:152*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 152*FLEN/8, x5, x1, x2) + +inst_103: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x219 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a19; op2val:0x0; + valaddr_reg:x4; val_offset:154*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 154*FLEN/8, x5, x1, x2) + +inst_104: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x219 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a19; op2val:0x0; + valaddr_reg:x4; val_offset:156*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 156*FLEN/8, x5, x1, x2) + +inst_105: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x75a8; op2val:0x1; + valaddr_reg:x4; val_offset:158*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 158*FLEN/8, x5, x1, x2) + +inst_106: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x75a8; op2val:0x1; + valaddr_reg:x4; val_offset:160*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 160*FLEN/8, x5, x1, x2) + +inst_107: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x75a8; op2val:0x1; + valaddr_reg:x4; val_offset:162*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 162*FLEN/8, x5, x1, x2) + +inst_108: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x75a8; op2val:0x1; + valaddr_reg:x4; val_offset:164*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 164*FLEN/8, x5, x1, x2) + +inst_109: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x75a8; op2val:0x1; + valaddr_reg:x4; val_offset:166*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 166*FLEN/8, x5, x1, x2) + +inst_110: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb1; op2val:0x8000; + valaddr_reg:x4; val_offset:168*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 168*FLEN/8, x5, x1, x2) + +inst_111: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb1; op2val:0x8000; + valaddr_reg:x4; val_offset:170*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 170*FLEN/8, x5, x1, x2) + +inst_112: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb1; op2val:0x8000; + valaddr_reg:x4; val_offset:172*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 172*FLEN/8, x5, x1, x2) + +inst_113: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb1; op2val:0x8000; + valaddr_reg:x4; val_offset:174*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 174*FLEN/8, x5, x1, x2) + +inst_114: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb1; op2val:0x8000; + valaddr_reg:x4; val_offset:176*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 176*FLEN/8, x5, x1, x2) + +inst_115: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x207 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a07; op2val:0x8000; + valaddr_reg:x4; val_offset:178*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 178*FLEN/8, x5, x1, x2) + +inst_116: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x207 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a07; op2val:0x8000; + valaddr_reg:x4; val_offset:180*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 180*FLEN/8, x5, x1, x2) + +inst_117: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x207 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a07; op2val:0x8000; + valaddr_reg:x4; val_offset:182*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 182*FLEN/8, x5, x1, x2) + +inst_118: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x207 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a07; op2val:0x8000; + valaddr_reg:x4; val_offset:184*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 184*FLEN/8, x5, x1, x2) + +inst_119: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x207 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a07; op2val:0x8000; + valaddr_reg:x4; val_offset:186*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 186*FLEN/8, x5, x1, x2) + +inst_120: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x361 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7761; op2val:0x8000; + valaddr_reg:x4; val_offset:188*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 188*FLEN/8, x5, x1, x2) + +inst_121: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x361 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7761; op2val:0x8000; + valaddr_reg:x4; val_offset:190*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 190*FLEN/8, x5, x1, x2) + +inst_122: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x361 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7761; op2val:0x8000; + valaddr_reg:x4; val_offset:192*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 192*FLEN/8, x5, x1, x2) + +inst_123: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x361 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7761; op2val:0x8000; + valaddr_reg:x4; val_offset:194*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 194*FLEN/8, x5, x1, x2) + +inst_124: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x361 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7761; op2val:0x8000; + valaddr_reg:x4; val_offset:196*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 196*FLEN/8, x5, x1, x2) + +inst_125: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x77d6; op2val:0x8000; + valaddr_reg:x4; val_offset:198*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 198*FLEN/8, x5, x1, x2) + +inst_126: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x77d6; op2val:0x8000; + valaddr_reg:x4; val_offset:200*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 200*FLEN/8, x5, x1, x2) + +inst_127: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x77d6; op2val:0x8000; + valaddr_reg:x4; val_offset:202*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 202*FLEN/8, x5, x1, x2) + +inst_128: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x77d6; op2val:0x8000; + valaddr_reg:x4; val_offset:204*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 204*FLEN/8, x5, x1, x2) + +inst_129: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x77d6; op2val:0x8000; + valaddr_reg:x4; val_offset:206*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 206*FLEN/8, x5, x1, x2) + +inst_130: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7801; op2val:0x8000; + valaddr_reg:x4; val_offset:208*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 208*FLEN/8, x5, x1, x2) + +inst_131: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7801; op2val:0x8000; + valaddr_reg:x4; val_offset:210*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 210*FLEN/8, x5, x1, x2) + +inst_132: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7801; op2val:0x8000; + valaddr_reg:x4; val_offset:212*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 212*FLEN/8, x5, x1, x2) + +inst_133: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7801; op2val:0x8000; + valaddr_reg:x4; val_offset:214*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 214*FLEN/8, x5, x1, x2) + +inst_134: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7801; op2val:0x8000; + valaddr_reg:x4; val_offset:216*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 216*FLEN/8, x5, x1, x2) + +inst_135: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x75a9; op2val:0x8000; + valaddr_reg:x4; val_offset:218*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 218*FLEN/8, x5, x1, x2) + +inst_136: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x75a9; op2val:0x8000; + valaddr_reg:x4; val_offset:220*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 220*FLEN/8, x5, x1, x2) + +inst_137: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x75a9; op2val:0x8000; + valaddr_reg:x4; val_offset:222*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 222*FLEN/8, x5, x1, x2) + +inst_138: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x75a9; op2val:0x8000; + valaddr_reg:x4; val_offset:224*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 224*FLEN/8, x5, x1, x2) + +inst_139: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x75a9; op2val:0x8000; + valaddr_reg:x4; val_offset:226*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 226*FLEN/8, x5, x1, x2) + +inst_140: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x331 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b31; op2val:0x8000; + valaddr_reg:x4; val_offset:228*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 228*FLEN/8, x5, x1, x2) + +inst_141: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x331 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b31; op2val:0x8000; + valaddr_reg:x4; val_offset:230*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 230*FLEN/8, x5, x1, x2) + +inst_142: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x331 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b31; op2val:0x8000; + valaddr_reg:x4; val_offset:232*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 232*FLEN/8, x5, x1, x2) + +inst_143: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x331 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b31; op2val:0x8000; + valaddr_reg:x4; val_offset:234*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 234*FLEN/8, x5, x1, x2) + +inst_144: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x331 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b31; op2val:0x8000; + valaddr_reg:x4; val_offset:236*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 236*FLEN/8, x5, x1, x2) + +inst_145: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x08a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x788a; op2val:0x8000; + valaddr_reg:x4; val_offset:238*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 238*FLEN/8, x5, x1, x2) + +inst_146: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x08a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x788a; op2val:0x8000; + valaddr_reg:x4; val_offset:240*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 240*FLEN/8, x5, x1, x2) + +inst_147: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x08a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x788a; op2val:0x8000; + valaddr_reg:x4; val_offset:242*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 242*FLEN/8, x5, x1, x2) + +inst_148: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x08a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x788a; op2val:0x8000; + valaddr_reg:x4; val_offset:244*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 244*FLEN/8, x5, x1, x2) + +inst_149: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x08a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x788a; op2val:0x8000; + valaddr_reg:x4; val_offset:246*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 246*FLEN/8, x5, x1, x2) + +inst_150: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c9; op2val:0x8000; + valaddr_reg:x4; val_offset:248*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 248*FLEN/8, x5, x1, x2) + +inst_151: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c9; op2val:0x8000; + valaddr_reg:x4; val_offset:250*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 250*FLEN/8, x5, x1, x2) + +inst_152: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c9; op2val:0x8000; + valaddr_reg:x4; val_offset:252*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 252*FLEN/8, x5, x1, x2) + +inst_153: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c9; op2val:0x8000; + valaddr_reg:x4; val_offset:254*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 254*FLEN/8, x5, x1, x2) + +inst_154: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c9; op2val:0x8000; + valaddr_reg:x4; val_offset:256*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 256*FLEN/8, x5, x1, x2) + +inst_155: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x318 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7318; op2val:0x8000; + valaddr_reg:x4; val_offset:258*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 258*FLEN/8, x5, x1, x2) + +inst_156: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x318 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7318; op2val:0x8000; + valaddr_reg:x4; val_offset:260*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 260*FLEN/8, x5, x1, x2) + +inst_157: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x318 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7318; op2val:0x8000; + valaddr_reg:x4; val_offset:262*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 262*FLEN/8, x5, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_2) + +inst_158: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x318 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7318; op2val:0x8000; + valaddr_reg:x4; val_offset:264*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 264*FLEN/8, x5, x1, x2) + +inst_159: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x318 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7318; op2val:0x8000; + valaddr_reg:x4; val_offset:266*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 266*FLEN/8, x5, x1, x2) + +inst_160: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x198 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7998; op2val:0x8000; + valaddr_reg:x4; val_offset:268*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 268*FLEN/8, x5, x1, x2) + +inst_161: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x198 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7998; op2val:0x8000; + valaddr_reg:x4; val_offset:270*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 270*FLEN/8, x5, x1, x2) + +inst_162: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x198 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7998; op2val:0x8000; + valaddr_reg:x4; val_offset:272*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 272*FLEN/8, x5, x1, x2) + +inst_163: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x198 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7998; op2val:0x8000; + valaddr_reg:x4; val_offset:274*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 274*FLEN/8, x5, x1, x2) + +inst_164: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x198 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7998; op2val:0x8000; + valaddr_reg:x4; val_offset:276*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 276*FLEN/8, x5, x1, x2) + +inst_165: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x342 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b42; op2val:0x8000; + valaddr_reg:x4; val_offset:278*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 278*FLEN/8, x5, x1, x2) + +inst_166: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x342 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b42; op2val:0x8000; + valaddr_reg:x4; val_offset:280*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 280*FLEN/8, x5, x1, x2) + +inst_167: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x342 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b42; op2val:0x8000; + valaddr_reg:x4; val_offset:282*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 282*FLEN/8, x5, x1, x2) + +inst_168: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x342 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b42; op2val:0x8000; + valaddr_reg:x4; val_offset:284*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 284*FLEN/8, x5, x1, x2) + +inst_169: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x342 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b42; op2val:0x8000; + valaddr_reg:x4; val_offset:286*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 286*FLEN/8, x5, x1, x2) + +inst_170: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x349 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b49; op2val:0x8000; + valaddr_reg:x4; val_offset:288*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 288*FLEN/8, x5, x1, x2) + +inst_171: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x349 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b49; op2val:0x8000; + valaddr_reg:x4; val_offset:290*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 290*FLEN/8, x5, x1, x2) + +inst_172: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x349 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b49; op2val:0x8000; + valaddr_reg:x4; val_offset:292*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 292*FLEN/8, x5, x1, x2) + +inst_173: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x349 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b49; op2val:0x8000; + valaddr_reg:x4; val_offset:294*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 294*FLEN/8, x5, x1, x2) + +inst_174: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x349 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b49; op2val:0x8000; + valaddr_reg:x4; val_offset:296*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 296*FLEN/8, x5, x1, x2) + +inst_175: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba7; op2val:0x8000; + valaddr_reg:x4; val_offset:298*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 298*FLEN/8, x5, x1, x2) + +inst_176: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba7; op2val:0x8000; + valaddr_reg:x4; val_offset:300*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 300*FLEN/8, x5, x1, x2) + +inst_177: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba7; op2val:0x8000; + valaddr_reg:x4; val_offset:302*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 302*FLEN/8, x5, x1, x2) + +inst_178: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba7; op2val:0x8000; + valaddr_reg:x4; val_offset:304*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 304*FLEN/8, x5, x1, x2) + +inst_179: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba7; op2val:0x8000; + valaddr_reg:x4; val_offset:306*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 306*FLEN/8, x5, x1, x2) + +inst_180: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x008 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7808; op2val:0x8000; + valaddr_reg:x4; val_offset:308*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 308*FLEN/8, x5, x1, x2) + +inst_181: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x008 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7808; op2val:0x8000; + valaddr_reg:x4; val_offset:310*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 310*FLEN/8, x5, x1, x2) + +inst_182: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x008 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7808; op2val:0x8000; + valaddr_reg:x4; val_offset:312*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 312*FLEN/8, x5, x1, x2) + +inst_183: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x008 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7808; op2val:0x8000; + valaddr_reg:x4; val_offset:314*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 314*FLEN/8, x5, x1, x2) + +inst_184: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x008 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7808; op2val:0x8000; + valaddr_reg:x4; val_offset:316*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 316*FLEN/8, x5, x1, x2) + +inst_185: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x135 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7935; op2val:0x8000; + valaddr_reg:x4; val_offset:318*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 318*FLEN/8, x5, x1, x2) + +inst_186: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x135 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7935; op2val:0x8000; + valaddr_reg:x4; val_offset:320*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 320*FLEN/8, x5, x1, x2) + +inst_187: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x135 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7935; op2val:0x8000; + valaddr_reg:x4; val_offset:322*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 322*FLEN/8, x5, x1, x2) + +inst_188: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x135 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7935; op2val:0x8000; + valaddr_reg:x4; val_offset:324*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 324*FLEN/8, x5, x1, x2) + +inst_189: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x135 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7935; op2val:0x8000; + valaddr_reg:x4; val_offset:326*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 326*FLEN/8, x5, x1, x2) + +inst_190: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x74fc; op2val:0x8000; + valaddr_reg:x4; val_offset:328*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 328*FLEN/8, x5, x1, x2) + +inst_191: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x74fc; op2val:0x8000; + valaddr_reg:x4; val_offset:330*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 330*FLEN/8, x5, x1, x2) + +inst_192: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x74fc; op2val:0x8000; + valaddr_reg:x4; val_offset:332*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 332*FLEN/8, x5, x1, x2) + +inst_193: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x74fc; op2val:0x8000; + valaddr_reg:x4; val_offset:334*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 334*FLEN/8, x5, x1, x2) + +inst_194: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x74fc; op2val:0x8000; + valaddr_reg:x4; val_offset:336*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 336*FLEN/8, x5, x1, x2) + +inst_195: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x017 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7817; op2val:0x8000; + valaddr_reg:x4; val_offset:338*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 338*FLEN/8, x5, x1, x2) + +inst_196: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x017 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7817; op2val:0x8000; + valaddr_reg:x4; val_offset:340*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 340*FLEN/8, x5, x1, x2) + +inst_197: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x017 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7817; op2val:0x8000; + valaddr_reg:x4; val_offset:342*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 342*FLEN/8, x5, x1, x2) + +inst_198: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x017 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7817; op2val:0x8000; + valaddr_reg:x4; val_offset:344*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 344*FLEN/8, x5, x1, x2) + +inst_199: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x017 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7817; op2val:0x8000; + valaddr_reg:x4; val_offset:346*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 346*FLEN/8, x5, x1, x2) + +inst_200: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x78fb; op2val:0x8000; + valaddr_reg:x4; val_offset:348*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 348*FLEN/8, x5, x1, x2) + +inst_201: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x78fb; op2val:0x8000; + valaddr_reg:x4; val_offset:350*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 350*FLEN/8, x5, x1, x2) + +inst_202: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x78fb; op2val:0x8000; + valaddr_reg:x4; val_offset:352*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 352*FLEN/8, x5, x1, x2) + +inst_203: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x78fb; op2val:0x8000; + valaddr_reg:x4; val_offset:354*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 354*FLEN/8, x5, x1, x2) + +inst_204: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x78fb; op2val:0x8000; + valaddr_reg:x4; val_offset:356*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 356*FLEN/8, x5, x1, x2) + +inst_205: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a8f; op2val:0x8000; + valaddr_reg:x4; val_offset:358*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 358*FLEN/8, x5, x1, x2) + +inst_206: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a8f; op2val:0x8000; + valaddr_reg:x4; val_offset:360*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 360*FLEN/8, x5, x1, x2) + +inst_207: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a8f; op2val:0x8000; + valaddr_reg:x4; val_offset:362*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 362*FLEN/8, x5, x1, x2) + +inst_208: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a8f; op2val:0x8000; + valaddr_reg:x4; val_offset:364*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 364*FLEN/8, x5, x1, x2) + +inst_209: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a8f; op2val:0x8000; + valaddr_reg:x4; val_offset:366*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 366*FLEN/8, x5, x1, x2) + +inst_210: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x341 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b41; op2val:0x8000; + valaddr_reg:x4; val_offset:368*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 368*FLEN/8, x5, x1, x2) + +inst_211: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x341 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b41; op2val:0x8000; + valaddr_reg:x4; val_offset:370*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 370*FLEN/8, x5, x1, x2) + +inst_212: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x341 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b41; op2val:0x8000; + valaddr_reg:x4; val_offset:372*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 372*FLEN/8, x5, x1, x2) + +inst_213: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x341 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b41; op2val:0x8000; + valaddr_reg:x4; val_offset:374*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 374*FLEN/8, x5, x1, x2) + +inst_214: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x341 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b41; op2val:0x8000; + valaddr_reg:x4; val_offset:376*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 376*FLEN/8, x5, x1, x2) + +inst_215: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79f4; op2val:0x8000; + valaddr_reg:x4; val_offset:378*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 378*FLEN/8, x5, x1, x2) + +inst_216: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79f4; op2val:0x8000; + valaddr_reg:x4; val_offset:380*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 380*FLEN/8, x5, x1, x2) + +inst_217: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79f4; op2val:0x8000; + valaddr_reg:x4; val_offset:382*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 382*FLEN/8, x5, x1, x2) + +inst_218: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79f4; op2val:0x8000; + valaddr_reg:x4; val_offset:384*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 384*FLEN/8, x5, x1, x2) + +inst_219: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79f4; op2val:0x8000; + valaddr_reg:x4; val_offset:386*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 386*FLEN/8, x5, x1, x2) + +inst_220: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba5; op2val:0x0; + valaddr_reg:x4; val_offset:388*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 388*FLEN/8, x5, x1, x2) + +inst_221: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba5; op2val:0x0; + valaddr_reg:x4; val_offset:390*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 390*FLEN/8, x5, x1, x2) + +inst_222: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba5; op2val:0x0; + valaddr_reg:x4; val_offset:392*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 392*FLEN/8, x5, x1, x2) + +inst_223: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x78d8; op2val:0x0; + valaddr_reg:x4; val_offset:394*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 394*FLEN/8, x5, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(27452,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(27452,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(27452,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(27452,32,FLEN) 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+rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x4_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x4_1: + .fill 34*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_0: + .fill 26*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_2: + .fill 132*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fmul_b6-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fmul_b6-01.S new file mode 100644 index 000000000..9d6fcc561 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fmul_b6-01.S @@ -0,0 +1,474 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 04:50:26 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fmul.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fmul.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fmul_b6 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fmul_b6) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x9,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd != rs2, rs1==x11, rs2==x23, rd==x11,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x11; op2:x23; dest:x11; op1val:0x0; op2val:0xfbff; + valaddr_reg:x9; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x11, x11, x23, dyn, 0, 0, x9, 0*FLEN/8, x15, x1, x8) + +inst_1: +// rs1 == rs2 == rd, rs1==x6, rs2==x6, rd==x6,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x6; op2:x6; dest:x6; op1val:0x0; op2val:0x0; + valaddr_reg:x9; val_offset:2*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x6, x6, x6, dyn, 32, 0, x9, 2*FLEN/8, x15, x1, x8) + +inst_2: +// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==x10, rs2==x18, rd==x26,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x10; op2:x18; dest:x26; op1val:0x0; op2val:0xfbff; + valaddr_reg:x9; val_offset:4*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x26, x10, x18, dyn, 64, 0, x9, 4*FLEN/8, x15, x1, x8) + +inst_3: +// rs1 == rs2 != rd, rs1==x4, rs2==x4, rd==x0,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x4; op2:x4; dest:x0; op1val:0x0; op2val:0x0; + valaddr_reg:x9; val_offset:6*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x0, x4, x4, dyn, 96, 0, x9, 6*FLEN/8, x15, x1, x8) + +inst_4: +// rs2 == rd != rs1, rs1==x5, rs2==x2, rd==x2,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x5; op2:x2; dest:x2; op1val:0x0; op2val:0xfbff; + valaddr_reg:x9; val_offset:8*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x2, x5, x2, dyn, 128, 0, x9, 8*FLEN/8, x15, x1, x8) + +inst_5: +// rs1==x17, rs2==x30, rd==x19,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x17; op2:x30; dest:x19; op1val:0x0; op2val:0x7bff; + valaddr_reg:x9; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x19, x17, x30, dyn, 0, 0, x9, 10*FLEN/8, x15, x1, x8) + +inst_6: +// rs1==x28, rs2==x24, rd==x27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x28; op2:x24; dest:x27; op1val:0x0; op2val:0x7bff; + valaddr_reg:x9; val_offset:12*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x27, x28, x24, dyn, 32, 0, x9, 12*FLEN/8, x15, x1, x8) + +inst_7: +// rs1==x3, rs2==x25, rd==x17,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x3; op2:x25; dest:x17; op1val:0x0; op2val:0x7bff; + valaddr_reg:x9; val_offset:14*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x17, x3, x25, dyn, 64, 0, x9, 14*FLEN/8, x15, x1, x8) + +inst_8: +// rs1==x19, rs2==x0, rd==x24,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x19; op2:x0; dest:x24; op1val:0x0; op2val:0x0; + valaddr_reg:x9; val_offset:16*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x24, x19, x0, dyn, 96, 0, x9, 16*FLEN/8, x15, x1, x8) + +inst_9: +// rs1==x21, rs2==x11, rd==x12,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x21; op2:x11; dest:x12; op1val:0x0; op2val:0x7bff; + valaddr_reg:x9; val_offset:18*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x12, x21, x11, dyn, 128, 0, x9, 18*FLEN/8, x15, x1, x8) + +inst_10: +// rs1==x29, rs2==x21, rd==x10, +/* opcode: fmul.h ; op1:x29; op2:x21; dest:x10; op1val:0x0; op2val:0x0; + valaddr_reg:x9; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x10, x29, x21, dyn, 0, 0, x9, 20*FLEN/8, x15, x1, x8) + +inst_11: +// rs1==x26, rs2==x13, rd==x25, +/* opcode: fmul.h ; op1:x26; op2:x13; dest:x25; op1val:0x0; op2val:0x0; + valaddr_reg:x9; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x25, x26, x13, dyn, 0, 0, x9, 22*FLEN/8, x15, x1, x8) + +inst_12: +// rs1==x24, rs2==x28, rd==x7, +/* opcode: fmul.h ; op1:x24; op2:x28; dest:x7; op1val:0x0; op2val:0x0; + valaddr_reg:x9; val_offset:24*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x7, x24, x28, dyn, 0, 0, x9, 24*FLEN/8, x15, x1, x8) + +inst_13: +// rs1==x12, rs2==x31, rd==x14, +/* opcode: fmul.h ; op1:x12; op2:x31; dest:x14; op1val:0x0; op2val:0x0; + valaddr_reg:x9; val_offset:26*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x14, x12, x31, dyn, 0, 0, x9, 26*FLEN/8, x15, x1, x8) +RVTEST_VALBASEUPD(x11,test_dataset_1) + +inst_14: +// rs1==x2, rs2==x22, rd==x15, +/* opcode: fmul.h ; op1:x2; op2:x22; dest:x15; op1val:0x0; op2val:0x0; + valaddr_reg:x11; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8 +*/ +TEST_FPRR_OP(fmul.h, x15, x2, x22, dyn, 0, 0, x11, 0*FLEN/8, x13, x1, x8) +RVTEST_SIGBASE(x2,signature_x2_0) + +inst_15: +// rs1==x16, rs2==x12, rd==x31, +/* opcode: fmul.h ; op1:x16; op2:x12; dest:x31; op1val:0x0; op2val:0x0; + valaddr_reg:x11; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fmul.h, x31, x16, x12, dyn, 0, 0, x11, 2*FLEN/8, x13, x2, x6) + +inst_16: +// rs1==x23, rs2==x8, rd==x28, +/* opcode: fmul.h ; op1:x23; op2:x8; dest:x28; op1val:0x0; op2val:0x0; + valaddr_reg:x11; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fmul.h, x28, x23, x8, dyn, 0, 0, x11, 4*FLEN/8, x13, x2, x6) + +inst_17: +// rs1==x25, rs2==x29, rd==x16, +/* opcode: fmul.h ; op1:x25; op2:x29; dest:x16; op1val:0x0; op2val:0x0; + valaddr_reg:x11; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fmul.h, x16, x25, x29, dyn, 0, 0, x11, 6*FLEN/8, x13, x2, x6) + +inst_18: +// rs1==x1, rs2==x9, rd==x22, +/* opcode: fmul.h ; op1:x1; op2:x9; dest:x22; op1val:0x0; op2val:0x0; + valaddr_reg:x11; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fmul.h, x22, x1, x9, dyn, 0, 0, x11, 8*FLEN/8, x13, x2, x6) + +inst_19: +// rs1==x8, rs2==x26, rd==x20, +/* opcode: fmul.h ; op1:x8; op2:x26; dest:x20; op1val:0x0; op2val:0x0; + valaddr_reg:x11; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fmul.h, x20, x8, x26, dyn, 0, 0, x11, 10*FLEN/8, x13, x2, x6) + +inst_20: +// rs1==x30, rs2==x27, rd==x3, +/* opcode: fmul.h ; op1:x30; op2:x27; dest:x3; op1val:0x0; op2val:0x0; + valaddr_reg:x11; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fmul.h, x3, x30, x27, dyn, 0, 0, x11, 12*FLEN/8, x13, x2, x6) + +inst_21: +// rs1==x27, rs2==x10, rd==x23, +/* opcode: fmul.h ; op1:x27; op2:x10; dest:x23; op1val:0x0; op2val:0x0; + valaddr_reg:x11; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fmul.h, x23, x27, x10, dyn, 0, 0, x11, 14*FLEN/8, x13, x2, x6) + +inst_22: +// rs1==x22, rs2==x19, rd==x1, +/* opcode: fmul.h ; op1:x22; op2:x19; dest:x1; op1val:0x0; op2val:0x0; + valaddr_reg:x11; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fmul.h, x1, x22, x19, dyn, 0, 0, x11, 16*FLEN/8, x13, x2, x6) + +inst_23: +// rs1==x0, rs2==x3, rd==x29, +/* opcode: fmul.h ; op1:x0; op2:x3; dest:x29; op1val:0x0; op2val:0x0; + valaddr_reg:x11; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fmul.h, x29, x0, x3, dyn, 0, 0, x11, 18*FLEN/8, x13, x2, x6) + +inst_24: +// rs1==x31, rs2==x7, rd==x5, +/* opcode: fmul.h ; op1:x31; op2:x7; dest:x5; op1val:0x0; op2val:0x0; + valaddr_reg:x11; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fmul.h, x5, x31, x7, dyn, 0, 0, x11, 20*FLEN/8, x13, x2, x6) + +inst_25: +// rs1==x20, rs2==x15, rd==x9, +/* opcode: fmul.h ; op1:x20; op2:x15; dest:x9; op1val:0x0; op2val:0x0; + valaddr_reg:x11; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fmul.h, x9, x20, x15, dyn, 0, 0, x11, 22*FLEN/8, x13, x2, x6) + +inst_26: +// rs1==x9, rs2==x16, rd==x4, +/* opcode: fmul.h ; op1:x9; op2:x16; dest:x4; op1val:0x0; op2val:0x0; + valaddr_reg:x11; val_offset:24*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fmul.h, x4, x9, x16, dyn, 0, 0, x11, 24*FLEN/8, x13, x2, x6) + +inst_27: +// rs1==x7, rs2==x20, rd==x21, +/* opcode: fmul.h ; op1:x7; op2:x20; dest:x21; op1val:0x0; op2val:0x0; + valaddr_reg:x11; val_offset:26*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fmul.h, x21, x7, x20, dyn, 0, 0, x11, 26*FLEN/8, x13, x2, x6) +RVTEST_VALBASEUPD(x4,test_dataset_2) + +inst_28: +// rs1==x18, rs2==x17, rd==x8, +/* opcode: fmul.h ; op1:x18; op2:x17; dest:x8; op1val:0x0; op2val:0x0; + valaddr_reg:x4; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP(fmul.h, x8, x18, x17, dyn, 0, 0, x4, 0*FLEN/8, x9, x2, x6) + +inst_29: +// rs1==x14, rs2==x1, rd==x18, +/* opcode: fmul.h ; op1:x14; op2:x1; dest:x18; op1val:0x0; op2val:0x0; + valaddr_reg:x4; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x18, x14, x1, dyn, 0, 0, x4, 2*FLEN/8, x9, x2, x3) +RVTEST_SIGBASE(x2,signature_x2_1) + +inst_30: +// rs1==x15, rs2==x5, rd==x30, +/* opcode: fmul.h ; op1:x15; op2:x5; dest:x30; op1val:0x0; op2val:0x0; + valaddr_reg:x4; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x30, x15, x5, dyn, 0, 0, x4, 4*FLEN/8, x9, x2, x3) + +inst_31: +// rs1==x13, +/* opcode: fmul.h ; op1:x13; op2:x22; dest:x27; op1val:0x0; op2val:0x0; + valaddr_reg:x4; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x27, x13, x22, dyn, 0, 0, x4, 6*FLEN/8, x9, x2, x3) + +inst_32: +// rs2==x14, +/* opcode: fmul.h ; op1:x22; op2:x14; dest:x15; op1val:0x0; op2val:0x0; + valaddr_reg:x4; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x15, x22, x14, dyn, 0, 0, x4, 8*FLEN/8, x9, x2, x3) + +inst_33: +// rd==x13, +/* opcode: fmul.h ; op1:x7; op2:x1; dest:x13; op1val:0x0; op2val:0x0; + valaddr_reg:x4; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x13, x7, x1, dyn, 0, 0, x4, 10*FLEN/8, x9, x2, x3) + +inst_34: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xfbff; + valaddr_reg:x4; val_offset:12*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 12*FLEN/8, x9, x2, x3) + +inst_35: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xfbff; + valaddr_reg:x4; val_offset:14*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 14*FLEN/8, x9, x2, x3) + +inst_36: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x7bff; + valaddr_reg:x4; val_offset:16*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 16*FLEN/8, x9, x2, x3) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +test_dataset_1: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +test_dataset_2: +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 30*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_0: + .fill 30*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_1: + .fill 14*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fmul_b7-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fmul_b7-01.S new file mode 100644 index 000000000..911efc825 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fmul_b7-01.S @@ -0,0 +1,714 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 04:50:26 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fmul.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fmul.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fmul_b7 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fmul_b7) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x18,test_dataset_0) +RVTEST_SIGBASE(x9,signature_x9_1) + +inst_0: +// rs1 == rd != rs2, rs1==x4, rs2==x7, rd==x4,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x4; op2:x7; dest:x4; op1val:0x7ba5; op2val:0x0; + valaddr_reg:x18; val_offset:0*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP(fmul.h, x4, x4, x7, dyn, 96, 0, x18, 0*FLEN/8, x21, x9, x10) + +inst_1: +// rs1 == rs2 == rd, rs1==x8, rs2==x8, rd==x8,fs1 == 0 and fe1 == 0x1a and fm1 == 0x33c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x8; op2:x8; dest:x8; op1val:0x6b3c; op2val:0x6b3c; + valaddr_reg:x18; val_offset:2*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP(fmul.h, x8, x8, x8, dyn, 96, 0, x18, 2*FLEN/8, x21, x9, x10) + +inst_2: +// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==x12, rs2==x23, rd==x19,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x12; op2:x23; dest:x19; op1val:0x7aae; op2val:0x0; + valaddr_reg:x18; val_offset:4*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP(fmul.h, x19, x12, x23, dyn, 96, 0, x18, 4*FLEN/8, x21, x9, x10) + +inst_3: +// rs1 == rs2 != rd, rs1==x29, rs2==x29, rd==x23,fs1 == 0 and fe1 == 0x1e and fm1 == 0x15a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x29; op2:x29; dest:x23; op1val:0x795a; op2val:0x795a; + valaddr_reg:x18; val_offset:6*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP(fmul.h, x23, x29, x29, dyn, 96, 0, x18, 6*FLEN/8, x21, x9, x10) + +inst_4: +// rs2 == rd != rs1, rs1==x11, rs2==x1, rd==x1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x11; op2:x1; dest:x1; op1val:0x78d8; op2val:0x0; + valaddr_reg:x18; val_offset:8*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP(fmul.h, x1, x11, x1, dyn, 96, 0, x18, 8*FLEN/8, x21, x9, x10) + +inst_5: +// rs1==x5, rs2==x24, rd==x3,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x5; op2:x24; dest:x3; op1val:0x78a5; op2val:0x0; + valaddr_reg:x18; val_offset:10*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP(fmul.h, x3, x5, x24, dyn, 96, 0, x18, 10*FLEN/8, x21, x9, x10) + +inst_6: +// rs1==x3, rs2==x26, rd==x16,fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x3; op2:x26; dest:x16; op1val:0x76e3; op2val:0x0; + valaddr_reg:x18; val_offset:12*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP(fmul.h, x16, x3, x26, dyn, 96, 0, x18, 12*FLEN/8, x21, x9, x10) + +inst_7: +// rs1==x23, rs2==x20, rd==x15,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x23; op2:x20; dest:x15; op1val:0x79c8; op2val:0x0; + valaddr_reg:x18; val_offset:14*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP(fmul.h, x15, x23, x20, dyn, 96, 0, x18, 14*FLEN/8, x21, x9, x10) + +inst_8: +// rs1==x6, rs2==x31, rd==x26,fs1 == 0 and fe1 == 0x1e and fm1 == 0x397 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x6; op2:x31; dest:x26; op1val:0x7b97; op2val:0x0; + valaddr_reg:x18; val_offset:16*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP(fmul.h, x26, x6, x31, dyn, 96, 0, x18, 16*FLEN/8, x21, x9, x10) + +inst_9: +// rs1==x2, rs2==x22, rd==x12,fs1 == 0 and fe1 == 0x1d and fm1 == 0x31d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x2; op2:x22; dest:x12; op1val:0x771d; op2val:0x0; + valaddr_reg:x18; val_offset:18*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP(fmul.h, x12, x2, x22, dyn, 96, 0, x18, 18*FLEN/8, x21, x9, x10) + +inst_10: +// rs1==x17, rs2==x0, rd==x29,fs1 == 0 and fe1 == 0x1a and fm1 == 0x099 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x17; op2:x0; dest:x29; op1val:0x6899; op2val:0x0; + valaddr_reg:x18; val_offset:20*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP(fmul.h, x29, x17, x0, dyn, 96, 0, x18, 20*FLEN/8, x21, x9, x10) + +inst_11: +// rs1==x24, rs2==x3, rd==x13,fs1 == 0 and fe1 == 0x1d and fm1 == 0x36f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x24; op2:x3; dest:x13; op1val:0x776f; op2val:0x0; + valaddr_reg:x18; val_offset:22*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP(fmul.h, x13, x24, x3, dyn, 96, 0, x18, 22*FLEN/8, x21, x9, x10) + +inst_12: +// rs1==x14, rs2==x12, rd==x6,fs1 == 0 and fe1 == 0x1d and fm1 == 0x213 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x14; op2:x12; dest:x6; op1val:0x7613; op2val:0x0; + valaddr_reg:x18; val_offset:24*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP(fmul.h, x6, x14, x12, dyn, 96, 0, x18, 24*FLEN/8, x21, x9, x10) +RVTEST_VALBASEUPD(x4,test_dataset_1) + +inst_13: +// rs1==x1, rs2==x17, rd==x18,fs1 == 0 and fe1 == 0x1e and fm1 == 0x034 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x1; op2:x17; dest:x18; op1val:0x7834; op2val:0x0; + valaddr_reg:x4; val_offset:0*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP(fmul.h, x18, x1, x17, dyn, 96, 0, x4, 0*FLEN/8, x6, x9, x10) + +inst_14: +// rs1==x21, rs2==x11, rd==x27,fs1 == 0 and fe1 == 0x1c and fm1 == 0x38d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x21; op2:x11; dest:x27; op1val:0x738d; op2val:0x0; + valaddr_reg:x4; val_offset:2*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP(fmul.h, x27, x21, x11, dyn, 96, 0, x4, 2*FLEN/8, x6, x9, x10) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_15: +// rs1==x30, rs2==x19, rd==x17,fs1 == 0 and fe1 == 0x1d and fm1 == 0x133 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x19; dest:x17; op1val:0x7533; op2val:0x0; + valaddr_reg:x4; val_offset:4*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x17, x30, x19, dyn, 96, 0, x4, 4*FLEN/8, x6, x1, x3) + +inst_16: +// rs1==x15, rs2==x16, rd==x10,fs1 == 0 and fe1 == 0x1e and fm1 == 0x014 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x15; op2:x16; dest:x10; op1val:0x7814; op2val:0x0; + valaddr_reg:x4; val_offset:6*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x10, x15, x16, dyn, 96, 0, x4, 6*FLEN/8, x6, x1, x3) + +inst_17: +// rs1==x9, rs2==x21, rd==x31,fs1 == 0 and fe1 == 0x1e and fm1 == 0x164 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x9; op2:x21; dest:x31; op1val:0x7964; op2val:0x0; + valaddr_reg:x4; val_offset:8*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x9, x21, dyn, 96, 0, x4, 8*FLEN/8, x6, x1, x3) + +inst_18: +// rs1==x22, rs2==x30, rd==x0,fs1 == 0 and fe1 == 0x1e and fm1 == 0x325 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x22; op2:x30; dest:x0; op1val:0x7b25; op2val:0x0; + valaddr_reg:x4; val_offset:10*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x0, x22, x30, dyn, 96, 0, x4, 10*FLEN/8, x6, x1, x3) + +inst_19: +// rs1==x10, rs2==x27, rd==x28,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1df and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x10; op2:x27; dest:x28; op1val:0x79df; op2val:0x0; + valaddr_reg:x4; val_offset:12*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x28, x10, x27, dyn, 96, 0, x4, 12*FLEN/8, x6, x1, x3) + +inst_20: +// rs1==x16, rs2==x18, rd==x25,fs1 == 0 and fe1 == 0x1e and fm1 == 0x219 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x16; op2:x18; dest:x25; op1val:0x7a19; op2val:0x0; + valaddr_reg:x4; val_offset:14*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x25, x16, x18, dyn, 96, 0, x4, 14*FLEN/8, x6, x1, x3) + +inst_21: +// rs1==x7, rs2==x15, rd==x11,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x7; op2:x15; dest:x11; op1val:0x75a8; op2val:0x0; + valaddr_reg:x4; val_offset:16*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x11, x7, x15, dyn, 96, 0, x4, 16*FLEN/8, x6, x1, x3) + +inst_22: +// rs1==x27, rs2==x10, rd==x9,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x27; op2:x10; dest:x9; op1val:0x7bb1; op2val:0x0; + valaddr_reg:x4; val_offset:18*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x9, x27, x10, dyn, 96, 0, x4, 18*FLEN/8, x6, x1, x3) + +inst_23: +// rs1==x18, rs2==x2, rd==x21,fs1 == 0 and fe1 == 0x1e and fm1 == 0x207 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x18; op2:x2; dest:x21; op1val:0x7a07; op2val:0x0; + valaddr_reg:x4; val_offset:20*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x21, x18, x2, dyn, 96, 0, x4, 20*FLEN/8, x6, x1, x3) + +inst_24: +// rs1==x19, rs2==x14, rd==x24,fs1 == 0 and fe1 == 0x1d and fm1 == 0x361 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x19; op2:x14; dest:x24; op1val:0x7761; op2val:0x0; + valaddr_reg:x4; val_offset:22*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x24, x19, x14, dyn, 96, 0, x4, 22*FLEN/8, x6, x1, x3) + +inst_25: +// rs1==x26, rs2==x9, rd==x22,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x26; op2:x9; dest:x22; op1val:0x77d6; op2val:0x0; + valaddr_reg:x4; val_offset:24*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x22, x26, x9, dyn, 96, 0, x4, 24*FLEN/8, x6, x1, x3) + +inst_26: +// rs1==x0, rs2==x13, rd==x30,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x0; op2:x13; dest:x30; op1val:0x0; op2val:0x0; + valaddr_reg:x4; val_offset:26*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x30, x0, x13, dyn, 96, 0, x4, 26*FLEN/8, x6, x1, x3) + +inst_27: +// rs1==x20, rs2==x28, rd==x5,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x20; op2:x28; dest:x5; op1val:0x75a9; op2val:0x0; + valaddr_reg:x4; val_offset:28*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x5, x20, x28, dyn, 96, 0, x4, 28*FLEN/8, x6, x1, x3) +RVTEST_VALBASEUPD(x8,test_dataset_2) + +inst_28: +// rs1==x31, rs2==x6, rd==x2,fs1 == 0 and fe1 == 0x1e and fm1 == 0x331 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x31; op2:x6; dest:x2; op1val:0x7b31; op2val:0x0; + valaddr_reg:x8; val_offset:0*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x2, x31, x6, dyn, 96, 0, x8, 0*FLEN/8, x9, x1, x3) + +inst_29: +// rs1==x28, rs2==x4, rd==x7,fs1 == 0 and fe1 == 0x1e and fm1 == 0x08a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x28; op2:x4; dest:x7; op1val:0x788a; op2val:0x0; + valaddr_reg:x8; val_offset:2*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x7, x28, x4, dyn, 96, 0, x8, 2*FLEN/8, x9, x1, x3) + +inst_30: +// rs1==x13, rs2==x5, rd==x14,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x13; op2:x5; dest:x14; op1val:0x79c9; op2val:0x0; + valaddr_reg:x8; val_offset:4*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x14, x13, x5, dyn, 96, 0, x8, 4*FLEN/8, x9, x1, x2) + +inst_31: +// rs1==x25,fs1 == 0 and fe1 == 0x1c and fm1 == 0x318 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x25; op2:x5; dest:x24; op1val:0x7318; op2val:0x0; + valaddr_reg:x8; val_offset:6*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x24, x25, x5, dyn, 96, 0, x8, 6*FLEN/8, x9, x1, x2) + +inst_32: +// rs2==x25,fs1 == 0 and fe1 == 0x1e and fm1 == 0x198 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x16; op2:x25; dest:x18; op1val:0x7998; op2val:0x0; + valaddr_reg:x8; val_offset:8*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x18, x16, x25, dyn, 96, 0, x8, 8*FLEN/8, x9, x1, x2) + +inst_33: +// rd==x20,fs1 == 0 and fe1 == 0x1e and fm1 == 0x342 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x16; op2:x28; dest:x20; op1val:0x7b42; op2val:0x0; + valaddr_reg:x8; val_offset:10*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x20, x16, x28, dyn, 96, 0, x8, 10*FLEN/8, x9, x1, x2) + +inst_34: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x349 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b49; op2val:0x0; + valaddr_reg:x8; val_offset:12*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x8, 12*FLEN/8, x9, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_35: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba7; op2val:0x0; + valaddr_reg:x8; val_offset:14*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x8, 14*FLEN/8, x9, x1, x2) + +inst_36: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x008 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7808; op2val:0x0; + valaddr_reg:x8; val_offset:16*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x8, 16*FLEN/8, x9, x1, x2) + +inst_37: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x135 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7935; op2val:0x0; + valaddr_reg:x8; val_offset:18*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x8, 18*FLEN/8, x9, x1, x2) + +inst_38: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0fc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x74fc; op2val:0x0; + valaddr_reg:x8; val_offset:20*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x8, 20*FLEN/8, x9, x1, x2) + +inst_39: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x017 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7817; op2val:0x0; + valaddr_reg:x8; val_offset:22*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x8, 22*FLEN/8, x9, x1, x2) + +inst_40: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x78fb; op2val:0x0; + valaddr_reg:x8; val_offset:24*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x8, 24*FLEN/8, x9, x1, x2) + +inst_41: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a8f; op2val:0x0; + valaddr_reg:x8; val_offset:26*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x8, 26*FLEN/8, x9, x1, x2) + +inst_42: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x341 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x068 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b41; op2val:0x1468; + valaddr_reg:x8; val_offset:28*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x8, 28*FLEN/8, x9, x1, x2) + +inst_43: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f4 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x15f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79f4; op2val:0x155f; + valaddr_reg:x8; val_offset:30*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x8, 30*FLEN/8, x9, x1, x2) + +inst_44: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x138 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x221 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7938; op2val:0x1621; + valaddr_reg:x8; val_offset:32*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x8, 32*FLEN/8, x9, x1, x2) + +inst_45: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x33f and fs2 == 0 and fe2 == 0x07 and fm2 == 0x06a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x733f; op2val:0x1c6a; + valaddr_reg:x8; val_offset:34*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x8, 34*FLEN/8, x9, x1, x2) + +inst_46: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2cc and fs2 == 0 and fe2 == 0x08 and fm2 == 0x0b4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ecc; op2val:0x20b4; + valaddr_reg:x8; val_offset:36*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x8, 36*FLEN/8, x9, x1, x2) + +inst_47: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d4 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x0af and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ad4; op2val:0x14af; + valaddr_reg:x8; val_offset:38*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x8, 38*FLEN/8, x9, x1, x2) + +inst_48: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2bb and fs2 == 0 and fe2 == 0x07 and fm2 == 0x0c0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x72bb; op2val:0x1cc0; + valaddr_reg:x8; val_offset:40*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x8, 40*FLEN/8, x9, x1, x2) + +inst_49: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2c3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x012 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x76c3; op2val:0x12; + valaddr_reg:x8; val_offset:42*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x8, 42*FLEN/8, x9, x1, x2) + +inst_50: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x014 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0fb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6814; op2val:0xfb; + valaddr_reg:x8; val_offset:44*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x8, 44*FLEN/8, x9, x1, x2) + +inst_51: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x17f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x02e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x717f; op2val:0x2e; + valaddr_reg:x8; val_offset:46*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x8, 46*FLEN/8, x9, x1, x2) + +inst_52: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x14d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x060 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d4d; op2val:0x60; + valaddr_reg:x8; val_offset:48*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x8, 48*FLEN/8, x9, x1, x2) + +inst_53: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x27d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x13b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x667d; op2val:0x13b; + valaddr_reg:x8; val_offset:50*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x8, 50*FLEN/8, x9, x1, x2) + +inst_54: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x16a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x656a; op2val:0x17a; + valaddr_reg:x8; val_offset:52*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x8, 52*FLEN/8, x9, x1, x2) + +inst_55: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x280 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x009 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a80; op2val:0x9; + valaddr_reg:x8; val_offset:54*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x8, 54*FLEN/8, x9, x1, x2) + +inst_56: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x33c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6b3c; op2val:0x0; + valaddr_reg:x8; val_offset:56*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x8, 56*FLEN/8, x9, x1, x2) + +inst_57: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x795a; op2val:0x0; + valaddr_reg:x8; val_offset:58*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x8, 58*FLEN/8, x9, x1, x2) + +inst_58: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x099 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6899; op2val:0x0; + valaddr_reg:x8; val_offset:60*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x8, 60*FLEN/8, x9, x1, x2) + +inst_59: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x325 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b25; op2val:0x0; + valaddr_reg:x8; val_offset:62*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x8, 62*FLEN/8, x9, x1, x2) + +inst_60: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7801; op2val:0x0; + valaddr_reg:x8; val_offset:64*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x8, 64*FLEN/8, x9, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(27452,32,FLEN) +NAN_BOXED(27452,32,FLEN) +NAN_BOXED(31406,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31066,32,FLEN) +NAN_BOXED(31066,32,FLEN) +NAN_BOXED(30936,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(30885,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(30435,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31176,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31639,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(30493,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(26777,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(30575,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(30227,32,FLEN) +NAN_BOXED(0,32,FLEN) +test_dataset_1: +NAN_BOXED(30772,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(29581,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(30003,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(30740,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31076,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31525,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31199,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31257,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(30120,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31665,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31239,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(30561,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(30678,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(30121,32,FLEN) +NAN_BOXED(0,32,FLEN) +test_dataset_2: +NAN_BOXED(31537,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(30858,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31177,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(29464,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31128,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31554,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31561,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31655,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(30728,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31029,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(29948,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(30743,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(30971,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31375,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31553,16,FLEN) +NAN_BOXED(5224,16,FLEN) +NAN_BOXED(31220,16,FLEN) +NAN_BOXED(5471,16,FLEN) +NAN_BOXED(31032,16,FLEN) +NAN_BOXED(5665,16,FLEN) +NAN_BOXED(29503,16,FLEN) +NAN_BOXED(7274,16,FLEN) +NAN_BOXED(28364,16,FLEN) +NAN_BOXED(8372,16,FLEN) +NAN_BOXED(31444,16,FLEN) +NAN_BOXED(5295,16,FLEN) +NAN_BOXED(29371,16,FLEN) +NAN_BOXED(7360,16,FLEN) +NAN_BOXED(30403,16,FLEN) +NAN_BOXED(18,16,FLEN) +NAN_BOXED(26644,16,FLEN) +NAN_BOXED(251,16,FLEN) +NAN_BOXED(29055,16,FLEN) +NAN_BOXED(46,16,FLEN) +NAN_BOXED(27981,16,FLEN) +NAN_BOXED(96,16,FLEN) +NAN_BOXED(26237,16,FLEN) +NAN_BOXED(315,16,FLEN) +NAN_BOXED(25962,16,FLEN) +NAN_BOXED(378,16,FLEN) +NAN_BOXED(31360,16,FLEN) +NAN_BOXED(9,16,FLEN) +NAN_BOXED(27452,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31066,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(26777,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31525,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(30721,16,FLEN) +NAN_BOXED(0,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x9_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x9_1: + .fill 30*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_0: + .fill 40*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 52*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fmul_b8-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fmul_b8-01.S new file mode 100644 index 000000000..484450a30 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fmul_b8-01.S @@ -0,0 +1,16866 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 04:50:26 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fmul.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fmul.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fmul_b8 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fmul_b8) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x6,test_dataset_0) +RVTEST_SIGBASE(x2,signature_x2_1) + +inst_0: +// rs1 == rd != rs2, rs1==x16, rs2==x22, rd==x16,fs1 == 0 and fe1 == 0x0a and fm1 == 0x1a0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x02d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x16; op2:x22; dest:x16; op1val:0x29a0; op2val:0x2d; + valaddr_reg:x6; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fmul.h, x16, x16, x22, dyn, 0, 0, x6, 0*FLEN/8, x9, x2, x5) + +inst_1: +// rs1 == rs2 == rd, rs1==x28, rs2==x28, rd==x28,fs1 == 0 and fe1 == 0x0a and fm1 == 0x1a0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x02d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x28; op2:x28; dest:x28; op1val:0x29a0; op2val:0x29a0; + valaddr_reg:x6; val_offset:2*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fmul.h, x28, x28, x28, dyn, 32, 0, x6, 2*FLEN/8, x9, x2, x5) + +inst_2: +// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==x4, rs2==x18, rd==x11,fs1 == 0 and fe1 == 0x0a and fm1 == 0x1a0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x02d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x4; op2:x18; dest:x11; op1val:0x29a0; op2val:0x2d; + valaddr_reg:x6; val_offset:4*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fmul.h, x11, x4, x18, dyn, 64, 0, x6, 4*FLEN/8, x9, x2, x5) + +inst_3: +// rs1 == rs2 != rd, rs1==x15, rs2==x15, rd==x24,fs1 == 0 and fe1 == 0x0a and fm1 == 0x1a0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x02d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x15; op2:x15; dest:x24; op1val:0x29a0; op2val:0x29a0; + valaddr_reg:x6; val_offset:6*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fmul.h, x24, x15, x15, dyn, 96, 0, x6, 6*FLEN/8, x9, x2, x5) + +inst_4: +// rs2 == rd != rs1, rs1==x8, rs2==x23, rd==x23,fs1 == 0 and fe1 == 0x0a and fm1 == 0x1a0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x02d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x8; op2:x23; dest:x23; op1val:0x29a0; op2val:0x2d; + valaddr_reg:x6; val_offset:8*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fmul.h, x23, x8, x23, dyn, 128, 0, x6, 8*FLEN/8, x9, x2, x5) + +inst_5: +// rs1==x7, rs2==x24, rd==x1,fs1 == 0 and fe1 == 0x0e and fm1 == 0x38c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x7; op2:x24; dest:x1; op1val:0x3b8c; op2val:0x2; + valaddr_reg:x6; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fmul.h, x1, x7, x24, dyn, 0, 0, x6, 10*FLEN/8, x9, x2, x5) + +inst_6: +// rs1==x30, rs2==x12, rd==x25,fs1 == 0 and fe1 == 0x0e and fm1 == 0x38c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x12; dest:x25; op1val:0x3b8c; op2val:0x2; + valaddr_reg:x6; val_offset:12*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fmul.h, x25, x30, x12, dyn, 32, 0, x6, 12*FLEN/8, x9, x2, x5) + +inst_7: +// rs1==x29, rs2==x3, rd==x20,fs1 == 0 and fe1 == 0x0e and fm1 == 0x38c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x29; op2:x3; dest:x20; op1val:0x3b8c; op2val:0x2; + valaddr_reg:x6; val_offset:14*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fmul.h, x20, x29, x3, dyn, 64, 0, x6, 14*FLEN/8, x9, x2, x5) + +inst_8: +// rs1==x14, rs2==x17, rd==x10,fs1 == 0 and fe1 == 0x0e and fm1 == 0x38c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x14; op2:x17; dest:x10; op1val:0x3b8c; op2val:0x2; + valaddr_reg:x6; val_offset:16*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fmul.h, x10, x14, x17, dyn, 96, 0, x6, 16*FLEN/8, x9, x2, x5) + +inst_9: +// rs1==x23, rs2==x4, rd==x21,fs1 == 0 and fe1 == 0x0e and fm1 == 0x38c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x23; op2:x4; dest:x21; op1val:0x3b8c; op2val:0x2; + valaddr_reg:x6; val_offset:18*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fmul.h, x21, x23, x4, dyn, 128, 0, x6, 18*FLEN/8, x9, x2, x5) + +inst_10: +// rs1==x19, rs2==x16, rd==x27,fs1 == 0 and fe1 == 0x0c and fm1 == 0x143 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x19; op2:x16; dest:x27; op1val:0x3143; op2val:0xc; + valaddr_reg:x6; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fmul.h, x27, x19, x16, dyn, 0, 0, x6, 20*FLEN/8, x9, x2, x5) +RVTEST_VALBASEUPD(x15,test_dataset_1) + +inst_11: +// rs1==x26, rs2==x6, rd==x29,fs1 == 0 and fe1 == 0x0c and fm1 == 0x143 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x26; op2:x6; dest:x29; op1val:0x3143; op2val:0xc; + valaddr_reg:x15; val_offset:0*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x5 +*/ +TEST_FPRR_OP(fmul.h, x29, x26, x6, dyn, 32, 0, x15, 0*FLEN/8, x16, x2, x5) +RVTEST_SIGBASE(x4,signature_x4_0) + +inst_12: +// rs1==x20, rs2==x30, rd==x13,fs1 == 0 and fe1 == 0x0c and fm1 == 0x143 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x20; op2:x30; dest:x13; op1val:0x3143; op2val:0xc; + valaddr_reg:x15; val_offset:2*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x11 +*/ +TEST_FPRR_OP(fmul.h, x13, x20, x30, dyn, 64, 0, x15, 2*FLEN/8, x16, x4, x11) + +inst_13: +// rs1==x9, rs2==x19, rd==x18,fs1 == 0 and fe1 == 0x0c and fm1 == 0x143 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x9; op2:x19; dest:x18; op1val:0x3143; op2val:0xc; + valaddr_reg:x15; val_offset:4*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x11 +*/ +TEST_FPRR_OP(fmul.h, x18, x9, x19, dyn, 96, 0, x15, 4*FLEN/8, x16, x4, x11) + +inst_14: +// rs1==x2, rs2==x25, rd==x30,fs1 == 0 and fe1 == 0x0c and fm1 == 0x143 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x2; op2:x25; dest:x30; op1val:0x3143; op2val:0xc; + valaddr_reg:x15; val_offset:6*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x11 +*/ +TEST_FPRR_OP(fmul.h, x30, x2, x25, dyn, 128, 0, x15, 6*FLEN/8, x16, x4, x11) + +inst_15: +// rs1==x10, rs2==x26, rd==x6,fs1 == 0 and fe1 == 0x0d and fm1 == 0x148 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x006 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x10; op2:x26; dest:x6; op1val:0x3548; op2val:0x6; + valaddr_reg:x15; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x11 +*/ +TEST_FPRR_OP(fmul.h, x6, x10, x26, dyn, 0, 0, x15, 8*FLEN/8, x16, x4, x11) + +inst_16: +// rs1==x3, rs2==x13, rd==x12,fs1 == 0 and fe1 == 0x0d and fm1 == 0x148 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x006 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x3; op2:x13; dest:x12; op1val:0x3548; op2val:0x6; + valaddr_reg:x15; val_offset:10*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x11 +*/ +TEST_FPRR_OP(fmul.h, x12, x3, x13, dyn, 32, 0, x15, 10*FLEN/8, x16, x4, x11) + +inst_17: +// rs1==x17, rs2==x8, rd==x14,fs1 == 0 and fe1 == 0x0d and fm1 == 0x148 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x006 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x17; op2:x8; dest:x14; op1val:0x3548; op2val:0x6; + valaddr_reg:x15; val_offset:12*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x11 +*/ +TEST_FPRR_OP(fmul.h, x14, x17, x8, dyn, 64, 0, x15, 12*FLEN/8, x16, x4, x11) + +inst_18: +// rs1==x12, rs2==x31, rd==x17,fs1 == 0 and fe1 == 0x0d and fm1 == 0x148 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x006 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x12; op2:x31; dest:x17; op1val:0x3548; op2val:0x6; + valaddr_reg:x15; val_offset:14*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x11 +*/ +TEST_FPRR_OP(fmul.h, x17, x12, x31, dyn, 96, 0, x15, 14*FLEN/8, x16, x4, x11) + +inst_19: +// rs1==x22, rs2==x0, rd==x26,fs1 == 0 and fe1 == 0x0d and fm1 == 0x148 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x006 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x22; op2:x0; dest:x26; op1val:0x3548; op2val:0x0; + valaddr_reg:x15; val_offset:16*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x11 +*/ +TEST_FPRR_OP(fmul.h, x26, x22, x0, dyn, 128, 0, x15, 16*FLEN/8, x16, x4, x11) + +inst_20: +// rs1==x5, rs2==x1, rd==x8,fs1 == 0 and fe1 == 0x0d and fm1 == 0x24e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x005 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x5; op2:x1; dest:x8; op1val:0x364e; op2val:0x5; + valaddr_reg:x15; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x11 +*/ +TEST_FPRR_OP(fmul.h, x8, x5, x1, dyn, 0, 0, x15, 18*FLEN/8, x16, x4, x11) + +inst_21: +// rs1==x21, rs2==x5, rd==x7,fs1 == 0 and fe1 == 0x0d and fm1 == 0x24e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x005 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x21; op2:x5; dest:x7; op1val:0x364e; op2val:0x5; + valaddr_reg:x15; val_offset:20*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x11 +*/ +TEST_FPRR_OP(fmul.h, x7, x21, x5, dyn, 32, 0, x15, 20*FLEN/8, x16, x4, x11) +RVTEST_VALBASEUPD(x16,test_dataset_2) + +inst_22: +// rs1==x24, rs2==x29, rd==x15,fs1 == 0 and fe1 == 0x0d and fm1 == 0x24e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x005 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x24; op2:x29; dest:x15; op1val:0x364e; op2val:0x5; + valaddr_reg:x16; val_offset:0*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x11 +*/ +TEST_FPRR_OP(fmul.h, x15, x24, x29, dyn, 64, 0, x16, 0*FLEN/8, x17, x4, x11) + +inst_23: +// rs1==x27, rs2==x2, rd==x31,fs1 == 0 and fe1 == 0x0d and fm1 == 0x24e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x005 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x27; op2:x2; dest:x31; op1val:0x364e; op2val:0x5; + valaddr_reg:x16; val_offset:2*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x27, x2, dyn, 96, 0, x16, 2*FLEN/8, x17, x4, x12) +RVTEST_SIGBASE(x8,signature_x8_0) + +inst_24: +// rs1==x6, rs2==x27, rd==x9,fs1 == 0 and fe1 == 0x0d and fm1 == 0x24e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x005 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x6; op2:x27; dest:x9; op1val:0x364e; op2val:0x5; + valaddr_reg:x16; val_offset:4*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x9, x6, x27, dyn, 128, 0, x16, 4*FLEN/8, x17, x8, x12) + +inst_25: +// rs1==x31, rs2==x10, rd==x0,fs1 == 0 and fe1 == 0x0d and fm1 == 0x2b3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x004 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x31; op2:x10; dest:x0; op1val:0x36b3; op2val:0x4; + valaddr_reg:x16; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x0, x31, x10, dyn, 0, 0, x16, 6*FLEN/8, x17, x8, x12) + +inst_26: +// rs1==x1, rs2==x21, rd==x5,fs1 == 0 and fe1 == 0x0d and fm1 == 0x2b3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x004 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x1; op2:x21; dest:x5; op1val:0x36b3; op2val:0x4; + valaddr_reg:x16; val_offset:8*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x5, x1, x21, dyn, 32, 0, x16, 8*FLEN/8, x17, x8, x12) + +inst_27: +// rs1==x11, rs2==x20, rd==x19,fs1 == 0 and fe1 == 0x0d and fm1 == 0x2b3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x004 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x11; op2:x20; dest:x19; op1val:0x36b3; op2val:0x4; + valaddr_reg:x16; val_offset:10*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x19, x11, x20, dyn, 64, 0, x16, 10*FLEN/8, x17, x8, x12) + +inst_28: +// rs1==x25, rs2==x9, rd==x22,fs1 == 0 and fe1 == 0x0d and fm1 == 0x2b3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x004 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x25; op2:x9; dest:x22; op1val:0x36b3; op2val:0x4; + valaddr_reg:x16; val_offset:12*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x22, x25, x9, dyn, 96, 0, x16, 12*FLEN/8, x17, x8, x12) + +inst_29: +// rs1==x0, rs2==x7, rd==x3,fs1 == 0 and fe1 == 0x0d and fm1 == 0x2b3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x004 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x0; op2:x7; dest:x3; op1val:0x0; op2val:0x4; + valaddr_reg:x16; val_offset:14*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x3, x0, x7, dyn, 128, 0, x16, 14*FLEN/8, x17, x8, x12) + +inst_30: +// rs1==x18, rs2==x14, rd==x4,fs1 == 0 and fe1 == 0x0e and fm1 == 0x08d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x18; op2:x14; dest:x4; op1val:0x388d; op2val:0x3; + valaddr_reg:x16; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x4, x18, x14, dyn, 0, 0, x16, 16*FLEN/8, x17, x8, x12) + +inst_31: +// rs1==x13, rs2==x11, rd==x2,fs1 == 0 and fe1 == 0x0e and fm1 == 0x08d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x003 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x13; op2:x11; dest:x2; op1val:0x388d; op2val:0x3; + valaddr_reg:x16; val_offset:18*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x2, x13, x11, dyn, 32, 0, x16, 18*FLEN/8, x17, x8, x12) +RVTEST_VALBASEUPD(x1,test_dataset_3) + +inst_32: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x08d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x003 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x388d; op2val:0x3; + valaddr_reg:x1; val_offset:0*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 0*FLEN/8, x2, x8, x12) + +inst_33: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x08d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x003 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x388d; op2val:0x3; + valaddr_reg:x1; val_offset:2*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2*FLEN/8, x2, x8, x12) + +inst_34: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x08d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x003 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x388d; op2val:0x3; + valaddr_reg:x1; val_offset:4*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 4*FLEN/8, x2, x8, x12) + +inst_35: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x06e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x346e; op2val:0x7; + valaddr_reg:x1; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 6*FLEN/8, x2, x8, x12) + +inst_36: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x06e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x007 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x346e; op2val:0x7; + valaddr_reg:x1; val_offset:8*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 8*FLEN/8, x2, x8, x12) + +inst_37: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x06e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x007 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x346e; op2val:0x7; + valaddr_reg:x1; val_offset:10*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 10*FLEN/8, x2, x8, x12) + +inst_38: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x06e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x007 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x346e; op2val:0x7; + valaddr_reg:x1; val_offset:12*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 12*FLEN/8, x2, x8, x12) + +inst_39: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x06e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x007 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x346e; op2val:0x7; + valaddr_reg:x1; val_offset:14*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 14*FLEN/8, x2, x8, x12) + +inst_40: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x27a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x027 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2a7a; op2val:0x27; + valaddr_reg:x1; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 16*FLEN/8, x2, x8, x12) + +inst_41: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x27a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x027 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2a7a; op2val:0x27; + valaddr_reg:x1; val_offset:18*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 18*FLEN/8, x2, x8, x12) + +inst_42: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x27a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x027 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2a7a; op2val:0x27; + valaddr_reg:x1; val_offset:20*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 20*FLEN/8, x2, x8, x12) + +inst_43: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x27a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x027 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2a7a; op2val:0x27; + valaddr_reg:x1; val_offset:22*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 22*FLEN/8, x2, x8, x12) + +inst_44: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x27a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x027 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2a7a; op2val:0x27; + valaddr_reg:x1; val_offset:24*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 24*FLEN/8, x2, x8, x12) + +inst_45: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x070 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3870; op2val:0x3; + valaddr_reg:x1; val_offset:26*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 26*FLEN/8, x2, x8, x12) + +inst_46: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x070 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x003 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3870; op2val:0x3; + valaddr_reg:x1; val_offset:28*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 28*FLEN/8, x2, x8, x12) + +inst_47: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x070 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x003 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3870; op2val:0x3; + valaddr_reg:x1; val_offset:30*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 30*FLEN/8, x2, x8, x12) + +inst_48: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x070 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x003 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3870; op2val:0x3; + valaddr_reg:x1; val_offset:32*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 32*FLEN/8, x2, x8, x12) + +inst_49: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x070 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x003 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3870; op2val:0x3; + valaddr_reg:x1; val_offset:34*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 34*FLEN/8, x2, x8, x12) + +inst_50: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bb6; op2val:0x2; + valaddr_reg:x1; val_offset:36*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 36*FLEN/8, x2, x8, x12) + +inst_51: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bb6; op2val:0x2; + valaddr_reg:x1; val_offset:38*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 38*FLEN/8, x2, x8, x12) + +inst_52: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bb6; op2val:0x2; + valaddr_reg:x1; val_offset:40*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 40*FLEN/8, x2, x8, x12) + +inst_53: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bb6; op2val:0x2; + valaddr_reg:x1; val_offset:42*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 42*FLEN/8, x2, x8, x12) + +inst_54: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bb6; op2val:0x2; + valaddr_reg:x1; val_offset:44*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 44*FLEN/8, x2, x8, x12) + +inst_55: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x047 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3847; op2val:0x3; + valaddr_reg:x1; val_offset:46*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 46*FLEN/8, x2, x8, x12) + +inst_56: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x047 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x003 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3847; op2val:0x3; + valaddr_reg:x1; val_offset:48*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 48*FLEN/8, x2, x8, x12) + +inst_57: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x047 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x003 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3847; op2val:0x3; + valaddr_reg:x1; val_offset:50*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 50*FLEN/8, x2, x8, x12) + +inst_58: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x047 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x003 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3847; op2val:0x3; + valaddr_reg:x1; val_offset:52*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 52*FLEN/8, x2, x8, x12) + +inst_59: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x047 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x003 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3847; op2val:0x3; + valaddr_reg:x1; val_offset:54*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 54*FLEN/8, x2, x8, x12) + +inst_60: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x38f5; op2val:0x3; + valaddr_reg:x1; val_offset:56*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 56*FLEN/8, x2, x8, x12) + +inst_61: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x003 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x38f5; op2val:0x3; + valaddr_reg:x1; val_offset:58*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 58*FLEN/8, x2, x8, x12) + +inst_62: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x003 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x38f5; op2val:0x3; + valaddr_reg:x1; val_offset:60*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 60*FLEN/8, x2, x8, x12) + +inst_63: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x003 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x38f5; op2val:0x3; + valaddr_reg:x1; val_offset:62*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 62*FLEN/8, x2, x8, x12) + +inst_64: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x003 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x38f5; op2val:0x3; + valaddr_reg:x1; val_offset:64*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 64*FLEN/8, x2, x8, x12) + +inst_65: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x396 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x004 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3796; op2val:0x4; + valaddr_reg:x1; val_offset:66*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 66*FLEN/8, x2, x8, x12) + +inst_66: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x396 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x004 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3796; op2val:0x4; + valaddr_reg:x1; val_offset:68*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 68*FLEN/8, x2, x8, x12) + +inst_67: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x396 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x004 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3796; op2val:0x4; + valaddr_reg:x1; val_offset:70*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 70*FLEN/8, x2, x8, x12) + +inst_68: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x396 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x004 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3796; op2val:0x4; + valaddr_reg:x1; val_offset:72*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 72*FLEN/8, x2, x8, x12) + +inst_69: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x396 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x004 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3796; op2val:0x4; + valaddr_reg:x1; val_offset:74*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 74*FLEN/8, x2, x8, x12) + +inst_70: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x21c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a1c; op2val:0x2; + valaddr_reg:x1; val_offset:76*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 76*FLEN/8, x2, x8, x12) + +inst_71: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x21c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a1c; op2val:0x2; + valaddr_reg:x1; val_offset:78*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 78*FLEN/8, x2, x8, x12) + +inst_72: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x21c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a1c; op2val:0x2; + valaddr_reg:x1; val_offset:80*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 80*FLEN/8, x2, x8, x12) + +inst_73: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x21c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a1c; op2val:0x2; + valaddr_reg:x1; val_offset:82*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 82*FLEN/8, x2, x8, x12) + +inst_74: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x21c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a1c; op2val:0x2; + valaddr_reg:x1; val_offset:84*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 84*FLEN/8, x2, x8, x12) + +inst_75: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x166 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3966; op2val:0x2; + valaddr_reg:x1; val_offset:86*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 86*FLEN/8, x2, x8, x12) + +inst_76: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x166 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3966; op2val:0x2; + valaddr_reg:x1; val_offset:88*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 88*FLEN/8, x2, x8, x12) + +inst_77: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x166 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3966; op2val:0x2; + valaddr_reg:x1; val_offset:90*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 90*FLEN/8, x2, x8, x12) + +inst_78: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x166 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3966; op2val:0x2; + valaddr_reg:x1; val_offset:92*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 92*FLEN/8, x2, x8, x12) + +inst_79: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x166 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3966; op2val:0x2; + valaddr_reg:x1; val_offset:94*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 94*FLEN/8, x2, x8, x12) + +inst_80: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x004 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x37d6; op2val:0x4; + valaddr_reg:x1; val_offset:96*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 96*FLEN/8, x2, x8, x12) + +inst_81: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x004 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x37d6; op2val:0x4; + valaddr_reg:x1; val_offset:98*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 98*FLEN/8, x2, x8, x12) + +inst_82: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x004 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x37d6; op2val:0x4; + valaddr_reg:x1; val_offset:100*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 100*FLEN/8, x2, x8, x12) + +inst_83: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x004 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x37d6; op2val:0x4; + valaddr_reg:x1; val_offset:102*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 102*FLEN/8, x2, x8, x12) + +inst_84: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x004 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x37d6; op2val:0x4; + valaddr_reg:x1; val_offset:104*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 104*FLEN/8, x2, x8, x12) + +inst_85: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x135 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x006 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3535; op2val:0x6; + valaddr_reg:x1; val_offset:106*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 106*FLEN/8, x2, x8, x12) + +inst_86: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x135 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x006 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3535; op2val:0x6; + valaddr_reg:x1; val_offset:108*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 108*FLEN/8, x2, x8, x12) + +inst_87: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x135 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x006 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3535; op2val:0x6; + valaddr_reg:x1; val_offset:110*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 110*FLEN/8, x2, x8, x12) + +inst_88: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x135 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x006 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3535; op2val:0x6; + valaddr_reg:x1; val_offset:112*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 112*FLEN/8, x2, x8, x12) + +inst_89: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x135 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x006 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3535; op2val:0x6; + valaddr_reg:x1; val_offset:114*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 114*FLEN/8, x2, x8, x12) + +inst_90: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2cf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x012 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ecf; op2val:0x12; + valaddr_reg:x1; val_offset:116*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 116*FLEN/8, x2, x8, x12) + +inst_91: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2cf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x012 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ecf; op2val:0x12; + valaddr_reg:x1; val_offset:118*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 118*FLEN/8, x2, x8, x12) + +inst_92: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2cf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x012 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ecf; op2val:0x12; + valaddr_reg:x1; val_offset:120*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 120*FLEN/8, x2, x8, x12) + +inst_93: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2cf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x012 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ecf; op2val:0x12; + valaddr_reg:x1; val_offset:122*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 122*FLEN/8, x2, x8, x12) + +inst_94: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2cf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x012 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ecf; op2val:0x12; + valaddr_reg:x1; val_offset:124*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 124*FLEN/8, x2, x8, x12) + +inst_95: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x03f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x343f; op2val:0x7; + valaddr_reg:x1; val_offset:126*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 126*FLEN/8, x2, x8, x12) + +inst_96: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x03f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x007 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x343f; op2val:0x7; + valaddr_reg:x1; val_offset:128*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 128*FLEN/8, x2, x8, x12) + +inst_97: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x03f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x007 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x343f; op2val:0x7; + valaddr_reg:x1; val_offset:130*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 130*FLEN/8, x2, x8, x12) + +inst_98: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x03f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x007 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x343f; op2val:0x7; + valaddr_reg:x1; val_offset:132*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 132*FLEN/8, x2, x8, x12) + +inst_99: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x03f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x007 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x343f; op2val:0x7; + valaddr_reg:x1; val_offset:134*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 134*FLEN/8, x2, x8, x12) + +inst_100: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x396 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x008 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3396; op2val:0x8; + valaddr_reg:x1; val_offset:136*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 136*FLEN/8, x2, x8, x12) + +inst_101: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x396 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x008 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3396; op2val:0x8; + valaddr_reg:x1; val_offset:138*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 138*FLEN/8, x2, x8, x12) + +inst_102: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x396 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x008 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3396; op2val:0x8; + valaddr_reg:x1; val_offset:140*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 140*FLEN/8, x2, x8, x12) + +inst_103: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x396 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x008 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3396; op2val:0x8; + valaddr_reg:x1; val_offset:142*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 142*FLEN/8, x2, x8, x12) + +inst_104: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x396 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x008 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3396; op2val:0x8; + valaddr_reg:x1; val_offset:144*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 144*FLEN/8, x2, x8, x12) + +inst_105: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x12b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x392b; op2val:0x3; + valaddr_reg:x1; val_offset:146*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 146*FLEN/8, x2, x8, x12) + +inst_106: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x12b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x003 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x392b; op2val:0x3; + valaddr_reg:x1; val_offset:148*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 148*FLEN/8, x2, x8, x12) + +inst_107: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x12b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x003 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x392b; op2val:0x3; + valaddr_reg:x1; val_offset:150*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 150*FLEN/8, x2, x8, x12) + +inst_108: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x12b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x003 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x392b; op2val:0x3; + valaddr_reg:x1; val_offset:152*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 152*FLEN/8, x2, x8, x12) + +inst_109: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x12b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x003 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x392b; op2val:0x3; + valaddr_reg:x1; val_offset:154*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 154*FLEN/8, x2, x8, x12) + +inst_110: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x0e0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x034 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x28e0; op2val:0x34; + valaddr_reg:x1; val_offset:156*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 156*FLEN/8, x2, x8, x12) + +inst_111: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x0e0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x034 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x28e0; op2val:0x34; + valaddr_reg:x1; val_offset:158*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 158*FLEN/8, x2, x8, x12) + +inst_112: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x0e0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x034 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x28e0; op2val:0x34; + valaddr_reg:x1; val_offset:160*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 160*FLEN/8, x2, x8, x12) + +inst_113: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x0e0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x034 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x28e0; op2val:0x34; + valaddr_reg:x1; val_offset:162*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 162*FLEN/8, x2, x8, x12) + +inst_114: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x0e0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x034 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x28e0; op2val:0x34; + valaddr_reg:x1; val_offset:164*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 164*FLEN/8, x2, x8, x12) + +inst_115: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3df and fs2 == 0 and fe2 == 0x00 and fm2 == 0x008 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x33df; op2val:0x8; + valaddr_reg:x1; val_offset:166*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 166*FLEN/8, x2, x8, x12) + +inst_116: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3df and fs2 == 0 and fe2 == 0x00 and fm2 == 0x008 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x33df; op2val:0x8; + valaddr_reg:x1; val_offset:168*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 168*FLEN/8, x2, x8, x12) + +inst_117: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3df and fs2 == 0 and fe2 == 0x00 and fm2 == 0x008 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x33df; op2val:0x8; + valaddr_reg:x1; val_offset:170*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 170*FLEN/8, x2, x8, x12) + +inst_118: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3df and fs2 == 0 and fe2 == 0x00 and fm2 == 0x008 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x33df; op2val:0x8; + valaddr_reg:x1; val_offset:172*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 172*FLEN/8, x2, x8, x12) + +inst_119: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3df and fs2 == 0 and fe2 == 0x00 and fm2 == 0x008 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x33df; op2val:0x8; + valaddr_reg:x1; val_offset:174*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 174*FLEN/8, x2, x8, x12) + +inst_120: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x04f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x384f; op2val:0x3; + valaddr_reg:x1; val_offset:176*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 176*FLEN/8, x2, x8, x12) + +inst_121: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x04f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x003 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x384f; op2val:0x3; + valaddr_reg:x1; val_offset:178*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 178*FLEN/8, x2, x8, x12) + +inst_122: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x04f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x003 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x384f; op2val:0x3; + valaddr_reg:x1; val_offset:180*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 180*FLEN/8, x2, x8, x12) + +inst_123: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x04f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x003 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x384f; op2val:0x3; + valaddr_reg:x1; val_offset:182*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 182*FLEN/8, x2, x8, x12) + +inst_124: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x04f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x003 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x384f; op2val:0x3; + valaddr_reg:x1; val_offset:184*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 184*FLEN/8, x2, x8, x12) + +inst_125: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x014 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3814; op2val:0x3; + valaddr_reg:x1; val_offset:186*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 186*FLEN/8, x2, x8, x12) + +inst_126: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x014 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x003 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3814; op2val:0x3; + valaddr_reg:x1; val_offset:188*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 188*FLEN/8, x2, x8, x12) + +inst_127: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x014 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x003 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3814; op2val:0x3; + valaddr_reg:x1; val_offset:190*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 190*FLEN/8, x2, x8, x12) + +inst_128: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x014 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x003 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3814; op2val:0x3; + valaddr_reg:x1; val_offset:192*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 192*FLEN/8, x2, x8, x12) + +inst_129: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x014 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x003 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3814; op2val:0x3; + valaddr_reg:x1; val_offset:194*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 194*FLEN/8, x2, x8, x12) + +inst_130: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x004 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x37fc; op2val:0x4; + valaddr_reg:x1; val_offset:196*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 196*FLEN/8, x2, x8, x12) + +inst_131: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x004 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x37fc; op2val:0x4; + valaddr_reg:x1; val_offset:198*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 198*FLEN/8, x2, x8, x12) + +inst_132: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x004 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x37fc; op2val:0x4; + valaddr_reg:x1; val_offset:200*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 200*FLEN/8, x2, x8, x12) + +inst_133: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x004 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x37fc; op2val:0x4; + valaddr_reg:x1; val_offset:202*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 202*FLEN/8, x2, x8, x12) + +inst_134: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x004 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x37fc; op2val:0x4; + valaddr_reg:x1; val_offset:204*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 204*FLEN/8, x2, x8, x12) + +inst_135: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x26b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x013 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e6b; op2val:0x13; + valaddr_reg:x1; val_offset:206*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 206*FLEN/8, x2, x8, x12) + +inst_136: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x26b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x013 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e6b; op2val:0x13; + valaddr_reg:x1; val_offset:208*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 208*FLEN/8, x2, x8, x12) + +inst_137: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x26b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x013 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e6b; op2val:0x13; + valaddr_reg:x1; val_offset:210*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 210*FLEN/8, x2, x8, x12) + +inst_138: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x26b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x013 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e6b; op2val:0x13; + valaddr_reg:x1; val_offset:212*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 212*FLEN/8, x2, x8, x12) + +inst_139: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x26b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x013 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e6b; op2val:0x13; + valaddr_reg:x1; val_offset:214*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 214*FLEN/8, x2, x8, x12) + +inst_140: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2ea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x004 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x36ea; op2val:0x4; + valaddr_reg:x1; val_offset:216*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 216*FLEN/8, x2, x8, x12) + +inst_141: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2ea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x004 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x36ea; op2val:0x4; + valaddr_reg:x1; val_offset:218*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 218*FLEN/8, x2, x8, x12) + +inst_142: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2ea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x004 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x36ea; op2val:0x4; + valaddr_reg:x1; val_offset:220*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 220*FLEN/8, x2, x8, x12) + +inst_143: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2ea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x004 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x36ea; op2val:0x4; + valaddr_reg:x1; val_offset:222*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 222*FLEN/8, x2, x8, x12) + +inst_144: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2ea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x004 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x36ea; op2val:0x4; + valaddr_reg:x1; val_offset:224*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 224*FLEN/8, x2, x8, x12) + +inst_145: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x06b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x346b; op2val:0x7; + valaddr_reg:x1; val_offset:226*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 226*FLEN/8, x2, x8, x12) + +inst_146: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x06b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x007 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x346b; op2val:0x7; + valaddr_reg:x1; val_offset:228*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 228*FLEN/8, x2, x8, x12) + +inst_147: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x06b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x007 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x346b; op2val:0x7; + valaddr_reg:x1; val_offset:230*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 230*FLEN/8, x2, x8, x12) + +inst_148: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x06b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x007 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x346b; op2val:0x7; + valaddr_reg:x1; val_offset:232*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 232*FLEN/8, x2, x8, x12) + +inst_149: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x06b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x007 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x346b; op2val:0x7; + valaddr_reg:x1; val_offset:234*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 234*FLEN/8, x2, x8, x12) + +inst_150: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x239 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a39; op2val:0x2; + valaddr_reg:x1; val_offset:236*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 236*FLEN/8, x2, x8, x12) + +inst_151: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x239 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a39; op2val:0x2; + valaddr_reg:x1; val_offset:238*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 238*FLEN/8, x2, x8, x12) +RVTEST_SIGBASE(x8,signature_x8_1) + +inst_152: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x239 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a39; op2val:0x2; + valaddr_reg:x1; val_offset:240*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 240*FLEN/8, x2, x8, x12) + +inst_153: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x239 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a39; op2val:0x2; + valaddr_reg:x1; val_offset:242*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 242*FLEN/8, x2, x8, x12) + +inst_154: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x239 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a39; op2val:0x2; + valaddr_reg:x1; val_offset:244*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 244*FLEN/8, x2, x8, x12) + +inst_155: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ce and fs2 == 0 and fe2 == 0x00 and fm2 == 0x006 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x34ce; op2val:0x6; + valaddr_reg:x1; val_offset:246*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 246*FLEN/8, x2, x8, x12) + +inst_156: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ce and fs2 == 0 and fe2 == 0x00 and fm2 == 0x006 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x34ce; op2val:0x6; + valaddr_reg:x1; val_offset:248*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 248*FLEN/8, x2, x8, x12) + +inst_157: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ce and fs2 == 0 and fe2 == 0x00 and fm2 == 0x006 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x34ce; op2val:0x6; + valaddr_reg:x1; val_offset:250*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 250*FLEN/8, x2, x8, x12) + +inst_158: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ce and fs2 == 0 and fe2 == 0x00 and fm2 == 0x006 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x34ce; op2val:0x6; + valaddr_reg:x1; val_offset:252*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 252*FLEN/8, x2, x8, x12) + +inst_159: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ce and fs2 == 0 and fe2 == 0x00 and fm2 == 0x006 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x34ce; op2val:0x6; + valaddr_reg:x1; val_offset:254*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 254*FLEN/8, x2, x8, x12) + +inst_160: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1e4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x015 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2de4; op2val:0x15; + valaddr_reg:x1; val_offset:256*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 256*FLEN/8, x2, x8, x12) + +inst_161: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1e4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x015 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2de4; op2val:0x15; + valaddr_reg:x1; val_offset:258*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 258*FLEN/8, x2, x8, x12) + +inst_162: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1e4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x015 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2de4; op2val:0x15; + valaddr_reg:x1; val_offset:260*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 260*FLEN/8, x2, x8, x12) + +inst_163: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1e4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x015 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2de4; op2val:0x15; + valaddr_reg:x1; val_offset:262*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 262*FLEN/8, x2, x8, x12) + +inst_164: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1e4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x015 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2de4; op2val:0x15; + valaddr_reg:x1; val_offset:264*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 264*FLEN/8, x2, x8, x12) + +inst_165: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1ab and fs2 == 0 and fe2 == 0x00 and fm2 == 0x016 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2dab; op2val:0x16; + valaddr_reg:x1; val_offset:266*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 266*FLEN/8, x2, x8, x12) + +inst_166: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1ab and fs2 == 0 and fe2 == 0x00 and fm2 == 0x016 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2dab; op2val:0x16; + valaddr_reg:x1; val_offset:268*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 268*FLEN/8, x2, x8, x12) + +inst_167: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1ab and fs2 == 0 and fe2 == 0x00 and fm2 == 0x016 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2dab; op2val:0x16; + valaddr_reg:x1; val_offset:270*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 270*FLEN/8, x2, x8, x12) + +inst_168: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1ab and fs2 == 0 and fe2 == 0x00 and fm2 == 0x016 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2dab; op2val:0x16; + valaddr_reg:x1; val_offset:272*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 272*FLEN/8, x2, x8, x12) + +inst_169: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1ab and fs2 == 0 and fe2 == 0x00 and fm2 == 0x016 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2dab; op2val:0x16; + valaddr_reg:x1; val_offset:274*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 274*FLEN/8, x2, x8, x12) + +inst_170: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x175 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x02e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2975; op2val:0x2e; + valaddr_reg:x1; val_offset:276*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 276*FLEN/8, x2, x8, x12) + +inst_171: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x175 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x02e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2975; op2val:0x2e; + valaddr_reg:x1; val_offset:278*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 278*FLEN/8, x2, x8, x12) + +inst_172: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x175 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x02e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2975; op2val:0x2e; + valaddr_reg:x1; val_offset:280*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 280*FLEN/8, x2, x8, x12) + +inst_173: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x175 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x02e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2975; op2val:0x2e; + valaddr_reg:x1; val_offset:282*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 282*FLEN/8, x2, x8, x12) + +inst_174: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x175 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x02e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2975; op2val:0x2e; + valaddr_reg:x1; val_offset:284*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 284*FLEN/8, x2, x8, x12) + +inst_175: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x004 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x37ee; op2val:0x4; + valaddr_reg:x1; val_offset:286*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 286*FLEN/8, x2, x8, x12) + +inst_176: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x004 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x37ee; op2val:0x4; + valaddr_reg:x1; val_offset:288*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 288*FLEN/8, x2, x8, x12) + +inst_177: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x004 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x37ee; op2val:0x4; + valaddr_reg:x1; val_offset:290*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 290*FLEN/8, x2, x8, x12) + +inst_178: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x004 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x37ee; op2val:0x4; + valaddr_reg:x1; val_offset:292*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 292*FLEN/8, x2, x8, x12) + +inst_179: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x004 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x37ee; op2val:0x4; + valaddr_reg:x1; val_offset:294*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 294*FLEN/8, x2, x8, x12) + +inst_180: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x193 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x005 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3593; op2val:0x5; + valaddr_reg:x1; val_offset:296*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 296*FLEN/8, x2, x8, x12) + +inst_181: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x193 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x005 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3593; op2val:0x5; + valaddr_reg:x1; val_offset:298*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 298*FLEN/8, x2, x8, x12) + +inst_182: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x193 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x005 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3593; op2val:0x5; + valaddr_reg:x1; val_offset:300*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 300*FLEN/8, x2, x8, x12) + +inst_183: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x193 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x005 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3593; op2val:0x5; + valaddr_reg:x1; val_offset:302*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 302*FLEN/8, x2, x8, x12) + +inst_184: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x193 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x005 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3593; op2val:0x5; + valaddr_reg:x1; val_offset:304*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 304*FLEN/8, x2, x8, x12) + +inst_185: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x181 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3981; op2val:0x2; + valaddr_reg:x1; val_offset:306*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 306*FLEN/8, x2, x8, x12) + +inst_186: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x181 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3981; op2val:0x2; + valaddr_reg:x1; val_offset:308*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 308*FLEN/8, x2, x8, x12) + +inst_187: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x181 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3981; op2val:0x2; + valaddr_reg:x1; val_offset:310*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 310*FLEN/8, x2, x8, x12) + +inst_188: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x181 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3981; op2val:0x2; + valaddr_reg:x1; val_offset:312*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 312*FLEN/8, x2, x8, x12) + +inst_189: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x181 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3981; op2val:0x2; + valaddr_reg:x1; val_offset:314*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 314*FLEN/8, x2, x8, x12) + +inst_190: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3cf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x004 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x37cf; op2val:0x4; + valaddr_reg:x1; val_offset:316*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 316*FLEN/8, x2, x8, x12) + +inst_191: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3cf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x004 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x37cf; op2val:0x4; + valaddr_reg:x1; val_offset:318*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 318*FLEN/8, x2, x8, x12) + +inst_192: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3cf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x004 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x37cf; op2val:0x4; + valaddr_reg:x1; val_offset:320*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 320*FLEN/8, x2, x8, x12) + +inst_193: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3cf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x004 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x37cf; op2val:0x4; + valaddr_reg:x1; val_offset:322*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 322*FLEN/8, x2, x8, x12) + +inst_194: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3cf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x004 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x37cf; op2val:0x4; + valaddr_reg:x1; val_offset:324*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 324*FLEN/8, x2, x8, x12) + +inst_195: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x207 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x005 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3607; op2val:0x5; + valaddr_reg:x1; val_offset:326*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 326*FLEN/8, x2, x8, x12) + +inst_196: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x207 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x005 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3607; op2val:0x5; + valaddr_reg:x1; val_offset:328*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 328*FLEN/8, x2, x8, x12) + +inst_197: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x207 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x005 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3607; op2val:0x5; + valaddr_reg:x1; val_offset:330*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 330*FLEN/8, x2, x8, x12) + +inst_198: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x207 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x005 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3607; op2val:0x5; + valaddr_reg:x1; val_offset:332*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 332*FLEN/8, x2, x8, x12) + +inst_199: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x207 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x005 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3607; op2val:0x5; + valaddr_reg:x1; val_offset:334*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 334*FLEN/8, x2, x8, x12) + +inst_200: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1bf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x31bf; op2val:0xb; + valaddr_reg:x1; val_offset:336*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 336*FLEN/8, x2, x8, x12) + +inst_201: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1bf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x31bf; op2val:0xb; + valaddr_reg:x1; val_offset:338*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 338*FLEN/8, x2, x8, x12) + +inst_202: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1bf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x31bf; op2val:0xb; + valaddr_reg:x1; val_offset:340*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 340*FLEN/8, x2, x8, x12) + +inst_203: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1bf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x31bf; op2val:0xb; + valaddr_reg:x1; val_offset:342*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 342*FLEN/8, x2, x8, x12) + +inst_204: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1bf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x31bf; op2val:0xb; + valaddr_reg:x1; val_offset:344*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 344*FLEN/8, x2, x8, x12) + +inst_205: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1e9 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x166 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2de9; op2val:0x1166; + valaddr_reg:x1; val_offset:346*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 346*FLEN/8, x2, x8, x12) + +inst_206: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1e9 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x166 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2de9; op2val:0x1166; + valaddr_reg:x1; val_offset:348*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 348*FLEN/8, x2, x8, x12) + +inst_207: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1e9 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x166 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2de9; op2val:0x1166; + valaddr_reg:x1; val_offset:350*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 350*FLEN/8, x2, x8, x12) + +inst_208: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1e9 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x166 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2de9; op2val:0x1166; + valaddr_reg:x1; val_offset:352*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 352*FLEN/8, x2, x8, x12) + +inst_209: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1e9 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x166 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2de9; op2val:0x1166; + valaddr_reg:x1; val_offset:354*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 354*FLEN/8, x2, x8, x12) + +inst_210: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x015 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3d1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3415; op2val:0xbd1; + valaddr_reg:x1; val_offset:356*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 356*FLEN/8, x2, x8, x12) + +inst_211: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x015 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3d1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3415; op2val:0xbd1; + valaddr_reg:x1; val_offset:358*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 358*FLEN/8, x2, x8, x12) + +inst_212: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x015 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3d1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3415; op2val:0xbd1; + valaddr_reg:x1; val_offset:360*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 360*FLEN/8, x2, x8, x12) + +inst_213: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x015 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3d1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3415; op2val:0xbd1; + valaddr_reg:x1; val_offset:362*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 362*FLEN/8, x2, x8, x12) + +inst_214: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x015 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3d1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3415; op2val:0xbd1; + valaddr_reg:x1; val_offset:364*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 364*FLEN/8, x2, x8, x12) + +inst_215: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x18d and fs2 == 0 and fe2 == 0x02 and fm2 == 0x1c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x358d; op2val:0x9c0; + valaddr_reg:x1; val_offset:366*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 366*FLEN/8, x2, x8, x12) + +inst_216: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x18d and fs2 == 0 and fe2 == 0x02 and fm2 == 0x1c0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x358d; op2val:0x9c0; + valaddr_reg:x1; val_offset:368*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 368*FLEN/8, x2, x8, x12) + +inst_217: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x18d and fs2 == 0 and fe2 == 0x02 and fm2 == 0x1c0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x358d; op2val:0x9c0; + valaddr_reg:x1; val_offset:370*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 370*FLEN/8, x2, x8, x12) + +inst_218: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x18d and fs2 == 0 and fe2 == 0x02 and fm2 == 0x1c0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x358d; op2val:0x9c0; + valaddr_reg:x1; val_offset:372*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 372*FLEN/8, x2, x8, x12) + +inst_219: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x18d and fs2 == 0 and fe2 == 0x02 and fm2 == 0x1c0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x358d; op2val:0x9c0; + valaddr_reg:x1; val_offset:374*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 374*FLEN/8, x2, x8, x12) + +inst_220: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x22f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x129 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a2f; op2val:0x529; + valaddr_reg:x1; val_offset:376*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 376*FLEN/8, x2, x8, x12) + +inst_221: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x22f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x129 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a2f; op2val:0x529; + valaddr_reg:x1; val_offset:378*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 378*FLEN/8, x2, x8, x12) + +inst_222: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x22f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x129 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a2f; op2val:0x529; + valaddr_reg:x1; val_offset:380*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 380*FLEN/8, x2, x8, x12) + +inst_223: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x22f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x129 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a2f; op2val:0x529; + valaddr_reg:x1; val_offset:382*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 382*FLEN/8, x2, x8, x12) + +inst_224: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x22f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x129 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a2f; op2val:0x529; + valaddr_reg:x1; val_offset:384*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 384*FLEN/8, x2, x8, x12) + +inst_225: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x326 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x077 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b26; op2val:0x477; + valaddr_reg:x1; val_offset:386*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 386*FLEN/8, x2, x8, x12) + +inst_226: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x326 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x077 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b26; op2val:0x477; + valaddr_reg:x1; val_offset:388*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 388*FLEN/8, x2, x8, x12) + +inst_227: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x326 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x077 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b26; op2val:0x477; + valaddr_reg:x1; val_offset:390*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 390*FLEN/8, x2, x8, x12) + +inst_228: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x326 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x077 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b26; op2val:0x477; + valaddr_reg:x1; val_offset:392*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 392*FLEN/8, x2, x8, x12) + +inst_229: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x326 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x077 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b26; op2val:0x477; + valaddr_reg:x1; val_offset:394*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 394*FLEN/8, x2, x8, x12) + +inst_230: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0ac and fs2 == 0 and fe2 == 0x03 and fm2 == 0x2d4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x30ac; op2val:0xed4; + valaddr_reg:x1; val_offset:396*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 396*FLEN/8, x2, x8, x12) + +inst_231: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0ac and fs2 == 0 and fe2 == 0x03 and fm2 == 0x2d4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x30ac; op2val:0xed4; + valaddr_reg:x1; val_offset:398*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 398*FLEN/8, x2, x8, x12) + +inst_232: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0ac and fs2 == 0 and fe2 == 0x03 and fm2 == 0x2d4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x30ac; op2val:0xed4; + valaddr_reg:x1; val_offset:400*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 400*FLEN/8, x2, x8, x12) + +inst_233: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0ac and fs2 == 0 and fe2 == 0x03 and fm2 == 0x2d4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x30ac; op2val:0xed4; + valaddr_reg:x1; val_offset:402*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 402*FLEN/8, x2, x8, x12) + +inst_234: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0ac and fs2 == 0 and fe2 == 0x03 and fm2 == 0x2d4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x30ac; op2val:0xed4; + valaddr_reg:x1; val_offset:404*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 404*FLEN/8, x2, x8, x12) + +inst_235: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x250 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a50; op2val:0x50e; + valaddr_reg:x1; val_offset:406*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 406*FLEN/8, x2, x8, x12) + +inst_236: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x250 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a50; op2val:0x50e; + valaddr_reg:x1; val_offset:408*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 408*FLEN/8, x2, x8, x12) + +inst_237: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x250 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a50; op2val:0x50e; + valaddr_reg:x1; val_offset:410*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 410*FLEN/8, x2, x8, x12) + +inst_238: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x250 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a50; op2val:0x50e; + valaddr_reg:x1; val_offset:412*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 412*FLEN/8, x2, x8, x12) + +inst_239: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x250 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a50; op2val:0x50e; + valaddr_reg:x1; val_offset:414*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 414*FLEN/8, x2, x8, x12) + +inst_240: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x09d and fs2 == 0 and fe2 == 0x01 and fm2 == 0x2eb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x389d; op2val:0x6eb; + valaddr_reg:x1; val_offset:416*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 416*FLEN/8, x2, x8, x12) + +inst_241: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x09d and fs2 == 0 and fe2 == 0x01 and fm2 == 0x2eb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x389d; op2val:0x6eb; + valaddr_reg:x1; val_offset:418*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 418*FLEN/8, x2, x8, x12) + +inst_242: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x09d and fs2 == 0 and fe2 == 0x01 and fm2 == 0x2eb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x389d; op2val:0x6eb; + valaddr_reg:x1; val_offset:420*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 420*FLEN/8, x2, x8, x12) + +inst_243: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x09d and fs2 == 0 and fe2 == 0x01 and fm2 == 0x2eb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x389d; op2val:0x6eb; + valaddr_reg:x1; val_offset:422*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 422*FLEN/8, x2, x8, x12) + +inst_244: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x09d and fs2 == 0 and fe2 == 0x01 and fm2 == 0x2eb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x389d; op2val:0x6eb; + valaddr_reg:x1; val_offset:424*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 424*FLEN/8, x2, x8, x12) + +inst_245: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3be and fs2 == 0 and fe2 == 0x01 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bbe; op2val:0x41f; + valaddr_reg:x1; val_offset:426*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 426*FLEN/8, x2, x8, x12) + +inst_246: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3be and fs2 == 0 and fe2 == 0x01 and fm2 == 0x01f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bbe; op2val:0x41f; + valaddr_reg:x1; val_offset:428*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 428*FLEN/8, x2, x8, x12) + +inst_247: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3be and fs2 == 0 and fe2 == 0x01 and fm2 == 0x01f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bbe; op2val:0x41f; + valaddr_reg:x1; val_offset:430*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 430*FLEN/8, x2, x8, x12) + +inst_248: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3be and fs2 == 0 and fe2 == 0x01 and fm2 == 0x01f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bbe; op2val:0x41f; + valaddr_reg:x1; val_offset:432*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 432*FLEN/8, x2, x8, x12) + +inst_249: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3be and fs2 == 0 and fe2 == 0x01 and fm2 == 0x01f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bbe; op2val:0x41f; + valaddr_reg:x1; val_offset:434*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 434*FLEN/8, x2, x8, x12) + +inst_250: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2a0 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0d2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aa0; op2val:0x4d2; + valaddr_reg:x1; val_offset:436*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 436*FLEN/8, x2, x8, x12) + +inst_251: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2a0 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0d2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aa0; op2val:0x4d2; + valaddr_reg:x1; val_offset:438*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 438*FLEN/8, x2, x8, x12) + +inst_252: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2a0 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0d2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aa0; op2val:0x4d2; + valaddr_reg:x1; val_offset:440*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 440*FLEN/8, x2, x8, x12) + +inst_253: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2a0 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0d2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aa0; op2val:0x4d2; + valaddr_reg:x1; val_offset:442*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 442*FLEN/8, x2, x8, x12) + +inst_254: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2a0 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0d2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aa0; op2val:0x4d2; + valaddr_reg:x1; val_offset:444*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 444*FLEN/8, x2, x8, x12) + +inst_255: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x356 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x05a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b56; op2val:0x45a; + valaddr_reg:x1; val_offset:446*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 446*FLEN/8, x2, x8, x12) + +inst_256: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x356 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x05a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b56; op2val:0x45a; + valaddr_reg:x1; val_offset:448*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 448*FLEN/8, x2, x8, x12) + +inst_257: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x356 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x05a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b56; op2val:0x45a; + valaddr_reg:x1; val_offset:450*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 450*FLEN/8, x2, x8, x12) + +inst_258: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x356 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x05a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b56; op2val:0x45a; + valaddr_reg:x1; val_offset:452*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 452*FLEN/8, x2, x8, x12) + +inst_259: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x356 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x05a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b56; op2val:0x45a; + valaddr_reg:x1; val_offset:454*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 454*FLEN/8, x2, x8, x12) + +inst_260: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3cc and fs2 == 0 and fe2 == 0x01 and fm2 == 0x018 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bcc; op2val:0x418; + valaddr_reg:x1; val_offset:456*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 456*FLEN/8, x2, x8, x12) + +inst_261: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3cc and fs2 == 0 and fe2 == 0x01 and fm2 == 0x018 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bcc; op2val:0x418; + valaddr_reg:x1; val_offset:458*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 458*FLEN/8, x2, x8, x12) + +inst_262: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3cc and fs2 == 0 and fe2 == 0x01 and fm2 == 0x018 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bcc; op2val:0x418; + valaddr_reg:x1; val_offset:460*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 460*FLEN/8, x2, x8, x12) + +inst_263: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3cc and fs2 == 0 and fe2 == 0x01 and fm2 == 0x018 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bcc; op2val:0x418; + valaddr_reg:x1; val_offset:462*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 462*FLEN/8, x2, x8, x12) + +inst_264: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3cc and fs2 == 0 and fe2 == 0x01 and fm2 == 0x018 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bcc; op2val:0x418; + valaddr_reg:x1; val_offset:464*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 464*FLEN/8, x2, x8, x12) + +inst_265: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d4 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x014 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bd4; op2val:0x414; + valaddr_reg:x1; val_offset:466*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 466*FLEN/8, x2, x8, x12) + +inst_266: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d4 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x014 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bd4; op2val:0x414; + valaddr_reg:x1; val_offset:468*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 468*FLEN/8, x2, x8, x12) + +inst_267: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d4 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x014 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bd4; op2val:0x414; + valaddr_reg:x1; val_offset:470*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 470*FLEN/8, x2, x8, x12) + +inst_268: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d4 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x014 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bd4; op2val:0x414; + valaddr_reg:x1; val_offset:472*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 472*FLEN/8, x2, x8, x12) + +inst_269: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d4 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x014 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bd4; op2val:0x414; + valaddr_reg:x1; val_offset:474*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 474*FLEN/8, x2, x8, x12) + +inst_270: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1f9 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x158 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x31f9; op2val:0xd58; + valaddr_reg:x1; val_offset:476*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 476*FLEN/8, x2, x8, x12) + +inst_271: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1f9 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x158 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x31f9; op2val:0xd58; + valaddr_reg:x1; val_offset:478*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 478*FLEN/8, x2, x8, x12) + +inst_272: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1f9 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x158 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x31f9; op2val:0xd58; + valaddr_reg:x1; val_offset:480*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 480*FLEN/8, x2, x8, x12) + +inst_273: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1f9 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x158 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x31f9; op2val:0xd58; + valaddr_reg:x1; val_offset:482*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 482*FLEN/8, x2, x8, x12) + +inst_274: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1f9 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x158 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x31f9; op2val:0xd58; + valaddr_reg:x1; val_offset:484*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 484*FLEN/8, x2, x8, x12) + +inst_275: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x287 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0e4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a87; op2val:0x4e4; + valaddr_reg:x1; val_offset:486*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 486*FLEN/8, x2, x8, x12) + +inst_276: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x287 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0e4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a87; op2val:0x4e4; + valaddr_reg:x1; val_offset:488*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 488*FLEN/8, x2, x8, x12) + +inst_277: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x287 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0e4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a87; op2val:0x4e4; + valaddr_reg:x1; val_offset:490*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 490*FLEN/8, x2, x8, x12) + +inst_278: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x287 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0e4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a87; op2val:0x4e4; + valaddr_reg:x1; val_offset:492*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 492*FLEN/8, x2, x8, x12) + +inst_279: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x287 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0e4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a87; op2val:0x4e4; + valaddr_reg:x1; val_offset:494*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 494*FLEN/8, x2, x8, x12) +RVTEST_SIGBASE(x8,signature_x8_2) + +inst_280: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ea and fs2 == 0 and fe2 == 0x01 and fm2 == 0x27f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x38ea; op2val:0x67f; + valaddr_reg:x1; val_offset:496*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 496*FLEN/8, x2, x8, x12) + +inst_281: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ea and fs2 == 0 and fe2 == 0x01 and fm2 == 0x27f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x38ea; op2val:0x67f; + valaddr_reg:x1; val_offset:498*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 498*FLEN/8, x2, x8, x12) + +inst_282: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ea and fs2 == 0 and fe2 == 0x01 and fm2 == 0x27f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x38ea; op2val:0x67f; + valaddr_reg:x1; val_offset:500*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 500*FLEN/8, x2, x8, x12) + +inst_283: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ea and fs2 == 0 and fe2 == 0x01 and fm2 == 0x27f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x38ea; op2val:0x67f; + valaddr_reg:x1; val_offset:502*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 502*FLEN/8, x2, x8, x12) + +inst_284: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ea and fs2 == 0 and fe2 == 0x01 and fm2 == 0x27f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x38ea; op2val:0x67f; + valaddr_reg:x1; val_offset:504*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 504*FLEN/8, x2, x8, x12) + +inst_285: +// fs1 == 0 and fe1 == 0x08 and fm1 == 0x126 and fs2 == 0 and fe2 == 0x07 and fm2 == 0x233 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2126; op2val:0x1e33; + valaddr_reg:x1; val_offset:506*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 506*FLEN/8, x2, x8, x12) + +inst_286: +// fs1 == 0 and fe1 == 0x08 and fm1 == 0x126 and fs2 == 0 and fe2 == 0x07 and fm2 == 0x233 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2126; op2val:0x1e33; + valaddr_reg:x1; val_offset:508*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 508*FLEN/8, x2, x8, x12) + +inst_287: +// fs1 == 0 and fe1 == 0x08 and fm1 == 0x126 and fs2 == 0 and fe2 == 0x07 and fm2 == 0x233 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2126; op2val:0x1e33; + valaddr_reg:x1; val_offset:510*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 510*FLEN/8, x2, x8, x12) + +inst_288: +// fs1 == 0 and fe1 == 0x08 and fm1 == 0x126 and fs2 == 0 and fe2 == 0x07 and fm2 == 0x233 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2126; op2val:0x1e33; + valaddr_reg:x1; val_offset:512*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 512*FLEN/8, x2, x8, x12) + +inst_289: +// fs1 == 0 and fe1 == 0x08 and fm1 == 0x126 and fs2 == 0 and fe2 == 0x07 and fm2 == 0x233 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2126; op2val:0x1e33; + valaddr_reg:x1; val_offset:514*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 514*FLEN/8, x2, x8, x12) + +inst_290: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b5 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x024 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bb5; op2val:0x424; + valaddr_reg:x1; val_offset:516*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 516*FLEN/8, x2, x8, x12) + +inst_291: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b5 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x024 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bb5; op2val:0x424; + valaddr_reg:x1; val_offset:518*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 518*FLEN/8, x2, x8, x12) + +inst_292: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b5 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x024 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bb5; op2val:0x424; + valaddr_reg:x1; val_offset:520*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 520*FLEN/8, x2, x8, x12) + +inst_293: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b5 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x024 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bb5; op2val:0x424; + valaddr_reg:x1; val_offset:522*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 522*FLEN/8, x2, x8, x12) + +inst_294: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b5 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x024 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bb5; op2val:0x424; + valaddr_reg:x1; val_offset:524*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 524*FLEN/8, x2, x8, x12) + +inst_295: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x228 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x130 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3628; op2val:0x930; + valaddr_reg:x1; val_offset:526*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 526*FLEN/8, x2, x8, x12) + +inst_296: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x228 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x130 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3628; op2val:0x930; + valaddr_reg:x1; val_offset:528*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 528*FLEN/8, x2, x8, x12) + +inst_297: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x228 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x130 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3628; op2val:0x930; + valaddr_reg:x1; val_offset:530*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 530*FLEN/8, x2, x8, x12) + +inst_298: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x228 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x130 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3628; op2val:0x930; + valaddr_reg:x1; val_offset:532*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 532*FLEN/8, x2, x8, x12) + +inst_299: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x228 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x130 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3628; op2val:0x930; + valaddr_reg:x1; val_offset:534*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 534*FLEN/8, x2, x8, x12) + +inst_300: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x318 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x080 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b18; op2val:0x480; + valaddr_reg:x1; val_offset:536*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 536*FLEN/8, x2, x8, x12) + +inst_301: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x318 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x080 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b18; op2val:0x480; + valaddr_reg:x1; val_offset:538*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 538*FLEN/8, x2, x8, x12) + +inst_302: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x318 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x080 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b18; op2val:0x480; + valaddr_reg:x1; val_offset:540*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 540*FLEN/8, x2, x8, x12) + +inst_303: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x318 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x080 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b18; op2val:0x480; + valaddr_reg:x1; val_offset:542*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 542*FLEN/8, x2, x8, x12) + +inst_304: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x318 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x080 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b18; op2val:0x480; + valaddr_reg:x1; val_offset:544*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 544*FLEN/8, x2, x8, x12) + +inst_305: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x01e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bc0; op2val:0x41e; + valaddr_reg:x1; val_offset:546*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 546*FLEN/8, x2, x8, x12) + +inst_306: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x01e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bc0; op2val:0x41e; + valaddr_reg:x1; val_offset:548*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 548*FLEN/8, x2, x8, x12) + +inst_307: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x01e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bc0; op2val:0x41e; + valaddr_reg:x1; val_offset:550*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 550*FLEN/8, x2, x8, x12) + +inst_308: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x01e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bc0; op2val:0x41e; + valaddr_reg:x1; val_offset:552*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 552*FLEN/8, x2, x8, x12) + +inst_309: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x01e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bc0; op2val:0x41e; + valaddr_reg:x1; val_offset:554*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 554*FLEN/8, x2, x8, x12) + +inst_310: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x37d and fs2 == 0 and fe2 == 0x03 and fm2 == 0x043 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x337d; op2val:0xc43; + valaddr_reg:x1; val_offset:556*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 556*FLEN/8, x2, x8, x12) + +inst_311: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x37d and fs2 == 0 and fe2 == 0x03 and fm2 == 0x043 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x337d; op2val:0xc43; + valaddr_reg:x1; val_offset:558*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 558*FLEN/8, x2, x8, x12) + +inst_312: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x37d and fs2 == 0 and fe2 == 0x03 and fm2 == 0x043 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x337d; op2val:0xc43; + valaddr_reg:x1; val_offset:560*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 560*FLEN/8, x2, x8, x12) + +inst_313: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x37d and fs2 == 0 and fe2 == 0x03 and fm2 == 0x043 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x337d; op2val:0xc43; + valaddr_reg:x1; val_offset:562*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 562*FLEN/8, x2, x8, x12) + +inst_314: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x37d and fs2 == 0 and fe2 == 0x03 and fm2 == 0x043 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x337d; op2val:0xc43; + valaddr_reg:x1; val_offset:564*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 564*FLEN/8, x2, x8, x12) + +inst_315: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x246 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x117 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e46; op2val:0x1117; + valaddr_reg:x1; val_offset:566*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 566*FLEN/8, x2, x8, x12) + +inst_316: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x246 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x117 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e46; op2val:0x1117; + valaddr_reg:x1; val_offset:568*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 568*FLEN/8, x2, x8, x12) + +inst_317: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x246 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x117 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e46; op2val:0x1117; + valaddr_reg:x1; val_offset:570*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 570*FLEN/8, x2, x8, x12) + +inst_318: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x246 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x117 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e46; op2val:0x1117; + valaddr_reg:x1; val_offset:572*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 572*FLEN/8, x2, x8, x12) + +inst_319: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x246 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x117 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e46; op2val:0x1117; + valaddr_reg:x1; val_offset:574*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 574*FLEN/8, x2, x8, x12) + +inst_320: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x067 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x340 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3067; op2val:0xf40; + valaddr_reg:x1; val_offset:576*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 576*FLEN/8, x2, x8, x12) + +inst_321: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x067 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x340 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3067; op2val:0xf40; + valaddr_reg:x1; val_offset:578*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 578*FLEN/8, x2, x8, x12) + +inst_322: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x067 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x340 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3067; op2val:0xf40; + valaddr_reg:x1; val_offset:580*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 580*FLEN/8, x2, x8, x12) + +inst_323: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x067 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x340 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3067; op2val:0xf40; + valaddr_reg:x1; val_offset:582*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 582*FLEN/8, x2, x8, x12) + +inst_324: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x067 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x340 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3067; op2val:0xf40; + valaddr_reg:x1; val_offset:584*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 584*FLEN/8, x2, x8, x12) + +inst_325: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x392 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3837; op2val:0x792; + valaddr_reg:x1; val_offset:586*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 586*FLEN/8, x2, x8, x12) + +inst_326: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x392 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3837; op2val:0x792; + valaddr_reg:x1; val_offset:588*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 588*FLEN/8, x2, x8, x12) + +inst_327: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x392 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3837; op2val:0x792; + valaddr_reg:x1; val_offset:590*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 590*FLEN/8, x2, x8, x12) + +inst_328: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x392 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3837; op2val:0x792; + valaddr_reg:x1; val_offset:592*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 592*FLEN/8, x2, x8, x12) + +inst_329: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x392 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3837; op2val:0x792; + valaddr_reg:x1; val_offset:594*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 594*FLEN/8, x2, x8, x12) + +inst_330: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x16d and fs2 == 0 and fe2 == 0x02 and fm2 == 0x1e2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x356d; op2val:0x9e2; + valaddr_reg:x1; val_offset:596*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 596*FLEN/8, x2, x8, x12) + +inst_331: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x16d and fs2 == 0 and fe2 == 0x02 and fm2 == 0x1e2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x356d; op2val:0x9e2; + valaddr_reg:x1; val_offset:598*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 598*FLEN/8, x2, x8, x12) + +inst_332: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x16d and fs2 == 0 and fe2 == 0x02 and fm2 == 0x1e2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x356d; op2val:0x9e2; + valaddr_reg:x1; val_offset:600*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 600*FLEN/8, x2, x8, x12) + +inst_333: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x16d and fs2 == 0 and fe2 == 0x02 and fm2 == 0x1e2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x356d; op2val:0x9e2; + valaddr_reg:x1; val_offset:602*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 602*FLEN/8, x2, x8, x12) + +inst_334: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x16d and fs2 == 0 and fe2 == 0x02 and fm2 == 0x1e2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x356d; op2val:0x9e2; + valaddr_reg:x1; val_offset:604*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 604*FLEN/8, x2, x8, x12) + +inst_335: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x32f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x072 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b2f; op2val:0x472; + valaddr_reg:x1; val_offset:606*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 606*FLEN/8, x2, x8, x12) + +inst_336: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x32f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x072 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b2f; op2val:0x472; + valaddr_reg:x1; val_offset:608*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 608*FLEN/8, x2, x8, x12) + +inst_337: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x32f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x072 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b2f; op2val:0x472; + valaddr_reg:x1; val_offset:610*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 610*FLEN/8, x2, x8, x12) + +inst_338: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x32f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x072 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b2f; op2val:0x472; + valaddr_reg:x1; val_offset:612*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 612*FLEN/8, x2, x8, x12) + +inst_339: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x32f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x072 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b2f; op2val:0x472; + valaddr_reg:x1; val_offset:614*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 614*FLEN/8, x2, x8, x12) + +inst_340: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x002 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3f7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3002; op2val:0xff7; + valaddr_reg:x1; val_offset:616*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 616*FLEN/8, x2, x8, x12) + +inst_341: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x002 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3f7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3002; op2val:0xff7; + valaddr_reg:x1; val_offset:618*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 618*FLEN/8, x2, x8, x12) + +inst_342: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x002 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3f7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3002; op2val:0xff7; + valaddr_reg:x1; val_offset:620*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 620*FLEN/8, x2, x8, x12) + +inst_343: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x002 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3f7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3002; op2val:0xff7; + valaddr_reg:x1; val_offset:622*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 622*FLEN/8, x2, x8, x12) + +inst_344: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x002 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3f7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3002; op2val:0xff7; + valaddr_reg:x1; val_offset:624*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 624*FLEN/8, x2, x8, x12) + +inst_345: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2a4 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x0cf and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x36a4; op2val:0x8cf; + valaddr_reg:x1; val_offset:626*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 626*FLEN/8, x2, x8, x12) + +inst_346: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2a4 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x0cf and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x36a4; op2val:0x8cf; + valaddr_reg:x1; val_offset:628*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 628*FLEN/8, x2, x8, x12) + +inst_347: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2a4 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x0cf and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x36a4; op2val:0x8cf; + valaddr_reg:x1; val_offset:630*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 630*FLEN/8, x2, x8, x12) + +inst_348: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2a4 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x0cf and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x36a4; op2val:0x8cf; + valaddr_reg:x1; val_offset:632*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 632*FLEN/8, x2, x8, x12) + +inst_349: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2a4 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x0cf and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x36a4; op2val:0x8cf; + valaddr_reg:x1; val_offset:634*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 634*FLEN/8, x2, x8, x12) + +inst_350: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3c3 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x01d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x37c3; op2val:0x81d; + valaddr_reg:x1; val_offset:636*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 636*FLEN/8, x2, x8, x12) + +inst_351: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3c3 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x01d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x37c3; op2val:0x81d; + valaddr_reg:x1; val_offset:638*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 638*FLEN/8, x2, x8, x12) + +inst_352: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3c3 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x01d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x37c3; op2val:0x81d; + valaddr_reg:x1; val_offset:640*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 640*FLEN/8, x2, x8, x12) + +inst_353: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3c3 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x01d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x37c3; op2val:0x81d; + valaddr_reg:x1; val_offset:642*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 642*FLEN/8, x2, x8, x12) + +inst_354: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3c3 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x01d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x37c3; op2val:0x81d; + valaddr_reg:x1; val_offset:644*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 644*FLEN/8, x2, x8, x12) + +inst_355: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x129 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x22f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2929; op2val:0x162f; + valaddr_reg:x1; val_offset:646*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 646*FLEN/8, x2, x8, x12) + +inst_356: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x129 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x22f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2929; op2val:0x162f; + valaddr_reg:x1; val_offset:648*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 648*FLEN/8, x2, x8, x12) + +inst_357: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x129 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x22f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2929; op2val:0x162f; + valaddr_reg:x1; val_offset:650*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 650*FLEN/8, x2, x8, x12) + +inst_358: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x129 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x22f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2929; op2val:0x162f; + valaddr_reg:x1; val_offset:652*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 652*FLEN/8, x2, x8, x12) + +inst_359: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x129 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x22f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2929; op2val:0x162f; + valaddr_reg:x1; val_offset:654*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 654*FLEN/8, x2, x8, x12) + +inst_360: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x24d and fs2 == 0 and fe2 == 0x02 and fm2 == 0x111 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x364d; op2val:0x911; + valaddr_reg:x1; val_offset:656*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 656*FLEN/8, x2, x8, x12) + +inst_361: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x24d and fs2 == 0 and fe2 == 0x02 and fm2 == 0x111 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x364d; op2val:0x911; + valaddr_reg:x1; val_offset:658*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 658*FLEN/8, x2, x8, x12) + +inst_362: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x24d and fs2 == 0 and fe2 == 0x02 and fm2 == 0x111 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x364d; op2val:0x911; + valaddr_reg:x1; val_offset:660*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 660*FLEN/8, x2, x8, x12) + +inst_363: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x24d and fs2 == 0 and fe2 == 0x02 and fm2 == 0x111 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x364d; op2val:0x911; + valaddr_reg:x1; val_offset:662*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 662*FLEN/8, x2, x8, x12) + +inst_364: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x24d and fs2 == 0 and fe2 == 0x02 and fm2 == 0x111 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x364d; op2val:0x911; + valaddr_reg:x1; val_offset:664*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 664*FLEN/8, x2, x8, x12) + +inst_365: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3db and fs2 == 0 and fe2 == 0x01 and fm2 == 0x010 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bdb; op2val:0x410; + valaddr_reg:x1; val_offset:666*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 666*FLEN/8, x2, x8, x12) + +inst_366: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3db and fs2 == 0 and fe2 == 0x01 and fm2 == 0x010 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bdb; op2val:0x410; + valaddr_reg:x1; val_offset:668*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 668*FLEN/8, x2, x8, x12) + +inst_367: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3db and fs2 == 0 and fe2 == 0x01 and fm2 == 0x010 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bdb; op2val:0x410; + valaddr_reg:x1; val_offset:670*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 670*FLEN/8, x2, x8, x12) + +inst_368: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3db and fs2 == 0 and fe2 == 0x01 and fm2 == 0x010 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bdb; op2val:0x410; + valaddr_reg:x1; val_offset:672*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 672*FLEN/8, x2, x8, x12) + +inst_369: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3db and fs2 == 0 and fe2 == 0x01 and fm2 == 0x010 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bdb; op2val:0x410; + valaddr_reg:x1; val_offset:674*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 674*FLEN/8, x2, x8, x12) + +inst_370: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2e0 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0a5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ae0; op2val:0x4a5; + valaddr_reg:x1; val_offset:676*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 676*FLEN/8, x2, x8, x12) + +inst_371: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2e0 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0a5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ae0; op2val:0x4a5; + valaddr_reg:x1; val_offset:678*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 678*FLEN/8, x2, x8, x12) + +inst_372: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2e0 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0a5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ae0; op2val:0x4a5; + valaddr_reg:x1; val_offset:680*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 680*FLEN/8, x2, x8, x12) + +inst_373: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2e0 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0a5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ae0; op2val:0x4a5; + valaddr_reg:x1; val_offset:682*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 682*FLEN/8, x2, x8, x12) + +inst_374: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2e0 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0a5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ae0; op2val:0x4a5; + valaddr_reg:x1; val_offset:684*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 684*FLEN/8, x2, x8, x12) + +inst_375: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3bb and fs2 == 0 and fe2 == 0x01 and fm2 == 0x021 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bbb; op2val:0x421; + valaddr_reg:x1; val_offset:686*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 686*FLEN/8, x2, x8, x12) + +inst_376: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3bb and fs2 == 0 and fe2 == 0x01 and fm2 == 0x021 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bbb; op2val:0x421; + valaddr_reg:x1; val_offset:688*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 688*FLEN/8, x2, x8, x12) + +inst_377: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3bb and fs2 == 0 and fe2 == 0x01 and fm2 == 0x021 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bbb; op2val:0x421; + valaddr_reg:x1; val_offset:690*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 690*FLEN/8, x2, x8, x12) + +inst_378: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3bb and fs2 == 0 and fe2 == 0x01 and fm2 == 0x021 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bbb; op2val:0x421; + valaddr_reg:x1; val_offset:692*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 692*FLEN/8, x2, x8, x12) + +inst_379: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3bb and fs2 == 0 and fe2 == 0x01 and fm2 == 0x021 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bbb; op2val:0x421; + valaddr_reg:x1; val_offset:694*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 694*FLEN/8, x2, x8, x12) + +inst_380: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x33b and fs2 == 0 and fe2 == 0x01 and fm2 == 0x06a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b3b; op2val:0x46a; + valaddr_reg:x1; val_offset:696*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 696*FLEN/8, x2, x8, x12) + +inst_381: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x33b and fs2 == 0 and fe2 == 0x01 and fm2 == 0x06a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b3b; op2val:0x46a; + valaddr_reg:x1; val_offset:698*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 698*FLEN/8, x2, x8, x12) + +inst_382: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x33b and fs2 == 0 and fe2 == 0x01 and fm2 == 0x06a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b3b; op2val:0x46a; + valaddr_reg:x1; val_offset:700*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 700*FLEN/8, x2, x8, x12) + +inst_383: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x33b and fs2 == 0 and fe2 == 0x01 and fm2 == 0x06a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b3b; op2val:0x46a; + valaddr_reg:x1; val_offset:702*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 702*FLEN/8, x2, x8, x12) + +inst_384: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x33b and fs2 == 0 and fe2 == 0x01 and fm2 == 0x06a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b3b; op2val:0x46a; + valaddr_reg:x1; val_offset:704*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 704*FLEN/8, x2, x8, x12) + +inst_385: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3de and fs2 == 0 and fe2 == 0x02 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x37de; op2val:0x80f; + valaddr_reg:x1; val_offset:706*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 706*FLEN/8, x2, x8, x12) + +inst_386: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3de and fs2 == 0 and fe2 == 0x02 and fm2 == 0x00f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x37de; op2val:0x80f; + valaddr_reg:x1; val_offset:708*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 708*FLEN/8, x2, x8, x12) + +inst_387: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3de and fs2 == 0 and fe2 == 0x02 and fm2 == 0x00f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x37de; op2val:0x80f; + valaddr_reg:x1; val_offset:710*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 710*FLEN/8, x2, x8, x12) + +inst_388: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3de and fs2 == 0 and fe2 == 0x02 and fm2 == 0x00f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x37de; op2val:0x80f; + valaddr_reg:x1; val_offset:712*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 712*FLEN/8, x2, x8, x12) + +inst_389: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3de and fs2 == 0 and fe2 == 0x02 and fm2 == 0x00f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x37de; op2val:0x80f; + valaddr_reg:x1; val_offset:714*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 714*FLEN/8, x2, x8, x12) + +inst_390: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x038 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x391 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2c38; op2val:0x1391; + valaddr_reg:x1; val_offset:716*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 716*FLEN/8, x2, x8, x12) + +inst_391: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x038 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x391 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2c38; op2val:0x1391; + valaddr_reg:x1; val_offset:718*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 718*FLEN/8, x2, x8, x12) + +inst_392: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x038 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x391 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2c38; op2val:0x1391; + valaddr_reg:x1; val_offset:720*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 720*FLEN/8, x2, x8, x12) + +inst_393: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x038 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x391 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2c38; op2val:0x1391; + valaddr_reg:x1; val_offset:722*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 722*FLEN/8, x2, x8, x12) + +inst_394: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x038 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x391 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2c38; op2val:0x1391; + valaddr_reg:x1; val_offset:724*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 724*FLEN/8, x2, x8, x12) + +inst_395: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x223 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x133 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a23; op2val:0x533; + valaddr_reg:x1; val_offset:726*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 726*FLEN/8, x2, x8, x12) + +inst_396: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x223 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x133 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a23; op2val:0x533; + valaddr_reg:x1; val_offset:728*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 728*FLEN/8, x2, x8, x12) + +inst_397: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x223 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x133 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a23; op2val:0x533; + valaddr_reg:x1; val_offset:730*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 730*FLEN/8, x2, x8, x12) + +inst_398: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x223 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x133 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a23; op2val:0x533; + valaddr_reg:x1; val_offset:732*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 732*FLEN/8, x2, x8, x12) + +inst_399: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x223 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x133 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a23; op2val:0x533; + valaddr_reg:x1; val_offset:734*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 734*FLEN/8, x2, x8, x12) + +inst_400: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x154 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x39fe; op2val:0x554; + valaddr_reg:x1; val_offset:736*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 736*FLEN/8, x2, x8, x12) + +inst_401: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x154 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x39fe; op2val:0x554; + valaddr_reg:x1; val_offset:738*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 738*FLEN/8, x2, x8, x12) + +inst_402: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x154 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x39fe; op2val:0x554; + valaddr_reg:x1; val_offset:740*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 740*FLEN/8, x2, x8, x12) + +inst_403: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x154 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x39fe; op2val:0x554; + valaddr_reg:x1; val_offset:742*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 742*FLEN/8, x2, x8, x12) + +inst_404: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x154 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x39fe; op2val:0x554; + valaddr_reg:x1; val_offset:744*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 744*FLEN/8, x2, x8, x12) + +inst_405: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x203 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x14f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3603; op2val:0x94f; + valaddr_reg:x1; val_offset:746*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 746*FLEN/8, x2, x8, x12) + +inst_406: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x203 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x14f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3603; op2val:0x94f; + valaddr_reg:x1; val_offset:748*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 748*FLEN/8, x2, x8, x12) + +inst_407: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x203 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x14f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3603; op2val:0x94f; + valaddr_reg:x1; val_offset:750*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 750*FLEN/8, x2, x8, x12) +RVTEST_SIGBASE(x8,signature_x8_3) + +inst_408: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x203 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x14f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3603; op2val:0x94f; + valaddr_reg:x1; val_offset:752*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 752*FLEN/8, x2, x8, x12) + +inst_409: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x203 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x14f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3603; op2val:0x94f; + valaddr_reg:x1; val_offset:754*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 754*FLEN/8, x2, x8, x12) + +inst_410: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0a6 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x2de and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x34a6; op2val:0xade; + valaddr_reg:x1; val_offset:756*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 756*FLEN/8, x2, x8, x12) + +inst_411: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0a6 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x2de and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x34a6; op2val:0xade; + valaddr_reg:x1; val_offset:758*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 758*FLEN/8, x2, x8, x12) + +inst_412: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0a6 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x2de and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x34a6; op2val:0xade; + valaddr_reg:x1; val_offset:760*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 760*FLEN/8, x2, x8, x12) + +inst_413: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0a6 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x2de and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x34a6; op2val:0xade; + valaddr_reg:x1; val_offset:762*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 762*FLEN/8, x2, x8, x12) + +inst_414: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0a6 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x2de and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x34a6; op2val:0xade; + valaddr_reg:x1; val_offset:764*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 764*FLEN/8, x2, x8, x12) + +inst_415: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x09d and fs2 == 0 and fe2 == 0x01 and fm2 == 0x09e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x389d; op2val:0x49e; + valaddr_reg:x1; val_offset:766*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 766*FLEN/8, x2, x8, x12) + +inst_416: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x09d and fs2 == 0 and fe2 == 0x01 and fm2 == 0x09e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x389d; op2val:0x49e; + valaddr_reg:x1; val_offset:768*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 768*FLEN/8, x2, x8, x12) + +inst_417: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x09d and fs2 == 0 and fe2 == 0x01 and fm2 == 0x09e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x389d; op2val:0x49e; + valaddr_reg:x1; val_offset:770*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 770*FLEN/8, x2, x8, x12) + +inst_418: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x09d and fs2 == 0 and fe2 == 0x01 and fm2 == 0x09e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x389d; op2val:0x49e; + valaddr_reg:x1; val_offset:772*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 772*FLEN/8, x2, x8, x12) + +inst_419: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x09d and fs2 == 0 and fe2 == 0x01 and fm2 == 0x09e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x389d; op2val:0x49e; + valaddr_reg:x1; val_offset:774*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 774*FLEN/8, x2, x8, x12) + +inst_420: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2ad and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bf6; op2val:0x2ad; + valaddr_reg:x1; val_offset:776*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 776*FLEN/8, x2, x8, x12) + +inst_421: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2ad and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bf6; op2val:0x2ad; + valaddr_reg:x1; val_offset:778*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 778*FLEN/8, x2, x8, x12) + +inst_422: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2ad and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bf6; op2val:0x2ad; + valaddr_reg:x1; val_offset:780*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 780*FLEN/8, x2, x8, x12) + +inst_423: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2ad and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bf6; op2val:0x2ad; + valaddr_reg:x1; val_offset:782*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 782*FLEN/8, x2, x8, x12) + +inst_424: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2ad and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bf6; op2val:0x2ad; + valaddr_reg:x1; val_offset:784*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 784*FLEN/8, x2, x8, x12) + +inst_425: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ba and fs2 == 0 and fe2 == 0x01 and fm2 == 0x081 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x38ba; op2val:0x481; + valaddr_reg:x1; val_offset:786*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 786*FLEN/8, x2, x8, x12) + +inst_426: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ba and fs2 == 0 and fe2 == 0x01 and fm2 == 0x081 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x38ba; op2val:0x481; + valaddr_reg:x1; val_offset:788*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 788*FLEN/8, x2, x8, x12) + +inst_427: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ba and fs2 == 0 and fe2 == 0x01 and fm2 == 0x081 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x38ba; op2val:0x481; + valaddr_reg:x1; val_offset:790*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 790*FLEN/8, x2, x8, x12) + +inst_428: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ba and fs2 == 0 and fe2 == 0x01 and fm2 == 0x081 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x38ba; op2val:0x481; + valaddr_reg:x1; val_offset:792*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 792*FLEN/8, x2, x8, x12) + +inst_429: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ba and fs2 == 0 and fe2 == 0x01 and fm2 == 0x081 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x38ba; op2val:0x481; + valaddr_reg:x1; val_offset:794*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 794*FLEN/8, x2, x8, x12) + +inst_430: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x06b and fs2 == 0 and fe2 == 0x02 and fm2 == 0x0d2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x346b; op2val:0x8d2; + valaddr_reg:x1; val_offset:796*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 796*FLEN/8, x2, x8, x12) + +inst_431: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x06b and fs2 == 0 and fe2 == 0x02 and fm2 == 0x0d2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x346b; op2val:0x8d2; + valaddr_reg:x1; val_offset:798*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 798*FLEN/8, x2, x8, x12) + +inst_432: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x06b and fs2 == 0 and fe2 == 0x02 and fm2 == 0x0d2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x346b; op2val:0x8d2; + valaddr_reg:x1; val_offset:800*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 800*FLEN/8, x2, x8, x12) + +inst_433: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x06b and fs2 == 0 and fe2 == 0x02 and fm2 == 0x0d2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x346b; op2val:0x8d2; + valaddr_reg:x1; val_offset:802*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 802*FLEN/8, x2, x8, x12) + +inst_434: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x06b and fs2 == 0 and fe2 == 0x02 and fm2 == 0x0d2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x346b; op2val:0x8d2; + valaddr_reg:x1; val_offset:804*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 804*FLEN/8, x2, x8, x12) + +inst_435: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x333 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2f5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b33; op2val:0x2f5; + valaddr_reg:x1; val_offset:806*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 806*FLEN/8, x2, x8, x12) + +inst_436: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x333 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2f5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b33; op2val:0x2f5; + valaddr_reg:x1; val_offset:808*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 808*FLEN/8, x2, x8, x12) + +inst_437: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x333 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2f5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b33; op2val:0x2f5; + valaddr_reg:x1; val_offset:810*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 810*FLEN/8, x2, x8, x12) + +inst_438: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x333 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2f5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b33; op2val:0x2f5; + valaddr_reg:x1; val_offset:812*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 812*FLEN/8, x2, x8, x12) + +inst_439: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x333 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2f5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b33; op2val:0x2f5; + valaddr_reg:x1; val_offset:814*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 814*FLEN/8, x2, x8, x12) + +inst_440: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x225 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x377 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a25; op2val:0x377; + valaddr_reg:x1; val_offset:816*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 816*FLEN/8, x2, x8, x12) + +inst_441: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x225 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x377 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a25; op2val:0x377; + valaddr_reg:x1; val_offset:818*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 818*FLEN/8, x2, x8, x12) + +inst_442: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x225 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x377 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a25; op2val:0x377; + valaddr_reg:x1; val_offset:820*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 820*FLEN/8, x2, x8, x12) + +inst_443: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x225 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x377 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a25; op2val:0x377; + valaddr_reg:x1; val_offset:822*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 822*FLEN/8, x2, x8, x12) + +inst_444: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x225 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x377 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a25; op2val:0x377; + valaddr_reg:x1; val_offset:824*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 824*FLEN/8, x2, x8, x12) + +inst_445: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ab and fs2 == 0 and fe2 == 0x01 and fm2 == 0x18f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x37ab; op2val:0x58f; + valaddr_reg:x1; val_offset:826*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 826*FLEN/8, x2, x8, x12) + +inst_446: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ab and fs2 == 0 and fe2 == 0x01 and fm2 == 0x18f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x37ab; op2val:0x58f; + valaddr_reg:x1; val_offset:828*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 828*FLEN/8, x2, x8, x12) + +inst_447: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ab and fs2 == 0 and fe2 == 0x01 and fm2 == 0x18f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x37ab; op2val:0x58f; + valaddr_reg:x1; val_offset:830*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 830*FLEN/8, x2, x8, x12) + +inst_448: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ab and fs2 == 0 and fe2 == 0x01 and fm2 == 0x18f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x37ab; op2val:0x58f; + valaddr_reg:x1; val_offset:832*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 832*FLEN/8, x2, x8, x12) + +inst_449: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ab and fs2 == 0 and fe2 == 0x01 and fm2 == 0x18f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x37ab; op2val:0x58f; + valaddr_reg:x1; val_offset:834*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 834*FLEN/8, x2, x8, x12) + +inst_450: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x185 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3dc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3985; op2val:0x3dc; + valaddr_reg:x1; val_offset:836*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 836*FLEN/8, x2, x8, x12) + +inst_451: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x185 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3dc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3985; op2val:0x3dc; + valaddr_reg:x1; val_offset:838*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 838*FLEN/8, x2, x8, x12) + +inst_452: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x185 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3dc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3985; op2val:0x3dc; + valaddr_reg:x1; val_offset:840*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 840*FLEN/8, x2, x8, x12) + +inst_453: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x185 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3dc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3985; op2val:0x3dc; + valaddr_reg:x1; val_offset:842*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 842*FLEN/8, x2, x8, x12) + +inst_454: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x185 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3dc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3985; op2val:0x3dc; + valaddr_reg:x1; val_offset:844*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 844*FLEN/8, x2, x8, x12) + +inst_455: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x24c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x362 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a4c; op2val:0x362; + valaddr_reg:x1; val_offset:846*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 846*FLEN/8, x2, x8, x12) + +inst_456: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x24c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x362 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a4c; op2val:0x362; + valaddr_reg:x1; val_offset:848*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 848*FLEN/8, x2, x8, x12) + +inst_457: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x24c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x362 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a4c; op2val:0x362; + valaddr_reg:x1; val_offset:850*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 850*FLEN/8, x2, x8, x12) + +inst_458: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x24c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x362 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a4c; op2val:0x362; + valaddr_reg:x1; val_offset:852*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 852*FLEN/8, x2, x8, x12) + +inst_459: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x24c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x362 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a4c; op2val:0x362; + valaddr_reg:x1; val_offset:854*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 854*FLEN/8, x2, x8, x12) + +inst_460: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x0b9 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x082 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x28b9; op2val:0x1482; + valaddr_reg:x1; val_offset:856*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 856*FLEN/8, x2, x8, x12) + +inst_461: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x0b9 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x082 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x28b9; op2val:0x1482; + valaddr_reg:x1; val_offset:858*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 858*FLEN/8, x2, x8, x12) + +inst_462: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x0b9 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x082 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x28b9; op2val:0x1482; + valaddr_reg:x1; val_offset:860*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 860*FLEN/8, x2, x8, x12) + +inst_463: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x0b9 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x082 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x28b9; op2val:0x1482; + valaddr_reg:x1; val_offset:862*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 862*FLEN/8, x2, x8, x12) + +inst_464: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x0b9 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x082 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x28b9; op2val:0x1482; + valaddr_reg:x1; val_offset:864*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 864*FLEN/8, x2, x8, x12) + +inst_465: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x087 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0b4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3887; op2val:0x4b4; + valaddr_reg:x1; val_offset:866*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 866*FLEN/8, x2, x8, x12) + +inst_466: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x087 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0b4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3887; op2val:0x4b4; + valaddr_reg:x1; val_offset:868*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 868*FLEN/8, x2, x8, x12) + +inst_467: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x087 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0b4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3887; op2val:0x4b4; + valaddr_reg:x1; val_offset:870*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 870*FLEN/8, x2, x8, x12) + +inst_468: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x087 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0b4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3887; op2val:0x4b4; + valaddr_reg:x1; val_offset:872*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 872*FLEN/8, x2, x8, x12) + +inst_469: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x087 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0b4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3887; op2val:0x4b4; + valaddr_reg:x1; val_offset:874*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 874*FLEN/8, x2, x8, x12) + +inst_470: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2b4 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x25c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x36b4; op2val:0x65c; + valaddr_reg:x1; val_offset:876*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 876*FLEN/8, x2, x8, x12) + +inst_471: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2b4 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x25c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x36b4; op2val:0x65c; + valaddr_reg:x1; val_offset:878*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 878*FLEN/8, x2, x8, x12) + +inst_472: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2b4 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x25c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x36b4; op2val:0x65c; + valaddr_reg:x1; val_offset:880*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 880*FLEN/8, x2, x8, x12) + +inst_473: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2b4 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x25c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x36b4; op2val:0x65c; + valaddr_reg:x1; val_offset:882*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 882*FLEN/8, x2, x8, x12) + +inst_474: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2b4 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x25c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x36b4; op2val:0x65c; + valaddr_reg:x1; val_offset:884*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 884*FLEN/8, x2, x8, x12) + +inst_475: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0a7 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x094 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x38a7; op2val:0x494; + valaddr_reg:x1; val_offset:886*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 886*FLEN/8, x2, x8, x12) + +inst_476: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0a7 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x094 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x38a7; op2val:0x494; + valaddr_reg:x1; val_offset:888*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 888*FLEN/8, x2, x8, x12) + +inst_477: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0a7 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x094 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x38a7; op2val:0x494; + valaddr_reg:x1; val_offset:890*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 890*FLEN/8, x2, x8, x12) + +inst_478: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0a7 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x094 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x38a7; op2val:0x494; + valaddr_reg:x1; val_offset:892*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 892*FLEN/8, x2, x8, x12) + +inst_479: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0a7 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x094 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x38a7; op2val:0x494; + valaddr_reg:x1; val_offset:894*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 894*FLEN/8, x2, x8, x12) + +inst_480: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x28c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x341 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a8c; op2val:0x341; + valaddr_reg:x1; val_offset:896*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 896*FLEN/8, x2, x8, x12) + +inst_481: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x28c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x341 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a8c; op2val:0x341; + valaddr_reg:x1; val_offset:898*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 898*FLEN/8, x2, x8, x12) + +inst_482: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x28c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x341 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a8c; op2val:0x341; + valaddr_reg:x1; val_offset:900*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 900*FLEN/8, x2, x8, x12) + +inst_483: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x28c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x341 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a8c; op2val:0x341; + valaddr_reg:x1; val_offset:902*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 902*FLEN/8, x2, x8, x12) + +inst_484: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x28c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x341 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a8c; op2val:0x341; + valaddr_reg:x1; val_offset:904*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 904*FLEN/8, x2, x8, x12) + +inst_485: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x250 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x2bf and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3250; op2val:0xabf; + valaddr_reg:x1; val_offset:906*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 906*FLEN/8, x2, x8, x12) + +inst_486: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x250 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x2bf and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3250; op2val:0xabf; + valaddr_reg:x1; val_offset:908*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 908*FLEN/8, x2, x8, x12) + +inst_487: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x250 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x2bf and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3250; op2val:0xabf; + valaddr_reg:x1; val_offset:910*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 910*FLEN/8, x2, x8, x12) + +inst_488: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x250 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x2bf and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3250; op2val:0xabf; + valaddr_reg:x1; val_offset:912*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 912*FLEN/8, x2, x8, x12) + +inst_489: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x250 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x2bf and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3250; op2val:0xabf; + valaddr_reg:x1; val_offset:914*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 914*FLEN/8, x2, x8, x12) + +inst_490: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3b1 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x18a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x37b1; op2val:0x58a; + valaddr_reg:x1; val_offset:916*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 916*FLEN/8, x2, x8, x12) + +inst_491: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3b1 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x18a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x37b1; op2val:0x58a; + valaddr_reg:x1; val_offset:918*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 918*FLEN/8, x2, x8, x12) + +inst_492: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3b1 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x18a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x37b1; op2val:0x58a; + valaddr_reg:x1; val_offset:920*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 920*FLEN/8, x2, x8, x12) + +inst_493: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3b1 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x18a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x37b1; op2val:0x58a; + valaddr_reg:x1; val_offset:922*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 922*FLEN/8, x2, x8, x12) + +inst_494: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3b1 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x18a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x37b1; op2val:0x58a; + valaddr_reg:x1; val_offset:924*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 924*FLEN/8, x2, x8, x12) + +inst_495: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x23b and fs2 == 0 and fe2 == 0x01 and fm2 == 0x2d6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x363b; op2val:0x6d6; + valaddr_reg:x1; val_offset:926*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 926*FLEN/8, x2, x8, x12) + +inst_496: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x23b and fs2 == 0 and fe2 == 0x01 and fm2 == 0x2d6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x363b; op2val:0x6d6; + valaddr_reg:x1; val_offset:928*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 928*FLEN/8, x2, x8, x12) + +inst_497: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x23b and fs2 == 0 and fe2 == 0x01 and fm2 == 0x2d6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x363b; op2val:0x6d6; + valaddr_reg:x1; val_offset:930*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 930*FLEN/8, x2, x8, x12) + +inst_498: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x23b and fs2 == 0 and fe2 == 0x01 and fm2 == 0x2d6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x363b; op2val:0x6d6; + valaddr_reg:x1; val_offset:932*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 932*FLEN/8, x2, x8, x12) + +inst_499: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x23b and fs2 == 0 and fe2 == 0x01 and fm2 == 0x2d6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x363b; op2val:0x6d6; + valaddr_reg:x1; val_offset:934*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 934*FLEN/8, x2, x8, x12) + +inst_500: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x03a and fs2 == 0 and fe2 == 0x06 and fm2 == 0x10a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x243a; op2val:0x190a; + valaddr_reg:x1; val_offset:936*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 936*FLEN/8, x2, x8, x12) + +inst_501: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x03a and fs2 == 0 and fe2 == 0x06 and fm2 == 0x10a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x243a; op2val:0x190a; + valaddr_reg:x1; val_offset:938*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 938*FLEN/8, x2, x8, x12) + +inst_502: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x03a and fs2 == 0 and fe2 == 0x06 and fm2 == 0x10a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x243a; op2val:0x190a; + valaddr_reg:x1; val_offset:940*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 940*FLEN/8, x2, x8, x12) + +inst_503: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x03a and fs2 == 0 and fe2 == 0x06 and fm2 == 0x10a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x243a; op2val:0x190a; + valaddr_reg:x1; val_offset:942*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 942*FLEN/8, x2, x8, x12) + +inst_504: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x03a and fs2 == 0 and fe2 == 0x06 and fm2 == 0x10a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x243a; op2val:0x190a; + valaddr_reg:x1; val_offset:944*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 944*FLEN/8, x2, x8, x12) + +inst_505: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2b7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bd8; op2val:0x2b7; + valaddr_reg:x1; val_offset:946*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 946*FLEN/8, x2, x8, x12) + +inst_506: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2b7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bd8; op2val:0x2b7; + valaddr_reg:x1; val_offset:948*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 948*FLEN/8, x2, x8, x12) + +inst_507: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2b7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bd8; op2val:0x2b7; + valaddr_reg:x1; val_offset:950*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 950*FLEN/8, x2, x8, x12) + +inst_508: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2b7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bd8; op2val:0x2b7; + valaddr_reg:x1; val_offset:952*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 952*FLEN/8, x2, x8, x12) + +inst_509: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2b7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bd8; op2val:0x2b7; + valaddr_reg:x1; val_offset:954*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 954*FLEN/8, x2, x8, x12) + +inst_510: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x330 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2f6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b30; op2val:0x2f6; + valaddr_reg:x1; val_offset:956*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 956*FLEN/8, x2, x8, x12) + +inst_511: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x330 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2f6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b30; op2val:0x2f6; + valaddr_reg:x1; val_offset:958*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 958*FLEN/8, x2, x8, x12) + +inst_512: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x330 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2f6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b30; op2val:0x2f6; + valaddr_reg:x1; val_offset:960*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 960*FLEN/8, x2, x8, x12) + +inst_513: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x330 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2f6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b30; op2val:0x2f6; + valaddr_reg:x1; val_offset:962*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 962*FLEN/8, x2, x8, x12) + +inst_514: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x330 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2f6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b30; op2val:0x2f6; + valaddr_reg:x1; val_offset:964*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 964*FLEN/8, x2, x8, x12) + +inst_515: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x119 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x02d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3119; op2val:0xc2d; + valaddr_reg:x1; val_offset:966*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 966*FLEN/8, x2, x8, x12) + +inst_516: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x119 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x02d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3119; op2val:0xc2d; + valaddr_reg:x1; val_offset:968*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 968*FLEN/8, x2, x8, x12) + +inst_517: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x119 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x02d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3119; op2val:0xc2d; + valaddr_reg:x1; val_offset:970*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 970*FLEN/8, x2, x8, x12) + +inst_518: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x119 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x02d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3119; op2val:0xc2d; + valaddr_reg:x1; val_offset:972*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 972*FLEN/8, x2, x8, x12) + +inst_519: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x119 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x02d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3119; op2val:0xc2d; + valaddr_reg:x1; val_offset:974*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 974*FLEN/8, x2, x8, x12) + +inst_520: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3df and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2b4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bdf; op2val:0x2b4; + valaddr_reg:x1; val_offset:976*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 976*FLEN/8, x2, x8, x12) + +inst_521: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3df and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2b4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bdf; op2val:0x2b4; + valaddr_reg:x1; val_offset:978*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 978*FLEN/8, x2, x8, x12) + +inst_522: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3df and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2b4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bdf; op2val:0x2b4; + valaddr_reg:x1; val_offset:980*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 980*FLEN/8, x2, x8, x12) + +inst_523: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3df and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2b4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bdf; op2val:0x2b4; + valaddr_reg:x1; val_offset:982*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 982*FLEN/8, x2, x8, x12) + +inst_524: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3df and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2b4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bdf; op2val:0x2b4; + valaddr_reg:x1; val_offset:984*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 984*FLEN/8, x2, x8, x12) + +inst_525: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0b6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x085 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x38b6; op2val:0x485; + valaddr_reg:x1; val_offset:986*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 986*FLEN/8, x2, x8, x12) + +inst_526: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0b6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x085 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x38b6; op2val:0x485; + valaddr_reg:x1; val_offset:988*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 988*FLEN/8, x2, x8, x12) + +inst_527: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0b6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x085 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x38b6; op2val:0x485; + valaddr_reg:x1; val_offset:990*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 990*FLEN/8, x2, x8, x12) + +inst_528: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0b6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x085 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x38b6; op2val:0x485; + valaddr_reg:x1; val_offset:992*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 992*FLEN/8, x2, x8, x12) + +inst_529: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0b6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x085 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x38b6; op2val:0x485; + valaddr_reg:x1; val_offset:994*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 994*FLEN/8, x2, x8, x12) + +inst_530: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x35d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a55; op2val:0x35d; + valaddr_reg:x1; val_offset:996*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 996*FLEN/8, x2, x8, x12) + +inst_531: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x35d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a55; op2val:0x35d; + valaddr_reg:x1; val_offset:998*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 998*FLEN/8, x2, x8, x12) + +inst_532: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x35d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a55; op2val:0x35d; + valaddr_reg:x1; val_offset:1000*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1000*FLEN/8, x2, x8, x12) + +inst_533: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x35d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a55; op2val:0x35d; + valaddr_reg:x1; val_offset:1002*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1002*FLEN/8, x2, x8, x12) + +inst_534: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x35d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a55; op2val:0x35d; + valaddr_reg:x1; val_offset:1004*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1004*FLEN/8, x2, x8, x12) + +inst_535: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x368 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b68; op2val:0x2e0; + valaddr_reg:x1; val_offset:1006*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1006*FLEN/8, x2, x8, x12) +RVTEST_SIGBASE(x8,signature_x8_4) + +inst_536: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x368 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b68; op2val:0x2e0; + valaddr_reg:x1; val_offset:1008*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1008*FLEN/8, x2, x8, x12) + +inst_537: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x368 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b68; op2val:0x2e0; + valaddr_reg:x1; val_offset:1010*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1010*FLEN/8, x2, x8, x12) + +inst_538: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x368 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b68; op2val:0x2e0; + valaddr_reg:x1; val_offset:1012*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1012*FLEN/8, x2, x8, x12) + +inst_539: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x368 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b68; op2val:0x2e0; + valaddr_reg:x1; val_offset:1014*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1014*FLEN/8, x2, x8, x12) + +inst_540: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x104 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3904; op2val:0x43f; + valaddr_reg:x1; val_offset:1016*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1016*FLEN/8, x2, x8, x12) + +inst_541: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x104 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x03f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3904; op2val:0x43f; + valaddr_reg:x1; val_offset:1018*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1018*FLEN/8, x2, x8, x12) + +inst_542: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x104 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x03f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3904; op2val:0x43f; + valaddr_reg:x1; val_offset:1020*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1020*FLEN/8, x2, x8, x12) + +inst_543: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x104 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x03f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3904; op2val:0x43f; + valaddr_reg:x1; val_offset:1022*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1022*FLEN/8, x2, x8, x12) + +inst_544: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x104 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x03f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3904; op2val:0x43f; + valaddr_reg:x1; val_offset:1024*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1024*FLEN/8, x2, x8, x12) + +inst_545: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x363 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b63; op2val:0x2e2; + valaddr_reg:x1; val_offset:1026*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1026*FLEN/8, x2, x8, x12) + +inst_546: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x363 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b63; op2val:0x2e2; + valaddr_reg:x1; val_offset:1028*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1028*FLEN/8, x2, x8, x12) + +inst_547: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x363 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b63; op2val:0x2e2; + valaddr_reg:x1; val_offset:1030*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1030*FLEN/8, x2, x8, x12) + +inst_548: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x363 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b63; op2val:0x2e2; + valaddr_reg:x1; val_offset:1032*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1032*FLEN/8, x2, x8, x12) + +inst_549: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x363 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b63; op2val:0x2e2; + valaddr_reg:x1; val_offset:1034*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1034*FLEN/8, x2, x8, x12) + +inst_550: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x276 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x34c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a76; op2val:0x34c; + valaddr_reg:x1; val_offset:1036*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1036*FLEN/8, x2, x8, x12) + +inst_551: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x276 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x34c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a76; op2val:0x34c; + valaddr_reg:x1; val_offset:1038*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1038*FLEN/8, x2, x8, x12) + +inst_552: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x276 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x34c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a76; op2val:0x34c; + valaddr_reg:x1; val_offset:1040*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1040*FLEN/8, x2, x8, x12) + +inst_553: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x276 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x34c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a76; op2val:0x34c; + valaddr_reg:x1; val_offset:1042*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1042*FLEN/8, x2, x8, x12) + +inst_554: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x276 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x34c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a76; op2val:0x34c; + valaddr_reg:x1; val_offset:1044*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1044*FLEN/8, x2, x8, x12) + +inst_555: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0dd and fs2 == 0 and fe2 == 0x01 and fm2 == 0x061 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x38dd; op2val:0x461; + valaddr_reg:x1; val_offset:1046*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1046*FLEN/8, x2, x8, x12) + +inst_556: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0dd and fs2 == 0 and fe2 == 0x01 and fm2 == 0x061 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x38dd; op2val:0x461; + valaddr_reg:x1; val_offset:1048*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1048*FLEN/8, x2, x8, x12) + +inst_557: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0dd and fs2 == 0 and fe2 == 0x01 and fm2 == 0x061 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x38dd; op2val:0x461; + valaddr_reg:x1; val_offset:1050*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1050*FLEN/8, x2, x8, x12) + +inst_558: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0dd and fs2 == 0 and fe2 == 0x01 and fm2 == 0x061 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x38dd; op2val:0x461; + valaddr_reg:x1; val_offset:1052*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1052*FLEN/8, x2, x8, x12) + +inst_559: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0dd and fs2 == 0 and fe2 == 0x01 and fm2 == 0x061 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x38dd; op2val:0x461; + valaddr_reg:x1; val_offset:1054*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1054*FLEN/8, x2, x8, x12) + +inst_560: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3e2 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x167 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x33e2; op2val:0x967; + valaddr_reg:x1; val_offset:1056*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1056*FLEN/8, x2, x8, x12) + +inst_561: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3e2 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x167 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x33e2; op2val:0x967; + valaddr_reg:x1; val_offset:1058*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1058*FLEN/8, x2, x8, x12) + +inst_562: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3e2 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x167 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x33e2; op2val:0x967; + valaddr_reg:x1; val_offset:1060*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1060*FLEN/8, x2, x8, x12) + +inst_563: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3e2 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x167 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x33e2; op2val:0x967; + valaddr_reg:x1; val_offset:1062*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1062*FLEN/8, x2, x8, x12) + +inst_564: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3e2 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x167 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x33e2; op2val:0x967; + valaddr_reg:x1; val_offset:1064*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1064*FLEN/8, x2, x8, x12) + +inst_565: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x306 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x308 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b06; op2val:0x308; + valaddr_reg:x1; val_offset:1066*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1066*FLEN/8, x2, x8, x12) + +inst_566: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x306 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x308 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b06; op2val:0x308; + valaddr_reg:x1; val_offset:1068*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1068*FLEN/8, x2, x8, x12) + +inst_567: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x306 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x308 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b06; op2val:0x308; + valaddr_reg:x1; val_offset:1070*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1070*FLEN/8, x2, x8, x12) + +inst_568: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x306 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x308 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b06; op2val:0x308; + valaddr_reg:x1; val_offset:1072*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1072*FLEN/8, x2, x8, x12) + +inst_569: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x306 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x308 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b06; op2val:0x308; + valaddr_reg:x1; val_offset:1074*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1074*FLEN/8, x2, x8, x12) + +inst_570: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x35b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b5b; op2val:0x2e5; + valaddr_reg:x1; val_offset:1076*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1076*FLEN/8, x2, x8, x12) + +inst_571: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x35b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b5b; op2val:0x2e5; + valaddr_reg:x1; val_offset:1078*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1078*FLEN/8, x2, x8, x12) + +inst_572: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x35b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b5b; op2val:0x2e5; + valaddr_reg:x1; val_offset:1080*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1080*FLEN/8, x2, x8, x12) + +inst_573: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x35b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b5b; op2val:0x2e5; + valaddr_reg:x1; val_offset:1082*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1082*FLEN/8, x2, x8, x12) + +inst_574: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x35b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b5b; op2val:0x2e5; + valaddr_reg:x1; val_offset:1084*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1084*FLEN/8, x2, x8, x12) + +inst_575: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1be and fs2 == 0 and fe2 == 0x01 and fm2 == 0x36b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x35be; op2val:0x76b; + valaddr_reg:x1; val_offset:1086*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1086*FLEN/8, x2, x8, x12) + +inst_576: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1be and fs2 == 0 and fe2 == 0x01 and fm2 == 0x36b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x35be; op2val:0x76b; + valaddr_reg:x1; val_offset:1088*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1088*FLEN/8, x2, x8, x12) + +inst_577: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1be and fs2 == 0 and fe2 == 0x01 and fm2 == 0x36b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x35be; op2val:0x76b; + valaddr_reg:x1; val_offset:1090*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1090*FLEN/8, x2, x8, x12) + +inst_578: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1be and fs2 == 0 and fe2 == 0x01 and fm2 == 0x36b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x35be; op2val:0x76b; + valaddr_reg:x1; val_offset:1092*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1092*FLEN/8, x2, x8, x12) + +inst_579: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1be and fs2 == 0 and fe2 == 0x01 and fm2 == 0x36b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x35be; op2val:0x76b; + valaddr_reg:x1; val_offset:1094*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1094*FLEN/8, x2, x8, x12) + +inst_580: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0eb and fs2 == 0 and fe2 == 0x02 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x34eb; op2val:0x855; + valaddr_reg:x1; val_offset:1096*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1096*FLEN/8, x2, x8, x12) + +inst_581: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0eb and fs2 == 0 and fe2 == 0x02 and fm2 == 0x055 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x34eb; op2val:0x855; + valaddr_reg:x1; val_offset:1098*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1098*FLEN/8, x2, x8, x12) + +inst_582: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0eb and fs2 == 0 and fe2 == 0x02 and fm2 == 0x055 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x34eb; op2val:0x855; + valaddr_reg:x1; val_offset:1100*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1100*FLEN/8, x2, x8, x12) + +inst_583: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0eb and fs2 == 0 and fe2 == 0x02 and fm2 == 0x055 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x34eb; op2val:0x855; + valaddr_reg:x1; val_offset:1102*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1102*FLEN/8, x2, x8, x12) + +inst_584: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0eb and fs2 == 0 and fe2 == 0x02 and fm2 == 0x055 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x34eb; op2val:0x855; + valaddr_reg:x1; val_offset:1104*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1104*FLEN/8, x2, x8, x12) + +inst_585: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x174 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3d0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3574; op2val:0x7d0; + valaddr_reg:x1; val_offset:1106*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1106*FLEN/8, x2, x8, x12) + +inst_586: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x174 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3d0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3574; op2val:0x7d0; + valaddr_reg:x1; val_offset:1108*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1108*FLEN/8, x2, x8, x12) + +inst_587: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x174 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3d0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3574; op2val:0x7d0; + valaddr_reg:x1; val_offset:1110*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1110*FLEN/8, x2, x8, x12) + +inst_588: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x174 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3d0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3574; op2val:0x7d0; + valaddr_reg:x1; val_offset:1112*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1112*FLEN/8, x2, x8, x12) + +inst_589: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x174 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3d0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3574; op2val:0x7d0; + valaddr_reg:x1; val_offset:1114*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1114*FLEN/8, x2, x8, x12) + +inst_590: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x06c and fs2 == 0 and fe2 == 0x02 and fm2 == 0x0d1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x346c; op2val:0x8d1; + valaddr_reg:x1; val_offset:1116*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1116*FLEN/8, x2, x8, x12) + +inst_591: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x06c and fs2 == 0 and fe2 == 0x02 and fm2 == 0x0d1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x346c; op2val:0x8d1; + valaddr_reg:x1; val_offset:1118*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1118*FLEN/8, x2, x8, x12) + +inst_592: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x06c and fs2 == 0 and fe2 == 0x02 and fm2 == 0x0d1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x346c; op2val:0x8d1; + valaddr_reg:x1; val_offset:1120*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1120*FLEN/8, x2, x8, x12) + +inst_593: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x06c and fs2 == 0 and fe2 == 0x02 and fm2 == 0x0d1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x346c; op2val:0x8d1; + valaddr_reg:x1; val_offset:1122*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1122*FLEN/8, x2, x8, x12) + +inst_594: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x06c and fs2 == 0 and fe2 == 0x02 and fm2 == 0x0d1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x346c; op2val:0x8d1; + valaddr_reg:x1; val_offset:1124*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1124*FLEN/8, x2, x8, x12) + +inst_595: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x123 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x025 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3923; op2val:0x425; + valaddr_reg:x1; val_offset:1126*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1126*FLEN/8, x2, x8, x12) + +inst_596: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x123 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x025 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3923; op2val:0x425; + valaddr_reg:x1; val_offset:1128*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1128*FLEN/8, x2, x8, x12) + +inst_597: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x123 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x025 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3923; op2val:0x425; + valaddr_reg:x1; val_offset:1130*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1130*FLEN/8, x2, x8, x12) + +inst_598: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x123 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x025 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3923; op2val:0x425; + valaddr_reg:x1; val_offset:1132*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1132*FLEN/8, x2, x8, x12) + +inst_599: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x123 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x025 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3923; op2val:0x425; + valaddr_reg:x1; val_offset:1134*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1134*FLEN/8, x2, x8, x12) + +inst_600: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x271 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3271; op2val:0xa9e; + valaddr_reg:x1; val_offset:1136*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1136*FLEN/8, x2, x8, x12) + +inst_601: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x271 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3271; op2val:0xa9e; + valaddr_reg:x1; val_offset:1138*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1138*FLEN/8, x2, x8, x12) + +inst_602: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x271 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3271; op2val:0xa9e; + valaddr_reg:x1; val_offset:1140*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1140*FLEN/8, x2, x8, x12) + +inst_603: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x271 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3271; op2val:0xa9e; + valaddr_reg:x1; val_offset:1142*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1142*FLEN/8, x2, x8, x12) + +inst_604: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x271 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x29e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3271; op2val:0xa9e; + valaddr_reg:x1; val_offset:1144*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1144*FLEN/8, x2, x8, x12) + +inst_605: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x394 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x19f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3794; op2val:0x59f; + valaddr_reg:x1; val_offset:1146*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1146*FLEN/8, x2, x8, x12) + +inst_606: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x394 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x19f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3794; op2val:0x59f; + valaddr_reg:x1; val_offset:1148*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1148*FLEN/8, x2, x8, x12) + +inst_607: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x394 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x19f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3794; op2val:0x59f; + valaddr_reg:x1; val_offset:1150*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1150*FLEN/8, x2, x8, x12) + +inst_608: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x394 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x19f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3794; op2val:0x59f; + valaddr_reg:x1; val_offset:1152*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1152*FLEN/8, x2, x8, x12) + +inst_609: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x394 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x19f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3794; op2val:0x59f; + valaddr_reg:x1; val_offset:1154*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1154*FLEN/8, x2, x8, x12) + +inst_610: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x1cd and fs2 == 0 and fe2 == 0x04 and fm2 == 0x358 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x29cd; op2val:0x1358; + valaddr_reg:x1; val_offset:1156*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1156*FLEN/8, x2, x8, x12) + +inst_611: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x1cd and fs2 == 0 and fe2 == 0x04 and fm2 == 0x358 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x29cd; op2val:0x1358; + valaddr_reg:x1; val_offset:1158*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1158*FLEN/8, x2, x8, x12) + +inst_612: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x1cd and fs2 == 0 and fe2 == 0x04 and fm2 == 0x358 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x29cd; op2val:0x1358; + valaddr_reg:x1; val_offset:1160*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1160*FLEN/8, x2, x8, x12) + +inst_613: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x1cd and fs2 == 0 and fe2 == 0x04 and fm2 == 0x358 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x29cd; op2val:0x1358; + valaddr_reg:x1; val_offset:1162*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1162*FLEN/8, x2, x8, x12) + +inst_614: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x1cd and fs2 == 0 and fe2 == 0x04 and fm2 == 0x358 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x29cd; op2val:0x1358; + valaddr_reg:x1; val_offset:1164*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1164*FLEN/8, x2, x8, x12) + +inst_615: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x059 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x0e6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2c59; op2val:0x10e6; + valaddr_reg:x1; val_offset:1166*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1166*FLEN/8, x2, x8, x12) + +inst_616: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x059 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x0e6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2c59; op2val:0x10e6; + valaddr_reg:x1; val_offset:1168*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1168*FLEN/8, x2, x8, x12) + +inst_617: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x059 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x0e6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2c59; op2val:0x10e6; + valaddr_reg:x1; val_offset:1170*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1170*FLEN/8, x2, x8, x12) + +inst_618: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x059 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x0e6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2c59; op2val:0x10e6; + valaddr_reg:x1; val_offset:1172*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1172*FLEN/8, x2, x8, x12) + +inst_619: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x059 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x0e6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2c59; op2val:0x10e6; + valaddr_reg:x1; val_offset:1174*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1174*FLEN/8, x2, x8, x12) + +inst_620: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3c9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x39a0; op2val:0x3c9; + valaddr_reg:x1; val_offset:1176*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1176*FLEN/8, x2, x8, x12) + +inst_621: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3c9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x39a0; op2val:0x3c9; + valaddr_reg:x1; val_offset:1178*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1178*FLEN/8, x2, x8, x12) + +inst_622: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3c9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x39a0; op2val:0x3c9; + valaddr_reg:x1; val_offset:1180*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1180*FLEN/8, x2, x8, x12) + +inst_623: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3c9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x39a0; op2val:0x3c9; + valaddr_reg:x1; val_offset:1182*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1182*FLEN/8, x2, x8, x12) + +inst_624: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3c9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x39a0; op2val:0x3c9; + valaddr_reg:x1; val_offset:1184*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1184*FLEN/8, x2, x8, x12) + +inst_625: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x017 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3d4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3817; op2val:0x7d4; + valaddr_reg:x1; val_offset:1186*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1186*FLEN/8, x2, x8, x12) + +inst_626: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x017 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3d4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3817; op2val:0x7d4; + valaddr_reg:x1; val_offset:1188*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1188*FLEN/8, x2, x8, x12) + +inst_627: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x017 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3d4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3817; op2val:0x7d4; + valaddr_reg:x1; val_offset:1190*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1190*FLEN/8, x2, x8, x12) + +inst_628: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x017 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3d4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3817; op2val:0x7d4; + valaddr_reg:x1; val_offset:1192*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1192*FLEN/8, x2, x8, x12) + +inst_629: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x017 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3d4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3817; op2val:0x7d4; + valaddr_reg:x1; val_offset:1194*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1194*FLEN/8, x2, x8, x12) + +inst_630: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x094 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x2fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3894; op2val:0x6fe; + valaddr_reg:x1; val_offset:1196*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1196*FLEN/8, x2, x8, x12) + +inst_631: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x094 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x2fe and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3894; op2val:0x6fe; + valaddr_reg:x1; val_offset:1198*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1198*FLEN/8, x2, x8, x12) + +inst_632: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x094 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x2fe and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3894; op2val:0x6fe; + valaddr_reg:x1; val_offset:1200*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1200*FLEN/8, x2, x8, x12) + +inst_633: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x094 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x2fe and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3894; op2val:0x6fe; + valaddr_reg:x1; val_offset:1202*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1202*FLEN/8, x2, x8, x12) + +inst_634: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x094 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x2fe and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3894; op2val:0x6fe; + valaddr_reg:x1; val_offset:1204*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1204*FLEN/8, x2, x8, x12) + +inst_635: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x136 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x224 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d36; op2val:0x1224; + valaddr_reg:x1; val_offset:1206*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1206*FLEN/8, x2, x8, x12) + +inst_636: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x136 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x224 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d36; op2val:0x1224; + valaddr_reg:x1; val_offset:1208*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1208*FLEN/8, x2, x8, x12) + +inst_637: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x136 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x224 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d36; op2val:0x1224; + valaddr_reg:x1; val_offset:1210*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1210*FLEN/8, x2, x8, x12) + +inst_638: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x136 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x224 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d36; op2val:0x1224; + valaddr_reg:x1; val_offset:1212*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1212*FLEN/8, x2, x8, x12) + +inst_639: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x136 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x224 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d36; op2val:0x1224; + valaddr_reg:x1; val_offset:1214*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1214*FLEN/8, x2, x8, x12) + +inst_640: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1d4 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x17e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x31d4; op2val:0xd7e; + valaddr_reg:x1; val_offset:1216*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1216*FLEN/8, x2, x8, x12) + +inst_641: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1d4 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x17e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x31d4; op2val:0xd7e; + valaddr_reg:x1; val_offset:1218*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1218*FLEN/8, x2, x8, x12) + +inst_642: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1d4 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x17e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x31d4; op2val:0xd7e; + valaddr_reg:x1; val_offset:1220*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1220*FLEN/8, x2, x8, x12) + +inst_643: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1d4 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x17e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x31d4; op2val:0xd7e; + valaddr_reg:x1; val_offset:1222*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1222*FLEN/8, x2, x8, x12) + +inst_644: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1d4 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x17e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x31d4; op2val:0xd7e; + valaddr_reg:x1; val_offset:1224*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1224*FLEN/8, x2, x8, x12) + +inst_645: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x126 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x237 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3926; op2val:0x637; + valaddr_reg:x1; val_offset:1226*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1226*FLEN/8, x2, x8, x12) + +inst_646: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x126 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x237 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3926; op2val:0x637; + valaddr_reg:x1; val_offset:1228*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1228*FLEN/8, x2, x8, x12) + +inst_647: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x126 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x237 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3926; op2val:0x637; + valaddr_reg:x1; val_offset:1230*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1230*FLEN/8, x2, x8, x12) + +inst_648: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x126 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x237 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3926; op2val:0x637; + valaddr_reg:x1; val_offset:1232*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1232*FLEN/8, x2, x8, x12) + +inst_649: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x126 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x237 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3926; op2val:0x637; + valaddr_reg:x1; val_offset:1234*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1234*FLEN/8, x2, x8, x12) + +inst_650: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d3 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0b1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ad3; op2val:0x4b1; + valaddr_reg:x1; val_offset:1236*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1236*FLEN/8, x2, x8, x12) + +inst_651: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d3 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0b1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ad3; op2val:0x4b1; + valaddr_reg:x1; val_offset:1238*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1238*FLEN/8, x2, x8, x12) + +inst_652: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d3 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0b1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ad3; op2val:0x4b1; + valaddr_reg:x1; val_offset:1240*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1240*FLEN/8, x2, x8, x12) + +inst_653: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d3 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0b1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ad3; op2val:0x4b1; + valaddr_reg:x1; val_offset:1242*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1242*FLEN/8, x2, x8, x12) + +inst_654: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d3 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0b1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ad3; op2val:0x4b1; + valaddr_reg:x1; val_offset:1244*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1244*FLEN/8, x2, x8, x12) + +inst_655: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x377 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x04a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b77; op2val:0x44a; + valaddr_reg:x1; val_offset:1246*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1246*FLEN/8, x2, x8, x12) + +inst_656: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x377 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x04a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b77; op2val:0x44a; + valaddr_reg:x1; val_offset:1248*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1248*FLEN/8, x2, x8, x12) + +inst_657: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x377 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x04a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b77; op2val:0x44a; + valaddr_reg:x1; val_offset:1250*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1250*FLEN/8, x2, x8, x12) + +inst_658: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x377 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x04a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b77; op2val:0x44a; + valaddr_reg:x1; val_offset:1252*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1252*FLEN/8, x2, x8, x12) + +inst_659: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x377 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x04a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b77; op2val:0x44a; + valaddr_reg:x1; val_offset:1254*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1254*FLEN/8, x2, x8, x12) + +inst_660: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2b1 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x0c9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2eb1; op2val:0x10c9; + valaddr_reg:x1; val_offset:1256*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1256*FLEN/8, x2, x8, x12) + +inst_661: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2b1 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x0c9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2eb1; op2val:0x10c9; + valaddr_reg:x1; val_offset:1258*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1258*FLEN/8, x2, x8, x12) + +inst_662: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2b1 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x0c9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2eb1; op2val:0x10c9; + valaddr_reg:x1; val_offset:1260*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1260*FLEN/8, x2, x8, x12) + +inst_663: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2b1 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x0c9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2eb1; op2val:0x10c9; + valaddr_reg:x1; val_offset:1262*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1262*FLEN/8, x2, x8, x12) +RVTEST_SIGBASE(x8,signature_x8_5) + +inst_664: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2b1 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x0c9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2eb1; op2val:0x10c9; + valaddr_reg:x1; val_offset:1264*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1264*FLEN/8, x2, x8, x12) + +inst_665: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a1 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x1b0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x35a1; op2val:0x9b0; + valaddr_reg:x1; val_offset:1266*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1266*FLEN/8, x2, x8, x12) + +inst_666: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a1 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x1b0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x35a1; op2val:0x9b0; + valaddr_reg:x1; val_offset:1268*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1268*FLEN/8, x2, x8, x12) + +inst_667: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a1 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x1b0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x35a1; op2val:0x9b0; + valaddr_reg:x1; val_offset:1270*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1270*FLEN/8, x2, x8, x12) + +inst_668: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a1 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x1b0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x35a1; op2val:0x9b0; + valaddr_reg:x1; val_offset:1272*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1272*FLEN/8, x2, x8, x12) + +inst_669: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a1 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x1b0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x35a1; op2val:0x9b0; + valaddr_reg:x1; val_offset:1274*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1274*FLEN/8, x2, x8, x12) + +inst_670: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a1 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1b0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x39a1; op2val:0x5b0; + valaddr_reg:x1; val_offset:1276*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1276*FLEN/8, x2, x8, x12) + +inst_671: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a1 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1b0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x39a1; op2val:0x5b0; + valaddr_reg:x1; val_offset:1278*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1278*FLEN/8, x2, x8, x12) + +inst_672: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a1 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1b0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x39a1; op2val:0x5b0; + valaddr_reg:x1; val_offset:1280*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1280*FLEN/8, x2, x8, x12) + +inst_673: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a1 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1b0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x39a1; op2val:0x5b0; + valaddr_reg:x1; val_offset:1282*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1282*FLEN/8, x2, x8, x12) + +inst_674: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a1 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1b0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x39a1; op2val:0x5b0; + valaddr_reg:x1; val_offset:1284*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1284*FLEN/8, x2, x8, x12) + +inst_675: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x144 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x214 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3544; op2val:0xa14; + valaddr_reg:x1; val_offset:1286*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1286*FLEN/8, x2, x8, x12) + +inst_676: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x144 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x214 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3544; op2val:0xa14; + valaddr_reg:x1; val_offset:1288*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1288*FLEN/8, x2, x8, x12) + +inst_677: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x144 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x214 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3544; op2val:0xa14; + valaddr_reg:x1; val_offset:1290*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1290*FLEN/8, x2, x8, x12) + +inst_678: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x144 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x214 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3544; op2val:0xa14; + valaddr_reg:x1; val_offset:1292*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1292*FLEN/8, x2, x8, x12) + +inst_679: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x144 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x214 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3544; op2val:0xa14; + valaddr_reg:x1; val_offset:1294*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1294*FLEN/8, x2, x8, x12) + +inst_680: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x07d and fs2 == 0 and fe2 == 0x01 and fm2 == 0x322 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x387d; op2val:0x722; + valaddr_reg:x1; val_offset:1296*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1296*FLEN/8, x2, x8, x12) + +inst_681: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x07d and fs2 == 0 and fe2 == 0x01 and fm2 == 0x322 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x387d; op2val:0x722; + valaddr_reg:x1; val_offset:1298*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1298*FLEN/8, x2, x8, x12) + +inst_682: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x07d and fs2 == 0 and fe2 == 0x01 and fm2 == 0x322 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x387d; op2val:0x722; + valaddr_reg:x1; val_offset:1300*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1300*FLEN/8, x2, x8, x12) + +inst_683: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x07d and fs2 == 0 and fe2 == 0x01 and fm2 == 0x322 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x387d; op2val:0x722; + valaddr_reg:x1; val_offset:1302*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1302*FLEN/8, x2, x8, x12) + +inst_684: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x07d and fs2 == 0 and fe2 == 0x01 and fm2 == 0x322 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x387d; op2val:0x722; + valaddr_reg:x1; val_offset:1304*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1304*FLEN/8, x2, x8, x12) + +inst_685: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x082 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b1a; op2val:0x482; + valaddr_reg:x1; val_offset:1306*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1306*FLEN/8, x2, x8, x12) + +inst_686: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x082 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b1a; op2val:0x482; + valaddr_reg:x1; val_offset:1308*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1308*FLEN/8, x2, x8, x12) + +inst_687: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x082 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b1a; op2val:0x482; + valaddr_reg:x1; val_offset:1310*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1310*FLEN/8, x2, x8, x12) + +inst_688: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x082 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b1a; op2val:0x482; + valaddr_reg:x1; val_offset:1312*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1312*FLEN/8, x2, x8, x12) + +inst_689: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x082 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b1a; op2val:0x482; + valaddr_reg:x1; val_offset:1314*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1314*FLEN/8, x2, x8, x12) + +inst_690: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x26a and fs2 == 0 and fe2 == 0x05 and fm2 == 0x0fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2a6a; op2val:0x14fe; + valaddr_reg:x1; val_offset:1316*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1316*FLEN/8, x2, x8, x12) + +inst_691: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x26a and fs2 == 0 and fe2 == 0x05 and fm2 == 0x0fe and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2a6a; op2val:0x14fe; + valaddr_reg:x1; val_offset:1318*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1318*FLEN/8, x2, x8, x12) + +inst_692: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x26a and fs2 == 0 and fe2 == 0x05 and fm2 == 0x0fe and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2a6a; op2val:0x14fe; + valaddr_reg:x1; val_offset:1320*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1320*FLEN/8, x2, x8, x12) + +inst_693: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x26a and fs2 == 0 and fe2 == 0x05 and fm2 == 0x0fe and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2a6a; op2val:0x14fe; + valaddr_reg:x1; val_offset:1322*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1322*FLEN/8, x2, x8, x12) + +inst_694: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x26a and fs2 == 0 and fe2 == 0x05 and fm2 == 0x0fe and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2a6a; op2val:0x14fe; + valaddr_reg:x1; val_offset:1324*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1324*FLEN/8, x2, x8, x12) + +inst_695: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x33b and fs2 == 0 and fe2 == 0x01 and fm2 == 0x06e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b3b; op2val:0x46e; + valaddr_reg:x1; val_offset:1326*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1326*FLEN/8, x2, x8, x12) + +inst_696: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x33b and fs2 == 0 and fe2 == 0x01 and fm2 == 0x06e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b3b; op2val:0x46e; + valaddr_reg:x1; val_offset:1328*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1328*FLEN/8, x2, x8, x12) + +inst_697: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x33b and fs2 == 0 and fe2 == 0x01 and fm2 == 0x06e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b3b; op2val:0x46e; + valaddr_reg:x1; val_offset:1330*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1330*FLEN/8, x2, x8, x12) + +inst_698: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x33b and fs2 == 0 and fe2 == 0x01 and fm2 == 0x06e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b3b; op2val:0x46e; + valaddr_reg:x1; val_offset:1332*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1332*FLEN/8, x2, x8, x12) + +inst_699: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x33b and fs2 == 0 and fe2 == 0x01 and fm2 == 0x06e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b3b; op2val:0x46e; + valaddr_reg:x1; val_offset:1334*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1334*FLEN/8, x2, x8, x12) + +inst_700: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x08e and fs2 == 0 and fe2 == 0x02 and fm2 == 0x308 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x348e; op2val:0xb08; + valaddr_reg:x1; val_offset:1336*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1336*FLEN/8, x2, x8, x12) + +inst_701: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x08e and fs2 == 0 and fe2 == 0x02 and fm2 == 0x308 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x348e; op2val:0xb08; + valaddr_reg:x1; val_offset:1338*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1338*FLEN/8, x2, x8, x12) + +inst_702: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x08e and fs2 == 0 and fe2 == 0x02 and fm2 == 0x308 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x348e; op2val:0xb08; + valaddr_reg:x1; val_offset:1340*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1340*FLEN/8, x2, x8, x12) + +inst_703: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x08e and fs2 == 0 and fe2 == 0x02 and fm2 == 0x308 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x348e; op2val:0xb08; + valaddr_reg:x1; val_offset:1342*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1342*FLEN/8, x2, x8, x12) + +inst_704: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x08e and fs2 == 0 and fe2 == 0x02 and fm2 == 0x308 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x348e; op2val:0xb08; + valaddr_reg:x1; val_offset:1344*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1344*FLEN/8, x2, x8, x12) + +inst_705: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2ba and fs2 == 0 and fe2 == 0x04 and fm2 == 0x0c2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2eba; op2val:0x10c2; + valaddr_reg:x1; val_offset:1346*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1346*FLEN/8, x2, x8, x12) + +inst_706: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2ba and fs2 == 0 and fe2 == 0x04 and fm2 == 0x0c2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2eba; op2val:0x10c2; + valaddr_reg:x1; val_offset:1348*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1348*FLEN/8, x2, x8, x12) + +inst_707: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2ba and fs2 == 0 and fe2 == 0x04 and fm2 == 0x0c2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2eba; op2val:0x10c2; + valaddr_reg:x1; val_offset:1350*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1350*FLEN/8, x2, x8, x12) + +inst_708: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2ba and fs2 == 0 and fe2 == 0x04 and fm2 == 0x0c2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2eba; op2val:0x10c2; + valaddr_reg:x1; val_offset:1352*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1352*FLEN/8, x2, x8, x12) + +inst_709: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2ba and fs2 == 0 and fe2 == 0x04 and fm2 == 0x0c2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2eba; op2val:0x10c2; + valaddr_reg:x1; val_offset:1354*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1354*FLEN/8, x2, x8, x12) + +inst_710: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0bf and fs2 == 0 and fe2 == 0x02 and fm2 == 0x2be and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x34bf; op2val:0xabe; + valaddr_reg:x1; val_offset:1356*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1356*FLEN/8, x2, x8, x12) + +inst_711: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0bf and fs2 == 0 and fe2 == 0x02 and fm2 == 0x2be and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x34bf; op2val:0xabe; + valaddr_reg:x1; val_offset:1358*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1358*FLEN/8, x2, x8, x12) + +inst_712: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0bf and fs2 == 0 and fe2 == 0x02 and fm2 == 0x2be and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x34bf; op2val:0xabe; + valaddr_reg:x1; val_offset:1360*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1360*FLEN/8, x2, x8, x12) + +inst_713: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0bf and fs2 == 0 and fe2 == 0x02 and fm2 == 0x2be and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x34bf; op2val:0xabe; + valaddr_reg:x1; val_offset:1362*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1362*FLEN/8, x2, x8, x12) + +inst_714: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0bf and fs2 == 0 and fe2 == 0x02 and fm2 == 0x2be and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x34bf; op2val:0xabe; + valaddr_reg:x1; val_offset:1364*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1364*FLEN/8, x2, x8, x12) + +inst_715: +// fs1 == 0 and fe1 == 0x07 and fm1 == 0x10b and fs2 == 0 and fe2 == 0x08 and fm2 == 0x259 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x1d0b; op2val:0x2259; + valaddr_reg:x1; val_offset:1366*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1366*FLEN/8, x2, x8, x12) + +inst_716: +// fs1 == 0 and fe1 == 0x07 and fm1 == 0x10b and fs2 == 0 and fe2 == 0x08 and fm2 == 0x259 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x1d0b; op2val:0x2259; + valaddr_reg:x1; val_offset:1368*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1368*FLEN/8, x2, x8, x12) + +inst_717: +// fs1 == 0 and fe1 == 0x07 and fm1 == 0x10b and fs2 == 0 and fe2 == 0x08 and fm2 == 0x259 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x1d0b; op2val:0x2259; + valaddr_reg:x1; val_offset:1370*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1370*FLEN/8, x2, x8, x12) + +inst_718: +// fs1 == 0 and fe1 == 0x07 and fm1 == 0x10b and fs2 == 0 and fe2 == 0x08 and fm2 == 0x259 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x1d0b; op2val:0x2259; + valaddr_reg:x1; val_offset:1372*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1372*FLEN/8, x2, x8, x12) + +inst_719: +// fs1 == 0 and fe1 == 0x07 and fm1 == 0x10b and fs2 == 0 and fe2 == 0x08 and fm2 == 0x259 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x1d0b; op2val:0x2259; + valaddr_reg:x1; val_offset:1374*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1374*FLEN/8, x2, x8, x12) + +inst_720: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2d3 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x0b1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x36d3; op2val:0x8b1; + valaddr_reg:x1; val_offset:1376*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1376*FLEN/8, x2, x8, x12) + +inst_721: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2d3 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x0b1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x36d3; op2val:0x8b1; + valaddr_reg:x1; val_offset:1378*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1378*FLEN/8, x2, x8, x12) + +inst_722: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2d3 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x0b1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x36d3; op2val:0x8b1; + valaddr_reg:x1; val_offset:1380*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1380*FLEN/8, x2, x8, x12) + +inst_723: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2d3 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x0b1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x36d3; op2val:0x8b1; + valaddr_reg:x1; val_offset:1382*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1382*FLEN/8, x2, x8, x12) + +inst_724: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2d3 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x0b1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x36d3; op2val:0x8b1; + valaddr_reg:x1; val_offset:1384*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1384*FLEN/8, x2, x8, x12) + +inst_725: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x078 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x32a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3878; op2val:0x72a; + valaddr_reg:x1; val_offset:1386*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1386*FLEN/8, x2, x8, x12) + +inst_726: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x078 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x32a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3878; op2val:0x72a; + valaddr_reg:x1; val_offset:1388*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1388*FLEN/8, x2, x8, x12) + +inst_727: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x078 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x32a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3878; op2val:0x72a; + valaddr_reg:x1; val_offset:1390*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1390*FLEN/8, x2, x8, x12) + +inst_728: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x078 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x32a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3878; op2val:0x72a; + valaddr_reg:x1; val_offset:1392*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1392*FLEN/8, x2, x8, x12) + +inst_729: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x078 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x32a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3878; op2val:0x72a; + valaddr_reg:x1; val_offset:1394*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1394*FLEN/8, x2, x8, x12) + +inst_730: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x27a and fs2 == 0 and fe2 == 0x02 and fm2 == 0x0f2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x367a; op2val:0x8f2; + valaddr_reg:x1; val_offset:1396*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1396*FLEN/8, x2, x8, x12) + +inst_731: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x27a and fs2 == 0 and fe2 == 0x02 and fm2 == 0x0f2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x367a; op2val:0x8f2; + valaddr_reg:x1; val_offset:1398*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1398*FLEN/8, x2, x8, x12) + +inst_732: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x27a and fs2 == 0 and fe2 == 0x02 and fm2 == 0x0f2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x367a; op2val:0x8f2; + valaddr_reg:x1; val_offset:1400*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1400*FLEN/8, x2, x8, x12) + +inst_733: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x27a and fs2 == 0 and fe2 == 0x02 and fm2 == 0x0f2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x367a; op2val:0x8f2; + valaddr_reg:x1; val_offset:1402*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1402*FLEN/8, x2, x8, x12) + +inst_734: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x27a and fs2 == 0 and fe2 == 0x02 and fm2 == 0x0f2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x367a; op2val:0x8f2; + valaddr_reg:x1; val_offset:1404*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1404*FLEN/8, x2, x8, x12) + +inst_735: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x28e and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0e2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a8e; op2val:0x4e2; + valaddr_reg:x1; val_offset:1406*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1406*FLEN/8, x2, x8, x12) + +inst_736: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x28e and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0e2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a8e; op2val:0x4e2; + valaddr_reg:x1; val_offset:1408*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1408*FLEN/8, x2, x8, x12) + +inst_737: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x28e and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0e2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a8e; op2val:0x4e2; + valaddr_reg:x1; val_offset:1410*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1410*FLEN/8, x2, x8, x12) + +inst_738: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x28e and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0e2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a8e; op2val:0x4e2; + valaddr_reg:x1; val_offset:1412*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1412*FLEN/8, x2, x8, x12) + +inst_739: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x28e and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0e2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a8e; op2val:0x4e2; + valaddr_reg:x1; val_offset:1414*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1414*FLEN/8, x2, x8, x12) + +inst_740: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x023 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3bc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3823; op2val:0x7bc; + valaddr_reg:x1; val_offset:1416*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1416*FLEN/8, x2, x8, x12) + +inst_741: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x023 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3bc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3823; op2val:0x7bc; + valaddr_reg:x1; val_offset:1418*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1418*FLEN/8, x2, x8, x12) + +inst_742: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x023 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3bc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3823; op2val:0x7bc; + valaddr_reg:x1; val_offset:1420*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1420*FLEN/8, x2, x8, x12) + +inst_743: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x023 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3bc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3823; op2val:0x7bc; + valaddr_reg:x1; val_offset:1422*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1422*FLEN/8, x2, x8, x12) + +inst_744: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x023 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3bc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3823; op2val:0x7bc; + valaddr_reg:x1; val_offset:1424*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1424*FLEN/8, x2, x8, x12) + +inst_745: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0a2 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x2ea and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x34a2; op2val:0xaea; + valaddr_reg:x1; val_offset:1426*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1426*FLEN/8, x2, x8, x12) + +inst_746: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0a2 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x2ea and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x34a2; op2val:0xaea; + valaddr_reg:x1; val_offset:1428*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1428*FLEN/8, x2, x8, x12) + +inst_747: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0a2 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x2ea and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x34a2; op2val:0xaea; + valaddr_reg:x1; val_offset:1430*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1430*FLEN/8, x2, x8, x12) + +inst_748: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0a2 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x2ea and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x34a2; op2val:0xaea; + valaddr_reg:x1; val_offset:1432*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1432*FLEN/8, x2, x8, x12) + +inst_749: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0a2 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x2ea and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x34a2; op2val:0xaea; + valaddr_reg:x1; val_offset:1434*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1434*FLEN/8, x2, x8, x12) + +inst_750: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0b6 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x2cb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x34b6; op2val:0xacb; + valaddr_reg:x1; val_offset:1436*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1436*FLEN/8, x2, x8, x12) + +inst_751: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0b6 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x2cb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x34b6; op2val:0xacb; + valaddr_reg:x1; val_offset:1438*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1438*FLEN/8, x2, x8, x12) + +inst_752: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0b6 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x2cb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x34b6; op2val:0xacb; + valaddr_reg:x1; val_offset:1440*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1440*FLEN/8, x2, x8, x12) + +inst_753: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0b6 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x2cb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x34b6; op2val:0xacb; + valaddr_reg:x1; val_offset:1442*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1442*FLEN/8, x2, x8, x12) + +inst_754: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0b6 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x2cb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x34b6; op2val:0xacb; + valaddr_reg:x1; val_offset:1444*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1444*FLEN/8, x2, x8, x12) + +inst_755: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x0df and fs2 == 0 and fe2 == 0x05 and fm2 == 0x292 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x28df; op2val:0x1692; + valaddr_reg:x1; val_offset:1446*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1446*FLEN/8, x2, x8, x12) + +inst_756: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x0df and fs2 == 0 and fe2 == 0x05 and fm2 == 0x292 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x28df; op2val:0x1692; + valaddr_reg:x1; val_offset:1448*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1448*FLEN/8, x2, x8, x12) + +inst_757: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x0df and fs2 == 0 and fe2 == 0x05 and fm2 == 0x292 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x28df; op2val:0x1692; + valaddr_reg:x1; val_offset:1450*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1450*FLEN/8, x2, x8, x12) + +inst_758: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x0df and fs2 == 0 and fe2 == 0x05 and fm2 == 0x292 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x28df; op2val:0x1692; + valaddr_reg:x1; val_offset:1452*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1452*FLEN/8, x2, x8, x12) + +inst_759: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x0df and fs2 == 0 and fe2 == 0x05 and fm2 == 0x292 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x28df; op2val:0x1692; + valaddr_reg:x1; val_offset:1454*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1454*FLEN/8, x2, x8, x12) + +inst_760: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x012 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3de and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3412; op2val:0xbde; + valaddr_reg:x1; val_offset:1456*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1456*FLEN/8, x2, x8, x12) + +inst_761: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x012 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3de and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3412; op2val:0xbde; + valaddr_reg:x1; val_offset:1458*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1458*FLEN/8, x2, x8, x12) + +inst_762: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x012 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3de and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3412; op2val:0xbde; + valaddr_reg:x1; val_offset:1460*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1460*FLEN/8, x2, x8, x12) + +inst_763: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x012 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3de and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3412; op2val:0xbde; + valaddr_reg:x1; val_offset:1462*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1462*FLEN/8, x2, x8, x12) + +inst_764: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x012 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3de and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3412; op2val:0xbde; + valaddr_reg:x1; val_offset:1464*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1464*FLEN/8, x2, x8, x12) + +inst_765: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x032 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x33a1; op2val:0xc32; + valaddr_reg:x1; val_offset:1466*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1466*FLEN/8, x2, x8, x12) + +inst_766: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x032 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x33a1; op2val:0xc32; + valaddr_reg:x1; val_offset:1468*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1468*FLEN/8, x2, x8, x12) + +inst_767: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x032 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x33a1; op2val:0xc32; + valaddr_reg:x1; val_offset:1470*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1470*FLEN/8, x2, x8, x12) + +inst_768: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x032 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x33a1; op2val:0xc32; + valaddr_reg:x1; val_offset:1472*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1472*FLEN/8, x2, x8, x12) + +inst_769: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x032 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x33a1; op2val:0xc32; + valaddr_reg:x1; val_offset:1474*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1474*FLEN/8, x2, x8, x12) + +inst_770: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x233 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a33; op2val:0x52a; + valaddr_reg:x1; val_offset:1476*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1476*FLEN/8, x2, x8, x12) + +inst_771: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x233 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a33; op2val:0x52a; + valaddr_reg:x1; val_offset:1478*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1478*FLEN/8, x2, x8, x12) + +inst_772: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x233 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a33; op2val:0x52a; + valaddr_reg:x1; val_offset:1480*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1480*FLEN/8, x2, x8, x12) + +inst_773: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x233 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a33; op2val:0x52a; + valaddr_reg:x1; val_offset:1482*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1482*FLEN/8, x2, x8, x12) + +inst_774: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x233 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a33; op2val:0x52a; + valaddr_reg:x1; val_offset:1484*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1484*FLEN/8, x2, x8, x12) + +inst_775: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0c7 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x2b4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x38c7; op2val:0x6b4; + valaddr_reg:x1; val_offset:1486*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1486*FLEN/8, x2, x8, x12) + +inst_776: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0c7 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x2b4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x38c7; op2val:0x6b4; + valaddr_reg:x1; val_offset:1488*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1488*FLEN/8, x2, x8, x12) + +inst_777: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0c7 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x2b4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x38c7; op2val:0x6b4; + valaddr_reg:x1; val_offset:1490*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1490*FLEN/8, x2, x8, x12) + +inst_778: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0c7 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x2b4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x38c7; op2val:0x6b4; + valaddr_reg:x1; val_offset:1492*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1492*FLEN/8, x2, x8, x12) + +inst_779: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0c7 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x2b4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x38c7; op2val:0x6b4; + valaddr_reg:x1; val_offset:1494*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1494*FLEN/8, x2, x8, x12) + +inst_780: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x1d7 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x17b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x25d7; op2val:0x197b; + valaddr_reg:x1; val_offset:1496*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1496*FLEN/8, x2, x8, x12) + +inst_781: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x1d7 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x17b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x25d7; op2val:0x197b; + valaddr_reg:x1; val_offset:1498*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1498*FLEN/8, x2, x8, x12) + +inst_782: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x1d7 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x17b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x25d7; op2val:0x197b; + valaddr_reg:x1; val_offset:1500*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1500*FLEN/8, x2, x8, x12) + +inst_783: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x1d7 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x17b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x25d7; op2val:0x197b; + valaddr_reg:x1; val_offset:1502*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1502*FLEN/8, x2, x8, x12) + +inst_784: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x1d7 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x17b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x25d7; op2val:0x197b; + valaddr_reg:x1; val_offset:1504*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1504*FLEN/8, x2, x8, x12) + +inst_785: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e8 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3be8; op2val:0x40d; + valaddr_reg:x1; val_offset:1506*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1506*FLEN/8, x2, x8, x12) + +inst_786: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e8 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3be8; op2val:0x40d; + valaddr_reg:x1; val_offset:1508*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1508*FLEN/8, x2, x8, x12) + +inst_787: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e8 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3be8; op2val:0x40d; + valaddr_reg:x1; val_offset:1510*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1510*FLEN/8, x2, x8, x12) + +inst_788: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e8 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3be8; op2val:0x40d; + valaddr_reg:x1; val_offset:1512*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1512*FLEN/8, x2, x8, x12) + +inst_789: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e8 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3be8; op2val:0x40d; + valaddr_reg:x1; val_offset:1514*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1514*FLEN/8, x2, x8, x12) + +inst_790: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x09d and fs2 == 0 and fe2 == 0x02 and fm2 == 0x2f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x349d; op2val:0xaf0; + valaddr_reg:x1; val_offset:1516*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1516*FLEN/8, x2, x8, x12) + +inst_791: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x09d and fs2 == 0 and fe2 == 0x02 and fm2 == 0x2f0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x349d; op2val:0xaf0; + valaddr_reg:x1; val_offset:1518*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1518*FLEN/8, x2, x8, x12) +RVTEST_SIGBASE(x8,signature_x8_6) + +inst_792: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x09d and fs2 == 0 and fe2 == 0x02 and fm2 == 0x2f0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x349d; op2val:0xaf0; + valaddr_reg:x1; val_offset:1520*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1520*FLEN/8, x2, x8, x12) + +inst_793: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x09d and fs2 == 0 and fe2 == 0x02 and fm2 == 0x2f0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x349d; op2val:0xaf0; + valaddr_reg:x1; val_offset:1522*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1522*FLEN/8, x2, x8, x12) + +inst_794: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x09d and fs2 == 0 and fe2 == 0x02 and fm2 == 0x2f0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x349d; op2val:0xaf0; + valaddr_reg:x1; val_offset:1524*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1524*FLEN/8, x2, x8, x12) + +inst_795: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x199 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x1b8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3599; op2val:0x9b8; + valaddr_reg:x1; val_offset:1526*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1526*FLEN/8, x2, x8, x12) + +inst_796: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x199 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x1b8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3599; op2val:0x9b8; + valaddr_reg:x1; val_offset:1528*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1528*FLEN/8, x2, x8, x12) + +inst_797: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x199 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x1b8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3599; op2val:0x9b8; + valaddr_reg:x1; val_offset:1530*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1530*FLEN/8, x2, x8, x12) + +inst_798: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x199 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x1b8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3599; op2val:0x9b8; + valaddr_reg:x1; val_offset:1532*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1532*FLEN/8, x2, x8, x12) + +inst_799: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x199 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x1b8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3599; op2val:0x9b8; + valaddr_reg:x1; val_offset:1534*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1534*FLEN/8, x2, x8, x12) + +inst_800: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3dc and fs2 == 0 and fe2 == 0x01 and fm2 == 0x013 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bdc; op2val:0x413; + valaddr_reg:x1; val_offset:1536*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1536*FLEN/8, x2, x8, x12) + +inst_801: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3dc and fs2 == 0 and fe2 == 0x01 and fm2 == 0x013 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bdc; op2val:0x413; + valaddr_reg:x1; val_offset:1538*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1538*FLEN/8, x2, x8, x12) + +inst_802: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3dc and fs2 == 0 and fe2 == 0x01 and fm2 == 0x013 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bdc; op2val:0x413; + valaddr_reg:x1; val_offset:1540*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1540*FLEN/8, x2, x8, x12) + +inst_803: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3dc and fs2 == 0 and fe2 == 0x01 and fm2 == 0x013 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bdc; op2val:0x413; + valaddr_reg:x1; val_offset:1542*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1542*FLEN/8, x2, x8, x12) + +inst_804: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3dc and fs2 == 0 and fe2 == 0x01 and fm2 == 0x013 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bdc; op2val:0x413; + valaddr_reg:x1; val_offset:1544*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1544*FLEN/8, x2, x8, x12) + +inst_805: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x054 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x366 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3454; op2val:0xb66; + valaddr_reg:x1; val_offset:1546*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1546*FLEN/8, x2, x8, x12) + +inst_806: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x054 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x366 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3454; op2val:0xb66; + valaddr_reg:x1; val_offset:1548*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1548*FLEN/8, x2, x8, x12) + +inst_807: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x054 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x366 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3454; op2val:0xb66; + valaddr_reg:x1; val_offset:1550*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1550*FLEN/8, x2, x8, x12) + +inst_808: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x054 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x366 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3454; op2val:0xb66; + valaddr_reg:x1; val_offset:1552*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1552*FLEN/8, x2, x8, x12) + +inst_809: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x054 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x366 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3454; op2val:0xb66; + valaddr_reg:x1; val_offset:1554*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1554*FLEN/8, x2, x8, x12) + +inst_810: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x210 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x148 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e10; op2val:0x1148; + valaddr_reg:x1; val_offset:1556*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1556*FLEN/8, x2, x8, x12) + +inst_811: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x210 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x148 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e10; op2val:0x1148; + valaddr_reg:x1; val_offset:1558*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1558*FLEN/8, x2, x8, x12) + +inst_812: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x210 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x148 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e10; op2val:0x1148; + valaddr_reg:x1; val_offset:1560*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1560*FLEN/8, x2, x8, x12) + +inst_813: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x210 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x148 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e10; op2val:0x1148; + valaddr_reg:x1; val_offset:1562*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1562*FLEN/8, x2, x8, x12) + +inst_814: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x210 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x148 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e10; op2val:0x1148; + valaddr_reg:x1; val_offset:1564*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1564*FLEN/8, x2, x8, x12) + +inst_815: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x332 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x073 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b32; op2val:0x473; + valaddr_reg:x1; val_offset:1566*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1566*FLEN/8, x2, x8, x12) + +inst_816: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x332 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x073 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b32; op2val:0x473; + valaddr_reg:x1; val_offset:1568*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1568*FLEN/8, x2, x8, x12) + +inst_817: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x332 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x073 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b32; op2val:0x473; + valaddr_reg:x1; val_offset:1570*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1570*FLEN/8, x2, x8, x12) + +inst_818: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x332 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x073 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b32; op2val:0x473; + valaddr_reg:x1; val_offset:1572*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1572*FLEN/8, x2, x8, x12) + +inst_819: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x332 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x073 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b32; op2val:0x473; + valaddr_reg:x1; val_offset:1574*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1574*FLEN/8, x2, x8, x12) + +inst_820: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x375 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3375; op2val:0xc4b; + valaddr_reg:x1; val_offset:1576*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1576*FLEN/8, x2, x8, x12) + +inst_821: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x375 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3375; op2val:0xc4b; + valaddr_reg:x1; val_offset:1578*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1578*FLEN/8, x2, x8, x12) + +inst_822: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x375 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3375; op2val:0xc4b; + valaddr_reg:x1; val_offset:1580*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1580*FLEN/8, x2, x8, x12) + +inst_823: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x375 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3375; op2val:0xc4b; + valaddr_reg:x1; val_offset:1582*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1582*FLEN/8, x2, x8, x12) + +inst_824: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x375 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x04b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3375; op2val:0xc4b; + valaddr_reg:x1; val_offset:1584*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1584*FLEN/8, x2, x8, x12) + +inst_825: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x017 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3d3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3417; op2val:0xbd3; + valaddr_reg:x1; val_offset:1586*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1586*FLEN/8, x2, x8, x12) + +inst_826: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x017 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3d3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3417; op2val:0xbd3; + valaddr_reg:x1; val_offset:1588*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1588*FLEN/8, x2, x8, x12) + +inst_827: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x017 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3d3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3417; op2val:0xbd3; + valaddr_reg:x1; val_offset:1590*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1590*FLEN/8, x2, x8, x12) + +inst_828: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x017 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3d3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3417; op2val:0xbd3; + valaddr_reg:x1; val_offset:1592*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1592*FLEN/8, x2, x8, x12) + +inst_829: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x017 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3d3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3417; op2val:0xbd3; + valaddr_reg:x1; val_offset:1594*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1594*FLEN/8, x2, x8, x12) + +inst_830: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x277 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0f4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a77; op2val:0x4f4; + valaddr_reg:x1; val_offset:1596*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1596*FLEN/8, x2, x8, x12) + +inst_831: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x277 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0f4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a77; op2val:0x4f4; + valaddr_reg:x1; val_offset:1598*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1598*FLEN/8, x2, x8, x12) + +inst_832: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x277 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0f4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a77; op2val:0x4f4; + valaddr_reg:x1; val_offset:1600*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1600*FLEN/8, x2, x8, x12) + +inst_833: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x277 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0f4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a77; op2val:0x4f4; + valaddr_reg:x1; val_offset:1602*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1602*FLEN/8, x2, x8, x12) + +inst_834: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x277 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0f4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a77; op2val:0x4f4; + valaddr_reg:x1; val_offset:1604*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1604*FLEN/8, x2, x8, x12) + +inst_835: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2e5 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x106 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ae5; op2val:0x506; + valaddr_reg:x1; val_offset:1606*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1606*FLEN/8, x2, x8, x12) + +inst_836: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2e5 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x106 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ae5; op2val:0x506; + valaddr_reg:x1; val_offset:1608*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1608*FLEN/8, x2, x8, x12) + +inst_837: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2e5 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x106 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ae5; op2val:0x506; + valaddr_reg:x1; val_offset:1610*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1610*FLEN/8, x2, x8, x12) + +inst_838: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2e5 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x106 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ae5; op2val:0x506; + valaddr_reg:x1; val_offset:1612*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1612*FLEN/8, x2, x8, x12) + +inst_839: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2e5 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x106 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ae5; op2val:0x506; + valaddr_reg:x1; val_offset:1614*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1614*FLEN/8, x2, x8, x12) + +inst_840: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x086 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3a8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3886; op2val:0x7a8; + valaddr_reg:x1; val_offset:1616*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1616*FLEN/8, x2, x8, x12) + +inst_841: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x086 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3a8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3886; op2val:0x7a8; + valaddr_reg:x1; val_offset:1618*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1618*FLEN/8, x2, x8, x12) + +inst_842: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x086 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3a8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3886; op2val:0x7a8; + valaddr_reg:x1; val_offset:1620*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1620*FLEN/8, x2, x8, x12) + +inst_843: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x086 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3a8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3886; op2val:0x7a8; + valaddr_reg:x1; val_offset:1622*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1622*FLEN/8, x2, x8, x12) + +inst_844: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x086 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3a8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3886; op2val:0x7a8; + valaddr_reg:x1; val_offset:1624*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1624*FLEN/8, x2, x8, x12) + +inst_845: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2f1 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x0fd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x36f1; op2val:0x8fd; + valaddr_reg:x1; val_offset:1626*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1626*FLEN/8, x2, x8, x12) + +inst_846: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2f1 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x0fd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x36f1; op2val:0x8fd; + valaddr_reg:x1; val_offset:1628*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1628*FLEN/8, x2, x8, x12) + +inst_847: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2f1 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x0fd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x36f1; op2val:0x8fd; + valaddr_reg:x1; val_offset:1630*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1630*FLEN/8, x2, x8, x12) + +inst_848: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2f1 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x0fd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x36f1; op2val:0x8fd; + valaddr_reg:x1; val_offset:1632*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1632*FLEN/8, x2, x8, x12) + +inst_849: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2f1 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x0fd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x36f1; op2val:0x8fd; + valaddr_reg:x1; val_offset:1634*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1634*FLEN/8, x2, x8, x12) + +inst_850: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x25c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x173 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a5c; op2val:0x573; + valaddr_reg:x1; val_offset:1636*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1636*FLEN/8, x2, x8, x12) + +inst_851: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x25c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x173 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a5c; op2val:0x573; + valaddr_reg:x1; val_offset:1638*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1638*FLEN/8, x2, x8, x12) + +inst_852: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x25c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x173 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a5c; op2val:0x573; + valaddr_reg:x1; val_offset:1640*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1640*FLEN/8, x2, x8, x12) + +inst_853: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x25c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x173 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a5c; op2val:0x573; + valaddr_reg:x1; val_offset:1642*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1642*FLEN/8, x2, x8, x12) + +inst_854: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x25c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x173 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a5c; op2val:0x573; + valaddr_reg:x1; val_offset:1644*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1644*FLEN/8, x2, x8, x12) + +inst_855: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0ac and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b6a; op2val:0x4ac; + valaddr_reg:x1; val_offset:1646*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1646*FLEN/8, x2, x8, x12) + +inst_856: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0ac and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b6a; op2val:0x4ac; + valaddr_reg:x1; val_offset:1648*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1648*FLEN/8, x2, x8, x12) + +inst_857: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0ac and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b6a; op2val:0x4ac; + valaddr_reg:x1; val_offset:1650*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1650*FLEN/8, x2, x8, x12) + +inst_858: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0ac and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b6a; op2val:0x4ac; + valaddr_reg:x1; val_offset:1652*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1652*FLEN/8, x2, x8, x12) + +inst_859: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0ac and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b6a; op2val:0x4ac; + valaddr_reg:x1; val_offset:1654*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1654*FLEN/8, x2, x8, x12) + +inst_860: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x01d and fs2 == 0 and fe2 == 0x02 and fm2 == 0x035 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x381d; op2val:0x835; + valaddr_reg:x1; val_offset:1656*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1656*FLEN/8, x2, x8, x12) + +inst_861: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x01d and fs2 == 0 and fe2 == 0x02 and fm2 == 0x035 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x381d; op2val:0x835; + valaddr_reg:x1; val_offset:1658*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1658*FLEN/8, x2, x8, x12) + +inst_862: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x01d and fs2 == 0 and fe2 == 0x02 and fm2 == 0x035 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x381d; op2val:0x835; + valaddr_reg:x1; val_offset:1660*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1660*FLEN/8, x2, x8, x12) + +inst_863: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x01d and fs2 == 0 and fe2 == 0x02 and fm2 == 0x035 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x381d; op2val:0x835; + valaddr_reg:x1; val_offset:1662*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1662*FLEN/8, x2, x8, x12) + +inst_864: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x01d and fs2 == 0 and fe2 == 0x02 and fm2 == 0x035 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x381d; op2val:0x835; + valaddr_reg:x1; val_offset:1664*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1664*FLEN/8, x2, x8, x12) + +inst_865: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x177 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x257 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3577; op2val:0xa57; + valaddr_reg:x1; val_offset:1666*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1666*FLEN/8, x2, x8, x12) + +inst_866: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x177 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x257 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3577; op2val:0xa57; + valaddr_reg:x1; val_offset:1668*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1668*FLEN/8, x2, x8, x12) + +inst_867: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x177 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x257 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3577; op2val:0xa57; + valaddr_reg:x1; val_offset:1670*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1670*FLEN/8, x2, x8, x12) + +inst_868: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x177 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x257 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3577; op2val:0xa57; + valaddr_reg:x1; val_offset:1672*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1672*FLEN/8, x2, x8, x12) + +inst_869: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x177 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x257 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3577; op2val:0xa57; + valaddr_reg:x1; val_offset:1674*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1674*FLEN/8, x2, x8, x12) + +inst_870: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x01e and fs2 == 0 and fe2 == 0x02 and fm2 == 0x034 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x381e; op2val:0x834; + valaddr_reg:x1; val_offset:1676*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1676*FLEN/8, x2, x8, x12) + +inst_871: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x01e and fs2 == 0 and fe2 == 0x02 and fm2 == 0x034 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x381e; op2val:0x834; + valaddr_reg:x1; val_offset:1678*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1678*FLEN/8, x2, x8, x12) + +inst_872: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x01e and fs2 == 0 and fe2 == 0x02 and fm2 == 0x034 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x381e; op2val:0x834; + valaddr_reg:x1; val_offset:1680*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1680*FLEN/8, x2, x8, x12) + +inst_873: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x01e and fs2 == 0 and fe2 == 0x02 and fm2 == 0x034 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x381e; op2val:0x834; + valaddr_reg:x1; val_offset:1682*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1682*FLEN/8, x2, x8, x12) + +inst_874: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x01e and fs2 == 0 and fe2 == 0x02 and fm2 == 0x034 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x381e; op2val:0x834; + valaddr_reg:x1; val_offset:1684*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1684*FLEN/8, x2, x8, x12) + +inst_875: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x152 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x283 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3952; op2val:0x683; + valaddr_reg:x1; val_offset:1686*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1686*FLEN/8, x2, x8, x12) + +inst_876: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x152 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x283 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3952; op2val:0x683; + valaddr_reg:x1; val_offset:1688*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1688*FLEN/8, x2, x8, x12) + +inst_877: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x152 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x283 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3952; op2val:0x683; + valaddr_reg:x1; val_offset:1690*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1690*FLEN/8, x2, x8, x12) + +inst_878: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x152 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x283 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3952; op2val:0x683; + valaddr_reg:x1; val_offset:1692*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1692*FLEN/8, x2, x8, x12) + +inst_879: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x152 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x283 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3952; op2val:0x683; + valaddr_reg:x1; val_offset:1694*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1694*FLEN/8, x2, x8, x12) + +inst_880: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3f4 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x05b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x37f4; op2val:0x85b; + valaddr_reg:x1; val_offset:1696*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1696*FLEN/8, x2, x8, x12) + +inst_881: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3f4 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x05b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x37f4; op2val:0x85b; + valaddr_reg:x1; val_offset:1698*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1698*FLEN/8, x2, x8, x12) + +inst_882: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3f4 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x05b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x37f4; op2val:0x85b; + valaddr_reg:x1; val_offset:1700*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1700*FLEN/8, x2, x8, x12) + +inst_883: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3f4 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x05b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x37f4; op2val:0x85b; + valaddr_reg:x1; val_offset:1702*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1702*FLEN/8, x2, x8, x12) + +inst_884: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3f4 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x05b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x37f4; op2val:0x85b; + valaddr_reg:x1; val_offset:1704*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1704*FLEN/8, x2, x8, x12) + +inst_885: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x35c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0b5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b5c; op2val:0x4b5; + valaddr_reg:x1; val_offset:1706*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1706*FLEN/8, x2, x8, x12) + +inst_886: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x35c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0b5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b5c; op2val:0x4b5; + valaddr_reg:x1; val_offset:1708*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1708*FLEN/8, x2, x8, x12) + +inst_887: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x35c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0b5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b5c; op2val:0x4b5; + valaddr_reg:x1; val_offset:1710*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1710*FLEN/8, x2, x8, x12) + +inst_888: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x35c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0b5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b5c; op2val:0x4b5; + valaddr_reg:x1; val_offset:1712*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1712*FLEN/8, x2, x8, x12) + +inst_889: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x35c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0b5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b5c; op2val:0x4b5; + valaddr_reg:x1; val_offset:1714*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1714*FLEN/8, x2, x8, x12) + +inst_890: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x29c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x13e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a9c; op2val:0x53e; + valaddr_reg:x1; val_offset:1716*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1716*FLEN/8, x2, x8, x12) + +inst_891: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x29c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x13e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a9c; op2val:0x53e; + valaddr_reg:x1; val_offset:1718*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1718*FLEN/8, x2, x8, x12) + +inst_892: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x29c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x13e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a9c; op2val:0x53e; + valaddr_reg:x1; val_offset:1720*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1720*FLEN/8, x2, x8, x12) + +inst_893: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x29c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x13e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a9c; op2val:0x53e; + valaddr_reg:x1; val_offset:1722*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1722*FLEN/8, x2, x8, x12) + +inst_894: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x29c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x13e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a9c; op2val:0x53e; + valaddr_reg:x1; val_offset:1724*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1724*FLEN/8, x2, x8, x12) + +inst_895: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2e6 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x105 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x32e6; op2val:0xd05; + valaddr_reg:x1; val_offset:1726*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1726*FLEN/8, x2, x8, x12) + +inst_896: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2e6 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x105 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x32e6; op2val:0xd05; + valaddr_reg:x1; val_offset:1728*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1728*FLEN/8, x2, x8, x12) + +inst_897: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2e6 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x105 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x32e6; op2val:0xd05; + valaddr_reg:x1; val_offset:1730*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1730*FLEN/8, x2, x8, x12) + +inst_898: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2e6 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x105 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x32e6; op2val:0xd05; + valaddr_reg:x1; val_offset:1732*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1732*FLEN/8, x2, x8, x12) + +inst_899: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2e6 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x105 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x32e6; op2val:0xd05; + valaddr_reg:x1; val_offset:1734*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1734*FLEN/8, x2, x8, x12) + +inst_900: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x133 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x2aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3533; op2val:0xaaa; + valaddr_reg:x1; val_offset:1736*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1736*FLEN/8, x2, x8, x12) + +inst_901: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x133 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x2aa and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3533; op2val:0xaaa; + valaddr_reg:x1; val_offset:1738*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1738*FLEN/8, x2, x8, x12) + +inst_902: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x133 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x2aa and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3533; op2val:0xaaa; + valaddr_reg:x1; val_offset:1740*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1740*FLEN/8, x2, x8, x12) + +inst_903: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x133 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x2aa and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3533; op2val:0xaaa; + valaddr_reg:x1; val_offset:1742*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1742*FLEN/8, x2, x8, x12) + +inst_904: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x133 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x2aa and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3533; op2val:0xaaa; + valaddr_reg:x1; val_offset:1744*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1744*FLEN/8, x2, x8, x12) + +inst_905: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x05a and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3f6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x305a; op2val:0xff6; + valaddr_reg:x1; val_offset:1746*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1746*FLEN/8, x2, x8, x12) + +inst_906: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x05a and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3f6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x305a; op2val:0xff6; + valaddr_reg:x1; val_offset:1748*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1748*FLEN/8, x2, x8, x12) + +inst_907: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x05a and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3f6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x305a; op2val:0xff6; + valaddr_reg:x1; val_offset:1750*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1750*FLEN/8, x2, x8, x12) + +inst_908: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x05a and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3f6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x305a; op2val:0xff6; + valaddr_reg:x1; val_offset:1752*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1752*FLEN/8, x2, x8, x12) + +inst_909: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x05a and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3f6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x305a; op2val:0xff6; + valaddr_reg:x1; val_offset:1754*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1754*FLEN/8, x2, x8, x12) + +inst_910: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b3 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ab3; op2val:0x52c; + valaddr_reg:x1; val_offset:1756*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1756*FLEN/8, x2, x8, x12) + +inst_911: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b3 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ab3; op2val:0x52c; + valaddr_reg:x1; val_offset:1758*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1758*FLEN/8, x2, x8, x12) + +inst_912: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b3 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ab3; op2val:0x52c; + valaddr_reg:x1; val_offset:1760*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1760*FLEN/8, x2, x8, x12) + +inst_913: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b3 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ab3; op2val:0x52c; + valaddr_reg:x1; val_offset:1762*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1762*FLEN/8, x2, x8, x12) + +inst_914: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b3 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ab3; op2val:0x52c; + valaddr_reg:x1; val_offset:1764*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1764*FLEN/8, x2, x8, x12) + +inst_915: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x048 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x00b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3848; op2val:0x80b; + valaddr_reg:x1; val_offset:1766*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1766*FLEN/8, x2, x8, x12) + +inst_916: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x048 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x00b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3848; op2val:0x80b; + valaddr_reg:x1; val_offset:1768*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1768*FLEN/8, x2, x8, x12) + +inst_917: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x048 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x00b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3848; op2val:0x80b; + valaddr_reg:x1; val_offset:1770*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1770*FLEN/8, x2, x8, x12) + +inst_918: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x048 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x00b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3848; op2val:0x80b; + valaddr_reg:x1; val_offset:1772*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1772*FLEN/8, x2, x8, x12) + +inst_919: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x048 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x00b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3848; op2val:0x80b; + valaddr_reg:x1; val_offset:1774*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1774*FLEN/8, x2, x8, x12) +RVTEST_SIGBASE(x8,signature_x8_7) + +inst_920: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ea and fs2 == 0 and fe2 == 0x01 and fm2 == 0x060 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bea; op2val:0x460; + valaddr_reg:x1; val_offset:1776*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1776*FLEN/8, x2, x8, x12) + +inst_921: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ea and fs2 == 0 and fe2 == 0x01 and fm2 == 0x060 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bea; op2val:0x460; + valaddr_reg:x1; val_offset:1778*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1778*FLEN/8, x2, x8, x12) + +inst_922: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ea and fs2 == 0 and fe2 == 0x01 and fm2 == 0x060 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bea; op2val:0x460; + valaddr_reg:x1; val_offset:1780*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1780*FLEN/8, x2, x8, x12) + +inst_923: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ea and fs2 == 0 and fe2 == 0x01 and fm2 == 0x060 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bea; op2val:0x460; + valaddr_reg:x1; val_offset:1782*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1782*FLEN/8, x2, x8, x12) + +inst_924: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ea and fs2 == 0 and fe2 == 0x01 and fm2 == 0x060 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bea; op2val:0x460; + valaddr_reg:x1; val_offset:1784*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1784*FLEN/8, x2, x8, x12) + +inst_925: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x03e and fs2 == 0 and fe2 == 0x06 and fm2 == 0x015 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x283e; op2val:0x1815; + valaddr_reg:x1; val_offset:1786*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1786*FLEN/8, x2, x8, x12) + +inst_926: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x03e and fs2 == 0 and fe2 == 0x06 and fm2 == 0x015 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x283e; op2val:0x1815; + valaddr_reg:x1; val_offset:1788*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1788*FLEN/8, x2, x8, x12) + +inst_927: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x03e and fs2 == 0 and fe2 == 0x06 and fm2 == 0x015 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x283e; op2val:0x1815; + valaddr_reg:x1; val_offset:1790*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1790*FLEN/8, x2, x8, x12) + +inst_928: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x03e and fs2 == 0 and fe2 == 0x06 and fm2 == 0x015 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x283e; op2val:0x1815; + valaddr_reg:x1; val_offset:1792*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1792*FLEN/8, x2, x8, x12) + +inst_929: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x03e and fs2 == 0 and fe2 == 0x06 and fm2 == 0x015 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x283e; op2val:0x1815; + valaddr_reg:x1; val_offset:1794*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1794*FLEN/8, x2, x8, x12) + +inst_930: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x364 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x0b0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3764; op2val:0x8b0; + valaddr_reg:x1; val_offset:1796*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1796*FLEN/8, x2, x8, x12) + +inst_931: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x364 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x0b0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3764; op2val:0x8b0; + valaddr_reg:x1; val_offset:1798*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1798*FLEN/8, x2, x8, x12) + +inst_932: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x364 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x0b0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3764; op2val:0x8b0; + valaddr_reg:x1; val_offset:1800*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1800*FLEN/8, x2, x8, x12) + +inst_933: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x364 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x0b0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3764; op2val:0x8b0; + valaddr_reg:x1; val_offset:1802*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1802*FLEN/8, x2, x8, x12) + +inst_934: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x364 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x0b0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3764; op2val:0x8b0; + valaddr_reg:x1; val_offset:1804*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1804*FLEN/8, x2, x8, x12) + +inst_935: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x075 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3c6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3875; op2val:0x7c6; + valaddr_reg:x1; val_offset:1806*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1806*FLEN/8, x2, x8, x12) + +inst_936: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x075 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3c6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3875; op2val:0x7c6; + valaddr_reg:x1; val_offset:1808*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1808*FLEN/8, x2, x8, x12) + +inst_937: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x075 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3c6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3875; op2val:0x7c6; + valaddr_reg:x1; val_offset:1810*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1810*FLEN/8, x2, x8, x12) + +inst_938: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x075 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3c6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3875; op2val:0x7c6; + valaddr_reg:x1; val_offset:1812*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1812*FLEN/8, x2, x8, x12) + +inst_939: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x075 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3c6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3875; op2val:0x7c6; + valaddr_reg:x1; val_offset:1814*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1814*FLEN/8, x2, x8, x12) + +inst_940: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x188 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x243 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3988; op2val:0x643; + valaddr_reg:x1; val_offset:1816*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1816*FLEN/8, x2, x8, x12) + +inst_941: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x188 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x243 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3988; op2val:0x643; + valaddr_reg:x1; val_offset:1818*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1818*FLEN/8, x2, x8, x12) + +inst_942: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x188 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x243 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3988; op2val:0x643; + valaddr_reg:x1; val_offset:1820*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1820*FLEN/8, x2, x8, x12) + +inst_943: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x188 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x243 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3988; op2val:0x643; + valaddr_reg:x1; val_offset:1822*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1822*FLEN/8, x2, x8, x12) + +inst_944: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x188 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x243 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3988; op2val:0x643; + valaddr_reg:x1; val_offset:1824*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1824*FLEN/8, x2, x8, x12) + +inst_945: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x021 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x032 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3821; op2val:0x832; + valaddr_reg:x1; val_offset:1826*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1826*FLEN/8, x2, x8, x12) + +inst_946: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x021 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x032 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3821; op2val:0x832; + valaddr_reg:x1; val_offset:1828*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1828*FLEN/8, x2, x8, x12) + +inst_947: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x021 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x032 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3821; op2val:0x832; + valaddr_reg:x1; val_offset:1830*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1830*FLEN/8, x2, x8, x12) + +inst_948: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x021 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x032 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3821; op2val:0x832; + valaddr_reg:x1; val_offset:1832*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1832*FLEN/8, x2, x8, x12) + +inst_949: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x021 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x032 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3821; op2val:0x832; + valaddr_reg:x1; val_offset:1834*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1834*FLEN/8, x2, x8, x12) + +inst_950: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x176 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x258 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d76; op2val:0x1258; + valaddr_reg:x1; val_offset:1836*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1836*FLEN/8, x2, x8, x12) + +inst_951: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x176 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x258 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d76; op2val:0x1258; + valaddr_reg:x1; val_offset:1838*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1838*FLEN/8, x2, x8, x12) + +inst_952: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x176 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x258 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d76; op2val:0x1258; + valaddr_reg:x1; val_offset:1840*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1840*FLEN/8, x2, x8, x12) + +inst_953: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x176 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x258 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d76; op2val:0x1258; + valaddr_reg:x1; val_offset:1842*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1842*FLEN/8, x2, x8, x12) + +inst_954: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x176 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x258 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d76; op2val:0x1258; + valaddr_reg:x1; val_offset:1844*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1844*FLEN/8, x2, x8, x12) + +inst_955: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x19f and fs2 == 0 and fe2 == 0x03 and fm2 == 0x22a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x319f; op2val:0xe2a; + valaddr_reg:x1; val_offset:1846*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1846*FLEN/8, x2, x8, x12) + +inst_956: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x19f and fs2 == 0 and fe2 == 0x03 and fm2 == 0x22a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x319f; op2val:0xe2a; + valaddr_reg:x1; val_offset:1848*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1848*FLEN/8, x2, x8, x12) + +inst_957: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x19f and fs2 == 0 and fe2 == 0x03 and fm2 == 0x22a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x319f; op2val:0xe2a; + valaddr_reg:x1; val_offset:1850*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1850*FLEN/8, x2, x8, x12) + +inst_958: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x19f and fs2 == 0 and fe2 == 0x03 and fm2 == 0x22a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x319f; op2val:0xe2a; + valaddr_reg:x1; val_offset:1852*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1852*FLEN/8, x2, x8, x12) + +inst_959: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x19f and fs2 == 0 and fe2 == 0x03 and fm2 == 0x22a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x319f; op2val:0xe2a; + valaddr_reg:x1; val_offset:1854*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1854*FLEN/8, x2, x8, x12) + +inst_960: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a8 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x21f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x35a8; op2val:0xa1f; + valaddr_reg:x1; val_offset:1856*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1856*FLEN/8, x2, x8, x12) + +inst_961: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a8 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x21f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x35a8; op2val:0xa1f; + valaddr_reg:x1; val_offset:1858*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1858*FLEN/8, x2, x8, x12) + +inst_962: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a8 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x21f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x35a8; op2val:0xa1f; + valaddr_reg:x1; val_offset:1860*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1860*FLEN/8, x2, x8, x12) + +inst_963: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a8 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x21f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x35a8; op2val:0xa1f; + valaddr_reg:x1; val_offset:1862*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1862*FLEN/8, x2, x8, x12) + +inst_964: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a8 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x21f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x35a8; op2val:0xa1f; + valaddr_reg:x1; val_offset:1864*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1864*FLEN/8, x2, x8, x12) + +inst_965: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x18b and fs2 == 0 and fe2 == 0x02 and fm2 == 0x23f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x358b; op2val:0xa3f; + valaddr_reg:x1; val_offset:1866*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1866*FLEN/8, x2, x8, x12) + +inst_966: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x18b and fs2 == 0 and fe2 == 0x02 and fm2 == 0x23f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x358b; op2val:0xa3f; + valaddr_reg:x1; val_offset:1868*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1868*FLEN/8, x2, x8, x12) + +inst_967: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x18b and fs2 == 0 and fe2 == 0x02 and fm2 == 0x23f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x358b; op2val:0xa3f; + valaddr_reg:x1; val_offset:1870*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1870*FLEN/8, x2, x8, x12) + +inst_968: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x18b and fs2 == 0 and fe2 == 0x02 and fm2 == 0x23f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x358b; op2val:0xa3f; + valaddr_reg:x1; val_offset:1872*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1872*FLEN/8, x2, x8, x12) + +inst_969: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x18b and fs2 == 0 and fe2 == 0x02 and fm2 == 0x23f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x358b; op2val:0xa3f; + valaddr_reg:x1; val_offset:1874*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1874*FLEN/8, x2, x8, x12) + +inst_970: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x119 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x2cc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3119; op2val:0xecc; + valaddr_reg:x1; val_offset:1876*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1876*FLEN/8, x2, x8, x12) + +inst_971: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x119 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x2cc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3119; op2val:0xecc; + valaddr_reg:x1; val_offset:1878*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1878*FLEN/8, x2, x8, x12) + +inst_972: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x119 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x2cc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3119; op2val:0xecc; + valaddr_reg:x1; val_offset:1880*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1880*FLEN/8, x2, x8, x12) + +inst_973: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x119 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x2cc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3119; op2val:0xecc; + valaddr_reg:x1; val_offset:1882*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1882*FLEN/8, x2, x8, x12) + +inst_974: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x119 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x2cc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3119; op2val:0xecc; + valaddr_reg:x1; val_offset:1884*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1884*FLEN/8, x2, x8, x12) + +inst_975: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1de and fs2 == 0 and fe2 == 0x02 and fm2 == 0x1e8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x35de; op2val:0x9e8; + valaddr_reg:x1; val_offset:1886*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1886*FLEN/8, x2, x8, x12) + +inst_976: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1de and fs2 == 0 and fe2 == 0x02 and fm2 == 0x1e8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x35de; op2val:0x9e8; + valaddr_reg:x1; val_offset:1888*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1888*FLEN/8, x2, x8, x12) + +inst_977: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1de and fs2 == 0 and fe2 == 0x02 and fm2 == 0x1e8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x35de; op2val:0x9e8; + valaddr_reg:x1; val_offset:1890*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1890*FLEN/8, x2, x8, x12) + +inst_978: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1de and fs2 == 0 and fe2 == 0x02 and fm2 == 0x1e8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x35de; op2val:0x9e8; + valaddr_reg:x1; val_offset:1892*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1892*FLEN/8, x2, x8, x12) + +inst_979: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1de and fs2 == 0 and fe2 == 0x02 and fm2 == 0x1e8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x35de; op2val:0x9e8; + valaddr_reg:x1; val_offset:1894*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1894*FLEN/8, x2, x8, x12) + +inst_980: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x383 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x09c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3783; op2val:0x89c; + valaddr_reg:x1; val_offset:1896*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1896*FLEN/8, x2, x8, x12) + +inst_981: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x383 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x09c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3783; op2val:0x89c; + valaddr_reg:x1; val_offset:1898*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1898*FLEN/8, x2, x8, x12) + +inst_982: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x383 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x09c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3783; op2val:0x89c; + valaddr_reg:x1; val_offset:1900*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1900*FLEN/8, x2, x8, x12) + +inst_983: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x383 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x09c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3783; op2val:0x89c; + valaddr_reg:x1; val_offset:1902*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1902*FLEN/8, x2, x8, x12) + +inst_984: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x383 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x09c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3783; op2val:0x89c; + valaddr_reg:x1; val_offset:1904*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1904*FLEN/8, x2, x8, x12) + +inst_985: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x278 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x15b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3278; op2val:0xd5b; + valaddr_reg:x1; val_offset:1906*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1906*FLEN/8, x2, x8, x12) + +inst_986: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x278 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x15b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3278; op2val:0xd5b; + valaddr_reg:x1; val_offset:1908*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1908*FLEN/8, x2, x8, x12) + +inst_987: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x278 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x15b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3278; op2val:0xd5b; + valaddr_reg:x1; val_offset:1910*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1910*FLEN/8, x2, x8, x12) + +inst_988: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x278 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x15b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3278; op2val:0xd5b; + valaddr_reg:x1; val_offset:1912*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1912*FLEN/8, x2, x8, x12) + +inst_989: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x278 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x15b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3278; op2val:0xd5b; + valaddr_reg:x1; val_offset:1914*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1914*FLEN/8, x2, x8, x12) + +inst_990: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x189 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x242 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3989; op2val:0x642; + valaddr_reg:x1; val_offset:1916*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1916*FLEN/8, x2, x8, x12) + +inst_991: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x189 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x242 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3989; op2val:0x642; + valaddr_reg:x1; val_offset:1918*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1918*FLEN/8, x2, x8, x12) + +inst_992: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x189 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x242 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3989; op2val:0x642; + valaddr_reg:x1; val_offset:1920*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1920*FLEN/8, x2, x8, x12) + +inst_993: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x189 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x242 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3989; op2val:0x642; + valaddr_reg:x1; val_offset:1922*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1922*FLEN/8, x2, x8, x12) + +inst_994: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x189 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x242 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3989; op2val:0x642; + valaddr_reg:x1; val_offset:1924*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1924*FLEN/8, x2, x8, x12) + +inst_995: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x057 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3857; op2val:0x7fc; + valaddr_reg:x1; val_offset:1926*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1926*FLEN/8, x2, x8, x12) + +inst_996: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x057 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3fc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3857; op2val:0x7fc; + valaddr_reg:x1; val_offset:1928*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1928*FLEN/8, x2, x8, x12) + +inst_997: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x057 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3fc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3857; op2val:0x7fc; + valaddr_reg:x1; val_offset:1930*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1930*FLEN/8, x2, x8, x12) + +inst_998: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x057 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3fc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3857; op2val:0x7fc; + valaddr_reg:x1; val_offset:1932*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1932*FLEN/8, x2, x8, x12) + +inst_999: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x057 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3fc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3857; op2val:0x7fc; + valaddr_reg:x1; val_offset:1934*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1934*FLEN/8, x2, x8, x12) + +inst_1000: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x39c7; op2val:0x5ff; + valaddr_reg:x1; val_offset:1936*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1936*FLEN/8, x2, x8, x12) + +inst_1001: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x39c7; op2val:0x5ff; + valaddr_reg:x1; val_offset:1938*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1938*FLEN/8, x2, x8, x12) + +inst_1002: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x39c7; op2val:0x5ff; + valaddr_reg:x1; val_offset:1940*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1940*FLEN/8, x2, x8, x12) + +inst_1003: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x39c7; op2val:0x5ff; + valaddr_reg:x1; val_offset:1942*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1942*FLEN/8, x2, x8, x12) + +inst_1004: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x39c7; op2val:0x5ff; + valaddr_reg:x1; val_offset:1944*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1944*FLEN/8, x2, x8, x12) + +inst_1005: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b1a; op2val:0x4e0; + valaddr_reg:x1; val_offset:1946*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1946*FLEN/8, x2, x8, x12) + +inst_1006: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0e0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b1a; op2val:0x4e0; + valaddr_reg:x1; val_offset:1948*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1948*FLEN/8, x2, x8, x12) + +inst_1007: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0e0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b1a; op2val:0x4e0; + valaddr_reg:x1; val_offset:1950*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1950*FLEN/8, x2, x8, x12) + +inst_1008: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0e0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b1a; op2val:0x4e0; + valaddr_reg:x1; val_offset:1952*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1952*FLEN/8, x2, x8, x12) + +inst_1009: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0e0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b1a; op2val:0x4e0; + valaddr_reg:x1; val_offset:1954*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1954*FLEN/8, x2, x8, x12) + +inst_1010: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0f7 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x2fa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x38f7; op2val:0x6fa; + valaddr_reg:x1; val_offset:1956*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1956*FLEN/8, x2, x8, x12) + +inst_1011: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0f7 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x2fa and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x38f7; op2val:0x6fa; + valaddr_reg:x1; val_offset:1958*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1958*FLEN/8, x2, x8, x12) + +inst_1012: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0f7 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x2fa and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x38f7; op2val:0x6fa; + valaddr_reg:x1; val_offset:1960*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1960*FLEN/8, x2, x8, x12) + +inst_1013: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0f7 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x2fa and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x38f7; op2val:0x6fa; + valaddr_reg:x1; val_offset:1962*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1962*FLEN/8, x2, x8, x12) + +inst_1014: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0f7 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x2fa and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x38f7; op2val:0x6fa; + valaddr_reg:x1; val_offset:1964*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1964*FLEN/8, x2, x8, x12) + +inst_1015: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x173 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x25b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3973; op2val:0x65b; + valaddr_reg:x1; val_offset:1966*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1966*FLEN/8, x2, x8, x12) + +inst_1016: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x173 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x25b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3973; op2val:0x65b; + valaddr_reg:x1; val_offset:1968*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1968*FLEN/8, x2, x8, x12) + +inst_1017: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x173 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x25b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3973; op2val:0x65b; + valaddr_reg:x1; val_offset:1970*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1970*FLEN/8, x2, x8, x12) + +inst_1018: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x173 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x25b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3973; op2val:0x65b; + valaddr_reg:x1; val_offset:1972*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1972*FLEN/8, x2, x8, x12) + +inst_1019: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x173 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x25b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3973; op2val:0x65b; + valaddr_reg:x1; val_offset:1974*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1974*FLEN/8, x2, x8, x12) + +inst_1020: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x076 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3c3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3876; op2val:0x7c3; + valaddr_reg:x1; val_offset:1976*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1976*FLEN/8, x2, x8, x12) + +inst_1021: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x076 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3c3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3876; op2val:0x7c3; + valaddr_reg:x1; val_offset:1978*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1978*FLEN/8, x2, x8, x12) + +inst_1022: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x076 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3c3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3876; op2val:0x7c3; + valaddr_reg:x1; val_offset:1980*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1980*FLEN/8, x2, x8, x12) + +inst_1023: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x076 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3c3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3876; op2val:0x7c3; + valaddr_reg:x1; val_offset:1982*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1982*FLEN/8, x2, x8, x12) + +inst_1024: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x076 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3c3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3876; op2val:0x7c3; + valaddr_reg:x1; val_offset:1984*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1984*FLEN/8, x2, x8, x12) + +inst_1025: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x122 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ec0; op2val:0x1122; + valaddr_reg:x1; val_offset:1986*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1986*FLEN/8, x2, x8, x12) + +inst_1026: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x122 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ec0; op2val:0x1122; + valaddr_reg:x1; val_offset:1988*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1988*FLEN/8, x2, x8, x12) + +inst_1027: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x122 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ec0; op2val:0x1122; + valaddr_reg:x1; val_offset:1990*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 1990*FLEN/8, x2, x8, x12) + +inst_1028: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x122 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ec0; op2val:0x1122; + valaddr_reg:x1; val_offset:1992*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 1992*FLEN/8, x2, x8, x12) + +inst_1029: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x122 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ec0; op2val:0x1122; + valaddr_reg:x1; val_offset:1994*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 1994*FLEN/8, x2, x8, x12) + +inst_1030: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x081 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x3b1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2c81; op2val:0x13b1; + valaddr_reg:x1; val_offset:1996*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 1996*FLEN/8, x2, x8, x12) + +inst_1031: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x081 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x3b1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2c81; op2val:0x13b1; + valaddr_reg:x1; val_offset:1998*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 1998*FLEN/8, x2, x8, x12) + +inst_1032: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x081 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x3b1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2c81; op2val:0x13b1; + valaddr_reg:x1; val_offset:2000*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2000*FLEN/8, x2, x8, x12) + +inst_1033: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x081 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x3b1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2c81; op2val:0x13b1; + valaddr_reg:x1; val_offset:2002*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2002*FLEN/8, x2, x8, x12) + +inst_1034: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x081 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x3b1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2c81; op2val:0x13b1; + valaddr_reg:x1; val_offset:2004*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2004*FLEN/8, x2, x8, x12) + +inst_1035: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x334 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b34; op2val:0x52e; + valaddr_reg:x1; val_offset:2006*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2006*FLEN/8, x2, x8, x12) + +inst_1036: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x334 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b34; op2val:0x52e; + valaddr_reg:x1; val_offset:2008*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2008*FLEN/8, x2, x8, x12) + +inst_1037: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x334 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b34; op2val:0x52e; + valaddr_reg:x1; val_offset:2010*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2010*FLEN/8, x2, x8, x12) + +inst_1038: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x334 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b34; op2val:0x52e; + valaddr_reg:x1; val_offset:2012*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2012*FLEN/8, x2, x8, x12) + +inst_1039: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x334 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b34; op2val:0x52e; + valaddr_reg:x1; val_offset:2014*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2014*FLEN/8, x2, x8, x12) + +inst_1040: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x27b and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1c1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a7b; op2val:0x5c1; + valaddr_reg:x1; val_offset:2016*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2016*FLEN/8, x2, x8, x12) + +inst_1041: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x27b and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1c1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a7b; op2val:0x5c1; + valaddr_reg:x1; val_offset:2018*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2018*FLEN/8, x2, x8, x12) + +inst_1042: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x27b and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1c1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a7b; op2val:0x5c1; + valaddr_reg:x1; val_offset:2020*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2020*FLEN/8, x2, x8, x12) + +inst_1043: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x27b and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1c1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a7b; op2val:0x5c1; + valaddr_reg:x1; val_offset:2022*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2022*FLEN/8, x2, x8, x12) + +inst_1044: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x27b and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1c1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a7b; op2val:0x5c1; + valaddr_reg:x1; val_offset:2024*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2024*FLEN/8, x2, x8, x12) + +inst_1045: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x102 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x372 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3902; op2val:0x772; + valaddr_reg:x1; val_offset:2026*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2026*FLEN/8, x2, x8, x12) + +inst_1046: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x102 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x372 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3902; op2val:0x772; + valaddr_reg:x1; val_offset:2028*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2028*FLEN/8, x2, x8, x12) + +inst_1047: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x102 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x372 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3902; op2val:0x772; + valaddr_reg:x1; val_offset:2030*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2030*FLEN/8, x2, x8, x12) +RVTEST_SIGBASE(x8,signature_x8_8) + +inst_1048: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x102 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x372 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3902; op2val:0x772; + valaddr_reg:x1; val_offset:2032*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2032*FLEN/8, x2, x8, x12) + +inst_1049: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x102 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x372 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3902; op2val:0x772; + valaddr_reg:x1; val_offset:2034*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2034*FLEN/8, x2, x8, x12) + +inst_1050: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x28f and fs2 == 0 and fe2 == 0x03 and fm2 == 0x1b0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x328f; op2val:0xdb0; + valaddr_reg:x1; val_offset:2036*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2036*FLEN/8, x2, x8, x12) + +inst_1051: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x28f and fs2 == 0 and fe2 == 0x03 and fm2 == 0x1b0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x328f; op2val:0xdb0; + valaddr_reg:x1; val_offset:2038*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2038*FLEN/8, x2, x8, x12) + +inst_1052: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x28f and fs2 == 0 and fe2 == 0x03 and fm2 == 0x1b0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x328f; op2val:0xdb0; + valaddr_reg:x1; val_offset:2040*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2040*FLEN/8, x2, x8, x12) + +inst_1053: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x28f and fs2 == 0 and fe2 == 0x03 and fm2 == 0x1b0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x328f; op2val:0xdb0; + valaddr_reg:x1; val_offset:2042*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2042*FLEN/8, x2, x8, x12) + +inst_1054: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x28f and fs2 == 0 and fe2 == 0x03 and fm2 == 0x1b0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x328f; op2val:0xdb0; + valaddr_reg:x1; val_offset:2044*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2044*FLEN/8, x2, x8, x12) + +inst_1055: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x220 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x216 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3220; op2val:0xe16; + valaddr_reg:x1; val_offset:2046*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2046*FLEN/8, x2, x8, x12) + +inst_1056: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x220 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x216 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3220; op2val:0xe16; + valaddr_reg:x1; val_offset:2048*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2048*FLEN/8, x2, x8, x12) + +inst_1057: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x220 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x216 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3220; op2val:0xe16; + valaddr_reg:x1; val_offset:2050*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2050*FLEN/8, x2, x8, x12) + +inst_1058: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x220 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x216 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3220; op2val:0xe16; + valaddr_reg:x1; val_offset:2052*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2052*FLEN/8, x2, x8, x12) + +inst_1059: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x220 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x216 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3220; op2val:0xe16; + valaddr_reg:x1; val_offset:2054*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2054*FLEN/8, x2, x8, x12) + +inst_1060: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0cc and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3c6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x38cc; op2val:0x7c6; + valaddr_reg:x1; val_offset:2056*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2056*FLEN/8, x2, x8, x12) + +inst_1061: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0cc and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3c6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x38cc; op2val:0x7c6; + valaddr_reg:x1; val_offset:2058*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2058*FLEN/8, x2, x8, x12) + +inst_1062: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0cc and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3c6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x38cc; op2val:0x7c6; + valaddr_reg:x1; val_offset:2060*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2060*FLEN/8, x2, x8, x12) + +inst_1063: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0cc and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3c6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x38cc; op2val:0x7c6; + valaddr_reg:x1; val_offset:2062*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2062*FLEN/8, x2, x8, x12) + +inst_1064: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0cc and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3c6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x38cc; op2val:0x7c6; + valaddr_reg:x1; val_offset:2064*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2064*FLEN/8, x2, x8, x12) + +inst_1065: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x143 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x317 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3943; op2val:0x717; + valaddr_reg:x1; val_offset:2066*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2066*FLEN/8, x2, x8, x12) + +inst_1066: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x143 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x317 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3943; op2val:0x717; + valaddr_reg:x1; val_offset:2068*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2068*FLEN/8, x2, x8, x12) + +inst_1067: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x143 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x317 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3943; op2val:0x717; + valaddr_reg:x1; val_offset:2070*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2070*FLEN/8, x2, x8, x12) + +inst_1068: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x143 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x317 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3943; op2val:0x717; + valaddr_reg:x1; val_offset:2072*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2072*FLEN/8, x2, x8, x12) + +inst_1069: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x143 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x317 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3943; op2val:0x717; + valaddr_reg:x1; val_offset:2074*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2074*FLEN/8, x2, x8, x12) + +inst_1070: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0be and fs2 == 0 and fe2 == 0x04 and fm2 == 0x3dd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2cbe; op2val:0x13dd; + valaddr_reg:x1; val_offset:2076*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2076*FLEN/8, x2, x8, x12) + +inst_1071: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0be and fs2 == 0 and fe2 == 0x04 and fm2 == 0x3dd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2cbe; op2val:0x13dd; + valaddr_reg:x1; val_offset:2078*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2078*FLEN/8, x2, x8, x12) + +inst_1072: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0be and fs2 == 0 and fe2 == 0x04 and fm2 == 0x3dd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2cbe; op2val:0x13dd; + valaddr_reg:x1; val_offset:2080*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2080*FLEN/8, x2, x8, x12) + +inst_1073: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0be and fs2 == 0 and fe2 == 0x04 and fm2 == 0x3dd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2cbe; op2val:0x13dd; + valaddr_reg:x1; val_offset:2082*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2082*FLEN/8, x2, x8, x12) + +inst_1074: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0be and fs2 == 0 and fe2 == 0x04 and fm2 == 0x3dd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2cbe; op2val:0x13dd; + valaddr_reg:x1; val_offset:2084*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2084*FLEN/8, x2, x8, x12) + +inst_1075: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0f6 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x385 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x34f6; op2val:0xb85; + valaddr_reg:x1; val_offset:2086*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2086*FLEN/8, x2, x8, x12) + +inst_1076: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0f6 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x385 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x34f6; op2val:0xb85; + valaddr_reg:x1; val_offset:2088*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2088*FLEN/8, x2, x8, x12) + +inst_1077: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0f6 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x385 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x34f6; op2val:0xb85; + valaddr_reg:x1; val_offset:2090*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2090*FLEN/8, x2, x8, x12) + +inst_1078: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0f6 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x385 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x34f6; op2val:0xb85; + valaddr_reg:x1; val_offset:2092*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2092*FLEN/8, x2, x8, x12) + +inst_1079: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0f6 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x385 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x34f6; op2val:0xb85; + valaddr_reg:x1; val_offset:2094*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2094*FLEN/8, x2, x8, x12) + +inst_1080: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x01e and fs2 == 0 and fe2 == 0x03 and fm2 == 0x087 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x341e; op2val:0xc87; + valaddr_reg:x1; val_offset:2096*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2096*FLEN/8, x2, x8, x12) + +inst_1081: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x01e and fs2 == 0 and fe2 == 0x03 and fm2 == 0x087 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x341e; op2val:0xc87; + valaddr_reg:x1; val_offset:2098*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2098*FLEN/8, x2, x8, x12) + +inst_1082: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x01e and fs2 == 0 and fe2 == 0x03 and fm2 == 0x087 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x341e; op2val:0xc87; + valaddr_reg:x1; val_offset:2100*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2100*FLEN/8, x2, x8, x12) + +inst_1083: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x01e and fs2 == 0 and fe2 == 0x03 and fm2 == 0x087 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x341e; op2val:0xc87; + valaddr_reg:x1; val_offset:2102*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2102*FLEN/8, x2, x8, x12) + +inst_1084: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x01e and fs2 == 0 and fe2 == 0x03 and fm2 == 0x087 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x341e; op2val:0xc87; + valaddr_reg:x1; val_offset:2104*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2104*FLEN/8, x2, x8, x12) + +inst_1085: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x02f and fs2 == 0 and fe2 == 0x04 and fm2 == 0x075 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x302f; op2val:0x1075; + valaddr_reg:x1; val_offset:2106*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2106*FLEN/8, x2, x8, x12) + +inst_1086: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x02f and fs2 == 0 and fe2 == 0x04 and fm2 == 0x075 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x302f; op2val:0x1075; + valaddr_reg:x1; val_offset:2108*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2108*FLEN/8, x2, x8, x12) + +inst_1087: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x02f and fs2 == 0 and fe2 == 0x04 and fm2 == 0x075 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x302f; op2val:0x1075; + valaddr_reg:x1; val_offset:2110*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2110*FLEN/8, x2, x8, x12) + +inst_1088: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x02f and fs2 == 0 and fe2 == 0x04 and fm2 == 0x075 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x302f; op2val:0x1075; + valaddr_reg:x1; val_offset:2112*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2112*FLEN/8, x2, x8, x12) + +inst_1089: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x02f and fs2 == 0 and fe2 == 0x04 and fm2 == 0x075 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x302f; op2val:0x1075; + valaddr_reg:x1; val_offset:2114*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2114*FLEN/8, x2, x8, x12) + +inst_1090: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3e3 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x0bb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x33e3; op2val:0xcbb; + valaddr_reg:x1; val_offset:2116*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2116*FLEN/8, x2, x8, x12) + +inst_1091: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3e3 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x0bb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x33e3; op2val:0xcbb; + valaddr_reg:x1; val_offset:2118*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2118*FLEN/8, x2, x8, x12) + +inst_1092: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3e3 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x0bb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x33e3; op2val:0xcbb; + valaddr_reg:x1; val_offset:2120*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2120*FLEN/8, x2, x8, x12) + +inst_1093: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3e3 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x0bb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x33e3; op2val:0xcbb; + valaddr_reg:x1; val_offset:2122*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2122*FLEN/8, x2, x8, x12) + +inst_1094: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3e3 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x0bb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x33e3; op2val:0xcbb; + valaddr_reg:x1; val_offset:2124*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2124*FLEN/8, x2, x8, x12) + +inst_1095: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1aa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x295 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x39aa; op2val:0x695; + valaddr_reg:x1; val_offset:2126*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2126*FLEN/8, x2, x8, x12) + +inst_1096: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1aa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x295 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x39aa; op2val:0x695; + valaddr_reg:x1; val_offset:2128*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2128*FLEN/8, x2, x8, x12) + +inst_1097: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1aa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x295 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x39aa; op2val:0x695; + valaddr_reg:x1; val_offset:2130*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2130*FLEN/8, x2, x8, x12) + +inst_1098: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1aa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x295 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x39aa; op2val:0x695; + valaddr_reg:x1; val_offset:2132*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2132*FLEN/8, x2, x8, x12) + +inst_1099: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1aa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x295 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x39aa; op2val:0x695; + valaddr_reg:x1; val_offset:2134*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2134*FLEN/8, x2, x8, x12) + +inst_1100: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x145 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x314 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3545; op2val:0xb14; + valaddr_reg:x1; val_offset:2136*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2136*FLEN/8, x2, x8, x12) + +inst_1101: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x145 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x314 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3545; op2val:0xb14; + valaddr_reg:x1; val_offset:2138*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2138*FLEN/8, x2, x8, x12) + +inst_1102: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x145 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x314 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3545; op2val:0xb14; + valaddr_reg:x1; val_offset:2140*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2140*FLEN/8, x2, x8, x12) + +inst_1103: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x145 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x314 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3545; op2val:0xb14; + valaddr_reg:x1; val_offset:2142*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2142*FLEN/8, x2, x8, x12) + +inst_1104: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x145 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x314 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3545; op2val:0xb14; + valaddr_reg:x1; val_offset:2144*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2144*FLEN/8, x2, x8, x12) + +inst_1105: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3b6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x38d6; op2val:0x7b6; + valaddr_reg:x1; val_offset:2146*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2146*FLEN/8, x2, x8, x12) + +inst_1106: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3b6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x38d6; op2val:0x7b6; + valaddr_reg:x1; val_offset:2148*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2148*FLEN/8, x2, x8, x12) + +inst_1107: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3b6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x38d6; op2val:0x7b6; + valaddr_reg:x1; val_offset:2150*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2150*FLEN/8, x2, x8, x12) + +inst_1108: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3b6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x38d6; op2val:0x7b6; + valaddr_reg:x1; val_offset:2152*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2152*FLEN/8, x2, x8, x12) + +inst_1109: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3b6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x38d6; op2val:0x7b6; + valaddr_reg:x1; val_offset:2154*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2154*FLEN/8, x2, x8, x12) + +inst_1110: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x16b and fs2 == 0 and fe2 == 0x05 and fm2 == 0x2e1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x296b; op2val:0x16e1; + valaddr_reg:x1; val_offset:2156*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2156*FLEN/8, x2, x8, x12) + +inst_1111: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x16b and fs2 == 0 and fe2 == 0x05 and fm2 == 0x2e1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x296b; op2val:0x16e1; + valaddr_reg:x1; val_offset:2158*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2158*FLEN/8, x2, x8, x12) + +inst_1112: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x16b and fs2 == 0 and fe2 == 0x05 and fm2 == 0x2e1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x296b; op2val:0x16e1; + valaddr_reg:x1; val_offset:2160*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2160*FLEN/8, x2, x8, x12) + +inst_1113: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x16b and fs2 == 0 and fe2 == 0x05 and fm2 == 0x2e1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x296b; op2val:0x16e1; + valaddr_reg:x1; val_offset:2162*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2162*FLEN/8, x2, x8, x12) + +inst_1114: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x16b and fs2 == 0 and fe2 == 0x05 and fm2 == 0x2e1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x296b; op2val:0x16e1; + valaddr_reg:x1; val_offset:2164*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2164*FLEN/8, x2, x8, x12) + +inst_1115: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02f and fs2 == 0 and fe2 == 0x02 and fm2 == 0x074 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x382f; op2val:0x874; + valaddr_reg:x1; val_offset:2166*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2166*FLEN/8, x2, x8, x12) + +inst_1116: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02f and fs2 == 0 and fe2 == 0x02 and fm2 == 0x074 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x382f; op2val:0x874; + valaddr_reg:x1; val_offset:2168*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2168*FLEN/8, x2, x8, x12) + +inst_1117: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02f and fs2 == 0 and fe2 == 0x02 and fm2 == 0x074 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x382f; op2val:0x874; + valaddr_reg:x1; val_offset:2170*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2170*FLEN/8, x2, x8, x12) + +inst_1118: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02f and fs2 == 0 and fe2 == 0x02 and fm2 == 0x074 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x382f; op2val:0x874; + valaddr_reg:x1; val_offset:2172*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2172*FLEN/8, x2, x8, x12) + +inst_1119: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02f and fs2 == 0 and fe2 == 0x02 and fm2 == 0x074 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x382f; op2val:0x874; + valaddr_reg:x1; val_offset:2174*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2174*FLEN/8, x2, x8, x12) + +inst_1120: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x282 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1bb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a82; op2val:0x5bb; + valaddr_reg:x1; val_offset:2176*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2176*FLEN/8, x2, x8, x12) + +inst_1121: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x282 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1bb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a82; op2val:0x5bb; + valaddr_reg:x1; val_offset:2178*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2178*FLEN/8, x2, x8, x12) + +inst_1122: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x282 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1bb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a82; op2val:0x5bb; + valaddr_reg:x1; val_offset:2180*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2180*FLEN/8, x2, x8, x12) + +inst_1123: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x282 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1bb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a82; op2val:0x5bb; + valaddr_reg:x1; val_offset:2182*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2182*FLEN/8, x2, x8, x12) + +inst_1124: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x282 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1bb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a82; op2val:0x5bb; + valaddr_reg:x1; val_offset:2184*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2184*FLEN/8, x2, x8, x12) + +inst_1125: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fb and fs2 == 0 and fe2 == 0x01 and fm2 == 0x157 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3afb; op2val:0x557; + valaddr_reg:x1; val_offset:2186*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2186*FLEN/8, x2, x8, x12) + +inst_1126: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fb and fs2 == 0 and fe2 == 0x01 and fm2 == 0x157 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3afb; op2val:0x557; + valaddr_reg:x1; val_offset:2188*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2188*FLEN/8, x2, x8, x12) + +inst_1127: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fb and fs2 == 0 and fe2 == 0x01 and fm2 == 0x157 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3afb; op2val:0x557; + valaddr_reg:x1; val_offset:2190*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2190*FLEN/8, x2, x8, x12) + +inst_1128: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fb and fs2 == 0 and fe2 == 0x01 and fm2 == 0x157 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3afb; op2val:0x557; + valaddr_reg:x1; val_offset:2192*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2192*FLEN/8, x2, x8, x12) + +inst_1129: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fb and fs2 == 0 and fe2 == 0x01 and fm2 == 0x157 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3afb; op2val:0x557; + valaddr_reg:x1; val_offset:2194*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2194*FLEN/8, x2, x8, x12) + +inst_1130: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x131 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x32f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3931; op2val:0x72f; + valaddr_reg:x1; val_offset:2196*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2196*FLEN/8, x2, x8, x12) + +inst_1131: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x131 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x32f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3931; op2val:0x72f; + valaddr_reg:x1; val_offset:2198*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2198*FLEN/8, x2, x8, x12) + +inst_1132: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x131 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x32f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3931; op2val:0x72f; + valaddr_reg:x1; val_offset:2200*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2200*FLEN/8, x2, x8, x12) + +inst_1133: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x131 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x32f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3931; op2val:0x72f; + valaddr_reg:x1; val_offset:2202*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2202*FLEN/8, x2, x8, x12) + +inst_1134: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x131 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x32f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3931; op2val:0x72f; + valaddr_reg:x1; val_offset:2204*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2204*FLEN/8, x2, x8, x12) + +inst_1135: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x146 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x313 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d46; op2val:0x1313; + valaddr_reg:x1; val_offset:2206*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2206*FLEN/8, x2, x8, x12) + +inst_1136: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x146 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x313 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d46; op2val:0x1313; + valaddr_reg:x1; val_offset:2208*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2208*FLEN/8, x2, x8, x12) + +inst_1137: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x146 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x313 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d46; op2val:0x1313; + valaddr_reg:x1; val_offset:2210*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2210*FLEN/8, x2, x8, x12) + +inst_1138: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x146 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x313 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d46; op2val:0x1313; + valaddr_reg:x1; val_offset:2212*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2212*FLEN/8, x2, x8, x12) + +inst_1139: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x146 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x313 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d46; op2val:0x1313; + valaddr_reg:x1; val_offset:2214*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2214*FLEN/8, x2, x8, x12) + +inst_1140: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x0e3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x33a1; op2val:0xce3; + valaddr_reg:x1; val_offset:2216*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2216*FLEN/8, x2, x8, x12) + +inst_1141: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x0e3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x33a1; op2val:0xce3; + valaddr_reg:x1; val_offset:2218*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2218*FLEN/8, x2, x8, x12) + +inst_1142: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x0e3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x33a1; op2val:0xce3; + valaddr_reg:x1; val_offset:2220*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2220*FLEN/8, x2, x8, x12) + +inst_1143: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x0e3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x33a1; op2val:0xce3; + valaddr_reg:x1; val_offset:2222*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2222*FLEN/8, x2, x8, x12) + +inst_1144: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x0e3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x33a1; op2val:0xce3; + valaddr_reg:x1; val_offset:2224*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2224*FLEN/8, x2, x8, x12) + +inst_1145: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x351 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x119 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3751; op2val:0x919; + valaddr_reg:x1; val_offset:2226*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2226*FLEN/8, x2, x8, x12) + +inst_1146: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x351 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x119 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3751; op2val:0x919; + valaddr_reg:x1; val_offset:2228*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2228*FLEN/8, x2, x8, x12) + +inst_1147: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x351 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x119 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3751; op2val:0x919; + valaddr_reg:x1; val_offset:2230*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2230*FLEN/8, x2, x8, x12) + +inst_1148: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x351 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x119 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3751; op2val:0x919; + valaddr_reg:x1; val_offset:2232*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2232*FLEN/8, x2, x8, x12) + +inst_1149: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x351 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x119 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3751; op2val:0x919; + valaddr_reg:x1; val_offset:2234*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2234*FLEN/8, x2, x8, x12) + +inst_1150: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x154 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3154; op2val:0xf00; + valaddr_reg:x1; val_offset:2236*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2236*FLEN/8, x2, x8, x12) + +inst_1151: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x154 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x300 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3154; op2val:0xf00; + valaddr_reg:x1; val_offset:2238*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2238*FLEN/8, x2, x8, x12) + +inst_1152: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x154 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x300 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3154; op2val:0xf00; + valaddr_reg:x1; val_offset:2240*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2240*FLEN/8, x2, x8, x12) + +inst_1153: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x154 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x300 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3154; op2val:0xf00; + valaddr_reg:x1; val_offset:2242*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2242*FLEN/8, x2, x8, x12) + +inst_1154: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x154 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x300 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3154; op2val:0xf00; + valaddr_reg:x1; val_offset:2244*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2244*FLEN/8, x2, x8, x12) + +inst_1155: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1b9 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x285 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x39b9; op2val:0x685; + valaddr_reg:x1; val_offset:2246*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2246*FLEN/8, x2, x8, x12) + +inst_1156: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1b9 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x285 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x39b9; op2val:0x685; + valaddr_reg:x1; val_offset:2248*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2248*FLEN/8, x2, x8, x12) + +inst_1157: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1b9 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x285 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x39b9; op2val:0x685; + valaddr_reg:x1; val_offset:2250*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2250*FLEN/8, x2, x8, x12) + +inst_1158: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1b9 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x285 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x39b9; op2val:0x685; + valaddr_reg:x1; val_offset:2252*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2252*FLEN/8, x2, x8, x12) + +inst_1159: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1b9 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x285 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x39b9; op2val:0x685; + valaddr_reg:x1; val_offset:2254*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2254*FLEN/8, x2, x8, x12) + +inst_1160: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2cb and fs2 == 0 and fe2 == 0x01 and fm2 == 0x17d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3acb; op2val:0x57d; + valaddr_reg:x1; val_offset:2256*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2256*FLEN/8, x2, x8, x12) + +inst_1161: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2cb and fs2 == 0 and fe2 == 0x01 and fm2 == 0x17d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3acb; op2val:0x57d; + valaddr_reg:x1; val_offset:2258*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2258*FLEN/8, x2, x8, x12) + +inst_1162: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2cb and fs2 == 0 and fe2 == 0x01 and fm2 == 0x17d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3acb; op2val:0x57d; + valaddr_reg:x1; val_offset:2260*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2260*FLEN/8, x2, x8, x12) + +inst_1163: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2cb and fs2 == 0 and fe2 == 0x01 and fm2 == 0x17d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3acb; op2val:0x57d; + valaddr_reg:x1; val_offset:2262*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2262*FLEN/8, x2, x8, x12) + +inst_1164: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2cb and fs2 == 0 and fe2 == 0x01 and fm2 == 0x17d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3acb; op2val:0x57d; + valaddr_reg:x1; val_offset:2264*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2264*FLEN/8, x2, x8, x12) + +inst_1165: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0ba and fs2 == 0 and fe2 == 0x04 and fm2 == 0x3e4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2cba; op2val:0x13e4; + valaddr_reg:x1; val_offset:2266*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2266*FLEN/8, x2, x8, x12) + +inst_1166: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0ba and fs2 == 0 and fe2 == 0x04 and fm2 == 0x3e4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2cba; op2val:0x13e4; + valaddr_reg:x1; val_offset:2268*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2268*FLEN/8, x2, x8, x12) + +inst_1167: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0ba and fs2 == 0 and fe2 == 0x04 and fm2 == 0x3e4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2cba; op2val:0x13e4; + valaddr_reg:x1; val_offset:2270*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2270*FLEN/8, x2, x8, x12) + +inst_1168: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0ba and fs2 == 0 and fe2 == 0x04 and fm2 == 0x3e4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2cba; op2val:0x13e4; + valaddr_reg:x1; val_offset:2272*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2272*FLEN/8, x2, x8, x12) + +inst_1169: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0ba and fs2 == 0 and fe2 == 0x04 and fm2 == 0x3e4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2cba; op2val:0x13e4; + valaddr_reg:x1; val_offset:2274*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2274*FLEN/8, x2, x8, x12) + +inst_1170: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2dc and fs2 == 0 and fe2 == 0x01 and fm2 == 0x170 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3adc; op2val:0x570; + valaddr_reg:x1; val_offset:2276*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2276*FLEN/8, x2, x8, x12) + +inst_1171: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2dc and fs2 == 0 and fe2 == 0x01 and fm2 == 0x170 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3adc; op2val:0x570; + valaddr_reg:x1; val_offset:2278*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2278*FLEN/8, x2, x8, x12) + +inst_1172: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2dc and fs2 == 0 and fe2 == 0x01 and fm2 == 0x170 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3adc; op2val:0x570; + valaddr_reg:x1; val_offset:2280*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2280*FLEN/8, x2, x8, x12) + +inst_1173: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2dc and fs2 == 0 and fe2 == 0x01 and fm2 == 0x170 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3adc; op2val:0x570; + valaddr_reg:x1; val_offset:2282*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2282*FLEN/8, x2, x8, x12) + +inst_1174: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2dc and fs2 == 0 and fe2 == 0x01 and fm2 == 0x170 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3adc; op2val:0x570; + valaddr_reg:x1; val_offset:2284*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2284*FLEN/8, x2, x8, x12) + +inst_1175: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x23a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x39fe; op2val:0x63a; + valaddr_reg:x1; val_offset:2286*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2286*FLEN/8, x2, x8, x12) +RVTEST_SIGBASE(x8,signature_x8_9) + +inst_1176: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x23a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x39fe; op2val:0x63a; + valaddr_reg:x1; val_offset:2288*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2288*FLEN/8, x2, x8, x12) + +inst_1177: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x23a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x39fe; op2val:0x63a; + valaddr_reg:x1; val_offset:2290*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2290*FLEN/8, x2, x8, x12) + +inst_1178: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x23a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x39fe; op2val:0x63a; + valaddr_reg:x1; val_offset:2292*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2292*FLEN/8, x2, x8, x12) + +inst_1179: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x23a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x39fe; op2val:0x63a; + valaddr_reg:x1; val_offset:2294*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2294*FLEN/8, x2, x8, x12) + +inst_1180: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x238 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x39ff; op2val:0x638; + valaddr_reg:x1; val_offset:2296*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2296*FLEN/8, x2, x8, x12) + +inst_1181: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x238 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x39ff; op2val:0x638; + valaddr_reg:x1; val_offset:2298*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2298*FLEN/8, x2, x8, x12) + +inst_1182: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x238 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x39ff; op2val:0x638; + valaddr_reg:x1; val_offset:2300*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2300*FLEN/8, x2, x8, x12) + +inst_1183: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x238 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x39ff; op2val:0x638; + valaddr_reg:x1; val_offset:2302*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2302*FLEN/8, x2, x8, x12) + +inst_1184: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x238 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x39ff; op2val:0x638; + valaddr_reg:x1; val_offset:2304*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2304*FLEN/8, x2, x8, x12) + +inst_1185: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x207 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x230 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a07; op2val:0x630; + valaddr_reg:x1; val_offset:2306*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2306*FLEN/8, x2, x8, x12) + +inst_1186: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x207 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x230 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a07; op2val:0x630; + valaddr_reg:x1; val_offset:2308*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2308*FLEN/8, x2, x8, x12) + +inst_1187: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x207 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x230 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a07; op2val:0x630; + valaddr_reg:x1; val_offset:2310*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2310*FLEN/8, x2, x8, x12) + +inst_1188: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x207 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x230 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a07; op2val:0x630; + valaddr_reg:x1; val_offset:2312*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2312*FLEN/8, x2, x8, x12) + +inst_1189: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x207 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x230 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a07; op2val:0x630; + valaddr_reg:x1; val_offset:2314*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2314*FLEN/8, x2, x8, x12) + +inst_1190: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x23b and fs2 == 0 and fe2 == 0x02 and fm2 == 0x1fd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x363b; op2val:0x9fd; + valaddr_reg:x1; val_offset:2316*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2316*FLEN/8, x2, x8, x12) + +inst_1191: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x23b and fs2 == 0 and fe2 == 0x02 and fm2 == 0x1fd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x363b; op2val:0x9fd; + valaddr_reg:x1; val_offset:2318*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2318*FLEN/8, x2, x8, x12) + +inst_1192: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x23b and fs2 == 0 and fe2 == 0x02 and fm2 == 0x1fd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x363b; op2val:0x9fd; + valaddr_reg:x1; val_offset:2320*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2320*FLEN/8, x2, x8, x12) + +inst_1193: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x23b and fs2 == 0 and fe2 == 0x02 and fm2 == 0x1fd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x363b; op2val:0x9fd; + valaddr_reg:x1; val_offset:2322*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2322*FLEN/8, x2, x8, x12) + +inst_1194: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x23b and fs2 == 0 and fe2 == 0x02 and fm2 == 0x1fd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x363b; op2val:0x9fd; + valaddr_reg:x1; val_offset:2324*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2324*FLEN/8, x2, x8, x12) + +inst_1195: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x104 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x36f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3904; op2val:0x76f; + valaddr_reg:x1; val_offset:2326*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2326*FLEN/8, x2, x8, x12) + +inst_1196: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x104 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x36f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3904; op2val:0x76f; + valaddr_reg:x1; val_offset:2328*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2328*FLEN/8, x2, x8, x12) + +inst_1197: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x104 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x36f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3904; op2val:0x76f; + valaddr_reg:x1; val_offset:2330*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2330*FLEN/8, x2, x8, x12) + +inst_1198: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x104 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x36f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3904; op2val:0x76f; + valaddr_reg:x1; val_offset:2332*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2332*FLEN/8, x2, x8, x12) + +inst_1199: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x104 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x36f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3904; op2val:0x76f; + valaddr_reg:x1; val_offset:2334*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2334*FLEN/8, x2, x8, x12) + +inst_1200: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x381 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b81; op2val:0x4f8; + valaddr_reg:x1; val_offset:2336*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2336*FLEN/8, x2, x8, x12) + +inst_1201: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x381 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0f8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b81; op2val:0x4f8; + valaddr_reg:x1; val_offset:2338*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2338*FLEN/8, x2, x8, x12) + +inst_1202: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x381 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0f8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b81; op2val:0x4f8; + valaddr_reg:x1; val_offset:2340*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2340*FLEN/8, x2, x8, x12) + +inst_1203: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x381 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0f8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b81; op2val:0x4f8; + valaddr_reg:x1; val_offset:2342*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2342*FLEN/8, x2, x8, x12) + +inst_1204: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x381 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0f8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b81; op2val:0x4f8; + valaddr_reg:x1; val_offset:2344*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2344*FLEN/8, x2, x8, x12) + +inst_1205: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0c6 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3d0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x30c6; op2val:0xfd0; + valaddr_reg:x1; val_offset:2346*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2346*FLEN/8, x2, x8, x12) + +inst_1206: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0c6 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3d0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x30c6; op2val:0xfd0; + valaddr_reg:x1; val_offset:2348*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2348*FLEN/8, x2, x8, x12) + +inst_1207: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0c6 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3d0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x30c6; op2val:0xfd0; + valaddr_reg:x1; val_offset:2350*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2350*FLEN/8, x2, x8, x12) + +inst_1208: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0c6 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3d0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x30c6; op2val:0xfd0; + valaddr_reg:x1; val_offset:2352*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2352*FLEN/8, x2, x8, x12) + +inst_1209: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0c6 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3d0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x30c6; op2val:0xfd0; + valaddr_reg:x1; val_offset:2354*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2354*FLEN/8, x2, x8, x12) + +inst_1210: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x314 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x145 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3314; op2val:0xd45; + valaddr_reg:x1; val_offset:2356*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2356*FLEN/8, x2, x8, x12) + +inst_1211: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x314 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x145 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3314; op2val:0xd45; + valaddr_reg:x1; val_offset:2358*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2358*FLEN/8, x2, x8, x12) + +inst_1212: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x314 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x145 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3314; op2val:0xd45; + valaddr_reg:x1; val_offset:2360*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2360*FLEN/8, x2, x8, x12) + +inst_1213: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x314 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x145 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3314; op2val:0xd45; + valaddr_reg:x1; val_offset:2362*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2362*FLEN/8, x2, x8, x12) + +inst_1214: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x314 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x145 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3314; op2val:0xd45; + valaddr_reg:x1; val_offset:2364*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2364*FLEN/8, x2, x8, x12) + +inst_1215: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x0e3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x37a1; op2val:0x8e3; + valaddr_reg:x1; val_offset:2366*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2366*FLEN/8, x2, x8, x12) + +inst_1216: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x0e3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x37a1; op2val:0x8e3; + valaddr_reg:x1; val_offset:2368*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2368*FLEN/8, x2, x8, x12) + +inst_1217: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x0e3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x37a1; op2val:0x8e3; + valaddr_reg:x1; val_offset:2370*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2370*FLEN/8, x2, x8, x12) + +inst_1218: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x0e3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x37a1; op2val:0x8e3; + valaddr_reg:x1; val_offset:2372*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2372*FLEN/8, x2, x8, x12) + +inst_1219: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x0e3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x37a1; op2val:0x8e3; + valaddr_reg:x1; val_offset:2374*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2374*FLEN/8, x2, x8, x12) + +inst_1220: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x14b and fs2 == 0 and fe2 == 0x01 and fm2 == 0x30b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x394b; op2val:0x70b; + valaddr_reg:x1; val_offset:2376*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2376*FLEN/8, x2, x8, x12) + +inst_1221: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x14b and fs2 == 0 and fe2 == 0x01 and fm2 == 0x30b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x394b; op2val:0x70b; + valaddr_reg:x1; val_offset:2378*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2378*FLEN/8, x2, x8, x12) + +inst_1222: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x14b and fs2 == 0 and fe2 == 0x01 and fm2 == 0x30b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x394b; op2val:0x70b; + valaddr_reg:x1; val_offset:2380*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2380*FLEN/8, x2, x8, x12) + +inst_1223: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x14b and fs2 == 0 and fe2 == 0x01 and fm2 == 0x30b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x394b; op2val:0x70b; + valaddr_reg:x1; val_offset:2382*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2382*FLEN/8, x2, x8, x12) + +inst_1224: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x14b and fs2 == 0 and fe2 == 0x01 and fm2 == 0x30b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x394b; op2val:0x70b; + valaddr_reg:x1; val_offset:2384*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2384*FLEN/8, x2, x8, x12) + +inst_1225: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x23c and fs2 == 0 and fe2 == 0x02 and fm2 == 0x1fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x363c; op2val:0x9fc; + valaddr_reg:x1; val_offset:2386*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2386*FLEN/8, x2, x8, x12) + +inst_1226: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x23c and fs2 == 0 and fe2 == 0x02 and fm2 == 0x1fc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x363c; op2val:0x9fc; + valaddr_reg:x1; val_offset:2388*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2388*FLEN/8, x2, x8, x12) + +inst_1227: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x23c and fs2 == 0 and fe2 == 0x02 and fm2 == 0x1fc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x363c; op2val:0x9fc; + valaddr_reg:x1; val_offset:2390*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2390*FLEN/8, x2, x8, x12) + +inst_1228: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x23c and fs2 == 0 and fe2 == 0x02 and fm2 == 0x1fc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x363c; op2val:0x9fc; + valaddr_reg:x1; val_offset:2392*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2392*FLEN/8, x2, x8, x12) + +inst_1229: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x23c and fs2 == 0 and fe2 == 0x02 and fm2 == 0x1fc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x363c; op2val:0x9fc; + valaddr_reg:x1; val_offset:2394*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2394*FLEN/8, x2, x8, x12) + +inst_1230: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x191 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x2b3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x1991; op2val:0x26b3; + valaddr_reg:x1; val_offset:2396*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2396*FLEN/8, x2, x8, x12) + +inst_1231: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x191 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x2b3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x1991; op2val:0x26b3; + valaddr_reg:x1; val_offset:2398*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2398*FLEN/8, x2, x8, x12) + +inst_1232: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x191 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x2b3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x1991; op2val:0x26b3; + valaddr_reg:x1; val_offset:2400*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2400*FLEN/8, x2, x8, x12) + +inst_1233: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x191 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x2b3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x1991; op2val:0x26b3; + valaddr_reg:x1; val_offset:2402*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2402*FLEN/8, x2, x8, x12) + +inst_1234: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x191 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x2b3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x1991; op2val:0x26b3; + valaddr_reg:x1; val_offset:2404*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2404*FLEN/8, x2, x8, x12) + +inst_1235: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x035 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x06e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3835; op2val:0x86e; + valaddr_reg:x1; val_offset:2406*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2406*FLEN/8, x2, x8, x12) + +inst_1236: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x035 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x06e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3835; op2val:0x86e; + valaddr_reg:x1; val_offset:2408*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2408*FLEN/8, x2, x8, x12) + +inst_1237: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x035 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x06e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3835; op2val:0x86e; + valaddr_reg:x1; val_offset:2410*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2410*FLEN/8, x2, x8, x12) + +inst_1238: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x035 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x06e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3835; op2val:0x86e; + valaddr_reg:x1; val_offset:2412*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2412*FLEN/8, x2, x8, x12) + +inst_1239: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x035 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x06e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3835; op2val:0x86e; + valaddr_reg:x1; val_offset:2414*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2414*FLEN/8, x2, x8, x12) + +inst_1240: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x177 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x2d4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3977; op2val:0x6d4; + valaddr_reg:x1; val_offset:2416*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2416*FLEN/8, x2, x8, x12) + +inst_1241: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x177 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x2d4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3977; op2val:0x6d4; + valaddr_reg:x1; val_offset:2418*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2418*FLEN/8, x2, x8, x12) + +inst_1242: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x177 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x2d4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3977; op2val:0x6d4; + valaddr_reg:x1; val_offset:2420*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2420*FLEN/8, x2, x8, x12) + +inst_1243: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x177 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x2d4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3977; op2val:0x6d4; + valaddr_reg:x1; val_offset:2422*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2422*FLEN/8, x2, x8, x12) + +inst_1244: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x177 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x2d4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3977; op2val:0x6d4; + valaddr_reg:x1; val_offset:2424*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2424*FLEN/8, x2, x8, x12) + +inst_1245: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x0d4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x29f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x50d4; op2val:0x3e9f; + valaddr_reg:x1; val_offset:2426*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2426*FLEN/8, x2, x8, x12) + +inst_1246: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x0d4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x29f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x50d4; op2val:0x3e9f; + valaddr_reg:x1; val_offset:2428*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2428*FLEN/8, x2, x8, x12) + +inst_1247: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x0d4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x29f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x50d4; op2val:0x3e9f; + valaddr_reg:x1; val_offset:2430*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2430*FLEN/8, x2, x8, x12) + +inst_1248: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x0d4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x29f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x50d4; op2val:0x3e9f; + valaddr_reg:x1; val_offset:2432*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2432*FLEN/8, x2, x8, x12) + +inst_1249: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x0d4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x29f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x50d4; op2val:0x3e9f; + valaddr_reg:x1; val_offset:2434*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2434*FLEN/8, x2, x8, x12) + +inst_1250: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x05d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x354 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x505d; op2val:0x3f54; + valaddr_reg:x1; val_offset:2436*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2436*FLEN/8, x2, x8, x12) + +inst_1251: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x05d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x354 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x505d; op2val:0x3f54; + valaddr_reg:x1; val_offset:2438*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2438*FLEN/8, x2, x8, x12) + +inst_1252: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x05d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x354 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x505d; op2val:0x3f54; + valaddr_reg:x1; val_offset:2440*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2440*FLEN/8, x2, x8, x12) + +inst_1253: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x05d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x354 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x505d; op2val:0x3f54; + valaddr_reg:x1; val_offset:2442*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2442*FLEN/8, x2, x8, x12) + +inst_1254: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x05d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x354 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x505d; op2val:0x3f54; + valaddr_reg:x1; val_offset:2444*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2444*FLEN/8, x2, x8, x12) + +inst_1255: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3e9 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x00b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x53e9; op2val:0x3c0b; + valaddr_reg:x1; val_offset:2446*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2446*FLEN/8, x2, x8, x12) + +inst_1256: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3e9 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x00b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x53e9; op2val:0x3c0b; + valaddr_reg:x1; val_offset:2448*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2448*FLEN/8, x2, x8, x12) + +inst_1257: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3e9 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x00b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x53e9; op2val:0x3c0b; + valaddr_reg:x1; val_offset:2450*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2450*FLEN/8, x2, x8, x12) + +inst_1258: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3e9 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x00b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x53e9; op2val:0x3c0b; + valaddr_reg:x1; val_offset:2452*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2452*FLEN/8, x2, x8, x12) + +inst_1259: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3e9 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x00b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x53e9; op2val:0x3c0b; + valaddr_reg:x1; val_offset:2454*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2454*FLEN/8, x2, x8, x12) + +inst_1260: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x369 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x051 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x4f69; op2val:0x4051; + valaddr_reg:x1; val_offset:2456*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2456*FLEN/8, x2, x8, x12) + +inst_1261: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x369 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x051 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x4f69; op2val:0x4051; + valaddr_reg:x1; val_offset:2458*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2458*FLEN/8, x2, x8, x12) + +inst_1262: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x369 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x051 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x4f69; op2val:0x4051; + valaddr_reg:x1; val_offset:2460*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2460*FLEN/8, x2, x8, x12) + +inst_1263: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x369 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x051 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x4f69; op2val:0x4051; + valaddr_reg:x1; val_offset:2462*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2462*FLEN/8, x2, x8, x12) + +inst_1264: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x369 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x051 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x4f69; op2val:0x4051; + valaddr_reg:x1; val_offset:2464*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2464*FLEN/8, x2, x8, x12) + +inst_1265: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x042 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x384 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x5042; op2val:0x3f84; + valaddr_reg:x1; val_offset:2466*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2466*FLEN/8, x2, x8, x12) + +inst_1266: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x042 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x384 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x5042; op2val:0x3f84; + valaddr_reg:x1; val_offset:2468*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2468*FLEN/8, x2, x8, x12) + +inst_1267: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x042 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x384 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x5042; op2val:0x3f84; + valaddr_reg:x1; val_offset:2470*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2470*FLEN/8, x2, x8, x12) + +inst_1268: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x042 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x384 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x5042; op2val:0x3f84; + valaddr_reg:x1; val_offset:2472*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2472*FLEN/8, x2, x8, x12) + +inst_1269: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x042 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x384 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x5042; op2val:0x3f84; + valaddr_reg:x1; val_offset:2474*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2474*FLEN/8, x2, x8, x12) + +inst_1270: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x3d2 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x017 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x47d2; op2val:0x4817; + valaddr_reg:x1; val_offset:2476*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2476*FLEN/8, x2, x8, x12) + +inst_1271: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x3d2 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x017 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x47d2; op2val:0x4817; + valaddr_reg:x1; val_offset:2478*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2478*FLEN/8, x2, x8, x12) + +inst_1272: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x3d2 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x017 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x47d2; op2val:0x4817; + valaddr_reg:x1; val_offset:2480*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2480*FLEN/8, x2, x8, x12) + +inst_1273: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x3d2 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x017 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x47d2; op2val:0x4817; + valaddr_reg:x1; val_offset:2482*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2482*FLEN/8, x2, x8, x12) + +inst_1274: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x3d2 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x017 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x47d2; op2val:0x4817; + valaddr_reg:x1; val_offset:2484*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2484*FLEN/8, x2, x8, x12) + +inst_1275: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x08a and fs2 == 0 and fe2 == 0x11 and fm2 == 0x30c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x488a; op2val:0x470c; + valaddr_reg:x1; val_offset:2486*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2486*FLEN/8, x2, x8, x12) + +inst_1276: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x08a and fs2 == 0 and fe2 == 0x11 and fm2 == 0x30c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x488a; op2val:0x470c; + valaddr_reg:x1; val_offset:2488*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2488*FLEN/8, x2, x8, x12) + +inst_1277: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x08a and fs2 == 0 and fe2 == 0x11 and fm2 == 0x30c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x488a; op2val:0x470c; + valaddr_reg:x1; val_offset:2490*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2490*FLEN/8, x2, x8, x12) + +inst_1278: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x08a and fs2 == 0 and fe2 == 0x11 and fm2 == 0x30c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x488a; op2val:0x470c; + valaddr_reg:x1; val_offset:2492*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2492*FLEN/8, x2, x8, x12) + +inst_1279: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x08a and fs2 == 0 and fe2 == 0x11 and fm2 == 0x30c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x488a; op2val:0x470c; + valaddr_reg:x1; val_offset:2494*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2494*FLEN/8, x2, x8, x12) + +inst_1280: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x17a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1d7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x517a; op2val:0x3dd7; + valaddr_reg:x1; val_offset:2496*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2496*FLEN/8, x2, x8, x12) + +inst_1281: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x17a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1d7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x517a; op2val:0x3dd7; + valaddr_reg:x1; val_offset:2498*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2498*FLEN/8, x2, x8, x12) + +inst_1282: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x17a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1d7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x517a; op2val:0x3dd7; + valaddr_reg:x1; val_offset:2500*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2500*FLEN/8, x2, x8, x12) + +inst_1283: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x17a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1d7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x517a; op2val:0x3dd7; + valaddr_reg:x1; val_offset:2502*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2502*FLEN/8, x2, x8, x12) + +inst_1284: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x17a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1d7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x517a; op2val:0x3dd7; + valaddr_reg:x1; val_offset:2504*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2504*FLEN/8, x2, x8, x12) + +inst_1285: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x1df and fs2 == 0 and fe2 == 0x12 and fm2 == 0x173 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x45df; op2val:0x4973; + valaddr_reg:x1; val_offset:2506*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2506*FLEN/8, x2, x8, x12) + +inst_1286: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x1df and fs2 == 0 and fe2 == 0x12 and fm2 == 0x173 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x45df; op2val:0x4973; + valaddr_reg:x1; val_offset:2508*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2508*FLEN/8, x2, x8, x12) + +inst_1287: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x1df and fs2 == 0 and fe2 == 0x12 and fm2 == 0x173 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x45df; op2val:0x4973; + valaddr_reg:x1; val_offset:2510*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2510*FLEN/8, x2, x8, x12) + +inst_1288: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x1df and fs2 == 0 and fe2 == 0x12 and fm2 == 0x173 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x45df; op2val:0x4973; + valaddr_reg:x1; val_offset:2512*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2512*FLEN/8, x2, x8, x12) + +inst_1289: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x1df and fs2 == 0 and fe2 == 0x12 and fm2 == 0x173 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x45df; op2val:0x4973; + valaddr_reg:x1; val_offset:2514*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2514*FLEN/8, x2, x8, x12) + +inst_1290: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x268 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x5268; op2val:0x3cfe; + valaddr_reg:x1; val_offset:2516*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2516*FLEN/8, x2, x8, x12) + +inst_1291: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x268 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0fe and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x5268; op2val:0x3cfe; + valaddr_reg:x1; val_offset:2518*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2518*FLEN/8, x2, x8, x12) + +inst_1292: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x268 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0fe and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x5268; op2val:0x3cfe; + valaddr_reg:x1; val_offset:2520*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2520*FLEN/8, x2, x8, x12) + +inst_1293: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x268 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0fe and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x5268; op2val:0x3cfe; + valaddr_reg:x1; val_offset:2522*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2522*FLEN/8, x2, x8, x12) + +inst_1294: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x268 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0fe and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x5268; op2val:0x3cfe; + valaddr_reg:x1; val_offset:2524*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2524*FLEN/8, x2, x8, x12) + +inst_1295: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x3ad and fs2 == 0 and fe2 == 0x12 and fm2 == 0x02b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x47ad; op2val:0x482b; + valaddr_reg:x1; val_offset:2526*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2526*FLEN/8, x2, x8, x12) + +inst_1296: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x3ad and fs2 == 0 and fe2 == 0x12 and fm2 == 0x02b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x47ad; op2val:0x482b; + valaddr_reg:x1; val_offset:2528*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2528*FLEN/8, x2, x8, x12) + +inst_1297: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x3ad and fs2 == 0 and fe2 == 0x12 and fm2 == 0x02b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x47ad; op2val:0x482b; + valaddr_reg:x1; val_offset:2530*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2530*FLEN/8, x2, x8, x12) + +inst_1298: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x3ad and fs2 == 0 and fe2 == 0x12 and fm2 == 0x02b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x47ad; op2val:0x482b; + valaddr_reg:x1; val_offset:2532*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2532*FLEN/8, x2, x8, x12) + +inst_1299: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x3ad and fs2 == 0 and fe2 == 0x12 and fm2 == 0x02b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x47ad; op2val:0x482b; + valaddr_reg:x1; val_offset:2534*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2534*FLEN/8, x2, x8, x12) + +inst_1300: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x1f4 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x15f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x49f4; op2val:0x455f; + valaddr_reg:x1; val_offset:2536*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2536*FLEN/8, x2, x8, x12) + +inst_1301: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x1f4 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x15f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x49f4; op2val:0x455f; + valaddr_reg:x1; val_offset:2538*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2538*FLEN/8, x2, x8, x12) + +inst_1302: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x1f4 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x15f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x49f4; op2val:0x455f; + valaddr_reg:x1; val_offset:2540*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2540*FLEN/8, x2, x8, x12) + +inst_1303: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x1f4 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x15f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x49f4; op2val:0x455f; + valaddr_reg:x1; val_offset:2542*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2542*FLEN/8, x2, x8, x12) +RVTEST_SIGBASE(x8,signature_x8_10) + +inst_1304: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x1f4 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x15f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x49f4; op2val:0x455f; + valaddr_reg:x1; val_offset:2544*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2544*FLEN/8, x2, x8, x12) + +inst_1305: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x166 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1ed and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x5166; op2val:0x3ded; + valaddr_reg:x1; val_offset:2546*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2546*FLEN/8, x2, x8, x12) + +inst_1306: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x166 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1ed and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x5166; op2val:0x3ded; + valaddr_reg:x1; val_offset:2548*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2548*FLEN/8, x2, x8, x12) + +inst_1307: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x166 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1ed and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x5166; op2val:0x3ded; + valaddr_reg:x1; val_offset:2550*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2550*FLEN/8, x2, x8, x12) + +inst_1308: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x166 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1ed and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x5166; op2val:0x3ded; + valaddr_reg:x1; val_offset:2552*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2552*FLEN/8, x2, x8, x12) + +inst_1309: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x166 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1ed and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x5166; op2val:0x3ded; + valaddr_reg:x1; val_offset:2554*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2554*FLEN/8, x2, x8, x12) + +inst_1310: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3c7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x01d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x53c7; op2val:0x3c1d; + valaddr_reg:x1; val_offset:2556*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2556*FLEN/8, x2, x8, x12) + +inst_1311: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3c7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x01d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x53c7; op2val:0x3c1d; + valaddr_reg:x1; val_offset:2558*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2558*FLEN/8, x2, x8, x12) + +inst_1312: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3c7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x01d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x53c7; op2val:0x3c1d; + valaddr_reg:x1; val_offset:2560*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2560*FLEN/8, x2, x8, x12) + +inst_1313: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3c7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x01d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x53c7; op2val:0x3c1d; + valaddr_reg:x1; val_offset:2562*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2562*FLEN/8, x2, x8, x12) + +inst_1314: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3c7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x01d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x53c7; op2val:0x3c1d; + valaddr_reg:x1; val_offset:2564*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2564*FLEN/8, x2, x8, x12) + +inst_1315: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x022 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x3bd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x4422; op2val:0x4bbd; + valaddr_reg:x1; val_offset:2566*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2566*FLEN/8, x2, x8, x12) + +inst_1316: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x022 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x3bd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x4422; op2val:0x4bbd; + valaddr_reg:x1; val_offset:2568*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2568*FLEN/8, x2, x8, x12) + +inst_1317: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x022 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x3bd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x4422; op2val:0x4bbd; + valaddr_reg:x1; val_offset:2570*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2570*FLEN/8, x2, x8, x12) + +inst_1318: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x022 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x3bd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x4422; op2val:0x4bbd; + valaddr_reg:x1; val_offset:2572*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2572*FLEN/8, x2, x8, x12) + +inst_1319: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x022 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x3bd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x4422; op2val:0x4bbd; + valaddr_reg:x1; val_offset:2574*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2574*FLEN/8, x2, x8, x12) + +inst_1320: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x00d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3e4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x4c0d; op2val:0x43e4; + valaddr_reg:x1; val_offset:2576*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2576*FLEN/8, x2, x8, x12) + +inst_1321: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x00d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3e4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x4c0d; op2val:0x43e4; + valaddr_reg:x1; val_offset:2578*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2578*FLEN/8, x2, x8, x12) + +inst_1322: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x00d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3e4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x4c0d; op2val:0x43e4; + valaddr_reg:x1; val_offset:2580*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2580*FLEN/8, x2, x8, x12) + +inst_1323: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x00d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3e4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x4c0d; op2val:0x43e4; + valaddr_reg:x1; val_offset:2582*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2582*FLEN/8, x2, x8, x12) + +inst_1324: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x00d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3e4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x4c0d; op2val:0x43e4; + valaddr_reg:x1; val_offset:2584*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2584*FLEN/8, x2, x8, x12) + +inst_1325: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x086 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x312 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x5086; op2val:0x3f12; + valaddr_reg:x1; val_offset:2586*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2586*FLEN/8, x2, x8, x12) + +inst_1326: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x086 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x312 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x5086; op2val:0x3f12; + valaddr_reg:x1; val_offset:2588*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2588*FLEN/8, x2, x8, x12) + +inst_1327: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x086 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x312 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x5086; op2val:0x3f12; + valaddr_reg:x1; val_offset:2590*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2590*FLEN/8, x2, x8, x12) + +inst_1328: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x086 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x312 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x5086; op2val:0x3f12; + valaddr_reg:x1; val_offset:2592*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2592*FLEN/8, x2, x8, x12) + +inst_1329: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x086 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x312 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x5086; op2val:0x3f12; + valaddr_reg:x1; val_offset:2594*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2594*FLEN/8, x2, x8, x12) + +inst_1330: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x014 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3d8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x5014; op2val:0x3fd8; + valaddr_reg:x1; val_offset:2596*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2596*FLEN/8, x2, x8, x12) + +inst_1331: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x014 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3d8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x5014; op2val:0x3fd8; + valaddr_reg:x1; val_offset:2598*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2598*FLEN/8, x2, x8, x12) + +inst_1332: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x014 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3d8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x5014; op2val:0x3fd8; + valaddr_reg:x1; val_offset:2600*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2600*FLEN/8, x2, x8, x12) + +inst_1333: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x014 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3d8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x5014; op2val:0x3fd8; + valaddr_reg:x1; val_offset:2602*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2602*FLEN/8, x2, x8, x12) + +inst_1334: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x014 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3d8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x5014; op2val:0x3fd8; + valaddr_reg:x1; val_offset:2604*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2604*FLEN/8, x2, x8, x12) + +inst_1335: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x2c9 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0b6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x4ac9; op2val:0x44b6; + valaddr_reg:x1; val_offset:2606*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2606*FLEN/8, x2, x8, x12) + +inst_1336: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x2c9 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0b6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x4ac9; op2val:0x44b6; + valaddr_reg:x1; val_offset:2608*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2608*FLEN/8, x2, x8, x12) + +inst_1337: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x2c9 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0b6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x4ac9; op2val:0x44b6; + valaddr_reg:x1; val_offset:2610*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2610*FLEN/8, x2, x8, x12) + +inst_1338: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x2c9 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0b6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x4ac9; op2val:0x44b6; + valaddr_reg:x1; val_offset:2612*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2612*FLEN/8, x2, x8, x12) + +inst_1339: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x2c9 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0b6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x4ac9; op2val:0x44b6; + valaddr_reg:x1; val_offset:2614*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2614*FLEN/8, x2, x8, x12) + +inst_1340: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x299 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0d9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x5299; op2val:0x3cd9; + valaddr_reg:x1; val_offset:2616*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2616*FLEN/8, x2, x8, x12) + +inst_1341: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x299 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0d9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x5299; op2val:0x3cd9; + valaddr_reg:x1; val_offset:2618*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2618*FLEN/8, x2, x8, x12) + +inst_1342: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x299 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0d9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x5299; op2val:0x3cd9; + valaddr_reg:x1; val_offset:2620*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2620*FLEN/8, x2, x8, x12) + +inst_1343: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x299 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0d9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x5299; op2val:0x3cd9; + valaddr_reg:x1; val_offset:2622*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2622*FLEN/8, x2, x8, x12) + +inst_1344: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x299 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0d9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x5299; op2val:0x3cd9; + valaddr_reg:x1; val_offset:2624*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2624*FLEN/8, x2, x8, x12) + +inst_1345: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x17e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1d2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x517e; op2val:0x3dd2; + valaddr_reg:x1; val_offset:2626*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2626*FLEN/8, x2, x8, x12) + +inst_1346: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x17e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1d2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x517e; op2val:0x3dd2; + valaddr_reg:x1; val_offset:2628*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2628*FLEN/8, x2, x8, x12) + +inst_1347: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x17e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1d2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x517e; op2val:0x3dd2; + valaddr_reg:x1; val_offset:2630*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2630*FLEN/8, x2, x8, x12) + +inst_1348: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x17e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1d2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x517e; op2val:0x3dd2; + valaddr_reg:x1; val_offset:2632*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2632*FLEN/8, x2, x8, x12) + +inst_1349: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x17e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1d2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x517e; op2val:0x3dd2; + valaddr_reg:x1; val_offset:2634*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2634*FLEN/8, x2, x8, x12) + +inst_1350: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x0e8 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x284 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x48e8; op2val:0x4684; + valaddr_reg:x1; val_offset:2636*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2636*FLEN/8, x2, x8, x12) + +inst_1351: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x0e8 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x284 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x48e8; op2val:0x4684; + valaddr_reg:x1; val_offset:2638*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2638*FLEN/8, x2, x8, x12) + +inst_1352: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x0e8 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x284 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x48e8; op2val:0x4684; + valaddr_reg:x1; val_offset:2640*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2640*FLEN/8, x2, x8, x12) + +inst_1353: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x0e8 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x284 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x48e8; op2val:0x4684; + valaddr_reg:x1; val_offset:2642*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2642*FLEN/8, x2, x8, x12) + +inst_1354: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x0e8 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x284 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x48e8; op2val:0x4684; + valaddr_reg:x1; val_offset:2644*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2644*FLEN/8, x2, x8, x12) + +inst_1355: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x0a6 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x2e1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x48a6; op2val:0x46e1; + valaddr_reg:x1; val_offset:2646*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2646*FLEN/8, x2, x8, x12) + +inst_1356: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x0a6 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x2e1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x48a6; op2val:0x46e1; + valaddr_reg:x1; val_offset:2648*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2648*FLEN/8, x2, x8, x12) + +inst_1357: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x0a6 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x2e1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x48a6; op2val:0x46e1; + valaddr_reg:x1; val_offset:2650*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2650*FLEN/8, x2, x8, x12) + +inst_1358: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x0a6 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x2e1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x48a6; op2val:0x46e1; + valaddr_reg:x1; val_offset:2652*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2652*FLEN/8, x2, x8, x12) + +inst_1359: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x0a6 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x2e1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x48a6; op2val:0x46e1; + valaddr_reg:x1; val_offset:2654*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2654*FLEN/8, x2, x8, x12) + +inst_1360: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x3d1 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x017 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x47d1; op2val:0x4817; + valaddr_reg:x1; val_offset:2656*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2656*FLEN/8, x2, x8, x12) + +inst_1361: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x3d1 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x017 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x47d1; op2val:0x4817; + valaddr_reg:x1; val_offset:2658*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2658*FLEN/8, x2, x8, x12) + +inst_1362: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x3d1 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x017 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x47d1; op2val:0x4817; + valaddr_reg:x1; val_offset:2660*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2660*FLEN/8, x2, x8, x12) + +inst_1363: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x3d1 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x017 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x47d1; op2val:0x4817; + valaddr_reg:x1; val_offset:2662*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2662*FLEN/8, x2, x8, x12) + +inst_1364: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x3d1 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x017 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x47d1; op2val:0x4817; + valaddr_reg:x1; val_offset:2664*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2664*FLEN/8, x2, x8, x12) + +inst_1365: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x059 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x35b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x4459; op2val:0x4b5b; + valaddr_reg:x1; val_offset:2666*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2666*FLEN/8, x2, x8, x12) + +inst_1366: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x059 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x35b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x4459; op2val:0x4b5b; + valaddr_reg:x1; val_offset:2668*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2668*FLEN/8, x2, x8, x12) + +inst_1367: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x059 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x35b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x4459; op2val:0x4b5b; + valaddr_reg:x1; val_offset:2670*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2670*FLEN/8, x2, x8, x12) + +inst_1368: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x059 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x35b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x4459; op2val:0x4b5b; + valaddr_reg:x1; val_offset:2672*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2672*FLEN/8, x2, x8, x12) + +inst_1369: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x059 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x35b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x4459; op2val:0x4b5b; + valaddr_reg:x1; val_offset:2674*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2674*FLEN/8, x2, x8, x12) + +inst_1370: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x238 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x124 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x4e38; op2val:0x4124; + valaddr_reg:x1; val_offset:2676*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2676*FLEN/8, x2, x8, x12) + +inst_1371: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x238 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x124 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x4e38; op2val:0x4124; + valaddr_reg:x1; val_offset:2678*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2678*FLEN/8, x2, x8, x12) + +inst_1372: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x238 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x124 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x4e38; op2val:0x4124; + valaddr_reg:x1; val_offset:2680*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2680*FLEN/8, x2, x8, x12) + +inst_1373: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x238 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x124 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x4e38; op2val:0x4124; + valaddr_reg:x1; val_offset:2682*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2682*FLEN/8, x2, x8, x12) + +inst_1374: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x238 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x124 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x4e38; op2val:0x4124; + valaddr_reg:x1; val_offset:2684*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2684*FLEN/8, x2, x8, x12) + +inst_1375: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0a5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x52e3; op2val:0x3ca5; + valaddr_reg:x1; val_offset:2686*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2686*FLEN/8, x2, x8, x12) + +inst_1376: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0a5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x52e3; op2val:0x3ca5; + valaddr_reg:x1; val_offset:2688*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2688*FLEN/8, x2, x8, x12) + +inst_1377: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0a5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x52e3; op2val:0x3ca5; + valaddr_reg:x1; val_offset:2690*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2690*FLEN/8, x2, x8, x12) + +inst_1378: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0a5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x52e3; op2val:0x3ca5; + valaddr_reg:x1; val_offset:2692*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2692*FLEN/8, x2, x8, x12) + +inst_1379: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0a5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x52e3; op2val:0x3ca5; + valaddr_reg:x1; val_offset:2694*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2694*FLEN/8, x2, x8, x12) + +inst_1380: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x18a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x51c7; op2val:0x3d8a; + valaddr_reg:x1; val_offset:2696*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2696*FLEN/8, x2, x8, x12) + +inst_1381: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x18a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x51c7; op2val:0x3d8a; + valaddr_reg:x1; val_offset:2698*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2698*FLEN/8, x2, x8, x12) + +inst_1382: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x18a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x51c7; op2val:0x3d8a; + valaddr_reg:x1; val_offset:2700*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2700*FLEN/8, x2, x8, x12) + +inst_1383: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x18a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x51c7; op2val:0x3d8a; + valaddr_reg:x1; val_offset:2702*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2702*FLEN/8, x2, x8, x12) + +inst_1384: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x18a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x51c7; op2val:0x3d8a; + valaddr_reg:x1; val_offset:2704*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2704*FLEN/8, x2, x8, x12) + +inst_1385: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x358 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x05b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x5358; op2val:0x3c5b; + valaddr_reg:x1; val_offset:2706*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2706*FLEN/8, x2, x8, x12) + +inst_1386: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x358 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x05b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x5358; op2val:0x3c5b; + valaddr_reg:x1; val_offset:2708*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2708*FLEN/8, x2, x8, x12) + +inst_1387: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x358 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x05b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x5358; op2val:0x3c5b; + valaddr_reg:x1; val_offset:2710*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2710*FLEN/8, x2, x8, x12) + +inst_1388: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x358 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x05b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x5358; op2val:0x3c5b; + valaddr_reg:x1; val_offset:2712*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2712*FLEN/8, x2, x8, x12) + +inst_1389: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x358 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x05b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x5358; op2val:0x3c5b; + valaddr_reg:x1; val_offset:2714*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2714*FLEN/8, x2, x8, x12) + +inst_1390: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x3a4 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x02f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x47a4; op2val:0x482f; + valaddr_reg:x1; val_offset:2716*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2716*FLEN/8, x2, x8, x12) + +inst_1391: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x3a4 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x02f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x47a4; op2val:0x482f; + valaddr_reg:x1; val_offset:2718*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2718*FLEN/8, x2, x8, x12) + +inst_1392: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x3a4 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x02f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x47a4; op2val:0x482f; + valaddr_reg:x1; val_offset:2720*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2720*FLEN/8, x2, x8, x12) + +inst_1393: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x3a4 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x02f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x47a4; op2val:0x482f; + valaddr_reg:x1; val_offset:2722*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2722*FLEN/8, x2, x8, x12) + +inst_1394: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x3a4 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x02f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x47a4; op2val:0x482f; + valaddr_reg:x1; val_offset:2724*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2724*FLEN/8, x2, x8, x12) + +inst_1395: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x110 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x251 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x5110; op2val:0x3e51; + valaddr_reg:x1; val_offset:2726*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2726*FLEN/8, x2, x8, x12) + +inst_1396: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x110 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x251 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x5110; op2val:0x3e51; + valaddr_reg:x1; val_offset:2728*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2728*FLEN/8, x2, x8, x12) + +inst_1397: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x110 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x251 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x5110; op2val:0x3e51; + valaddr_reg:x1; val_offset:2730*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2730*FLEN/8, x2, x8, x12) + +inst_1398: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x110 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x251 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x5110; op2val:0x3e51; + valaddr_reg:x1; val_offset:2732*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2732*FLEN/8, x2, x8, x12) + +inst_1399: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x110 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x251 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x5110; op2val:0x3e51; + valaddr_reg:x1; val_offset:2734*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2734*FLEN/8, x2, x8, x12) + +inst_1400: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x231 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x12a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x4e31; op2val:0x412a; + valaddr_reg:x1; val_offset:2736*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2736*FLEN/8, x2, x8, x12) + +inst_1401: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x231 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x12a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x4e31; op2val:0x412a; + valaddr_reg:x1; val_offset:2738*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2738*FLEN/8, x2, x8, x12) + +inst_1402: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x231 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x12a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x4e31; op2val:0x412a; + valaddr_reg:x1; val_offset:2740*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2740*FLEN/8, x2, x8, x12) + +inst_1403: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x231 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x12a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x4e31; op2val:0x412a; + valaddr_reg:x1; val_offset:2742*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2742*FLEN/8, x2, x8, x12) + +inst_1404: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x231 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x12a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x4e31; op2val:0x412a; + valaddr_reg:x1; val_offset:2744*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2744*FLEN/8, x2, x8, x12) + +inst_1405: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x309 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x08c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x4f09; op2val:0x408c; + valaddr_reg:x1; val_offset:2746*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2746*FLEN/8, x2, x8, x12) + +inst_1406: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x309 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x08c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x4f09; op2val:0x408c; + valaddr_reg:x1; val_offset:2748*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2748*FLEN/8, x2, x8, x12) + +inst_1407: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x309 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x08c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x4f09; op2val:0x408c; + valaddr_reg:x1; val_offset:2750*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2750*FLEN/8, x2, x8, x12) + +inst_1408: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x309 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x08c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x4f09; op2val:0x408c; + valaddr_reg:x1; val_offset:2752*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2752*FLEN/8, x2, x8, x12) + +inst_1409: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x309 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x08c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x4f09; op2val:0x408c; + valaddr_reg:x1; val_offset:2754*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2754*FLEN/8, x2, x8, x12) + +inst_1410: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x285 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0e8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x4e85; op2val:0x40e8; + valaddr_reg:x1; val_offset:2756*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2756*FLEN/8, x2, x8, x12) + +inst_1411: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x285 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0e8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x4e85; op2val:0x40e8; + valaddr_reg:x1; val_offset:2758*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2758*FLEN/8, x2, x8, x12) + +inst_1412: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x285 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0e8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x4e85; op2val:0x40e8; + valaddr_reg:x1; val_offset:2760*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2760*FLEN/8, x2, x8, x12) + +inst_1413: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x285 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0e8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x4e85; op2val:0x40e8; + valaddr_reg:x1; val_offset:2762*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2762*FLEN/8, x2, x8, x12) + +inst_1414: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x285 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0e8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x4e85; op2val:0x40e8; + valaddr_reg:x1; val_offset:2764*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2764*FLEN/8, x2, x8, x12) + +inst_1415: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x284 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0e9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x5284; op2val:0x3ce9; + valaddr_reg:x1; val_offset:2766*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2766*FLEN/8, x2, x8, x12) + +inst_1416: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x284 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0e9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x5284; op2val:0x3ce9; + valaddr_reg:x1; val_offset:2768*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2768*FLEN/8, x2, x8, x12) + +inst_1417: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x284 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0e9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x5284; op2val:0x3ce9; + valaddr_reg:x1; val_offset:2770*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2770*FLEN/8, x2, x8, x12) + +inst_1418: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x284 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0e9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x5284; op2val:0x3ce9; + valaddr_reg:x1; val_offset:2772*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2772*FLEN/8, x2, x8, x12) + +inst_1419: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x284 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0e9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x5284; op2val:0x3ce9; + valaddr_reg:x1; val_offset:2774*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2774*FLEN/8, x2, x8, x12) + +inst_1420: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3b2 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x028 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x4fb2; op2val:0x4028; + valaddr_reg:x1; val_offset:2776*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2776*FLEN/8, x2, x8, x12) + +inst_1421: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3b2 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x028 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x4fb2; op2val:0x4028; + valaddr_reg:x1; val_offset:2778*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2778*FLEN/8, x2, x8, x12) + +inst_1422: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3b2 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x028 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x4fb2; op2val:0x4028; + valaddr_reg:x1; val_offset:2780*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2780*FLEN/8, x2, x8, x12) + +inst_1423: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3b2 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x028 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x4fb2; op2val:0x4028; + valaddr_reg:x1; val_offset:2782*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2782*FLEN/8, x2, x8, x12) + +inst_1424: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3b2 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x028 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x4fb2; op2val:0x4028; + valaddr_reg:x1; val_offset:2784*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2784*FLEN/8, x2, x8, x12) + +inst_1425: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x227 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x133 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x5227; op2val:0x3d33; + valaddr_reg:x1; val_offset:2786*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2786*FLEN/8, x2, x8, x12) + +inst_1426: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x227 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x133 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x5227; op2val:0x3d33; + valaddr_reg:x1; val_offset:2788*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2788*FLEN/8, x2, x8, x12) + +inst_1427: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x227 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x133 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x5227; op2val:0x3d33; + valaddr_reg:x1; val_offset:2790*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2790*FLEN/8, x2, x8, x12) + +inst_1428: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x227 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x133 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x5227; op2val:0x3d33; + valaddr_reg:x1; val_offset:2792*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2792*FLEN/8, x2, x8, x12) + +inst_1429: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x227 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x133 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x5227; op2val:0x3d33; + valaddr_reg:x1; val_offset:2794*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2794*FLEN/8, x2, x8, x12) + +inst_1430: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x3b7 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x025 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x4bb7; op2val:0x4425; + valaddr_reg:x1; val_offset:2796*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2796*FLEN/8, x2, x8, x12) + +inst_1431: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x3b7 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x025 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x4bb7; op2val:0x4425; + valaddr_reg:x1; val_offset:2798*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2798*FLEN/8, x2, x8, x12) +RVTEST_SIGBASE(x8,signature_x8_11) + +inst_1432: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x3b7 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x025 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x4bb7; op2val:0x4425; + valaddr_reg:x1; val_offset:2800*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2800*FLEN/8, x2, x8, x12) + +inst_1433: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x3b7 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x025 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x4bb7; op2val:0x4425; + valaddr_reg:x1; val_offset:2802*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2802*FLEN/8, x2, x8, x12) + +inst_1434: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x3b7 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x025 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x4bb7; op2val:0x4425; + valaddr_reg:x1; val_offset:2804*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2804*FLEN/8, x2, x8, x12) + +inst_1435: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1a1 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1af and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x51a1; op2val:0x3daf; + valaddr_reg:x1; val_offset:2806*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2806*FLEN/8, x2, x8, x12) + +inst_1436: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1a1 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1af and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x51a1; op2val:0x3daf; + valaddr_reg:x1; val_offset:2808*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2808*FLEN/8, x2, x8, x12) + +inst_1437: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1a1 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1af and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x51a1; op2val:0x3daf; + valaddr_reg:x1; val_offset:2810*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2810*FLEN/8, x2, x8, x12) + +inst_1438: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1a1 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1af and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x51a1; op2val:0x3daf; + valaddr_reg:x1; val_offset:2812*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2812*FLEN/8, x2, x8, x12) + +inst_1439: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1a1 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1af and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x51a1; op2val:0x3daf; + valaddr_reg:x1; val_offset:2814*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2814*FLEN/8, x2, x8, x12) + +inst_1440: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x1db and fs2 == 0 and fe2 == 0x13 and fm2 == 0x176 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x41db; op2val:0x4d76; + valaddr_reg:x1; val_offset:2816*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2816*FLEN/8, x2, x8, x12) + +inst_1441: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x1db and fs2 == 0 and fe2 == 0x13 and fm2 == 0x176 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x41db; op2val:0x4d76; + valaddr_reg:x1; val_offset:2818*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2818*FLEN/8, x2, x8, x12) + +inst_1442: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x1db and fs2 == 0 and fe2 == 0x13 and fm2 == 0x176 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x41db; op2val:0x4d76; + valaddr_reg:x1; val_offset:2820*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2820*FLEN/8, x2, x8, x12) + +inst_1443: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x1db and fs2 == 0 and fe2 == 0x13 and fm2 == 0x176 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x41db; op2val:0x4d76; + valaddr_reg:x1; val_offset:2822*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2822*FLEN/8, x2, x8, x12) + +inst_1444: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x1db and fs2 == 0 and fe2 == 0x13 and fm2 == 0x176 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x41db; op2val:0x4d76; + valaddr_reg:x1; val_offset:2824*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2824*FLEN/8, x2, x8, x12) + +inst_1445: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x2dd and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0a9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x4add; op2val:0x44a9; + valaddr_reg:x1; val_offset:2826*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2826*FLEN/8, x2, x8, x12) + +inst_1446: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x2dd and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0a9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x4add; op2val:0x44a9; + valaddr_reg:x1; val_offset:2828*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2828*FLEN/8, x2, x8, x12) + +inst_1447: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x2dd and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0a9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x4add; op2val:0x44a9; + valaddr_reg:x1; val_offset:2830*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2830*FLEN/8, x2, x8, x12) + +inst_1448: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x2dd and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0a9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x4add; op2val:0x44a9; + valaddr_reg:x1; val_offset:2832*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2832*FLEN/8, x2, x8, x12) + +inst_1449: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x2dd and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0a9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x4add; op2val:0x44a9; + valaddr_reg:x1; val_offset:2834*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2834*FLEN/8, x2, x8, x12) + +inst_1450: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x0b1 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2d2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x50b1; op2val:0x3ed2; + valaddr_reg:x1; val_offset:2836*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2836*FLEN/8, x2, x8, x12) + +inst_1451: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x0b1 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2d2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x50b1; op2val:0x3ed2; + valaddr_reg:x1; val_offset:2838*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2838*FLEN/8, x2, x8, x12) + +inst_1452: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x0b1 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2d2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x50b1; op2val:0x3ed2; + valaddr_reg:x1; val_offset:2840*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2840*FLEN/8, x2, x8, x12) + +inst_1453: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x0b1 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2d2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x50b1; op2val:0x3ed2; + valaddr_reg:x1; val_offset:2842*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2842*FLEN/8, x2, x8, x12) + +inst_1454: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x0b1 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2d2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x50b1; op2val:0x3ed2; + valaddr_reg:x1; val_offset:2844*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2844*FLEN/8, x2, x8, x12) + +inst_1455: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x24e and fs2 == 0 and fe2 == 0x0b and fm2 == 0x113 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x364e; op2val:0x2d13; + valaddr_reg:x1; val_offset:2846*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2846*FLEN/8, x2, x8, x12) + +inst_1456: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x24e and fs2 == 0 and fe2 == 0x0b and fm2 == 0x113 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x364e; op2val:0x2d13; + valaddr_reg:x1; val_offset:2848*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2848*FLEN/8, x2, x8, x12) + +inst_1457: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x24e and fs2 == 0 and fe2 == 0x0b and fm2 == 0x113 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x364e; op2val:0x2d13; + valaddr_reg:x1; val_offset:2850*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2850*FLEN/8, x2, x8, x12) + +inst_1458: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x24e and fs2 == 0 and fe2 == 0x0b and fm2 == 0x113 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x364e; op2val:0x2d13; + valaddr_reg:x1; val_offset:2852*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2852*FLEN/8, x2, x8, x12) + +inst_1459: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x24e and fs2 == 0 and fe2 == 0x0b and fm2 == 0x113 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x364e; op2val:0x2d13; + valaddr_reg:x1; val_offset:2854*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2854*FLEN/8, x2, x8, x12) + +inst_1460: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x11b and fs2 == 0 and fe2 == 0x0b and fm2 == 0x243 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x351b; op2val:0x2e43; + valaddr_reg:x1; val_offset:2856*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2856*FLEN/8, x2, x8, x12) + +inst_1461: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x11b and fs2 == 0 and fe2 == 0x0b and fm2 == 0x243 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x351b; op2val:0x2e43; + valaddr_reg:x1; val_offset:2858*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2858*FLEN/8, x2, x8, x12) + +inst_1462: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x11b and fs2 == 0 and fe2 == 0x0b and fm2 == 0x243 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x351b; op2val:0x2e43; + valaddr_reg:x1; val_offset:2860*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2860*FLEN/8, x2, x8, x12) + +inst_1463: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x11b and fs2 == 0 and fe2 == 0x0b and fm2 == 0x243 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x351b; op2val:0x2e43; + valaddr_reg:x1; val_offset:2862*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2862*FLEN/8, x2, x8, x12) + +inst_1464: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x11b and fs2 == 0 and fe2 == 0x0b and fm2 == 0x243 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x351b; op2val:0x2e43; + valaddr_reg:x1; val_offset:2864*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2864*FLEN/8, x2, x8, x12) + +inst_1465: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x031 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ba1; op2val:0x2831; + valaddr_reg:x1; val_offset:2866*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2866*FLEN/8, x2, x8, x12) + +inst_1466: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x031 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ba1; op2val:0x2831; + valaddr_reg:x1; val_offset:2868*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2868*FLEN/8, x2, x8, x12) + +inst_1467: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x031 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ba1; op2val:0x2831; + valaddr_reg:x1; val_offset:2870*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2870*FLEN/8, x2, x8, x12) + +inst_1468: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x031 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ba1; op2val:0x2831; + valaddr_reg:x1; val_offset:2872*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2872*FLEN/8, x2, x8, x12) + +inst_1469: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x031 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ba1; op2val:0x2831; + valaddr_reg:x1; val_offset:2874*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2874*FLEN/8, x2, x8, x12) + +inst_1470: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x27c and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0ef and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x327c; op2val:0x30ef; + valaddr_reg:x1; val_offset:2876*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2876*FLEN/8, x2, x8, x12) + +inst_1471: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x27c and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0ef and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x327c; op2val:0x30ef; + valaddr_reg:x1; val_offset:2878*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2878*FLEN/8, x2, x8, x12) + +inst_1472: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x27c and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0ef and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x327c; op2val:0x30ef; + valaddr_reg:x1; val_offset:2880*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2880*FLEN/8, x2, x8, x12) + +inst_1473: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x27c and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0ef and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x327c; op2val:0x30ef; + valaddr_reg:x1; val_offset:2882*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2882*FLEN/8, x2, x8, x12) + +inst_1474: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x27c and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0ef and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x327c; op2val:0x30ef; + valaddr_reg:x1; val_offset:2884*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2884*FLEN/8, x2, x8, x12) + +inst_1475: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2ba and fs2 == 0 and fe2 == 0x0b and fm2 == 0x0c1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x36ba; op2val:0x2cc1; + valaddr_reg:x1; val_offset:2886*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2886*FLEN/8, x2, x8, x12) + +inst_1476: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2ba and fs2 == 0 and fe2 == 0x0b and fm2 == 0x0c1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x36ba; op2val:0x2cc1; + valaddr_reg:x1; val_offset:2888*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2888*FLEN/8, x2, x8, x12) + +inst_1477: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2ba and fs2 == 0 and fe2 == 0x0b and fm2 == 0x0c1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x36ba; op2val:0x2cc1; + valaddr_reg:x1; val_offset:2890*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2890*FLEN/8, x2, x8, x12) + +inst_1478: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2ba and fs2 == 0 and fe2 == 0x0b and fm2 == 0x0c1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x36ba; op2val:0x2cc1; + valaddr_reg:x1; val_offset:2892*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2892*FLEN/8, x2, x8, x12) + +inst_1479: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2ba and fs2 == 0 and fe2 == 0x0b and fm2 == 0x0c1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x36ba; op2val:0x2cc1; + valaddr_reg:x1; val_offset:2894*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2894*FLEN/8, x2, x8, x12) + +inst_1480: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x27b and fs2 == 0 and fe2 == 0x0a and fm2 == 0x0ef and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a7b; op2val:0x28ef; + valaddr_reg:x1; val_offset:2896*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2896*FLEN/8, x2, x8, x12) + +inst_1481: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x27b and fs2 == 0 and fe2 == 0x0a and fm2 == 0x0ef and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a7b; op2val:0x28ef; + valaddr_reg:x1; val_offset:2898*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2898*FLEN/8, x2, x8, x12) + +inst_1482: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x27b and fs2 == 0 and fe2 == 0x0a and fm2 == 0x0ef and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a7b; op2val:0x28ef; + valaddr_reg:x1; val_offset:2900*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2900*FLEN/8, x2, x8, x12) + +inst_1483: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x27b and fs2 == 0 and fe2 == 0x0a and fm2 == 0x0ef and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a7b; op2val:0x28ef; + valaddr_reg:x1; val_offset:2902*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2902*FLEN/8, x2, x8, x12) + +inst_1484: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x27b and fs2 == 0 and fe2 == 0x0a and fm2 == 0x0ef and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a7b; op2val:0x28ef; + valaddr_reg:x1; val_offset:2904*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2904*FLEN/8, x2, x8, x12) + +inst_1485: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x225 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x135 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3625; op2val:0x2d35; + valaddr_reg:x1; val_offset:2906*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2906*FLEN/8, x2, x8, x12) + +inst_1486: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x225 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x135 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3625; op2val:0x2d35; + valaddr_reg:x1; val_offset:2908*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2908*FLEN/8, x2, x8, x12) + +inst_1487: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x225 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x135 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3625; op2val:0x2d35; + valaddr_reg:x1; val_offset:2910*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2910*FLEN/8, x2, x8, x12) + +inst_1488: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x225 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x135 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3625; op2val:0x2d35; + valaddr_reg:x1; val_offset:2912*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2912*FLEN/8, x2, x8, x12) + +inst_1489: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x225 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x135 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3625; op2val:0x2d35; + valaddr_reg:x1; val_offset:2914*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2914*FLEN/8, x2, x8, x12) + +inst_1490: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x28e and fs2 == 0 and fe2 == 0x0a and fm2 == 0x0e1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a8e; op2val:0x28e1; + valaddr_reg:x1; val_offset:2916*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2916*FLEN/8, x2, x8, x12) + +inst_1491: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x28e and fs2 == 0 and fe2 == 0x0a and fm2 == 0x0e1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a8e; op2val:0x28e1; + valaddr_reg:x1; val_offset:2918*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2918*FLEN/8, x2, x8, x12) + +inst_1492: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x28e and fs2 == 0 and fe2 == 0x0a and fm2 == 0x0e1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a8e; op2val:0x28e1; + valaddr_reg:x1; val_offset:2920*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2920*FLEN/8, x2, x8, x12) + +inst_1493: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x28e and fs2 == 0 and fe2 == 0x0a and fm2 == 0x0e1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a8e; op2val:0x28e1; + valaddr_reg:x1; val_offset:2922*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2922*FLEN/8, x2, x8, x12) + +inst_1494: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x28e and fs2 == 0 and fe2 == 0x0a and fm2 == 0x0e1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a8e; op2val:0x28e1; + valaddr_reg:x1; val_offset:2924*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2924*FLEN/8, x2, x8, x12) + +inst_1495: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2bb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0c1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2abb; op2val:0x38c1; + valaddr_reg:x1; val_offset:2926*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2926*FLEN/8, x2, x8, x12) + +inst_1496: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2bb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0c1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2abb; op2val:0x38c1; + valaddr_reg:x1; val_offset:2928*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2928*FLEN/8, x2, x8, x12) + +inst_1497: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2bb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0c1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2abb; op2val:0x38c1; + valaddr_reg:x1; val_offset:2930*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2930*FLEN/8, x2, x8, x12) + +inst_1498: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2bb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0c1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2abb; op2val:0x38c1; + valaddr_reg:x1; val_offset:2932*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2932*FLEN/8, x2, x8, x12) + +inst_1499: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2bb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0c1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2abb; op2val:0x38c1; + valaddr_reg:x1; val_offset:2934*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2934*FLEN/8, x2, x8, x12) + +inst_1500: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x067 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x344 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3867; op2val:0x2b44; + valaddr_reg:x1; val_offset:2936*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2936*FLEN/8, x2, x8, x12) + +inst_1501: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x067 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x344 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3867; op2val:0x2b44; + valaddr_reg:x1; val_offset:2938*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2938*FLEN/8, x2, x8, x12) + +inst_1502: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x067 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x344 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3867; op2val:0x2b44; + valaddr_reg:x1; val_offset:2940*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2940*FLEN/8, x2, x8, x12) + +inst_1503: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x067 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x344 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3867; op2val:0x2b44; + valaddr_reg:x1; val_offset:2942*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2942*FLEN/8, x2, x8, x12) + +inst_1504: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x067 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x344 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3867; op2val:0x2b44; + valaddr_reg:x1; val_offset:2944*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2944*FLEN/8, x2, x8, x12) + +inst_1505: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x261 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x103 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a61; op2val:0x2903; + valaddr_reg:x1; val_offset:2946*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2946*FLEN/8, x2, x8, x12) + +inst_1506: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x261 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x103 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a61; op2val:0x2903; + valaddr_reg:x1; val_offset:2948*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2948*FLEN/8, x2, x8, x12) + +inst_1507: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x261 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x103 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a61; op2val:0x2903; + valaddr_reg:x1; val_offset:2950*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2950*FLEN/8, x2, x8, x12) + +inst_1508: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x261 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x103 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a61; op2val:0x2903; + valaddr_reg:x1; val_offset:2952*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2952*FLEN/8, x2, x8, x12) + +inst_1509: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x261 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x103 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a61; op2val:0x2903; + valaddr_reg:x1; val_offset:2954*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2954*FLEN/8, x2, x8, x12) + +inst_1510: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x122 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x23b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3522; op2val:0x2e3b; + valaddr_reg:x1; val_offset:2956*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2956*FLEN/8, x2, x8, x12) + +inst_1511: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x122 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x23b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3522; op2val:0x2e3b; + valaddr_reg:x1; val_offset:2958*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2958*FLEN/8, x2, x8, x12) + +inst_1512: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x122 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x23b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3522; op2val:0x2e3b; + valaddr_reg:x1; val_offset:2960*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2960*FLEN/8, x2, x8, x12) + +inst_1513: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x122 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x23b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3522; op2val:0x2e3b; + valaddr_reg:x1; val_offset:2962*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2962*FLEN/8, x2, x8, x12) + +inst_1514: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x122 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x23b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3522; op2val:0x2e3b; + valaddr_reg:x1; val_offset:2964*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2964*FLEN/8, x2, x8, x12) + +inst_1515: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x006 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3f4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3006; op2val:0x33f4; + valaddr_reg:x1; val_offset:2966*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2966*FLEN/8, x2, x8, x12) + +inst_1516: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x006 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3f4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3006; op2val:0x33f4; + valaddr_reg:x1; val_offset:2968*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2968*FLEN/8, x2, x8, x12) + +inst_1517: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x006 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3f4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3006; op2val:0x33f4; + valaddr_reg:x1; val_offset:2970*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2970*FLEN/8, x2, x8, x12) + +inst_1518: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x006 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3f4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3006; op2val:0x33f4; + valaddr_reg:x1; val_offset:2972*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2972*FLEN/8, x2, x8, x12) + +inst_1519: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x006 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3f4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3006; op2val:0x33f4; + valaddr_reg:x1; val_offset:2974*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2974*FLEN/8, x2, x8, x12) + +inst_1520: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0cd and fs2 == 0 and fe2 == 0x0a and fm2 == 0x2aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x38cd; op2val:0x2aaa; + valaddr_reg:x1; val_offset:2976*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2976*FLEN/8, x2, x8, x12) + +inst_1521: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0cd and fs2 == 0 and fe2 == 0x0a and fm2 == 0x2aa and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x38cd; op2val:0x2aaa; + valaddr_reg:x1; val_offset:2978*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2978*FLEN/8, x2, x8, x12) + +inst_1522: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0cd and fs2 == 0 and fe2 == 0x0a and fm2 == 0x2aa and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x38cd; op2val:0x2aaa; + valaddr_reg:x1; val_offset:2980*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2980*FLEN/8, x2, x8, x12) + +inst_1523: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0cd and fs2 == 0 and fe2 == 0x0a and fm2 == 0x2aa and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x38cd; op2val:0x2aaa; + valaddr_reg:x1; val_offset:2982*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2982*FLEN/8, x2, x8, x12) + +inst_1524: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0cd and fs2 == 0 and fe2 == 0x0a and fm2 == 0x2aa and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x38cd; op2val:0x2aaa; + valaddr_reg:x1; val_offset:2984*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2984*FLEN/8, x2, x8, x12) + +inst_1525: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0d5 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x29f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x34d5; op2val:0x2e9f; + valaddr_reg:x1; val_offset:2986*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2986*FLEN/8, x2, x8, x12) + +inst_1526: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0d5 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x29f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x34d5; op2val:0x2e9f; + valaddr_reg:x1; val_offset:2988*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2988*FLEN/8, x2, x8, x12) + +inst_1527: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0d5 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x29f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x34d5; op2val:0x2e9f; + valaddr_reg:x1; val_offset:2990*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 2990*FLEN/8, x2, x8, x12) + +inst_1528: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0d5 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x29f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x34d5; op2val:0x2e9f; + valaddr_reg:x1; val_offset:2992*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 2992*FLEN/8, x2, x8, x12) + +inst_1529: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0d5 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x29f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x34d5; op2val:0x2e9f; + valaddr_reg:x1; val_offset:2994*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 2994*FLEN/8, x2, x8, x12) + +inst_1530: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1c8 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x189 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x35c8; op2val:0x2d89; + valaddr_reg:x1; val_offset:2996*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 2996*FLEN/8, x2, x8, x12) + +inst_1531: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1c8 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x189 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x35c8; op2val:0x2d89; + valaddr_reg:x1; val_offset:2998*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 2998*FLEN/8, x2, x8, x12) + +inst_1532: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1c8 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x189 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x35c8; op2val:0x2d89; + valaddr_reg:x1; val_offset:3000*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 3000*FLEN/8, x2, x8, x12) + +inst_1533: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1c8 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x189 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x35c8; op2val:0x2d89; + valaddr_reg:x1; val_offset:3002*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 3002*FLEN/8, x2, x8, x12) + +inst_1534: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1c8 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x189 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x35c8; op2val:0x2d89; + valaddr_reg:x1; val_offset:3004*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 3004*FLEN/8, x2, x8, x12) + +inst_1535: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x11d and fs2 == 0 and fe2 == 0x0b and fm2 == 0x241 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x351d; op2val:0x2e41; + valaddr_reg:x1; val_offset:3006*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 3006*FLEN/8, x2, x8, x12) + +inst_1536: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x11d and fs2 == 0 and fe2 == 0x0b and fm2 == 0x241 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x351d; op2val:0x2e41; + valaddr_reg:x1; val_offset:3008*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 3008*FLEN/8, x2, x8, x12) + +inst_1537: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x11d and fs2 == 0 and fe2 == 0x0b and fm2 == 0x241 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x351d; op2val:0x2e41; + valaddr_reg:x1; val_offset:3010*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 3010*FLEN/8, x2, x8, x12) + +inst_1538: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x11d and fs2 == 0 and fe2 == 0x0b and fm2 == 0x241 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x351d; op2val:0x2e41; + valaddr_reg:x1; val_offset:3012*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 3012*FLEN/8, x2, x8, x12) + +inst_1539: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x11d and fs2 == 0 and fe2 == 0x0b and fm2 == 0x241 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x351d; op2val:0x2e41; + valaddr_reg:x1; val_offset:3014*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 3014*FLEN/8, x2, x8, x12) + +inst_1540: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x38c and fs2 == 0 and fe2 == 0x0d and fm2 == 0x03d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2f8c; op2val:0x343d; + valaddr_reg:x1; val_offset:3016*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 3016*FLEN/8, x2, x8, x12) + +inst_1541: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x38c and fs2 == 0 and fe2 == 0x0d and fm2 == 0x03d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2f8c; op2val:0x343d; + valaddr_reg:x1; val_offset:3018*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 3018*FLEN/8, x2, x8, x12) + +inst_1542: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x38c and fs2 == 0 and fe2 == 0x0d and fm2 == 0x03d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2f8c; op2val:0x343d; + valaddr_reg:x1; val_offset:3020*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 3020*FLEN/8, x2, x8, x12) + +inst_1543: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x38c and fs2 == 0 and fe2 == 0x0d and fm2 == 0x03d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2f8c; op2val:0x343d; + valaddr_reg:x1; val_offset:3022*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 3022*FLEN/8, x2, x8, x12) + +inst_1544: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x38c and fs2 == 0 and fe2 == 0x0d and fm2 == 0x03d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2f8c; op2val:0x343d; + valaddr_reg:x1; val_offset:3024*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 3024*FLEN/8, x2, x8, x12) + +inst_1545: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x16a and fs2 == 0 and fe2 == 0x0a and fm2 == 0x1e8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x396a; op2val:0x29e8; + valaddr_reg:x1; val_offset:3026*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 3026*FLEN/8, x2, x8, x12) + +inst_1546: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x16a and fs2 == 0 and fe2 == 0x0a and fm2 == 0x1e8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x396a; op2val:0x29e8; + valaddr_reg:x1; val_offset:3028*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 3028*FLEN/8, x2, x8, x12) + +inst_1547: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x16a and fs2 == 0 and fe2 == 0x0a and fm2 == 0x1e8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x396a; op2val:0x29e8; + valaddr_reg:x1; val_offset:3030*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 3030*FLEN/8, x2, x8, x12) + +inst_1548: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x16a and fs2 == 0 and fe2 == 0x0a and fm2 == 0x1e8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x396a; op2val:0x29e8; + valaddr_reg:x1; val_offset:3032*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 3032*FLEN/8, x2, x8, x12) + +inst_1549: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x16a and fs2 == 0 and fe2 == 0x0a and fm2 == 0x1e8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x396a; op2val:0x29e8; + valaddr_reg:x1; val_offset:3034*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 3034*FLEN/8, x2, x8, x12) + +inst_1550: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0f5 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x274 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x38f5; op2val:0x2a74; + valaddr_reg:x1; val_offset:3036*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 3036*FLEN/8, x2, x8, x12) + +inst_1551: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0f5 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x274 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x38f5; op2val:0x2a74; + valaddr_reg:x1; val_offset:3038*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 3038*FLEN/8, x2, x8, x12) + +inst_1552: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0f5 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x274 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x38f5; op2val:0x2a74; + valaddr_reg:x1; val_offset:3040*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 3040*FLEN/8, x2, x8, x12) + +inst_1553: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0f5 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x274 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x38f5; op2val:0x2a74; + valaddr_reg:x1; val_offset:3042*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 3042*FLEN/8, x2, x8, x12) + +inst_1554: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0f5 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x274 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x38f5; op2val:0x2a74; + valaddr_reg:x1; val_offset:3044*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 3044*FLEN/8, x2, x8, x12) + +inst_1555: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2b9 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0c2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2eb9; op2val:0x34c2; + valaddr_reg:x1; val_offset:3046*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 3046*FLEN/8, x2, x8, x12) + +inst_1556: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2b9 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0c2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2eb9; op2val:0x34c2; + valaddr_reg:x1; val_offset:3048*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 3048*FLEN/8, x2, x8, x12) + +inst_1557: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2b9 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0c2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2eb9; op2val:0x34c2; + valaddr_reg:x1; val_offset:3050*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 3050*FLEN/8, x2, x8, x12) + +inst_1558: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2b9 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0c2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2eb9; op2val:0x34c2; + valaddr_reg:x1; val_offset:3052*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 3052*FLEN/8, x2, x8, x12) + +inst_1559: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2b9 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0c2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2eb9; op2val:0x34c2; + valaddr_reg:x1; val_offset:3054*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 3054*FLEN/8, x2, x8, x12) +RVTEST_SIGBASE(x8,signature_x8_12) + +inst_1560: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x007 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3407; op2val:0x2ff0; + valaddr_reg:x1; val_offset:3056*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 3056*FLEN/8, x2, x8, x12) + +inst_1561: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x007 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3f0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3407; op2val:0x2ff0; + valaddr_reg:x1; val_offset:3058*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 3058*FLEN/8, x2, x8, x12) + +inst_1562: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x007 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3f0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3407; op2val:0x2ff0; + valaddr_reg:x1; val_offset:3060*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 3060*FLEN/8, x2, x8, x12) + +inst_1563: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x007 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3f0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3407; op2val:0x2ff0; + valaddr_reg:x1; val_offset:3062*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 3062*FLEN/8, x2, x8, x12) + +inst_1564: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x007 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3f0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3407; op2val:0x2ff0; + valaddr_reg:x1; val_offset:3064*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 3064*FLEN/8, x2, x8, x12) + +inst_1565: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3a0 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x032 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x33a0; op2val:0x3032; + valaddr_reg:x1; val_offset:3066*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 3066*FLEN/8, x2, x8, x12) + +inst_1566: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3a0 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x032 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x33a0; op2val:0x3032; + valaddr_reg:x1; val_offset:3068*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 3068*FLEN/8, x2, x8, x12) + +inst_1567: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3a0 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x032 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x33a0; op2val:0x3032; + valaddr_reg:x1; val_offset:3070*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 3070*FLEN/8, x2, x8, x12) + +inst_1568: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3a0 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x032 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x33a0; op2val:0x3032; + valaddr_reg:x1; val_offset:3072*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 3072*FLEN/8, x2, x8, x12) + +inst_1569: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3a0 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x032 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x33a0; op2val:0x3032; + valaddr_reg:x1; val_offset:3074*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 3074*FLEN/8, x2, x8, x12) + +inst_1570: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x07a and fs2 == 0 and fe2 == 0x0a and fm2 == 0x325 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x387a; op2val:0x2b25; + valaddr_reg:x1; val_offset:3076*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 3076*FLEN/8, x2, x8, x12) + +inst_1571: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x07a and fs2 == 0 and fe2 == 0x0a and fm2 == 0x325 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x387a; op2val:0x2b25; + valaddr_reg:x1; val_offset:3078*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 3078*FLEN/8, x2, x8, x12) + +inst_1572: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x07a and fs2 == 0 and fe2 == 0x0a and fm2 == 0x325 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x387a; op2val:0x2b25; + valaddr_reg:x1; val_offset:3080*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 3080*FLEN/8, x2, x8, x12) + +inst_1573: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x07a and fs2 == 0 and fe2 == 0x0a and fm2 == 0x325 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x387a; op2val:0x2b25; + valaddr_reg:x1; val_offset:3082*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 3082*FLEN/8, x2, x8, x12) + +inst_1574: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x07a and fs2 == 0 and fe2 == 0x0a and fm2 == 0x325 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x387a; op2val:0x2b25; + valaddr_reg:x1; val_offset:3084*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 3084*FLEN/8, x2, x8, x12) + +inst_1575: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x055 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x363 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3855; op2val:0x2b63; + valaddr_reg:x1; val_offset:3086*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 3086*FLEN/8, x2, x8, x12) + +inst_1576: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x055 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x363 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3855; op2val:0x2b63; + valaddr_reg:x1; val_offset:3088*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 3088*FLEN/8, x2, x8, x12) + +inst_1577: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x055 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x363 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3855; op2val:0x2b63; + valaddr_reg:x1; val_offset:3090*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 3090*FLEN/8, x2, x8, x12) + +inst_1578: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x055 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x363 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3855; op2val:0x2b63; + valaddr_reg:x1; val_offset:3092*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 3092*FLEN/8, x2, x8, x12) + +inst_1579: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x055 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x363 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3855; op2val:0x2b63; + valaddr_reg:x1; val_offset:3094*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 3094*FLEN/8, x2, x8, x12) + +inst_1580: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x285 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x0e8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a85; op2val:0x28e8; + valaddr_reg:x1; val_offset:3096*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 3096*FLEN/8, x2, x8, x12) + +inst_1581: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x285 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x0e8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a85; op2val:0x28e8; + valaddr_reg:x1; val_offset:3098*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 3098*FLEN/8, x2, x8, x12) + +inst_1582: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x285 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x0e8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a85; op2val:0x28e8; + valaddr_reg:x1; val_offset:3100*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 3100*FLEN/8, x2, x8, x12) + +inst_1583: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x285 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x0e8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a85; op2val:0x28e8; + valaddr_reg:x1; val_offset:3102*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 3102*FLEN/8, x2, x8, x12) + +inst_1584: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x285 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x0e8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a85; op2val:0x28e8; + valaddr_reg:x1; val_offset:3104*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 3104*FLEN/8, x2, x8, x12) + +inst_1585: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x282 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x0ea and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a82; op2val:0x28ea; + valaddr_reg:x1; val_offset:3106*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 3106*FLEN/8, x2, x8, x12) + +inst_1586: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x282 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x0ea and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a82; op2val:0x28ea; + valaddr_reg:x1; val_offset:3108*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 3108*FLEN/8, x2, x8, x12) + +inst_1587: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x282 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x0ea and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a82; op2val:0x28ea; + valaddr_reg:x1; val_offset:3110*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 3110*FLEN/8, x2, x8, x12) + +inst_1588: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x282 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x0ea and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a82; op2val:0x28ea; + valaddr_reg:x1; val_offset:3112*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 3112*FLEN/8, x2, x8, x12) + +inst_1589: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x282 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x0ea and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a82; op2val:0x28ea; + valaddr_reg:x1; val_offset:3114*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 3114*FLEN/8, x2, x8, x12) + +inst_1590: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x31d and fs2 == 0 and fe2 == 0x0b and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x371d; op2val:0x2c7f; + valaddr_reg:x1; val_offset:3116*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 3116*FLEN/8, x2, x8, x12) + +inst_1591: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x31d and fs2 == 0 and fe2 == 0x0b and fm2 == 0x07f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x371d; op2val:0x2c7f; + valaddr_reg:x1; val_offset:3118*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 3118*FLEN/8, x2, x8, x12) + +inst_1592: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x31d and fs2 == 0 and fe2 == 0x0b and fm2 == 0x07f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x371d; op2val:0x2c7f; + valaddr_reg:x1; val_offset:3120*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 3120*FLEN/8, x2, x8, x12) + +inst_1593: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x31d and fs2 == 0 and fe2 == 0x0b and fm2 == 0x07f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x371d; op2val:0x2c7f; + valaddr_reg:x1; val_offset:3122*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 3122*FLEN/8, x2, x8, x12) + +inst_1594: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x31d and fs2 == 0 and fe2 == 0x0b and fm2 == 0x07f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x371d; op2val:0x2c7f; + valaddr_reg:x1; val_offset:3124*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 3124*FLEN/8, x2, x8, x12) + +inst_1595: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ad and fs2 == 0 and fe2 == 0x0a and fm2 == 0x0ca and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aad; op2val:0x28ca; + valaddr_reg:x1; val_offset:3126*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 3126*FLEN/8, x2, x8, x12) + +inst_1596: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ad and fs2 == 0 and fe2 == 0x0a and fm2 == 0x0ca and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aad; op2val:0x28ca; + valaddr_reg:x1; val_offset:3128*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 3128*FLEN/8, x2, x8, x12) + +inst_1597: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ad and fs2 == 0 and fe2 == 0x0a and fm2 == 0x0ca and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aad; op2val:0x28ca; + valaddr_reg:x1; val_offset:3130*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 3130*FLEN/8, x2, x8, x12) + +inst_1598: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ad and fs2 == 0 and fe2 == 0x0a and fm2 == 0x0ca and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aad; op2val:0x28ca; + valaddr_reg:x1; val_offset:3132*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 3132*FLEN/8, x2, x8, x12) + +inst_1599: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ad and fs2 == 0 and fe2 == 0x0a and fm2 == 0x0ca and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aad; op2val:0x28ca; + valaddr_reg:x1; val_offset:3134*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 3134*FLEN/8, x2, x8, x12) + +inst_1600: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x155 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3155; op2val:0x31ff; + valaddr_reg:x1; val_offset:3136*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 3136*FLEN/8, x2, x8, x12) + +inst_1601: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x155 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3155; op2val:0x31ff; + valaddr_reg:x1; val_offset:3138*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 3138*FLEN/8, x2, x8, x12) + +inst_1602: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x155 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3155; op2val:0x31ff; + valaddr_reg:x1; val_offset:3140*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 3140*FLEN/8, x2, x8, x12) + +inst_1603: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x155 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3155; op2val:0x31ff; + valaddr_reg:x1; val_offset:3142*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 3142*FLEN/8, x2, x8, x12) + +inst_1604: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x155 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3155; op2val:0x31ff; + valaddr_reg:x1; val_offset:3144*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 3144*FLEN/8, x2, x8, x12) + +inst_1605: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x274 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x0f4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3674; op2val:0x2cf4; + valaddr_reg:x1; val_offset:3146*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 3146*FLEN/8, x2, x8, x12) + +inst_1606: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x274 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x0f4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3674; op2val:0x2cf4; + valaddr_reg:x1; val_offset:3148*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 3148*FLEN/8, x2, x8, x12) + +inst_1607: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x274 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x0f4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3674; op2val:0x2cf4; + valaddr_reg:x1; val_offset:3150*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 3150*FLEN/8, x2, x8, x12) + +inst_1608: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x274 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x0f4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3674; op2val:0x2cf4; + valaddr_reg:x1; val_offset:3152*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 3152*FLEN/8, x2, x8, x12) + +inst_1609: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x274 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x0f4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3674; op2val:0x2cf4; + valaddr_reg:x1; val_offset:3154*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 3154*FLEN/8, x2, x8, x12) + +inst_1610: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x091 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3091; op2val:0x3300; + valaddr_reg:x1; val_offset:3156*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 3156*FLEN/8, x2, x8, x12) + +inst_1611: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x091 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x300 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3091; op2val:0x3300; + valaddr_reg:x1; val_offset:3158*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 3158*FLEN/8, x2, x8, x12) + +inst_1612: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x091 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x300 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3091; op2val:0x3300; + valaddr_reg:x1; val_offset:3160*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 3160*FLEN/8, x2, x8, x12) + +inst_1613: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x091 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x300 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3091; op2val:0x3300; + valaddr_reg:x1; val_offset:3162*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 3162*FLEN/8, x2, x8, x12) + +inst_1614: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x091 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x300 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3091; op2val:0x3300; + valaddr_reg:x1; val_offset:3164*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 3164*FLEN/8, x2, x8, x12) + +inst_1615: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x19d and fs2 == 0 and fe2 == 0x0a and fm2 == 0x1b3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x399d; op2val:0x29b3; + valaddr_reg:x1; val_offset:3166*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 3166*FLEN/8, x2, x8, x12) + +inst_1616: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x19d and fs2 == 0 and fe2 == 0x0a and fm2 == 0x1b3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x399d; op2val:0x29b3; + valaddr_reg:x1; val_offset:3168*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 3168*FLEN/8, x2, x8, x12) + +inst_1617: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x19d and fs2 == 0 and fe2 == 0x0a and fm2 == 0x1b3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x399d; op2val:0x29b3; + valaddr_reg:x1; val_offset:3170*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 3170*FLEN/8, x2, x8, x12) + +inst_1618: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x19d and fs2 == 0 and fe2 == 0x0a and fm2 == 0x1b3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x399d; op2val:0x29b3; + valaddr_reg:x1; val_offset:3172*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 3172*FLEN/8, x2, x8, x12) + +inst_1619: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x19d and fs2 == 0 and fe2 == 0x0a and fm2 == 0x1b3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x399d; op2val:0x29b3; + valaddr_reg:x1; val_offset:3174*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 3174*FLEN/8, x2, x8, x12) + +inst_1620: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x20e and fs2 == 0 and fe2 == 0x0c and fm2 == 0x148 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x320e; op2val:0x3148; + valaddr_reg:x1; val_offset:3176*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 3176*FLEN/8, x2, x8, x12) + +inst_1621: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x20e and fs2 == 0 and fe2 == 0x0c and fm2 == 0x148 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x320e; op2val:0x3148; + valaddr_reg:x1; val_offset:3178*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 3178*FLEN/8, x2, x8, x12) + +inst_1622: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x20e and fs2 == 0 and fe2 == 0x0c and fm2 == 0x148 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x320e; op2val:0x3148; + valaddr_reg:x1; val_offset:3180*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 3180*FLEN/8, x2, x8, x12) + +inst_1623: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x20e and fs2 == 0 and fe2 == 0x0c and fm2 == 0x148 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x320e; op2val:0x3148; + valaddr_reg:x1; val_offset:3182*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 3182*FLEN/8, x2, x8, x12) + +inst_1624: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x20e and fs2 == 0 and fe2 == 0x0c and fm2 == 0x148 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x320e; op2val:0x3148; + valaddr_reg:x1; val_offset:3184*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 3184*FLEN/8, x2, x8, x12) + +inst_1625: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e6 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x00c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3be6; op2val:0x280c; + valaddr_reg:x1; val_offset:3186*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 3186*FLEN/8, x2, x8, x12) + +inst_1626: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e6 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x00c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3be6; op2val:0x280c; + valaddr_reg:x1; val_offset:3188*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 3188*FLEN/8, x2, x8, x12) + +inst_1627: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e6 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x00c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3be6; op2val:0x280c; + valaddr_reg:x1; val_offset:3190*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 3190*FLEN/8, x2, x8, x12) + +inst_1628: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e6 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x00c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3be6; op2val:0x280c; + valaddr_reg:x1; val_offset:3192*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 3192*FLEN/8, x2, x8, x12) + +inst_1629: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e6 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x00c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3be6; op2val:0x280c; + valaddr_reg:x1; val_offset:3194*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 3194*FLEN/8, x2, x8, x12) + +inst_1630: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x277 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x0f3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a77; op2val:0x28f3; + valaddr_reg:x1; val_offset:3196*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 3196*FLEN/8, x2, x8, x12) + +inst_1631: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x277 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x0f3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a77; op2val:0x28f3; + valaddr_reg:x1; val_offset:3198*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 3198*FLEN/8, x2, x8, x12) + +inst_1632: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x277 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x0f3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a77; op2val:0x28f3; + valaddr_reg:x1; val_offset:3200*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 3200*FLEN/8, x2, x8, x12) + +inst_1633: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x277 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x0f3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a77; op2val:0x28f3; + valaddr_reg:x1; val_offset:3202*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 3202*FLEN/8, x2, x8, x12) + +inst_1634: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x277 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x0f3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a77; op2val:0x28f3; + valaddr_reg:x1; val_offset:3204*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 3204*FLEN/8, x2, x8, x12) + +inst_1635: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x187 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x1ca and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3987; op2val:0x29ca; + valaddr_reg:x1; val_offset:3206*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 3206*FLEN/8, x2, x8, x12) + +inst_1636: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x187 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x1ca and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3987; op2val:0x29ca; + valaddr_reg:x1; val_offset:3208*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 3208*FLEN/8, x2, x8, x12) + +inst_1637: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x187 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x1ca and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3987; op2val:0x29ca; + valaddr_reg:x1; val_offset:3210*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 3210*FLEN/8, x2, x8, x12) + +inst_1638: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x187 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x1ca and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3987; op2val:0x29ca; + valaddr_reg:x1; val_offset:3212*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 3212*FLEN/8, x2, x8, x12) + +inst_1639: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x187 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x1ca and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3987; op2val:0x29ca; + valaddr_reg:x1; val_offset:3214*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 3214*FLEN/8, x2, x8, x12) + +inst_1640: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0c6 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2b3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x34c6; op2val:0x2eb3; + valaddr_reg:x1; val_offset:3216*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 3216*FLEN/8, x2, x8, x12) + +inst_1641: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0c6 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2b3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x34c6; op2val:0x2eb3; + valaddr_reg:x1; val_offset:3218*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 3218*FLEN/8, x2, x8, x12) + +inst_1642: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0c6 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2b3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x34c6; op2val:0x2eb3; + valaddr_reg:x1; val_offset:3220*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 3220*FLEN/8, x2, x8, x12) + +inst_1643: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0c6 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2b3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x34c6; op2val:0x2eb3; + valaddr_reg:x1; val_offset:3222*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 3222*FLEN/8, x2, x8, x12) + +inst_1644: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0c6 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2b3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x34c6; op2val:0x2eb3; + valaddr_reg:x1; val_offset:3224*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 3224*FLEN/8, x2, x8, x12) + +inst_1645: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x095 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x2fa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3895; op2val:0x2afa; + valaddr_reg:x1; val_offset:3226*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 3226*FLEN/8, x2, x8, x12) + +inst_1646: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x095 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x2fa and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3895; op2val:0x2afa; + valaddr_reg:x1; val_offset:3228*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 3228*FLEN/8, x2, x8, x12) + +inst_1647: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x095 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x2fa and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3895; op2val:0x2afa; + valaddr_reg:x1; val_offset:3230*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 3230*FLEN/8, x2, x8, x12) + +inst_1648: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x095 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x2fa and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3895; op2val:0x2afa; + valaddr_reg:x1; val_offset:3232*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 3232*FLEN/8, x2, x8, x12) + +inst_1649: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x095 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x2fa and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3895; op2val:0x2afa; + valaddr_reg:x1; val_offset:3234*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 3234*FLEN/8, x2, x8, x12) + +inst_1650: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x229 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x131 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3229; op2val:0x3131; + valaddr_reg:x1; val_offset:3236*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 3236*FLEN/8, x2, x8, x12) + +inst_1651: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x229 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x131 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3229; op2val:0x3131; + valaddr_reg:x1; val_offset:3238*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 3238*FLEN/8, x2, x8, x12) + +inst_1652: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x229 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x131 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3229; op2val:0x3131; + valaddr_reg:x1; val_offset:3240*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 3240*FLEN/8, x2, x8, x12) + +inst_1653: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x229 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x131 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3229; op2val:0x3131; + valaddr_reg:x1; val_offset:3242*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 3242*FLEN/8, x2, x8, x12) + +inst_1654: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x229 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x131 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3229; op2val:0x3131; + valaddr_reg:x1; val_offset:3244*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 3244*FLEN/8, x2, x8, x12) + +inst_1655: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x303 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x090 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3703; op2val:0x2c90; + valaddr_reg:x1; val_offset:3246*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 3246*FLEN/8, x2, x8, x12) + +inst_1656: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x303 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x090 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3703; op2val:0x2c90; + valaddr_reg:x1; val_offset:3248*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 3248*FLEN/8, x2, x8, x12) + +inst_1657: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x303 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x090 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3703; op2val:0x2c90; + valaddr_reg:x1; val_offset:3250*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 3250*FLEN/8, x2, x8, x12) + +inst_1658: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x303 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x090 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3703; op2val:0x2c90; + valaddr_reg:x1; val_offset:3252*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 3252*FLEN/8, x2, x8, x12) + +inst_1659: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x303 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x090 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3703; op2val:0x2c90; + valaddr_reg:x1; val_offset:3254*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 3254*FLEN/8, x2, x8, x12) + +inst_1660: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d5 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x0af and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ad5; op2val:0x28af; + valaddr_reg:x1; val_offset:3256*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 3256*FLEN/8, x2, x8, x12) + +inst_1661: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d5 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x0af and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ad5; op2val:0x28af; + valaddr_reg:x1; val_offset:3258*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 3258*FLEN/8, x2, x8, x12) + +inst_1662: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d5 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x0af and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ad5; op2val:0x28af; + valaddr_reg:x1; val_offset:3260*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x1, 3260*FLEN/8, x2, x8, x12) + +inst_1663: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d5 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x0af and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ad5; op2val:0x28af; + valaddr_reg:x1; val_offset:3262*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 3262*FLEN/8, x2, x8, x12) + +inst_1664: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d5 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x0af and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ad5; op2val:0x28af; + valaddr_reg:x1; val_offset:3264*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 3264*FLEN/8, x2, x8, x12) + +inst_1665: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x1a0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x02d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x29a0; op2val:0x2d; + valaddr_reg:x1; val_offset:3266*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x1, 3266*FLEN/8, x2, x8, x12) + +inst_1666: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x1a0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x02d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x29a0; op2val:0x2d; + valaddr_reg:x1; val_offset:3268*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x1, 3268*FLEN/8, x2, x8, x12) + +inst_1667: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x148 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x006 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3548; op2val:0x6; + valaddr_reg:x1; val_offset:3270*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 3270*FLEN/8, x2, x8, x12) + +inst_1668: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2b3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x004 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x36b3; op2val:0x4; + valaddr_reg:x1; val_offset:3272*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x1, 3272*FLEN/8, x2, x8, x12) + +inst_1669: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2b3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x004 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x36b3; op2val:0x4; + valaddr_reg:x1; val_offset:3274*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x1, 3274*FLEN/8, x2, x8, x12) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(10656,32,FLEN) +NAN_BOXED(45,32,FLEN) +NAN_BOXED(10656,32,FLEN) +NAN_BOXED(10656,32,FLEN) +NAN_BOXED(10656,32,FLEN) +NAN_BOXED(45,32,FLEN) +NAN_BOXED(10656,32,FLEN) +NAN_BOXED(10656,32,FLEN) +NAN_BOXED(10656,32,FLEN) +NAN_BOXED(45,32,FLEN) +NAN_BOXED(15244,32,FLEN) +NAN_BOXED(2,32,FLEN) +NAN_BOXED(15244,32,FLEN) +NAN_BOXED(2,32,FLEN) +NAN_BOXED(15244,32,FLEN) +NAN_BOXED(2,32,FLEN) +NAN_BOXED(15244,32,FLEN) +NAN_BOXED(2,32,FLEN) +NAN_BOXED(15244,32,FLEN) +NAN_BOXED(2,32,FLEN) +NAN_BOXED(12611,32,FLEN) +NAN_BOXED(12,32,FLEN) +test_dataset_1: +NAN_BOXED(12611,32,FLEN) +NAN_BOXED(12,32,FLEN) +NAN_BOXED(12611,32,FLEN) +NAN_BOXED(12,32,FLEN) +NAN_BOXED(12611,32,FLEN) +NAN_BOXED(12,32,FLEN) +NAN_BOXED(12611,32,FLEN) +NAN_BOXED(12,32,FLEN) +NAN_BOXED(13640,32,FLEN) +NAN_BOXED(6,32,FLEN) +NAN_BOXED(13640,32,FLEN) +NAN_BOXED(6,32,FLEN) +NAN_BOXED(13640,32,FLEN) +NAN_BOXED(6,32,FLEN) +NAN_BOXED(13640,32,FLEN) +NAN_BOXED(6,32,FLEN) +NAN_BOXED(13640,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(13902,32,FLEN) +NAN_BOXED(5,32,FLEN) +NAN_BOXED(13902,32,FLEN) +NAN_BOXED(5,32,FLEN) +test_dataset_2: +NAN_BOXED(13902,32,FLEN) +NAN_BOXED(5,32,FLEN) +NAN_BOXED(13902,32,FLEN) +NAN_BOXED(5,32,FLEN) +NAN_BOXED(13902,32,FLEN) +NAN_BOXED(5,32,FLEN) +NAN_BOXED(14003,32,FLEN) +NAN_BOXED(4,32,FLEN) +NAN_BOXED(14003,32,FLEN) +NAN_BOXED(4,32,FLEN) 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256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x8_6: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x8_7: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x8_8: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x8_9: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x8_10: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x8_11: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x8_12: + .fill 220*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fmul_b9-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fmul_b9-01.S new file mode 100644 index 000000000..1d0c1b553 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fmul_b9-01.S @@ -0,0 +1,1494 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 04:50:26 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fmul.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fmul.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fmul_b9 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fmul_b9) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x6,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd != rs2, rs1==x21, rs2==x29, rd==x21,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x21; op2:x29; dest:x21; op1val:0x0; op2val:0x0; + valaddr_reg:x6; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x21, x21, x29, dyn, 0, 0, x6, 0*FLEN/8, x7, x1, x2) + +inst_1: +// rs1 == rs2 == rd, rs1==x27, rs2==x27, rd==x27,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x27; op2:x27; dest:x27; op1val:0x8000; op2val:0x8000; + valaddr_reg:x6; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x27, x27, x27, dyn, 0, 0, x6, 2*FLEN/8, x7, x1, x2) + +inst_2: +// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==x30, rs2==x8, rd==x0,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x08 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x8; dest:x0; op1val:0x3c00; op2val:0x2000; + valaddr_reg:x6; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x0, x30, x8, dyn, 0, 0, x6, 4*FLEN/8, x7, x1, x2) + +inst_3: +// rs1 == rs2 != rd, rs1==x14, rs2==x14, rd==x31,fs1 == 0 and fe1 == 0x08 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x14; op2:x14; dest:x31; op1val:0x2000; op2val:0x2000; + valaddr_reg:x6; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x31, x14, x14, dyn, 0, 0, x6, 6*FLEN/8, x7, x1, x2) + +inst_4: +// rs2 == rd != rs1, rs1==x3, rs2==x18, rd==x18,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x3; op2:x18; dest:x18; op1val:0x3c00; op2val:0x3ff8; + valaddr_reg:x6; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x18, x3, x18, dyn, 0, 0, x6, 8*FLEN/8, x7, x1, x2) + +inst_5: +// rs1==x16, rs2==x23, rd==x10,fs1 == 0 and fe1 == 0x0f and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x16; op2:x23; dest:x10; op1val:0x3ff8; op2val:0x3c00; + valaddr_reg:x6; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x10, x16, x23, dyn, 0, 0, x6, 10*FLEN/8, x7, x1, x2) + +inst_6: +// rs1==x28, rs2==x16, rd==x4,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x28; op2:x16; dest:x4; op1val:0x3c00; op2val:0x3000; + valaddr_reg:x6; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x4, x28, x16, dyn, 0, 0, x6, 12*FLEN/8, x7, x1, x2) + +inst_7: +// rs1==x5, rs2==x11, rd==x29,fs1 == 0 and fe1 == 0x0c and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x5; op2:x11; dest:x29; op1val:0x3000; op2val:0x3c00; + valaddr_reg:x6; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x29, x5, x11, dyn, 0, 0, x6, 14*FLEN/8, x7, x1, x2) + +inst_8: +// rs1==x15, rs2==x4, rd==x20,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x15; op2:x4; dest:x20; op1val:0x3c00; op2val:0x2ff8; + valaddr_reg:x6; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x20, x15, x4, dyn, 0, 0, x6, 16*FLEN/8, x7, x1, x2) + +inst_9: +// rs1==x9, rs2==x25, rd==x14,fs1 == 0 and fe1 == 0x0b and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x9; op2:x25; dest:x14; op1val:0x2ff8; op2val:0x3c00; + valaddr_reg:x6; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x14, x9, x25, dyn, 0, 0, x6, 18*FLEN/8, x7, x1, x2) + +inst_10: +// rs1==x11, rs2==x30, rd==x28,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x11; op2:x30; dest:x28; op1val:0x3c00; op2val:0x3800; + valaddr_reg:x6; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x28, x11, x30, dyn, 0, 0, x6, 20*FLEN/8, x7, x1, x2) + +inst_11: +// rs1==x20, rs2==x17, rd==x22,fs1 == 0 and fe1 == 0x0e and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x20; op2:x17; dest:x22; op1val:0x3800; op2val:0x3c00; + valaddr_reg:x6; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x22, x20, x17, dyn, 0, 0, x6, 22*FLEN/8, x7, x1, x2) + +inst_12: +// rs1==x12, rs2==x31, rd==x8,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x12; op2:x31; dest:x8; op1val:0x3c00; op2val:0x27f8; + valaddr_reg:x6; val_offset:24*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x8, x12, x31, dyn, 0, 0, x6, 24*FLEN/8, x7, x1, x2) +RVTEST_VALBASEUPD(x14,test_dataset_1) + +inst_13: +// rs1==x18, rs2==x3, rd==x13,fs1 == 0 and fe1 == 0x09 and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x18; op2:x3; dest:x13; op1val:0x27f8; op2val:0x3c00; + valaddr_reg:x14; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x13, x18, x3, dyn, 0, 0, x14, 0*FLEN/8, x15, x1, x2) + +inst_14: +// rs1==x13, rs2==x6, rd==x23,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x13; op2:x6; dest:x23; op1val:0x3c00; op2val:0x3c00; + valaddr_reg:x14; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fmul.h, x23, x13, x6, dyn, 0, 0, x14, 2*FLEN/8, x15, x1, x2) + +inst_15: +// rs1==x22, rs2==x21, rd==x5,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x08 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x22; op2:x21; dest:x5; op1val:0x3c00; op2val:0x23f8; + valaddr_reg:x14; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x11 +*/ +TEST_FPRR_OP(fmul.h, x5, x22, x21, dyn, 0, 0, x14, 4*FLEN/8, x15, x1, x11) + +inst_16: +// rs1==x2, rs2==x5, rd==x26,fs1 == 0 and fe1 == 0x08 and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x2; op2:x5; dest:x26; op1val:0x23f8; op2val:0x3c00; + valaddr_reg:x14; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x11 +*/ +TEST_FPRR_OP(fmul.h, x26, x2, x5, dyn, 0, 0, x14, 6*FLEN/8, x15, x1, x11) +RVTEST_SIGBASE(x5,signature_x5_0) + +inst_17: +// rs1==x29, rs2==x0, rd==x6,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x29; op2:x0; dest:x6; op1val:0x3c00; op2val:0x0; + valaddr_reg:x14; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x11 +*/ +TEST_FPRR_OP(fmul.h, x6, x29, x0, dyn, 0, 0, x14, 8*FLEN/8, x15, x5, x11) + +inst_18: +// rs1==x25, rs2==x1, rd==x9,fs1 == 0 and fe1 == 0x0f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x25; op2:x1; dest:x9; op1val:0x3e00; op2val:0x3c00; + valaddr_reg:x14; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x11 +*/ +TEST_FPRR_OP(fmul.h, x9, x25, x1, dyn, 0, 0, x14, 10*FLEN/8, x15, x5, x11) + +inst_19: +// rs1==x31, rs2==x12, rd==x2,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x08 and fm2 == 0x1f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x31; op2:x12; dest:x2; op1val:0x3c00; op2val:0x21f8; + valaddr_reg:x14; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x11 +*/ +TEST_FPRR_OP(fmul.h, x2, x31, x12, dyn, 0, 0, x14, 12*FLEN/8, x15, x5, x11) + +inst_20: +// rs1==x8, rs2==x26, rd==x12,fs1 == 0 and fe1 == 0x08 and fm1 == 0x1f8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x8; op2:x26; dest:x12; op1val:0x21f8; op2val:0x3c00; + valaddr_reg:x14; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x11 +*/ +TEST_FPRR_OP(fmul.h, x12, x8, x26, dyn, 0, 0, x14, 14*FLEN/8, x15, x5, x11) + +inst_21: +// rs1==x7, rs2==x10, rd==x30,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x7; op2:x10; dest:x30; op1val:0x3c00; op2val:0x3f00; + valaddr_reg:x14; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x11 +*/ +TEST_FPRR_OP(fmul.h, x30, x7, x10, dyn, 0, 0, x14, 16*FLEN/8, x15, x5, x11) + +inst_22: +// rs1==x17, rs2==x28, rd==x24,fs1 == 0 and fe1 == 0x0f and fm1 == 0x300 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x17; op2:x28; dest:x24; op1val:0x3f00; op2val:0x3c00; + valaddr_reg:x14; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x11 +*/ +TEST_FPRR_OP(fmul.h, x24, x17, x28, dyn, 0, 0, x14, 18*FLEN/8, x15, x5, x11) + +inst_23: +// rs1==x4, rs2==x20, rd==x16,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x08 and fm2 == 0x0f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x4; op2:x20; dest:x16; op1val:0x3c00; op2val:0x20f8; + valaddr_reg:x14; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x11 +*/ +TEST_FPRR_OP(fmul.h, x16, x4, x20, dyn, 0, 0, x14, 20*FLEN/8, x15, x5, x11) +RVTEST_VALBASEUPD(x4,test_dataset_2) + +inst_24: +// rs1==x26, rs2==x13, rd==x3,fs1 == 0 and fe1 == 0x08 and fm1 == 0x0f8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x26; op2:x13; dest:x3; op1val:0x20f8; op2val:0x3c00; + valaddr_reg:x4; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x11 +*/ +TEST_FPRR_OP(fmul.h, x3, x26, x13, dyn, 0, 0, x4, 0*FLEN/8, x8, x5, x11) + +inst_25: +// rs1==x24, rs2==x7, rd==x25,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x24; op2:x7; dest:x25; op1val:0x3c00; op2val:0x3f80; + valaddr_reg:x4; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x11 +*/ +TEST_FPRR_OP(fmul.h, x25, x24, x7, dyn, 0, 0, x4, 2*FLEN/8, x8, x5, x11) + +inst_26: +// rs1==x1, rs2==x2, rd==x7,fs1 == 0 and fe1 == 0x0f and fm1 == 0x380 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x1; op2:x2; dest:x7; op1val:0x3f80; op2val:0x3c00; + valaddr_reg:x4; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x11 +*/ +TEST_FPRR_OP(fmul.h, x7, x1, x2, dyn, 0, 0, x4, 4*FLEN/8, x8, x5, x11) + +inst_27: +// rs1==x6, rs2==x22, rd==x19,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x08 and fm2 == 0x078 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x6; op2:x22; dest:x19; op1val:0x3c00; op2val:0x2078; + valaddr_reg:x4; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x11 +*/ +TEST_FPRR_OP(fmul.h, x19, x6, x22, dyn, 0, 0, x4, 6*FLEN/8, x8, x5, x11) + +inst_28: +// rs1==x23, rs2==x15, rd==x17,fs1 == 0 and fe1 == 0x08 and fm1 == 0x078 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x23; op2:x15; dest:x17; op1val:0x2078; op2val:0x3c00; + valaddr_reg:x4; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x11 +*/ +TEST_FPRR_OP(fmul.h, x17, x23, x15, dyn, 0, 0, x4, 8*FLEN/8, x8, x5, x11) + +inst_29: +// rs1==x0, rs2==x19, rd==x11,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x0; op2:x19; dest:x11; op1val:0x0; op2val:0x3fc0; + valaddr_reg:x4; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x11, x0, x19, dyn, 0, 0, x4, 10*FLEN/8, x8, x5, x3) +RVTEST_SIGBASE(x2,signature_x2_0) + +inst_30: +// rs1==x10, rs2==x9, rd==x1,fs1 == 0 and fe1 == 0x0f and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x10; op2:x9; dest:x1; op1val:0x3fc0; op2val:0x3c00; + valaddr_reg:x4; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x1, x10, x9, dyn, 0, 0, x4, 12*FLEN/8, x8, x2, x3) + +inst_31: +// rs1==x19, rs2==x24, rd==x15,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x08 and fm2 == 0x038 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x19; op2:x24; dest:x15; op1val:0x3c00; op2val:0x2038; + valaddr_reg:x4; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x15, x19, x24, dyn, 0, 0, x4, 14*FLEN/8, x8, x2, x3) + +inst_32: +// fs1 == 0 and fe1 == 0x08 and fm1 == 0x038 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2038; op2val:0x3c00; + valaddr_reg:x4; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 16*FLEN/8, x8, x2, x3) + +inst_33: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3fe0; + valaddr_reg:x4; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 18*FLEN/8, x8, x2, x3) + +inst_34: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fe0; op2val:0x3c00; + valaddr_reg:x4; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 20*FLEN/8, x8, x2, x3) + +inst_35: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x08 and fm2 == 0x018 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2018; + valaddr_reg:x4; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 22*FLEN/8, x8, x2, x3) + +inst_36: +// fs1 == 0 and fe1 == 0x08 and fm1 == 0x018 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2018; op2val:0x3c00; + valaddr_reg:x4; val_offset:24*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 24*FLEN/8, x8, x2, x3) + +inst_37: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3ff0; + valaddr_reg:x4; val_offset:26*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 26*FLEN/8, x8, x2, x3) + +inst_38: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff0; op2val:0x3c00; + valaddr_reg:x4; val_offset:28*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 28*FLEN/8, x8, x2, x3) + +inst_39: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x08 and fm2 == 0x008 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2008; + valaddr_reg:x4; val_offset:30*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 30*FLEN/8, x8, x2, x3) + +inst_40: +// fs1 == 0 and fe1 == 0x08 and fm1 == 0x008 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2008; op2val:0x3c00; + valaddr_reg:x4; val_offset:32*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 32*FLEN/8, x8, x2, x3) + +inst_41: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x1b0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2db0; + valaddr_reg:x4; val_offset:34*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 34*FLEN/8, x8, x2, x3) + +inst_42: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1b0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2db0; op2val:0x3c00; + valaddr_reg:x4; val_offset:36*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 36*FLEN/8, x8, x2, x3) + +inst_43: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x368 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3b68; + valaddr_reg:x4; val_offset:38*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 38*FLEN/8, x8, x2, x3) + +inst_44: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x368 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b68; op2val:0x3c00; + valaddr_reg:x4; val_offset:40*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 40*FLEN/8, x8, x2, x3) + +inst_45: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x260 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2660; + valaddr_reg:x4; val_offset:42*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 42*FLEN/8, x8, x2, x3) + +inst_46: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x260 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2660; op2val:0x3c00; + valaddr_reg:x4; val_offset:44*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 44*FLEN/8, x8, x2, x3) + +inst_47: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x198 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3998; + valaddr_reg:x4; val_offset:46*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 46*FLEN/8, x8, x2, x3) + +inst_48: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x198 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3998; op2val:0x3c00; + valaddr_reg:x4; val_offset:48*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 48*FLEN/8, x8, x2, x3) + +inst_49: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2e8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2ee8; + valaddr_reg:x4; val_offset:50*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 50*FLEN/8, x8, x2, x3) + +inst_50: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2e8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ee8; op2val:0x3c00; + valaddr_reg:x4; val_offset:52*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 52*FLEN/8, x8, x2, x3) + +inst_51: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x110 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3110; + valaddr_reg:x4; val_offset:54*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 54*FLEN/8, x8, x2, x3) + +inst_52: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x110 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3110; op2val:0x3c00; + valaddr_reg:x4; val_offset:56*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 56*FLEN/8, x8, x2, x3) + +inst_53: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x120 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2920; + valaddr_reg:x4; val_offset:58*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 58*FLEN/8, x8, x2, x3) + +inst_54: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x120 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2920; op2val:0x3c00; + valaddr_reg:x4; val_offset:60*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 60*FLEN/8, x8, x2, x3) + +inst_55: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2d8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x36d8; + valaddr_reg:x4; val_offset:62*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 62*FLEN/8, x8, x2, x3) + +inst_56: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2d8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x36d8; op2val:0x3c00; + valaddr_reg:x4; val_offset:64*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 64*FLEN/8, x8, x2, x3) + +inst_57: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x0c8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2cc8; + valaddr_reg:x4; val_offset:66*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 66*FLEN/8, x8, x2, x3) + +inst_58: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0c8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2cc8; op2val:0x3c00; + valaddr_reg:x4; val_offset:68*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 68*FLEN/8, x8, x2, x3) + +inst_59: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x330 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3330; + valaddr_reg:x4; val_offset:70*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 70*FLEN/8, x8, x2, x3) + +inst_60: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x330 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3330; op2val:0x3c00; + valaddr_reg:x4; val_offset:72*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 72*FLEN/8, x8, x2, x3) + +inst_61: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x08 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xa000; + valaddr_reg:x4; val_offset:74*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 74*FLEN/8, x8, x2, x3) + +inst_62: +// fs1 == 1 and fe1 == 0x08 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xa000; op2val:0xbc00; + valaddr_reg:x4; val_offset:76*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 76*FLEN/8, x8, x2, x3) + +inst_63: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbff8; + valaddr_reg:x4; val_offset:78*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 78*FLEN/8, x8, x2, x3) + +inst_64: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xbff8; op2val:0xbc00; + valaddr_reg:x4; val_offset:80*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 80*FLEN/8, x8, x2, x3) + +inst_65: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb000; + valaddr_reg:x4; val_offset:82*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 82*FLEN/8, x8, x2, x3) + +inst_66: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xb000; op2val:0xbc00; + valaddr_reg:x4; val_offset:84*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 84*FLEN/8, x8, x2, x3) + +inst_67: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xaff8; + valaddr_reg:x4; val_offset:86*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 86*FLEN/8, x8, x2, x3) + +inst_68: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xaff8; op2val:0xbc00; + valaddr_reg:x4; val_offset:88*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 88*FLEN/8, x8, x2, x3) + +inst_69: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb800; + valaddr_reg:x4; val_offset:90*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 90*FLEN/8, x8, x2, x3) + +inst_70: +// fs1 == 1 and fe1 == 0x0e and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xb800; op2val:0xbc00; + valaddr_reg:x4; val_offset:92*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 92*FLEN/8, x8, x2, x3) + +inst_71: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x09 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xa7f8; + valaddr_reg:x4; val_offset:94*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 94*FLEN/8, x8, x2, x3) + +inst_72: +// fs1 == 1 and fe1 == 0x09 and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xa7f8; op2val:0xbc00; + valaddr_reg:x4; val_offset:96*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 96*FLEN/8, x8, x2, x3) + +inst_73: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbc00; + valaddr_reg:x4; val_offset:98*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 98*FLEN/8, x8, x2, x3) + +inst_74: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x08 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xa3f8; + valaddr_reg:x4; val_offset:100*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 100*FLEN/8, x8, x2, x3) + +inst_75: +// fs1 == 1 and fe1 == 0x08 and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xa3f8; op2val:0xbc00; + valaddr_reg:x4; val_offset:102*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 102*FLEN/8, x8, x2, x3) + +inst_76: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbe00; + valaddr_reg:x4; val_offset:104*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 104*FLEN/8, x8, x2, x3) + +inst_77: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xbe00; op2val:0xbc00; + valaddr_reg:x4; val_offset:106*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 106*FLEN/8, x8, x2, x3) + +inst_78: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x08 and fm2 == 0x1f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xa1f8; + valaddr_reg:x4; val_offset:108*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 108*FLEN/8, x8, x2, x3) + +inst_79: +// fs1 == 1 and fe1 == 0x08 and fm1 == 0x1f8 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xa1f8; op2val:0xbc00; + valaddr_reg:x4; val_offset:110*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 110*FLEN/8, x8, x2, x3) + +inst_80: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbf00; + valaddr_reg:x4; val_offset:112*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 112*FLEN/8, x8, x2, x3) + +inst_81: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x300 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xbf00; op2val:0xbc00; + valaddr_reg:x4; val_offset:114*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 114*FLEN/8, x8, x2, x3) + +inst_82: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x08 and fm2 == 0x0f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xa0f8; + valaddr_reg:x4; val_offset:116*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 116*FLEN/8, x8, x2, x3) + +inst_83: +// fs1 == 1 and fe1 == 0x08 and fm1 == 0x0f8 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xa0f8; op2val:0xbc00; + valaddr_reg:x4; val_offset:118*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 118*FLEN/8, x8, x2, x3) + +inst_84: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbf80; + valaddr_reg:x4; val_offset:120*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 120*FLEN/8, x8, x2, x3) + +inst_85: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x380 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xbf80; op2val:0xbc00; + valaddr_reg:x4; val_offset:122*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 122*FLEN/8, x8, x2, x3) + +inst_86: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x08 and fm2 == 0x078 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xa078; + valaddr_reg:x4; val_offset:124*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 124*FLEN/8, x8, x2, x3) + +inst_87: +// fs1 == 1 and fe1 == 0x08 and fm1 == 0x078 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xa078; op2val:0xbc00; + valaddr_reg:x4; val_offset:126*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 126*FLEN/8, x8, x2, x3) + +inst_88: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbfc0; + valaddr_reg:x4; val_offset:128*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 128*FLEN/8, x8, x2, x3) + +inst_89: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xbfc0; op2val:0xbc00; + valaddr_reg:x4; val_offset:130*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 130*FLEN/8, x8, x2, x3) + +inst_90: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x08 and fm2 == 0x038 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xa038; + valaddr_reg:x4; val_offset:132*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 132*FLEN/8, x8, x2, x3) + +inst_91: +// fs1 == 1 and fe1 == 0x08 and fm1 == 0x038 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xa038; op2val:0xbc00; + valaddr_reg:x4; val_offset:134*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 134*FLEN/8, x8, x2, x3) + +inst_92: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbfe0; + valaddr_reg:x4; val_offset:136*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 136*FLEN/8, x8, x2, x3) + +inst_93: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xbfe0; op2val:0xbc00; + valaddr_reg:x4; val_offset:138*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 138*FLEN/8, x8, x2, x3) + +inst_94: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x08 and fm2 == 0x018 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xa018; + valaddr_reg:x4; val_offset:140*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 140*FLEN/8, x8, x2, x3) + +inst_95: +// fs1 == 1 and fe1 == 0x08 and fm1 == 0x018 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xa018; op2val:0xbc00; + valaddr_reg:x4; val_offset:142*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 142*FLEN/8, x8, x2, x3) + +inst_96: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbff0; + valaddr_reg:x4; val_offset:144*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 144*FLEN/8, x8, x2, x3) + +inst_97: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xbff0; op2val:0xbc00; + valaddr_reg:x4; val_offset:146*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 146*FLEN/8, x8, x2, x3) + +inst_98: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x08 and fm2 == 0x008 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xa008; + valaddr_reg:x4; val_offset:148*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 148*FLEN/8, x8, x2, x3) + +inst_99: +// fs1 == 1 and fe1 == 0x08 and fm1 == 0x008 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xa008; op2val:0xbc00; + valaddr_reg:x4; val_offset:150*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 150*FLEN/8, x8, x2, x3) + +inst_100: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1b0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xadb0; + valaddr_reg:x4; val_offset:152*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 152*FLEN/8, x8, x2, x3) + +inst_101: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x1b0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xadb0; op2val:0xbc00; + valaddr_reg:x4; val_offset:154*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 154*FLEN/8, x8, x2, x3) + +inst_102: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x368 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbb68; + valaddr_reg:x4; val_offset:156*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 156*FLEN/8, x8, x2, x3) + +inst_103: +// fs1 == 1 and fe1 == 0x0e and fm1 == 0x368 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xbb68; op2val:0xbc00; + valaddr_reg:x4; val_offset:158*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 158*FLEN/8, x8, x2, x3) + +inst_104: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x09 and fm2 == 0x260 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xa660; + valaddr_reg:x4; val_offset:160*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 160*FLEN/8, x8, x2, x3) + +inst_105: +// fs1 == 1 and fe1 == 0x09 and fm1 == 0x260 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xa660; op2val:0xbc00; + valaddr_reg:x4; val_offset:162*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 162*FLEN/8, x8, x2, x3) + +inst_106: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x198 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb998; + valaddr_reg:x4; val_offset:164*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 164*FLEN/8, x8, x2, x3) + +inst_107: +// fs1 == 1 and fe1 == 0x0e and fm1 == 0x198 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xb998; op2val:0xbc00; + valaddr_reg:x4; val_offset:166*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 166*FLEN/8, x8, x2, x3) + +inst_108: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x2e8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xaee8; + valaddr_reg:x4; val_offset:168*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 168*FLEN/8, x8, x2, x3) + +inst_109: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x2e8 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xaee8; op2val:0xbc00; + valaddr_reg:x4; val_offset:170*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 170*FLEN/8, x8, x2, x3) + +inst_110: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x110 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb110; + valaddr_reg:x4; val_offset:172*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 172*FLEN/8, x8, x2, x3) + +inst_111: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x110 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xb110; op2val:0xbc00; + valaddr_reg:x4; val_offset:174*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 174*FLEN/8, x8, x2, x3) + +inst_112: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x120 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xa920; + valaddr_reg:x4; val_offset:176*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 176*FLEN/8, x8, x2, x3) + +inst_113: +// fs1 == 1 and fe1 == 0x0a and fm1 == 0x120 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xa920; op2val:0xbc00; + valaddr_reg:x4; val_offset:178*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 178*FLEN/8, x8, x2, x3) + +inst_114: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2d8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb6d8; + valaddr_reg:x4; val_offset:180*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 180*FLEN/8, x8, x2, x3) + +inst_115: +// fs1 == 1 and fe1 == 0x0d and fm1 == 0x2d8 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xb6d8; op2val:0xbc00; + valaddr_reg:x4; val_offset:182*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 182*FLEN/8, x8, x2, x3) + +inst_116: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x0c8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xacc8; + valaddr_reg:x4; val_offset:184*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 184*FLEN/8, x8, x2, x3) + +inst_117: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x0c8 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xacc8; op2val:0xbc00; + valaddr_reg:x4; val_offset:186*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 186*FLEN/8, x8, x2, x3) + +inst_118: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x330 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb330; + valaddr_reg:x4; val_offset:188*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 188*FLEN/8, x8, x2, x3) + +inst_119: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x330 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xb330; op2val:0xbc00; + valaddr_reg:x4; val_offset:190*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 190*FLEN/8, x8, x2, x3) + +inst_120: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x0; + valaddr_reg:x4; val_offset:192*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 192*FLEN/8, x8, x2, x3) + +inst_121: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x1; + valaddr_reg:x4; val_offset:194*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 194*FLEN/8, x8, x2, x3) + +inst_122: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8000; + valaddr_reg:x4; val_offset:196*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 196*FLEN/8, x8, x2, x3) + +inst_123: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8001; + valaddr_reg:x4; val_offset:198*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 198*FLEN/8, x8, x2, x3) + +inst_124: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x0; + valaddr_reg:x4; val_offset:200*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 200*FLEN/8, x8, x2, x3) + +inst_125: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x3ff; + valaddr_reg:x4; val_offset:202*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 202*FLEN/8, x8, x2, x3) + +inst_126: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8000; + valaddr_reg:x4; val_offset:204*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 204*FLEN/8, x8, x2, x3) + +inst_127: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x83ff; + valaddr_reg:x4; val_offset:206*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 206*FLEN/8, x8, x2, x3) + +inst_128: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x0; + valaddr_reg:x4; val_offset:208*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 208*FLEN/8, x8, x2, x3) + +inst_129: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x400; + valaddr_reg:x4; val_offset:210*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 210*FLEN/8, x8, x2, x3) + +inst_130: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8000; + valaddr_reg:x4; val_offset:212*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 212*FLEN/8, x8, x2, x3) + +inst_131: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8400; + valaddr_reg:x4; val_offset:214*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 214*FLEN/8, x8, x2, x3) + +inst_132: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7bff; + valaddr_reg:x4; val_offset:216*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 216*FLEN/8, x8, x2, x3) + +inst_133: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfbff; + valaddr_reg:x4; val_offset:218*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 218*FLEN/8, x8, x2, x3) + +inst_134: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8000; + valaddr_reg:x4; val_offset:220*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 220*FLEN/8, x8, x2, x3) + +inst_135: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x08 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2000; + valaddr_reg:x4; val_offset:222*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 222*FLEN/8, x8, x2, x3) + +inst_136: +// fs1 == 0 and fe1 == 0x08 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x2000; op2val:0x3c00; + valaddr_reg:x4; val_offset:224*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 224*FLEN/8, x8, x2, x3) + +inst_137: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3e00; + valaddr_reg:x4; val_offset:226*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 226*FLEN/8, x8, x2, x3) + +inst_138: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3fc0; + valaddr_reg:x4; val_offset:228*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 228*FLEN/8, x8, x2, x3) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(15360,32,FLEN) +NAN_BOXED(8192,32,FLEN) +NAN_BOXED(8192,32,FLEN) +NAN_BOXED(8192,32,FLEN) +NAN_BOXED(15360,32,FLEN) +NAN_BOXED(16376,32,FLEN) +NAN_BOXED(16376,32,FLEN) +NAN_BOXED(15360,32,FLEN) +NAN_BOXED(15360,32,FLEN) +NAN_BOXED(12288,32,FLEN) +NAN_BOXED(12288,32,FLEN) +NAN_BOXED(15360,32,FLEN) +NAN_BOXED(15360,32,FLEN) +NAN_BOXED(12280,32,FLEN) +NAN_BOXED(12280,32,FLEN) +NAN_BOXED(15360,32,FLEN) +NAN_BOXED(15360,32,FLEN) +NAN_BOXED(14336,32,FLEN) +NAN_BOXED(14336,32,FLEN) +NAN_BOXED(15360,32,FLEN) +NAN_BOXED(15360,32,FLEN) +NAN_BOXED(10232,32,FLEN) +test_dataset_1: +NAN_BOXED(10232,32,FLEN) +NAN_BOXED(15360,32,FLEN) +NAN_BOXED(15360,32,FLEN) +NAN_BOXED(15360,32,FLEN) +NAN_BOXED(15360,32,FLEN) +NAN_BOXED(9208,32,FLEN) +NAN_BOXED(9208,32,FLEN) +NAN_BOXED(15360,32,FLEN) +NAN_BOXED(15360,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(15872,32,FLEN) +NAN_BOXED(15360,32,FLEN) +NAN_BOXED(15360,32,FLEN) +NAN_BOXED(8696,32,FLEN) +NAN_BOXED(8696,32,FLEN) +NAN_BOXED(15360,32,FLEN) +NAN_BOXED(15360,32,FLEN) +NAN_BOXED(16128,32,FLEN) +NAN_BOXED(16128,32,FLEN) +NAN_BOXED(15360,32,FLEN) +NAN_BOXED(15360,32,FLEN) +NAN_BOXED(8440,32,FLEN) +test_dataset_2: +NAN_BOXED(8440,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(16256,16,FLEN) +NAN_BOXED(16256,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(8312,16,FLEN) +NAN_BOXED(8312,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(16320,16,FLEN) +NAN_BOXED(16320,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(8248,16,FLEN) +NAN_BOXED(8248,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(16352,16,FLEN) +NAN_BOXED(16352,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(8216,16,FLEN) +NAN_BOXED(8216,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(16368,16,FLEN) +NAN_BOXED(16368,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(8200,16,FLEN) +NAN_BOXED(8200,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(11696,16,FLEN) +NAN_BOXED(11696,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15208,16,FLEN) +NAN_BOXED(15208,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(9824,16,FLEN) +NAN_BOXED(9824,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(14744,16,FLEN) +NAN_BOXED(14744,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(12008,16,FLEN) +NAN_BOXED(12008,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(12560,16,FLEN) +NAN_BOXED(12560,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(10528,16,FLEN) +NAN_BOXED(10528,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(14040,16,FLEN) +NAN_BOXED(14040,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(11464,16,FLEN) +NAN_BOXED(11464,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(13104,16,FLEN) +NAN_BOXED(13104,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(40960,16,FLEN) +NAN_BOXED(40960,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(49144,16,FLEN) +NAN_BOXED(49144,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(45056,16,FLEN) +NAN_BOXED(45056,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(45048,16,FLEN) +NAN_BOXED(45048,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(47104,16,FLEN) +NAN_BOXED(47104,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(43000,16,FLEN) +NAN_BOXED(43000,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(41976,16,FLEN) +NAN_BOXED(41976,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48640,16,FLEN) +NAN_BOXED(48640,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(41464,16,FLEN) +NAN_BOXED(41464,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48896,16,FLEN) +NAN_BOXED(48896,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(41208,16,FLEN) +NAN_BOXED(41208,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(49024,16,FLEN) +NAN_BOXED(49024,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(41080,16,FLEN) +NAN_BOXED(41080,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(49088,16,FLEN) +NAN_BOXED(49088,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(41016,16,FLEN) +NAN_BOXED(41016,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(49120,16,FLEN) +NAN_BOXED(49120,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(40984,16,FLEN) +NAN_BOXED(40984,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(49136,16,FLEN) +NAN_BOXED(49136,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(40968,16,FLEN) +NAN_BOXED(40968,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(44464,16,FLEN) +NAN_BOXED(44464,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(47976,16,FLEN) +NAN_BOXED(47976,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(42592,16,FLEN) +NAN_BOXED(42592,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(47512,16,FLEN) +NAN_BOXED(47512,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(44776,16,FLEN) +NAN_BOXED(44776,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(45328,16,FLEN) +NAN_BOXED(45328,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(43296,16,FLEN) +NAN_BOXED(43296,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(46808,16,FLEN) +NAN_BOXED(46808,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(44232,16,FLEN) +NAN_BOXED(44232,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(45872,16,FLEN) +NAN_BOXED(45872,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(8192,16,FLEN) +NAN_BOXED(8192,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15872,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(16320,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 34*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x5_0: + .fill 26*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_0: + .fill 218*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fnmadd_b14-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fnmadd_b14-01.S new file mode 100644 index 000000000..f7c20bce7 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fnmadd_b14-01.S @@ -0,0 +1,566 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 06:03:37 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fnmadd.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fnmadd.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fnmadd_b14 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fnmadd_b14) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x6,test_dataset_0) +RVTEST_SIGBASE(x4,signature_x4_1) + +inst_0: +// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==x27, rs2==x29, rs3==x27, rd==x26,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x394 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x33c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x27; op2:x29; op3:x27; dest:x26; op1val:0x7ba5; op2val:0x7b94; +op3val:0x7ba5; valaddr_reg:x6; val_offset:0*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x26, x27, x29, x27, dyn, 0, 0, x6, 0*FLEN/8, x14, x4, x5) + +inst_1: +// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==x3, rs2==x15, rs3==x15, rd==x22,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x394 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x33c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x3; op2:x15; op3:x15; dest:x22; op1val:0x7ba5; op2val:0x7b94; +op3val:0x7b94; valaddr_reg:x6; val_offset:3*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x22, x3, x15, x15, dyn, 0, 0, x6, 3*FLEN/8, x14, x4, x5) + +inst_2: +// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==x22, rs2==x16, rs3==x26, rd==x31,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x394 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x33c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x22; op2:x16; op3:x26; dest:x31; op1val:0x7ba5; op2val:0x7b94; +op3val:0x373c; valaddr_reg:x6; val_offset:6*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x22, x16, x26, dyn, 0, 0, x6, 6*FLEN/8, x14, x4, x5) + +inst_3: +// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==x0, rs2==x18, rs3==x30, rd==x18,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x394 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x33c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x0; op2:x18; op3:x30; dest:x18; op1val:0x0; op2val:0x7b94; +op3val:0x3b3c; valaddr_reg:x6; val_offset:9*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x18, x0, x18, x30, dyn, 0, 0, x6, 9*FLEN/8, x14, x4, x5) + +inst_4: +// rs1 == rd == rs3 != rs2, rs1==x25, rs2==x30, rs3==x25, rd==x25,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x394 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x33c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x25; op2:x30; op3:x25; dest:x25; op1val:0x7ba5; op2val:0x7b94; +op3val:0x7ba5; valaddr_reg:x6; val_offset:12*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x25, x25, x30, x25, dyn, 0, 0, x6, 12*FLEN/8, x14, x4, x5) + +inst_5: +// rs1 == rs2 == rs3 != rd, rs1==x13, rs2==x13, rs3==x13, rd==x0,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x394 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x33c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x13; op2:x13; op3:x13; dest:x0; op1val:0x7ba5; op2val:0x7ba5; +op3val:0x7ba5; valaddr_reg:x6; val_offset:15*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x0, x13, x13, x13, dyn, 0, 0, x6, 15*FLEN/8, x14, x4, x5) + +inst_6: +// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==x26, rs2==x26, rs3==x5, rd==x12,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x394 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x33c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x26; op2:x26; op3:x5; dest:x12; op1val:0x7ba5; op2val:0x7ba5; +op3val:0x473c; valaddr_reg:x6; val_offset:18*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x12, x26, x26, x5, dyn, 0, 0, x6, 18*FLEN/8, x14, x4, x5) + +inst_7: +// rd == rs2 == rs3 != rs1, rs1==x9, rs2==x10, rs3==x10, rd==x10,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x394 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x33c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x9; op2:x10; op3:x10; dest:x10; op1val:0x7ba5; op2val:0x7b94; +op3val:0x7b94; valaddr_reg:x6; val_offset:21*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x10, x9, x10, x10, dyn, 0, 0, x6, 21*FLEN/8, x14, x4, x5) + +inst_8: +// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==x17, rs2==x0, rs3==x23, rd==x17,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x394 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x33c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x17; op2:x0; op3:x23; dest:x17; op1val:0x7ba5; op2val:0x0; +op3val:0x4f3c; valaddr_reg:x6; val_offset:24*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x17, x17, x0, x23, dyn, 0, 0, x6, 24*FLEN/8, x14, x4, x5) + +inst_9: +// rs1 == rs2 == rs3 == rd, rs1==x1, rs2==x1, rs3==x1, rd==x1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x394 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x33c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x1; op2:x1; op3:x1; dest:x1; op1val:0x7ba5; op2val:0x7ba5; +op3val:0x7ba5; valaddr_reg:x6; val_offset:27*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x1, x1, x1, x1, dyn, 0, 0, x6, 27*FLEN/8, x14, x4, x5) + +inst_10: +// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==x8, rs2==x19, rs3==x3, rd==x3,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x394 and fs3 == 0 and fe3 == 0x15 and fm3 == 0x33c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x8; op2:x19; op3:x3; dest:x3; op1val:0x7ba5; op2val:0x7b94; +op3val:0x573c; valaddr_reg:x6; val_offset:30*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x3, x8, x19, x3, dyn, 0, 0, x6, 30*FLEN/8, x14, x4, x5) + +inst_11: +// rs1 == rs2 == rd != rs3, rs1==x7, rs2==x7, rs3==x24, rd==x7,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x394 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x33c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x7; op2:x7; op3:x24; dest:x7; op1val:0x7ba5; op2val:0x7ba5; +op3val:0x5b3c; valaddr_reg:x6; val_offset:33*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x7, x7, x7, x24, dyn, 0, 0, x6, 33*FLEN/8, x14, x4, x5) + +inst_12: +// rs1==x19, rs2==x3, rs3==x16, rd==x2,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x394 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x33c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x19; op2:x3; op3:x16; dest:x2; op1val:0x7ba5; op2val:0x7b94; +op3val:0x5f3c; valaddr_reg:x6; val_offset:36*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x2, x19, x3, x16, dyn, 0, 0, x6, 36*FLEN/8, x14, x4, x5) + +inst_13: +// rs1==x11, rs2==x21, rs3==x14, rd==x13,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x394 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x33c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x11; op2:x21; op3:x14; dest:x13; op1val:0x7ba5; op2val:0x7b94; +op3val:0x633c; valaddr_reg:x6; val_offset:39*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x13, x11, x21, x14, dyn, 0, 0, x6, 39*FLEN/8, x14, x4, x5) +RVTEST_VALBASEUPD(x7,test_dataset_1) + +inst_14: +// rs1==x6, rs2==x20, rs3==x0, rd==x27,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x394 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x33c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x6; op2:x20; op3:x0; dest:x27; op1val:0x7ba5; op2val:0x7b94; +op3val:0x0; valaddr_reg:x7; val_offset:0*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x27, x6, x20, x0, dyn, 0, 0, x7, 0*FLEN/8, x10, x4, x5) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_15: +// rs1==x28, rs2==x25, rs3==x17, rd==x15,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x394 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x33c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x28; op2:x25; op3:x17; dest:x15; op1val:0x7ba5; op2val:0x7b94; +op3val:0x6b3c; valaddr_reg:x7; val_offset:3*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x15, x28, x25, x17, dyn, 0, 0, x7, 3*FLEN/8, x10, x1, x3) + +inst_16: +// rs1==x14, rs2==x11, rs3==x22, rd==x20,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x394 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x33c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x14; op2:x11; op3:x22; dest:x20; op1val:0x7ba5; op2val:0x7b94; +op3val:0x6f3c; valaddr_reg:x7; val_offset:6*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x20, x14, x11, x22, dyn, 0, 0, x7, 6*FLEN/8, x10, x1, x3) + +inst_17: +// rs1==x15, rs2==x22, rs3==x11, rd==x6,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x394 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x33c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x15; op2:x22; op3:x11; dest:x6; op1val:0x7ba5; op2val:0x7b94; +op3val:0x733c; valaddr_reg:x7; val_offset:9*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x6, x15, x22, x11, dyn, 0, 0, x7, 9*FLEN/8, x10, x1, x3) + +inst_18: +// rs1==x16, rs2==x24, rs3==x12, rd==x28,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x394 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x33c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x16; op2:x24; op3:x12; dest:x28; op1val:0x7ba5; op2val:0x7b94; +op3val:0x773c; valaddr_reg:x7; val_offset:12*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x28, x16, x24, x12, dyn, 0, 0, x7, 12*FLEN/8, x10, x1, x3) + +inst_19: +// rs1==x23, rs2==x2, rs3==x6, rd==x29,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x394 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x33c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x23; op2:x2; op3:x6; dest:x29; op1val:0x7ba5; op2val:0x7b94; +op3val:0x7b3c; valaddr_reg:x7; val_offset:15*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x29, x23, x2, x6, dyn, 0, 0, x7, 15*FLEN/8, x10, x1, x3) + +inst_20: +// rs1==x21, rs2==x27, rs3==x20, rd==x14,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x394 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x21; op2:x27; op3:x20; dest:x14; op1val:0x7ba5; op2val:0x7b94; +op3val:0x7bff; valaddr_reg:x7; val_offset:18*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x14, x21, x27, x20, dyn, 0, 0, x7, 18*FLEN/8, x10, x1, x3) + +inst_21: +// rs1==x12, rs2==x9, rs3==x2, rd==x16, +/* opcode: fnmadd.h ; op1:x12; op2:x9; op3:x2; dest:x16; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x7; val_offset:21*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x16, x12, x9, x2, dyn, 0, 0, x7, 21*FLEN/8, x10, x1, x3) + +inst_22: +// rs1==x4, rs2==x8, rs3==x29, rd==x30, +/* opcode: fnmadd.h ; op1:x4; op2:x8; op3:x29; dest:x30; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x7; val_offset:24*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x30, x4, x8, x29, dyn, 0, 0, x7, 24*FLEN/8, x10, x1, x3) + +inst_23: +// rs1==x31, rs2==x23, rs3==x28, rd==x24, +/* opcode: fnmadd.h ; op1:x31; op2:x23; op3:x28; dest:x24; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x7; val_offset:27*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x24, x31, x23, x28, dyn, 0, 0, x7, 27*FLEN/8, x10, x1, x3) +RVTEST_VALBASEUPD(x13,test_dataset_2) + +inst_24: +// rs1==x2, rs2==x12, rs3==x21, rd==x11, +/* opcode: fnmadd.h ; op1:x2; op2:x12; op3:x21; dest:x11; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x13; val_offset:0*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x11, x2, x12, x21, dyn, 0, 0, x13, 0*FLEN/8, x19, x1, x3) + +inst_25: +// rs1==x18, rs2==x17, rs3==x19, rd==x4, +/* opcode: fnmadd.h ; op1:x18; op2:x17; op3:x19; dest:x4; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x13; val_offset:3*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x4, x18, x17, x19, dyn, 0, 0, x13, 3*FLEN/8, x19, x1, x3) + +inst_26: +// rs1==x10, rs2==x31, rs3==x8, rd==x9, +/* opcode: fnmadd.h ; op1:x10; op2:x31; op3:x8; dest:x9; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x13; val_offset:6*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x9, x10, x31, x8, dyn, 0, 0, x13, 6*FLEN/8, x19, x1, x3) + +inst_27: +// rs1==x20, rs2==x28, rs3==x7, rd==x8, +/* opcode: fnmadd.h ; op1:x20; op2:x28; op3:x7; dest:x8; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x13; val_offset:9*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x8, x20, x28, x7, dyn, 0, 0, x13, 9*FLEN/8, x19, x1, x7) + +inst_28: +// rs1==x24, rs2==x4, rs3==x31, rd==x5, +/* opcode: fnmadd.h ; op1:x24; op2:x4; op3:x31; dest:x5; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x13; val_offset:12*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x5, x24, x4, x31, dyn, 0, 0, x13, 12*FLEN/8, x19, x1, x7) +RVTEST_SIGBASE(x3,signature_x3_0) + +inst_29: +// rs1==x30, rs2==x14, rs3==x18, rd==x23, +/* opcode: fnmadd.h ; op1:x30; op2:x14; op3:x18; dest:x23; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x13; val_offset:15*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x23, x30, x14, x18, dyn, 0, 0, x13, 15*FLEN/8, x19, x3, x7) + +inst_30: +// rs1==x29, rs2==x6, rs3==x4, rd==x21, +/* opcode: fnmadd.h ; op1:x29; op2:x6; op3:x4; dest:x21; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x13; val_offset:18*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x21, x29, x6, x4, dyn, 0, 0, x13, 18*FLEN/8, x19, x3, x7) + +inst_31: +// rs1==x5, +/* opcode: fnmadd.h ; op1:x5; op2:x20; op3:x7; dest:x2; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x13; val_offset:21*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x2, x5, x20, x7, dyn, 0, 0, x13, 21*FLEN/8, x19, x3, x7) + +inst_32: +// rs2==x5, +/* opcode: fnmadd.h ; op1:x21; op2:x5; op3:x29; dest:x1; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x13; val_offset:24*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x1, x21, x5, x29, dyn, 0, 0, x13, 24*FLEN/8, x19, x3, x7) + +inst_33: +// rs3==x9, +/* opcode: fnmadd.h ; op1:x16; op2:x15; op3:x9; dest:x23; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x13; val_offset:27*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x23, x16, x15, x9, dyn, 0, 0, x13, 27*FLEN/8, x19, x3, x7) +RVTEST_VALBASEUPD(x1,test_dataset_3) + +inst_34: +// rd==x19, +/* opcode: fnmadd.h ; op1:x5; op2:x22; op3:x4; dest:x19; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x1; val_offset:0*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x19, x5, x22, x4, dyn, 0, 0, x1, 0*FLEN/8, x2, x3, x7) + +inst_35: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x394 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x33c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ba5; op2val:0x7b94; +op3val:0x2f3c; valaddr_reg:x1; val_offset:3*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3*FLEN/8, x2, x3, x7) + +inst_36: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x394 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x33c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ba5; op2val:0x7b94; +op3val:0x333c; valaddr_reg:x1; val_offset:6*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 6*FLEN/8, x2, x3, x7) + +inst_37: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x394 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x33c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ba5; op2val:0x7b94; +op3val:0x3b3c; valaddr_reg:x1; val_offset:9*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 9*FLEN/8, x2, x3, x7) + +inst_38: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x394 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x33c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ba5; op2val:0x7b94; +op3val:0x3f3c; valaddr_reg:x1; val_offset:12*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 12*FLEN/8, x2, x3, x7) + +inst_39: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x394 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x33c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ba5; op2val:0x7b94; +op3val:0x433c; valaddr_reg:x1; val_offset:15*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 15*FLEN/8, x2, x3, x7) + +inst_40: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x394 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x33c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ba5; op2val:0x7b94; +op3val:0x473c; valaddr_reg:x1; val_offset:18*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 18*FLEN/8, x2, x3, x7) + +inst_41: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x394 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x33c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ba5; op2val:0x7b94; +op3val:0x4b3c; valaddr_reg:x1; val_offset:21*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 21*FLEN/8, x2, x3, x7) + +inst_42: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x394 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x33c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ba5; op2val:0x7b94; +op3val:0x4f3c; valaddr_reg:x1; val_offset:24*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 24*FLEN/8, x2, x3, x7) + +inst_43: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x394 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x33c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ba5; op2val:0x7b94; +op3val:0x533c; valaddr_reg:x1; val_offset:27*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 27*FLEN/8, x2, x3, x7) + +inst_44: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x394 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x33c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ba5; op2val:0x7b94; +op3val:0x5b3c; valaddr_reg:x1; val_offset:30*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 30*FLEN/8, x2, x3, x7) + +inst_45: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x394 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x33c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ba5; op2val:0x7b94; +op3val:0x673c; valaddr_reg:x1; val_offset:33*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 33*FLEN/8, x2, x3, x7) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(31636,32,FLEN) +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(31636,32,FLEN) +NAN_BOXED(31636,32,FLEN) +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(31636,32,FLEN) +NAN_BOXED(14140,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31636,32,FLEN) +NAN_BOXED(15164,32,FLEN) +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(31636,32,FLEN) +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(18236,32,FLEN) +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(31636,32,FLEN) +NAN_BOXED(31636,32,FLEN) +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(20284,32,FLEN) +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(31636,32,FLEN) +NAN_BOXED(22332,32,FLEN) +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(23356,32,FLEN) +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(31636,32,FLEN) +NAN_BOXED(24380,32,FLEN) +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(31636,32,FLEN) +NAN_BOXED(25404,32,FLEN) +test_dataset_1: +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(31636,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(31636,32,FLEN) +NAN_BOXED(27452,32,FLEN) +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(31636,32,FLEN) +NAN_BOXED(28476,32,FLEN) +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(31636,32,FLEN) +NAN_BOXED(29500,32,FLEN) +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(31636,32,FLEN) +NAN_BOXED(30524,32,FLEN) +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(31636,32,FLEN) +NAN_BOXED(31548,32,FLEN) +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(31636,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +test_dataset_2: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +test_dataset_3: +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31653,16,FLEN) +NAN_BOXED(31636,16,FLEN) +NAN_BOXED(12092,16,FLEN) +NAN_BOXED(31653,16,FLEN) +NAN_BOXED(31636,16,FLEN) +NAN_BOXED(13116,16,FLEN) +NAN_BOXED(31653,16,FLEN) +NAN_BOXED(31636,16,FLEN) +NAN_BOXED(15164,16,FLEN) +NAN_BOXED(31653,16,FLEN) +NAN_BOXED(31636,16,FLEN) +NAN_BOXED(16188,16,FLEN) +NAN_BOXED(31653,16,FLEN) +NAN_BOXED(31636,16,FLEN) +NAN_BOXED(17212,16,FLEN) +NAN_BOXED(31653,16,FLEN) +NAN_BOXED(31636,16,FLEN) +NAN_BOXED(18236,16,FLEN) +NAN_BOXED(31653,16,FLEN) +NAN_BOXED(31636,16,FLEN) +NAN_BOXED(19260,16,FLEN) +NAN_BOXED(31653,16,FLEN) +NAN_BOXED(31636,16,FLEN) +NAN_BOXED(20284,16,FLEN) +NAN_BOXED(31653,16,FLEN) +NAN_BOXED(31636,16,FLEN) +NAN_BOXED(21308,16,FLEN) +NAN_BOXED(31653,16,FLEN) +NAN_BOXED(31636,16,FLEN) +NAN_BOXED(23356,16,FLEN) +NAN_BOXED(31653,16,FLEN) +NAN_BOXED(31636,16,FLEN) +NAN_BOXED(26428,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x4_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x4_1: + .fill 30*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_0: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x3_0: + .fill 34*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fnmadd_b16-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fnmadd_b16-01.S new file mode 100644 index 000000000..b6df41757 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fnmadd_b16-01.S @@ -0,0 +1,2251 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 06:03:37 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fnmadd.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fnmadd.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fnmadd_b16 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fnmadd_b16) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x2,test_dataset_0) +RVTEST_SIGBASE(x12,signature_x12_1) + +inst_0: +// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==x25, rs2==x13, rs3==x25, rd==x31,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x394 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x25; op2:x13; op3:x25; dest:x31; op1val:0x7ba5; op2val:0x7b94; +op3val:0x7ba5; valaddr_reg:x2; val_offset:0*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x25, x13, x25, dyn, 0, 0, x2, 0*FLEN/8, x14, x12, x4) + +inst_1: +// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==x8, rs2==x28, rs3==x28, rd==x11,fs1 == 0 and fe1 == 0x1b and fm1 == 0x16d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ae and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x8; op2:x28; op3:x28; dest:x11; op1val:0x6d6d; op2val:0x7aae; +op3val:0x7aae; valaddr_reg:x2; val_offset:3*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x11, x8, x28, x28, dyn, 0, 0, x2, 3*FLEN/8, x14, x12, x4) + +inst_2: +// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==x9, rs2==x23, rs3==x10, rd==x13,fs1 == 0 and fe1 == 0x1e and fm1 == 0x15a and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0ed and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x9; op2:x23; op3:x10; dest:x13; op1val:0x795a; op2val:0x74ed; +op3val:0xfbff; valaddr_reg:x2; val_offset:6*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x13, x9, x23, x10, dyn, 0, 0, x2, 6*FLEN/8, x14, x12, x4) + +inst_3: +// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==x5, rs2==x27, rs3==x26, rd==x27,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0da and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0a5 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x5; op2:x27; op3:x26; dest:x27; op1val:0x78da; op2val:0x78a5; +op3val:0xfbff; valaddr_reg:x2; val_offset:9*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x27, x5, x27, x26, dyn, 0, 0, x2, 9*FLEN/8, x14, x12, x4) + +inst_4: +// rs1 == rd == rs3 != rs2, rs1==x24, rs2==x3, rs3==x24, rd==x24,fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x24b and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x24; op2:x3; op3:x24; dest:x24; op1val:0x76e3; op2val:0x764b; +op3val:0x76e3; valaddr_reg:x2; val_offset:12*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x24, x24, x3, x24, dyn, 0, 0, x2, 12*FLEN/8, x14, x12, x4) + +inst_5: +// rs1 == rs2 == rs3 != rd, rs1==x30, rs2==x30, rs3==x30, rd==x10,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x397 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x30; op3:x30; dest:x10; op1val:0x7bf4; op2val:0x7bf4; +op3val:0x7bf4; valaddr_reg:x2; val_offset:15*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x10, x30, x30, x30, dyn, 0, 0, x2, 15*FLEN/8, x14, x12, x4) + +inst_6: +// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==x15, rs2==x15, rs3==x22, rd==x1,fs1 == 0 and fe1 == 0x1d and fm1 == 0x31d and fs2 == 0 and fe2 == 0x1d and fm2 == 0x04a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x15; op2:x15; op3:x22; dest:x1; op1val:0x771d; op2val:0x771d; +op3val:0xfbff; valaddr_reg:x2; val_offset:18*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x1, x15, x15, x22, dyn, 0, 0, x2, 18*FLEN/8, x14, x12, x4) + +inst_7: +// rd == rs2 == rs3 != rs1, rs1==x7, rs2==x18, rs3==x18, rd==x18,fs1 == 0 and fe1 == 0x19 and fm1 == 0x305 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x36f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x7; op2:x18; op3:x18; dest:x18; op1val:0x6705; op2val:0x776f; +op3val:0x776f; valaddr_reg:x2; val_offset:21*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x18, x7, x18, x18, dyn, 0, 0, x2, 21*FLEN/8, x14, x12, x4) + +inst_8: +// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==x16, rs2==x6, rs3==x12, rd==x16,fs1 == 0 and fe1 == 0x1d and fm1 == 0x213 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x321 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x16; op2:x6; op3:x12; dest:x16; op1val:0x7613; op2val:0x7b21; +op3val:0xfbff; valaddr_reg:x2; val_offset:24*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x16, x16, x6, x12, dyn, 0, 0, x2, 24*FLEN/8, x14, x12, x4) + +inst_9: +// rs1 == rs2 == rs3 == rd, rs1==x19, rs2==x19, rs3==x19, rd==x19,fs1 == 0 and fe1 == 0x1e and fm1 == 0x07b and fs2 == 0 and fe2 == 0x1c and fm2 == 0x38d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x19; op2:x19; op3:x19; dest:x19; op1val:0x787b; op2val:0x787b; +op3val:0x787b; valaddr_reg:x2; val_offset:27*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x19, x19, x19, x19, dyn, 0, 0, x2, 27*FLEN/8, x14, x12, x4) + +inst_10: +// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==x28, rs2==x11, rs3==x21, rd==x21,fs1 == 0 and fe1 == 0x1d and fm1 == 0x133 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x05f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x28; op2:x11; op3:x21; dest:x21; op1val:0x7533; op2val:0x705f; +op3val:0xfbff; valaddr_reg:x2; val_offset:30*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x21, x28, x11, x21, dyn, 0, 0, x2, 30*FLEN/8, x14, x12, x4) +RVTEST_VALBASEUPD(x1,test_dataset_1) + +inst_11: +// rs1 == rs2 == rd != rs3, rs1==x17, rs2==x17, rs3==x5, rd==x17,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x164 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x17; op2:x17; op3:x5; dest:x17; op1val:0x7bfc; op2val:0x7bfc; +op3val:0xfbff; valaddr_reg:x1; val_offset:0*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x17, x17, x17, x5, dyn, 0, 0, x1, 0*FLEN/8, x3, x12, x4) + +inst_12: +// rs1==x18, rs2==x16, rs3==x9, rd==x5,fs1 == 0 and fe1 == 0x1e and fm1 == 0x325 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x25e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x18; op2:x16; op3:x9; dest:x5; op1val:0x7b25; op2val:0x7a5e; +op3val:0xfbff; valaddr_reg:x1; val_offset:3*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x5, x18, x16, x9, dyn, 0, 0, x1, 3*FLEN/8, x3, x12, x4) + +inst_13: +// rs1==x31, rs2==x10, rs3==x15, rd==x2,fs1 == 0 and fe1 == 0x1e and fm1 == 0x33f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x219 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x31; op2:x10; op3:x15; dest:x2; op1val:0x7b3f; op2val:0x7a19; +op3val:0xfbff; valaddr_reg:x1; val_offset:6*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x2, x31, x10, x15, dyn, 0, 0, x1, 6*FLEN/8, x3, x12, x4) + +inst_14: +// rs1==x4, rs2==x2, rs3==x6, rd==x8,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3d8 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x4; op2:x2; op3:x6; dest:x8; op1val:0x75a8; op2val:0x7bd8; +op3val:0xfbff; valaddr_reg:x1; val_offset:9*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x8, x4, x2, x6, dyn, 0, 0, x1, 9*FLEN/8, x3, x12, x11) +RVTEST_SIGBASE(x2,signature_x2_0) + +inst_15: +// rs1==x22, rs2==x25, rs3==x1, rd==x14,fs1 == 0 and fe1 == 0x1c and fm1 == 0x127 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x207 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x22; op2:x25; op3:x1; dest:x14; op1val:0x7127; op2val:0x7a07; +op3val:0xfbff; valaddr_reg:x1; val_offset:12*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x14, x22, x25, x1, dyn, 0, 0, x1, 12*FLEN/8, x3, x2, x11) + +inst_16: +// rs1==x29, rs2==x24, rs3==x11, rd==x15,fs1 == 0 and fe1 == 0x1d and fm1 == 0x360 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x03d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x29; op2:x24; op3:x11; dest:x15; op1val:0x7760; op2val:0x783d; +op3val:0xfbff; valaddr_reg:x1; val_offset:15*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x15, x29, x24, x11, dyn, 0, 0, x1, 15*FLEN/8, x3, x2, x11) + +inst_17: +// rs1==x27, rs2==x0, rs3==x29, rd==x30,fs1 == 0 and fe1 == 0x1e and fm1 == 0x365 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x27; op2:x0; op3:x29; dest:x30; op1val:0x7b65; op2val:0x0; +op3val:0xfbff; valaddr_reg:x1; val_offset:18*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x30, x27, x0, x29, dyn, 0, 0, x1, 18*FLEN/8, x3, x2, x11) + +inst_18: +// rs1==x10, rs2==x26, rs3==x13, rd==x9,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x30f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x10; op2:x26; op3:x13; dest:x9; op1val:0x75a8; op2val:0x7b0f; +op3val:0xfbff; valaddr_reg:x1; val_offset:21*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x9, x10, x26, x13, dyn, 0, 0, x1, 21*FLEN/8, x3, x2, x11) + +inst_19: +// rs1==x20, rs2==x31, rs3==x0, rd==x29,fs1 == 0 and fe1 == 0x1d and fm1 == 0x35f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x08a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x20; op2:x31; op3:x0; dest:x29; op1val:0x775f; op2val:0x788a; +op3val:0x0; valaddr_reg:x1; val_offset:24*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x29, x20, x31, x0, dyn, 0, 0, x1, 24*FLEN/8, x3, x2, x11) + +inst_20: +// rs1==x6, rs2==x8, rs3==x4, rd==x7,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c9 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3c8 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x6; op2:x8; op3:x4; dest:x7; op1val:0x79c9; op2val:0x77c8; +op3val:0xfbff; valaddr_reg:x1; val_offset:27*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x7, x6, x8, x4, dyn, 0, 0, x1, 27*FLEN/8, x3, x2, x11) +RVTEST_VALBASEUPD(x15,test_dataset_2) + +inst_21: +// rs1==x13, rs2==x5, rs3==x23, rd==x3,fs1 == 0 and fe1 == 0x1d and fm1 == 0x131 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x198 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x13; op2:x5; op3:x23; dest:x3; op1val:0x7531; op2val:0x7998; +op3val:0xfbff; valaddr_reg:x15; val_offset:0*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x3, x13, x5, x23, dyn, 0, 0, x15, 0*FLEN/8, x17, x2, x11) + +inst_22: +// rs1==x21, rs2==x29, rs3==x17, rd==x28,fs1 == 0 and fe1 == 0x1e and fm1 == 0x342 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x049 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x21; op2:x29; op3:x17; dest:x28; op1val:0x7b42; op2val:0x7449; +op3val:0xfbff; valaddr_reg:x15; val_offset:3*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x28, x21, x29, x17, dyn, 0, 0, x15, 3*FLEN/8, x17, x2, x11) + +inst_23: +// rs1==x12, rs2==x7, rs3==x3, rd==x4,fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3a7 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x12; op2:x7; op3:x3; dest:x4; op1val:0x74f3; op2val:0x7ba7; +op3val:0xfbff; valaddr_reg:x15; val_offset:6*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x4, x12, x7, x3, dyn, 0, 0, x15, 6*FLEN/8, x17, x2, x11) + +inst_24: +// rs1==x23, rs2==x1, rs3==x27, rd==x25,fs1 == 0 and fe1 == 0x1e and fm1 == 0x008 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x023 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x23; op2:x1; op3:x27; dest:x25; op1val:0x7808; op2val:0x7823; +op3val:0xfbff; valaddr_reg:x15; val_offset:9*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x25, x23, x1, x27, dyn, 0, 0, x15, 9*FLEN/8, x17, x2, x11) +RVTEST_SIGBASE(x7,signature_x7_0) + +inst_25: +// rs1==x3, rs2==x12, rs3==x2, rd==x6,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b3 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0fc and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x3; op2:x12; op3:x2; dest:x6; op1val:0x78b3; op2val:0x74fc; +op3val:0xfbff; valaddr_reg:x15; val_offset:12*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x6, x3, x12, x2, dyn, 0, 0, x15, 12*FLEN/8, x17, x7, x10) + +inst_26: +// rs1==x11, rs2==x21, rs3==x7, rd==x26,fs1 == 0 and fe1 == 0x1e and fm1 == 0x017 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x378 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x11; op2:x21; op3:x7; dest:x26; op1val:0x7817; op2val:0x7b78; +op3val:0xfbff; valaddr_reg:x15; val_offset:15*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x26, x11, x21, x7, dyn, 0, 0, x15, 15*FLEN/8, x17, x7, x10) + +inst_27: +// rs1==x26, rs2==x20, rs3==x31, rd==x23,fs1 == 0 and fe1 == 0x1b and fm1 == 0x0d2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x28f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x26; op2:x20; op3:x31; dest:x23; op1val:0x6cd2; op2val:0x7a8f; +op3val:0xfbff; valaddr_reg:x15; val_offset:18*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x23, x26, x20, x31, dyn, 0, 0, x15, 18*FLEN/8, x17, x7, x10) + +inst_28: +// rs1==x1, rs2==x4, rs3==x14, rd==x0,fs1 == 0 and fe1 == 0x1e and fm1 == 0x341 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x21f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x1; op2:x4; op3:x14; dest:x0; op1val:0x7b41; op2val:0x721f; +op3val:0xfbff; valaddr_reg:x15; val_offset:21*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x0, x1, x4, x14, dyn, 0, 0, x15, 21*FLEN/8, x17, x7, x10) + +inst_29: +// rs1==x2, rs2==x9, rs3==x20, rd==x22,fs1 == 0 and fe1 == 0x1a and fm1 == 0x384 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x138 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x2; op2:x9; op3:x20; dest:x22; op1val:0x6b84; op2val:0x7938; +op3val:0xfbff; valaddr_reg:x15; val_offset:24*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x22, x2, x9, x20, dyn, 0, 0, x15, 24*FLEN/8, x17, x7, x10) + +inst_30: +// rs1==x0, rs2==x22, rs3==x16, rd==x20,fs1 == 0 and fe1 == 0x1c and fm1 == 0x33f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x300 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x0; op2:x22; op3:x16; dest:x20; op1val:0x0; op2val:0x7b00; +op3val:0xfbff; valaddr_reg:x15; val_offset:27*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x20, x0, x22, x16, dyn, 0, 0, x15, 27*FLEN/8, x17, x7, x10) + +inst_31: +// rs1==x14,fs1 == 0 and fe1 == 0x1e and fm1 == 0x02d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2d4 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x14; op2:x18; op3:x16; dest:x0; op1val:0x782d; op2val:0x7ad4; +op3val:0xfbff; valaddr_reg:x15; val_offset:30*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x0, x14, x18, x16, dyn, 0, 0, x15, 30*FLEN/8, x17, x7, x10) + +inst_32: +// rs2==x14,fs1 == 0 and fe1 == 0x1c and fm1 == 0x2bb and fs2 == 0 and fe2 == 0x1e and fm2 == 0x30a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x16; op2:x14; op3:x1; dest:x5; op1val:0x72bb; op2val:0x7b0a; +op3val:0xfbff; valaddr_reg:x15; val_offset:33*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x5, x16, x14, x1, dyn, 0, 0, x15, 33*FLEN/8, x17, x7, x10) + +inst_33: +// rs3==x8,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1bb and fs2 == 0 and fe2 == 0x1a and fm2 == 0x013 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x5; op2:x26; op3:x8; dest:x0; op1val:0x79bb; op2val:0x6813; +op3val:0xfbff; valaddr_reg:x15; val_offset:36*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x0, x5, x26, x8, dyn, 0, 0, x15, 36*FLEN/8, x17, x7, x10) + +inst_34: +// rd==x12,fs1 == 0 and fe1 == 0x1c and fm1 == 0x17f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x161 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x14; op2:x8; op3:x19; dest:x12; op1val:0x717f; op2val:0x7961; +op3val:0xfbff; valaddr_reg:x15; val_offset:39*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x12, x14, x8, x19, dyn, 0, 0, x15, 39*FLEN/8, x17, x7, x10) +RVTEST_VALBASEUPD(x1,test_dataset_3) + +inst_35: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x27c and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ba1; op2val:0x667c; +op3val:0xfbff; valaddr_reg:x1; val_offset:0*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 0*FLEN/8, x2, x7, x10) + +inst_36: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x169 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x016 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6569; op2val:0x7416; +op3val:0xfbff; valaddr_reg:x1; val_offset:3*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3*FLEN/8, x2, x7, x10) + +inst_37: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x106 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1e0 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7106; op2val:0x71e0; +op3val:0xfbff; valaddr_reg:x1; val_offset:6*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 6*FLEN/8, x2, x7, x10) + +inst_38: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x22a and fs2 == 0 and fe2 == 0x1a and fm2 == 0x185 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x762a; op2val:0x6985; +op3val:0xfbff; valaddr_reg:x1; val_offset:9*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 9*FLEN/8, x2, x7, x10) + +inst_39: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0d7 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x0a3 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70d7; op2val:0x68a3; +op3val:0xfbff; valaddr_reg:x1; val_offset:12*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 12*FLEN/8, x2, x7, x10) + +inst_40: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0eb and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1ef and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78eb; op2val:0x79ef; +op3val:0xfbff; valaddr_reg:x1; val_offset:15*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 15*FLEN/8, x2, x7, x10) + +inst_41: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x164 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x3e2 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7564; op2val:0x67e2; +op3val:0xfbff; valaddr_reg:x1; val_offset:18*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 18*FLEN/8, x2, x7, x10) + +inst_42: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1ea and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a1f; op2val:0x79ea; +op3val:0xfbff; valaddr_reg:x1; val_offset:21*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 21*FLEN/8, x2, x7, x10) + +inst_43: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2e5 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a0a; op2val:0x7ae5; +op3val:0xfbff; valaddr_reg:x1; val_offset:24*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 24*FLEN/8, x2, x7, x10) + +inst_44: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x38f and fs2 == 0 and fe2 == 0x1c and fm2 == 0x336 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x778f; op2val:0x7336; +op3val:0xfbff; valaddr_reg:x1; val_offset:27*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 27*FLEN/8, x2, x7, x10) + +inst_45: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x10e and fs2 == 0 and fe2 == 0x1b and fm2 == 0x287 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x750e; op2val:0x6e87; +op3val:0xfbff; valaddr_reg:x1; val_offset:30*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 30*FLEN/8, x2, x7, x10) + +inst_46: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2fe and fs2 == 0 and fe2 == 0x1c and fm2 == 0x014 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7afe; op2val:0x7014; +op3val:0xfbff; valaddr_reg:x1; val_offset:33*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 33*FLEN/8, x2, x7, x10) + +inst_47: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x248 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x01d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7648; op2val:0x781d; +op3val:0xfbff; valaddr_reg:x1; val_offset:36*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 36*FLEN/8, x2, x7, x10) + +inst_48: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ac and fs2 == 0 and fe2 == 0x1d and fm2 == 0x024 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bac; op2val:0x7424; +op3val:0xfbff; valaddr_reg:x1; val_offset:39*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 39*FLEN/8, x2, x7, x10) + +inst_49: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2b6 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x09d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76b6; op2val:0x649d; +op3val:0xfbff; valaddr_reg:x1; val_offset:42*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 42*FLEN/8, x2, x7, x10) + +inst_50: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x07e and fs2 == 0 and fe2 == 0x1a and fm2 == 0x343 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x707e; op2val:0x6b43; +op3val:0xfbff; valaddr_reg:x1; val_offset:45*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 45*FLEN/8, x2, x7, x10) + +inst_51: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x127 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x221 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7127; op2val:0x6e21; +op3val:0xfbff; valaddr_reg:x1; val_offset:48*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 48*FLEN/8, x2, x7, x10) + +inst_52: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x010 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3dd and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7810; op2val:0x7bdd; +op3val:0xfbff; valaddr_reg:x1; val_offset:51*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 51*FLEN/8, x2, x7, x10) + +inst_53: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f3 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x36f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bf3; op2val:0x736f; +op3val:0xfbff; valaddr_reg:x1; val_offset:54*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 54*FLEN/8, x2, x7, x10) + +inst_54: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0ba and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7402; op2val:0x78ba; +op3val:0xfbff; valaddr_reg:x1; val_offset:57*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 57*FLEN/8, x2, x7, x10) + +inst_55: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x266 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1ac and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a66; op2val:0x79ac; +op3val:0xfbff; valaddr_reg:x1; val_offset:60*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 60*FLEN/8, x2, x7, x10) + +inst_56: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2c3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x035 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76c3; op2val:0x7835; +op3val:0xfbff; valaddr_reg:x1; val_offset:63*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 63*FLEN/8, x2, x7, x10) + +inst_57: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x08a and fs2 == 0 and fe2 == 0x1d and fm2 == 0x289 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x688a; op2val:0x7689; +op3val:0xfbff; valaddr_reg:x1; val_offset:66*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 66*FLEN/8, x2, x7, x10) + +inst_58: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c9 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3b4 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79c9; op2val:0x73b4; +op3val:0xfbff; valaddr_reg:x1; val_offset:69*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 69*FLEN/8, x2, x7, x10) + +inst_59: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1d0 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x367 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71d0; op2val:0x7367; +op3val:0xfbff; valaddr_reg:x1; val_offset:72*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 72*FLEN/8, x2, x7, x10) + +inst_60: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x029 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x36d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7829; op2val:0x776d; +op3val:0xfbff; valaddr_reg:x1; val_offset:75*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 75*FLEN/8, x2, x7, x10) + +inst_61: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x121 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2cb and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7921; op2val:0x72cb; +op3val:0xfbff; valaddr_reg:x1; val_offset:78*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 78*FLEN/8, x2, x7, x10) + +inst_62: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1d4 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bb3; op2val:0x79d4; +op3val:0xfbff; valaddr_reg:x1; val_offset:81*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 81*FLEN/8, x2, x7, x10) + +inst_63: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x017 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0a5 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7817; op2val:0x78a5; +op3val:0xfbff; valaddr_reg:x1; val_offset:84*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 84*FLEN/8, x2, x7, x10) + +inst_64: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2af and fs2 == 0 and fe2 == 0x1e and fm2 == 0x032 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76af; op2val:0x7832; +op3val:0xfbff; valaddr_reg:x1; val_offset:87*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 87*FLEN/8, x2, x7, x10) + +inst_65: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x26b and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dff; op2val:0x7a6b; +op3val:0xfbff; valaddr_reg:x1; val_offset:90*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 90*FLEN/8, x2, x7, x10) + +inst_66: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x026 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x35e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7826; op2val:0x7b5e; +op3val:0xfbff; valaddr_reg:x1; val_offset:93*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 93*FLEN/8, x2, x7, x10) + +inst_67: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3dd and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74a1; op2val:0x7bdd; +op3val:0xfbff; valaddr_reg:x1; val_offset:96*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 96*FLEN/8, x2, x7, x10) + +inst_68: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x0e0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x17a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x64e0; op2val:0x797a; +op3val:0xfbff; valaddr_reg:x1; val_offset:99*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 99*FLEN/8, x2, x7, x10) + +inst_69: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0e4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b8 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74e4; op2val:0x7ab8; +op3val:0xfbff; valaddr_reg:x1; val_offset:102*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 102*FLEN/8, x2, x7, x10) + +inst_70: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x005 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x338 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6405; op2val:0x7738; +op3val:0xfbff; valaddr_reg:x1; val_offset:105*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 105*FLEN/8, x2, x7, x10) + +inst_71: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3c5 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2a9 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77c5; op2val:0x72a9; +op3val:0xfbff; valaddr_reg:x1; val_offset:108*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 108*FLEN/8, x2, x7, x10) + +inst_72: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0b8 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x08c and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6cb8; op2val:0x748c; +op3val:0xfbff; valaddr_reg:x1; val_offset:111*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 111*FLEN/8, x2, x7, x10) + +inst_73: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37a and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0e5 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b7a; op2val:0x6ce5; +op3val:0xfbff; valaddr_reg:x1; val_offset:114*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 114*FLEN/8, x2, x7, x10) + +inst_74: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x227 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x091 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7227; op2val:0x7891; +op3val:0xfbff; valaddr_reg:x1; val_offset:117*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 117*FLEN/8, x2, x7, x10) + +inst_75: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x368 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x206 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7768; op2val:0x7a06; +op3val:0xfbff; valaddr_reg:x1; val_offset:120*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 120*FLEN/8, x2, x7, x10) + +inst_76: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3c9 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3ca and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6fc9; op2val:0x6fca; +op3val:0xfbff; valaddr_reg:x1; val_offset:123*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 123*FLEN/8, x2, x7, x10) + +inst_77: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2cc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x120 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7acc; op2val:0x7920; +op3val:0xfbff; valaddr_reg:x1; val_offset:126*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 126*FLEN/8, x2, x7, x10) + +inst_78: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x189 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x24f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7989; op2val:0x664f; +op3val:0xfbff; valaddr_reg:x1; val_offset:129*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 129*FLEN/8, x2, x7, x10) + +inst_79: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x236 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1c9 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a36; op2val:0x79c9; +op3val:0xfbff; valaddr_reg:x1; val_offset:132*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 132*FLEN/8, x2, x7, x10) + +inst_80: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1b7 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x34f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75b7; op2val:0x774f; +op3val:0xfbff; valaddr_reg:x1; val_offset:135*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 135*FLEN/8, x2, x7, x10) + +inst_81: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x04d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x035 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x744d; op2val:0x7835; +op3val:0xfbff; valaddr_reg:x1; val_offset:138*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 138*FLEN/8, x2, x7, x10) + +inst_82: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x26e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ba2; op2val:0x7a6e; +op3val:0xfbff; valaddr_reg:x1; val_offset:141*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 141*FLEN/8, x2, x7, x10) + +inst_83: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2af and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0be and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aaf; op2val:0x74be; +op3val:0xfbff; valaddr_reg:x1; val_offset:144*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 144*FLEN/8, x2, x7, x10) + +inst_84: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d1 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x026 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77d1; op2val:0x7426; +op3val:0xfbff; valaddr_reg:x1; val_offset:147*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 147*FLEN/8, x2, x7, x10) + +inst_85: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x16e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x358 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x796e; op2val:0x7b58; +op3val:0xfbff; valaddr_reg:x1; val_offset:150*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 150*FLEN/8, x2, x7, x10) + +inst_86: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28a and fs2 == 0 and fe2 == 0x1b and fm2 == 0x223 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8a; op2val:0x6e23; +op3val:0xfbff; valaddr_reg:x1; val_offset:153*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 153*FLEN/8, x2, x7, x10) + +inst_87: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3fa and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0af and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bfa; op2val:0x70af; +op3val:0xfbff; valaddr_reg:x1; val_offset:156*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 156*FLEN/8, x2, x7, x10) + +inst_88: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x046 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x182 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c46; op2val:0x6d82; +op3val:0xfbff; valaddr_reg:x1; val_offset:159*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 159*FLEN/8, x2, x7, x10) + +inst_89: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x12e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7be7; op2val:0x792e; +op3val:0xfbff; valaddr_reg:x1; val_offset:162*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 162*FLEN/8, x2, x7, x10) + +inst_90: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0bd and fs2 == 0 and fe2 == 0x1c and fm2 == 0x369 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74bd; op2val:0x7369; +op3val:0xfbff; valaddr_reg:x1; val_offset:165*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 165*FLEN/8, x2, x7, x10) + +inst_91: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x172 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x304 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7972; op2val:0x7704; +op3val:0xfbff; valaddr_reg:x1; val_offset:168*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 168*FLEN/8, x2, x7, x10) + +inst_92: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x32b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x053 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f2b; op2val:0x7853; +op3val:0xfbff; valaddr_reg:x1; val_offset:171*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 171*FLEN/8, x2, x7, x10) + +inst_93: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20b and fs2 == 0 and fe2 == 0x1b and fm2 == 0x226 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a0b; op2val:0x6e26; +op3val:0xfbff; valaddr_reg:x1; val_offset:174*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 174*FLEN/8, x2, x7, x10) + +inst_94: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b8 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x01d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79b8; op2val:0x741d; +op3val:0xfbff; valaddr_reg:x1; val_offset:177*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 177*FLEN/8, x2, x7, x10) + +inst_95: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x35f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x19f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x775f; op2val:0x799f; +op3val:0xfbff; valaddr_reg:x1; val_offset:180*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 180*FLEN/8, x2, x7, x10) + +inst_96: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x242 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bf5; op2val:0x7a42; +op3val:0xfbff; valaddr_reg:x1; val_offset:183*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 183*FLEN/8, x2, x7, x10) + +inst_97: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0a1 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x30e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70a1; op2val:0x770e; +op3val:0xfbff; valaddr_reg:x1; val_offset:186*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 186*FLEN/8, x2, x7, x10) + +inst_98: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x30d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78c2; op2val:0x7b0d; +op3val:0xfbff; valaddr_reg:x1; val_offset:189*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 189*FLEN/8, x2, x7, x10) + +inst_99: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x014 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3b7 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7814; op2val:0x77b7; +op3val:0xfbff; valaddr_reg:x1; val_offset:192*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 192*FLEN/8, x2, x7, x10) + +inst_100: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ae and fs2 == 0 and fe2 == 0x1e and fm2 == 0x37d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79ae; op2val:0x7b7d; +op3val:0xfbff; valaddr_reg:x1; val_offset:195*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 195*FLEN/8, x2, x7, x10) + +inst_101: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x38e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3b1 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x778e; op2val:0x7bb1; +op3val:0xfbff; valaddr_reg:x1; val_offset:198*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 198*FLEN/8, x2, x7, x10) + +inst_102: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x143 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f6; op2val:0x7943; +op3val:0xfbff; valaddr_reg:x1; val_offset:201*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 201*FLEN/8, x2, x7, x10) + +inst_103: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d0 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x332 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ad0; op2val:0x7332; +op3val:0xfbff; valaddr_reg:x1; val_offset:204*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 204*FLEN/8, x2, x7, x10) + +inst_104: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x270 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7670; op2val:0x7955; +op3val:0xfbff; valaddr_reg:x1; val_offset:207*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 207*FLEN/8, x2, x7, x10) + +inst_105: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x1f0 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7913; op2val:0x61f0; +op3val:0xfbff; valaddr_reg:x1; val_offset:210*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 210*FLEN/8, x2, x7, x10) + +inst_106: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x30f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79b0; op2val:0x7b0f; +op3val:0xfbff; valaddr_reg:x1; val_offset:213*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 213*FLEN/8, x2, x7, x10) + +inst_107: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x286 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x062 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a86; op2val:0x6462; +op3val:0xfbff; valaddr_reg:x1; val_offset:216*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 216*FLEN/8, x2, x7, x10) + +inst_108: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0d9 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79d5; op2val:0x78d9; +op3val:0xfbff; valaddr_reg:x1; val_offset:219*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 219*FLEN/8, x2, x7, x10) + +inst_109: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x312 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x26d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b12; op2val:0x6e6d; +op3val:0xfbff; valaddr_reg:x1; val_offset:222*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 222*FLEN/8, x2, x7, x10) + +inst_110: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x222 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x261 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a22; op2val:0x7261; +op3val:0xfbff; valaddr_reg:x1; val_offset:225*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 225*FLEN/8, x2, x7, x10) + +inst_111: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b0 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x21f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78b0; op2val:0x721f; +op3val:0xfbff; valaddr_reg:x1; val_offset:228*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 228*FLEN/8, x2, x7, x10) + +inst_112: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x068 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0e5 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7068; op2val:0x78e5; +op3val:0xfbff; valaddr_reg:x1; val_offset:231*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 231*FLEN/8, x2, x7, x10) + +inst_113: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x00e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x086 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x740e; op2val:0x7886; +op3val:0xfbff; valaddr_reg:x1; val_offset:234*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 234*FLEN/8, x2, x7, x10) + +inst_114: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x28e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3bb and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x728e; op2val:0x7bbb; +op3val:0xfbff; valaddr_reg:x1; val_offset:237*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 237*FLEN/8, x2, x7, x10) + +inst_115: +// fs1 == 0 and fe1 == 0x16 and fm1 == 0x237 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3c3 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5a37; op2val:0x77c3; +op3val:0xfbff; valaddr_reg:x1; val_offset:240*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 240*FLEN/8, x2, x7, x10) + +inst_116: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x143 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x208 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7943; op2val:0x7a08; +op3val:0xfbff; valaddr_reg:x1; val_offset:243*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 243*FLEN/8, x2, x7, x10) + +inst_117: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x165 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x15b and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7965; op2val:0x755b; +op3val:0xfbff; valaddr_reg:x1; val_offset:246*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 246*FLEN/8, x2, x7, x10) + +inst_118: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x005 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x30b and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7805; op2val:0x670b; +op3val:0xfbff; valaddr_reg:x1; val_offset:249*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 249*FLEN/8, x2, x7, x10) + +inst_119: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x207 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x18e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a07; op2val:0x718e; +op3val:0xfbff; valaddr_reg:x1; val_offset:252*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 252*FLEN/8, x2, x7, x10) + +inst_120: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x245 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x277 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a45; op2val:0x7677; +op3val:0xfbff; valaddr_reg:x1; val_offset:255*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 255*FLEN/8, x2, x7, x10) + +inst_121: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x24b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2e8 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a4b; op2val:0x7ae8; +op3val:0xfbff; valaddr_reg:x1; val_offset:258*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 258*FLEN/8, x2, x7, x10) + +inst_122: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x133 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x21a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7133; op2val:0x761a; +op3val:0xfbff; valaddr_reg:x1; val_offset:261*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 261*FLEN/8, x2, x7, x10) + +inst_123: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0b6 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x152 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74b6; op2val:0x6152; +op3val:0xfbff; valaddr_reg:x1; val_offset:264*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 264*FLEN/8, x2, x7, x10) + +inst_124: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3bb and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1dc and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bbb; op2val:0x75dc; +op3val:0xfbff; valaddr_reg:x1; val_offset:267*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 267*FLEN/8, x2, x7, x10) + +inst_125: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x21d and fs2 == 0 and fe2 == 0x1d and fm2 == 0x314 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x761d; op2val:0x7714; +op3val:0xfbff; valaddr_reg:x1; val_offset:270*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 270*FLEN/8, x2, x7, x10) + +inst_126: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ee and fs2 == 0 and fe2 == 0x1e and fm2 == 0x130 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74ee; op2val:0x7930; +op3val:0xfbff; valaddr_reg:x1; val_offset:273*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 273*FLEN/8, x2, x7, x10) + +inst_127: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x350 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x784e; op2val:0x7b50; +op3val:0xfbff; valaddr_reg:x1; val_offset:276*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 276*FLEN/8, x2, x7, x10) + +inst_128: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x297 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0dd and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a97; op2val:0x74dd; +op3val:0xfbff; valaddr_reg:x1; val_offset:279*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 279*FLEN/8, x2, x7, x10) + +inst_129: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x139 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5d; op2val:0x7939; +op3val:0xfbff; valaddr_reg:x1; val_offset:282*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 282*FLEN/8, x2, x7, x10) + +inst_130: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b8 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x1f2 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ab8; op2val:0x6df2; +op3val:0xfbff; valaddr_reg:x1; val_offset:285*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 285*FLEN/8, x2, x7, x10) + +inst_131: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x241 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x03d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7641; op2val:0x783d; +op3val:0xfbff; valaddr_reg:x1; val_offset:288*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 288*FLEN/8, x2, x7, x10) + +inst_132: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x261 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x107 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a61; op2val:0x7907; +op3val:0xfbff; valaddr_reg:x1; val_offset:291*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 291*FLEN/8, x2, x7, x10) + +inst_133: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x373 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x351 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7373; op2val:0x7751; +op3val:0xfbff; valaddr_reg:x1; val_offset:294*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 294*FLEN/8, x2, x7, x10) + +inst_134: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x070 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3a8 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7470; op2val:0x7ba8; +op3val:0xfbff; valaddr_reg:x1; val_offset:297*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 297*FLEN/8, x2, x7, x10) + +inst_135: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28b and fs2 == 0 and fe2 == 0x1d and fm2 == 0x210 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8b; op2val:0x7610; +op3val:0xfbff; valaddr_reg:x1; val_offset:300*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 300*FLEN/8, x2, x7, x10) + +inst_136: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x117 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0f3 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7517; op2val:0x6cf3; +op3val:0xfbff; valaddr_reg:x1; val_offset:303*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 303*FLEN/8, x2, x7, x10) + +inst_137: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x153 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x311 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7153; op2val:0x7711; +op3val:0xfbff; valaddr_reg:x1; val_offset:306*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 306*FLEN/8, x2, x7, x10) + +inst_138: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x327 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x35e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b27; op2val:0x7b5e; +op3val:0xfbff; valaddr_reg:x1; val_offset:309*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 309*FLEN/8, x2, x7, x10) + +inst_139: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x11d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x36e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x791d; op2val:0x7b6e; +op3val:0xfbff; valaddr_reg:x1; val_offset:312*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 312*FLEN/8, x2, x7, x10) + +inst_140: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x25e and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39b and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e5e; op2val:0x739b; +op3val:0xfbff; valaddr_reg:x1; val_offset:315*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 315*FLEN/8, x2, x7, x10) + +inst_141: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x16c and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1fa and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x796c; op2val:0x75fa; +op3val:0xfbff; valaddr_reg:x1; val_offset:318*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 318*FLEN/8, x2, x7, x10) + +inst_142: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25b and fs2 == 0 and fe2 == 0x1c and fm2 == 0x375 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5b; op2val:0x7375; +op3val:0xfbff; valaddr_reg:x1; val_offset:321*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 321*FLEN/8, x2, x7, x10) + +inst_143: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x10f and fs2 == 0 and fe2 == 0x1d and fm2 == 0x266 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x790f; op2val:0x7666; +op3val:0xfbff; valaddr_reg:x1; val_offset:324*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 324*FLEN/8, x2, x7, x10) + +inst_144: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x179 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x306 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7579; op2val:0x7b06; +op3val:0xfbff; valaddr_reg:x1; val_offset:327*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 327*FLEN/8, x2, x7, x10) + +inst_145: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x184 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7804; op2val:0x7984; +op3val:0xfbff; valaddr_reg:x1; val_offset:330*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 330*FLEN/8, x2, x7, x10) + +inst_146: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f0; op2val:0x7a01; +op3val:0xfbff; valaddr_reg:x1; val_offset:333*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 333*FLEN/8, x2, x7, x10) + +inst_147: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x206 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b7b; op2val:0x7a06; +op3val:0xfbff; valaddr_reg:x1; val_offset:336*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 336*FLEN/8, x2, x7, x10) + +inst_148: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0fa and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74a9; op2val:0x78fa; +op3val:0xfbff; valaddr_reg:x1; val_offset:339*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 339*FLEN/8, x2, x7, x10) + +inst_149: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1e0 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x251 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75e0; op2val:0x7651; +op3val:0xfbff; valaddr_reg:x1; val_offset:342*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 342*FLEN/8, x2, x7, x10) + +inst_150: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a8 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1a9 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ba8; op2val:0x75a9; +op3val:0xfbff; valaddr_reg:x1; val_offset:345*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 345*FLEN/8, x2, x7, x10) + +inst_151: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x325 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1f6 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b25; op2val:0x71f6; +op3val:0xfbff; valaddr_reg:x1; val_offset:348*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 348*FLEN/8, x2, x7, x10) + +inst_152: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x010 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x32c and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7010; op2val:0x672c; +op3val:0xfbff; valaddr_reg:x1; val_offset:351*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 351*FLEN/8, x2, x7, x10) +RVTEST_SIGBASE(x7,signature_x7_1) + +inst_153: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1be and fs2 == 0 and fe2 == 0x1e and fm2 == 0x356 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75be; op2val:0x7b56; +op3val:0xfbff; valaddr_reg:x1; val_offset:354*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 354*FLEN/8, x2, x7, x10) + +inst_154: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x216 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2fa and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a16; op2val:0x76fa; +op3val:0xfbff; valaddr_reg:x1; val_offset:357*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 357*FLEN/8, x2, x7, x10) + +inst_155: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x392 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2aa and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7392; op2val:0x7aaa; +op3val:0xfbff; valaddr_reg:x1; val_offset:360*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 360*FLEN/8, x2, x7, x10) + +inst_156: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x08d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x119 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x748d; op2val:0x7919; +op3val:0xfbff; valaddr_reg:x1; val_offset:363*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 363*FLEN/8, x2, x7, x10) + +inst_157: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x10f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x367 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x750f; op2val:0x7b67; +op3val:0xfbff; valaddr_reg:x1; val_offset:366*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 366*FLEN/8, x2, x7, x10) + +inst_158: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x08c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x289 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x708c; op2val:0x7289; +op3val:0xfbff; valaddr_reg:x1; val_offset:369*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 369*FLEN/8, x2, x7, x10) + +inst_159: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2b9 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76b9; op2val:0x7400; +op3val:0xfbff; valaddr_reg:x1; val_offset:372*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 372*FLEN/8, x2, x7, x10) + +inst_160: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3e2 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3ad and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73e2; op2val:0x73ad; +op3val:0xfbff; valaddr_reg:x1; val_offset:375*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 375*FLEN/8, x2, x7, x10) + +inst_161: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x161 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1f6 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7561; op2val:0x75f6; +op3val:0xfbff; valaddr_reg:x1; val_offset:378*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 378*FLEN/8, x2, x7, x10) + +inst_162: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3e4 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x09b and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6be4; op2val:0x709b; +op3val:0xfbff; valaddr_reg:x1; val_offset:381*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 381*FLEN/8, x2, x7, x10) + +inst_163: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2df and fs2 == 0 and fe2 == 0x1e and fm2 == 0x23a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76df; op2val:0x7a3a; +op3val:0xfbff; valaddr_reg:x1; val_offset:384*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 384*FLEN/8, x2, x7, x10) + +inst_164: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c2 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x782e; op2val:0x7ac2; +op3val:0xfbff; valaddr_reg:x1; val_offset:387*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 387*FLEN/8, x2, x7, x10) + +inst_165: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x224 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0e1 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a24; op2val:0x78e1; +op3val:0xfbff; valaddr_reg:x1; val_offset:390*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 390*FLEN/8, x2, x7, x10) + +inst_166: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f9 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x246 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bf9; op2val:0x7646; +op3val:0xfbff; valaddr_reg:x1; val_offset:393*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 393*FLEN/8, x2, x7, x10) + +inst_167: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0f4 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x111 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78f4; op2val:0x7511; +op3val:0xfbff; valaddr_reg:x1; val_offset:396*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 396*FLEN/8, x2, x7, x10) + +inst_168: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0b3 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78c7; op2val:0x78b3; +op3val:0xfbff; valaddr_reg:x1; val_offset:399*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 399*FLEN/8, x2, x7, x10) + +inst_169: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3e8 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7be0; op2val:0x7be8; +op3val:0xfbff; valaddr_reg:x1; val_offset:402*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 402*FLEN/8, x2, x7, x10) + +inst_170: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x345 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x295 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7745; op2val:0x7695; +op3val:0xfbff; valaddr_reg:x1; val_offset:405*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 405*FLEN/8, x2, x7, x10) + +inst_171: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x1e7 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2ec and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x69e7; op2val:0x6eec; +op3val:0xfbff; valaddr_reg:x1; val_offset:408*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 408*FLEN/8, x2, x7, x10) + +inst_172: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x019 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x37e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7019; op2val:0x7b7e; +op3val:0xfbff; valaddr_reg:x1; val_offset:411*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 411*FLEN/8, x2, x7, x10) + +inst_173: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x351 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0f2 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b51; op2val:0x6cf2; +op3val:0xfbff; valaddr_reg:x1; val_offset:414*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 414*FLEN/8, x2, x7, x10) + +inst_174: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x261 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x086 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a61; op2val:0x6086; +op3val:0xfbff; valaddr_reg:x1; val_offset:417*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 417*FLEN/8, x2, x7, x10) + +inst_175: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x19b and fs2 == 0 and fe2 == 0x1c and fm2 == 0x189 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x759b; op2val:0x7189; +op3val:0xfbff; valaddr_reg:x1; val_offset:420*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 420*FLEN/8, x2, x7, x10) + +inst_176: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15b and fs2 == 0 and fe2 == 0x1b and fm2 == 0x1e1 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x795b; op2val:0x6de1; +op3val:0xfbff; valaddr_reg:x1; val_offset:423*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 423*FLEN/8, x2, x7, x10) + +inst_177: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x131 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x25d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7931; op2val:0x6a5d; +op3val:0xfbff; valaddr_reg:x1; val_offset:426*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 426*FLEN/8, x2, x7, x10) + +inst_178: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3b9 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3b3 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73b9; op2val:0x77b3; +op3val:0xfbff; valaddr_reg:x1; val_offset:429*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 429*FLEN/8, x2, x7, x10) + +inst_179: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x06f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x003 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x706f; op2val:0x7803; +op3val:0xfbff; valaddr_reg:x1; val_offset:432*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 432*FLEN/8, x2, x7, x10) + +inst_180: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x262 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x358 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7262; op2val:0x7b58; +op3val:0xfbff; valaddr_reg:x1; val_offset:435*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 435*FLEN/8, x2, x7, x10) + +inst_181: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x173 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x782e; op2val:0x7973; +op3val:0xfbff; valaddr_reg:x1; val_offset:438*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 438*FLEN/8, x2, x7, x10) + +inst_182: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x07a and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3de and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x707a; op2val:0x77de; +op3val:0xfbff; valaddr_reg:x1; val_offset:441*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 441*FLEN/8, x2, x7, x10) + +inst_183: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x374 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2ec and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f74; op2val:0x6eec; +op3val:0xfbff; valaddr_reg:x1; val_offset:444*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 444*FLEN/8, x2, x7, x10) + +inst_184: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x2cc and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2e2 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6acc; op2val:0x72e2; +op3val:0xfbff; valaddr_reg:x1; val_offset:447*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 447*FLEN/8, x2, x7, x10) + +inst_185: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fa and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2dd and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fa; op2val:0x7add; +op3val:0xfbff; valaddr_reg:x1; val_offset:450*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 450*FLEN/8, x2, x7, x10) + +inst_186: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1bc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x00e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79bc; op2val:0x780e; +op3val:0xfbff; valaddr_reg:x1; val_offset:453*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 453*FLEN/8, x2, x7, x10) + +inst_187: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x136 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2be and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7136; op2val:0x6ebe; +op3val:0xfbff; valaddr_reg:x1; val_offset:456*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 456*FLEN/8, x2, x7, x10) + +inst_188: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x103 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2ba and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7903; op2val:0x72ba; +op3val:0xfbff; valaddr_reg:x1; val_offset:459*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 459*FLEN/8, x2, x7, x10) + +inst_189: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0c1 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2e3 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74c1; op2val:0x76e3; +op3val:0xfbff; valaddr_reg:x1; val_offset:462*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 462*FLEN/8, x2, x7, x10) + +inst_190: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x25e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x260 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x765e; op2val:0x7a60; +op3val:0xfbff; valaddr_reg:x1; val_offset:465*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 465*FLEN/8, x2, x7, x10) + +inst_191: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x07f and fs2 == 0 and fe2 == 0x1d and fm2 == 0x38f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x787f; op2val:0x778f; +op3val:0xfbff; valaddr_reg:x1; val_offset:468*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 468*FLEN/8, x2, x7, x10) + +inst_192: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x21e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3e4 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a1e; op2val:0x7be4; +op3val:0xfbff; valaddr_reg:x1; val_offset:471*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 471*FLEN/8, x2, x7, x10) + +inst_193: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x196 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x799f; op2val:0x7996; +op3val:0xfbff; valaddr_reg:x1; val_offset:474*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 474*FLEN/8, x2, x7, x10) + +inst_194: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x3d5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x069 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x67d5; op2val:0x7869; +op3val:0xfbff; valaddr_reg:x1; val_offset:477*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 477*FLEN/8, x2, x7, x10) + +inst_195: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x237 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0a2 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7237; op2val:0x78a2; +op3val:0xfbff; valaddr_reg:x1; val_offset:480*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 480*FLEN/8, x2, x7, x10) + +inst_196: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1ef and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7900; op2val:0x79ef; +op3val:0xfbff; valaddr_reg:x1; val_offset:483*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 483*FLEN/8, x2, x7, x10) + +inst_197: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x399 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x21d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7799; op2val:0x6a1d; +op3val:0xfbff; valaddr_reg:x1; val_offset:486*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 486*FLEN/8, x2, x7, x10) + +inst_198: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x294 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ae and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a94; op2val:0x7aae; +op3val:0xfbff; valaddr_reg:x1; val_offset:489*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 489*FLEN/8, x2, x7, x10) + +inst_199: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x0e2 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x243 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x68e2; op2val:0x7243; +op3val:0xfbff; valaddr_reg:x1; val_offset:492*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 492*FLEN/8, x2, x7, x10) + +inst_200: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x394 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ba5; op2val:0x7b94; +op3val:0xfbff; valaddr_reg:x1; val_offset:495*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 495*FLEN/8, x2, x7, x10) + +inst_201: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x16d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ae and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d6d; op2val:0x7aae; +op3val:0xfbff; valaddr_reg:x1; val_offset:498*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 498*FLEN/8, x2, x7, x10) + +inst_202: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x24b and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76e3; op2val:0x764b; +op3val:0xfbff; valaddr_reg:x1; val_offset:501*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 501*FLEN/8, x2, x7, x10) + +inst_203: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x397 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bf4; op2val:0x7b97; +op3val:0xfbff; valaddr_reg:x1; val_offset:504*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 504*FLEN/8, x2, x7, x10) + +inst_204: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31d and fs2 == 0 and fe2 == 0x1d and fm2 == 0x04a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x771d; op2val:0x744a; +op3val:0xfbff; valaddr_reg:x1; val_offset:507*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 507*FLEN/8, x2, x7, x10) + +inst_205: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x305 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x36f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6705; op2val:0x776f; +op3val:0xfbff; valaddr_reg:x1; val_offset:510*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 510*FLEN/8, x2, x7, x10) + +inst_206: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x07b and fs2 == 0 and fe2 == 0x1c and fm2 == 0x38d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x787b; op2val:0x738d; +op3val:0xfbff; valaddr_reg:x1; val_offset:513*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 513*FLEN/8, x2, x7, x10) + +inst_207: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x164 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bfc; op2val:0x7964; +op3val:0xfbff; valaddr_reg:x1; val_offset:516*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 516*FLEN/8, x2, x7, x10) + +inst_208: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x365 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b65; op2val:0x7801; +op3val:0xfbff; valaddr_reg:x1; val_offset:519*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 519*FLEN/8, x2, x7, x10) + +inst_209: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x35f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x08a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x775f; op2val:0x788a; +op3val:0xfbff; valaddr_reg:x1; val_offset:522*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 522*FLEN/8, x2, x7, x10) + +inst_210: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x341 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x21f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b41; op2val:0x721f; +op3val:0xfbff; valaddr_reg:x1; val_offset:525*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 525*FLEN/8, x2, x7, x10) + +inst_211: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x33f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x300 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x733f; op2val:0x7b00; +op3val:0xfbff; valaddr_reg:x1; val_offset:528*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 528*FLEN/8, x2, x7, x10) + +inst_212: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2d4 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x782d; op2val:0x7ad4; +op3val:0xfbff; valaddr_reg:x1; val_offset:531*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 531*FLEN/8, x2, x7, x10) + +inst_213: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1bb and fs2 == 0 and fe2 == 0x1a and fm2 == 0x013 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79bb; op2val:0x6813; +op3val:0xfbff; valaddr_reg:x1; val_offset:534*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 534*FLEN/8, x2, x7, x10) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(31636,32,FLEN) +NAN_BOXED(31653,16,FLEN) +NAN_BOXED(28013,32,FLEN) +NAN_BOXED(31406,32,FLEN) +NAN_BOXED(31406,16,FLEN) +NAN_BOXED(31066,32,FLEN) +NAN_BOXED(29933,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30938,32,FLEN) +NAN_BOXED(30885,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30435,32,FLEN) +NAN_BOXED(30283,32,FLEN) +NAN_BOXED(30435,16,FLEN) +NAN_BOXED(31732,32,FLEN) +NAN_BOXED(31732,32,FLEN) +NAN_BOXED(31732,16,FLEN) +NAN_BOXED(30493,32,FLEN) +NAN_BOXED(30493,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(26373,32,FLEN) +NAN_BOXED(30575,32,FLEN) +NAN_BOXED(30575,16,FLEN) +NAN_BOXED(30227,32,FLEN) +NAN_BOXED(31521,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30843,32,FLEN) +NAN_BOXED(30843,32,FLEN) +NAN_BOXED(30843,16,FLEN) +NAN_BOXED(30003,32,FLEN) +NAN_BOXED(28767,32,FLEN) +NAN_BOXED(64511,16,FLEN) +test_dataset_1: +NAN_BOXED(31740,32,FLEN) +NAN_BOXED(31740,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31525,32,FLEN) +NAN_BOXED(31326,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31551,32,FLEN) +NAN_BOXED(31257,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30120,32,FLEN) +NAN_BOXED(31704,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28967,32,FLEN) +NAN_BOXED(31239,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30560,32,FLEN) +NAN_BOXED(30781,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31589,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30120,32,FLEN) +NAN_BOXED(31503,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30559,32,FLEN) +NAN_BOXED(30858,32,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31177,32,FLEN) +NAN_BOXED(30664,32,FLEN) +NAN_BOXED(64511,16,FLEN) +test_dataset_2: +NAN_BOXED(30001,32,FLEN) +NAN_BOXED(31128,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31554,32,FLEN) +NAN_BOXED(29769,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29939,32,FLEN) +NAN_BOXED(31655,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30728,32,FLEN) +NAN_BOXED(30755,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30899,32,FLEN) +NAN_BOXED(29948,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30743,32,FLEN) +NAN_BOXED(31608,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(27858,32,FLEN) +NAN_BOXED(31375,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31553,32,FLEN) +NAN_BOXED(29215,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(27524,32,FLEN) +NAN_BOXED(31032,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31488,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30765,32,FLEN) +NAN_BOXED(31444,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29371,32,FLEN) +NAN_BOXED(31498,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31163,32,FLEN) +NAN_BOXED(26643,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29055,32,FLEN) +NAN_BOXED(31073,32,FLEN) +NAN_BOXED(64511,16,FLEN) +test_dataset_3: +NAN_BOXED(31649,16,FLEN) +NAN_BOXED(26236,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(25961,16,FLEN) +NAN_BOXED(29718,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28934,16,FLEN) +NAN_BOXED(29152,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30250,16,FLEN) +NAN_BOXED(27013,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28887,16,FLEN) +NAN_BOXED(26787,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30955,16,FLEN) +NAN_BOXED(31215,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30052,16,FLEN) +NAN_BOXED(26594,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31263,16,FLEN) +NAN_BOXED(31210,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31242,16,FLEN) +NAN_BOXED(31461,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30607,16,FLEN) +NAN_BOXED(29494,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29966,16,FLEN) +NAN_BOXED(28295,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31486,16,FLEN) +NAN_BOXED(28692,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30280,16,FLEN) +NAN_BOXED(30749,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31660,16,FLEN) +NAN_BOXED(29732,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30390,16,FLEN) +NAN_BOXED(25757,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28798,16,FLEN) +NAN_BOXED(27459,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28967,16,FLEN) +NAN_BOXED(28193,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30736,16,FLEN) +NAN_BOXED(31709,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31731,16,FLEN) +NAN_BOXED(29551,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29698,16,FLEN) +NAN_BOXED(30906,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31334,16,FLEN) +NAN_BOXED(31148,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30403,16,FLEN) +NAN_BOXED(30773,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(26762,16,FLEN) +NAN_BOXED(30345,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31177,16,FLEN) +NAN_BOXED(29620,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29136,16,FLEN) +NAN_BOXED(29543,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30761,16,FLEN) +NAN_BOXED(30573,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31009,16,FLEN) +NAN_BOXED(29387,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31667,16,FLEN) +NAN_BOXED(31188,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30743,16,FLEN) +NAN_BOXED(30885,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30383,16,FLEN) +NAN_BOXED(30770,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28159,16,FLEN) +NAN_BOXED(31339,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30758,16,FLEN) +NAN_BOXED(31582,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29857,16,FLEN) +NAN_BOXED(31709,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(25824,16,FLEN) +NAN_BOXED(31098,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29924,16,FLEN) +NAN_BOXED(31416,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(25605,16,FLEN) +NAN_BOXED(30520,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30661,16,FLEN) +NAN_BOXED(29353,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(27832,16,FLEN) +NAN_BOXED(29836,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31610,16,FLEN) +NAN_BOXED(27877,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29223,16,FLEN) +NAN_BOXED(30865,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30568,16,FLEN) +NAN_BOXED(31238,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28617,16,FLEN) +NAN_BOXED(28618,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31436,16,FLEN) +NAN_BOXED(31008,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31113,16,FLEN) +NAN_BOXED(26191,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31286,16,FLEN) +NAN_BOXED(31177,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30135,16,FLEN) +NAN_BOXED(30543,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29773,16,FLEN) +NAN_BOXED(30773,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31650,16,FLEN) +NAN_BOXED(31342,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31407,16,FLEN) +NAN_BOXED(29886,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30673,16,FLEN) +NAN_BOXED(29734,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31086,16,FLEN) +NAN_BOXED(31576,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31370,16,FLEN) +NAN_BOXED(28195,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31738,16,FLEN) +NAN_BOXED(28847,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(27718,16,FLEN) +NAN_BOXED(28034,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31719,16,FLEN) +NAN_BOXED(31022,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29885,16,FLEN) +NAN_BOXED(29545,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31090,16,FLEN) +NAN_BOXED(30468,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28459,16,FLEN) +NAN_BOXED(30803,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31243,16,FLEN) +NAN_BOXED(28198,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31160,16,FLEN) +NAN_BOXED(29725,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30559,16,FLEN) +NAN_BOXED(31135,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31733,16,FLEN) +NAN_BOXED(31298,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28833,16,FLEN) +NAN_BOXED(30478,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30914,16,FLEN) +NAN_BOXED(31501,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30740,16,FLEN) +NAN_BOXED(30647,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31150,16,FLEN) +NAN_BOXED(31613,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30606,16,FLEN) +NAN_BOXED(31665,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31222,16,FLEN) +NAN_BOXED(31043,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31440,16,FLEN) +NAN_BOXED(29490,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30320,16,FLEN) +NAN_BOXED(31061,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30995,16,FLEN) +NAN_BOXED(25072,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31152,16,FLEN) +NAN_BOXED(31503,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31366,16,FLEN) +NAN_BOXED(25698,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31189,16,FLEN) +NAN_BOXED(30937,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31506,16,FLEN) +NAN_BOXED(28269,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31266,16,FLEN) +NAN_BOXED(29281,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30896,16,FLEN) +NAN_BOXED(29215,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28776,16,FLEN) +NAN_BOXED(30949,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29710,16,FLEN) +NAN_BOXED(30854,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29326,16,FLEN) +NAN_BOXED(31675,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(23095,16,FLEN) +NAN_BOXED(30659,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31043,16,FLEN) +NAN_BOXED(31240,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31077,16,FLEN) +NAN_BOXED(30043,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30725,16,FLEN) +NAN_BOXED(26379,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31239,16,FLEN) +NAN_BOXED(29070,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31301,16,FLEN) +NAN_BOXED(30327,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31307,16,FLEN) +NAN_BOXED(31464,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28979,16,FLEN) +NAN_BOXED(30234,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29878,16,FLEN) +NAN_BOXED(24914,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31675,16,FLEN) +NAN_BOXED(30172,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30237,16,FLEN) +NAN_BOXED(30484,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29934,16,FLEN) +NAN_BOXED(31024,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30798,16,FLEN) +NAN_BOXED(31568,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31383,16,FLEN) +NAN_BOXED(29917,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31325,16,FLEN) +NAN_BOXED(31033,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31416,16,FLEN) +NAN_BOXED(28146,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30273,16,FLEN) +NAN_BOXED(30781,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31329,16,FLEN) +NAN_BOXED(30983,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29555,16,FLEN) +NAN_BOXED(30545,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29808,16,FLEN) +NAN_BOXED(31656,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31371,16,FLEN) +NAN_BOXED(30224,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29975,16,FLEN) +NAN_BOXED(27891,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29011,16,FLEN) +NAN_BOXED(30481,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31527,16,FLEN) +NAN_BOXED(31582,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31005,16,FLEN) +NAN_BOXED(31598,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28254,16,FLEN) +NAN_BOXED(29595,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31084,16,FLEN) +NAN_BOXED(30202,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31323,16,FLEN) +NAN_BOXED(29557,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30991,16,FLEN) +NAN_BOXED(30310,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30073,16,FLEN) +NAN_BOXED(31494,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30724,16,FLEN) +NAN_BOXED(31108,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31216,16,FLEN) +NAN_BOXED(31233,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31611,16,FLEN) +NAN_BOXED(31238,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29865,16,FLEN) +NAN_BOXED(30970,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30176,16,FLEN) +NAN_BOXED(30289,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31656,16,FLEN) +NAN_BOXED(30121,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31525,16,FLEN) +NAN_BOXED(29174,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28688,16,FLEN) +NAN_BOXED(26412,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30142,16,FLEN) +NAN_BOXED(31574,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31254,16,FLEN) +NAN_BOXED(30458,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29586,16,FLEN) +NAN_BOXED(31402,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29837,16,FLEN) +NAN_BOXED(31001,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29967,16,FLEN) +NAN_BOXED(31591,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28812,16,FLEN) +NAN_BOXED(29321,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30393,16,FLEN) +NAN_BOXED(29696,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29666,16,FLEN) +NAN_BOXED(29613,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30049,16,FLEN) +NAN_BOXED(30198,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(27620,16,FLEN) +NAN_BOXED(28827,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30431,16,FLEN) +NAN_BOXED(31290,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30766,16,FLEN) +NAN_BOXED(31426,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31268,16,FLEN) +NAN_BOXED(30945,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31737,16,FLEN) +NAN_BOXED(30278,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30964,16,FLEN) +NAN_BOXED(29969,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30919,16,FLEN) +NAN_BOXED(30899,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31712,16,FLEN) +NAN_BOXED(31720,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30533,16,FLEN) +NAN_BOXED(30357,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(27111,16,FLEN) +NAN_BOXED(28396,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28697,16,FLEN) +NAN_BOXED(31614,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31569,16,FLEN) +NAN_BOXED(27890,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31329,16,FLEN) +NAN_BOXED(24710,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30107,16,FLEN) +NAN_BOXED(29065,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31067,16,FLEN) +NAN_BOXED(28129,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31025,16,FLEN) +NAN_BOXED(27229,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29625,16,FLEN) +NAN_BOXED(30643,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28783,16,FLEN) +NAN_BOXED(30723,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29282,16,FLEN) +NAN_BOXED(31576,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30766,16,FLEN) +NAN_BOXED(31091,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28794,16,FLEN) +NAN_BOXED(30686,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28532,16,FLEN) +NAN_BOXED(28396,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(27340,16,FLEN) +NAN_BOXED(29410,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30970,16,FLEN) +NAN_BOXED(31453,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31164,16,FLEN) +NAN_BOXED(30734,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28982,16,FLEN) +NAN_BOXED(28350,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30979,16,FLEN) +NAN_BOXED(29370,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29889,16,FLEN) +NAN_BOXED(30435,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30302,16,FLEN) +NAN_BOXED(31328,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30847,16,FLEN) +NAN_BOXED(30607,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31262,16,FLEN) +NAN_BOXED(31716,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31135,16,FLEN) +NAN_BOXED(31126,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(26581,16,FLEN) +NAN_BOXED(30825,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29239,16,FLEN) +NAN_BOXED(30882,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(31215,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30617,16,FLEN) +NAN_BOXED(27165,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31380,16,FLEN) +NAN_BOXED(31406,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(26850,16,FLEN) +NAN_BOXED(29251,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31653,16,FLEN) +NAN_BOXED(31636,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28013,16,FLEN) +NAN_BOXED(31406,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30435,16,FLEN) +NAN_BOXED(30283,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31732,16,FLEN) +NAN_BOXED(31639,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30493,16,FLEN) +NAN_BOXED(29770,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(26373,16,FLEN) +NAN_BOXED(30575,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30843,16,FLEN) +NAN_BOXED(29581,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31740,16,FLEN) +NAN_BOXED(31076,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31589,16,FLEN) +NAN_BOXED(30721,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30559,16,FLEN) +NAN_BOXED(30858,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31553,16,FLEN) +NAN_BOXED(29215,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29503,16,FLEN) +NAN_BOXED(31488,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30765,16,FLEN) +NAN_BOXED(31444,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31163,16,FLEN) +NAN_BOXED(26643,16,FLEN) +NAN_BOXED(64511,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x12_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x12_1: + .fill 30*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_0: + .fill 20*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x7_0: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x7_1: + .fill 122*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fnmadd_b17-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fnmadd_b17-01.S new file mode 100644 index 000000000..477bb6a95 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fnmadd_b17-01.S @@ -0,0 +1,2219 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 06:03:37 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fnmadd.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fnmadd.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fnmadd_b17 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fnmadd_b17) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x7,test_dataset_0) +RVTEST_SIGBASE(x3,signature_x3_1) + +inst_0: +// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==x8, rs2==x17, rs3==x8, rd==x4,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x394 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x8; op2:x17; op3:x8; dest:x4; op1val:0x7ba5; op2val:0x7b94; +op3val:0x7ba5; valaddr_reg:x7; val_offset:0*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x4, x8, x17, x8, dyn, 0, 0, x7, 0*FLEN/8, x9, x3, x10) + +inst_1: +// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==x30, rs2==x29, rs3==x29, rd==x20,fs1 == 0 and fe1 == 0x1b and fm1 == 0x16d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ae and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x29; dest:x20; op1val:0x6d6d; op2val:0x7aae; +op3val:0x7aae; valaddr_reg:x7; val_offset:3*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x20, x30, x29, x29, dyn, 0, 0, x7, 3*FLEN/8, x9, x3, x10) + +inst_2: +// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==x22, rs2==x18, rs3==x9, rd==x0,fs1 == 0 and fe1 == 0x1e and fm1 == 0x15a and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0ed and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x22; op2:x18; op3:x9; dest:x0; op1val:0x795a; op2val:0x74ed; +op3val:0xfbff; valaddr_reg:x7; val_offset:6*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x0, x22, x18, x9, dyn, 0, 0, x7, 6*FLEN/8, x9, x3, x10) + +inst_3: +// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==x27, rs2==x24, rs3==x14, rd==x24,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0da and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0a5 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x27; op2:x24; op3:x14; dest:x24; op1val:0x78da; op2val:0x78a5; +op3val:0xfbff; valaddr_reg:x7; val_offset:9*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x24, x27, x24, x14, dyn, 0, 0, x7, 9*FLEN/8, x9, x3, x10) + +inst_4: +// rs1 == rd == rs3 != rs2, rs1==x5, rs2==x0, rs3==x5, rd==x5,fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x24b and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x5; op2:x0; op3:x5; dest:x5; op1val:0x76e3; op2val:0x0; +op3val:0x76e3; valaddr_reg:x7; val_offset:12*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x5, x5, x0, x5, dyn, 0, 0, x7, 12*FLEN/8, x9, x3, x10) + +inst_5: +// rs1 == rs2 == rs3 != rd, rs1==x6, rs2==x6, rs3==x6, rd==x1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x397 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x6; op2:x6; op3:x6; dest:x1; op1val:0x7bf4; op2val:0x7bf4; +op3val:0x7bf4; valaddr_reg:x7; val_offset:15*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x1, x6, x6, x6, dyn, 0, 0, x7, 15*FLEN/8, x9, x3, x10) + +inst_6: +// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==x21, rs2==x21, rs3==x31, rd==x15,fs1 == 0 and fe1 == 0x1d and fm1 == 0x31d and fs2 == 0 and fe2 == 0x1d and fm2 == 0x04a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x21; op2:x21; op3:x31; dest:x15; op1val:0x771d; op2val:0x771d; +op3val:0xfbff; valaddr_reg:x7; val_offset:18*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x15, x21, x21, x31, dyn, 0, 0, x7, 18*FLEN/8, x9, x3, x10) + +inst_7: +// rd == rs2 == rs3 != rs1, rs1==x18, rs2==x25, rs3==x25, rd==x25,fs1 == 0 and fe1 == 0x19 and fm1 == 0x305 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x36f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x18; op2:x25; op3:x25; dest:x25; op1val:0x6705; op2val:0x776f; +op3val:0x776f; valaddr_reg:x7; val_offset:21*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x25, x18, x25, x25, dyn, 0, 0, x7, 21*FLEN/8, x9, x3, x10) + +inst_8: +// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==x17, rs2==x2, rs3==x28, rd==x17,fs1 == 0 and fe1 == 0x1d and fm1 == 0x213 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x321 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x17; op2:x2; op3:x28; dest:x17; op1val:0x7613; op2val:0x7b21; +op3val:0xfbff; valaddr_reg:x7; val_offset:24*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x17, x17, x2, x28, dyn, 0, 0, x7, 24*FLEN/8, x9, x3, x10) + +inst_9: +// rs1 == rs2 == rs3 == rd, rs1==x11, rs2==x11, rs3==x11, rd==x11,fs1 == 0 and fe1 == 0x1e and fm1 == 0x07b and fs2 == 0 and fe2 == 0x1c and fm2 == 0x38d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x11; op2:x11; op3:x11; dest:x11; op1val:0x787b; op2val:0x787b; +op3val:0x787b; valaddr_reg:x7; val_offset:27*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x11, x11, x11, x11, dyn, 0, 0, x7, 27*FLEN/8, x9, x3, x10) + +inst_10: +// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==x14, rs2==x8, rs3==x21, rd==x21,fs1 == 0 and fe1 == 0x1d and fm1 == 0x133 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x05f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x14; op2:x8; op3:x21; dest:x21; op1val:0x7533; op2val:0x705f; +op3val:0xfbff; valaddr_reg:x7; val_offset:30*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x21, x14, x8, x21, dyn, 0, 0, x7, 30*FLEN/8, x9, x3, x10) + +inst_11: +// rs1 == rs2 == rd != rs3, rs1==x16, rs2==x16, rs3==x12, rd==x16,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x164 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x16; op2:x16; op3:x12; dest:x16; op1val:0x7bfc; op2val:0x7bfc; +op3val:0xfbff; valaddr_reg:x7; val_offset:33*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x16, x16, x16, x12, dyn, 0, 0, x7, 33*FLEN/8, x9, x3, x10) + +inst_12: +// rs1==x15, rs2==x1, rs3==x24, rd==x19,fs1 == 0 and fe1 == 0x1e and fm1 == 0x325 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x25e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x15; op2:x1; op3:x24; dest:x19; op1val:0x7b25; op2val:0x7a5e; +op3val:0xfbff; valaddr_reg:x7; val_offset:36*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x19, x15, x1, x24, dyn, 0, 0, x7, 36*FLEN/8, x9, x3, x10) + +inst_13: +// rs1==x20, rs2==x19, rs3==x4, rd==x13,fs1 == 0 and fe1 == 0x1e and fm1 == 0x33f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x219 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x20; op2:x19; op3:x4; dest:x13; op1val:0x7b3f; op2val:0x7a19; +op3val:0xfbff; valaddr_reg:x7; val_offset:39*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x13, x20, x19, x4, dyn, 0, 0, x7, 39*FLEN/8, x9, x3, x10) +RVTEST_VALBASEUPD(x4,test_dataset_1) + +inst_14: +// rs1==x26, rs2==x9, rs3==x2, rd==x7,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3d8 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x26; op2:x9; op3:x2; dest:x7; op1val:0x75a8; op2val:0x7bd8; +op3val:0xfbff; valaddr_reg:x4; val_offset:0*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x7, x26, x9, x2, dyn, 0, 0, x4, 0*FLEN/8, x15, x3, x10) +RVTEST_SIGBASE(x11,signature_x11_0) + +inst_15: +// rs1==x0, rs2==x20, rs3==x23, rd==x2,fs1 == 0 and fe1 == 0x1c and fm1 == 0x127 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x207 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x0; op2:x20; op3:x23; dest:x2; op1val:0x0; op2val:0x7a07; +op3val:0xfbff; valaddr_reg:x4; val_offset:3*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x2, x0, x20, x23, dyn, 0, 0, x4, 3*FLEN/8, x15, x11, x6) + +inst_16: +// rs1==x1, rs2==x27, rs3==x13, rd==x22,fs1 == 0 and fe1 == 0x1d and fm1 == 0x360 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x03d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x1; op2:x27; op3:x13; dest:x22; op1val:0x7760; op2val:0x783d; +op3val:0xfbff; valaddr_reg:x4; val_offset:6*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x22, x1, x27, x13, dyn, 0, 0, x4, 6*FLEN/8, x15, x11, x6) + +inst_17: +// rs1==x19, rs2==x23, rs3==x15, rd==x14,fs1 == 0 and fe1 == 0x1e and fm1 == 0x365 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x19; op2:x23; op3:x15; dest:x14; op1val:0x7b65; op2val:0x7801; +op3val:0xfbff; valaddr_reg:x4; val_offset:9*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x14, x19, x23, x15, dyn, 0, 0, x4, 9*FLEN/8, x15, x11, x6) + +inst_18: +// rs1==x7, rs2==x12, rs3==x20, rd==x29,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x30f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x7; op2:x12; op3:x20; dest:x29; op1val:0x75a8; op2val:0x7b0f; +op3val:0xfbff; valaddr_reg:x4; val_offset:12*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x29, x7, x12, x20, dyn, 0, 0, x4, 12*FLEN/8, x15, x11, x6) + +inst_19: +// rs1==x23, rs2==x14, rs3==x0, rd==x28,fs1 == 0 and fe1 == 0x1d and fm1 == 0x35f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x08a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x23; op2:x14; op3:x0; dest:x28; op1val:0x775f; op2val:0x788a; +op3val:0x0; valaddr_reg:x4; val_offset:15*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x28, x23, x14, x0, dyn, 0, 0, x4, 15*FLEN/8, x15, x11, x6) + +inst_20: +// rs1==x13, rs2==x28, rs3==x30, rd==x10,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c9 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3c8 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x13; op2:x28; op3:x30; dest:x10; op1val:0x79c9; op2val:0x77c8; +op3val:0xfbff; valaddr_reg:x4; val_offset:18*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x10, x13, x28, x30, dyn, 0, 0, x4, 18*FLEN/8, x15, x11, x6) + +inst_21: +// rs1==x24, rs2==x10, rs3==x22, rd==x12,fs1 == 0 and fe1 == 0x1d and fm1 == 0x131 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x198 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x24; op2:x10; op3:x22; dest:x12; op1val:0x7531; op2val:0x7998; +op3val:0xfbff; valaddr_reg:x4; val_offset:21*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x12, x24, x10, x22, dyn, 0, 0, x4, 21*FLEN/8, x15, x11, x6) + +inst_22: +// rs1==x9, rs2==x30, rs3==x26, rd==x8,fs1 == 0 and fe1 == 0x1e and fm1 == 0x342 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x049 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x9; op2:x30; op3:x26; dest:x8; op1val:0x7b42; op2val:0x7449; +op3val:0xfbff; valaddr_reg:x4; val_offset:24*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x8, x9, x30, x26, dyn, 0, 0, x4, 24*FLEN/8, x15, x11, x6) + +inst_23: +// rs1==x31, rs2==x5, rs3==x19, rd==x30,fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3a7 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x31; op2:x5; op3:x19; dest:x30; op1val:0x74f3; op2val:0x7ba7; +op3val:0xfbff; valaddr_reg:x4; val_offset:27*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x30, x31, x5, x19, dyn, 0, 0, x4, 27*FLEN/8, x15, x11, x6) +RVTEST_VALBASEUPD(x8,test_dataset_2) + +inst_24: +// rs1==x29, rs2==x13, rs3==x18, rd==x23,fs1 == 0 and fe1 == 0x1e and fm1 == 0x008 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x023 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x29; op2:x13; op3:x18; dest:x23; op1val:0x7808; op2val:0x7823; +op3val:0xfbff; valaddr_reg:x8; val_offset:0*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x23, x29, x13, x18, dyn, 0, 0, x8, 0*FLEN/8, x14, x11, x6) + +inst_25: +// rs1==x25, rs2==x3, rs3==x16, rd==x18,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b3 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0fc and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x25; op2:x3; op3:x16; dest:x18; op1val:0x78b3; op2val:0x74fc; +op3val:0xfbff; valaddr_reg:x8; val_offset:3*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x18, x25, x3, x16, dyn, 0, 0, x8, 3*FLEN/8, x14, x11, x6) + +inst_26: +// rs1==x4, rs2==x22, rs3==x17, rd==x3,fs1 == 0 and fe1 == 0x1e and fm1 == 0x017 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x378 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x4; op2:x22; op3:x17; dest:x3; op1val:0x7817; op2val:0x7b78; +op3val:0xfbff; valaddr_reg:x8; val_offset:6*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x3, x4, x22, x17, dyn, 0, 0, x8, 6*FLEN/8, x14, x11, x6) + +inst_27: +// rs1==x12, rs2==x15, rs3==x7, rd==x6,fs1 == 0 and fe1 == 0x1b and fm1 == 0x0d2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x28f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x12; op2:x15; op3:x7; dest:x6; op1val:0x6cd2; op2val:0x7a8f; +op3val:0xfbff; valaddr_reg:x8; val_offset:9*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x6, x12, x15, x7, dyn, 0, 0, x8, 9*FLEN/8, x14, x11, x5) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_28: +// rs1==x2, rs2==x31, rs3==x3, rd==x27,fs1 == 0 and fe1 == 0x1e and fm1 == 0x341 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x21f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x2; op2:x31; op3:x3; dest:x27; op1val:0x7b41; op2val:0x721f; +op3val:0xfbff; valaddr_reg:x8; val_offset:12*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x27, x2, x31, x3, dyn, 0, 0, x8, 12*FLEN/8, x14, x1, x5) + +inst_29: +// rs1==x28, rs2==x26, rs3==x27, rd==x9,fs1 == 0 and fe1 == 0x1a and fm1 == 0x384 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x138 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x28; op2:x26; op3:x27; dest:x9; op1val:0x6b84; op2val:0x7938; +op3val:0xfbff; valaddr_reg:x8; val_offset:15*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x9, x28, x26, x27, dyn, 0, 0, x8, 15*FLEN/8, x14, x1, x5) + +inst_30: +// rs1==x10, rs2==x4, rs3==x1, rd==x26,fs1 == 0 and fe1 == 0x1c and fm1 == 0x33f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x300 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x10; op2:x4; op3:x1; dest:x26; op1val:0x733f; op2val:0x7b00; +op3val:0xfbff; valaddr_reg:x8; val_offset:18*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x26, x10, x4, x1, dyn, 0, 0, x8, 18*FLEN/8, x14, x1, x5) + +inst_31: +// rs1==x3, rs2==x7, rs3==x10, rd==x31,fs1 == 0 and fe1 == 0x1e and fm1 == 0x02d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2d4 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x3; op2:x7; op3:x10; dest:x31; op1val:0x782d; op2val:0x7ad4; +op3val:0xfbff; valaddr_reg:x8; val_offset:21*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x3, x7, x10, dyn, 0, 0, x8, 21*FLEN/8, x14, x1, x5) + +inst_32: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2bb and fs2 == 0 and fe2 == 0x1e and fm2 == 0x30a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72bb; op2val:0x7b0a; +op3val:0xfbff; valaddr_reg:x8; val_offset:24*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 24*FLEN/8, x14, x1, x5) + +inst_33: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1bb and fs2 == 0 and fe2 == 0x1a and fm2 == 0x013 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79bb; op2val:0x6813; +op3val:0xfbff; valaddr_reg:x8; val_offset:27*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 27*FLEN/8, x14, x1, x5) + +inst_34: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x17f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x161 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x717f; op2val:0x7961; +op3val:0xfbff; valaddr_reg:x8; val_offset:30*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 30*FLEN/8, x14, x1, x5) + +inst_35: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x27c and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ba1; op2val:0x667c; +op3val:0xfbff; valaddr_reg:x8; val_offset:33*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 33*FLEN/8, x14, x1, x5) + +inst_36: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x169 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x016 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6569; op2val:0x7416; +op3val:0xfbff; valaddr_reg:x8; val_offset:36*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 36*FLEN/8, x14, x1, x5) + +inst_37: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x106 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1e0 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7106; op2val:0x71e0; +op3val:0xfbff; valaddr_reg:x8; val_offset:39*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 39*FLEN/8, x14, x1, x5) + +inst_38: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x22a and fs2 == 0 and fe2 == 0x1a and fm2 == 0x185 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x762a; op2val:0x6985; +op3val:0xfbff; valaddr_reg:x8; val_offset:42*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 42*FLEN/8, x14, x1, x5) + +inst_39: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0d7 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x0a3 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70d7; op2val:0x68a3; +op3val:0xfbff; valaddr_reg:x8; val_offset:45*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 45*FLEN/8, x14, x1, x5) + +inst_40: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0eb and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1ef and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78eb; op2val:0x79ef; +op3val:0xfbff; valaddr_reg:x8; val_offset:48*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 48*FLEN/8, x14, x1, x5) + +inst_41: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x164 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x3e2 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7564; op2val:0x67e2; +op3val:0xfbff; valaddr_reg:x8; val_offset:51*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 51*FLEN/8, x14, x1, x5) + +inst_42: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1ea and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a1f; op2val:0x79ea; +op3val:0xfbff; valaddr_reg:x8; val_offset:54*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 54*FLEN/8, x14, x1, x5) + +inst_43: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2e5 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a0a; op2val:0x7ae5; +op3val:0xfbff; valaddr_reg:x8; val_offset:57*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 57*FLEN/8, x14, x1, x5) + +inst_44: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x38f and fs2 == 0 and fe2 == 0x1c and fm2 == 0x336 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x778f; op2val:0x7336; +op3val:0xfbff; valaddr_reg:x8; val_offset:60*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 60*FLEN/8, x14, x1, x5) + +inst_45: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x10e and fs2 == 0 and fe2 == 0x1b and fm2 == 0x287 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x750e; op2val:0x6e87; +op3val:0xfbff; valaddr_reg:x8; val_offset:63*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 63*FLEN/8, x14, x1, x5) + +inst_46: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2fe and fs2 == 0 and fe2 == 0x1c and fm2 == 0x014 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7afe; op2val:0x7014; +op3val:0xfbff; valaddr_reg:x8; val_offset:66*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 66*FLEN/8, x14, x1, x5) + +inst_47: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x248 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x01d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7648; op2val:0x781d; +op3val:0xfbff; valaddr_reg:x8; val_offset:69*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 69*FLEN/8, x14, x1, x5) + +inst_48: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ac and fs2 == 0 and fe2 == 0x1d and fm2 == 0x024 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bac; op2val:0x7424; +op3val:0xfbff; valaddr_reg:x8; val_offset:72*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 72*FLEN/8, x14, x1, x5) + +inst_49: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2b6 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x09d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76b6; op2val:0x649d; +op3val:0xfbff; valaddr_reg:x8; val_offset:75*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 75*FLEN/8, x14, x1, x5) + +inst_50: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x07e and fs2 == 0 and fe2 == 0x1a and fm2 == 0x343 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x707e; op2val:0x6b43; +op3val:0xfbff; valaddr_reg:x8; val_offset:78*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 78*FLEN/8, x14, x1, x5) + +inst_51: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x127 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x221 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7127; op2val:0x6e21; +op3val:0xfbff; valaddr_reg:x8; val_offset:81*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 81*FLEN/8, x14, x1, x5) + +inst_52: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x010 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3dd and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7810; op2val:0x7bdd; +op3val:0xfbff; valaddr_reg:x8; val_offset:84*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 84*FLEN/8, x14, x1, x5) + +inst_53: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f3 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x36f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bf3; op2val:0x736f; +op3val:0xfbff; valaddr_reg:x8; val_offset:87*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 87*FLEN/8, x14, x1, x5) + +inst_54: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0ba and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7402; op2val:0x78ba; +op3val:0xfbff; valaddr_reg:x8; val_offset:90*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 90*FLEN/8, x14, x1, x5) + +inst_55: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x266 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1ac and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a66; op2val:0x79ac; +op3val:0xfbff; valaddr_reg:x8; val_offset:93*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 93*FLEN/8, x14, x1, x5) + +inst_56: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2c3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x035 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76c3; op2val:0x7835; +op3val:0xfbff; valaddr_reg:x8; val_offset:96*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 96*FLEN/8, x14, x1, x5) + +inst_57: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x08a and fs2 == 0 and fe2 == 0x1d and fm2 == 0x289 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x688a; op2val:0x7689; +op3val:0xfbff; valaddr_reg:x8; val_offset:99*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 99*FLEN/8, x14, x1, x5) + +inst_58: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c9 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3b4 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79c9; op2val:0x73b4; +op3val:0xfbff; valaddr_reg:x8; val_offset:102*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 102*FLEN/8, x14, x1, x5) + +inst_59: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1d0 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x367 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71d0; op2val:0x7367; +op3val:0xfbff; valaddr_reg:x8; val_offset:105*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 105*FLEN/8, x14, x1, x5) + +inst_60: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x029 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x36d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7829; op2val:0x776d; +op3val:0xfbff; valaddr_reg:x8; val_offset:108*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 108*FLEN/8, x14, x1, x5) + +inst_61: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x121 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2cb and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7921; op2val:0x72cb; +op3val:0xfbff; valaddr_reg:x8; val_offset:111*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 111*FLEN/8, x14, x1, x5) + +inst_62: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1d4 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bb3; op2val:0x79d4; +op3val:0xfbff; valaddr_reg:x8; val_offset:114*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 114*FLEN/8, x14, x1, x5) + +inst_63: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x017 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0a5 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7817; op2val:0x78a5; +op3val:0xfbff; valaddr_reg:x8; val_offset:117*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 117*FLEN/8, x14, x1, x5) + +inst_64: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2af and fs2 == 0 and fe2 == 0x1e and fm2 == 0x032 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76af; op2val:0x7832; +op3val:0xfbff; valaddr_reg:x8; val_offset:120*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 120*FLEN/8, x14, x1, x5) + +inst_65: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x26b and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dff; op2val:0x7a6b; +op3val:0xfbff; valaddr_reg:x8; val_offset:123*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 123*FLEN/8, x14, x1, x5) + +inst_66: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x026 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x35e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7826; op2val:0x7b5e; +op3val:0xfbff; valaddr_reg:x8; val_offset:126*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 126*FLEN/8, x14, x1, x5) + +inst_67: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3dd and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74a1; op2val:0x7bdd; +op3val:0xfbff; valaddr_reg:x8; val_offset:129*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 129*FLEN/8, x14, x1, x5) + +inst_68: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x0e0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x17a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x64e0; op2val:0x797a; +op3val:0xfbff; valaddr_reg:x8; val_offset:132*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 132*FLEN/8, x14, x1, x5) + +inst_69: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0e4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b8 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74e4; op2val:0x7ab8; +op3val:0xfbff; valaddr_reg:x8; val_offset:135*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 135*FLEN/8, x14, x1, x5) + +inst_70: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x005 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x338 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6405; op2val:0x7738; +op3val:0xfbff; valaddr_reg:x8; val_offset:138*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 138*FLEN/8, x14, x1, x5) + +inst_71: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3c5 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2a9 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77c5; op2val:0x72a9; +op3val:0xfbff; valaddr_reg:x8; val_offset:141*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 141*FLEN/8, x14, x1, x5) + +inst_72: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0b8 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x08c and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6cb8; op2val:0x748c; +op3val:0xfbff; valaddr_reg:x8; val_offset:144*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 144*FLEN/8, x14, x1, x5) + +inst_73: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37a and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0e5 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b7a; op2val:0x6ce5; +op3val:0xfbff; valaddr_reg:x8; val_offset:147*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 147*FLEN/8, x14, x1, x5) + +inst_74: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x227 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x091 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7227; op2val:0x7891; +op3val:0xfbff; valaddr_reg:x8; val_offset:150*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 150*FLEN/8, x14, x1, x5) + +inst_75: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x368 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x206 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7768; op2val:0x7a06; +op3val:0xfbff; valaddr_reg:x8; val_offset:153*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 153*FLEN/8, x14, x1, x5) + +inst_76: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3c9 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3ca and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6fc9; op2val:0x6fca; +op3val:0xfbff; valaddr_reg:x8; val_offset:156*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 156*FLEN/8, x14, x1, x5) + +inst_77: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2cc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x120 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7acc; op2val:0x7920; +op3val:0xfbff; valaddr_reg:x8; val_offset:159*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 159*FLEN/8, x14, x1, x5) + +inst_78: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x189 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x24f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7989; op2val:0x664f; +op3val:0xfbff; valaddr_reg:x8; val_offset:162*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 162*FLEN/8, x14, x1, x5) + +inst_79: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x236 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1c9 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a36; op2val:0x79c9; +op3val:0xfbff; valaddr_reg:x8; val_offset:165*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 165*FLEN/8, x14, x1, x5) + +inst_80: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1b7 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x34f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75b7; op2val:0x774f; +op3val:0xfbff; valaddr_reg:x8; val_offset:168*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 168*FLEN/8, x14, x1, x5) + +inst_81: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x04d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x035 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x744d; op2val:0x7835; +op3val:0xfbff; valaddr_reg:x8; val_offset:171*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 171*FLEN/8, x14, x1, x5) + +inst_82: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x26e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ba2; op2val:0x7a6e; +op3val:0xfbff; valaddr_reg:x8; val_offset:174*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 174*FLEN/8, x14, x1, x5) + +inst_83: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2af and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0be and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aaf; op2val:0x74be; +op3val:0xfbff; valaddr_reg:x8; val_offset:177*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 177*FLEN/8, x14, x1, x5) + +inst_84: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d1 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x026 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77d1; op2val:0x7426; +op3val:0xfbff; valaddr_reg:x8; val_offset:180*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 180*FLEN/8, x14, x1, x5) + +inst_85: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x16e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x358 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x796e; op2val:0x7b58; +op3val:0xfbff; valaddr_reg:x8; val_offset:183*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 183*FLEN/8, x14, x1, x5) + +inst_86: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28a and fs2 == 0 and fe2 == 0x1b and fm2 == 0x223 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8a; op2val:0x6e23; +op3val:0xfbff; valaddr_reg:x8; val_offset:186*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 186*FLEN/8, x14, x1, x5) + +inst_87: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3fa and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0af and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bfa; op2val:0x70af; +op3val:0xfbff; valaddr_reg:x8; val_offset:189*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 189*FLEN/8, x14, x1, x5) + +inst_88: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x046 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x182 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c46; op2val:0x6d82; +op3val:0xfbff; valaddr_reg:x8; val_offset:192*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 192*FLEN/8, x14, x1, x5) + +inst_89: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x12e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7be7; op2val:0x792e; +op3val:0xfbff; valaddr_reg:x8; val_offset:195*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 195*FLEN/8, x14, x1, x5) + +inst_90: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0bd and fs2 == 0 and fe2 == 0x1c and fm2 == 0x369 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74bd; op2val:0x7369; +op3val:0xfbff; valaddr_reg:x8; val_offset:198*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 198*FLEN/8, x14, x1, x5) + +inst_91: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x172 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x304 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7972; op2val:0x7704; +op3val:0xfbff; valaddr_reg:x8; val_offset:201*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 201*FLEN/8, x14, x1, x5) + +inst_92: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x32b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x053 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f2b; op2val:0x7853; +op3val:0xfbff; valaddr_reg:x8; val_offset:204*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 204*FLEN/8, x14, x1, x5) + +inst_93: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20b and fs2 == 0 and fe2 == 0x1b and fm2 == 0x226 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a0b; op2val:0x6e26; +op3val:0xfbff; valaddr_reg:x8; val_offset:207*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 207*FLEN/8, x14, x1, x5) + +inst_94: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b8 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x01d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79b8; op2val:0x741d; +op3val:0xfbff; valaddr_reg:x8; val_offset:210*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 210*FLEN/8, x14, x1, x5) + +inst_95: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x35f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x19f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x775f; op2val:0x799f; +op3val:0xfbff; valaddr_reg:x8; val_offset:213*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 213*FLEN/8, x14, x1, x5) + +inst_96: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x242 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bf5; op2val:0x7a42; +op3val:0xfbff; valaddr_reg:x8; val_offset:216*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 216*FLEN/8, x14, x1, x5) + +inst_97: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0a1 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x30e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70a1; op2val:0x770e; +op3val:0xfbff; valaddr_reg:x8; val_offset:219*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 219*FLEN/8, x14, x1, x5) + +inst_98: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x30d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78c2; op2val:0x7b0d; +op3val:0xfbff; valaddr_reg:x8; val_offset:222*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 222*FLEN/8, x14, x1, x5) + +inst_99: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x014 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3b7 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7814; op2val:0x77b7; +op3val:0xfbff; valaddr_reg:x8; val_offset:225*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 225*FLEN/8, x14, x1, x5) + +inst_100: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ae and fs2 == 0 and fe2 == 0x1e and fm2 == 0x37d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79ae; op2val:0x7b7d; +op3val:0xfbff; valaddr_reg:x8; val_offset:228*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 228*FLEN/8, x14, x1, x5) + +inst_101: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x38e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3b1 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x778e; op2val:0x7bb1; +op3val:0xfbff; valaddr_reg:x8; val_offset:231*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 231*FLEN/8, x14, x1, x5) + +inst_102: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x143 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f6; op2val:0x7943; +op3val:0xfbff; valaddr_reg:x8; val_offset:234*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 234*FLEN/8, x14, x1, x5) + +inst_103: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d0 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x332 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ad0; op2val:0x7332; +op3val:0xfbff; valaddr_reg:x8; val_offset:237*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 237*FLEN/8, x14, x1, x5) + +inst_104: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x270 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7670; op2val:0x7955; +op3val:0xfbff; valaddr_reg:x8; val_offset:240*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 240*FLEN/8, x14, x1, x5) + +inst_105: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x1f0 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7913; op2val:0x61f0; +op3val:0xfbff; valaddr_reg:x8; val_offset:243*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 243*FLEN/8, x14, x1, x5) + +inst_106: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x30f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79b0; op2val:0x7b0f; +op3val:0xfbff; valaddr_reg:x8; val_offset:246*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 246*FLEN/8, x14, x1, x5) + +inst_107: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x286 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x062 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a86; op2val:0x6462; +op3val:0xfbff; valaddr_reg:x8; val_offset:249*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 249*FLEN/8, x14, x1, x5) + +inst_108: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0d9 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79d5; op2val:0x78d9; +op3val:0xfbff; valaddr_reg:x8; val_offset:252*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 252*FLEN/8, x14, x1, x5) + +inst_109: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x312 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x26d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b12; op2val:0x6e6d; +op3val:0xfbff; valaddr_reg:x8; val_offset:255*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 255*FLEN/8, x14, x1, x5) + +inst_110: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x222 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x261 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a22; op2val:0x7261; +op3val:0xfbff; valaddr_reg:x8; val_offset:258*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 258*FLEN/8, x14, x1, x5) + +inst_111: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b0 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x21f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78b0; op2val:0x721f; +op3val:0xfbff; valaddr_reg:x8; val_offset:261*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 261*FLEN/8, x14, x1, x5) + +inst_112: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x068 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0e5 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7068; op2val:0x78e5; +op3val:0xfbff; valaddr_reg:x8; val_offset:264*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 264*FLEN/8, x14, x1, x5) + +inst_113: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x00e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x086 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x740e; op2val:0x7886; +op3val:0xfbff; valaddr_reg:x8; val_offset:267*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 267*FLEN/8, x14, x1, x5) + +inst_114: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x28e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3bb and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x728e; op2val:0x7bbb; +op3val:0xfbff; valaddr_reg:x8; val_offset:270*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 270*FLEN/8, x14, x1, x5) + +inst_115: +// fs1 == 0 and fe1 == 0x16 and fm1 == 0x237 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3c3 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5a37; op2val:0x77c3; +op3val:0xfbff; valaddr_reg:x8; val_offset:273*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 273*FLEN/8, x14, x1, x5) + +inst_116: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x143 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x208 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7943; op2val:0x7a08; +op3val:0xfbff; valaddr_reg:x8; val_offset:276*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 276*FLEN/8, x14, x1, x5) + +inst_117: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x165 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x15b and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7965; op2val:0x755b; +op3val:0xfbff; valaddr_reg:x8; val_offset:279*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 279*FLEN/8, x14, x1, x5) + +inst_118: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x005 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x30b and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7805; op2val:0x670b; +op3val:0xfbff; valaddr_reg:x8; val_offset:282*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 282*FLEN/8, x14, x1, x5) + +inst_119: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x207 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x18e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a07; op2val:0x718e; +op3val:0xfbff; valaddr_reg:x8; val_offset:285*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 285*FLEN/8, x14, x1, x5) + +inst_120: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x245 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x277 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a45; op2val:0x7677; +op3val:0xfbff; valaddr_reg:x8; val_offset:288*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 288*FLEN/8, x14, x1, x5) + +inst_121: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x24b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2e8 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a4b; op2val:0x7ae8; +op3val:0xfbff; valaddr_reg:x8; val_offset:291*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 291*FLEN/8, x14, x1, x5) + +inst_122: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x133 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x21a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7133; op2val:0x761a; +op3val:0xfbff; valaddr_reg:x8; val_offset:294*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 294*FLEN/8, x14, x1, x5) + +inst_123: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0b6 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x152 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74b6; op2val:0x6152; +op3val:0xfbff; valaddr_reg:x8; val_offset:297*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 297*FLEN/8, x14, x1, x5) + +inst_124: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3bb and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1dc and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bbb; op2val:0x75dc; +op3val:0xfbff; valaddr_reg:x8; val_offset:300*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 300*FLEN/8, x14, x1, x5) + +inst_125: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x21d and fs2 == 0 and fe2 == 0x1d and fm2 == 0x314 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x761d; op2val:0x7714; +op3val:0xfbff; valaddr_reg:x8; val_offset:303*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 303*FLEN/8, x14, x1, x5) + +inst_126: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ee and fs2 == 0 and fe2 == 0x1e and fm2 == 0x130 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74ee; op2val:0x7930; +op3val:0xfbff; valaddr_reg:x8; val_offset:306*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 306*FLEN/8, x14, x1, x5) + +inst_127: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x350 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x784e; op2val:0x7b50; +op3val:0xfbff; valaddr_reg:x8; val_offset:309*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 309*FLEN/8, x14, x1, x5) + +inst_128: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x297 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0dd and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a97; op2val:0x74dd; +op3val:0xfbff; valaddr_reg:x8; val_offset:312*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 312*FLEN/8, x14, x1, x5) + +inst_129: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x139 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5d; op2val:0x7939; +op3val:0xfbff; valaddr_reg:x8; val_offset:315*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 315*FLEN/8, x14, x1, x5) + +inst_130: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b8 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x1f2 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ab8; op2val:0x6df2; +op3val:0xfbff; valaddr_reg:x8; val_offset:318*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 318*FLEN/8, x14, x1, x5) + +inst_131: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x241 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x03d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7641; op2val:0x783d; +op3val:0xfbff; valaddr_reg:x8; val_offset:321*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 321*FLEN/8, x14, x1, x5) + +inst_132: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x261 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x107 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a61; op2val:0x7907; +op3val:0xfbff; valaddr_reg:x8; val_offset:324*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 324*FLEN/8, x14, x1, x5) + +inst_133: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x373 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x351 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7373; op2val:0x7751; +op3val:0xfbff; valaddr_reg:x8; val_offset:327*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 327*FLEN/8, x14, x1, x5) + +inst_134: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x070 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3a8 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7470; op2val:0x7ba8; +op3val:0xfbff; valaddr_reg:x8; val_offset:330*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 330*FLEN/8, x14, x1, x5) + +inst_135: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28b and fs2 == 0 and fe2 == 0x1d and fm2 == 0x210 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8b; op2val:0x7610; +op3val:0xfbff; valaddr_reg:x8; val_offset:333*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 333*FLEN/8, x14, x1, x5) + +inst_136: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x117 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0f3 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7517; op2val:0x6cf3; +op3val:0xfbff; valaddr_reg:x8; val_offset:336*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 336*FLEN/8, x14, x1, x5) + +inst_137: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x153 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x311 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7153; op2val:0x7711; +op3val:0xfbff; valaddr_reg:x8; val_offset:339*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 339*FLEN/8, x14, x1, x5) + +inst_138: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x327 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x35e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b27; op2val:0x7b5e; +op3val:0xfbff; valaddr_reg:x8; val_offset:342*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 342*FLEN/8, x14, x1, x5) + +inst_139: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x11d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x36e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x791d; op2val:0x7b6e; +op3val:0xfbff; valaddr_reg:x8; val_offset:345*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 345*FLEN/8, x14, x1, x5) + +inst_140: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x25e and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39b and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e5e; op2val:0x739b; +op3val:0xfbff; valaddr_reg:x8; val_offset:348*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 348*FLEN/8, x14, x1, x5) + +inst_141: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x16c and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1fa and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x796c; op2val:0x75fa; +op3val:0xfbff; valaddr_reg:x8; val_offset:351*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 351*FLEN/8, x14, x1, x5) + +inst_142: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25b and fs2 == 0 and fe2 == 0x1c and fm2 == 0x375 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5b; op2val:0x7375; +op3val:0xfbff; valaddr_reg:x8; val_offset:354*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 354*FLEN/8, x14, x1, x5) + +inst_143: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x10f and fs2 == 0 and fe2 == 0x1d and fm2 == 0x266 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x790f; op2val:0x7666; +op3val:0xfbff; valaddr_reg:x8; val_offset:357*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 357*FLEN/8, x14, x1, x5) + +inst_144: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x179 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x306 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7579; op2val:0x7b06; +op3val:0xfbff; valaddr_reg:x8; val_offset:360*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 360*FLEN/8, x14, x1, x5) + +inst_145: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x184 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7804; op2val:0x7984; +op3val:0xfbff; valaddr_reg:x8; val_offset:363*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 363*FLEN/8, x14, x1, x5) + +inst_146: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f0; op2val:0x7a01; +op3val:0xfbff; valaddr_reg:x8; val_offset:366*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 366*FLEN/8, x14, x1, x5) + +inst_147: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x206 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b7b; op2val:0x7a06; +op3val:0xfbff; valaddr_reg:x8; val_offset:369*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 369*FLEN/8, x14, x1, x5) + +inst_148: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0fa and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74a9; op2val:0x78fa; +op3val:0xfbff; valaddr_reg:x8; val_offset:372*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 372*FLEN/8, x14, x1, x5) + +inst_149: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1e0 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x251 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75e0; op2val:0x7651; +op3val:0xfbff; valaddr_reg:x8; val_offset:375*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 375*FLEN/8, x14, x1, x5) + +inst_150: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a8 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1a9 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ba8; op2val:0x75a9; +op3val:0xfbff; valaddr_reg:x8; val_offset:378*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 378*FLEN/8, x14, x1, x5) + +inst_151: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x325 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1f6 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b25; op2val:0x71f6; +op3val:0xfbff; valaddr_reg:x8; val_offset:381*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 381*FLEN/8, x14, x1, x5) + +inst_152: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x010 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x32c and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7010; op2val:0x672c; +op3val:0xfbff; valaddr_reg:x8; val_offset:384*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 384*FLEN/8, x14, x1, x5) + +inst_153: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1be and fs2 == 0 and fe2 == 0x1e and fm2 == 0x356 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75be; op2val:0x7b56; +op3val:0xfbff; valaddr_reg:x8; val_offset:387*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 387*FLEN/8, x14, x1, x5) + +inst_154: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x216 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2fa and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a16; op2val:0x76fa; +op3val:0xfbff; valaddr_reg:x8; val_offset:390*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 390*FLEN/8, x14, x1, x5) + +inst_155: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x392 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2aa and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7392; op2val:0x7aaa; +op3val:0xfbff; valaddr_reg:x8; val_offset:393*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 393*FLEN/8, x14, x1, x5) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_156: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x08d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x119 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x748d; op2val:0x7919; +op3val:0xfbff; valaddr_reg:x8; val_offset:396*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 396*FLEN/8, x14, x1, x5) + +inst_157: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x10f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x367 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x750f; op2val:0x7b67; +op3val:0xfbff; valaddr_reg:x8; val_offset:399*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 399*FLEN/8, x14, x1, x5) + +inst_158: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x08c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x289 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x708c; op2val:0x7289; +op3val:0xfbff; valaddr_reg:x8; val_offset:402*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 402*FLEN/8, x14, x1, x5) + +inst_159: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2b9 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76b9; op2val:0x7400; +op3val:0xfbff; valaddr_reg:x8; val_offset:405*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 405*FLEN/8, x14, x1, x5) + +inst_160: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3e2 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3ad and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73e2; op2val:0x73ad; +op3val:0xfbff; valaddr_reg:x8; val_offset:408*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 408*FLEN/8, x14, x1, x5) + +inst_161: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x161 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1f6 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7561; op2val:0x75f6; +op3val:0xfbff; valaddr_reg:x8; val_offset:411*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 411*FLEN/8, x14, x1, x5) + +inst_162: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3e4 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x09b and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6be4; op2val:0x709b; +op3val:0xfbff; valaddr_reg:x8; val_offset:414*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 414*FLEN/8, x14, x1, x5) + +inst_163: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2df and fs2 == 0 and fe2 == 0x1e and fm2 == 0x23a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76df; op2val:0x7a3a; +op3val:0xfbff; valaddr_reg:x8; val_offset:417*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 417*FLEN/8, x14, x1, x5) + +inst_164: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c2 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x782e; op2val:0x7ac2; +op3val:0xfbff; valaddr_reg:x8; val_offset:420*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 420*FLEN/8, x14, x1, x5) + +inst_165: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x224 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0e1 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a24; op2val:0x78e1; +op3val:0xfbff; valaddr_reg:x8; val_offset:423*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 423*FLEN/8, x14, x1, x5) + +inst_166: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f9 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x246 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bf9; op2val:0x7646; +op3val:0xfbff; valaddr_reg:x8; val_offset:426*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 426*FLEN/8, x14, x1, x5) + +inst_167: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0f4 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x111 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78f4; op2val:0x7511; +op3val:0xfbff; valaddr_reg:x8; val_offset:429*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 429*FLEN/8, x14, x1, x5) + +inst_168: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0b3 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78c7; op2val:0x78b3; +op3val:0xfbff; valaddr_reg:x8; val_offset:432*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 432*FLEN/8, x14, x1, x5) + +inst_169: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3e8 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7be0; op2val:0x7be8; +op3val:0xfbff; valaddr_reg:x8; val_offset:435*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 435*FLEN/8, x14, x1, x5) + +inst_170: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x345 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x295 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7745; op2val:0x7695; +op3val:0xfbff; valaddr_reg:x8; val_offset:438*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 438*FLEN/8, x14, x1, x5) + +inst_171: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x1e7 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2ec and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x69e7; op2val:0x6eec; +op3val:0xfbff; valaddr_reg:x8; val_offset:441*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 441*FLEN/8, x14, x1, x5) + +inst_172: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x019 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x37e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7019; op2val:0x7b7e; +op3val:0xfbff; valaddr_reg:x8; val_offset:444*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 444*FLEN/8, x14, x1, x5) + +inst_173: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x351 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0f2 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b51; op2val:0x6cf2; +op3val:0xfbff; valaddr_reg:x8; val_offset:447*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 447*FLEN/8, x14, x1, x5) + +inst_174: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x261 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x086 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a61; op2val:0x6086; +op3val:0xfbff; valaddr_reg:x8; val_offset:450*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 450*FLEN/8, x14, x1, x5) + +inst_175: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x19b and fs2 == 0 and fe2 == 0x1c and fm2 == 0x189 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x759b; op2val:0x7189; +op3val:0xfbff; valaddr_reg:x8; val_offset:453*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 453*FLEN/8, x14, x1, x5) + +inst_176: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15b and fs2 == 0 and fe2 == 0x1b and fm2 == 0x1e1 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x795b; op2val:0x6de1; +op3val:0xfbff; valaddr_reg:x8; val_offset:456*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 456*FLEN/8, x14, x1, x5) + +inst_177: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x131 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x25d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7931; op2val:0x6a5d; +op3val:0xfbff; valaddr_reg:x8; val_offset:459*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 459*FLEN/8, x14, x1, x5) + +inst_178: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3b9 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3b3 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73b9; op2val:0x77b3; +op3val:0xfbff; valaddr_reg:x8; val_offset:462*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 462*FLEN/8, x14, x1, x5) + +inst_179: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x06f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x003 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x706f; op2val:0x7803; +op3val:0xfbff; valaddr_reg:x8; val_offset:465*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 465*FLEN/8, x14, x1, x5) + +inst_180: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x262 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x358 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7262; op2val:0x7b58; +op3val:0xfbff; valaddr_reg:x8; val_offset:468*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 468*FLEN/8, x14, x1, x5) + +inst_181: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x173 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x782e; op2val:0x7973; +op3val:0xfbff; valaddr_reg:x8; val_offset:471*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 471*FLEN/8, x14, x1, x5) + +inst_182: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x07a and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3de and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x707a; op2val:0x77de; +op3val:0xfbff; valaddr_reg:x8; val_offset:474*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 474*FLEN/8, x14, x1, x5) + +inst_183: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x374 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2ec and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f74; op2val:0x6eec; +op3val:0xfbff; valaddr_reg:x8; val_offset:477*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 477*FLEN/8, x14, x1, x5) + +inst_184: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x2cc and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2e2 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6acc; op2val:0x72e2; +op3val:0xfbff; valaddr_reg:x8; val_offset:480*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 480*FLEN/8, x14, x1, x5) + +inst_185: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fa and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2dd and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fa; op2val:0x7add; +op3val:0xfbff; valaddr_reg:x8; val_offset:483*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 483*FLEN/8, x14, x1, x5) + +inst_186: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1bc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x00e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79bc; op2val:0x780e; +op3val:0xfbff; valaddr_reg:x8; val_offset:486*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 486*FLEN/8, x14, x1, x5) + +inst_187: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x136 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2be and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7136; op2val:0x6ebe; +op3val:0xfbff; valaddr_reg:x8; val_offset:489*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 489*FLEN/8, x14, x1, x5) + +inst_188: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x103 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2ba and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7903; op2val:0x72ba; +op3val:0xfbff; valaddr_reg:x8; val_offset:492*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 492*FLEN/8, x14, x1, x5) + +inst_189: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0c1 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2e3 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74c1; op2val:0x76e3; +op3val:0xfbff; valaddr_reg:x8; val_offset:495*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 495*FLEN/8, x14, x1, x5) + +inst_190: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x25e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x260 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x765e; op2val:0x7a60; +op3val:0xfbff; valaddr_reg:x8; val_offset:498*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 498*FLEN/8, x14, x1, x5) + +inst_191: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x07f and fs2 == 0 and fe2 == 0x1d and fm2 == 0x38f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x787f; op2val:0x778f; +op3val:0xfbff; valaddr_reg:x8; val_offset:501*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 501*FLEN/8, x14, x1, x5) + +inst_192: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x21e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3e4 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a1e; op2val:0x7be4; +op3val:0xfbff; valaddr_reg:x8; val_offset:504*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 504*FLEN/8, x14, x1, x5) + +inst_193: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x196 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x799f; op2val:0x7996; +op3val:0xfbff; valaddr_reg:x8; val_offset:507*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 507*FLEN/8, x14, x1, x5) + +inst_194: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x3d5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x069 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x67d5; op2val:0x7869; +op3val:0xfbff; valaddr_reg:x8; val_offset:510*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 510*FLEN/8, x14, x1, x5) + +inst_195: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x237 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0a2 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7237; op2val:0x78a2; +op3val:0xfbff; valaddr_reg:x8; val_offset:513*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 513*FLEN/8, x14, x1, x5) + +inst_196: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1ef and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7900; op2val:0x79ef; +op3val:0xfbff; valaddr_reg:x8; val_offset:516*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 516*FLEN/8, x14, x1, x5) + +inst_197: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x399 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x21d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7799; op2val:0x6a1d; +op3val:0xfbff; valaddr_reg:x8; val_offset:519*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 519*FLEN/8, x14, x1, x5) + +inst_198: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x294 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ae and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a94; op2val:0x7aae; +op3val:0xfbff; valaddr_reg:x8; val_offset:522*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 522*FLEN/8, x14, x1, x5) + +inst_199: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x0e2 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x243 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x68e2; op2val:0x7243; +op3val:0xfbff; valaddr_reg:x8; val_offset:525*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 525*FLEN/8, x14, x1, x5) + +inst_200: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x394 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ba5; op2val:0x7b94; +op3val:0xfbff; valaddr_reg:x8; val_offset:528*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 528*FLEN/8, x14, x1, x5) + +inst_201: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x16d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ae and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d6d; op2val:0x7aae; +op3val:0xfbff; valaddr_reg:x8; val_offset:531*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 531*FLEN/8, x14, x1, x5) + +inst_202: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15a and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0ed and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x795a; op2val:0x74ed; +op3val:0xfbff; valaddr_reg:x8; val_offset:534*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 534*FLEN/8, x14, x1, x5) + +inst_203: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x24b and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76e3; op2val:0x764b; +op3val:0xfbff; valaddr_reg:x8; val_offset:537*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 537*FLEN/8, x14, x1, x5) + +inst_204: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x397 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bf4; op2val:0x7b97; +op3val:0xfbff; valaddr_reg:x8; val_offset:540*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 540*FLEN/8, x14, x1, x5) + +inst_205: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31d and fs2 == 0 and fe2 == 0x1d and fm2 == 0x04a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x771d; op2val:0x744a; +op3val:0xfbff; valaddr_reg:x8; val_offset:543*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 543*FLEN/8, x14, x1, x5) + +inst_206: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x305 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x36f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6705; op2val:0x776f; +op3val:0xfbff; valaddr_reg:x8; val_offset:546*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 546*FLEN/8, x14, x1, x5) + +inst_207: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x07b and fs2 == 0 and fe2 == 0x1c and fm2 == 0x38d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x787b; op2val:0x738d; +op3val:0xfbff; valaddr_reg:x8; val_offset:549*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 549*FLEN/8, x14, x1, x5) + +inst_208: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x164 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bfc; op2val:0x7964; +op3val:0xfbff; valaddr_reg:x8; val_offset:552*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 552*FLEN/8, x14, x1, x5) + +inst_209: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x127 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x207 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7127; op2val:0x7a07; +op3val:0xfbff; valaddr_reg:x8; val_offset:555*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 555*FLEN/8, x14, x1, x5) + +inst_210: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x35f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x08a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x775f; op2val:0x788a; +op3val:0xfbff; valaddr_reg:x8; val_offset:558*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x8, 558*FLEN/8, x14, x1, x5) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(31653,32,FLEN) +NAN_BOXED(31636,32,FLEN) +NAN_BOXED(31653,16,FLEN) +NAN_BOXED(28013,32,FLEN) +NAN_BOXED(31406,32,FLEN) +NAN_BOXED(31406,16,FLEN) +NAN_BOXED(31066,32,FLEN) +NAN_BOXED(29933,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30938,32,FLEN) +NAN_BOXED(30885,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30435,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(30435,16,FLEN) +NAN_BOXED(31732,32,FLEN) +NAN_BOXED(31732,32,FLEN) +NAN_BOXED(31732,16,FLEN) +NAN_BOXED(30493,32,FLEN) +NAN_BOXED(30493,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(26373,32,FLEN) +NAN_BOXED(30575,32,FLEN) +NAN_BOXED(30575,16,FLEN) +NAN_BOXED(30227,32,FLEN) +NAN_BOXED(31521,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30843,32,FLEN) +NAN_BOXED(30843,32,FLEN) +NAN_BOXED(30843,16,FLEN) +NAN_BOXED(30003,32,FLEN) +NAN_BOXED(28767,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31740,32,FLEN) +NAN_BOXED(31740,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31525,32,FLEN) +NAN_BOXED(31326,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31551,32,FLEN) +NAN_BOXED(31257,32,FLEN) +NAN_BOXED(64511,16,FLEN) +test_dataset_1: +NAN_BOXED(30120,32,FLEN) +NAN_BOXED(31704,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31239,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30560,32,FLEN) +NAN_BOXED(30781,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31589,32,FLEN) +NAN_BOXED(30721,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30120,32,FLEN) +NAN_BOXED(31503,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30559,32,FLEN) +NAN_BOXED(30858,32,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31177,32,FLEN) +NAN_BOXED(30664,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30001,32,FLEN) +NAN_BOXED(31128,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31554,32,FLEN) +NAN_BOXED(29769,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29939,32,FLEN) +NAN_BOXED(31655,32,FLEN) +NAN_BOXED(64511,16,FLEN) +test_dataset_2: +NAN_BOXED(30728,16,FLEN) +NAN_BOXED(30755,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30899,16,FLEN) +NAN_BOXED(29948,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30743,16,FLEN) +NAN_BOXED(31608,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(27858,16,FLEN) +NAN_BOXED(31375,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31553,16,FLEN) +NAN_BOXED(29215,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(27524,16,FLEN) +NAN_BOXED(31032,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29503,16,FLEN) +NAN_BOXED(31488,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30765,16,FLEN) +NAN_BOXED(31444,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29371,16,FLEN) +NAN_BOXED(31498,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31163,16,FLEN) +NAN_BOXED(26643,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29055,16,FLEN) +NAN_BOXED(31073,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31649,16,FLEN) +NAN_BOXED(26236,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(25961,16,FLEN) +NAN_BOXED(29718,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28934,16,FLEN) +NAN_BOXED(29152,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30250,16,FLEN) +NAN_BOXED(27013,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28887,16,FLEN) +NAN_BOXED(26787,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30955,16,FLEN) +NAN_BOXED(31215,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30052,16,FLEN) +NAN_BOXED(26594,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31263,16,FLEN) +NAN_BOXED(31210,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31242,16,FLEN) +NAN_BOXED(31461,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30607,16,FLEN) +NAN_BOXED(29494,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29966,16,FLEN) +NAN_BOXED(28295,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31486,16,FLEN) +NAN_BOXED(28692,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30280,16,FLEN) +NAN_BOXED(30749,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31660,16,FLEN) +NAN_BOXED(29732,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30390,16,FLEN) +NAN_BOXED(25757,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28798,16,FLEN) +NAN_BOXED(27459,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28967,16,FLEN) +NAN_BOXED(28193,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30736,16,FLEN) +NAN_BOXED(31709,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31731,16,FLEN) +NAN_BOXED(29551,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29698,16,FLEN) +NAN_BOXED(30906,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31334,16,FLEN) +NAN_BOXED(31148,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30403,16,FLEN) +NAN_BOXED(30773,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(26762,16,FLEN) +NAN_BOXED(30345,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31177,16,FLEN) +NAN_BOXED(29620,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29136,16,FLEN) +NAN_BOXED(29543,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30761,16,FLEN) +NAN_BOXED(30573,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31009,16,FLEN) +NAN_BOXED(29387,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31667,16,FLEN) +NAN_BOXED(31188,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30743,16,FLEN) +NAN_BOXED(30885,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30383,16,FLEN) +NAN_BOXED(30770,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28159,16,FLEN) +NAN_BOXED(31339,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30758,16,FLEN) +NAN_BOXED(31582,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29857,16,FLEN) +NAN_BOXED(31709,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(25824,16,FLEN) +NAN_BOXED(31098,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29924,16,FLEN) +NAN_BOXED(31416,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(25605,16,FLEN) +NAN_BOXED(30520,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30661,16,FLEN) +NAN_BOXED(29353,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(27832,16,FLEN) +NAN_BOXED(29836,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31610,16,FLEN) +NAN_BOXED(27877,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29223,16,FLEN) +NAN_BOXED(30865,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30568,16,FLEN) +NAN_BOXED(31238,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28617,16,FLEN) +NAN_BOXED(28618,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31436,16,FLEN) +NAN_BOXED(31008,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31113,16,FLEN) +NAN_BOXED(26191,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31286,16,FLEN) +NAN_BOXED(31177,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30135,16,FLEN) +NAN_BOXED(30543,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29773,16,FLEN) +NAN_BOXED(30773,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31650,16,FLEN) +NAN_BOXED(31342,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31407,16,FLEN) +NAN_BOXED(29886,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30673,16,FLEN) +NAN_BOXED(29734,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31086,16,FLEN) +NAN_BOXED(31576,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31370,16,FLEN) +NAN_BOXED(28195,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31738,16,FLEN) +NAN_BOXED(28847,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(27718,16,FLEN) +NAN_BOXED(28034,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31719,16,FLEN) +NAN_BOXED(31022,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29885,16,FLEN) +NAN_BOXED(29545,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31090,16,FLEN) +NAN_BOXED(30468,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28459,16,FLEN) +NAN_BOXED(30803,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31243,16,FLEN) +NAN_BOXED(28198,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31160,16,FLEN) +NAN_BOXED(29725,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30559,16,FLEN) +NAN_BOXED(31135,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31733,16,FLEN) +NAN_BOXED(31298,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28833,16,FLEN) +NAN_BOXED(30478,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30914,16,FLEN) +NAN_BOXED(31501,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30740,16,FLEN) +NAN_BOXED(30647,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31150,16,FLEN) +NAN_BOXED(31613,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30606,16,FLEN) +NAN_BOXED(31665,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31222,16,FLEN) +NAN_BOXED(31043,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31440,16,FLEN) +NAN_BOXED(29490,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30320,16,FLEN) +NAN_BOXED(31061,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30995,16,FLEN) +NAN_BOXED(25072,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31152,16,FLEN) +NAN_BOXED(31503,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31366,16,FLEN) +NAN_BOXED(25698,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31189,16,FLEN) +NAN_BOXED(30937,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31506,16,FLEN) +NAN_BOXED(28269,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31266,16,FLEN) +NAN_BOXED(29281,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30896,16,FLEN) +NAN_BOXED(29215,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28776,16,FLEN) +NAN_BOXED(30949,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29710,16,FLEN) +NAN_BOXED(30854,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29326,16,FLEN) +NAN_BOXED(31675,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(23095,16,FLEN) +NAN_BOXED(30659,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31043,16,FLEN) +NAN_BOXED(31240,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31077,16,FLEN) +NAN_BOXED(30043,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30725,16,FLEN) +NAN_BOXED(26379,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31239,16,FLEN) +NAN_BOXED(29070,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31301,16,FLEN) +NAN_BOXED(30327,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31307,16,FLEN) +NAN_BOXED(31464,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28979,16,FLEN) +NAN_BOXED(30234,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29878,16,FLEN) +NAN_BOXED(24914,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31675,16,FLEN) +NAN_BOXED(30172,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30237,16,FLEN) +NAN_BOXED(30484,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29934,16,FLEN) +NAN_BOXED(31024,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30798,16,FLEN) +NAN_BOXED(31568,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31383,16,FLEN) +NAN_BOXED(29917,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31325,16,FLEN) +NAN_BOXED(31033,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31416,16,FLEN) +NAN_BOXED(28146,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30273,16,FLEN) +NAN_BOXED(30781,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31329,16,FLEN) +NAN_BOXED(30983,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29555,16,FLEN) +NAN_BOXED(30545,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29808,16,FLEN) +NAN_BOXED(31656,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31371,16,FLEN) +NAN_BOXED(30224,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29975,16,FLEN) +NAN_BOXED(27891,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29011,16,FLEN) +NAN_BOXED(30481,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31527,16,FLEN) +NAN_BOXED(31582,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31005,16,FLEN) +NAN_BOXED(31598,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28254,16,FLEN) +NAN_BOXED(29595,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31084,16,FLEN) +NAN_BOXED(30202,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31323,16,FLEN) +NAN_BOXED(29557,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30991,16,FLEN) +NAN_BOXED(30310,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30073,16,FLEN) +NAN_BOXED(31494,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30724,16,FLEN) +NAN_BOXED(31108,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31216,16,FLEN) +NAN_BOXED(31233,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31611,16,FLEN) +NAN_BOXED(31238,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29865,16,FLEN) +NAN_BOXED(30970,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30176,16,FLEN) +NAN_BOXED(30289,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31656,16,FLEN) +NAN_BOXED(30121,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31525,16,FLEN) +NAN_BOXED(29174,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28688,16,FLEN) +NAN_BOXED(26412,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30142,16,FLEN) +NAN_BOXED(31574,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31254,16,FLEN) +NAN_BOXED(30458,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29586,16,FLEN) +NAN_BOXED(31402,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29837,16,FLEN) +NAN_BOXED(31001,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29967,16,FLEN) +NAN_BOXED(31591,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28812,16,FLEN) +NAN_BOXED(29321,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30393,16,FLEN) +NAN_BOXED(29696,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29666,16,FLEN) +NAN_BOXED(29613,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30049,16,FLEN) +NAN_BOXED(30198,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(27620,16,FLEN) +NAN_BOXED(28827,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30431,16,FLEN) +NAN_BOXED(31290,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30766,16,FLEN) +NAN_BOXED(31426,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31268,16,FLEN) +NAN_BOXED(30945,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31737,16,FLEN) +NAN_BOXED(30278,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30964,16,FLEN) +NAN_BOXED(29969,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30919,16,FLEN) +NAN_BOXED(30899,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31712,16,FLEN) +NAN_BOXED(31720,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30533,16,FLEN) +NAN_BOXED(30357,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(27111,16,FLEN) +NAN_BOXED(28396,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28697,16,FLEN) +NAN_BOXED(31614,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31569,16,FLEN) +NAN_BOXED(27890,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31329,16,FLEN) +NAN_BOXED(24710,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30107,16,FLEN) +NAN_BOXED(29065,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31067,16,FLEN) +NAN_BOXED(28129,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31025,16,FLEN) +NAN_BOXED(27229,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29625,16,FLEN) +NAN_BOXED(30643,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28783,16,FLEN) +NAN_BOXED(30723,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29282,16,FLEN) +NAN_BOXED(31576,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30766,16,FLEN) +NAN_BOXED(31091,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28794,16,FLEN) +NAN_BOXED(30686,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28532,16,FLEN) +NAN_BOXED(28396,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(27340,16,FLEN) +NAN_BOXED(29410,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30970,16,FLEN) +NAN_BOXED(31453,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31164,16,FLEN) +NAN_BOXED(30734,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28982,16,FLEN) +NAN_BOXED(28350,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30979,16,FLEN) +NAN_BOXED(29370,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29889,16,FLEN) +NAN_BOXED(30435,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30302,16,FLEN) +NAN_BOXED(31328,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30847,16,FLEN) +NAN_BOXED(30607,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31262,16,FLEN) +NAN_BOXED(31716,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31135,16,FLEN) +NAN_BOXED(31126,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(26581,16,FLEN) +NAN_BOXED(30825,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29239,16,FLEN) +NAN_BOXED(30882,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(31215,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30617,16,FLEN) +NAN_BOXED(27165,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31380,16,FLEN) +NAN_BOXED(31406,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(26850,16,FLEN) +NAN_BOXED(29251,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31653,16,FLEN) +NAN_BOXED(31636,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28013,16,FLEN) +NAN_BOXED(31406,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31066,16,FLEN) +NAN_BOXED(29933,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30435,16,FLEN) +NAN_BOXED(30283,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31732,16,FLEN) +NAN_BOXED(31639,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30493,16,FLEN) +NAN_BOXED(29770,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(26373,16,FLEN) +NAN_BOXED(30575,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30843,16,FLEN) +NAN_BOXED(29581,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31740,16,FLEN) +NAN_BOXED(31076,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28967,16,FLEN) +NAN_BOXED(31239,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30559,16,FLEN) +NAN_BOXED(30858,16,FLEN) +NAN_BOXED(64511,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x3_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x3_1: + .fill 30*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x11_0: + .fill 26*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_0: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 110*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fnmadd_b18-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fnmadd_b18-01.S new file mode 100644 index 000000000..9a60375b9 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fnmadd_b18-01.S @@ -0,0 +1,3054 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 06:03:37 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fnmadd.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fnmadd.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fnmadd_b18 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fnmadd_b18) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x14,test_dataset_0) +RVTEST_SIGBASE(x2,signature_x2_1) + +inst_0: +// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==x26, rs2==x7, rs3==x26, rd==x23,fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x26; op2:x7; op3:x26; dest:x23; op1val:0x704c; op2val:0x8000; +op3val:0x704c; valaddr_reg:x14; val_offset:0*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x23, x26, x7, x26, dyn, 0, 0, x14, 0*FLEN/8, x16, x2, x11) + +inst_1: +// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==x1, rs2==x15, rs3==x15, rd==x12,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x1; op2:x15; op3:x15; dest:x12; op1val:0x7ac6; op2val:0x8000; +op3val:0x8000; valaddr_reg:x14; val_offset:3*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x12, x1, x15, x15, dyn, 0, 0, x14, 3*FLEN/8, x16, x2, x11) + +inst_2: +// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==x9, rs2==x26, rs3==x12, rd==x21,fs1 == 0 and fe1 == 0x1e and fm1 == 0x21b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x9; op2:x26; op3:x12; dest:x21; op1val:0x7a1b; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x14; val_offset:6*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x21, x9, x26, x12, dyn, 0, 0, x14, 6*FLEN/8, x16, x2, x11) + +inst_3: +// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==x13, rs2==x3, rs3==x27, rd==x3,fs1 == 0 and fe1 == 0x1d and fm1 == 0x014 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x13; op2:x3; op3:x27; dest:x3; op1val:0x7414; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x14; val_offset:9*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x3, x13, x3, x27, dyn, 0, 0, x14, 9*FLEN/8, x16, x2, x11) + +inst_4: +// rs1 == rd == rs3 != rs2, rs1==x6, rs2==x8, rs3==x6, rd==x6,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ec and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x6; op2:x8; op3:x6; dest:x6; op1val:0x77ec; op2val:0x8000; +op3val:0x77ec; valaddr_reg:x14; val_offset:12*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x6, x6, x8, x6, dyn, 0, 0, x14, 12*FLEN/8, x16, x2, x11) + +inst_5: +// rs1 == rs2 == rs3 != rd, rs1==x10, rs2==x10, rs3==x10, rd==x24,fs1 == 0 and fe1 == 0x1d and fm1 == 0x330 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x10; op2:x10; op3:x10; dest:x24; op1val:0x7730; op2val:0x7730; +op3val:0x7730; valaddr_reg:x14; val_offset:15*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x24, x10, x10, x10, dyn, 0, 0, x14, 15*FLEN/8, x16, x2, x11) + +inst_6: +// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==x4, rs2==x4, rs3==x16, rd==x19,fs1 == 0 and fe1 == 0x1e and fm1 == 0x135 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x4; op2:x4; op3:x16; dest:x19; op1val:0x7935; op2val:0x7935; +op3val:0xfbff; valaddr_reg:x14; val_offset:18*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x19, x4, x4, x16, dyn, 0, 0, x14, 18*FLEN/8, x16, x2, x11) + +inst_7: +// rd == rs2 == rs3 != rs1, rs1==x8, rs2==x29, rs3==x29, rd==x29,fs1 == 0 and fe1 == 0x1e and fm1 == 0x24e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x8; op2:x29; op3:x29; dest:x29; op1val:0x7a4e; op2val:0x0; +op3val:0x0; valaddr_reg:x14; val_offset:21*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x29, x8, x29, x29, dyn, 0, 0, x14, 21*FLEN/8, x16, x2, x11) + +inst_8: +// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==x22, rs2==x0, rs3==x18, rd==x22,fs1 == 0 and fe1 == 0x1b and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x22; op2:x0; op3:x18; dest:x22; op1val:0x6e01; op2val:0x0; +op3val:0xfbff; valaddr_reg:x14; val_offset:24*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x22, x22, x0, x18, dyn, 0, 0, x14, 24*FLEN/8, x16, x2, x11) + +inst_9: +// rs1 == rs2 == rs3 == rd, rs1==x25, rs2==x25, rs3==x25, rd==x25,fs1 == 0 and fe1 == 0x19 and fm1 == 0x341 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x25; op2:x25; op3:x25; dest:x25; op1val:0x6741; op2val:0x6741; +op3val:0x6741; valaddr_reg:x14; val_offset:27*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x25, x25, x25, x25, dyn, 0, 0, x14, 27*FLEN/8, x16, x2, x11) + +inst_10: +// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==x12, rs2==x6, rs3==x1, rd==x1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x12; op2:x6; op3:x1; dest:x1; op1val:0x7aae; op2val:0x0; +op3val:0xfbff; valaddr_reg:x14; val_offset:30*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x1, x12, x6, x1, dyn, 0, 0, x14, 30*FLEN/8, x16, x2, x11) + +inst_11: +// rs1 == rs2 == rd != rs3, rs1==x27, rs2==x27, rs3==x31, rd==x27,fs1 == 0 and fe1 == 0x1d and fm1 == 0x2eb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x27; op2:x27; op3:x31; dest:x27; op1val:0x76eb; op2val:0x76eb; +op3val:0xfbff; valaddr_reg:x14; val_offset:33*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x27, x27, x27, x31, dyn, 0, 0, x14, 33*FLEN/8, x16, x2, x11) + +inst_12: +// rs1==x0, rs2==x20, rs3==x23, rd==x4,fs1 == 0 and fe1 == 0x1e and fm1 == 0x218 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x0; op2:x20; op3:x23; dest:x4; op1val:0x0; op2val:0x0; +op3val:0xfbff; valaddr_reg:x14; val_offset:36*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x4, x0, x20, x23, dyn, 0, 0, x14, 36*FLEN/8, x16, x2, x11) + +inst_13: +// rs1==x5, rs2==x18, rs3==x24, rd==x31,fs1 == 0 and fe1 == 0x16 and fm1 == 0x057 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x5; op2:x18; op3:x24; dest:x31; op1val:0x5857; op2val:0x0; +op3val:0xfbff; valaddr_reg:x14; val_offset:39*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x5, x18, x24, dyn, 0, 0, x14, 39*FLEN/8, x16, x2, x11) +RVTEST_VALBASEUPD(x10,test_dataset_1) + +inst_14: +// rs1==x28, rs2==x30, rs3==x19, rd==x7,fs1 == 0 and fe1 == 0x1d and fm1 == 0x31f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x28; op2:x30; op3:x19; dest:x7; op1val:0x771f; op2val:0x0; +op3val:0xfbff; valaddr_reg:x10; val_offset:0*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x7, x28, x30, x19, dyn, 0, 0, x10, 0*FLEN/8, x19, x2, x6) +RVTEST_SIGBASE(x4,signature_x4_0) + +inst_15: +// rs1==x21, rs2==x13, rs3==x22, rd==x28,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x21; op2:x13; op3:x22; dest:x28; op1val:0x79c5; op2val:0x0; +op3val:0xfbff; valaddr_reg:x10; val_offset:3*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x28, x21, x13, x22, dyn, 0, 0, x10, 3*FLEN/8, x19, x4, x6) + +inst_16: +// rs1==x23, rs2==x17, rs3==x9, rd==x15,fs1 == 0 and fe1 == 0x1c and fm1 == 0x351 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x23; op2:x17; op3:x9; dest:x15; op1val:0x7351; op2val:0x0; +op3val:0xfbff; valaddr_reg:x10; val_offset:6*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x15, x23, x17, x9, dyn, 0, 0, x10, 6*FLEN/8, x19, x4, x6) + +inst_17: +// rs1==x2, rs2==x21, rs3==x5, rd==x8,fs1 == 0 and fe1 == 0x1e and fm1 == 0x38e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x2; op2:x21; op3:x5; dest:x8; op1val:0x7b8e; op2val:0x0; +op3val:0xfbff; valaddr_reg:x10; val_offset:9*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x8, x2, x21, x5, dyn, 0, 0, x10, 9*FLEN/8, x19, x4, x6) + +inst_18: +// rs1==x20, rs2==x24, rs3==x11, rd==x5,fs1 == 0 and fe1 == 0x1e and fm1 == 0x335 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x20; op2:x24; op3:x11; dest:x5; op1val:0x7b35; op2val:0x0; +op3val:0xfbff; valaddr_reg:x10; val_offset:12*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x5, x20, x24, x11, dyn, 0, 0, x10, 12*FLEN/8, x19, x4, x6) + +inst_19: +// rs1==x11, rs2==x5, rs3==x21, rd==x26,fs1 == 0 and fe1 == 0x19 and fm1 == 0x3d4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x11; op2:x5; op3:x21; dest:x26; op1val:0x67d4; op2val:0x0; +op3val:0xfbff; valaddr_reg:x10; val_offset:15*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x26, x11, x5, x21, dyn, 0, 0, x10, 15*FLEN/8, x19, x4, x6) + +inst_20: +// rs1==x15, rs2==x28, rs3==x2, rd==x9,fs1 == 0 and fe1 == 0x19 and fm1 == 0x283 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x15; op2:x28; op3:x2; dest:x9; op1val:0x6683; op2val:0x0; +op3val:0xfbff; valaddr_reg:x10; val_offset:18*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x9, x15, x28, x2, dyn, 0, 0, x10, 18*FLEN/8, x19, x4, x6) + +inst_21: +// rs1==x30, rs2==x11, rs3==x13, rd==x0,fs1 == 0 and fe1 == 0x1e and fm1 == 0x054 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x11; op3:x13; dest:x0; op1val:0x7854; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x10; val_offset:21*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x0, x30, x11, x13, dyn, 0, 0, x10, 21*FLEN/8, x19, x4, x6) + +inst_22: +// rs1==x7, rs2==x16, rs3==x17, rd==x11,fs1 == 0 and fe1 == 0x1e and fm1 == 0x382 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x7; op2:x16; op3:x17; dest:x11; op1val:0x7b82; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x10; val_offset:24*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x11, x7, x16, x17, dyn, 0, 0, x10, 24*FLEN/8, x19, x4, x6) + +inst_23: +// rs1==x3, rs2==x22, rs3==x30, rd==x14,fs1 == 0 and fe1 == 0x1d and fm1 == 0x218 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x3; op2:x22; op3:x30; dest:x14; op1val:0x7618; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x10; val_offset:27*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x14, x3, x22, x30, dyn, 0, 0, x10, 27*FLEN/8, x19, x4, x6) + +inst_24: +// rs1==x14, rs2==x1, rs3==x8, rd==x30,fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ed and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x14; op2:x1; op3:x8; dest:x30; op1val:0x72ed; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x10; val_offset:30*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x30, x14, x1, x8, dyn, 0, 0, x10, 30*FLEN/8, x19, x4, x6) + +inst_25: +// rs1==x18, rs2==x12, rs3==x0, rd==x20,fs1 == 0 and fe1 == 0x1d and fm1 == 0x2c0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x18; op2:x12; op3:x0; dest:x20; op1val:0x76c0; op2val:0x8000; +op3val:0x0; valaddr_reg:x10; val_offset:33*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x20, x18, x12, x0, dyn, 0, 0, x10, 33*FLEN/8, x19, x4, x6) +RVTEST_VALBASEUPD(x5,test_dataset_2) + +inst_26: +// rs1==x17, rs2==x9, rs3==x20, rd==x13,fs1 == 0 and fe1 == 0x19 and fm1 == 0x36f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x17; op2:x9; op3:x20; dest:x13; op1val:0x676f; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:0*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x13, x17, x9, x20, dyn, 0, 0, x5, 0*FLEN/8, x7, x4, x6) + +inst_27: +// rs1==x31, rs2==x2, rs3==x7, rd==x10,fs1 == 0 and fe1 == 0x1c and fm1 == 0x317 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x31; op2:x2; op3:x7; dest:x10; op1val:0x7317; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:3*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x10, x31, x2, x7, dyn, 0, 0, x5, 3*FLEN/8, x7, x4, x6) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_28: +// rs1==x29, rs2==x31, rs3==x4, rd==x2,fs1 == 0 and fe1 == 0x1d and fm1 == 0x300 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x29; op2:x31; op3:x4; dest:x2; op1val:0x7700; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:6*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x2, x29, x31, x4, dyn, 0, 0, x5, 6*FLEN/8, x7, x1, x3) + +inst_29: +// rs1==x19, rs2==x14, rs3==x28, rd==x18,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ed and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x19; op2:x14; op3:x28; dest:x18; op1val:0x77ed; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:9*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x18, x19, x14, x28, dyn, 0, 0, x5, 9*FLEN/8, x7, x1, x3) + +inst_30: +// rs1==x24, rs2==x19, rs3==x3, rd==x16,fs1 == 0 and fe1 == 0x1c and fm1 == 0x374 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x24; op2:x19; op3:x3; dest:x16; op1val:0x7374; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:12*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x16, x24, x19, x3, dyn, 0, 0, x5, 12*FLEN/8, x7, x1, x3) + +inst_31: +// rs1==x16, rs2==x23, rs3==x14, rd==x17,fs1 == 0 and fe1 == 0x1c and fm1 == 0x362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x16; op2:x23; op3:x14; dest:x17; op1val:0x7362; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:15*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x17, x16, x23, x14, dyn, 0, 0, x5, 15*FLEN/8, x7, x1, x3) + +inst_32: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72ff; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:18*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 18*FLEN/8, x7, x1, x3) + +inst_33: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x359 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7759; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:21*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 21*FLEN/8, x7, x1, x3) + +inst_34: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74a2; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:24*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 24*FLEN/8, x7, x1, x3) + +inst_35: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x180 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6580; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:27*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 27*FLEN/8, x7, x1, x3) + +inst_36: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ab2; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:30*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 30*FLEN/8, x7, x1, x3) + +inst_37: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x073 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7873; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:33*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 33*FLEN/8, x7, x1, x3) + +inst_38: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x122 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7922; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:36*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 36*FLEN/8, x7, x1, x3) + +inst_39: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1f2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71f2; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:39*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 39*FLEN/8, x7, x1, x3) + +inst_40: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bef; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:42*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 42*FLEN/8, x7, x1, x3) + +inst_41: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ae0; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:45*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 45*FLEN/8, x7, x1, x3) + +inst_42: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3bb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6fbb; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:48*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 48*FLEN/8, x7, x1, x3) + +inst_43: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x152 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7552; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:51*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 51*FLEN/8, x7, x1, x3) + +inst_44: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79c4; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:54*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 54*FLEN/8, x7, x1, x3) + +inst_45: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1af and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79af; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:57*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 57*FLEN/8, x7, x1, x3) + +inst_46: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b7c; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:60*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 60*FLEN/8, x7, x1, x3) + +inst_47: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76c0; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:63*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 63*FLEN/8, x7, x1, x3) + +inst_48: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aa3; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:66*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 66*FLEN/8, x7, x1, x3) + +inst_49: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x795c; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:69*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 69*FLEN/8, x7, x1, x3) + +inst_50: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0da and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74da; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:72*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 72*FLEN/8, x7, x1, x3) + +inst_51: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78b2; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:75*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 75*FLEN/8, x7, x1, x3) + +inst_52: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b0e; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:78*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 78*FLEN/8, x7, x1, x3) + +inst_53: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ac4; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:81*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 81*FLEN/8, x7, x1, x3) + +inst_54: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x780a; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:84*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 84*FLEN/8, x7, x1, x3) + +inst_55: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78b5; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:87*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 87*FLEN/8, x7, x1, x3) + +inst_56: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x06b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x686b; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:90*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 90*FLEN/8, x7, x1, x3) + +inst_57: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3c3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73c3; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:93*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 93*FLEN/8, x7, x1, x3) + +inst_58: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x260 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a60; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:96*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 96*FLEN/8, x7, x1, x3) + +inst_59: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76a0; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:99*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 99*FLEN/8, x7, x1, x3) + +inst_60: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x188 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7188; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:102*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 102*FLEN/8, x7, x1, x3) + +inst_61: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x063 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7863; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:105*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 105*FLEN/8, x7, x1, x3) + +inst_62: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x799f; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:108*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 108*FLEN/8, x7, x1, x3) + +inst_63: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x164 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7964; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:111*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 111*FLEN/8, x7, x1, x3) + +inst_64: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75fe; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:114*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 114*FLEN/8, x7, x1, x3) + +inst_65: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x305 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7705; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:117*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 117*FLEN/8, x7, x1, x3) + +inst_66: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x010 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7810; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:120*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 120*FLEN/8, x7, x1, x3) + +inst_67: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x239 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a39; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:123*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 123*FLEN/8, x7, x1, x3) + +inst_68: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x782a; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:126*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 126*FLEN/8, x7, x1, x3) + +inst_69: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x24a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x764a; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:129*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 129*FLEN/8, x7, x1, x3) + +inst_70: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77d4; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:132*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 132*FLEN/8, x7, x1, x3) + +inst_71: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x392 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6792; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:135*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 135*FLEN/8, x7, x1, x3) + +inst_72: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x190 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6990; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:138*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 138*FLEN/8, x7, x1, x3) + +inst_73: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x799f; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:141*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 141*FLEN/8, x7, x1, x3) + +inst_74: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3dc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bdc; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:144*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 144*FLEN/8, x7, x1, x3) + +inst_75: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0be and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78be; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:147*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 147*FLEN/8, x7, x1, x3) + +inst_76: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x24b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x764b; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:150*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 150*FLEN/8, x7, x1, x3) + +inst_77: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x172 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7172; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:153*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 153*FLEN/8, x7, x1, x3) + +inst_78: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7804; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:156*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 156*FLEN/8, x7, x1, x3) + +inst_79: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3da and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bda; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:159*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 159*FLEN/8, x7, x1, x3) + +inst_80: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x229 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a29; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:162*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 162*FLEN/8, x7, x1, x3) + +inst_81: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x050 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7850; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:165*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 165*FLEN/8, x7, x1, x3) + +inst_82: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ae1; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:168*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 168*FLEN/8, x7, x1, x3) + +inst_83: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x36d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x736d; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:171*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 171*FLEN/8, x7, x1, x3) + +inst_84: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x01b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x781b; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:174*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 174*FLEN/8, x7, x1, x3) + +inst_85: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x39d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b9d; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:177*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 177*FLEN/8, x7, x1, x3) + +inst_86: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x789e; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:180*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 180*FLEN/8, x7, x1, x3) + +inst_87: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x357 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7757; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:183*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 183*FLEN/8, x7, x1, x3) + +inst_88: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x04e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x744e; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:186*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 186*FLEN/8, x7, x1, x3) + +inst_89: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x061 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7861; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:189*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 189*FLEN/8, x7, x1, x3) + +inst_90: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ba7; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:192*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 192*FLEN/8, x7, x1, x3) + +inst_91: +// fs1 == 0 and fe1 == 0x17 and fm1 == 0x1db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5ddb; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:195*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 195*FLEN/8, x7, x1, x3) + +inst_92: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x244 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a44; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:198*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 198*FLEN/8, x7, x1, x3) + +inst_93: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8f; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:201*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 201*FLEN/8, x7, x1, x3) + +inst_94: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x316 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b16; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:204*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 204*FLEN/8, x7, x1, x3) + +inst_95: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1eb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79eb; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:207*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 207*FLEN/8, x7, x1, x3) + +inst_96: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x278 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a78; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:210*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 210*FLEN/8, x7, x1, x3) + +inst_97: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x025 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7825; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:213*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 213*FLEN/8, x7, x1, x3) + +inst_98: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x07d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x787d; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:216*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 216*FLEN/8, x7, x1, x3) + +inst_99: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2d0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76d0; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:219*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 219*FLEN/8, x7, x1, x3) + +inst_100: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x32e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6b2e; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:222*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 222*FLEN/8, x7, x1, x3) + +inst_101: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7af4; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:225*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 225*FLEN/8, x7, x1, x3) + +inst_102: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x08e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x788e; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:228*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 228*FLEN/8, x7, x1, x3) + +inst_103: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x264 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7264; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:231*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 231*FLEN/8, x7, x1, x3) + +inst_104: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x009 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7809; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:234*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 234*FLEN/8, x7, x1, x3) + +inst_105: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3c1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77c1; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:237*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 237*FLEN/8, x7, x1, x3) + +inst_106: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1b4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75b4; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:240*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 240*FLEN/8, x7, x1, x3) + +inst_107: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x188 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7588; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:243*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 243*FLEN/8, x7, x1, x3) + +inst_108: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x784e; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:246*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 246*FLEN/8, x7, x1, x3) + +inst_109: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fc; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:249*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 249*FLEN/8, x7, x1, x3) + +inst_110: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e5; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:252*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 252*FLEN/8, x7, x1, x3) + +inst_111: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x353 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7753; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:255*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 255*FLEN/8, x7, x1, x3) + +inst_112: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x329 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6729; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:258*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 258*FLEN/8, x7, x1, x3) + +inst_113: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x358 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7358; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:261*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 261*FLEN/8, x7, x1, x3) + +inst_114: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1ab and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71ab; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:264*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 264*FLEN/8, x7, x1, x3) + +inst_115: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ac and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78ac; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:267*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 267*FLEN/8, x7, x1, x3) + +inst_116: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ae2; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:270*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 270*FLEN/8, x7, x1, x3) + +inst_117: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x262 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a62; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:273*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 273*FLEN/8, x7, x1, x3) + +inst_118: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5f; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:276*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 276*FLEN/8, x7, x1, x3) + +inst_119: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x287 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a87; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:279*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 279*FLEN/8, x7, x1, x3) + +inst_120: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x015 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7415; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:282*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 282*FLEN/8, x7, x1, x3) + +inst_121: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2bb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7abb; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:285*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 285*FLEN/8, x7, x1, x3) + +inst_122: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x161 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7961; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:288*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 288*FLEN/8, x7, x1, x3) + +inst_123: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x153 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d53; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:291*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 291*FLEN/8, x7, x1, x3) + +inst_124: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x046 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6446; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:294*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 294*FLEN/8, x7, x1, x3) + +inst_125: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x375 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6375; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:297*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 297*FLEN/8, x7, x1, x3) + +inst_126: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a0a; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:300*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 300*FLEN/8, x7, x1, x3) + +inst_127: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3fb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73fb; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:303*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 303*FLEN/8, x7, x1, x3) + +inst_128: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x301 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f01; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:306*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 306*FLEN/8, x7, x1, x3) + +inst_129: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fe; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:309*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 309*FLEN/8, x7, x1, x3) + +inst_130: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x182 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7582; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:312*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 312*FLEN/8, x7, x1, x3) + +inst_131: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x072 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c72; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:315*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 315*FLEN/8, x7, x1, x3) + +inst_132: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x11b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x711b; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:318*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 318*FLEN/8, x7, x1, x3) + +inst_133: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x037 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7837; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:321*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 321*FLEN/8, x7, x1, x3) + +inst_134: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x160 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7160; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:324*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 324*FLEN/8, x7, x1, x3) + +inst_135: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x05d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x745d; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:327*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 327*FLEN/8, x7, x1, x3) + +inst_136: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79b0; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:330*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 330*FLEN/8, x7, x1, x3) + +inst_137: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x345 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7745; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:333*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 333*FLEN/8, x7, x1, x3) + +inst_138: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x126 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7526; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:336*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 336*FLEN/8, x7, x1, x3) + +inst_139: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x393 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7793; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:339*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 339*FLEN/8, x7, x1, x3) + +inst_140: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x20d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x660d; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:342*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 342*FLEN/8, x7, x1, x3) + +inst_141: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x22e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x762e; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:345*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 345*FLEN/8, x7, x1, x3) + +inst_142: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76bb; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:348*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 348*FLEN/8, x7, x1, x3) + +inst_143: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x203 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7203; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:351*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 351*FLEN/8, x7, x1, x3) + +inst_144: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2f5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ef5; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:354*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 354*FLEN/8, x7, x1, x3) + +inst_145: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x331 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b31; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:357*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 357*FLEN/8, x7, x1, x3) + +inst_146: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x014 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7814; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:360*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 360*FLEN/8, x7, x1, x3) + +inst_147: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72b0; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:363*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 363*FLEN/8, x7, x1, x3) + +inst_148: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78d7; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:366*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 366*FLEN/8, x7, x1, x3) + +inst_149: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x288 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a88; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:369*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 369*FLEN/8, x7, x1, x3) + +inst_150: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x154 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6554; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:372*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 372*FLEN/8, x7, x1, x3) + +inst_151: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x093 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6493; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:375*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 375*FLEN/8, x7, x1, x3) + +inst_152: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0af and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70af; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:378*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 378*FLEN/8, x7, x1, x3) + +inst_153: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1bf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79bf; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:381*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 381*FLEN/8, x7, x1, x3) + +inst_154: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x120 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7120; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:384*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 384*FLEN/8, x7, x1, x3) + +inst_155: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79a2; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:387*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 387*FLEN/8, x7, x1, x3) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_156: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x16c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x796c; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:390*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 390*FLEN/8, x7, x1, x3) + +inst_157: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x05b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x785b; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:393*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 393*FLEN/8, x7, x1, x3) + +inst_158: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x30e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x730e; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:396*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 396*FLEN/8, x7, x1, x3) + +inst_159: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3cd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bcd; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:399*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 399*FLEN/8, x7, x1, x3) + +inst_160: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x261 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a61; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:402*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 402*FLEN/8, x7, x1, x3) + +inst_161: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x021 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7821; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:405*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 405*FLEN/8, x7, x1, x3) + +inst_162: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x323 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7323; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:408*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 408*FLEN/8, x7, x1, x3) + +inst_163: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x792f; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:411*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 411*FLEN/8, x7, x1, x3) + +inst_164: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x250 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7650; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:414*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 414*FLEN/8, x7, x1, x3) + +inst_165: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x789a; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:417*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 417*FLEN/8, x7, x1, x3) + +inst_166: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x123 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7523; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:420*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 420*FLEN/8, x7, x1, x3) + +inst_167: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x10b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x790b; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:423*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 423*FLEN/8, x7, x1, x3) + +inst_168: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x385 and fs2 == 1 and fe2 == 0x09 and fm2 == 0x151 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6b85; op2val:0xa551; +op3val:0xfbff; valaddr_reg:x5; val_offset:426*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 426*FLEN/8, x7, x1, x3) + +inst_169: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0c6 and fs2 == 1 and fe2 == 0x07 and fm2 == 0x030 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74c6; op2val:0x9c30; +op3val:0xfbff; valaddr_reg:x5; val_offset:429*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 429*FLEN/8, x7, x1, x3) + +inst_170: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3bd and fs2 == 1 and fe2 == 0x05 and fm2 == 0x12b and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bbd; op2val:0x952b; +op3val:0xfbff; valaddr_reg:x5; val_offset:432*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 432*FLEN/8, x7, x1, x3) + +inst_171: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x300 and fs2 == 1 and fe2 == 0x05 and fm2 == 0x1b6 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b00; op2val:0x95b6; +op3val:0xfbff; valaddr_reg:x5; val_offset:435*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 435*FLEN/8, x7, x1, x3) + +inst_172: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0e6 and fs2 == 1 and fe2 == 0x07 and fm2 == 0x014 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74e6; op2val:0x9c14; +op3val:0xfbff; valaddr_reg:x5; val_offset:438*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 438*FLEN/8, x7, x1, x3) + +inst_173: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2dd and fs2 == 1 and fe2 == 0x05 and fm2 == 0x1d3 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7add; op2val:0x95d3; +op3val:0xfbff; valaddr_reg:x5; val_offset:441*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 441*FLEN/8, x7, x1, x3) + +inst_174: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f6 and fs2 == 1 and fe2 == 0x07 and fm2 == 0x007 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74f6; op2val:0x9c07; +op3val:0xfbff; valaddr_reg:x5; val_offset:444*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 444*FLEN/8, x7, x1, x3) + +inst_175: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x382 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x153 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b82; op2val:0x1553; +op3val:0xfbff; valaddr_reg:x5; val_offset:447*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 447*FLEN/8, x7, x1, x3) + +inst_176: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f2 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x2b9 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f2; op2val:0x16b9; +op3val:0xfbff; valaddr_reg:x5; val_offset:450*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 450*FLEN/8, x7, x1, x3) + +inst_177: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a7 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x202 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76a7; op2val:0x1a02; +op3val:0xfbff; valaddr_reg:x5; val_offset:453*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 453*FLEN/8, x7, x1, x3) + +inst_178: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x009 and fs2 == 0 and fe2 == 0x07 and fm2 == 0x0f4 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7409; op2val:0x1cf4; +op3val:0xfbff; valaddr_reg:x5; val_offset:456*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 456*FLEN/8, x7, x1, x3) + +inst_179: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x058 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x099 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6058; op2val:0x3099; +op3val:0xfbff; valaddr_reg:x5; val_offset:459*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 459*FLEN/8, x7, x1, x3) + +inst_180: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x306 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x1b1 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b06; op2val:0x15b1; +op3val:0xfbff; valaddr_reg:x5; val_offset:462*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 462*FLEN/8, x7, x1, x3) + +inst_181: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x0da and fs2 == 0 and fe2 == 0x0a and fm2 == 0x01f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x68da; op2val:0x281f; +op3val:0xfbff; valaddr_reg:x5; val_offset:465*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 465*FLEN/8, x7, x1, x3) + +inst_182: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28d and fs2 == 0 and fe2 == 0x05 and fm2 == 0x21a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8d; op2val:0x161a; +op3val:0xfbff; valaddr_reg:x5; val_offset:468*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 468*FLEN/8, x7, x1, x3) + +inst_183: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b1 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x132 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bb1; op2val:0x1532; +op3val:0xfbff; valaddr_reg:x5; val_offset:471*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 471*FLEN/8, x7, x1, x3) + +inst_184: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x08f and fs2 == 0 and fe2 == 0x06 and fm2 == 0x062 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x788f; op2val:0x1862; +op3val:0xfbff; valaddr_reg:x5; val_offset:474*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 474*FLEN/8, x7, x1, x3) + +inst_185: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x17c and fs2 == 0 and fe2 == 0x07 and fm2 == 0x34a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x717c; op2val:0x1f4a; +op3val:0xfbff; valaddr_reg:x5; val_offset:477*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 477*FLEN/8, x7, x1, x3) + +inst_186: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f0 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x1c3 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7af0; op2val:0x15c3; +op3val:0xfbff; valaddr_reg:x5; val_offset:480*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 480*FLEN/8, x7, x1, x3) + +inst_187: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c9 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x123 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bc9; op2val:0x1523; +op3val:0xfbff; valaddr_reg:x5; val_offset:483*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 483*FLEN/8, x7, x1, x3) + +inst_188: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a1 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x31a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79a1; op2val:0x171a; +op3val:0xfbff; valaddr_reg:x5; val_offset:486*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 486*FLEN/8, x7, x1, x3) + +inst_189: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x011 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x0ea and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7811; op2val:0x98ea; +op3val:0xfbff; valaddr_reg:x5; val_offset:489*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 489*FLEN/8, x7, x1, x3) + +inst_190: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x20b and fs2 == 1 and fe2 == 0x06 and fm2 == 0x29e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x760b; op2val:0x9a9e; +op3val:0xfbff; valaddr_reg:x5; val_offset:492*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 492*FLEN/8, x7, x1, x3) + +inst_191: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x18c and fs2 == 1 and fe2 == 0x06 and fm2 == 0x335 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x758c; op2val:0x9b35; +op3val:0xfbff; valaddr_reg:x5; val_offset:495*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 495*FLEN/8, x7, x1, x3) + +inst_192: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x294 and fs2 == 1 and fe2 == 0x07 and fm2 == 0x213 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7294; op2val:0x9e13; +op3val:0xfbff; valaddr_reg:x5; val_offset:498*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 498*FLEN/8, x7, x1, x3) + +inst_193: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x164 and fs2 == 1 and fe2 == 0x05 and fm2 == 0x36b and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7964; op2val:0x976b; +op3val:0xfbff; valaddr_reg:x5; val_offset:501*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 501*FLEN/8, x7, x1, x3) + +inst_194: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2ec and fs2 == 1 and fe2 == 0x06 and fm2 == 0x1c6 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76ec; op2val:0x99c6; +op3val:0xfbff; valaddr_reg:x5; val_offset:504*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 504*FLEN/8, x7, x1, x3) + +inst_195: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x235 and fs2 == 1 and fe2 == 0x07 and fm2 == 0x271 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7235; op2val:0x9e71; +op3val:0xfbff; valaddr_reg:x5; val_offset:507*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 507*FLEN/8, x7, x1, x3) + +inst_196: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2ae and fs2 == 1 and fe2 == 0x00 and fm2 == 0x072 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6eae; op2val:0x8072; +op3val:0xfbff; valaddr_reg:x5; val_offset:510*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 510*FLEN/8, x7, x1, x3) + +inst_197: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x153 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x012 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7953; op2val:0x8012; +op3val:0xfbff; valaddr_reg:x5; val_offset:513*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 513*FLEN/8, x7, x1, x3) + +inst_198: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0bc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x028 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74bc; op2val:0x8028; +op3val:0xfbff; valaddr_reg:x5; val_offset:516*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 516*FLEN/8, x7, x1, x3) + +inst_199: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x018 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77fe; op2val:0x8018; +op3val:0xfbff; valaddr_reg:x5; val_offset:519*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 519*FLEN/8, x7, x1, x3) + +inst_200: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x134 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x024 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7534; op2val:0x8024; +op3val:0xfbff; valaddr_reg:x5; val_offset:522*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 522*FLEN/8, x7, x1, x3) + +inst_201: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7af8; op2val:0x800d; +op3val:0xfbff; valaddr_reg:x5; val_offset:525*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 525*FLEN/8, x7, x1, x3) + +inst_202: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x331 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b31; op2val:0x800d; +op3val:0xfbff; valaddr_reg:x5; val_offset:528*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 528*FLEN/8, x7, x1, x3) + +inst_203: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x0a2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x297 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x64a2; op2val:0x297; +op3val:0xfbff; valaddr_reg:x5; val_offset:531*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 531*FLEN/8, x7, x1, x3) + +inst_204: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x26c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03b and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x726c; op2val:0x3b; +op3val:0xfbff; valaddr_reg:x5; val_offset:534*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 534*FLEN/8, x7, x1, x3) + +inst_205: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x13d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x024 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x753d; op2val:0x24; +op3val:0xfbff; valaddr_reg:x5; val_offset:537*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 537*FLEN/8, x7, x1, x3) + +inst_206: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00c and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7be4; op2val:0xc; +op3val:0xfbff; valaddr_reg:x5; val_offset:540*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 540*FLEN/8, x7, x1, x3) + +inst_207: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x242 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a42; op2val:0xf; +op3val:0xfbff; valaddr_reg:x5; val_offset:543*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 543*FLEN/8, x7, x1, x3) + +inst_208: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x16c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x023 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x756c; op2val:0x23; +op3val:0xfbff; valaddr_reg:x5; val_offset:546*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 546*FLEN/8, x7, x1, x3) + +inst_209: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2d0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x038 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72d0; op2val:0x38; +op3val:0xfbff; valaddr_reg:x5; val_offset:549*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 549*FLEN/8, x7, x1, x3) + +inst_210: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x164 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x011 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7964; op2val:0x11; +op3val:0xfbff; valaddr_reg:x5; val_offset:552*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 552*FLEN/8, x7, x1, x3) + +inst_211: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ab2; op2val:0xe; +op3val:0xfbff; valaddr_reg:x5; val_offset:555*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 555*FLEN/8, x7, x1, x3) + +inst_212: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x374 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00c and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b74; op2val:0xc; +op3val:0xfbff; valaddr_reg:x5; val_offset:558*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 558*FLEN/8, x7, x1, x3) + +inst_213: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x17f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x022 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x757f; op2val:0x22; +op3val:0xfbff; valaddr_reg:x5; val_offset:561*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 561*FLEN/8, x7, x1, x3) + +inst_214: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b0e; op2val:0xd; +op3val:0xfbff; valaddr_reg:x5; val_offset:564*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 564*FLEN/8, x7, x1, x3) + +inst_215: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x17e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x011 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x797e; op2val:0x11; +op3val:0xfbff; valaddr_reg:x5; val_offset:567*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 567*FLEN/8, x7, x1, x3) + +inst_216: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3bf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x018 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77bf; op2val:0x18; +op3val:0xfbff; valaddr_reg:x5; val_offset:570*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 570*FLEN/8, x7, x1, x3) + +inst_217: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00c and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7be1; op2val:0x800c; +op3val:0xfbff; valaddr_reg:x5; val_offset:573*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 573*FLEN/8, x7, x1, x3) + +inst_218: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x381 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x033 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7381; op2val:0x8033; +op3val:0xfbff; valaddr_reg:x5; val_offset:576*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 576*FLEN/8, x7, x1, x3) + +inst_219: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1cd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x010 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79cd; op2val:0x8010; +op3val:0xfbff; valaddr_reg:x5; val_offset:579*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 579*FLEN/8, x7, x1, x3) + +inst_220: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x16a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x08d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d6a; op2val:0x808d; +op3val:0xfbff; valaddr_reg:x5; val_offset:582*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 582*FLEN/8, x7, x1, x3) + +inst_221: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x16d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x046 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x716d; op2val:0x8046; +op3val:0xfbff; valaddr_reg:x5; val_offset:585*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 585*FLEN/8, x7, x1, x3) + +inst_222: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x348 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b48; op2val:0x800d; +op3val:0xfbff; valaddr_reg:x5; val_offset:588*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 588*FLEN/8, x7, x1, x3) + +inst_223: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2cf and fs2 == 1 and fe2 == 0x00 and fm2 == 0x038 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72cf; op2val:0x8038; +op3val:0xfbff; valaddr_reg:x5; val_offset:591*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 591*FLEN/8, x7, x1, x3) + +inst_224: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x211 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x144 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a11; op2val:0xbd44; +op3val:0xfbff; valaddr_reg:x5; val_offset:594*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 594*FLEN/8, x7, x1, x3) + +inst_225: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0cc and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2aa and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78cc; op2val:0x3eaa; +op3val:0xfbff; valaddr_reg:x5; val_offset:597*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 597*FLEN/8, x7, x1, x3) + +inst_226: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b9 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0c1 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ab9; op2val:0xbcc1; +op3val:0xfbff; valaddr_reg:x5; val_offset:600*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 600*FLEN/8, x7, x1, x3) + +inst_227: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1e3 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x16e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75e3; op2val:0x416e; +op3val:0xfbff; valaddr_reg:x5; val_offset:603*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 603*FLEN/8, x7, x1, x3) + +inst_228: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x171 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e0 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7571; op2val:0xc1e0; +op3val:0xfbff; valaddr_reg:x5; val_offset:606*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 606*FLEN/8, x7, x1, x3) + +inst_229: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a8 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x2de and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74a8; op2val:0x42de; +op3val:0xfbff; valaddr_reg:x5; val_offset:609*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 609*FLEN/8, x7, x1, x3) + +inst_230: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x0f and fm2 == 0x09c and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aef; op2val:0xbc9c; +op3val:0xfbff; valaddr_reg:x5; val_offset:612*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 612*FLEN/8, x7, x1, x3) + +inst_231: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x29f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78d4; op2val:0x3e9f; +op3val:0xfbff; valaddr_reg:x5; val_offset:615*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 615*FLEN/8, x7, x1, x3) + +inst_232: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a1 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x031 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ba1; op2val:0xbc31; +op3val:0xfbff; valaddr_reg:x5; val_offset:618*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 618*FLEN/8, x7, x1, x3) + +inst_233: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x318 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x082 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b18; op2val:0x3c82; +op3val:0xfbff; valaddr_reg:x5; val_offset:621*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 621*FLEN/8, x7, x1, x3) + +inst_234: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x054 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x363 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7054; op2val:0xc763; +op3val:0xfbff; valaddr_reg:x5; val_offset:624*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 624*FLEN/8, x7, x1, x3) + +inst_235: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x068 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x341 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7868; op2val:0x3f41; +op3val:0xfbff; valaddr_reg:x5; val_offset:627*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 627*FLEN/8, x7, x1, x3) + +inst_236: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2ab and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0cb and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6eab; op2val:0xc8cb; +op3val:0xfbff; valaddr_reg:x5; val_offset:630*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 630*FLEN/8, x7, x1, x3) + +inst_237: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x102 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x262 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6902; op2val:0x4e62; +op3val:0xfbff; valaddr_reg:x5; val_offset:633*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 633*FLEN/8, x7, x1, x3) + +inst_238: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0ae and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2d4 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6cae; op2val:0xbed4; +op3val:0xfbff; valaddr_reg:x5; val_offset:636*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 636*FLEN/8, x7, x1, x3) + +inst_239: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ed and fs2 == 0 and fe2 == 0x0c and fm2 == 0x09e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aed; op2val:0x309e; +op3val:0xfbff; valaddr_reg:x5; val_offset:639*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 639*FLEN/8, x7, x1, x3) + +inst_240: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x24d and fs2 == 1 and fe2 == 0x0d and fm2 == 0x113 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a4d; op2val:0xb513; +op3val:0xfbff; valaddr_reg:x5; val_offset:642*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 642*FLEN/8, x7, x1, x3) + +inst_241: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x29f and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0d3 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a9f; op2val:0x34d3; +op3val:0xfbff; valaddr_reg:x5; val_offset:645*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 645*FLEN/8, x7, x1, x3) + +inst_242: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x173 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1dd and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7573; op2val:0xbddd; +op3val:0xfbff; valaddr_reg:x5; val_offset:648*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 648*FLEN/8, x7, x1, x3) + +inst_243: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0eb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x280 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78eb; op2val:0x3a80; +op3val:0xfbff; valaddr_reg:x5; val_offset:651*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 651*FLEN/8, x7, x1, x3) + +inst_244: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x240 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x11d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a40; op2val:0xbd1d; +op3val:0xfbff; valaddr_reg:x5; val_offset:654*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 654*FLEN/8, x7, x1, x3) + +inst_245: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x20b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x14a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x760b; op2val:0x414a; +op3val:0xfbff; valaddr_reg:x5; val_offset:657*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 657*FLEN/8, x7, x1, x3) + +inst_246: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x090 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x302 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7890; op2val:0xc302; +op3val:0xfbff; valaddr_reg:x5; val_offset:660*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 660*FLEN/8, x7, x1, x3) + +inst_247: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x327 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x078 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7327; op2val:0x4878; +op3val:0xfbff; valaddr_reg:x5; val_offset:663*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 663*FLEN/8, x7, x1, x3) + +inst_248: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x13a and fs2 == 1 and fe2 == 0x14 and fm2 == 0x21d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d3a; op2val:0xd21d; +op3val:0xfbff; valaddr_reg:x5; val_offset:666*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 666*FLEN/8, x7, x1, x3) + +inst_249: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x044 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x37f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7444; op2val:0x4b7f; +op3val:0xfbff; valaddr_reg:x5; val_offset:669*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 669*FLEN/8, x7, x1, x3) + +inst_250: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x31f and fs2 == 1 and fe2 == 0x12 and fm2 == 0x07d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b1f; op2val:0xc87d; +op3val:0xfbff; valaddr_reg:x5; val_offset:672*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 672*FLEN/8, x7, x1, x3) + +inst_251: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x083 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x316 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7883; op2val:0x4b16; +op3val:0xfbff; valaddr_reg:x5; val_offset:675*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 675*FLEN/8, x7, x1, x3) + +inst_252: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x365 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b65; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:678*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 678*FLEN/8, x7, x1, x3) + +inst_253: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x352 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7752; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:681*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 681*FLEN/8, x7, x1, x3) + +inst_254: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x06e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x746e; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:684*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 684*FLEN/8, x7, x1, x3) + +inst_255: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x24b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a4b; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:687*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 687*FLEN/8, x7, x1, x3) + +inst_256: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x29e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a9e; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:690*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 690*FLEN/8, x7, x1, x3) + +inst_257: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x258 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6258; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:693*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 693*FLEN/8, x7, x1, x3) + +inst_258: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1dd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ddd; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:696*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 696*FLEN/8, x7, x1, x3) + +inst_259: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x35d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f5d; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:699*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 699*FLEN/8, x7, x1, x3) + +inst_260: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x313 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b13; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:702*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 702*FLEN/8, x7, x1, x3) + +inst_261: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x11f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x691f; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:705*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 705*FLEN/8, x7, x1, x3) + +inst_262: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73aa; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:708*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 708*FLEN/8, x7, x1, x3) + +inst_263: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7be6; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:711*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 711*FLEN/8, x7, x1, x3) + +inst_264: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x364 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f64; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:714*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 714*FLEN/8, x7, x1, x3) + +inst_265: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x15a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x715a; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:717*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 717*FLEN/8, x7, x1, x3) + +inst_266: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3b8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73b8; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:720*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 720*FLEN/8, x7, x1, x3) + +inst_267: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f2; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:723*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 723*FLEN/8, x7, x1, x3) + +inst_268: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x294 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e94; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:726*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 726*FLEN/8, x7, x1, x3) + +inst_269: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x348 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b48; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:729*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 729*FLEN/8, x7, x1, x3) + +inst_270: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x20c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x760c; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:732*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 732*FLEN/8, x7, x1, x3) + +inst_271: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bc2; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:735*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 735*FLEN/8, x7, x1, x3) + +inst_272: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x345 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b45; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:738*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 738*FLEN/8, x7, x1, x3) + +inst_273: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0b3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74b3; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:741*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 741*FLEN/8, x7, x1, x3) + +inst_274: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x00d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x740d; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:744*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 744*FLEN/8, x7, x1, x3) + +inst_275: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77a0; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:747*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 747*FLEN/8, x7, x1, x3) + +inst_276: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x267 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e67; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:750*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 750*FLEN/8, x7, x1, x3) + +inst_277: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x136 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7936; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:753*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 753*FLEN/8, x7, x1, x3) + +inst_278: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x112 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6912; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:756*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 756*FLEN/8, x7, x1, x3) + +inst_279: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x162 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6162; op2val:0x1; +op3val:0xfbff; valaddr_reg:x5; val_offset:759*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 759*FLEN/8, x7, x1, x3) + +inst_280: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bdb; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:762*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 762*FLEN/8, x7, x1, x3) + +inst_281: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ba and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74ba; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:765*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 765*FLEN/8, x7, x1, x3) + +inst_282: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x704c; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:768*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 768*FLEN/8, x7, x1, x3) + +inst_283: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ac6; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:771*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 771*FLEN/8, x7, x1, x3) +RVTEST_SIGBASE(x1,signature_x1_2) + +inst_284: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ec and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77ec; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:774*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 774*FLEN/8, x7, x1, x3) + +inst_285: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x330 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7730; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:777*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 777*FLEN/8, x7, x1, x3) + +inst_286: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x135 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7935; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:780*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 780*FLEN/8, x7, x1, x3) + +inst_287: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x24e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a4e; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:783*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 783*FLEN/8, x7, x1, x3) + +inst_288: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e01; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:786*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 786*FLEN/8, x7, x1, x3) + +inst_289: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x341 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6741; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:789*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 789*FLEN/8, x7, x1, x3) + +inst_290: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2eb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76eb; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:792*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 792*FLEN/8, x7, x1, x3) + +inst_291: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x218 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a18; op2val:0x0; +op3val:0xfbff; valaddr_reg:x5; val_offset:795*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 795*FLEN/8, x7, x1, x3) + +inst_292: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x054 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7854; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:798*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 798*FLEN/8, x7, x1, x3) + +inst_293: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2c0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76c0; op2val:0x8000; +op3val:0xfbff; valaddr_reg:x5; val_offset:801*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 801*FLEN/8, x7, x1, x3) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(28748,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(28748,16,FLEN) +NAN_BOXED(31430,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31259,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29716,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30700,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(30700,16,FLEN) +NAN_BOXED(30512,32,FLEN) +NAN_BOXED(30512,16,FLEN) +NAN_BOXED(30512,16,FLEN) +NAN_BOXED(31029,32,FLEN) +NAN_BOXED(31029,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31310,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(28161,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(26433,32,FLEN) +NAN_BOXED(26433,32,FLEN) +NAN_BOXED(26433,16,FLEN) +NAN_BOXED(31406,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30443,32,FLEN) +NAN_BOXED(30443,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(22615,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64511,16,FLEN) +test_dataset_1: +NAN_BOXED(30495,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31173,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29521,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31630,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31541,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(26580,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(26243,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30804,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31618,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30232,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29421,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30400,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(0,16,FLEN) +test_dataset_2: +NAN_BOXED(26479,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29463,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30464,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30701,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29556,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29538,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29439,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30553,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29858,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(25984,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31410,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30835,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31010,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29170,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31727,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31456,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28603,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30034,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31172,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31151,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31612,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30400,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31395,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31068,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29914,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30898,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31502,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31428,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30730,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30901,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(26731,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29635,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31328,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30368,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29064,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30819,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31135,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31076,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30206,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30469,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30736,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31289,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30762,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30282,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30676,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(26514,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(27024,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31135,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31708,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30910,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30283,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29042,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30724,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31706,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31273,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30800,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31457,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29549,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30747,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31645,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30878,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30551,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29774,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30817,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31655,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(24027,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31300,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31375,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31510,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31211,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31352,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30757,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30845,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30416,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(27438,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31476,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30862,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29284,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30729,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30657,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30132,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30088,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30798,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30972,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30949,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30547,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(26409,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29528,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29099,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30892,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31458,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31330,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31327,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31367,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29717,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31419,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31073,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(27987,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(25670,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(25461,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31242,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29691,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28417,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30974,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30082,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(27762,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(28955,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30775,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29024,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29789,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31152,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30533,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29990,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) 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+NAN_BOXED(30400,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x2_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_1: + .fill 30*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x4_0: + .fill 26*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_0: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_2: + .fill 20*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fnmadd_b2-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fnmadd_b2-01.S new file mode 100644 index 000000000..22897600b --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fnmadd_b2-01.S @@ -0,0 +1,1419 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 06:03:37 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fnmadd.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fnmadd.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fnmadd_b2 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fnmadd_b2) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x6,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==x31, rs2==x2, rs3==x31, rd==x28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x04a and fs2 == 0 and fe2 == 0x0c and fm2 == 0x052 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x31; op2:x2; op3:x31; dest:x28; op1val:0x4a; op2val:0x3052; +op3val:0x4a; valaddr_reg:x6; val_offset:0*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x28, x31, x2, x31, dyn, 0, 0, x6, 0*FLEN/8, x9, x1, x5) + +inst_1: +// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==x29, rs2==x25, rs3==x25, rd==x26,fs1 == 0 and fe1 == 0x00 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x218 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x062 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x29; op2:x25; op3:x25; dest:x26; op1val:0x3f; op2val:0x3e18; +op3val:0x3e18; valaddr_reg:x6; val_offset:3*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x26, x29, x25, x25, dyn, 0, 0, x6, 3*FLEN/8, x9, x1, x5) + +inst_2: +// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==x21, rs2==x3, rs3==x30, rd==x11,fs1 == 0 and fe1 == 0x00 and fm1 == 0x022 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x387 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x005 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x21; op2:x3; op3:x30; dest:x11; op1val:0x22; op2val:0x2787; +op3val:0x5; valaddr_reg:x6; val_offset:6*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x11, x21, x3, x30, dyn, 0, 0, x6, 6*FLEN/8, x9, x1, x5) + +inst_3: +// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==x4, rs2==x30, rs3==x29, rd==x30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x176 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x013 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x4; op2:x30; op3:x29; dest:x30; op1val:0x1; op2val:0x4976; +op3val:0x13; valaddr_reg:x6; val_offset:9*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x30, x4, x30, x29, dyn, 0, 0, x6, 9*FLEN/8, x9, x1, x5) + +inst_4: +// rs1 == rd == rs3 != rs2, rs1==x22, rs2==x15, rs3==x22, rd==x22,fs1 == 0 and fe1 == 0x00 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1a5 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x04c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x22; op2:x15; op3:x22; dest:x22; op1val:0x55; op2val:0x39a5; +op3val:0x55; valaddr_reg:x6; val_offset:12*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x22, x22, x15, x22, dyn, 0, 0, x6, 12*FLEN/8, x9, x1, x5) + +inst_5: +// rs1 == rs2 == rs3 != rd, rs1==x26, rs2==x26, rs3==x26, rd==x29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x03d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x053 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x062 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x26; op2:x26; op3:x26; dest:x29; op1val:0x3d; op2val:0x3d; +op3val:0x3d; valaddr_reg:x6; val_offset:15*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x29, x26, x26, x26, dyn, 0, 0, x6, 15*FLEN/8, x9, x1, x5) + +inst_6: +// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==x11, rs2==x11, rs3==x27, rd==x2,fs1 == 0 and fe1 == 0x00 and fm1 == 0x05f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x163 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x030 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x11; op2:x11; op3:x27; dest:x2; op1val:0x5f; op2val:0x5f; +op3val:0x30; valaddr_reg:x6; val_offset:18*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x2, x11, x11, x27, dyn, 0, 0, x6, 18*FLEN/8, x9, x1, x5) + +inst_7: +// rd == rs2 == rs3 != rs1, rs1==x17, rs2==x10, rs3==x10, rd==x10,fs1 == 0 and fe1 == 0x00 and fm1 == 0x029 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1a8 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x063 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x17; op2:x10; op3:x10; dest:x10; op1val:0x29; op2val:0xb9a8; +op3val:0xb9a8; valaddr_reg:x6; val_offset:21*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x10, x17, x10, x10, dyn, 0, 0, x6, 21*FLEN/8, x9, x1, x5) + +inst_8: +// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==x18, rs2==x19, rs3==x13, rd==x18,fs1 == 0 and fe1 == 0x00 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x15 and fm2 == 0x09a and fs3 == 0 and fe3 == 0x00 and fm3 == 0x023 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x18; op2:x19; op3:x13; dest:x18; op1val:0x3; op2val:0xd49a; +op3val:0x23; valaddr_reg:x6; val_offset:24*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x18, x18, x19, x13, dyn, 0, 0, x6, 24*FLEN/8, x9, x1, x5) + +inst_9: +// rs1 == rs2 == rs3 == rd, rs1==x8, rs2==x8, rs3==x8, rd==x8,fs1 == 0 and fe1 == 0x00 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x11 and fm2 == 0x3b6 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x01a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x8; op2:x8; op3:x8; dest:x8; op1val:0x3f; op2val:0x3f; +op3val:0x3f; valaddr_reg:x6; val_offset:27*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x8, x8, x8, x8, dyn, 0, 0, x6, 27*FLEN/8, x9, x1, x5) + +inst_10: +// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==x3, rs2==x18, rs3==x24, rd==x24,fs1 == 0 and fe1 == 0x00 and fm1 == 0x05e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x098 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x035 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x3; op2:x18; op3:x24; dest:x24; op1val:0x5e; op2val:0x3898; +op3val:0x35; valaddr_reg:x6; val_offset:30*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x24, x3, x18, x24, dyn, 0, 0, x6, 30*FLEN/8, x9, x1, x5) + +inst_11: +// rs1 == rs2 == rd != rs3, rs1==x7, rs2==x7, rs3==x16, rd==x7,fs1 == 0 and fe1 == 0x00 and fm1 == 0x045 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x02c and fs3 == 0 and fe3 == 0x00 and fm3 == 0x046 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x7; op2:x7; op3:x16; dest:x7; op1val:0x45; op2val:0x45; +op3val:0x46; valaddr_reg:x6; val_offset:33*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x7, x7, x7, x16, dyn, 0, 0, x6, 33*FLEN/8, x9, x1, x5) + +inst_12: +// rs1==x24, rs2==x22, rs3==x1, rd==x19,fs1 == 0 and fe1 == 0x00 and fm1 == 0x058 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x22e and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x24; op2:x22; op3:x1; dest:x19; op1val:0x58; op2val:0x322e; +op3val:0xd; valaddr_reg:x6; val_offset:36*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x19, x24, x22, x1, dyn, 0, 0, x6, 36*FLEN/8, x9, x1, x5) + +inst_13: +// rs1==x27, rs2==x31, rs3==x15, rd==x23,fs1 == 0 and fe1 == 0x00 and fm1 == 0x019 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x27a and fs3 == 0 and fe3 == 0x00 and fm3 == 0x049 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x27; op2:x31; op3:x15; dest:x23; op1val:0x19; op2val:0x427a; +op3val:0x49; valaddr_reg:x6; val_offset:39*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x23, x27, x31, x15, dyn, 0, 0, x6, 39*FLEN/8, x9, x1, x5) +RVTEST_VALBASEUPD(x8,test_dataset_1) + +inst_14: +// rs1==x25, rs2==x13, rs3==x2, rd==x21,fs1 == 0 and fe1 == 0x00 and fm1 == 0x047 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1f8 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x05a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x25; op2:x13; op3:x2; dest:x21; op1val:0x47; op2val:0x3df8; +op3val:0x5a; valaddr_reg:x8; val_offset:0*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x21, x25, x13, x2, dyn, 0, 0, x8, 0*FLEN/8, x11, x1, x5) + +inst_15: +// rs1==x30, rs2==x21, rs3==x11, rd==x31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x05e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x19d and fs3 == 0 and fe3 == 0x00 and fm3 == 0x022 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x21; op3:x11; dest:x31; op1val:0x5e; op2val:0x399d; +op3val:0x22; valaddr_reg:x8; val_offset:3*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x21, x11, dyn, 0, 0, x8, 3*FLEN/8, x11, x1, x5) + +inst_16: +// rs1==x2, rs2==x4, rs3==x0, rd==x16,fs1 == 0 and fe1 == 0x00 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2ba and fs3 == 0 and fe3 == 0x00 and fm3 == 0x04f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x2; op2:x4; op3:x0; dest:x16; op1val:0x55; op2val:0x3eba; +op3val:0x0; valaddr_reg:x8; val_offset:6*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x16, x2, x4, x0, dyn, 0, 0, x8, 6*FLEN/8, x11, x1, x5) + +inst_17: +// rs1==x12, rs2==x9, rs3==x21, rd==x0,fs1 == 0 and fe1 == 0x00 and fm1 == 0x058 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x25d and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x12; op2:x9; op3:x21; dest:x0; op1val:0x58; op2val:0x3e5d; +op3val:0xc; valaddr_reg:x8; val_offset:9*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x0, x12, x9, x21, dyn, 0, 0, x8, 9*FLEN/8, x11, x1, x7) +RVTEST_SIGBASE(x2,signature_x2_0) + +inst_18: +// rs1==x6, rs2==x12, rs3==x5, rd==x27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x037 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x16f and fs3 == 0 and fe3 == 0x00 and fm3 == 0x02b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x6; op2:x12; op3:x5; dest:x27; op1val:0x37; op2val:0x456f; +op3val:0x2b; valaddr_reg:x8; val_offset:12*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x27, x6, x12, x5, dyn, 0, 0, x8, 12*FLEN/8, x11, x2, x7) + +inst_19: +// rs1==x15, rs2==x28, rs3==x6, rd==x20,fs1 == 0 and fe1 == 0x00 and fm1 == 0x00c and fs2 == 0 and fe2 == 0x14 and fm2 == 0x1d2 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x02f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x15; op2:x28; op3:x6; dest:x20; op1val:0xc; op2val:0x51d2; +op3val:0x2f; valaddr_reg:x8; val_offset:15*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x20, x15, x28, x6, dyn, 0, 0, x8, 15*FLEN/8, x11, x2, x7) + +inst_20: +// rs1==x16, rs2==x24, rs3==x12, rd==x15,fs1 == 0 and fe1 == 0x0f and fm1 == 0x035 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x39b and fs3 == 0 and fe3 == 0x0f and fm3 == 0x021 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x16; op2:x24; op3:x12; dest:x15; op1val:0x3c35; op2val:0x279b; +op3val:0x3c21; valaddr_reg:x8; val_offset:18*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x15, x16, x24, x12, dyn, 0, 0, x8, 18*FLEN/8, x11, x2, x7) + +inst_21: +// rs1==x20, rs2==x29, rs3==x4, rd==x9,fs1 == 0 and fe1 == 0x0f and fm1 == 0x039 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x135 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x05a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x20; op2:x29; op3:x4; dest:x9; op1val:0x3c39; op2val:0x2d35; +op3val:0x3c5a; valaddr_reg:x8; val_offset:21*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x9, x20, x29, x4, dyn, 0, 0, x8, 21*FLEN/8, x11, x2, x7) + +inst_22: +// rs1==x23, rs2==x16, rs3==x14, rd==x25,fs1 == 0 and fe1 == 0x0f and fm1 == 0x00d and fs2 == 0 and fe2 == 0x0b and fm2 == 0x1bd and fs3 == 0 and fe3 == 0x0f and fm3 == 0x061 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x23; op2:x16; op3:x14; dest:x25; op1val:0x3c0d; op2val:0x2dbd; +op3val:0x3c61; valaddr_reg:x8; val_offset:24*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x25, x23, x16, x14, dyn, 0, 0, x8, 24*FLEN/8, x11, x2, x7) + +inst_23: +// rs1==x9, rs2==x23, rs3==x18, rd==x3,fs1 == 0 and fe1 == 0x0f and fm1 == 0x01a and fs2 == 0 and fe2 == 0x0b and fm2 == 0x0ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x05a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x9; op2:x23; op3:x18; dest:x3; op1val:0x3c1a; op2val:0x2cff; +op3val:0x3c5a; valaddr_reg:x8; val_offset:27*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x3, x9, x23, x18, dyn, 0, 0, x8, 27*FLEN/8, x11, x2, x7) + +inst_24: +// rs1==x5, rs2==x27, rs3==x7, rd==x12,fs1 == 0 and fe1 == 0x0f and fm1 == 0x052 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x117 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x026 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x5; op2:x27; op3:x7; dest:x12; op1val:0x3c52; op2val:0x2517; +op3val:0x3c26; valaddr_reg:x8; val_offset:30*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x12, x5, x27, x7, dyn, 0, 0, x8, 30*FLEN/8, x11, x2, x7) + +inst_25: +// rs1==x10, rs2==x6, rs3==x9, rd==x13,fs1 == 0 and fe1 == 0x0f and fm1 == 0x00d and fs2 == 1 and fe2 == 0x09 and fm2 == 0x26b and fs3 == 0 and fe3 == 0x0f and fm3 == 0x006 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x10; op2:x6; op3:x9; dest:x13; op1val:0x3c0d; op2val:0xa66b; +op3val:0x3c06; valaddr_reg:x8; val_offset:33*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x13, x10, x6, x9, dyn, 0, 0, x8, 33*FLEN/8, x11, x2, x7) + +inst_26: +// rs1==x14, rs2==x17, rs3==x28, rd==x4,fs1 == 0 and fe1 == 0x0f and fm1 == 0x04c and fs2 == 1 and fe2 == 0x0a and fm2 == 0x06b and fs3 == 0 and fe3 == 0x0f and fm3 == 0x01a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x14; op2:x17; op3:x28; dest:x4; op1val:0x3c4c; op2val:0xa86b; +op3val:0x3c1a; valaddr_reg:x8; val_offset:36*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x4, x14, x17, x28, dyn, 0, 0, x8, 36*FLEN/8, x11, x2, x7) +RVTEST_VALBASEUPD(x3,test_dataset_2) + +inst_27: +// rs1==x19, rs2==x14, rs3==x3, rd==x17,fs1 == 0 and fe1 == 0x0f and fm1 == 0x054 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x0ad and fs3 == 0 and fe3 == 0x0f and fm3 == 0x02f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x19; op2:x14; op3:x3; dest:x17; op1val:0x3c54; op2val:0xacad; +op3val:0x3c2f; valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x17, x19, x14, x3, dyn, 0, 0, x3, 0*FLEN/8, x4, x2, x7) + +inst_28: +// rs1==x28, rs2==x20, rs3==x23, rd==x14,fs1 == 0 and fe1 == 0x0f and fm1 == 0x03f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2cc and fs3 == 0 and fe3 == 0x0f and fm3 == 0x019 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x28; op2:x20; op3:x23; dest:x14; op1val:0x3c3f; op2val:0xb2cc; +op3val:0x3c19; valaddr_reg:x3; val_offset:3*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x14, x28, x20, x23, dyn, 0, 0, x3, 3*FLEN/8, x4, x2, x7) + +inst_29: +// rs1==x0, rs2==x1, rs3==x17, rd==x5,fs1 == 0 and fe1 == 0x0f and fm1 == 0x042 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x26d and fs3 == 0 and fe3 == 0x0f and fm3 == 0x04a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x0; op2:x1; op3:x17; dest:x5; op1val:0x0; op2val:0xb66d; +op3val:0x3c4a; valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x5, x0, x1, x17, dyn, 0, 0, x3, 6*FLEN/8, x4, x2, x7) + +inst_30: +// rs1==x1, rs2==x0, rs3==x19, rd==x6,fs1 == 0 and fe1 == 0x0f and fm1 == 0x053 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3ba and fs3 == 0 and fe3 == 0x0f and fm3 == 0x05a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x1; op2:x0; op3:x19; dest:x6; op1val:0x3c53; op2val:0x0; +op3val:0x3c5a; valaddr_reg:x3; val_offset:9*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x6, x1, x0, x19, dyn, 0, 0, x3, 9*FLEN/8, x4, x2, x7) + +inst_31: +// rs1==x13, rs2==x5, rs3==x20, rd==x1,fs1 == 0 and fe1 == 0x0f and fm1 == 0x041 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x38b and fs3 == 0 and fe3 == 0x0f and fm3 == 0x004 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x13; op2:x5; op3:x20; dest:x1; op1val:0x3c41; op2val:0x3f8b; +op3val:0x3c04; valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x1, x13, x5, x20, dyn, 0, 0, x3, 12*FLEN/8, x4, x2, x7) + +inst_32: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x052 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x397 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x02f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c52; op2val:0x3f97; +op3val:0x3c2f; valaddr_reg:x3; val_offset:15*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 15*FLEN/8, x4, x2, x7) + +inst_33: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x020 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x00a and fs3 == 0 and fe3 == 0x0f and fm3 == 0x04e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c20; op2val:0x400a; +op3val:0x3c4e; valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 18*FLEN/8, x4, x2, x7) + +inst_34: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x038 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3c9 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x027 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c38; op2val:0x3fc9; +op3val:0x3c27; valaddr_reg:x3; val_offset:21*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 21*FLEN/8, x4, x2, x7) + +inst_35: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x02e and fs2 == 0 and fe2 == 0x10 and fm2 == 0x007 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x04c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c2e; op2val:0x4007; +op3val:0x3c4c; valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 24*FLEN/8, x4, x2, x7) + +inst_36: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x010 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x015 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x00c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c10; op2val:0x4015; +op3val:0x3c0c; valaddr_reg:x3; val_offset:27*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 27*FLEN/8, x4, x2, x7) + +inst_37: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x041 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x027 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x057 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c41; op2val:0x4027; +op3val:0x3c57; valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 30*FLEN/8, x4, x2, x7) + +inst_38: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x044 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x044 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x01a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c44; op2val:0x4044; +op3val:0x3c1a; valaddr_reg:x3; val_offset:33*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 33*FLEN/8, x4, x2, x7) + +inst_39: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x00f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x113 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x04e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c0f; op2val:0x4113; +op3val:0x3c4e; valaddr_reg:x3; val_offset:36*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 36*FLEN/8, x4, x2, x7) + +inst_40: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x266 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x023 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x55; op2val:0x3666; +op3val:0x23; valaddr_reg:x3; val_offset:39*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 39*FLEN/8, x4, x2, x7) + +inst_41: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x028 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x080 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x05d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x28; op2val:0x4080; +op3val:0x5d; valaddr_reg:x3; val_offset:42*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 42*FLEN/8, x4, x2, x7) + +inst_42: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x01a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2c4 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x031 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1a; op2val:0x3ec4; +op3val:0x31; valaddr_reg:x3; val_offset:45*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 45*FLEN/8, x4, x2, x7) + +inst_43: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03e and fs2 == 0 and fe2 == 0x0d and fm2 == 0x129 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x01d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3e; op2val:0x3529; +op3val:0x1d; valaddr_reg:x3; val_offset:48*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 48*FLEN/8, x4, x2, x7) + +inst_44: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x012 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x2aa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x04d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x12; op2val:0x42aa; +op3val:0x4d; valaddr_reg:x3; val_offset:51*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 51*FLEN/8, x4, x2, x7) + +inst_45: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x01b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x038 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x05a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1b; op2val:0x4038; +op3val:0x5a; valaddr_reg:x3; val_offset:54*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 54*FLEN/8, x4, x2, x7) + +inst_46: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x043 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x385 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x43; op2val:0xbb85; +op3val:0x2; valaddr_reg:x3; val_offset:57*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 57*FLEN/8, x4, x2, x7) + +inst_47: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x019 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x047 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x016 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x19; op2val:0xc447; +op3val:0x16; valaddr_reg:x3; val_offset:60*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 60*FLEN/8, x4, x2, x7) + +inst_48: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x340 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x053 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3; op2val:0xd340; +op3val:0x53; valaddr_reg:x3; val_offset:63*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 63*FLEN/8, x4, x2, x7) + +inst_49: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x02b and fs2 == 1 and fe2 == 0x12 and fm2 == 0x120 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x048 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2b; op2val:0xc920; +op3val:0x48; valaddr_reg:x3; val_offset:66*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 66*FLEN/8, x4, x2, x7) + +inst_50: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x056 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x389 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x050 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x56; op2val:0x3b89; +op3val:0x50; valaddr_reg:x3; val_offset:69*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 69*FLEN/8, x4, x2, x7) + +inst_51: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x050 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x04c and fs3 == 0 and fe3 == 0x00 and fm3 == 0x028 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x50; op2val:0x384c; +op3val:0x28; valaddr_reg:x3; val_offset:72*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 72*FLEN/8, x4, x2, x7) + +inst_52: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x030 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x080 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x031 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30; op2val:0x3c80; +op3val:0x31; valaddr_reg:x3; val_offset:75*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 75*FLEN/8, x4, x2, x7) + +inst_53: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x044 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2f0 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x032 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x44; op2val:0x3af0; +op3val:0x32; valaddr_reg:x3; val_offset:78*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 78*FLEN/8, x4, x2, x7) + +inst_54: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x026 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x328 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x011 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x26; op2val:0x3b28; +op3val:0x11; valaddr_reg:x3; val_offset:81*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 81*FLEN/8, x4, x2, x7) + +inst_55: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x057 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x069 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x57; op2val:0x3c69; +op3val:0x3f; valaddr_reg:x3; val_offset:84*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 84*FLEN/8, x4, x2, x7) + +inst_56: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x25b and fs3 == 0 and fe3 == 0x00 and fm3 == 0x018 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7; op2val:0x4a5b; +op3val:0x18; valaddr_reg:x3; val_offset:87*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 87*FLEN/8, x4, x2, x7) + +inst_57: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x037 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x37d and fs3 == 0 and fe3 == 0x00 and fm3 == 0x04d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37; op2val:0x437d; +op3val:0x4d; valaddr_reg:x3; val_offset:90*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 90*FLEN/8, x4, x2, x7) + +inst_58: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x060 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x26a and fs3 == 0 and fe3 == 0x00 and fm3 == 0x033 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x60; op2val:0x426a; +op3val:0x33; valaddr_reg:x3; val_offset:93*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 93*FLEN/8, x4, x2, x7) + +inst_59: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00d and fs2 == 0 and fe2 == 0x14 and fm2 == 0x17b and fs3 == 0 and fe3 == 0x00 and fm3 == 0x039 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xd; op2val:0x517b; +op3val:0x39; valaddr_reg:x3; val_offset:96*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 96*FLEN/8, x4, x2, x7) + +inst_60: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x020 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x3e4 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x20; op2val:0xcfe4; +op3val:0xc; valaddr_reg:x3; val_offset:99*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 99*FLEN/8, x4, x2, x7) + +inst_61: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x04e and fs2 == 1 and fe2 == 0x12 and fm2 == 0x1fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x056 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4e; op2val:0xc9fe; +op3val:0x56; valaddr_reg:x3; val_offset:102*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 102*FLEN/8, x4, x2, x7) + +inst_62: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03a and fs2 == 1 and fe2 == 0x13 and fm2 == 0x024 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x03a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a; op2val:0xcc24; +op3val:0x3a; valaddr_reg:x3; val_offset:105*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 105*FLEN/8, x4, x2, x7) + +inst_63: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x031 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x120 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31; op2val:0xcd20; +op3val:0xa; valaddr_reg:x3; val_offset:108*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 108*FLEN/8, x4, x2, x7) + +inst_64: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x043 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x31a and fs3 == 0 and fe3 == 0x00 and fm3 == 0x037 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x43; op2val:0xcb1a; +op3val:0x37; valaddr_reg:x3; val_offset:111*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 111*FLEN/8, x4, x2, x7) + +inst_65: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03d and fs2 == 1 and fe2 == 0x12 and fm2 == 0x3cd and fs3 == 0 and fe3 == 0x00 and fm3 == 0x027 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3d; op2val:0xcbcd; +op3val:0x27; valaddr_reg:x3; val_offset:114*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 114*FLEN/8, x4, x2, x7) + +inst_66: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x05b and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0fa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x035 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5b; op2val:0xc8fa; +op3val:0x35; valaddr_reg:x3; val_offset:117*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 117*FLEN/8, x4, x2, x7) + +inst_67: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00b and fs2 == 1 and fe2 == 0x15 and fm2 == 0x0f1 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x019 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xb; op2val:0xd4f1; +op3val:0x19; valaddr_reg:x3; val_offset:120*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 120*FLEN/8, x4, x2, x7) + +inst_68: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x060 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x312 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x058 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x60; op2val:0xc712; +op3val:0x58; valaddr_reg:x3; val_offset:123*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 123*FLEN/8, x4, x2, x7) + +inst_69: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x023 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x278 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x03a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x23; op2val:0xca78; +op3val:0x3a; valaddr_reg:x3; val_offset:126*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 126*FLEN/8, x4, x2, x7) + +inst_70: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x13 and fm2 == 0x06c and fs3 == 0 and fe3 == 0x00 and fm3 == 0x05d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f; op2val:0x4c6c; +op3val:0x5d; valaddr_reg:x3; val_offset:129*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 129*FLEN/8, x4, x2, x7) + +inst_71: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x017 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x190 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x17; op2val:0x5190; +op3val:0x3; valaddr_reg:x3; val_offset:132*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 132*FLEN/8, x4, x2, x7) + +inst_72: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x003 and fs2 == 0 and fe2 == 0x17 and fm2 == 0x1aa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x045 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3; op2val:0x5daa; +op3val:0x45; valaddr_reg:x3; val_offset:135*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 135*FLEN/8, x4, x2, x7) + +inst_73: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x010 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x018 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x021 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x10; op2val:0x5418; +op3val:0x21; valaddr_reg:x3; val_offset:138*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 138*FLEN/8, x4, x2, x7) + +inst_74: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x04c and fs2 == 0 and fe2 == 0x12 and fm2 == 0x2ef and fs3 == 0 and fe3 == 0x00 and fm3 == 0x02f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c; op2val:0x4aef; +op3val:0x2f; valaddr_reg:x3; val_offset:141*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 141*FLEN/8, x4, x2, x7) + +inst_75: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x019 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x11e and fs3 == 0 and fe3 == 0x00 and fm3 == 0x021 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x19; op2val:0x511e; +op3val:0x21; valaddr_reg:x3; val_offset:144*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 144*FLEN/8, x4, x2, x7) + +inst_76: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x041 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x3d2 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x03a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x41; op2val:0x4bd2; +op3val:0x3a; valaddr_reg:x3; val_offset:147*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 147*FLEN/8, x4, x2, x7) + +inst_77: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x02b and fs2 == 0 and fe2 == 0x13 and fm2 == 0x197 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x043 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2b; op2val:0x4d97; +op3val:0x43; valaddr_reg:x3; val_offset:150*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 150*FLEN/8, x4, x2, x7) + +inst_78: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x021 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x236 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x035 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x21; op2val:0x4e36; +op3val:0x35; valaddr_reg:x3; val_offset:153*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 153*FLEN/8, x4, x2, x7) + +inst_79: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x036 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x176 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x04f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36; op2val:0x4976; +op3val:0x4f; valaddr_reg:x3; val_offset:156*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 156*FLEN/8, x4, x2, x7) + +inst_80: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x0a and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x023 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x43f; op2val:0x2800; +op3val:0x423; valaddr_reg:x3; val_offset:159*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 159*FLEN/8, x4, x2, x7) + +inst_81: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x04e and fs2 == 0 and fe2 == 0x0a and fm2 == 0x2da and fs3 == 0 and fe3 == 0x01 and fm3 == 0x03d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x44e; op2val:0x2ada; +op3val:0x43d; valaddr_reg:x3; val_offset:162*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 162*FLEN/8, x4, x2, x7) + +inst_82: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x2b1 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x03e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x455; op2val:0x2ab1; +op3val:0x43e; valaddr_reg:x3; val_offset:165*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 165*FLEN/8, x4, x2, x7) + +inst_83: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x08 and fm2 == 0x12e and fs3 == 0 and fe3 == 0x01 and fm3 == 0x013 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x43f; op2val:0x212e; +op3val:0x413; valaddr_reg:x3; val_offset:168*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 168*FLEN/8, x4, x2, x7) + +inst_84: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x05d and fs2 == 0 and fe2 == 0x09 and fm2 == 0x390 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x031 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x45d; op2val:0x2790; +op3val:0x431; valaddr_reg:x3; val_offset:171*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 171*FLEN/8, x4, x2, x7) + +inst_85: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x040 and fs2 == 0 and fe2 == 0x07 and fm2 == 0x387 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x028 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x440; op2val:0x1f87; +op3val:0x428; valaddr_reg:x3; val_offset:174*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 174*FLEN/8, x4, x2, x7) + +inst_86: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x052 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x368 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x03c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x452; op2val:0x9b68; +op3val:0x43c; valaddr_reg:x3; val_offset:177*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 177*FLEN/8, x4, x2, x7) + +inst_87: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x02a and fs2 == 1 and fe2 == 0x0b and fm2 == 0x0dc and fs3 == 0 and fe3 == 0x01 and fm3 == 0x02f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x42a; op2val:0xacdc; +op3val:0x42f; valaddr_reg:x3; val_offset:180*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 180*FLEN/8, x4, x2, x7) + +inst_88: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2c7 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x015 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x455; op2val:0xb2c7; +op3val:0x415; valaddr_reg:x3; val_offset:183*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 183*FLEN/8, x4, x2, x7) + +inst_89: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x050 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2b5 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x031 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x450; op2val:0xb6b5; +op3val:0x431; valaddr_reg:x3; val_offset:186*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 186*FLEN/8, x4, x2, x7) + +inst_90: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x059 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3a4 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x04e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x459; op2val:0x3fa4; +op3val:0x44e; valaddr_reg:x3; val_offset:189*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 189*FLEN/8, x4, x2, x7) + +inst_91: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x023 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3e5 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x029 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x423; op2val:0x3fe5; +op3val:0x429; valaddr_reg:x3; val_offset:192*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 192*FLEN/8, x4, x2, x7) + +inst_92: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x053 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x399 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x033 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x453; op2val:0x3f99; +op3val:0x433; valaddr_reg:x3; val_offset:195*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 195*FLEN/8, x4, x2, x7) + +inst_93: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3e9 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x05e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x43f; op2val:0x3fe9; +op3val:0x45e; valaddr_reg:x3; val_offset:198*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 198*FLEN/8, x4, x2, x7) + +inst_94: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x015 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x005 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x026 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x415; op2val:0x4005; +op3val:0x426; valaddr_reg:x3; val_offset:201*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 201*FLEN/8, x4, x2, x7) + +inst_95: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x048 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x398 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x448; op2val:0x3f98; +op3val:0x401; valaddr_reg:x3; val_offset:204*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 204*FLEN/8, x4, x2, x7) + +inst_96: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x050 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3dc and fs3 == 0 and fe3 == 0x01 and fm3 == 0x03a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x450; op2val:0x3fdc; +op3val:0x43a; valaddr_reg:x3; val_offset:207*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 207*FLEN/8, x4, x2, x7) + +inst_97: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x008 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x043 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x018 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x408; op2val:0x4043; +op3val:0x418; valaddr_reg:x3; val_offset:210*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 210*FLEN/8, x4, x2, x7) + +inst_98: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x004 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0a2 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x04f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x404; op2val:0x40a2; +op3val:0x44f; valaddr_reg:x3; val_offset:213*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 213*FLEN/8, x4, x2, x7) + +inst_99: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x049 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0b1 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x449; op2val:0x40b1; +op3val:0x40f; valaddr_reg:x3; val_offset:216*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 216*FLEN/8, x4, x2, x7) + +inst_100: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x058 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2b0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x05c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7858; op2val:0xbab0; +op3val:0x785c; valaddr_reg:x3; val_offset:219*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 219*FLEN/8, x4, x2, x7) + +inst_101: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x030 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x344 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x02f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7830; op2val:0xbb44; +op3val:0x782f; valaddr_reg:x3; val_offset:222*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 222*FLEN/8, x4, x2, x7) + +inst_102: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x040 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2ef and fs3 == 0 and fe3 == 0x1e and fm3 == 0x04c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7840; op2val:0xbaef; +op3val:0x784c; valaddr_reg:x3; val_offset:225*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 225*FLEN/8, x4, x2, x7) + +inst_103: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x008 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3ac and fs3 == 0 and fe3 == 0x1e and fm3 == 0x019 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7808; op2val:0xbbac; +op3val:0x7819; valaddr_reg:x3; val_offset:228*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 228*FLEN/8, x4, x2, x7) + +inst_104: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x014 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x372 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x023 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7814; op2val:0xbb72; +op3val:0x7823; valaddr_reg:x3; val_offset:231*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 231*FLEN/8, x4, x2, x7) + +inst_105: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x32c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x784f; op2val:0xbb2c; +op3val:0x7802; valaddr_reg:x3; val_offset:234*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 234*FLEN/8, x4, x2, x7) + +inst_106: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x037 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x29b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x044 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7837; op2val:0xba9b; +op3val:0x7844; valaddr_reg:x3; val_offset:237*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 237*FLEN/8, x4, x2, x7) + +inst_107: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x03f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x283 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x783f; op2val:0xba83; +op3val:0x780a; valaddr_reg:x3; val_offset:240*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 240*FLEN/8, x4, x2, x7) + +inst_108: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x03d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x16f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x01e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x783d; op2val:0xb96f; +op3val:0x781e; valaddr_reg:x3; val_offset:243*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 243*FLEN/8, x4, x2, x7) + +inst_109: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00d and fs2 == 1 and fe2 == 0x0d and fm2 == 0x324 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x030 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x780d; op2val:0xb724; +op3val:0x7830; valaddr_reg:x3; val_offset:246*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 246*FLEN/8, x4, x2, x7) + +inst_110: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1c4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x013 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x782f; op2val:0x41c4; +op3val:0x7813; valaddr_reg:x3; val_offset:249*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 249*FLEN/8, x4, x2, x7) + +inst_111: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x058 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1aa and fs3 == 0 and fe3 == 0x1e and fm3 == 0x051 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7858; op2val:0x41aa; +op3val:0x7851; valaddr_reg:x3; val_offset:252*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 252*FLEN/8, x4, x2, x7) + +inst_112: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x020 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1f4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x04e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7820; op2val:0x41f4; +op3val:0x784e; valaddr_reg:x3; val_offset:255*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 255*FLEN/8, x4, x2, x7) + +inst_113: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x029 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1c9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x013 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7829; op2val:0x41c9; +op3val:0x7813; valaddr_reg:x3; val_offset:258*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 258*FLEN/8, x4, x2, x7) + +inst_114: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x005 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x218 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x051 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7805; op2val:0x4218; +op3val:0x7851; valaddr_reg:x3; val_offset:261*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 261*FLEN/8, x4, x2, x7) + +inst_115: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x056 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x17f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7856; op2val:0x417f; +op3val:0x780d; valaddr_reg:x3; val_offset:264*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 264*FLEN/8, x4, x2, x7) + +inst_116: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x05c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x169 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x785c; op2val:0x4169; +op3val:0x780e; valaddr_reg:x3; val_offset:267*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 267*FLEN/8, x4, x2, x7) + +inst_117: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x006 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1e0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x053 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7806; op2val:0x41e0; +op3val:0x7853; valaddr_reg:x3; val_offset:270*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 270*FLEN/8, x4, x2, x7) + +inst_118: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x03e and fs2 == 0 and fe2 == 0x10 and fm2 == 0x14b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x03c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x783e; op2val:0x414b; +op3val:0x783c; valaddr_reg:x3; val_offset:273*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 273*FLEN/8, x4, x2, x7) + +inst_119: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x05d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x099 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x009 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x785d; op2val:0x4099; +op3val:0x7809; valaddr_reg:x3; val_offset:276*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 276*FLEN/8, x4, x2, x7) + +inst_120: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x04a and fs2 == 0 and fe2 == 0x0c and fm2 == 0x052 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4a; op2val:0x3052; +op3val:0xb; valaddr_reg:x3; val_offset:279*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 279*FLEN/8, x4, x2, x7) + +inst_121: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x218 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x062 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f; op2val:0x3e18; +op3val:0x62; valaddr_reg:x3; val_offset:282*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 282*FLEN/8, x4, x2, x7) + +inst_122: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1a5 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x04c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x55; op2val:0x39a5; +op3val:0x4c; valaddr_reg:x3; val_offset:285*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 285*FLEN/8, x4, x2, x7) + +inst_123: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x053 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x062 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3d; op2val:0x3c53; +op3val:0x62; valaddr_reg:x3; val_offset:288*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 288*FLEN/8, x4, x2, x7) + +inst_124: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x05f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x163 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x030 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5f; op2val:0xb163; +op3val:0x30; valaddr_reg:x3; val_offset:291*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 291*FLEN/8, x4, x2, x7) + +inst_125: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x029 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1a8 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x063 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x29; op2val:0xb9a8; +op3val:0x63; valaddr_reg:x3; val_offset:294*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 294*FLEN/8, x4, x2, x7) + +inst_126: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x11 and fm2 == 0x3b6 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x01a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f; op2val:0xc7b6; +op3val:0x1a; valaddr_reg:x3; val_offset:297*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 297*FLEN/8, x4, x2, x7) + +inst_127: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x045 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x02c and fs3 == 0 and fe3 == 0x00 and fm3 == 0x046 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x45; op2val:0x3c2c; +op3val:0x46; valaddr_reg:x3; val_offset:300*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 300*FLEN/8, x4, x2, x7) + +inst_128: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2ba and fs3 == 0 and fe3 == 0x00 and fm3 == 0x04f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x55; op2val:0x3eba; +op3val:0x4f; valaddr_reg:x3; val_offset:303*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 303*FLEN/8, x4, x2, x7) + +inst_129: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x058 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x25d and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x58; op2val:0x3e5d; +op3val:0xc; valaddr_reg:x3; val_offset:306*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 306*FLEN/8, x4, x2, x7) + +inst_130: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x042 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x26d and fs3 == 0 and fe3 == 0x0f and fm3 == 0x04a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c42; op2val:0xb66d; +op3val:0x3c4a; valaddr_reg:x3; val_offset:309*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 309*FLEN/8, x4, x2, x7) + +inst_131: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x053 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3ba and fs3 == 0 and fe3 == 0x0f and fm3 == 0x05a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c53; op2val:0x3fba; +op3val:0x3c5a; valaddr_reg:x3; val_offset:312*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 312*FLEN/8, x4, x2, x7) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(74,32,FLEN) +NAN_BOXED(12370,32,FLEN) +NAN_BOXED(74,32,FLEN) +NAN_BOXED(63,32,FLEN) +NAN_BOXED(15896,32,FLEN) +NAN_BOXED(15896,32,FLEN) +NAN_BOXED(34,32,FLEN) +NAN_BOXED(10119,32,FLEN) +NAN_BOXED(5,32,FLEN) +NAN_BOXED(1,32,FLEN) +NAN_BOXED(18806,32,FLEN) +NAN_BOXED(19,32,FLEN) +NAN_BOXED(85,32,FLEN) +NAN_BOXED(14757,32,FLEN) +NAN_BOXED(85,32,FLEN) +NAN_BOXED(61,32,FLEN) +NAN_BOXED(61,32,FLEN) +NAN_BOXED(61,32,FLEN) +NAN_BOXED(95,32,FLEN) +NAN_BOXED(95,16,FLEN) +NAN_BOXED(48,32,FLEN) +NAN_BOXED(41,32,FLEN) +NAN_BOXED(47528,16,FLEN) +NAN_BOXED(47528,32,FLEN) +NAN_BOXED(3,32,FLEN) +NAN_BOXED(54426,16,FLEN) +NAN_BOXED(35,32,FLEN) +NAN_BOXED(63,32,FLEN) +NAN_BOXED(63,16,FLEN) +NAN_BOXED(63,32,FLEN) +NAN_BOXED(94,32,FLEN) +NAN_BOXED(14488,32,FLEN) +NAN_BOXED(53,32,FLEN) +NAN_BOXED(69,32,FLEN) +NAN_BOXED(69,32,FLEN) +NAN_BOXED(70,32,FLEN) +NAN_BOXED(88,32,FLEN) +NAN_BOXED(12846,32,FLEN) +NAN_BOXED(13,32,FLEN) +NAN_BOXED(25,32,FLEN) +NAN_BOXED(17018,32,FLEN) +NAN_BOXED(73,32,FLEN) +test_dataset_1: +NAN_BOXED(71,32,FLEN) +NAN_BOXED(15864,32,FLEN) +NAN_BOXED(90,32,FLEN) +NAN_BOXED(94,32,FLEN) +NAN_BOXED(14749,32,FLEN) +NAN_BOXED(34,32,FLEN) +NAN_BOXED(85,32,FLEN) +NAN_BOXED(16058,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(88,32,FLEN) +NAN_BOXED(15965,32,FLEN) +NAN_BOXED(12,32,FLEN) +NAN_BOXED(55,32,FLEN) +NAN_BOXED(17775,32,FLEN) +NAN_BOXED(43,32,FLEN) +NAN_BOXED(12,32,FLEN) +NAN_BOXED(20946,32,FLEN) +NAN_BOXED(47,32,FLEN) +NAN_BOXED(15413,32,FLEN) +NAN_BOXED(10139,32,FLEN) +NAN_BOXED(15393,32,FLEN) +NAN_BOXED(15417,32,FLEN) +NAN_BOXED(11573,32,FLEN) +NAN_BOXED(15450,32,FLEN) +NAN_BOXED(15373,32,FLEN) +NAN_BOXED(11709,32,FLEN) +NAN_BOXED(15457,32,FLEN) +NAN_BOXED(15386,32,FLEN) +NAN_BOXED(11519,32,FLEN) +NAN_BOXED(15450,32,FLEN) +NAN_BOXED(15442,32,FLEN) +NAN_BOXED(9495,32,FLEN) +NAN_BOXED(15398,32,FLEN) +NAN_BOXED(15373,32,FLEN) +NAN_BOXED(42603,16,FLEN) +NAN_BOXED(15366,32,FLEN) +NAN_BOXED(15436,32,FLEN) +NAN_BOXED(43115,16,FLEN) +NAN_BOXED(15386,32,FLEN) +test_dataset_2: +NAN_BOXED(15444,16,FLEN) +NAN_BOXED(44205,16,FLEN) +NAN_BOXED(15407,16,FLEN) +NAN_BOXED(15423,16,FLEN) +NAN_BOXED(45772,16,FLEN) +NAN_BOXED(15385,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(46701,16,FLEN) +NAN_BOXED(15434,16,FLEN) +NAN_BOXED(15443,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(15450,16,FLEN) +NAN_BOXED(15425,16,FLEN) +NAN_BOXED(16267,16,FLEN) +NAN_BOXED(15364,16,FLEN) +NAN_BOXED(15442,16,FLEN) +NAN_BOXED(16279,16,FLEN) +NAN_BOXED(15407,16,FLEN) +NAN_BOXED(15392,16,FLEN) +NAN_BOXED(16394,16,FLEN) +NAN_BOXED(15438,16,FLEN) +NAN_BOXED(15416,16,FLEN) +NAN_BOXED(16329,16,FLEN) +NAN_BOXED(15399,16,FLEN) +NAN_BOXED(15406,16,FLEN) +NAN_BOXED(16391,16,FLEN) +NAN_BOXED(15436,16,FLEN) +NAN_BOXED(15376,16,FLEN) +NAN_BOXED(16405,16,FLEN) +NAN_BOXED(15372,16,FLEN) +NAN_BOXED(15425,16,FLEN) +NAN_BOXED(16423,16,FLEN) +NAN_BOXED(15447,16,FLEN) +NAN_BOXED(15428,16,FLEN) +NAN_BOXED(16452,16,FLEN) +NAN_BOXED(15386,16,FLEN) +NAN_BOXED(15375,16,FLEN) +NAN_BOXED(16659,16,FLEN) +NAN_BOXED(15438,16,FLEN) +NAN_BOXED(85,16,FLEN) +NAN_BOXED(13926,16,FLEN) +NAN_BOXED(35,16,FLEN) +NAN_BOXED(40,16,FLEN) +NAN_BOXED(16512,16,FLEN) +NAN_BOXED(93,16,FLEN) +NAN_BOXED(26,16,FLEN) +NAN_BOXED(16068,16,FLEN) +NAN_BOXED(49,16,FLEN) +NAN_BOXED(62,16,FLEN) +NAN_BOXED(13609,16,FLEN) +NAN_BOXED(29,16,FLEN) +NAN_BOXED(18,16,FLEN) +NAN_BOXED(17066,16,FLEN) +NAN_BOXED(77,16,FLEN) +NAN_BOXED(27,16,FLEN) +NAN_BOXED(16440,16,FLEN) +NAN_BOXED(90,16,FLEN) +NAN_BOXED(67,16,FLEN) +NAN_BOXED(48005,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(25,16,FLEN) +NAN_BOXED(50247,16,FLEN) +NAN_BOXED(22,16,FLEN) +NAN_BOXED(3,16,FLEN) +NAN_BOXED(54080,16,FLEN) +NAN_BOXED(83,16,FLEN) +NAN_BOXED(43,16,FLEN) +NAN_BOXED(51488,16,FLEN) +NAN_BOXED(72,16,FLEN) +NAN_BOXED(86,16,FLEN) +NAN_BOXED(15241,16,FLEN) +NAN_BOXED(80,16,FLEN) +NAN_BOXED(80,16,FLEN) +NAN_BOXED(14412,16,FLEN) +NAN_BOXED(40,16,FLEN) +NAN_BOXED(48,16,FLEN) +NAN_BOXED(15488,16,FLEN) +NAN_BOXED(49,16,FLEN) +NAN_BOXED(68,16,FLEN) +NAN_BOXED(15088,16,FLEN) +NAN_BOXED(50,16,FLEN) +NAN_BOXED(38,16,FLEN) +NAN_BOXED(15144,16,FLEN) +NAN_BOXED(17,16,FLEN) +NAN_BOXED(87,16,FLEN) +NAN_BOXED(15465,16,FLEN) +NAN_BOXED(63,16,FLEN) +NAN_BOXED(7,16,FLEN) +NAN_BOXED(19035,16,FLEN) +NAN_BOXED(24,16,FLEN) +NAN_BOXED(55,16,FLEN) +NAN_BOXED(17277,16,FLEN) +NAN_BOXED(77,16,FLEN) +NAN_BOXED(96,16,FLEN) +NAN_BOXED(17002,16,FLEN) +NAN_BOXED(51,16,FLEN) +NAN_BOXED(13,16,FLEN) +NAN_BOXED(20859,16,FLEN) +NAN_BOXED(57,16,FLEN) +NAN_BOXED(32,16,FLEN) +NAN_BOXED(53220,16,FLEN) +NAN_BOXED(12,16,FLEN) +NAN_BOXED(78,16,FLEN) +NAN_BOXED(51710,16,FLEN) +NAN_BOXED(86,16,FLEN) +NAN_BOXED(58,16,FLEN) +NAN_BOXED(52260,16,FLEN) +NAN_BOXED(58,16,FLEN) +NAN_BOXED(49,16,FLEN) +NAN_BOXED(52512,16,FLEN) +NAN_BOXED(10,16,FLEN) +NAN_BOXED(67,16,FLEN) +NAN_BOXED(51994,16,FLEN) +NAN_BOXED(55,16,FLEN) +NAN_BOXED(61,16,FLEN) +NAN_BOXED(52173,16,FLEN) +NAN_BOXED(39,16,FLEN) +NAN_BOXED(91,16,FLEN) +NAN_BOXED(51450,16,FLEN) +NAN_BOXED(53,16,FLEN) +NAN_BOXED(11,16,FLEN) +NAN_BOXED(54513,16,FLEN) +NAN_BOXED(25,16,FLEN) +NAN_BOXED(96,16,FLEN) +NAN_BOXED(50962,16,FLEN) +NAN_BOXED(88,16,FLEN) +NAN_BOXED(35,16,FLEN) +NAN_BOXED(51832,16,FLEN) +NAN_BOXED(58,16,FLEN) +NAN_BOXED(63,16,FLEN) +NAN_BOXED(19564,16,FLEN) +NAN_BOXED(93,16,FLEN) +NAN_BOXED(23,16,FLEN) +NAN_BOXED(20880,16,FLEN) +NAN_BOXED(3,16,FLEN) +NAN_BOXED(3,16,FLEN) +NAN_BOXED(23978,16,FLEN) +NAN_BOXED(69,16,FLEN) +NAN_BOXED(16,16,FLEN) +NAN_BOXED(21528,16,FLEN) +NAN_BOXED(33,16,FLEN) +NAN_BOXED(76,16,FLEN) +NAN_BOXED(19183,16,FLEN) +NAN_BOXED(47,16,FLEN) +NAN_BOXED(25,16,FLEN) +NAN_BOXED(20766,16,FLEN) +NAN_BOXED(33,16,FLEN) +NAN_BOXED(65,16,FLEN) +NAN_BOXED(19410,16,FLEN) +NAN_BOXED(58,16,FLEN) +NAN_BOXED(43,16,FLEN) +NAN_BOXED(19863,16,FLEN) +NAN_BOXED(67,16,FLEN) +NAN_BOXED(33,16,FLEN) +NAN_BOXED(20022,16,FLEN) +NAN_BOXED(53,16,FLEN) +NAN_BOXED(54,16,FLEN) +NAN_BOXED(18806,16,FLEN) +NAN_BOXED(79,16,FLEN) +NAN_BOXED(1087,16,FLEN) +NAN_BOXED(10240,16,FLEN) +NAN_BOXED(1059,16,FLEN) +NAN_BOXED(1102,16,FLEN) +NAN_BOXED(10970,16,FLEN) +NAN_BOXED(1085,16,FLEN) +NAN_BOXED(1109,16,FLEN) +NAN_BOXED(10929,16,FLEN) +NAN_BOXED(1086,16,FLEN) +NAN_BOXED(1087,16,FLEN) +NAN_BOXED(8494,16,FLEN) +NAN_BOXED(1043,16,FLEN) +NAN_BOXED(1117,16,FLEN) +NAN_BOXED(10128,16,FLEN) +NAN_BOXED(1073,16,FLEN) +NAN_BOXED(1088,16,FLEN) +NAN_BOXED(8071,16,FLEN) +NAN_BOXED(1064,16,FLEN) +NAN_BOXED(1106,16,FLEN) +NAN_BOXED(39784,16,FLEN) +NAN_BOXED(1084,16,FLEN) +NAN_BOXED(1066,16,FLEN) +NAN_BOXED(44252,16,FLEN) +NAN_BOXED(1071,16,FLEN) +NAN_BOXED(1109,16,FLEN) +NAN_BOXED(45767,16,FLEN) +NAN_BOXED(1045,16,FLEN) +NAN_BOXED(1104,16,FLEN) +NAN_BOXED(46773,16,FLEN) +NAN_BOXED(1073,16,FLEN) +NAN_BOXED(1113,16,FLEN) +NAN_BOXED(16292,16,FLEN) +NAN_BOXED(1102,16,FLEN) +NAN_BOXED(1059,16,FLEN) +NAN_BOXED(16357,16,FLEN) +NAN_BOXED(1065,16,FLEN) +NAN_BOXED(1107,16,FLEN) +NAN_BOXED(16281,16,FLEN) +NAN_BOXED(1075,16,FLEN) +NAN_BOXED(1087,16,FLEN) +NAN_BOXED(16361,16,FLEN) +NAN_BOXED(1118,16,FLEN) +NAN_BOXED(1045,16,FLEN) +NAN_BOXED(16389,16,FLEN) +NAN_BOXED(1062,16,FLEN) +NAN_BOXED(1096,16,FLEN) +NAN_BOXED(16280,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(1104,16,FLEN) +NAN_BOXED(16348,16,FLEN) +NAN_BOXED(1082,16,FLEN) +NAN_BOXED(1032,16,FLEN) +NAN_BOXED(16451,16,FLEN) +NAN_BOXED(1048,16,FLEN) +NAN_BOXED(1028,16,FLEN) +NAN_BOXED(16546,16,FLEN) +NAN_BOXED(1103,16,FLEN) +NAN_BOXED(1097,16,FLEN) +NAN_BOXED(16561,16,FLEN) +NAN_BOXED(1039,16,FLEN) +NAN_BOXED(30808,16,FLEN) +NAN_BOXED(47792,16,FLEN) +NAN_BOXED(30812,16,FLEN) +NAN_BOXED(30768,16,FLEN) +NAN_BOXED(47940,16,FLEN) +NAN_BOXED(30767,16,FLEN) +NAN_BOXED(30784,16,FLEN) +NAN_BOXED(47855,16,FLEN) +NAN_BOXED(30796,16,FLEN) +NAN_BOXED(30728,16,FLEN) +NAN_BOXED(48044,16,FLEN) +NAN_BOXED(30745,16,FLEN) +NAN_BOXED(30740,16,FLEN) +NAN_BOXED(47986,16,FLEN) +NAN_BOXED(30755,16,FLEN) +NAN_BOXED(30799,16,FLEN) +NAN_BOXED(47916,16,FLEN) +NAN_BOXED(30722,16,FLEN) +NAN_BOXED(30775,16,FLEN) +NAN_BOXED(47771,16,FLEN) +NAN_BOXED(30788,16,FLEN) +NAN_BOXED(30783,16,FLEN) +NAN_BOXED(47747,16,FLEN) +NAN_BOXED(30730,16,FLEN) +NAN_BOXED(30781,16,FLEN) +NAN_BOXED(47471,16,FLEN) +NAN_BOXED(30750,16,FLEN) +NAN_BOXED(30733,16,FLEN) +NAN_BOXED(46884,16,FLEN) +NAN_BOXED(30768,16,FLEN) +NAN_BOXED(30767,16,FLEN) +NAN_BOXED(16836,16,FLEN) +NAN_BOXED(30739,16,FLEN) +NAN_BOXED(30808,16,FLEN) +NAN_BOXED(16810,16,FLEN) +NAN_BOXED(30801,16,FLEN) +NAN_BOXED(30752,16,FLEN) +NAN_BOXED(16884,16,FLEN) +NAN_BOXED(30798,16,FLEN) +NAN_BOXED(30761,16,FLEN) +NAN_BOXED(16841,16,FLEN) +NAN_BOXED(30739,16,FLEN) +NAN_BOXED(30725,16,FLEN) +NAN_BOXED(16920,16,FLEN) +NAN_BOXED(30801,16,FLEN) +NAN_BOXED(30806,16,FLEN) +NAN_BOXED(16767,16,FLEN) +NAN_BOXED(30733,16,FLEN) +NAN_BOXED(30812,16,FLEN) +NAN_BOXED(16745,16,FLEN) +NAN_BOXED(30734,16,FLEN) +NAN_BOXED(30726,16,FLEN) +NAN_BOXED(16864,16,FLEN) +NAN_BOXED(30803,16,FLEN) +NAN_BOXED(30782,16,FLEN) +NAN_BOXED(16715,16,FLEN) +NAN_BOXED(30780,16,FLEN) +NAN_BOXED(30813,16,FLEN) +NAN_BOXED(16537,16,FLEN) +NAN_BOXED(30729,16,FLEN) +NAN_BOXED(74,16,FLEN) +NAN_BOXED(12370,16,FLEN) +NAN_BOXED(11,16,FLEN) +NAN_BOXED(63,16,FLEN) +NAN_BOXED(15896,16,FLEN) +NAN_BOXED(98,16,FLEN) +NAN_BOXED(85,16,FLEN) +NAN_BOXED(14757,16,FLEN) +NAN_BOXED(76,16,FLEN) +NAN_BOXED(61,16,FLEN) +NAN_BOXED(15443,16,FLEN) +NAN_BOXED(98,16,FLEN) +NAN_BOXED(95,16,FLEN) +NAN_BOXED(45411,16,FLEN) +NAN_BOXED(48,16,FLEN) +NAN_BOXED(41,16,FLEN) +NAN_BOXED(47528,16,FLEN) +NAN_BOXED(99,16,FLEN) +NAN_BOXED(63,16,FLEN) +NAN_BOXED(51126,16,FLEN) +NAN_BOXED(26,16,FLEN) +NAN_BOXED(69,16,FLEN) +NAN_BOXED(15404,16,FLEN) +NAN_BOXED(70,16,FLEN) +NAN_BOXED(85,16,FLEN) +NAN_BOXED(16058,16,FLEN) +NAN_BOXED(79,16,FLEN) +NAN_BOXED(88,16,FLEN) +NAN_BOXED(15965,16,FLEN) +NAN_BOXED(12,16,FLEN) +NAN_BOXED(15426,16,FLEN) +NAN_BOXED(46701,16,FLEN) +NAN_BOXED(15434,16,FLEN) +NAN_BOXED(15443,16,FLEN) +NAN_BOXED(16314,16,FLEN) +NAN_BOXED(15450,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 36*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_0: + .fill 228*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fnmadd_b3-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fnmadd_b3-01.S new file mode 100644 index 000000000..b60de5af0 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fnmadd_b3-01.S @@ -0,0 +1,11466 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 06:03:37 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fnmadd.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fnmadd.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fnmadd_b3 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fnmadd_b3) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x7,test_dataset_0) +RVTEST_SIGBASE(x5,signature_x5_1) + +inst_0: +// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==x2, rs2==x21, rs3==x2, rd==x1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x257 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x024 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x292 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x2; op2:x21; op3:x2; dest:x1; op1val:0x7a57; op2val:0x3c24; +op3val:0x7a57; valaddr_reg:x7; val_offset:0*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x1, x2, x21, x2, dyn, 0, 0, x7, 0*FLEN/8, x11, x5, x6) + +inst_1: +// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==x13, rs2==x8, rs3==x8, rd==x12,fs1 == 0 and fe1 == 0x1e and fm1 == 0x257 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x024 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x292 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x13; op2:x8; op3:x8; dest:x12; op1val:0x7a57; op2val:0x3c24; +op3val:0x3c24; valaddr_reg:x7; val_offset:3*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x12, x13, x8, x8, dyn, 32, 0, x7, 3*FLEN/8, x11, x5, x6) + +inst_2: +// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==x28, rs2==x20, rs3==x13, rd==x18,fs1 == 0 and fe1 == 0x1e and fm1 == 0x257 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x024 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x292 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x28; op2:x20; op3:x13; dest:x18; op1val:0x7a57; op2val:0x3c24; +op3val:0x7a92; valaddr_reg:x7; val_offset:6*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x18, x28, x20, x13, dyn, 64, 0, x7, 6*FLEN/8, x11, x5, x6) + +inst_3: +// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==x19, rs2==x27, rs3==x18, rd==x27,fs1 == 0 and fe1 == 0x1e and fm1 == 0x257 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x024 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x292 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x19; op2:x27; op3:x18; dest:x27; op1val:0x7a57; op2val:0x3c24; +op3val:0x7a92; valaddr_reg:x7; val_offset:9*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x27, x19, x27, x18, dyn, 96, 0, x7, 9*FLEN/8, x11, x5, x6) + +inst_4: +// rs1 == rd == rs3 != rs2, rs1==x15, rs2==x29, rs3==x15, rd==x15,fs1 == 0 and fe1 == 0x1e and fm1 == 0x257 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x024 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x292 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x15; op2:x29; op3:x15; dest:x15; op1val:0x7a57; op2val:0x3c24; +op3val:0x7a57; valaddr_reg:x7; val_offset:12*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x15, x15, x29, x15, dyn, 128, 0, x7, 12*FLEN/8, x11, x5, x6) + +inst_5: +// rs1 == rs2 == rs3 != rd, rs1==x22, rs2==x22, rs3==x22, rd==x3,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3c1 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x050 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x02f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x22; op2:x22; op3:x22; dest:x3; op1val:0x77c1; op2val:0x77c1; +op3val:0x77c1; valaddr_reg:x7; val_offset:15*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x3, x22, x22, x22, dyn, 0, 0, x7, 15*FLEN/8, x11, x5, x6) + +inst_6: +// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==x9, rs2==x9, rs3==x12, rd==x19,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3c1 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x050 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x02f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x9; op2:x9; op3:x12; dest:x19; op1val:0x77c1; op2val:0x77c1; +op3val:0x742f; valaddr_reg:x7; val_offset:18*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x19, x9, x9, x12, dyn, 32, 0, x7, 18*FLEN/8, x11, x5, x6) + +inst_7: +// rd == rs2 == rs3 != rs1, rs1==x26, rs2==x4, rs3==x4, rd==x4,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3c1 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x050 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x02f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x26; op2:x4; op3:x4; dest:x4; op1val:0x77c1; op2val:0x3850; +op3val:0x3850; valaddr_reg:x7; val_offset:21*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x4, x26, x4, x4, dyn, 64, 0, x7, 21*FLEN/8, x11, x5, x6) + +inst_8: +// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==x17, rs2==x1, rs3==x31, rd==x17,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3c1 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x050 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x02f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x17; op2:x1; op3:x31; dest:x17; op1val:0x77c1; op2val:0x3850; +op3val:0x742f; valaddr_reg:x7; val_offset:24*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x17, x17, x1, x31, dyn, 96, 0, x7, 24*FLEN/8, x11, x5, x6) + +inst_9: +// rs1 == rs2 == rs3 == rd, rs1==x10, rs2==x10, rs3==x10, rd==x10,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3c1 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x050 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x02f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x10; op2:x10; op3:x10; dest:x10; op1val:0x77c1; op2val:0x77c1; +op3val:0x77c1; valaddr_reg:x7; val_offset:27*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x10, x10, x10, x10, dyn, 128, 0, x7, 27*FLEN/8, x11, x5, x6) + +inst_10: +// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==x27, rs2==x24, rs3==x28, rd==x28,fs1 == 0 and fe1 == 0x13 and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x18b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x27; op2:x24; op3:x28; dest:x28; op1val:0x4fa5; op2val:0x658b; +op3val:0x794c; valaddr_reg:x7; val_offset:30*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x28, x27, x24, x28, dyn, 0, 0, x7, 30*FLEN/8, x11, x5, x6) + +inst_11: +// rs1 == rs2 == rd != rs3, rs1==x16, rs2==x16, rs3==x21, rd==x16,fs1 == 0 and fe1 == 0x13 and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x18b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x16; op2:x16; op3:x21; dest:x16; op1val:0x4fa5; op2val:0x4fa5; +op3val:0x794c; valaddr_reg:x7; val_offset:33*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x16, x16, x16, x21, dyn, 32, 0, x7, 33*FLEN/8, x11, x5, x6) +RVTEST_VALBASEUPD(x16,test_dataset_1) + +inst_12: +// rs1==x24, rs2==x11, rs3==x1, rd==x21,fs1 == 0 and fe1 == 0x13 and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x18b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x24; op2:x11; op3:x1; dest:x21; op1val:0x4fa5; op2val:0x658b; +op3val:0x794c; valaddr_reg:x16; val_offset:0*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x21, x24, x11, x1, dyn, 64, 0, x16, 0*FLEN/8, x17, x5, x6) + +inst_13: +// rs1==x21, rs2==x30, rs3==x24, rd==x26,fs1 == 0 and fe1 == 0x13 and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x18b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x21; op2:x30; op3:x24; dest:x26; op1val:0x4fa5; op2val:0x658b; +op3val:0x794c; valaddr_reg:x16; val_offset:3*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x26, x21, x30, x24, dyn, 96, 0, x16, 3*FLEN/8, x17, x5, x6) + +inst_14: +// rs1==x12, rs2==x25, rs3==x0, rd==x22,fs1 == 0 and fe1 == 0x13 and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x18b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x12; op2:x25; op3:x0; dest:x22; op1val:0x4fa5; op2val:0x658b; +op3val:0x0; valaddr_reg:x16; val_offset:6*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x22, x12, x25, x0, dyn, 128, 0, x16, 6*FLEN/8, x17, x5, x1) +RVTEST_SIGBASE(x10,signature_x10_0) + +inst_15: +// rs1==x7, rs2==x15, rs3==x16, rd==x25,fs1 == 0 and fe1 == 0x1d and fm1 == 0x385 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x276 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x213 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x7; op2:x15; op3:x16; dest:x25; op1val:0x7785; op2val:0x3e76; +op3val:0x7a13; valaddr_reg:x16; val_offset:9*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x25, x7, x15, x16, dyn, 0, 0, x16, 9*FLEN/8, x17, x10, x1) + +inst_16: +// rs1==x14, rs2==x13, rs3==x26, rd==x2,fs1 == 0 and fe1 == 0x1d and fm1 == 0x385 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x276 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x213 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x14; op2:x13; op3:x26; dest:x2; op1val:0x7785; op2val:0x3e76; +op3val:0x7a13; valaddr_reg:x16; val_offset:12*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x2, x14, x13, x26, dyn, 32, 0, x16, 12*FLEN/8, x17, x10, x1) + +inst_17: +// rs1==x31, rs2==x18, rs3==x3, rd==x23,fs1 == 0 and fe1 == 0x1d and fm1 == 0x385 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x276 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x213 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x31; op2:x18; op3:x3; dest:x23; op1val:0x7785; op2val:0x3e76; +op3val:0x7a13; valaddr_reg:x16; val_offset:15*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x23, x31, x18, x3, dyn, 64, 0, x16, 15*FLEN/8, x17, x10, x1) + +inst_18: +// rs1==x5, rs2==x26, rs3==x20, rd==x8,fs1 == 0 and fe1 == 0x1d and fm1 == 0x385 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x276 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x213 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x5; op2:x26; op3:x20; dest:x8; op1val:0x7785; op2val:0x3e76; +op3val:0x7a13; valaddr_reg:x16; val_offset:18*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x8, x5, x26, x20, dyn, 96, 0, x16, 18*FLEN/8, x17, x10, x1) + +inst_19: +// rs1==x8, rs2==x7, rs3==x25, rd==x9,fs1 == 0 and fe1 == 0x1d and fm1 == 0x385 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x276 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x213 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x8; op2:x7; op3:x25; dest:x9; op1val:0x7785; op2val:0x3e76; +op3val:0x7a13; valaddr_reg:x16; val_offset:21*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x9, x8, x7, x25, dyn, 128, 0, x16, 21*FLEN/8, x17, x10, x1) + +inst_20: +// rs1==x6, rs2==x2, rs3==x19, rd==x14,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1f7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x020 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x228 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x6; op2:x2; op3:x19; dest:x14; op1val:0x75f7; op2val:0x4020; +op3val:0x7a28; valaddr_reg:x16; val_offset:24*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x14, x6, x2, x19, dyn, 0, 0, x16, 24*FLEN/8, x17, x10, x1) + +inst_21: +// rs1==x18, rs2==x3, rs3==x5, rd==x24,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1f7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x020 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x228 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x18; op2:x3; op3:x5; dest:x24; op1val:0x75f7; op2val:0x4020; +op3val:0x7a28; valaddr_reg:x16; val_offset:27*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x24, x18, x3, x5, dyn, 32, 0, x16, 27*FLEN/8, x17, x10, x1) + +inst_22: +// rs1==x4, rs2==x5, rs3==x11, rd==x0,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1f7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x020 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x228 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x4; op2:x5; op3:x11; dest:x0; op1val:0x75f7; op2val:0x4020; +op3val:0x7a28; valaddr_reg:x16; val_offset:30*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x0, x4, x5, x11, dyn, 64, 0, x16, 30*FLEN/8, x17, x10, x1) +RVTEST_VALBASEUPD(x4,test_dataset_2) + +inst_23: +// rs1==x29, rs2==x31, rs3==x17, rd==x11,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1f7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x020 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x228 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x29; op2:x31; op3:x17; dest:x11; op1val:0x75f7; op2val:0x4020; +op3val:0x7a28; valaddr_reg:x4; val_offset:0*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x11, x29, x31, x17, dyn, 96, 0, x4, 0*FLEN/8, x8, x10, x1) + +inst_24: +// rs1==x3, rs2==x28, rs3==x23, rd==x30,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1f7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x020 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x228 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x3; op2:x28; op3:x23; dest:x30; op1val:0x75f7; op2val:0x4020; +op3val:0x7a28; valaddr_reg:x4; val_offset:3*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x30, x3, x28, x23, dyn, 128, 0, x4, 3*FLEN/8, x8, x10, x1) + +inst_25: +// rs1==x11, rs2==x0, rs3==x14, rd==x5,fs1 == 0 and fe1 == 0x1d and fm1 == 0x05c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x269 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x11; op2:x0; op3:x14; dest:x5; op1val:0x745c; op2val:0x0; +op3val:0x7a69; valaddr_reg:x4; val_offset:6*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x5, x11, x0, x14, dyn, 0, 0, x4, 6*FLEN/8, x8, x10, x1) + +inst_26: +// rs1==x30, rs2==x17, rs3==x9, rd==x7,fs1 == 0 and fe1 == 0x1d and fm1 == 0x05c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x269 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x17; op3:x9; dest:x7; op1val:0x745c; op2val:0x41e1; +op3val:0x7a69; valaddr_reg:x4; val_offset:9*FLEN/8; rmval:dyn; +testreg:x1; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x7, x30, x17, x9, dyn, 32, 0, x4, 9*FLEN/8, x8, x10, x1) + +inst_27: +// rs1==x1, rs2==x12, rs3==x30, rd==x20,fs1 == 0 and fe1 == 0x1d and fm1 == 0x05c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x269 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x1; op2:x12; op3:x30; dest:x20; op1val:0x745c; op2val:0x41e1; +op3val:0x7a69; valaddr_reg:x4; val_offset:12*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x20, x1, x12, x30, dyn, 64, 0, x4, 12*FLEN/8, x8, x10, x3) +RVTEST_SIGBASE(x2,signature_x2_0) + +inst_28: +// rs1==x20, rs2==x23, rs3==x6, rd==x29,fs1 == 0 and fe1 == 0x1d and fm1 == 0x05c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x269 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x20; op2:x23; op3:x6; dest:x29; op1val:0x745c; op2val:0x41e1; +op3val:0x7a69; valaddr_reg:x4; val_offset:15*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x29, x20, x23, x6, dyn, 96, 0, x4, 15*FLEN/8, x8, x2, x3) + +inst_29: +// rs1==x25, rs2==x14, rs3==x27, rd==x31,fs1 == 0 and fe1 == 0x1d and fm1 == 0x05c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x269 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x25; op2:x14; op3:x27; dest:x31; op1val:0x745c; op2val:0x41e1; +op3val:0x7a69; valaddr_reg:x4; val_offset:18*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x25, x14, x27, dyn, 128, 0, x4, 18*FLEN/8, x8, x2, x3) + +inst_30: +// rs1==x0, rs2==x19, rs3==x7, rd==x13,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x089 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x29e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x0; op2:x19; op3:x7; dest:x13; op1val:0x0; op2val:0x3889; +op3val:0x769e; valaddr_reg:x4; val_offset:21*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x13, x0, x19, x7, dyn, 0, 0, x4, 21*FLEN/8, x8, x2, x3) + +inst_31: +// rs1==x23,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x089 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x29e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x23; op2:x28; op3:x10; dest:x16; op1val:0x79d5; op2val:0x3889; +op3val:0x769e; valaddr_reg:x4; val_offset:24*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x16, x23, x28, x10, dyn, 32, 0, x4, 24*FLEN/8, x8, x2, x3) + +inst_32: +// rs2==x6,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x089 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x29e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x9; op2:x6; op3:x18; dest:x23; op1val:0x79d5; op2val:0x3889; +op3val:0x769e; valaddr_reg:x4; val_offset:27*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x23, x9, x6, x18, dyn, 64, 0, x4, 27*FLEN/8, x8, x2, x3) + +inst_33: +// rs3==x29,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x089 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x29e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x18; op2:x19; op3:x29; dest:x1; op1val:0x79d5; op2val:0x3889; +op3val:0x769e; valaddr_reg:x4; val_offset:30*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x1, x18, x19, x29, dyn, 96, 0, x4, 30*FLEN/8, x8, x2, x3) + +inst_34: +// rd==x6,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x089 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x29e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x22; op2:x24; op3:x3; dest:x6; op1val:0x79d5; op2val:0x3889; +op3val:0x769e; valaddr_reg:x4; val_offset:33*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x6, x22, x24, x3, dyn, 128, 0, x4, 33*FLEN/8, x8, x2, x3) +RVTEST_VALBASEUPD(x1,test_dataset_3) + +inst_35: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x111 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x174 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x784d; op2val:0x3d11; +op3val:0x7974; valaddr_reg:x1; val_offset:0*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 0*FLEN/8, x4, x2, x3) + +inst_36: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x111 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x174 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x784d; op2val:0x3d11; +op3val:0x7974; valaddr_reg:x1; val_offset:3*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3*FLEN/8, x4, x2, x3) + +inst_37: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x111 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x174 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x784d; op2val:0x3d11; +op3val:0x7974; valaddr_reg:x1; val_offset:6*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 6*FLEN/8, x4, x2, x3) + +inst_38: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x111 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x174 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x784d; op2val:0x3d11; +op3val:0x7974; valaddr_reg:x1; val_offset:9*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 9*FLEN/8, x4, x2, x3) + +inst_39: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x111 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x174 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x784d; op2val:0x3d11; +op3val:0x7974; valaddr_reg:x1; val_offset:12*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 12*FLEN/8, x4, x2, x3) + +inst_40: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x22c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1bc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x06d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x722c; op2val:0x41bc; +op3val:0x786d; valaddr_reg:x1; val_offset:15*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 15*FLEN/8, x4, x2, x3) + +inst_41: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x22c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1bc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x06d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x722c; op2val:0x41bc; +op3val:0x786d; valaddr_reg:x1; val_offset:18*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 18*FLEN/8, x4, x2, x3) + +inst_42: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x22c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1bc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x06d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x722c; op2val:0x41bc; +op3val:0x786d; valaddr_reg:x1; val_offset:21*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 21*FLEN/8, x4, x2, x3) + +inst_43: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x22c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1bc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x06d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x722c; op2val:0x41bc; +op3val:0x786d; valaddr_reg:x1; val_offset:24*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 24*FLEN/8, x4, x2, x3) + +inst_44: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x22c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1bc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x06d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x722c; op2val:0x41bc; +op3val:0x786d; valaddr_reg:x1; val_offset:27*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 27*FLEN/8, x4, x2, x3) + +inst_45: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x270 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x146 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a70; op2val:0x3546; +op3val:0x743f; valaddr_reg:x1; val_offset:30*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 30*FLEN/8, x4, x2, x3) + +inst_46: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x270 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x146 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x03f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a70; op2val:0x3546; +op3val:0x743f; valaddr_reg:x1; val_offset:33*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 33*FLEN/8, x4, x2, x3) + +inst_47: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x270 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x146 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x03f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a70; op2val:0x3546; +op3val:0x743f; valaddr_reg:x1; val_offset:36*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 36*FLEN/8, x4, x2, x3) + +inst_48: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x270 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x146 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x03f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a70; op2val:0x3546; +op3val:0x743f; valaddr_reg:x1; val_offset:39*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 39*FLEN/8, x4, x2, x3) + +inst_49: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x270 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x146 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x03f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a70; op2val:0x3546; +op3val:0x743f; valaddr_reg:x1; val_offset:42*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 42*FLEN/8, x4, x2, x3) + +inst_50: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x17b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a6c; op2val:0x3ad4; +op3val:0x797b; valaddr_reg:x1; val_offset:45*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 45*FLEN/8, x4, x2, x3) + +inst_51: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x17b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a6c; op2val:0x3ad4; +op3val:0x797b; valaddr_reg:x1; val_offset:48*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 48*FLEN/8, x4, x2, x3) + +inst_52: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x17b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a6c; op2val:0x3ad4; +op3val:0x797b; valaddr_reg:x1; val_offset:51*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 51*FLEN/8, x4, x2, x3) + +inst_53: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x17b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a6c; op2val:0x3ad4; +op3val:0x797b; valaddr_reg:x1; val_offset:54*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 54*FLEN/8, x4, x2, x3) + +inst_54: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x17b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a6c; op2val:0x3ad4; +op3val:0x797b; valaddr_reg:x1; val_offset:57*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 57*FLEN/8, x4, x2, x3) + +inst_55: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x25c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x15d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ac0; op2val:0x365c; +op3val:0x755d; valaddr_reg:x1; val_offset:60*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 60*FLEN/8, x4, x2, x3) + +inst_56: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x25c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x15d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ac0; op2val:0x365c; +op3val:0x755d; valaddr_reg:x1; val_offset:63*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 63*FLEN/8, x4, x2, x3) + +inst_57: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x25c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x15d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ac0; op2val:0x365c; +op3val:0x755d; valaddr_reg:x1; val_offset:66*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 66*FLEN/8, x4, x2, x3) + +inst_58: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x25c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x15d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ac0; op2val:0x365c; +op3val:0x755d; valaddr_reg:x1; val_offset:69*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 69*FLEN/8, x4, x2, x3) + +inst_59: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x25c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x15d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ac0; op2val:0x365c; +op3val:0x755d; valaddr_reg:x1; val_offset:72*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 72*FLEN/8, x4, x2, x3) + +inst_60: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1f5 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x04b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x266 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6df5; op2val:0x484b; +op3val:0x7a66; valaddr_reg:x1; val_offset:75*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 75*FLEN/8, x4, x2, x3) + +inst_61: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1f5 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x04b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x266 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6df5; op2val:0x484b; +op3val:0x7a66; valaddr_reg:x1; val_offset:78*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 78*FLEN/8, x4, x2, x3) + +inst_62: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1f5 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x04b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x266 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6df5; op2val:0x484b; +op3val:0x7a66; valaddr_reg:x1; val_offset:81*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 81*FLEN/8, x4, x2, x3) + +inst_63: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1f5 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x04b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x266 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6df5; op2val:0x484b; +op3val:0x7a66; valaddr_reg:x1; val_offset:84*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 84*FLEN/8, x4, x2, x3) + +inst_64: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1f5 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x04b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x266 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6df5; op2val:0x484b; +op3val:0x7a66; valaddr_reg:x1; val_offset:87*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 87*FLEN/8, x4, x2, x3) + +inst_65: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x06c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x31e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a6f; op2val:0x386c; +op3val:0x771e; valaddr_reg:x1; val_offset:90*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 90*FLEN/8, x4, x2, x3) + +inst_66: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x06c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x31e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a6f; op2val:0x386c; +op3val:0x771e; valaddr_reg:x1; val_offset:93*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 93*FLEN/8, x4, x2, x3) + +inst_67: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x06c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x31e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a6f; op2val:0x386c; +op3val:0x771e; valaddr_reg:x1; val_offset:96*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 96*FLEN/8, x4, x2, x3) + +inst_68: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x06c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x31e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a6f; op2val:0x386c; +op3val:0x771e; valaddr_reg:x1; val_offset:99*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 99*FLEN/8, x4, x2, x3) + +inst_69: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x06c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x31e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a6f; op2val:0x386c; +op3val:0x771e; valaddr_reg:x1; val_offset:102*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 102*FLEN/8, x4, x2, x3) + +inst_70: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x10 and fm2 == 0x034 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x24e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dff; op2val:0x4034; +op3val:0x724e; valaddr_reg:x1; val_offset:105*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 105*FLEN/8, x4, x2, x3) + +inst_71: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x10 and fm2 == 0x034 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x24e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dff; op2val:0x4034; +op3val:0x724e; valaddr_reg:x1; val_offset:108*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 108*FLEN/8, x4, x2, x3) + +inst_72: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x10 and fm2 == 0x034 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x24e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dff; op2val:0x4034; +op3val:0x724e; valaddr_reg:x1; val_offset:111*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 111*FLEN/8, x4, x2, x3) + +inst_73: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x10 and fm2 == 0x034 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x24e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dff; op2val:0x4034; +op3val:0x724e; valaddr_reg:x1; val_offset:114*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 114*FLEN/8, x4, x2, x3) + +inst_74: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x10 and fm2 == 0x034 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x24e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dff; op2val:0x4034; +op3val:0x724e; valaddr_reg:x1; val_offset:117*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 117*FLEN/8, x4, x2, x3) + +inst_75: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x356 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7913; op2val:0x3756; +op3val:0x74a8; valaddr_reg:x1; val_offset:120*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 120*FLEN/8, x4, x2, x3) + +inst_76: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x356 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7913; op2val:0x3756; +op3val:0x74a8; valaddr_reg:x1; val_offset:123*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 123*FLEN/8, x4, x2, x3) + +inst_77: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x356 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7913; op2val:0x3756; +op3val:0x74a8; valaddr_reg:x1; val_offset:126*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 126*FLEN/8, x4, x2, x3) + +inst_78: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x356 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7913; op2val:0x3756; +op3val:0x74a8; valaddr_reg:x1; val_offset:129*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 129*FLEN/8, x4, x2, x3) + +inst_79: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x356 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7913; op2val:0x3756; +op3val:0x74a8; valaddr_reg:x1; val_offset:132*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 132*FLEN/8, x4, x2, x3) + +inst_80: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x39b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0f3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0b4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b9b; op2val:0x38f3; +op3val:0x78b4; valaddr_reg:x1; val_offset:135*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 135*FLEN/8, x4, x2, x3) + +inst_81: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x39b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0f3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0b4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b9b; op2val:0x38f3; +op3val:0x78b4; valaddr_reg:x1; val_offset:138*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 138*FLEN/8, x4, x2, x3) + +inst_82: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x39b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0f3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0b4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b9b; op2val:0x38f3; +op3val:0x78b4; valaddr_reg:x1; val_offset:141*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 141*FLEN/8, x4, x2, x3) + +inst_83: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x39b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0f3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0b4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b9b; op2val:0x38f3; +op3val:0x78b4; valaddr_reg:x1; val_offset:144*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 144*FLEN/8, x4, x2, x3) + +inst_84: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x39b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0f3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0b4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b9b; op2val:0x38f3; +op3val:0x78b4; valaddr_reg:x1; val_offset:147*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 147*FLEN/8, x4, x2, x3) + +inst_85: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x26c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x286 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x13d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x726c; op2val:0x4286; +op3val:0x793d; valaddr_reg:x1; val_offset:150*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 150*FLEN/8, x4, x2, x3) + +inst_86: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x26c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x286 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x13d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x726c; op2val:0x4286; +op3val:0x793d; valaddr_reg:x1; val_offset:153*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 153*FLEN/8, x4, x2, x3) + +inst_87: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x26c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x286 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x13d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x726c; op2val:0x4286; +op3val:0x793d; valaddr_reg:x1; val_offset:156*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 156*FLEN/8, x4, x2, x3) + +inst_88: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x26c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x286 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x13d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x726c; op2val:0x4286; +op3val:0x793d; valaddr_reg:x1; val_offset:159*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 159*FLEN/8, x4, x2, x3) + +inst_89: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x26c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x286 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x13d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x726c; op2val:0x4286; +op3val:0x793d; valaddr_reg:x1; val_offset:162*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 162*FLEN/8, x4, x2, x3) + +inst_90: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c3 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x12d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x375 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c3; op2val:0x412d; +op3val:0x7b75; valaddr_reg:x1; val_offset:165*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 165*FLEN/8, x4, x2, x3) + +inst_91: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c3 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x12d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x375 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c3; op2val:0x412d; +op3val:0x7b75; valaddr_reg:x1; val_offset:168*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 168*FLEN/8, x4, x2, x3) + +inst_92: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c3 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x12d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x375 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c3; op2val:0x412d; +op3val:0x7b75; valaddr_reg:x1; val_offset:171*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 171*FLEN/8, x4, x2, x3) + +inst_93: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c3 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x12d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x375 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c3; op2val:0x412d; +op3val:0x7b75; valaddr_reg:x1; val_offset:174*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 174*FLEN/8, x4, x2, x3) + +inst_94: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c3 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x12d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x375 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c3; op2val:0x412d; +op3val:0x7b75; valaddr_reg:x1; val_offset:177*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 177*FLEN/8, x4, x2, x3) + +inst_95: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x345 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x086 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x01d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b45; op2val:0x3886; +op3val:0x781d; valaddr_reg:x1; val_offset:180*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 180*FLEN/8, x4, x2, x3) + +inst_96: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x345 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x086 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x01d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b45; op2val:0x3886; +op3val:0x781d; valaddr_reg:x1; val_offset:183*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 183*FLEN/8, x4, x2, x3) + +inst_97: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x345 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x086 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x01d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b45; op2val:0x3886; +op3val:0x781d; valaddr_reg:x1; val_offset:186*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 186*FLEN/8, x4, x2, x3) + +inst_98: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x345 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x086 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x01d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b45; op2val:0x3886; +op3val:0x781d; valaddr_reg:x1; val_offset:189*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 189*FLEN/8, x4, x2, x3) + +inst_99: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x345 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x086 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x01d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b45; op2val:0x3886; +op3val:0x781d; valaddr_reg:x1; val_offset:192*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 192*FLEN/8, x4, x2, x3) + +inst_100: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x127 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x054 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x194 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7927; op2val:0x3c54; +op3val:0x7994; valaddr_reg:x1; val_offset:195*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 195*FLEN/8, x4, x2, x3) + +inst_101: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x127 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x054 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x194 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7927; op2val:0x3c54; +op3val:0x7994; valaddr_reg:x1; val_offset:198*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 198*FLEN/8, x4, x2, x3) + +inst_102: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x127 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x054 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x194 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7927; op2val:0x3c54; +op3val:0x7994; valaddr_reg:x1; val_offset:201*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 201*FLEN/8, x4, x2, x3) + +inst_103: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x127 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x054 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x194 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7927; op2val:0x3c54; +op3val:0x7994; valaddr_reg:x1; val_offset:204*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 204*FLEN/8, x4, x2, x3) + +inst_104: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x127 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x054 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x194 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7927; op2val:0x3c54; +op3val:0x7994; valaddr_reg:x1; val_offset:207*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 207*FLEN/8, x4, x2, x3) + +inst_105: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x270 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0d9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ce and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a70; op2val:0x3cd9; +op3val:0x7bce; valaddr_reg:x1; val_offset:210*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 210*FLEN/8, x4, x2, x3) + +inst_106: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x270 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0d9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ce and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a70; op2val:0x3cd9; +op3val:0x7bce; valaddr_reg:x1; val_offset:213*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 213*FLEN/8, x4, x2, x3) + +inst_107: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x270 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0d9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ce and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a70; op2val:0x3cd9; +op3val:0x7bce; valaddr_reg:x1; val_offset:216*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 216*FLEN/8, x4, x2, x3) + +inst_108: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x270 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0d9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ce and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a70; op2val:0x3cd9; +op3val:0x7bce; valaddr_reg:x1; val_offset:219*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 219*FLEN/8, x4, x2, x3) + +inst_109: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x270 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0d9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ce and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a70; op2val:0x3cd9; +op3val:0x7bce; valaddr_reg:x1; val_offset:222*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 222*FLEN/8, x4, x2, x3) + +inst_110: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x346 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x25a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1c7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6746; op2val:0x4a5a; +op3val:0x75c7; valaddr_reg:x1; val_offset:225*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 225*FLEN/8, x4, x2, x3) + +inst_111: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x346 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x25a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1c7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6746; op2val:0x4a5a; +op3val:0x75c7; valaddr_reg:x1; val_offset:228*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 228*FLEN/8, x4, x2, x3) + +inst_112: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x346 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x25a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1c7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6746; op2val:0x4a5a; +op3val:0x75c7; valaddr_reg:x1; val_offset:231*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 231*FLEN/8, x4, x2, x3) + +inst_113: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x346 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x25a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1c7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6746; op2val:0x4a5a; +op3val:0x75c7; valaddr_reg:x1; val_offset:234*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 234*FLEN/8, x4, x2, x3) + +inst_114: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x346 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x25a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1c7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6746; op2val:0x4a5a; +op3val:0x75c7; valaddr_reg:x1; val_offset:237*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 237*FLEN/8, x4, x2, x3) + +inst_115: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0cf and fs2 == 0 and fe2 == 0x0e and fm2 == 0x00b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0dd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78cf; op2val:0x380b; +op3val:0x74dd; valaddr_reg:x1; val_offset:240*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 240*FLEN/8, x4, x2, x3) + +inst_116: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0cf and fs2 == 0 and fe2 == 0x0e and fm2 == 0x00b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0dd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78cf; op2val:0x380b; +op3val:0x74dd; valaddr_reg:x1; val_offset:243*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 243*FLEN/8, x4, x2, x3) + +inst_117: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0cf and fs2 == 0 and fe2 == 0x0e and fm2 == 0x00b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0dd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78cf; op2val:0x380b; +op3val:0x74dd; valaddr_reg:x1; val_offset:246*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 246*FLEN/8, x4, x2, x3) + +inst_118: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0cf and fs2 == 0 and fe2 == 0x0e and fm2 == 0x00b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0dd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78cf; op2val:0x380b; +op3val:0x74dd; valaddr_reg:x1; val_offset:249*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 249*FLEN/8, x4, x2, x3) + +inst_119: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0cf and fs2 == 0 and fe2 == 0x0e and fm2 == 0x00b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0dd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78cf; op2val:0x380b; +op3val:0x74dd; valaddr_reg:x1; val_offset:252*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 252*FLEN/8, x4, x2, x3) + +inst_120: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b6 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0df and fs3 == 0 and fe3 == 0x1b and fm3 == 0x1bc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78b6; op2val:0x30df; +op3val:0x6dbc; valaddr_reg:x1; val_offset:255*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 255*FLEN/8, x4, x2, x3) + +inst_121: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b6 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0df and fs3 == 0 and fe3 == 0x1b and fm3 == 0x1bc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78b6; op2val:0x30df; +op3val:0x6dbc; valaddr_reg:x1; val_offset:258*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 258*FLEN/8, x4, x2, x3) + +inst_122: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b6 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0df and fs3 == 0 and fe3 == 0x1b and fm3 == 0x1bc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78b6; op2val:0x30df; +op3val:0x6dbc; valaddr_reg:x1; val_offset:261*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 261*FLEN/8, x4, x2, x3) + +inst_123: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b6 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0df and fs3 == 0 and fe3 == 0x1b and fm3 == 0x1bc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78b6; op2val:0x30df; +op3val:0x6dbc; valaddr_reg:x1; val_offset:264*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 264*FLEN/8, x4, x2, x3) + +inst_124: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b6 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0df and fs3 == 0 and fe3 == 0x1b and fm3 == 0x1bc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78b6; op2val:0x30df; +op3val:0x6dbc; valaddr_reg:x1; val_offset:267*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 267*FLEN/8, x4, x2, x3) + +inst_125: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x309 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0c6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x033 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b09; op2val:0x38c6; +op3val:0x7833; valaddr_reg:x1; val_offset:270*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 270*FLEN/8, x4, x2, x3) + +inst_126: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x309 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0c6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x033 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b09; op2val:0x38c6; +op3val:0x7833; valaddr_reg:x1; val_offset:273*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 273*FLEN/8, x4, x2, x3) + +inst_127: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x309 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0c6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x033 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b09; op2val:0x38c6; +op3val:0x7833; valaddr_reg:x1; val_offset:276*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 276*FLEN/8, x4, x2, x3) + +inst_128: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x309 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0c6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x033 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b09; op2val:0x38c6; +op3val:0x7833; valaddr_reg:x1; val_offset:279*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 279*FLEN/8, x4, x2, x3) + +inst_129: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x309 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0c6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x033 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b09; op2val:0x38c6; +op3val:0x7833; valaddr_reg:x1; val_offset:282*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 282*FLEN/8, x4, x2, x3) + +inst_130: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x379 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1ac and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f79; op2val:0x45ac; +op3val:0x794c; valaddr_reg:x1; val_offset:285*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 285*FLEN/8, x4, x2, x3) + +inst_131: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x379 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1ac and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f79; op2val:0x45ac; +op3val:0x794c; valaddr_reg:x1; val_offset:288*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 288*FLEN/8, x4, x2, x3) + +inst_132: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x379 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1ac and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f79; op2val:0x45ac; +op3val:0x794c; valaddr_reg:x1; val_offset:291*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 291*FLEN/8, x4, x2, x3) + +inst_133: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x379 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1ac and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f79; op2val:0x45ac; +op3val:0x794c; valaddr_reg:x1; val_offset:294*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 294*FLEN/8, x4, x2, x3) + +inst_134: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x379 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1ac and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f79; op2val:0x45ac; +op3val:0x794c; valaddr_reg:x1; val_offset:297*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 297*FLEN/8, x4, x2, x3) + +inst_135: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0fe and fs2 == 0 and fe2 == 0x0e and fm2 == 0x106 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x246 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74fe; op2val:0x3906; +op3val:0x7246; valaddr_reg:x1; val_offset:300*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 300*FLEN/8, x4, x2, x3) + +inst_136: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0fe and fs2 == 0 and fe2 == 0x0e and fm2 == 0x106 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x246 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74fe; op2val:0x3906; +op3val:0x7246; valaddr_reg:x1; val_offset:303*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 303*FLEN/8, x4, x2, x3) + +inst_137: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0fe and fs2 == 0 and fe2 == 0x0e and fm2 == 0x106 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x246 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74fe; op2val:0x3906; +op3val:0x7246; valaddr_reg:x1; val_offset:306*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 306*FLEN/8, x4, x2, x3) + +inst_138: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0fe and fs2 == 0 and fe2 == 0x0e and fm2 == 0x106 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x246 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74fe; op2val:0x3906; +op3val:0x7246; valaddr_reg:x1; val_offset:309*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 309*FLEN/8, x4, x2, x3) + +inst_139: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0fe and fs2 == 0 and fe2 == 0x0e and fm2 == 0x106 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x246 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74fe; op2val:0x3906; +op3val:0x7246; valaddr_reg:x1; val_offset:312*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 312*FLEN/8, x4, x2, x3) + +inst_140: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3bc and fs2 == 0 and fe2 == 0x0d and fm2 == 0x091 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x06a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77bc; op2val:0x3491; +op3val:0x706a; valaddr_reg:x1; val_offset:315*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 315*FLEN/8, x4, x2, x3) + +inst_141: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3bc and fs2 == 0 and fe2 == 0x0d and fm2 == 0x091 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x06a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77bc; op2val:0x3491; +op3val:0x706a; valaddr_reg:x1; val_offset:318*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 318*FLEN/8, x4, x2, x3) + +inst_142: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3bc and fs2 == 0 and fe2 == 0x0d and fm2 == 0x091 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x06a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77bc; op2val:0x3491; +op3val:0x706a; valaddr_reg:x1; val_offset:321*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 321*FLEN/8, x4, x2, x3) + +inst_143: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3bc and fs2 == 0 and fe2 == 0x0d and fm2 == 0x091 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x06a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77bc; op2val:0x3491; +op3val:0x706a; valaddr_reg:x1; val_offset:324*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 324*FLEN/8, x4, x2, x3) + +inst_144: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3bc and fs2 == 0 and fe2 == 0x0d and fm2 == 0x091 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x06a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77bc; op2val:0x3491; +op3val:0x706a; valaddr_reg:x1; val_offset:327*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 327*FLEN/8, x4, x2, x3) + +inst_145: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2b6 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x01f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2eb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72b6; op2val:0x441f; +op3val:0x7aeb; valaddr_reg:x1; val_offset:330*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 330*FLEN/8, x4, x2, x3) + +inst_146: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2b6 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x01f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2eb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72b6; op2val:0x441f; +op3val:0x7aeb; valaddr_reg:x1; val_offset:333*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 333*FLEN/8, x4, x2, x3) + +inst_147: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2b6 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x01f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2eb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72b6; op2val:0x441f; +op3val:0x7aeb; valaddr_reg:x1; val_offset:336*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 336*FLEN/8, x4, x2, x3) + +inst_148: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2b6 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x01f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2eb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72b6; op2val:0x441f; +op3val:0x7aeb; valaddr_reg:x1; val_offset:339*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 339*FLEN/8, x4, x2, x3) + +inst_149: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2b6 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x01f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2eb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72b6; op2val:0x441f; +op3val:0x7aeb; valaddr_reg:x1; val_offset:342*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 342*FLEN/8, x4, x2, x3) + +inst_150: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x195 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x098 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x26a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7995; op2val:0x2498; +op3val:0x626a; valaddr_reg:x1; val_offset:345*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 345*FLEN/8, x4, x2, x3) + +inst_151: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x195 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x098 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x26a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7995; op2val:0x2498; +op3val:0x626a; valaddr_reg:x1; val_offset:348*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 348*FLEN/8, x4, x2, x3) + +inst_152: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x195 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x098 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x26a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7995; op2val:0x2498; +op3val:0x626a; valaddr_reg:x1; val_offset:351*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 351*FLEN/8, x4, x2, x3) + +inst_153: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x195 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x098 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x26a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7995; op2val:0x2498; +op3val:0x626a; valaddr_reg:x1; val_offset:354*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 354*FLEN/8, x4, x2, x3) + +inst_154: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x195 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x098 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x26a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7995; op2val:0x2498; +op3val:0x626a; valaddr_reg:x1; val_offset:357*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 357*FLEN/8, x4, x2, x3) + +inst_155: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x238 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x19e and fs3 == 0 and fe3 == 0x19 and fm3 == 0x05e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a38; op2val:0x259e; +op3val:0x645e; valaddr_reg:x1; val_offset:360*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 360*FLEN/8, x4, x2, x3) +RVTEST_SIGBASE(x2,signature_x2_1) + +inst_156: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x238 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x19e and fs3 == 0 and fe3 == 0x19 and fm3 == 0x05e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a38; op2val:0x259e; +op3val:0x645e; valaddr_reg:x1; val_offset:363*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 363*FLEN/8, x4, x2, x3) + +inst_157: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x238 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x19e and fs3 == 0 and fe3 == 0x19 and fm3 == 0x05e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a38; op2val:0x259e; +op3val:0x645e; valaddr_reg:x1; val_offset:366*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 366*FLEN/8, x4, x2, x3) + +inst_158: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x238 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x19e and fs3 == 0 and fe3 == 0x19 and fm3 == 0x05e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a38; op2val:0x259e; +op3val:0x645e; valaddr_reg:x1; val_offset:369*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 369*FLEN/8, x4, x2, x3) + +inst_159: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x238 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x19e and fs3 == 0 and fe3 == 0x19 and fm3 == 0x05e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a38; op2val:0x259e; +op3val:0x645e; valaddr_reg:x1; val_offset:372*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 372*FLEN/8, x4, x2, x3) + +inst_160: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x152 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x16e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x33b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7552; op2val:0x416e; +op3val:0x7b3b; valaddr_reg:x1; val_offset:375*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 375*FLEN/8, x4, x2, x3) + +inst_161: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x152 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x16e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x33b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7552; op2val:0x416e; +op3val:0x7b3b; valaddr_reg:x1; val_offset:378*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 378*FLEN/8, x4, x2, x3) + +inst_162: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x152 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x16e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x33b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7552; op2val:0x416e; +op3val:0x7b3b; valaddr_reg:x1; val_offset:381*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 381*FLEN/8, x4, x2, x3) + +inst_163: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x152 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x16e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x33b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7552; op2val:0x416e; +op3val:0x7b3b; valaddr_reg:x1; val_offset:384*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 384*FLEN/8, x4, x2, x3) + +inst_164: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x152 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x16e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x33b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7552; op2val:0x416e; +op3val:0x7b3b; valaddr_reg:x1; val_offset:387*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 387*FLEN/8, x4, x2, x3) + +inst_165: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0f5 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3e5 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0e5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78f5; op2val:0x37e5; +op3val:0x74e5; valaddr_reg:x1; val_offset:390*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 390*FLEN/8, x4, x2, x3) + +inst_166: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0f5 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3e5 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0e5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78f5; op2val:0x37e5; +op3val:0x74e5; valaddr_reg:x1; val_offset:393*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 393*FLEN/8, x4, x2, x3) + +inst_167: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0f5 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3e5 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0e5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78f5; op2val:0x37e5; +op3val:0x74e5; valaddr_reg:x1; val_offset:396*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 396*FLEN/8, x4, x2, x3) + +inst_168: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0f5 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3e5 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0e5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78f5; op2val:0x37e5; +op3val:0x74e5; valaddr_reg:x1; val_offset:399*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 399*FLEN/8, x4, x2, x3) + +inst_169: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0f5 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3e5 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0e5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78f5; op2val:0x37e5; +op3val:0x74e5; valaddr_reg:x1; val_offset:402*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 402*FLEN/8, x4, x2, x3) + +inst_170: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x209 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x01f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x239 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7609; op2val:0x3c1f; +op3val:0x7639; valaddr_reg:x1; val_offset:405*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 405*FLEN/8, x4, x2, x3) + +inst_171: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x209 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x01f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x239 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7609; op2val:0x3c1f; +op3val:0x7639; valaddr_reg:x1; val_offset:408*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 408*FLEN/8, x4, x2, x3) + +inst_172: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x209 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x01f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x239 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7609; op2val:0x3c1f; +op3val:0x7639; valaddr_reg:x1; val_offset:411*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 411*FLEN/8, x4, x2, x3) + +inst_173: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x209 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x01f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x239 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7609; op2val:0x3c1f; +op3val:0x7639; valaddr_reg:x1; val_offset:414*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 414*FLEN/8, x4, x2, x3) + +inst_174: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x209 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x01f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x239 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7609; op2val:0x3c1f; +op3val:0x7639; valaddr_reg:x1; val_offset:417*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 417*FLEN/8, x4, x2, x3) + +inst_175: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x00e and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x700e; op2val:0x47e1; +op3val:0x7bfe; valaddr_reg:x1; val_offset:420*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 420*FLEN/8, x4, x2, x3) + +inst_176: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x00e and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3fe and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x700e; op2val:0x47e1; +op3val:0x7bfe; valaddr_reg:x1; val_offset:423*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 423*FLEN/8, x4, x2, x3) + +inst_177: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x00e and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3fe and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x700e; op2val:0x47e1; +op3val:0x7bfe; valaddr_reg:x1; val_offset:426*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 426*FLEN/8, x4, x2, x3) + +inst_178: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x00e and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3fe and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x700e; op2val:0x47e1; +op3val:0x7bfe; valaddr_reg:x1; val_offset:429*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 429*FLEN/8, x4, x2, x3) + +inst_179: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x00e and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3fe and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x700e; op2val:0x47e1; +op3val:0x7bfe; valaddr_reg:x1; val_offset:432*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 432*FLEN/8, x4, x2, x3) + +inst_180: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3da and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2c3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ae3; op2val:0x47da; +op3val:0x76c3; valaddr_reg:x1; val_offset:435*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 435*FLEN/8, x4, x2, x3) + +inst_181: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3da and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2c3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ae3; op2val:0x47da; +op3val:0x76c3; valaddr_reg:x1; val_offset:438*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 438*FLEN/8, x4, x2, x3) + +inst_182: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3da and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2c3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ae3; op2val:0x47da; +op3val:0x76c3; valaddr_reg:x1; val_offset:441*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 441*FLEN/8, x4, x2, x3) + +inst_183: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3da and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2c3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ae3; op2val:0x47da; +op3val:0x76c3; valaddr_reg:x1; val_offset:444*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 444*FLEN/8, x4, x2, x3) + +inst_184: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3da and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2c3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ae3; op2val:0x47da; +op3val:0x76c3; valaddr_reg:x1; val_offset:447*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 447*FLEN/8, x4, x2, x3) + +inst_185: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x043 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x25c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f7; op2val:0x3843; +op3val:0x765c; valaddr_reg:x1; val_offset:450*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 450*FLEN/8, x4, x2, x3) + +inst_186: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x043 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x25c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f7; op2val:0x3843; +op3val:0x765c; valaddr_reg:x1; val_offset:453*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 453*FLEN/8, x4, x2, x3) + +inst_187: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x043 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x25c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f7; op2val:0x3843; +op3val:0x765c; valaddr_reg:x1; val_offset:456*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 456*FLEN/8, x4, x2, x3) + +inst_188: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x043 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x25c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f7; op2val:0x3843; +op3val:0x765c; valaddr_reg:x1; val_offset:459*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 459*FLEN/8, x4, x2, x3) + +inst_189: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x043 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x25c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f7; op2val:0x3843; +op3val:0x765c; valaddr_reg:x1; val_offset:462*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 462*FLEN/8, x4, x2, x3) + +inst_190: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d8 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3d8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd8; op2val:0x3400; +op3val:0x73d8; valaddr_reg:x1; val_offset:465*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 465*FLEN/8, x4, x2, x3) + +inst_191: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d8 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3d8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd8; op2val:0x3400; +op3val:0x73d8; valaddr_reg:x1; val_offset:468*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 468*FLEN/8, x4, x2, x3) + +inst_192: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d8 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3d8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd8; op2val:0x3400; +op3val:0x73d8; valaddr_reg:x1; val_offset:471*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 471*FLEN/8, x4, x2, x3) + +inst_193: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d8 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3d8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd8; op2val:0x3400; +op3val:0x73d8; valaddr_reg:x1; val_offset:474*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 474*FLEN/8, x4, x2, x3) + +inst_194: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d8 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3d8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd8; op2val:0x3400; +op3val:0x73d8; valaddr_reg:x1; val_offset:477*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 477*FLEN/8, x4, x2, x3) + +inst_195: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d4 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x34a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x322 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd4; op2val:0x3b4a; +op3val:0x7b22; valaddr_reg:x1; val_offset:480*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 480*FLEN/8, x4, x2, x3) + +inst_196: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d4 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x34a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x322 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd4; op2val:0x3b4a; +op3val:0x7b22; valaddr_reg:x1; val_offset:483*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 483*FLEN/8, x4, x2, x3) + +inst_197: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d4 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x34a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x322 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd4; op2val:0x3b4a; +op3val:0x7b22; valaddr_reg:x1; val_offset:486*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 486*FLEN/8, x4, x2, x3) + +inst_198: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d4 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x34a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x322 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd4; op2val:0x3b4a; +op3val:0x7b22; valaddr_reg:x1; val_offset:489*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 489*FLEN/8, x4, x2, x3) + +inst_199: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d4 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x34a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x322 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd4; op2val:0x3b4a; +op3val:0x7b22; valaddr_reg:x1; val_offset:492*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 492*FLEN/8, x4, x2, x3) + +inst_200: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x14f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x31c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x795b; op2val:0x3d4f; +op3val:0x7b1c; valaddr_reg:x1; val_offset:495*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 495*FLEN/8, x4, x2, x3) + +inst_201: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x14f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x31c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x795b; op2val:0x3d4f; +op3val:0x7b1c; valaddr_reg:x1; val_offset:498*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 498*FLEN/8, x4, x2, x3) + +inst_202: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x14f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x31c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x795b; op2val:0x3d4f; +op3val:0x7b1c; valaddr_reg:x1; val_offset:501*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 501*FLEN/8, x4, x2, x3) + +inst_203: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x14f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x31c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x795b; op2val:0x3d4f; +op3val:0x7b1c; valaddr_reg:x1; val_offset:504*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 504*FLEN/8, x4, x2, x3) + +inst_204: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x14f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x31c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x795b; op2val:0x3d4f; +op3val:0x7b1c; valaddr_reg:x1; val_offset:507*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 507*FLEN/8, x4, x2, x3) + +inst_205: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x326 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x36f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7726; op2val:0x3f6f; +op3val:0x7aa5; valaddr_reg:x1; val_offset:510*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 510*FLEN/8, x4, x2, x3) + +inst_206: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x326 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x36f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7726; op2val:0x3f6f; +op3val:0x7aa5; valaddr_reg:x1; val_offset:513*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 513*FLEN/8, x4, x2, x3) + +inst_207: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x326 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x36f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7726; op2val:0x3f6f; +op3val:0x7aa5; valaddr_reg:x1; val_offset:516*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 516*FLEN/8, x4, x2, x3) + +inst_208: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x326 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x36f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7726; op2val:0x3f6f; +op3val:0x7aa5; valaddr_reg:x1; val_offset:519*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 519*FLEN/8, x4, x2, x3) + +inst_209: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x326 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x36f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7726; op2val:0x3f6f; +op3val:0x7aa5; valaddr_reg:x1; val_offset:522*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 522*FLEN/8, x4, x2, x3) + +inst_210: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x131 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x021 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5d; op2val:0x3931; +op3val:0x7821; valaddr_reg:x1; val_offset:525*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 525*FLEN/8, x4, x2, x3) + +inst_211: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x131 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x021 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5d; op2val:0x3931; +op3val:0x7821; valaddr_reg:x1; val_offset:528*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 528*FLEN/8, x4, x2, x3) + +inst_212: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x131 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x021 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5d; op2val:0x3931; +op3val:0x7821; valaddr_reg:x1; val_offset:531*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 531*FLEN/8, x4, x2, x3) + +inst_213: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x131 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x021 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5d; op2val:0x3931; +op3val:0x7821; valaddr_reg:x1; val_offset:534*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 534*FLEN/8, x4, x2, x3) + +inst_214: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x131 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x021 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5d; op2val:0x3931; +op3val:0x7821; valaddr_reg:x1; val_offset:537*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 537*FLEN/8, x4, x2, x3) + +inst_215: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x388 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7788; op2val:0x3dfe; +op3val:0x79a4; valaddr_reg:x1; val_offset:540*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 540*FLEN/8, x4, x2, x3) + +inst_216: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x388 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7788; op2val:0x3dfe; +op3val:0x79a4; valaddr_reg:x1; val_offset:543*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 543*FLEN/8, x4, x2, x3) + +inst_217: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x388 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7788; op2val:0x3dfe; +op3val:0x79a4; valaddr_reg:x1; val_offset:546*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 546*FLEN/8, x4, x2, x3) + +inst_218: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x388 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7788; op2val:0x3dfe; +op3val:0x79a4; valaddr_reg:x1; val_offset:549*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 549*FLEN/8, x4, x2, x3) + +inst_219: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x388 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7788; op2val:0x3dfe; +op3val:0x79a4; valaddr_reg:x1; val_offset:552*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 552*FLEN/8, x4, x2, x3) + +inst_220: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x28a and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2b9 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x17f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x768a; op2val:0x32b9; +op3val:0x6d7f; valaddr_reg:x1; val_offset:555*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 555*FLEN/8, x4, x2, x3) + +inst_221: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x28a and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2b9 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x17f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x768a; op2val:0x32b9; +op3val:0x6d7f; valaddr_reg:x1; val_offset:558*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 558*FLEN/8, x4, x2, x3) + +inst_222: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x28a and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2b9 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x17f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x768a; op2val:0x32b9; +op3val:0x6d7f; valaddr_reg:x1; val_offset:561*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 561*FLEN/8, x4, x2, x3) + +inst_223: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x28a and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2b9 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x17f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x768a; op2val:0x32b9; +op3val:0x6d7f; valaddr_reg:x1; val_offset:564*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 564*FLEN/8, x4, x2, x3) + +inst_224: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x28a and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2b9 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x17f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x768a; op2val:0x32b9; +op3val:0x6d7f; valaddr_reg:x1; val_offset:567*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 567*FLEN/8, x4, x2, x3) + +inst_225: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f8 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1b2 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x040 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f8; op2val:0x35b2; +op3val:0x7440; valaddr_reg:x1; val_offset:570*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 570*FLEN/8, x4, x2, x3) + +inst_226: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f8 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1b2 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x040 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f8; op2val:0x35b2; +op3val:0x7440; valaddr_reg:x1; val_offset:573*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 573*FLEN/8, x4, x2, x3) + +inst_227: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f8 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1b2 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x040 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f8; op2val:0x35b2; +op3val:0x7440; valaddr_reg:x1; val_offset:576*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 576*FLEN/8, x4, x2, x3) + +inst_228: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f8 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1b2 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x040 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f8; op2val:0x35b2; +op3val:0x7440; valaddr_reg:x1; val_offset:579*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 579*FLEN/8, x4, x2, x3) + +inst_229: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f8 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1b2 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x040 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f8; op2val:0x35b2; +op3val:0x7440; valaddr_reg:x1; val_offset:582*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 582*FLEN/8, x4, x2, x3) + +inst_230: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3cc and fs2 == 0 and fe2 == 0x0f and fm2 == 0x26e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x244 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77cc; op2val:0x3e6e; +op3val:0x7a44; valaddr_reg:x1; val_offset:585*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 585*FLEN/8, x4, x2, x3) + +inst_231: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3cc and fs2 == 0 and fe2 == 0x0f and fm2 == 0x26e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x244 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77cc; op2val:0x3e6e; +op3val:0x7a44; valaddr_reg:x1; val_offset:588*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 588*FLEN/8, x4, x2, x3) + +inst_232: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3cc and fs2 == 0 and fe2 == 0x0f and fm2 == 0x26e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x244 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77cc; op2val:0x3e6e; +op3val:0x7a44; valaddr_reg:x1; val_offset:591*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 591*FLEN/8, x4, x2, x3) + +inst_233: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3cc and fs2 == 0 and fe2 == 0x0f and fm2 == 0x26e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x244 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77cc; op2val:0x3e6e; +op3val:0x7a44; valaddr_reg:x1; val_offset:594*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 594*FLEN/8, x4, x2, x3) + +inst_234: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3cc and fs2 == 0 and fe2 == 0x0f and fm2 == 0x26e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x244 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77cc; op2val:0x3e6e; +op3val:0x7a44; valaddr_reg:x1; val_offset:597*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 597*FLEN/8, x4, x2, x3) + +inst_235: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x181 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x011 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x199 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7181; op2val:0x3011; +op3val:0x6599; valaddr_reg:x1; val_offset:600*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 600*FLEN/8, x4, x2, x3) + +inst_236: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x181 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x011 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x199 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7181; op2val:0x3011; +op3val:0x6599; valaddr_reg:x1; val_offset:603*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 603*FLEN/8, x4, x2, x3) + +inst_237: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x181 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x011 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x199 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7181; op2val:0x3011; +op3val:0x6599; valaddr_reg:x1; val_offset:606*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 606*FLEN/8, x4, x2, x3) + +inst_238: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x181 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x011 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x199 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7181; op2val:0x3011; +op3val:0x6599; valaddr_reg:x1; val_offset:609*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 609*FLEN/8, x4, x2, x3) + +inst_239: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x181 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x011 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x199 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7181; op2val:0x3011; +op3val:0x6599; valaddr_reg:x1; val_offset:612*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 612*FLEN/8, x4, x2, x3) + +inst_240: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3e6 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0b6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6fe6; op2val:0x44c5; +op3val:0x78b6; valaddr_reg:x1; val_offset:615*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 615*FLEN/8, x4, x2, x3) + +inst_241: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3e6 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0b6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6fe6; op2val:0x44c5; +op3val:0x78b6; valaddr_reg:x1; val_offset:618*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 618*FLEN/8, x4, x2, x3) + +inst_242: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3e6 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0b6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6fe6; op2val:0x44c5; +op3val:0x78b6; valaddr_reg:x1; val_offset:621*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 621*FLEN/8, x4, x2, x3) + +inst_243: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3e6 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0b6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6fe6; op2val:0x44c5; +op3val:0x78b6; valaddr_reg:x1; val_offset:624*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 624*FLEN/8, x4, x2, x3) + +inst_244: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3e6 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0b6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6fe6; op2val:0x44c5; +op3val:0x78b6; valaddr_reg:x1; val_offset:627*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 627*FLEN/8, x4, x2, x3) + +inst_245: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1ad and fs3 == 0 and fe3 == 0x1d and fm3 == 0x019 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c6; op2val:0x39ad; +op3val:0x7419; valaddr_reg:x1; val_offset:630*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 630*FLEN/8, x4, x2, x3) + +inst_246: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1ad and fs3 == 0 and fe3 == 0x1d and fm3 == 0x019 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c6; op2val:0x39ad; +op3val:0x7419; valaddr_reg:x1; val_offset:633*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 633*FLEN/8, x4, x2, x3) + +inst_247: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1ad and fs3 == 0 and fe3 == 0x1d and fm3 == 0x019 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c6; op2val:0x39ad; +op3val:0x7419; valaddr_reg:x1; val_offset:636*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 636*FLEN/8, x4, x2, x3) + +inst_248: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1ad and fs3 == 0 and fe3 == 0x1d and fm3 == 0x019 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c6; op2val:0x39ad; +op3val:0x7419; valaddr_reg:x1; val_offset:639*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 639*FLEN/8, x4, x2, x3) + +inst_249: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1ad and fs3 == 0 and fe3 == 0x1d and fm3 == 0x019 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c6; op2val:0x39ad; +op3val:0x7419; valaddr_reg:x1; val_offset:642*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 642*FLEN/8, x4, x2, x3) + +inst_250: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x338 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x01b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x36a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7738; op2val:0x401b; +op3val:0x7b6a; valaddr_reg:x1; val_offset:645*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 645*FLEN/8, x4, x2, x3) + +inst_251: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x338 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x01b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x36a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7738; op2val:0x401b; +op3val:0x7b6a; valaddr_reg:x1; val_offset:648*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 648*FLEN/8, x4, x2, x3) + +inst_252: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x338 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x01b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x36a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7738; op2val:0x401b; +op3val:0x7b6a; valaddr_reg:x1; val_offset:651*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 651*FLEN/8, x4, x2, x3) + +inst_253: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x338 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x01b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x36a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7738; op2val:0x401b; +op3val:0x7b6a; valaddr_reg:x1; val_offset:654*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 654*FLEN/8, x4, x2, x3) + +inst_254: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x338 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x01b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x36a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7738; op2val:0x401b; +op3val:0x7b6a; valaddr_reg:x1; val_offset:657*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 657*FLEN/8, x4, x2, x3) + +inst_255: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x013 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x272 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x290 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7413; op2val:0x3e72; +op3val:0x7690; valaddr_reg:x1; val_offset:660*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 660*FLEN/8, x4, x2, x3) + +inst_256: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x013 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x272 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x290 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7413; op2val:0x3e72; +op3val:0x7690; valaddr_reg:x1; val_offset:663*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 663*FLEN/8, x4, x2, x3) + +inst_257: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x013 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x272 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x290 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7413; op2val:0x3e72; +op3val:0x7690; valaddr_reg:x1; val_offset:666*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 666*FLEN/8, x4, x2, x3) + +inst_258: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x013 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x272 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x290 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7413; op2val:0x3e72; +op3val:0x7690; valaddr_reg:x1; val_offset:669*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 669*FLEN/8, x4, x2, x3) + +inst_259: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x013 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x272 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x290 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7413; op2val:0x3e72; +op3val:0x7690; valaddr_reg:x1; val_offset:672*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 672*FLEN/8, x4, x2, x3) + +inst_260: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x307 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x191 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0e5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b07; op2val:0x3991; +op3val:0x78e5; valaddr_reg:x1; val_offset:675*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 675*FLEN/8, x4, x2, x3) + +inst_261: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x307 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x191 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0e5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b07; op2val:0x3991; +op3val:0x78e5; valaddr_reg:x1; val_offset:678*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 678*FLEN/8, x4, x2, x3) + +inst_262: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x307 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x191 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0e5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b07; op2val:0x3991; +op3val:0x78e5; valaddr_reg:x1; val_offset:681*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 681*FLEN/8, x4, x2, x3) + +inst_263: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x307 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x191 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0e5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b07; op2val:0x3991; +op3val:0x78e5; valaddr_reg:x1; val_offset:684*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 684*FLEN/8, x4, x2, x3) + +inst_264: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x307 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x191 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0e5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b07; op2val:0x3991; +op3val:0x78e5; valaddr_reg:x1; val_offset:687*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 687*FLEN/8, x4, x2, x3) + +inst_265: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x048 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x316 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x397 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7448; op2val:0x3f16; +op3val:0x7797; valaddr_reg:x1; val_offset:690*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 690*FLEN/8, x4, x2, x3) + +inst_266: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x048 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x316 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x397 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7448; op2val:0x3f16; +op3val:0x7797; valaddr_reg:x1; val_offset:693*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 693*FLEN/8, x4, x2, x3) + +inst_267: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x048 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x316 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x397 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7448; op2val:0x3f16; +op3val:0x7797; valaddr_reg:x1; val_offset:696*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 696*FLEN/8, x4, x2, x3) + +inst_268: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x048 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x316 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x397 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7448; op2val:0x3f16; +op3val:0x7797; valaddr_reg:x1; val_offset:699*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 699*FLEN/8, x4, x2, x3) + +inst_269: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x048 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x316 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x397 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7448; op2val:0x3f16; +op3val:0x7797; valaddr_reg:x1; val_offset:702*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 702*FLEN/8, x4, x2, x3) + +inst_270: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a7 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0c1 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x08c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77a7; op2val:0x34c1; +op3val:0x708c; valaddr_reg:x1; val_offset:705*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 705*FLEN/8, x4, x2, x3) + +inst_271: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a7 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0c1 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x08c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77a7; op2val:0x34c1; +op3val:0x708c; valaddr_reg:x1; val_offset:708*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 708*FLEN/8, x4, x2, x3) + +inst_272: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a7 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0c1 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x08c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77a7; op2val:0x34c1; +op3val:0x708c; valaddr_reg:x1; val_offset:711*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 711*FLEN/8, x4, x2, x3) + +inst_273: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a7 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0c1 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x08c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77a7; op2val:0x34c1; +op3val:0x708c; valaddr_reg:x1; val_offset:714*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 714*FLEN/8, x4, x2, x3) + +inst_274: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a7 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0c1 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x08c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77a7; op2val:0x34c1; +op3val:0x708c; valaddr_reg:x1; val_offset:717*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 717*FLEN/8, x4, x2, x3) + +inst_275: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x209 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x27a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0e3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7609; op2val:0x3a7a; +op3val:0x74e3; valaddr_reg:x1; val_offset:720*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 720*FLEN/8, x4, x2, x3) + +inst_276: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x209 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x27a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0e3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7609; op2val:0x3a7a; +op3val:0x74e3; valaddr_reg:x1; val_offset:723*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 723*FLEN/8, x4, x2, x3) + +inst_277: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x209 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x27a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0e3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7609; op2val:0x3a7a; +op3val:0x74e3; valaddr_reg:x1; val_offset:726*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 726*FLEN/8, x4, x2, x3) + +inst_278: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x209 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x27a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0e3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7609; op2val:0x3a7a; +op3val:0x74e3; valaddr_reg:x1; val_offset:729*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 729*FLEN/8, x4, x2, x3) + +inst_279: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x209 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x27a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0e3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7609; op2val:0x3a7a; +op3val:0x74e3; valaddr_reg:x1; val_offset:732*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 732*FLEN/8, x4, x2, x3) + +inst_280: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26f and fs2 == 0 and fe2 == 0x0d and fm2 == 0x26e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x12c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a6f; op2val:0x366e; +op3val:0x752c; valaddr_reg:x1; val_offset:735*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 735*FLEN/8, x4, x2, x3) + +inst_281: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26f and fs2 == 0 and fe2 == 0x0d and fm2 == 0x26e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x12c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a6f; op2val:0x366e; +op3val:0x752c; valaddr_reg:x1; val_offset:738*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 738*FLEN/8, x4, x2, x3) + +inst_282: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26f and fs2 == 0 and fe2 == 0x0d and fm2 == 0x26e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x12c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a6f; op2val:0x366e; +op3val:0x752c; valaddr_reg:x1; val_offset:741*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 741*FLEN/8, x4, x2, x3) + +inst_283: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26f and fs2 == 0 and fe2 == 0x0d and fm2 == 0x26e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x12c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a6f; op2val:0x366e; +op3val:0x752c; valaddr_reg:x1; val_offset:744*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 744*FLEN/8, x4, x2, x3) +RVTEST_SIGBASE(x2,signature_x2_2) + +inst_284: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26f and fs2 == 0 and fe2 == 0x0d and fm2 == 0x26e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x12c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a6f; op2val:0x366e; +op3val:0x752c; valaddr_reg:x1; val_offset:747*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 747*FLEN/8, x4, x2, x3) + +inst_285: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x145 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1e3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3c3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7945; op2val:0x3de3; +op3val:0x7bc3; valaddr_reg:x1; val_offset:750*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 750*FLEN/8, x4, x2, x3) + +inst_286: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x145 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1e3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3c3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7945; op2val:0x3de3; +op3val:0x7bc3; valaddr_reg:x1; val_offset:753*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 753*FLEN/8, x4, x2, x3) + +inst_287: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x145 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1e3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3c3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7945; op2val:0x3de3; +op3val:0x7bc3; valaddr_reg:x1; val_offset:756*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 756*FLEN/8, x4, x2, x3) + +inst_288: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x145 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1e3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3c3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7945; op2val:0x3de3; +op3val:0x7bc3; valaddr_reg:x1; val_offset:759*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 759*FLEN/8, x4, x2, x3) + +inst_289: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x145 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1e3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3c3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7945; op2val:0x3de3; +op3val:0x7bc3; valaddr_reg:x1; val_offset:762*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 762*FLEN/8, x4, x2, x3) + +inst_290: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x361 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x284 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x203 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b61; op2val:0x3684; +op3val:0x7603; valaddr_reg:x1; val_offset:765*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 765*FLEN/8, x4, x2, x3) + +inst_291: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x361 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x284 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x203 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b61; op2val:0x3684; +op3val:0x7603; valaddr_reg:x1; val_offset:768*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 768*FLEN/8, x4, x2, x3) + +inst_292: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x361 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x284 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x203 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b61; op2val:0x3684; +op3val:0x7603; valaddr_reg:x1; val_offset:771*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 771*FLEN/8, x4, x2, x3) + +inst_293: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x361 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x284 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x203 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b61; op2val:0x3684; +op3val:0x7603; valaddr_reg:x1; val_offset:774*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 774*FLEN/8, x4, x2, x3) + +inst_294: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x361 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x284 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x203 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b61; op2val:0x3684; +op3val:0x7603; valaddr_reg:x1; val_offset:777*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 777*FLEN/8, x4, x2, x3) + +inst_295: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d2 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x03f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x11e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78d2; op2val:0x383f; +op3val:0x751e; valaddr_reg:x1; val_offset:780*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 780*FLEN/8, x4, x2, x3) + +inst_296: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d2 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x03f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x11e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78d2; op2val:0x383f; +op3val:0x751e; valaddr_reg:x1; val_offset:783*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 783*FLEN/8, x4, x2, x3) + +inst_297: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d2 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x03f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x11e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78d2; op2val:0x383f; +op3val:0x751e; valaddr_reg:x1; val_offset:786*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 786*FLEN/8, x4, x2, x3) + +inst_298: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d2 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x03f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x11e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78d2; op2val:0x383f; +op3val:0x751e; valaddr_reg:x1; val_offset:789*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 789*FLEN/8, x4, x2, x3) + +inst_299: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d2 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x03f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x11e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78d2; op2val:0x383f; +op3val:0x751e; valaddr_reg:x1; val_offset:792*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 792*FLEN/8, x4, x2, x3) + +inst_300: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x25e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0e6 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3cd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x765e; op2val:0x3ce6; +op3val:0x77cd; valaddr_reg:x1; val_offset:795*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 795*FLEN/8, x4, x2, x3) + +inst_301: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x25e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0e6 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3cd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x765e; op2val:0x3ce6; +op3val:0x77cd; valaddr_reg:x1; val_offset:798*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 798*FLEN/8, x4, x2, x3) + +inst_302: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x25e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0e6 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3cd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x765e; op2val:0x3ce6; +op3val:0x77cd; valaddr_reg:x1; val_offset:801*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 801*FLEN/8, x4, x2, x3) + +inst_303: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x25e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0e6 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3cd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x765e; op2val:0x3ce6; +op3val:0x77cd; valaddr_reg:x1; val_offset:804*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 804*FLEN/8, x4, x2, x3) + +inst_304: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x25e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0e6 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3cd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x765e; op2val:0x3ce6; +op3val:0x77cd; valaddr_reg:x1; val_offset:807*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 807*FLEN/8, x4, x2, x3) + +inst_305: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x258 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0b8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x37d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a58; op2val:0x3cb8; +op3val:0x7b7d; valaddr_reg:x1; val_offset:810*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 810*FLEN/8, x4, x2, x3) + +inst_306: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x258 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0b8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x37d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a58; op2val:0x3cb8; +op3val:0x7b7d; valaddr_reg:x1; val_offset:813*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 813*FLEN/8, x4, x2, x3) + +inst_307: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x258 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0b8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x37d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a58; op2val:0x3cb8; +op3val:0x7b7d; valaddr_reg:x1; val_offset:816*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 816*FLEN/8, x4, x2, x3) + +inst_308: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x258 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0b8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x37d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a58; op2val:0x3cb8; +op3val:0x7b7d; valaddr_reg:x1; val_offset:819*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 819*FLEN/8, x4, x2, x3) + +inst_309: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x258 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0b8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x37d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a58; op2val:0x3cb8; +op3val:0x7b7d; valaddr_reg:x1; val_offset:822*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 822*FLEN/8, x4, x2, x3) + +inst_310: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a6 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x176 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x25a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74a6; op2val:0x2576; +op3val:0x5e5a; valaddr_reg:x1; val_offset:825*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 825*FLEN/8, x4, x2, x3) + +inst_311: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a6 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x176 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x25a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74a6; op2val:0x2576; +op3val:0x5e5a; valaddr_reg:x1; val_offset:828*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 828*FLEN/8, x4, x2, x3) + +inst_312: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a6 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x176 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x25a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74a6; op2val:0x2576; +op3val:0x5e5a; valaddr_reg:x1; val_offset:831*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 831*FLEN/8, x4, x2, x3) + +inst_313: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a6 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x176 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x25a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74a6; op2val:0x2576; +op3val:0x5e5a; valaddr_reg:x1; val_offset:834*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 834*FLEN/8, x4, x2, x3) + +inst_314: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a6 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x176 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x25a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74a6; op2val:0x2576; +op3val:0x5e5a; valaddr_reg:x1; val_offset:837*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 837*FLEN/8, x4, x2, x3) + +inst_315: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x32f and fs2 == 0 and fe2 == 0x0c and fm2 == 0x011 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x34e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x772f; op2val:0x3011; +op3val:0x6b4e; valaddr_reg:x1; val_offset:840*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 840*FLEN/8, x4, x2, x3) + +inst_316: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x32f and fs2 == 0 and fe2 == 0x0c and fm2 == 0x011 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x34e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x772f; op2val:0x3011; +op3val:0x6b4e; valaddr_reg:x1; val_offset:843*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 843*FLEN/8, x4, x2, x3) + +inst_317: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x32f and fs2 == 0 and fe2 == 0x0c and fm2 == 0x011 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x34e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x772f; op2val:0x3011; +op3val:0x6b4e; valaddr_reg:x1; val_offset:846*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 846*FLEN/8, x4, x2, x3) + +inst_318: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x32f and fs2 == 0 and fe2 == 0x0c and fm2 == 0x011 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x34e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x772f; op2val:0x3011; +op3val:0x6b4e; valaddr_reg:x1; val_offset:849*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 849*FLEN/8, x4, x2, x3) + +inst_319: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x32f and fs2 == 0 and fe2 == 0x0c and fm2 == 0x011 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x34e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x772f; op2val:0x3011; +op3val:0x6b4e; valaddr_reg:x1; val_offset:852*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 852*FLEN/8, x4, x2, x3) + +inst_320: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x3b5 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x26b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x22f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x67b5; op2val:0x4e6b; +op3val:0x7a2f; valaddr_reg:x1; val_offset:855*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 855*FLEN/8, x4, x2, x3) + +inst_321: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x3b5 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x26b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x22f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x67b5; op2val:0x4e6b; +op3val:0x7a2f; valaddr_reg:x1; val_offset:858*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 858*FLEN/8, x4, x2, x3) + +inst_322: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x3b5 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x26b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x22f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x67b5; op2val:0x4e6b; +op3val:0x7a2f; valaddr_reg:x1; val_offset:861*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 861*FLEN/8, x4, x2, x3) + +inst_323: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x3b5 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x26b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x22f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x67b5; op2val:0x4e6b; +op3val:0x7a2f; valaddr_reg:x1; val_offset:864*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 864*FLEN/8, x4, x2, x3) + +inst_324: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x3b5 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x26b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x22f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x67b5; op2val:0x4e6b; +op3val:0x7a2f; valaddr_reg:x1; val_offset:867*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 867*FLEN/8, x4, x2, x3) + +inst_325: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x32c and fs2 == 0 and fe2 == 0x11 and fm2 == 0x268 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1be and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f2c; op2val:0x4668; +op3val:0x79be; valaddr_reg:x1; val_offset:870*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 870*FLEN/8, x4, x2, x3) + +inst_326: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x32c and fs2 == 0 and fe2 == 0x11 and fm2 == 0x268 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1be and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f2c; op2val:0x4668; +op3val:0x79be; valaddr_reg:x1; val_offset:873*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 873*FLEN/8, x4, x2, x3) + +inst_327: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x32c and fs2 == 0 and fe2 == 0x11 and fm2 == 0x268 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1be and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f2c; op2val:0x4668; +op3val:0x79be; valaddr_reg:x1; val_offset:876*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 876*FLEN/8, x4, x2, x3) + +inst_328: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x32c and fs2 == 0 and fe2 == 0x11 and fm2 == 0x268 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1be and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f2c; op2val:0x4668; +op3val:0x79be; valaddr_reg:x1; val_offset:879*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 879*FLEN/8, x4, x2, x3) + +inst_329: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x32c and fs2 == 0 and fe2 == 0x11 and fm2 == 0x268 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1be and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f2c; op2val:0x4668; +op3val:0x79be; valaddr_reg:x1; val_offset:882*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 882*FLEN/8, x4, x2, x3) + +inst_330: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ca and fs2 == 0 and fe2 == 0x10 and fm2 == 0x12f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75ca; op2val:0x412f; +op3val:0x7b80; valaddr_reg:x1; val_offset:885*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 885*FLEN/8, x4, x2, x3) + +inst_331: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ca and fs2 == 0 and fe2 == 0x10 and fm2 == 0x12f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x380 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75ca; op2val:0x412f; +op3val:0x7b80; valaddr_reg:x1; val_offset:888*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 888*FLEN/8, x4, x2, x3) + +inst_332: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ca and fs2 == 0 and fe2 == 0x10 and fm2 == 0x12f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x380 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75ca; op2val:0x412f; +op3val:0x7b80; valaddr_reg:x1; val_offset:891*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 891*FLEN/8, x4, x2, x3) + +inst_333: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ca and fs2 == 0 and fe2 == 0x10 and fm2 == 0x12f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x380 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75ca; op2val:0x412f; +op3val:0x7b80; valaddr_reg:x1; val_offset:894*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 894*FLEN/8, x4, x2, x3) + +inst_334: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ca and fs2 == 0 and fe2 == 0x10 and fm2 == 0x12f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x380 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75ca; op2val:0x412f; +op3val:0x7b80; valaddr_reg:x1; val_offset:897*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 897*FLEN/8, x4, x2, x3) + +inst_335: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d3 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x0ab and fs3 == 0 and fe3 == 0x1a and fm3 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ad3; op2val:0x2cab; +op3val:0x6bf8; valaddr_reg:x1; val_offset:900*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 900*FLEN/8, x4, x2, x3) + +inst_336: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d3 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x0ab and fs3 == 0 and fe3 == 0x1a and fm3 == 0x3f8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ad3; op2val:0x2cab; +op3val:0x6bf8; valaddr_reg:x1; val_offset:903*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 903*FLEN/8, x4, x2, x3) + +inst_337: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d3 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x0ab and fs3 == 0 and fe3 == 0x1a and fm3 == 0x3f8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ad3; op2val:0x2cab; +op3val:0x6bf8; valaddr_reg:x1; val_offset:906*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 906*FLEN/8, x4, x2, x3) + +inst_338: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d3 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x0ab and fs3 == 0 and fe3 == 0x1a and fm3 == 0x3f8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ad3; op2val:0x2cab; +op3val:0x6bf8; valaddr_reg:x1; val_offset:909*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 909*FLEN/8, x4, x2, x3) + +inst_339: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d3 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x0ab and fs3 == 0 and fe3 == 0x1a and fm3 == 0x3f8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ad3; op2val:0x2cab; +op3val:0x6bf8; valaddr_reg:x1; val_offset:912*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 912*FLEN/8, x4, x2, x3) + +inst_340: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x229 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0ea and fs3 == 0 and fe3 == 0x1e and fm3 == 0x393 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7229; op2val:0x44ea; +op3val:0x7b93; valaddr_reg:x1; val_offset:915*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 915*FLEN/8, x4, x2, x3) + +inst_341: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x229 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0ea and fs3 == 0 and fe3 == 0x1e and fm3 == 0x393 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7229; op2val:0x44ea; +op3val:0x7b93; valaddr_reg:x1; val_offset:918*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 918*FLEN/8, x4, x2, x3) + +inst_342: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x229 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0ea and fs3 == 0 and fe3 == 0x1e and fm3 == 0x393 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7229; op2val:0x44ea; +op3val:0x7b93; valaddr_reg:x1; val_offset:921*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 921*FLEN/8, x4, x2, x3) + +inst_343: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x229 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0ea and fs3 == 0 and fe3 == 0x1e and fm3 == 0x393 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7229; op2val:0x44ea; +op3val:0x7b93; valaddr_reg:x1; val_offset:924*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 924*FLEN/8, x4, x2, x3) + +inst_344: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x229 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0ea and fs3 == 0 and fe3 == 0x1e and fm3 == 0x393 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7229; op2val:0x44ea; +op3val:0x7b93; valaddr_reg:x1; val_offset:927*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 927*FLEN/8, x4, x2, x3) + +inst_345: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x181 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e7; op2val:0x3981; +op3val:0x76c0; valaddr_reg:x1; val_offset:930*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 930*FLEN/8, x4, x2, x3) + +inst_346: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x181 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2c0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e7; op2val:0x3981; +op3val:0x76c0; valaddr_reg:x1; val_offset:933*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 933*FLEN/8, x4, x2, x3) + +inst_347: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x181 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2c0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e7; op2val:0x3981; +op3val:0x76c0; valaddr_reg:x1; val_offset:936*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 936*FLEN/8, x4, x2, x3) + +inst_348: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x181 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2c0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e7; op2val:0x3981; +op3val:0x76c0; valaddr_reg:x1; val_offset:939*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 939*FLEN/8, x4, x2, x3) + +inst_349: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x181 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2c0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e7; op2val:0x3981; +op3val:0x76c0; valaddr_reg:x1; val_offset:942*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 942*FLEN/8, x4, x2, x3) + +inst_350: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x241 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x028 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x281 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a41; op2val:0x3c28; +op3val:0x7a81; valaddr_reg:x1; val_offset:945*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 945*FLEN/8, x4, x2, x3) + +inst_351: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x241 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x028 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x281 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a41; op2val:0x3c28; +op3val:0x7a81; valaddr_reg:x1; val_offset:948*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 948*FLEN/8, x4, x2, x3) + +inst_352: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x241 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x028 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x281 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a41; op2val:0x3c28; +op3val:0x7a81; valaddr_reg:x1; val_offset:951*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 951*FLEN/8, x4, x2, x3) + +inst_353: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x241 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x028 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x281 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a41; op2val:0x3c28; +op3val:0x7a81; valaddr_reg:x1; val_offset:954*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 954*FLEN/8, x4, x2, x3) + +inst_354: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x241 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x028 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x281 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a41; op2val:0x3c28; +op3val:0x7a81; valaddr_reg:x1; val_offset:957*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 957*FLEN/8, x4, x2, x3) + +inst_355: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3dd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3a1 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x37f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77dd; op2val:0x3ba1; +op3val:0x777f; valaddr_reg:x1; val_offset:960*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 960*FLEN/8, x4, x2, x3) + +inst_356: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3dd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3a1 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x37f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77dd; op2val:0x3ba1; +op3val:0x777f; valaddr_reg:x1; val_offset:963*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 963*FLEN/8, x4, x2, x3) + +inst_357: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3dd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3a1 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x37f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77dd; op2val:0x3ba1; +op3val:0x777f; valaddr_reg:x1; val_offset:966*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 966*FLEN/8, x4, x2, x3) + +inst_358: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3dd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3a1 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x37f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77dd; op2val:0x3ba1; +op3val:0x777f; valaddr_reg:x1; val_offset:969*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 969*FLEN/8, x4, x2, x3) + +inst_359: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3dd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3a1 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x37f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77dd; op2val:0x3ba1; +op3val:0x777f; valaddr_reg:x1; val_offset:972*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 972*FLEN/8, x4, x2, x3) + +inst_360: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x268 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x33a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1c9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e68; op2val:0x433a; +op3val:0x75c9; valaddr_reg:x1; val_offset:975*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 975*FLEN/8, x4, x2, x3) + +inst_361: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x268 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x33a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1c9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e68; op2val:0x433a; +op3val:0x75c9; valaddr_reg:x1; val_offset:978*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 978*FLEN/8, x4, x2, x3) + +inst_362: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x268 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x33a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1c9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e68; op2val:0x433a; +op3val:0x75c9; valaddr_reg:x1; val_offset:981*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 981*FLEN/8, x4, x2, x3) + +inst_363: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x268 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x33a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1c9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e68; op2val:0x433a; +op3val:0x75c9; valaddr_reg:x1; val_offset:984*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 984*FLEN/8, x4, x2, x3) + +inst_364: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x268 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x33a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1c9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e68; op2val:0x433a; +op3val:0x75c9; valaddr_reg:x1; val_offset:987*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 987*FLEN/8, x4, x2, x3) + +inst_365: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0a3 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x050 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70a3; op2val:0x4450; +op3val:0x7900; valaddr_reg:x1; val_offset:990*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 990*FLEN/8, x4, x2, x3) + +inst_366: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0a3 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x050 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x100 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70a3; op2val:0x4450; +op3val:0x7900; valaddr_reg:x1; val_offset:993*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 993*FLEN/8, x4, x2, x3) + +inst_367: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0a3 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x050 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x100 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70a3; op2val:0x4450; +op3val:0x7900; valaddr_reg:x1; val_offset:996*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 996*FLEN/8, x4, x2, x3) + +inst_368: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0a3 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x050 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x100 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70a3; op2val:0x4450; +op3val:0x7900; valaddr_reg:x1; val_offset:999*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 999*FLEN/8, x4, x2, x3) + +inst_369: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0a3 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x050 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x100 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70a3; op2val:0x4450; +op3val:0x7900; valaddr_reg:x1; val_offset:1002*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1002*FLEN/8, x4, x2, x3) + +inst_370: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d9 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x39c and fs3 == 0 and fe3 == 0x1c and fm3 == 0x09d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78d9; op2val:0x339c; +op3val:0x709d; valaddr_reg:x1; val_offset:1005*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1005*FLEN/8, x4, x2, x3) + +inst_371: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d9 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x39c and fs3 == 0 and fe3 == 0x1c and fm3 == 0x09d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78d9; op2val:0x339c; +op3val:0x709d; valaddr_reg:x1; val_offset:1008*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1008*FLEN/8, x4, x2, x3) + +inst_372: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d9 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x39c and fs3 == 0 and fe3 == 0x1c and fm3 == 0x09d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78d9; op2val:0x339c; +op3val:0x709d; valaddr_reg:x1; val_offset:1011*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1011*FLEN/8, x4, x2, x3) + +inst_373: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d9 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x39c and fs3 == 0 and fe3 == 0x1c and fm3 == 0x09d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78d9; op2val:0x339c; +op3val:0x709d; valaddr_reg:x1; val_offset:1014*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1014*FLEN/8, x4, x2, x3) + +inst_374: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d9 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x39c and fs3 == 0 and fe3 == 0x1c and fm3 == 0x09d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78d9; op2val:0x339c; +op3val:0x709d; valaddr_reg:x1; val_offset:1017*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1017*FLEN/8, x4, x2, x3) + +inst_375: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x105 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0f5 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x239 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7905; op2val:0x30f5; +op3val:0x6e39; valaddr_reg:x1; val_offset:1020*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1020*FLEN/8, x4, x2, x3) + +inst_376: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x105 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0f5 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x239 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7905; op2val:0x30f5; +op3val:0x6e39; valaddr_reg:x1; val_offset:1023*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1023*FLEN/8, x4, x2, x3) + +inst_377: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x105 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0f5 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x239 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7905; op2val:0x30f5; +op3val:0x6e39; valaddr_reg:x1; val_offset:1026*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1026*FLEN/8, x4, x2, x3) + +inst_378: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x105 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0f5 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x239 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7905; op2val:0x30f5; +op3val:0x6e39; valaddr_reg:x1; val_offset:1029*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1029*FLEN/8, x4, x2, x3) + +inst_379: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x105 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0f5 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x239 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7905; op2val:0x30f5; +op3val:0x6e39; valaddr_reg:x1; val_offset:1032*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1032*FLEN/8, x4, x2, x3) + +inst_380: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2be and fs2 == 0 and fe2 == 0x11 and fm2 == 0x21f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x129 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ebe; op2val:0x461f; +op3val:0x7929; valaddr_reg:x1; val_offset:1035*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1035*FLEN/8, x4, x2, x3) + +inst_381: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2be and fs2 == 0 and fe2 == 0x11 and fm2 == 0x21f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x129 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ebe; op2val:0x461f; +op3val:0x7929; valaddr_reg:x1; val_offset:1038*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1038*FLEN/8, x4, x2, x3) + +inst_382: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2be and fs2 == 0 and fe2 == 0x11 and fm2 == 0x21f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x129 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ebe; op2val:0x461f; +op3val:0x7929; valaddr_reg:x1; val_offset:1041*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1041*FLEN/8, x4, x2, x3) + +inst_383: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2be and fs2 == 0 and fe2 == 0x11 and fm2 == 0x21f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x129 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ebe; op2val:0x461f; +op3val:0x7929; valaddr_reg:x1; val_offset:1044*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1044*FLEN/8, x4, x2, x3) + +inst_384: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2be and fs2 == 0 and fe2 == 0x11 and fm2 == 0x21f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x129 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ebe; op2val:0x461f; +op3val:0x7929; valaddr_reg:x1; val_offset:1047*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1047*FLEN/8, x4, x2, x3) + +inst_385: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x366 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3c6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x331 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7766; op2val:0x3fc6; +op3val:0x7b31; valaddr_reg:x1; val_offset:1050*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1050*FLEN/8, x4, x2, x3) + +inst_386: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x366 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3c6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x331 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7766; op2val:0x3fc6; +op3val:0x7b31; valaddr_reg:x1; val_offset:1053*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1053*FLEN/8, x4, x2, x3) + +inst_387: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x366 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3c6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x331 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7766; op2val:0x3fc6; +op3val:0x7b31; valaddr_reg:x1; val_offset:1056*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1056*FLEN/8, x4, x2, x3) + +inst_388: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x366 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3c6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x331 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7766; op2val:0x3fc6; +op3val:0x7b31; valaddr_reg:x1; val_offset:1059*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1059*FLEN/8, x4, x2, x3) + +inst_389: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x366 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3c6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x331 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7766; op2val:0x3fc6; +op3val:0x7b31; valaddr_reg:x1; val_offset:1062*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1062*FLEN/8, x4, x2, x3) + +inst_390: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x107 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x075 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x19b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7907; op2val:0x3c75; +op3val:0x799b; valaddr_reg:x1; val_offset:1065*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1065*FLEN/8, x4, x2, x3) + +inst_391: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x107 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x075 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x19b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7907; op2val:0x3c75; +op3val:0x799b; valaddr_reg:x1; val_offset:1068*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1068*FLEN/8, x4, x2, x3) + +inst_392: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x107 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x075 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x19b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7907; op2val:0x3c75; +op3val:0x799b; valaddr_reg:x1; val_offset:1071*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1071*FLEN/8, x4, x2, x3) + +inst_393: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x107 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x075 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x19b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7907; op2val:0x3c75; +op3val:0x799b; valaddr_reg:x1; val_offset:1074*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1074*FLEN/8, x4, x2, x3) + +inst_394: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x107 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x075 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x19b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7907; op2val:0x3c75; +op3val:0x799b; valaddr_reg:x1; val_offset:1077*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1077*FLEN/8, x4, x2, x3) + +inst_395: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x010 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x28e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7010; op2val:0x468e; +op3val:0x7aa8; valaddr_reg:x1; val_offset:1080*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1080*FLEN/8, x4, x2, x3) + +inst_396: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x010 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x28e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7010; op2val:0x468e; +op3val:0x7aa8; valaddr_reg:x1; val_offset:1083*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1083*FLEN/8, x4, x2, x3) + +inst_397: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x010 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x28e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7010; op2val:0x468e; +op3val:0x7aa8; valaddr_reg:x1; val_offset:1086*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1086*FLEN/8, x4, x2, x3) + +inst_398: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x010 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x28e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7010; op2val:0x468e; +op3val:0x7aa8; valaddr_reg:x1; val_offset:1089*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1089*FLEN/8, x4, x2, x3) + +inst_399: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x010 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x28e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7010; op2val:0x468e; +op3val:0x7aa8; valaddr_reg:x1; val_offset:1092*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1092*FLEN/8, x4, x2, x3) + +inst_400: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x158 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x365 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0f1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d58; op2val:0x4765; +op3val:0x78f1; valaddr_reg:x1; val_offset:1095*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1095*FLEN/8, x4, x2, x3) + +inst_401: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x158 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x365 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0f1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d58; op2val:0x4765; +op3val:0x78f1; valaddr_reg:x1; val_offset:1098*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1098*FLEN/8, x4, x2, x3) + +inst_402: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x158 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x365 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0f1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d58; op2val:0x4765; +op3val:0x78f1; valaddr_reg:x1; val_offset:1101*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1101*FLEN/8, x4, x2, x3) + +inst_403: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x158 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x365 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0f1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d58; op2val:0x4765; +op3val:0x78f1; valaddr_reg:x1; val_offset:1104*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1104*FLEN/8, x4, x2, x3) + +inst_404: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x158 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x365 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0f1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d58; op2val:0x4765; +op3val:0x78f1; valaddr_reg:x1; val_offset:1107*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1107*FLEN/8, x4, x2, x3) + +inst_405: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x349 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3f7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x342 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b49; op2val:0x3bf7; +op3val:0x7b42; valaddr_reg:x1; val_offset:1110*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1110*FLEN/8, x4, x2, x3) + +inst_406: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x349 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3f7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x342 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b49; op2val:0x3bf7; +op3val:0x7b42; valaddr_reg:x1; val_offset:1113*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1113*FLEN/8, x4, x2, x3) + +inst_407: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x349 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3f7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x342 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b49; op2val:0x3bf7; +op3val:0x7b42; valaddr_reg:x1; val_offset:1116*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1116*FLEN/8, x4, x2, x3) + +inst_408: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x349 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3f7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x342 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b49; op2val:0x3bf7; +op3val:0x7b42; valaddr_reg:x1; val_offset:1119*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1119*FLEN/8, x4, x2, x3) + +inst_409: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x349 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3f7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x342 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b49; op2val:0x3bf7; +op3val:0x7b42; valaddr_reg:x1; val_offset:1122*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1122*FLEN/8, x4, x2, x3) + +inst_410: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x324 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x00c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x33a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b24; op2val:0x380c; +op3val:0x773a; valaddr_reg:x1; val_offset:1125*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1125*FLEN/8, x4, x2, x3) + +inst_411: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x324 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x00c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x33a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b24; op2val:0x380c; +op3val:0x773a; valaddr_reg:x1; val_offset:1128*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1128*FLEN/8, x4, x2, x3) +RVTEST_SIGBASE(x2,signature_x2_3) + +inst_412: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x324 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x00c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x33a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b24; op2val:0x380c; +op3val:0x773a; valaddr_reg:x1; val_offset:1131*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1131*FLEN/8, x4, x2, x3) + +inst_413: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x324 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x00c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x33a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b24; op2val:0x380c; +op3val:0x773a; valaddr_reg:x1; val_offset:1134*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1134*FLEN/8, x4, x2, x3) + +inst_414: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x324 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x00c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x33a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b24; op2val:0x380c; +op3val:0x773a; valaddr_reg:x1; val_offset:1137*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1137*FLEN/8, x4, x2, x3) + +inst_415: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x18c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x08f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x253 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x798c; op2val:0x3c8f; +op3val:0x7a53; valaddr_reg:x1; val_offset:1140*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1140*FLEN/8, x4, x2, x3) + +inst_416: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x18c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x08f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x253 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x798c; op2val:0x3c8f; +op3val:0x7a53; valaddr_reg:x1; val_offset:1143*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1143*FLEN/8, x4, x2, x3) + +inst_417: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x18c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x08f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x253 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x798c; op2val:0x3c8f; +op3val:0x7a53; valaddr_reg:x1; val_offset:1146*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1146*FLEN/8, x4, x2, x3) + +inst_418: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x18c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x08f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x253 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x798c; op2val:0x3c8f; +op3val:0x7a53; valaddr_reg:x1; val_offset:1149*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1149*FLEN/8, x4, x2, x3) + +inst_419: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x18c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x08f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x253 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x798c; op2val:0x3c8f; +op3val:0x7a53; valaddr_reg:x1; val_offset:1152*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1152*FLEN/8, x4, x2, x3) + +inst_420: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x062 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x2e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x38b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7062; op2val:0x46e1; +op3val:0x7b8b; valaddr_reg:x1; val_offset:1155*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1155*FLEN/8, x4, x2, x3) + +inst_421: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x062 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x2e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x38b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7062; op2val:0x46e1; +op3val:0x7b8b; valaddr_reg:x1; val_offset:1158*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1158*FLEN/8, x4, x2, x3) + +inst_422: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x062 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x2e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x38b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7062; op2val:0x46e1; +op3val:0x7b8b; valaddr_reg:x1; val_offset:1161*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1161*FLEN/8, x4, x2, x3) + +inst_423: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x062 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x2e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x38b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7062; op2val:0x46e1; +op3val:0x7b8b; valaddr_reg:x1; val_offset:1164*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1164*FLEN/8, x4, x2, x3) + +inst_424: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x062 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x2e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x38b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7062; op2val:0x46e1; +op3val:0x7b8b; valaddr_reg:x1; val_offset:1167*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1167*FLEN/8, x4, x2, x3) + +inst_425: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x344 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3c3 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x30d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b44; op2val:0x37c3; +op3val:0x770d; valaddr_reg:x1; val_offset:1170*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1170*FLEN/8, x4, x2, x3) + +inst_426: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x344 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3c3 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x30d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b44; op2val:0x37c3; +op3val:0x770d; valaddr_reg:x1; val_offset:1173*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1173*FLEN/8, x4, x2, x3) + +inst_427: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x344 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3c3 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x30d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b44; op2val:0x37c3; +op3val:0x770d; valaddr_reg:x1; val_offset:1176*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1176*FLEN/8, x4, x2, x3) + +inst_428: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x344 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3c3 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x30d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b44; op2val:0x37c3; +op3val:0x770d; valaddr_reg:x1; val_offset:1179*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1179*FLEN/8, x4, x2, x3) + +inst_429: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x344 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3c3 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x30d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b44; op2val:0x37c3; +op3val:0x770d; valaddr_reg:x1; val_offset:1182*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1182*FLEN/8, x4, x2, x3) + +inst_430: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x239 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x098 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x326 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a39; op2val:0x3898; +op3val:0x7726; valaddr_reg:x1; val_offset:1185*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1185*FLEN/8, x4, x2, x3) + +inst_431: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x239 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x098 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x326 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a39; op2val:0x3898; +op3val:0x7726; valaddr_reg:x1; val_offset:1188*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1188*FLEN/8, x4, x2, x3) + +inst_432: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x239 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x098 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x326 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a39; op2val:0x3898; +op3val:0x7726; valaddr_reg:x1; val_offset:1191*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1191*FLEN/8, x4, x2, x3) + +inst_433: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x239 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x098 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x326 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a39; op2val:0x3898; +op3val:0x7726; valaddr_reg:x1; val_offset:1194*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1194*FLEN/8, x4, x2, x3) + +inst_434: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x239 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x098 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x326 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a39; op2val:0x3898; +op3val:0x7726; valaddr_reg:x1; val_offset:1197*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1197*FLEN/8, x4, x2, x3) + +inst_435: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x06b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x127 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1b2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x746b; op2val:0x4127; +op3val:0x79b2; valaddr_reg:x1; val_offset:1200*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1200*FLEN/8, x4, x2, x3) + +inst_436: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x06b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x127 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1b2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x746b; op2val:0x4127; +op3val:0x79b2; valaddr_reg:x1; val_offset:1203*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1203*FLEN/8, x4, x2, x3) + +inst_437: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x06b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x127 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1b2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x746b; op2val:0x4127; +op3val:0x79b2; valaddr_reg:x1; val_offset:1206*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1206*FLEN/8, x4, x2, x3) + +inst_438: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x06b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x127 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1b2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x746b; op2val:0x4127; +op3val:0x79b2; valaddr_reg:x1; val_offset:1209*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1209*FLEN/8, x4, x2, x3) + +inst_439: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x06b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x127 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1b2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x746b; op2val:0x4127; +op3val:0x79b2; valaddr_reg:x1; val_offset:1212*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1212*FLEN/8, x4, x2, x3) + +inst_440: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x012 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x248 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x266 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c12; op2val:0x4a48; +op3val:0x7a66; valaddr_reg:x1; val_offset:1215*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1215*FLEN/8, x4, x2, x3) + +inst_441: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x012 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x248 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x266 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c12; op2val:0x4a48; +op3val:0x7a66; valaddr_reg:x1; val_offset:1218*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1218*FLEN/8, x4, x2, x3) + +inst_442: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x012 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x248 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x266 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c12; op2val:0x4a48; +op3val:0x7a66; valaddr_reg:x1; val_offset:1221*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1221*FLEN/8, x4, x2, x3) + +inst_443: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x012 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x248 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x266 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c12; op2val:0x4a48; +op3val:0x7a66; valaddr_reg:x1; val_offset:1224*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1224*FLEN/8, x4, x2, x3) + +inst_444: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x012 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x248 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x266 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c12; op2val:0x4a48; +op3val:0x7a66; valaddr_reg:x1; val_offset:1227*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1227*FLEN/8, x4, x2, x3) + +inst_445: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d2 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0ae and fs3 == 0 and fe3 == 0x1d and fm3 == 0x093 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd2; op2val:0x34ae; +op3val:0x7493; valaddr_reg:x1; val_offset:1230*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1230*FLEN/8, x4, x2, x3) + +inst_446: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d2 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0ae and fs3 == 0 and fe3 == 0x1d and fm3 == 0x093 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd2; op2val:0x34ae; +op3val:0x7493; valaddr_reg:x1; val_offset:1233*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1233*FLEN/8, x4, x2, x3) + +inst_447: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d2 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0ae and fs3 == 0 and fe3 == 0x1d and fm3 == 0x093 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd2; op2val:0x34ae; +op3val:0x7493; valaddr_reg:x1; val_offset:1236*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1236*FLEN/8, x4, x2, x3) + +inst_448: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d2 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0ae and fs3 == 0 and fe3 == 0x1d and fm3 == 0x093 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd2; op2val:0x34ae; +op3val:0x7493; valaddr_reg:x1; val_offset:1239*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1239*FLEN/8, x4, x2, x3) + +inst_449: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d2 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0ae and fs3 == 0 and fe3 == 0x1d and fm3 == 0x093 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd2; op2val:0x34ae; +op3val:0x7493; valaddr_reg:x1; val_offset:1242*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1242*FLEN/8, x4, x2, x3) + +inst_450: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x383 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x1b3 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x15a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b83; op2val:0x2db3; +op3val:0x6d5a; valaddr_reg:x1; val_offset:1245*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1245*FLEN/8, x4, x2, x3) + +inst_451: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x383 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x1b3 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x15a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b83; op2val:0x2db3; +op3val:0x6d5a; valaddr_reg:x1; val_offset:1248*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1248*FLEN/8, x4, x2, x3) + +inst_452: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x383 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x1b3 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x15a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b83; op2val:0x2db3; +op3val:0x6d5a; valaddr_reg:x1; val_offset:1251*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1251*FLEN/8, x4, x2, x3) + +inst_453: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x383 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x1b3 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x15a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b83; op2val:0x2db3; +op3val:0x6d5a; valaddr_reg:x1; val_offset:1254*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1254*FLEN/8, x4, x2, x3) + +inst_454: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x383 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x1b3 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x15a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b83; op2val:0x2db3; +op3val:0x6d5a; valaddr_reg:x1; val_offset:1257*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1257*FLEN/8, x4, x2, x3) + +inst_455: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2dc and fs2 == 0 and fe2 == 0x0d and fm2 == 0x137 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x079 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7adc; op2val:0x3537; +op3val:0x7479; valaddr_reg:x1; val_offset:1260*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1260*FLEN/8, x4, x2, x3) + +inst_456: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2dc and fs2 == 0 and fe2 == 0x0d and fm2 == 0x137 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x079 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7adc; op2val:0x3537; +op3val:0x7479; valaddr_reg:x1; val_offset:1263*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1263*FLEN/8, x4, x2, x3) + +inst_457: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2dc and fs2 == 0 and fe2 == 0x0d and fm2 == 0x137 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x079 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7adc; op2val:0x3537; +op3val:0x7479; valaddr_reg:x1; val_offset:1266*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1266*FLEN/8, x4, x2, x3) + +inst_458: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2dc and fs2 == 0 and fe2 == 0x0d and fm2 == 0x137 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x079 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7adc; op2val:0x3537; +op3val:0x7479; valaddr_reg:x1; val_offset:1269*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1269*FLEN/8, x4, x2, x3) + +inst_459: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2dc and fs2 == 0 and fe2 == 0x0d and fm2 == 0x137 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x079 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7adc; op2val:0x3537; +op3val:0x7479; valaddr_reg:x1; val_offset:1272*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1272*FLEN/8, x4, x2, x3) + +inst_460: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b9 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x321 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2e3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bb9; op2val:0x3721; +op3val:0x76e3; valaddr_reg:x1; val_offset:1275*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1275*FLEN/8, x4, x2, x3) + +inst_461: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b9 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x321 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2e3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bb9; op2val:0x3721; +op3val:0x76e3; valaddr_reg:x1; val_offset:1278*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1278*FLEN/8, x4, x2, x3) + +inst_462: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b9 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x321 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2e3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bb9; op2val:0x3721; +op3val:0x76e3; valaddr_reg:x1; val_offset:1281*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1281*FLEN/8, x4, x2, x3) + +inst_463: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b9 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x321 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2e3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bb9; op2val:0x3721; +op3val:0x76e3; valaddr_reg:x1; val_offset:1284*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1284*FLEN/8, x4, x2, x3) + +inst_464: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b9 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x321 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2e3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bb9; op2val:0x3721; +op3val:0x76e3; valaddr_reg:x1; val_offset:1287*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1287*FLEN/8, x4, x2, x3) + +inst_465: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x35f and fs2 == 0 and fe2 == 0x0a and fm2 == 0x06e and fs3 == 0 and fe3 == 0x1a and fm3 == 0x015 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b5f; op2val:0x286e; +op3val:0x6815; valaddr_reg:x1; val_offset:1290*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1290*FLEN/8, x4, x2, x3) + +inst_466: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x35f and fs2 == 0 and fe2 == 0x0a and fm2 == 0x06e and fs3 == 0 and fe3 == 0x1a and fm3 == 0x015 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b5f; op2val:0x286e; +op3val:0x6815; valaddr_reg:x1; val_offset:1293*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1293*FLEN/8, x4, x2, x3) + +inst_467: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x35f and fs2 == 0 and fe2 == 0x0a and fm2 == 0x06e and fs3 == 0 and fe3 == 0x1a and fm3 == 0x015 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b5f; op2val:0x286e; +op3val:0x6815; valaddr_reg:x1; val_offset:1296*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1296*FLEN/8, x4, x2, x3) + +inst_468: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x35f and fs2 == 0 and fe2 == 0x0a and fm2 == 0x06e and fs3 == 0 and fe3 == 0x1a and fm3 == 0x015 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b5f; op2val:0x286e; +op3val:0x6815; valaddr_reg:x1; val_offset:1299*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1299*FLEN/8, x4, x2, x3) + +inst_469: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x35f and fs2 == 0 and fe2 == 0x0a and fm2 == 0x06e and fs3 == 0 and fe3 == 0x1a and fm3 == 0x015 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b5f; op2val:0x286e; +op3val:0x6815; valaddr_reg:x1; val_offset:1302*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1302*FLEN/8, x4, x2, x3) + +inst_470: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x17a and fs2 == 0 and fe2 == 0x12 and fm2 == 0x0c3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x287 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d7a; op2val:0x48c3; +op3val:0x7a87; valaddr_reg:x1; val_offset:1305*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1305*FLEN/8, x4, x2, x3) + +inst_471: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x17a and fs2 == 0 and fe2 == 0x12 and fm2 == 0x0c3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x287 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d7a; op2val:0x48c3; +op3val:0x7a87; valaddr_reg:x1; val_offset:1308*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1308*FLEN/8, x4, x2, x3) + +inst_472: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x17a and fs2 == 0 and fe2 == 0x12 and fm2 == 0x0c3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x287 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d7a; op2val:0x48c3; +op3val:0x7a87; valaddr_reg:x1; val_offset:1311*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1311*FLEN/8, x4, x2, x3) + +inst_473: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x17a and fs2 == 0 and fe2 == 0x12 and fm2 == 0x0c3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x287 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d7a; op2val:0x48c3; +op3val:0x7a87; valaddr_reg:x1; val_offset:1314*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1314*FLEN/8, x4, x2, x3) + +inst_474: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x17a and fs2 == 0 and fe2 == 0x12 and fm2 == 0x0c3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x287 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d7a; op2val:0x48c3; +op3val:0x7a87; valaddr_reg:x1; val_offset:1317*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1317*FLEN/8, x4, x2, x3) + +inst_475: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x11b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2b5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x048 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x791b; op2val:0x3ab5; +op3val:0x7848; valaddr_reg:x1; val_offset:1320*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1320*FLEN/8, x4, x2, x3) + +inst_476: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x11b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2b5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x048 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x791b; op2val:0x3ab5; +op3val:0x7848; valaddr_reg:x1; val_offset:1323*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1323*FLEN/8, x4, x2, x3) + +inst_477: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x11b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2b5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x048 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x791b; op2val:0x3ab5; +op3val:0x7848; valaddr_reg:x1; val_offset:1326*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1326*FLEN/8, x4, x2, x3) + +inst_478: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x11b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2b5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x048 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x791b; op2val:0x3ab5; +op3val:0x7848; valaddr_reg:x1; val_offset:1329*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1329*FLEN/8, x4, x2, x3) + +inst_479: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x11b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2b5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x048 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x791b; op2val:0x3ab5; +op3val:0x7848; valaddr_reg:x1; val_offset:1332*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1332*FLEN/8, x4, x2, x3) + +inst_480: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x02f and fs2 == 0 and fe2 == 0x11 and fm2 == 0x14b and fs3 == 0 and fe3 == 0x1c and fm3 == 0x18b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x682f; op2val:0x454b; +op3val:0x718b; valaddr_reg:x1; val_offset:1335*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1335*FLEN/8, x4, x2, x3) + +inst_481: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x02f and fs2 == 0 and fe2 == 0x11 and fm2 == 0x14b and fs3 == 0 and fe3 == 0x1c and fm3 == 0x18b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x682f; op2val:0x454b; +op3val:0x718b; valaddr_reg:x1; val_offset:1338*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1338*FLEN/8, x4, x2, x3) + +inst_482: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x02f and fs2 == 0 and fe2 == 0x11 and fm2 == 0x14b and fs3 == 0 and fe3 == 0x1c and fm3 == 0x18b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x682f; op2val:0x454b; +op3val:0x718b; valaddr_reg:x1; val_offset:1341*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1341*FLEN/8, x4, x2, x3) + +inst_483: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x02f and fs2 == 0 and fe2 == 0x11 and fm2 == 0x14b and fs3 == 0 and fe3 == 0x1c and fm3 == 0x18b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x682f; op2val:0x454b; +op3val:0x718b; valaddr_reg:x1; val_offset:1344*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1344*FLEN/8, x4, x2, x3) + +inst_484: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x02f and fs2 == 0 and fe2 == 0x11 and fm2 == 0x14b and fs3 == 0 and fe3 == 0x1c and fm3 == 0x18b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x682f; op2val:0x454b; +op3val:0x718b; valaddr_reg:x1; val_offset:1347*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1347*FLEN/8, x4, x2, x3) + +inst_485: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ec and fs2 == 0 and fe2 == 0x0c and fm2 == 0x07f and fs3 == 0 and fe3 == 0x1a and fm3 == 0x2a9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75ec; op2val:0x307f; +op3val:0x6aa9; valaddr_reg:x1; val_offset:1350*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1350*FLEN/8, x4, x2, x3) + +inst_486: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ec and fs2 == 0 and fe2 == 0x0c and fm2 == 0x07f and fs3 == 0 and fe3 == 0x1a and fm3 == 0x2a9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75ec; op2val:0x307f; +op3val:0x6aa9; valaddr_reg:x1; val_offset:1353*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1353*FLEN/8, x4, x2, x3) + +inst_487: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ec and fs2 == 0 and fe2 == 0x0c and fm2 == 0x07f and fs3 == 0 and fe3 == 0x1a and fm3 == 0x2a9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75ec; op2val:0x307f; +op3val:0x6aa9; valaddr_reg:x1; val_offset:1356*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1356*FLEN/8, x4, x2, x3) + +inst_488: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ec and fs2 == 0 and fe2 == 0x0c and fm2 == 0x07f and fs3 == 0 and fe3 == 0x1a and fm3 == 0x2a9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75ec; op2val:0x307f; +op3val:0x6aa9; valaddr_reg:x1; val_offset:1359*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1359*FLEN/8, x4, x2, x3) + +inst_489: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ec and fs2 == 0 and fe2 == 0x0c and fm2 == 0x07f and fs3 == 0 and fe3 == 0x1a and fm3 == 0x2a9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75ec; op2val:0x307f; +op3val:0x6aa9; valaddr_reg:x1; val_offset:1362*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1362*FLEN/8, x4, x2, x3) + +inst_490: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x22a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x21e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bf0; op2val:0x3a2a; +op3val:0x7a1e; valaddr_reg:x1; val_offset:1365*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1365*FLEN/8, x4, x2, x3) + +inst_491: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x22a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x21e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bf0; op2val:0x3a2a; +op3val:0x7a1e; valaddr_reg:x1; val_offset:1368*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1368*FLEN/8, x4, x2, x3) + +inst_492: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x22a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x21e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bf0; op2val:0x3a2a; +op3val:0x7a1e; valaddr_reg:x1; val_offset:1371*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1371*FLEN/8, x4, x2, x3) + +inst_493: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x22a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x21e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bf0; op2val:0x3a2a; +op3val:0x7a1e; valaddr_reg:x1; val_offset:1374*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1374*FLEN/8, x4, x2, x3) + +inst_494: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x22a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x21e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bf0; op2val:0x3a2a; +op3val:0x7a1e; valaddr_reg:x1; val_offset:1377*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1377*FLEN/8, x4, x2, x3) + +inst_495: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x398 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1e6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x19a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b98; op2val:0x39e6; +op3val:0x799a; valaddr_reg:x1; val_offset:1380*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1380*FLEN/8, x4, x2, x3) + +inst_496: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x398 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1e6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x19a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b98; op2val:0x39e6; +op3val:0x799a; valaddr_reg:x1; val_offset:1383*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1383*FLEN/8, x4, x2, x3) + +inst_497: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x398 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1e6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x19a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b98; op2val:0x39e6; +op3val:0x799a; valaddr_reg:x1; val_offset:1386*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1386*FLEN/8, x4, x2, x3) + +inst_498: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x398 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1e6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x19a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b98; op2val:0x39e6; +op3val:0x799a; valaddr_reg:x1; val_offset:1389*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1389*FLEN/8, x4, x2, x3) + +inst_499: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x398 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1e6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x19a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b98; op2val:0x39e6; +op3val:0x799a; valaddr_reg:x1; val_offset:1392*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1392*FLEN/8, x4, x2, x3) + +inst_500: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x17e and fs2 == 0 and fe2 == 0x0c and fm2 == 0x33a and fs3 == 0 and fe3 == 0x1b and fm3 == 0x0f6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x757e; op2val:0x333a; +op3val:0x6cf6; valaddr_reg:x1; val_offset:1395*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1395*FLEN/8, x4, x2, x3) + +inst_501: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x17e and fs2 == 0 and fe2 == 0x0c and fm2 == 0x33a and fs3 == 0 and fe3 == 0x1b and fm3 == 0x0f6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x757e; op2val:0x333a; +op3val:0x6cf6; valaddr_reg:x1; val_offset:1398*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1398*FLEN/8, x4, x2, x3) + +inst_502: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x17e and fs2 == 0 and fe2 == 0x0c and fm2 == 0x33a and fs3 == 0 and fe3 == 0x1b and fm3 == 0x0f6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x757e; op2val:0x333a; +op3val:0x6cf6; valaddr_reg:x1; val_offset:1401*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1401*FLEN/8, x4, x2, x3) + +inst_503: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x17e and fs2 == 0 and fe2 == 0x0c and fm2 == 0x33a and fs3 == 0 and fe3 == 0x1b and fm3 == 0x0f6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x757e; op2val:0x333a; +op3val:0x6cf6; valaddr_reg:x1; val_offset:1404*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1404*FLEN/8, x4, x2, x3) + +inst_504: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x17e and fs2 == 0 and fe2 == 0x0c and fm2 == 0x33a and fs3 == 0 and fe3 == 0x1b and fm3 == 0x0f6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x757e; op2val:0x333a; +op3val:0x6cf6; valaddr_reg:x1; val_offset:1407*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1407*FLEN/8, x4, x2, x3) + +inst_505: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d9 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0fd and fs3 == 0 and fe3 == 0x1b and fm3 == 0x34b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79d9; op2val:0x30fd; +op3val:0x6f4b; valaddr_reg:x1; val_offset:1410*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1410*FLEN/8, x4, x2, x3) + +inst_506: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d9 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0fd and fs3 == 0 and fe3 == 0x1b and fm3 == 0x34b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79d9; op2val:0x30fd; +op3val:0x6f4b; valaddr_reg:x1; val_offset:1413*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1413*FLEN/8, x4, x2, x3) + +inst_507: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d9 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0fd and fs3 == 0 and fe3 == 0x1b and fm3 == 0x34b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79d9; op2val:0x30fd; +op3val:0x6f4b; valaddr_reg:x1; val_offset:1416*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1416*FLEN/8, x4, x2, x3) + +inst_508: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d9 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0fd and fs3 == 0 and fe3 == 0x1b and fm3 == 0x34b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79d9; op2val:0x30fd; +op3val:0x6f4b; valaddr_reg:x1; val_offset:1419*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1419*FLEN/8, x4, x2, x3) + +inst_509: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d9 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0fd and fs3 == 0 and fe3 == 0x1b and fm3 == 0x34b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79d9; op2val:0x30fd; +op3val:0x6f4b; valaddr_reg:x1; val_offset:1422*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1422*FLEN/8, x4, x2, x3) + +inst_510: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x05f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2c9 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x36b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x785f; op2val:0x3ac9; +op3val:0x776b; valaddr_reg:x1; val_offset:1425*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1425*FLEN/8, x4, x2, x3) + +inst_511: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x05f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2c9 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x36b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x785f; op2val:0x3ac9; +op3val:0x776b; valaddr_reg:x1; val_offset:1428*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1428*FLEN/8, x4, x2, x3) + +inst_512: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x05f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2c9 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x36b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x785f; op2val:0x3ac9; +op3val:0x776b; valaddr_reg:x1; val_offset:1431*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1431*FLEN/8, x4, x2, x3) + +inst_513: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x05f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2c9 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x36b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x785f; op2val:0x3ac9; +op3val:0x776b; valaddr_reg:x1; val_offset:1434*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1434*FLEN/8, x4, x2, x3) + +inst_514: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x05f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2c9 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x36b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x785f; op2val:0x3ac9; +op3val:0x776b; valaddr_reg:x1; val_offset:1437*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1437*FLEN/8, x4, x2, x3) + +inst_515: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3e8 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0dd and fs3 == 0 and fe3 == 0x1b and fm3 == 0x0cf and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77e8; op2val:0x30dd; +op3val:0x6ccf; valaddr_reg:x1; val_offset:1440*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1440*FLEN/8, x4, x2, x3) + +inst_516: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3e8 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0dd and fs3 == 0 and fe3 == 0x1b and fm3 == 0x0cf and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77e8; op2val:0x30dd; +op3val:0x6ccf; valaddr_reg:x1; val_offset:1443*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1443*FLEN/8, x4, x2, x3) + +inst_517: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3e8 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0dd and fs3 == 0 and fe3 == 0x1b and fm3 == 0x0cf and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77e8; op2val:0x30dd; +op3val:0x6ccf; valaddr_reg:x1; val_offset:1446*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1446*FLEN/8, x4, x2, x3) + +inst_518: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3e8 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0dd and fs3 == 0 and fe3 == 0x1b and fm3 == 0x0cf and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77e8; op2val:0x30dd; +op3val:0x6ccf; valaddr_reg:x1; val_offset:1449*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1449*FLEN/8, x4, x2, x3) + +inst_519: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3e8 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0dd and fs3 == 0 and fe3 == 0x1b and fm3 == 0x0cf and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77e8; op2val:0x30dd; +op3val:0x6ccf; valaddr_reg:x1; val_offset:1452*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1452*FLEN/8, x4, x2, x3) + +inst_520: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0bb and fs2 == 0 and fe2 == 0x11 and fm2 == 0x308 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x029 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6cbb; op2val:0x4708; +op3val:0x7829; valaddr_reg:x1; val_offset:1455*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1455*FLEN/8, x4, x2, x3) + +inst_521: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0bb and fs2 == 0 and fe2 == 0x11 and fm2 == 0x308 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x029 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6cbb; op2val:0x4708; +op3val:0x7829; valaddr_reg:x1; val_offset:1458*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1458*FLEN/8, x4, x2, x3) + +inst_522: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0bb and fs2 == 0 and fe2 == 0x11 and fm2 == 0x308 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x029 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6cbb; op2val:0x4708; +op3val:0x7829; valaddr_reg:x1; val_offset:1461*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1461*FLEN/8, x4, x2, x3) + +inst_523: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0bb and fs2 == 0 and fe2 == 0x11 and fm2 == 0x308 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x029 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6cbb; op2val:0x4708; +op3val:0x7829; valaddr_reg:x1; val_offset:1464*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1464*FLEN/8, x4, x2, x3) + +inst_524: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0bb and fs2 == 0 and fe2 == 0x11 and fm2 == 0x308 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x029 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6cbb; op2val:0x4708; +op3val:0x7829; valaddr_reg:x1; val_offset:1467*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1467*FLEN/8, x4, x2, x3) + +inst_525: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x3cd and fs2 == 0 and fe2 == 0x13 and fm2 == 0x04e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x033 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x67cd; op2val:0x4c4e; +op3val:0x7833; valaddr_reg:x1; val_offset:1470*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1470*FLEN/8, x4, x2, x3) + +inst_526: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x3cd and fs2 == 0 and fe2 == 0x13 and fm2 == 0x04e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x033 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x67cd; op2val:0x4c4e; +op3val:0x7833; valaddr_reg:x1; val_offset:1473*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1473*FLEN/8, x4, x2, x3) + +inst_527: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x3cd and fs2 == 0 and fe2 == 0x13 and fm2 == 0x04e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x033 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x67cd; op2val:0x4c4e; +op3val:0x7833; valaddr_reg:x1; val_offset:1476*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1476*FLEN/8, x4, x2, x3) + +inst_528: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x3cd and fs2 == 0 and fe2 == 0x13 and fm2 == 0x04e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x033 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x67cd; op2val:0x4c4e; +op3val:0x7833; valaddr_reg:x1; val_offset:1479*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1479*FLEN/8, x4, x2, x3) + +inst_529: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x3cd and fs2 == 0 and fe2 == 0x13 and fm2 == 0x04e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x033 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x67cd; op2val:0x4c4e; +op3val:0x7833; valaddr_reg:x1; val_offset:1482*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1482*FLEN/8, x4, x2, x3) + +inst_530: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0ce and fs2 == 0 and fe2 == 0x0f and fm2 == 0x37f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x081 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70ce; op2val:0x3f7f; +op3val:0x7481; valaddr_reg:x1; val_offset:1485*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1485*FLEN/8, x4, x2, x3) + +inst_531: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0ce and fs2 == 0 and fe2 == 0x0f and fm2 == 0x37f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x081 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70ce; op2val:0x3f7f; +op3val:0x7481; valaddr_reg:x1; val_offset:1488*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1488*FLEN/8, x4, x2, x3) + +inst_532: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0ce and fs2 == 0 and fe2 == 0x0f and fm2 == 0x37f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x081 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70ce; op2val:0x3f7f; +op3val:0x7481; valaddr_reg:x1; val_offset:1491*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1491*FLEN/8, x4, x2, x3) + +inst_533: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0ce and fs2 == 0 and fe2 == 0x0f and fm2 == 0x37f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x081 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70ce; op2val:0x3f7f; +op3val:0x7481; valaddr_reg:x1; val_offset:1494*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1494*FLEN/8, x4, x2, x3) + +inst_534: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0ce and fs2 == 0 and fe2 == 0x0f and fm2 == 0x37f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x081 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70ce; op2val:0x3f7f; +op3val:0x7481; valaddr_reg:x1; val_offset:1497*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1497*FLEN/8, x4, x2, x3) + +inst_535: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0d4 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x387 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x08b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70d4; op2val:0x4387; +op3val:0x788b; valaddr_reg:x1; val_offset:1500*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1500*FLEN/8, x4, x2, x3) + +inst_536: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0d4 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x387 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x08b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70d4; op2val:0x4387; +op3val:0x788b; valaddr_reg:x1; val_offset:1503*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1503*FLEN/8, x4, x2, x3) + +inst_537: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0d4 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x387 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x08b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70d4; op2val:0x4387; +op3val:0x788b; valaddr_reg:x1; val_offset:1506*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1506*FLEN/8, x4, x2, x3) + +inst_538: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0d4 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x387 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x08b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70d4; op2val:0x4387; +op3val:0x788b; valaddr_reg:x1; val_offset:1509*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1509*FLEN/8, x4, x2, x3) + +inst_539: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0d4 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x387 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x08b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70d4; op2val:0x4387; +op3val:0x788b; valaddr_reg:x1; val_offset:1512*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1512*FLEN/8, x4, x2, x3) +RVTEST_SIGBASE(x2,signature_x2_4) + +inst_540: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x235 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x098 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x322 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7635; op2val:0x3898; +op3val:0x7322; valaddr_reg:x1; val_offset:1515*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1515*FLEN/8, x4, x2, x3) + +inst_541: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x235 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x098 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x322 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7635; op2val:0x3898; +op3val:0x7322; valaddr_reg:x1; val_offset:1518*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1518*FLEN/8, x4, x2, x3) + +inst_542: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x235 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x098 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x322 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7635; op2val:0x3898; +op3val:0x7322; valaddr_reg:x1; val_offset:1521*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1521*FLEN/8, x4, x2, x3) + +inst_543: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x235 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x098 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x322 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7635; op2val:0x3898; +op3val:0x7322; valaddr_reg:x1; val_offset:1524*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1524*FLEN/8, x4, x2, x3) + +inst_544: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x235 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x098 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x322 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7635; op2val:0x3898; +op3val:0x7322; valaddr_reg:x1; val_offset:1527*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1527*FLEN/8, x4, x2, x3) + +inst_545: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x316 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x117 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x082 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7316; op2val:0x4117; +op3val:0x7882; valaddr_reg:x1; val_offset:1530*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1530*FLEN/8, x4, x2, x3) + +inst_546: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x316 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x117 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x082 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7316; op2val:0x4117; +op3val:0x7882; valaddr_reg:x1; val_offset:1533*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1533*FLEN/8, x4, x2, x3) + +inst_547: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x316 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x117 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x082 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7316; op2val:0x4117; +op3val:0x7882; valaddr_reg:x1; val_offset:1536*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1536*FLEN/8, x4, x2, x3) + +inst_548: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x316 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x117 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x082 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7316; op2val:0x4117; +op3val:0x7882; valaddr_reg:x1; val_offset:1539*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1539*FLEN/8, x4, x2, x3) + +inst_549: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x316 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x117 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x082 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7316; op2val:0x4117; +op3val:0x7882; valaddr_reg:x1; val_offset:1542*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1542*FLEN/8, x4, x2, x3) + +inst_550: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x347 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x35d and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2b3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b47; op2val:0x375d; +op3val:0x76b3; valaddr_reg:x1; val_offset:1545*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1545*FLEN/8, x4, x2, x3) + +inst_551: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x347 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x35d and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2b3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b47; op2val:0x375d; +op3val:0x76b3; valaddr_reg:x1; val_offset:1548*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1548*FLEN/8, x4, x2, x3) + +inst_552: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x347 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x35d and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2b3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b47; op2val:0x375d; +op3val:0x76b3; valaddr_reg:x1; val_offset:1551*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1551*FLEN/8, x4, x2, x3) + +inst_553: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x347 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x35d and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2b3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b47; op2val:0x375d; +op3val:0x76b3; valaddr_reg:x1; val_offset:1554*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1554*FLEN/8, x4, x2, x3) + +inst_554: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x347 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x35d and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2b3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b47; op2val:0x375d; +op3val:0x76b3; valaddr_reg:x1; val_offset:1557*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1557*FLEN/8, x4, x2, x3) + +inst_555: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x138 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3c1 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x10f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7138; op2val:0x3fc1; +op3val:0x750f; valaddr_reg:x1; val_offset:1560*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1560*FLEN/8, x4, x2, x3) + +inst_556: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x138 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3c1 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x10f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7138; op2val:0x3fc1; +op3val:0x750f; valaddr_reg:x1; val_offset:1563*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1563*FLEN/8, x4, x2, x3) + +inst_557: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x138 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3c1 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x10f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7138; op2val:0x3fc1; +op3val:0x750f; valaddr_reg:x1; val_offset:1566*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1566*FLEN/8, x4, x2, x3) + +inst_558: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x138 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3c1 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x10f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7138; op2val:0x3fc1; +op3val:0x750f; valaddr_reg:x1; val_offset:1569*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1569*FLEN/8, x4, x2, x3) + +inst_559: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x138 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3c1 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x10f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7138; op2val:0x3fc1; +op3val:0x750f; valaddr_reg:x1; val_offset:1572*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1572*FLEN/8, x4, x2, x3) + +inst_560: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3af and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0c3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x093 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73af; op2val:0x40c3; +op3val:0x7893; valaddr_reg:x1; val_offset:1575*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1575*FLEN/8, x4, x2, x3) + +inst_561: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3af and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0c3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x093 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73af; op2val:0x40c3; +op3val:0x7893; valaddr_reg:x1; val_offset:1578*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1578*FLEN/8, x4, x2, x3) + +inst_562: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3af and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0c3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x093 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73af; op2val:0x40c3; +op3val:0x7893; valaddr_reg:x1; val_offset:1581*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1581*FLEN/8, x4, x2, x3) + +inst_563: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3af and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0c3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x093 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73af; op2val:0x40c3; +op3val:0x7893; valaddr_reg:x1; val_offset:1584*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1584*FLEN/8, x4, x2, x3) + +inst_564: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3af and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0c3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x093 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73af; op2val:0x40c3; +op3val:0x7893; valaddr_reg:x1; val_offset:1587*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1587*FLEN/8, x4, x2, x3) + +inst_565: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x249 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1c9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x08c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a49; op2val:0x39c9; +op3val:0x788c; valaddr_reg:x1; val_offset:1590*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1590*FLEN/8, x4, x2, x3) + +inst_566: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x249 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1c9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x08c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a49; op2val:0x39c9; +op3val:0x788c; valaddr_reg:x1; val_offset:1593*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1593*FLEN/8, x4, x2, x3) + +inst_567: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x249 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1c9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x08c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a49; op2val:0x39c9; +op3val:0x788c; valaddr_reg:x1; val_offset:1596*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1596*FLEN/8, x4, x2, x3) + +inst_568: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x249 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1c9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x08c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a49; op2val:0x39c9; +op3val:0x788c; valaddr_reg:x1; val_offset:1599*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1599*FLEN/8, x4, x2, x3) + +inst_569: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x249 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1c9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x08c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a49; op2val:0x39c9; +op3val:0x788c; valaddr_reg:x1; val_offset:1602*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1602*FLEN/8, x4, x2, x3) + +inst_570: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x204 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2ea and fs3 == 0 and fe3 == 0x1d and fm3 == 0x133 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7204; op2val:0x3eea; +op3val:0x7533; valaddr_reg:x1; val_offset:1605*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1605*FLEN/8, x4, x2, x3) + +inst_571: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x204 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2ea and fs3 == 0 and fe3 == 0x1d and fm3 == 0x133 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7204; op2val:0x3eea; +op3val:0x7533; valaddr_reg:x1; val_offset:1608*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1608*FLEN/8, x4, x2, x3) + +inst_572: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x204 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2ea and fs3 == 0 and fe3 == 0x1d and fm3 == 0x133 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7204; op2val:0x3eea; +op3val:0x7533; valaddr_reg:x1; val_offset:1611*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1611*FLEN/8, x4, x2, x3) + +inst_573: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x204 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2ea and fs3 == 0 and fe3 == 0x1d and fm3 == 0x133 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7204; op2val:0x3eea; +op3val:0x7533; valaddr_reg:x1; val_offset:1614*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1614*FLEN/8, x4, x2, x3) + +inst_574: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x204 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2ea and fs3 == 0 and fe3 == 0x1d and fm3 == 0x133 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7204; op2val:0x3eea; +op3val:0x7533; valaddr_reg:x1; val_offset:1617*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1617*FLEN/8, x4, x2, x3) + +inst_575: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x218 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0a0 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x30d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7618; op2val:0x3ca0; +op3val:0x770d; valaddr_reg:x1; val_offset:1620*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1620*FLEN/8, x4, x2, x3) + +inst_576: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x218 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0a0 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x30d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7618; op2val:0x3ca0; +op3val:0x770d; valaddr_reg:x1; val_offset:1623*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1623*FLEN/8, x4, x2, x3) + +inst_577: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x218 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0a0 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x30d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7618; op2val:0x3ca0; +op3val:0x770d; valaddr_reg:x1; val_offset:1626*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1626*FLEN/8, x4, x2, x3) + +inst_578: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x218 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0a0 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x30d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7618; op2val:0x3ca0; +op3val:0x770d; valaddr_reg:x1; val_offset:1629*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1629*FLEN/8, x4, x2, x3) + +inst_579: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x218 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0a0 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x30d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7618; op2val:0x3ca0; +op3val:0x770d; valaddr_reg:x1; val_offset:1632*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1632*FLEN/8, x4, x2, x3) + +inst_580: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x25b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x104 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3f9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x765b; op2val:0x4104; +op3val:0x7bf9; valaddr_reg:x1; val_offset:1635*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1635*FLEN/8, x4, x2, x3) + +inst_581: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x25b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x104 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3f9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x765b; op2val:0x4104; +op3val:0x7bf9; valaddr_reg:x1; val_offset:1638*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1638*FLEN/8, x4, x2, x3) + +inst_582: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x25b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x104 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3f9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x765b; op2val:0x4104; +op3val:0x7bf9; valaddr_reg:x1; val_offset:1641*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1641*FLEN/8, x4, x2, x3) + +inst_583: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x25b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x104 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3f9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x765b; op2val:0x4104; +op3val:0x7bf9; valaddr_reg:x1; val_offset:1644*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1644*FLEN/8, x4, x2, x3) + +inst_584: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x25b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x104 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3f9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x765b; op2val:0x4104; +op3val:0x7bf9; valaddr_reg:x1; val_offset:1647*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1647*FLEN/8, x4, x2, x3) + +inst_585: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x068 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ce and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7868; op2val:0x3cce; +op3val:0x794b; valaddr_reg:x1; val_offset:1650*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1650*FLEN/8, x4, x2, x3) + +inst_586: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x068 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ce and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7868; op2val:0x3cce; +op3val:0x794b; valaddr_reg:x1; val_offset:1653*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1653*FLEN/8, x4, x2, x3) + +inst_587: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x068 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ce and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7868; op2val:0x3cce; +op3val:0x794b; valaddr_reg:x1; val_offset:1656*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1656*FLEN/8, x4, x2, x3) + +inst_588: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x068 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ce and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7868; op2val:0x3cce; +op3val:0x794b; valaddr_reg:x1; val_offset:1659*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1659*FLEN/8, x4, x2, x3) + +inst_589: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x068 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ce and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7868; op2val:0x3cce; +op3val:0x794b; valaddr_reg:x1; val_offset:1662*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1662*FLEN/8, x4, x2, x3) + +inst_590: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ba and fs2 == 0 and fe2 == 0x0e and fm2 == 0x334 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x128 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79ba; op2val:0x3b34; +op3val:0x7928; valaddr_reg:x1; val_offset:1665*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1665*FLEN/8, x4, x2, x3) + +inst_591: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ba and fs2 == 0 and fe2 == 0x0e and fm2 == 0x334 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x128 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79ba; op2val:0x3b34; +op3val:0x7928; valaddr_reg:x1; val_offset:1668*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1668*FLEN/8, x4, x2, x3) + +inst_592: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ba and fs2 == 0 and fe2 == 0x0e and fm2 == 0x334 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x128 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79ba; op2val:0x3b34; +op3val:0x7928; valaddr_reg:x1; val_offset:1671*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1671*FLEN/8, x4, x2, x3) + +inst_593: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ba and fs2 == 0 and fe2 == 0x0e and fm2 == 0x334 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x128 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79ba; op2val:0x3b34; +op3val:0x7928; valaddr_reg:x1; val_offset:1674*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1674*FLEN/8, x4, x2, x3) + +inst_594: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ba and fs2 == 0 and fe2 == 0x0e and fm2 == 0x334 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x128 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79ba; op2val:0x3b34; +op3val:0x7928; valaddr_reg:x1; val_offset:1677*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1677*FLEN/8, x4, x2, x3) + +inst_595: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x270 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x365 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1f3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a70; op2val:0x3765; +op3val:0x75f3; valaddr_reg:x1; val_offset:1680*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1680*FLEN/8, x4, x2, x3) + +inst_596: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x270 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x365 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1f3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a70; op2val:0x3765; +op3val:0x75f3; valaddr_reg:x1; val_offset:1683*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1683*FLEN/8, x4, x2, x3) + +inst_597: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x270 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x365 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1f3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a70; op2val:0x3765; +op3val:0x75f3; valaddr_reg:x1; val_offset:1686*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1686*FLEN/8, x4, x2, x3) + +inst_598: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x270 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x365 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1f3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a70; op2val:0x3765; +op3val:0x75f3; valaddr_reg:x1; val_offset:1689*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1689*FLEN/8, x4, x2, x3) + +inst_599: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x270 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x365 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1f3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a70; op2val:0x3765; +op3val:0x75f3; valaddr_reg:x1; val_offset:1692*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1692*FLEN/8, x4, x2, x3) + +inst_600: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x154 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1d6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3c6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7954; op2val:0x3dd6; +op3val:0x7bc6; valaddr_reg:x1; val_offset:1695*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1695*FLEN/8, x4, x2, x3) + +inst_601: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x154 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1d6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3c6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7954; op2val:0x3dd6; +op3val:0x7bc6; valaddr_reg:x1; val_offset:1698*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1698*FLEN/8, x4, x2, x3) + +inst_602: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x154 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1d6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3c6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7954; op2val:0x3dd6; +op3val:0x7bc6; valaddr_reg:x1; val_offset:1701*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1701*FLEN/8, x4, x2, x3) + +inst_603: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x154 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1d6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3c6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7954; op2val:0x3dd6; +op3val:0x7bc6; valaddr_reg:x1; val_offset:1704*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1704*FLEN/8, x4, x2, x3) + +inst_604: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x154 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1d6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3c6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7954; op2val:0x3dd6; +op3val:0x7bc6; valaddr_reg:x1; val_offset:1707*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1707*FLEN/8, x4, x2, x3) + +inst_605: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x13f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x39f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x713f; op2val:0x439f; +op3val:0x7900; valaddr_reg:x1; val_offset:1710*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1710*FLEN/8, x4, x2, x3) + +inst_606: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x13f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x39f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x100 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x713f; op2val:0x439f; +op3val:0x7900; valaddr_reg:x1; val_offset:1713*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1713*FLEN/8, x4, x2, x3) + +inst_607: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x13f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x39f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x100 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x713f; op2val:0x439f; +op3val:0x7900; valaddr_reg:x1; val_offset:1716*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1716*FLEN/8, x4, x2, x3) + +inst_608: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x13f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x39f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x100 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x713f; op2val:0x439f; +op3val:0x7900; valaddr_reg:x1; val_offset:1719*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1719*FLEN/8, x4, x2, x3) + +inst_609: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x13f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x39f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x100 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x713f; op2val:0x439f; +op3val:0x7900; valaddr_reg:x1; val_offset:1722*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1722*FLEN/8, x4, x2, x3) + +inst_610: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x226 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x114 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x3d0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7626; op2val:0x3114; +op3val:0x6bd0; valaddr_reg:x1; val_offset:1725*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1725*FLEN/8, x4, x2, x3) + +inst_611: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x226 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x114 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x3d0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7626; op2val:0x3114; +op3val:0x6bd0; valaddr_reg:x1; val_offset:1728*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1728*FLEN/8, x4, x2, x3) + +inst_612: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x226 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x114 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x3d0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7626; op2val:0x3114; +op3val:0x6bd0; valaddr_reg:x1; val_offset:1731*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1731*FLEN/8, x4, x2, x3) + +inst_613: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x226 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x114 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x3d0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7626; op2val:0x3114; +op3val:0x6bd0; valaddr_reg:x1; val_offset:1734*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1734*FLEN/8, x4, x2, x3) + +inst_614: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x226 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x114 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x3d0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7626; op2val:0x3114; +op3val:0x6bd0; valaddr_reg:x1; val_offset:1737*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1737*FLEN/8, x4, x2, x3) + +inst_615: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x11a and fs2 == 0 and fe2 == 0x13 and fm2 == 0x0c1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x211 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x691a; op2val:0x4cc1; +op3val:0x7a11; valaddr_reg:x1; val_offset:1740*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1740*FLEN/8, x4, x2, x3) + +inst_616: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x11a and fs2 == 0 and fe2 == 0x13 and fm2 == 0x0c1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x211 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x691a; op2val:0x4cc1; +op3val:0x7a11; valaddr_reg:x1; val_offset:1743*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1743*FLEN/8, x4, x2, x3) + +inst_617: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x11a and fs2 == 0 and fe2 == 0x13 and fm2 == 0x0c1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x211 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x691a; op2val:0x4cc1; +op3val:0x7a11; valaddr_reg:x1; val_offset:1746*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1746*FLEN/8, x4, x2, x3) + +inst_618: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x11a and fs2 == 0 and fe2 == 0x13 and fm2 == 0x0c1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x211 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x691a; op2val:0x4cc1; +op3val:0x7a11; valaddr_reg:x1; val_offset:1749*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1749*FLEN/8, x4, x2, x3) + +inst_619: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x11a and fs2 == 0 and fe2 == 0x13 and fm2 == 0x0c1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x211 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x691a; op2val:0x4cc1; +op3val:0x7a11; valaddr_reg:x1; val_offset:1752*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1752*FLEN/8, x4, x2, x3) + +inst_620: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x354 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x234 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1af and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f54; op2val:0x4634; +op3val:0x79af; valaddr_reg:x1; val_offset:1755*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1755*FLEN/8, x4, x2, x3) + +inst_621: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x354 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x234 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1af and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f54; op2val:0x4634; +op3val:0x79af; valaddr_reg:x1; val_offset:1758*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1758*FLEN/8, x4, x2, x3) + +inst_622: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x354 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x234 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1af and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f54; op2val:0x4634; +op3val:0x79af; valaddr_reg:x1; val_offset:1761*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1761*FLEN/8, x4, x2, x3) + +inst_623: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x354 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x234 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1af and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f54; op2val:0x4634; +op3val:0x79af; valaddr_reg:x1; val_offset:1764*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1764*FLEN/8, x4, x2, x3) + +inst_624: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x354 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x234 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1af and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f54; op2val:0x4634; +op3val:0x79af; valaddr_reg:x1; val_offset:1767*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1767*FLEN/8, x4, x2, x3) + +inst_625: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x268 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x357 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1e1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e68; op2val:0x4357; +op3val:0x75e1; valaddr_reg:x1; val_offset:1770*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1770*FLEN/8, x4, x2, x3) + +inst_626: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x268 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x357 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1e1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e68; op2val:0x4357; +op3val:0x75e1; valaddr_reg:x1; val_offset:1773*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1773*FLEN/8, x4, x2, x3) + +inst_627: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x268 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x357 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1e1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e68; op2val:0x4357; +op3val:0x75e1; valaddr_reg:x1; val_offset:1776*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1776*FLEN/8, x4, x2, x3) + +inst_628: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x268 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x357 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1e1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e68; op2val:0x4357; +op3val:0x75e1; valaddr_reg:x1; val_offset:1779*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1779*FLEN/8, x4, x2, x3) + +inst_629: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x268 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x357 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1e1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e68; op2val:0x4357; +op3val:0x75e1; valaddr_reg:x1; val_offset:1782*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1782*FLEN/8, x4, x2, x3) + +inst_630: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x01e and fs2 == 0 and fe2 == 0x13 and fm2 == 0x036 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x057 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x681e; op2val:0x4c36; +op3val:0x7857; valaddr_reg:x1; val_offset:1785*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1785*FLEN/8, x4, x2, x3) + +inst_631: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x01e and fs2 == 0 and fe2 == 0x13 and fm2 == 0x036 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x057 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x681e; op2val:0x4c36; +op3val:0x7857; valaddr_reg:x1; val_offset:1788*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1788*FLEN/8, x4, x2, x3) + +inst_632: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x01e and fs2 == 0 and fe2 == 0x13 and fm2 == 0x036 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x057 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x681e; op2val:0x4c36; +op3val:0x7857; valaddr_reg:x1; val_offset:1791*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1791*FLEN/8, x4, x2, x3) + +inst_633: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x01e and fs2 == 0 and fe2 == 0x13 and fm2 == 0x036 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x057 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x681e; op2val:0x4c36; +op3val:0x7857; valaddr_reg:x1; val_offset:1794*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1794*FLEN/8, x4, x2, x3) + +inst_634: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x01e and fs2 == 0 and fe2 == 0x13 and fm2 == 0x036 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x057 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x681e; op2val:0x4c36; +op3val:0x7857; valaddr_reg:x1; val_offset:1797*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1797*FLEN/8, x4, x2, x3) + +inst_635: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x249 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x096 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x337 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a49; op2val:0x3496; +op3val:0x7337; valaddr_reg:x1; val_offset:1800*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1800*FLEN/8, x4, x2, x3) + +inst_636: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x249 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x096 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x337 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a49; op2val:0x3496; +op3val:0x7337; valaddr_reg:x1; val_offset:1803*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1803*FLEN/8, x4, x2, x3) + +inst_637: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x249 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x096 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x337 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a49; op2val:0x3496; +op3val:0x7337; valaddr_reg:x1; val_offset:1806*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1806*FLEN/8, x4, x2, x3) + +inst_638: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x249 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x096 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x337 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a49; op2val:0x3496; +op3val:0x7337; valaddr_reg:x1; val_offset:1809*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1809*FLEN/8, x4, x2, x3) + +inst_639: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x249 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x096 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x337 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a49; op2val:0x3496; +op3val:0x7337; valaddr_reg:x1; val_offset:1812*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1812*FLEN/8, x4, x2, x3) + +inst_640: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x085 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x286 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x35f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7885; op2val:0x3e86; +op3val:0x7b5f; valaddr_reg:x1; val_offset:1815*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1815*FLEN/8, x4, x2, x3) + +inst_641: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x085 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x286 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x35f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7885; op2val:0x3e86; +op3val:0x7b5f; valaddr_reg:x1; val_offset:1818*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1818*FLEN/8, x4, x2, x3) + +inst_642: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x085 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x286 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x35f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7885; op2val:0x3e86; +op3val:0x7b5f; valaddr_reg:x1; val_offset:1821*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1821*FLEN/8, x4, x2, x3) + +inst_643: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x085 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x286 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x35f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7885; op2val:0x3e86; +op3val:0x7b5f; valaddr_reg:x1; val_offset:1824*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1824*FLEN/8, x4, x2, x3) + +inst_644: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x085 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x286 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x35f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7885; op2val:0x3e86; +op3val:0x7b5f; valaddr_reg:x1; val_offset:1827*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1827*FLEN/8, x4, x2, x3) + +inst_645: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0b1 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x26b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x388 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74b1; op2val:0x3e6b; +op3val:0x7788; valaddr_reg:x1; val_offset:1830*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1830*FLEN/8, x4, x2, x3) + +inst_646: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0b1 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x26b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x388 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74b1; op2val:0x3e6b; +op3val:0x7788; valaddr_reg:x1; val_offset:1833*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1833*FLEN/8, x4, x2, x3) + +inst_647: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0b1 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x26b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x388 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74b1; op2val:0x3e6b; +op3val:0x7788; valaddr_reg:x1; val_offset:1836*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1836*FLEN/8, x4, x2, x3) + +inst_648: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0b1 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x26b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x388 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74b1; op2val:0x3e6b; +op3val:0x7788; valaddr_reg:x1; val_offset:1839*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1839*FLEN/8, x4, x2, x3) + +inst_649: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0b1 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x26b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x388 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74b1; op2val:0x3e6b; +op3val:0x7788; valaddr_reg:x1; val_offset:1842*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1842*FLEN/8, x4, x2, x3) + +inst_650: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ca and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0c6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2e9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79ca; op2val:0x3cc6; +op3val:0x7ae9; valaddr_reg:x1; val_offset:1845*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1845*FLEN/8, x4, x2, x3) + +inst_651: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ca and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0c6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2e9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79ca; op2val:0x3cc6; +op3val:0x7ae9; valaddr_reg:x1; val_offset:1848*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1848*FLEN/8, x4, x2, x3) + +inst_652: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ca and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0c6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2e9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79ca; op2val:0x3cc6; +op3val:0x7ae9; valaddr_reg:x1; val_offset:1851*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1851*FLEN/8, x4, x2, x3) + +inst_653: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ca and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0c6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2e9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79ca; op2val:0x3cc6; +op3val:0x7ae9; valaddr_reg:x1; val_offset:1854*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1854*FLEN/8, x4, x2, x3) + +inst_654: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ca and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0c6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2e9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79ca; op2val:0x3cc6; +op3val:0x7ae9; valaddr_reg:x1; val_offset:1857*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1857*FLEN/8, x4, x2, x3) + +inst_655: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x164 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3d8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x149 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7164; op2val:0x43d8; +op3val:0x7949; valaddr_reg:x1; val_offset:1860*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1860*FLEN/8, x4, x2, x3) + +inst_656: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x164 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3d8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x149 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7164; op2val:0x43d8; +op3val:0x7949; valaddr_reg:x1; val_offset:1863*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1863*FLEN/8, x4, x2, x3) + +inst_657: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x164 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3d8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x149 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7164; op2val:0x43d8; +op3val:0x7949; valaddr_reg:x1; val_offset:1866*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1866*FLEN/8, x4, x2, x3) + +inst_658: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x164 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3d8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x149 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7164; op2val:0x43d8; +op3val:0x7949; valaddr_reg:x1; val_offset:1869*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1869*FLEN/8, x4, x2, x3) + +inst_659: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x164 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3d8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x149 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7164; op2val:0x43d8; +op3val:0x7949; valaddr_reg:x1; val_offset:1872*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1872*FLEN/8, x4, x2, x3) + +inst_660: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3ae and fs2 == 0 and fe2 == 0x0e and fm2 == 0x37a and fs3 == 0 and fe3 == 0x1b and fm3 == 0x32d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6fae; op2val:0x3b7a; +op3val:0x6f2d; valaddr_reg:x1; val_offset:1875*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1875*FLEN/8, x4, x2, x3) + +inst_661: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3ae and fs2 == 0 and fe2 == 0x0e and fm2 == 0x37a and fs3 == 0 and fe3 == 0x1b and fm3 == 0x32d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6fae; op2val:0x3b7a; +op3val:0x6f2d; valaddr_reg:x1; val_offset:1878*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1878*FLEN/8, x4, x2, x3) + +inst_662: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3ae and fs2 == 0 and fe2 == 0x0e and fm2 == 0x37a and fs3 == 0 and fe3 == 0x1b and fm3 == 0x32d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6fae; op2val:0x3b7a; +op3val:0x6f2d; valaddr_reg:x1; val_offset:1881*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1881*FLEN/8, x4, x2, x3) + +inst_663: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3ae and fs2 == 0 and fe2 == 0x0e and fm2 == 0x37a and fs3 == 0 and fe3 == 0x1b and fm3 == 0x32d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6fae; op2val:0x3b7a; +op3val:0x6f2d; valaddr_reg:x1; val_offset:1884*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1884*FLEN/8, x4, x2, x3) + +inst_664: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3ae and fs2 == 0 and fe2 == 0x0e and fm2 == 0x37a and fs3 == 0 and fe3 == 0x1b and fm3 == 0x32d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6fae; op2val:0x3b7a; +op3val:0x6f2d; valaddr_reg:x1; val_offset:1887*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1887*FLEN/8, x4, x2, x3) + +inst_665: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3dc and fs2 == 0 and fe2 == 0x0a and fm2 == 0x283 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x266 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bdc; op2val:0x2a83; +op3val:0x6a66; valaddr_reg:x1; val_offset:1890*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1890*FLEN/8, x4, x2, x3) + +inst_666: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3dc and fs2 == 0 and fe2 == 0x0a and fm2 == 0x283 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x266 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bdc; op2val:0x2a83; +op3val:0x6a66; valaddr_reg:x1; val_offset:1893*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1893*FLEN/8, x4, x2, x3) + +inst_667: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3dc and fs2 == 0 and fe2 == 0x0a and fm2 == 0x283 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x266 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bdc; op2val:0x2a83; +op3val:0x6a66; valaddr_reg:x1; val_offset:1896*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1896*FLEN/8, x4, x2, x3) +RVTEST_SIGBASE(x2,signature_x2_5) + +inst_668: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3dc and fs2 == 0 and fe2 == 0x0a and fm2 == 0x283 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x266 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bdc; op2val:0x2a83; +op3val:0x6a66; valaddr_reg:x1; val_offset:1899*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1899*FLEN/8, x4, x2, x3) + +inst_669: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3dc and fs2 == 0 and fe2 == 0x0a and fm2 == 0x283 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x266 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bdc; op2val:0x2a83; +op3val:0x6a66; valaddr_reg:x1; val_offset:1902*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1902*FLEN/8, x4, x2, x3) + +inst_670: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x35a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x286 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b5a; op2val:0x3a86; +op3val:0x79ff; valaddr_reg:x1; val_offset:1905*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1905*FLEN/8, x4, x2, x3) + +inst_671: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x35a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x286 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b5a; op2val:0x3a86; +op3val:0x79ff; valaddr_reg:x1; val_offset:1908*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1908*FLEN/8, x4, x2, x3) + +inst_672: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x35a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x286 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b5a; op2val:0x3a86; +op3val:0x79ff; valaddr_reg:x1; val_offset:1911*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1911*FLEN/8, x4, x2, x3) + +inst_673: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x35a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x286 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b5a; op2val:0x3a86; +op3val:0x79ff; valaddr_reg:x1; val_offset:1914*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1914*FLEN/8, x4, x2, x3) + +inst_674: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x35a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x286 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b5a; op2val:0x3a86; +op3val:0x79ff; valaddr_reg:x1; val_offset:1917*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1917*FLEN/8, x4, x2, x3) + +inst_675: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x167 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x051 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1d5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7967; op2val:0x3c51; +op3val:0x79d5; valaddr_reg:x1; val_offset:1920*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1920*FLEN/8, x4, x2, x3) + +inst_676: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x167 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x051 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1d5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7967; op2val:0x3c51; +op3val:0x79d5; valaddr_reg:x1; val_offset:1923*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1923*FLEN/8, x4, x2, x3) + +inst_677: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x167 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x051 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1d5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7967; op2val:0x3c51; +op3val:0x79d5; valaddr_reg:x1; val_offset:1926*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1926*FLEN/8, x4, x2, x3) + +inst_678: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x167 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x051 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1d5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7967; op2val:0x3c51; +op3val:0x79d5; valaddr_reg:x1; val_offset:1929*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1929*FLEN/8, x4, x2, x3) + +inst_679: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x167 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x051 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1d5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7967; op2val:0x3c51; +op3val:0x79d5; valaddr_reg:x1; val_offset:1932*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1932*FLEN/8, x4, x2, x3) + +inst_680: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x134 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x30e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x097 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7934; op2val:0x370e; +op3val:0x7497; valaddr_reg:x1; val_offset:1935*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1935*FLEN/8, x4, x2, x3) + +inst_681: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x134 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x30e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x097 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7934; op2val:0x370e; +op3val:0x7497; valaddr_reg:x1; val_offset:1938*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1938*FLEN/8, x4, x2, x3) + +inst_682: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x134 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x30e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x097 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7934; op2val:0x370e; +op3val:0x7497; valaddr_reg:x1; val_offset:1941*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1941*FLEN/8, x4, x2, x3) + +inst_683: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x134 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x30e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x097 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7934; op2val:0x370e; +op3val:0x7497; valaddr_reg:x1; val_offset:1944*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1944*FLEN/8, x4, x2, x3) + +inst_684: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x134 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x30e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x097 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7934; op2val:0x370e; +op3val:0x7497; valaddr_reg:x1; val_offset:1947*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1947*FLEN/8, x4, x2, x3) + +inst_685: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x317 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x34b and fs3 == 0 and fe3 == 0x1c and fm3 == 0x277 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7717; op2val:0x374b; +op3val:0x7277; valaddr_reg:x1; val_offset:1950*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1950*FLEN/8, x4, x2, x3) + +inst_686: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x317 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x34b and fs3 == 0 and fe3 == 0x1c and fm3 == 0x277 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7717; op2val:0x374b; +op3val:0x7277; valaddr_reg:x1; val_offset:1953*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1953*FLEN/8, x4, x2, x3) + +inst_687: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x317 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x34b and fs3 == 0 and fe3 == 0x1c and fm3 == 0x277 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7717; op2val:0x374b; +op3val:0x7277; valaddr_reg:x1; val_offset:1956*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1956*FLEN/8, x4, x2, x3) + +inst_688: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x317 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x34b and fs3 == 0 and fe3 == 0x1c and fm3 == 0x277 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7717; op2val:0x374b; +op3val:0x7277; valaddr_reg:x1; val_offset:1959*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1959*FLEN/8, x4, x2, x3) + +inst_689: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x317 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x34b and fs3 == 0 and fe3 == 0x1c and fm3 == 0x277 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7717; op2val:0x374b; +op3val:0x7277; valaddr_reg:x1; val_offset:1962*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1962*FLEN/8, x4, x2, x3) + +inst_690: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2de and fs2 == 0 and fe2 == 0x0e and fm2 == 0x340 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x23a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ade; op2val:0x3b40; +op3val:0x7a3a; valaddr_reg:x1; val_offset:1965*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1965*FLEN/8, x4, x2, x3) + +inst_691: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2de and fs2 == 0 and fe2 == 0x0e and fm2 == 0x340 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x23a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ade; op2val:0x3b40; +op3val:0x7a3a; valaddr_reg:x1; val_offset:1968*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1968*FLEN/8, x4, x2, x3) + +inst_692: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2de and fs2 == 0 and fe2 == 0x0e and fm2 == 0x340 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x23a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ade; op2val:0x3b40; +op3val:0x7a3a; valaddr_reg:x1; val_offset:1971*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1971*FLEN/8, x4, x2, x3) + +inst_693: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2de and fs2 == 0 and fe2 == 0x0e and fm2 == 0x340 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x23a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ade; op2val:0x3b40; +op3val:0x7a3a; valaddr_reg:x1; val_offset:1974*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1974*FLEN/8, x4, x2, x3) + +inst_694: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2de and fs2 == 0 and fe2 == 0x0e and fm2 == 0x340 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x23a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ade; op2val:0x3b40; +op3val:0x7a3a; valaddr_reg:x1; val_offset:1977*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1977*FLEN/8, x4, x2, x3) + +inst_695: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x24c and fs2 == 0 and fe2 == 0x0d and fm2 == 0x058 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2d7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a4c; op2val:0x3458; +op3val:0x72d7; valaddr_reg:x1; val_offset:1980*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1980*FLEN/8, x4, x2, x3) + +inst_696: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x24c and fs2 == 0 and fe2 == 0x0d and fm2 == 0x058 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2d7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a4c; op2val:0x3458; +op3val:0x72d7; valaddr_reg:x1; val_offset:1983*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1983*FLEN/8, x4, x2, x3) + +inst_697: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x24c and fs2 == 0 and fe2 == 0x0d and fm2 == 0x058 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2d7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a4c; op2val:0x3458; +op3val:0x72d7; valaddr_reg:x1; val_offset:1986*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1986*FLEN/8, x4, x2, x3) + +inst_698: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x24c and fs2 == 0 and fe2 == 0x0d and fm2 == 0x058 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2d7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a4c; op2val:0x3458; +op3val:0x72d7; valaddr_reg:x1; val_offset:1989*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1989*FLEN/8, x4, x2, x3) + +inst_699: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x24c and fs2 == 0 and fe2 == 0x0d and fm2 == 0x058 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2d7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a4c; op2val:0x3458; +op3val:0x72d7; valaddr_reg:x1; val_offset:1992*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1992*FLEN/8, x4, x2, x3) + +inst_700: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0bc and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2e3 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x013 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78bc; op2val:0x36e3; +op3val:0x7413; valaddr_reg:x1; val_offset:1995*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1995*FLEN/8, x4, x2, x3) + +inst_701: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0bc and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2e3 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x013 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78bc; op2val:0x36e3; +op3val:0x7413; valaddr_reg:x1; val_offset:1998*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1998*FLEN/8, x4, x2, x3) + +inst_702: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0bc and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2e3 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x013 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78bc; op2val:0x36e3; +op3val:0x7413; valaddr_reg:x1; val_offset:2001*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2001*FLEN/8, x4, x2, x3) + +inst_703: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0bc and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2e3 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x013 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78bc; op2val:0x36e3; +op3val:0x7413; valaddr_reg:x1; val_offset:2004*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2004*FLEN/8, x4, x2, x3) + +inst_704: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0bc and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2e3 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x013 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78bc; op2val:0x36e3; +op3val:0x7413; valaddr_reg:x1; val_offset:2007*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2007*FLEN/8, x4, x2, x3) + +inst_705: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x252 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x389 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1f4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a52; op2val:0x3b89; +op3val:0x79f4; valaddr_reg:x1; val_offset:2010*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2010*FLEN/8, x4, x2, x3) + +inst_706: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x252 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x389 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1f4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a52; op2val:0x3b89; +op3val:0x79f4; valaddr_reg:x1; val_offset:2013*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2013*FLEN/8, x4, x2, x3) + +inst_707: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x252 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x389 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1f4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a52; op2val:0x3b89; +op3val:0x79f4; valaddr_reg:x1; val_offset:2016*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2016*FLEN/8, x4, x2, x3) + +inst_708: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x252 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x389 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1f4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a52; op2val:0x3b89; +op3val:0x79f4; valaddr_reg:x1; val_offset:2019*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2019*FLEN/8, x4, x2, x3) + +inst_709: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x252 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x389 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1f4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a52; op2val:0x3b89; +op3val:0x79f4; valaddr_reg:x1; val_offset:2022*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2022*FLEN/8, x4, x2, x3) + +inst_710: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f4 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1b1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bf4; op2val:0x39b1; +op3val:0x79a9; valaddr_reg:x1; val_offset:2025*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2025*FLEN/8, x4, x2, x3) + +inst_711: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f4 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1b1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bf4; op2val:0x39b1; +op3val:0x79a9; valaddr_reg:x1; val_offset:2028*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2028*FLEN/8, x4, x2, x3) + +inst_712: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f4 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1b1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bf4; op2val:0x39b1; +op3val:0x79a9; valaddr_reg:x1; val_offset:2031*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2031*FLEN/8, x4, x2, x3) + +inst_713: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f4 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1b1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bf4; op2val:0x39b1; +op3val:0x79a9; valaddr_reg:x1; val_offset:2034*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2034*FLEN/8, x4, x2, x3) + +inst_714: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f4 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1b1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bf4; op2val:0x39b1; +op3val:0x79a9; valaddr_reg:x1; val_offset:2037*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2037*FLEN/8, x4, x2, x3) + +inst_715: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x177 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x08b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x236 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7977; op2val:0x3c8b; +op3val:0x7a36; valaddr_reg:x1; val_offset:2040*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2040*FLEN/8, x4, x2, x3) + +inst_716: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x177 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x08b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x236 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7977; op2val:0x3c8b; +op3val:0x7a36; valaddr_reg:x1; val_offset:2043*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2043*FLEN/8, x4, x2, x3) + +inst_717: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x177 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x08b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x236 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7977; op2val:0x3c8b; +op3val:0x7a36; valaddr_reg:x1; val_offset:2046*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2046*FLEN/8, x4, x2, x3) + +inst_718: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x177 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x08b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x236 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7977; op2val:0x3c8b; +op3val:0x7a36; valaddr_reg:x1; val_offset:2049*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2049*FLEN/8, x4, x2, x3) + +inst_719: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x177 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x08b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x236 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7977; op2val:0x3c8b; +op3val:0x7a36; valaddr_reg:x1; val_offset:2052*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2052*FLEN/8, x4, x2, x3) + +inst_720: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1fe and fs2 == 0 and fe2 == 0x11 and fm2 == 0x25a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0c2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dfe; op2val:0x465a; +op3val:0x78c2; valaddr_reg:x1; val_offset:2055*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2055*FLEN/8, x4, x2, x3) + +inst_721: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1fe and fs2 == 0 and fe2 == 0x11 and fm2 == 0x25a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0c2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dfe; op2val:0x465a; +op3val:0x78c2; valaddr_reg:x1; val_offset:2058*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2058*FLEN/8, x4, x2, x3) + +inst_722: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1fe and fs2 == 0 and fe2 == 0x11 and fm2 == 0x25a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0c2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dfe; op2val:0x465a; +op3val:0x78c2; valaddr_reg:x1; val_offset:2061*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2061*FLEN/8, x4, x2, x3) + +inst_723: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1fe and fs2 == 0 and fe2 == 0x11 and fm2 == 0x25a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0c2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dfe; op2val:0x465a; +op3val:0x78c2; valaddr_reg:x1; val_offset:2064*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2064*FLEN/8, x4, x2, x3) + +inst_724: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1fe and fs2 == 0 and fe2 == 0x11 and fm2 == 0x25a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0c2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dfe; op2val:0x465a; +op3val:0x78c2; valaddr_reg:x1; val_offset:2067*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2067*FLEN/8, x4, x2, x3) + +inst_725: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x030 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x19a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1df and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6830; op2val:0x499a; +op3val:0x75df; valaddr_reg:x1; val_offset:2070*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2070*FLEN/8, x4, x2, x3) + +inst_726: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x030 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x19a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1df and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6830; op2val:0x499a; +op3val:0x75df; valaddr_reg:x1; val_offset:2073*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2073*FLEN/8, x4, x2, x3) + +inst_727: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x030 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x19a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1df and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6830; op2val:0x499a; +op3val:0x75df; valaddr_reg:x1; val_offset:2076*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2076*FLEN/8, x4, x2, x3) + +inst_728: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x030 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x19a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1df and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6830; op2val:0x499a; +op3val:0x75df; valaddr_reg:x1; val_offset:2079*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2079*FLEN/8, x4, x2, x3) + +inst_729: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x030 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x19a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1df and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6830; op2val:0x499a; +op3val:0x75df; valaddr_reg:x1; val_offset:2082*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2082*FLEN/8, x4, x2, x3) + +inst_730: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x37e and fs2 == 0 and fe2 == 0x12 and fm2 == 0x00c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x395 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f7e; op2val:0x480c; +op3val:0x7b95; valaddr_reg:x1; val_offset:2085*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2085*FLEN/8, x4, x2, x3) + +inst_731: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x37e and fs2 == 0 and fe2 == 0x12 and fm2 == 0x00c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x395 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f7e; op2val:0x480c; +op3val:0x7b95; valaddr_reg:x1; val_offset:2088*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2088*FLEN/8, x4, x2, x3) + +inst_732: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x37e and fs2 == 0 and fe2 == 0x12 and fm2 == 0x00c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x395 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f7e; op2val:0x480c; +op3val:0x7b95; valaddr_reg:x1; val_offset:2091*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2091*FLEN/8, x4, x2, x3) + +inst_733: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x37e and fs2 == 0 and fe2 == 0x12 and fm2 == 0x00c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x395 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f7e; op2val:0x480c; +op3val:0x7b95; valaddr_reg:x1; val_offset:2094*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2094*FLEN/8, x4, x2, x3) + +inst_734: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x37e and fs2 == 0 and fe2 == 0x12 and fm2 == 0x00c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x395 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f7e; op2val:0x480c; +op3val:0x7b95; valaddr_reg:x1; val_offset:2097*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2097*FLEN/8, x4, x2, x3) + +inst_735: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x32b and fs2 == 0 and fe2 == 0x14 and fm2 == 0x01b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x35d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x672b; op2val:0x501b; +op3val:0x7b5d; valaddr_reg:x1; val_offset:2100*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2100*FLEN/8, x4, x2, x3) + +inst_736: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x32b and fs2 == 0 and fe2 == 0x14 and fm2 == 0x01b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x35d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x672b; op2val:0x501b; +op3val:0x7b5d; valaddr_reg:x1; val_offset:2103*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2103*FLEN/8, x4, x2, x3) + +inst_737: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x32b and fs2 == 0 and fe2 == 0x14 and fm2 == 0x01b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x35d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x672b; op2val:0x501b; +op3val:0x7b5d; valaddr_reg:x1; val_offset:2106*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2106*FLEN/8, x4, x2, x3) + +inst_738: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x32b and fs2 == 0 and fe2 == 0x14 and fm2 == 0x01b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x35d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x672b; op2val:0x501b; +op3val:0x7b5d; valaddr_reg:x1; val_offset:2109*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2109*FLEN/8, x4, x2, x3) + +inst_739: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x32b and fs2 == 0 and fe2 == 0x14 and fm2 == 0x01b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x35d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x672b; op2val:0x501b; +op3val:0x7b5d; valaddr_reg:x1; val_offset:2112*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2112*FLEN/8, x4, x2, x3) + +inst_740: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x394 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x35a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2f7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b94; op2val:0x375a; +op3val:0x76f7; valaddr_reg:x1; val_offset:2115*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2115*FLEN/8, x4, x2, x3) + +inst_741: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x394 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x35a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2f7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b94; op2val:0x375a; +op3val:0x76f7; valaddr_reg:x1; val_offset:2118*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2118*FLEN/8, x4, x2, x3) + +inst_742: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x394 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x35a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2f7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b94; op2val:0x375a; +op3val:0x76f7; valaddr_reg:x1; val_offset:2121*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2121*FLEN/8, x4, x2, x3) + +inst_743: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x394 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x35a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2f7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b94; op2val:0x375a; +op3val:0x76f7; valaddr_reg:x1; val_offset:2124*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2124*FLEN/8, x4, x2, x3) + +inst_744: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x394 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x35a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2f7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b94; op2val:0x375a; +op3val:0x76f7; valaddr_reg:x1; val_offset:2127*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2127*FLEN/8, x4, x2, x3) + +inst_745: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a8 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x3f5 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x29f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aa8; op2val:0x2bf5; +op3val:0x6a9f; valaddr_reg:x1; val_offset:2130*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2130*FLEN/8, x4, x2, x3) + +inst_746: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a8 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x3f5 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x29f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aa8; op2val:0x2bf5; +op3val:0x6a9f; valaddr_reg:x1; val_offset:2133*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2133*FLEN/8, x4, x2, x3) + +inst_747: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a8 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x3f5 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x29f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aa8; op2val:0x2bf5; +op3val:0x6a9f; valaddr_reg:x1; val_offset:2136*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2136*FLEN/8, x4, x2, x3) + +inst_748: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a8 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x3f5 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x29f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aa8; op2val:0x2bf5; +op3val:0x6a9f; valaddr_reg:x1; val_offset:2139*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2139*FLEN/8, x4, x2, x3) + +inst_749: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a8 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x3f5 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x29f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aa8; op2val:0x2bf5; +op3val:0x6a9f; valaddr_reg:x1; val_offset:2142*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2142*FLEN/8, x4, x2, x3) + +inst_750: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x075 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x084 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x109 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7075; op2val:0x2c84; +op3val:0x6109; valaddr_reg:x1; val_offset:2145*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2145*FLEN/8, x4, x2, x3) + +inst_751: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x075 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x084 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x109 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7075; op2val:0x2c84; +op3val:0x6109; valaddr_reg:x1; val_offset:2148*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2148*FLEN/8, x4, x2, x3) + +inst_752: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x075 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x084 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x109 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7075; op2val:0x2c84; +op3val:0x6109; valaddr_reg:x1; val_offset:2151*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2151*FLEN/8, x4, x2, x3) + +inst_753: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x075 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x084 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x109 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7075; op2val:0x2c84; +op3val:0x6109; valaddr_reg:x1; val_offset:2154*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2154*FLEN/8, x4, x2, x3) + +inst_754: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x075 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x084 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x109 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7075; op2val:0x2c84; +op3val:0x6109; valaddr_reg:x1; val_offset:2157*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2157*FLEN/8, x4, x2, x3) + +inst_755: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x05b and fs2 == 0 and fe2 == 0x0a and fm2 == 0x0e0 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x150 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c5b; op2val:0x28e0; +op3val:0x5950; valaddr_reg:x1; val_offset:2160*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2160*FLEN/8, x4, x2, x3) + +inst_756: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x05b and fs2 == 0 and fe2 == 0x0a and fm2 == 0x0e0 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x150 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c5b; op2val:0x28e0; +op3val:0x5950; valaddr_reg:x1; val_offset:2163*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2163*FLEN/8, x4, x2, x3) + +inst_757: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x05b and fs2 == 0 and fe2 == 0x0a and fm2 == 0x0e0 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x150 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c5b; op2val:0x28e0; +op3val:0x5950; valaddr_reg:x1; val_offset:2166*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2166*FLEN/8, x4, x2, x3) + +inst_758: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x05b and fs2 == 0 and fe2 == 0x0a and fm2 == 0x0e0 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x150 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c5b; op2val:0x28e0; +op3val:0x5950; valaddr_reg:x1; val_offset:2169*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2169*FLEN/8, x4, x2, x3) + +inst_759: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x05b and fs2 == 0 and fe2 == 0x0a and fm2 == 0x0e0 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x150 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c5b; op2val:0x28e0; +op3val:0x5950; valaddr_reg:x1; val_offset:2172*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2172*FLEN/8, x4, x2, x3) + +inst_760: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x29f and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2c3 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x199 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a9f; op2val:0x2ec3; +op3val:0x6d99; valaddr_reg:x1; val_offset:2175*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2175*FLEN/8, x4, x2, x3) + +inst_761: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x29f and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2c3 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x199 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a9f; op2val:0x2ec3; +op3val:0x6d99; valaddr_reg:x1; val_offset:2178*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2178*FLEN/8, x4, x2, x3) + +inst_762: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x29f and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2c3 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x199 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a9f; op2val:0x2ec3; +op3val:0x6d99; valaddr_reg:x1; val_offset:2181*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2181*FLEN/8, x4, x2, x3) + +inst_763: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x29f and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2c3 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x199 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a9f; op2val:0x2ec3; +op3val:0x6d99; valaddr_reg:x1; val_offset:2184*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2184*FLEN/8, x4, x2, x3) + +inst_764: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x29f and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2c3 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x199 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a9f; op2val:0x2ec3; +op3val:0x6d99; valaddr_reg:x1; val_offset:2187*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2187*FLEN/8, x4, x2, x3) + +inst_765: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b9 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x366 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x05e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78b9; op2val:0x3766; +op3val:0x745e; valaddr_reg:x1; val_offset:2190*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2190*FLEN/8, x4, x2, x3) + +inst_766: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b9 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x366 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x05e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78b9; op2val:0x3766; +op3val:0x745e; valaddr_reg:x1; val_offset:2193*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2193*FLEN/8, x4, x2, x3) + +inst_767: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b9 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x366 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x05e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78b9; op2val:0x3766; +op3val:0x745e; valaddr_reg:x1; val_offset:2196*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2196*FLEN/8, x4, x2, x3) + +inst_768: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b9 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x366 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x05e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78b9; op2val:0x3766; +op3val:0x745e; valaddr_reg:x1; val_offset:2199*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2199*FLEN/8, x4, x2, x3) + +inst_769: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b9 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x366 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x05e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78b9; op2val:0x3766; +op3val:0x745e; valaddr_reg:x1; val_offset:2202*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2202*FLEN/8, x4, x2, x3) + +inst_770: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x03c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2b4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x703c; op2val:0x4255; +op3val:0x76b4; valaddr_reg:x1; val_offset:2205*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2205*FLEN/8, x4, x2, x3) + +inst_771: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x03c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2b4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x703c; op2val:0x4255; +op3val:0x76b4; valaddr_reg:x1; val_offset:2208*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2208*FLEN/8, x4, x2, x3) + +inst_772: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x03c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2b4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x703c; op2val:0x4255; +op3val:0x76b4; valaddr_reg:x1; val_offset:2211*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2211*FLEN/8, x4, x2, x3) + +inst_773: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x03c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2b4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x703c; op2val:0x4255; +op3val:0x76b4; valaddr_reg:x1; val_offset:2214*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2214*FLEN/8, x4, x2, x3) + +inst_774: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x03c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2b4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x703c; op2val:0x4255; +op3val:0x76b4; valaddr_reg:x1; val_offset:2217*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2217*FLEN/8, x4, x2, x3) + +inst_775: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1d1 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x15f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3d0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71d1; op2val:0x455f; +op3val:0x7bd0; valaddr_reg:x1; val_offset:2220*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2220*FLEN/8, x4, x2, x3) + +inst_776: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1d1 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x15f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3d0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71d1; op2val:0x455f; +op3val:0x7bd0; valaddr_reg:x1; val_offset:2223*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2223*FLEN/8, x4, x2, x3) + +inst_777: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1d1 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x15f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3d0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71d1; op2val:0x455f; +op3val:0x7bd0; valaddr_reg:x1; val_offset:2226*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2226*FLEN/8, x4, x2, x3) + +inst_778: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1d1 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x15f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3d0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71d1; op2val:0x455f; +op3val:0x7bd0; valaddr_reg:x1; val_offset:2229*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2229*FLEN/8, x4, x2, x3) + +inst_779: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1d1 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x15f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3d0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71d1; op2val:0x455f; +op3val:0x7bd0; valaddr_reg:x1; val_offset:2232*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2232*FLEN/8, x4, x2, x3) + +inst_780: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x223 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x22f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0bf and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7623; op2val:0x3e2f; +op3val:0x78bf; valaddr_reg:x1; val_offset:2235*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2235*FLEN/8, x4, x2, x3) + +inst_781: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x223 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x22f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0bf and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7623; op2val:0x3e2f; +op3val:0x78bf; valaddr_reg:x1; val_offset:2238*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2238*FLEN/8, x4, x2, x3) + +inst_782: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x223 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x22f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0bf and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7623; op2val:0x3e2f; +op3val:0x78bf; valaddr_reg:x1; val_offset:2241*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2241*FLEN/8, x4, x2, x3) + +inst_783: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x223 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x22f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0bf and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7623; op2val:0x3e2f; +op3val:0x78bf; valaddr_reg:x1; val_offset:2244*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2244*FLEN/8, x4, x2, x3) + +inst_784: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x223 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x22f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0bf and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7623; op2val:0x3e2f; +op3val:0x78bf; valaddr_reg:x1; val_offset:2247*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2247*FLEN/8, x4, x2, x3) + +inst_785: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x081 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x073 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x103 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7881; op2val:0x3c73; +op3val:0x7903; valaddr_reg:x1; val_offset:2250*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2250*FLEN/8, x4, x2, x3) + +inst_786: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x081 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x073 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x103 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7881; op2val:0x3c73; +op3val:0x7903; valaddr_reg:x1; val_offset:2253*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2253*FLEN/8, x4, x2, x3) + +inst_787: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x081 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x073 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x103 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7881; op2val:0x3c73; +op3val:0x7903; valaddr_reg:x1; val_offset:2256*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2256*FLEN/8, x4, x2, x3) + +inst_788: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x081 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x073 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x103 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7881; op2val:0x3c73; +op3val:0x7903; valaddr_reg:x1; val_offset:2259*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2259*FLEN/8, x4, x2, x3) + +inst_789: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x081 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x073 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x103 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7881; op2val:0x3c73; +op3val:0x7903; valaddr_reg:x1; val_offset:2262*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2262*FLEN/8, x4, x2, x3) + +inst_790: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ae and fs2 == 0 and fe2 == 0x0e and fm2 == 0x07f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x052 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77ae; op2val:0x387f; +op3val:0x7452; valaddr_reg:x1; val_offset:2265*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2265*FLEN/8, x4, x2, x3) + +inst_791: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ae and fs2 == 0 and fe2 == 0x0e and fm2 == 0x07f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x052 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77ae; op2val:0x387f; +op3val:0x7452; valaddr_reg:x1; val_offset:2268*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2268*FLEN/8, x4, x2, x3) + +inst_792: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ae and fs2 == 0 and fe2 == 0x0e and fm2 == 0x07f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x052 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77ae; op2val:0x387f; +op3val:0x7452; valaddr_reg:x1; val_offset:2271*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2271*FLEN/8, x4, x2, x3) + +inst_793: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ae and fs2 == 0 and fe2 == 0x0e and fm2 == 0x07f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x052 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77ae; op2val:0x387f; +op3val:0x7452; valaddr_reg:x1; val_offset:2274*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2274*FLEN/8, x4, x2, x3) + +inst_794: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ae and fs2 == 0 and fe2 == 0x0e and fm2 == 0x07f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x052 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77ae; op2val:0x387f; +op3val:0x7452; valaddr_reg:x1; val_offset:2277*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2277*FLEN/8, x4, x2, x3) + +inst_795: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x060 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x27e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x319 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7060; op2val:0x467e; +op3val:0x7b19; valaddr_reg:x1; val_offset:2280*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2280*FLEN/8, x4, x2, x3) +RVTEST_SIGBASE(x2,signature_x2_6) + +inst_796: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x060 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x27e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x319 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7060; op2val:0x467e; +op3val:0x7b19; valaddr_reg:x1; val_offset:2283*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2283*FLEN/8, x4, x2, x3) + +inst_797: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x060 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x27e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x319 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7060; op2val:0x467e; +op3val:0x7b19; valaddr_reg:x1; val_offset:2286*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2286*FLEN/8, x4, x2, x3) + +inst_798: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x060 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x27e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x319 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7060; op2val:0x467e; +op3val:0x7b19; valaddr_reg:x1; val_offset:2289*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2289*FLEN/8, x4, x2, x3) + +inst_799: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x060 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x27e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x319 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7060; op2val:0x467e; +op3val:0x7b19; valaddr_reg:x1; val_offset:2292*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2292*FLEN/8, x4, x2, x3) + +inst_800: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x228 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0a8 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x32b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7228; op2val:0x40a8; +op3val:0x772b; valaddr_reg:x1; val_offset:2295*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2295*FLEN/8, x4, x2, x3) + +inst_801: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x228 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0a8 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x32b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7228; op2val:0x40a8; +op3val:0x772b; valaddr_reg:x1; val_offset:2298*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2298*FLEN/8, x4, x2, x3) + +inst_802: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x228 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0a8 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x32b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7228; op2val:0x40a8; +op3val:0x772b; valaddr_reg:x1; val_offset:2301*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2301*FLEN/8, x4, x2, x3) + +inst_803: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x228 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0a8 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x32b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7228; op2val:0x40a8; +op3val:0x772b; valaddr_reg:x1; val_offset:2304*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2304*FLEN/8, x4, x2, x3) + +inst_804: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x228 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0a8 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x32b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7228; op2val:0x40a8; +op3val:0x772b; valaddr_reg:x1; val_offset:2307*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2307*FLEN/8, x4, x2, x3) + +inst_805: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x276 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1b3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x09b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a76; op2val:0x39b3; +op3val:0x789b; valaddr_reg:x1; val_offset:2310*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2310*FLEN/8, x4, x2, x3) + +inst_806: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x276 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1b3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x09b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a76; op2val:0x39b3; +op3val:0x789b; valaddr_reg:x1; val_offset:2313*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2313*FLEN/8, x4, x2, x3) + +inst_807: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x276 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1b3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x09b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a76; op2val:0x39b3; +op3val:0x789b; valaddr_reg:x1; val_offset:2316*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2316*FLEN/8, x4, x2, x3) + +inst_808: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x276 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1b3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x09b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a76; op2val:0x39b3; +op3val:0x789b; valaddr_reg:x1; val_offset:2319*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2319*FLEN/8, x4, x2, x3) + +inst_809: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x276 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1b3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x09b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a76; op2val:0x39b3; +op3val:0x789b; valaddr_reg:x1; val_offset:2322*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2322*FLEN/8, x4, x2, x3) + +inst_810: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x394 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x279 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b94; op2val:0x3ad4; +op3val:0x7a79; valaddr_reg:x1; val_offset:2325*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2325*FLEN/8, x4, x2, x3) + +inst_811: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x394 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x279 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b94; op2val:0x3ad4; +op3val:0x7a79; valaddr_reg:x1; val_offset:2328*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2328*FLEN/8, x4, x2, x3) + +inst_812: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x394 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x279 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b94; op2val:0x3ad4; +op3val:0x7a79; valaddr_reg:x1; val_offset:2331*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2331*FLEN/8, x4, x2, x3) + +inst_813: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x394 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x279 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b94; op2val:0x3ad4; +op3val:0x7a79; valaddr_reg:x1; val_offset:2334*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2334*FLEN/8, x4, x2, x3) + +inst_814: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x394 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x279 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b94; op2val:0x3ad4; +op3val:0x7a79; valaddr_reg:x1; val_offset:2337*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2337*FLEN/8, x4, x2, x3) + +inst_815: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x01b and fs2 == 0 and fe2 == 0x0c and fm2 == 0x378 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x3ab and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x781b; op2val:0x3378; +op3val:0x6fab; valaddr_reg:x1; val_offset:2340*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2340*FLEN/8, x4, x2, x3) + +inst_816: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x01b and fs2 == 0 and fe2 == 0x0c and fm2 == 0x378 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x3ab and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x781b; op2val:0x3378; +op3val:0x6fab; valaddr_reg:x1; val_offset:2343*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2343*FLEN/8, x4, x2, x3) + +inst_817: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x01b and fs2 == 0 and fe2 == 0x0c and fm2 == 0x378 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x3ab and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x781b; op2val:0x3378; +op3val:0x6fab; valaddr_reg:x1; val_offset:2346*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2346*FLEN/8, x4, x2, x3) + +inst_818: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x01b and fs2 == 0 and fe2 == 0x0c and fm2 == 0x378 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x3ab and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x781b; op2val:0x3378; +op3val:0x6fab; valaddr_reg:x1; val_offset:2349*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2349*FLEN/8, x4, x2, x3) + +inst_819: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x01b and fs2 == 0 and fe2 == 0x0c and fm2 == 0x378 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x3ab and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x781b; op2val:0x3378; +op3val:0x6fab; valaddr_reg:x1; val_offset:2352*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2352*FLEN/8, x4, x2, x3) + +inst_820: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0bd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x264 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x393 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78bd; op2val:0x3a64; +op3val:0x7793; valaddr_reg:x1; val_offset:2355*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2355*FLEN/8, x4, x2, x3) + +inst_821: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0bd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x264 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x393 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78bd; op2val:0x3a64; +op3val:0x7793; valaddr_reg:x1; val_offset:2358*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2358*FLEN/8, x4, x2, x3) + +inst_822: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0bd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x264 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x393 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78bd; op2val:0x3a64; +op3val:0x7793; valaddr_reg:x1; val_offset:2361*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2361*FLEN/8, x4, x2, x3) + +inst_823: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0bd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x264 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x393 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78bd; op2val:0x3a64; +op3val:0x7793; valaddr_reg:x1; val_offset:2364*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2364*FLEN/8, x4, x2, x3) + +inst_824: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0bd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x264 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x393 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78bd; op2val:0x3a64; +op3val:0x7793; valaddr_reg:x1; val_offset:2367*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2367*FLEN/8, x4, x2, x3) + +inst_825: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e4 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0ed and fs3 == 0 and fe3 == 0x1e and fm3 == 0x03e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ae4; op2val:0x38ed; +op3val:0x783e; valaddr_reg:x1; val_offset:2370*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2370*FLEN/8, x4, x2, x3) + +inst_826: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e4 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0ed and fs3 == 0 and fe3 == 0x1e and fm3 == 0x03e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ae4; op2val:0x38ed; +op3val:0x783e; valaddr_reg:x1; val_offset:2373*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2373*FLEN/8, x4, x2, x3) + +inst_827: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e4 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0ed and fs3 == 0 and fe3 == 0x1e and fm3 == 0x03e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ae4; op2val:0x38ed; +op3val:0x783e; valaddr_reg:x1; val_offset:2376*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2376*FLEN/8, x4, x2, x3) + +inst_828: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e4 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0ed and fs3 == 0 and fe3 == 0x1e and fm3 == 0x03e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ae4; op2val:0x38ed; +op3val:0x783e; valaddr_reg:x1; val_offset:2379*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2379*FLEN/8, x4, x2, x3) + +inst_829: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e4 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0ed and fs3 == 0 and fe3 == 0x1e and fm3 == 0x03e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ae4; op2val:0x38ed; +op3val:0x783e; valaddr_reg:x1; val_offset:2382*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2382*FLEN/8, x4, x2, x3) + +inst_830: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x18d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ad and fs3 == 0 and fe3 == 0x1e and fm3 == 0x27d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x798d; op2val:0x3cad; +op3val:0x7a7d; valaddr_reg:x1; val_offset:2385*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2385*FLEN/8, x4, x2, x3) + +inst_831: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x18d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ad and fs3 == 0 and fe3 == 0x1e and fm3 == 0x27d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x798d; op2val:0x3cad; +op3val:0x7a7d; valaddr_reg:x1; val_offset:2388*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2388*FLEN/8, x4, x2, x3) + +inst_832: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x18d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ad and fs3 == 0 and fe3 == 0x1e and fm3 == 0x27d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x798d; op2val:0x3cad; +op3val:0x7a7d; valaddr_reg:x1; val_offset:2391*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2391*FLEN/8, x4, x2, x3) + +inst_833: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x18d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ad and fs3 == 0 and fe3 == 0x1e and fm3 == 0x27d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x798d; op2val:0x3cad; +op3val:0x7a7d; valaddr_reg:x1; val_offset:2394*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2394*FLEN/8, x4, x2, x3) + +inst_834: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x18d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ad and fs3 == 0 and fe3 == 0x1e and fm3 == 0x27d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x798d; op2val:0x3cad; +op3val:0x7a7d; valaddr_reg:x1; val_offset:2397*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2397*FLEN/8, x4, x2, x3) + +inst_835: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x386 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x328 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2bb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7786; op2val:0x3f28; +op3val:0x7abb; valaddr_reg:x1; val_offset:2400*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2400*FLEN/8, x4, x2, x3) + +inst_836: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x386 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x328 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2bb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7786; op2val:0x3f28; +op3val:0x7abb; valaddr_reg:x1; val_offset:2403*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2403*FLEN/8, x4, x2, x3) + +inst_837: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x386 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x328 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2bb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7786; op2val:0x3f28; +op3val:0x7abb; valaddr_reg:x1; val_offset:2406*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2406*FLEN/8, x4, x2, x3) + +inst_838: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x386 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x328 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2bb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7786; op2val:0x3f28; +op3val:0x7abb; valaddr_reg:x1; val_offset:2409*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2409*FLEN/8, x4, x2, x3) + +inst_839: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x386 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x328 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2bb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7786; op2val:0x3f28; +op3val:0x7abb; valaddr_reg:x1; val_offset:2412*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2412*FLEN/8, x4, x2, x3) + +inst_840: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x330 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x175 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0ef and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b30; op2val:0x3175; +op3val:0x70ef; valaddr_reg:x1; val_offset:2415*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2415*FLEN/8, x4, x2, x3) + +inst_841: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x330 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x175 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0ef and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b30; op2val:0x3175; +op3val:0x70ef; valaddr_reg:x1; val_offset:2418*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2418*FLEN/8, x4, x2, x3) + +inst_842: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x330 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x175 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0ef and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b30; op2val:0x3175; +op3val:0x70ef; valaddr_reg:x1; val_offset:2421*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2421*FLEN/8, x4, x2, x3) + +inst_843: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x330 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x175 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0ef and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b30; op2val:0x3175; +op3val:0x70ef; valaddr_reg:x1; val_offset:2424*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2424*FLEN/8, x4, x2, x3) + +inst_844: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x330 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x175 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0ef and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b30; op2val:0x3175; +op3val:0x70ef; valaddr_reg:x1; val_offset:2427*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2427*FLEN/8, x4, x2, x3) + +inst_845: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x359 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x38f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b59; op2val:0x3b8f; +op3val:0x7af4; valaddr_reg:x1; val_offset:2430*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2430*FLEN/8, x4, x2, x3) + +inst_846: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x359 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x38f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b59; op2val:0x3b8f; +op3val:0x7af4; valaddr_reg:x1; val_offset:2433*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2433*FLEN/8, x4, x2, x3) + +inst_847: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x359 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x38f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b59; op2val:0x3b8f; +op3val:0x7af4; valaddr_reg:x1; val_offset:2436*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2436*FLEN/8, x4, x2, x3) + +inst_848: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x359 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x38f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b59; op2val:0x3b8f; +op3val:0x7af4; valaddr_reg:x1; val_offset:2439*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2439*FLEN/8, x4, x2, x3) + +inst_849: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x359 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x38f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b59; op2val:0x3b8f; +op3val:0x7af4; valaddr_reg:x1; val_offset:2442*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2442*FLEN/8, x4, x2, x3) + +inst_850: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d6 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x24d and fs3 == 0 and fe3 == 0x1d and fm3 == 0x166 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ad6; op2val:0x364d; +op3val:0x7566; valaddr_reg:x1; val_offset:2445*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2445*FLEN/8, x4, x2, x3) + +inst_851: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d6 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x24d and fs3 == 0 and fe3 == 0x1d and fm3 == 0x166 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ad6; op2val:0x364d; +op3val:0x7566; valaddr_reg:x1; val_offset:2448*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2448*FLEN/8, x4, x2, x3) + +inst_852: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d6 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x24d and fs3 == 0 and fe3 == 0x1d and fm3 == 0x166 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ad6; op2val:0x364d; +op3val:0x7566; valaddr_reg:x1; val_offset:2451*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2451*FLEN/8, x4, x2, x3) + +inst_853: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d6 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x24d and fs3 == 0 and fe3 == 0x1d and fm3 == 0x166 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ad6; op2val:0x364d; +op3val:0x7566; valaddr_reg:x1; val_offset:2454*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2454*FLEN/8, x4, x2, x3) + +inst_854: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d6 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x24d and fs3 == 0 and fe3 == 0x1d and fm3 == 0x166 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ad6; op2val:0x364d; +op3val:0x7566; valaddr_reg:x1; val_offset:2457*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2457*FLEN/8, x4, x2, x3) + +inst_855: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x007 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x030 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7407; op2val:0x3830; +op3val:0x703f; valaddr_reg:x1; val_offset:2460*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2460*FLEN/8, x4, x2, x3) + +inst_856: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x007 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x030 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x03f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7407; op2val:0x3830; +op3val:0x703f; valaddr_reg:x1; val_offset:2463*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2463*FLEN/8, x4, x2, x3) + +inst_857: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x007 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x030 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x03f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7407; op2val:0x3830; +op3val:0x703f; valaddr_reg:x1; val_offset:2466*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2466*FLEN/8, x4, x2, x3) + +inst_858: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x007 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x030 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x03f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7407; op2val:0x3830; +op3val:0x703f; valaddr_reg:x1; val_offset:2469*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2469*FLEN/8, x4, x2, x3) + +inst_859: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x007 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x030 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x03f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7407; op2val:0x3830; +op3val:0x703f; valaddr_reg:x1; val_offset:2472*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2472*FLEN/8, x4, x2, x3) + +inst_860: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ee and fs2 == 0 and fe2 == 0x10 and fm2 == 0x09a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2d6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75ee; op2val:0x409a; +op3val:0x7ad6; valaddr_reg:x1; val_offset:2475*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2475*FLEN/8, x4, x2, x3) + +inst_861: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ee and fs2 == 0 and fe2 == 0x10 and fm2 == 0x09a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2d6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75ee; op2val:0x409a; +op3val:0x7ad6; valaddr_reg:x1; val_offset:2478*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2478*FLEN/8, x4, x2, x3) + +inst_862: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ee and fs2 == 0 and fe2 == 0x10 and fm2 == 0x09a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2d6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75ee; op2val:0x409a; +op3val:0x7ad6; valaddr_reg:x1; val_offset:2481*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2481*FLEN/8, x4, x2, x3) + +inst_863: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ee and fs2 == 0 and fe2 == 0x10 and fm2 == 0x09a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2d6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75ee; op2val:0x409a; +op3val:0x7ad6; valaddr_reg:x1; val_offset:2484*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2484*FLEN/8, x4, x2, x3) + +inst_864: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ee and fs2 == 0 and fe2 == 0x10 and fm2 == 0x09a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2d6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75ee; op2val:0x409a; +op3val:0x7ad6; valaddr_reg:x1; val_offset:2487*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2487*FLEN/8, x4, x2, x3) + +inst_865: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1cd and fs2 == 0 and fe2 == 0x08 and fm2 == 0x233 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x17f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75cd; op2val:0x2233; +op3val:0x5d7f; valaddr_reg:x1; val_offset:2490*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2490*FLEN/8, x4, x2, x3) + +inst_866: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1cd and fs2 == 0 and fe2 == 0x08 and fm2 == 0x233 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x17f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75cd; op2val:0x2233; +op3val:0x5d7f; valaddr_reg:x1; val_offset:2493*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2493*FLEN/8, x4, x2, x3) + +inst_867: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1cd and fs2 == 0 and fe2 == 0x08 and fm2 == 0x233 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x17f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75cd; op2val:0x2233; +op3val:0x5d7f; valaddr_reg:x1; val_offset:2496*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2496*FLEN/8, x4, x2, x3) + +inst_868: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1cd and fs2 == 0 and fe2 == 0x08 and fm2 == 0x233 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x17f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75cd; op2val:0x2233; +op3val:0x5d7f; valaddr_reg:x1; val_offset:2499*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2499*FLEN/8, x4, x2, x3) + +inst_869: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1cd and fs2 == 0 and fe2 == 0x08 and fm2 == 0x233 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x17f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75cd; op2val:0x2233; +op3val:0x5d7f; valaddr_reg:x1; val_offset:2502*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2502*FLEN/8, x4, x2, x3) + +inst_870: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0e0 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x047 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x147 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74e0; op2val:0x3447; +op3val:0x6d47; valaddr_reg:x1; val_offset:2505*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2505*FLEN/8, x4, x2, x3) + +inst_871: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0e0 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x047 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x147 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74e0; op2val:0x3447; +op3val:0x6d47; valaddr_reg:x1; val_offset:2508*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2508*FLEN/8, x4, x2, x3) + +inst_872: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0e0 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x047 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x147 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74e0; op2val:0x3447; +op3val:0x6d47; valaddr_reg:x1; val_offset:2511*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2511*FLEN/8, x4, x2, x3) + +inst_873: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0e0 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x047 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x147 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74e0; op2val:0x3447; +op3val:0x6d47; valaddr_reg:x1; val_offset:2514*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2514*FLEN/8, x4, x2, x3) + +inst_874: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0e0 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x047 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x147 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74e0; op2val:0x3447; +op3val:0x6d47; valaddr_reg:x1; val_offset:2517*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2517*FLEN/8, x4, x2, x3) + +inst_875: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fa and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0f1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x224 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fa; op2val:0x3cf1; +op3val:0x7a24; valaddr_reg:x1; val_offset:2520*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2520*FLEN/8, x4, x2, x3) + +inst_876: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fa and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0f1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x224 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fa; op2val:0x3cf1; +op3val:0x7a24; valaddr_reg:x1; val_offset:2523*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2523*FLEN/8, x4, x2, x3) + +inst_877: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fa and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0f1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x224 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fa; op2val:0x3cf1; +op3val:0x7a24; valaddr_reg:x1; val_offset:2526*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2526*FLEN/8, x4, x2, x3) + +inst_878: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fa and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0f1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x224 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fa; op2val:0x3cf1; +op3val:0x7a24; valaddr_reg:x1; val_offset:2529*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2529*FLEN/8, x4, x2, x3) + +inst_879: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fa and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0f1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x224 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fa; op2val:0x3cf1; +op3val:0x7a24; valaddr_reg:x1; val_offset:2532*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2532*FLEN/8, x4, x2, x3) + +inst_880: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x368 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x23b and fs3 == 0 and fe3 == 0x1b and fm3 == 0x1b5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b68; op2val:0x2e3b; +op3val:0x6db5; valaddr_reg:x1; val_offset:2535*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2535*FLEN/8, x4, x2, x3) + +inst_881: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x368 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x23b and fs3 == 0 and fe3 == 0x1b and fm3 == 0x1b5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b68; op2val:0x2e3b; +op3val:0x6db5; valaddr_reg:x1; val_offset:2538*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2538*FLEN/8, x4, x2, x3) + +inst_882: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x368 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x23b and fs3 == 0 and fe3 == 0x1b and fm3 == 0x1b5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b68; op2val:0x2e3b; +op3val:0x6db5; valaddr_reg:x1; val_offset:2541*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2541*FLEN/8, x4, x2, x3) + +inst_883: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x368 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x23b and fs3 == 0 and fe3 == 0x1b and fm3 == 0x1b5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b68; op2val:0x2e3b; +op3val:0x6db5; valaddr_reg:x1; val_offset:2544*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2544*FLEN/8, x4, x2, x3) + +inst_884: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x368 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x23b and fs3 == 0 and fe3 == 0x1b and fm3 == 0x1b5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b68; op2val:0x2e3b; +op3val:0x6db5; valaddr_reg:x1; val_offset:2547*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2547*FLEN/8, x4, x2, x3) + +inst_885: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x215 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x006 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7615; op2val:0x3555; +op3val:0x7006; valaddr_reg:x1; val_offset:2550*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2550*FLEN/8, x4, x2, x3) + +inst_886: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x215 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x006 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7615; op2val:0x3555; +op3val:0x7006; valaddr_reg:x1; val_offset:2553*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2553*FLEN/8, x4, x2, x3) + +inst_887: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x215 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x006 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7615; op2val:0x3555; +op3val:0x7006; valaddr_reg:x1; val_offset:2556*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2556*FLEN/8, x4, x2, x3) + +inst_888: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x215 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x006 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7615; op2val:0x3555; +op3val:0x7006; valaddr_reg:x1; val_offset:2559*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2559*FLEN/8, x4, x2, x3) + +inst_889: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x215 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x006 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7615; op2val:0x3555; +op3val:0x7006; valaddr_reg:x1; val_offset:2562*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2562*FLEN/8, x4, x2, x3) + +inst_890: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x347 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x35c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2b1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b47; op2val:0x3b5c; +op3val:0x7ab1; valaddr_reg:x1; val_offset:2565*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2565*FLEN/8, x4, x2, x3) + +inst_891: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x347 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x35c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2b1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b47; op2val:0x3b5c; +op3val:0x7ab1; valaddr_reg:x1; val_offset:2568*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2568*FLEN/8, x4, x2, x3) + +inst_892: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x347 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x35c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2b1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b47; op2val:0x3b5c; +op3val:0x7ab1; valaddr_reg:x1; val_offset:2571*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2571*FLEN/8, x4, x2, x3) + +inst_893: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x347 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x35c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2b1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b47; op2val:0x3b5c; +op3val:0x7ab1; valaddr_reg:x1; val_offset:2574*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2574*FLEN/8, x4, x2, x3) + +inst_894: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x347 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x35c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2b1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b47; op2val:0x3b5c; +op3val:0x7ab1; valaddr_reg:x1; val_offset:2577*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2577*FLEN/8, x4, x2, x3) + +inst_895: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x028 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x359 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3a0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7828; op2val:0x3f59; +op3val:0x7ba0; valaddr_reg:x1; val_offset:2580*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2580*FLEN/8, x4, x2, x3) + +inst_896: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x028 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x359 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3a0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7828; op2val:0x3f59; +op3val:0x7ba0; valaddr_reg:x1; val_offset:2583*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2583*FLEN/8, x4, x2, x3) + +inst_897: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x028 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x359 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3a0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7828; op2val:0x3f59; +op3val:0x7ba0; valaddr_reg:x1; val_offset:2586*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2586*FLEN/8, x4, x2, x3) + +inst_898: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x028 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x359 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3a0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7828; op2val:0x3f59; +op3val:0x7ba0; valaddr_reg:x1; val_offset:2589*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2589*FLEN/8, x4, x2, x3) + +inst_899: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x028 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x359 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3a0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7828; op2val:0x3f59; +op3val:0x7ba0; valaddr_reg:x1; val_offset:2592*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2592*FLEN/8, x4, x2, x3) + +inst_900: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x029 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1fa and fs3 == 0 and fe3 == 0x1e and fm3 == 0x235 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7829; op2val:0x3dfa; +op3val:0x7a35; valaddr_reg:x1; val_offset:2595*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2595*FLEN/8, x4, x2, x3) + +inst_901: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x029 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1fa and fs3 == 0 and fe3 == 0x1e and fm3 == 0x235 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7829; op2val:0x3dfa; +op3val:0x7a35; valaddr_reg:x1; val_offset:2598*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2598*FLEN/8, x4, x2, x3) + +inst_902: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x029 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1fa and fs3 == 0 and fe3 == 0x1e and fm3 == 0x235 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7829; op2val:0x3dfa; +op3val:0x7a35; valaddr_reg:x1; val_offset:2601*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2601*FLEN/8, x4, x2, x3) + +inst_903: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x029 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1fa and fs3 == 0 and fe3 == 0x1e and fm3 == 0x235 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7829; op2val:0x3dfa; +op3val:0x7a35; valaddr_reg:x1; val_offset:2604*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2604*FLEN/8, x4, x2, x3) + +inst_904: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x029 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1fa and fs3 == 0 and fe3 == 0x1e and fm3 == 0x235 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7829; op2val:0x3dfa; +op3val:0x7a35; valaddr_reg:x1; val_offset:2607*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2607*FLEN/8, x4, x2, x3) + +inst_905: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ce and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1fc and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1d3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77ce; op2val:0x39fc; +op3val:0x75d3; valaddr_reg:x1; val_offset:2610*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2610*FLEN/8, x4, x2, x3) + +inst_906: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ce and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1fc and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1d3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77ce; op2val:0x39fc; +op3val:0x75d3; valaddr_reg:x1; val_offset:2613*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2613*FLEN/8, x4, x2, x3) + +inst_907: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ce and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1fc and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1d3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77ce; op2val:0x39fc; +op3val:0x75d3; valaddr_reg:x1; val_offset:2616*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2616*FLEN/8, x4, x2, x3) + +inst_908: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ce and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1fc and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1d3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77ce; op2val:0x39fc; +op3val:0x75d3; valaddr_reg:x1; val_offset:2619*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2619*FLEN/8, x4, x2, x3) + +inst_909: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ce and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1fc and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1d3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77ce; op2val:0x39fc; +op3val:0x75d3; valaddr_reg:x1; val_offset:2622*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2622*FLEN/8, x4, x2, x3) + +inst_910: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2c7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ba and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bf3; op2val:0x3ac7; +op3val:0x7aba; valaddr_reg:x1; val_offset:2625*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2625*FLEN/8, x4, x2, x3) + +inst_911: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2c7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ba and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bf3; op2val:0x3ac7; +op3val:0x7aba; valaddr_reg:x1; val_offset:2628*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2628*FLEN/8, x4, x2, x3) + +inst_912: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2c7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ba and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bf3; op2val:0x3ac7; +op3val:0x7aba; valaddr_reg:x1; val_offset:2631*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2631*FLEN/8, x4, x2, x3) + +inst_913: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2c7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ba and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bf3; op2val:0x3ac7; +op3val:0x7aba; valaddr_reg:x1; val_offset:2634*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2634*FLEN/8, x4, x2, x3) + +inst_914: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2c7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ba and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bf3; op2val:0x3ac7; +op3val:0x7aba; valaddr_reg:x1; val_offset:2637*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2637*FLEN/8, x4, x2, x3) + +inst_915: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0bb and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1de and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ef and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78bb; op2val:0x3dde; +op3val:0x7aef; valaddr_reg:x1; val_offset:2640*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2640*FLEN/8, x4, x2, x3) + +inst_916: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0bb and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1de and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ef and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78bb; op2val:0x3dde; +op3val:0x7aef; valaddr_reg:x1; val_offset:2643*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2643*FLEN/8, x4, x2, x3) + +inst_917: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0bb and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1de and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ef and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78bb; op2val:0x3dde; +op3val:0x7aef; valaddr_reg:x1; val_offset:2646*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2646*FLEN/8, x4, x2, x3) + +inst_918: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0bb and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1de and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ef and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78bb; op2val:0x3dde; +op3val:0x7aef; valaddr_reg:x1; val_offset:2649*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2649*FLEN/8, x4, x2, x3) + +inst_919: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0bb and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1de and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ef and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78bb; op2val:0x3dde; +op3val:0x7aef; valaddr_reg:x1; val_offset:2652*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2652*FLEN/8, x4, x2, x3) + +inst_920: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x131 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0eb and fs3 == 0 and fe3 == 0x1e and fm3 == 0x261 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7931; op2val:0x3ceb; +op3val:0x7a61; valaddr_reg:x1; val_offset:2655*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2655*FLEN/8, x4, x2, x3) + +inst_921: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x131 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0eb and fs3 == 0 and fe3 == 0x1e and fm3 == 0x261 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7931; op2val:0x3ceb; +op3val:0x7a61; valaddr_reg:x1; val_offset:2658*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2658*FLEN/8, x4, x2, x3) + +inst_922: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x131 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0eb and fs3 == 0 and fe3 == 0x1e and fm3 == 0x261 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7931; op2val:0x3ceb; +op3val:0x7a61; valaddr_reg:x1; val_offset:2661*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2661*FLEN/8, x4, x2, x3) + +inst_923: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x131 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0eb and fs3 == 0 and fe3 == 0x1e and fm3 == 0x261 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7931; op2val:0x3ceb; +op3val:0x7a61; valaddr_reg:x1; val_offset:2664*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2664*FLEN/8, x4, x2, x3) +RVTEST_SIGBASE(x2,signature_x2_7) + +inst_924: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x131 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0eb and fs3 == 0 and fe3 == 0x1e and fm3 == 0x261 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7931; op2val:0x3ceb; +op3val:0x7a61; valaddr_reg:x1; val_offset:2667*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2667*FLEN/8, x4, x2, x3) + +inst_925: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x044 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3f0 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x034 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c44; op2val:0x3ff0; +op3val:0x7034; valaddr_reg:x1; val_offset:2670*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2670*FLEN/8, x4, x2, x3) + +inst_926: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x044 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3f0 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x034 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c44; op2val:0x3ff0; +op3val:0x7034; valaddr_reg:x1; val_offset:2673*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2673*FLEN/8, x4, x2, x3) + +inst_927: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x044 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3f0 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x034 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c44; op2val:0x3ff0; +op3val:0x7034; valaddr_reg:x1; val_offset:2676*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2676*FLEN/8, x4, x2, x3) + +inst_928: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x044 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3f0 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x034 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c44; op2val:0x3ff0; +op3val:0x7034; valaddr_reg:x1; val_offset:2679*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2679*FLEN/8, x4, x2, x3) + +inst_929: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x044 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3f0 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x034 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c44; op2val:0x3ff0; +op3val:0x7034; valaddr_reg:x1; val_offset:2682*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2682*FLEN/8, x4, x2, x3) + +inst_930: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2ff and fs2 == 0 and fe2 == 0x11 and fm2 == 0x185 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0d2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6eff; op2val:0x4585; +op3val:0x78d2; valaddr_reg:x1; val_offset:2685*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2685*FLEN/8, x4, x2, x3) + +inst_931: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2ff and fs2 == 0 and fe2 == 0x11 and fm2 == 0x185 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0d2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6eff; op2val:0x4585; +op3val:0x78d2; valaddr_reg:x1; val_offset:2688*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2688*FLEN/8, x4, x2, x3) + +inst_932: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2ff and fs2 == 0 and fe2 == 0x11 and fm2 == 0x185 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0d2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6eff; op2val:0x4585; +op3val:0x78d2; valaddr_reg:x1; val_offset:2691*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2691*FLEN/8, x4, x2, x3) + +inst_933: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2ff and fs2 == 0 and fe2 == 0x11 and fm2 == 0x185 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0d2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6eff; op2val:0x4585; +op3val:0x78d2; valaddr_reg:x1; val_offset:2694*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2694*FLEN/8, x4, x2, x3) + +inst_934: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2ff and fs2 == 0 and fe2 == 0x11 and fm2 == 0x185 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0d2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6eff; op2val:0x4585; +op3val:0x78d2; valaddr_reg:x1; val_offset:2697*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2697*FLEN/8, x4, x2, x3) + +inst_935: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c1 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2f1 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0f6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79c1; op2val:0x32f1; +op3val:0x70f6; valaddr_reg:x1; val_offset:2700*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2700*FLEN/8, x4, x2, x3) + +inst_936: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c1 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2f1 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0f6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79c1; op2val:0x32f1; +op3val:0x70f6; valaddr_reg:x1; val_offset:2703*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2703*FLEN/8, x4, x2, x3) + +inst_937: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c1 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2f1 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0f6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79c1; op2val:0x32f1; +op3val:0x70f6; valaddr_reg:x1; val_offset:2706*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2706*FLEN/8, x4, x2, x3) + +inst_938: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c1 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2f1 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0f6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79c1; op2val:0x32f1; +op3val:0x70f6; valaddr_reg:x1; val_offset:2709*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2709*FLEN/8, x4, x2, x3) + +inst_939: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c1 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2f1 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0f6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79c1; op2val:0x32f1; +op3val:0x70f6; valaddr_reg:x1; val_offset:2712*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2712*FLEN/8, x4, x2, x3) + +inst_940: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00a and fs2 == 0 and fe2 == 0x0c and fm2 == 0x342 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x344 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x780a; op2val:0x3342; +op3val:0x6f44; valaddr_reg:x1; val_offset:2715*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2715*FLEN/8, x4, x2, x3) + +inst_941: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00a and fs2 == 0 and fe2 == 0x0c and fm2 == 0x342 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x344 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x780a; op2val:0x3342; +op3val:0x6f44; valaddr_reg:x1; val_offset:2718*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2718*FLEN/8, x4, x2, x3) + +inst_942: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00a and fs2 == 0 and fe2 == 0x0c and fm2 == 0x342 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x344 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x780a; op2val:0x3342; +op3val:0x6f44; valaddr_reg:x1; val_offset:2721*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2721*FLEN/8, x4, x2, x3) + +inst_943: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00a and fs2 == 0 and fe2 == 0x0c and fm2 == 0x342 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x344 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x780a; op2val:0x3342; +op3val:0x6f44; valaddr_reg:x1; val_offset:2724*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2724*FLEN/8, x4, x2, x3) + +inst_944: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00a and fs2 == 0 and fe2 == 0x0c and fm2 == 0x342 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x344 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x780a; op2val:0x3342; +op3val:0x6f44; valaddr_reg:x1; val_offset:2727*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2727*FLEN/8, x4, x2, x3) + +inst_945: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x17f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x086 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x23a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x797f; op2val:0x3c86; +op3val:0x7a3a; valaddr_reg:x1; val_offset:2730*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2730*FLEN/8, x4, x2, x3) + +inst_946: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x17f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x086 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x23a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x797f; op2val:0x3c86; +op3val:0x7a3a; valaddr_reg:x1; val_offset:2733*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2733*FLEN/8, x4, x2, x3) + +inst_947: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x17f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x086 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x23a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x797f; op2val:0x3c86; +op3val:0x7a3a; valaddr_reg:x1; val_offset:2736*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2736*FLEN/8, x4, x2, x3) + +inst_948: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x17f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x086 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x23a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x797f; op2val:0x3c86; +op3val:0x7a3a; valaddr_reg:x1; val_offset:2739*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2739*FLEN/8, x4, x2, x3) + +inst_949: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x17f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x086 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x23a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x797f; op2val:0x3c86; +op3val:0x7a3a; valaddr_reg:x1; val_offset:2742*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2742*FLEN/8, x4, x2, x3) + +inst_950: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x18b and fs2 == 0 and fe2 == 0x12 and fm2 == 0x1a5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3d6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d8b; op2val:0x49a5; +op3val:0x7bd6; valaddr_reg:x1; val_offset:2745*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2745*FLEN/8, x4, x2, x3) + +inst_951: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x18b and fs2 == 0 and fe2 == 0x12 and fm2 == 0x1a5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3d6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d8b; op2val:0x49a5; +op3val:0x7bd6; valaddr_reg:x1; val_offset:2748*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2748*FLEN/8, x4, x2, x3) + +inst_952: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x18b and fs2 == 0 and fe2 == 0x12 and fm2 == 0x1a5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3d6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d8b; op2val:0x49a5; +op3val:0x7bd6; valaddr_reg:x1; val_offset:2751*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2751*FLEN/8, x4, x2, x3) + +inst_953: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x18b and fs2 == 0 and fe2 == 0x12 and fm2 == 0x1a5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3d6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d8b; op2val:0x49a5; +op3val:0x7bd6; valaddr_reg:x1; val_offset:2754*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2754*FLEN/8, x4, x2, x3) + +inst_954: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x18b and fs2 == 0 and fe2 == 0x12 and fm2 == 0x1a5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3d6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d8b; op2val:0x49a5; +op3val:0x7bd6; valaddr_reg:x1; val_offset:2757*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2757*FLEN/8, x4, x2, x3) + +inst_955: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x151 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1f6 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x3fd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7951; op2val:0x31f6; +op3val:0x6ffd; valaddr_reg:x1; val_offset:2760*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2760*FLEN/8, x4, x2, x3) + +inst_956: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x151 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1f6 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x3fd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7951; op2val:0x31f6; +op3val:0x6ffd; valaddr_reg:x1; val_offset:2763*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2763*FLEN/8, x4, x2, x3) + +inst_957: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x151 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1f6 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x3fd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7951; op2val:0x31f6; +op3val:0x6ffd; valaddr_reg:x1; val_offset:2766*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2766*FLEN/8, x4, x2, x3) + +inst_958: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x151 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1f6 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x3fd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7951; op2val:0x31f6; +op3val:0x6ffd; valaddr_reg:x1; val_offset:2769*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2769*FLEN/8, x4, x2, x3) + +inst_959: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x151 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1f6 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x3fd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7951; op2val:0x31f6; +op3val:0x6ffd; valaddr_reg:x1; val_offset:2772*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2772*FLEN/8, x4, x2, x3) + +inst_960: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x19d and fs2 == 0 and fe2 == 0x0d and fm2 == 0x32b and fs3 == 0 and fe3 == 0x1c and fm3 == 0x10f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x759d; op2val:0x372b; +op3val:0x710f; valaddr_reg:x1; val_offset:2775*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2775*FLEN/8, x4, x2, x3) + +inst_961: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x19d and fs2 == 0 and fe2 == 0x0d and fm2 == 0x32b and fs3 == 0 and fe3 == 0x1c and fm3 == 0x10f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x759d; op2val:0x372b; +op3val:0x710f; valaddr_reg:x1; val_offset:2778*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2778*FLEN/8, x4, x2, x3) + +inst_962: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x19d and fs2 == 0 and fe2 == 0x0d and fm2 == 0x32b and fs3 == 0 and fe3 == 0x1c and fm3 == 0x10f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x759d; op2val:0x372b; +op3val:0x710f; valaddr_reg:x1; val_offset:2781*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2781*FLEN/8, x4, x2, x3) + +inst_963: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x19d and fs2 == 0 and fe2 == 0x0d and fm2 == 0x32b and fs3 == 0 and fe3 == 0x1c and fm3 == 0x10f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x759d; op2val:0x372b; +op3val:0x710f; valaddr_reg:x1; val_offset:2784*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2784*FLEN/8, x4, x2, x3) + +inst_964: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x19d and fs2 == 0 and fe2 == 0x0d and fm2 == 0x32b and fs3 == 0 and fe3 == 0x1c and fm3 == 0x10f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x759d; op2val:0x372b; +op3val:0x710f; valaddr_reg:x1; val_offset:2787*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2787*FLEN/8, x4, x2, x3) + +inst_965: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d2 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x108 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x354 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79d2; op2val:0x3d08; +op3val:0x7b54; valaddr_reg:x1; val_offset:2790*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2790*FLEN/8, x4, x2, x3) + +inst_966: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d2 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x108 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x354 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79d2; op2val:0x3d08; +op3val:0x7b54; valaddr_reg:x1; val_offset:2793*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2793*FLEN/8, x4, x2, x3) + +inst_967: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d2 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x108 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x354 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79d2; op2val:0x3d08; +op3val:0x7b54; valaddr_reg:x1; val_offset:2796*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2796*FLEN/8, x4, x2, x3) + +inst_968: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d2 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x108 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x354 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79d2; op2val:0x3d08; +op3val:0x7b54; valaddr_reg:x1; val_offset:2799*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2799*FLEN/8, x4, x2, x3) + +inst_969: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d2 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x108 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x354 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79d2; op2val:0x3d08; +op3val:0x7b54; valaddr_reg:x1; val_offset:2802*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2802*FLEN/8, x4, x2, x3) + +inst_970: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x19a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x02e and fs3 == 0 and fe3 == 0x1c and fm3 == 0x1e2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x719a; op2val:0x3c2e; +op3val:0x71e2; valaddr_reg:x1; val_offset:2805*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2805*FLEN/8, x4, x2, x3) + +inst_971: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x19a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x02e and fs3 == 0 and fe3 == 0x1c and fm3 == 0x1e2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x719a; op2val:0x3c2e; +op3val:0x71e2; valaddr_reg:x1; val_offset:2808*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2808*FLEN/8, x4, x2, x3) + +inst_972: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x19a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x02e and fs3 == 0 and fe3 == 0x1c and fm3 == 0x1e2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x719a; op2val:0x3c2e; +op3val:0x71e2; valaddr_reg:x1; val_offset:2811*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2811*FLEN/8, x4, x2, x3) + +inst_973: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x19a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x02e and fs3 == 0 and fe3 == 0x1c and fm3 == 0x1e2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x719a; op2val:0x3c2e; +op3val:0x71e2; valaddr_reg:x1; val_offset:2814*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2814*FLEN/8, x4, x2, x3) + +inst_974: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x19a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x02e and fs3 == 0 and fe3 == 0x1c and fm3 == 0x1e2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x719a; op2val:0x3c2e; +op3val:0x71e2; valaddr_reg:x1; val_offset:2817*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2817*FLEN/8, x4, x2, x3) + +inst_975: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x107 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x175 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2df and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7907; op2val:0x3d75; +op3val:0x7adf; valaddr_reg:x1; val_offset:2820*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2820*FLEN/8, x4, x2, x3) + +inst_976: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x107 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x175 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2df and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7907; op2val:0x3d75; +op3val:0x7adf; valaddr_reg:x1; val_offset:2823*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2823*FLEN/8, x4, x2, x3) + +inst_977: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x107 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x175 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2df and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7907; op2val:0x3d75; +op3val:0x7adf; valaddr_reg:x1; val_offset:2826*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2826*FLEN/8, x4, x2, x3) + +inst_978: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x107 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x175 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2df and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7907; op2val:0x3d75; +op3val:0x7adf; valaddr_reg:x1; val_offset:2829*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2829*FLEN/8, x4, x2, x3) + +inst_979: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x107 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x175 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2df and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7907; op2val:0x3d75; +op3val:0x7adf; valaddr_reg:x1; val_offset:2832*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2832*FLEN/8, x4, x2, x3) + +inst_980: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1e8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0f4 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x352 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79e8; op2val:0x38f4; +op3val:0x7752; valaddr_reg:x1; val_offset:2835*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2835*FLEN/8, x4, x2, x3) + +inst_981: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1e8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0f4 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x352 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79e8; op2val:0x38f4; +op3val:0x7752; valaddr_reg:x1; val_offset:2838*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2838*FLEN/8, x4, x2, x3) + +inst_982: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1e8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0f4 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x352 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79e8; op2val:0x38f4; +op3val:0x7752; valaddr_reg:x1; val_offset:2841*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2841*FLEN/8, x4, x2, x3) + +inst_983: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1e8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0f4 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x352 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79e8; op2val:0x38f4; +op3val:0x7752; valaddr_reg:x1; val_offset:2844*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2844*FLEN/8, x4, x2, x3) + +inst_984: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1e8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0f4 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x352 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79e8; op2val:0x38f4; +op3val:0x7752; valaddr_reg:x1; val_offset:2847*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2847*FLEN/8, x4, x2, x3) + +inst_985: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x311 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x18e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0e9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f11; op2val:0x458e; +op3val:0x78e9; valaddr_reg:x1; val_offset:2850*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2850*FLEN/8, x4, x2, x3) + +inst_986: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x311 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x18e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0e9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f11; op2val:0x458e; +op3val:0x78e9; valaddr_reg:x1; val_offset:2853*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2853*FLEN/8, x4, x2, x3) + +inst_987: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x311 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x18e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0e9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f11; op2val:0x458e; +op3val:0x78e9; valaddr_reg:x1; val_offset:2856*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2856*FLEN/8, x4, x2, x3) + +inst_988: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x311 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x18e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0e9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f11; op2val:0x458e; +op3val:0x78e9; valaddr_reg:x1; val_offset:2859*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2859*FLEN/8, x4, x2, x3) + +inst_989: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x311 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x18e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0e9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f11; op2val:0x458e; +op3val:0x78e9; valaddr_reg:x1; val_offset:2862*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2862*FLEN/8, x4, x2, x3) + +inst_990: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x30e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x26d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7749; op2val:0x3f0e; +op3val:0x7a6d; valaddr_reg:x1; val_offset:2865*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2865*FLEN/8, x4, x2, x3) + +inst_991: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x30e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x26d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7749; op2val:0x3f0e; +op3val:0x7a6d; valaddr_reg:x1; val_offset:2868*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2868*FLEN/8, x4, x2, x3) + +inst_992: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x30e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x26d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7749; op2val:0x3f0e; +op3val:0x7a6d; valaddr_reg:x1; val_offset:2871*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2871*FLEN/8, x4, x2, x3) + +inst_993: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x30e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x26d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7749; op2val:0x3f0e; +op3val:0x7a6d; valaddr_reg:x1; val_offset:2874*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2874*FLEN/8, x4, x2, x3) + +inst_994: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x30e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x26d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7749; op2val:0x3f0e; +op3val:0x7a6d; valaddr_reg:x1; val_offset:2877*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2877*FLEN/8, x4, x2, x3) + +inst_995: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x092 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x122 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1de and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7892; op2val:0x3d22; +op3val:0x79de; valaddr_reg:x1; val_offset:2880*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2880*FLEN/8, x4, x2, x3) + +inst_996: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x092 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x122 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1de and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7892; op2val:0x3d22; +op3val:0x79de; valaddr_reg:x1; val_offset:2883*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2883*FLEN/8, x4, x2, x3) + +inst_997: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x092 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x122 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1de and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7892; op2val:0x3d22; +op3val:0x79de; valaddr_reg:x1; val_offset:2886*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2886*FLEN/8, x4, x2, x3) + +inst_998: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x092 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x122 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1de and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7892; op2val:0x3d22; +op3val:0x79de; valaddr_reg:x1; val_offset:2889*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2889*FLEN/8, x4, x2, x3) + +inst_999: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x092 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x122 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1de and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7892; op2val:0x3d22; +op3val:0x79de; valaddr_reg:x1; val_offset:2892*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2892*FLEN/8, x4, x2, x3) + +inst_1000: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x128 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x101 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bc3; op2val:0x3928; +op3val:0x7901; valaddr_reg:x1; val_offset:2895*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2895*FLEN/8, x4, x2, x3) + +inst_1001: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x128 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x101 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bc3; op2val:0x3928; +op3val:0x7901; valaddr_reg:x1; val_offset:2898*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2898*FLEN/8, x4, x2, x3) + +inst_1002: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x128 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x101 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bc3; op2val:0x3928; +op3val:0x7901; valaddr_reg:x1; val_offset:2901*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2901*FLEN/8, x4, x2, x3) + +inst_1003: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x128 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x101 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bc3; op2val:0x3928; +op3val:0x7901; valaddr_reg:x1; val_offset:2904*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2904*FLEN/8, x4, x2, x3) + +inst_1004: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x128 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x101 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bc3; op2val:0x3928; +op3val:0x7901; valaddr_reg:x1; val_offset:2907*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2907*FLEN/8, x4, x2, x3) + +inst_1005: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x34a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0ce and fs3 == 0 and fe3 == 0x1d and fm3 == 0x061 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b4a; op2val:0x34ce; +op3val:0x7461; valaddr_reg:x1; val_offset:2910*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2910*FLEN/8, x4, x2, x3) + +inst_1006: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x34a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0ce and fs3 == 0 and fe3 == 0x1d and fm3 == 0x061 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b4a; op2val:0x34ce; +op3val:0x7461; valaddr_reg:x1; val_offset:2913*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2913*FLEN/8, x4, x2, x3) + +inst_1007: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x34a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0ce and fs3 == 0 and fe3 == 0x1d and fm3 == 0x061 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b4a; op2val:0x34ce; +op3val:0x7461; valaddr_reg:x1; val_offset:2916*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2916*FLEN/8, x4, x2, x3) + +inst_1008: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x34a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0ce and fs3 == 0 and fe3 == 0x1d and fm3 == 0x061 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b4a; op2val:0x34ce; +op3val:0x7461; valaddr_reg:x1; val_offset:2919*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2919*FLEN/8, x4, x2, x3) + +inst_1009: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x34a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0ce and fs3 == 0 and fe3 == 0x1d and fm3 == 0x061 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b4a; op2val:0x34ce; +op3val:0x7461; valaddr_reg:x1; val_offset:2922*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2922*FLEN/8, x4, x2, x3) + +inst_1010: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x257 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x073 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x30e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5657; op2val:0x6073; +op3val:0x7b0e; valaddr_reg:x1; val_offset:2925*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2925*FLEN/8, x4, x2, x3) + +inst_1011: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x257 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x073 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x30e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5657; op2val:0x6073; +op3val:0x7b0e; valaddr_reg:x1; val_offset:2928*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2928*FLEN/8, x4, x2, x3) + +inst_1012: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x257 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x073 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x30e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5657; op2val:0x6073; +op3val:0x7b0e; valaddr_reg:x1; val_offset:2931*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2931*FLEN/8, x4, x2, x3) + +inst_1013: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x257 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x073 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x30e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5657; op2val:0x6073; +op3val:0x7b0e; valaddr_reg:x1; val_offset:2934*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2934*FLEN/8, x4, x2, x3) + +inst_1014: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x257 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x073 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x30e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5657; op2val:0x6073; +op3val:0x7b0e; valaddr_reg:x1; val_offset:2937*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2937*FLEN/8, x4, x2, x3) + +inst_1015: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x027 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3f1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x67a5; op2val:0x5027; +op3val:0x7bf1; valaddr_reg:x1; val_offset:2940*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2940*FLEN/8, x4, x2, x3) + +inst_1016: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x027 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3f1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x67a5; op2val:0x5027; +op3val:0x7bf1; valaddr_reg:x1; val_offset:2943*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2943*FLEN/8, x4, x2, x3) + +inst_1017: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x027 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3f1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x67a5; op2val:0x5027; +op3val:0x7bf1; valaddr_reg:x1; val_offset:2946*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2946*FLEN/8, x4, x2, x3) + +inst_1018: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x027 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3f1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x67a5; op2val:0x5027; +op3val:0x7bf1; valaddr_reg:x1; val_offset:2949*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2949*FLEN/8, x4, x2, x3) + +inst_1019: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x027 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3f1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x67a5; op2val:0x5027; +op3val:0x7bf1; valaddr_reg:x1; val_offset:2952*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2952*FLEN/8, x4, x2, x3) + +inst_1020: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x04d and fs3 == 0 and fe3 == 0x1a and fm3 == 0x3d7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7749; op2val:0x304d; +op3val:0x6bd7; valaddr_reg:x1; val_offset:2955*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2955*FLEN/8, x4, x2, x3) + +inst_1021: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x04d and fs3 == 0 and fe3 == 0x1a and fm3 == 0x3d7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7749; op2val:0x304d; +op3val:0x6bd7; valaddr_reg:x1; val_offset:2958*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2958*FLEN/8, x4, x2, x3) + +inst_1022: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x04d and fs3 == 0 and fe3 == 0x1a and fm3 == 0x3d7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7749; op2val:0x304d; +op3val:0x6bd7; valaddr_reg:x1; val_offset:2961*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2961*FLEN/8, x4, x2, x3) + +inst_1023: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x04d and fs3 == 0 and fe3 == 0x1a and fm3 == 0x3d7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7749; op2val:0x304d; +op3val:0x6bd7; valaddr_reg:x1; val_offset:2964*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2964*FLEN/8, x4, x2, x3) + +inst_1024: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x04d and fs3 == 0 and fe3 == 0x1a and fm3 == 0x3d7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7749; op2val:0x304d; +op3val:0x6bd7; valaddr_reg:x1; val_offset:2967*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2967*FLEN/8, x4, x2, x3) + +inst_1025: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x064 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x140 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1c4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7464; op2val:0x4140; +op3val:0x79c4; valaddr_reg:x1; val_offset:2970*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2970*FLEN/8, x4, x2, x3) + +inst_1026: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x064 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x140 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1c4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7464; op2val:0x4140; +op3val:0x79c4; valaddr_reg:x1; val_offset:2973*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2973*FLEN/8, x4, x2, x3) + +inst_1027: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x064 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x140 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1c4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7464; op2val:0x4140; +op3val:0x79c4; valaddr_reg:x1; val_offset:2976*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2976*FLEN/8, x4, x2, x3) + +inst_1028: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x064 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x140 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1c4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7464; op2val:0x4140; +op3val:0x79c4; valaddr_reg:x1; val_offset:2979*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2979*FLEN/8, x4, x2, x3) + +inst_1029: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x064 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x140 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1c4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7464; op2val:0x4140; +op3val:0x79c4; valaddr_reg:x1; val_offset:2982*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2982*FLEN/8, x4, x2, x3) + +inst_1030: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x224 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x27f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0fd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7624; op2val:0x3e7f; +op3val:0x78fd; valaddr_reg:x1; val_offset:2985*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2985*FLEN/8, x4, x2, x3) + +inst_1031: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x224 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x27f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0fd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7624; op2val:0x3e7f; +op3val:0x78fd; valaddr_reg:x1; val_offset:2988*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2988*FLEN/8, x4, x2, x3) + +inst_1032: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x224 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x27f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0fd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7624; op2val:0x3e7f; +op3val:0x78fd; valaddr_reg:x1; val_offset:2991*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2991*FLEN/8, x4, x2, x3) + +inst_1033: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x224 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x27f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0fd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7624; op2val:0x3e7f; +op3val:0x78fd; valaddr_reg:x1; val_offset:2994*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2994*FLEN/8, x4, x2, x3) + +inst_1034: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x224 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x27f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0fd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7624; op2val:0x3e7f; +op3val:0x78fd; valaddr_reg:x1; val_offset:2997*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2997*FLEN/8, x4, x2, x3) + +inst_1035: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x285 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x019 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ae and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e85; op2val:0x4819; +op3val:0x7aae; valaddr_reg:x1; val_offset:3000*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3000*FLEN/8, x4, x2, x3) + +inst_1036: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x285 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x019 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ae and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e85; op2val:0x4819; +op3val:0x7aae; valaddr_reg:x1; val_offset:3003*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3003*FLEN/8, x4, x2, x3) + +inst_1037: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x285 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x019 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ae and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e85; op2val:0x4819; +op3val:0x7aae; valaddr_reg:x1; val_offset:3006*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3006*FLEN/8, x4, x2, x3) + +inst_1038: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x285 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x019 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ae and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e85; op2val:0x4819; +op3val:0x7aae; valaddr_reg:x1; val_offset:3009*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3009*FLEN/8, x4, x2, x3) + +inst_1039: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x285 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x019 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ae and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e85; op2val:0x4819; +op3val:0x7aae; valaddr_reg:x1; val_offset:3012*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3012*FLEN/8, x4, x2, x3) + +inst_1040: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1f7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x076 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75f7; op2val:0x4076; +op3val:0x7aa8; valaddr_reg:x1; val_offset:3015*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3015*FLEN/8, x4, x2, x3) + +inst_1041: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1f7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x076 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75f7; op2val:0x4076; +op3val:0x7aa8; valaddr_reg:x1; val_offset:3018*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3018*FLEN/8, x4, x2, x3) + +inst_1042: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1f7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x076 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75f7; op2val:0x4076; +op3val:0x7aa8; valaddr_reg:x1; val_offset:3021*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3021*FLEN/8, x4, x2, x3) + +inst_1043: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1f7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x076 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75f7; op2val:0x4076; +op3val:0x7aa8; valaddr_reg:x1; val_offset:3024*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3024*FLEN/8, x4, x2, x3) + +inst_1044: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1f7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x076 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75f7; op2val:0x4076; +op3val:0x7aa8; valaddr_reg:x1; val_offset:3027*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3027*FLEN/8, x4, x2, x3) + +inst_1045: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0b6 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x087 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70b6; op2val:0x4487; +op3val:0x7955; valaddr_reg:x1; val_offset:3030*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3030*FLEN/8, x4, x2, x3) + +inst_1046: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0b6 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x087 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x155 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70b6; op2val:0x4487; +op3val:0x7955; valaddr_reg:x1; val_offset:3033*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3033*FLEN/8, x4, x2, x3) + +inst_1047: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0b6 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x087 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x155 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70b6; op2val:0x4487; +op3val:0x7955; valaddr_reg:x1; val_offset:3036*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3036*FLEN/8, x4, x2, x3) + +inst_1048: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0b6 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x087 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x155 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70b6; op2val:0x4487; +op3val:0x7955; valaddr_reg:x1; val_offset:3039*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3039*FLEN/8, x4, x2, x3) + +inst_1049: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0b6 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x087 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x155 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70b6; op2val:0x4487; +op3val:0x7955; valaddr_reg:x1; val_offset:3042*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3042*FLEN/8, x4, x2, x3) + +inst_1050: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x380 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2e5 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x277 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7780; op2val:0x3ae5; +op3val:0x7677; valaddr_reg:x1; val_offset:3045*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3045*FLEN/8, x4, x2, x3) + +inst_1051: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x380 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2e5 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x277 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7780; op2val:0x3ae5; +op3val:0x7677; valaddr_reg:x1; val_offset:3048*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3048*FLEN/8, x4, x2, x3) +RVTEST_SIGBASE(x2,signature_x2_8) + +inst_1052: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x380 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2e5 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x277 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7780; op2val:0x3ae5; +op3val:0x7677; valaddr_reg:x1; val_offset:3051*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3051*FLEN/8, x4, x2, x3) + +inst_1053: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x380 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2e5 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x277 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7780; op2val:0x3ae5; +op3val:0x7677; valaddr_reg:x1; val_offset:3054*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3054*FLEN/8, x4, x2, x3) + +inst_1054: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x380 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2e5 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x277 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7780; op2val:0x3ae5; +op3val:0x7677; valaddr_reg:x1; val_offset:3057*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3057*FLEN/8, x4, x2, x3) + +inst_1055: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x0f3 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x2de and fs3 == 0 and fe3 == 0x1e and fm3 == 0x040 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x64f3; op2val:0x4ede; +op3val:0x7840; valaddr_reg:x1; val_offset:3060*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3060*FLEN/8, x4, x2, x3) + +inst_1056: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x0f3 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x2de and fs3 == 0 and fe3 == 0x1e and fm3 == 0x040 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x64f3; op2val:0x4ede; +op3val:0x7840; valaddr_reg:x1; val_offset:3063*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3063*FLEN/8, x4, x2, x3) + +inst_1057: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x0f3 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x2de and fs3 == 0 and fe3 == 0x1e and fm3 == 0x040 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x64f3; op2val:0x4ede; +op3val:0x7840; valaddr_reg:x1; val_offset:3066*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3066*FLEN/8, x4, x2, x3) + +inst_1058: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x0f3 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x2de and fs3 == 0 and fe3 == 0x1e and fm3 == 0x040 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x64f3; op2val:0x4ede; +op3val:0x7840; valaddr_reg:x1; val_offset:3069*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3069*FLEN/8, x4, x2, x3) + +inst_1059: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x0f3 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x2de and fs3 == 0 and fe3 == 0x1e and fm3 == 0x040 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x64f3; op2val:0x4ede; +op3val:0x7840; valaddr_reg:x1; val_offset:3072*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3072*FLEN/8, x4, x2, x3) + +inst_1060: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b3 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3ef and fs3 == 0 and fe3 == 0x1b and fm3 == 0x2a5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ab3; op2val:0x2fef; +op3val:0x6ea5; valaddr_reg:x1; val_offset:3075*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3075*FLEN/8, x4, x2, x3) + +inst_1061: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b3 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3ef and fs3 == 0 and fe3 == 0x1b and fm3 == 0x2a5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ab3; op2val:0x2fef; +op3val:0x6ea5; valaddr_reg:x1; val_offset:3078*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3078*FLEN/8, x4, x2, x3) + +inst_1062: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b3 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3ef and fs3 == 0 and fe3 == 0x1b and fm3 == 0x2a5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ab3; op2val:0x2fef; +op3val:0x6ea5; valaddr_reg:x1; val_offset:3081*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3081*FLEN/8, x4, x2, x3) + +inst_1063: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b3 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3ef and fs3 == 0 and fe3 == 0x1b and fm3 == 0x2a5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ab3; op2val:0x2fef; +op3val:0x6ea5; valaddr_reg:x1; val_offset:3084*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3084*FLEN/8, x4, x2, x3) + +inst_1064: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b3 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3ef and fs3 == 0 and fe3 == 0x1b and fm3 == 0x2a5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ab3; op2val:0x2fef; +op3val:0x6ea5; valaddr_reg:x1; val_offset:3087*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3087*FLEN/8, x4, x2, x3) + +inst_1065: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x320 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x329 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x261 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7720; op2val:0x2729; +op3val:0x6261; valaddr_reg:x1; val_offset:3090*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3090*FLEN/8, x4, x2, x3) + +inst_1066: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x320 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x329 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x261 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7720; op2val:0x2729; +op3val:0x6261; valaddr_reg:x1; val_offset:3093*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3093*FLEN/8, x4, x2, x3) + +inst_1067: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x320 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x329 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x261 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7720; op2val:0x2729; +op3val:0x6261; valaddr_reg:x1; val_offset:3096*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3096*FLEN/8, x4, x2, x3) + +inst_1068: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x320 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x329 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x261 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7720; op2val:0x2729; +op3val:0x6261; valaddr_reg:x1; val_offset:3099*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3099*FLEN/8, x4, x2, x3) + +inst_1069: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x320 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x329 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x261 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7720; op2val:0x2729; +op3val:0x6261; valaddr_reg:x1; val_offset:3102*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3102*FLEN/8, x4, x2, x3) + +inst_1070: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f2 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3cd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bf2; op2val:0x3bcd; +op3val:0x7bc0; valaddr_reg:x1; val_offset:3105*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3105*FLEN/8, x4, x2, x3) + +inst_1071: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f2 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3cd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3c0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bf2; op2val:0x3bcd; +op3val:0x7bc0; valaddr_reg:x1; val_offset:3108*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3108*FLEN/8, x4, x2, x3) + +inst_1072: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f2 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3cd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3c0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bf2; op2val:0x3bcd; +op3val:0x7bc0; valaddr_reg:x1; val_offset:3111*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3111*FLEN/8, x4, x2, x3) + +inst_1073: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f2 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3cd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3c0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bf2; op2val:0x3bcd; +op3val:0x7bc0; valaddr_reg:x1; val_offset:3114*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3114*FLEN/8, x4, x2, x3) + +inst_1074: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f2 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3cd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3c0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bf2; op2val:0x3bcd; +op3val:0x7bc0; valaddr_reg:x1; val_offset:3117*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3117*FLEN/8, x4, x2, x3) + +inst_1075: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x16c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1a9 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3ad and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x796c; op2val:0x39a9; +op3val:0x77ad; valaddr_reg:x1; val_offset:3120*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3120*FLEN/8, x4, x2, x3) + +inst_1076: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x16c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1a9 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3ad and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x796c; op2val:0x39a9; +op3val:0x77ad; valaddr_reg:x1; val_offset:3123*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3123*FLEN/8, x4, x2, x3) + +inst_1077: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x16c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1a9 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3ad and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x796c; op2val:0x39a9; +op3val:0x77ad; valaddr_reg:x1; val_offset:3126*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3126*FLEN/8, x4, x2, x3) + +inst_1078: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x16c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1a9 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3ad and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x796c; op2val:0x39a9; +op3val:0x77ad; valaddr_reg:x1; val_offset:3129*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3129*FLEN/8, x4, x2, x3) + +inst_1079: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x16c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1a9 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3ad and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x796c; op2val:0x39a9; +op3val:0x77ad; valaddr_reg:x1; val_offset:3132*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3132*FLEN/8, x4, x2, x3) + +inst_1080: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x080 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2e1 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x3be and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c80; op2val:0x3ee1; +op3val:0x6fbe; valaddr_reg:x1; val_offset:3135*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3135*FLEN/8, x4, x2, x3) + +inst_1081: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x080 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2e1 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x3be and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c80; op2val:0x3ee1; +op3val:0x6fbe; valaddr_reg:x1; val_offset:3138*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3138*FLEN/8, x4, x2, x3) + +inst_1082: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x080 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2e1 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x3be and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c80; op2val:0x3ee1; +op3val:0x6fbe; valaddr_reg:x1; val_offset:3141*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3141*FLEN/8, x4, x2, x3) + +inst_1083: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x080 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2e1 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x3be and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c80; op2val:0x3ee1; +op3val:0x6fbe; valaddr_reg:x1; val_offset:3144*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3144*FLEN/8, x4, x2, x3) + +inst_1084: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x080 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2e1 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x3be and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c80; op2val:0x3ee1; +op3val:0x6fbe; valaddr_reg:x1; val_offset:3147*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3147*FLEN/8, x4, x2, x3) + +inst_1085: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a3 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x081 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x25a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79a3; op2val:0x3c81; +op3val:0x7a5a; valaddr_reg:x1; val_offset:3150*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3150*FLEN/8, x4, x2, x3) + +inst_1086: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a3 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x081 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x25a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79a3; op2val:0x3c81; +op3val:0x7a5a; valaddr_reg:x1; val_offset:3153*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3153*FLEN/8, x4, x2, x3) + +inst_1087: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a3 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x081 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x25a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79a3; op2val:0x3c81; +op3val:0x7a5a; valaddr_reg:x1; val_offset:3156*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3156*FLEN/8, x4, x2, x3) + +inst_1088: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a3 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x081 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x25a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79a3; op2val:0x3c81; +op3val:0x7a5a; valaddr_reg:x1; val_offset:3159*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3159*FLEN/8, x4, x2, x3) + +inst_1089: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a3 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x081 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x25a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79a3; op2val:0x3c81; +op3val:0x7a5a; valaddr_reg:x1; val_offset:3162*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3162*FLEN/8, x4, x2, x3) + +inst_1090: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2f8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2e3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7be8; op2val:0x3af8; +op3val:0x7ae3; valaddr_reg:x1; val_offset:3165*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3165*FLEN/8, x4, x2, x3) + +inst_1091: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2f8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2e3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7be8; op2val:0x3af8; +op3val:0x7ae3; valaddr_reg:x1; val_offset:3168*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3168*FLEN/8, x4, x2, x3) + +inst_1092: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2f8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2e3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7be8; op2val:0x3af8; +op3val:0x7ae3; valaddr_reg:x1; val_offset:3171*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3171*FLEN/8, x4, x2, x3) + +inst_1093: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2f8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2e3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7be8; op2val:0x3af8; +op3val:0x7ae3; valaddr_reg:x1; val_offset:3174*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3174*FLEN/8, x4, x2, x3) + +inst_1094: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2f8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2e3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7be8; op2val:0x3af8; +op3val:0x7ae3; valaddr_reg:x1; val_offset:3177*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3177*FLEN/8, x4, x2, x3) + +inst_1095: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x300 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0a9 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x015 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7700; op2val:0x38a9; +op3val:0x7415; valaddr_reg:x1; val_offset:3180*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3180*FLEN/8, x4, x2, x3) + +inst_1096: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x300 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0a9 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x015 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7700; op2val:0x38a9; +op3val:0x7415; valaddr_reg:x1; val_offset:3183*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3183*FLEN/8, x4, x2, x3) + +inst_1097: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x300 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0a9 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x015 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7700; op2val:0x38a9; +op3val:0x7415; valaddr_reg:x1; val_offset:3186*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3186*FLEN/8, x4, x2, x3) + +inst_1098: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x300 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0a9 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x015 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7700; op2val:0x38a9; +op3val:0x7415; valaddr_reg:x1; val_offset:3189*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3189*FLEN/8, x4, x2, x3) + +inst_1099: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x300 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0a9 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x015 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7700; op2val:0x38a9; +op3val:0x7415; valaddr_reg:x1; val_offset:3192*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3192*FLEN/8, x4, x2, x3) + +inst_1100: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x055 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x11b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x188 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7855; op2val:0x391b; +op3val:0x7588; valaddr_reg:x1; val_offset:3195*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3195*FLEN/8, x4, x2, x3) + +inst_1101: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x055 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x11b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x188 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7855; op2val:0x391b; +op3val:0x7588; valaddr_reg:x1; val_offset:3198*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3198*FLEN/8, x4, x2, x3) + +inst_1102: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x055 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x11b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x188 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7855; op2val:0x391b; +op3val:0x7588; valaddr_reg:x1; val_offset:3201*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3201*FLEN/8, x4, x2, x3) + +inst_1103: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x055 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x11b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x188 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7855; op2val:0x391b; +op3val:0x7588; valaddr_reg:x1; val_offset:3204*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3204*FLEN/8, x4, x2, x3) + +inst_1104: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x055 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x11b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x188 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7855; op2val:0x391b; +op3val:0x7588; valaddr_reg:x1; val_offset:3207*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3207*FLEN/8, x4, x2, x3) + +inst_1105: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x05b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x27d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x311 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x785b; op2val:0x3e7d; +op3val:0x7b11; valaddr_reg:x1; val_offset:3210*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3210*FLEN/8, x4, x2, x3) + +inst_1106: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x05b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x27d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x311 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x785b; op2val:0x3e7d; +op3val:0x7b11; valaddr_reg:x1; val_offset:3213*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3213*FLEN/8, x4, x2, x3) + +inst_1107: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x05b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x27d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x311 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x785b; op2val:0x3e7d; +op3val:0x7b11; valaddr_reg:x1; val_offset:3216*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3216*FLEN/8, x4, x2, x3) + +inst_1108: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x05b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x27d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x311 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x785b; op2val:0x3e7d; +op3val:0x7b11; valaddr_reg:x1; val_offset:3219*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3219*FLEN/8, x4, x2, x3) + +inst_1109: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x05b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x27d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x311 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x785b; op2val:0x3e7d; +op3val:0x7b11; valaddr_reg:x1; val_offset:3222*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3222*FLEN/8, x4, x2, x3) + +inst_1110: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x33e and fs2 == 0 and fe2 == 0x10 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3d8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x773e; op2val:0x4055; +op3val:0x7bd8; valaddr_reg:x1; val_offset:3225*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3225*FLEN/8, x4, x2, x3) + +inst_1111: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x33e and fs2 == 0 and fe2 == 0x10 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3d8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x773e; op2val:0x4055; +op3val:0x7bd8; valaddr_reg:x1; val_offset:3228*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3228*FLEN/8, x4, x2, x3) + +inst_1112: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x33e and fs2 == 0 and fe2 == 0x10 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3d8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x773e; op2val:0x4055; +op3val:0x7bd8; valaddr_reg:x1; val_offset:3231*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3231*FLEN/8, x4, x2, x3) + +inst_1113: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x33e and fs2 == 0 and fe2 == 0x10 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3d8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x773e; op2val:0x4055; +op3val:0x7bd8; valaddr_reg:x1; val_offset:3234*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3234*FLEN/8, x4, x2, x3) + +inst_1114: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x33e and fs2 == 0 and fe2 == 0x10 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3d8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x773e; op2val:0x4055; +op3val:0x7bd8; valaddr_reg:x1; val_offset:3237*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3237*FLEN/8, x4, x2, x3) + +inst_1115: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1be and fs2 == 0 and fe2 == 0x0b and fm2 == 0x013 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x1da and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79be; op2val:0x2c13; +op3val:0x69da; valaddr_reg:x1; val_offset:3240*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3240*FLEN/8, x4, x2, x3) + +inst_1116: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1be and fs2 == 0 and fe2 == 0x0b and fm2 == 0x013 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x1da and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79be; op2val:0x2c13; +op3val:0x69da; valaddr_reg:x1; val_offset:3243*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3243*FLEN/8, x4, x2, x3) + +inst_1117: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1be and fs2 == 0 and fe2 == 0x0b and fm2 == 0x013 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x1da and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79be; op2val:0x2c13; +op3val:0x69da; valaddr_reg:x1; val_offset:3246*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3246*FLEN/8, x4, x2, x3) + +inst_1118: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1be and fs2 == 0 and fe2 == 0x0b and fm2 == 0x013 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x1da and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79be; op2val:0x2c13; +op3val:0x69da; valaddr_reg:x1; val_offset:3249*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3249*FLEN/8, x4, x2, x3) + +inst_1119: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1be and fs2 == 0 and fe2 == 0x0b and fm2 == 0x013 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x1da and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79be; op2val:0x2c13; +op3val:0x69da; valaddr_reg:x1; val_offset:3252*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3252*FLEN/8, x4, x2, x3) + +inst_1120: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x257 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x024 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x292 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a57; op2val:0x3c24; +op3val:0x7a92; valaddr_reg:x1; val_offset:3255*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3255*FLEN/8, x4, x2, x3) + +inst_1121: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x257 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x024 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x292 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a57; op2val:0x3c24; +op3val:0x7a92; valaddr_reg:x1; val_offset:3258*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3258*FLEN/8, x4, x2, x3) + +inst_1122: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x257 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x024 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x292 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a57; op2val:0x3c24; +op3val:0x7a92; valaddr_reg:x1; val_offset:3261*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3261*FLEN/8, x4, x2, x3) + +inst_1123: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3c1 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x050 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x02f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77c1; op2val:0x3850; +op3val:0x742f; valaddr_reg:x1; val_offset:3264*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3264*FLEN/8, x4, x2, x3) + +inst_1124: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3c1 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x050 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x02f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77c1; op2val:0x3850; +op3val:0x742f; valaddr_reg:x1; val_offset:3267*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3267*FLEN/8, x4, x2, x3) + +inst_1125: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3c1 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x050 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x02f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77c1; op2val:0x3850; +op3val:0x742f; valaddr_reg:x1; val_offset:3270*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3270*FLEN/8, x4, x2, x3) + +inst_1126: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3c1 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x050 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x02f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77c1; op2val:0x3850; +op3val:0x742f; valaddr_reg:x1; val_offset:3273*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3273*FLEN/8, x4, x2, x3) + +inst_1127: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x18b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4fa5; op2val:0x658b; +op3val:0x794c; valaddr_reg:x1; val_offset:3276*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3276*FLEN/8, x4, x2, x3) + +inst_1128: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x18b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4fa5; op2val:0x658b; +op3val:0x794c; valaddr_reg:x1; val_offset:3279*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3279*FLEN/8, x4, x2, x3) + +inst_1129: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1f7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x020 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x228 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75f7; op2val:0x4020; +op3val:0x7a28; valaddr_reg:x1; val_offset:3282*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3282*FLEN/8, x4, x2, x3) + +inst_1130: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x05c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x269 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x745c; op2val:0x41e1; +op3val:0x7a69; valaddr_reg:x1; val_offset:3285*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3285*FLEN/8, x4, x2, x3) + +inst_1131: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x089 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x29e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79d5; op2val:0x3889; +op3val:0x769e; valaddr_reg:x1; val_offset:3288*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3288*FLEN/8, x4, x2, x3) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(31319,32,FLEN) +NAN_BOXED(15396,32,FLEN) +NAN_BOXED(31319,32,FLEN) +NAN_BOXED(31319,32,FLEN) +NAN_BOXED(15396,32,FLEN) +NAN_BOXED(15396,32,FLEN) +NAN_BOXED(31319,32,FLEN) +NAN_BOXED(15396,32,FLEN) +NAN_BOXED(31378,32,FLEN) +NAN_BOXED(31319,32,FLEN) +NAN_BOXED(15396,32,FLEN) +NAN_BOXED(31378,32,FLEN) +NAN_BOXED(31319,32,FLEN) +NAN_BOXED(15396,32,FLEN) +NAN_BOXED(31319,32,FLEN) +NAN_BOXED(30657,32,FLEN) +NAN_BOXED(30657,32,FLEN) +NAN_BOXED(30657,32,FLEN) +NAN_BOXED(30657,32,FLEN) +NAN_BOXED(30657,32,FLEN) +NAN_BOXED(29743,32,FLEN) +NAN_BOXED(30657,32,FLEN) +NAN_BOXED(14416,32,FLEN) +NAN_BOXED(14416,32,FLEN) +NAN_BOXED(30657,32,FLEN) +NAN_BOXED(14416,32,FLEN) +NAN_BOXED(29743,32,FLEN) +NAN_BOXED(30657,32,FLEN) +NAN_BOXED(30657,32,FLEN) +NAN_BOXED(30657,32,FLEN) +NAN_BOXED(20389,32,FLEN) +NAN_BOXED(25995,32,FLEN) +NAN_BOXED(31052,32,FLEN) +NAN_BOXED(20389,32,FLEN) +NAN_BOXED(20389,32,FLEN) +NAN_BOXED(31052,32,FLEN) +test_dataset_1: +NAN_BOXED(20389,32,FLEN) +NAN_BOXED(25995,32,FLEN) +NAN_BOXED(31052,32,FLEN) +NAN_BOXED(20389,32,FLEN) +NAN_BOXED(25995,32,FLEN) +NAN_BOXED(31052,32,FLEN) +NAN_BOXED(20389,32,FLEN) +NAN_BOXED(25995,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(30597,32,FLEN) +NAN_BOXED(15990,32,FLEN) +NAN_BOXED(31251,32,FLEN) +NAN_BOXED(30597,32,FLEN) +NAN_BOXED(15990,32,FLEN) +NAN_BOXED(31251,32,FLEN) +NAN_BOXED(30597,32,FLEN) +NAN_BOXED(15990,32,FLEN) +NAN_BOXED(31251,32,FLEN) +NAN_BOXED(30597,32,FLEN) +NAN_BOXED(15990,32,FLEN) +NAN_BOXED(31251,32,FLEN) +NAN_BOXED(30597,32,FLEN) +NAN_BOXED(15990,32,FLEN) +NAN_BOXED(31251,32,FLEN) +NAN_BOXED(30199,32,FLEN) +NAN_BOXED(16416,32,FLEN) +NAN_BOXED(31272,32,FLEN) +NAN_BOXED(30199,32,FLEN) +NAN_BOXED(16416,32,FLEN) +NAN_BOXED(31272,32,FLEN) +NAN_BOXED(30199,32,FLEN) +NAN_BOXED(16416,32,FLEN) +NAN_BOXED(31272,32,FLEN) +test_dataset_2: +NAN_BOXED(30199,32,FLEN) +NAN_BOXED(16416,32,FLEN) +NAN_BOXED(31272,32,FLEN) +NAN_BOXED(30199,32,FLEN) +NAN_BOXED(16416,32,FLEN) +NAN_BOXED(31272,32,FLEN) +NAN_BOXED(29788,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31337,32,FLEN) +NAN_BOXED(29788,32,FLEN) +NAN_BOXED(16865,32,FLEN) +NAN_BOXED(31337,32,FLEN) +NAN_BOXED(29788,32,FLEN) +NAN_BOXED(16865,32,FLEN) +NAN_BOXED(31337,32,FLEN) +NAN_BOXED(29788,32,FLEN) +NAN_BOXED(16865,32,FLEN) +NAN_BOXED(31337,32,FLEN) +NAN_BOXED(29788,32,FLEN) +NAN_BOXED(16865,32,FLEN) +NAN_BOXED(31337,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(14473,32,FLEN) +NAN_BOXED(30366,32,FLEN) +NAN_BOXED(31189,32,FLEN) +NAN_BOXED(14473,32,FLEN) +NAN_BOXED(30366,32,FLEN) +NAN_BOXED(31189,32,FLEN) +NAN_BOXED(14473,32,FLEN) +NAN_BOXED(30366,32,FLEN) +NAN_BOXED(31189,32,FLEN) +NAN_BOXED(14473,32,FLEN) +NAN_BOXED(30366,32,FLEN) +NAN_BOXED(31189,32,FLEN) +NAN_BOXED(14473,32,FLEN) +NAN_BOXED(30366,32,FLEN) +test_dataset_3: +NAN_BOXED(30797,16,FLEN) +NAN_BOXED(15633,16,FLEN) +NAN_BOXED(31092,16,FLEN) +NAN_BOXED(30797,16,FLEN) +NAN_BOXED(15633,16,FLEN) +NAN_BOXED(31092,16,FLEN) +NAN_BOXED(30797,16,FLEN) +NAN_BOXED(15633,16,FLEN) +NAN_BOXED(31092,16,FLEN) +NAN_BOXED(30797,16,FLEN) +NAN_BOXED(15633,16,FLEN) +NAN_BOXED(31092,16,FLEN) +NAN_BOXED(30797,16,FLEN) +NAN_BOXED(15633,16,FLEN) +NAN_BOXED(31092,16,FLEN) +NAN_BOXED(29228,16,FLEN) +NAN_BOXED(16828,16,FLEN) +NAN_BOXED(30829,16,FLEN) +NAN_BOXED(29228,16,FLEN) +NAN_BOXED(16828,16,FLEN) +NAN_BOXED(30829,16,FLEN) +NAN_BOXED(29228,16,FLEN) +NAN_BOXED(16828,16,FLEN) +NAN_BOXED(30829,16,FLEN) +NAN_BOXED(29228,16,FLEN) +NAN_BOXED(16828,16,FLEN) +NAN_BOXED(30829,16,FLEN) +NAN_BOXED(29228,16,FLEN) +NAN_BOXED(16828,16,FLEN) +NAN_BOXED(30829,16,FLEN) +NAN_BOXED(31344,16,FLEN) +NAN_BOXED(13638,16,FLEN) +NAN_BOXED(29759,16,FLEN) +NAN_BOXED(31344,16,FLEN) +NAN_BOXED(13638,16,FLEN) +NAN_BOXED(29759,16,FLEN) +NAN_BOXED(31344,16,FLEN) +NAN_BOXED(13638,16,FLEN) +NAN_BOXED(29759,16,FLEN) +NAN_BOXED(31344,16,FLEN) +NAN_BOXED(13638,16,FLEN) +NAN_BOXED(29759,16,FLEN) +NAN_BOXED(31344,16,FLEN) +NAN_BOXED(13638,16,FLEN) +NAN_BOXED(29759,16,FLEN) +NAN_BOXED(31340,16,FLEN) +NAN_BOXED(15060,16,FLEN) +NAN_BOXED(31099,16,FLEN) +NAN_BOXED(31340,16,FLEN) +NAN_BOXED(15060,16,FLEN) +NAN_BOXED(31099,16,FLEN) +NAN_BOXED(31340,16,FLEN) +NAN_BOXED(15060,16,FLEN) +NAN_BOXED(31099,16,FLEN) +NAN_BOXED(31340,16,FLEN) +NAN_BOXED(15060,16,FLEN) +NAN_BOXED(31099,16,FLEN) +NAN_BOXED(31340,16,FLEN) +NAN_BOXED(15060,16,FLEN) +NAN_BOXED(31099,16,FLEN) +NAN_BOXED(31424,16,FLEN) +NAN_BOXED(13916,16,FLEN) +NAN_BOXED(30045,16,FLEN) +NAN_BOXED(31424,16,FLEN) +NAN_BOXED(13916,16,FLEN) +NAN_BOXED(30045,16,FLEN) +NAN_BOXED(31424,16,FLEN) +NAN_BOXED(13916,16,FLEN) +NAN_BOXED(30045,16,FLEN) +NAN_BOXED(31424,16,FLEN) +NAN_BOXED(13916,16,FLEN) +NAN_BOXED(30045,16,FLEN) +NAN_BOXED(31424,16,FLEN) +NAN_BOXED(13916,16,FLEN) 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+ .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_2: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_3: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_4: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_5: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_6: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_7: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_8: + .fill 160*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fnmadd_b4-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fnmadd_b4-01.S new file mode 100644 index 000000000..caf15c5db --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fnmadd_b4-01.S @@ -0,0 +1,1614 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 06:03:37 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fnmadd.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fnmadd.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fnmadd_b4 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fnmadd_b4) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x10,test_dataset_0) +RVTEST_SIGBASE(x5,signature_x5_1) + +inst_0: +// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==x17, rs2==x24, rs3==x17, rd==x9,fs1 == 0 and fe1 == 0x1e and fm1 == 0x257 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x32e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x292 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x17; op2:x24; op3:x17; dest:x9; op1val:0x7a57; op2val:0xb32e; +op3val:0x7a57; valaddr_reg:x10; val_offset:0*FLEN/8; rmval:dyn; +testreg:x8; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x9, x17, x24, x17, dyn, 0, 0, x10, 0*FLEN/8, x13, x5, x8) + +inst_1: +// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==x16, rs2==x19, rs3==x19, rd==x0,fs1 == 0 and fe1 == 0x1e and fm1 == 0x257 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x32e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x292 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x16; op2:x19; op3:x19; dest:x0; op1val:0x7a57; op2val:0xb32e; +op3val:0xb32e; valaddr_reg:x10; val_offset:3*FLEN/8; rmval:dyn; +testreg:x8; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x0, x16, x19, x19, dyn, 32, 0, x10, 3*FLEN/8, x13, x5, x8) + +inst_2: +// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==x3, rs2==x15, rs3==x26, rd==x14,fs1 == 0 and fe1 == 0x1e and fm1 == 0x257 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x32e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x292 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x3; op2:x15; op3:x26; dest:x14; op1val:0x7a57; op2val:0xb32e; +op3val:0x7a92; valaddr_reg:x10; val_offset:6*FLEN/8; rmval:dyn; +testreg:x8; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x14, x3, x15, x26, dyn, 64, 0, x10, 6*FLEN/8, x13, x5, x8) + +inst_3: +// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==x24, rs2==x3, rs3==x8, rd==x3,fs1 == 0 and fe1 == 0x1e and fm1 == 0x257 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x32e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x292 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x24; op2:x3; op3:x8; dest:x3; op1val:0x7a57; op2val:0xb32e; +op3val:0x7a92; valaddr_reg:x10; val_offset:9*FLEN/8; rmval:dyn; +testreg:x8; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x3, x24, x3, x8, dyn, 96, 0, x10, 9*FLEN/8, x13, x5, x8) + +inst_4: +// rs1 == rd == rs3 != rs2, rs1==x18, rs2==x7, rs3==x18, rd==x18,fs1 == 0 and fe1 == 0x1e and fm1 == 0x257 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x32e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x292 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x18; op2:x7; op3:x18; dest:x18; op1val:0x7a57; op2val:0xb32e; +op3val:0x7a57; valaddr_reg:x10; val_offset:12*FLEN/8; rmval:dyn; +testreg:x8; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x18, x18, x7, x18, dyn, 128, 0, x10, 12*FLEN/8, x13, x5, x8) + +inst_5: +// rs1 == rs2 == rs3 != rd, rs1==x1, rs2==x1, rs3==x1, rd==x2,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3c1 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x133 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x02f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x1; op2:x1; op3:x1; dest:x2; op1val:0x77c1; op2val:0x77c1; +op3val:0x77c1; valaddr_reg:x10; val_offset:15*FLEN/8; rmval:dyn; +testreg:x8; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x2, x1, x1, x1, dyn, 0, 0, x10, 15*FLEN/8, x13, x5, x8) + +inst_6: +// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==x4, rs2==x4, rs3==x29, rd==x26,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3c1 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x133 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x02f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x4; op2:x4; op3:x29; dest:x26; op1val:0x77c1; op2val:0x77c1; +op3val:0x742f; valaddr_reg:x10; val_offset:18*FLEN/8; rmval:dyn; +testreg:x8; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x26, x4, x4, x29, dyn, 32, 0, x10, 18*FLEN/8, x13, x5, x8) + +inst_7: +// rd == rs2 == rs3 != rs1, rs1==x30, rs2==x25, rs3==x25, rd==x25,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3c1 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x133 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x02f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x25; op3:x25; dest:x25; op1val:0x77c1; op2val:0x4133; +op3val:0x4133; valaddr_reg:x10; val_offset:21*FLEN/8; rmval:dyn; +testreg:x8; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x25, x30, x25, x25, dyn, 64, 0, x10, 21*FLEN/8, x13, x5, x8) + +inst_8: +// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==x15, rs2==x12, rs3==x24, rd==x15,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3c1 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x133 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x02f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x15; op2:x12; op3:x24; dest:x15; op1val:0x77c1; op2val:0x4133; +op3val:0x742f; valaddr_reg:x10; val_offset:24*FLEN/8; rmval:dyn; +testreg:x8; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x15, x15, x12, x24, dyn, 96, 0, x10, 24*FLEN/8, x13, x5, x8) + +inst_9: +// rs1 == rs2 == rs3 == rd, rs1==x28, rs2==x28, rs3==x28, rd==x28,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3c1 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x133 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x02f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x28; op2:x28; op3:x28; dest:x28; op1val:0x77c1; op2val:0x77c1; +op3val:0x77c1; valaddr_reg:x10; val_offset:27*FLEN/8; rmval:dyn; +testreg:x8; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x28, x28, x28, x28, dyn, 128, 0, x10, 27*FLEN/8, x13, x5, x8) + +inst_10: +// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==x26, rs2==x27, rs3==x6, rd==x6,fs1 == 0 and fe1 == 0x13 and fm1 == 0x3a5 and fs2 == 1 and fe2 == 0x18 and fm2 == 0x1a4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x26; op2:x27; op3:x6; dest:x6; op1val:0x4fa5; op2val:0xe1a4; +op3val:0x794c; valaddr_reg:x10; val_offset:30*FLEN/8; rmval:dyn; +testreg:x8; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x6, x26, x27, x6, dyn, 0, 0, x10, 30*FLEN/8, x13, x5, x8) + +inst_11: +// rs1 == rs2 == rd != rs3, rs1==x20, rs2==x20, rs3==x16, rd==x20,fs1 == 0 and fe1 == 0x13 and fm1 == 0x3a5 and fs2 == 1 and fe2 == 0x18 and fm2 == 0x1a4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x20; op2:x20; op3:x16; dest:x20; op1val:0x4fa5; op2val:0x4fa5; +op3val:0x794c; valaddr_reg:x10; val_offset:33*FLEN/8; rmval:dyn; +testreg:x8; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x20, x20, x20, x16, dyn, 32, 0, x10, 33*FLEN/8, x13, x5, x8) + +inst_12: +// rs1==x22, rs2==x11, rs3==x5, rd==x4,fs1 == 0 and fe1 == 0x13 and fm1 == 0x3a5 and fs2 == 1 and fe2 == 0x18 and fm2 == 0x1a4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x22; op2:x11; op3:x5; dest:x4; op1val:0x4fa5; op2val:0xe1a4; +op3val:0x794c; valaddr_reg:x10; val_offset:36*FLEN/8; rmval:dyn; +testreg:x8; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x4, x22, x11, x5, dyn, 64, 0, x10, 36*FLEN/8, x13, x5, x8) +RVTEST_VALBASEUPD(x15,test_dataset_1) + +inst_13: +// rs1==x14, rs2==x17, rs3==x12, rd==x19,fs1 == 0 and fe1 == 0x13 and fm1 == 0x3a5 and fs2 == 1 and fe2 == 0x18 and fm2 == 0x1a4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x14; op2:x17; op3:x12; dest:x19; op1val:0x4fa5; op2val:0xe1a4; +op3val:0x794c; valaddr_reg:x15; val_offset:0*FLEN/8; rmval:dyn; +testreg:x8; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x19, x14, x17, x12, dyn, 96, 0, x15, 0*FLEN/8, x20, x5, x8) + +inst_14: +// rs1==x21, rs2==x31, rs3==x4, rd==x17,fs1 == 0 and fe1 == 0x13 and fm1 == 0x3a5 and fs2 == 1 and fe2 == 0x18 and fm2 == 0x1a4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x21; op2:x31; op3:x4; dest:x17; op1val:0x4fa5; op2val:0xe1a4; +op3val:0x794c; valaddr_reg:x15; val_offset:3*FLEN/8; rmval:dyn; +testreg:x8; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x17, x21, x31, x4, dyn, 128, 0, x15, 3*FLEN/8, x20, x5, x8) +RVTEST_SIGBASE(x3,signature_x3_0) + +inst_15: +// rs1==x11, rs2==x16, rs3==x14, rd==x23,fs1 == 0 and fe1 == 0x1d and fm1 == 0x385 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x37b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x213 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x11; op2:x16; op3:x14; dest:x23; op1val:0x7785; op2val:0x437b; +op3val:0x7a13; valaddr_reg:x15; val_offset:6*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x23, x11, x16, x14, dyn, 0, 0, x15, 6*FLEN/8, x20, x3, x4) + +inst_16: +// rs1==x31, rs2==x9, rs3==x22, rd==x12,fs1 == 0 and fe1 == 0x1d and fm1 == 0x385 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x37b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x213 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x31; op2:x9; op3:x22; dest:x12; op1val:0x7785; op2val:0x437b; +op3val:0x7a13; valaddr_reg:x15; val_offset:9*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x12, x31, x9, x22, dyn, 32, 0, x15, 9*FLEN/8, x20, x3, x4) + +inst_17: +// rs1==x23, rs2==x14, rs3==x27, rd==x1,fs1 == 0 and fe1 == 0x1d and fm1 == 0x385 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x37b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x213 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x23; op2:x14; op3:x27; dest:x1; op1val:0x7785; op2val:0x437b; +op3val:0x7a13; valaddr_reg:x15; val_offset:12*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x1, x23, x14, x27, dyn, 64, 0, x15, 12*FLEN/8, x20, x3, x4) + +inst_18: +// rs1==x5, rs2==x8, rs3==x3, rd==x7,fs1 == 0 and fe1 == 0x1d and fm1 == 0x385 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x37b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x213 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x5; op2:x8; op3:x3; dest:x7; op1val:0x7785; op2val:0x437b; +op3val:0x7a13; valaddr_reg:x15; val_offset:15*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x7, x5, x8, x3, dyn, 96, 0, x15, 15*FLEN/8, x20, x3, x4) + +inst_19: +// rs1==x27, rs2==x18, rs3==x31, rd==x30,fs1 == 0 and fe1 == 0x1d and fm1 == 0x385 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x37b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x213 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x27; op2:x18; op3:x31; dest:x30; op1val:0x7785; op2val:0x437b; +op3val:0x7a13; valaddr_reg:x15; val_offset:18*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x30, x27, x18, x31, dyn, 128, 0, x15, 18*FLEN/8, x20, x3, x4) + +inst_20: +// rs1==x12, rs2==x6, rs3==x10, rd==x13,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1f7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0ed and fs3 == 0 and fe3 == 0x1e and fm3 == 0x228 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x12; op2:x6; op3:x10; dest:x13; op1val:0x75f7; op2val:0xb8ed; +op3val:0x7a28; valaddr_reg:x15; val_offset:21*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x13, x12, x6, x10, dyn, 0, 0, x15, 21*FLEN/8, x20, x3, x4) + +inst_21: +// rs1==x13, rs2==x10, rs3==x9, rd==x31,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1f7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0ed and fs3 == 0 and fe3 == 0x1e and fm3 == 0x228 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x13; op2:x10; op3:x9; dest:x31; op1val:0x75f7; op2val:0xb8ed; +op3val:0x7a28; valaddr_reg:x15; val_offset:24*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x13, x10, x9, dyn, 32, 0, x15, 24*FLEN/8, x20, x3, x4) + +inst_22: +// rs1==x19, rs2==x26, rs3==x23, rd==x8,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1f7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0ed and fs3 == 0 and fe3 == 0x1e and fm3 == 0x228 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x19; op2:x26; op3:x23; dest:x8; op1val:0x75f7; op2val:0xb8ed; +op3val:0x7a28; valaddr_reg:x15; val_offset:27*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x8, x19, x26, x23, dyn, 64, 0, x15, 27*FLEN/8, x20, x3, x4) + +inst_23: +// rs1==x9, rs2==x2, rs3==x15, rd==x29,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1f7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0ed and fs3 == 0 and fe3 == 0x1e and fm3 == 0x228 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x9; op2:x2; op3:x15; dest:x29; op1val:0x75f7; op2val:0xb8ed; +op3val:0x7a28; valaddr_reg:x15; val_offset:30*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x29, x9, x2, x15, dyn, 96, 0, x15, 30*FLEN/8, x20, x3, x4) +RVTEST_VALBASEUPD(x9,test_dataset_2) + +inst_24: +// rs1==x8, rs2==x13, rs3==x21, rd==x5,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1f7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0ed and fs3 == 0 and fe3 == 0x1e and fm3 == 0x228 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x8; op2:x13; op3:x21; dest:x5; op1val:0x75f7; op2val:0xb8ed; +op3val:0x7a28; valaddr_reg:x9; val_offset:0*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x5, x8, x13, x21, dyn, 128, 0, x9, 0*FLEN/8, x12, x3, x4) + +inst_25: +// rs1==x7, rs2==x21, rs3==x13, rd==x27,fs1 == 0 and fe1 == 0x1d and fm1 == 0x05c and fs2 == 0 and fe2 == 0x11 and fm2 == 0x29b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x269 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x7; op2:x21; op3:x13; dest:x27; op1val:0x745c; op2val:0x469b; +op3val:0x7a69; valaddr_reg:x9; val_offset:3*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x27, x7, x21, x13, dyn, 0, 0, x9, 3*FLEN/8, x12, x3, x4) + +inst_26: +// rs1==x6, rs2==x5, rs3==x0, rd==x10,fs1 == 0 and fe1 == 0x1d and fm1 == 0x05c and fs2 == 0 and fe2 == 0x11 and fm2 == 0x29b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x269 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x6; op2:x5; op3:x0; dest:x10; op1val:0x745c; op2val:0x469b; +op3val:0x0; valaddr_reg:x9; val_offset:6*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x10, x6, x5, x0, dyn, 32, 0, x9, 6*FLEN/8, x12, x3, x4) + +inst_27: +// rs1==x29, rs2==x0, rs3==x2, rd==x11,fs1 == 0 and fe1 == 0x1d and fm1 == 0x05c and fs2 == 0 and fe2 == 0x11 and fm2 == 0x29b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x269 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x29; op2:x0; op3:x2; dest:x11; op1val:0x745c; op2val:0x0; +op3val:0x7a69; valaddr_reg:x9; val_offset:9*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x11, x29, x0, x2, dyn, 64, 0, x9, 9*FLEN/8, x12, x3, x4) + +inst_28: +// rs1==x10, rs2==x22, rs3==x7, rd==x24,fs1 == 0 and fe1 == 0x1d and fm1 == 0x05c and fs2 == 0 and fe2 == 0x11 and fm2 == 0x29b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x269 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x10; op2:x22; op3:x7; dest:x24; op1val:0x745c; op2val:0x469b; +op3val:0x7a69; valaddr_reg:x9; val_offset:12*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x24, x10, x22, x7, dyn, 96, 0, x9, 12*FLEN/8, x12, x3, x4) + +inst_29: +// rs1==x0, rs2==x30, rs3==x20, rd==x21,fs1 == 0 and fe1 == 0x1d and fm1 == 0x05c and fs2 == 0 and fe2 == 0x11 and fm2 == 0x29b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x269 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x0; op2:x30; op3:x20; dest:x21; op1val:0x0; op2val:0x469b; +op3val:0x7a69; valaddr_reg:x9; val_offset:15*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x21, x0, x30, x20, dyn, 128, 0, x9, 15*FLEN/8, x12, x3, x4) + +inst_30: +// rs1==x2, rs2==x23, rs3==x11, rd==x22,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x26c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x29e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x2; op2:x23; op3:x11; dest:x22; op1val:0x79d5; op2val:0xba6c; +op3val:0x769e; valaddr_reg:x9; val_offset:18*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x22, x2, x23, x11, dyn, 0, 0, x9, 18*FLEN/8, x12, x3, x4) + +inst_31: +// rs1==x25, rs2==x29, rs3==x30, rd==x16,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x26c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x29e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x25; op2:x29; op3:x30; dest:x16; op1val:0x79d5; op2val:0xba6c; +op3val:0x769e; valaddr_reg:x9; val_offset:21*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x16, x25, x29, x30, dyn, 32, 0, x9, 21*FLEN/8, x12, x3, x4) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_32: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x26c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x29e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79d5; op2val:0xba6c; +op3val:0x769e; valaddr_reg:x9; val_offset:24*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x9, 24*FLEN/8, x12, x1, x4) + +inst_33: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x26c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x29e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79d5; op2val:0xba6c; +op3val:0x769e; valaddr_reg:x9; val_offset:27*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x9, 27*FLEN/8, x12, x1, x4) + +inst_34: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x26c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x29e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79d5; op2val:0xba6c; +op3val:0x769e; valaddr_reg:x9; val_offset:30*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x9, 30*FLEN/8, x12, x1, x4) + +inst_35: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x23f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x174 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x784d; op2val:0x423f; +op3val:0x7974; valaddr_reg:x9; val_offset:33*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x9, 33*FLEN/8, x12, x1, x4) + +inst_36: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x23f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x174 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x784d; op2val:0x423f; +op3val:0x7974; valaddr_reg:x9; val_offset:36*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x9, 36*FLEN/8, x12, x1, x4) + +inst_37: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x23f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x174 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x784d; op2val:0x423f; +op3val:0x7974; valaddr_reg:x9; val_offset:39*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x9, 39*FLEN/8, x12, x1, x4) + +inst_38: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x23f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x174 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x784d; op2val:0x423f; +op3val:0x7974; valaddr_reg:x9; val_offset:42*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x9, 42*FLEN/8, x12, x1, x4) + +inst_39: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x23f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x174 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x784d; op2val:0x423f; +op3val:0x7974; valaddr_reg:x9; val_offset:45*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x9, 45*FLEN/8, x12, x1, x4) + +inst_40: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x22c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0a0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x06d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x722c; op2val:0xc0a0; +op3val:0x786d; valaddr_reg:x9; val_offset:48*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x9, 48*FLEN/8, x12, x1, x4) + +inst_41: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x22c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0a0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x06d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x722c; op2val:0xc0a0; +op3val:0x786d; valaddr_reg:x9; val_offset:51*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x9, 51*FLEN/8, x12, x1, x4) + +inst_42: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x22c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0a0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x06d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x722c; op2val:0xc0a0; +op3val:0x786d; valaddr_reg:x9; val_offset:54*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x9, 54*FLEN/8, x12, x1, x4) + +inst_43: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x22c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0a0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x06d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x722c; op2val:0xc0a0; +op3val:0x786d; valaddr_reg:x9; val_offset:57*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x9, 57*FLEN/8, x12, x1, x4) + +inst_44: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x22c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0a0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x06d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x722c; op2val:0xc0a0; +op3val:0x786d; valaddr_reg:x9; val_offset:60*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x9, 60*FLEN/8, x12, x1, x4) + +inst_45: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x270 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x249 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a70; op2val:0x3e49; +op3val:0x743f; valaddr_reg:x9; val_offset:63*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x9, 63*FLEN/8, x12, x1, x4) + +inst_46: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x270 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x249 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x03f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a70; op2val:0x3e49; +op3val:0x743f; valaddr_reg:x9; val_offset:66*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x9, 66*FLEN/8, x12, x1, x4) + +inst_47: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x270 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x249 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x03f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a70; op2val:0x3e49; +op3val:0x743f; valaddr_reg:x9; val_offset:69*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x9, 69*FLEN/8, x12, x1, x4) + +inst_48: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x270 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x249 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x03f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a70; op2val:0x3e49; +op3val:0x743f; valaddr_reg:x9; val_offset:72*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x9, 72*FLEN/8, x12, x1, x4) + +inst_49: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x270 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x249 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x03f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a70; op2val:0x3e49; +op3val:0x743f; valaddr_reg:x9; val_offset:75*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x9, 75*FLEN/8, x12, x1, x4) + +inst_50: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x242 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x17b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a6c; op2val:0xb642; +op3val:0x797b; valaddr_reg:x9; val_offset:78*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x9, 78*FLEN/8, x12, x1, x4) + +inst_51: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x242 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x17b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a6c; op2val:0xb642; +op3val:0x797b; valaddr_reg:x9; val_offset:81*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x9, 81*FLEN/8, x12, x1, x4) + +inst_52: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x242 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x17b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a6c; op2val:0xb642; +op3val:0x797b; valaddr_reg:x9; val_offset:84*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x9, 84*FLEN/8, x12, x1, x4) + +inst_53: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x242 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x17b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a6c; op2val:0xb642; +op3val:0x797b; valaddr_reg:x9; val_offset:87*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x9, 87*FLEN/8, x12, x1, x4) + +inst_54: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x242 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x17b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a6c; op2val:0xb642; +op3val:0x797b; valaddr_reg:x9; val_offset:90*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x9, 90*FLEN/8, x12, x1, x4) + +inst_55: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x253 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x15d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ac0; op2val:0x3e53; +op3val:0x755d; valaddr_reg:x9; val_offset:93*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x9, 93*FLEN/8, x12, x1, x4) + +inst_56: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x253 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x15d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ac0; op2val:0x3e53; +op3val:0x755d; valaddr_reg:x9; val_offset:96*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x9, 96*FLEN/8, x12, x1, x4) + +inst_57: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x253 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x15d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ac0; op2val:0x3e53; +op3val:0x755d; valaddr_reg:x9; val_offset:99*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x9, 99*FLEN/8, x12, x1, x4) + +inst_58: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x253 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x15d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ac0; op2val:0x3e53; +op3val:0x755d; valaddr_reg:x9; val_offset:102*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x9, 102*FLEN/8, x12, x1, x4) + +inst_59: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x253 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x15d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ac0; op2val:0x3e53; +op3val:0x755d; valaddr_reg:x9; val_offset:105*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x9, 105*FLEN/8, x12, x1, x4) + +inst_60: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1f5 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x049 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x266 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6df5; op2val:0xc049; +op3val:0x7a66; valaddr_reg:x9; val_offset:108*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x9, 108*FLEN/8, x12, x1, x4) + +inst_61: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1f5 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x049 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x266 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6df5; op2val:0xc049; +op3val:0x7a66; valaddr_reg:x9; val_offset:111*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x9, 111*FLEN/8, x12, x1, x4) + +inst_62: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1f5 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x049 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x266 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6df5; op2val:0xc049; +op3val:0x7a66; valaddr_reg:x9; val_offset:114*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x9, 114*FLEN/8, x12, x1, x4) + +inst_63: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1f5 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x049 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x266 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6df5; op2val:0xc049; +op3val:0x7a66; valaddr_reg:x9; val_offset:117*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x9, 117*FLEN/8, x12, x1, x4) + +inst_64: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1f5 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x049 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x266 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6df5; op2val:0xc049; +op3val:0x7a66; valaddr_reg:x9; val_offset:120*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x9, 120*FLEN/8, x12, x1, x4) + +inst_65: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x32e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x31e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a6f; op2val:0x3f2e; +op3val:0x771e; valaddr_reg:x9; val_offset:123*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x9, 123*FLEN/8, x12, x1, x4) + +inst_66: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x32e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x31e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a6f; op2val:0x3f2e; +op3val:0x771e; valaddr_reg:x9; val_offset:126*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x9, 126*FLEN/8, x12, x1, x4) + +inst_67: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x32e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x31e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a6f; op2val:0x3f2e; +op3val:0x771e; valaddr_reg:x9; val_offset:129*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x9, 129*FLEN/8, x12, x1, x4) + +inst_68: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x32e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x31e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a6f; op2val:0x3f2e; +op3val:0x771e; valaddr_reg:x9; val_offset:132*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x9, 132*FLEN/8, x12, x1, x4) + +inst_69: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x32e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x31e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a6f; op2val:0x3f2e; +op3val:0x771e; valaddr_reg:x9; val_offset:135*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x9, 135*FLEN/8, x12, x1, x4) + +inst_70: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x0e and fm2 == 0x227 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x24e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dff; op2val:0x3a27; +op3val:0x724e; valaddr_reg:x9; val_offset:138*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x9, 138*FLEN/8, x12, x1, x4) + +inst_71: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x0e and fm2 == 0x227 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x24e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dff; op2val:0x3a27; +op3val:0x724e; valaddr_reg:x9; val_offset:141*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x9, 141*FLEN/8, x12, x1, x4) + +inst_72: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x0e and fm2 == 0x227 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x24e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dff; op2val:0x3a27; +op3val:0x724e; valaddr_reg:x9; val_offset:144*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x9, 144*FLEN/8, x12, x1, x4) + +inst_73: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x0e and fm2 == 0x227 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x24e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dff; op2val:0x3a27; +op3val:0x724e; valaddr_reg:x9; val_offset:147*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x9, 147*FLEN/8, x12, x1, x4) + +inst_74: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x0e and fm2 == 0x227 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x24e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dff; op2val:0x3a27; +op3val:0x724e; valaddr_reg:x9; val_offset:150*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x9, 150*FLEN/8, x12, x1, x4) + +inst_75: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x13e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7913; op2val:0x393e; +op3val:0x74a8; valaddr_reg:x9; val_offset:153*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x9, 153*FLEN/8, x12, x1, x4) + +inst_76: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x13e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7913; op2val:0x393e; +op3val:0x74a8; valaddr_reg:x9; val_offset:156*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x9, 156*FLEN/8, x12, x1, x4) + +inst_77: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x13e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7913; op2val:0x393e; +op3val:0x74a8; valaddr_reg:x9; val_offset:159*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x9, 159*FLEN/8, x12, x1, x4) + +inst_78: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x13e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7913; op2val:0x393e; +op3val:0x74a8; valaddr_reg:x9; val_offset:162*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x9, 162*FLEN/8, x12, x1, x4) + +inst_79: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x13e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7913; op2val:0x393e; +op3val:0x74a8; valaddr_reg:x9; val_offset:165*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x9, 165*FLEN/8, x12, x1, x4) + +inst_80: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x39b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1b1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0b4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b9b; op2val:0x35b1; +op3val:0x78b4; valaddr_reg:x9; val_offset:168*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x9, 168*FLEN/8, x12, x1, x4) + +inst_81: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x39b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1b1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0b4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b9b; op2val:0x35b1; +op3val:0x78b4; valaddr_reg:x9; val_offset:171*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x9, 171*FLEN/8, x12, x1, x4) + +inst_82: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x39b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1b1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0b4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b9b; op2val:0x35b1; +op3val:0x78b4; valaddr_reg:x9; val_offset:174*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x9, 174*FLEN/8, x12, x1, x4) + +inst_83: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x39b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1b1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0b4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b9b; op2val:0x35b1; +op3val:0x78b4; valaddr_reg:x9; val_offset:177*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x9, 177*FLEN/8, x12, x1, x4) + +inst_84: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x39b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1b1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0b4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b9b; op2val:0x35b1; +op3val:0x78b4; valaddr_reg:x9; val_offset:180*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x9, 180*FLEN/8, x12, x1, x4) + +inst_85: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x26c and fs2 == 0 and fe2 == 0x11 and fm2 == 0x081 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x13d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x726c; op2val:0x4481; +op3val:0x793d; valaddr_reg:x9; val_offset:183*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x9, 183*FLEN/8, x12, x1, x4) + +inst_86: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x26c and fs2 == 0 and fe2 == 0x11 and fm2 == 0x081 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x13d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x726c; op2val:0x4481; +op3val:0x793d; valaddr_reg:x9; val_offset:186*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x9, 186*FLEN/8, x12, x1, x4) + +inst_87: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x26c and fs2 == 0 and fe2 == 0x11 and fm2 == 0x081 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x13d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x726c; op2val:0x4481; +op3val:0x793d; valaddr_reg:x9; val_offset:189*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x9, 189*FLEN/8, x12, x1, x4) + +inst_88: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x26c and fs2 == 0 and fe2 == 0x11 and fm2 == 0x081 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x13d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x726c; op2val:0x4481; +op3val:0x793d; valaddr_reg:x9; val_offset:192*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x9, 192*FLEN/8, x12, x1, x4) + +inst_89: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x26c and fs2 == 0 and fe2 == 0x11 and fm2 == 0x081 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x13d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x726c; op2val:0x4481; +op3val:0x793d; valaddr_reg:x9; val_offset:195*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x9, 195*FLEN/8, x12, x1, x4) + +inst_90: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c3 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0cd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x375 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c3; op2val:0x3ccd; +op3val:0x7b75; valaddr_reg:x9; val_offset:198*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x9, 198*FLEN/8, x12, x1, x4) + +inst_91: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c3 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0cd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x375 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c3; op2val:0x3ccd; +op3val:0x7b75; valaddr_reg:x9; val_offset:201*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x9, 201*FLEN/8, x12, x1, x4) + +inst_92: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c3 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0cd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x375 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c3; op2val:0x3ccd; +op3val:0x7b75; valaddr_reg:x9; val_offset:204*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x9, 204*FLEN/8, x12, x1, x4) + +inst_93: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c3 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0cd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x375 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c3; op2val:0x3ccd; +op3val:0x7b75; valaddr_reg:x9; val_offset:207*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x9, 207*FLEN/8, x12, x1, x4) + +inst_94: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c3 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0cd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x375 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c3; op2val:0x3ccd; +op3val:0x7b75; valaddr_reg:x9; val_offset:210*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x9, 210*FLEN/8, x12, x1, x4) + +inst_95: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x345 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x076 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x01d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b45; op2val:0x3c76; +op3val:0x781d; valaddr_reg:x9; val_offset:213*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x9, 213*FLEN/8, x12, x1, x4) + +inst_96: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x345 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x076 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x01d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b45; op2val:0x3c76; +op3val:0x781d; valaddr_reg:x9; val_offset:216*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x9, 216*FLEN/8, x12, x1, x4) + +inst_97: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x345 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x076 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x01d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b45; op2val:0x3c76; +op3val:0x781d; valaddr_reg:x9; val_offset:219*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x9, 219*FLEN/8, x12, x1, x4) + +inst_98: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x345 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x076 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x01d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b45; op2val:0x3c76; +op3val:0x781d; valaddr_reg:x9; val_offset:222*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x9, 222*FLEN/8, x12, x1, x4) + +inst_99: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x345 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x076 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x01d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b45; op2val:0x3c76; +op3val:0x781d; valaddr_reg:x9; val_offset:225*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x9, 225*FLEN/8, x12, x1, x4) + +inst_100: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x127 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x37f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x194 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7927; op2val:0xb77f; +op3val:0x7994; valaddr_reg:x9; val_offset:228*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x9, 228*FLEN/8, x12, x1, x4) + +inst_101: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x127 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x37f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x194 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7927; op2val:0xb77f; +op3val:0x7994; valaddr_reg:x9; val_offset:231*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x9, 231*FLEN/8, x12, x1, x4) + +inst_102: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x127 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x37f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x194 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7927; op2val:0xb77f; +op3val:0x7994; valaddr_reg:x9; val_offset:234*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x9, 234*FLEN/8, x12, x1, x4) + +inst_103: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x127 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x37f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x194 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7927; op2val:0xb77f; +op3val:0x7994; valaddr_reg:x9; val_offset:237*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x9, 237*FLEN/8, x12, x1, x4) + +inst_104: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x127 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x37f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x194 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7927; op2val:0xb77f; +op3val:0x7994; valaddr_reg:x9; val_offset:240*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x9, 240*FLEN/8, x12, x1, x4) + +inst_105: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x270 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0e8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ce and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a70; op2val:0x40e8; +op3val:0x7bce; valaddr_reg:x9; val_offset:243*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x9, 243*FLEN/8, x12, x1, x4) + +inst_106: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x270 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0e8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ce and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a70; op2val:0x40e8; +op3val:0x7bce; valaddr_reg:x9; val_offset:246*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x9, 246*FLEN/8, x12, x1, x4) + +inst_107: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x270 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0e8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ce and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a70; op2val:0x40e8; +op3val:0x7bce; valaddr_reg:x9; val_offset:249*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x9, 249*FLEN/8, x12, x1, x4) + +inst_108: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x270 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0e8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ce and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a70; op2val:0x40e8; +op3val:0x7bce; valaddr_reg:x9; val_offset:252*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x9, 252*FLEN/8, x12, x1, x4) + +inst_109: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x270 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0e8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ce and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a70; op2val:0x40e8; +op3val:0x7bce; valaddr_reg:x9; val_offset:255*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x9, 255*FLEN/8, x12, x1, x4) + +inst_110: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x346 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x333 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1c7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6746; op2val:0xd333; +op3val:0x75c7; valaddr_reg:x9; val_offset:258*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x9, 258*FLEN/8, x12, x1, x4) + +inst_111: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x346 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x333 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1c7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6746; op2val:0xd333; +op3val:0x75c7; valaddr_reg:x9; val_offset:261*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x9, 261*FLEN/8, x12, x1, x4) + +inst_112: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x346 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x333 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1c7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6746; op2val:0xd333; +op3val:0x75c7; valaddr_reg:x9; val_offset:264*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x9, 264*FLEN/8, x12, x1, x4) + +inst_113: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x346 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x333 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1c7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6746; op2val:0xd333; +op3val:0x75c7; valaddr_reg:x9; val_offset:267*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x9, 267*FLEN/8, x12, x1, x4) + +inst_114: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x346 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x333 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1c7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6746; op2val:0xd333; +op3val:0x75c7; valaddr_reg:x9; val_offset:270*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x9, 270*FLEN/8, x12, x1, x4) + +inst_115: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0cf and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3a8 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0dd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78cf; op2val:0x43a8; +op3val:0x74dd; valaddr_reg:x9; val_offset:273*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x9, 273*FLEN/8, x12, x1, x4) + +inst_116: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0cf and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3a8 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0dd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78cf; op2val:0x43a8; +op3val:0x74dd; valaddr_reg:x9; val_offset:276*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x9, 276*FLEN/8, x12, x1, x4) + +inst_117: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0cf and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3a8 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0dd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78cf; op2val:0x43a8; +op3val:0x74dd; valaddr_reg:x9; val_offset:279*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x9, 279*FLEN/8, x12, x1, x4) + +inst_118: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0cf and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3a8 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0dd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78cf; op2val:0x43a8; +op3val:0x74dd; valaddr_reg:x9; val_offset:282*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x9, 282*FLEN/8, x12, x1, x4) + +inst_119: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0cf and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3a8 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0dd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78cf; op2val:0x43a8; +op3val:0x74dd; valaddr_reg:x9; val_offset:285*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x9, 285*FLEN/8, x12, x1, x4) + +inst_120: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b6 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2a3 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x1bc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78b6; op2val:0xc6a3; +op3val:0x6dbc; valaddr_reg:x9; val_offset:288*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x9, 288*FLEN/8, x12, x1, x4) + +inst_121: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b6 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2a3 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x1bc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78b6; op2val:0xc6a3; +op3val:0x6dbc; valaddr_reg:x9; val_offset:291*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x9, 291*FLEN/8, x12, x1, x4) + +inst_122: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b6 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2a3 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x1bc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78b6; op2val:0xc6a3; +op3val:0x6dbc; valaddr_reg:x9; val_offset:294*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x9, 294*FLEN/8, x12, x1, x4) + +inst_123: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b6 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2a3 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x1bc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78b6; op2val:0xc6a3; +op3val:0x6dbc; valaddr_reg:x9; val_offset:297*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x9, 297*FLEN/8, x12, x1, x4) + +inst_124: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b6 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2a3 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x1bc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78b6; op2val:0xc6a3; +op3val:0x6dbc; valaddr_reg:x9; val_offset:300*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x9, 300*FLEN/8, x12, x1, x4) + +inst_125: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x309 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x124 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x033 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b09; op2val:0x4524; +op3val:0x7833; valaddr_reg:x9; val_offset:303*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x9, 303*FLEN/8, x12, x1, x4) + +inst_126: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x309 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x124 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x033 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b09; op2val:0x4524; +op3val:0x7833; valaddr_reg:x9; val_offset:306*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x9, 306*FLEN/8, x12, x1, x4) + +inst_127: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x309 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x124 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x033 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b09; op2val:0x4524; +op3val:0x7833; valaddr_reg:x9; val_offset:309*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x9, 309*FLEN/8, x12, x1, x4) + +inst_128: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x309 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x124 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x033 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b09; op2val:0x4524; +op3val:0x7833; valaddr_reg:x9; val_offset:312*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x9, 312*FLEN/8, x12, x1, x4) + +inst_129: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x309 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x124 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x033 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b09; op2val:0x4524; +op3val:0x7833; valaddr_reg:x9; val_offset:315*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x9, 315*FLEN/8, x12, x1, x4) + +inst_130: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x379 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x3d9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f79; op2val:0xd3d9; +op3val:0x794c; valaddr_reg:x9; val_offset:318*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x9, 318*FLEN/8, x12, x1, x4) + +inst_131: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x379 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x3d9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f79; op2val:0xd3d9; +op3val:0x794c; valaddr_reg:x9; val_offset:321*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x9, 321*FLEN/8, x12, x1, x4) + +inst_132: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x379 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x3d9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f79; op2val:0xd3d9; +op3val:0x794c; valaddr_reg:x9; val_offset:324*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x9, 324*FLEN/8, x12, x1, x4) + +inst_133: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x379 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x3d9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f79; op2val:0xd3d9; +op3val:0x794c; valaddr_reg:x9; val_offset:327*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x9, 327*FLEN/8, x12, x1, x4) + +inst_134: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x379 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x3d9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f79; op2val:0xd3d9; +op3val:0x794c; valaddr_reg:x9; val_offset:330*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x9, 330*FLEN/8, x12, x1, x4) + +inst_135: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0fe and fs2 == 0 and fe2 == 0x13 and fm2 == 0x28f and fs3 == 0 and fe3 == 0x1c and fm3 == 0x246 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74fe; op2val:0x4e8f; +op3val:0x7246; valaddr_reg:x9; val_offset:333*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x9, 333*FLEN/8, x12, x1, x4) + +inst_136: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0fe and fs2 == 0 and fe2 == 0x13 and fm2 == 0x28f and fs3 == 0 and fe3 == 0x1c and fm3 == 0x246 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74fe; op2val:0x4e8f; +op3val:0x7246; valaddr_reg:x9; val_offset:336*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x9, 336*FLEN/8, x12, x1, x4) + +inst_137: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0fe and fs2 == 0 and fe2 == 0x13 and fm2 == 0x28f and fs3 == 0 and fe3 == 0x1c and fm3 == 0x246 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74fe; op2val:0x4e8f; +op3val:0x7246; valaddr_reg:x9; val_offset:339*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x9, 339*FLEN/8, x12, x1, x4) + +inst_138: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0fe and fs2 == 0 and fe2 == 0x13 and fm2 == 0x28f and fs3 == 0 and fe3 == 0x1c and fm3 == 0x246 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74fe; op2val:0x4e8f; +op3val:0x7246; valaddr_reg:x9; val_offset:342*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x9, 342*FLEN/8, x12, x1, x4) + +inst_139: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0fe and fs2 == 0 and fe2 == 0x13 and fm2 == 0x28f and fs3 == 0 and fe3 == 0x1c and fm3 == 0x246 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74fe; op2val:0x4e8f; +op3val:0x7246; valaddr_reg:x9; val_offset:345*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x9, 345*FLEN/8, x12, x1, x4) + +inst_140: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x257 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x32e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x292 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a57; op2val:0xb32e; +op3val:0x7a92; valaddr_reg:x9; val_offset:348*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x9, 348*FLEN/8, x12, x1, x4) + +inst_141: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x257 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x32e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x292 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a57; op2val:0xb32e; +op3val:0x7a92; valaddr_reg:x9; val_offset:351*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x9, 351*FLEN/8, x12, x1, x4) + +inst_142: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x257 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x32e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x292 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a57; op2val:0xb32e; +op3val:0x7a92; valaddr_reg:x9; val_offset:354*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x9, 354*FLEN/8, x12, x1, x4) + +inst_143: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3c1 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x133 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x02f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77c1; op2val:0x4133; +op3val:0x742f; valaddr_reg:x9; val_offset:357*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x9, 357*FLEN/8, x12, x1, x4) + +inst_144: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3c1 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x133 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x02f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77c1; op2val:0x4133; +op3val:0x742f; valaddr_reg:x9; val_offset:360*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x9, 360*FLEN/8, x12, x1, x4) + +inst_145: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3c1 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x133 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x02f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77c1; op2val:0x4133; +op3val:0x742f; valaddr_reg:x9; val_offset:363*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x9, 363*FLEN/8, x12, x1, x4) + +inst_146: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3c1 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x133 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x02f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77c1; op2val:0x4133; +op3val:0x742f; valaddr_reg:x9; val_offset:366*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x9, 366*FLEN/8, x12, x1, x4) + +inst_147: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3a5 and fs2 == 1 and fe2 == 0x18 and fm2 == 0x1a4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4fa5; op2val:0xe1a4; +op3val:0x794c; valaddr_reg:x9; val_offset:369*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x9, 369*FLEN/8, x12, x1, x4) + +inst_148: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x05c and fs2 == 0 and fe2 == 0x11 and fm2 == 0x29b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x269 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x745c; op2val:0x469b; +op3val:0x7a69; valaddr_reg:x9; val_offset:372*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x9, 372*FLEN/8, x12, x1, x4) + +inst_149: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x05c and fs2 == 0 and fe2 == 0x11 and fm2 == 0x29b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x269 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x745c; op2val:0x469b; +op3val:0x7a69; valaddr_reg:x9; val_offset:375*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x9, 375*FLEN/8, x12, x1, x4) + +inst_150: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x05c and fs2 == 0 and fe2 == 0x11 and fm2 == 0x29b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x269 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x745c; op2val:0x469b; +op3val:0x7a69; valaddr_reg:x9; val_offset:378*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x9, 378*FLEN/8, x12, x1, x4) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(31319,32,FLEN) +NAN_BOXED(45870,16,FLEN) +NAN_BOXED(31319,32,FLEN) +NAN_BOXED(31319,32,FLEN) +NAN_BOXED(45870,16,FLEN) +NAN_BOXED(45870,32,FLEN) +NAN_BOXED(31319,32,FLEN) +NAN_BOXED(45870,16,FLEN) +NAN_BOXED(31378,32,FLEN) +NAN_BOXED(31319,32,FLEN) +NAN_BOXED(45870,16,FLEN) +NAN_BOXED(31378,32,FLEN) +NAN_BOXED(31319,32,FLEN) +NAN_BOXED(45870,16,FLEN) +NAN_BOXED(31319,32,FLEN) +NAN_BOXED(30657,32,FLEN) +NAN_BOXED(30657,32,FLEN) +NAN_BOXED(30657,32,FLEN) +NAN_BOXED(30657,32,FLEN) +NAN_BOXED(30657,32,FLEN) +NAN_BOXED(29743,32,FLEN) +NAN_BOXED(30657,32,FLEN) +NAN_BOXED(16691,32,FLEN) +NAN_BOXED(16691,32,FLEN) +NAN_BOXED(30657,32,FLEN) +NAN_BOXED(16691,32,FLEN) +NAN_BOXED(29743,32,FLEN) +NAN_BOXED(30657,32,FLEN) +NAN_BOXED(30657,32,FLEN) +NAN_BOXED(30657,32,FLEN) +NAN_BOXED(20389,32,FLEN) +NAN_BOXED(57764,16,FLEN) +NAN_BOXED(31052,32,FLEN) +NAN_BOXED(20389,32,FLEN) +NAN_BOXED(20389,16,FLEN) +NAN_BOXED(31052,32,FLEN) +NAN_BOXED(20389,32,FLEN) +NAN_BOXED(57764,16,FLEN) +NAN_BOXED(31052,32,FLEN) +test_dataset_1: +NAN_BOXED(20389,32,FLEN) +NAN_BOXED(57764,16,FLEN) +NAN_BOXED(31052,32,FLEN) +NAN_BOXED(20389,32,FLEN) +NAN_BOXED(57764,16,FLEN) +NAN_BOXED(31052,32,FLEN) +NAN_BOXED(30597,32,FLEN) +NAN_BOXED(17275,32,FLEN) +NAN_BOXED(31251,32,FLEN) +NAN_BOXED(30597,32,FLEN) +NAN_BOXED(17275,32,FLEN) +NAN_BOXED(31251,32,FLEN) +NAN_BOXED(30597,32,FLEN) +NAN_BOXED(17275,32,FLEN) +NAN_BOXED(31251,32,FLEN) +NAN_BOXED(30597,32,FLEN) +NAN_BOXED(17275,32,FLEN) +NAN_BOXED(31251,32,FLEN) +NAN_BOXED(30597,32,FLEN) +NAN_BOXED(17275,32,FLEN) +NAN_BOXED(31251,32,FLEN) +NAN_BOXED(30199,32,FLEN) +NAN_BOXED(47341,16,FLEN) +NAN_BOXED(31272,32,FLEN) +NAN_BOXED(30199,32,FLEN) +NAN_BOXED(47341,16,FLEN) +NAN_BOXED(31272,32,FLEN) +NAN_BOXED(30199,32,FLEN) +NAN_BOXED(47341,16,FLEN) +NAN_BOXED(31272,32,FLEN) +NAN_BOXED(30199,32,FLEN) +NAN_BOXED(47341,16,FLEN) +NAN_BOXED(31272,32,FLEN) +test_dataset_2: +NAN_BOXED(30199,16,FLEN) +NAN_BOXED(47341,16,FLEN) +NAN_BOXED(31272,16,FLEN) +NAN_BOXED(29788,16,FLEN) +NAN_BOXED(18075,16,FLEN) +NAN_BOXED(31337,16,FLEN) +NAN_BOXED(29788,16,FLEN) +NAN_BOXED(18075,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(29788,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31337,16,FLEN) +NAN_BOXED(29788,16,FLEN) +NAN_BOXED(18075,16,FLEN) +NAN_BOXED(31337,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(18075,16,FLEN) +NAN_BOXED(31337,16,FLEN) +NAN_BOXED(31189,16,FLEN) +NAN_BOXED(47724,16,FLEN) +NAN_BOXED(30366,16,FLEN) +NAN_BOXED(31189,16,FLEN) +NAN_BOXED(47724,16,FLEN) +NAN_BOXED(30366,16,FLEN) +NAN_BOXED(31189,16,FLEN) +NAN_BOXED(47724,16,FLEN) +NAN_BOXED(30366,16,FLEN) +NAN_BOXED(31189,16,FLEN) +NAN_BOXED(47724,16,FLEN) +NAN_BOXED(30366,16,FLEN) +NAN_BOXED(31189,16,FLEN) +NAN_BOXED(47724,16,FLEN) +NAN_BOXED(30366,16,FLEN) +NAN_BOXED(30797,16,FLEN) +NAN_BOXED(16959,16,FLEN) +NAN_BOXED(31092,16,FLEN) +NAN_BOXED(30797,16,FLEN) +NAN_BOXED(16959,16,FLEN) +NAN_BOXED(31092,16,FLEN) +NAN_BOXED(30797,16,FLEN) +NAN_BOXED(16959,16,FLEN) +NAN_BOXED(31092,16,FLEN) +NAN_BOXED(30797,16,FLEN) +NAN_BOXED(16959,16,FLEN) +NAN_BOXED(31092,16,FLEN) +NAN_BOXED(30797,16,FLEN) +NAN_BOXED(16959,16,FLEN) +NAN_BOXED(31092,16,FLEN) +NAN_BOXED(29228,16,FLEN) +NAN_BOXED(49312,16,FLEN) +NAN_BOXED(30829,16,FLEN) +NAN_BOXED(29228,16,FLEN) +NAN_BOXED(49312,16,FLEN) +NAN_BOXED(30829,16,FLEN) +NAN_BOXED(29228,16,FLEN) +NAN_BOXED(49312,16,FLEN) +NAN_BOXED(30829,16,FLEN) +NAN_BOXED(29228,16,FLEN) +NAN_BOXED(49312,16,FLEN) +NAN_BOXED(30829,16,FLEN) +NAN_BOXED(29228,16,FLEN) +NAN_BOXED(49312,16,FLEN) +NAN_BOXED(30829,16,FLEN) +NAN_BOXED(31344,16,FLEN) +NAN_BOXED(15945,16,FLEN) +NAN_BOXED(29759,16,FLEN) +NAN_BOXED(31344,16,FLEN) +NAN_BOXED(15945,16,FLEN) +NAN_BOXED(29759,16,FLEN) +NAN_BOXED(31344,16,FLEN) +NAN_BOXED(15945,16,FLEN) +NAN_BOXED(29759,16,FLEN) +NAN_BOXED(31344,16,FLEN) +NAN_BOXED(15945,16,FLEN) +NAN_BOXED(29759,16,FLEN) +NAN_BOXED(31344,16,FLEN) +NAN_BOXED(15945,16,FLEN) +NAN_BOXED(29759,16,FLEN) +NAN_BOXED(31340,16,FLEN) +NAN_BOXED(46658,16,FLEN) +NAN_BOXED(31099,16,FLEN) +NAN_BOXED(31340,16,FLEN) +NAN_BOXED(46658,16,FLEN) +NAN_BOXED(31099,16,FLEN) +NAN_BOXED(31340,16,FLEN) +NAN_BOXED(46658,16,FLEN) +NAN_BOXED(31099,16,FLEN) +NAN_BOXED(31340,16,FLEN) +NAN_BOXED(46658,16,FLEN) +NAN_BOXED(31099,16,FLEN) +NAN_BOXED(31340,16,FLEN) +NAN_BOXED(46658,16,FLEN) +NAN_BOXED(31099,16,FLEN) +NAN_BOXED(31424,16,FLEN) +NAN_BOXED(15955,16,FLEN) +NAN_BOXED(30045,16,FLEN) +NAN_BOXED(31424,16,FLEN) +NAN_BOXED(15955,16,FLEN) +NAN_BOXED(30045,16,FLEN) +NAN_BOXED(31424,16,FLEN) +NAN_BOXED(15955,16,FLEN) +NAN_BOXED(30045,16,FLEN) +NAN_BOXED(31424,16,FLEN) +NAN_BOXED(15955,16,FLEN) +NAN_BOXED(30045,16,FLEN) +NAN_BOXED(31424,16,FLEN) +NAN_BOXED(15955,16,FLEN) +NAN_BOXED(30045,16,FLEN) +NAN_BOXED(28149,16,FLEN) +NAN_BOXED(49225,16,FLEN) +NAN_BOXED(31334,16,FLEN) +NAN_BOXED(28149,16,FLEN) +NAN_BOXED(49225,16,FLEN) +NAN_BOXED(31334,16,FLEN) +NAN_BOXED(28149,16,FLEN) +NAN_BOXED(49225,16,FLEN) +NAN_BOXED(31334,16,FLEN) +NAN_BOXED(28149,16,FLEN) +NAN_BOXED(49225,16,FLEN) +NAN_BOXED(31334,16,FLEN) +NAN_BOXED(28149,16,FLEN) +NAN_BOXED(49225,16,FLEN) +NAN_BOXED(31334,16,FLEN) +NAN_BOXED(31343,16,FLEN) +NAN_BOXED(16174,16,FLEN) +NAN_BOXED(30494,16,FLEN) +NAN_BOXED(31343,16,FLEN) +NAN_BOXED(16174,16,FLEN) +NAN_BOXED(30494,16,FLEN) +NAN_BOXED(31343,16,FLEN) +NAN_BOXED(16174,16,FLEN) +NAN_BOXED(30494,16,FLEN) +NAN_BOXED(31343,16,FLEN) +NAN_BOXED(16174,16,FLEN) +NAN_BOXED(30494,16,FLEN) +NAN_BOXED(31343,16,FLEN) +NAN_BOXED(16174,16,FLEN) +NAN_BOXED(30494,16,FLEN) +NAN_BOXED(28159,16,FLEN) +NAN_BOXED(14887,16,FLEN) +NAN_BOXED(29262,16,FLEN) +NAN_BOXED(28159,16,FLEN) +NAN_BOXED(14887,16,FLEN) +NAN_BOXED(29262,16,FLEN) +NAN_BOXED(28159,16,FLEN) +NAN_BOXED(14887,16,FLEN) +NAN_BOXED(29262,16,FLEN) +NAN_BOXED(28159,16,FLEN) +NAN_BOXED(14887,16,FLEN) +NAN_BOXED(29262,16,FLEN) +NAN_BOXED(28159,16,FLEN) +NAN_BOXED(14887,16,FLEN) +NAN_BOXED(29262,16,FLEN) +NAN_BOXED(30995,16,FLEN) +NAN_BOXED(14654,16,FLEN) +NAN_BOXED(29864,16,FLEN) +NAN_BOXED(30995,16,FLEN) +NAN_BOXED(14654,16,FLEN) +NAN_BOXED(29864,16,FLEN) +NAN_BOXED(30995,16,FLEN) +NAN_BOXED(14654,16,FLEN) +NAN_BOXED(29864,16,FLEN) +NAN_BOXED(30995,16,FLEN) +NAN_BOXED(14654,16,FLEN) +NAN_BOXED(29864,16,FLEN) +NAN_BOXED(30995,16,FLEN) +NAN_BOXED(14654,16,FLEN) +NAN_BOXED(29864,16,FLEN) +NAN_BOXED(31643,16,FLEN) +NAN_BOXED(13745,16,FLEN) +NAN_BOXED(30900,16,FLEN) +NAN_BOXED(31643,16,FLEN) +NAN_BOXED(13745,16,FLEN) +NAN_BOXED(30900,16,FLEN) +NAN_BOXED(31643,16,FLEN) +NAN_BOXED(13745,16,FLEN) +NAN_BOXED(30900,16,FLEN) +NAN_BOXED(31643,16,FLEN) +NAN_BOXED(13745,16,FLEN) +NAN_BOXED(30900,16,FLEN) +NAN_BOXED(31643,16,FLEN) +NAN_BOXED(13745,16,FLEN) +NAN_BOXED(30900,16,FLEN) +NAN_BOXED(29292,16,FLEN) +NAN_BOXED(17537,16,FLEN) +NAN_BOXED(31037,16,FLEN) +NAN_BOXED(29292,16,FLEN) +NAN_BOXED(17537,16,FLEN) +NAN_BOXED(31037,16,FLEN) +NAN_BOXED(29292,16,FLEN) +NAN_BOXED(17537,16,FLEN) +NAN_BOXED(31037,16,FLEN) +NAN_BOXED(29292,16,FLEN) +NAN_BOXED(17537,16,FLEN) +NAN_BOXED(31037,16,FLEN) +NAN_BOXED(29292,16,FLEN) +NAN_BOXED(17537,16,FLEN) +NAN_BOXED(31037,16,FLEN) +NAN_BOXED(30147,16,FLEN) +NAN_BOXED(15565,16,FLEN) +NAN_BOXED(31605,16,FLEN) +NAN_BOXED(30147,16,FLEN) +NAN_BOXED(15565,16,FLEN) +NAN_BOXED(31605,16,FLEN) +NAN_BOXED(30147,16,FLEN) +NAN_BOXED(15565,16,FLEN) +NAN_BOXED(31605,16,FLEN) +NAN_BOXED(30147,16,FLEN) +NAN_BOXED(15565,16,FLEN) +NAN_BOXED(31605,16,FLEN) +NAN_BOXED(30147,16,FLEN) +NAN_BOXED(15565,16,FLEN) +NAN_BOXED(31605,16,FLEN) +NAN_BOXED(31557,16,FLEN) +NAN_BOXED(15478,16,FLEN) +NAN_BOXED(30749,16,FLEN) +NAN_BOXED(31557,16,FLEN) +NAN_BOXED(15478,16,FLEN) +NAN_BOXED(30749,16,FLEN) +NAN_BOXED(31557,16,FLEN) +NAN_BOXED(15478,16,FLEN) +NAN_BOXED(30749,16,FLEN) +NAN_BOXED(31557,16,FLEN) +NAN_BOXED(15478,16,FLEN) +NAN_BOXED(30749,16,FLEN) +NAN_BOXED(31557,16,FLEN) +NAN_BOXED(15478,16,FLEN) +NAN_BOXED(30749,16,FLEN) +NAN_BOXED(31015,16,FLEN) +NAN_BOXED(46975,16,FLEN) +NAN_BOXED(31124,16,FLEN) +NAN_BOXED(31015,16,FLEN) +NAN_BOXED(46975,16,FLEN) +NAN_BOXED(31124,16,FLEN) +NAN_BOXED(31015,16,FLEN) +NAN_BOXED(46975,16,FLEN) +NAN_BOXED(31124,16,FLEN) +NAN_BOXED(31015,16,FLEN) +NAN_BOXED(46975,16,FLEN) +NAN_BOXED(31124,16,FLEN) +NAN_BOXED(31015,16,FLEN) +NAN_BOXED(46975,16,FLEN) +NAN_BOXED(31124,16,FLEN) +NAN_BOXED(31344,16,FLEN) +NAN_BOXED(16616,16,FLEN) +NAN_BOXED(31694,16,FLEN) +NAN_BOXED(31344,16,FLEN) +NAN_BOXED(16616,16,FLEN) +NAN_BOXED(31694,16,FLEN) +NAN_BOXED(31344,16,FLEN) +NAN_BOXED(16616,16,FLEN) +NAN_BOXED(31694,16,FLEN) +NAN_BOXED(31344,16,FLEN) +NAN_BOXED(16616,16,FLEN) +NAN_BOXED(31694,16,FLEN) +NAN_BOXED(31344,16,FLEN) +NAN_BOXED(16616,16,FLEN) +NAN_BOXED(31694,16,FLEN) +NAN_BOXED(26438,16,FLEN) +NAN_BOXED(54067,16,FLEN) +NAN_BOXED(30151,16,FLEN) +NAN_BOXED(26438,16,FLEN) +NAN_BOXED(54067,16,FLEN) +NAN_BOXED(30151,16,FLEN) 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+NAN_BOXED(28092,16,FLEN) +NAN_BOXED(31497,16,FLEN) +NAN_BOXED(17700,16,FLEN) +NAN_BOXED(30771,16,FLEN) +NAN_BOXED(31497,16,FLEN) +NAN_BOXED(17700,16,FLEN) +NAN_BOXED(30771,16,FLEN) +NAN_BOXED(31497,16,FLEN) +NAN_BOXED(17700,16,FLEN) +NAN_BOXED(30771,16,FLEN) +NAN_BOXED(31497,16,FLEN) +NAN_BOXED(17700,16,FLEN) +NAN_BOXED(30771,16,FLEN) +NAN_BOXED(31497,16,FLEN) +NAN_BOXED(17700,16,FLEN) +NAN_BOXED(30771,16,FLEN) +NAN_BOXED(28537,16,FLEN) +NAN_BOXED(54233,16,FLEN) +NAN_BOXED(31052,16,FLEN) +NAN_BOXED(28537,16,FLEN) +NAN_BOXED(54233,16,FLEN) +NAN_BOXED(31052,16,FLEN) +NAN_BOXED(28537,16,FLEN) +NAN_BOXED(54233,16,FLEN) +NAN_BOXED(31052,16,FLEN) +NAN_BOXED(28537,16,FLEN) +NAN_BOXED(54233,16,FLEN) +NAN_BOXED(31052,16,FLEN) +NAN_BOXED(28537,16,FLEN) +NAN_BOXED(54233,16,FLEN) +NAN_BOXED(31052,16,FLEN) +NAN_BOXED(29950,16,FLEN) +NAN_BOXED(20111,16,FLEN) +NAN_BOXED(29254,16,FLEN) +NAN_BOXED(29950,16,FLEN) +NAN_BOXED(20111,16,FLEN) +NAN_BOXED(29254,16,FLEN) +NAN_BOXED(29950,16,FLEN) +NAN_BOXED(20111,16,FLEN) +NAN_BOXED(29254,16,FLEN) +NAN_BOXED(29950,16,FLEN) +NAN_BOXED(20111,16,FLEN) +NAN_BOXED(29254,16,FLEN) +NAN_BOXED(29950,16,FLEN) +NAN_BOXED(20111,16,FLEN) +NAN_BOXED(29254,16,FLEN) +NAN_BOXED(31319,16,FLEN) +NAN_BOXED(45870,16,FLEN) +NAN_BOXED(31378,16,FLEN) +NAN_BOXED(31319,16,FLEN) +NAN_BOXED(45870,16,FLEN) +NAN_BOXED(31378,16,FLEN) +NAN_BOXED(31319,16,FLEN) +NAN_BOXED(45870,16,FLEN) +NAN_BOXED(31378,16,FLEN) +NAN_BOXED(30657,16,FLEN) +NAN_BOXED(16691,16,FLEN) +NAN_BOXED(29743,16,FLEN) +NAN_BOXED(30657,16,FLEN) +NAN_BOXED(16691,16,FLEN) +NAN_BOXED(29743,16,FLEN) +NAN_BOXED(30657,16,FLEN) +NAN_BOXED(16691,16,FLEN) +NAN_BOXED(29743,16,FLEN) +NAN_BOXED(30657,16,FLEN) +NAN_BOXED(16691,16,FLEN) +NAN_BOXED(29743,16,FLEN) +NAN_BOXED(20389,16,FLEN) +NAN_BOXED(57764,16,FLEN) +NAN_BOXED(31052,16,FLEN) +NAN_BOXED(29788,16,FLEN) +NAN_BOXED(18075,16,FLEN) +NAN_BOXED(31337,16,FLEN) +NAN_BOXED(29788,16,FLEN) +NAN_BOXED(18075,16,FLEN) +NAN_BOXED(31337,16,FLEN) +NAN_BOXED(29788,16,FLEN) +NAN_BOXED(18075,16,FLEN) +NAN_BOXED(31337,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x5_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x5_1: + .fill 30*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x3_0: + .fill 34*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_0: + .fill 238*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fnmadd_b5-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fnmadd_b5-01.S new file mode 100644 index 000000000..e1eae727b --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fnmadd_b5-01.S @@ -0,0 +1,2419 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 06:03:37 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fnmadd.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fnmadd.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fnmadd_b5 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fnmadd_b5) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x5,test_dataset_0) +RVTEST_SIGBASE(x4,signature_x4_1) + +inst_0: +// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==x10, rs2==x18, rs3==x10, rd==x7,fs1 == 0 and fe1 == 0x1e and fm1 == 0x257 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x024 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x292 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x10; op2:x18; op3:x10; dest:x7; op1val:0x7a57; op2val:0x3c24; +op3val:0x7a57; valaddr_reg:x5; val_offset:0*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x7, x10, x18, x10, dyn, 0, 0, x5, 0*FLEN/8, x11, x4, x6) + +inst_1: +// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==x8, rs2==x2, rs3==x2, rd==x3,fs1 == 0 and fe1 == 0x1e and fm1 == 0x257 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x024 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x292 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x8; op2:x2; op3:x2; dest:x3; op1val:0x7a57; op2val:0x3c24; +op3val:0x3c24; valaddr_reg:x5; val_offset:3*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x3, x8, x2, x2, dyn, 32, 0, x5, 3*FLEN/8, x11, x4, x6) + +inst_2: +// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==x31, rs2==x29, rs3==x19, rd==x17,fs1 == 0 and fe1 == 0x1e and fm1 == 0x257 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x024 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x292 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x31; op2:x29; op3:x19; dest:x17; op1val:0x7a57; op2val:0x3c24; +op3val:0x7a92; valaddr_reg:x5; val_offset:6*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x17, x31, x29, x19, dyn, 64, 0, x5, 6*FLEN/8, x11, x4, x6) + +inst_3: +// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==x2, rs2==x15, rs3==x21, rd==x15,fs1 == 0 and fe1 == 0x1e and fm1 == 0x257 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x024 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x292 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x2; op2:x15; op3:x21; dest:x15; op1val:0x7a57; op2val:0x3c24; +op3val:0x7a92; valaddr_reg:x5; val_offset:9*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x15, x2, x15, x21, dyn, 96, 0, x5, 9*FLEN/8, x11, x4, x6) + +inst_4: +// rs1 == rd == rs3 != rs2, rs1==x18, rs2==x1, rs3==x18, rd==x18,fs1 == 0 and fe1 == 0x1e and fm1 == 0x257 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x024 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x292 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x18; op2:x1; op3:x18; dest:x18; op1val:0x7a57; op2val:0x3c24; +op3val:0x7a57; valaddr_reg:x5; val_offset:12*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x18, x18, x1, x18, dyn, 128, 0, x5, 12*FLEN/8, x11, x4, x6) + +inst_5: +// rs1 == rs2 == rs3 != rd, rs1==x14, rs2==x14, rs3==x14, rd==x12,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3c1 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x050 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x02f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x14; op2:x14; op3:x14; dest:x12; op1val:0x77c1; op2val:0x77c1; +op3val:0x77c1; valaddr_reg:x5; val_offset:15*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x12, x14, x14, x14, dyn, 0, 0, x5, 15*FLEN/8, x11, x4, x6) + +inst_6: +// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==x25, rs2==x25, rs3==x12, rd==x13,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3c1 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x050 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x02f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x25; op2:x25; op3:x12; dest:x13; op1val:0x77c1; op2val:0x77c1; +op3val:0x742f; valaddr_reg:x5; val_offset:18*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x13, x25, x25, x12, dyn, 32, 0, x5, 18*FLEN/8, x11, x4, x6) + +inst_7: +// rd == rs2 == rs3 != rs1, rs1==x20, rs2==x16, rs3==x16, rd==x16,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3c1 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x050 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x02f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x20; op2:x16; op3:x16; dest:x16; op1val:0x77c1; op2val:0x3850; +op3val:0x3850; valaddr_reg:x5; val_offset:21*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x16, x20, x16, x16, dyn, 64, 0, x5, 21*FLEN/8, x11, x4, x6) + +inst_8: +// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==x9, rs2==x24, rs3==x1, rd==x9,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3c1 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x050 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x02f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x9; op2:x24; op3:x1; dest:x9; op1val:0x77c1; op2val:0x3850; +op3val:0x742f; valaddr_reg:x5; val_offset:24*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x9, x9, x24, x1, dyn, 96, 0, x5, 24*FLEN/8, x11, x4, x6) + +inst_9: +// rs1 == rs2 == rs3 == rd, rs1==x22, rs2==x22, rs3==x22, rd==x22,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3c1 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x050 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x02f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x22; op2:x22; op3:x22; dest:x22; op1val:0x77c1; op2val:0x77c1; +op3val:0x77c1; valaddr_reg:x5; val_offset:27*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x22, x22, x22, x22, dyn, 128, 0, x5, 27*FLEN/8, x11, x4, x6) + +inst_10: +// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==x29, rs2==x28, rs3==x20, rd==x20,fs1 == 0 and fe1 == 0x13 and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x18b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x29; op2:x28; op3:x20; dest:x20; op1val:0x4fa5; op2val:0x658b; +op3val:0x794c; valaddr_reg:x5; val_offset:30*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x20, x29, x28, x20, dyn, 0, 0, x5, 30*FLEN/8, x11, x4, x6) + +inst_11: +// rs1 == rs2 == rd != rs3, rs1==x19, rs2==x19, rs3==x0, rd==x19,fs1 == 0 and fe1 == 0x13 and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x18b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x19; op2:x19; op3:x0; dest:x19; op1val:0x4fa5; op2val:0x4fa5; +op3val:0x0; valaddr_reg:x5; val_offset:33*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x19, x19, x19, x0, dyn, 32, 0, x5, 33*FLEN/8, x11, x4, x6) +RVTEST_VALBASEUPD(x1,test_dataset_1) + +inst_12: +// rs1==x28, rs2==x23, rs3==x30, rd==x14,fs1 == 0 and fe1 == 0x13 and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x18b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x28; op2:x23; op3:x30; dest:x14; op1val:0x4fa5; op2val:0x658b; +op3val:0x794c; valaddr_reg:x1; val_offset:0*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x14, x28, x23, x30, dyn, 64, 0, x1, 0*FLEN/8, x17, x4, x6) + +inst_13: +// rs1==x15, rs2==x5, rs3==x8, rd==x21,fs1 == 0 and fe1 == 0x13 and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x18b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x15; op2:x5; op3:x8; dest:x21; op1val:0x4fa5; op2val:0x658b; +op3val:0x794c; valaddr_reg:x1; val_offset:3*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x21, x15, x5, x8, dyn, 96, 0, x1, 3*FLEN/8, x17, x4, x6) +RVTEST_SIGBASE(x2,signature_x2_0) + +inst_14: +// rs1==x16, rs2==x26, rs3==x31, rd==x29,fs1 == 0 and fe1 == 0x13 and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x18b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x16; op2:x26; op3:x31; dest:x29; op1val:0x4fa5; op2val:0x658b; +op3val:0x794c; valaddr_reg:x1; val_offset:6*FLEN/8; rmval:dyn; +testreg:x8; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x29, x16, x26, x31, dyn, 128, 0, x1, 6*FLEN/8, x17, x2, x8) + +inst_15: +// rs1==x13, rs2==x30, rs3==x5, rd==x27,fs1 == 0 and fe1 == 0x1d and fm1 == 0x385 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x276 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x213 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x13; op2:x30; op3:x5; dest:x27; op1val:0x7785; op2val:0x3e76; +op3val:0x7a13; valaddr_reg:x1; val_offset:9*FLEN/8; rmval:dyn; +testreg:x8; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x27, x13, x30, x5, dyn, 0, 0, x1, 9*FLEN/8, x17, x2, x8) + +inst_16: +// rs1==x11, rs2==x10, rs3==x27, rd==x23,fs1 == 0 and fe1 == 0x1d and fm1 == 0x385 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x276 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x213 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x11; op2:x10; op3:x27; dest:x23; op1val:0x7785; op2val:0x3e76; +op3val:0x7a13; valaddr_reg:x1; val_offset:12*FLEN/8; rmval:dyn; +testreg:x8; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x23, x11, x10, x27, dyn, 32, 0, x1, 12*FLEN/8, x17, x2, x8) + +inst_17: +// rs1==x3, rs2==x13, rs3==x17, rd==x25,fs1 == 0 and fe1 == 0x1d and fm1 == 0x385 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x276 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x213 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x3; op2:x13; op3:x17; dest:x25; op1val:0x7785; op2val:0x3e76; +op3val:0x7a13; valaddr_reg:x1; val_offset:15*FLEN/8; rmval:dyn; +testreg:x8; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x25, x3, x13, x17, dyn, 64, 0, x1, 15*FLEN/8, x17, x2, x8) + +inst_18: +// rs1==x4, rs2==x7, rs3==x29, rd==x26,fs1 == 0 and fe1 == 0x1d and fm1 == 0x385 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x276 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x213 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x4; op2:x7; op3:x29; dest:x26; op1val:0x7785; op2val:0x3e76; +op3val:0x7a13; valaddr_reg:x1; val_offset:18*FLEN/8; rmval:dyn; +testreg:x8; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x26, x4, x7, x29, dyn, 96, 0, x1, 18*FLEN/8, x17, x2, x8) + +inst_19: +// rs1==x27, rs2==x12, rs3==x4, rd==x30,fs1 == 0 and fe1 == 0x1d and fm1 == 0x385 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x276 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x213 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x27; op2:x12; op3:x4; dest:x30; op1val:0x7785; op2val:0x3e76; +op3val:0x7a13; valaddr_reg:x1; val_offset:21*FLEN/8; rmval:dyn; +testreg:x8; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x30, x27, x12, x4, dyn, 128, 0, x1, 21*FLEN/8, x17, x2, x8) + +inst_20: +// rs1==x12, rs2==x6, rs3==x7, rd==x0,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1f7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x020 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x228 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x12; op2:x6; op3:x7; dest:x0; op1val:0x75f7; op2val:0x4020; +op3val:0x7a28; valaddr_reg:x1; val_offset:24*FLEN/8; rmval:dyn; +testreg:x8; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x0, x12, x6, x7, dyn, 0, 0, x1, 24*FLEN/8, x17, x2, x8) + +inst_21: +// rs1==x5, rs2==x4, rs3==x23, rd==x31,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1f7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x020 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x228 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x5; op2:x4; op3:x23; dest:x31; op1val:0x75f7; op2val:0x4020; +op3val:0x7a28; valaddr_reg:x1; val_offset:27*FLEN/8; rmval:dyn; +testreg:x8; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x5, x4, x23, dyn, 32, 0, x1, 27*FLEN/8, x17, x2, x8) + +inst_22: +// rs1==x30, rs2==x9, rs3==x26, rd==x11,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1f7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x020 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x228 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x9; op3:x26; dest:x11; op1val:0x75f7; op2val:0x4020; +op3val:0x7a28; valaddr_reg:x1; val_offset:30*FLEN/8; rmval:dyn; +testreg:x8; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x11, x30, x9, x26, dyn, 64, 0, x1, 30*FLEN/8, x17, x2, x8) +RVTEST_VALBASEUPD(x9,test_dataset_2) + +inst_23: +// rs1==x24, rs2==x21, rs3==x13, rd==x28,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1f7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x020 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x228 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x24; op2:x21; op3:x13; dest:x28; op1val:0x75f7; op2val:0x4020; +op3val:0x7a28; valaddr_reg:x9; val_offset:0*FLEN/8; rmval:dyn; +testreg:x8; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x28, x24, x21, x13, dyn, 96, 0, x9, 0*FLEN/8, x12, x2, x8) + +inst_24: +// rs1==x23, rs2==x17, rs3==x28, rd==x1,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1f7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x020 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x228 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x23; op2:x17; op3:x28; dest:x1; op1val:0x75f7; op2val:0x4020; +op3val:0x7a28; valaddr_reg:x9; val_offset:3*FLEN/8; rmval:dyn; +testreg:x8; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x1, x23, x17, x28, dyn, 128, 0, x9, 3*FLEN/8, x12, x2, x8) + +inst_25: +// rs1==x17, rs2==x0, rs3==x24, rd==x6,fs1 == 0 and fe1 == 0x1d and fm1 == 0x05c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x269 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x17; op2:x0; op3:x24; dest:x6; op1val:0x745c; op2val:0x0; +op3val:0x7a69; valaddr_reg:x9; val_offset:6*FLEN/8; rmval:dyn; +testreg:x8; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x6, x17, x0, x24, dyn, 0, 0, x9, 6*FLEN/8, x12, x2, x8) + +inst_26: +// rs1==x0, rs2==x11, rs3==x25, rd==x24,fs1 == 0 and fe1 == 0x1d and fm1 == 0x05c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x269 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x0; op2:x11; op3:x25; dest:x24; op1val:0x0; op2val:0x41e1; +op3val:0x7a69; valaddr_reg:x9; val_offset:9*FLEN/8; rmval:dyn; +testreg:x8; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x24, x0, x11, x25, dyn, 32, 0, x9, 9*FLEN/8, x12, x2, x8) + +inst_27: +// rs1==x6, rs2==x27, rs3==x9, rd==x4,fs1 == 0 and fe1 == 0x1d and fm1 == 0x05c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x269 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x6; op2:x27; op3:x9; dest:x4; op1val:0x745c; op2val:0x41e1; +op3val:0x7a69; valaddr_reg:x9; val_offset:12*FLEN/8; rmval:dyn; +testreg:x8; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x4, x6, x27, x9, dyn, 64, 0, x9, 12*FLEN/8, x12, x2, x8) + +inst_28: +// rs1==x1, rs2==x20, rs3==x11, rd==x10,fs1 == 0 and fe1 == 0x1d and fm1 == 0x05c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x269 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x1; op2:x20; op3:x11; dest:x10; op1val:0x745c; op2val:0x41e1; +op3val:0x7a69; valaddr_reg:x9; val_offset:15*FLEN/8; rmval:dyn; +testreg:x8; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x10, x1, x20, x11, dyn, 96, 0, x9, 15*FLEN/8, x12, x2, x8) + +inst_29: +// rs1==x21, rs2==x8, rs3==x15, rd==x5,fs1 == 0 and fe1 == 0x1d and fm1 == 0x05c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x269 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x21; op2:x8; op3:x15; dest:x5; op1val:0x745c; op2val:0x41e1; +op3val:0x7a69; valaddr_reg:x9; val_offset:18*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x5, x21, x8, x15, dyn, 128, 0, x9, 18*FLEN/8, x12, x2, x4) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_30: +// rs1==x7, rs2==x31, rs3==x6, rd==x8,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x089 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x29e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x7; op2:x31; op3:x6; dest:x8; op1val:0x79d5; op2val:0x3889; +op3val:0x769e; valaddr_reg:x9; val_offset:21*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x8, x7, x31, x6, dyn, 0, 0, x9, 21*FLEN/8, x12, x1, x4) + +inst_31: +// rs1==x26,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x089 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x29e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x26; op2:x7; op3:x28; dest:x6; op1val:0x79d5; op2val:0x3889; +op3val:0x769e; valaddr_reg:x9; val_offset:24*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x6, x26, x7, x28, dyn, 32, 0, x9, 24*FLEN/8, x12, x1, x4) + +inst_32: +// rs2==x3,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x089 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x29e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x28; op2:x3; op3:x12; dest:x17; op1val:0x79d5; op2val:0x3889; +op3val:0x769e; valaddr_reg:x9; val_offset:27*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x17, x28, x3, x12, dyn, 64, 0, x9, 27*FLEN/8, x12, x1, x4) + +inst_33: +// rs3==x3,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x089 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x29e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x31; op2:x11; op3:x3; dest:x7; op1val:0x79d5; op2val:0x3889; +op3val:0x769e; valaddr_reg:x9; val_offset:30*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x7, x31, x11, x3, dyn, 96, 0, x9, 30*FLEN/8, x12, x1, x4) + +inst_34: +// rd==x2,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x089 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x29e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x28; op2:x14; op3:x3; dest:x2; op1val:0x79d5; op2val:0x3889; +op3val:0x769e; valaddr_reg:x9; val_offset:33*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x2, x28, x14, x3, dyn, 128, 0, x9, 33*FLEN/8, x12, x1, x4) + +inst_35: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x111 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x174 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x784d; op2val:0x3d11; +op3val:0x7974; valaddr_reg:x9; val_offset:36*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x9, 36*FLEN/8, x12, x1, x4) + +inst_36: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x111 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x174 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x784d; op2val:0x3d11; +op3val:0x7974; valaddr_reg:x9; val_offset:39*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x9, 39*FLEN/8, x12, x1, x4) + +inst_37: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x111 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x174 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x784d; op2val:0x3d11; +op3val:0x7974; valaddr_reg:x9; val_offset:42*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x9, 42*FLEN/8, x12, x1, x4) + +inst_38: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x111 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x174 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x784d; op2val:0x3d11; +op3val:0x7974; valaddr_reg:x9; val_offset:45*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x9, 45*FLEN/8, x12, x1, x4) + +inst_39: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x111 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x174 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x784d; op2val:0x3d11; +op3val:0x7974; valaddr_reg:x9; val_offset:48*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x9, 48*FLEN/8, x12, x1, x4) + +inst_40: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x22c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1bc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x06d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x722c; op2val:0x41bc; +op3val:0x786d; valaddr_reg:x9; val_offset:51*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x9, 51*FLEN/8, x12, x1, x4) + +inst_41: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x22c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1bc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x06d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x722c; op2val:0x41bc; +op3val:0x786d; valaddr_reg:x9; val_offset:54*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x9, 54*FLEN/8, x12, x1, x4) + +inst_42: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x22c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1bc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x06d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x722c; op2val:0x41bc; +op3val:0x786d; valaddr_reg:x9; val_offset:57*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x9, 57*FLEN/8, x12, x1, x4) + +inst_43: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x22c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1bc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x06d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x722c; op2val:0x41bc; +op3val:0x786d; valaddr_reg:x9; val_offset:60*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x9, 60*FLEN/8, x12, x1, x4) + +inst_44: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x22c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1bc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x06d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x722c; op2val:0x41bc; +op3val:0x786d; valaddr_reg:x9; val_offset:63*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x9, 63*FLEN/8, x12, x1, x4) + +inst_45: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x270 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x146 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a70; op2val:0x3546; +op3val:0x743f; valaddr_reg:x9; val_offset:66*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x9, 66*FLEN/8, x12, x1, x4) + +inst_46: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x270 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x146 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x03f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a70; op2val:0x3546; +op3val:0x743f; valaddr_reg:x9; val_offset:69*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x9, 69*FLEN/8, x12, x1, x4) + +inst_47: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x270 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x146 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x03f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a70; op2val:0x3546; +op3val:0x743f; valaddr_reg:x9; val_offset:72*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x9, 72*FLEN/8, x12, x1, x4) + +inst_48: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x270 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x146 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x03f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a70; op2val:0x3546; +op3val:0x743f; valaddr_reg:x9; val_offset:75*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x9, 75*FLEN/8, x12, x1, x4) + +inst_49: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x270 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x146 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x03f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a70; op2val:0x3546; +op3val:0x743f; valaddr_reg:x9; val_offset:78*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x9, 78*FLEN/8, x12, x1, x4) + +inst_50: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x17b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a6c; op2val:0x3ad4; +op3val:0x797b; valaddr_reg:x9; val_offset:81*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x9, 81*FLEN/8, x12, x1, x4) + +inst_51: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x17b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a6c; op2val:0x3ad4; +op3val:0x797b; valaddr_reg:x9; val_offset:84*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x9, 84*FLEN/8, x12, x1, x4) + +inst_52: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x17b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a6c; op2val:0x3ad4; +op3val:0x797b; valaddr_reg:x9; val_offset:87*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x9, 87*FLEN/8, x12, x1, x4) + +inst_53: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x17b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a6c; op2val:0x3ad4; +op3val:0x797b; valaddr_reg:x9; val_offset:90*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x9, 90*FLEN/8, x12, x1, x4) + +inst_54: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x17b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a6c; op2val:0x3ad4; +op3val:0x797b; valaddr_reg:x9; val_offset:93*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x9, 93*FLEN/8, x12, x1, x4) + +inst_55: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x25c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x15d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ac0; op2val:0x365c; +op3val:0x755d; valaddr_reg:x9; val_offset:96*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x9, 96*FLEN/8, x12, x1, x4) + +inst_56: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x25c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x15d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ac0; op2val:0x365c; +op3val:0x755d; valaddr_reg:x9; val_offset:99*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x9, 99*FLEN/8, x12, x1, x4) + +inst_57: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x25c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x15d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ac0; op2val:0x365c; +op3val:0x755d; valaddr_reg:x9; val_offset:102*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x9, 102*FLEN/8, x12, x1, x4) + +inst_58: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x25c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x15d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ac0; op2val:0x365c; +op3val:0x755d; valaddr_reg:x9; val_offset:105*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x9, 105*FLEN/8, x12, x1, x4) + +inst_59: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x25c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x15d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ac0; op2val:0x365c; +op3val:0x755d; valaddr_reg:x9; val_offset:108*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x9, 108*FLEN/8, x12, x1, x4) + +inst_60: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1f5 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x04b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x266 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6df5; op2val:0x484b; +op3val:0x7a66; valaddr_reg:x9; val_offset:111*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x9, 111*FLEN/8, x12, x1, x4) + +inst_61: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1f5 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x04b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x266 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6df5; op2val:0x484b; +op3val:0x7a66; valaddr_reg:x9; val_offset:114*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x9, 114*FLEN/8, x12, x1, x4) + +inst_62: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1f5 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x04b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x266 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6df5; op2val:0x484b; +op3val:0x7a66; valaddr_reg:x9; val_offset:117*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x9, 117*FLEN/8, x12, x1, x4) + +inst_63: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1f5 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x04b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x266 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6df5; op2val:0x484b; +op3val:0x7a66; valaddr_reg:x9; val_offset:120*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x9, 120*FLEN/8, x12, x1, x4) + +inst_64: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1f5 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x04b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x266 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6df5; op2val:0x484b; +op3val:0x7a66; valaddr_reg:x9; val_offset:123*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x9, 123*FLEN/8, x12, x1, x4) + +inst_65: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x06c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x31e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a6f; op2val:0x386c; +op3val:0x771e; valaddr_reg:x9; val_offset:126*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x9, 126*FLEN/8, x12, x1, x4) + +inst_66: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x06c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x31e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a6f; op2val:0x386c; +op3val:0x771e; valaddr_reg:x9; val_offset:129*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x9, 129*FLEN/8, x12, x1, x4) + +inst_67: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x06c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x31e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a6f; op2val:0x386c; +op3val:0x771e; valaddr_reg:x9; val_offset:132*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x9, 132*FLEN/8, x12, x1, x4) + +inst_68: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x06c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x31e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a6f; op2val:0x386c; +op3val:0x771e; valaddr_reg:x9; val_offset:135*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x9, 135*FLEN/8, x12, x1, x4) + +inst_69: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x06c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x31e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a6f; op2val:0x386c; +op3val:0x771e; valaddr_reg:x9; val_offset:138*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x9, 138*FLEN/8, x12, x1, x4) + +inst_70: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x10 and fm2 == 0x034 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x24e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dff; op2val:0x4034; +op3val:0x724e; valaddr_reg:x9; val_offset:141*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x9, 141*FLEN/8, x12, x1, x4) + +inst_71: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x10 and fm2 == 0x034 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x24e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dff; op2val:0x4034; +op3val:0x724e; valaddr_reg:x9; val_offset:144*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x9, 144*FLEN/8, x12, x1, x4) + +inst_72: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x10 and fm2 == 0x034 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x24e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dff; op2val:0x4034; +op3val:0x724e; valaddr_reg:x9; val_offset:147*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x9, 147*FLEN/8, x12, x1, x4) + +inst_73: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x10 and fm2 == 0x034 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x24e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dff; op2val:0x4034; +op3val:0x724e; valaddr_reg:x9; val_offset:150*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x9, 150*FLEN/8, x12, x1, x4) + +inst_74: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x10 and fm2 == 0x034 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x24e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dff; op2val:0x4034; +op3val:0x724e; valaddr_reg:x9; val_offset:153*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x9, 153*FLEN/8, x12, x1, x4) + +inst_75: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x356 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7913; op2val:0x3756; +op3val:0x74a8; valaddr_reg:x9; val_offset:156*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x9, 156*FLEN/8, x12, x1, x4) + +inst_76: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x356 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7913; op2val:0x3756; +op3val:0x74a8; valaddr_reg:x9; val_offset:159*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x9, 159*FLEN/8, x12, x1, x4) + +inst_77: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x356 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7913; op2val:0x3756; +op3val:0x74a8; valaddr_reg:x9; val_offset:162*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x9, 162*FLEN/8, x12, x1, x4) + +inst_78: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x356 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7913; op2val:0x3756; +op3val:0x74a8; valaddr_reg:x9; val_offset:165*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x9, 165*FLEN/8, x12, x1, x4) + +inst_79: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x356 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7913; op2val:0x3756; +op3val:0x74a8; valaddr_reg:x9; val_offset:168*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x9, 168*FLEN/8, x12, x1, x4) + +inst_80: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x39b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0f3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0b4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b9b; op2val:0x38f3; +op3val:0x78b4; valaddr_reg:x9; val_offset:171*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x9, 171*FLEN/8, x12, x1, x4) + +inst_81: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x39b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0f3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0b4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b9b; op2val:0x38f3; +op3val:0x78b4; valaddr_reg:x9; val_offset:174*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x9, 174*FLEN/8, x12, x1, x4) + +inst_82: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x39b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0f3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0b4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b9b; op2val:0x38f3; +op3val:0x78b4; valaddr_reg:x9; val_offset:177*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x9, 177*FLEN/8, x12, x1, x4) + +inst_83: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x39b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0f3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0b4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b9b; op2val:0x38f3; +op3val:0x78b4; valaddr_reg:x9; val_offset:180*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x9, 180*FLEN/8, x12, x1, x4) + +inst_84: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x39b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0f3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0b4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b9b; op2val:0x38f3; +op3val:0x78b4; valaddr_reg:x9; val_offset:183*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x9, 183*FLEN/8, x12, x1, x4) + +inst_85: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x26c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x286 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x13d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x726c; op2val:0x4286; +op3val:0x793d; valaddr_reg:x9; val_offset:186*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x9, 186*FLEN/8, x12, x1, x4) + +inst_86: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x26c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x286 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x13d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x726c; op2val:0x4286; +op3val:0x793d; valaddr_reg:x9; val_offset:189*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x9, 189*FLEN/8, x12, x1, x4) + +inst_87: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x26c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x286 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x13d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x726c; op2val:0x4286; +op3val:0x793d; valaddr_reg:x9; val_offset:192*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x9, 192*FLEN/8, x12, x1, x4) + +inst_88: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x26c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x286 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x13d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x726c; op2val:0x4286; +op3val:0x793d; valaddr_reg:x9; val_offset:195*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x9, 195*FLEN/8, x12, x1, x4) + +inst_89: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x26c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x286 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x13d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x726c; op2val:0x4286; +op3val:0x793d; valaddr_reg:x9; val_offset:198*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x9, 198*FLEN/8, x12, x1, x4) + +inst_90: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c3 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x12d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x375 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c3; op2val:0x412d; +op3val:0x7b75; valaddr_reg:x9; val_offset:201*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x9, 201*FLEN/8, x12, x1, x4) + +inst_91: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c3 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x12d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x375 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c3; op2val:0x412d; +op3val:0x7b75; valaddr_reg:x9; val_offset:204*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x9, 204*FLEN/8, x12, x1, x4) + +inst_92: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c3 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x12d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x375 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c3; op2val:0x412d; +op3val:0x7b75; valaddr_reg:x9; val_offset:207*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x9, 207*FLEN/8, x12, x1, x4) + +inst_93: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c3 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x12d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x375 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c3; op2val:0x412d; +op3val:0x7b75; valaddr_reg:x9; val_offset:210*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x9, 210*FLEN/8, x12, x1, x4) + +inst_94: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c3 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x12d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x375 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c3; op2val:0x412d; +op3val:0x7b75; valaddr_reg:x9; val_offset:213*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x9, 213*FLEN/8, x12, x1, x4) + +inst_95: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x345 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x086 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x01d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b45; op2val:0x3886; +op3val:0x781d; valaddr_reg:x9; val_offset:216*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x9, 216*FLEN/8, x12, x1, x4) + +inst_96: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x345 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x086 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x01d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b45; op2val:0x3886; +op3val:0x781d; valaddr_reg:x9; val_offset:219*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x9, 219*FLEN/8, x12, x1, x4) + +inst_97: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x345 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x086 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x01d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b45; op2val:0x3886; +op3val:0x781d; valaddr_reg:x9; val_offset:222*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x9, 222*FLEN/8, x12, x1, x4) + +inst_98: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x345 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x086 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x01d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b45; op2val:0x3886; +op3val:0x781d; valaddr_reg:x9; val_offset:225*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x9, 225*FLEN/8, x12, x1, x4) + +inst_99: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x345 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x086 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x01d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b45; op2val:0x3886; +op3val:0x781d; valaddr_reg:x9; val_offset:228*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x9, 228*FLEN/8, x12, x1, x4) + +inst_100: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x127 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x054 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x194 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7927; op2val:0x3c54; +op3val:0x7994; valaddr_reg:x9; val_offset:231*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x9, 231*FLEN/8, x12, x1, x4) + +inst_101: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x127 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x054 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x194 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7927; op2val:0x3c54; +op3val:0x7994; valaddr_reg:x9; val_offset:234*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x9, 234*FLEN/8, x12, x1, x4) + +inst_102: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x127 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x054 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x194 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7927; op2val:0x3c54; +op3val:0x7994; valaddr_reg:x9; val_offset:237*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x9, 237*FLEN/8, x12, x1, x4) + +inst_103: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x127 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x054 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x194 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7927; op2val:0x3c54; +op3val:0x7994; valaddr_reg:x9; val_offset:240*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x9, 240*FLEN/8, x12, x1, x4) + +inst_104: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x127 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x054 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x194 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7927; op2val:0x3c54; +op3val:0x7994; valaddr_reg:x9; val_offset:243*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x9, 243*FLEN/8, x12, x1, x4) + +inst_105: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x270 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0d9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ce and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a70; op2val:0x3cd9; +op3val:0x7bce; valaddr_reg:x9; val_offset:246*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x9, 246*FLEN/8, x12, x1, x4) + +inst_106: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x270 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0d9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ce and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a70; op2val:0x3cd9; +op3val:0x7bce; valaddr_reg:x9; val_offset:249*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x9, 249*FLEN/8, x12, x1, x4) + +inst_107: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x270 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0d9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ce and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a70; op2val:0x3cd9; +op3val:0x7bce; valaddr_reg:x9; val_offset:252*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x9, 252*FLEN/8, x12, x1, x4) + +inst_108: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x270 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0d9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ce and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a70; op2val:0x3cd9; +op3val:0x7bce; valaddr_reg:x9; val_offset:255*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x9, 255*FLEN/8, x12, x1, x4) + +inst_109: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x270 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0d9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ce and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a70; op2val:0x3cd9; +op3val:0x7bce; valaddr_reg:x9; val_offset:258*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x9, 258*FLEN/8, x12, x1, x4) + +inst_110: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x346 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x25a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1c7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6746; op2val:0x4a5a; +op3val:0x75c7; valaddr_reg:x9; val_offset:261*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x9, 261*FLEN/8, x12, x1, x4) + +inst_111: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x346 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x25a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1c7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6746; op2val:0x4a5a; +op3val:0x75c7; valaddr_reg:x9; val_offset:264*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x9, 264*FLEN/8, x12, x1, x4) + +inst_112: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x346 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x25a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1c7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6746; op2val:0x4a5a; +op3val:0x75c7; valaddr_reg:x9; val_offset:267*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x9, 267*FLEN/8, x12, x1, x4) + +inst_113: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x346 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x25a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1c7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6746; op2val:0x4a5a; +op3val:0x75c7; valaddr_reg:x9; val_offset:270*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x9, 270*FLEN/8, x12, x1, x4) + +inst_114: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x346 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x25a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1c7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6746; op2val:0x4a5a; +op3val:0x75c7; valaddr_reg:x9; val_offset:273*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x9, 273*FLEN/8, x12, x1, x4) + +inst_115: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0cf and fs2 == 0 and fe2 == 0x0e and fm2 == 0x00b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0dd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78cf; op2val:0x380b; +op3val:0x74dd; valaddr_reg:x9; val_offset:276*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x9, 276*FLEN/8, x12, x1, x4) + +inst_116: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0cf and fs2 == 0 and fe2 == 0x0e and fm2 == 0x00b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0dd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78cf; op2val:0x380b; +op3val:0x74dd; valaddr_reg:x9; val_offset:279*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x9, 279*FLEN/8, x12, x1, x4) + +inst_117: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0cf and fs2 == 0 and fe2 == 0x0e and fm2 == 0x00b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0dd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78cf; op2val:0x380b; +op3val:0x74dd; valaddr_reg:x9; val_offset:282*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x9, 282*FLEN/8, x12, x1, x4) + +inst_118: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0cf and fs2 == 0 and fe2 == 0x0e and fm2 == 0x00b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0dd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78cf; op2val:0x380b; +op3val:0x74dd; valaddr_reg:x9; val_offset:285*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x9, 285*FLEN/8, x12, x1, x4) + +inst_119: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0cf and fs2 == 0 and fe2 == 0x0e and fm2 == 0x00b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0dd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78cf; op2val:0x380b; +op3val:0x74dd; valaddr_reg:x9; val_offset:288*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x9, 288*FLEN/8, x12, x1, x4) + +inst_120: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b6 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0df and fs3 == 0 and fe3 == 0x1b and fm3 == 0x1bc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78b6; op2val:0x30df; +op3val:0x6dbc; valaddr_reg:x9; val_offset:291*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x9, 291*FLEN/8, x12, x1, x4) + +inst_121: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b6 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0df and fs3 == 0 and fe3 == 0x1b and fm3 == 0x1bc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78b6; op2val:0x30df; +op3val:0x6dbc; valaddr_reg:x9; val_offset:294*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x9, 294*FLEN/8, x12, x1, x4) + +inst_122: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b6 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0df and fs3 == 0 and fe3 == 0x1b and fm3 == 0x1bc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78b6; op2val:0x30df; +op3val:0x6dbc; valaddr_reg:x9; val_offset:297*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x9, 297*FLEN/8, x12, x1, x4) + +inst_123: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b6 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0df and fs3 == 0 and fe3 == 0x1b and fm3 == 0x1bc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78b6; op2val:0x30df; +op3val:0x6dbc; valaddr_reg:x9; val_offset:300*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x9, 300*FLEN/8, x12, x1, x4) + +inst_124: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b6 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0df and fs3 == 0 and fe3 == 0x1b and fm3 == 0x1bc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78b6; op2val:0x30df; +op3val:0x6dbc; valaddr_reg:x9; val_offset:303*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x9, 303*FLEN/8, x12, x1, x4) + +inst_125: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x309 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0c6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x033 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b09; op2val:0x38c6; +op3val:0x7833; valaddr_reg:x9; val_offset:306*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x9, 306*FLEN/8, x12, x1, x4) + +inst_126: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x309 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0c6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x033 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b09; op2val:0x38c6; +op3val:0x7833; valaddr_reg:x9; val_offset:309*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x9, 309*FLEN/8, x12, x1, x4) + +inst_127: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x309 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0c6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x033 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b09; op2val:0x38c6; +op3val:0x7833; valaddr_reg:x9; val_offset:312*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x9, 312*FLEN/8, x12, x1, x4) + +inst_128: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x309 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0c6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x033 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b09; op2val:0x38c6; +op3val:0x7833; valaddr_reg:x9; val_offset:315*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x9, 315*FLEN/8, x12, x1, x4) + +inst_129: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x309 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0c6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x033 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b09; op2val:0x38c6; +op3val:0x7833; valaddr_reg:x9; val_offset:318*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x9, 318*FLEN/8, x12, x1, x4) + +inst_130: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x379 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1ac and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f79; op2val:0x45ac; +op3val:0x794c; valaddr_reg:x9; val_offset:321*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x9, 321*FLEN/8, x12, x1, x4) + +inst_131: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x379 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1ac and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f79; op2val:0x45ac; +op3val:0x794c; valaddr_reg:x9; val_offset:324*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x9, 324*FLEN/8, x12, x1, x4) + +inst_132: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x379 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1ac and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f79; op2val:0x45ac; +op3val:0x794c; valaddr_reg:x9; val_offset:327*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x9, 327*FLEN/8, x12, x1, x4) + +inst_133: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x379 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1ac and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f79; op2val:0x45ac; +op3val:0x794c; valaddr_reg:x9; val_offset:330*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x9, 330*FLEN/8, x12, x1, x4) + +inst_134: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x379 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1ac and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f79; op2val:0x45ac; +op3val:0x794c; valaddr_reg:x9; val_offset:333*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x9, 333*FLEN/8, x12, x1, x4) + +inst_135: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0fe and fs2 == 0 and fe2 == 0x0e and fm2 == 0x106 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x246 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74fe; op2val:0x3906; +op3val:0x7246; valaddr_reg:x9; val_offset:336*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x9, 336*FLEN/8, x12, x1, x4) + +inst_136: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0fe and fs2 == 0 and fe2 == 0x0e and fm2 == 0x106 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x246 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74fe; op2val:0x3906; +op3val:0x7246; valaddr_reg:x9; val_offset:339*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x9, 339*FLEN/8, x12, x1, x4) + +inst_137: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0fe and fs2 == 0 and fe2 == 0x0e and fm2 == 0x106 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x246 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74fe; op2val:0x3906; +op3val:0x7246; valaddr_reg:x9; val_offset:342*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x9, 342*FLEN/8, x12, x1, x4) + +inst_138: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0fe and fs2 == 0 and fe2 == 0x0e and fm2 == 0x106 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x246 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74fe; op2val:0x3906; +op3val:0x7246; valaddr_reg:x9; val_offset:345*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x9, 345*FLEN/8, x12, x1, x4) + +inst_139: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0fe and fs2 == 0 and fe2 == 0x0e and fm2 == 0x106 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x246 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74fe; op2val:0x3906; +op3val:0x7246; valaddr_reg:x9; val_offset:348*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x9, 348*FLEN/8, x12, x1, x4) + +inst_140: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3bc and fs2 == 0 and fe2 == 0x0d and fm2 == 0x091 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x06a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77bc; op2val:0x3491; +op3val:0x706a; valaddr_reg:x9; val_offset:351*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x9, 351*FLEN/8, x12, x1, x4) + +inst_141: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3bc and fs2 == 0 and fe2 == 0x0d and fm2 == 0x091 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x06a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77bc; op2val:0x3491; +op3val:0x706a; valaddr_reg:x9; val_offset:354*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x9, 354*FLEN/8, x12, x1, x4) + +inst_142: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3bc and fs2 == 0 and fe2 == 0x0d and fm2 == 0x091 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x06a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77bc; op2val:0x3491; +op3val:0x706a; valaddr_reg:x9; val_offset:357*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x9, 357*FLEN/8, x12, x1, x4) + +inst_143: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3bc and fs2 == 0 and fe2 == 0x0d and fm2 == 0x091 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x06a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77bc; op2val:0x3491; +op3val:0x706a; valaddr_reg:x9; val_offset:360*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x9, 360*FLEN/8, x12, x1, x4) + +inst_144: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3bc and fs2 == 0 and fe2 == 0x0d and fm2 == 0x091 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x06a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77bc; op2val:0x3491; +op3val:0x706a; valaddr_reg:x9; val_offset:363*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x9, 363*FLEN/8, x12, x1, x4) + +inst_145: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2b6 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x01f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2eb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72b6; op2val:0x441f; +op3val:0x7aeb; valaddr_reg:x9; val_offset:366*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x9, 366*FLEN/8, x12, x1, x4) + +inst_146: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2b6 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x01f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2eb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72b6; op2val:0x441f; +op3val:0x7aeb; valaddr_reg:x9; val_offset:369*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x9, 369*FLEN/8, x12, x1, x4) + +inst_147: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2b6 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x01f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2eb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72b6; op2val:0x441f; +op3val:0x7aeb; valaddr_reg:x9; val_offset:372*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x9, 372*FLEN/8, x12, x1, x4) + +inst_148: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2b6 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x01f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2eb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72b6; op2val:0x441f; +op3val:0x7aeb; valaddr_reg:x9; val_offset:375*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x9, 375*FLEN/8, x12, x1, x4) + +inst_149: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2b6 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x01f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2eb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72b6; op2val:0x441f; +op3val:0x7aeb; valaddr_reg:x9; val_offset:378*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x9, 378*FLEN/8, x12, x1, x4) + +inst_150: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x195 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x098 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x26a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7995; op2val:0x2498; +op3val:0x626a; valaddr_reg:x9; val_offset:381*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x9, 381*FLEN/8, x12, x1, x4) + +inst_151: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x195 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x098 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x26a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7995; op2val:0x2498; +op3val:0x626a; valaddr_reg:x9; val_offset:384*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x9, 384*FLEN/8, x12, x1, x4) + +inst_152: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x195 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x098 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x26a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7995; op2val:0x2498; +op3val:0x626a; valaddr_reg:x9; val_offset:387*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x9, 387*FLEN/8, x12, x1, x4) + +inst_153: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x195 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x098 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x26a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7995; op2val:0x2498; +op3val:0x626a; valaddr_reg:x9; val_offset:390*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x9, 390*FLEN/8, x12, x1, x4) + +inst_154: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x195 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x098 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x26a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7995; op2val:0x2498; +op3val:0x626a; valaddr_reg:x9; val_offset:393*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x9, 393*FLEN/8, x12, x1, x4) + +inst_155: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x238 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x19e and fs3 == 0 and fe3 == 0x19 and fm3 == 0x05e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a38; op2val:0x259e; +op3val:0x645e; valaddr_reg:x9; val_offset:396*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x9, 396*FLEN/8, x12, x1, x4) + +inst_156: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x238 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x19e and fs3 == 0 and fe3 == 0x19 and fm3 == 0x05e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a38; op2val:0x259e; +op3val:0x645e; valaddr_reg:x9; val_offset:399*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x9, 399*FLEN/8, x12, x1, x4) + +inst_157: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x238 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x19e and fs3 == 0 and fe3 == 0x19 and fm3 == 0x05e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a38; op2val:0x259e; +op3val:0x645e; valaddr_reg:x9; val_offset:402*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x9, 402*FLEN/8, x12, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_158: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x238 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x19e and fs3 == 0 and fe3 == 0x19 and fm3 == 0x05e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a38; op2val:0x259e; +op3val:0x645e; valaddr_reg:x9; val_offset:405*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x9, 405*FLEN/8, x12, x1, x4) + +inst_159: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x238 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x19e and fs3 == 0 and fe3 == 0x19 and fm3 == 0x05e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a38; op2val:0x259e; +op3val:0x645e; valaddr_reg:x9; val_offset:408*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x9, 408*FLEN/8, x12, x1, x4) + +inst_160: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x152 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x16e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x33b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7552; op2val:0x416e; +op3val:0x7b3b; valaddr_reg:x9; val_offset:411*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x9, 411*FLEN/8, x12, x1, x4) + +inst_161: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x152 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x16e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x33b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7552; op2val:0x416e; +op3val:0x7b3b; valaddr_reg:x9; val_offset:414*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x9, 414*FLEN/8, x12, x1, x4) + +inst_162: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x152 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x16e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x33b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7552; op2val:0x416e; +op3val:0x7b3b; valaddr_reg:x9; val_offset:417*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x9, 417*FLEN/8, x12, x1, x4) + +inst_163: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x152 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x16e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x33b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7552; op2val:0x416e; +op3val:0x7b3b; valaddr_reg:x9; val_offset:420*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x9, 420*FLEN/8, x12, x1, x4) + +inst_164: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x152 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x16e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x33b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7552; op2val:0x416e; +op3val:0x7b3b; valaddr_reg:x9; val_offset:423*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x9, 423*FLEN/8, x12, x1, x4) + +inst_165: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0f5 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3e5 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0e5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78f5; op2val:0x37e5; +op3val:0x74e5; valaddr_reg:x9; val_offset:426*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x9, 426*FLEN/8, x12, x1, x4) + +inst_166: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0f5 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3e5 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0e5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78f5; op2val:0x37e5; +op3val:0x74e5; valaddr_reg:x9; val_offset:429*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x9, 429*FLEN/8, x12, x1, x4) + +inst_167: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0f5 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3e5 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0e5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78f5; op2val:0x37e5; +op3val:0x74e5; valaddr_reg:x9; val_offset:432*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x9, 432*FLEN/8, x12, x1, x4) + +inst_168: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0f5 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3e5 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0e5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78f5; op2val:0x37e5; +op3val:0x74e5; valaddr_reg:x9; val_offset:435*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x9, 435*FLEN/8, x12, x1, x4) + +inst_169: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0f5 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3e5 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0e5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78f5; op2val:0x37e5; +op3val:0x74e5; valaddr_reg:x9; val_offset:438*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x9, 438*FLEN/8, x12, x1, x4) + +inst_170: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x209 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x01f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x239 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7609; op2val:0x3c1f; +op3val:0x7639; valaddr_reg:x9; val_offset:441*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x9, 441*FLEN/8, x12, x1, x4) + +inst_171: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x209 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x01f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x239 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7609; op2val:0x3c1f; +op3val:0x7639; valaddr_reg:x9; val_offset:444*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x9, 444*FLEN/8, x12, x1, x4) + +inst_172: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x209 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x01f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x239 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7609; op2val:0x3c1f; +op3val:0x7639; valaddr_reg:x9; val_offset:447*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x9, 447*FLEN/8, x12, x1, x4) + +inst_173: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x209 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x01f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x239 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7609; op2val:0x3c1f; +op3val:0x7639; valaddr_reg:x9; val_offset:450*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x9, 450*FLEN/8, x12, x1, x4) + +inst_174: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x209 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x01f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x239 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7609; op2val:0x3c1f; +op3val:0x7639; valaddr_reg:x9; val_offset:453*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x9, 453*FLEN/8, x12, x1, x4) + +inst_175: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x00e and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x700e; op2val:0x47e1; +op3val:0x7bfe; valaddr_reg:x9; val_offset:456*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x9, 456*FLEN/8, x12, x1, x4) + +inst_176: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x00e and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3fe and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x700e; op2val:0x47e1; +op3val:0x7bfe; valaddr_reg:x9; val_offset:459*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x9, 459*FLEN/8, x12, x1, x4) + +inst_177: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x00e and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3fe and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x700e; op2val:0x47e1; +op3val:0x7bfe; valaddr_reg:x9; val_offset:462*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x9, 462*FLEN/8, x12, x1, x4) + +inst_178: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x00e and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3fe and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x700e; op2val:0x47e1; +op3val:0x7bfe; valaddr_reg:x9; val_offset:465*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x9, 465*FLEN/8, x12, x1, x4) + +inst_179: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x00e and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3fe and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x700e; op2val:0x47e1; +op3val:0x7bfe; valaddr_reg:x9; val_offset:468*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x9, 468*FLEN/8, x12, x1, x4) + +inst_180: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3da and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2c3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ae3; op2val:0x47da; +op3val:0x76c3; valaddr_reg:x9; val_offset:471*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x9, 471*FLEN/8, x12, x1, x4) + +inst_181: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3da and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2c3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ae3; op2val:0x47da; +op3val:0x76c3; valaddr_reg:x9; val_offset:474*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x9, 474*FLEN/8, x12, x1, x4) + +inst_182: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3da and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2c3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ae3; op2val:0x47da; +op3val:0x76c3; valaddr_reg:x9; val_offset:477*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x9, 477*FLEN/8, x12, x1, x4) + +inst_183: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3da and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2c3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ae3; op2val:0x47da; +op3val:0x76c3; valaddr_reg:x9; val_offset:480*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x9, 480*FLEN/8, x12, x1, x4) + +inst_184: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3da and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2c3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ae3; op2val:0x47da; +op3val:0x76c3; valaddr_reg:x9; val_offset:483*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x9, 483*FLEN/8, x12, x1, x4) + +inst_185: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x043 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x25c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f7; op2val:0x3843; +op3val:0x765c; valaddr_reg:x9; val_offset:486*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x9, 486*FLEN/8, x12, x1, x4) + +inst_186: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x043 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x25c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f7; op2val:0x3843; +op3val:0x765c; valaddr_reg:x9; val_offset:489*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x9, 489*FLEN/8, x12, x1, x4) + +inst_187: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x043 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x25c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f7; op2val:0x3843; +op3val:0x765c; valaddr_reg:x9; val_offset:492*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x9, 492*FLEN/8, x12, x1, x4) + +inst_188: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x043 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x25c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f7; op2val:0x3843; +op3val:0x765c; valaddr_reg:x9; val_offset:495*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x9, 495*FLEN/8, x12, x1, x4) + +inst_189: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x043 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x25c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f7; op2val:0x3843; +op3val:0x765c; valaddr_reg:x9; val_offset:498*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x9, 498*FLEN/8, x12, x1, x4) + +inst_190: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d8 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3d8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd8; op2val:0x3400; +op3val:0x73d8; valaddr_reg:x9; val_offset:501*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x9, 501*FLEN/8, x12, x1, x4) + +inst_191: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d8 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3d8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd8; op2val:0x3400; +op3val:0x73d8; valaddr_reg:x9; val_offset:504*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x9, 504*FLEN/8, x12, x1, x4) + +inst_192: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d8 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3d8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd8; op2val:0x3400; +op3val:0x73d8; valaddr_reg:x9; val_offset:507*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x9, 507*FLEN/8, x12, x1, x4) + +inst_193: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d8 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3d8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd8; op2val:0x3400; +op3val:0x73d8; valaddr_reg:x9; val_offset:510*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x9, 510*FLEN/8, x12, x1, x4) + +inst_194: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d8 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3d8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd8; op2val:0x3400; +op3val:0x73d8; valaddr_reg:x9; val_offset:513*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x9, 513*FLEN/8, x12, x1, x4) + +inst_195: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d4 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x34a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x322 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd4; op2val:0x3b4a; +op3val:0x7b22; valaddr_reg:x9; val_offset:516*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x9, 516*FLEN/8, x12, x1, x4) + +inst_196: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d4 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x34a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x322 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd4; op2val:0x3b4a; +op3val:0x7b22; valaddr_reg:x9; val_offset:519*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x9, 519*FLEN/8, x12, x1, x4) + +inst_197: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d4 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x34a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x322 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd4; op2val:0x3b4a; +op3val:0x7b22; valaddr_reg:x9; val_offset:522*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x9, 522*FLEN/8, x12, x1, x4) + +inst_198: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d4 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x34a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x322 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd4; op2val:0x3b4a; +op3val:0x7b22; valaddr_reg:x9; val_offset:525*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x9, 525*FLEN/8, x12, x1, x4) + +inst_199: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d4 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x34a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x322 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd4; op2val:0x3b4a; +op3val:0x7b22; valaddr_reg:x9; val_offset:528*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x9, 528*FLEN/8, x12, x1, x4) + +inst_200: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x14f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x31c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x795b; op2val:0x3d4f; +op3val:0x7b1c; valaddr_reg:x9; val_offset:531*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x9, 531*FLEN/8, x12, x1, x4) + +inst_201: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x14f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x31c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x795b; op2val:0x3d4f; +op3val:0x7b1c; valaddr_reg:x9; val_offset:534*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x9, 534*FLEN/8, x12, x1, x4) + +inst_202: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x14f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x31c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x795b; op2val:0x3d4f; +op3val:0x7b1c; valaddr_reg:x9; val_offset:537*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x9, 537*FLEN/8, x12, x1, x4) + +inst_203: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x14f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x31c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x795b; op2val:0x3d4f; +op3val:0x7b1c; valaddr_reg:x9; val_offset:540*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x9, 540*FLEN/8, x12, x1, x4) + +inst_204: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x14f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x31c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x795b; op2val:0x3d4f; +op3val:0x7b1c; valaddr_reg:x9; val_offset:543*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x9, 543*FLEN/8, x12, x1, x4) + +inst_205: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x326 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x36f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7726; op2val:0x3f6f; +op3val:0x7aa5; valaddr_reg:x9; val_offset:546*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x9, 546*FLEN/8, x12, x1, x4) + +inst_206: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x326 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x36f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7726; op2val:0x3f6f; +op3val:0x7aa5; valaddr_reg:x9; val_offset:549*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x9, 549*FLEN/8, x12, x1, x4) + +inst_207: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x326 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x36f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7726; op2val:0x3f6f; +op3val:0x7aa5; valaddr_reg:x9; val_offset:552*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x9, 552*FLEN/8, x12, x1, x4) + +inst_208: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x326 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x36f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7726; op2val:0x3f6f; +op3val:0x7aa5; valaddr_reg:x9; val_offset:555*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x9, 555*FLEN/8, x12, x1, x4) + +inst_209: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x326 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x36f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7726; op2val:0x3f6f; +op3val:0x7aa5; valaddr_reg:x9; val_offset:558*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x9, 558*FLEN/8, x12, x1, x4) + +inst_210: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x131 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x021 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5d; op2val:0x3931; +op3val:0x7821; valaddr_reg:x9; val_offset:561*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x9, 561*FLEN/8, x12, x1, x4) + +inst_211: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x131 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x021 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5d; op2val:0x3931; +op3val:0x7821; valaddr_reg:x9; val_offset:564*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x9, 564*FLEN/8, x12, x1, x4) + +inst_212: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x131 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x021 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5d; op2val:0x3931; +op3val:0x7821; valaddr_reg:x9; val_offset:567*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x9, 567*FLEN/8, x12, x1, x4) + +inst_213: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x131 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x021 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5d; op2val:0x3931; +op3val:0x7821; valaddr_reg:x9; val_offset:570*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x9, 570*FLEN/8, x12, x1, x4) + +inst_214: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x131 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x021 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5d; op2val:0x3931; +op3val:0x7821; valaddr_reg:x9; val_offset:573*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x9, 573*FLEN/8, x12, x1, x4) + +inst_215: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x388 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7788; op2val:0x3dfe; +op3val:0x79a4; valaddr_reg:x9; val_offset:576*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x9, 576*FLEN/8, x12, x1, x4) + +inst_216: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x388 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7788; op2val:0x3dfe; +op3val:0x79a4; valaddr_reg:x9; val_offset:579*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x9, 579*FLEN/8, x12, x1, x4) + +inst_217: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x388 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7788; op2val:0x3dfe; +op3val:0x79a4; valaddr_reg:x9; val_offset:582*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x9, 582*FLEN/8, x12, x1, x4) + +inst_218: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x388 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7788; op2val:0x3dfe; +op3val:0x79a4; valaddr_reg:x9; val_offset:585*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x9, 585*FLEN/8, x12, x1, x4) + +inst_219: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x388 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7788; op2val:0x3dfe; +op3val:0x79a4; valaddr_reg:x9; val_offset:588*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x9, 588*FLEN/8, x12, x1, x4) + +inst_220: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x257 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x024 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x292 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a57; op2val:0x3c24; +op3val:0x7a92; valaddr_reg:x9; val_offset:591*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x9, 591*FLEN/8, x12, x1, x4) + +inst_221: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x257 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x024 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x292 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a57; op2val:0x3c24; +op3val:0x7a92; valaddr_reg:x9; val_offset:594*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x9, 594*FLEN/8, x12, x1, x4) + +inst_222: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x257 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x024 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x292 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a57; op2val:0x3c24; +op3val:0x7a92; valaddr_reg:x9; val_offset:597*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x9, 597*FLEN/8, x12, x1, x4) + +inst_223: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3c1 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x050 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x02f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77c1; op2val:0x3850; +op3val:0x742f; valaddr_reg:x9; val_offset:600*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x9, 600*FLEN/8, x12, x1, x4) + +inst_224: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3c1 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x050 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x02f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77c1; op2val:0x3850; +op3val:0x742f; valaddr_reg:x9; val_offset:603*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x9, 603*FLEN/8, x12, x1, x4) + +inst_225: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3c1 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x050 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x02f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77c1; op2val:0x3850; +op3val:0x742f; valaddr_reg:x9; val_offset:606*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x9, 606*FLEN/8, x12, x1, x4) + +inst_226: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3c1 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x050 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x02f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77c1; op2val:0x3850; +op3val:0x742f; valaddr_reg:x9; val_offset:609*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x9, 609*FLEN/8, x12, x1, x4) + +inst_227: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x18b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4fa5; op2val:0x658b; +op3val:0x794c; valaddr_reg:x9; val_offset:612*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x9, 612*FLEN/8, x12, x1, x4) + +inst_228: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1f7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x020 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x228 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75f7; op2val:0x4020; +op3val:0x7a28; valaddr_reg:x9; val_offset:615*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x9, 615*FLEN/8, x12, x1, x4) + +inst_229: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x05c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x269 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x745c; op2val:0x41e1; +op3val:0x7a69; valaddr_reg:x9; val_offset:618*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x9, 618*FLEN/8, x12, x1, x4) + +inst_230: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x05c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x269 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x745c; op2val:0x41e1; +op3val:0x7a69; valaddr_reg:x9; val_offset:621*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x9, 621*FLEN/8, x12, x1, x4) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(31319,32,FLEN) +NAN_BOXED(15396,32,FLEN) +NAN_BOXED(31319,32,FLEN) +NAN_BOXED(31319,32,FLEN) +NAN_BOXED(15396,32,FLEN) +NAN_BOXED(15396,32,FLEN) +NAN_BOXED(31319,32,FLEN) +NAN_BOXED(15396,32,FLEN) +NAN_BOXED(31378,32,FLEN) +NAN_BOXED(31319,32,FLEN) +NAN_BOXED(15396,32,FLEN) +NAN_BOXED(31378,32,FLEN) +NAN_BOXED(31319,32,FLEN) +NAN_BOXED(15396,32,FLEN) +NAN_BOXED(31319,32,FLEN) +NAN_BOXED(30657,32,FLEN) +NAN_BOXED(30657,32,FLEN) +NAN_BOXED(30657,32,FLEN) +NAN_BOXED(30657,32,FLEN) +NAN_BOXED(30657,32,FLEN) +NAN_BOXED(29743,32,FLEN) +NAN_BOXED(30657,32,FLEN) +NAN_BOXED(14416,32,FLEN) +NAN_BOXED(14416,32,FLEN) +NAN_BOXED(30657,32,FLEN) +NAN_BOXED(14416,32,FLEN) +NAN_BOXED(29743,32,FLEN) +NAN_BOXED(30657,32,FLEN) +NAN_BOXED(30657,32,FLEN) +NAN_BOXED(30657,32,FLEN) +NAN_BOXED(20389,32,FLEN) +NAN_BOXED(25995,32,FLEN) +NAN_BOXED(31052,32,FLEN) +NAN_BOXED(20389,32,FLEN) +NAN_BOXED(20389,32,FLEN) +NAN_BOXED(0,32,FLEN) +test_dataset_1: +NAN_BOXED(20389,32,FLEN) +NAN_BOXED(25995,32,FLEN) +NAN_BOXED(31052,32,FLEN) +NAN_BOXED(20389,32,FLEN) +NAN_BOXED(25995,32,FLEN) +NAN_BOXED(31052,32,FLEN) +NAN_BOXED(20389,32,FLEN) +NAN_BOXED(25995,32,FLEN) +NAN_BOXED(31052,32,FLEN) +NAN_BOXED(30597,32,FLEN) +NAN_BOXED(15990,32,FLEN) +NAN_BOXED(31251,32,FLEN) +NAN_BOXED(30597,32,FLEN) +NAN_BOXED(15990,32,FLEN) +NAN_BOXED(31251,32,FLEN) +NAN_BOXED(30597,32,FLEN) +NAN_BOXED(15990,32,FLEN) +NAN_BOXED(31251,32,FLEN) +NAN_BOXED(30597,32,FLEN) +NAN_BOXED(15990,32,FLEN) +NAN_BOXED(31251,32,FLEN) +NAN_BOXED(30597,32,FLEN) +NAN_BOXED(15990,32,FLEN) +NAN_BOXED(31251,32,FLEN) +NAN_BOXED(30199,32,FLEN) +NAN_BOXED(16416,32,FLEN) +NAN_BOXED(31272,32,FLEN) +NAN_BOXED(30199,32,FLEN) +NAN_BOXED(16416,32,FLEN) +NAN_BOXED(31272,32,FLEN) +NAN_BOXED(30199,32,FLEN) +NAN_BOXED(16416,32,FLEN) +NAN_BOXED(31272,32,FLEN) +test_dataset_2: +NAN_BOXED(30199,16,FLEN) +NAN_BOXED(16416,16,FLEN) +NAN_BOXED(31272,16,FLEN) +NAN_BOXED(30199,16,FLEN) +NAN_BOXED(16416,16,FLEN) +NAN_BOXED(31272,16,FLEN) +NAN_BOXED(29788,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31337,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(16865,16,FLEN) +NAN_BOXED(31337,16,FLEN) +NAN_BOXED(29788,16,FLEN) +NAN_BOXED(16865,16,FLEN) +NAN_BOXED(31337,16,FLEN) +NAN_BOXED(29788,16,FLEN) +NAN_BOXED(16865,16,FLEN) +NAN_BOXED(31337,16,FLEN) +NAN_BOXED(29788,16,FLEN) +NAN_BOXED(16865,16,FLEN) +NAN_BOXED(31337,16,FLEN) +NAN_BOXED(31189,16,FLEN) +NAN_BOXED(14473,16,FLEN) +NAN_BOXED(30366,16,FLEN) +NAN_BOXED(31189,16,FLEN) +NAN_BOXED(14473,16,FLEN) +NAN_BOXED(30366,16,FLEN) +NAN_BOXED(31189,16,FLEN) +NAN_BOXED(14473,16,FLEN) +NAN_BOXED(30366,16,FLEN) +NAN_BOXED(31189,16,FLEN) +NAN_BOXED(14473,16,FLEN) +NAN_BOXED(30366,16,FLEN) +NAN_BOXED(31189,16,FLEN) +NAN_BOXED(14473,16,FLEN) +NAN_BOXED(30366,16,FLEN) +NAN_BOXED(30797,16,FLEN) +NAN_BOXED(15633,16,FLEN) +NAN_BOXED(31092,16,FLEN) +NAN_BOXED(30797,16,FLEN) +NAN_BOXED(15633,16,FLEN) +NAN_BOXED(31092,16,FLEN) +NAN_BOXED(30797,16,FLEN) +NAN_BOXED(15633,16,FLEN) +NAN_BOXED(31092,16,FLEN) +NAN_BOXED(30797,16,FLEN) +NAN_BOXED(15633,16,FLEN) +NAN_BOXED(31092,16,FLEN) +NAN_BOXED(30797,16,FLEN) +NAN_BOXED(15633,16,FLEN) +NAN_BOXED(31092,16,FLEN) +NAN_BOXED(29228,16,FLEN) +NAN_BOXED(16828,16,FLEN) +NAN_BOXED(30829,16,FLEN) +NAN_BOXED(29228,16,FLEN) +NAN_BOXED(16828,16,FLEN) +NAN_BOXED(30829,16,FLEN) +NAN_BOXED(29228,16,FLEN) +NAN_BOXED(16828,16,FLEN) +NAN_BOXED(30829,16,FLEN) +NAN_BOXED(29228,16,FLEN) +NAN_BOXED(16828,16,FLEN) +NAN_BOXED(30829,16,FLEN) +NAN_BOXED(29228,16,FLEN) +NAN_BOXED(16828,16,FLEN) +NAN_BOXED(30829,16,FLEN) +NAN_BOXED(31344,16,FLEN) +NAN_BOXED(13638,16,FLEN) +NAN_BOXED(29759,16,FLEN) +NAN_BOXED(31344,16,FLEN) +NAN_BOXED(13638,16,FLEN) +NAN_BOXED(29759,16,FLEN) +NAN_BOXED(31344,16,FLEN) +NAN_BOXED(13638,16,FLEN) +NAN_BOXED(29759,16,FLEN) +NAN_BOXED(31344,16,FLEN) +NAN_BOXED(13638,16,FLEN) +NAN_BOXED(29759,16,FLEN) +NAN_BOXED(31344,16,FLEN) +NAN_BOXED(13638,16,FLEN) +NAN_BOXED(29759,16,FLEN) +NAN_BOXED(31340,16,FLEN) +NAN_BOXED(15060,16,FLEN) +NAN_BOXED(31099,16,FLEN) +NAN_BOXED(31340,16,FLEN) +NAN_BOXED(15060,16,FLEN) +NAN_BOXED(31099,16,FLEN) +NAN_BOXED(31340,16,FLEN) +NAN_BOXED(15060,16,FLEN) +NAN_BOXED(31099,16,FLEN) +NAN_BOXED(31340,16,FLEN) +NAN_BOXED(15060,16,FLEN) +NAN_BOXED(31099,16,FLEN) +NAN_BOXED(31340,16,FLEN) +NAN_BOXED(15060,16,FLEN) +NAN_BOXED(31099,16,FLEN) +NAN_BOXED(31424,16,FLEN) +NAN_BOXED(13916,16,FLEN) +NAN_BOXED(30045,16,FLEN) +NAN_BOXED(31424,16,FLEN) +NAN_BOXED(13916,16,FLEN) +NAN_BOXED(30045,16,FLEN) +NAN_BOXED(31424,16,FLEN) +NAN_BOXED(13916,16,FLEN) +NAN_BOXED(30045,16,FLEN) +NAN_BOXED(31424,16,FLEN) +NAN_BOXED(13916,16,FLEN) +NAN_BOXED(30045,16,FLEN) +NAN_BOXED(31424,16,FLEN) +NAN_BOXED(13916,16,FLEN) +NAN_BOXED(30045,16,FLEN) +NAN_BOXED(28149,16,FLEN) +NAN_BOXED(18507,16,FLEN) +NAN_BOXED(31334,16,FLEN) +NAN_BOXED(28149,16,FLEN) +NAN_BOXED(18507,16,FLEN) +NAN_BOXED(31334,16,FLEN) +NAN_BOXED(28149,16,FLEN) +NAN_BOXED(18507,16,FLEN) +NAN_BOXED(31334,16,FLEN) +NAN_BOXED(28149,16,FLEN) +NAN_BOXED(18507,16,FLEN) +NAN_BOXED(31334,16,FLEN) +NAN_BOXED(28149,16,FLEN) +NAN_BOXED(18507,16,FLEN) +NAN_BOXED(31334,16,FLEN) +NAN_BOXED(31343,16,FLEN) +NAN_BOXED(14444,16,FLEN) +NAN_BOXED(30494,16,FLEN) +NAN_BOXED(31343,16,FLEN) +NAN_BOXED(14444,16,FLEN) +NAN_BOXED(30494,16,FLEN) +NAN_BOXED(31343,16,FLEN) +NAN_BOXED(14444,16,FLEN) +NAN_BOXED(30494,16,FLEN) +NAN_BOXED(31343,16,FLEN) +NAN_BOXED(14444,16,FLEN) +NAN_BOXED(30494,16,FLEN) +NAN_BOXED(31343,16,FLEN) +NAN_BOXED(14444,16,FLEN) +NAN_BOXED(30494,16,FLEN) +NAN_BOXED(28159,16,FLEN) +NAN_BOXED(16436,16,FLEN) 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.fill 146*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fnmadd_b6-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fnmadd_b6-01.S new file mode 100644 index 000000000..6ed534e63 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fnmadd_b6-01.S @@ -0,0 +1,474 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 06:03:37 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fnmadd.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fnmadd.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fnmadd_b6 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fnmadd_b6) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x5,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==x4, rs2==x20, rs3==x4, rd==x11,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x4; op2:x20; op3:x4; dest:x11; op1val:0x0; op2val:0x7bff; +op3val:0x0; valaddr_reg:x5; val_offset:0*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x11, x4, x20, x4, dyn, 0, 0, x5, 0*FLEN/8, x6, x1, x9) + +inst_1: +// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==x3, rs2==x21, rs3==x21, rd==x8,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x3; op2:x21; op3:x21; dest:x8; op1val:0x0; op2val:0x7bff; +op3val:0x7bff; valaddr_reg:x5; val_offset:3*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x8, x3, x21, x21, dyn, 32, 0, x5, 3*FLEN/8, x6, x1, x9) + +inst_2: +// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==x26, rs2==x28, rs3==x12, rd==x18,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x26; op2:x28; op3:x12; dest:x18; op1val:0x0; op2val:0x7bff; +op3val:0x0; valaddr_reg:x5; val_offset:6*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x18, x26, x28, x12, dyn, 64, 0, x5, 6*FLEN/8, x6, x1, x9) + +inst_3: +// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==x7, rs2==x31, rs3==x26, rd==x31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x7; op2:x31; op3:x26; dest:x31; op1val:0x0; op2val:0x7bff; +op3val:0x0; valaddr_reg:x5; val_offset:9*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x7, x31, x26, dyn, 96, 0, x5, 9*FLEN/8, x6, x1, x9) + +inst_4: +// rs1 == rd == rs3 != rs2, rs1==x22, rs2==x16, rs3==x22, rd==x22,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x22; op2:x16; op3:x22; dest:x22; op1val:0x0; op2val:0x7bff; +op3val:0x0; valaddr_reg:x5; val_offset:12*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x22, x22, x16, x22, dyn, 128, 0, x5, 12*FLEN/8, x6, x1, x9) + +inst_5: +// rs1 == rs2 == rs3 != rd, rs1==x14, rs2==x14, rs3==x14, rd==x24,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x14; op2:x14; op3:x14; dest:x24; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x5; val_offset:15*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x24, x14, x14, x14, dyn, 0, 0, x5, 15*FLEN/8, x6, x1, x9) + +inst_6: +// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==x19, rs2==x19, rs3==x9, rd==x14,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x19; op2:x19; op3:x9; dest:x14; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x5; val_offset:18*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x14, x19, x19, x9, dyn, 32, 0, x5, 18*FLEN/8, x6, x1, x9) + +inst_7: +// rd == rs2 == rs3 != rs1, rs1==x29, rs2==x2, rs3==x2, rd==x2,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x29; op2:x2; op3:x2; dest:x2; op1val:0x0; op2val:0xfbff; +op3val:0xfbff; valaddr_reg:x5; val_offset:21*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x2, x29, x2, x2, dyn, 64, 0, x5, 21*FLEN/8, x6, x1, x9) + +inst_8: +// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==x25, rs2==x22, rs3==x15, rd==x25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x25; op2:x22; op3:x15; dest:x25; op1val:0x0; op2val:0xfbff; +op3val:0x0; valaddr_reg:x5; val_offset:24*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x25, x25, x22, x15, dyn, 96, 0, x5, 24*FLEN/8, x6, x1, x9) + +inst_9: +// rs1 == rs2 == rs3 == rd, rs1==x30, rs2==x30, rs3==x30, rd==x30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x30; op3:x30; dest:x30; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x5; val_offset:27*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x30, x30, x30, x30, dyn, 128, 0, x5, 27*FLEN/8, x6, x1, x9) + +inst_10: +// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==x10, rs2==x13, rs3==x20, rd==x20, +/* opcode: fnmadd.h ; op1:x10; op2:x13; op3:x20; dest:x20; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x5; val_offset:30*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x20, x10, x13, x20, dyn, 0, 0, x5, 30*FLEN/8, x6, x1, x9) +RVTEST_VALBASEUPD(x11,test_dataset_1) + +inst_11: +// rs1 == rs2 == rd != rs3, rs1==x15, rs2==x15, rs3==x29, rd==x15, +/* opcode: fnmadd.h ; op1:x15; op2:x15; op3:x29; dest:x15; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x11; val_offset:0*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x15, x15, x15, x29, dyn, 0, 0, x11, 0*FLEN/8, x16, x1, x9) + +inst_12: +// rs1==x20, rs2==x26, rs3==x24, rd==x3, +/* opcode: fnmadd.h ; op1:x20; op2:x26; op3:x24; dest:x3; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x11; val_offset:3*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x3, x20, x26, x24, dyn, 0, 0, x11, 3*FLEN/8, x16, x1, x9) + +inst_13: +// rs1==x6, rs2==x7, rs3==x28, rd==x5, +/* opcode: fnmadd.h ; op1:x6; op2:x7; op3:x28; dest:x5; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x11; val_offset:6*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x5, x6, x7, x28, dyn, 0, 0, x11, 6*FLEN/8, x16, x1, x9) +RVTEST_SIGBASE(x13,signature_x13_0) + +inst_14: +// rs1==x27, rs2==x29, rs3==x23, rd==x0, +/* opcode: fnmadd.h ; op1:x27; op2:x29; op3:x23; dest:x0; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x11; val_offset:9*FLEN/8; rmval:dyn; +testreg:x14; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x0, x27, x29, x23, dyn, 0, 0, x11, 9*FLEN/8, x16, x13, x14) + +inst_15: +// rs1==x5, rs2==x3, rs3==x17, rd==x4, +/* opcode: fnmadd.h ; op1:x5; op2:x3; op3:x17; dest:x4; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x11; val_offset:12*FLEN/8; rmval:dyn; +testreg:x14; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x4, x5, x3, x17, dyn, 0, 0, x11, 12*FLEN/8, x16, x13, x14) + +inst_16: +// rs1==x23, rs2==x8, rs3==x7, rd==x1, +/* opcode: fnmadd.h ; op1:x23; op2:x8; op3:x7; dest:x1; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x11; val_offset:15*FLEN/8; rmval:dyn; +testreg:x14; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x1, x23, x8, x7, dyn, 0, 0, x11, 15*FLEN/8, x16, x13, x14) + +inst_17: +// rs1==x1, rs2==x12, rs3==x10, rd==x9, +/* opcode: fnmadd.h ; op1:x1; op2:x12; op3:x10; dest:x9; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x11; val_offset:18*FLEN/8; rmval:dyn; +testreg:x14; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x9, x1, x12, x10, dyn, 0, 0, x11, 18*FLEN/8, x16, x13, x14) + +inst_18: +// rs1==x2, rs2==x0, rs3==x16, rd==x21, +/* opcode: fnmadd.h ; op1:x2; op2:x0; op3:x16; dest:x21; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x11; val_offset:21*FLEN/8; rmval:dyn; +testreg:x14; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x21, x2, x0, x16, dyn, 0, 0, x11, 21*FLEN/8, x16, x13, x14) + +inst_19: +// rs1==x18, rs2==x1, rs3==x31, rd==x12, +/* opcode: fnmadd.h ; op1:x18; op2:x1; op3:x31; dest:x12; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x11; val_offset:24*FLEN/8; rmval:dyn; +testreg:x14; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x12, x18, x1, x31, dyn, 0, 0, x11, 24*FLEN/8, x16, x13, x14) + +inst_20: +// rs1==x21, rs2==x24, rs3==x11, rd==x6, +/* opcode: fnmadd.h ; op1:x21; op2:x24; op3:x11; dest:x6; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x11; val_offset:27*FLEN/8; rmval:dyn; +testreg:x14; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x6, x21, x24, x11, dyn, 0, 0, x11, 27*FLEN/8, x16, x13, x14) + +inst_21: +// rs1==x28, rs2==x17, rs3==x19, rd==x7, +/* opcode: fnmadd.h ; op1:x28; op2:x17; op3:x19; dest:x7; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x11; val_offset:30*FLEN/8; rmval:dyn; +testreg:x14; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x7, x28, x17, x19, dyn, 0, 0, x11, 30*FLEN/8, x16, x13, x14) + +inst_22: +// rs1==x12, rs2==x23, rs3==x8, rd==x27, +/* opcode: fnmadd.h ; op1:x12; op2:x23; op3:x8; dest:x27; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x11; val_offset:33*FLEN/8; rmval:dyn; +testreg:x14; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x27, x12, x23, x8, dyn, 0, 0, x11, 33*FLEN/8, x16, x13, x14) + +inst_23: +// rs1==x31, rs2==x4, rs3==x6, rd==x10, +/* opcode: fnmadd.h ; op1:x31; op2:x4; op3:x6; dest:x10; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x11; val_offset:36*FLEN/8; rmval:dyn; +testreg:x14; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x10, x31, x4, x6, dyn, 0, 0, x11, 36*FLEN/8, x16, x13, x14) +RVTEST_VALBASEUPD(x3,test_dataset_2) + +inst_24: +// rs1==x17, rs2==x25, rs3==x1, rd==x26, +/* opcode: fnmadd.h ; op1:x17; op2:x25; op3:x1; dest:x26; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn; +testreg:x14; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x26, x17, x25, x1, dyn, 0, 0, x3, 0*FLEN/8, x4, x13, x14) + +inst_25: +// rs1==x11, rs2==x6, rs3==x25, rd==x16, +/* opcode: fnmadd.h ; op1:x11; op2:x6; op3:x25; dest:x16; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x3; val_offset:3*FLEN/8; rmval:dyn; +testreg:x14; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x16, x11, x6, x25, dyn, 0, 0, x3, 3*FLEN/8, x4, x13, x14) + +inst_26: +// rs1==x0, rs2==x18, rs3==x13, rd==x17, +/* opcode: fnmadd.h ; op1:x0; op2:x18; op3:x13; dest:x17; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x17, x0, x18, x13, dyn, 0, 0, x3, 6*FLEN/8, x4, x13, x2) + +inst_27: +// rs1==x9, rs2==x10, rs3==x3, rd==x23, +/* opcode: fnmadd.h ; op1:x9; op2:x10; op3:x3; dest:x23; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x3; val_offset:9*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x23, x9, x10, x3, dyn, 0, 0, x3, 9*FLEN/8, x4, x13, x2) + +inst_28: +// rs1==x8, rs2==x5, rs3==x27, rd==x19, +/* opcode: fnmadd.h ; op1:x8; op2:x5; op3:x27; dest:x19; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x19, x8, x5, x27, dyn, 0, 0, x3, 12*FLEN/8, x4, x13, x2) +RVTEST_SIGBASE(x1,signature_x1_2) + +inst_29: +// rs1==x24, rs2==x27, rs3==x18, rd==x29, +/* opcode: fnmadd.h ; op1:x24; op2:x27; op3:x18; dest:x29; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x3; val_offset:15*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x29, x24, x27, x18, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==x13, rs2==x9, rs3==x5, rd==x28, +/* opcode: fnmadd.h ; op1:x13; op2:x9; op3:x5; dest:x28; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x28, x13, x9, x5, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==x16, rs2==x11, rs3==x0, rd==x13, +/* opcode: fnmadd.h ; op1:x16; op2:x11; op3:x0; dest:x13; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x3; val_offset:21*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x13, x16, x11, x0, dyn, 0, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_32: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7bff; +op3val:0x0; valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_33: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfbff; +op3val:0x0; valaddr_reg:x3; val_offset:27*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_34: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfbff; +op3val:0x0; valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_35: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfbff; +op3val:0x0; valaddr_reg:x3; val_offset:33*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x3, 33*FLEN/8, x4, x1, x2) + +inst_36: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfbff; +op3val:0x0; valaddr_reg:x3; val_offset:36*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x3, 36*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(64511,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +test_dataset_1: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +test_dataset_2: +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(0,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x13_0: + .fill 30*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_2: + .fill 16*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fnmadd_b7-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fnmadd_b7-01.S new file mode 100644 index 000000000..7d519ec4c --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fnmadd_b7-01.S @@ -0,0 +1,786 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 06:03:37 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fnmadd.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fnmadd.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fnmadd_b7 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fnmadd_b7) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x2,test_dataset_0) +RVTEST_SIGBASE(x8,signature_x8_1) + +inst_0: +// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==x16, rs2==x4, rs3==x16, rd==x23,fs1 == 0 and fe1 == 0x1e and fm1 == 0x257 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x024 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x292 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x16; op2:x4; op3:x16; dest:x23; op1val:0x7a57; op2val:0x3c24; +op3val:0x7a57; valaddr_reg:x2; val_offset:0*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x23, x16, x4, x16, dyn, 96, 0, x2, 0*FLEN/8, x7, x8, x6) + +inst_1: +// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==x22, rs2==x26, rs3==x26, rd==x15,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3c1 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x050 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x02f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x22; op2:x26; op3:x26; dest:x15; op1val:0x77c1; op2val:0x3850; +op3val:0x3850; valaddr_reg:x2; val_offset:3*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x15, x22, x26, x26, dyn, 96, 0, x2, 3*FLEN/8, x7, x8, x6) + +inst_2: +// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==x4, rs2==x20, rs3==x17, rd==x29,fs1 == 0 and fe1 == 0x13 and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x18b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x4; op2:x20; op3:x17; dest:x29; op1val:0x4fa5; op2val:0x658b; +op3val:0x794c; valaddr_reg:x2; val_offset:6*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x29, x4, x20, x17, dyn, 96, 0, x2, 6*FLEN/8, x7, x8, x6) + +inst_3: +// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==x0, rs2==x1, rs3==x8, rd==x1,fs1 == 0 and fe1 == 0x1d and fm1 == 0x385 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x276 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x213 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x0; op2:x1; op3:x8; dest:x1; op1val:0x0; op2val:0x3e76; +op3val:0x7a13; valaddr_reg:x2; val_offset:9*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x1, x0, x1, x8, dyn, 96, 0, x2, 9*FLEN/8, x7, x8, x6) + +inst_4: +// rs1 == rd == rs3 != rs2, rs1==x13, rs2==x12, rs3==x13, rd==x13,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1f7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x020 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x228 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x13; op2:x12; op3:x13; dest:x13; op1val:0x75f7; op2val:0x4020; +op3val:0x75f7; valaddr_reg:x2; val_offset:12*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x13, x13, x12, x13, dyn, 96, 0, x2, 12*FLEN/8, x7, x8, x6) + +inst_5: +// rs1 == rs2 == rs3 != rd, rs1==x30, rs2==x30, rs3==x30, rd==x19,fs1 == 0 and fe1 == 0x1d and fm1 == 0x05c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x269 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x30; op3:x30; dest:x19; op1val:0x745c; op2val:0x745c; +op3val:0x745c; valaddr_reg:x2; val_offset:15*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x19, x30, x30, x30, dyn, 96, 0, x2, 15*FLEN/8, x7, x8, x6) + +inst_6: +// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==x25, rs2==x25, rs3==x12, rd==x27,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x089 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x29e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x25; op2:x25; op3:x12; dest:x27; op1val:0x79d5; op2val:0x79d5; +op3val:0x769e; valaddr_reg:x2; val_offset:18*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x27, x25, x25, x12, dyn, 96, 0, x2, 18*FLEN/8, x7, x8, x6) + +inst_7: +// rd == rs2 == rs3 != rs1, rs1==x11, rs2==x18, rs3==x18, rd==x18,fs1 == 0 and fe1 == 0x1e and fm1 == 0x04d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x111 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x174 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x11; op2:x18; op3:x18; dest:x18; op1val:0x784d; op2val:0x3d11; +op3val:0x3d11; valaddr_reg:x2; val_offset:21*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x18, x11, x18, x18, dyn, 96, 0, x2, 21*FLEN/8, x7, x8, x6) + +inst_8: +// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==x3, rs2==x10, rs3==x4, rd==x3,fs1 == 0 and fe1 == 0x1c and fm1 == 0x22c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1bc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x06d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x3; op2:x10; op3:x4; dest:x3; op1val:0x722c; op2val:0x41bc; +op3val:0x786d; valaddr_reg:x2; val_offset:24*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x3, x3, x10, x4, dyn, 96, 0, x2, 24*FLEN/8, x7, x8, x6) + +inst_9: +// rs1 == rs2 == rs3 == rd, rs1==x21, rs2==x21, rs3==x21, rd==x21,fs1 == 0 and fe1 == 0x1e and fm1 == 0x270 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x146 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x03f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x21; op2:x21; op3:x21; dest:x21; op1val:0x7a70; op2val:0x7a70; +op3val:0x7a70; valaddr_reg:x2; val_offset:27*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x21, x21, x21, x21, dyn, 96, 0, x2, 27*FLEN/8, x7, x8, x6) + +inst_10: +// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==x28, rs2==x5, rs3==x24, rd==x24,fs1 == 0 and fe1 == 0x1e and fm1 == 0x26c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x17b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x28; op2:x5; op3:x24; dest:x24; op1val:0x7a6c; op2val:0x3ad4; +op3val:0x797b; valaddr_reg:x2; val_offset:30*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x24, x28, x5, x24, dyn, 96, 0, x2, 30*FLEN/8, x7, x8, x6) +RVTEST_VALBASEUPD(x18,test_dataset_1) + +inst_11: +// rs1 == rs2 == rd != rs3, rs1==x2, rs2==x2, rs3==x1, rd==x2,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x25c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x15d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x2; op2:x2; op3:x1; dest:x2; op1val:0x7ac0; op2val:0x7ac0; +op3val:0x755d; valaddr_reg:x18; val_offset:0*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x2, x2, x2, x1, dyn, 96, 0, x18, 0*FLEN/8, x20, x8, x6) + +inst_12: +// rs1==x6, rs2==x7, rs3==x19, rd==x16,fs1 == 0 and fe1 == 0x1b and fm1 == 0x1f5 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x04b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x266 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x6; op2:x7; op3:x19; dest:x16; op1val:0x6df5; op2val:0x484b; +op3val:0x7a66; valaddr_reg:x18; val_offset:3*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x16, x6, x7, x19, dyn, 96, 0, x18, 3*FLEN/8, x20, x8, x10) +RVTEST_SIGBASE(x2,signature_x2_0) + +inst_13: +// rs1==x9, rs2==x3, rs3==x11, rd==x12,fs1 == 0 and fe1 == 0x1e and fm1 == 0x26f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x06c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x31e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x9; op2:x3; op3:x11; dest:x12; op1val:0x7a6f; op2val:0x386c; +op3val:0x771e; valaddr_reg:x18; val_offset:6*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x12, x9, x3, x11, dyn, 96, 0, x18, 6*FLEN/8, x20, x2, x10) + +inst_14: +// rs1==x8, rs2==x16, rs3==x14, rd==x22,fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x10 and fm2 == 0x034 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x24e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x8; op2:x16; op3:x14; dest:x22; op1val:0x6dff; op2val:0x4034; +op3val:0x724e; valaddr_reg:x18; val_offset:9*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x22, x8, x16, x14, dyn, 96, 0, x18, 9*FLEN/8, x20, x2, x10) + +inst_15: +// rs1==x1, rs2==x29, rs3==x23, rd==x8,fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x356 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x1; op2:x29; op3:x23; dest:x8; op1val:0x7913; op2val:0x3756; +op3val:0x74a8; valaddr_reg:x18; val_offset:12*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x8, x1, x29, x23, dyn, 96, 0, x18, 12*FLEN/8, x20, x2, x10) + +inst_16: +// rs1==x14, rs2==x8, rs3==x5, rd==x11,fs1 == 0 and fe1 == 0x1e and fm1 == 0x39b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0f3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0b4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x14; op2:x8; op3:x5; dest:x11; op1val:0x7b9b; op2val:0x38f3; +op3val:0x78b4; valaddr_reg:x18; val_offset:15*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x11, x14, x8, x5, dyn, 96, 0, x18, 15*FLEN/8, x20, x2, x10) + +inst_17: +// rs1==x7, rs2==x13, rs3==x10, rd==x5,fs1 == 0 and fe1 == 0x1c and fm1 == 0x26c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x286 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x13d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x7; op2:x13; op3:x10; dest:x5; op1val:0x726c; op2val:0x4286; +op3val:0x793d; valaddr_reg:x18; val_offset:18*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x5, x7, x13, x10, dyn, 96, 0, x18, 18*FLEN/8, x20, x2, x10) + +inst_18: +// rs1==x19, rs2==x23, rs3==x6, rd==x0,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c3 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x12d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x375 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x19; op2:x23; op3:x6; dest:x0; op1val:0x75c3; op2val:0x412d; +op3val:0x7b75; valaddr_reg:x18; val_offset:21*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x0, x19, x23, x6, dyn, 96, 0, x18, 21*FLEN/8, x20, x2, x10) + +inst_19: +// rs1==x12, rs2==x9, rs3==x27, rd==x31,fs1 == 0 and fe1 == 0x1e and fm1 == 0x345 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x086 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x01d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x12; op2:x9; op3:x27; dest:x31; op1val:0x7b45; op2val:0x3886; +op3val:0x781d; valaddr_reg:x18; val_offset:24*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x12, x9, x27, dyn, 96, 0, x18, 24*FLEN/8, x20, x2, x10) + +inst_20: +// rs1==x29, rs2==x15, rs3==x28, rd==x4,fs1 == 0 and fe1 == 0x1e and fm1 == 0x127 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x054 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x194 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x29; op2:x15; op3:x28; dest:x4; op1val:0x7927; op2val:0x3c54; +op3val:0x7994; valaddr_reg:x18; val_offset:27*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x4, x29, x15, x28, dyn, 96, 0, x18, 27*FLEN/8, x20, x2, x10) + +inst_21: +// rs1==x17, rs2==x6, rs3==x9, rd==x14,fs1 == 0 and fe1 == 0x1e and fm1 == 0x270 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0d9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ce and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x17; op2:x6; op3:x9; dest:x14; op1val:0x7a70; op2val:0x3cd9; +op3val:0x7bce; valaddr_reg:x18; val_offset:30*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x14, x17, x6, x9, dyn, 96, 0, x18, 30*FLEN/8, x20, x2, x10) + +inst_22: +// rs1==x31, rs2==x24, rs3==x29, rd==x26,fs1 == 0 and fe1 == 0x19 and fm1 == 0x346 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x25a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1c7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x31; op2:x24; op3:x29; dest:x26; op1val:0x6746; op2val:0x4a5a; +op3val:0x75c7; valaddr_reg:x18; val_offset:33*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x26, x31, x24, x29, dyn, 96, 0, x18, 33*FLEN/8, x20, x2, x10) +RVTEST_VALBASEUPD(x4,test_dataset_2) + +inst_23: +// rs1==x18, rs2==x28, rs3==x15, rd==x7,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0cf and fs2 == 0 and fe2 == 0x0e and fm2 == 0x00b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0dd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x18; op2:x28; op3:x15; dest:x7; op1val:0x78cf; op2val:0x380b; +op3val:0x74dd; valaddr_reg:x4; val_offset:0*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x7, x18, x28, x15, dyn, 96, 0, x4, 0*FLEN/8, x8, x2, x10) + +inst_24: +// rs1==x15, rs2==x19, rs3==x0, rd==x28,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b6 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0df and fs3 == 0 and fe3 == 0x1b and fm3 == 0x1bc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x15; op2:x19; op3:x0; dest:x28; op1val:0x78b6; op2val:0x30df; +op3val:0x0; valaddr_reg:x4; val_offset:3*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x28, x15, x19, x0, dyn, 96, 0, x4, 3*FLEN/8, x8, x2, x3) + +inst_25: +// rs1==x24, rs2==x31, rs3==x25, rd==x6,fs1 == 0 and fe1 == 0x1e and fm1 == 0x309 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0c6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x033 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x24; op2:x31; op3:x25; dest:x6; op1val:0x7b09; op2val:0x38c6; +op3val:0x7833; valaddr_reg:x4; val_offset:6*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x6, x24, x31, x25, dyn, 96, 0, x4, 6*FLEN/8, x8, x2, x3) + +inst_26: +// rs1==x23, rs2==x14, rs3==x22, rd==x30,fs1 == 0 and fe1 == 0x1b and fm1 == 0x379 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1ac and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x23; op2:x14; op3:x22; dest:x30; op1val:0x6f79; op2val:0x45ac; +op3val:0x794c; valaddr_reg:x4; val_offset:9*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x30, x23, x14, x22, dyn, 96, 0, x4, 9*FLEN/8, x8, x2, x3) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_27: +// rs1==x10, rs2==x17, rs3==x3, rd==x9,fs1 == 0 and fe1 == 0x1d and fm1 == 0x0fe and fs2 == 0 and fe2 == 0x0e and fm2 == 0x106 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x246 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x10; op2:x17; op3:x3; dest:x9; op1val:0x74fe; op2val:0x3906; +op3val:0x7246; valaddr_reg:x4; val_offset:12*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x9, x10, x17, x3, dyn, 96, 0, x4, 12*FLEN/8, x8, x1, x3) + +inst_28: +// rs1==x26, rs2==x27, rs3==x2, rd==x20,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3bc and fs2 == 0 and fe2 == 0x0d and fm2 == 0x091 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x06a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x26; op2:x27; op3:x2; dest:x20; op1val:0x77bc; op2val:0x3491; +op3val:0x706a; valaddr_reg:x4; val_offset:15*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x20, x26, x27, x2, dyn, 96, 0, x4, 15*FLEN/8, x8, x1, x3) + +inst_29: +// rs1==x20, rs2==x22, rs3==x7, rd==x17,fs1 == 0 and fe1 == 0x1c and fm1 == 0x2b6 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x01f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2eb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x20; op2:x22; op3:x7; dest:x17; op1val:0x72b6; op2val:0x441f; +op3val:0x7aeb; valaddr_reg:x4; val_offset:18*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x17, x20, x22, x7, dyn, 96, 0, x4, 18*FLEN/8, x8, x1, x3) + +inst_30: +// rs1==x5, rs2==x11, rs3==x31, rd==x25,fs1 == 0 and fe1 == 0x1e and fm1 == 0x195 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x098 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x26a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x5; op2:x11; op3:x31; dest:x25; op1val:0x7995; op2val:0x2498; +op3val:0x626a; valaddr_reg:x4; val_offset:21*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x25, x5, x11, x31, dyn, 96, 0, x4, 21*FLEN/8, x8, x1, x3) +RVTEST_VALBASEUPD(x2,test_dataset_3) + +inst_31: +// rs1==x27, rs2==x0, rs3==x20, rd==x10,fs1 == 0 and fe1 == 0x1e and fm1 == 0x238 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x19e and fs3 == 0 and fe3 == 0x19 and fm3 == 0x05e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x27; op2:x0; op3:x20; dest:x10; op1val:0x7a38; op2val:0x0; +op3val:0x645e; valaddr_reg:x2; val_offset:0*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x10, x27, x0, x20, dyn, 96, 0, x2, 0*FLEN/8, x4, x1, x3) + +inst_32: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x152 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x16e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x33b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7552; op2val:0x416e; +op3val:0x7b3b; valaddr_reg:x2; val_offset:3*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 3*FLEN/8, x4, x1, x3) + +inst_33: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0f5 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3e5 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0e5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78f5; op2val:0x37e5; +op3val:0x74e5; valaddr_reg:x2; val_offset:6*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 6*FLEN/8, x4, x1, x3) + +inst_34: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x209 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x01f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x239 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7609; op2val:0x3c1f; +op3val:0x7639; valaddr_reg:x2; val_offset:9*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 9*FLEN/8, x4, x1, x3) + +inst_35: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x00e and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3fe and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x700e; op2val:0x47e1; +op3val:0x7bfe; valaddr_reg:x2; val_offset:12*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 12*FLEN/8, x4, x1, x3) + +inst_36: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3da and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2c3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ae3; op2val:0x47da; +op3val:0x76c3; valaddr_reg:x2; val_offset:15*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 15*FLEN/8, x4, x1, x3) + +inst_37: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x043 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x25c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f7; op2val:0x3843; +op3val:0x765c; valaddr_reg:x2; val_offset:18*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 18*FLEN/8, x4, x1, x3) + +inst_38: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d8 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3d8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd8; op2val:0x3400; +op3val:0x73d8; valaddr_reg:x2; val_offset:21*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 21*FLEN/8, x4, x1, x3) + +inst_39: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d4 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x34a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x322 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd4; op2val:0x3b4a; +op3val:0x7b22; valaddr_reg:x2; val_offset:24*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 24*FLEN/8, x4, x1, x3) + +inst_40: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x14f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x31c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x795b; op2val:0x3d4f; +op3val:0x7b1c; valaddr_reg:x2; val_offset:27*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 27*FLEN/8, x4, x1, x3) + +inst_41: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x326 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x36f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7726; op2val:0x3f6f; +op3val:0x7aa5; valaddr_reg:x2; val_offset:30*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 30*FLEN/8, x4, x1, x3) + +inst_42: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x12e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x021 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5d; op2val:0x392e; +op3val:0x7821; valaddr_reg:x2; val_offset:33*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 33*FLEN/8, x4, x1, x3) + +inst_43: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x388 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1fc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7788; op2val:0x3dfc; +op3val:0x79a4; valaddr_reg:x2; val_offset:36*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 36*FLEN/8, x4, x1, x3) + +inst_44: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x28a and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2a5 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x17f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x768a; op2val:0x32a5; +op3val:0x6d7f; valaddr_reg:x2; val_offset:39*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 39*FLEN/8, x4, x1, x3) + +inst_45: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f8 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1ad and fs3 == 0 and fe3 == 0x1d and fm3 == 0x040 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f8; op2val:0x35ad; +op3val:0x7440; valaddr_reg:x2; val_offset:42*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 42*FLEN/8, x4, x1, x3) + +inst_46: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3cc and fs2 == 0 and fe2 == 0x0f and fm2 == 0x26c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x244 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77cc; op2val:0x3e6c; +op3val:0x7a44; valaddr_reg:x2; val_offset:45*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 45*FLEN/8, x4, x1, x3) + +inst_47: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x181 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3c6 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x199 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7181; op2val:0x2fc6; +op3val:0x6599; valaddr_reg:x2; val_offset:48*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 48*FLEN/8, x4, x1, x3) + +inst_48: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3e6 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0c3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0b6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6fe6; op2val:0x44c3; +op3val:0x78b6; valaddr_reg:x2; val_offset:51*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 51*FLEN/8, x4, x1, x3) + +inst_49: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1ad and fs3 == 0 and fe3 == 0x1d and fm3 == 0x019 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c6; op2val:0x39ad; +op3val:0x7419; valaddr_reg:x2; val_offset:54*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 54*FLEN/8, x4, x1, x3) + +inst_50: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x338 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x01b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x36a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7738; op2val:0x401b; +op3val:0x7b6a; valaddr_reg:x2; val_offset:57*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 57*FLEN/8, x4, x1, x3) + +inst_51: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x013 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x272 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x290 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7413; op2val:0x3e72; +op3val:0x7690; valaddr_reg:x2; val_offset:60*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 60*FLEN/8, x4, x1, x3) + +inst_52: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x307 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x191 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0e5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b07; op2val:0x3991; +op3val:0x78e5; valaddr_reg:x2; val_offset:63*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 63*FLEN/8, x4, x1, x3) + +inst_53: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x048 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x316 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x397 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7448; op2val:0x3f16; +op3val:0x7797; valaddr_reg:x2; val_offset:66*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 66*FLEN/8, x4, x1, x3) + +inst_54: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a7 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0c1 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x08c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77a7; op2val:0x34c1; +op3val:0x708c; valaddr_reg:x2; val_offset:69*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 69*FLEN/8, x4, x1, x3) + +inst_55: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x209 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x27a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0e3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7609; op2val:0x3a7a; +op3val:0x74e3; valaddr_reg:x2; val_offset:72*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 72*FLEN/8, x4, x1, x3) + +inst_56: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x257 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x024 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x292 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a57; op2val:0x3c24; +op3val:0x7a92; valaddr_reg:x2; val_offset:75*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 75*FLEN/8, x4, x1, x3) + +inst_57: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3c1 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x050 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x02f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77c1; op2val:0x3850; +op3val:0x742f; valaddr_reg:x2; val_offset:78*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 78*FLEN/8, x4, x1, x3) + +inst_58: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x385 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x276 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x213 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7785; op2val:0x3e76; +op3val:0x7a13; valaddr_reg:x2; val_offset:81*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 81*FLEN/8, x4, x1, x3) + +inst_59: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1f7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x020 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x228 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75f7; op2val:0x4020; +op3val:0x7a28; valaddr_reg:x2; val_offset:84*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 84*FLEN/8, x4, x1, x3) + +inst_60: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x05c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x269 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x745c; op2val:0x41e1; +op3val:0x7a69; valaddr_reg:x2; val_offset:87*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 87*FLEN/8, x4, x1, x3) + +inst_61: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x089 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x29e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79d5; op2val:0x3889; +op3val:0x769e; valaddr_reg:x2; val_offset:90*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 90*FLEN/8, x4, x1, x3) + +inst_62: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x111 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x174 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x784d; op2val:0x3d11; +op3val:0x7974; valaddr_reg:x2; val_offset:93*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 93*FLEN/8, x4, x1, x3) + +inst_63: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x270 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x146 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x03f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a70; op2val:0x3546; +op3val:0x743f; valaddr_reg:x2; val_offset:96*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 96*FLEN/8, x4, x1, x3) + +inst_64: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x25c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x15d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ac0; op2val:0x365c; +op3val:0x755d; valaddr_reg:x2; val_offset:99*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 99*FLEN/8, x4, x1, x3) + +inst_65: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c3 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x12d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x375 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c3; op2val:0x412d; +op3val:0x7b75; valaddr_reg:x2; val_offset:102*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 102*FLEN/8, x4, x1, x3) + +inst_66: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b6 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0df and fs3 == 0 and fe3 == 0x1b and fm3 == 0x1bc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78b6; op2val:0x30df; +op3val:0x6dbc; valaddr_reg:x2; val_offset:105*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 105*FLEN/8, x4, x1, x3) + +inst_67: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x238 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x19e and fs3 == 0 and fe3 == 0x19 and fm3 == 0x05e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a38; op2val:0x259e; +op3val:0x645e; valaddr_reg:x2; val_offset:108*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x2, 108*FLEN/8, x4, x1, x3) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(31319,32,FLEN) +NAN_BOXED(15396,32,FLEN) +NAN_BOXED(31319,32,FLEN) +NAN_BOXED(30657,32,FLEN) +NAN_BOXED(14416,32,FLEN) +NAN_BOXED(14416,32,FLEN) +NAN_BOXED(20389,32,FLEN) +NAN_BOXED(25995,32,FLEN) +NAN_BOXED(31052,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(15990,32,FLEN) +NAN_BOXED(31251,32,FLEN) +NAN_BOXED(30199,32,FLEN) +NAN_BOXED(16416,32,FLEN) +NAN_BOXED(30199,32,FLEN) +NAN_BOXED(29788,32,FLEN) +NAN_BOXED(29788,32,FLEN) +NAN_BOXED(29788,32,FLEN) +NAN_BOXED(31189,32,FLEN) +NAN_BOXED(31189,32,FLEN) +NAN_BOXED(30366,32,FLEN) +NAN_BOXED(30797,32,FLEN) +NAN_BOXED(15633,32,FLEN) +NAN_BOXED(15633,32,FLEN) +NAN_BOXED(29228,32,FLEN) +NAN_BOXED(16828,32,FLEN) +NAN_BOXED(30829,32,FLEN) +NAN_BOXED(31344,32,FLEN) +NAN_BOXED(31344,32,FLEN) +NAN_BOXED(31344,32,FLEN) +NAN_BOXED(31340,32,FLEN) +NAN_BOXED(15060,32,FLEN) +NAN_BOXED(31099,32,FLEN) +test_dataset_1: +NAN_BOXED(31424,32,FLEN) +NAN_BOXED(31424,32,FLEN) +NAN_BOXED(30045,32,FLEN) +NAN_BOXED(28149,32,FLEN) +NAN_BOXED(18507,32,FLEN) +NAN_BOXED(31334,32,FLEN) +NAN_BOXED(31343,32,FLEN) +NAN_BOXED(14444,32,FLEN) +NAN_BOXED(30494,32,FLEN) +NAN_BOXED(28159,32,FLEN) +NAN_BOXED(16436,32,FLEN) +NAN_BOXED(29262,32,FLEN) +NAN_BOXED(30995,32,FLEN) +NAN_BOXED(14166,32,FLEN) +NAN_BOXED(29864,32,FLEN) +NAN_BOXED(31643,32,FLEN) +NAN_BOXED(14579,32,FLEN) +NAN_BOXED(30900,32,FLEN) +NAN_BOXED(29292,32,FLEN) +NAN_BOXED(17030,32,FLEN) +NAN_BOXED(31037,32,FLEN) +NAN_BOXED(30147,32,FLEN) +NAN_BOXED(16685,32,FLEN) +NAN_BOXED(31605,32,FLEN) +NAN_BOXED(31557,32,FLEN) +NAN_BOXED(14470,32,FLEN) +NAN_BOXED(30749,32,FLEN) +NAN_BOXED(31015,32,FLEN) +NAN_BOXED(15444,32,FLEN) +NAN_BOXED(31124,32,FLEN) +NAN_BOXED(31344,32,FLEN) +NAN_BOXED(15577,32,FLEN) +NAN_BOXED(31694,32,FLEN) +NAN_BOXED(26438,32,FLEN) +NAN_BOXED(19034,32,FLEN) +NAN_BOXED(30151,32,FLEN) +test_dataset_2: +NAN_BOXED(30927,32,FLEN) +NAN_BOXED(14347,32,FLEN) +NAN_BOXED(29917,32,FLEN) +NAN_BOXED(30902,32,FLEN) +NAN_BOXED(12511,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31497,32,FLEN) +NAN_BOXED(14534,32,FLEN) +NAN_BOXED(30771,32,FLEN) +NAN_BOXED(28537,32,FLEN) +NAN_BOXED(17836,32,FLEN) +NAN_BOXED(31052,32,FLEN) +NAN_BOXED(29950,32,FLEN) +NAN_BOXED(14598,32,FLEN) +NAN_BOXED(29254,32,FLEN) +NAN_BOXED(30652,32,FLEN) +NAN_BOXED(13457,32,FLEN) +NAN_BOXED(28778,32,FLEN) +NAN_BOXED(29366,32,FLEN) +NAN_BOXED(17439,32,FLEN) +NAN_BOXED(31467,32,FLEN) +NAN_BOXED(31125,32,FLEN) +NAN_BOXED(9368,32,FLEN) +NAN_BOXED(25194,32,FLEN) +test_dataset_3: +NAN_BOXED(31288,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(25694,16,FLEN) +NAN_BOXED(30034,16,FLEN) +NAN_BOXED(16750,16,FLEN) +NAN_BOXED(31547,16,FLEN) +NAN_BOXED(30965,16,FLEN) +NAN_BOXED(14309,16,FLEN) +NAN_BOXED(29925,16,FLEN) +NAN_BOXED(30217,16,FLEN) +NAN_BOXED(15391,16,FLEN) +NAN_BOXED(30265,16,FLEN) +NAN_BOXED(28686,16,FLEN) +NAN_BOXED(18401,16,FLEN) +NAN_BOXED(31742,16,FLEN) +NAN_BOXED(27363,16,FLEN) +NAN_BOXED(18394,16,FLEN) +NAN_BOXED(30403,16,FLEN) +NAN_BOXED(31223,16,FLEN) +NAN_BOXED(14403,16,FLEN) +NAN_BOXED(30300,16,FLEN) +NAN_BOXED(31704,16,FLEN) +NAN_BOXED(13312,16,FLEN) +NAN_BOXED(29656,16,FLEN) +NAN_BOXED(31700,16,FLEN) +NAN_BOXED(15178,16,FLEN) +NAN_BOXED(31522,16,FLEN) +NAN_BOXED(31067,16,FLEN) +NAN_BOXED(15695,16,FLEN) +NAN_BOXED(31516,16,FLEN) +NAN_BOXED(30502,16,FLEN) +NAN_BOXED(16239,16,FLEN) +NAN_BOXED(31397,16,FLEN) +NAN_BOXED(31325,16,FLEN) +NAN_BOXED(14638,16,FLEN) +NAN_BOXED(30753,16,FLEN) +NAN_BOXED(30600,16,FLEN) +NAN_BOXED(15868,16,FLEN) +NAN_BOXED(31140,16,FLEN) +NAN_BOXED(30346,16,FLEN) +NAN_BOXED(12965,16,FLEN) +NAN_BOXED(28031,16,FLEN) +NAN_BOXED(31224,16,FLEN) +NAN_BOXED(13741,16,FLEN) +NAN_BOXED(29760,16,FLEN) +NAN_BOXED(30668,16,FLEN) +NAN_BOXED(15980,16,FLEN) +NAN_BOXED(31300,16,FLEN) +NAN_BOXED(29057,16,FLEN) +NAN_BOXED(12230,16,FLEN) +NAN_BOXED(26009,16,FLEN) +NAN_BOXED(28646,16,FLEN) +NAN_BOXED(17603,16,FLEN) +NAN_BOXED(30902,16,FLEN) +NAN_BOXED(30150,16,FLEN) +NAN_BOXED(14765,16,FLEN) +NAN_BOXED(29721,16,FLEN) +NAN_BOXED(30520,16,FLEN) +NAN_BOXED(16411,16,FLEN) +NAN_BOXED(31594,16,FLEN) +NAN_BOXED(29715,16,FLEN) +NAN_BOXED(15986,16,FLEN) +NAN_BOXED(30352,16,FLEN) +NAN_BOXED(31495,16,FLEN) +NAN_BOXED(14737,16,FLEN) +NAN_BOXED(30949,16,FLEN) +NAN_BOXED(29768,16,FLEN) +NAN_BOXED(16150,16,FLEN) +NAN_BOXED(30615,16,FLEN) +NAN_BOXED(30631,16,FLEN) +NAN_BOXED(13505,16,FLEN) +NAN_BOXED(28812,16,FLEN) +NAN_BOXED(30217,16,FLEN) +NAN_BOXED(14970,16,FLEN) +NAN_BOXED(29923,16,FLEN) +NAN_BOXED(31319,16,FLEN) +NAN_BOXED(15396,16,FLEN) +NAN_BOXED(31378,16,FLEN) +NAN_BOXED(30657,16,FLEN) +NAN_BOXED(14416,16,FLEN) +NAN_BOXED(29743,16,FLEN) +NAN_BOXED(30597,16,FLEN) +NAN_BOXED(15990,16,FLEN) +NAN_BOXED(31251,16,FLEN) +NAN_BOXED(30199,16,FLEN) +NAN_BOXED(16416,16,FLEN) +NAN_BOXED(31272,16,FLEN) +NAN_BOXED(29788,16,FLEN) +NAN_BOXED(16865,16,FLEN) +NAN_BOXED(31337,16,FLEN) +NAN_BOXED(31189,16,FLEN) +NAN_BOXED(14473,16,FLEN) +NAN_BOXED(30366,16,FLEN) +NAN_BOXED(30797,16,FLEN) +NAN_BOXED(15633,16,FLEN) +NAN_BOXED(31092,16,FLEN) +NAN_BOXED(31344,16,FLEN) +NAN_BOXED(13638,16,FLEN) +NAN_BOXED(29759,16,FLEN) +NAN_BOXED(31424,16,FLEN) +NAN_BOXED(13916,16,FLEN) +NAN_BOXED(30045,16,FLEN) +NAN_BOXED(30147,16,FLEN) +NAN_BOXED(16685,16,FLEN) +NAN_BOXED(31605,16,FLEN) +NAN_BOXED(30902,16,FLEN) +NAN_BOXED(12511,16,FLEN) +NAN_BOXED(28092,16,FLEN) +NAN_BOXED(31288,16,FLEN) +NAN_BOXED(9630,16,FLEN) +NAN_BOXED(25694,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x8_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x8_1: + .fill 26*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_0: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_0: + .fill 82*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fnmadd_b8-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fnmadd_b8-01.S new file mode 100644 index 000000000..b549efff8 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fnmadd_b8-01.S @@ -0,0 +1,17084 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 06:03:37 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fnmadd.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fnmadd.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fnmadd_b8 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fnmadd_b8) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x13,test_dataset_0) +RVTEST_SIGBASE(x6,signature_x6_1) + +inst_0: +// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==x25, rs2==x5, rs3==x25, rd==x7,fs1 == 0 and fe1 == 0x0c and fm1 == 0x29c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2e4 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1b2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x25; op2:x5; op3:x25; dest:x7; op1val:0x329c; op2val:0x3ae4; +op3val:0x329c; valaddr_reg:x13; val_offset:0*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x7, x25, x5, x25, dyn, 0, 0, x13, 0*FLEN/8, x16, x6, x10) + +inst_1: +// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==x18, rs2==x19, rs3==x19, rd==x1,fs1 == 0 and fe1 == 0x0c and fm1 == 0x29c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2e4 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1b2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x18; op2:x19; op3:x19; dest:x1; op1val:0x329c; op2val:0x3ae4; +op3val:0x3ae4; valaddr_reg:x13; val_offset:3*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x1, x18, x19, x19, dyn, 32, 0, x13, 3*FLEN/8, x16, x6, x10) + +inst_2: +// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==x3, rs2==x1, rs3==x13, rd==x9,fs1 == 0 and fe1 == 0x0c and fm1 == 0x29c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2e4 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1b2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x3; op2:x1; op3:x13; dest:x9; op1val:0x329c; op2val:0x3ae4; +op3val:0x31b2; valaddr_reg:x13; val_offset:6*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x9, x3, x1, x13, dyn, 64, 0, x13, 6*FLEN/8, x16, x6, x10) + +inst_3: +// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==x2, rs2==x14, rs3==x0, rd==x14,fs1 == 0 and fe1 == 0x0c and fm1 == 0x29c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2e4 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1b2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x2; op2:x14; op3:x0; dest:x14; op1val:0x329c; op2val:0x3ae4; +op3val:0x0; valaddr_reg:x13; val_offset:9*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x14, x2, x14, x0, dyn, 96, 0, x13, 9*FLEN/8, x16, x6, x10) + +inst_4: +// rs1 == rd == rs3 != rs2, rs1==x12, rs2==x3, rs3==x12, rd==x12,fs1 == 0 and fe1 == 0x0c and fm1 == 0x29c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2e4 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1b2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x12; op2:x3; op3:x12; dest:x12; op1val:0x329c; op2val:0x3ae4; +op3val:0x329c; valaddr_reg:x13; val_offset:12*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x12, x12, x3, x12, dyn, 128, 0, x13, 12*FLEN/8, x16, x6, x10) + +inst_5: +// rs1 == rs2 == rs3 != rd, rs1==x11, rs2==x11, rs3==x11, rd==x21,fs1 == 0 and fe1 == 0x0e and fm1 == 0x01e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1bc and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x11; op2:x11; op3:x11; dest:x21; op1val:0x381e; op2val:0x381e; +op3val:0x381e; valaddr_reg:x13; val_offset:15*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x21, x11, x11, x11, dyn, 0, 0, x13, 15*FLEN/8, x16, x6, x10) + +inst_6: +// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==x22, rs2==x22, rs3==x21, rd==x24,fs1 == 0 and fe1 == 0x0e and fm1 == 0x01e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1bc and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x22; op2:x22; op3:x21; dest:x24; op1val:0x381e; op2val:0x381e; +op3val:0x39e8; valaddr_reg:x13; val_offset:18*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x24, x22, x22, x21, dyn, 32, 0, x13, 18*FLEN/8, x16, x6, x10) + +inst_7: +// rd == rs2 == rs3 != rs1, rs1==x9, rs2==x15, rs3==x15, rd==x15,fs1 == 0 and fe1 == 0x0e and fm1 == 0x01e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1bc and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x9; op2:x15; op3:x15; dest:x15; op1val:0x381e; op2val:0x3dbc; +op3val:0x3dbc; valaddr_reg:x13; val_offset:21*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x15, x9, x15, x15, dyn, 64, 0, x13, 21*FLEN/8, x16, x6, x10) + +inst_8: +// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==x26, rs2==x0, rs3==x22, rd==x26,fs1 == 0 and fe1 == 0x0e and fm1 == 0x01e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1bc and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x26; op2:x0; op3:x22; dest:x26; op1val:0x381e; op2val:0x0; +op3val:0x39e8; valaddr_reg:x13; val_offset:24*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x26, x26, x0, x22, dyn, 96, 0, x13, 24*FLEN/8, x16, x6, x10) + +inst_9: +// rs1 == rs2 == rs3 == rd, rs1==x23, rs2==x23, rs3==x23, rd==x23,fs1 == 0 and fe1 == 0x0e and fm1 == 0x01e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1bc and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x23; op2:x23; op3:x23; dest:x23; op1val:0x381e; op2val:0x381e; +op3val:0x381e; valaddr_reg:x13; val_offset:27*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x23, x23, x23, x23, dyn, 128, 0, x13, 27*FLEN/8, x16, x6, x10) + +inst_10: +// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==x20, rs2==x7, rs3==x5, rd==x5,fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0d and fm2 == 0x165 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x165 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x20; op2:x7; op3:x5; dest:x5; op1val:0x3bff; op2val:0x3565; +op3val:0x3565; valaddr_reg:x13; val_offset:30*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x5, x20, x7, x5, dyn, 0, 0, x13, 30*FLEN/8, x16, x6, x10) + +inst_11: +// rs1 == rs2 == rd != rs3, rs1==x28, rs2==x28, rs3==x2, rd==x28,fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0d and fm2 == 0x165 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x165 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x28; op2:x28; op3:x2; dest:x28; op1val:0x3bff; op2val:0x3bff; +op3val:0x3565; valaddr_reg:x13; val_offset:33*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x28, x28, x28, x2, dyn, 32, 0, x13, 33*FLEN/8, x16, x6, x10) + +inst_12: +// rs1==x19, rs2==x8, rs3==x14, rd==x4,fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0d and fm2 == 0x165 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x165 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x19; op2:x8; op3:x14; dest:x4; op1val:0x3bff; op2val:0x3565; +op3val:0x3565; valaddr_reg:x13; val_offset:36*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x4, x19, x8, x14, dyn, 64, 0, x13, 36*FLEN/8, x16, x6, x10) +RVTEST_VALBASEUPD(x11,test_dataset_1) + +inst_13: +// rs1==x30, rs2==x20, rs3==x26, rd==x13,fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0d and fm2 == 0x165 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x165 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x20; op3:x26; dest:x13; op1val:0x3bff; op2val:0x3565; +op3val:0x3565; valaddr_reg:x11; val_offset:0*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x13, x30, x20, x26, dyn, 96, 0, x11, 0*FLEN/8, x15, x6, x10) + +inst_14: +// rs1==x16, rs2==x4, rs3==x10, rd==x30,fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0d and fm2 == 0x165 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x165 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x16; op2:x4; op3:x10; dest:x30; op1val:0x3bff; op2val:0x3565; +op3val:0x3565; valaddr_reg:x11; val_offset:3*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x30, x16, x4, x10, dyn, 128, 0, x11, 3*FLEN/8, x15, x6, x9) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_15: +// rs1==x13, rs2==x26, rs3==x16, rd==x27,fs1 == 0 and fe1 == 0x0e and fm1 == 0x03c and fs2 == 0 and fe2 == 0x0d and fm2 == 0x341 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3b0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x13; op2:x26; op3:x16; dest:x27; op1val:0x383c; op2val:0x3741; +op3val:0x33b0; valaddr_reg:x11; val_offset:6*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x27, x13, x26, x16, dyn, 0, 0, x11, 6*FLEN/8, x15, x1, x9) + +inst_16: +// rs1==x21, rs2==x13, rs3==x28, rd==x10,fs1 == 0 and fe1 == 0x0e and fm1 == 0x03c and fs2 == 0 and fe2 == 0x0d and fm2 == 0x341 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3b0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x21; op2:x13; op3:x28; dest:x10; op1val:0x383c; op2val:0x3741; +op3val:0x33b0; valaddr_reg:x11; val_offset:9*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x10, x21, x13, x28, dyn, 32, 0, x11, 9*FLEN/8, x15, x1, x9) + +inst_17: +// rs1==x5, rs2==x27, rs3==x18, rd==x17,fs1 == 0 and fe1 == 0x0e and fm1 == 0x03c and fs2 == 0 and fe2 == 0x0d and fm2 == 0x341 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3b0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x5; op2:x27; op3:x18; dest:x17; op1val:0x383c; op2val:0x3741; +op3val:0x33b0; valaddr_reg:x11; val_offset:12*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x17, x5, x27, x18, dyn, 64, 0, x11, 12*FLEN/8, x15, x1, x9) + +inst_18: +// rs1==x0, rs2==x12, rs3==x29, rd==x6,fs1 == 0 and fe1 == 0x0e and fm1 == 0x03c and fs2 == 0 and fe2 == 0x0d and fm2 == 0x341 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3b0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x0; op2:x12; op3:x29; dest:x6; op1val:0x0; op2val:0x3741; +op3val:0x33b0; valaddr_reg:x11; val_offset:15*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x6, x0, x12, x29, dyn, 96, 0, x11, 15*FLEN/8, x15, x1, x9) + +inst_19: +// rs1==x6, rs2==x31, rs3==x17, rd==x25,fs1 == 0 and fe1 == 0x0e and fm1 == 0x03c and fs2 == 0 and fe2 == 0x0d and fm2 == 0x341 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3b0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x6; op2:x31; op3:x17; dest:x25; op1val:0x383c; op2val:0x3741; +op3val:0x33b0; valaddr_reg:x11; val_offset:18*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x25, x6, x31, x17, dyn, 128, 0, x11, 18*FLEN/8, x15, x1, x9) + +inst_20: +// rs1==x17, rs2==x6, rs3==x8, rd==x0,fs1 == 0 and fe1 == 0x0e and fm1 == 0x103 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1dd and fs3 == 0 and fe3 == 0x0c and fm3 == 0x35b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x17; op2:x6; op3:x8; dest:x0; op1val:0x3903; op2val:0x35dd; +op3val:0x335b; valaddr_reg:x11; val_offset:21*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x0, x17, x6, x8, dyn, 0, 0, x11, 21*FLEN/8, x15, x1, x9) + +inst_21: +// rs1==x7, rs2==x17, rs3==x9, rd==x29,fs1 == 0 and fe1 == 0x0e and fm1 == 0x103 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1dd and fs3 == 0 and fe3 == 0x0c and fm3 == 0x35b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x7; op2:x17; op3:x9; dest:x29; op1val:0x3903; op2val:0x35dd; +op3val:0x335b; valaddr_reg:x11; val_offset:24*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x29, x7, x17, x9, dyn, 32, 0, x11, 24*FLEN/8, x15, x1, x9) + +inst_22: +// rs1==x14, rs2==x24, rs3==x6, rd==x2,fs1 == 0 and fe1 == 0x0e and fm1 == 0x103 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1dd and fs3 == 0 and fe3 == 0x0c and fm3 == 0x35b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x14; op2:x24; op3:x6; dest:x2; op1val:0x3903; op2val:0x35dd; +op3val:0x335b; valaddr_reg:x11; val_offset:27*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x2, x14, x24, x6, dyn, 64, 0, x11, 27*FLEN/8, x15, x1, x9) + +inst_23: +// rs1==x4, rs2==x2, rs3==x27, rd==x20,fs1 == 0 and fe1 == 0x0e and fm1 == 0x103 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1dd and fs3 == 0 and fe3 == 0x0c and fm3 == 0x35b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x4; op2:x2; op3:x27; dest:x20; op1val:0x3903; op2val:0x35dd; +op3val:0x335b; valaddr_reg:x11; val_offset:30*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x20, x4, x2, x27, dyn, 96, 0, x11, 30*FLEN/8, x15, x1, x9) + +inst_24: +// rs1==x8, rs2==x25, rs3==x30, rd==x3,fs1 == 0 and fe1 == 0x0e and fm1 == 0x103 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1dd and fs3 == 0 and fe3 == 0x0c and fm3 == 0x35b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x8; op2:x25; op3:x30; dest:x3; op1val:0x3903; op2val:0x35dd; +op3val:0x335b; valaddr_reg:x11; val_offset:33*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x3, x8, x25, x30, dyn, 128, 0, x11, 33*FLEN/8, x15, x1, x9) +RVTEST_VALBASEUPD(x4,test_dataset_2) + +inst_25: +// rs1==x27, rs2==x10, rs3==x24, rd==x16,fs1 == 0 and fe1 == 0x0e and fm1 == 0x1d1 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x05b and fs3 == 0 and fe3 == 0x0c and fm3 == 0x256 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x27; op2:x10; op3:x24; dest:x16; op1val:0x39d1; op2val:0x345b; +op3val:0x3256; valaddr_reg:x4; val_offset:0*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x16, x27, x10, x24, dyn, 0, 0, x4, 0*FLEN/8, x5, x1, x9) + +inst_26: +// rs1==x10, rs2==x29, rs3==x20, rd==x19,fs1 == 0 and fe1 == 0x0e and fm1 == 0x1d1 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x05b and fs3 == 0 and fe3 == 0x0c and fm3 == 0x256 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x10; op2:x29; op3:x20; dest:x19; op1val:0x39d1; op2val:0x345b; +op3val:0x3256; valaddr_reg:x4; val_offset:3*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x19, x10, x29, x20, dyn, 32, 0, x4, 3*FLEN/8, x5, x1, x9) + +inst_27: +// rs1==x29, rs2==x16, rs3==x31, rd==x22,fs1 == 0 and fe1 == 0x0e and fm1 == 0x1d1 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x05b and fs3 == 0 and fe3 == 0x0c and fm3 == 0x256 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x29; op2:x16; op3:x31; dest:x22; op1val:0x39d1; op2val:0x345b; +op3val:0x3256; valaddr_reg:x4; val_offset:6*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x22, x29, x16, x31, dyn, 64, 0, x4, 6*FLEN/8, x5, x1, x9) + +inst_28: +// rs1==x24, rs2==x9, rs3==x1, rd==x8,fs1 == 0 and fe1 == 0x0e and fm1 == 0x1d1 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x05b and fs3 == 0 and fe3 == 0x0c and fm3 == 0x256 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x24; op2:x9; op3:x1; dest:x8; op1val:0x39d1; op2val:0x345b; +op3val:0x3256; valaddr_reg:x4; val_offset:9*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x8, x24, x9, x1, dyn, 96, 0, x4, 9*FLEN/8, x5, x1, x3) + +inst_29: +// rs1==x31, rs2==x18, rs3==x4, rd==x11,fs1 == 0 and fe1 == 0x0e and fm1 == 0x1d1 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x05b and fs3 == 0 and fe3 == 0x0c and fm3 == 0x256 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x31; op2:x18; op3:x4; dest:x11; op1val:0x39d1; op2val:0x345b; +op3val:0x3256; valaddr_reg:x4; val_offset:12*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x11, x31, x18, x4, dyn, 128, 0, x4, 12*FLEN/8, x5, x1, x3) +RVTEST_SIGBASE(x2,signature_x2_0) + +inst_30: +// rs1==x1, rs2==x21, rs3==x3, rd==x31,fs1 == 0 and fe1 == 0x0d and fm1 == 0x052 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x056 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0b0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x1; op2:x21; op3:x3; dest:x31; op1val:0x3452; op2val:0x4056; +op3val:0x38b0; valaddr_reg:x4; val_offset:15*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x1, x21, x3, dyn, 0, 0, x4, 15*FLEN/8, x5, x2, x3) + +inst_31: +// rs1==x15, rs2==x30, rs3==x7, rd==x18,fs1 == 0 and fe1 == 0x0d and fm1 == 0x052 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x056 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0b0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x15; op2:x30; op3:x7; dest:x18; op1val:0x3452; op2val:0x4056; +op3val:0x38b0; valaddr_reg:x4; val_offset:18*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x18, x15, x30, x7, dyn, 32, 0, x4, 18*FLEN/8, x5, x2, x3) + +inst_32: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x052 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x056 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0b0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3452; op2val:0x4056; +op3val:0x38b0; valaddr_reg:x4; val_offset:21*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 21*FLEN/8, x5, x2, x3) + +inst_33: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x052 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x056 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0b0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3452; op2val:0x4056; +op3val:0x38b0; valaddr_reg:x4; val_offset:24*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 24*FLEN/8, x5, x2, x3) + +inst_34: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x052 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x056 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0b0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3452; op2val:0x4056; +op3val:0x38b0; valaddr_reg:x4; val_offset:27*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 27*FLEN/8, x5, x2, x3) + +inst_35: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x363 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x182 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x116 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3763; op2val:0x3982; +op3val:0x3516; valaddr_reg:x4; val_offset:30*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 30*FLEN/8, x5, x2, x3) + +inst_36: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x363 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x182 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x116 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3763; op2val:0x3982; +op3val:0x3516; valaddr_reg:x4; val_offset:33*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 33*FLEN/8, x5, x2, x3) + +inst_37: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x363 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x182 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x116 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3763; op2val:0x3982; +op3val:0x3516; valaddr_reg:x4; val_offset:36*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 36*FLEN/8, x5, x2, x3) + +inst_38: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x363 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x182 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x116 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3763; op2val:0x3982; +op3val:0x3516; valaddr_reg:x4; val_offset:39*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 39*FLEN/8, x5, x2, x3) + +inst_39: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x363 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x182 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x116 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3763; op2val:0x3982; +op3val:0x3516; valaddr_reg:x4; val_offset:42*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 42*FLEN/8, x5, x2, x3) + +inst_40: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x274 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x06c and fs3 == 0 and fe3 == 0x0d and fm3 == 0x324 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a74; op2val:0x386c; +op3val:0x3724; valaddr_reg:x4; val_offset:45*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 45*FLEN/8, x5, x2, x3) + +inst_41: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x274 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x06c and fs3 == 0 and fe3 == 0x0d and fm3 == 0x324 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a74; op2val:0x386c; +op3val:0x3724; valaddr_reg:x4; val_offset:48*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 48*FLEN/8, x5, x2, x3) + +inst_42: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x274 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x06c and fs3 == 0 and fe3 == 0x0d and fm3 == 0x324 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a74; op2val:0x386c; +op3val:0x3724; valaddr_reg:x4; val_offset:51*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 51*FLEN/8, x5, x2, x3) + +inst_43: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x274 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x06c and fs3 == 0 and fe3 == 0x0d and fm3 == 0x324 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a74; op2val:0x386c; +op3val:0x3724; valaddr_reg:x4; val_offset:54*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 54*FLEN/8, x5, x2, x3) + +inst_44: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x274 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x06c and fs3 == 0 and fe3 == 0x0d and fm3 == 0x324 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a74; op2val:0x386c; +op3val:0x3724; valaddr_reg:x4; val_offset:57*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 57*FLEN/8, x5, x2, x3) + +inst_45: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x23c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x389 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x323c; op2val:0x4389; +op3val:0x39e0; valaddr_reg:x4; val_offset:60*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 60*FLEN/8, x5, x2, x3) + +inst_46: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x23c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x389 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x323c; op2val:0x4389; +op3val:0x39e0; valaddr_reg:x4; val_offset:63*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 63*FLEN/8, x5, x2, x3) + +inst_47: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x23c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x389 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x323c; op2val:0x4389; +op3val:0x39e0; valaddr_reg:x4; val_offset:66*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 66*FLEN/8, x5, x2, x3) + +inst_48: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x23c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x389 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x323c; op2val:0x4389; +op3val:0x39e0; valaddr_reg:x4; val_offset:69*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 69*FLEN/8, x5, x2, x3) + +inst_49: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x23c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x389 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x323c; op2val:0x4389; +op3val:0x39e0; valaddr_reg:x4; val_offset:72*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 72*FLEN/8, x5, x2, x3) + +inst_50: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x264 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x107 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x324a; op2val:0x3e64; +op3val:0x3507; valaddr_reg:x4; val_offset:75*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 75*FLEN/8, x5, x2, x3) + +inst_51: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x264 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x107 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x324a; op2val:0x3e64; +op3val:0x3507; valaddr_reg:x4; val_offset:78*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 78*FLEN/8, x5, x2, x3) + +inst_52: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x264 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x107 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x324a; op2val:0x3e64; +op3val:0x3507; valaddr_reg:x4; val_offset:81*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 81*FLEN/8, x5, x2, x3) + +inst_53: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x264 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x107 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x324a; op2val:0x3e64; +op3val:0x3507; valaddr_reg:x4; val_offset:84*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 84*FLEN/8, x5, x2, x3) + +inst_54: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x264 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x107 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x324a; op2val:0x3e64; +op3val:0x3507; valaddr_reg:x4; val_offset:87*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 87*FLEN/8, x5, x2, x3) + +inst_55: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0fb and fs2 == 0 and fe2 == 0x11 and fm2 == 0x044 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x150 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30fb; op2val:0x4444; +op3val:0x3950; valaddr_reg:x4; val_offset:90*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 90*FLEN/8, x5, x2, x3) + +inst_56: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0fb and fs2 == 0 and fe2 == 0x11 and fm2 == 0x044 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x150 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30fb; op2val:0x4444; +op3val:0x3950; valaddr_reg:x4; val_offset:93*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 93*FLEN/8, x5, x2, x3) + +inst_57: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0fb and fs2 == 0 and fe2 == 0x11 and fm2 == 0x044 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x150 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30fb; op2val:0x4444; +op3val:0x3950; valaddr_reg:x4; val_offset:96*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 96*FLEN/8, x5, x2, x3) + +inst_58: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0fb and fs2 == 0 and fe2 == 0x11 and fm2 == 0x044 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x150 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30fb; op2val:0x4444; +op3val:0x3950; valaddr_reg:x4; val_offset:99*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 99*FLEN/8, x5, x2, x3) + +inst_59: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0fb and fs2 == 0 and fe2 == 0x11 and fm2 == 0x044 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x150 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30fb; op2val:0x4444; +op3val:0x3950; valaddr_reg:x4; val_offset:102*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 102*FLEN/8, x5, x2, x3) + +inst_60: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x341 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x30c and fs3 == 0 and fe3 == 0x0c and fm3 == 0x264 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b41; op2val:0x330c; +op3val:0x3264; valaddr_reg:x4; val_offset:105*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 105*FLEN/8, x5, x2, x3) + +inst_61: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x341 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x30c and fs3 == 0 and fe3 == 0x0c and fm3 == 0x264 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b41; op2val:0x330c; +op3val:0x3264; valaddr_reg:x4; val_offset:108*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 108*FLEN/8, x5, x2, x3) + +inst_62: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x341 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x30c and fs3 == 0 and fe3 == 0x0c and fm3 == 0x264 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b41; op2val:0x330c; +op3val:0x3264; valaddr_reg:x4; val_offset:111*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 111*FLEN/8, x5, x2, x3) + +inst_63: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x341 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x30c and fs3 == 0 and fe3 == 0x0c and fm3 == 0x264 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b41; op2val:0x330c; +op3val:0x3264; valaddr_reg:x4; val_offset:114*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 114*FLEN/8, x5, x2, x3) + +inst_64: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x341 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x30c and fs3 == 0 and fe3 == 0x0c and fm3 == 0x264 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b41; op2val:0x330c; +op3val:0x3264; valaddr_reg:x4; val_offset:117*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 117*FLEN/8, x5, x2, x3) + +inst_65: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x23f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1af and fs3 == 0 and fe3 == 0x0e and fm3 == 0x070 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x323f; op2val:0x41af; +op3val:0x3870; valaddr_reg:x4; val_offset:120*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 120*FLEN/8, x5, x2, x3) + +inst_66: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x23f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1af and fs3 == 0 and fe3 == 0x0e and fm3 == 0x070 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x323f; op2val:0x41af; +op3val:0x3870; valaddr_reg:x4; val_offset:123*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 123*FLEN/8, x5, x2, x3) + +inst_67: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x23f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1af and fs3 == 0 and fe3 == 0x0e and fm3 == 0x070 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x323f; op2val:0x41af; +op3val:0x3870; valaddr_reg:x4; val_offset:126*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 126*FLEN/8, x5, x2, x3) + +inst_68: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x23f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1af and fs3 == 0 and fe3 == 0x0e and fm3 == 0x070 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x323f; op2val:0x41af; +op3val:0x3870; valaddr_reg:x4; val_offset:129*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 129*FLEN/8, x5, x2, x3) + +inst_69: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x23f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1af and fs3 == 0 and fe3 == 0x0e and fm3 == 0x070 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x323f; op2val:0x41af; +op3val:0x3870; valaddr_reg:x4; val_offset:132*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 132*FLEN/8, x5, x2, x3) + +inst_70: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x33f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x316 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x26c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b3f; op2val:0x3b16; +op3val:0x3a6c; valaddr_reg:x4; val_offset:135*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 135*FLEN/8, x5, x2, x3) + +inst_71: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x33f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x316 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x26c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b3f; op2val:0x3b16; +op3val:0x3a6c; valaddr_reg:x4; val_offset:138*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 138*FLEN/8, x5, x2, x3) + +inst_72: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x33f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x316 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x26c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b3f; op2val:0x3b16; +op3val:0x3a6c; valaddr_reg:x4; val_offset:141*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 141*FLEN/8, x5, x2, x3) + +inst_73: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x33f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x316 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x26c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b3f; op2val:0x3b16; +op3val:0x3a6c; valaddr_reg:x4; val_offset:144*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 144*FLEN/8, x5, x2, x3) + +inst_74: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x33f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x316 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x26c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b3f; op2val:0x3b16; +op3val:0x3a6c; valaddr_reg:x4; val_offset:147*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 147*FLEN/8, x5, x2, x3) + +inst_75: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1d7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3c4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ab and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35d7; op2val:0x3fc4; +op3val:0x39ab; valaddr_reg:x4; val_offset:150*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 150*FLEN/8, x5, x2, x3) + +inst_76: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1d7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3c4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ab and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35d7; op2val:0x3fc4; +op3val:0x39ab; valaddr_reg:x4; val_offset:153*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 153*FLEN/8, x5, x2, x3) + +inst_77: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1d7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3c4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ab and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35d7; op2val:0x3fc4; +op3val:0x39ab; valaddr_reg:x4; val_offset:156*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 156*FLEN/8, x5, x2, x3) + +inst_78: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1d7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3c4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ab and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35d7; op2val:0x3fc4; +op3val:0x39ab; valaddr_reg:x4; val_offset:159*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 159*FLEN/8, x5, x2, x3) + +inst_79: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1d7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3c4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ab and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35d7; op2val:0x3fc4; +op3val:0x39ab; valaddr_reg:x4; val_offset:162*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 162*FLEN/8, x5, x2, x3) + +inst_80: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x239 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x03a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x295 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2a39; op2val:0x483a; +op3val:0x3695; valaddr_reg:x4; val_offset:165*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 165*FLEN/8, x5, x2, x3) + +inst_81: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x239 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x03a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x295 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2a39; op2val:0x483a; +op3val:0x3695; valaddr_reg:x4; val_offset:168*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 168*FLEN/8, x5, x2, x3) + +inst_82: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x239 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x03a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x295 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2a39; op2val:0x483a; +op3val:0x3695; valaddr_reg:x4; val_offset:171*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 171*FLEN/8, x5, x2, x3) + +inst_83: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x239 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x03a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x295 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2a39; op2val:0x483a; +op3val:0x3695; valaddr_reg:x4; val_offset:174*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 174*FLEN/8, x5, x2, x3) + +inst_84: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x239 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x03a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x295 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2a39; op2val:0x483a; +op3val:0x3695; valaddr_reg:x4; val_offset:177*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 177*FLEN/8, x5, x2, x3) + +inst_85: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x264 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2e6 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x183 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a64; op2val:0x36e6; +op3val:0x3583; valaddr_reg:x4; val_offset:180*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 180*FLEN/8, x5, x2, x3) + +inst_86: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x264 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2e6 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x183 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a64; op2val:0x36e6; +op3val:0x3583; valaddr_reg:x4; val_offset:183*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 183*FLEN/8, x5, x2, x3) + +inst_87: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x264 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2e6 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x183 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a64; op2val:0x36e6; +op3val:0x3583; valaddr_reg:x4; val_offset:186*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 186*FLEN/8, x5, x2, x3) + +inst_88: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x264 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2e6 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x183 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a64; op2val:0x36e6; +op3val:0x3583; valaddr_reg:x4; val_offset:189*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 189*FLEN/8, x5, x2, x3) + +inst_89: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x264 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2e6 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x183 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a64; op2val:0x36e6; +op3val:0x3583; valaddr_reg:x4; val_offset:192*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 192*FLEN/8, x5, x2, x3) + +inst_90: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11d and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2ba and fs3 == 0 and fe3 == 0x0b and fm3 == 0x04e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x391d; op2val:0x2eba; +op3val:0x2c4e; valaddr_reg:x4; val_offset:195*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 195*FLEN/8, x5, x2, x3) + +inst_91: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11d and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2ba and fs3 == 0 and fe3 == 0x0b and fm3 == 0x04e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x391d; op2val:0x2eba; +op3val:0x2c4e; valaddr_reg:x4; val_offset:198*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 198*FLEN/8, x5, x2, x3) + +inst_92: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11d and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2ba and fs3 == 0 and fe3 == 0x0b and fm3 == 0x04e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x391d; op2val:0x2eba; +op3val:0x2c4e; valaddr_reg:x4; val_offset:201*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 201*FLEN/8, x5, x2, x3) + +inst_93: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11d and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2ba and fs3 == 0 and fe3 == 0x0b and fm3 == 0x04e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x391d; op2val:0x2eba; +op3val:0x2c4e; valaddr_reg:x4; val_offset:204*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 204*FLEN/8, x5, x2, x3) + +inst_94: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11d and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2ba and fs3 == 0 and fe3 == 0x0b and fm3 == 0x04e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x391d; op2val:0x2eba; +op3val:0x2c4e; valaddr_reg:x4; val_offset:207*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 207*FLEN/8, x5, x2, x3) + +inst_95: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1ca and fs2 == 0 and fe2 == 0x11 and fm2 == 0x15d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3c3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2dca; op2val:0x455d; +op3val:0x37c3; valaddr_reg:x4; val_offset:210*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 210*FLEN/8, x5, x2, x3) + +inst_96: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1ca and fs2 == 0 and fe2 == 0x11 and fm2 == 0x15d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3c3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2dca; op2val:0x455d; +op3val:0x37c3; valaddr_reg:x4; val_offset:213*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 213*FLEN/8, x5, x2, x3) + +inst_97: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1ca and fs2 == 0 and fe2 == 0x11 and fm2 == 0x15d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3c3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2dca; op2val:0x455d; +op3val:0x37c3; valaddr_reg:x4; val_offset:216*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 216*FLEN/8, x5, x2, x3) + +inst_98: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1ca and fs2 == 0 and fe2 == 0x11 and fm2 == 0x15d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3c3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2dca; op2val:0x455d; +op3val:0x37c3; valaddr_reg:x4; val_offset:219*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 219*FLEN/8, x5, x2, x3) + +inst_99: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1ca and fs2 == 0 and fe2 == 0x11 and fm2 == 0x15d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3c3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2dca; op2val:0x455d; +op3val:0x37c3; valaddr_reg:x4; val_offset:222*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 222*FLEN/8, x5, x2, x3) + +inst_100: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1af and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2cc and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0d5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35af; op2val:0x3acc; +op3val:0x34d5; valaddr_reg:x4; val_offset:225*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 225*FLEN/8, x5, x2, x3) + +inst_101: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1af and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2cc and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0d5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35af; op2val:0x3acc; +op3val:0x34d5; valaddr_reg:x4; val_offset:228*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 228*FLEN/8, x5, x2, x3) + +inst_102: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1af and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2cc and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0d5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35af; op2val:0x3acc; +op3val:0x34d5; valaddr_reg:x4; val_offset:231*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 231*FLEN/8, x5, x2, x3) + +inst_103: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1af and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2cc and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0d5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35af; op2val:0x3acc; +op3val:0x34d5; valaddr_reg:x4; val_offset:234*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 234*FLEN/8, x5, x2, x3) + +inst_104: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1af and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2cc and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0d5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35af; op2val:0x3acc; +op3val:0x34d5; valaddr_reg:x4; val_offset:237*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 237*FLEN/8, x5, x2, x3) + +inst_105: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x239 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3c6 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x20c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3239; op2val:0x2fc6; +op3val:0x260c; valaddr_reg:x4; val_offset:240*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 240*FLEN/8, x5, x2, x3) + +inst_106: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x239 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3c6 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x20c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3239; op2val:0x2fc6; +op3val:0x260c; valaddr_reg:x4; val_offset:243*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 243*FLEN/8, x5, x2, x3) + +inst_107: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x239 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3c6 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x20c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3239; op2val:0x2fc6; +op3val:0x260c; valaddr_reg:x4; val_offset:246*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 246*FLEN/8, x5, x2, x3) + +inst_108: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x239 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3c6 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x20c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3239; op2val:0x2fc6; +op3val:0x260c; valaddr_reg:x4; val_offset:249*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 249*FLEN/8, x5, x2, x3) + +inst_109: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x239 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3c6 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x20c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3239; op2val:0x2fc6; +op3val:0x260c; valaddr_reg:x4; val_offset:252*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 252*FLEN/8, x5, x2, x3) + +inst_110: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x142 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x11b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bc5; op2val:0x3942; +op3val:0x391b; valaddr_reg:x4; val_offset:255*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 255*FLEN/8, x5, x2, x3) + +inst_111: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x142 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x11b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bc5; op2val:0x3942; +op3val:0x391b; valaddr_reg:x4; val_offset:258*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 258*FLEN/8, x5, x2, x3) + +inst_112: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x142 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x11b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bc5; op2val:0x3942; +op3val:0x391b; valaddr_reg:x4; val_offset:261*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 261*FLEN/8, x5, x2, x3) + +inst_113: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x142 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x11b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bc5; op2val:0x3942; +op3val:0x391b; valaddr_reg:x4; val_offset:264*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 264*FLEN/8, x5, x2, x3) + +inst_114: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x142 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x11b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bc5; op2val:0x3942; +op3val:0x391b; valaddr_reg:x4; val_offset:267*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 267*FLEN/8, x5, x2, x3) + +inst_115: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x25f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2fc and fs3 == 0 and fe3 == 0x0e and fm3 == 0x190 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x365f; op2val:0x3efc; +op3val:0x3990; valaddr_reg:x4; val_offset:270*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 270*FLEN/8, x5, x2, x3) + +inst_116: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x25f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2fc and fs3 == 0 and fe3 == 0x0e and fm3 == 0x190 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x365f; op2val:0x3efc; +op3val:0x3990; valaddr_reg:x4; val_offset:273*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 273*FLEN/8, x5, x2, x3) + +inst_117: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x25f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2fc and fs3 == 0 and fe3 == 0x0e and fm3 == 0x190 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x365f; op2val:0x3efc; +op3val:0x3990; valaddr_reg:x4; val_offset:276*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 276*FLEN/8, x5, x2, x3) + +inst_118: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x25f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2fc and fs3 == 0 and fe3 == 0x0e and fm3 == 0x190 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x365f; op2val:0x3efc; +op3val:0x3990; valaddr_reg:x4; val_offset:279*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 279*FLEN/8, x5, x2, x3) + +inst_119: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x25f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2fc and fs3 == 0 and fe3 == 0x0e and fm3 == 0x190 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x365f; op2val:0x3efc; +op3val:0x3990; valaddr_reg:x4; val_offset:282*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 282*FLEN/8, x5, x2, x3) + +inst_120: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x292 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x06e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x348 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3692; op2val:0x406e; +op3val:0x3b48; valaddr_reg:x4; val_offset:285*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 285*FLEN/8, x5, x2, x3) + +inst_121: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x292 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x06e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x348 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3692; op2val:0x406e; +op3val:0x3b48; valaddr_reg:x4; val_offset:288*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 288*FLEN/8, x5, x2, x3) + +inst_122: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x292 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x06e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x348 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3692; op2val:0x406e; +op3val:0x3b48; valaddr_reg:x4; val_offset:291*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 291*FLEN/8, x5, x2, x3) + +inst_123: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x292 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x06e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x348 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3692; op2val:0x406e; +op3val:0x3b48; valaddr_reg:x4; val_offset:294*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 294*FLEN/8, x5, x2, x3) + +inst_124: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x292 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x06e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x348 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3692; op2val:0x406e; +op3val:0x3b48; valaddr_reg:x4; val_offset:297*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 297*FLEN/8, x5, x2, x3) + +inst_125: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3ac and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3ea and fs3 == 0 and fe3 == 0x0d and fm3 == 0x398 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2fac; op2val:0x43ea; +op3val:0x3798; valaddr_reg:x4; val_offset:300*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 300*FLEN/8, x5, x2, x3) + +inst_126: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3ac and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3ea and fs3 == 0 and fe3 == 0x0d and fm3 == 0x398 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2fac; op2val:0x43ea; +op3val:0x3798; valaddr_reg:x4; val_offset:303*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 303*FLEN/8, x5, x2, x3) + +inst_127: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3ac and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3ea and fs3 == 0 and fe3 == 0x0d and fm3 == 0x398 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2fac; op2val:0x43ea; +op3val:0x3798; valaddr_reg:x4; val_offset:306*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 306*FLEN/8, x5, x2, x3) + +inst_128: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3ac and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3ea and fs3 == 0 and fe3 == 0x0d and fm3 == 0x398 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2fac; op2val:0x43ea; +op3val:0x3798; valaddr_reg:x4; val_offset:309*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 309*FLEN/8, x5, x2, x3) + +inst_129: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3ac and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3ea and fs3 == 0 and fe3 == 0x0d and fm3 == 0x398 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2fac; op2val:0x43ea; +op3val:0x3798; valaddr_reg:x4; val_offset:312*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 312*FLEN/8, x5, x2, x3) + +inst_130: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x310 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x21c and fs3 == 0 and fe3 == 0x0d and fm3 == 0x165 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b10; op2val:0x361c; +op3val:0x3565; valaddr_reg:x4; val_offset:315*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 315*FLEN/8, x5, x2, x3) + +inst_131: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x310 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x21c and fs3 == 0 and fe3 == 0x0d and fm3 == 0x165 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b10; op2val:0x361c; +op3val:0x3565; valaddr_reg:x4; val_offset:318*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 318*FLEN/8, x5, x2, x3) + +inst_132: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x310 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x21c and fs3 == 0 and fe3 == 0x0d and fm3 == 0x165 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b10; op2val:0x361c; +op3val:0x3565; valaddr_reg:x4; val_offset:321*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 321*FLEN/8, x5, x2, x3) + +inst_133: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x310 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x21c and fs3 == 0 and fe3 == 0x0d and fm3 == 0x165 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b10; op2val:0x361c; +op3val:0x3565; valaddr_reg:x4; val_offset:324*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 324*FLEN/8, x5, x2, x3) + +inst_134: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x310 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x21c and fs3 == 0 and fe3 == 0x0d and fm3 == 0x165 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b10; op2val:0x361c; +op3val:0x3565; valaddr_reg:x4; val_offset:327*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 327*FLEN/8, x5, x2, x3) + +inst_135: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x180 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ac and fs3 == 0 and fe3 == 0x0e and fm3 == 0x26e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3980; op2val:0x3cac; +op3val:0x3a6e; valaddr_reg:x4; val_offset:330*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 330*FLEN/8, x5, x2, x3) + +inst_136: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x180 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ac and fs3 == 0 and fe3 == 0x0e and fm3 == 0x26e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3980; op2val:0x3cac; +op3val:0x3a6e; valaddr_reg:x4; val_offset:333*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 333*FLEN/8, x5, x2, x3) + +inst_137: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x180 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ac and fs3 == 0 and fe3 == 0x0e and fm3 == 0x26e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3980; op2val:0x3cac; +op3val:0x3a6e; valaddr_reg:x4; val_offset:336*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 336*FLEN/8, x5, x2, x3) + +inst_138: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x180 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ac and fs3 == 0 and fe3 == 0x0e and fm3 == 0x26e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3980; op2val:0x3cac; +op3val:0x3a6e; valaddr_reg:x4; val_offset:339*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 339*FLEN/8, x5, x2, x3) + +inst_139: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x180 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ac and fs3 == 0 and fe3 == 0x0e and fm3 == 0x26e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3980; op2val:0x3cac; +op3val:0x3a6e; valaddr_reg:x4; val_offset:342*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 342*FLEN/8, x5, x2, x3) + +inst_140: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x021 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2ad and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2e5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3821; op2val:0x3ead; +op3val:0x3ae5; valaddr_reg:x4; val_offset:345*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 345*FLEN/8, x5, x2, x3) + +inst_141: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x021 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2ad and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2e5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3821; op2val:0x3ead; +op3val:0x3ae5; valaddr_reg:x4; val_offset:348*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 348*FLEN/8, x5, x2, x3) + +inst_142: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x021 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2ad and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2e5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3821; op2val:0x3ead; +op3val:0x3ae5; valaddr_reg:x4; val_offset:351*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 351*FLEN/8, x5, x2, x3) + +inst_143: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x021 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2ad and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2e5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3821; op2val:0x3ead; +op3val:0x3ae5; valaddr_reg:x4; val_offset:354*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 354*FLEN/8, x5, x2, x3) + +inst_144: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x021 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2ad and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2e5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3821; op2val:0x3ead; +op3val:0x3ae5; valaddr_reg:x4; val_offset:357*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 357*FLEN/8, x5, x2, x3) + +inst_145: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x252 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x172 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x04d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a52; op2val:0x3172; +op3val:0x304d; valaddr_reg:x4; val_offset:360*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 360*FLEN/8, x5, x2, x3) + +inst_146: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x252 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x172 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x04d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a52; op2val:0x3172; +op3val:0x304d; valaddr_reg:x4; val_offset:363*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 363*FLEN/8, x5, x2, x3) + +inst_147: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x252 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x172 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x04d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a52; op2val:0x3172; +op3val:0x304d; valaddr_reg:x4; val_offset:366*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 366*FLEN/8, x5, x2, x3) + +inst_148: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x252 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x172 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x04d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a52; op2val:0x3172; +op3val:0x304d; valaddr_reg:x4; val_offset:369*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 369*FLEN/8, x5, x2, x3) + +inst_149: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x252 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x172 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x04d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a52; op2val:0x3172; +op3val:0x304d; valaddr_reg:x4; val_offset:372*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 372*FLEN/8, x5, x2, x3) + +inst_150: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0d4 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x28b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3e6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34d4; op2val:0x428b; +op3val:0x3be6; valaddr_reg:x4; val_offset:375*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 375*FLEN/8, x5, x2, x3) + +inst_151: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0d4 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x28b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3e6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34d4; op2val:0x428b; +op3val:0x3be6; valaddr_reg:x4; val_offset:378*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 378*FLEN/8, x5, x2, x3) + +inst_152: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0d4 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x28b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3e6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34d4; op2val:0x428b; +op3val:0x3be6; valaddr_reg:x4; val_offset:381*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 381*FLEN/8, x5, x2, x3) + +inst_153: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0d4 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x28b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3e6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34d4; op2val:0x428b; +op3val:0x3be6; valaddr_reg:x4; val_offset:384*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 384*FLEN/8, x5, x2, x3) + +inst_154: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0d4 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x28b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3e6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34d4; op2val:0x428b; +op3val:0x3be6; valaddr_reg:x4; val_offset:387*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 387*FLEN/8, x5, x2, x3) + +inst_155: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x31a and fs2 == 0 and fe2 == 0x11 and fm2 == 0x06d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3dd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x331a; op2val:0x446d; +op3val:0x3bdd; valaddr_reg:x4; val_offset:390*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 390*FLEN/8, x5, x2, x3) + +inst_156: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x31a and fs2 == 0 and fe2 == 0x11 and fm2 == 0x06d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3dd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x331a; op2val:0x446d; +op3val:0x3bdd; valaddr_reg:x4; val_offset:393*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 393*FLEN/8, x5, x2, x3) + +inst_157: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x31a and fs2 == 0 and fe2 == 0x11 and fm2 == 0x06d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3dd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x331a; op2val:0x446d; +op3val:0x3bdd; valaddr_reg:x4; val_offset:396*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 396*FLEN/8, x5, x2, x3) +RVTEST_SIGBASE(x2,signature_x2_1) + +inst_158: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x31a and fs2 == 0 and fe2 == 0x11 and fm2 == 0x06d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3dd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x331a; op2val:0x446d; +op3val:0x3bdd; valaddr_reg:x4; val_offset:399*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 399*FLEN/8, x5, x2, x3) + +inst_159: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x31a and fs2 == 0 and fe2 == 0x11 and fm2 == 0x06d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3dd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x331a; op2val:0x446d; +op3val:0x3bdd; valaddr_reg:x4; val_offset:402*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 402*FLEN/8, x5, x2, x3) + +inst_160: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x156 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x095 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x21d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3956; op2val:0x3095; +op3val:0x2e1d; valaddr_reg:x4; val_offset:405*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 405*FLEN/8, x5, x2, x3) + +inst_161: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x156 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x095 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x21d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3956; op2val:0x3095; +op3val:0x2e1d; valaddr_reg:x4; val_offset:408*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 408*FLEN/8, x5, x2, x3) + +inst_162: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x156 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x095 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x21d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3956; op2val:0x3095; +op3val:0x2e1d; valaddr_reg:x4; val_offset:411*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 411*FLEN/8, x5, x2, x3) + +inst_163: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x156 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x095 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x21d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3956; op2val:0x3095; +op3val:0x2e1d; valaddr_reg:x4; val_offset:414*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 414*FLEN/8, x5, x2, x3) + +inst_164: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x156 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x095 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x21d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3956; op2val:0x3095; +op3val:0x2e1d; valaddr_reg:x4; val_offset:417*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 417*FLEN/8, x5, x2, x3) + +inst_165: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x213 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x34f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x18d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3613; op2val:0x3f4f; +op3val:0x398d; valaddr_reg:x4; val_offset:420*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 420*FLEN/8, x5, x2, x3) + +inst_166: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x213 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x34f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x18d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3613; op2val:0x3f4f; +op3val:0x398d; valaddr_reg:x4; val_offset:423*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 423*FLEN/8, x5, x2, x3) + +inst_167: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x213 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x34f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x18d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3613; op2val:0x3f4f; +op3val:0x398d; valaddr_reg:x4; val_offset:426*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 426*FLEN/8, x5, x2, x3) + +inst_168: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x213 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x34f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x18d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3613; op2val:0x3f4f; +op3val:0x398d; valaddr_reg:x4; val_offset:429*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 429*FLEN/8, x5, x2, x3) + +inst_169: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x213 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x34f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x18d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3613; op2val:0x3f4f; +op3val:0x398d; valaddr_reg:x4; val_offset:432*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 432*FLEN/8, x5, x2, x3) + +inst_170: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0fb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3d9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0e2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38fb; op2val:0x3bd9; +op3val:0x38e2; valaddr_reg:x4; val_offset:435*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 435*FLEN/8, x5, x2, x3) + +inst_171: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0fb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3d9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0e2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38fb; op2val:0x3bd9; +op3val:0x38e2; valaddr_reg:x4; val_offset:438*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 438*FLEN/8, x5, x2, x3) + +inst_172: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0fb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3d9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0e2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38fb; op2val:0x3bd9; +op3val:0x38e2; valaddr_reg:x4; val_offset:441*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 441*FLEN/8, x5, x2, x3) + +inst_173: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0fb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3d9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0e2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38fb; op2val:0x3bd9; +op3val:0x38e2; valaddr_reg:x4; val_offset:444*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 444*FLEN/8, x5, x2, x3) + +inst_174: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0fb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3d9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0e2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38fb; op2val:0x3bd9; +op3val:0x38e2; valaddr_reg:x4; val_offset:447*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 447*FLEN/8, x5, x2, x3) + +inst_175: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fc and fs2 == 0 and fe2 == 0x02 and fm2 == 0x08e and fs3 == 0 and fe3 == 0x01 and fm3 == 0x3f6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3afc; op2val:0x88e; +op3val:0x7f6; valaddr_reg:x4; val_offset:450*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 450*FLEN/8, x5, x2, x3) + +inst_176: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fc and fs2 == 0 and fe2 == 0x02 and fm2 == 0x08e and fs3 == 0 and fe3 == 0x01 and fm3 == 0x3f6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3afc; op2val:0x88e; +op3val:0x7f6; valaddr_reg:x4; val_offset:453*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 453*FLEN/8, x5, x2, x3) + +inst_177: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fc and fs2 == 0 and fe2 == 0x02 and fm2 == 0x08e and fs3 == 0 and fe3 == 0x01 and fm3 == 0x3f6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3afc; op2val:0x88e; +op3val:0x7f6; valaddr_reg:x4; val_offset:456*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 456*FLEN/8, x5, x2, x3) + +inst_178: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fc and fs2 == 0 and fe2 == 0x02 and fm2 == 0x08e and fs3 == 0 and fe3 == 0x01 and fm3 == 0x3f6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3afc; op2val:0x88e; +op3val:0x7f6; valaddr_reg:x4; val_offset:459*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 459*FLEN/8, x5, x2, x3) + +inst_179: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fc and fs2 == 0 and fe2 == 0x02 and fm2 == 0x08e and fs3 == 0 and fe3 == 0x01 and fm3 == 0x3f6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3afc; op2val:0x88e; +op3val:0x7f6; valaddr_reg:x4; val_offset:462*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 462*FLEN/8, x5, x2, x3) + +inst_180: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x391 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0e1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x09d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b91; op2val:0x38e1; +op3val:0x389d; valaddr_reg:x4; val_offset:465*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 465*FLEN/8, x5, x2, x3) + +inst_181: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x391 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0e1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x09d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b91; op2val:0x38e1; +op3val:0x389d; valaddr_reg:x4; val_offset:468*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 468*FLEN/8, x5, x2, x3) + +inst_182: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x391 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0e1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x09d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b91; op2val:0x38e1; +op3val:0x389d; valaddr_reg:x4; val_offset:471*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 471*FLEN/8, x5, x2, x3) + +inst_183: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x391 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0e1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x09d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b91; op2val:0x38e1; +op3val:0x389d; valaddr_reg:x4; val_offset:474*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 474*FLEN/8, x5, x2, x3) + +inst_184: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x391 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0e1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x09d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b91; op2val:0x38e1; +op3val:0x389d; valaddr_reg:x4; val_offset:477*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 477*FLEN/8, x5, x2, x3) + +inst_185: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x00f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0bf and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0d1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x340f; op2val:0x40bf; +op3val:0x38d1; valaddr_reg:x4; val_offset:480*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 480*FLEN/8, x5, x2, x3) + +inst_186: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x00f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0bf and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0d1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x340f; op2val:0x40bf; +op3val:0x38d1; valaddr_reg:x4; val_offset:483*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 483*FLEN/8, x5, x2, x3) + +inst_187: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x00f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0bf and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0d1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x340f; op2val:0x40bf; +op3val:0x38d1; valaddr_reg:x4; val_offset:486*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 486*FLEN/8, x5, x2, x3) + +inst_188: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x00f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0bf and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0d1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x340f; op2val:0x40bf; +op3val:0x38d1; valaddr_reg:x4; val_offset:489*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 489*FLEN/8, x5, x2, x3) + +inst_189: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x00f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0bf and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0d1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x340f; op2val:0x40bf; +op3val:0x38d1; valaddr_reg:x4; val_offset:492*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 492*FLEN/8, x5, x2, x3) + +inst_190: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x0de and fs2 == 0 and fe2 == 0x14 and fm2 == 0x0f5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x209 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x24de; op2val:0x50f5; +op3val:0x3a09; valaddr_reg:x4; val_offset:495*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 495*FLEN/8, x5, x2, x3) + +inst_191: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x0de and fs2 == 0 and fe2 == 0x14 and fm2 == 0x0f5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x209 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x24de; op2val:0x50f5; +op3val:0x3a09; valaddr_reg:x4; val_offset:498*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 498*FLEN/8, x5, x2, x3) + +inst_192: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x0de and fs2 == 0 and fe2 == 0x14 and fm2 == 0x0f5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x209 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x24de; op2val:0x50f5; +op3val:0x3a09; valaddr_reg:x4; val_offset:501*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 501*FLEN/8, x5, x2, x3) + +inst_193: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x0de and fs2 == 0 and fe2 == 0x14 and fm2 == 0x0f5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x209 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x24de; op2val:0x50f5; +op3val:0x3a09; valaddr_reg:x4; val_offset:504*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 504*FLEN/8, x5, x2, x3) + +inst_194: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x0de and fs2 == 0 and fe2 == 0x14 and fm2 == 0x0f5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x209 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x24de; op2val:0x50f5; +op3val:0x3a09; valaddr_reg:x4; val_offset:507*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 507*FLEN/8, x5, x2, x3) + +inst_195: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x14f and fs2 == 0 and fe2 == 0x11 and fm2 == 0x131 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x2e5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x254f; op2val:0x4531; +op3val:0x2ee5; valaddr_reg:x4; val_offset:510*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 510*FLEN/8, x5, x2, x3) + +inst_196: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x14f and fs2 == 0 and fe2 == 0x11 and fm2 == 0x131 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x2e5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x254f; op2val:0x4531; +op3val:0x2ee5; valaddr_reg:x4; val_offset:513*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 513*FLEN/8, x5, x2, x3) + +inst_197: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x14f and fs2 == 0 and fe2 == 0x11 and fm2 == 0x131 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x2e5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x254f; op2val:0x4531; +op3val:0x2ee5; valaddr_reg:x4; val_offset:516*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 516*FLEN/8, x5, x2, x3) + +inst_198: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x14f and fs2 == 0 and fe2 == 0x11 and fm2 == 0x131 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x2e5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x254f; op2val:0x4531; +op3val:0x2ee5; valaddr_reg:x4; val_offset:519*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 519*FLEN/8, x5, x2, x3) + +inst_199: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x14f and fs2 == 0 and fe2 == 0x11 and fm2 == 0x131 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x2e5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x254f; op2val:0x4531; +op3val:0x2ee5; valaddr_reg:x4; val_offset:522*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 522*FLEN/8, x5, x2, x3) + +inst_200: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x146 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x15c and fs3 == 0 and fe3 == 0x0b and fm3 == 0x312 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3546; op2val:0x355c; +op3val:0x2f12; valaddr_reg:x4; val_offset:525*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 525*FLEN/8, x5, x2, x3) + +inst_201: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x146 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x15c and fs3 == 0 and fe3 == 0x0b and fm3 == 0x312 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3546; op2val:0x355c; +op3val:0x2f12; valaddr_reg:x4; val_offset:528*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 528*FLEN/8, x5, x2, x3) + +inst_202: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x146 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x15c and fs3 == 0 and fe3 == 0x0b and fm3 == 0x312 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3546; op2val:0x355c; +op3val:0x2f12; valaddr_reg:x4; val_offset:531*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 531*FLEN/8, x5, x2, x3) + +inst_203: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x146 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x15c and fs3 == 0 and fe3 == 0x0b and fm3 == 0x312 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3546; op2val:0x355c; +op3val:0x2f12; valaddr_reg:x4; val_offset:534*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 534*FLEN/8, x5, x2, x3) + +inst_204: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x146 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x15c and fs3 == 0 and fe3 == 0x0b and fm3 == 0x312 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3546; op2val:0x355c; +op3val:0x2f12; valaddr_reg:x4; val_offset:537*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 537*FLEN/8, x5, x2, x3) + +inst_205: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x06c and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0e2 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x166 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x386c; op2val:0x34e2; +op3val:0x3166; valaddr_reg:x4; val_offset:540*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 540*FLEN/8, x5, x2, x3) + +inst_206: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x06c and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0e2 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x166 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x386c; op2val:0x34e2; +op3val:0x3166; valaddr_reg:x4; val_offset:543*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 543*FLEN/8, x5, x2, x3) + +inst_207: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x06c and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0e2 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x166 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x386c; op2val:0x34e2; +op3val:0x3166; valaddr_reg:x4; val_offset:546*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 546*FLEN/8, x5, x2, x3) + +inst_208: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x06c and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0e2 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x166 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x386c; op2val:0x34e2; +op3val:0x3166; valaddr_reg:x4; val_offset:549*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 549*FLEN/8, x5, x2, x3) + +inst_209: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x06c and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0e2 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x166 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x386c; op2val:0x34e2; +op3val:0x3166; valaddr_reg:x4; val_offset:552*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 552*FLEN/8, x5, x2, x3) + +inst_210: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x286 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0bd and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3bb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3286; op2val:0x40bd; +op3val:0x37bb; valaddr_reg:x4; val_offset:555*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 555*FLEN/8, x5, x2, x3) + +inst_211: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x286 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0bd and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3bb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3286; op2val:0x40bd; +op3val:0x37bb; valaddr_reg:x4; val_offset:558*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 558*FLEN/8, x5, x2, x3) + +inst_212: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x286 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0bd and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3bb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3286; op2val:0x40bd; +op3val:0x37bb; valaddr_reg:x4; val_offset:561*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 561*FLEN/8, x5, x2, x3) + +inst_213: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x286 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0bd and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3bb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3286; op2val:0x40bd; +op3val:0x37bb; valaddr_reg:x4; val_offset:564*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 564*FLEN/8, x5, x2, x3) + +inst_214: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x286 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0bd and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3bb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3286; op2val:0x40bd; +op3val:0x37bb; valaddr_reg:x4; val_offset:567*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 567*FLEN/8, x5, x2, x3) + +inst_215: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x03b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x073 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0b5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x383b; op2val:0x3873; +op3val:0x34b5; valaddr_reg:x4; val_offset:570*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 570*FLEN/8, x5, x2, x3) + +inst_216: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x03b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x073 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0b5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x383b; op2val:0x3873; +op3val:0x34b5; valaddr_reg:x4; val_offset:573*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 573*FLEN/8, x5, x2, x3) + +inst_217: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x03b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x073 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0b5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x383b; op2val:0x3873; +op3val:0x34b5; valaddr_reg:x4; val_offset:576*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 576*FLEN/8, x5, x2, x3) + +inst_218: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x03b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x073 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0b5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x383b; op2val:0x3873; +op3val:0x34b5; valaddr_reg:x4; val_offset:579*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 579*FLEN/8, x5, x2, x3) + +inst_219: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x03b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x073 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0b5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x383b; op2val:0x3873; +op3val:0x34b5; valaddr_reg:x4; val_offset:582*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 582*FLEN/8, x5, x2, x3) + +inst_220: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ba and fs2 == 0 and fe2 == 0x0f and fm2 == 0x22f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x350 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ba; op2val:0x3e2f; +op3val:0x3b50; valaddr_reg:x4; val_offset:585*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 585*FLEN/8, x5, x2, x3) + +inst_221: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ba and fs2 == 0 and fe2 == 0x0f and fm2 == 0x22f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x350 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ba; op2val:0x3e2f; +op3val:0x3b50; valaddr_reg:x4; val_offset:588*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 588*FLEN/8, x5, x2, x3) + +inst_222: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ba and fs2 == 0 and fe2 == 0x0f and fm2 == 0x22f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x350 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ba; op2val:0x3e2f; +op3val:0x3b50; valaddr_reg:x4; val_offset:591*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 591*FLEN/8, x5, x2, x3) + +inst_223: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ba and fs2 == 0 and fe2 == 0x0f and fm2 == 0x22f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x350 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ba; op2val:0x3e2f; +op3val:0x3b50; valaddr_reg:x4; val_offset:594*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 594*FLEN/8, x5, x2, x3) + +inst_224: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ba and fs2 == 0 and fe2 == 0x0f and fm2 == 0x22f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x350 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ba; op2val:0x3e2f; +op3val:0x3b50; valaddr_reg:x4; val_offset:597*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 597*FLEN/8, x5, x2, x3) + +inst_225: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x00e and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1ca and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1df and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x340e; op2val:0x41ca; +op3val:0x39df; valaddr_reg:x4; val_offset:600*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 600*FLEN/8, x5, x2, x3) + +inst_226: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x00e and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1ca and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1df and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x340e; op2val:0x41ca; +op3val:0x39df; valaddr_reg:x4; val_offset:603*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 603*FLEN/8, x5, x2, x3) + +inst_227: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x00e and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1ca and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1df and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x340e; op2val:0x41ca; +op3val:0x39df; valaddr_reg:x4; val_offset:606*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 606*FLEN/8, x5, x2, x3) + +inst_228: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x00e and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1ca and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1df and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x340e; op2val:0x41ca; +op3val:0x39df; valaddr_reg:x4; val_offset:609*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 609*FLEN/8, x5, x2, x3) + +inst_229: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x00e and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1ca and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1df and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x340e; op2val:0x41ca; +op3val:0x39df; valaddr_reg:x4; val_offset:612*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 612*FLEN/8, x5, x2, x3) + +inst_230: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x019 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2be and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2e9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3819; op2val:0x36be; +op3val:0x32e9; valaddr_reg:x4; val_offset:615*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 615*FLEN/8, x5, x2, x3) + +inst_231: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x019 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2be and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2e9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3819; op2val:0x36be; +op3val:0x32e9; valaddr_reg:x4; val_offset:618*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 618*FLEN/8, x5, x2, x3) + +inst_232: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x019 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2be and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2e9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3819; op2val:0x36be; +op3val:0x32e9; valaddr_reg:x4; val_offset:621*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 621*FLEN/8, x5, x2, x3) + +inst_233: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x019 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2be and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2e9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3819; op2val:0x36be; +op3val:0x32e9; valaddr_reg:x4; val_offset:624*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 624*FLEN/8, x5, x2, x3) + +inst_234: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x019 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2be and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2e9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3819; op2val:0x36be; +op3val:0x32e9; valaddr_reg:x4; val_offset:627*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 627*FLEN/8, x5, x2, x3) + +inst_235: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x29f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0b9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3d3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a9f; op2val:0x3cb9; +op3val:0x3bd3; valaddr_reg:x4; val_offset:630*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 630*FLEN/8, x5, x2, x3) + +inst_236: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x29f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0b9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3d3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a9f; op2val:0x3cb9; +op3val:0x3bd3; valaddr_reg:x4; val_offset:633*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 633*FLEN/8, x5, x2, x3) + +inst_237: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x29f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0b9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3d3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a9f; op2val:0x3cb9; +op3val:0x3bd3; valaddr_reg:x4; val_offset:636*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 636*FLEN/8, x5, x2, x3) + +inst_238: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x29f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0b9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3d3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a9f; op2val:0x3cb9; +op3val:0x3bd3; valaddr_reg:x4; val_offset:639*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 639*FLEN/8, x5, x2, x3) + +inst_239: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x29f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0b9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3d3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a9f; op2val:0x3cb9; +op3val:0x3bd3; valaddr_reg:x4; val_offset:642*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 642*FLEN/8, x5, x2, x3) + +inst_240: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x303 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x37e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x291 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b03; op2val:0x377e; +op3val:0x3691; valaddr_reg:x4; val_offset:645*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 645*FLEN/8, x5, x2, x3) + +inst_241: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x303 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x37e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x291 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b03; op2val:0x377e; +op3val:0x3691; valaddr_reg:x4; val_offset:648*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 648*FLEN/8, x5, x2, x3) + +inst_242: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x303 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x37e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x291 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b03; op2val:0x377e; +op3val:0x3691; valaddr_reg:x4; val_offset:651*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 651*FLEN/8, x5, x2, x3) + +inst_243: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x303 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x37e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x291 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b03; op2val:0x377e; +op3val:0x3691; valaddr_reg:x4; val_offset:654*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 654*FLEN/8, x5, x2, x3) + +inst_244: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x303 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x37e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x291 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b03; op2val:0x377e; +op3val:0x3691; valaddr_reg:x4; val_offset:657*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 657*FLEN/8, x5, x2, x3) + +inst_245: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0a7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1f3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x391c; op2val:0x3ca7; +op3val:0x39f3; valaddr_reg:x4; val_offset:660*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 660*FLEN/8, x5, x2, x3) + +inst_246: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0a7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1f3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x391c; op2val:0x3ca7; +op3val:0x39f3; valaddr_reg:x4; val_offset:663*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 663*FLEN/8, x5, x2, x3) + +inst_247: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0a7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1f3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x391c; op2val:0x3ca7; +op3val:0x39f3; valaddr_reg:x4; val_offset:666*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 666*FLEN/8, x5, x2, x3) + +inst_248: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0a7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1f3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x391c; op2val:0x3ca7; +op3val:0x39f3; valaddr_reg:x4; val_offset:669*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 669*FLEN/8, x5, x2, x3) + +inst_249: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0a7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1f3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x391c; op2val:0x3ca7; +op3val:0x39f3; valaddr_reg:x4; val_offset:672*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 672*FLEN/8, x5, x2, x3) + +inst_250: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x063 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x039 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0a3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3863; op2val:0x3039; +op3val:0x2ca3; valaddr_reg:x4; val_offset:675*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 675*FLEN/8, x5, x2, x3) + +inst_251: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x063 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x039 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0a3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3863; op2val:0x3039; +op3val:0x2ca3; valaddr_reg:x4; val_offset:678*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 678*FLEN/8, x5, x2, x3) + +inst_252: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x063 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x039 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0a3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3863; op2val:0x3039; +op3val:0x2ca3; valaddr_reg:x4; val_offset:681*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 681*FLEN/8, x5, x2, x3) + +inst_253: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x063 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x039 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0a3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3863; op2val:0x3039; +op3val:0x2ca3; valaddr_reg:x4; val_offset:684*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 684*FLEN/8, x5, x2, x3) + +inst_254: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x063 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x039 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0a3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3863; op2val:0x3039; +op3val:0x2ca3; valaddr_reg:x4; val_offset:687*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 687*FLEN/8, x5, x2, x3) + +inst_255: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1f6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x253 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0b7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39f6; op2val:0x3a53; +op3val:0x38b7; valaddr_reg:x4; val_offset:690*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 690*FLEN/8, x5, x2, x3) + +inst_256: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1f6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x253 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0b7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39f6; op2val:0x3a53; +op3val:0x38b7; valaddr_reg:x4; val_offset:693*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 693*FLEN/8, x5, x2, x3) + +inst_257: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1f6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x253 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0b7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39f6; op2val:0x3a53; +op3val:0x38b7; valaddr_reg:x4; val_offset:696*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 696*FLEN/8, x5, x2, x3) + +inst_258: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1f6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x253 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0b7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39f6; op2val:0x3a53; +op3val:0x38b7; valaddr_reg:x4; val_offset:699*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 699*FLEN/8, x5, x2, x3) + +inst_259: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1f6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x253 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0b7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39f6; op2val:0x3a53; +op3val:0x38b7; valaddr_reg:x4; val_offset:702*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 702*FLEN/8, x5, x2, x3) + +inst_260: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3ba and fs2 == 0 and fe2 == 0x10 and fm2 == 0x26c and fs3 == 0 and fe3 == 0x0d and fm3 == 0x234 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2fba; op2val:0x426c; +op3val:0x3634; valaddr_reg:x4; val_offset:705*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 705*FLEN/8, x5, x2, x3) + +inst_261: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3ba and fs2 == 0 and fe2 == 0x10 and fm2 == 0x26c and fs3 == 0 and fe3 == 0x0d and fm3 == 0x234 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2fba; op2val:0x426c; +op3val:0x3634; valaddr_reg:x4; val_offset:708*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 708*FLEN/8, x5, x2, x3) + +inst_262: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3ba and fs2 == 0 and fe2 == 0x10 and fm2 == 0x26c and fs3 == 0 and fe3 == 0x0d and fm3 == 0x234 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2fba; op2val:0x426c; +op3val:0x3634; valaddr_reg:x4; val_offset:711*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 711*FLEN/8, x5, x2, x3) + +inst_263: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3ba and fs2 == 0 and fe2 == 0x10 and fm2 == 0x26c and fs3 == 0 and fe3 == 0x0d and fm3 == 0x234 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2fba; op2val:0x426c; +op3val:0x3634; valaddr_reg:x4; val_offset:714*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 714*FLEN/8, x5, x2, x3) + +inst_264: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3ba and fs2 == 0 and fe2 == 0x10 and fm2 == 0x26c and fs3 == 0 and fe3 == 0x0d and fm3 == 0x234 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2fba; op2val:0x426c; +op3val:0x3634; valaddr_reg:x4; val_offset:717*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 717*FLEN/8, x5, x2, x3) + +inst_265: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1db and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1bd and fs3 == 0 and fe3 == 0x0e and fm3 == 0x033 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39db; op2val:0x39bd; +op3val:0x3833; valaddr_reg:x4; val_offset:720*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 720*FLEN/8, x5, x2, x3) + +inst_266: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1db and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1bd and fs3 == 0 and fe3 == 0x0e and fm3 == 0x033 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39db; op2val:0x39bd; +op3val:0x3833; valaddr_reg:x4; val_offset:723*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 723*FLEN/8, x5, x2, x3) + +inst_267: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1db and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1bd and fs3 == 0 and fe3 == 0x0e and fm3 == 0x033 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39db; op2val:0x39bd; +op3val:0x3833; valaddr_reg:x4; val_offset:726*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 726*FLEN/8, x5, x2, x3) + +inst_268: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1db and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1bd and fs3 == 0 and fe3 == 0x0e and fm3 == 0x033 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39db; op2val:0x39bd; +op3val:0x3833; valaddr_reg:x4; val_offset:729*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 729*FLEN/8, x5, x2, x3) + +inst_269: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1db and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1bd and fs3 == 0 and fe3 == 0x0e and fm3 == 0x033 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39db; op2val:0x39bd; +op3val:0x3833; valaddr_reg:x4; val_offset:732*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 732*FLEN/8, x5, x2, x3) + +inst_270: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x294 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2dc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x382c; op2val:0x3e94; +op3val:0x3adc; valaddr_reg:x4; val_offset:735*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 735*FLEN/8, x5, x2, x3) + +inst_271: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x294 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2dc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x382c; op2val:0x3e94; +op3val:0x3adc; valaddr_reg:x4; val_offset:738*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 738*FLEN/8, x5, x2, x3) + +inst_272: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x294 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2dc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x382c; op2val:0x3e94; +op3val:0x3adc; valaddr_reg:x4; val_offset:741*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 741*FLEN/8, x5, x2, x3) + +inst_273: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x294 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2dc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x382c; op2val:0x3e94; +op3val:0x3adc; valaddr_reg:x4; val_offset:744*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 744*FLEN/8, x5, x2, x3) + +inst_274: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x294 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2dc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x382c; op2val:0x3e94; +op3val:0x3adc; valaddr_reg:x4; val_offset:747*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 747*FLEN/8, x5, x2, x3) + +inst_275: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0fa and fs2 == 0 and fe2 == 0x0f and fm2 == 0x076 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x18e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38fa; op2val:0x3c76; +op3val:0x398e; valaddr_reg:x4; val_offset:750*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 750*FLEN/8, x5, x2, x3) + +inst_276: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0fa and fs2 == 0 and fe2 == 0x0f and fm2 == 0x076 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x18e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38fa; op2val:0x3c76; +op3val:0x398e; valaddr_reg:x4; val_offset:753*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 753*FLEN/8, x5, x2, x3) + +inst_277: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0fa and fs2 == 0 and fe2 == 0x0f and fm2 == 0x076 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x18e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38fa; op2val:0x3c76; +op3val:0x398e; valaddr_reg:x4; val_offset:756*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 756*FLEN/8, x5, x2, x3) + +inst_278: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0fa and fs2 == 0 and fe2 == 0x0f and fm2 == 0x076 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x18e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38fa; op2val:0x3c76; +op3val:0x398e; valaddr_reg:x4; val_offset:759*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 759*FLEN/8, x5, x2, x3) + +inst_279: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0fa and fs2 == 0 and fe2 == 0x0f and fm2 == 0x076 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x18e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38fa; op2val:0x3c76; +op3val:0x398e; valaddr_reg:x4; val_offset:762*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 762*FLEN/8, x5, x2, x3) + +inst_280: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x23f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x2ed and fs3 == 0 and fe3 == 0x0e and fm3 == 0x169 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x323f; op2val:0x42ed; +op3val:0x3969; valaddr_reg:x4; val_offset:765*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 765*FLEN/8, x5, x2, x3) + +inst_281: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x23f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x2ed and fs3 == 0 and fe3 == 0x0e and fm3 == 0x169 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x323f; op2val:0x42ed; +op3val:0x3969; valaddr_reg:x4; val_offset:768*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 768*FLEN/8, x5, x2, x3) + +inst_282: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x23f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x2ed and fs3 == 0 and fe3 == 0x0e and fm3 == 0x169 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x323f; op2val:0x42ed; +op3val:0x3969; valaddr_reg:x4; val_offset:771*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 771*FLEN/8, x5, x2, x3) + +inst_283: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x23f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x2ed and fs3 == 0 and fe3 == 0x0e and fm3 == 0x169 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x323f; op2val:0x42ed; +op3val:0x3969; valaddr_reg:x4; val_offset:774*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 774*FLEN/8, x5, x2, x3) + +inst_284: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x23f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x2ed and fs3 == 0 and fe3 == 0x0e and fm3 == 0x169 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x323f; op2val:0x42ed; +op3val:0x3969; valaddr_reg:x4; val_offset:777*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 777*FLEN/8, x5, x2, x3) + +inst_285: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x173 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x17d and fs3 == 0 and fe3 == 0x09 and fm3 == 0x37f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3573; op2val:0x2d7d; +op3val:0x277f; valaddr_reg:x4; val_offset:780*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 780*FLEN/8, x5, x2, x3) +RVTEST_SIGBASE(x2,signature_x2_2) + +inst_286: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x173 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x17d and fs3 == 0 and fe3 == 0x09 and fm3 == 0x37f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3573; op2val:0x2d7d; +op3val:0x277f; valaddr_reg:x4; val_offset:783*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 783*FLEN/8, x5, x2, x3) + +inst_287: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x173 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x17d and fs3 == 0 and fe3 == 0x09 and fm3 == 0x37f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3573; op2val:0x2d7d; +op3val:0x277f; valaddr_reg:x4; val_offset:786*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 786*FLEN/8, x5, x2, x3) + +inst_288: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x173 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x17d and fs3 == 0 and fe3 == 0x09 and fm3 == 0x37f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3573; op2val:0x2d7d; +op3val:0x277f; valaddr_reg:x4; val_offset:789*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 789*FLEN/8, x5, x2, x3) + +inst_289: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x173 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x17d and fs3 == 0 and fe3 == 0x09 and fm3 == 0x37f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3573; op2val:0x2d7d; +op3val:0x277f; valaddr_reg:x4; val_offset:792*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 792*FLEN/8, x5, x2, x3) + +inst_290: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0ed and fs2 == 0 and fe2 == 0x12 and fm2 == 0x00d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0fd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ced; op2val:0x480d; +op3val:0x38fd; valaddr_reg:x4; val_offset:795*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 795*FLEN/8, x5, x2, x3) + +inst_291: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0ed and fs2 == 0 and fe2 == 0x12 and fm2 == 0x00d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0fd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ced; op2val:0x480d; +op3val:0x38fd; valaddr_reg:x4; val_offset:798*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 798*FLEN/8, x5, x2, x3) + +inst_292: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0ed and fs2 == 0 and fe2 == 0x12 and fm2 == 0x00d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0fd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ced; op2val:0x480d; +op3val:0x38fd; valaddr_reg:x4; val_offset:801*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 801*FLEN/8, x5, x2, x3) + +inst_293: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0ed and fs2 == 0 and fe2 == 0x12 and fm2 == 0x00d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0fd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ced; op2val:0x480d; +op3val:0x38fd; valaddr_reg:x4; val_offset:804*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 804*FLEN/8, x5, x2, x3) + +inst_294: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0ed and fs2 == 0 and fe2 == 0x12 and fm2 == 0x00d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0fd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ced; op2val:0x480d; +op3val:0x38fd; valaddr_reg:x4; val_offset:807*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 807*FLEN/8, x5, x2, x3) + +inst_295: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x25a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2d9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x170 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x365a; op2val:0x3ed9; +op3val:0x3970; valaddr_reg:x4; val_offset:810*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 810*FLEN/8, x5, x2, x3) + +inst_296: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x25a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2d9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x170 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x365a; op2val:0x3ed9; +op3val:0x3970; valaddr_reg:x4; val_offset:813*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 813*FLEN/8, x5, x2, x3) + +inst_297: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x25a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2d9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x170 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x365a; op2val:0x3ed9; +op3val:0x3970; valaddr_reg:x4; val_offset:816*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 816*FLEN/8, x5, x2, x3) + +inst_298: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x25a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2d9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x170 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x365a; op2val:0x3ed9; +op3val:0x3970; valaddr_reg:x4; val_offset:819*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 819*FLEN/8, x5, x2, x3) + +inst_299: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x25a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2d9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x170 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x365a; op2val:0x3ed9; +op3val:0x3970; valaddr_reg:x4; val_offset:822*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 822*FLEN/8, x5, x2, x3) + +inst_300: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d0 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ce and fs3 == 0 and fe3 == 0x0e and fm3 == 0x018 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38d0; op2val:0x3ace; +op3val:0x3818; valaddr_reg:x4; val_offset:825*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 825*FLEN/8, x5, x2, x3) + +inst_301: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d0 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ce and fs3 == 0 and fe3 == 0x0e and fm3 == 0x018 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38d0; op2val:0x3ace; +op3val:0x3818; valaddr_reg:x4; val_offset:828*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 828*FLEN/8, x5, x2, x3) + +inst_302: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d0 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ce and fs3 == 0 and fe3 == 0x0e and fm3 == 0x018 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38d0; op2val:0x3ace; +op3val:0x3818; valaddr_reg:x4; val_offset:831*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 831*FLEN/8, x5, x2, x3) + +inst_303: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d0 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ce and fs3 == 0 and fe3 == 0x0e and fm3 == 0x018 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38d0; op2val:0x3ace; +op3val:0x3818; valaddr_reg:x4; val_offset:834*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 834*FLEN/8, x5, x2, x3) + +inst_304: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d0 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ce and fs3 == 0 and fe3 == 0x0e and fm3 == 0x018 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38d0; op2val:0x3ace; +op3val:0x3818; valaddr_reg:x4; val_offset:837*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 837*FLEN/8, x5, x2, x3) + +inst_305: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x29c and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0e8 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x329c; op2val:0x34e8; +op3val:0x2c0f; valaddr_reg:x4; val_offset:840*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 840*FLEN/8, x5, x2, x3) + +inst_306: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x29c and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0e8 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x00f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x329c; op2val:0x34e8; +op3val:0x2c0f; valaddr_reg:x4; val_offset:843*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 843*FLEN/8, x5, x2, x3) + +inst_307: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x29c and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0e8 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x00f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x329c; op2val:0x34e8; +op3val:0x2c0f; valaddr_reg:x4; val_offset:846*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 846*FLEN/8, x5, x2, x3) + +inst_308: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x29c and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0e8 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x00f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x329c; op2val:0x34e8; +op3val:0x2c0f; valaddr_reg:x4; val_offset:849*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 849*FLEN/8, x5, x2, x3) + +inst_309: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x29c and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0e8 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x00f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x329c; op2val:0x34e8; +op3val:0x2c0f; valaddr_reg:x4; val_offset:852*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 852*FLEN/8, x5, x2, x3) + +inst_310: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ac and fs2 == 0 and fe2 == 0x0f and fm2 == 0x19a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3f3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39ac; op2val:0x3d9a; +op3val:0x3bf3; valaddr_reg:x4; val_offset:855*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 855*FLEN/8, x5, x2, x3) + +inst_311: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ac and fs2 == 0 and fe2 == 0x0f and fm2 == 0x19a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3f3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39ac; op2val:0x3d9a; +op3val:0x3bf3; valaddr_reg:x4; val_offset:858*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 858*FLEN/8, x5, x2, x3) + +inst_312: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ac and fs2 == 0 and fe2 == 0x0f and fm2 == 0x19a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3f3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39ac; op2val:0x3d9a; +op3val:0x3bf3; valaddr_reg:x4; val_offset:861*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 861*FLEN/8, x5, x2, x3) + +inst_313: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ac and fs2 == 0 and fe2 == 0x0f and fm2 == 0x19a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3f3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39ac; op2val:0x3d9a; +op3val:0x3bf3; valaddr_reg:x4; val_offset:864*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 864*FLEN/8, x5, x2, x3) + +inst_314: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ac and fs2 == 0 and fe2 == 0x0f and fm2 == 0x19a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3f3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39ac; op2val:0x3d9a; +op3val:0x3bf3; valaddr_reg:x4; val_offset:867*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 867*FLEN/8, x5, x2, x3) + +inst_315: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x067 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2d9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x38b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3867; op2val:0x3ed9; +op3val:0x3b8b; valaddr_reg:x4; val_offset:870*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 870*FLEN/8, x5, x2, x3) + +inst_316: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x067 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2d9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x38b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3867; op2val:0x3ed9; +op3val:0x3b8b; valaddr_reg:x4; val_offset:873*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 873*FLEN/8, x5, x2, x3) + +inst_317: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x067 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2d9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x38b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3867; op2val:0x3ed9; +op3val:0x3b8b; valaddr_reg:x4; val_offset:876*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 876*FLEN/8, x5, x2, x3) + +inst_318: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x067 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2d9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x38b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3867; op2val:0x3ed9; +op3val:0x3b8b; valaddr_reg:x4; val_offset:879*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 879*FLEN/8, x5, x2, x3) + +inst_319: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x067 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2d9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x38b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3867; op2val:0x3ed9; +op3val:0x3b8b; valaddr_reg:x4; val_offset:882*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 882*FLEN/8, x5, x2, x3) + +inst_320: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c2 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x378 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x33f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bc2; op2val:0x3378; +op3val:0x333f; valaddr_reg:x4; val_offset:885*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 885*FLEN/8, x5, x2, x3) + +inst_321: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c2 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x378 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x33f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bc2; op2val:0x3378; +op3val:0x333f; valaddr_reg:x4; val_offset:888*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 888*FLEN/8, x5, x2, x3) + +inst_322: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c2 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x378 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x33f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bc2; op2val:0x3378; +op3val:0x333f; valaddr_reg:x4; val_offset:891*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 891*FLEN/8, x5, x2, x3) + +inst_323: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c2 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x378 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x33f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bc2; op2val:0x3378; +op3val:0x333f; valaddr_reg:x4; val_offset:894*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 894*FLEN/8, x5, x2, x3) + +inst_324: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c2 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x378 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x33f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bc2; op2val:0x3378; +op3val:0x333f; valaddr_reg:x4; val_offset:897*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 897*FLEN/8, x5, x2, x3) + +inst_325: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x112 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x081 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b1a; op2val:0x3512; +op3val:0x3481; valaddr_reg:x4; val_offset:900*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 900*FLEN/8, x5, x2, x3) + +inst_326: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x112 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x081 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b1a; op2val:0x3512; +op3val:0x3481; valaddr_reg:x4; val_offset:903*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 903*FLEN/8, x5, x2, x3) + +inst_327: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x112 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x081 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b1a; op2val:0x3512; +op3val:0x3481; valaddr_reg:x4; val_offset:906*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 906*FLEN/8, x5, x2, x3) + +inst_328: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x112 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x081 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b1a; op2val:0x3512; +op3val:0x3481; valaddr_reg:x4; val_offset:909*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 909*FLEN/8, x5, x2, x3) + +inst_329: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x112 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x081 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b1a; op2val:0x3512; +op3val:0x3481; valaddr_reg:x4; val_offset:912*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 912*FLEN/8, x5, x2, x3) + +inst_330: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11a and fs2 == 0 and fe2 == 0x0b and fm2 == 0x22c and fs3 == 0 and fe3 == 0x0a and fm3 == 0x3e3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x391a; op2val:0x2e2c; +op3val:0x2be3; valaddr_reg:x4; val_offset:915*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 915*FLEN/8, x5, x2, x3) + +inst_331: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11a and fs2 == 0 and fe2 == 0x0b and fm2 == 0x22c and fs3 == 0 and fe3 == 0x0a and fm3 == 0x3e3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x391a; op2val:0x2e2c; +op3val:0x2be3; valaddr_reg:x4; val_offset:918*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 918*FLEN/8, x5, x2, x3) + +inst_332: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11a and fs2 == 0 and fe2 == 0x0b and fm2 == 0x22c and fs3 == 0 and fe3 == 0x0a and fm3 == 0x3e3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x391a; op2val:0x2e2c; +op3val:0x2be3; valaddr_reg:x4; val_offset:921*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 921*FLEN/8, x5, x2, x3) + +inst_333: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11a and fs2 == 0 and fe2 == 0x0b and fm2 == 0x22c and fs3 == 0 and fe3 == 0x0a and fm3 == 0x3e3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x391a; op2val:0x2e2c; +op3val:0x2be3; valaddr_reg:x4; val_offset:924*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 924*FLEN/8, x5, x2, x3) + +inst_334: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11a and fs2 == 0 and fe2 == 0x0b and fm2 == 0x22c and fs3 == 0 and fe3 == 0x0a and fm3 == 0x3e3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x391a; op2val:0x2e2c; +op3val:0x2be3; valaddr_reg:x4; val_offset:927*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 927*FLEN/8, x5, x2, x3) + +inst_335: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0b0 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x265 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30b0; op2val:0x4665; +op3val:0x3b80; valaddr_reg:x4; val_offset:930*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 930*FLEN/8, x5, x2, x3) + +inst_336: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0b0 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x265 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x380 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30b0; op2val:0x4665; +op3val:0x3b80; valaddr_reg:x4; val_offset:933*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 933*FLEN/8, x5, x2, x3) + +inst_337: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0b0 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x265 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x380 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30b0; op2val:0x4665; +op3val:0x3b80; valaddr_reg:x4; val_offset:936*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 936*FLEN/8, x5, x2, x3) + +inst_338: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0b0 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x265 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x380 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30b0; op2val:0x4665; +op3val:0x3b80; valaddr_reg:x4; val_offset:939*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 939*FLEN/8, x5, x2, x3) + +inst_339: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0b0 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x265 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x380 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30b0; op2val:0x4665; +op3val:0x3b80; valaddr_reg:x4; val_offset:942*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 942*FLEN/8, x5, x2, x3) + +inst_340: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x275 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x02b and fs3 == 0 and fe3 == 0x0a and fm3 == 0x2bd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a75; op2val:0x2c2b; +op3val:0x2abd; valaddr_reg:x4; val_offset:945*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 945*FLEN/8, x5, x2, x3) + +inst_341: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x275 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x02b and fs3 == 0 and fe3 == 0x0a and fm3 == 0x2bd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a75; op2val:0x2c2b; +op3val:0x2abd; valaddr_reg:x4; val_offset:948*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 948*FLEN/8, x5, x2, x3) + +inst_342: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x275 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x02b and fs3 == 0 and fe3 == 0x0a and fm3 == 0x2bd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a75; op2val:0x2c2b; +op3val:0x2abd; valaddr_reg:x4; val_offset:951*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 951*FLEN/8, x5, x2, x3) + +inst_343: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x275 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x02b and fs3 == 0 and fe3 == 0x0a and fm3 == 0x2bd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a75; op2val:0x2c2b; +op3val:0x2abd; valaddr_reg:x4; val_offset:954*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 954*FLEN/8, x5, x2, x3) + +inst_344: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x275 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x02b and fs3 == 0 and fe3 == 0x0a and fm3 == 0x2bd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a75; op2val:0x2c2b; +op3val:0x2abd; valaddr_reg:x4; val_offset:957*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 957*FLEN/8, x5, x2, x3) + +inst_345: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x22f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1fa and fs3 == 0 and fe3 == 0x0e and fm3 == 0x09f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x362f; op2val:0x3dfa; +op3val:0x389f; valaddr_reg:x4; val_offset:960*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 960*FLEN/8, x5, x2, x3) + +inst_346: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x22f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1fa and fs3 == 0 and fe3 == 0x0e and fm3 == 0x09f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x362f; op2val:0x3dfa; +op3val:0x389f; valaddr_reg:x4; val_offset:963*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 963*FLEN/8, x5, x2, x3) + +inst_347: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x22f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1fa and fs3 == 0 and fe3 == 0x0e and fm3 == 0x09f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x362f; op2val:0x3dfa; +op3val:0x389f; valaddr_reg:x4; val_offset:966*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 966*FLEN/8, x5, x2, x3) + +inst_348: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x22f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1fa and fs3 == 0 and fe3 == 0x0e and fm3 == 0x09f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x362f; op2val:0x3dfa; +op3val:0x389f; valaddr_reg:x4; val_offset:969*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 969*FLEN/8, x5, x2, x3) + +inst_349: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x22f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1fa and fs3 == 0 and fe3 == 0x0e and fm3 == 0x09f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x362f; op2val:0x3dfa; +op3val:0x389f; valaddr_reg:x4; val_offset:972*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 972*FLEN/8, x5, x2, x3) + +inst_350: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2f7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d9 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32f7; op2val:0x3ad9; +op3val:0x31f8; valaddr_reg:x4; val_offset:975*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 975*FLEN/8, x5, x2, x3) + +inst_351: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2f7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d9 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1f8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32f7; op2val:0x3ad9; +op3val:0x31f8; valaddr_reg:x4; val_offset:978*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 978*FLEN/8, x5, x2, x3) + +inst_352: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2f7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d9 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1f8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32f7; op2val:0x3ad9; +op3val:0x31f8; valaddr_reg:x4; val_offset:981*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 981*FLEN/8, x5, x2, x3) + +inst_353: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2f7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d9 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1f8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32f7; op2val:0x3ad9; +op3val:0x31f8; valaddr_reg:x4; val_offset:984*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 984*FLEN/8, x5, x2, x3) + +inst_354: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2f7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d9 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1f8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32f7; op2val:0x3ad9; +op3val:0x31f8; valaddr_reg:x4; val_offset:987*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 987*FLEN/8, x5, x2, x3) + +inst_355: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x011 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x02d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3811; op2val:0x3c2d; +op3val:0x383f; valaddr_reg:x4; val_offset:990*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 990*FLEN/8, x5, x2, x3) + +inst_356: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x011 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x02d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x03f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3811; op2val:0x3c2d; +op3val:0x383f; valaddr_reg:x4; val_offset:993*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 993*FLEN/8, x5, x2, x3) + +inst_357: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x011 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x02d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x03f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3811; op2val:0x3c2d; +op3val:0x383f; valaddr_reg:x4; val_offset:996*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 996*FLEN/8, x5, x2, x3) + +inst_358: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x011 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x02d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x03f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3811; op2val:0x3c2d; +op3val:0x383f; valaddr_reg:x4; val_offset:999*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 999*FLEN/8, x5, x2, x3) + +inst_359: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x011 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x02d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x03f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3811; op2val:0x3c2d; +op3val:0x383f; valaddr_reg:x4; val_offset:1002*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1002*FLEN/8, x5, x2, x3) + +inst_360: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x332 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1ac and fs3 == 0 and fe3 == 0x0e and fm3 == 0x11a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b32; op2val:0x39ac; +op3val:0x391a; valaddr_reg:x4; val_offset:1005*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1005*FLEN/8, x5, x2, x3) + +inst_361: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x332 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1ac and fs3 == 0 and fe3 == 0x0e and fm3 == 0x11a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b32; op2val:0x39ac; +op3val:0x391a; valaddr_reg:x4; val_offset:1008*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1008*FLEN/8, x5, x2, x3) + +inst_362: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x332 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1ac and fs3 == 0 and fe3 == 0x0e and fm3 == 0x11a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b32; op2val:0x39ac; +op3val:0x391a; valaddr_reg:x4; val_offset:1011*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 1011*FLEN/8, x5, x2, x3) + +inst_363: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x332 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1ac and fs3 == 0 and fe3 == 0x0e and fm3 == 0x11a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b32; op2val:0x39ac; +op3val:0x391a; valaddr_reg:x4; val_offset:1014*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 1014*FLEN/8, x5, x2, x3) + +inst_364: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x332 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1ac and fs3 == 0 and fe3 == 0x0e and fm3 == 0x11a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b32; op2val:0x39ac; +op3val:0x391a; valaddr_reg:x4; val_offset:1017*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1017*FLEN/8, x5, x2, x3) + +inst_365: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d7 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x301 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1fd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ad7; op2val:0x3701; +op3val:0x35fd; valaddr_reg:x4; val_offset:1020*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1020*FLEN/8, x5, x2, x3) + +inst_366: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d7 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x301 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1fd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ad7; op2val:0x3701; +op3val:0x35fd; valaddr_reg:x4; val_offset:1023*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1023*FLEN/8, x5, x2, x3) + +inst_367: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d7 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x301 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1fd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ad7; op2val:0x3701; +op3val:0x35fd; valaddr_reg:x4; val_offset:1026*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 1026*FLEN/8, x5, x2, x3) + +inst_368: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d7 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x301 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1fd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ad7; op2val:0x3701; +op3val:0x35fd; valaddr_reg:x4; val_offset:1029*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 1029*FLEN/8, x5, x2, x3) + +inst_369: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d7 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x301 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1fd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ad7; op2val:0x3701; +op3val:0x35fd; valaddr_reg:x4; val_offset:1032*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1032*FLEN/8, x5, x2, x3) + +inst_370: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x24b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x059 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2d8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x364b; op2val:0x4059; +op3val:0x3ad8; valaddr_reg:x4; val_offset:1035*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1035*FLEN/8, x5, x2, x3) + +inst_371: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x24b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x059 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2d8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x364b; op2val:0x4059; +op3val:0x3ad8; valaddr_reg:x4; val_offset:1038*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1038*FLEN/8, x5, x2, x3) + +inst_372: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x24b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x059 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2d8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x364b; op2val:0x4059; +op3val:0x3ad8; valaddr_reg:x4; val_offset:1041*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 1041*FLEN/8, x5, x2, x3) + +inst_373: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x24b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x059 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2d8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x364b; op2val:0x4059; +op3val:0x3ad8; valaddr_reg:x4; val_offset:1044*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 1044*FLEN/8, x5, x2, x3) + +inst_374: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x24b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x059 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2d8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x364b; op2val:0x4059; +op3val:0x3ad8; valaddr_reg:x4; val_offset:1047*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1047*FLEN/8, x5, x2, x3) + +inst_375: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1f3 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0da and fs3 == 0 and fe3 == 0x0e and fm3 == 0x338 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35f3; op2val:0x40da; +op3val:0x3b38; valaddr_reg:x4; val_offset:1050*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1050*FLEN/8, x5, x2, x3) + +inst_376: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1f3 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0da and fs3 == 0 and fe3 == 0x0e and fm3 == 0x338 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35f3; op2val:0x40da; +op3val:0x3b38; valaddr_reg:x4; val_offset:1053*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1053*FLEN/8, x5, x2, x3) + +inst_377: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1f3 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0da and fs3 == 0 and fe3 == 0x0e and fm3 == 0x338 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35f3; op2val:0x40da; +op3val:0x3b38; valaddr_reg:x4; val_offset:1056*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 1056*FLEN/8, x5, x2, x3) + +inst_378: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1f3 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0da and fs3 == 0 and fe3 == 0x0e and fm3 == 0x338 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35f3; op2val:0x40da; +op3val:0x3b38; valaddr_reg:x4; val_offset:1059*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 1059*FLEN/8, x5, x2, x3) + +inst_379: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1f3 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0da and fs3 == 0 and fe3 == 0x0e and fm3 == 0x338 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35f3; op2val:0x40da; +op3val:0x3b38; valaddr_reg:x4; val_offset:1062*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1062*FLEN/8, x5, x2, x3) + +inst_380: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x328 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x256 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1ab and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b28; op2val:0x3656; +op3val:0x35ab; valaddr_reg:x4; val_offset:1065*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1065*FLEN/8, x5, x2, x3) + +inst_381: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x328 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x256 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1ab and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b28; op2val:0x3656; +op3val:0x35ab; valaddr_reg:x4; val_offset:1068*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1068*FLEN/8, x5, x2, x3) + +inst_382: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x328 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x256 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1ab and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b28; op2val:0x3656; +op3val:0x35ab; valaddr_reg:x4; val_offset:1071*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 1071*FLEN/8, x5, x2, x3) + +inst_383: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x328 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x256 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1ab and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b28; op2val:0x3656; +op3val:0x35ab; valaddr_reg:x4; val_offset:1074*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 1074*FLEN/8, x5, x2, x3) + +inst_384: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x328 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x256 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1ab and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b28; op2val:0x3656; +op3val:0x35ab; valaddr_reg:x4; val_offset:1077*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1077*FLEN/8, x5, x2, x3) + +inst_385: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x04c and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1fa and fs3 == 0 and fe3 == 0x0b and fm3 == 0x26e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x384c; op2val:0x31fa; +op3val:0x2e6e; valaddr_reg:x4; val_offset:1080*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1080*FLEN/8, x5, x2, x3) + +inst_386: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x04c and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1fa and fs3 == 0 and fe3 == 0x0b and fm3 == 0x26e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x384c; op2val:0x31fa; +op3val:0x2e6e; valaddr_reg:x4; val_offset:1083*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1083*FLEN/8, x5, x2, x3) + +inst_387: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x04c and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1fa and fs3 == 0 and fe3 == 0x0b and fm3 == 0x26e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x384c; op2val:0x31fa; +op3val:0x2e6e; valaddr_reg:x4; val_offset:1086*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 1086*FLEN/8, x5, x2, x3) + +inst_388: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x04c and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1fa and fs3 == 0 and fe3 == 0x0b and fm3 == 0x26e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x384c; op2val:0x31fa; +op3val:0x2e6e; valaddr_reg:x4; val_offset:1089*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 1089*FLEN/8, x5, x2, x3) + +inst_389: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x04c and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1fa and fs3 == 0 and fe3 == 0x0b and fm3 == 0x26e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x384c; op2val:0x31fa; +op3val:0x2e6e; valaddr_reg:x4; val_offset:1092*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1092*FLEN/8, x5, x2, x3) + +inst_390: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ee and fs2 == 0 and fe2 == 0x0e and fm2 == 0x271 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0c7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35ee; op2val:0x3a71; +op3val:0x34c7; valaddr_reg:x4; val_offset:1095*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1095*FLEN/8, x5, x2, x3) + +inst_391: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ee and fs2 == 0 and fe2 == 0x0e and fm2 == 0x271 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0c7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35ee; op2val:0x3a71; +op3val:0x34c7; valaddr_reg:x4; val_offset:1098*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1098*FLEN/8, x5, x2, x3) + +inst_392: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ee and fs2 == 0 and fe2 == 0x0e and fm2 == 0x271 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0c7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35ee; op2val:0x3a71; +op3val:0x34c7; valaddr_reg:x4; val_offset:1101*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 1101*FLEN/8, x5, x2, x3) + +inst_393: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ee and fs2 == 0 and fe2 == 0x0e and fm2 == 0x271 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0c7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35ee; op2val:0x3a71; +op3val:0x34c7; valaddr_reg:x4; val_offset:1104*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 1104*FLEN/8, x5, x2, x3) + +inst_394: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ee and fs2 == 0 and fe2 == 0x0e and fm2 == 0x271 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0c7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35ee; op2val:0x3a71; +op3val:0x34c7; valaddr_reg:x4; val_offset:1107*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1107*FLEN/8, x5, x2, x3) + +inst_395: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fb and fs2 == 0 and fe2 == 0x0c and fm2 == 0x222 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x15b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3afb; op2val:0x3222; +op3val:0x315b; valaddr_reg:x4; val_offset:1110*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1110*FLEN/8, x5, x2, x3) + +inst_396: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fb and fs2 == 0 and fe2 == 0x0c and fm2 == 0x222 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x15b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3afb; op2val:0x3222; +op3val:0x315b; valaddr_reg:x4; val_offset:1113*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1113*FLEN/8, x5, x2, x3) + +inst_397: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fb and fs2 == 0 and fe2 == 0x0c and fm2 == 0x222 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x15b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3afb; op2val:0x3222; +op3val:0x315b; valaddr_reg:x4; val_offset:1116*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 1116*FLEN/8, x5, x2, x3) + +inst_398: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fb and fs2 == 0 and fe2 == 0x0c and fm2 == 0x222 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x15b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3afb; op2val:0x3222; +op3val:0x315b; valaddr_reg:x4; val_offset:1119*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 1119*FLEN/8, x5, x2, x3) + +inst_399: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fb and fs2 == 0 and fe2 == 0x0c and fm2 == 0x222 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x15b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3afb; op2val:0x3222; +op3val:0x315b; valaddr_reg:x4; val_offset:1122*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1122*FLEN/8, x5, x2, x3) + +inst_400: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x354 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2aa and fs3 == 0 and fe3 == 0x0d and fm3 == 0x21c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b54; op2val:0x36aa; +op3val:0x361c; valaddr_reg:x4; val_offset:1125*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1125*FLEN/8, x5, x2, x3) + +inst_401: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x354 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2aa and fs3 == 0 and fe3 == 0x0d and fm3 == 0x21c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b54; op2val:0x36aa; +op3val:0x361c; valaddr_reg:x4; val_offset:1128*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1128*FLEN/8, x5, x2, x3) + +inst_402: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x354 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2aa and fs3 == 0 and fe3 == 0x0d and fm3 == 0x21c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b54; op2val:0x36aa; +op3val:0x361c; valaddr_reg:x4; val_offset:1131*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 1131*FLEN/8, x5, x2, x3) + +inst_403: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x354 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2aa and fs3 == 0 and fe3 == 0x0d and fm3 == 0x21c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b54; op2val:0x36aa; +op3val:0x361c; valaddr_reg:x4; val_offset:1134*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 1134*FLEN/8, x5, x2, x3) + +inst_404: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x354 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2aa and fs3 == 0 and fe3 == 0x0d and fm3 == 0x21c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b54; op2val:0x36aa; +op3val:0x361c; valaddr_reg:x4; val_offset:1137*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1137*FLEN/8, x5, x2, x3) + +inst_405: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1ac and fs2 == 0 and fe2 == 0x0f and fm2 == 0x029 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1e8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2dac; op2val:0x3c29; +op3val:0x2de8; valaddr_reg:x4; val_offset:1140*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1140*FLEN/8, x5, x2, x3) + +inst_406: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1ac and fs2 == 0 and fe2 == 0x0f and fm2 == 0x029 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1e8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2dac; op2val:0x3c29; +op3val:0x2de8; valaddr_reg:x4; val_offset:1143*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1143*FLEN/8, x5, x2, x3) + +inst_407: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1ac and fs2 == 0 and fe2 == 0x0f and fm2 == 0x029 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1e8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2dac; op2val:0x3c29; +op3val:0x2de8; valaddr_reg:x4; val_offset:1146*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 1146*FLEN/8, x5, x2, x3) + +inst_408: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1ac and fs2 == 0 and fe2 == 0x0f and fm2 == 0x029 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1e8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2dac; op2val:0x3c29; +op3val:0x2de8; valaddr_reg:x4; val_offset:1149*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 1149*FLEN/8, x5, x2, x3) + +inst_409: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1ac and fs2 == 0 and fe2 == 0x0f and fm2 == 0x029 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1e8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2dac; op2val:0x3c29; +op3val:0x2de8; valaddr_reg:x4; val_offset:1152*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1152*FLEN/8, x5, x2, x3) + +inst_410: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2d5 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x122 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x062 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ed5; op2val:0x4522; +op3val:0x3862; valaddr_reg:x4; val_offset:1155*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1155*FLEN/8, x5, x2, x3) + +inst_411: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2d5 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x122 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x062 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ed5; op2val:0x4522; +op3val:0x3862; valaddr_reg:x4; val_offset:1158*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1158*FLEN/8, x5, x2, x3) + +inst_412: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2d5 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x122 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x062 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ed5; op2val:0x4522; +op3val:0x3862; valaddr_reg:x4; val_offset:1161*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 1161*FLEN/8, x5, x2, x3) + +inst_413: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2d5 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x122 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x062 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ed5; op2val:0x4522; +op3val:0x3862; valaddr_reg:x4; val_offset:1164*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 1164*FLEN/8, x5, x2, x3) +RVTEST_SIGBASE(x2,signature_x2_3) + +inst_414: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2d5 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x122 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x062 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ed5; op2val:0x4522; +op3val:0x3862; valaddr_reg:x4; val_offset:1167*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1167*FLEN/8, x5, x2, x3) + +inst_415: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0e6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x173 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2ad and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34e6; op2val:0x3973; +op3val:0x32ad; valaddr_reg:x4; val_offset:1170*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1170*FLEN/8, x5, x2, x3) + +inst_416: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0e6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x173 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2ad and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34e6; op2val:0x3973; +op3val:0x32ad; valaddr_reg:x4; val_offset:1173*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1173*FLEN/8, x5, x2, x3) + +inst_417: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0e6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x173 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2ad and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34e6; op2val:0x3973; +op3val:0x32ad; valaddr_reg:x4; val_offset:1176*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 1176*FLEN/8, x5, x2, x3) + +inst_418: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0e6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x173 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2ad and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34e6; op2val:0x3973; +op3val:0x32ad; valaddr_reg:x4; val_offset:1179*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 1179*FLEN/8, x5, x2, x3) + +inst_419: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0e6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x173 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2ad and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34e6; op2val:0x3973; +op3val:0x32ad; valaddr_reg:x4; val_offset:1182*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1182*FLEN/8, x5, x2, x3) + +inst_420: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2e7 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x032 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x33f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ae7; op2val:0x2c32; +op3val:0x2b3f; valaddr_reg:x4; val_offset:1185*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1185*FLEN/8, x5, x2, x3) + +inst_421: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2e7 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x032 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x33f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ae7; op2val:0x2c32; +op3val:0x2b3f; valaddr_reg:x4; val_offset:1188*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1188*FLEN/8, x5, x2, x3) + +inst_422: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2e7 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x032 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x33f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ae7; op2val:0x2c32; +op3val:0x2b3f; valaddr_reg:x4; val_offset:1191*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 1191*FLEN/8, x5, x2, x3) + +inst_423: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2e7 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x032 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x33f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ae7; op2val:0x2c32; +op3val:0x2b3f; valaddr_reg:x4; val_offset:1194*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 1194*FLEN/8, x5, x2, x3) + +inst_424: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2e7 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x032 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x33f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ae7; op2val:0x2c32; +op3val:0x2b3f; valaddr_reg:x4; val_offset:1197*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1197*FLEN/8, x5, x2, x3) + +inst_425: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1d7 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x220 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x079 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2dd7; op2val:0x4620; +op3val:0x3879; valaddr_reg:x4; val_offset:1200*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1200*FLEN/8, x5, x2, x3) + +inst_426: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1d7 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x220 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x079 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2dd7; op2val:0x4620; +op3val:0x3879; valaddr_reg:x4; val_offset:1203*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1203*FLEN/8, x5, x2, x3) + +inst_427: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1d7 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x220 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x079 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2dd7; op2val:0x4620; +op3val:0x3879; valaddr_reg:x4; val_offset:1206*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 1206*FLEN/8, x5, x2, x3) + +inst_428: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1d7 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x220 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x079 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2dd7; op2val:0x4620; +op3val:0x3879; valaddr_reg:x4; val_offset:1209*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 1209*FLEN/8, x5, x2, x3) + +inst_429: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1d7 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x220 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x079 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2dd7; op2val:0x4620; +op3val:0x3879; valaddr_reg:x4; val_offset:1212*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1212*FLEN/8, x5, x2, x3) + +inst_430: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x316 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0fd and fs3 == 0 and fe3 == 0x0e and fm3 == 0x06c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3316; op2val:0x40fd; +op3val:0x386c; valaddr_reg:x4; val_offset:1215*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1215*FLEN/8, x5, x2, x3) + +inst_431: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x316 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0fd and fs3 == 0 and fe3 == 0x0e and fm3 == 0x06c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3316; op2val:0x40fd; +op3val:0x386c; valaddr_reg:x4; val_offset:1218*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1218*FLEN/8, x5, x2, x3) + +inst_432: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x316 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0fd and fs3 == 0 and fe3 == 0x0e and fm3 == 0x06c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3316; op2val:0x40fd; +op3val:0x386c; valaddr_reg:x4; val_offset:1221*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 1221*FLEN/8, x5, x2, x3) + +inst_433: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x316 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0fd and fs3 == 0 and fe3 == 0x0e and fm3 == 0x06c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3316; op2val:0x40fd; +op3val:0x386c; valaddr_reg:x4; val_offset:1224*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 1224*FLEN/8, x5, x2, x3) + +inst_434: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x316 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0fd and fs3 == 0 and fe3 == 0x0e and fm3 == 0x06c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3316; op2val:0x40fd; +op3val:0x386c; valaddr_reg:x4; val_offset:1227*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1227*FLEN/8, x5, x2, x3) + +inst_435: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1c9 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x25b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x099 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39c9; op2val:0x365b; +op3val:0x3499; valaddr_reg:x4; val_offset:1230*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1230*FLEN/8, x5, x2, x3) + +inst_436: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1c9 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x25b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x099 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39c9; op2val:0x365b; +op3val:0x3499; valaddr_reg:x4; val_offset:1233*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1233*FLEN/8, x5, x2, x3) + +inst_437: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1c9 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x25b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x099 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39c9; op2val:0x365b; +op3val:0x3499; valaddr_reg:x4; val_offset:1236*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 1236*FLEN/8, x5, x2, x3) + +inst_438: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1c9 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x25b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x099 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39c9; op2val:0x365b; +op3val:0x3499; valaddr_reg:x4; val_offset:1239*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 1239*FLEN/8, x5, x2, x3) + +inst_439: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1c9 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x25b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x099 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39c9; op2val:0x365b; +op3val:0x3499; valaddr_reg:x4; val_offset:1242*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1242*FLEN/8, x5, x2, x3) + +inst_440: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x37d and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2d3 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x265 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b7d; op2val:0x32d3; +op3val:0x3265; valaddr_reg:x4; val_offset:1245*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1245*FLEN/8, x5, x2, x3) + +inst_441: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x37d and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2d3 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x265 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b7d; op2val:0x32d3; +op3val:0x3265; valaddr_reg:x4; val_offset:1248*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1248*FLEN/8, x5, x2, x3) + +inst_442: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x37d and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2d3 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x265 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b7d; op2val:0x32d3; +op3val:0x3265; valaddr_reg:x4; val_offset:1251*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 1251*FLEN/8, x5, x2, x3) + +inst_443: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x37d and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2d3 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x265 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b7d; op2val:0x32d3; +op3val:0x3265; valaddr_reg:x4; val_offset:1254*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 1254*FLEN/8, x5, x2, x3) + +inst_444: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x37d and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2d3 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x265 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b7d; op2val:0x32d3; +op3val:0x3265; valaddr_reg:x4; val_offset:1257*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1257*FLEN/8, x5, x2, x3) + +inst_445: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x19f and fs2 == 0 and fe2 == 0x14 and fm2 == 0x010 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1b6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x259f; op2val:0x5010; +op3val:0x39b6; valaddr_reg:x4; val_offset:1260*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1260*FLEN/8, x5, x2, x3) + +inst_446: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x19f and fs2 == 0 and fe2 == 0x14 and fm2 == 0x010 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1b6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x259f; op2val:0x5010; +op3val:0x39b6; valaddr_reg:x4; val_offset:1263*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1263*FLEN/8, x5, x2, x3) + +inst_447: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x19f and fs2 == 0 and fe2 == 0x14 and fm2 == 0x010 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1b6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x259f; op2val:0x5010; +op3val:0x39b6; valaddr_reg:x4; val_offset:1266*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 1266*FLEN/8, x5, x2, x3) + +inst_448: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x19f and fs2 == 0 and fe2 == 0x14 and fm2 == 0x010 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1b6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x259f; op2val:0x5010; +op3val:0x39b6; valaddr_reg:x4; val_offset:1269*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 1269*FLEN/8, x5, x2, x3) + +inst_449: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x19f and fs2 == 0 and fe2 == 0x14 and fm2 == 0x010 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1b6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x259f; op2val:0x5010; +op3val:0x39b6; valaddr_reg:x4; val_offset:1272*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1272*FLEN/8, x5, x2, x3) + +inst_450: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x3ba and fs2 == 0 and fe2 == 0x12 and fm2 == 0x396 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x354 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2bba; op2val:0x4b96; +op3val:0x3b54; valaddr_reg:x4; val_offset:1275*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1275*FLEN/8, x5, x2, x3) + +inst_451: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x3ba and fs2 == 0 and fe2 == 0x12 and fm2 == 0x396 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x354 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2bba; op2val:0x4b96; +op3val:0x3b54; valaddr_reg:x4; val_offset:1278*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1278*FLEN/8, x5, x2, x3) + +inst_452: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x3ba and fs2 == 0 and fe2 == 0x12 and fm2 == 0x396 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x354 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2bba; op2val:0x4b96; +op3val:0x3b54; valaddr_reg:x4; val_offset:1281*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 1281*FLEN/8, x5, x2, x3) + +inst_453: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x3ba and fs2 == 0 and fe2 == 0x12 and fm2 == 0x396 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x354 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2bba; op2val:0x4b96; +op3val:0x3b54; valaddr_reg:x4; val_offset:1284*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 1284*FLEN/8, x5, x2, x3) + +inst_454: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x3ba and fs2 == 0 and fe2 == 0x12 and fm2 == 0x396 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x354 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2bba; op2val:0x4b96; +op3val:0x3b54; valaddr_reg:x4; val_offset:1287*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1287*FLEN/8, x5, x2, x3) + +inst_455: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x08a and fs2 == 0 and fe2 == 0x11 and fm2 == 0x112 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1c2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x308a; op2val:0x4512; +op3val:0x39c2; valaddr_reg:x4; val_offset:1290*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1290*FLEN/8, x5, x2, x3) + +inst_456: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x08a and fs2 == 0 and fe2 == 0x11 and fm2 == 0x112 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1c2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x308a; op2val:0x4512; +op3val:0x39c2; valaddr_reg:x4; val_offset:1293*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1293*FLEN/8, x5, x2, x3) + +inst_457: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x08a and fs2 == 0 and fe2 == 0x11 and fm2 == 0x112 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1c2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x308a; op2val:0x4512; +op3val:0x39c2; valaddr_reg:x4; val_offset:1296*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 1296*FLEN/8, x5, x2, x3) + +inst_458: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x08a and fs2 == 0 and fe2 == 0x11 and fm2 == 0x112 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1c2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x308a; op2val:0x4512; +op3val:0x39c2; valaddr_reg:x4; val_offset:1299*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 1299*FLEN/8, x5, x2, x3) + +inst_459: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x08a and fs2 == 0 and fe2 == 0x11 and fm2 == 0x112 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1c2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x308a; op2val:0x4512; +op3val:0x39c2; valaddr_reg:x4; val_offset:1302*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1302*FLEN/8, x5, x2, x3) + +inst_460: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x054 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x035 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2854; op2val:0x4c35; +op3val:0x388d; valaddr_reg:x4; val_offset:1305*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1305*FLEN/8, x5, x2, x3) + +inst_461: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x054 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x035 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2854; op2val:0x4c35; +op3val:0x388d; valaddr_reg:x4; val_offset:1308*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1308*FLEN/8, x5, x2, x3) + +inst_462: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x054 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x035 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2854; op2val:0x4c35; +op3val:0x388d; valaddr_reg:x4; val_offset:1311*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 1311*FLEN/8, x5, x2, x3) + +inst_463: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x054 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x035 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2854; op2val:0x4c35; +op3val:0x388d; valaddr_reg:x4; val_offset:1314*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 1314*FLEN/8, x5, x2, x3) + +inst_464: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x054 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x035 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2854; op2val:0x4c35; +op3val:0x388d; valaddr_reg:x4; val_offset:1317*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1317*FLEN/8, x5, x2, x3) + +inst_465: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0fb and fs2 == 0 and fe2 == 0x12 and fm2 == 0x237 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3be and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2cfb; op2val:0x4a37; +op3val:0x3bbe; valaddr_reg:x4; val_offset:1320*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1320*FLEN/8, x5, x2, x3) + +inst_466: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0fb and fs2 == 0 and fe2 == 0x12 and fm2 == 0x237 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3be and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2cfb; op2val:0x4a37; +op3val:0x3bbe; valaddr_reg:x4; val_offset:1323*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1323*FLEN/8, x5, x2, x3) + +inst_467: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0fb and fs2 == 0 and fe2 == 0x12 and fm2 == 0x237 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3be and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2cfb; op2val:0x4a37; +op3val:0x3bbe; valaddr_reg:x4; val_offset:1326*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 1326*FLEN/8, x5, x2, x3) + +inst_468: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0fb and fs2 == 0 and fe2 == 0x12 and fm2 == 0x237 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3be and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2cfb; op2val:0x4a37; +op3val:0x3bbe; valaddr_reg:x4; val_offset:1329*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 1329*FLEN/8, x5, x2, x3) + +inst_469: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0fb and fs2 == 0 and fe2 == 0x12 and fm2 == 0x237 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3be and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2cfb; op2val:0x4a37; +op3val:0x3bbe; valaddr_reg:x4; val_offset:1332*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1332*FLEN/8, x5, x2, x3) + +inst_470: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x350 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x26d and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b50; op2val:0x326d; +op3val:0x31e0; valaddr_reg:x4; val_offset:1335*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1335*FLEN/8, x5, x2, x3) + +inst_471: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x350 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x26d and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1e0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b50; op2val:0x326d; +op3val:0x31e0; valaddr_reg:x4; val_offset:1338*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1338*FLEN/8, x5, x2, x3) + +inst_472: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x350 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x26d and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1e0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b50; op2val:0x326d; +op3val:0x31e0; valaddr_reg:x4; val_offset:1341*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 1341*FLEN/8, x5, x2, x3) + +inst_473: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x350 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x26d and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1e0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b50; op2val:0x326d; +op3val:0x31e0; valaddr_reg:x4; val_offset:1344*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 1344*FLEN/8, x5, x2, x3) + +inst_474: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x350 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x26d and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1e0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b50; op2val:0x326d; +op3val:0x31e0; valaddr_reg:x4; val_offset:1347*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1347*FLEN/8, x5, x2, x3) + +inst_475: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1c8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x123 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x36e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35c8; op2val:0x3d23; +op3val:0x376e; valaddr_reg:x4; val_offset:1350*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1350*FLEN/8, x5, x2, x3) + +inst_476: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1c8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x123 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x36e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35c8; op2val:0x3d23; +op3val:0x376e; valaddr_reg:x4; val_offset:1353*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1353*FLEN/8, x5, x2, x3) + +inst_477: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1c8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x123 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x36e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35c8; op2val:0x3d23; +op3val:0x376e; valaddr_reg:x4; val_offset:1356*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 1356*FLEN/8, x5, x2, x3) + +inst_478: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1c8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x123 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x36e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35c8; op2val:0x3d23; +op3val:0x376e; valaddr_reg:x4; val_offset:1359*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 1359*FLEN/8, x5, x2, x3) + +inst_479: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1c8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x123 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x36e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35c8; op2val:0x3d23; +op3val:0x376e; valaddr_reg:x4; val_offset:1362*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1362*FLEN/8, x5, x2, x3) + +inst_480: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3bd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x29d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bbd; op2val:0x3ad6; +op3val:0x3a9d; valaddr_reg:x4; val_offset:1365*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1365*FLEN/8, x5, x2, x3) + +inst_481: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3bd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x29d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bbd; op2val:0x3ad6; +op3val:0x3a9d; valaddr_reg:x4; val_offset:1368*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1368*FLEN/8, x5, x2, x3) + +inst_482: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3bd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x29d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bbd; op2val:0x3ad6; +op3val:0x3a9d; valaddr_reg:x4; val_offset:1371*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 1371*FLEN/8, x5, x2, x3) + +inst_483: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3bd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x29d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bbd; op2val:0x3ad6; +op3val:0x3a9d; valaddr_reg:x4; val_offset:1374*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 1374*FLEN/8, x5, x2, x3) + +inst_484: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3bd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x29d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bbd; op2val:0x3ad6; +op3val:0x3a9d; valaddr_reg:x4; val_offset:1377*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1377*FLEN/8, x5, x2, x3) + +inst_485: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x109 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x205 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x395 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3909; op2val:0x3e05; +op3val:0x3b95; valaddr_reg:x4; val_offset:1380*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1380*FLEN/8, x5, x2, x3) + +inst_486: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x109 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x205 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x395 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3909; op2val:0x3e05; +op3val:0x3b95; valaddr_reg:x4; val_offset:1383*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1383*FLEN/8, x5, x2, x3) + +inst_487: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x109 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x205 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x395 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3909; op2val:0x3e05; +op3val:0x3b95; valaddr_reg:x4; val_offset:1386*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 1386*FLEN/8, x5, x2, x3) + +inst_488: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x109 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x205 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x395 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3909; op2val:0x3e05; +op3val:0x3b95; valaddr_reg:x4; val_offset:1389*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 1389*FLEN/8, x5, x2, x3) + +inst_489: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x109 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x205 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x395 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3909; op2val:0x3e05; +op3val:0x3b95; valaddr_reg:x4; val_offset:1392*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1392*FLEN/8, x5, x2, x3) + +inst_490: +// fs1 == 0 and fe1 == 0x07 and fm1 == 0x32b and fs2 == 0 and fe2 == 0x14 and fm2 == 0x031 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x383 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1f2b; op2val:0x5031; +op3val:0x3383; valaddr_reg:x4; val_offset:1395*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1395*FLEN/8, x5, x2, x3) + +inst_491: +// fs1 == 0 and fe1 == 0x07 and fm1 == 0x32b and fs2 == 0 and fe2 == 0x14 and fm2 == 0x031 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x383 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1f2b; op2val:0x5031; +op3val:0x3383; valaddr_reg:x4; val_offset:1398*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1398*FLEN/8, x5, x2, x3) + +inst_492: +// fs1 == 0 and fe1 == 0x07 and fm1 == 0x32b and fs2 == 0 and fe2 == 0x14 and fm2 == 0x031 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x383 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1f2b; op2val:0x5031; +op3val:0x3383; valaddr_reg:x4; val_offset:1401*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 1401*FLEN/8, x5, x2, x3) + +inst_493: +// fs1 == 0 and fe1 == 0x07 and fm1 == 0x32b and fs2 == 0 and fe2 == 0x14 and fm2 == 0x031 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x383 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1f2b; op2val:0x5031; +op3val:0x3383; valaddr_reg:x4; val_offset:1404*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 1404*FLEN/8, x5, x2, x3) + +inst_494: +// fs1 == 0 and fe1 == 0x07 and fm1 == 0x32b and fs2 == 0 and fe2 == 0x14 and fm2 == 0x031 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x383 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1f2b; op2val:0x5031; +op3val:0x3383; valaddr_reg:x4; val_offset:1407*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1407*FLEN/8, x5, x2, x3) + +inst_495: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x26e and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1f5 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0ca and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2a6e; op2val:0x45f5; +op3val:0x34ca; valaddr_reg:x4; val_offset:1410*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1410*FLEN/8, x5, x2, x3) + +inst_496: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x26e and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1f5 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0ca and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2a6e; op2val:0x45f5; +op3val:0x34ca; valaddr_reg:x4; val_offset:1413*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1413*FLEN/8, x5, x2, x3) + +inst_497: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x26e and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1f5 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0ca and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2a6e; op2val:0x45f5; +op3val:0x34ca; valaddr_reg:x4; val_offset:1416*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 1416*FLEN/8, x5, x2, x3) + +inst_498: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x26e and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1f5 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0ca and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2a6e; op2val:0x45f5; +op3val:0x34ca; valaddr_reg:x4; val_offset:1419*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 1419*FLEN/8, x5, x2, x3) + +inst_499: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x26e and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1f5 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0ca and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2a6e; op2val:0x45f5; +op3val:0x34ca; valaddr_reg:x4; val_offset:1422*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1422*FLEN/8, x5, x2, x3) + +inst_500: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x140 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x19e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x361 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3940; op2val:0x3d9e; +op3val:0x3b61; valaddr_reg:x4; val_offset:1425*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1425*FLEN/8, x5, x2, x3) + +inst_501: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x140 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x19e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x361 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3940; op2val:0x3d9e; +op3val:0x3b61; valaddr_reg:x4; val_offset:1428*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1428*FLEN/8, x5, x2, x3) + +inst_502: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x140 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x19e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x361 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3940; op2val:0x3d9e; +op3val:0x3b61; valaddr_reg:x4; val_offset:1431*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 1431*FLEN/8, x5, x2, x3) + +inst_503: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x140 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x19e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x361 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3940; op2val:0x3d9e; +op3val:0x3b61; valaddr_reg:x4; val_offset:1434*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 1434*FLEN/8, x5, x2, x3) + +inst_504: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x140 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x19e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x361 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3940; op2val:0x3d9e; +op3val:0x3b61; valaddr_reg:x4; val_offset:1437*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1437*FLEN/8, x5, x2, x3) + +inst_505: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x04b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x299 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x316 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x344b; op2val:0x4299; +op3val:0x3b16; valaddr_reg:x4; val_offset:1440*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1440*FLEN/8, x5, x2, x3) + +inst_506: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x04b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x299 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x316 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x344b; op2val:0x4299; +op3val:0x3b16; valaddr_reg:x4; val_offset:1443*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1443*FLEN/8, x5, x2, x3) + +inst_507: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x04b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x299 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x316 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x344b; op2val:0x4299; +op3val:0x3b16; valaddr_reg:x4; val_offset:1446*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 1446*FLEN/8, x5, x2, x3) + +inst_508: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x04b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x299 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x316 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x344b; op2val:0x4299; +op3val:0x3b16; valaddr_reg:x4; val_offset:1449*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 1449*FLEN/8, x5, x2, x3) + +inst_509: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x04b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x299 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x316 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x344b; op2val:0x4299; +op3val:0x3b16; valaddr_reg:x4; val_offset:1452*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1452*FLEN/8, x5, x2, x3) + +inst_510: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x33f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0bb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x049 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x373f; op2val:0x3cbb; +op3val:0x3849; valaddr_reg:x4; val_offset:1455*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1455*FLEN/8, x5, x2, x3) + +inst_511: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x33f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0bb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x049 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x373f; op2val:0x3cbb; +op3val:0x3849; valaddr_reg:x4; val_offset:1458*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1458*FLEN/8, x5, x2, x3) + +inst_512: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x33f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0bb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x049 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x373f; op2val:0x3cbb; +op3val:0x3849; valaddr_reg:x4; val_offset:1461*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 1461*FLEN/8, x5, x2, x3) + +inst_513: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x33f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0bb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x049 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x373f; op2val:0x3cbb; +op3val:0x3849; valaddr_reg:x4; val_offset:1464*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 1464*FLEN/8, x5, x2, x3) + +inst_514: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x33f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0bb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x049 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x373f; op2val:0x3cbb; +op3val:0x3849; valaddr_reg:x4; val_offset:1467*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1467*FLEN/8, x5, x2, x3) + +inst_515: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x00b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x351 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x366 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x380b; op2val:0x3f51; +op3val:0x3b66; valaddr_reg:x4; val_offset:1470*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1470*FLEN/8, x5, x2, x3) + +inst_516: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x00b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x351 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x366 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x380b; op2val:0x3f51; +op3val:0x3b66; valaddr_reg:x4; val_offset:1473*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1473*FLEN/8, x5, x2, x3) + +inst_517: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x00b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x351 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x366 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x380b; op2val:0x3f51; +op3val:0x3b66; valaddr_reg:x4; val_offset:1476*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 1476*FLEN/8, x5, x2, x3) + +inst_518: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x00b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x351 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x366 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x380b; op2val:0x3f51; +op3val:0x3b66; valaddr_reg:x4; val_offset:1479*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 1479*FLEN/8, x5, x2, x3) + +inst_519: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x00b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x351 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x366 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x380b; op2val:0x3f51; +op3val:0x3b66; valaddr_reg:x4; val_offset:1482*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1482*FLEN/8, x5, x2, x3) + +inst_520: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x368 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x024 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3ad and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b68; op2val:0x3824; +op3val:0x37ad; valaddr_reg:x4; val_offset:1485*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1485*FLEN/8, x5, x2, x3) + +inst_521: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x368 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x024 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3ad and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b68; op2val:0x3824; +op3val:0x37ad; valaddr_reg:x4; val_offset:1488*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1488*FLEN/8, x5, x2, x3) + +inst_522: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x368 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x024 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3ad and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b68; op2val:0x3824; +op3val:0x37ad; valaddr_reg:x4; val_offset:1491*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 1491*FLEN/8, x5, x2, x3) + +inst_523: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x368 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x024 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3ad and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b68; op2val:0x3824; +op3val:0x37ad; valaddr_reg:x4; val_offset:1494*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 1494*FLEN/8, x5, x2, x3) + +inst_524: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x368 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x024 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3ad and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b68; op2val:0x3824; +op3val:0x37ad; valaddr_reg:x4; val_offset:1497*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1497*FLEN/8, x5, x2, x3) + +inst_525: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c1 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3d4 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x397 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bc1; op2val:0x37d4; +op3val:0x3797; valaddr_reg:x4; val_offset:1500*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1500*FLEN/8, x5, x2, x3) + +inst_526: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c1 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3d4 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x397 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bc1; op2val:0x37d4; +op3val:0x3797; valaddr_reg:x4; val_offset:1503*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1503*FLEN/8, x5, x2, x3) + +inst_527: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c1 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3d4 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x397 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bc1; op2val:0x37d4; +op3val:0x3797; valaddr_reg:x4; val_offset:1506*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 1506*FLEN/8, x5, x2, x3) + +inst_528: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c1 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3d4 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x397 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bc1; op2val:0x37d4; +op3val:0x3797; valaddr_reg:x4; val_offset:1509*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 1509*FLEN/8, x5, x2, x3) + +inst_529: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c1 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3d4 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x397 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bc1; op2val:0x37d4; +op3val:0x3797; valaddr_reg:x4; val_offset:1512*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1512*FLEN/8, x5, x2, x3) + +inst_530: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2cc and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2c3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1bf and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3acc; op2val:0x3ac3; +op3val:0x39bf; valaddr_reg:x4; val_offset:1515*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1515*FLEN/8, x5, x2, x3) + +inst_531: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2cc and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2c3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1bf and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3acc; op2val:0x3ac3; +op3val:0x39bf; valaddr_reg:x4; val_offset:1518*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1518*FLEN/8, x5, x2, x3) + +inst_532: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2cc and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2c3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1bf and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3acc; op2val:0x3ac3; +op3val:0x39bf; valaddr_reg:x4; val_offset:1521*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 1521*FLEN/8, x5, x2, x3) + +inst_533: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2cc and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2c3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1bf and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3acc; op2val:0x3ac3; +op3val:0x39bf; valaddr_reg:x4; val_offset:1524*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 1524*FLEN/8, x5, x2, x3) + +inst_534: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2cc and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2c3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1bf and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3acc; op2val:0x3ac3; +op3val:0x39bf; valaddr_reg:x4; val_offset:1527*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1527*FLEN/8, x5, x2, x3) + +inst_535: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ca and fs2 == 0 and fe2 == 0x0e and fm2 == 0x010 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2e7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aca; op2val:0x3810; +op3val:0x36e7; valaddr_reg:x4; val_offset:1530*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1530*FLEN/8, x5, x2, x3) + +inst_536: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ca and fs2 == 0 and fe2 == 0x0e and fm2 == 0x010 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2e7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aca; op2val:0x3810; +op3val:0x36e7; valaddr_reg:x4; val_offset:1533*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1533*FLEN/8, x5, x2, x3) + +inst_537: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ca and fs2 == 0 and fe2 == 0x0e and fm2 == 0x010 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2e7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aca; op2val:0x3810; +op3val:0x36e7; valaddr_reg:x4; val_offset:1536*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 1536*FLEN/8, x5, x2, x3) + +inst_538: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ca and fs2 == 0 and fe2 == 0x0e and fm2 == 0x010 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2e7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aca; op2val:0x3810; +op3val:0x36e7; valaddr_reg:x4; val_offset:1539*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 1539*FLEN/8, x5, x2, x3) + +inst_539: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ca and fs2 == 0 and fe2 == 0x0e and fm2 == 0x010 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2e7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aca; op2val:0x3810; +op3val:0x36e7; valaddr_reg:x4; val_offset:1542*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1542*FLEN/8, x5, x2, x3) + +inst_540: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x114 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x237 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38e4; op2val:0x3d14; +op3val:0x3a37; valaddr_reg:x4; val_offset:1545*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1545*FLEN/8, x5, x2, x3) + +inst_541: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x114 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x237 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38e4; op2val:0x3d14; +op3val:0x3a37; valaddr_reg:x4; val_offset:1548*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1548*FLEN/8, x5, x2, x3) +RVTEST_SIGBASE(x2,signature_x2_4) + +inst_542: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x114 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x237 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38e4; op2val:0x3d14; +op3val:0x3a37; valaddr_reg:x4; val_offset:1551*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 1551*FLEN/8, x5, x2, x3) + +inst_543: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x114 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x237 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38e4; op2val:0x3d14; +op3val:0x3a37; valaddr_reg:x4; val_offset:1554*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 1554*FLEN/8, x5, x2, x3) + +inst_544: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x114 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x237 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38e4; op2val:0x3d14; +op3val:0x3a37; valaddr_reg:x4; val_offset:1557*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1557*FLEN/8, x5, x2, x3) + +inst_545: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x07a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2f9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a3a; op2val:0x387a; +op3val:0x36f9; valaddr_reg:x4; val_offset:1560*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1560*FLEN/8, x5, x2, x3) + +inst_546: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x07a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2f9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a3a; op2val:0x387a; +op3val:0x36f9; valaddr_reg:x4; val_offset:1563*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1563*FLEN/8, x5, x2, x3) + +inst_547: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x07a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2f9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a3a; op2val:0x387a; +op3val:0x36f9; valaddr_reg:x4; val_offset:1566*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 1566*FLEN/8, x5, x2, x3) + +inst_548: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x07a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2f9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a3a; op2val:0x387a; +op3val:0x36f9; valaddr_reg:x4; val_offset:1569*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 1569*FLEN/8, x5, x2, x3) + +inst_549: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x07a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2f9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a3a; op2val:0x387a; +op3val:0x36f9; valaddr_reg:x4; val_offset:1572*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1572*FLEN/8, x5, x2, x3) + +inst_550: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1b9 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x27e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0a5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2db9; op2val:0x467e; +op3val:0x38a5; valaddr_reg:x4; val_offset:1575*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1575*FLEN/8, x5, x2, x3) + +inst_551: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1b9 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x27e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0a5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2db9; op2val:0x467e; +op3val:0x38a5; valaddr_reg:x4; val_offset:1578*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1578*FLEN/8, x5, x2, x3) + +inst_552: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1b9 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x27e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0a5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2db9; op2val:0x467e; +op3val:0x38a5; valaddr_reg:x4; val_offset:1581*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 1581*FLEN/8, x5, x2, x3) + +inst_553: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1b9 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x27e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0a5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2db9; op2val:0x467e; +op3val:0x38a5; valaddr_reg:x4; val_offset:1584*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 1584*FLEN/8, x5, x2, x3) + +inst_554: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1b9 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x27e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0a5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2db9; op2val:0x467e; +op3val:0x38a5; valaddr_reg:x4; val_offset:1587*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1587*FLEN/8, x5, x2, x3) + +inst_555: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b1 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x288 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x177 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ab1; op2val:0x3a88; +op3val:0x3977; valaddr_reg:x4; val_offset:1590*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1590*FLEN/8, x5, x2, x3) + +inst_556: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b1 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x288 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x177 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ab1; op2val:0x3a88; +op3val:0x3977; valaddr_reg:x4; val_offset:1593*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1593*FLEN/8, x5, x2, x3) + +inst_557: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b1 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x288 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x177 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ab1; op2val:0x3a88; +op3val:0x3977; valaddr_reg:x4; val_offset:1596*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 1596*FLEN/8, x5, x2, x3) + +inst_558: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b1 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x288 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x177 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ab1; op2val:0x3a88; +op3val:0x3977; valaddr_reg:x4; val_offset:1599*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 1599*FLEN/8, x5, x2, x3) + +inst_559: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b1 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x288 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x177 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ab1; op2val:0x3a88; +op3val:0x3977; valaddr_reg:x4; val_offset:1602*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1602*FLEN/8, x5, x2, x3) + +inst_560: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x213 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x080 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2d7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a13; op2val:0x3880; +op3val:0x36d7; valaddr_reg:x4; val_offset:1605*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1605*FLEN/8, x5, x2, x3) + +inst_561: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x213 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x080 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2d7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a13; op2val:0x3880; +op3val:0x36d7; valaddr_reg:x4; val_offset:1608*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1608*FLEN/8, x5, x2, x3) + +inst_562: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x213 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x080 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2d7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a13; op2val:0x3880; +op3val:0x36d7; valaddr_reg:x4; val_offset:1611*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 1611*FLEN/8, x5, x2, x3) + +inst_563: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x213 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x080 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2d7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a13; op2val:0x3880; +op3val:0x36d7; valaddr_reg:x4; val_offset:1614*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 1614*FLEN/8, x5, x2, x3) + +inst_564: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x213 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x080 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2d7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a13; op2val:0x3880; +op3val:0x36d7; valaddr_reg:x4; val_offset:1617*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1617*FLEN/8, x5, x2, x3) + +inst_565: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2d5 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x009 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2e5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32d5; op2val:0x4009; +op3val:0x36e5; valaddr_reg:x4; val_offset:1620*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1620*FLEN/8, x5, x2, x3) + +inst_566: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2d5 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x009 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2e5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32d5; op2val:0x4009; +op3val:0x36e5; valaddr_reg:x4; val_offset:1623*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1623*FLEN/8, x5, x2, x3) + +inst_567: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2d5 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x009 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2e5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32d5; op2val:0x4009; +op3val:0x36e5; valaddr_reg:x4; val_offset:1626*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 1626*FLEN/8, x5, x2, x3) + +inst_568: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2d5 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x009 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2e5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32d5; op2val:0x4009; +op3val:0x36e5; valaddr_reg:x4; val_offset:1629*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 1629*FLEN/8, x5, x2, x3) + +inst_569: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2d5 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x009 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2e5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32d5; op2val:0x4009; +op3val:0x36e5; valaddr_reg:x4; val_offset:1632*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1632*FLEN/8, x5, x2, x3) + +inst_570: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x27e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2a6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x165 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a7e; op2val:0x3aa6; +op3val:0x3965; valaddr_reg:x4; val_offset:1635*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1635*FLEN/8, x5, x2, x3) + +inst_571: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x27e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2a6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x165 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a7e; op2val:0x3aa6; +op3val:0x3965; valaddr_reg:x4; val_offset:1638*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1638*FLEN/8, x5, x2, x3) + +inst_572: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x27e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2a6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x165 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a7e; op2val:0x3aa6; +op3val:0x3965; valaddr_reg:x4; val_offset:1641*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 1641*FLEN/8, x5, x2, x3) + +inst_573: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x27e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2a6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x165 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a7e; op2val:0x3aa6; +op3val:0x3965; valaddr_reg:x4; val_offset:1644*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 1644*FLEN/8, x5, x2, x3) + +inst_574: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x27e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2a6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x165 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a7e; op2val:0x3aa6; +op3val:0x3965; valaddr_reg:x4; val_offset:1647*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1647*FLEN/8, x5, x2, x3) + +inst_575: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0f3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x339 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x078 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38f3; op2val:0x3b39; +op3val:0x3878; valaddr_reg:x4; val_offset:1650*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1650*FLEN/8, x5, x2, x3) + +inst_576: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0f3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x339 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x078 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38f3; op2val:0x3b39; +op3val:0x3878; valaddr_reg:x4; val_offset:1653*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1653*FLEN/8, x5, x2, x3) + +inst_577: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0f3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x339 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x078 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38f3; op2val:0x3b39; +op3val:0x3878; valaddr_reg:x4; val_offset:1656*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 1656*FLEN/8, x5, x2, x3) + +inst_578: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0f3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x339 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x078 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38f3; op2val:0x3b39; +op3val:0x3878; valaddr_reg:x4; val_offset:1659*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 1659*FLEN/8, x5, x2, x3) + +inst_579: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0f3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x339 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x078 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38f3; op2val:0x3b39; +op3val:0x3878; valaddr_reg:x4; val_offset:1662*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1662*FLEN/8, x5, x2, x3) + +inst_580: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d1 and fs2 == 0 and fe2 == 0x07 and fm2 == 0x036 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x129 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38d1; op2val:0x1c36; +op3val:0x1929; valaddr_reg:x4; val_offset:1665*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1665*FLEN/8, x5, x2, x3) + +inst_581: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d1 and fs2 == 0 and fe2 == 0x07 and fm2 == 0x036 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x129 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38d1; op2val:0x1c36; +op3val:0x1929; valaddr_reg:x4; val_offset:1668*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1668*FLEN/8, x5, x2, x3) + +inst_582: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d1 and fs2 == 0 and fe2 == 0x07 and fm2 == 0x036 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x129 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38d1; op2val:0x1c36; +op3val:0x1929; valaddr_reg:x4; val_offset:1671*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 1671*FLEN/8, x5, x2, x3) + +inst_583: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d1 and fs2 == 0 and fe2 == 0x07 and fm2 == 0x036 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x129 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38d1; op2val:0x1c36; +op3val:0x1929; valaddr_reg:x4; val_offset:1674*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 1674*FLEN/8, x5, x2, x3) + +inst_584: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d1 and fs2 == 0 and fe2 == 0x07 and fm2 == 0x036 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x129 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38d1; op2val:0x1c36; +op3val:0x1929; valaddr_reg:x4; val_offset:1677*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1677*FLEN/8, x5, x2, x3) + +inst_585: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x32e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x205 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x168 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x372e; op2val:0x3a05; +op3val:0x3568; valaddr_reg:x4; val_offset:1680*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1680*FLEN/8, x5, x2, x3) + +inst_586: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x32e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x205 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x168 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x372e; op2val:0x3a05; +op3val:0x3568; valaddr_reg:x4; val_offset:1683*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1683*FLEN/8, x5, x2, x3) + +inst_587: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x32e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x205 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x168 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x372e; op2val:0x3a05; +op3val:0x3568; valaddr_reg:x4; val_offset:1686*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 1686*FLEN/8, x5, x2, x3) + +inst_588: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x32e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x205 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x168 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x372e; op2val:0x3a05; +op3val:0x3568; valaddr_reg:x4; val_offset:1689*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 1689*FLEN/8, x5, x2, x3) + +inst_589: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x32e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x205 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x168 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x372e; op2val:0x3a05; +op3val:0x3568; valaddr_reg:x4; val_offset:1692*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1692*FLEN/8, x5, x2, x3) + +inst_590: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x089 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x100 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1ad and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3489; op2val:0x3d00; +op3val:0x35ad; valaddr_reg:x4; val_offset:1695*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1695*FLEN/8, x5, x2, x3) + +inst_591: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x089 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x100 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1ad and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3489; op2val:0x3d00; +op3val:0x35ad; valaddr_reg:x4; val_offset:1698*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1698*FLEN/8, x5, x2, x3) + +inst_592: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x089 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x100 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1ad and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3489; op2val:0x3d00; +op3val:0x35ad; valaddr_reg:x4; val_offset:1701*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 1701*FLEN/8, x5, x2, x3) + +inst_593: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x089 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x100 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1ad and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3489; op2val:0x3d00; +op3val:0x35ad; valaddr_reg:x4; val_offset:1704*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 1704*FLEN/8, x5, x2, x3) + +inst_594: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x089 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x100 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1ad and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3489; op2val:0x3d00; +op3val:0x35ad; valaddr_reg:x4; val_offset:1707*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1707*FLEN/8, x5, x2, x3) + +inst_595: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x23b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x272 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x105 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x323b; op2val:0x4272; +op3val:0x3905; valaddr_reg:x4; val_offset:1710*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1710*FLEN/8, x5, x2, x3) + +inst_596: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x23b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x272 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x105 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x323b; op2val:0x4272; +op3val:0x3905; valaddr_reg:x4; val_offset:1713*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1713*FLEN/8, x5, x2, x3) + +inst_597: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x23b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x272 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x105 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x323b; op2val:0x4272; +op3val:0x3905; valaddr_reg:x4; val_offset:1716*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 1716*FLEN/8, x5, x2, x3) + +inst_598: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x23b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x272 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x105 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x323b; op2val:0x4272; +op3val:0x3905; valaddr_reg:x4; val_offset:1719*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 1719*FLEN/8, x5, x2, x3) + +inst_599: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x23b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x272 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x105 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x323b; op2val:0x4272; +op3val:0x3905; valaddr_reg:x4; val_offset:1722*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1722*FLEN/8, x5, x2, x3) + +inst_600: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x155 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x143 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x307 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3555; op2val:0x2d43; +op3val:0x2707; valaddr_reg:x4; val_offset:1725*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1725*FLEN/8, x5, x2, x3) + +inst_601: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x155 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x143 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x307 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3555; op2val:0x2d43; +op3val:0x2707; valaddr_reg:x4; val_offset:1728*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1728*FLEN/8, x5, x2, x3) + +inst_602: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x155 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x143 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x307 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3555; op2val:0x2d43; +op3val:0x2707; valaddr_reg:x4; val_offset:1731*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 1731*FLEN/8, x5, x2, x3) + +inst_603: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x155 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x143 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x307 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3555; op2val:0x2d43; +op3val:0x2707; valaddr_reg:x4; val_offset:1734*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 1734*FLEN/8, x5, x2, x3) + +inst_604: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x155 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x143 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x307 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3555; op2val:0x2d43; +op3val:0x2707; valaddr_reg:x4; val_offset:1737*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1737*FLEN/8, x5, x2, x3) + +inst_605: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2af and fs2 == 0 and fe2 == 0x0d and fm2 == 0x32b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aaf; op2val:0x372b; +op3val:0x35fe; valaddr_reg:x4; val_offset:1740*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1740*FLEN/8, x5, x2, x3) + +inst_606: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2af and fs2 == 0 and fe2 == 0x0d and fm2 == 0x32b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1fe and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aaf; op2val:0x372b; +op3val:0x35fe; valaddr_reg:x4; val_offset:1743*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1743*FLEN/8, x5, x2, x3) + +inst_607: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2af and fs2 == 0 and fe2 == 0x0d and fm2 == 0x32b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1fe and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aaf; op2val:0x372b; +op3val:0x35fe; valaddr_reg:x4; val_offset:1746*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 1746*FLEN/8, x5, x2, x3) + +inst_608: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2af and fs2 == 0 and fe2 == 0x0d and fm2 == 0x32b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1fe and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aaf; op2val:0x372b; +op3val:0x35fe; valaddr_reg:x4; val_offset:1749*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 1749*FLEN/8, x5, x2, x3) + +inst_609: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2af and fs2 == 0 and fe2 == 0x0d and fm2 == 0x32b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1fe and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aaf; op2val:0x372b; +op3val:0x35fe; valaddr_reg:x4; val_offset:1752*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1752*FLEN/8, x5, x2, x3) + +inst_610: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ec and fs2 == 0 and fe2 == 0x0f and fm2 == 0x21a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x382 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ec; op2val:0x3e1a; +op3val:0x3b82; valaddr_reg:x4; val_offset:1755*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1755*FLEN/8, x5, x2, x3) + +inst_611: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ec and fs2 == 0 and fe2 == 0x0f and fm2 == 0x21a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x382 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ec; op2val:0x3e1a; +op3val:0x3b82; valaddr_reg:x4; val_offset:1758*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1758*FLEN/8, x5, x2, x3) + +inst_612: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ec and fs2 == 0 and fe2 == 0x0f and fm2 == 0x21a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x382 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ec; op2val:0x3e1a; +op3val:0x3b82; valaddr_reg:x4; val_offset:1761*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 1761*FLEN/8, x5, x2, x3) + +inst_613: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ec and fs2 == 0 and fe2 == 0x0f and fm2 == 0x21a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x382 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ec; op2val:0x3e1a; +op3val:0x3b82; valaddr_reg:x4; val_offset:1764*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 1764*FLEN/8, x5, x2, x3) + +inst_614: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ec and fs2 == 0 and fe2 == 0x0f and fm2 == 0x21a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x382 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ec; op2val:0x3e1a; +op3val:0x3b82; valaddr_reg:x4; val_offset:1767*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1767*FLEN/8, x5, x2, x3) + +inst_615: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ae and fs2 == 0 and fe2 == 0x0d and fm2 == 0x004 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3b6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bae; op2val:0x3404; +op3val:0x33b6; valaddr_reg:x4; val_offset:1770*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1770*FLEN/8, x5, x2, x3) + +inst_616: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ae and fs2 == 0 and fe2 == 0x0d and fm2 == 0x004 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3b6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bae; op2val:0x3404; +op3val:0x33b6; valaddr_reg:x4; val_offset:1773*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1773*FLEN/8, x5, x2, x3) + +inst_617: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ae and fs2 == 0 and fe2 == 0x0d and fm2 == 0x004 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3b6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bae; op2val:0x3404; +op3val:0x33b6; valaddr_reg:x4; val_offset:1776*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 1776*FLEN/8, x5, x2, x3) + +inst_618: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ae and fs2 == 0 and fe2 == 0x0d and fm2 == 0x004 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3b6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bae; op2val:0x3404; +op3val:0x33b6; valaddr_reg:x4; val_offset:1779*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 1779*FLEN/8, x5, x2, x3) + +inst_619: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ae and fs2 == 0 and fe2 == 0x0d and fm2 == 0x004 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3b6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bae; op2val:0x3404; +op3val:0x33b6; valaddr_reg:x4; val_offset:1782*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1782*FLEN/8, x5, x2, x3) + +inst_620: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x315 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x138 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x09f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b15; op2val:0x3538; +op3val:0x349f; valaddr_reg:x4; val_offset:1785*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1785*FLEN/8, x5, x2, x3) + +inst_621: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x315 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x138 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x09f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b15; op2val:0x3538; +op3val:0x349f; valaddr_reg:x4; val_offset:1788*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1788*FLEN/8, x5, x2, x3) + +inst_622: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x315 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x138 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x09f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b15; op2val:0x3538; +op3val:0x349f; valaddr_reg:x4; val_offset:1791*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 1791*FLEN/8, x5, x2, x3) + +inst_623: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x315 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x138 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x09f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b15; op2val:0x3538; +op3val:0x349f; valaddr_reg:x4; val_offset:1794*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 1794*FLEN/8, x5, x2, x3) + +inst_624: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x315 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x138 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x09f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b15; op2val:0x3538; +op3val:0x349f; valaddr_reg:x4; val_offset:1797*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1797*FLEN/8, x5, x2, x3) + +inst_625: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x332 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x19f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x10f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b32; op2val:0x399f; +op3val:0x390f; valaddr_reg:x4; val_offset:1800*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1800*FLEN/8, x5, x2, x3) + +inst_626: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x332 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x19f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x10f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b32; op2val:0x399f; +op3val:0x390f; valaddr_reg:x4; val_offset:1803*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1803*FLEN/8, x5, x2, x3) + +inst_627: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x332 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x19f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x10f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b32; op2val:0x399f; +op3val:0x390f; valaddr_reg:x4; val_offset:1806*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 1806*FLEN/8, x5, x2, x3) + +inst_628: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x332 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x19f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x10f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b32; op2val:0x399f; +op3val:0x390f; valaddr_reg:x4; val_offset:1809*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 1809*FLEN/8, x5, x2, x3) + +inst_629: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x332 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x19f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x10f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b32; op2val:0x399f; +op3val:0x390f; valaddr_reg:x4; val_offset:1812*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1812*FLEN/8, x5, x2, x3) + +inst_630: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3be and fs2 == 0 and fe2 == 0x0d and fm2 == 0x38f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x351 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bbe; op2val:0x378f; +op3val:0x3751; valaddr_reg:x4; val_offset:1815*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1815*FLEN/8, x5, x2, x3) + +inst_631: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3be and fs2 == 0 and fe2 == 0x0d and fm2 == 0x38f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x351 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bbe; op2val:0x378f; +op3val:0x3751; valaddr_reg:x4; val_offset:1818*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1818*FLEN/8, x5, x2, x3) + +inst_632: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3be and fs2 == 0 and fe2 == 0x0d and fm2 == 0x38f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x351 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bbe; op2val:0x378f; +op3val:0x3751; valaddr_reg:x4; val_offset:1821*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 1821*FLEN/8, x5, x2, x3) + +inst_633: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3be and fs2 == 0 and fe2 == 0x0d and fm2 == 0x38f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x351 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bbe; op2val:0x378f; +op3val:0x3751; valaddr_reg:x4; val_offset:1824*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 1824*FLEN/8, x5, x2, x3) + +inst_634: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3be and fs2 == 0 and fe2 == 0x0d and fm2 == 0x38f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x351 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bbe; op2val:0x378f; +op3val:0x3751; valaddr_reg:x4; val_offset:1827*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1827*FLEN/8, x5, x2, x3) + +inst_635: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2d6 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x33f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x232 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32d6; op2val:0x433f; +op3val:0x3a32; valaddr_reg:x4; val_offset:1830*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1830*FLEN/8, x5, x2, x3) + +inst_636: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2d6 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x33f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x232 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32d6; op2val:0x433f; +op3val:0x3a32; valaddr_reg:x4; val_offset:1833*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1833*FLEN/8, x5, x2, x3) + +inst_637: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2d6 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x33f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x232 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32d6; op2val:0x433f; +op3val:0x3a32; valaddr_reg:x4; val_offset:1836*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 1836*FLEN/8, x5, x2, x3) + +inst_638: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2d6 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x33f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x232 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32d6; op2val:0x433f; +op3val:0x3a32; valaddr_reg:x4; val_offset:1839*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 1839*FLEN/8, x5, x2, x3) + +inst_639: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2d6 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x33f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x232 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32d6; op2val:0x433f; +op3val:0x3a32; valaddr_reg:x4; val_offset:1842*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1842*FLEN/8, x5, x2, x3) + +inst_640: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2f4 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1b8 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0fa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36f4; op2val:0x31b8; +op3val:0x2cfa; valaddr_reg:x4; val_offset:1845*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1845*FLEN/8, x5, x2, x3) + +inst_641: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2f4 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1b8 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0fa and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36f4; op2val:0x31b8; +op3val:0x2cfa; valaddr_reg:x4; val_offset:1848*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1848*FLEN/8, x5, x2, x3) + +inst_642: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2f4 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1b8 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0fa and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36f4; op2val:0x31b8; +op3val:0x2cfa; valaddr_reg:x4; val_offset:1851*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 1851*FLEN/8, x5, x2, x3) + +inst_643: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2f4 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1b8 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0fa and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36f4; op2val:0x31b8; +op3val:0x2cfa; valaddr_reg:x4; val_offset:1854*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 1854*FLEN/8, x5, x2, x3) + +inst_644: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2f4 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1b8 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0fa and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36f4; op2val:0x31b8; +op3val:0x2cfa; valaddr_reg:x4; val_offset:1857*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1857*FLEN/8, x5, x2, x3) + +inst_645: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1fd and fs3 == 0 and fe3 == 0x0e and fm3 == 0x03b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39a6; op2val:0x39fd; +op3val:0x383b; valaddr_reg:x4; val_offset:1860*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1860*FLEN/8, x5, x2, x3) + +inst_646: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1fd and fs3 == 0 and fe3 == 0x0e and fm3 == 0x03b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39a6; op2val:0x39fd; +op3val:0x383b; valaddr_reg:x4; val_offset:1863*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1863*FLEN/8, x5, x2, x3) + +inst_647: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1fd and fs3 == 0 and fe3 == 0x0e and fm3 == 0x03b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39a6; op2val:0x39fd; +op3val:0x383b; valaddr_reg:x4; val_offset:1866*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 1866*FLEN/8, x5, x2, x3) + +inst_648: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1fd and fs3 == 0 and fe3 == 0x0e and fm3 == 0x03b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39a6; op2val:0x39fd; +op3val:0x383b; valaddr_reg:x4; val_offset:1869*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 1869*FLEN/8, x5, x2, x3) + +inst_649: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1fd and fs3 == 0 and fe3 == 0x0e and fm3 == 0x03b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39a6; op2val:0x39fd; +op3val:0x383b; valaddr_reg:x4; val_offset:1872*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1872*FLEN/8, x5, x2, x3) + +inst_650: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x06a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3df and fs3 == 0 and fe3 == 0x0c and fm3 == 0x058 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x346a; op2val:0x37df; +op3val:0x3058; valaddr_reg:x4; val_offset:1875*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1875*FLEN/8, x5, x2, x3) + +inst_651: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x06a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3df and fs3 == 0 and fe3 == 0x0c and fm3 == 0x058 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x346a; op2val:0x37df; +op3val:0x3058; valaddr_reg:x4; val_offset:1878*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1878*FLEN/8, x5, x2, x3) + +inst_652: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x06a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3df and fs3 == 0 and fe3 == 0x0c and fm3 == 0x058 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x346a; op2val:0x37df; +op3val:0x3058; valaddr_reg:x4; val_offset:1881*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 1881*FLEN/8, x5, x2, x3) + +inst_653: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x06a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3df and fs3 == 0 and fe3 == 0x0c and fm3 == 0x058 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x346a; op2val:0x37df; +op3val:0x3058; valaddr_reg:x4; val_offset:1884*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 1884*FLEN/8, x5, x2, x3) + +inst_654: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x06a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3df and fs3 == 0 and fe3 == 0x0c and fm3 == 0x058 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x346a; op2val:0x37df; +op3val:0x3058; valaddr_reg:x4; val_offset:1887*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1887*FLEN/8, x5, x2, x3) + +inst_655: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2a6 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x284 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x16b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aa6; op2val:0x3684; +op3val:0x356b; valaddr_reg:x4; val_offset:1890*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1890*FLEN/8, x5, x2, x3) + +inst_656: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2a6 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x284 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x16b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aa6; op2val:0x3684; +op3val:0x356b; valaddr_reg:x4; val_offset:1893*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1893*FLEN/8, x5, x2, x3) + +inst_657: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2a6 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x284 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x16b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aa6; op2val:0x3684; +op3val:0x356b; valaddr_reg:x4; val_offset:1896*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 1896*FLEN/8, x5, x2, x3) + +inst_658: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2a6 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x284 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x16b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aa6; op2val:0x3684; +op3val:0x356b; valaddr_reg:x4; val_offset:1899*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 1899*FLEN/8, x5, x2, x3) + +inst_659: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2a6 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x284 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x16b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aa6; op2val:0x3684; +op3val:0x356b; valaddr_reg:x4; val_offset:1902*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1902*FLEN/8, x5, x2, x3) + +inst_660: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x30a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x009 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x31a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b0a; op2val:0x3c09; +op3val:0x3b1a; valaddr_reg:x4; val_offset:1905*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1905*FLEN/8, x5, x2, x3) + +inst_661: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x30a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x009 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x31a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b0a; op2val:0x3c09; +op3val:0x3b1a; valaddr_reg:x4; val_offset:1908*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1908*FLEN/8, x5, x2, x3) + +inst_662: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x30a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x009 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x31a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b0a; op2val:0x3c09; +op3val:0x3b1a; valaddr_reg:x4; val_offset:1911*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 1911*FLEN/8, x5, x2, x3) + +inst_663: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x30a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x009 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x31a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b0a; op2val:0x3c09; +op3val:0x3b1a; valaddr_reg:x4; val_offset:1914*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 1914*FLEN/8, x5, x2, x3) + +inst_664: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x30a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x009 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x31a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b0a; op2val:0x3c09; +op3val:0x3b1a; valaddr_reg:x4; val_offset:1917*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1917*FLEN/8, x5, x2, x3) + +inst_665: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x04d and fs2 == 0 and fe2 == 0x14 and fm2 == 0x310 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x399 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x244d; op2val:0x5310; +op3val:0x3b99; valaddr_reg:x4; val_offset:1920*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1920*FLEN/8, x5, x2, x3) + +inst_666: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x04d and fs2 == 0 and fe2 == 0x14 and fm2 == 0x310 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x399 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x244d; op2val:0x5310; +op3val:0x3b99; valaddr_reg:x4; val_offset:1923*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1923*FLEN/8, x5, x2, x3) + +inst_667: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x04d and fs2 == 0 and fe2 == 0x14 and fm2 == 0x310 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x399 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x244d; op2val:0x5310; +op3val:0x3b99; valaddr_reg:x4; val_offset:1926*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 1926*FLEN/8, x5, x2, x3) + +inst_668: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x04d and fs2 == 0 and fe2 == 0x14 and fm2 == 0x310 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x399 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x244d; op2val:0x5310; +op3val:0x3b99; valaddr_reg:x4; val_offset:1929*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 1929*FLEN/8, x5, x2, x3) + +inst_669: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x04d and fs2 == 0 and fe2 == 0x14 and fm2 == 0x310 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x399 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x244d; op2val:0x5310; +op3val:0x3b99; valaddr_reg:x4; val_offset:1932*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1932*FLEN/8, x5, x2, x3) +RVTEST_SIGBASE(x2,signature_x2_5) + +inst_670: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x122 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x23a and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2d22; op2val:0x423a; +op3val:0x33ff; valaddr_reg:x4; val_offset:1935*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1935*FLEN/8, x5, x2, x3) + +inst_671: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x122 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x23a and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2d22; op2val:0x423a; +op3val:0x33ff; valaddr_reg:x4; val_offset:1938*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1938*FLEN/8, x5, x2, x3) + +inst_672: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x122 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x23a and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2d22; op2val:0x423a; +op3val:0x33ff; valaddr_reg:x4; val_offset:1941*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 1941*FLEN/8, x5, x2, x3) + +inst_673: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x122 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x23a and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2d22; op2val:0x423a; +op3val:0x33ff; valaddr_reg:x4; val_offset:1944*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 1944*FLEN/8, x5, x2, x3) + +inst_674: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x122 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x23a and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2d22; op2val:0x423a; +op3val:0x33ff; valaddr_reg:x4; val_offset:1947*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1947*FLEN/8, x5, x2, x3) + +inst_675: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x12f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ad and fs3 == 0 and fe3 == 0x0d and fm3 == 0x054 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x352f; op2val:0x3aad; +op3val:0x3454; valaddr_reg:x4; val_offset:1950*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1950*FLEN/8, x5, x2, x3) + +inst_676: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x12f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ad and fs3 == 0 and fe3 == 0x0d and fm3 == 0x054 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x352f; op2val:0x3aad; +op3val:0x3454; valaddr_reg:x4; val_offset:1953*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1953*FLEN/8, x5, x2, x3) + +inst_677: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x12f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ad and fs3 == 0 and fe3 == 0x0d and fm3 == 0x054 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x352f; op2val:0x3aad; +op3val:0x3454; valaddr_reg:x4; val_offset:1956*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 1956*FLEN/8, x5, x2, x3) + +inst_678: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x12f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ad and fs3 == 0 and fe3 == 0x0d and fm3 == 0x054 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x352f; op2val:0x3aad; +op3val:0x3454; valaddr_reg:x4; val_offset:1959*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 1959*FLEN/8, x5, x2, x3) + +inst_679: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x12f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ad and fs3 == 0 and fe3 == 0x0d and fm3 == 0x054 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x352f; op2val:0x3aad; +op3val:0x3454; valaddr_reg:x4; val_offset:1962*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1962*FLEN/8, x5, x2, x3) + +inst_680: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x195 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x015 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1b4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3595; op2val:0x4015; +op3val:0x39b4; valaddr_reg:x4; val_offset:1965*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1965*FLEN/8, x5, x2, x3) + +inst_681: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x195 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x015 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1b4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3595; op2val:0x4015; +op3val:0x39b4; valaddr_reg:x4; val_offset:1968*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1968*FLEN/8, x5, x2, x3) + +inst_682: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x195 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x015 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1b4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3595; op2val:0x4015; +op3val:0x39b4; valaddr_reg:x4; val_offset:1971*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 1971*FLEN/8, x5, x2, x3) + +inst_683: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x195 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x015 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1b4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3595; op2val:0x4015; +op3val:0x39b4; valaddr_reg:x4; val_offset:1974*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 1974*FLEN/8, x5, x2, x3) + +inst_684: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x195 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x015 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1b4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3595; op2val:0x4015; +op3val:0x39b4; valaddr_reg:x4; val_offset:1977*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1977*FLEN/8, x5, x2, x3) + +inst_685: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x074 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1bb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x262 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3874; op2val:0x3dbb; +op3val:0x3a62; valaddr_reg:x4; val_offset:1980*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1980*FLEN/8, x5, x2, x3) + +inst_686: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x074 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1bb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x262 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3874; op2val:0x3dbb; +op3val:0x3a62; valaddr_reg:x4; val_offset:1983*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1983*FLEN/8, x5, x2, x3) + +inst_687: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x074 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1bb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x262 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3874; op2val:0x3dbb; +op3val:0x3a62; valaddr_reg:x4; val_offset:1986*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 1986*FLEN/8, x5, x2, x3) + +inst_688: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x074 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1bb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x262 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3874; op2val:0x3dbb; +op3val:0x3a62; valaddr_reg:x4; val_offset:1989*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 1989*FLEN/8, x5, x2, x3) + +inst_689: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x074 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1bb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x262 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3874; op2val:0x3dbb; +op3val:0x3a62; valaddr_reg:x4; val_offset:1992*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 1992*FLEN/8, x5, x2, x3) + +inst_690: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x081 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x248 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x314 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3081; op2val:0x3e48; +op3val:0x3314; valaddr_reg:x4; val_offset:1995*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 1995*FLEN/8, x5, x2, x3) + +inst_691: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x081 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x248 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x314 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3081; op2val:0x3e48; +op3val:0x3314; valaddr_reg:x4; val_offset:1998*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 1998*FLEN/8, x5, x2, x3) + +inst_692: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x081 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x248 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x314 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3081; op2val:0x3e48; +op3val:0x3314; valaddr_reg:x4; val_offset:2001*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2001*FLEN/8, x5, x2, x3) + +inst_693: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x081 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x248 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x314 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3081; op2val:0x3e48; +op3val:0x3314; valaddr_reg:x4; val_offset:2004*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2004*FLEN/8, x5, x2, x3) + +inst_694: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x081 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x248 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x314 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3081; op2val:0x3e48; +op3val:0x3314; valaddr_reg:x4; val_offset:2007*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2007*FLEN/8, x5, x2, x3) + +inst_695: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2cc and fs2 == 0 and fe2 == 0x10 and fm2 == 0x365 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x249 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32cc; op2val:0x4365; +op3val:0x3a49; valaddr_reg:x4; val_offset:2010*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 2010*FLEN/8, x5, x2, x3) + +inst_696: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2cc and fs2 == 0 and fe2 == 0x10 and fm2 == 0x365 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x249 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32cc; op2val:0x4365; +op3val:0x3a49; valaddr_reg:x4; val_offset:2013*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 2013*FLEN/8, x5, x2, x3) + +inst_697: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2cc and fs2 == 0 and fe2 == 0x10 and fm2 == 0x365 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x249 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32cc; op2val:0x4365; +op3val:0x3a49; valaddr_reg:x4; val_offset:2016*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2016*FLEN/8, x5, x2, x3) + +inst_698: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2cc and fs2 == 0 and fe2 == 0x10 and fm2 == 0x365 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x249 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32cc; op2val:0x4365; +op3val:0x3a49; valaddr_reg:x4; val_offset:2019*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2019*FLEN/8, x5, x2, x3) + +inst_699: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2cc and fs2 == 0 and fe2 == 0x10 and fm2 == 0x365 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x249 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32cc; op2val:0x4365; +op3val:0x3a49; valaddr_reg:x4; val_offset:2022*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2022*FLEN/8, x5, x2, x3) + +inst_700: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x286 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x34e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1f5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3686; op2val:0x3f4e; +op3val:0x39f5; valaddr_reg:x4; val_offset:2025*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 2025*FLEN/8, x5, x2, x3) + +inst_701: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x286 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x34e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1f5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3686; op2val:0x3f4e; +op3val:0x39f5; valaddr_reg:x4; val_offset:2028*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 2028*FLEN/8, x5, x2, x3) + +inst_702: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x286 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x34e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1f5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3686; op2val:0x3f4e; +op3val:0x39f5; valaddr_reg:x4; val_offset:2031*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2031*FLEN/8, x5, x2, x3) + +inst_703: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x286 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x34e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1f5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3686; op2val:0x3f4e; +op3val:0x39f5; valaddr_reg:x4; val_offset:2034*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2034*FLEN/8, x5, x2, x3) + +inst_704: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x286 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x34e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1f5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3686; op2val:0x3f4e; +op3val:0x39f5; valaddr_reg:x4; val_offset:2037*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2037*FLEN/8, x5, x2, x3) + +inst_705: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2b4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0df and fs3 == 0 and fe3 == 0x0d and fm3 == 0x015 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32b4; op2val:0x3cdf; +op3val:0x3415; valaddr_reg:x4; val_offset:2040*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 2040*FLEN/8, x5, x2, x3) + +inst_706: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2b4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0df and fs3 == 0 and fe3 == 0x0d and fm3 == 0x015 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32b4; op2val:0x3cdf; +op3val:0x3415; valaddr_reg:x4; val_offset:2043*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 2043*FLEN/8, x5, x2, x3) + +inst_707: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2b4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0df and fs3 == 0 and fe3 == 0x0d and fm3 == 0x015 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32b4; op2val:0x3cdf; +op3val:0x3415; valaddr_reg:x4; val_offset:2046*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2046*FLEN/8, x5, x2, x3) + +inst_708: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2b4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0df and fs3 == 0 and fe3 == 0x0d and fm3 == 0x015 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32b4; op2val:0x3cdf; +op3val:0x3415; valaddr_reg:x4; val_offset:2049*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2049*FLEN/8, x5, x2, x3) + +inst_709: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2b4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0df and fs3 == 0 and fe3 == 0x0d and fm3 == 0x015 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32b4; op2val:0x3cdf; +op3val:0x3415; valaddr_reg:x4; val_offset:2052*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2052*FLEN/8, x5, x2, x3) + +inst_710: +// fs1 == 0 and fe1 == 0x07 and fm1 == 0x110 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x35f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0ab and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1d10; op2val:0x535f; +op3val:0x34ab; valaddr_reg:x4; val_offset:2055*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 2055*FLEN/8, x5, x2, x3) + +inst_711: +// fs1 == 0 and fe1 == 0x07 and fm1 == 0x110 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x35f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0ab and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1d10; op2val:0x535f; +op3val:0x34ab; valaddr_reg:x4; val_offset:2058*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 2058*FLEN/8, x5, x2, x3) + +inst_712: +// fs1 == 0 and fe1 == 0x07 and fm1 == 0x110 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x35f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0ab and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1d10; op2val:0x535f; +op3val:0x34ab; valaddr_reg:x4; val_offset:2061*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2061*FLEN/8, x5, x2, x3) + +inst_713: +// fs1 == 0 and fe1 == 0x07 and fm1 == 0x110 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x35f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0ab and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1d10; op2val:0x535f; +op3val:0x34ab; valaddr_reg:x4; val_offset:2064*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2064*FLEN/8, x5, x2, x3) + +inst_714: +// fs1 == 0 and fe1 == 0x07 and fm1 == 0x110 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x35f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0ab and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1d10; op2val:0x535f; +op3val:0x34ab; valaddr_reg:x4; val_offset:2067*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2067*FLEN/8, x5, x2, x3) + +inst_715: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x10e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1a4 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x323 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x350e; op2val:0x39a4; +op3val:0x3323; valaddr_reg:x4; val_offset:2070*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 2070*FLEN/8, x5, x2, x3) + +inst_716: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x10e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1a4 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x323 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x350e; op2val:0x39a4; +op3val:0x3323; valaddr_reg:x4; val_offset:2073*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 2073*FLEN/8, x5, x2, x3) + +inst_717: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x10e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1a4 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x323 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x350e; op2val:0x39a4; +op3val:0x3323; valaddr_reg:x4; val_offset:2076*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2076*FLEN/8, x5, x2, x3) + +inst_718: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x10e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1a4 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x323 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x350e; op2val:0x39a4; +op3val:0x3323; valaddr_reg:x4; val_offset:2079*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2079*FLEN/8, x5, x2, x3) + +inst_719: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x10e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1a4 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x323 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x350e; op2val:0x39a4; +op3val:0x3323; valaddr_reg:x4; val_offset:2082*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2082*FLEN/8, x5, x2, x3) + +inst_720: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x340 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x324 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x279 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b40; op2val:0x3724; +op3val:0x3679; valaddr_reg:x4; val_offset:2085*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 2085*FLEN/8, x5, x2, x3) + +inst_721: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x340 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x324 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x279 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b40; op2val:0x3724; +op3val:0x3679; valaddr_reg:x4; val_offset:2088*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 2088*FLEN/8, x5, x2, x3) + +inst_722: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x340 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x324 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x279 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b40; op2val:0x3724; +op3val:0x3679; valaddr_reg:x4; val_offset:2091*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2091*FLEN/8, x5, x2, x3) + +inst_723: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x340 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x324 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x279 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b40; op2val:0x3724; +op3val:0x3679; valaddr_reg:x4; val_offset:2094*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2094*FLEN/8, x5, x2, x3) + +inst_724: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x340 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x324 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x279 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b40; op2val:0x3724; +op3val:0x3679; valaddr_reg:x4; val_offset:2097*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2097*FLEN/8, x5, x2, x3) + +inst_725: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3bc and fs2 == 0 and fe2 == 0x0e and fm2 == 0x13b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x110 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bbc; op2val:0x393b; +op3val:0x3910; valaddr_reg:x4; val_offset:2100*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 2100*FLEN/8, x5, x2, x3) + +inst_726: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3bc and fs2 == 0 and fe2 == 0x0e and fm2 == 0x13b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x110 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bbc; op2val:0x393b; +op3val:0x3910; valaddr_reg:x4; val_offset:2103*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 2103*FLEN/8, x5, x2, x3) + +inst_727: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3bc and fs2 == 0 and fe2 == 0x0e and fm2 == 0x13b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x110 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bbc; op2val:0x393b; +op3val:0x3910; valaddr_reg:x4; val_offset:2106*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2106*FLEN/8, x5, x2, x3) + +inst_728: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3bc and fs2 == 0 and fe2 == 0x0e and fm2 == 0x13b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x110 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bbc; op2val:0x393b; +op3val:0x3910; valaddr_reg:x4; val_offset:2109*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2109*FLEN/8, x5, x2, x3) + +inst_729: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3bc and fs2 == 0 and fe2 == 0x0e and fm2 == 0x13b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x110 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bbc; op2val:0x393b; +op3val:0x3910; valaddr_reg:x4; val_offset:2112*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2112*FLEN/8, x5, x2, x3) + +inst_730: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x310 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x378 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x29a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b10; op2val:0x2b78; +op3val:0x2a9a; valaddr_reg:x4; val_offset:2115*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 2115*FLEN/8, x5, x2, x3) + +inst_731: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x310 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x378 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x29a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b10; op2val:0x2b78; +op3val:0x2a9a; valaddr_reg:x4; val_offset:2118*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 2118*FLEN/8, x5, x2, x3) + +inst_732: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x310 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x378 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x29a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b10; op2val:0x2b78; +op3val:0x2a9a; valaddr_reg:x4; val_offset:2121*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2121*FLEN/8, x5, x2, x3) + +inst_733: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x310 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x378 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x29a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b10; op2val:0x2b78; +op3val:0x2a9a; valaddr_reg:x4; val_offset:2124*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2124*FLEN/8, x5, x2, x3) + +inst_734: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x310 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x378 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x29a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b10; op2val:0x2b78; +op3val:0x2a9a; valaddr_reg:x4; val_offset:2127*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2127*FLEN/8, x5, x2, x3) + +inst_735: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c6 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x12e and fs3 == 0 and fe3 == 0x0b and fm3 == 0x10a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bc6; op2val:0x2d2e; +op3val:0x2d0a; valaddr_reg:x4; val_offset:2130*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 2130*FLEN/8, x5, x2, x3) + +inst_736: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c6 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x12e and fs3 == 0 and fe3 == 0x0b and fm3 == 0x10a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bc6; op2val:0x2d2e; +op3val:0x2d0a; valaddr_reg:x4; val_offset:2133*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 2133*FLEN/8, x5, x2, x3) + +inst_737: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c6 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x12e and fs3 == 0 and fe3 == 0x0b and fm3 == 0x10a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bc6; op2val:0x2d2e; +op3val:0x2d0a; valaddr_reg:x4; val_offset:2136*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2136*FLEN/8, x5, x2, x3) + +inst_738: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c6 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x12e and fs3 == 0 and fe3 == 0x0b and fm3 == 0x10a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bc6; op2val:0x2d2e; +op3val:0x2d0a; valaddr_reg:x4; val_offset:2139*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2139*FLEN/8, x5, x2, x3) + +inst_739: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c6 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x12e and fs3 == 0 and fe3 == 0x0b and fm3 == 0x10a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bc6; op2val:0x2d2e; +op3val:0x2d0a; valaddr_reg:x4; val_offset:2142*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2142*FLEN/8, x5, x2, x3) + +inst_740: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2ad and fs2 == 0 and fe2 == 0x12 and fm2 == 0x168 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x083 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2aad; op2val:0x4968; +op3val:0x3883; valaddr_reg:x4; val_offset:2145*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 2145*FLEN/8, x5, x2, x3) + +inst_741: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2ad and fs2 == 0 and fe2 == 0x12 and fm2 == 0x168 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x083 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2aad; op2val:0x4968; +op3val:0x3883; valaddr_reg:x4; val_offset:2148*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 2148*FLEN/8, x5, x2, x3) + +inst_742: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2ad and fs2 == 0 and fe2 == 0x12 and fm2 == 0x168 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x083 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2aad; op2val:0x4968; +op3val:0x3883; valaddr_reg:x4; val_offset:2151*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2151*FLEN/8, x5, x2, x3) + +inst_743: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2ad and fs2 == 0 and fe2 == 0x12 and fm2 == 0x168 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x083 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2aad; op2val:0x4968; +op3val:0x3883; valaddr_reg:x4; val_offset:2154*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2154*FLEN/8, x5, x2, x3) + +inst_744: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2ad and fs2 == 0 and fe2 == 0x12 and fm2 == 0x168 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x083 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2aad; op2val:0x4968; +op3val:0x3883; valaddr_reg:x4; val_offset:2157*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2157*FLEN/8, x5, x2, x3) + +inst_745: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x15c and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1a8 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x396 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x315c; op2val:0x45a8; +op3val:0x3b96; valaddr_reg:x4; val_offset:2160*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 2160*FLEN/8, x5, x2, x3) + +inst_746: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x15c and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1a8 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x396 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x315c; op2val:0x45a8; +op3val:0x3b96; valaddr_reg:x4; val_offset:2163*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 2163*FLEN/8, x5, x2, x3) + +inst_747: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x15c and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1a8 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x396 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x315c; op2val:0x45a8; +op3val:0x3b96; valaddr_reg:x4; val_offset:2166*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2166*FLEN/8, x5, x2, x3) + +inst_748: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x15c and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1a8 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x396 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x315c; op2val:0x45a8; +op3val:0x3b96; valaddr_reg:x4; val_offset:2169*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2169*FLEN/8, x5, x2, x3) + +inst_749: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x15c and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1a8 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x396 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x315c; op2val:0x45a8; +op3val:0x3b96; valaddr_reg:x4; val_offset:2172*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2172*FLEN/8, x5, x2, x3) + +inst_750: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2e2 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x09a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3eb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ae2; op2val:0x3c9a; +op3val:0x3beb; valaddr_reg:x4; val_offset:2175*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 2175*FLEN/8, x5, x2, x3) + +inst_751: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2e2 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x09a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3eb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ae2; op2val:0x3c9a; +op3val:0x3beb; valaddr_reg:x4; val_offset:2178*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 2178*FLEN/8, x5, x2, x3) + +inst_752: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2e2 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x09a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3eb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ae2; op2val:0x3c9a; +op3val:0x3beb; valaddr_reg:x4; val_offset:2181*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2181*FLEN/8, x5, x2, x3) + +inst_753: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2e2 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x09a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3eb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ae2; op2val:0x3c9a; +op3val:0x3beb; valaddr_reg:x4; val_offset:2184*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2184*FLEN/8, x5, x2, x3) + +inst_754: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2e2 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x09a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3eb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ae2; op2val:0x3c9a; +op3val:0x3beb; valaddr_reg:x4; val_offset:2187*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2187*FLEN/8, x5, x2, x3) + +inst_755: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x374 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x047 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3fa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b74; op2val:0x3c47; +op3val:0x3bfa; valaddr_reg:x4; val_offset:2190*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 2190*FLEN/8, x5, x2, x3) + +inst_756: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x374 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x047 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3fa and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b74; op2val:0x3c47; +op3val:0x3bfa; valaddr_reg:x4; val_offset:2193*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 2193*FLEN/8, x5, x2, x3) + +inst_757: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x374 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x047 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3fa and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b74; op2val:0x3c47; +op3val:0x3bfa; valaddr_reg:x4; val_offset:2196*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2196*FLEN/8, x5, x2, x3) + +inst_758: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x374 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x047 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3fa and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b74; op2val:0x3c47; +op3val:0x3bfa; valaddr_reg:x4; val_offset:2199*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2199*FLEN/8, x5, x2, x3) + +inst_759: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x374 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x047 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3fa and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b74; op2val:0x3c47; +op3val:0x3bfa; valaddr_reg:x4; val_offset:2202*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2202*FLEN/8, x5, x2, x3) + +inst_760: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x17e and fs2 == 0 and fe2 == 0x11 and fm2 == 0x150 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x34c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x317e; op2val:0x4550; +op3val:0x3b4c; valaddr_reg:x4; val_offset:2205*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 2205*FLEN/8, x5, x2, x3) + +inst_761: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x17e and fs2 == 0 and fe2 == 0x11 and fm2 == 0x150 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x34c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x317e; op2val:0x4550; +op3val:0x3b4c; valaddr_reg:x4; val_offset:2208*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 2208*FLEN/8, x5, x2, x3) + +inst_762: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x17e and fs2 == 0 and fe2 == 0x11 and fm2 == 0x150 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x34c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x317e; op2val:0x4550; +op3val:0x3b4c; valaddr_reg:x4; val_offset:2211*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2211*FLEN/8, x5, x2, x3) + +inst_763: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x17e and fs2 == 0 and fe2 == 0x11 and fm2 == 0x150 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x34c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x317e; op2val:0x4550; +op3val:0x3b4c; valaddr_reg:x4; val_offset:2214*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2214*FLEN/8, x5, x2, x3) + +inst_764: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x17e and fs2 == 0 and fe2 == 0x11 and fm2 == 0x150 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x34c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x317e; op2val:0x4550; +op3val:0x3b4c; valaddr_reg:x4; val_offset:2217*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2217*FLEN/8, x5, x2, x3) + +inst_765: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x28c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x31a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1d0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x368c; op2val:0x3f1a; +op3val:0x39d0; valaddr_reg:x4; val_offset:2220*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 2220*FLEN/8, x5, x2, x3) + +inst_766: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x28c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x31a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1d0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x368c; op2val:0x3f1a; +op3val:0x39d0; valaddr_reg:x4; val_offset:2223*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 2223*FLEN/8, x5, x2, x3) + +inst_767: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x28c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x31a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1d0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x368c; op2val:0x3f1a; +op3val:0x39d0; valaddr_reg:x4; val_offset:2226*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2226*FLEN/8, x5, x2, x3) + +inst_768: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x28c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x31a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1d0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x368c; op2val:0x3f1a; +op3val:0x39d0; valaddr_reg:x4; val_offset:2229*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2229*FLEN/8, x5, x2, x3) + +inst_769: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x28c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x31a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1d0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x368c; op2val:0x3f1a; +op3val:0x39d0; valaddr_reg:x4; val_offset:2232*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2232*FLEN/8, x5, x2, x3) + +inst_770: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2f0 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x15a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0a5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3af0; op2val:0x395a; +op3val:0x38a5; valaddr_reg:x4; val_offset:2235*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 2235*FLEN/8, x5, x2, x3) + +inst_771: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2f0 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x15a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0a5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3af0; op2val:0x395a; +op3val:0x38a5; valaddr_reg:x4; val_offset:2238*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 2238*FLEN/8, x5, x2, x3) + +inst_772: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2f0 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x15a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0a5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3af0; op2val:0x395a; +op3val:0x38a5; valaddr_reg:x4; val_offset:2241*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2241*FLEN/8, x5, x2, x3) + +inst_773: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2f0 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x15a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0a5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3af0; op2val:0x395a; +op3val:0x38a5; valaddr_reg:x4; val_offset:2244*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2244*FLEN/8, x5, x2, x3) + +inst_774: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2f0 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x15a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0a5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3af0; op2val:0x395a; +op3val:0x38a5; valaddr_reg:x4; val_offset:2247*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2247*FLEN/8, x5, x2, x3) + +inst_775: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x28b and fs2 == 0 and fe2 == 0x09 and fm2 == 0x323 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x1db and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a8b; op2val:0x2723; +op3val:0x25db; valaddr_reg:x4; val_offset:2250*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 2250*FLEN/8, x5, x2, x3) + +inst_776: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x28b and fs2 == 0 and fe2 == 0x09 and fm2 == 0x323 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x1db and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a8b; op2val:0x2723; +op3val:0x25db; valaddr_reg:x4; val_offset:2253*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 2253*FLEN/8, x5, x2, x3) + +inst_777: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x28b and fs2 == 0 and fe2 == 0x09 and fm2 == 0x323 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x1db and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a8b; op2val:0x2723; +op3val:0x25db; valaddr_reg:x4; val_offset:2256*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2256*FLEN/8, x5, x2, x3) + +inst_778: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x28b and fs2 == 0 and fe2 == 0x09 and fm2 == 0x323 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x1db and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a8b; op2val:0x2723; +op3val:0x25db; valaddr_reg:x4; val_offset:2259*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2259*FLEN/8, x5, x2, x3) + +inst_779: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x28b and fs2 == 0 and fe2 == 0x09 and fm2 == 0x323 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x1db and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a8b; op2val:0x2723; +op3val:0x25db; valaddr_reg:x4; val_offset:2262*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2262*FLEN/8, x5, x2, x3) + +inst_780: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ed and fs2 == 0 and fe2 == 0x0e and fm2 == 0x146 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x27f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ed; op2val:0x3946; +op3val:0x367f; valaddr_reg:x4; val_offset:2265*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 2265*FLEN/8, x5, x2, x3) + +inst_781: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ed and fs2 == 0 and fe2 == 0x0e and fm2 == 0x146 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x27f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ed; op2val:0x3946; +op3val:0x367f; valaddr_reg:x4; val_offset:2268*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 2268*FLEN/8, x5, x2, x3) + +inst_782: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ed and fs2 == 0 and fe2 == 0x0e and fm2 == 0x146 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x27f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ed; op2val:0x3946; +op3val:0x367f; valaddr_reg:x4; val_offset:2271*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2271*FLEN/8, x5, x2, x3) + +inst_783: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ed and fs2 == 0 and fe2 == 0x0e and fm2 == 0x146 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x27f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ed; op2val:0x3946; +op3val:0x367f; valaddr_reg:x4; val_offset:2274*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2274*FLEN/8, x5, x2, x3) + +inst_784: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ed and fs2 == 0 and fe2 == 0x0e and fm2 == 0x146 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x27f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ed; op2val:0x3946; +op3val:0x367f; valaddr_reg:x4; val_offset:2277*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2277*FLEN/8, x5, x2, x3) + +inst_785: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2fb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d6 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36fb; op2val:0x3ad6; +op3val:0x35f8; valaddr_reg:x4; val_offset:2280*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 2280*FLEN/8, x5, x2, x3) + +inst_786: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2fb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d6 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1f8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36fb; op2val:0x3ad6; +op3val:0x35f8; valaddr_reg:x4; val_offset:2283*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 2283*FLEN/8, x5, x2, x3) + +inst_787: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2fb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d6 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1f8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36fb; op2val:0x3ad6; +op3val:0x35f8; valaddr_reg:x4; val_offset:2286*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2286*FLEN/8, x5, x2, x3) + +inst_788: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2fb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d6 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1f8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36fb; op2val:0x3ad6; +op3val:0x35f8; valaddr_reg:x4; val_offset:2289*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2289*FLEN/8, x5, x2, x3) + +inst_789: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2fb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d6 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1f8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36fb; op2val:0x3ad6; +op3val:0x35f8; valaddr_reg:x4; val_offset:2292*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2292*FLEN/8, x5, x2, x3) + +inst_790: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x028 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x19e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1d6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3828; op2val:0x3d9e; +op3val:0x39d6; valaddr_reg:x4; val_offset:2295*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 2295*FLEN/8, x5, x2, x3) + +inst_791: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x028 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x19e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1d6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3828; op2val:0x3d9e; +op3val:0x39d6; valaddr_reg:x4; val_offset:2298*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 2298*FLEN/8, x5, x2, x3) + +inst_792: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x028 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x19e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1d6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3828; op2val:0x3d9e; +op3val:0x39d6; valaddr_reg:x4; val_offset:2301*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2301*FLEN/8, x5, x2, x3) + +inst_793: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x028 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x19e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1d6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3828; op2val:0x3d9e; +op3val:0x39d6; valaddr_reg:x4; val_offset:2304*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2304*FLEN/8, x5, x2, x3) + +inst_794: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x028 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x19e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1d6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3828; op2val:0x3d9e; +op3val:0x39d6; valaddr_reg:x4; val_offset:2307*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2307*FLEN/8, x5, x2, x3) + +inst_795: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2e7 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x026 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x32b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ae7; op2val:0x3026; +op3val:0x2f2b; valaddr_reg:x4; val_offset:2310*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 2310*FLEN/8, x5, x2, x3) + +inst_796: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2e7 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x026 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x32b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ae7; op2val:0x3026; +op3val:0x2f2b; valaddr_reg:x4; val_offset:2313*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 2313*FLEN/8, x5, x2, x3) + +inst_797: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2e7 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x026 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x32b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ae7; op2val:0x3026; +op3val:0x2f2b; valaddr_reg:x4; val_offset:2316*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2316*FLEN/8, x5, x2, x3) +RVTEST_SIGBASE(x2,signature_x2_6) + +inst_798: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2e7 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x026 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x32b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ae7; op2val:0x3026; +op3val:0x2f2b; valaddr_reg:x4; val_offset:2319*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2319*FLEN/8, x5, x2, x3) + +inst_799: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2e7 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x026 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x32b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ae7; op2val:0x3026; +op3val:0x2f2b; valaddr_reg:x4; val_offset:2322*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2322*FLEN/8, x5, x2, x3) + +inst_800: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x275 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x176 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x069 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a75; op2val:0x3976; +op3val:0x3869; valaddr_reg:x4; val_offset:2325*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 2325*FLEN/8, x5, x2, x3) + +inst_801: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x275 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x176 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x069 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a75; op2val:0x3976; +op3val:0x3869; valaddr_reg:x4; val_offset:2328*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 2328*FLEN/8, x5, x2, x3) + +inst_802: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x275 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x176 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x069 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a75; op2val:0x3976; +op3val:0x3869; valaddr_reg:x4; val_offset:2331*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2331*FLEN/8, x5, x2, x3) + +inst_803: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x275 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x176 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x069 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a75; op2val:0x3976; +op3val:0x3869; valaddr_reg:x4; val_offset:2334*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2334*FLEN/8, x5, x2, x3) + +inst_804: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x275 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x176 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x069 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a75; op2val:0x3976; +op3val:0x3869; valaddr_reg:x4; val_offset:2337*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2337*FLEN/8, x5, x2, x3) + +inst_805: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x222 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x06c and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2c8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3222; op2val:0x406c; +op3val:0x36c8; valaddr_reg:x4; val_offset:2340*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 2340*FLEN/8, x5, x2, x3) + +inst_806: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x222 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x06c and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2c8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3222; op2val:0x406c; +op3val:0x36c8; valaddr_reg:x4; val_offset:2343*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 2343*FLEN/8, x5, x2, x3) + +inst_807: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x222 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x06c and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2c8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3222; op2val:0x406c; +op3val:0x36c8; valaddr_reg:x4; val_offset:2346*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2346*FLEN/8, x5, x2, x3) + +inst_808: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x222 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x06c and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2c8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3222; op2val:0x406c; +op3val:0x36c8; valaddr_reg:x4; val_offset:2349*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2349*FLEN/8, x5, x2, x3) + +inst_809: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x222 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x06c and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2c8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3222; op2val:0x406c; +op3val:0x36c8; valaddr_reg:x4; val_offset:2352*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2352*FLEN/8, x5, x2, x3) + +inst_810: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2a7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x353 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x218 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2aa7; op2val:0x4353; +op3val:0x3218; valaddr_reg:x4; val_offset:2355*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 2355*FLEN/8, x5, x2, x3) + +inst_811: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2a7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x353 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x218 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2aa7; op2val:0x4353; +op3val:0x3218; valaddr_reg:x4; val_offset:2358*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 2358*FLEN/8, x5, x2, x3) + +inst_812: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2a7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x353 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x218 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2aa7; op2val:0x4353; +op3val:0x3218; valaddr_reg:x4; val_offset:2361*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2361*FLEN/8, x5, x2, x3) + +inst_813: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2a7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x353 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x218 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2aa7; op2val:0x4353; +op3val:0x3218; valaddr_reg:x4; val_offset:2364*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2364*FLEN/8, x5, x2, x3) + +inst_814: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2a7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x353 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x218 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2aa7; op2val:0x4353; +op3val:0x3218; valaddr_reg:x4; val_offset:2367*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2367*FLEN/8, x5, x2, x3) + +inst_815: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3c8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x33c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x30a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37c8; op2val:0x3f3c; +op3val:0x3b0a; valaddr_reg:x4; val_offset:2370*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 2370*FLEN/8, x5, x2, x3) + +inst_816: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3c8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x33c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x30a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37c8; op2val:0x3f3c; +op3val:0x3b0a; valaddr_reg:x4; val_offset:2373*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 2373*FLEN/8, x5, x2, x3) + +inst_817: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3c8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x33c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x30a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37c8; op2val:0x3f3c; +op3val:0x3b0a; valaddr_reg:x4; val_offset:2376*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2376*FLEN/8, x5, x2, x3) + +inst_818: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3c8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x33c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x30a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37c8; op2val:0x3f3c; +op3val:0x3b0a; valaddr_reg:x4; val_offset:2379*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2379*FLEN/8, x5, x2, x3) + +inst_819: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3c8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x33c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x30a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37c8; op2val:0x3f3c; +op3val:0x3b0a; valaddr_reg:x4; val_offset:2382*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2382*FLEN/8, x5, x2, x3) + +inst_820: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x284 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x12a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x035 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3684; op2val:0x3d2a; +op3val:0x3835; valaddr_reg:x4; val_offset:2385*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 2385*FLEN/8, x5, x2, x3) + +inst_821: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x284 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x12a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x035 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3684; op2val:0x3d2a; +op3val:0x3835; valaddr_reg:x4; val_offset:2388*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 2388*FLEN/8, x5, x2, x3) + +inst_822: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x284 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x12a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x035 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3684; op2val:0x3d2a; +op3val:0x3835; valaddr_reg:x4; val_offset:2391*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2391*FLEN/8, x5, x2, x3) + +inst_823: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x284 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x12a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x035 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3684; op2val:0x3d2a; +op3val:0x3835; valaddr_reg:x4; val_offset:2394*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2394*FLEN/8, x5, x2, x3) + +inst_824: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x284 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x12a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x035 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3684; op2val:0x3d2a; +op3val:0x3835; valaddr_reg:x4; val_offset:2397*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2397*FLEN/8, x5, x2, x3) + +inst_825: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x06c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x2c8 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x381 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x306c; op2val:0x42c8; +op3val:0x3781; valaddr_reg:x4; val_offset:2400*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 2400*FLEN/8, x5, x2, x3) + +inst_826: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x06c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x2c8 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x381 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x306c; op2val:0x42c8; +op3val:0x3781; valaddr_reg:x4; val_offset:2403*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 2403*FLEN/8, x5, x2, x3) + +inst_827: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x06c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x2c8 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x381 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x306c; op2val:0x42c8; +op3val:0x3781; valaddr_reg:x4; val_offset:2406*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2406*FLEN/8, x5, x2, x3) + +inst_828: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x06c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x2c8 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x381 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x306c; op2val:0x42c8; +op3val:0x3781; valaddr_reg:x4; val_offset:2409*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2409*FLEN/8, x5, x2, x3) + +inst_829: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x06c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x2c8 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x381 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x306c; op2val:0x42c8; +op3val:0x3781; valaddr_reg:x4; val_offset:2412*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2412*FLEN/8, x5, x2, x3) + +inst_830: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0e4 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0ed and fs3 == 0 and fe3 == 0x0c and fm3 == 0x207 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34e4; op2val:0x38ed; +op3val:0x3207; valaddr_reg:x4; val_offset:2415*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 2415*FLEN/8, x5, x2, x3) + +inst_831: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0e4 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0ed and fs3 == 0 and fe3 == 0x0c and fm3 == 0x207 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34e4; op2val:0x38ed; +op3val:0x3207; valaddr_reg:x4; val_offset:2418*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 2418*FLEN/8, x5, x2, x3) + +inst_832: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0e4 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0ed and fs3 == 0 and fe3 == 0x0c and fm3 == 0x207 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34e4; op2val:0x38ed; +op3val:0x3207; valaddr_reg:x4; val_offset:2421*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2421*FLEN/8, x5, x2, x3) + +inst_833: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0e4 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0ed and fs3 == 0 and fe3 == 0x0c and fm3 == 0x207 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34e4; op2val:0x38ed; +op3val:0x3207; valaddr_reg:x4; val_offset:2424*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2424*FLEN/8, x5, x2, x3) + +inst_834: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0e4 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0ed and fs3 == 0 and fe3 == 0x0c and fm3 == 0x207 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34e4; op2val:0x38ed; +op3val:0x3207; valaddr_reg:x4; val_offset:2427*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2427*FLEN/8, x5, x2, x3) + +inst_835: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x03c and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0c6 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x10f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x383c; op2val:0x34c6; +op3val:0x310f; valaddr_reg:x4; val_offset:2430*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 2430*FLEN/8, x5, x2, x3) + +inst_836: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x03c and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0c6 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x10f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x383c; op2val:0x34c6; +op3val:0x310f; valaddr_reg:x4; val_offset:2433*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 2433*FLEN/8, x5, x2, x3) + +inst_837: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x03c and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0c6 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x10f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x383c; op2val:0x34c6; +op3val:0x310f; valaddr_reg:x4; val_offset:2436*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2436*FLEN/8, x5, x2, x3) + +inst_838: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x03c and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0c6 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x10f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x383c; op2val:0x34c6; +op3val:0x310f; valaddr_reg:x4; val_offset:2439*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2439*FLEN/8, x5, x2, x3) + +inst_839: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x03c and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0c6 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x10f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x383c; op2val:0x34c6; +op3val:0x310f; valaddr_reg:x4; val_offset:2442*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2442*FLEN/8, x5, x2, x3) + +inst_840: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x272 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x032 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2c3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e72; op2val:0x4832; +op3val:0x3ac3; valaddr_reg:x4; val_offset:2445*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 2445*FLEN/8, x5, x2, x3) + +inst_841: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x272 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x032 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2c3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e72; op2val:0x4832; +op3val:0x3ac3; valaddr_reg:x4; val_offset:2448*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 2448*FLEN/8, x5, x2, x3) + +inst_842: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x272 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x032 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2c3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e72; op2val:0x4832; +op3val:0x3ac3; valaddr_reg:x4; val_offset:2451*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2451*FLEN/8, x5, x2, x3) + +inst_843: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x272 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x032 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2c3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e72; op2val:0x4832; +op3val:0x3ac3; valaddr_reg:x4; val_offset:2454*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2454*FLEN/8, x5, x2, x3) + +inst_844: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x272 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x032 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2c3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e72; op2val:0x4832; +op3val:0x3ac3; valaddr_reg:x4; val_offset:2457*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2457*FLEN/8, x5, x2, x3) + +inst_845: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x12d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x270 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x02b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2d2d; op2val:0x3e70; +op3val:0x302b; valaddr_reg:x4; val_offset:2460*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 2460*FLEN/8, x5, x2, x3) + +inst_846: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x12d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x270 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x02b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2d2d; op2val:0x3e70; +op3val:0x302b; valaddr_reg:x4; val_offset:2463*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 2463*FLEN/8, x5, x2, x3) + +inst_847: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x12d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x270 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x02b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2d2d; op2val:0x3e70; +op3val:0x302b; valaddr_reg:x4; val_offset:2466*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2466*FLEN/8, x5, x2, x3) + +inst_848: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x12d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x270 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x02b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2d2d; op2val:0x3e70; +op3val:0x302b; valaddr_reg:x4; val_offset:2469*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2469*FLEN/8, x5, x2, x3) + +inst_849: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x12d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x270 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x02b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2d2d; op2val:0x3e70; +op3val:0x302b; valaddr_reg:x4; val_offset:2472*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2472*FLEN/8, x5, x2, x3) + +inst_850: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0a4 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x090 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x14c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30a4; op2val:0x4490; +op3val:0x394c; valaddr_reg:x4; val_offset:2475*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 2475*FLEN/8, x5, x2, x3) + +inst_851: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0a4 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x090 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x14c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30a4; op2val:0x4490; +op3val:0x394c; valaddr_reg:x4; val_offset:2478*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 2478*FLEN/8, x5, x2, x3) + +inst_852: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0a4 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x090 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x14c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30a4; op2val:0x4490; +op3val:0x394c; valaddr_reg:x4; val_offset:2481*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2481*FLEN/8, x5, x2, x3) + +inst_853: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0a4 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x090 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x14c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30a4; op2val:0x4490; +op3val:0x394c; valaddr_reg:x4; val_offset:2484*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2484*FLEN/8, x5, x2, x3) + +inst_854: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0a4 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x090 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x14c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30a4; op2val:0x4490; +op3val:0x394c; valaddr_reg:x4; val_offset:2487*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2487*FLEN/8, x5, x2, x3) + +inst_855: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fc and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0a2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ef and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39fc; op2val:0x3ca2; +op3val:0x3aef; valaddr_reg:x4; val_offset:2490*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 2490*FLEN/8, x5, x2, x3) + +inst_856: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fc and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0a2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ef and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39fc; op2val:0x3ca2; +op3val:0x3aef; valaddr_reg:x4; val_offset:2493*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 2493*FLEN/8, x5, x2, x3) + +inst_857: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fc and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0a2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ef and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39fc; op2val:0x3ca2; +op3val:0x3aef; valaddr_reg:x4; val_offset:2496*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2496*FLEN/8, x5, x2, x3) + +inst_858: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fc and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0a2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ef and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39fc; op2val:0x3ca2; +op3val:0x3aef; valaddr_reg:x4; val_offset:2499*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2499*FLEN/8, x5, x2, x3) + +inst_859: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fc and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0a2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ef and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39fc; op2val:0x3ca2; +op3val:0x3aef; valaddr_reg:x4; val_offset:2502*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2502*FLEN/8, x5, x2, x3) + +inst_860: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x108 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x35f and fs3 == 0 and fe3 == 0x0c and fm3 == 0x0a4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3908; op2val:0x335f; +op3val:0x30a4; valaddr_reg:x4; val_offset:2505*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 2505*FLEN/8, x5, x2, x3) + +inst_861: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x108 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x35f and fs3 == 0 and fe3 == 0x0c and fm3 == 0x0a4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3908; op2val:0x335f; +op3val:0x30a4; valaddr_reg:x4; val_offset:2508*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 2508*FLEN/8, x5, x2, x3) + +inst_862: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x108 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x35f and fs3 == 0 and fe3 == 0x0c and fm3 == 0x0a4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3908; op2val:0x335f; +op3val:0x30a4; valaddr_reg:x4; val_offset:2511*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2511*FLEN/8, x5, x2, x3) + +inst_863: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x108 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x35f and fs3 == 0 and fe3 == 0x0c and fm3 == 0x0a4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3908; op2val:0x335f; +op3val:0x30a4; valaddr_reg:x4; val_offset:2514*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2514*FLEN/8, x5, x2, x3) + +inst_864: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x108 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x35f and fs3 == 0 and fe3 == 0x0c and fm3 == 0x0a4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3908; op2val:0x335f; +op3val:0x30a4; valaddr_reg:x4; val_offset:2517*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2517*FLEN/8, x5, x2, x3) + +inst_865: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x118 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x23e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3f5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3918; op2val:0x3e3e; +op3val:0x3bf5; valaddr_reg:x4; val_offset:2520*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 2520*FLEN/8, x5, x2, x3) + +inst_866: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x118 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x23e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3f5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3918; op2val:0x3e3e; +op3val:0x3bf5; valaddr_reg:x4; val_offset:2523*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 2523*FLEN/8, x5, x2, x3) + +inst_867: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x118 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x23e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3f5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3918; op2val:0x3e3e; +op3val:0x3bf5; valaddr_reg:x4; val_offset:2526*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2526*FLEN/8, x5, x2, x3) + +inst_868: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x118 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x23e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3f5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3918; op2val:0x3e3e; +op3val:0x3bf5; valaddr_reg:x4; val_offset:2529*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2529*FLEN/8, x5, x2, x3) + +inst_869: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x118 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x23e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3f5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3918; op2val:0x3e3e; +op3val:0x3bf5; valaddr_reg:x4; val_offset:2532*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2532*FLEN/8, x5, x2, x3) + +inst_870: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x18f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x147 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x356 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x398f; op2val:0x3d47; +op3val:0x3b56; valaddr_reg:x4; val_offset:2535*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 2535*FLEN/8, x5, x2, x3) + +inst_871: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x18f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x147 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x356 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x398f; op2val:0x3d47; +op3val:0x3b56; valaddr_reg:x4; val_offset:2538*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 2538*FLEN/8, x5, x2, x3) + +inst_872: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x18f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x147 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x356 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x398f; op2val:0x3d47; +op3val:0x3b56; valaddr_reg:x4; val_offset:2541*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2541*FLEN/8, x5, x2, x3) + +inst_873: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x18f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x147 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x356 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x398f; op2val:0x3d47; +op3val:0x3b56; valaddr_reg:x4; val_offset:2544*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2544*FLEN/8, x5, x2, x3) + +inst_874: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x18f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x147 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x356 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x398f; op2val:0x3d47; +op3val:0x3b56; valaddr_reg:x4; val_offset:2547*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2547*FLEN/8, x5, x2, x3) + +inst_875: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x20a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0e9 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x36b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x360a; op2val:0x38e9; +op3val:0x336b; valaddr_reg:x4; val_offset:2550*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 2550*FLEN/8, x5, x2, x3) + +inst_876: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x20a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0e9 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x36b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x360a; op2val:0x38e9; +op3val:0x336b; valaddr_reg:x4; val_offset:2553*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 2553*FLEN/8, x5, x2, x3) + +inst_877: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x20a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0e9 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x36b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x360a; op2val:0x38e9; +op3val:0x336b; valaddr_reg:x4; val_offset:2556*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2556*FLEN/8, x5, x2, x3) + +inst_878: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x20a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0e9 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x36b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x360a; op2val:0x38e9; +op3val:0x336b; valaddr_reg:x4; val_offset:2559*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2559*FLEN/8, x5, x2, x3) + +inst_879: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x20a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0e9 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x36b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x360a; op2val:0x38e9; +op3val:0x336b; valaddr_reg:x4; val_offset:2562*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2562*FLEN/8, x5, x2, x3) + +inst_880: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0b3 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x233 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x349 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2cb3; op2val:0x4a33; +op3val:0x3b49; valaddr_reg:x4; val_offset:2565*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 2565*FLEN/8, x5, x2, x3) + +inst_881: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0b3 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x233 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x349 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2cb3; op2val:0x4a33; +op3val:0x3b49; valaddr_reg:x4; val_offset:2568*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 2568*FLEN/8, x5, x2, x3) + +inst_882: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0b3 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x233 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x349 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2cb3; op2val:0x4a33; +op3val:0x3b49; valaddr_reg:x4; val_offset:2571*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2571*FLEN/8, x5, x2, x3) + +inst_883: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0b3 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x233 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x349 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2cb3; op2val:0x4a33; +op3val:0x3b49; valaddr_reg:x4; val_offset:2574*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2574*FLEN/8, x5, x2, x3) + +inst_884: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0b3 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x233 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x349 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2cb3; op2val:0x4a33; +op3val:0x3b49; valaddr_reg:x4; val_offset:2577*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2577*FLEN/8, x5, x2, x3) + +inst_885: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0f4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1a4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38f4; op2val:0x3da4; +op3val:0x3afe; valaddr_reg:x4; val_offset:2580*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 2580*FLEN/8, x5, x2, x3) + +inst_886: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0f4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1a4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2fe and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38f4; op2val:0x3da4; +op3val:0x3afe; valaddr_reg:x4; val_offset:2583*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 2583*FLEN/8, x5, x2, x3) + +inst_887: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0f4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1a4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2fe and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38f4; op2val:0x3da4; +op3val:0x3afe; valaddr_reg:x4; val_offset:2586*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2586*FLEN/8, x5, x2, x3) + +inst_888: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0f4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1a4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2fe and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38f4; op2val:0x3da4; +op3val:0x3afe; valaddr_reg:x4; val_offset:2589*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2589*FLEN/8, x5, x2, x3) + +inst_889: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0f4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1a4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2fe and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38f4; op2val:0x3da4; +op3val:0x3afe; valaddr_reg:x4; val_offset:2592*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2592*FLEN/8, x5, x2, x3) + +inst_890: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1bc and fs2 == 0 and fe2 == 0x0f and fm2 == 0x346 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x138 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2dbc; op2val:0x3f46; +op3val:0x3138; valaddr_reg:x4; val_offset:2595*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 2595*FLEN/8, x5, x2, x3) + +inst_891: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1bc and fs2 == 0 and fe2 == 0x0f and fm2 == 0x346 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x138 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2dbc; op2val:0x3f46; +op3val:0x3138; valaddr_reg:x4; val_offset:2598*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 2598*FLEN/8, x5, x2, x3) + +inst_892: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1bc and fs2 == 0 and fe2 == 0x0f and fm2 == 0x346 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x138 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2dbc; op2val:0x3f46; +op3val:0x3138; valaddr_reg:x4; val_offset:2601*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2601*FLEN/8, x5, x2, x3) + +inst_893: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1bc and fs2 == 0 and fe2 == 0x0f and fm2 == 0x346 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x138 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2dbc; op2val:0x3f46; +op3val:0x3138; valaddr_reg:x4; val_offset:2604*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2604*FLEN/8, x5, x2, x3) + +inst_894: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1bc and fs2 == 0 and fe2 == 0x0f and fm2 == 0x346 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x138 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2dbc; op2val:0x3f46; +op3val:0x3138; valaddr_reg:x4; val_offset:2607*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2607*FLEN/8, x5, x2, x3) + +inst_895: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3af and fs2 == 0 and fe2 == 0x0b and fm2 == 0x21f and fs3 == 0 and fe3 == 0x0a and fm3 == 0x1e4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37af; op2val:0x2e1f; +op3val:0x29e4; valaddr_reg:x4; val_offset:2610*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 2610*FLEN/8, x5, x2, x3) + +inst_896: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3af and fs2 == 0 and fe2 == 0x0b and fm2 == 0x21f and fs3 == 0 and fe3 == 0x0a and fm3 == 0x1e4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37af; op2val:0x2e1f; +op3val:0x29e4; valaddr_reg:x4; val_offset:2613*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 2613*FLEN/8, x5, x2, x3) + +inst_897: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3af and fs2 == 0 and fe2 == 0x0b and fm2 == 0x21f and fs3 == 0 and fe3 == 0x0a and fm3 == 0x1e4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37af; op2val:0x2e1f; +op3val:0x29e4; valaddr_reg:x4; val_offset:2616*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2616*FLEN/8, x5, x2, x3) + +inst_898: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3af and fs2 == 0 and fe2 == 0x0b and fm2 == 0x21f and fs3 == 0 and fe3 == 0x0a and fm3 == 0x1e4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37af; op2val:0x2e1f; +op3val:0x29e4; valaddr_reg:x4; val_offset:2619*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2619*FLEN/8, x5, x2, x3) + +inst_899: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3af and fs2 == 0 and fe2 == 0x0b and fm2 == 0x21f and fs3 == 0 and fe3 == 0x0a and fm3 == 0x1e4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37af; op2val:0x2e1f; +op3val:0x29e4; valaddr_reg:x4; val_offset:2622*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2622*FLEN/8, x5, x2, x3) + +inst_900: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ad and fs2 == 0 and fe2 == 0x0d and fm2 == 0x374 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x327 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37ad; op2val:0x3774; +op3val:0x3327; valaddr_reg:x4; val_offset:2625*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 2625*FLEN/8, x5, x2, x3) + +inst_901: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ad and fs2 == 0 and fe2 == 0x0d and fm2 == 0x374 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x327 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37ad; op2val:0x3774; +op3val:0x3327; valaddr_reg:x4; val_offset:2628*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 2628*FLEN/8, x5, x2, x3) + +inst_902: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ad and fs2 == 0 and fe2 == 0x0d and fm2 == 0x374 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x327 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37ad; op2val:0x3774; +op3val:0x3327; valaddr_reg:x4; val_offset:2631*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2631*FLEN/8, x5, x2, x3) + +inst_903: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ad and fs2 == 0 and fe2 == 0x0d and fm2 == 0x374 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x327 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37ad; op2val:0x3774; +op3val:0x3327; valaddr_reg:x4; val_offset:2634*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2634*FLEN/8, x5, x2, x3) + +inst_904: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ad and fs2 == 0 and fe2 == 0x0d and fm2 == 0x374 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x327 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37ad; op2val:0x3774; +op3val:0x3327; valaddr_reg:x4; val_offset:2637*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2637*FLEN/8, x5, x2, x3) + +inst_905: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x018 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0f7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x116 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3818; op2val:0x3cf7; +op3val:0x3916; valaddr_reg:x4; val_offset:2640*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 2640*FLEN/8, x5, x2, x3) + +inst_906: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x018 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0f7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x116 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3818; op2val:0x3cf7; +op3val:0x3916; valaddr_reg:x4; val_offset:2643*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 2643*FLEN/8, x5, x2, x3) + +inst_907: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x018 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0f7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x116 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3818; op2val:0x3cf7; +op3val:0x3916; valaddr_reg:x4; val_offset:2646*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2646*FLEN/8, x5, x2, x3) + +inst_908: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x018 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0f7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x116 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3818; op2val:0x3cf7; +op3val:0x3916; valaddr_reg:x4; val_offset:2649*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2649*FLEN/8, x5, x2, x3) + +inst_909: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x018 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0f7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x116 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3818; op2val:0x3cf7; +op3val:0x3916; valaddr_reg:x4; val_offset:2652*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2652*FLEN/8, x5, x2, x3) + +inst_910: +// fs1 == 0 and fe1 == 0x07 and fm1 == 0x1c9 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x300 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x111 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1dc9; op2val:0x4f00; +op3val:0x3111; valaddr_reg:x4; val_offset:2655*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 2655*FLEN/8, x5, x2, x3) + +inst_911: +// fs1 == 0 and fe1 == 0x07 and fm1 == 0x1c9 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x300 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x111 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1dc9; op2val:0x4f00; +op3val:0x3111; valaddr_reg:x4; val_offset:2658*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 2658*FLEN/8, x5, x2, x3) + +inst_912: +// fs1 == 0 and fe1 == 0x07 and fm1 == 0x1c9 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x300 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x111 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1dc9; op2val:0x4f00; +op3val:0x3111; valaddr_reg:x4; val_offset:2661*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2661*FLEN/8, x5, x2, x3) + +inst_913: +// fs1 == 0 and fe1 == 0x07 and fm1 == 0x1c9 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x300 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x111 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1dc9; op2val:0x4f00; +op3val:0x3111; valaddr_reg:x4; val_offset:2664*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2664*FLEN/8, x5, x2, x3) + +inst_914: +// fs1 == 0 and fe1 == 0x07 and fm1 == 0x1c9 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x300 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x111 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1dc9; op2val:0x4f00; +op3val:0x3111; valaddr_reg:x4; val_offset:2667*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2667*FLEN/8, x5, x2, x3) + +inst_915: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x288 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x133 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x040 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3688; op2val:0x3533; +op3val:0x3040; valaddr_reg:x4; val_offset:2670*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 2670*FLEN/8, x5, x2, x3) + +inst_916: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x288 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x133 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x040 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3688; op2val:0x3533; +op3val:0x3040; valaddr_reg:x4; val_offset:2673*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 2673*FLEN/8, x5, x2, x3) + +inst_917: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x288 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x133 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x040 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3688; op2val:0x3533; +op3val:0x3040; valaddr_reg:x4; val_offset:2676*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2676*FLEN/8, x5, x2, x3) + +inst_918: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x288 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x133 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x040 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3688; op2val:0x3533; +op3val:0x3040; valaddr_reg:x4; val_offset:2679*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2679*FLEN/8, x5, x2, x3) + +inst_919: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x288 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x133 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x040 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3688; op2val:0x3533; +op3val:0x3040; valaddr_reg:x4; val_offset:2682*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2682*FLEN/8, x5, x2, x3) + +inst_920: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x19c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x09d and fs3 == 0 and fe3 == 0x0c and fm3 == 0x279 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x359c; op2val:0x389d; +op3val:0x3279; valaddr_reg:x4; val_offset:2685*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 2685*FLEN/8, x5, x2, x3) + +inst_921: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x19c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x09d and fs3 == 0 and fe3 == 0x0c and fm3 == 0x279 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x359c; op2val:0x389d; +op3val:0x3279; valaddr_reg:x4; val_offset:2688*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 2688*FLEN/8, x5, x2, x3) + +inst_922: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x19c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x09d and fs3 == 0 and fe3 == 0x0c and fm3 == 0x279 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x359c; op2val:0x389d; +op3val:0x3279; valaddr_reg:x4; val_offset:2691*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2691*FLEN/8, x5, x2, x3) + +inst_923: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x19c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x09d and fs3 == 0 and fe3 == 0x0c and fm3 == 0x279 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x359c; op2val:0x389d; +op3val:0x3279; valaddr_reg:x4; val_offset:2694*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2694*FLEN/8, x5, x2, x3) + +inst_924: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x19c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x09d and fs3 == 0 and fe3 == 0x0c and fm3 == 0x279 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x359c; op2val:0x389d; +op3val:0x3279; valaddr_reg:x4; val_offset:2697*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2697*FLEN/8, x5, x2, x3) + +inst_925: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x377 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x371 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2f2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b77; op2val:0x3b71; +op3val:0x3af2; valaddr_reg:x4; val_offset:2700*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 2700*FLEN/8, x5, x2, x3) +RVTEST_SIGBASE(x2,signature_x2_7) + +inst_926: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x377 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x371 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2f2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b77; op2val:0x3b71; +op3val:0x3af2; valaddr_reg:x4; val_offset:2703*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 2703*FLEN/8, x5, x2, x3) + +inst_927: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x377 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x371 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2f2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b77; op2val:0x3b71; +op3val:0x3af2; valaddr_reg:x4; val_offset:2706*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2706*FLEN/8, x5, x2, x3) + +inst_928: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x377 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x371 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2f2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b77; op2val:0x3b71; +op3val:0x3af2; valaddr_reg:x4; val_offset:2709*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2709*FLEN/8, x5, x2, x3) + +inst_929: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x377 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x371 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2f2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b77; op2val:0x3b71; +op3val:0x3af2; valaddr_reg:x4; val_offset:2712*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2712*FLEN/8, x5, x2, x3) + +inst_930: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31f and fs2 == 0 and fe2 == 0x0d and fm2 == 0x321 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x259 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b1f; op2val:0x3721; +op3val:0x3659; valaddr_reg:x4; val_offset:2715*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 2715*FLEN/8, x5, x2, x3) + +inst_931: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31f and fs2 == 0 and fe2 == 0x0d and fm2 == 0x321 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x259 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b1f; op2val:0x3721; +op3val:0x3659; valaddr_reg:x4; val_offset:2718*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 2718*FLEN/8, x5, x2, x3) + +inst_932: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31f and fs2 == 0 and fe2 == 0x0d and fm2 == 0x321 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x259 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b1f; op2val:0x3721; +op3val:0x3659; valaddr_reg:x4; val_offset:2721*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2721*FLEN/8, x5, x2, x3) + +inst_933: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31f and fs2 == 0 and fe2 == 0x0d and fm2 == 0x321 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x259 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b1f; op2val:0x3721; +op3val:0x3659; valaddr_reg:x4; val_offset:2724*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2724*FLEN/8, x5, x2, x3) + +inst_934: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31f and fs2 == 0 and fe2 == 0x0d and fm2 == 0x321 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x259 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b1f; op2val:0x3721; +op3val:0x3659; valaddr_reg:x4; val_offset:2727*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2727*FLEN/8, x5, x2, x3) + +inst_935: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x07c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x206 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2c2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x347c; op2val:0x4206; +op3val:0x3ac2; valaddr_reg:x4; val_offset:2730*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 2730*FLEN/8, x5, x2, x3) + +inst_936: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x07c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x206 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2c2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x347c; op2val:0x4206; +op3val:0x3ac2; valaddr_reg:x4; val_offset:2733*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 2733*FLEN/8, x5, x2, x3) + +inst_937: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x07c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x206 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2c2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x347c; op2val:0x4206; +op3val:0x3ac2; valaddr_reg:x4; val_offset:2736*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2736*FLEN/8, x5, x2, x3) + +inst_938: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x07c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x206 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2c2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x347c; op2val:0x4206; +op3val:0x3ac2; valaddr_reg:x4; val_offset:2739*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2739*FLEN/8, x5, x2, x3) + +inst_939: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x07c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x206 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2c2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x347c; op2val:0x4206; +op3val:0x3ac2; valaddr_reg:x4; val_offset:2742*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2742*FLEN/8, x5, x2, x3) + +inst_940: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3eb and fs2 == 0 and fe2 == 0x0f and fm2 == 0x329 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x317 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37eb; op2val:0x3f29; +op3val:0x3b17; valaddr_reg:x4; val_offset:2745*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 2745*FLEN/8, x5, x2, x3) + +inst_941: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3eb and fs2 == 0 and fe2 == 0x0f and fm2 == 0x329 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x317 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37eb; op2val:0x3f29; +op3val:0x3b17; valaddr_reg:x4; val_offset:2748*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 2748*FLEN/8, x5, x2, x3) + +inst_942: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3eb and fs2 == 0 and fe2 == 0x0f and fm2 == 0x329 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x317 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37eb; op2val:0x3f29; +op3val:0x3b17; valaddr_reg:x4; val_offset:2751*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2751*FLEN/8, x5, x2, x3) + +inst_943: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3eb and fs2 == 0 and fe2 == 0x0f and fm2 == 0x329 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x317 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37eb; op2val:0x3f29; +op3val:0x3b17; valaddr_reg:x4; val_offset:2754*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2754*FLEN/8, x5, x2, x3) + +inst_944: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3eb and fs2 == 0 and fe2 == 0x0f and fm2 == 0x329 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x317 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37eb; op2val:0x3f29; +op3val:0x3b17; valaddr_reg:x4; val_offset:2757*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2757*FLEN/8, x5, x2, x3) + +inst_945: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1a8 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x312 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34ff; op2val:0x39a8; +op3val:0x3312; valaddr_reg:x4; val_offset:2760*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 2760*FLEN/8, x5, x2, x3) + +inst_946: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1a8 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x312 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34ff; op2val:0x39a8; +op3val:0x3312; valaddr_reg:x4; val_offset:2763*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 2763*FLEN/8, x5, x2, x3) + +inst_947: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1a8 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x312 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34ff; op2val:0x39a8; +op3val:0x3312; valaddr_reg:x4; val_offset:2766*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2766*FLEN/8, x5, x2, x3) + +inst_948: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1a8 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x312 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34ff; op2val:0x39a8; +op3val:0x3312; valaddr_reg:x4; val_offset:2769*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2769*FLEN/8, x5, x2, x3) + +inst_949: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1a8 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x312 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34ff; op2val:0x39a8; +op3val:0x3312; valaddr_reg:x4; val_offset:2772*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2772*FLEN/8, x5, x2, x3) + +inst_950: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x34e and fs2 == 0 and fe2 == 0x09 and fm2 == 0x19a and fs3 == 0 and fe3 == 0x09 and fm3 == 0x122 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b4e; op2val:0x259a; +op3val:0x2522; valaddr_reg:x4; val_offset:2775*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 2775*FLEN/8, x5, x2, x3) + +inst_951: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x34e and fs2 == 0 and fe2 == 0x09 and fm2 == 0x19a and fs3 == 0 and fe3 == 0x09 and fm3 == 0x122 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b4e; op2val:0x259a; +op3val:0x2522; valaddr_reg:x4; val_offset:2778*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 2778*FLEN/8, x5, x2, x3) + +inst_952: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x34e and fs2 == 0 and fe2 == 0x09 and fm2 == 0x19a and fs3 == 0 and fe3 == 0x09 and fm3 == 0x122 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b4e; op2val:0x259a; +op3val:0x2522; valaddr_reg:x4; val_offset:2781*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2781*FLEN/8, x5, x2, x3) + +inst_953: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x34e and fs2 == 0 and fe2 == 0x09 and fm2 == 0x19a and fs3 == 0 and fe3 == 0x09 and fm3 == 0x122 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b4e; op2val:0x259a; +op3val:0x2522; valaddr_reg:x4; val_offset:2784*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2784*FLEN/8, x5, x2, x3) + +inst_954: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x34e and fs2 == 0 and fe2 == 0x09 and fm2 == 0x19a and fs3 == 0 and fe3 == 0x09 and fm3 == 0x122 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b4e; op2val:0x259a; +op3val:0x2522; valaddr_reg:x4; val_offset:2787*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2787*FLEN/8, x5, x2, x3) + +inst_955: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x15c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x138 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x355c; op2val:0x4138; +op3val:0x3b00; valaddr_reg:x4; val_offset:2790*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 2790*FLEN/8, x5, x2, x3) + +inst_956: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x15c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x138 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x300 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x355c; op2val:0x4138; +op3val:0x3b00; valaddr_reg:x4; val_offset:2793*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 2793*FLEN/8, x5, x2, x3) + +inst_957: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x15c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x138 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x300 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x355c; op2val:0x4138; +op3val:0x3b00; valaddr_reg:x4; val_offset:2796*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2796*FLEN/8, x5, x2, x3) + +inst_958: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x15c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x138 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x300 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x355c; op2val:0x4138; +op3val:0x3b00; valaddr_reg:x4; val_offset:2799*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2799*FLEN/8, x5, x2, x3) + +inst_959: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x15c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x138 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x300 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x355c; op2val:0x4138; +op3val:0x3b00; valaddr_reg:x4; val_offset:2802*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2802*FLEN/8, x5, x2, x3) + +inst_960: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x131 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x130 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2bb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3931; op2val:0x3d30; +op3val:0x3abb; valaddr_reg:x4; val_offset:2805*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 2805*FLEN/8, x5, x2, x3) + +inst_961: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x131 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x130 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2bb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3931; op2val:0x3d30; +op3val:0x3abb; valaddr_reg:x4; val_offset:2808*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 2808*FLEN/8, x5, x2, x3) + +inst_962: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x131 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x130 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2bb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3931; op2val:0x3d30; +op3val:0x3abb; valaddr_reg:x4; val_offset:2811*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2811*FLEN/8, x5, x2, x3) + +inst_963: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x131 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x130 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2bb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3931; op2val:0x3d30; +op3val:0x3abb; valaddr_reg:x4; val_offset:2814*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2814*FLEN/8, x5, x2, x3) + +inst_964: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x131 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x130 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2bb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3931; op2val:0x3d30; +op3val:0x3abb; valaddr_reg:x4; val_offset:2817*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2817*FLEN/8, x5, x2, x3) + +inst_965: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x05a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0e5 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x345a; op2val:0x34e5; +op3val:0x2d55; valaddr_reg:x4; val_offset:2820*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 2820*FLEN/8, x5, x2, x3) + +inst_966: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x05a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0e5 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x155 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x345a; op2val:0x34e5; +op3val:0x2d55; valaddr_reg:x4; val_offset:2823*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 2823*FLEN/8, x5, x2, x3) + +inst_967: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x05a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0e5 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x155 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x345a; op2val:0x34e5; +op3val:0x2d55; valaddr_reg:x4; val_offset:2826*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2826*FLEN/8, x5, x2, x3) + +inst_968: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x05a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0e5 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x155 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x345a; op2val:0x34e5; +op3val:0x2d55; valaddr_reg:x4; val_offset:2829*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2829*FLEN/8, x5, x2, x3) + +inst_969: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x05a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0e5 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x155 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x345a; op2val:0x34e5; +op3val:0x2d55; valaddr_reg:x4; val_offset:2832*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2832*FLEN/8, x5, x2, x3) + +inst_970: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x299 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3e9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x287 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a99; op2val:0x3be9; +op3val:0x3a87; valaddr_reg:x4; val_offset:2835*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 2835*FLEN/8, x5, x2, x3) + +inst_971: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x299 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3e9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x287 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a99; op2val:0x3be9; +op3val:0x3a87; valaddr_reg:x4; val_offset:2838*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 2838*FLEN/8, x5, x2, x3) + +inst_972: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x299 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3e9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x287 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a99; op2val:0x3be9; +op3val:0x3a87; valaddr_reg:x4; val_offset:2841*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2841*FLEN/8, x5, x2, x3) + +inst_973: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x299 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3e9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x287 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a99; op2val:0x3be9; +op3val:0x3a87; valaddr_reg:x4; val_offset:2844*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2844*FLEN/8, x5, x2, x3) + +inst_974: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x299 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3e9 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x287 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a99; op2val:0x3be9; +op3val:0x3a87; valaddr_reg:x4; val_offset:2847*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2847*FLEN/8, x5, x2, x3) + +inst_975: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1f0 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x20e and fs3 == 0 and fe3 == 0x0c and fm3 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35f0; op2val:0x360e; +op3val:0x307f; valaddr_reg:x4; val_offset:2850*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 2850*FLEN/8, x5, x2, x3) + +inst_976: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1f0 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x20e and fs3 == 0 and fe3 == 0x0c and fm3 == 0x07f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35f0; op2val:0x360e; +op3val:0x307f; valaddr_reg:x4; val_offset:2853*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 2853*FLEN/8, x5, x2, x3) + +inst_977: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1f0 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x20e and fs3 == 0 and fe3 == 0x0c and fm3 == 0x07f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35f0; op2val:0x360e; +op3val:0x307f; valaddr_reg:x4; val_offset:2856*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2856*FLEN/8, x5, x2, x3) + +inst_978: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1f0 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x20e and fs3 == 0 and fe3 == 0x0c and fm3 == 0x07f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35f0; op2val:0x360e; +op3val:0x307f; valaddr_reg:x4; val_offset:2859*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2859*FLEN/8, x5, x2, x3) + +inst_979: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1f0 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x20e and fs3 == 0 and fe3 == 0x0c and fm3 == 0x07f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35f0; op2val:0x360e; +op3val:0x307f; valaddr_reg:x4; val_offset:2862*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2862*FLEN/8, x5, x2, x3) + +inst_980: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x02d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x027 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x056 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x342d; op2val:0x4027; +op3val:0x3856; valaddr_reg:x4; val_offset:2865*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 2865*FLEN/8, x5, x2, x3) + +inst_981: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x02d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x027 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x056 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x342d; op2val:0x4027; +op3val:0x3856; valaddr_reg:x4; val_offset:2868*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 2868*FLEN/8, x5, x2, x3) + +inst_982: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x02d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x027 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x056 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x342d; op2val:0x4027; +op3val:0x3856; valaddr_reg:x4; val_offset:2871*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2871*FLEN/8, x5, x2, x3) + +inst_983: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x02d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x027 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x056 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x342d; op2val:0x4027; +op3val:0x3856; valaddr_reg:x4; val_offset:2874*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2874*FLEN/8, x5, x2, x3) + +inst_984: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x02d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x027 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x056 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x342d; op2val:0x4027; +op3val:0x3856; valaddr_reg:x4; val_offset:2877*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2877*FLEN/8, x5, x2, x3) + +inst_985: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31d and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2f0 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x22c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b1d; op2val:0x36f0; +op3val:0x362c; valaddr_reg:x4; val_offset:2880*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 2880*FLEN/8, x5, x2, x3) + +inst_986: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31d and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2f0 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x22c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b1d; op2val:0x36f0; +op3val:0x362c; valaddr_reg:x4; val_offset:2883*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 2883*FLEN/8, x5, x2, x3) + +inst_987: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31d and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2f0 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x22c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b1d; op2val:0x36f0; +op3val:0x362c; valaddr_reg:x4; val_offset:2886*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2886*FLEN/8, x5, x2, x3) + +inst_988: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31d and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2f0 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x22c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b1d; op2val:0x36f0; +op3val:0x362c; valaddr_reg:x4; val_offset:2889*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2889*FLEN/8, x5, x2, x3) + +inst_989: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31d and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2f0 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x22c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b1d; op2val:0x36f0; +op3val:0x362c; valaddr_reg:x4; val_offset:2892*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2892*FLEN/8, x5, x2, x3) + +inst_990: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x05b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1c4 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x247 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x385b; op2val:0x35c4; +op3val:0x3247; valaddr_reg:x4; val_offset:2895*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 2895*FLEN/8, x5, x2, x3) + +inst_991: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x05b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1c4 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x247 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x385b; op2val:0x35c4; +op3val:0x3247; valaddr_reg:x4; val_offset:2898*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 2898*FLEN/8, x5, x2, x3) + +inst_992: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x05b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1c4 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x247 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x385b; op2val:0x35c4; +op3val:0x3247; valaddr_reg:x4; val_offset:2901*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2901*FLEN/8, x5, x2, x3) + +inst_993: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x05b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1c4 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x247 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x385b; op2val:0x35c4; +op3val:0x3247; valaddr_reg:x4; val_offset:2904*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2904*FLEN/8, x5, x2, x3) + +inst_994: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x05b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1c4 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x247 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x385b; op2val:0x35c4; +op3val:0x3247; valaddr_reg:x4; val_offset:2907*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2907*FLEN/8, x5, x2, x3) + +inst_995: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2d9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0f8 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x041 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36d9; op2val:0x38f8; +op3val:0x3441; valaddr_reg:x4; val_offset:2910*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 2910*FLEN/8, x5, x2, x3) + +inst_996: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2d9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0f8 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x041 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36d9; op2val:0x38f8; +op3val:0x3441; valaddr_reg:x4; val_offset:2913*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 2913*FLEN/8, x5, x2, x3) + +inst_997: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2d9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0f8 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x041 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36d9; op2val:0x38f8; +op3val:0x3441; valaddr_reg:x4; val_offset:2916*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2916*FLEN/8, x5, x2, x3) + +inst_998: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2d9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0f8 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x041 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36d9; op2val:0x38f8; +op3val:0x3441; valaddr_reg:x4; val_offset:2919*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2919*FLEN/8, x5, x2, x3) + +inst_999: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2d9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0f8 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x041 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36d9; op2val:0x38f8; +op3val:0x3441; valaddr_reg:x4; val_offset:2922*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2922*FLEN/8, x5, x2, x3) + +inst_1000: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x36a and fs2 == 0 and fe2 == 0x12 and fm2 == 0x274 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x276a; op2val:0x4a74; +op3val:0x35fc; valaddr_reg:x4; val_offset:2925*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 2925*FLEN/8, x5, x2, x3) + +inst_1001: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x36a and fs2 == 0 and fe2 == 0x12 and fm2 == 0x274 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1fc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x276a; op2val:0x4a74; +op3val:0x35fc; valaddr_reg:x4; val_offset:2928*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 2928*FLEN/8, x5, x2, x3) + +inst_1002: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x36a and fs2 == 0 and fe2 == 0x12 and fm2 == 0x274 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1fc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x276a; op2val:0x4a74; +op3val:0x35fc; valaddr_reg:x4; val_offset:2931*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2931*FLEN/8, x5, x2, x3) + +inst_1003: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x36a and fs2 == 0 and fe2 == 0x12 and fm2 == 0x274 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1fc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x276a; op2val:0x4a74; +op3val:0x35fc; valaddr_reg:x4; val_offset:2934*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2934*FLEN/8, x5, x2, x3) + +inst_1004: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x36a and fs2 == 0 and fe2 == 0x12 and fm2 == 0x274 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1fc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x276a; op2val:0x4a74; +op3val:0x35fc; valaddr_reg:x4; val_offset:2937*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2937*FLEN/8, x5, x2, x3) + +inst_1005: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1a8 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x01b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ce and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2da8; op2val:0x481b; +op3val:0x39ce; valaddr_reg:x4; val_offset:2940*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 2940*FLEN/8, x5, x2, x3) + +inst_1006: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1a8 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x01b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ce and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2da8; op2val:0x481b; +op3val:0x39ce; valaddr_reg:x4; val_offset:2943*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 2943*FLEN/8, x5, x2, x3) + +inst_1007: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1a8 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x01b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ce and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2da8; op2val:0x481b; +op3val:0x39ce; valaddr_reg:x4; val_offset:2946*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2946*FLEN/8, x5, x2, x3) + +inst_1008: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1a8 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x01b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ce and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2da8; op2val:0x481b; +op3val:0x39ce; valaddr_reg:x4; val_offset:2949*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2949*FLEN/8, x5, x2, x3) + +inst_1009: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1a8 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x01b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ce and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2da8; op2val:0x481b; +op3val:0x39ce; valaddr_reg:x4; val_offset:2952*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2952*FLEN/8, x5, x2, x3) + +inst_1010: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x0b and fm2 == 0x389 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x387 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bfc; op2val:0x2f89; +op3val:0x2f87; valaddr_reg:x4; val_offset:2955*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 2955*FLEN/8, x5, x2, x3) + +inst_1011: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x0b and fm2 == 0x389 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x387 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bfc; op2val:0x2f89; +op3val:0x2f87; valaddr_reg:x4; val_offset:2958*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 2958*FLEN/8, x5, x2, x3) + +inst_1012: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x0b and fm2 == 0x389 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x387 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bfc; op2val:0x2f89; +op3val:0x2f87; valaddr_reg:x4; val_offset:2961*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2961*FLEN/8, x5, x2, x3) + +inst_1013: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x0b and fm2 == 0x389 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x387 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bfc; op2val:0x2f89; +op3val:0x2f87; valaddr_reg:x4; val_offset:2964*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2964*FLEN/8, x5, x2, x3) + +inst_1014: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x0b and fm2 == 0x389 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x387 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bfc; op2val:0x2f89; +op3val:0x2f87; valaddr_reg:x4; val_offset:2967*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2967*FLEN/8, x5, x2, x3) + +inst_1015: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c2 and fs2 == 0 and fe2 == 0x07 and fm2 == 0x2b7 and fs3 == 0 and fe3 == 0x07 and fm3 == 0x295 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bc2; op2val:0x1eb7; +op3val:0x1e95; valaddr_reg:x4; val_offset:2970*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 2970*FLEN/8, x5, x2, x3) + +inst_1016: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c2 and fs2 == 0 and fe2 == 0x07 and fm2 == 0x2b7 and fs3 == 0 and fe3 == 0x07 and fm3 == 0x295 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bc2; op2val:0x1eb7; +op3val:0x1e95; valaddr_reg:x4; val_offset:2973*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 2973*FLEN/8, x5, x2, x3) + +inst_1017: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c2 and fs2 == 0 and fe2 == 0x07 and fm2 == 0x2b7 and fs3 == 0 and fe3 == 0x07 and fm3 == 0x295 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bc2; op2val:0x1eb7; +op3val:0x1e95; valaddr_reg:x4; val_offset:2976*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2976*FLEN/8, x5, x2, x3) + +inst_1018: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c2 and fs2 == 0 and fe2 == 0x07 and fm2 == 0x2b7 and fs3 == 0 and fe3 == 0x07 and fm3 == 0x295 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bc2; op2val:0x1eb7; +op3val:0x1e95; valaddr_reg:x4; val_offset:2979*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2979*FLEN/8, x5, x2, x3) + +inst_1019: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c2 and fs2 == 0 and fe2 == 0x07 and fm2 == 0x2b7 and fs3 == 0 and fe3 == 0x07 and fm3 == 0x295 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bc2; op2val:0x1eb7; +op3val:0x1e95; valaddr_reg:x4; val_offset:2982*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2982*FLEN/8, x5, x2, x3) + +inst_1020: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x05a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2e5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x382 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x385a; op2val:0x3ee5; +op3val:0x3b82; valaddr_reg:x4; val_offset:2985*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 2985*FLEN/8, x5, x2, x3) + +inst_1021: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x05a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2e5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x382 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x385a; op2val:0x3ee5; +op3val:0x3b82; valaddr_reg:x4; val_offset:2988*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 2988*FLEN/8, x5, x2, x3) + +inst_1022: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x05a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2e5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x382 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x385a; op2val:0x3ee5; +op3val:0x3b82; valaddr_reg:x4; val_offset:2991*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 2991*FLEN/8, x5, x2, x3) + +inst_1023: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x05a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2e5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x382 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x385a; op2val:0x3ee5; +op3val:0x3b82; valaddr_reg:x4; val_offset:2994*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 2994*FLEN/8, x5, x2, x3) + +inst_1024: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x05a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2e5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x382 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x385a; op2val:0x3ee5; +op3val:0x3b82; valaddr_reg:x4; val_offset:2997*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 2997*FLEN/8, x5, x2, x3) + +inst_1025: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1cd and fs2 == 0 and fe2 == 0x0d and fm2 == 0x225 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x075 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39cd; op2val:0x3625; +op3val:0x3475; valaddr_reg:x4; val_offset:3000*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3000*FLEN/8, x5, x2, x3) + +inst_1026: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1cd and fs2 == 0 and fe2 == 0x0d and fm2 == 0x225 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x075 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39cd; op2val:0x3625; +op3val:0x3475; valaddr_reg:x4; val_offset:3003*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3003*FLEN/8, x5, x2, x3) + +inst_1027: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1cd and fs2 == 0 and fe2 == 0x0d and fm2 == 0x225 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x075 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39cd; op2val:0x3625; +op3val:0x3475; valaddr_reg:x4; val_offset:3006*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3006*FLEN/8, x5, x2, x3) + +inst_1028: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1cd and fs2 == 0 and fe2 == 0x0d and fm2 == 0x225 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x075 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39cd; op2val:0x3625; +op3val:0x3475; valaddr_reg:x4; val_offset:3009*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3009*FLEN/8, x5, x2, x3) + +inst_1029: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1cd and fs2 == 0 and fe2 == 0x0d and fm2 == 0x225 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x075 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39cd; op2val:0x3625; +op3val:0x3475; valaddr_reg:x4; val_offset:3012*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 3012*FLEN/8, x5, x2, x3) + +inst_1030: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ed and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0e2 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x204 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ed; op2val:0x38e2; +op3val:0x3604; valaddr_reg:x4; val_offset:3015*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3015*FLEN/8, x5, x2, x3) + +inst_1031: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ed and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0e2 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x204 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ed; op2val:0x38e2; +op3val:0x3604; valaddr_reg:x4; val_offset:3018*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3018*FLEN/8, x5, x2, x3) + +inst_1032: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ed and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0e2 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x204 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ed; op2val:0x38e2; +op3val:0x3604; valaddr_reg:x4; val_offset:3021*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3021*FLEN/8, x5, x2, x3) + +inst_1033: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ed and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0e2 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x204 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ed; op2val:0x38e2; +op3val:0x3604; valaddr_reg:x4; val_offset:3024*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3024*FLEN/8, x5, x2, x3) + +inst_1034: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ed and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0e2 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x204 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ed; op2val:0x38e2; +op3val:0x3604; valaddr_reg:x4; val_offset:3027*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 3027*FLEN/8, x5, x2, x3) + +inst_1035: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x32f and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1db and fs3 == 0 and fe3 == 0x0c and fm3 == 0x142 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b2f; op2val:0x31db; +op3val:0x3142; valaddr_reg:x4; val_offset:3030*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3030*FLEN/8, x5, x2, x3) + +inst_1036: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x32f and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1db and fs3 == 0 and fe3 == 0x0c and fm3 == 0x142 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b2f; op2val:0x31db; +op3val:0x3142; valaddr_reg:x4; val_offset:3033*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3033*FLEN/8, x5, x2, x3) + +inst_1037: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x32f and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1db and fs3 == 0 and fe3 == 0x0c and fm3 == 0x142 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b2f; op2val:0x31db; +op3val:0x3142; valaddr_reg:x4; val_offset:3036*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3036*FLEN/8, x5, x2, x3) + +inst_1038: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x32f and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1db and fs3 == 0 and fe3 == 0x0c and fm3 == 0x142 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b2f; op2val:0x31db; +op3val:0x3142; valaddr_reg:x4; val_offset:3039*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3039*FLEN/8, x5, x2, x3) + +inst_1039: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x32f and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1db and fs3 == 0 and fe3 == 0x0c and fm3 == 0x142 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b2f; op2val:0x31db; +op3val:0x3142; valaddr_reg:x4; val_offset:3042*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 3042*FLEN/8, x5, x2, x3) + +inst_1040: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x103 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x044 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x15a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3903; op2val:0x3444; +op3val:0x315a; valaddr_reg:x4; val_offset:3045*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3045*FLEN/8, x5, x2, x3) + +inst_1041: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x103 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x044 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x15a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3903; op2val:0x3444; +op3val:0x315a; valaddr_reg:x4; val_offset:3048*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3048*FLEN/8, x5, x2, x3) + +inst_1042: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x103 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x044 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x15a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3903; op2val:0x3444; +op3val:0x315a; valaddr_reg:x4; val_offset:3051*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3051*FLEN/8, x5, x2, x3) + +inst_1043: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x103 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x044 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x15a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3903; op2val:0x3444; +op3val:0x315a; valaddr_reg:x4; val_offset:3054*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3054*FLEN/8, x5, x2, x3) + +inst_1044: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x103 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x044 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x15a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3903; op2val:0x3444; +op3val:0x315a; valaddr_reg:x4; val_offset:3057*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 3057*FLEN/8, x5, x2, x3) + +inst_1045: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d2 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x23e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x152 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ad2; op2val:0x363e; +op3val:0x3552; valaddr_reg:x4; val_offset:3060*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3060*FLEN/8, x5, x2, x3) + +inst_1046: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d2 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x23e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x152 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ad2; op2val:0x363e; +op3val:0x3552; valaddr_reg:x4; val_offset:3063*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3063*FLEN/8, x5, x2, x3) + +inst_1047: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d2 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x23e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x152 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ad2; op2val:0x363e; +op3val:0x3552; valaddr_reg:x4; val_offset:3066*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3066*FLEN/8, x5, x2, x3) + +inst_1048: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d2 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x23e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x152 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ad2; op2val:0x363e; +op3val:0x3552; valaddr_reg:x4; val_offset:3069*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3069*FLEN/8, x5, x2, x3) + +inst_1049: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d2 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x23e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x152 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ad2; op2val:0x363e; +op3val:0x3552; valaddr_reg:x4; val_offset:3072*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 3072*FLEN/8, x5, x2, x3) + +inst_1050: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x03f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x07c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0c3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x383f; op2val:0x3c7c; +op3val:0x38c3; valaddr_reg:x4; val_offset:3075*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3075*FLEN/8, x5, x2, x3) + +inst_1051: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x03f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x07c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0c3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x383f; op2val:0x3c7c; +op3val:0x38c3; valaddr_reg:x4; val_offset:3078*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3078*FLEN/8, x5, x2, x3) + +inst_1052: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x03f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x07c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0c3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x383f; op2val:0x3c7c; +op3val:0x38c3; valaddr_reg:x4; val_offset:3081*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3081*FLEN/8, x5, x2, x3) + +inst_1053: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x03f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x07c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0c3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x383f; op2val:0x3c7c; +op3val:0x38c3; valaddr_reg:x4; val_offset:3084*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3084*FLEN/8, x5, x2, x3) +RVTEST_SIGBASE(x2,signature_x2_8) + +inst_1054: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x03f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x07c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0c3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x383f; op2val:0x3c7c; +op3val:0x38c3; valaddr_reg:x4; val_offset:3087*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 3087*FLEN/8, x5, x2, x3) + +inst_1055: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d8 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3a3 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x37e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bd8; op2val:0x37a3; +op3val:0x377e; valaddr_reg:x4; val_offset:3090*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3090*FLEN/8, x5, x2, x3) + +inst_1056: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d8 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3a3 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x37e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bd8; op2val:0x37a3; +op3val:0x377e; valaddr_reg:x4; val_offset:3093*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3093*FLEN/8, x5, x2, x3) + +inst_1057: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d8 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3a3 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x37e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bd8; op2val:0x37a3; +op3val:0x377e; valaddr_reg:x4; val_offset:3096*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3096*FLEN/8, x5, x2, x3) + +inst_1058: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d8 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3a3 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x37e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bd8; op2val:0x37a3; +op3val:0x377e; valaddr_reg:x4; val_offset:3099*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3099*FLEN/8, x5, x2, x3) + +inst_1059: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d8 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3a3 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x37e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bd8; op2val:0x37a3; +op3val:0x377e; valaddr_reg:x4; val_offset:3102*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 3102*FLEN/8, x5, x2, x3) + +inst_1060: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x12f and fs2 == 0 and fe2 == 0x11 and fm2 == 0x187 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x32b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x312f; op2val:0x4587; +op3val:0x3b2b; valaddr_reg:x4; val_offset:3105*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3105*FLEN/8, x5, x2, x3) + +inst_1061: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x12f and fs2 == 0 and fe2 == 0x11 and fm2 == 0x187 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x32b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x312f; op2val:0x4587; +op3val:0x3b2b; valaddr_reg:x4; val_offset:3108*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3108*FLEN/8, x5, x2, x3) + +inst_1062: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x12f and fs2 == 0 and fe2 == 0x11 and fm2 == 0x187 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x32b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x312f; op2val:0x4587; +op3val:0x3b2b; valaddr_reg:x4; val_offset:3111*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3111*FLEN/8, x5, x2, x3) + +inst_1063: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x12f and fs2 == 0 and fe2 == 0x11 and fm2 == 0x187 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x32b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x312f; op2val:0x4587; +op3val:0x3b2b; valaddr_reg:x4; val_offset:3114*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3114*FLEN/8, x5, x2, x3) + +inst_1064: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x12f and fs2 == 0 and fe2 == 0x11 and fm2 == 0x187 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x32b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x312f; op2val:0x4587; +op3val:0x3b2b; valaddr_reg:x4; val_offset:3117*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 3117*FLEN/8, x5, x2, x3) + +inst_1065: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x06f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x320 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3e6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x386f; op2val:0x3f20; +op3val:0x3be6; valaddr_reg:x4; val_offset:3120*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3120*FLEN/8, x5, x2, x3) + +inst_1066: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x06f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x320 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3e6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x386f; op2val:0x3f20; +op3val:0x3be6; valaddr_reg:x4; val_offset:3123*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3123*FLEN/8, x5, x2, x3) + +inst_1067: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x06f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x320 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3e6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x386f; op2val:0x3f20; +op3val:0x3be6; valaddr_reg:x4; val_offset:3126*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3126*FLEN/8, x5, x2, x3) + +inst_1068: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x06f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x320 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3e6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x386f; op2val:0x3f20; +op3val:0x3be6; valaddr_reg:x4; val_offset:3129*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3129*FLEN/8, x5, x2, x3) + +inst_1069: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x06f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x320 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3e6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x386f; op2val:0x3f20; +op3val:0x3be6; valaddr_reg:x4; val_offset:3132*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 3132*FLEN/8, x5, x2, x3) + +inst_1070: +// fs1 == 0 and fe1 == 0x07 and fm1 == 0x219 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x11e and fs3 == 0 and fe3 == 0x09 and fm3 == 0x3d2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1e19; op2val:0x451e; +op3val:0x27d2; valaddr_reg:x4; val_offset:3135*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3135*FLEN/8, x5, x2, x3) + +inst_1071: +// fs1 == 0 and fe1 == 0x07 and fm1 == 0x219 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x11e and fs3 == 0 and fe3 == 0x09 and fm3 == 0x3d2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1e19; op2val:0x451e; +op3val:0x27d2; valaddr_reg:x4; val_offset:3138*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3138*FLEN/8, x5, x2, x3) + +inst_1072: +// fs1 == 0 and fe1 == 0x07 and fm1 == 0x219 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x11e and fs3 == 0 and fe3 == 0x09 and fm3 == 0x3d2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1e19; op2val:0x451e; +op3val:0x27d2; valaddr_reg:x4; val_offset:3141*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3141*FLEN/8, x5, x2, x3) + +inst_1073: +// fs1 == 0 and fe1 == 0x07 and fm1 == 0x219 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x11e and fs3 == 0 and fe3 == 0x09 and fm3 == 0x3d2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1e19; op2val:0x451e; +op3val:0x27d2; valaddr_reg:x4; val_offset:3144*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3144*FLEN/8, x5, x2, x3) + +inst_1074: +// fs1 == 0 and fe1 == 0x07 and fm1 == 0x219 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x11e and fs3 == 0 and fe3 == 0x09 and fm3 == 0x3d2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1e19; op2val:0x451e; +op3val:0x27d2; valaddr_reg:x4; val_offset:3147*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 3147*FLEN/8, x5, x2, x3) + +inst_1075: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x125 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x277 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x028 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3525; op2val:0x3e77; +op3val:0x3828; valaddr_reg:x4; val_offset:3150*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3150*FLEN/8, x5, x2, x3) + +inst_1076: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x125 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x277 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x028 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3525; op2val:0x3e77; +op3val:0x3828; valaddr_reg:x4; val_offset:3153*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3153*FLEN/8, x5, x2, x3) + +inst_1077: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x125 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x277 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x028 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3525; op2val:0x3e77; +op3val:0x3828; valaddr_reg:x4; val_offset:3156*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3156*FLEN/8, x5, x2, x3) + +inst_1078: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x125 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x277 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x028 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3525; op2val:0x3e77; +op3val:0x3828; valaddr_reg:x4; val_offset:3159*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3159*FLEN/8, x5, x2, x3) + +inst_1079: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x125 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x277 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x028 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3525; op2val:0x3e77; +op3val:0x3828; valaddr_reg:x4; val_offset:3162*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 3162*FLEN/8, x5, x2, x3) + +inst_1080: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x390 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x308 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b6f; op2val:0x3b90; +op3val:0x3b08; valaddr_reg:x4; val_offset:3165*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3165*FLEN/8, x5, x2, x3) + +inst_1081: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x390 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x308 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b6f; op2val:0x3b90; +op3val:0x3b08; valaddr_reg:x4; val_offset:3168*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3168*FLEN/8, x5, x2, x3) + +inst_1082: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x390 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x308 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b6f; op2val:0x3b90; +op3val:0x3b08; valaddr_reg:x4; val_offset:3171*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3171*FLEN/8, x5, x2, x3) + +inst_1083: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x390 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x308 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b6f; op2val:0x3b90; +op3val:0x3b08; valaddr_reg:x4; val_offset:3174*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3174*FLEN/8, x5, x2, x3) + +inst_1084: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x390 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x308 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b6f; op2val:0x3b90; +op3val:0x3b08; valaddr_reg:x4; val_offset:3177*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 3177*FLEN/8, x5, x2, x3) + +inst_1085: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0b8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x192 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x293 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34b8; op2val:0x3992; +op3val:0x3293; valaddr_reg:x4; val_offset:3180*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3180*FLEN/8, x5, x2, x3) + +inst_1086: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0b8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x192 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x293 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34b8; op2val:0x3992; +op3val:0x3293; valaddr_reg:x4; val_offset:3183*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3183*FLEN/8, x5, x2, x3) + +inst_1087: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0b8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x192 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x293 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34b8; op2val:0x3992; +op3val:0x3293; valaddr_reg:x4; val_offset:3186*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3186*FLEN/8, x5, x2, x3) + +inst_1088: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0b8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x192 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x293 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34b8; op2val:0x3992; +op3val:0x3293; valaddr_reg:x4; val_offset:3189*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3189*FLEN/8, x5, x2, x3) + +inst_1089: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0b8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x192 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x293 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34b8; op2val:0x3992; +op3val:0x3293; valaddr_reg:x4; val_offset:3192*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 3192*FLEN/8, x5, x2, x3) + +inst_1090: +// fs1 == 0 and fe1 == 0x08 and fm1 == 0x1a0 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x24a and fs3 == 0 and fe3 == 0x0c and fm3 == 0x06d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x21a0; op2val:0x4a4a; +op3val:0x306d; valaddr_reg:x4; val_offset:3195*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3195*FLEN/8, x5, x2, x3) + +inst_1091: +// fs1 == 0 and fe1 == 0x08 and fm1 == 0x1a0 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x24a and fs3 == 0 and fe3 == 0x0c and fm3 == 0x06d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x21a0; op2val:0x4a4a; +op3val:0x306d; valaddr_reg:x4; val_offset:3198*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3198*FLEN/8, x5, x2, x3) + +inst_1092: +// fs1 == 0 and fe1 == 0x08 and fm1 == 0x1a0 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x24a and fs3 == 0 and fe3 == 0x0c and fm3 == 0x06d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x21a0; op2val:0x4a4a; +op3val:0x306d; valaddr_reg:x4; val_offset:3201*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3201*FLEN/8, x5, x2, x3) + +inst_1093: +// fs1 == 0 and fe1 == 0x08 and fm1 == 0x1a0 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x24a and fs3 == 0 and fe3 == 0x0c and fm3 == 0x06d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x21a0; op2val:0x4a4a; +op3val:0x306d; valaddr_reg:x4; val_offset:3204*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3204*FLEN/8, x5, x2, x3) + +inst_1094: +// fs1 == 0 and fe1 == 0x08 and fm1 == 0x1a0 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x24a and fs3 == 0 and fe3 == 0x0c and fm3 == 0x06d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x21a0; op2val:0x4a4a; +op3val:0x306d; valaddr_reg:x4; val_offset:3207*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 3207*FLEN/8, x5, x2, x3) + +inst_1095: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x07f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x14c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1f5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x387f; op2val:0x3d4c; +op3val:0x39f5; valaddr_reg:x4; val_offset:3210*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3210*FLEN/8, x5, x2, x3) + +inst_1096: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x07f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x14c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1f5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x387f; op2val:0x3d4c; +op3val:0x39f5; valaddr_reg:x4; val_offset:3213*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3213*FLEN/8, x5, x2, x3) + +inst_1097: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x07f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x14c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1f5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x387f; op2val:0x3d4c; +op3val:0x39f5; valaddr_reg:x4; val_offset:3216*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3216*FLEN/8, x5, x2, x3) + +inst_1098: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x07f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x14c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1f5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x387f; op2val:0x3d4c; +op3val:0x39f5; valaddr_reg:x4; val_offset:3219*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3219*FLEN/8, x5, x2, x3) + +inst_1099: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x07f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x14c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1f5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x387f; op2val:0x3d4c; +op3val:0x39f5; valaddr_reg:x4; val_offset:3222*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 3222*FLEN/8, x5, x2, x3) + +inst_1100: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x354 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1b5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x13b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3754; op2val:0x3db5; +op3val:0x393b; valaddr_reg:x4; val_offset:3225*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3225*FLEN/8, x5, x2, x3) + +inst_1101: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x354 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1b5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x13b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3754; op2val:0x3db5; +op3val:0x393b; valaddr_reg:x4; val_offset:3228*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3228*FLEN/8, x5, x2, x3) + +inst_1102: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x354 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1b5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x13b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3754; op2val:0x3db5; +op3val:0x393b; valaddr_reg:x4; val_offset:3231*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3231*FLEN/8, x5, x2, x3) + +inst_1103: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x354 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1b5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x13b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3754; op2val:0x3db5; +op3val:0x393b; valaddr_reg:x4; val_offset:3234*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3234*FLEN/8, x5, x2, x3) + +inst_1104: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x354 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1b5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x13b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3754; op2val:0x3db5; +op3val:0x393b; valaddr_reg:x4; val_offset:3237*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 3237*FLEN/8, x5, x2, x3) + +inst_1105: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x348 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x013 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x36c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3748; op2val:0x3413; +op3val:0x2f6c; valaddr_reg:x4; val_offset:3240*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3240*FLEN/8, x5, x2, x3) + +inst_1106: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x348 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x013 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x36c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3748; op2val:0x3413; +op3val:0x2f6c; valaddr_reg:x4; val_offset:3243*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3243*FLEN/8, x5, x2, x3) + +inst_1107: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x348 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x013 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x36c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3748; op2val:0x3413; +op3val:0x2f6c; valaddr_reg:x4; val_offset:3246*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3246*FLEN/8, x5, x2, x3) + +inst_1108: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x348 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x013 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x36c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3748; op2val:0x3413; +op3val:0x2f6c; valaddr_reg:x4; val_offset:3249*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3249*FLEN/8, x5, x2, x3) + +inst_1109: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x348 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x013 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x36c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3748; op2val:0x3413; +op3val:0x2f6c; valaddr_reg:x4; val_offset:3252*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 3252*FLEN/8, x5, x2, x3) + +inst_1110: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x060 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x065 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x0d3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3860; op2val:0x2865; +op3val:0x24d3; valaddr_reg:x4; val_offset:3255*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3255*FLEN/8, x5, x2, x3) + +inst_1111: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x060 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x065 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x0d3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3860; op2val:0x2865; +op3val:0x24d3; valaddr_reg:x4; val_offset:3258*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3258*FLEN/8, x5, x2, x3) + +inst_1112: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x060 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x065 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x0d3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3860; op2val:0x2865; +op3val:0x24d3; valaddr_reg:x4; val_offset:3261*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3261*FLEN/8, x5, x2, x3) + +inst_1113: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x060 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x065 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x0d3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3860; op2val:0x2865; +op3val:0x24d3; valaddr_reg:x4; val_offset:3264*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3264*FLEN/8, x5, x2, x3) + +inst_1114: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x060 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x065 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x0d3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3860; op2val:0x2865; +op3val:0x24d3; valaddr_reg:x4; val_offset:3267*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 3267*FLEN/8, x5, x2, x3) + +inst_1115: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x081 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x2c6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3a2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3481; op2val:0x42c6; +op3val:0x3ba2; valaddr_reg:x4; val_offset:3270*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3270*FLEN/8, x5, x2, x3) + +inst_1116: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x081 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x2c6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3a2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3481; op2val:0x42c6; +op3val:0x3ba2; valaddr_reg:x4; val_offset:3273*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3273*FLEN/8, x5, x2, x3) + +inst_1117: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x081 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x2c6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3a2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3481; op2val:0x42c6; +op3val:0x3ba2; valaddr_reg:x4; val_offset:3276*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3276*FLEN/8, x5, x2, x3) + +inst_1118: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x081 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x2c6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3a2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3481; op2val:0x42c6; +op3val:0x3ba2; valaddr_reg:x4; val_offset:3279*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3279*FLEN/8, x5, x2, x3) + +inst_1119: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x081 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x2c6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3a2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3481; op2val:0x42c6; +op3val:0x3ba2; valaddr_reg:x4; val_offset:3282*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 3282*FLEN/8, x5, x2, x3) + +inst_1120: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x00d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x158 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x16a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x340d; op2val:0x3d58; +op3val:0x356a; valaddr_reg:x4; val_offset:3285*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3285*FLEN/8, x5, x2, x3) + +inst_1121: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x00d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x158 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x16a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x340d; op2val:0x3d58; +op3val:0x356a; valaddr_reg:x4; val_offset:3288*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3288*FLEN/8, x5, x2, x3) + +inst_1122: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x00d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x158 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x16a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x340d; op2val:0x3d58; +op3val:0x356a; valaddr_reg:x4; val_offset:3291*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3291*FLEN/8, x5, x2, x3) + +inst_1123: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x00d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x158 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x16a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x340d; op2val:0x3d58; +op3val:0x356a; valaddr_reg:x4; val_offset:3294*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3294*FLEN/8, x5, x2, x3) + +inst_1124: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x00d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x158 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x16a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x340d; op2val:0x3d58; +op3val:0x356a; valaddr_reg:x4; val_offset:3297*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 3297*FLEN/8, x5, x2, x3) + +inst_1125: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x20c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x145 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3f9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x360c; op2val:0x4145; +op3val:0x3bf9; valaddr_reg:x4; val_offset:3300*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3300*FLEN/8, x5, x2, x3) + +inst_1126: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x20c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x145 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3f9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x360c; op2val:0x4145; +op3val:0x3bf9; valaddr_reg:x4; val_offset:3303*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3303*FLEN/8, x5, x2, x3) + +inst_1127: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x20c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x145 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3f9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x360c; op2val:0x4145; +op3val:0x3bf9; valaddr_reg:x4; val_offset:3306*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3306*FLEN/8, x5, x2, x3) + +inst_1128: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x20c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x145 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3f9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x360c; op2val:0x4145; +op3val:0x3bf9; valaddr_reg:x4; val_offset:3309*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3309*FLEN/8, x5, x2, x3) + +inst_1129: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x20c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x145 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3f9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x360c; op2val:0x4145; +op3val:0x3bf9; valaddr_reg:x4; val_offset:3312*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 3312*FLEN/8, x5, x2, x3) + +inst_1130: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3c1 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x02a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x009 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2fc1; op2val:0x442a; +op3val:0x3809; valaddr_reg:x4; val_offset:3315*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3315*FLEN/8, x5, x2, x3) + +inst_1131: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3c1 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x02a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x009 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2fc1; op2val:0x442a; +op3val:0x3809; valaddr_reg:x4; val_offset:3318*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3318*FLEN/8, x5, x2, x3) + +inst_1132: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3c1 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x02a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x009 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2fc1; op2val:0x442a; +op3val:0x3809; valaddr_reg:x4; val_offset:3321*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3321*FLEN/8, x5, x2, x3) + +inst_1133: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3c1 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x02a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x009 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2fc1; op2val:0x442a; +op3val:0x3809; valaddr_reg:x4; val_offset:3324*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3324*FLEN/8, x5, x2, x3) + +inst_1134: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3c1 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x02a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x009 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2fc1; op2val:0x442a; +op3val:0x3809; valaddr_reg:x4; val_offset:3327*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 3327*FLEN/8, x5, x2, x3) + +inst_1135: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x369 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x329 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2a3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3769; op2val:0x3f29; +op3val:0x3aa3; valaddr_reg:x4; val_offset:3330*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3330*FLEN/8, x5, x2, x3) + +inst_1136: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x369 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x329 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2a3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3769; op2val:0x3f29; +op3val:0x3aa3; valaddr_reg:x4; val_offset:3333*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3333*FLEN/8, x5, x2, x3) + +inst_1137: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x369 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x329 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2a3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3769; op2val:0x3f29; +op3val:0x3aa3; valaddr_reg:x4; val_offset:3336*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3336*FLEN/8, x5, x2, x3) + +inst_1138: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x369 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x329 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2a3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3769; op2val:0x3f29; +op3val:0x3aa3; valaddr_reg:x4; val_offset:3339*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3339*FLEN/8, x5, x2, x3) + +inst_1139: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x369 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x329 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2a3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3769; op2val:0x3f29; +op3val:0x3aa3; valaddr_reg:x4; val_offset:3342*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 3342*FLEN/8, x5, x2, x3) + +inst_1140: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x016 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3e3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bb7; op2val:0x3c16; +op3val:0x3be3; valaddr_reg:x4; val_offset:3345*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3345*FLEN/8, x5, x2, x3) + +inst_1141: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x016 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3e3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bb7; op2val:0x3c16; +op3val:0x3be3; valaddr_reg:x4; val_offset:3348*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3348*FLEN/8, x5, x2, x3) + +inst_1142: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x016 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3e3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bb7; op2val:0x3c16; +op3val:0x3be3; valaddr_reg:x4; val_offset:3351*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3351*FLEN/8, x5, x2, x3) + +inst_1143: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x016 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3e3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bb7; op2val:0x3c16; +op3val:0x3be3; valaddr_reg:x4; val_offset:3354*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3354*FLEN/8, x5, x2, x3) + +inst_1144: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x016 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3e3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bb7; op2val:0x3c16; +op3val:0x3be3; valaddr_reg:x4; val_offset:3357*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 3357*FLEN/8, x5, x2, x3) + +inst_1145: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x252 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x30b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x191 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a52; op2val:0x3b0b; +op3val:0x3991; valaddr_reg:x4; val_offset:3360*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3360*FLEN/8, x5, x2, x3) + +inst_1146: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x252 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x30b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x191 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a52; op2val:0x3b0b; +op3val:0x3991; valaddr_reg:x4; val_offset:3363*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3363*FLEN/8, x5, x2, x3) + +inst_1147: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x252 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x30b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x191 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a52; op2val:0x3b0b; +op3val:0x3991; valaddr_reg:x4; val_offset:3366*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3366*FLEN/8, x5, x2, x3) + +inst_1148: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x252 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x30b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x191 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a52; op2val:0x3b0b; +op3val:0x3991; valaddr_reg:x4; val_offset:3369*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3369*FLEN/8, x5, x2, x3) + +inst_1149: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x252 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x30b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x191 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a52; op2val:0x3b0b; +op3val:0x3991; valaddr_reg:x4; val_offset:3372*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 3372*FLEN/8, x5, x2, x3) + +inst_1150: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2c4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x073 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x388 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ac4; op2val:0x3c73; +op3val:0x3b88; valaddr_reg:x4; val_offset:3375*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3375*FLEN/8, x5, x2, x3) + +inst_1151: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2c4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x073 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x388 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ac4; op2val:0x3c73; +op3val:0x3b88; valaddr_reg:x4; val_offset:3378*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3378*FLEN/8, x5, x2, x3) + +inst_1152: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2c4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x073 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x388 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ac4; op2val:0x3c73; +op3val:0x3b88; valaddr_reg:x4; val_offset:3381*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3381*FLEN/8, x5, x2, x3) + +inst_1153: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2c4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x073 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x388 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ac4; op2val:0x3c73; +op3val:0x3b88; valaddr_reg:x4; val_offset:3384*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3384*FLEN/8, x5, x2, x3) + +inst_1154: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2c4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x073 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x388 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ac4; op2val:0x3c73; +op3val:0x3b88; valaddr_reg:x4; val_offset:3387*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 3387*FLEN/8, x5, x2, x3) + +inst_1155: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x05c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x05d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0c2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x345c; op2val:0x3c5d; +op3val:0x34c2; valaddr_reg:x4; val_offset:3390*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3390*FLEN/8, x5, x2, x3) + +inst_1156: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x05c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x05d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0c2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x345c; op2val:0x3c5d; +op3val:0x34c2; valaddr_reg:x4; val_offset:3393*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3393*FLEN/8, x5, x2, x3) + +inst_1157: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x05c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x05d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0c2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x345c; op2val:0x3c5d; +op3val:0x34c2; valaddr_reg:x4; val_offset:3396*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3396*FLEN/8, x5, x2, x3) + +inst_1158: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x05c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x05d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0c2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x345c; op2val:0x3c5d; +op3val:0x34c2; valaddr_reg:x4; val_offset:3399*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3399*FLEN/8, x5, x2, x3) + +inst_1159: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x05c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x05d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0c2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x345c; op2val:0x3c5d; +op3val:0x34c2; valaddr_reg:x4; val_offset:3402*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 3402*FLEN/8, x5, x2, x3) + +inst_1160: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x38d and fs2 == 0 and fe2 == 0x11 and fm2 == 0x2a1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x242 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f8d; op2val:0x46a1; +op3val:0x3a42; valaddr_reg:x4; val_offset:3405*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3405*FLEN/8, x5, x2, x3) + +inst_1161: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x38d and fs2 == 0 and fe2 == 0x11 and fm2 == 0x2a1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x242 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f8d; op2val:0x46a1; +op3val:0x3a42; valaddr_reg:x4; val_offset:3408*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3408*FLEN/8, x5, x2, x3) + +inst_1162: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x38d and fs2 == 0 and fe2 == 0x11 and fm2 == 0x2a1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x242 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f8d; op2val:0x46a1; +op3val:0x3a42; valaddr_reg:x4; val_offset:3411*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3411*FLEN/8, x5, x2, x3) + +inst_1163: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x38d and fs2 == 0 and fe2 == 0x11 and fm2 == 0x2a1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x242 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f8d; op2val:0x46a1; +op3val:0x3a42; valaddr_reg:x4; val_offset:3414*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3414*FLEN/8, x5, x2, x3) + +inst_1164: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x38d and fs2 == 0 and fe2 == 0x11 and fm2 == 0x2a1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x242 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f8d; op2val:0x46a1; +op3val:0x3a42; valaddr_reg:x4; val_offset:3417*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 3417*FLEN/8, x5, x2, x3) + +inst_1165: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x058 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1f8 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x27d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3458; op2val:0x3df8; +op3val:0x367d; valaddr_reg:x4; val_offset:3420*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3420*FLEN/8, x5, x2, x3) + +inst_1166: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x058 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1f8 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x27d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3458; op2val:0x3df8; +op3val:0x367d; valaddr_reg:x4; val_offset:3423*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3423*FLEN/8, x5, x2, x3) + +inst_1167: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x058 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1f8 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x27d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3458; op2val:0x3df8; +op3val:0x367d; valaddr_reg:x4; val_offset:3426*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3426*FLEN/8, x5, x2, x3) + +inst_1168: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x058 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1f8 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x27d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3458; op2val:0x3df8; +op3val:0x367d; valaddr_reg:x4; val_offset:3429*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3429*FLEN/8, x5, x2, x3) + +inst_1169: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x058 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1f8 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x27d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3458; op2val:0x3df8; +op3val:0x367d; valaddr_reg:x4; val_offset:3432*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 3432*FLEN/8, x5, x2, x3) + +inst_1170: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x347 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x065 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b47; op2val:0x3065; +op3val:0x3000; valaddr_reg:x4; val_offset:3435*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3435*FLEN/8, x5, x2, x3) + +inst_1171: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x347 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x065 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b47; op2val:0x3065; +op3val:0x3000; valaddr_reg:x4; val_offset:3438*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3438*FLEN/8, x5, x2, x3) + +inst_1172: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x347 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x065 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b47; op2val:0x3065; +op3val:0x3000; valaddr_reg:x4; val_offset:3441*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3441*FLEN/8, x5, x2, x3) + +inst_1173: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x347 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x065 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b47; op2val:0x3065; +op3val:0x3000; valaddr_reg:x4; val_offset:3444*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3444*FLEN/8, x5, x2, x3) + +inst_1174: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x347 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x065 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b47; op2val:0x3065; +op3val:0x3000; valaddr_reg:x4; val_offset:3447*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 3447*FLEN/8, x5, x2, x3) + +inst_1175: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x124 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x112 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x285 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3924; op2val:0x3d12; +op3val:0x3a85; valaddr_reg:x4; val_offset:3450*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3450*FLEN/8, x5, x2, x3) + +inst_1176: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x124 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x112 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x285 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3924; op2val:0x3d12; +op3val:0x3a85; valaddr_reg:x4; val_offset:3453*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3453*FLEN/8, x5, x2, x3) + +inst_1177: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x124 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x112 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x285 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3924; op2val:0x3d12; +op3val:0x3a85; valaddr_reg:x4; val_offset:3456*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3456*FLEN/8, x5, x2, x3) + +inst_1178: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x124 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x112 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x285 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3924; op2val:0x3d12; +op3val:0x3a85; valaddr_reg:x4; val_offset:3459*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3459*FLEN/8, x5, x2, x3) + +inst_1179: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x124 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x112 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x285 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3924; op2val:0x3d12; +op3val:0x3a85; valaddr_reg:x4; val_offset:3462*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 3462*FLEN/8, x5, x2, x3) + +inst_1180: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x288 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x1ed and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0d8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a88; op2val:0x2ded; +op3val:0x2cd8; valaddr_reg:x4; val_offset:3465*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3465*FLEN/8, x5, x2, x3) + +inst_1181: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x288 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x1ed and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0d8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a88; op2val:0x2ded; +op3val:0x2cd8; valaddr_reg:x4; val_offset:3468*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3468*FLEN/8, x5, x2, x3) +RVTEST_SIGBASE(x2,signature_x2_9) + +inst_1182: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x288 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x1ed and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0d8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a88; op2val:0x2ded; +op3val:0x2cd8; valaddr_reg:x4; val_offset:3471*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3471*FLEN/8, x5, x2, x3) + +inst_1183: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x288 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x1ed and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0d8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a88; op2val:0x2ded; +op3val:0x2cd8; valaddr_reg:x4; val_offset:3474*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3474*FLEN/8, x5, x2, x3) + +inst_1184: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x288 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x1ed and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0d8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a88; op2val:0x2ded; +op3val:0x2cd8; valaddr_reg:x4; val_offset:3477*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 3477*FLEN/8, x5, x2, x3) + +inst_1185: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x252 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0ec and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a3b; op2val:0x3a52; +op3val:0x38ec; valaddr_reg:x4; val_offset:3480*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3480*FLEN/8, x5, x2, x3) + +inst_1186: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x252 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0ec and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a3b; op2val:0x3a52; +op3val:0x38ec; valaddr_reg:x4; val_offset:3483*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3483*FLEN/8, x5, x2, x3) + +inst_1187: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x252 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0ec and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a3b; op2val:0x3a52; +op3val:0x38ec; valaddr_reg:x4; val_offset:3486*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3486*FLEN/8, x5, x2, x3) + +inst_1188: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x252 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0ec and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a3b; op2val:0x3a52; +op3val:0x38ec; valaddr_reg:x4; val_offset:3489*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3489*FLEN/8, x5, x2, x3) + +inst_1189: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x252 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0ec and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a3b; op2val:0x3a52; +op3val:0x38ec; valaddr_reg:x4; val_offset:3492*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 3492*FLEN/8, x5, x2, x3) + +inst_1190: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x33f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1a8 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x120 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x373f; op2val:0x3da8; +op3val:0x3920; valaddr_reg:x4; val_offset:3495*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3495*FLEN/8, x5, x2, x3) + +inst_1191: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x33f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1a8 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x120 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x373f; op2val:0x3da8; +op3val:0x3920; valaddr_reg:x4; val_offset:3498*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3498*FLEN/8, x5, x2, x3) + +inst_1192: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x33f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1a8 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x120 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x373f; op2val:0x3da8; +op3val:0x3920; valaddr_reg:x4; val_offset:3501*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3501*FLEN/8, x5, x2, x3) + +inst_1193: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x33f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1a8 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x120 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x373f; op2val:0x3da8; +op3val:0x3920; valaddr_reg:x4; val_offset:3504*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3504*FLEN/8, x5, x2, x3) + +inst_1194: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x33f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1a8 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x120 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x373f; op2val:0x3da8; +op3val:0x3920; valaddr_reg:x4; val_offset:3507*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 3507*FLEN/8, x5, x2, x3) + +inst_1195: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x181 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x14d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x34c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3581; op2val:0x414d; +op3val:0x3b4c; valaddr_reg:x4; val_offset:3510*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3510*FLEN/8, x5, x2, x3) + +inst_1196: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x181 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x14d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x34c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3581; op2val:0x414d; +op3val:0x3b4c; valaddr_reg:x4; val_offset:3513*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3513*FLEN/8, x5, x2, x3) + +inst_1197: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x181 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x14d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x34c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3581; op2val:0x414d; +op3val:0x3b4c; valaddr_reg:x4; val_offset:3516*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3516*FLEN/8, x5, x2, x3) + +inst_1198: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x181 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x14d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x34c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3581; op2val:0x414d; +op3val:0x3b4c; valaddr_reg:x4; val_offset:3519*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3519*FLEN/8, x5, x2, x3) + +inst_1199: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x181 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x14d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x34c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3581; op2val:0x414d; +op3val:0x3b4c; valaddr_reg:x4; val_offset:3522*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 3522*FLEN/8, x5, x2, x3) + +inst_1200: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x08f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1d4 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2a5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x388f; op2val:0x39d4; +op3val:0x36a5; valaddr_reg:x4; val_offset:3525*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3525*FLEN/8, x5, x2, x3) + +inst_1201: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x08f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1d4 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2a5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x388f; op2val:0x39d4; +op3val:0x36a5; valaddr_reg:x4; val_offset:3528*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3528*FLEN/8, x5, x2, x3) + +inst_1202: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x08f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1d4 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2a5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x388f; op2val:0x39d4; +op3val:0x36a5; valaddr_reg:x4; val_offset:3531*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3531*FLEN/8, x5, x2, x3) + +inst_1203: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x08f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1d4 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2a5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x388f; op2val:0x39d4; +op3val:0x36a5; valaddr_reg:x4; val_offset:3534*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3534*FLEN/8, x5, x2, x3) + +inst_1204: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x08f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1d4 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2a5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x388f; op2val:0x39d4; +op3val:0x36a5; valaddr_reg:x4; val_offset:3537*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 3537*FLEN/8, x5, x2, x3) + +inst_1205: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x218 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x01a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x241 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3618; op2val:0x3c1a; +op3val:0x3641; valaddr_reg:x4; val_offset:3540*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3540*FLEN/8, x5, x2, x3) + +inst_1206: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x218 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x01a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x241 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3618; op2val:0x3c1a; +op3val:0x3641; valaddr_reg:x4; val_offset:3543*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3543*FLEN/8, x5, x2, x3) + +inst_1207: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x218 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x01a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x241 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3618; op2val:0x3c1a; +op3val:0x3641; valaddr_reg:x4; val_offset:3546*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3546*FLEN/8, x5, x2, x3) + +inst_1208: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x218 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x01a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x241 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3618; op2val:0x3c1a; +op3val:0x3641; valaddr_reg:x4; val_offset:3549*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3549*FLEN/8, x5, x2, x3) + +inst_1209: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x218 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x01a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x241 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3618; op2val:0x3c1a; +op3val:0x3641; valaddr_reg:x4; val_offset:3552*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 3552*FLEN/8, x5, x2, x3) + +inst_1210: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1d8 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3eb and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1ca and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39d8; op2val:0x37eb; +op3val:0x35ca; valaddr_reg:x4; val_offset:3555*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3555*FLEN/8, x5, x2, x3) + +inst_1211: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1d8 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3eb and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1ca and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39d8; op2val:0x37eb; +op3val:0x35ca; valaddr_reg:x4; val_offset:3558*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3558*FLEN/8, x5, x2, x3) + +inst_1212: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1d8 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3eb and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1ca and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39d8; op2val:0x37eb; +op3val:0x35ca; valaddr_reg:x4; val_offset:3561*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3561*FLEN/8, x5, x2, x3) + +inst_1213: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1d8 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3eb and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1ca and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39d8; op2val:0x37eb; +op3val:0x35ca; valaddr_reg:x4; val_offset:3564*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3564*FLEN/8, x5, x2, x3) + +inst_1214: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1d8 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3eb and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1ca and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39d8; op2val:0x37eb; +op3val:0x35ca; valaddr_reg:x4; val_offset:3567*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 3567*FLEN/8, x5, x2, x3) + +inst_1215: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x322 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x0a4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x024 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2722; op2val:0x4ca4; +op3val:0x3824; valaddr_reg:x4; val_offset:3570*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3570*FLEN/8, x5, x2, x3) + +inst_1216: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x322 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x0a4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x024 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2722; op2val:0x4ca4; +op3val:0x3824; valaddr_reg:x4; val_offset:3573*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3573*FLEN/8, x5, x2, x3) + +inst_1217: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x322 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x0a4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x024 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2722; op2val:0x4ca4; +op3val:0x3824; valaddr_reg:x4; val_offset:3576*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3576*FLEN/8, x5, x2, x3) + +inst_1218: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x322 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x0a4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x024 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2722; op2val:0x4ca4; +op3val:0x3824; valaddr_reg:x4; val_offset:3579*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3579*FLEN/8, x5, x2, x3) + +inst_1219: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x322 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x0a4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x024 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2722; op2val:0x4ca4; +op3val:0x3824; valaddr_reg:x4; val_offset:3582*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 3582*FLEN/8, x5, x2, x3) + +inst_1220: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1b2 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x353 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x138 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35b2; op2val:0x3753; +op3val:0x3138; valaddr_reg:x4; val_offset:3585*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3585*FLEN/8, x5, x2, x3) + +inst_1221: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1b2 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x353 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x138 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35b2; op2val:0x3753; +op3val:0x3138; valaddr_reg:x4; val_offset:3588*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3588*FLEN/8, x5, x2, x3) + +inst_1222: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1b2 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x353 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x138 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35b2; op2val:0x3753; +op3val:0x3138; valaddr_reg:x4; val_offset:3591*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3591*FLEN/8, x5, x2, x3) + +inst_1223: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1b2 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x353 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x138 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35b2; op2val:0x3753; +op3val:0x3138; valaddr_reg:x4; val_offset:3594*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3594*FLEN/8, x5, x2, x3) + +inst_1224: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1b2 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x353 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x138 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35b2; op2val:0x3753; +op3val:0x3138; valaddr_reg:x4; val_offset:3597*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 3597*FLEN/8, x5, x2, x3) + +inst_1225: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3db and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39fb; op2val:0x3bdb; +op3val:0x39e0; valaddr_reg:x4; val_offset:3600*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3600*FLEN/8, x5, x2, x3) + +inst_1226: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3db and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39fb; op2val:0x3bdb; +op3val:0x39e0; valaddr_reg:x4; val_offset:3603*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3603*FLEN/8, x5, x2, x3) + +inst_1227: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3db and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39fb; op2val:0x3bdb; +op3val:0x39e0; valaddr_reg:x4; val_offset:3606*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3606*FLEN/8, x5, x2, x3) + +inst_1228: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3db and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39fb; op2val:0x3bdb; +op3val:0x39e0; valaddr_reg:x4; val_offset:3609*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3609*FLEN/8, x5, x2, x3) + +inst_1229: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3db and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39fb; op2val:0x3bdb; +op3val:0x39e0; valaddr_reg:x4; val_offset:3612*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 3612*FLEN/8, x5, x2, x3) + +inst_1230: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x3a3 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x1db and fs3 == 0 and fe3 == 0x0e and fm3 == 0x198 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x27a3; op2val:0x4ddb; +op3val:0x3998; valaddr_reg:x4; val_offset:3615*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3615*FLEN/8, x5, x2, x3) + +inst_1231: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x3a3 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x1db and fs3 == 0 and fe3 == 0x0e and fm3 == 0x198 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x27a3; op2val:0x4ddb; +op3val:0x3998; valaddr_reg:x4; val_offset:3618*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3618*FLEN/8, x5, x2, x3) + +inst_1232: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x3a3 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x1db and fs3 == 0 and fe3 == 0x0e and fm3 == 0x198 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x27a3; op2val:0x4ddb; +op3val:0x3998; valaddr_reg:x4; val_offset:3621*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3621*FLEN/8, x5, x2, x3) + +inst_1233: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x3a3 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x1db and fs3 == 0 and fe3 == 0x0e and fm3 == 0x198 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x27a3; op2val:0x4ddb; +op3val:0x3998; valaddr_reg:x4; val_offset:3624*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3624*FLEN/8, x5, x2, x3) + +inst_1234: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x3a3 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x1db and fs3 == 0 and fe3 == 0x0e and fm3 == 0x198 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x27a3; op2val:0x4ddb; +op3val:0x3998; valaddr_reg:x4; val_offset:3627*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 3627*FLEN/8, x5, x2, x3) + +inst_1235: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x097 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x062 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x108 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3897; op2val:0x3c62; +op3val:0x3908; valaddr_reg:x4; val_offset:3630*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3630*FLEN/8, x5, x2, x3) + +inst_1236: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x097 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x062 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x108 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3897; op2val:0x3c62; +op3val:0x3908; valaddr_reg:x4; val_offset:3633*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3633*FLEN/8, x5, x2, x3) + +inst_1237: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x097 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x062 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x108 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3897; op2val:0x3c62; +op3val:0x3908; valaddr_reg:x4; val_offset:3636*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3636*FLEN/8, x5, x2, x3) + +inst_1238: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x097 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x062 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x108 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3897; op2val:0x3c62; +op3val:0x3908; valaddr_reg:x4; val_offset:3639*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3639*FLEN/8, x5, x2, x3) + +inst_1239: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x097 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x062 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x108 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3897; op2val:0x3c62; +op3val:0x3908; valaddr_reg:x4; val_offset:3642*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 3642*FLEN/8, x5, x2, x3) + +inst_1240: +// fs1 == 0 and fe1 == 0x07 and fm1 == 0x313 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x01d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x347 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1f13; op2val:0x541d; +op3val:0x3747; valaddr_reg:x4; val_offset:3645*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3645*FLEN/8, x5, x2, x3) + +inst_1241: +// fs1 == 0 and fe1 == 0x07 and fm1 == 0x313 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x01d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x347 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1f13; op2val:0x541d; +op3val:0x3747; valaddr_reg:x4; val_offset:3648*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3648*FLEN/8, x5, x2, x3) + +inst_1242: +// fs1 == 0 and fe1 == 0x07 and fm1 == 0x313 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x01d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x347 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1f13; op2val:0x541d; +op3val:0x3747; valaddr_reg:x4; val_offset:3651*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3651*FLEN/8, x5, x2, x3) + +inst_1243: +// fs1 == 0 and fe1 == 0x07 and fm1 == 0x313 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x01d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x347 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1f13; op2val:0x541d; +op3val:0x3747; valaddr_reg:x4; val_offset:3654*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3654*FLEN/8, x5, x2, x3) + +inst_1244: +// fs1 == 0 and fe1 == 0x07 and fm1 == 0x313 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x01d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x347 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1f13; op2val:0x541d; +op3val:0x3747; valaddr_reg:x4; val_offset:3657*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 3657*FLEN/8, x5, x2, x3) + +inst_1245: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2a6 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x007 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ea6; op2val:0x4807; +op3val:0x3ab3; valaddr_reg:x4; val_offset:3660*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3660*FLEN/8, x5, x2, x3) + +inst_1246: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2a6 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x007 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ea6; op2val:0x4807; +op3val:0x3ab3; valaddr_reg:x4; val_offset:3663*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3663*FLEN/8, x5, x2, x3) + +inst_1247: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2a6 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x007 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ea6; op2val:0x4807; +op3val:0x3ab3; valaddr_reg:x4; val_offset:3666*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3666*FLEN/8, x5, x2, x3) + +inst_1248: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2a6 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x007 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ea6; op2val:0x4807; +op3val:0x3ab3; valaddr_reg:x4; val_offset:3669*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3669*FLEN/8, x5, x2, x3) + +inst_1249: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2a6 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x007 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ea6; op2val:0x4807; +op3val:0x3ab3; valaddr_reg:x4; val_offset:3672*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 3672*FLEN/8, x5, x2, x3) + +inst_1250: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3c1 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x19a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39c7; op2val:0x37c1; +op3val:0x359a; valaddr_reg:x4; val_offset:3675*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3675*FLEN/8, x5, x2, x3) + +inst_1251: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3c1 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x19a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39c7; op2val:0x37c1; +op3val:0x359a; valaddr_reg:x4; val_offset:3678*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3678*FLEN/8, x5, x2, x3) + +inst_1252: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3c1 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x19a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39c7; op2val:0x37c1; +op3val:0x359a; valaddr_reg:x4; val_offset:3681*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3681*FLEN/8, x5, x2, x3) + +inst_1253: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3c1 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x19a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39c7; op2val:0x37c1; +op3val:0x359a; valaddr_reg:x4; val_offset:3684*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3684*FLEN/8, x5, x2, x3) + +inst_1254: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3c1 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x19a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39c7; op2val:0x37c1; +op3val:0x359a; valaddr_reg:x4; val_offset:3687*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 3687*FLEN/8, x5, x2, x3) + +inst_1255: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x174 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3e6 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x163 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3974; op2val:0x37e6; +op3val:0x3563; valaddr_reg:x4; val_offset:3690*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3690*FLEN/8, x5, x2, x3) + +inst_1256: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x174 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3e6 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x163 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3974; op2val:0x37e6; +op3val:0x3563; valaddr_reg:x4; val_offset:3693*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3693*FLEN/8, x5, x2, x3) + +inst_1257: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x174 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3e6 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x163 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3974; op2val:0x37e6; +op3val:0x3563; valaddr_reg:x4; val_offset:3696*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3696*FLEN/8, x5, x2, x3) + +inst_1258: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x174 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3e6 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x163 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3974; op2val:0x37e6; +op3val:0x3563; valaddr_reg:x4; val_offset:3699*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3699*FLEN/8, x5, x2, x3) + +inst_1259: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x174 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3e6 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x163 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3974; op2val:0x37e6; +op3val:0x3563; valaddr_reg:x4; val_offset:3702*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 3702*FLEN/8, x5, x2, x3) + +inst_1260: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x01f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x30a and fs3 == 0 and fe3 == 0x11 and fm3 == 0x1ec and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x501f; op2val:0xbf0a; +op3val:0x45ec; valaddr_reg:x4; val_offset:3705*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3705*FLEN/8, x5, x2, x3) + +inst_1261: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x01f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x30a and fs3 == 0 and fe3 == 0x11 and fm3 == 0x1ec and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x501f; op2val:0xbf0a; +op3val:0x45ec; valaddr_reg:x4; val_offset:3708*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3708*FLEN/8, x5, x2, x3) + +inst_1262: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x01f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x30a and fs3 == 0 and fe3 == 0x11 and fm3 == 0x1ec and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x501f; op2val:0xbf0a; +op3val:0x45ec; valaddr_reg:x4; val_offset:3711*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3711*FLEN/8, x5, x2, x3) + +inst_1263: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x01f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x30a and fs3 == 0 and fe3 == 0x11 and fm3 == 0x1ec and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x501f; op2val:0xbf0a; +op3val:0x45ec; valaddr_reg:x4; val_offset:3714*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3714*FLEN/8, x5, x2, x3) + +inst_1264: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x01f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x30a and fs3 == 0 and fe3 == 0x11 and fm3 == 0x1ec and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x501f; op2val:0xbf0a; +op3val:0x45ec; valaddr_reg:x4; val_offset:3717*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 3717*FLEN/8, x5, x2, x3) + +inst_1265: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x005 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x065 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x328 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4805; op2val:0xc465; +op3val:0x4f28; valaddr_reg:x4; val_offset:3720*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3720*FLEN/8, x5, x2, x3) + +inst_1266: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x005 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x065 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x328 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4805; op2val:0xc465; +op3val:0x4f28; valaddr_reg:x4; val_offset:3723*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3723*FLEN/8, x5, x2, x3) + +inst_1267: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x005 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x065 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x328 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4805; op2val:0xc465; +op3val:0x4f28; valaddr_reg:x4; val_offset:3726*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3726*FLEN/8, x5, x2, x3) + +inst_1268: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x005 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x065 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x328 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4805; op2val:0xc465; +op3val:0x4f28; valaddr_reg:x4; val_offset:3729*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3729*FLEN/8, x5, x2, x3) + +inst_1269: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x005 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x065 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x328 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4805; op2val:0xc465; +op3val:0x4f28; valaddr_reg:x4; val_offset:3732*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 3732*FLEN/8, x5, x2, x3) + +inst_1270: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x053 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1fe and fs3 == 0 and fe3 == 0x12 and fm3 == 0x20f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5053; op2val:0xbdfe; +op3val:0x4a0f; valaddr_reg:x4; val_offset:3735*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3735*FLEN/8, x5, x2, x3) + +inst_1271: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x053 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1fe and fs3 == 0 and fe3 == 0x12 and fm3 == 0x20f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5053; op2val:0xbdfe; +op3val:0x4a0f; valaddr_reg:x4; val_offset:3738*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3738*FLEN/8, x5, x2, x3) + +inst_1272: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x053 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1fe and fs3 == 0 and fe3 == 0x12 and fm3 == 0x20f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5053; op2val:0xbdfe; +op3val:0x4a0f; valaddr_reg:x4; val_offset:3741*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3741*FLEN/8, x5, x2, x3) + +inst_1273: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x053 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1fe and fs3 == 0 and fe3 == 0x12 and fm3 == 0x20f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5053; op2val:0xbdfe; +op3val:0x4a0f; valaddr_reg:x4; val_offset:3744*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3744*FLEN/8, x5, x2, x3) + +inst_1274: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x053 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1fe and fs3 == 0 and fe3 == 0x12 and fm3 == 0x20f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5053; op2val:0xbdfe; +op3val:0x4a0f; valaddr_reg:x4; val_offset:3747*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 3747*FLEN/8, x5, x2, x3) + +inst_1275: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x065 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x328 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x04d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c65; op2val:0xc328; +op3val:0x3c4d; valaddr_reg:x4; val_offset:3750*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3750*FLEN/8, x5, x2, x3) + +inst_1276: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x065 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x328 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x04d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c65; op2val:0xc328; +op3val:0x3c4d; valaddr_reg:x4; val_offset:3753*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3753*FLEN/8, x5, x2, x3) + +inst_1277: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x065 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x328 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x04d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c65; op2val:0xc328; +op3val:0x3c4d; valaddr_reg:x4; val_offset:3756*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3756*FLEN/8, x5, x2, x3) + +inst_1278: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x065 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x328 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x04d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c65; op2val:0xc328; +op3val:0x3c4d; valaddr_reg:x4; val_offset:3759*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3759*FLEN/8, x5, x2, x3) + +inst_1279: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x065 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x328 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x04d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c65; op2val:0xc328; +op3val:0x3c4d; valaddr_reg:x4; val_offset:3762*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 3762*FLEN/8, x5, x2, x3) + +inst_1280: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x070 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0e7 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x11e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c70; op2val:0xc0e7; +op3val:0x4d1e; valaddr_reg:x4; val_offset:3765*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3765*FLEN/8, x5, x2, x3) + +inst_1281: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x070 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0e7 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x11e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c70; op2val:0xc0e7; +op3val:0x4d1e; valaddr_reg:x4; val_offset:3768*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3768*FLEN/8, x5, x2, x3) + +inst_1282: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x070 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0e7 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x11e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c70; op2val:0xc0e7; +op3val:0x4d1e; valaddr_reg:x4; val_offset:3771*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3771*FLEN/8, x5, x2, x3) + +inst_1283: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x070 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0e7 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x11e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c70; op2val:0xc0e7; +op3val:0x4d1e; valaddr_reg:x4; val_offset:3774*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3774*FLEN/8, x5, x2, x3) + +inst_1284: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x070 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0e7 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x11e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c70; op2val:0xc0e7; +op3val:0x4d1e; valaddr_reg:x4; val_offset:3777*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 3777*FLEN/8, x5, x2, x3) + +inst_1285: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x25e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x006 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0cc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4e5e; op2val:0xbc06; +op3val:0x50cc; valaddr_reg:x4; val_offset:3780*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3780*FLEN/8, x5, x2, x3) + +inst_1286: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x25e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x006 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0cc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4e5e; op2val:0xbc06; +op3val:0x50cc; valaddr_reg:x4; val_offset:3783*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3783*FLEN/8, x5, x2, x3) + +inst_1287: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x25e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x006 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0cc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4e5e; op2val:0xbc06; +op3val:0x50cc; valaddr_reg:x4; val_offset:3786*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3786*FLEN/8, x5, x2, x3) + +inst_1288: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x25e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x006 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0cc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4e5e; op2val:0xbc06; +op3val:0x50cc; valaddr_reg:x4; val_offset:3789*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3789*FLEN/8, x5, x2, x3) + +inst_1289: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x25e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x006 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0cc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4e5e; op2val:0xbc06; +op3val:0x50cc; valaddr_reg:x4; val_offset:3792*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 3792*FLEN/8, x5, x2, x3) + +inst_1290: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2d7 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x135 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x1c6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x52d7; op2val:0xb535; +op3val:0x51c6; valaddr_reg:x4; val_offset:3795*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3795*FLEN/8, x5, x2, x3) + +inst_1291: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2d7 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x135 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x1c6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x52d7; op2val:0xb535; +op3val:0x51c6; valaddr_reg:x4; val_offset:3798*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3798*FLEN/8, x5, x2, x3) + +inst_1292: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2d7 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x135 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x1c6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x52d7; op2val:0xb535; +op3val:0x51c6; valaddr_reg:x4; val_offset:3801*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3801*FLEN/8, x5, x2, x3) + +inst_1293: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2d7 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x135 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x1c6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x52d7; op2val:0xb535; +op3val:0x51c6; valaddr_reg:x4; val_offset:3804*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3804*FLEN/8, x5, x2, x3) + +inst_1294: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2d7 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x135 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x1c6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x52d7; op2val:0xb535; +op3val:0x51c6; valaddr_reg:x4; val_offset:3807*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 3807*FLEN/8, x5, x2, x3) + +inst_1295: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1f5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x394 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x0b4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x51f5; op2val:0xbb94; +op3val:0x4cb4; valaddr_reg:x4; val_offset:3810*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3810*FLEN/8, x5, x2, x3) + +inst_1296: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1f5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x394 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x0b4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x51f5; op2val:0xbb94; +op3val:0x4cb4; valaddr_reg:x4; val_offset:3813*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3813*FLEN/8, x5, x2, x3) + +inst_1297: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1f5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x394 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x0b4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x51f5; op2val:0xbb94; +op3val:0x4cb4; valaddr_reg:x4; val_offset:3816*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3816*FLEN/8, x5, x2, x3) + +inst_1298: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1f5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x394 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x0b4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x51f5; op2val:0xbb94; +op3val:0x4cb4; valaddr_reg:x4; val_offset:3819*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3819*FLEN/8, x5, x2, x3) + +inst_1299: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1f5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x394 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x0b4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x51f5; op2val:0xbb94; +op3val:0x4cb4; valaddr_reg:x4; val_offset:3822*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 3822*FLEN/8, x5, x2, x3) + +inst_1300: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x045 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x1d9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5007; op2val:0xb845; +op3val:0x51d9; valaddr_reg:x4; val_offset:3825*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3825*FLEN/8, x5, x2, x3) + +inst_1301: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x045 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x1d9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5007; op2val:0xb845; +op3val:0x51d9; valaddr_reg:x4; val_offset:3828*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3828*FLEN/8, x5, x2, x3) + +inst_1302: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x045 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x1d9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5007; op2val:0xb845; +op3val:0x51d9; valaddr_reg:x4; val_offset:3831*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3831*FLEN/8, x5, x2, x3) + +inst_1303: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x045 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x1d9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5007; op2val:0xb845; +op3val:0x51d9; valaddr_reg:x4; val_offset:3834*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3834*FLEN/8, x5, x2, x3) + +inst_1304: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x045 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x1d9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5007; op2val:0xb845; +op3val:0x51d9; valaddr_reg:x4; val_offset:3837*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 3837*FLEN/8, x5, x2, x3) + +inst_1305: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x32a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2ae and fs3 == 0 and fe3 == 0x13 and fm3 == 0x009 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x532a; op2val:0xbaae; +op3val:0x4c09; valaddr_reg:x4; val_offset:3840*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3840*FLEN/8, x5, x2, x3) + +inst_1306: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x32a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2ae and fs3 == 0 and fe3 == 0x13 and fm3 == 0x009 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x532a; op2val:0xbaae; +op3val:0x4c09; valaddr_reg:x4; val_offset:3843*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3843*FLEN/8, x5, x2, x3) + +inst_1307: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x32a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2ae and fs3 == 0 and fe3 == 0x13 and fm3 == 0x009 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x532a; op2val:0xbaae; +op3val:0x4c09; valaddr_reg:x4; val_offset:3846*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3846*FLEN/8, x5, x2, x3) + +inst_1308: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x32a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2ae and fs3 == 0 and fe3 == 0x13 and fm3 == 0x009 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x532a; op2val:0xbaae; +op3val:0x4c09; valaddr_reg:x4; val_offset:3849*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3849*FLEN/8, x5, x2, x3) + +inst_1309: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x32a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2ae and fs3 == 0 and fe3 == 0x13 and fm3 == 0x009 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x532a; op2val:0xbaae; +op3val:0x4c09; valaddr_reg:x4; val_offset:3852*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 3852*FLEN/8, x5, x2, x3) +RVTEST_SIGBASE(x2,signature_x2_10) + +inst_1310: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x3cb and fs2 == 1 and fe2 == 0x13 and fm2 == 0x3ac and fs3 == 0 and fe3 == 0x11 and fm3 == 0x034 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3fcb; op2val:0xcfac; +op3val:0x4434; valaddr_reg:x4; val_offset:3855*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3855*FLEN/8, x5, x2, x3) + +inst_1311: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x3cb and fs2 == 1 and fe2 == 0x13 and fm2 == 0x3ac and fs3 == 0 and fe3 == 0x11 and fm3 == 0x034 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3fcb; op2val:0xcfac; +op3val:0x4434; valaddr_reg:x4; val_offset:3858*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3858*FLEN/8, x5, x2, x3) + +inst_1312: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x3cb and fs2 == 1 and fe2 == 0x13 and fm2 == 0x3ac and fs3 == 0 and fe3 == 0x11 and fm3 == 0x034 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3fcb; op2val:0xcfac; +op3val:0x4434; valaddr_reg:x4; val_offset:3861*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3861*FLEN/8, x5, x2, x3) + +inst_1313: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x3cb and fs2 == 1 and fe2 == 0x13 and fm2 == 0x3ac and fs3 == 0 and fe3 == 0x11 and fm3 == 0x034 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3fcb; op2val:0xcfac; +op3val:0x4434; valaddr_reg:x4; val_offset:3864*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3864*FLEN/8, x5, x2, x3) + +inst_1314: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x3cb and fs2 == 1 and fe2 == 0x13 and fm2 == 0x3ac and fs3 == 0 and fe3 == 0x11 and fm3 == 0x034 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3fcb; op2val:0xcfac; +op3val:0x4434; valaddr_reg:x4; val_offset:3867*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 3867*FLEN/8, x5, x2, x3) + +inst_1315: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x02f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3b2 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x2fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x502f; op2val:0xb3b2; +op3val:0x52fe; valaddr_reg:x4; val_offset:3870*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3870*FLEN/8, x5, x2, x3) + +inst_1316: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x02f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3b2 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x2fe and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x502f; op2val:0xb3b2; +op3val:0x52fe; valaddr_reg:x4; val_offset:3873*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3873*FLEN/8, x5, x2, x3) + +inst_1317: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x02f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3b2 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x2fe and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x502f; op2val:0xb3b2; +op3val:0x52fe; valaddr_reg:x4; val_offset:3876*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3876*FLEN/8, x5, x2, x3) + +inst_1318: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x02f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3b2 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x2fe and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x502f; op2val:0xb3b2; +op3val:0x52fe; valaddr_reg:x4; val_offset:3879*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3879*FLEN/8, x5, x2, x3) + +inst_1319: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x02f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3b2 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x2fe and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x502f; op2val:0xb3b2; +op3val:0x52fe; valaddr_reg:x4; val_offset:3882*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 3882*FLEN/8, x5, x2, x3) + +inst_1320: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x154 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x11c and fs3 == 0 and fe3 == 0x14 and fm3 == 0x24c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4954; op2val:0xbd1c; +op3val:0x524c; valaddr_reg:x4; val_offset:3885*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3885*FLEN/8, x5, x2, x3) + +inst_1321: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x154 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x11c and fs3 == 0 and fe3 == 0x14 and fm3 == 0x24c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4954; op2val:0xbd1c; +op3val:0x524c; valaddr_reg:x4; val_offset:3888*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3888*FLEN/8, x5, x2, x3) + +inst_1322: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x154 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x11c and fs3 == 0 and fe3 == 0x14 and fm3 == 0x24c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4954; op2val:0xbd1c; +op3val:0x524c; valaddr_reg:x4; val_offset:3891*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3891*FLEN/8, x5, x2, x3) + +inst_1323: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x154 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x11c and fs3 == 0 and fe3 == 0x14 and fm3 == 0x24c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4954; op2val:0xbd1c; +op3val:0x524c; valaddr_reg:x4; val_offset:3894*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3894*FLEN/8, x5, x2, x3) + +inst_1324: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x154 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x11c and fs3 == 0 and fe3 == 0x14 and fm3 == 0x24c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4954; op2val:0xbd1c; +op3val:0x524c; valaddr_reg:x4; val_offset:3897*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 3897*FLEN/8, x5, x2, x3) + +inst_1325: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x12c and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2a1 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x2ed and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x512c; op2val:0xb2a1; +op3val:0x52ed; valaddr_reg:x4; val_offset:3900*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3900*FLEN/8, x5, x2, x3) + +inst_1326: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x12c and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2a1 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x2ed and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x512c; op2val:0xb2a1; +op3val:0x52ed; valaddr_reg:x4; val_offset:3903*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3903*FLEN/8, x5, x2, x3) + +inst_1327: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x12c and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2a1 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x2ed and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x512c; op2val:0xb2a1; +op3val:0x52ed; valaddr_reg:x4; val_offset:3906*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3906*FLEN/8, x5, x2, x3) + +inst_1328: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x12c and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2a1 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x2ed and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x512c; op2val:0xb2a1; +op3val:0x52ed; valaddr_reg:x4; val_offset:3909*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3909*FLEN/8, x5, x2, x3) + +inst_1329: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x12c and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2a1 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x2ed and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x512c; op2val:0xb2a1; +op3val:0x52ed; valaddr_reg:x4; val_offset:3912*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 3912*FLEN/8, x5, x2, x3) + +inst_1330: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x338 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3c9 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x3c3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5338; op2val:0xbbc9; +op3val:0x47c3; valaddr_reg:x4; val_offset:3915*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3915*FLEN/8, x5, x2, x3) + +inst_1331: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x338 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3c9 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x3c3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5338; op2val:0xbbc9; +op3val:0x47c3; valaddr_reg:x4; val_offset:3918*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3918*FLEN/8, x5, x2, x3) + +inst_1332: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x338 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3c9 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x3c3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5338; op2val:0xbbc9; +op3val:0x47c3; valaddr_reg:x4; val_offset:3921*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3921*FLEN/8, x5, x2, x3) + +inst_1333: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x338 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3c9 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x3c3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5338; op2val:0xbbc9; +op3val:0x47c3; valaddr_reg:x4; val_offset:3924*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3924*FLEN/8, x5, x2, x3) + +inst_1334: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x338 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3c9 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x3c3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5338; op2val:0xbbc9; +op3val:0x47c3; valaddr_reg:x4; val_offset:3927*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 3927*FLEN/8, x5, x2, x3) + +inst_1335: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x260 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x045 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x0c3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5260; op2val:0xbc45; +op3val:0x48c3; valaddr_reg:x4; val_offset:3930*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3930*FLEN/8, x5, x2, x3) + +inst_1336: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x260 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x045 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x0c3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5260; op2val:0xbc45; +op3val:0x48c3; valaddr_reg:x4; val_offset:3933*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3933*FLEN/8, x5, x2, x3) + +inst_1337: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x260 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x045 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x0c3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5260; op2val:0xbc45; +op3val:0x48c3; valaddr_reg:x4; val_offset:3936*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3936*FLEN/8, x5, x2, x3) + +inst_1338: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x260 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x045 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x0c3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5260; op2val:0xbc45; +op3val:0x48c3; valaddr_reg:x4; val_offset:3939*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3939*FLEN/8, x5, x2, x3) + +inst_1339: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x260 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x045 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x0c3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5260; op2val:0xbc45; +op3val:0x48c3; valaddr_reg:x4; val_offset:3942*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 3942*FLEN/8, x5, x2, x3) + +inst_1340: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x03d and fs2 == 1 and fe2 == 0x11 and fm2 == 0x077 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x287 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x483d; op2val:0xc477; +op3val:0x4e87; valaddr_reg:x4; val_offset:3945*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3945*FLEN/8, x5, x2, x3) + +inst_1341: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x03d and fs2 == 1 and fe2 == 0x11 and fm2 == 0x077 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x287 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x483d; op2val:0xc477; +op3val:0x4e87; valaddr_reg:x4; val_offset:3948*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3948*FLEN/8, x5, x2, x3) + +inst_1342: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x03d and fs2 == 1 and fe2 == 0x11 and fm2 == 0x077 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x287 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x483d; op2val:0xc477; +op3val:0x4e87; valaddr_reg:x4; val_offset:3951*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3951*FLEN/8, x5, x2, x3) + +inst_1343: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x03d and fs2 == 1 and fe2 == 0x11 and fm2 == 0x077 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x287 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x483d; op2val:0xc477; +op3val:0x4e87; valaddr_reg:x4; val_offset:3954*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3954*FLEN/8, x5, x2, x3) + +inst_1344: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x03d and fs2 == 1 and fe2 == 0x11 and fm2 == 0x077 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x287 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x483d; op2val:0xc477; +op3val:0x4e87; valaddr_reg:x4; val_offset:3957*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 3957*FLEN/8, x5, x2, x3) + +inst_1345: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3f2 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x35f and fs3 == 0 and fe3 == 0x11 and fm3 == 0x164 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4ff2; op2val:0xbf5f; +op3val:0x4564; valaddr_reg:x4; val_offset:3960*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3960*FLEN/8, x5, x2, x3) + +inst_1346: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3f2 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x35f and fs3 == 0 and fe3 == 0x11 and fm3 == 0x164 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4ff2; op2val:0xbf5f; +op3val:0x4564; valaddr_reg:x4; val_offset:3963*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3963*FLEN/8, x5, x2, x3) + +inst_1347: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3f2 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x35f and fs3 == 0 and fe3 == 0x11 and fm3 == 0x164 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4ff2; op2val:0xbf5f; +op3val:0x4564; valaddr_reg:x4; val_offset:3966*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3966*FLEN/8, x5, x2, x3) + +inst_1348: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3f2 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x35f and fs3 == 0 and fe3 == 0x11 and fm3 == 0x164 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4ff2; op2val:0xbf5f; +op3val:0x4564; valaddr_reg:x4; val_offset:3969*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3969*FLEN/8, x5, x2, x3) + +inst_1349: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3f2 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x35f and fs3 == 0 and fe3 == 0x11 and fm3 == 0x164 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4ff2; op2val:0xbf5f; +op3val:0x4564; valaddr_reg:x4; val_offset:3972*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 3972*FLEN/8, x5, x2, x3) + +inst_1350: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x097 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1a8 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x207 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c97; op2val:0xc1a8; +op3val:0x4a07; valaddr_reg:x4; val_offset:3975*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3975*FLEN/8, x5, x2, x3) + +inst_1351: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x097 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1a8 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x207 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c97; op2val:0xc1a8; +op3val:0x4a07; valaddr_reg:x4; val_offset:3978*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3978*FLEN/8, x5, x2, x3) + +inst_1352: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x097 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1a8 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x207 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c97; op2val:0xc1a8; +op3val:0x4a07; valaddr_reg:x4; val_offset:3981*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3981*FLEN/8, x5, x2, x3) + +inst_1353: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x097 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1a8 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x207 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c97; op2val:0xc1a8; +op3val:0x4a07; valaddr_reg:x4; val_offset:3984*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3984*FLEN/8, x5, x2, x3) + +inst_1354: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x097 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1a8 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x207 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c97; op2val:0xc1a8; +op3val:0x4a07; valaddr_reg:x4; val_offset:3987*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 3987*FLEN/8, x5, x2, x3) + +inst_1355: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x0c0 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1f9 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x33a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x48c0; op2val:0xc5f9; +op3val:0x473a; valaddr_reg:x4; val_offset:3990*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 3990*FLEN/8, x5, x2, x3) + +inst_1356: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x0c0 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1f9 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x33a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x48c0; op2val:0xc5f9; +op3val:0x473a; valaddr_reg:x4; val_offset:3993*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 3993*FLEN/8, x5, x2, x3) + +inst_1357: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x0c0 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1f9 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x33a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x48c0; op2val:0xc5f9; +op3val:0x473a; valaddr_reg:x4; val_offset:3996*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 3996*FLEN/8, x5, x2, x3) + +inst_1358: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x0c0 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1f9 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x33a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x48c0; op2val:0xc5f9; +op3val:0x473a; valaddr_reg:x4; val_offset:3999*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 3999*FLEN/8, x5, x2, x3) + +inst_1359: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x0c0 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1f9 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x33a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x48c0; op2val:0xc5f9; +op3val:0x473a; valaddr_reg:x4; val_offset:4002*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4002*FLEN/8, x5, x2, x3) + +inst_1360: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x0fe and fs2 == 1 and fe2 == 0x13 and fm2 == 0x0ef and fs3 == 0 and fe3 == 0x12 and fm3 == 0x35a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x40fe; op2val:0xccef; +op3val:0x4b5a; valaddr_reg:x4; val_offset:4005*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4005*FLEN/8, x5, x2, x3) + +inst_1361: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x0fe and fs2 == 1 and fe2 == 0x13 and fm2 == 0x0ef and fs3 == 0 and fe3 == 0x12 and fm3 == 0x35a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x40fe; op2val:0xccef; +op3val:0x4b5a; valaddr_reg:x4; val_offset:4008*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4008*FLEN/8, x5, x2, x3) + +inst_1362: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x0fe and fs2 == 1 and fe2 == 0x13 and fm2 == 0x0ef and fs3 == 0 and fe3 == 0x12 and fm3 == 0x35a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x40fe; op2val:0xccef; +op3val:0x4b5a; valaddr_reg:x4; val_offset:4011*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 4011*FLEN/8, x5, x2, x3) + +inst_1363: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x0fe and fs2 == 1 and fe2 == 0x13 and fm2 == 0x0ef and fs3 == 0 and fe3 == 0x12 and fm3 == 0x35a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x40fe; op2val:0xccef; +op3val:0x4b5a; valaddr_reg:x4; val_offset:4014*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4014*FLEN/8, x5, x2, x3) + +inst_1364: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x0fe and fs2 == 1 and fe2 == 0x13 and fm2 == 0x0ef and fs3 == 0 and fe3 == 0x12 and fm3 == 0x35a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x40fe; op2val:0xccef; +op3val:0x4b5a; valaddr_reg:x4; val_offset:4017*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4017*FLEN/8, x5, x2, x3) + +inst_1365: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x167 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2c3 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x2dd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4d67; op2val:0xbec3; +op3val:0x4edd; valaddr_reg:x4; val_offset:4020*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4020*FLEN/8, x5, x2, x3) + +inst_1366: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x167 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2c3 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x2dd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4d67; op2val:0xbec3; +op3val:0x4edd; valaddr_reg:x4; val_offset:4023*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4023*FLEN/8, x5, x2, x3) + +inst_1367: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x167 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2c3 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x2dd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4d67; op2val:0xbec3; +op3val:0x4edd; valaddr_reg:x4; val_offset:4026*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 4026*FLEN/8, x5, x2, x3) + +inst_1368: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x167 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2c3 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x2dd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4d67; op2val:0xbec3; +op3val:0x4edd; valaddr_reg:x4; val_offset:4029*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4029*FLEN/8, x5, x2, x3) + +inst_1369: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x167 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2c3 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x2dd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4d67; op2val:0xbec3; +op3val:0x4edd; valaddr_reg:x4; val_offset:4032*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4032*FLEN/8, x5, x2, x3) + +inst_1370: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x198 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x05e and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0f1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5198; op2val:0xb85e; +op3val:0x50f1; valaddr_reg:x4; val_offset:4035*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4035*FLEN/8, x5, x2, x3) + +inst_1371: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x198 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x05e and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0f1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5198; op2val:0xb85e; +op3val:0x50f1; valaddr_reg:x4; val_offset:4038*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4038*FLEN/8, x5, x2, x3) + +inst_1372: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x198 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x05e and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0f1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5198; op2val:0xb85e; +op3val:0x50f1; valaddr_reg:x4; val_offset:4041*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 4041*FLEN/8, x5, x2, x3) + +inst_1373: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x198 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x05e and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0f1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5198; op2val:0xb85e; +op3val:0x50f1; valaddr_reg:x4; val_offset:4044*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4044*FLEN/8, x5, x2, x3) + +inst_1374: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x198 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x05e and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0f1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5198; op2val:0xb85e; +op3val:0x50f1; valaddr_reg:x4; val_offset:4047*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4047*FLEN/8, x5, x2, x3) + +inst_1375: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3ef and fs2 == 1 and fe2 == 0x0f and fm2 == 0x160 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x156 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4fef; op2val:0xbd60; +op3val:0x4d56; valaddr_reg:x4; val_offset:4050*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4050*FLEN/8, x5, x2, x3) + +inst_1376: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3ef and fs2 == 1 and fe2 == 0x0f and fm2 == 0x160 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x156 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4fef; op2val:0xbd60; +op3val:0x4d56; valaddr_reg:x4; val_offset:4053*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4053*FLEN/8, x5, x2, x3) + +inst_1377: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3ef and fs2 == 1 and fe2 == 0x0f and fm2 == 0x160 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x156 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4fef; op2val:0xbd60; +op3val:0x4d56; valaddr_reg:x4; val_offset:4056*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 4056*FLEN/8, x5, x2, x3) + +inst_1378: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3ef and fs2 == 1 and fe2 == 0x0f and fm2 == 0x160 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x156 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4fef; op2val:0xbd60; +op3val:0x4d56; valaddr_reg:x4; val_offset:4059*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4059*FLEN/8, x5, x2, x3) + +inst_1379: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3ef and fs2 == 1 and fe2 == 0x0f and fm2 == 0x160 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x156 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4fef; op2val:0xbd60; +op3val:0x4d56; valaddr_reg:x4; val_offset:4062*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4062*FLEN/8, x5, x2, x3) + +inst_1380: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x0f7 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x11e and fs3 == 0 and fe3 == 0x12 and fm3 == 0x293 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x50f7; op2val:0xbd1e; +op3val:0x4a93; valaddr_reg:x4; val_offset:4065*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4065*FLEN/8, x5, x2, x3) + +inst_1381: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x0f7 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x11e and fs3 == 0 and fe3 == 0x12 and fm3 == 0x293 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x50f7; op2val:0xbd1e; +op3val:0x4a93; valaddr_reg:x4; val_offset:4068*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4068*FLEN/8, x5, x2, x3) + +inst_1382: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x0f7 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x11e and fs3 == 0 and fe3 == 0x12 and fm3 == 0x293 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x50f7; op2val:0xbd1e; +op3val:0x4a93; valaddr_reg:x4; val_offset:4071*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 4071*FLEN/8, x5, x2, x3) + +inst_1383: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x0f7 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x11e and fs3 == 0 and fe3 == 0x12 and fm3 == 0x293 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x50f7; op2val:0xbd1e; +op3val:0x4a93; valaddr_reg:x4; val_offset:4074*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4074*FLEN/8, x5, x2, x3) + +inst_1384: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x0f7 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x11e and fs3 == 0 and fe3 == 0x12 and fm3 == 0x293 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x50f7; op2val:0xbd1e; +op3val:0x4a93; valaddr_reg:x4; val_offset:4077*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4077*FLEN/8, x5, x2, x3) + +inst_1385: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x216 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x097 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4a16; op2val:0xc497; +op3val:0x480f; valaddr_reg:x4; val_offset:4080*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4080*FLEN/8, x5, x2, x3) + +inst_1386: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x216 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x097 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x00f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4a16; op2val:0xc497; +op3val:0x480f; valaddr_reg:x4; val_offset:4083*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4083*FLEN/8, x5, x2, x3) + +inst_1387: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x216 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x097 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x00f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4a16; op2val:0xc497; +op3val:0x480f; valaddr_reg:x4; val_offset:4086*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 4086*FLEN/8, x5, x2, x3) + +inst_1388: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x216 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x097 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x00f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4a16; op2val:0xc497; +op3val:0x480f; valaddr_reg:x4; val_offset:4089*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4089*FLEN/8, x5, x2, x3) + +inst_1389: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x216 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x097 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x00f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4a16; op2val:0xc497; +op3val:0x480f; valaddr_reg:x4; val_offset:4092*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4092*FLEN/8, x5, x2, x3) + +inst_1390: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x165 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x106 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x0e3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5165; op2val:0xbd06; +op3val:0x48e3; valaddr_reg:x4; val_offset:4095*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4095*FLEN/8, x5, x2, x3) + +inst_1391: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x165 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x106 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x0e3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5165; op2val:0xbd06; +op3val:0x48e3; valaddr_reg:x4; val_offset:4098*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4098*FLEN/8, x5, x2, x3) + +inst_1392: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x165 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x106 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x0e3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5165; op2val:0xbd06; +op3val:0x48e3; valaddr_reg:x4; val_offset:4101*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 4101*FLEN/8, x5, x2, x3) + +inst_1393: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x165 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x106 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x0e3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5165; op2val:0xbd06; +op3val:0x48e3; valaddr_reg:x4; val_offset:4104*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4104*FLEN/8, x5, x2, x3) + +inst_1394: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x165 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x106 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x0e3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5165; op2val:0xbd06; +op3val:0x48e3; valaddr_reg:x4; val_offset:4107*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4107*FLEN/8, x5, x2, x3) + +inst_1395: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x385 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x16e and fs3 == 0 and fe3 == 0x13 and fm3 == 0x1c9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4b85; op2val:0xc16e; +op3val:0x4dc9; valaddr_reg:x4; val_offset:4110*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4110*FLEN/8, x5, x2, x3) + +inst_1396: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x385 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x16e and fs3 == 0 and fe3 == 0x13 and fm3 == 0x1c9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4b85; op2val:0xc16e; +op3val:0x4dc9; valaddr_reg:x4; val_offset:4113*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4113*FLEN/8, x5, x2, x3) + +inst_1397: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x385 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x16e and fs3 == 0 and fe3 == 0x13 and fm3 == 0x1c9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4b85; op2val:0xc16e; +op3val:0x4dc9; valaddr_reg:x4; val_offset:4116*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 4116*FLEN/8, x5, x2, x3) + +inst_1398: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x385 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x16e and fs3 == 0 and fe3 == 0x13 and fm3 == 0x1c9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4b85; op2val:0xc16e; +op3val:0x4dc9; valaddr_reg:x4; val_offset:4119*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4119*FLEN/8, x5, x2, x3) + +inst_1399: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x385 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x16e and fs3 == 0 and fe3 == 0x13 and fm3 == 0x1c9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4b85; op2val:0xc16e; +op3val:0x4dc9; valaddr_reg:x4; val_offset:4122*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4122*FLEN/8, x5, x2, x3) + +inst_1400: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x090 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0dc and fs3 == 0 and fe3 == 0x14 and fm3 == 0x139 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5090; op2val:0xb8dc; +op3val:0x5139; valaddr_reg:x4; val_offset:4125*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4125*FLEN/8, x5, x2, x3) + +inst_1401: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x090 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0dc and fs3 == 0 and fe3 == 0x14 and fm3 == 0x139 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5090; op2val:0xb8dc; +op3val:0x5139; valaddr_reg:x4; val_offset:4128*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4128*FLEN/8, x5, x2, x3) + +inst_1402: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x090 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0dc and fs3 == 0 and fe3 == 0x14 and fm3 == 0x139 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5090; op2val:0xb8dc; +op3val:0x5139; valaddr_reg:x4; val_offset:4131*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 4131*FLEN/8, x5, x2, x3) + +inst_1403: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x090 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0dc and fs3 == 0 and fe3 == 0x14 and fm3 == 0x139 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5090; op2val:0xb8dc; +op3val:0x5139; valaddr_reg:x4; val_offset:4134*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4134*FLEN/8, x5, x2, x3) + +inst_1404: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x090 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0dc and fs3 == 0 and fe3 == 0x14 and fm3 == 0x139 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5090; op2val:0xb8dc; +op3val:0x5139; valaddr_reg:x4; val_offset:4137*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4137*FLEN/8, x5, x2, x3) + +inst_1405: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x0ca and fs2 == 1 and fe2 == 0x0e and fm2 == 0x150 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0d1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x50ca; op2val:0xb950; +op3val:0x50d1; valaddr_reg:x4; val_offset:4140*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4140*FLEN/8, x5, x2, x3) + +inst_1406: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x0ca and fs2 == 1 and fe2 == 0x0e and fm2 == 0x150 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0d1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x50ca; op2val:0xb950; +op3val:0x50d1; valaddr_reg:x4; val_offset:4143*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4143*FLEN/8, x5, x2, x3) + +inst_1407: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x0ca and fs2 == 1 and fe2 == 0x0e and fm2 == 0x150 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0d1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x50ca; op2val:0xb950; +op3val:0x50d1; valaddr_reg:x4; val_offset:4146*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 4146*FLEN/8, x5, x2, x3) + +inst_1408: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x0ca and fs2 == 1 and fe2 == 0x0e and fm2 == 0x150 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0d1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x50ca; op2val:0xb950; +op3val:0x50d1; valaddr_reg:x4; val_offset:4149*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4149*FLEN/8, x5, x2, x3) + +inst_1409: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x0ca and fs2 == 1 and fe2 == 0x0e and fm2 == 0x150 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0d1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x50ca; op2val:0xb950; +op3val:0x50d1; valaddr_reg:x4; val_offset:4152*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4152*FLEN/8, x5, x2, x3) + +inst_1410: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x291 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2b3 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x350 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4a91; op2val:0xb6b3; +op3val:0x5350; valaddr_reg:x4; val_offset:4155*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4155*FLEN/8, x5, x2, x3) + +inst_1411: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x291 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2b3 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x350 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4a91; op2val:0xb6b3; +op3val:0x5350; valaddr_reg:x4; val_offset:4158*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4158*FLEN/8, x5, x2, x3) + +inst_1412: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x291 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2b3 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x350 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4a91; op2val:0xb6b3; +op3val:0x5350; valaddr_reg:x4; val_offset:4161*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 4161*FLEN/8, x5, x2, x3) + +inst_1413: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x291 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2b3 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x350 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4a91; op2val:0xb6b3; +op3val:0x5350; valaddr_reg:x4; val_offset:4164*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4164*FLEN/8, x5, x2, x3) + +inst_1414: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x291 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2b3 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x350 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4a91; op2val:0xb6b3; +op3val:0x5350; valaddr_reg:x4; val_offset:4167*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4167*FLEN/8, x5, x2, x3) + +inst_1415: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1ee and fs2 == 1 and fe2 == 0x0e and fm2 == 0x24d and fs3 == 0 and fe3 == 0x13 and fm3 == 0x2a8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x51ee; op2val:0xba4d; +op3val:0x4ea8; valaddr_reg:x4; val_offset:4170*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4170*FLEN/8, x5, x2, x3) + +inst_1416: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1ee and fs2 == 1 and fe2 == 0x0e and fm2 == 0x24d and fs3 == 0 and fe3 == 0x13 and fm3 == 0x2a8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x51ee; op2val:0xba4d; +op3val:0x4ea8; valaddr_reg:x4; val_offset:4173*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4173*FLEN/8, x5, x2, x3) + +inst_1417: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1ee and fs2 == 1 and fe2 == 0x0e and fm2 == 0x24d and fs3 == 0 and fe3 == 0x13 and fm3 == 0x2a8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x51ee; op2val:0xba4d; +op3val:0x4ea8; valaddr_reg:x4; val_offset:4176*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 4176*FLEN/8, x5, x2, x3) + +inst_1418: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1ee and fs2 == 1 and fe2 == 0x0e and fm2 == 0x24d and fs3 == 0 and fe3 == 0x13 and fm3 == 0x2a8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x51ee; op2val:0xba4d; +op3val:0x4ea8; valaddr_reg:x4; val_offset:4179*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4179*FLEN/8, x5, x2, x3) + +inst_1419: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1ee and fs2 == 1 and fe2 == 0x0e and fm2 == 0x24d and fs3 == 0 and fe3 == 0x13 and fm3 == 0x2a8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x51ee; op2val:0xba4d; +op3val:0x4ea8; valaddr_reg:x4; val_offset:4182*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4182*FLEN/8, x5, x2, x3) + +inst_1420: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x27f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x01a and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0ab and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4e7f; op2val:0xbc1a; +op3val:0x50ab; valaddr_reg:x4; val_offset:4185*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4185*FLEN/8, x5, x2, x3) + +inst_1421: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x27f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x01a and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0ab and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4e7f; op2val:0xbc1a; +op3val:0x50ab; valaddr_reg:x4; val_offset:4188*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4188*FLEN/8, x5, x2, x3) + +inst_1422: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x27f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x01a and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0ab and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4e7f; op2val:0xbc1a; +op3val:0x50ab; valaddr_reg:x4; val_offset:4191*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 4191*FLEN/8, x5, x2, x3) + +inst_1423: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x27f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x01a and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0ab and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4e7f; op2val:0xbc1a; +op3val:0x50ab; valaddr_reg:x4; val_offset:4194*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4194*FLEN/8, x5, x2, x3) + +inst_1424: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x27f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x01a and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0ab and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4e7f; op2val:0xbc1a; +op3val:0x50ab; valaddr_reg:x4; val_offset:4197*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4197*FLEN/8, x5, x2, x3) + +inst_1425: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x043 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x141 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x132 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4843; op2val:0xc141; +op3val:0x5132; valaddr_reg:x4; val_offset:4200*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4200*FLEN/8, x5, x2, x3) + +inst_1426: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x043 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x141 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x132 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4843; op2val:0xc141; +op3val:0x5132; valaddr_reg:x4; val_offset:4203*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4203*FLEN/8, x5, x2, x3) + +inst_1427: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x043 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x141 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x132 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4843; op2val:0xc141; +op3val:0x5132; valaddr_reg:x4; val_offset:4206*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 4206*FLEN/8, x5, x2, x3) + +inst_1428: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x043 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x141 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x132 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4843; op2val:0xc141; +op3val:0x5132; valaddr_reg:x4; val_offset:4209*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4209*FLEN/8, x5, x2, x3) + +inst_1429: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x043 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x141 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x132 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4843; op2val:0xc141; +op3val:0x5132; valaddr_reg:x4; val_offset:4212*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4212*FLEN/8, x5, x2, x3) + +inst_1430: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x33c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x189 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x1fb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x533c; op2val:0xb989; +op3val:0x4dfb; valaddr_reg:x4; val_offset:4215*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4215*FLEN/8, x5, x2, x3) + +inst_1431: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x33c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x189 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x1fb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x533c; op2val:0xb989; +op3val:0x4dfb; valaddr_reg:x4; val_offset:4218*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4218*FLEN/8, x5, x2, x3) + +inst_1432: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x33c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x189 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x1fb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x533c; op2val:0xb989; +op3val:0x4dfb; valaddr_reg:x4; val_offset:4221*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 4221*FLEN/8, x5, x2, x3) + +inst_1433: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x33c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x189 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x1fb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x533c; op2val:0xb989; +op3val:0x4dfb; valaddr_reg:x4; val_offset:4224*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4224*FLEN/8, x5, x2, x3) + +inst_1434: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x33c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x189 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x1fb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x533c; op2val:0xb989; +op3val:0x4dfb; valaddr_reg:x4; val_offset:4227*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4227*FLEN/8, x5, x2, x3) + +inst_1435: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x00e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1cd and fs3 == 0 and fe3 == 0x13 and fm3 == 0x03c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x500e; op2val:0xbdcd; +op3val:0x4c3c; valaddr_reg:x4; val_offset:4230*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4230*FLEN/8, x5, x2, x3) + +inst_1436: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x00e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1cd and fs3 == 0 and fe3 == 0x13 and fm3 == 0x03c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x500e; op2val:0xbdcd; +op3val:0x4c3c; valaddr_reg:x4; val_offset:4233*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4233*FLEN/8, x5, x2, x3) + +inst_1437: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x00e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1cd and fs3 == 0 and fe3 == 0x13 and fm3 == 0x03c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x500e; op2val:0xbdcd; +op3val:0x4c3c; valaddr_reg:x4; val_offset:4236*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 4236*FLEN/8, x5, x2, x3) +RVTEST_SIGBASE(x2,signature_x2_11) + +inst_1438: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x00e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1cd and fs3 == 0 and fe3 == 0x13 and fm3 == 0x03c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x500e; op2val:0xbdcd; +op3val:0x4c3c; valaddr_reg:x4; val_offset:4239*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4239*FLEN/8, x5, x2, x3) + +inst_1439: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x00e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1cd and fs3 == 0 and fe3 == 0x13 and fm3 == 0x03c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x500e; op2val:0xbdcd; +op3val:0x4c3c; valaddr_reg:x4; val_offset:4242*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4242*FLEN/8, x5, x2, x3) + +inst_1440: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x349 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x163 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x22f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5349; op2val:0xb963; +op3val:0x4e2f; valaddr_reg:x4; val_offset:4245*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4245*FLEN/8, x5, x2, x3) + +inst_1441: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x349 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x163 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x22f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5349; op2val:0xb963; +op3val:0x4e2f; valaddr_reg:x4; val_offset:4248*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4248*FLEN/8, x5, x2, x3) + +inst_1442: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x349 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x163 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x22f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5349; op2val:0xb963; +op3val:0x4e2f; valaddr_reg:x4; val_offset:4251*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 4251*FLEN/8, x5, x2, x3) + +inst_1443: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x349 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x163 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x22f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5349; op2val:0xb963; +op3val:0x4e2f; valaddr_reg:x4; val_offset:4254*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4254*FLEN/8, x5, x2, x3) + +inst_1444: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x349 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x163 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x22f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5349; op2val:0xb963; +op3val:0x4e2f; valaddr_reg:x4; val_offset:4257*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4257*FLEN/8, x5, x2, x3) + +inst_1445: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x1ee and fs2 == 1 and fe2 == 0x0e and fm2 == 0x21a and fs3 == 0 and fe3 == 0x14 and fm3 == 0x1bd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4dee; op2val:0xba1a; +op3val:0x51bd; valaddr_reg:x4; val_offset:4260*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4260*FLEN/8, x5, x2, x3) + +inst_1446: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x1ee and fs2 == 1 and fe2 == 0x0e and fm2 == 0x21a and fs3 == 0 and fe3 == 0x14 and fm3 == 0x1bd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4dee; op2val:0xba1a; +op3val:0x51bd; valaddr_reg:x4; val_offset:4263*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4263*FLEN/8, x5, x2, x3) + +inst_1447: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x1ee and fs2 == 1 and fe2 == 0x0e and fm2 == 0x21a and fs3 == 0 and fe3 == 0x14 and fm3 == 0x1bd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4dee; op2val:0xba1a; +op3val:0x51bd; valaddr_reg:x4; val_offset:4266*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 4266*FLEN/8, x5, x2, x3) + +inst_1448: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x1ee and fs2 == 1 and fe2 == 0x0e and fm2 == 0x21a and fs3 == 0 and fe3 == 0x14 and fm3 == 0x1bd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4dee; op2val:0xba1a; +op3val:0x51bd; valaddr_reg:x4; val_offset:4269*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4269*FLEN/8, x5, x2, x3) + +inst_1449: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x1ee and fs2 == 1 and fe2 == 0x0e and fm2 == 0x21a and fs3 == 0 and fe3 == 0x14 and fm3 == 0x1bd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4dee; op2val:0xba1a; +op3val:0x51bd; valaddr_reg:x4; val_offset:4272*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4272*FLEN/8, x5, x2, x3) + +inst_1450: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x21e and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3d4 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x340 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4e1e; op2val:0xb3d4; +op3val:0x5340; valaddr_reg:x4; val_offset:4275*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4275*FLEN/8, x5, x2, x3) + +inst_1451: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x21e and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3d4 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x340 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4e1e; op2val:0xb3d4; +op3val:0x5340; valaddr_reg:x4; val_offset:4278*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4278*FLEN/8, x5, x2, x3) + +inst_1452: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x21e and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3d4 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x340 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4e1e; op2val:0xb3d4; +op3val:0x5340; valaddr_reg:x4; val_offset:4281*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 4281*FLEN/8, x5, x2, x3) + +inst_1453: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x21e and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3d4 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x340 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4e1e; op2val:0xb3d4; +op3val:0x5340; valaddr_reg:x4; val_offset:4284*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4284*FLEN/8, x5, x2, x3) + +inst_1454: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x21e and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3d4 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x340 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4e1e; op2val:0xb3d4; +op3val:0x5340; valaddr_reg:x4; val_offset:4287*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4287*FLEN/8, x5, x2, x3) + +inst_1455: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x2ba and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b2 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0c3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4eba; op2val:0xbbb2; +op3val:0x50c3; valaddr_reg:x4; val_offset:4290*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4290*FLEN/8, x5, x2, x3) + +inst_1456: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x2ba and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b2 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0c3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4eba; op2val:0xbbb2; +op3val:0x50c3; valaddr_reg:x4; val_offset:4293*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4293*FLEN/8, x5, x2, x3) + +inst_1457: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x2ba and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b2 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0c3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4eba; op2val:0xbbb2; +op3val:0x50c3; valaddr_reg:x4; val_offset:4296*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 4296*FLEN/8, x5, x2, x3) + +inst_1458: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x2ba and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b2 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0c3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4eba; op2val:0xbbb2; +op3val:0x50c3; valaddr_reg:x4; val_offset:4299*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4299*FLEN/8, x5, x2, x3) + +inst_1459: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x2ba and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b2 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0c3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4eba; op2val:0xbbb2; +op3val:0x50c3; valaddr_reg:x4; val_offset:4302*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4302*FLEN/8, x5, x2, x3) + +inst_1460: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x10d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x11e and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0c4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4d0d; op2val:0xbd1e; +op3val:0x50c4; valaddr_reg:x4; val_offset:4305*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4305*FLEN/8, x5, x2, x3) + +inst_1461: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x10d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x11e and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0c4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4d0d; op2val:0xbd1e; +op3val:0x50c4; valaddr_reg:x4; val_offset:4308*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4308*FLEN/8, x5, x2, x3) + +inst_1462: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x10d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x11e and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0c4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4d0d; op2val:0xbd1e; +op3val:0x50c4; valaddr_reg:x4; val_offset:4311*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 4311*FLEN/8, x5, x2, x3) + +inst_1463: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x10d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x11e and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0c4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4d0d; op2val:0xbd1e; +op3val:0x50c4; valaddr_reg:x4; val_offset:4314*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4314*FLEN/8, x5, x2, x3) + +inst_1464: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x10d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x11e and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0c4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4d0d; op2val:0xbd1e; +op3val:0x50c4; valaddr_reg:x4; val_offset:4317*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4317*FLEN/8, x5, x2, x3) + +inst_1465: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3b0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x357 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x38e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4fb0; op2val:0xbf57; +op3val:0x478e; valaddr_reg:x4; val_offset:4320*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4320*FLEN/8, x5, x2, x3) + +inst_1466: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3b0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x357 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x38e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4fb0; op2val:0xbf57; +op3val:0x478e; valaddr_reg:x4; val_offset:4323*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4323*FLEN/8, x5, x2, x3) + +inst_1467: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3b0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x357 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x38e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4fb0; op2val:0xbf57; +op3val:0x478e; valaddr_reg:x4; val_offset:4326*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 4326*FLEN/8, x5, x2, x3) + +inst_1468: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3b0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x357 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x38e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4fb0; op2val:0xbf57; +op3val:0x478e; valaddr_reg:x4; val_offset:4329*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4329*FLEN/8, x5, x2, x3) + +inst_1469: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3b0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x357 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x38e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4fb0; op2val:0xbf57; +op3val:0x478e; valaddr_reg:x4; val_offset:4332*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4332*FLEN/8, x5, x2, x3) + +inst_1470: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x071 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1db and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2c1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3071; op2val:0x45db; +op3val:0x3ac1; valaddr_reg:x4; val_offset:4335*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4335*FLEN/8, x5, x2, x3) + +inst_1471: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x071 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1db and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2c1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3071; op2val:0x45db; +op3val:0x3ac1; valaddr_reg:x4; val_offset:4338*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4338*FLEN/8, x5, x2, x3) + +inst_1472: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x071 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1db and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2c1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3071; op2val:0x45db; +op3val:0x3ac1; valaddr_reg:x4; val_offset:4341*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 4341*FLEN/8, x5, x2, x3) + +inst_1473: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x071 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1db and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2c1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3071; op2val:0x45db; +op3val:0x3ac1; valaddr_reg:x4; val_offset:4344*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4344*FLEN/8, x5, x2, x3) + +inst_1474: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x071 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1db and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2c1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3071; op2val:0x45db; +op3val:0x3ac1; valaddr_reg:x4; val_offset:4347*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4347*FLEN/8, x5, x2, x3) + +inst_1475: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x313 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1a8 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x181 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3713; op2val:0x39a8; +op3val:0x3581; valaddr_reg:x4; val_offset:4350*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4350*FLEN/8, x5, x2, x3) + +inst_1476: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x313 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1a8 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x181 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3713; op2val:0x39a8; +op3val:0x3581; valaddr_reg:x4; val_offset:4353*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4353*FLEN/8, x5, x2, x3) + +inst_1477: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x313 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1a8 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x181 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3713; op2val:0x39a8; +op3val:0x3581; valaddr_reg:x4; val_offset:4356*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 4356*FLEN/8, x5, x2, x3) + +inst_1478: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x313 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1a8 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x181 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3713; op2val:0x39a8; +op3val:0x3581; valaddr_reg:x4; val_offset:4359*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4359*FLEN/8, x5, x2, x3) + +inst_1479: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x313 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1a8 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x181 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3713; op2val:0x39a8; +op3val:0x3581; valaddr_reg:x4; val_offset:4362*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4362*FLEN/8, x5, x2, x3) + +inst_1480: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x05e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x175 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x385e; op2val:0x3cc5; +op3val:0x3975; valaddr_reg:x4; val_offset:4365*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4365*FLEN/8, x5, x2, x3) + +inst_1481: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x05e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x175 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x385e; op2val:0x3cc5; +op3val:0x3975; valaddr_reg:x4; val_offset:4368*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4368*FLEN/8, x5, x2, x3) + +inst_1482: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x05e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x175 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x385e; op2val:0x3cc5; +op3val:0x3975; valaddr_reg:x4; val_offset:4371*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 4371*FLEN/8, x5, x2, x3) + +inst_1483: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x05e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x175 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x385e; op2val:0x3cc5; +op3val:0x3975; valaddr_reg:x4; val_offset:4374*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4374*FLEN/8, x5, x2, x3) + +inst_1484: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x05e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x175 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x385e; op2val:0x3cc5; +op3val:0x3975; valaddr_reg:x4; val_offset:4377*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4377*FLEN/8, x5, x2, x3) + +inst_1485: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x07b and fs2 == 0 and fe2 == 0x04 and fm2 == 0x276 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x00e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x387b; op2val:0x1276; +op3val:0x280e; valaddr_reg:x4; val_offset:4380*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4380*FLEN/8, x5, x2, x3) + +inst_1486: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x07b and fs2 == 0 and fe2 == 0x04 and fm2 == 0x276 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x00e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x387b; op2val:0x1276; +op3val:0x280e; valaddr_reg:x4; val_offset:4383*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4383*FLEN/8, x5, x2, x3) + +inst_1487: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x07b and fs2 == 0 and fe2 == 0x04 and fm2 == 0x276 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x00e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x387b; op2val:0x1276; +op3val:0x280e; valaddr_reg:x4; val_offset:4386*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 4386*FLEN/8, x5, x2, x3) + +inst_1488: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x07b and fs2 == 0 and fe2 == 0x04 and fm2 == 0x276 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x00e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x387b; op2val:0x1276; +op3val:0x280e; valaddr_reg:x4; val_offset:4389*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4389*FLEN/8, x5, x2, x3) + +inst_1489: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x07b and fs2 == 0 and fe2 == 0x04 and fm2 == 0x276 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x00e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x387b; op2val:0x1276; +op3val:0x280e; valaddr_reg:x4; val_offset:4392*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4392*FLEN/8, x5, x2, x3) + +inst_1490: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e8 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x335 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x090 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3be8; op2val:0x2f35; +op3val:0x3090; valaddr_reg:x4; val_offset:4395*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4395*FLEN/8, x5, x2, x3) + +inst_1491: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e8 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x335 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x090 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3be8; op2val:0x2f35; +op3val:0x3090; valaddr_reg:x4; val_offset:4398*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4398*FLEN/8, x5, x2, x3) + +inst_1492: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e8 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x335 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x090 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3be8; op2val:0x2f35; +op3val:0x3090; valaddr_reg:x4; val_offset:4401*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 4401*FLEN/8, x5, x2, x3) + +inst_1493: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e8 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x335 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x090 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3be8; op2val:0x2f35; +op3val:0x3090; valaddr_reg:x4; val_offset:4404*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4404*FLEN/8, x5, x2, x3) + +inst_1494: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e8 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x335 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x090 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3be8; op2val:0x2f35; +op3val:0x3090; valaddr_reg:x4; val_offset:4407*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4407*FLEN/8, x5, x2, x3) + +inst_1495: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x296 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0e2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x045 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3696; op2val:0x3ce2; +op3val:0x3845; valaddr_reg:x4; val_offset:4410*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4410*FLEN/8, x5, x2, x3) + +inst_1496: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x296 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0e2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x045 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3696; op2val:0x3ce2; +op3val:0x3845; valaddr_reg:x4; val_offset:4413*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4413*FLEN/8, x5, x2, x3) + +inst_1497: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x296 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0e2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x045 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3696; op2val:0x3ce2; +op3val:0x3845; valaddr_reg:x4; val_offset:4416*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 4416*FLEN/8, x5, x2, x3) + +inst_1498: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x296 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0e2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x045 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3696; op2val:0x3ce2; +op3val:0x3845; valaddr_reg:x4; val_offset:4419*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4419*FLEN/8, x5, x2, x3) + +inst_1499: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x296 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0e2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x045 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3696; op2val:0x3ce2; +op3val:0x3845; valaddr_reg:x4; val_offset:4422*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4422*FLEN/8, x5, x2, x3) + +inst_1500: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x21d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x34e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x215 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x361d; op2val:0x3b4e; +op3val:0x3615; valaddr_reg:x4; val_offset:4425*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4425*FLEN/8, x5, x2, x3) + +inst_1501: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x21d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x34e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x215 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x361d; op2val:0x3b4e; +op3val:0x3615; valaddr_reg:x4; val_offset:4428*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4428*FLEN/8, x5, x2, x3) + +inst_1502: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x21d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x34e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x215 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x361d; op2val:0x3b4e; +op3val:0x3615; valaddr_reg:x4; val_offset:4431*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 4431*FLEN/8, x5, x2, x3) + +inst_1503: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x21d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x34e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x215 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x361d; op2val:0x3b4e; +op3val:0x3615; valaddr_reg:x4; val_offset:4434*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4434*FLEN/8, x5, x2, x3) + +inst_1504: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x21d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x34e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x215 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x361d; op2val:0x3b4e; +op3val:0x3615; valaddr_reg:x4; val_offset:4437*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4437*FLEN/8, x5, x2, x3) + +inst_1505: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x242 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x36f and fs3 == 0 and fe3 == 0x0a and fm3 == 0x2e8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3242; op2val:0x2f6f; +op3val:0x2ae8; valaddr_reg:x4; val_offset:4440*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4440*FLEN/8, x5, x2, x3) + +inst_1506: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x242 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x36f and fs3 == 0 and fe3 == 0x0a and fm3 == 0x2e8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3242; op2val:0x2f6f; +op3val:0x2ae8; valaddr_reg:x4; val_offset:4443*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4443*FLEN/8, x5, x2, x3) + +inst_1507: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x242 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x36f and fs3 == 0 and fe3 == 0x0a and fm3 == 0x2e8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3242; op2val:0x2f6f; +op3val:0x2ae8; valaddr_reg:x4; val_offset:4446*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 4446*FLEN/8, x5, x2, x3) + +inst_1508: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x242 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x36f and fs3 == 0 and fe3 == 0x0a and fm3 == 0x2e8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3242; op2val:0x2f6f; +op3val:0x2ae8; valaddr_reg:x4; val_offset:4449*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4449*FLEN/8, x5, x2, x3) + +inst_1509: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x242 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x36f and fs3 == 0 and fe3 == 0x0a and fm3 == 0x2e8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3242; op2val:0x2f6f; +op3val:0x2ae8; valaddr_reg:x4; val_offset:4452*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4452*FLEN/8, x5, x2, x3) + +inst_1510: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x104 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x147 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3801; op2val:0x3d04; +op3val:0x3947; valaddr_reg:x4; val_offset:4455*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4455*FLEN/8, x5, x2, x3) + +inst_1511: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x104 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x147 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3801; op2val:0x3d04; +op3val:0x3947; valaddr_reg:x4; val_offset:4458*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4458*FLEN/8, x5, x2, x3) + +inst_1512: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x104 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x147 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3801; op2val:0x3d04; +op3val:0x3947; valaddr_reg:x4; val_offset:4461*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 4461*FLEN/8, x5, x2, x3) + +inst_1513: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x104 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x147 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3801; op2val:0x3d04; +op3val:0x3947; valaddr_reg:x4; val_offset:4464*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4464*FLEN/8, x5, x2, x3) + +inst_1514: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x104 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x147 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3801; op2val:0x3d04; +op3val:0x3947; valaddr_reg:x4; val_offset:4467*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4467*FLEN/8, x5, x2, x3) + +inst_1515: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x130 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x045 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x38a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3930; op2val:0x3045; +op3val:0x2f8a; valaddr_reg:x4; val_offset:4470*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4470*FLEN/8, x5, x2, x3) + +inst_1516: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x130 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x045 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x38a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3930; op2val:0x3045; +op3val:0x2f8a; valaddr_reg:x4; val_offset:4473*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4473*FLEN/8, x5, x2, x3) + +inst_1517: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x130 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x045 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x38a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3930; op2val:0x3045; +op3val:0x2f8a; valaddr_reg:x4; val_offset:4476*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 4476*FLEN/8, x5, x2, x3) + +inst_1518: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x130 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x045 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x38a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3930; op2val:0x3045; +op3val:0x2f8a; valaddr_reg:x4; val_offset:4479*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4479*FLEN/8, x5, x2, x3) + +inst_1519: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x130 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x045 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x38a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3930; op2val:0x3045; +op3val:0x2f8a; valaddr_reg:x4; val_offset:4482*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4482*FLEN/8, x5, x2, x3) + +inst_1520: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x047 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2bb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x373 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3847; op2val:0x3ebb; +op3val:0x3b73; valaddr_reg:x4; val_offset:4485*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4485*FLEN/8, x5, x2, x3) + +inst_1521: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x047 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2bb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x373 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3847; op2val:0x3ebb; +op3val:0x3b73; valaddr_reg:x4; val_offset:4488*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4488*FLEN/8, x5, x2, x3) + +inst_1522: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x047 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2bb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x373 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3847; op2val:0x3ebb; +op3val:0x3b73; valaddr_reg:x4; val_offset:4491*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 4491*FLEN/8, x5, x2, x3) + +inst_1523: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x047 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2bb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x373 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3847; op2val:0x3ebb; +op3val:0x3b73; valaddr_reg:x4; val_offset:4494*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4494*FLEN/8, x5, x2, x3) + +inst_1524: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x047 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2bb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x373 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3847; op2val:0x3ebb; +op3val:0x3b73; valaddr_reg:x4; val_offset:4497*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4497*FLEN/8, x5, x2, x3) + +inst_1525: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2e8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3f1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x31b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36e8; op2val:0x3ff1; +op3val:0x3b1b; valaddr_reg:x4; val_offset:4500*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4500*FLEN/8, x5, x2, x3) + +inst_1526: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2e8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3f1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x31b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36e8; op2val:0x3ff1; +op3val:0x3b1b; valaddr_reg:x4; val_offset:4503*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4503*FLEN/8, x5, x2, x3) + +inst_1527: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2e8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3f1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x31b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36e8; op2val:0x3ff1; +op3val:0x3b1b; valaddr_reg:x4; val_offset:4506*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 4506*FLEN/8, x5, x2, x3) + +inst_1528: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2e8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3f1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x31b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36e8; op2val:0x3ff1; +op3val:0x3b1b; valaddr_reg:x4; val_offset:4509*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4509*FLEN/8, x5, x2, x3) + +inst_1529: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2e8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3f1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x31b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36e8; op2val:0x3ff1; +op3val:0x3b1b; valaddr_reg:x4; val_offset:4512*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4512*FLEN/8, x5, x2, x3) + +inst_1530: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x150 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x013 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1e9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3950; op2val:0x3813; +op3val:0x35e9; valaddr_reg:x4; val_offset:4515*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4515*FLEN/8, x5, x2, x3) + +inst_1531: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x150 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x013 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1e9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3950; op2val:0x3813; +op3val:0x35e9; valaddr_reg:x4; val_offset:4518*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4518*FLEN/8, x5, x2, x3) + +inst_1532: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x150 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x013 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1e9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3950; op2val:0x3813; +op3val:0x35e9; valaddr_reg:x4; val_offset:4521*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 4521*FLEN/8, x5, x2, x3) + +inst_1533: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x150 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x013 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1e9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3950; op2val:0x3813; +op3val:0x35e9; valaddr_reg:x4; val_offset:4524*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4524*FLEN/8, x5, x2, x3) + +inst_1534: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x150 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x013 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1e9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3950; op2val:0x3813; +op3val:0x35e9; valaddr_reg:x4; val_offset:4527*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4527*FLEN/8, x5, x2, x3) + +inst_1535: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x281 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x06a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3af and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3681; op2val:0x3c6a; +op3val:0x37af; valaddr_reg:x4; val_offset:4530*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4530*FLEN/8, x5, x2, x3) + +inst_1536: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x281 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x06a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3af and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3681; op2val:0x3c6a; +op3val:0x37af; valaddr_reg:x4; val_offset:4533*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4533*FLEN/8, x5, x2, x3) + +inst_1537: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x281 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x06a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3af and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3681; op2val:0x3c6a; +op3val:0x37af; valaddr_reg:x4; val_offset:4536*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 4536*FLEN/8, x5, x2, x3) + +inst_1538: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x281 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x06a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3af and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3681; op2val:0x3c6a; +op3val:0x37af; valaddr_reg:x4; val_offset:4539*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4539*FLEN/8, x5, x2, x3) + +inst_1539: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x281 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x06a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3af and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3681; op2val:0x3c6a; +op3val:0x37af; valaddr_reg:x4; val_offset:4542*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4542*FLEN/8, x5, x2, x3) + +inst_1540: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3b9 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x291 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3248; op2val:0x3fb9; +op3val:0x3691; valaddr_reg:x4; val_offset:4545*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4545*FLEN/8, x5, x2, x3) + +inst_1541: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3b9 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x291 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3248; op2val:0x3fb9; +op3val:0x3691; valaddr_reg:x4; val_offset:4548*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4548*FLEN/8, x5, x2, x3) + +inst_1542: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3b9 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x291 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3248; op2val:0x3fb9; +op3val:0x3691; valaddr_reg:x4; val_offset:4551*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 4551*FLEN/8, x5, x2, x3) + +inst_1543: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3b9 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x291 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3248; op2val:0x3fb9; +op3val:0x3691; valaddr_reg:x4; val_offset:4554*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4554*FLEN/8, x5, x2, x3) + +inst_1544: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3b9 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x291 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3248; op2val:0x3fb9; +op3val:0x3691; valaddr_reg:x4; val_offset:4557*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4557*FLEN/8, x5, x2, x3) + +inst_1545: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x3b1 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x213 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2d8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2bb1; op2val:0x4213; +op3val:0x32d8; valaddr_reg:x4; val_offset:4560*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4560*FLEN/8, x5, x2, x3) + +inst_1546: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x3b1 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x213 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2d8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2bb1; op2val:0x4213; +op3val:0x32d8; valaddr_reg:x4; val_offset:4563*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4563*FLEN/8, x5, x2, x3) + +inst_1547: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x3b1 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x213 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2d8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2bb1; op2val:0x4213; +op3val:0x32d8; valaddr_reg:x4; val_offset:4566*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 4566*FLEN/8, x5, x2, x3) + +inst_1548: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x3b1 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x213 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2d8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2bb1; op2val:0x4213; +op3val:0x32d8; valaddr_reg:x4; val_offset:4569*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4569*FLEN/8, x5, x2, x3) + +inst_1549: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x3b1 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x213 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2d8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2bb1; op2val:0x4213; +op3val:0x32d8; valaddr_reg:x4; val_offset:4572*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4572*FLEN/8, x5, x2, x3) + +inst_1550: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1f3 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x08d and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3c5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39f3; op2val:0x348d; +op3val:0x33c5; valaddr_reg:x4; val_offset:4575*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4575*FLEN/8, x5, x2, x3) + +inst_1551: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1f3 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x08d and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3c5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39f3; op2val:0x348d; +op3val:0x33c5; valaddr_reg:x4; val_offset:4578*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4578*FLEN/8, x5, x2, x3) + +inst_1552: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1f3 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x08d and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3c5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39f3; op2val:0x348d; +op3val:0x33c5; valaddr_reg:x4; val_offset:4581*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 4581*FLEN/8, x5, x2, x3) + +inst_1553: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1f3 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x08d and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3c5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39f3; op2val:0x348d; +op3val:0x33c5; valaddr_reg:x4; val_offset:4584*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4584*FLEN/8, x5, x2, x3) + +inst_1554: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1f3 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x08d and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3c5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39f3; op2val:0x348d; +op3val:0x33c5; valaddr_reg:x4; val_offset:4587*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4587*FLEN/8, x5, x2, x3) + +inst_1555: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x133 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x139 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x165 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3933; op2val:0x2d39; +op3val:0x2d65; valaddr_reg:x4; val_offset:4590*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4590*FLEN/8, x5, x2, x3) + +inst_1556: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x133 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x139 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x165 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3933; op2val:0x2d39; +op3val:0x2d65; valaddr_reg:x4; val_offset:4593*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4593*FLEN/8, x5, x2, x3) + +inst_1557: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x133 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x139 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x165 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3933; op2val:0x2d39; +op3val:0x2d65; valaddr_reg:x4; val_offset:4596*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 4596*FLEN/8, x5, x2, x3) + +inst_1558: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x133 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x139 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x165 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3933; op2val:0x2d39; +op3val:0x2d65; valaddr_reg:x4; val_offset:4599*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4599*FLEN/8, x5, x2, x3) + +inst_1559: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x133 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x139 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x165 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3933; op2val:0x2d39; +op3val:0x2d65; valaddr_reg:x4; val_offset:4602*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4602*FLEN/8, x5, x2, x3) + +inst_1560: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x267 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1a2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0c2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3667; op2val:0x3da2; +op3val:0x38c2; valaddr_reg:x4; val_offset:4605*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4605*FLEN/8, x5, x2, x3) + +inst_1561: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x267 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1a2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0c2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3667; op2val:0x3da2; +op3val:0x38c2; valaddr_reg:x4; val_offset:4608*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4608*FLEN/8, x5, x2, x3) + +inst_1562: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x267 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1a2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0c2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3667; op2val:0x3da2; +op3val:0x38c2; valaddr_reg:x4; val_offset:4611*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 4611*FLEN/8, x5, x2, x3) + +inst_1563: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x267 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1a2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0c2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3667; op2val:0x3da2; +op3val:0x38c2; valaddr_reg:x4; val_offset:4614*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4614*FLEN/8, x5, x2, x3) + +inst_1564: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x267 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1a2 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0c2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3667; op2val:0x3da2; +op3val:0x38c2; valaddr_reg:x4; val_offset:4617*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4617*FLEN/8, x5, x2, x3) + +inst_1565: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2a4 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1ad and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1b7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aa4; op2val:0x31ad; +op3val:0x31b7; valaddr_reg:x4; val_offset:4620*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4620*FLEN/8, x5, x2, x3) +RVTEST_SIGBASE(x2,signature_x2_12) + +inst_1566: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2a4 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1ad and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1b7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aa4; op2val:0x31ad; +op3val:0x31b7; valaddr_reg:x4; val_offset:4623*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4623*FLEN/8, x5, x2, x3) + +inst_1567: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2a4 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1ad and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1b7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aa4; op2val:0x31ad; +op3val:0x31b7; valaddr_reg:x4; val_offset:4626*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 4626*FLEN/8, x5, x2, x3) + +inst_1568: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2a4 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1ad and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1b7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aa4; op2val:0x31ad; +op3val:0x31b7; valaddr_reg:x4; val_offset:4629*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4629*FLEN/8, x5, x2, x3) + +inst_1569: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2a4 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1ad and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1b7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aa4; op2val:0x31ad; +op3val:0x31b7; valaddr_reg:x4; val_offset:4632*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4632*FLEN/8, x5, x2, x3) + +inst_1570: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x144 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1cb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3944; op2val:0x3dcb; +op3val:0x3be0; valaddr_reg:x4; val_offset:4635*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4635*FLEN/8, x5, x2, x3) + +inst_1571: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x144 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1cb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3e0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3944; op2val:0x3dcb; +op3val:0x3be0; valaddr_reg:x4; val_offset:4638*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4638*FLEN/8, x5, x2, x3) + +inst_1572: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x144 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1cb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3e0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3944; op2val:0x3dcb; +op3val:0x3be0; valaddr_reg:x4; val_offset:4641*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 4641*FLEN/8, x5, x2, x3) + +inst_1573: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x144 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1cb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3e0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3944; op2val:0x3dcb; +op3val:0x3be0; valaddr_reg:x4; val_offset:4644*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4644*FLEN/8, x5, x2, x3) + +inst_1574: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x144 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1cb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3e0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3944; op2val:0x3dcb; +op3val:0x3be0; valaddr_reg:x4; val_offset:4647*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4647*FLEN/8, x5, x2, x3) + +inst_1575: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x31a and fs2 == 0 and fe2 == 0x11 and fm2 == 0x056 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3f3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x331a; op2val:0x4456; +op3val:0x3bf3; valaddr_reg:x4; val_offset:4650*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4650*FLEN/8, x5, x2, x3) + +inst_1576: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x31a and fs2 == 0 and fe2 == 0x11 and fm2 == 0x056 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3f3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x331a; op2val:0x4456; +op3val:0x3bf3; valaddr_reg:x4; val_offset:4653*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4653*FLEN/8, x5, x2, x3) + +inst_1577: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x31a and fs2 == 0 and fe2 == 0x11 and fm2 == 0x056 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3f3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x331a; op2val:0x4456; +op3val:0x3bf3; valaddr_reg:x4; val_offset:4656*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 4656*FLEN/8, x5, x2, x3) + +inst_1578: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x31a and fs2 == 0 and fe2 == 0x11 and fm2 == 0x056 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3f3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x331a; op2val:0x4456; +op3val:0x3bf3; valaddr_reg:x4; val_offset:4659*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4659*FLEN/8, x5, x2, x3) + +inst_1579: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x31a and fs2 == 0 and fe2 == 0x11 and fm2 == 0x056 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3f3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x331a; op2val:0x4456; +op3val:0x3bf3; valaddr_reg:x4; val_offset:4662*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4662*FLEN/8, x5, x2, x3) + +inst_1580: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3a7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3da and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3c3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ba7; op2val:0x3bda; +op3val:0x3bc3; valaddr_reg:x4; val_offset:4665*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4665*FLEN/8, x5, x2, x3) + +inst_1581: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3a7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3da and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3c3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ba7; op2val:0x3bda; +op3val:0x3bc3; valaddr_reg:x4; val_offset:4668*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4668*FLEN/8, x5, x2, x3) + +inst_1582: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3a7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3da and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3c3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ba7; op2val:0x3bda; +op3val:0x3bc3; valaddr_reg:x4; val_offset:4671*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 4671*FLEN/8, x5, x2, x3) + +inst_1583: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3a7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3da and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3c3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ba7; op2val:0x3bda; +op3val:0x3bc3; valaddr_reg:x4; val_offset:4674*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4674*FLEN/8, x5, x2, x3) + +inst_1584: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3a7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3da and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3c3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ba7; op2val:0x3bda; +op3val:0x3bc3; valaddr_reg:x4; val_offset:4677*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4677*FLEN/8, x5, x2, x3) + +inst_1585: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x202 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x084 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x349 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3602; op2val:0x3c84; +op3val:0x3749; valaddr_reg:x4; val_offset:4680*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4680*FLEN/8, x5, x2, x3) + +inst_1586: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x202 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x084 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x349 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3602; op2val:0x3c84; +op3val:0x3749; valaddr_reg:x4; val_offset:4683*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4683*FLEN/8, x5, x2, x3) + +inst_1587: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x202 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x084 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x349 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3602; op2val:0x3c84; +op3val:0x3749; valaddr_reg:x4; val_offset:4686*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 4686*FLEN/8, x5, x2, x3) + +inst_1588: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x202 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x084 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x349 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3602; op2val:0x3c84; +op3val:0x3749; valaddr_reg:x4; val_offset:4689*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4689*FLEN/8, x5, x2, x3) + +inst_1589: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x202 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x084 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x349 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3602; op2val:0x3c84; +op3val:0x3749; valaddr_reg:x4; val_offset:4692*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4692*FLEN/8, x5, x2, x3) + +inst_1590: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x040 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x394 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x207 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3840; op2val:0x2f94; +op3val:0x2e07; valaddr_reg:x4; val_offset:4695*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4695*FLEN/8, x5, x2, x3) + +inst_1591: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x040 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x394 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x207 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3840; op2val:0x2f94; +op3val:0x2e07; valaddr_reg:x4; val_offset:4698*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4698*FLEN/8, x5, x2, x3) + +inst_1592: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x040 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x394 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x207 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3840; op2val:0x2f94; +op3val:0x2e07; valaddr_reg:x4; val_offset:4701*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 4701*FLEN/8, x5, x2, x3) + +inst_1593: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x040 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x394 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x207 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3840; op2val:0x2f94; +op3val:0x2e07; valaddr_reg:x4; val_offset:4704*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4704*FLEN/8, x5, x2, x3) + +inst_1594: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x040 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x394 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x207 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3840; op2val:0x2f94; +op3val:0x2e07; valaddr_reg:x4; val_offset:4707*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4707*FLEN/8, x5, x2, x3) + +inst_1595: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x05a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1a7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x267 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x385a; op2val:0x3da7; +op3val:0x3a67; valaddr_reg:x4; val_offset:4710*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4710*FLEN/8, x5, x2, x3) + +inst_1596: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x05a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1a7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x267 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x385a; op2val:0x3da7; +op3val:0x3a67; valaddr_reg:x4; val_offset:4713*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4713*FLEN/8, x5, x2, x3) + +inst_1597: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x05a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1a7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x267 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x385a; op2val:0x3da7; +op3val:0x3a67; valaddr_reg:x4; val_offset:4716*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 4716*FLEN/8, x5, x2, x3) + +inst_1598: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x05a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1a7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x267 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x385a; op2val:0x3da7; +op3val:0x3a67; valaddr_reg:x4; val_offset:4719*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4719*FLEN/8, x5, x2, x3) + +inst_1599: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x05a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1a7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x267 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x385a; op2val:0x3da7; +op3val:0x3a67; valaddr_reg:x4; val_offset:4722*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4722*FLEN/8, x5, x2, x3) + +inst_1600: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x070 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x237 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x325 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2870; op2val:0x4e37; +op3val:0x3b25; valaddr_reg:x4; val_offset:4725*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4725*FLEN/8, x5, x2, x3) + +inst_1601: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x070 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x237 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x325 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2870; op2val:0x4e37; +op3val:0x3b25; valaddr_reg:x4; val_offset:4728*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4728*FLEN/8, x5, x2, x3) + +inst_1602: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x070 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x237 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x325 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2870; op2val:0x4e37; +op3val:0x3b25; valaddr_reg:x4; val_offset:4731*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 4731*FLEN/8, x5, x2, x3) + +inst_1603: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x070 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x237 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x325 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2870; op2val:0x4e37; +op3val:0x3b25; valaddr_reg:x4; val_offset:4734*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4734*FLEN/8, x5, x2, x3) + +inst_1604: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x070 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x237 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x325 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2870; op2val:0x4e37; +op3val:0x3b25; valaddr_reg:x4; val_offset:4737*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4737*FLEN/8, x5, x2, x3) + +inst_1605: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x39d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x253 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x246 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b9d; op2val:0x3a53; +op3val:0x3a46; valaddr_reg:x4; val_offset:4740*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4740*FLEN/8, x5, x2, x3) + +inst_1606: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x39d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x253 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x246 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b9d; op2val:0x3a53; +op3val:0x3a46; valaddr_reg:x4; val_offset:4743*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4743*FLEN/8, x5, x2, x3) + +inst_1607: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x39d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x253 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x246 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b9d; op2val:0x3a53; +op3val:0x3a46; valaddr_reg:x4; val_offset:4746*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 4746*FLEN/8, x5, x2, x3) + +inst_1608: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x39d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x253 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x246 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b9d; op2val:0x3a53; +op3val:0x3a46; valaddr_reg:x4; val_offset:4749*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4749*FLEN/8, x5, x2, x3) + +inst_1609: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x39d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x253 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x246 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b9d; op2val:0x3a53; +op3val:0x3a46; valaddr_reg:x4; val_offset:4752*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4752*FLEN/8, x5, x2, x3) + +inst_1610: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2e8 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x139 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0c3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ae8; op2val:0x4939; +op3val:0x38c3; valaddr_reg:x4; val_offset:4755*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4755*FLEN/8, x5, x2, x3) + +inst_1611: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2e8 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x139 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0c3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ae8; op2val:0x4939; +op3val:0x38c3; valaddr_reg:x4; val_offset:4758*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4758*FLEN/8, x5, x2, x3) + +inst_1612: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2e8 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x139 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0c3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ae8; op2val:0x4939; +op3val:0x38c3; valaddr_reg:x4; val_offset:4761*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 4761*FLEN/8, x5, x2, x3) + +inst_1613: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2e8 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x139 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0c3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ae8; op2val:0x4939; +op3val:0x38c3; valaddr_reg:x4; val_offset:4764*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4764*FLEN/8, x5, x2, x3) + +inst_1614: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2e8 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x139 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0c3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ae8; op2val:0x4939; +op3val:0x38c3; valaddr_reg:x4; val_offset:4767*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4767*FLEN/8, x5, x2, x3) + +inst_1615: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x13b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x377 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x122 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x393b; op2val:0x3b77; +op3val:0x3922; valaddr_reg:x4; val_offset:4770*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4770*FLEN/8, x5, x2, x3) + +inst_1616: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x13b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x377 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x122 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x393b; op2val:0x3b77; +op3val:0x3922; valaddr_reg:x4; val_offset:4773*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4773*FLEN/8, x5, x2, x3) + +inst_1617: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x13b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x377 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x122 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x393b; op2val:0x3b77; +op3val:0x3922; valaddr_reg:x4; val_offset:4776*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 4776*FLEN/8, x5, x2, x3) + +inst_1618: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x13b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x377 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x122 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x393b; op2val:0x3b77; +op3val:0x3922; valaddr_reg:x4; val_offset:4779*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4779*FLEN/8, x5, x2, x3) + +inst_1619: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x13b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x377 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x122 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x393b; op2val:0x3b77; +op3val:0x3922; valaddr_reg:x4; val_offset:4782*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4782*FLEN/8, x5, x2, x3) + +inst_1620: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x121 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1e8 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x049 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3921; op2val:0x35e8; +op3val:0x3449; valaddr_reg:x4; val_offset:4785*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4785*FLEN/8, x5, x2, x3) + +inst_1621: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x121 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1e8 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x049 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3921; op2val:0x35e8; +op3val:0x3449; valaddr_reg:x4; val_offset:4788*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4788*FLEN/8, x5, x2, x3) + +inst_1622: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x121 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1e8 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x049 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3921; op2val:0x35e8; +op3val:0x3449; valaddr_reg:x4; val_offset:4791*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 4791*FLEN/8, x5, x2, x3) + +inst_1623: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x121 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1e8 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x049 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3921; op2val:0x35e8; +op3val:0x3449; valaddr_reg:x4; val_offset:4794*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4794*FLEN/8, x5, x2, x3) + +inst_1624: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x121 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1e8 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x049 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3921; op2val:0x35e8; +op3val:0x3449; valaddr_reg:x4; val_offset:4797*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4797*FLEN/8, x5, x2, x3) + +inst_1625: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x21c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x34f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1d5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x361c; op2val:0x3f4f; +op3val:0x39d5; valaddr_reg:x4; val_offset:4800*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4800*FLEN/8, x5, x2, x3) + +inst_1626: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x21c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x34f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1d5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x361c; op2val:0x3f4f; +op3val:0x39d5; valaddr_reg:x4; val_offset:4803*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4803*FLEN/8, x5, x2, x3) + +inst_1627: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x21c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x34f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1d5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x361c; op2val:0x3f4f; +op3val:0x39d5; valaddr_reg:x4; val_offset:4806*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 4806*FLEN/8, x5, x2, x3) + +inst_1628: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x21c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x34f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1d5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x361c; op2val:0x3f4f; +op3val:0x39d5; valaddr_reg:x4; val_offset:4809*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4809*FLEN/8, x5, x2, x3) + +inst_1629: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x21c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x34f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1d5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x361c; op2val:0x3f4f; +op3val:0x39d5; valaddr_reg:x4; val_offset:4812*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4812*FLEN/8, x5, x2, x3) + +inst_1630: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x286 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2fd and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2b3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a86; op2val:0x32fd; +op3val:0x32b3; valaddr_reg:x4; val_offset:4815*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4815*FLEN/8, x5, x2, x3) + +inst_1631: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x286 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2fd and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2b3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a86; op2val:0x32fd; +op3val:0x32b3; valaddr_reg:x4; val_offset:4818*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4818*FLEN/8, x5, x2, x3) + +inst_1632: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x286 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2fd and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2b3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a86; op2val:0x32fd; +op3val:0x32b3; valaddr_reg:x4; val_offset:4821*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 4821*FLEN/8, x5, x2, x3) + +inst_1633: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x286 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2fd and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2b3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a86; op2val:0x32fd; +op3val:0x32b3; valaddr_reg:x4; val_offset:4824*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4824*FLEN/8, x5, x2, x3) + +inst_1634: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x286 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2fd and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2b3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a86; op2val:0x32fd; +op3val:0x32b3; valaddr_reg:x4; val_offset:4827*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4827*FLEN/8, x5, x2, x3) + +inst_1635: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x34b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x03b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x01c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x374b; op2val:0x3c3b; +op3val:0x381c; valaddr_reg:x4; val_offset:4830*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4830*FLEN/8, x5, x2, x3) + +inst_1636: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x34b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x03b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x01c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x374b; op2val:0x3c3b; +op3val:0x381c; valaddr_reg:x4; val_offset:4833*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4833*FLEN/8, x5, x2, x3) + +inst_1637: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x34b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x03b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x01c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x374b; op2val:0x3c3b; +op3val:0x381c; valaddr_reg:x4; val_offset:4836*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 4836*FLEN/8, x5, x2, x3) + +inst_1638: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x34b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x03b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x01c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x374b; op2val:0x3c3b; +op3val:0x381c; valaddr_reg:x4; val_offset:4839*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4839*FLEN/8, x5, x2, x3) + +inst_1639: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x34b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x03b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x01c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x374b; op2val:0x3c3b; +op3val:0x381c; valaddr_reg:x4; val_offset:4842*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4842*FLEN/8, x5, x2, x3) + +inst_1640: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x271 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x33b and fs3 == 0 and fe3 == 0x0a and fm3 == 0x2e9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a71; op2val:0x273b; +op3val:0x2ae9; valaddr_reg:x4; val_offset:4845*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4845*FLEN/8, x5, x2, x3) + +inst_1641: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x271 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x33b and fs3 == 0 and fe3 == 0x0a and fm3 == 0x2e9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a71; op2val:0x273b; +op3val:0x2ae9; valaddr_reg:x4; val_offset:4848*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4848*FLEN/8, x5, x2, x3) + +inst_1642: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x271 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x33b and fs3 == 0 and fe3 == 0x0a and fm3 == 0x2e9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a71; op2val:0x273b; +op3val:0x2ae9; valaddr_reg:x4; val_offset:4851*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 4851*FLEN/8, x5, x2, x3) + +inst_1643: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x271 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x33b and fs3 == 0 and fe3 == 0x0a and fm3 == 0x2e9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a71; op2val:0x273b; +op3val:0x2ae9; valaddr_reg:x4; val_offset:4854*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4854*FLEN/8, x5, x2, x3) + +inst_1644: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x271 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x33b and fs3 == 0 and fe3 == 0x0a and fm3 == 0x2e9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a71; op2val:0x273b; +op3val:0x2ae9; valaddr_reg:x4; val_offset:4857*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4857*FLEN/8, x5, x2, x3) + +inst_1645: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ce and fs2 == 0 and fe2 == 0x0c and fm2 == 0x131 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x311 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37ce; op2val:0x3131; +op3val:0x2f11; valaddr_reg:x4; val_offset:4860*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4860*FLEN/8, x5, x2, x3) + +inst_1646: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ce and fs2 == 0 and fe2 == 0x0c and fm2 == 0x131 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x311 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37ce; op2val:0x3131; +op3val:0x2f11; valaddr_reg:x4; val_offset:4863*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4863*FLEN/8, x5, x2, x3) + +inst_1647: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ce and fs2 == 0 and fe2 == 0x0c and fm2 == 0x131 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x311 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37ce; op2val:0x3131; +op3val:0x2f11; valaddr_reg:x4; val_offset:4866*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 4866*FLEN/8, x5, x2, x3) + +inst_1648: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ce and fs2 == 0 and fe2 == 0x0c and fm2 == 0x131 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x311 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37ce; op2val:0x3131; +op3val:0x2f11; valaddr_reg:x4; val_offset:4869*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4869*FLEN/8, x5, x2, x3) + +inst_1649: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ce and fs2 == 0 and fe2 == 0x0c and fm2 == 0x131 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x311 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37ce; op2val:0x3131; +op3val:0x2f11; valaddr_reg:x4; val_offset:4872*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4872*FLEN/8, x5, x2, x3) + +inst_1650: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x18d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x007 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x219 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x358d; op2val:0x3c07; +op3val:0x3619; valaddr_reg:x4; val_offset:4875*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4875*FLEN/8, x5, x2, x3) + +inst_1651: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x18d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x007 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x219 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x358d; op2val:0x3c07; +op3val:0x3619; valaddr_reg:x4; val_offset:4878*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4878*FLEN/8, x5, x2, x3) + +inst_1652: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x18d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x007 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x219 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x358d; op2val:0x3c07; +op3val:0x3619; valaddr_reg:x4; val_offset:4881*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 4881*FLEN/8, x5, x2, x3) + +inst_1653: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x18d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x007 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x219 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x358d; op2val:0x3c07; +op3val:0x3619; valaddr_reg:x4; val_offset:4884*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4884*FLEN/8, x5, x2, x3) + +inst_1654: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x18d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x007 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x219 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x358d; op2val:0x3c07; +op3val:0x3619; valaddr_reg:x4; val_offset:4887*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4887*FLEN/8, x5, x2, x3) + +inst_1655: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3cf and fs2 == 0 and fe2 == 0x0b and fm2 == 0x174 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x353 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bcf; op2val:0x2d74; +op3val:0x2f53; valaddr_reg:x4; val_offset:4890*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4890*FLEN/8, x5, x2, x3) + +inst_1656: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3cf and fs2 == 0 and fe2 == 0x0b and fm2 == 0x174 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x353 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bcf; op2val:0x2d74; +op3val:0x2f53; valaddr_reg:x4; val_offset:4893*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4893*FLEN/8, x5, x2, x3) + +inst_1657: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3cf and fs2 == 0 and fe2 == 0x0b and fm2 == 0x174 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x353 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bcf; op2val:0x2d74; +op3val:0x2f53; valaddr_reg:x4; val_offset:4896*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 4896*FLEN/8, x5, x2, x3) + +inst_1658: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3cf and fs2 == 0 and fe2 == 0x0b and fm2 == 0x174 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x353 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bcf; op2val:0x2d74; +op3val:0x2f53; valaddr_reg:x4; val_offset:4899*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4899*FLEN/8, x5, x2, x3) + +inst_1659: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3cf and fs2 == 0 and fe2 == 0x0b and fm2 == 0x174 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x353 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bcf; op2val:0x2d74; +op3val:0x2f53; valaddr_reg:x4; val_offset:4902*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4902*FLEN/8, x5, x2, x3) + +inst_1660: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x182 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x132 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x368 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3182; op2val:0x4532; +op3val:0x3b68; valaddr_reg:x4; val_offset:4905*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4905*FLEN/8, x5, x2, x3) + +inst_1661: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x182 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x132 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x368 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3182; op2val:0x4532; +op3val:0x3b68; valaddr_reg:x4; val_offset:4908*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4908*FLEN/8, x5, x2, x3) + +inst_1662: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x182 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x132 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x368 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3182; op2val:0x4532; +op3val:0x3b68; valaddr_reg:x4; val_offset:4911*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 4911*FLEN/8, x5, x2, x3) + +inst_1663: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x182 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x132 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x368 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3182; op2val:0x4532; +op3val:0x3b68; valaddr_reg:x4; val_offset:4914*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4914*FLEN/8, x5, x2, x3) + +inst_1664: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x182 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x132 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x368 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3182; op2val:0x4532; +op3val:0x3b68; valaddr_reg:x4; val_offset:4917*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4917*FLEN/8, x5, x2, x3) + +inst_1665: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x35e and fs2 == 0 and fe2 == 0x0d and fm2 == 0x177 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x188 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b5e; op2val:0x3577; +op3val:0x3588; valaddr_reg:x4; val_offset:4920*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4920*FLEN/8, x5, x2, x3) + +inst_1666: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x35e and fs2 == 0 and fe2 == 0x0d and fm2 == 0x177 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x188 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b5e; op2val:0x3577; +op3val:0x3588; valaddr_reg:x4; val_offset:4923*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4923*FLEN/8, x5, x2, x3) + +inst_1667: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x35e and fs2 == 0 and fe2 == 0x0d and fm2 == 0x177 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x188 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b5e; op2val:0x3577; +op3val:0x3588; valaddr_reg:x4; val_offset:4926*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 4926*FLEN/8, x5, x2, x3) + +inst_1668: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x35e and fs2 == 0 and fe2 == 0x0d and fm2 == 0x177 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x188 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b5e; op2val:0x3577; +op3val:0x3588; valaddr_reg:x4; val_offset:4929*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4929*FLEN/8, x5, x2, x3) + +inst_1669: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x35e and fs2 == 0 and fe2 == 0x0d and fm2 == 0x177 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x188 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b5e; op2val:0x3577; +op3val:0x3588; valaddr_reg:x4; val_offset:4932*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4932*FLEN/8, x5, x2, x3) + +inst_1670: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a6 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x06d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x280 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35a6; op2val:0x406d; +op3val:0x3a80; valaddr_reg:x4; val_offset:4935*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4935*FLEN/8, x5, x2, x3) + +inst_1671: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a6 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x06d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x280 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35a6; op2val:0x406d; +op3val:0x3a80; valaddr_reg:x4; val_offset:4938*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4938*FLEN/8, x5, x2, x3) + +inst_1672: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a6 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x06d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x280 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35a6; op2val:0x406d; +op3val:0x3a80; valaddr_reg:x4; val_offset:4941*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 4941*FLEN/8, x5, x2, x3) + +inst_1673: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a6 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x06d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x280 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35a6; op2val:0x406d; +op3val:0x3a80; valaddr_reg:x4; val_offset:4944*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4944*FLEN/8, x5, x2, x3) + +inst_1674: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a6 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x06d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x280 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35a6; op2val:0x406d; +op3val:0x3a80; valaddr_reg:x4; val_offset:4947*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4947*FLEN/8, x5, x2, x3) + +inst_1675: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x11f and fs2 == 0 and fe2 == 0x13 and fm2 == 0x174 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x33b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x291f; op2val:0x4d74; +op3val:0x3b3b; valaddr_reg:x4; val_offset:4950*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4950*FLEN/8, x5, x2, x3) + +inst_1676: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x11f and fs2 == 0 and fe2 == 0x13 and fm2 == 0x174 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x33b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x291f; op2val:0x4d74; +op3val:0x3b3b; valaddr_reg:x4; val_offset:4953*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4953*FLEN/8, x5, x2, x3) + +inst_1677: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x11f and fs2 == 0 and fe2 == 0x13 and fm2 == 0x174 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x33b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x291f; op2val:0x4d74; +op3val:0x3b3b; valaddr_reg:x4; val_offset:4956*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 4956*FLEN/8, x5, x2, x3) + +inst_1678: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x11f and fs2 == 0 and fe2 == 0x13 and fm2 == 0x174 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x33b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x291f; op2val:0x4d74; +op3val:0x3b3b; valaddr_reg:x4; val_offset:4959*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4959*FLEN/8, x5, x2, x3) + +inst_1679: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x11f and fs2 == 0 and fe2 == 0x13 and fm2 == 0x174 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x33b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x291f; op2val:0x4d74; +op3val:0x3b3b; valaddr_reg:x4; val_offset:4962*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4962*FLEN/8, x5, x2, x3) + +inst_1680: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x29c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2e4 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1b2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x329c; op2val:0x3ae4; +op3val:0x31b2; valaddr_reg:x4; val_offset:4965*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4965*FLEN/8, x5, x2, x3) + +inst_1681: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x29c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2e4 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1b2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x329c; op2val:0x3ae4; +op3val:0x31b2; valaddr_reg:x4; val_offset:4968*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4968*FLEN/8, x5, x2, x3) + +inst_1682: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x29c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2e4 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1b2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x329c; op2val:0x3ae4; +op3val:0x31b2; valaddr_reg:x4; val_offset:4971*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4971*FLEN/8, x5, x2, x3) + +inst_1683: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x29c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2e4 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1b2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x329c; op2val:0x3ae4; +op3val:0x31b2; valaddr_reg:x4; val_offset:4974*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4974*FLEN/8, x5, x2, x3) + +inst_1684: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x01e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1bc and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x381e; op2val:0x3dbc; +op3val:0x39e8; valaddr_reg:x4; val_offset:4977*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4977*FLEN/8, x5, x2, x3) + +inst_1685: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x01e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1bc and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x381e; op2val:0x3dbc; +op3val:0x39e8; valaddr_reg:x4; val_offset:4980*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4980*FLEN/8, x5, x2, x3) + +inst_1686: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x01e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1bc and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x381e; op2val:0x3dbc; +op3val:0x39e8; valaddr_reg:x4; val_offset:4983*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 64, 0, x4, 4983*FLEN/8, x5, x2, x3) + +inst_1687: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x01e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1bc and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x381e; op2val:0x3dbc; +op3val:0x39e8; valaddr_reg:x4; val_offset:4986*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4986*FLEN/8, x5, x2, x3) + +inst_1688: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x01e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1bc and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x381e; op2val:0x3dbc; +op3val:0x39e8; valaddr_reg:x4; val_offset:4989*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 128, 0, x4, 4989*FLEN/8, x5, x2, x3) + +inst_1689: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0d and fm2 == 0x165 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x165 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bff; op2val:0x3565; +op3val:0x3565; valaddr_reg:x4; val_offset:4992*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 32, 0, x4, 4992*FLEN/8, x5, x2, x3) + +inst_1690: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x03c and fs2 == 0 and fe2 == 0x0d and fm2 == 0x341 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3b0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x383c; op2val:0x3741; +op3val:0x33b0; valaddr_reg:x4; val_offset:4995*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 96, 0, x4, 4995*FLEN/8, x5, x2, x3) + +inst_1691: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x103 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1dd and fs3 == 0 and fe3 == 0x0c and fm3 == 0x35b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3903; op2val:0x35dd; +op3val:0x335b; valaddr_reg:x4; val_offset:4998*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x4, 4998*FLEN/8, x5, x2, x3) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(12956,32,FLEN) +NAN_BOXED(15076,32,FLEN) +NAN_BOXED(12956,32,FLEN) +NAN_BOXED(12956,32,FLEN) +NAN_BOXED(15076,32,FLEN) +NAN_BOXED(15076,32,FLEN) +NAN_BOXED(12956,32,FLEN) +NAN_BOXED(15076,32,FLEN) +NAN_BOXED(12722,32,FLEN) +NAN_BOXED(12956,32,FLEN) +NAN_BOXED(15076,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(12956,32,FLEN) +NAN_BOXED(15076,32,FLEN) +NAN_BOXED(12956,32,FLEN) +NAN_BOXED(14366,32,FLEN) +NAN_BOXED(14366,32,FLEN) +NAN_BOXED(14366,32,FLEN) +NAN_BOXED(14366,32,FLEN) +NAN_BOXED(14366,32,FLEN) +NAN_BOXED(14824,32,FLEN) +NAN_BOXED(14366,32,FLEN) +NAN_BOXED(15804,32,FLEN) +NAN_BOXED(15804,32,FLEN) +NAN_BOXED(14366,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(14824,32,FLEN) +NAN_BOXED(14366,32,FLEN) +NAN_BOXED(14366,32,FLEN) +NAN_BOXED(14366,32,FLEN) +NAN_BOXED(15359,32,FLEN) +NAN_BOXED(13669,32,FLEN) +NAN_BOXED(13669,32,FLEN) +NAN_BOXED(15359,32,FLEN) +NAN_BOXED(15359,32,FLEN) +NAN_BOXED(13669,32,FLEN) +NAN_BOXED(15359,32,FLEN) +NAN_BOXED(13669,32,FLEN) +NAN_BOXED(13669,32,FLEN) +test_dataset_1: +NAN_BOXED(15359,32,FLEN) +NAN_BOXED(13669,32,FLEN) +NAN_BOXED(13669,32,FLEN) +NAN_BOXED(15359,32,FLEN) +NAN_BOXED(13669,32,FLEN) +NAN_BOXED(13669,32,FLEN) +NAN_BOXED(14396,32,FLEN) +NAN_BOXED(14145,32,FLEN) +NAN_BOXED(13232,32,FLEN) +NAN_BOXED(14396,32,FLEN) +NAN_BOXED(14145,32,FLEN) +NAN_BOXED(13232,32,FLEN) +NAN_BOXED(14396,32,FLEN) +NAN_BOXED(14145,32,FLEN) +NAN_BOXED(13232,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(14145,32,FLEN) +NAN_BOXED(13232,32,FLEN) +NAN_BOXED(14396,32,FLEN) +NAN_BOXED(14145,32,FLEN) +NAN_BOXED(13232,32,FLEN) +NAN_BOXED(14595,32,FLEN) +NAN_BOXED(13789,32,FLEN) +NAN_BOXED(13147,32,FLEN) +NAN_BOXED(14595,32,FLEN) +NAN_BOXED(13789,32,FLEN) +NAN_BOXED(13147,32,FLEN) +NAN_BOXED(14595,32,FLEN) +NAN_BOXED(13789,32,FLEN) +NAN_BOXED(13147,32,FLEN) +NAN_BOXED(14595,32,FLEN) +NAN_BOXED(13789,32,FLEN) +NAN_BOXED(13147,32,FLEN) +NAN_BOXED(14595,32,FLEN) +NAN_BOXED(13789,32,FLEN) +NAN_BOXED(13147,32,FLEN) +test_dataset_2: +NAN_BOXED(14801,16,FLEN) +NAN_BOXED(13403,16,FLEN) +NAN_BOXED(12886,16,FLEN) +NAN_BOXED(14801,16,FLEN) +NAN_BOXED(13403,16,FLEN) +NAN_BOXED(12886,16,FLEN) +NAN_BOXED(14801,16,FLEN) +NAN_BOXED(13403,16,FLEN) +NAN_BOXED(12886,16,FLEN) +NAN_BOXED(14801,16,FLEN) +NAN_BOXED(13403,16,FLEN) +NAN_BOXED(12886,16,FLEN) +NAN_BOXED(14801,16,FLEN) +NAN_BOXED(13403,16,FLEN) +NAN_BOXED(12886,16,FLEN) +NAN_BOXED(13394,16,FLEN) +NAN_BOXED(16470,16,FLEN) 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+NAN_BOXED(19828,16,FLEN) +NAN_BOXED(15163,16,FLEN) +NAN_BOXED(10527,16,FLEN) +NAN_BOXED(19828,16,FLEN) +NAN_BOXED(15163,16,FLEN) +NAN_BOXED(10527,16,FLEN) +NAN_BOXED(19828,16,FLEN) +NAN_BOXED(15163,16,FLEN) +NAN_BOXED(12956,16,FLEN) +NAN_BOXED(15076,16,FLEN) +NAN_BOXED(12722,16,FLEN) +NAN_BOXED(12956,16,FLEN) +NAN_BOXED(15076,16,FLEN) +NAN_BOXED(12722,16,FLEN) +NAN_BOXED(12956,16,FLEN) +NAN_BOXED(15076,16,FLEN) +NAN_BOXED(12722,16,FLEN) +NAN_BOXED(12956,16,FLEN) +NAN_BOXED(15076,16,FLEN) +NAN_BOXED(12722,16,FLEN) +NAN_BOXED(14366,16,FLEN) +NAN_BOXED(15804,16,FLEN) +NAN_BOXED(14824,16,FLEN) +NAN_BOXED(14366,16,FLEN) +NAN_BOXED(15804,16,FLEN) +NAN_BOXED(14824,16,FLEN) +NAN_BOXED(14366,16,FLEN) +NAN_BOXED(15804,16,FLEN) +NAN_BOXED(14824,16,FLEN) +NAN_BOXED(14366,16,FLEN) +NAN_BOXED(15804,16,FLEN) +NAN_BOXED(14824,16,FLEN) +NAN_BOXED(14366,16,FLEN) +NAN_BOXED(15804,16,FLEN) +NAN_BOXED(14824,16,FLEN) +NAN_BOXED(15359,16,FLEN) +NAN_BOXED(13669,16,FLEN) +NAN_BOXED(13669,16,FLEN) +NAN_BOXED(14396,16,FLEN) +NAN_BOXED(14145,16,FLEN) +NAN_BOXED(13232,16,FLEN) +NAN_BOXED(14595,16,FLEN) +NAN_BOXED(13789,16,FLEN) +NAN_BOXED(13147,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x6_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x6_1: + .fill 30*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_0: + .fill 30*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_0: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_1: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_2: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_3: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_4: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_5: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_6: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_7: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_8: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_9: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_10: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_11: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_12: + .fill 252*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fnmsub_b14-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fnmsub_b14-01.S new file mode 100644 index 000000000..05660e5bf --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fnmsub_b14-01.S @@ -0,0 +1,514 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 06:07:02 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fnmsub.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fnmsub.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fnmsub_b14 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fnmsub_b14) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x2,test_dataset_0) +RVTEST_SIGBASE(x7,signature_x7_1) + +inst_0: +// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==x29, rs2==x29, rs3==x0, rd==x26,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x05a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ea and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x29; op2:x29; op3:x0; dest:x26; op1val:0x739c; op2val:0x739c; +op3val:0x0; valaddr_reg:x2; val_offset:0*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x26, x29, x29, x0, dyn, 0, 0, x2, 0*FLEN/8, x9, x7, x10) + +inst_1: +// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==x6, rs2==x21, rs3==x30, rd==x6,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x05a and fs3 == 0 and fe3 == 0x0f and fm3 == 0x1ea and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x6; op2:x21; op3:x30; dest:x6; op1val:0x739c; op2val:0x785a; +op3val:0x3dea; valaddr_reg:x2; val_offset:3*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x6, x6, x21, x30, dyn, 0, 0, x2, 3*FLEN/8, x9, x7, x10) + +inst_2: +// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==x27, rs2==x6, rs3==x26, rd==x8,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x05a and fs3 == 0 and fe3 == 0x10 and fm3 == 0x1ea and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x27; op2:x6; op3:x26; dest:x8; op1val:0x739c; op2val:0x785a; +op3val:0x41ea; valaddr_reg:x2; val_offset:6*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x8, x27, x6, x26, dyn, 0, 0, x2, 6*FLEN/8, x9, x7, x10) + +inst_3: +// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==x17, rs2==x4, rs3==x17, rd==x22,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x05a and fs3 == 0 and fe3 == 0x11 and fm3 == 0x1ea and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x17; op2:x4; op3:x17; dest:x22; op1val:0x739c; op2val:0x785a; +op3val:0x739c; valaddr_reg:x2; val_offset:9*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x22, x17, x4, x17, dyn, 0, 0, x2, 9*FLEN/8, x9, x7, x10) + +inst_4: +// rs1 == rs2 == rs3 != rd, rs1==x1, rs2==x1, rs3==x1, rd==x21,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x05a and fs3 == 0 and fe3 == 0x12 and fm3 == 0x1ea and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x1; op2:x1; op3:x1; dest:x21; op1val:0x739c; op2val:0x739c; +op3val:0x739c; valaddr_reg:x2; val_offset:12*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x21, x1, x1, x1, dyn, 0, 0, x2, 12*FLEN/8, x9, x7, x10) + +inst_5: +// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==x5, rs2==x3, rs3==x15, rd==x15,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x05a and fs3 == 0 and fe3 == 0x13 and fm3 == 0x1ea and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x5; op2:x3; op3:x15; dest:x15; op1val:0x739c; op2val:0x785a; +op3val:0x4dea; valaddr_reg:x2; val_offset:15*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x15, x5, x3, x15, dyn, 0, 0, x2, 15*FLEN/8, x9, x7, x10) + +inst_6: +// rd == rs2 == rs3 != rs1, rs1==x30, rs2==x14, rs3==x14, rd==x14,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x05a and fs3 == 0 and fe3 == 0x14 and fm3 == 0x1ea and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x14; op3:x14; dest:x14; op1val:0x739c; op2val:0x785a; +op3val:0x785a; valaddr_reg:x2; val_offset:18*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x14, x30, x14, x14, dyn, 0, 0, x2, 18*FLEN/8, x9, x7, x10) + +inst_7: +// rs1 == rd == rs3 != rs2, rs1==x31, rs2==x8, rs3==x31, rd==x31,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x05a and fs3 == 0 and fe3 == 0x15 and fm3 == 0x1ea and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x31; op2:x8; op3:x31; dest:x31; op1val:0x739c; op2val:0x785a; +op3val:0x739c; valaddr_reg:x2; val_offset:21*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x31, x8, x31, dyn, 0, 0, x2, 21*FLEN/8, x9, x7, x10) + +inst_8: +// rs1 == rs2 == rs3 == rd, rs1==x28, rs2==x28, rs3==x28, rd==x28,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x05a and fs3 == 0 and fe3 == 0x16 and fm3 == 0x1ea and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x28; op2:x28; op3:x28; dest:x28; op1val:0x739c; op2val:0x739c; +op3val:0x739c; valaddr_reg:x2; val_offset:24*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x28, x28, x28, x28, dyn, 0, 0, x2, 24*FLEN/8, x9, x7, x10) + +inst_9: +// rs1 == rs2 == rd != rs3, rs1==x25, rs2==x25, rs3==x12, rd==x25,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x05a and fs3 == 0 and fe3 == 0x17 and fm3 == 0x1ea and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x25; op2:x25; op3:x12; dest:x25; op1val:0x739c; op2val:0x739c; +op3val:0x5dea; valaddr_reg:x2; val_offset:27*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x25, x25, x25, x12, dyn, 0, 0, x2, 27*FLEN/8, x9, x7, x10) + +inst_10: +// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==x23, rs2==x19, rs3==x6, rd==x19,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x05a and fs3 == 0 and fe3 == 0x18 and fm3 == 0x1ea and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x23; op2:x19; op3:x6; dest:x19; op1val:0x739c; op2val:0x785a; +op3val:0x61ea; valaddr_reg:x2; val_offset:30*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x19, x23, x19, x6, dyn, 0, 0, x2, 30*FLEN/8, x9, x7, x10) + +inst_11: +// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==x22, rs2==x13, rs3==x13, rd==x16,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x05a and fs3 == 0 and fe3 == 0x19 and fm3 == 0x1ea and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x22; op2:x13; op3:x13; dest:x16; op1val:0x739c; op2val:0x785a; +op3val:0x785a; valaddr_reg:x2; val_offset:33*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x16, x22, x13, x13, dyn, 0, 0, x2, 33*FLEN/8, x9, x7, x10) +RVTEST_VALBASEUPD(x6,test_dataset_1) + +inst_12: +// rs1==x0, rs2==x30, rs3==x4, rd==x23,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x05a and fs3 == 0 and fe3 == 0x1a and fm3 == 0x1ea and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x0; op2:x30; op3:x4; dest:x23; op1val:0x0; op2val:0x785a; +op3val:0x69ea; valaddr_reg:x6; val_offset:0*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x23, x0, x30, x4, dyn, 0, 0, x6, 0*FLEN/8, x12, x7, x10) + +inst_13: +// rs1==x13, rs2==x9, rs3==x22, rd==x3,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x05a and fs3 == 0 and fe3 == 0x1b and fm3 == 0x1ea and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x13; op2:x9; op3:x22; dest:x3; op1val:0x739c; op2val:0x785a; +op3val:0x6dea; valaddr_reg:x6; val_offset:3*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x3, x13, x9, x22, dyn, 0, 0, x6, 3*FLEN/8, x12, x7, x10) + +inst_14: +// rs1==x14, rs2==x27, rs3==x29, rd==x2,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x05a and fs3 == 0 and fe3 == 0x1c and fm3 == 0x1ea and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x14; op2:x27; op3:x29; dest:x2; op1val:0x739c; op2val:0x785a; +op3val:0x71ea; valaddr_reg:x6; val_offset:6*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x2, x14, x27, x29, dyn, 0, 0, x6, 6*FLEN/8, x12, x7, x10) + +inst_15: +// rs1==x10, rs2==x17, rs3==x9, rd==x18,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x05a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1ea and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x10; op2:x17; op3:x9; dest:x18; op1val:0x739c; op2val:0x785a; +op3val:0x75ea; valaddr_reg:x6; val_offset:9*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x18, x10, x17, x9, dyn, 0, 0, x6, 9*FLEN/8, x12, x7, x3) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_16: +// rs1==x7, rs2==x15, rs3==x23, rd==x17,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x05a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ea and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x7; op2:x15; op3:x23; dest:x17; op1val:0x739c; op2val:0x785a; +op3val:0x79ea; valaddr_reg:x6; val_offset:12*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x17, x7, x15, x23, dyn, 0, 0, x6, 12*FLEN/8, x12, x1, x3) + +inst_17: +// rs1==x21, rs2==x18, rs3==x5, rd==x20,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x05a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x21; op2:x18; op3:x5; dest:x20; op1val:0x739c; op2val:0x785a; +op3val:0x7bff; valaddr_reg:x6; val_offset:15*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x20, x21, x18, x5, dyn, 0, 0, x6, 15*FLEN/8, x12, x1, x3) + +inst_18: +// rs1==x4, rs2==x26, rs3==x21, rd==x5, +/* opcode: fnmsub.h ; op1:x4; op2:x26; op3:x21; dest:x5; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x6; val_offset:18*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x5, x4, x26, x21, dyn, 0, 0, x6, 18*FLEN/8, x12, x1, x3) + +inst_19: +// rs1==x8, rs2==x7, rs3==x19, rd==x10, +/* opcode: fnmsub.h ; op1:x8; op2:x7; op3:x19; dest:x10; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x6; val_offset:21*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x10, x8, x7, x19, dyn, 0, 0, x6, 21*FLEN/8, x12, x1, x3) + +inst_20: +// rs1==x19, rs2==x2, rs3==x11, rd==x30, +/* opcode: fnmsub.h ; op1:x19; op2:x2; op3:x11; dest:x30; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x6; val_offset:24*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x30, x19, x2, x11, dyn, 0, 0, x6, 24*FLEN/8, x12, x1, x3) + +inst_21: +// rs1==x9, rs2==x22, rs3==x25, rd==x11, +/* opcode: fnmsub.h ; op1:x9; op2:x22; op3:x25; dest:x11; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x6; val_offset:27*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x11, x9, x22, x25, dyn, 0, 0, x6, 27*FLEN/8, x12, x1, x3) + +inst_22: +// rs1==x16, rs2==x5, rs3==x10, rd==x29, +/* opcode: fnmsub.h ; op1:x16; op2:x5; op3:x10; dest:x29; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x6; val_offset:30*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x29, x16, x5, x10, dyn, 0, 0, x6, 30*FLEN/8, x12, x1, x3) +RVTEST_VALBASEUPD(x6,test_dataset_2) + +inst_23: +// rs1==x12, rs2==x31, rs3==x18, rd==x9, +/* opcode: fnmsub.h ; op1:x12; op2:x31; op3:x18; dest:x9; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x6; val_offset:0*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x9, x12, x31, x18, dyn, 0, 0, x6, 0*FLEN/8, x8, x1, x3) + +inst_24: +// rs1==x26, rs2==x23, rs3==x3, rd==x27, +/* opcode: fnmsub.h ; op1:x26; op2:x23; op3:x3; dest:x27; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x6; val_offset:3*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x27, x26, x23, x3, dyn, 0, 0, x6, 3*FLEN/8, x8, x1, x3) + +inst_25: +// rs1==x18, rs2==x11, rs3==x20, rd==x24, +/* opcode: fnmsub.h ; op1:x18; op2:x11; op3:x20; dest:x24; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x6; val_offset:6*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x24, x18, x11, x20, dyn, 0, 0, x6, 6*FLEN/8, x8, x1, x3) + +inst_26: +// rs1==x3, rs2==x20, rs3==x7, rd==x13, +/* opcode: fnmsub.h ; op1:x3; op2:x20; op3:x7; dest:x13; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x6; val_offset:9*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x13, x3, x20, x7, dyn, 0, 0, x6, 9*FLEN/8, x8, x1, x5) +RVTEST_SIGBASE(x3,signature_x3_0) + +inst_27: +// rs1==x11, rs2==x12, rs3==x2, rd==x7, +/* opcode: fnmsub.h ; op1:x11; op2:x12; op3:x2; dest:x7; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x6; val_offset:12*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x7, x11, x12, x2, dyn, 0, 0, x6, 12*FLEN/8, x8, x3, x5) + +inst_28: +// rs1==x24, rs2==x16, rs3==x8, rd==x0, +/* opcode: fnmsub.h ; op1:x24; op2:x16; op3:x8; dest:x0; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x6; val_offset:15*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x0, x24, x16, x8, dyn, 0, 0, x6, 15*FLEN/8, x8, x3, x5) + +inst_29: +// rs1==x20, rs2==x24, rs3==x27, rd==x12, +/* opcode: fnmsub.h ; op1:x20; op2:x24; op3:x27; dest:x12; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x6; val_offset:18*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x12, x20, x24, x27, dyn, 0, 0, x6, 18*FLEN/8, x8, x3, x5) + +inst_30: +// rs1==x15, rs2==x0, rs3==x16, rd==x4, +/* opcode: fnmsub.h ; op1:x15; op2:x0; op3:x16; dest:x4; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x6; val_offset:21*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x4, x15, x0, x16, dyn, 0, 0, x6, 21*FLEN/8, x8, x3, x5) + +inst_31: +// rs1==x2, rs2==x10, rs3==x24, rd==x1, +/* opcode: fnmsub.h ; op1:x2; op2:x10; op3:x24; dest:x1; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x6; val_offset:24*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x1, x2, x10, x24, dyn, 0, 0, x6, 24*FLEN/8, x8, x3, x5) + +inst_32: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x05a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ea and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x739c; op2val:0x785a; +op3val:0x39ea; valaddr_reg:x6; val_offset:27*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x6, 27*FLEN/8, x8, x3, x5) + +inst_33: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x05a and fs3 == 0 and fe3 == 0x11 and fm3 == 0x1ea and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x739c; op2val:0x785a; +op3val:0x45ea; valaddr_reg:x6; val_offset:30*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x6, 30*FLEN/8, x8, x3, x5) + +inst_34: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x05a and fs3 == 0 and fe3 == 0x12 and fm3 == 0x1ea and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x739c; op2val:0x785a; +op3val:0x49ea; valaddr_reg:x6; val_offset:33*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x6, 33*FLEN/8, x8, x3, x5) + +inst_35: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x05a and fs3 == 0 and fe3 == 0x14 and fm3 == 0x1ea and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x739c; op2val:0x785a; +op3val:0x51ea; valaddr_reg:x6; val_offset:36*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x6, 36*FLEN/8, x8, x3, x5) + +inst_36: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x05a and fs3 == 0 and fe3 == 0x15 and fm3 == 0x1ea and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x739c; op2val:0x785a; +op3val:0x55ea; valaddr_reg:x6; val_offset:39*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x6, 39*FLEN/8, x8, x3, x5) + +inst_37: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x05a and fs3 == 0 and fe3 == 0x16 and fm3 == 0x1ea and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x739c; op2val:0x785a; +op3val:0x59ea; valaddr_reg:x6; val_offset:42*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x6, 42*FLEN/8, x8, x3, x5) + +inst_38: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x05a and fs3 == 0 and fe3 == 0x17 and fm3 == 0x1ea and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x739c; op2val:0x785a; +op3val:0x5dea; valaddr_reg:x6; val_offset:45*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x6, 45*FLEN/8, x8, x3, x5) + +inst_39: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x05a and fs3 == 0 and fe3 == 0x19 and fm3 == 0x1ea and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x739c; op2val:0x785a; +op3val:0x65ea; valaddr_reg:x6; val_offset:48*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x6, 48*FLEN/8, x8, x3, x5) + +inst_40: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x05a and fs3 == 0 and fe3 == 0x1a and fm3 == 0x1ea and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x739c; op2val:0x785a; +op3val:0x69ea; valaddr_reg:x6; val_offset:51*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x6, 51*FLEN/8, x8, x3, x5) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(30810,32,FLEN) +NAN_BOXED(15850,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(30810,32,FLEN) +NAN_BOXED(16874,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(30810,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(30810,32,FLEN) +NAN_BOXED(19946,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(30810,32,FLEN) +NAN_BOXED(30810,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(30810,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(24042,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(30810,32,FLEN) +NAN_BOXED(25066,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(30810,32,FLEN) +NAN_BOXED(30810,32,FLEN) +test_dataset_1: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(30810,32,FLEN) +NAN_BOXED(27114,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(30810,32,FLEN) +NAN_BOXED(28138,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(30810,32,FLEN) +NAN_BOXED(29162,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(30810,32,FLEN) +NAN_BOXED(30186,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(30810,32,FLEN) +NAN_BOXED(31210,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(30810,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +test_dataset_2: +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(29596,16,FLEN) +NAN_BOXED(30810,16,FLEN) +NAN_BOXED(14826,16,FLEN) +NAN_BOXED(29596,16,FLEN) +NAN_BOXED(30810,16,FLEN) +NAN_BOXED(17898,16,FLEN) +NAN_BOXED(29596,16,FLEN) +NAN_BOXED(30810,16,FLEN) +NAN_BOXED(18922,16,FLEN) +NAN_BOXED(29596,16,FLEN) +NAN_BOXED(30810,16,FLEN) +NAN_BOXED(20970,16,FLEN) +NAN_BOXED(29596,16,FLEN) +NAN_BOXED(30810,16,FLEN) +NAN_BOXED(21994,16,FLEN) +NAN_BOXED(29596,16,FLEN) +NAN_BOXED(30810,16,FLEN) +NAN_BOXED(23018,16,FLEN) +NAN_BOXED(29596,16,FLEN) +NAN_BOXED(30810,16,FLEN) +NAN_BOXED(24042,16,FLEN) +NAN_BOXED(29596,16,FLEN) +NAN_BOXED(30810,16,FLEN) +NAN_BOXED(26090,16,FLEN) +NAN_BOXED(29596,16,FLEN) +NAN_BOXED(30810,16,FLEN) +NAN_BOXED(27114,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x7_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x7_1: + .fill 32*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_0: + .fill 22*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x3_0: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fnmsub_b16-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fnmsub_b16-01.S new file mode 100644 index 000000000..709ff8134 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fnmsub_b16-01.S @@ -0,0 +1,2231 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 06:07:02 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fnmsub.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fnmsub.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fnmsub_b16 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fnmsub_b16) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x9,signature_x9_1) + +inst_0: +// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==x23, rs2==x23, rs3==x3, rd==x16,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x05a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x23; op2:x23; op3:x3; dest:x16; op1val:0x739c; op2val:0x739c; +op3val:0x7bff; valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn; +testreg:x17; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x16, x23, x23, x3, dyn, 0, 0, x3, 0*FLEN/8, x18, x9, x17) + +inst_1: +// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==x6, rs2==x2, rs3==x28, rd==x6,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x100 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x6; op2:x2; op3:x28; dest:x6; op1val:0x78d4; op2val:0x7900; +op3val:0x7bff; valaddr_reg:x3; val_offset:3*FLEN/8; rmval:dyn; +testreg:x17; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x6, x6, x2, x28, dyn, 0, 0, x3, 3*FLEN/8, x18, x9, x17) + +inst_2: +// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==x16, rs2==x5, rs3==x30, rd==x8,fs1 == 0 and fe1 == 0x18 and fm1 == 0x2bd and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x16; op2:x5; op3:x30; dest:x8; op1val:0x62bd; op2val:0x7ab2; +op3val:0x7bff; valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn; +testreg:x17; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x8, x16, x5, x30, dyn, 0, 0, x3, 6*FLEN/8, x18, x9, x17) + +inst_3: +// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==x19, rs2==x21, rs3==x19, rd==x29,fs1 == 0 and fe1 == 0x1c and fm1 == 0x37e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3f6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x19; op2:x21; op3:x19; dest:x29; op1val:0x737e; op2val:0x7bf6; +op3val:0x737e; valaddr_reg:x3; val_offset:9*FLEN/8; rmval:dyn; +testreg:x17; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x29, x19, x21, x19, dyn, 0, 0, x3, 9*FLEN/8, x18, x9, x17) + +inst_4: +// rs1 == rs2 == rs3 != rd, rs1==x4, rs2==x4, rs3==x4, rd==x15,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x39e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x4; op2:x4; op3:x4; dest:x15; op1val:0x7ab0; op2val:0x7ab0; +op3val:0x7ab0; valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn; +testreg:x17; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x15, x4, x4, x4, dyn, 0, 0, x3, 12*FLEN/8, x18, x9, x17) + +inst_5: +// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==x1, rs2==x11, rs3==x12, rd==x12,fs1 == 0 and fe1 == 0x1c and fm1 == 0x0d1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x113 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x1; op2:x11; op3:x12; dest:x12; op1val:0x70d1; op2val:0x7913; +op3val:0x7bff; valaddr_reg:x3; val_offset:15*FLEN/8; rmval:dyn; +testreg:x17; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x12, x1, x11, x12, dyn, 0, 0, x3, 15*FLEN/8, x18, x9, x17) + +inst_6: +// rd == rs2 == rs3 != rs1, rs1==x25, rs2==x20, rs3==x20, rd==x20,fs1 == 0 and fe1 == 0x1e and fm1 == 0x02e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1ed and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x25; op2:x20; op3:x20; dest:x20; op1val:0x782e; op2val:0x79ed; +op3val:0x79ed; valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn; +testreg:x17; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x20, x25, x20, x20, dyn, 0, 0, x3, 18*FLEN/8, x18, x9, x17) + +inst_7: +// rs1 == rd == rs3 != rs2, rs1==x14, rs2==x15, rs3==x14, rd==x14,fs1 == 0 and fe1 == 0x1b and fm1 == 0x018 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x210 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x14; op2:x15; op3:x14; dest:x14; op1val:0x6c18; op2val:0x7a10; +op3val:0x6c18; valaddr_reg:x3; val_offset:21*FLEN/8; rmval:dyn; +testreg:x17; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x14, x14, x15, x14, dyn, 0, 0, x3, 21*FLEN/8, x18, x9, x17) + +inst_8: +// rs1 == rs2 == rs3 == rd, rs1==x13, rs2==x13, rs3==x13, rd==x13,fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d1 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x3ef and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x13; op2:x13; op3:x13; dest:x13; op1val:0x74d1; op2val:0x74d1; +op3val:0x74d1; valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn; +testreg:x17; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x13, x13, x13, x13, dyn, 0, 0, x3, 24*FLEN/8, x18, x9, x17) + +inst_9: +// rs1 == rs2 == rd != rs3, rs1==x24, rs2==x24, rs3==x5, rd==x24,fs1 == 0 and fe1 == 0x1d and fm1 == 0x38f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1bf and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x24; op2:x24; op3:x5; dest:x24; op1val:0x778f; op2val:0x778f; +op3val:0x7bff; valaddr_reg:x3; val_offset:27*FLEN/8; rmval:dyn; +testreg:x17; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x24, x24, x24, x5, dyn, 0, 0, x3, 27*FLEN/8, x18, x9, x17) + +inst_10: +// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==x2, rs2==x19, rs3==x9, rd==x19,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x35d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x2; op2:x19; op3:x9; dest:x19; op1val:0x79b5; op2val:0x7b5d; +op3val:0x7bff; valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn; +testreg:x17; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x19, x2, x19, x9, dyn, 0, 0, x3, 30*FLEN/8, x18, x9, x17) + +inst_11: +// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==x10, rs2==x26, rs3==x26, rd==x7,fs1 == 0 and fe1 == 0x1e and fm1 == 0x267 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x31c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x10; op2:x26; op3:x26; dest:x7; op1val:0x7a67; op2val:0x771c; +op3val:0x771c; valaddr_reg:x3; val_offset:33*FLEN/8; rmval:dyn; +testreg:x17; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x7, x10, x26, x26, dyn, 0, 0, x3, 33*FLEN/8, x18, x9, x17) +RVTEST_VALBASEUPD(x10,test_dataset_1) + +inst_12: +// rs1==x18, rs2==x3, rs3==x1, rd==x31,fs1 == 0 and fe1 == 0x1e and fm1 == 0x307 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x23b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x18; op2:x3; op3:x1; dest:x31; op1val:0x7b07; op2val:0x6e3b; +op3val:0x7bff; valaddr_reg:x10; val_offset:0*FLEN/8; rmval:dyn; +testreg:x17; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x18, x3, x1, dyn, 0, 0, x10, 0*FLEN/8, x16, x9, x17) +RVTEST_SIGBASE(x2,signature_x2_0) + +inst_13: +// rs1==x12, rs2==x14, rs3==x29, rd==x3,fs1 == 0 and fe1 == 0x1c and fm1 == 0x2f0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3b8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x12; op2:x14; op3:x29; dest:x3; op1val:0x72f0; op2val:0x7bb8; +op3val:0x7bff; valaddr_reg:x10; val_offset:3*FLEN/8; rmval:dyn; +testreg:x13; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x3, x12, x14, x29, dyn, 0, 0, x10, 3*FLEN/8, x16, x2, x13) + +inst_14: +// rs1==x15, rs2==x6, rs3==x7, rd==x4,fs1 == 0 and fe1 == 0x1e and fm1 == 0x102 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0d0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x15; op2:x6; op3:x7; dest:x4; op1val:0x7902; op2val:0x74d0; +op3val:0x7bff; valaddr_reg:x10; val_offset:6*FLEN/8; rmval:dyn; +testreg:x13; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x4, x15, x6, x7, dyn, 0, 0, x10, 6*FLEN/8, x16, x2, x13) + +inst_15: +// rs1==x5, rs2==x31, rs3==x15, rd==x17,fs1 == 0 and fe1 == 0x1d and fm1 == 0x22b and fs2 == 0 and fe2 == 0x1d and fm2 == 0x19c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x5; op2:x31; op3:x15; dest:x17; op1val:0x762b; op2val:0x759c; +op3val:0x7bff; valaddr_reg:x10; val_offset:9*FLEN/8; rmval:dyn; +testreg:x13; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x17, x5, x31, x15, dyn, 0, 0, x10, 9*FLEN/8, x16, x2, x13) + +inst_16: +// rs1==x29, rs2==x12, rs3==x23, rd==x27,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ab and fs2 == 0 and fe2 == 0x1e and fm2 == 0x33a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x29; op2:x12; op3:x23; dest:x27; op1val:0x78ab; op2val:0x7b3a; +op3val:0x7bff; valaddr_reg:x10; val_offset:12*FLEN/8; rmval:dyn; +testreg:x13; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x27, x29, x12, x23, dyn, 0, 0, x10, 12*FLEN/8, x16, x2, x13) + +inst_17: +// rs1==x20, rs2==x25, rs3==x0, rd==x22,fs1 == 0 and fe1 == 0x1e and fm1 == 0x36d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2d9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x20; op2:x25; op3:x0; dest:x22; op1val:0x7b6d; op2val:0x7ad9; +op3val:0x0; valaddr_reg:x10; val_offset:15*FLEN/8; rmval:dyn; +testreg:x13; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x22, x20, x25, x0, dyn, 0, 0, x10, 15*FLEN/8, x16, x2, x13) + +inst_18: +// rs1==x17, rs2==x8, rs3==x22, rd==x0,fs1 == 0 and fe1 == 0x1e and fm1 == 0x15e and fs2 == 0 and fe2 == 0x1c and fm2 == 0x137 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x17; op2:x8; op3:x22; dest:x0; op1val:0x795e; op2val:0x7137; +op3val:0x7bff; valaddr_reg:x10; val_offset:18*FLEN/8; rmval:dyn; +testreg:x13; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x0, x17, x8, x22, dyn, 0, 0, x10, 18*FLEN/8, x16, x2, x13) + +inst_19: +// rs1==x26, rs2==x1, rs3==x16, rd==x28,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x33b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x26; op2:x1; op3:x16; dest:x28; op1val:0x7bb6; op2val:0x7b3b; +op3val:0x7bff; valaddr_reg:x10; val_offset:21*FLEN/8; rmval:dyn; +testreg:x13; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x28, x26, x1, x16, dyn, 0, 0, x10, 21*FLEN/8, x16, x2, x13) + +inst_20: +// rs1==x7, rs2==x0, rs3==x21, rd==x5,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b5 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2c0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x7; op2:x0; op3:x21; dest:x5; op1val:0x79b5; op2val:0x0; +op3val:0x7bff; valaddr_reg:x10; val_offset:24*FLEN/8; rmval:dyn; +testreg:x13; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x5, x7, x0, x21, dyn, 0, 0, x10, 24*FLEN/8, x16, x2, x13) + +inst_21: +// rs1==x27, rs2==x9, rs3==x31, rd==x11,fs1 == 0 and fe1 == 0x1e and fm1 == 0x096 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x08e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x27; op2:x9; op3:x31; dest:x11; op1val:0x7896; op2val:0x748e; +op3val:0x7bff; valaddr_reg:x10; val_offset:27*FLEN/8; rmval:dyn; +testreg:x13; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x11, x27, x9, x31, dyn, 0, 0, x10, 27*FLEN/8, x16, x2, x13) +RVTEST_VALBASEUPD(x6,test_dataset_2) + +inst_22: +// rs1==x11, rs2==x29, rs3==x17, rd==x26,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ea and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x11; op2:x29; op3:x17; dest:x26; op1val:0x7ad4; op2val:0x7bea; +op3val:0x7bff; valaddr_reg:x6; val_offset:0*FLEN/8; rmval:dyn; +testreg:x13; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x26, x11, x29, x17, dyn, 0, 0, x6, 0*FLEN/8, x12, x2, x13) + +inst_23: +// rs1==x9, rs2==x27, rs3==x24, rd==x25,fs1 == 0 and fe1 == 0x1e and fm1 == 0x266 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x290 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x9; op2:x27; op3:x24; dest:x25; op1val:0x7a66; op2val:0x7690; +op3val:0x7bff; valaddr_reg:x6; val_offset:3*FLEN/8; rmval:dyn; +testreg:x13; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x25, x9, x27, x24, dyn, 0, 0, x6, 3*FLEN/8, x12, x2, x13) + +inst_24: +// rs1==x8, rs2==x10, rs3==x27, rd==x23,fs1 == 0 and fe1 == 0x1d and fm1 == 0x0b3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x225 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x8; op2:x10; op3:x27; dest:x23; op1val:0x74b3; op2val:0x7a25; +op3val:0x7bff; valaddr_reg:x6; val_offset:6*FLEN/8; rmval:dyn; +testreg:x13; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x23, x8, x10, x27, dyn, 0, 0, x6, 6*FLEN/8, x12, x2, x13) + +inst_25: +// rs1==x21, rs2==x30, rs3==x25, rd==x18,fs1 == 0 and fe1 == 0x1a and fm1 == 0x1a7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0e9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x21; op2:x30; op3:x25; dest:x18; op1val:0x69a7; op2val:0x78e9; +op3val:0x7bff; valaddr_reg:x6; val_offset:9*FLEN/8; rmval:dyn; +testreg:x13; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x18, x21, x30, x25, dyn, 0, 0, x6, 9*FLEN/8, x12, x2, x13) +RVTEST_SIGBASE(x4,signature_x4_0) + +inst_26: +// rs1==x28, rs2==x18, rs3==x6, rd==x9,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1be and fs2 == 0 and fe2 == 0x1d and fm2 == 0x14a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x28; op2:x18; op3:x6; dest:x9; op1val:0x79be; op2val:0x754a; +op3val:0x7bff; valaddr_reg:x6; val_offset:12*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x9, x28, x18, x6, dyn, 0, 0, x6, 12*FLEN/8, x12, x4, x5) + +inst_27: +// rs1==x3, rs2==x22, rs3==x2, rd==x1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x00a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x3; op2:x22; op3:x2; dest:x1; op1val:0x7bd7; op2val:0x780a; +op3val:0x7bff; valaddr_reg:x6; val_offset:15*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x1, x3, x22, x2, dyn, 0, 0, x6, 15*FLEN/8, x12, x4, x5) + +inst_28: +// rs1==x22, rs2==x7, rs3==x8, rd==x10,fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f3 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0ec and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x22; op2:x7; op3:x8; dest:x10; op1val:0x74f3; op2val:0x6cec; +op3val:0x7bff; valaddr_reg:x6; val_offset:18*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x10, x22, x7, x8, dyn, 0, 0, x6, 18*FLEN/8, x12, x4, x5) + +inst_29: +// rs1==x0, rs2==x28, rs3==x10, rd==x30,fs1 == 0 and fe1 == 0x1a and fm1 == 0x003 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x250 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x0; op2:x28; op3:x10; dest:x30; op1val:0x0; op2val:0x7250; +op3val:0x7bff; valaddr_reg:x6; val_offset:21*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x30, x0, x28, x10, dyn, 0, 0, x6, 21*FLEN/8, x12, x4, x5) + +inst_30: +// rs1==x30, rs2==x17, rs3==x11, rd==x2,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e1 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x17; op3:x11; dest:x2; op1val:0x78e1; op2val:0x70fe; +op3val:0x7bff; valaddr_reg:x6; val_offset:24*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x2, x30, x17, x11, dyn, 0, 0, x6, 24*FLEN/8, x12, x4, x5) + +inst_31: +// rs1==x31, rs2==x16, rs3==x18, rd==x21,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f0 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x104 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x31; op2:x16; op3:x18; dest:x21; op1val:0x7af0; op2val:0x7504; +op3val:0x7bff; valaddr_reg:x6; val_offset:27*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x21, x31, x16, x18, dyn, 0, 0, x6, 27*FLEN/8, x12, x4, x5) +RVTEST_VALBASEUPD(x1,test_dataset_3) + +inst_32: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32b and fs2 == 0 and fe2 == 0x1d and fm2 == 0x20a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b2b; op2val:0x760a; +op3val:0x7bff; valaddr_reg:x1; val_offset:0*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 0*FLEN/8, x2, x4, x5) + +inst_33: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x028 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x126 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7828; op2val:0x7926; +op3val:0x7bff; valaddr_reg:x1; val_offset:3*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3*FLEN/8, x2, x4, x5) + +inst_34: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x078 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0f5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7878; op2val:0x78f5; +op3val:0x7bff; valaddr_reg:x1; val_offset:6*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 6*FLEN/8, x2, x4, x5) + +inst_35: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00d and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2e5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x780d; op2val:0x76e5; +op3val:0x7bff; valaddr_reg:x1; val_offset:9*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 9*FLEN/8, x2, x4, x5) + +inst_36: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x399 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0d0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7399; op2val:0x74d0; +op3val:0x7bff; valaddr_reg:x1; val_offset:12*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 12*FLEN/8, x2, x4, x5) + +inst_37: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x062 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x782a; op2val:0x7862; +op3val:0x7bff; valaddr_reg:x1; val_offset:15*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 15*FLEN/8, x2, x4, x5) + +inst_38: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0a3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76a3; op2val:0x78a3; +op3val:0x7bff; valaddr_reg:x1; val_offset:18*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 18*FLEN/8, x2, x4, x5) + +inst_39: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ec and fs2 == 0 and fe2 == 0x1e and fm2 == 0x10e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78ec; op2val:0x790e; +op3val:0x7bff; valaddr_reg:x1; val_offset:21*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 21*FLEN/8, x2, x4, x5) + +inst_40: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x104 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x374 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7904; op2val:0x7774; +op3val:0x7bff; valaddr_reg:x1; val_offset:24*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 24*FLEN/8, x2, x4, x5) + +inst_41: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1a7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75a3; op2val:0x79a7; +op3val:0x7bff; valaddr_reg:x1; val_offset:27*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 27*FLEN/8, x2, x4, x5) + +inst_42: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x1ad and fs2 == 0 and fe2 == 0x1a and fm2 == 0x3c0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x65ad; op2val:0x6bc0; +op3val:0x7bff; valaddr_reg:x1; val_offset:30*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 30*FLEN/8, x2, x4, x5) + +inst_43: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b3 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x004 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bb3; op2val:0x7404; +op3val:0x7bff; valaddr_reg:x1; val_offset:33*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 33*FLEN/8, x2, x4, x5) + +inst_44: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0bd and fs2 == 0 and fe2 == 0x1d and fm2 == 0x11e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78bd; op2val:0x751e; +op3val:0x7bff; valaddr_reg:x1; val_offset:36*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 36*FLEN/8, x2, x4, x5) + +inst_45: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x100 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1e7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7500; op2val:0x75e7; +op3val:0x7bff; valaddr_reg:x1; val_offset:39*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 39*FLEN/8, x2, x4, x5) + +inst_46: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0cd and fs2 == 0 and fe2 == 0x1d and fm2 == 0x208 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74cd; op2val:0x7608; +op3val:0x7bff; valaddr_reg:x1; val_offset:42*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 42*FLEN/8, x2, x4, x5) + +inst_47: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x08d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x66e3; op2val:0x788d; +op3val:0x7bff; valaddr_reg:x1; val_offset:45*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 45*FLEN/8, x2, x4, x5) + +inst_48: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f5 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x31e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74f5; op2val:0x731e; +op3val:0x7bff; valaddr_reg:x1; val_offset:48*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 48*FLEN/8, x2, x4, x5) + +inst_49: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3a2 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73a2; op2val:0x71fe; +op3val:0x7bff; valaddr_reg:x1; val_offset:51*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 51*FLEN/8, x2, x4, x5) + +inst_50: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x194 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x283 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7994; op2val:0x6e83; +op3val:0x7bff; valaddr_reg:x1; val_offset:54*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 54*FLEN/8, x2, x4, x5) + +inst_51: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x156 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2aa and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7556; op2val:0x7aaa; +op3val:0x7bff; valaddr_reg:x1; val_offset:57*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 57*FLEN/8, x2, x4, x5) + +inst_52: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d7 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x16a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ad7; op2val:0x716a; +op3val:0x7bff; valaddr_reg:x1; val_offset:60*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 60*FLEN/8, x2, x4, x5) + +inst_53: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x133 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x313 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7933; op2val:0x7b13; +op3val:0x7bff; valaddr_reg:x1; val_offset:63*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 63*FLEN/8, x2, x4, x5) + +inst_54: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x332 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3bc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7332; op2val:0x6fbc; +op3val:0x7bff; valaddr_reg:x1; val_offset:66*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 66*FLEN/8, x2, x4, x5) + +inst_55: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x21a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x273 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x721a; op2val:0x7a73; +op3val:0x7bff; valaddr_reg:x1; val_offset:69*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 69*FLEN/8, x2, x4, x5) + +inst_56: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1df and fs2 == 0 and fe2 == 0x1d and fm2 == 0x074 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71df; op2val:0x7474; +op3val:0x7bff; valaddr_reg:x1; val_offset:72*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 72*FLEN/8, x2, x4, x5) + +inst_57: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x122 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x272 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7922; op2val:0x7a72; +op3val:0x7bff; valaddr_reg:x1; val_offset:75*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 75*FLEN/8, x2, x4, x5) + +inst_58: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x025 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0ab and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7025; op2val:0x74ab; +op3val:0x7bff; valaddr_reg:x1; val_offset:78*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 78*FLEN/8, x2, x4, x5) + +inst_59: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x056 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x189 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7456; op2val:0x7589; +op3val:0x7bff; valaddr_reg:x1; val_offset:81*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 81*FLEN/8, x2, x4, x5) + +inst_60: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2b6 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x28c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76b6; op2val:0x768c; +op3val:0x7bff; valaddr_reg:x1; val_offset:84*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 84*FLEN/8, x2, x4, x5) + +inst_61: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0fd and fs2 == 0 and fe2 == 0x17 and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70fd; op2val:0x5cc5; +op3val:0x7bff; valaddr_reg:x1; val_offset:87*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 87*FLEN/8, x2, x4, x5) + +inst_62: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x309 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3e4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b09; op2val:0x7be4; +op3val:0x7bff; valaddr_reg:x1; val_offset:90*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 90*FLEN/8, x2, x4, x5) + +inst_63: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x398 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x36a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b98; op2val:0x7b6a; +op3val:0x7bff; valaddr_reg:x1; val_offset:93*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 93*FLEN/8, x2, x4, x5) + +inst_64: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f6; op2val:0x7ab0; +op3val:0x7bff; valaddr_reg:x1; val_offset:96*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 96*FLEN/8, x2, x4, x5) + +inst_65: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x026 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x09f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7826; op2val:0x749f; +op3val:0x7bff; valaddr_reg:x1; val_offset:99*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 99*FLEN/8, x2, x4, x5) + +inst_66: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x346 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x05a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7346; op2val:0x6c5a; +op3val:0x7bff; valaddr_reg:x1; val_offset:102*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 102*FLEN/8, x2, x4, x5) + +inst_67: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x097 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x27a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7497; op2val:0x7a7a; +op3val:0x7bff; valaddr_reg:x1; val_offset:105*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 105*FLEN/8, x2, x4, x5) + +inst_68: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x339 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x18c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b39; op2val:0x798c; +op3val:0x7bff; valaddr_reg:x1; val_offset:108*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 108*FLEN/8, x2, x4, x5) + +inst_69: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x331 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b2b; op2val:0x7b31; +op3val:0x7bff; valaddr_reg:x1; val_offset:111*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 111*FLEN/8, x2, x4, x5) + +inst_70: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x2ba and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1f5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x62ba; op2val:0x79f5; +op3val:0x7bff; valaddr_reg:x1; val_offset:114*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 114*FLEN/8, x2, x4, x5) + +inst_71: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0cb and fs2 == 0 and fe2 == 0x1e and fm2 == 0x14c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74cb; op2val:0x794c; +op3val:0x7bff; valaddr_reg:x1; val_offset:117*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 117*FLEN/8, x2, x4, x5) + +inst_72: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x29d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x382 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x769d; op2val:0x7b82; +op3val:0x7bff; valaddr_reg:x1; val_offset:120*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 120*FLEN/8, x2, x4, x5) + +inst_73: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x175 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x009 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7575; op2val:0x7409; +op3val:0x7bff; valaddr_reg:x1; val_offset:123*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 123*FLEN/8, x2, x4, x5) + +inst_74: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x241 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77a1; op2val:0x7a41; +op3val:0x7bff; valaddr_reg:x1; val_offset:126*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 126*FLEN/8, x2, x4, x5) + +inst_75: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x24f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x046 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x724f; op2val:0x7846; +op3val:0x7bff; valaddr_reg:x1; val_offset:129*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 129*FLEN/8, x2, x4, x5) + +inst_76: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x17a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x254 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x717a; op2val:0x7a54; +op3val:0x7bff; valaddr_reg:x1; val_offset:132*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 132*FLEN/8, x2, x4, x5) + +inst_77: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x271 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x295 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a71; op2val:0x7a95; +op3val:0x7bff; valaddr_reg:x1; val_offset:135*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 135*FLEN/8, x2, x4, x5) + +inst_78: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x106 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2e5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7906; op2val:0x7ae5; +op3val:0x7bff; valaddr_reg:x1; val_offset:138*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 138*FLEN/8, x2, x4, x5) + +inst_79: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x057 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x04b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7457; op2val:0x744b; +op3val:0x7bff; valaddr_reg:x1; val_offset:141*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 141*FLEN/8, x2, x4, x5) + +inst_80: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2c3 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x390 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76c3; op2val:0x7790; +op3val:0x7bff; valaddr_reg:x1; val_offset:144*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 144*FLEN/8, x2, x4, x5) + +inst_81: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x367 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x303 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5767; op2val:0x6b03; +op3val:0x7bff; valaddr_reg:x1; val_offset:147*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 147*FLEN/8, x2, x4, x5) + +inst_82: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x060 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ff8; op2val:0x6c60; +op3val:0x7bff; valaddr_reg:x1; val_offset:150*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 150*FLEN/8, x2, x4, x5) + +inst_83: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d5 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x182 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ad5; op2val:0x6d82; +op3val:0x7bff; valaddr_reg:x1; val_offset:153*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 153*FLEN/8, x2, x4, x5) + +inst_84: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x10d and fs2 == 0 and fe2 == 0x1d and fm2 == 0x107 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x750d; op2val:0x7507; +op3val:0x7bff; valaddr_reg:x1; val_offset:156*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 156*FLEN/8, x2, x4, x5) + +inst_85: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0b0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x792c; op2val:0x78b0; +op3val:0x7bff; valaddr_reg:x1; val_offset:159*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 159*FLEN/8, x2, x4, x5) + +inst_86: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x21c and fs2 == 0 and fe2 == 0x1d and fm2 == 0x142 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x721c; op2val:0x7542; +op3val:0x7bff; valaddr_reg:x1; val_offset:162*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 162*FLEN/8, x2, x4, x5) + +inst_87: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x071 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1b9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7871; op2val:0x79b9; +op3val:0x7bff; valaddr_reg:x1; val_offset:165*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 165*FLEN/8, x2, x4, x5) + +inst_88: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x11c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1b6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d1c; op2val:0x71b6; +op3val:0x7bff; valaddr_reg:x1; val_offset:168*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 168*FLEN/8, x2, x4, x5) + +inst_89: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x242 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78d5; op2val:0x7a42; +op3val:0x7bff; valaddr_reg:x1; val_offset:171*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 171*FLEN/8, x2, x4, x5) + +inst_90: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x267 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0fb and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a67; op2val:0x78fb; +op3val:0x7bff; valaddr_reg:x1; val_offset:174*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 174*FLEN/8, x2, x4, x5) + +inst_91: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1f4 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3ef and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75f4; op2val:0x77ef; +op3val:0x7bff; valaddr_reg:x1; val_offset:177*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 177*FLEN/8, x2, x4, x5) + +inst_92: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2b9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x18c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76b9; op2val:0x798c; +op3val:0x7bff; valaddr_reg:x1; val_offset:180*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 180*FLEN/8, x2, x4, x5) + +inst_93: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x048 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73d6; op2val:0x7848; +op3val:0x7bff; valaddr_reg:x1; val_offset:183*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 183*FLEN/8, x2, x4, x5) + +inst_94: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x094 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2cb and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c94; op2val:0x76cb; +op3val:0x7bff; valaddr_reg:x1; val_offset:186*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 186*FLEN/8, x2, x4, x5) + +inst_95: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x308 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x37c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b08; op2val:0x7b7c; +op3val:0x7bff; valaddr_reg:x1; val_offset:189*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 189*FLEN/8, x2, x4, x5) + +inst_96: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x253 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b2d; op2val:0x7a53; +op3val:0x7bff; valaddr_reg:x1; val_offset:192*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 192*FLEN/8, x2, x4, x5) + +inst_97: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x36c and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3e0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x776c; op2val:0x6fe0; +op3val:0x7bff; valaddr_reg:x1; val_offset:195*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 195*FLEN/8, x2, x4, x5) + +inst_98: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x14b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x318 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x794b; op2val:0x7b18; +op3val:0x7bff; valaddr_reg:x1; val_offset:198*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 198*FLEN/8, x2, x4, x5) + +inst_99: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x156 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1dd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7956; op2val:0x79dd; +op3val:0x7bff; valaddr_reg:x1; val_offset:201*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 201*FLEN/8, x2, x4, x5) + +inst_100: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x298 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0b3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e98; op2val:0x78b3; +op3val:0x7bff; valaddr_reg:x1; val_offset:204*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 204*FLEN/8, x2, x4, x5) + +inst_101: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x097 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x231 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7097; op2val:0x7a31; +op3val:0x7bff; valaddr_reg:x1; val_offset:207*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 207*FLEN/8, x2, x4, x5) + +inst_102: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1df and fs2 == 0 and fe2 == 0x1b and fm2 == 0x25a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ddf; op2val:0x6e5a; +op3val:0x7bff; valaddr_reg:x1; val_offset:210*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 210*FLEN/8, x2, x4, x5) + +inst_103: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1ba and fs2 == 0 and fe2 == 0x19 and fm2 == 0x202 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71ba; op2val:0x6602; +op3val:0x7bff; valaddr_reg:x1; val_offset:213*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 213*FLEN/8, x2, x4, x5) + +inst_104: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3c2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2bf and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6fc2; op2val:0x7abf; +op3val:0x7bff; valaddr_reg:x1; val_offset:216*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 216*FLEN/8, x2, x4, x5) + +inst_105: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2af and fs2 == 0 and fe2 == 0x1e and fm2 == 0x39d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aaf; op2val:0x7b9d; +op3val:0x7bff; valaddr_reg:x1; val_offset:219*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 219*FLEN/8, x2, x4, x5) + +inst_106: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x263 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x0a3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a63; op2val:0x68a3; +op3val:0x7bff; valaddr_reg:x1; val_offset:222*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 222*FLEN/8, x2, x4, x5) + +inst_107: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x016 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1b7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7816; op2val:0x79b7; +op3val:0x7bff; valaddr_reg:x1; val_offset:225*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 225*FLEN/8, x2, x4, x5) + +inst_108: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1fd and fs2 == 0 and fe2 == 0x1e and fm2 == 0x379 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79fd; op2val:0x7b79; +op3val:0x7bff; valaddr_reg:x1; val_offset:228*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 228*FLEN/8, x2, x4, x5) + +inst_109: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x12f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x082 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x752f; op2val:0x7882; +op3val:0x7bff; valaddr_reg:x1; val_offset:231*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 231*FLEN/8, x2, x4, x5) + +inst_110: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3be and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1bf and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73be; op2val:0x71bf; +op3val:0x7bff; valaddr_reg:x1; val_offset:234*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 234*FLEN/8, x2, x4, x5) + +inst_111: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ec and fs2 == 0 and fe2 == 0x1e and fm2 == 0x206 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78ec; op2val:0x7a06; +op3val:0x7bff; valaddr_reg:x1; val_offset:237*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 237*FLEN/8, x2, x4, x5) + +inst_112: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1e0 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x257 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75e0; op2val:0x7657; +op3val:0x7bff; valaddr_reg:x1; val_offset:240*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 240*FLEN/8, x2, x4, x5) + +inst_113: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x153 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76b0; op2val:0x6d53; +op3val:0x7bff; valaddr_reg:x1; val_offset:243*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 243*FLEN/8, x2, x4, x5) + +inst_114: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c7 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x29a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bc7; op2val:0x769a; +op3val:0x7bff; valaddr_reg:x1; val_offset:246*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 246*FLEN/8, x2, x4, x5) + +inst_115: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x123 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x186 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7123; op2val:0x7986; +op3val:0x7bff; valaddr_reg:x1; val_offset:249*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 249*FLEN/8, x2, x4, x5) + +inst_116: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x163 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x022 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7963; op2val:0x7822; +op3val:0x7bff; valaddr_reg:x1; val_offset:252*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 252*FLEN/8, x2, x4, x5) + +inst_117: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x124 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x32c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7924; op2val:0x7b2c; +op3val:0x7bff; valaddr_reg:x1; val_offset:255*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 255*FLEN/8, x2, x4, x5) + +inst_118: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x221 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1fb and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e21; op2val:0x79fb; +op3val:0x7bff; valaddr_reg:x1; val_offset:258*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 258*FLEN/8, x2, x4, x5) + +inst_119: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x022 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x315 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7822; op2val:0x7715; +op3val:0x7bff; valaddr_reg:x1; val_offset:261*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 261*FLEN/8, x2, x4, x5) + +inst_120: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1f3 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x046 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71f3; op2val:0x7446; +op3val:0x7bff; valaddr_reg:x1; val_offset:264*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 264*FLEN/8, x2, x4, x5) + +inst_121: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ae and fs2 == 0 and fe2 == 0x1d and fm2 == 0x108 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78ae; op2val:0x7508; +op3val:0x7bff; valaddr_reg:x1; val_offset:267*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 267*FLEN/8, x2, x4, x5) + +inst_122: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x186 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x39f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7986; op2val:0x7b9f; +op3val:0x7bff; valaddr_reg:x1; val_offset:270*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 270*FLEN/8, x2, x4, x5) + +inst_123: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a3 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x29b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79a3; op2val:0x769b; +op3val:0x7bff; valaddr_reg:x1; val_offset:273*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 273*FLEN/8, x2, x4, x5) + +inst_124: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ac and fs2 == 0 and fe2 == 0x1d and fm2 == 0x045 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78ac; op2val:0x7445; +op3val:0x7bff; valaddr_reg:x1; val_offset:276*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 276*FLEN/8, x2, x4, x5) + +inst_125: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x1ea and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3ab and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x65ea; op2val:0x77ab; +op3val:0x7bff; valaddr_reg:x1; val_offset:279*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 279*FLEN/8, x2, x4, x5) + +inst_126: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x182 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1c3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7182; op2val:0x75c3; +op3val:0x7bff; valaddr_reg:x1; val_offset:282*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 282*FLEN/8, x2, x4, x5) + +inst_127: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x230 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x097 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a30; op2val:0x7097; +op3val:0x7bff; valaddr_reg:x1; val_offset:285*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 285*FLEN/8, x2, x4, x5) + +inst_128: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ab and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0ca and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77ab; op2val:0x78ca; +op3val:0x7bff; valaddr_reg:x1; val_offset:288*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 288*FLEN/8, x2, x4, x5) + +inst_129: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ac and fs2 == 0 and fe2 == 0x1e and fm2 == 0x291 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aac; op2val:0x7a91; +op3val:0x7bff; valaddr_reg:x1; val_offset:291*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 291*FLEN/8, x2, x4, x5) + +inst_130: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3b2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1c3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77b2; op2val:0x79c3; +op3val:0x7bff; valaddr_reg:x1; val_offset:294*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 294*FLEN/8, x2, x4, x5) + +inst_131: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x266 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1dd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7666; op2val:0x79dd; +op3val:0x7bff; valaddr_reg:x1; val_offset:297*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 297*FLEN/8, x2, x4, x5) + +inst_132: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x379 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x357 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7779; op2val:0x7357; +op3val:0x7bff; valaddr_reg:x1; val_offset:300*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 300*FLEN/8, x2, x4, x5) + +inst_133: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1bd and fs2 == 0 and fe2 == 0x1e and fm2 == 0x166 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79bd; op2val:0x7966; +op3val:0x7bff; valaddr_reg:x1; val_offset:303*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 303*FLEN/8, x2, x4, x5) + +inst_134: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d3 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3be and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ad3; op2val:0x73be; +op3val:0x7bff; valaddr_reg:x1; val_offset:306*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 306*FLEN/8, x2, x4, x5) + +inst_135: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x022 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1fc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7422; op2val:0x71fc; +op3val:0x7bff; valaddr_reg:x1; val_offset:309*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 309*FLEN/8, x2, x4, x5) + +inst_136: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2dd and fs2 == 0 and fe2 == 0x1e and fm2 == 0x331 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7add; op2val:0x7b31; +op3val:0x7bff; valaddr_reg:x1; val_offset:312*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 312*FLEN/8, x2, x4, x5) + +inst_137: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ea and fs2 == 0 and fe2 == 0x1d and fm2 == 0x103 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aea; op2val:0x7503; +op3val:0x7bff; valaddr_reg:x1; val_offset:315*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 315*FLEN/8, x2, x4, x5) + +inst_138: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d4 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x17f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79d4; op2val:0x6d7f; +op3val:0x7bff; valaddr_reg:x1; val_offset:318*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 318*FLEN/8, x2, x4, x5) + +inst_139: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ab and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0aa and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aab; op2val:0x74aa; +op3val:0x7bff; valaddr_reg:x1; val_offset:321*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 321*FLEN/8, x2, x4, x5) + +inst_140: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x166 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78a3; op2val:0x7966; +op3val:0x7bff; valaddr_reg:x1; val_offset:324*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 324*FLEN/8, x2, x4, x5) + +inst_141: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x15a and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2f9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x755a; op2val:0x76f9; +op3val:0x7bff; valaddr_reg:x1; val_offset:327*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 327*FLEN/8, x2, x4, x5) + +inst_142: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2b8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0ad and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72b8; op2val:0x78ad; +op3val:0x7bff; valaddr_reg:x1; val_offset:330*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 330*FLEN/8, x2, x4, x5) + +inst_143: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x240 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x05a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7640; op2val:0x785a; +op3val:0x7bff; valaddr_reg:x1; val_offset:333*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 333*FLEN/8, x2, x4, x5) + +inst_144: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x064 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x152 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7464; op2val:0x7952; +op3val:0x7bff; valaddr_reg:x1; val_offset:336*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 336*FLEN/8, x2, x4, x5) + +inst_145: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x318 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x344 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b18; op2val:0x7b44; +op3val:0x7bff; valaddr_reg:x1; val_offset:339*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 339*FLEN/8, x2, x4, x5) + +inst_146: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x386 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1fc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b86; op2val:0x75fc; +op3val:0x7bff; valaddr_reg:x1; val_offset:342*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 342*FLEN/8, x2, x4, x5) + +inst_147: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0b9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a0e; op2val:0x74b9; +op3val:0x7bff; valaddr_reg:x1; val_offset:345*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 345*FLEN/8, x2, x4, x5) + +inst_148: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x13a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x271 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x793a; op2val:0x7a71; +op3val:0x7bff; valaddr_reg:x1; val_offset:348*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 348*FLEN/8, x2, x4, x5) + +inst_149: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x207 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3af and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a07; op2val:0x7baf; +op3val:0x7bff; valaddr_reg:x1; val_offset:351*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 351*FLEN/8, x2, x4, x5) + +inst_150: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x049 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x33f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7849; op2val:0x6f3f; +op3val:0x7bff; valaddr_reg:x1; val_offset:354*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 354*FLEN/8, x2, x4, x5) + +inst_151: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1bd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75a1; op2val:0x79bd; +op3val:0x7bff; valaddr_reg:x1; val_offset:357*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 357*FLEN/8, x2, x4, x5) + +inst_152: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x087 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1d2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7887; op2val:0x71d2; +op3val:0x7bff; valaddr_reg:x1; val_offset:360*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 360*FLEN/8, x2, x4, x5) + +inst_153: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x10b and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1ba and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x790b; op2val:0x71ba; +op3val:0x7bff; valaddr_reg:x1; val_offset:363*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 363*FLEN/8, x2, x4, x5) +RVTEST_SIGBASE(x4,signature_x4_1) + +inst_154: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x13d and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3e0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x793d; op2val:0x6fe0; +op3val:0x7bff; valaddr_reg:x1; val_offset:366*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 366*FLEN/8, x2, x4, x5) + +inst_155: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x085 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x14d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7085; op2val:0x754d; +op3val:0x7bff; valaddr_reg:x1; val_offset:369*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 369*FLEN/8, x2, x4, x5) + +inst_156: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x06f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78c6; op2val:0x786f; +op3val:0x7bff; valaddr_reg:x1; val_offset:372*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 372*FLEN/8, x2, x4, x5) + +inst_157: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x351 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7751; op2val:0x74ff; +op3val:0x7bff; valaddr_reg:x1; val_offset:375*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 375*FLEN/8, x2, x4, x5) + +inst_158: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x063 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1b9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c63; op2val:0x79b9; +op3val:0x7bff; valaddr_reg:x1; val_offset:378*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 378*FLEN/8, x2, x4, x5) + +inst_159: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x057 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1ea and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7857; op2val:0x79ea; +op3val:0x7bff; valaddr_reg:x1; val_offset:381*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 381*FLEN/8, x2, x4, x5) + +inst_160: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x040 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x221 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7440; op2val:0x7621; +op3val:0x7bff; valaddr_reg:x1; val_offset:384*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 384*FLEN/8, x2, x4, x5) + +inst_161: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x163 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x009 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6963; op2val:0x7809; +op3val:0x7bff; valaddr_reg:x1; val_offset:387*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 387*FLEN/8, x2, x4, x5) + +inst_162: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x225 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1a9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a25; op2val:0x75a9; +op3val:0x7bff; valaddr_reg:x1; val_offset:390*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 390*FLEN/8, x2, x4, x5) + +inst_163: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x273 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x054 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7673; op2val:0x7854; +op3val:0x7bff; valaddr_reg:x1; val_offset:393*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 393*FLEN/8, x2, x4, x5) + +inst_164: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75a4; op2val:0x7ac5; +op3val:0x7bff; valaddr_reg:x1; val_offset:396*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 396*FLEN/8, x2, x4, x5) + +inst_165: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x053 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x25f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7453; op2val:0x6e5f; +op3val:0x7bff; valaddr_reg:x1; val_offset:399*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 399*FLEN/8, x2, x4, x5) + +inst_166: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x23a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1d0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a3a; op2val:0x79d0; +op3val:0x7bff; valaddr_reg:x1; val_offset:402*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 402*FLEN/8, x2, x4, x5) + +inst_167: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x20c and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2a9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x720c; op2val:0x76a9; +op3val:0x7bff; valaddr_reg:x1; val_offset:405*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 405*FLEN/8, x2, x4, x5) + +inst_168: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x285 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1fc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a85; op2val:0x79fc; +op3val:0x7bff; valaddr_reg:x1; val_offset:408*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 408*FLEN/8, x2, x4, x5) + +inst_169: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0af and fs2 == 0 and fe2 == 0x1d and fm2 == 0x25f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70af; op2val:0x765f; +op3val:0x7bff; valaddr_reg:x1; val_offset:411*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 411*FLEN/8, x2, x4, x5) + +inst_170: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x037 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x08b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7837; op2val:0x788b; +op3val:0x7bff; valaddr_reg:x1; val_offset:414*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 414*FLEN/8, x2, x4, x5) + +inst_171: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x240 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7400; op2val:0x7a40; +op3val:0x7bff; valaddr_reg:x1; val_offset:417*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 417*FLEN/8, x2, x4, x5) + +inst_172: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x320 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a6c; op2val:0x7b20; +op3val:0x7bff; valaddr_reg:x1; val_offset:420*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 420*FLEN/8, x2, x4, x5) + +inst_173: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x220 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x06b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7620; op2val:0x786b; +op3val:0x7bff; valaddr_reg:x1; val_offset:423*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 423*FLEN/8, x2, x4, x5) + +inst_174: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x111 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3cf and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7911; op2val:0x7bcf; +op3val:0x7bff; valaddr_reg:x1; val_offset:426*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 426*FLEN/8, x2, x4, x5) + +inst_175: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0c9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2e0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74c9; op2val:0x7ae0; +op3val:0x7bff; valaddr_reg:x1; val_offset:429*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 429*FLEN/8, x2, x4, x5) + +inst_176: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ce and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1cf and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78ce; op2val:0x79cf; +op3val:0x7bff; valaddr_reg:x1; val_offset:432*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 432*FLEN/8, x2, x4, x5) + +inst_177: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x229 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x14a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a29; op2val:0x794a; +op3val:0x7bff; valaddr_reg:x1; val_offset:435*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 435*FLEN/8, x2, x4, x5) + +inst_178: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 0 and fe2 == 0x1d and fm2 == 0x35d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x782f; op2val:0x775d; +op3val:0x7bff; valaddr_reg:x1; val_offset:438*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 438*FLEN/8, x2, x4, x5) + +inst_179: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x03b and fs2 == 0 and fe2 == 0x1a and fm2 == 0x0bd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x783b; op2val:0x68bd; +op3val:0x7bff; valaddr_reg:x1; val_offset:441*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 441*FLEN/8, x2, x4, x5) + +inst_180: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12a and fs2 == 0 and fe2 == 0x1d and fm2 == 0x31a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x792a; op2val:0x771a; +op3val:0x7bff; valaddr_reg:x1; val_offset:444*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 444*FLEN/8, x2, x4, x5) + +inst_181: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ab and fs2 == 0 and fe2 == 0x1e and fm2 == 0x322 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bab; op2val:0x7b22; +op3val:0x7bff; valaddr_reg:x1; val_offset:447*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 447*FLEN/8, x2, x4, x5) + +inst_182: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0fb and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a55; op2val:0x78fb; +op3val:0x7bff; valaddr_reg:x1; val_offset:450*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 450*FLEN/8, x2, x4, x5) + +inst_183: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c1 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x377 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c1; op2val:0x7377; +op3val:0x7bff; valaddr_reg:x1; val_offset:453*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 453*FLEN/8, x2, x4, x5) + +inst_184: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x36f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x784f; op2val:0x7b6f; +op3val:0x7bff; valaddr_reg:x1; val_offset:456*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 456*FLEN/8, x2, x4, x5) + +inst_185: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x18d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7af5; op2val:0x798d; +op3val:0x7bff; valaddr_reg:x1; val_offset:459*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 459*FLEN/8, x2, x4, x5) + +inst_186: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2dc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0ce and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7adc; op2val:0x78ce; +op3val:0x7bff; valaddr_reg:x1; val_offset:462*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 462*FLEN/8, x2, x4, x5) + +inst_187: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1ea and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79b9; op2val:0x79ea; +op3val:0x7bff; valaddr_reg:x1; val_offset:465*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 465*FLEN/8, x2, x4, x5) + +inst_188: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x273 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x373 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a73; op2val:0x7b73; +op3val:0x7bff; valaddr_reg:x1; val_offset:468*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 468*FLEN/8, x2, x4, x5) + +inst_189: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2fd and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76fd; op2val:0x7a0d; +op3val:0x7bff; valaddr_reg:x1; val_offset:471*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 471*FLEN/8, x2, x4, x5) + +inst_190: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2fa and fs2 == 0 and fe2 == 0x1a and fm2 == 0x176 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6efa; op2val:0x6976; +op3val:0x7bff; valaddr_reg:x1; val_offset:474*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 474*FLEN/8, x2, x4, x5) + +inst_191: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x268 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x124 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7268; op2val:0x7124; +op3val:0x7bff; valaddr_reg:x1; val_offset:477*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 477*FLEN/8, x2, x4, x5) + +inst_192: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x197 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x04c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7997; op2val:0x784c; +op3val:0x7bff; valaddr_reg:x1; val_offset:480*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 480*FLEN/8, x2, x4, x5) + +inst_193: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x130 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0df and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7930; op2val:0x74df; +op3val:0x7bff; valaddr_reg:x1; val_offset:483*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 483*FLEN/8, x2, x4, x5) + +inst_194: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20d and fs2 == 0 and fe2 == 0x1d and fm2 == 0x26b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a0d; op2val:0x766b; +op3val:0x7bff; valaddr_reg:x1; val_offset:486*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 486*FLEN/8, x2, x4, x5) + +inst_195: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x331 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1c1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b31; op2val:0x79c1; +op3val:0x7bff; valaddr_reg:x1; val_offset:489*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 489*FLEN/8, x2, x4, x5) + +inst_196: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ee and fs2 == 0 and fe2 == 0x1e and fm2 == 0x03b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75ee; op2val:0x783b; +op3val:0x7bff; valaddr_reg:x1; val_offset:492*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 492*FLEN/8, x2, x4, x5) + +inst_197: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x328 and fs2 == 0 and fe2 == 0x16 and fm2 == 0x187 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7328; op2val:0x5987; +op3val:0x7bff; valaddr_reg:x1; val_offset:495*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 495*FLEN/8, x2, x4, x5) + +inst_198: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x243 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x096 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a43; op2val:0x7096; +op3val:0x7bff; valaddr_reg:x1; val_offset:498*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 498*FLEN/8, x2, x4, x5) + +inst_199: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x23f and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2b1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x723f; op2val:0x72b1; +op3val:0x7bff; valaddr_reg:x1; val_offset:501*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 501*FLEN/8, x2, x4, x5) + +inst_200: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x05a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x739c; op2val:0x785a; +op3val:0x7bff; valaddr_reg:x1; val_offset:504*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 504*FLEN/8, x2, x4, x5) + +inst_201: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x37e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3f6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x737e; op2val:0x7bf6; +op3val:0x7bff; valaddr_reg:x1; val_offset:507*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 507*FLEN/8, x2, x4, x5) + +inst_202: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x39e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ab0; op2val:0x779e; +op3val:0x7bff; valaddr_reg:x1; val_offset:510*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 510*FLEN/8, x2, x4, x5) + +inst_203: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1ed and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x782e; op2val:0x79ed; +op3val:0x7bff; valaddr_reg:x1; val_offset:513*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 513*FLEN/8, x2, x4, x5) + +inst_204: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x018 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x210 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c18; op2val:0x7a10; +op3val:0x7bff; valaddr_reg:x1; val_offset:516*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 516*FLEN/8, x2, x4, x5) + +inst_205: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d1 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x3ef and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74d1; op2val:0x67ef; +op3val:0x7bff; valaddr_reg:x1; val_offset:519*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 519*FLEN/8, x2, x4, x5) + +inst_206: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x38f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1bf and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x778f; op2val:0x79bf; +op3val:0x7bff; valaddr_reg:x1; val_offset:522*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 522*FLEN/8, x2, x4, x5) + +inst_207: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x267 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x31c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a67; op2val:0x771c; +op3val:0x7bff; valaddr_reg:x1; val_offset:525*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 525*FLEN/8, x2, x4, x5) + +inst_208: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x36d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2d9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b6d; op2val:0x7ad9; +op3val:0x7bff; valaddr_reg:x1; val_offset:528*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 528*FLEN/8, x2, x4, x5) + +inst_209: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15e and fs2 == 0 and fe2 == 0x1c and fm2 == 0x137 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x795e; op2val:0x7137; +op3val:0x7bff; valaddr_reg:x1; val_offset:531*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 531*FLEN/8, x2, x4, x5) + +inst_210: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b5 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2c0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79b5; op2val:0x72c0; +op3val:0x7bff; valaddr_reg:x1; val_offset:534*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 534*FLEN/8, x2, x4, x5) + +inst_211: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x003 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x250 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6803; op2val:0x7250; +op3val:0x7bff; valaddr_reg:x1; val_offset:537*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 537*FLEN/8, x2, x4, x5) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(30932,32,FLEN) +NAN_BOXED(30976,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(25277,32,FLEN) +NAN_BOXED(31410,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(29566,32,FLEN) +NAN_BOXED(31734,32,FLEN) +NAN_BOXED(29566,32,FLEN) +NAN_BOXED(31408,32,FLEN) +NAN_BOXED(31408,32,FLEN) +NAN_BOXED(31408,32,FLEN) +NAN_BOXED(28881,32,FLEN) +NAN_BOXED(30995,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(30766,32,FLEN) +NAN_BOXED(31213,32,FLEN) +NAN_BOXED(31213,32,FLEN) +NAN_BOXED(27672,32,FLEN) +NAN_BOXED(31248,32,FLEN) +NAN_BOXED(27672,32,FLEN) +NAN_BOXED(29905,32,FLEN) +NAN_BOXED(29905,32,FLEN) +NAN_BOXED(29905,32,FLEN) +NAN_BOXED(30607,32,FLEN) +NAN_BOXED(30607,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(31157,32,FLEN) +NAN_BOXED(31581,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(31335,32,FLEN) +NAN_BOXED(30492,32,FLEN) +NAN_BOXED(30492,32,FLEN) +test_dataset_1: +NAN_BOXED(31495,32,FLEN) +NAN_BOXED(28219,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(29424,32,FLEN) +NAN_BOXED(31672,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(30978,32,FLEN) +NAN_BOXED(29904,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(30251,32,FLEN) +NAN_BOXED(30108,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(30891,32,FLEN) +NAN_BOXED(31546,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(31597,32,FLEN) +NAN_BOXED(31449,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31070,32,FLEN) +NAN_BOXED(28983,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(31670,32,FLEN) +NAN_BOXED(31547,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(31157,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(30870,32,FLEN) +NAN_BOXED(29838,32,FLEN) +NAN_BOXED(31743,32,FLEN) +test_dataset_2: +NAN_BOXED(31444,32,FLEN) +NAN_BOXED(31722,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(31334,32,FLEN) +NAN_BOXED(30352,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(29875,32,FLEN) +NAN_BOXED(31269,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(27047,32,FLEN) +NAN_BOXED(30953,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(31166,32,FLEN) +NAN_BOXED(30026,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(31703,32,FLEN) +NAN_BOXED(30730,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(29939,32,FLEN) +NAN_BOXED(27884,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(29264,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(30945,32,FLEN) +NAN_BOXED(28926,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(31472,32,FLEN) +NAN_BOXED(29956,32,FLEN) +NAN_BOXED(31743,32,FLEN) +test_dataset_3: +NAN_BOXED(31531,16,FLEN) +NAN_BOXED(30218,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30760,16,FLEN) +NAN_BOXED(31014,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30840,16,FLEN) +NAN_BOXED(30965,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30733,16,FLEN) +NAN_BOXED(30437,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29593,16,FLEN) +NAN_BOXED(29904,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30762,16,FLEN) +NAN_BOXED(30818,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30371,16,FLEN) +NAN_BOXED(30883,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30956,16,FLEN) +NAN_BOXED(30990,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30980,16,FLEN) +NAN_BOXED(30580,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30115,16,FLEN) +NAN_BOXED(31143,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(26029,16,FLEN) +NAN_BOXED(27584,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31667,16,FLEN) +NAN_BOXED(29700,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30909,16,FLEN) +NAN_BOXED(29982,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29952,16,FLEN) +NAN_BOXED(30183,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29901,16,FLEN) +NAN_BOXED(30216,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(26339,16,FLEN) +NAN_BOXED(30861,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29941,16,FLEN) +NAN_BOXED(29470,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29602,16,FLEN) +NAN_BOXED(29182,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31124,16,FLEN) +NAN_BOXED(28291,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30038,16,FLEN) +NAN_BOXED(31402,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31447,16,FLEN) +NAN_BOXED(29034,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31027,16,FLEN) +NAN_BOXED(31507,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29490,16,FLEN) +NAN_BOXED(28604,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29210,16,FLEN) +NAN_BOXED(31347,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29151,16,FLEN) +NAN_BOXED(29812,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31010,16,FLEN) +NAN_BOXED(31346,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(28709,16,FLEN) +NAN_BOXED(29867,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29782,16,FLEN) +NAN_BOXED(30089,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30390,16,FLEN) +NAN_BOXED(30348,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(28925,16,FLEN) +NAN_BOXED(23749,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31497,16,FLEN) +NAN_BOXED(31716,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31640,16,FLEN) +NAN_BOXED(31594,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31222,16,FLEN) +NAN_BOXED(31408,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30758,16,FLEN) +NAN_BOXED(29855,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29510,16,FLEN) +NAN_BOXED(27738,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29847,16,FLEN) +NAN_BOXED(31354,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31545,16,FLEN) +NAN_BOXED(31116,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31531,16,FLEN) +NAN_BOXED(31537,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(25274,16,FLEN) +NAN_BOXED(31221,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29899,16,FLEN) +NAN_BOXED(31052,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30365,16,FLEN) +NAN_BOXED(31618,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30069,16,FLEN) +NAN_BOXED(29705,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30625,16,FLEN) +NAN_BOXED(31297,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29263,16,FLEN) +NAN_BOXED(30790,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29050,16,FLEN) +NAN_BOXED(31316,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31345,16,FLEN) +NAN_BOXED(31381,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30982,16,FLEN) +NAN_BOXED(31461,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29783,16,FLEN) +NAN_BOXED(29771,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30403,16,FLEN) +NAN_BOXED(30608,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(22375,16,FLEN) +NAN_BOXED(27395,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(28664,16,FLEN) +NAN_BOXED(27744,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31445,16,FLEN) +NAN_BOXED(28034,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29965,16,FLEN) +NAN_BOXED(29959,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31020,16,FLEN) +NAN_BOXED(30896,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29212,16,FLEN) +NAN_BOXED(30018,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30833,16,FLEN) +NAN_BOXED(31161,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(27932,16,FLEN) +NAN_BOXED(29110,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30933,16,FLEN) +NAN_BOXED(31298,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31335,16,FLEN) +NAN_BOXED(30971,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30196,16,FLEN) +NAN_BOXED(30703,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30393,16,FLEN) +NAN_BOXED(31116,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29654,16,FLEN) +NAN_BOXED(30792,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(27796,16,FLEN) +NAN_BOXED(30411,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31496,16,FLEN) +NAN_BOXED(31612,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31533,16,FLEN) +NAN_BOXED(31315,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30572,16,FLEN) +NAN_BOXED(28640,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31051,16,FLEN) +NAN_BOXED(31512,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31062,16,FLEN) +NAN_BOXED(31197,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(28312,16,FLEN) +NAN_BOXED(30899,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(28823,16,FLEN) +NAN_BOXED(31281,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(28127,16,FLEN) +NAN_BOXED(28250,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29114,16,FLEN) +NAN_BOXED(26114,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(28610,16,FLEN) +NAN_BOXED(31423,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31407,16,FLEN) +NAN_BOXED(31645,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31331,16,FLEN) +NAN_BOXED(26787,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30742,16,FLEN) +NAN_BOXED(31159,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31229,16,FLEN) +NAN_BOXED(31609,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29999,16,FLEN) +NAN_BOXED(30850,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29630,16,FLEN) +NAN_BOXED(29119,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30956,16,FLEN) +NAN_BOXED(31238,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30176,16,FLEN) +NAN_BOXED(30295,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30384,16,FLEN) +NAN_BOXED(27987,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31687,16,FLEN) +NAN_BOXED(30362,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(28963,16,FLEN) +NAN_BOXED(31110,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31075,16,FLEN) +NAN_BOXED(30754,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31012,16,FLEN) +NAN_BOXED(31532,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(28193,16,FLEN) +NAN_BOXED(31227,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30754,16,FLEN) +NAN_BOXED(30485,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29171,16,FLEN) +NAN_BOXED(29766,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30894,16,FLEN) +NAN_BOXED(29960,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31110,16,FLEN) +NAN_BOXED(31647,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31139,16,FLEN) +NAN_BOXED(30363,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30892,16,FLEN) +NAN_BOXED(29765,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(26090,16,FLEN) +NAN_BOXED(30635,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29058,16,FLEN) +NAN_BOXED(30147,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31280,16,FLEN) +NAN_BOXED(28823,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30635,16,FLEN) +NAN_BOXED(30922,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31404,16,FLEN) +NAN_BOXED(31377,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30642,16,FLEN) +NAN_BOXED(31171,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30310,16,FLEN) +NAN_BOXED(31197,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30585,16,FLEN) +NAN_BOXED(29527,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31165,16,FLEN) +NAN_BOXED(31078,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31443,16,FLEN) +NAN_BOXED(29630,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29730,16,FLEN) +NAN_BOXED(29180,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31453,16,FLEN) +NAN_BOXED(31537,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31466,16,FLEN) +NAN_BOXED(29955,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31188,16,FLEN) +NAN_BOXED(28031,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31403,16,FLEN) +NAN_BOXED(29866,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30883,16,FLEN) +NAN_BOXED(31078,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30042,16,FLEN) +NAN_BOXED(30457,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29368,16,FLEN) +NAN_BOXED(30893,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30272,16,FLEN) +NAN_BOXED(30810,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29796,16,FLEN) +NAN_BOXED(31058,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31512,16,FLEN) +NAN_BOXED(31556,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31622,16,FLEN) +NAN_BOXED(30204,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31246,16,FLEN) +NAN_BOXED(29881,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31034,16,FLEN) +NAN_BOXED(31345,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31239,16,FLEN) +NAN_BOXED(31663,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30793,16,FLEN) +NAN_BOXED(28479,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30113,16,FLEN) +NAN_BOXED(31165,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30855,16,FLEN) +NAN_BOXED(29138,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30987,16,FLEN) +NAN_BOXED(29114,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31037,16,FLEN) +NAN_BOXED(28640,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(28805,16,FLEN) +NAN_BOXED(30029,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30918,16,FLEN) +NAN_BOXED(30831,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30545,16,FLEN) +NAN_BOXED(29951,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(27747,16,FLEN) +NAN_BOXED(31161,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30807,16,FLEN) +NAN_BOXED(31210,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29760,16,FLEN) +NAN_BOXED(30241,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(26979,16,FLEN) +NAN_BOXED(30729,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31269,16,FLEN) +NAN_BOXED(30121,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30323,16,FLEN) +NAN_BOXED(30804,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30116,16,FLEN) +NAN_BOXED(31429,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29779,16,FLEN) +NAN_BOXED(28255,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31290,16,FLEN) +NAN_BOXED(31184,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29196,16,FLEN) +NAN_BOXED(30377,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31365,16,FLEN) +NAN_BOXED(31228,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(28847,16,FLEN) +NAN_BOXED(30303,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30775,16,FLEN) +NAN_BOXED(30859,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29696,16,FLEN) +NAN_BOXED(31296,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31340,16,FLEN) +NAN_BOXED(31520,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30240,16,FLEN) +NAN_BOXED(30827,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30993,16,FLEN) +NAN_BOXED(31695,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29897,16,FLEN) +NAN_BOXED(31456,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30926,16,FLEN) +NAN_BOXED(31183,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31273,16,FLEN) +NAN_BOXED(31050,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30767,16,FLEN) +NAN_BOXED(30557,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30779,16,FLEN) +NAN_BOXED(26813,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31018,16,FLEN) +NAN_BOXED(30490,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31659,16,FLEN) +NAN_BOXED(31522,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31317,16,FLEN) +NAN_BOXED(30971,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30145,16,FLEN) +NAN_BOXED(29559,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30799,16,FLEN) +NAN_BOXED(31599,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31477,16,FLEN) +NAN_BOXED(31117,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31452,16,FLEN) +NAN_BOXED(30926,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31161,16,FLEN) +NAN_BOXED(31210,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31347,16,FLEN) +NAN_BOXED(31603,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30461,16,FLEN) +NAN_BOXED(31245,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(28410,16,FLEN) +NAN_BOXED(26998,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29288,16,FLEN) +NAN_BOXED(28964,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31127,16,FLEN) +NAN_BOXED(30796,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31024,16,FLEN) +NAN_BOXED(29919,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31245,16,FLEN) +NAN_BOXED(30315,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31537,16,FLEN) +NAN_BOXED(31169,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30190,16,FLEN) +NAN_BOXED(30779,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29480,16,FLEN) +NAN_BOXED(22919,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31299,16,FLEN) +NAN_BOXED(28822,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29247,16,FLEN) +NAN_BOXED(29361,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29596,16,FLEN) +NAN_BOXED(30810,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29566,16,FLEN) +NAN_BOXED(31734,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31408,16,FLEN) +NAN_BOXED(30622,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30766,16,FLEN) +NAN_BOXED(31213,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(27672,16,FLEN) +NAN_BOXED(31248,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29905,16,FLEN) +NAN_BOXED(26607,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30607,16,FLEN) +NAN_BOXED(31167,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31335,16,FLEN) +NAN_BOXED(30492,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31597,16,FLEN) +NAN_BOXED(31449,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31070,16,FLEN) +NAN_BOXED(28983,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31157,16,FLEN) +NAN_BOXED(29376,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(26627,16,FLEN) +NAN_BOXED(29264,16,FLEN) +NAN_BOXED(31743,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x9_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x9_1: + .fill 26*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_0: + .fill 26*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x4_0: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x4_1: + .fill 116*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fnmsub_b17-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fnmsub_b17-01.S new file mode 100644 index 000000000..ce03a8ee9 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fnmsub_b17-01.S @@ -0,0 +1,2199 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 06:07:02 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fnmsub.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fnmsub.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fnmsub_b17 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fnmsub_b17) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x5,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==x15, rs2==x15, rs3==x13, rd==x27,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x05a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x15; op2:x15; op3:x13; dest:x27; op1val:0x739c; op2val:0x739c; +op3val:0x7bff; valaddr_reg:x5; val_offset:0*FLEN/8; rmval:dyn; +testreg:x8; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x27, x15, x15, x13, dyn, 0, 0, x5, 0*FLEN/8, x10, x1, x8) + +inst_1: +// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==x3, rs2==x31, rs3==x24, rd==x3,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x100 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x3; op2:x31; op3:x24; dest:x3; op1val:0x78d4; op2val:0x7900; +op3val:0x7bff; valaddr_reg:x5; val_offset:3*FLEN/8; rmval:dyn; +testreg:x8; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x3, x3, x31, x24, dyn, 0, 0, x5, 3*FLEN/8, x10, x1, x8) + +inst_2: +// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==x7, rs2==x25, rs3==x10, rd==x13,fs1 == 0 and fe1 == 0x18 and fm1 == 0x2bd and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x7; op2:x25; op3:x10; dest:x13; op1val:0x62bd; op2val:0x7ab2; +op3val:0x7bff; valaddr_reg:x5; val_offset:6*FLEN/8; rmval:dyn; +testreg:x8; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x13, x7, x25, x10, dyn, 0, 0, x5, 6*FLEN/8, x10, x1, x8) + +inst_3: +// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==x19, rs2==x2, rs3==x19, rd==x14,fs1 == 0 and fe1 == 0x1c and fm1 == 0x37e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3f6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x19; op2:x2; op3:x19; dest:x14; op1val:0x737e; op2val:0x7bf6; +op3val:0x737e; valaddr_reg:x5; val_offset:9*FLEN/8; rmval:dyn; +testreg:x8; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x14, x19, x2, x19, dyn, 0, 0, x5, 9*FLEN/8, x10, x1, x8) + +inst_4: +// rs1 == rs2 == rs3 != rd, rs1==x12, rs2==x12, rs3==x12, rd==x17,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x39e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x12; op2:x12; op3:x12; dest:x17; op1val:0x7ab0; op2val:0x7ab0; +op3val:0x7ab0; valaddr_reg:x5; val_offset:12*FLEN/8; rmval:dyn; +testreg:x8; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x17, x12, x12, x12, dyn, 0, 0, x5, 12*FLEN/8, x10, x1, x8) + +inst_5: +// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==x6, rs2==x4, rs3==x28, rd==x28,fs1 == 0 and fe1 == 0x1c and fm1 == 0x0d1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x113 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x6; op2:x4; op3:x28; dest:x28; op1val:0x70d1; op2val:0x7913; +op3val:0x7bff; valaddr_reg:x5; val_offset:15*FLEN/8; rmval:dyn; +testreg:x8; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x28, x6, x4, x28, dyn, 0, 0, x5, 15*FLEN/8, x10, x1, x8) + +inst_6: +// rd == rs2 == rs3 != rs1, rs1==x24, rs2==x0, rs3==x0, rd==x0,fs1 == 0 and fe1 == 0x1e and fm1 == 0x02e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1ed and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x24; op2:x0; op3:x0; dest:x0; op1val:0x782e; op2val:0x0; +op3val:0x0; valaddr_reg:x5; val_offset:18*FLEN/8; rmval:dyn; +testreg:x8; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x0, x24, x0, x0, dyn, 0, 0, x5, 18*FLEN/8, x10, x1, x8) + +inst_7: +// rs1 == rd == rs3 != rs2, rs1==x9, rs2==x7, rs3==x9, rd==x9,fs1 == 0 and fe1 == 0x1b and fm1 == 0x018 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x210 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x9; op2:x7; op3:x9; dest:x9; op1val:0x6c18; op2val:0x7a10; +op3val:0x6c18; valaddr_reg:x5; val_offset:21*FLEN/8; rmval:dyn; +testreg:x8; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x9, x9, x7, x9, dyn, 0, 0, x5, 21*FLEN/8, x10, x1, x8) + +inst_8: +// rs1 == rs2 == rs3 == rd, rs1==x16, rs2==x16, rs3==x16, rd==x16,fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d1 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x3ef and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x16; op2:x16; op3:x16; dest:x16; op1val:0x74d1; op2val:0x74d1; +op3val:0x74d1; valaddr_reg:x5; val_offset:24*FLEN/8; rmval:dyn; +testreg:x8; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x16, x16, x16, x16, dyn, 0, 0, x5, 24*FLEN/8, x10, x1, x8) + +inst_9: +// rs1 == rs2 == rd != rs3, rs1==x30, rs2==x30, rs3==x4, rd==x30,fs1 == 0 and fe1 == 0x1d and fm1 == 0x38f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1bf and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x30; op3:x4; dest:x30; op1val:0x778f; op2val:0x778f; +op3val:0x7bff; valaddr_reg:x5; val_offset:27*FLEN/8; rmval:dyn; +testreg:x8; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x30, x30, x30, x4, dyn, 0, 0, x5, 27*FLEN/8, x10, x1, x8) + +inst_10: +// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==x17, rs2==x29, rs3==x3, rd==x29,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x35d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x17; op2:x29; op3:x3; dest:x29; op1val:0x79b5; op2val:0x7b5d; +op3val:0x7bff; valaddr_reg:x5; val_offset:30*FLEN/8; rmval:dyn; +testreg:x8; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x29, x17, x29, x3, dyn, 0, 0, x5, 30*FLEN/8, x10, x1, x8) + +inst_11: +// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==x21, rs2==x22, rs3==x22, rd==x20,fs1 == 0 and fe1 == 0x1e and fm1 == 0x267 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x31c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x21; op2:x22; op3:x22; dest:x20; op1val:0x7a67; op2val:0x771c; +op3val:0x771c; valaddr_reg:x5; val_offset:33*FLEN/8; rmval:dyn; +testreg:x8; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x20, x21, x22, x22, dyn, 0, 0, x5, 33*FLEN/8, x10, x1, x8) +RVTEST_VALBASEUPD(x9,test_dataset_1) + +inst_12: +// rs1==x11, rs2==x20, rs3==x6, rd==x5,fs1 == 0 and fe1 == 0x1e and fm1 == 0x307 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x23b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x11; op2:x20; op3:x6; dest:x5; op1val:0x7b07; op2val:0x6e3b; +op3val:0x7bff; valaddr_reg:x9; val_offset:0*FLEN/8; rmval:dyn; +testreg:x8; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x5, x11, x20, x6, dyn, 0, 0, x9, 0*FLEN/8, x10, x1, x8) +RVTEST_SIGBASE(x3,signature_x3_0) + +inst_13: +// rs1==x26, rs2==x5, rs3==x30, rd==x6,fs1 == 0 and fe1 == 0x1c and fm1 == 0x2f0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3b8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x26; op2:x5; op3:x30; dest:x6; op1val:0x72f0; op2val:0x7bb8; +op3val:0x7bff; valaddr_reg:x9; val_offset:3*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x6, x26, x5, x30, dyn, 0, 0, x9, 3*FLEN/8, x10, x3, x7) + +inst_14: +// rs1==x2, rs2==x14, rs3==x20, rd==x8,fs1 == 0 and fe1 == 0x1e and fm1 == 0x102 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0d0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x2; op2:x14; op3:x20; dest:x8; op1val:0x7902; op2val:0x74d0; +op3val:0x7bff; valaddr_reg:x9; val_offset:6*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x8, x2, x14, x20, dyn, 0, 0, x9, 6*FLEN/8, x10, x3, x7) + +inst_15: +// rs1==x28, rs2==x18, rs3==x21, rd==x19,fs1 == 0 and fe1 == 0x1d and fm1 == 0x22b and fs2 == 0 and fe2 == 0x1d and fm2 == 0x19c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x28; op2:x18; op3:x21; dest:x19; op1val:0x762b; op2val:0x759c; +op3val:0x7bff; valaddr_reg:x9; val_offset:9*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x19, x28, x18, x21, dyn, 0, 0, x9, 9*FLEN/8, x10, x3, x7) + +inst_16: +// rs1==x13, rs2==x24, rs3==x26, rd==x25,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ab and fs2 == 0 and fe2 == 0x1e and fm2 == 0x33a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x13; op2:x24; op3:x26; dest:x25; op1val:0x78ab; op2val:0x7b3a; +op3val:0x7bff; valaddr_reg:x9; val_offset:12*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x25, x13, x24, x26, dyn, 0, 0, x9, 12*FLEN/8, x10, x3, x7) + +inst_17: +// rs1==x18, rs2==x13, rs3==x11, rd==x2,fs1 == 0 and fe1 == 0x1e and fm1 == 0x36d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2d9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x18; op2:x13; op3:x11; dest:x2; op1val:0x7b6d; op2val:0x7ad9; +op3val:0x7bff; valaddr_reg:x9; val_offset:15*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x2, x18, x13, x11, dyn, 0, 0, x9, 15*FLEN/8, x10, x3, x7) + +inst_18: +// rs1==x23, rs2==x1, rs3==x7, rd==x22,fs1 == 0 and fe1 == 0x1e and fm1 == 0x15e and fs2 == 0 and fe2 == 0x1c and fm2 == 0x137 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x23; op2:x1; op3:x7; dest:x22; op1val:0x795e; op2val:0x7137; +op3val:0x7bff; valaddr_reg:x9; val_offset:18*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x22, x23, x1, x7, dyn, 0, 0, x9, 18*FLEN/8, x10, x3, x7) + +inst_19: +// rs1==x4, rs2==x28, rs3==x29, rd==x12,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x33b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x4; op2:x28; op3:x29; dest:x12; op1val:0x7bb6; op2val:0x7b3b; +op3val:0x7bff; valaddr_reg:x9; val_offset:21*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x12, x4, x28, x29, dyn, 0, 0, x9, 21*FLEN/8, x10, x3, x7) + +inst_20: +// rs1==x0, rs2==x17, rs3==x25, rd==x18,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b5 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2c0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x0; op2:x17; op3:x25; dest:x18; op1val:0x0; op2val:0x72c0; +op3val:0x7bff; valaddr_reg:x9; val_offset:24*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x18, x0, x17, x25, dyn, 0, 0, x9, 24*FLEN/8, x10, x3, x7) + +inst_21: +// rs1==x25, rs2==x21, rs3==x1, rd==x4,fs1 == 0 and fe1 == 0x1e and fm1 == 0x096 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x08e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x25; op2:x21; op3:x1; dest:x4; op1val:0x7896; op2val:0x748e; +op3val:0x7bff; valaddr_reg:x9; val_offset:27*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x4, x25, x21, x1, dyn, 0, 0, x9, 27*FLEN/8, x10, x3, x7) + +inst_22: +// rs1==x20, rs2==x23, rs3==x18, rd==x15,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ea and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x20; op2:x23; op3:x18; dest:x15; op1val:0x7ad4; op2val:0x7bea; +op3val:0x7bff; valaddr_reg:x9; val_offset:30*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x15, x20, x23, x18, dyn, 0, 0, x9, 30*FLEN/8, x10, x3, x7) +RVTEST_VALBASEUPD(x12,test_dataset_2) + +inst_23: +// rs1==x22, rs2==x9, rs3==x5, rd==x26,fs1 == 0 and fe1 == 0x1e and fm1 == 0x266 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x290 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x22; op2:x9; op3:x5; dest:x26; op1val:0x7a66; op2val:0x7690; +op3val:0x7bff; valaddr_reg:x12; val_offset:0*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x26, x22, x9, x5, dyn, 0, 0, x12, 0*FLEN/8, x13, x3, x7) + +inst_24: +// rs1==x10, rs2==x27, rs3==x8, rd==x11,fs1 == 0 and fe1 == 0x1d and fm1 == 0x0b3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x225 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x10; op2:x27; op3:x8; dest:x11; op1val:0x74b3; op2val:0x7a25; +op3val:0x7bff; valaddr_reg:x12; val_offset:3*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x11, x10, x27, x8, dyn, 0, 0, x12, 3*FLEN/8, x13, x3, x7) +RVTEST_SIGBASE(x2,signature_x2_0) + +inst_25: +// rs1==x5, rs2==x6, rs3==x27, rd==x1,fs1 == 0 and fe1 == 0x1a and fm1 == 0x1a7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0e9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x5; op2:x6; op3:x27; dest:x1; op1val:0x69a7; op2val:0x78e9; +op3val:0x7bff; valaddr_reg:x12; val_offset:6*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x1, x5, x6, x27, dyn, 0, 0, x12, 6*FLEN/8, x13, x2, x4) + +inst_26: +// rs1==x31, rs2==x3, rs3==x2, rd==x21,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1be and fs2 == 0 and fe2 == 0x1d and fm2 == 0x14a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x31; op2:x3; op3:x2; dest:x21; op1val:0x79be; op2val:0x754a; +op3val:0x7bff; valaddr_reg:x12; val_offset:9*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x21, x31, x3, x2, dyn, 0, 0, x12, 9*FLEN/8, x13, x2, x4) + +inst_27: +// rs1==x1, rs2==x26, rs3==x14, rd==x24,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x00a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x1; op2:x26; op3:x14; dest:x24; op1val:0x7bd7; op2val:0x780a; +op3val:0x7bff; valaddr_reg:x12; val_offset:12*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x24, x1, x26, x14, dyn, 0, 0, x12, 12*FLEN/8, x13, x2, x4) + +inst_28: +// rs1==x8, rs2==x10, rs3==x17, rd==x7,fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f3 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0ec and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x8; op2:x10; op3:x17; dest:x7; op1val:0x74f3; op2val:0x6cec; +op3val:0x7bff; valaddr_reg:x12; val_offset:15*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x7, x8, x10, x17, dyn, 0, 0, x12, 15*FLEN/8, x13, x2, x4) + +inst_29: +// rs1==x14, rs2==x8, rs3==x15, rd==x10,fs1 == 0 and fe1 == 0x1a and fm1 == 0x003 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x250 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x14; op2:x8; op3:x15; dest:x10; op1val:0x6803; op2val:0x7250; +op3val:0x7bff; valaddr_reg:x12; val_offset:18*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x10, x14, x8, x15, dyn, 0, 0, x12, 18*FLEN/8, x13, x2, x4) + +inst_30: +// rs1==x29, rs2==x19, rs3==x31, rd==x23,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e1 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x29; op2:x19; op3:x31; dest:x23; op1val:0x78e1; op2val:0x70fe; +op3val:0x7bff; valaddr_reg:x12; val_offset:21*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x23, x29, x19, x31, dyn, 0, 0, x12, 21*FLEN/8, x13, x2, x4) + +inst_31: +// rs1==x27, rs2==x11, rs3==x23, rd==x31,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f0 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x104 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x27; op2:x11; op3:x23; dest:x31; op1val:0x7af0; op2val:0x7504; +op3val:0x7bff; valaddr_reg:x12; val_offset:24*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x27, x11, x23, dyn, 0, 0, x12, 24*FLEN/8, x13, x2, x4) + +inst_32: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32b and fs2 == 0 and fe2 == 0x1d and fm2 == 0x20a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b2b; op2val:0x760a; +op3val:0x7bff; valaddr_reg:x12; val_offset:27*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 27*FLEN/8, x13, x2, x4) + +inst_33: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x028 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x126 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7828; op2val:0x7926; +op3val:0x7bff; valaddr_reg:x12; val_offset:30*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 30*FLEN/8, x13, x2, x4) + +inst_34: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x078 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0f5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7878; op2val:0x78f5; +op3val:0x7bff; valaddr_reg:x12; val_offset:33*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 33*FLEN/8, x13, x2, x4) + +inst_35: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00d and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2e5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x780d; op2val:0x76e5; +op3val:0x7bff; valaddr_reg:x12; val_offset:36*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 36*FLEN/8, x13, x2, x4) + +inst_36: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x399 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0d0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7399; op2val:0x74d0; +op3val:0x7bff; valaddr_reg:x12; val_offset:39*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 39*FLEN/8, x13, x2, x4) + +inst_37: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x062 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x782a; op2val:0x7862; +op3val:0x7bff; valaddr_reg:x12; val_offset:42*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 42*FLEN/8, x13, x2, x4) + +inst_38: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0a3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76a3; op2val:0x78a3; +op3val:0x7bff; valaddr_reg:x12; val_offset:45*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 45*FLEN/8, x13, x2, x4) + +inst_39: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ec and fs2 == 0 and fe2 == 0x1e and fm2 == 0x10e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78ec; op2val:0x790e; +op3val:0x7bff; valaddr_reg:x12; val_offset:48*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 48*FLEN/8, x13, x2, x4) + +inst_40: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x104 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x374 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7904; op2val:0x7774; +op3val:0x7bff; valaddr_reg:x12; val_offset:51*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 51*FLEN/8, x13, x2, x4) + +inst_41: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1a7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75a3; op2val:0x79a7; +op3val:0x7bff; valaddr_reg:x12; val_offset:54*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 54*FLEN/8, x13, x2, x4) + +inst_42: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x1ad and fs2 == 0 and fe2 == 0x1a and fm2 == 0x3c0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x65ad; op2val:0x6bc0; +op3val:0x7bff; valaddr_reg:x12; val_offset:57*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 57*FLEN/8, x13, x2, x4) + +inst_43: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b3 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x004 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bb3; op2val:0x7404; +op3val:0x7bff; valaddr_reg:x12; val_offset:60*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 60*FLEN/8, x13, x2, x4) + +inst_44: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0bd and fs2 == 0 and fe2 == 0x1d and fm2 == 0x11e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78bd; op2val:0x751e; +op3val:0x7bff; valaddr_reg:x12; val_offset:63*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 63*FLEN/8, x13, x2, x4) + +inst_45: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x100 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1e7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7500; op2val:0x75e7; +op3val:0x7bff; valaddr_reg:x12; val_offset:66*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 66*FLEN/8, x13, x2, x4) + +inst_46: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0cd and fs2 == 0 and fe2 == 0x1d and fm2 == 0x208 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74cd; op2val:0x7608; +op3val:0x7bff; valaddr_reg:x12; val_offset:69*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 69*FLEN/8, x13, x2, x4) + +inst_47: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x08d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x66e3; op2val:0x788d; +op3val:0x7bff; valaddr_reg:x12; val_offset:72*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 72*FLEN/8, x13, x2, x4) + +inst_48: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f5 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x31e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74f5; op2val:0x731e; +op3val:0x7bff; valaddr_reg:x12; val_offset:75*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 75*FLEN/8, x13, x2, x4) + +inst_49: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3a2 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73a2; op2val:0x71fe; +op3val:0x7bff; valaddr_reg:x12; val_offset:78*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 78*FLEN/8, x13, x2, x4) + +inst_50: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x194 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x283 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7994; op2val:0x6e83; +op3val:0x7bff; valaddr_reg:x12; val_offset:81*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 81*FLEN/8, x13, x2, x4) + +inst_51: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x156 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2aa and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7556; op2val:0x7aaa; +op3val:0x7bff; valaddr_reg:x12; val_offset:84*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 84*FLEN/8, x13, x2, x4) + +inst_52: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d7 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x16a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ad7; op2val:0x716a; +op3val:0x7bff; valaddr_reg:x12; val_offset:87*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 87*FLEN/8, x13, x2, x4) + +inst_53: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x133 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x313 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7933; op2val:0x7b13; +op3val:0x7bff; valaddr_reg:x12; val_offset:90*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 90*FLEN/8, x13, x2, x4) + +inst_54: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x332 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3bc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7332; op2val:0x6fbc; +op3val:0x7bff; valaddr_reg:x12; val_offset:93*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 93*FLEN/8, x13, x2, x4) + +inst_55: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x21a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x273 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x721a; op2val:0x7a73; +op3val:0x7bff; valaddr_reg:x12; val_offset:96*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 96*FLEN/8, x13, x2, x4) + +inst_56: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1df and fs2 == 0 and fe2 == 0x1d and fm2 == 0x074 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71df; op2val:0x7474; +op3val:0x7bff; valaddr_reg:x12; val_offset:99*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 99*FLEN/8, x13, x2, x4) + +inst_57: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x122 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x272 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7922; op2val:0x7a72; +op3val:0x7bff; valaddr_reg:x12; val_offset:102*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 102*FLEN/8, x13, x2, x4) + +inst_58: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x025 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0ab and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7025; op2val:0x74ab; +op3val:0x7bff; valaddr_reg:x12; val_offset:105*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 105*FLEN/8, x13, x2, x4) + +inst_59: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x056 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x189 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7456; op2val:0x7589; +op3val:0x7bff; valaddr_reg:x12; val_offset:108*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 108*FLEN/8, x13, x2, x4) + +inst_60: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2b6 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x28c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76b6; op2val:0x768c; +op3val:0x7bff; valaddr_reg:x12; val_offset:111*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 111*FLEN/8, x13, x2, x4) + +inst_61: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0fd and fs2 == 0 and fe2 == 0x17 and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70fd; op2val:0x5cc5; +op3val:0x7bff; valaddr_reg:x12; val_offset:114*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 114*FLEN/8, x13, x2, x4) + +inst_62: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x309 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3e4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b09; op2val:0x7be4; +op3val:0x7bff; valaddr_reg:x12; val_offset:117*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 117*FLEN/8, x13, x2, x4) + +inst_63: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x398 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x36a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b98; op2val:0x7b6a; +op3val:0x7bff; valaddr_reg:x12; val_offset:120*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 120*FLEN/8, x13, x2, x4) + +inst_64: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f6; op2val:0x7ab0; +op3val:0x7bff; valaddr_reg:x12; val_offset:123*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 123*FLEN/8, x13, x2, x4) + +inst_65: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x026 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x09f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7826; op2val:0x749f; +op3val:0x7bff; valaddr_reg:x12; val_offset:126*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 126*FLEN/8, x13, x2, x4) + +inst_66: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x346 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x05a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7346; op2val:0x6c5a; +op3val:0x7bff; valaddr_reg:x12; val_offset:129*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 129*FLEN/8, x13, x2, x4) + +inst_67: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x097 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x27a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7497; op2val:0x7a7a; +op3val:0x7bff; valaddr_reg:x12; val_offset:132*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 132*FLEN/8, x13, x2, x4) + +inst_68: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x339 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x18c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b39; op2val:0x798c; +op3val:0x7bff; valaddr_reg:x12; val_offset:135*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 135*FLEN/8, x13, x2, x4) + +inst_69: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x331 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b2b; op2val:0x7b31; +op3val:0x7bff; valaddr_reg:x12; val_offset:138*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 138*FLEN/8, x13, x2, x4) + +inst_70: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x2ba and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1f5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x62ba; op2val:0x79f5; +op3val:0x7bff; valaddr_reg:x12; val_offset:141*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 141*FLEN/8, x13, x2, x4) + +inst_71: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0cb and fs2 == 0 and fe2 == 0x1e and fm2 == 0x14c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74cb; op2val:0x794c; +op3val:0x7bff; valaddr_reg:x12; val_offset:144*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 144*FLEN/8, x13, x2, x4) + +inst_72: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x29d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x382 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x769d; op2val:0x7b82; +op3val:0x7bff; valaddr_reg:x12; val_offset:147*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 147*FLEN/8, x13, x2, x4) + +inst_73: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x175 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x009 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7575; op2val:0x7409; +op3val:0x7bff; valaddr_reg:x12; val_offset:150*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 150*FLEN/8, x13, x2, x4) + +inst_74: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x241 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77a1; op2val:0x7a41; +op3val:0x7bff; valaddr_reg:x12; val_offset:153*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 153*FLEN/8, x13, x2, x4) + +inst_75: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x24f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x046 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x724f; op2val:0x7846; +op3val:0x7bff; valaddr_reg:x12; val_offset:156*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 156*FLEN/8, x13, x2, x4) + +inst_76: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x17a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x254 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x717a; op2val:0x7a54; +op3val:0x7bff; valaddr_reg:x12; val_offset:159*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 159*FLEN/8, x13, x2, x4) + +inst_77: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x271 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x295 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a71; op2val:0x7a95; +op3val:0x7bff; valaddr_reg:x12; val_offset:162*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 162*FLEN/8, x13, x2, x4) + +inst_78: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x106 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2e5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7906; op2val:0x7ae5; +op3val:0x7bff; valaddr_reg:x12; val_offset:165*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 165*FLEN/8, x13, x2, x4) + +inst_79: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x057 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x04b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7457; op2val:0x744b; +op3val:0x7bff; valaddr_reg:x12; val_offset:168*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 168*FLEN/8, x13, x2, x4) + +inst_80: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2c3 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x390 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76c3; op2val:0x7790; +op3val:0x7bff; valaddr_reg:x12; val_offset:171*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 171*FLEN/8, x13, x2, x4) + +inst_81: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x367 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x303 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5767; op2val:0x6b03; +op3val:0x7bff; valaddr_reg:x12; val_offset:174*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 174*FLEN/8, x13, x2, x4) + +inst_82: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x060 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ff8; op2val:0x6c60; +op3val:0x7bff; valaddr_reg:x12; val_offset:177*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 177*FLEN/8, x13, x2, x4) + +inst_83: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d5 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x182 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ad5; op2val:0x6d82; +op3val:0x7bff; valaddr_reg:x12; val_offset:180*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 180*FLEN/8, x13, x2, x4) + +inst_84: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x10d and fs2 == 0 and fe2 == 0x1d and fm2 == 0x107 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x750d; op2val:0x7507; +op3val:0x7bff; valaddr_reg:x12; val_offset:183*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 183*FLEN/8, x13, x2, x4) + +inst_85: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0b0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x792c; op2val:0x78b0; +op3val:0x7bff; valaddr_reg:x12; val_offset:186*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 186*FLEN/8, x13, x2, x4) + +inst_86: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x21c and fs2 == 0 and fe2 == 0x1d and fm2 == 0x142 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x721c; op2val:0x7542; +op3val:0x7bff; valaddr_reg:x12; val_offset:189*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 189*FLEN/8, x13, x2, x4) + +inst_87: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x071 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1b9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7871; op2val:0x79b9; +op3val:0x7bff; valaddr_reg:x12; val_offset:192*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 192*FLEN/8, x13, x2, x4) + +inst_88: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x11c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1b6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d1c; op2val:0x71b6; +op3val:0x7bff; valaddr_reg:x12; val_offset:195*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 195*FLEN/8, x13, x2, x4) + +inst_89: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x242 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78d5; op2val:0x7a42; +op3val:0x7bff; valaddr_reg:x12; val_offset:198*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 198*FLEN/8, x13, x2, x4) + +inst_90: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x267 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0fb and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a67; op2val:0x78fb; +op3val:0x7bff; valaddr_reg:x12; val_offset:201*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 201*FLEN/8, x13, x2, x4) + +inst_91: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1f4 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3ef and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75f4; op2val:0x77ef; +op3val:0x7bff; valaddr_reg:x12; val_offset:204*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 204*FLEN/8, x13, x2, x4) + +inst_92: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2b9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x18c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76b9; op2val:0x798c; +op3val:0x7bff; valaddr_reg:x12; val_offset:207*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 207*FLEN/8, x13, x2, x4) + +inst_93: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x048 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73d6; op2val:0x7848; +op3val:0x7bff; valaddr_reg:x12; val_offset:210*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 210*FLEN/8, x13, x2, x4) + +inst_94: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x094 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2cb and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c94; op2val:0x76cb; +op3val:0x7bff; valaddr_reg:x12; val_offset:213*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 213*FLEN/8, x13, x2, x4) + +inst_95: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x308 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x37c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b08; op2val:0x7b7c; +op3val:0x7bff; valaddr_reg:x12; val_offset:216*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 216*FLEN/8, x13, x2, x4) + +inst_96: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x253 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b2d; op2val:0x7a53; +op3val:0x7bff; valaddr_reg:x12; val_offset:219*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 219*FLEN/8, x13, x2, x4) + +inst_97: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x36c and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3e0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x776c; op2val:0x6fe0; +op3val:0x7bff; valaddr_reg:x12; val_offset:222*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 222*FLEN/8, x13, x2, x4) + +inst_98: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x14b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x318 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x794b; op2val:0x7b18; +op3val:0x7bff; valaddr_reg:x12; val_offset:225*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 225*FLEN/8, x13, x2, x4) + +inst_99: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x156 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1dd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7956; op2val:0x79dd; +op3val:0x7bff; valaddr_reg:x12; val_offset:228*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 228*FLEN/8, x13, x2, x4) + +inst_100: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x298 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0b3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e98; op2val:0x78b3; +op3val:0x7bff; valaddr_reg:x12; val_offset:231*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 231*FLEN/8, x13, x2, x4) + +inst_101: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x097 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x231 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7097; op2val:0x7a31; +op3val:0x7bff; valaddr_reg:x12; val_offset:234*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 234*FLEN/8, x13, x2, x4) + +inst_102: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1df and fs2 == 0 and fe2 == 0x1b and fm2 == 0x25a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ddf; op2val:0x6e5a; +op3val:0x7bff; valaddr_reg:x12; val_offset:237*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 237*FLEN/8, x13, x2, x4) + +inst_103: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1ba and fs2 == 0 and fe2 == 0x19 and fm2 == 0x202 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71ba; op2val:0x6602; +op3val:0x7bff; valaddr_reg:x12; val_offset:240*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 240*FLEN/8, x13, x2, x4) + +inst_104: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3c2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2bf and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6fc2; op2val:0x7abf; +op3val:0x7bff; valaddr_reg:x12; val_offset:243*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 243*FLEN/8, x13, x2, x4) + +inst_105: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2af and fs2 == 0 and fe2 == 0x1e and fm2 == 0x39d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aaf; op2val:0x7b9d; +op3val:0x7bff; valaddr_reg:x12; val_offset:246*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 246*FLEN/8, x13, x2, x4) + +inst_106: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x263 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x0a3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a63; op2val:0x68a3; +op3val:0x7bff; valaddr_reg:x12; val_offset:249*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 249*FLEN/8, x13, x2, x4) + +inst_107: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x016 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1b7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7816; op2val:0x79b7; +op3val:0x7bff; valaddr_reg:x12; val_offset:252*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 252*FLEN/8, x13, x2, x4) + +inst_108: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1fd and fs2 == 0 and fe2 == 0x1e and fm2 == 0x379 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79fd; op2val:0x7b79; +op3val:0x7bff; valaddr_reg:x12; val_offset:255*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 255*FLEN/8, x13, x2, x4) + +inst_109: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x12f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x082 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x752f; op2val:0x7882; +op3val:0x7bff; valaddr_reg:x12; val_offset:258*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 258*FLEN/8, x13, x2, x4) + +inst_110: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3be and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1bf and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73be; op2val:0x71bf; +op3val:0x7bff; valaddr_reg:x12; val_offset:261*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 261*FLEN/8, x13, x2, x4) + +inst_111: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ec and fs2 == 0 and fe2 == 0x1e and fm2 == 0x206 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78ec; op2val:0x7a06; +op3val:0x7bff; valaddr_reg:x12; val_offset:264*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 264*FLEN/8, x13, x2, x4) + +inst_112: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1e0 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x257 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75e0; op2val:0x7657; +op3val:0x7bff; valaddr_reg:x12; val_offset:267*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 267*FLEN/8, x13, x2, x4) + +inst_113: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x153 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76b0; op2val:0x6d53; +op3val:0x7bff; valaddr_reg:x12; val_offset:270*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 270*FLEN/8, x13, x2, x4) + +inst_114: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c7 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x29a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bc7; op2val:0x769a; +op3val:0x7bff; valaddr_reg:x12; val_offset:273*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 273*FLEN/8, x13, x2, x4) + +inst_115: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x123 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x186 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7123; op2val:0x7986; +op3val:0x7bff; valaddr_reg:x12; val_offset:276*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 276*FLEN/8, x13, x2, x4) + +inst_116: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x163 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x022 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7963; op2val:0x7822; +op3val:0x7bff; valaddr_reg:x12; val_offset:279*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 279*FLEN/8, x13, x2, x4) + +inst_117: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x124 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x32c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7924; op2val:0x7b2c; +op3val:0x7bff; valaddr_reg:x12; val_offset:282*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 282*FLEN/8, x13, x2, x4) + +inst_118: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x221 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1fb and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e21; op2val:0x79fb; +op3val:0x7bff; valaddr_reg:x12; val_offset:285*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 285*FLEN/8, x13, x2, x4) + +inst_119: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x022 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x315 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7822; op2val:0x7715; +op3val:0x7bff; valaddr_reg:x12; val_offset:288*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 288*FLEN/8, x13, x2, x4) + +inst_120: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1f3 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x046 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71f3; op2val:0x7446; +op3val:0x7bff; valaddr_reg:x12; val_offset:291*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 291*FLEN/8, x13, x2, x4) + +inst_121: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ae and fs2 == 0 and fe2 == 0x1d and fm2 == 0x108 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78ae; op2val:0x7508; +op3val:0x7bff; valaddr_reg:x12; val_offset:294*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 294*FLEN/8, x13, x2, x4) + +inst_122: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x186 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x39f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7986; op2val:0x7b9f; +op3val:0x7bff; valaddr_reg:x12; val_offset:297*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 297*FLEN/8, x13, x2, x4) + +inst_123: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a3 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x29b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79a3; op2val:0x769b; +op3val:0x7bff; valaddr_reg:x12; val_offset:300*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 300*FLEN/8, x13, x2, x4) + +inst_124: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ac and fs2 == 0 and fe2 == 0x1d and fm2 == 0x045 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78ac; op2val:0x7445; +op3val:0x7bff; valaddr_reg:x12; val_offset:303*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 303*FLEN/8, x13, x2, x4) + +inst_125: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x1ea and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3ab and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x65ea; op2val:0x77ab; +op3val:0x7bff; valaddr_reg:x12; val_offset:306*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 306*FLEN/8, x13, x2, x4) + +inst_126: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x182 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1c3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7182; op2val:0x75c3; +op3val:0x7bff; valaddr_reg:x12; val_offset:309*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 309*FLEN/8, x13, x2, x4) + +inst_127: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x230 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x097 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a30; op2val:0x7097; +op3val:0x7bff; valaddr_reg:x12; val_offset:312*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 312*FLEN/8, x13, x2, x4) + +inst_128: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ab and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0ca and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77ab; op2val:0x78ca; +op3val:0x7bff; valaddr_reg:x12; val_offset:315*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 315*FLEN/8, x13, x2, x4) + +inst_129: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ac and fs2 == 0 and fe2 == 0x1e and fm2 == 0x291 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aac; op2val:0x7a91; +op3val:0x7bff; valaddr_reg:x12; val_offset:318*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 318*FLEN/8, x13, x2, x4) + +inst_130: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3b2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1c3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77b2; op2val:0x79c3; +op3val:0x7bff; valaddr_reg:x12; val_offset:321*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 321*FLEN/8, x13, x2, x4) + +inst_131: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x266 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1dd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7666; op2val:0x79dd; +op3val:0x7bff; valaddr_reg:x12; val_offset:324*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 324*FLEN/8, x13, x2, x4) + +inst_132: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x379 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x357 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7779; op2val:0x7357; +op3val:0x7bff; valaddr_reg:x12; val_offset:327*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 327*FLEN/8, x13, x2, x4) + +inst_133: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1bd and fs2 == 0 and fe2 == 0x1e and fm2 == 0x166 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79bd; op2val:0x7966; +op3val:0x7bff; valaddr_reg:x12; val_offset:330*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 330*FLEN/8, x13, x2, x4) + +inst_134: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d3 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3be and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ad3; op2val:0x73be; +op3val:0x7bff; valaddr_reg:x12; val_offset:333*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 333*FLEN/8, x13, x2, x4) + +inst_135: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x022 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1fc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7422; op2val:0x71fc; +op3val:0x7bff; valaddr_reg:x12; val_offset:336*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 336*FLEN/8, x13, x2, x4) + +inst_136: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2dd and fs2 == 0 and fe2 == 0x1e and fm2 == 0x331 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7add; op2val:0x7b31; +op3val:0x7bff; valaddr_reg:x12; val_offset:339*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 339*FLEN/8, x13, x2, x4) + +inst_137: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ea and fs2 == 0 and fe2 == 0x1d and fm2 == 0x103 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aea; op2val:0x7503; +op3val:0x7bff; valaddr_reg:x12; val_offset:342*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 342*FLEN/8, x13, x2, x4) + +inst_138: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d4 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x17f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79d4; op2val:0x6d7f; +op3val:0x7bff; valaddr_reg:x12; val_offset:345*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 345*FLEN/8, x13, x2, x4) + +inst_139: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ab and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0aa and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aab; op2val:0x74aa; +op3val:0x7bff; valaddr_reg:x12; val_offset:348*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 348*FLEN/8, x13, x2, x4) + +inst_140: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x166 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78a3; op2val:0x7966; +op3val:0x7bff; valaddr_reg:x12; val_offset:351*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 351*FLEN/8, x13, x2, x4) + +inst_141: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x15a and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2f9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x755a; op2val:0x76f9; +op3val:0x7bff; valaddr_reg:x12; val_offset:354*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 354*FLEN/8, x13, x2, x4) + +inst_142: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2b8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0ad and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72b8; op2val:0x78ad; +op3val:0x7bff; valaddr_reg:x12; val_offset:357*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 357*FLEN/8, x13, x2, x4) + +inst_143: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x240 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x05a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7640; op2val:0x785a; +op3val:0x7bff; valaddr_reg:x12; val_offset:360*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 360*FLEN/8, x13, x2, x4) + +inst_144: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x064 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x152 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7464; op2val:0x7952; +op3val:0x7bff; valaddr_reg:x12; val_offset:363*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 363*FLEN/8, x13, x2, x4) + +inst_145: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x318 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x344 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b18; op2val:0x7b44; +op3val:0x7bff; valaddr_reg:x12; val_offset:366*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 366*FLEN/8, x13, x2, x4) + +inst_146: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x386 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1fc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b86; op2val:0x75fc; +op3val:0x7bff; valaddr_reg:x12; val_offset:369*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 369*FLEN/8, x13, x2, x4) + +inst_147: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0b9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a0e; op2val:0x74b9; +op3val:0x7bff; valaddr_reg:x12; val_offset:372*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 372*FLEN/8, x13, x2, x4) + +inst_148: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x13a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x271 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x793a; op2val:0x7a71; +op3val:0x7bff; valaddr_reg:x12; val_offset:375*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 375*FLEN/8, x13, x2, x4) + +inst_149: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x207 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3af and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a07; op2val:0x7baf; +op3val:0x7bff; valaddr_reg:x12; val_offset:378*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 378*FLEN/8, x13, x2, x4) + +inst_150: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x049 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x33f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7849; op2val:0x6f3f; +op3val:0x7bff; valaddr_reg:x12; val_offset:381*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 381*FLEN/8, x13, x2, x4) + +inst_151: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1bd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75a1; op2val:0x79bd; +op3val:0x7bff; valaddr_reg:x12; val_offset:384*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 384*FLEN/8, x13, x2, x4) + +inst_152: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x087 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1d2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7887; op2val:0x71d2; +op3val:0x7bff; valaddr_reg:x12; val_offset:387*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 387*FLEN/8, x13, x2, x4) +RVTEST_SIGBASE(x2,signature_x2_1) + +inst_153: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x10b and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1ba and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x790b; op2val:0x71ba; +op3val:0x7bff; valaddr_reg:x12; val_offset:390*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 390*FLEN/8, x13, x2, x4) + +inst_154: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x13d and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3e0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x793d; op2val:0x6fe0; +op3val:0x7bff; valaddr_reg:x12; val_offset:393*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 393*FLEN/8, x13, x2, x4) + +inst_155: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x085 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x14d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7085; op2val:0x754d; +op3val:0x7bff; valaddr_reg:x12; val_offset:396*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 396*FLEN/8, x13, x2, x4) + +inst_156: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x06f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78c6; op2val:0x786f; +op3val:0x7bff; valaddr_reg:x12; val_offset:399*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 399*FLEN/8, x13, x2, x4) + +inst_157: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x351 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7751; op2val:0x74ff; +op3val:0x7bff; valaddr_reg:x12; val_offset:402*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 402*FLEN/8, x13, x2, x4) + +inst_158: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x063 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1b9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c63; op2val:0x79b9; +op3val:0x7bff; valaddr_reg:x12; val_offset:405*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 405*FLEN/8, x13, x2, x4) + +inst_159: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x057 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1ea and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7857; op2val:0x79ea; +op3val:0x7bff; valaddr_reg:x12; val_offset:408*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 408*FLEN/8, x13, x2, x4) + +inst_160: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x040 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x221 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7440; op2val:0x7621; +op3val:0x7bff; valaddr_reg:x12; val_offset:411*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 411*FLEN/8, x13, x2, x4) + +inst_161: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x163 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x009 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6963; op2val:0x7809; +op3val:0x7bff; valaddr_reg:x12; val_offset:414*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 414*FLEN/8, x13, x2, x4) + +inst_162: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x225 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1a9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a25; op2val:0x75a9; +op3val:0x7bff; valaddr_reg:x12; val_offset:417*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 417*FLEN/8, x13, x2, x4) + +inst_163: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x273 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x054 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7673; op2val:0x7854; +op3val:0x7bff; valaddr_reg:x12; val_offset:420*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 420*FLEN/8, x13, x2, x4) + +inst_164: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75a4; op2val:0x7ac5; +op3val:0x7bff; valaddr_reg:x12; val_offset:423*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 423*FLEN/8, x13, x2, x4) + +inst_165: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x053 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x25f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7453; op2val:0x6e5f; +op3val:0x7bff; valaddr_reg:x12; val_offset:426*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 426*FLEN/8, x13, x2, x4) + +inst_166: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x23a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1d0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a3a; op2val:0x79d0; +op3val:0x7bff; valaddr_reg:x12; val_offset:429*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 429*FLEN/8, x13, x2, x4) + +inst_167: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x20c and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2a9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x720c; op2val:0x76a9; +op3val:0x7bff; valaddr_reg:x12; val_offset:432*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 432*FLEN/8, x13, x2, x4) + +inst_168: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x285 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1fc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a85; op2val:0x79fc; +op3val:0x7bff; valaddr_reg:x12; val_offset:435*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 435*FLEN/8, x13, x2, x4) + +inst_169: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0af and fs2 == 0 and fe2 == 0x1d and fm2 == 0x25f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70af; op2val:0x765f; +op3val:0x7bff; valaddr_reg:x12; val_offset:438*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 438*FLEN/8, x13, x2, x4) + +inst_170: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x037 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x08b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7837; op2val:0x788b; +op3val:0x7bff; valaddr_reg:x12; val_offset:441*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 441*FLEN/8, x13, x2, x4) + +inst_171: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x240 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7400; op2val:0x7a40; +op3val:0x7bff; valaddr_reg:x12; val_offset:444*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 444*FLEN/8, x13, x2, x4) + +inst_172: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x320 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a6c; op2val:0x7b20; +op3val:0x7bff; valaddr_reg:x12; val_offset:447*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 447*FLEN/8, x13, x2, x4) + +inst_173: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x220 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x06b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7620; op2val:0x786b; +op3val:0x7bff; valaddr_reg:x12; val_offset:450*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 450*FLEN/8, x13, x2, x4) + +inst_174: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x111 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3cf and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7911; op2val:0x7bcf; +op3val:0x7bff; valaddr_reg:x12; val_offset:453*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 453*FLEN/8, x13, x2, x4) + +inst_175: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0c9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2e0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74c9; op2val:0x7ae0; +op3val:0x7bff; valaddr_reg:x12; val_offset:456*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 456*FLEN/8, x13, x2, x4) + +inst_176: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ce and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1cf and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78ce; op2val:0x79cf; +op3val:0x7bff; valaddr_reg:x12; val_offset:459*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 459*FLEN/8, x13, x2, x4) + +inst_177: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x229 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x14a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a29; op2val:0x794a; +op3val:0x7bff; valaddr_reg:x12; val_offset:462*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 462*FLEN/8, x13, x2, x4) + +inst_178: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 0 and fe2 == 0x1d and fm2 == 0x35d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x782f; op2val:0x775d; +op3val:0x7bff; valaddr_reg:x12; val_offset:465*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 465*FLEN/8, x13, x2, x4) + +inst_179: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x03b and fs2 == 0 and fe2 == 0x1a and fm2 == 0x0bd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x783b; op2val:0x68bd; +op3val:0x7bff; valaddr_reg:x12; val_offset:468*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 468*FLEN/8, x13, x2, x4) + +inst_180: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12a and fs2 == 0 and fe2 == 0x1d and fm2 == 0x31a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x792a; op2val:0x771a; +op3val:0x7bff; valaddr_reg:x12; val_offset:471*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 471*FLEN/8, x13, x2, x4) + +inst_181: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ab and fs2 == 0 and fe2 == 0x1e and fm2 == 0x322 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bab; op2val:0x7b22; +op3val:0x7bff; valaddr_reg:x12; val_offset:474*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 474*FLEN/8, x13, x2, x4) + +inst_182: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0fb and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a55; op2val:0x78fb; +op3val:0x7bff; valaddr_reg:x12; val_offset:477*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 477*FLEN/8, x13, x2, x4) + +inst_183: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c1 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x377 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c1; op2val:0x7377; +op3val:0x7bff; valaddr_reg:x12; val_offset:480*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 480*FLEN/8, x13, x2, x4) + +inst_184: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x36f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x784f; op2val:0x7b6f; +op3val:0x7bff; valaddr_reg:x12; val_offset:483*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 483*FLEN/8, x13, x2, x4) + +inst_185: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x18d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7af5; op2val:0x798d; +op3val:0x7bff; valaddr_reg:x12; val_offset:486*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 486*FLEN/8, x13, x2, x4) + +inst_186: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2dc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0ce and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7adc; op2val:0x78ce; +op3val:0x7bff; valaddr_reg:x12; val_offset:489*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 489*FLEN/8, x13, x2, x4) + +inst_187: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1ea and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79b9; op2val:0x79ea; +op3val:0x7bff; valaddr_reg:x12; val_offset:492*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 492*FLEN/8, x13, x2, x4) + +inst_188: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x273 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x373 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a73; op2val:0x7b73; +op3val:0x7bff; valaddr_reg:x12; val_offset:495*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 495*FLEN/8, x13, x2, x4) + +inst_189: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2fd and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76fd; op2val:0x7a0d; +op3val:0x7bff; valaddr_reg:x12; val_offset:498*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 498*FLEN/8, x13, x2, x4) + +inst_190: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2fa and fs2 == 0 and fe2 == 0x1a and fm2 == 0x176 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6efa; op2val:0x6976; +op3val:0x7bff; valaddr_reg:x12; val_offset:501*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 501*FLEN/8, x13, x2, x4) + +inst_191: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x268 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x124 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7268; op2val:0x7124; +op3val:0x7bff; valaddr_reg:x12; val_offset:504*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 504*FLEN/8, x13, x2, x4) + +inst_192: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x197 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x04c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7997; op2val:0x784c; +op3val:0x7bff; valaddr_reg:x12; val_offset:507*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 507*FLEN/8, x13, x2, x4) + +inst_193: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x130 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0df and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7930; op2val:0x74df; +op3val:0x7bff; valaddr_reg:x12; val_offset:510*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 510*FLEN/8, x13, x2, x4) + +inst_194: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20d and fs2 == 0 and fe2 == 0x1d and fm2 == 0x26b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a0d; op2val:0x766b; +op3val:0x7bff; valaddr_reg:x12; val_offset:513*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 513*FLEN/8, x13, x2, x4) + +inst_195: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x331 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1c1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b31; op2val:0x79c1; +op3val:0x7bff; valaddr_reg:x12; val_offset:516*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 516*FLEN/8, x13, x2, x4) + +inst_196: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ee and fs2 == 0 and fe2 == 0x1e and fm2 == 0x03b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75ee; op2val:0x783b; +op3val:0x7bff; valaddr_reg:x12; val_offset:519*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 519*FLEN/8, x13, x2, x4) + +inst_197: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x328 and fs2 == 0 and fe2 == 0x16 and fm2 == 0x187 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7328; op2val:0x5987; +op3val:0x7bff; valaddr_reg:x12; val_offset:522*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 522*FLEN/8, x13, x2, x4) + +inst_198: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x243 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x096 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a43; op2val:0x7096; +op3val:0x7bff; valaddr_reg:x12; val_offset:525*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 525*FLEN/8, x13, x2, x4) + +inst_199: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x23f and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2b1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x723f; op2val:0x72b1; +op3val:0x7bff; valaddr_reg:x12; val_offset:528*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 528*FLEN/8, x13, x2, x4) + +inst_200: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x05a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x739c; op2val:0x785a; +op3val:0x7bff; valaddr_reg:x12; val_offset:531*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 531*FLEN/8, x13, x2, x4) + +inst_201: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x37e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3f6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x737e; op2val:0x7bf6; +op3val:0x7bff; valaddr_reg:x12; val_offset:534*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 534*FLEN/8, x13, x2, x4) + +inst_202: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x39e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ab0; op2val:0x779e; +op3val:0x7bff; valaddr_reg:x12; val_offset:537*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 537*FLEN/8, x13, x2, x4) + +inst_203: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1ed and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x782e; op2val:0x79ed; +op3val:0x7bff; valaddr_reg:x12; val_offset:540*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 540*FLEN/8, x13, x2, x4) + +inst_204: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x018 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x210 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c18; op2val:0x7a10; +op3val:0x7bff; valaddr_reg:x12; val_offset:543*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 543*FLEN/8, x13, x2, x4) + +inst_205: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d1 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x3ef and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74d1; op2val:0x67ef; +op3val:0x7bff; valaddr_reg:x12; val_offset:546*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 546*FLEN/8, x13, x2, x4) + +inst_206: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x38f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1bf and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x778f; op2val:0x79bf; +op3val:0x7bff; valaddr_reg:x12; val_offset:549*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 549*FLEN/8, x13, x2, x4) + +inst_207: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x267 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x31c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a67; op2val:0x771c; +op3val:0x7bff; valaddr_reg:x12; val_offset:552*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 552*FLEN/8, x13, x2, x4) + +inst_208: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b5 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2c0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79b5; op2val:0x72c0; +op3val:0x7bff; valaddr_reg:x12; val_offset:555*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x12, 555*FLEN/8, x13, x2, x4) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(30932,32,FLEN) +NAN_BOXED(30976,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(25277,32,FLEN) +NAN_BOXED(31410,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(29566,32,FLEN) +NAN_BOXED(31734,32,FLEN) +NAN_BOXED(29566,32,FLEN) +NAN_BOXED(31408,32,FLEN) +NAN_BOXED(31408,32,FLEN) +NAN_BOXED(31408,32,FLEN) +NAN_BOXED(28881,32,FLEN) +NAN_BOXED(30995,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(30766,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(27672,32,FLEN) +NAN_BOXED(31248,32,FLEN) +NAN_BOXED(27672,32,FLEN) +NAN_BOXED(29905,32,FLEN) +NAN_BOXED(29905,32,FLEN) +NAN_BOXED(29905,32,FLEN) +NAN_BOXED(30607,32,FLEN) +NAN_BOXED(30607,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(31157,32,FLEN) +NAN_BOXED(31581,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(31335,32,FLEN) +NAN_BOXED(30492,32,FLEN) +NAN_BOXED(30492,32,FLEN) +test_dataset_1: +NAN_BOXED(31495,32,FLEN) +NAN_BOXED(28219,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(29424,32,FLEN) +NAN_BOXED(31672,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(30978,32,FLEN) +NAN_BOXED(29904,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(30251,32,FLEN) +NAN_BOXED(30108,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(30891,32,FLEN) +NAN_BOXED(31546,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(31597,32,FLEN) +NAN_BOXED(31449,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(31070,32,FLEN) +NAN_BOXED(28983,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(31670,32,FLEN) +NAN_BOXED(31547,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(29376,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(30870,32,FLEN) +NAN_BOXED(29838,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(31444,32,FLEN) +NAN_BOXED(31722,32,FLEN) +NAN_BOXED(31743,32,FLEN) +test_dataset_2: +NAN_BOXED(31334,16,FLEN) +NAN_BOXED(30352,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29875,16,FLEN) +NAN_BOXED(31269,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(27047,16,FLEN) +NAN_BOXED(30953,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31166,16,FLEN) +NAN_BOXED(30026,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31703,16,FLEN) +NAN_BOXED(30730,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29939,16,FLEN) +NAN_BOXED(27884,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(26627,16,FLEN) +NAN_BOXED(29264,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30945,16,FLEN) +NAN_BOXED(28926,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31472,16,FLEN) +NAN_BOXED(29956,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31531,16,FLEN) +NAN_BOXED(30218,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30760,16,FLEN) +NAN_BOXED(31014,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30840,16,FLEN) +NAN_BOXED(30965,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30733,16,FLEN) +NAN_BOXED(30437,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29593,16,FLEN) +NAN_BOXED(29904,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30762,16,FLEN) +NAN_BOXED(30818,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30371,16,FLEN) +NAN_BOXED(30883,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30956,16,FLEN) +NAN_BOXED(30990,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30980,16,FLEN) +NAN_BOXED(30580,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30115,16,FLEN) +NAN_BOXED(31143,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(26029,16,FLEN) +NAN_BOXED(27584,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31667,16,FLEN) +NAN_BOXED(29700,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30909,16,FLEN) +NAN_BOXED(29982,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29952,16,FLEN) +NAN_BOXED(30183,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29901,16,FLEN) +NAN_BOXED(30216,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(26339,16,FLEN) +NAN_BOXED(30861,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29941,16,FLEN) +NAN_BOXED(29470,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29602,16,FLEN) +NAN_BOXED(29182,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31124,16,FLEN) +NAN_BOXED(28291,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30038,16,FLEN) +NAN_BOXED(31402,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31447,16,FLEN) +NAN_BOXED(29034,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31027,16,FLEN) +NAN_BOXED(31507,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29490,16,FLEN) +NAN_BOXED(28604,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29210,16,FLEN) +NAN_BOXED(31347,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29151,16,FLEN) +NAN_BOXED(29812,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31010,16,FLEN) +NAN_BOXED(31346,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(28709,16,FLEN) +NAN_BOXED(29867,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29782,16,FLEN) +NAN_BOXED(30089,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30390,16,FLEN) +NAN_BOXED(30348,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(28925,16,FLEN) +NAN_BOXED(23749,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31497,16,FLEN) +NAN_BOXED(31716,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31640,16,FLEN) +NAN_BOXED(31594,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31222,16,FLEN) +NAN_BOXED(31408,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30758,16,FLEN) +NAN_BOXED(29855,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29510,16,FLEN) +NAN_BOXED(27738,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29847,16,FLEN) +NAN_BOXED(31354,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31545,16,FLEN) +NAN_BOXED(31116,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31531,16,FLEN) +NAN_BOXED(31537,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(25274,16,FLEN) +NAN_BOXED(31221,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29899,16,FLEN) +NAN_BOXED(31052,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30365,16,FLEN) +NAN_BOXED(31618,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30069,16,FLEN) +NAN_BOXED(29705,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30625,16,FLEN) +NAN_BOXED(31297,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29263,16,FLEN) +NAN_BOXED(30790,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29050,16,FLEN) +NAN_BOXED(31316,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31345,16,FLEN) +NAN_BOXED(31381,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30982,16,FLEN) +NAN_BOXED(31461,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29783,16,FLEN) +NAN_BOXED(29771,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30403,16,FLEN) +NAN_BOXED(30608,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(22375,16,FLEN) +NAN_BOXED(27395,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(28664,16,FLEN) +NAN_BOXED(27744,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31445,16,FLEN) +NAN_BOXED(28034,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29965,16,FLEN) +NAN_BOXED(29959,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31020,16,FLEN) +NAN_BOXED(30896,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29212,16,FLEN) +NAN_BOXED(30018,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30833,16,FLEN) +NAN_BOXED(31161,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(27932,16,FLEN) +NAN_BOXED(29110,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30933,16,FLEN) +NAN_BOXED(31298,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31335,16,FLEN) +NAN_BOXED(30971,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30196,16,FLEN) +NAN_BOXED(30703,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30393,16,FLEN) +NAN_BOXED(31116,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29654,16,FLEN) +NAN_BOXED(30792,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(27796,16,FLEN) +NAN_BOXED(30411,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31496,16,FLEN) +NAN_BOXED(31612,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31533,16,FLEN) +NAN_BOXED(31315,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30572,16,FLEN) +NAN_BOXED(28640,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31051,16,FLEN) +NAN_BOXED(31512,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31062,16,FLEN) +NAN_BOXED(31197,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(28312,16,FLEN) +NAN_BOXED(30899,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(28823,16,FLEN) +NAN_BOXED(31281,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(28127,16,FLEN) +NAN_BOXED(28250,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29114,16,FLEN) +NAN_BOXED(26114,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(28610,16,FLEN) +NAN_BOXED(31423,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31407,16,FLEN) +NAN_BOXED(31645,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31331,16,FLEN) +NAN_BOXED(26787,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30742,16,FLEN) +NAN_BOXED(31159,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31229,16,FLEN) +NAN_BOXED(31609,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29999,16,FLEN) +NAN_BOXED(30850,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29630,16,FLEN) +NAN_BOXED(29119,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30956,16,FLEN) +NAN_BOXED(31238,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30176,16,FLEN) +NAN_BOXED(30295,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30384,16,FLEN) +NAN_BOXED(27987,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31687,16,FLEN) +NAN_BOXED(30362,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(28963,16,FLEN) +NAN_BOXED(31110,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31075,16,FLEN) +NAN_BOXED(30754,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31012,16,FLEN) +NAN_BOXED(31532,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(28193,16,FLEN) +NAN_BOXED(31227,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30754,16,FLEN) +NAN_BOXED(30485,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29171,16,FLEN) +NAN_BOXED(29766,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30894,16,FLEN) +NAN_BOXED(29960,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31110,16,FLEN) +NAN_BOXED(31647,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31139,16,FLEN) +NAN_BOXED(30363,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30892,16,FLEN) +NAN_BOXED(29765,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(26090,16,FLEN) +NAN_BOXED(30635,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29058,16,FLEN) +NAN_BOXED(30147,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31280,16,FLEN) +NAN_BOXED(28823,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30635,16,FLEN) +NAN_BOXED(30922,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31404,16,FLEN) +NAN_BOXED(31377,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30642,16,FLEN) +NAN_BOXED(31171,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30310,16,FLEN) +NAN_BOXED(31197,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30585,16,FLEN) +NAN_BOXED(29527,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31165,16,FLEN) +NAN_BOXED(31078,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31443,16,FLEN) +NAN_BOXED(29630,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29730,16,FLEN) +NAN_BOXED(29180,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31453,16,FLEN) +NAN_BOXED(31537,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31466,16,FLEN) +NAN_BOXED(29955,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31188,16,FLEN) +NAN_BOXED(28031,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31403,16,FLEN) +NAN_BOXED(29866,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30883,16,FLEN) +NAN_BOXED(31078,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30042,16,FLEN) +NAN_BOXED(30457,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29368,16,FLEN) +NAN_BOXED(30893,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30272,16,FLEN) +NAN_BOXED(30810,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29796,16,FLEN) +NAN_BOXED(31058,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31512,16,FLEN) +NAN_BOXED(31556,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31622,16,FLEN) +NAN_BOXED(30204,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31246,16,FLEN) +NAN_BOXED(29881,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31034,16,FLEN) +NAN_BOXED(31345,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31239,16,FLEN) +NAN_BOXED(31663,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30793,16,FLEN) +NAN_BOXED(28479,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30113,16,FLEN) +NAN_BOXED(31165,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30855,16,FLEN) +NAN_BOXED(29138,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30987,16,FLEN) +NAN_BOXED(29114,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31037,16,FLEN) +NAN_BOXED(28640,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(28805,16,FLEN) +NAN_BOXED(30029,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30918,16,FLEN) +NAN_BOXED(30831,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30545,16,FLEN) +NAN_BOXED(29951,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(27747,16,FLEN) +NAN_BOXED(31161,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30807,16,FLEN) +NAN_BOXED(31210,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29760,16,FLEN) +NAN_BOXED(30241,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(26979,16,FLEN) +NAN_BOXED(30729,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31269,16,FLEN) +NAN_BOXED(30121,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30323,16,FLEN) +NAN_BOXED(30804,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30116,16,FLEN) +NAN_BOXED(31429,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29779,16,FLEN) +NAN_BOXED(28255,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31290,16,FLEN) +NAN_BOXED(31184,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29196,16,FLEN) +NAN_BOXED(30377,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31365,16,FLEN) +NAN_BOXED(31228,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(28847,16,FLEN) +NAN_BOXED(30303,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30775,16,FLEN) +NAN_BOXED(30859,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29696,16,FLEN) +NAN_BOXED(31296,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31340,16,FLEN) +NAN_BOXED(31520,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30240,16,FLEN) +NAN_BOXED(30827,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30993,16,FLEN) +NAN_BOXED(31695,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29897,16,FLEN) +NAN_BOXED(31456,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30926,16,FLEN) +NAN_BOXED(31183,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31273,16,FLEN) +NAN_BOXED(31050,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30767,16,FLEN) +NAN_BOXED(30557,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30779,16,FLEN) +NAN_BOXED(26813,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31018,16,FLEN) +NAN_BOXED(30490,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31659,16,FLEN) +NAN_BOXED(31522,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31317,16,FLEN) +NAN_BOXED(30971,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30145,16,FLEN) +NAN_BOXED(29559,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30799,16,FLEN) +NAN_BOXED(31599,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31477,16,FLEN) +NAN_BOXED(31117,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31452,16,FLEN) +NAN_BOXED(30926,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31161,16,FLEN) +NAN_BOXED(31210,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31347,16,FLEN) +NAN_BOXED(31603,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30461,16,FLEN) +NAN_BOXED(31245,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(28410,16,FLEN) +NAN_BOXED(26998,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29288,16,FLEN) +NAN_BOXED(28964,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31127,16,FLEN) +NAN_BOXED(30796,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31024,16,FLEN) +NAN_BOXED(29919,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31245,16,FLEN) +NAN_BOXED(30315,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31537,16,FLEN) +NAN_BOXED(31169,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30190,16,FLEN) +NAN_BOXED(30779,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29480,16,FLEN) +NAN_BOXED(22919,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31299,16,FLEN) +NAN_BOXED(28822,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29247,16,FLEN) +NAN_BOXED(29361,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29596,16,FLEN) +NAN_BOXED(30810,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29566,16,FLEN) +NAN_BOXED(31734,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31408,16,FLEN) +NAN_BOXED(30622,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30766,16,FLEN) +NAN_BOXED(31213,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(27672,16,FLEN) +NAN_BOXED(31248,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29905,16,FLEN) +NAN_BOXED(26607,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30607,16,FLEN) +NAN_BOXED(31167,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31335,16,FLEN) +NAN_BOXED(30492,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31157,16,FLEN) +NAN_BOXED(29376,16,FLEN) +NAN_BOXED(31743,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 26*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x3_0: + .fill 24*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_0: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_1: + .fill 112*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fnmsub_b18-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fnmsub_b18-01.S new file mode 100644 index 000000000..42ca86873 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fnmsub_b18-01.S @@ -0,0 +1,3049 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 06:07:02 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fnmsub.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fnmsub.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fnmsub_b18 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fnmsub_b18) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x14,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==x23, rs2==x23, rs3==x29, rd==x8,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x23; op2:x23; op3:x29; dest:x8; op1val:0x739c; op2val:0x739c; +op3val:0x7bff; valaddr_reg:x14; val_offset:0*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x8, x23, x23, x29, dyn, 0, 0, x14, 0*FLEN/8, x22, x1, x10) + +inst_1: +// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==x3, rs2==x6, rs3==x28, rd==x3,fs1 == 0 and fe1 == 0x1e and fm1 == 0x05a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x3; op2:x6; op3:x28; dest:x3; op1val:0x785a; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x14; val_offset:3*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x3, x3, x6, x28, dyn, 0, 0, x14, 3*FLEN/8, x22, x1, x10) + +inst_2: +// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==x15, rs2==x12, rs3==x20, rd==x21,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ea and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x15; op2:x12; op3:x20; dest:x21; op1val:0x75ea; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x14; val_offset:6*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x21, x15, x12, x20, dyn, 0, 0, x14, 6*FLEN/8, x22, x1, x10) + +inst_3: +// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==x21, rs2==x17, rs3==x21, rd==x5,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x21; op2:x17; op3:x21; dest:x5; op1val:0x78d4; op2val:0x8000; +op3val:0x78d4; valaddr_reg:x14; val_offset:9*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x5, x21, x17, x21, dyn, 0, 0, x14, 9*FLEN/8, x22, x1, x10) + +inst_4: +// rs1 == rs2 == rs3 != rd, rs1==x4, rs2==x4, rs3==x4, rd==x12,fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x4; op2:x4; op3:x4; dest:x12; op1val:0x7900; op2val:0x7900; +op3val:0x7900; valaddr_reg:x14; val_offset:12*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x12, x4, x4, x4, dyn, 0, 0, x14, 12*FLEN/8, x22, x1, x10) + +inst_5: +// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==x5, rs2==x16, rs3==x26, rd==x26,fs1 == 0 and fe1 == 0x1b and fm1 == 0x031 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x5; op2:x16; op3:x26; dest:x26; op1val:0x6c31; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x14; val_offset:15*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x26, x5, x16, x26, dyn, 0, 0, x14, 15*FLEN/8, x22, x1, x10) + +inst_6: +// rd == rs2 == rs3 != rs1, rs1==x13, rs2==x2, rs3==x2, rd==x2,fs1 == 0 and fe1 == 0x18 and fm1 == 0x2bf and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x13; op2:x2; op3:x2; dest:x2; op1val:0x62bf; op2val:0x8000; +op3val:0x8000; valaddr_reg:x14; val_offset:18*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x2, x13, x2, x2, dyn, 0, 0, x14, 18*FLEN/8, x22, x1, x10) + +inst_7: +// rs1 == rd == rs3 != rs2, rs1==x30, rs2==x13, rs3==x30, rd==x30,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x13; op3:x30; dest:x30; op1val:0x7ab2; op2val:0x0; +op3val:0x7ab2; valaddr_reg:x14; val_offset:21*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x30, x30, x13, x30, dyn, 0, 0, x14, 21*FLEN/8, x22, x1, x10) + +inst_8: +// rs1 == rs2 == rs3 == rd, rs1==x7, rs2==x7, rs3==x7, rd==x7,fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x7; op2:x7; op3:x7; dest:x7; op1val:0x7425; op2val:0x7425; +op3val:0x7425; valaddr_reg:x14; val_offset:24*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x7, x7, x7, x7, dyn, 0, 0, x14, 24*FLEN/8, x22, x1, x10) + +inst_9: +// rs1 == rs2 == rd != rs3, rs1==x9, rs2==x9, rs3==x27, rd==x9,fs1 == 0 and fe1 == 0x1c and fm1 == 0x37e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x9; op2:x9; op3:x27; dest:x9; op1val:0x737e; op2val:0x737e; +op3val:0x7bff; valaddr_reg:x14; val_offset:27*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x9, x9, x9, x27, dyn, 0, 0, x14, 27*FLEN/8, x22, x1, x10) + +inst_10: +// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==x11, rs2==x28, rs3==x6, rd==x28,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x11; op2:x28; op3:x6; dest:x28; op1val:0x7bf6; op2val:0x0; +op3val:0x7bff; valaddr_reg:x14; val_offset:30*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x28, x11, x28, x6, dyn, 0, 0, x14, 30*FLEN/8, x22, x1, x10) + +inst_11: +// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==x16, rs2==x19, rs3==x19, rd==x13,fs1 == 0 and fe1 == 0x1d and fm1 == 0x385 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x16; op2:x19; op3:x19; dest:x13; op1val:0x7785; op2val:0x0; +op3val:0x0; valaddr_reg:x14; val_offset:33*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x13, x16, x19, x19, dyn, 0, 0, x14, 33*FLEN/8, x22, x1, x10) + +inst_12: +// rs1==x6, rs2==x25, rs3==x8, rd==x19,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x6; op2:x25; op3:x8; dest:x19; op1val:0x7ab0; op2val:0x0; +op3val:0x7bff; valaddr_reg:x14; val_offset:36*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x19, x6, x25, x8, dyn, 0, 0, x14, 36*FLEN/8, x22, x1, x10) + +inst_13: +// rs1==x20, rs2==x18, rs3==x22, rd==x4,fs1 == 0 and fe1 == 0x1d and fm1 == 0x39e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x20; op2:x18; op3:x22; dest:x4; op1val:0x779e; op2val:0x0; +op3val:0x7bff; valaddr_reg:x14; val_offset:39*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x4, x20, x18, x22, dyn, 0, 0, x14, 39*FLEN/8, x22, x1, x10) +RVTEST_VALBASEUPD(x7,test_dataset_1) + +inst_14: +// rs1==x2, rs2==x26, rs3==x23, rd==x20,fs1 == 0 and fe1 == 0x1e and fm1 == 0x11c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x2; op2:x26; op3:x23; dest:x20; op1val:0x791c; op2val:0x0; +op3val:0x7bff; valaddr_reg:x7; val_offset:0*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x20, x2, x26, x23, dyn, 0, 0, x7, 0*FLEN/8, x8, x1, x10) + +inst_15: +// rs1==x29, rs2==x20, rs3==x14, rd==x6,fs1 == 0 and fe1 == 0x1c and fm1 == 0x0d1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x29; op2:x20; op3:x14; dest:x6; op1val:0x70d1; op2val:0x0; +op3val:0x7bff; valaddr_reg:x7; val_offset:3*FLEN/8; rmval:dyn; +testreg:x10; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x6, x29, x20, x14, dyn, 0, 0, x7, 3*FLEN/8, x8, x1, x10) + +inst_16: +// rs1==x19, rs2==x5, rs3==x25, rd==x10,fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x19; op2:x5; op3:x25; dest:x10; op1val:0x7913; op2val:0x0; +op3val:0x7bff; valaddr_reg:x7; val_offset:6*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x10, x19, x5, x25, dyn, 0, 0, x7, 6*FLEN/8, x8, x1, x4) +RVTEST_SIGBASE(x2,signature_x2_0) + +inst_17: +// rs1==x27, rs2==x10, rs3==x31, rd==x17,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x27; op2:x10; op3:x31; dest:x17; op1val:0x7af0; op2val:0x0; +op3val:0x7bff; valaddr_reg:x7; val_offset:9*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x17, x27, x10, x31, dyn, 0, 0, x7, 9*FLEN/8, x8, x2, x4) + +inst_18: +// rs1==x22, rs2==x24, rs3==x12, rd==x23,fs1 == 0 and fe1 == 0x1e and fm1 == 0x02e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x22; op2:x24; op3:x12; dest:x23; op1val:0x782e; op2val:0x0; +op3val:0x7bff; valaddr_reg:x7; val_offset:12*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x23, x22, x24, x12, dyn, 0, 0, x7, 12*FLEN/8, x8, x2, x4) + +inst_19: +// rs1==x28, rs2==x0, rs3==x5, rd==x29,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x28; op2:x0; op3:x5; dest:x29; op1val:0x79ed; op2val:0x0; +op3val:0x7bff; valaddr_reg:x7; val_offset:15*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x29, x28, x0, x5, dyn, 0, 0, x7, 15*FLEN/8, x8, x2, x4) + +inst_20: +// rs1==x24, rs2==x30, rs3==x13, rd==x27,fs1 == 0 and fe1 == 0x1e and fm1 == 0x15e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x24; op2:x30; op3:x13; dest:x27; op1val:0x795e; op2val:0x0; +op3val:0x7bff; valaddr_reg:x7; val_offset:18*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x27, x24, x30, x13, dyn, 0, 0, x7, 18*FLEN/8, x8, x2, x4) + +inst_21: +// rs1==x14, rs2==x22, rs3==x16, rd==x1,fs1 == 0 and fe1 == 0x1b and fm1 == 0x018 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x14; op2:x22; op3:x16; dest:x1; op1val:0x6c18; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x7; val_offset:21*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x1, x14, x22, x16, dyn, 0, 0, x7, 21*FLEN/8, x8, x2, x4) + +inst_22: +// rs1==x26, rs2==x27, rs3==x0, rd==x16,fs1 == 0 and fe1 == 0x1e and fm1 == 0x210 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x26; op2:x27; op3:x0; dest:x16; op1val:0x7a10; op2val:0x8000; +op3val:0x0; valaddr_reg:x7; val_offset:24*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x16, x26, x27, x0, dyn, 0, 0, x7, 24*FLEN/8, x8, x2, x4) + +inst_23: +// rs1==x0, rs2==x21, rs3==x10, rd==x25,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x0; op2:x21; op3:x10; dest:x25; op1val:0x0; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x7; val_offset:27*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x25, x0, x21, x10, dyn, 0, 0, x7, 27*FLEN/8, x8, x2, x4) + +inst_24: +// rs1==x10, rs2==x3, rs3==x1, rd==x11,fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x10; op2:x3; op3:x1; dest:x11; op1val:0x74d1; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x7; val_offset:30*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x11, x10, x3, x1, dyn, 0, 0, x7, 30*FLEN/8, x8, x2, x4) + +inst_25: +// rs1==x17, rs2==x15, rs3==x11, rd==x0,fs1 == 0 and fe1 == 0x19 and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x17; op2:x15; op3:x11; dest:x0; op1val:0x67f0; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x7; val_offset:33*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x0, x17, x15, x11, dyn, 0, 0, x7, 33*FLEN/8, x8, x2, x4) +RVTEST_VALBASEUPD(x5,test_dataset_2) + +inst_26: +// rs1==x8, rs2==x11, rs3==x9, rd==x18,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x8; op2:x11; op3:x9; dest:x18; op1val:0x7aeb; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:0*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x18, x8, x11, x9, dyn, 0, 0, x5, 0*FLEN/8, x6, x2, x4) + +inst_27: +// rs1==x31, rs2==x14, rs3==x18, rd==x24,fs1 == 0 and fe1 == 0x1d and fm1 == 0x38f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x31; op2:x14; op3:x18; dest:x24; op1val:0x778f; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:3*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x24, x31, x14, x18, dyn, 0, 0, x5, 3*FLEN/8, x6, x2, x4) + +inst_28: +// rs1==x12, rs2==x29, rs3==x24, rd==x31,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1bf and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x12; op2:x29; op3:x24; dest:x31; op1val:0x79bf; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:6*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x12, x29, x24, dyn, 0, 0, x5, 6*FLEN/8, x6, x2, x4) + +inst_29: +// rs1==x25, rs2==x1, rs3==x3, rd==x22,fs1 == 0 and fe1 == 0x1e and fm1 == 0x306 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x25; op2:x1; op3:x3; dest:x22; op1val:0x7b06; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:9*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x22, x25, x1, x3, dyn, 0, 0, x5, 9*FLEN/8, x6, x2, x3) + +inst_30: +// rs1==x1, rs2==x31, rs3==x15, rd==x14,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x1; op2:x31; op3:x15; dest:x14; op1val:0x79b5; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:12*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x14, x1, x31, x15, dyn, 0, 0, x5, 12*FLEN/8, x6, x2, x3) + +inst_31: +// rs1==x18, rs2==x8, rs3==x17, rd==x15,fs1 == 0 and fe1 == 0x1e and fm1 == 0x35d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x18; op2:x8; op3:x17; dest:x15; op1val:0x7b5d; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:15*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x15, x18, x8, x17, dyn, 0, 0, x5, 15*FLEN/8, x6, x2, x3) + +inst_32: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x251 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7651; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:18*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 18*FLEN/8, x6, x2, x3) + +inst_33: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x267 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a67; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:21*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 21*FLEN/8, x6, x2, x3) + +inst_34: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x771c; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:24*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 24*FLEN/8, x6, x2, x3) + +inst_35: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b7b; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:27*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 27*FLEN/8, x6, x2, x3) + +inst_36: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x307 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b07; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:30*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 30*FLEN/8, x6, x2, x3) + +inst_37: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x23c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e3c; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:33*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 33*FLEN/8, x6, x2, x3) + +inst_38: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x059 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7059; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:36*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 36*FLEN/8, x6, x2, x3) + +inst_39: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72f0; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:39*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 39*FLEN/8, x6, x2, x3) + +inst_40: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bb8; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:42*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 42*FLEN/8, x6, x2, x3) + +inst_41: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2f9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76f9; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:45*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 45*FLEN/8, x6, x2, x3) + +inst_42: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x102 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7902; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:48*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 48*FLEN/8, x6, x2, x3) + +inst_43: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74d0; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:51*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 51*FLEN/8, x6, x2, x3) + +inst_44: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x780e; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:54*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 54*FLEN/8, x6, x2, x3) + +inst_45: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x22b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x762b; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:57*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 57*FLEN/8, x6, x2, x3) + +inst_46: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x19c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x759c; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:60*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 60*FLEN/8, x6, x2, x3) + +inst_47: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ad and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78ad; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:63*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 63*FLEN/8, x6, x2, x3) + +inst_48: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ab and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78ab; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:66*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 66*FLEN/8, x6, x2, x3) + +inst_49: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x33a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b3a; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:69*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 69*FLEN/8, x6, x2, x3) + +inst_50: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x174 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7974; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:72*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 72*FLEN/8, x6, x2, x3) + +inst_51: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x36d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b6d; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:75*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 75*FLEN/8, x6, x2, x3) + +inst_52: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ad9; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:78*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 78*FLEN/8, x6, x2, x3) + +inst_53: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ec and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bec; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:81*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 81*FLEN/8, x6, x2, x3) + +inst_54: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x795e; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:84*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 84*FLEN/8, x6, x2, x3) + +inst_55: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x137 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7137; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:87*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 87*FLEN/8, x6, x2, x3) + +inst_56: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ae1; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:90*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 90*FLEN/8, x6, x2, x3) + +inst_57: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bb6; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:93*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 93*FLEN/8, x6, x2, x3) + +inst_58: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x33b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b3b; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:96*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 96*FLEN/8, x6, x2, x3) + +inst_59: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x08c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x788c; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:99*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 99*FLEN/8, x6, x2, x3) + +inst_60: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2c0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72c0; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:102*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 102*FLEN/8, x6, x2, x3) + +inst_61: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aa6; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:105*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 105*FLEN/8, x6, x2, x3) + +inst_62: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x096 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7896; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:108*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 108*FLEN/8, x6, x2, x3) + +inst_63: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x08e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x748e; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:111*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 111*FLEN/8, x6, x2, x3) + +inst_64: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x00f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c0f; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:114*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 114*FLEN/8, x6, x2, x3) + +inst_65: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ad4; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:117*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 117*FLEN/8, x6, x2, x3) + +inst_66: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bea; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:120*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 120*FLEN/8, x6, x2, x3) + +inst_67: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6da9; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:123*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 123*FLEN/8, x6, x2, x3) + +inst_68: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x266 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a66; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:126*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 126*FLEN/8, x6, x2, x3) + +inst_69: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x290 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7690; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:129*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 129*FLEN/8, x6, x2, x3) + +inst_70: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0d2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70d2; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:132*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 132*FLEN/8, x6, x2, x3) + +inst_71: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0b3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74b3; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:135*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 135*FLEN/8, x6, x2, x3) + +inst_72: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x225 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a25; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:138*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 138*FLEN/8, x6, x2, x3) + +inst_73: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2fa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7afa; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:141*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 141*FLEN/8, x6, x2, x3) + +inst_74: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x1a7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x69a7; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:144*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 144*FLEN/8, x6, x2, x3) + +inst_75: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e9; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:147*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 147*FLEN/8, x6, x2, x3) + +inst_76: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x1c0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x69c0; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:150*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 150*FLEN/8, x6, x2, x3) + +inst_77: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1be and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79be; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:153*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 153*FLEN/8, x6, x2, x3) + +inst_78: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x14a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x754a; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:156*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 156*FLEN/8, x6, x2, x3) + +inst_79: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b0b; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:159*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 159*FLEN/8, x6, x2, x3) + +inst_80: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd7; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:162*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 162*FLEN/8, x6, x2, x3) + +inst_81: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x780a; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:165*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 165*FLEN/8, x6, x2, x3) + +inst_82: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3fb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bfb; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:168*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 168*FLEN/8, x6, x2, x3) + +inst_83: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74f3; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:171*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 171*FLEN/8, x6, x2, x3) + +inst_84: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0ec and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6cec; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:174*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 174*FLEN/8, x6, x2, x3) + +inst_85: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0cb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78cb; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:177*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 177*FLEN/8, x6, x2, x3) + +inst_86: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x004 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6804; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:180*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 180*FLEN/8, x6, x2, x3) + +inst_87: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x250 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7250; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:183*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 183*FLEN/8, x6, x2, x3) + +inst_88: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x286 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7686; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:186*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 186*FLEN/8, x6, x2, x3) + +inst_89: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e1; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:189*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 189*FLEN/8, x6, x2, x3) + +inst_90: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70ff; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:192*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 192*FLEN/8, x6, x2, x3) + +inst_91: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x696e; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:195*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 195*FLEN/8, x6, x2, x3) + +inst_92: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x104 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7504; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:198*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 198*FLEN/8, x6, x2, x3) + +inst_93: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7baa; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:201*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 201*FLEN/8, x6, x2, x3) + +inst_94: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b2b; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:204*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 204*FLEN/8, x6, x2, x3) + +inst_95: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x20a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x760a; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:207*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 207*FLEN/8, x6, x2, x3) + +inst_96: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x35c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x775c; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:210*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 210*FLEN/8, x6, x2, x3) + +inst_97: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x028 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7828; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:213*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 213*FLEN/8, x6, x2, x3) + +inst_98: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x126 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7926; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:216*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 216*FLEN/8, x6, x2, x3) + +inst_99: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78c3; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:219*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 219*FLEN/8, x6, x2, x3) + +inst_100: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x078 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7878; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:222*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 222*FLEN/8, x6, x2, x3) + +inst_101: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78f5; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:225*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 225*FLEN/8, x6, x2, x3) + +inst_102: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x385 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b85; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:228*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 228*FLEN/8, x6, x2, x3) + +inst_103: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x780d; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:231*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 231*FLEN/8, x6, x2, x3) + +inst_104: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76e5; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:234*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 234*FLEN/8, x6, x2, x3) + +inst_105: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79c2; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:237*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 237*FLEN/8, x6, x2, x3) + +inst_106: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x399 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7399; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:240*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 240*FLEN/8, x6, x2, x3) + +inst_107: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74d0; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:243*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 243*FLEN/8, x6, x2, x3) + +inst_108: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd1; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:246*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 246*FLEN/8, x6, x2, x3) + +inst_109: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x782a; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:249*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 249*FLEN/8, x6, x2, x3) + +inst_110: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x062 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7862; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:252*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 252*FLEN/8, x6, x2, x3) + +inst_111: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x1de and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x61de; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:255*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 255*FLEN/8, x6, x2, x3) + +inst_112: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76a3; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:258*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 258*FLEN/8, x6, x2, x3) + +inst_113: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78a3; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:261*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 261*FLEN/8, x6, x2, x3) + +inst_114: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x122 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6522; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:264*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 264*FLEN/8, x6, x2, x3) + +inst_115: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ec and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78ec; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:267*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 267*FLEN/8, x6, x2, x3) + +inst_116: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x10e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x790e; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:270*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 270*FLEN/8, x6, x2, x3) + +inst_117: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3b0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6bb0; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:273*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 273*FLEN/8, x6, x2, x3) + +inst_118: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x104 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7904; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:276*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 276*FLEN/8, x6, x2, x3) + +inst_119: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x374 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7774; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:279*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 279*FLEN/8, x6, x2, x3) + +inst_120: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x16e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x796e; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:282*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 282*FLEN/8, x6, x2, x3) + +inst_121: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75a3; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:285*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 285*FLEN/8, x6, x2, x3) + +inst_122: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79a7; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:288*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 288*FLEN/8, x6, x2, x3) + +inst_123: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1e6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79e6; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:291*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 291*FLEN/8, x6, x2, x3) + +inst_124: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x1ae and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x65ae; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:294*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 294*FLEN/8, x6, x2, x3) + +inst_125: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6bc0; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:297*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 297*FLEN/8, x6, x2, x3) + +inst_126: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x167 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7967; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:300*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 300*FLEN/8, x6, x2, x3) + +inst_127: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bb3; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:303*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 303*FLEN/8, x6, x2, x3) + +inst_128: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x004 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7404; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:306*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 306*FLEN/8, x6, x2, x3) + +inst_129: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x34c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x774c; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:309*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 309*FLEN/8, x6, x2, x3) + +inst_130: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0bd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78bd; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:312*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 312*FLEN/8, x6, x2, x3) + +inst_131: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x11e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x751e; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:315*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 315*FLEN/8, x6, x2, x3) + +inst_132: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1d2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75d2; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:318*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 318*FLEN/8, x6, x2, x3) + +inst_133: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x100 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7500; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:321*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 321*FLEN/8, x6, x2, x3) + +inst_134: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1e7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75e7; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:324*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 324*FLEN/8, x6, x2, x3) + +inst_135: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78c3; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:327*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 327*FLEN/8, x6, x2, x3) + +inst_136: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0cd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74cd; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:330*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 330*FLEN/8, x6, x2, x3) + +inst_137: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x208 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7608; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:333*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 333*FLEN/8, x6, x2, x3) + +inst_138: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x22c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a2c; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:336*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 336*FLEN/8, x6, x2, x3) + +inst_139: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x2e4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x66e4; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:339*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 339*FLEN/8, x6, x2, x3) + +inst_140: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x08d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x788d; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:342*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 342*FLEN/8, x6, x2, x3) + +inst_141: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1e0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79e0; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:345*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 345*FLEN/8, x6, x2, x3) + +inst_142: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74f5; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:348*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 348*FLEN/8, x6, x2, x3) + +inst_143: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x31e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x731e; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:351*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 351*FLEN/8, x6, x2, x3) + +inst_144: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a6d; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:354*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 354*FLEN/8, x6, x2, x3) +RVTEST_SIGBASE(x2,signature_x2_1) + +inst_145: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3a2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73a2; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:357*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 357*FLEN/8, x6, x2, x3) + +inst_146: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71fe; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:360*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 360*FLEN/8, x6, x2, x3) + +inst_147: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76f5; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:363*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 363*FLEN/8, x6, x2, x3) + +inst_148: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x194 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7994; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:366*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 366*FLEN/8, x6, x2, x3) + +inst_149: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x283 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e83; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:369*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 369*FLEN/8, x6, x2, x3) + +inst_150: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x126 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7526; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:372*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 372*FLEN/8, x6, x2, x3) + +inst_151: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x156 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7556; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:375*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 375*FLEN/8, x6, x2, x3) + +inst_152: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aaa; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:378*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 378*FLEN/8, x6, x2, x3) + +inst_153: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x302 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7702; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:381*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 381*FLEN/8, x6, x2, x3) + +inst_154: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ad7; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:384*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 384*FLEN/8, x6, x2, x3) + +inst_155: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x16a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x716a; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:387*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 387*FLEN/8, x6, x2, x3) + +inst_156: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x162 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7562; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:390*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 390*FLEN/8, x6, x2, x3) + +inst_157: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x133 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7933; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:393*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 393*FLEN/8, x6, x2, x3) + +inst_158: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x313 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b13; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:396*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 396*FLEN/8, x6, x2, x3) + +inst_159: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x336 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7736; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:399*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 399*FLEN/8, x6, x2, x3) + +inst_160: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x332 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7332; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:402*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 402*FLEN/8, x6, x2, x3) + +inst_161: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3bc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6fbc; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:405*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 405*FLEN/8, x6, x2, x3) + +inst_162: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x03c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x783c; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:408*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 408*FLEN/8, x6, x2, x3) + +inst_163: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x21a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x721a; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:411*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 411*FLEN/8, x6, x2, x3) + +inst_164: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x273 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a73; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:414*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 414*FLEN/8, x6, x2, x3) + +inst_165: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ab4; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:417*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 417*FLEN/8, x6, x2, x3) + +inst_166: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1df and fs2 == 1 and fe2 == 0x07 and fm2 == 0x2cf and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71df; op2val:0x9ecf; +op3val:0x7bff; valaddr_reg:x5; val_offset:420*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 420*FLEN/8, x6, x2, x3) + +inst_167: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x074 and fs2 == 1 and fe2 == 0x07 and fm2 == 0x07d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7474; op2val:0x9c7d; +op3val:0x7bff; valaddr_reg:x5; val_offset:423*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 423*FLEN/8, x6, x2, x3) + +inst_168: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x274 and fs2 == 1 and fe2 == 0x05 and fm2 == 0x232 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a74; op2val:0x9632; +op3val:0x7bff; valaddr_reg:x5; val_offset:426*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 426*FLEN/8, x6, x2, x3) + +inst_169: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x122 and fs2 == 1 and fe2 == 0x05 and fm2 == 0x3ca and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7922; op2val:0x97ca; +op3val:0x7bff; valaddr_reg:x5; val_offset:429*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 429*FLEN/8, x6, x2, x3) + +inst_170: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x272 and fs2 == 1 and fe2 == 0x05 and fm2 == 0x234 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a72; op2val:0x9634; +op3val:0x7bff; valaddr_reg:x5; val_offset:432*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 432*FLEN/8, x6, x2, x3) + +inst_171: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x185 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x33e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7585; op2val:0x9b3e; +op3val:0x7bff; valaddr_reg:x5; val_offset:435*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 435*FLEN/8, x6, x2, x3) + +inst_172: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x026 and fs2 == 1 and fe2 == 0x08 and fm2 == 0x0d2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7026; op2val:0xa0d2; +op3val:0x7bff; valaddr_reg:x5; val_offset:438*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 438*FLEN/8, x6, x2, x3) + +inst_173: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ab and fs2 == 0 and fe2 == 0x07 and fm2 == 0x048 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74ab; op2val:0x1c48; +op3val:0x7bff; valaddr_reg:x5; val_offset:441*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 441*FLEN/8, x6, x2, x3) + +inst_174: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x259 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x24d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a59; op2val:0x164d; +op3val:0x7bff; valaddr_reg:x5; val_offset:444*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 444*FLEN/8, x6, x2, x3) + +inst_175: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x056 and fs2 == 0 and fe2 == 0x07 and fm2 == 0x09c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7456; op2val:0x1c9c; +op3val:0x7bff; valaddr_reg:x5; val_offset:447*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 447*FLEN/8, x6, x2, x3) + +inst_176: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x18a and fs2 == 0 and fe2 == 0x06 and fm2 == 0x338 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x758a; op2val:0x1b38; +op3val:0x7bff; valaddr_reg:x5; val_offset:450*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 450*FLEN/8, x6, x2, x3) + +inst_177: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2aa and fs2 == 0 and fe2 == 0x06 and fm2 == 0x1ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76aa; op2val:0x19ff; +op3val:0x7bff; valaddr_reg:x5; val_offset:453*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 453*FLEN/8, x6, x2, x3) + +inst_178: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2b6 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x1f5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76b6; op2val:0x19f5; +op3val:0x7bff; valaddr_reg:x5; val_offset:456*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 456*FLEN/8, x6, x2, x3) + +inst_179: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x28c and fs2 == 0 and fe2 == 0x06 and fm2 == 0x21b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x768c; op2val:0x1a1b; +op3val:0x7bff; valaddr_reg:x5; val_offset:459*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 459*FLEN/8, x6, x2, x3) + +inst_180: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x35c and fs2 == 0 and fe2 == 0x05 and fm2 == 0x16f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b5c; op2val:0x156f; +op3val:0x7bff; valaddr_reg:x5; val_offset:462*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 462*FLEN/8, x6, x2, x3) + +inst_181: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0fd and fs2 == 0 and fe2 == 0x08 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70fd; op2val:0x2002; +op3val:0x7bff; valaddr_reg:x5; val_offset:465*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 465*FLEN/8, x6, x2, x3) + +inst_182: +// fs1 == 0 and fe1 == 0x17 and fm1 == 0x0c9 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x02d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5cc9; op2val:0x342d; +op3val:0x7bff; valaddr_reg:x5; val_offset:468*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 468*FLEN/8, x6, x2, x3) + +inst_183: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x38a and fs2 == 0 and fe2 == 0x05 and fm2 == 0x14d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b8a; op2val:0x154d; +op3val:0x7bff; valaddr_reg:x5; val_offset:471*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 471*FLEN/8, x6, x2, x3) + +inst_184: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x309 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x1af and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b09; op2val:0x15af; +op3val:0x7bff; valaddr_reg:x5; val_offset:474*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 474*FLEN/8, x6, x2, x3) + +inst_185: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e4 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x111 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7be4; op2val:0x1511; +op3val:0x7bff; valaddr_reg:x5; val_offset:477*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 477*FLEN/8, x6, x2, x3) + +inst_186: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2f2 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x1c2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76f2; op2val:0x19c2; +op3val:0x7bff; valaddr_reg:x5; val_offset:480*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 480*FLEN/8, x6, x2, x3) + +inst_187: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x398 and fs2 == 1 and fe2 == 0x05 and fm2 == 0x143 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b98; op2val:0x9543; +op3val:0x7bff; valaddr_reg:x5; val_offset:483*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 483*FLEN/8, x6, x2, x3) + +inst_188: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x36a and fs2 == 1 and fe2 == 0x05 and fm2 == 0x164 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b6a; op2val:0x9564; +op3val:0x7bff; valaddr_reg:x5; val_offset:486*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 486*FLEN/8, x6, x2, x3) + +inst_189: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x31a and fs2 == 1 and fe2 == 0x07 and fm2 == 0x1a1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x731a; op2val:0x9da1; +op3val:0x7bff; valaddr_reg:x5; val_offset:489*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 489*FLEN/8, x6, x2, x3) + +inst_190: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f6 and fs2 == 1 and fe2 == 0x05 and fm2 == 0x2b5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f6; op2val:0x96b5; +op3val:0x7bff; valaddr_reg:x5; val_offset:492*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 492*FLEN/8, x6, x2, x3) + +inst_191: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 1 and fe2 == 0x05 and fm2 == 0x1fa and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ab0; op2val:0x95fa; +op3val:0x7bff; valaddr_reg:x5; val_offset:495*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 495*FLEN/8, x6, x2, x3) + +inst_192: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x14d and fs2 == 1 and fe2 == 0x05 and fm2 == 0x38b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x794d; op2val:0x978b; +op3val:0x7bff; valaddr_reg:x5; val_offset:498*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 498*FLEN/8, x6, x2, x3) + +inst_193: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x026 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x0d1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7826; op2val:0x98d1; +op3val:0x7bff; valaddr_reg:x5; val_offset:501*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 501*FLEN/8, x6, x2, x3) + +inst_194: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x09f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x029 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x749f; op2val:0x8029; +op3val:0x7bff; valaddr_reg:x5; val_offset:504*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 504*FLEN/8, x6, x2, x3) + +inst_195: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x174 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x023 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7574; op2val:0x8023; +op3val:0x7bff; valaddr_reg:x5; val_offset:507*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 507*FLEN/8, x6, x2, x3) + +inst_196: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x346 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x034 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7346; op2val:0x8034; +op3val:0x7bff; valaddr_reg:x5; val_offset:510*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 510*FLEN/8, x6, x2, x3) + +inst_197: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x05a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0b0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c5a; op2val:0x80b0; +op3val:0x7bff; valaddr_reg:x5; val_offset:513*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 513*FLEN/8, x6, x2, x3) + +inst_198: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x014 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78b5; op2val:0x8014; +op3val:0x7bff; valaddr_reg:x5; val_offset:516*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 516*FLEN/8, x6, x2, x3) + +inst_199: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x097 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x029 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7497; op2val:0x8029; +op3val:0x7bff; valaddr_reg:x5; val_offset:519*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 519*FLEN/8, x6, x2, x3) + +inst_200: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x27a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a7a; op2val:0x800e; +op3val:0x7bff; valaddr_reg:x5; val_offset:522*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 522*FLEN/8, x6, x2, x3) + +inst_201: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x1c4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x10a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x69c4; op2val:0x10a; +op3val:0x7bff; valaddr_reg:x5; val_offset:525*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 525*FLEN/8, x6, x2, x3) + +inst_202: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x339 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b39; op2val:0xd; +op3val:0x7bff; valaddr_reg:x5; val_offset:528*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 528*FLEN/8, x6, x2, x3) + +inst_203: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x18c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x011 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x798c; op2val:0x11; +op3val:0x7bff; valaddr_reg:x5; val_offset:531*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 531*FLEN/8, x6, x2, x3) + +inst_204: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x363 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b63; op2val:0xc; +op3val:0x7bff; valaddr_reg:x5; val_offset:534*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 534*FLEN/8, x6, x2, x3) + +inst_205: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b2b; op2val:0xd; +op3val:0x7bff; valaddr_reg:x5; val_offset:537*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 537*FLEN/8, x6, x2, x3) + +inst_206: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x331 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b31; op2val:0xd; +op3val:0x7bff; valaddr_reg:x5; val_offset:540*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 540*FLEN/8, x6, x2, x3) + +inst_207: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x014 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x789d; op2val:0x14; +op3val:0x7bff; valaddr_reg:x5; val_offset:543*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 543*FLEN/8, x6, x2, x3) + +inst_208: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x2bc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x390 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x62bc; op2val:0x390; +op3val:0x7bff; valaddr_reg:x5; val_offset:546*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 546*FLEN/8, x6, x2, x3) + +inst_209: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x010 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f5; op2val:0x10; +op3val:0x7bff; valaddr_reg:x5; val_offset:549*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 549*FLEN/8, x6, x2, x3) + +inst_210: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x17e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x045 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x717e; op2val:0x45; +op3val:0x7bff; valaddr_reg:x5; val_offset:552*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 552*FLEN/8, x6, x2, x3) + +inst_211: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0cb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x028 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74cb; op2val:0x28; +op3val:0x7bff; valaddr_reg:x5; val_offset:555*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 555*FLEN/8, x6, x2, x3) + +inst_212: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x14c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x012 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x794c; op2val:0x12; +op3val:0x7bff; valaddr_reg:x5; val_offset:558*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 558*FLEN/8, x6, x2, x3) + +inst_213: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x032 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x016 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7832; op2val:0x16; +op3val:0x7bff; valaddr_reg:x5; val_offset:561*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 561*FLEN/8, x6, x2, x3) + +inst_214: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x29d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x01d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x769d; op2val:0x1d; +op3val:0x7bff; valaddr_reg:x5; val_offset:564*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 564*FLEN/8, x6, x2, x3) + +inst_215: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x382 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b82; op2val:0x800c; +op3val:0x7bff; valaddr_reg:x5; val_offset:567*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 567*FLEN/8, x6, x2, x3) + +inst_216: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x013 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e5; op2val:0x8013; +op3val:0x7bff; valaddr_reg:x5; val_offset:570*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 570*FLEN/8, x6, x2, x3) + +inst_217: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x175 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x023 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7575; op2val:0x8023; +op3val:0x7bff; valaddr_reg:x5; val_offset:573*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 573*FLEN/8, x6, x2, x3) + +inst_218: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x009 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x02f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7409; op2val:0x802f; +op3val:0x7bff; valaddr_reg:x5; val_offset:576*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 576*FLEN/8, x6, x2, x3) + +inst_219: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ae3; op2val:0x800d; +op3val:0x7bff; valaddr_reg:x5; val_offset:579*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 579*FLEN/8, x6, x2, x3) + +inst_220: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x019 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77a1; op2val:0x8019; +op3val:0x7bff; valaddr_reg:x5; val_offset:582*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 582*FLEN/8, x6, x2, x3) + +inst_221: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x241 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a41; op2val:0x800f; +op3val:0x7bff; valaddr_reg:x5; val_offset:585*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 585*FLEN/8, x6, x2, x3) + +inst_222: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a0 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1af and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75a0; op2val:0xc1af; +op3val:0x7bff; valaddr_reg:x5; val_offset:588*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 588*FLEN/8, x6, x2, x3) + +inst_223: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x24f and fs2 == 0 and fe2 == 0x11 and fm2 == 0x111 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x724f; op2val:0x4511; +op3val:0x7bff; valaddr_reg:x5; val_offset:591*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 591*FLEN/8, x6, x2, x3) + +inst_224: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x046 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x37b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7846; op2val:0xbf7b; +op3val:0x7bff; valaddr_reg:x5; val_offset:594*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 594*FLEN/8, x6, x2, x3) + +inst_225: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x288 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0e5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a88; op2val:0x3ce5; +op3val:0x7bff; valaddr_reg:x5; val_offset:597*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 597*FLEN/8, x6, x2, x3) + +inst_226: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x17a and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1d6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x717a; op2val:0xc5d6; +op3val:0x7bff; valaddr_reg:x5; val_offset:600*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 600*FLEN/8, x6, x2, x3) + +inst_227: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x254 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x10d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a54; op2val:0x3d0d; +op3val:0x7bff; valaddr_reg:x5; val_offset:603*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 603*FLEN/8, x6, x2, x3) + +inst_228: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x35e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x056 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b5e; op2val:0xbc56; +op3val:0x7bff; valaddr_reg:x5; val_offset:606*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 606*FLEN/8, x6, x2, x3) + +inst_229: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x271 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0f6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a71; op2val:0x3cf6; +op3val:0x7bff; valaddr_reg:x5; val_offset:609*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 609*FLEN/8, x6, x2, x3) + +inst_230: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x295 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0db and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a95; op2val:0xbcdb; +op3val:0x7bff; valaddr_reg:x5; val_offset:612*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 612*FLEN/8, x6, x2, x3) + +inst_231: +// fs1 == 0 and fe1 == 0x17 and fm1 == 0x3b2 and fs2 == 0 and fe2 == 0x16 and fm2 == 0x027 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5fb2; op2val:0x5827; +op3val:0x7bff; valaddr_reg:x5; val_offset:615*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 615*FLEN/8, x6, x2, x3) + +inst_232: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x106 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x25c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7906; op2val:0xbe5c; +op3val:0x7bff; valaddr_reg:x5; val_offset:618*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 618*FLEN/8, x6, x2, x3) + +inst_233: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e5 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0a3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ae5; op2val:0x3ca3; +op3val:0x7bff; valaddr_reg:x5; val_offset:621*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 621*FLEN/8, x6, x2, x3) + +inst_234: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x263 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x101 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6a63; op2val:0xcd01; +op3val:0x7bff; valaddr_reg:x5; val_offset:624*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 624*FLEN/8, x6, x2, x3) + +inst_235: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x057 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x35e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7457; op2val:0x435e; +op3val:0x7bff; valaddr_reg:x5; val_offset:627*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 627*FLEN/8, x6, x2, x3) + +inst_236: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x04b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x372 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x744b; op2val:0xb772; +op3val:0x7bff; valaddr_reg:x5; val_offset:630*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 630*FLEN/8, x6, x2, x3) + +inst_237: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x037 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x396 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7837; op2val:0x3396; +op3val:0x7bff; valaddr_reg:x5; val_offset:633*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 633*FLEN/8, x6, x2, x3) + +inst_238: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2c3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0ba and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76c3; op2val:0xb8ba; +op3val:0x7bff; valaddr_reg:x5; val_offset:636*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 636*FLEN/8, x6, x2, x3) + +inst_239: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x390 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x03a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7790; op2val:0x383a; +op3val:0x7bff; valaddr_reg:x5; val_offset:639*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 639*FLEN/8, x6, x2, x3) + +inst_240: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x235 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x126 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a35; op2val:0xb926; +op3val:0x7bff; valaddr_reg:x5; val_offset:642*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 642*FLEN/8, x6, x2, x3) + +inst_241: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x377 and fs2 == 0 and fe2 == 0x17 and fm2 == 0x048 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5777; op2val:0x5c48; +op3val:0x7bff; valaddr_reg:x5; val_offset:645*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 645*FLEN/8, x6, x2, x3) + +inst_242: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x304 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x08e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6b04; op2val:0xcc8e; +op3val:0x7bff; valaddr_reg:x5; val_offset:648*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 648*FLEN/8, x6, x2, x3) + +inst_243: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x00e and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x700e; op2val:0x47e1; +op3val:0x7bff; valaddr_reg:x5; val_offset:651*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 651*FLEN/8, x6, x2, x3) + +inst_244: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3f9 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ff9; op2val:0xcc02; +op3val:0x7bff; valaddr_reg:x5; val_offset:654*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 654*FLEN/8, x6, x2, x3) + +inst_245: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x060 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x34e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c60; op2val:0x4f4e; +op3val:0x7bff; valaddr_reg:x5; val_offset:657*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 657*FLEN/8, x6, x2, x3) + +inst_246: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3cb and fs2 == 1 and fe2 == 0x11 and fm2 == 0x01a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bcb; op2val:0xc41a; +op3val:0x7bff; valaddr_reg:x5; val_offset:660*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 660*FLEN/8, x6, x2, x3) + +inst_247: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d5 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0ae and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ad5; op2val:0x44ae; +op3val:0x7bff; valaddr_reg:x5; val_offset:663*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 663*FLEN/8, x6, x2, x3) + +inst_248: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x182 and fs2 == 1 and fe2 == 0x15 and fm2 == 0x1cd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d82; op2val:0xd5cd; +op3val:0x7bff; valaddr_reg:x5; val_offset:666*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 666*FLEN/8, x6, x2, x3) + +inst_249: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x003 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x3f7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7803; op2val:0x4bf7; +op3val:0x7bff; valaddr_reg:x5; val_offset:669*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 669*FLEN/8, x6, x2, x3) + +inst_250: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x10d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x750d; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:672*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 672*FLEN/8, x6, x2, x3) + +inst_251: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x107 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7507; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:675*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 675*FLEN/8, x6, x2, x3) + +inst_252: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x19e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x759e; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:678*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 678*FLEN/8, x6, x2, x3) + +inst_253: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x792c; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:681*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 681*FLEN/8, x6, x2, x3) + +inst_254: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78b0; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:684*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 684*FLEN/8, x6, x2, x3) + +inst_255: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c5; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:687*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 687*FLEN/8, x6, x2, x3) + +inst_256: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x21c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x721c; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:690*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 690*FLEN/8, x6, x2, x3) + +inst_257: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x142 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7542; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:693*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 693*FLEN/8, x6, x2, x3) + +inst_258: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3ea and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6fea; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:696*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 696*FLEN/8, x6, x2, x3) + +inst_259: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x071 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7871; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:699*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 699*FLEN/8, x6, x2, x3) + +inst_260: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79b9; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:702*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 702*FLEN/8, x6, x2, x3) + +inst_261: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x214 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7614; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:705*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 705*FLEN/8, x6, x2, x3) + +inst_262: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x11c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d1c; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:708*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 708*FLEN/8, x6, x2, x3) + +inst_263: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71b6; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:711*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 711*FLEN/8, x6, x2, x3) + +inst_264: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1f8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75f8; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:714*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 714*FLEN/8, x6, x2, x3) + +inst_265: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78d5; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:717*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 717*FLEN/8, x6, x2, x3) + +inst_266: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x242 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a42; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:720*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 720*FLEN/8, x6, x2, x3) + +inst_267: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x214 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7614; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:723*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 723*FLEN/8, x6, x2, x3) + +inst_268: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x267 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a67; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:726*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 726*FLEN/8, x6, x2, x3) + +inst_269: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fb; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:729*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 729*FLEN/8, x6, x2, x3) + +inst_270: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76e6; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:732*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 732*FLEN/8, x6, x2, x3) + +inst_271: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1f4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75f4; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:735*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 735*FLEN/8, x6, x2, x3) + +inst_272: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77ef; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:738*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 738*FLEN/8, x6, x2, x3) +RVTEST_SIGBASE(x2,signature_x2_2) + +inst_273: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x799e; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:741*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 741*FLEN/8, x6, x2, x3) + +inst_274: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76b9; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:744*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 744*FLEN/8, x6, x2, x3) + +inst_275: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x18c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x798c; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:747*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 747*FLEN/8, x6, x2, x3) + +inst_276: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x35e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x775e; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:750*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 750*FLEN/8, x6, x2, x3) + +inst_277: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73d6; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:753*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 753*FLEN/8, x6, x2, x3) + +inst_278: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x048 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7848; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:756*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 756*FLEN/8, x6, x2, x3) + +inst_279: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x18f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x798f; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:759*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 759*FLEN/8, x6, x2, x3) + +inst_280: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x094 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c94; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:762*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 762*FLEN/8, x6, x2, x3) + +inst_281: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2cb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76cb; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:765*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 765*FLEN/8, x6, x2, x3) + +inst_282: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x739c; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:768*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 768*FLEN/8, x6, x2, x3) + +inst_283: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78d4; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:771*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 771*FLEN/8, x6, x2, x3) + +inst_284: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7900; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:774*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 774*FLEN/8, x6, x2, x3) + +inst_285: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x2bf and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x62bf; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:777*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 777*FLEN/8, x6, x2, x3) + +inst_286: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ab2; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:780*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 780*FLEN/8, x6, x2, x3) + +inst_287: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7425; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:783*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 783*FLEN/8, x6, x2, x3) + +inst_288: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x37e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x737e; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:786*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 786*FLEN/8, x6, x2, x3) + +inst_289: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x385 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7785; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:789*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 789*FLEN/8, x6, x2, x3) + +inst_290: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79ed; op2val:0x0; +op3val:0x7bff; valaddr_reg:x5; val_offset:792*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 792*FLEN/8, x6, x2, x3) + +inst_291: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x210 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a10; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:795*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 795*FLEN/8, x6, x2, x3) + +inst_292: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78b9; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:798*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 798*FLEN/8, x6, x2, x3) + +inst_293: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x67f0; op2val:0x8000; +op3val:0x7bff; valaddr_reg:x5; val_offset:801*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 801*FLEN/8, x6, x2, x3) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(29596,32,FLEN) +NAN_BOXED(29596,16,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(30810,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(30186,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(30932,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(30932,32,FLEN) +NAN_BOXED(30976,32,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(30976,32,FLEN) +NAN_BOXED(27697,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(25279,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32768,32,FLEN) +NAN_BOXED(31410,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31410,32,FLEN) +NAN_BOXED(29733,32,FLEN) +NAN_BOXED(29733,32,FLEN) +NAN_BOXED(29733,32,FLEN) +NAN_BOXED(29566,32,FLEN) +NAN_BOXED(29566,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(31734,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(30597,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31408,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(30622,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31743,32,FLEN) +test_dataset_1: +NAN_BOXED(31004,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(28881,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(30995,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(31472,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(30766,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(31213,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(31070,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(27672,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(31248,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(29905,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(26608,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,32,FLEN) +test_dataset_2: +NAN_BOXED(31467,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30607,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31167,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31494,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31157,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31581,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30289,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31335,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30492,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31611,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31495,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(28220,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(28761,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29424,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31672,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30457,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30978,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29904,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30734,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30251,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30108,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30893,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30891,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31546,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31092,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31597,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31449,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31724,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31070,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(28983,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31457,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31670,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31547,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30860,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29376,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31398,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30870,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29838,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(27663,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31444,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31722,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(28073,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31334,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30352,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(28882,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29875,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31269,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31482,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(27047,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30953,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(27072,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31166,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30026,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31499,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31703,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30730,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31739,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29939,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(27884,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30923,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(26628,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29264,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30342,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30945,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(28927,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(26990,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29956,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31658,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31531,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30218,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30556,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30760,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31014,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30915,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30840,16,FLEN) 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+NAN_BOXED(27796,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30411,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29596,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30932,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30976,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(25279,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31410,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29733,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29566,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30597,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31213,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31248,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30905,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(26608,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 34*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_0: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_1: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_2: + .fill 42*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fnmsub_b2-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fnmsub_b2-01.S new file mode 100644 index 000000000..f88d6ce60 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fnmsub_b2-01.S @@ -0,0 +1,1394 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 06:07:02 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fnmsub.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fnmsub.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fnmsub_b2 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fnmsub_b2) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x7,test_dataset_0) +RVTEST_SIGBASE(x3,signature_x3_1) + +inst_0: +// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==x26, rs2==x26, rs3==x7, rd==x18,fs1 == 0 and fe1 == 0x00 and fm1 == 0x01e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x288 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x030 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x26; op2:x26; op3:x7; dest:x18; op1val:0x1e; op2val:0x1e; +op3val:0x30; valaddr_reg:x7; val_offset:0*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x18, x26, x26, x7, dyn, 0, 0, x7, 0*FLEN/8, x9, x3, x6) + +inst_1: +// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==x25, rs2==x14, rs3==x13, rd==x25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x031 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x234 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x011 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x25; op2:x14; op3:x13; dest:x25; op1val:0x31; op2val:0xb634; +op3val:0x11; valaddr_reg:x7; val_offset:3*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x25, x25, x14, x13, dyn, 0, 0, x7, 3*FLEN/8, x9, x3, x6) + +inst_2: +// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==x31, rs2==x4, rs3==x22, rd==x30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x019 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x399 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x05b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x31; op2:x4; op3:x22; dest:x30; op1val:0x19; op2val:0xc399; +op3val:0x5b; valaddr_reg:x7; val_offset:6*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x30, x31, x4, x22, dyn, 0, 0, x7, 6*FLEN/8, x9, x3, x6) + +inst_3: +// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==x14, rs2==x31, rs3==x14, rd==x19,fs1 == 0 and fe1 == 0x00 and fm1 == 0x006 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x14; op2:x31; op3:x14; dest:x19; op1val:0x6; op2val:0xc255; +op3val:0x6; valaddr_reg:x7; val_offset:9*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x19, x14, x31, x14, dyn, 0, 0, x7, 9*FLEN/8, x9, x3, x6) + +inst_4: +// rs1 == rs2 == rs3 != rd, rs1==x27, rs2==x27, rs3==x27, rd==x2,fs1 == 0 and fe1 == 0x00 and fm1 == 0x012 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x020 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x27; op2:x27; op3:x27; dest:x2; op1val:0x12; op2val:0x12; +op3val:0x12; valaddr_reg:x7; val_offset:12*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x2, x27, x27, x27, dyn, 0, 0, x7, 12*FLEN/8, x9, x3, x6) + +inst_5: +// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==x11, rs2==x25, rs3==x8, rd==x8,fs1 == 0 and fe1 == 0x00 and fm1 == 0x041 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x342 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x01b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x11; op2:x25; op3:x8; dest:x8; op1val:0x41; op2val:0xbb42; +op3val:0x1b; valaddr_reg:x7; val_offset:15*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x8, x11, x25, x8, dyn, 0, 0, x7, 15*FLEN/8, x9, x3, x6) + +inst_6: +// rd == rs2 == rs3 != rs1, rs1==x4, rs2==x21, rs3==x21, rd==x21,fs1 == 0 and fe1 == 0x00 and fm1 == 0x034 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1a7 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x053 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x4; op2:x21; op3:x21; dest:x21; op1val:0x34; op2val:0xc1a7; +op3val:0xc1a7; valaddr_reg:x7; val_offset:18*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x21, x4, x21, x21, dyn, 0, 0, x7, 18*FLEN/8, x9, x3, x6) + +inst_7: +// rs1 == rd == rs3 != rs2, rs1==x28, rs2==x12, rs3==x28, rd==x28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x004 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x1d8 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x03b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x28; op2:x12; op3:x28; dest:x28; op1val:0x4; op2val:0xd1d8; +op3val:0x4; valaddr_reg:x7; val_offset:21*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x28, x28, x12, x28, dyn, 0, 0, x7, 21*FLEN/8, x9, x3, x6) + +inst_8: +// rs1 == rs2 == rs3 == rd, rs1==x24, rs2==x24, rs3==x24, rd==x24,fs1 == 0 and fe1 == 0x00 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x11 and fm2 == 0x100 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x03b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x24; op2:x24; op3:x24; dest:x24; op1val:0x3f; op2val:0x3f; +op3val:0x3f; valaddr_reg:x7; val_offset:24*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x24, x24, x24, x24, dyn, 0, 0, x7, 24*FLEN/8, x9, x3, x6) + +inst_9: +// rs1 == rs2 == rd != rs3, rs1==x0, rs2==x0, rs3==x12, rd==x0,fs1 == 0 and fe1 == 0x00 and fm1 == 0x032 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x1c2 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x040 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x0; op2:x0; op3:x12; dest:x0; op1val:0x0; op2val:0x0; +op3val:0x40; valaddr_reg:x7; val_offset:27*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x0, x0, x0, x12, dyn, 0, 0, x7, 27*FLEN/8, x9, x3, x6) + +inst_10: +// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==x18, rs2==x11, rs3==x30, rd==x11,fs1 == 0 and fe1 == 0x00 and fm1 == 0x04a and fs2 == 1 and fe2 == 0x0d and fm2 == 0x130 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x019 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x18; op2:x11; op3:x30; dest:x11; op1val:0x4a; op2val:0xb530; +op3val:0x19; valaddr_reg:x7; val_offset:30*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x11, x18, x11, x30, dyn, 0, 0, x7, 30*FLEN/8, x9, x3, x6) + +inst_11: +// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==x16, rs2==x29, rs3==x29, rd==x14,fs1 == 0 and fe1 == 0x00 and fm1 == 0x034 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x227 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x16; op2:x29; op3:x29; dest:x14; op1val:0x34; op2val:0xb227; +op3val:0xb227; valaddr_reg:x7; val_offset:33*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x14, x16, x29, x29, dyn, 0, 0, x7, 33*FLEN/8, x9, x3, x6) + +inst_12: +// rs1==x22, rs2==x10, rs3==x9, rd==x4,fs1 == 0 and fe1 == 0x00 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x29a and fs3 == 0 and fe3 == 0x00 and fm3 == 0x01e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x22; op2:x10; op3:x9; dest:x4; op1val:0x3f; op2val:0xb69a; +op3val:0x1e; valaddr_reg:x7; val_offset:36*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x4, x22, x10, x9, dyn, 0, 0, x7, 36*FLEN/8, x9, x3, x6) + +inst_13: +// rs1==x1, rs2==x5, rs3==x3, rd==x16,fs1 == 0 and fe1 == 0x00 and fm1 == 0x062 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x287 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x1; op2:x5; op3:x3; dest:x16; op1val:0x62; op2val:0x2a87; +op3val:0x3; valaddr_reg:x7; val_offset:39*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x16, x1, x5, x3, dyn, 0, 0, x7, 39*FLEN/8, x9, x3, x6) +RVTEST_VALBASEUPD(x1,test_dataset_1) + +inst_14: +// rs1==x29, rs2==x22, rs3==x1, rd==x27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x05a and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2c1 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x023 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x29; op2:x22; op3:x1; dest:x27; op1val:0x5a; op2val:0xb2c1; +op3val:0x23; valaddr_reg:x1; val_offset:0*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x27, x29, x22, x1, dyn, 0, 0, x1, 0*FLEN/8, x2, x3, x6) + +inst_15: +// rs1==x7, rs2==x8, rs3==x6, rd==x9,fs1 == 0 and fe1 == 0x00 and fm1 == 0x043 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x103 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x035 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x7; op2:x8; op3:x6; dest:x9; op1val:0x43; op2val:0xb503; +op3val:0x35; valaddr_reg:x1; val_offset:3*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x9, x7, x8, x6, dyn, 0, 0, x1, 3*FLEN/8, x2, x3, x6) + +inst_16: +// rs1==x23, rs2==x15, rs3==x5, rd==x17,fs1 == 0 and fe1 == 0x00 and fm1 == 0x03d and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3de and fs3 == 0 and fe3 == 0x00 and fm3 == 0x031 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x23; op2:x15; op3:x5; dest:x17; op1val:0x3d; op2val:0x33de; +op3val:0x31; valaddr_reg:x1; val_offset:6*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x17, x23, x15, x5, dyn, 0, 0, x1, 6*FLEN/8, x2, x3, x11) +RVTEST_SIGBASE(x4,signature_x4_0) + +inst_17: +// rs1==x21, rs2==x30, rs3==x0, rd==x10,fs1 == 0 and fe1 == 0x00 and fm1 == 0x05d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0dc and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x21; op2:x30; op3:x0; dest:x10; op1val:0x5d; op2val:0x3cdc; +op3val:0x0; valaddr_reg:x1; val_offset:9*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x10, x21, x30, x0, dyn, 0, 0, x1, 9*FLEN/8, x2, x4, x11) + +inst_18: +// rs1==x8, rs2==x16, rs3==x31, rd==x29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x139 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x022 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x8; op2:x16; op3:x31; dest:x29; op1val:0x55; op2val:0x4139; +op3val:0x22; valaddr_reg:x1; val_offset:12*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x29, x8, x16, x31, dyn, 0, 0, x1, 12*FLEN/8, x2, x4, x11) + +inst_19: +// rs1==x12, rs2==x9, rs3==x18, rd==x7,fs1 == 0 and fe1 == 0x00 and fm1 == 0x00d and fs2 == 0 and fe2 == 0x14 and fm2 == 0x0d6 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x009 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x12; op2:x9; op3:x18; dest:x7; op1val:0xd; op2val:0x50d6; +op3val:0x9; valaddr_reg:x1; val_offset:15*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x7, x12, x9, x18, dyn, 0, 0, x1, 15*FLEN/8, x2, x4, x11) + +inst_20: +// rs1==x30, rs2==x19, rs3==x17, rd==x5,fs1 == 0 and fe1 == 0x0f and fm1 == 0x032 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3ed and fs3 == 0 and fe3 == 0x0f and fm3 == 0x050 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x19; op3:x17; dest:x5; op1val:0x3c32; op2val:0xbfed; +op3val:0x3c50; valaddr_reg:x1; val_offset:18*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x5, x30, x19, x17, dyn, 0, 0, x1, 18*FLEN/8, x2, x4, x11) + +inst_21: +// rs1==x20, rs2==x28, rs3==x11, rd==x26,fs1 == 0 and fe1 == 0x0f and fm1 == 0x031 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3b1 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x00e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x20; op2:x28; op3:x11; dest:x26; op1val:0x3c31; op2val:0xbfb1; +op3val:0x3c0e; valaddr_reg:x1; val_offset:21*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x26, x20, x28, x11, dyn, 0, 0, x1, 21*FLEN/8, x2, x4, x11) + +inst_22: +// rs1==x3, rs2==x20, rs3==x25, rd==x6,fs1 == 0 and fe1 == 0x0f and fm1 == 0x055 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x36e and fs3 == 0 and fe3 == 0x0f and fm3 == 0x008 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x3; op2:x20; op3:x25; dest:x6; op1val:0x3c55; op2val:0xbf6e; +op3val:0x3c08; valaddr_reg:x1; val_offset:24*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x6, x3, x20, x25, dyn, 0, 0, x1, 24*FLEN/8, x2, x4, x11) + +inst_23: +// rs1==x13, rs2==x7, rs3==x10, rd==x20,fs1 == 0 and fe1 == 0x0f and fm1 == 0x02c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3d1 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x13; op2:x7; op3:x10; dest:x20; op1val:0x3c2c; op2val:0xbfd1; +op3val:0x3c1f; valaddr_reg:x1; val_offset:27*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x20, x13, x7, x10, dyn, 0, 0, x1, 27*FLEN/8, x2, x4, x11) +RVTEST_VALBASEUPD(x8,test_dataset_2) + +inst_24: +// rs1==x9, rs2==x1, rs3==x4, rd==x31,fs1 == 0 and fe1 == 0x0f and fm1 == 0x059 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x375 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x00c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x9; op2:x1; op3:x4; dest:x31; op1val:0x3c59; op2val:0xbf75; +op3val:0x3c0c; valaddr_reg:x8; val_offset:0*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x9, x1, x4, dyn, 0, 0, x8, 0*FLEN/8, x14, x4, x11) + +inst_25: +// rs1==x2, rs2==x6, rs3==x26, rd==x13,fs1 == 0 and fe1 == 0x0f and fm1 == 0x040 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3f4 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x054 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x2; op2:x6; op3:x26; dest:x13; op1val:0x3c40; op2val:0xbff4; +op3val:0x3c54; valaddr_reg:x8; val_offset:3*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x13, x2, x6, x26, dyn, 0, 0, x8, 3*FLEN/8, x14, x4, x11) + +inst_26: +// rs1==x10, rs2==x18, rs3==x20, rd==x15,fs1 == 0 and fe1 == 0x0f and fm1 == 0x043 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3d7 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x01b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x10; op2:x18; op3:x20; dest:x15; op1val:0x3c43; op2val:0xbfd7; +op3val:0x3c1b; valaddr_reg:x8; val_offset:6*FLEN/8; rmval:dyn; +testreg:x11; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x15, x10, x18, x20, dyn, 0, 0, x8, 6*FLEN/8, x14, x4, x11) + +inst_27: +// rs1==x19, rs2==x23, rs3==x15, rd==x12,fs1 == 0 and fe1 == 0x0f and fm1 == 0x04b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3fd and fs3 == 0 and fe3 == 0x0f and fm3 == 0x013 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x19; op2:x23; op3:x15; dest:x12; op1val:0x3c4b; op2val:0xbffd; +op3val:0x3c13; valaddr_reg:x8; val_offset:9*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x12, x19, x23, x15, dyn, 0, 0, x8, 9*FLEN/8, x14, x4, x7) + +inst_28: +// rs1==x17, rs2==x13, rs3==x2, rd==x23,fs1 == 0 and fe1 == 0x0f and fm1 == 0x04e and fs2 == 1 and fe2 == 0x10 and fm2 == 0x032 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x009 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x17; op2:x13; op3:x2; dest:x23; op1val:0x3c4e; op2val:0xc032; +op3val:0x3c09; valaddr_reg:x8; val_offset:12*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x23, x17, x13, x2, dyn, 0, 0, x8, 12*FLEN/8, x14, x4, x7) + +inst_29: +// rs1==x15, rs2==x17, rs3==x19, rd==x22,fs1 == 0 and fe1 == 0x0f and fm1 == 0x046 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0b0 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x005 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x15; op2:x17; op3:x19; dest:x22; op1val:0x3c46; op2val:0xc0b0; +op3val:0x3c05; valaddr_reg:x8; val_offset:15*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x22, x15, x17, x19, dyn, 0, 0, x8, 15*FLEN/8, x14, x4, x7) +RVTEST_SIGBASE(x4,signature_x4_1) + +inst_30: +// rs1==x5, rs2==x2, rs3==x16, rd==x3,fs1 == 0 and fe1 == 0x0f and fm1 == 0x03f and fs2 == 1 and fe2 == 0x0b and fm2 == 0x13d and fs3 == 0 and fe3 == 0x0f and fm3 == 0x05a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x5; op2:x2; op3:x16; dest:x3; op1val:0x3c3f; op2val:0xad3d; +op3val:0x3c5a; valaddr_reg:x8; val_offset:18*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x3, x5, x2, x16, dyn, 0, 0, x8, 18*FLEN/8, x14, x4, x7) + +inst_31: +// rs1==x6, rs2==x3, rs3==x23, rd==x1,fs1 == 0 and fe1 == 0x0f and fm1 == 0x019 and fs2 == 1 and fe2 == 0x09 and fm2 == 0x026 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x013 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x6; op2:x3; op3:x23; dest:x1; op1val:0x3c19; op2val:0xa426; +op3val:0x3c13; valaddr_reg:x8; val_offset:21*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x1, x6, x3, x23, dyn, 0, 0, x8, 21*FLEN/8, x14, x4, x7) + +inst_32: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x04b and fs2 == 1 and fe2 == 0x0a and fm2 == 0x267 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x03b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c4b; op2val:0xaa67; +op3val:0x3c3b; valaddr_reg:x8; val_offset:24*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 24*FLEN/8, x14, x4, x7) + +inst_33: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x05e and fs2 == 1 and fe2 == 0x0a and fm2 == 0x3ab and fs3 == 0 and fe3 == 0x0f and fm3 == 0x04b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c5e; op2val:0xabab; +op3val:0x3c4b; valaddr_reg:x8; val_offset:27*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 27*FLEN/8, x14, x4, x7) + +inst_34: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x039 and fs2 == 1 and fe2 == 0x09 and fm2 == 0x0f9 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x025 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c39; op2val:0xa4f9; +op3val:0x3c25; valaddr_reg:x8; val_offset:30*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 30*FLEN/8, x14, x4, x7) + +inst_35: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x048 and fs2 == 1 and fe2 == 0x08 and fm2 == 0x28a and fs3 == 0 and fe3 == 0x0f and fm3 == 0x02e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c48; op2val:0xa28a; +op3val:0x3c2e; valaddr_reg:x8; val_offset:33*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 33*FLEN/8, x14, x4, x7) + +inst_36: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x037 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x174 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x012 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c37; op2val:0x2974; +op3val:0x3c12; valaddr_reg:x8; val_offset:36*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 36*FLEN/8, x14, x4, x7) + +inst_37: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x015 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x359 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x062 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c15; op2val:0x2759; +op3val:0x3c62; valaddr_reg:x8; val_offset:39*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 39*FLEN/8, x14, x4, x7) + +inst_38: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x04d and fs2 == 0 and fe2 == 0x0c and fm2 == 0x310 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x00d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c4d; op2val:0x3310; +op3val:0x3c0d; valaddr_reg:x8; val_offset:42*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 42*FLEN/8, x14, x4, x7) + +inst_39: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x045 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x231 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x059 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c45; op2val:0x3631; +op3val:0x3c59; valaddr_reg:x8; val_offset:45*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 45*FLEN/8, x14, x4, x7) + +inst_40: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x029 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x070 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x05a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x29; op2val:0xc070; +op3val:0x5a; valaddr_reg:x8; val_offset:48*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 48*FLEN/8, x14, x4, x7) + +inst_41: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x02e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x37a and fs3 == 0 and fe3 == 0x00 and fm3 == 0x053 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e; op2val:0xbf7a; +op3val:0x53; valaddr_reg:x8; val_offset:51*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 51*FLEN/8, x14, x4, x7) + +inst_42: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x040 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x060 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x041 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x40; op2val:0xbc60; +op3val:0x41; valaddr_reg:x8; val_offset:54*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 54*FLEN/8, x14, x4, x7) + +inst_43: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x050 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x300 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x01a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x50; op2val:0xb700; +op3val:0x1a; valaddr_reg:x8; val_offset:57*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 57*FLEN/8, x14, x4, x7) + +inst_44: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x028 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x366 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x014 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x28; op2val:0xbb66; +op3val:0x14; valaddr_reg:x8; val_offset:60*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 60*FLEN/8, x14, x4, x7) + +inst_45: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x02e and fs2 == 1 and fe2 == 0x10 and fm2 == 0x064 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x044 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e; op2val:0xc064; +op3val:0x44; valaddr_reg:x8; val_offset:63*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 63*FLEN/8, x14, x4, x7) + +inst_46: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x025 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x314 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x042 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x25; op2val:0xc314; +op3val:0x42; valaddr_reg:x8; val_offset:66*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 66*FLEN/8, x14, x4, x7) + +inst_47: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x28a and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x55; op2val:0xbe8a; +op3val:0xa; valaddr_reg:x8; val_offset:69*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 69*FLEN/8, x14, x4, x7) + +inst_48: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x041 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x156 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x05a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x41; op2val:0xc556; +op3val:0x5a; valaddr_reg:x8; val_offset:72*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 72*FLEN/8, x14, x4, x7) + +inst_49: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x046 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x3be and fs3 == 0 and fe3 == 0x00 and fm3 == 0x01d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x46; op2val:0xc7be; +op3val:0x1d; valaddr_reg:x8; val_offset:75*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 75*FLEN/8, x14, x4, x7) + +inst_50: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x02d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x182 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x020 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2d; op2val:0xb982; +op3val:0x20; valaddr_reg:x8; val_offset:78*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 78*FLEN/8, x14, x4, x7) + +inst_51: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x060 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x026 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xcc60; +op3val:0x26; valaddr_reg:x8; val_offset:81*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 81*FLEN/8, x14, x4, x7) + +inst_52: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x02c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x05d and fs3 == 0 and fe3 == 0x00 and fm3 == 0x01d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2c; op2val:0xb85d; +op3val:0x1d; valaddr_reg:x8; val_offset:84*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 84*FLEN/8, x14, x4, x7) + +inst_53: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x023 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x350 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x005 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x23; op2val:0x2f50; +op3val:0x5; valaddr_reg:x8; val_offset:87*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 87*FLEN/8, x14, x4, x7) + +inst_54: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x037 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0a7 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x021 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37; op2val:0xb4a7; +op3val:0x21; valaddr_reg:x8; val_offset:90*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 90*FLEN/8, x14, x4, x7) + +inst_55: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x031 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x3d6 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x027 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31; op2val:0xafd6; +op3val:0x27; valaddr_reg:x8; val_offset:93*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 93*FLEN/8, x14, x4, x7) + +inst_56: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x05b and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3bc and fs3 == 0 and fe3 == 0x00 and fm3 == 0x036 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5b; op2val:0x2fbc; +op3val:0x36; valaddr_reg:x8; val_offset:96*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 96*FLEN/8, x14, x4, x7) + +inst_57: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x017 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3a6 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x17; op2val:0x3fa6; +op3val:0x55; valaddr_reg:x8; val_offset:99*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 99*FLEN/8, x14, x4, x7) + +inst_58: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x033 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0be and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x33; op2val:0x44be; +op3val:0xf; valaddr_reg:x8; val_offset:102*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 102*FLEN/8, x14, x4, x7) + +inst_59: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x016 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x0dd and fs3 == 0 and fe3 == 0x00 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x16; op2val:0x4cdd; +op3val:0x55; valaddr_reg:x8; val_offset:105*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 105*FLEN/8, x14, x4, x7) + +inst_60: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x004 and fs2 == 1 and fe2 == 0x17 and fm2 == 0x018 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x01a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4; op2val:0xdc18; +op3val:0x1a; valaddr_reg:x8; val_offset:108*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 108*FLEN/8, x14, x4, x7) + +inst_61: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x063 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x143 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x015 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x63; op2val:0xc943; +op3val:0x15; valaddr_reg:x8; val_offset:111*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 111*FLEN/8, x14, x4, x7) + +inst_62: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x027 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x2a0 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x27; op2val:0xcea0; +op3val:0xf; valaddr_reg:x8; val_offset:114*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 114*FLEN/8, x14, x4, x7) + +inst_63: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x18 and fm2 == 0x059 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x062 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xe059; +op3val:0x62; valaddr_reg:x8; val_offset:117*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 117*FLEN/8, x14, x4, x7) + +inst_64: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x031 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x15c and fs3 == 0 and fe3 == 0x00 and fm3 == 0x02c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31; op2val:0xcd5c; +op3val:0x2c; valaddr_reg:x8; val_offset:120*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 120*FLEN/8, x14, x4, x7) + +inst_65: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x016 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x20b and fs3 == 0 and fe3 == 0x00 and fm3 == 0x049 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x16; op2val:0xd20b; +op3val:0x49; valaddr_reg:x8; val_offset:123*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 123*FLEN/8, x14, x4, x7) + +inst_66: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x038 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x06a and fs3 == 0 and fe3 == 0x00 and fm3 == 0x01e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38; op2val:0xcc6a; +op3val:0x1e; valaddr_reg:x8; val_offset:126*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 126*FLEN/8, x14, x4, x7) + +inst_67: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x012 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x295 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x035 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x12; op2val:0xd295; +op3val:0x35; valaddr_reg:x8; val_offset:129*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 129*FLEN/8, x14, x4, x7) + +inst_68: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x049 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x1a6 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x03a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x49; op2val:0xc9a6; +op3val:0x3a; valaddr_reg:x8; val_offset:132*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 132*FLEN/8, x14, x4, x7) + +inst_69: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x035 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x154 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x036 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35; op2val:0xc954; +op3val:0x36; valaddr_reg:x8; val_offset:135*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 135*FLEN/8, x14, x4, x7) + +inst_70: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00b and fs2 == 0 and fe2 == 0x15 and fm2 == 0x160 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x04c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xb; op2val:0x5560; +op3val:0x4c; valaddr_reg:x8; val_offset:138*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 138*FLEN/8, x14, x4, x7) + +inst_71: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x009 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x2d5 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x025 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x9; op2val:0x56d5; +op3val:0x25; valaddr_reg:x8; val_offset:141*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 141*FLEN/8, x14, x4, x7) + +inst_72: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x05c and fs2 == 0 and fe2 == 0x12 and fm2 == 0x177 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5c; op2val:0x4977; +op3val:0xd; valaddr_reg:x8; val_offset:144*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 144*FLEN/8, x14, x4, x7) + +inst_73: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x005 and fs2 == 0 and fe2 == 0x16 and fm2 == 0x246 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5; op2val:0x5a46; +op3val:0xb; valaddr_reg:x8; val_offset:147*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 147*FLEN/8, x14, x4, x7) + +inst_74: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x1d7 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x55; op2val:0x49d7; +op3val:0xe; valaddr_reg:x8; val_offset:150*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 150*FLEN/8, x14, x4, x7) + +inst_75: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x062 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x0b6 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x043 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x62; op2val:0x48b6; +op3val:0x43; valaddr_reg:x8; val_offset:153*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 153*FLEN/8, x14, x4, x7) + +inst_76: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x044 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x2b4 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x02f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x44; op2val:0x4ab4; +op3val:0x2f; valaddr_reg:x8; val_offset:156*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 156*FLEN/8, x14, x4, x7) + +inst_77: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x014 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x130 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x041 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x14; op2val:0x5130; +op3val:0x41; valaddr_reg:x8; val_offset:159*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 159*FLEN/8, x14, x4, x7) + +inst_78: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x12 and fm2 == 0x15d and fs3 == 0 and fe3 == 0x00 and fm3 == 0x05b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f; op2val:0x495d; +op3val:0x5b; valaddr_reg:x8; val_offset:162*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 162*FLEN/8, x14, x4, x7) + +inst_79: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x014 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x169 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x04e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x14; op2val:0x4d69; +op3val:0x4e; valaddr_reg:x8; val_offset:165*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 165*FLEN/8, x14, x4, x7) + +inst_80: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x009 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x003 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x019 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x409; op2val:0xc003; +op3val:0x419; valaddr_reg:x8; val_offset:168*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 168*FLEN/8, x14, x4, x7) + +inst_81: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x006 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x012 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x403; op2val:0xc006; +op3val:0x412; valaddr_reg:x8; val_offset:171*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 171*FLEN/8, x14, x4, x7) + +inst_82: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x02c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3df and fs3 == 0 and fe3 == 0x01 and fm3 == 0x032 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x42c; op2val:0xbfdf; +op3val:0x432; valaddr_reg:x8; val_offset:174*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 174*FLEN/8, x14, x4, x7) + +inst_83: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3ae and fs3 == 0 and fe3 == 0x01 and fm3 == 0x04a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x455; op2val:0xbfae; +op3val:0x44a; valaddr_reg:x8; val_offset:177*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 177*FLEN/8, x14, x4, x7) + +inst_84: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x010 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x027 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x060 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x410; op2val:0xc027; +op3val:0x460; valaddr_reg:x8; val_offset:180*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 180*FLEN/8, x14, x4, x7) + +inst_85: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x027 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x02d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x427; op2val:0xbfff; +op3val:0x42d; valaddr_reg:x8; val_offset:183*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 183*FLEN/8, x14, x4, x7) + +inst_86: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x02a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x00c and fs3 == 0 and fe3 == 0x01 and fm3 == 0x02f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x42a; op2val:0xc00c; +op3val:0x42f; valaddr_reg:x8; val_offset:186*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 186*FLEN/8, x14, x4, x7) + +inst_87: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x068 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x053 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x401; op2val:0xc068; +op3val:0x453; valaddr_reg:x8; val_offset:189*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 189*FLEN/8, x14, x4, x7) + +inst_88: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x040 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x048 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x01b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x440; op2val:0xc048; +op3val:0x41b; valaddr_reg:x8; val_offset:192*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 192*FLEN/8, x14, x4, x7) + +inst_89: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x008 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x11d and fs3 == 0 and fe3 == 0x01 and fm3 == 0x050 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x408; op2val:0xc11d; +op3val:0x450; valaddr_reg:x8; val_offset:195*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 195*FLEN/8, x14, x4, x7) + +inst_90: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x005 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x208 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x062 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x405; op2val:0xae08; +op3val:0x462; valaddr_reg:x8; val_offset:198*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 198*FLEN/8, x14, x4, x7) + +inst_91: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x04b and fs2 == 1 and fe2 == 0x09 and fm2 == 0x0e4 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x017 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x44b; op2val:0xa4e4; +op3val:0x417; valaddr_reg:x8; val_offset:201*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 201*FLEN/8, x14, x4, x7) + +inst_92: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x017 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x0e3 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x02c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x417; op2val:0xa8e3; +op3val:0x42c; valaddr_reg:x8; val_offset:204*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 204*FLEN/8, x14, x4, x7) + +inst_93: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x038 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x1ce and fs3 == 0 and fe3 == 0x01 and fm3 == 0x039 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x438; op2val:0xa9ce; +op3val:0x439; valaddr_reg:x8; val_offset:207*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 207*FLEN/8, x14, x4, x7) + +inst_94: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x010 and fs2 == 0 and fe2 == 0x07 and fm2 == 0x0ec and fs3 == 0 and fe3 == 0x01 and fm3 == 0x00b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x410; op2val:0x1cec; +op3val:0x40b; valaddr_reg:x8; val_offset:210*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 210*FLEN/8, x14, x4, x7) + +inst_95: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x01a and fs2 == 1 and fe2 == 0x0a and fm2 == 0x19b and fs3 == 0 and fe3 == 0x01 and fm3 == 0x04e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x41a; op2val:0xa99b; +op3val:0x44e; valaddr_reg:x8; val_offset:213*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 213*FLEN/8, x14, x4, x7) + +inst_96: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x01d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2f0 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x040 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x41d; op2val:0x2f0; +op3val:0x440; valaddr_reg:x8; val_offset:216*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 216*FLEN/8, x14, x4, x7) + +inst_97: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x03d and fs2 == 0 and fe2 == 0x0b and fm2 == 0x25e and fs3 == 0 and fe3 == 0x01 and fm3 == 0x014 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x43d; op2val:0x2e5e; +op3val:0x414; valaddr_reg:x8; val_offset:219*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 219*FLEN/8, x14, x4, x7) + +inst_98: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x031 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x328 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x010 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x431; op2val:0x3328; +op3val:0x410; valaddr_reg:x8; val_offset:222*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 222*FLEN/8, x14, x4, x7) + +inst_99: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x00e and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2bc and fs3 == 0 and fe3 == 0x01 and fm3 == 0x04b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x40e; op2val:0x36bc; +op3val:0x44b; valaddr_reg:x8; val_offset:225*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 225*FLEN/8, x14, x4, x7) + +inst_100: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x05d and fs2 == 1 and fe2 == 0x10 and fm2 == 0x199 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x03a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x785d; op2val:0xc199; +op3val:0x783a; valaddr_reg:x8; val_offset:228*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 228*FLEN/8, x14, x4, x7) + +inst_101: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x053 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x193 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x011 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7853; op2val:0xc193; +op3val:0x7811; valaddr_reg:x8; val_offset:231*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 231*FLEN/8, x14, x4, x7) + +inst_102: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x05d and fs2 == 1 and fe2 == 0x10 and fm2 == 0x197 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x039 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x785d; op2val:0xc197; +op3val:0x7839; valaddr_reg:x8; val_offset:234*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 234*FLEN/8, x14, x4, x7) + +inst_103: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x042 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1ca and fs3 == 0 and fe3 == 0x1e and fm3 == 0x05d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7842; op2val:0xc1ca; +op3val:0x785d; valaddr_reg:x8; val_offset:237*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 237*FLEN/8, x14, x4, x7) + +inst_104: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x213 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x05c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x780c; op2val:0xc213; +op3val:0x785c; valaddr_reg:x8; val_offset:240*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 240*FLEN/8, x14, x4, x7) + +inst_105: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x03d and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1bc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x049 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x783d; op2val:0xc1bc; +op3val:0x7849; valaddr_reg:x8; val_offset:243*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 243*FLEN/8, x14, x4, x7) + +inst_106: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x033 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1ae and fs3 == 0 and fe3 == 0x1e and fm3 == 0x02f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7833; op2val:0xc1ae; +op3val:0x782f; valaddr_reg:x8; val_offset:246*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 246*FLEN/8, x14, x4, x7) + +inst_107: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x03b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x17d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x01d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x783b; op2val:0xc17d; +op3val:0x781d; valaddr_reg:x8; val_offset:249*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 249*FLEN/8, x14, x4, x7) + +inst_108: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x007 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x182 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x01a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7807; op2val:0xc182; +op3val:0x781a; valaddr_reg:x8; val_offset:252*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 252*FLEN/8, x14, x4, x7) + +inst_109: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x007 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x113 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x03a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7807; op2val:0xc113; +op3val:0x783a; valaddr_reg:x8; val_offset:255*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 255*FLEN/8, x14, x4, x7) + +inst_110: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3c2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x780f; op2val:0x3bc2; +op3val:0x780e; valaddr_reg:x8; val_offset:258*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 258*FLEN/8, x14, x4, x7) + +inst_111: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x01c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x30e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x05d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x781c; op2val:0x3b0e; +op3val:0x785d; valaddr_reg:x8; val_offset:261*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 261*FLEN/8, x14, x4, x7) + +inst_112: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x33e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x05b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7801; op2val:0x3b3e; +op3val:0x785b; valaddr_reg:x8; val_offset:264*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 264*FLEN/8, x14, x4, x7) + +inst_113: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2cd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x04f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x784d; op2val:0x3acd; +op3val:0x784f; valaddr_reg:x8; val_offset:267*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 267*FLEN/8, x14, x4, x7) + +inst_114: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x003 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x330 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x054 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7803; op2val:0x3b30; +op3val:0x7854; valaddr_reg:x8; val_offset:270*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 270*FLEN/8, x14, x4, x7) + +inst_115: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2fb and fs3 == 0 and fe3 == 0x1e and fm3 == 0x038 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x782f; op2val:0x3afb; +op3val:0x7838; valaddr_reg:x8; val_offset:273*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 273*FLEN/8, x14, x4, x7) + +inst_116: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x044 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2f0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7844; op2val:0x3af0; +op3val:0x780c; valaddr_reg:x8; val_offset:276*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 276*FLEN/8, x14, x4, x7) + +inst_117: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x060 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1b3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x061 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7860; op2val:0x39b3; +op3val:0x7861; valaddr_reg:x8; val_offset:279*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 279*FLEN/8, x14, x4, x7) + +inst_118: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x119 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x041 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x784d; op2val:0x3919; +op3val:0x7841; valaddr_reg:x8; val_offset:282*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 282*FLEN/8, x14, x4, x7) + +inst_119: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x05b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x249 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x049 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x785b; op2val:0x3649; +op3val:0x7849; valaddr_reg:x8; val_offset:285*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 285*FLEN/8, x14, x4, x7) + +inst_120: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x01e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x288 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x030 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1e; op2val:0xbe88; +op3val:0x30; valaddr_reg:x8; val_offset:288*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 288*FLEN/8, x14, x4, x7) + +inst_121: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x006 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6; op2val:0xc255; +op3val:0xb; valaddr_reg:x8; val_offset:291*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 291*FLEN/8, x14, x4, x7) + +inst_122: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x012 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x020 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x12; op2val:0xc155; +op3val:0x20; valaddr_reg:x8; val_offset:294*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 294*FLEN/8, x14, x4, x7) + +inst_123: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x034 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1a7 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x053 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34; op2val:0xc1a7; +op3val:0x53; valaddr_reg:x8; val_offset:297*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 297*FLEN/8, x14, x4, x7) + +inst_124: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x004 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x1d8 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x03b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4; op2val:0xd1d8; +op3val:0x3b; valaddr_reg:x8; val_offset:300*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 300*FLEN/8, x14, x4, x7) + +inst_125: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x11 and fm2 == 0x100 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x03b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f; op2val:0xc500; +op3val:0x3b; valaddr_reg:x8; val_offset:303*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 303*FLEN/8, x14, x4, x7) + +inst_126: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x032 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x1c2 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x040 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32; op2val:0xc9c2; +op3val:0x40; valaddr_reg:x8; val_offset:306*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 306*FLEN/8, x14, x4, x7) + +inst_127: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x034 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x227 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34; op2val:0xb227; +op3val:0xc; valaddr_reg:x8; val_offset:309*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 309*FLEN/8, x14, x4, x7) + +inst_128: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x05d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0dc and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5d; op2val:0x3cdc; +op3val:0xf; valaddr_reg:x8; val_offset:312*FLEN/8; rmval:dyn; +testreg:x7; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 312*FLEN/8, x14, x4, x7) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(30,32,FLEN) +NAN_BOXED(30,16,FLEN) +NAN_BOXED(48,32,FLEN) +NAN_BOXED(49,32,FLEN) +NAN_BOXED(46644,16,FLEN) +NAN_BOXED(17,32,FLEN) +NAN_BOXED(25,32,FLEN) +NAN_BOXED(50073,16,FLEN) +NAN_BOXED(91,32,FLEN) +NAN_BOXED(6,32,FLEN) +NAN_BOXED(49749,16,FLEN) +NAN_BOXED(6,32,FLEN) +NAN_BOXED(18,32,FLEN) +NAN_BOXED(18,16,FLEN) +NAN_BOXED(18,32,FLEN) +NAN_BOXED(65,32,FLEN) +NAN_BOXED(47938,16,FLEN) +NAN_BOXED(27,32,FLEN) +NAN_BOXED(52,32,FLEN) +NAN_BOXED(49575,16,FLEN) +NAN_BOXED(49575,32,FLEN) +NAN_BOXED(4,32,FLEN) +NAN_BOXED(53720,16,FLEN) +NAN_BOXED(4,32,FLEN) +NAN_BOXED(63,32,FLEN) +NAN_BOXED(63,16,FLEN) +NAN_BOXED(63,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64,32,FLEN) +NAN_BOXED(74,32,FLEN) +NAN_BOXED(46384,16,FLEN) +NAN_BOXED(25,32,FLEN) +NAN_BOXED(52,32,FLEN) +NAN_BOXED(45607,16,FLEN) +NAN_BOXED(45607,32,FLEN) +NAN_BOXED(63,32,FLEN) +NAN_BOXED(46746,16,FLEN) +NAN_BOXED(30,32,FLEN) +NAN_BOXED(98,32,FLEN) +NAN_BOXED(10887,32,FLEN) +NAN_BOXED(3,32,FLEN) +test_dataset_1: +NAN_BOXED(90,32,FLEN) +NAN_BOXED(45761,16,FLEN) +NAN_BOXED(35,32,FLEN) +NAN_BOXED(67,32,FLEN) +NAN_BOXED(46339,16,FLEN) +NAN_BOXED(53,32,FLEN) +NAN_BOXED(61,32,FLEN) +NAN_BOXED(13278,32,FLEN) +NAN_BOXED(49,32,FLEN) +NAN_BOXED(93,32,FLEN) +NAN_BOXED(15580,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(85,32,FLEN) +NAN_BOXED(16697,32,FLEN) +NAN_BOXED(34,32,FLEN) +NAN_BOXED(13,32,FLEN) +NAN_BOXED(20694,32,FLEN) +NAN_BOXED(9,32,FLEN) +NAN_BOXED(15410,32,FLEN) +NAN_BOXED(49133,16,FLEN) +NAN_BOXED(15440,32,FLEN) +NAN_BOXED(15409,32,FLEN) +NAN_BOXED(49073,16,FLEN) +NAN_BOXED(15374,32,FLEN) +NAN_BOXED(15445,32,FLEN) +NAN_BOXED(49006,16,FLEN) +NAN_BOXED(15368,32,FLEN) +NAN_BOXED(15404,32,FLEN) +NAN_BOXED(49105,16,FLEN) +NAN_BOXED(15391,32,FLEN) +test_dataset_2: +NAN_BOXED(15449,16,FLEN) +NAN_BOXED(49013,16,FLEN) +NAN_BOXED(15372,16,FLEN) +NAN_BOXED(15424,16,FLEN) +NAN_BOXED(49140,16,FLEN) +NAN_BOXED(15444,16,FLEN) +NAN_BOXED(15427,16,FLEN) +NAN_BOXED(49111,16,FLEN) +NAN_BOXED(15387,16,FLEN) +NAN_BOXED(15435,16,FLEN) +NAN_BOXED(49149,16,FLEN) +NAN_BOXED(15379,16,FLEN) +NAN_BOXED(15438,16,FLEN) +NAN_BOXED(49202,16,FLEN) +NAN_BOXED(15369,16,FLEN) +NAN_BOXED(15430,16,FLEN) +NAN_BOXED(49328,16,FLEN) +NAN_BOXED(15365,16,FLEN) +NAN_BOXED(15423,16,FLEN) +NAN_BOXED(44349,16,FLEN) +NAN_BOXED(15450,16,FLEN) +NAN_BOXED(15385,16,FLEN) +NAN_BOXED(42022,16,FLEN) +NAN_BOXED(15379,16,FLEN) +NAN_BOXED(15435,16,FLEN) +NAN_BOXED(43623,16,FLEN) +NAN_BOXED(15419,16,FLEN) +NAN_BOXED(15454,16,FLEN) +NAN_BOXED(43947,16,FLEN) +NAN_BOXED(15435,16,FLEN) +NAN_BOXED(15417,16,FLEN) +NAN_BOXED(42233,16,FLEN) +NAN_BOXED(15397,16,FLEN) +NAN_BOXED(15432,16,FLEN) +NAN_BOXED(41610,16,FLEN) +NAN_BOXED(15406,16,FLEN) +NAN_BOXED(15415,16,FLEN) +NAN_BOXED(10612,16,FLEN) +NAN_BOXED(15378,16,FLEN) +NAN_BOXED(15381,16,FLEN) +NAN_BOXED(10073,16,FLEN) +NAN_BOXED(15458,16,FLEN) +NAN_BOXED(15437,16,FLEN) +NAN_BOXED(13072,16,FLEN) +NAN_BOXED(15373,16,FLEN) +NAN_BOXED(15429,16,FLEN) +NAN_BOXED(13873,16,FLEN) +NAN_BOXED(15449,16,FLEN) +NAN_BOXED(41,16,FLEN) +NAN_BOXED(49264,16,FLEN) +NAN_BOXED(90,16,FLEN) +NAN_BOXED(46,16,FLEN) +NAN_BOXED(49018,16,FLEN) +NAN_BOXED(83,16,FLEN) +NAN_BOXED(64,16,FLEN) +NAN_BOXED(48224,16,FLEN) +NAN_BOXED(65,16,FLEN) +NAN_BOXED(80,16,FLEN) +NAN_BOXED(46848,16,FLEN) +NAN_BOXED(26,16,FLEN) +NAN_BOXED(40,16,FLEN) +NAN_BOXED(47974,16,FLEN) +NAN_BOXED(20,16,FLEN) +NAN_BOXED(46,16,FLEN) +NAN_BOXED(49252,16,FLEN) +NAN_BOXED(68,16,FLEN) +NAN_BOXED(37,16,FLEN) +NAN_BOXED(49940,16,FLEN) +NAN_BOXED(66,16,FLEN) +NAN_BOXED(85,16,FLEN) +NAN_BOXED(48778,16,FLEN) +NAN_BOXED(10,16,FLEN) +NAN_BOXED(65,16,FLEN) +NAN_BOXED(50518,16,FLEN) +NAN_BOXED(90,16,FLEN) +NAN_BOXED(70,16,FLEN) +NAN_BOXED(51134,16,FLEN) +NAN_BOXED(29,16,FLEN) +NAN_BOXED(45,16,FLEN) +NAN_BOXED(47490,16,FLEN) +NAN_BOXED(32,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(52320,16,FLEN) +NAN_BOXED(38,16,FLEN) +NAN_BOXED(44,16,FLEN) +NAN_BOXED(47197,16,FLEN) +NAN_BOXED(29,16,FLEN) +NAN_BOXED(35,16,FLEN) +NAN_BOXED(12112,16,FLEN) +NAN_BOXED(5,16,FLEN) +NAN_BOXED(55,16,FLEN) +NAN_BOXED(46247,16,FLEN) +NAN_BOXED(33,16,FLEN) +NAN_BOXED(49,16,FLEN) +NAN_BOXED(45014,16,FLEN) +NAN_BOXED(39,16,FLEN) +NAN_BOXED(91,16,FLEN) +NAN_BOXED(12220,16,FLEN) +NAN_BOXED(54,16,FLEN) +NAN_BOXED(23,16,FLEN) +NAN_BOXED(16294,16,FLEN) +NAN_BOXED(85,16,FLEN) +NAN_BOXED(51,16,FLEN) +NAN_BOXED(17598,16,FLEN) +NAN_BOXED(15,16,FLEN) +NAN_BOXED(22,16,FLEN) +NAN_BOXED(19677,16,FLEN) +NAN_BOXED(85,16,FLEN) +NAN_BOXED(4,16,FLEN) +NAN_BOXED(56344,16,FLEN) +NAN_BOXED(26,16,FLEN) +NAN_BOXED(99,16,FLEN) +NAN_BOXED(51523,16,FLEN) +NAN_BOXED(21,16,FLEN) +NAN_BOXED(39,16,FLEN) +NAN_BOXED(52896,16,FLEN) +NAN_BOXED(15,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(57433,16,FLEN) +NAN_BOXED(98,16,FLEN) +NAN_BOXED(49,16,FLEN) +NAN_BOXED(52572,16,FLEN) +NAN_BOXED(44,16,FLEN) +NAN_BOXED(22,16,FLEN) +NAN_BOXED(53771,16,FLEN) +NAN_BOXED(73,16,FLEN) +NAN_BOXED(56,16,FLEN) +NAN_BOXED(52330,16,FLEN) +NAN_BOXED(30,16,FLEN) +NAN_BOXED(18,16,FLEN) +NAN_BOXED(53909,16,FLEN) +NAN_BOXED(53,16,FLEN) +NAN_BOXED(73,16,FLEN) +NAN_BOXED(51622,16,FLEN) +NAN_BOXED(58,16,FLEN) +NAN_BOXED(53,16,FLEN) +NAN_BOXED(51540,16,FLEN) +NAN_BOXED(54,16,FLEN) +NAN_BOXED(11,16,FLEN) +NAN_BOXED(21856,16,FLEN) +NAN_BOXED(76,16,FLEN) +NAN_BOXED(9,16,FLEN) +NAN_BOXED(22229,16,FLEN) +NAN_BOXED(37,16,FLEN) +NAN_BOXED(92,16,FLEN) +NAN_BOXED(18807,16,FLEN) +NAN_BOXED(13,16,FLEN) +NAN_BOXED(5,16,FLEN) +NAN_BOXED(23110,16,FLEN) +NAN_BOXED(11,16,FLEN) +NAN_BOXED(85,16,FLEN) +NAN_BOXED(18903,16,FLEN) +NAN_BOXED(14,16,FLEN) +NAN_BOXED(98,16,FLEN) +NAN_BOXED(18614,16,FLEN) +NAN_BOXED(67,16,FLEN) +NAN_BOXED(68,16,FLEN) +NAN_BOXED(19124,16,FLEN) +NAN_BOXED(47,16,FLEN) +NAN_BOXED(20,16,FLEN) +NAN_BOXED(20784,16,FLEN) +NAN_BOXED(65,16,FLEN) +NAN_BOXED(63,16,FLEN) +NAN_BOXED(18781,16,FLEN) +NAN_BOXED(91,16,FLEN) +NAN_BOXED(20,16,FLEN) +NAN_BOXED(19817,16,FLEN) +NAN_BOXED(78,16,FLEN) +NAN_BOXED(1033,16,FLEN) +NAN_BOXED(49155,16,FLEN) +NAN_BOXED(1049,16,FLEN) +NAN_BOXED(1027,16,FLEN) +NAN_BOXED(49158,16,FLEN) +NAN_BOXED(1042,16,FLEN) +NAN_BOXED(1068,16,FLEN) +NAN_BOXED(49119,16,FLEN) +NAN_BOXED(1074,16,FLEN) +NAN_BOXED(1109,16,FLEN) +NAN_BOXED(49070,16,FLEN) +NAN_BOXED(1098,16,FLEN) +NAN_BOXED(1040,16,FLEN) +NAN_BOXED(49191,16,FLEN) +NAN_BOXED(1120,16,FLEN) +NAN_BOXED(1063,16,FLEN) +NAN_BOXED(49151,16,FLEN) +NAN_BOXED(1069,16,FLEN) +NAN_BOXED(1066,16,FLEN) +NAN_BOXED(49164,16,FLEN) +NAN_BOXED(1071,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(49256,16,FLEN) +NAN_BOXED(1107,16,FLEN) +NAN_BOXED(1088,16,FLEN) +NAN_BOXED(49224,16,FLEN) +NAN_BOXED(1051,16,FLEN) +NAN_BOXED(1032,16,FLEN) +NAN_BOXED(49437,16,FLEN) +NAN_BOXED(1104,16,FLEN) +NAN_BOXED(1029,16,FLEN) +NAN_BOXED(44552,16,FLEN) +NAN_BOXED(1122,16,FLEN) +NAN_BOXED(1099,16,FLEN) +NAN_BOXED(42212,16,FLEN) +NAN_BOXED(1047,16,FLEN) +NAN_BOXED(1047,16,FLEN) +NAN_BOXED(43235,16,FLEN) +NAN_BOXED(1068,16,FLEN) +NAN_BOXED(1080,16,FLEN) +NAN_BOXED(43470,16,FLEN) +NAN_BOXED(1081,16,FLEN) +NAN_BOXED(1040,16,FLEN) +NAN_BOXED(7404,16,FLEN) +NAN_BOXED(1035,16,FLEN) +NAN_BOXED(1050,16,FLEN) +NAN_BOXED(43419,16,FLEN) +NAN_BOXED(1102,16,FLEN) +NAN_BOXED(1053,16,FLEN) +NAN_BOXED(752,16,FLEN) +NAN_BOXED(1088,16,FLEN) +NAN_BOXED(1085,16,FLEN) +NAN_BOXED(11870,16,FLEN) +NAN_BOXED(1044,16,FLEN) +NAN_BOXED(1073,16,FLEN) +NAN_BOXED(13096,16,FLEN) +NAN_BOXED(1040,16,FLEN) +NAN_BOXED(1038,16,FLEN) +NAN_BOXED(14012,16,FLEN) +NAN_BOXED(1099,16,FLEN) +NAN_BOXED(30813,16,FLEN) +NAN_BOXED(49561,16,FLEN) +NAN_BOXED(30778,16,FLEN) +NAN_BOXED(30803,16,FLEN) +NAN_BOXED(49555,16,FLEN) +NAN_BOXED(30737,16,FLEN) +NAN_BOXED(30813,16,FLEN) +NAN_BOXED(49559,16,FLEN) +NAN_BOXED(30777,16,FLEN) +NAN_BOXED(30786,16,FLEN) +NAN_BOXED(49610,16,FLEN) +NAN_BOXED(30813,16,FLEN) +NAN_BOXED(30732,16,FLEN) +NAN_BOXED(49683,16,FLEN) +NAN_BOXED(30812,16,FLEN) +NAN_BOXED(30781,16,FLEN) +NAN_BOXED(49596,16,FLEN) +NAN_BOXED(30793,16,FLEN) +NAN_BOXED(30771,16,FLEN) +NAN_BOXED(49582,16,FLEN) +NAN_BOXED(30767,16,FLEN) +NAN_BOXED(30779,16,FLEN) +NAN_BOXED(49533,16,FLEN) +NAN_BOXED(30749,16,FLEN) +NAN_BOXED(30727,16,FLEN) +NAN_BOXED(49538,16,FLEN) +NAN_BOXED(30746,16,FLEN) +NAN_BOXED(30727,16,FLEN) +NAN_BOXED(49427,16,FLEN) +NAN_BOXED(30778,16,FLEN) +NAN_BOXED(30735,16,FLEN) +NAN_BOXED(15298,16,FLEN) +NAN_BOXED(30734,16,FLEN) +NAN_BOXED(30748,16,FLEN) +NAN_BOXED(15118,16,FLEN) +NAN_BOXED(30813,16,FLEN) +NAN_BOXED(30721,16,FLEN) +NAN_BOXED(15166,16,FLEN) +NAN_BOXED(30811,16,FLEN) +NAN_BOXED(30797,16,FLEN) +NAN_BOXED(15053,16,FLEN) +NAN_BOXED(30799,16,FLEN) +NAN_BOXED(30723,16,FLEN) +NAN_BOXED(15152,16,FLEN) +NAN_BOXED(30804,16,FLEN) +NAN_BOXED(30767,16,FLEN) +NAN_BOXED(15099,16,FLEN) +NAN_BOXED(30776,16,FLEN) +NAN_BOXED(30788,16,FLEN) +NAN_BOXED(15088,16,FLEN) +NAN_BOXED(30732,16,FLEN) +NAN_BOXED(30816,16,FLEN) +NAN_BOXED(14771,16,FLEN) +NAN_BOXED(30817,16,FLEN) +NAN_BOXED(30797,16,FLEN) +NAN_BOXED(14617,16,FLEN) +NAN_BOXED(30785,16,FLEN) +NAN_BOXED(30811,16,FLEN) +NAN_BOXED(13897,16,FLEN) +NAN_BOXED(30793,16,FLEN) +NAN_BOXED(30,16,FLEN) +NAN_BOXED(48776,16,FLEN) +NAN_BOXED(48,16,FLEN) +NAN_BOXED(6,16,FLEN) +NAN_BOXED(49749,16,FLEN) +NAN_BOXED(11,16,FLEN) +NAN_BOXED(18,16,FLEN) +NAN_BOXED(49493,16,FLEN) +NAN_BOXED(32,16,FLEN) +NAN_BOXED(52,16,FLEN) +NAN_BOXED(49575,16,FLEN) +NAN_BOXED(83,16,FLEN) +NAN_BOXED(4,16,FLEN) +NAN_BOXED(53720,16,FLEN) +NAN_BOXED(59,16,FLEN) +NAN_BOXED(63,16,FLEN) +NAN_BOXED(50432,16,FLEN) +NAN_BOXED(59,16,FLEN) +NAN_BOXED(50,16,FLEN) +NAN_BOXED(51650,16,FLEN) +NAN_BOXED(64,16,FLEN) +NAN_BOXED(52,16,FLEN) +NAN_BOXED(45607,16,FLEN) +NAN_BOXED(12,16,FLEN) +NAN_BOXED(93,16,FLEN) +NAN_BOXED(15580,16,FLEN) +NAN_BOXED(15,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x3_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x3_1: + .fill 34*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x4_0: + .fill 26*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x4_1: + .fill 198*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fnmsub_b3-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fnmsub_b3-01.S new file mode 100644 index 000000000..69265e7c7 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fnmsub_b3-01.S @@ -0,0 +1,11454 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 06:07:02 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fnmsub.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fnmsub.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fnmsub_b3 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fnmsub_b3) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x11,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==x22, rs2==x22, rs3==x1, rd==x15,fs1 == 0 and fe1 == 0x1c and fm1 == 0x340 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x03e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x22; op2:x22; op3:x1; dest:x15; op1val:0x7340; op2val:0x7340; +op3val:0x7bb1; valaddr_reg:x11; val_offset:0*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x15, x22, x22, x1, dyn, 0, 0, x11, 0*FLEN/8, x13, x1, x5) + +inst_1: +// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==x29, rs2==x10, rs3==x6, rd==x29,fs1 == 0 and fe1 == 0x1c and fm1 == 0x340 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x03e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x29; op2:x10; op3:x6; dest:x29; op1val:0x7340; op2val:0xc43e; +op3val:0x7bb1; valaddr_reg:x11; val_offset:3*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x29, x29, x10, x6, dyn, 32, 0, x11, 3*FLEN/8, x13, x1, x5) + +inst_2: +// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==x20, rs2==x7, rs3==x17, rd==x23,fs1 == 0 and fe1 == 0x1c and fm1 == 0x340 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x03e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x20; op2:x7; op3:x17; dest:x23; op1val:0x7340; op2val:0xc43e; +op3val:0x7bb1; valaddr_reg:x11; val_offset:6*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x23, x20, x7, x17, dyn, 64, 0, x11, 6*FLEN/8, x13, x1, x5) + +inst_3: +// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==x27, rs2==x20, rs3==x27, rd==x0,fs1 == 0 and fe1 == 0x1c and fm1 == 0x340 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x03e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x27; op2:x20; op3:x27; dest:x0; op1val:0x7340; op2val:0xc43e; +op3val:0x7340; valaddr_reg:x11; val_offset:9*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x0, x27, x20, x27, dyn, 96, 0, x11, 9*FLEN/8, x13, x1, x5) + +inst_4: +// rs1 == rs2 == rs3 != rd, rs1==x25, rs2==x25, rs3==x25, rd==x26,fs1 == 0 and fe1 == 0x1c and fm1 == 0x340 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x03e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x25; op2:x25; op3:x25; dest:x26; op1val:0x7340; op2val:0x7340; +op3val:0x7340; valaddr_reg:x11; val_offset:12*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x26, x25, x25, x25, dyn, 128, 0, x11, 12*FLEN/8, x13, x1, x5) + +inst_5: +// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==x17, rs2==x3, rs3==x2, rd==x2,fs1 == 0 and fe1 == 0x1c and fm1 == 0x00a and fs2 == 1 and fe2 == 0x11 and fm2 == 0x194 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x17; op2:x3; op3:x2; dest:x2; op1val:0x700a; op2val:0xc594; +op3val:0x79a2; valaddr_reg:x11; val_offset:15*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x2, x17, x3, x2, dyn, 0, 0, x11, 15*FLEN/8, x13, x1, x5) + +inst_6: +// rd == rs2 == rs3 != rs1, rs1==x9, rs2==x28, rs3==x28, rd==x28,fs1 == 0 and fe1 == 0x1c and fm1 == 0x00a and fs2 == 1 and fe2 == 0x11 and fm2 == 0x194 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x9; op2:x28; op3:x28; dest:x28; op1val:0x700a; op2val:0xc594; +op3val:0xc594; valaddr_reg:x11; val_offset:18*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x28, x9, x28, x28, dyn, 32, 0, x11, 18*FLEN/8, x13, x1, x5) + +inst_7: +// rs1 == rd == rs3 != rs2, rs1==x3, rs2==x23, rs3==x3, rd==x3,fs1 == 0 and fe1 == 0x1c and fm1 == 0x00a and fs2 == 1 and fe2 == 0x11 and fm2 == 0x194 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x3; op2:x23; op3:x3; dest:x3; op1val:0x700a; op2val:0xc594; +op3val:0x700a; valaddr_reg:x11; val_offset:21*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x3, x3, x23, x3, dyn, 64, 0, x11, 21*FLEN/8, x13, x1, x5) + +inst_8: +// rs1 == rs2 == rs3 == rd, rs1==x8, rs2==x8, rs3==x8, rd==x8,fs1 == 0 and fe1 == 0x1c and fm1 == 0x00a and fs2 == 1 and fe2 == 0x11 and fm2 == 0x194 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x8; op2:x8; op3:x8; dest:x8; op1val:0x700a; op2val:0x700a; +op3val:0x700a; valaddr_reg:x11; val_offset:24*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x8, x8, x8, x8, dyn, 96, 0, x11, 24*FLEN/8, x13, x1, x5) + +inst_9: +// rs1 == rs2 == rd != rs3, rs1==x6, rs2==x6, rs3==x24, rd==x6,fs1 == 0 and fe1 == 0x1c and fm1 == 0x00a and fs2 == 1 and fe2 == 0x11 and fm2 == 0x194 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x6; op2:x6; op3:x24; dest:x6; op1val:0x700a; op2val:0x700a; +op3val:0x79a2; valaddr_reg:x11; val_offset:27*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x6, x6, x6, x24, dyn, 128, 0, x11, 27*FLEN/8, x13, x1, x5) + +inst_10: +// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==x26, rs2==x4, rs3==x10, rd==x4,fs1 == 0 and fe1 == 0x1b and fm1 == 0x173 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1cf and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3ea and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x26; op2:x4; op3:x10; dest:x4; op1val:0x6d73; op2val:0xc1cf; +op3val:0x73ea; valaddr_reg:x11; val_offset:30*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x4, x26, x4, x10, dyn, 0, 0, x11, 30*FLEN/8, x13, x1, x5) + +inst_11: +// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==x21, rs2==x31, rs3==x31, rd==x12,fs1 == 0 and fe1 == 0x1b and fm1 == 0x173 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1cf and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3ea and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x21; op2:x31; op3:x31; dest:x12; op1val:0x6d73; op2val:0xc1cf; +op3val:0xc1cf; valaddr_reg:x11; val_offset:33*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x12, x21, x31, x31, dyn, 32, 0, x11, 33*FLEN/8, x13, x1, x5) + +inst_12: +// rs1==x0, rs2==x26, rs3==x7, rd==x18,fs1 == 0 and fe1 == 0x1b and fm1 == 0x173 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1cf and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3ea and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x0; op2:x26; op3:x7; dest:x18; op1val:0x0; op2val:0xc1cf; +op3val:0x73ea; valaddr_reg:x11; val_offset:36*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x18, x0, x26, x7, dyn, 64, 0, x11, 36*FLEN/8, x13, x1, x5) +RVTEST_VALBASEUPD(x8,test_dataset_1) + +inst_13: +// rs1==x19, rs2==x16, rs3==x9, rd==x13,fs1 == 0 and fe1 == 0x1b and fm1 == 0x173 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1cf and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3ea and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x19; op2:x16; op3:x9; dest:x13; op1val:0x6d73; op2val:0xc1cf; +op3val:0x73ea; valaddr_reg:x8; val_offset:0*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x13, x19, x16, x9, dyn, 96, 0, x8, 0*FLEN/8, x20, x1, x5) +RVTEST_SIGBASE(x3,signature_x3_0) + +inst_14: +// rs1==x4, rs2==x21, rs3==x19, rd==x16,fs1 == 0 and fe1 == 0x1b and fm1 == 0x173 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1cf and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3ea and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x4; op2:x21; op3:x19; dest:x16; op1val:0x6d73; op2val:0xc1cf; +op3val:0x73ea; valaddr_reg:x8; val_offset:3*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x16, x4, x21, x19, dyn, 128, 0, x8, 3*FLEN/8, x20, x3, x6) + +inst_15: +// rs1==x24, rs2==x15, rs3==x14, rd==x22,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3fd and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2b4 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2b2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x24; op2:x15; op3:x14; dest:x22; op1val:0x7bfd; op2val:0xb2b4; +op3val:0x72b2; valaddr_reg:x8; val_offset:6*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x22, x24, x15, x14, dyn, 0, 0, x8, 6*FLEN/8, x20, x3, x6) + +inst_16: +// rs1==x2, rs2==x18, rs3==x30, rd==x25,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3fd and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2b4 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2b2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x2; op2:x18; op3:x30; dest:x25; op1val:0x7bfd; op2val:0xb2b4; +op3val:0x72b2; valaddr_reg:x8; val_offset:9*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x25, x2, x18, x30, dyn, 32, 0, x8, 9*FLEN/8, x20, x3, x6) + +inst_17: +// rs1==x13, rs2==x14, rs3==x23, rd==x27,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3fd and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2b4 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2b2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x13; op2:x14; op3:x23; dest:x27; op1val:0x7bfd; op2val:0xb2b4; +op3val:0x72b2; valaddr_reg:x8; val_offset:12*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x27, x13, x14, x23, dyn, 64, 0, x8, 12*FLEN/8, x20, x3, x6) + +inst_18: +// rs1==x10, rs2==x1, rs3==x0, rd==x9,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3fd and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2b4 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2b2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x10; op2:x1; op3:x0; dest:x9; op1val:0x7bfd; op2val:0xb2b4; +op3val:0x0; valaddr_reg:x8; val_offset:15*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x9, x10, x1, x0, dyn, 96, 0, x8, 15*FLEN/8, x20, x3, x6) + +inst_19: +// rs1==x15, rs2==x17, rs3==x29, rd==x1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3fd and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2b4 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2b2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x15; op2:x17; op3:x29; dest:x1; op1val:0x7bfd; op2val:0xb2b4; +op3val:0x72b2; valaddr_reg:x8; val_offset:18*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x1, x15, x17, x29, dyn, 128, 0, x8, 18*FLEN/8, x20, x3, x6) + +inst_20: +// rs1==x16, rs2==x12, rs3==x13, rd==x10,fs1 == 0 and fe1 == 0x1e and fm1 == 0x121 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1b8 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x357 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x16; op2:x12; op3:x13; dest:x10; op1val:0x7921; op2val:0xb9b8; +op3val:0x7757; valaddr_reg:x8; val_offset:21*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x10, x16, x12, x13, dyn, 0, 0, x8, 21*FLEN/8, x20, x3, x6) + +inst_21: +// rs1==x1, rs2==x13, rs3==x20, rd==x21,fs1 == 0 and fe1 == 0x1e and fm1 == 0x121 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1b8 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x357 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x1; op2:x13; op3:x20; dest:x21; op1val:0x7921; op2val:0xb9b8; +op3val:0x7757; valaddr_reg:x8; val_offset:24*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x21, x1, x13, x20, dyn, 32, 0, x8, 24*FLEN/8, x20, x3, x6) + +inst_22: +// rs1==x5, rs2==x19, rs3==x12, rd==x11,fs1 == 0 and fe1 == 0x1e and fm1 == 0x121 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1b8 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x357 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x5; op2:x19; op3:x12; dest:x11; op1val:0x7921; op2val:0xb9b8; +op3val:0x7757; valaddr_reg:x8; val_offset:27*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x11, x5, x19, x12, dyn, 64, 0, x8, 27*FLEN/8, x20, x3, x6) + +inst_23: +// rs1==x7, rs2==x30, rs3==x22, rd==x24,fs1 == 0 and fe1 == 0x1e and fm1 == 0x121 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1b8 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x357 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x7; op2:x30; op3:x22; dest:x24; op1val:0x7921; op2val:0xb9b8; +op3val:0x7757; valaddr_reg:x8; val_offset:30*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x24, x7, x30, x22, dyn, 96, 0, x8, 30*FLEN/8, x20, x3, x6) +RVTEST_VALBASEUPD(x8,test_dataset_2) + +inst_24: +// rs1==x30, rs2==x11, rs3==x26, rd==x7,fs1 == 0 and fe1 == 0x1e and fm1 == 0x121 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1b8 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x357 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x11; op3:x26; dest:x7; op1val:0x7921; op2val:0xb9b8; +op3val:0x7757; valaddr_reg:x8; val_offset:0*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x7, x30, x11, x26, dyn, 128, 0, x8, 0*FLEN/8, x10, x3, x6) + +inst_25: +// rs1==x23, rs2==x27, rs3==x18, rd==x19,fs1 == 0 and fe1 == 0x1d and fm1 == 0x33f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x05e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3ea and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x23; op2:x27; op3:x18; dest:x19; op1val:0x773f; op2val:0xbc5e; +op3val:0x77ea; valaddr_reg:x8; val_offset:3*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x19, x23, x27, x18, dyn, 0, 0, x8, 3*FLEN/8, x10, x3, x6) + +inst_26: +// rs1==x14, rs2==x29, rs3==x4, rd==x5,fs1 == 0 and fe1 == 0x1d and fm1 == 0x33f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x05e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3ea and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x14; op2:x29; op3:x4; dest:x5; op1val:0x773f; op2val:0xbc5e; +op3val:0x77ea; valaddr_reg:x8; val_offset:6*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x5, x14, x29, x4, dyn, 32, 0, x8, 6*FLEN/8, x10, x3, x6) + +inst_27: +// rs1==x12, rs2==x9, rs3==x11, rd==x30,fs1 == 0 and fe1 == 0x1d and fm1 == 0x33f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x05e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3ea and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x12; op2:x9; op3:x11; dest:x30; op1val:0x773f; op2val:0xbc5e; +op3val:0x77ea; valaddr_reg:x8; val_offset:9*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x30, x12, x9, x11, dyn, 64, 0, x8, 9*FLEN/8, x10, x3, x4) + +inst_28: +// rs1==x18, rs2==x5, rs3==x21, rd==x14,fs1 == 0 and fe1 == 0x1d and fm1 == 0x33f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x05e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3ea and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x18; op2:x5; op3:x21; dest:x14; op1val:0x773f; op2val:0xbc5e; +op3val:0x77ea; valaddr_reg:x8; val_offset:12*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x14, x18, x5, x21, dyn, 96, 0, x8, 12*FLEN/8, x10, x3, x4) + +inst_29: +// rs1==x31, rs2==x0, rs3==x15, rd==x17,fs1 == 0 and fe1 == 0x1d and fm1 == 0x33f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x05e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3ea and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x31; op2:x0; op3:x15; dest:x17; op1val:0x773f; op2val:0x0; +op3val:0x77ea; valaddr_reg:x8; val_offset:15*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x17, x31, x0, x15, dyn, 128, 0, x8, 15*FLEN/8, x10, x3, x4) +RVTEST_SIGBASE(x1,signature_x1_2) + +inst_30: +// rs1==x11, rs2==x24, rs3==x16, rd==x31,fs1 == 0 and fe1 == 0x1c and fm1 == 0x226 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x051 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x11; op2:x24; op3:x16; dest:x31; op1val:0x7226; op2val:0xc451; +op3val:0x7aa4; valaddr_reg:x8; val_offset:18*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x11, x24, x16, dyn, 0, 0, x8, 18*FLEN/8, x10, x1, x4) + +inst_31: +// rs1==x28, rs2==x2, rs3==x5, rd==x20,fs1 == 0 and fe1 == 0x1c and fm1 == 0x226 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x051 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x28; op2:x2; op3:x5; dest:x20; op1val:0x7226; op2val:0xc451; +op3val:0x7aa4; valaddr_reg:x8; val_offset:21*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x20, x28, x2, x5, dyn, 32, 0, x8, 21*FLEN/8, x10, x1, x4) + +inst_32: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x226 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x051 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7226; op2val:0xc451; +op3val:0x7aa4; valaddr_reg:x8; val_offset:24*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 24*FLEN/8, x10, x1, x4) + +inst_33: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x226 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x051 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7226; op2val:0xc451; +op3val:0x7aa4; valaddr_reg:x8; val_offset:27*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 27*FLEN/8, x10, x1, x4) + +inst_34: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x226 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x051 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7226; op2val:0xc451; +op3val:0x7aa4; valaddr_reg:x8; val_offset:30*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 30*FLEN/8, x10, x1, x4) + +inst_35: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ba and fs2 == 1 and fe2 == 0x10 and fm2 == 0x13a and fs3 == 0 and fe3 == 0x1c and fm3 == 0x37d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dba; op2val:0xc13a; +op3val:0x737d; valaddr_reg:x8; val_offset:33*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 33*FLEN/8, x10, x1, x4) + +inst_36: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ba and fs2 == 1 and fe2 == 0x10 and fm2 == 0x13a and fs3 == 0 and fe3 == 0x1c and fm3 == 0x37d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dba; op2val:0xc13a; +op3val:0x737d; valaddr_reg:x8; val_offset:36*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 36*FLEN/8, x10, x1, x4) + +inst_37: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ba and fs2 == 1 and fe2 == 0x10 and fm2 == 0x13a and fs3 == 0 and fe3 == 0x1c and fm3 == 0x37d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dba; op2val:0xc13a; +op3val:0x737d; valaddr_reg:x8; val_offset:39*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 39*FLEN/8, x10, x1, x4) + +inst_38: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ba and fs2 == 1 and fe2 == 0x10 and fm2 == 0x13a and fs3 == 0 and fe3 == 0x1c and fm3 == 0x37d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dba; op2val:0xc13a; +op3val:0x737d; valaddr_reg:x8; val_offset:42*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 42*FLEN/8, x10, x1, x4) + +inst_39: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ba and fs2 == 1 and fe2 == 0x10 and fm2 == 0x13a and fs3 == 0 and fe3 == 0x1c and fm3 == 0x37d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dba; op2val:0xc13a; +op3val:0x737d; valaddr_reg:x8; val_offset:45*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 45*FLEN/8, x10, x1, x4) + +inst_40: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x11e and fs2 == 1 and fe2 == 0x12 and fm2 == 0x2aa and fs3 == 0 and fe3 == 0x1d and fm3 == 0x044 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x651e; op2val:0xcaaa; +op3val:0x7444; valaddr_reg:x8; val_offset:48*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 48*FLEN/8, x10, x1, x4) + +inst_41: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x11e and fs2 == 1 and fe2 == 0x12 and fm2 == 0x2aa and fs3 == 0 and fe3 == 0x1d and fm3 == 0x044 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x651e; op2val:0xcaaa; +op3val:0x7444; valaddr_reg:x8; val_offset:51*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 51*FLEN/8, x10, x1, x4) + +inst_42: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x11e and fs2 == 1 and fe2 == 0x12 and fm2 == 0x2aa and fs3 == 0 and fe3 == 0x1d and fm3 == 0x044 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x651e; op2val:0xcaaa; +op3val:0x7444; valaddr_reg:x8; val_offset:54*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 54*FLEN/8, x10, x1, x4) + +inst_43: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x11e and fs2 == 1 and fe2 == 0x12 and fm2 == 0x2aa and fs3 == 0 and fe3 == 0x1d and fm3 == 0x044 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x651e; op2val:0xcaaa; +op3val:0x7444; valaddr_reg:x8; val_offset:57*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 57*FLEN/8, x10, x1, x4) + +inst_44: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x11e and fs2 == 1 and fe2 == 0x12 and fm2 == 0x2aa and fs3 == 0 and fe3 == 0x1d and fm3 == 0x044 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x651e; op2val:0xcaaa; +op3val:0x7444; valaddr_reg:x8; val_offset:60*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 60*FLEN/8, x10, x1, x4) + +inst_45: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x285 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x06c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x336 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7685; op2val:0xc06c; +op3val:0x7b36; valaddr_reg:x8; val_offset:63*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 63*FLEN/8, x10, x1, x4) + +inst_46: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x285 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x06c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x336 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7685; op2val:0xc06c; +op3val:0x7b36; valaddr_reg:x8; val_offset:66*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 66*FLEN/8, x10, x1, x4) + +inst_47: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x285 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x06c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x336 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7685; op2val:0xc06c; +op3val:0x7b36; valaddr_reg:x8; val_offset:69*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 69*FLEN/8, x10, x1, x4) + +inst_48: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x285 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x06c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x336 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7685; op2val:0xc06c; +op3val:0x7b36; valaddr_reg:x8; val_offset:72*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 72*FLEN/8, x10, x1, x4) + +inst_49: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x285 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x06c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x336 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7685; op2val:0xc06c; +op3val:0x7b36; valaddr_reg:x8; val_offset:75*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 75*FLEN/8, x10, x1, x4) + +inst_50: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x20f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0cd and fs3 == 0 and fe3 == 0x1b and fm3 == 0x346 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x760f; op2val:0xb4cd; +op3val:0x6f46; valaddr_reg:x8; val_offset:78*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 78*FLEN/8, x10, x1, x4) + +inst_51: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x20f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0cd and fs3 == 0 and fe3 == 0x1b and fm3 == 0x346 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x760f; op2val:0xb4cd; +op3val:0x6f46; valaddr_reg:x8; val_offset:81*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 81*FLEN/8, x10, x1, x4) + +inst_52: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x20f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0cd and fs3 == 0 and fe3 == 0x1b and fm3 == 0x346 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x760f; op2val:0xb4cd; +op3val:0x6f46; valaddr_reg:x8; val_offset:84*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 84*FLEN/8, x10, x1, x4) + +inst_53: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x20f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0cd and fs3 == 0 and fe3 == 0x1b and fm3 == 0x346 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x760f; op2val:0xb4cd; +op3val:0x6f46; valaddr_reg:x8; val_offset:87*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 87*FLEN/8, x10, x1, x4) + +inst_54: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x20f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0cd and fs3 == 0 and fe3 == 0x1b and fm3 == 0x346 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x760f; op2val:0xb4cd; +op3val:0x6f46; valaddr_reg:x8; val_offset:90*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 90*FLEN/8, x10, x1, x4) + +inst_55: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x021 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3ad and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ed and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7421; op2val:0xc3ad; +op3val:0x7bed; valaddr_reg:x8; val_offset:93*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 93*FLEN/8, x10, x1, x4) + +inst_56: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x021 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3ad and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ed and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7421; op2val:0xc3ad; +op3val:0x7bed; valaddr_reg:x8; val_offset:96*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 96*FLEN/8, x10, x1, x4) + +inst_57: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x021 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3ad and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ed and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7421; op2val:0xc3ad; +op3val:0x7bed; valaddr_reg:x8; val_offset:99*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 99*FLEN/8, x10, x1, x4) + +inst_58: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x021 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3ad and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ed and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7421; op2val:0xc3ad; +op3val:0x7bed; valaddr_reg:x8; val_offset:102*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 102*FLEN/8, x10, x1, x4) + +inst_59: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x021 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3ad and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ed and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7421; op2val:0xc3ad; +op3val:0x7bed; valaddr_reg:x8; val_offset:105*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 105*FLEN/8, x10, x1, x4) + +inst_60: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x009 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0e9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0f5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c09; op2val:0xc8e9; +op3val:0x78f5; valaddr_reg:x8; val_offset:108*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 108*FLEN/8, x10, x1, x4) + +inst_61: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x009 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0e9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0f5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c09; op2val:0xc8e9; +op3val:0x78f5; valaddr_reg:x8; val_offset:111*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 111*FLEN/8, x10, x1, x4) + +inst_62: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x009 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0e9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0f5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c09; op2val:0xc8e9; +op3val:0x78f5; valaddr_reg:x8; val_offset:114*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 114*FLEN/8, x10, x1, x4) + +inst_63: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x009 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0e9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0f5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c09; op2val:0xc8e9; +op3val:0x78f5; valaddr_reg:x8; val_offset:117*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 117*FLEN/8, x10, x1, x4) + +inst_64: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x009 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0e9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0f5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c09; op2val:0xc8e9; +op3val:0x78f5; valaddr_reg:x8; val_offset:120*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 120*FLEN/8, x10, x1, x4) + +inst_65: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x208 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x301 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x148 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7608; op2val:0xbf01; +op3val:0x7948; valaddr_reg:x8; val_offset:123*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 123*FLEN/8, x10, x1, x4) + +inst_66: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x208 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x301 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x148 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7608; op2val:0xbf01; +op3val:0x7948; valaddr_reg:x8; val_offset:126*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 126*FLEN/8, x10, x1, x4) + +inst_67: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x208 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x301 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x148 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7608; op2val:0xbf01; +op3val:0x7948; valaddr_reg:x8; val_offset:129*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 129*FLEN/8, x10, x1, x4) + +inst_68: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x208 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x301 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x148 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7608; op2val:0xbf01; +op3val:0x7948; valaddr_reg:x8; val_offset:132*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 132*FLEN/8, x10, x1, x4) + +inst_69: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x208 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x301 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x148 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7608; op2val:0xbf01; +op3val:0x7948; valaddr_reg:x8; val_offset:135*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 135*FLEN/8, x10, x1, x4) + +inst_70: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x169 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x015 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x187 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7569; op2val:0xc015; +op3val:0x7987; valaddr_reg:x8; val_offset:138*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 138*FLEN/8, x10, x1, x4) + +inst_71: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x169 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x015 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x187 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7569; op2val:0xc015; +op3val:0x7987; valaddr_reg:x8; val_offset:141*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 141*FLEN/8, x10, x1, x4) + +inst_72: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x169 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x015 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x187 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7569; op2val:0xc015; +op3val:0x7987; valaddr_reg:x8; val_offset:144*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 144*FLEN/8, x10, x1, x4) + +inst_73: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x169 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x015 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x187 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7569; op2val:0xc015; +op3val:0x7987; valaddr_reg:x8; val_offset:147*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 147*FLEN/8, x10, x1, x4) + +inst_74: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x169 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x015 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x187 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7569; op2val:0xc015; +op3val:0x7987; valaddr_reg:x8; val_offset:150*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 150*FLEN/8, x10, x1, x4) + +inst_75: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3f5 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x139 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x131 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77f5; op2val:0xbd39; +op3val:0x7931; valaddr_reg:x8; val_offset:153*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 153*FLEN/8, x10, x1, x4) + +inst_76: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3f5 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x139 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x131 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77f5; op2val:0xbd39; +op3val:0x7931; valaddr_reg:x8; val_offset:156*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 156*FLEN/8, x10, x1, x4) + +inst_77: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3f5 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x139 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x131 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77f5; op2val:0xbd39; +op3val:0x7931; valaddr_reg:x8; val_offset:159*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 159*FLEN/8, x10, x1, x4) + +inst_78: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3f5 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x139 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x131 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77f5; op2val:0xbd39; +op3val:0x7931; valaddr_reg:x8; val_offset:162*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 162*FLEN/8, x10, x1, x4) + +inst_79: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3f5 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x139 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x131 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77f5; op2val:0xbd39; +op3val:0x7931; valaddr_reg:x8; val_offset:165*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 165*FLEN/8, x10, x1, x4) + +inst_80: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x335 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x129 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b35; op2val:0xb929; +op3val:0x78a6; valaddr_reg:x8; val_offset:168*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 168*FLEN/8, x10, x1, x4) + +inst_81: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x335 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x129 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b35; op2val:0xb929; +op3val:0x78a6; valaddr_reg:x8; val_offset:171*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 171*FLEN/8, x10, x1, x4) + +inst_82: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x335 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x129 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b35; op2val:0xb929; +op3val:0x78a6; valaddr_reg:x8; val_offset:174*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 174*FLEN/8, x10, x1, x4) + +inst_83: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x335 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x129 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b35; op2val:0xb929; +op3val:0x78a6; valaddr_reg:x8; val_offset:177*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 177*FLEN/8, x10, x1, x4) + +inst_84: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x335 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x129 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b35; op2val:0xb929; +op3val:0x78a6; valaddr_reg:x8; val_offset:180*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 180*FLEN/8, x10, x1, x4) + +inst_85: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x08b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x33f and fs3 == 0 and fe3 == 0x1b and fm3 == 0x01e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x708b; op2val:0xb73f; +op3val:0x6c1e; valaddr_reg:x8; val_offset:183*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 183*FLEN/8, x10, x1, x4) + +inst_86: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x08b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x33f and fs3 == 0 and fe3 == 0x1b and fm3 == 0x01e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x708b; op2val:0xb73f; +op3val:0x6c1e; valaddr_reg:x8; val_offset:186*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 186*FLEN/8, x10, x1, x4) + +inst_87: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x08b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x33f and fs3 == 0 and fe3 == 0x1b and fm3 == 0x01e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x708b; op2val:0xb73f; +op3val:0x6c1e; valaddr_reg:x8; val_offset:189*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 189*FLEN/8, x10, x1, x4) + +inst_88: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x08b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x33f and fs3 == 0 and fe3 == 0x1b and fm3 == 0x01e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x708b; op2val:0xb73f; +op3val:0x6c1e; valaddr_reg:x8; val_offset:192*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 192*FLEN/8, x10, x1, x4) + +inst_89: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x08b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x33f and fs3 == 0 and fe3 == 0x1b and fm3 == 0x01e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x708b; op2val:0xb73f; +op3val:0x6c1e; valaddr_reg:x8; val_offset:195*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 195*FLEN/8, x10, x1, x4) + +inst_90: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x390 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x021 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3d0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b90; op2val:0xb821; +op3val:0x77d0; valaddr_reg:x8; val_offset:198*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 198*FLEN/8, x10, x1, x4) + +inst_91: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x390 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x021 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3d0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b90; op2val:0xb821; +op3val:0x77d0; valaddr_reg:x8; val_offset:201*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 201*FLEN/8, x10, x1, x4) + +inst_92: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x390 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x021 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3d0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b90; op2val:0xb821; +op3val:0x77d0; valaddr_reg:x8; val_offset:204*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 204*FLEN/8, x10, x1, x4) + +inst_93: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x390 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x021 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3d0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b90; op2val:0xb821; +op3val:0x77d0; valaddr_reg:x8; val_offset:207*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 207*FLEN/8, x10, x1, x4) + +inst_94: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x390 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x021 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3d0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b90; op2val:0xb821; +op3val:0x77d0; valaddr_reg:x8; val_offset:210*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 210*FLEN/8, x10, x1, x4) + +inst_95: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x233 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x390 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7233; op2val:0xc4e1; +op3val:0x7b90; valaddr_reg:x8; val_offset:213*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 213*FLEN/8, x10, x1, x4) + +inst_96: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x233 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x390 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7233; op2val:0xc4e1; +op3val:0x7b90; valaddr_reg:x8; val_offset:216*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 216*FLEN/8, x10, x1, x4) + +inst_97: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x233 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x390 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7233; op2val:0xc4e1; +op3val:0x7b90; valaddr_reg:x8; val_offset:219*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 219*FLEN/8, x10, x1, x4) + +inst_98: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x233 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x390 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7233; op2val:0xc4e1; +op3val:0x7b90; valaddr_reg:x8; val_offset:222*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 222*FLEN/8, x10, x1, x4) + +inst_99: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x233 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x390 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7233; op2val:0xc4e1; +op3val:0x7b90; valaddr_reg:x8; val_offset:225*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 225*FLEN/8, x10, x1, x4) + +inst_100: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a1 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x109 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1d4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78a1; op2val:0xbd09; +op3val:0x79d4; valaddr_reg:x8; val_offset:228*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 228*FLEN/8, x10, x1, x4) + +inst_101: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a1 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x109 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1d4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78a1; op2val:0xbd09; +op3val:0x79d4; valaddr_reg:x8; val_offset:231*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 231*FLEN/8, x10, x1, x4) + +inst_102: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a1 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x109 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1d4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78a1; op2val:0xbd09; +op3val:0x79d4; valaddr_reg:x8; val_offset:234*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 234*FLEN/8, x10, x1, x4) + +inst_103: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a1 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x109 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1d4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78a1; op2val:0xbd09; +op3val:0x79d4; valaddr_reg:x8; val_offset:237*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 237*FLEN/8, x10, x1, x4) + +inst_104: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a1 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x109 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1d4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78a1; op2val:0xbd09; +op3val:0x79d4; valaddr_reg:x8; val_offset:240*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 240*FLEN/8, x10, x1, x4) + +inst_105: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x130 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x091 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b0b; op2val:0xb530; +op3val:0x7491; valaddr_reg:x8; val_offset:243*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 243*FLEN/8, x10, x1, x4) + +inst_106: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x130 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x091 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b0b; op2val:0xb530; +op3val:0x7491; valaddr_reg:x8; val_offset:246*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 246*FLEN/8, x10, x1, x4) + +inst_107: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x130 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x091 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b0b; op2val:0xb530; +op3val:0x7491; valaddr_reg:x8; val_offset:249*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 249*FLEN/8, x10, x1, x4) + +inst_108: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x130 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x091 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b0b; op2val:0xb530; +op3val:0x7491; valaddr_reg:x8; val_offset:252*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 252*FLEN/8, x10, x1, x4) + +inst_109: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x130 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x091 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b0b; op2val:0xb530; +op3val:0x7491; valaddr_reg:x8; val_offset:255*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 255*FLEN/8, x10, x1, x4) + +inst_110: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1b4 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ec and fs3 == 0 and fe3 == 0x1e and fm3 == 0x305 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75b4; op2val:0xc0ec; +op3val:0x7b05; valaddr_reg:x8; val_offset:258*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 258*FLEN/8, x10, x1, x4) + +inst_111: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1b4 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ec and fs3 == 0 and fe3 == 0x1e and fm3 == 0x305 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75b4; op2val:0xc0ec; +op3val:0x7b05; valaddr_reg:x8; val_offset:261*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 261*FLEN/8, x10, x1, x4) + +inst_112: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1b4 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ec and fs3 == 0 and fe3 == 0x1e and fm3 == 0x305 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75b4; op2val:0xc0ec; +op3val:0x7b05; valaddr_reg:x8; val_offset:264*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 264*FLEN/8, x10, x1, x4) + +inst_113: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1b4 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ec and fs3 == 0 and fe3 == 0x1e and fm3 == 0x305 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75b4; op2val:0xc0ec; +op3val:0x7b05; valaddr_reg:x8; val_offset:267*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 267*FLEN/8, x10, x1, x4) + +inst_114: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1b4 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ec and fs3 == 0 and fe3 == 0x1e and fm3 == 0x305 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75b4; op2val:0xc0ec; +op3val:0x7b05; valaddr_reg:x8; val_offset:270*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 270*FLEN/8, x10, x1, x4) + +inst_115: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x051 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1a9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x21c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7051; op2val:0xc5a9; +op3val:0x7a1c; valaddr_reg:x8; val_offset:273*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 273*FLEN/8, x10, x1, x4) + +inst_116: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x051 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1a9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x21c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7051; op2val:0xc5a9; +op3val:0x7a1c; valaddr_reg:x8; val_offset:276*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 276*FLEN/8, x10, x1, x4) + +inst_117: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x051 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1a9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x21c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7051; op2val:0xc5a9; +op3val:0x7a1c; valaddr_reg:x8; val_offset:279*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 279*FLEN/8, x10, x1, x4) + +inst_118: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x051 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1a9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x21c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7051; op2val:0xc5a9; +op3val:0x7a1c; valaddr_reg:x8; val_offset:282*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 282*FLEN/8, x10, x1, x4) + +inst_119: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x051 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1a9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x21c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7051; op2val:0xc5a9; +op3val:0x7a1c; valaddr_reg:x8; val_offset:285*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 285*FLEN/8, x10, x1, x4) + +inst_120: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x23e and fs2 == 1 and fe2 == 0x11 and fm2 == 0x311 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x184 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e3e; op2val:0xc711; +op3val:0x7984; valaddr_reg:x8; val_offset:288*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 288*FLEN/8, x10, x1, x4) + +inst_121: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x23e and fs2 == 1 and fe2 == 0x11 and fm2 == 0x311 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x184 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e3e; op2val:0xc711; +op3val:0x7984; valaddr_reg:x8; val_offset:291*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 291*FLEN/8, x10, x1, x4) + +inst_122: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x23e and fs2 == 1 and fe2 == 0x11 and fm2 == 0x311 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x184 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e3e; op2val:0xc711; +op3val:0x7984; valaddr_reg:x8; val_offset:294*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 294*FLEN/8, x10, x1, x4) + +inst_123: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x23e and fs2 == 1 and fe2 == 0x11 and fm2 == 0x311 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x184 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e3e; op2val:0xc711; +op3val:0x7984; valaddr_reg:x8; val_offset:297*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 297*FLEN/8, x10, x1, x4) + +inst_124: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x23e and fs2 == 1 and fe2 == 0x11 and fm2 == 0x311 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x184 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e3e; op2val:0xc711; +op3val:0x7984; valaddr_reg:x8; val_offset:300*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 300*FLEN/8, x10, x1, x4) + +inst_125: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x169 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x398 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x799d; op2val:0xbd69; +op3val:0x7b98; valaddr_reg:x8; val_offset:303*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 303*FLEN/8, x10, x1, x4) + +inst_126: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x169 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x398 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x799d; op2val:0xbd69; +op3val:0x7b98; valaddr_reg:x8; val_offset:306*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 306*FLEN/8, x10, x1, x4) + +inst_127: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x169 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x398 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x799d; op2val:0xbd69; +op3val:0x7b98; valaddr_reg:x8; val_offset:309*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 309*FLEN/8, x10, x1, x4) + +inst_128: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x169 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x398 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x799d; op2val:0xbd69; +op3val:0x7b98; valaddr_reg:x8; val_offset:312*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 312*FLEN/8, x10, x1, x4) + +inst_129: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x169 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x398 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x799d; op2val:0xbd69; +op3val:0x7b98; valaddr_reg:x8; val_offset:315*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 315*FLEN/8, x10, x1, x4) + +inst_130: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2be and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0c6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x006 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7abe; op2val:0xb8c6; +op3val:0x7806; valaddr_reg:x8; val_offset:318*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 318*FLEN/8, x10, x1, x4) + +inst_131: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2be and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0c6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x006 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7abe; op2val:0xb8c6; +op3val:0x7806; valaddr_reg:x8; val_offset:321*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 321*FLEN/8, x10, x1, x4) + +inst_132: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2be and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0c6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x006 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7abe; op2val:0xb8c6; +op3val:0x7806; valaddr_reg:x8; val_offset:324*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 324*FLEN/8, x10, x1, x4) + +inst_133: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2be and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0c6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x006 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7abe; op2val:0xb8c6; +op3val:0x7806; valaddr_reg:x8; val_offset:327*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 327*FLEN/8, x10, x1, x4) + +inst_134: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2be and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0c6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x006 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7abe; op2val:0xb8c6; +op3val:0x7806; valaddr_reg:x8; val_offset:330*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 330*FLEN/8, x10, x1, x4) + +inst_135: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x252 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x213 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0cd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7252; op2val:0xba13; +op3val:0x70cd; valaddr_reg:x8; val_offset:333*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 333*FLEN/8, x10, x1, x4) + +inst_136: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x252 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x213 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0cd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7252; op2val:0xba13; +op3val:0x70cd; valaddr_reg:x8; val_offset:336*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 336*FLEN/8, x10, x1, x4) + +inst_137: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x252 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x213 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0cd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7252; op2val:0xba13; +op3val:0x70cd; valaddr_reg:x8; val_offset:339*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 339*FLEN/8, x10, x1, x4) + +inst_138: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x252 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x213 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0cd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7252; op2val:0xba13; +op3val:0x70cd; valaddr_reg:x8; val_offset:342*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 342*FLEN/8, x10, x1, x4) + +inst_139: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x252 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x213 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0cd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7252; op2val:0xba13; +op3val:0x70cd; valaddr_reg:x8; val_offset:345*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 345*FLEN/8, x10, x1, x4) + +inst_140: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x03a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x013 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x783a; op2val:0xbbb6; +op3val:0x7813; valaddr_reg:x8; val_offset:348*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 348*FLEN/8, x10, x1, x4) + +inst_141: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x03a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x013 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x783a; op2val:0xbbb6; +op3val:0x7813; valaddr_reg:x8; val_offset:351*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 351*FLEN/8, x10, x1, x4) + +inst_142: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x03a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x013 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x783a; op2val:0xbbb6; +op3val:0x7813; valaddr_reg:x8; val_offset:354*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 354*FLEN/8, x10, x1, x4) + +inst_143: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x03a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x013 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x783a; op2val:0xbbb6; +op3val:0x7813; valaddr_reg:x8; val_offset:357*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 357*FLEN/8, x10, x1, x4) + +inst_144: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x03a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x013 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x783a; op2val:0xbbb6; +op3val:0x7813; valaddr_reg:x8; val_offset:360*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 360*FLEN/8, x10, x1, x4) + +inst_145: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x091 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x252 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x338 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c91; op2val:0xca52; +op3val:0x7b38; valaddr_reg:x8; val_offset:363*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 363*FLEN/8, x10, x1, x4) + +inst_146: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x091 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x252 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x338 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c91; op2val:0xca52; +op3val:0x7b38; valaddr_reg:x8; val_offset:366*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 366*FLEN/8, x10, x1, x4) + +inst_147: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x091 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x252 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x338 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c91; op2val:0xca52; +op3val:0x7b38; valaddr_reg:x8; val_offset:369*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 369*FLEN/8, x10, x1, x4) + +inst_148: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x091 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x252 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x338 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c91; op2val:0xca52; +op3val:0x7b38; valaddr_reg:x8; val_offset:372*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 372*FLEN/8, x10, x1, x4) + +inst_149: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x091 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x252 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x338 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c91; op2val:0xca52; +op3val:0x7b38; valaddr_reg:x8; val_offset:375*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 375*FLEN/8, x10, x1, x4) + +inst_150: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x187 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x19b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x780e; op2val:0xbd87; +op3val:0x799b; valaddr_reg:x8; val_offset:378*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 378*FLEN/8, x10, x1, x4) + +inst_151: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x187 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x19b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x780e; op2val:0xbd87; +op3val:0x799b; valaddr_reg:x8; val_offset:381*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 381*FLEN/8, x10, x1, x4) + +inst_152: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x187 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x19b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x780e; op2val:0xbd87; +op3val:0x799b; valaddr_reg:x8; val_offset:384*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 384*FLEN/8, x10, x1, x4) + +inst_153: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x187 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x19b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x780e; op2val:0xbd87; +op3val:0x799b; valaddr_reg:x8; val_offset:387*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 387*FLEN/8, x10, x1, x4) + +inst_154: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x187 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x19b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x780e; op2val:0xbd87; +op3val:0x799b; valaddr_reg:x8; val_offset:390*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 390*FLEN/8, x10, x1, x4) + +inst_155: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x309 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x06f and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3cd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7309; op2val:0xbc6f; +op3val:0x73cd; valaddr_reg:x8; val_offset:393*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 393*FLEN/8, x10, x1, x4) + +inst_156: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x309 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x06f and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3cd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7309; op2val:0xbc6f; +op3val:0x73cd; valaddr_reg:x8; val_offset:396*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 396*FLEN/8, x10, x1, x4) + +inst_157: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x309 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x06f and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3cd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7309; op2val:0xbc6f; +op3val:0x73cd; valaddr_reg:x8; val_offset:399*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 399*FLEN/8, x10, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_3) + +inst_158: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x309 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x06f and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3cd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7309; op2val:0xbc6f; +op3val:0x73cd; valaddr_reg:x8; val_offset:402*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 402*FLEN/8, x10, x1, x4) + +inst_159: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x309 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x06f and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3cd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7309; op2val:0xbc6f; +op3val:0x73cd; valaddr_reg:x8; val_offset:405*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 405*FLEN/8, x10, x1, x4) + +inst_160: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x21b and fs2 == 1 and fe2 == 0x13 and fm2 == 0x331 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x17d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x621b; op2val:0xcf31; +op3val:0x757d; valaddr_reg:x8; val_offset:408*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 408*FLEN/8, x10, x1, x4) + +inst_161: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x21b and fs2 == 1 and fe2 == 0x13 and fm2 == 0x331 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x17d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x621b; op2val:0xcf31; +op3val:0x757d; valaddr_reg:x8; val_offset:411*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 411*FLEN/8, x10, x1, x4) + +inst_162: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x21b and fs2 == 1 and fe2 == 0x13 and fm2 == 0x331 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x17d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x621b; op2val:0xcf31; +op3val:0x757d; valaddr_reg:x8; val_offset:414*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 414*FLEN/8, x10, x1, x4) + +inst_163: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x21b and fs2 == 1 and fe2 == 0x13 and fm2 == 0x331 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x17d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x621b; op2val:0xcf31; +op3val:0x757d; valaddr_reg:x8; val_offset:417*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 417*FLEN/8, x10, x1, x4) + +inst_164: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x21b and fs2 == 1 and fe2 == 0x13 and fm2 == 0x331 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x17d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x621b; op2val:0xcf31; +op3val:0x757d; valaddr_reg:x8; val_offset:420*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 420*FLEN/8, x10, x1, x4) + +inst_165: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x044 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x258 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2c5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7444; op2val:0xbe58; +op3val:0x76c5; valaddr_reg:x8; val_offset:423*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 423*FLEN/8, x10, x1, x4) + +inst_166: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x044 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x258 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2c5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7444; op2val:0xbe58; +op3val:0x76c5; valaddr_reg:x8; val_offset:426*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 426*FLEN/8, x10, x1, x4) + +inst_167: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x044 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x258 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2c5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7444; op2val:0xbe58; +op3val:0x76c5; valaddr_reg:x8; val_offset:429*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 429*FLEN/8, x10, x1, x4) + +inst_168: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x044 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x258 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2c5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7444; op2val:0xbe58; +op3val:0x76c5; valaddr_reg:x8; val_offset:432*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 432*FLEN/8, x10, x1, x4) + +inst_169: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x044 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x258 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2c5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7444; op2val:0xbe58; +op3val:0x76c5; valaddr_reg:x8; val_offset:435*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 435*FLEN/8, x10, x1, x4) + +inst_170: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x207 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x06d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ab and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7607; op2val:0xc06d; +op3val:0x7aab; valaddr_reg:x8; val_offset:438*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 438*FLEN/8, x10, x1, x4) + +inst_171: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x207 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x06d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ab and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7607; op2val:0xc06d; +op3val:0x7aab; valaddr_reg:x8; val_offset:441*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 441*FLEN/8, x10, x1, x4) + +inst_172: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x207 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x06d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ab and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7607; op2val:0xc06d; +op3val:0x7aab; valaddr_reg:x8; val_offset:444*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 444*FLEN/8, x10, x1, x4) + +inst_173: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x207 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x06d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ab and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7607; op2val:0xc06d; +op3val:0x7aab; valaddr_reg:x8; val_offset:447*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 447*FLEN/8, x10, x1, x4) + +inst_174: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x207 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x06d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ab and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7607; op2val:0xc06d; +op3val:0x7aab; valaddr_reg:x8; val_offset:450*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 450*FLEN/8, x10, x1, x4) + +inst_175: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x320 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x24a and fs3 == 0 and fe3 == 0x1c and fm3 == 0x19b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b20; op2val:0xb24a; +op3val:0x719b; valaddr_reg:x8; val_offset:453*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 453*FLEN/8, x10, x1, x4) + +inst_176: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x320 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x24a and fs3 == 0 and fe3 == 0x1c and fm3 == 0x19b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b20; op2val:0xb24a; +op3val:0x719b; valaddr_reg:x8; val_offset:456*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 456*FLEN/8, x10, x1, x4) + +inst_177: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x320 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x24a and fs3 == 0 and fe3 == 0x1c and fm3 == 0x19b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b20; op2val:0xb24a; +op3val:0x719b; valaddr_reg:x8; val_offset:459*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 459*FLEN/8, x10, x1, x4) + +inst_178: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x320 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x24a and fs3 == 0 and fe3 == 0x1c and fm3 == 0x19b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b20; op2val:0xb24a; +op3val:0x719b; valaddr_reg:x8; val_offset:462*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 462*FLEN/8, x10, x1, x4) + +inst_179: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x320 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x24a and fs3 == 0 and fe3 == 0x1c and fm3 == 0x19b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b20; op2val:0xb24a; +op3val:0x719b; valaddr_reg:x8; val_offset:465*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 465*FLEN/8, x10, x1, x4) + +inst_180: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x256 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2b5 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x150 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7656; op2val:0xb6b5; +op3val:0x7150; valaddr_reg:x8; val_offset:468*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 468*FLEN/8, x10, x1, x4) + +inst_181: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x256 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2b5 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x150 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7656; op2val:0xb6b5; +op3val:0x7150; valaddr_reg:x8; val_offset:471*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 471*FLEN/8, x10, x1, x4) + +inst_182: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x256 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2b5 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x150 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7656; op2val:0xb6b5; +op3val:0x7150; valaddr_reg:x8; val_offset:474*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 474*FLEN/8, x10, x1, x4) + +inst_183: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x256 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2b5 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x150 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7656; op2val:0xb6b5; +op3val:0x7150; valaddr_reg:x8; val_offset:477*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 477*FLEN/8, x10, x1, x4) + +inst_184: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x256 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2b5 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x150 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7656; op2val:0xb6b5; +op3val:0x7150; valaddr_reg:x8; val_offset:480*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 480*FLEN/8, x10, x1, x4) + +inst_185: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x14d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3cb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x794d; op2val:0xbde1; +op3val:0x7bcb; valaddr_reg:x8; val_offset:483*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 483*FLEN/8, x10, x1, x4) + +inst_186: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x14d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3cb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x794d; op2val:0xbde1; +op3val:0x7bcb; valaddr_reg:x8; val_offset:486*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 486*FLEN/8, x10, x1, x4) + +inst_187: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x14d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3cb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x794d; op2val:0xbde1; +op3val:0x7bcb; valaddr_reg:x8; val_offset:489*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 489*FLEN/8, x10, x1, x4) + +inst_188: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x14d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3cb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x794d; op2val:0xbde1; +op3val:0x7bcb; valaddr_reg:x8; val_offset:492*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 492*FLEN/8, x10, x1, x4) + +inst_189: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x14d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3cb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x794d; op2val:0xbde1; +op3val:0x7bcb; valaddr_reg:x8; val_offset:495*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 495*FLEN/8, x10, x1, x4) + +inst_190: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x274 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x398 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x220 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7274; op2val:0xc398; +op3val:0x7a20; valaddr_reg:x8; val_offset:498*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 498*FLEN/8, x10, x1, x4) + +inst_191: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x274 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x398 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x220 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7274; op2val:0xc398; +op3val:0x7a20; valaddr_reg:x8; val_offset:501*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 501*FLEN/8, x10, x1, x4) + +inst_192: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x274 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x398 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x220 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7274; op2val:0xc398; +op3val:0x7a20; valaddr_reg:x8; val_offset:504*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 504*FLEN/8, x10, x1, x4) + +inst_193: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x274 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x398 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x220 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7274; op2val:0xc398; +op3val:0x7a20; valaddr_reg:x8; val_offset:507*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 507*FLEN/8, x10, x1, x4) + +inst_194: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x274 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x398 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x220 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7274; op2val:0xc398; +op3val:0x7a20; valaddr_reg:x8; val_offset:510*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 510*FLEN/8, x10, x1, x4) + +inst_195: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0cc and fs2 == 1 and fe2 == 0x0a and fm2 == 0x1a5 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x2c5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74cc; op2val:0xa9a5; +op3val:0x62c5; valaddr_reg:x8; val_offset:513*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 513*FLEN/8, x10, x1, x4) + +inst_196: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0cc and fs2 == 1 and fe2 == 0x0a and fm2 == 0x1a5 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x2c5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74cc; op2val:0xa9a5; +op3val:0x62c5; valaddr_reg:x8; val_offset:516*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 516*FLEN/8, x10, x1, x4) + +inst_197: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0cc and fs2 == 1 and fe2 == 0x0a and fm2 == 0x1a5 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x2c5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74cc; op2val:0xa9a5; +op3val:0x62c5; valaddr_reg:x8; val_offset:519*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 519*FLEN/8, x10, x1, x4) + +inst_198: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0cc and fs2 == 1 and fe2 == 0x0a and fm2 == 0x1a5 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x2c5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74cc; op2val:0xa9a5; +op3val:0x62c5; valaddr_reg:x8; val_offset:522*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 522*FLEN/8, x10, x1, x4) + +inst_199: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0cc and fs2 == 1 and fe2 == 0x0a and fm2 == 0x1a5 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x2c5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74cc; op2val:0xa9a5; +op3val:0x62c5; valaddr_reg:x8; val_offset:525*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 525*FLEN/8, x10, x1, x4) + +inst_200: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x21c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x327 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x177 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a1c; op2val:0xb727; +op3val:0x7577; valaddr_reg:x8; val_offset:528*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 528*FLEN/8, x10, x1, x4) + +inst_201: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x21c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x327 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x177 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a1c; op2val:0xb727; +op3val:0x7577; valaddr_reg:x8; val_offset:531*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 531*FLEN/8, x10, x1, x4) + +inst_202: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x21c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x327 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x177 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a1c; op2val:0xb727; +op3val:0x7577; valaddr_reg:x8; val_offset:534*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 534*FLEN/8, x10, x1, x4) + +inst_203: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x21c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x327 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x177 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a1c; op2val:0xb727; +op3val:0x7577; valaddr_reg:x8; val_offset:537*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 537*FLEN/8, x10, x1, x4) + +inst_204: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x21c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x327 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x177 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a1c; op2val:0xb727; +op3val:0x7577; valaddr_reg:x8; val_offset:540*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 540*FLEN/8, x10, x1, x4) + +inst_205: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x171 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x11e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2f7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7171; op2val:0xc11e; +op3val:0x76f7; valaddr_reg:x8; val_offset:543*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 543*FLEN/8, x10, x1, x4) + +inst_206: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x171 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x11e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2f7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7171; op2val:0xc11e; +op3val:0x76f7; valaddr_reg:x8; val_offset:546*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 546*FLEN/8, x10, x1, x4) + +inst_207: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x171 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x11e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2f7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7171; op2val:0xc11e; +op3val:0x76f7; valaddr_reg:x8; val_offset:549*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 549*FLEN/8, x10, x1, x4) + +inst_208: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x171 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x11e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2f7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7171; op2val:0xc11e; +op3val:0x76f7; valaddr_reg:x8; val_offset:552*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 552*FLEN/8, x10, x1, x4) + +inst_209: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x171 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x11e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2f7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7171; op2val:0xc11e; +op3val:0x76f7; valaddr_reg:x8; val_offset:555*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 555*FLEN/8, x10, x1, x4) + +inst_210: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x369 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x314 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x28e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7369; op2val:0xbf14; +op3val:0x768e; valaddr_reg:x8; val_offset:558*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 558*FLEN/8, x10, x1, x4) + +inst_211: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x369 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x314 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x28e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7369; op2val:0xbf14; +op3val:0x768e; valaddr_reg:x8; val_offset:561*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 561*FLEN/8, x10, x1, x4) + +inst_212: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x369 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x314 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x28e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7369; op2val:0xbf14; +op3val:0x768e; valaddr_reg:x8; val_offset:564*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 564*FLEN/8, x10, x1, x4) + +inst_213: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x369 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x314 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x28e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7369; op2val:0xbf14; +op3val:0x768e; valaddr_reg:x8; val_offset:567*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 567*FLEN/8, x10, x1, x4) + +inst_214: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x369 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x314 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x28e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7369; op2val:0xbf14; +op3val:0x768e; valaddr_reg:x8; val_offset:570*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 570*FLEN/8, x10, x1, x4) + +inst_215: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x322 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x37f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2af and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7722; op2val:0xbb7f; +op3val:0x76af; valaddr_reg:x8; val_offset:573*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 573*FLEN/8, x10, x1, x4) + +inst_216: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x322 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x37f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2af and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7722; op2val:0xbb7f; +op3val:0x76af; valaddr_reg:x8; val_offset:576*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 576*FLEN/8, x10, x1, x4) + +inst_217: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x322 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x37f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2af and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7722; op2val:0xbb7f; +op3val:0x76af; valaddr_reg:x8; val_offset:579*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 579*FLEN/8, x10, x1, x4) + +inst_218: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x322 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x37f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2af and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7722; op2val:0xbb7f; +op3val:0x76af; valaddr_reg:x8; val_offset:582*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 582*FLEN/8, x10, x1, x4) + +inst_219: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x322 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x37f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2af and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7722; op2val:0xbb7f; +op3val:0x76af; valaddr_reg:x8; val_offset:585*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 585*FLEN/8, x10, x1, x4) + +inst_220: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b4 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3d9 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x09e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78b4; op2val:0xb7d9; +op3val:0x749e; valaddr_reg:x8; val_offset:588*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 588*FLEN/8, x10, x1, x4) + +inst_221: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b4 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3d9 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x09e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78b4; op2val:0xb7d9; +op3val:0x749e; valaddr_reg:x8; val_offset:591*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 591*FLEN/8, x10, x1, x4) + +inst_222: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b4 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3d9 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x09e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78b4; op2val:0xb7d9; +op3val:0x749e; valaddr_reg:x8; val_offset:594*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 594*FLEN/8, x10, x1, x4) + +inst_223: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b4 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3d9 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x09e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78b4; op2val:0xb7d9; +op3val:0x749e; valaddr_reg:x8; val_offset:597*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 597*FLEN/8, x10, x1, x4) + +inst_224: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b4 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3d9 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x09e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78b4; op2val:0xb7d9; +op3val:0x749e; valaddr_reg:x8; val_offset:600*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 600*FLEN/8, x10, x1, x4) + +inst_225: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x215 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x32b and fs3 == 0 and fe3 == 0x1b and fm3 == 0x174 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e15; op2val:0xbb2b; +op3val:0x6d74; valaddr_reg:x8; val_offset:603*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 603*FLEN/8, x10, x1, x4) + +inst_226: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x215 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x32b and fs3 == 0 and fe3 == 0x1b and fm3 == 0x174 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e15; op2val:0xbb2b; +op3val:0x6d74; valaddr_reg:x8; val_offset:606*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 606*FLEN/8, x10, x1, x4) + +inst_227: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x215 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x32b and fs3 == 0 and fe3 == 0x1b and fm3 == 0x174 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e15; op2val:0xbb2b; +op3val:0x6d74; valaddr_reg:x8; val_offset:609*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 609*FLEN/8, x10, x1, x4) + +inst_228: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x215 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x32b and fs3 == 0 and fe3 == 0x1b and fm3 == 0x174 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e15; op2val:0xbb2b; +op3val:0x6d74; valaddr_reg:x8; val_offset:612*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 612*FLEN/8, x10, x1, x4) + +inst_229: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x215 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x32b and fs3 == 0 and fe3 == 0x1b and fm3 == 0x174 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e15; op2val:0xbb2b; +op3val:0x6d74; valaddr_reg:x8; val_offset:615*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 615*FLEN/8, x10, x1, x4) + +inst_230: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2d0 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0e3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x02a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ed0; op2val:0xc4e3; +op3val:0x782a; valaddr_reg:x8; val_offset:618*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 618*FLEN/8, x10, x1, x4) + +inst_231: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2d0 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0e3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x02a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ed0; op2val:0xc4e3; +op3val:0x782a; valaddr_reg:x8; val_offset:621*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 621*FLEN/8, x10, x1, x4) + +inst_232: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2d0 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0e3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x02a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ed0; op2val:0xc4e3; +op3val:0x782a; valaddr_reg:x8; val_offset:624*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 624*FLEN/8, x10, x1, x4) + +inst_233: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2d0 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0e3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x02a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ed0; op2val:0xc4e3; +op3val:0x782a; valaddr_reg:x8; val_offset:627*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 627*FLEN/8, x10, x1, x4) + +inst_234: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2d0 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0e3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x02a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ed0; op2val:0xc4e3; +op3val:0x782a; valaddr_reg:x8; val_offset:630*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 630*FLEN/8, x10, x1, x4) + +inst_235: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c2 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x07c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x275 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c2; op2val:0xc07c; +op3val:0x7a75; valaddr_reg:x8; val_offset:633*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 633*FLEN/8, x10, x1, x4) + +inst_236: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c2 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x07c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x275 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c2; op2val:0xc07c; +op3val:0x7a75; valaddr_reg:x8; val_offset:636*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 636*FLEN/8, x10, x1, x4) + +inst_237: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c2 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x07c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x275 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c2; op2val:0xc07c; +op3val:0x7a75; valaddr_reg:x8; val_offset:639*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 639*FLEN/8, x10, x1, x4) + +inst_238: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c2 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x07c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x275 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c2; op2val:0xc07c; +op3val:0x7a75; valaddr_reg:x8; val_offset:642*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 642*FLEN/8, x10, x1, x4) + +inst_239: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c2 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x07c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x275 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c2; op2val:0xc07c; +op3val:0x7a75; valaddr_reg:x8; val_offset:645*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 645*FLEN/8, x10, x1, x4) + +inst_240: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x009 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x19c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7809; op2val:0xbd9c; +op3val:0x79a9; valaddr_reg:x8; val_offset:648*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 648*FLEN/8, x10, x1, x4) + +inst_241: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x009 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x19c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7809; op2val:0xbd9c; +op3val:0x79a9; valaddr_reg:x8; val_offset:651*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 651*FLEN/8, x10, x1, x4) + +inst_242: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x009 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x19c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7809; op2val:0xbd9c; +op3val:0x79a9; valaddr_reg:x8; val_offset:654*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 654*FLEN/8, x10, x1, x4) + +inst_243: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x009 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x19c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7809; op2val:0xbd9c; +op3val:0x79a9; valaddr_reg:x8; val_offset:657*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 657*FLEN/8, x10, x1, x4) + +inst_244: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x009 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x19c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7809; op2val:0xbd9c; +op3val:0x79a9; valaddr_reg:x8; val_offset:660*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 660*FLEN/8, x10, x1, x4) + +inst_245: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d6 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x01c and fs3 == 0 and fe3 == 0x1b and fm3 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd6; op2val:0xac1c; +op3val:0x6c07; valaddr_reg:x8; val_offset:663*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 663*FLEN/8, x10, x1, x4) + +inst_246: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d6 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x01c and fs3 == 0 and fe3 == 0x1b and fm3 == 0x007 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd6; op2val:0xac1c; +op3val:0x6c07; valaddr_reg:x8; val_offset:666*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 666*FLEN/8, x10, x1, x4) + +inst_247: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d6 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x01c and fs3 == 0 and fe3 == 0x1b and fm3 == 0x007 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd6; op2val:0xac1c; +op3val:0x6c07; valaddr_reg:x8; val_offset:669*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 669*FLEN/8, x10, x1, x4) + +inst_248: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d6 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x01c and fs3 == 0 and fe3 == 0x1b and fm3 == 0x007 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd6; op2val:0xac1c; +op3val:0x6c07; valaddr_reg:x8; val_offset:672*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 672*FLEN/8, x10, x1, x4) + +inst_249: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d6 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x01c and fs3 == 0 and fe3 == 0x1b and fm3 == 0x007 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd6; op2val:0xac1c; +op3val:0x6c07; valaddr_reg:x8; val_offset:675*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 675*FLEN/8, x10, x1, x4) + +inst_250: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x056 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x023 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x07d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6456; op2val:0xc823; +op3val:0x707d; valaddr_reg:x8; val_offset:678*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 678*FLEN/8, x10, x1, x4) + +inst_251: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x056 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x023 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x07d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6456; op2val:0xc823; +op3val:0x707d; valaddr_reg:x8; val_offset:681*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 681*FLEN/8, x10, x1, x4) + +inst_252: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x056 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x023 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x07d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6456; op2val:0xc823; +op3val:0x707d; valaddr_reg:x8; val_offset:684*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 684*FLEN/8, x10, x1, x4) + +inst_253: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x056 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x023 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x07d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6456; op2val:0xc823; +op3val:0x707d; valaddr_reg:x8; val_offset:687*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 687*FLEN/8, x10, x1, x4) + +inst_254: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x056 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x023 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x07d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6456; op2val:0xc823; +op3val:0x707d; valaddr_reg:x8; val_offset:690*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 690*FLEN/8, x10, x1, x4) + +inst_255: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x22d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1f0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x096 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x762d; op2val:0xbdf0; +op3val:0x7896; valaddr_reg:x8; val_offset:693*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 693*FLEN/8, x10, x1, x4) + +inst_256: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x22d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1f0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x096 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x762d; op2val:0xbdf0; +op3val:0x7896; valaddr_reg:x8; val_offset:696*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 696*FLEN/8, x10, x1, x4) + +inst_257: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x22d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1f0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x096 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x762d; op2val:0xbdf0; +op3val:0x7896; valaddr_reg:x8; val_offset:699*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 699*FLEN/8, x10, x1, x4) + +inst_258: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x22d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1f0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x096 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x762d; op2val:0xbdf0; +op3val:0x7896; valaddr_reg:x8; val_offset:702*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 702*FLEN/8, x10, x1, x4) + +inst_259: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x22d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1f0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x096 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x762d; op2val:0xbdf0; +op3val:0x7896; valaddr_reg:x8; val_offset:705*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 705*FLEN/8, x10, x1, x4) + +inst_260: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f2 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x38f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x19e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f2; op2val:0xb78f; +op3val:0x759e; valaddr_reg:x8; val_offset:708*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 708*FLEN/8, x10, x1, x4) + +inst_261: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f2 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x38f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x19e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f2; op2val:0xb78f; +op3val:0x759e; valaddr_reg:x8; val_offset:711*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 711*FLEN/8, x10, x1, x4) + +inst_262: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f2 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x38f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x19e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f2; op2val:0xb78f; +op3val:0x759e; valaddr_reg:x8; val_offset:714*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 714*FLEN/8, x10, x1, x4) + +inst_263: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f2 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x38f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x19e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f2; op2val:0xb78f; +op3val:0x759e; valaddr_reg:x8; val_offset:717*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 717*FLEN/8, x10, x1, x4) + +inst_264: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f2 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x38f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x19e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f2; op2val:0xb78f; +op3val:0x759e; valaddr_reg:x8; val_offset:720*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 720*FLEN/8, x10, x1, x4) + +inst_265: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b7 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x245 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x20c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bb7; op2val:0x9a45; +op3val:0x5a0c; valaddr_reg:x8; val_offset:723*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 723*FLEN/8, x10, x1, x4) + +inst_266: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b7 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x245 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x20c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bb7; op2val:0x9a45; +op3val:0x5a0c; valaddr_reg:x8; val_offset:726*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 726*FLEN/8, x10, x1, x4) + +inst_267: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b7 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x245 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x20c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bb7; op2val:0x9a45; +op3val:0x5a0c; valaddr_reg:x8; val_offset:729*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 729*FLEN/8, x10, x1, x4) + +inst_268: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b7 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x245 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x20c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bb7; op2val:0x9a45; +op3val:0x5a0c; valaddr_reg:x8; val_offset:732*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 732*FLEN/8, x10, x1, x4) + +inst_269: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b7 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x245 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x20c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bb7; op2val:0x9a45; +op3val:0x5a0c; valaddr_reg:x8; val_offset:735*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 735*FLEN/8, x10, x1, x4) + +inst_270: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 1 and fe2 == 0x0d and fm2 == 0x005 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2b8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aae; op2val:0xb405; +op3val:0x72b8; valaddr_reg:x8; val_offset:738*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 738*FLEN/8, x10, x1, x4) + +inst_271: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 1 and fe2 == 0x0d and fm2 == 0x005 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2b8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aae; op2val:0xb405; +op3val:0x72b8; valaddr_reg:x8; val_offset:741*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 741*FLEN/8, x10, x1, x4) + +inst_272: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 1 and fe2 == 0x0d and fm2 == 0x005 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2b8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aae; op2val:0xb405; +op3val:0x72b8; valaddr_reg:x8; val_offset:744*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 744*FLEN/8, x10, x1, x4) + +inst_273: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 1 and fe2 == 0x0d and fm2 == 0x005 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2b8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aae; op2val:0xb405; +op3val:0x72b8; valaddr_reg:x8; val_offset:747*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 747*FLEN/8, x10, x1, x4) + +inst_274: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 1 and fe2 == 0x0d and fm2 == 0x005 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2b8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aae; op2val:0xb405; +op3val:0x72b8; valaddr_reg:x8; val_offset:750*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 750*FLEN/8, x10, x1, x4) + +inst_275: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ff and fs2 == 1 and fe2 == 0x0a and fm2 == 0x0d8 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x03d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aff; op2val:0xa8d8; +op3val:0x683d; valaddr_reg:x8; val_offset:753*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 753*FLEN/8, x10, x1, x4) + +inst_276: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ff and fs2 == 1 and fe2 == 0x0a and fm2 == 0x0d8 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x03d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aff; op2val:0xa8d8; +op3val:0x683d; valaddr_reg:x8; val_offset:756*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 756*FLEN/8, x10, x1, x4) + +inst_277: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ff and fs2 == 1 and fe2 == 0x0a and fm2 == 0x0d8 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x03d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aff; op2val:0xa8d8; +op3val:0x683d; valaddr_reg:x8; val_offset:759*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 759*FLEN/8, x10, x1, x4) + +inst_278: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ff and fs2 == 1 and fe2 == 0x0a and fm2 == 0x0d8 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x03d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aff; op2val:0xa8d8; +op3val:0x683d; valaddr_reg:x8; val_offset:762*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 762*FLEN/8, x10, x1, x4) + +inst_279: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ff and fs2 == 1 and fe2 == 0x0a and fm2 == 0x0d8 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x03d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aff; op2val:0xa8d8; +op3val:0x683d; valaddr_reg:x8; val_offset:765*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 765*FLEN/8, x10, x1, x4) + +inst_280: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x24b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x212 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bb7; op2val:0xba4b; +op3val:0x7a12; valaddr_reg:x8; val_offset:768*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 768*FLEN/8, x10, x1, x4) + +inst_281: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x24b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x212 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bb7; op2val:0xba4b; +op3val:0x7a12; valaddr_reg:x8; val_offset:771*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 771*FLEN/8, x10, x1, x4) + +inst_282: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x24b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x212 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bb7; op2val:0xba4b; +op3val:0x7a12; valaddr_reg:x8; val_offset:774*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 774*FLEN/8, x10, x1, x4) + +inst_283: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x24b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x212 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bb7; op2val:0xba4b; +op3val:0x7a12; valaddr_reg:x8; val_offset:777*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 777*FLEN/8, x10, x1, x4) + +inst_284: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x24b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x212 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bb7; op2val:0xba4b; +op3val:0x7a12; valaddr_reg:x8; val_offset:780*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 780*FLEN/8, x10, x1, x4) + +inst_285: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3eb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0af and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7beb; op2val:0xb8af; +op3val:0x78a3; valaddr_reg:x8; val_offset:783*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 783*FLEN/8, x10, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_4) + +inst_286: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3eb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0af and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7beb; op2val:0xb8af; +op3val:0x78a3; valaddr_reg:x8; val_offset:786*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 786*FLEN/8, x10, x1, x4) + +inst_287: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3eb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0af and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7beb; op2val:0xb8af; +op3val:0x78a3; valaddr_reg:x8; val_offset:789*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 789*FLEN/8, x10, x1, x4) + +inst_288: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3eb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0af and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7beb; op2val:0xb8af; +op3val:0x78a3; valaddr_reg:x8; val_offset:792*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 792*FLEN/8, x10, x1, x4) + +inst_289: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3eb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0af and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7beb; op2val:0xb8af; +op3val:0x78a3; valaddr_reg:x8; val_offset:795*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 795*FLEN/8, x10, x1, x4) + +inst_290: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1af and fs2 == 1 and fe2 == 0x11 and fm2 == 0x174 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3c1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71af; op2val:0xc574; +op3val:0x7bc1; valaddr_reg:x8; val_offset:798*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 798*FLEN/8, x10, x1, x4) + +inst_291: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1af and fs2 == 1 and fe2 == 0x11 and fm2 == 0x174 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3c1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71af; op2val:0xc574; +op3val:0x7bc1; valaddr_reg:x8; val_offset:801*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 801*FLEN/8, x10, x1, x4) + +inst_292: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1af and fs2 == 1 and fe2 == 0x11 and fm2 == 0x174 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3c1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71af; op2val:0xc574; +op3val:0x7bc1; valaddr_reg:x8; val_offset:804*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 804*FLEN/8, x10, x1, x4) + +inst_293: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1af and fs2 == 1 and fe2 == 0x11 and fm2 == 0x174 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3c1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71af; op2val:0xc574; +op3val:0x7bc1; valaddr_reg:x8; val_offset:807*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 807*FLEN/8, x10, x1, x4) + +inst_294: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1af and fs2 == 1 and fe2 == 0x11 and fm2 == 0x174 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3c1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71af; op2val:0xc574; +op3val:0x7bc1; valaddr_reg:x8; val_offset:810*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 810*FLEN/8, x10, x1, x4) + +inst_295: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x30f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x20a and fs3 == 0 and fe3 == 0x1b and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x770f; op2val:0xb20a; +op3val:0x6d55; valaddr_reg:x8; val_offset:813*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 813*FLEN/8, x10, x1, x4) + +inst_296: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x30f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x20a and fs3 == 0 and fe3 == 0x1b and fm3 == 0x155 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x770f; op2val:0xb20a; +op3val:0x6d55; valaddr_reg:x8; val_offset:816*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 816*FLEN/8, x10, x1, x4) + +inst_297: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x30f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x20a and fs3 == 0 and fe3 == 0x1b and fm3 == 0x155 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x770f; op2val:0xb20a; +op3val:0x6d55; valaddr_reg:x8; val_offset:819*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 819*FLEN/8, x10, x1, x4) + +inst_298: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x30f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x20a and fs3 == 0 and fe3 == 0x1b and fm3 == 0x155 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x770f; op2val:0xb20a; +op3val:0x6d55; valaddr_reg:x8; val_offset:822*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 822*FLEN/8, x10, x1, x4) + +inst_299: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x30f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x20a and fs3 == 0 and fe3 == 0x1b and fm3 == 0x155 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x770f; op2val:0xb20a; +op3val:0x6d55; valaddr_reg:x8; val_offset:825*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 825*FLEN/8, x10, x1, x4) + +inst_300: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x292 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3f3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78d7; op2val:0xba92; +op3val:0x77f3; valaddr_reg:x8; val_offset:828*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 828*FLEN/8, x10, x1, x4) + +inst_301: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x292 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3f3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78d7; op2val:0xba92; +op3val:0x77f3; valaddr_reg:x8; val_offset:831*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 831*FLEN/8, x10, x1, x4) + +inst_302: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x292 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3f3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78d7; op2val:0xba92; +op3val:0x77f3; valaddr_reg:x8; val_offset:834*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 834*FLEN/8, x10, x1, x4) + +inst_303: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x292 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3f3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78d7; op2val:0xba92; +op3val:0x77f3; valaddr_reg:x8; val_offset:837*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 837*FLEN/8, x10, x1, x4) + +inst_304: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x292 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3f3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78d7; op2val:0xba92; +op3val:0x77f3; valaddr_reg:x8; val_offset:840*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 840*FLEN/8, x10, x1, x4) + +inst_305: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x391 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x139 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0f1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7791; op2val:0xb539; +op3val:0x70f1; valaddr_reg:x8; val_offset:843*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 843*FLEN/8, x10, x1, x4) + +inst_306: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x391 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x139 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0f1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7791; op2val:0xb539; +op3val:0x70f1; valaddr_reg:x8; val_offset:846*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 846*FLEN/8, x10, x1, x4) + +inst_307: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x391 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x139 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0f1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7791; op2val:0xb539; +op3val:0x70f1; valaddr_reg:x8; val_offset:849*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 849*FLEN/8, x10, x1, x4) + +inst_308: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x391 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x139 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0f1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7791; op2val:0xb539; +op3val:0x70f1; valaddr_reg:x8; val_offset:852*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 852*FLEN/8, x10, x1, x4) + +inst_309: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x391 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x139 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0f1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7791; op2val:0xb539; +op3val:0x70f1; valaddr_reg:x8; val_offset:855*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 855*FLEN/8, x10, x1, x4) + +inst_310: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3ce and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0c2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6fce; op2val:0xc4c2; +op3val:0x78a4; valaddr_reg:x8; val_offset:858*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 858*FLEN/8, x10, x1, x4) + +inst_311: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3ce and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0c2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6fce; op2val:0xc4c2; +op3val:0x78a4; valaddr_reg:x8; val_offset:861*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 861*FLEN/8, x10, x1, x4) + +inst_312: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3ce and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0c2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6fce; op2val:0xc4c2; +op3val:0x78a4; valaddr_reg:x8; val_offset:864*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 864*FLEN/8, x10, x1, x4) + +inst_313: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3ce and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0c2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6fce; op2val:0xc4c2; +op3val:0x78a4; valaddr_reg:x8; val_offset:867*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 867*FLEN/8, x10, x1, x4) + +inst_314: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3ce and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0c2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6fce; op2val:0xc4c2; +op3val:0x78a4; valaddr_reg:x8; val_offset:870*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 870*FLEN/8, x10, x1, x4) + +inst_315: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x33d and fs2 == 1 and fe2 == 0x0d and fm2 == 0x078 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x00b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x773d; op2val:0xb478; +op3val:0x700b; valaddr_reg:x8; val_offset:873*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 873*FLEN/8, x10, x1, x4) + +inst_316: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x33d and fs2 == 1 and fe2 == 0x0d and fm2 == 0x078 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x00b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x773d; op2val:0xb478; +op3val:0x700b; valaddr_reg:x8; val_offset:876*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 876*FLEN/8, x10, x1, x4) + +inst_317: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x33d and fs2 == 1 and fe2 == 0x0d and fm2 == 0x078 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x00b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x773d; op2val:0xb478; +op3val:0x700b; valaddr_reg:x8; val_offset:879*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 879*FLEN/8, x10, x1, x4) + +inst_318: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x33d and fs2 == 1 and fe2 == 0x0d and fm2 == 0x078 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x00b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x773d; op2val:0xb478; +op3val:0x700b; valaddr_reg:x8; val_offset:882*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 882*FLEN/8, x10, x1, x4) + +inst_319: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x33d and fs2 == 1 and fe2 == 0x0d and fm2 == 0x078 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x00b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x773d; op2val:0xb478; +op3val:0x700b; valaddr_reg:x8; val_offset:885*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 885*FLEN/8, x10, x1, x4) + +inst_320: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x307 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x29a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1cd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7707; op2val:0xbe9a; +op3val:0x79cd; valaddr_reg:x8; val_offset:888*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 888*FLEN/8, x10, x1, x4) + +inst_321: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x307 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x29a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1cd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7707; op2val:0xbe9a; +op3val:0x79cd; valaddr_reg:x8; val_offset:891*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 891*FLEN/8, x10, x1, x4) + +inst_322: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x307 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x29a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1cd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7707; op2val:0xbe9a; +op3val:0x79cd; valaddr_reg:x8; val_offset:894*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 894*FLEN/8, x10, x1, x4) + +inst_323: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x307 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x29a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1cd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7707; op2val:0xbe9a; +op3val:0x79cd; valaddr_reg:x8; val_offset:897*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 897*FLEN/8, x10, x1, x4) + +inst_324: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x307 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x29a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1cd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7707; op2val:0xbe9a; +op3val:0x79cd; valaddr_reg:x8; val_offset:900*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 900*FLEN/8, x10, x1, x4) + +inst_325: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x145 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x389 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79b8; op2val:0xb945; +op3val:0x7789; valaddr_reg:x8; val_offset:903*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 903*FLEN/8, x10, x1, x4) + +inst_326: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x145 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x389 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79b8; op2val:0xb945; +op3val:0x7789; valaddr_reg:x8; val_offset:906*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 906*FLEN/8, x10, x1, x4) + +inst_327: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x145 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x389 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79b8; op2val:0xb945; +op3val:0x7789; valaddr_reg:x8; val_offset:909*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 909*FLEN/8, x10, x1, x4) + +inst_328: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x145 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x389 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79b8; op2val:0xb945; +op3val:0x7789; valaddr_reg:x8; val_offset:912*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 912*FLEN/8, x10, x1, x4) + +inst_329: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x145 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x389 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79b8; op2val:0xb945; +op3val:0x7789; valaddr_reg:x8; val_offset:915*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 915*FLEN/8, x10, x1, x4) + +inst_330: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x24c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x354 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1c5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x764c; op2val:0xbb54; +op3val:0x75c5; valaddr_reg:x8; val_offset:918*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 918*FLEN/8, x10, x1, x4) + +inst_331: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x24c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x354 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1c5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x764c; op2val:0xbb54; +op3val:0x75c5; valaddr_reg:x8; val_offset:921*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 921*FLEN/8, x10, x1, x4) + +inst_332: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x24c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x354 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1c5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x764c; op2val:0xbb54; +op3val:0x75c5; valaddr_reg:x8; val_offset:924*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 924*FLEN/8, x10, x1, x4) + +inst_333: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x24c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x354 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1c5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x764c; op2val:0xbb54; +op3val:0x75c5; valaddr_reg:x8; val_offset:927*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 927*FLEN/8, x10, x1, x4) + +inst_334: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x24c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x354 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1c5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x764c; op2val:0xbb54; +op3val:0x75c5; valaddr_reg:x8; val_offset:930*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 930*FLEN/8, x10, x1, x4) + +inst_335: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x336 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x301 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x251 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7336; op2val:0xbb01; +op3val:0x7251; valaddr_reg:x8; val_offset:933*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 933*FLEN/8, x10, x1, x4) + +inst_336: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x336 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x301 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x251 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7336; op2val:0xbb01; +op3val:0x7251; valaddr_reg:x8; val_offset:936*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 936*FLEN/8, x10, x1, x4) + +inst_337: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x336 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x301 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x251 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7336; op2val:0xbb01; +op3val:0x7251; valaddr_reg:x8; val_offset:939*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 939*FLEN/8, x10, x1, x4) + +inst_338: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x336 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x301 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x251 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7336; op2val:0xbb01; +op3val:0x7251; valaddr_reg:x8; val_offset:942*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 942*FLEN/8, x10, x1, x4) + +inst_339: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x336 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x301 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x251 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7336; op2val:0xbb01; +op3val:0x7251; valaddr_reg:x8; val_offset:945*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 945*FLEN/8, x10, x1, x4) + +inst_340: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x322 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3c2 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x2eb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7722; op2val:0xb3c2; +op3val:0x6eeb; valaddr_reg:x8; val_offset:948*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 948*FLEN/8, x10, x1, x4) + +inst_341: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x322 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3c2 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x2eb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7722; op2val:0xb3c2; +op3val:0x6eeb; valaddr_reg:x8; val_offset:951*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 951*FLEN/8, x10, x1, x4) + +inst_342: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x322 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3c2 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x2eb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7722; op2val:0xb3c2; +op3val:0x6eeb; valaddr_reg:x8; val_offset:954*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 954*FLEN/8, x10, x1, x4) + +inst_343: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x322 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3c2 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x2eb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7722; op2val:0xb3c2; +op3val:0x6eeb; valaddr_reg:x8; val_offset:957*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 957*FLEN/8, x10, x1, x4) + +inst_344: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x322 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3c2 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x2eb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7722; op2val:0xb3c2; +op3val:0x6eeb; valaddr_reg:x8; val_offset:960*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 960*FLEN/8, x10, x1, x4) + +inst_345: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1cc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3d0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79cc; op2val:0xbbd0; +op3val:0x79a9; valaddr_reg:x8; val_offset:963*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 963*FLEN/8, x10, x1, x4) + +inst_346: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1cc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3d0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79cc; op2val:0xbbd0; +op3val:0x79a9; valaddr_reg:x8; val_offset:966*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 966*FLEN/8, x10, x1, x4) + +inst_347: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1cc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3d0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79cc; op2val:0xbbd0; +op3val:0x79a9; valaddr_reg:x8; val_offset:969*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 969*FLEN/8, x10, x1, x4) + +inst_348: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1cc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3d0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79cc; op2val:0xbbd0; +op3val:0x79a9; valaddr_reg:x8; val_offset:972*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 972*FLEN/8, x10, x1, x4) + +inst_349: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1cc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3d0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79cc; op2val:0xbbd0; +op3val:0x79a9; valaddr_reg:x8; val_offset:975*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 975*FLEN/8, x10, x1, x4) + +inst_350: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e3 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x0bc and fs3 == 0 and fe3 == 0x19 and fm3 == 0x1ca and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e3; op2val:0xa8bc; +op3val:0x65ca; valaddr_reg:x8; val_offset:978*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 978*FLEN/8, x10, x1, x4) + +inst_351: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e3 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x0bc and fs3 == 0 and fe3 == 0x19 and fm3 == 0x1ca and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e3; op2val:0xa8bc; +op3val:0x65ca; valaddr_reg:x8; val_offset:981*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 981*FLEN/8, x10, x1, x4) + +inst_352: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e3 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x0bc and fs3 == 0 and fe3 == 0x19 and fm3 == 0x1ca and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e3; op2val:0xa8bc; +op3val:0x65ca; valaddr_reg:x8; val_offset:984*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 984*FLEN/8, x10, x1, x4) + +inst_353: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e3 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x0bc and fs3 == 0 and fe3 == 0x19 and fm3 == 0x1ca and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e3; op2val:0xa8bc; +op3val:0x65ca; valaddr_reg:x8; val_offset:987*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 987*FLEN/8, x10, x1, x4) + +inst_354: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e3 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x0bc and fs3 == 0 and fe3 == 0x19 and fm3 == 0x1ca and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e3; op2val:0xa8bc; +op3val:0x65ca; valaddr_reg:x8; val_offset:990*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 990*FLEN/8, x10, x1, x4) + +inst_355: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1d2 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0c0 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2ea and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75d2; op2val:0xbcc0; +op3val:0x76ea; valaddr_reg:x8; val_offset:993*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 993*FLEN/8, x10, x1, x4) + +inst_356: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1d2 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0c0 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2ea and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75d2; op2val:0xbcc0; +op3val:0x76ea; valaddr_reg:x8; val_offset:996*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 996*FLEN/8, x10, x1, x4) + +inst_357: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1d2 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0c0 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2ea and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75d2; op2val:0xbcc0; +op3val:0x76ea; valaddr_reg:x8; val_offset:999*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 999*FLEN/8, x10, x1, x4) + +inst_358: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1d2 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0c0 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2ea and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75d2; op2val:0xbcc0; +op3val:0x76ea; valaddr_reg:x8; val_offset:1002*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1002*FLEN/8, x10, x1, x4) + +inst_359: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1d2 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0c0 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2ea and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75d2; op2val:0xbcc0; +op3val:0x76ea; valaddr_reg:x8; val_offset:1005*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1005*FLEN/8, x10, x1, x4) + +inst_360: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1f8 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x12f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3bd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6df8; op2val:0xc92f; +op3val:0x7bbd; valaddr_reg:x8; val_offset:1008*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1008*FLEN/8, x10, x1, x4) + +inst_361: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1f8 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x12f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3bd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6df8; op2val:0xc92f; +op3val:0x7bbd; valaddr_reg:x8; val_offset:1011*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1011*FLEN/8, x10, x1, x4) + +inst_362: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1f8 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x12f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3bd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6df8; op2val:0xc92f; +op3val:0x7bbd; valaddr_reg:x8; val_offset:1014*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1014*FLEN/8, x10, x1, x4) + +inst_363: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1f8 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x12f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3bd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6df8; op2val:0xc92f; +op3val:0x7bbd; valaddr_reg:x8; val_offset:1017*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1017*FLEN/8, x10, x1, x4) + +inst_364: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1f8 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x12f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3bd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6df8; op2val:0xc92f; +op3val:0x7bbd; valaddr_reg:x8; val_offset:1020*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1020*FLEN/8, x10, x1, x4) + +inst_365: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x152 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x004 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a0a; op2val:0xb952; +op3val:0x7804; valaddr_reg:x8; val_offset:1023*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1023*FLEN/8, x10, x1, x4) + +inst_366: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x152 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x004 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a0a; op2val:0xb952; +op3val:0x7804; valaddr_reg:x8; val_offset:1026*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1026*FLEN/8, x10, x1, x4) + +inst_367: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x152 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x004 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a0a; op2val:0xb952; +op3val:0x7804; valaddr_reg:x8; val_offset:1029*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1029*FLEN/8, x10, x1, x4) + +inst_368: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x152 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x004 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a0a; op2val:0xb952; +op3val:0x7804; valaddr_reg:x8; val_offset:1032*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1032*FLEN/8, x10, x1, x4) + +inst_369: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x152 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x004 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a0a; op2val:0xb952; +op3val:0x7804; valaddr_reg:x8; val_offset:1035*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1035*FLEN/8, x10, x1, x4) + +inst_370: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a3 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x08d and fs3 == 0 and fe3 == 0x1c and fm3 == 0x26b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79a3; op2val:0xb48d; +op3val:0x726b; valaddr_reg:x8; val_offset:1038*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1038*FLEN/8, x10, x1, x4) + +inst_371: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a3 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x08d and fs3 == 0 and fe3 == 0x1c and fm3 == 0x26b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79a3; op2val:0xb48d; +op3val:0x726b; valaddr_reg:x8; val_offset:1041*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1041*FLEN/8, x10, x1, x4) + +inst_372: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a3 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x08d and fs3 == 0 and fe3 == 0x1c and fm3 == 0x26b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79a3; op2val:0xb48d; +op3val:0x726b; valaddr_reg:x8; val_offset:1044*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1044*FLEN/8, x10, x1, x4) + +inst_373: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a3 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x08d and fs3 == 0 and fe3 == 0x1c and fm3 == 0x26b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79a3; op2val:0xb48d; +op3val:0x726b; valaddr_reg:x8; val_offset:1047*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1047*FLEN/8, x10, x1, x4) + +inst_374: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a3 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x08d and fs3 == 0 and fe3 == 0x1c and fm3 == 0x26b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79a3; op2val:0xb48d; +op3val:0x726b; valaddr_reg:x8; val_offset:1050*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1050*FLEN/8, x10, x1, x4) + +inst_375: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x356 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x095 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x034 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7356; op2val:0xc095; +op3val:0x7834; valaddr_reg:x8; val_offset:1053*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1053*FLEN/8, x10, x1, x4) + +inst_376: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x356 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x095 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x034 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7356; op2val:0xc095; +op3val:0x7834; valaddr_reg:x8; val_offset:1056*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1056*FLEN/8, x10, x1, x4) + +inst_377: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x356 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x095 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x034 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7356; op2val:0xc095; +op3val:0x7834; valaddr_reg:x8; val_offset:1059*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1059*FLEN/8, x10, x1, x4) + +inst_378: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x356 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x095 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x034 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7356; op2val:0xc095; +op3val:0x7834; valaddr_reg:x8; val_offset:1062*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1062*FLEN/8, x10, x1, x4) + +inst_379: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x356 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x095 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x034 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7356; op2val:0xc095; +op3val:0x7834; valaddr_reg:x8; val_offset:1065*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1065*FLEN/8, x10, x1, x4) + +inst_380: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f2 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2f5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x12c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f2; op2val:0xbaf5; +op3val:0x792c; valaddr_reg:x8; val_offset:1068*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1068*FLEN/8, x10, x1, x4) + +inst_381: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f2 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2f5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x12c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f2; op2val:0xbaf5; +op3val:0x792c; valaddr_reg:x8; val_offset:1071*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1071*FLEN/8, x10, x1, x4) + +inst_382: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f2 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2f5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x12c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f2; op2val:0xbaf5; +op3val:0x792c; valaddr_reg:x8; val_offset:1074*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1074*FLEN/8, x10, x1, x4) + +inst_383: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f2 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2f5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x12c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f2; op2val:0xbaf5; +op3val:0x792c; valaddr_reg:x8; val_offset:1077*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1077*FLEN/8, x10, x1, x4) + +inst_384: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f2 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2f5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x12c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f2; op2val:0xbaf5; +op3val:0x792c; valaddr_reg:x8; val_offset:1080*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1080*FLEN/8, x10, x1, x4) + +inst_385: +// fs1 == 0 and fe1 == 0x17 and fm1 == 0x2db and fs2 == 1 and fe2 == 0x15 and fm2 == 0x1b8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0e7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5edb; op2val:0xd5b8; +op3val:0x78e7; valaddr_reg:x8; val_offset:1083*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1083*FLEN/8, x10, x1, x4) + +inst_386: +// fs1 == 0 and fe1 == 0x17 and fm1 == 0x2db and fs2 == 1 and fe2 == 0x15 and fm2 == 0x1b8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0e7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5edb; op2val:0xd5b8; +op3val:0x78e7; valaddr_reg:x8; val_offset:1086*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1086*FLEN/8, x10, x1, x4) + +inst_387: +// fs1 == 0 and fe1 == 0x17 and fm1 == 0x2db and fs2 == 1 and fe2 == 0x15 and fm2 == 0x1b8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0e7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5edb; op2val:0xd5b8; +op3val:0x78e7; valaddr_reg:x8; val_offset:1089*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1089*FLEN/8, x10, x1, x4) + +inst_388: +// fs1 == 0 and fe1 == 0x17 and fm1 == 0x2db and fs2 == 1 and fe2 == 0x15 and fm2 == 0x1b8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0e7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5edb; op2val:0xd5b8; +op3val:0x78e7; valaddr_reg:x8; val_offset:1092*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1092*FLEN/8, x10, x1, x4) + +inst_389: +// fs1 == 0 and fe1 == 0x17 and fm1 == 0x2db and fs2 == 1 and fe2 == 0x15 and fm2 == 0x1b8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0e7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5edb; op2val:0xd5b8; +op3val:0x78e7; valaddr_reg:x8; val_offset:1095*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1095*FLEN/8, x10, x1, x4) + +inst_390: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x344 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x28a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1f1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b44; op2val:0xba8a; +op3val:0x79f1; valaddr_reg:x8; val_offset:1098*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1098*FLEN/8, x10, x1, x4) + +inst_391: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x344 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x28a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1f1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b44; op2val:0xba8a; +op3val:0x79f1; valaddr_reg:x8; val_offset:1101*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1101*FLEN/8, x10, x1, x4) + +inst_392: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x344 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x28a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1f1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b44; op2val:0xba8a; +op3val:0x79f1; valaddr_reg:x8; val_offset:1104*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1104*FLEN/8, x10, x1, x4) + +inst_393: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x344 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x28a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1f1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b44; op2val:0xba8a; +op3val:0x79f1; valaddr_reg:x8; val_offset:1107*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1107*FLEN/8, x10, x1, x4) + +inst_394: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x344 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x28a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1f1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b44; op2val:0xba8a; +op3val:0x79f1; valaddr_reg:x8; val_offset:1110*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1110*FLEN/8, x10, x1, x4) + +inst_395: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x36a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x03b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3d9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b6a; op2val:0xbc3b; +op3val:0x7bd9; valaddr_reg:x8; val_offset:1113*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1113*FLEN/8, x10, x1, x4) + +inst_396: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x36a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x03b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3d9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b6a; op2val:0xbc3b; +op3val:0x7bd9; valaddr_reg:x8; val_offset:1116*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1116*FLEN/8, x10, x1, x4) + +inst_397: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x36a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x03b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3d9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b6a; op2val:0xbc3b; +op3val:0x7bd9; valaddr_reg:x8; val_offset:1119*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1119*FLEN/8, x10, x1, x4) + +inst_398: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x36a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x03b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3d9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b6a; op2val:0xbc3b; +op3val:0x7bd9; valaddr_reg:x8; val_offset:1122*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1122*FLEN/8, x10, x1, x4) + +inst_399: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x36a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x03b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3d9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b6a; op2val:0xbc3b; +op3val:0x7bd9; valaddr_reg:x8; val_offset:1125*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1125*FLEN/8, x10, x1, x4) + +inst_400: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x327 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x14d and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0bd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7327; op2val:0xbd4d; +op3val:0x74bd; valaddr_reg:x8; val_offset:1128*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1128*FLEN/8, x10, x1, x4) + +inst_401: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x327 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x14d and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0bd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7327; op2val:0xbd4d; +op3val:0x74bd; valaddr_reg:x8; val_offset:1131*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1131*FLEN/8, x10, x1, x4) + +inst_402: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x327 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x14d and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0bd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7327; op2val:0xbd4d; +op3val:0x74bd; valaddr_reg:x8; val_offset:1134*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1134*FLEN/8, x10, x1, x4) + +inst_403: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x327 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x14d and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0bd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7327; op2val:0xbd4d; +op3val:0x74bd; valaddr_reg:x8; val_offset:1137*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1137*FLEN/8, x10, x1, x4) + +inst_404: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x327 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x14d and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0bd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7327; op2val:0xbd4d; +op3val:0x74bd; valaddr_reg:x8; val_offset:1140*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1140*FLEN/8, x10, x1, x4) + +inst_405: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x060 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x323 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3cf and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7860; op2val:0xbf23; +op3val:0x7bcf; valaddr_reg:x8; val_offset:1143*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1143*FLEN/8, x10, x1, x4) + +inst_406: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x060 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x323 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3cf and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7860; op2val:0xbf23; +op3val:0x7bcf; valaddr_reg:x8; val_offset:1146*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1146*FLEN/8, x10, x1, x4) + +inst_407: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x060 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x323 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3cf and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7860; op2val:0xbf23; +op3val:0x7bcf; valaddr_reg:x8; val_offset:1149*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1149*FLEN/8, x10, x1, x4) + +inst_408: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x060 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x323 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3cf and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7860; op2val:0xbf23; +op3val:0x7bcf; valaddr_reg:x8; val_offset:1152*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1152*FLEN/8, x10, x1, x4) + +inst_409: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x060 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x323 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3cf and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7860; op2val:0xbf23; +op3val:0x7bcf; valaddr_reg:x8; val_offset:1155*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1155*FLEN/8, x10, x1, x4) + +inst_410: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1e7 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x119 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x387 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75e7; op2val:0xc119; +op3val:0x7b87; valaddr_reg:x8; val_offset:1158*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1158*FLEN/8, x10, x1, x4) + +inst_411: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1e7 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x119 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x387 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75e7; op2val:0xc119; +op3val:0x7b87; valaddr_reg:x8; val_offset:1161*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1161*FLEN/8, x10, x1, x4) + +inst_412: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1e7 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x119 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x387 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75e7; op2val:0xc119; +op3val:0x7b87; valaddr_reg:x8; val_offset:1164*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1164*FLEN/8, x10, x1, x4) + +inst_413: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1e7 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x119 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x387 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75e7; op2val:0xc119; +op3val:0x7b87; valaddr_reg:x8; val_offset:1167*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1167*FLEN/8, x10, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_5) + +inst_414: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1e7 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x119 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x387 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75e7; op2val:0xc119; +op3val:0x7b87; valaddr_reg:x8; val_offset:1170*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1170*FLEN/8, x10, x1, x4) + +inst_415: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2cc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0db and fs3 == 0 and fe3 == 0x1e and fm3 == 0x020 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7acc; op2val:0xb8db; +op3val:0x7820; valaddr_reg:x8; val_offset:1173*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1173*FLEN/8, x10, x1, x4) + +inst_416: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2cc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0db and fs3 == 0 and fe3 == 0x1e and fm3 == 0x020 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7acc; op2val:0xb8db; +op3val:0x7820; valaddr_reg:x8; val_offset:1176*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1176*FLEN/8, x10, x1, x4) + +inst_417: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2cc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0db and fs3 == 0 and fe3 == 0x1e and fm3 == 0x020 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7acc; op2val:0xb8db; +op3val:0x7820; valaddr_reg:x8; val_offset:1179*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1179*FLEN/8, x10, x1, x4) + +inst_418: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2cc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0db and fs3 == 0 and fe3 == 0x1e and fm3 == 0x020 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7acc; op2val:0xb8db; +op3val:0x7820; valaddr_reg:x8; val_offset:1182*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1182*FLEN/8, x10, x1, x4) + +inst_419: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2cc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0db and fs3 == 0 and fe3 == 0x1e and fm3 == 0x020 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7acc; op2val:0xb8db; +op3val:0x7820; valaddr_reg:x8; val_offset:1185*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1185*FLEN/8, x10, x1, x4) + +inst_420: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x21f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3a7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78ff; op2val:0xbe1f; +op3val:0x7ba7; valaddr_reg:x8; val_offset:1188*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1188*FLEN/8, x10, x1, x4) + +inst_421: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x21f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3a7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78ff; op2val:0xbe1f; +op3val:0x7ba7; valaddr_reg:x8; val_offset:1191*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1191*FLEN/8, x10, x1, x4) + +inst_422: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x21f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3a7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78ff; op2val:0xbe1f; +op3val:0x7ba7; valaddr_reg:x8; val_offset:1194*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1194*FLEN/8, x10, x1, x4) + +inst_423: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x21f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3a7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78ff; op2val:0xbe1f; +op3val:0x7ba7; valaddr_reg:x8; val_offset:1197*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1197*FLEN/8, x10, x1, x4) + +inst_424: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x21f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3a7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78ff; op2val:0xbe1f; +op3val:0x7ba7; valaddr_reg:x8; val_offset:1200*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1200*FLEN/8, x10, x1, x4) + +inst_425: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x243 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x20b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0bb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a43; op2val:0xb60b; +op3val:0x74bb; valaddr_reg:x8; val_offset:1203*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1203*FLEN/8, x10, x1, x4) + +inst_426: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x243 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x20b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0bb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a43; op2val:0xb60b; +op3val:0x74bb; valaddr_reg:x8; val_offset:1206*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1206*FLEN/8, x10, x1, x4) + +inst_427: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x243 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x20b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0bb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a43; op2val:0xb60b; +op3val:0x74bb; valaddr_reg:x8; val_offset:1209*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1209*FLEN/8, x10, x1, x4) + +inst_428: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x243 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x20b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0bb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a43; op2val:0xb60b; +op3val:0x74bb; valaddr_reg:x8; val_offset:1212*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1212*FLEN/8, x10, x1, x4) + +inst_429: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x243 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x20b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0bb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a43; op2val:0xb60b; +op3val:0x74bb; valaddr_reg:x8; val_offset:1215*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1215*FLEN/8, x10, x1, x4) + +inst_430: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c3 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x368 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x242 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ac3; op2val:0xb368; +op3val:0x7242; valaddr_reg:x8; val_offset:1218*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1218*FLEN/8, x10, x1, x4) + +inst_431: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c3 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x368 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x242 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ac3; op2val:0xb368; +op3val:0x7242; valaddr_reg:x8; val_offset:1221*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1221*FLEN/8, x10, x1, x4) + +inst_432: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c3 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x368 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x242 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ac3; op2val:0xb368; +op3val:0x7242; valaddr_reg:x8; val_offset:1224*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1224*FLEN/8, x10, x1, x4) + +inst_433: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c3 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x368 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x242 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ac3; op2val:0xb368; +op3val:0x7242; valaddr_reg:x8; val_offset:1227*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1227*FLEN/8, x10, x1, x4) + +inst_434: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c3 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x368 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x242 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ac3; op2val:0xb368; +op3val:0x7242; valaddr_reg:x8; val_offset:1230*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1230*FLEN/8, x10, x1, x4) + +inst_435: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ea and fs2 == 1 and fe2 == 0x10 and fm2 == 0x12e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75ea; op2val:0xc12e; +op3val:0x7baa; valaddr_reg:x8; val_offset:1233*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1233*FLEN/8, x10, x1, x4) + +inst_436: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ea and fs2 == 1 and fe2 == 0x10 and fm2 == 0x12e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3aa and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75ea; op2val:0xc12e; +op3val:0x7baa; valaddr_reg:x8; val_offset:1236*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1236*FLEN/8, x10, x1, x4) + +inst_437: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ea and fs2 == 1 and fe2 == 0x10 and fm2 == 0x12e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3aa and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75ea; op2val:0xc12e; +op3val:0x7baa; valaddr_reg:x8; val_offset:1239*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1239*FLEN/8, x10, x1, x4) + +inst_438: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ea and fs2 == 1 and fe2 == 0x10 and fm2 == 0x12e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3aa and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75ea; op2val:0xc12e; +op3val:0x7baa; valaddr_reg:x8; val_offset:1242*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1242*FLEN/8, x10, x1, x4) + +inst_439: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ea and fs2 == 1 and fe2 == 0x10 and fm2 == 0x12e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3aa and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75ea; op2val:0xc12e; +op3val:0x7baa; valaddr_reg:x8; val_offset:1245*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1245*FLEN/8, x10, x1, x4) + +inst_440: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c5 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1e4 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0fd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ac5; op2val:0xb5e4; +op3val:0x74fd; valaddr_reg:x8; val_offset:1248*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1248*FLEN/8, x10, x1, x4) + +inst_441: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c5 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1e4 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0fd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ac5; op2val:0xb5e4; +op3val:0x74fd; valaddr_reg:x8; val_offset:1251*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1251*FLEN/8, x10, x1, x4) + +inst_442: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c5 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1e4 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0fd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ac5; op2val:0xb5e4; +op3val:0x74fd; valaddr_reg:x8; val_offset:1254*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1254*FLEN/8, x10, x1, x4) + +inst_443: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c5 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1e4 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0fd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ac5; op2val:0xb5e4; +op3val:0x74fd; valaddr_reg:x8; val_offset:1257*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1257*FLEN/8, x10, x1, x4) + +inst_444: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c5 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1e4 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0fd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ac5; op2val:0xb5e4; +op3val:0x74fd; valaddr_reg:x8; val_offset:1260*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1260*FLEN/8, x10, x1, x4) + +inst_445: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a5 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x038 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0e6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74a5; op2val:0xc038; +op3val:0x78e6; valaddr_reg:x8; val_offset:1263*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1263*FLEN/8, x10, x1, x4) + +inst_446: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a5 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x038 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0e6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74a5; op2val:0xc038; +op3val:0x78e6; valaddr_reg:x8; val_offset:1266*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1266*FLEN/8, x10, x1, x4) + +inst_447: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a5 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x038 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0e6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74a5; op2val:0xc038; +op3val:0x78e6; valaddr_reg:x8; val_offset:1269*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1269*FLEN/8, x10, x1, x4) + +inst_448: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a5 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x038 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0e6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74a5; op2val:0xc038; +op3val:0x78e6; valaddr_reg:x8; val_offset:1272*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1272*FLEN/8, x10, x1, x4) + +inst_449: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a5 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x038 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0e6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74a5; op2val:0xc038; +op3val:0x78e6; valaddr_reg:x8; val_offset:1275*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1275*FLEN/8, x10, x1, x4) + +inst_450: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2bc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x27f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x178 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7abc; op2val:0xba7f; +op3val:0x7978; valaddr_reg:x8; val_offset:1278*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1278*FLEN/8, x10, x1, x4) + +inst_451: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2bc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x27f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x178 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7abc; op2val:0xba7f; +op3val:0x7978; valaddr_reg:x8; val_offset:1281*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1281*FLEN/8, x10, x1, x4) + +inst_452: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2bc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x27f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x178 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7abc; op2val:0xba7f; +op3val:0x7978; valaddr_reg:x8; val_offset:1284*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1284*FLEN/8, x10, x1, x4) + +inst_453: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2bc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x27f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x178 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7abc; op2val:0xba7f; +op3val:0x7978; valaddr_reg:x8; val_offset:1287*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1287*FLEN/8, x10, x1, x4) + +inst_454: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2bc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x27f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x178 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7abc; op2val:0xba7f; +op3val:0x7978; valaddr_reg:x8; val_offset:1290*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1290*FLEN/8, x10, x1, x4) + +inst_455: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x238 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1d2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b7c; op2val:0xba38; +op3val:0x79d2; valaddr_reg:x8; val_offset:1293*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1293*FLEN/8, x10, x1, x4) + +inst_456: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x238 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1d2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b7c; op2val:0xba38; +op3val:0x79d2; valaddr_reg:x8; val_offset:1296*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1296*FLEN/8, x10, x1, x4) + +inst_457: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x238 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1d2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b7c; op2val:0xba38; +op3val:0x79d2; valaddr_reg:x8; val_offset:1299*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1299*FLEN/8, x10, x1, x4) + +inst_458: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x238 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1d2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b7c; op2val:0xba38; +op3val:0x79d2; valaddr_reg:x8; val_offset:1302*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1302*FLEN/8, x10, x1, x4) + +inst_459: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x238 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1d2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b7c; op2val:0xba38; +op3val:0x79d2; valaddr_reg:x8; val_offset:1305*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1305*FLEN/8, x10, x1, x4) + +inst_460: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x290 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1e5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0d6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a90; op2val:0xb9e5; +op3val:0x78d6; valaddr_reg:x8; val_offset:1308*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1308*FLEN/8, x10, x1, x4) + +inst_461: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x290 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1e5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0d6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a90; op2val:0xb9e5; +op3val:0x78d6; valaddr_reg:x8; val_offset:1311*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1311*FLEN/8, x10, x1, x4) + +inst_462: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x290 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1e5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0d6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a90; op2val:0xb9e5; +op3val:0x78d6; valaddr_reg:x8; val_offset:1314*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1314*FLEN/8, x10, x1, x4) + +inst_463: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x290 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1e5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0d6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a90; op2val:0xb9e5; +op3val:0x78d6; valaddr_reg:x8; val_offset:1317*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1317*FLEN/8, x10, x1, x4) + +inst_464: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x290 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1e5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0d6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a90; op2val:0xb9e5; +op3val:0x78d6; valaddr_reg:x8; val_offset:1320*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1320*FLEN/8, x10, x1, x4) + +inst_465: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ca and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0b8 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2d6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75ca; op2val:0xbcb8; +op3val:0x76d6; valaddr_reg:x8; val_offset:1323*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1323*FLEN/8, x10, x1, x4) + +inst_466: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ca and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0b8 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2d6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75ca; op2val:0xbcb8; +op3val:0x76d6; valaddr_reg:x8; val_offset:1326*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1326*FLEN/8, x10, x1, x4) + +inst_467: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ca and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0b8 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2d6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75ca; op2val:0xbcb8; +op3val:0x76d6; valaddr_reg:x8; val_offset:1329*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1329*FLEN/8, x10, x1, x4) + +inst_468: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ca and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0b8 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2d6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75ca; op2val:0xbcb8; +op3val:0x76d6; valaddr_reg:x8; val_offset:1332*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1332*FLEN/8, x10, x1, x4) + +inst_469: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ca and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0b8 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2d6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75ca; op2val:0xbcb8; +op3val:0x76d6; valaddr_reg:x8; val_offset:1335*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1335*FLEN/8, x10, x1, x4) + +inst_470: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d5 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x051 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x03a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77d5; op2val:0xbc51; +op3val:0x783a; valaddr_reg:x8; val_offset:1338*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1338*FLEN/8, x10, x1, x4) + +inst_471: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d5 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x051 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x03a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77d5; op2val:0xbc51; +op3val:0x783a; valaddr_reg:x8; val_offset:1341*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1341*FLEN/8, x10, x1, x4) + +inst_472: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d5 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x051 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x03a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77d5; op2val:0xbc51; +op3val:0x783a; valaddr_reg:x8; val_offset:1344*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1344*FLEN/8, x10, x1, x4) + +inst_473: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d5 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x051 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x03a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77d5; op2val:0xbc51; +op3val:0x783a; valaddr_reg:x8; val_offset:1347*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1347*FLEN/8, x10, x1, x4) + +inst_474: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d5 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x051 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x03a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77d5; op2val:0xbc51; +op3val:0x783a; valaddr_reg:x8; val_offset:1350*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1350*FLEN/8, x10, x1, x4) + +inst_475: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b3 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x121 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x04c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ab3; op2val:0xb521; +op3val:0x744c; valaddr_reg:x8; val_offset:1353*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1353*FLEN/8, x10, x1, x4) + +inst_476: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b3 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x121 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x04c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ab3; op2val:0xb521; +op3val:0x744c; valaddr_reg:x8; val_offset:1356*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1356*FLEN/8, x10, x1, x4) + +inst_477: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b3 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x121 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x04c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ab3; op2val:0xb521; +op3val:0x744c; valaddr_reg:x8; val_offset:1359*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1359*FLEN/8, x10, x1, x4) + +inst_478: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b3 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x121 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x04c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ab3; op2val:0xb521; +op3val:0x744c; valaddr_reg:x8; val_offset:1362*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1362*FLEN/8, x10, x1, x4) + +inst_479: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b3 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x121 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x04c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ab3; op2val:0xb521; +op3val:0x744c; valaddr_reg:x8; val_offset:1365*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1365*FLEN/8, x10, x1, x4) + +inst_480: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x064 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x157 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1dc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c64; op2val:0xc957; +op3val:0x79dc; valaddr_reg:x8; val_offset:1368*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1368*FLEN/8, x10, x1, x4) + +inst_481: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x064 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x157 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1dc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c64; op2val:0xc957; +op3val:0x79dc; valaddr_reg:x8; val_offset:1371*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1371*FLEN/8, x10, x1, x4) + +inst_482: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x064 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x157 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1dc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c64; op2val:0xc957; +op3val:0x79dc; valaddr_reg:x8; val_offset:1374*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1374*FLEN/8, x10, x1, x4) + +inst_483: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x064 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x157 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1dc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c64; op2val:0xc957; +op3val:0x79dc; valaddr_reg:x8; val_offset:1377*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1377*FLEN/8, x10, x1, x4) + +inst_484: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x064 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x157 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1dc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c64; op2val:0xc957; +op3val:0x79dc; valaddr_reg:x8; val_offset:1380*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1380*FLEN/8, x10, x1, x4) + +inst_485: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x055 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x232 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2b6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7455; op2val:0xbe32; +op3val:0x76b6; valaddr_reg:x8; val_offset:1383*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1383*FLEN/8, x10, x1, x4) + +inst_486: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x055 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x232 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2b6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7455; op2val:0xbe32; +op3val:0x76b6; valaddr_reg:x8; val_offset:1386*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1386*FLEN/8, x10, x1, x4) + +inst_487: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x055 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x232 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2b6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7455; op2val:0xbe32; +op3val:0x76b6; valaddr_reg:x8; val_offset:1389*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1389*FLEN/8, x10, x1, x4) + +inst_488: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x055 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x232 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2b6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7455; op2val:0xbe32; +op3val:0x76b6; valaddr_reg:x8; val_offset:1392*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1392*FLEN/8, x10, x1, x4) + +inst_489: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x055 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x232 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2b6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7455; op2val:0xbe32; +op3val:0x76b6; valaddr_reg:x8; val_offset:1395*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1395*FLEN/8, x10, x1, x4) + +inst_490: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x37c and fs2 == 1 and fe2 == 0x11 and fm2 == 0x315 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f7c; op2val:0xc715; +op3val:0x7aa1; valaddr_reg:x8; val_offset:1398*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1398*FLEN/8, x10, x1, x4) + +inst_491: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x37c and fs2 == 1 and fe2 == 0x11 and fm2 == 0x315 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f7c; op2val:0xc715; +op3val:0x7aa1; valaddr_reg:x8; val_offset:1401*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1401*FLEN/8, x10, x1, x4) + +inst_492: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x37c and fs2 == 1 and fe2 == 0x11 and fm2 == 0x315 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f7c; op2val:0xc715; +op3val:0x7aa1; valaddr_reg:x8; val_offset:1404*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1404*FLEN/8, x10, x1, x4) + +inst_493: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x37c and fs2 == 1 and fe2 == 0x11 and fm2 == 0x315 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f7c; op2val:0xc715; +op3val:0x7aa1; valaddr_reg:x8; val_offset:1407*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1407*FLEN/8, x10, x1, x4) + +inst_494: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x37c and fs2 == 1 and fe2 == 0x11 and fm2 == 0x315 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f7c; op2val:0xc715; +op3val:0x7aa1; valaddr_reg:x8; val_offset:1410*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1410*FLEN/8, x10, x1, x4) + +inst_495: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x061 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x042 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7461; op2val:0xbc42; +op3val:0x74aa; valaddr_reg:x8; val_offset:1413*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1413*FLEN/8, x10, x1, x4) + +inst_496: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x061 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x042 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0aa and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7461; op2val:0xbc42; +op3val:0x74aa; valaddr_reg:x8; val_offset:1416*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1416*FLEN/8, x10, x1, x4) + +inst_497: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x061 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x042 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0aa and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7461; op2val:0xbc42; +op3val:0x74aa; valaddr_reg:x8; val_offset:1419*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1419*FLEN/8, x10, x1, x4) + +inst_498: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x061 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x042 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0aa and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7461; op2val:0xbc42; +op3val:0x74aa; valaddr_reg:x8; val_offset:1422*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1422*FLEN/8, x10, x1, x4) + +inst_499: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x061 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x042 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0aa and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7461; op2val:0xbc42; +op3val:0x74aa; valaddr_reg:x8; val_offset:1425*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1425*FLEN/8, x10, x1, x4) + +inst_500: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x104 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x008 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a6e; op2val:0xb904; +op3val:0x7808; valaddr_reg:x8; val_offset:1428*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1428*FLEN/8, x10, x1, x4) + +inst_501: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x104 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x008 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a6e; op2val:0xb904; +op3val:0x7808; valaddr_reg:x8; val_offset:1431*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1431*FLEN/8, x10, x1, x4) + +inst_502: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x104 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x008 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a6e; op2val:0xb904; +op3val:0x7808; valaddr_reg:x8; val_offset:1434*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1434*FLEN/8, x10, x1, x4) + +inst_503: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x104 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x008 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a6e; op2val:0xb904; +op3val:0x7808; valaddr_reg:x8; val_offset:1437*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1437*FLEN/8, x10, x1, x4) + +inst_504: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x104 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x008 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a6e; op2val:0xb904; +op3val:0x7808; valaddr_reg:x8; val_offset:1440*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1440*FLEN/8, x10, x1, x4) + +inst_505: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x06f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x268 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x31a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x746f; op2val:0xc268; +op3val:0x7b1a; valaddr_reg:x8; val_offset:1443*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1443*FLEN/8, x10, x1, x4) + +inst_506: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x06f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x268 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x31a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x746f; op2val:0xc268; +op3val:0x7b1a; valaddr_reg:x8; val_offset:1446*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1446*FLEN/8, x10, x1, x4) + +inst_507: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x06f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x268 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x31a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x746f; op2val:0xc268; +op3val:0x7b1a; valaddr_reg:x8; val_offset:1449*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1449*FLEN/8, x10, x1, x4) + +inst_508: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x06f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x268 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x31a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x746f; op2val:0xc268; +op3val:0x7b1a; valaddr_reg:x8; val_offset:1452*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1452*FLEN/8, x10, x1, x4) + +inst_509: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x06f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x268 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x31a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x746f; op2val:0xc268; +op3val:0x7b1a; valaddr_reg:x8; val_offset:1455*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1455*FLEN/8, x10, x1, x4) + +inst_510: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x295 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x305 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1c7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7695; op2val:0xbb05; +op3val:0x75c7; valaddr_reg:x8; val_offset:1458*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1458*FLEN/8, x10, x1, x4) + +inst_511: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x295 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x305 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1c7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7695; op2val:0xbb05; +op3val:0x75c7; valaddr_reg:x8; val_offset:1461*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1461*FLEN/8, x10, x1, x4) + +inst_512: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x295 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x305 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1c7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7695; op2val:0xbb05; +op3val:0x75c7; valaddr_reg:x8; val_offset:1464*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1464*FLEN/8, x10, x1, x4) + +inst_513: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x295 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x305 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1c7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7695; op2val:0xbb05; +op3val:0x75c7; valaddr_reg:x8; val_offset:1467*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1467*FLEN/8, x10, x1, x4) + +inst_514: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x295 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x305 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1c7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7695; op2val:0xbb05; +op3val:0x75c7; valaddr_reg:x8; val_offset:1470*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1470*FLEN/8, x10, x1, x4) + +inst_515: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x28c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x251 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bb8; op2val:0xba8c; +op3val:0x7a51; valaddr_reg:x8; val_offset:1473*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1473*FLEN/8, x10, x1, x4) + +inst_516: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x28c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x251 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bb8; op2val:0xba8c; +op3val:0x7a51; valaddr_reg:x8; val_offset:1476*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1476*FLEN/8, x10, x1, x4) + +inst_517: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x28c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x251 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bb8; op2val:0xba8c; +op3val:0x7a51; valaddr_reg:x8; val_offset:1479*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1479*FLEN/8, x10, x1, x4) + +inst_518: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x28c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x251 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bb8; op2val:0xba8c; +op3val:0x7a51; valaddr_reg:x8; val_offset:1482*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1482*FLEN/8, x10, x1, x4) + +inst_519: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x28c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x251 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bb8; op2val:0xba8c; +op3val:0x7a51; valaddr_reg:x8; val_offset:1485*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1485*FLEN/8, x10, x1, x4) + +inst_520: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f9 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x159 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f9; op2val:0xb559; +op3val:0x73fe; valaddr_reg:x8; val_offset:1488*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1488*FLEN/8, x10, x1, x4) + +inst_521: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f9 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x159 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3fe and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f9; op2val:0xb559; +op3val:0x73fe; valaddr_reg:x8; val_offset:1491*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1491*FLEN/8, x10, x1, x4) + +inst_522: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f9 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x159 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3fe and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f9; op2val:0xb559; +op3val:0x73fe; valaddr_reg:x8; val_offset:1494*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1494*FLEN/8, x10, x1, x4) + +inst_523: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f9 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x159 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3fe and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f9; op2val:0xb559; +op3val:0x73fe; valaddr_reg:x8; val_offset:1497*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1497*FLEN/8, x10, x1, x4) + +inst_524: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f9 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x159 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3fe and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f9; op2val:0xb559; +op3val:0x73fe; valaddr_reg:x8; val_offset:1500*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1500*FLEN/8, x10, x1, x4) + +inst_525: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x280 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1de and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0c5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a80; op2val:0xb9de; +op3val:0x78c5; valaddr_reg:x8; val_offset:1503*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1503*FLEN/8, x10, x1, x4) + +inst_526: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x280 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1de and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0c5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a80; op2val:0xb9de; +op3val:0x78c5; valaddr_reg:x8; val_offset:1506*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1506*FLEN/8, x10, x1, x4) + +inst_527: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x280 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1de and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0c5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a80; op2val:0xb9de; +op3val:0x78c5; valaddr_reg:x8; val_offset:1509*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1509*FLEN/8, x10, x1, x4) + +inst_528: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x280 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1de and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0c5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a80; op2val:0xb9de; +op3val:0x78c5; valaddr_reg:x8; val_offset:1512*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1512*FLEN/8, x10, x1, x4) + +inst_529: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x280 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1de and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0c5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a80; op2val:0xb9de; +op3val:0x78c5; valaddr_reg:x8; val_offset:1515*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1515*FLEN/8, x10, x1, x4) + +inst_530: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a2 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x318 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1e2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aa2; op2val:0xb718; +op3val:0x75e2; valaddr_reg:x8; val_offset:1518*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1518*FLEN/8, x10, x1, x4) + +inst_531: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a2 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x318 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1e2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aa2; op2val:0xb718; +op3val:0x75e2; valaddr_reg:x8; val_offset:1521*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1521*FLEN/8, x10, x1, x4) + +inst_532: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a2 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x318 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1e2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aa2; op2val:0xb718; +op3val:0x75e2; valaddr_reg:x8; val_offset:1524*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1524*FLEN/8, x10, x1, x4) + +inst_533: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a2 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x318 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1e2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aa2; op2val:0xb718; +op3val:0x75e2; valaddr_reg:x8; val_offset:1527*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1527*FLEN/8, x10, x1, x4) + +inst_534: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a2 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x318 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1e2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aa2; op2val:0xb718; +op3val:0x75e2; valaddr_reg:x8; val_offset:1530*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1530*FLEN/8, x10, x1, x4) + +inst_535: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x23e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x010 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x258 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a3e; op2val:0xbc10; +op3val:0x7a58; valaddr_reg:x8; val_offset:1533*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1533*FLEN/8, x10, x1, x4) + +inst_536: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x23e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x010 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x258 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a3e; op2val:0xbc10; +op3val:0x7a58; valaddr_reg:x8; val_offset:1536*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1536*FLEN/8, x10, x1, x4) + +inst_537: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x23e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x010 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x258 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a3e; op2val:0xbc10; +op3val:0x7a58; valaddr_reg:x8; val_offset:1539*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1539*FLEN/8, x10, x1, x4) + +inst_538: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x23e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x010 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x258 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a3e; op2val:0xbc10; +op3val:0x7a58; valaddr_reg:x8; val_offset:1542*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1542*FLEN/8, x10, x1, x4) + +inst_539: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x23e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x010 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x258 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a3e; op2val:0xbc10; +op3val:0x7a58; valaddr_reg:x8; val_offset:1545*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1545*FLEN/8, x10, x1, x4) + +inst_540: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x234 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2c0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x13c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7634; op2val:0xbec0; +op3val:0x793c; valaddr_reg:x8; val_offset:1548*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1548*FLEN/8, x10, x1, x4) + +inst_541: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x234 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2c0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x13c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7634; op2val:0xbec0; +op3val:0x793c; valaddr_reg:x8; val_offset:1551*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1551*FLEN/8, x10, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_6) + +inst_542: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x234 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2c0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x13c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7634; op2val:0xbec0; +op3val:0x793c; valaddr_reg:x8; val_offset:1554*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1554*FLEN/8, x10, x1, x4) + +inst_543: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x234 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2c0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x13c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7634; op2val:0xbec0; +op3val:0x793c; valaddr_reg:x8; val_offset:1557*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1557*FLEN/8, x10, x1, x4) + +inst_544: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x234 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2c0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x13c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7634; op2val:0xbec0; +op3val:0x793c; valaddr_reg:x8; val_offset:1560*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1560*FLEN/8, x10, x1, x4) + +inst_545: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x23d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x117 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a3d; op2val:0xbd17; +op3val:0x7bf0; valaddr_reg:x8; val_offset:1563*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1563*FLEN/8, x10, x1, x4) + +inst_546: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x23d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x117 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3f0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a3d; op2val:0xbd17; +op3val:0x7bf0; valaddr_reg:x8; val_offset:1566*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1566*FLEN/8, x10, x1, x4) + +inst_547: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x23d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x117 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3f0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a3d; op2val:0xbd17; +op3val:0x7bf0; valaddr_reg:x8; val_offset:1569*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1569*FLEN/8, x10, x1, x4) + +inst_548: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x23d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x117 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3f0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a3d; op2val:0xbd17; +op3val:0x7bf0; valaddr_reg:x8; val_offset:1572*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1572*FLEN/8, x10, x1, x4) + +inst_549: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x23d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x117 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3f0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a3d; op2val:0xbd17; +op3val:0x7bf0; valaddr_reg:x8; val_offset:1575*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1575*FLEN/8, x10, x1, x4) + +inst_550: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x35c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2d5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x249 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b5c; op2val:0xbad5; +op3val:0x7a49; valaddr_reg:x8; val_offset:1578*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1578*FLEN/8, x10, x1, x4) + +inst_551: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x35c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2d5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x249 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b5c; op2val:0xbad5; +op3val:0x7a49; valaddr_reg:x8; val_offset:1581*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1581*FLEN/8, x10, x1, x4) + +inst_552: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x35c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2d5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x249 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b5c; op2val:0xbad5; +op3val:0x7a49; valaddr_reg:x8; val_offset:1584*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1584*FLEN/8, x10, x1, x4) + +inst_553: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x35c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2d5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x249 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b5c; op2val:0xbad5; +op3val:0x7a49; valaddr_reg:x8; val_offset:1587*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1587*FLEN/8, x10, x1, x4) + +inst_554: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x35c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2d5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x249 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b5c; op2val:0xbad5; +op3val:0x7a49; valaddr_reg:x8; val_offset:1590*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1590*FLEN/8, x10, x1, x4) + +inst_555: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x060 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x075 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0e1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7060; op2val:0xc475; +op3val:0x78e1; valaddr_reg:x8; val_offset:1593*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1593*FLEN/8, x10, x1, x4) + +inst_556: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x060 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x075 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0e1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7060; op2val:0xc475; +op3val:0x78e1; valaddr_reg:x8; val_offset:1596*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1596*FLEN/8, x10, x1, x4) + +inst_557: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x060 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x075 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0e1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7060; op2val:0xc475; +op3val:0x78e1; valaddr_reg:x8; val_offset:1599*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1599*FLEN/8, x10, x1, x4) + +inst_558: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x060 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x075 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0e1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7060; op2val:0xc475; +op3val:0x78e1; valaddr_reg:x8; val_offset:1602*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1602*FLEN/8, x10, x1, x4) + +inst_559: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x060 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x075 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0e1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7060; op2val:0xc475; +op3val:0x78e1; valaddr_reg:x8; val_offset:1605*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1605*FLEN/8, x10, x1, x4) + +inst_560: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x17a and fs2 == 1 and fe2 == 0x0c and fm2 == 0x011 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x191 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x797a; op2val:0xb011; +op3val:0x6d91; valaddr_reg:x8; val_offset:1608*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1608*FLEN/8, x10, x1, x4) + +inst_561: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x17a and fs2 == 1 and fe2 == 0x0c and fm2 == 0x011 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x191 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x797a; op2val:0xb011; +op3val:0x6d91; valaddr_reg:x8; val_offset:1611*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1611*FLEN/8, x10, x1, x4) + +inst_562: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x17a and fs2 == 1 and fe2 == 0x0c and fm2 == 0x011 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x191 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x797a; op2val:0xb011; +op3val:0x6d91; valaddr_reg:x8; val_offset:1614*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1614*FLEN/8, x10, x1, x4) + +inst_563: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x17a and fs2 == 1 and fe2 == 0x0c and fm2 == 0x011 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x191 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x797a; op2val:0xb011; +op3val:0x6d91; valaddr_reg:x8; val_offset:1617*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1617*FLEN/8, x10, x1, x4) + +inst_564: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x17a and fs2 == 1 and fe2 == 0x0c and fm2 == 0x011 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x191 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x797a; op2val:0xb011; +op3val:0x6d91; valaddr_reg:x8; val_offset:1620*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1620*FLEN/8, x10, x1, x4) + +inst_565: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x366 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x382 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7766; op2val:0xbf82; +op3val:0x7af2; valaddr_reg:x8; val_offset:1623*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1623*FLEN/8, x10, x1, x4) + +inst_566: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x366 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x382 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7766; op2val:0xbf82; +op3val:0x7af2; valaddr_reg:x8; val_offset:1626*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1626*FLEN/8, x10, x1, x4) + +inst_567: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x366 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x382 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7766; op2val:0xbf82; +op3val:0x7af2; valaddr_reg:x8; val_offset:1629*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1629*FLEN/8, x10, x1, x4) + +inst_568: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x366 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x382 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7766; op2val:0xbf82; +op3val:0x7af2; valaddr_reg:x8; val_offset:1632*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1632*FLEN/8, x10, x1, x4) + +inst_569: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x366 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x382 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7766; op2val:0xbf82; +op3val:0x7af2; valaddr_reg:x8; val_offset:1635*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1635*FLEN/8, x10, x1, x4) + +inst_570: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x33d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x016 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x366 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b3d; op2val:0xbc16; +op3val:0x7b66; valaddr_reg:x8; val_offset:1638*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1638*FLEN/8, x10, x1, x4) + +inst_571: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x33d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x016 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x366 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b3d; op2val:0xbc16; +op3val:0x7b66; valaddr_reg:x8; val_offset:1641*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1641*FLEN/8, x10, x1, x4) + +inst_572: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x33d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x016 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x366 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b3d; op2val:0xbc16; +op3val:0x7b66; valaddr_reg:x8; val_offset:1644*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1644*FLEN/8, x10, x1, x4) + +inst_573: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x33d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x016 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x366 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b3d; op2val:0xbc16; +op3val:0x7b66; valaddr_reg:x8; val_offset:1647*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1647*FLEN/8, x10, x1, x4) + +inst_574: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x33d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x016 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x366 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b3d; op2val:0xbc16; +op3val:0x7b66; valaddr_reg:x8; val_offset:1650*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1650*FLEN/8, x10, x1, x4) + +inst_575: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ee and fs2 == 1 and fe2 == 0x11 and fm2 == 0x28c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0da and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dee; op2val:0xc68c; +op3val:0x78da; valaddr_reg:x8; val_offset:1653*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1653*FLEN/8, x10, x1, x4) + +inst_576: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ee and fs2 == 1 and fe2 == 0x11 and fm2 == 0x28c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0da and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dee; op2val:0xc68c; +op3val:0x78da; valaddr_reg:x8; val_offset:1656*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1656*FLEN/8, x10, x1, x4) + +inst_577: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ee and fs2 == 1 and fe2 == 0x11 and fm2 == 0x28c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0da and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dee; op2val:0xc68c; +op3val:0x78da; valaddr_reg:x8; val_offset:1659*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1659*FLEN/8, x10, x1, x4) + +inst_578: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ee and fs2 == 1 and fe2 == 0x11 and fm2 == 0x28c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0da and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dee; op2val:0xc68c; +op3val:0x78da; valaddr_reg:x8; val_offset:1662*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1662*FLEN/8, x10, x1, x4) + +inst_579: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ee and fs2 == 1 and fe2 == 0x11 and fm2 == 0x28c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0da and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dee; op2val:0xc68c; +op3val:0x78da; valaddr_reg:x8; val_offset:1665*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1665*FLEN/8, x10, x1, x4) + +inst_580: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ea and fs2 == 1 and fe2 == 0x0e and fm2 == 0x209 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x138 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aea; op2val:0xba09; +op3val:0x7938; valaddr_reg:x8; val_offset:1668*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1668*FLEN/8, x10, x1, x4) + +inst_581: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ea and fs2 == 1 and fe2 == 0x0e and fm2 == 0x209 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x138 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aea; op2val:0xba09; +op3val:0x7938; valaddr_reg:x8; val_offset:1671*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1671*FLEN/8, x10, x1, x4) + +inst_582: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ea and fs2 == 1 and fe2 == 0x0e and fm2 == 0x209 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x138 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aea; op2val:0xba09; +op3val:0x7938; valaddr_reg:x8; val_offset:1674*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1674*FLEN/8, x10, x1, x4) + +inst_583: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ea and fs2 == 1 and fe2 == 0x0e and fm2 == 0x209 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x138 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aea; op2val:0xba09; +op3val:0x7938; valaddr_reg:x8; val_offset:1677*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1677*FLEN/8, x10, x1, x4) + +inst_584: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ea and fs2 == 1 and fe2 == 0x0e and fm2 == 0x209 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x138 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aea; op2val:0xba09; +op3val:0x7938; valaddr_reg:x8; val_offset:1680*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1680*FLEN/8, x10, x1, x4) + +inst_585: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x11d and fs2 == 1 and fe2 == 0x0b and fm2 == 0x3bf and fs3 == 0 and fe3 == 0x1a and fm3 == 0x0f4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x751d; op2val:0xafbf; +op3val:0x68f4; valaddr_reg:x8; val_offset:1683*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1683*FLEN/8, x10, x1, x4) + +inst_586: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x11d and fs2 == 1 and fe2 == 0x0b and fm2 == 0x3bf and fs3 == 0 and fe3 == 0x1a and fm3 == 0x0f4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x751d; op2val:0xafbf; +op3val:0x68f4; valaddr_reg:x8; val_offset:1686*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1686*FLEN/8, x10, x1, x4) + +inst_587: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x11d and fs2 == 1 and fe2 == 0x0b and fm2 == 0x3bf and fs3 == 0 and fe3 == 0x1a and fm3 == 0x0f4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x751d; op2val:0xafbf; +op3val:0x68f4; valaddr_reg:x8; val_offset:1689*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1689*FLEN/8, x10, x1, x4) + +inst_588: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x11d and fs2 == 1 and fe2 == 0x0b and fm2 == 0x3bf and fs3 == 0 and fe3 == 0x1a and fm3 == 0x0f4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x751d; op2val:0xafbf; +op3val:0x68f4; valaddr_reg:x8; val_offset:1692*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1692*FLEN/8, x10, x1, x4) + +inst_589: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x11d and fs2 == 1 and fe2 == 0x0b and fm2 == 0x3bf and fs3 == 0 and fe3 == 0x1a and fm3 == 0x0f4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x751d; op2val:0xafbf; +op3val:0x68f4; valaddr_reg:x8; val_offset:1695*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1695*FLEN/8, x10, x1, x4) + +inst_590: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x35a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x378 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2de and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b5a; op2val:0xbb78; +op3val:0x7ade; valaddr_reg:x8; val_offset:1698*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1698*FLEN/8, x10, x1, x4) + +inst_591: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x35a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x378 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2de and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b5a; op2val:0xbb78; +op3val:0x7ade; valaddr_reg:x8; val_offset:1701*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1701*FLEN/8, x10, x1, x4) + +inst_592: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x35a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x378 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2de and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b5a; op2val:0xbb78; +op3val:0x7ade; valaddr_reg:x8; val_offset:1704*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1704*FLEN/8, x10, x1, x4) + +inst_593: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x35a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x378 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2de and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b5a; op2val:0xbb78; +op3val:0x7ade; valaddr_reg:x8; val_offset:1707*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1707*FLEN/8, x10, x1, x4) + +inst_594: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x35a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x378 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2de and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b5a; op2val:0xbb78; +op3val:0x7ade; valaddr_reg:x8; val_offset:1710*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1710*FLEN/8, x10, x1, x4) + +inst_595: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x13a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x07b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1db and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x793a; op2val:0xb87b; +op3val:0x75db; valaddr_reg:x8; val_offset:1713*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1713*FLEN/8, x10, x1, x4) + +inst_596: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x13a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x07b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1db and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x793a; op2val:0xb87b; +op3val:0x75db; valaddr_reg:x8; val_offset:1716*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1716*FLEN/8, x10, x1, x4) + +inst_597: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x13a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x07b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1db and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x793a; op2val:0xb87b; +op3val:0x75db; valaddr_reg:x8; val_offset:1719*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1719*FLEN/8, x10, x1, x4) + +inst_598: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x13a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x07b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1db and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x793a; op2val:0xb87b; +op3val:0x75db; valaddr_reg:x8; val_offset:1722*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1722*FLEN/8, x10, x1, x4) + +inst_599: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x13a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x07b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1db and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x793a; op2val:0xb87b; +op3val:0x75db; valaddr_reg:x8; val_offset:1725*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1725*FLEN/8, x10, x1, x4) + +inst_600: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x29f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3de and fs3 == 0 and fe3 == 0x1e and fm3 == 0x283 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a9f; op2val:0xbbde; +op3val:0x7a83; valaddr_reg:x8; val_offset:1728*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1728*FLEN/8, x10, x1, x4) + +inst_601: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x29f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3de and fs3 == 0 and fe3 == 0x1e and fm3 == 0x283 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a9f; op2val:0xbbde; +op3val:0x7a83; valaddr_reg:x8; val_offset:1731*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1731*FLEN/8, x10, x1, x4) + +inst_602: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x29f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3de and fs3 == 0 and fe3 == 0x1e and fm3 == 0x283 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a9f; op2val:0xbbde; +op3val:0x7a83; valaddr_reg:x8; val_offset:1734*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1734*FLEN/8, x10, x1, x4) + +inst_603: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x29f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3de and fs3 == 0 and fe3 == 0x1e and fm3 == 0x283 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a9f; op2val:0xbbde; +op3val:0x7a83; valaddr_reg:x8; val_offset:1737*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1737*FLEN/8, x10, x1, x4) + +inst_604: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x29f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3de and fs3 == 0 and fe3 == 0x1e and fm3 == 0x283 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a9f; op2val:0xbbde; +op3val:0x7a83; valaddr_reg:x8; val_offset:1740*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1740*FLEN/8, x10, x1, x4) + +inst_605: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1cb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x29e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0cb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79cb; op2val:0xba9e; +op3val:0x78cb; valaddr_reg:x8; val_offset:1743*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1743*FLEN/8, x10, x1, x4) + +inst_606: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1cb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x29e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0cb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79cb; op2val:0xba9e; +op3val:0x78cb; valaddr_reg:x8; val_offset:1746*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1746*FLEN/8, x10, x1, x4) + +inst_607: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1cb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x29e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0cb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79cb; op2val:0xba9e; +op3val:0x78cb; valaddr_reg:x8; val_offset:1749*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1749*FLEN/8, x10, x1, x4) + +inst_608: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1cb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x29e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0cb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79cb; op2val:0xba9e; +op3val:0x78cb; valaddr_reg:x8; val_offset:1752*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1752*FLEN/8, x10, x1, x4) + +inst_609: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1cb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x29e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0cb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79cb; op2val:0xba9e; +op3val:0x78cb; valaddr_reg:x8; val_offset:1755*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1755*FLEN/8, x10, x1, x4) + +inst_610: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x11b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x36e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0be and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x751b; op2val:0xbb6e; +op3val:0x74be; valaddr_reg:x8; val_offset:1758*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1758*FLEN/8, x10, x1, x4) + +inst_611: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x11b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x36e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0be and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x751b; op2val:0xbb6e; +op3val:0x74be; valaddr_reg:x8; val_offset:1761*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1761*FLEN/8, x10, x1, x4) + +inst_612: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x11b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x36e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0be and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x751b; op2val:0xbb6e; +op3val:0x74be; valaddr_reg:x8; val_offset:1764*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1764*FLEN/8, x10, x1, x4) + +inst_613: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x11b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x36e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0be and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x751b; op2val:0xbb6e; +op3val:0x74be; valaddr_reg:x8; val_offset:1767*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1767*FLEN/8, x10, x1, x4) + +inst_614: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x11b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x36e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0be and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x751b; op2val:0xbb6e; +op3val:0x74be; valaddr_reg:x8; val_offset:1770*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1770*FLEN/8, x10, x1, x4) + +inst_615: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1b7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x350 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x139 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75b7; op2val:0xbb50; +op3val:0x7539; valaddr_reg:x8; val_offset:1773*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1773*FLEN/8, x10, x1, x4) + +inst_616: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1b7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x350 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x139 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75b7; op2val:0xbb50; +op3val:0x7539; valaddr_reg:x8; val_offset:1776*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1776*FLEN/8, x10, x1, x4) + +inst_617: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1b7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x350 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x139 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75b7; op2val:0xbb50; +op3val:0x7539; valaddr_reg:x8; val_offset:1779*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1779*FLEN/8, x10, x1, x4) + +inst_618: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1b7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x350 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x139 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75b7; op2val:0xbb50; +op3val:0x7539; valaddr_reg:x8; val_offset:1782*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1782*FLEN/8, x10, x1, x4) + +inst_619: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1b7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x350 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x139 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75b7; op2val:0xbb50; +op3val:0x7539; valaddr_reg:x8; val_offset:1785*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1785*FLEN/8, x10, x1, x4) + +inst_620: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x028 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x303 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x34a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7828; op2val:0xb303; +op3val:0x6f4a; valaddr_reg:x8; val_offset:1788*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1788*FLEN/8, x10, x1, x4) + +inst_621: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x028 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x303 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x34a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7828; op2val:0xb303; +op3val:0x6f4a; valaddr_reg:x8; val_offset:1791*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1791*FLEN/8, x10, x1, x4) + +inst_622: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x028 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x303 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x34a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7828; op2val:0xb303; +op3val:0x6f4a; valaddr_reg:x8; val_offset:1794*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1794*FLEN/8, x10, x1, x4) + +inst_623: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x028 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x303 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x34a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7828; op2val:0xb303; +op3val:0x6f4a; valaddr_reg:x8; val_offset:1797*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1797*FLEN/8, x10, x1, x4) + +inst_624: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x028 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x303 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x34a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7828; op2val:0xb303; +op3val:0x6f4a; valaddr_reg:x8; val_offset:1800*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1800*FLEN/8, x10, x1, x4) + +inst_625: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c4 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3b8 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x190 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79c4; op2val:0xb7b8; +op3val:0x7590; valaddr_reg:x8; val_offset:1803*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1803*FLEN/8, x10, x1, x4) + +inst_626: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c4 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3b8 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x190 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79c4; op2val:0xb7b8; +op3val:0x7590; valaddr_reg:x8; val_offset:1806*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1806*FLEN/8, x10, x1, x4) + +inst_627: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c4 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3b8 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x190 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79c4; op2val:0xb7b8; +op3val:0x7590; valaddr_reg:x8; val_offset:1809*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1809*FLEN/8, x10, x1, x4) + +inst_628: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c4 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3b8 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x190 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79c4; op2val:0xb7b8; +op3val:0x7590; valaddr_reg:x8; val_offset:1812*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1812*FLEN/8, x10, x1, x4) + +inst_629: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c4 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3b8 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x190 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79c4; op2val:0xb7b8; +op3val:0x7590; valaddr_reg:x8; val_offset:1815*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1815*FLEN/8, x10, x1, x4) + +inst_630: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x11c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x262 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x013 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x711c; op2val:0xbe62; +op3val:0x7413; valaddr_reg:x8; val_offset:1818*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1818*FLEN/8, x10, x1, x4) + +inst_631: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x11c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x262 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x013 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x711c; op2val:0xbe62; +op3val:0x7413; valaddr_reg:x8; val_offset:1821*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1821*FLEN/8, x10, x1, x4) + +inst_632: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x11c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x262 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x013 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x711c; op2val:0xbe62; +op3val:0x7413; valaddr_reg:x8; val_offset:1824*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1824*FLEN/8, x10, x1, x4) + +inst_633: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x11c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x262 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x013 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x711c; op2val:0xbe62; +op3val:0x7413; valaddr_reg:x8; val_offset:1827*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1827*FLEN/8, x10, x1, x4) + +inst_634: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x11c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x262 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x013 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x711c; op2val:0xbe62; +op3val:0x7413; valaddr_reg:x8; val_offset:1830*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1830*FLEN/8, x10, x1, x4) + +inst_635: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x239 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x06e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2e5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7639; op2val:0xbc6e; +op3val:0x76e5; valaddr_reg:x8; val_offset:1833*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1833*FLEN/8, x10, x1, x4) + +inst_636: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x239 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x06e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2e5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7639; op2val:0xbc6e; +op3val:0x76e5; valaddr_reg:x8; val_offset:1836*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1836*FLEN/8, x10, x1, x4) + +inst_637: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x239 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x06e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2e5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7639; op2val:0xbc6e; +op3val:0x76e5; valaddr_reg:x8; val_offset:1839*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1839*FLEN/8, x10, x1, x4) + +inst_638: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x239 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x06e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2e5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7639; op2val:0xbc6e; +op3val:0x76e5; valaddr_reg:x8; val_offset:1842*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1842*FLEN/8, x10, x1, x4) + +inst_639: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x239 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x06e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2e5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7639; op2val:0xbc6e; +op3val:0x76e5; valaddr_reg:x8; val_offset:1845*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1845*FLEN/8, x10, x1, x4) + +inst_640: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x241 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x015 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x262 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a41; op2val:0xb015; +op3val:0x6e62; valaddr_reg:x8; val_offset:1848*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1848*FLEN/8, x10, x1, x4) + +inst_641: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x241 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x015 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x262 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a41; op2val:0xb015; +op3val:0x6e62; valaddr_reg:x8; val_offset:1851*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1851*FLEN/8, x10, x1, x4) + +inst_642: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x241 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x015 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x262 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a41; op2val:0xb015; +op3val:0x6e62; valaddr_reg:x8; val_offset:1854*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1854*FLEN/8, x10, x1, x4) + +inst_643: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x241 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x015 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x262 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a41; op2val:0xb015; +op3val:0x6e62; valaddr_reg:x8; val_offset:1857*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1857*FLEN/8, x10, x1, x4) + +inst_644: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x241 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x015 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x262 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a41; op2val:0xb015; +op3val:0x6e62; valaddr_reg:x8; val_offset:1860*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1860*FLEN/8, x10, x1, x4) + +inst_645: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x31e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x144 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0b0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x731e; op2val:0xbd44; +op3val:0x74b0; valaddr_reg:x8; val_offset:1863*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1863*FLEN/8, x10, x1, x4) + +inst_646: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x31e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x144 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0b0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x731e; op2val:0xbd44; +op3val:0x74b0; valaddr_reg:x8; val_offset:1866*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1866*FLEN/8, x10, x1, x4) + +inst_647: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x31e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x144 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0b0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x731e; op2val:0xbd44; +op3val:0x74b0; valaddr_reg:x8; val_offset:1869*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1869*FLEN/8, x10, x1, x4) + +inst_648: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x31e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x144 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0b0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x731e; op2val:0xbd44; +op3val:0x74b0; valaddr_reg:x8; val_offset:1872*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1872*FLEN/8, x10, x1, x4) + +inst_649: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x31e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x144 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0b0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x731e; op2val:0xbd44; +op3val:0x74b0; valaddr_reg:x8; val_offset:1875*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1875*FLEN/8, x10, x1, x4) + +inst_650: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1a6 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x03d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71a6; op2val:0xc43d; +op3val:0x79fe; valaddr_reg:x8; val_offset:1878*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1878*FLEN/8, x10, x1, x4) + +inst_651: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1a6 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x03d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1fe and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71a6; op2val:0xc43d; +op3val:0x79fe; valaddr_reg:x8; val_offset:1881*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1881*FLEN/8, x10, x1, x4) + +inst_652: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1a6 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x03d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1fe and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71a6; op2val:0xc43d; +op3val:0x79fe; valaddr_reg:x8; val_offset:1884*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1884*FLEN/8, x10, x1, x4) + +inst_653: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1a6 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x03d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1fe and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71a6; op2val:0xc43d; +op3val:0x79fe; valaddr_reg:x8; val_offset:1887*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1887*FLEN/8, x10, x1, x4) + +inst_654: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1a6 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x03d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1fe and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71a6; op2val:0xc43d; +op3val:0x79fe; valaddr_reg:x8; val_offset:1890*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1890*FLEN/8, x10, x1, x4) + +inst_655: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2f9 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x378 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x282 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ef9; op2val:0xb778; +op3val:0x6a82; valaddr_reg:x8; val_offset:1893*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1893*FLEN/8, x10, x1, x4) + +inst_656: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2f9 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x378 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x282 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ef9; op2val:0xb778; +op3val:0x6a82; valaddr_reg:x8; val_offset:1896*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1896*FLEN/8, x10, x1, x4) + +inst_657: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2f9 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x378 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x282 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ef9; op2val:0xb778; +op3val:0x6a82; valaddr_reg:x8; val_offset:1899*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1899*FLEN/8, x10, x1, x4) + +inst_658: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2f9 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x378 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x282 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ef9; op2val:0xb778; +op3val:0x6a82; valaddr_reg:x8; val_offset:1902*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1902*FLEN/8, x10, x1, x4) + +inst_659: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2f9 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x378 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x282 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ef9; op2val:0xb778; +op3val:0x6a82; valaddr_reg:x8; val_offset:1905*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1905*FLEN/8, x10, x1, x4) + +inst_660: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x071 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x14c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1e2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7871; op2val:0xbd4c; +op3val:0x79e2; valaddr_reg:x8; val_offset:1908*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1908*FLEN/8, x10, x1, x4) + +inst_661: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x071 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x14c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1e2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7871; op2val:0xbd4c; +op3val:0x79e2; valaddr_reg:x8; val_offset:1911*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1911*FLEN/8, x10, x1, x4) + +inst_662: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x071 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x14c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1e2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7871; op2val:0xbd4c; +op3val:0x79e2; valaddr_reg:x8; val_offset:1914*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1914*FLEN/8, x10, x1, x4) + +inst_663: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x071 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x14c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1e2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7871; op2val:0xbd4c; +op3val:0x79e2; valaddr_reg:x8; val_offset:1917*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1917*FLEN/8, x10, x1, x4) + +inst_664: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x071 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x14c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1e2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7871; op2val:0xbd4c; +op3val:0x79e2; valaddr_reg:x8; val_offset:1920*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1920*FLEN/8, x10, x1, x4) + +inst_665: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x298 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x16c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x079 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a98; op2val:0xb96c; +op3val:0x7879; valaddr_reg:x8; val_offset:1923*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1923*FLEN/8, x10, x1, x4) + +inst_666: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x298 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x16c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x079 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a98; op2val:0xb96c; +op3val:0x7879; valaddr_reg:x8; val_offset:1926*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1926*FLEN/8, x10, x1, x4) + +inst_667: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x298 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x16c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x079 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a98; op2val:0xb96c; +op3val:0x7879; valaddr_reg:x8; val_offset:1929*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1929*FLEN/8, x10, x1, x4) + +inst_668: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x298 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x16c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x079 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a98; op2val:0xb96c; +op3val:0x7879; valaddr_reg:x8; val_offset:1932*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1932*FLEN/8, x10, x1, x4) + +inst_669: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x298 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x16c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x079 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a98; op2val:0xb96c; +op3val:0x7879; valaddr_reg:x8; val_offset:1935*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1935*FLEN/8, x10, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_7) + +inst_670: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x139 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x165 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x30d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7539; op2val:0xc165; +op3val:0x7b0d; valaddr_reg:x8; val_offset:1938*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1938*FLEN/8, x10, x1, x4) + +inst_671: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x139 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x165 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x30d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7539; op2val:0xc165; +op3val:0x7b0d; valaddr_reg:x8; val_offset:1941*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1941*FLEN/8, x10, x1, x4) + +inst_672: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x139 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x165 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x30d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7539; op2val:0xc165; +op3val:0x7b0d; valaddr_reg:x8; val_offset:1944*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1944*FLEN/8, x10, x1, x4) + +inst_673: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x139 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x165 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x30d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7539; op2val:0xc165; +op3val:0x7b0d; valaddr_reg:x8; val_offset:1947*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1947*FLEN/8, x10, x1, x4) + +inst_674: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x139 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x165 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x30d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7539; op2val:0xc165; +op3val:0x7b0d; valaddr_reg:x8; val_offset:1950*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1950*FLEN/8, x10, x1, x4) + +inst_675: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1e2 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x134 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3a8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79e2; op2val:0xb934; +op3val:0x77a8; valaddr_reg:x8; val_offset:1953*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1953*FLEN/8, x10, x1, x4) + +inst_676: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1e2 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x134 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3a8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79e2; op2val:0xb934; +op3val:0x77a8; valaddr_reg:x8; val_offset:1956*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1956*FLEN/8, x10, x1, x4) + +inst_677: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1e2 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x134 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3a8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79e2; op2val:0xb934; +op3val:0x77a8; valaddr_reg:x8; val_offset:1959*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1959*FLEN/8, x10, x1, x4) + +inst_678: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1e2 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x134 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3a8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79e2; op2val:0xb934; +op3val:0x77a8; valaddr_reg:x8; val_offset:1962*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1962*FLEN/8, x10, x1, x4) + +inst_679: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1e2 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x134 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3a8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79e2; op2val:0xb934; +op3val:0x77a8; valaddr_reg:x8; val_offset:1965*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1965*FLEN/8, x10, x1, x4) + +inst_680: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x080 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2a6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x37c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7880; op2val:0xbea6; +op3val:0x7b7c; valaddr_reg:x8; val_offset:1968*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1968*FLEN/8, x10, x1, x4) + +inst_681: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x080 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2a6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x37c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7880; op2val:0xbea6; +op3val:0x7b7c; valaddr_reg:x8; val_offset:1971*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1971*FLEN/8, x10, x1, x4) + +inst_682: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x080 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2a6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x37c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7880; op2val:0xbea6; +op3val:0x7b7c; valaddr_reg:x8; val_offset:1974*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1974*FLEN/8, x10, x1, x4) + +inst_683: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x080 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2a6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x37c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7880; op2val:0xbea6; +op3val:0x7b7c; valaddr_reg:x8; val_offset:1977*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1977*FLEN/8, x10, x1, x4) + +inst_684: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x080 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2a6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x37c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7880; op2val:0xbea6; +op3val:0x7b7c; valaddr_reg:x8; val_offset:1980*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1980*FLEN/8, x10, x1, x4) + +inst_685: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f9 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x378 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x372 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bf9; op2val:0xbb78; +op3val:0x7b72; valaddr_reg:x8; val_offset:1983*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1983*FLEN/8, x10, x1, x4) + +inst_686: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f9 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x378 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x372 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bf9; op2val:0xbb78; +op3val:0x7b72; valaddr_reg:x8; val_offset:1986*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1986*FLEN/8, x10, x1, x4) + +inst_687: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f9 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x378 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x372 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bf9; op2val:0xbb78; +op3val:0x7b72; valaddr_reg:x8; val_offset:1989*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1989*FLEN/8, x10, x1, x4) + +inst_688: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f9 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x378 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x372 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bf9; op2val:0xbb78; +op3val:0x7b72; valaddr_reg:x8; val_offset:1992*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1992*FLEN/8, x10, x1, x4) + +inst_689: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f9 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x378 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x372 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bf9; op2val:0xbb78; +op3val:0x7b72; valaddr_reg:x8; val_offset:1995*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1995*FLEN/8, x10, x1, x4) + +inst_690: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x03e and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ed and fs3 == 0 and fe3 == 0x1d and fm3 == 0x13a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x703e; op2val:0xc0ed; +op3val:0x753a; valaddr_reg:x8; val_offset:1998*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1998*FLEN/8, x10, x1, x4) + +inst_691: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x03e and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ed and fs3 == 0 and fe3 == 0x1d and fm3 == 0x13a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x703e; op2val:0xc0ed; +op3val:0x753a; valaddr_reg:x8; val_offset:2001*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2001*FLEN/8, x10, x1, x4) + +inst_692: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x03e and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ed and fs3 == 0 and fe3 == 0x1d and fm3 == 0x13a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x703e; op2val:0xc0ed; +op3val:0x753a; valaddr_reg:x8; val_offset:2004*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2004*FLEN/8, x10, x1, x4) + +inst_693: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x03e and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ed and fs3 == 0 and fe3 == 0x1d and fm3 == 0x13a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x703e; op2val:0xc0ed; +op3val:0x753a; valaddr_reg:x8; val_offset:2007*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2007*FLEN/8, x10, x1, x4) + +inst_694: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x03e and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ed and fs3 == 0 and fe3 == 0x1d and fm3 == 0x13a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x703e; op2val:0xc0ed; +op3val:0x753a; valaddr_reg:x8; val_offset:2010*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2010*FLEN/8, x10, x1, x4) + +inst_695: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x285 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2a1 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x167 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7685; op2val:0xb6a1; +op3val:0x7167; valaddr_reg:x8; val_offset:2013*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2013*FLEN/8, x10, x1, x4) + +inst_696: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x285 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2a1 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x167 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7685; op2val:0xb6a1; +op3val:0x7167; valaddr_reg:x8; val_offset:2016*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2016*FLEN/8, x10, x1, x4) + +inst_697: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x285 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2a1 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x167 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7685; op2val:0xb6a1; +op3val:0x7167; valaddr_reg:x8; val_offset:2019*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2019*FLEN/8, x10, x1, x4) + +inst_698: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x285 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2a1 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x167 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7685; op2val:0xb6a1; +op3val:0x7167; valaddr_reg:x8; val_offset:2022*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2022*FLEN/8, x10, x1, x4) + +inst_699: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x285 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2a1 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x167 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7685; op2val:0xb6a1; +op3val:0x7167; valaddr_reg:x8; val_offset:2025*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2025*FLEN/8, x10, x1, x4) + +inst_700: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x217 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x11c and fs3 == 0 and fe3 == 0x1a and fm3 == 0x3c9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a17; op2val:0xad1c; +op3val:0x6bc9; valaddr_reg:x8; val_offset:2028*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2028*FLEN/8, x10, x1, x4) + +inst_701: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x217 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x11c and fs3 == 0 and fe3 == 0x1a and fm3 == 0x3c9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a17; op2val:0xad1c; +op3val:0x6bc9; valaddr_reg:x8; val_offset:2031*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2031*FLEN/8, x10, x1, x4) + +inst_702: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x217 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x11c and fs3 == 0 and fe3 == 0x1a and fm3 == 0x3c9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a17; op2val:0xad1c; +op3val:0x6bc9; valaddr_reg:x8; val_offset:2034*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2034*FLEN/8, x10, x1, x4) + +inst_703: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x217 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x11c and fs3 == 0 and fe3 == 0x1a and fm3 == 0x3c9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a17; op2val:0xad1c; +op3val:0x6bc9; valaddr_reg:x8; val_offset:2037*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2037*FLEN/8, x10, x1, x4) + +inst_704: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x217 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x11c and fs3 == 0 and fe3 == 0x1a and fm3 == 0x3c9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a17; op2val:0xad1c; +op3val:0x6bc9; valaddr_reg:x8; val_offset:2040*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2040*FLEN/8, x10, x1, x4) + +inst_705: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x318 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x147 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0ae and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b18; op2val:0xb947; +op3val:0x78ae; valaddr_reg:x8; val_offset:2043*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2043*FLEN/8, x10, x1, x4) + +inst_706: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x318 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x147 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0ae and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b18; op2val:0xb947; +op3val:0x78ae; valaddr_reg:x8; val_offset:2046*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2046*FLEN/8, x10, x1, x4) + +inst_707: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x318 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x147 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0ae and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b18; op2val:0xb947; +op3val:0x78ae; valaddr_reg:x8; val_offset:2049*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2049*FLEN/8, x10, x1, x4) + +inst_708: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x318 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x147 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0ae and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b18; op2val:0xb947; +op3val:0x78ae; valaddr_reg:x8; val_offset:2052*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2052*FLEN/8, x10, x1, x4) + +inst_709: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x318 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x147 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0ae and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b18; op2val:0xb947; +op3val:0x78ae; valaddr_reg:x8; val_offset:2055*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2055*FLEN/8, x10, x1, x4) + +inst_710: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x168 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2a2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e8; op2val:0xb968; +op3val:0x76a2; valaddr_reg:x8; val_offset:2058*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2058*FLEN/8, x10, x1, x4) + +inst_711: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x168 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2a2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e8; op2val:0xb968; +op3val:0x76a2; valaddr_reg:x8; val_offset:2061*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2061*FLEN/8, x10, x1, x4) + +inst_712: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x168 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2a2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e8; op2val:0xb968; +op3val:0x76a2; valaddr_reg:x8; val_offset:2064*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2064*FLEN/8, x10, x1, x4) + +inst_713: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x168 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2a2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e8; op2val:0xb968; +op3val:0x76a2; valaddr_reg:x8; val_offset:2067*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2067*FLEN/8, x10, x1, x4) + +inst_714: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x168 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2a2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e8; op2val:0xb968; +op3val:0x76a2; valaddr_reg:x8; val_offset:2070*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2070*FLEN/8, x10, x1, x4) + +inst_715: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0f0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x09f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b7d; op2val:0xb8f0; +op3val:0x789f; valaddr_reg:x8; val_offset:2073*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2073*FLEN/8, x10, x1, x4) + +inst_716: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0f0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x09f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b7d; op2val:0xb8f0; +op3val:0x789f; valaddr_reg:x8; val_offset:2076*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2076*FLEN/8, x10, x1, x4) + +inst_717: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0f0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x09f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b7d; op2val:0xb8f0; +op3val:0x789f; valaddr_reg:x8; val_offset:2079*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2079*FLEN/8, x10, x1, x4) + +inst_718: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0f0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x09f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b7d; op2val:0xb8f0; +op3val:0x789f; valaddr_reg:x8; val_offset:2082*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2082*FLEN/8, x10, x1, x4) + +inst_719: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0f0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x09f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b7d; op2val:0xb8f0; +op3val:0x789f; valaddr_reg:x8; val_offset:2085*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2085*FLEN/8, x10, x1, x4) + +inst_720: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x01d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x360 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b2b; op2val:0xbc1d; +op3val:0x7b60; valaddr_reg:x8; val_offset:2088*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2088*FLEN/8, x10, x1, x4) + +inst_721: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x01d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x360 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b2b; op2val:0xbc1d; +op3val:0x7b60; valaddr_reg:x8; val_offset:2091*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2091*FLEN/8, x10, x1, x4) + +inst_722: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x01d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x360 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b2b; op2val:0xbc1d; +op3val:0x7b60; valaddr_reg:x8; val_offset:2094*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2094*FLEN/8, x10, x1, x4) + +inst_723: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x01d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x360 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b2b; op2val:0xbc1d; +op3val:0x7b60; valaddr_reg:x8; val_offset:2097*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2097*FLEN/8, x10, x1, x4) + +inst_724: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x01d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x360 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b2b; op2val:0xbc1d; +op3val:0x7b60; valaddr_reg:x8; val_offset:2100*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2100*FLEN/8, x10, x1, x4) + +inst_725: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x188 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1ae and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3dc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7988; op2val:0xbdae; +op3val:0x7bdc; valaddr_reg:x8; val_offset:2103*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2103*FLEN/8, x10, x1, x4) + +inst_726: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x188 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1ae and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3dc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7988; op2val:0xbdae; +op3val:0x7bdc; valaddr_reg:x8; val_offset:2106*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2106*FLEN/8, x10, x1, x4) + +inst_727: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x188 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1ae and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3dc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7988; op2val:0xbdae; +op3val:0x7bdc; valaddr_reg:x8; val_offset:2109*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2109*FLEN/8, x10, x1, x4) + +inst_728: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x188 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1ae and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3dc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7988; op2val:0xbdae; +op3val:0x7bdc; valaddr_reg:x8; val_offset:2112*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2112*FLEN/8, x10, x1, x4) + +inst_729: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x188 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1ae and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3dc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7988; op2val:0xbdae; +op3val:0x7bdc; valaddr_reg:x8; val_offset:2115*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2115*FLEN/8, x10, x1, x4) + +inst_730: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1fd and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1dc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77d4; op2val:0xb9fd; +op3val:0x75dc; valaddr_reg:x8; val_offset:2118*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2118*FLEN/8, x10, x1, x4) + +inst_731: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1fd and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1dc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77d4; op2val:0xb9fd; +op3val:0x75dc; valaddr_reg:x8; val_offset:2121*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2121*FLEN/8, x10, x1, x4) + +inst_732: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1fd and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1dc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77d4; op2val:0xb9fd; +op3val:0x75dc; valaddr_reg:x8; val_offset:2124*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2124*FLEN/8, x10, x1, x4) + +inst_733: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1fd and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1dc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77d4; op2val:0xb9fd; +op3val:0x75dc; valaddr_reg:x8; val_offset:2127*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2127*FLEN/8, x10, x1, x4) + +inst_734: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1fd and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1dc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77d4; op2val:0xb9fd; +op3val:0x75dc; valaddr_reg:x8; val_offset:2130*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2130*FLEN/8, x10, x1, x4) + +inst_735: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2bf and fs2 == 1 and fe2 == 0x0e and fm2 == 0x101 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x038 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7abf; op2val:0xb901; +op3val:0x7838; valaddr_reg:x8; val_offset:2133*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2133*FLEN/8, x10, x1, x4) + +inst_736: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2bf and fs2 == 1 and fe2 == 0x0e and fm2 == 0x101 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x038 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7abf; op2val:0xb901; +op3val:0x7838; valaddr_reg:x8; val_offset:2136*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2136*FLEN/8, x10, x1, x4) + +inst_737: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2bf and fs2 == 1 and fe2 == 0x0e and fm2 == 0x101 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x038 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7abf; op2val:0xb901; +op3val:0x7838; valaddr_reg:x8; val_offset:2139*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2139*FLEN/8, x10, x1, x4) + +inst_738: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2bf and fs2 == 1 and fe2 == 0x0e and fm2 == 0x101 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x038 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7abf; op2val:0xb901; +op3val:0x7838; valaddr_reg:x8; val_offset:2142*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2142*FLEN/8, x10, x1, x4) + +inst_739: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2bf and fs2 == 1 and fe2 == 0x0e and fm2 == 0x101 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x038 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7abf; op2val:0xb901; +op3val:0x7838; valaddr_reg:x8; val_offset:2145*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2145*FLEN/8, x10, x1, x4) + +inst_740: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x067 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x170 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74f0; op2val:0xc067; +op3val:0x7970; valaddr_reg:x8; val_offset:2148*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2148*FLEN/8, x10, x1, x4) + +inst_741: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x067 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x170 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74f0; op2val:0xc067; +op3val:0x7970; valaddr_reg:x8; val_offset:2151*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2151*FLEN/8, x10, x1, x4) + +inst_742: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x067 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x170 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74f0; op2val:0xc067; +op3val:0x7970; valaddr_reg:x8; val_offset:2154*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2154*FLEN/8, x10, x1, x4) + +inst_743: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x067 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x170 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74f0; op2val:0xc067; +op3val:0x7970; valaddr_reg:x8; val_offset:2157*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2157*FLEN/8, x10, x1, x4) + +inst_744: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x067 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x170 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74f0; op2val:0xc067; +op3val:0x7970; valaddr_reg:x8; val_offset:2160*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2160*FLEN/8, x10, x1, x4) + +inst_745: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x39c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x04c and fs3 == 0 and fe3 == 0x1c and fm3 == 0x017 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x779c; op2val:0xb44c; +op3val:0x7017; valaddr_reg:x8; val_offset:2163*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2163*FLEN/8, x10, x1, x4) + +inst_746: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x39c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x04c and fs3 == 0 and fe3 == 0x1c and fm3 == 0x017 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x779c; op2val:0xb44c; +op3val:0x7017; valaddr_reg:x8; val_offset:2166*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2166*FLEN/8, x10, x1, x4) + +inst_747: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x39c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x04c and fs3 == 0 and fe3 == 0x1c and fm3 == 0x017 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x779c; op2val:0xb44c; +op3val:0x7017; valaddr_reg:x8; val_offset:2169*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2169*FLEN/8, x10, x1, x4) + +inst_748: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x39c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x04c and fs3 == 0 and fe3 == 0x1c and fm3 == 0x017 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x779c; op2val:0xb44c; +op3val:0x7017; valaddr_reg:x8; val_offset:2172*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2172*FLEN/8, x10, x1, x4) + +inst_749: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x39c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x04c and fs3 == 0 and fe3 == 0x1c and fm3 == 0x017 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x779c; op2val:0xb44c; +op3val:0x7017; valaddr_reg:x8; val_offset:2175*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2175*FLEN/8, x10, x1, x4) + +inst_750: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0c6 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ab3; op2val:0xb8c6; +op3val:0x77fe; valaddr_reg:x8; val_offset:2178*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2178*FLEN/8, x10, x1, x4) + +inst_751: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0c6 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3fe and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ab3; op2val:0xb8c6; +op3val:0x77fe; valaddr_reg:x8; val_offset:2181*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2181*FLEN/8, x10, x1, x4) + +inst_752: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0c6 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3fe and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ab3; op2val:0xb8c6; +op3val:0x77fe; valaddr_reg:x8; val_offset:2184*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2184*FLEN/8, x10, x1, x4) + +inst_753: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0c6 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3fe and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ab3; op2val:0xb8c6; +op3val:0x77fe; valaddr_reg:x8; val_offset:2187*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2187*FLEN/8, x10, x1, x4) + +inst_754: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0c6 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3fe and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ab3; op2val:0xb8c6; +op3val:0x77fe; valaddr_reg:x8; val_offset:2190*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2190*FLEN/8, x10, x1, x4) + +inst_755: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x064 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x044 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bc4; op2val:0xb864; +op3val:0x7844; valaddr_reg:x8; val_offset:2193*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2193*FLEN/8, x10, x1, x4) + +inst_756: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x064 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x044 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bc4; op2val:0xb864; +op3val:0x7844; valaddr_reg:x8; val_offset:2196*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2196*FLEN/8, x10, x1, x4) + +inst_757: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x064 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x044 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bc4; op2val:0xb864; +op3val:0x7844; valaddr_reg:x8; val_offset:2199*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2199*FLEN/8, x10, x1, x4) + +inst_758: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x064 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x044 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bc4; op2val:0xb864; +op3val:0x7844; valaddr_reg:x8; val_offset:2202*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2202*FLEN/8, x10, x1, x4) + +inst_759: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x064 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x044 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bc4; op2val:0xb864; +op3val:0x7844; valaddr_reg:x8; val_offset:2205*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2205*FLEN/8, x10, x1, x4) + +inst_760: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37d and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0f0 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x09f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b7d; op2val:0xb4f0; +op3val:0x749f; valaddr_reg:x8; val_offset:2208*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2208*FLEN/8, x10, x1, x4) + +inst_761: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37d and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0f0 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x09f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b7d; op2val:0xb4f0; +op3val:0x749f; valaddr_reg:x8; val_offset:2211*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2211*FLEN/8, x10, x1, x4) + +inst_762: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37d and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0f0 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x09f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b7d; op2val:0xb4f0; +op3val:0x749f; valaddr_reg:x8; val_offset:2214*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2214*FLEN/8, x10, x1, x4) + +inst_763: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37d and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0f0 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x09f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b7d; op2val:0xb4f0; +op3val:0x749f; valaddr_reg:x8; val_offset:2217*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2217*FLEN/8, x10, x1, x4) + +inst_764: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37d and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0f0 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x09f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b7d; op2val:0xb4f0; +op3val:0x749f; valaddr_reg:x8; val_offset:2220*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2220*FLEN/8, x10, x1, x4) + +inst_765: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2f4 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0d7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x035 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72f4; op2val:0xc0d7; +op3val:0x7835; valaddr_reg:x8; val_offset:2223*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2223*FLEN/8, x10, x1, x4) + +inst_766: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2f4 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0d7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x035 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72f4; op2val:0xc0d7; +op3val:0x7835; valaddr_reg:x8; val_offset:2226*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2226*FLEN/8, x10, x1, x4) + +inst_767: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2f4 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0d7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x035 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72f4; op2val:0xc0d7; +op3val:0x7835; valaddr_reg:x8; val_offset:2229*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2229*FLEN/8, x10, x1, x4) + +inst_768: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2f4 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0d7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x035 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72f4; op2val:0xc0d7; +op3val:0x7835; valaddr_reg:x8; val_offset:2232*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2232*FLEN/8, x10, x1, x4) + +inst_769: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2f4 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0d7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x035 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72f4; op2val:0xc0d7; +op3val:0x7835; valaddr_reg:x8; val_offset:2235*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2235*FLEN/8, x10, x1, x4) + +inst_770: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x221 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x04d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x298 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a21; op2val:0xbc4d; +op3val:0x7a98; valaddr_reg:x8; val_offset:2238*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2238*FLEN/8, x10, x1, x4) + +inst_771: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x221 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x04d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x298 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a21; op2val:0xbc4d; +op3val:0x7a98; valaddr_reg:x8; val_offset:2241*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2241*FLEN/8, x10, x1, x4) + +inst_772: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x221 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x04d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x298 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a21; op2val:0xbc4d; +op3val:0x7a98; valaddr_reg:x8; val_offset:2244*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2244*FLEN/8, x10, x1, x4) + +inst_773: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x221 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x04d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x298 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a21; op2val:0xbc4d; +op3val:0x7a98; valaddr_reg:x8; val_offset:2247*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2247*FLEN/8, x10, x1, x4) + +inst_774: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x221 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x04d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x298 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a21; op2val:0xbc4d; +op3val:0x7a98; valaddr_reg:x8; val_offset:2250*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2250*FLEN/8, x10, x1, x4) + +inst_775: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12d and fs2 == 1 and fe2 == 0x0c and fm2 == 0x224 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x3f3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x792d; op2val:0xb224; +op3val:0x6ff3; valaddr_reg:x8; val_offset:2253*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2253*FLEN/8, x10, x1, x4) + +inst_776: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12d and fs2 == 1 and fe2 == 0x0c and fm2 == 0x224 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x3f3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x792d; op2val:0xb224; +op3val:0x6ff3; valaddr_reg:x8; val_offset:2256*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2256*FLEN/8, x10, x1, x4) + +inst_777: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12d and fs2 == 1 and fe2 == 0x0c and fm2 == 0x224 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x3f3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x792d; op2val:0xb224; +op3val:0x6ff3; valaddr_reg:x8; val_offset:2259*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2259*FLEN/8, x10, x1, x4) + +inst_778: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12d and fs2 == 1 and fe2 == 0x0c and fm2 == 0x224 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x3f3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x792d; op2val:0xb224; +op3val:0x6ff3; valaddr_reg:x8; val_offset:2262*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2262*FLEN/8, x10, x1, x4) + +inst_779: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12d and fs2 == 1 and fe2 == 0x0c and fm2 == 0x224 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x3f3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x792d; op2val:0xb224; +op3val:0x6ff3; valaddr_reg:x8; val_offset:2265*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2265*FLEN/8, x10, x1, x4) + +inst_780: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x24d and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1ad and fs3 == 0 and fe3 == 0x1a and fm3 == 0x079 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x764d; op2val:0xadad; +op3val:0x6879; valaddr_reg:x8; val_offset:2268*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2268*FLEN/8, x10, x1, x4) + +inst_781: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x24d and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1ad and fs3 == 0 and fe3 == 0x1a and fm3 == 0x079 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x764d; op2val:0xadad; +op3val:0x6879; valaddr_reg:x8; val_offset:2271*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2271*FLEN/8, x10, x1, x4) + +inst_782: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x24d and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1ad and fs3 == 0 and fe3 == 0x1a and fm3 == 0x079 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x764d; op2val:0xadad; +op3val:0x6879; valaddr_reg:x8; val_offset:2274*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2274*FLEN/8, x10, x1, x4) + +inst_783: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x24d and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1ad and fs3 == 0 and fe3 == 0x1a and fm3 == 0x079 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x764d; op2val:0xadad; +op3val:0x6879; valaddr_reg:x8; val_offset:2277*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2277*FLEN/8, x10, x1, x4) + +inst_784: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x24d and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1ad and fs3 == 0 and fe3 == 0x1a and fm3 == 0x079 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x764d; op2val:0xadad; +op3val:0x6879; valaddr_reg:x8; val_offset:2280*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2280*FLEN/8, x10, x1, x4) + +inst_785: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1f0 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x116 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x38d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75f0; op2val:0xc116; +op3val:0x7b8d; valaddr_reg:x8; val_offset:2283*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2283*FLEN/8, x10, x1, x4) + +inst_786: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1f0 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x116 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x38d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75f0; op2val:0xc116; +op3val:0x7b8d; valaddr_reg:x8; val_offset:2286*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2286*FLEN/8, x10, x1, x4) + +inst_787: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1f0 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x116 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x38d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75f0; op2val:0xc116; +op3val:0x7b8d; valaddr_reg:x8; val_offset:2289*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2289*FLEN/8, x10, x1, x4) + +inst_788: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1f0 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x116 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x38d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75f0; op2val:0xc116; +op3val:0x7b8d; valaddr_reg:x8; val_offset:2292*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2292*FLEN/8, x10, x1, x4) + +inst_789: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1f0 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x116 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x38d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75f0; op2val:0xc116; +op3val:0x7b8d; valaddr_reg:x8; val_offset:2295*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2295*FLEN/8, x10, x1, x4) + +inst_790: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x18c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x007 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x196 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x758c; op2val:0xc007; +op3val:0x7996; valaddr_reg:x8; val_offset:2298*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2298*FLEN/8, x10, x1, x4) + +inst_791: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x18c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x007 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x196 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x758c; op2val:0xc007; +op3val:0x7996; valaddr_reg:x8; val_offset:2301*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2301*FLEN/8, x10, x1, x4) + +inst_792: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x18c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x007 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x196 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x758c; op2val:0xc007; +op3val:0x7996; valaddr_reg:x8; val_offset:2304*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2304*FLEN/8, x10, x1, x4) + +inst_793: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x18c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x007 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x196 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x758c; op2val:0xc007; +op3val:0x7996; valaddr_reg:x8; val_offset:2307*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2307*FLEN/8, x10, x1, x4) + +inst_794: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x18c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x007 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x196 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x758c; op2val:0xc007; +op3val:0x7996; valaddr_reg:x8; val_offset:2310*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2310*FLEN/8, x10, x1, x4) + +inst_795: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0f8 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x360 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x094 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78f8; op2val:0xb360; +op3val:0x7094; valaddr_reg:x8; val_offset:2313*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2313*FLEN/8, x10, x1, x4) + +inst_796: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0f8 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x360 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x094 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78f8; op2val:0xb360; +op3val:0x7094; valaddr_reg:x8; val_offset:2316*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2316*FLEN/8, x10, x1, x4) + +inst_797: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0f8 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x360 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x094 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78f8; op2val:0xb360; +op3val:0x7094; valaddr_reg:x8; val_offset:2319*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2319*FLEN/8, x10, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_8) + +inst_798: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0f8 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x360 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x094 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78f8; op2val:0xb360; +op3val:0x7094; valaddr_reg:x8; val_offset:2322*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2322*FLEN/8, x10, x1, x4) + +inst_799: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0f8 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x360 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x094 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78f8; op2val:0xb360; +op3val:0x7094; valaddr_reg:x8; val_offset:2325*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2325*FLEN/8, x10, x1, x4) + +inst_800: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x181 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x369 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x119 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7981; op2val:0xaf69; +op3val:0x6d19; valaddr_reg:x8; val_offset:2328*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2328*FLEN/8, x10, x1, x4) + +inst_801: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x181 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x369 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x119 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7981; op2val:0xaf69; +op3val:0x6d19; valaddr_reg:x8; val_offset:2331*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2331*FLEN/8, x10, x1, x4) + +inst_802: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x181 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x369 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x119 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7981; op2val:0xaf69; +op3val:0x6d19; valaddr_reg:x8; val_offset:2334*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2334*FLEN/8, x10, x1, x4) + +inst_803: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x181 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x369 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x119 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7981; op2val:0xaf69; +op3val:0x6d19; valaddr_reg:x8; val_offset:2337*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2337*FLEN/8, x10, x1, x4) + +inst_804: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x181 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x369 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x119 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7981; op2val:0xaf69; +op3val:0x6d19; valaddr_reg:x8; val_offset:2340*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2340*FLEN/8, x10, x1, x4) + +inst_805: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1e8 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x247 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71e8; op2val:0xc247; +op3val:0x78a3; valaddr_reg:x8; val_offset:2343*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2343*FLEN/8, x10, x1, x4) + +inst_806: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1e8 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x247 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71e8; op2val:0xc247; +op3val:0x78a3; valaddr_reg:x8; val_offset:2346*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2346*FLEN/8, x10, x1, x4) + +inst_807: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1e8 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x247 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71e8; op2val:0xc247; +op3val:0x78a3; valaddr_reg:x8; val_offset:2349*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2349*FLEN/8, x10, x1, x4) + +inst_808: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1e8 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x247 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71e8; op2val:0xc247; +op3val:0x78a3; valaddr_reg:x8; val_offset:2352*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2352*FLEN/8, x10, x1, x4) + +inst_809: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1e8 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x247 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71e8; op2val:0xc247; +op3val:0x78a3; valaddr_reg:x8; val_offset:2355*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2355*FLEN/8, x10, x1, x4) + +inst_810: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x013 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x391 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7013; op2val:0xc791; +op3val:0x7bb6; valaddr_reg:x8; val_offset:2358*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2358*FLEN/8, x10, x1, x4) + +inst_811: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x013 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x391 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7013; op2val:0xc791; +op3val:0x7bb6; valaddr_reg:x8; val_offset:2361*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2361*FLEN/8, x10, x1, x4) + +inst_812: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x013 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x391 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7013; op2val:0xc791; +op3val:0x7bb6; valaddr_reg:x8; val_offset:2364*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2364*FLEN/8, x10, x1, x4) + +inst_813: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x013 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x391 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7013; op2val:0xc791; +op3val:0x7bb6; valaddr_reg:x8; val_offset:2367*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2367*FLEN/8, x10, x1, x4) + +inst_814: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x013 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x391 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7013; op2val:0xc791; +op3val:0x7bb6; valaddr_reg:x8; val_offset:2370*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2370*FLEN/8, x10, x1, x4) + +inst_815: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2ce and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1ec and fs3 == 0 and fe3 == 0x1e and fm3 == 0x10a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76ce; op2val:0xbdec; +op3val:0x790a; valaddr_reg:x8; val_offset:2373*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2373*FLEN/8, x10, x1, x4) + +inst_816: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2ce and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1ec and fs3 == 0 and fe3 == 0x1e and fm3 == 0x10a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76ce; op2val:0xbdec; +op3val:0x790a; valaddr_reg:x8; val_offset:2376*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2376*FLEN/8, x10, x1, x4) + +inst_817: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2ce and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1ec and fs3 == 0 and fe3 == 0x1e and fm3 == 0x10a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76ce; op2val:0xbdec; +op3val:0x790a; valaddr_reg:x8; val_offset:2379*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2379*FLEN/8, x10, x1, x4) + +inst_818: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2ce and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1ec and fs3 == 0 and fe3 == 0x1e and fm3 == 0x10a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76ce; op2val:0xbdec; +op3val:0x790a; valaddr_reg:x8; val_offset:2382*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2382*FLEN/8, x10, x1, x4) + +inst_819: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2ce and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1ec and fs3 == 0 and fe3 == 0x1e and fm3 == 0x10a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76ce; op2val:0xbdec; +op3val:0x790a; valaddr_reg:x8; val_offset:2385*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2385*FLEN/8, x10, x1, x4) + +inst_820: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b7 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x32a and fs3 == 0 and fe3 == 0x1b and fm3 == 0x2e9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bb7; op2val:0xaf2a; +op3val:0x6ee9; valaddr_reg:x8; val_offset:2388*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2388*FLEN/8, x10, x1, x4) + +inst_821: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b7 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x32a and fs3 == 0 and fe3 == 0x1b and fm3 == 0x2e9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bb7; op2val:0xaf2a; +op3val:0x6ee9; valaddr_reg:x8; val_offset:2391*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2391*FLEN/8, x10, x1, x4) + +inst_822: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b7 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x32a and fs3 == 0 and fe3 == 0x1b and fm3 == 0x2e9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bb7; op2val:0xaf2a; +op3val:0x6ee9; valaddr_reg:x8; val_offset:2394*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2394*FLEN/8, x10, x1, x4) + +inst_823: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b7 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x32a and fs3 == 0 and fe3 == 0x1b and fm3 == 0x2e9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bb7; op2val:0xaf2a; +op3val:0x6ee9; valaddr_reg:x8; val_offset:2397*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2397*FLEN/8, x10, x1, x4) + +inst_824: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b7 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x32a and fs3 == 0 and fe3 == 0x1b and fm3 == 0x2e9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bb7; op2val:0xaf2a; +op3val:0x6ee9; valaddr_reg:x8; val_offset:2400*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2400*FLEN/8, x10, x1, x4) + +inst_825: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3fd and fs2 == 1 and fe2 == 0x0a and fm2 == 0x113 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x111 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bfd; op2val:0xa913; +op3val:0x6911; valaddr_reg:x8; val_offset:2403*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2403*FLEN/8, x10, x1, x4) + +inst_826: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3fd and fs2 == 1 and fe2 == 0x0a and fm2 == 0x113 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x111 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bfd; op2val:0xa913; +op3val:0x6911; valaddr_reg:x8; val_offset:2406*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2406*FLEN/8, x10, x1, x4) + +inst_827: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3fd and fs2 == 1 and fe2 == 0x0a and fm2 == 0x113 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x111 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bfd; op2val:0xa913; +op3val:0x6911; valaddr_reg:x8; val_offset:2409*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2409*FLEN/8, x10, x1, x4) + +inst_828: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3fd and fs2 == 1 and fe2 == 0x0a and fm2 == 0x113 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x111 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bfd; op2val:0xa913; +op3val:0x6911; valaddr_reg:x8; val_offset:2412*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2412*FLEN/8, x10, x1, x4) + +inst_829: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3fd and fs2 == 1 and fe2 == 0x0a and fm2 == 0x113 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x111 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bfd; op2val:0xa913; +op3val:0x6911; valaddr_reg:x8; val_offset:2415*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2415*FLEN/8, x10, x1, x4) + +inst_830: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ce and fs2 == 1 and fe2 == 0x0f and fm2 == 0x05d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x13e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78ce; op2val:0xbc5d; +op3val:0x793e; valaddr_reg:x8; val_offset:2418*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2418*FLEN/8, x10, x1, x4) + +inst_831: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ce and fs2 == 1 and fe2 == 0x0f and fm2 == 0x05d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x13e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78ce; op2val:0xbc5d; +op3val:0x793e; valaddr_reg:x8; val_offset:2421*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2421*FLEN/8, x10, x1, x4) + +inst_832: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ce and fs2 == 1 and fe2 == 0x0f and fm2 == 0x05d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x13e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78ce; op2val:0xbc5d; +op3val:0x793e; valaddr_reg:x8; val_offset:2424*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2424*FLEN/8, x10, x1, x4) + +inst_833: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ce and fs2 == 1 and fe2 == 0x0f and fm2 == 0x05d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x13e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78ce; op2val:0xbc5d; +op3val:0x793e; valaddr_reg:x8; val_offset:2427*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2427*FLEN/8, x10, x1, x4) + +inst_834: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ce and fs2 == 1 and fe2 == 0x0f and fm2 == 0x05d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x13e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78ce; op2val:0xbc5d; +op3val:0x793e; valaddr_reg:x8; val_offset:2430*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2430*FLEN/8, x10, x1, x4) + +inst_835: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e2 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1d0 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1ba and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7be2; op2val:0xb5d0; +op3val:0x75ba; valaddr_reg:x8; val_offset:2433*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2433*FLEN/8, x10, x1, x4) + +inst_836: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e2 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1d0 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1ba and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7be2; op2val:0xb5d0; +op3val:0x75ba; valaddr_reg:x8; val_offset:2436*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2436*FLEN/8, x10, x1, x4) + +inst_837: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e2 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1d0 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1ba and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7be2; op2val:0xb5d0; +op3val:0x75ba; valaddr_reg:x8; val_offset:2439*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2439*FLEN/8, x10, x1, x4) + +inst_838: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e2 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1d0 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1ba and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7be2; op2val:0xb5d0; +op3val:0x75ba; valaddr_reg:x8; val_offset:2442*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2442*FLEN/8, x10, x1, x4) + +inst_839: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e2 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1d0 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1ba and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7be2; op2val:0xb5d0; +op3val:0x75ba; valaddr_reg:x8; val_offset:2445*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2445*FLEN/8, x10, x1, x4) + +inst_840: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x392 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x180 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x132 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b92; op2val:0xb980; +op3val:0x7932; valaddr_reg:x8; val_offset:2448*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2448*FLEN/8, x10, x1, x4) + +inst_841: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x392 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x180 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x132 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b92; op2val:0xb980; +op3val:0x7932; valaddr_reg:x8; val_offset:2451*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2451*FLEN/8, x10, x1, x4) + +inst_842: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x392 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x180 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x132 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b92; op2val:0xb980; +op3val:0x7932; valaddr_reg:x8; val_offset:2454*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2454*FLEN/8, x10, x1, x4) + +inst_843: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x392 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x180 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x132 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b92; op2val:0xb980; +op3val:0x7932; valaddr_reg:x8; val_offset:2457*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2457*FLEN/8, x10, x1, x4) + +inst_844: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x392 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x180 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x132 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b92; op2val:0xb980; +op3val:0x7932; valaddr_reg:x8; val_offset:2460*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2460*FLEN/8, x10, x1, x4) + +inst_845: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x39f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1bb and fs3 == 0 and fe3 == 0x1c and fm3 == 0x16d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x779f; op2val:0xb5bb; +op3val:0x716d; valaddr_reg:x8; val_offset:2463*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2463*FLEN/8, x10, x1, x4) + +inst_846: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x39f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1bb and fs3 == 0 and fe3 == 0x1c and fm3 == 0x16d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x779f; op2val:0xb5bb; +op3val:0x716d; valaddr_reg:x8; val_offset:2466*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2466*FLEN/8, x10, x1, x4) + +inst_847: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x39f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1bb and fs3 == 0 and fe3 == 0x1c and fm3 == 0x16d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x779f; op2val:0xb5bb; +op3val:0x716d; valaddr_reg:x8; val_offset:2469*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2469*FLEN/8, x10, x1, x4) + +inst_848: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x39f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1bb and fs3 == 0 and fe3 == 0x1c and fm3 == 0x16d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x779f; op2val:0xb5bb; +op3val:0x716d; valaddr_reg:x8; val_offset:2472*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2472*FLEN/8, x10, x1, x4) + +inst_849: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x39f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1bb and fs3 == 0 and fe3 == 0x1c and fm3 == 0x16d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x779f; op2val:0xb5bb; +op3val:0x716d; valaddr_reg:x8; val_offset:2475*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2475*FLEN/8, x10, x1, x4) + +inst_850: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x38a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x236 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1d7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x738a; op2val:0xbe36; +op3val:0x75d7; valaddr_reg:x8; val_offset:2478*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2478*FLEN/8, x10, x1, x4) + +inst_851: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x38a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x236 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1d7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x738a; op2val:0xbe36; +op3val:0x75d7; valaddr_reg:x8; val_offset:2481*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2481*FLEN/8, x10, x1, x4) + +inst_852: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x38a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x236 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1d7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x738a; op2val:0xbe36; +op3val:0x75d7; valaddr_reg:x8; val_offset:2484*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2484*FLEN/8, x10, x1, x4) + +inst_853: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x38a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x236 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1d7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x738a; op2val:0xbe36; +op3val:0x75d7; valaddr_reg:x8; val_offset:2487*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2487*FLEN/8, x10, x1, x4) + +inst_854: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x38a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x236 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1d7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x738a; op2val:0xbe36; +op3val:0x75d7; valaddr_reg:x8; val_offset:2490*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2490*FLEN/8, x10, x1, x4) + +inst_855: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x189 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x04e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1f1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7589; op2val:0xbc4e; +op3val:0x75f1; valaddr_reg:x8; val_offset:2493*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2493*FLEN/8, x10, x1, x4) + +inst_856: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x189 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x04e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1f1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7589; op2val:0xbc4e; +op3val:0x75f1; valaddr_reg:x8; val_offset:2496*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2496*FLEN/8, x10, x1, x4) + +inst_857: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x189 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x04e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1f1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7589; op2val:0xbc4e; +op3val:0x75f1; valaddr_reg:x8; val_offset:2499*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2499*FLEN/8, x10, x1, x4) + +inst_858: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x189 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x04e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1f1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7589; op2val:0xbc4e; +op3val:0x75f1; valaddr_reg:x8; val_offset:2502*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2502*FLEN/8, x10, x1, x4) + +inst_859: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x189 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x04e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1f1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7589; op2val:0xbc4e; +op3val:0x75f1; valaddr_reg:x8; val_offset:2505*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2505*FLEN/8, x10, x1, x4) + +inst_860: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x276 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x371 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a76; op2val:0xb771; +op3val:0x75fe; valaddr_reg:x8; val_offset:2508*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2508*FLEN/8, x10, x1, x4) + +inst_861: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x276 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x371 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1fe and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a76; op2val:0xb771; +op3val:0x75fe; valaddr_reg:x8; val_offset:2511*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2511*FLEN/8, x10, x1, x4) + +inst_862: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x276 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x371 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1fe and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a76; op2val:0xb771; +op3val:0x75fe; valaddr_reg:x8; val_offset:2514*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2514*FLEN/8, x10, x1, x4) + +inst_863: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x276 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x371 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1fe and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a76; op2val:0xb771; +op3val:0x75fe; valaddr_reg:x8; val_offset:2517*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2517*FLEN/8, x10, x1, x4) + +inst_864: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x276 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x371 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1fe and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a76; op2val:0xb771; +op3val:0x75fe; valaddr_reg:x8; val_offset:2520*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2520*FLEN/8, x10, x1, x4) + +inst_865: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x106 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x007 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x0f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7906; op2val:0xac07; +op3val:0x68f0; valaddr_reg:x8; val_offset:2523*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2523*FLEN/8, x10, x1, x4) + +inst_866: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x106 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x007 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x0f0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7906; op2val:0xac07; +op3val:0x68f0; valaddr_reg:x8; val_offset:2526*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2526*FLEN/8, x10, x1, x4) + +inst_867: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x106 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x007 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x0f0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7906; op2val:0xac07; +op3val:0x68f0; valaddr_reg:x8; val_offset:2529*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2529*FLEN/8, x10, x1, x4) + +inst_868: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x106 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x007 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x0f0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7906; op2val:0xac07; +op3val:0x68f0; valaddr_reg:x8; val_offset:2532*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2532*FLEN/8, x10, x1, x4) + +inst_869: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x106 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x007 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x0f0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7906; op2val:0xac07; +op3val:0x68f0; valaddr_reg:x8; val_offset:2535*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2535*FLEN/8, x10, x1, x4) + +inst_870: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x080 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x10d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ad and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7080; op2val:0xc50d; +op3val:0x79ad; valaddr_reg:x8; val_offset:2538*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2538*FLEN/8, x10, x1, x4) + +inst_871: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x080 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x10d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ad and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7080; op2val:0xc50d; +op3val:0x79ad; valaddr_reg:x8; val_offset:2541*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2541*FLEN/8, x10, x1, x4) + +inst_872: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x080 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x10d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ad and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7080; op2val:0xc50d; +op3val:0x79ad; valaddr_reg:x8; val_offset:2544*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2544*FLEN/8, x10, x1, x4) + +inst_873: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x080 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x10d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ad and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7080; op2val:0xc50d; +op3val:0x79ad; valaddr_reg:x8; val_offset:2547*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2547*FLEN/8, x10, x1, x4) + +inst_874: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x080 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x10d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ad and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7080; op2val:0xc50d; +op3val:0x79ad; valaddr_reg:x8; val_offset:2550*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2550*FLEN/8, x10, x1, x4) + +inst_875: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x31f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x19b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x101 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b1f; op2val:0xb59b; +op3val:0x7501; valaddr_reg:x8; val_offset:2553*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2553*FLEN/8, x10, x1, x4) + +inst_876: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x31f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x19b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x101 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b1f; op2val:0xb59b; +op3val:0x7501; valaddr_reg:x8; val_offset:2556*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2556*FLEN/8, x10, x1, x4) + +inst_877: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x31f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x19b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x101 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b1f; op2val:0xb59b; +op3val:0x7501; valaddr_reg:x8; val_offset:2559*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2559*FLEN/8, x10, x1, x4) + +inst_878: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x31f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x19b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x101 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b1f; op2val:0xb59b; +op3val:0x7501; valaddr_reg:x8; val_offset:2562*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2562*FLEN/8, x10, x1, x4) + +inst_879: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x31f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x19b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x101 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b1f; op2val:0xb59b; +op3val:0x7501; valaddr_reg:x8; val_offset:2565*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2565*FLEN/8, x10, x1, x4) + +inst_880: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x027 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x322 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x370 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6827; op2val:0xc722; +op3val:0x7370; valaddr_reg:x8; val_offset:2568*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2568*FLEN/8, x10, x1, x4) + +inst_881: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x027 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x322 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x370 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6827; op2val:0xc722; +op3val:0x7370; valaddr_reg:x8; val_offset:2571*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2571*FLEN/8, x10, x1, x4) + +inst_882: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x027 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x322 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x370 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6827; op2val:0xc722; +op3val:0x7370; valaddr_reg:x8; val_offset:2574*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2574*FLEN/8, x10, x1, x4) + +inst_883: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x027 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x322 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x370 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6827; op2val:0xc722; +op3val:0x7370; valaddr_reg:x8; val_offset:2577*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2577*FLEN/8, x10, x1, x4) + +inst_884: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x027 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x322 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x370 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6827; op2val:0xc722; +op3val:0x7370; valaddr_reg:x8; val_offset:2580*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2580*FLEN/8, x10, x1, x4) + +inst_885: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x00e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1dc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c3; op2val:0xbc0e; +op3val:0x75dc; valaddr_reg:x8; val_offset:2583*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2583*FLEN/8, x10, x1, x4) + +inst_886: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x00e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1dc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c3; op2val:0xbc0e; +op3val:0x75dc; valaddr_reg:x8; val_offset:2586*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2586*FLEN/8, x10, x1, x4) + +inst_887: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x00e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1dc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c3; op2val:0xbc0e; +op3val:0x75dc; valaddr_reg:x8; val_offset:2589*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2589*FLEN/8, x10, x1, x4) + +inst_888: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x00e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1dc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c3; op2val:0xbc0e; +op3val:0x75dc; valaddr_reg:x8; val_offset:2592*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2592*FLEN/8, x10, x1, x4) + +inst_889: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x00e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1dc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c3; op2val:0xbc0e; +op3val:0x75dc; valaddr_reg:x8; val_offset:2595*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2595*FLEN/8, x10, x1, x4) + +inst_890: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x07d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x048 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0d3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x787d; op2val:0xb848; +op3val:0x74d3; valaddr_reg:x8; val_offset:2598*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2598*FLEN/8, x10, x1, x4) + +inst_891: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x07d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x048 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0d3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x787d; op2val:0xb848; +op3val:0x74d3; valaddr_reg:x8; val_offset:2601*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2601*FLEN/8, x10, x1, x4) + +inst_892: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x07d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x048 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0d3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x787d; op2val:0xb848; +op3val:0x74d3; valaddr_reg:x8; val_offset:2604*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2604*FLEN/8, x10, x1, x4) + +inst_893: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x07d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x048 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0d3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x787d; op2val:0xb848; +op3val:0x74d3; valaddr_reg:x8; val_offset:2607*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2607*FLEN/8, x10, x1, x4) + +inst_894: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x07d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x048 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0d3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x787d; op2val:0xb848; +op3val:0x74d3; valaddr_reg:x8; val_offset:2610*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2610*FLEN/8, x10, x1, x4) + +inst_895: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0da and fs3 == 0 and fe3 == 0x1e and fm3 == 0x248 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x792c; op2val:0xbcda; +op3val:0x7a48; valaddr_reg:x8; val_offset:2613*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2613*FLEN/8, x10, x1, x4) + +inst_896: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0da and fs3 == 0 and fe3 == 0x1e and fm3 == 0x248 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x792c; op2val:0xbcda; +op3val:0x7a48; valaddr_reg:x8; val_offset:2616*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2616*FLEN/8, x10, x1, x4) + +inst_897: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0da and fs3 == 0 and fe3 == 0x1e and fm3 == 0x248 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x792c; op2val:0xbcda; +op3val:0x7a48; valaddr_reg:x8; val_offset:2619*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2619*FLEN/8, x10, x1, x4) + +inst_898: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0da and fs3 == 0 and fe3 == 0x1e and fm3 == 0x248 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x792c; op2val:0xbcda; +op3val:0x7a48; valaddr_reg:x8; val_offset:2622*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2622*FLEN/8, x10, x1, x4) + +inst_899: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0da and fs3 == 0 and fe3 == 0x1e and fm3 == 0x248 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x792c; op2val:0xbcda; +op3val:0x7a48; valaddr_reg:x8; val_offset:2625*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2625*FLEN/8, x10, x1, x4) + +inst_900: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x243 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x390 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ed and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a43; op2val:0xbb90; +op3val:0x79ed; valaddr_reg:x8; val_offset:2628*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2628*FLEN/8, x10, x1, x4) + +inst_901: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x243 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x390 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ed and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a43; op2val:0xbb90; +op3val:0x79ed; valaddr_reg:x8; val_offset:2631*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2631*FLEN/8, x10, x1, x4) + +inst_902: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x243 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x390 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ed and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a43; op2val:0xbb90; +op3val:0x79ed; valaddr_reg:x8; val_offset:2634*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2634*FLEN/8, x10, x1, x4) + +inst_903: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x243 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x390 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ed and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a43; op2val:0xbb90; +op3val:0x79ed; valaddr_reg:x8; val_offset:2637*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2637*FLEN/8, x10, x1, x4) + +inst_904: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x243 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x390 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ed and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a43; op2val:0xbb90; +op3val:0x79ed; valaddr_reg:x8; val_offset:2640*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2640*FLEN/8, x10, x1, x4) + +inst_905: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ab and fs2 == 1 and fe2 == 0x0d and fm2 == 0x31e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x02b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78ab; op2val:0xb71e; +op3val:0x742b; valaddr_reg:x8; val_offset:2643*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2643*FLEN/8, x10, x1, x4) + +inst_906: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ab and fs2 == 1 and fe2 == 0x0d and fm2 == 0x31e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x02b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78ab; op2val:0xb71e; +op3val:0x742b; valaddr_reg:x8; val_offset:2646*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2646*FLEN/8, x10, x1, x4) + +inst_907: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ab and fs2 == 1 and fe2 == 0x0d and fm2 == 0x31e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x02b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78ab; op2val:0xb71e; +op3val:0x742b; valaddr_reg:x8; val_offset:2649*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2649*FLEN/8, x10, x1, x4) + +inst_908: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ab and fs2 == 1 and fe2 == 0x0d and fm2 == 0x31e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x02b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78ab; op2val:0xb71e; +op3val:0x742b; valaddr_reg:x8; val_offset:2652*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2652*FLEN/8, x10, x1, x4) + +inst_909: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ab and fs2 == 1 and fe2 == 0x0d and fm2 == 0x31e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x02b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78ab; op2val:0xb71e; +op3val:0x742b; valaddr_reg:x8; val_offset:2655*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2655*FLEN/8, x10, x1, x4) + +inst_910: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ba and fs2 == 1 and fe2 == 0x0d and fm2 == 0x17c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aba; op2val:0xb57c; +op3val:0x74a1; valaddr_reg:x8; val_offset:2658*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2658*FLEN/8, x10, x1, x4) + +inst_911: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ba and fs2 == 1 and fe2 == 0x0d and fm2 == 0x17c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aba; op2val:0xb57c; +op3val:0x74a1; valaddr_reg:x8; val_offset:2661*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2661*FLEN/8, x10, x1, x4) + +inst_912: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ba and fs2 == 1 and fe2 == 0x0d and fm2 == 0x17c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aba; op2val:0xb57c; +op3val:0x74a1; valaddr_reg:x8; val_offset:2664*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2664*FLEN/8, x10, x1, x4) + +inst_913: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ba and fs2 == 1 and fe2 == 0x0d and fm2 == 0x17c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aba; op2val:0xb57c; +op3val:0x74a1; valaddr_reg:x8; val_offset:2667*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2667*FLEN/8, x10, x1, x4) + +inst_914: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ba and fs2 == 1 and fe2 == 0x0d and fm2 == 0x17c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aba; op2val:0xb57c; +op3val:0x74a1; valaddr_reg:x8; val_offset:2670*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2670*FLEN/8, x10, x1, x4) + +inst_915: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e0 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x026 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x326 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ae0; op2val:0xb826; +op3val:0x7726; valaddr_reg:x8; val_offset:2673*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2673*FLEN/8, x10, x1, x4) + +inst_916: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e0 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x026 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x326 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ae0; op2val:0xb826; +op3val:0x7726; valaddr_reg:x8; val_offset:2676*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2676*FLEN/8, x10, x1, x4) + +inst_917: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e0 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x026 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x326 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ae0; op2val:0xb826; +op3val:0x7726; valaddr_reg:x8; val_offset:2679*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2679*FLEN/8, x10, x1, x4) + +inst_918: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e0 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x026 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x326 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ae0; op2val:0xb826; +op3val:0x7726; valaddr_reg:x8; val_offset:2682*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2682*FLEN/8, x10, x1, x4) + +inst_919: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e0 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x026 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x326 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ae0; op2val:0xb826; +op3val:0x7726; valaddr_reg:x8; val_offset:2685*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2685*FLEN/8, x10, x1, x4) + +inst_920: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x107 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3fb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7907; op2val:0xba55; +op3val:0x77fb; valaddr_reg:x8; val_offset:2688*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2688*FLEN/8, x10, x1, x4) + +inst_921: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x107 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3fb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7907; op2val:0xba55; +op3val:0x77fb; valaddr_reg:x8; val_offset:2691*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2691*FLEN/8, x10, x1, x4) + +inst_922: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x107 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3fb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7907; op2val:0xba55; +op3val:0x77fb; valaddr_reg:x8; val_offset:2694*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2694*FLEN/8, x10, x1, x4) + +inst_923: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x107 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3fb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7907; op2val:0xba55; +op3val:0x77fb; valaddr_reg:x8; val_offset:2697*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2697*FLEN/8, x10, x1, x4) + +inst_924: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x107 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3fb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7907; op2val:0xba55; +op3val:0x77fb; valaddr_reg:x8; val_offset:2700*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2700*FLEN/8, x10, x1, x4) + +inst_925: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x13a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x029 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x174 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x793a; op2val:0xb829; +op3val:0x7574; valaddr_reg:x8; val_offset:2703*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2703*FLEN/8, x10, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_9) + +inst_926: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x13a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x029 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x174 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x793a; op2val:0xb829; +op3val:0x7574; valaddr_reg:x8; val_offset:2706*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2706*FLEN/8, x10, x1, x4) + +inst_927: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x13a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x029 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x174 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x793a; op2val:0xb829; +op3val:0x7574; valaddr_reg:x8; val_offset:2709*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2709*FLEN/8, x10, x1, x4) + +inst_928: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x13a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x029 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x174 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x793a; op2val:0xb829; +op3val:0x7574; valaddr_reg:x8; val_offset:2712*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2712*FLEN/8, x10, x1, x4) + +inst_929: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x13a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x029 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x174 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x793a; op2val:0xb829; +op3val:0x7574; valaddr_reg:x8; val_offset:2715*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2715*FLEN/8, x10, x1, x4) + +inst_930: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x116 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1e3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x789f; op2val:0xbd16; +op3val:0x79e3; valaddr_reg:x8; val_offset:2718*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2718*FLEN/8, x10, x1, x4) + +inst_931: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x116 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1e3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x789f; op2val:0xbd16; +op3val:0x79e3; valaddr_reg:x8; val_offset:2721*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2721*FLEN/8, x10, x1, x4) + +inst_932: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x116 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1e3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x789f; op2val:0xbd16; +op3val:0x79e3; valaddr_reg:x8; val_offset:2724*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2724*FLEN/8, x10, x1, x4) + +inst_933: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x116 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1e3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x789f; op2val:0xbd16; +op3val:0x79e3; valaddr_reg:x8; val_offset:2727*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2727*FLEN/8, x10, x1, x4) + +inst_934: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x116 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1e3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x789f; op2val:0xbd16; +op3val:0x79e3; valaddr_reg:x8; val_offset:2730*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2730*FLEN/8, x10, x1, x4) + +inst_935: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c7 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2a2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0cd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c7; op2val:0xbea2; +op3val:0x78cd; valaddr_reg:x8; val_offset:2733*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2733*FLEN/8, x10, x1, x4) + +inst_936: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c7 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2a2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0cd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c7; op2val:0xbea2; +op3val:0x78cd; valaddr_reg:x8; val_offset:2736*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2736*FLEN/8, x10, x1, x4) + +inst_937: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c7 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2a2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0cd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c7; op2val:0xbea2; +op3val:0x78cd; valaddr_reg:x8; val_offset:2739*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2739*FLEN/8, x10, x1, x4) + +inst_938: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c7 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2a2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0cd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c7; op2val:0xbea2; +op3val:0x78cd; valaddr_reg:x8; val_offset:2742*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2742*FLEN/8, x10, x1, x4) + +inst_939: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c7 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2a2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0cd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c7; op2val:0xbea2; +op3val:0x78cd; valaddr_reg:x8; val_offset:2745*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2745*FLEN/8, x10, x1, x4) + +inst_940: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x34c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x01c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x384 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x774c; op2val:0xbc1c; +op3val:0x7784; valaddr_reg:x8; val_offset:2748*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2748*FLEN/8, x10, x1, x4) + +inst_941: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x34c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x01c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x384 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x774c; op2val:0xbc1c; +op3val:0x7784; valaddr_reg:x8; val_offset:2751*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2751*FLEN/8, x10, x1, x4) + +inst_942: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x34c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x01c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x384 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x774c; op2val:0xbc1c; +op3val:0x7784; valaddr_reg:x8; val_offset:2754*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2754*FLEN/8, x10, x1, x4) + +inst_943: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x34c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x01c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x384 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x774c; op2val:0xbc1c; +op3val:0x7784; valaddr_reg:x8; val_offset:2757*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2757*FLEN/8, x10, x1, x4) + +inst_944: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x34c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x01c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x384 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x774c; op2val:0xbc1c; +op3val:0x7784; valaddr_reg:x8; val_offset:2760*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2760*FLEN/8, x10, x1, x4) + +inst_945: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x222 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1b5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x05e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7622; op2val:0xbdb5; +op3val:0x785e; valaddr_reg:x8; val_offset:2763*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2763*FLEN/8, x10, x1, x4) + +inst_946: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x222 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1b5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x05e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7622; op2val:0xbdb5; +op3val:0x785e; valaddr_reg:x8; val_offset:2766*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2766*FLEN/8, x10, x1, x4) + +inst_947: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x222 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1b5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x05e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7622; op2val:0xbdb5; +op3val:0x785e; valaddr_reg:x8; val_offset:2769*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2769*FLEN/8, x10, x1, x4) + +inst_948: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x222 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1b5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x05e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7622; op2val:0xbdb5; +op3val:0x785e; valaddr_reg:x8; val_offset:2772*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2772*FLEN/8, x10, x1, x4) + +inst_949: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x222 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1b5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x05e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7622; op2val:0xbdb5; +op3val:0x785e; valaddr_reg:x8; val_offset:2775*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2775*FLEN/8, x10, x1, x4) + +inst_950: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ac and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3e1 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x18e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79ac; op2val:0xb3e1; +op3val:0x718e; valaddr_reg:x8; val_offset:2778*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2778*FLEN/8, x10, x1, x4) + +inst_951: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ac and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3e1 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x18e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79ac; op2val:0xb3e1; +op3val:0x718e; valaddr_reg:x8; val_offset:2781*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2781*FLEN/8, x10, x1, x4) + +inst_952: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ac and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3e1 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x18e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79ac; op2val:0xb3e1; +op3val:0x718e; valaddr_reg:x8; val_offset:2784*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2784*FLEN/8, x10, x1, x4) + +inst_953: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ac and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3e1 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x18e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79ac; op2val:0xb3e1; +op3val:0x718e; valaddr_reg:x8; val_offset:2787*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2787*FLEN/8, x10, x1, x4) + +inst_954: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ac and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3e1 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x18e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79ac; op2val:0xb3e1; +op3val:0x718e; valaddr_reg:x8; val_offset:2790*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2790*FLEN/8, x10, x1, x4) + +inst_955: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0ac and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1a4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x295 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70ac; op2val:0xc5a4; +op3val:0x7a95; valaddr_reg:x8; val_offset:2793*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2793*FLEN/8, x10, x1, x4) + +inst_956: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0ac and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1a4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x295 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70ac; op2val:0xc5a4; +op3val:0x7a95; valaddr_reg:x8; val_offset:2796*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2796*FLEN/8, x10, x1, x4) + +inst_957: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0ac and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1a4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x295 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70ac; op2val:0xc5a4; +op3val:0x7a95; valaddr_reg:x8; val_offset:2799*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2799*FLEN/8, x10, x1, x4) + +inst_958: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0ac and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1a4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x295 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70ac; op2val:0xc5a4; +op3val:0x7a95; valaddr_reg:x8; val_offset:2802*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2802*FLEN/8, x10, x1, x4) + +inst_959: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0ac and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1a4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x295 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70ac; op2val:0xc5a4; +op3val:0x7a95; valaddr_reg:x8; val_offset:2805*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2805*FLEN/8, x10, x1, x4) + +inst_960: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1a9 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x07c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x257 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6da9; op2val:0xc87c; +op3val:0x7a57; valaddr_reg:x8; val_offset:2808*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2808*FLEN/8, x10, x1, x4) + +inst_961: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1a9 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x07c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x257 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6da9; op2val:0xc87c; +op3val:0x7a57; valaddr_reg:x8; val_offset:2811*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2811*FLEN/8, x10, x1, x4) + +inst_962: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1a9 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x07c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x257 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6da9; op2val:0xc87c; +op3val:0x7a57; valaddr_reg:x8; val_offset:2814*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2814*FLEN/8, x10, x1, x4) + +inst_963: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1a9 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x07c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x257 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6da9; op2val:0xc87c; +op3val:0x7a57; valaddr_reg:x8; val_offset:2817*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2817*FLEN/8, x10, x1, x4) + +inst_964: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1a9 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x07c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x257 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6da9; op2val:0xc87c; +op3val:0x7a57; valaddr_reg:x8; val_offset:2820*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2820*FLEN/8, x10, x1, x4) + +inst_965: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x211 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x09b and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2f6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a11; op2val:0xb49b; +op3val:0x72f6; valaddr_reg:x8; val_offset:2823*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2823*FLEN/8, x10, x1, x4) + +inst_966: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x211 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x09b and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2f6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a11; op2val:0xb49b; +op3val:0x72f6; valaddr_reg:x8; val_offset:2826*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2826*FLEN/8, x10, x1, x4) + +inst_967: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x211 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x09b and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2f6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a11; op2val:0xb49b; +op3val:0x72f6; valaddr_reg:x8; val_offset:2829*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2829*FLEN/8, x10, x1, x4) + +inst_968: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x211 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x09b and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2f6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a11; op2val:0xb49b; +op3val:0x72f6; valaddr_reg:x8; val_offset:2832*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2832*FLEN/8, x10, x1, x4) + +inst_969: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x211 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x09b and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2f6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a11; op2val:0xb49b; +op3val:0x72f6; valaddr_reg:x8; val_offset:2835*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2835*FLEN/8, x10, x1, x4) + +inst_970: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x115 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x266 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x00d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7915; op2val:0xb666; +op3val:0x740d; valaddr_reg:x8; val_offset:2838*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2838*FLEN/8, x10, x1, x4) + +inst_971: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x115 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x266 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x00d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7915; op2val:0xb666; +op3val:0x740d; valaddr_reg:x8; val_offset:2841*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2841*FLEN/8, x10, x1, x4) + +inst_972: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x115 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x266 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x00d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7915; op2val:0xb666; +op3val:0x740d; valaddr_reg:x8; val_offset:2844*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2844*FLEN/8, x10, x1, x4) + +inst_973: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x115 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x266 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x00d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7915; op2val:0xb666; +op3val:0x740d; valaddr_reg:x8; val_offset:2847*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2847*FLEN/8, x10, x1, x4) + +inst_974: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x115 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x266 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x00d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7915; op2val:0xb666; +op3val:0x740d; valaddr_reg:x8; val_offset:2850*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2850*FLEN/8, x10, x1, x4) + +inst_975: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30c and fs2 == 1 and fe2 == 0x0c and fm2 == 0x332 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x24f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b0c; op2val:0xb332; +op3val:0x724f; valaddr_reg:x8; val_offset:2853*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2853*FLEN/8, x10, x1, x4) + +inst_976: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30c and fs2 == 1 and fe2 == 0x0c and fm2 == 0x332 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x24f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b0c; op2val:0xb332; +op3val:0x724f; valaddr_reg:x8; val_offset:2856*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2856*FLEN/8, x10, x1, x4) + +inst_977: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30c and fs2 == 1 and fe2 == 0x0c and fm2 == 0x332 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x24f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b0c; op2val:0xb332; +op3val:0x724f; valaddr_reg:x8; val_offset:2859*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2859*FLEN/8, x10, x1, x4) + +inst_978: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30c and fs2 == 1 and fe2 == 0x0c and fm2 == 0x332 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x24f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b0c; op2val:0xb332; +op3val:0x724f; valaddr_reg:x8; val_offset:2862*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2862*FLEN/8, x10, x1, x4) + +inst_979: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30c and fs2 == 1 and fe2 == 0x0c and fm2 == 0x332 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x24f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b0c; op2val:0xb332; +op3val:0x724f; valaddr_reg:x8; val_offset:2865*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2865*FLEN/8, x10, x1, x4) + +inst_980: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x366 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x110 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x0ae and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f66; op2val:0xb510; +op3val:0x68ae; valaddr_reg:x8; val_offset:2868*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2868*FLEN/8, x10, x1, x4) + +inst_981: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x366 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x110 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x0ae and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f66; op2val:0xb510; +op3val:0x68ae; valaddr_reg:x8; val_offset:2871*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2871*FLEN/8, x10, x1, x4) + +inst_982: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x366 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x110 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x0ae and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f66; op2val:0xb510; +op3val:0x68ae; valaddr_reg:x8; val_offset:2874*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2874*FLEN/8, x10, x1, x4) + +inst_983: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x366 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x110 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x0ae and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f66; op2val:0xb510; +op3val:0x68ae; valaddr_reg:x8; val_offset:2877*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2877*FLEN/8, x10, x1, x4) + +inst_984: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x366 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x110 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x0ae and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f66; op2val:0xb510; +op3val:0x68ae; valaddr_reg:x8; val_offset:2880*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2880*FLEN/8, x10, x1, x4) + +inst_985: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1be and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0b7 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2c6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79be; op2val:0xb4b7; +op3val:0x72c6; valaddr_reg:x8; val_offset:2883*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2883*FLEN/8, x10, x1, x4) + +inst_986: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1be and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0b7 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2c6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79be; op2val:0xb4b7; +op3val:0x72c6; valaddr_reg:x8; val_offset:2886*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2886*FLEN/8, x10, x1, x4) + +inst_987: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1be and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0b7 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2c6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79be; op2val:0xb4b7; +op3val:0x72c6; valaddr_reg:x8; val_offset:2889*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2889*FLEN/8, x10, x1, x4) + +inst_988: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1be and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0b7 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2c6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79be; op2val:0xb4b7; +op3val:0x72c6; valaddr_reg:x8; val_offset:2892*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2892*FLEN/8, x10, x1, x4) + +inst_989: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1be and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0b7 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2c6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79be; op2val:0xb4b7; +op3val:0x72c6; valaddr_reg:x8; val_offset:2895*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2895*FLEN/8, x10, x1, x4) + +inst_990: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x106 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x237 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3cf and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7506; op2val:0xc237; +op3val:0x7bcf; valaddr_reg:x8; val_offset:2898*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2898*FLEN/8, x10, x1, x4) + +inst_991: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x106 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x237 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3cf and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7506; op2val:0xc237; +op3val:0x7bcf; valaddr_reg:x8; val_offset:2901*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2901*FLEN/8, x10, x1, x4) + +inst_992: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x106 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x237 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3cf and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7506; op2val:0xc237; +op3val:0x7bcf; valaddr_reg:x8; val_offset:2904*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2904*FLEN/8, x10, x1, x4) + +inst_993: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x106 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x237 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3cf and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7506; op2val:0xc237; +op3val:0x7bcf; valaddr_reg:x8; val_offset:2907*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2907*FLEN/8, x10, x1, x4) + +inst_994: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x106 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x237 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3cf and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7506; op2val:0xc237; +op3val:0x7bcf; valaddr_reg:x8; val_offset:2910*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2910*FLEN/8, x10, x1, x4) + +inst_995: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1e2 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1e5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79e2; op2val:0xbc02; +op3val:0x79e5; valaddr_reg:x8; val_offset:2913*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2913*FLEN/8, x10, x1, x4) + +inst_996: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1e2 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1e5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79e2; op2val:0xbc02; +op3val:0x79e5; valaddr_reg:x8; val_offset:2916*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2916*FLEN/8, x10, x1, x4) + +inst_997: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1e2 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1e5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79e2; op2val:0xbc02; +op3val:0x79e5; valaddr_reg:x8; val_offset:2919*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2919*FLEN/8, x10, x1, x4) + +inst_998: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1e2 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1e5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79e2; op2val:0xbc02; +op3val:0x79e5; valaddr_reg:x8; val_offset:2922*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2922*FLEN/8, x10, x1, x4) + +inst_999: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1e2 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1e5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79e2; op2val:0xbc02; +op3val:0x79e5; valaddr_reg:x8; val_offset:2925*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2925*FLEN/8, x10, x1, x4) + +inst_1000: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x073 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x11f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x789a; op2val:0xbc73; +op3val:0x791f; valaddr_reg:x8; val_offset:2928*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2928*FLEN/8, x10, x1, x4) + +inst_1001: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x073 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x11f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x789a; op2val:0xbc73; +op3val:0x791f; valaddr_reg:x8; val_offset:2931*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2931*FLEN/8, x10, x1, x4) + +inst_1002: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x073 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x11f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x789a; op2val:0xbc73; +op3val:0x791f; valaddr_reg:x8; val_offset:2934*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2934*FLEN/8, x10, x1, x4) + +inst_1003: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x073 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x11f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x789a; op2val:0xbc73; +op3val:0x791f; valaddr_reg:x8; val_offset:2937*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2937*FLEN/8, x10, x1, x4) + +inst_1004: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x073 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x11f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x789a; op2val:0xbc73; +op3val:0x791f; valaddr_reg:x8; val_offset:2940*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2940*FLEN/8, x10, x1, x4) + +inst_1005: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x1a8 and fs2 == 1 and fe2 == 0x15 and fm2 == 0x097 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x27f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x61a8; op2val:0xd497; +op3val:0x7a7f; valaddr_reg:x8; val_offset:2943*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2943*FLEN/8, x10, x1, x4) + +inst_1006: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x1a8 and fs2 == 1 and fe2 == 0x15 and fm2 == 0x097 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x27f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x61a8; op2val:0xd497; +op3val:0x7a7f; valaddr_reg:x8; val_offset:2946*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2946*FLEN/8, x10, x1, x4) + +inst_1007: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x1a8 and fs2 == 1 and fe2 == 0x15 and fm2 == 0x097 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x27f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x61a8; op2val:0xd497; +op3val:0x7a7f; valaddr_reg:x8; val_offset:2949*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2949*FLEN/8, x10, x1, x4) + +inst_1008: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x1a8 and fs2 == 1 and fe2 == 0x15 and fm2 == 0x097 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x27f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x61a8; op2val:0xd497; +op3val:0x7a7f; valaddr_reg:x8; val_offset:2952*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2952*FLEN/8, x10, x1, x4) + +inst_1009: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x1a8 and fs2 == 1 and fe2 == 0x15 and fm2 == 0x097 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x27f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x61a8; op2val:0xd497; +op3val:0x7a7f; valaddr_reg:x8; val_offset:2955*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2955*FLEN/8, x10, x1, x4) + +inst_1010: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x143 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x131 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2d5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7543; op2val:0xc131; +op3val:0x7ad5; valaddr_reg:x8; val_offset:2958*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2958*FLEN/8, x10, x1, x4) + +inst_1011: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x143 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x131 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2d5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7543; op2val:0xc131; +op3val:0x7ad5; valaddr_reg:x8; val_offset:2961*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2961*FLEN/8, x10, x1, x4) + +inst_1012: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x143 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x131 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2d5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7543; op2val:0xc131; +op3val:0x7ad5; valaddr_reg:x8; val_offset:2964*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2964*FLEN/8, x10, x1, x4) + +inst_1013: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x143 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x131 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2d5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7543; op2val:0xc131; +op3val:0x7ad5; valaddr_reg:x8; val_offset:2967*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2967*FLEN/8, x10, x1, x4) + +inst_1014: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x143 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x131 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2d5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7543; op2val:0xc131; +op3val:0x7ad5; valaddr_reg:x8; val_offset:2970*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2970*FLEN/8, x10, x1, x4) + +inst_1015: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a1 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x065 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x349 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76a1; op2val:0xc065; +op3val:0x7b49; valaddr_reg:x8; val_offset:2973*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2973*FLEN/8, x10, x1, x4) + +inst_1016: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a1 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x065 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x349 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76a1; op2val:0xc065; +op3val:0x7b49; valaddr_reg:x8; val_offset:2976*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2976*FLEN/8, x10, x1, x4) + +inst_1017: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a1 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x065 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x349 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76a1; op2val:0xc065; +op3val:0x7b49; valaddr_reg:x8; val_offset:2979*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2979*FLEN/8, x10, x1, x4) + +inst_1018: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a1 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x065 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x349 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76a1; op2val:0xc065; +op3val:0x7b49; valaddr_reg:x8; val_offset:2982*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2982*FLEN/8, x10, x1, x4) + +inst_1019: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a1 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x065 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x349 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76a1; op2val:0xc065; +op3val:0x7b49; valaddr_reg:x8; val_offset:2985*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2985*FLEN/8, x10, x1, x4) + +inst_1020: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3b6 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x010 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3d6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4fb6; op2val:0xe810; +op3val:0x7bd6; valaddr_reg:x8; val_offset:2988*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2988*FLEN/8, x10, x1, x4) + +inst_1021: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3b6 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x010 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3d6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4fb6; op2val:0xe810; +op3val:0x7bd6; valaddr_reg:x8; val_offset:2991*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2991*FLEN/8, x10, x1, x4) + +inst_1022: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3b6 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x010 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3d6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4fb6; op2val:0xe810; +op3val:0x7bd6; valaddr_reg:x8; val_offset:2994*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2994*FLEN/8, x10, x1, x4) + +inst_1023: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3b6 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x010 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3d6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4fb6; op2val:0xe810; +op3val:0x7bd6; valaddr_reg:x8; val_offset:2997*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2997*FLEN/8, x10, x1, x4) + +inst_1024: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3b6 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x010 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3d6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4fb6; op2val:0xe810; +op3val:0x7bd6; valaddr_reg:x8; val_offset:3000*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3000*FLEN/8, x10, x1, x4) + +inst_1025: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x221 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x154 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x015 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e21; op2val:0xc554; +op3val:0x7815; valaddr_reg:x8; val_offset:3003*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3003*FLEN/8, x10, x1, x4) + +inst_1026: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x221 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x154 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x015 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e21; op2val:0xc554; +op3val:0x7815; valaddr_reg:x8; val_offset:3006*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3006*FLEN/8, x10, x1, x4) + +inst_1027: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x221 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x154 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x015 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e21; op2val:0xc554; +op3val:0x7815; valaddr_reg:x8; val_offset:3009*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3009*FLEN/8, x10, x1, x4) + +inst_1028: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x221 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x154 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x015 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e21; op2val:0xc554; +op3val:0x7815; valaddr_reg:x8; val_offset:3012*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3012*FLEN/8, x10, x1, x4) + +inst_1029: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x221 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x154 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x015 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e21; op2val:0xc554; +op3val:0x7815; valaddr_reg:x8; val_offset:3015*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3015*FLEN/8, x10, x1, x4) + +inst_1030: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3b3 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x018 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3e2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77b3; op2val:0xc018; +op3val:0x7be2; valaddr_reg:x8; val_offset:3018*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3018*FLEN/8, x10, x1, x4) + +inst_1031: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3b3 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x018 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3e2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77b3; op2val:0xc018; +op3val:0x7be2; valaddr_reg:x8; val_offset:3021*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3021*FLEN/8, x10, x1, x4) + +inst_1032: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3b3 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x018 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3e2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77b3; op2val:0xc018; +op3val:0x7be2; valaddr_reg:x8; val_offset:3024*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3024*FLEN/8, x10, x1, x4) + +inst_1033: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3b3 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x018 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3e2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77b3; op2val:0xc018; +op3val:0x7be2; valaddr_reg:x8; val_offset:3027*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3027*FLEN/8, x10, x1, x4) + +inst_1034: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3b3 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x018 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3e2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77b3; op2val:0xc018; +op3val:0x7be2; valaddr_reg:x8; val_offset:3030*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3030*FLEN/8, x10, x1, x4) + +inst_1035: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1bb and fs2 == 1 and fe2 == 0x0f and fm2 == 0x17a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3d9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79bb; op2val:0xbd7a; +op3val:0x7bd9; valaddr_reg:x8; val_offset:3033*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3033*FLEN/8, x10, x1, x4) + +inst_1036: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1bb and fs2 == 1 and fe2 == 0x0f and fm2 == 0x17a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3d9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79bb; op2val:0xbd7a; +op3val:0x7bd9; valaddr_reg:x8; val_offset:3036*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3036*FLEN/8, x10, x1, x4) + +inst_1037: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1bb and fs2 == 1 and fe2 == 0x0f and fm2 == 0x17a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3d9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79bb; op2val:0xbd7a; +op3val:0x7bd9; valaddr_reg:x8; val_offset:3039*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3039*FLEN/8, x10, x1, x4) + +inst_1038: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1bb and fs2 == 1 and fe2 == 0x0f and fm2 == 0x17a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3d9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79bb; op2val:0xbd7a; +op3val:0x7bd9; valaddr_reg:x8; val_offset:3042*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3042*FLEN/8, x10, x1, x4) + +inst_1039: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1bb and fs2 == 1 and fe2 == 0x0f and fm2 == 0x17a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3d9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79bb; op2val:0xbd7a; +op3val:0x7bd9; valaddr_reg:x8; val_offset:3045*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3045*FLEN/8, x10, x1, x4) + +inst_1040: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x33e and fs2 == 1 and fe2 == 0x0d and fm2 == 0x382 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2cc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b3e; op2val:0xb782; +op3val:0x76cc; valaddr_reg:x8; val_offset:3048*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3048*FLEN/8, x10, x1, x4) + +inst_1041: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x33e and fs2 == 1 and fe2 == 0x0d and fm2 == 0x382 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2cc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b3e; op2val:0xb782; +op3val:0x76cc; valaddr_reg:x8; val_offset:3051*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3051*FLEN/8, x10, x1, x4) + +inst_1042: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x33e and fs2 == 1 and fe2 == 0x0d and fm2 == 0x382 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2cc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b3e; op2val:0xb782; +op3val:0x76cc; valaddr_reg:x8; val_offset:3054*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3054*FLEN/8, x10, x1, x4) + +inst_1043: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x33e and fs2 == 1 and fe2 == 0x0d and fm2 == 0x382 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2cc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b3e; op2val:0xb782; +op3val:0x76cc; valaddr_reg:x8; val_offset:3057*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3057*FLEN/8, x10, x1, x4) + +inst_1044: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x33e and fs2 == 1 and fe2 == 0x0d and fm2 == 0x382 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2cc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b3e; op2val:0xb782; +op3val:0x76cc; valaddr_reg:x8; val_offset:3060*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3060*FLEN/8, x10, x1, x4) + +inst_1045: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0b9 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3e6 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70b9; op2val:0xbbe6; +op3val:0x70aa; valaddr_reg:x8; val_offset:3063*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3063*FLEN/8, x10, x1, x4) + +inst_1046: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0b9 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3e6 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0aa and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70b9; op2val:0xbbe6; +op3val:0x70aa; valaddr_reg:x8; val_offset:3066*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3066*FLEN/8, x10, x1, x4) + +inst_1047: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0b9 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3e6 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0aa and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70b9; op2val:0xbbe6; +op3val:0x70aa; valaddr_reg:x8; val_offset:3069*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3069*FLEN/8, x10, x1, x4) + +inst_1048: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0b9 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3e6 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0aa and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70b9; op2val:0xbbe6; +op3val:0x70aa; valaddr_reg:x8; val_offset:3072*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3072*FLEN/8, x10, x1, x4) + +inst_1049: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0b9 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3e6 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0aa and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70b9; op2val:0xbbe6; +op3val:0x70aa; valaddr_reg:x8; val_offset:3075*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3075*FLEN/8, x10, x1, x4) + +inst_1050: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ac and fs2 == 1 and fe2 == 0x0f and fm2 == 0x15d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x39b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79ac; op2val:0xbd5d; +op3val:0x7b9b; valaddr_reg:x8; val_offset:3078*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3078*FLEN/8, x10, x1, x4) + +inst_1051: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ac and fs2 == 1 and fe2 == 0x0f and fm2 == 0x15d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x39b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79ac; op2val:0xbd5d; +op3val:0x7b9b; valaddr_reg:x8; val_offset:3081*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3081*FLEN/8, x10, x1, x4) + +inst_1052: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ac and fs2 == 1 and fe2 == 0x0f and fm2 == 0x15d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x39b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79ac; op2val:0xbd5d; +op3val:0x7b9b; valaddr_reg:x8; val_offset:3084*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3084*FLEN/8, x10, x1, x4) + +inst_1053: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ac and fs2 == 1 and fe2 == 0x0f and fm2 == 0x15d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x39b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79ac; op2val:0xbd5d; +op3val:0x7b9b; valaddr_reg:x8; val_offset:3087*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3087*FLEN/8, x10, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_10) + +inst_1054: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ac and fs2 == 1 and fe2 == 0x0f and fm2 == 0x15d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x39b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79ac; op2val:0xbd5d; +op3val:0x7b9b; valaddr_reg:x8; val_offset:3090*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3090*FLEN/8, x10, x1, x4) + +inst_1055: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x151 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x02a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x189 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7951; op2val:0xb82a; +op3val:0x7589; valaddr_reg:x8; val_offset:3093*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3093*FLEN/8, x10, x1, x4) + +inst_1056: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x151 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x02a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x189 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7951; op2val:0xb82a; +op3val:0x7589; valaddr_reg:x8; val_offset:3096*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3096*FLEN/8, x10, x1, x4) + +inst_1057: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x151 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x02a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x189 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7951; op2val:0xb82a; +op3val:0x7589; valaddr_reg:x8; val_offset:3099*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3099*FLEN/8, x10, x1, x4) + +inst_1058: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x151 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x02a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x189 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7951; op2val:0xb82a; +op3val:0x7589; valaddr_reg:x8; val_offset:3102*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3102*FLEN/8, x10, x1, x4) + +inst_1059: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x151 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x02a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x189 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7951; op2val:0xb82a; +op3val:0x7589; valaddr_reg:x8; val_offset:3105*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3105*FLEN/8, x10, x1, x4) + +inst_1060: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c6 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x066 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x140 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78c6; op2val:0xbc66; +op3val:0x7940; valaddr_reg:x8; val_offset:3108*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3108*FLEN/8, x10, x1, x4) + +inst_1061: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c6 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x066 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x140 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78c6; op2val:0xbc66; +op3val:0x7940; valaddr_reg:x8; val_offset:3111*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3111*FLEN/8, x10, x1, x4) + +inst_1062: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c6 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x066 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x140 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78c6; op2val:0xbc66; +op3val:0x7940; valaddr_reg:x8; val_offset:3114*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3114*FLEN/8, x10, x1, x4) + +inst_1063: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c6 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x066 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x140 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78c6; op2val:0xbc66; +op3val:0x7940; valaddr_reg:x8; val_offset:3117*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3117*FLEN/8, x10, x1, x4) + +inst_1064: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c6 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x066 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x140 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78c6; op2val:0xbc66; +op3val:0x7940; valaddr_reg:x8; val_offset:3120*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3120*FLEN/8, x10, x1, x4) + +inst_1065: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x00b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x17c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x18c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x740b; op2val:0xc17c; +op3val:0x798c; valaddr_reg:x8; val_offset:3123*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3123*FLEN/8, x10, x1, x4) + +inst_1066: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x00b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x17c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x18c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x740b; op2val:0xc17c; +op3val:0x798c; valaddr_reg:x8; val_offset:3126*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3126*FLEN/8, x10, x1, x4) + +inst_1067: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x00b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x17c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x18c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x740b; op2val:0xc17c; +op3val:0x798c; valaddr_reg:x8; val_offset:3129*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3129*FLEN/8, x10, x1, x4) + +inst_1068: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x00b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x17c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x18c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x740b; op2val:0xc17c; +op3val:0x798c; valaddr_reg:x8; val_offset:3132*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3132*FLEN/8, x10, x1, x4) + +inst_1069: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x00b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x17c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x18c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x740b; op2val:0xc17c; +op3val:0x798c; valaddr_reg:x8; val_offset:3135*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3135*FLEN/8, x10, x1, x4) + +inst_1070: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x25e and fs2 == 1 and fe2 == 0x0c and fm2 == 0x076 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x31b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x725e; op2val:0xb076; +op3val:0x671b; valaddr_reg:x8; val_offset:3138*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3138*FLEN/8, x10, x1, x4) + +inst_1071: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x25e and fs2 == 1 and fe2 == 0x0c and fm2 == 0x076 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x31b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x725e; op2val:0xb076; +op3val:0x671b; valaddr_reg:x8; val_offset:3141*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3141*FLEN/8, x10, x1, x4) + +inst_1072: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x25e and fs2 == 1 and fe2 == 0x0c and fm2 == 0x076 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x31b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x725e; op2val:0xb076; +op3val:0x671b; valaddr_reg:x8; val_offset:3144*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3144*FLEN/8, x10, x1, x4) + +inst_1073: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x25e and fs2 == 1 and fe2 == 0x0c and fm2 == 0x076 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x31b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x725e; op2val:0xb076; +op3val:0x671b; valaddr_reg:x8; val_offset:3147*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3147*FLEN/8, x10, x1, x4) + +inst_1074: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x25e and fs2 == 1 and fe2 == 0x0c and fm2 == 0x076 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x31b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x725e; op2val:0xb076; +op3val:0x671b; valaddr_reg:x8; val_offset:3150*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3150*FLEN/8, x10, x1, x4) + +inst_1075: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x01c and fs2 == 1 and fe2 == 0x11 and fm2 == 0x398 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3ce and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c1c; op2val:0xc798; +op3val:0x77ce; valaddr_reg:x8; val_offset:3153*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3153*FLEN/8, x10, x1, x4) + +inst_1076: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x01c and fs2 == 1 and fe2 == 0x11 and fm2 == 0x398 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3ce and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c1c; op2val:0xc798; +op3val:0x77ce; valaddr_reg:x8; val_offset:3156*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3156*FLEN/8, x10, x1, x4) + +inst_1077: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x01c and fs2 == 1 and fe2 == 0x11 and fm2 == 0x398 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3ce and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c1c; op2val:0xc798; +op3val:0x77ce; valaddr_reg:x8; val_offset:3159*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3159*FLEN/8, x10, x1, x4) + +inst_1078: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x01c and fs2 == 1 and fe2 == 0x11 and fm2 == 0x398 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3ce and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c1c; op2val:0xc798; +op3val:0x77ce; valaddr_reg:x8; val_offset:3162*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3162*FLEN/8, x10, x1, x4) + +inst_1079: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x01c and fs2 == 1 and fe2 == 0x11 and fm2 == 0x398 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3ce and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c1c; op2val:0xc798; +op3val:0x77ce; valaddr_reg:x8; val_offset:3165*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3165*FLEN/8, x10, x1, x4) + +inst_1080: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x190 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x12f and fs3 == 0 and fe3 == 0x1c and fm3 == 0x336 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7990; op2val:0xb52f; +op3val:0x7336; valaddr_reg:x8; val_offset:3168*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3168*FLEN/8, x10, x1, x4) + +inst_1081: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x190 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x12f and fs3 == 0 and fe3 == 0x1c and fm3 == 0x336 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7990; op2val:0xb52f; +op3val:0x7336; valaddr_reg:x8; val_offset:3171*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3171*FLEN/8, x10, x1, x4) + +inst_1082: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x190 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x12f and fs3 == 0 and fe3 == 0x1c and fm3 == 0x336 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7990; op2val:0xb52f; +op3val:0x7336; valaddr_reg:x8; val_offset:3174*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3174*FLEN/8, x10, x1, x4) + +inst_1083: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x190 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x12f and fs3 == 0 and fe3 == 0x1c and fm3 == 0x336 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7990; op2val:0xb52f; +op3val:0x7336; valaddr_reg:x8; val_offset:3177*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3177*FLEN/8, x10, x1, x4) + +inst_1084: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x190 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x12f and fs3 == 0 and fe3 == 0x1c and fm3 == 0x336 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7990; op2val:0xb52f; +op3val:0x7336; valaddr_reg:x8; val_offset:3180*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3180*FLEN/8, x10, x1, x4) + +inst_1085: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x258 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2fc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x18a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7658; op2val:0xbefc; +op3val:0x798a; valaddr_reg:x8; val_offset:3183*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3183*FLEN/8, x10, x1, x4) + +inst_1086: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x258 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2fc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x18a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7658; op2val:0xbefc; +op3val:0x798a; valaddr_reg:x8; val_offset:3186*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3186*FLEN/8, x10, x1, x4) + +inst_1087: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x258 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2fc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x18a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7658; op2val:0xbefc; +op3val:0x798a; valaddr_reg:x8; val_offset:3189*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3189*FLEN/8, x10, x1, x4) + +inst_1088: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x258 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2fc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x18a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7658; op2val:0xbefc; +op3val:0x798a; valaddr_reg:x8; val_offset:3192*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3192*FLEN/8, x10, x1, x4) + +inst_1089: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x258 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2fc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x18a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7658; op2val:0xbefc; +op3val:0x798a; valaddr_reg:x8; val_offset:3195*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3195*FLEN/8, x10, x1, x4) + +inst_1090: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x035 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3f0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x02d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7435; op2val:0xbff0; +op3val:0x782d; valaddr_reg:x8; val_offset:3198*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3198*FLEN/8, x10, x1, x4) + +inst_1091: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x035 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3f0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x02d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7435; op2val:0xbff0; +op3val:0x782d; valaddr_reg:x8; val_offset:3201*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3201*FLEN/8, x10, x1, x4) + +inst_1092: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x035 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3f0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x02d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7435; op2val:0xbff0; +op3val:0x782d; valaddr_reg:x8; val_offset:3204*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3204*FLEN/8, x10, x1, x4) + +inst_1093: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x035 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3f0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x02d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7435; op2val:0xbff0; +op3val:0x782d; valaddr_reg:x8; val_offset:3207*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3207*FLEN/8, x10, x1, x4) + +inst_1094: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x035 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3f0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x02d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7435; op2val:0xbff0; +op3val:0x782d; valaddr_reg:x8; val_offset:3210*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3210*FLEN/8, x10, x1, x4) + +inst_1095: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d2 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x163 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x27e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78d2; op2val:0xb963; +op3val:0x767e; valaddr_reg:x8; val_offset:3213*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3213*FLEN/8, x10, x1, x4) + +inst_1096: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d2 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x163 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x27e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78d2; op2val:0xb963; +op3val:0x767e; valaddr_reg:x8; val_offset:3216*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3216*FLEN/8, x10, x1, x4) + +inst_1097: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d2 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x163 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x27e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78d2; op2val:0xb963; +op3val:0x767e; valaddr_reg:x8; val_offset:3219*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3219*FLEN/8, x10, x1, x4) + +inst_1098: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d2 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x163 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x27e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78d2; op2val:0xb963; +op3val:0x767e; valaddr_reg:x8; val_offset:3222*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3222*FLEN/8, x10, x1, x4) + +inst_1099: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d2 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x163 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x27e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78d2; op2val:0xb963; +op3val:0x767e; valaddr_reg:x8; val_offset:3225*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3225*FLEN/8, x10, x1, x4) + +inst_1100: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2aa and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2a5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x189 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72aa; op2val:0xc2a5; +op3val:0x7989; valaddr_reg:x8; val_offset:3228*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3228*FLEN/8, x10, x1, x4) + +inst_1101: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2aa and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2a5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x189 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72aa; op2val:0xc2a5; +op3val:0x7989; valaddr_reg:x8; val_offset:3231*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3231*FLEN/8, x10, x1, x4) + +inst_1102: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2aa and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2a5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x189 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72aa; op2val:0xc2a5; +op3val:0x7989; valaddr_reg:x8; val_offset:3234*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3234*FLEN/8, x10, x1, x4) + +inst_1103: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2aa and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2a5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x189 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72aa; op2val:0xc2a5; +op3val:0x7989; valaddr_reg:x8; val_offset:3237*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3237*FLEN/8, x10, x1, x4) + +inst_1104: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2aa and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2a5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x189 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72aa; op2val:0xc2a5; +op3val:0x7989; valaddr_reg:x8; val_offset:3240*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3240*FLEN/8, x10, x1, x4) + +inst_1105: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x050 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x20b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x799b; op2val:0xb450; +op3val:0x720b; valaddr_reg:x8; val_offset:3243*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3243*FLEN/8, x10, x1, x4) + +inst_1106: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x050 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x20b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x799b; op2val:0xb450; +op3val:0x720b; valaddr_reg:x8; val_offset:3246*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3246*FLEN/8, x10, x1, x4) + +inst_1107: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x050 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x20b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x799b; op2val:0xb450; +op3val:0x720b; valaddr_reg:x8; val_offset:3249*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3249*FLEN/8, x10, x1, x4) + +inst_1108: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x050 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x20b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x799b; op2val:0xb450; +op3val:0x720b; valaddr_reg:x8; val_offset:3252*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3252*FLEN/8, x10, x1, x4) + +inst_1109: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x050 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x20b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x799b; op2val:0xb450; +op3val:0x720b; valaddr_reg:x8; val_offset:3255*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3255*FLEN/8, x10, x1, x4) + +inst_1110: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x274 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x27e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x13d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a74; op2val:0xba7e; +op3val:0x793d; valaddr_reg:x8; val_offset:3258*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3258*FLEN/8, x10, x1, x4) + +inst_1111: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x274 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x27e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x13d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a74; op2val:0xba7e; +op3val:0x793d; valaddr_reg:x8; val_offset:3261*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3261*FLEN/8, x10, x1, x4) + +inst_1112: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x274 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x27e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x13d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a74; op2val:0xba7e; +op3val:0x793d; valaddr_reg:x8; val_offset:3264*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3264*FLEN/8, x10, x1, x4) + +inst_1113: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x274 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x27e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x13d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a74; op2val:0xba7e; +op3val:0x793d; valaddr_reg:x8; val_offset:3267*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3267*FLEN/8, x10, x1, x4) + +inst_1114: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x274 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x27e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x13d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a74; op2val:0xba7e; +op3val:0x793d; valaddr_reg:x8; val_offset:3270*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3270*FLEN/8, x10, x1, x4) + +inst_1115: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ed and fs2 == 1 and fe2 == 0x0e and fm2 == 0x334 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x23d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aed; op2val:0xbb34; +op3val:0x7a3d; valaddr_reg:x8; val_offset:3273*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3273*FLEN/8, x10, x1, x4) + +inst_1116: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ed and fs2 == 1 and fe2 == 0x0e and fm2 == 0x334 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x23d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aed; op2val:0xbb34; +op3val:0x7a3d; valaddr_reg:x8; val_offset:3276*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3276*FLEN/8, x10, x1, x4) + +inst_1117: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ed and fs2 == 1 and fe2 == 0x0e and fm2 == 0x334 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x23d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aed; op2val:0xbb34; +op3val:0x7a3d; valaddr_reg:x8; val_offset:3279*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3279*FLEN/8, x10, x1, x4) + +inst_1118: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ed and fs2 == 1 and fe2 == 0x0e and fm2 == 0x334 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x23d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aed; op2val:0xbb34; +op3val:0x7a3d; valaddr_reg:x8; val_offset:3282*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3282*FLEN/8, x10, x1, x4) + +inst_1119: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ed and fs2 == 1 and fe2 == 0x0e and fm2 == 0x334 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x23d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aed; op2val:0xbb34; +op3val:0x7a3d; valaddr_reg:x8; val_offset:3285*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3285*FLEN/8, x10, x1, x4) + +inst_1120: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x340 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x03e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7340; op2val:0xc43e; +op3val:0x7bb1; valaddr_reg:x8; val_offset:3288*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3288*FLEN/8, x10, x1, x4) + +inst_1121: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x340 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x03e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7340; op2val:0xc43e; +op3val:0x7bb1; valaddr_reg:x8; val_offset:3291*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3291*FLEN/8, x10, x1, x4) + +inst_1122: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x340 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x03e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7340; op2val:0xc43e; +op3val:0x7bb1; valaddr_reg:x8; val_offset:3294*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3294*FLEN/8, x10, x1, x4) + +inst_1123: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x00a and fs2 == 1 and fe2 == 0x11 and fm2 == 0x194 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x700a; op2val:0xc594; +op3val:0x79a2; valaddr_reg:x8; val_offset:3297*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3297*FLEN/8, x10, x1, x4) + +inst_1124: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x00a and fs2 == 1 and fe2 == 0x11 and fm2 == 0x194 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x700a; op2val:0xc594; +op3val:0x79a2; valaddr_reg:x8; val_offset:3300*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3300*FLEN/8, x10, x1, x4) + +inst_1125: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x00a and fs2 == 1 and fe2 == 0x11 and fm2 == 0x194 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x700a; op2val:0xc594; +op3val:0x79a2; valaddr_reg:x8; val_offset:3303*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3303*FLEN/8, x10, x1, x4) + +inst_1126: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x00a and fs2 == 1 and fe2 == 0x11 and fm2 == 0x194 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x700a; op2val:0xc594; +op3val:0x79a2; valaddr_reg:x8; val_offset:3306*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3306*FLEN/8, x10, x1, x4) + +inst_1127: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x173 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1cf and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3ea and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d73; op2val:0xc1cf; +op3val:0x73ea; valaddr_reg:x8; val_offset:3309*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3309*FLEN/8, x10, x1, x4) + +inst_1128: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x173 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1cf and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3ea and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d73; op2val:0xc1cf; +op3val:0x73ea; valaddr_reg:x8; val_offset:3312*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3312*FLEN/8, x10, x1, x4) + +inst_1129: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3fd and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2b4 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2b2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bfd; op2val:0xb2b4; +op3val:0x72b2; valaddr_reg:x8; val_offset:3315*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3315*FLEN/8, x10, x1, x4) + +inst_1130: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x33f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x05e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3ea and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x773f; op2val:0xbc5e; +op3val:0x77ea; valaddr_reg:x8; val_offset:3318*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3318*FLEN/8, x10, x1, x4) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(29504,32,FLEN) +NAN_BOXED(29504,16,FLEN) +NAN_BOXED(31665,32,FLEN) +NAN_BOXED(29504,32,FLEN) +NAN_BOXED(50238,16,FLEN) +NAN_BOXED(31665,32,FLEN) +NAN_BOXED(29504,32,FLEN) +NAN_BOXED(50238,16,FLEN) +NAN_BOXED(31665,32,FLEN) +NAN_BOXED(29504,32,FLEN) +NAN_BOXED(50238,16,FLEN) +NAN_BOXED(29504,32,FLEN) +NAN_BOXED(29504,32,FLEN) +NAN_BOXED(29504,16,FLEN) +NAN_BOXED(29504,32,FLEN) +NAN_BOXED(28682,32,FLEN) +NAN_BOXED(50580,16,FLEN) +NAN_BOXED(31138,32,FLEN) +NAN_BOXED(28682,32,FLEN) +NAN_BOXED(50580,16,FLEN) +NAN_BOXED(50580,32,FLEN) +NAN_BOXED(28682,32,FLEN) +NAN_BOXED(50580,16,FLEN) +NAN_BOXED(28682,32,FLEN) +NAN_BOXED(28682,32,FLEN) +NAN_BOXED(28682,16,FLEN) +NAN_BOXED(28682,32,FLEN) +NAN_BOXED(28682,32,FLEN) +NAN_BOXED(28682,16,FLEN) +NAN_BOXED(31138,32,FLEN) +NAN_BOXED(28019,32,FLEN) +NAN_BOXED(49615,16,FLEN) +NAN_BOXED(29674,32,FLEN) +NAN_BOXED(28019,32,FLEN) +NAN_BOXED(49615,16,FLEN) +NAN_BOXED(49615,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(49615,16,FLEN) +NAN_BOXED(29674,32,FLEN) +test_dataset_1: +NAN_BOXED(28019,32,FLEN) +NAN_BOXED(49615,16,FLEN) +NAN_BOXED(29674,32,FLEN) +NAN_BOXED(28019,32,FLEN) +NAN_BOXED(49615,16,FLEN) +NAN_BOXED(29674,32,FLEN) +NAN_BOXED(31741,32,FLEN) +NAN_BOXED(45748,16,FLEN) +NAN_BOXED(29362,32,FLEN) +NAN_BOXED(31741,32,FLEN) +NAN_BOXED(45748,16,FLEN) +NAN_BOXED(29362,32,FLEN) +NAN_BOXED(31741,32,FLEN) +NAN_BOXED(45748,16,FLEN) +NAN_BOXED(29362,32,FLEN) +NAN_BOXED(31741,32,FLEN) +NAN_BOXED(45748,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31741,32,FLEN) +NAN_BOXED(45748,16,FLEN) +NAN_BOXED(29362,32,FLEN) +NAN_BOXED(31009,32,FLEN) +NAN_BOXED(47544,16,FLEN) +NAN_BOXED(30551,32,FLEN) +NAN_BOXED(31009,32,FLEN) +NAN_BOXED(47544,16,FLEN) +NAN_BOXED(30551,32,FLEN) +NAN_BOXED(31009,32,FLEN) +NAN_BOXED(47544,16,FLEN) +NAN_BOXED(30551,32,FLEN) +NAN_BOXED(31009,32,FLEN) +NAN_BOXED(47544,16,FLEN) +NAN_BOXED(30551,32,FLEN) +test_dataset_2: +NAN_BOXED(31009,16,FLEN) +NAN_BOXED(47544,16,FLEN) +NAN_BOXED(30551,16,FLEN) +NAN_BOXED(30527,16,FLEN) +NAN_BOXED(48222,16,FLEN) +NAN_BOXED(30698,16,FLEN) +NAN_BOXED(30527,16,FLEN) +NAN_BOXED(48222,16,FLEN) +NAN_BOXED(30698,16,FLEN) +NAN_BOXED(30527,16,FLEN) +NAN_BOXED(48222,16,FLEN) +NAN_BOXED(30698,16,FLEN) +NAN_BOXED(30527,16,FLEN) +NAN_BOXED(48222,16,FLEN) +NAN_BOXED(30698,16,FLEN) +NAN_BOXED(30527,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(30698,16,FLEN) +NAN_BOXED(29222,16,FLEN) +NAN_BOXED(50257,16,FLEN) +NAN_BOXED(31396,16,FLEN) +NAN_BOXED(29222,16,FLEN) +NAN_BOXED(50257,16,FLEN) +NAN_BOXED(31396,16,FLEN) +NAN_BOXED(29222,16,FLEN) +NAN_BOXED(50257,16,FLEN) +NAN_BOXED(31396,16,FLEN) +NAN_BOXED(29222,16,FLEN) +NAN_BOXED(50257,16,FLEN) +NAN_BOXED(31396,16,FLEN) +NAN_BOXED(29222,16,FLEN) +NAN_BOXED(50257,16,FLEN) +NAN_BOXED(31396,16,FLEN) +NAN_BOXED(28090,16,FLEN) +NAN_BOXED(49466,16,FLEN) +NAN_BOXED(29565,16,FLEN) +NAN_BOXED(28090,16,FLEN) +NAN_BOXED(49466,16,FLEN) +NAN_BOXED(29565,16,FLEN) +NAN_BOXED(28090,16,FLEN) +NAN_BOXED(49466,16,FLEN) +NAN_BOXED(29565,16,FLEN) +NAN_BOXED(28090,16,FLEN) +NAN_BOXED(49466,16,FLEN) +NAN_BOXED(29565,16,FLEN) +NAN_BOXED(28090,16,FLEN) +NAN_BOXED(49466,16,FLEN) +NAN_BOXED(29565,16,FLEN) +NAN_BOXED(25886,16,FLEN) +NAN_BOXED(51882,16,FLEN) +NAN_BOXED(29764,16,FLEN) +NAN_BOXED(25886,16,FLEN) +NAN_BOXED(51882,16,FLEN) +NAN_BOXED(29764,16,FLEN) +NAN_BOXED(25886,16,FLEN) +NAN_BOXED(51882,16,FLEN) +NAN_BOXED(29764,16,FLEN) +NAN_BOXED(25886,16,FLEN) +NAN_BOXED(51882,16,FLEN) +NAN_BOXED(29764,16,FLEN) +NAN_BOXED(25886,16,FLEN) +NAN_BOXED(51882,16,FLEN) +NAN_BOXED(29764,16,FLEN) +NAN_BOXED(30341,16,FLEN) +NAN_BOXED(49260,16,FLEN) +NAN_BOXED(31542,16,FLEN) +NAN_BOXED(30341,16,FLEN) +NAN_BOXED(49260,16,FLEN) +NAN_BOXED(31542,16,FLEN) +NAN_BOXED(30341,16,FLEN) +NAN_BOXED(49260,16,FLEN) +NAN_BOXED(31542,16,FLEN) +NAN_BOXED(30341,16,FLEN) +NAN_BOXED(49260,16,FLEN) +NAN_BOXED(31542,16,FLEN) +NAN_BOXED(30341,16,FLEN) +NAN_BOXED(49260,16,FLEN) +NAN_BOXED(31542,16,FLEN) +NAN_BOXED(30223,16,FLEN) +NAN_BOXED(46285,16,FLEN) +NAN_BOXED(28486,16,FLEN) +NAN_BOXED(30223,16,FLEN) +NAN_BOXED(46285,16,FLEN) +NAN_BOXED(28486,16,FLEN) +NAN_BOXED(30223,16,FLEN) +NAN_BOXED(46285,16,FLEN) +NAN_BOXED(28486,16,FLEN) +NAN_BOXED(30223,16,FLEN) +NAN_BOXED(46285,16,FLEN) +NAN_BOXED(28486,16,FLEN) +NAN_BOXED(30223,16,FLEN) +NAN_BOXED(46285,16,FLEN) +NAN_BOXED(28486,16,FLEN) +NAN_BOXED(29729,16,FLEN) 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+NAN_BOXED(47924,16,FLEN) +NAN_BOXED(31293,16,FLEN) +NAN_BOXED(29504,16,FLEN) +NAN_BOXED(50238,16,FLEN) +NAN_BOXED(31665,16,FLEN) +NAN_BOXED(29504,16,FLEN) +NAN_BOXED(50238,16,FLEN) +NAN_BOXED(31665,16,FLEN) +NAN_BOXED(29504,16,FLEN) +NAN_BOXED(50238,16,FLEN) +NAN_BOXED(31665,16,FLEN) +NAN_BOXED(28682,16,FLEN) +NAN_BOXED(50580,16,FLEN) +NAN_BOXED(31138,16,FLEN) +NAN_BOXED(28682,16,FLEN) +NAN_BOXED(50580,16,FLEN) +NAN_BOXED(31138,16,FLEN) +NAN_BOXED(28682,16,FLEN) +NAN_BOXED(50580,16,FLEN) +NAN_BOXED(31138,16,FLEN) +NAN_BOXED(28682,16,FLEN) +NAN_BOXED(50580,16,FLEN) +NAN_BOXED(31138,16,FLEN) +NAN_BOXED(28019,16,FLEN) +NAN_BOXED(49615,16,FLEN) +NAN_BOXED(29674,16,FLEN) +NAN_BOXED(28019,16,FLEN) +NAN_BOXED(49615,16,FLEN) +NAN_BOXED(29674,16,FLEN) +NAN_BOXED(31741,16,FLEN) +NAN_BOXED(45748,16,FLEN) +NAN_BOXED(29362,16,FLEN) +NAN_BOXED(30527,16,FLEN) +NAN_BOXED(48222,16,FLEN) +NAN_BOXED(30698,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x3_0: + .fill 32*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_2: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_3: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_4: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_5: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_6: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_7: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_8: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_9: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_10: + .fill 154*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fnmsub_b4-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fnmsub_b4-01.S new file mode 100644 index 000000000..78b3c492c --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fnmsub_b4-01.S @@ -0,0 +1,1626 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 06:07:02 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fnmsub.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fnmsub.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fnmsub_b4 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fnmsub_b4) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x4,test_dataset_0) +RVTEST_SIGBASE(x19,signature_x19_1) + +inst_0: +// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==x25, rs2==x25, rs3==x14, rd==x17,fs1 == 0 and fe1 == 0x1c and fm1 == 0x340 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x053 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x25; op2:x25; op3:x14; dest:x17; op1val:0x7340; op2val:0x7340; +op3val:0x7bb1; valaddr_reg:x4; val_offset:0*FLEN/8; rmval:dyn; +testreg:x21; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x17, x25, x25, x14, dyn, 0, 0, x4, 0*FLEN/8, x7, x19, x21) + +inst_1: +// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==x0, rs2==x20, rs3==x18, rd==x0,fs1 == 0 and fe1 == 0x1c and fm1 == 0x340 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x053 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x0; op2:x20; op3:x18; dest:x0; op1val:0x0; op2val:0xc853; +op3val:0x7bb1; valaddr_reg:x4; val_offset:3*FLEN/8; rmval:dyn; +testreg:x21; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x0, x0, x20, x18, dyn, 32, 0, x4, 3*FLEN/8, x7, x19, x21) + +inst_2: +// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==x27, rs2==x30, rs3==x5, rd==x2,fs1 == 0 and fe1 == 0x1c and fm1 == 0x340 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x053 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x27; op2:x30; op3:x5; dest:x2; op1val:0x7340; op2val:0xc853; +op3val:0x7bb1; valaddr_reg:x4; val_offset:6*FLEN/8; rmval:dyn; +testreg:x21; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x2, x27, x30, x5, dyn, 64, 0, x4, 6*FLEN/8, x7, x19, x21) + +inst_3: +// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==x1, rs2==x5, rs3==x1, rd==x22,fs1 == 0 and fe1 == 0x1c and fm1 == 0x340 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x053 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x1; op2:x5; op3:x1; dest:x22; op1val:0x7340; op2val:0xc853; +op3val:0x7340; valaddr_reg:x4; val_offset:9*FLEN/8; rmval:dyn; +testreg:x21; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x22, x1, x5, x1, dyn, 96, 0, x4, 9*FLEN/8, x7, x19, x21) + +inst_4: +// rs1 == rs2 == rs3 != rd, rs1==x9, rs2==x9, rs3==x9, rd==x26,fs1 == 0 and fe1 == 0x1c and fm1 == 0x340 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x053 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x9; op2:x9; op3:x9; dest:x26; op1val:0x7340; op2val:0x7340; +op3val:0x7340; valaddr_reg:x4; val_offset:12*FLEN/8; rmval:dyn; +testreg:x21; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x26, x9, x9, x9, dyn, 128, 0, x4, 12*FLEN/8, x7, x19, x21) + +inst_5: +// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==x11, rs2==x15, rs3==x25, rd==x25,fs1 == 0 and fe1 == 0x1c and fm1 == 0x00a and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0ac and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x11; op2:x15; op3:x25; dest:x25; op1val:0x700a; op2val:0x40ac; +op3val:0x79a2; valaddr_reg:x4; val_offset:15*FLEN/8; rmval:dyn; +testreg:x21; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x25, x11, x15, x25, dyn, 0, 0, x4, 15*FLEN/8, x7, x19, x21) + +inst_6: +// rd == rs2 == rs3 != rs1, rs1==x6, rs2==x10, rs3==x10, rd==x10,fs1 == 0 and fe1 == 0x1c and fm1 == 0x00a and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0ac and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x6; op2:x10; op3:x10; dest:x10; op1val:0x700a; op2val:0x40ac; +op3val:0x40ac; valaddr_reg:x4; val_offset:18*FLEN/8; rmval:dyn; +testreg:x21; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x10, x6, x10, x10, dyn, 32, 0, x4, 18*FLEN/8, x7, x19, x21) + +inst_7: +// rs1 == rd == rs3 != rs2, rs1==x15, rs2==x29, rs3==x15, rd==x15,fs1 == 0 and fe1 == 0x1c and fm1 == 0x00a and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0ac and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x15; op2:x29; op3:x15; dest:x15; op1val:0x700a; op2val:0x40ac; +op3val:0x700a; valaddr_reg:x4; val_offset:21*FLEN/8; rmval:dyn; +testreg:x21; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x15, x15, x29, x15, dyn, 64, 0, x4, 21*FLEN/8, x7, x19, x21) + +inst_8: +// rs1 == rs2 == rs3 == rd, rs1==x8, rs2==x8, rs3==x8, rd==x8,fs1 == 0 and fe1 == 0x1c and fm1 == 0x00a and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0ac and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x8; op2:x8; op3:x8; dest:x8; op1val:0x700a; op2val:0x700a; +op3val:0x700a; valaddr_reg:x4; val_offset:24*FLEN/8; rmval:dyn; +testreg:x21; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x8, x8, x8, x8, dyn, 96, 0, x4, 24*FLEN/8, x7, x19, x21) + +inst_9: +// rs1 == rs2 == rd != rs3, rs1==x16, rs2==x16, rs3==x26, rd==x16,fs1 == 0 and fe1 == 0x1c and fm1 == 0x00a and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0ac and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x16; op2:x16; op3:x26; dest:x16; op1val:0x700a; op2val:0x700a; +op3val:0x79a2; valaddr_reg:x4; val_offset:27*FLEN/8; rmval:dyn; +testreg:x21; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x16, x16, x16, x26, dyn, 128, 0, x4, 27*FLEN/8, x7, x19, x21) + +inst_10: +// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==x14, rs2==x18, rs3==x6, rd==x18,fs1 == 0 and fe1 == 0x1b and fm1 == 0x173 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x352 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3ea and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x14; op2:x18; op3:x6; dest:x18; op1val:0x6d73; op2val:0xcb52; +op3val:0x73ea; valaddr_reg:x4; val_offset:30*FLEN/8; rmval:dyn; +testreg:x21; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x18, x14, x18, x6, dyn, 0, 0, x4, 30*FLEN/8, x7, x19, x21) + +inst_11: +// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==x3, rs2==x17, rs3==x17, rd==x30,fs1 == 0 and fe1 == 0x1b and fm1 == 0x173 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x352 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3ea and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x3; op2:x17; op3:x17; dest:x30; op1val:0x6d73; op2val:0xcb52; +op3val:0xcb52; valaddr_reg:x4; val_offset:33*FLEN/8; rmval:dyn; +testreg:x21; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x30, x3, x17, x17, dyn, 32, 0, x4, 33*FLEN/8, x7, x19, x21) + +inst_12: +// rs1==x13, rs2==x12, rs3==x23, rd==x3,fs1 == 0 and fe1 == 0x1b and fm1 == 0x173 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x352 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3ea and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x13; op2:x12; op3:x23; dest:x3; op1val:0x6d73; op2val:0xcb52; +op3val:0x73ea; valaddr_reg:x4; val_offset:36*FLEN/8; rmval:dyn; +testreg:x21; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x3, x13, x12, x23, dyn, 64, 0, x4, 36*FLEN/8, x7, x19, x21) +RVTEST_VALBASEUPD(x13,test_dataset_1) + +inst_13: +// rs1==x7, rs2==x0, rs3==x11, rd==x4,fs1 == 0 and fe1 == 0x1b and fm1 == 0x173 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x352 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3ea and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x7; op2:x0; op3:x11; dest:x4; op1val:0x6d73; op2val:0x0; +op3val:0x73ea; valaddr_reg:x13; val_offset:0*FLEN/8; rmval:dyn; +testreg:x21; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x4, x7, x0, x11, dyn, 96, 0, x13, 0*FLEN/8, x15, x19, x21) +RVTEST_SIGBASE(x8,signature_x8_0) + +inst_14: +// rs1==x30, rs2==x24, rs3==x21, rd==x7,fs1 == 0 and fe1 == 0x1b and fm1 == 0x173 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x352 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3ea and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x24; op3:x21; dest:x7; op1val:0x6d73; op2val:0xcb52; +op3val:0x73ea; valaddr_reg:x13; val_offset:3*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x7, x30, x24, x21, dyn, 128, 0, x13, 3*FLEN/8, x15, x8, x9) + +inst_15: +// rs1==x31, rs2==x26, rs3==x13, rd==x19,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3fd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x254 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2b2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x31; op2:x26; op3:x13; dest:x19; op1val:0x7bfd; op2val:0x3a54; +op3val:0x72b2; valaddr_reg:x13; val_offset:6*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x19, x31, x26, x13, dyn, 0, 0, x13, 6*FLEN/8, x15, x8, x9) + +inst_16: +// rs1==x19, rs2==x11, rs3==x3, rd==x21,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3fd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x254 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2b2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x19; op2:x11; op3:x3; dest:x21; op1val:0x7bfd; op2val:0x3a54; +op3val:0x72b2; valaddr_reg:x13; val_offset:9*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x21, x19, x11, x3, dyn, 32, 0, x13, 9*FLEN/8, x15, x8, x9) + +inst_17: +// rs1==x10, rs2==x2, rs3==x27, rd==x6,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3fd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x254 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2b2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x10; op2:x2; op3:x27; dest:x6; op1val:0x7bfd; op2val:0x3a54; +op3val:0x72b2; valaddr_reg:x13; val_offset:12*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x6, x10, x2, x27, dyn, 64, 0, x13, 12*FLEN/8, x15, x8, x9) + +inst_18: +// rs1==x22, rs2==x31, rs3==x16, rd==x29,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3fd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x254 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2b2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x22; op2:x31; op3:x16; dest:x29; op1val:0x7bfd; op2val:0x3a54; +op3val:0x72b2; valaddr_reg:x13; val_offset:15*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x29, x22, x31, x16, dyn, 96, 0, x13, 15*FLEN/8, x15, x8, x9) + +inst_19: +// rs1==x23, rs2==x1, rs3==x2, rd==x27,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3fd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x254 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2b2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x23; op2:x1; op3:x2; dest:x27; op1val:0x7bfd; op2val:0x3a54; +op3val:0x72b2; valaddr_reg:x13; val_offset:18*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x27, x23, x1, x2, dyn, 128, 0, x13, 18*FLEN/8, x15, x8, x9) + +inst_20: +// rs1==x5, rs2==x14, rs3==x22, rd==x24,fs1 == 0 and fe1 == 0x1e and fm1 == 0x121 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x08b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x357 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x5; op2:x14; op3:x22; dest:x24; op1val:0x7921; op2val:0xc08b; +op3val:0x7757; valaddr_reg:x13; val_offset:21*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x24, x5, x14, x22, dyn, 0, 0, x13, 21*FLEN/8, x15, x8, x9) + +inst_21: +// rs1==x18, rs2==x27, rs3==x24, rd==x5,fs1 == 0 and fe1 == 0x1e and fm1 == 0x121 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x08b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x357 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x18; op2:x27; op3:x24; dest:x5; op1val:0x7921; op2val:0xc08b; +op3val:0x7757; valaddr_reg:x13; val_offset:24*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x5, x18, x27, x24, dyn, 32, 0, x13, 24*FLEN/8, x15, x8, x9) + +inst_22: +// rs1==x12, rs2==x3, rs3==x28, rd==x14,fs1 == 0 and fe1 == 0x1e and fm1 == 0x121 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x08b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x357 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x12; op2:x3; op3:x28; dest:x14; op1val:0x7921; op2val:0xc08b; +op3val:0x7757; valaddr_reg:x13; val_offset:27*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x14, x12, x3, x28, dyn, 64, 0, x13, 27*FLEN/8, x15, x8, x9) +RVTEST_VALBASEUPD(x3,test_dataset_2) + +inst_23: +// rs1==x29, rs2==x7, rs3==x31, rd==x20,fs1 == 0 and fe1 == 0x1e and fm1 == 0x121 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x08b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x357 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x29; op2:x7; op3:x31; dest:x20; op1val:0x7921; op2val:0xc08b; +op3val:0x7757; valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x20, x29, x7, x31, dyn, 96, 0, x3, 0*FLEN/8, x5, x8, x9) + +inst_24: +// rs1==x2, rs2==x6, rs3==x30, rd==x1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x121 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x08b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x357 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x2; op2:x6; op3:x30; dest:x1; op1val:0x7921; op2val:0xc08b; +op3val:0x7757; valaddr_reg:x3; val_offset:3*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x1, x2, x6, x30, dyn, 128, 0, x3, 3*FLEN/8, x5, x8, x9) + +inst_25: +// rs1==x26, rs2==x23, rs3==x29, rd==x28,fs1 == 0 and fe1 == 0x1d and fm1 == 0x33f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x075 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3ea and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x26; op2:x23; op3:x29; dest:x28; op1val:0x773f; op2val:0x3c75; +op3val:0x77ea; valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x28, x26, x23, x29, dyn, 0, 0, x3, 6*FLEN/8, x5, x8, x9) + +inst_26: +// rs1==x4, rs2==x28, rs3==x20, rd==x11,fs1 == 0 and fe1 == 0x1d and fm1 == 0x33f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x075 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3ea and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x4; op2:x28; op3:x20; dest:x11; op1val:0x773f; op2val:0x3c75; +op3val:0x77ea; valaddr_reg:x3; val_offset:9*FLEN/8; rmval:dyn; +testreg:x9; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x11, x4, x28, x20, dyn, 32, 0, x3, 9*FLEN/8, x5, x8, x9) + +inst_27: +// rs1==x28, rs2==x22, rs3==x7, rd==x23,fs1 == 0 and fe1 == 0x1d and fm1 == 0x33f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x075 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3ea and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x28; op2:x22; op3:x7; dest:x23; op1val:0x773f; op2val:0x3c75; +op3val:0x77ea; valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x23, x28, x22, x7, dyn, 64, 0, x3, 12*FLEN/8, x5, x8, x2) + +inst_28: +// rs1==x24, rs2==x21, rs3==x4, rd==x12,fs1 == 0 and fe1 == 0x1d and fm1 == 0x33f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x075 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3ea and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x24; op2:x21; op3:x4; dest:x12; op1val:0x773f; op2val:0x3c75; +op3val:0x77ea; valaddr_reg:x3; val_offset:15*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x12, x24, x21, x4, dyn, 96, 0, x3, 15*FLEN/8, x5, x8, x2) + +inst_29: +// rs1==x17, rs2==x4, rs3==x0, rd==x13,fs1 == 0 and fe1 == 0x1d and fm1 == 0x33f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x075 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3ea and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x17; op2:x4; op3:x0; dest:x13; op1val:0x773f; op2val:0x3c75; +op3val:0x0; valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x13, x17, x4, x0, dyn, 128, 0, x3, 18*FLEN/8, x5, x8, x2) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_30: +// rs1==x21, rs2==x13, rs3==x12, rd==x31,fs1 == 0 and fe1 == 0x1c and fm1 == 0x226 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0c2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x21; op2:x13; op3:x12; dest:x31; op1val:0x7226; op2val:0xc8c2; +op3val:0x7aa4; valaddr_reg:x3; val_offset:21*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x21, x13, x12, dyn, 0, 0, x3, 21*FLEN/8, x5, x1, x2) + +inst_31: +// rs1==x20,fs1 == 0 and fe1 == 0x1c and fm1 == 0x226 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0c2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x20; op2:x0; op3:x7; dest:x19; op1val:0x7226; op2val:0x0; +op3val:0x7aa4; valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x19, x20, x0, x7, dyn, 32, 0, x3, 24*FLEN/8, x5, x1, x2) + +inst_32: +// rs2==x19,fs1 == 0 and fe1 == 0x1c and fm1 == 0x226 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0c2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x29; op2:x19; op3:x28; dest:x11; op1val:0x7226; op2val:0xc8c2; +op3val:0x7aa4; valaddr_reg:x3; val_offset:27*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x11, x29, x19, x28, dyn, 64, 0, x3, 27*FLEN/8, x5, x1, x2) + +inst_33: +// rs3==x19,fs1 == 0 and fe1 == 0x1c and fm1 == 0x226 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0c2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x27; op2:x20; op3:x19; dest:x14; op1val:0x7226; op2val:0xc8c2; +op3val:0x7aa4; valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x14, x27, x20, x19, dyn, 96, 0, x3, 30*FLEN/8, x5, x1, x2) + +inst_34: +// rd==x9,fs1 == 0 and fe1 == 0x1c and fm1 == 0x226 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0c2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x19; op2:x7; op3:x5; dest:x9; op1val:0x7226; op2val:0xc8c2; +op3val:0x7aa4; valaddr_reg:x3; val_offset:33*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x9, x19, x7, x5, dyn, 128, 0, x3, 33*FLEN/8, x5, x1, x2) + +inst_35: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ba and fs2 == 0 and fe2 == 0x12 and fm2 == 0x046 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x37d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dba; op2val:0x4846; +op3val:0x737d; valaddr_reg:x3; val_offset:36*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 36*FLEN/8, x5, x1, x2) +RVTEST_VALBASEUPD(x3,test_dataset_3) + +inst_36: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ba and fs2 == 0 and fe2 == 0x12 and fm2 == 0x046 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x37d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dba; op2val:0x4846; +op3val:0x737d; valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_37: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ba and fs2 == 0 and fe2 == 0x12 and fm2 == 0x046 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x37d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dba; op2val:0x4846; +op3val:0x737d; valaddr_reg:x3; val_offset:3*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_38: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ba and fs2 == 0 and fe2 == 0x12 and fm2 == 0x046 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x37d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dba; op2val:0x4846; +op3val:0x737d; valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_39: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ba and fs2 == 0 and fe2 == 0x12 and fm2 == 0x046 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x37d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dba; op2val:0x4846; +op3val:0x737d; valaddr_reg:x3; val_offset:9*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_40: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x11e and fs2 == 1 and fe2 == 0x14 and fm2 == 0x3ea and fs3 == 0 and fe3 == 0x1d and fm3 == 0x044 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x651e; op2val:0xd3ea; +op3val:0x7444; valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_41: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x11e and fs2 == 1 and fe2 == 0x14 and fm2 == 0x3ea and fs3 == 0 and fe3 == 0x1d and fm3 == 0x044 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x651e; op2val:0xd3ea; +op3val:0x7444; valaddr_reg:x3; val_offset:15*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_42: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x11e and fs2 == 1 and fe2 == 0x14 and fm2 == 0x3ea and fs3 == 0 and fe3 == 0x1d and fm3 == 0x044 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x651e; op2val:0xd3ea; +op3val:0x7444; valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_43: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x11e and fs2 == 1 and fe2 == 0x14 and fm2 == 0x3ea and fs3 == 0 and fe3 == 0x1d and fm3 == 0x044 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x651e; op2val:0xd3ea; +op3val:0x7444; valaddr_reg:x3; val_offset:21*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_44: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x11e and fs2 == 1 and fe2 == 0x14 and fm2 == 0x3ea and fs3 == 0 and fe3 == 0x1d and fm3 == 0x044 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x651e; op2val:0xd3ea; +op3val:0x7444; valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_45: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x285 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3af and fs3 == 0 and fe3 == 0x1e and fm3 == 0x336 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7685; op2val:0x33af; +op3val:0x7b36; valaddr_reg:x3; val_offset:27*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_46: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x285 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3af and fs3 == 0 and fe3 == 0x1e and fm3 == 0x336 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7685; op2val:0x33af; +op3val:0x7b36; valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_47: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x285 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3af and fs3 == 0 and fe3 == 0x1e and fm3 == 0x336 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7685; op2val:0x33af; +op3val:0x7b36; valaddr_reg:x3; val_offset:33*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x3, 33*FLEN/8, x4, x1, x2) + +inst_48: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x285 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3af and fs3 == 0 and fe3 == 0x1e and fm3 == 0x336 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7685; op2val:0x33af; +op3val:0x7b36; valaddr_reg:x3; val_offset:36*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x3, 36*FLEN/8, x4, x1, x2) + +inst_49: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x285 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3af and fs3 == 0 and fe3 == 0x1e and fm3 == 0x336 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7685; op2val:0x33af; +op3val:0x7b36; valaddr_reg:x3; val_offset:39*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x3, 39*FLEN/8, x4, x1, x2) + +inst_50: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x20f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e0 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x346 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x760f; op2val:0xc1e0; +op3val:0x6f46; valaddr_reg:x3; val_offset:42*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 42*FLEN/8, x4, x1, x2) + +inst_51: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x20f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e0 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x346 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x760f; op2val:0xc1e0; +op3val:0x6f46; valaddr_reg:x3; val_offset:45*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x3, 45*FLEN/8, x4, x1, x2) + +inst_52: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x20f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e0 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x346 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x760f; op2val:0xc1e0; +op3val:0x6f46; valaddr_reg:x3; val_offset:48*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x3, 48*FLEN/8, x4, x1, x2) + +inst_53: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x20f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e0 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x346 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x760f; op2val:0xc1e0; +op3val:0x6f46; valaddr_reg:x3; val_offset:51*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x3, 51*FLEN/8, x4, x1, x2) + +inst_54: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x20f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e0 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x346 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x760f; op2val:0xc1e0; +op3val:0x6f46; valaddr_reg:x3; val_offset:54*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x3, 54*FLEN/8, x4, x1, x2) + +inst_55: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x021 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x029 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ed and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7421; op2val:0x2829; +op3val:0x7bed; valaddr_reg:x3; val_offset:57*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 57*FLEN/8, x4, x1, x2) + +inst_56: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x021 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x029 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ed and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7421; op2val:0x2829; +op3val:0x7bed; valaddr_reg:x3; val_offset:60*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x3, 60*FLEN/8, x4, x1, x2) + +inst_57: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x021 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x029 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ed and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7421; op2val:0x2829; +op3val:0x7bed; valaddr_reg:x3; val_offset:63*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x3, 63*FLEN/8, x4, x1, x2) + +inst_58: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x021 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x029 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ed and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7421; op2val:0x2829; +op3val:0x7bed; valaddr_reg:x3; val_offset:66*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x3, 66*FLEN/8, x4, x1, x2) + +inst_59: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x021 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x029 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ed and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7421; op2val:0x2829; +op3val:0x7bed; valaddr_reg:x3; val_offset:69*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x3, 69*FLEN/8, x4, x1, x2) + +inst_60: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x009 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x26b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0f5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c09; op2val:0xce6b; +op3val:0x78f5; valaddr_reg:x3; val_offset:72*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 72*FLEN/8, x4, x1, x2) + +inst_61: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x009 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x26b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0f5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c09; op2val:0xce6b; +op3val:0x78f5; valaddr_reg:x3; val_offset:75*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x3, 75*FLEN/8, x4, x1, x2) + +inst_62: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x009 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x26b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0f5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c09; op2val:0xce6b; +op3val:0x78f5; valaddr_reg:x3; val_offset:78*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x3, 78*FLEN/8, x4, x1, x2) + +inst_63: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x009 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x26b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0f5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c09; op2val:0xce6b; +op3val:0x78f5; valaddr_reg:x3; val_offset:81*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x3, 81*FLEN/8, x4, x1, x2) + +inst_64: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x009 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x26b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0f5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c09; op2val:0xce6b; +op3val:0x78f5; valaddr_reg:x3; val_offset:84*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x3, 84*FLEN/8, x4, x1, x2) + +inst_65: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x208 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x331 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x148 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7608; op2val:0x3b31; +op3val:0x7948; valaddr_reg:x3; val_offset:87*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 87*FLEN/8, x4, x1, x2) + +inst_66: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x208 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x331 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x148 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7608; op2val:0x3b31; +op3val:0x7948; valaddr_reg:x3; val_offset:90*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x3, 90*FLEN/8, x4, x1, x2) + +inst_67: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x208 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x331 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x148 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7608; op2val:0x3b31; +op3val:0x7948; valaddr_reg:x3; val_offset:93*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x3, 93*FLEN/8, x4, x1, x2) + +inst_68: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x208 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x331 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x148 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7608; op2val:0x3b31; +op3val:0x7948; valaddr_reg:x3; val_offset:96*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x3, 96*FLEN/8, x4, x1, x2) + +inst_69: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x208 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x331 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x148 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7608; op2val:0x3b31; +op3val:0x7948; valaddr_reg:x3; val_offset:99*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x3, 99*FLEN/8, x4, x1, x2) + +inst_70: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x169 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0d2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x187 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7569; op2val:0xc0d2; +op3val:0x7987; valaddr_reg:x3; val_offset:102*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 102*FLEN/8, x4, x1, x2) + +inst_71: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x169 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0d2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x187 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7569; op2val:0xc0d2; +op3val:0x7987; valaddr_reg:x3; val_offset:105*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x3, 105*FLEN/8, x4, x1, x2) + +inst_72: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x169 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0d2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x187 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7569; op2val:0xc0d2; +op3val:0x7987; valaddr_reg:x3; val_offset:108*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x3, 108*FLEN/8, x4, x1, x2) + +inst_73: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x169 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0d2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x187 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7569; op2val:0xc0d2; +op3val:0x7987; valaddr_reg:x3; val_offset:111*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x3, 111*FLEN/8, x4, x1, x2) + +inst_74: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x169 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0d2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x187 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7569; op2val:0xc0d2; +op3val:0x7987; valaddr_reg:x3; val_offset:114*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x3, 114*FLEN/8, x4, x1, x2) + +inst_75: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3f5 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x037 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x131 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77f5; op2val:0xbc37; +op3val:0x7931; valaddr_reg:x3; val_offset:117*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 117*FLEN/8, x4, x1, x2) + +inst_76: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3f5 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x037 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x131 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77f5; op2val:0xbc37; +op3val:0x7931; valaddr_reg:x3; val_offset:120*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x3, 120*FLEN/8, x4, x1, x2) + +inst_77: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3f5 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x037 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x131 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77f5; op2val:0xbc37; +op3val:0x7931; valaddr_reg:x3; val_offset:123*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x3, 123*FLEN/8, x4, x1, x2) + +inst_78: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3f5 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x037 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x131 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77f5; op2val:0xbc37; +op3val:0x7931; valaddr_reg:x3; val_offset:126*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x3, 126*FLEN/8, x4, x1, x2) + +inst_79: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3f5 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x037 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x131 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77f5; op2val:0xbc37; +op3val:0x7931; valaddr_reg:x3; val_offset:129*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x3, 129*FLEN/8, x4, x1, x2) + +inst_80: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x335 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x361 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b35; op2val:0xbb61; +op3val:0x78a6; valaddr_reg:x3; val_offset:132*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 132*FLEN/8, x4, x1, x2) + +inst_81: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x335 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x361 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b35; op2val:0xbb61; +op3val:0x78a6; valaddr_reg:x3; val_offset:135*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x3, 135*FLEN/8, x4, x1, x2) + +inst_82: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x335 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x361 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b35; op2val:0xbb61; +op3val:0x78a6; valaddr_reg:x3; val_offset:138*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x3, 138*FLEN/8, x4, x1, x2) + +inst_83: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x335 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x361 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b35; op2val:0xbb61; +op3val:0x78a6; valaddr_reg:x3; val_offset:141*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x3, 141*FLEN/8, x4, x1, x2) + +inst_84: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x335 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x361 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b35; op2val:0xbb61; +op3val:0x78a6; valaddr_reg:x3; val_offset:144*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x3, 144*FLEN/8, x4, x1, x2) + +inst_85: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x08b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x139 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x01e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x708b; op2val:0x3d39; +op3val:0x6c1e; valaddr_reg:x3; val_offset:147*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 147*FLEN/8, x4, x1, x2) + +inst_86: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x08b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x139 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x01e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x708b; op2val:0x3d39; +op3val:0x6c1e; valaddr_reg:x3; val_offset:150*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x3, 150*FLEN/8, x4, x1, x2) + +inst_87: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x08b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x139 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x01e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x708b; op2val:0x3d39; +op3val:0x6c1e; valaddr_reg:x3; val_offset:153*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x3, 153*FLEN/8, x4, x1, x2) + +inst_88: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x08b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x139 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x01e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x708b; op2val:0x3d39; +op3val:0x6c1e; valaddr_reg:x3; val_offset:156*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x3, 156*FLEN/8, x4, x1, x2) + +inst_89: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x08b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x139 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x01e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x708b; op2val:0x3d39; +op3val:0x6c1e; valaddr_reg:x3; val_offset:159*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x3, 159*FLEN/8, x4, x1, x2) + +inst_90: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x390 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x02e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3d0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b90; op2val:0xbc2e; +op3val:0x77d0; valaddr_reg:x3; val_offset:162*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 162*FLEN/8, x4, x1, x2) + +inst_91: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x390 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x02e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3d0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b90; op2val:0xbc2e; +op3val:0x77d0; valaddr_reg:x3; val_offset:165*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x3, 165*FLEN/8, x4, x1, x2) + +inst_92: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x390 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x02e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3d0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b90; op2val:0xbc2e; +op3val:0x77d0; valaddr_reg:x3; val_offset:168*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x3, 168*FLEN/8, x4, x1, x2) + +inst_93: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x390 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x02e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3d0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b90; op2val:0xbc2e; +op3val:0x77d0; valaddr_reg:x3; val_offset:171*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x3, 171*FLEN/8, x4, x1, x2) + +inst_94: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x390 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x02e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3d0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b90; op2val:0xbc2e; +op3val:0x77d0; valaddr_reg:x3; val_offset:174*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x3, 174*FLEN/8, x4, x1, x2) + +inst_95: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x233 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x09a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x390 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7233; op2val:0xc09a; +op3val:0x7b90; valaddr_reg:x3; val_offset:177*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 177*FLEN/8, x4, x1, x2) + +inst_96: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x233 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x09a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x390 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7233; op2val:0xc09a; +op3val:0x7b90; valaddr_reg:x3; val_offset:180*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x3, 180*FLEN/8, x4, x1, x2) + +inst_97: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x233 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x09a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x390 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7233; op2val:0xc09a; +op3val:0x7b90; valaddr_reg:x3; val_offset:183*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x3, 183*FLEN/8, x4, x1, x2) + +inst_98: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x233 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x09a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x390 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7233; op2val:0xc09a; +op3val:0x7b90; valaddr_reg:x3; val_offset:186*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x3, 186*FLEN/8, x4, x1, x2) + +inst_99: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x233 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x09a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x390 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7233; op2val:0xc09a; +op3val:0x7b90; valaddr_reg:x3; val_offset:189*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x3, 189*FLEN/8, x4, x1, x2) + +inst_100: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a1 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1f8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1d4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78a1; op2val:0xc1f8; +op3val:0x79d4; valaddr_reg:x3; val_offset:192*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 192*FLEN/8, x4, x1, x2) + +inst_101: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a1 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1f8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1d4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78a1; op2val:0xc1f8; +op3val:0x79d4; valaddr_reg:x3; val_offset:195*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x3, 195*FLEN/8, x4, x1, x2) + +inst_102: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a1 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1f8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1d4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78a1; op2val:0xc1f8; +op3val:0x79d4; valaddr_reg:x3; val_offset:198*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x3, 198*FLEN/8, x4, x1, x2) + +inst_103: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a1 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1f8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1d4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78a1; op2val:0xc1f8; +op3val:0x79d4; valaddr_reg:x3; val_offset:201*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x3, 201*FLEN/8, x4, x1, x2) + +inst_104: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a1 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1f8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1d4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78a1; op2val:0xc1f8; +op3val:0x79d4; valaddr_reg:x3; val_offset:204*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x3, 204*FLEN/8, x4, x1, x2) + +inst_105: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x27c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x091 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b0b; op2val:0x3a7c; +op3val:0x7491; valaddr_reg:x3; val_offset:207*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 207*FLEN/8, x4, x1, x2) + +inst_106: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x27c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x091 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b0b; op2val:0x3a7c; +op3val:0x7491; valaddr_reg:x3; val_offset:210*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x3, 210*FLEN/8, x4, x1, x2) + +inst_107: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x27c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x091 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b0b; op2val:0x3a7c; +op3val:0x7491; valaddr_reg:x3; val_offset:213*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x3, 213*FLEN/8, x4, x1, x2) + +inst_108: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x27c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x091 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b0b; op2val:0x3a7c; +op3val:0x7491; valaddr_reg:x3; val_offset:216*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x3, 216*FLEN/8, x4, x1, x2) + +inst_109: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x27c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x091 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b0b; op2val:0x3a7c; +op3val:0x7491; valaddr_reg:x3; val_offset:219*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x3, 219*FLEN/8, x4, x1, x2) + +inst_110: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1b4 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x008 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x305 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75b4; op2val:0xc808; +op3val:0x7b05; valaddr_reg:x3; val_offset:222*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 222*FLEN/8, x4, x1, x2) + +inst_111: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1b4 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x008 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x305 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75b4; op2val:0xc808; +op3val:0x7b05; valaddr_reg:x3; val_offset:225*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x3, 225*FLEN/8, x4, x1, x2) + +inst_112: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1b4 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x008 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x305 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75b4; op2val:0xc808; +op3val:0x7b05; valaddr_reg:x3; val_offset:228*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x3, 228*FLEN/8, x4, x1, x2) + +inst_113: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1b4 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x008 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x305 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75b4; op2val:0xc808; +op3val:0x7b05; valaddr_reg:x3; val_offset:231*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x3, 231*FLEN/8, x4, x1, x2) + +inst_114: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1b4 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x008 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x305 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75b4; op2val:0xc808; +op3val:0x7b05; valaddr_reg:x3; val_offset:234*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x3, 234*FLEN/8, x4, x1, x2) + +inst_115: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x051 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x093 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x21c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7051; op2val:0x4893; +op3val:0x7a1c; valaddr_reg:x3; val_offset:237*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 237*FLEN/8, x4, x1, x2) + +inst_116: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x051 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x093 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x21c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7051; op2val:0x4893; +op3val:0x7a1c; valaddr_reg:x3; val_offset:240*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x3, 240*FLEN/8, x4, x1, x2) + +inst_117: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x051 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x093 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x21c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7051; op2val:0x4893; +op3val:0x7a1c; valaddr_reg:x3; val_offset:243*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x3, 243*FLEN/8, x4, x1, x2) + +inst_118: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x051 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x093 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x21c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7051; op2val:0x4893; +op3val:0x7a1c; valaddr_reg:x3; val_offset:246*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x3, 246*FLEN/8, x4, x1, x2) + +inst_119: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x051 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x093 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x21c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7051; op2val:0x4893; +op3val:0x7a1c; valaddr_reg:x3; val_offset:249*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x3, 249*FLEN/8, x4, x1, x2) + +inst_120: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x23e and fs2 == 1 and fe2 == 0x14 and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x184 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e3e; op2val:0xd201; +op3val:0x7984; valaddr_reg:x3; val_offset:252*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 252*FLEN/8, x4, x1, x2) + +inst_121: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x23e and fs2 == 1 and fe2 == 0x14 and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x184 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e3e; op2val:0xd201; +op3val:0x7984; valaddr_reg:x3; val_offset:255*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x3, 255*FLEN/8, x4, x1, x2) + +inst_122: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x23e and fs2 == 1 and fe2 == 0x14 and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x184 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e3e; op2val:0xd201; +op3val:0x7984; valaddr_reg:x3; val_offset:258*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x3, 258*FLEN/8, x4, x1, x2) + +inst_123: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x23e and fs2 == 1 and fe2 == 0x14 and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x184 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e3e; op2val:0xd201; +op3val:0x7984; valaddr_reg:x3; val_offset:261*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x3, 261*FLEN/8, x4, x1, x2) + +inst_124: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x23e and fs2 == 1 and fe2 == 0x14 and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x184 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e3e; op2val:0xd201; +op3val:0x7984; valaddr_reg:x3; val_offset:264*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x3, 264*FLEN/8, x4, x1, x2) + +inst_125: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19d and fs2 == 0 and fe2 == 0x11 and fm2 == 0x058 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x398 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x799d; op2val:0x4458; +op3val:0x7b98; valaddr_reg:x3; val_offset:267*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 267*FLEN/8, x4, x1, x2) + +inst_126: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19d and fs2 == 0 and fe2 == 0x11 and fm2 == 0x058 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x398 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x799d; op2val:0x4458; +op3val:0x7b98; valaddr_reg:x3; val_offset:270*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x3, 270*FLEN/8, x4, x1, x2) + +inst_127: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19d and fs2 == 0 and fe2 == 0x11 and fm2 == 0x058 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x398 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x799d; op2val:0x4458; +op3val:0x7b98; valaddr_reg:x3; val_offset:273*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x3, 273*FLEN/8, x4, x1, x2) + +inst_128: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19d and fs2 == 0 and fe2 == 0x11 and fm2 == 0x058 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x398 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x799d; op2val:0x4458; +op3val:0x7b98; valaddr_reg:x3; val_offset:276*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x3, 276*FLEN/8, x4, x1, x2) + +inst_129: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19d and fs2 == 0 and fe2 == 0x11 and fm2 == 0x058 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x398 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x799d; op2val:0x4458; +op3val:0x7b98; valaddr_reg:x3; val_offset:279*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x3, 279*FLEN/8, x4, x1, x2) + +inst_130: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2be and fs2 == 1 and fe2 == 0x12 and fm2 == 0x10a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x006 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7abe; op2val:0xc90a; +op3val:0x7806; valaddr_reg:x3; val_offset:282*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 282*FLEN/8, x4, x1, x2) + +inst_131: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2be and fs2 == 1 and fe2 == 0x12 and fm2 == 0x10a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x006 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7abe; op2val:0xc90a; +op3val:0x7806; valaddr_reg:x3; val_offset:285*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x3, 285*FLEN/8, x4, x1, x2) + +inst_132: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2be and fs2 == 1 and fe2 == 0x12 and fm2 == 0x10a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x006 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7abe; op2val:0xc90a; +op3val:0x7806; valaddr_reg:x3; val_offset:288*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x3, 288*FLEN/8, x4, x1, x2) + +inst_133: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2be and fs2 == 1 and fe2 == 0x12 and fm2 == 0x10a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x006 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7abe; op2val:0xc90a; +op3val:0x7806; valaddr_reg:x3; val_offset:291*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x3, 291*FLEN/8, x4, x1, x2) + +inst_134: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2be and fs2 == 1 and fe2 == 0x12 and fm2 == 0x10a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x006 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7abe; op2val:0xc90a; +op3val:0x7806; valaddr_reg:x3; val_offset:294*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x3, 294*FLEN/8, x4, x1, x2) + +inst_135: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x252 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x0f6 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0cd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7252; op2val:0x50f6; +op3val:0x70cd; valaddr_reg:x3; val_offset:297*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 297*FLEN/8, x4, x1, x2) + +inst_136: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x252 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x0f6 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0cd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7252; op2val:0x50f6; +op3val:0x70cd; valaddr_reg:x3; val_offset:300*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x3, 300*FLEN/8, x4, x1, x2) + +inst_137: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x252 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x0f6 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0cd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7252; op2val:0x50f6; +op3val:0x70cd; valaddr_reg:x3; val_offset:303*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x3, 303*FLEN/8, x4, x1, x2) + +inst_138: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x252 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x0f6 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0cd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7252; op2val:0x50f6; +op3val:0x70cd; valaddr_reg:x3; val_offset:306*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x3, 306*FLEN/8, x4, x1, x2) + +inst_139: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x252 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x0f6 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0cd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7252; op2val:0x50f6; +op3val:0x70cd; valaddr_reg:x3; val_offset:309*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x3, 309*FLEN/8, x4, x1, x2) + +inst_140: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x340 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x053 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7340; op2val:0xc853; +op3val:0x7bb1; valaddr_reg:x3; val_offset:312*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x3, 312*FLEN/8, x4, x1, x2) + +inst_141: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x340 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x053 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7340; op2val:0xc853; +op3val:0x7bb1; valaddr_reg:x3; val_offset:315*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x3, 315*FLEN/8, x4, x1, x2) + +inst_142: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x340 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x053 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7340; op2val:0xc853; +op3val:0x7bb1; valaddr_reg:x3; val_offset:318*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x3, 318*FLEN/8, x4, x1, x2) + +inst_143: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x340 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x053 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7340; op2val:0xc853; +op3val:0x7bb1; valaddr_reg:x3; val_offset:321*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x3, 321*FLEN/8, x4, x1, x2) + +inst_144: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x00a and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0ac and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x700a; op2val:0x40ac; +op3val:0x79a2; valaddr_reg:x3; val_offset:324*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x3, 324*FLEN/8, x4, x1, x2) + +inst_145: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x00a and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0ac and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x700a; op2val:0x40ac; +op3val:0x79a2; valaddr_reg:x3; val_offset:327*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x3, 327*FLEN/8, x4, x1, x2) + +inst_146: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x00a and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0ac and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x700a; op2val:0x40ac; +op3val:0x79a2; valaddr_reg:x3; val_offset:330*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x3, 330*FLEN/8, x4, x1, x2) + +inst_147: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x00a and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0ac and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x700a; op2val:0x40ac; +op3val:0x79a2; valaddr_reg:x3; val_offset:333*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x3, 333*FLEN/8, x4, x1, x2) + +inst_148: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x173 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x352 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3ea and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d73; op2val:0xcb52; +op3val:0x73ea; valaddr_reg:x3; val_offset:336*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x3, 336*FLEN/8, x4, x1, x2) + +inst_149: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x173 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x352 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3ea and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d73; op2val:0xcb52; +op3val:0x73ea; valaddr_reg:x3; val_offset:339*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x3, 339*FLEN/8, x4, x1, x2) + +inst_150: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x33f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x075 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3ea and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x773f; op2val:0x3c75; +op3val:0x77ea; valaddr_reg:x3; val_offset:342*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x3, 342*FLEN/8, x4, x1, x2) + +inst_151: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x226 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0c2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7226; op2val:0xc8c2; +op3val:0x7aa4; valaddr_reg:x3; val_offset:345*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x3, 345*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(29504,32,FLEN) +NAN_BOXED(29504,16,FLEN) +NAN_BOXED(31665,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(51283,16,FLEN) +NAN_BOXED(31665,32,FLEN) +NAN_BOXED(29504,32,FLEN) +NAN_BOXED(51283,16,FLEN) +NAN_BOXED(31665,32,FLEN) +NAN_BOXED(29504,32,FLEN) +NAN_BOXED(51283,16,FLEN) +NAN_BOXED(29504,32,FLEN) +NAN_BOXED(29504,32,FLEN) +NAN_BOXED(29504,16,FLEN) +NAN_BOXED(29504,32,FLEN) +NAN_BOXED(28682,32,FLEN) +NAN_BOXED(16556,32,FLEN) +NAN_BOXED(31138,32,FLEN) +NAN_BOXED(28682,32,FLEN) +NAN_BOXED(16556,32,FLEN) +NAN_BOXED(16556,32,FLEN) +NAN_BOXED(28682,32,FLEN) +NAN_BOXED(16556,32,FLEN) +NAN_BOXED(28682,32,FLEN) +NAN_BOXED(28682,32,FLEN) +NAN_BOXED(28682,32,FLEN) +NAN_BOXED(28682,32,FLEN) +NAN_BOXED(28682,32,FLEN) +NAN_BOXED(28682,32,FLEN) +NAN_BOXED(31138,32,FLEN) +NAN_BOXED(28019,32,FLEN) +NAN_BOXED(52050,16,FLEN) +NAN_BOXED(29674,32,FLEN) +NAN_BOXED(28019,32,FLEN) +NAN_BOXED(52050,16,FLEN) +NAN_BOXED(52050,32,FLEN) +NAN_BOXED(28019,32,FLEN) +NAN_BOXED(52050,16,FLEN) +NAN_BOXED(29674,32,FLEN) +test_dataset_1: +NAN_BOXED(28019,32,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(29674,32,FLEN) +NAN_BOXED(28019,32,FLEN) +NAN_BOXED(52050,16,FLEN) +NAN_BOXED(29674,32,FLEN) +NAN_BOXED(31741,32,FLEN) +NAN_BOXED(14932,32,FLEN) +NAN_BOXED(29362,32,FLEN) +NAN_BOXED(31741,32,FLEN) +NAN_BOXED(14932,32,FLEN) +NAN_BOXED(29362,32,FLEN) +NAN_BOXED(31741,32,FLEN) +NAN_BOXED(14932,32,FLEN) +NAN_BOXED(29362,32,FLEN) +NAN_BOXED(31741,32,FLEN) +NAN_BOXED(14932,32,FLEN) +NAN_BOXED(29362,32,FLEN) +NAN_BOXED(31741,32,FLEN) +NAN_BOXED(14932,32,FLEN) +NAN_BOXED(29362,32,FLEN) +NAN_BOXED(31009,32,FLEN) +NAN_BOXED(49291,16,FLEN) +NAN_BOXED(30551,32,FLEN) +NAN_BOXED(31009,32,FLEN) +NAN_BOXED(49291,16,FLEN) +NAN_BOXED(30551,32,FLEN) +NAN_BOXED(31009,32,FLEN) +NAN_BOXED(49291,16,FLEN) +NAN_BOXED(30551,32,FLEN) +test_dataset_2: +NAN_BOXED(31009,32,FLEN) +NAN_BOXED(49291,16,FLEN) +NAN_BOXED(30551,32,FLEN) +NAN_BOXED(31009,32,FLEN) +NAN_BOXED(49291,16,FLEN) +NAN_BOXED(30551,32,FLEN) +NAN_BOXED(30527,32,FLEN) +NAN_BOXED(15477,32,FLEN) +NAN_BOXED(30698,32,FLEN) +NAN_BOXED(30527,32,FLEN) +NAN_BOXED(15477,32,FLEN) +NAN_BOXED(30698,32,FLEN) +NAN_BOXED(30527,32,FLEN) +NAN_BOXED(15477,32,FLEN) +NAN_BOXED(30698,32,FLEN) +NAN_BOXED(30527,32,FLEN) +NAN_BOXED(15477,32,FLEN) +NAN_BOXED(30698,32,FLEN) +NAN_BOXED(30527,32,FLEN) +NAN_BOXED(15477,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(29222,32,FLEN) +NAN_BOXED(51394,16,FLEN) +NAN_BOXED(31396,32,FLEN) +NAN_BOXED(29222,32,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31396,32,FLEN) +NAN_BOXED(29222,32,FLEN) +NAN_BOXED(51394,16,FLEN) +NAN_BOXED(31396,32,FLEN) +NAN_BOXED(29222,32,FLEN) +NAN_BOXED(51394,16,FLEN) +NAN_BOXED(31396,32,FLEN) +NAN_BOXED(29222,32,FLEN) +NAN_BOXED(51394,16,FLEN) +NAN_BOXED(31396,32,FLEN) +NAN_BOXED(28090,32,FLEN) +NAN_BOXED(18502,32,FLEN) +NAN_BOXED(29565,32,FLEN) +test_dataset_3: +NAN_BOXED(28090,16,FLEN) +NAN_BOXED(18502,16,FLEN) +NAN_BOXED(29565,16,FLEN) +NAN_BOXED(28090,16,FLEN) +NAN_BOXED(18502,16,FLEN) +NAN_BOXED(29565,16,FLEN) +NAN_BOXED(28090,16,FLEN) +NAN_BOXED(18502,16,FLEN) +NAN_BOXED(29565,16,FLEN) +NAN_BOXED(28090,16,FLEN) +NAN_BOXED(18502,16,FLEN) +NAN_BOXED(29565,16,FLEN) +NAN_BOXED(25886,16,FLEN) +NAN_BOXED(54250,16,FLEN) +NAN_BOXED(29764,16,FLEN) +NAN_BOXED(25886,16,FLEN) +NAN_BOXED(54250,16,FLEN) +NAN_BOXED(29764,16,FLEN) +NAN_BOXED(25886,16,FLEN) +NAN_BOXED(54250,16,FLEN) +NAN_BOXED(29764,16,FLEN) +NAN_BOXED(25886,16,FLEN) +NAN_BOXED(54250,16,FLEN) +NAN_BOXED(29764,16,FLEN) +NAN_BOXED(25886,16,FLEN) +NAN_BOXED(54250,16,FLEN) +NAN_BOXED(29764,16,FLEN) +NAN_BOXED(30341,16,FLEN) +NAN_BOXED(13231,16,FLEN) +NAN_BOXED(31542,16,FLEN) +NAN_BOXED(30341,16,FLEN) +NAN_BOXED(13231,16,FLEN) +NAN_BOXED(31542,16,FLEN) +NAN_BOXED(30341,16,FLEN) +NAN_BOXED(13231,16,FLEN) +NAN_BOXED(31542,16,FLEN) +NAN_BOXED(30341,16,FLEN) +NAN_BOXED(13231,16,FLEN) +NAN_BOXED(31542,16,FLEN) +NAN_BOXED(30341,16,FLEN) +NAN_BOXED(13231,16,FLEN) +NAN_BOXED(31542,16,FLEN) +NAN_BOXED(30223,16,FLEN) +NAN_BOXED(49632,16,FLEN) +NAN_BOXED(28486,16,FLEN) +NAN_BOXED(30223,16,FLEN) +NAN_BOXED(49632,16,FLEN) +NAN_BOXED(28486,16,FLEN) +NAN_BOXED(30223,16,FLEN) +NAN_BOXED(49632,16,FLEN) +NAN_BOXED(28486,16,FLEN) +NAN_BOXED(30223,16,FLEN) +NAN_BOXED(49632,16,FLEN) +NAN_BOXED(28486,16,FLEN) +NAN_BOXED(30223,16,FLEN) +NAN_BOXED(49632,16,FLEN) +NAN_BOXED(28486,16,FLEN) +NAN_BOXED(29729,16,FLEN) +NAN_BOXED(10281,16,FLEN) +NAN_BOXED(31725,16,FLEN) +NAN_BOXED(29729,16,FLEN) +NAN_BOXED(10281,16,FLEN) +NAN_BOXED(31725,16,FLEN) +NAN_BOXED(29729,16,FLEN) +NAN_BOXED(10281,16,FLEN) +NAN_BOXED(31725,16,FLEN) +NAN_BOXED(29729,16,FLEN) +NAN_BOXED(10281,16,FLEN) +NAN_BOXED(31725,16,FLEN) +NAN_BOXED(29729,16,FLEN) +NAN_BOXED(10281,16,FLEN) +NAN_BOXED(31725,16,FLEN) +NAN_BOXED(27657,16,FLEN) +NAN_BOXED(52843,16,FLEN) +NAN_BOXED(30965,16,FLEN) +NAN_BOXED(27657,16,FLEN) +NAN_BOXED(52843,16,FLEN) +NAN_BOXED(30965,16,FLEN) +NAN_BOXED(27657,16,FLEN) +NAN_BOXED(52843,16,FLEN) +NAN_BOXED(30965,16,FLEN) +NAN_BOXED(27657,16,FLEN) +NAN_BOXED(52843,16,FLEN) +NAN_BOXED(30965,16,FLEN) +NAN_BOXED(27657,16,FLEN) +NAN_BOXED(52843,16,FLEN) +NAN_BOXED(30965,16,FLEN) +NAN_BOXED(30216,16,FLEN) +NAN_BOXED(15153,16,FLEN) +NAN_BOXED(31048,16,FLEN) +NAN_BOXED(30216,16,FLEN) +NAN_BOXED(15153,16,FLEN) +NAN_BOXED(31048,16,FLEN) +NAN_BOXED(30216,16,FLEN) +NAN_BOXED(15153,16,FLEN) +NAN_BOXED(31048,16,FLEN) +NAN_BOXED(30216,16,FLEN) +NAN_BOXED(15153,16,FLEN) +NAN_BOXED(31048,16,FLEN) +NAN_BOXED(30216,16,FLEN) +NAN_BOXED(15153,16,FLEN) +NAN_BOXED(31048,16,FLEN) +NAN_BOXED(30057,16,FLEN) +NAN_BOXED(49362,16,FLEN) +NAN_BOXED(31111,16,FLEN) +NAN_BOXED(30057,16,FLEN) +NAN_BOXED(49362,16,FLEN) +NAN_BOXED(31111,16,FLEN) +NAN_BOXED(30057,16,FLEN) +NAN_BOXED(49362,16,FLEN) +NAN_BOXED(31111,16,FLEN) +NAN_BOXED(30057,16,FLEN) +NAN_BOXED(49362,16,FLEN) +NAN_BOXED(31111,16,FLEN) +NAN_BOXED(30057,16,FLEN) +NAN_BOXED(49362,16,FLEN) +NAN_BOXED(31111,16,FLEN) +NAN_BOXED(30709,16,FLEN) +NAN_BOXED(48183,16,FLEN) +NAN_BOXED(31025,16,FLEN) +NAN_BOXED(30709,16,FLEN) +NAN_BOXED(48183,16,FLEN) +NAN_BOXED(31025,16,FLEN) +NAN_BOXED(30709,16,FLEN) +NAN_BOXED(48183,16,FLEN) +NAN_BOXED(31025,16,FLEN) +NAN_BOXED(30709,16,FLEN) +NAN_BOXED(48183,16,FLEN) +NAN_BOXED(31025,16,FLEN) +NAN_BOXED(30709,16,FLEN) +NAN_BOXED(48183,16,FLEN) +NAN_BOXED(31025,16,FLEN) +NAN_BOXED(31541,16,FLEN) +NAN_BOXED(47969,16,FLEN) +NAN_BOXED(30886,16,FLEN) +NAN_BOXED(31541,16,FLEN) +NAN_BOXED(47969,16,FLEN) +NAN_BOXED(30886,16,FLEN) +NAN_BOXED(31541,16,FLEN) +NAN_BOXED(47969,16,FLEN) +NAN_BOXED(30886,16,FLEN) +NAN_BOXED(31541,16,FLEN) +NAN_BOXED(47969,16,FLEN) +NAN_BOXED(30886,16,FLEN) +NAN_BOXED(31541,16,FLEN) +NAN_BOXED(47969,16,FLEN) +NAN_BOXED(30886,16,FLEN) +NAN_BOXED(28811,16,FLEN) +NAN_BOXED(15673,16,FLEN) +NAN_BOXED(27678,16,FLEN) +NAN_BOXED(28811,16,FLEN) +NAN_BOXED(15673,16,FLEN) +NAN_BOXED(27678,16,FLEN) +NAN_BOXED(28811,16,FLEN) +NAN_BOXED(15673,16,FLEN) +NAN_BOXED(27678,16,FLEN) +NAN_BOXED(28811,16,FLEN) +NAN_BOXED(15673,16,FLEN) +NAN_BOXED(27678,16,FLEN) +NAN_BOXED(28811,16,FLEN) +NAN_BOXED(15673,16,FLEN) +NAN_BOXED(27678,16,FLEN) +NAN_BOXED(31632,16,FLEN) +NAN_BOXED(48174,16,FLEN) +NAN_BOXED(30672,16,FLEN) +NAN_BOXED(31632,16,FLEN) +NAN_BOXED(48174,16,FLEN) +NAN_BOXED(30672,16,FLEN) +NAN_BOXED(31632,16,FLEN) +NAN_BOXED(48174,16,FLEN) +NAN_BOXED(30672,16,FLEN) +NAN_BOXED(31632,16,FLEN) +NAN_BOXED(48174,16,FLEN) +NAN_BOXED(30672,16,FLEN) +NAN_BOXED(31632,16,FLEN) +NAN_BOXED(48174,16,FLEN) +NAN_BOXED(30672,16,FLEN) +NAN_BOXED(29235,16,FLEN) +NAN_BOXED(49306,16,FLEN) +NAN_BOXED(31632,16,FLEN) +NAN_BOXED(29235,16,FLEN) +NAN_BOXED(49306,16,FLEN) +NAN_BOXED(31632,16,FLEN) +NAN_BOXED(29235,16,FLEN) +NAN_BOXED(49306,16,FLEN) +NAN_BOXED(31632,16,FLEN) +NAN_BOXED(29235,16,FLEN) +NAN_BOXED(49306,16,FLEN) +NAN_BOXED(31632,16,FLEN) +NAN_BOXED(29235,16,FLEN) +NAN_BOXED(49306,16,FLEN) +NAN_BOXED(31632,16,FLEN) +NAN_BOXED(30881,16,FLEN) +NAN_BOXED(49656,16,FLEN) +NAN_BOXED(31188,16,FLEN) +NAN_BOXED(30881,16,FLEN) +NAN_BOXED(49656,16,FLEN) +NAN_BOXED(31188,16,FLEN) +NAN_BOXED(30881,16,FLEN) +NAN_BOXED(49656,16,FLEN) +NAN_BOXED(31188,16,FLEN) +NAN_BOXED(30881,16,FLEN) +NAN_BOXED(49656,16,FLEN) +NAN_BOXED(31188,16,FLEN) +NAN_BOXED(30881,16,FLEN) +NAN_BOXED(49656,16,FLEN) +NAN_BOXED(31188,16,FLEN) +NAN_BOXED(31499,16,FLEN) +NAN_BOXED(14972,16,FLEN) +NAN_BOXED(29841,16,FLEN) +NAN_BOXED(31499,16,FLEN) +NAN_BOXED(14972,16,FLEN) +NAN_BOXED(29841,16,FLEN) +NAN_BOXED(31499,16,FLEN) +NAN_BOXED(14972,16,FLEN) +NAN_BOXED(29841,16,FLEN) +NAN_BOXED(31499,16,FLEN) +NAN_BOXED(14972,16,FLEN) +NAN_BOXED(29841,16,FLEN) +NAN_BOXED(31499,16,FLEN) +NAN_BOXED(14972,16,FLEN) +NAN_BOXED(29841,16,FLEN) +NAN_BOXED(30132,16,FLEN) +NAN_BOXED(51208,16,FLEN) +NAN_BOXED(31493,16,FLEN) +NAN_BOXED(30132,16,FLEN) +NAN_BOXED(51208,16,FLEN) +NAN_BOXED(31493,16,FLEN) +NAN_BOXED(30132,16,FLEN) +NAN_BOXED(51208,16,FLEN) +NAN_BOXED(31493,16,FLEN) +NAN_BOXED(30132,16,FLEN) +NAN_BOXED(51208,16,FLEN) +NAN_BOXED(31493,16,FLEN) +NAN_BOXED(30132,16,FLEN) +NAN_BOXED(51208,16,FLEN) +NAN_BOXED(31493,16,FLEN) +NAN_BOXED(28753,16,FLEN) +NAN_BOXED(18579,16,FLEN) +NAN_BOXED(31260,16,FLEN) +NAN_BOXED(28753,16,FLEN) +NAN_BOXED(18579,16,FLEN) +NAN_BOXED(31260,16,FLEN) +NAN_BOXED(28753,16,FLEN) +NAN_BOXED(18579,16,FLEN) +NAN_BOXED(31260,16,FLEN) +NAN_BOXED(28753,16,FLEN) +NAN_BOXED(18579,16,FLEN) +NAN_BOXED(31260,16,FLEN) +NAN_BOXED(28753,16,FLEN) +NAN_BOXED(18579,16,FLEN) +NAN_BOXED(31260,16,FLEN) +NAN_BOXED(28222,16,FLEN) +NAN_BOXED(53761,16,FLEN) +NAN_BOXED(31108,16,FLEN) +NAN_BOXED(28222,16,FLEN) +NAN_BOXED(53761,16,FLEN) +NAN_BOXED(31108,16,FLEN) +NAN_BOXED(28222,16,FLEN) +NAN_BOXED(53761,16,FLEN) +NAN_BOXED(31108,16,FLEN) +NAN_BOXED(28222,16,FLEN) +NAN_BOXED(53761,16,FLEN) +NAN_BOXED(31108,16,FLEN) +NAN_BOXED(28222,16,FLEN) +NAN_BOXED(53761,16,FLEN) +NAN_BOXED(31108,16,FLEN) +NAN_BOXED(31133,16,FLEN) +NAN_BOXED(17496,16,FLEN) +NAN_BOXED(31640,16,FLEN) +NAN_BOXED(31133,16,FLEN) +NAN_BOXED(17496,16,FLEN) +NAN_BOXED(31640,16,FLEN) +NAN_BOXED(31133,16,FLEN) +NAN_BOXED(17496,16,FLEN) +NAN_BOXED(31640,16,FLEN) +NAN_BOXED(31133,16,FLEN) +NAN_BOXED(17496,16,FLEN) +NAN_BOXED(31640,16,FLEN) +NAN_BOXED(31133,16,FLEN) +NAN_BOXED(17496,16,FLEN) +NAN_BOXED(31640,16,FLEN) +NAN_BOXED(31422,16,FLEN) +NAN_BOXED(51466,16,FLEN) +NAN_BOXED(30726,16,FLEN) +NAN_BOXED(31422,16,FLEN) +NAN_BOXED(51466,16,FLEN) +NAN_BOXED(30726,16,FLEN) +NAN_BOXED(31422,16,FLEN) +NAN_BOXED(51466,16,FLEN) +NAN_BOXED(30726,16,FLEN) +NAN_BOXED(31422,16,FLEN) +NAN_BOXED(51466,16,FLEN) +NAN_BOXED(30726,16,FLEN) +NAN_BOXED(31422,16,FLEN) +NAN_BOXED(51466,16,FLEN) +NAN_BOXED(30726,16,FLEN) +NAN_BOXED(29266,16,FLEN) +NAN_BOXED(20726,16,FLEN) +NAN_BOXED(28877,16,FLEN) +NAN_BOXED(29266,16,FLEN) +NAN_BOXED(20726,16,FLEN) +NAN_BOXED(28877,16,FLEN) +NAN_BOXED(29266,16,FLEN) +NAN_BOXED(20726,16,FLEN) +NAN_BOXED(28877,16,FLEN) +NAN_BOXED(29266,16,FLEN) +NAN_BOXED(20726,16,FLEN) +NAN_BOXED(28877,16,FLEN) +NAN_BOXED(29266,16,FLEN) +NAN_BOXED(20726,16,FLEN) +NAN_BOXED(28877,16,FLEN) +NAN_BOXED(29504,16,FLEN) +NAN_BOXED(51283,16,FLEN) +NAN_BOXED(31665,16,FLEN) +NAN_BOXED(29504,16,FLEN) +NAN_BOXED(51283,16,FLEN) +NAN_BOXED(31665,16,FLEN) +NAN_BOXED(29504,16,FLEN) +NAN_BOXED(51283,16,FLEN) +NAN_BOXED(31665,16,FLEN) +NAN_BOXED(29504,16,FLEN) +NAN_BOXED(51283,16,FLEN) +NAN_BOXED(31665,16,FLEN) +NAN_BOXED(28682,16,FLEN) +NAN_BOXED(16556,16,FLEN) +NAN_BOXED(31138,16,FLEN) +NAN_BOXED(28682,16,FLEN) +NAN_BOXED(16556,16,FLEN) +NAN_BOXED(31138,16,FLEN) +NAN_BOXED(28682,16,FLEN) +NAN_BOXED(16556,16,FLEN) +NAN_BOXED(31138,16,FLEN) +NAN_BOXED(28682,16,FLEN) +NAN_BOXED(16556,16,FLEN) +NAN_BOXED(31138,16,FLEN) +NAN_BOXED(28019,16,FLEN) +NAN_BOXED(52050,16,FLEN) +NAN_BOXED(29674,16,FLEN) +NAN_BOXED(28019,16,FLEN) +NAN_BOXED(52050,16,FLEN) +NAN_BOXED(29674,16,FLEN) +NAN_BOXED(30527,16,FLEN) +NAN_BOXED(15477,16,FLEN) +NAN_BOXED(30698,16,FLEN) +NAN_BOXED(29222,16,FLEN) +NAN_BOXED(51394,16,FLEN) +NAN_BOXED(31396,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x19_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x19_1: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x8_0: + .fill 32*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_0: + .fill 244*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fnmsub_b5-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fnmsub_b5-01.S new file mode 100644 index 000000000..d1e035fa3 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fnmsub_b5-01.S @@ -0,0 +1,2409 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 06:07:02 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fnmsub.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fnmsub.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fnmsub_b5 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fnmsub_b5) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x4,test_dataset_0) +RVTEST_SIGBASE(x9,signature_x9_1) + +inst_0: +// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==x5, rs2==x5, rs3==x14, rd==x2,fs1 == 0 and fe1 == 0x1c and fm1 == 0x340 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x03e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x5; op2:x5; op3:x14; dest:x2; op1val:0x7340; op2val:0x7340; +op3val:0x7bb1; valaddr_reg:x4; val_offset:0*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x2, x5, x5, x14, dyn, 0, 0, x4, 0*FLEN/8, x7, x9, x12) + +inst_1: +// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==x17, rs2==x25, rs3==x28, rd==x17,fs1 == 0 and fe1 == 0x1c and fm1 == 0x340 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x03e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x17; op2:x25; op3:x28; dest:x17; op1val:0x7340; op2val:0xc43e; +op3val:0x7bb1; valaddr_reg:x4; val_offset:3*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x17, x17, x25, x28, dyn, 32, 0, x4, 3*FLEN/8, x7, x9, x12) + +inst_2: +// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==x2, rs2==x26, rs3==x9, rd==x1,fs1 == 0 and fe1 == 0x1c and fm1 == 0x340 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x03e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x2; op2:x26; op3:x9; dest:x1; op1val:0x7340; op2val:0xc43e; +op3val:0x7bb1; valaddr_reg:x4; val_offset:6*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x1, x2, x26, x9, dyn, 64, 0, x4, 6*FLEN/8, x7, x9, x12) + +inst_3: +// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==x0, rs2==x19, rs3==x0, rd==x8,fs1 == 0 and fe1 == 0x1c and fm1 == 0x340 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x03e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x0; op2:x19; op3:x0; dest:x8; op1val:0x0; op2val:0xc43e; +op3val:0x0; valaddr_reg:x4; val_offset:9*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x8, x0, x19, x0, dyn, 96, 0, x4, 9*FLEN/8, x7, x9, x12) + +inst_4: +// rs1 == rs2 == rs3 != rd, rs1==x30, rs2==x30, rs3==x30, rd==x31,fs1 == 0 and fe1 == 0x1c and fm1 == 0x340 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x03e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x30; op3:x30; dest:x31; op1val:0x7340; op2val:0x7340; +op3val:0x7340; valaddr_reg:x4; val_offset:12*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x30, x30, dyn, 128, 0, x4, 12*FLEN/8, x7, x9, x12) + +inst_5: +// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==x15, rs2==x14, rs3==x11, rd==x11,fs1 == 0 and fe1 == 0x1c and fm1 == 0x00a and fs2 == 1 and fe2 == 0x11 and fm2 == 0x194 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x15; op2:x14; op3:x11; dest:x11; op1val:0x700a; op2val:0xc594; +op3val:0x79a2; valaddr_reg:x4; val_offset:15*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x11, x15, x14, x11, dyn, 0, 0, x4, 15*FLEN/8, x7, x9, x12) + +inst_6: +// rd == rs2 == rs3 != rs1, rs1==x6, rs2==x3, rs3==x3, rd==x3,fs1 == 0 and fe1 == 0x1c and fm1 == 0x00a and fs2 == 1 and fe2 == 0x11 and fm2 == 0x194 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x6; op2:x3; op3:x3; dest:x3; op1val:0x700a; op2val:0xc594; +op3val:0xc594; valaddr_reg:x4; val_offset:18*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x3, x6, x3, x3, dyn, 32, 0, x4, 18*FLEN/8, x7, x9, x12) + +inst_7: +// rs1 == rd == rs3 != rs2, rs1==x19, rs2==x23, rs3==x19, rd==x19,fs1 == 0 and fe1 == 0x1c and fm1 == 0x00a and fs2 == 1 and fe2 == 0x11 and fm2 == 0x194 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x19; op2:x23; op3:x19; dest:x19; op1val:0x700a; op2val:0xc594; +op3val:0x700a; valaddr_reg:x4; val_offset:21*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x19, x19, x23, x19, dyn, 64, 0, x4, 21*FLEN/8, x7, x9, x12) + +inst_8: +// rs1 == rs2 == rs3 == rd, rs1==x24, rs2==x24, rs3==x24, rd==x24,fs1 == 0 and fe1 == 0x1c and fm1 == 0x00a and fs2 == 1 and fe2 == 0x11 and fm2 == 0x194 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x24; op2:x24; op3:x24; dest:x24; op1val:0x700a; op2val:0x700a; +op3val:0x700a; valaddr_reg:x4; val_offset:24*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x24, x24, x24, x24, dyn, 96, 0, x4, 24*FLEN/8, x7, x9, x12) + +inst_9: +// rs1 == rs2 == rd != rs3, rs1==x21, rs2==x21, rs3==x2, rd==x21,fs1 == 0 and fe1 == 0x1c and fm1 == 0x00a and fs2 == 1 and fe2 == 0x11 and fm2 == 0x194 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x21; op2:x21; op3:x2; dest:x21; op1val:0x700a; op2val:0x700a; +op3val:0x79a2; valaddr_reg:x4; val_offset:27*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x21, x21, x21, x2, dyn, 128, 0, x4, 27*FLEN/8, x7, x9, x12) + +inst_10: +// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==x3, rs2==x16, rs3==x4, rd==x16,fs1 == 0 and fe1 == 0x1b and fm1 == 0x173 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1cf and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3ea and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x3; op2:x16; op3:x4; dest:x16; op1val:0x6d73; op2val:0xc1cf; +op3val:0x73ea; valaddr_reg:x4; val_offset:30*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x16, x3, x16, x4, dyn, 0, 0, x4, 30*FLEN/8, x7, x9, x12) + +inst_11: +// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==x31, rs2==x10, rs3==x10, rd==x29,fs1 == 0 and fe1 == 0x1b and fm1 == 0x173 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1cf and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3ea and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x31; op2:x10; op3:x10; dest:x29; op1val:0x6d73; op2val:0xc1cf; +op3val:0xc1cf; valaddr_reg:x4; val_offset:33*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x29, x31, x10, x10, dyn, 32, 0, x4, 33*FLEN/8, x7, x9, x12) + +inst_12: +// rs1==x8, rs2==x6, rs3==x27, rd==x18,fs1 == 0 and fe1 == 0x1b and fm1 == 0x173 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1cf and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3ea and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x8; op2:x6; op3:x27; dest:x18; op1val:0x6d73; op2val:0xc1cf; +op3val:0x73ea; valaddr_reg:x4; val_offset:36*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x18, x8, x6, x27, dyn, 64, 0, x4, 36*FLEN/8, x7, x9, x12) +RVTEST_VALBASEUPD(x8,test_dataset_1) + +inst_13: +// rs1==x20, rs2==x7, rs3==x17, rd==x4,fs1 == 0 and fe1 == 0x1b and fm1 == 0x173 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1cf and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3ea and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x20; op2:x7; op3:x17; dest:x4; op1val:0x6d73; op2val:0xc1cf; +op3val:0x73ea; valaddr_reg:x8; val_offset:0*FLEN/8; rmval:dyn; +testreg:x12; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x4, x20, x7, x17, dyn, 96, 0, x8, 0*FLEN/8, x19, x9, x12) +RVTEST_SIGBASE(x3,signature_x3_0) + +inst_14: +// rs1==x1, rs2==x15, rs3==x20, rd==x25,fs1 == 0 and fe1 == 0x1b and fm1 == 0x173 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1cf and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3ea and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x1; op2:x15; op3:x20; dest:x25; op1val:0x6d73; op2val:0xc1cf; +op3val:0x73ea; valaddr_reg:x8; val_offset:3*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x25, x1, x15, x20, dyn, 128, 0, x8, 3*FLEN/8, x19, x3, x6) + +inst_15: +// rs1==x9, rs2==x22, rs3==x7, rd==x5,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3fd and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2b4 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2b2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x9; op2:x22; op3:x7; dest:x5; op1val:0x7bfd; op2val:0xb2b4; +op3val:0x72b2; valaddr_reg:x8; val_offset:6*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x5, x9, x22, x7, dyn, 0, 0, x8, 6*FLEN/8, x19, x3, x6) + +inst_16: +// rs1==x14, rs2==x13, rs3==x29, rd==x23,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3fd and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2b4 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2b2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x14; op2:x13; op3:x29; dest:x23; op1val:0x7bfd; op2val:0xb2b4; +op3val:0x72b2; valaddr_reg:x8; val_offset:9*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x23, x14, x13, x29, dyn, 32, 0, x8, 9*FLEN/8, x19, x3, x6) + +inst_17: +// rs1==x10, rs2==x31, rs3==x5, rd==x13,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3fd and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2b4 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2b2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x10; op2:x31; op3:x5; dest:x13; op1val:0x7bfd; op2val:0xb2b4; +op3val:0x72b2; valaddr_reg:x8; val_offset:12*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x13, x10, x31, x5, dyn, 64, 0, x8, 12*FLEN/8, x19, x3, x6) + +inst_18: +// rs1==x18, rs2==x11, rs3==x23, rd==x9,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3fd and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2b4 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2b2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x18; op2:x11; op3:x23; dest:x9; op1val:0x7bfd; op2val:0xb2b4; +op3val:0x72b2; valaddr_reg:x8; val_offset:15*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x9, x18, x11, x23, dyn, 96, 0, x8, 15*FLEN/8, x19, x3, x6) + +inst_19: +// rs1==x12, rs2==x17, rs3==x15, rd==x14,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3fd and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2b4 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2b2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x12; op2:x17; op3:x15; dest:x14; op1val:0x7bfd; op2val:0xb2b4; +op3val:0x72b2; valaddr_reg:x8; val_offset:18*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x14, x12, x17, x15, dyn, 128, 0, x8, 18*FLEN/8, x19, x3, x6) + +inst_20: +// rs1==x22, rs2==x9, rs3==x18, rd==x12,fs1 == 0 and fe1 == 0x1e and fm1 == 0x121 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1b8 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x357 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x22; op2:x9; op3:x18; dest:x12; op1val:0x7921; op2val:0xb9b8; +op3val:0x7757; valaddr_reg:x8; val_offset:21*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x12, x22, x9, x18, dyn, 0, 0, x8, 21*FLEN/8, x19, x3, x6) + +inst_21: +// rs1==x27, rs2==x2, rs3==x16, rd==x30,fs1 == 0 and fe1 == 0x1e and fm1 == 0x121 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1b8 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x357 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x27; op2:x2; op3:x16; dest:x30; op1val:0x7921; op2val:0xb9b8; +op3val:0x7757; valaddr_reg:x8; val_offset:24*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x30, x27, x2, x16, dyn, 32, 0, x8, 24*FLEN/8, x19, x3, x6) + +inst_22: +// rs1==x16, rs2==x29, rs3==x6, rd==x10,fs1 == 0 and fe1 == 0x1e and fm1 == 0x121 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1b8 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x357 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x16; op2:x29; op3:x6; dest:x10; op1val:0x7921; op2val:0xb9b8; +op3val:0x7757; valaddr_reg:x8; val_offset:27*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x10, x16, x29, x6, dyn, 64, 0, x8, 27*FLEN/8, x19, x3, x6) +RVTEST_VALBASEUPD(x5,test_dataset_2) + +inst_23: +// rs1==x26, rs2==x0, rs3==x8, rd==x27,fs1 == 0 and fe1 == 0x1e and fm1 == 0x121 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1b8 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x357 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x26; op2:x0; op3:x8; dest:x27; op1val:0x7921; op2val:0x0; +op3val:0x7757; valaddr_reg:x5; val_offset:0*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x27, x26, x0, x8, dyn, 96, 0, x5, 0*FLEN/8, x9, x3, x6) + +inst_24: +// rs1==x29, rs2==x1, rs3==x22, rd==x26,fs1 == 0 and fe1 == 0x1e and fm1 == 0x121 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1b8 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x357 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x29; op2:x1; op3:x22; dest:x26; op1val:0x7921; op2val:0xb9b8; +op3val:0x7757; valaddr_reg:x5; val_offset:3*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x26, x29, x1, x22, dyn, 128, 0, x5, 3*FLEN/8, x9, x3, x6) + +inst_25: +// rs1==x11, rs2==x4, rs3==x21, rd==x15,fs1 == 0 and fe1 == 0x1d and fm1 == 0x33f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x05e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3ea and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x11; op2:x4; op3:x21; dest:x15; op1val:0x773f; op2val:0xbc5e; +op3val:0x77ea; valaddr_reg:x5; val_offset:6*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x15, x11, x4, x21, dyn, 0, 0, x5, 6*FLEN/8, x9, x3, x6) + +inst_26: +// rs1==x13, rs2==x27, rs3==x31, rd==x20,fs1 == 0 and fe1 == 0x1d and fm1 == 0x33f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x05e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3ea and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x13; op2:x27; op3:x31; dest:x20; op1val:0x773f; op2val:0xbc5e; +op3val:0x77ea; valaddr_reg:x5; val_offset:9*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x20, x13, x27, x31, dyn, 32, 0, x5, 9*FLEN/8, x9, x3, x6) + +inst_27: +// rs1==x25, rs2==x12, rs3==x26, rd==x28,fs1 == 0 and fe1 == 0x1d and fm1 == 0x33f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x05e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3ea and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x25; op2:x12; op3:x26; dest:x28; op1val:0x773f; op2val:0xbc5e; +op3val:0x77ea; valaddr_reg:x5; val_offset:12*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x28, x25, x12, x26, dyn, 64, 0, x5, 12*FLEN/8, x9, x3, x6) + +inst_28: +// rs1==x4, rs2==x18, rs3==x25, rd==x22,fs1 == 0 and fe1 == 0x1d and fm1 == 0x33f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x05e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3ea and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x4; op2:x18; op3:x25; dest:x22; op1val:0x773f; op2val:0xbc5e; +op3val:0x77ea; valaddr_reg:x5; val_offset:15*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x22, x4, x18, x25, dyn, 96, 0, x5, 15*FLEN/8, x9, x3, x2) + +inst_29: +// rs1==x7, rs2==x8, rs3==x1, rd==x0,fs1 == 0 and fe1 == 0x1d and fm1 == 0x33f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x05e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3ea and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x7; op2:x8; op3:x1; dest:x0; op1val:0x773f; op2val:0xbc5e; +op3val:0x77ea; valaddr_reg:x5; val_offset:18*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x0, x7, x8, x1, dyn, 128, 0, x5, 18*FLEN/8, x9, x3, x2) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_30: +// rs1==x28, rs2==x20, rs3==x13, rd==x6,fs1 == 0 and fe1 == 0x1c and fm1 == 0x226 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x051 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x28; op2:x20; op3:x13; dest:x6; op1val:0x7226; op2val:0xc451; +op3val:0x7aa4; valaddr_reg:x5; val_offset:21*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x6, x28, x20, x13, dyn, 0, 0, x5, 21*FLEN/8, x9, x1, x2) + +inst_31: +// rs1==x23, rs2==x28, rs3==x12, rd==x7,fs1 == 0 and fe1 == 0x1c and fm1 == 0x226 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x051 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x23; op2:x28; op3:x12; dest:x7; op1val:0x7226; op2val:0xc451; +op3val:0x7aa4; valaddr_reg:x5; val_offset:24*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x7, x23, x28, x12, dyn, 32, 0, x5, 24*FLEN/8, x9, x1, x2) + +inst_32: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x226 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x051 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7226; op2val:0xc451; +op3val:0x7aa4; valaddr_reg:x5; val_offset:27*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x5, 27*FLEN/8, x9, x1, x2) + +inst_33: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x226 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x051 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7226; op2val:0xc451; +op3val:0x7aa4; valaddr_reg:x5; val_offset:30*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x5, 30*FLEN/8, x9, x1, x2) + +inst_34: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x226 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x051 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7226; op2val:0xc451; +op3val:0x7aa4; valaddr_reg:x5; val_offset:33*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x5, 33*FLEN/8, x9, x1, x2) + +inst_35: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ba and fs2 == 1 and fe2 == 0x10 and fm2 == 0x13a and fs3 == 0 and fe3 == 0x1c and fm3 == 0x37d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dba; op2val:0xc13a; +op3val:0x737d; valaddr_reg:x5; val_offset:36*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 36*FLEN/8, x9, x1, x2) + +inst_36: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ba and fs2 == 1 and fe2 == 0x10 and fm2 == 0x13a and fs3 == 0 and fe3 == 0x1c and fm3 == 0x37d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dba; op2val:0xc13a; +op3val:0x737d; valaddr_reg:x5; val_offset:39*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x5, 39*FLEN/8, x9, x1, x2) + +inst_37: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ba and fs2 == 1 and fe2 == 0x10 and fm2 == 0x13a and fs3 == 0 and fe3 == 0x1c and fm3 == 0x37d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dba; op2val:0xc13a; +op3val:0x737d; valaddr_reg:x5; val_offset:42*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x5, 42*FLEN/8, x9, x1, x2) + +inst_38: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ba and fs2 == 1 and fe2 == 0x10 and fm2 == 0x13a and fs3 == 0 and fe3 == 0x1c and fm3 == 0x37d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dba; op2val:0xc13a; +op3val:0x737d; valaddr_reg:x5; val_offset:45*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x5, 45*FLEN/8, x9, x1, x2) + +inst_39: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ba and fs2 == 1 and fe2 == 0x10 and fm2 == 0x13a and fs3 == 0 and fe3 == 0x1c and fm3 == 0x37d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dba; op2val:0xc13a; +op3val:0x737d; valaddr_reg:x5; val_offset:48*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x5, 48*FLEN/8, x9, x1, x2) + +inst_40: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x11e and fs2 == 1 and fe2 == 0x12 and fm2 == 0x2aa and fs3 == 0 and fe3 == 0x1d and fm3 == 0x044 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x651e; op2val:0xcaaa; +op3val:0x7444; valaddr_reg:x5; val_offset:51*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 51*FLEN/8, x9, x1, x2) + +inst_41: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x11e and fs2 == 1 and fe2 == 0x12 and fm2 == 0x2aa and fs3 == 0 and fe3 == 0x1d and fm3 == 0x044 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x651e; op2val:0xcaaa; +op3val:0x7444; valaddr_reg:x5; val_offset:54*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x5, 54*FLEN/8, x9, x1, x2) + +inst_42: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x11e and fs2 == 1 and fe2 == 0x12 and fm2 == 0x2aa and fs3 == 0 and fe3 == 0x1d and fm3 == 0x044 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x651e; op2val:0xcaaa; +op3val:0x7444; valaddr_reg:x5; val_offset:57*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x5, 57*FLEN/8, x9, x1, x2) + +inst_43: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x11e and fs2 == 1 and fe2 == 0x12 and fm2 == 0x2aa and fs3 == 0 and fe3 == 0x1d and fm3 == 0x044 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x651e; op2val:0xcaaa; +op3val:0x7444; valaddr_reg:x5; val_offset:60*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x5, 60*FLEN/8, x9, x1, x2) + +inst_44: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x11e and fs2 == 1 and fe2 == 0x12 and fm2 == 0x2aa and fs3 == 0 and fe3 == 0x1d and fm3 == 0x044 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x651e; op2val:0xcaaa; +op3val:0x7444; valaddr_reg:x5; val_offset:63*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x5, 63*FLEN/8, x9, x1, x2) + +inst_45: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x285 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x06c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x336 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7685; op2val:0xc06c; +op3val:0x7b36; valaddr_reg:x5; val_offset:66*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 66*FLEN/8, x9, x1, x2) + +inst_46: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x285 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x06c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x336 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7685; op2val:0xc06c; +op3val:0x7b36; valaddr_reg:x5; val_offset:69*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x5, 69*FLEN/8, x9, x1, x2) + +inst_47: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x285 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x06c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x336 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7685; op2val:0xc06c; +op3val:0x7b36; valaddr_reg:x5; val_offset:72*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x5, 72*FLEN/8, x9, x1, x2) + +inst_48: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x285 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x06c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x336 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7685; op2val:0xc06c; +op3val:0x7b36; valaddr_reg:x5; val_offset:75*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x5, 75*FLEN/8, x9, x1, x2) + +inst_49: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x285 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x06c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x336 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7685; op2val:0xc06c; +op3val:0x7b36; valaddr_reg:x5; val_offset:78*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x5, 78*FLEN/8, x9, x1, x2) + +inst_50: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x20f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0cd and fs3 == 0 and fe3 == 0x1b and fm3 == 0x346 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x760f; op2val:0xb4cd; +op3val:0x6f46; valaddr_reg:x5; val_offset:81*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 81*FLEN/8, x9, x1, x2) + +inst_51: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x20f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0cd and fs3 == 0 and fe3 == 0x1b and fm3 == 0x346 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x760f; op2val:0xb4cd; +op3val:0x6f46; valaddr_reg:x5; val_offset:84*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x5, 84*FLEN/8, x9, x1, x2) + +inst_52: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x20f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0cd and fs3 == 0 and fe3 == 0x1b and fm3 == 0x346 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x760f; op2val:0xb4cd; +op3val:0x6f46; valaddr_reg:x5; val_offset:87*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x5, 87*FLEN/8, x9, x1, x2) + +inst_53: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x20f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0cd and fs3 == 0 and fe3 == 0x1b and fm3 == 0x346 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x760f; op2val:0xb4cd; +op3val:0x6f46; valaddr_reg:x5; val_offset:90*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x5, 90*FLEN/8, x9, x1, x2) + +inst_54: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x20f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0cd and fs3 == 0 and fe3 == 0x1b and fm3 == 0x346 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x760f; op2val:0xb4cd; +op3val:0x6f46; valaddr_reg:x5; val_offset:93*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x5, 93*FLEN/8, x9, x1, x2) + +inst_55: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x021 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3ad and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ed and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7421; op2val:0xc3ad; +op3val:0x7bed; valaddr_reg:x5; val_offset:96*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 96*FLEN/8, x9, x1, x2) + +inst_56: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x021 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3ad and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ed and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7421; op2val:0xc3ad; +op3val:0x7bed; valaddr_reg:x5; val_offset:99*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x5, 99*FLEN/8, x9, x1, x2) + +inst_57: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x021 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3ad and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ed and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7421; op2val:0xc3ad; +op3val:0x7bed; valaddr_reg:x5; val_offset:102*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x5, 102*FLEN/8, x9, x1, x2) + +inst_58: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x021 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3ad and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ed and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7421; op2val:0xc3ad; +op3val:0x7bed; valaddr_reg:x5; val_offset:105*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x5, 105*FLEN/8, x9, x1, x2) + +inst_59: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x021 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3ad and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ed and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7421; op2val:0xc3ad; +op3val:0x7bed; valaddr_reg:x5; val_offset:108*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x5, 108*FLEN/8, x9, x1, x2) + +inst_60: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x009 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0e9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0f5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c09; op2val:0xc8e9; +op3val:0x78f5; valaddr_reg:x5; val_offset:111*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 111*FLEN/8, x9, x1, x2) + +inst_61: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x009 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0e9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0f5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c09; op2val:0xc8e9; +op3val:0x78f5; valaddr_reg:x5; val_offset:114*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x5, 114*FLEN/8, x9, x1, x2) + +inst_62: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x009 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0e9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0f5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c09; op2val:0xc8e9; +op3val:0x78f5; valaddr_reg:x5; val_offset:117*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x5, 117*FLEN/8, x9, x1, x2) + +inst_63: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x009 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0e9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0f5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c09; op2val:0xc8e9; +op3val:0x78f5; valaddr_reg:x5; val_offset:120*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x5, 120*FLEN/8, x9, x1, x2) + +inst_64: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x009 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0e9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0f5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c09; op2val:0xc8e9; +op3val:0x78f5; valaddr_reg:x5; val_offset:123*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x5, 123*FLEN/8, x9, x1, x2) + +inst_65: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x208 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x301 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x148 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7608; op2val:0xbf01; +op3val:0x7948; valaddr_reg:x5; val_offset:126*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 126*FLEN/8, x9, x1, x2) + +inst_66: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x208 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x301 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x148 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7608; op2val:0xbf01; +op3val:0x7948; valaddr_reg:x5; val_offset:129*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x5, 129*FLEN/8, x9, x1, x2) + +inst_67: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x208 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x301 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x148 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7608; op2val:0xbf01; +op3val:0x7948; valaddr_reg:x5; val_offset:132*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x5, 132*FLEN/8, x9, x1, x2) + +inst_68: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x208 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x301 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x148 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7608; op2val:0xbf01; +op3val:0x7948; valaddr_reg:x5; val_offset:135*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x5, 135*FLEN/8, x9, x1, x2) + +inst_69: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x208 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x301 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x148 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7608; op2val:0xbf01; +op3val:0x7948; valaddr_reg:x5; val_offset:138*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x5, 138*FLEN/8, x9, x1, x2) + +inst_70: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x169 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x015 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x187 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7569; op2val:0xc015; +op3val:0x7987; valaddr_reg:x5; val_offset:141*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 141*FLEN/8, x9, x1, x2) + +inst_71: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x169 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x015 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x187 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7569; op2val:0xc015; +op3val:0x7987; valaddr_reg:x5; val_offset:144*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x5, 144*FLEN/8, x9, x1, x2) + +inst_72: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x169 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x015 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x187 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7569; op2val:0xc015; +op3val:0x7987; valaddr_reg:x5; val_offset:147*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x5, 147*FLEN/8, x9, x1, x2) + +inst_73: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x169 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x015 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x187 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7569; op2val:0xc015; +op3val:0x7987; valaddr_reg:x5; val_offset:150*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x5, 150*FLEN/8, x9, x1, x2) + +inst_74: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x169 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x015 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x187 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7569; op2val:0xc015; +op3val:0x7987; valaddr_reg:x5; val_offset:153*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x5, 153*FLEN/8, x9, x1, x2) + +inst_75: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3f5 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x139 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x131 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77f5; op2val:0xbd39; +op3val:0x7931; valaddr_reg:x5; val_offset:156*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 156*FLEN/8, x9, x1, x2) + +inst_76: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3f5 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x139 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x131 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77f5; op2val:0xbd39; +op3val:0x7931; valaddr_reg:x5; val_offset:159*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x5, 159*FLEN/8, x9, x1, x2) + +inst_77: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3f5 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x139 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x131 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77f5; op2val:0xbd39; +op3val:0x7931; valaddr_reg:x5; val_offset:162*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x5, 162*FLEN/8, x9, x1, x2) + +inst_78: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3f5 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x139 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x131 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77f5; op2val:0xbd39; +op3val:0x7931; valaddr_reg:x5; val_offset:165*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x5, 165*FLEN/8, x9, x1, x2) + +inst_79: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3f5 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x139 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x131 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77f5; op2val:0xbd39; +op3val:0x7931; valaddr_reg:x5; val_offset:168*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x5, 168*FLEN/8, x9, x1, x2) + +inst_80: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x335 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x129 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b35; op2val:0xb929; +op3val:0x78a6; valaddr_reg:x5; val_offset:171*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 171*FLEN/8, x9, x1, x2) + +inst_81: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x335 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x129 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b35; op2val:0xb929; +op3val:0x78a6; valaddr_reg:x5; val_offset:174*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x5, 174*FLEN/8, x9, x1, x2) + +inst_82: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x335 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x129 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b35; op2val:0xb929; +op3val:0x78a6; valaddr_reg:x5; val_offset:177*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x5, 177*FLEN/8, x9, x1, x2) + +inst_83: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x335 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x129 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b35; op2val:0xb929; +op3val:0x78a6; valaddr_reg:x5; val_offset:180*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x5, 180*FLEN/8, x9, x1, x2) + +inst_84: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x335 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x129 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b35; op2val:0xb929; +op3val:0x78a6; valaddr_reg:x5; val_offset:183*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x5, 183*FLEN/8, x9, x1, x2) + +inst_85: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x08b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x33f and fs3 == 0 and fe3 == 0x1b and fm3 == 0x01e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x708b; op2val:0xb73f; +op3val:0x6c1e; valaddr_reg:x5; val_offset:186*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 186*FLEN/8, x9, x1, x2) + +inst_86: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x08b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x33f and fs3 == 0 and fe3 == 0x1b and fm3 == 0x01e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x708b; op2val:0xb73f; +op3val:0x6c1e; valaddr_reg:x5; val_offset:189*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x5, 189*FLEN/8, x9, x1, x2) + +inst_87: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x08b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x33f and fs3 == 0 and fe3 == 0x1b and fm3 == 0x01e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x708b; op2val:0xb73f; +op3val:0x6c1e; valaddr_reg:x5; val_offset:192*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x5, 192*FLEN/8, x9, x1, x2) + +inst_88: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x08b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x33f and fs3 == 0 and fe3 == 0x1b and fm3 == 0x01e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x708b; op2val:0xb73f; +op3val:0x6c1e; valaddr_reg:x5; val_offset:195*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x5, 195*FLEN/8, x9, x1, x2) + +inst_89: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x08b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x33f and fs3 == 0 and fe3 == 0x1b and fm3 == 0x01e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x708b; op2val:0xb73f; +op3val:0x6c1e; valaddr_reg:x5; val_offset:198*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x5, 198*FLEN/8, x9, x1, x2) + +inst_90: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x390 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x021 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3d0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b90; op2val:0xb821; +op3val:0x77d0; valaddr_reg:x5; val_offset:201*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 201*FLEN/8, x9, x1, x2) + +inst_91: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x390 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x021 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3d0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b90; op2val:0xb821; +op3val:0x77d0; valaddr_reg:x5; val_offset:204*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x5, 204*FLEN/8, x9, x1, x2) + +inst_92: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x390 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x021 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3d0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b90; op2val:0xb821; +op3val:0x77d0; valaddr_reg:x5; val_offset:207*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x5, 207*FLEN/8, x9, x1, x2) + +inst_93: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x390 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x021 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3d0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b90; op2val:0xb821; +op3val:0x77d0; valaddr_reg:x5; val_offset:210*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x5, 210*FLEN/8, x9, x1, x2) + +inst_94: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x390 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x021 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3d0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b90; op2val:0xb821; +op3val:0x77d0; valaddr_reg:x5; val_offset:213*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x5, 213*FLEN/8, x9, x1, x2) + +inst_95: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x233 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x390 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7233; op2val:0xc4e1; +op3val:0x7b90; valaddr_reg:x5; val_offset:216*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 216*FLEN/8, x9, x1, x2) + +inst_96: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x233 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x390 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7233; op2val:0xc4e1; +op3val:0x7b90; valaddr_reg:x5; val_offset:219*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x5, 219*FLEN/8, x9, x1, x2) + +inst_97: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x233 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x390 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7233; op2val:0xc4e1; +op3val:0x7b90; valaddr_reg:x5; val_offset:222*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x5, 222*FLEN/8, x9, x1, x2) + +inst_98: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x233 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x390 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7233; op2val:0xc4e1; +op3val:0x7b90; valaddr_reg:x5; val_offset:225*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x5, 225*FLEN/8, x9, x1, x2) + +inst_99: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x233 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x390 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7233; op2val:0xc4e1; +op3val:0x7b90; valaddr_reg:x5; val_offset:228*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x5, 228*FLEN/8, x9, x1, x2) + +inst_100: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a1 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x109 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1d4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78a1; op2val:0xbd09; +op3val:0x79d4; valaddr_reg:x5; val_offset:231*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 231*FLEN/8, x9, x1, x2) + +inst_101: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a1 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x109 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1d4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78a1; op2val:0xbd09; +op3val:0x79d4; valaddr_reg:x5; val_offset:234*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x5, 234*FLEN/8, x9, x1, x2) + +inst_102: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a1 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x109 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1d4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78a1; op2val:0xbd09; +op3val:0x79d4; valaddr_reg:x5; val_offset:237*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x5, 237*FLEN/8, x9, x1, x2) + +inst_103: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a1 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x109 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1d4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78a1; op2val:0xbd09; +op3val:0x79d4; valaddr_reg:x5; val_offset:240*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x5, 240*FLEN/8, x9, x1, x2) + +inst_104: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a1 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x109 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1d4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78a1; op2val:0xbd09; +op3val:0x79d4; valaddr_reg:x5; val_offset:243*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x5, 243*FLEN/8, x9, x1, x2) + +inst_105: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x130 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x091 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b0b; op2val:0xb530; +op3val:0x7491; valaddr_reg:x5; val_offset:246*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 246*FLEN/8, x9, x1, x2) + +inst_106: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x130 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x091 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b0b; op2val:0xb530; +op3val:0x7491; valaddr_reg:x5; val_offset:249*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x5, 249*FLEN/8, x9, x1, x2) + +inst_107: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x130 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x091 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b0b; op2val:0xb530; +op3val:0x7491; valaddr_reg:x5; val_offset:252*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x5, 252*FLEN/8, x9, x1, x2) + +inst_108: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x130 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x091 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b0b; op2val:0xb530; +op3val:0x7491; valaddr_reg:x5; val_offset:255*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x5, 255*FLEN/8, x9, x1, x2) + +inst_109: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x130 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x091 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b0b; op2val:0xb530; +op3val:0x7491; valaddr_reg:x5; val_offset:258*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x5, 258*FLEN/8, x9, x1, x2) + +inst_110: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1b4 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ec and fs3 == 0 and fe3 == 0x1e and fm3 == 0x305 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75b4; op2val:0xc0ec; +op3val:0x7b05; valaddr_reg:x5; val_offset:261*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 261*FLEN/8, x9, x1, x2) + +inst_111: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1b4 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ec and fs3 == 0 and fe3 == 0x1e and fm3 == 0x305 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75b4; op2val:0xc0ec; +op3val:0x7b05; valaddr_reg:x5; val_offset:264*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x5, 264*FLEN/8, x9, x1, x2) + +inst_112: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1b4 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ec and fs3 == 0 and fe3 == 0x1e and fm3 == 0x305 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75b4; op2val:0xc0ec; +op3val:0x7b05; valaddr_reg:x5; val_offset:267*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x5, 267*FLEN/8, x9, x1, x2) + +inst_113: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1b4 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ec and fs3 == 0 and fe3 == 0x1e and fm3 == 0x305 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75b4; op2val:0xc0ec; +op3val:0x7b05; valaddr_reg:x5; val_offset:270*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x5, 270*FLEN/8, x9, x1, x2) + +inst_114: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1b4 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ec and fs3 == 0 and fe3 == 0x1e and fm3 == 0x305 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75b4; op2val:0xc0ec; +op3val:0x7b05; valaddr_reg:x5; val_offset:273*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x5, 273*FLEN/8, x9, x1, x2) + +inst_115: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x051 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1a9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x21c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7051; op2val:0xc5a9; +op3val:0x7a1c; valaddr_reg:x5; val_offset:276*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 276*FLEN/8, x9, x1, x2) + +inst_116: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x051 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1a9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x21c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7051; op2val:0xc5a9; +op3val:0x7a1c; valaddr_reg:x5; val_offset:279*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x5, 279*FLEN/8, x9, x1, x2) + +inst_117: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x051 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1a9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x21c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7051; op2val:0xc5a9; +op3val:0x7a1c; valaddr_reg:x5; val_offset:282*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x5, 282*FLEN/8, x9, x1, x2) + +inst_118: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x051 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1a9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x21c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7051; op2val:0xc5a9; +op3val:0x7a1c; valaddr_reg:x5; val_offset:285*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x5, 285*FLEN/8, x9, x1, x2) + +inst_119: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x051 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1a9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x21c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7051; op2val:0xc5a9; +op3val:0x7a1c; valaddr_reg:x5; val_offset:288*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x5, 288*FLEN/8, x9, x1, x2) + +inst_120: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x23e and fs2 == 1 and fe2 == 0x11 and fm2 == 0x311 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x184 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e3e; op2val:0xc711; +op3val:0x7984; valaddr_reg:x5; val_offset:291*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 291*FLEN/8, x9, x1, x2) + +inst_121: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x23e and fs2 == 1 and fe2 == 0x11 and fm2 == 0x311 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x184 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e3e; op2val:0xc711; +op3val:0x7984; valaddr_reg:x5; val_offset:294*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x5, 294*FLEN/8, x9, x1, x2) + +inst_122: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x23e and fs2 == 1 and fe2 == 0x11 and fm2 == 0x311 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x184 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e3e; op2val:0xc711; +op3val:0x7984; valaddr_reg:x5; val_offset:297*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x5, 297*FLEN/8, x9, x1, x2) + +inst_123: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x23e and fs2 == 1 and fe2 == 0x11 and fm2 == 0x311 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x184 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e3e; op2val:0xc711; +op3val:0x7984; valaddr_reg:x5; val_offset:300*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x5, 300*FLEN/8, x9, x1, x2) + +inst_124: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x23e and fs2 == 1 and fe2 == 0x11 and fm2 == 0x311 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x184 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e3e; op2val:0xc711; +op3val:0x7984; valaddr_reg:x5; val_offset:303*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x5, 303*FLEN/8, x9, x1, x2) + +inst_125: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x169 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x398 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x799d; op2val:0xbd69; +op3val:0x7b98; valaddr_reg:x5; val_offset:306*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 306*FLEN/8, x9, x1, x2) + +inst_126: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x169 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x398 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x799d; op2val:0xbd69; +op3val:0x7b98; valaddr_reg:x5; val_offset:309*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x5, 309*FLEN/8, x9, x1, x2) + +inst_127: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x169 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x398 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x799d; op2val:0xbd69; +op3val:0x7b98; valaddr_reg:x5; val_offset:312*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x5, 312*FLEN/8, x9, x1, x2) + +inst_128: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x169 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x398 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x799d; op2val:0xbd69; +op3val:0x7b98; valaddr_reg:x5; val_offset:315*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x5, 315*FLEN/8, x9, x1, x2) + +inst_129: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x169 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x398 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x799d; op2val:0xbd69; +op3val:0x7b98; valaddr_reg:x5; val_offset:318*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x5, 318*FLEN/8, x9, x1, x2) + +inst_130: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2be and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0c6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x006 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7abe; op2val:0xb8c6; +op3val:0x7806; valaddr_reg:x5; val_offset:321*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 321*FLEN/8, x9, x1, x2) + +inst_131: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2be and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0c6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x006 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7abe; op2val:0xb8c6; +op3val:0x7806; valaddr_reg:x5; val_offset:324*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x5, 324*FLEN/8, x9, x1, x2) + +inst_132: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2be and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0c6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x006 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7abe; op2val:0xb8c6; +op3val:0x7806; valaddr_reg:x5; val_offset:327*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x5, 327*FLEN/8, x9, x1, x2) + +inst_133: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2be and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0c6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x006 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7abe; op2val:0xb8c6; +op3val:0x7806; valaddr_reg:x5; val_offset:330*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x5, 330*FLEN/8, x9, x1, x2) + +inst_134: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2be and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0c6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x006 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7abe; op2val:0xb8c6; +op3val:0x7806; valaddr_reg:x5; val_offset:333*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x5, 333*FLEN/8, x9, x1, x2) + +inst_135: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x252 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x213 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0cd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7252; op2val:0xba13; +op3val:0x70cd; valaddr_reg:x5; val_offset:336*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 336*FLEN/8, x9, x1, x2) + +inst_136: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x252 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x213 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0cd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7252; op2val:0xba13; +op3val:0x70cd; valaddr_reg:x5; val_offset:339*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x5, 339*FLEN/8, x9, x1, x2) + +inst_137: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x252 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x213 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0cd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7252; op2val:0xba13; +op3val:0x70cd; valaddr_reg:x5; val_offset:342*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x5, 342*FLEN/8, x9, x1, x2) + +inst_138: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x252 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x213 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0cd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7252; op2val:0xba13; +op3val:0x70cd; valaddr_reg:x5; val_offset:345*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x5, 345*FLEN/8, x9, x1, x2) + +inst_139: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x252 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x213 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0cd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7252; op2val:0xba13; +op3val:0x70cd; valaddr_reg:x5; val_offset:348*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x5, 348*FLEN/8, x9, x1, x2) + +inst_140: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x03a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x013 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x783a; op2val:0xbbb6; +op3val:0x7813; valaddr_reg:x5; val_offset:351*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 351*FLEN/8, x9, x1, x2) + +inst_141: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x03a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x013 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x783a; op2val:0xbbb6; +op3val:0x7813; valaddr_reg:x5; val_offset:354*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x5, 354*FLEN/8, x9, x1, x2) + +inst_142: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x03a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x013 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x783a; op2val:0xbbb6; +op3val:0x7813; valaddr_reg:x5; val_offset:357*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x5, 357*FLEN/8, x9, x1, x2) + +inst_143: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x03a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x013 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x783a; op2val:0xbbb6; +op3val:0x7813; valaddr_reg:x5; val_offset:360*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x5, 360*FLEN/8, x9, x1, x2) + +inst_144: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x03a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x013 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x783a; op2val:0xbbb6; +op3val:0x7813; valaddr_reg:x5; val_offset:363*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x5, 363*FLEN/8, x9, x1, x2) + +inst_145: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x091 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x252 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x338 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c91; op2val:0xca52; +op3val:0x7b38; valaddr_reg:x5; val_offset:366*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 366*FLEN/8, x9, x1, x2) + +inst_146: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x091 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x252 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x338 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c91; op2val:0xca52; +op3val:0x7b38; valaddr_reg:x5; val_offset:369*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x5, 369*FLEN/8, x9, x1, x2) + +inst_147: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x091 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x252 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x338 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c91; op2val:0xca52; +op3val:0x7b38; valaddr_reg:x5; val_offset:372*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x5, 372*FLEN/8, x9, x1, x2) + +inst_148: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x091 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x252 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x338 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c91; op2val:0xca52; +op3val:0x7b38; valaddr_reg:x5; val_offset:375*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x5, 375*FLEN/8, x9, x1, x2) + +inst_149: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x091 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x252 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x338 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c91; op2val:0xca52; +op3val:0x7b38; valaddr_reg:x5; val_offset:378*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x5, 378*FLEN/8, x9, x1, x2) + +inst_150: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x187 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x19b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x780e; op2val:0xbd87; +op3val:0x799b; valaddr_reg:x5; val_offset:381*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 381*FLEN/8, x9, x1, x2) + +inst_151: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x187 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x19b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x780e; op2val:0xbd87; +op3val:0x799b; valaddr_reg:x5; val_offset:384*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x5, 384*FLEN/8, x9, x1, x2) + +inst_152: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x187 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x19b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x780e; op2val:0xbd87; +op3val:0x799b; valaddr_reg:x5; val_offset:387*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x5, 387*FLEN/8, x9, x1, x2) + +inst_153: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x187 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x19b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x780e; op2val:0xbd87; +op3val:0x799b; valaddr_reg:x5; val_offset:390*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x5, 390*FLEN/8, x9, x1, x2) + +inst_154: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x187 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x19b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x780e; op2val:0xbd87; +op3val:0x799b; valaddr_reg:x5; val_offset:393*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x5, 393*FLEN/8, x9, x1, x2) + +inst_155: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x309 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x06f and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3cd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7309; op2val:0xbc6f; +op3val:0x73cd; valaddr_reg:x5; val_offset:396*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 396*FLEN/8, x9, x1, x2) + +inst_156: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x309 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x06f and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3cd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7309; op2val:0xbc6f; +op3val:0x73cd; valaddr_reg:x5; val_offset:399*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x5, 399*FLEN/8, x9, x1, x2) + +inst_157: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x309 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x06f and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3cd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7309; op2val:0xbc6f; +op3val:0x73cd; valaddr_reg:x5; val_offset:402*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x5, 402*FLEN/8, x9, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_158: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x309 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x06f and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3cd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7309; op2val:0xbc6f; +op3val:0x73cd; valaddr_reg:x5; val_offset:405*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x5, 405*FLEN/8, x9, x1, x2) + +inst_159: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x309 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x06f and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3cd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7309; op2val:0xbc6f; +op3val:0x73cd; valaddr_reg:x5; val_offset:408*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x5, 408*FLEN/8, x9, x1, x2) + +inst_160: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x21b and fs2 == 1 and fe2 == 0x13 and fm2 == 0x331 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x17d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x621b; op2val:0xcf31; +op3val:0x757d; valaddr_reg:x5; val_offset:411*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 411*FLEN/8, x9, x1, x2) + +inst_161: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x21b and fs2 == 1 and fe2 == 0x13 and fm2 == 0x331 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x17d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x621b; op2val:0xcf31; +op3val:0x757d; valaddr_reg:x5; val_offset:414*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x5, 414*FLEN/8, x9, x1, x2) + +inst_162: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x21b and fs2 == 1 and fe2 == 0x13 and fm2 == 0x331 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x17d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x621b; op2val:0xcf31; +op3val:0x757d; valaddr_reg:x5; val_offset:417*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x5, 417*FLEN/8, x9, x1, x2) + +inst_163: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x21b and fs2 == 1 and fe2 == 0x13 and fm2 == 0x331 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x17d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x621b; op2val:0xcf31; +op3val:0x757d; valaddr_reg:x5; val_offset:420*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x5, 420*FLEN/8, x9, x1, x2) + +inst_164: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x21b and fs2 == 1 and fe2 == 0x13 and fm2 == 0x331 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x17d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x621b; op2val:0xcf31; +op3val:0x757d; valaddr_reg:x5; val_offset:423*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x5, 423*FLEN/8, x9, x1, x2) + +inst_165: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x044 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x258 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2c5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7444; op2val:0xbe58; +op3val:0x76c5; valaddr_reg:x5; val_offset:426*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 426*FLEN/8, x9, x1, x2) + +inst_166: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x044 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x258 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2c5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7444; op2val:0xbe58; +op3val:0x76c5; valaddr_reg:x5; val_offset:429*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x5, 429*FLEN/8, x9, x1, x2) + +inst_167: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x044 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x258 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2c5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7444; op2val:0xbe58; +op3val:0x76c5; valaddr_reg:x5; val_offset:432*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x5, 432*FLEN/8, x9, x1, x2) + +inst_168: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x044 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x258 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2c5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7444; op2val:0xbe58; +op3val:0x76c5; valaddr_reg:x5; val_offset:435*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x5, 435*FLEN/8, x9, x1, x2) + +inst_169: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x044 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x258 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2c5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7444; op2val:0xbe58; +op3val:0x76c5; valaddr_reg:x5; val_offset:438*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x5, 438*FLEN/8, x9, x1, x2) + +inst_170: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x207 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x06d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ab and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7607; op2val:0xc06d; +op3val:0x7aab; valaddr_reg:x5; val_offset:441*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 441*FLEN/8, x9, x1, x2) + +inst_171: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x207 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x06d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ab and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7607; op2val:0xc06d; +op3val:0x7aab; valaddr_reg:x5; val_offset:444*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x5, 444*FLEN/8, x9, x1, x2) + +inst_172: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x207 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x06d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ab and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7607; op2val:0xc06d; +op3val:0x7aab; valaddr_reg:x5; val_offset:447*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x5, 447*FLEN/8, x9, x1, x2) + +inst_173: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x207 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x06d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ab and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7607; op2val:0xc06d; +op3val:0x7aab; valaddr_reg:x5; val_offset:450*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x5, 450*FLEN/8, x9, x1, x2) + +inst_174: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x207 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x06d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ab and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7607; op2val:0xc06d; +op3val:0x7aab; valaddr_reg:x5; val_offset:453*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x5, 453*FLEN/8, x9, x1, x2) + +inst_175: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x320 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x24a and fs3 == 0 and fe3 == 0x1c and fm3 == 0x19b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b20; op2val:0xb24a; +op3val:0x719b; valaddr_reg:x5; val_offset:456*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 456*FLEN/8, x9, x1, x2) + +inst_176: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x320 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x24a and fs3 == 0 and fe3 == 0x1c and fm3 == 0x19b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b20; op2val:0xb24a; +op3val:0x719b; valaddr_reg:x5; val_offset:459*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x5, 459*FLEN/8, x9, x1, x2) + +inst_177: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x320 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x24a and fs3 == 0 and fe3 == 0x1c and fm3 == 0x19b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b20; op2val:0xb24a; +op3val:0x719b; valaddr_reg:x5; val_offset:462*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x5, 462*FLEN/8, x9, x1, x2) + +inst_178: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x320 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x24a and fs3 == 0 and fe3 == 0x1c and fm3 == 0x19b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b20; op2val:0xb24a; +op3val:0x719b; valaddr_reg:x5; val_offset:465*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x5, 465*FLEN/8, x9, x1, x2) + +inst_179: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x320 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x24a and fs3 == 0 and fe3 == 0x1c and fm3 == 0x19b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b20; op2val:0xb24a; +op3val:0x719b; valaddr_reg:x5; val_offset:468*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x5, 468*FLEN/8, x9, x1, x2) + +inst_180: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x256 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2b5 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x150 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7656; op2val:0xb6b5; +op3val:0x7150; valaddr_reg:x5; val_offset:471*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 471*FLEN/8, x9, x1, x2) + +inst_181: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x256 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2b5 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x150 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7656; op2val:0xb6b5; +op3val:0x7150; valaddr_reg:x5; val_offset:474*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x5, 474*FLEN/8, x9, x1, x2) + +inst_182: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x256 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2b5 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x150 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7656; op2val:0xb6b5; +op3val:0x7150; valaddr_reg:x5; val_offset:477*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x5, 477*FLEN/8, x9, x1, x2) + +inst_183: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x256 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2b5 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x150 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7656; op2val:0xb6b5; +op3val:0x7150; valaddr_reg:x5; val_offset:480*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x5, 480*FLEN/8, x9, x1, x2) + +inst_184: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x256 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2b5 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x150 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7656; op2val:0xb6b5; +op3val:0x7150; valaddr_reg:x5; val_offset:483*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x5, 483*FLEN/8, x9, x1, x2) + +inst_185: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x14d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3cb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x794d; op2val:0xbde1; +op3val:0x7bcb; valaddr_reg:x5; val_offset:486*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 486*FLEN/8, x9, x1, x2) + +inst_186: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x14d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3cb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x794d; op2val:0xbde1; +op3val:0x7bcb; valaddr_reg:x5; val_offset:489*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x5, 489*FLEN/8, x9, x1, x2) + +inst_187: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x14d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3cb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x794d; op2val:0xbde1; +op3val:0x7bcb; valaddr_reg:x5; val_offset:492*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x5, 492*FLEN/8, x9, x1, x2) + +inst_188: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x14d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3cb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x794d; op2val:0xbde1; +op3val:0x7bcb; valaddr_reg:x5; val_offset:495*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x5, 495*FLEN/8, x9, x1, x2) + +inst_189: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x14d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3cb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x794d; op2val:0xbde1; +op3val:0x7bcb; valaddr_reg:x5; val_offset:498*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x5, 498*FLEN/8, x9, x1, x2) + +inst_190: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x274 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x398 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x220 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7274; op2val:0xc398; +op3val:0x7a20; valaddr_reg:x5; val_offset:501*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 501*FLEN/8, x9, x1, x2) + +inst_191: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x274 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x398 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x220 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7274; op2val:0xc398; +op3val:0x7a20; valaddr_reg:x5; val_offset:504*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x5, 504*FLEN/8, x9, x1, x2) + +inst_192: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x274 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x398 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x220 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7274; op2val:0xc398; +op3val:0x7a20; valaddr_reg:x5; val_offset:507*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x5, 507*FLEN/8, x9, x1, x2) + +inst_193: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x274 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x398 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x220 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7274; op2val:0xc398; +op3val:0x7a20; valaddr_reg:x5; val_offset:510*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x5, 510*FLEN/8, x9, x1, x2) + +inst_194: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x274 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x398 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x220 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7274; op2val:0xc398; +op3val:0x7a20; valaddr_reg:x5; val_offset:513*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x5, 513*FLEN/8, x9, x1, x2) + +inst_195: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0cc and fs2 == 1 and fe2 == 0x0a and fm2 == 0x1a5 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x2c5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74cc; op2val:0xa9a5; +op3val:0x62c5; valaddr_reg:x5; val_offset:516*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 516*FLEN/8, x9, x1, x2) + +inst_196: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0cc and fs2 == 1 and fe2 == 0x0a and fm2 == 0x1a5 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x2c5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74cc; op2val:0xa9a5; +op3val:0x62c5; valaddr_reg:x5; val_offset:519*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x5, 519*FLEN/8, x9, x1, x2) + +inst_197: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0cc and fs2 == 1 and fe2 == 0x0a and fm2 == 0x1a5 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x2c5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74cc; op2val:0xa9a5; +op3val:0x62c5; valaddr_reg:x5; val_offset:522*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x5, 522*FLEN/8, x9, x1, x2) + +inst_198: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0cc and fs2 == 1 and fe2 == 0x0a and fm2 == 0x1a5 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x2c5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74cc; op2val:0xa9a5; +op3val:0x62c5; valaddr_reg:x5; val_offset:525*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x5, 525*FLEN/8, x9, x1, x2) + +inst_199: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0cc and fs2 == 1 and fe2 == 0x0a and fm2 == 0x1a5 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x2c5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74cc; op2val:0xa9a5; +op3val:0x62c5; valaddr_reg:x5; val_offset:528*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x5, 528*FLEN/8, x9, x1, x2) + +inst_200: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x21c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x327 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x177 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a1c; op2val:0xb727; +op3val:0x7577; valaddr_reg:x5; val_offset:531*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 531*FLEN/8, x9, x1, x2) + +inst_201: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x21c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x327 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x177 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a1c; op2val:0xb727; +op3val:0x7577; valaddr_reg:x5; val_offset:534*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x5, 534*FLEN/8, x9, x1, x2) + +inst_202: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x21c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x327 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x177 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a1c; op2val:0xb727; +op3val:0x7577; valaddr_reg:x5; val_offset:537*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x5, 537*FLEN/8, x9, x1, x2) + +inst_203: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x21c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x327 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x177 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a1c; op2val:0xb727; +op3val:0x7577; valaddr_reg:x5; val_offset:540*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x5, 540*FLEN/8, x9, x1, x2) + +inst_204: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x21c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x327 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x177 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a1c; op2val:0xb727; +op3val:0x7577; valaddr_reg:x5; val_offset:543*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x5, 543*FLEN/8, x9, x1, x2) + +inst_205: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x171 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x11e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2f7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7171; op2val:0xc11e; +op3val:0x76f7; valaddr_reg:x5; val_offset:546*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 546*FLEN/8, x9, x1, x2) + +inst_206: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x171 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x11e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2f7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7171; op2val:0xc11e; +op3val:0x76f7; valaddr_reg:x5; val_offset:549*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x5, 549*FLEN/8, x9, x1, x2) + +inst_207: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x171 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x11e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2f7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7171; op2val:0xc11e; +op3val:0x76f7; valaddr_reg:x5; val_offset:552*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x5, 552*FLEN/8, x9, x1, x2) + +inst_208: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x171 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x11e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2f7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7171; op2val:0xc11e; +op3val:0x76f7; valaddr_reg:x5; val_offset:555*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x5, 555*FLEN/8, x9, x1, x2) + +inst_209: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x171 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x11e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2f7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7171; op2val:0xc11e; +op3val:0x76f7; valaddr_reg:x5; val_offset:558*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x5, 558*FLEN/8, x9, x1, x2) + +inst_210: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x369 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x314 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x28e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7369; op2val:0xbf14; +op3val:0x768e; valaddr_reg:x5; val_offset:561*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 561*FLEN/8, x9, x1, x2) + +inst_211: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x369 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x314 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x28e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7369; op2val:0xbf14; +op3val:0x768e; valaddr_reg:x5; val_offset:564*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x5, 564*FLEN/8, x9, x1, x2) + +inst_212: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x369 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x314 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x28e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7369; op2val:0xbf14; +op3val:0x768e; valaddr_reg:x5; val_offset:567*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x5, 567*FLEN/8, x9, x1, x2) + +inst_213: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x369 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x314 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x28e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7369; op2val:0xbf14; +op3val:0x768e; valaddr_reg:x5; val_offset:570*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x5, 570*FLEN/8, x9, x1, x2) + +inst_214: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x369 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x314 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x28e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7369; op2val:0xbf14; +op3val:0x768e; valaddr_reg:x5; val_offset:573*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x5, 573*FLEN/8, x9, x1, x2) + +inst_215: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x322 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x37f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2af and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7722; op2val:0xbb7f; +op3val:0x76af; valaddr_reg:x5; val_offset:576*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 576*FLEN/8, x9, x1, x2) + +inst_216: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x322 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x37f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2af and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7722; op2val:0xbb7f; +op3val:0x76af; valaddr_reg:x5; val_offset:579*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x5, 579*FLEN/8, x9, x1, x2) + +inst_217: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x322 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x37f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2af and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7722; op2val:0xbb7f; +op3val:0x76af; valaddr_reg:x5; val_offset:582*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x5, 582*FLEN/8, x9, x1, x2) + +inst_218: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x322 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x37f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2af and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7722; op2val:0xbb7f; +op3val:0x76af; valaddr_reg:x5; val_offset:585*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x5, 585*FLEN/8, x9, x1, x2) + +inst_219: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x322 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x37f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2af and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7722; op2val:0xbb7f; +op3val:0x76af; valaddr_reg:x5; val_offset:588*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x5, 588*FLEN/8, x9, x1, x2) + +inst_220: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x340 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x03e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7340; op2val:0xc43e; +op3val:0x7bb1; valaddr_reg:x5; val_offset:591*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x5, 591*FLEN/8, x9, x1, x2) + +inst_221: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x340 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x03e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7340; op2val:0xc43e; +op3val:0x7bb1; valaddr_reg:x5; val_offset:594*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x5, 594*FLEN/8, x9, x1, x2) + +inst_222: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x340 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x03e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7340; op2val:0xc43e; +op3val:0x7bb1; valaddr_reg:x5; val_offset:597*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x5, 597*FLEN/8, x9, x1, x2) + +inst_223: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x00a and fs2 == 1 and fe2 == 0x11 and fm2 == 0x194 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x700a; op2val:0xc594; +op3val:0x79a2; valaddr_reg:x5; val_offset:600*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x5, 600*FLEN/8, x9, x1, x2) + +inst_224: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x00a and fs2 == 1 and fe2 == 0x11 and fm2 == 0x194 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x700a; op2val:0xc594; +op3val:0x79a2; valaddr_reg:x5; val_offset:603*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x5, 603*FLEN/8, x9, x1, x2) + +inst_225: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x00a and fs2 == 1 and fe2 == 0x11 and fm2 == 0x194 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x700a; op2val:0xc594; +op3val:0x79a2; valaddr_reg:x5; val_offset:606*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x5, 606*FLEN/8, x9, x1, x2) + +inst_226: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x00a and fs2 == 1 and fe2 == 0x11 and fm2 == 0x194 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x700a; op2val:0xc594; +op3val:0x79a2; valaddr_reg:x5; val_offset:609*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x5, 609*FLEN/8, x9, x1, x2) + +inst_227: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x173 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1cf and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3ea and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d73; op2val:0xc1cf; +op3val:0x73ea; valaddr_reg:x5; val_offset:612*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x5, 612*FLEN/8, x9, x1, x2) + +inst_228: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x121 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1b8 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x357 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7921; op2val:0xb9b8; +op3val:0x7757; valaddr_reg:x5; val_offset:615*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x5, 615*FLEN/8, x9, x1, x2) + +inst_229: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x33f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x05e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3ea and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x773f; op2val:0xbc5e; +op3val:0x77ea; valaddr_reg:x5; val_offset:618*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x5, 618*FLEN/8, x9, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(29504,32,FLEN) +NAN_BOXED(29504,16,FLEN) +NAN_BOXED(31665,32,FLEN) +NAN_BOXED(29504,32,FLEN) +NAN_BOXED(50238,16,FLEN) +NAN_BOXED(31665,32,FLEN) +NAN_BOXED(29504,32,FLEN) +NAN_BOXED(50238,16,FLEN) +NAN_BOXED(31665,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(50238,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(29504,32,FLEN) +NAN_BOXED(29504,16,FLEN) +NAN_BOXED(29504,32,FLEN) +NAN_BOXED(28682,32,FLEN) +NAN_BOXED(50580,16,FLEN) +NAN_BOXED(31138,32,FLEN) +NAN_BOXED(28682,32,FLEN) +NAN_BOXED(50580,16,FLEN) +NAN_BOXED(50580,32,FLEN) +NAN_BOXED(28682,32,FLEN) +NAN_BOXED(50580,16,FLEN) +NAN_BOXED(28682,32,FLEN) +NAN_BOXED(28682,32,FLEN) +NAN_BOXED(28682,16,FLEN) +NAN_BOXED(28682,32,FLEN) +NAN_BOXED(28682,32,FLEN) +NAN_BOXED(28682,16,FLEN) +NAN_BOXED(31138,32,FLEN) +NAN_BOXED(28019,32,FLEN) +NAN_BOXED(49615,16,FLEN) +NAN_BOXED(29674,32,FLEN) +NAN_BOXED(28019,32,FLEN) +NAN_BOXED(49615,16,FLEN) +NAN_BOXED(49615,32,FLEN) +NAN_BOXED(28019,32,FLEN) +NAN_BOXED(49615,16,FLEN) +NAN_BOXED(29674,32,FLEN) +test_dataset_1: +NAN_BOXED(28019,32,FLEN) +NAN_BOXED(49615,16,FLEN) +NAN_BOXED(29674,32,FLEN) +NAN_BOXED(28019,32,FLEN) +NAN_BOXED(49615,16,FLEN) +NAN_BOXED(29674,32,FLEN) +NAN_BOXED(31741,32,FLEN) +NAN_BOXED(45748,16,FLEN) +NAN_BOXED(29362,32,FLEN) +NAN_BOXED(31741,32,FLEN) +NAN_BOXED(45748,16,FLEN) +NAN_BOXED(29362,32,FLEN) +NAN_BOXED(31741,32,FLEN) +NAN_BOXED(45748,16,FLEN) +NAN_BOXED(29362,32,FLEN) +NAN_BOXED(31741,32,FLEN) +NAN_BOXED(45748,16,FLEN) +NAN_BOXED(29362,32,FLEN) +NAN_BOXED(31741,32,FLEN) +NAN_BOXED(45748,16,FLEN) +NAN_BOXED(29362,32,FLEN) +NAN_BOXED(31009,32,FLEN) +NAN_BOXED(47544,16,FLEN) +NAN_BOXED(30551,32,FLEN) +NAN_BOXED(31009,32,FLEN) +NAN_BOXED(47544,16,FLEN) +NAN_BOXED(30551,32,FLEN) +NAN_BOXED(31009,32,FLEN) +NAN_BOXED(47544,16,FLEN) +NAN_BOXED(30551,32,FLEN) +test_dataset_2: +NAN_BOXED(31009,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(30551,16,FLEN) +NAN_BOXED(31009,16,FLEN) +NAN_BOXED(47544,16,FLEN) +NAN_BOXED(30551,16,FLEN) +NAN_BOXED(30527,16,FLEN) +NAN_BOXED(48222,16,FLEN) +NAN_BOXED(30698,16,FLEN) +NAN_BOXED(30527,16,FLEN) +NAN_BOXED(48222,16,FLEN) +NAN_BOXED(30698,16,FLEN) +NAN_BOXED(30527,16,FLEN) +NAN_BOXED(48222,16,FLEN) +NAN_BOXED(30698,16,FLEN) +NAN_BOXED(30527,16,FLEN) +NAN_BOXED(48222,16,FLEN) +NAN_BOXED(30698,16,FLEN) +NAN_BOXED(30527,16,FLEN) +NAN_BOXED(48222,16,FLEN) +NAN_BOXED(30698,16,FLEN) +NAN_BOXED(29222,16,FLEN) +NAN_BOXED(50257,16,FLEN) +NAN_BOXED(31396,16,FLEN) +NAN_BOXED(29222,16,FLEN) +NAN_BOXED(50257,16,FLEN) +NAN_BOXED(31396,16,FLEN) +NAN_BOXED(29222,16,FLEN) +NAN_BOXED(50257,16,FLEN) +NAN_BOXED(31396,16,FLEN) +NAN_BOXED(29222,16,FLEN) +NAN_BOXED(50257,16,FLEN) +NAN_BOXED(31396,16,FLEN) +NAN_BOXED(29222,16,FLEN) +NAN_BOXED(50257,16,FLEN) +NAN_BOXED(31396,16,FLEN) +NAN_BOXED(28090,16,FLEN) +NAN_BOXED(49466,16,FLEN) +NAN_BOXED(29565,16,FLEN) +NAN_BOXED(28090,16,FLEN) +NAN_BOXED(49466,16,FLEN) +NAN_BOXED(29565,16,FLEN) +NAN_BOXED(28090,16,FLEN) +NAN_BOXED(49466,16,FLEN) +NAN_BOXED(29565,16,FLEN) +NAN_BOXED(28090,16,FLEN) +NAN_BOXED(49466,16,FLEN) +NAN_BOXED(29565,16,FLEN) +NAN_BOXED(28090,16,FLEN) +NAN_BOXED(49466,16,FLEN) +NAN_BOXED(29565,16,FLEN) +NAN_BOXED(25886,16,FLEN) +NAN_BOXED(51882,16,FLEN) +NAN_BOXED(29764,16,FLEN) +NAN_BOXED(25886,16,FLEN) +NAN_BOXED(51882,16,FLEN) +NAN_BOXED(29764,16,FLEN) +NAN_BOXED(25886,16,FLEN) +NAN_BOXED(51882,16,FLEN) +NAN_BOXED(29764,16,FLEN) +NAN_BOXED(25886,16,FLEN) +NAN_BOXED(51882,16,FLEN) +NAN_BOXED(29764,16,FLEN) +NAN_BOXED(25886,16,FLEN) +NAN_BOXED(51882,16,FLEN) +NAN_BOXED(29764,16,FLEN) +NAN_BOXED(30341,16,FLEN) +NAN_BOXED(49260,16,FLEN) +NAN_BOXED(31542,16,FLEN) +NAN_BOXED(30341,16,FLEN) +NAN_BOXED(49260,16,FLEN) +NAN_BOXED(31542,16,FLEN) +NAN_BOXED(30341,16,FLEN) +NAN_BOXED(49260,16,FLEN) +NAN_BOXED(31542,16,FLEN) +NAN_BOXED(30341,16,FLEN) +NAN_BOXED(49260,16,FLEN) +NAN_BOXED(31542,16,FLEN) +NAN_BOXED(30341,16,FLEN) +NAN_BOXED(49260,16,FLEN) +NAN_BOXED(31542,16,FLEN) +NAN_BOXED(30223,16,FLEN) +NAN_BOXED(46285,16,FLEN) +NAN_BOXED(28486,16,FLEN) +NAN_BOXED(30223,16,FLEN) +NAN_BOXED(46285,16,FLEN) +NAN_BOXED(28486,16,FLEN) +NAN_BOXED(30223,16,FLEN) +NAN_BOXED(46285,16,FLEN) +NAN_BOXED(28486,16,FLEN) +NAN_BOXED(30223,16,FLEN) +NAN_BOXED(46285,16,FLEN) +NAN_BOXED(28486,16,FLEN) +NAN_BOXED(30223,16,FLEN) +NAN_BOXED(46285,16,FLEN) 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+NAN_BOXED(47999,16,FLEN) +NAN_BOXED(30383,16,FLEN) +NAN_BOXED(29504,16,FLEN) +NAN_BOXED(50238,16,FLEN) +NAN_BOXED(31665,16,FLEN) +NAN_BOXED(29504,16,FLEN) +NAN_BOXED(50238,16,FLEN) +NAN_BOXED(31665,16,FLEN) +NAN_BOXED(29504,16,FLEN) +NAN_BOXED(50238,16,FLEN) +NAN_BOXED(31665,16,FLEN) +NAN_BOXED(28682,16,FLEN) +NAN_BOXED(50580,16,FLEN) +NAN_BOXED(31138,16,FLEN) +NAN_BOXED(28682,16,FLEN) +NAN_BOXED(50580,16,FLEN) +NAN_BOXED(31138,16,FLEN) +NAN_BOXED(28682,16,FLEN) +NAN_BOXED(50580,16,FLEN) +NAN_BOXED(31138,16,FLEN) +NAN_BOXED(28682,16,FLEN) +NAN_BOXED(50580,16,FLEN) +NAN_BOXED(31138,16,FLEN) +NAN_BOXED(28019,16,FLEN) +NAN_BOXED(49615,16,FLEN) +NAN_BOXED(29674,16,FLEN) +NAN_BOXED(31009,16,FLEN) +NAN_BOXED(47544,16,FLEN) +NAN_BOXED(30551,16,FLEN) +NAN_BOXED(30527,16,FLEN) +NAN_BOXED(48222,16,FLEN) +NAN_BOXED(30698,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x9_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x9_1: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x3_0: + .fill 32*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_0: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 144*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fnmsub_b6-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fnmsub_b6-01.S new file mode 100644 index 000000000..df6ff27cf --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fnmsub_b6-01.S @@ -0,0 +1,476 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 06:07:02 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fnmsub.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fnmsub.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fnmsub_b6 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fnmsub_b6) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x10,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==x31, rs2==x31, rs3==x21, rd==x24,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x31; op2:x31; op3:x21; dest:x24; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x10; val_offset:0*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x24, x31, x31, x21, dyn, 0, 0, x10, 0*FLEN/8, x12, x1, x3) + +inst_1: +// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==x9, rs2==x13, rs3==x16, rd==x9,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x9; op2:x13; op3:x16; dest:x9; op1val:0x0; op2val:0x7bff; +op3val:0x0; valaddr_reg:x10; val_offset:3*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x9, x9, x13, x16, dyn, 32, 0, x10, 3*FLEN/8, x12, x1, x3) + +inst_2: +// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==x14, rs2==x23, rs3==x22, rd==x21,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x14; op2:x23; op3:x22; dest:x21; op1val:0x0; op2val:0x7bff; +op3val:0x0; valaddr_reg:x10; val_offset:6*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x21, x14, x23, x22, dyn, 64, 0, x10, 6*FLEN/8, x12, x1, x3) + +inst_3: +// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==x7, rs2==x4, rs3==x7, rd==x19,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x7; op2:x4; op3:x7; dest:x19; op1val:0x0; op2val:0x7bff; +op3val:0x0; valaddr_reg:x10; val_offset:9*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x19, x7, x4, x7, dyn, 96, 0, x10, 9*FLEN/8, x12, x1, x3) + +inst_4: +// rs1 == rs2 == rs3 != rd, rs1==x0, rs2==x0, rs3==x0, rd==x17,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x0; op2:x0; op3:x0; dest:x17; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x10; val_offset:12*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x17, x0, x0, x0, dyn, 128, 0, x10, 12*FLEN/8, x12, x1, x3) + +inst_5: +// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==x22, rs2==x24, rs3==x25, rd==x25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x22; op2:x24; op3:x25; dest:x25; op1val:0x0; op2val:0xfbff; +op3val:0x0; valaddr_reg:x10; val_offset:15*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x25, x22, x24, x25, dyn, 0, 0, x10, 15*FLEN/8, x12, x1, x3) + +inst_6: +// rd == rs2 == rs3 != rs1, rs1==x8, rs2==x27, rs3==x27, rd==x27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x8; op2:x27; op3:x27; dest:x27; op1val:0x0; op2val:0xfbff; +op3val:0xfbff; valaddr_reg:x10; val_offset:18*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x27, x8, x27, x27, dyn, 32, 0, x10, 18*FLEN/8, x12, x1, x3) + +inst_7: +// rs1 == rd == rs3 != rs2, rs1==x5, rs2==x21, rs3==x5, rd==x5,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x5; op2:x21; op3:x5; dest:x5; op1val:0x0; op2val:0xfbff; +op3val:0x0; valaddr_reg:x10; val_offset:21*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x5, x5, x21, x5, dyn, 64, 0, x10, 21*FLEN/8, x12, x1, x3) + +inst_8: +// rs1 == rs2 == rs3 == rd, rs1==x2, rs2==x2, rs3==x2, rd==x2,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x2; op2:x2; op3:x2; dest:x2; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x10; val_offset:24*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x2, x2, x2, x2, dyn, 96, 0, x10, 24*FLEN/8, x12, x1, x3) + +inst_9: +// rs1 == rs2 == rd != rs3, rs1==x11, rs2==x11, rs3==x10, rd==x11,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x11; op2:x11; op3:x10; dest:x11; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x10; val_offset:27*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x11, x11, x11, x10, dyn, 128, 0, x10, 27*FLEN/8, x12, x1, x3) + +inst_10: +// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==x18, rs2==x16, rs3==x12, rd==x16, +/* opcode: fnmsub.h ; op1:x18; op2:x16; op3:x12; dest:x16; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x10; val_offset:30*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x16, x18, x16, x12, dyn, 0, 0, x10, 30*FLEN/8, x12, x1, x3) + +inst_11: +// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==x28, rs2==x6, rs3==x6, rd==x13, +/* opcode: fnmsub.h ; op1:x28; op2:x6; op3:x6; dest:x13; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x10; val_offset:33*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x13, x28, x6, x6, dyn, 0, 0, x10, 33*FLEN/8, x12, x1, x3) +RVTEST_VALBASEUPD(x4,test_dataset_1) + +inst_12: +// rs1==x26, rs2==x22, rs3==x28, rd==x7, +/* opcode: fnmsub.h ; op1:x26; op2:x22; op3:x28; dest:x7; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x4; val_offset:0*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x7, x26, x22, x28, dyn, 0, 0, x4, 0*FLEN/8, x9, x1, x3) + +inst_13: +// rs1==x20, rs2==x17, rs3==x3, rd==x26, +/* opcode: fnmsub.h ; op1:x20; op2:x17; op3:x3; dest:x26; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x4; val_offset:3*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x26, x20, x17, x3, dyn, 0, 0, x4, 3*FLEN/8, x9, x1, x3) + +inst_14: +// rs1==x24, rs2==x12, rs3==x4, rd==x29, +/* opcode: fnmsub.h ; op1:x24; op2:x12; op3:x4; dest:x29; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x4; val_offset:6*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x29, x24, x12, x4, dyn, 0, 0, x4, 6*FLEN/8, x9, x1, x5) +RVTEST_SIGBASE(x2,signature_x2_0) + +inst_15: +// rs1==x10, rs2==x25, rs3==x26, rd==x15, +/* opcode: fnmsub.h ; op1:x10; op2:x25; op3:x26; dest:x15; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x4; val_offset:9*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x15, x10, x25, x26, dyn, 0, 0, x4, 9*FLEN/8, x9, x2, x5) + +inst_16: +// rs1==x19, rs2==x8, rs3==x24, rd==x1, +/* opcode: fnmsub.h ; op1:x19; op2:x8; op3:x24; dest:x1; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x4; val_offset:12*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x1, x19, x8, x24, dyn, 0, 0, x4, 12*FLEN/8, x9, x2, x5) + +inst_17: +// rs1==x12, rs2==x14, rs3==x1, rd==x3, +/* opcode: fnmsub.h ; op1:x12; op2:x14; op3:x1; dest:x3; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x4; val_offset:15*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x3, x12, x14, x1, dyn, 0, 0, x4, 15*FLEN/8, x9, x2, x5) + +inst_18: +// rs1==x6, rs2==x18, rs3==x31, rd==x30, +/* opcode: fnmsub.h ; op1:x6; op2:x18; op3:x31; dest:x30; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x4; val_offset:18*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x30, x6, x18, x31, dyn, 0, 0, x4, 18*FLEN/8, x9, x2, x5) + +inst_19: +// rs1==x16, rs2==x30, rs3==x15, rd==x12, +/* opcode: fnmsub.h ; op1:x16; op2:x30; op3:x15; dest:x12; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x4; val_offset:21*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x12, x16, x30, x15, dyn, 0, 0, x4, 21*FLEN/8, x9, x2, x5) + +inst_20: +// rs1==x17, rs2==x28, rs3==x14, rd==x18, +/* opcode: fnmsub.h ; op1:x17; op2:x28; op3:x14; dest:x18; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x4; val_offset:24*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x18, x17, x28, x14, dyn, 0, 0, x4, 24*FLEN/8, x9, x2, x5) + +inst_21: +// rs1==x23, rs2==x1, rs3==x20, rd==x31, +/* opcode: fnmsub.h ; op1:x23; op2:x1; op3:x20; dest:x31; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x4; val_offset:27*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x23, x1, x20, dyn, 0, 0, x4, 27*FLEN/8, x9, x2, x5) +RVTEST_VALBASEUPD(x11,test_dataset_2) + +inst_22: +// rs1==x15, rs2==x10, rs3==x8, rd==x23, +/* opcode: fnmsub.h ; op1:x15; op2:x10; op3:x8; dest:x23; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x11; val_offset:0*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x23, x15, x10, x8, dyn, 0, 0, x11, 0*FLEN/8, x12, x2, x5) + +inst_23: +// rs1==x4, rs2==x15, rs3==x30, rd==x8, +/* opcode: fnmsub.h ; op1:x4; op2:x15; op3:x30; dest:x8; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x11; val_offset:3*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x8, x4, x15, x30, dyn, 0, 0, x11, 3*FLEN/8, x12, x2, x5) + +inst_24: +// rs1==x27, rs2==x20, rs3==x23, rd==x6, +/* opcode: fnmsub.h ; op1:x27; op2:x20; op3:x23; dest:x6; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x11; val_offset:6*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x6, x27, x20, x23, dyn, 0, 0, x11, 6*FLEN/8, x12, x2, x5) + +inst_25: +// rs1==x21, rs2==x19, rs3==x29, rd==x22, +/* opcode: fnmsub.h ; op1:x21; op2:x19; op3:x29; dest:x22; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x11; val_offset:9*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x22, x21, x19, x29, dyn, 0, 0, x11, 9*FLEN/8, x12, x2, x5) + +inst_26: +// rs1==x25, rs2==x7, rs3==x17, rd==x20, +/* opcode: fnmsub.h ; op1:x25; op2:x7; op3:x17; dest:x20; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x11; val_offset:12*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x20, x25, x7, x17, dyn, 0, 0, x11, 12*FLEN/8, x12, x2, x6) + +inst_27: +// rs1==x3, rs2==x26, rs3==x9, rd==x4, +/* opcode: fnmsub.h ; op1:x3; op2:x26; op3:x9; dest:x4; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x11; val_offset:15*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x4, x3, x26, x9, dyn, 0, 0, x11, 15*FLEN/8, x12, x2, x6) + +inst_28: +// rs1==x29, rs2==x3, rs3==x11, rd==x10, +/* opcode: fnmsub.h ; op1:x29; op2:x3; op3:x11; dest:x10; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x11; val_offset:18*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x10, x29, x3, x11, dyn, 0, 0, x11, 18*FLEN/8, x12, x2, x6) +RVTEST_SIGBASE(x2,signature_x2_1) + +inst_29: +// rs1==x30, rs2==x9, rs3==x13, rd==x28, +/* opcode: fnmsub.h ; op1:x30; op2:x9; op3:x13; dest:x28; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x11; val_offset:21*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x28, x30, x9, x13, dyn, 0, 0, x11, 21*FLEN/8, x12, x2, x6) + +inst_30: +// rs1==x1, rs2==x29, rs3==x19, rd==x0, +/* opcode: fnmsub.h ; op1:x1; op2:x29; op3:x19; dest:x0; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x11; val_offset:24*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x0, x1, x29, x19, dyn, 0, 0, x11, 24*FLEN/8, x12, x2, x6) + +inst_31: +// rs1==x13, rs2==x5, rs3==x18, rd==x14, +/* opcode: fnmsub.h ; op1:x13; op2:x5; op3:x18; dest:x14; op1val:0x0; op2val:0x0; +op3val:0x0; valaddr_reg:x11; val_offset:27*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x14, x13, x5, x18, dyn, 0, 0, x11, 27*FLEN/8, x12, x2, x6) +RVTEST_VALBASEUPD(x1,test_dataset_3) + +inst_32: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7bff; +op3val:0x0; valaddr_reg:x1; val_offset:0*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x1, 0*FLEN/8, x3, x2, x6) + +inst_33: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7bff; +op3val:0x0; valaddr_reg:x1; val_offset:3*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3*FLEN/8, x3, x2, x6) + +inst_34: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfbff; +op3val:0x0; valaddr_reg:x1; val_offset:6*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x1, 6*FLEN/8, x3, x2, x6) + +inst_35: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfbff; +op3val:0x0; valaddr_reg:x1; val_offset:9*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x1, 9*FLEN/8, x3, x2, x6) + +inst_36: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfbff; +op3val:0x0; valaddr_reg:x1; val_offset:12*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x1, 12*FLEN/8, x3, x2, x6) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(64511,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +test_dataset_1: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +test_dataset_2: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +test_dataset_3: +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(0,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 30*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_0: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_1: + .fill 16*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fnmsub_b7-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fnmsub_b7-01.S new file mode 100644 index 000000000..36b66087a --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fnmsub_b7-01.S @@ -0,0 +1,766 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 06:07:02 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fnmsub.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fnmsub.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fnmsub_b7 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fnmsub_b7) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x4,test_dataset_0) +RVTEST_SIGBASE(x2,signature_x2_1) + +inst_0: +// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==x0, rs2==x0, rs3==x6, rd==x12,fs1 == 0 and fe1 == 0x1c and fm1 == 0x340 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x03e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x0; op2:x0; op3:x6; dest:x12; op1val:0x0; op2val:0x0; +op3val:0x7bb1; valaddr_reg:x4; val_offset:0*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x12, x0, x0, x6, dyn, 96, 0, x4, 0*FLEN/8, x13, x2, x3) + +inst_1: +// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==x8, rs2==x22, rs3==x23, rd==x8,fs1 == 0 and fe1 == 0x1c and fm1 == 0x00a and fs2 == 1 and fe2 == 0x11 and fm2 == 0x194 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x8; op2:x22; op3:x23; dest:x8; op1val:0x700a; op2val:0xc594; +op3val:0x79a2; valaddr_reg:x4; val_offset:3*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x8, x8, x22, x23, dyn, 96, 0, x4, 3*FLEN/8, x13, x2, x3) + +inst_2: +// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==x10, rs2==x28, rs3==x12, rd==x7,fs1 == 0 and fe1 == 0x1b and fm1 == 0x173 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1cf and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3ea and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x10; op2:x28; op3:x12; dest:x7; op1val:0x6d73; op2val:0xc1cf; +op3val:0x73ea; valaddr_reg:x4; val_offset:6*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x7, x10, x28, x12, dyn, 96, 0, x4, 6*FLEN/8, x13, x2, x3) + +inst_3: +// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==x18, rs2==x6, rs3==x18, rd==x31,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3fd and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2b4 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2b2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x18; op2:x6; op3:x18; dest:x31; op1val:0x7bfd; op2val:0xb2b4; +op3val:0x7bfd; valaddr_reg:x4; val_offset:9*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x18, x6, x18, dyn, 96, 0, x4, 9*FLEN/8, x13, x2, x3) + +inst_4: +// rs1 == rs2 == rs3 != rd, rs1==x5, rs2==x5, rs3==x5, rd==x19,fs1 == 0 and fe1 == 0x1e and fm1 == 0x121 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1b8 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x357 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x5; op2:x5; op3:x5; dest:x19; op1val:0x7921; op2val:0x7921; +op3val:0x7921; valaddr_reg:x4; val_offset:12*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x19, x5, x5, x5, dyn, 96, 0, x4, 12*FLEN/8, x13, x2, x3) + +inst_5: +// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==x9, rs2==x30, rs3==x16, rd==x16,fs1 == 0 and fe1 == 0x1d and fm1 == 0x33f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x05e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3ea and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x9; op2:x30; op3:x16; dest:x16; op1val:0x773f; op2val:0xbc5e; +op3val:0x77ea; valaddr_reg:x4; val_offset:15*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x16, x9, x30, x16, dyn, 96, 0, x4, 15*FLEN/8, x13, x2, x3) + +inst_6: +// rd == rs2 == rs3 != rs1, rs1==x31, rs2==x29, rs3==x29, rd==x29,fs1 == 0 and fe1 == 0x1c and fm1 == 0x226 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x051 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x31; op2:x29; op3:x29; dest:x29; op1val:0x7226; op2val:0xc451; +op3val:0xc451; valaddr_reg:x4; val_offset:18*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x29, x31, x29, x29, dyn, 96, 0, x4, 18*FLEN/8, x13, x2, x3) + +inst_7: +// rs1 == rd == rs3 != rs2, rs1==x17, rs2==x14, rs3==x17, rd==x17,fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ba and fs2 == 1 and fe2 == 0x10 and fm2 == 0x13a and fs3 == 0 and fe3 == 0x1c and fm3 == 0x37d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x17; op2:x14; op3:x17; dest:x17; op1val:0x6dba; op2val:0xc13a; +op3val:0x6dba; valaddr_reg:x4; val_offset:21*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x17, x17, x14, x17, dyn, 96, 0, x4, 21*FLEN/8, x13, x2, x3) + +inst_8: +// rs1 == rs2 == rs3 == rd, rs1==x21, rs2==x21, rs3==x21, rd==x21,fs1 == 0 and fe1 == 0x19 and fm1 == 0x11e and fs2 == 1 and fe2 == 0x12 and fm2 == 0x2aa and fs3 == 0 and fe3 == 0x1d and fm3 == 0x044 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x21; op2:x21; op3:x21; dest:x21; op1val:0x651e; op2val:0x651e; +op3val:0x651e; valaddr_reg:x4; val_offset:24*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x21, x21, x21, x21, dyn, 96, 0, x4, 24*FLEN/8, x13, x2, x3) + +inst_9: +// rs1 == rs2 == rd != rs3, rs1==x1, rs2==x1, rs3==x31, rd==x1,fs1 == 0 and fe1 == 0x1d and fm1 == 0x285 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x06c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x336 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x1; op2:x1; op3:x31; dest:x1; op1val:0x7685; op2val:0x7685; +op3val:0x7b36; valaddr_reg:x4; val_offset:27*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x1, x1, x1, x31, dyn, 96, 0, x4, 27*FLEN/8, x13, x2, x3) + +inst_10: +// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==x24, rs2==x11, rs3==x0, rd==x11,fs1 == 0 and fe1 == 0x1d and fm1 == 0x20f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0cd and fs3 == 0 and fe3 == 0x1b and fm3 == 0x346 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x24; op2:x11; op3:x0; dest:x11; op1val:0x760f; op2val:0xb4cd; +op3val:0x0; valaddr_reg:x4; val_offset:30*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x11, x24, x11, x0, dyn, 96, 0, x4, 30*FLEN/8, x13, x2, x3) + +inst_11: +// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==x26, rs2==x7, rs3==x7, rd==x10,fs1 == 0 and fe1 == 0x1d and fm1 == 0x021 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3ad and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ed and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x26; op2:x7; op3:x7; dest:x10; op1val:0x7421; op2val:0xc3ad; +op3val:0xc3ad; valaddr_reg:x4; val_offset:33*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x10, x26, x7, x7, dyn, 96, 0, x4, 33*FLEN/8, x13, x2, x3) +RVTEST_VALBASEUPD(x7,test_dataset_1) + +inst_12: +// rs1==x22, rs2==x20, rs3==x10, rd==x28,fs1 == 0 and fe1 == 0x1b and fm1 == 0x009 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0e9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0f5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x22; op2:x20; op3:x10; dest:x28; op1val:0x6c09; op2val:0xc8e9; +op3val:0x78f5; valaddr_reg:x7; val_offset:0*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x28, x22, x20, x10, dyn, 96, 0, x7, 0*FLEN/8, x8, x2, x3) + +inst_13: +// rs1==x13, rs2==x10, rs3==x8, rd==x9,fs1 == 0 and fe1 == 0x1d and fm1 == 0x208 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x301 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x148 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x13; op2:x10; op3:x8; dest:x9; op1val:0x7608; op2val:0xbf01; +op3val:0x7948; valaddr_reg:x7; val_offset:3*FLEN/8; rmval:dyn; +testreg:x3; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x9, x13, x10, x8, dyn, 96, 0, x7, 3*FLEN/8, x8, x2, x3) + +inst_14: +// rs1==x23, rs2==x3, rs3==x14, rd==x20,fs1 == 0 and fe1 == 0x1d and fm1 == 0x169 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x015 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x187 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x23; op2:x3; op3:x14; dest:x20; op1val:0x7569; op2val:0xc015; +op3val:0x7987; valaddr_reg:x7; val_offset:6*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x20, x23, x3, x14, dyn, 96, 0, x7, 6*FLEN/8, x8, x2, x5) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_15: +// rs1==x29, rs2==x18, rs3==x1, rd==x3,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3f5 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x139 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x131 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x29; op2:x18; op3:x1; dest:x3; op1val:0x77f5; op2val:0xbd39; +op3val:0x7931; valaddr_reg:x7; val_offset:9*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x3, x29, x18, x1, dyn, 96, 0, x7, 9*FLEN/8, x8, x1, x5) + +inst_16: +// rs1==x12, rs2==x31, rs3==x28, rd==x13,fs1 == 0 and fe1 == 0x1e and fm1 == 0x335 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x129 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x12; op2:x31; op3:x28; dest:x13; op1val:0x7b35; op2val:0xb929; +op3val:0x78a6; valaddr_reg:x7; val_offset:12*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x13, x12, x31, x28, dyn, 96, 0, x7, 12*FLEN/8, x8, x1, x5) + +inst_17: +// rs1==x16, rs2==x26, rs3==x20, rd==x15,fs1 == 0 and fe1 == 0x1c and fm1 == 0x08b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x33f and fs3 == 0 and fe3 == 0x1b and fm3 == 0x01e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x16; op2:x26; op3:x20; dest:x15; op1val:0x708b; op2val:0xb73f; +op3val:0x6c1e; valaddr_reg:x7; val_offset:15*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x15, x16, x26, x20, dyn, 96, 0, x7, 15*FLEN/8, x8, x1, x5) + +inst_18: +// rs1==x15, rs2==x25, rs3==x11, rd==x2,fs1 == 0 and fe1 == 0x1e and fm1 == 0x390 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x021 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3d0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x15; op2:x25; op3:x11; dest:x2; op1val:0x7b90; op2val:0xb821; +op3val:0x77d0; valaddr_reg:x7; val_offset:18*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x2, x15, x25, x11, dyn, 96, 0, x7, 18*FLEN/8, x8, x1, x5) + +inst_19: +// rs1==x6, rs2==x27, rs3==x9, rd==x14,fs1 == 0 and fe1 == 0x1c and fm1 == 0x233 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x390 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x6; op2:x27; op3:x9; dest:x14; op1val:0x7233; op2val:0xc4e1; +op3val:0x7b90; valaddr_reg:x7; val_offset:21*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x14, x6, x27, x9, dyn, 96, 0, x7, 21*FLEN/8, x8, x1, x5) + +inst_20: +// rs1==x25, rs2==x17, rs3==x19, rd==x18,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a1 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x109 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1d4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x25; op2:x17; op3:x19; dest:x18; op1val:0x78a1; op2val:0xbd09; +op3val:0x79d4; valaddr_reg:x7; val_offset:24*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x18, x25, x17, x19, dyn, 96, 0, x7, 24*FLEN/8, x8, x1, x5) + +inst_21: +// rs1==x4, rs2==x16, rs3==x27, rd==x6,fs1 == 0 and fe1 == 0x1e and fm1 == 0x30b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x130 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x091 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x4; op2:x16; op3:x27; dest:x6; op1val:0x7b0b; op2val:0xb530; +op3val:0x7491; valaddr_reg:x7; val_offset:27*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x6, x4, x16, x27, dyn, 96, 0, x7, 27*FLEN/8, x8, x1, x5) +RVTEST_VALBASEUPD(x6,test_dataset_2) + +inst_22: +// rs1==x20, rs2==x15, rs3==x2, rd==x22,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1b4 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ec and fs3 == 0 and fe3 == 0x1e and fm3 == 0x305 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x20; op2:x15; op3:x2; dest:x22; op1val:0x75b4; op2val:0xc0ec; +op3val:0x7b05; valaddr_reg:x6; val_offset:0*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x22, x20, x15, x2, dyn, 96, 0, x6, 0*FLEN/8, x10, x1, x5) + +inst_23: +// rs1==x19, rs2==x4, rs3==x13, rd==x26,fs1 == 0 and fe1 == 0x1c and fm1 == 0x051 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1a9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x21c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x19; op2:x4; op3:x13; dest:x26; op1val:0x7051; op2val:0xc5a9; +op3val:0x7a1c; valaddr_reg:x6; val_offset:3*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x26, x19, x4, x13, dyn, 96, 0, x6, 3*FLEN/8, x10, x1, x5) + +inst_24: +// rs1==x2, rs2==x13, rs3==x22, rd==x23,fs1 == 0 and fe1 == 0x1b and fm1 == 0x23e and fs2 == 1 and fe2 == 0x11 and fm2 == 0x311 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x184 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x2; op2:x13; op3:x22; dest:x23; op1val:0x6e3e; op2val:0xc711; +op3val:0x7984; valaddr_reg:x6; val_offset:6*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x23, x2, x13, x22, dyn, 96, 0, x6, 6*FLEN/8, x10, x1, x5) + +inst_25: +// rs1==x30, rs2==x19, rs3==x25, rd==x4,fs1 == 0 and fe1 == 0x1e and fm1 == 0x19d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x169 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x398 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x19; op3:x25; dest:x4; op1val:0x799d; op2val:0xbd69; +op3val:0x7b98; valaddr_reg:x6; val_offset:9*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x4, x30, x19, x25, dyn, 96, 0, x6, 9*FLEN/8, x10, x1, x5) + +inst_26: +// rs1==x11, rs2==x23, rs3==x3, rd==x0,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2be and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0c6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x006 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x11; op2:x23; op3:x3; dest:x0; op1val:0x7abe; op2val:0xb8c6; +op3val:0x7806; valaddr_reg:x6; val_offset:12*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x0, x11, x23, x3, dyn, 96, 0, x6, 12*FLEN/8, x10, x1, x5) + +inst_27: +// rs1==x28, rs2==x24, rs3==x26, rd==x27,fs1 == 0 and fe1 == 0x1c and fm1 == 0x252 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x213 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0cd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x28; op2:x24; op3:x26; dest:x27; op1val:0x7252; op2val:0xba13; +op3val:0x70cd; valaddr_reg:x6; val_offset:15*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x27, x28, x24, x26, dyn, 96, 0, x6, 15*FLEN/8, x10, x1, x5) + +inst_28: +// rs1==x27, rs2==x8, rs3==x24, rd==x30,fs1 == 0 and fe1 == 0x1e and fm1 == 0x03a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x013 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x27; op2:x8; op3:x24; dest:x30; op1val:0x783a; op2val:0xbbb6; +op3val:0x7813; valaddr_reg:x6; val_offset:18*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x30, x27, x8, x24, dyn, 96, 0, x6, 18*FLEN/8, x10, x1, x4) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_29: +// rs1==x14, rs2==x2, rs3==x30, rd==x24,fs1 == 0 and fe1 == 0x1b and fm1 == 0x091 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x252 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x338 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x14; op2:x2; op3:x30; dest:x24; op1val:0x6c91; op2val:0xca52; +op3val:0x7b38; valaddr_reg:x6; val_offset:21*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x24, x14, x2, x30, dyn, 96, 0, x6, 21*FLEN/8, x10, x1, x4) + +inst_30: +// rs1==x7, rs2==x12, rs3==x4, rd==x25,fs1 == 0 and fe1 == 0x1e and fm1 == 0x00e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x187 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x19b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x7; op2:x12; op3:x4; dest:x25; op1val:0x780e; op2val:0xbd87; +op3val:0x799b; valaddr_reg:x6; val_offset:24*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x25, x7, x12, x4, dyn, 96, 0, x6, 24*FLEN/8, x10, x1, x4) + +inst_31: +// rs1==x3, rs2==x9, rs3==x15, rd==x5,fs1 == 0 and fe1 == 0x1c and fm1 == 0x309 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x06f and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3cd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x3; op2:x9; op3:x15; dest:x5; op1val:0x7309; op2val:0xbc6f; +op3val:0x73cd; valaddr_reg:x6; val_offset:27*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x5, x3, x9, x15, dyn, 96, 0, x6, 27*FLEN/8, x10, x1, x4) + +inst_32: +// fs1 == 0 and fe1 == 0x18 and fm1 == 0x21b and fs2 == 1 and fe2 == 0x13 and fm2 == 0x331 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x17d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x621b; op2val:0xcf31; +op3val:0x757d; valaddr_reg:x6; val_offset:30*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x6, 30*FLEN/8, x10, x1, x4) +RVTEST_VALBASEUPD(x2,test_dataset_3) + +inst_33: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x044 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x258 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2c5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7444; op2val:0xbe58; +op3val:0x76c5; valaddr_reg:x2; val_offset:0*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 0*FLEN/8, x3, x1, x4) + +inst_34: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x207 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x06d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ab and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7607; op2val:0xc06d; +op3val:0x7aab; valaddr_reg:x2; val_offset:3*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 3*FLEN/8, x3, x1, x4) + +inst_35: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x320 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x24a and fs3 == 0 and fe3 == 0x1c and fm3 == 0x19b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b20; op2val:0xb24a; +op3val:0x719b; valaddr_reg:x2; val_offset:6*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 6*FLEN/8, x3, x1, x4) + +inst_36: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x256 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2b5 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x150 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7656; op2val:0xb6b5; +op3val:0x7150; valaddr_reg:x2; val_offset:9*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 9*FLEN/8, x3, x1, x4) + +inst_37: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x14d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1e1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3cb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x794d; op2val:0xbde1; +op3val:0x7bcb; valaddr_reg:x2; val_offset:12*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 12*FLEN/8, x3, x1, x4) + +inst_38: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x274 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x398 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x220 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7274; op2val:0xc398; +op3val:0x7a20; valaddr_reg:x2; val_offset:15*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 15*FLEN/8, x3, x1, x4) + +inst_39: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0cc and fs2 == 1 and fe2 == 0x0a and fm2 == 0x1a5 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x2c5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74cc; op2val:0xa9a5; +op3val:0x62c5; valaddr_reg:x2; val_offset:18*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 18*FLEN/8, x3, x1, x4) + +inst_40: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x21c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x327 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x177 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a1c; op2val:0xb727; +op3val:0x7577; valaddr_reg:x2; val_offset:21*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 21*FLEN/8, x3, x1, x4) + +inst_41: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x171 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x11e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2f7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7171; op2val:0xc11e; +op3val:0x76f7; valaddr_reg:x2; val_offset:24*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 24*FLEN/8, x3, x1, x4) + +inst_42: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x369 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x318 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x28e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7369; op2val:0xbf18; +op3val:0x768e; valaddr_reg:x2; val_offset:27*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 27*FLEN/8, x3, x1, x4) + +inst_43: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x322 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x383 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2af and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7722; op2val:0xbb83; +op3val:0x76af; valaddr_reg:x2; val_offset:30*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 30*FLEN/8, x3, x1, x4) + +inst_44: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b4 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3e0 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x09e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78b4; op2val:0xb7e0; +op3val:0x749e; valaddr_reg:x2; val_offset:33*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 33*FLEN/8, x3, x1, x4) + +inst_45: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x215 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x340 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x174 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e15; op2val:0xbb40; +op3val:0x6d74; valaddr_reg:x2; val_offset:36*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 36*FLEN/8, x3, x1, x4) + +inst_46: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2d0 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0e6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x02a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ed0; op2val:0xc4e6; +op3val:0x782a; valaddr_reg:x2; val_offset:39*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 39*FLEN/8, x3, x1, x4) + +inst_47: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c2 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x07d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x275 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c2; op2val:0xc07d; +op3val:0x7a75; valaddr_reg:x2; val_offset:42*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 42*FLEN/8, x3, x1, x4) + +inst_48: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x009 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x19e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7809; op2val:0xbd9e; +op3val:0x79a9; valaddr_reg:x2; val_offset:45*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 45*FLEN/8, x3, x1, x4) + +inst_49: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d6 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x01c and fs3 == 0 and fe3 == 0x1b and fm3 == 0x007 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd6; op2val:0xac1c; +op3val:0x6c07; valaddr_reg:x2; val_offset:48*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 48*FLEN/8, x3, x1, x4) + +inst_50: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x056 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x023 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x07d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6456; op2val:0xc823; +op3val:0x707d; valaddr_reg:x2; val_offset:51*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 51*FLEN/8, x3, x1, x4) + +inst_51: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x22d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1f0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x096 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x762d; op2val:0xbdf0; +op3val:0x7896; valaddr_reg:x2; val_offset:54*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 54*FLEN/8, x3, x1, x4) + +inst_52: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f2 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x38f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x19e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f2; op2val:0xb78f; +op3val:0x759e; valaddr_reg:x2; val_offset:57*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 57*FLEN/8, x3, x1, x4) + +inst_53: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b7 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x246 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x20c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bb7; op2val:0x9a46; +op3val:0x5a0c; valaddr_reg:x2; val_offset:60*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 60*FLEN/8, x3, x1, x4) + +inst_54: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 1 and fe2 == 0x0d and fm2 == 0x005 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2b8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aae; op2val:0xb405; +op3val:0x72b8; valaddr_reg:x2; val_offset:63*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 63*FLEN/8, x3, x1, x4) + +inst_55: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ff and fs2 == 1 and fe2 == 0x0a and fm2 == 0x0d8 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x03d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aff; op2val:0xa8d8; +op3val:0x683d; valaddr_reg:x2; val_offset:66*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 66*FLEN/8, x3, x1, x4) + +inst_56: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x340 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x03e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7340; op2val:0xc43e; +op3val:0x7bb1; valaddr_reg:x2; val_offset:69*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 69*FLEN/8, x3, x1, x4) + +inst_57: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3fd and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2b4 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2b2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bfd; op2val:0xb2b4; +op3val:0x72b2; valaddr_reg:x2; val_offset:72*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 72*FLEN/8, x3, x1, x4) + +inst_58: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x121 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1b8 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x357 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7921; op2val:0xb9b8; +op3val:0x7757; valaddr_reg:x2; val_offset:75*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 75*FLEN/8, x3, x1, x4) + +inst_59: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x226 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x051 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7226; op2val:0xc451; +op3val:0x7aa4; valaddr_reg:x2; val_offset:78*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 78*FLEN/8, x3, x1, x4) + +inst_60: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ba and fs2 == 1 and fe2 == 0x10 and fm2 == 0x13a and fs3 == 0 and fe3 == 0x1c and fm3 == 0x37d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dba; op2val:0xc13a; +op3val:0x737d; valaddr_reg:x2; val_offset:81*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 81*FLEN/8, x3, x1, x4) + +inst_61: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x11e and fs2 == 1 and fe2 == 0x12 and fm2 == 0x2aa and fs3 == 0 and fe3 == 0x1d and fm3 == 0x044 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x651e; op2val:0xcaaa; +op3val:0x7444; valaddr_reg:x2; val_offset:84*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 84*FLEN/8, x3, x1, x4) + +inst_62: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x285 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x06c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x336 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7685; op2val:0xc06c; +op3val:0x7b36; valaddr_reg:x2; val_offset:87*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 87*FLEN/8, x3, x1, x4) + +inst_63: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x20f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0cd and fs3 == 0 and fe3 == 0x1b and fm3 == 0x346 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x760f; op2val:0xb4cd; +op3val:0x6f46; valaddr_reg:x2; val_offset:90*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 90*FLEN/8, x3, x1, x4) + +inst_64: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x021 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3ad and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ed and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7421; op2val:0xc3ad; +op3val:0x7bed; valaddr_reg:x2; val_offset:93*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 93*FLEN/8, x3, x1, x4) + +inst_65: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2be and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0c6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x006 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7abe; op2val:0xb8c6; +op3val:0x7806; valaddr_reg:x2; val_offset:96*FLEN/8; rmval:dyn; +testreg:x4; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x2, 96*FLEN/8, x3, x1, x4) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31665,32,FLEN) +NAN_BOXED(28682,32,FLEN) +NAN_BOXED(50580,16,FLEN) +NAN_BOXED(31138,32,FLEN) +NAN_BOXED(28019,32,FLEN) +NAN_BOXED(49615,16,FLEN) +NAN_BOXED(29674,32,FLEN) +NAN_BOXED(31741,32,FLEN) +NAN_BOXED(45748,16,FLEN) +NAN_BOXED(31741,32,FLEN) +NAN_BOXED(31009,32,FLEN) +NAN_BOXED(31009,16,FLEN) +NAN_BOXED(31009,32,FLEN) +NAN_BOXED(30527,32,FLEN) +NAN_BOXED(48222,16,FLEN) +NAN_BOXED(30698,32,FLEN) +NAN_BOXED(29222,32,FLEN) +NAN_BOXED(50257,16,FLEN) +NAN_BOXED(50257,32,FLEN) +NAN_BOXED(28090,32,FLEN) +NAN_BOXED(49466,16,FLEN) +NAN_BOXED(28090,32,FLEN) +NAN_BOXED(25886,32,FLEN) +NAN_BOXED(25886,16,FLEN) +NAN_BOXED(25886,32,FLEN) +NAN_BOXED(30341,32,FLEN) +NAN_BOXED(30341,16,FLEN) +NAN_BOXED(31542,32,FLEN) +NAN_BOXED(30223,32,FLEN) +NAN_BOXED(46285,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(29729,32,FLEN) +NAN_BOXED(50093,16,FLEN) +NAN_BOXED(50093,32,FLEN) +test_dataset_1: +NAN_BOXED(27657,32,FLEN) +NAN_BOXED(51433,16,FLEN) +NAN_BOXED(30965,32,FLEN) +NAN_BOXED(30216,32,FLEN) +NAN_BOXED(48897,16,FLEN) +NAN_BOXED(31048,32,FLEN) +NAN_BOXED(30057,32,FLEN) +NAN_BOXED(49173,16,FLEN) +NAN_BOXED(31111,32,FLEN) +NAN_BOXED(30709,32,FLEN) +NAN_BOXED(48441,16,FLEN) +NAN_BOXED(31025,32,FLEN) +NAN_BOXED(31541,32,FLEN) +NAN_BOXED(47401,16,FLEN) +NAN_BOXED(30886,32,FLEN) +NAN_BOXED(28811,32,FLEN) +NAN_BOXED(46911,16,FLEN) +NAN_BOXED(27678,32,FLEN) +NAN_BOXED(31632,32,FLEN) +NAN_BOXED(47137,16,FLEN) +NAN_BOXED(30672,32,FLEN) +NAN_BOXED(29235,32,FLEN) +NAN_BOXED(50401,16,FLEN) +NAN_BOXED(31632,32,FLEN) +NAN_BOXED(30881,32,FLEN) +NAN_BOXED(48393,16,FLEN) +NAN_BOXED(31188,32,FLEN) +NAN_BOXED(31499,32,FLEN) +NAN_BOXED(46384,16,FLEN) +NAN_BOXED(29841,32,FLEN) +test_dataset_2: +NAN_BOXED(30132,32,FLEN) +NAN_BOXED(49388,16,FLEN) +NAN_BOXED(31493,32,FLEN) +NAN_BOXED(28753,32,FLEN) +NAN_BOXED(50601,16,FLEN) +NAN_BOXED(31260,32,FLEN) +NAN_BOXED(28222,32,FLEN) +NAN_BOXED(50961,16,FLEN) +NAN_BOXED(31108,32,FLEN) +NAN_BOXED(31133,32,FLEN) +NAN_BOXED(48489,16,FLEN) +NAN_BOXED(31640,32,FLEN) +NAN_BOXED(31422,32,FLEN) +NAN_BOXED(47302,16,FLEN) +NAN_BOXED(30726,32,FLEN) +NAN_BOXED(29266,32,FLEN) +NAN_BOXED(47635,16,FLEN) +NAN_BOXED(28877,32,FLEN) +NAN_BOXED(30778,32,FLEN) +NAN_BOXED(48054,16,FLEN) +NAN_BOXED(30739,32,FLEN) +NAN_BOXED(27793,32,FLEN) +NAN_BOXED(51794,16,FLEN) +NAN_BOXED(31544,32,FLEN) +NAN_BOXED(30734,32,FLEN) +NAN_BOXED(48519,16,FLEN) +NAN_BOXED(31131,32,FLEN) +NAN_BOXED(29449,32,FLEN) +NAN_BOXED(48239,16,FLEN) +NAN_BOXED(29645,32,FLEN) +NAN_BOXED(25115,32,FLEN) +NAN_BOXED(53041,16,FLEN) +NAN_BOXED(30077,32,FLEN) +test_dataset_3: +NAN_BOXED(29764,16,FLEN) +NAN_BOXED(48728,16,FLEN) +NAN_BOXED(30405,16,FLEN) +NAN_BOXED(30215,16,FLEN) +NAN_BOXED(49261,16,FLEN) +NAN_BOXED(31403,16,FLEN) +NAN_BOXED(31520,16,FLEN) +NAN_BOXED(45642,16,FLEN) +NAN_BOXED(29083,16,FLEN) +NAN_BOXED(30294,16,FLEN) +NAN_BOXED(46773,16,FLEN) +NAN_BOXED(29008,16,FLEN) +NAN_BOXED(31053,16,FLEN) +NAN_BOXED(48609,16,FLEN) +NAN_BOXED(31691,16,FLEN) +NAN_BOXED(29300,16,FLEN) +NAN_BOXED(50072,16,FLEN) +NAN_BOXED(31264,16,FLEN) +NAN_BOXED(29900,16,FLEN) +NAN_BOXED(43429,16,FLEN) +NAN_BOXED(25285,16,FLEN) +NAN_BOXED(31260,16,FLEN) +NAN_BOXED(46887,16,FLEN) +NAN_BOXED(30071,16,FLEN) +NAN_BOXED(29041,16,FLEN) +NAN_BOXED(49438,16,FLEN) +NAN_BOXED(30455,16,FLEN) +NAN_BOXED(29545,16,FLEN) +NAN_BOXED(48920,16,FLEN) +NAN_BOXED(30350,16,FLEN) +NAN_BOXED(30498,16,FLEN) +NAN_BOXED(48003,16,FLEN) +NAN_BOXED(30383,16,FLEN) +NAN_BOXED(30900,16,FLEN) +NAN_BOXED(47072,16,FLEN) +NAN_BOXED(29854,16,FLEN) +NAN_BOXED(28181,16,FLEN) +NAN_BOXED(47936,16,FLEN) +NAN_BOXED(28020,16,FLEN) +NAN_BOXED(28368,16,FLEN) +NAN_BOXED(50406,16,FLEN) +NAN_BOXED(30762,16,FLEN) +NAN_BOXED(30146,16,FLEN) +NAN_BOXED(49277,16,FLEN) +NAN_BOXED(31349,16,FLEN) +NAN_BOXED(30729,16,FLEN) +NAN_BOXED(48542,16,FLEN) +NAN_BOXED(31145,16,FLEN) +NAN_BOXED(31702,16,FLEN) +NAN_BOXED(44060,16,FLEN) +NAN_BOXED(27655,16,FLEN) +NAN_BOXED(25686,16,FLEN) +NAN_BOXED(51235,16,FLEN) +NAN_BOXED(28797,16,FLEN) +NAN_BOXED(30253,16,FLEN) +NAN_BOXED(48624,16,FLEN) +NAN_BOXED(30870,16,FLEN) +NAN_BOXED(31218,16,FLEN) +NAN_BOXED(46991,16,FLEN) +NAN_BOXED(30110,16,FLEN) +NAN_BOXED(31671,16,FLEN) +NAN_BOXED(39494,16,FLEN) +NAN_BOXED(23052,16,FLEN) +NAN_BOXED(31406,16,FLEN) +NAN_BOXED(46085,16,FLEN) +NAN_BOXED(29368,16,FLEN) +NAN_BOXED(31487,16,FLEN) +NAN_BOXED(43224,16,FLEN) +NAN_BOXED(26685,16,FLEN) +NAN_BOXED(29504,16,FLEN) +NAN_BOXED(50238,16,FLEN) +NAN_BOXED(31665,16,FLEN) +NAN_BOXED(31741,16,FLEN) +NAN_BOXED(45748,16,FLEN) +NAN_BOXED(29362,16,FLEN) +NAN_BOXED(31009,16,FLEN) +NAN_BOXED(47544,16,FLEN) +NAN_BOXED(30551,16,FLEN) +NAN_BOXED(29222,16,FLEN) +NAN_BOXED(50257,16,FLEN) +NAN_BOXED(31396,16,FLEN) +NAN_BOXED(28090,16,FLEN) +NAN_BOXED(49466,16,FLEN) +NAN_BOXED(29565,16,FLEN) +NAN_BOXED(25886,16,FLEN) +NAN_BOXED(51882,16,FLEN) +NAN_BOXED(29764,16,FLEN) +NAN_BOXED(30341,16,FLEN) +NAN_BOXED(49260,16,FLEN) +NAN_BOXED(31542,16,FLEN) +NAN_BOXED(30223,16,FLEN) +NAN_BOXED(46285,16,FLEN) +NAN_BOXED(28486,16,FLEN) +NAN_BOXED(29729,16,FLEN) +NAN_BOXED(50093,16,FLEN) +NAN_BOXED(31725,16,FLEN) +NAN_BOXED(31422,16,FLEN) +NAN_BOXED(47302,16,FLEN) +NAN_BOXED(30726,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x2_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_1: + .fill 30*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_0: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 74*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fnmsub_b8-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fnmsub_b8-01.S new file mode 100644 index 000000000..db76c5ae0 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fnmsub_b8-01.S @@ -0,0 +1,17079 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 06:07:02 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fnmsub.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fnmsub.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fnmsub_b8 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fnmsub_b8) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x7,test_dataset_0) +RVTEST_SIGBASE(x4,signature_x4_1) + +inst_0: +// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==x8, rs2==x8, rs3==x13, rd==x22,fs1 == 0 and fe1 == 0x0e and fm1 == 0x22f and fs2 == 1 and fe2 == 0x0a and fm2 == 0x23d and fs3 == 0 and fe3 == 0x0a and fm3 == 0x0d3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x8; op2:x8; op3:x13; dest:x22; op1val:0x3a2f; op2val:0x3a2f; +op3val:0x28d3; valaddr_reg:x7; val_offset:0*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x22, x8, x8, x13, dyn, 0, 0, x7, 0*FLEN/8, x9, x4, x2) + +inst_1: +// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==x0, rs2==x10, rs3==x23, rd==x0,fs1 == 0 and fe1 == 0x0e and fm1 == 0x22f and fs2 == 1 and fe2 == 0x0a and fm2 == 0x23d and fs3 == 0 and fe3 == 0x0a and fm3 == 0x0d3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x0; op2:x10; op3:x23; dest:x0; op1val:0x0; op2val:0xaa3d; +op3val:0x28d3; valaddr_reg:x7; val_offset:3*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x0, x0, x10, x23, dyn, 32, 0, x7, 3*FLEN/8, x9, x4, x2) + +inst_2: +// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==x23, rs2==x25, rs3==x27, rd==x28,fs1 == 0 and fe1 == 0x0e and fm1 == 0x22f and fs2 == 1 and fe2 == 0x0a and fm2 == 0x23d and fs3 == 0 and fe3 == 0x0a and fm3 == 0x0d3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x23; op2:x25; op3:x27; dest:x28; op1val:0x3a2f; op2val:0xaa3d; +op3val:0x28d3; valaddr_reg:x7; val_offset:6*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x28, x23, x25, x27, dyn, 64, 0, x7, 6*FLEN/8, x9, x4, x2) + +inst_3: +// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==x24, rs2==x12, rs3==x24, rd==x27,fs1 == 0 and fe1 == 0x0e and fm1 == 0x22f and fs2 == 1 and fe2 == 0x0a and fm2 == 0x23d and fs3 == 0 and fe3 == 0x0a and fm3 == 0x0d3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x24; op2:x12; op3:x24; dest:x27; op1val:0x3a2f; op2val:0xaa3d; +op3val:0x3a2f; valaddr_reg:x7; val_offset:9*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x27, x24, x12, x24, dyn, 96, 0, x7, 9*FLEN/8, x9, x4, x2) + +inst_4: +// rs1 == rs2 == rs3 != rd, rs1==x1, rs2==x1, rs3==x1, rd==x10,fs1 == 0 and fe1 == 0x0e and fm1 == 0x22f and fs2 == 1 and fe2 == 0x0a and fm2 == 0x23d and fs3 == 0 and fe3 == 0x0a and fm3 == 0x0d3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x1; op2:x1; op3:x1; dest:x10; op1val:0x3a2f; op2val:0x3a2f; +op3val:0x3a2f; valaddr_reg:x7; val_offset:12*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x10, x1, x1, x1, dyn, 128, 0, x7, 12*FLEN/8, x9, x4, x2) + +inst_5: +// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==x22, rs2==x0, rs3==x18, rd==x18,fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fd and fs2 == 1 and fe2 == 0x0d and fm2 == 0x167 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0b9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x22; op2:x0; op3:x18; dest:x18; op1val:0x3afd; op2val:0x0; +op3val:0x34b9; valaddr_reg:x7; val_offset:15*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x18, x22, x0, x18, dyn, 0, 0, x7, 15*FLEN/8, x9, x4, x2) + +inst_6: +// rd == rs2 == rs3 != rs1, rs1==x3, rs2==x17, rs3==x17, rd==x17,fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fd and fs2 == 1 and fe2 == 0x0d and fm2 == 0x167 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0b9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x3; op2:x17; op3:x17; dest:x17; op1val:0x3afd; op2val:0xb567; +op3val:0xb567; valaddr_reg:x7; val_offset:18*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x17, x3, x17, x17, dyn, 32, 0, x7, 18*FLEN/8, x9, x4, x2) + +inst_7: +// rs1 == rd == rs3 != rs2, rs1==x14, rs2==x31, rs3==x14, rd==x14,fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fd and fs2 == 1 and fe2 == 0x0d and fm2 == 0x167 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0b9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x14; op2:x31; op3:x14; dest:x14; op1val:0x3afd; op2val:0xb567; +op3val:0x3afd; valaddr_reg:x7; val_offset:21*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x14, x14, x31, x14, dyn, 64, 0, x7, 21*FLEN/8, x9, x4, x2) + +inst_8: +// rs1 == rs2 == rs3 == rd, rs1==x6, rs2==x6, rs3==x6, rd==x6,fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fd and fs2 == 1 and fe2 == 0x0d and fm2 == 0x167 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0b9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x6; op2:x6; op3:x6; dest:x6; op1val:0x3afd; op2val:0x3afd; +op3val:0x3afd; valaddr_reg:x7; val_offset:24*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x6, x6, x6, x6, dyn, 96, 0, x7, 24*FLEN/8, x9, x4, x2) + +inst_9: +// rs1 == rs2 == rd != rs3, rs1==x26, rs2==x26, rs3==x25, rd==x26,fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fd and fs2 == 1 and fe2 == 0x0d and fm2 == 0x167 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0b9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x26; op2:x26; op3:x25; dest:x26; op1val:0x3afd; op2val:0x3afd; +op3val:0x34b9; valaddr_reg:x7; val_offset:27*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x26, x26, x26, x25, dyn, 128, 0, x7, 27*FLEN/8, x9, x4, x2) + +inst_10: +// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==x29, rs2==x19, rs3==x0, rd==x19,fs1 == 0 and fe1 == 0x0e and fm1 == 0x351 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x294 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x205 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x29; op2:x19; op3:x0; dest:x19; op1val:0x3b51; op2val:0xba94; +op3val:0x0; valaddr_reg:x7; val_offset:30*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x19, x29, x19, x0, dyn, 0, 0, x7, 30*FLEN/8, x9, x4, x2) + +inst_11: +// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==x5, rs2==x30, rs3==x30, rd==x21,fs1 == 0 and fe1 == 0x0e and fm1 == 0x351 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x294 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x205 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x5; op2:x30; op3:x30; dest:x21; op1val:0x3b51; op2val:0xba94; +op3val:0xba94; valaddr_reg:x7; val_offset:33*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x21, x5, x30, x30, dyn, 32, 0, x7, 33*FLEN/8, x9, x4, x2) +RVTEST_VALBASEUPD(x13,test_dataset_1) + +inst_12: +// rs1==x9, rs2==x5, rs3==x26, rd==x11,fs1 == 0 and fe1 == 0x0e and fm1 == 0x351 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x294 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x205 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x9; op2:x5; op3:x26; dest:x11; op1val:0x3b51; op2val:0xba94; +op3val:0x3a05; valaddr_reg:x13; val_offset:0*FLEN/8; rmval:dyn; +testreg:x2; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x11, x9, x5, x26, dyn, 64, 0, x13, 0*FLEN/8, x15, x4, x2) + +inst_13: +// rs1==x2, rs2==x24, rs3==x21, rd==x25,fs1 == 0 and fe1 == 0x0e and fm1 == 0x351 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x294 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x205 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x2; op2:x24; op3:x21; dest:x25; op1val:0x3b51; op2val:0xba94; +op3val:0x3a05; valaddr_reg:x13; val_offset:3*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x25, x2, x24, x21, dyn, 96, 0, x13, 3*FLEN/8, x15, x4, x6) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_14: +// rs1==x19, rs2==x29, rs3==x4, rd==x24,fs1 == 0 and fe1 == 0x0e and fm1 == 0x351 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x294 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x205 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x19; op2:x29; op3:x4; dest:x24; op1val:0x3b51; op2val:0xba94; +op3val:0x3a05; valaddr_reg:x13; val_offset:6*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x24, x19, x29, x4, dyn, 128, 0, x13, 6*FLEN/8, x15, x1, x6) + +inst_15: +// rs1==x17, rs2==x4, rs3==x9, rd==x2,fs1 == 0 and fe1 == 0x04 and fm1 == 0x323 and fs2 == 1 and fe2 == 0x18 and fm2 == 0x316 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x253 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x17; op2:x4; op3:x9; dest:x2; op1val:0x1323; op2val:0xe316; +op3val:0x3a53; valaddr_reg:x13; val_offset:9*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x2, x17, x4, x9, dyn, 0, 0, x13, 9*FLEN/8, x15, x1, x6) + +inst_16: +// rs1==x10, rs2==x18, rs3==x2, rd==x5,fs1 == 0 and fe1 == 0x04 and fm1 == 0x323 and fs2 == 1 and fe2 == 0x18 and fm2 == 0x316 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x253 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x10; op2:x18; op3:x2; dest:x5; op1val:0x1323; op2val:0xe316; +op3val:0x3a53; valaddr_reg:x13; val_offset:12*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x5, x10, x18, x2, dyn, 32, 0, x13, 12*FLEN/8, x15, x1, x6) + +inst_17: +// rs1==x31, rs2==x14, rs3==x15, rd==x8,fs1 == 0 and fe1 == 0x04 and fm1 == 0x323 and fs2 == 1 and fe2 == 0x18 and fm2 == 0x316 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x253 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x31; op2:x14; op3:x15; dest:x8; op1val:0x1323; op2val:0xe316; +op3val:0x3a53; valaddr_reg:x13; val_offset:15*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x8, x31, x14, x15, dyn, 64, 0, x13, 15*FLEN/8, x15, x1, x6) + +inst_18: +// rs1==x7, rs2==x20, rs3==x22, rd==x3,fs1 == 0 and fe1 == 0x04 and fm1 == 0x323 and fs2 == 1 and fe2 == 0x18 and fm2 == 0x316 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x253 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x7; op2:x20; op3:x22; dest:x3; op1val:0x1323; op2val:0xe316; +op3val:0x3a53; valaddr_reg:x13; val_offset:18*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x3, x7, x20, x22, dyn, 96, 0, x13, 18*FLEN/8, x15, x1, x6) + +inst_19: +// rs1==x27, rs2==x23, rs3==x28, rd==x20,fs1 == 0 and fe1 == 0x04 and fm1 == 0x323 and fs2 == 1 and fe2 == 0x18 and fm2 == 0x316 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x253 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x27; op2:x23; op3:x28; dest:x20; op1val:0x1323; op2val:0xe316; +op3val:0x3a53; valaddr_reg:x13; val_offset:21*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x20, x27, x23, x28, dyn, 128, 0, x13, 21*FLEN/8, x15, x1, x6) + +inst_20: +// rs1==x16, rs2==x9, rs3==x5, rd==x4,fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ba and fs2 == 1 and fe2 == 0x0f and fm2 == 0x20a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x053 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x16; op2:x9; op3:x5; dest:x4; op1val:0x35ba; op2val:0xbe0a; +op3val:0x3853; valaddr_reg:x13; val_offset:24*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x4, x16, x9, x5, dyn, 0, 0, x13, 24*FLEN/8, x15, x1, x6) + +inst_21: +// rs1==x20, rs2==x3, rs3==x10, rd==x12,fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ba and fs2 == 1 and fe2 == 0x0f and fm2 == 0x20a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x053 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x20; op2:x3; op3:x10; dest:x12; op1val:0x35ba; op2val:0xbe0a; +op3val:0x3853; valaddr_reg:x13; val_offset:27*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x12, x20, x3, x10, dyn, 32, 0, x13, 27*FLEN/8, x15, x1, x6) +RVTEST_VALBASEUPD(x8,test_dataset_2) + +inst_22: +// rs1==x15, rs2==x22, rs3==x3, rd==x7,fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ba and fs2 == 1 and fe2 == 0x0f and fm2 == 0x20a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x053 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x15; op2:x22; op3:x3; dest:x7; op1val:0x35ba; op2val:0xbe0a; +op3val:0x3853; valaddr_reg:x8; val_offset:0*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x7, x15, x22, x3, dyn, 64, 0, x8, 0*FLEN/8, x10, x1, x6) + +inst_23: +// rs1==x28, rs2==x11, rs3==x8, rd==x30,fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ba and fs2 == 1 and fe2 == 0x0f and fm2 == 0x20a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x053 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x28; op2:x11; op3:x8; dest:x30; op1val:0x35ba; op2val:0xbe0a; +op3val:0x3853; valaddr_reg:x8; val_offset:3*FLEN/8; rmval:dyn; +testreg:x6; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x30, x28, x11, x8, dyn, 96, 0, x8, 3*FLEN/8, x10, x1, x6) +RVTEST_SIGBASE(x3,signature_x3_0) + +inst_24: +// rs1==x13, rs2==x7, rs3==x12, rd==x31,fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ba and fs2 == 1 and fe2 == 0x0f and fm2 == 0x20a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x053 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x13; op2:x7; op3:x12; dest:x31; op1val:0x35ba; op2val:0xbe0a; +op3val:0x3853; valaddr_reg:x8; val_offset:6*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x13, x7, x12, dyn, 128, 0, x8, 6*FLEN/8, x10, x3, x5) + +inst_25: +// rs1==x21, rs2==x27, rs3==x7, rd==x15,fs1 == 0 and fe1 == 0x0e and fm1 == 0x05f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x363 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x00a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x21; op2:x27; op3:x7; dest:x15; op1val:0x385f; op2val:0xbb63; +op3val:0x380a; valaddr_reg:x8; val_offset:9*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x15, x21, x27, x7, dyn, 0, 0, x8, 9*FLEN/8, x10, x3, x5) + +inst_26: +// rs1==x11, rs2==x16, rs3==x29, rd==x13,fs1 == 0 and fe1 == 0x0e and fm1 == 0x05f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x363 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x00a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x11; op2:x16; op3:x29; dest:x13; op1val:0x385f; op2val:0xbb63; +op3val:0x380a; valaddr_reg:x8; val_offset:12*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x13, x11, x16, x29, dyn, 32, 0, x8, 12*FLEN/8, x10, x3, x5) + +inst_27: +// rs1==x4, rs2==x15, rs3==x31, rd==x16,fs1 == 0 and fe1 == 0x0e and fm1 == 0x05f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x363 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x00a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x4; op2:x15; op3:x31; dest:x16; op1val:0x385f; op2val:0xbb63; +op3val:0x380a; valaddr_reg:x8; val_offset:15*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x16, x4, x15, x31, dyn, 64, 0, x8, 15*FLEN/8, x10, x3, x5) + +inst_28: +// rs1==x18, rs2==x13, rs3==x19, rd==x23,fs1 == 0 and fe1 == 0x0e and fm1 == 0x05f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x363 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x00a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x18; op2:x13; op3:x19; dest:x23; op1val:0x385f; op2val:0xbb63; +op3val:0x380a; valaddr_reg:x8; val_offset:18*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x23, x18, x13, x19, dyn, 96, 0, x8, 18*FLEN/8, x10, x3, x5) + +inst_29: +// rs1==x30, rs2==x28, rs3==x20, rd==x9,fs1 == 0 and fe1 == 0x0e and fm1 == 0x05f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x363 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x00a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x28; op3:x20; dest:x9; op1val:0x385f; op2val:0xbb63; +op3val:0x380a; valaddr_reg:x8; val_offset:21*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x9, x30, x28, x20, dyn, 128, 0, x8, 21*FLEN/8, x10, x3, x5) + +inst_30: +// rs1==x12, rs2==x2, rs3==x16, rd==x1,fs1 == 0 and fe1 == 0x0e and fm1 == 0x276 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2b6 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x16c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x12; op2:x2; op3:x16; dest:x1; op1val:0x3a76; op2val:0xb2b6; +op3val:0x316c; valaddr_reg:x8; val_offset:24*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x1, x12, x2, x16, dyn, 0, 0, x8, 24*FLEN/8, x10, x3, x5) + +inst_31: +// rs1==x25, rs2==x21, rs3==x11, rd==x29,fs1 == 0 and fe1 == 0x0e and fm1 == 0x276 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2b6 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x16c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x25; op2:x21; op3:x11; dest:x29; op1val:0x3a76; op2val:0xb2b6; +op3val:0x316c; valaddr_reg:x8; val_offset:27*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x29, x25, x21, x11, dyn, 32, 0, x8, 27*FLEN/8, x10, x3, x5) + +inst_32: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x276 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2b6 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x16c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a76; op2val:0xb2b6; +op3val:0x316c; valaddr_reg:x8; val_offset:30*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 30*FLEN/8, x10, x3, x5) + +inst_33: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x276 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2b6 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x16c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a76; op2val:0xb2b6; +op3val:0x316c; valaddr_reg:x8; val_offset:33*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 33*FLEN/8, x10, x3, x5) + +inst_34: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x276 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2b6 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x16c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a76; op2val:0xb2b6; +op3val:0x316c; valaddr_reg:x8; val_offset:36*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 36*FLEN/8, x10, x3, x5) + +inst_35: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x348 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2ba and fs3 == 0 and fe3 == 0x0e and fm3 == 0x220 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b48; op2val:0xbaba; +op3val:0x3a20; valaddr_reg:x8; val_offset:39*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 39*FLEN/8, x10, x3, x5) + +inst_36: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x348 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2ba and fs3 == 0 and fe3 == 0x0e and fm3 == 0x220 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b48; op2val:0xbaba; +op3val:0x3a20; valaddr_reg:x8; val_offset:42*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 42*FLEN/8, x10, x3, x5) + +inst_37: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x348 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2ba and fs3 == 0 and fe3 == 0x0e and fm3 == 0x220 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b48; op2val:0xbaba; +op3val:0x3a20; valaddr_reg:x8; val_offset:45*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 45*FLEN/8, x10, x3, x5) + +inst_38: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x348 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2ba and fs3 == 0 and fe3 == 0x0e and fm3 == 0x220 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b48; op2val:0xbaba; +op3val:0x3a20; valaddr_reg:x8; val_offset:48*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 48*FLEN/8, x10, x3, x5) + +inst_39: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x348 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2ba and fs3 == 0 and fe3 == 0x0e and fm3 == 0x220 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b48; op2val:0xbaba; +op3val:0x3a20; valaddr_reg:x8; val_offset:51*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 51*FLEN/8, x10, x3, x5) + +inst_40: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1fc and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1dd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bd7; op2val:0xb9fc; +op3val:0x39dd; valaddr_reg:x8; val_offset:54*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 54*FLEN/8, x10, x3, x5) + +inst_41: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1fc and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1dd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bd7; op2val:0xb9fc; +op3val:0x39dd; valaddr_reg:x8; val_offset:57*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 57*FLEN/8, x10, x3, x5) + +inst_42: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1fc and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1dd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bd7; op2val:0xb9fc; +op3val:0x39dd; valaddr_reg:x8; val_offset:60*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 60*FLEN/8, x10, x3, x5) + +inst_43: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1fc and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1dd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bd7; op2val:0xb9fc; +op3val:0x39dd; valaddr_reg:x8; val_offset:63*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 63*FLEN/8, x10, x3, x5) + +inst_44: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1fc and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1dd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bd7; op2val:0xb9fc; +op3val:0x39dd; valaddr_reg:x8; val_offset:66*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 66*FLEN/8, x10, x3, x5) + +inst_45: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0bd and fs2 == 1 and fe2 == 0x0c and fm2 == 0x14a and fs3 == 0 and fe3 == 0x0b and fm3 == 0x244 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38bd; op2val:0xb14a; +op3val:0x2e44; valaddr_reg:x8; val_offset:69*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 69*FLEN/8, x10, x3, x5) + +inst_46: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0bd and fs2 == 1 and fe2 == 0x0c and fm2 == 0x14a and fs3 == 0 and fe3 == 0x0b and fm3 == 0x244 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38bd; op2val:0xb14a; +op3val:0x2e44; valaddr_reg:x8; val_offset:72*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 72*FLEN/8, x10, x3, x5) + +inst_47: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0bd and fs2 == 1 and fe2 == 0x0c and fm2 == 0x14a and fs3 == 0 and fe3 == 0x0b and fm3 == 0x244 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38bd; op2val:0xb14a; +op3val:0x2e44; valaddr_reg:x8; val_offset:75*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 75*FLEN/8, x10, x3, x5) + +inst_48: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0bd and fs2 == 1 and fe2 == 0x0c and fm2 == 0x14a and fs3 == 0 and fe3 == 0x0b and fm3 == 0x244 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38bd; op2val:0xb14a; +op3val:0x2e44; valaddr_reg:x8; val_offset:78*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 78*FLEN/8, x10, x3, x5) + +inst_49: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0bd and fs2 == 1 and fe2 == 0x0c and fm2 == 0x14a and fs3 == 0 and fe3 == 0x0b and fm3 == 0x244 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38bd; op2val:0xb14a; +op3val:0x2e44; valaddr_reg:x8; val_offset:81*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 81*FLEN/8, x10, x3, x5) + +inst_50: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0f7 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1b5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x317 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38f7; op2val:0xbdb5; +op3val:0x3b17; valaddr_reg:x8; val_offset:84*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 84*FLEN/8, x10, x3, x5) + +inst_51: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0f7 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1b5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x317 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38f7; op2val:0xbdb5; +op3val:0x3b17; valaddr_reg:x8; val_offset:87*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 87*FLEN/8, x10, x3, x5) + +inst_52: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0f7 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1b5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x317 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38f7; op2val:0xbdb5; +op3val:0x3b17; valaddr_reg:x8; val_offset:90*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 90*FLEN/8, x10, x3, x5) + +inst_53: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0f7 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1b5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x317 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38f7; op2val:0xbdb5; +op3val:0x3b17; valaddr_reg:x8; val_offset:93*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 93*FLEN/8, x10, x3, x5) + +inst_54: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0f7 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1b5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x317 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38f7; op2val:0xbdb5; +op3val:0x3b17; valaddr_reg:x8; val_offset:96*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 96*FLEN/8, x10, x3, x5) + +inst_55: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ee and fs2 == 1 and fe2 == 0x08 and fm2 == 0x1cc and fs3 == 0 and fe3 == 0x08 and fm3 == 0x04c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39ee; op2val:0xa1cc; +op3val:0x204c; valaddr_reg:x8; val_offset:99*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 99*FLEN/8, x10, x3, x5) + +inst_56: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ee and fs2 == 1 and fe2 == 0x08 and fm2 == 0x1cc and fs3 == 0 and fe3 == 0x08 and fm3 == 0x04c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39ee; op2val:0xa1cc; +op3val:0x204c; valaddr_reg:x8; val_offset:102*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 102*FLEN/8, x10, x3, x5) + +inst_57: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ee and fs2 == 1 and fe2 == 0x08 and fm2 == 0x1cc and fs3 == 0 and fe3 == 0x08 and fm3 == 0x04c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39ee; op2val:0xa1cc; +op3val:0x204c; valaddr_reg:x8; val_offset:105*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 105*FLEN/8, x10, x3, x5) + +inst_58: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ee and fs2 == 1 and fe2 == 0x08 and fm2 == 0x1cc and fs3 == 0 and fe3 == 0x08 and fm3 == 0x04c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39ee; op2val:0xa1cc; +op3val:0x204c; valaddr_reg:x8; val_offset:108*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 108*FLEN/8, x10, x3, x5) + +inst_59: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ee and fs2 == 1 and fe2 == 0x08 and fm2 == 0x1cc and fs3 == 0 and fe3 == 0x08 and fm3 == 0x04c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39ee; op2val:0xa1cc; +op3val:0x204c; valaddr_reg:x8; val_offset:111*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 111*FLEN/8, x10, x3, x5) + +inst_60: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x37e and fs2 == 1 and fe2 == 0x0d and fm2 == 0x27c and fs3 == 0 and fe3 == 0x0d and fm3 == 0x213 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b7e; op2val:0xb67c; +op3val:0x3613; valaddr_reg:x8; val_offset:114*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 114*FLEN/8, x10, x3, x5) + +inst_61: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x37e and fs2 == 1 and fe2 == 0x0d and fm2 == 0x27c and fs3 == 0 and fe3 == 0x0d and fm3 == 0x213 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b7e; op2val:0xb67c; +op3val:0x3613; valaddr_reg:x8; val_offset:117*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 117*FLEN/8, x10, x3, x5) + +inst_62: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x37e and fs2 == 1 and fe2 == 0x0d and fm2 == 0x27c and fs3 == 0 and fe3 == 0x0d and fm3 == 0x213 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b7e; op2val:0xb67c; +op3val:0x3613; valaddr_reg:x8; val_offset:120*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 120*FLEN/8, x10, x3, x5) + +inst_63: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x37e and fs2 == 1 and fe2 == 0x0d and fm2 == 0x27c and fs3 == 0 and fe3 == 0x0d and fm3 == 0x213 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b7e; op2val:0xb67c; +op3val:0x3613; valaddr_reg:x8; val_offset:123*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 123*FLEN/8, x10, x3, x5) + +inst_64: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x37e and fs2 == 1 and fe2 == 0x0d and fm2 == 0x27c and fs3 == 0 and fe3 == 0x0d and fm3 == 0x213 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b7e; op2val:0xb67c; +op3val:0x3613; valaddr_reg:x8; val_offset:126*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 126*FLEN/8, x10, x3, x5) + +inst_65: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x05b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x16d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38fb; op2val:0xb85b; +op3val:0x356d; valaddr_reg:x8; val_offset:129*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 129*FLEN/8, x10, x3, x5) + +inst_66: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x05b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x16d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38fb; op2val:0xb85b; +op3val:0x356d; valaddr_reg:x8; val_offset:132*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 132*FLEN/8, x10, x3, x5) + +inst_67: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x05b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x16d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38fb; op2val:0xb85b; +op3val:0x356d; valaddr_reg:x8; val_offset:135*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 135*FLEN/8, x10, x3, x5) + +inst_68: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x05b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x16d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38fb; op2val:0xb85b; +op3val:0x356d; valaddr_reg:x8; val_offset:138*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 138*FLEN/8, x10, x3, x5) + +inst_69: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x05b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x16d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38fb; op2val:0xb85b; +op3val:0x356d; valaddr_reg:x8; val_offset:141*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 141*FLEN/8, x10, x3, x5) + +inst_70: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x14a and fs2 == 1 and fe2 == 0x0d and fm2 == 0x377 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x394a; op2val:0xb777; +op3val:0x34f0; valaddr_reg:x8; val_offset:144*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 144*FLEN/8, x10, x3, x5) + +inst_71: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x14a and fs2 == 1 and fe2 == 0x0d and fm2 == 0x377 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0f0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x394a; op2val:0xb777; +op3val:0x34f0; valaddr_reg:x8; val_offset:147*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 147*FLEN/8, x10, x3, x5) + +inst_72: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x14a and fs2 == 1 and fe2 == 0x0d and fm2 == 0x377 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0f0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x394a; op2val:0xb777; +op3val:0x34f0; valaddr_reg:x8; val_offset:150*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 150*FLEN/8, x10, x3, x5) + +inst_73: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x14a and fs2 == 1 and fe2 == 0x0d and fm2 == 0x377 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0f0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x394a; op2val:0xb777; +op3val:0x34f0; valaddr_reg:x8; val_offset:153*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 153*FLEN/8, x10, x3, x5) + +inst_74: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x14a and fs2 == 1 and fe2 == 0x0d and fm2 == 0x377 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0f0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x394a; op2val:0xb777; +op3val:0x34f0; valaddr_reg:x8; val_offset:156*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 156*FLEN/8, x10, x3, x5) + +inst_75: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x004 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x193 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x19a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3804; op2val:0xb993; +op3val:0x359a; valaddr_reg:x8; val_offset:159*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 159*FLEN/8, x10, x3, x5) + +inst_76: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x004 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x193 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x19a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3804; op2val:0xb993; +op3val:0x359a; valaddr_reg:x8; val_offset:162*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 162*FLEN/8, x10, x3, x5) + +inst_77: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x004 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x193 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x19a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3804; op2val:0xb993; +op3val:0x359a; valaddr_reg:x8; val_offset:165*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 165*FLEN/8, x10, x3, x5) + +inst_78: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x004 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x193 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x19a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3804; op2val:0xb993; +op3val:0x359a; valaddr_reg:x8; val_offset:168*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 168*FLEN/8, x10, x3, x5) + +inst_79: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x004 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x193 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x19a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3804; op2val:0xb993; +op3val:0x359a; valaddr_reg:x8; val_offset:171*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 171*FLEN/8, x10, x3, x5) + +inst_80: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x24f and fs2 == 1 and fe2 == 0x11 and fm2 == 0x03e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e4f; op2val:0xc43e; +op3val:0x36b2; valaddr_reg:x8; val_offset:174*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 174*FLEN/8, x10, x3, x5) + +inst_81: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x24f and fs2 == 1 and fe2 == 0x11 and fm2 == 0x03e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e4f; op2val:0xc43e; +op3val:0x36b2; valaddr_reg:x8; val_offset:177*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 177*FLEN/8, x10, x3, x5) + +inst_82: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x24f and fs2 == 1 and fe2 == 0x11 and fm2 == 0x03e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e4f; op2val:0xc43e; +op3val:0x36b2; valaddr_reg:x8; val_offset:180*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 180*FLEN/8, x10, x3, x5) + +inst_83: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x24f and fs2 == 1 and fe2 == 0x11 and fm2 == 0x03e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e4f; op2val:0xc43e; +op3val:0x36b2; valaddr_reg:x8; val_offset:183*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 183*FLEN/8, x10, x3, x5) + +inst_84: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x24f and fs2 == 1 and fe2 == 0x11 and fm2 == 0x03e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e4f; op2val:0xc43e; +op3val:0x36b2; valaddr_reg:x8; val_offset:186*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 186*FLEN/8, x10, x3, x5) + +inst_85: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2dc and fs2 == 1 and fe2 == 0x0f and fm2 == 0x05c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x37c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3adc; op2val:0xbc5c; +op3val:0x3b7c; valaddr_reg:x8; val_offset:189*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 189*FLEN/8, x10, x3, x5) + +inst_86: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2dc and fs2 == 1 and fe2 == 0x0f and fm2 == 0x05c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x37c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3adc; op2val:0xbc5c; +op3val:0x3b7c; valaddr_reg:x8; val_offset:192*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 192*FLEN/8, x10, x3, x5) + +inst_87: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2dc and fs2 == 1 and fe2 == 0x0f and fm2 == 0x05c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x37c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3adc; op2val:0xbc5c; +op3val:0x3b7c; valaddr_reg:x8; val_offset:195*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 195*FLEN/8, x10, x3, x5) + +inst_88: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2dc and fs2 == 1 and fe2 == 0x0f and fm2 == 0x05c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x37c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3adc; op2val:0xbc5c; +op3val:0x3b7c; valaddr_reg:x8; val_offset:198*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 198*FLEN/8, x10, x3, x5) + +inst_89: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2dc and fs2 == 1 and fe2 == 0x0f and fm2 == 0x05c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x37c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3adc; op2val:0xbc5c; +op3val:0x3b7c; valaddr_reg:x8; val_offset:201*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 201*FLEN/8, x10, x3, x5) + +inst_90: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2e7 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0bd and fs3 == 0 and fe3 == 0x0e and fm3 == 0x017 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ae7; op2val:0xc8bd; +op3val:0x3817; valaddr_reg:x8; val_offset:204*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 204*FLEN/8, x10, x3, x5) + +inst_91: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2e7 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0bd and fs3 == 0 and fe3 == 0x0e and fm3 == 0x017 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ae7; op2val:0xc8bd; +op3val:0x3817; valaddr_reg:x8; val_offset:207*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 207*FLEN/8, x10, x3, x5) + +inst_92: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2e7 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0bd and fs3 == 0 and fe3 == 0x0e and fm3 == 0x017 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ae7; op2val:0xc8bd; +op3val:0x3817; valaddr_reg:x8; val_offset:210*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 210*FLEN/8, x10, x3, x5) + +inst_93: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2e7 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0bd and fs3 == 0 and fe3 == 0x0e and fm3 == 0x017 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ae7; op2val:0xc8bd; +op3val:0x3817; valaddr_reg:x8; val_offset:213*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 213*FLEN/8, x10, x3, x5) + +inst_94: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2e7 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0bd and fs3 == 0 and fe3 == 0x0e and fm3 == 0x017 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ae7; op2val:0xc8bd; +op3val:0x3817; valaddr_reg:x8; val_offset:216*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 216*FLEN/8, x10, x3, x5) + +inst_95: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x272 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x048 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x2e8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a72; op2val:0xac48; +op3val:0x2ae8; valaddr_reg:x8; val_offset:219*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 219*FLEN/8, x10, x3, x5) + +inst_96: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x272 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x048 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x2e8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a72; op2val:0xac48; +op3val:0x2ae8; valaddr_reg:x8; val_offset:222*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 222*FLEN/8, x10, x3, x5) + +inst_97: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x272 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x048 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x2e8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a72; op2val:0xac48; +op3val:0x2ae8; valaddr_reg:x8; val_offset:225*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 225*FLEN/8, x10, x3, x5) + +inst_98: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x272 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x048 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x2e8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a72; op2val:0xac48; +op3val:0x2ae8; valaddr_reg:x8; val_offset:228*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 228*FLEN/8, x10, x3, x5) + +inst_99: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x272 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x048 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x2e8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a72; op2val:0xac48; +op3val:0x2ae8; valaddr_reg:x8; val_offset:231*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 231*FLEN/8, x10, x3, x5) + +inst_100: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2bc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x126 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x056 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36bc; op2val:0xb926; +op3val:0x3456; valaddr_reg:x8; val_offset:234*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 234*FLEN/8, x10, x3, x5) + +inst_101: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2bc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x126 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x056 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36bc; op2val:0xb926; +op3val:0x3456; valaddr_reg:x8; val_offset:237*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 237*FLEN/8, x10, x3, x5) + +inst_102: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2bc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x126 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x056 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36bc; op2val:0xb926; +op3val:0x3456; valaddr_reg:x8; val_offset:240*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 240*FLEN/8, x10, x3, x5) + +inst_103: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2bc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x126 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x056 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36bc; op2val:0xb926; +op3val:0x3456; valaddr_reg:x8; val_offset:243*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 243*FLEN/8, x10, x3, x5) + +inst_104: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2bc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x126 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x056 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36bc; op2val:0xb926; +op3val:0x3456; valaddr_reg:x8; val_offset:246*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 246*FLEN/8, x10, x3, x5) + +inst_105: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x39e and fs2 == 1 and fe2 == 0x11 and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1b6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f9e; op2val:0xc600; +op3val:0x39b6; valaddr_reg:x8; val_offset:249*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 249*FLEN/8, x10, x3, x5) + +inst_106: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x39e and fs2 == 1 and fe2 == 0x11 and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1b6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f9e; op2val:0xc600; +op3val:0x39b6; valaddr_reg:x8; val_offset:252*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 252*FLEN/8, x10, x3, x5) + +inst_107: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x39e and fs2 == 1 and fe2 == 0x11 and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1b6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f9e; op2val:0xc600; +op3val:0x39b6; valaddr_reg:x8; val_offset:255*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 255*FLEN/8, x10, x3, x5) + +inst_108: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x39e and fs2 == 1 and fe2 == 0x11 and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1b6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f9e; op2val:0xc600; +op3val:0x39b6; valaddr_reg:x8; val_offset:258*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 258*FLEN/8, x10, x3, x5) + +inst_109: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x39e and fs2 == 1 and fe2 == 0x11 and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1b6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f9e; op2val:0xc600; +op3val:0x39b6; valaddr_reg:x8; val_offset:261*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 261*FLEN/8, x10, x3, x5) + +inst_110: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x125 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x210 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x3cd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3925; op2val:0xb210; +op3val:0x2fcd; valaddr_reg:x8; val_offset:264*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 264*FLEN/8, x10, x3, x5) + +inst_111: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x125 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x210 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x3cd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3925; op2val:0xb210; +op3val:0x2fcd; valaddr_reg:x8; val_offset:267*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 267*FLEN/8, x10, x3, x5) + +inst_112: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x125 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x210 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x3cd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3925; op2val:0xb210; +op3val:0x2fcd; valaddr_reg:x8; val_offset:270*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 270*FLEN/8, x10, x3, x5) + +inst_113: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x125 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x210 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x3cd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3925; op2val:0xb210; +op3val:0x2fcd; valaddr_reg:x8; val_offset:273*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 273*FLEN/8, x10, x3, x5) + +inst_114: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x125 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x210 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x3cd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3925; op2val:0xb210; +op3val:0x2fcd; valaddr_reg:x8; val_offset:276*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 276*FLEN/8, x10, x3, x5) + +inst_115: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2eb and fs2 == 1 and fe2 == 0x0d and fm2 == 0x05c and fs3 == 0 and fe3 == 0x0c and fm3 == 0x38a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aeb; op2val:0xb45c; +op3val:0x338a; valaddr_reg:x8; val_offset:279*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 279*FLEN/8, x10, x3, x5) + +inst_116: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2eb and fs2 == 1 and fe2 == 0x0d and fm2 == 0x05c and fs3 == 0 and fe3 == 0x0c and fm3 == 0x38a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aeb; op2val:0xb45c; +op3val:0x338a; valaddr_reg:x8; val_offset:282*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 282*FLEN/8, x10, x3, x5) + +inst_117: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2eb and fs2 == 1 and fe2 == 0x0d and fm2 == 0x05c and fs3 == 0 and fe3 == 0x0c and fm3 == 0x38a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aeb; op2val:0xb45c; +op3val:0x338a; valaddr_reg:x8; val_offset:285*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 285*FLEN/8, x10, x3, x5) + +inst_118: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2eb and fs2 == 1 and fe2 == 0x0d and fm2 == 0x05c and fs3 == 0 and fe3 == 0x0c and fm3 == 0x38a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aeb; op2val:0xb45c; +op3val:0x338a; valaddr_reg:x8; val_offset:288*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 288*FLEN/8, x10, x3, x5) + +inst_119: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2eb and fs2 == 1 and fe2 == 0x0d and fm2 == 0x05c and fs3 == 0 and fe3 == 0x0c and fm3 == 0x38a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aeb; op2val:0xb45c; +op3val:0x338a; valaddr_reg:x8; val_offset:291*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 291*FLEN/8, x10, x3, x5) + +inst_120: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x338 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x17e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0f5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b38; op2val:0xb57e; +op3val:0x34f5; valaddr_reg:x8; val_offset:294*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 294*FLEN/8, x10, x3, x5) + +inst_121: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x338 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x17e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0f5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b38; op2val:0xb57e; +op3val:0x34f5; valaddr_reg:x8; val_offset:297*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 297*FLEN/8, x10, x3, x5) + +inst_122: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x338 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x17e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0f5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b38; op2val:0xb57e; +op3val:0x34f5; valaddr_reg:x8; val_offset:300*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 300*FLEN/8, x10, x3, x5) + +inst_123: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x338 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x17e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0f5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b38; op2val:0xb57e; +op3val:0x34f5; valaddr_reg:x8; val_offset:303*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 303*FLEN/8, x10, x3, x5) + +inst_124: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x338 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x17e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0f5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b38; op2val:0xb57e; +op3val:0x34f5; valaddr_reg:x8; val_offset:306*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 306*FLEN/8, x10, x3, x5) + +inst_125: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0c4 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x15f and fs3 == 0 and fe3 == 0x0a and fm3 == 0x266 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34c4; op2val:0xb15f; +op3val:0x2a66; valaddr_reg:x8; val_offset:309*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 309*FLEN/8, x10, x3, x5) + +inst_126: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0c4 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x15f and fs3 == 0 and fe3 == 0x0a and fm3 == 0x266 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34c4; op2val:0xb15f; +op3val:0x2a66; valaddr_reg:x8; val_offset:312*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 312*FLEN/8, x10, x3, x5) + +inst_127: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0c4 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x15f and fs3 == 0 and fe3 == 0x0a and fm3 == 0x266 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34c4; op2val:0xb15f; +op3val:0x2a66; valaddr_reg:x8; val_offset:315*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 315*FLEN/8, x10, x3, x5) + +inst_128: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0c4 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x15f and fs3 == 0 and fe3 == 0x0a and fm3 == 0x266 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34c4; op2val:0xb15f; +op3val:0x2a66; valaddr_reg:x8; val_offset:318*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 318*FLEN/8, x10, x3, x5) + +inst_129: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0c4 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x15f and fs3 == 0 and fe3 == 0x0a and fm3 == 0x266 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34c4; op2val:0xb15f; +op3val:0x2a66; valaddr_reg:x8; val_offset:321*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 321*FLEN/8, x10, x3, x5) + +inst_130: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x102 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x257 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3f1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3102; op2val:0xc257; +op3val:0x37f1; valaddr_reg:x8; val_offset:324*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 324*FLEN/8, x10, x3, x5) + +inst_131: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x102 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x257 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3f1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3102; op2val:0xc257; +op3val:0x37f1; valaddr_reg:x8; val_offset:327*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 327*FLEN/8, x10, x3, x5) + +inst_132: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x102 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x257 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3f1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3102; op2val:0xc257; +op3val:0x37f1; valaddr_reg:x8; val_offset:330*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 330*FLEN/8, x10, x3, x5) + +inst_133: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x102 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x257 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3f1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3102; op2val:0xc257; +op3val:0x37f1; valaddr_reg:x8; val_offset:333*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 333*FLEN/8, x10, x3, x5) + +inst_134: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x102 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x257 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3f1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3102; op2val:0xc257; +op3val:0x37f1; valaddr_reg:x8; val_offset:336*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 336*FLEN/8, x10, x3, x5) + +inst_135: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x26b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x03c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2cc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a6b; op2val:0xbc3c; +op3val:0x3acc; valaddr_reg:x8; val_offset:339*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 339*FLEN/8, x10, x3, x5) + +inst_136: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x26b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x03c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2cc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a6b; op2val:0xbc3c; +op3val:0x3acc; valaddr_reg:x8; val_offset:342*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 342*FLEN/8, x10, x3, x5) + +inst_137: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x26b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x03c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2cc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a6b; op2val:0xbc3c; +op3val:0x3acc; valaddr_reg:x8; val_offset:345*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 345*FLEN/8, x10, x3, x5) + +inst_138: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x26b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x03c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2cc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a6b; op2val:0xbc3c; +op3val:0x3acc; valaddr_reg:x8; val_offset:348*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 348*FLEN/8, x10, x3, x5) + +inst_139: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x26b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x03c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2cc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a6b; op2val:0xbc3c; +op3val:0x3acc; valaddr_reg:x8; val_offset:351*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 351*FLEN/8, x10, x3, x5) + +inst_140: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x38a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x029 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3d7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x378a; op2val:0xbc29; +op3val:0x37d7; valaddr_reg:x8; val_offset:354*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 354*FLEN/8, x10, x3, x5) + +inst_141: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x38a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x029 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3d7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x378a; op2val:0xbc29; +op3val:0x37d7; valaddr_reg:x8; val_offset:357*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 357*FLEN/8, x10, x3, x5) + +inst_142: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x38a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x029 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3d7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x378a; op2val:0xbc29; +op3val:0x37d7; valaddr_reg:x8; val_offset:360*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 360*FLEN/8, x10, x3, x5) + +inst_143: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x38a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x029 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3d7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x378a; op2val:0xbc29; +op3val:0x37d7; valaddr_reg:x8; val_offset:363*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 363*FLEN/8, x10, x3, x5) + +inst_144: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x38a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x029 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3d7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x378a; op2val:0xbc29; +op3val:0x37d7; valaddr_reg:x8; val_offset:366*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 366*FLEN/8, x10, x3, x5) + +inst_145: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36d and fs2 == 1 and fe2 == 0x0b and fm2 == 0x2ab and fs3 == 0 and fe3 == 0x0b and fm3 == 0x231 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b6d; op2val:0xaeab; +op3val:0x2e31; valaddr_reg:x8; val_offset:369*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 369*FLEN/8, x10, x3, x5) + +inst_146: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36d and fs2 == 1 and fe2 == 0x0b and fm2 == 0x2ab and fs3 == 0 and fe3 == 0x0b and fm3 == 0x231 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b6d; op2val:0xaeab; +op3val:0x2e31; valaddr_reg:x8; val_offset:372*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 372*FLEN/8, x10, x3, x5) + +inst_147: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36d and fs2 == 1 and fe2 == 0x0b and fm2 == 0x2ab and fs3 == 0 and fe3 == 0x0b and fm3 == 0x231 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b6d; op2val:0xaeab; +op3val:0x2e31; valaddr_reg:x8; val_offset:375*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 375*FLEN/8, x10, x3, x5) + +inst_148: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36d and fs2 == 1 and fe2 == 0x0b and fm2 == 0x2ab and fs3 == 0 and fe3 == 0x0b and fm3 == 0x231 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b6d; op2val:0xaeab; +op3val:0x2e31; valaddr_reg:x8; val_offset:378*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 378*FLEN/8, x10, x3, x5) + +inst_149: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36d and fs2 == 1 and fe2 == 0x0b and fm2 == 0x2ab and fs3 == 0 and fe3 == 0x0b and fm3 == 0x231 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b6d; op2val:0xaeab; +op3val:0x2e31; valaddr_reg:x8; val_offset:381*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 381*FLEN/8, x10, x3, x5) + +inst_150: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3e1 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0d9 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0c7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37e1; op2val:0xb8d9; +op3val:0x34c7; valaddr_reg:x8; val_offset:384*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 384*FLEN/8, x10, x3, x5) + +inst_151: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3e1 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0d9 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0c7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37e1; op2val:0xb8d9; +op3val:0x34c7; valaddr_reg:x8; val_offset:387*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 387*FLEN/8, x10, x3, x5) +RVTEST_SIGBASE(x3,signature_x3_1) + +inst_152: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3e1 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0d9 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0c7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37e1; op2val:0xb8d9; +op3val:0x34c7; valaddr_reg:x8; val_offset:390*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 390*FLEN/8, x10, x3, x5) + +inst_153: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3e1 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0d9 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0c7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37e1; op2val:0xb8d9; +op3val:0x34c7; valaddr_reg:x8; val_offset:393*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 393*FLEN/8, x10, x3, x5) + +inst_154: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3e1 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0d9 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0c7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37e1; op2val:0xb8d9; +op3val:0x34c7; valaddr_reg:x8; val_offset:396*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 396*FLEN/8, x10, x3, x5) + +inst_155: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3c1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x20c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a3d; op2val:0xbbc1; +op3val:0x3a0c; valaddr_reg:x8; val_offset:399*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 399*FLEN/8, x10, x3, x5) + +inst_156: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3c1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x20c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a3d; op2val:0xbbc1; +op3val:0x3a0c; valaddr_reg:x8; val_offset:402*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 402*FLEN/8, x10, x3, x5) + +inst_157: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3c1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x20c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a3d; op2val:0xbbc1; +op3val:0x3a0c; valaddr_reg:x8; val_offset:405*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 405*FLEN/8, x10, x3, x5) + +inst_158: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3c1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x20c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a3d; op2val:0xbbc1; +op3val:0x3a0c; valaddr_reg:x8; val_offset:408*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 408*FLEN/8, x10, x3, x5) + +inst_159: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3c1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x20c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a3d; op2val:0xbbc1; +op3val:0x3a0c; valaddr_reg:x8; val_offset:411*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 411*FLEN/8, x10, x3, x5) + +inst_160: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x151 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x141 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3be7; op2val:0xb951; +op3val:0x3941; valaddr_reg:x8; val_offset:414*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 414*FLEN/8, x10, x3, x5) + +inst_161: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x151 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x141 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3be7; op2val:0xb951; +op3val:0x3941; valaddr_reg:x8; val_offset:417*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 417*FLEN/8, x10, x3, x5) + +inst_162: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x151 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x141 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3be7; op2val:0xb951; +op3val:0x3941; valaddr_reg:x8; val_offset:420*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 420*FLEN/8, x10, x3, x5) + +inst_163: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x151 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x141 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3be7; op2val:0xb951; +op3val:0x3941; valaddr_reg:x8; val_offset:423*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 423*FLEN/8, x10, x3, x5) + +inst_164: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x151 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x141 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3be7; op2val:0xb951; +op3val:0x3941; valaddr_reg:x8; val_offset:426*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 426*FLEN/8, x10, x3, x5) + +inst_165: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1dd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x24a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x09c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39dd; op2val:0xba4a; +op3val:0x389c; valaddr_reg:x8; val_offset:429*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 429*FLEN/8, x10, x3, x5) + +inst_166: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1dd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x24a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x09c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39dd; op2val:0xba4a; +op3val:0x389c; valaddr_reg:x8; val_offset:432*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 432*FLEN/8, x10, x3, x5) + +inst_167: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1dd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x24a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x09c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39dd; op2val:0xba4a; +op3val:0x389c; valaddr_reg:x8; val_offset:435*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 435*FLEN/8, x10, x3, x5) + +inst_168: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1dd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x24a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x09c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39dd; op2val:0xba4a; +op3val:0x389c; valaddr_reg:x8; val_offset:438*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 438*FLEN/8, x10, x3, x5) + +inst_169: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1dd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x24a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x09c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39dd; op2val:0xba4a; +op3val:0x389c; valaddr_reg:x8; val_offset:441*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 441*FLEN/8, x10, x3, x5) + +inst_170: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0fc and fs2 == 1 and fe2 == 0x0d and fm2 == 0x041 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x14d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38fc; op2val:0xb441; +op3val:0x314d; valaddr_reg:x8; val_offset:444*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 444*FLEN/8, x10, x3, x5) + +inst_171: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0fc and fs2 == 1 and fe2 == 0x0d and fm2 == 0x041 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x14d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38fc; op2val:0xb441; +op3val:0x314d; valaddr_reg:x8; val_offset:447*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 447*FLEN/8, x10, x3, x5) + +inst_172: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0fc and fs2 == 1 and fe2 == 0x0d and fm2 == 0x041 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x14d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38fc; op2val:0xb441; +op3val:0x314d; valaddr_reg:x8; val_offset:450*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 450*FLEN/8, x10, x3, x5) + +inst_173: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0fc and fs2 == 1 and fe2 == 0x0d and fm2 == 0x041 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x14d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38fc; op2val:0xb441; +op3val:0x314d; valaddr_reg:x8; val_offset:453*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 453*FLEN/8, x10, x3, x5) + +inst_174: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0fc and fs2 == 1 and fe2 == 0x0d and fm2 == 0x041 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x14d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38fc; op2val:0xb441; +op3val:0x314d; valaddr_reg:x8; val_offset:456*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 456*FLEN/8, x10, x3, x5) + +inst_175: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2f2 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x399 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x299 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ef2; op2val:0xc799; +op3val:0x3a99; valaddr_reg:x8; val_offset:459*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 459*FLEN/8, x10, x3, x5) + +inst_176: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2f2 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x399 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x299 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ef2; op2val:0xc799; +op3val:0x3a99; valaddr_reg:x8; val_offset:462*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 462*FLEN/8, x10, x3, x5) + +inst_177: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2f2 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x399 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x299 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ef2; op2val:0xc799; +op3val:0x3a99; valaddr_reg:x8; val_offset:465*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 465*FLEN/8, x10, x3, x5) + +inst_178: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2f2 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x399 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x299 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ef2; op2val:0xc799; +op3val:0x3a99; valaddr_reg:x8; val_offset:468*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 468*FLEN/8, x10, x3, x5) + +inst_179: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2f2 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x399 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x299 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ef2; op2val:0xc799; +op3val:0x3a99; valaddr_reg:x8; val_offset:471*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 471*FLEN/8, x10, x3, x5) + +inst_180: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x186 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ab and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38d4; op2val:0xbd86; +op3val:0x3aab; valaddr_reg:x8; val_offset:474*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 474*FLEN/8, x10, x3, x5) + +inst_181: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x186 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ab and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38d4; op2val:0xbd86; +op3val:0x3aab; valaddr_reg:x8; val_offset:477*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 477*FLEN/8, x10, x3, x5) + +inst_182: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x186 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ab and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38d4; op2val:0xbd86; +op3val:0x3aab; valaddr_reg:x8; val_offset:480*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 480*FLEN/8, x10, x3, x5) + +inst_183: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x186 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ab and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38d4; op2val:0xbd86; +op3val:0x3aab; valaddr_reg:x8; val_offset:483*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 483*FLEN/8, x10, x3, x5) + +inst_184: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x186 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ab and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38d4; op2val:0xbd86; +op3val:0x3aab; valaddr_reg:x8; val_offset:486*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 486*FLEN/8, x10, x3, x5) + +inst_185: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x163 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x0c7 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x270 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3563; op2val:0xacc7; +op3val:0x2670; valaddr_reg:x8; val_offset:489*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 489*FLEN/8, x10, x3, x5) + +inst_186: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x163 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x0c7 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x270 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3563; op2val:0xacc7; +op3val:0x2670; valaddr_reg:x8; val_offset:492*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 492*FLEN/8, x10, x3, x5) + +inst_187: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x163 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x0c7 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x270 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3563; op2val:0xacc7; +op3val:0x2670; valaddr_reg:x8; val_offset:495*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 495*FLEN/8, x10, x3, x5) + +inst_188: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x163 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x0c7 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x270 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3563; op2val:0xacc7; +op3val:0x2670; valaddr_reg:x8; val_offset:498*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 498*FLEN/8, x10, x3, x5) + +inst_189: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x163 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x0c7 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x270 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3563; op2val:0xacc7; +op3val:0x2670; valaddr_reg:x8; val_offset:501*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 501*FLEN/8, x10, x3, x5) + +inst_190: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x262 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0ae and fs3 == 0 and fe3 == 0x0c and fm3 == 0x379 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a62; op2val:0xb4ae; +op3val:0x3379; valaddr_reg:x8; val_offset:504*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 504*FLEN/8, x10, x3, x5) + +inst_191: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x262 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0ae and fs3 == 0 and fe3 == 0x0c and fm3 == 0x379 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a62; op2val:0xb4ae; +op3val:0x3379; valaddr_reg:x8; val_offset:507*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 507*FLEN/8, x10, x3, x5) + +inst_192: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x262 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0ae and fs3 == 0 and fe3 == 0x0c and fm3 == 0x379 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a62; op2val:0xb4ae; +op3val:0x3379; valaddr_reg:x8; val_offset:510*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 510*FLEN/8, x10, x3, x5) + +inst_193: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x262 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0ae and fs3 == 0 and fe3 == 0x0c and fm3 == 0x379 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a62; op2val:0xb4ae; +op3val:0x3379; valaddr_reg:x8; val_offset:513*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 513*FLEN/8, x10, x3, x5) + +inst_194: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x262 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0ae and fs3 == 0 and fe3 == 0x0c and fm3 == 0x379 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a62; op2val:0xb4ae; +op3val:0x3379; valaddr_reg:x8; val_offset:516*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 516*FLEN/8, x10, x3, x5) + +inst_195: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x199 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1a3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3e4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3999; op2val:0xbda3; +op3val:0x3be4; valaddr_reg:x8; val_offset:519*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 519*FLEN/8, x10, x3, x5) + +inst_196: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x199 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1a3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3e4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3999; op2val:0xbda3; +op3val:0x3be4; valaddr_reg:x8; val_offset:522*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 522*FLEN/8, x10, x3, x5) + +inst_197: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x199 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1a3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3e4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3999; op2val:0xbda3; +op3val:0x3be4; valaddr_reg:x8; val_offset:525*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 525*FLEN/8, x10, x3, x5) + +inst_198: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x199 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1a3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3e4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3999; op2val:0xbda3; +op3val:0x3be4; valaddr_reg:x8; val_offset:528*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 528*FLEN/8, x10, x3, x5) + +inst_199: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x199 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1a3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3e4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3999; op2val:0xbda3; +op3val:0x3be4; valaddr_reg:x8; val_offset:531*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 531*FLEN/8, x10, x3, x5) + +inst_200: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x38a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x195 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x143 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x338a; op2val:0xc195; +op3val:0x3943; valaddr_reg:x8; val_offset:534*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 534*FLEN/8, x10, x3, x5) + +inst_201: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x38a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x195 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x143 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x338a; op2val:0xc195; +op3val:0x3943; valaddr_reg:x8; val_offset:537*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 537*FLEN/8, x10, x3, x5) + +inst_202: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x38a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x195 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x143 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x338a; op2val:0xc195; +op3val:0x3943; valaddr_reg:x8; val_offset:540*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 540*FLEN/8, x10, x3, x5) + +inst_203: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x38a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x195 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x143 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x338a; op2val:0xc195; +op3val:0x3943; valaddr_reg:x8; val_offset:543*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 543*FLEN/8, x10, x3, x5) + +inst_204: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x38a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x195 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x143 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x338a; op2val:0xc195; +op3val:0x3943; valaddr_reg:x8; val_offset:546*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 546*FLEN/8, x10, x3, x5) + +inst_205: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2a3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x170 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x083 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aa3; op2val:0xb970; +op3val:0x3883; valaddr_reg:x8; val_offset:549*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 549*FLEN/8, x10, x3, x5) + +inst_206: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2a3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x170 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x083 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aa3; op2val:0xb970; +op3val:0x3883; valaddr_reg:x8; val_offset:552*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 552*FLEN/8, x10, x3, x5) + +inst_207: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2a3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x170 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x083 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aa3; op2val:0xb970; +op3val:0x3883; valaddr_reg:x8; val_offset:555*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 555*FLEN/8, x10, x3, x5) + +inst_208: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2a3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x170 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x083 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aa3; op2val:0xb970; +op3val:0x3883; valaddr_reg:x8; val_offset:558*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 558*FLEN/8, x10, x3, x5) + +inst_209: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2a3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x170 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x083 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aa3; op2val:0xb970; +op3val:0x3883; valaddr_reg:x8; val_offset:561*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 561*FLEN/8, x10, x3, x5) + +inst_210: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x225 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x224 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0b8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a25; op2val:0xba24; +op3val:0x38b8; valaddr_reg:x8; val_offset:564*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 564*FLEN/8, x10, x3, x5) + +inst_211: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x225 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x224 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0b8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a25; op2val:0xba24; +op3val:0x38b8; valaddr_reg:x8; val_offset:567*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 567*FLEN/8, x10, x3, x5) + +inst_212: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x225 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x224 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0b8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a25; op2val:0xba24; +op3val:0x38b8; valaddr_reg:x8; val_offset:570*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 570*FLEN/8, x10, x3, x5) + +inst_213: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x225 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x224 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0b8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a25; op2val:0xba24; +op3val:0x38b8; valaddr_reg:x8; val_offset:573*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 573*FLEN/8, x10, x3, x5) + +inst_214: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x225 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x224 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0b8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a25; op2val:0xba24; +op3val:0x38b8; valaddr_reg:x8; val_offset:576*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 576*FLEN/8, x10, x3, x5) + +inst_215: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x06e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x034 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0a8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x386e; op2val:0xbc34; +op3val:0x38a8; valaddr_reg:x8; val_offset:579*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 579*FLEN/8, x10, x3, x5) + +inst_216: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x06e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x034 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0a8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x386e; op2val:0xbc34; +op3val:0x38a8; valaddr_reg:x8; val_offset:582*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 582*FLEN/8, x10, x3, x5) + +inst_217: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x06e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x034 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0a8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x386e; op2val:0xbc34; +op3val:0x38a8; valaddr_reg:x8; val_offset:585*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 585*FLEN/8, x10, x3, x5) + +inst_218: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x06e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x034 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0a8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x386e; op2val:0xbc34; +op3val:0x38a8; valaddr_reg:x8; val_offset:588*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 588*FLEN/8, x10, x3, x5) + +inst_219: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x06e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x034 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0a8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x386e; op2val:0xbc34; +op3val:0x38a8; valaddr_reg:x8; val_offset:591*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 591*FLEN/8, x10, x3, x5) + +inst_220: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x295 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2ea and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1b0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3695; op2val:0xbeea; +op3val:0x39b0; valaddr_reg:x8; val_offset:594*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 594*FLEN/8, x10, x3, x5) + +inst_221: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x295 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2ea and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1b0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3695; op2val:0xbeea; +op3val:0x39b0; valaddr_reg:x8; val_offset:597*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 597*FLEN/8, x10, x3, x5) + +inst_222: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x295 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2ea and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1b0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3695; op2val:0xbeea; +op3val:0x39b0; valaddr_reg:x8; val_offset:600*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 600*FLEN/8, x10, x3, x5) + +inst_223: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x295 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2ea and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1b0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3695; op2val:0xbeea; +op3val:0x39b0; valaddr_reg:x8; val_offset:603*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 603*FLEN/8, x10, x3, x5) + +inst_224: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x295 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2ea and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1b0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3695; op2val:0xbeea; +op3val:0x39b0; valaddr_reg:x8; val_offset:606*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 606*FLEN/8, x10, x3, x5) + +inst_225: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x33d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x00b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x351 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b3d; op2val:0xbc0b; +op3val:0x3b51; valaddr_reg:x8; val_offset:609*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 609*FLEN/8, x10, x3, x5) + +inst_226: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x33d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x00b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x351 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b3d; op2val:0xbc0b; +op3val:0x3b51; valaddr_reg:x8; val_offset:612*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 612*FLEN/8, x10, x3, x5) + +inst_227: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x33d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x00b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x351 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b3d; op2val:0xbc0b; +op3val:0x3b51; valaddr_reg:x8; val_offset:615*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 615*FLEN/8, x10, x3, x5) + +inst_228: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x33d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x00b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x351 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b3d; op2val:0xbc0b; +op3val:0x3b51; valaddr_reg:x8; val_offset:618*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 618*FLEN/8, x10, x3, x5) + +inst_229: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x33d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x00b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x351 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b3d; op2val:0xbc0b; +op3val:0x3b51; valaddr_reg:x8; val_offset:621*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 621*FLEN/8, x10, x3, x5) + +inst_230: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x325 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x04a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b25; op2val:0xb84a; +op3val:0x37aa; valaddr_reg:x8; val_offset:624*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 624*FLEN/8, x10, x3, x5) + +inst_231: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x325 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x04a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3aa and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b25; op2val:0xb84a; +op3val:0x37aa; valaddr_reg:x8; val_offset:627*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 627*FLEN/8, x10, x3, x5) + +inst_232: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x325 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x04a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3aa and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b25; op2val:0xb84a; +op3val:0x37aa; valaddr_reg:x8; val_offset:630*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 630*FLEN/8, x10, x3, x5) + +inst_233: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x325 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x04a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3aa and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b25; op2val:0xb84a; +op3val:0x37aa; valaddr_reg:x8; val_offset:633*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 633*FLEN/8, x10, x3, x5) + +inst_234: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x325 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x04a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3aa and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b25; op2val:0xb84a; +op3val:0x37aa; valaddr_reg:x8; val_offset:636*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 636*FLEN/8, x10, x3, x5) + +inst_235: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11e and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0cf and fs3 == 0 and fe3 == 0x0c and fm3 == 0x227 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x391e; op2val:0xb4cf; +op3val:0x3227; valaddr_reg:x8; val_offset:639*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 639*FLEN/8, x10, x3, x5) + +inst_236: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11e and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0cf and fs3 == 0 and fe3 == 0x0c and fm3 == 0x227 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x391e; op2val:0xb4cf; +op3val:0x3227; valaddr_reg:x8; val_offset:642*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 642*FLEN/8, x10, x3, x5) + +inst_237: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11e and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0cf and fs3 == 0 and fe3 == 0x0c and fm3 == 0x227 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x391e; op2val:0xb4cf; +op3val:0x3227; valaddr_reg:x8; val_offset:645*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 645*FLEN/8, x10, x3, x5) + +inst_238: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11e and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0cf and fs3 == 0 and fe3 == 0x0c and fm3 == 0x227 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x391e; op2val:0xb4cf; +op3val:0x3227; valaddr_reg:x8; val_offset:648*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 648*FLEN/8, x10, x3, x5) + +inst_239: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11e and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0cf and fs3 == 0 and fe3 == 0x0c and fm3 == 0x227 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x391e; op2val:0xb4cf; +op3val:0x3227; valaddr_reg:x8; val_offset:651*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 651*FLEN/8, x10, x3, x5) + +inst_240: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3eb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0b7 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0ab and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37eb; op2val:0xb8b7; +op3val:0x34ab; valaddr_reg:x8; val_offset:654*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 654*FLEN/8, x10, x3, x5) + +inst_241: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3eb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0b7 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0ab and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37eb; op2val:0xb8b7; +op3val:0x34ab; valaddr_reg:x8; val_offset:657*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 657*FLEN/8, x10, x3, x5) + +inst_242: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3eb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0b7 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0ab and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37eb; op2val:0xb8b7; +op3val:0x34ab; valaddr_reg:x8; val_offset:660*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 660*FLEN/8, x10, x3, x5) + +inst_243: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3eb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0b7 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0ab and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37eb; op2val:0xb8b7; +op3val:0x34ab; valaddr_reg:x8; val_offset:663*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 663*FLEN/8, x10, x3, x5) + +inst_244: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3eb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0b7 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0ab and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37eb; op2val:0xb8b7; +op3val:0x34ab; valaddr_reg:x8; val_offset:666*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 666*FLEN/8, x10, x3, x5) + +inst_245: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x11d and fs2 == 1 and fe2 == 0x14 and fm2 == 0x1dc and fs3 == 0 and fe3 == 0x0e and fm3 == 0x37f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x251d; op2val:0xd1dc; +op3val:0x3b7f; valaddr_reg:x8; val_offset:669*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 669*FLEN/8, x10, x3, x5) + +inst_246: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x11d and fs2 == 1 and fe2 == 0x14 and fm2 == 0x1dc and fs3 == 0 and fe3 == 0x0e and fm3 == 0x37f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x251d; op2val:0xd1dc; +op3val:0x3b7f; valaddr_reg:x8; val_offset:672*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 672*FLEN/8, x10, x3, x5) + +inst_247: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x11d and fs2 == 1 and fe2 == 0x14 and fm2 == 0x1dc and fs3 == 0 and fe3 == 0x0e and fm3 == 0x37f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x251d; op2val:0xd1dc; +op3val:0x3b7f; valaddr_reg:x8; val_offset:675*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 675*FLEN/8, x10, x3, x5) + +inst_248: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x11d and fs2 == 1 and fe2 == 0x14 and fm2 == 0x1dc and fs3 == 0 and fe3 == 0x0e and fm3 == 0x37f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x251d; op2val:0xd1dc; +op3val:0x3b7f; valaddr_reg:x8; val_offset:678*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 678*FLEN/8, x10, x3, x5) + +inst_249: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x11d and fs2 == 1 and fe2 == 0x14 and fm2 == 0x1dc and fs3 == 0 and fe3 == 0x0e and fm3 == 0x37f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x251d; op2val:0xd1dc; +op3val:0x3b7f; valaddr_reg:x8; val_offset:681*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 681*FLEN/8, x10, x3, x5) + +inst_250: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3dd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2fe and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bdd; op2val:0xbafe; +op3val:0x3ae0; valaddr_reg:x8; val_offset:684*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 684*FLEN/8, x10, x3, x5) + +inst_251: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3dd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2fe and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2e0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bdd; op2val:0xbafe; +op3val:0x3ae0; valaddr_reg:x8; val_offset:687*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 687*FLEN/8, x10, x3, x5) + +inst_252: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3dd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2fe and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2e0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bdd; op2val:0xbafe; +op3val:0x3ae0; valaddr_reg:x8; val_offset:690*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 690*FLEN/8, x10, x3, x5) + +inst_253: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3dd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2fe and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2e0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bdd; op2val:0xbafe; +op3val:0x3ae0; valaddr_reg:x8; val_offset:693*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 693*FLEN/8, x10, x3, x5) + +inst_254: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3dd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2fe and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2e0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bdd; op2val:0xbafe; +op3val:0x3ae0; valaddr_reg:x8; val_offset:696*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 696*FLEN/8, x10, x3, x5) + +inst_255: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x18f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2d2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38e8; op2val:0xb98f; +op3val:0x36d2; valaddr_reg:x8; val_offset:699*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 699*FLEN/8, x10, x3, x5) + +inst_256: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x18f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2d2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38e8; op2val:0xb98f; +op3val:0x36d2; valaddr_reg:x8; val_offset:702*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 702*FLEN/8, x10, x3, x5) + +inst_257: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x18f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2d2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38e8; op2val:0xb98f; +op3val:0x36d2; valaddr_reg:x8; val_offset:705*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 705*FLEN/8, x10, x3, x5) + +inst_258: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x18f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2d2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38e8; op2val:0xb98f; +op3val:0x36d2; valaddr_reg:x8; val_offset:708*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 708*FLEN/8, x10, x3, x5) + +inst_259: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x18f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2d2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38e8; op2val:0xb98f; +op3val:0x36d2; valaddr_reg:x8; val_offset:711*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 711*FLEN/8, x10, x3, x5) + +inst_260: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x019 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x10f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x130 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3419; op2val:0xc10f; +op3val:0x3930; valaddr_reg:x8; val_offset:714*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 714*FLEN/8, x10, x3, x5) + +inst_261: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x019 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x10f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x130 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3419; op2val:0xc10f; +op3val:0x3930; valaddr_reg:x8; val_offset:717*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 717*FLEN/8, x10, x3, x5) + +inst_262: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x019 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x10f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x130 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3419; op2val:0xc10f; +op3val:0x3930; valaddr_reg:x8; val_offset:720*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 720*FLEN/8, x10, x3, x5) + +inst_263: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x019 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x10f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x130 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3419; op2val:0xc10f; +op3val:0x3930; valaddr_reg:x8; val_offset:723*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 723*FLEN/8, x10, x3, x5) + +inst_264: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x019 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x10f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x130 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3419; op2val:0xc10f; +op3val:0x3930; valaddr_reg:x8; val_offset:726*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 726*FLEN/8, x10, x3, x5) + +inst_265: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x07e and fs2 == 1 and fe2 == 0x13 and fm2 == 0x31a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3f9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x287e; op2val:0xcf1a; +op3val:0x3bf9; valaddr_reg:x8; val_offset:729*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 729*FLEN/8, x10, x3, x5) + +inst_266: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x07e and fs2 == 1 and fe2 == 0x13 and fm2 == 0x31a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3f9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x287e; op2val:0xcf1a; +op3val:0x3bf9; valaddr_reg:x8; val_offset:732*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 732*FLEN/8, x10, x3, x5) + +inst_267: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x07e and fs2 == 1 and fe2 == 0x13 and fm2 == 0x31a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3f9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x287e; op2val:0xcf1a; +op3val:0x3bf9; valaddr_reg:x8; val_offset:735*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 735*FLEN/8, x10, x3, x5) + +inst_268: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x07e and fs2 == 1 and fe2 == 0x13 and fm2 == 0x31a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3f9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x287e; op2val:0xcf1a; +op3val:0x3bf9; valaddr_reg:x8; val_offset:738*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 738*FLEN/8, x10, x3, x5) + +inst_269: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x07e and fs2 == 1 and fe2 == 0x13 and fm2 == 0x31a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3f9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x287e; op2val:0xcf1a; +op3val:0x3bf9; valaddr_reg:x8; val_offset:741*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 741*FLEN/8, x10, x3, x5) + +inst_270: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x142 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0ce and fs3 == 0 and fe3 == 0x0e and fm3 == 0x251 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3142; op2val:0xc4ce; +op3val:0x3a51; valaddr_reg:x8; val_offset:744*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 744*FLEN/8, x10, x3, x5) + +inst_271: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x142 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0ce and fs3 == 0 and fe3 == 0x0e and fm3 == 0x251 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3142; op2val:0xc4ce; +op3val:0x3a51; valaddr_reg:x8; val_offset:747*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 747*FLEN/8, x10, x3, x5) + +inst_272: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x142 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0ce and fs3 == 0 and fe3 == 0x0e and fm3 == 0x251 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3142; op2val:0xc4ce; +op3val:0x3a51; valaddr_reg:x8; val_offset:750*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 750*FLEN/8, x10, x3, x5) + +inst_273: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x142 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0ce and fs3 == 0 and fe3 == 0x0e and fm3 == 0x251 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3142; op2val:0xc4ce; +op3val:0x3a51; valaddr_reg:x8; val_offset:753*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 753*FLEN/8, x10, x3, x5) + +inst_274: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x142 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0ce and fs3 == 0 and fe3 == 0x0e and fm3 == 0x251 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3142; op2val:0xc4ce; +op3val:0x3a51; valaddr_reg:x8; val_offset:756*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 756*FLEN/8, x10, x3, x5) + +inst_275: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3fd and fs2 == 1 and fe2 == 0x11 and fm2 == 0x3be and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3bc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ffd; op2val:0xc7be; +op3val:0x3bbc; valaddr_reg:x8; val_offset:759*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 759*FLEN/8, x10, x3, x5) + +inst_276: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3fd and fs2 == 1 and fe2 == 0x11 and fm2 == 0x3be and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3bc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ffd; op2val:0xc7be; +op3val:0x3bbc; valaddr_reg:x8; val_offset:762*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 762*FLEN/8, x10, x3, x5) + +inst_277: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3fd and fs2 == 1 and fe2 == 0x11 and fm2 == 0x3be and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3bc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ffd; op2val:0xc7be; +op3val:0x3bbc; valaddr_reg:x8; val_offset:765*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 765*FLEN/8, x10, x3, x5) + +inst_278: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3fd and fs2 == 1 and fe2 == 0x11 and fm2 == 0x3be and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3bc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ffd; op2val:0xc7be; +op3val:0x3bbc; valaddr_reg:x8; val_offset:768*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 768*FLEN/8, x10, x3, x5) + +inst_279: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3fd and fs2 == 1 and fe2 == 0x11 and fm2 == 0x3be and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3bc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ffd; op2val:0xc7be; +op3val:0x3bbc; valaddr_reg:x8; val_offset:771*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 771*FLEN/8, x10, x3, x5) +RVTEST_SIGBASE(x3,signature_x3_2) + +inst_280: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x077 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2e6 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3b3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2877; op2val:0xc6e6; +op3val:0x33b3; valaddr_reg:x8; val_offset:774*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 774*FLEN/8, x10, x3, x5) + +inst_281: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x077 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2e6 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3b3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2877; op2val:0xc6e6; +op3val:0x33b3; valaddr_reg:x8; val_offset:777*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 777*FLEN/8, x10, x3, x5) + +inst_282: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x077 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2e6 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3b3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2877; op2val:0xc6e6; +op3val:0x33b3; valaddr_reg:x8; val_offset:780*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 780*FLEN/8, x10, x3, x5) + +inst_283: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x077 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2e6 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3b3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2877; op2val:0xc6e6; +op3val:0x33b3; valaddr_reg:x8; val_offset:783*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 783*FLEN/8, x10, x3, x5) + +inst_284: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x077 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2e6 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3b3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2877; op2val:0xc6e6; +op3val:0x33b3; valaddr_reg:x8; val_offset:786*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 786*FLEN/8, x10, x3, x5) + +inst_285: +// fs1 == 0 and fe1 == 0x08 and fm1 == 0x0ea and fs2 == 1 and fe2 == 0x14 and fm2 == 0x178 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x20ea; op2val:0xd178; +op3val:0x36b8; valaddr_reg:x8; val_offset:789*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 789*FLEN/8, x10, x3, x5) + +inst_286: +// fs1 == 0 and fe1 == 0x08 and fm1 == 0x0ea and fs2 == 1 and fe2 == 0x14 and fm2 == 0x178 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x20ea; op2val:0xd178; +op3val:0x36b8; valaddr_reg:x8; val_offset:792*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 792*FLEN/8, x10, x3, x5) + +inst_287: +// fs1 == 0 and fe1 == 0x08 and fm1 == 0x0ea and fs2 == 1 and fe2 == 0x14 and fm2 == 0x178 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x20ea; op2val:0xd178; +op3val:0x36b8; valaddr_reg:x8; val_offset:795*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 795*FLEN/8, x10, x3, x5) + +inst_288: +// fs1 == 0 and fe1 == 0x08 and fm1 == 0x0ea and fs2 == 1 and fe2 == 0x14 and fm2 == 0x178 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x20ea; op2val:0xd178; +op3val:0x36b8; valaddr_reg:x8; val_offset:798*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 798*FLEN/8, x10, x3, x5) + +inst_289: +// fs1 == 0 and fe1 == 0x08 and fm1 == 0x0ea and fs2 == 1 and fe2 == 0x14 and fm2 == 0x178 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x20ea; op2val:0xd178; +op3val:0x36b8; valaddr_reg:x8; val_offset:801*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 801*FLEN/8, x10, x3, x5) + +inst_290: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x293 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x0b5 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x3ba and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a93; op2val:0xa8b5; +op3val:0x27ba; valaddr_reg:x8; val_offset:804*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 804*FLEN/8, x10, x3, x5) + +inst_291: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x293 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x0b5 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x3ba and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a93; op2val:0xa8b5; +op3val:0x27ba; valaddr_reg:x8; val_offset:807*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 807*FLEN/8, x10, x3, x5) + +inst_292: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x293 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x0b5 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x3ba and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a93; op2val:0xa8b5; +op3val:0x27ba; valaddr_reg:x8; val_offset:810*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 810*FLEN/8, x10, x3, x5) + +inst_293: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x293 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x0b5 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x3ba and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a93; op2val:0xa8b5; +op3val:0x27ba; valaddr_reg:x8; val_offset:813*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 813*FLEN/8, x10, x3, x5) + +inst_294: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x293 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x0b5 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x3ba and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a93; op2val:0xa8b5; +op3val:0x27ba; valaddr_reg:x8; val_offset:816*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 816*FLEN/8, x10, x3, x5) + +inst_295: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x077 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x290 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x355 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3877; op2val:0xbe90; +op3val:0x3b55; valaddr_reg:x8; val_offset:819*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 819*FLEN/8, x10, x3, x5) + +inst_296: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x077 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x290 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x355 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3877; op2val:0xbe90; +op3val:0x3b55; valaddr_reg:x8; val_offset:822*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 822*FLEN/8, x10, x3, x5) + +inst_297: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x077 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x290 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x355 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3877; op2val:0xbe90; +op3val:0x3b55; valaddr_reg:x8; val_offset:825*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 825*FLEN/8, x10, x3, x5) + +inst_298: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x077 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x290 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x355 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3877; op2val:0xbe90; +op3val:0x3b55; valaddr_reg:x8; val_offset:828*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 828*FLEN/8, x10, x3, x5) + +inst_299: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x077 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x290 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x355 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3877; op2val:0xbe90; +op3val:0x3b55; valaddr_reg:x8; val_offset:831*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 831*FLEN/8, x10, x3, x5) + +inst_300: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x250 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x118 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x005 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3650; op2val:0xbd18; +op3val:0x3805; valaddr_reg:x8; val_offset:834*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 834*FLEN/8, x10, x3, x5) + +inst_301: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x250 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x118 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x005 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3650; op2val:0xbd18; +op3val:0x3805; valaddr_reg:x8; val_offset:837*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 837*FLEN/8, x10, x3, x5) + +inst_302: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x250 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x118 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x005 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3650; op2val:0xbd18; +op3val:0x3805; valaddr_reg:x8; val_offset:840*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 840*FLEN/8, x10, x3, x5) + +inst_303: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x250 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x118 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x005 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3650; op2val:0xbd18; +op3val:0x3805; valaddr_reg:x8; val_offset:843*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 843*FLEN/8, x10, x3, x5) + +inst_304: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x250 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x118 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x005 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3650; op2val:0xbd18; +op3val:0x3805; valaddr_reg:x8; val_offset:846*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 846*FLEN/8, x10, x3, x5) + +inst_305: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x036 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x26b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2c3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3836; op2val:0xbe6b; +op3val:0x3ac3; valaddr_reg:x8; val_offset:849*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 849*FLEN/8, x10, x3, x5) + +inst_306: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x036 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x26b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2c3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3836; op2val:0xbe6b; +op3val:0x3ac3; valaddr_reg:x8; val_offset:852*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 852*FLEN/8, x10, x3, x5) + +inst_307: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x036 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x26b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2c3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3836; op2val:0xbe6b; +op3val:0x3ac3; valaddr_reg:x8; val_offset:855*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 855*FLEN/8, x10, x3, x5) + +inst_308: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x036 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x26b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2c3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3836; op2val:0xbe6b; +op3val:0x3ac3; valaddr_reg:x8; val_offset:858*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 858*FLEN/8, x10, x3, x5) + +inst_309: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x036 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x26b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2c3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3836; op2val:0xbe6b; +op3val:0x3ac3; valaddr_reg:x8; val_offset:861*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 861*FLEN/8, x10, x3, x5) + +inst_310: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x306 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3a4 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b06; op2val:0xb7a4; +op3val:0x36b5; valaddr_reg:x8; val_offset:864*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 864*FLEN/8, x10, x3, x5) + +inst_311: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x306 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3a4 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b06; op2val:0xb7a4; +op3val:0x36b5; valaddr_reg:x8; val_offset:867*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 867*FLEN/8, x10, x3, x5) + +inst_312: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x306 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3a4 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b06; op2val:0xb7a4; +op3val:0x36b5; valaddr_reg:x8; val_offset:870*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 870*FLEN/8, x10, x3, x5) + +inst_313: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x306 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3a4 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b06; op2val:0xb7a4; +op3val:0x36b5; valaddr_reg:x8; val_offset:873*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 873*FLEN/8, x10, x3, x5) + +inst_314: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x306 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3a4 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b06; op2val:0xb7a4; +op3val:0x36b5; valaddr_reg:x8; val_offset:876*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 876*FLEN/8, x10, x3, x5) + +inst_315: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x060 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x262 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2fd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3860; op2val:0xbe62; +op3val:0x3afd; valaddr_reg:x8; val_offset:879*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 879*FLEN/8, x10, x3, x5) + +inst_316: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x060 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x262 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2fd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3860; op2val:0xbe62; +op3val:0x3afd; valaddr_reg:x8; val_offset:882*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 882*FLEN/8, x10, x3, x5) + +inst_317: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x060 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x262 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2fd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3860; op2val:0xbe62; +op3val:0x3afd; valaddr_reg:x8; val_offset:885*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 885*FLEN/8, x10, x3, x5) + +inst_318: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x060 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x262 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2fd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3860; op2val:0xbe62; +op3val:0x3afd; valaddr_reg:x8; val_offset:888*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 888*FLEN/8, x10, x3, x5) + +inst_319: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x060 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x262 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2fd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3860; op2val:0xbe62; +op3val:0x3afd; valaddr_reg:x8; val_offset:891*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 891*FLEN/8, x10, x3, x5) + +inst_320: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x07b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3d6 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x064 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x387b; op2val:0xb7d6; +op3val:0x3464; valaddr_reg:x8; val_offset:894*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 894*FLEN/8, x10, x3, x5) + +inst_321: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x07b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3d6 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x064 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x387b; op2val:0xb7d6; +op3val:0x3464; valaddr_reg:x8; val_offset:897*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 897*FLEN/8, x10, x3, x5) + +inst_322: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x07b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3d6 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x064 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x387b; op2val:0xb7d6; +op3val:0x3464; valaddr_reg:x8; val_offset:900*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 900*FLEN/8, x10, x3, x5) + +inst_323: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x07b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3d6 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x064 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x387b; op2val:0xb7d6; +op3val:0x3464; valaddr_reg:x8; val_offset:903*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 903*FLEN/8, x10, x3, x5) + +inst_324: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x07b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3d6 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x064 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x387b; op2val:0xb7d6; +op3val:0x3464; valaddr_reg:x8; val_offset:906*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 906*FLEN/8, x10, x3, x5) + +inst_325: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x08d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x36e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x03a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x348d; op2val:0xbf6e; +op3val:0x383a; valaddr_reg:x8; val_offset:909*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 909*FLEN/8, x10, x3, x5) + +inst_326: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x08d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x36e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x03a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x348d; op2val:0xbf6e; +op3val:0x383a; valaddr_reg:x8; val_offset:912*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 912*FLEN/8, x10, x3, x5) + +inst_327: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x08d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x36e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x03a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x348d; op2val:0xbf6e; +op3val:0x383a; valaddr_reg:x8; val_offset:915*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 915*FLEN/8, x10, x3, x5) + +inst_328: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x08d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x36e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x03a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x348d; op2val:0xbf6e; +op3val:0x383a; valaddr_reg:x8; val_offset:918*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 918*FLEN/8, x10, x3, x5) + +inst_329: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x08d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x36e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x03a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x348d; op2val:0xbf6e; +op3val:0x383a; valaddr_reg:x8; val_offset:921*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 921*FLEN/8, x10, x3, x5) + +inst_330: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d9 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x037 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x11d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38d9; op2val:0xbc37; +op3val:0x391d; valaddr_reg:x8; val_offset:924*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 924*FLEN/8, x10, x3, x5) + +inst_331: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d9 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x037 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x11d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38d9; op2val:0xbc37; +op3val:0x391d; valaddr_reg:x8; val_offset:927*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 927*FLEN/8, x10, x3, x5) + +inst_332: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d9 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x037 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x11d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38d9; op2val:0xbc37; +op3val:0x391d; valaddr_reg:x8; val_offset:930*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 930*FLEN/8, x10, x3, x5) + +inst_333: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d9 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x037 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x11d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38d9; op2val:0xbc37; +op3val:0x391d; valaddr_reg:x8; val_offset:933*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 933*FLEN/8, x10, x3, x5) + +inst_334: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d9 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x037 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x11d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38d9; op2val:0xbc37; +op3val:0x391d; valaddr_reg:x8; val_offset:936*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 936*FLEN/8, x10, x3, x5) + +inst_335: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x232 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x025 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x26b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a32; op2val:0xbc25; +op3val:0x3a6b; valaddr_reg:x8; val_offset:939*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 939*FLEN/8, x10, x3, x5) + +inst_336: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x232 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x025 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x26b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a32; op2val:0xbc25; +op3val:0x3a6b; valaddr_reg:x8; val_offset:942*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 942*FLEN/8, x10, x3, x5) + +inst_337: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x232 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x025 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x26b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a32; op2val:0xbc25; +op3val:0x3a6b; valaddr_reg:x8; val_offset:945*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 945*FLEN/8, x10, x3, x5) + +inst_338: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x232 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x025 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x26b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a32; op2val:0xbc25; +op3val:0x3a6b; valaddr_reg:x8; val_offset:948*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 948*FLEN/8, x10, x3, x5) + +inst_339: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x232 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x025 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x26b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a32; op2val:0xbc25; +op3val:0x3a6b; valaddr_reg:x8; val_offset:951*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 951*FLEN/8, x10, x3, x5) + +inst_340: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x06e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x271 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x322 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x386e; op2val:0xbe71; +op3val:0x3b22; valaddr_reg:x8; val_offset:954*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 954*FLEN/8, x10, x3, x5) + +inst_341: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x06e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x271 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x322 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x386e; op2val:0xbe71; +op3val:0x3b22; valaddr_reg:x8; val_offset:957*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 957*FLEN/8, x10, x3, x5) + +inst_342: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x06e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x271 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x322 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x386e; op2val:0xbe71; +op3val:0x3b22; valaddr_reg:x8; val_offset:960*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 960*FLEN/8, x10, x3, x5) + +inst_343: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x06e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x271 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x322 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x386e; op2val:0xbe71; +op3val:0x3b22; valaddr_reg:x8; val_offset:963*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 963*FLEN/8, x10, x3, x5) + +inst_344: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x06e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x271 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x322 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x386e; op2val:0xbe71; +op3val:0x3b22; valaddr_reg:x8; val_offset:966*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 966*FLEN/8, x10, x3, x5) + +inst_345: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x066 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x03e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3466; op2val:0xbc3e; +op3val:0x34aa; valaddr_reg:x8; val_offset:969*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 969*FLEN/8, x10, x3, x5) + +inst_346: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x066 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x03e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0aa and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3466; op2val:0xbc3e; +op3val:0x34aa; valaddr_reg:x8; val_offset:972*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 972*FLEN/8, x10, x3, x5) + +inst_347: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x066 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x03e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0aa and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3466; op2val:0xbc3e; +op3val:0x34aa; valaddr_reg:x8; val_offset:975*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 975*FLEN/8, x10, x3, x5) + +inst_348: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x066 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x03e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0aa and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3466; op2val:0xbc3e; +op3val:0x34aa; valaddr_reg:x8; val_offset:978*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 978*FLEN/8, x10, x3, x5) + +inst_349: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x066 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x03e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0aa and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3466; op2val:0xbc3e; +op3val:0x34aa; valaddr_reg:x8; val_offset:981*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 981*FLEN/8, x10, x3, x5) + +inst_350: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x237 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x108 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3d1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3637; op2val:0xc108; +op3val:0x3bd1; valaddr_reg:x8; val_offset:984*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 984*FLEN/8, x10, x3, x5) + +inst_351: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x237 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x108 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3d1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3637; op2val:0xc108; +op3val:0x3bd1; valaddr_reg:x8; val_offset:987*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 987*FLEN/8, x10, x3, x5) + +inst_352: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x237 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x108 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3d1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3637; op2val:0xc108; +op3val:0x3bd1; valaddr_reg:x8; val_offset:990*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 990*FLEN/8, x10, x3, x5) + +inst_353: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x237 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x108 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3d1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3637; op2val:0xc108; +op3val:0x3bd1; valaddr_reg:x8; val_offset:993*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 993*FLEN/8, x10, x3, x5) + +inst_354: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x237 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x108 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3d1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3637; op2val:0xc108; +op3val:0x3bd1; valaddr_reg:x8; val_offset:996*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 996*FLEN/8, x10, x3, x5) + +inst_355: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x116 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x324 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3916; op2val:0xbb24; +op3val:0x388a; valaddr_reg:x8; val_offset:999*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 999*FLEN/8, x10, x3, x5) + +inst_356: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x116 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x324 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3916; op2val:0xbb24; +op3val:0x388a; valaddr_reg:x8; val_offset:1002*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1002*FLEN/8, x10, x3, x5) + +inst_357: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x116 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x324 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3916; op2val:0xbb24; +op3val:0x388a; valaddr_reg:x8; val_offset:1005*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1005*FLEN/8, x10, x3, x5) + +inst_358: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x116 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x324 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3916; op2val:0xbb24; +op3val:0x388a; valaddr_reg:x8; val_offset:1008*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1008*FLEN/8, x10, x3, x5) + +inst_359: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x116 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x324 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3916; op2val:0xbb24; +op3val:0x388a; valaddr_reg:x8; val_offset:1011*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1011*FLEN/8, x10, x3, x5) + +inst_360: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x340 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x090 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x021 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b40; op2val:0xa890; +op3val:0x2821; valaddr_reg:x8; val_offset:1014*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1014*FLEN/8, x10, x3, x5) + +inst_361: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x340 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x090 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x021 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b40; op2val:0xa890; +op3val:0x2821; valaddr_reg:x8; val_offset:1017*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1017*FLEN/8, x10, x3, x5) + +inst_362: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x340 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x090 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x021 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b40; op2val:0xa890; +op3val:0x2821; valaddr_reg:x8; val_offset:1020*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1020*FLEN/8, x10, x3, x5) + +inst_363: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x340 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x090 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x021 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b40; op2val:0xa890; +op3val:0x2821; valaddr_reg:x8; val_offset:1023*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1023*FLEN/8, x10, x3, x5) + +inst_364: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x340 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x090 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x021 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b40; op2val:0xa890; +op3val:0x2821; valaddr_reg:x8; val_offset:1026*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1026*FLEN/8, x10, x3, x5) + +inst_365: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3d2 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x012 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3f5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x33d2; op2val:0xc012; +op3val:0x37f5; valaddr_reg:x8; val_offset:1029*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1029*FLEN/8, x10, x3, x5) + +inst_366: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3d2 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x012 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3f5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x33d2; op2val:0xc012; +op3val:0x37f5; valaddr_reg:x8; val_offset:1032*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1032*FLEN/8, x10, x3, x5) + +inst_367: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3d2 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x012 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3f5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x33d2; op2val:0xc012; +op3val:0x37f5; valaddr_reg:x8; val_offset:1035*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1035*FLEN/8, x10, x3, x5) + +inst_368: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3d2 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x012 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3f5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x33d2; op2val:0xc012; +op3val:0x37f5; valaddr_reg:x8; val_offset:1038*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1038*FLEN/8, x10, x3, x5) + +inst_369: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3d2 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x012 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3f5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x33d2; op2val:0xc012; +op3val:0x37f5; valaddr_reg:x8; val_offset:1041*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1041*FLEN/8, x10, x3, x5) + +inst_370: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0b7 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x16c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x265 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34b7; op2val:0xc16c; +op3val:0x3a65; valaddr_reg:x8; val_offset:1044*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1044*FLEN/8, x10, x3, x5) + +inst_371: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0b7 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x16c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x265 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34b7; op2val:0xc16c; +op3val:0x3a65; valaddr_reg:x8; val_offset:1047*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1047*FLEN/8, x10, x3, x5) + +inst_372: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0b7 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x16c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x265 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34b7; op2val:0xc16c; +op3val:0x3a65; valaddr_reg:x8; val_offset:1050*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1050*FLEN/8, x10, x3, x5) + +inst_373: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0b7 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x16c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x265 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34b7; op2val:0xc16c; +op3val:0x3a65; valaddr_reg:x8; val_offset:1053*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1053*FLEN/8, x10, x3, x5) + +inst_374: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0b7 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x16c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x265 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34b7; op2val:0xc16c; +op3val:0x3a65; valaddr_reg:x8; val_offset:1056*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1056*FLEN/8, x10, x3, x5) + +inst_375: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x22a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0ec and fs3 == 0 and fe3 == 0x0d and fm3 == 0x396 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a2a; op2val:0xb8ec; +op3val:0x3796; valaddr_reg:x8; val_offset:1059*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1059*FLEN/8, x10, x3, x5) + +inst_376: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x22a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0ec and fs3 == 0 and fe3 == 0x0d and fm3 == 0x396 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a2a; op2val:0xb8ec; +op3val:0x3796; valaddr_reg:x8; val_offset:1062*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1062*FLEN/8, x10, x3, x5) + +inst_377: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x22a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0ec and fs3 == 0 and fe3 == 0x0d and fm3 == 0x396 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a2a; op2val:0xb8ec; +op3val:0x3796; valaddr_reg:x8; val_offset:1065*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1065*FLEN/8, x10, x3, x5) + +inst_378: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x22a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0ec and fs3 == 0 and fe3 == 0x0d and fm3 == 0x396 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a2a; op2val:0xb8ec; +op3val:0x3796; valaddr_reg:x8; val_offset:1068*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1068*FLEN/8, x10, x3, x5) + +inst_379: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x22a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0ec and fs3 == 0 and fe3 == 0x0d and fm3 == 0x396 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a2a; op2val:0xb8ec; +op3val:0x3796; valaddr_reg:x8; val_offset:1071*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1071*FLEN/8, x10, x3, x5) + +inst_380: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x018 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x182 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1a4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3418; op2val:0xbd82; +op3val:0x35a4; valaddr_reg:x8; val_offset:1074*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1074*FLEN/8, x10, x3, x5) + +inst_381: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x018 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x182 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1a4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3418; op2val:0xbd82; +op3val:0x35a4; valaddr_reg:x8; val_offset:1077*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1077*FLEN/8, x10, x3, x5) + +inst_382: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x018 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x182 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1a4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3418; op2val:0xbd82; +op3val:0x35a4; valaddr_reg:x8; val_offset:1080*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1080*FLEN/8, x10, x3, x5) + +inst_383: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x018 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x182 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1a4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3418; op2val:0xbd82; +op3val:0x35a4; valaddr_reg:x8; val_offset:1083*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1083*FLEN/8, x10, x3, x5) + +inst_384: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x018 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x182 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1a4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3418; op2val:0xbd82; +op3val:0x35a4; valaddr_reg:x8; val_offset:1086*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1086*FLEN/8, x10, x3, x5) + +inst_385: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f2 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x23b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x230 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bf2; op2val:0xb63b; +op3val:0x3630; valaddr_reg:x8; val_offset:1089*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1089*FLEN/8, x10, x3, x5) + +inst_386: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f2 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x23b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x230 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bf2; op2val:0xb63b; +op3val:0x3630; valaddr_reg:x8; val_offset:1092*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1092*FLEN/8, x10, x3, x5) + +inst_387: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f2 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x23b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x230 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bf2; op2val:0xb63b; +op3val:0x3630; valaddr_reg:x8; val_offset:1095*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1095*FLEN/8, x10, x3, x5) + +inst_388: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f2 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x23b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x230 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bf2; op2val:0xb63b; +op3val:0x3630; valaddr_reg:x8; val_offset:1098*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1098*FLEN/8, x10, x3, x5) + +inst_389: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f2 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x23b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x230 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bf2; op2val:0xb63b; +op3val:0x3630; valaddr_reg:x8; val_offset:1101*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1101*FLEN/8, x10, x3, x5) + +inst_390: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1d6 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1a1 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x01b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2dd6; op2val:0xc1a1; +op3val:0x341b; valaddr_reg:x8; val_offset:1104*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1104*FLEN/8, x10, x3, x5) + +inst_391: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1d6 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1a1 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x01b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2dd6; op2val:0xc1a1; +op3val:0x341b; valaddr_reg:x8; val_offset:1107*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1107*FLEN/8, x10, x3, x5) + +inst_392: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1d6 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1a1 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x01b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2dd6; op2val:0xc1a1; +op3val:0x341b; valaddr_reg:x8; val_offset:1110*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1110*FLEN/8, x10, x3, x5) + +inst_393: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1d6 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1a1 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x01b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2dd6; op2val:0xc1a1; +op3val:0x341b; valaddr_reg:x8; val_offset:1113*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1113*FLEN/8, x10, x3, x5) + +inst_394: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1d6 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1a1 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x01b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2dd6; op2val:0xc1a1; +op3val:0x341b; valaddr_reg:x8; val_offset:1116*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1116*FLEN/8, x10, x3, x5) + +inst_395: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0a3 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x00f and fs3 == 0 and fe3 == 0x09 and fm3 == 0x0b1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ca3; op2val:0xb40f; +op3val:0x24b1; valaddr_reg:x8; val_offset:1119*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1119*FLEN/8, x10, x3, x5) + +inst_396: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0a3 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x00f and fs3 == 0 and fe3 == 0x09 and fm3 == 0x0b1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ca3; op2val:0xb40f; +op3val:0x24b1; valaddr_reg:x8; val_offset:1122*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1122*FLEN/8, x10, x3, x5) + +inst_397: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0a3 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x00f and fs3 == 0 and fe3 == 0x09 and fm3 == 0x0b1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ca3; op2val:0xb40f; +op3val:0x24b1; valaddr_reg:x8; val_offset:1125*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1125*FLEN/8, x10, x3, x5) + +inst_398: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0a3 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x00f and fs3 == 0 and fe3 == 0x09 and fm3 == 0x0b1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ca3; op2val:0xb40f; +op3val:0x24b1; valaddr_reg:x8; val_offset:1128*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1128*FLEN/8, x10, x3, x5) + +inst_399: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0a3 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x00f and fs3 == 0 and fe3 == 0x09 and fm3 == 0x0b1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ca3; op2val:0xb40f; +op3val:0x24b1; valaddr_reg:x8; val_offset:1131*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1131*FLEN/8, x10, x3, x5) + +inst_400: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x235 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x340 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a35; op2val:0xbb40; +op3val:0x39a0; valaddr_reg:x8; val_offset:1134*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1134*FLEN/8, x10, x3, x5) + +inst_401: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x235 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x340 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a35; op2val:0xbb40; +op3val:0x39a0; valaddr_reg:x8; val_offset:1137*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1137*FLEN/8, x10, x3, x5) + +inst_402: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x235 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x340 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a35; op2val:0xbb40; +op3val:0x39a0; valaddr_reg:x8; val_offset:1140*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1140*FLEN/8, x10, x3, x5) + +inst_403: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x235 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x340 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a35; op2val:0xbb40; +op3val:0x39a0; valaddr_reg:x8; val_offset:1143*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1143*FLEN/8, x10, x3, x5) + +inst_404: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x235 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x340 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a35; op2val:0xbb40; +op3val:0x39a0; valaddr_reg:x8; val_offset:1146*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1146*FLEN/8, x10, x3, x5) + +inst_405: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x33e and fs2 == 1 and fe2 == 0x0a and fm2 == 0x297 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x1f4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x373e; op2val:0xaa97; +op3val:0x25f4; valaddr_reg:x8; val_offset:1149*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1149*FLEN/8, x10, x3, x5) + +inst_406: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x33e and fs2 == 1 and fe2 == 0x0a and fm2 == 0x297 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x1f4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x373e; op2val:0xaa97; +op3val:0x25f4; valaddr_reg:x8; val_offset:1152*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1152*FLEN/8, x10, x3, x5) + +inst_407: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x33e and fs2 == 1 and fe2 == 0x0a and fm2 == 0x297 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x1f4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x373e; op2val:0xaa97; +op3val:0x25f4; valaddr_reg:x8; val_offset:1155*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1155*FLEN/8, x10, x3, x5) +RVTEST_SIGBASE(x3,signature_x3_3) + +inst_408: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x33e and fs2 == 1 and fe2 == 0x0a and fm2 == 0x297 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x1f4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x373e; op2val:0xaa97; +op3val:0x25f4; valaddr_reg:x8; val_offset:1158*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1158*FLEN/8, x10, x3, x5) + +inst_409: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x33e and fs2 == 1 and fe2 == 0x0a and fm2 == 0x297 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x1f4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x373e; op2val:0xaa97; +op3val:0x25f4; valaddr_reg:x8; val_offset:1161*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1161*FLEN/8, x10, x3, x5) + +inst_410: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x10b and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1f4 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x381 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x390b; op2val:0xadf4; +op3val:0x2b81; valaddr_reg:x8; val_offset:1164*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1164*FLEN/8, x10, x3, x5) + +inst_411: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x10b and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1f4 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x381 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x390b; op2val:0xadf4; +op3val:0x2b81; valaddr_reg:x8; val_offset:1167*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1167*FLEN/8, x10, x3, x5) + +inst_412: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x10b and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1f4 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x381 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x390b; op2val:0xadf4; +op3val:0x2b81; valaddr_reg:x8; val_offset:1170*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1170*FLEN/8, x10, x3, x5) + +inst_413: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x10b and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1f4 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x381 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x390b; op2val:0xadf4; +op3val:0x2b81; valaddr_reg:x8; val_offset:1173*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1173*FLEN/8, x10, x3, x5) + +inst_414: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x10b and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1f4 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x381 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x390b; op2val:0xadf4; +op3val:0x2b81; valaddr_reg:x8; val_offset:1176*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1176*FLEN/8, x10, x3, x5) + +inst_415: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0c9 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x278 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3bd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30c9; op2val:0xc278; +op3val:0x37bd; valaddr_reg:x8; val_offset:1179*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1179*FLEN/8, x10, x3, x5) + +inst_416: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0c9 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x278 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3bd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30c9; op2val:0xc278; +op3val:0x37bd; valaddr_reg:x8; val_offset:1182*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1182*FLEN/8, x10, x3, x5) + +inst_417: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0c9 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x278 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3bd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30c9; op2val:0xc278; +op3val:0x37bd; valaddr_reg:x8; val_offset:1185*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1185*FLEN/8, x10, x3, x5) + +inst_418: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0c9 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x278 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3bd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30c9; op2val:0xc278; +op3val:0x37bd; valaddr_reg:x8; val_offset:1188*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1188*FLEN/8, x10, x3, x5) + +inst_419: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0c9 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x278 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3bd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30c9; op2val:0xc278; +op3val:0x37bd; valaddr_reg:x8; val_offset:1191*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1191*FLEN/8, x10, x3, x5) + +inst_420: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x0b and fm2 == 0x358 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x180 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35ff; op2val:0xaf58; +op3val:0x2980; valaddr_reg:x8; val_offset:1194*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1194*FLEN/8, x10, x3, x5) + +inst_421: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x0b and fm2 == 0x358 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x180 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35ff; op2val:0xaf58; +op3val:0x2980; valaddr_reg:x8; val_offset:1197*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1197*FLEN/8, x10, x3, x5) + +inst_422: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x0b and fm2 == 0x358 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x180 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35ff; op2val:0xaf58; +op3val:0x2980; valaddr_reg:x8; val_offset:1200*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1200*FLEN/8, x10, x3, x5) + +inst_423: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x0b and fm2 == 0x358 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x180 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35ff; op2val:0xaf58; +op3val:0x2980; valaddr_reg:x8; val_offset:1203*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1203*FLEN/8, x10, x3, x5) + +inst_424: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x0b and fm2 == 0x358 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x180 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35ff; op2val:0xaf58; +op3val:0x2980; valaddr_reg:x8; val_offset:1206*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1206*FLEN/8, x10, x3, x5) + +inst_425: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x10 and fm2 == 0x27f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32ef; op2val:0xc27f; +op3val:0x39a2; valaddr_reg:x8; val_offset:1209*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1209*FLEN/8, x10, x3, x5) + +inst_426: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x10 and fm2 == 0x27f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32ef; op2val:0xc27f; +op3val:0x39a2; valaddr_reg:x8; val_offset:1212*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1212*FLEN/8, x10, x3, x5) + +inst_427: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x10 and fm2 == 0x27f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32ef; op2val:0xc27f; +op3val:0x39a2; valaddr_reg:x8; val_offset:1215*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1215*FLEN/8, x10, x3, x5) + +inst_428: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x10 and fm2 == 0x27f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32ef; op2val:0xc27f; +op3val:0x39a2; valaddr_reg:x8; val_offset:1218*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1218*FLEN/8, x10, x3, x5) + +inst_429: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x10 and fm2 == 0x27f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32ef; op2val:0xc27f; +op3val:0x39a2; valaddr_reg:x8; val_offset:1221*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1221*FLEN/8, x10, x3, x5) + +inst_430: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x136 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x26f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30f0; op2val:0xc536; +op3val:0x3a6f; valaddr_reg:x8; val_offset:1224*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1224*FLEN/8, x10, x3, x5) + +inst_431: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x136 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x26f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30f0; op2val:0xc536; +op3val:0x3a6f; valaddr_reg:x8; val_offset:1227*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1227*FLEN/8, x10, x3, x5) + +inst_432: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x136 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x26f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30f0; op2val:0xc536; +op3val:0x3a6f; valaddr_reg:x8; val_offset:1230*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1230*FLEN/8, x10, x3, x5) + +inst_433: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x136 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x26f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30f0; op2val:0xc536; +op3val:0x3a6f; valaddr_reg:x8; val_offset:1233*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1233*FLEN/8, x10, x3, x5) + +inst_434: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x136 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x26f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30f0; op2val:0xc536; +op3val:0x3a6f; valaddr_reg:x8; val_offset:1236*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1236*FLEN/8, x10, x3, x5) + +inst_435: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x10a and fs2 == 1 and fe2 == 0x0b and fm2 == 0x037 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x14e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x390a; op2val:0xac37; +op3val:0x294e; valaddr_reg:x8; val_offset:1239*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1239*FLEN/8, x10, x3, x5) + +inst_436: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x10a and fs2 == 1 and fe2 == 0x0b and fm2 == 0x037 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x14e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x390a; op2val:0xac37; +op3val:0x294e; valaddr_reg:x8; val_offset:1242*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1242*FLEN/8, x10, x3, x5) + +inst_437: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x10a and fs2 == 1 and fe2 == 0x0b and fm2 == 0x037 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x14e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x390a; op2val:0xac37; +op3val:0x294e; valaddr_reg:x8; val_offset:1245*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1245*FLEN/8, x10, x3, x5) + +inst_438: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x10a and fs2 == 1 and fe2 == 0x0b and fm2 == 0x037 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x14e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x390a; op2val:0xac37; +op3val:0x294e; valaddr_reg:x8; val_offset:1248*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1248*FLEN/8, x10, x3, x5) + +inst_439: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x10a and fs2 == 1 and fe2 == 0x0b and fm2 == 0x037 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x14e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x390a; op2val:0xac37; +op3val:0x294e; valaddr_reg:x8; val_offset:1251*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1251*FLEN/8, x10, x3, x5) + +inst_440: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0e5 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x07f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x181 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30e5; op2val:0xc47f; +op3val:0x3981; valaddr_reg:x8; val_offset:1254*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1254*FLEN/8, x10, x3, x5) + +inst_441: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0e5 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x07f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x181 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30e5; op2val:0xc47f; +op3val:0x3981; valaddr_reg:x8; val_offset:1257*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1257*FLEN/8, x10, x3, x5) + +inst_442: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0e5 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x07f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x181 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30e5; op2val:0xc47f; +op3val:0x3981; valaddr_reg:x8; val_offset:1260*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1260*FLEN/8, x10, x3, x5) + +inst_443: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0e5 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x07f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x181 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30e5; op2val:0xc47f; +op3val:0x3981; valaddr_reg:x8; val_offset:1263*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1263*FLEN/8, x10, x3, x5) + +inst_444: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0e5 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x07f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x181 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30e5; op2val:0xc47f; +op3val:0x3981; valaddr_reg:x8; val_offset:1266*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1266*FLEN/8, x10, x3, x5) + +inst_445: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ad and fs2 == 1 and fe2 == 0x0e and fm2 == 0x05d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x231 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39ad; op2val:0xb85d; +op3val:0x3631; valaddr_reg:x8; val_offset:1269*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1269*FLEN/8, x10, x3, x5) + +inst_446: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ad and fs2 == 1 and fe2 == 0x0e and fm2 == 0x05d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x231 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39ad; op2val:0xb85d; +op3val:0x3631; valaddr_reg:x8; val_offset:1272*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1272*FLEN/8, x10, x3, x5) + +inst_447: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ad and fs2 == 1 and fe2 == 0x0e and fm2 == 0x05d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x231 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39ad; op2val:0xb85d; +op3val:0x3631; valaddr_reg:x8; val_offset:1275*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1275*FLEN/8, x10, x3, x5) + +inst_448: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ad and fs2 == 1 and fe2 == 0x0e and fm2 == 0x05d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x231 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39ad; op2val:0xb85d; +op3val:0x3631; valaddr_reg:x8; val_offset:1278*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1278*FLEN/8, x10, x3, x5) + +inst_449: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ad and fs2 == 1 and fe2 == 0x0e and fm2 == 0x05d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x231 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39ad; op2val:0xb85d; +op3val:0x3631; valaddr_reg:x8; val_offset:1281*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1281*FLEN/8, x10, x3, x5) + +inst_450: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x109 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x003 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x10d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3109; op2val:0xc003; +op3val:0x350d; valaddr_reg:x8; val_offset:1284*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1284*FLEN/8, x10, x3, x5) + +inst_451: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x109 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x003 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x10d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3109; op2val:0xc003; +op3val:0x350d; valaddr_reg:x8; val_offset:1287*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1287*FLEN/8, x10, x3, x5) + +inst_452: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x109 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x003 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x10d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3109; op2val:0xc003; +op3val:0x350d; valaddr_reg:x8; val_offset:1290*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1290*FLEN/8, x10, x3, x5) + +inst_453: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x109 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x003 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x10d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3109; op2val:0xc003; +op3val:0x350d; valaddr_reg:x8; val_offset:1293*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1293*FLEN/8, x10, x3, x5) + +inst_454: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x109 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x003 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x10d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3109; op2val:0xc003; +op3val:0x350d; valaddr_reg:x8; val_offset:1296*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1296*FLEN/8, x10, x3, x5) + +inst_455: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x018 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x040 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x05a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2c18; op2val:0xc440; +op3val:0x345a; valaddr_reg:x8; val_offset:1299*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1299*FLEN/8, x10, x3, x5) + +inst_456: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x018 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x040 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x05a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2c18; op2val:0xc440; +op3val:0x345a; valaddr_reg:x8; val_offset:1302*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1302*FLEN/8, x10, x3, x5) + +inst_457: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x018 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x040 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x05a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2c18; op2val:0xc440; +op3val:0x345a; valaddr_reg:x8; val_offset:1305*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1305*FLEN/8, x10, x3, x5) + +inst_458: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x018 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x040 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x05a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2c18; op2val:0xc440; +op3val:0x345a; valaddr_reg:x8; val_offset:1308*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1308*FLEN/8, x10, x3, x5) + +inst_459: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x018 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x040 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x05a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2c18; op2val:0xc440; +op3val:0x345a; valaddr_reg:x8; val_offset:1311*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1311*FLEN/8, x10, x3, x5) + +inst_460: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1bb and fs2 == 1 and fe2 == 0x10 and fm2 == 0x069 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x252 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31bb; op2val:0xc069; +op3val:0x3652; valaddr_reg:x8; val_offset:1314*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1314*FLEN/8, x10, x3, x5) + +inst_461: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1bb and fs2 == 1 and fe2 == 0x10 and fm2 == 0x069 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x252 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31bb; op2val:0xc069; +op3val:0x3652; valaddr_reg:x8; val_offset:1317*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1317*FLEN/8, x10, x3, x5) + +inst_462: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1bb and fs2 == 1 and fe2 == 0x10 and fm2 == 0x069 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x252 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31bb; op2val:0xc069; +op3val:0x3652; valaddr_reg:x8; val_offset:1320*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1320*FLEN/8, x10, x3, x5) + +inst_463: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1bb and fs2 == 1 and fe2 == 0x10 and fm2 == 0x069 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x252 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31bb; op2val:0xc069; +op3val:0x3652; valaddr_reg:x8; val_offset:1323*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1323*FLEN/8, x10, x3, x5) + +inst_464: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1bb and fs2 == 1 and fe2 == 0x10 and fm2 == 0x069 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x252 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31bb; op2val:0xc069; +op3val:0x3652; valaddr_reg:x8; val_offset:1326*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1326*FLEN/8, x10, x3, x5) + +inst_465: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x32e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x094 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x391a; op2val:0xbb2e; +op3val:0x3894; valaddr_reg:x8; val_offset:1329*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1329*FLEN/8, x10, x3, x5) + +inst_466: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x32e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x094 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x391a; op2val:0xbb2e; +op3val:0x3894; valaddr_reg:x8; val_offset:1332*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1332*FLEN/8, x10, x3, x5) + +inst_467: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x32e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x094 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x391a; op2val:0xbb2e; +op3val:0x3894; valaddr_reg:x8; val_offset:1335*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1335*FLEN/8, x10, x3, x5) + +inst_468: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x32e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x094 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x391a; op2val:0xbb2e; +op3val:0x3894; valaddr_reg:x8; val_offset:1338*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1338*FLEN/8, x10, x3, x5) + +inst_469: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x32e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x094 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x391a; op2val:0xbb2e; +op3val:0x3894; valaddr_reg:x8; val_offset:1341*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1341*FLEN/8, x10, x3, x5) + +inst_470: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x014 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x363 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x389 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3814; op2val:0xbb63; +op3val:0x3789; valaddr_reg:x8; val_offset:1344*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1344*FLEN/8, x10, x3, x5) + +inst_471: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x014 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x363 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x389 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3814; op2val:0xbb63; +op3val:0x3789; valaddr_reg:x8; val_offset:1347*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1347*FLEN/8, x10, x3, x5) + +inst_472: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x014 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x363 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x389 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3814; op2val:0xbb63; +op3val:0x3789; valaddr_reg:x8; val_offset:1350*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1350*FLEN/8, x10, x3, x5) + +inst_473: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x014 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x363 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x389 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3814; op2val:0xbb63; +op3val:0x3789; valaddr_reg:x8; val_offset:1353*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1353*FLEN/8, x10, x3, x5) + +inst_474: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x014 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x363 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x389 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3814; op2val:0xbb63; +op3val:0x3789; valaddr_reg:x8; val_offset:1356*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1356*FLEN/8, x10, x3, x5) + +inst_475: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x12d and fs2 == 1 and fe2 == 0x11 and fm2 == 0x084 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1d9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x312d; op2val:0xc484; +op3val:0x39d9; valaddr_reg:x8; val_offset:1359*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1359*FLEN/8, x10, x3, x5) + +inst_476: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x12d and fs2 == 1 and fe2 == 0x11 and fm2 == 0x084 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1d9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x312d; op2val:0xc484; +op3val:0x39d9; valaddr_reg:x8; val_offset:1362*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1362*FLEN/8, x10, x3, x5) + +inst_477: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x12d and fs2 == 1 and fe2 == 0x11 and fm2 == 0x084 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1d9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x312d; op2val:0xc484; +op3val:0x39d9; valaddr_reg:x8; val_offset:1365*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1365*FLEN/8, x10, x3, x5) + +inst_478: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x12d and fs2 == 1 and fe2 == 0x11 and fm2 == 0x084 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1d9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x312d; op2val:0xc484; +op3val:0x39d9; valaddr_reg:x8; val_offset:1368*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1368*FLEN/8, x10, x3, x5) + +inst_479: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x12d and fs2 == 1 and fe2 == 0x11 and fm2 == 0x084 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1d9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x312d; op2val:0xc484; +op3val:0x39d9; valaddr_reg:x8; val_offset:1371*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1371*FLEN/8, x10, x3, x5) + +inst_480: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x373 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x095 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x045 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b73; op2val:0xb495; +op3val:0x3445; valaddr_reg:x8; val_offset:1374*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1374*FLEN/8, x10, x3, x5) + +inst_481: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x373 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x095 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x045 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b73; op2val:0xb495; +op3val:0x3445; valaddr_reg:x8; val_offset:1377*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1377*FLEN/8, x10, x3, x5) + +inst_482: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x373 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x095 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x045 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b73; op2val:0xb495; +op3val:0x3445; valaddr_reg:x8; val_offset:1380*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1380*FLEN/8, x10, x3, x5) + +inst_483: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x373 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x095 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x045 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b73; op2val:0xb495; +op3val:0x3445; valaddr_reg:x8; val_offset:1383*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1383*FLEN/8, x10, x3, x5) + +inst_484: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x373 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x095 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x045 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b73; op2val:0xb495; +op3val:0x3445; valaddr_reg:x8; val_offset:1386*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1386*FLEN/8, x10, x3, x5) + +inst_485: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1d5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x25e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0a4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39d5; op2val:0xba5e; +op3val:0x38a4; valaddr_reg:x8; val_offset:1389*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1389*FLEN/8, x10, x3, x5) + +inst_486: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1d5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x25e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0a4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39d5; op2val:0xba5e; +op3val:0x38a4; valaddr_reg:x8; val_offset:1392*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1392*FLEN/8, x10, x3, x5) + +inst_487: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1d5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x25e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0a4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39d5; op2val:0xba5e; +op3val:0x38a4; valaddr_reg:x8; val_offset:1395*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1395*FLEN/8, x10, x3, x5) + +inst_488: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1d5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x25e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0a4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39d5; op2val:0xba5e; +op3val:0x38a4; valaddr_reg:x8; val_offset:1398*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1398*FLEN/8, x10, x3, x5) + +inst_489: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1d5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x25e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0a4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39d5; op2val:0xba5e; +op3val:0x38a4; valaddr_reg:x8; val_offset:1401*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1401*FLEN/8, x10, x3, x5) + +inst_490: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x310 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x230 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x176 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b10; op2val:0xb230; +op3val:0x3176; valaddr_reg:x8; val_offset:1404*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1404*FLEN/8, x10, x3, x5) + +inst_491: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x310 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x230 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x176 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b10; op2val:0xb230; +op3val:0x3176; valaddr_reg:x8; val_offset:1407*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1407*FLEN/8, x10, x3, x5) + +inst_492: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x310 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x230 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x176 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b10; op2val:0xb230; +op3val:0x3176; valaddr_reg:x8; val_offset:1410*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1410*FLEN/8, x10, x3, x5) + +inst_493: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x310 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x230 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x176 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b10; op2val:0xb230; +op3val:0x3176; valaddr_reg:x8; val_offset:1413*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1413*FLEN/8, x10, x3, x5) + +inst_494: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x310 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x230 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x176 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b10; op2val:0xb230; +op3val:0x3176; valaddr_reg:x8; val_offset:1416*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1416*FLEN/8, x10, x3, x5) + +inst_495: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ce and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3ce and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39ce; op2val:0xbbce; +op3val:0x39aa; valaddr_reg:x8; val_offset:1419*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1419*FLEN/8, x10, x3, x5) + +inst_496: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ce and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3ce and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1aa and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39ce; op2val:0xbbce; +op3val:0x39aa; valaddr_reg:x8; val_offset:1422*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1422*FLEN/8, x10, x3, x5) + +inst_497: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ce and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3ce and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1aa and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39ce; op2val:0xbbce; +op3val:0x39aa; valaddr_reg:x8; val_offset:1425*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1425*FLEN/8, x10, x3, x5) + +inst_498: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ce and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3ce and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1aa and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39ce; op2val:0xbbce; +op3val:0x39aa; valaddr_reg:x8; val_offset:1428*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1428*FLEN/8, x10, x3, x5) + +inst_499: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ce and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3ce and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1aa and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39ce; op2val:0xbbce; +op3val:0x39aa; valaddr_reg:x8; val_offset:1431*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1431*FLEN/8, x10, x3, x5) + +inst_500: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x244 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x110 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3ee and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3244; op2val:0xc110; +op3val:0x37ee; valaddr_reg:x8; val_offset:1434*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1434*FLEN/8, x10, x3, x5) + +inst_501: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x244 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x110 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3ee and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3244; op2val:0xc110; +op3val:0x37ee; valaddr_reg:x8; val_offset:1437*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1437*FLEN/8, x10, x3, x5) + +inst_502: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x244 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x110 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3ee and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3244; op2val:0xc110; +op3val:0x37ee; valaddr_reg:x8; val_offset:1440*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1440*FLEN/8, x10, x3, x5) + +inst_503: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x244 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x110 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3ee and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3244; op2val:0xc110; +op3val:0x37ee; valaddr_reg:x8; val_offset:1443*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1443*FLEN/8, x10, x3, x5) + +inst_504: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x244 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x110 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3ee and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3244; op2val:0xc110; +op3val:0x37ee; valaddr_reg:x8; val_offset:1446*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1446*FLEN/8, x10, x3, x5) + +inst_505: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1c8 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0f1 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x325 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39c8; op2val:0xb0f1; +op3val:0x2f25; valaddr_reg:x8; val_offset:1449*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1449*FLEN/8, x10, x3, x5) + +inst_506: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1c8 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0f1 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x325 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39c8; op2val:0xb0f1; +op3val:0x2f25; valaddr_reg:x8; val_offset:1452*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1452*FLEN/8, x10, x3, x5) + +inst_507: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1c8 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0f1 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x325 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39c8; op2val:0xb0f1; +op3val:0x2f25; valaddr_reg:x8; val_offset:1455*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1455*FLEN/8, x10, x3, x5) + +inst_508: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1c8 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0f1 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x325 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39c8; op2val:0xb0f1; +op3val:0x2f25; valaddr_reg:x8; val_offset:1458*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1458*FLEN/8, x10, x3, x5) + +inst_509: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1c8 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0f1 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x325 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39c8; op2val:0xb0f1; +op3val:0x2f25; valaddr_reg:x8; val_offset:1461*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1461*FLEN/8, x10, x3, x5) + +inst_510: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0b4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x057 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x11b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38b4; op2val:0xbc57; +op3val:0x391b; valaddr_reg:x8; val_offset:1464*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1464*FLEN/8, x10, x3, x5) + +inst_511: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0b4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x057 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x11b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38b4; op2val:0xbc57; +op3val:0x391b; valaddr_reg:x8; val_offset:1467*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1467*FLEN/8, x10, x3, x5) + +inst_512: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0b4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x057 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x11b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38b4; op2val:0xbc57; +op3val:0x391b; valaddr_reg:x8; val_offset:1470*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1470*FLEN/8, x10, x3, x5) + +inst_513: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0b4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x057 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x11b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38b4; op2val:0xbc57; +op3val:0x391b; valaddr_reg:x8; val_offset:1473*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1473*FLEN/8, x10, x3, x5) + +inst_514: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0b4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x057 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x11b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38b4; op2val:0xbc57; +op3val:0x391b; valaddr_reg:x8; val_offset:1476*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1476*FLEN/8, x10, x3, x5) + +inst_515: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x06d and fs2 == 1 and fe2 == 0x11 and fm2 == 0x211 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2b7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x286d; op2val:0xc611; +op3val:0x32b7; valaddr_reg:x8; val_offset:1479*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1479*FLEN/8, x10, x3, x5) + +inst_516: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x06d and fs2 == 1 and fe2 == 0x11 and fm2 == 0x211 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2b7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x286d; op2val:0xc611; +op3val:0x32b7; valaddr_reg:x8; val_offset:1482*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1482*FLEN/8, x10, x3, x5) + +inst_517: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x06d and fs2 == 1 and fe2 == 0x11 and fm2 == 0x211 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2b7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x286d; op2val:0xc611; +op3val:0x32b7; valaddr_reg:x8; val_offset:1485*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1485*FLEN/8, x10, x3, x5) + +inst_518: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x06d and fs2 == 1 and fe2 == 0x11 and fm2 == 0x211 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2b7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x286d; op2val:0xc611; +op3val:0x32b7; valaddr_reg:x8; val_offset:1488*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1488*FLEN/8, x10, x3, x5) + +inst_519: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x06d and fs2 == 1 and fe2 == 0x11 and fm2 == 0x211 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2b7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x286d; op2val:0xc611; +op3val:0x32b7; valaddr_reg:x8; val_offset:1491*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1491*FLEN/8, x10, x3, x5) + +inst_520: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x00a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1f0 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x340a; op2val:0xc1f0; +op3val:0x3a00; valaddr_reg:x8; val_offset:1494*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1494*FLEN/8, x10, x3, x5) + +inst_521: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x00a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1f0 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x200 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x340a; op2val:0xc1f0; +op3val:0x3a00; valaddr_reg:x8; val_offset:1497*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1497*FLEN/8, x10, x3, x5) + +inst_522: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x00a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1f0 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x200 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x340a; op2val:0xc1f0; +op3val:0x3a00; valaddr_reg:x8; val_offset:1500*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1500*FLEN/8, x10, x3, x5) + +inst_523: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x00a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1f0 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x200 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x340a; op2val:0xc1f0; +op3val:0x3a00; valaddr_reg:x8; val_offset:1503*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1503*FLEN/8, x10, x3, x5) + +inst_524: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x00a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1f0 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x200 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x340a; op2val:0xc1f0; +op3val:0x3a00; valaddr_reg:x8; val_offset:1506*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1506*FLEN/8, x10, x3, x5) + +inst_525: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1f9 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x052 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x274 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31f9; op2val:0xc052; +op3val:0x3674; valaddr_reg:x8; val_offset:1509*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1509*FLEN/8, x10, x3, x5) + +inst_526: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1f9 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x052 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x274 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31f9; op2val:0xc052; +op3val:0x3674; valaddr_reg:x8; val_offset:1512*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1512*FLEN/8, x10, x3, x5) + +inst_527: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1f9 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x052 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x274 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31f9; op2val:0xc052; +op3val:0x3674; valaddr_reg:x8; val_offset:1515*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1515*FLEN/8, x10, x3, x5) + +inst_528: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1f9 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x052 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x274 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31f9; op2val:0xc052; +op3val:0x3674; valaddr_reg:x8; val_offset:1518*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1518*FLEN/8, x10, x3, x5) + +inst_529: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1f9 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x052 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x274 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31f9; op2val:0xc052; +op3val:0x3674; valaddr_reg:x8; val_offset:1521*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1521*FLEN/8, x10, x3, x5) + +inst_530: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x173 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x36c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x10e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3173; op2val:0xc36c; +op3val:0x390e; valaddr_reg:x8; val_offset:1524*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1524*FLEN/8, x10, x3, x5) + +inst_531: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x173 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x36c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x10e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3173; op2val:0xc36c; +op3val:0x390e; valaddr_reg:x8; val_offset:1527*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1527*FLEN/8, x10, x3, x5) + +inst_532: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x173 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x36c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x10e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3173; op2val:0xc36c; +op3val:0x390e; valaddr_reg:x8; val_offset:1530*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1530*FLEN/8, x10, x3, x5) + +inst_533: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x173 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x36c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x10e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3173; op2val:0xc36c; +op3val:0x390e; valaddr_reg:x8; val_offset:1533*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1533*FLEN/8, x10, x3, x5) + +inst_534: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x173 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x36c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x10e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3173; op2val:0xc36c; +op3val:0x390e; valaddr_reg:x8; val_offset:1536*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1536*FLEN/8, x10, x3, x5) + +inst_535: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x304 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x38a and fs3 == 0 and fe3 == 0x0c and fm3 == 0x29c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3304; op2val:0xbb8a; +op3val:0x329c; valaddr_reg:x8; val_offset:1539*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1539*FLEN/8, x10, x3, x5) +RVTEST_SIGBASE(x3,signature_x3_4) + +inst_536: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x304 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x38a and fs3 == 0 and fe3 == 0x0c and fm3 == 0x29c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3304; op2val:0xbb8a; +op3val:0x329c; valaddr_reg:x8; val_offset:1542*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1542*FLEN/8, x10, x3, x5) + +inst_537: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x304 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x38a and fs3 == 0 and fe3 == 0x0c and fm3 == 0x29c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3304; op2val:0xbb8a; +op3val:0x329c; valaddr_reg:x8; val_offset:1545*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1545*FLEN/8, x10, x3, x5) + +inst_538: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x304 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x38a and fs3 == 0 and fe3 == 0x0c and fm3 == 0x29c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3304; op2val:0xbb8a; +op3val:0x329c; valaddr_reg:x8; val_offset:1548*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1548*FLEN/8, x10, x3, x5) + +inst_539: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x304 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x38a and fs3 == 0 and fe3 == 0x0c and fm3 == 0x29c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3304; op2val:0xbb8a; +op3val:0x329c; valaddr_reg:x8; val_offset:1551*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1551*FLEN/8, x10, x3, x5) + +inst_540: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x083 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x186 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38e5; op2val:0xb883; +op3val:0x3586; valaddr_reg:x8; val_offset:1554*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1554*FLEN/8, x10, x3, x5) + +inst_541: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x083 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x186 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38e5; op2val:0xb883; +op3val:0x3586; valaddr_reg:x8; val_offset:1557*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1557*FLEN/8, x10, x3, x5) + +inst_542: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x083 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x186 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38e5; op2val:0xb883; +op3val:0x3586; valaddr_reg:x8; val_offset:1560*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1560*FLEN/8, x10, x3, x5) + +inst_543: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x083 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x186 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38e5; op2val:0xb883; +op3val:0x3586; valaddr_reg:x8; val_offset:1563*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1563*FLEN/8, x10, x3, x5) + +inst_544: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x083 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x186 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38e5; op2val:0xb883; +op3val:0x3586; valaddr_reg:x8; val_offset:1566*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1566*FLEN/8, x10, x3, x5) + +inst_545: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x308 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x013 and fs3 == 0 and fe3 == 0x07 and fm3 == 0x31f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3308; op2val:0xa813; +op3val:0x1f1f; valaddr_reg:x8; val_offset:1569*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1569*FLEN/8, x10, x3, x5) + +inst_546: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x308 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x013 and fs3 == 0 and fe3 == 0x07 and fm3 == 0x31f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3308; op2val:0xa813; +op3val:0x1f1f; valaddr_reg:x8; val_offset:1572*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1572*FLEN/8, x10, x3, x5) + +inst_547: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x308 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x013 and fs3 == 0 and fe3 == 0x07 and fm3 == 0x31f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3308; op2val:0xa813; +op3val:0x1f1f; valaddr_reg:x8; val_offset:1575*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1575*FLEN/8, x10, x3, x5) + +inst_548: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x308 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x013 and fs3 == 0 and fe3 == 0x07 and fm3 == 0x31f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3308; op2val:0xa813; +op3val:0x1f1f; valaddr_reg:x8; val_offset:1578*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1578*FLEN/8, x10, x3, x5) + +inst_549: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x308 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x013 and fs3 == 0 and fe3 == 0x07 and fm3 == 0x31f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3308; op2val:0xa813; +op3val:0x1f1f; valaddr_reg:x8; val_offset:1581*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1581*FLEN/8, x10, x3, x5) + +inst_550: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x117 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x15f and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2d7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2d17; op2val:0xc15f; +op3val:0x32d7; valaddr_reg:x8; val_offset:1584*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1584*FLEN/8, x10, x3, x5) + +inst_551: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x117 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x15f and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2d7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2d17; op2val:0xc15f; +op3val:0x32d7; valaddr_reg:x8; val_offset:1587*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1587*FLEN/8, x10, x3, x5) + +inst_552: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x117 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x15f and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2d7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2d17; op2val:0xc15f; +op3val:0x32d7; valaddr_reg:x8; val_offset:1590*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1590*FLEN/8, x10, x3, x5) + +inst_553: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x117 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x15f and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2d7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2d17; op2val:0xc15f; +op3val:0x32d7; valaddr_reg:x8; val_offset:1593*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1593*FLEN/8, x10, x3, x5) + +inst_554: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x117 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x15f and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2d7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2d17; op2val:0xc15f; +op3val:0x32d7; valaddr_reg:x8; val_offset:1596*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1596*FLEN/8, x10, x3, x5) + +inst_555: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2e7 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x339 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x23c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ae7; op2val:0xb739; +op3val:0x363c; valaddr_reg:x8; val_offset:1599*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1599*FLEN/8, x10, x3, x5) + +inst_556: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2e7 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x339 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x23c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ae7; op2val:0xb739; +op3val:0x363c; valaddr_reg:x8; val_offset:1602*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1602*FLEN/8, x10, x3, x5) + +inst_557: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2e7 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x339 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x23c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ae7; op2val:0xb739; +op3val:0x363c; valaddr_reg:x8; val_offset:1605*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1605*FLEN/8, x10, x3, x5) + +inst_558: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2e7 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x339 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x23c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ae7; op2val:0xb739; +op3val:0x363c; valaddr_reg:x8; val_offset:1608*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1608*FLEN/8, x10, x3, x5) + +inst_559: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2e7 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x339 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x23c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ae7; op2val:0xb739; +op3val:0x363c; valaddr_reg:x8; val_offset:1611*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1611*FLEN/8, x10, x3, x5) + +inst_560: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x10a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1cc and fs3 == 0 and fe3 == 0x0e and fm3 == 0x34d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x350a; op2val:0xc1cc; +op3val:0x3b4d; valaddr_reg:x8; val_offset:1614*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1614*FLEN/8, x10, x3, x5) + +inst_561: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x10a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1cc and fs3 == 0 and fe3 == 0x0e and fm3 == 0x34d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x350a; op2val:0xc1cc; +op3val:0x3b4d; valaddr_reg:x8; val_offset:1617*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1617*FLEN/8, x10, x3, x5) + +inst_562: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x10a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1cc and fs3 == 0 and fe3 == 0x0e and fm3 == 0x34d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x350a; op2val:0xc1cc; +op3val:0x3b4d; valaddr_reg:x8; val_offset:1620*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1620*FLEN/8, x10, x3, x5) + +inst_563: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x10a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1cc and fs3 == 0 and fe3 == 0x0e and fm3 == 0x34d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x350a; op2val:0xc1cc; +op3val:0x3b4d; valaddr_reg:x8; val_offset:1623*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1623*FLEN/8, x10, x3, x5) + +inst_564: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x10a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1cc and fs3 == 0 and fe3 == 0x0e and fm3 == 0x34d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x350a; op2val:0xc1cc; +op3val:0x3b4d; valaddr_reg:x8; val_offset:1626*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1626*FLEN/8, x10, x3, x5) + +inst_565: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x04c and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3d2 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x033 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x384c; op2val:0xb3d2; +op3val:0x3033; valaddr_reg:x8; val_offset:1629*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1629*FLEN/8, x10, x3, x5) + +inst_566: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x04c and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3d2 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x033 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x384c; op2val:0xb3d2; +op3val:0x3033; valaddr_reg:x8; val_offset:1632*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1632*FLEN/8, x10, x3, x5) + +inst_567: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x04c and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3d2 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x033 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x384c; op2val:0xb3d2; +op3val:0x3033; valaddr_reg:x8; val_offset:1635*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1635*FLEN/8, x10, x3, x5) + +inst_568: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x04c and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3d2 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x033 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x384c; op2val:0xb3d2; +op3val:0x3033; valaddr_reg:x8; val_offset:1638*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1638*FLEN/8, x10, x3, x5) + +inst_569: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x04c and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3d2 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x033 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x384c; op2val:0xb3d2; +op3val:0x3033; valaddr_reg:x8; val_offset:1641*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1641*FLEN/8, x10, x3, x5) + +inst_570: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x20e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x252 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0c8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e0e; op2val:0xba52; +op3val:0x2cc8; valaddr_reg:x8; val_offset:1644*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1644*FLEN/8, x10, x3, x5) + +inst_571: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x20e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x252 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0c8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e0e; op2val:0xba52; +op3val:0x2cc8; valaddr_reg:x8; val_offset:1647*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1647*FLEN/8, x10, x3, x5) + +inst_572: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x20e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x252 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0c8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e0e; op2val:0xba52; +op3val:0x2cc8; valaddr_reg:x8; val_offset:1650*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1650*FLEN/8, x10, x3, x5) + +inst_573: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x20e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x252 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0c8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e0e; op2val:0xba52; +op3val:0x2cc8; valaddr_reg:x8; val_offset:1653*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1653*FLEN/8, x10, x3, x5) + +inst_574: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x20e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x252 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0c8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e0e; op2val:0xba52; +op3val:0x2cc8; valaddr_reg:x8; val_offset:1656*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1656*FLEN/8, x10, x3, x5) + +inst_575: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x342 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2ee and fs3 == 0 and fe3 == 0x0d and fm3 == 0x249 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b42; op2val:0xb6ee; +op3val:0x3649; valaddr_reg:x8; val_offset:1659*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1659*FLEN/8, x10, x3, x5) + +inst_576: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x342 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2ee and fs3 == 0 and fe3 == 0x0d and fm3 == 0x249 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b42; op2val:0xb6ee; +op3val:0x3649; valaddr_reg:x8; val_offset:1662*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1662*FLEN/8, x10, x3, x5) + +inst_577: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x342 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2ee and fs3 == 0 and fe3 == 0x0d and fm3 == 0x249 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b42; op2val:0xb6ee; +op3val:0x3649; valaddr_reg:x8; val_offset:1665*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1665*FLEN/8, x10, x3, x5) + +inst_578: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x342 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2ee and fs3 == 0 and fe3 == 0x0d and fm3 == 0x249 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b42; op2val:0xb6ee; +op3val:0x3649; valaddr_reg:x8; val_offset:1668*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1668*FLEN/8, x10, x3, x5) + +inst_579: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x342 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2ee and fs3 == 0 and fe3 == 0x0d and fm3 == 0x249 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b42; op2val:0xb6ee; +op3val:0x3649; valaddr_reg:x8; val_offset:1671*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1671*FLEN/8, x10, x3, x5) + +inst_580: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x052 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x125 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x18e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3052; op2val:0xc125; +op3val:0x358e; valaddr_reg:x8; val_offset:1674*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1674*FLEN/8, x10, x3, x5) + +inst_581: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x052 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x125 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x18e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3052; op2val:0xc125; +op3val:0x358e; valaddr_reg:x8; val_offset:1677*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1677*FLEN/8, x10, x3, x5) + +inst_582: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x052 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x125 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x18e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3052; op2val:0xc125; +op3val:0x358e; valaddr_reg:x8; val_offset:1680*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1680*FLEN/8, x10, x3, x5) + +inst_583: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x052 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x125 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x18e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3052; op2val:0xc125; +op3val:0x358e; valaddr_reg:x8; val_offset:1683*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1683*FLEN/8, x10, x3, x5) + +inst_584: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x052 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x125 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x18e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3052; op2val:0xc125; +op3val:0x358e; valaddr_reg:x8; val_offset:1686*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1686*FLEN/8, x10, x3, x5) + +inst_585: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x170 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1a7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3b0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3970; op2val:0xbda7; +op3val:0x3bb0; valaddr_reg:x8; val_offset:1689*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1689*FLEN/8, x10, x3, x5) + +inst_586: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x170 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1a7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3b0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3970; op2val:0xbda7; +op3val:0x3bb0; valaddr_reg:x8; val_offset:1692*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1692*FLEN/8, x10, x3, x5) + +inst_587: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x170 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1a7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3b0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3970; op2val:0xbda7; +op3val:0x3bb0; valaddr_reg:x8; val_offset:1695*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1695*FLEN/8, x10, x3, x5) + +inst_588: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x170 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1a7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3b0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3970; op2val:0xbda7; +op3val:0x3bb0; valaddr_reg:x8; val_offset:1698*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1698*FLEN/8, x10, x3, x5) + +inst_589: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x170 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1a7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3b0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3970; op2val:0xbda7; +op3val:0x3bb0; valaddr_reg:x8; val_offset:1701*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1701*FLEN/8, x10, x3, x5) + +inst_590: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x122 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x307 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x082 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2d22; op2val:0xbf07; +op3val:0x3082; valaddr_reg:x8; val_offset:1704*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1704*FLEN/8, x10, x3, x5) + +inst_591: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x122 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x307 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x082 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2d22; op2val:0xbf07; +op3val:0x3082; valaddr_reg:x8; val_offset:1707*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1707*FLEN/8, x10, x3, x5) + +inst_592: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x122 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x307 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x082 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2d22; op2val:0xbf07; +op3val:0x3082; valaddr_reg:x8; val_offset:1710*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1710*FLEN/8, x10, x3, x5) + +inst_593: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x122 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x307 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x082 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2d22; op2val:0xbf07; +op3val:0x3082; valaddr_reg:x8; val_offset:1713*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1713*FLEN/8, x10, x3, x5) + +inst_594: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x122 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x307 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x082 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2d22; op2val:0xbf07; +op3val:0x3082; valaddr_reg:x8; val_offset:1716*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1716*FLEN/8, x10, x3, x5) + +inst_595: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x18a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x351 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x111 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x358a; op2val:0xbf51; +op3val:0x3911; valaddr_reg:x8; val_offset:1719*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1719*FLEN/8, x10, x3, x5) + +inst_596: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x18a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x351 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x111 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x358a; op2val:0xbf51; +op3val:0x3911; valaddr_reg:x8; val_offset:1722*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1722*FLEN/8, x10, x3, x5) + +inst_597: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x18a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x351 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x111 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x358a; op2val:0xbf51; +op3val:0x3911; valaddr_reg:x8; val_offset:1725*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1725*FLEN/8, x10, x3, x5) + +inst_598: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x18a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x351 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x111 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x358a; op2val:0xbf51; +op3val:0x3911; valaddr_reg:x8; val_offset:1728*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1728*FLEN/8, x10, x3, x5) + +inst_599: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x18a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x351 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x111 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x358a; op2val:0xbf51; +op3val:0x3911; valaddr_reg:x8; val_offset:1731*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1731*FLEN/8, x10, x3, x5) + +inst_600: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x17d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x051 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1ed and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x317d; op2val:0xbc51; +op3val:0x31ed; valaddr_reg:x8; val_offset:1734*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1734*FLEN/8, x10, x3, x5) + +inst_601: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x17d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x051 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1ed and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x317d; op2val:0xbc51; +op3val:0x31ed; valaddr_reg:x8; val_offset:1737*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1737*FLEN/8, x10, x3, x5) + +inst_602: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x17d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x051 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1ed and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x317d; op2val:0xbc51; +op3val:0x31ed; valaddr_reg:x8; val_offset:1740*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1740*FLEN/8, x10, x3, x5) + +inst_603: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x17d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x051 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1ed and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x317d; op2val:0xbc51; +op3val:0x31ed; valaddr_reg:x8; val_offset:1743*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1743*FLEN/8, x10, x3, x5) + +inst_604: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x17d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x051 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1ed and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x317d; op2val:0xbc51; +op3val:0x31ed; valaddr_reg:x8; val_offset:1746*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1746*FLEN/8, x10, x3, x5) + +inst_605: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x067 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1d0 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x267 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3467; op2val:0xbdd0; +op3val:0x3667; valaddr_reg:x8; val_offset:1749*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1749*FLEN/8, x10, x3, x5) + +inst_606: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x067 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1d0 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x267 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3467; op2val:0xbdd0; +op3val:0x3667; valaddr_reg:x8; val_offset:1752*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1752*FLEN/8, x10, x3, x5) + +inst_607: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x067 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1d0 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x267 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3467; op2val:0xbdd0; +op3val:0x3667; valaddr_reg:x8; val_offset:1755*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1755*FLEN/8, x10, x3, x5) + +inst_608: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x067 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1d0 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x267 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3467; op2val:0xbdd0; +op3val:0x3667; valaddr_reg:x8; val_offset:1758*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1758*FLEN/8, x10, x3, x5) + +inst_609: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x067 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1d0 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x267 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3467; op2val:0xbdd0; +op3val:0x3667; valaddr_reg:x8; val_offset:1761*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1761*FLEN/8, x10, x3, x5) + +inst_610: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x172 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x022 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3972; op2val:0xbc22; +op3val:0x39a0; valaddr_reg:x8; val_offset:1764*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1764*FLEN/8, x10, x3, x5) + +inst_611: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x172 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x022 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3972; op2val:0xbc22; +op3val:0x39a0; valaddr_reg:x8; val_offset:1767*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1767*FLEN/8, x10, x3, x5) + +inst_612: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x172 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x022 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3972; op2val:0xbc22; +op3val:0x39a0; valaddr_reg:x8; val_offset:1770*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1770*FLEN/8, x10, x3, x5) + +inst_613: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x172 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x022 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3972; op2val:0xbc22; +op3val:0x39a0; valaddr_reg:x8; val_offset:1773*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1773*FLEN/8, x10, x3, x5) + +inst_614: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x172 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x022 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3972; op2val:0xbc22; +op3val:0x39a0; valaddr_reg:x8; val_offset:1776*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1776*FLEN/8, x10, x3, x5) + +inst_615: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x123 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x030 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x162 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3923; op2val:0xbc30; +op3val:0x3962; valaddr_reg:x8; val_offset:1779*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1779*FLEN/8, x10, x3, x5) + +inst_616: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x123 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x030 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x162 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3923; op2val:0xbc30; +op3val:0x3962; valaddr_reg:x8; val_offset:1782*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1782*FLEN/8, x10, x3, x5) + +inst_617: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x123 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x030 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x162 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3923; op2val:0xbc30; +op3val:0x3962; valaddr_reg:x8; val_offset:1785*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1785*FLEN/8, x10, x3, x5) + +inst_618: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x123 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x030 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x162 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3923; op2val:0xbc30; +op3val:0x3962; valaddr_reg:x8; val_offset:1788*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1788*FLEN/8, x10, x3, x5) + +inst_619: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x123 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x030 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x162 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3923; op2val:0xbc30; +op3val:0x3962; valaddr_reg:x8; val_offset:1791*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1791*FLEN/8, x10, x3, x5) + +inst_620: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ad and fs2 == 1 and fe2 == 0x0f and fm2 == 0x362 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x316 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37ad; op2val:0xbf62; +op3val:0x3b16; valaddr_reg:x8; val_offset:1794*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1794*FLEN/8, x10, x3, x5) + +inst_621: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ad and fs2 == 1 and fe2 == 0x0f and fm2 == 0x362 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x316 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37ad; op2val:0xbf62; +op3val:0x3b16; valaddr_reg:x8; val_offset:1797*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1797*FLEN/8, x10, x3, x5) + +inst_622: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ad and fs2 == 1 and fe2 == 0x0f and fm2 == 0x362 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x316 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37ad; op2val:0xbf62; +op3val:0x3b16; valaddr_reg:x8; val_offset:1800*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1800*FLEN/8, x10, x3, x5) + +inst_623: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ad and fs2 == 1 and fe2 == 0x0f and fm2 == 0x362 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x316 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37ad; op2val:0xbf62; +op3val:0x3b16; valaddr_reg:x8; val_offset:1803*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1803*FLEN/8, x10, x3, x5) + +inst_624: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ad and fs2 == 1 and fe2 == 0x0f and fm2 == 0x362 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x316 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37ad; op2val:0xbf62; +op3val:0x3b16; valaddr_reg:x8; val_offset:1806*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1806*FLEN/8, x10, x3, x5) + +inst_625: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x075 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ae and fs3 == 0 and fe3 == 0x0e and fm3 == 0x137 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3475; op2val:0xc0ae; +op3val:0x3937; valaddr_reg:x8; val_offset:1809*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1809*FLEN/8, x10, x3, x5) + +inst_626: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x075 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ae and fs3 == 0 and fe3 == 0x0e and fm3 == 0x137 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3475; op2val:0xc0ae; +op3val:0x3937; valaddr_reg:x8; val_offset:1812*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1812*FLEN/8, x10, x3, x5) + +inst_627: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x075 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ae and fs3 == 0 and fe3 == 0x0e and fm3 == 0x137 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3475; op2val:0xc0ae; +op3val:0x3937; valaddr_reg:x8; val_offset:1815*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1815*FLEN/8, x10, x3, x5) + +inst_628: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x075 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ae and fs3 == 0 and fe3 == 0x0e and fm3 == 0x137 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3475; op2val:0xc0ae; +op3val:0x3937; valaddr_reg:x8; val_offset:1818*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1818*FLEN/8, x10, x3, x5) + +inst_629: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x075 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ae and fs3 == 0 and fe3 == 0x0e and fm3 == 0x137 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3475; op2val:0xc0ae; +op3val:0x3937; valaddr_reg:x8; val_offset:1821*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1821*FLEN/8, x10, x3, x5) + +inst_630: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x318 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1f5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ab8; op2val:0xbb18; +op3val:0x39f5; valaddr_reg:x8; val_offset:1824*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1824*FLEN/8, x10, x3, x5) + +inst_631: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x318 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1f5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ab8; op2val:0xbb18; +op3val:0x39f5; valaddr_reg:x8; val_offset:1827*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1827*FLEN/8, x10, x3, x5) + +inst_632: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x318 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1f5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ab8; op2val:0xbb18; +op3val:0x39f5; valaddr_reg:x8; val_offset:1830*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1830*FLEN/8, x10, x3, x5) + +inst_633: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x318 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1f5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ab8; op2val:0xbb18; +op3val:0x39f5; valaddr_reg:x8; val_offset:1833*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1833*FLEN/8, x10, x3, x5) + +inst_634: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x318 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1f5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ab8; op2val:0xbb18; +op3val:0x39f5; valaddr_reg:x8; val_offset:1836*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1836*FLEN/8, x10, x3, x5) + +inst_635: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e2 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x373 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38e2; op2val:0xbb73; +op3val:0x388c; valaddr_reg:x8; val_offset:1839*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1839*FLEN/8, x10, x3, x5) + +inst_636: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e2 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x373 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38e2; op2val:0xbb73; +op3val:0x388c; valaddr_reg:x8; val_offset:1842*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1842*FLEN/8, x10, x3, x5) + +inst_637: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e2 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x373 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38e2; op2val:0xbb73; +op3val:0x388c; valaddr_reg:x8; val_offset:1845*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1845*FLEN/8, x10, x3, x5) + +inst_638: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e2 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x373 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38e2; op2val:0xbb73; +op3val:0x388c; valaddr_reg:x8; val_offset:1848*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1848*FLEN/8, x10, x3, x5) + +inst_639: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e2 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x373 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38e2; op2val:0xbb73; +op3val:0x388c; valaddr_reg:x8; val_offset:1851*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1851*FLEN/8, x10, x3, x5) + +inst_640: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2f8 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x021 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x333 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32f8; op2val:0xc421; +op3val:0x3b33; valaddr_reg:x8; val_offset:1854*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1854*FLEN/8, x10, x3, x5) + +inst_641: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2f8 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x021 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x333 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32f8; op2val:0xc421; +op3val:0x3b33; valaddr_reg:x8; val_offset:1857*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1857*FLEN/8, x10, x3, x5) + +inst_642: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2f8 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x021 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x333 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32f8; op2val:0xc421; +op3val:0x3b33; valaddr_reg:x8; val_offset:1860*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1860*FLEN/8, x10, x3, x5) + +inst_643: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2f8 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x021 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x333 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32f8; op2val:0xc421; +op3val:0x3b33; valaddr_reg:x8; val_offset:1863*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1863*FLEN/8, x10, x3, x5) + +inst_644: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2f8 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x021 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x333 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32f8; op2val:0xc421; +op3val:0x3b33; valaddr_reg:x8; val_offset:1866*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1866*FLEN/8, x10, x3, x5) + +inst_645: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x238 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x346 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a38; op2val:0xbb46; +op3val:0x39a7; valaddr_reg:x8; val_offset:1869*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1869*FLEN/8, x10, x3, x5) + +inst_646: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x238 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x346 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a38; op2val:0xbb46; +op3val:0x39a7; valaddr_reg:x8; val_offset:1872*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1872*FLEN/8, x10, x3, x5) + +inst_647: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x238 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x346 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a38; op2val:0xbb46; +op3val:0x39a7; valaddr_reg:x8; val_offset:1875*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1875*FLEN/8, x10, x3, x5) + +inst_648: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x238 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x346 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a38; op2val:0xbb46; +op3val:0x39a7; valaddr_reg:x8; val_offset:1878*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1878*FLEN/8, x10, x3, x5) + +inst_649: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x238 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x346 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a38; op2val:0xbb46; +op3val:0x39a7; valaddr_reg:x8; val_offset:1881*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1881*FLEN/8, x10, x3, x5) + +inst_650: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x296 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0df and fs3 == 0 and fe3 == 0x0d and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a96; op2val:0xb4df; +op3val:0x3402; valaddr_reg:x8; val_offset:1884*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1884*FLEN/8, x10, x3, x5) + +inst_651: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x296 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0df and fs3 == 0 and fe3 == 0x0d and fm3 == 0x002 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a96; op2val:0xb4df; +op3val:0x3402; valaddr_reg:x8; val_offset:1887*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1887*FLEN/8, x10, x3, x5) + +inst_652: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x296 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0df and fs3 == 0 and fe3 == 0x0d and fm3 == 0x002 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a96; op2val:0xb4df; +op3val:0x3402; valaddr_reg:x8; val_offset:1890*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1890*FLEN/8, x10, x3, x5) + +inst_653: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x296 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0df and fs3 == 0 and fe3 == 0x0d and fm3 == 0x002 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a96; op2val:0xb4df; +op3val:0x3402; valaddr_reg:x8; val_offset:1893*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1893*FLEN/8, x10, x3, x5) + +inst_654: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x296 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0df and fs3 == 0 and fe3 == 0x0d and fm3 == 0x002 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a96; op2val:0xb4df; +op3val:0x3402; valaddr_reg:x8; val_offset:1896*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1896*FLEN/8, x10, x3, x5) + +inst_655: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x320 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x042 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x397 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b20; op2val:0xbc42; +op3val:0x3b97; valaddr_reg:x8; val_offset:1899*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1899*FLEN/8, x10, x3, x5) + +inst_656: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x320 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x042 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x397 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b20; op2val:0xbc42; +op3val:0x3b97; valaddr_reg:x8; val_offset:1902*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1902*FLEN/8, x10, x3, x5) + +inst_657: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x320 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x042 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x397 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b20; op2val:0xbc42; +op3val:0x3b97; valaddr_reg:x8; val_offset:1905*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1905*FLEN/8, x10, x3, x5) + +inst_658: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x320 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x042 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x397 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b20; op2val:0xbc42; +op3val:0x3b97; valaddr_reg:x8; val_offset:1908*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1908*FLEN/8, x10, x3, x5) + +inst_659: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x320 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x042 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x397 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b20; op2val:0xbc42; +op3val:0x3b97; valaddr_reg:x8; val_offset:1911*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1911*FLEN/8, x10, x3, x5) + +inst_660: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x31b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0c0 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x038 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x371b; op2val:0xb8c0; +op3val:0x3438; valaddr_reg:x8; val_offset:1914*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1914*FLEN/8, x10, x3, x5) + +inst_661: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x31b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0c0 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x038 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x371b; op2val:0xb8c0; +op3val:0x3438; valaddr_reg:x8; val_offset:1917*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1917*FLEN/8, x10, x3, x5) + +inst_662: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x31b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0c0 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x038 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x371b; op2val:0xb8c0; +op3val:0x3438; valaddr_reg:x8; val_offset:1920*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1920*FLEN/8, x10, x3, x5) + +inst_663: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x31b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0c0 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x038 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x371b; op2val:0xb8c0; +op3val:0x3438; valaddr_reg:x8; val_offset:1923*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1923*FLEN/8, x10, x3, x5) +RVTEST_SIGBASE(x3,signature_x3_5) + +inst_664: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x31b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0c0 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x038 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x371b; op2val:0xb8c0; +op3val:0x3438; valaddr_reg:x8; val_offset:1926*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1926*FLEN/8, x10, x3, x5) + +inst_665: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x199 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x109 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x30c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3199; op2val:0xc109; +op3val:0x370c; valaddr_reg:x8; val_offset:1929*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1929*FLEN/8, x10, x3, x5) + +inst_666: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x199 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x109 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x30c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3199; op2val:0xc109; +op3val:0x370c; valaddr_reg:x8; val_offset:1932*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1932*FLEN/8, x10, x3, x5) + +inst_667: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x199 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x109 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x30c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3199; op2val:0xc109; +op3val:0x370c; valaddr_reg:x8; val_offset:1935*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1935*FLEN/8, x10, x3, x5) + +inst_668: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x199 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x109 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x30c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3199; op2val:0xc109; +op3val:0x370c; valaddr_reg:x8; val_offset:1938*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1938*FLEN/8, x10, x3, x5) + +inst_669: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x199 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x109 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x30c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3199; op2val:0xc109; +op3val:0x370c; valaddr_reg:x8; val_offset:1941*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1941*FLEN/8, x10, x3, x5) + +inst_670: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x162 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x19e and fs3 == 0 and fe3 == 0x0b and fm3 == 0x38f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3962; op2val:0xb19e; +op3val:0x2f8f; valaddr_reg:x8; val_offset:1944*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1944*FLEN/8, x10, x3, x5) + +inst_671: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x162 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x19e and fs3 == 0 and fe3 == 0x0b and fm3 == 0x38f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3962; op2val:0xb19e; +op3val:0x2f8f; valaddr_reg:x8; val_offset:1947*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1947*FLEN/8, x10, x3, x5) + +inst_672: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x162 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x19e and fs3 == 0 and fe3 == 0x0b and fm3 == 0x38f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3962; op2val:0xb19e; +op3val:0x2f8f; valaddr_reg:x8; val_offset:1950*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1950*FLEN/8, x10, x3, x5) + +inst_673: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x162 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x19e and fs3 == 0 and fe3 == 0x0b and fm3 == 0x38f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3962; op2val:0xb19e; +op3val:0x2f8f; valaddr_reg:x8; val_offset:1953*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1953*FLEN/8, x10, x3, x5) + +inst_674: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x162 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x19e and fs3 == 0 and fe3 == 0x0b and fm3 == 0x38f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3962; op2val:0xb19e; +op3val:0x2f8f; valaddr_reg:x8; val_offset:1956*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1956*FLEN/8, x10, x3, x5) + +inst_675: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x038 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3e6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x02b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3438; op2val:0xbfe6; +op3val:0x382b; valaddr_reg:x8; val_offset:1959*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1959*FLEN/8, x10, x3, x5) + +inst_676: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x038 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3e6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x02b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3438; op2val:0xbfe6; +op3val:0x382b; valaddr_reg:x8; val_offset:1962*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1962*FLEN/8, x10, x3, x5) + +inst_677: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x038 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3e6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x02b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3438; op2val:0xbfe6; +op3val:0x382b; valaddr_reg:x8; val_offset:1965*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1965*FLEN/8, x10, x3, x5) + +inst_678: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x038 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3e6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x02b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3438; op2val:0xbfe6; +op3val:0x382b; valaddr_reg:x8; val_offset:1968*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1968*FLEN/8, x10, x3, x5) + +inst_679: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x038 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3e6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x02b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3438; op2val:0xbfe6; +op3val:0x382b; valaddr_reg:x8; val_offset:1971*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1971*FLEN/8, x10, x3, x5) + +inst_680: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2fe and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0b0 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x018 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36fe; op2val:0xb0b0; +op3val:0x2c18; valaddr_reg:x8; val_offset:1974*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1974*FLEN/8, x10, x3, x5) + +inst_681: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2fe and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0b0 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x018 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36fe; op2val:0xb0b0; +op3val:0x2c18; valaddr_reg:x8; val_offset:1977*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1977*FLEN/8, x10, x3, x5) + +inst_682: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2fe and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0b0 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x018 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36fe; op2val:0xb0b0; +op3val:0x2c18; valaddr_reg:x8; val_offset:1980*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1980*FLEN/8, x10, x3, x5) + +inst_683: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2fe and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0b0 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x018 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36fe; op2val:0xb0b0; +op3val:0x2c18; valaddr_reg:x8; val_offset:1983*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1983*FLEN/8, x10, x3, x5) + +inst_684: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2fe and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0b0 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x018 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36fe; op2val:0xb0b0; +op3val:0x2c18; valaddr_reg:x8; val_offset:1986*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1986*FLEN/8, x10, x3, x5) + +inst_685: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x189 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x25e and fs3 == 0 and fe3 == 0x0b and fm3 == 0x067 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1989; op2val:0xce5e; +op3val:0x2c67; valaddr_reg:x8; val_offset:1989*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1989*FLEN/8, x10, x3, x5) + +inst_686: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x189 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x25e and fs3 == 0 and fe3 == 0x0b and fm3 == 0x067 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1989; op2val:0xce5e; +op3val:0x2c67; valaddr_reg:x8; val_offset:1992*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1992*FLEN/8, x10, x3, x5) + +inst_687: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x189 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x25e and fs3 == 0 and fe3 == 0x0b and fm3 == 0x067 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1989; op2val:0xce5e; +op3val:0x2c67; valaddr_reg:x8; val_offset:1995*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1995*FLEN/8, x10, x3, x5) + +inst_688: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x189 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x25e and fs3 == 0 and fe3 == 0x0b and fm3 == 0x067 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1989; op2val:0xce5e; +op3val:0x2c67; valaddr_reg:x8; val_offset:1998*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1998*FLEN/8, x10, x3, x5) + +inst_689: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x189 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x25e and fs3 == 0 and fe3 == 0x0b and fm3 == 0x067 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1989; op2val:0xce5e; +op3val:0x2c67; valaddr_reg:x8; val_offset:2001*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2001*FLEN/8, x10, x3, x5) + +inst_690: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2f0 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x235 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x162 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3af0; op2val:0xba35; +op3val:0x3962; valaddr_reg:x8; val_offset:2004*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2004*FLEN/8, x10, x3, x5) + +inst_691: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2f0 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x235 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x162 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3af0; op2val:0xba35; +op3val:0x3962; valaddr_reg:x8; val_offset:2007*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2007*FLEN/8, x10, x3, x5) + +inst_692: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2f0 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x235 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x162 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3af0; op2val:0xba35; +op3val:0x3962; valaddr_reg:x8; val_offset:2010*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2010*FLEN/8, x10, x3, x5) + +inst_693: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2f0 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x235 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x162 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3af0; op2val:0xba35; +op3val:0x3962; valaddr_reg:x8; val_offset:2013*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2013*FLEN/8, x10, x3, x5) + +inst_694: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2f0 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x235 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x162 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3af0; op2val:0xba35; +op3val:0x3962; valaddr_reg:x8; val_offset:2016*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2016*FLEN/8, x10, x3, x5) + +inst_695: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0bc and fs2 == 1 and fe2 == 0x0f and fm2 == 0x19d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2a5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38bc; op2val:0xbd9d; +op3val:0x3aa5; valaddr_reg:x8; val_offset:2019*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2019*FLEN/8, x10, x3, x5) + +inst_696: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0bc and fs2 == 1 and fe2 == 0x0f and fm2 == 0x19d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2a5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38bc; op2val:0xbd9d; +op3val:0x3aa5; valaddr_reg:x8; val_offset:2022*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2022*FLEN/8, x10, x3, x5) + +inst_697: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0bc and fs2 == 1 and fe2 == 0x0f and fm2 == 0x19d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2a5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38bc; op2val:0xbd9d; +op3val:0x3aa5; valaddr_reg:x8; val_offset:2025*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2025*FLEN/8, x10, x3, x5) + +inst_698: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0bc and fs2 == 1 and fe2 == 0x0f and fm2 == 0x19d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2a5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38bc; op2val:0xbd9d; +op3val:0x3aa5; valaddr_reg:x8; val_offset:2028*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2028*FLEN/8, x10, x3, x5) + +inst_699: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0bc and fs2 == 1 and fe2 == 0x0f and fm2 == 0x19d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2a5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38bc; op2val:0xbd9d; +op3val:0x3aa5; valaddr_reg:x8; val_offset:2031*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2031*FLEN/8, x10, x3, x5) + +inst_700: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x39d and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3e4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x383 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x339d; op2val:0xc3e4; +op3val:0x3b83; valaddr_reg:x8; val_offset:2034*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2034*FLEN/8, x10, x3, x5) + +inst_701: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x39d and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3e4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x383 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x339d; op2val:0xc3e4; +op3val:0x3b83; valaddr_reg:x8; val_offset:2037*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2037*FLEN/8, x10, x3, x5) + +inst_702: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x39d and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3e4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x383 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x339d; op2val:0xc3e4; +op3val:0x3b83; valaddr_reg:x8; val_offset:2040*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2040*FLEN/8, x10, x3, x5) + +inst_703: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x39d and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3e4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x383 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x339d; op2val:0xc3e4; +op3val:0x3b83; valaddr_reg:x8; val_offset:2043*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2043*FLEN/8, x10, x3, x5) + +inst_704: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x39d and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3e4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x383 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x339d; op2val:0xc3e4; +op3val:0x3b83; valaddr_reg:x8; val_offset:2046*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2046*FLEN/8, x10, x3, x5) + +inst_705: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x334 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x35c and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2a1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f34; op2val:0xc35c; +op3val:0x36a1; valaddr_reg:x8; val_offset:2049*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2049*FLEN/8, x10, x3, x5) + +inst_706: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x334 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x35c and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2a1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f34; op2val:0xc35c; +op3val:0x36a1; valaddr_reg:x8; val_offset:2052*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2052*FLEN/8, x10, x3, x5) + +inst_707: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x334 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x35c and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2a1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f34; op2val:0xc35c; +op3val:0x36a1; valaddr_reg:x8; val_offset:2055*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2055*FLEN/8, x10, x3, x5) + +inst_708: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x334 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x35c and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2a1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f34; op2val:0xc35c; +op3val:0x36a1; valaddr_reg:x8; val_offset:2058*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2058*FLEN/8, x10, x3, x5) + +inst_709: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x334 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x35c and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2a1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f34; op2val:0xc35c; +op3val:0x36a1; valaddr_reg:x8; val_offset:2061*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2061*FLEN/8, x10, x3, x5) + +inst_710: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x22e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x20f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0ae and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x362e; op2val:0xbe0f; +op3val:0x38ae; valaddr_reg:x8; val_offset:2064*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2064*FLEN/8, x10, x3, x5) + +inst_711: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x22e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x20f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0ae and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x362e; op2val:0xbe0f; +op3val:0x38ae; valaddr_reg:x8; val_offset:2067*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2067*FLEN/8, x10, x3, x5) + +inst_712: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x22e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x20f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0ae and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x362e; op2val:0xbe0f; +op3val:0x38ae; valaddr_reg:x8; val_offset:2070*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2070*FLEN/8, x10, x3, x5) + +inst_713: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x22e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x20f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0ae and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x362e; op2val:0xbe0f; +op3val:0x38ae; valaddr_reg:x8; val_offset:2073*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2073*FLEN/8, x10, x3, x5) + +inst_714: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x22e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x20f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0ae and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x362e; op2val:0xbe0f; +op3val:0x38ae; valaddr_reg:x8; val_offset:2076*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2076*FLEN/8, x10, x3, x5) + +inst_715: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x011 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2a3 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2bf and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2c11; op2val:0xc6a3; +op3val:0x36bf; valaddr_reg:x8; val_offset:2079*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2079*FLEN/8, x10, x3, x5) + +inst_716: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x011 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2a3 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2bf and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2c11; op2val:0xc6a3; +op3val:0x36bf; valaddr_reg:x8; val_offset:2082*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2082*FLEN/8, x10, x3, x5) + +inst_717: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x011 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2a3 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2bf and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2c11; op2val:0xc6a3; +op3val:0x36bf; valaddr_reg:x8; val_offset:2085*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2085*FLEN/8, x10, x3, x5) + +inst_718: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x011 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2a3 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2bf and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2c11; op2val:0xc6a3; +op3val:0x36bf; valaddr_reg:x8; val_offset:2088*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2088*FLEN/8, x10, x3, x5) + +inst_719: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x011 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2a3 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2bf and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2c11; op2val:0xc6a3; +op3val:0x36bf; valaddr_reg:x8; val_offset:2091*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2091*FLEN/8, x10, x3, x5) + +inst_720: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x29f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1fc and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0f3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e9f; op2val:0xb9fc; +op3val:0x2cf3; valaddr_reg:x8; val_offset:2094*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2094*FLEN/8, x10, x3, x5) + +inst_721: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x29f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1fc and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0f3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e9f; op2val:0xb9fc; +op3val:0x2cf3; valaddr_reg:x8; val_offset:2097*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2097*FLEN/8, x10, x3, x5) + +inst_722: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x29f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1fc and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0f3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e9f; op2val:0xb9fc; +op3val:0x2cf3; valaddr_reg:x8; val_offset:2100*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2100*FLEN/8, x10, x3, x5) + +inst_723: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x29f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1fc and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0f3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e9f; op2val:0xb9fc; +op3val:0x2cf3; valaddr_reg:x8; val_offset:2103*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2103*FLEN/8, x10, x3, x5) + +inst_724: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x29f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1fc and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0f3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e9f; op2val:0xb9fc; +op3val:0x2cf3; valaddr_reg:x8; val_offset:2106*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2106*FLEN/8, x10, x3, x5) + +inst_725: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ed and fs2 == 1 and fe2 == 0x0a and fm2 == 0x2f7 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x046 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34ed; op2val:0xaaf7; +op3val:0x2446; valaddr_reg:x8; val_offset:2109*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2109*FLEN/8, x10, x3, x5) + +inst_726: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ed and fs2 == 1 and fe2 == 0x0a and fm2 == 0x2f7 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x046 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34ed; op2val:0xaaf7; +op3val:0x2446; valaddr_reg:x8; val_offset:2112*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2112*FLEN/8, x10, x3, x5) + +inst_727: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ed and fs2 == 1 and fe2 == 0x0a and fm2 == 0x2f7 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x046 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34ed; op2val:0xaaf7; +op3val:0x2446; valaddr_reg:x8; val_offset:2115*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2115*FLEN/8, x10, x3, x5) + +inst_728: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ed and fs2 == 1 and fe2 == 0x0a and fm2 == 0x2f7 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x046 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34ed; op2val:0xaaf7; +op3val:0x2446; valaddr_reg:x8; val_offset:2118*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2118*FLEN/8, x10, x3, x5) + +inst_729: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ed and fs2 == 1 and fe2 == 0x0a and fm2 == 0x2f7 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x046 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34ed; op2val:0xaaf7; +op3val:0x2446; valaddr_reg:x8; val_offset:2121*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2121*FLEN/8, x10, x3, x5) + +inst_730: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x015 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x111 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3815; op2val:0xbcf7; +op3val:0x3911; valaddr_reg:x8; val_offset:2124*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2124*FLEN/8, x10, x3, x5) + +inst_731: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x015 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x111 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3815; op2val:0xbcf7; +op3val:0x3911; valaddr_reg:x8; val_offset:2127*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2127*FLEN/8, x10, x3, x5) + +inst_732: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x015 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x111 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3815; op2val:0xbcf7; +op3val:0x3911; valaddr_reg:x8; val_offset:2130*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2130*FLEN/8, x10, x3, x5) + +inst_733: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x015 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x111 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3815; op2val:0xbcf7; +op3val:0x3911; valaddr_reg:x8; val_offset:2133*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2133*FLEN/8, x10, x3, x5) + +inst_734: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x015 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x111 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3815; op2val:0xbcf7; +op3val:0x3911; valaddr_reg:x8; val_offset:2136*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2136*FLEN/8, x10, x3, x5) + +inst_735: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0fe and fs2 == 1 and fe2 == 0x10 and fm2 == 0x20c and fs3 == 0 and fe3 == 0x0d and fm3 == 0x38d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30fe; op2val:0xc20c; +op3val:0x378d; valaddr_reg:x8; val_offset:2139*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2139*FLEN/8, x10, x3, x5) + +inst_736: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0fe and fs2 == 1 and fe2 == 0x10 and fm2 == 0x20c and fs3 == 0 and fe3 == 0x0d and fm3 == 0x38d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30fe; op2val:0xc20c; +op3val:0x378d; valaddr_reg:x8; val_offset:2142*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2142*FLEN/8, x10, x3, x5) + +inst_737: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0fe and fs2 == 1 and fe2 == 0x10 and fm2 == 0x20c and fs3 == 0 and fe3 == 0x0d and fm3 == 0x38d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30fe; op2val:0xc20c; +op3val:0x378d; valaddr_reg:x8; val_offset:2145*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2145*FLEN/8, x10, x3, x5) + +inst_738: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0fe and fs2 == 1 and fe2 == 0x10 and fm2 == 0x20c and fs3 == 0 and fe3 == 0x0d and fm3 == 0x38d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30fe; op2val:0xc20c; +op3val:0x378d; valaddr_reg:x8; val_offset:2148*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2148*FLEN/8, x10, x3, x5) + +inst_739: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0fe and fs2 == 1 and fe2 == 0x10 and fm2 == 0x20c and fs3 == 0 and fe3 == 0x0d and fm3 == 0x38d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30fe; op2val:0xc20c; +op3val:0x378d; valaddr_reg:x8; val_offset:2151*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2151*FLEN/8, x10, x3, x5) + +inst_740: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x187 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x368 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x11e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3987; op2val:0xb768; +op3val:0x351e; valaddr_reg:x8; val_offset:2154*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2154*FLEN/8, x10, x3, x5) + +inst_741: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x187 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x368 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x11e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3987; op2val:0xb768; +op3val:0x351e; valaddr_reg:x8; val_offset:2157*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2157*FLEN/8, x10, x3, x5) + +inst_742: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x187 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x368 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x11e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3987; op2val:0xb768; +op3val:0x351e; valaddr_reg:x8; val_offset:2160*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2160*FLEN/8, x10, x3, x5) + +inst_743: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x187 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x368 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x11e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3987; op2val:0xb768; +op3val:0x351e; valaddr_reg:x8; val_offset:2163*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2163*FLEN/8, x10, x3, x5) + +inst_744: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x187 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x368 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x11e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3987; op2val:0xb768; +op3val:0x351e; valaddr_reg:x8; val_offset:2166*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2166*FLEN/8, x10, x3, x5) + +inst_745: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x031 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2a7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2fa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3831; op2val:0xbea7; +op3val:0x3afa; valaddr_reg:x8; val_offset:2169*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2169*FLEN/8, x10, x3, x5) + +inst_746: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x031 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2a7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2fa and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3831; op2val:0xbea7; +op3val:0x3afa; valaddr_reg:x8; val_offset:2172*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2172*FLEN/8, x10, x3, x5) + +inst_747: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x031 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2a7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2fa and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3831; op2val:0xbea7; +op3val:0x3afa; valaddr_reg:x8; val_offset:2175*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2175*FLEN/8, x10, x3, x5) + +inst_748: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x031 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2a7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2fa and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3831; op2val:0xbea7; +op3val:0x3afa; valaddr_reg:x8; val_offset:2178*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2178*FLEN/8, x10, x3, x5) + +inst_749: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x031 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2a7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2fa and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3831; op2val:0xbea7; +op3val:0x3afa; valaddr_reg:x8; val_offset:2181*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2181*FLEN/8, x10, x3, x5) + +inst_750: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x130 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x22a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3130; op2val:0xc22a; +op3val:0x3800; valaddr_reg:x8; val_offset:2184*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2184*FLEN/8, x10, x3, x5) + +inst_751: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x130 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x22a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3130; op2val:0xc22a; +op3val:0x3800; valaddr_reg:x8; val_offset:2187*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2187*FLEN/8, x10, x3, x5) + +inst_752: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x130 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x22a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3130; op2val:0xc22a; +op3val:0x3800; valaddr_reg:x8; val_offset:2190*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2190*FLEN/8, x10, x3, x5) + +inst_753: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x130 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x22a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3130; op2val:0xc22a; +op3val:0x3800; valaddr_reg:x8; val_offset:2193*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2193*FLEN/8, x10, x3, x5) + +inst_754: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x130 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x22a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3130; op2val:0xc22a; +op3val:0x3800; valaddr_reg:x8; val_offset:2196*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2196*FLEN/8, x10, x3, x5) + +inst_755: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x34b and fs2 == 1 and fe2 == 0x13 and fm2 == 0x017 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x376 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x274b; op2val:0xcc17; +op3val:0x3776; valaddr_reg:x8; val_offset:2199*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2199*FLEN/8, x10, x3, x5) + +inst_756: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x34b and fs2 == 1 and fe2 == 0x13 and fm2 == 0x017 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x376 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x274b; op2val:0xcc17; +op3val:0x3776; valaddr_reg:x8; val_offset:2202*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2202*FLEN/8, x10, x3, x5) + +inst_757: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x34b and fs2 == 1 and fe2 == 0x13 and fm2 == 0x017 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x376 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x274b; op2val:0xcc17; +op3val:0x3776; valaddr_reg:x8; val_offset:2205*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2205*FLEN/8, x10, x3, x5) + +inst_758: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x34b and fs2 == 1 and fe2 == 0x13 and fm2 == 0x017 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x376 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x274b; op2val:0xcc17; +op3val:0x3776; valaddr_reg:x8; val_offset:2208*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2208*FLEN/8, x10, x3, x5) + +inst_759: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x34b and fs2 == 1 and fe2 == 0x13 and fm2 == 0x017 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x376 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x274b; op2val:0xcc17; +op3val:0x3776; valaddr_reg:x8; val_offset:2211*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2211*FLEN/8, x10, x3, x5) + +inst_760: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x00b and fs2 == 1 and fe2 == 0x12 and fm2 == 0x19f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1af and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2c0b; op2val:0xc99f; +op3val:0x39af; valaddr_reg:x8; val_offset:2214*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2214*FLEN/8, x10, x3, x5) + +inst_761: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x00b and fs2 == 1 and fe2 == 0x12 and fm2 == 0x19f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1af and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2c0b; op2val:0xc99f; +op3val:0x39af; valaddr_reg:x8; val_offset:2217*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2217*FLEN/8, x10, x3, x5) + +inst_762: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x00b and fs2 == 1 and fe2 == 0x12 and fm2 == 0x19f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1af and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2c0b; op2val:0xc99f; +op3val:0x39af; valaddr_reg:x8; val_offset:2220*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2220*FLEN/8, x10, x3, x5) + +inst_763: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x00b and fs2 == 1 and fe2 == 0x12 and fm2 == 0x19f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1af and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2c0b; op2val:0xc99f; +op3val:0x39af; valaddr_reg:x8; val_offset:2223*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2223*FLEN/8, x10, x3, x5) + +inst_764: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x00b and fs2 == 1 and fe2 == 0x12 and fm2 == 0x19f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1af and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2c0b; op2val:0xc99f; +op3val:0x39af; valaddr_reg:x8; val_offset:2226*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2226*FLEN/8, x10, x3, x5) + +inst_765: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x242 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0d7 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x393 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a42; op2val:0xb8d7; +op3val:0x3793; valaddr_reg:x8; val_offset:2229*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2229*FLEN/8, x10, x3, x5) + +inst_766: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x242 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0d7 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x393 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a42; op2val:0xb8d7; +op3val:0x3793; valaddr_reg:x8; val_offset:2232*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2232*FLEN/8, x10, x3, x5) + +inst_767: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x242 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0d7 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x393 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a42; op2val:0xb8d7; +op3val:0x3793; valaddr_reg:x8; val_offset:2235*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2235*FLEN/8, x10, x3, x5) + +inst_768: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x242 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0d7 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x393 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a42; op2val:0xb8d7; +op3val:0x3793; valaddr_reg:x8; val_offset:2238*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2238*FLEN/8, x10, x3, x5) + +inst_769: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x242 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0d7 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x393 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a42; op2val:0xb8d7; +op3val:0x3793; valaddr_reg:x8; val_offset:2241*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2241*FLEN/8, x10, x3, x5) + +inst_770: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x377 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x202 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x19b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3377; op2val:0xba02; +op3val:0x319b; valaddr_reg:x8; val_offset:2244*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2244*FLEN/8, x10, x3, x5) + +inst_771: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x377 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x202 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x19b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3377; op2val:0xba02; +op3val:0x319b; valaddr_reg:x8; val_offset:2247*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2247*FLEN/8, x10, x3, x5) + +inst_772: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x377 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x202 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x19b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3377; op2val:0xba02; +op3val:0x319b; valaddr_reg:x8; val_offset:2250*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2250*FLEN/8, x10, x3, x5) + +inst_773: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x377 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x202 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x19b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3377; op2val:0xba02; +op3val:0x319b; valaddr_reg:x8; val_offset:2253*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2253*FLEN/8, x10, x3, x5) + +inst_774: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x377 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x202 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x19b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3377; op2val:0xba02; +op3val:0x319b; valaddr_reg:x8; val_offset:2256*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2256*FLEN/8, x10, x3, x5) + +inst_775: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a4 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0f7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x301 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35a4; op2val:0xc0f7; +op3val:0x3b01; valaddr_reg:x8; val_offset:2259*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2259*FLEN/8, x10, x3, x5) + +inst_776: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a4 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0f7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x301 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35a4; op2val:0xc0f7; +op3val:0x3b01; valaddr_reg:x8; val_offset:2262*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2262*FLEN/8, x10, x3, x5) + +inst_777: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a4 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0f7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x301 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35a4; op2val:0xc0f7; +op3val:0x3b01; valaddr_reg:x8; val_offset:2265*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2265*FLEN/8, x10, x3, x5) + +inst_778: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a4 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0f7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x301 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35a4; op2val:0xc0f7; +op3val:0x3b01; valaddr_reg:x8; val_offset:2268*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2268*FLEN/8, x10, x3, x5) + +inst_779: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a4 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0f7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x301 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35a4; op2val:0xc0f7; +op3val:0x3b01; valaddr_reg:x8; val_offset:2271*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2271*FLEN/8, x10, x3, x5) + +inst_780: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d8 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x25e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3b8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38d8; op2val:0xbe5e; +op3val:0x3bb8; valaddr_reg:x8; val_offset:2274*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2274*FLEN/8, x10, x3, x5) + +inst_781: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d8 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x25e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3b8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38d8; op2val:0xbe5e; +op3val:0x3bb8; valaddr_reg:x8; val_offset:2277*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2277*FLEN/8, x10, x3, x5) + +inst_782: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d8 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x25e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3b8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38d8; op2val:0xbe5e; +op3val:0x3bb8; valaddr_reg:x8; val_offset:2280*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2280*FLEN/8, x10, x3, x5) + +inst_783: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d8 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x25e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3b8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38d8; op2val:0xbe5e; +op3val:0x3bb8; valaddr_reg:x8; val_offset:2283*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2283*FLEN/8, x10, x3, x5) + +inst_784: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d8 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x25e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3b8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38d8; op2val:0xbe5e; +op3val:0x3bb8; valaddr_reg:x8; val_offset:2286*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2286*FLEN/8, x10, x3, x5) + +inst_785: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x107 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1a3 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x314 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3907; op2val:0xada3; +op3val:0x2b14; valaddr_reg:x8; val_offset:2289*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2289*FLEN/8, x10, x3, x5) + +inst_786: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x107 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1a3 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x314 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3907; op2val:0xada3; +op3val:0x2b14; valaddr_reg:x8; val_offset:2292*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2292*FLEN/8, x10, x3, x5) + +inst_787: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x107 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1a3 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x314 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3907; op2val:0xada3; +op3val:0x2b14; valaddr_reg:x8; val_offset:2295*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2295*FLEN/8, x10, x3, x5) + +inst_788: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x107 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1a3 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x314 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3907; op2val:0xada3; +op3val:0x2b14; valaddr_reg:x8; val_offset:2298*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2298*FLEN/8, x10, x3, x5) + +inst_789: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x107 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1a3 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x314 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3907; op2val:0xada3; +op3val:0x2b14; valaddr_reg:x8; val_offset:2301*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2301*FLEN/8, x10, x3, x5) + +inst_790: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x139 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x361 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0d1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3939; op2val:0xb761; +op3val:0x34d1; valaddr_reg:x8; val_offset:2304*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2304*FLEN/8, x10, x3, x5) + +inst_791: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x139 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x361 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0d1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3939; op2val:0xb761; +op3val:0x34d1; valaddr_reg:x8; val_offset:2307*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2307*FLEN/8, x10, x3, x5) +RVTEST_SIGBASE(x3,signature_x3_6) + +inst_792: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x139 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x361 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0d1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3939; op2val:0xb761; +op3val:0x34d1; valaddr_reg:x8; val_offset:2310*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2310*FLEN/8, x10, x3, x5) + +inst_793: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x139 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x361 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0d1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3939; op2val:0xb761; +op3val:0x34d1; valaddr_reg:x8; val_offset:2313*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2313*FLEN/8, x10, x3, x5) + +inst_794: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x139 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x361 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0d1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3939; op2val:0xb761; +op3val:0x34d1; valaddr_reg:x8; val_offset:2316*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2316*FLEN/8, x10, x3, x5) + +inst_795: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x20e and fs2 == 1 and fe2 == 0x10 and fm2 == 0x086 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2da and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x360e; op2val:0xc086; +op3val:0x3ada; valaddr_reg:x8; val_offset:2319*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2319*FLEN/8, x10, x3, x5) + +inst_796: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x20e and fs2 == 1 and fe2 == 0x10 and fm2 == 0x086 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2da and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x360e; op2val:0xc086; +op3val:0x3ada; valaddr_reg:x8; val_offset:2322*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2322*FLEN/8, x10, x3, x5) + +inst_797: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x20e and fs2 == 1 and fe2 == 0x10 and fm2 == 0x086 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2da and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x360e; op2val:0xc086; +op3val:0x3ada; valaddr_reg:x8; val_offset:2325*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2325*FLEN/8, x10, x3, x5) + +inst_798: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x20e and fs2 == 1 and fe2 == 0x10 and fm2 == 0x086 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2da and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x360e; op2val:0xc086; +op3val:0x3ada; valaddr_reg:x8; val_offset:2328*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2328*FLEN/8, x10, x3, x5) + +inst_799: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x20e and fs2 == 1 and fe2 == 0x10 and fm2 == 0x086 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2da and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x360e; op2val:0xc086; +op3val:0x3ada; valaddr_reg:x8; val_offset:2331*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2331*FLEN/8, x10, x3, x5) + +inst_800: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0fc and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e8 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x35c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34fc; op2val:0xc1e8; +op3val:0x3b5c; valaddr_reg:x8; val_offset:2334*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2334*FLEN/8, x10, x3, x5) + +inst_801: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0fc and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e8 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x35c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34fc; op2val:0xc1e8; +op3val:0x3b5c; valaddr_reg:x8; val_offset:2337*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2337*FLEN/8, x10, x3, x5) + +inst_802: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0fc and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e8 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x35c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34fc; op2val:0xc1e8; +op3val:0x3b5c; valaddr_reg:x8; val_offset:2340*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2340*FLEN/8, x10, x3, x5) + +inst_803: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0fc and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e8 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x35c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34fc; op2val:0xc1e8; +op3val:0x3b5c; valaddr_reg:x8; val_offset:2343*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2343*FLEN/8, x10, x3, x5) + +inst_804: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0fc and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e8 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x35c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34fc; op2val:0xc1e8; +op3val:0x3b5c; valaddr_reg:x8; val_offset:2346*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2346*FLEN/8, x10, x3, x5) + +inst_805: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x285 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x01f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a85; op2val:0xb81f; +op3val:0x36b8; valaddr_reg:x8; val_offset:2349*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2349*FLEN/8, x10, x3, x5) + +inst_806: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x285 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x01f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a85; op2val:0xb81f; +op3val:0x36b8; valaddr_reg:x8; val_offset:2352*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2352*FLEN/8, x10, x3, x5) + +inst_807: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x285 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x01f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a85; op2val:0xb81f; +op3val:0x36b8; valaddr_reg:x8; val_offset:2355*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2355*FLEN/8, x10, x3, x5) + +inst_808: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x285 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x01f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a85; op2val:0xb81f; +op3val:0x36b8; valaddr_reg:x8; val_offset:2358*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2358*FLEN/8, x10, x3, x5) + +inst_809: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x285 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x01f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a85; op2val:0xb81f; +op3val:0x36b8; valaddr_reg:x8; val_offset:2361*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2361*FLEN/8, x10, x3, x5) + +inst_810: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fb and fs2 == 1 and fe2 == 0x0a and fm2 == 0x13a and fs3 == 0 and fe3 == 0x0a and fm3 == 0x08e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3afb; op2val:0xa93a; +op3val:0x288e; valaddr_reg:x8; val_offset:2364*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2364*FLEN/8, x10, x3, x5) + +inst_811: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fb and fs2 == 1 and fe2 == 0x0a and fm2 == 0x13a and fs3 == 0 and fe3 == 0x0a and fm3 == 0x08e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3afb; op2val:0xa93a; +op3val:0x288e; valaddr_reg:x8; val_offset:2367*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2367*FLEN/8, x10, x3, x5) + +inst_812: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fb and fs2 == 1 and fe2 == 0x0a and fm2 == 0x13a and fs3 == 0 and fe3 == 0x0a and fm3 == 0x08e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3afb; op2val:0xa93a; +op3val:0x288e; valaddr_reg:x8; val_offset:2370*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2370*FLEN/8, x10, x3, x5) + +inst_813: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fb and fs2 == 1 and fe2 == 0x0a and fm2 == 0x13a and fs3 == 0 and fe3 == 0x0a and fm3 == 0x08e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3afb; op2val:0xa93a; +op3val:0x288e; valaddr_reg:x8; val_offset:2373*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2373*FLEN/8, x10, x3, x5) + +inst_814: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fb and fs2 == 1 and fe2 == 0x0a and fm2 == 0x13a and fs3 == 0 and fe3 == 0x0a and fm3 == 0x08e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3afb; op2val:0xa93a; +op3val:0x288e; valaddr_reg:x8; val_offset:2376*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2376*FLEN/8, x10, x3, x5) + +inst_815: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x098 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x126 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1ea and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3898; op2val:0xb926; +op3val:0x35ea; valaddr_reg:x8; val_offset:2379*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2379*FLEN/8, x10, x3, x5) + +inst_816: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x098 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x126 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1ea and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3898; op2val:0xb926; +op3val:0x35ea; valaddr_reg:x8; val_offset:2382*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2382*FLEN/8, x10, x3, x5) + +inst_817: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x098 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x126 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1ea and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3898; op2val:0xb926; +op3val:0x35ea; valaddr_reg:x8; val_offset:2385*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2385*FLEN/8, x10, x3, x5) + +inst_818: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x098 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x126 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1ea and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3898; op2val:0xb926; +op3val:0x35ea; valaddr_reg:x8; val_offset:2388*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2388*FLEN/8, x10, x3, x5) + +inst_819: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x098 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x126 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1ea and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3898; op2val:0xb926; +op3val:0x35ea; valaddr_reg:x8; val_offset:2391*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2391*FLEN/8, x10, x3, x5) + +inst_820: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x078 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x262 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x322 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2878; op2val:0xce62; +op3val:0x3b22; valaddr_reg:x8; val_offset:2394*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2394*FLEN/8, x10, x3, x5) + +inst_821: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x078 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x262 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x322 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2878; op2val:0xce62; +op3val:0x3b22; valaddr_reg:x8; val_offset:2397*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2397*FLEN/8, x10, x3, x5) + +inst_822: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x078 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x262 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x322 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2878; op2val:0xce62; +op3val:0x3b22; valaddr_reg:x8; val_offset:2400*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2400*FLEN/8, x10, x3, x5) + +inst_823: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x078 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x262 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x322 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2878; op2val:0xce62; +op3val:0x3b22; valaddr_reg:x8; val_offset:2403*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2403*FLEN/8, x10, x3, x5) + +inst_824: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x078 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x262 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x322 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2878; op2val:0xce62; +op3val:0x3b22; valaddr_reg:x8; val_offset:2406*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2406*FLEN/8, x10, x3, x5) + +inst_825: +// fs1 == 0 and fe1 == 0x05 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x18 and fm2 == 0x3a1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3ae and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1407; op2val:0xe3a1; +op3val:0x3bae; valaddr_reg:x8; val_offset:2409*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2409*FLEN/8, x10, x3, x5) + +inst_826: +// fs1 == 0 and fe1 == 0x05 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x18 and fm2 == 0x3a1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3ae and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1407; op2val:0xe3a1; +op3val:0x3bae; valaddr_reg:x8; val_offset:2412*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2412*FLEN/8, x10, x3, x5) + +inst_827: +// fs1 == 0 and fe1 == 0x05 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x18 and fm2 == 0x3a1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3ae and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1407; op2val:0xe3a1; +op3val:0x3bae; valaddr_reg:x8; val_offset:2415*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2415*FLEN/8, x10, x3, x5) + +inst_828: +// fs1 == 0 and fe1 == 0x05 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x18 and fm2 == 0x3a1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3ae and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1407; op2val:0xe3a1; +op3val:0x3bae; valaddr_reg:x8; val_offset:2418*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2418*FLEN/8, x10, x3, x5) + +inst_829: +// fs1 == 0 and fe1 == 0x05 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x18 and fm2 == 0x3a1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3ae and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1407; op2val:0xe3a1; +op3val:0x3bae; valaddr_reg:x8; val_offset:2421*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2421*FLEN/8, x10, x3, x5) + +inst_830: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x261 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2e7 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x181 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3661; op2val:0xbae7; +op3val:0x3581; valaddr_reg:x8; val_offset:2424*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2424*FLEN/8, x10, x3, x5) + +inst_831: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x261 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2e7 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x181 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3661; op2val:0xbae7; +op3val:0x3581; valaddr_reg:x8; val_offset:2427*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2427*FLEN/8, x10, x3, x5) + +inst_832: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x261 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2e7 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x181 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3661; op2val:0xbae7; +op3val:0x3581; valaddr_reg:x8; val_offset:2430*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2430*FLEN/8, x10, x3, x5) + +inst_833: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x261 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2e7 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x181 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3661; op2val:0xbae7; +op3val:0x3581; valaddr_reg:x8; val_offset:2433*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2433*FLEN/8, x10, x3, x5) + +inst_834: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x261 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2e7 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x181 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3661; op2val:0xbae7; +op3val:0x3581; valaddr_reg:x8; val_offset:2436*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2436*FLEN/8, x10, x3, x5) + +inst_835: +// fs1 == 0 and fe1 == 0x08 and fm1 == 0x346 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x1a5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x122 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2346; op2val:0xd1a5; +op3val:0x3922; valaddr_reg:x8; val_offset:2439*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2439*FLEN/8, x10, x3, x5) + +inst_836: +// fs1 == 0 and fe1 == 0x08 and fm1 == 0x346 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x1a5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x122 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2346; op2val:0xd1a5; +op3val:0x3922; valaddr_reg:x8; val_offset:2442*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2442*FLEN/8, x10, x3, x5) + +inst_837: +// fs1 == 0 and fe1 == 0x08 and fm1 == 0x346 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x1a5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x122 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2346; op2val:0xd1a5; +op3val:0x3922; valaddr_reg:x8; val_offset:2445*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2445*FLEN/8, x10, x3, x5) + +inst_838: +// fs1 == 0 and fe1 == 0x08 and fm1 == 0x346 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x1a5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x122 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2346; op2val:0xd1a5; +op3val:0x3922; valaddr_reg:x8; val_offset:2448*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2448*FLEN/8, x10, x3, x5) + +inst_839: +// fs1 == 0 and fe1 == 0x08 and fm1 == 0x346 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x1a5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x122 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2346; op2val:0xd1a5; +op3val:0x3922; valaddr_reg:x8; val_offset:2451*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2451*FLEN/8, x10, x3, x5) + +inst_840: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2d2 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x290 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x198 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ad2; op2val:0xc690; +op3val:0x3598; valaddr_reg:x8; val_offset:2454*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2454*FLEN/8, x10, x3, x5) + +inst_841: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2d2 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x290 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x198 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ad2; op2val:0xc690; +op3val:0x3598; valaddr_reg:x8; val_offset:2457*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2457*FLEN/8, x10, x3, x5) + +inst_842: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2d2 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x290 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x198 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ad2; op2val:0xc690; +op3val:0x3598; valaddr_reg:x8; val_offset:2460*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2460*FLEN/8, x10, x3, x5) + +inst_843: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2d2 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x290 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x198 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ad2; op2val:0xc690; +op3val:0x3598; valaddr_reg:x8; val_offset:2463*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2463*FLEN/8, x10, x3, x5) + +inst_844: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2d2 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x290 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x198 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ad2; op2val:0xc690; +op3val:0x3598; valaddr_reg:x8; val_offset:2466*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2466*FLEN/8, x10, x3, x5) + +inst_845: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x258 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2a4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x382f; op2val:0xbe58; +op3val:0x3aa4; valaddr_reg:x8; val_offset:2469*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2469*FLEN/8, x10, x3, x5) + +inst_846: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x258 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2a4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x382f; op2val:0xbe58; +op3val:0x3aa4; valaddr_reg:x8; val_offset:2472*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2472*FLEN/8, x10, x3, x5) + +inst_847: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x258 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2a4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x382f; op2val:0xbe58; +op3val:0x3aa4; valaddr_reg:x8; val_offset:2475*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2475*FLEN/8, x10, x3, x5) + +inst_848: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x258 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2a4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x382f; op2val:0xbe58; +op3val:0x3aa4; valaddr_reg:x8; val_offset:2478*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2478*FLEN/8, x10, x3, x5) + +inst_849: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x258 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2a4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x382f; op2val:0xbe58; +op3val:0x3aa4; valaddr_reg:x8; val_offset:2481*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2481*FLEN/8, x10, x3, x5) + +inst_850: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x21d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2a5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x114 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a1d; op2val:0xbaa5; +op3val:0x3914; valaddr_reg:x8; val_offset:2484*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2484*FLEN/8, x10, x3, x5) + +inst_851: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x21d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2a5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x114 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a1d; op2val:0xbaa5; +op3val:0x3914; valaddr_reg:x8; val_offset:2487*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2487*FLEN/8, x10, x3, x5) + +inst_852: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x21d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2a5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x114 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a1d; op2val:0xbaa5; +op3val:0x3914; valaddr_reg:x8; val_offset:2490*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2490*FLEN/8, x10, x3, x5) + +inst_853: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x21d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2a5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x114 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a1d; op2val:0xbaa5; +op3val:0x3914; valaddr_reg:x8; val_offset:2493*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2493*FLEN/8, x10, x3, x5) + +inst_854: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x21d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2a5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x114 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a1d; op2val:0xbaa5; +op3val:0x3914; valaddr_reg:x8; val_offset:2496*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2496*FLEN/8, x10, x3, x5) + +inst_855: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x13a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b0 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x106 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x393a; op2val:0xbbb0; +op3val:0x3906; valaddr_reg:x8; val_offset:2499*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2499*FLEN/8, x10, x3, x5) + +inst_856: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x13a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b0 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x106 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x393a; op2val:0xbbb0; +op3val:0x3906; valaddr_reg:x8; val_offset:2502*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2502*FLEN/8, x10, x3, x5) + +inst_857: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x13a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b0 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x106 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x393a; op2val:0xbbb0; +op3val:0x3906; valaddr_reg:x8; val_offset:2505*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2505*FLEN/8, x10, x3, x5) + +inst_858: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x13a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b0 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x106 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x393a; op2val:0xbbb0; +op3val:0x3906; valaddr_reg:x8; val_offset:2508*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2508*FLEN/8, x10, x3, x5) + +inst_859: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x13a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b0 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x106 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x393a; op2val:0xbbb0; +op3val:0x3906; valaddr_reg:x8; val_offset:2511*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2511*FLEN/8, x10, x3, x5) + +inst_860: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x224 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x283 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3224; op2val:0xc283; +op3val:0x3900; valaddr_reg:x8; val_offset:2514*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2514*FLEN/8, x10, x3, x5) + +inst_861: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x224 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x283 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x100 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3224; op2val:0xc283; +op3val:0x3900; valaddr_reg:x8; val_offset:2517*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2517*FLEN/8, x10, x3, x5) + +inst_862: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x224 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x283 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x100 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3224; op2val:0xc283; +op3val:0x3900; valaddr_reg:x8; val_offset:2520*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2520*FLEN/8, x10, x3, x5) + +inst_863: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x224 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x283 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x100 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3224; op2val:0xc283; +op3val:0x3900; valaddr_reg:x8; val_offset:2523*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2523*FLEN/8, x10, x3, x5) + +inst_864: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x224 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x283 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x100 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3224; op2val:0xc283; +op3val:0x3900; valaddr_reg:x8; val_offset:2526*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2526*FLEN/8, x10, x3, x5) + +inst_865: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1f1 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x12d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3b0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35f1; op2val:0xc12d; +op3val:0x3bb0; valaddr_reg:x8; val_offset:2529*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2529*FLEN/8, x10, x3, x5) + +inst_866: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1f1 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x12d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3b0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35f1; op2val:0xc12d; +op3val:0x3bb0; valaddr_reg:x8; val_offset:2532*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2532*FLEN/8, x10, x3, x5) + +inst_867: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1f1 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x12d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3b0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35f1; op2val:0xc12d; +op3val:0x3bb0; valaddr_reg:x8; val_offset:2535*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2535*FLEN/8, x10, x3, x5) + +inst_868: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1f1 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x12d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3b0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35f1; op2val:0xc12d; +op3val:0x3bb0; valaddr_reg:x8; val_offset:2538*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2538*FLEN/8, x10, x3, x5) + +inst_869: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1f1 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x12d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3b0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35f1; op2val:0xc12d; +op3val:0x3bb0; valaddr_reg:x8; val_offset:2541*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2541*FLEN/8, x10, x3, x5) + +inst_870: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2df and fs2 == 1 and fe2 == 0x0d and fm2 == 0x167 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0a4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3adf; op2val:0xb567; +op3val:0x34a4; valaddr_reg:x8; val_offset:2544*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2544*FLEN/8, x10, x3, x5) + +inst_871: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2df and fs2 == 1 and fe2 == 0x0d and fm2 == 0x167 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0a4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3adf; op2val:0xb567; +op3val:0x34a4; valaddr_reg:x8; val_offset:2547*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2547*FLEN/8, x10, x3, x5) + +inst_872: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2df and fs2 == 1 and fe2 == 0x0d and fm2 == 0x167 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0a4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3adf; op2val:0xb567; +op3val:0x34a4; valaddr_reg:x8; val_offset:2550*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2550*FLEN/8, x10, x3, x5) + +inst_873: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2df and fs2 == 1 and fe2 == 0x0d and fm2 == 0x167 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0a4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3adf; op2val:0xb567; +op3val:0x34a4; valaddr_reg:x8; val_offset:2553*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2553*FLEN/8, x10, x3, x5) + +inst_874: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2df and fs2 == 1 and fe2 == 0x0d and fm2 == 0x167 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0a4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3adf; op2val:0xb567; +op3val:0x34a4; valaddr_reg:x8; val_offset:2556*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2556*FLEN/8, x10, x3, x5) + +inst_875: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x301 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x246 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x17e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f01; op2val:0xc646; +op3val:0x397e; valaddr_reg:x8; val_offset:2559*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2559*FLEN/8, x10, x3, x5) + +inst_876: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x301 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x246 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x17e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f01; op2val:0xc646; +op3val:0x397e; valaddr_reg:x8; val_offset:2562*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2562*FLEN/8, x10, x3, x5) + +inst_877: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x301 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x246 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x17e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f01; op2val:0xc646; +op3val:0x397e; valaddr_reg:x8; val_offset:2565*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2565*FLEN/8, x10, x3, x5) + +inst_878: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x301 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x246 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x17e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f01; op2val:0xc646; +op3val:0x397e; valaddr_reg:x8; val_offset:2568*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2568*FLEN/8, x10, x3, x5) + +inst_879: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x301 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x246 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x17e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f01; op2val:0xc646; +op3val:0x397e; valaddr_reg:x8; val_offset:2571*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2571*FLEN/8, x10, x3, x5) + +inst_880: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3bd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x258 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x223 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bbd; op2val:0xba58; +op3val:0x3a23; valaddr_reg:x8; val_offset:2574*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2574*FLEN/8, x10, x3, x5) + +inst_881: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3bd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x258 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x223 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bbd; op2val:0xba58; +op3val:0x3a23; valaddr_reg:x8; val_offset:2577*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2577*FLEN/8, x10, x3, x5) + +inst_882: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3bd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x258 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x223 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bbd; op2val:0xba58; +op3val:0x3a23; valaddr_reg:x8; val_offset:2580*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2580*FLEN/8, x10, x3, x5) + +inst_883: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3bd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x258 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x223 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bbd; op2val:0xba58; +op3val:0x3a23; valaddr_reg:x8; val_offset:2583*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2583*FLEN/8, x10, x3, x5) + +inst_884: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3bd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x258 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x223 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bbd; op2val:0xba58; +op3val:0x3a23; valaddr_reg:x8; val_offset:2586*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2586*FLEN/8, x10, x3, x5) + +inst_885: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3ed and fs3 == 0 and fe3 == 0x0e and fm3 == 0x111 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x391d; op2val:0xbbed; +op3val:0x3911; valaddr_reg:x8; val_offset:2589*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2589*FLEN/8, x10, x3, x5) + +inst_886: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3ed and fs3 == 0 and fe3 == 0x0e and fm3 == 0x111 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x391d; op2val:0xbbed; +op3val:0x3911; valaddr_reg:x8; val_offset:2592*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2592*FLEN/8, x10, x3, x5) + +inst_887: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3ed and fs3 == 0 and fe3 == 0x0e and fm3 == 0x111 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x391d; op2val:0xbbed; +op3val:0x3911; valaddr_reg:x8; val_offset:2595*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2595*FLEN/8, x10, x3, x5) + +inst_888: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3ed and fs3 == 0 and fe3 == 0x0e and fm3 == 0x111 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x391d; op2val:0xbbed; +op3val:0x3911; valaddr_reg:x8; val_offset:2598*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2598*FLEN/8, x10, x3, x5) + +inst_889: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3ed and fs3 == 0 and fe3 == 0x0e and fm3 == 0x111 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x391d; op2val:0xbbed; +op3val:0x3911; valaddr_reg:x8; val_offset:2601*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2601*FLEN/8, x10, x3, x5) + +inst_890: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x304 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x25e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x196 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3704; op2val:0xbe5e; +op3val:0x3996; valaddr_reg:x8; val_offset:2604*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2604*FLEN/8, x10, x3, x5) + +inst_891: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x304 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x25e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x196 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3704; op2val:0xbe5e; +op3val:0x3996; valaddr_reg:x8; val_offset:2607*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2607*FLEN/8, x10, x3, x5) + +inst_892: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x304 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x25e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x196 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3704; op2val:0xbe5e; +op3val:0x3996; valaddr_reg:x8; val_offset:2610*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2610*FLEN/8, x10, x3, x5) + +inst_893: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x304 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x25e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x196 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3704; op2val:0xbe5e; +op3val:0x3996; valaddr_reg:x8; val_offset:2613*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2613*FLEN/8, x10, x3, x5) + +inst_894: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x304 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x25e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x196 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3704; op2val:0xbe5e; +op3val:0x3996; valaddr_reg:x8; val_offset:2616*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2616*FLEN/8, x10, x3, x5) + +inst_895: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0da and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2da and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35a5; op2val:0xb8da; +op3val:0x32da; valaddr_reg:x8; val_offset:2619*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2619*FLEN/8, x10, x3, x5) + +inst_896: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0da and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2da and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35a5; op2val:0xb8da; +op3val:0x32da; valaddr_reg:x8; val_offset:2622*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2622*FLEN/8, x10, x3, x5) + +inst_897: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0da and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2da and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35a5; op2val:0xb8da; +op3val:0x32da; valaddr_reg:x8; val_offset:2625*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2625*FLEN/8, x10, x3, x5) + +inst_898: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0da and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2da and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35a5; op2val:0xb8da; +op3val:0x32da; valaddr_reg:x8; val_offset:2628*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2628*FLEN/8, x10, x3, x5) + +inst_899: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0da and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2da and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35a5; op2val:0xb8da; +op3val:0x32da; valaddr_reg:x8; val_offset:2631*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2631*FLEN/8, x10, x3, x5) + +inst_900: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2f0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x023 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32f0; op2val:0xbcc5; +op3val:0x3423; valaddr_reg:x8; val_offset:2634*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2634*FLEN/8, x10, x3, x5) + +inst_901: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2f0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x023 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32f0; op2val:0xbcc5; +op3val:0x3423; valaddr_reg:x8; val_offset:2637*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2637*FLEN/8, x10, x3, x5) + +inst_902: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2f0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x023 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32f0; op2val:0xbcc5; +op3val:0x3423; valaddr_reg:x8; val_offset:2640*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2640*FLEN/8, x10, x3, x5) + +inst_903: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2f0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x023 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32f0; op2val:0xbcc5; +op3val:0x3423; valaddr_reg:x8; val_offset:2643*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2643*FLEN/8, x10, x3, x5) + +inst_904: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2f0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x023 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32f0; op2val:0xbcc5; +op3val:0x3423; valaddr_reg:x8; val_offset:2646*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2646*FLEN/8, x10, x3, x5) + +inst_905: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2a7 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x31b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36a7; op2val:0xbf1b; +op3val:0x39e9; valaddr_reg:x8; val_offset:2649*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2649*FLEN/8, x10, x3, x5) + +inst_906: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2a7 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x31b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36a7; op2val:0xbf1b; +op3val:0x39e9; valaddr_reg:x8; val_offset:2652*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2652*FLEN/8, x10, x3, x5) + +inst_907: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2a7 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x31b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36a7; op2val:0xbf1b; +op3val:0x39e9; valaddr_reg:x8; val_offset:2655*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2655*FLEN/8, x10, x3, x5) + +inst_908: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2a7 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x31b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36a7; op2val:0xbf1b; +op3val:0x39e9; valaddr_reg:x8; val_offset:2658*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2658*FLEN/8, x10, x3, x5) + +inst_909: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2a7 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x31b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36a7; op2val:0xbf1b; +op3val:0x39e9; valaddr_reg:x8; val_offset:2661*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2661*FLEN/8, x10, x3, x5) + +inst_910: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x113 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x07a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ae and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3113; op2val:0xc47a; +op3val:0x39ae; valaddr_reg:x8; val_offset:2664*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2664*FLEN/8, x10, x3, x5) + +inst_911: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x113 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x07a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ae and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3113; op2val:0xc47a; +op3val:0x39ae; valaddr_reg:x8; val_offset:2667*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2667*FLEN/8, x10, x3, x5) + +inst_912: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x113 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x07a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ae and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3113; op2val:0xc47a; +op3val:0x39ae; valaddr_reg:x8; val_offset:2670*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2670*FLEN/8, x10, x3, x5) + +inst_913: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x113 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x07a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ae and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3113; op2val:0xc47a; +op3val:0x39ae; valaddr_reg:x8; val_offset:2673*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2673*FLEN/8, x10, x3, x5) + +inst_914: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x113 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x07a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ae and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3113; op2val:0xc47a; +op3val:0x39ae; valaddr_reg:x8; val_offset:2676*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2676*FLEN/8, x10, x3, x5) + +inst_915: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x07a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3e6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x06c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x307a; op2val:0xc3e6; +op3val:0x386c; valaddr_reg:x8; val_offset:2679*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2679*FLEN/8, x10, x3, x5) + +inst_916: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x07a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3e6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x06c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x307a; op2val:0xc3e6; +op3val:0x386c; valaddr_reg:x8; val_offset:2682*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2682*FLEN/8, x10, x3, x5) + +inst_917: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x07a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3e6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x06c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x307a; op2val:0xc3e6; +op3val:0x386c; valaddr_reg:x8; val_offset:2685*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2685*FLEN/8, x10, x3, x5) + +inst_918: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x07a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3e6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x06c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x307a; op2val:0xc3e6; +op3val:0x386c; valaddr_reg:x8; val_offset:2688*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2688*FLEN/8, x10, x3, x5) + +inst_919: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x07a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3e6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x06c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x307a; op2val:0xc3e6; +op3val:0x386c; valaddr_reg:x8; val_offset:2691*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2691*FLEN/8, x10, x3, x5) +RVTEST_SIGBASE(x3,signature_x3_7) + +inst_920: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ee and fs2 == 1 and fe2 == 0x0f and fm2 == 0x167 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35ee; op2val:0xbd67; +op3val:0x3801; valaddr_reg:x8; val_offset:2694*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2694*FLEN/8, x10, x3, x5) + +inst_921: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ee and fs2 == 1 and fe2 == 0x0f and fm2 == 0x167 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x001 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35ee; op2val:0xbd67; +op3val:0x3801; valaddr_reg:x8; val_offset:2697*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2697*FLEN/8, x10, x3, x5) + +inst_922: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ee and fs2 == 1 and fe2 == 0x0f and fm2 == 0x167 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x001 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35ee; op2val:0xbd67; +op3val:0x3801; valaddr_reg:x8; val_offset:2700*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2700*FLEN/8, x10, x3, x5) + +inst_923: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ee and fs2 == 1 and fe2 == 0x0f and fm2 == 0x167 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x001 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35ee; op2val:0xbd67; +op3val:0x3801; valaddr_reg:x8; val_offset:2703*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2703*FLEN/8, x10, x3, x5) + +inst_924: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ee and fs2 == 1 and fe2 == 0x0f and fm2 == 0x167 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x001 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35ee; op2val:0xbd67; +op3val:0x3801; valaddr_reg:x8; val_offset:2706*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2706*FLEN/8, x10, x3, x5) + +inst_925: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x189 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x39d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x145 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3589; op2val:0xbf9d; +op3val:0x3945; valaddr_reg:x8; val_offset:2709*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2709*FLEN/8, x10, x3, x5) + +inst_926: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x189 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x39d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x145 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3589; op2val:0xbf9d; +op3val:0x3945; valaddr_reg:x8; val_offset:2712*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2712*FLEN/8, x10, x3, x5) + +inst_927: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x189 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x39d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x145 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3589; op2val:0xbf9d; +op3val:0x3945; valaddr_reg:x8; val_offset:2715*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2715*FLEN/8, x10, x3, x5) + +inst_928: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x189 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x39d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x145 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3589; op2val:0xbf9d; +op3val:0x3945; valaddr_reg:x8; val_offset:2718*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2718*FLEN/8, x10, x3, x5) + +inst_929: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x189 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x39d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x145 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3589; op2val:0xbf9d; +op3val:0x3945; valaddr_reg:x8; val_offset:2721*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2721*FLEN/8, x10, x3, x5) + +inst_930: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2bf and fs2 == 1 and fe2 == 0x0e and fm2 == 0x100 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x037 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36bf; op2val:0xb900; +op3val:0x3437; valaddr_reg:x8; val_offset:2724*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2724*FLEN/8, x10, x3, x5) + +inst_931: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2bf and fs2 == 1 and fe2 == 0x0e and fm2 == 0x100 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x037 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36bf; op2val:0xb900; +op3val:0x3437; valaddr_reg:x8; val_offset:2727*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2727*FLEN/8, x10, x3, x5) + +inst_932: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2bf and fs2 == 1 and fe2 == 0x0e and fm2 == 0x100 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x037 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36bf; op2val:0xb900; +op3val:0x3437; valaddr_reg:x8; val_offset:2730*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2730*FLEN/8, x10, x3, x5) + +inst_933: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2bf and fs2 == 1 and fe2 == 0x0e and fm2 == 0x100 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x037 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36bf; op2val:0xb900; +op3val:0x3437; valaddr_reg:x8; val_offset:2733*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2733*FLEN/8, x10, x3, x5) + +inst_934: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2bf and fs2 == 1 and fe2 == 0x0e and fm2 == 0x100 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x037 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36bf; op2val:0xb900; +op3val:0x3437; valaddr_reg:x8; val_offset:2736*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2736*FLEN/8, x10, x3, x5) + +inst_935: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x101 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x264 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x391b; op2val:0xb901; +op3val:0x3664; valaddr_reg:x8; val_offset:2739*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2739*FLEN/8, x10, x3, x5) + +inst_936: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x101 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x264 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x391b; op2val:0xb901; +op3val:0x3664; valaddr_reg:x8; val_offset:2742*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2742*FLEN/8, x10, x3, x5) + +inst_937: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x101 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x264 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x391b; op2val:0xb901; +op3val:0x3664; valaddr_reg:x8; val_offset:2745*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2745*FLEN/8, x10, x3, x5) + +inst_938: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x101 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x264 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x391b; op2val:0xb901; +op3val:0x3664; valaddr_reg:x8; val_offset:2748*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2748*FLEN/8, x10, x3, x5) + +inst_939: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x101 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x264 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x391b; op2val:0xb901; +op3val:0x3664; valaddr_reg:x8; val_offset:2751*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2751*FLEN/8, x10, x3, x5) + +inst_940: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x059 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3cd and fs3 == 0 and fe3 == 0x0e and fm3 == 0x03d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3859; op2val:0xbbcd; +op3val:0x383d; valaddr_reg:x8; val_offset:2754*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2754*FLEN/8, x10, x3, x5) + +inst_941: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x059 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3cd and fs3 == 0 and fe3 == 0x0e and fm3 == 0x03d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3859; op2val:0xbbcd; +op3val:0x383d; valaddr_reg:x8; val_offset:2757*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2757*FLEN/8, x10, x3, x5) + +inst_942: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x059 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3cd and fs3 == 0 and fe3 == 0x0e and fm3 == 0x03d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3859; op2val:0xbbcd; +op3val:0x383d; valaddr_reg:x8; val_offset:2760*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2760*FLEN/8, x10, x3, x5) + +inst_943: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x059 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3cd and fs3 == 0 and fe3 == 0x0e and fm3 == 0x03d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3859; op2val:0xbbcd; +op3val:0x383d; valaddr_reg:x8; val_offset:2763*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2763*FLEN/8, x10, x3, x5) + +inst_944: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x059 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3cd and fs3 == 0 and fe3 == 0x0e and fm3 == 0x03d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3859; op2val:0xbbcd; +op3val:0x383d; valaddr_reg:x8; val_offset:2766*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2766*FLEN/8, x10, x3, x5) + +inst_945: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ee and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1e2 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x341 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ee; op2val:0xb9e2; +op3val:0x3741; valaddr_reg:x8; val_offset:2769*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2769*FLEN/8, x10, x3, x5) + +inst_946: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ee and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1e2 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x341 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ee; op2val:0xb9e2; +op3val:0x3741; valaddr_reg:x8; val_offset:2772*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2772*FLEN/8, x10, x3, x5) + +inst_947: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ee and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1e2 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x341 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ee; op2val:0xb9e2; +op3val:0x3741; valaddr_reg:x8; val_offset:2775*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2775*FLEN/8, x10, x3, x5) + +inst_948: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ee and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1e2 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x341 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ee; op2val:0xb9e2; +op3val:0x3741; valaddr_reg:x8; val_offset:2778*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2778*FLEN/8, x10, x3, x5) + +inst_949: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ee and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1e2 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x341 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ee; op2val:0xb9e2; +op3val:0x3741; valaddr_reg:x8; val_offset:2781*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2781*FLEN/8, x10, x3, x5) + +inst_950: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0a6 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1af and fs3 == 0 and fe3 == 0x0e and fm3 == 0x29c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34a6; op2val:0xc1af; +op3val:0x3a9c; valaddr_reg:x8; val_offset:2784*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2784*FLEN/8, x10, x3, x5) + +inst_951: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0a6 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1af and fs3 == 0 and fe3 == 0x0e and fm3 == 0x29c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34a6; op2val:0xc1af; +op3val:0x3a9c; valaddr_reg:x8; val_offset:2787*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2787*FLEN/8, x10, x3, x5) + +inst_952: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0a6 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1af and fs3 == 0 and fe3 == 0x0e and fm3 == 0x29c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34a6; op2val:0xc1af; +op3val:0x3a9c; valaddr_reg:x8; val_offset:2790*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2790*FLEN/8, x10, x3, x5) + +inst_953: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0a6 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1af and fs3 == 0 and fe3 == 0x0e and fm3 == 0x29c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34a6; op2val:0xc1af; +op3val:0x3a9c; valaddr_reg:x8; val_offset:2793*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2793*FLEN/8, x10, x3, x5) + +inst_954: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0a6 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1af and fs3 == 0 and fe3 == 0x0e and fm3 == 0x29c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34a6; op2val:0xc1af; +op3val:0x3a9c; valaddr_reg:x8; val_offset:2796*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2796*FLEN/8, x10, x3, x5) + +inst_955: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d4 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2a0 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1a8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ad4; op2val:0xb2a0; +op3val:0x31a8; valaddr_reg:x8; val_offset:2799*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2799*FLEN/8, x10, x3, x5) + +inst_956: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d4 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2a0 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1a8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ad4; op2val:0xb2a0; +op3val:0x31a8; valaddr_reg:x8; val_offset:2802*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2802*FLEN/8, x10, x3, x5) + +inst_957: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d4 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2a0 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1a8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ad4; op2val:0xb2a0; +op3val:0x31a8; valaddr_reg:x8; val_offset:2805*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2805*FLEN/8, x10, x3, x5) + +inst_958: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d4 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2a0 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1a8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ad4; op2val:0xb2a0; +op3val:0x31a8; valaddr_reg:x8; val_offset:2808*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2808*FLEN/8, x10, x3, x5) + +inst_959: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d4 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2a0 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1a8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ad4; op2val:0xb2a0; +op3val:0x31a8; valaddr_reg:x8; val_offset:2811*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2811*FLEN/8, x10, x3, x5) + +inst_960: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x34a and fs2 == 1 and fe2 == 0x0c and fm2 == 0x344 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x29f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b4a; op2val:0xb344; +op3val:0x329f; valaddr_reg:x8; val_offset:2814*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2814*FLEN/8, x10, x3, x5) + +inst_961: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x34a and fs2 == 1 and fe2 == 0x0c and fm2 == 0x344 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x29f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b4a; op2val:0xb344; +op3val:0x329f; valaddr_reg:x8; val_offset:2817*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2817*FLEN/8, x10, x3, x5) + +inst_962: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x34a and fs2 == 1 and fe2 == 0x0c and fm2 == 0x344 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x29f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b4a; op2val:0xb344; +op3val:0x329f; valaddr_reg:x8; val_offset:2820*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2820*FLEN/8, x10, x3, x5) + +inst_963: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x34a and fs2 == 1 and fe2 == 0x0c and fm2 == 0x344 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x29f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b4a; op2val:0xb344; +op3val:0x329f; valaddr_reg:x8; val_offset:2823*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2823*FLEN/8, x10, x3, x5) + +inst_964: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x34a and fs2 == 1 and fe2 == 0x0c and fm2 == 0x344 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x29f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b4a; op2val:0xb344; +op3val:0x329f; valaddr_reg:x8; val_offset:2826*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2826*FLEN/8, x10, x3, x5) + +inst_965: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3b5 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x27e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x242 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x33b5; op2val:0xc27e; +op3val:0x3a42; valaddr_reg:x8; val_offset:2829*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2829*FLEN/8, x10, x3, x5) + +inst_966: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3b5 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x27e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x242 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x33b5; op2val:0xc27e; +op3val:0x3a42; valaddr_reg:x8; val_offset:2832*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2832*FLEN/8, x10, x3, x5) + +inst_967: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3b5 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x27e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x242 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x33b5; op2val:0xc27e; +op3val:0x3a42; valaddr_reg:x8; val_offset:2835*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2835*FLEN/8, x10, x3, x5) + +inst_968: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3b5 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x27e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x242 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x33b5; op2val:0xc27e; +op3val:0x3a42; valaddr_reg:x8; val_offset:2838*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2838*FLEN/8, x10, x3, x5) + +inst_969: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3b5 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x27e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x242 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x33b5; op2val:0xc27e; +op3val:0x3a42; valaddr_reg:x8; val_offset:2841*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2841*FLEN/8, x10, x3, x5) + +inst_970: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1d2 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x01a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1f9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35d2; op2val:0xc01a; +op3val:0x39f9; valaddr_reg:x8; val_offset:2844*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2844*FLEN/8, x10, x3, x5) + +inst_971: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1d2 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x01a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1f9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35d2; op2val:0xc01a; +op3val:0x39f9; valaddr_reg:x8; val_offset:2847*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2847*FLEN/8, x10, x3, x5) + +inst_972: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1d2 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x01a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1f9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35d2; op2val:0xc01a; +op3val:0x39f9; valaddr_reg:x8; val_offset:2850*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2850*FLEN/8, x10, x3, x5) + +inst_973: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1d2 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x01a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1f9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35d2; op2val:0xc01a; +op3val:0x39f9; valaddr_reg:x8; val_offset:2853*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2853*FLEN/8, x10, x3, x5) + +inst_974: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1d2 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x01a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1f9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35d2; op2val:0xc01a; +op3val:0x39f9; valaddr_reg:x8; val_offset:2856*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2856*FLEN/8, x10, x3, x5) + +inst_975: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x393 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2c7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x26b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f93; op2val:0xc6c7; +op3val:0x3a6b; valaddr_reg:x8; val_offset:2859*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2859*FLEN/8, x10, x3, x5) + +inst_976: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x393 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2c7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x26b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f93; op2val:0xc6c7; +op3val:0x3a6b; valaddr_reg:x8; val_offset:2862*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2862*FLEN/8, x10, x3, x5) + +inst_977: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x393 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2c7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x26b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f93; op2val:0xc6c7; +op3val:0x3a6b; valaddr_reg:x8; val_offset:2865*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2865*FLEN/8, x10, x3, x5) + +inst_978: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x393 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2c7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x26b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f93; op2val:0xc6c7; +op3val:0x3a6b; valaddr_reg:x8; val_offset:2868*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2868*FLEN/8, x10, x3, x5) + +inst_979: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x393 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2c7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x26b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f93; op2val:0xc6c7; +op3val:0x3a6b; valaddr_reg:x8; val_offset:2871*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2871*FLEN/8, x10, x3, x5) + +inst_980: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x313 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x05b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3b5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b13; op2val:0xbc5b; +op3val:0x3bb5; valaddr_reg:x8; val_offset:2874*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2874*FLEN/8, x10, x3, x5) + +inst_981: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x313 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x05b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3b5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b13; op2val:0xbc5b; +op3val:0x3bb5; valaddr_reg:x8; val_offset:2877*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2877*FLEN/8, x10, x3, x5) + +inst_982: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x313 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x05b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3b5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b13; op2val:0xbc5b; +op3val:0x3bb5; valaddr_reg:x8; val_offset:2880*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2880*FLEN/8, x10, x3, x5) + +inst_983: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x313 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x05b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3b5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b13; op2val:0xbc5b; +op3val:0x3bb5; valaddr_reg:x8; val_offset:2883*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2883*FLEN/8, x10, x3, x5) + +inst_984: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x313 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x05b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3b5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b13; op2val:0xbc5b; +op3val:0x3bb5; valaddr_reg:x8; val_offset:2886*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2886*FLEN/8, x10, x3, x5) + +inst_985: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x081 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x199 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x24e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3481; op2val:0xc199; +op3val:0x3a4e; valaddr_reg:x8; val_offset:2889*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2889*FLEN/8, x10, x3, x5) + +inst_986: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x081 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x199 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x24e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3481; op2val:0xc199; +op3val:0x3a4e; valaddr_reg:x8; val_offset:2892*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2892*FLEN/8, x10, x3, x5) + +inst_987: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x081 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x199 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x24e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3481; op2val:0xc199; +op3val:0x3a4e; valaddr_reg:x8; val_offset:2895*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2895*FLEN/8, x10, x3, x5) + +inst_988: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x081 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x199 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x24e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3481; op2val:0xc199; +op3val:0x3a4e; valaddr_reg:x8; val_offset:2898*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2898*FLEN/8, x10, x3, x5) + +inst_989: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x081 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x199 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x24e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3481; op2val:0xc199; +op3val:0x3a4e; valaddr_reg:x8; val_offset:2901*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2901*FLEN/8, x10, x3, x5) + +inst_990: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x17c and fs2 == 1 and fe2 == 0x0a and fm2 == 0x052 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x1e9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x397c; op2val:0xa852; +op3val:0x25e9; valaddr_reg:x8; val_offset:2904*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2904*FLEN/8, x10, x3, x5) + +inst_991: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x17c and fs2 == 1 and fe2 == 0x0a and fm2 == 0x052 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x1e9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x397c; op2val:0xa852; +op3val:0x25e9; valaddr_reg:x8; val_offset:2907*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2907*FLEN/8, x10, x3, x5) + +inst_992: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x17c and fs2 == 1 and fe2 == 0x0a and fm2 == 0x052 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x1e9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x397c; op2val:0xa852; +op3val:0x25e9; valaddr_reg:x8; val_offset:2910*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2910*FLEN/8, x10, x3, x5) + +inst_993: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x17c and fs2 == 1 and fe2 == 0x0a and fm2 == 0x052 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x1e9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x397c; op2val:0xa852; +op3val:0x25e9; valaddr_reg:x8; val_offset:2913*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2913*FLEN/8, x10, x3, x5) + +inst_994: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x17c and fs2 == 1 and fe2 == 0x0a and fm2 == 0x052 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x1e9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x397c; op2val:0xa852; +op3val:0x25e9; valaddr_reg:x8; val_offset:2916*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2916*FLEN/8, x10, x3, x5) + +inst_995: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x039 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3f4 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x032 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3439; op2val:0xbbf4; +op3val:0x3432; valaddr_reg:x8; val_offset:2919*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2919*FLEN/8, x10, x3, x5) + +inst_996: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x039 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3f4 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x032 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3439; op2val:0xbbf4; +op3val:0x3432; valaddr_reg:x8; val_offset:2922*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2922*FLEN/8, x10, x3, x5) + +inst_997: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x039 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3f4 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x032 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3439; op2val:0xbbf4; +op3val:0x3432; valaddr_reg:x8; val_offset:2925*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2925*FLEN/8, x10, x3, x5) + +inst_998: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x039 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3f4 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x032 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3439; op2val:0xbbf4; +op3val:0x3432; valaddr_reg:x8; val_offset:2928*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2928*FLEN/8, x10, x3, x5) + +inst_999: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x039 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3f4 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x032 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3439; op2val:0xbbf4; +op3val:0x3432; valaddr_reg:x8; val_offset:2931*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2931*FLEN/8, x10, x3, x5) + +inst_1000: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2c9 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2c7 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36c9; op2val:0xbac7; +op3val:0x35c0; valaddr_reg:x8; val_offset:2934*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2934*FLEN/8, x10, x3, x5) + +inst_1001: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2c9 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2c7 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1c0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36c9; op2val:0xbac7; +op3val:0x35c0; valaddr_reg:x8; val_offset:2937*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2937*FLEN/8, x10, x3, x5) + +inst_1002: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2c9 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2c7 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1c0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36c9; op2val:0xbac7; +op3val:0x35c0; valaddr_reg:x8; val_offset:2940*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2940*FLEN/8, x10, x3, x5) + +inst_1003: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2c9 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2c7 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1c0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36c9; op2val:0xbac7; +op3val:0x35c0; valaddr_reg:x8; val_offset:2943*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2943*FLEN/8, x10, x3, x5) + +inst_1004: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2c9 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2c7 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1c0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36c9; op2val:0xbac7; +op3val:0x35c0; valaddr_reg:x8; val_offset:2946*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2946*FLEN/8, x10, x3, x5) + +inst_1005: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e9 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x211 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3be9; op2val:0xb211; +op3val:0x31ff; valaddr_reg:x8; val_offset:2949*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2949*FLEN/8, x10, x3, x5) + +inst_1006: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e9 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x211 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3be9; op2val:0xb211; +op3val:0x31ff; valaddr_reg:x8; val_offset:2952*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2952*FLEN/8, x10, x3, x5) + +inst_1007: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e9 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x211 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3be9; op2val:0xb211; +op3val:0x31ff; valaddr_reg:x8; val_offset:2955*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2955*FLEN/8, x10, x3, x5) + +inst_1008: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e9 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x211 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3be9; op2val:0xb211; +op3val:0x31ff; valaddr_reg:x8; val_offset:2958*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2958*FLEN/8, x10, x3, x5) + +inst_1009: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e9 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x211 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3be9; op2val:0xb211; +op3val:0x31ff; valaddr_reg:x8; val_offset:2961*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2961*FLEN/8, x10, x3, x5) + +inst_1010: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x15e and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2f0 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x0a7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x395e; op2val:0xb2f0; +op3val:0x30a7; valaddr_reg:x8; val_offset:2964*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2964*FLEN/8, x10, x3, x5) + +inst_1011: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x15e and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2f0 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x0a7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x395e; op2val:0xb2f0; +op3val:0x30a7; valaddr_reg:x8; val_offset:2967*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2967*FLEN/8, x10, x3, x5) + +inst_1012: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x15e and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2f0 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x0a7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x395e; op2val:0xb2f0; +op3val:0x30a7; valaddr_reg:x8; val_offset:2970*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2970*FLEN/8, x10, x3, x5) + +inst_1013: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x15e and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2f0 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x0a7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x395e; op2val:0xb2f0; +op3val:0x30a7; valaddr_reg:x8; val_offset:2973*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2973*FLEN/8, x10, x3, x5) + +inst_1014: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x15e and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2f0 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x0a7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x395e; op2val:0xb2f0; +op3val:0x30a7; valaddr_reg:x8; val_offset:2976*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2976*FLEN/8, x10, x3, x5) + +inst_1015: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0af and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0db and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1ae and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38af; op2val:0xb0db; +op3val:0x2dae; valaddr_reg:x8; val_offset:2979*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2979*FLEN/8, x10, x3, x5) + +inst_1016: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0af and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0db and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1ae and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38af; op2val:0xb0db; +op3val:0x2dae; valaddr_reg:x8; val_offset:2982*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2982*FLEN/8, x10, x3, x5) + +inst_1017: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0af and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0db and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1ae and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38af; op2val:0xb0db; +op3val:0x2dae; valaddr_reg:x8; val_offset:2985*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2985*FLEN/8, x10, x3, x5) + +inst_1018: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0af and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0db and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1ae and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38af; op2val:0xb0db; +op3val:0x2dae; valaddr_reg:x8; val_offset:2988*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2988*FLEN/8, x10, x3, x5) + +inst_1019: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0af and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0db and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1ae and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38af; op2val:0xb0db; +op3val:0x2dae; valaddr_reg:x8; val_offset:2991*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2991*FLEN/8, x10, x3, x5) + +inst_1020: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x09 and fm2 == 0x10d and fs3 == 0 and fe3 == 0x09 and fm3 == 0x108 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bff; op2val:0xa50d; +op3val:0x2508; valaddr_reg:x8; val_offset:2994*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2994*FLEN/8, x10, x3, x5) + +inst_1021: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x09 and fm2 == 0x10d and fs3 == 0 and fe3 == 0x09 and fm3 == 0x108 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bff; op2val:0xa50d; +op3val:0x2508; valaddr_reg:x8; val_offset:2997*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2997*FLEN/8, x10, x3, x5) + +inst_1022: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x09 and fm2 == 0x10d and fs3 == 0 and fe3 == 0x09 and fm3 == 0x108 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bff; op2val:0xa50d; +op3val:0x2508; valaddr_reg:x8; val_offset:3000*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3000*FLEN/8, x10, x3, x5) + +inst_1023: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x09 and fm2 == 0x10d and fs3 == 0 and fe3 == 0x09 and fm3 == 0x108 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bff; op2val:0xa50d; +op3val:0x2508; valaddr_reg:x8; val_offset:3003*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3003*FLEN/8, x10, x3, x5) + +inst_1024: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x09 and fm2 == 0x10d and fs3 == 0 and fe3 == 0x09 and fm3 == 0x108 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bff; op2val:0xa50d; +op3val:0x2508; valaddr_reg:x8; val_offset:3006*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3006*FLEN/8, x10, x3, x5) + +inst_1025: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x33b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x053 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3d3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b3b; op2val:0xb853; +op3val:0x37d3; valaddr_reg:x8; val_offset:3009*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3009*FLEN/8, x10, x3, x5) + +inst_1026: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x33b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x053 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3d3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b3b; op2val:0xb853; +op3val:0x37d3; valaddr_reg:x8; val_offset:3012*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3012*FLEN/8, x10, x3, x5) + +inst_1027: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x33b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x053 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3d3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b3b; op2val:0xb853; +op3val:0x37d3; valaddr_reg:x8; val_offset:3015*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3015*FLEN/8, x10, x3, x5) + +inst_1028: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x33b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x053 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3d3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b3b; op2val:0xb853; +op3val:0x37d3; valaddr_reg:x8; val_offset:3018*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3018*FLEN/8, x10, x3, x5) + +inst_1029: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x33b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x053 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3d3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b3b; op2val:0xb853; +op3val:0x37d3; valaddr_reg:x8; val_offset:3021*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3021*FLEN/8, x10, x3, x5) + +inst_1030: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x025 and fs2 == 1 and fe2 == 0x09 and fm2 == 0x2d2 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x30a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3825; op2val:0xa6d2; +op3val:0x230a; valaddr_reg:x8; val_offset:3024*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3024*FLEN/8, x10, x3, x5) + +inst_1031: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x025 and fs2 == 1 and fe2 == 0x09 and fm2 == 0x2d2 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x30a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3825; op2val:0xa6d2; +op3val:0x230a; valaddr_reg:x8; val_offset:3027*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3027*FLEN/8, x10, x3, x5) + +inst_1032: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x025 and fs2 == 1 and fe2 == 0x09 and fm2 == 0x2d2 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x30a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3825; op2val:0xa6d2; +op3val:0x230a; valaddr_reg:x8; val_offset:3030*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3030*FLEN/8, x10, x3, x5) + +inst_1033: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x025 and fs2 == 1 and fe2 == 0x09 and fm2 == 0x2d2 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x30a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3825; op2val:0xa6d2; +op3val:0x230a; valaddr_reg:x8; val_offset:3033*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3033*FLEN/8, x10, x3, x5) + +inst_1034: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x025 and fs2 == 1 and fe2 == 0x09 and fm2 == 0x2d2 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x30a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3825; op2val:0xa6d2; +op3val:0x230a; valaddr_reg:x8; val_offset:3036*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3036*FLEN/8, x10, x3, x5) + +inst_1035: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x088 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x01e and fs3 == 0 and fe3 == 0x09 and fm3 == 0x0a6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3488; op2val:0xac1e; +op3val:0x24a6; valaddr_reg:x8; val_offset:3039*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3039*FLEN/8, x10, x3, x5) + +inst_1036: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x088 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x01e and fs3 == 0 and fe3 == 0x09 and fm3 == 0x0a6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3488; op2val:0xac1e; +op3val:0x24a6; valaddr_reg:x8; val_offset:3042*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3042*FLEN/8, x10, x3, x5) + +inst_1037: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x088 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x01e and fs3 == 0 and fe3 == 0x09 and fm3 == 0x0a6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3488; op2val:0xac1e; +op3val:0x24a6; valaddr_reg:x8; val_offset:3045*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3045*FLEN/8, x10, x3, x5) + +inst_1038: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x088 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x01e and fs3 == 0 and fe3 == 0x09 and fm3 == 0x0a6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3488; op2val:0xac1e; +op3val:0x24a6; valaddr_reg:x8; val_offset:3048*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3048*FLEN/8, x10, x3, x5) + +inst_1039: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x088 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x01e and fs3 == 0 and fe3 == 0x09 and fm3 == 0x0a6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3488; op2val:0xac1e; +op3val:0x24a6; valaddr_reg:x8; val_offset:3051*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3051*FLEN/8, x10, x3, x5) + +inst_1040: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x209 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x218 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x099 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e09; op2val:0xc618; +op3val:0x3899; valaddr_reg:x8; val_offset:3054*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3054*FLEN/8, x10, x3, x5) + +inst_1041: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x209 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x218 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x099 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e09; op2val:0xc618; +op3val:0x3899; valaddr_reg:x8; val_offset:3057*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3057*FLEN/8, x10, x3, x5) + +inst_1042: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x209 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x218 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x099 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e09; op2val:0xc618; +op3val:0x3899; valaddr_reg:x8; val_offset:3060*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3060*FLEN/8, x10, x3, x5) + +inst_1043: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x209 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x218 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x099 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e09; op2val:0xc618; +op3val:0x3899; valaddr_reg:x8; val_offset:3063*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3063*FLEN/8, x10, x3, x5) + +inst_1044: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x209 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x218 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x099 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e09; op2val:0xc618; +op3val:0x3899; valaddr_reg:x8; val_offset:3066*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3066*FLEN/8, x10, x3, x5) + +inst_1045: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d1 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x002 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2d5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ad1; op2val:0xbc02; +op3val:0x3ad5; valaddr_reg:x8; val_offset:3069*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3069*FLEN/8, x10, x3, x5) + +inst_1046: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d1 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x002 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2d5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ad1; op2val:0xbc02; +op3val:0x3ad5; valaddr_reg:x8; val_offset:3072*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3072*FLEN/8, x10, x3, x5) + +inst_1047: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d1 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x002 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2d5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ad1; op2val:0xbc02; +op3val:0x3ad5; valaddr_reg:x8; val_offset:3075*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3075*FLEN/8, x10, x3, x5) +RVTEST_SIGBASE(x3,signature_x3_8) + +inst_1048: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d1 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x002 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2d5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ad1; op2val:0xbc02; +op3val:0x3ad5; valaddr_reg:x8; val_offset:3078*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3078*FLEN/8, x10, x3, x5) + +inst_1049: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d1 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x002 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2d5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ad1; op2val:0xbc02; +op3val:0x3ad5; valaddr_reg:x8; val_offset:3081*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3081*FLEN/8, x10, x3, x5) + +inst_1050: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0a6 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x162 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x23f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34a6; op2val:0xb162; +op3val:0x2a3f; valaddr_reg:x8; val_offset:3084*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3084*FLEN/8, x10, x3, x5) + +inst_1051: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0a6 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x162 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x23f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34a6; op2val:0xb162; +op3val:0x2a3f; valaddr_reg:x8; val_offset:3087*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3087*FLEN/8, x10, x3, x5) + +inst_1052: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0a6 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x162 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x23f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34a6; op2val:0xb162; +op3val:0x2a3f; valaddr_reg:x8; val_offset:3090*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3090*FLEN/8, x10, x3, x5) + +inst_1053: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0a6 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x162 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x23f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34a6; op2val:0xb162; +op3val:0x2a3f; valaddr_reg:x8; val_offset:3093*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3093*FLEN/8, x10, x3, x5) + +inst_1054: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0a6 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x162 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x23f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34a6; op2val:0xb162; +op3val:0x2a3f; valaddr_reg:x8; val_offset:3096*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3096*FLEN/8, x10, x3, x5) + +inst_1055: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x15c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3ce and fs3 == 0 and fe3 == 0x0e and fm3 == 0x13a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x355c; op2val:0xbfce; +op3val:0x393a; valaddr_reg:x8; val_offset:3099*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3099*FLEN/8, x10, x3, x5) + +inst_1056: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x15c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3ce and fs3 == 0 and fe3 == 0x0e and fm3 == 0x13a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x355c; op2val:0xbfce; +op3val:0x393a; valaddr_reg:x8; val_offset:3102*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3102*FLEN/8, x10, x3, x5) + +inst_1057: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x15c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3ce and fs3 == 0 and fe3 == 0x0e and fm3 == 0x13a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x355c; op2val:0xbfce; +op3val:0x393a; valaddr_reg:x8; val_offset:3105*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3105*FLEN/8, x10, x3, x5) + +inst_1058: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x15c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3ce and fs3 == 0 and fe3 == 0x0e and fm3 == 0x13a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x355c; op2val:0xbfce; +op3val:0x393a; valaddr_reg:x8; val_offset:3108*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3108*FLEN/8, x10, x3, x5) + +inst_1059: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x15c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3ce and fs3 == 0 and fe3 == 0x0e and fm3 == 0x13a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x355c; op2val:0xbfce; +op3val:0x393a; valaddr_reg:x8; val_offset:3111*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3111*FLEN/8, x10, x3, x5) + +inst_1060: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x271 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2d1 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x17d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3671; op2val:0xbad1; +op3val:0x357d; valaddr_reg:x8; val_offset:3114*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3114*FLEN/8, x10, x3, x5) + +inst_1061: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x271 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2d1 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x17d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3671; op2val:0xbad1; +op3val:0x357d; valaddr_reg:x8; val_offset:3117*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3117*FLEN/8, x10, x3, x5) + +inst_1062: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x271 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2d1 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x17d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3671; op2val:0xbad1; +op3val:0x357d; valaddr_reg:x8; val_offset:3120*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3120*FLEN/8, x10, x3, x5) + +inst_1063: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x271 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2d1 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x17d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3671; op2val:0xbad1; +op3val:0x357d; valaddr_reg:x8; val_offset:3123*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3123*FLEN/8, x10, x3, x5) + +inst_1064: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x271 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2d1 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x17d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3671; op2val:0xbad1; +op3val:0x357d; valaddr_reg:x8; val_offset:3126*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3126*FLEN/8, x10, x3, x5) + +inst_1065: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1f9 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x28e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0e5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39f9; op2val:0xb68e; +op3val:0x34e5; valaddr_reg:x8; val_offset:3129*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3129*FLEN/8, x10, x3, x5) + +inst_1066: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1f9 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x28e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0e5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39f9; op2val:0xb68e; +op3val:0x34e5; valaddr_reg:x8; val_offset:3132*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3132*FLEN/8, x10, x3, x5) + +inst_1067: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1f9 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x28e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0e5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39f9; op2val:0xb68e; +op3val:0x34e5; valaddr_reg:x8; val_offset:3135*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3135*FLEN/8, x10, x3, x5) + +inst_1068: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1f9 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x28e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0e5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39f9; op2val:0xb68e; +op3val:0x34e5; valaddr_reg:x8; val_offset:3138*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3138*FLEN/8, x10, x3, x5) + +inst_1069: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1f9 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x28e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0e5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39f9; op2val:0xb68e; +op3val:0x34e5; valaddr_reg:x8; val_offset:3141*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3141*FLEN/8, x10, x3, x5) + +inst_1070: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x268 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0db and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3c7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a68; op2val:0xbcdb; +op3val:0x3bc7; valaddr_reg:x8; val_offset:3144*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3144*FLEN/8, x10, x3, x5) + +inst_1071: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x268 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0db and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3c7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a68; op2val:0xbcdb; +op3val:0x3bc7; valaddr_reg:x8; val_offset:3147*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3147*FLEN/8, x10, x3, x5) + +inst_1072: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x268 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0db and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3c7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a68; op2val:0xbcdb; +op3val:0x3bc7; valaddr_reg:x8; val_offset:3150*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3150*FLEN/8, x10, x3, x5) + +inst_1073: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x268 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0db and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3c7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a68; op2val:0xbcdb; +op3val:0x3bc7; valaddr_reg:x8; val_offset:3153*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3153*FLEN/8, x10, x3, x5) + +inst_1074: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x268 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0db and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3c7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a68; op2val:0xbcdb; +op3val:0x3bc7; valaddr_reg:x8; val_offset:3156*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3156*FLEN/8, x10, x3, x5) + +inst_1075: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x37c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x060 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x018 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b7c; op2val:0xb860; +op3val:0x3818; valaddr_reg:x8; val_offset:3159*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3159*FLEN/8, x10, x3, x5) + +inst_1076: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x37c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x060 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x018 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b7c; op2val:0xb860; +op3val:0x3818; valaddr_reg:x8; val_offset:3162*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3162*FLEN/8, x10, x3, x5) + +inst_1077: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x37c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x060 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x018 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b7c; op2val:0xb860; +op3val:0x3818; valaddr_reg:x8; val_offset:3165*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3165*FLEN/8, x10, x3, x5) + +inst_1078: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x37c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x060 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x018 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b7c; op2val:0xb860; +op3val:0x3818; valaddr_reg:x8; val_offset:3168*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3168*FLEN/8, x10, x3, x5) + +inst_1079: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x37c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x060 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x018 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b7c; op2val:0xb860; +op3val:0x3818; valaddr_reg:x8; val_offset:3171*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3171*FLEN/8, x10, x3, x5) + +inst_1080: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0dd and fs2 == 1 and fe2 == 0x10 and fm2 == 0x118 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x232 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34dd; op2val:0xc118; +op3val:0x3a32; valaddr_reg:x8; val_offset:3174*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3174*FLEN/8, x10, x3, x5) + +inst_1081: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0dd and fs2 == 1 and fe2 == 0x10 and fm2 == 0x118 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x232 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34dd; op2val:0xc118; +op3val:0x3a32; valaddr_reg:x8; val_offset:3177*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3177*FLEN/8, x10, x3, x5) + +inst_1082: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0dd and fs2 == 1 and fe2 == 0x10 and fm2 == 0x118 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x232 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34dd; op2val:0xc118; +op3val:0x3a32; valaddr_reg:x8; val_offset:3180*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3180*FLEN/8, x10, x3, x5) + +inst_1083: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0dd and fs2 == 1 and fe2 == 0x10 and fm2 == 0x118 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x232 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34dd; op2val:0xc118; +op3val:0x3a32; valaddr_reg:x8; val_offset:3183*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3183*FLEN/8, x10, x3, x5) + +inst_1084: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0dd and fs2 == 1 and fe2 == 0x10 and fm2 == 0x118 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x232 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34dd; op2val:0xc118; +op3val:0x3a32; valaddr_reg:x8; val_offset:3186*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3186*FLEN/8, x10, x3, x5) + +inst_1085: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x012 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0e9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38d3; op2val:0xb812; +op3val:0x34e9; valaddr_reg:x8; val_offset:3189*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3189*FLEN/8, x10, x3, x5) + +inst_1086: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x012 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0e9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38d3; op2val:0xb812; +op3val:0x34e9; valaddr_reg:x8; val_offset:3192*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3192*FLEN/8, x10, x3, x5) + +inst_1087: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x012 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0e9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38d3; op2val:0xb812; +op3val:0x34e9; valaddr_reg:x8; val_offset:3195*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3195*FLEN/8, x10, x3, x5) + +inst_1088: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x012 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0e9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38d3; op2val:0xb812; +op3val:0x34e9; valaddr_reg:x8; val_offset:3198*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3198*FLEN/8, x10, x3, x5) + +inst_1089: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x012 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0e9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38d3; op2val:0xb812; +op3val:0x34e9; valaddr_reg:x8; val_offset:3201*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3201*FLEN/8, x10, x3, x5) + +inst_1090: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1e5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x12f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3a4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39e5; op2val:0xb92f; +op3val:0x37a4; valaddr_reg:x8; val_offset:3204*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3204*FLEN/8, x10, x3, x5) + +inst_1091: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1e5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x12f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3a4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39e5; op2val:0xb92f; +op3val:0x37a4; valaddr_reg:x8; val_offset:3207*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3207*FLEN/8, x10, x3, x5) + +inst_1092: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1e5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x12f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3a4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39e5; op2val:0xb92f; +op3val:0x37a4; valaddr_reg:x8; val_offset:3210*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3210*FLEN/8, x10, x3, x5) + +inst_1093: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1e5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x12f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3a4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39e5; op2val:0xb92f; +op3val:0x37a4; valaddr_reg:x8; val_offset:3213*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3213*FLEN/8, x10, x3, x5) + +inst_1094: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1e5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x12f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3a4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39e5; op2val:0xb92f; +op3val:0x37a4; valaddr_reg:x8; val_offset:3216*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3216*FLEN/8, x10, x3, x5) + +inst_1095: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x25a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1fb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x365a; op2val:0xbdfb; +op3val:0x38c0; valaddr_reg:x8; val_offset:3219*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3219*FLEN/8, x10, x3, x5) + +inst_1096: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x25a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1fb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0c0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x365a; op2val:0xbdfb; +op3val:0x38c0; valaddr_reg:x8; val_offset:3222*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3222*FLEN/8, x10, x3, x5) + +inst_1097: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x25a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1fb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0c0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x365a; op2val:0xbdfb; +op3val:0x38c0; valaddr_reg:x8; val_offset:3225*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3225*FLEN/8, x10, x3, x5) + +inst_1098: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x25a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1fb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0c0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x365a; op2val:0xbdfb; +op3val:0x38c0; valaddr_reg:x8; val_offset:3228*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3228*FLEN/8, x10, x3, x5) + +inst_1099: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x25a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1fb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0c0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x365a; op2val:0xbdfb; +op3val:0x38c0; valaddr_reg:x8; val_offset:3231*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3231*FLEN/8, x10, x3, x5) + +inst_1100: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x236 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0ea and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a55; op2val:0xb636; +op3val:0x34ea; valaddr_reg:x8; val_offset:3234*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3234*FLEN/8, x10, x3, x5) + +inst_1101: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x236 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0ea and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a55; op2val:0xb636; +op3val:0x34ea; valaddr_reg:x8; val_offset:3237*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3237*FLEN/8, x10, x3, x5) + +inst_1102: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x236 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0ea and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a55; op2val:0xb636; +op3val:0x34ea; valaddr_reg:x8; val_offset:3240*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3240*FLEN/8, x10, x3, x5) + +inst_1103: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x236 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0ea and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a55; op2val:0xb636; +op3val:0x34ea; valaddr_reg:x8; val_offset:3243*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3243*FLEN/8, x10, x3, x5) + +inst_1104: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x236 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0ea and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a55; op2val:0xb636; +op3val:0x34ea; valaddr_reg:x8; val_offset:3246*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3246*FLEN/8, x10, x3, x5) + +inst_1105: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0c8 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x16c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x27d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34c8; op2val:0xc16c; +op3val:0x3a7d; valaddr_reg:x8; val_offset:3249*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3249*FLEN/8, x10, x3, x5) + +inst_1106: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0c8 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x16c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x27d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34c8; op2val:0xc16c; +op3val:0x3a7d; valaddr_reg:x8; val_offset:3252*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3252*FLEN/8, x10, x3, x5) + +inst_1107: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0c8 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x16c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x27d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34c8; op2val:0xc16c; +op3val:0x3a7d; valaddr_reg:x8; val_offset:3255*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3255*FLEN/8, x10, x3, x5) + +inst_1108: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0c8 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x16c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x27d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34c8; op2val:0xc16c; +op3val:0x3a7d; valaddr_reg:x8; val_offset:3258*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3258*FLEN/8, x10, x3, x5) + +inst_1109: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0c8 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x16c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x27d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34c8; op2val:0xc16c; +op3val:0x3a7d; valaddr_reg:x8; val_offset:3261*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3261*FLEN/8, x10, x3, x5) + +inst_1110: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x22a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x328 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x184 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x322a; op2val:0xbf28; +op3val:0x3584; valaddr_reg:x8; val_offset:3264*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3264*FLEN/8, x10, x3, x5) + +inst_1111: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x22a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x328 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x184 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x322a; op2val:0xbf28; +op3val:0x3584; valaddr_reg:x8; val_offset:3267*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3267*FLEN/8, x10, x3, x5) + +inst_1112: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x22a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x328 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x184 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x322a; op2val:0xbf28; +op3val:0x3584; valaddr_reg:x8; val_offset:3270*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3270*FLEN/8, x10, x3, x5) + +inst_1113: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x22a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x328 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x184 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x322a; op2val:0xbf28; +op3val:0x3584; valaddr_reg:x8; val_offset:3273*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3273*FLEN/8, x10, x3, x5) + +inst_1114: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x22a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x328 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x184 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x322a; op2val:0xbf28; +op3val:0x3584; valaddr_reg:x8; val_offset:3276*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3276*FLEN/8, x10, x3, x5) + +inst_1115: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x046 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x295 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x309 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3046; op2val:0xbe95; +op3val:0x3309; valaddr_reg:x8; val_offset:3279*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3279*FLEN/8, x10, x3, x5) + +inst_1116: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x046 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x295 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x309 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3046; op2val:0xbe95; +op3val:0x3309; valaddr_reg:x8; val_offset:3282*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3282*FLEN/8, x10, x3, x5) + +inst_1117: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x046 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x295 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x309 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3046; op2val:0xbe95; +op3val:0x3309; valaddr_reg:x8; val_offset:3285*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3285*FLEN/8, x10, x3, x5) + +inst_1118: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x046 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x295 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x309 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3046; op2val:0xbe95; +op3val:0x3309; valaddr_reg:x8; val_offset:3288*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3288*FLEN/8, x10, x3, x5) + +inst_1119: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x046 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x295 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x309 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3046; op2val:0xbe95; +op3val:0x3309; valaddr_reg:x8; val_offset:3291*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3291*FLEN/8, x10, x3, x5) + +inst_1120: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x00b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x07f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x08c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x380b; op2val:0xb87f; +op3val:0x348c; valaddr_reg:x8; val_offset:3294*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3294*FLEN/8, x10, x3, x5) + +inst_1121: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x00b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x07f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x08c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x380b; op2val:0xb87f; +op3val:0x348c; valaddr_reg:x8; val_offset:3297*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3297*FLEN/8, x10, x3, x5) + +inst_1122: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x00b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x07f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x08c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x380b; op2val:0xb87f; +op3val:0x348c; valaddr_reg:x8; val_offset:3300*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3300*FLEN/8, x10, x3, x5) + +inst_1123: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x00b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x07f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x08c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x380b; op2val:0xb87f; +op3val:0x348c; valaddr_reg:x8; val_offset:3303*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3303*FLEN/8, x10, x3, x5) + +inst_1124: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x00b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x07f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x08c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x380b; op2val:0xb87f; +op3val:0x348c; valaddr_reg:x8; val_offset:3306*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3306*FLEN/8, x10, x3, x5) + +inst_1125: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x17b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x00b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x18b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x397b; op2val:0xb80b; +op3val:0x358b; valaddr_reg:x8; val_offset:3309*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3309*FLEN/8, x10, x3, x5) + +inst_1126: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x17b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x00b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x18b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x397b; op2val:0xb80b; +op3val:0x358b; valaddr_reg:x8; val_offset:3312*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3312*FLEN/8, x10, x3, x5) + +inst_1127: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x17b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x00b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x18b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x397b; op2val:0xb80b; +op3val:0x358b; valaddr_reg:x8; val_offset:3315*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3315*FLEN/8, x10, x3, x5) + +inst_1128: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x17b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x00b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x18b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x397b; op2val:0xb80b; +op3val:0x358b; valaddr_reg:x8; val_offset:3318*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3318*FLEN/8, x10, x3, x5) + +inst_1129: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x17b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x00b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x18b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x397b; op2val:0xb80b; +op3val:0x358b; valaddr_reg:x8; val_offset:3321*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3321*FLEN/8, x10, x3, x5) + +inst_1130: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x357 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1b4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x13b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b57; op2val:0xb9b4; +op3val:0x393b; valaddr_reg:x8; val_offset:3324*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3324*FLEN/8, x10, x3, x5) + +inst_1131: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x357 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1b4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x13b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b57; op2val:0xb9b4; +op3val:0x393b; valaddr_reg:x8; val_offset:3327*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3327*FLEN/8, x10, x3, x5) + +inst_1132: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x357 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1b4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x13b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b57; op2val:0xb9b4; +op3val:0x393b; valaddr_reg:x8; val_offset:3330*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3330*FLEN/8, x10, x3, x5) + +inst_1133: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x357 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1b4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x13b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b57; op2val:0xb9b4; +op3val:0x393b; valaddr_reg:x8; val_offset:3333*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3333*FLEN/8, x10, x3, x5) + +inst_1134: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x357 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1b4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x13b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b57; op2val:0xb9b4; +op3val:0x393b; valaddr_reg:x8; val_offset:3336*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3336*FLEN/8, x10, x3, x5) + +inst_1135: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3e7 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x36b and fs3 == 0 and fe3 == 0x0b and fm3 == 0x353 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37e7; op2val:0xb36b; +op3val:0x2f53; valaddr_reg:x8; val_offset:3339*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3339*FLEN/8, x10, x3, x5) + +inst_1136: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3e7 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x36b and fs3 == 0 and fe3 == 0x0b and fm3 == 0x353 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37e7; op2val:0xb36b; +op3val:0x2f53; valaddr_reg:x8; val_offset:3342*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3342*FLEN/8, x10, x3, x5) + +inst_1137: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3e7 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x36b and fs3 == 0 and fe3 == 0x0b and fm3 == 0x353 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37e7; op2val:0xb36b; +op3val:0x2f53; valaddr_reg:x8; val_offset:3345*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3345*FLEN/8, x10, x3, x5) + +inst_1138: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3e7 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x36b and fs3 == 0 and fe3 == 0x0b and fm3 == 0x353 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37e7; op2val:0xb36b; +op3val:0x2f53; valaddr_reg:x8; val_offset:3348*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3348*FLEN/8, x10, x3, x5) + +inst_1139: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3e7 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x36b and fs3 == 0 and fe3 == 0x0b and fm3 == 0x353 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37e7; op2val:0xb36b; +op3val:0x2f53; valaddr_reg:x8; val_offset:3351*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3351*FLEN/8, x10, x3, x5) + +inst_1140: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x10f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x09c and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1d3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x350f; op2val:0xb49c; +op3val:0x2dd3; valaddr_reg:x8; val_offset:3354*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3354*FLEN/8, x10, x3, x5) + +inst_1141: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x10f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x09c and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1d3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x350f; op2val:0xb49c; +op3val:0x2dd3; valaddr_reg:x8; val_offset:3357*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3357*FLEN/8, x10, x3, x5) + +inst_1142: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x10f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x09c and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1d3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x350f; op2val:0xb49c; +op3val:0x2dd3; valaddr_reg:x8; val_offset:3360*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3360*FLEN/8, x10, x3, x5) + +inst_1143: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x10f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x09c and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1d3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x350f; op2val:0xb49c; +op3val:0x2dd3; valaddr_reg:x8; val_offset:3363*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3363*FLEN/8, x10, x3, x5) + +inst_1144: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x10f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x09c and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1d3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x350f; op2val:0xb49c; +op3val:0x2dd3; valaddr_reg:x8; val_offset:3366*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3366*FLEN/8, x10, x3, x5) + +inst_1145: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x02f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x332 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x382 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x302f; op2val:0xb332; +op3val:0x2782; valaddr_reg:x8; val_offset:3369*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3369*FLEN/8, x10, x3, x5) + +inst_1146: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x02f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x332 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x382 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x302f; op2val:0xb332; +op3val:0x2782; valaddr_reg:x8; val_offset:3372*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3372*FLEN/8, x10, x3, x5) + +inst_1147: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x02f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x332 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x382 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x302f; op2val:0xb332; +op3val:0x2782; valaddr_reg:x8; val_offset:3375*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3375*FLEN/8, x10, x3, x5) + +inst_1148: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x02f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x332 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x382 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x302f; op2val:0xb332; +op3val:0x2782; valaddr_reg:x8; val_offset:3378*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3378*FLEN/8, x10, x3, x5) + +inst_1149: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x02f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x332 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x382 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x302f; op2val:0xb332; +op3val:0x2782; valaddr_reg:x8; val_offset:3381*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3381*FLEN/8, x10, x3, x5) + +inst_1150: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x21e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x002 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x221 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x361e; op2val:0xbc02; +op3val:0x3621; valaddr_reg:x8; val_offset:3384*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3384*FLEN/8, x10, x3, x5) + +inst_1151: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x21e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x002 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x221 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x361e; op2val:0xbc02; +op3val:0x3621; valaddr_reg:x8; val_offset:3387*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3387*FLEN/8, x10, x3, x5) + +inst_1152: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x21e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x002 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x221 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x361e; op2val:0xbc02; +op3val:0x3621; valaddr_reg:x8; val_offset:3390*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3390*FLEN/8, x10, x3, x5) + +inst_1153: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x21e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x002 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x221 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x361e; op2val:0xbc02; +op3val:0x3621; valaddr_reg:x8; val_offset:3393*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3393*FLEN/8, x10, x3, x5) + +inst_1154: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x21e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x002 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x221 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x361e; op2val:0xbc02; +op3val:0x3621; valaddr_reg:x8; val_offset:3396*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3396*FLEN/8, x10, x3, x5) + +inst_1155: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x03f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1dd and fs3 == 0 and fe3 == 0x0e and fm3 == 0x23b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x383f; op2val:0xbddd; +op3val:0x3a3b; valaddr_reg:x8; val_offset:3399*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3399*FLEN/8, x10, x3, x5) + +inst_1156: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x03f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1dd and fs3 == 0 and fe3 == 0x0e and fm3 == 0x23b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x383f; op2val:0xbddd; +op3val:0x3a3b; valaddr_reg:x8; val_offset:3402*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3402*FLEN/8, x10, x3, x5) + +inst_1157: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x03f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1dd and fs3 == 0 and fe3 == 0x0e and fm3 == 0x23b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x383f; op2val:0xbddd; +op3val:0x3a3b; valaddr_reg:x8; val_offset:3405*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3405*FLEN/8, x10, x3, x5) + +inst_1158: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x03f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1dd and fs3 == 0 and fe3 == 0x0e and fm3 == 0x23b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x383f; op2val:0xbddd; +op3val:0x3a3b; valaddr_reg:x8; val_offset:3408*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3408*FLEN/8, x10, x3, x5) + +inst_1159: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x03f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1dd and fs3 == 0 and fe3 == 0x0e and fm3 == 0x23b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x383f; op2val:0xbddd; +op3val:0x3a3b; valaddr_reg:x8; val_offset:3411*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3411*FLEN/8, x10, x3, x5) + +inst_1160: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x282 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3a9 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x23c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3282; op2val:0xbfa9; +op3val:0x363c; valaddr_reg:x8; val_offset:3414*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3414*FLEN/8, x10, x3, x5) + +inst_1161: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x282 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3a9 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x23c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3282; op2val:0xbfa9; +op3val:0x363c; valaddr_reg:x8; val_offset:3417*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3417*FLEN/8, x10, x3, x5) + +inst_1162: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x282 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3a9 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x23c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3282; op2val:0xbfa9; +op3val:0x363c; valaddr_reg:x8; val_offset:3420*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3420*FLEN/8, x10, x3, x5) + +inst_1163: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x282 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3a9 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x23c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3282; op2val:0xbfa9; +op3val:0x363c; valaddr_reg:x8; val_offset:3423*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3423*FLEN/8, x10, x3, x5) + +inst_1164: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x282 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3a9 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x23c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3282; op2val:0xbfa9; +op3val:0x363c; valaddr_reg:x8; val_offset:3426*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3426*FLEN/8, x10, x3, x5) + +inst_1165: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x341 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x214 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ab4; op2val:0xbb41; +op3val:0x3a14; valaddr_reg:x8; val_offset:3429*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3429*FLEN/8, x10, x3, x5) + +inst_1166: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x341 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x214 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ab4; op2val:0xbb41; +op3val:0x3a14; valaddr_reg:x8; val_offset:3432*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3432*FLEN/8, x10, x3, x5) + +inst_1167: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x341 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x214 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ab4; op2val:0xbb41; +op3val:0x3a14; valaddr_reg:x8; val_offset:3435*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3435*FLEN/8, x10, x3, x5) + +inst_1168: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x341 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x214 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ab4; op2val:0xbb41; +op3val:0x3a14; valaddr_reg:x8; val_offset:3438*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3438*FLEN/8, x10, x3, x5) + +inst_1169: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x341 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x214 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ab4; op2val:0xbb41; +op3val:0x3a14; valaddr_reg:x8; val_offset:3441*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3441*FLEN/8, x10, x3, x5) + +inst_1170: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1b2 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x070 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a3b; op2val:0xb5b2; +op3val:0x3470; valaddr_reg:x8; val_offset:3444*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3444*FLEN/8, x10, x3, x5) + +inst_1171: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1b2 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x070 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a3b; op2val:0xb5b2; +op3val:0x3470; valaddr_reg:x8; val_offset:3447*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3447*FLEN/8, x10, x3, x5) + +inst_1172: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1b2 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x070 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a3b; op2val:0xb5b2; +op3val:0x3470; valaddr_reg:x8; val_offset:3450*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3450*FLEN/8, x10, x3, x5) + +inst_1173: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1b2 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x070 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a3b; op2val:0xb5b2; +op3val:0x3470; valaddr_reg:x8; val_offset:3453*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3453*FLEN/8, x10, x3, x5) + +inst_1174: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1b2 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x070 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a3b; op2val:0xb5b2; +op3val:0x3470; valaddr_reg:x8; val_offset:3456*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3456*FLEN/8, x10, x3, x5) + +inst_1175: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x271 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3f0 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x264 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3671; op2val:0xbff0; +op3val:0x3a64; valaddr_reg:x8; val_offset:3459*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3459*FLEN/8, x10, x3, x5) +RVTEST_SIGBASE(x3,signature_x3_9) + +inst_1176: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x271 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3f0 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x264 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3671; op2val:0xbff0; +op3val:0x3a64; valaddr_reg:x8; val_offset:3462*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3462*FLEN/8, x10, x3, x5) + +inst_1177: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x271 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3f0 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x264 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3671; op2val:0xbff0; +op3val:0x3a64; valaddr_reg:x8; val_offset:3465*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3465*FLEN/8, x10, x3, x5) + +inst_1178: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x271 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3f0 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x264 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3671; op2val:0xbff0; +op3val:0x3a64; valaddr_reg:x8; val_offset:3468*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3468*FLEN/8, x10, x3, x5) + +inst_1179: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x271 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3f0 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x264 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3671; op2val:0xbff0; +op3val:0x3a64; valaddr_reg:x8; val_offset:3471*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3471*FLEN/8, x10, x3, x5) + +inst_1180: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x197 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34ff; op2val:0xbd97; +op3val:0x36fc; valaddr_reg:x8; val_offset:3474*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3474*FLEN/8, x10, x3, x5) + +inst_1181: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x197 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2fc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34ff; op2val:0xbd97; +op3val:0x36fc; valaddr_reg:x8; val_offset:3477*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3477*FLEN/8, x10, x3, x5) + +inst_1182: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x197 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2fc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34ff; op2val:0xbd97; +op3val:0x36fc; valaddr_reg:x8; val_offset:3480*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3480*FLEN/8, x10, x3, x5) + +inst_1183: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x197 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2fc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34ff; op2val:0xbd97; +op3val:0x36fc; valaddr_reg:x8; val_offset:3483*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3483*FLEN/8, x10, x3, x5) + +inst_1184: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x197 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2fc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34ff; op2val:0xbd97; +op3val:0x36fc; valaddr_reg:x8; val_offset:3486*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3486*FLEN/8, x10, x3, x5) + +inst_1185: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1de and fs2 == 1 and fe2 == 0x0e and fm2 == 0x20f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x071 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39de; op2val:0xba0f; +op3val:0x3871; valaddr_reg:x8; val_offset:3489*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3489*FLEN/8, x10, x3, x5) + +inst_1186: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1de and fs2 == 1 and fe2 == 0x0e and fm2 == 0x20f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x071 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39de; op2val:0xba0f; +op3val:0x3871; valaddr_reg:x8; val_offset:3492*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3492*FLEN/8, x10, x3, x5) + +inst_1187: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1de and fs2 == 1 and fe2 == 0x0e and fm2 == 0x20f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x071 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39de; op2val:0xba0f; +op3val:0x3871; valaddr_reg:x8; val_offset:3495*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3495*FLEN/8, x10, x3, x5) + +inst_1188: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1de and fs2 == 1 and fe2 == 0x0e and fm2 == 0x20f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x071 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39de; op2val:0xba0f; +op3val:0x3871; valaddr_reg:x8; val_offset:3498*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3498*FLEN/8, x10, x3, x5) + +inst_1189: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1de and fs2 == 1 and fe2 == 0x0e and fm2 == 0x20f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x071 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39de; op2val:0xba0f; +op3val:0x3871; valaddr_reg:x8; val_offset:3501*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3501*FLEN/8, x10, x3, x5) + +inst_1190: +// fs1 == 0 and fe1 == 0x07 and fm1 == 0x393 and fs2 == 1 and fe2 == 0x15 and fm2 == 0x342 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2df and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1f93; op2val:0xd742; +op3val:0x3adf; valaddr_reg:x8; val_offset:3504*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3504*FLEN/8, x10, x3, x5) + +inst_1191: +// fs1 == 0 and fe1 == 0x07 and fm1 == 0x393 and fs2 == 1 and fe2 == 0x15 and fm2 == 0x342 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2df and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1f93; op2val:0xd742; +op3val:0x3adf; valaddr_reg:x8; val_offset:3507*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3507*FLEN/8, x10, x3, x5) + +inst_1192: +// fs1 == 0 and fe1 == 0x07 and fm1 == 0x393 and fs2 == 1 and fe2 == 0x15 and fm2 == 0x342 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2df and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1f93; op2val:0xd742; +op3val:0x3adf; valaddr_reg:x8; val_offset:3510*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3510*FLEN/8, x10, x3, x5) + +inst_1193: +// fs1 == 0 and fe1 == 0x07 and fm1 == 0x393 and fs2 == 1 and fe2 == 0x15 and fm2 == 0x342 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2df and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1f93; op2val:0xd742; +op3val:0x3adf; valaddr_reg:x8; val_offset:3513*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3513*FLEN/8, x10, x3, x5) + +inst_1194: +// fs1 == 0 and fe1 == 0x07 and fm1 == 0x393 and fs2 == 1 and fe2 == 0x15 and fm2 == 0x342 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2df and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1f93; op2val:0xd742; +op3val:0x3adf; valaddr_reg:x8; val_offset:3516*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3516*FLEN/8, x10, x3, x5) + +inst_1195: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x21b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x042 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x27f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a1b; op2val:0xb842; +op3val:0x367f; valaddr_reg:x8; val_offset:3519*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3519*FLEN/8, x10, x3, x5) + +inst_1196: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x21b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x042 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x27f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a1b; op2val:0xb842; +op3val:0x367f; valaddr_reg:x8; val_offset:3522*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3522*FLEN/8, x10, x3, x5) + +inst_1197: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x21b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x042 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x27f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a1b; op2val:0xb842; +op3val:0x367f; valaddr_reg:x8; val_offset:3525*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3525*FLEN/8, x10, x3, x5) + +inst_1198: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x21b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x042 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x27f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a1b; op2val:0xb842; +op3val:0x367f; valaddr_reg:x8; val_offset:3528*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3528*FLEN/8, x10, x3, x5) + +inst_1199: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x21b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x042 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x27f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a1b; op2val:0xb842; +op3val:0x367f; valaddr_reg:x8; val_offset:3531*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3531*FLEN/8, x10, x3, x5) + +inst_1200: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x11f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3d6 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x103 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x311f; op2val:0xb7d6; +op3val:0x2d03; valaddr_reg:x8; val_offset:3534*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3534*FLEN/8, x10, x3, x5) + +inst_1201: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x11f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3d6 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x103 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x311f; op2val:0xb7d6; +op3val:0x2d03; valaddr_reg:x8; val_offset:3537*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3537*FLEN/8, x10, x3, x5) + +inst_1202: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x11f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3d6 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x103 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x311f; op2val:0xb7d6; +op3val:0x2d03; valaddr_reg:x8; val_offset:3540*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3540*FLEN/8, x10, x3, x5) + +inst_1203: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x11f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3d6 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x103 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x311f; op2val:0xb7d6; +op3val:0x2d03; valaddr_reg:x8; val_offset:3543*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3543*FLEN/8, x10, x3, x5) + +inst_1204: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x11f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3d6 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x103 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x311f; op2val:0xb7d6; +op3val:0x2d03; valaddr_reg:x8; val_offset:3546*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3546*FLEN/8, x10, x3, x5) + +inst_1205: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ce and fs2 == 1 and fe2 == 0x0d and fm2 == 0x228 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x365 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ce; op2val:0xb628; +op3val:0x3365; valaddr_reg:x8; val_offset:3549*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3549*FLEN/8, x10, x3, x5) + +inst_1206: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ce and fs2 == 1 and fe2 == 0x0d and fm2 == 0x228 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x365 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ce; op2val:0xb628; +op3val:0x3365; valaddr_reg:x8; val_offset:3552*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3552*FLEN/8, x10, x3, x5) + +inst_1207: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ce and fs2 == 1 and fe2 == 0x0d and fm2 == 0x228 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x365 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ce; op2val:0xb628; +op3val:0x3365; valaddr_reg:x8; val_offset:3555*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3555*FLEN/8, x10, x3, x5) + +inst_1208: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ce and fs2 == 1 and fe2 == 0x0d and fm2 == 0x228 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x365 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ce; op2val:0xb628; +op3val:0x3365; valaddr_reg:x8; val_offset:3558*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3558*FLEN/8, x10, x3, x5) + +inst_1209: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ce and fs2 == 1 and fe2 == 0x0d and fm2 == 0x228 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x365 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ce; op2val:0xb628; +op3val:0x3365; valaddr_reg:x8; val_offset:3561*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3561*FLEN/8, x10, x3, x5) + +inst_1210: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x30d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x192 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0e9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b0d; op2val:0xb992; +op3val:0x38e9; valaddr_reg:x8; val_offset:3564*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3564*FLEN/8, x10, x3, x5) + +inst_1211: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x30d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x192 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0e9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b0d; op2val:0xb992; +op3val:0x38e9; valaddr_reg:x8; val_offset:3567*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3567*FLEN/8, x10, x3, x5) + +inst_1212: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x30d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x192 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0e9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b0d; op2val:0xb992; +op3val:0x38e9; valaddr_reg:x8; val_offset:3570*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3570*FLEN/8, x10, x3, x5) + +inst_1213: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x30d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x192 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0e9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b0d; op2val:0xb992; +op3val:0x38e9; valaddr_reg:x8; val_offset:3573*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3573*FLEN/8, x10, x3, x5) + +inst_1214: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x30d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x192 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0e9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b0d; op2val:0xb992; +op3val:0x38e9; valaddr_reg:x8; val_offset:3576*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3576*FLEN/8, x10, x3, x5) + +inst_1215: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x094 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ae and fs3 == 0 and fe3 == 0x0d and fm3 == 0x15c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3094; op2val:0xc0ae; +op3val:0x355c; valaddr_reg:x8; val_offset:3579*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3579*FLEN/8, x10, x3, x5) + +inst_1216: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x094 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ae and fs3 == 0 and fe3 == 0x0d and fm3 == 0x15c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3094; op2val:0xc0ae; +op3val:0x355c; valaddr_reg:x8; val_offset:3582*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3582*FLEN/8, x10, x3, x5) + +inst_1217: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x094 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ae and fs3 == 0 and fe3 == 0x0d and fm3 == 0x15c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3094; op2val:0xc0ae; +op3val:0x355c; valaddr_reg:x8; val_offset:3585*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3585*FLEN/8, x10, x3, x5) + +inst_1218: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x094 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ae and fs3 == 0 and fe3 == 0x0d and fm3 == 0x15c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3094; op2val:0xc0ae; +op3val:0x355c; valaddr_reg:x8; val_offset:3588*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3588*FLEN/8, x10, x3, x5) + +inst_1219: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x094 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ae and fs3 == 0 and fe3 == 0x0d and fm3 == 0x15c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3094; op2val:0xc0ae; +op3val:0x355c; valaddr_reg:x8; val_offset:3591*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3591*FLEN/8, x10, x3, x5) + +inst_1220: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x06d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1ce and fs3 == 0 and fe3 == 0x0d and fm3 == 0x26c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x386d; op2val:0xb9ce; +op3val:0x366c; valaddr_reg:x8; val_offset:3594*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3594*FLEN/8, x10, x3, x5) + +inst_1221: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x06d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1ce and fs3 == 0 and fe3 == 0x0d and fm3 == 0x26c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x386d; op2val:0xb9ce; +op3val:0x366c; valaddr_reg:x8; val_offset:3597*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3597*FLEN/8, x10, x3, x5) + +inst_1222: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x06d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1ce and fs3 == 0 and fe3 == 0x0d and fm3 == 0x26c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x386d; op2val:0xb9ce; +op3val:0x366c; valaddr_reg:x8; val_offset:3600*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3600*FLEN/8, x10, x3, x5) + +inst_1223: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x06d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1ce and fs3 == 0 and fe3 == 0x0d and fm3 == 0x26c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x386d; op2val:0xb9ce; +op3val:0x366c; valaddr_reg:x8; val_offset:3603*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3603*FLEN/8, x10, x3, x5) + +inst_1224: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x06d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1ce and fs3 == 0 and fe3 == 0x0d and fm3 == 0x26c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x386d; op2val:0xb9ce; +op3val:0x366c; valaddr_reg:x8; val_offset:3606*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3606*FLEN/8, x10, x3, x5) + +inst_1225: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x019 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x30e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x33b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3819; op2val:0xbb0e; +op3val:0x373b; valaddr_reg:x8; val_offset:3609*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3609*FLEN/8, x10, x3, x5) + +inst_1226: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x019 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x30e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x33b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3819; op2val:0xbb0e; +op3val:0x373b; valaddr_reg:x8; val_offset:3612*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3612*FLEN/8, x10, x3, x5) + +inst_1227: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x019 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x30e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x33b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3819; op2val:0xbb0e; +op3val:0x373b; valaddr_reg:x8; val_offset:3615*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3615*FLEN/8, x10, x3, x5) + +inst_1228: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x019 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x30e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x33b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3819; op2val:0xbb0e; +op3val:0x373b; valaddr_reg:x8; val_offset:3618*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3618*FLEN/8, x10, x3, x5) + +inst_1229: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x019 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x30e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x33b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3819; op2val:0xbb0e; +op3val:0x373b; valaddr_reg:x8; val_offset:3621*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3621*FLEN/8, x10, x3, x5) + +inst_1230: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x36c and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2c1 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x240 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f6c; op2val:0xb2c1; +op3val:0x2640; valaddr_reg:x8; val_offset:3624*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3624*FLEN/8, x10, x3, x5) + +inst_1231: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x36c and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2c1 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x240 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f6c; op2val:0xb2c1; +op3val:0x2640; valaddr_reg:x8; val_offset:3627*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3627*FLEN/8, x10, x3, x5) + +inst_1232: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x36c and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2c1 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x240 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f6c; op2val:0xb2c1; +op3val:0x2640; valaddr_reg:x8; val_offset:3630*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3630*FLEN/8, x10, x3, x5) + +inst_1233: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x36c and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2c1 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x240 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f6c; op2val:0xb2c1; +op3val:0x2640; valaddr_reg:x8; val_offset:3633*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3633*FLEN/8, x10, x3, x5) + +inst_1234: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x36c and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2c1 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x240 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f6c; op2val:0xb2c1; +op3val:0x2640; valaddr_reg:x8; val_offset:3636*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3636*FLEN/8, x10, x3, x5) + +inst_1235: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x265 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0e7 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3d6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a65; op2val:0xb4e7; +op3val:0x33d6; valaddr_reg:x8; val_offset:3639*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3639*FLEN/8, x10, x3, x5) + +inst_1236: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x265 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0e7 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3d6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a65; op2val:0xb4e7; +op3val:0x33d6; valaddr_reg:x8; val_offset:3642*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3642*FLEN/8, x10, x3, x5) + +inst_1237: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x265 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0e7 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3d6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a65; op2val:0xb4e7; +op3val:0x33d6; valaddr_reg:x8; val_offset:3645*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3645*FLEN/8, x10, x3, x5) + +inst_1238: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x265 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0e7 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3d6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a65; op2val:0xb4e7; +op3val:0x33d6; valaddr_reg:x8; val_offset:3648*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3648*FLEN/8, x10, x3, x5) + +inst_1239: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x265 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0e7 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3d6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a65; op2val:0xb4e7; +op3val:0x33d6; valaddr_reg:x8; val_offset:3651*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3651*FLEN/8, x10, x3, x5) + +inst_1240: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x316 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x318 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x248 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2b16; op2val:0xc718; +op3val:0x3648; valaddr_reg:x8; val_offset:3654*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3654*FLEN/8, x10, x3, x5) + +inst_1241: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x316 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x318 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x248 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2b16; op2val:0xc718; +op3val:0x3648; valaddr_reg:x8; val_offset:3657*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3657*FLEN/8, x10, x3, x5) + +inst_1242: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x316 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x318 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x248 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2b16; op2val:0xc718; +op3val:0x3648; valaddr_reg:x8; val_offset:3660*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3660*FLEN/8, x10, x3, x5) + +inst_1243: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x316 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x318 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x248 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2b16; op2val:0xc718; +op3val:0x3648; valaddr_reg:x8; val_offset:3663*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3663*FLEN/8, x10, x3, x5) + +inst_1244: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x316 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x318 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x248 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2b16; op2val:0xc718; +op3val:0x3648; valaddr_reg:x8; val_offset:3666*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3666*FLEN/8, x10, x3, x5) + +inst_1245: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x106 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x105 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37fe; op2val:0xbd06; +op3val:0x3905; valaddr_reg:x8; val_offset:3669*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3669*FLEN/8, x10, x3, x5) + +inst_1246: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x106 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x105 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37fe; op2val:0xbd06; +op3val:0x3905; valaddr_reg:x8; val_offset:3672*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3672*FLEN/8, x10, x3, x5) + +inst_1247: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x106 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x105 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37fe; op2val:0xbd06; +op3val:0x3905; valaddr_reg:x8; val_offset:3675*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3675*FLEN/8, x10, x3, x5) + +inst_1248: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x106 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x105 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37fe; op2val:0xbd06; +op3val:0x3905; valaddr_reg:x8; val_offset:3678*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3678*FLEN/8, x10, x3, x5) + +inst_1249: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x106 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x105 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37fe; op2val:0xbd06; +op3val:0x3905; valaddr_reg:x8; val_offset:3681*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3681*FLEN/8, x10, x3, x5) + +inst_1250: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x020 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x280 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3820; op2val:0xba80; +op3val:0x36b5; valaddr_reg:x8; val_offset:3684*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3684*FLEN/8, x10, x3, x5) + +inst_1251: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x020 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x280 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3820; op2val:0xba80; +op3val:0x36b5; valaddr_reg:x8; val_offset:3687*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3687*FLEN/8, x10, x3, x5) + +inst_1252: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x020 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x280 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3820; op2val:0xba80; +op3val:0x36b5; valaddr_reg:x8; val_offset:3690*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3690*FLEN/8, x10, x3, x5) + +inst_1253: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x020 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x280 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3820; op2val:0xba80; +op3val:0x36b5; valaddr_reg:x8; val_offset:3693*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3693*FLEN/8, x10, x3, x5) + +inst_1254: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x020 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x280 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3820; op2val:0xba80; +op3val:0x36b5; valaddr_reg:x8; val_offset:3696*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3696*FLEN/8, x10, x3, x5) + +inst_1255: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x237 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x08f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x316 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3637; op2val:0xc08f; +op3val:0x3b16; valaddr_reg:x8; val_offset:3699*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3699*FLEN/8, x10, x3, x5) + +inst_1256: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x237 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x08f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x316 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3637; op2val:0xc08f; +op3val:0x3b16; valaddr_reg:x8; val_offset:3702*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3702*FLEN/8, x10, x3, x5) + +inst_1257: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x237 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x08f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x316 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3637; op2val:0xc08f; +op3val:0x3b16; valaddr_reg:x8; val_offset:3705*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3705*FLEN/8, x10, x3, x5) + +inst_1258: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x237 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x08f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x316 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3637; op2val:0xc08f; +op3val:0x3b16; valaddr_reg:x8; val_offset:3708*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3708*FLEN/8, x10, x3, x5) + +inst_1259: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x237 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x08f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x316 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3637; op2val:0xc08f; +op3val:0x3b16; valaddr_reg:x8; val_offset:3711*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3711*FLEN/8, x10, x3, x5) + +inst_1260: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3fd and fs2 == 1 and fe2 == 0x0f and fm2 == 0x127 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x098 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x53fd; op2val:0xbd27; +op3val:0x4c98; valaddr_reg:x8; val_offset:3714*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3714*FLEN/8, x10, x3, x5) + +inst_1261: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3fd and fs2 == 1 and fe2 == 0x0f and fm2 == 0x127 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x098 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x53fd; op2val:0xbd27; +op3val:0x4c98; valaddr_reg:x8; val_offset:3717*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3717*FLEN/8, x10, x3, x5) + +inst_1262: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3fd and fs2 == 1 and fe2 == 0x0f and fm2 == 0x127 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x098 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x53fd; op2val:0xbd27; +op3val:0x4c98; valaddr_reg:x8; val_offset:3720*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3720*FLEN/8, x10, x3, x5) + +inst_1263: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3fd and fs2 == 1 and fe2 == 0x0f and fm2 == 0x127 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x098 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x53fd; op2val:0xbd27; +op3val:0x4c98; valaddr_reg:x8; val_offset:3723*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3723*FLEN/8, x10, x3, x5) + +inst_1264: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3fd and fs2 == 1 and fe2 == 0x0f and fm2 == 0x127 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x098 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x53fd; op2val:0xbd27; +op3val:0x4c98; valaddr_reg:x8; val_offset:3726*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3726*FLEN/8, x10, x3, x5) + +inst_1265: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x06f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x05d and fs3 == 0 and fe3 == 0x12 and fm3 == 0x2bf and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x506f; op2val:0xc05d; +op3val:0x4abf; valaddr_reg:x8; val_offset:3729*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3729*FLEN/8, x10, x3, x5) + +inst_1266: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x06f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x05d and fs3 == 0 and fe3 == 0x12 and fm3 == 0x2bf and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x506f; op2val:0xc05d; +op3val:0x4abf; valaddr_reg:x8; val_offset:3732*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3732*FLEN/8, x10, x3, x5) + +inst_1267: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x06f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x05d and fs3 == 0 and fe3 == 0x12 and fm3 == 0x2bf and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x506f; op2val:0xc05d; +op3val:0x4abf; valaddr_reg:x8; val_offset:3735*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3735*FLEN/8, x10, x3, x5) + +inst_1268: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x06f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x05d and fs3 == 0 and fe3 == 0x12 and fm3 == 0x2bf and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x506f; op2val:0xc05d; +op3val:0x4abf; valaddr_reg:x8; val_offset:3738*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3738*FLEN/8, x10, x3, x5) + +inst_1269: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x06f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x05d and fs3 == 0 and fe3 == 0x12 and fm3 == 0x2bf and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x506f; op2val:0xc05d; +op3val:0x4abf; valaddr_reg:x8; val_offset:3741*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3741*FLEN/8, x10, x3, x5) + +inst_1270: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x118 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2d6 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x1b3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5118; op2val:0xbed6; +op3val:0x45b3; valaddr_reg:x8; val_offset:3744*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3744*FLEN/8, x10, x3, x5) + +inst_1271: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x118 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2d6 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x1b3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5118; op2val:0xbed6; +op3val:0x45b3; valaddr_reg:x8; val_offset:3747*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3747*FLEN/8, x10, x3, x5) + +inst_1272: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x118 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2d6 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x1b3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5118; op2val:0xbed6; +op3val:0x45b3; valaddr_reg:x8; val_offset:3750*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3750*FLEN/8, x10, x3, x5) + +inst_1273: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x118 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2d6 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x1b3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5118; op2val:0xbed6; +op3val:0x45b3; valaddr_reg:x8; val_offset:3753*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3753*FLEN/8, x10, x3, x5) + +inst_1274: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x118 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2d6 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x1b3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5118; op2val:0xbed6; +op3val:0x45b3; valaddr_reg:x8; val_offset:3756*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3756*FLEN/8, x10, x3, x5) + +inst_1275: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x188 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x008 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x24f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4d88; op2val:0xc408; +op3val:0x4e4f; valaddr_reg:x8; val_offset:3759*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3759*FLEN/8, x10, x3, x5) + +inst_1276: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x188 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x008 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x24f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4d88; op2val:0xc408; +op3val:0x4e4f; valaddr_reg:x8; val_offset:3762*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3762*FLEN/8, x10, x3, x5) + +inst_1277: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x188 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x008 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x24f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4d88; op2val:0xc408; +op3val:0x4e4f; valaddr_reg:x8; val_offset:3765*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3765*FLEN/8, x10, x3, x5) + +inst_1278: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x188 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x008 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x24f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4d88; op2val:0xc408; +op3val:0x4e4f; valaddr_reg:x8; val_offset:3768*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3768*FLEN/8, x10, x3, x5) + +inst_1279: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x188 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x008 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x24f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4d88; op2val:0xc408; +op3val:0x4e4f; valaddr_reg:x8; val_offset:3771*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3771*FLEN/8, x10, x3, x5) + +inst_1280: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x12e and fs2 == 1 and fe2 == 0x11 and fm2 == 0x09e and fs3 == 0 and fe3 == 0x13 and fm3 == 0x3ec and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4d2e; op2val:0xc49e; +op3val:0x4fec; valaddr_reg:x8; val_offset:3774*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3774*FLEN/8, x10, x3, x5) + +inst_1281: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x12e and fs2 == 1 and fe2 == 0x11 and fm2 == 0x09e and fs3 == 0 and fe3 == 0x13 and fm3 == 0x3ec and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4d2e; op2val:0xc49e; +op3val:0x4fec; valaddr_reg:x8; val_offset:3777*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3777*FLEN/8, x10, x3, x5) + +inst_1282: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x12e and fs2 == 1 and fe2 == 0x11 and fm2 == 0x09e and fs3 == 0 and fe3 == 0x13 and fm3 == 0x3ec and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4d2e; op2val:0xc49e; +op3val:0x4fec; valaddr_reg:x8; val_offset:3780*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3780*FLEN/8, x10, x3, x5) + +inst_1283: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x12e and fs2 == 1 and fe2 == 0x11 and fm2 == 0x09e and fs3 == 0 and fe3 == 0x13 and fm3 == 0x3ec and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4d2e; op2val:0xc49e; +op3val:0x4fec; valaddr_reg:x8; val_offset:3783*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3783*FLEN/8, x10, x3, x5) + +inst_1284: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x12e and fs2 == 1 and fe2 == 0x11 and fm2 == 0x09e and fs3 == 0 and fe3 == 0x13 and fm3 == 0x3ec and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4d2e; op2val:0xc49e; +op3val:0x4fec; valaddr_reg:x8; val_offset:3786*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3786*FLEN/8, x10, x3, x5) + +inst_1285: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x17c and fs2 == 1 and fe2 == 0x12 and fm2 == 0x05f and fs3 == 0 and fe3 == 0x13 and fm3 == 0x3fa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x497c; op2val:0xc85f; +op3val:0x4ffa; valaddr_reg:x8; val_offset:3789*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3789*FLEN/8, x10, x3, x5) + +inst_1286: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x17c and fs2 == 1 and fe2 == 0x12 and fm2 == 0x05f and fs3 == 0 and fe3 == 0x13 and fm3 == 0x3fa and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x497c; op2val:0xc85f; +op3val:0x4ffa; valaddr_reg:x8; val_offset:3792*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3792*FLEN/8, x10, x3, x5) + +inst_1287: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x17c and fs2 == 1 and fe2 == 0x12 and fm2 == 0x05f and fs3 == 0 and fe3 == 0x13 and fm3 == 0x3fa and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x497c; op2val:0xc85f; +op3val:0x4ffa; valaddr_reg:x8; val_offset:3795*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3795*FLEN/8, x10, x3, x5) + +inst_1288: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x17c and fs2 == 1 and fe2 == 0x12 and fm2 == 0x05f and fs3 == 0 and fe3 == 0x13 and fm3 == 0x3fa and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x497c; op2val:0xc85f; +op3val:0x4ffa; valaddr_reg:x8; val_offset:3798*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3798*FLEN/8, x10, x3, x5) + +inst_1289: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x17c and fs2 == 1 and fe2 == 0x12 and fm2 == 0x05f and fs3 == 0 and fe3 == 0x13 and fm3 == 0x3fa and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x497c; op2val:0xc85f; +op3val:0x4ffa; valaddr_reg:x8; val_offset:3801*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3801*FLEN/8, x10, x3, x5) + +inst_1290: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x264 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x017 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x113 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5264; op2val:0xc017; +op3val:0x5113; valaddr_reg:x8; val_offset:3804*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3804*FLEN/8, x10, x3, x5) + +inst_1291: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x264 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x017 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x113 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5264; op2val:0xc017; +op3val:0x5113; valaddr_reg:x8; val_offset:3807*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3807*FLEN/8, x10, x3, x5) + +inst_1292: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x264 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x017 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x113 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5264; op2val:0xc017; +op3val:0x5113; valaddr_reg:x8; val_offset:3810*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3810*FLEN/8, x10, x3, x5) + +inst_1293: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x264 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x017 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x113 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5264; op2val:0xc017; +op3val:0x5113; valaddr_reg:x8; val_offset:3813*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3813*FLEN/8, x10, x3, x5) + +inst_1294: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x264 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x017 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x113 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5264; op2val:0xc017; +op3val:0x5113; valaddr_reg:x8; val_offset:3816*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3816*FLEN/8, x10, x3, x5) + +inst_1295: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3c4 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x005 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x39b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x53c4; op2val:0xc005; +op3val:0x539b; valaddr_reg:x8; val_offset:3819*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3819*FLEN/8, x10, x3, x5) + +inst_1296: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3c4 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x005 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x39b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x53c4; op2val:0xc005; +op3val:0x539b; valaddr_reg:x8; val_offset:3822*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3822*FLEN/8, x10, x3, x5) + +inst_1297: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3c4 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x005 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x39b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x53c4; op2val:0xc005; +op3val:0x539b; valaddr_reg:x8; val_offset:3825*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3825*FLEN/8, x10, x3, x5) + +inst_1298: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3c4 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x005 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x39b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x53c4; op2val:0xc005; +op3val:0x539b; valaddr_reg:x8; val_offset:3828*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3828*FLEN/8, x10, x3, x5) + +inst_1299: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3c4 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x005 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x39b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x53c4; op2val:0xc005; +op3val:0x539b; valaddr_reg:x8; val_offset:3831*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3831*FLEN/8, x10, x3, x5) + +inst_1300: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3c5 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x214 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x39e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4fc5; op2val:0xc214; +op3val:0x4f9e; valaddr_reg:x8; val_offset:3834*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3834*FLEN/8, x10, x3, x5) + +inst_1301: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3c5 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x214 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x39e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4fc5; op2val:0xc214; +op3val:0x4f9e; valaddr_reg:x8; val_offset:3837*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3837*FLEN/8, x10, x3, x5) + +inst_1302: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3c5 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x214 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x39e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4fc5; op2val:0xc214; +op3val:0x4f9e; valaddr_reg:x8; val_offset:3840*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3840*FLEN/8, x10, x3, x5) + +inst_1303: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3c5 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x214 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x39e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4fc5; op2val:0xc214; +op3val:0x4f9e; valaddr_reg:x8; val_offset:3843*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3843*FLEN/8, x10, x3, x5) +RVTEST_SIGBASE(x3,signature_x3_10) + +inst_1304: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3c5 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x214 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x39e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4fc5; op2val:0xc214; +op3val:0x4f9e; valaddr_reg:x8; val_offset:3846*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3846*FLEN/8, x10, x3, x5) + +inst_1305: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x221 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0e9 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x30d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5221; op2val:0xc0e9; +op3val:0x530d; valaddr_reg:x8; val_offset:3849*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3849*FLEN/8, x10, x3, x5) + +inst_1306: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x221 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0e9 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x30d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5221; op2val:0xc0e9; +op3val:0x530d; valaddr_reg:x8; val_offset:3852*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3852*FLEN/8, x10, x3, x5) + +inst_1307: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x221 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0e9 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x30d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5221; op2val:0xc0e9; +op3val:0x530d; valaddr_reg:x8; val_offset:3855*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3855*FLEN/8, x10, x3, x5) + +inst_1308: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x221 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0e9 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x30d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5221; op2val:0xc0e9; +op3val:0x530d; valaddr_reg:x8; val_offset:3858*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3858*FLEN/8, x10, x3, x5) + +inst_1309: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x221 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0e9 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x30d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5221; op2val:0xc0e9; +op3val:0x530d; valaddr_reg:x8; val_offset:3861*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3861*FLEN/8, x10, x3, x5) + +inst_1310: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x062 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x21a and fs3 == 0 and fe3 == 0x14 and fm3 == 0x161 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5062; op2val:0xc21a; +op3val:0x5161; valaddr_reg:x8; val_offset:3864*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3864*FLEN/8, x10, x3, x5) + +inst_1311: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x062 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x21a and fs3 == 0 and fe3 == 0x14 and fm3 == 0x161 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5062; op2val:0xc21a; +op3val:0x5161; valaddr_reg:x8; val_offset:3867*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3867*FLEN/8, x10, x3, x5) + +inst_1312: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x062 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x21a and fs3 == 0 and fe3 == 0x14 and fm3 == 0x161 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5062; op2val:0xc21a; +op3val:0x5161; valaddr_reg:x8; val_offset:3870*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3870*FLEN/8, x10, x3, x5) + +inst_1313: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x062 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x21a and fs3 == 0 and fe3 == 0x14 and fm3 == 0x161 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5062; op2val:0xc21a; +op3val:0x5161; valaddr_reg:x8; val_offset:3873*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3873*FLEN/8, x10, x3, x5) + +inst_1314: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x062 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x21a and fs3 == 0 and fe3 == 0x14 and fm3 == 0x161 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5062; op2val:0xc21a; +op3val:0x5161; valaddr_reg:x8; val_offset:3876*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3876*FLEN/8, x10, x3, x5) + +inst_1315: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x190 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x05f and fs3 == 0 and fe3 == 0x14 and fm3 == 0x02c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5190; op2val:0xc05f; +op3val:0x502c; valaddr_reg:x8; val_offset:3879*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3879*FLEN/8, x10, x3, x5) + +inst_1316: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x190 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x05f and fs3 == 0 and fe3 == 0x14 and fm3 == 0x02c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5190; op2val:0xc05f; +op3val:0x502c; valaddr_reg:x8; val_offset:3882*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3882*FLEN/8, x10, x3, x5) + +inst_1317: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x190 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x05f and fs3 == 0 and fe3 == 0x14 and fm3 == 0x02c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5190; op2val:0xc05f; +op3val:0x502c; valaddr_reg:x8; val_offset:3885*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3885*FLEN/8, x10, x3, x5) + +inst_1318: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x190 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x05f and fs3 == 0 and fe3 == 0x14 and fm3 == 0x02c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5190; op2val:0xc05f; +op3val:0x502c; valaddr_reg:x8; val_offset:3888*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3888*FLEN/8, x10, x3, x5) + +inst_1319: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x190 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x05f and fs3 == 0 and fe3 == 0x14 and fm3 == 0x02c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5190; op2val:0xc05f; +op3val:0x502c; valaddr_reg:x8; val_offset:3891*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3891*FLEN/8, x10, x3, x5) + +inst_1320: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x020 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x177 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x291 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5020; op2val:0xc177; +op3val:0x4e91; valaddr_reg:x8; val_offset:3894*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3894*FLEN/8, x10, x3, x5) + +inst_1321: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x020 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x177 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x291 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5020; op2val:0xc177; +op3val:0x4e91; valaddr_reg:x8; val_offset:3897*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3897*FLEN/8, x10, x3, x5) + +inst_1322: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x020 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x177 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x291 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5020; op2val:0xc177; +op3val:0x4e91; valaddr_reg:x8; val_offset:3900*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3900*FLEN/8, x10, x3, x5) + +inst_1323: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x020 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x177 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x291 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5020; op2val:0xc177; +op3val:0x4e91; valaddr_reg:x8; val_offset:3903*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3903*FLEN/8, x10, x3, x5) + +inst_1324: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x020 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x177 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x291 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5020; op2val:0xc177; +op3val:0x4e91; valaddr_reg:x8; val_offset:3906*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3906*FLEN/8, x10, x3, x5) + +inst_1325: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x351 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x27b and fs3 == 0 and fe3 == 0x13 and fm3 == 0x3b8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4f51; op2val:0xc27b; +op3val:0x4fb8; valaddr_reg:x8; val_offset:3909*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3909*FLEN/8, x10, x3, x5) + +inst_1326: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x351 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x27b and fs3 == 0 and fe3 == 0x13 and fm3 == 0x3b8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4f51; op2val:0xc27b; +op3val:0x4fb8; valaddr_reg:x8; val_offset:3912*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3912*FLEN/8, x10, x3, x5) + +inst_1327: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x351 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x27b and fs3 == 0 and fe3 == 0x13 and fm3 == 0x3b8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4f51; op2val:0xc27b; +op3val:0x4fb8; valaddr_reg:x8; val_offset:3915*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3915*FLEN/8, x10, x3, x5) + +inst_1328: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x351 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x27b and fs3 == 0 and fe3 == 0x13 and fm3 == 0x3b8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4f51; op2val:0xc27b; +op3val:0x4fb8; valaddr_reg:x8; val_offset:3918*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3918*FLEN/8, x10, x3, x5) + +inst_1329: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x351 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x27b and fs3 == 0 and fe3 == 0x13 and fm3 == 0x3b8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4f51; op2val:0xc27b; +op3val:0x4fb8; valaddr_reg:x8; val_offset:3921*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3921*FLEN/8, x10, x3, x5) + +inst_1330: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x272 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1d2 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x188 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5272; op2val:0xbdd2; +op3val:0x4988; valaddr_reg:x8; val_offset:3924*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3924*FLEN/8, x10, x3, x5) + +inst_1331: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x272 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1d2 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x188 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5272; op2val:0xbdd2; +op3val:0x4988; valaddr_reg:x8; val_offset:3927*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3927*FLEN/8, x10, x3, x5) + +inst_1332: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x272 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1d2 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x188 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5272; op2val:0xbdd2; +op3val:0x4988; valaddr_reg:x8; val_offset:3930*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3930*FLEN/8, x10, x3, x5) + +inst_1333: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x272 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1d2 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x188 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5272; op2val:0xbdd2; +op3val:0x4988; valaddr_reg:x8; val_offset:3933*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3933*FLEN/8, x10, x3, x5) + +inst_1334: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x272 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1d2 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x188 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5272; op2val:0xbdd2; +op3val:0x4988; valaddr_reg:x8; val_offset:3936*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3936*FLEN/8, x10, x3, x5) + +inst_1335: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x034 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x352 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x365 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4834; op2val:0xcb52; +op3val:0x5365; valaddr_reg:x8; val_offset:3939*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3939*FLEN/8, x10, x3, x5) + +inst_1336: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x034 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x352 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x365 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4834; op2val:0xcb52; +op3val:0x5365; valaddr_reg:x8; val_offset:3942*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3942*FLEN/8, x10, x3, x5) + +inst_1337: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x034 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x352 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x365 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4834; op2val:0xcb52; +op3val:0x5365; valaddr_reg:x8; val_offset:3945*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3945*FLEN/8, x10, x3, x5) + +inst_1338: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x034 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x352 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x365 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4834; op2val:0xcb52; +op3val:0x5365; valaddr_reg:x8; val_offset:3948*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3948*FLEN/8, x10, x3, x5) + +inst_1339: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x034 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x352 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x365 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4834; op2val:0xcb52; +op3val:0x5365; valaddr_reg:x8; val_offset:3951*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3951*FLEN/8, x10, x3, x5) + +inst_1340: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x024 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x292 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x19d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5024; op2val:0xc292; +op3val:0x519d; valaddr_reg:x8; val_offset:3954*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3954*FLEN/8, x10, x3, x5) + +inst_1341: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x024 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x292 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x19d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5024; op2val:0xc292; +op3val:0x519d; valaddr_reg:x8; val_offset:3957*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3957*FLEN/8, x10, x3, x5) + +inst_1342: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x024 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x292 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x19d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5024; op2val:0xc292; +op3val:0x519d; valaddr_reg:x8; val_offset:3960*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3960*FLEN/8, x10, x3, x5) + +inst_1343: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x024 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x292 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x19d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5024; op2val:0xc292; +op3val:0x519d; valaddr_reg:x8; val_offset:3963*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3963*FLEN/8, x10, x3, x5) + +inst_1344: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x024 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x292 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x19d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5024; op2val:0xc292; +op3val:0x519d; valaddr_reg:x8; val_offset:3966*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3966*FLEN/8, x10, x3, x5) + +inst_1345: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x356 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x397 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x1ec and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5356; op2val:0xbf97; +op3val:0x51ec; valaddr_reg:x8; val_offset:3969*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3969*FLEN/8, x10, x3, x5) + +inst_1346: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x356 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x397 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x1ec and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5356; op2val:0xbf97; +op3val:0x51ec; valaddr_reg:x8; val_offset:3972*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3972*FLEN/8, x10, x3, x5) + +inst_1347: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x356 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x397 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x1ec and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5356; op2val:0xbf97; +op3val:0x51ec; valaddr_reg:x8; val_offset:3975*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3975*FLEN/8, x10, x3, x5) + +inst_1348: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x356 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x397 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x1ec and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5356; op2val:0xbf97; +op3val:0x51ec; valaddr_reg:x8; val_offset:3978*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3978*FLEN/8, x10, x3, x5) + +inst_1349: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x356 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x397 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x1ec and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5356; op2val:0xbf97; +op3val:0x51ec; valaddr_reg:x8; val_offset:3981*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3981*FLEN/8, x10, x3, x5) + +inst_1350: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x096 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2d0 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x39f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5096; op2val:0xc2d0; +op3val:0x539f; valaddr_reg:x8; val_offset:3984*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3984*FLEN/8, x10, x3, x5) + +inst_1351: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x096 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2d0 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x39f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5096; op2val:0xc2d0; +op3val:0x539f; valaddr_reg:x8; val_offset:3987*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3987*FLEN/8, x10, x3, x5) + +inst_1352: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x096 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2d0 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x39f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5096; op2val:0xc2d0; +op3val:0x539f; valaddr_reg:x8; val_offset:3990*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3990*FLEN/8, x10, x3, x5) + +inst_1353: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x096 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2d0 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x39f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5096; op2val:0xc2d0; +op3val:0x539f; valaddr_reg:x8; val_offset:3993*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3993*FLEN/8, x10, x3, x5) + +inst_1354: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x096 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2d0 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x39f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5096; op2val:0xc2d0; +op3val:0x539f; valaddr_reg:x8; val_offset:3996*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3996*FLEN/8, x10, x3, x5) + +inst_1355: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x10a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x09e and fs3 == 0 and fe3 == 0x13 and fm3 == 0x349 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x510a; op2val:0xc09e; +op3val:0x4f49; valaddr_reg:x8; val_offset:3999*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3999*FLEN/8, x10, x3, x5) + +inst_1356: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x10a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x09e and fs3 == 0 and fe3 == 0x13 and fm3 == 0x349 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x510a; op2val:0xc09e; +op3val:0x4f49; valaddr_reg:x8; val_offset:4002*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4002*FLEN/8, x10, x3, x5) + +inst_1357: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x10a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x09e and fs3 == 0 and fe3 == 0x13 and fm3 == 0x349 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x510a; op2val:0xc09e; +op3val:0x4f49; valaddr_reg:x8; val_offset:4005*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4005*FLEN/8, x10, x3, x5) + +inst_1358: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x10a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x09e and fs3 == 0 and fe3 == 0x13 and fm3 == 0x349 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x510a; op2val:0xc09e; +op3val:0x4f49; valaddr_reg:x8; val_offset:4008*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4008*FLEN/8, x10, x3, x5) + +inst_1359: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x10a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x09e and fs3 == 0 and fe3 == 0x13 and fm3 == 0x349 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x510a; op2val:0xc09e; +op3val:0x4f49; valaddr_reg:x8; val_offset:4011*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4011*FLEN/8, x10, x3, x5) + +inst_1360: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x241 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1ff and fs3 == 0 and fe3 == 0x12 and fm3 == 0x184 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4a41; op2val:0xc5ff; +op3val:0x4984; valaddr_reg:x8; val_offset:4014*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4014*FLEN/8, x10, x3, x5) + +inst_1361: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x241 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1ff and fs3 == 0 and fe3 == 0x12 and fm3 == 0x184 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4a41; op2val:0xc5ff; +op3val:0x4984; valaddr_reg:x8; val_offset:4017*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4017*FLEN/8, x10, x3, x5) + +inst_1362: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x241 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1ff and fs3 == 0 and fe3 == 0x12 and fm3 == 0x184 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4a41; op2val:0xc5ff; +op3val:0x4984; valaddr_reg:x8; val_offset:4020*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4020*FLEN/8, x10, x3, x5) + +inst_1363: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x241 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1ff and fs3 == 0 and fe3 == 0x12 and fm3 == 0x184 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4a41; op2val:0xc5ff; +op3val:0x4984; valaddr_reg:x8; val_offset:4023*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4023*FLEN/8, x10, x3, x5) + +inst_1364: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x241 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1ff and fs3 == 0 and fe3 == 0x12 and fm3 == 0x184 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4a41; op2val:0xc5ff; +op3val:0x4984; valaddr_reg:x8; val_offset:4026*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4026*FLEN/8, x10, x3, x5) + +inst_1365: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x25d and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x32f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x525d; op2val:0xc0c5; +op3val:0x532f; valaddr_reg:x8; val_offset:4029*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4029*FLEN/8, x10, x3, x5) + +inst_1366: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x25d and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x32f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x525d; op2val:0xc0c5; +op3val:0x532f; valaddr_reg:x8; val_offset:4032*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4032*FLEN/8, x10, x3, x5) + +inst_1367: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x25d and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x32f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x525d; op2val:0xc0c5; +op3val:0x532f; valaddr_reg:x8; val_offset:4035*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4035*FLEN/8, x10, x3, x5) + +inst_1368: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x25d and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x32f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x525d; op2val:0xc0c5; +op3val:0x532f; valaddr_reg:x8; val_offset:4038*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4038*FLEN/8, x10, x3, x5) + +inst_1369: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x25d and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x32f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x525d; op2val:0xc0c5; +op3val:0x532f; valaddr_reg:x8; val_offset:4041*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4041*FLEN/8, x10, x3, x5) + +inst_1370: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x1df and fs2 == 1 and fe2 == 0x11 and fm2 == 0x02f and fs3 == 0 and fe3 == 0x14 and fm3 == 0x04a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4ddf; op2val:0xc42f; +op3val:0x504a; valaddr_reg:x8; val_offset:4044*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4044*FLEN/8, x10, x3, x5) + +inst_1371: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x1df and fs2 == 1 and fe2 == 0x11 and fm2 == 0x02f and fs3 == 0 and fe3 == 0x14 and fm3 == 0x04a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4ddf; op2val:0xc42f; +op3val:0x504a; valaddr_reg:x8; val_offset:4047*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4047*FLEN/8, x10, x3, x5) + +inst_1372: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x1df and fs2 == 1 and fe2 == 0x11 and fm2 == 0x02f and fs3 == 0 and fe3 == 0x14 and fm3 == 0x04a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4ddf; op2val:0xc42f; +op3val:0x504a; valaddr_reg:x8; val_offset:4050*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4050*FLEN/8, x10, x3, x5) + +inst_1373: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x1df and fs2 == 1 and fe2 == 0x11 and fm2 == 0x02f and fs3 == 0 and fe3 == 0x14 and fm3 == 0x04a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4ddf; op2val:0xc42f; +op3val:0x504a; valaddr_reg:x8; val_offset:4053*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4053*FLEN/8, x10, x3, x5) + +inst_1374: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x1df and fs2 == 1 and fe2 == 0x11 and fm2 == 0x02f and fs3 == 0 and fe3 == 0x14 and fm3 == 0x04a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4ddf; op2val:0xc42f; +op3val:0x504a; valaddr_reg:x8; val_offset:4056*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4056*FLEN/8, x10, x3, x5) + +inst_1375: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x178 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0b8 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0e7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5178; op2val:0xc0b8; +op3val:0x50e7; valaddr_reg:x8; val_offset:4059*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4059*FLEN/8, x10, x3, x5) + +inst_1376: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x178 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0b8 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0e7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5178; op2val:0xc0b8; +op3val:0x50e7; valaddr_reg:x8; val_offset:4062*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4062*FLEN/8, x10, x3, x5) + +inst_1377: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x178 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0b8 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0e7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5178; op2val:0xc0b8; +op3val:0x50e7; valaddr_reg:x8; val_offset:4065*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4065*FLEN/8, x10, x3, x5) + +inst_1378: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x178 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0b8 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0e7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5178; op2val:0xc0b8; +op3val:0x50e7; valaddr_reg:x8; val_offset:4068*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4068*FLEN/8, x10, x3, x5) + +inst_1379: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x178 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0b8 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0e7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5178; op2val:0xc0b8; +op3val:0x50e7; valaddr_reg:x8; val_offset:4071*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4071*FLEN/8, x10, x3, x5) + +inst_1380: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x096 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2ac and fs3 == 0 and fe3 == 0x14 and fm3 == 0x34d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c96; op2val:0xc6ac; +op3val:0x534d; valaddr_reg:x8; val_offset:4074*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4074*FLEN/8, x10, x3, x5) + +inst_1381: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x096 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2ac and fs3 == 0 and fe3 == 0x14 and fm3 == 0x34d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c96; op2val:0xc6ac; +op3val:0x534d; valaddr_reg:x8; val_offset:4077*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4077*FLEN/8, x10, x3, x5) + +inst_1382: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x096 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2ac and fs3 == 0 and fe3 == 0x14 and fm3 == 0x34d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c96; op2val:0xc6ac; +op3val:0x534d; valaddr_reg:x8; val_offset:4080*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4080*FLEN/8, x10, x3, x5) + +inst_1383: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x096 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2ac and fs3 == 0 and fe3 == 0x14 and fm3 == 0x34d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c96; op2val:0xc6ac; +op3val:0x534d; valaddr_reg:x8; val_offset:4083*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4083*FLEN/8, x10, x3, x5) + +inst_1384: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x096 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2ac and fs3 == 0 and fe3 == 0x14 and fm3 == 0x34d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c96; op2val:0xc6ac; +op3val:0x534d; valaddr_reg:x8; val_offset:4086*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4086*FLEN/8, x10, x3, x5) + +inst_1385: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x078 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x226 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x1c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5078; op2val:0xc226; +op3val:0x51c0; valaddr_reg:x8; val_offset:4089*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4089*FLEN/8, x10, x3, x5) + +inst_1386: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x078 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x226 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x1c0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5078; op2val:0xc226; +op3val:0x51c0; valaddr_reg:x8; val_offset:4092*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4092*FLEN/8, x10, x3, x5) + +inst_1387: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x078 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x226 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x1c0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5078; op2val:0xc226; +op3val:0x51c0; valaddr_reg:x8; val_offset:4095*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4095*FLEN/8, x10, x3, x5) + +inst_1388: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x078 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x226 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x1c0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5078; op2val:0xc226; +op3val:0x51c0; valaddr_reg:x8; val_offset:4098*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4098*FLEN/8, x10, x3, x5) + +inst_1389: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x078 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x226 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x1c0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5078; op2val:0xc226; +op3val:0x51c0; valaddr_reg:x8; val_offset:4101*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4101*FLEN/8, x10, x3, x5) + +inst_1390: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x18c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x02c and fs3 == 0 and fe3 == 0x13 and fm3 == 0x327 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x518c; op2val:0xc02c; +op3val:0x4f27; valaddr_reg:x8; val_offset:4104*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4104*FLEN/8, x10, x3, x5) + +inst_1391: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x18c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x02c and fs3 == 0 and fe3 == 0x13 and fm3 == 0x327 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x518c; op2val:0xc02c; +op3val:0x4f27; valaddr_reg:x8; val_offset:4107*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4107*FLEN/8, x10, x3, x5) + +inst_1392: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x18c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x02c and fs3 == 0 and fe3 == 0x13 and fm3 == 0x327 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x518c; op2val:0xc02c; +op3val:0x4f27; valaddr_reg:x8; val_offset:4110*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4110*FLEN/8, x10, x3, x5) + +inst_1393: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x18c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x02c and fs3 == 0 and fe3 == 0x13 and fm3 == 0x327 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x518c; op2val:0xc02c; +op3val:0x4f27; valaddr_reg:x8; val_offset:4113*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4113*FLEN/8, x10, x3, x5) + +inst_1394: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x18c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x02c and fs3 == 0 and fe3 == 0x13 and fm3 == 0x327 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x518c; op2val:0xc02c; +op3val:0x4f27; valaddr_reg:x8; val_offset:4116*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4116*FLEN/8, x10, x3, x5) + +inst_1395: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1a6 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2d0 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x27b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x51a6; op2val:0xbed0; +op3val:0x4a7b; valaddr_reg:x8; val_offset:4119*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4119*FLEN/8, x10, x3, x5) + +inst_1396: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1a6 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2d0 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x27b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x51a6; op2val:0xbed0; +op3val:0x4a7b; valaddr_reg:x8; val_offset:4122*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4122*FLEN/8, x10, x3, x5) + +inst_1397: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1a6 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2d0 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x27b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x51a6; op2val:0xbed0; +op3val:0x4a7b; valaddr_reg:x8; val_offset:4125*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4125*FLEN/8, x10, x3, x5) + +inst_1398: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1a6 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2d0 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x27b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x51a6; op2val:0xbed0; +op3val:0x4a7b; valaddr_reg:x8; val_offset:4128*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4128*FLEN/8, x10, x3, x5) + +inst_1399: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1a6 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2d0 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x27b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x51a6; op2val:0xbed0; +op3val:0x4a7b; valaddr_reg:x8; val_offset:4131*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4131*FLEN/8, x10, x3, x5) + +inst_1400: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x070 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1f8 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x141 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5070; op2val:0xc1f8; +op3val:0x5141; valaddr_reg:x8; val_offset:4134*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4134*FLEN/8, x10, x3, x5) + +inst_1401: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x070 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1f8 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x141 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5070; op2val:0xc1f8; +op3val:0x5141; valaddr_reg:x8; val_offset:4137*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4137*FLEN/8, x10, x3, x5) + +inst_1402: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x070 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1f8 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x141 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5070; op2val:0xc1f8; +op3val:0x5141; valaddr_reg:x8; val_offset:4140*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4140*FLEN/8, x10, x3, x5) + +inst_1403: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x070 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1f8 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x141 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5070; op2val:0xc1f8; +op3val:0x5141; valaddr_reg:x8; val_offset:4143*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4143*FLEN/8, x10, x3, x5) + +inst_1404: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x070 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1f8 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x141 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5070; op2val:0xc1f8; +op3val:0x5141; valaddr_reg:x8; val_offset:4146*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4146*FLEN/8, x10, x3, x5) + +inst_1405: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x114 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x01a and fs3 == 0 and fe3 == 0x13 and fm3 == 0x0da and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5114; op2val:0xc01a; +op3val:0x4cda; valaddr_reg:x8; val_offset:4149*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4149*FLEN/8, x10, x3, x5) + +inst_1406: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x114 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x01a and fs3 == 0 and fe3 == 0x13 and fm3 == 0x0da and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5114; op2val:0xc01a; +op3val:0x4cda; valaddr_reg:x8; val_offset:4152*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4152*FLEN/8, x10, x3, x5) + +inst_1407: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x114 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x01a and fs3 == 0 and fe3 == 0x13 and fm3 == 0x0da and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5114; op2val:0xc01a; +op3val:0x4cda; valaddr_reg:x8; val_offset:4155*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4155*FLEN/8, x10, x3, x5) + +inst_1408: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x114 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x01a and fs3 == 0 and fe3 == 0x13 and fm3 == 0x0da and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5114; op2val:0xc01a; +op3val:0x4cda; valaddr_reg:x8; val_offset:4158*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4158*FLEN/8, x10, x3, x5) + +inst_1409: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x114 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x01a and fs3 == 0 and fe3 == 0x13 and fm3 == 0x0da and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5114; op2val:0xc01a; +op3val:0x4cda; valaddr_reg:x8; val_offset:4161*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4161*FLEN/8, x10, x3, x5) + +inst_1410: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x237 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1bd and fs3 == 0 and fe3 == 0x11 and fm3 == 0x361 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4a37; op2val:0xc5bd; +op3val:0x4761; valaddr_reg:x8; val_offset:4164*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4164*FLEN/8, x10, x3, x5) + +inst_1411: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x237 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1bd and fs3 == 0 and fe3 == 0x11 and fm3 == 0x361 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4a37; op2val:0xc5bd; +op3val:0x4761; valaddr_reg:x8; val_offset:4167*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4167*FLEN/8, x10, x3, x5) + +inst_1412: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x237 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1bd and fs3 == 0 and fe3 == 0x11 and fm3 == 0x361 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4a37; op2val:0xc5bd; +op3val:0x4761; valaddr_reg:x8; val_offset:4170*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4170*FLEN/8, x10, x3, x5) + +inst_1413: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x237 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1bd and fs3 == 0 and fe3 == 0x11 and fm3 == 0x361 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4a37; op2val:0xc5bd; +op3val:0x4761; valaddr_reg:x8; val_offset:4173*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4173*FLEN/8, x10, x3, x5) + +inst_1414: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x237 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1bd and fs3 == 0 and fe3 == 0x11 and fm3 == 0x361 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4a37; op2val:0xc5bd; +op3val:0x4761; valaddr_reg:x8; val_offset:4176*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4176*FLEN/8, x10, x3, x5) + +inst_1415: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x066 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x05a and fs3 == 0 and fe3 == 0x12 and fm3 == 0x24e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4866; op2val:0xc85a; +op3val:0x4a4e; valaddr_reg:x8; val_offset:4179*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4179*FLEN/8, x10, x3, x5) + +inst_1416: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x066 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x05a and fs3 == 0 and fe3 == 0x12 and fm3 == 0x24e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4866; op2val:0xc85a; +op3val:0x4a4e; valaddr_reg:x8; val_offset:4182*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4182*FLEN/8, x10, x3, x5) + +inst_1417: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x066 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x05a and fs3 == 0 and fe3 == 0x12 and fm3 == 0x24e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4866; op2val:0xc85a; +op3val:0x4a4e; valaddr_reg:x8; val_offset:4185*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4185*FLEN/8, x10, x3, x5) + +inst_1418: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x066 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x05a and fs3 == 0 and fe3 == 0x12 and fm3 == 0x24e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4866; op2val:0xc85a; +op3val:0x4a4e; valaddr_reg:x8; val_offset:4188*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4188*FLEN/8, x10, x3, x5) + +inst_1419: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x066 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x05a and fs3 == 0 and fe3 == 0x12 and fm3 == 0x24e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4866; op2val:0xc85a; +op3val:0x4a4e; valaddr_reg:x8; val_offset:4191*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4191*FLEN/8, x10, x3, x5) + +inst_1420: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3e5 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x262 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x09a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4fe5; op2val:0xc262; +op3val:0x509a; valaddr_reg:x8; val_offset:4194*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4194*FLEN/8, x10, x3, x5) + +inst_1421: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3e5 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x262 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x09a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4fe5; op2val:0xc262; +op3val:0x509a; valaddr_reg:x8; val_offset:4197*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4197*FLEN/8, x10, x3, x5) + +inst_1422: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3e5 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x262 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x09a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4fe5; op2val:0xc262; +op3val:0x509a; valaddr_reg:x8; val_offset:4200*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4200*FLEN/8, x10, x3, x5) + +inst_1423: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3e5 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x262 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x09a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4fe5; op2val:0xc262; +op3val:0x509a; valaddr_reg:x8; val_offset:4203*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4203*FLEN/8, x10, x3, x5) + +inst_1424: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3e5 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x262 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x09a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4fe5; op2val:0xc262; +op3val:0x509a; valaddr_reg:x8; val_offset:4206*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4206*FLEN/8, x10, x3, x5) + +inst_1425: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1af and fs2 == 1 and fe2 == 0x10 and fm2 == 0x012 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x326 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x51af; op2val:0xc012; +op3val:0x4f26; valaddr_reg:x8; val_offset:4209*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4209*FLEN/8, x10, x3, x5) + +inst_1426: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1af and fs2 == 1 and fe2 == 0x10 and fm2 == 0x012 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x326 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x51af; op2val:0xc012; +op3val:0x4f26; valaddr_reg:x8; val_offset:4212*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4212*FLEN/8, x10, x3, x5) + +inst_1427: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1af and fs2 == 1 and fe2 == 0x10 and fm2 == 0x012 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x326 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x51af; op2val:0xc012; +op3val:0x4f26; valaddr_reg:x8; val_offset:4215*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4215*FLEN/8, x10, x3, x5) + +inst_1428: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1af and fs2 == 1 and fe2 == 0x10 and fm2 == 0x012 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x326 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x51af; op2val:0xc012; +op3val:0x4f26; valaddr_reg:x8; val_offset:4218*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4218*FLEN/8, x10, x3, x5) + +inst_1429: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1af and fs2 == 1 and fe2 == 0x10 and fm2 == 0x012 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x326 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x51af; op2val:0xc012; +op3val:0x4f26; valaddr_reg:x8; val_offset:4221*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4221*FLEN/8, x10, x3, x5) + +inst_1430: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x22b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x16a and fs3 == 0 and fe3 == 0x10 and fm3 == 0x1bb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x522b; op2val:0xbd6a; +op3val:0x41bb; valaddr_reg:x8; val_offset:4224*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4224*FLEN/8, x10, x3, x5) + +inst_1431: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x22b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x16a and fs3 == 0 and fe3 == 0x10 and fm3 == 0x1bb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x522b; op2val:0xbd6a; +op3val:0x41bb; valaddr_reg:x8; val_offset:4227*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4227*FLEN/8, x10, x3, x5) +RVTEST_SIGBASE(x3,signature_x3_11) + +inst_1432: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x22b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x16a and fs3 == 0 and fe3 == 0x10 and fm3 == 0x1bb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x522b; op2val:0xbd6a; +op3val:0x41bb; valaddr_reg:x8; val_offset:4230*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4230*FLEN/8, x10, x3, x5) + +inst_1433: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x22b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x16a and fs3 == 0 and fe3 == 0x10 and fm3 == 0x1bb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x522b; op2val:0xbd6a; +op3val:0x41bb; valaddr_reg:x8; val_offset:4233*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4233*FLEN/8, x10, x3, x5) + +inst_1434: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x22b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x16a and fs3 == 0 and fe3 == 0x10 and fm3 == 0x1bb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x522b; op2val:0xbd6a; +op3val:0x41bb; valaddr_reg:x8; val_offset:4236*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4236*FLEN/8, x10, x3, x5) + +inst_1435: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x1bc and fs2 == 1 and fe2 == 0x10 and fm2 == 0x252 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x042 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4dbc; op2val:0xc252; +op3val:0x4842; valaddr_reg:x8; val_offset:4239*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4239*FLEN/8, x10, x3, x5) + +inst_1436: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x1bc and fs2 == 1 and fe2 == 0x10 and fm2 == 0x252 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x042 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4dbc; op2val:0xc252; +op3val:0x4842; valaddr_reg:x8; val_offset:4242*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4242*FLEN/8, x10, x3, x5) + +inst_1437: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x1bc and fs2 == 1 and fe2 == 0x10 and fm2 == 0x252 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x042 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4dbc; op2val:0xc252; +op3val:0x4842; valaddr_reg:x8; val_offset:4245*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4245*FLEN/8, x10, x3, x5) + +inst_1438: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x1bc and fs2 == 1 and fe2 == 0x10 and fm2 == 0x252 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x042 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4dbc; op2val:0xc252; +op3val:0x4842; valaddr_reg:x8; val_offset:4248*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4248*FLEN/8, x10, x3, x5) + +inst_1439: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x1bc and fs2 == 1 and fe2 == 0x10 and fm2 == 0x252 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x042 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4dbc; op2val:0xc252; +op3val:0x4842; valaddr_reg:x8; val_offset:4251*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4251*FLEN/8, x10, x3, x5) + +inst_1440: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x031 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x206 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0a2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5031; op2val:0xc206; +op3val:0x50a2; valaddr_reg:x8; val_offset:4254*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4254*FLEN/8, x10, x3, x5) + +inst_1441: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x031 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x206 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0a2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5031; op2val:0xc206; +op3val:0x50a2; valaddr_reg:x8; val_offset:4257*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4257*FLEN/8, x10, x3, x5) + +inst_1442: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x031 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x206 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0a2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5031; op2val:0xc206; +op3val:0x50a2; valaddr_reg:x8; val_offset:4260*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4260*FLEN/8, x10, x3, x5) + +inst_1443: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x031 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x206 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0a2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5031; op2val:0xc206; +op3val:0x50a2; valaddr_reg:x8; val_offset:4263*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4263*FLEN/8, x10, x3, x5) + +inst_1444: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x031 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x206 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0a2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5031; op2val:0xc206; +op3val:0x50a2; valaddr_reg:x8; val_offset:4266*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4266*FLEN/8, x10, x3, x5) + +inst_1445: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x0b8 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ec and fs3 == 0 and fe3 == 0x13 and fm3 == 0x33c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x50b8; op2val:0xc0ec; +op3val:0x4f3c; valaddr_reg:x8; val_offset:4269*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4269*FLEN/8, x10, x3, x5) + +inst_1446: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x0b8 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ec and fs3 == 0 and fe3 == 0x13 and fm3 == 0x33c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x50b8; op2val:0xc0ec; +op3val:0x4f3c; valaddr_reg:x8; val_offset:4272*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4272*FLEN/8, x10, x3, x5) + +inst_1447: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x0b8 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ec and fs3 == 0 and fe3 == 0x13 and fm3 == 0x33c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x50b8; op2val:0xc0ec; +op3val:0x4f3c; valaddr_reg:x8; val_offset:4275*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4275*FLEN/8, x10, x3, x5) + +inst_1448: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x0b8 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ec and fs3 == 0 and fe3 == 0x13 and fm3 == 0x33c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x50b8; op2val:0xc0ec; +op3val:0x4f3c; valaddr_reg:x8; val_offset:4278*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4278*FLEN/8, x10, x3, x5) + +inst_1449: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x0b8 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ec and fs3 == 0 and fe3 == 0x13 and fm3 == 0x33c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x50b8; op2val:0xc0ec; +op3val:0x4f3c; valaddr_reg:x8; val_offset:4281*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4281*FLEN/8, x10, x3, x5) + +inst_1450: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x20c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x315 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x16c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4e0c; op2val:0xc315; +op3val:0x4d6c; valaddr_reg:x8; val_offset:4284*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4284*FLEN/8, x10, x3, x5) + +inst_1451: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x20c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x315 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x16c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4e0c; op2val:0xc315; +op3val:0x4d6c; valaddr_reg:x8; val_offset:4287*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4287*FLEN/8, x10, x3, x5) + +inst_1452: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x20c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x315 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x16c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4e0c; op2val:0xc315; +op3val:0x4d6c; valaddr_reg:x8; val_offset:4290*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4290*FLEN/8, x10, x3, x5) + +inst_1453: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x20c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x315 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x16c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4e0c; op2val:0xc315; +op3val:0x4d6c; valaddr_reg:x8; val_offset:4293*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4293*FLEN/8, x10, x3, x5) + +inst_1454: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x20c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x315 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x16c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4e0c; op2val:0xc315; +op3val:0x4d6c; valaddr_reg:x8; val_offset:4296*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4296*FLEN/8, x10, x3, x5) + +inst_1455: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x3b1 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x104 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x297 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x47b1; op2val:0xc904; +op3val:0x4a97; valaddr_reg:x8; val_offset:4299*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4299*FLEN/8, x10, x3, x5) + +inst_1456: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x3b1 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x104 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x297 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x47b1; op2val:0xc904; +op3val:0x4a97; valaddr_reg:x8; val_offset:4302*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4302*FLEN/8, x10, x3, x5) + +inst_1457: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x3b1 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x104 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x297 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x47b1; op2val:0xc904; +op3val:0x4a97; valaddr_reg:x8; val_offset:4305*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4305*FLEN/8, x10, x3, x5) + +inst_1458: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x3b1 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x104 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x297 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x47b1; op2val:0xc904; +op3val:0x4a97; valaddr_reg:x8; val_offset:4308*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4308*FLEN/8, x10, x3, x5) + +inst_1459: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x3b1 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x104 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x297 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x47b1; op2val:0xc904; +op3val:0x4a97; valaddr_reg:x8; val_offset:4311*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4311*FLEN/8, x10, x3, x5) + +inst_1460: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3ea and fs2 == 1 and fe2 == 0x10 and fm2 == 0x25d and fs3 == 0 and fe3 == 0x14 and fm3 == 0x098 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4fea; op2val:0xc25d; +op3val:0x5098; valaddr_reg:x8; val_offset:4314*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4314*FLEN/8, x10, x3, x5) + +inst_1461: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3ea and fs2 == 1 and fe2 == 0x10 and fm2 == 0x25d and fs3 == 0 and fe3 == 0x14 and fm3 == 0x098 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4fea; op2val:0xc25d; +op3val:0x5098; valaddr_reg:x8; val_offset:4317*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4317*FLEN/8, x10, x3, x5) + +inst_1462: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3ea and fs2 == 1 and fe2 == 0x10 and fm2 == 0x25d and fs3 == 0 and fe3 == 0x14 and fm3 == 0x098 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4fea; op2val:0xc25d; +op3val:0x5098; valaddr_reg:x8; val_offset:4320*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4320*FLEN/8, x10, x3, x5) + +inst_1463: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3ea and fs2 == 1 and fe2 == 0x10 and fm2 == 0x25d and fs3 == 0 and fe3 == 0x14 and fm3 == 0x098 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4fea; op2val:0xc25d; +op3val:0x5098; valaddr_reg:x8; val_offset:4323*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4323*FLEN/8, x10, x3, x5) + +inst_1464: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3ea and fs2 == 1 and fe2 == 0x10 and fm2 == 0x25d and fs3 == 0 and fe3 == 0x14 and fm3 == 0x098 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4fea; op2val:0xc25d; +op3val:0x5098; valaddr_reg:x8; val_offset:4326*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4326*FLEN/8, x10, x3, x5) + +inst_1465: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x355 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x008 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x2c8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4755; op2val:0xcc08; +op3val:0x52c8; valaddr_reg:x8; val_offset:4329*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4329*FLEN/8, x10, x3, x5) + +inst_1466: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x355 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x008 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x2c8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4755; op2val:0xcc08; +op3val:0x52c8; valaddr_reg:x8; val_offset:4332*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4332*FLEN/8, x10, x3, x5) + +inst_1467: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x355 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x008 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x2c8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4755; op2val:0xcc08; +op3val:0x52c8; valaddr_reg:x8; val_offset:4335*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4335*FLEN/8, x10, x3, x5) + +inst_1468: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x355 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x008 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x2c8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4755; op2val:0xcc08; +op3val:0x52c8; valaddr_reg:x8; val_offset:4338*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4338*FLEN/8, x10, x3, x5) + +inst_1469: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x355 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x008 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x2c8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4755; op2val:0xcc08; +op3val:0x52c8; valaddr_reg:x8; val_offset:4341*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4341*FLEN/8, x10, x3, x5) + +inst_1470: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x379 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x305 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bc8; op2val:0xbb79; +op3val:0x3b05; valaddr_reg:x8; val_offset:4344*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4344*FLEN/8, x10, x3, x5) + +inst_1471: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x379 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x305 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bc8; op2val:0xbb79; +op3val:0x3b05; valaddr_reg:x8; val_offset:4347*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4347*FLEN/8, x10, x3, x5) + +inst_1472: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x379 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x305 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bc8; op2val:0xbb79; +op3val:0x3b05; valaddr_reg:x8; val_offset:4350*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4350*FLEN/8, x10, x3, x5) + +inst_1473: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x379 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x305 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bc8; op2val:0xbb79; +op3val:0x3b05; valaddr_reg:x8; val_offset:4353*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4353*FLEN/8, x10, x3, x5) + +inst_1474: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x379 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x305 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bc8; op2val:0xbb79; +op3val:0x3b05; valaddr_reg:x8; val_offset:4356*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4356*FLEN/8, x10, x3, x5) + +inst_1475: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x087 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x102 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x16b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3887; op2val:0xbd02; +op3val:0x396b; valaddr_reg:x8; val_offset:4359*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4359*FLEN/8, x10, x3, x5) + +inst_1476: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x087 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x102 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x16b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3887; op2val:0xbd02; +op3val:0x396b; valaddr_reg:x8; val_offset:4362*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4362*FLEN/8, x10, x3, x5) + +inst_1477: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x087 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x102 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x16b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3887; op2val:0xbd02; +op3val:0x396b; valaddr_reg:x8; val_offset:4365*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4365*FLEN/8, x10, x3, x5) + +inst_1478: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x087 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x102 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x16b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3887; op2val:0xbd02; +op3val:0x396b; valaddr_reg:x8; val_offset:4368*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4368*FLEN/8, x10, x3, x5) + +inst_1479: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x087 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x102 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x16b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3887; op2val:0xbd02; +op3val:0x396b; valaddr_reg:x8; val_offset:4371*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4371*FLEN/8, x10, x3, x5) + +inst_1480: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1d9 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x14e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37f0; op2val:0xb9d9; +op3val:0x354e; valaddr_reg:x8; val_offset:4374*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4374*FLEN/8, x10, x3, x5) + +inst_1481: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1d9 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x14e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37f0; op2val:0xb9d9; +op3val:0x354e; valaddr_reg:x8; val_offset:4377*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4377*FLEN/8, x10, x3, x5) + +inst_1482: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1d9 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x14e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37f0; op2val:0xb9d9; +op3val:0x354e; valaddr_reg:x8; val_offset:4380*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4380*FLEN/8, x10, x3, x5) + +inst_1483: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1d9 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x14e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37f0; op2val:0xb9d9; +op3val:0x354e; valaddr_reg:x8; val_offset:4383*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4383*FLEN/8, x10, x3, x5) + +inst_1484: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1d9 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x14e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37f0; op2val:0xb9d9; +op3val:0x354e; valaddr_reg:x8; val_offset:4386*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4386*FLEN/8, x10, x3, x5) + +inst_1485: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2c8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x11c and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36c8; op2val:0xb91c; +op3val:0x33aa; valaddr_reg:x8; val_offset:4389*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4389*FLEN/8, x10, x3, x5) + +inst_1486: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2c8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x11c and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3aa and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36c8; op2val:0xb91c; +op3val:0x33aa; valaddr_reg:x8; val_offset:4392*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4392*FLEN/8, x10, x3, x5) + +inst_1487: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2c8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x11c and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3aa and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36c8; op2val:0xb91c; +op3val:0x33aa; valaddr_reg:x8; val_offset:4395*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4395*FLEN/8, x10, x3, x5) + +inst_1488: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2c8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x11c and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3aa and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36c8; op2val:0xb91c; +op3val:0x33aa; valaddr_reg:x8; val_offset:4398*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4398*FLEN/8, x10, x3, x5) + +inst_1489: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2c8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x11c and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3aa and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36c8; op2val:0xb91c; +op3val:0x33aa; valaddr_reg:x8; val_offset:4401*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4401*FLEN/8, x10, x3, x5) + +inst_1490: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x05b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x186 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x184 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x385b; op2val:0xb986; +op3val:0x3584; valaddr_reg:x8; val_offset:4404*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4404*FLEN/8, x10, x3, x5) + +inst_1491: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x05b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x186 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x184 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x385b; op2val:0xb986; +op3val:0x3584; valaddr_reg:x8; val_offset:4407*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4407*FLEN/8, x10, x3, x5) + +inst_1492: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x05b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x186 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x184 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x385b; op2val:0xb986; +op3val:0x3584; valaddr_reg:x8; val_offset:4410*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4410*FLEN/8, x10, x3, x5) + +inst_1493: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x05b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x186 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x184 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x385b; op2val:0xb986; +op3val:0x3584; valaddr_reg:x8; val_offset:4413*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4413*FLEN/8, x10, x3, x5) + +inst_1494: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x05b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x186 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x184 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x385b; op2val:0xb986; +op3val:0x3584; valaddr_reg:x8; val_offset:4416*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4416*FLEN/8, x10, x3, x5) + +inst_1495: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0c2 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x21c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x305 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38c2; op2val:0xbe1c; +op3val:0x3b05; valaddr_reg:x8; val_offset:4419*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4419*FLEN/8, x10, x3, x5) + +inst_1496: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0c2 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x21c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x305 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38c2; op2val:0xbe1c; +op3val:0x3b05; valaddr_reg:x8; val_offset:4422*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4422*FLEN/8, x10, x3, x5) + +inst_1497: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0c2 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x21c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x305 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38c2; op2val:0xbe1c; +op3val:0x3b05; valaddr_reg:x8; val_offset:4425*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4425*FLEN/8, x10, x3, x5) + +inst_1498: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0c2 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x21c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x305 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38c2; op2val:0xbe1c; +op3val:0x3b05; valaddr_reg:x8; val_offset:4428*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4428*FLEN/8, x10, x3, x5) + +inst_1499: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0c2 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x21c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x305 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38c2; op2val:0xbe1c; +op3val:0x3b05; valaddr_reg:x8; val_offset:4431*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4431*FLEN/8, x10, x3, x5) + +inst_1500: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x35e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x297 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b6c; op2val:0xbb5e; +op3val:0x3a97; valaddr_reg:x8; val_offset:4434*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4434*FLEN/8, x10, x3, x5) + +inst_1501: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x35e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x297 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b6c; op2val:0xbb5e; +op3val:0x3a97; valaddr_reg:x8; val_offset:4437*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4437*FLEN/8, x10, x3, x5) + +inst_1502: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x35e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x297 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b6c; op2val:0xbb5e; +op3val:0x3a97; valaddr_reg:x8; val_offset:4440*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4440*FLEN/8, x10, x3, x5) + +inst_1503: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x35e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x297 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b6c; op2val:0xbb5e; +op3val:0x3a97; valaddr_reg:x8; val_offset:4443*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4443*FLEN/8, x10, x3, x5) + +inst_1504: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x35e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x297 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b6c; op2val:0xbb5e; +op3val:0x3a97; valaddr_reg:x8; val_offset:4446*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4446*FLEN/8, x10, x3, x5) + +inst_1505: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x08f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x15c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1dc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x388f; op2val:0xbd5c; +op3val:0x39dc; valaddr_reg:x8; val_offset:4449*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4449*FLEN/8, x10, x3, x5) + +inst_1506: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x08f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x15c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1dc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x388f; op2val:0xbd5c; +op3val:0x39dc; valaddr_reg:x8; val_offset:4452*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4452*FLEN/8, x10, x3, x5) + +inst_1507: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x08f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x15c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1dc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x388f; op2val:0xbd5c; +op3val:0x39dc; valaddr_reg:x8; val_offset:4455*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4455*FLEN/8, x10, x3, x5) + +inst_1508: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x08f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x15c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1dc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x388f; op2val:0xbd5c; +op3val:0x39dc; valaddr_reg:x8; val_offset:4458*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4458*FLEN/8, x10, x3, x5) + +inst_1509: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x08f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x15c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1dc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x388f; op2val:0xbd5c; +op3val:0x39dc; valaddr_reg:x8; val_offset:4461*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4461*FLEN/8, x10, x3, x5) + +inst_1510: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x34f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2bd and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1a8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x374f; op2val:0xbabd; +op3val:0x35a8; valaddr_reg:x8; val_offset:4464*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4464*FLEN/8, x10, x3, x5) + +inst_1511: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x34f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2bd and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1a8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x374f; op2val:0xbabd; +op3val:0x35a8; valaddr_reg:x8; val_offset:4467*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4467*FLEN/8, x10, x3, x5) + +inst_1512: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x34f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2bd and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1a8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x374f; op2val:0xbabd; +op3val:0x35a8; valaddr_reg:x8; val_offset:4470*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4470*FLEN/8, x10, x3, x5) + +inst_1513: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x34f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2bd and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1a8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x374f; op2val:0xbabd; +op3val:0x35a8; valaddr_reg:x8; val_offset:4473*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4473*FLEN/8, x10, x3, x5) + +inst_1514: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x34f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2bd and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1a8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x374f; op2val:0xbabd; +op3val:0x35a8; valaddr_reg:x8; val_offset:4476*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4476*FLEN/8, x10, x3, x5) + +inst_1515: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x301 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x00c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2d6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f01; op2val:0xc80c; +op3val:0x3ad6; valaddr_reg:x8; val_offset:4479*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4479*FLEN/8, x10, x3, x5) + +inst_1516: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x301 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x00c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2d6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f01; op2val:0xc80c; +op3val:0x3ad6; valaddr_reg:x8; val_offset:4482*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4482*FLEN/8, x10, x3, x5) + +inst_1517: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x301 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x00c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2d6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f01; op2val:0xc80c; +op3val:0x3ad6; valaddr_reg:x8; val_offset:4485*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4485*FLEN/8, x10, x3, x5) + +inst_1518: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x301 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x00c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2d6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f01; op2val:0xc80c; +op3val:0x3ad6; valaddr_reg:x8; val_offset:4488*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4488*FLEN/8, x10, x3, x5) + +inst_1519: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x301 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x00c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2d6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f01; op2val:0xc80c; +op3val:0x3ad6; valaddr_reg:x8; val_offset:4491*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4491*FLEN/8, x10, x3, x5) + +inst_1520: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0a0 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x31f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3fd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ca0; op2val:0xcb1f; +op3val:0x3bfd; valaddr_reg:x8; val_offset:4494*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4494*FLEN/8, x10, x3, x5) + +inst_1521: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0a0 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x31f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3fd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ca0; op2val:0xcb1f; +op3val:0x3bfd; valaddr_reg:x8; val_offset:4497*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4497*FLEN/8, x10, x3, x5) + +inst_1522: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0a0 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x31f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3fd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ca0; op2val:0xcb1f; +op3val:0x3bfd; valaddr_reg:x8; val_offset:4500*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4500*FLEN/8, x10, x3, x5) + +inst_1523: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0a0 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x31f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3fd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ca0; op2val:0xcb1f; +op3val:0x3bfd; valaddr_reg:x8; val_offset:4503*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4503*FLEN/8, x10, x3, x5) + +inst_1524: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0a0 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x31f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3fd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ca0; op2val:0xcb1f; +op3val:0x3bfd; valaddr_reg:x8; val_offset:4506*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4506*FLEN/8, x10, x3, x5) + +inst_1525: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x06e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x076 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x1e2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x306e; op2val:0xb876; +op3val:0x29e2; valaddr_reg:x8; val_offset:4509*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4509*FLEN/8, x10, x3, x5) + +inst_1526: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x06e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x076 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x1e2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x306e; op2val:0xb876; +op3val:0x29e2; valaddr_reg:x8; val_offset:4512*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4512*FLEN/8, x10, x3, x5) + +inst_1527: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x06e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x076 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x1e2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x306e; op2val:0xb876; +op3val:0x29e2; valaddr_reg:x8; val_offset:4515*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4515*FLEN/8, x10, x3, x5) + +inst_1528: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x06e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x076 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x1e2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x306e; op2val:0xb876; +op3val:0x29e2; valaddr_reg:x8; val_offset:4518*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4518*FLEN/8, x10, x3, x5) + +inst_1529: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x06e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x076 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x1e2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x306e; op2val:0xb876; +op3val:0x29e2; valaddr_reg:x8; val_offset:4521*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4521*FLEN/8, x10, x3, x5) + +inst_1530: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x12b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x261 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x33e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x392b; op2val:0xb661; +op3val:0x333e; valaddr_reg:x8; val_offset:4524*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4524*FLEN/8, x10, x3, x5) + +inst_1531: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x12b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x261 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x33e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x392b; op2val:0xb661; +op3val:0x333e; valaddr_reg:x8; val_offset:4527*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4527*FLEN/8, x10, x3, x5) + +inst_1532: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x12b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x261 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x33e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x392b; op2val:0xb661; +op3val:0x333e; valaddr_reg:x8; val_offset:4530*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4530*FLEN/8, x10, x3, x5) + +inst_1533: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x12b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x261 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x33e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x392b; op2val:0xb661; +op3val:0x333e; valaddr_reg:x8; val_offset:4533*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4533*FLEN/8, x10, x3, x5) + +inst_1534: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x12b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x261 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x33e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x392b; op2val:0xb661; +op3val:0x333e; valaddr_reg:x8; val_offset:4536*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4536*FLEN/8, x10, x3, x5) + +inst_1535: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x015 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3a0 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x349 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3815; op2val:0xbba0; +op3val:0x3749; valaddr_reg:x8; val_offset:4539*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4539*FLEN/8, x10, x3, x5) + +inst_1536: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x015 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3a0 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x349 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3815; op2val:0xbba0; +op3val:0x3749; valaddr_reg:x8; val_offset:4542*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4542*FLEN/8, x10, x3, x5) + +inst_1537: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x015 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3a0 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x349 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3815; op2val:0xbba0; +op3val:0x3749; valaddr_reg:x8; val_offset:4545*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4545*FLEN/8, x10, x3, x5) + +inst_1538: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x015 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3a0 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x349 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3815; op2val:0xbba0; +op3val:0x3749; valaddr_reg:x8; val_offset:4548*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4548*FLEN/8, x10, x3, x5) + +inst_1539: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x015 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3a0 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x349 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3815; op2val:0xbba0; +op3val:0x3749; valaddr_reg:x8; val_offset:4551*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4551*FLEN/8, x10, x3, x5) + +inst_1540: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x16c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x19f and fs3 == 0 and fe3 == 0x0b and fm3 == 0x19e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x316c; op2val:0xb99f; +op3val:0x2d9e; valaddr_reg:x8; val_offset:4554*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4554*FLEN/8, x10, x3, x5) + +inst_1541: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x16c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x19f and fs3 == 0 and fe3 == 0x0b and fm3 == 0x19e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x316c; op2val:0xb99f; +op3val:0x2d9e; valaddr_reg:x8; val_offset:4557*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4557*FLEN/8, x10, x3, x5) + +inst_1542: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x16c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x19f and fs3 == 0 and fe3 == 0x0b and fm3 == 0x19e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x316c; op2val:0xb99f; +op3val:0x2d9e; valaddr_reg:x8; val_offset:4560*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4560*FLEN/8, x10, x3, x5) + +inst_1543: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x16c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x19f and fs3 == 0 and fe3 == 0x0b and fm3 == 0x19e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x316c; op2val:0xb99f; +op3val:0x2d9e; valaddr_reg:x8; val_offset:4563*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4563*FLEN/8, x10, x3, x5) + +inst_1544: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x16c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x19f and fs3 == 0 and fe3 == 0x0b and fm3 == 0x19e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x316c; op2val:0xb99f; +op3val:0x2d9e; valaddr_reg:x8; val_offset:4566*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4566*FLEN/8, x10, x3, x5) + +inst_1545: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ac and fs2 == 1 and fe2 == 0x0f and fm2 == 0x09d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x24c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39ac; op2val:0xbc9d; +op3val:0x3a4c; valaddr_reg:x8; val_offset:4569*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4569*FLEN/8, x10, x3, x5) + +inst_1546: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ac and fs2 == 1 and fe2 == 0x0f and fm2 == 0x09d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x24c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39ac; op2val:0xbc9d; +op3val:0x3a4c; valaddr_reg:x8; val_offset:4572*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4572*FLEN/8, x10, x3, x5) + +inst_1547: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ac and fs2 == 1 and fe2 == 0x0f and fm2 == 0x09d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x24c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39ac; op2val:0xbc9d; +op3val:0x3a4c; valaddr_reg:x8; val_offset:4575*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4575*FLEN/8, x10, x3, x5) + +inst_1548: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ac and fs2 == 1 and fe2 == 0x0f and fm2 == 0x09d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x24c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39ac; op2val:0xbc9d; +op3val:0x3a4c; valaddr_reg:x8; val_offset:4578*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4578*FLEN/8, x10, x3, x5) + +inst_1549: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ac and fs2 == 1 and fe2 == 0x0f and fm2 == 0x09d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x24c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39ac; op2val:0xbc9d; +op3val:0x3a4c; valaddr_reg:x8; val_offset:4581*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4581*FLEN/8, x10, x3, x5) + +inst_1550: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x330 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x013 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2d3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f30; op2val:0xc413; +op3val:0x36d3; valaddr_reg:x8; val_offset:4584*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4584*FLEN/8, x10, x3, x5) + +inst_1551: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x330 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x013 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2d3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f30; op2val:0xc413; +op3val:0x36d3; valaddr_reg:x8; val_offset:4587*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4587*FLEN/8, x10, x3, x5) + +inst_1552: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x330 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x013 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2d3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f30; op2val:0xc413; +op3val:0x36d3; valaddr_reg:x8; val_offset:4590*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4590*FLEN/8, x10, x3, x5) + +inst_1553: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x330 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x013 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2d3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f30; op2val:0xc413; +op3val:0x36d3; valaddr_reg:x8; val_offset:4593*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4593*FLEN/8, x10, x3, x5) + +inst_1554: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x330 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x013 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2d3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f30; op2val:0xc413; +op3val:0x36d3; valaddr_reg:x8; val_offset:4596*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4596*FLEN/8, x10, x3, x5) + +inst_1555: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x00b and fs2 == 1 and fe2 == 0x11 and fm2 == 0x276 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x249 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x300b; op2val:0xc676; +op3val:0x3a49; valaddr_reg:x8; val_offset:4599*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4599*FLEN/8, x10, x3, x5) + +inst_1556: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x00b and fs2 == 1 and fe2 == 0x11 and fm2 == 0x276 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x249 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x300b; op2val:0xc676; +op3val:0x3a49; valaddr_reg:x8; val_offset:4602*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4602*FLEN/8, x10, x3, x5) + +inst_1557: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x00b and fs2 == 1 and fe2 == 0x11 and fm2 == 0x276 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x249 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x300b; op2val:0xc676; +op3val:0x3a49; valaddr_reg:x8; val_offset:4605*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4605*FLEN/8, x10, x3, x5) + +inst_1558: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x00b and fs2 == 1 and fe2 == 0x11 and fm2 == 0x276 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x249 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x300b; op2val:0xc676; +op3val:0x3a49; valaddr_reg:x8; val_offset:4608*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4608*FLEN/8, x10, x3, x5) + +inst_1559: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x00b and fs2 == 1 and fe2 == 0x11 and fm2 == 0x276 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x249 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x300b; op2val:0xc676; +op3val:0x3a49; valaddr_reg:x8; val_offset:4611*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4611*FLEN/8, x10, x3, x5) +RVTEST_SIGBASE(x3,signature_x3_12) + +inst_1560: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1ad and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0f1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2c3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31ad; op2val:0xc4f1; +op3val:0x3ac3; valaddr_reg:x8; val_offset:4614*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4614*FLEN/8, x10, x3, x5) + +inst_1561: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1ad and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0f1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2c3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31ad; op2val:0xc4f1; +op3val:0x3ac3; valaddr_reg:x8; val_offset:4617*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4617*FLEN/8, x10, x3, x5) + +inst_1562: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1ad and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0f1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2c3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31ad; op2val:0xc4f1; +op3val:0x3ac3; valaddr_reg:x8; val_offset:4620*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4620*FLEN/8, x10, x3, x5) + +inst_1563: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1ad and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0f1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2c3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31ad; op2val:0xc4f1; +op3val:0x3ac3; valaddr_reg:x8; val_offset:4623*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4623*FLEN/8, x10, x3, x5) + +inst_1564: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1ad and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0f1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2c3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31ad; op2val:0xc4f1; +op3val:0x3ac3; valaddr_reg:x8; val_offset:4626*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4626*FLEN/8, x10, x3, x5) + +inst_1565: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2dc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x303 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1c3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3adc; op2val:0xbb03; +op3val:0x39c3; valaddr_reg:x8; val_offset:4629*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4629*FLEN/8, x10, x3, x5) + +inst_1566: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2dc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x303 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1c3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3adc; op2val:0xbb03; +op3val:0x39c3; valaddr_reg:x8; val_offset:4632*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4632*FLEN/8, x10, x3, x5) + +inst_1567: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2dc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x303 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1c3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3adc; op2val:0xbb03; +op3val:0x39c3; valaddr_reg:x8; val_offset:4635*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4635*FLEN/8, x10, x3, x5) + +inst_1568: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2dc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x303 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1c3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3adc; op2val:0xbb03; +op3val:0x39c3; valaddr_reg:x8; val_offset:4638*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4638*FLEN/8, x10, x3, x5) + +inst_1569: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2dc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x303 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1c3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3adc; op2val:0xbb03; +op3val:0x39c3; valaddr_reg:x8; val_offset:4641*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4641*FLEN/8, x10, x3, x5) + +inst_1570: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x27d and fs2 == 1 and fe2 == 0x11 and fm2 == 0x277 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e7d; op2val:0xc677; +op3val:0x38ff; valaddr_reg:x8; val_offset:4644*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4644*FLEN/8, x10, x3, x5) + +inst_1571: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x27d and fs2 == 1 and fe2 == 0x11 and fm2 == 0x277 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e7d; op2val:0xc677; +op3val:0x38ff; valaddr_reg:x8; val_offset:4647*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4647*FLEN/8, x10, x3, x5) + +inst_1572: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x27d and fs2 == 1 and fe2 == 0x11 and fm2 == 0x277 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e7d; op2val:0xc677; +op3val:0x38ff; valaddr_reg:x8; val_offset:4650*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4650*FLEN/8, x10, x3, x5) + +inst_1573: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x27d and fs2 == 1 and fe2 == 0x11 and fm2 == 0x277 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e7d; op2val:0xc677; +op3val:0x38ff; valaddr_reg:x8; val_offset:4653*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4653*FLEN/8, x10, x3, x5) + +inst_1574: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x27d and fs2 == 1 and fe2 == 0x11 and fm2 == 0x277 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e7d; op2val:0xc677; +op3val:0x38ff; valaddr_reg:x8; val_offset:4656*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4656*FLEN/8, x10, x3, x5) + +inst_1575: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x096 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x13d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1c2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3896; op2val:0xbd3d; +op3val:0x39c2; valaddr_reg:x8; val_offset:4659*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4659*FLEN/8, x10, x3, x5) + +inst_1576: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x096 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x13d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1c2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3896; op2val:0xbd3d; +op3val:0x39c2; valaddr_reg:x8; val_offset:4662*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4662*FLEN/8, x10, x3, x5) + +inst_1577: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x096 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x13d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1c2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3896; op2val:0xbd3d; +op3val:0x39c2; valaddr_reg:x8; val_offset:4665*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4665*FLEN/8, x10, x3, x5) + +inst_1578: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x096 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x13d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1c2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3896; op2val:0xbd3d; +op3val:0x39c2; valaddr_reg:x8; val_offset:4668*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4668*FLEN/8, x10, x3, x5) + +inst_1579: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x096 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x13d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1c2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3896; op2val:0xbd3d; +op3val:0x39c2; valaddr_reg:x8; val_offset:4671*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4671*FLEN/8, x10, x3, x5) + +inst_1580: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x134 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x093 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b6b; op2val:0xb934; +op3val:0x3893; valaddr_reg:x8; val_offset:4674*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4674*FLEN/8, x10, x3, x5) + +inst_1581: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x134 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x093 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b6b; op2val:0xb934; +op3val:0x3893; valaddr_reg:x8; val_offset:4677*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4677*FLEN/8, x10, x3, x5) + +inst_1582: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x134 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x093 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b6b; op2val:0xb934; +op3val:0x3893; valaddr_reg:x8; val_offset:4680*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4680*FLEN/8, x10, x3, x5) + +inst_1583: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x134 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x093 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b6b; op2val:0xb934; +op3val:0x3893; valaddr_reg:x8; val_offset:4683*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4683*FLEN/8, x10, x3, x5) + +inst_1584: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x134 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x093 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b6b; op2val:0xb934; +op3val:0x3893; valaddr_reg:x8; val_offset:4686*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4686*FLEN/8, x10, x3, x5) + +inst_1585: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x026 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x173 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x168 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3826; op2val:0xbd73; +op3val:0x3968; valaddr_reg:x8; val_offset:4689*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4689*FLEN/8, x10, x3, x5) + +inst_1586: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x026 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x173 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x168 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3826; op2val:0xbd73; +op3val:0x3968; valaddr_reg:x8; val_offset:4692*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4692*FLEN/8, x10, x3, x5) + +inst_1587: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x026 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x173 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x168 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3826; op2val:0xbd73; +op3val:0x3968; valaddr_reg:x8; val_offset:4695*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4695*FLEN/8, x10, x3, x5) + +inst_1588: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x026 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x173 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x168 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3826; op2val:0xbd73; +op3val:0x3968; valaddr_reg:x8; val_offset:4698*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4698*FLEN/8, x10, x3, x5) + +inst_1589: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x026 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x173 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x168 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3826; op2val:0xbd73; +op3val:0x3968; valaddr_reg:x8; val_offset:4701*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4701*FLEN/8, x10, x3, x5) + +inst_1590: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ac and fs2 == 1 and fe2 == 0x10 and fm2 == 0x101 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x199 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34ac; op2val:0xc101; +op3val:0x3999; valaddr_reg:x8; val_offset:4704*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4704*FLEN/8, x10, x3, x5) + +inst_1591: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ac and fs2 == 1 and fe2 == 0x10 and fm2 == 0x101 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x199 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34ac; op2val:0xc101; +op3val:0x3999; valaddr_reg:x8; val_offset:4707*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4707*FLEN/8, x10, x3, x5) + +inst_1592: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ac and fs2 == 1 and fe2 == 0x10 and fm2 == 0x101 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x199 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34ac; op2val:0xc101; +op3val:0x3999; valaddr_reg:x8; val_offset:4710*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4710*FLEN/8, x10, x3, x5) + +inst_1593: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ac and fs2 == 1 and fe2 == 0x10 and fm2 == 0x101 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x199 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34ac; op2val:0xc101; +op3val:0x3999; valaddr_reg:x8; val_offset:4713*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4713*FLEN/8, x10, x3, x5) + +inst_1594: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ac and fs2 == 1 and fe2 == 0x10 and fm2 == 0x101 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x199 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34ac; op2val:0xc101; +op3val:0x3999; valaddr_reg:x8; val_offset:4716*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4716*FLEN/8, x10, x3, x5) + +inst_1595: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x288 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e3 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x39f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2a88; op2val:0xc1e3; +op3val:0x2f9f; valaddr_reg:x8; val_offset:4719*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4719*FLEN/8, x10, x3, x5) + +inst_1596: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x288 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e3 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x39f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2a88; op2val:0xc1e3; +op3val:0x2f9f; valaddr_reg:x8; val_offset:4722*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4722*FLEN/8, x10, x3, x5) + +inst_1597: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x288 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e3 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x39f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2a88; op2val:0xc1e3; +op3val:0x2f9f; valaddr_reg:x8; val_offset:4725*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4725*FLEN/8, x10, x3, x5) + +inst_1598: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x288 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e3 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x39f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2a88; op2val:0xc1e3; +op3val:0x2f9f; valaddr_reg:x8; val_offset:4728*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4728*FLEN/8, x10, x3, x5) + +inst_1599: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x288 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e3 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x39f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2a88; op2val:0xc1e3; +op3val:0x2f9f; valaddr_reg:x8; val_offset:4731*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4731*FLEN/8, x10, x3, x5) + +inst_1600: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x307 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x03f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x336 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3707; op2val:0xc03f; +op3val:0x3b36; valaddr_reg:x8; val_offset:4734*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4734*FLEN/8, x10, x3, x5) + +inst_1601: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x307 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x03f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x336 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3707; op2val:0xc03f; +op3val:0x3b36; valaddr_reg:x8; val_offset:4737*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4737*FLEN/8, x10, x3, x5) + +inst_1602: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x307 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x03f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x336 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3707; op2val:0xc03f; +op3val:0x3b36; valaddr_reg:x8; val_offset:4740*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4740*FLEN/8, x10, x3, x5) + +inst_1603: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x307 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x03f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x336 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3707; op2val:0xc03f; +op3val:0x3b36; valaddr_reg:x8; val_offset:4743*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4743*FLEN/8, x10, x3, x5) + +inst_1604: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x307 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x03f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x336 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3707; op2val:0xc03f; +op3val:0x3b36; valaddr_reg:x8; val_offset:4746*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4746*FLEN/8, x10, x3, x5) + +inst_1605: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x353 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x382 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x25f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3753; op2val:0xbb82; +op3val:0x365f; valaddr_reg:x8; val_offset:4749*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4749*FLEN/8, x10, x3, x5) + +inst_1606: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x353 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x382 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x25f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3753; op2val:0xbb82; +op3val:0x365f; valaddr_reg:x8; val_offset:4752*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4752*FLEN/8, x10, x3, x5) + +inst_1607: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x353 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x382 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x25f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3753; op2val:0xbb82; +op3val:0x365f; valaddr_reg:x8; val_offset:4755*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4755*FLEN/8, x10, x3, x5) + +inst_1608: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x353 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x382 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x25f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3753; op2val:0xbb82; +op3val:0x365f; valaddr_reg:x8; val_offset:4758*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4758*FLEN/8, x10, x3, x5) + +inst_1609: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x353 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x382 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x25f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3753; op2val:0xbb82; +op3val:0x365f; valaddr_reg:x8; val_offset:4761*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4761*FLEN/8, x10, x3, x5) + +inst_1610: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ec and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2b0 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0b4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35ec; op2val:0xbeb0; +op3val:0x38b4; valaddr_reg:x8; val_offset:4764*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4764*FLEN/8, x10, x3, x5) + +inst_1611: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ec and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2b0 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0b4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35ec; op2val:0xbeb0; +op3val:0x38b4; valaddr_reg:x8; val_offset:4767*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4767*FLEN/8, x10, x3, x5) + +inst_1612: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ec and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2b0 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0b4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35ec; op2val:0xbeb0; +op3val:0x38b4; valaddr_reg:x8; val_offset:4770*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4770*FLEN/8, x10, x3, x5) + +inst_1613: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ec and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2b0 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0b4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35ec; op2val:0xbeb0; +op3val:0x38b4; valaddr_reg:x8; val_offset:4773*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4773*FLEN/8, x10, x3, x5) + +inst_1614: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ec and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2b0 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0b4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35ec; op2val:0xbeb0; +op3val:0x38b4; valaddr_reg:x8; val_offset:4776*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4776*FLEN/8, x10, x3, x5) + +inst_1615: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0c3 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x310 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x068 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34c3; op2val:0xb310; +op3val:0x2868; valaddr_reg:x8; val_offset:4779*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4779*FLEN/8, x10, x3, x5) + +inst_1616: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0c3 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x310 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x068 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34c3; op2val:0xb310; +op3val:0x2868; valaddr_reg:x8; val_offset:4782*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4782*FLEN/8, x10, x3, x5) + +inst_1617: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0c3 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x310 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x068 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34c3; op2val:0xb310; +op3val:0x2868; valaddr_reg:x8; val_offset:4785*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4785*FLEN/8, x10, x3, x5) + +inst_1618: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0c3 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x310 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x068 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34c3; op2val:0xb310; +op3val:0x2868; valaddr_reg:x8; val_offset:4788*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4788*FLEN/8, x10, x3, x5) + +inst_1619: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0c3 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x310 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x068 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34c3; op2val:0xb310; +op3val:0x2868; valaddr_reg:x8; val_offset:4791*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4791*FLEN/8, x10, x3, x5) + +inst_1620: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x11d and fs2 == 1 and fe2 == 0x10 and fm2 == 0x234 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3ae and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x351d; op2val:0xc234; +op3val:0x3bae; valaddr_reg:x8; val_offset:4794*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4794*FLEN/8, x10, x3, x5) + +inst_1621: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x11d and fs2 == 1 and fe2 == 0x10 and fm2 == 0x234 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3ae and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x351d; op2val:0xc234; +op3val:0x3bae; valaddr_reg:x8; val_offset:4797*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4797*FLEN/8, x10, x3, x5) + +inst_1622: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x11d and fs2 == 1 and fe2 == 0x10 and fm2 == 0x234 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3ae and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x351d; op2val:0xc234; +op3val:0x3bae; valaddr_reg:x8; val_offset:4800*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4800*FLEN/8, x10, x3, x5) + +inst_1623: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x11d and fs2 == 1 and fe2 == 0x10 and fm2 == 0x234 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3ae and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x351d; op2val:0xc234; +op3val:0x3bae; valaddr_reg:x8; val_offset:4803*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4803*FLEN/8, x10, x3, x5) + +inst_1624: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x11d and fs2 == 1 and fe2 == 0x10 and fm2 == 0x234 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3ae and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x351d; op2val:0xc234; +op3val:0x3bae; valaddr_reg:x8; val_offset:4806*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4806*FLEN/8, x10, x3, x5) + +inst_1625: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x243 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x05e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x257 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3643; op2val:0xbc5e; +op3val:0x3657; valaddr_reg:x8; val_offset:4809*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4809*FLEN/8, x10, x3, x5) + +inst_1626: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x243 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x05e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x257 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3643; op2val:0xbc5e; +op3val:0x3657; valaddr_reg:x8; val_offset:4812*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4812*FLEN/8, x10, x3, x5) + +inst_1627: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x243 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x05e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x257 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3643; op2val:0xbc5e; +op3val:0x3657; valaddr_reg:x8; val_offset:4815*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4815*FLEN/8, x10, x3, x5) + +inst_1628: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x243 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x05e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x257 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3643; op2val:0xbc5e; +op3val:0x3657; valaddr_reg:x8; val_offset:4818*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4818*FLEN/8, x10, x3, x5) + +inst_1629: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x243 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x05e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x257 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3643; op2val:0xbc5e; +op3val:0x3657; valaddr_reg:x8; val_offset:4821*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4821*FLEN/8, x10, x3, x5) + +inst_1630: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x38c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x026 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1d4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x378c; op2val:0xb426; +op3val:0x2dd4; valaddr_reg:x8; val_offset:4824*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4824*FLEN/8, x10, x3, x5) + +inst_1631: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x38c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x026 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1d4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x378c; op2val:0xb426; +op3val:0x2dd4; valaddr_reg:x8; val_offset:4827*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4827*FLEN/8, x10, x3, x5) + +inst_1632: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x38c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x026 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1d4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x378c; op2val:0xb426; +op3val:0x2dd4; valaddr_reg:x8; val_offset:4830*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4830*FLEN/8, x10, x3, x5) + +inst_1633: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x38c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x026 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1d4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x378c; op2val:0xb426; +op3val:0x2dd4; valaddr_reg:x8; val_offset:4833*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4833*FLEN/8, x10, x3, x5) + +inst_1634: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x38c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x026 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1d4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x378c; op2val:0xb426; +op3val:0x2dd4; valaddr_reg:x8; val_offset:4836*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4836*FLEN/8, x10, x3, x5) + +inst_1635: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x398 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x046 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3dd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b98; op2val:0xbc46; +op3val:0x3bdd; valaddr_reg:x8; val_offset:4839*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4839*FLEN/8, x10, x3, x5) + +inst_1636: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x398 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x046 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3dd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b98; op2val:0xbc46; +op3val:0x3bdd; valaddr_reg:x8; val_offset:4842*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4842*FLEN/8, x10, x3, x5) + +inst_1637: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x398 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x046 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3dd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b98; op2val:0xbc46; +op3val:0x3bdd; valaddr_reg:x8; val_offset:4845*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4845*FLEN/8, x10, x3, x5) + +inst_1638: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x398 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x046 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3dd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b98; op2val:0xbc46; +op3val:0x3bdd; valaddr_reg:x8; val_offset:4848*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4848*FLEN/8, x10, x3, x5) + +inst_1639: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x398 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x046 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3dd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b98; op2val:0xbc46; +op3val:0x3bdd; valaddr_reg:x8; val_offset:4851*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4851*FLEN/8, x10, x3, x5) + +inst_1640: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ce and fs2 == 1 and fe2 == 0x10 and fm2 == 0x238 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x338 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34ce; op2val:0xc238; +op3val:0x3b38; valaddr_reg:x8; val_offset:4854*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4854*FLEN/8, x10, x3, x5) + +inst_1641: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ce and fs2 == 1 and fe2 == 0x10 and fm2 == 0x238 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x338 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34ce; op2val:0xc238; +op3val:0x3b38; valaddr_reg:x8; val_offset:4857*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4857*FLEN/8, x10, x3, x5) + +inst_1642: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ce and fs2 == 1 and fe2 == 0x10 and fm2 == 0x238 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x338 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34ce; op2val:0xc238; +op3val:0x3b38; valaddr_reg:x8; val_offset:4860*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4860*FLEN/8, x10, x3, x5) + +inst_1643: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ce and fs2 == 1 and fe2 == 0x10 and fm2 == 0x238 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x338 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34ce; op2val:0xc238; +op3val:0x3b38; valaddr_reg:x8; val_offset:4863*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4863*FLEN/8, x10, x3, x5) + +inst_1644: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ce and fs2 == 1 and fe2 == 0x10 and fm2 == 0x238 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x338 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34ce; op2val:0xc238; +op3val:0x3b38; valaddr_reg:x8; val_offset:4866*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4866*FLEN/8, x10, x3, x5) + +inst_1645: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x0d and fm2 == 0x06b and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2a9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aef; op2val:0xb46b; +op3val:0x32a9; valaddr_reg:x8; val_offset:4869*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4869*FLEN/8, x10, x3, x5) + +inst_1646: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x0d and fm2 == 0x06b and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2a9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aef; op2val:0xb46b; +op3val:0x32a9; valaddr_reg:x8; val_offset:4872*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4872*FLEN/8, x10, x3, x5) + +inst_1647: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x0d and fm2 == 0x06b and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2a9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aef; op2val:0xb46b; +op3val:0x32a9; valaddr_reg:x8; val_offset:4875*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4875*FLEN/8, x10, x3, x5) + +inst_1648: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x0d and fm2 == 0x06b and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2a9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aef; op2val:0xb46b; +op3val:0x32a9; valaddr_reg:x8; val_offset:4878*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4878*FLEN/8, x10, x3, x5) + +inst_1649: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x0d and fm2 == 0x06b and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2a9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aef; op2val:0xb46b; +op3val:0x32a9; valaddr_reg:x8; val_offset:4881*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4881*FLEN/8, x10, x3, x5) + +inst_1650: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x132 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x052 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x09e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3932; op2val:0xb452; +op3val:0x309e; valaddr_reg:x8; val_offset:4884*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4884*FLEN/8, x10, x3, x5) + +inst_1651: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x132 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x052 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x09e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3932; op2val:0xb452; +op3val:0x309e; valaddr_reg:x8; val_offset:4887*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4887*FLEN/8, x10, x3, x5) + +inst_1652: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x132 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x052 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x09e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3932; op2val:0xb452; +op3val:0x309e; valaddr_reg:x8; val_offset:4890*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4890*FLEN/8, x10, x3, x5) + +inst_1653: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x132 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x052 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x09e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3932; op2val:0xb452; +op3val:0x309e; valaddr_reg:x8; val_offset:4893*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4893*FLEN/8, x10, x3, x5) + +inst_1654: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x132 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x052 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x09e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3932; op2val:0xb452; +op3val:0x309e; valaddr_reg:x8; val_offset:4896*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4896*FLEN/8, x10, x3, x5) + +inst_1655: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x32c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2f2 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1ba and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x332c; op2val:0xbef2; +op3val:0x35ba; valaddr_reg:x8; val_offset:4899*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4899*FLEN/8, x10, x3, x5) + +inst_1656: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x32c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2f2 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1ba and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x332c; op2val:0xbef2; +op3val:0x35ba; valaddr_reg:x8; val_offset:4902*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4902*FLEN/8, x10, x3, x5) + +inst_1657: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x32c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2f2 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1ba and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x332c; op2val:0xbef2; +op3val:0x35ba; valaddr_reg:x8; val_offset:4905*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4905*FLEN/8, x10, x3, x5) + +inst_1658: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x32c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2f2 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1ba and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x332c; op2val:0xbef2; +op3val:0x35ba; valaddr_reg:x8; val_offset:4908*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4908*FLEN/8, x10, x3, x5) + +inst_1659: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x32c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2f2 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1ba and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x332c; op2val:0xbef2; +op3val:0x35ba; valaddr_reg:x8; val_offset:4911*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4911*FLEN/8, x10, x3, x5) + +inst_1660: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x138 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1d5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x35c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3938; op2val:0xbdd5; +op3val:0x3b5c; valaddr_reg:x8; val_offset:4914*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4914*FLEN/8, x10, x3, x5) + +inst_1661: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x138 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1d5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x35c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3938; op2val:0xbdd5; +op3val:0x3b5c; valaddr_reg:x8; val_offset:4917*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4917*FLEN/8, x10, x3, x5) + +inst_1662: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x138 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1d5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x35c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3938; op2val:0xbdd5; +op3val:0x3b5c; valaddr_reg:x8; val_offset:4920*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4920*FLEN/8, x10, x3, x5) + +inst_1663: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x138 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1d5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x35c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3938; op2val:0xbdd5; +op3val:0x3b5c; valaddr_reg:x8; val_offset:4923*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4923*FLEN/8, x10, x3, x5) + +inst_1664: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x138 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1d5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x35c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3938; op2val:0xbdd5; +op3val:0x3b5c; valaddr_reg:x8; val_offset:4926*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4926*FLEN/8, x10, x3, x5) + +inst_1665: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2f7 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2e6 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x102 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2af7; op2val:0xc2e6; +op3val:0x3102; valaddr_reg:x8; val_offset:4929*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4929*FLEN/8, x10, x3, x5) + +inst_1666: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2f7 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2e6 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x102 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2af7; op2val:0xc2e6; +op3val:0x3102; valaddr_reg:x8; val_offset:4932*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4932*FLEN/8, x10, x3, x5) + +inst_1667: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2f7 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2e6 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x102 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2af7; op2val:0xc2e6; +op3val:0x3102; valaddr_reg:x8; val_offset:4935*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4935*FLEN/8, x10, x3, x5) + +inst_1668: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2f7 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2e6 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x102 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2af7; op2val:0xc2e6; +op3val:0x3102; valaddr_reg:x8; val_offset:4938*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4938*FLEN/8, x10, x3, x5) + +inst_1669: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2f7 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2e6 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x102 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2af7; op2val:0xc2e6; +op3val:0x3102; valaddr_reg:x8; val_offset:4941*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4941*FLEN/8, x10, x3, x5) + +inst_1670: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x320 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0d5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x00e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f20; op2val:0xc4d5; +op3val:0x380e; valaddr_reg:x8; val_offset:4944*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4944*FLEN/8, x10, x3, x5) + +inst_1671: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x320 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0d5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x00e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f20; op2val:0xc4d5; +op3val:0x380e; valaddr_reg:x8; val_offset:4947*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4947*FLEN/8, x10, x3, x5) + +inst_1672: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x320 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0d5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x00e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f20; op2val:0xc4d5; +op3val:0x380e; valaddr_reg:x8; val_offset:4950*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4950*FLEN/8, x10, x3, x5) + +inst_1673: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x320 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0d5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x00e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f20; op2val:0xc4d5; +op3val:0x380e; valaddr_reg:x8; val_offset:4953*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4953*FLEN/8, x10, x3, x5) + +inst_1674: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x320 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0d5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x00e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f20; op2val:0xc4d5; +op3val:0x380e; valaddr_reg:x8; val_offset:4956*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4956*FLEN/8, x10, x3, x5) + +inst_1675: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1d2 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0a6 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x245 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39d2; op2val:0xb8a6; +op3val:0x3645; valaddr_reg:x8; val_offset:4959*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4959*FLEN/8, x10, x3, x5) + +inst_1676: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1d2 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0a6 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x245 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39d2; op2val:0xb8a6; +op3val:0x3645; valaddr_reg:x8; val_offset:4962*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4962*FLEN/8, x10, x3, x5) + +inst_1677: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1d2 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0a6 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x245 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39d2; op2val:0xb8a6; +op3val:0x3645; valaddr_reg:x8; val_offset:4965*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4965*FLEN/8, x10, x3, x5) + +inst_1678: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1d2 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0a6 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x245 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39d2; op2val:0xb8a6; +op3val:0x3645; valaddr_reg:x8; val_offset:4968*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4968*FLEN/8, x10, x3, x5) + +inst_1679: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1d2 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0a6 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x245 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39d2; op2val:0xb8a6; +op3val:0x3645; valaddr_reg:x8; val_offset:4971*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4971*FLEN/8, x10, x3, x5) + +inst_1680: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x22f and fs2 == 1 and fe2 == 0x0a and fm2 == 0x23d and fs3 == 0 and fe3 == 0x0a and fm3 == 0x0d3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a2f; op2val:0xaa3d; +op3val:0x28d3; valaddr_reg:x8; val_offset:4974*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4974*FLEN/8, x10, x3, x5) + +inst_1681: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x22f and fs2 == 1 and fe2 == 0x0a and fm2 == 0x23d and fs3 == 0 and fe3 == 0x0a and fm3 == 0x0d3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a2f; op2val:0xaa3d; +op3val:0x28d3; valaddr_reg:x8; val_offset:4977*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4977*FLEN/8, x10, x3, x5) + +inst_1682: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x22f and fs2 == 1 and fe2 == 0x0a and fm2 == 0x23d and fs3 == 0 and fe3 == 0x0a and fm3 == 0x0d3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a2f; op2val:0xaa3d; +op3val:0x28d3; valaddr_reg:x8; val_offset:4980*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4980*FLEN/8, x10, x3, x5) + +inst_1683: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x22f and fs2 == 1 and fe2 == 0x0a and fm2 == 0x23d and fs3 == 0 and fe3 == 0x0a and fm3 == 0x0d3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a2f; op2val:0xaa3d; +op3val:0x28d3; valaddr_reg:x8; val_offset:4983*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4983*FLEN/8, x10, x3, x5) + +inst_1684: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fd and fs2 == 1 and fe2 == 0x0d and fm2 == 0x167 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0b9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3afd; op2val:0xb567; +op3val:0x34b9; valaddr_reg:x8; val_offset:4986*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4986*FLEN/8, x10, x3, x5) + +inst_1685: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fd and fs2 == 1 and fe2 == 0x0d and fm2 == 0x167 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0b9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3afd; op2val:0xb567; +op3val:0x34b9; valaddr_reg:x8; val_offset:4989*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4989*FLEN/8, x10, x3, x5) + +inst_1686: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fd and fs2 == 1 and fe2 == 0x0d and fm2 == 0x167 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0b9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3afd; op2val:0xb567; +op3val:0x34b9; valaddr_reg:x8; val_offset:4992*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:64 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4992*FLEN/8, x10, x3, x5) + +inst_1687: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fd and fs2 == 1 and fe2 == 0x0d and fm2 == 0x167 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0b9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3afd; op2val:0xb567; +op3val:0x34b9; valaddr_reg:x8; val_offset:4995*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:96 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4995*FLEN/8, x10, x3, x5) +RVTEST_SIGBASE(x3,signature_x3_13) + +inst_1688: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fd and fs2 == 1 and fe2 == 0x0d and fm2 == 0x167 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0b9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3afd; op2val:0xb567; +op3val:0x34b9; valaddr_reg:x8; val_offset:4998*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:128 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4998*FLEN/8, x10, x3, x5) + +inst_1689: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x351 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x294 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x205 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b51; op2val:0xba94; +op3val:0x3a05; valaddr_reg:x8; val_offset:5001*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:0 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 5001*FLEN/8, x10, x3, x5) + +inst_1690: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x351 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x294 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x205 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000 +/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b51; op2val:0xba94; +op3val:0x3a05; valaddr_reg:x8; val_offset:5004*FLEN/8; rmval:dyn; +testreg:x5; fcsr_val:32 */ +TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 5004*FLEN/8, x10, x3, x5) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(14895,32,FLEN) +NAN_BOXED(14895,16,FLEN) +NAN_BOXED(10451,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(43581,16,FLEN) +NAN_BOXED(10451,32,FLEN) +NAN_BOXED(14895,32,FLEN) +NAN_BOXED(43581,16,FLEN) +NAN_BOXED(10451,32,FLEN) +NAN_BOXED(14895,32,FLEN) +NAN_BOXED(43581,16,FLEN) +NAN_BOXED(14895,32,FLEN) +NAN_BOXED(14895,32,FLEN) +NAN_BOXED(14895,16,FLEN) +NAN_BOXED(14895,32,FLEN) +NAN_BOXED(15101,32,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(13497,32,FLEN) +NAN_BOXED(15101,32,FLEN) +NAN_BOXED(46439,16,FLEN) +NAN_BOXED(46439,32,FLEN) +NAN_BOXED(15101,32,FLEN) +NAN_BOXED(46439,16,FLEN) +NAN_BOXED(15101,32,FLEN) +NAN_BOXED(15101,32,FLEN) +NAN_BOXED(15101,16,FLEN) +NAN_BOXED(15101,32,FLEN) +NAN_BOXED(15101,32,FLEN) +NAN_BOXED(15101,16,FLEN) +NAN_BOXED(13497,32,FLEN) +NAN_BOXED(15185,32,FLEN) +NAN_BOXED(47764,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(15185,32,FLEN) +NAN_BOXED(47764,16,FLEN) +NAN_BOXED(47764,32,FLEN) +test_dataset_1: +NAN_BOXED(15185,32,FLEN) +NAN_BOXED(47764,16,FLEN) +NAN_BOXED(14853,32,FLEN) +NAN_BOXED(15185,32,FLEN) +NAN_BOXED(47764,16,FLEN) +NAN_BOXED(14853,32,FLEN) +NAN_BOXED(15185,32,FLEN) +NAN_BOXED(47764,16,FLEN) +NAN_BOXED(14853,32,FLEN) +NAN_BOXED(4899,32,FLEN) +NAN_BOXED(58134,16,FLEN) +NAN_BOXED(14931,32,FLEN) +NAN_BOXED(4899,32,FLEN) +NAN_BOXED(58134,16,FLEN) +NAN_BOXED(14931,32,FLEN) +NAN_BOXED(4899,32,FLEN) +NAN_BOXED(58134,16,FLEN) +NAN_BOXED(14931,32,FLEN) +NAN_BOXED(4899,32,FLEN) +NAN_BOXED(58134,16,FLEN) +NAN_BOXED(14931,32,FLEN) +NAN_BOXED(4899,32,FLEN) +NAN_BOXED(58134,16,FLEN) +NAN_BOXED(14931,32,FLEN) +NAN_BOXED(13754,32,FLEN) +NAN_BOXED(48650,16,FLEN) +NAN_BOXED(14419,32,FLEN) +NAN_BOXED(13754,32,FLEN) +NAN_BOXED(48650,16,FLEN) +NAN_BOXED(14419,32,FLEN) +test_dataset_2: +NAN_BOXED(13754,16,FLEN) +NAN_BOXED(48650,16,FLEN) +NAN_BOXED(14419,16,FLEN) +NAN_BOXED(13754,16,FLEN) +NAN_BOXED(48650,16,FLEN) +NAN_BOXED(14419,16,FLEN) +NAN_BOXED(13754,16,FLEN) +NAN_BOXED(48650,16,FLEN) +NAN_BOXED(14419,16,FLEN) +NAN_BOXED(14431,16,FLEN) +NAN_BOXED(47971,16,FLEN) +NAN_BOXED(14346,16,FLEN) +NAN_BOXED(14431,16,FLEN) +NAN_BOXED(47971,16,FLEN) +NAN_BOXED(14346,16,FLEN) +NAN_BOXED(14431,16,FLEN) +NAN_BOXED(47971,16,FLEN) +NAN_BOXED(14346,16,FLEN) +NAN_BOXED(14431,16,FLEN) +NAN_BOXED(47971,16,FLEN) +NAN_BOXED(14346,16,FLEN) +NAN_BOXED(14431,16,FLEN) +NAN_BOXED(47971,16,FLEN) +NAN_BOXED(14346,16,FLEN) +NAN_BOXED(14966,16,FLEN) +NAN_BOXED(45750,16,FLEN) +NAN_BOXED(12652,16,FLEN) +NAN_BOXED(14966,16,FLEN) +NAN_BOXED(45750,16,FLEN) +NAN_BOXED(12652,16,FLEN) +NAN_BOXED(14966,16,FLEN) +NAN_BOXED(45750,16,FLEN) +NAN_BOXED(12652,16,FLEN) +NAN_BOXED(14966,16,FLEN) +NAN_BOXED(45750,16,FLEN) +NAN_BOXED(12652,16,FLEN) +NAN_BOXED(14966,16,FLEN) +NAN_BOXED(45750,16,FLEN) +NAN_BOXED(12652,16,FLEN) +NAN_BOXED(15176,16,FLEN) +NAN_BOXED(47802,16,FLEN) +NAN_BOXED(14880,16,FLEN) +NAN_BOXED(15176,16,FLEN) +NAN_BOXED(47802,16,FLEN) +NAN_BOXED(14880,16,FLEN) +NAN_BOXED(15176,16,FLEN) +NAN_BOXED(47802,16,FLEN) +NAN_BOXED(14880,16,FLEN) +NAN_BOXED(15176,16,FLEN) +NAN_BOXED(47802,16,FLEN) +NAN_BOXED(14880,16,FLEN) +NAN_BOXED(15176,16,FLEN) +NAN_BOXED(47802,16,FLEN) +NAN_BOXED(14880,16,FLEN) +NAN_BOXED(15319,16,FLEN) +NAN_BOXED(47612,16,FLEN) +NAN_BOXED(14813,16,FLEN) +NAN_BOXED(15319,16,FLEN) +NAN_BOXED(47612,16,FLEN) +NAN_BOXED(14813,16,FLEN) +NAN_BOXED(15319,16,FLEN) +NAN_BOXED(47612,16,FLEN) +NAN_BOXED(14813,16,FLEN) +NAN_BOXED(15319,16,FLEN) +NAN_BOXED(47612,16,FLEN) +NAN_BOXED(14813,16,FLEN) +NAN_BOXED(15319,16,FLEN) +NAN_BOXED(47612,16,FLEN) +NAN_BOXED(14813,16,FLEN) +NAN_BOXED(14525,16,FLEN) +NAN_BOXED(45386,16,FLEN) +NAN_BOXED(11844,16,FLEN) +NAN_BOXED(14525,16,FLEN) +NAN_BOXED(45386,16,FLEN) +NAN_BOXED(11844,16,FLEN) +NAN_BOXED(14525,16,FLEN) +NAN_BOXED(45386,16,FLEN) +NAN_BOXED(11844,16,FLEN) +NAN_BOXED(14525,16,FLEN) +NAN_BOXED(45386,16,FLEN) +NAN_BOXED(11844,16,FLEN) +NAN_BOXED(14525,16,FLEN) +NAN_BOXED(45386,16,FLEN) +NAN_BOXED(11844,16,FLEN) +NAN_BOXED(14583,16,FLEN) +NAN_BOXED(48565,16,FLEN) +NAN_BOXED(15127,16,FLEN) +NAN_BOXED(14583,16,FLEN) +NAN_BOXED(48565,16,FLEN) +NAN_BOXED(15127,16,FLEN) +NAN_BOXED(14583,16,FLEN) +NAN_BOXED(48565,16,FLEN) +NAN_BOXED(15127,16,FLEN) +NAN_BOXED(14583,16,FLEN) +NAN_BOXED(48565,16,FLEN) +NAN_BOXED(15127,16,FLEN) +NAN_BOXED(14583,16,FLEN) +NAN_BOXED(48565,16,FLEN) +NAN_BOXED(15127,16,FLEN) +NAN_BOXED(14830,16,FLEN) +NAN_BOXED(41420,16,FLEN) +NAN_BOXED(8268,16,FLEN) +NAN_BOXED(14830,16,FLEN) +NAN_BOXED(41420,16,FLEN) +NAN_BOXED(8268,16,FLEN) +NAN_BOXED(14830,16,FLEN) +NAN_BOXED(41420,16,FLEN) +NAN_BOXED(8268,16,FLEN) +NAN_BOXED(14830,16,FLEN) +NAN_BOXED(41420,16,FLEN) +NAN_BOXED(8268,16,FLEN) +NAN_BOXED(14830,16,FLEN) +NAN_BOXED(41420,16,FLEN) +NAN_BOXED(8268,16,FLEN) +NAN_BOXED(15230,16,FLEN) +NAN_BOXED(46716,16,FLEN) +NAN_BOXED(13843,16,FLEN) +NAN_BOXED(15230,16,FLEN) +NAN_BOXED(46716,16,FLEN) +NAN_BOXED(13843,16,FLEN) +NAN_BOXED(15230,16,FLEN) +NAN_BOXED(46716,16,FLEN) +NAN_BOXED(13843,16,FLEN) +NAN_BOXED(15230,16,FLEN) +NAN_BOXED(46716,16,FLEN) +NAN_BOXED(13843,16,FLEN) +NAN_BOXED(15230,16,FLEN) +NAN_BOXED(46716,16,FLEN) +NAN_BOXED(13843,16,FLEN) +NAN_BOXED(14587,16,FLEN) +NAN_BOXED(47195,16,FLEN) +NAN_BOXED(13677,16,FLEN) +NAN_BOXED(14587,16,FLEN) +NAN_BOXED(47195,16,FLEN) +NAN_BOXED(13677,16,FLEN) +NAN_BOXED(14587,16,FLEN) +NAN_BOXED(47195,16,FLEN) +NAN_BOXED(13677,16,FLEN) +NAN_BOXED(14587,16,FLEN) +NAN_BOXED(47195,16,FLEN) +NAN_BOXED(13677,16,FLEN) +NAN_BOXED(14587,16,FLEN) +NAN_BOXED(47195,16,FLEN) +NAN_BOXED(13677,16,FLEN) +NAN_BOXED(14666,16,FLEN) +NAN_BOXED(46967,16,FLEN) +NAN_BOXED(13552,16,FLEN) +NAN_BOXED(14666,16,FLEN) +NAN_BOXED(46967,16,FLEN) +NAN_BOXED(13552,16,FLEN) +NAN_BOXED(14666,16,FLEN) +NAN_BOXED(46967,16,FLEN) +NAN_BOXED(13552,16,FLEN) +NAN_BOXED(14666,16,FLEN) +NAN_BOXED(46967,16,FLEN) +NAN_BOXED(13552,16,FLEN) +NAN_BOXED(14666,16,FLEN) +NAN_BOXED(46967,16,FLEN) +NAN_BOXED(13552,16,FLEN) +NAN_BOXED(14340,16,FLEN) +NAN_BOXED(47507,16,FLEN) +NAN_BOXED(13722,16,FLEN) +NAN_BOXED(14340,16,FLEN) +NAN_BOXED(47507,16,FLEN) +NAN_BOXED(13722,16,FLEN) +NAN_BOXED(14340,16,FLEN) +NAN_BOXED(47507,16,FLEN) +NAN_BOXED(13722,16,FLEN) +NAN_BOXED(14340,16,FLEN) +NAN_BOXED(47507,16,FLEN) +NAN_BOXED(13722,16,FLEN) +NAN_BOXED(14340,16,FLEN) +NAN_BOXED(47507,16,FLEN) +NAN_BOXED(13722,16,FLEN) +NAN_BOXED(11855,16,FLEN) +NAN_BOXED(50238,16,FLEN) +NAN_BOXED(14002,16,FLEN) +NAN_BOXED(11855,16,FLEN) +NAN_BOXED(50238,16,FLEN) +NAN_BOXED(14002,16,FLEN) +NAN_BOXED(11855,16,FLEN) +NAN_BOXED(50238,16,FLEN) +NAN_BOXED(14002,16,FLEN) +NAN_BOXED(11855,16,FLEN) +NAN_BOXED(50238,16,FLEN) +NAN_BOXED(14002,16,FLEN) +NAN_BOXED(11855,16,FLEN) +NAN_BOXED(50238,16,FLEN) +NAN_BOXED(14002,16,FLEN) +NAN_BOXED(15068,16,FLEN) +NAN_BOXED(48220,16,FLEN) +NAN_BOXED(15228,16,FLEN) +NAN_BOXED(15068,16,FLEN) +NAN_BOXED(48220,16,FLEN) +NAN_BOXED(15228,16,FLEN) +NAN_BOXED(15068,16,FLEN) +NAN_BOXED(48220,16,FLEN) +NAN_BOXED(15228,16,FLEN) +NAN_BOXED(15068,16,FLEN) +NAN_BOXED(48220,16,FLEN) +NAN_BOXED(15228,16,FLEN) +NAN_BOXED(15068,16,FLEN) +NAN_BOXED(48220,16,FLEN) +NAN_BOXED(15228,16,FLEN) +NAN_BOXED(10983,16,FLEN) +NAN_BOXED(51389,16,FLEN) +NAN_BOXED(14359,16,FLEN) +NAN_BOXED(10983,16,FLEN) +NAN_BOXED(51389,16,FLEN) +NAN_BOXED(14359,16,FLEN) +NAN_BOXED(10983,16,FLEN) +NAN_BOXED(51389,16,FLEN) +NAN_BOXED(14359,16,FLEN) +NAN_BOXED(10983,16,FLEN) +NAN_BOXED(51389,16,FLEN) +NAN_BOXED(14359,16,FLEN) +NAN_BOXED(10983,16,FLEN) +NAN_BOXED(51389,16,FLEN) +NAN_BOXED(14359,16,FLEN) +NAN_BOXED(14962,16,FLEN) +NAN_BOXED(44104,16,FLEN) +NAN_BOXED(10984,16,FLEN) +NAN_BOXED(14962,16,FLEN) +NAN_BOXED(44104,16,FLEN) +NAN_BOXED(10984,16,FLEN) +NAN_BOXED(14962,16,FLEN) +NAN_BOXED(44104,16,FLEN) +NAN_BOXED(10984,16,FLEN) +NAN_BOXED(14962,16,FLEN) +NAN_BOXED(44104,16,FLEN) +NAN_BOXED(10984,16,FLEN) +NAN_BOXED(14962,16,FLEN) +NAN_BOXED(44104,16,FLEN) +NAN_BOXED(10984,16,FLEN) +NAN_BOXED(14012,16,FLEN) +NAN_BOXED(47398,16,FLEN) +NAN_BOXED(13398,16,FLEN) +NAN_BOXED(14012,16,FLEN) +NAN_BOXED(47398,16,FLEN) +NAN_BOXED(13398,16,FLEN) +NAN_BOXED(14012,16,FLEN) +NAN_BOXED(47398,16,FLEN) +NAN_BOXED(13398,16,FLEN) +NAN_BOXED(14012,16,FLEN) +NAN_BOXED(47398,16,FLEN) +NAN_BOXED(13398,16,FLEN) +NAN_BOXED(14012,16,FLEN) +NAN_BOXED(47398,16,FLEN) +NAN_BOXED(13398,16,FLEN) +NAN_BOXED(12190,16,FLEN) +NAN_BOXED(50688,16,FLEN) +NAN_BOXED(14774,16,FLEN) +NAN_BOXED(12190,16,FLEN) +NAN_BOXED(50688,16,FLEN) +NAN_BOXED(14774,16,FLEN) +NAN_BOXED(12190,16,FLEN) +NAN_BOXED(50688,16,FLEN) +NAN_BOXED(14774,16,FLEN) +NAN_BOXED(12190,16,FLEN) +NAN_BOXED(50688,16,FLEN) +NAN_BOXED(14774,16,FLEN) +NAN_BOXED(12190,16,FLEN) +NAN_BOXED(50688,16,FLEN) +NAN_BOXED(14774,16,FLEN) +NAN_BOXED(14629,16,FLEN) +NAN_BOXED(45584,16,FLEN) +NAN_BOXED(12237,16,FLEN) +NAN_BOXED(14629,16,FLEN) +NAN_BOXED(45584,16,FLEN) +NAN_BOXED(12237,16,FLEN) +NAN_BOXED(14629,16,FLEN) +NAN_BOXED(45584,16,FLEN) +NAN_BOXED(12237,16,FLEN) +NAN_BOXED(14629,16,FLEN) +NAN_BOXED(45584,16,FLEN) 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+NAN_BOXED(14350,16,FLEN) +NAN_BOXED(12064,16,FLEN) +NAN_BOXED(50389,16,FLEN) +NAN_BOXED(14350,16,FLEN) +NAN_BOXED(12064,16,FLEN) +NAN_BOXED(50389,16,FLEN) +NAN_BOXED(14350,16,FLEN) +NAN_BOXED(12064,16,FLEN) +NAN_BOXED(50389,16,FLEN) +NAN_BOXED(14350,16,FLEN) +NAN_BOXED(14802,16,FLEN) +NAN_BOXED(47270,16,FLEN) +NAN_BOXED(13893,16,FLEN) +NAN_BOXED(14802,16,FLEN) +NAN_BOXED(47270,16,FLEN) +NAN_BOXED(13893,16,FLEN) +NAN_BOXED(14802,16,FLEN) +NAN_BOXED(47270,16,FLEN) +NAN_BOXED(13893,16,FLEN) +NAN_BOXED(14802,16,FLEN) +NAN_BOXED(47270,16,FLEN) +NAN_BOXED(13893,16,FLEN) +NAN_BOXED(14802,16,FLEN) +NAN_BOXED(47270,16,FLEN) +NAN_BOXED(13893,16,FLEN) +NAN_BOXED(14895,16,FLEN) +NAN_BOXED(43581,16,FLEN) +NAN_BOXED(10451,16,FLEN) +NAN_BOXED(14895,16,FLEN) +NAN_BOXED(43581,16,FLEN) +NAN_BOXED(10451,16,FLEN) +NAN_BOXED(14895,16,FLEN) +NAN_BOXED(43581,16,FLEN) +NAN_BOXED(10451,16,FLEN) +NAN_BOXED(14895,16,FLEN) +NAN_BOXED(43581,16,FLEN) +NAN_BOXED(10451,16,FLEN) +NAN_BOXED(15101,16,FLEN) +NAN_BOXED(46439,16,FLEN) +NAN_BOXED(13497,16,FLEN) +NAN_BOXED(15101,16,FLEN) +NAN_BOXED(46439,16,FLEN) +NAN_BOXED(13497,16,FLEN) +NAN_BOXED(15101,16,FLEN) +NAN_BOXED(46439,16,FLEN) +NAN_BOXED(13497,16,FLEN) +NAN_BOXED(15101,16,FLEN) +NAN_BOXED(46439,16,FLEN) +NAN_BOXED(13497,16,FLEN) +NAN_BOXED(15101,16,FLEN) +NAN_BOXED(46439,16,FLEN) +NAN_BOXED(13497,16,FLEN) +NAN_BOXED(15185,16,FLEN) +NAN_BOXED(47764,16,FLEN) +NAN_BOXED(14853,16,FLEN) +NAN_BOXED(15185,16,FLEN) +NAN_BOXED(47764,16,FLEN) +NAN_BOXED(14853,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x4_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x4_1: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_0: + .fill 20*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x3_0: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x3_1: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x3_2: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x3_3: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x3_4: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x3_5: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x3_6: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x3_7: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x3_8: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x3_9: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x3_10: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x3_11: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x3_12: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x3_13: + .fill 6*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fsgnj_b1-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fsgnj_b1-01.S new file mode 100644 index 000000000..f97c18f15 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fsgnj_b1-01.S @@ -0,0 +1,5924 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 05:25:59 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fsgnj.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fsgnj.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fsgnj_b1 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fsgnj_b1) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rs2 != rd, rs1==x19, rs2==x19, rd==x29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x19; op2:x19; dest:x29; op1val:0x0; op2val:0x0; + valaddr_reg:x3; val_offset:0*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x29, x19, x19, 0, 0, x3, 0*FLEN/8, x9, x1, x2) + +inst_1: +// rs1 == rs2 == rd, rs1==x22, rs2==x22, rd==x22,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x22; op2:x22; dest:x22; op1val:0x0; op2val:0x0; + valaddr_reg:x3; val_offset:2*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x22, x22, x22, 0, 0, x3, 2*FLEN/8, x9, x1, x2) + +inst_2: +// rs2 == rd != rs1, rs1==x16, rs2==x0, rd==x0,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x16; op2:x0; dest:x0; op1val:0x0; op2val:0x0; + valaddr_reg:x3; val_offset:4*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x0, x16, x0, 0, 0, x3, 4*FLEN/8, x9, x1, x2) + +inst_3: +// rs1 == rd != rs2, rs1==x6, rs2==x4, rd==x6,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x6; op2:x4; dest:x6; op1val:0x0; op2val:0x8001; + valaddr_reg:x3; val_offset:6*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x6, x6, x4, 0, 0, x3, 6*FLEN/8, x9, x1, x2) + +inst_4: +// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==x17, rs2==x15, rd==x30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x17; op2:x15; dest:x30; op1val:0x0; op2val:0x2; + valaddr_reg:x3; val_offset:8*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x30, x17, x15, 0, 0, x3, 8*FLEN/8, x9, x1, x2) + +inst_5: +// rs1==x31, rs2==x20, rd==x19,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x31; op2:x20; dest:x19; op1val:0x0; op2val:0x83fe; + valaddr_reg:x3; val_offset:10*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x19, x31, x20, 0, 0, x3, 10*FLEN/8, x9, x1, x2) + +inst_6: +// rs1==x18, rs2==x28, rd==x13,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x18; op2:x28; dest:x13; op1val:0x0; op2val:0x3ff; + valaddr_reg:x3; val_offset:12*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x13, x18, x28, 0, 0, x3, 12*FLEN/8, x9, x1, x2) + +inst_7: +// rs1==x0, rs2==x25, rd==x21,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x0; op2:x25; dest:x21; op1val:0x0; op2val:0x83ff; + valaddr_reg:x3; val_offset:14*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x21, x0, x25, 0, 0, x3, 14*FLEN/8, x9, x1, x2) + +inst_8: +// rs1==x7, rs2==x30, rd==x23,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x7; op2:x30; dest:x23; op1val:0x0; op2val:0x400; + valaddr_reg:x3; val_offset:16*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x23, x7, x30, 0, 0, x3, 16*FLEN/8, x9, x1, x2) + +inst_9: +// rs1==x12, rs2==x13, rd==x8,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x12; op2:x13; dest:x8; op1val:0x0; op2val:0x8400; + valaddr_reg:x3; val_offset:18*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x8, x12, x13, 0, 0, x3, 18*FLEN/8, x9, x1, x2) + +inst_10: +// rs1==x26, rs2==x17, rd==x12,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x26; op2:x17; dest:x12; op1val:0x0; op2val:0x401; + valaddr_reg:x3; val_offset:20*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x12, x26, x17, 0, 0, x3, 20*FLEN/8, x9, x1, x2) + +inst_11: +// rs1==x14, rs2==x5, rd==x17,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x14; op2:x5; dest:x17; op1val:0x0; op2val:0x8455; + valaddr_reg:x3; val_offset:22*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x17, x14, x5, 0, 0, x3, 22*FLEN/8, x9, x1, x2) +RVTEST_VALBASEUPD(x12,test_dataset_1) + +inst_12: +// rs1==x10, rs2==x3, rd==x31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x10; op2:x3; dest:x31; op1val:0x0; op2val:0x7bff; + valaddr_reg:x12; val_offset:0*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x10, x3, 0, 0, x12, 0*FLEN/8, x16, x1, x2) + +inst_13: +// rs1==x20, rs2==x18, rd==x27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x20; op2:x18; dest:x27; op1val:0x0; op2val:0xfbff; + valaddr_reg:x12; val_offset:2*FLEN/8; fcsr: 0; + correctval:??; testreg:x19 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x27, x20, x18, 0, 0, x12, 2*FLEN/8, x16, x1, x19) +RVTEST_SIGBASE(x17,signature_x17_0) + +inst_14: +// rs1==x25, rs2==x1, rd==x14,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x25; op2:x1; dest:x14; op1val:0x0; op2val:0x7c00; + valaddr_reg:x12; val_offset:4*FLEN/8; fcsr: 0; + correctval:??; testreg:x19 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x14, x25, x1, 0, 0, x12, 4*FLEN/8, x16, x17, x19) + +inst_15: +// rs1==x27, rs2==x23, rd==x9,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x27; op2:x23; dest:x9; op1val:0x0; op2val:0xfc00; + valaddr_reg:x12; val_offset:6*FLEN/8; fcsr: 0; + correctval:??; testreg:x19 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x9, x27, x23, 0, 0, x12, 6*FLEN/8, x16, x17, x19) + +inst_16: +// rs1==x21, rs2==x26, rd==x24,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x21; op2:x26; dest:x24; op1val:0x0; op2val:0x7e00; + valaddr_reg:x12; val_offset:8*FLEN/8; fcsr: 0; + correctval:??; testreg:x19 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x24, x21, x26, 0, 0, x12, 8*FLEN/8, x16, x17, x19) + +inst_17: +// rs1==x9, rs2==x6, rd==x18,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x9; op2:x6; dest:x18; op1val:0x0; op2val:0xfe00; + valaddr_reg:x12; val_offset:10*FLEN/8; fcsr: 0; + correctval:??; testreg:x19 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x18, x9, x6, 0, 0, x12, 10*FLEN/8, x16, x17, x19) + +inst_18: +// rs1==x2, rs2==x7, rd==x25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x2; op2:x7; dest:x25; op1val:0x0; op2val:0x7e01; + valaddr_reg:x12; val_offset:12*FLEN/8; fcsr: 0; + correctval:??; testreg:x19 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x25, x2, x7, 0, 0, x12, 12*FLEN/8, x16, x17, x19) + +inst_19: +// rs1==x3, rs2==x14, rd==x5,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x3; op2:x14; dest:x5; op1val:0x0; op2val:0xfe55; + valaddr_reg:x12; val_offset:14*FLEN/8; fcsr: 0; + correctval:??; testreg:x19 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x5, x3, x14, 0, 0, x12, 14*FLEN/8, x16, x17, x19) + +inst_20: +// rs1==x4, rs2==x24, rd==x2,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x4; op2:x24; dest:x2; op1val:0x0; op2val:0x7c01; + valaddr_reg:x12; val_offset:16*FLEN/8; fcsr: 0; + correctval:??; testreg:x19 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x2, x4, x24, 0, 0, x12, 16*FLEN/8, x16, x17, x19) + +inst_21: +// rs1==x23, rs2==x27, rd==x11,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x23; op2:x27; dest:x11; op1val:0x0; op2val:0xfd55; + valaddr_reg:x12; val_offset:18*FLEN/8; fcsr: 0; + correctval:??; testreg:x19 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x11, x23, x27, 0, 0, x12, 18*FLEN/8, x16, x17, x19) + +inst_22: +// rs1==x15, rs2==x9, rd==x4,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x15; op2:x9; dest:x4; op1val:0x0; op2val:0x3c00; + valaddr_reg:x12; val_offset:20*FLEN/8; fcsr: 0; + correctval:??; testreg:x19 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x4, x15, x9, 0, 0, x12, 20*FLEN/8, x16, x17, x19) + +inst_23: +// rs1==x5, rs2==x8, rd==x10,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x5; op2:x8; dest:x10; op1val:0x0; op2val:0xbc00; + valaddr_reg:x12; val_offset:22*FLEN/8; fcsr: 0; + correctval:??; testreg:x19 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x10, x5, x8, 0, 0, x12, 22*FLEN/8, x16, x17, x19) + +inst_24: +// rs1==x13, rs2==x10, rd==x20,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x13; op2:x10; dest:x20; op1val:0x8000; op2val:0x0; + valaddr_reg:x12; val_offset:24*FLEN/8; fcsr: 0; + correctval:??; testreg:x19 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x20, x13, x10, 0, 0, x12, 24*FLEN/8, x16, x17, x19) +RVTEST_VALBASEUPD(x4,test_dataset_2) + +inst_25: +// rs1==x11, rs2==x2, rd==x15,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x11; op2:x2; dest:x15; op1val:0x8000; op2val:0x8000; + valaddr_reg:x4; val_offset:0*FLEN/8; fcsr: 0; + correctval:??; testreg:x19 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x15, x11, x2, 0, 0, x4, 0*FLEN/8, x6, x17, x19) + +inst_26: +// rs1==x29, rs2==x16, rd==x3,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x29; op2:x16; dest:x3; op1val:0x8000; op2val:0x1; + valaddr_reg:x4; val_offset:2*FLEN/8; fcsr: 0; + correctval:??; testreg:x19 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x3, x29, x16, 0, 0, x4, 2*FLEN/8, x6, x17, x19) + +inst_27: +// rs1==x8, rs2==x21, rd==x26,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x8; op2:x21; dest:x26; op1val:0x8000; op2val:0x8001; + valaddr_reg:x4; val_offset:4*FLEN/8; fcsr: 0; + correctval:??; testreg:x19 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x26, x8, x21, 0, 0, x4, 4*FLEN/8, x6, x17, x19) + +inst_28: +// rs1==x1, rs2==x12, rd==x16,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x1; op2:x12; dest:x16; op1val:0x8000; op2val:0x2; + valaddr_reg:x4; val_offset:6*FLEN/8; fcsr: 0; + correctval:??; testreg:x19 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x16, x1, x12, 0, 0, x4, 6*FLEN/8, x6, x17, x19) + +inst_29: +// rs1==x30, rs2==x11, rd==x1,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x11; dest:x1; op1val:0x8000; op2val:0x83fe; + valaddr_reg:x4; val_offset:8*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x1, x30, x11, 0, 0, x4, 8*FLEN/8, x6, x17, x2) +RVTEST_SIGBASE(x1,signature_x1_2) + +inst_30: +// rs1==x24, rs2==x31, rd==x7,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x24; op2:x31; dest:x7; op1val:0x8000; op2val:0x3ff; + valaddr_reg:x4; val_offset:10*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x7, x24, x31, 0, 0, x4, 10*FLEN/8, x6, x1, x2) + +inst_31: +// rs1==x28,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x28; op2:x5; dest:x31; op1val:0x8000; op2val:0x83ff; + valaddr_reg:x4; val_offset:12*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x28, x5, 0, 0, x4, 12*FLEN/8, x6, x1, x2) + +inst_32: +// rs2==x29,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x15; op2:x29; dest:x20; op1val:0x8000; op2val:0x400; + valaddr_reg:x4; val_offset:14*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x20, x15, x29, 0, 0, x4, 14*FLEN/8, x6, x1, x2) + +inst_33: +// rd==x28,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x9; op2:x12; dest:x28; op1val:0x8000; op2val:0x8400; + valaddr_reg:x4; val_offset:16*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x28, x9, x12, 0, 0, x4, 16*FLEN/8, x6, x1, x2) + +inst_34: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x401; + valaddr_reg:x4; val_offset:18*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 18*FLEN/8, x6, x1, x2) + +inst_35: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8455; + valaddr_reg:x4; val_offset:20*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 20*FLEN/8, x6, x1, x2) + +inst_36: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x7bff; + valaddr_reg:x4; val_offset:22*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 22*FLEN/8, x6, x1, x2) + +inst_37: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xfbff; + valaddr_reg:x4; val_offset:24*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 24*FLEN/8, x6, x1, x2) + +inst_38: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x7c00; + valaddr_reg:x4; val_offset:26*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 26*FLEN/8, x6, x1, x2) + +inst_39: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xfc00; + valaddr_reg:x4; val_offset:28*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 28*FLEN/8, x6, x1, x2) + +inst_40: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x7e00; + valaddr_reg:x4; val_offset:30*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 30*FLEN/8, x6, x1, x2) + +inst_41: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xfe00; + valaddr_reg:x4; val_offset:32*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 32*FLEN/8, x6, x1, x2) + +inst_42: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x7e01; + valaddr_reg:x4; val_offset:34*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 34*FLEN/8, x6, x1, x2) + +inst_43: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xfe55; + valaddr_reg:x4; val_offset:36*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 36*FLEN/8, x6, x1, x2) + +inst_44: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x7c01; + valaddr_reg:x4; val_offset:38*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 38*FLEN/8, x6, x1, x2) + +inst_45: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xfd55; + valaddr_reg:x4; val_offset:40*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 40*FLEN/8, x6, x1, x2) + +inst_46: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x3c00; + valaddr_reg:x4; val_offset:42*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 42*FLEN/8, x6, x1, x2) + +inst_47: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xbc00; + valaddr_reg:x4; val_offset:44*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 44*FLEN/8, x6, x1, x2) + +inst_48: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x0; + valaddr_reg:x4; val_offset:46*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 46*FLEN/8, x6, x1, x2) + +inst_49: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x8000; + valaddr_reg:x4; val_offset:48*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 48*FLEN/8, x6, x1, x2) + +inst_50: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x1; + valaddr_reg:x4; val_offset:50*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 50*FLEN/8, x6, x1, x2) + +inst_51: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x8001; + valaddr_reg:x4; val_offset:52*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 52*FLEN/8, x6, x1, x2) + +inst_52: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x2; + valaddr_reg:x4; val_offset:54*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 54*FLEN/8, x6, x1, x2) + +inst_53: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x83fe; + valaddr_reg:x4; val_offset:56*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 56*FLEN/8, x6, x1, x2) + +inst_54: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x3ff; + valaddr_reg:x4; val_offset:58*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 58*FLEN/8, x6, x1, x2) + +inst_55: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x83ff; + valaddr_reg:x4; val_offset:60*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 60*FLEN/8, x6, x1, x2) + +inst_56: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x400; + valaddr_reg:x4; val_offset:62*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 62*FLEN/8, x6, x1, x2) + +inst_57: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x8400; + valaddr_reg:x4; val_offset:64*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 64*FLEN/8, x6, x1, x2) + +inst_58: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x401; + valaddr_reg:x4; val_offset:66*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 66*FLEN/8, x6, x1, x2) + +inst_59: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x8455; + valaddr_reg:x4; val_offset:68*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 68*FLEN/8, x6, x1, x2) + +inst_60: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7bff; + valaddr_reg:x4; val_offset:70*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 70*FLEN/8, x6, x1, x2) + +inst_61: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xfbff; + valaddr_reg:x4; val_offset:72*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 72*FLEN/8, x6, x1, x2) + +inst_62: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7c00; + valaddr_reg:x4; val_offset:74*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 74*FLEN/8, x6, x1, x2) + +inst_63: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xfc00; + valaddr_reg:x4; val_offset:76*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 76*FLEN/8, x6, x1, x2) + +inst_64: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7e00; + valaddr_reg:x4; val_offset:78*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 78*FLEN/8, x6, x1, x2) + +inst_65: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xfe00; + valaddr_reg:x4; val_offset:80*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 80*FLEN/8, x6, x1, x2) + +inst_66: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7e01; + valaddr_reg:x4; val_offset:82*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 82*FLEN/8, x6, x1, x2) + +inst_67: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xfe55; + valaddr_reg:x4; val_offset:84*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 84*FLEN/8, x6, x1, x2) + +inst_68: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7c01; + valaddr_reg:x4; val_offset:86*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 86*FLEN/8, x6, x1, x2) + +inst_69: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xfd55; + valaddr_reg:x4; val_offset:88*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 88*FLEN/8, x6, x1, x2) + +inst_70: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x3c00; + valaddr_reg:x4; val_offset:90*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 90*FLEN/8, x6, x1, x2) + +inst_71: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xbc00; + valaddr_reg:x4; val_offset:92*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 92*FLEN/8, x6, x1, x2) + +inst_72: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x0; + valaddr_reg:x4; val_offset:94*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 94*FLEN/8, x6, x1, x2) + +inst_73: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8000; + valaddr_reg:x4; val_offset:96*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 96*FLEN/8, x6, x1, x2) + +inst_74: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x1; + valaddr_reg:x4; val_offset:98*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 98*FLEN/8, x6, x1, x2) + +inst_75: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8001; + valaddr_reg:x4; val_offset:100*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 100*FLEN/8, x6, x1, x2) + +inst_76: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x2; + valaddr_reg:x4; val_offset:102*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 102*FLEN/8, x6, x1, x2) + +inst_77: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x83fe; + valaddr_reg:x4; val_offset:104*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 104*FLEN/8, x6, x1, x2) + +inst_78: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x3ff; + valaddr_reg:x4; val_offset:106*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 106*FLEN/8, x6, x1, x2) + +inst_79: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x83ff; + valaddr_reg:x4; val_offset:108*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 108*FLEN/8, x6, x1, x2) + +inst_80: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x400; + valaddr_reg:x4; val_offset:110*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 110*FLEN/8, x6, x1, x2) + +inst_81: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8400; + valaddr_reg:x4; val_offset:112*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 112*FLEN/8, x6, x1, x2) + +inst_82: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x401; + valaddr_reg:x4; val_offset:114*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 114*FLEN/8, x6, x1, x2) + +inst_83: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8455; + valaddr_reg:x4; val_offset:116*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 116*FLEN/8, x6, x1, x2) + +inst_84: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x7bff; + valaddr_reg:x4; val_offset:118*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 118*FLEN/8, x6, x1, x2) + +inst_85: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xfbff; + valaddr_reg:x4; val_offset:120*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 120*FLEN/8, x6, x1, x2) + +inst_86: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x7c00; + valaddr_reg:x4; val_offset:122*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 122*FLEN/8, x6, x1, x2) + +inst_87: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xfc00; + valaddr_reg:x4; val_offset:124*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 124*FLEN/8, x6, x1, x2) + +inst_88: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x7e00; + valaddr_reg:x4; val_offset:126*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 126*FLEN/8, x6, x1, x2) + +inst_89: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xfe00; + valaddr_reg:x4; val_offset:128*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 128*FLEN/8, x6, x1, x2) + +inst_90: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x7e01; + valaddr_reg:x4; val_offset:130*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 130*FLEN/8, x6, x1, x2) + +inst_91: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xfe55; + valaddr_reg:x4; val_offset:132*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 132*FLEN/8, x6, x1, x2) + +inst_92: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x7c01; + valaddr_reg:x4; val_offset:134*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 134*FLEN/8, x6, x1, x2) + +inst_93: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xfd55; + valaddr_reg:x4; val_offset:136*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 136*FLEN/8, x6, x1, x2) + +inst_94: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x3c00; + valaddr_reg:x4; val_offset:138*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 138*FLEN/8, x6, x1, x2) + +inst_95: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xbc00; + valaddr_reg:x4; val_offset:140*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 140*FLEN/8, x6, x1, x2) + +inst_96: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x0; + valaddr_reg:x4; val_offset:142*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 142*FLEN/8, x6, x1, x2) + +inst_97: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x8000; + valaddr_reg:x4; val_offset:144*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 144*FLEN/8, x6, x1, x2) + +inst_98: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x1; + valaddr_reg:x4; val_offset:146*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 146*FLEN/8, x6, x1, x2) + +inst_99: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x8001; + valaddr_reg:x4; val_offset:148*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 148*FLEN/8, x6, x1, x2) + +inst_100: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x2; + valaddr_reg:x4; val_offset:150*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 150*FLEN/8, x6, x1, x2) + +inst_101: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x83fe; + valaddr_reg:x4; val_offset:152*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 152*FLEN/8, x6, x1, x2) + +inst_102: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x3ff; + valaddr_reg:x4; val_offset:154*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 154*FLEN/8, x6, x1, x2) + +inst_103: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x83ff; + valaddr_reg:x4; val_offset:156*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 156*FLEN/8, x6, x1, x2) + +inst_104: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x400; + valaddr_reg:x4; val_offset:158*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 158*FLEN/8, x6, x1, x2) + +inst_105: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x8400; + valaddr_reg:x4; val_offset:160*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 160*FLEN/8, x6, x1, x2) + +inst_106: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x401; + valaddr_reg:x4; val_offset:162*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 162*FLEN/8, x6, x1, x2) + +inst_107: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x8455; + valaddr_reg:x4; val_offset:164*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 164*FLEN/8, x6, x1, x2) + +inst_108: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x7bff; + valaddr_reg:x4; val_offset:166*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 166*FLEN/8, x6, x1, x2) + +inst_109: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xfbff; + valaddr_reg:x4; val_offset:168*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 168*FLEN/8, x6, x1, x2) + +inst_110: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x7c00; + valaddr_reg:x4; val_offset:170*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 170*FLEN/8, x6, x1, x2) + +inst_111: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xfc00; + valaddr_reg:x4; val_offset:172*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 172*FLEN/8, x6, x1, x2) + +inst_112: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x7e00; + valaddr_reg:x4; val_offset:174*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 174*FLEN/8, x6, x1, x2) + +inst_113: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xfe00; + valaddr_reg:x4; val_offset:176*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 176*FLEN/8, x6, x1, x2) + +inst_114: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x7e01; + valaddr_reg:x4; val_offset:178*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 178*FLEN/8, x6, x1, x2) + +inst_115: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xfe55; + valaddr_reg:x4; val_offset:180*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 180*FLEN/8, x6, x1, x2) + +inst_116: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x7c01; + valaddr_reg:x4; val_offset:182*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 182*FLEN/8, x6, x1, x2) + +inst_117: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xfd55; + valaddr_reg:x4; val_offset:184*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 184*FLEN/8, x6, x1, x2) + +inst_118: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x3c00; + valaddr_reg:x4; val_offset:186*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 186*FLEN/8, x6, x1, x2) + +inst_119: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xbc00; + valaddr_reg:x4; val_offset:188*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 188*FLEN/8, x6, x1, x2) + +inst_120: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x0; + valaddr_reg:x4; val_offset:190*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 190*FLEN/8, x6, x1, x2) + +inst_121: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x8000; + valaddr_reg:x4; val_offset:192*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 192*FLEN/8, x6, x1, x2) + +inst_122: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x1; + valaddr_reg:x4; val_offset:194*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 194*FLEN/8, x6, x1, x2) + +inst_123: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x8001; + valaddr_reg:x4; val_offset:196*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 196*FLEN/8, x6, x1, x2) + +inst_124: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x2; + valaddr_reg:x4; val_offset:198*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 198*FLEN/8, x6, x1, x2) + +inst_125: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x83fe; + valaddr_reg:x4; val_offset:200*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 200*FLEN/8, x6, x1, x2) + +inst_126: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x3ff; + valaddr_reg:x4; val_offset:202*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 202*FLEN/8, x6, x1, x2) + +inst_127: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x83ff; + valaddr_reg:x4; val_offset:204*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 204*FLEN/8, x6, x1, x2) + +inst_128: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x400; + valaddr_reg:x4; val_offset:206*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 206*FLEN/8, x6, x1, x2) + +inst_129: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x8400; + valaddr_reg:x4; val_offset:208*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 208*FLEN/8, x6, x1, x2) + +inst_130: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x401; + valaddr_reg:x4; val_offset:210*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 210*FLEN/8, x6, x1, x2) + +inst_131: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x8455; + valaddr_reg:x4; val_offset:212*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 212*FLEN/8, x6, x1, x2) + +inst_132: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x7bff; + valaddr_reg:x4; val_offset:214*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 214*FLEN/8, x6, x1, x2) + +inst_133: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xfbff; + valaddr_reg:x4; val_offset:216*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 216*FLEN/8, x6, x1, x2) + +inst_134: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x7c00; + valaddr_reg:x4; val_offset:218*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 218*FLEN/8, x6, x1, x2) + +inst_135: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xfc00; + valaddr_reg:x4; val_offset:220*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 220*FLEN/8, x6, x1, x2) + +inst_136: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x7e00; + valaddr_reg:x4; val_offset:222*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 222*FLEN/8, x6, x1, x2) + +inst_137: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xfe00; + valaddr_reg:x4; val_offset:224*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 224*FLEN/8, x6, x1, x2) + +inst_138: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x7e01; + valaddr_reg:x4; val_offset:226*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 226*FLEN/8, x6, x1, x2) + +inst_139: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xfe55; + valaddr_reg:x4; val_offset:228*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 228*FLEN/8, x6, x1, x2) + +inst_140: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x7c01; + valaddr_reg:x4; val_offset:230*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 230*FLEN/8, x6, x1, x2) + +inst_141: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xfd55; + valaddr_reg:x4; val_offset:232*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 232*FLEN/8, x6, x1, x2) + +inst_142: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x3c00; + valaddr_reg:x4; val_offset:234*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 234*FLEN/8, x6, x1, x2) + +inst_143: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xbc00; + valaddr_reg:x4; val_offset:236*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 236*FLEN/8, x6, x1, x2) + +inst_144: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x0; + valaddr_reg:x4; val_offset:238*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 238*FLEN/8, x6, x1, x2) + +inst_145: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x8000; + valaddr_reg:x4; val_offset:240*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 240*FLEN/8, x6, x1, x2) + +inst_146: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x1; + valaddr_reg:x4; val_offset:242*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 242*FLEN/8, x6, x1, x2) + +inst_147: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x8001; + valaddr_reg:x4; val_offset:244*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 244*FLEN/8, x6, x1, x2) + +inst_148: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x2; + valaddr_reg:x4; val_offset:246*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 246*FLEN/8, x6, x1, x2) + +inst_149: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x83fe; + valaddr_reg:x4; val_offset:248*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 248*FLEN/8, x6, x1, x2) + +inst_150: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x3ff; + valaddr_reg:x4; val_offset:250*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 250*FLEN/8, x6, x1, x2) + +inst_151: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x83ff; + valaddr_reg:x4; val_offset:252*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 252*FLEN/8, x6, x1, x2) + +inst_152: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x400; + valaddr_reg:x4; val_offset:254*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 254*FLEN/8, x6, x1, x2) + +inst_153: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x8400; + valaddr_reg:x4; val_offset:256*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 256*FLEN/8, x6, x1, x2) + +inst_154: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x401; + valaddr_reg:x4; val_offset:258*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 258*FLEN/8, x6, x1, x2) + +inst_155: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x8455; + valaddr_reg:x4; val_offset:260*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 260*FLEN/8, x6, x1, x2) + +inst_156: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7bff; + valaddr_reg:x4; val_offset:262*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 262*FLEN/8, x6, x1, x2) + +inst_157: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xfbff; + valaddr_reg:x4; val_offset:264*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 264*FLEN/8, x6, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_3) + +inst_158: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7c00; + valaddr_reg:x4; val_offset:266*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 266*FLEN/8, x6, x1, x2) + +inst_159: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xfc00; + valaddr_reg:x4; val_offset:268*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 268*FLEN/8, x6, x1, x2) + +inst_160: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7e00; + valaddr_reg:x4; val_offset:270*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 270*FLEN/8, x6, x1, x2) + +inst_161: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xfe00; + valaddr_reg:x4; val_offset:272*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 272*FLEN/8, x6, x1, x2) + +inst_162: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7e01; + valaddr_reg:x4; val_offset:274*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 274*FLEN/8, x6, x1, x2) + +inst_163: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xfe55; + valaddr_reg:x4; val_offset:276*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 276*FLEN/8, x6, x1, x2) + +inst_164: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7c01; + valaddr_reg:x4; val_offset:278*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 278*FLEN/8, x6, x1, x2) + +inst_165: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xfd55; + valaddr_reg:x4; val_offset:280*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 280*FLEN/8, x6, x1, x2) + +inst_166: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x3c00; + valaddr_reg:x4; val_offset:282*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 282*FLEN/8, x6, x1, x2) + +inst_167: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xbc00; + valaddr_reg:x4; val_offset:284*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 284*FLEN/8, x6, x1, x2) + +inst_168: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x0; + valaddr_reg:x4; val_offset:286*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 286*FLEN/8, x6, x1, x2) + +inst_169: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8000; + valaddr_reg:x4; val_offset:288*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 288*FLEN/8, x6, x1, x2) + +inst_170: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x1; + valaddr_reg:x4; val_offset:290*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 290*FLEN/8, x6, x1, x2) + +inst_171: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8001; + valaddr_reg:x4; val_offset:292*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 292*FLEN/8, x6, x1, x2) + +inst_172: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x2; + valaddr_reg:x4; val_offset:294*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 294*FLEN/8, x6, x1, x2) + +inst_173: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x83fe; + valaddr_reg:x4; val_offset:296*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 296*FLEN/8, x6, x1, x2) + +inst_174: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x3ff; + valaddr_reg:x4; val_offset:298*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 298*FLEN/8, x6, x1, x2) + +inst_175: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x83ff; + valaddr_reg:x4; val_offset:300*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 300*FLEN/8, x6, x1, x2) + +inst_176: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x400; + valaddr_reg:x4; val_offset:302*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 302*FLEN/8, x6, x1, x2) + +inst_177: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8400; + valaddr_reg:x4; val_offset:304*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 304*FLEN/8, x6, x1, x2) + +inst_178: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x401; + valaddr_reg:x4; val_offset:306*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 306*FLEN/8, x6, x1, x2) + +inst_179: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8455; + valaddr_reg:x4; val_offset:308*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 308*FLEN/8, x6, x1, x2) + +inst_180: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x7bff; + valaddr_reg:x4; val_offset:310*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 310*FLEN/8, x6, x1, x2) + +inst_181: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xfbff; + valaddr_reg:x4; val_offset:312*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 312*FLEN/8, x6, x1, x2) + +inst_182: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x7c00; + valaddr_reg:x4; val_offset:314*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 314*FLEN/8, x6, x1, x2) + +inst_183: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xfc00; + valaddr_reg:x4; val_offset:316*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 316*FLEN/8, x6, x1, x2) + +inst_184: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x7e00; + valaddr_reg:x4; val_offset:318*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 318*FLEN/8, x6, x1, x2) + +inst_185: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xfe00; + valaddr_reg:x4; val_offset:320*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 320*FLEN/8, x6, x1, x2) + +inst_186: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x7e01; + valaddr_reg:x4; val_offset:322*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 322*FLEN/8, x6, x1, x2) + +inst_187: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xfe55; + valaddr_reg:x4; val_offset:324*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 324*FLEN/8, x6, x1, x2) + +inst_188: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x7c01; + valaddr_reg:x4; val_offset:326*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 326*FLEN/8, x6, x1, x2) + +inst_189: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xfd55; + valaddr_reg:x4; val_offset:328*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 328*FLEN/8, x6, x1, x2) + +inst_190: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x3c00; + valaddr_reg:x4; val_offset:330*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 330*FLEN/8, x6, x1, x2) + +inst_191: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xbc00; + valaddr_reg:x4; val_offset:332*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 332*FLEN/8, x6, x1, x2) + +inst_192: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x0; + valaddr_reg:x4; val_offset:334*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 334*FLEN/8, x6, x1, x2) + +inst_193: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x8000; + valaddr_reg:x4; val_offset:336*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 336*FLEN/8, x6, x1, x2) + +inst_194: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x1; + valaddr_reg:x4; val_offset:338*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 338*FLEN/8, x6, x1, x2) + +inst_195: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x8001; + valaddr_reg:x4; val_offset:340*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 340*FLEN/8, x6, x1, x2) + +inst_196: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x2; + valaddr_reg:x4; val_offset:342*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 342*FLEN/8, x6, x1, x2) + +inst_197: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x83fe; + valaddr_reg:x4; val_offset:344*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 344*FLEN/8, x6, x1, x2) + +inst_198: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x3ff; + valaddr_reg:x4; val_offset:346*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 346*FLEN/8, x6, x1, x2) + +inst_199: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x83ff; + valaddr_reg:x4; val_offset:348*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 348*FLEN/8, x6, x1, x2) + +inst_200: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x400; + valaddr_reg:x4; val_offset:350*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 350*FLEN/8, x6, x1, x2) + +inst_201: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x8400; + valaddr_reg:x4; val_offset:352*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 352*FLEN/8, x6, x1, x2) + +inst_202: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x401; + valaddr_reg:x4; val_offset:354*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 354*FLEN/8, x6, x1, x2) + +inst_203: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x8455; + valaddr_reg:x4; val_offset:356*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 356*FLEN/8, x6, x1, x2) + +inst_204: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7bff; + valaddr_reg:x4; val_offset:358*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 358*FLEN/8, x6, x1, x2) + +inst_205: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xfbff; + valaddr_reg:x4; val_offset:360*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 360*FLEN/8, x6, x1, x2) + +inst_206: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7c00; + valaddr_reg:x4; val_offset:362*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 362*FLEN/8, x6, x1, x2) + +inst_207: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xfc00; + valaddr_reg:x4; val_offset:364*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 364*FLEN/8, x6, x1, x2) + +inst_208: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7e00; + valaddr_reg:x4; val_offset:366*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 366*FLEN/8, x6, x1, x2) + +inst_209: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xfe00; + valaddr_reg:x4; val_offset:368*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 368*FLEN/8, x6, x1, x2) + +inst_210: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7e01; + valaddr_reg:x4; val_offset:370*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 370*FLEN/8, x6, x1, x2) + +inst_211: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xfe55; + valaddr_reg:x4; val_offset:372*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 372*FLEN/8, x6, x1, x2) + +inst_212: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7c01; + valaddr_reg:x4; val_offset:374*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 374*FLEN/8, x6, x1, x2) + +inst_213: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xfd55; + valaddr_reg:x4; val_offset:376*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 376*FLEN/8, x6, x1, x2) + +inst_214: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x3c00; + valaddr_reg:x4; val_offset:378*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 378*FLEN/8, x6, x1, x2) + +inst_215: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xbc00; + valaddr_reg:x4; val_offset:380*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 380*FLEN/8, x6, x1, x2) + +inst_216: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x0; + valaddr_reg:x4; val_offset:382*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 382*FLEN/8, x6, x1, x2) + +inst_217: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8000; + valaddr_reg:x4; val_offset:384*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 384*FLEN/8, x6, x1, x2) + +inst_218: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x1; + valaddr_reg:x4; val_offset:386*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 386*FLEN/8, x6, x1, x2) + +inst_219: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8001; + valaddr_reg:x4; val_offset:388*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 388*FLEN/8, x6, x1, x2) + +inst_220: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x2; + valaddr_reg:x4; val_offset:390*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 390*FLEN/8, x6, x1, x2) + +inst_221: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x83fe; + valaddr_reg:x4; val_offset:392*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 392*FLEN/8, x6, x1, x2) + +inst_222: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x3ff; + valaddr_reg:x4; val_offset:394*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 394*FLEN/8, x6, x1, x2) + +inst_223: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x83ff; + valaddr_reg:x4; val_offset:396*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 396*FLEN/8, x6, x1, x2) + +inst_224: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x400; + valaddr_reg:x4; val_offset:398*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 398*FLEN/8, x6, x1, x2) + +inst_225: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8400; + valaddr_reg:x4; val_offset:400*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 400*FLEN/8, x6, x1, x2) + +inst_226: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x401; + valaddr_reg:x4; val_offset:402*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 402*FLEN/8, x6, x1, x2) + +inst_227: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8455; + valaddr_reg:x4; val_offset:404*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 404*FLEN/8, x6, x1, x2) + +inst_228: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x7bff; + valaddr_reg:x4; val_offset:406*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 406*FLEN/8, x6, x1, x2) + +inst_229: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xfbff; + valaddr_reg:x4; val_offset:408*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 408*FLEN/8, x6, x1, x2) + +inst_230: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x7c00; + valaddr_reg:x4; val_offset:410*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 410*FLEN/8, x6, x1, x2) + +inst_231: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xfc00; + valaddr_reg:x4; val_offset:412*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 412*FLEN/8, x6, x1, x2) + +inst_232: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x7e00; + valaddr_reg:x4; val_offset:414*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 414*FLEN/8, x6, x1, x2) + +inst_233: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xfe00; + valaddr_reg:x4; val_offset:416*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 416*FLEN/8, x6, x1, x2) + +inst_234: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x7e01; + valaddr_reg:x4; val_offset:418*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 418*FLEN/8, x6, x1, x2) + +inst_235: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xfe55; + valaddr_reg:x4; val_offset:420*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 420*FLEN/8, x6, x1, x2) + +inst_236: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x7c01; + valaddr_reg:x4; val_offset:422*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 422*FLEN/8, x6, x1, x2) + +inst_237: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xfd55; + valaddr_reg:x4; val_offset:424*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 424*FLEN/8, x6, x1, x2) + +inst_238: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x3c00; + valaddr_reg:x4; val_offset:426*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 426*FLEN/8, x6, x1, x2) + +inst_239: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xbc00; + valaddr_reg:x4; val_offset:428*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 428*FLEN/8, x6, x1, x2) + +inst_240: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x0; + valaddr_reg:x4; val_offset:430*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 430*FLEN/8, x6, x1, x2) + +inst_241: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x8000; + valaddr_reg:x4; val_offset:432*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 432*FLEN/8, x6, x1, x2) + +inst_242: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x1; + valaddr_reg:x4; val_offset:434*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 434*FLEN/8, x6, x1, x2) + +inst_243: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x8001; + valaddr_reg:x4; val_offset:436*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 436*FLEN/8, x6, x1, x2) + +inst_244: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x2; + valaddr_reg:x4; val_offset:438*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 438*FLEN/8, x6, x1, x2) + +inst_245: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x83fe; + valaddr_reg:x4; val_offset:440*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 440*FLEN/8, x6, x1, x2) + +inst_246: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x3ff; + valaddr_reg:x4; val_offset:442*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 442*FLEN/8, x6, x1, x2) + +inst_247: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x83ff; + valaddr_reg:x4; val_offset:444*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 444*FLEN/8, x6, x1, x2) + +inst_248: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x400; + valaddr_reg:x4; val_offset:446*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 446*FLEN/8, x6, x1, x2) + +inst_249: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x8400; + valaddr_reg:x4; val_offset:448*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 448*FLEN/8, x6, x1, x2) + +inst_250: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x401; + valaddr_reg:x4; val_offset:450*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 450*FLEN/8, x6, x1, x2) + +inst_251: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x8455; + valaddr_reg:x4; val_offset:452*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 452*FLEN/8, x6, x1, x2) + +inst_252: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x7bff; + valaddr_reg:x4; val_offset:454*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 454*FLEN/8, x6, x1, x2) + +inst_253: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xfbff; + valaddr_reg:x4; val_offset:456*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 456*FLEN/8, x6, x1, x2) + +inst_254: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x7c00; + valaddr_reg:x4; val_offset:458*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 458*FLEN/8, x6, x1, x2) + +inst_255: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xfc00; + valaddr_reg:x4; val_offset:460*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 460*FLEN/8, x6, x1, x2) + +inst_256: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x7e00; + valaddr_reg:x4; val_offset:462*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 462*FLEN/8, x6, x1, x2) + +inst_257: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xfe00; + valaddr_reg:x4; val_offset:464*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 464*FLEN/8, x6, x1, x2) + +inst_258: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x7e01; + valaddr_reg:x4; val_offset:466*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 466*FLEN/8, x6, x1, x2) + +inst_259: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xfe55; + valaddr_reg:x4; val_offset:468*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 468*FLEN/8, x6, x1, x2) + +inst_260: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x7c01; + valaddr_reg:x4; val_offset:470*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 470*FLEN/8, x6, x1, x2) + +inst_261: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xfd55; + valaddr_reg:x4; val_offset:472*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 472*FLEN/8, x6, x1, x2) + +inst_262: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x3c00; + valaddr_reg:x4; val_offset:474*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 474*FLEN/8, x6, x1, x2) + +inst_263: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xbc00; + valaddr_reg:x4; val_offset:476*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 476*FLEN/8, x6, x1, x2) + +inst_264: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x0; + valaddr_reg:x4; val_offset:478*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 478*FLEN/8, x6, x1, x2) + +inst_265: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x8000; + valaddr_reg:x4; val_offset:480*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 480*FLEN/8, x6, x1, x2) + +inst_266: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x1; + valaddr_reg:x4; val_offset:482*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 482*FLEN/8, x6, x1, x2) + +inst_267: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x8001; + valaddr_reg:x4; val_offset:484*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 484*FLEN/8, x6, x1, x2) + +inst_268: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x2; + valaddr_reg:x4; val_offset:486*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 486*FLEN/8, x6, x1, x2) + +inst_269: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x83fe; + valaddr_reg:x4; val_offset:488*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 488*FLEN/8, x6, x1, x2) + +inst_270: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x3ff; + valaddr_reg:x4; val_offset:490*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 490*FLEN/8, x6, x1, x2) + +inst_271: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x83ff; + valaddr_reg:x4; val_offset:492*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 492*FLEN/8, x6, x1, x2) + +inst_272: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x400; + valaddr_reg:x4; val_offset:494*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 494*FLEN/8, x6, x1, x2) + +inst_273: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x8400; + valaddr_reg:x4; val_offset:496*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 496*FLEN/8, x6, x1, x2) + +inst_274: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x401; + valaddr_reg:x4; val_offset:498*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 498*FLEN/8, x6, x1, x2) + +inst_275: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x8455; + valaddr_reg:x4; val_offset:500*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 500*FLEN/8, x6, x1, x2) + +inst_276: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x7bff; + valaddr_reg:x4; val_offset:502*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 502*FLEN/8, x6, x1, x2) + +inst_277: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xfbff; + valaddr_reg:x4; val_offset:504*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 504*FLEN/8, x6, x1, x2) + +inst_278: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x7c00; + valaddr_reg:x4; val_offset:506*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 506*FLEN/8, x6, x1, x2) + +inst_279: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xfc00; + valaddr_reg:x4; val_offset:508*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 508*FLEN/8, x6, x1, x2) + +inst_280: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x7e00; + valaddr_reg:x4; val_offset:510*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 510*FLEN/8, x6, x1, x2) + +inst_281: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xfe00; + valaddr_reg:x4; val_offset:512*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 512*FLEN/8, x6, x1, x2) + +inst_282: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x7e01; + valaddr_reg:x4; val_offset:514*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 514*FLEN/8, x6, x1, x2) + +inst_283: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xfe55; + valaddr_reg:x4; val_offset:516*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 516*FLEN/8, x6, x1, x2) + +inst_284: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x7c01; + valaddr_reg:x4; val_offset:518*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 518*FLEN/8, x6, x1, x2) + +inst_285: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xfd55; + valaddr_reg:x4; val_offset:520*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 520*FLEN/8, x6, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_4) + +inst_286: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x3c00; + valaddr_reg:x4; val_offset:522*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 522*FLEN/8, x6, x1, x2) + +inst_287: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xbc00; + valaddr_reg:x4; val_offset:524*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 524*FLEN/8, x6, x1, x2) + +inst_288: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x0; + valaddr_reg:x4; val_offset:526*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 526*FLEN/8, x6, x1, x2) + +inst_289: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8000; + valaddr_reg:x4; val_offset:528*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 528*FLEN/8, x6, x1, x2) + +inst_290: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x1; + valaddr_reg:x4; val_offset:530*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 530*FLEN/8, x6, x1, x2) + +inst_291: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8001; + valaddr_reg:x4; val_offset:532*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 532*FLEN/8, x6, x1, x2) + +inst_292: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x2; + valaddr_reg:x4; val_offset:534*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 534*FLEN/8, x6, x1, x2) + +inst_293: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x83fe; + valaddr_reg:x4; val_offset:536*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 536*FLEN/8, x6, x1, x2) + +inst_294: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x3ff; + valaddr_reg:x4; val_offset:538*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 538*FLEN/8, x6, x1, x2) + +inst_295: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x83ff; + valaddr_reg:x4; val_offset:540*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 540*FLEN/8, x6, x1, x2) + +inst_296: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x400; + valaddr_reg:x4; val_offset:542*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 542*FLEN/8, x6, x1, x2) + +inst_297: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8400; + valaddr_reg:x4; val_offset:544*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 544*FLEN/8, x6, x1, x2) + +inst_298: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x401; + valaddr_reg:x4; val_offset:546*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 546*FLEN/8, x6, x1, x2) + +inst_299: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8455; + valaddr_reg:x4; val_offset:548*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 548*FLEN/8, x6, x1, x2) + +inst_300: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7bff; + valaddr_reg:x4; val_offset:550*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 550*FLEN/8, x6, x1, x2) + +inst_301: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xfbff; + valaddr_reg:x4; val_offset:552*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 552*FLEN/8, x6, x1, x2) + +inst_302: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7c00; + valaddr_reg:x4; val_offset:554*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 554*FLEN/8, x6, x1, x2) + +inst_303: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xfc00; + valaddr_reg:x4; val_offset:556*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 556*FLEN/8, x6, x1, x2) + +inst_304: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7e00; + valaddr_reg:x4; val_offset:558*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 558*FLEN/8, x6, x1, x2) + +inst_305: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xfe00; + valaddr_reg:x4; val_offset:560*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 560*FLEN/8, x6, x1, x2) + +inst_306: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7e01; + valaddr_reg:x4; val_offset:562*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 562*FLEN/8, x6, x1, x2) + +inst_307: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xfe55; + valaddr_reg:x4; val_offset:564*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 564*FLEN/8, x6, x1, x2) + +inst_308: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7c01; + valaddr_reg:x4; val_offset:566*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 566*FLEN/8, x6, x1, x2) + +inst_309: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xfd55; + valaddr_reg:x4; val_offset:568*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 568*FLEN/8, x6, x1, x2) + +inst_310: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x3c00; + valaddr_reg:x4; val_offset:570*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 570*FLEN/8, x6, x1, x2) + +inst_311: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xbc00; + valaddr_reg:x4; val_offset:572*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 572*FLEN/8, x6, x1, x2) + +inst_312: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x0; + valaddr_reg:x4; val_offset:574*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 574*FLEN/8, x6, x1, x2) + +inst_313: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8000; + valaddr_reg:x4; val_offset:576*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 576*FLEN/8, x6, x1, x2) + +inst_314: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x1; + valaddr_reg:x4; val_offset:578*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 578*FLEN/8, x6, x1, x2) + +inst_315: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8001; + valaddr_reg:x4; val_offset:580*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 580*FLEN/8, x6, x1, x2) + +inst_316: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x2; + valaddr_reg:x4; val_offset:582*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 582*FLEN/8, x6, x1, x2) + +inst_317: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x83fe; + valaddr_reg:x4; val_offset:584*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 584*FLEN/8, x6, x1, x2) + +inst_318: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x3ff; + valaddr_reg:x4; val_offset:586*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 586*FLEN/8, x6, x1, x2) + +inst_319: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x83ff; + valaddr_reg:x4; val_offset:588*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 588*FLEN/8, x6, x1, x2) + +inst_320: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x400; + valaddr_reg:x4; val_offset:590*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 590*FLEN/8, x6, x1, x2) + +inst_321: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8400; + valaddr_reg:x4; val_offset:592*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 592*FLEN/8, x6, x1, x2) + +inst_322: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x401; + valaddr_reg:x4; val_offset:594*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 594*FLEN/8, x6, x1, x2) + +inst_323: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8455; + valaddr_reg:x4; val_offset:596*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 596*FLEN/8, x6, x1, x2) + +inst_324: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7bff; + valaddr_reg:x4; val_offset:598*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 598*FLEN/8, x6, x1, x2) + +inst_325: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfbff; + valaddr_reg:x4; val_offset:600*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 600*FLEN/8, x6, x1, x2) + +inst_326: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7c00; + valaddr_reg:x4; val_offset:602*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 602*FLEN/8, x6, x1, x2) + +inst_327: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfc00; + valaddr_reg:x4; val_offset:604*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 604*FLEN/8, x6, x1, x2) + +inst_328: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7e00; + valaddr_reg:x4; val_offset:606*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 606*FLEN/8, x6, x1, x2) + +inst_329: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfe00; + valaddr_reg:x4; val_offset:608*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 608*FLEN/8, x6, x1, x2) + +inst_330: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7e01; + valaddr_reg:x4; val_offset:610*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 610*FLEN/8, x6, x1, x2) + +inst_331: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfe55; + valaddr_reg:x4; val_offset:612*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 612*FLEN/8, x6, x1, x2) + +inst_332: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7c01; + valaddr_reg:x4; val_offset:614*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 614*FLEN/8, x6, x1, x2) + +inst_333: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfd55; + valaddr_reg:x4; val_offset:616*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 616*FLEN/8, x6, x1, x2) + +inst_334: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x3c00; + valaddr_reg:x4; val_offset:618*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 618*FLEN/8, x6, x1, x2) + +inst_335: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xbc00; + valaddr_reg:x4; val_offset:620*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 620*FLEN/8, x6, x1, x2) + +inst_336: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x0; + valaddr_reg:x4; val_offset:622*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 622*FLEN/8, x6, x1, x2) + +inst_337: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x8000; + valaddr_reg:x4; val_offset:624*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 624*FLEN/8, x6, x1, x2) + +inst_338: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x1; + valaddr_reg:x4; val_offset:626*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 626*FLEN/8, x6, x1, x2) + +inst_339: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x8001; + valaddr_reg:x4; val_offset:628*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 628*FLEN/8, x6, x1, x2) + +inst_340: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x2; + valaddr_reg:x4; val_offset:630*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 630*FLEN/8, x6, x1, x2) + +inst_341: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x83fe; + valaddr_reg:x4; val_offset:632*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 632*FLEN/8, x6, x1, x2) + +inst_342: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x3ff; + valaddr_reg:x4; val_offset:634*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 634*FLEN/8, x6, x1, x2) + +inst_343: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x83ff; + valaddr_reg:x4; val_offset:636*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 636*FLEN/8, x6, x1, x2) + +inst_344: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x400; + valaddr_reg:x4; val_offset:638*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 638*FLEN/8, x6, x1, x2) + +inst_345: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x8400; + valaddr_reg:x4; val_offset:640*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 640*FLEN/8, x6, x1, x2) + +inst_346: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x401; + valaddr_reg:x4; val_offset:642*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 642*FLEN/8, x6, x1, x2) + +inst_347: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x8455; + valaddr_reg:x4; val_offset:644*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 644*FLEN/8, x6, x1, x2) + +inst_348: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x7bff; + valaddr_reg:x4; val_offset:646*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 646*FLEN/8, x6, x1, x2) + +inst_349: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xfbff; + valaddr_reg:x4; val_offset:648*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 648*FLEN/8, x6, x1, x2) + +inst_350: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x7c00; + valaddr_reg:x4; val_offset:650*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 650*FLEN/8, x6, x1, x2) + +inst_351: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xfc00; + valaddr_reg:x4; val_offset:652*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 652*FLEN/8, x6, x1, x2) + +inst_352: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x7e00; + valaddr_reg:x4; val_offset:654*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 654*FLEN/8, x6, x1, x2) + +inst_353: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xfe00; + valaddr_reg:x4; val_offset:656*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 656*FLEN/8, x6, x1, x2) + +inst_354: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x7e01; + valaddr_reg:x4; val_offset:658*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 658*FLEN/8, x6, x1, x2) + +inst_355: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xfe55; + valaddr_reg:x4; val_offset:660*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 660*FLEN/8, x6, x1, x2) + +inst_356: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x7c01; + valaddr_reg:x4; val_offset:662*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 662*FLEN/8, x6, x1, x2) + +inst_357: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xfd55; + valaddr_reg:x4; val_offset:664*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 664*FLEN/8, x6, x1, x2) + +inst_358: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x3c00; + valaddr_reg:x4; val_offset:666*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 666*FLEN/8, x6, x1, x2) + +inst_359: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xbc00; + valaddr_reg:x4; val_offset:668*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 668*FLEN/8, x6, x1, x2) + +inst_360: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x0; + valaddr_reg:x4; val_offset:670*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 670*FLEN/8, x6, x1, x2) + +inst_361: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x8000; + valaddr_reg:x4; val_offset:672*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 672*FLEN/8, x6, x1, x2) + +inst_362: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x1; + valaddr_reg:x4; val_offset:674*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 674*FLEN/8, x6, x1, x2) + +inst_363: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x8001; + valaddr_reg:x4; val_offset:676*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 676*FLEN/8, x6, x1, x2) + +inst_364: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x2; + valaddr_reg:x4; val_offset:678*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 678*FLEN/8, x6, x1, x2) + +inst_365: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x83fe; + valaddr_reg:x4; val_offset:680*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 680*FLEN/8, x6, x1, x2) + +inst_366: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x3ff; + valaddr_reg:x4; val_offset:682*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 682*FLEN/8, x6, x1, x2) + +inst_367: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x83ff; + valaddr_reg:x4; val_offset:684*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 684*FLEN/8, x6, x1, x2) + +inst_368: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x400; + valaddr_reg:x4; val_offset:686*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 686*FLEN/8, x6, x1, x2) + +inst_369: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x8400; + valaddr_reg:x4; val_offset:688*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 688*FLEN/8, x6, x1, x2) + +inst_370: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x401; + valaddr_reg:x4; val_offset:690*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 690*FLEN/8, x6, x1, x2) + +inst_371: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x8455; + valaddr_reg:x4; val_offset:692*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 692*FLEN/8, x6, x1, x2) + +inst_372: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x7bff; + valaddr_reg:x4; val_offset:694*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 694*FLEN/8, x6, x1, x2) + +inst_373: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xfbff; + valaddr_reg:x4; val_offset:696*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 696*FLEN/8, x6, x1, x2) + +inst_374: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x7c00; + valaddr_reg:x4; val_offset:698*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 698*FLEN/8, x6, x1, x2) + +inst_375: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xfc00; + valaddr_reg:x4; val_offset:700*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 700*FLEN/8, x6, x1, x2) + +inst_376: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x7e00; + valaddr_reg:x4; val_offset:702*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 702*FLEN/8, x6, x1, x2) + +inst_377: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xfe00; + valaddr_reg:x4; val_offset:704*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 704*FLEN/8, x6, x1, x2) + +inst_378: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x7e01; + valaddr_reg:x4; val_offset:706*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 706*FLEN/8, x6, x1, x2) + +inst_379: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xfe55; + valaddr_reg:x4; val_offset:708*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 708*FLEN/8, x6, x1, x2) + +inst_380: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x7c01; + valaddr_reg:x4; val_offset:710*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 710*FLEN/8, x6, x1, x2) + +inst_381: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xfd55; + valaddr_reg:x4; val_offset:712*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 712*FLEN/8, x6, x1, x2) + +inst_382: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x3c00; + valaddr_reg:x4; val_offset:714*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 714*FLEN/8, x6, x1, x2) + +inst_383: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xbc00; + valaddr_reg:x4; val_offset:716*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 716*FLEN/8, x6, x1, x2) + +inst_384: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x0; + valaddr_reg:x4; val_offset:718*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 718*FLEN/8, x6, x1, x2) + +inst_385: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x8000; + valaddr_reg:x4; val_offset:720*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 720*FLEN/8, x6, x1, x2) + +inst_386: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x1; + valaddr_reg:x4; val_offset:722*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 722*FLEN/8, x6, x1, x2) + +inst_387: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x8001; + valaddr_reg:x4; val_offset:724*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 724*FLEN/8, x6, x1, x2) + +inst_388: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x2; + valaddr_reg:x4; val_offset:726*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 726*FLEN/8, x6, x1, x2) + +inst_389: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x83fe; + valaddr_reg:x4; val_offset:728*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 728*FLEN/8, x6, x1, x2) + +inst_390: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x3ff; + valaddr_reg:x4; val_offset:730*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 730*FLEN/8, x6, x1, x2) + +inst_391: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x83ff; + valaddr_reg:x4; val_offset:732*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 732*FLEN/8, x6, x1, x2) + +inst_392: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x400; + valaddr_reg:x4; val_offset:734*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 734*FLEN/8, x6, x1, x2) + +inst_393: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x8400; + valaddr_reg:x4; val_offset:736*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 736*FLEN/8, x6, x1, x2) + +inst_394: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x401; + valaddr_reg:x4; val_offset:738*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 738*FLEN/8, x6, x1, x2) + +inst_395: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x8455; + valaddr_reg:x4; val_offset:740*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 740*FLEN/8, x6, x1, x2) + +inst_396: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x7bff; + valaddr_reg:x4; val_offset:742*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 742*FLEN/8, x6, x1, x2) + +inst_397: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xfbff; + valaddr_reg:x4; val_offset:744*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 744*FLEN/8, x6, x1, x2) + +inst_398: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x7c00; + valaddr_reg:x4; val_offset:746*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 746*FLEN/8, x6, x1, x2) + +inst_399: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xfc00; + valaddr_reg:x4; val_offset:748*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 748*FLEN/8, x6, x1, x2) + +inst_400: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x7e00; + valaddr_reg:x4; val_offset:750*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 750*FLEN/8, x6, x1, x2) + +inst_401: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xfe00; + valaddr_reg:x4; val_offset:752*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 752*FLEN/8, x6, x1, x2) + +inst_402: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x7e01; + valaddr_reg:x4; val_offset:754*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 754*FLEN/8, x6, x1, x2) + +inst_403: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xfe55; + valaddr_reg:x4; val_offset:756*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 756*FLEN/8, x6, x1, x2) + +inst_404: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x7c01; + valaddr_reg:x4; val_offset:758*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 758*FLEN/8, x6, x1, x2) + +inst_405: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xfd55; + valaddr_reg:x4; val_offset:760*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 760*FLEN/8, x6, x1, x2) + +inst_406: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x3c00; + valaddr_reg:x4; val_offset:762*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 762*FLEN/8, x6, x1, x2) + +inst_407: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xbc00; + valaddr_reg:x4; val_offset:764*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 764*FLEN/8, x6, x1, x2) + +inst_408: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x0; + valaddr_reg:x4; val_offset:766*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 766*FLEN/8, x6, x1, x2) + +inst_409: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x8000; + valaddr_reg:x4; val_offset:768*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 768*FLEN/8, x6, x1, x2) + +inst_410: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x1; + valaddr_reg:x4; val_offset:770*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 770*FLEN/8, x6, x1, x2) + +inst_411: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x8001; + valaddr_reg:x4; val_offset:772*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 772*FLEN/8, x6, x1, x2) + +inst_412: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x2; + valaddr_reg:x4; val_offset:774*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 774*FLEN/8, x6, x1, x2) + +inst_413: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x83fe; + valaddr_reg:x4; val_offset:776*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 776*FLEN/8, x6, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_5) + +inst_414: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x3ff; + valaddr_reg:x4; val_offset:778*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 778*FLEN/8, x6, x1, x2) + +inst_415: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x83ff; + valaddr_reg:x4; val_offset:780*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 780*FLEN/8, x6, x1, x2) + +inst_416: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x400; + valaddr_reg:x4; val_offset:782*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 782*FLEN/8, x6, x1, x2) + +inst_417: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x8400; + valaddr_reg:x4; val_offset:784*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 784*FLEN/8, x6, x1, x2) + +inst_418: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x401; + valaddr_reg:x4; val_offset:786*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 786*FLEN/8, x6, x1, x2) + +inst_419: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x8455; + valaddr_reg:x4; val_offset:788*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 788*FLEN/8, x6, x1, x2) + +inst_420: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x7bff; + valaddr_reg:x4; val_offset:790*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 790*FLEN/8, x6, x1, x2) + +inst_421: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xfbff; + valaddr_reg:x4; val_offset:792*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 792*FLEN/8, x6, x1, x2) + +inst_422: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x7c00; + valaddr_reg:x4; val_offset:794*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 794*FLEN/8, x6, x1, x2) + +inst_423: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xfc00; + valaddr_reg:x4; val_offset:796*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 796*FLEN/8, x6, x1, x2) + +inst_424: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x7e00; + valaddr_reg:x4; val_offset:798*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 798*FLEN/8, x6, x1, x2) + +inst_425: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xfe00; + valaddr_reg:x4; val_offset:800*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 800*FLEN/8, x6, x1, x2) + +inst_426: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x7e01; + valaddr_reg:x4; val_offset:802*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 802*FLEN/8, x6, x1, x2) + +inst_427: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xfe55; + valaddr_reg:x4; val_offset:804*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 804*FLEN/8, x6, x1, x2) + +inst_428: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x7c01; + valaddr_reg:x4; val_offset:806*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 806*FLEN/8, x6, x1, x2) + +inst_429: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xfd55; + valaddr_reg:x4; val_offset:808*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 808*FLEN/8, x6, x1, x2) + +inst_430: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x3c00; + valaddr_reg:x4; val_offset:810*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 810*FLEN/8, x6, x1, x2) + +inst_431: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xbc00; + valaddr_reg:x4; val_offset:812*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 812*FLEN/8, x6, x1, x2) + +inst_432: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x0; + valaddr_reg:x4; val_offset:814*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 814*FLEN/8, x6, x1, x2) + +inst_433: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x8000; + valaddr_reg:x4; val_offset:816*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 816*FLEN/8, x6, x1, x2) + +inst_434: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x1; + valaddr_reg:x4; val_offset:818*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 818*FLEN/8, x6, x1, x2) + +inst_435: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x8001; + valaddr_reg:x4; val_offset:820*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 820*FLEN/8, x6, x1, x2) + +inst_436: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x2; + valaddr_reg:x4; val_offset:822*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 822*FLEN/8, x6, x1, x2) + +inst_437: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x83fe; + valaddr_reg:x4; val_offset:824*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 824*FLEN/8, x6, x1, x2) + +inst_438: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x3ff; + valaddr_reg:x4; val_offset:826*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 826*FLEN/8, x6, x1, x2) + +inst_439: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x83ff; + valaddr_reg:x4; val_offset:828*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 828*FLEN/8, x6, x1, x2) + +inst_440: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x400; + valaddr_reg:x4; val_offset:830*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 830*FLEN/8, x6, x1, x2) + +inst_441: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x8400; + valaddr_reg:x4; val_offset:832*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 832*FLEN/8, x6, x1, x2) + +inst_442: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x401; + valaddr_reg:x4; val_offset:834*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 834*FLEN/8, x6, x1, x2) + +inst_443: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x8455; + valaddr_reg:x4; val_offset:836*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 836*FLEN/8, x6, x1, x2) + +inst_444: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x7bff; + valaddr_reg:x4; val_offset:838*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 838*FLEN/8, x6, x1, x2) + +inst_445: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xfbff; + valaddr_reg:x4; val_offset:840*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 840*FLEN/8, x6, x1, x2) + +inst_446: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x7c00; + valaddr_reg:x4; val_offset:842*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 842*FLEN/8, x6, x1, x2) + +inst_447: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xfc00; + valaddr_reg:x4; val_offset:844*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 844*FLEN/8, x6, x1, x2) + +inst_448: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x7e00; + valaddr_reg:x4; val_offset:846*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 846*FLEN/8, x6, x1, x2) + +inst_449: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xfe00; + valaddr_reg:x4; val_offset:848*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 848*FLEN/8, x6, x1, x2) + +inst_450: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x7e01; + valaddr_reg:x4; val_offset:850*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 850*FLEN/8, x6, x1, x2) + +inst_451: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xfe55; + valaddr_reg:x4; val_offset:852*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 852*FLEN/8, x6, x1, x2) + +inst_452: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x7c01; + valaddr_reg:x4; val_offset:854*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 854*FLEN/8, x6, x1, x2) + +inst_453: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xfd55; + valaddr_reg:x4; val_offset:856*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 856*FLEN/8, x6, x1, x2) + +inst_454: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x3c00; + valaddr_reg:x4; val_offset:858*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 858*FLEN/8, x6, x1, x2) + +inst_455: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xbc00; + valaddr_reg:x4; val_offset:860*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 860*FLEN/8, x6, x1, x2) + +inst_456: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x0; + valaddr_reg:x4; val_offset:862*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 862*FLEN/8, x6, x1, x2) + +inst_457: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x8000; + valaddr_reg:x4; val_offset:864*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 864*FLEN/8, x6, x1, x2) + +inst_458: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x1; + valaddr_reg:x4; val_offset:866*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 866*FLEN/8, x6, x1, x2) + +inst_459: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x8001; + valaddr_reg:x4; val_offset:868*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 868*FLEN/8, x6, x1, x2) + +inst_460: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x2; + valaddr_reg:x4; val_offset:870*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 870*FLEN/8, x6, x1, x2) + +inst_461: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x83fe; + valaddr_reg:x4; val_offset:872*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 872*FLEN/8, x6, x1, x2) + +inst_462: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x3ff; + valaddr_reg:x4; val_offset:874*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 874*FLEN/8, x6, x1, x2) + +inst_463: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x83ff; + valaddr_reg:x4; val_offset:876*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 876*FLEN/8, x6, x1, x2) + +inst_464: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x400; + valaddr_reg:x4; val_offset:878*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 878*FLEN/8, x6, x1, x2) + +inst_465: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x8400; + valaddr_reg:x4; val_offset:880*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 880*FLEN/8, x6, x1, x2) + +inst_466: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x401; + valaddr_reg:x4; val_offset:882*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 882*FLEN/8, x6, x1, x2) + +inst_467: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x8455; + valaddr_reg:x4; val_offset:884*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 884*FLEN/8, x6, x1, x2) + +inst_468: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x7bff; + valaddr_reg:x4; val_offset:886*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 886*FLEN/8, x6, x1, x2) + +inst_469: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xfbff; + valaddr_reg:x4; val_offset:888*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 888*FLEN/8, x6, x1, x2) + +inst_470: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x7c00; + valaddr_reg:x4; val_offset:890*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 890*FLEN/8, x6, x1, x2) + +inst_471: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xfc00; + valaddr_reg:x4; val_offset:892*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 892*FLEN/8, x6, x1, x2) + +inst_472: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x7e00; + valaddr_reg:x4; val_offset:894*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 894*FLEN/8, x6, x1, x2) + +inst_473: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xfe00; + valaddr_reg:x4; val_offset:896*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 896*FLEN/8, x6, x1, x2) + +inst_474: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x7e01; + valaddr_reg:x4; val_offset:898*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 898*FLEN/8, x6, x1, x2) + +inst_475: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xfe55; + valaddr_reg:x4; val_offset:900*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 900*FLEN/8, x6, x1, x2) + +inst_476: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x7c01; + valaddr_reg:x4; val_offset:902*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 902*FLEN/8, x6, x1, x2) + +inst_477: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xfd55; + valaddr_reg:x4; val_offset:904*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 904*FLEN/8, x6, x1, x2) + +inst_478: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x3c00; + valaddr_reg:x4; val_offset:906*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 906*FLEN/8, x6, x1, x2) + +inst_479: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xbc00; + valaddr_reg:x4; val_offset:908*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 908*FLEN/8, x6, x1, x2) + +inst_480: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x0; + valaddr_reg:x4; val_offset:910*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 910*FLEN/8, x6, x1, x2) + +inst_481: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x8000; + valaddr_reg:x4; val_offset:912*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 912*FLEN/8, x6, x1, x2) + +inst_482: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x1; + valaddr_reg:x4; val_offset:914*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 914*FLEN/8, x6, x1, x2) + +inst_483: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x8001; + valaddr_reg:x4; val_offset:916*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 916*FLEN/8, x6, x1, x2) + +inst_484: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x2; + valaddr_reg:x4; val_offset:918*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 918*FLEN/8, x6, x1, x2) + +inst_485: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x83fe; + valaddr_reg:x4; val_offset:920*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 920*FLEN/8, x6, x1, x2) + +inst_486: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x3ff; + valaddr_reg:x4; val_offset:922*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 922*FLEN/8, x6, x1, x2) + +inst_487: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x83ff; + valaddr_reg:x4; val_offset:924*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 924*FLEN/8, x6, x1, x2) + +inst_488: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x400; + valaddr_reg:x4; val_offset:926*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 926*FLEN/8, x6, x1, x2) + +inst_489: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x8400; + valaddr_reg:x4; val_offset:928*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 928*FLEN/8, x6, x1, x2) + +inst_490: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x401; + valaddr_reg:x4; val_offset:930*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 930*FLEN/8, x6, x1, x2) + +inst_491: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x8455; + valaddr_reg:x4; val_offset:932*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 932*FLEN/8, x6, x1, x2) + +inst_492: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x7bff; + valaddr_reg:x4; val_offset:934*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 934*FLEN/8, x6, x1, x2) + +inst_493: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xfbff; + valaddr_reg:x4; val_offset:936*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 936*FLEN/8, x6, x1, x2) + +inst_494: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x7c00; + valaddr_reg:x4; val_offset:938*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 938*FLEN/8, x6, x1, x2) + +inst_495: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xfc00; + valaddr_reg:x4; val_offset:940*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 940*FLEN/8, x6, x1, x2) + +inst_496: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x7e00; + valaddr_reg:x4; val_offset:942*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 942*FLEN/8, x6, x1, x2) + +inst_497: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xfe00; + valaddr_reg:x4; val_offset:944*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 944*FLEN/8, x6, x1, x2) + +inst_498: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x7e01; + valaddr_reg:x4; val_offset:946*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 946*FLEN/8, x6, x1, x2) + +inst_499: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xfe55; + valaddr_reg:x4; val_offset:948*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 948*FLEN/8, x6, x1, x2) + +inst_500: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x7c01; + valaddr_reg:x4; val_offset:950*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 950*FLEN/8, x6, x1, x2) + +inst_501: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xfd55; + valaddr_reg:x4; val_offset:952*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 952*FLEN/8, x6, x1, x2) + +inst_502: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x3c00; + valaddr_reg:x4; val_offset:954*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 954*FLEN/8, x6, x1, x2) + +inst_503: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xbc00; + valaddr_reg:x4; val_offset:956*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 956*FLEN/8, x6, x1, x2) + +inst_504: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x0; + valaddr_reg:x4; val_offset:958*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 958*FLEN/8, x6, x1, x2) + +inst_505: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x8000; + valaddr_reg:x4; val_offset:960*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 960*FLEN/8, x6, x1, x2) + +inst_506: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x1; + valaddr_reg:x4; val_offset:962*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 962*FLEN/8, x6, x1, x2) + +inst_507: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x8001; + valaddr_reg:x4; val_offset:964*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 964*FLEN/8, x6, x1, x2) + +inst_508: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x2; + valaddr_reg:x4; val_offset:966*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 966*FLEN/8, x6, x1, x2) + +inst_509: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x83fe; + valaddr_reg:x4; val_offset:968*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 968*FLEN/8, x6, x1, x2) + +inst_510: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x3ff; + valaddr_reg:x4; val_offset:970*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 970*FLEN/8, x6, x1, x2) + +inst_511: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x83ff; + valaddr_reg:x4; val_offset:972*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 972*FLEN/8, x6, x1, x2) + +inst_512: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x400; + valaddr_reg:x4; val_offset:974*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 974*FLEN/8, x6, x1, x2) + +inst_513: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x8400; + valaddr_reg:x4; val_offset:976*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 976*FLEN/8, x6, x1, x2) + +inst_514: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x401; + valaddr_reg:x4; val_offset:978*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 978*FLEN/8, x6, x1, x2) + +inst_515: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x8455; + valaddr_reg:x4; val_offset:980*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 980*FLEN/8, x6, x1, x2) + +inst_516: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x7bff; + valaddr_reg:x4; val_offset:982*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 982*FLEN/8, x6, x1, x2) + +inst_517: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xfbff; + valaddr_reg:x4; val_offset:984*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 984*FLEN/8, x6, x1, x2) + +inst_518: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x7c00; + valaddr_reg:x4; val_offset:986*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 986*FLEN/8, x6, x1, x2) + +inst_519: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xfc00; + valaddr_reg:x4; val_offset:988*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 988*FLEN/8, x6, x1, x2) + +inst_520: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x7e00; + valaddr_reg:x4; val_offset:990*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 990*FLEN/8, x6, x1, x2) + +inst_521: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xfe00; + valaddr_reg:x4; val_offset:992*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 992*FLEN/8, x6, x1, x2) + +inst_522: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x7e01; + valaddr_reg:x4; val_offset:994*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 994*FLEN/8, x6, x1, x2) + +inst_523: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xfe55; + valaddr_reg:x4; val_offset:996*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 996*FLEN/8, x6, x1, x2) + +inst_524: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x7c01; + valaddr_reg:x4; val_offset:998*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 998*FLEN/8, x6, x1, x2) + +inst_525: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xfd55; + valaddr_reg:x4; val_offset:1000*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 1000*FLEN/8, x6, x1, x2) + +inst_526: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x3c00; + valaddr_reg:x4; val_offset:1002*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 1002*FLEN/8, x6, x1, x2) + +inst_527: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xbc00; + valaddr_reg:x4; val_offset:1004*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 1004*FLEN/8, x6, x1, x2) + +inst_528: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x0; + valaddr_reg:x4; val_offset:1006*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 1006*FLEN/8, x6, x1, x2) + +inst_529: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x8000; + valaddr_reg:x4; val_offset:1008*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 1008*FLEN/8, x6, x1, x2) + +inst_530: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x1; + valaddr_reg:x4; val_offset:1010*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 1010*FLEN/8, x6, x1, x2) + +inst_531: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x8001; + valaddr_reg:x4; val_offset:1012*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 1012*FLEN/8, x6, x1, x2) + +inst_532: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2; + valaddr_reg:x4; val_offset:1014*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 1014*FLEN/8, x6, x1, x2) + +inst_533: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x83fe; + valaddr_reg:x4; val_offset:1016*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 1016*FLEN/8, x6, x1, x2) + +inst_534: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3ff; + valaddr_reg:x4; val_offset:1018*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 1018*FLEN/8, x6, x1, x2) + +inst_535: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x83ff; + valaddr_reg:x4; val_offset:1020*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 1020*FLEN/8, x6, x1, x2) + +inst_536: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x400; + valaddr_reg:x4; val_offset:1022*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 1022*FLEN/8, x6, x1, x2) + +inst_537: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x8400; + valaddr_reg:x4; val_offset:1024*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 1024*FLEN/8, x6, x1, x2) + +inst_538: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x401; + valaddr_reg:x4; val_offset:1026*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 1026*FLEN/8, x6, x1, x2) + +inst_539: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x8455; + valaddr_reg:x4; val_offset:1028*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 1028*FLEN/8, x6, x1, x2) + +inst_540: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7bff; + valaddr_reg:x4; val_offset:1030*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 1030*FLEN/8, x6, x1, x2) + +inst_541: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xfbff; + valaddr_reg:x4; val_offset:1032*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 1032*FLEN/8, x6, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_6) + +inst_542: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7c00; + valaddr_reg:x4; val_offset:1034*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 1034*FLEN/8, x6, x1, x2) + +inst_543: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xfc00; + valaddr_reg:x4; val_offset:1036*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 1036*FLEN/8, x6, x1, x2) + +inst_544: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7e00; + valaddr_reg:x4; val_offset:1038*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 1038*FLEN/8, x6, x1, x2) + +inst_545: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xfe00; + valaddr_reg:x4; val_offset:1040*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 1040*FLEN/8, x6, x1, x2) + +inst_546: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7e01; + valaddr_reg:x4; val_offset:1042*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 1042*FLEN/8, x6, x1, x2) + +inst_547: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xfe55; + valaddr_reg:x4; val_offset:1044*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 1044*FLEN/8, x6, x1, x2) + +inst_548: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7c01; + valaddr_reg:x4; val_offset:1046*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 1046*FLEN/8, x6, x1, x2) + +inst_549: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xfd55; + valaddr_reg:x4; val_offset:1048*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 1048*FLEN/8, x6, x1, x2) + +inst_550: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3c00; + valaddr_reg:x4; val_offset:1050*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 1050*FLEN/8, x6, x1, x2) + +inst_551: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xbc00; + valaddr_reg:x4; val_offset:1052*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 1052*FLEN/8, x6, x1, x2) + +inst_552: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x0; + valaddr_reg:x4; val_offset:1054*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 1054*FLEN/8, x6, x1, x2) + +inst_553: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x8000; + valaddr_reg:x4; val_offset:1056*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 1056*FLEN/8, x6, x1, x2) + +inst_554: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x1; + valaddr_reg:x4; val_offset:1058*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 1058*FLEN/8, x6, x1, x2) + +inst_555: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x8001; + valaddr_reg:x4; val_offset:1060*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 1060*FLEN/8, x6, x1, x2) + +inst_556: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x2; + valaddr_reg:x4; val_offset:1062*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 1062*FLEN/8, x6, x1, x2) + +inst_557: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x83fe; + valaddr_reg:x4; val_offset:1064*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 1064*FLEN/8, x6, x1, x2) + +inst_558: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x3ff; + valaddr_reg:x4; val_offset:1066*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 1066*FLEN/8, x6, x1, x2) + +inst_559: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x83ff; + valaddr_reg:x4; val_offset:1068*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 1068*FLEN/8, x6, x1, x2) + +inst_560: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x400; + valaddr_reg:x4; val_offset:1070*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 1070*FLEN/8, x6, x1, x2) + +inst_561: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x8400; + valaddr_reg:x4; val_offset:1072*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 1072*FLEN/8, x6, x1, x2) + +inst_562: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x401; + valaddr_reg:x4; val_offset:1074*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 1074*FLEN/8, x6, x1, x2) + +inst_563: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x8455; + valaddr_reg:x4; val_offset:1076*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 1076*FLEN/8, x6, x1, x2) + +inst_564: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x7bff; + valaddr_reg:x4; val_offset:1078*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 1078*FLEN/8, x6, x1, x2) + +inst_565: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xfbff; + valaddr_reg:x4; val_offset:1080*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 1080*FLEN/8, x6, x1, x2) + +inst_566: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x7c00; + valaddr_reg:x4; val_offset:1082*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 1082*FLEN/8, x6, x1, x2) + +inst_567: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xfc00; + valaddr_reg:x4; val_offset:1084*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 1084*FLEN/8, x6, x1, x2) + +inst_568: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x7e00; + valaddr_reg:x4; val_offset:1086*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 1086*FLEN/8, x6, x1, x2) + +inst_569: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xfe00; + valaddr_reg:x4; val_offset:1088*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 1088*FLEN/8, x6, x1, x2) + +inst_570: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x7e01; + valaddr_reg:x4; val_offset:1090*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 1090*FLEN/8, x6, x1, x2) + +inst_571: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xfe55; + valaddr_reg:x4; val_offset:1092*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 1092*FLEN/8, x6, x1, x2) + +inst_572: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x7c01; + valaddr_reg:x4; val_offset:1094*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 1094*FLEN/8, x6, x1, x2) + +inst_573: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xfd55; + valaddr_reg:x4; val_offset:1096*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 1096*FLEN/8, x6, x1, x2) + +inst_574: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x3c00; + valaddr_reg:x4; val_offset:1098*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 1098*FLEN/8, x6, x1, x2) + +inst_575: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbc00; + valaddr_reg:x4; val_offset:1100*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 1100*FLEN/8, x6, x1, x2) + +inst_576: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x0; + valaddr_reg:x4; val_offset:1102*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 1102*FLEN/8, x6, x1, x2) + +inst_577: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x8000; + valaddr_reg:x4; val_offset:1104*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 1104*FLEN/8, x6, x1, x2) + +inst_578: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x1; + valaddr_reg:x4; val_offset:1106*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 1106*FLEN/8, x6, x1, x2) + +inst_579: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnj.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x83ff; + valaddr_reg:x4; val_offset:1108*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnj.h, x31, x30, x29, 0, 0, x4, 1108*FLEN/8, x6, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(2,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(1023,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(1024,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(1025,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(33877,16,FLEN) +test_dataset_1: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31744,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32256,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32257,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31745,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(15360,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(0,32,FLEN) +test_dataset_2: +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(33790,16,FLEN) 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+NAN_BOXED(64853,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(33791,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x17_0: + .fill 32*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_2: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_3: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_4: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_5: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_6: + .fill 76*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fsgnjn_b1-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fsgnjn_b1-01.S new file mode 100644 index 000000000..bd63ab524 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fsgnjn_b1-01.S @@ -0,0 +1,5934 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 05:26:24 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fsgnjn.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fsgnjn.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fsgnjn_b1 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fsgnjn_b1) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x8,test_dataset_0) +RVTEST_SIGBASE(x4,signature_x4_1) + +inst_0: +// rs2 == rd != rs1, rs1==x24, rs2==x15, rd==x15,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x24; op2:x15; dest:x15; op1val:0x0; op2val:0x0; + valaddr_reg:x8; val_offset:0*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x15, x24, x15, 0, 0, x8, 0*FLEN/8, x18, x4, x6) + +inst_1: +// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==x16, rs2==x7, rd==x19,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x16; op2:x7; dest:x19; op1val:0x0; op2val:0x8000; + valaddr_reg:x8; val_offset:2*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x19, x16, x7, 0, 0, x8, 2*FLEN/8, x18, x4, x6) + +inst_2: +// rs1 == rs2 != rd, rs1==x20, rs2==x20, rd==x3,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x20; op2:x20; dest:x3; op1val:0x0; op2val:0x0; + valaddr_reg:x8; val_offset:4*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x3, x20, x20, 0, 0, x8, 4*FLEN/8, x18, x4, x6) + +inst_3: +// rs1 == rd != rs2, rs1==x22, rs2==x11, rd==x22,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x22; op2:x11; dest:x22; op1val:0x0; op2val:0x8001; + valaddr_reg:x8; val_offset:6*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x22, x22, x11, 0, 0, x8, 6*FLEN/8, x18, x4, x6) + +inst_4: +// rs1 == rs2 == rd, rs1==x10, rs2==x10, rd==x10,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x10; op2:x10; dest:x10; op1val:0x0; op2val:0x0; + valaddr_reg:x8; val_offset:8*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x10, x10, x10, 0, 0, x8, 8*FLEN/8, x18, x4, x6) + +inst_5: +// rs1==x23, rs2==x1, rd==x24,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x23; op2:x1; dest:x24; op1val:0x0; op2val:0x83fe; + valaddr_reg:x8; val_offset:10*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x24, x23, x1, 0, 0, x8, 10*FLEN/8, x18, x4, x6) + +inst_6: +// rs1==x5, rs2==x19, rd==x16,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x5; op2:x19; dest:x16; op1val:0x0; op2val:0x3ff; + valaddr_reg:x8; val_offset:12*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x16, x5, x19, 0, 0, x8, 12*FLEN/8, x18, x4, x6) + +inst_7: +// rs1==x25, rs2==x9, rd==x21,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x25; op2:x9; dest:x21; op1val:0x0; op2val:0x83ff; + valaddr_reg:x8; val_offset:14*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x21, x25, x9, 0, 0, x8, 14*FLEN/8, x18, x4, x6) + +inst_8: +// rs1==x29, rs2==x17, rd==x7,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x29; op2:x17; dest:x7; op1val:0x0; op2val:0x400; + valaddr_reg:x8; val_offset:16*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x7, x29, x17, 0, 0, x8, 16*FLEN/8, x18, x4, x6) + +inst_9: +// rs1==x12, rs2==x22, rd==x13,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x12; op2:x22; dest:x13; op1val:0x0; op2val:0x8400; + valaddr_reg:x8; val_offset:18*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x13, x12, x22, 0, 0, x8, 18*FLEN/8, x18, x4, x6) + +inst_10: +// rs1==x2, rs2==x12, rd==x23,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x2; op2:x12; dest:x23; op1val:0x0; op2val:0x401; + valaddr_reg:x8; val_offset:20*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x23, x2, x12, 0, 0, x8, 20*FLEN/8, x18, x4, x6) + +inst_11: +// rs1==x26, rs2==x0, rd==x2,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x26; op2:x0; dest:x2; op1val:0x0; op2val:0x0; + valaddr_reg:x8; val_offset:22*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x2, x26, x0, 0, 0, x8, 22*FLEN/8, x18, x4, x6) + +inst_12: +// rs1==x21, rs2==x13, rd==x14,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x21; op2:x13; dest:x14; op1val:0x0; op2val:0x7bff; + valaddr_reg:x8; val_offset:24*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x14, x21, x13, 0, 0, x8, 24*FLEN/8, x18, x4, x6) +RVTEST_VALBASEUPD(x2,test_dataset_1) + +inst_13: +// rs1==x19, rs2==x27, rd==x18,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x19; op2:x27; dest:x18; op1val:0x0; op2val:0xfbff; + valaddr_reg:x2; val_offset:0*FLEN/8; fcsr: 0; + correctval:??; testreg:x6 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x18, x19, x27, 0, 0, x2, 0*FLEN/8, x7, x4, x6) + +inst_14: +// rs1==x9, rs2==x24, rd==x31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x9; op2:x24; dest:x31; op1val:0x0; op2val:0x7c00; + valaddr_reg:x2; val_offset:2*FLEN/8; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x9, x24, 0, 0, x2, 2*FLEN/8, x7, x4, x12) +RVTEST_SIGBASE(x10,signature_x10_0) + +inst_15: +// rs1==x3, rs2==x16, rd==x8,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x3; op2:x16; dest:x8; op1val:0x0; op2val:0xfc00; + valaddr_reg:x2; val_offset:4*FLEN/8; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x8, x3, x16, 0, 0, x2, 4*FLEN/8, x7, x10, x12) + +inst_16: +// rs1==x30, rs2==x18, rd==x0,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x18; dest:x0; op1val:0x0; op2val:0x7e00; + valaddr_reg:x2; val_offset:6*FLEN/8; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x0, x30, x18, 0, 0, x2, 6*FLEN/8, x7, x10, x12) + +inst_17: +// rs1==x15, rs2==x30, rd==x17,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x15; op2:x30; dest:x17; op1val:0x0; op2val:0xfe00; + valaddr_reg:x2; val_offset:8*FLEN/8; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x17, x15, x30, 0, 0, x2, 8*FLEN/8, x7, x10, x12) + +inst_18: +// rs1==x27, rs2==x28, rd==x6,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x27; op2:x28; dest:x6; op1val:0x0; op2val:0x7e01; + valaddr_reg:x2; val_offset:10*FLEN/8; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x6, x27, x28, 0, 0, x2, 10*FLEN/8, x7, x10, x12) + +inst_19: +// rs1==x0, rs2==x4, rd==x11,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x0; op2:x4; dest:x11; op1val:0x0; op2val:0xfe55; + valaddr_reg:x2; val_offset:12*FLEN/8; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x11, x0, x4, 0, 0, x2, 12*FLEN/8, x7, x10, x12) + +inst_20: +// rs1==x1, rs2==x29, rd==x5,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x1; op2:x29; dest:x5; op1val:0x0; op2val:0x7c01; + valaddr_reg:x2; val_offset:14*FLEN/8; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x5, x1, x29, 0, 0, x2, 14*FLEN/8, x7, x10, x12) + +inst_21: +// rs1==x14, rs2==x23, rd==x20,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x14; op2:x23; dest:x20; op1val:0x0; op2val:0xfd55; + valaddr_reg:x2; val_offset:16*FLEN/8; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x20, x14, x23, 0, 0, x2, 16*FLEN/8, x7, x10, x12) + +inst_22: +// rs1==x8, rs2==x6, rd==x26,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x8; op2:x6; dest:x26; op1val:0x0; op2val:0x3c00; + valaddr_reg:x2; val_offset:18*FLEN/8; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x26, x8, x6, 0, 0, x2, 18*FLEN/8, x7, x10, x12) +RVTEST_VALBASEUPD(x15,test_dataset_2) + +inst_23: +// rs1==x18, rs2==x21, rd==x4,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x18; op2:x21; dest:x4; op1val:0x0; op2val:0xbc00; + valaddr_reg:x15; val_offset:0*FLEN/8; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x4, x18, x21, 0, 0, x15, 0*FLEN/8, x16, x10, x12) + +inst_24: +// rs1==x6, rs2==x5, rd==x28,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x6; op2:x5; dest:x28; op1val:0x8000; op2val:0x0; + valaddr_reg:x15; val_offset:2*FLEN/8; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x28, x6, x5, 0, 0, x15, 2*FLEN/8, x16, x10, x12) + +inst_25: +// rs1==x17, rs2==x25, rd==x27,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x17; op2:x25; dest:x27; op1val:0x8000; op2val:0x8000; + valaddr_reg:x15; val_offset:4*FLEN/8; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x27, x17, x25, 0, 0, x15, 4*FLEN/8, x16, x10, x12) + +inst_26: +// rs1==x7, rs2==x2, rd==x1,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x7; op2:x2; dest:x1; op1val:0x8000; op2val:0x1; + valaddr_reg:x15; val_offset:6*FLEN/8; fcsr: 0; + correctval:??; testreg:x12 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x1, x7, x2, 0, 0, x15, 6*FLEN/8, x16, x10, x12) + +inst_27: +// rs1==x4, rs2==x26, rd==x9,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x4; op2:x26; dest:x9; op1val:0x8000; op2val:0x8001; + valaddr_reg:x15; val_offset:8*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x9, x4, x26, 0, 0, x15, 8*FLEN/8, x16, x10, x2) + +inst_28: +// rs1==x13, rs2==x14, rd==x30,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x13; op2:x14; dest:x30; op1val:0x8000; op2val:0x2; + valaddr_reg:x15; val_offset:10*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x30, x13, x14, 0, 0, x15, 10*FLEN/8, x16, x10, x2) + +inst_29: +// rs1==x28, rs2==x3, rd==x12,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x28; op2:x3; dest:x12; op1val:0x8000; op2val:0x83fe; + valaddr_reg:x15; val_offset:12*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x12, x28, x3, 0, 0, x15, 12*FLEN/8, x16, x10, x2) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_30: +// rs1==x31, rs2==x8, rd==x29,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x31; op2:x8; dest:x29; op1val:0x8000; op2val:0x3ff; + valaddr_reg:x15; val_offset:14*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x29, x31, x8, 0, 0, x15, 14*FLEN/8, x16, x1, x2) + +inst_31: +// rs1==x11, rs2==x31, rd==x25,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x11; op2:x31; dest:x25; op1val:0x8000; op2val:0x83ff; + valaddr_reg:x15; val_offset:16*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x25, x11, x31, 0, 0, x15, 16*FLEN/8, x16, x1, x2) + +inst_32: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x400; + valaddr_reg:x15; val_offset:18*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 18*FLEN/8, x16, x1, x2) + +inst_33: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8400; + valaddr_reg:x15; val_offset:20*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 20*FLEN/8, x16, x1, x2) + +inst_34: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x401; + valaddr_reg:x15; val_offset:22*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 22*FLEN/8, x16, x1, x2) + +inst_35: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8455; + valaddr_reg:x15; val_offset:24*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 24*FLEN/8, x16, x1, x2) + +inst_36: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x7bff; + valaddr_reg:x15; val_offset:26*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 26*FLEN/8, x16, x1, x2) + +inst_37: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xfbff; + valaddr_reg:x15; val_offset:28*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 28*FLEN/8, x16, x1, x2) + +inst_38: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x7c00; + valaddr_reg:x15; val_offset:30*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 30*FLEN/8, x16, x1, x2) + +inst_39: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xfc00; + valaddr_reg:x15; val_offset:32*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 32*FLEN/8, x16, x1, x2) + +inst_40: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x7e00; + valaddr_reg:x15; val_offset:34*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 34*FLEN/8, x16, x1, x2) + +inst_41: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xfe00; + valaddr_reg:x15; val_offset:36*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 36*FLEN/8, x16, x1, x2) + +inst_42: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x7e01; + valaddr_reg:x15; val_offset:38*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 38*FLEN/8, x16, x1, x2) + +inst_43: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xfe55; + valaddr_reg:x15; val_offset:40*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 40*FLEN/8, x16, x1, x2) + +inst_44: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x7c01; + valaddr_reg:x15; val_offset:42*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 42*FLEN/8, x16, x1, x2) + +inst_45: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xfd55; + valaddr_reg:x15; val_offset:44*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 44*FLEN/8, x16, x1, x2) + +inst_46: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x3c00; + valaddr_reg:x15; val_offset:46*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 46*FLEN/8, x16, x1, x2) + +inst_47: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xbc00; + valaddr_reg:x15; val_offset:48*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 48*FLEN/8, x16, x1, x2) + +inst_48: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x0; + valaddr_reg:x15; val_offset:50*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 50*FLEN/8, x16, x1, x2) + +inst_49: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x8000; + valaddr_reg:x15; val_offset:52*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 52*FLEN/8, x16, x1, x2) + +inst_50: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x1; + valaddr_reg:x15; val_offset:54*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 54*FLEN/8, x16, x1, x2) + +inst_51: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x8001; + valaddr_reg:x15; val_offset:56*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 56*FLEN/8, x16, x1, x2) + +inst_52: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x2; + valaddr_reg:x15; val_offset:58*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 58*FLEN/8, x16, x1, x2) + +inst_53: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x83fe; + valaddr_reg:x15; val_offset:60*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 60*FLEN/8, x16, x1, x2) + +inst_54: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x3ff; + valaddr_reg:x15; val_offset:62*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 62*FLEN/8, x16, x1, x2) + +inst_55: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x83ff; + valaddr_reg:x15; val_offset:64*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 64*FLEN/8, x16, x1, x2) + +inst_56: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x400; + valaddr_reg:x15; val_offset:66*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 66*FLEN/8, x16, x1, x2) + +inst_57: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x8400; + valaddr_reg:x15; val_offset:68*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 68*FLEN/8, x16, x1, x2) + +inst_58: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x401; + valaddr_reg:x15; val_offset:70*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 70*FLEN/8, x16, x1, x2) + +inst_59: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x8455; + valaddr_reg:x15; val_offset:72*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 72*FLEN/8, x16, x1, x2) + +inst_60: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7bff; + valaddr_reg:x15; val_offset:74*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 74*FLEN/8, x16, x1, x2) + +inst_61: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xfbff; + valaddr_reg:x15; val_offset:76*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 76*FLEN/8, x16, x1, x2) + +inst_62: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7c00; + valaddr_reg:x15; val_offset:78*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 78*FLEN/8, x16, x1, x2) + +inst_63: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xfc00; + valaddr_reg:x15; val_offset:80*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 80*FLEN/8, x16, x1, x2) + +inst_64: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7e00; + valaddr_reg:x15; val_offset:82*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 82*FLEN/8, x16, x1, x2) + +inst_65: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xfe00; + valaddr_reg:x15; val_offset:84*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 84*FLEN/8, x16, x1, x2) + +inst_66: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7e01; + valaddr_reg:x15; val_offset:86*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 86*FLEN/8, x16, x1, x2) + +inst_67: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xfe55; + valaddr_reg:x15; val_offset:88*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 88*FLEN/8, x16, x1, x2) + +inst_68: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7c01; + valaddr_reg:x15; val_offset:90*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 90*FLEN/8, x16, x1, x2) + +inst_69: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xfd55; + valaddr_reg:x15; val_offset:92*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 92*FLEN/8, x16, x1, x2) + +inst_70: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x3c00; + valaddr_reg:x15; val_offset:94*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 94*FLEN/8, x16, x1, x2) + +inst_71: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xbc00; + valaddr_reg:x15; val_offset:96*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 96*FLEN/8, x16, x1, x2) + +inst_72: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x0; + valaddr_reg:x15; val_offset:98*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 98*FLEN/8, x16, x1, x2) + +inst_73: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8000; + valaddr_reg:x15; val_offset:100*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 100*FLEN/8, x16, x1, x2) + +inst_74: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x1; + valaddr_reg:x15; val_offset:102*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 102*FLEN/8, x16, x1, x2) + +inst_75: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8001; + valaddr_reg:x15; val_offset:104*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 104*FLEN/8, x16, x1, x2) + +inst_76: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x2; + valaddr_reg:x15; val_offset:106*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 106*FLEN/8, x16, x1, x2) + +inst_77: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x83fe; + valaddr_reg:x15; val_offset:108*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 108*FLEN/8, x16, x1, x2) + +inst_78: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x3ff; + valaddr_reg:x15; val_offset:110*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 110*FLEN/8, x16, x1, x2) + +inst_79: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x83ff; + valaddr_reg:x15; val_offset:112*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 112*FLEN/8, x16, x1, x2) + +inst_80: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x400; + valaddr_reg:x15; val_offset:114*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 114*FLEN/8, x16, x1, x2) + +inst_81: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8400; + valaddr_reg:x15; val_offset:116*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 116*FLEN/8, x16, x1, x2) + +inst_82: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x401; + valaddr_reg:x15; val_offset:118*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 118*FLEN/8, x16, x1, x2) + +inst_83: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8455; + valaddr_reg:x15; val_offset:120*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 120*FLEN/8, x16, x1, x2) + +inst_84: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x7bff; + valaddr_reg:x15; val_offset:122*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 122*FLEN/8, x16, x1, x2) + +inst_85: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xfbff; + valaddr_reg:x15; val_offset:124*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 124*FLEN/8, x16, x1, x2) + +inst_86: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x7c00; + valaddr_reg:x15; val_offset:126*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 126*FLEN/8, x16, x1, x2) + +inst_87: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xfc00; + valaddr_reg:x15; val_offset:128*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 128*FLEN/8, x16, x1, x2) + +inst_88: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x7e00; + valaddr_reg:x15; val_offset:130*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 130*FLEN/8, x16, x1, x2) + +inst_89: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xfe00; + valaddr_reg:x15; val_offset:132*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 132*FLEN/8, x16, x1, x2) + +inst_90: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x7e01; + valaddr_reg:x15; val_offset:134*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 134*FLEN/8, x16, x1, x2) + +inst_91: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xfe55; + valaddr_reg:x15; val_offset:136*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 136*FLEN/8, x16, x1, x2) + +inst_92: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x7c01; + valaddr_reg:x15; val_offset:138*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 138*FLEN/8, x16, x1, x2) + +inst_93: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xfd55; + valaddr_reg:x15; val_offset:140*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 140*FLEN/8, x16, x1, x2) + +inst_94: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x3c00; + valaddr_reg:x15; val_offset:142*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 142*FLEN/8, x16, x1, x2) + +inst_95: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xbc00; + valaddr_reg:x15; val_offset:144*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 144*FLEN/8, x16, x1, x2) + +inst_96: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x0; + valaddr_reg:x15; val_offset:146*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 146*FLEN/8, x16, x1, x2) + +inst_97: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x8000; + valaddr_reg:x15; val_offset:148*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 148*FLEN/8, x16, x1, x2) + +inst_98: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x1; + valaddr_reg:x15; val_offset:150*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 150*FLEN/8, x16, x1, x2) + +inst_99: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x8001; + valaddr_reg:x15; val_offset:152*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 152*FLEN/8, x16, x1, x2) + +inst_100: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x2; + valaddr_reg:x15; val_offset:154*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 154*FLEN/8, x16, x1, x2) + +inst_101: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x83fe; + valaddr_reg:x15; val_offset:156*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 156*FLEN/8, x16, x1, x2) + +inst_102: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x3ff; + valaddr_reg:x15; val_offset:158*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 158*FLEN/8, x16, x1, x2) + +inst_103: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x83ff; + valaddr_reg:x15; val_offset:160*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 160*FLEN/8, x16, x1, x2) + +inst_104: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x400; + valaddr_reg:x15; val_offset:162*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 162*FLEN/8, x16, x1, x2) + +inst_105: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x8400; + valaddr_reg:x15; val_offset:164*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 164*FLEN/8, x16, x1, x2) + +inst_106: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x401; + valaddr_reg:x15; val_offset:166*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 166*FLEN/8, x16, x1, x2) + +inst_107: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x8455; + valaddr_reg:x15; val_offset:168*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 168*FLEN/8, x16, x1, x2) + +inst_108: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x7bff; + valaddr_reg:x15; val_offset:170*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 170*FLEN/8, x16, x1, x2) + +inst_109: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xfbff; + valaddr_reg:x15; val_offset:172*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 172*FLEN/8, x16, x1, x2) + +inst_110: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x7c00; + valaddr_reg:x15; val_offset:174*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 174*FLEN/8, x16, x1, x2) + +inst_111: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xfc00; + valaddr_reg:x15; val_offset:176*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 176*FLEN/8, x16, x1, x2) + +inst_112: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x7e00; + valaddr_reg:x15; val_offset:178*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 178*FLEN/8, x16, x1, x2) + +inst_113: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xfe00; + valaddr_reg:x15; val_offset:180*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 180*FLEN/8, x16, x1, x2) + +inst_114: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x7e01; + valaddr_reg:x15; val_offset:182*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 182*FLEN/8, x16, x1, x2) + +inst_115: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xfe55; + valaddr_reg:x15; val_offset:184*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 184*FLEN/8, x16, x1, x2) + +inst_116: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x7c01; + valaddr_reg:x15; val_offset:186*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 186*FLEN/8, x16, x1, x2) + +inst_117: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xfd55; + valaddr_reg:x15; val_offset:188*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 188*FLEN/8, x16, x1, x2) + +inst_118: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x3c00; + valaddr_reg:x15; val_offset:190*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 190*FLEN/8, x16, x1, x2) + +inst_119: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xbc00; + valaddr_reg:x15; val_offset:192*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 192*FLEN/8, x16, x1, x2) + +inst_120: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x0; + valaddr_reg:x15; val_offset:194*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 194*FLEN/8, x16, x1, x2) + +inst_121: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x8000; + valaddr_reg:x15; val_offset:196*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 196*FLEN/8, x16, x1, x2) + +inst_122: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x1; + valaddr_reg:x15; val_offset:198*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 198*FLEN/8, x16, x1, x2) + +inst_123: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x8001; + valaddr_reg:x15; val_offset:200*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 200*FLEN/8, x16, x1, x2) + +inst_124: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x2; + valaddr_reg:x15; val_offset:202*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 202*FLEN/8, x16, x1, x2) + +inst_125: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x83fe; + valaddr_reg:x15; val_offset:204*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 204*FLEN/8, x16, x1, x2) + +inst_126: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x3ff; + valaddr_reg:x15; val_offset:206*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 206*FLEN/8, x16, x1, x2) + +inst_127: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x83ff; + valaddr_reg:x15; val_offset:208*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 208*FLEN/8, x16, x1, x2) + +inst_128: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x400; + valaddr_reg:x15; val_offset:210*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 210*FLEN/8, x16, x1, x2) + +inst_129: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x8400; + valaddr_reg:x15; val_offset:212*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 212*FLEN/8, x16, x1, x2) + +inst_130: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x401; + valaddr_reg:x15; val_offset:214*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 214*FLEN/8, x16, x1, x2) + +inst_131: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x8455; + valaddr_reg:x15; val_offset:216*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 216*FLEN/8, x16, x1, x2) + +inst_132: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x7bff; + valaddr_reg:x15; val_offset:218*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 218*FLEN/8, x16, x1, x2) + +inst_133: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xfbff; + valaddr_reg:x15; val_offset:220*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 220*FLEN/8, x16, x1, x2) + +inst_134: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x7c00; + valaddr_reg:x15; val_offset:222*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 222*FLEN/8, x16, x1, x2) + +inst_135: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xfc00; + valaddr_reg:x15; val_offset:224*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 224*FLEN/8, x16, x1, x2) + +inst_136: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x7e00; + valaddr_reg:x15; val_offset:226*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 226*FLEN/8, x16, x1, x2) + +inst_137: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xfe00; + valaddr_reg:x15; val_offset:228*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 228*FLEN/8, x16, x1, x2) + +inst_138: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x7e01; + valaddr_reg:x15; val_offset:230*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 230*FLEN/8, x16, x1, x2) + +inst_139: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xfe55; + valaddr_reg:x15; val_offset:232*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 232*FLEN/8, x16, x1, x2) + +inst_140: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x7c01; + valaddr_reg:x15; val_offset:234*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 234*FLEN/8, x16, x1, x2) + +inst_141: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xfd55; + valaddr_reg:x15; val_offset:236*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 236*FLEN/8, x16, x1, x2) + +inst_142: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x3c00; + valaddr_reg:x15; val_offset:238*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 238*FLEN/8, x16, x1, x2) + +inst_143: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xbc00; + valaddr_reg:x15; val_offset:240*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 240*FLEN/8, x16, x1, x2) + +inst_144: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x0; + valaddr_reg:x15; val_offset:242*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 242*FLEN/8, x16, x1, x2) + +inst_145: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x8000; + valaddr_reg:x15; val_offset:244*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 244*FLEN/8, x16, x1, x2) + +inst_146: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x1; + valaddr_reg:x15; val_offset:246*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 246*FLEN/8, x16, x1, x2) + +inst_147: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x8001; + valaddr_reg:x15; val_offset:248*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 248*FLEN/8, x16, x1, x2) + +inst_148: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x2; + valaddr_reg:x15; val_offset:250*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 250*FLEN/8, x16, x1, x2) + +inst_149: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x83fe; + valaddr_reg:x15; val_offset:252*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 252*FLEN/8, x16, x1, x2) + +inst_150: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x3ff; + valaddr_reg:x15; val_offset:254*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 254*FLEN/8, x16, x1, x2) + +inst_151: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x83ff; + valaddr_reg:x15; val_offset:256*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 256*FLEN/8, x16, x1, x2) + +inst_152: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x400; + valaddr_reg:x15; val_offset:258*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 258*FLEN/8, x16, x1, x2) + +inst_153: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x8400; + valaddr_reg:x15; val_offset:260*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 260*FLEN/8, x16, x1, x2) + +inst_154: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x401; + valaddr_reg:x15; val_offset:262*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 262*FLEN/8, x16, x1, x2) + +inst_155: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x8455; + valaddr_reg:x15; val_offset:264*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 264*FLEN/8, x16, x1, x2) + +inst_156: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7bff; + valaddr_reg:x15; val_offset:266*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 266*FLEN/8, x16, x1, x2) + +inst_157: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xfbff; + valaddr_reg:x15; val_offset:268*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 268*FLEN/8, x16, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_158: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7c00; + valaddr_reg:x15; val_offset:270*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 270*FLEN/8, x16, x1, x2) + +inst_159: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xfc00; + valaddr_reg:x15; val_offset:272*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 272*FLEN/8, x16, x1, x2) + +inst_160: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7e00; + valaddr_reg:x15; val_offset:274*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 274*FLEN/8, x16, x1, x2) + +inst_161: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xfe00; + valaddr_reg:x15; val_offset:276*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 276*FLEN/8, x16, x1, x2) + +inst_162: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7e01; + valaddr_reg:x15; val_offset:278*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 278*FLEN/8, x16, x1, x2) + +inst_163: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xfe55; + valaddr_reg:x15; val_offset:280*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 280*FLEN/8, x16, x1, x2) + +inst_164: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7c01; + valaddr_reg:x15; val_offset:282*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 282*FLEN/8, x16, x1, x2) + +inst_165: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xfd55; + valaddr_reg:x15; val_offset:284*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 284*FLEN/8, x16, x1, x2) + +inst_166: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x3c00; + valaddr_reg:x15; val_offset:286*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 286*FLEN/8, x16, x1, x2) + +inst_167: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xbc00; + valaddr_reg:x15; val_offset:288*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 288*FLEN/8, x16, x1, x2) + +inst_168: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x0; + valaddr_reg:x15; val_offset:290*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 290*FLEN/8, x16, x1, x2) + +inst_169: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8000; + valaddr_reg:x15; val_offset:292*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 292*FLEN/8, x16, x1, x2) + +inst_170: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x1; + valaddr_reg:x15; val_offset:294*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 294*FLEN/8, x16, x1, x2) + +inst_171: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8001; + valaddr_reg:x15; val_offset:296*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 296*FLEN/8, x16, x1, x2) + +inst_172: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x2; + valaddr_reg:x15; val_offset:298*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 298*FLEN/8, x16, x1, x2) + +inst_173: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x83fe; + valaddr_reg:x15; val_offset:300*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 300*FLEN/8, x16, x1, x2) + +inst_174: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x3ff; + valaddr_reg:x15; val_offset:302*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 302*FLEN/8, x16, x1, x2) + +inst_175: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x83ff; + valaddr_reg:x15; val_offset:304*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 304*FLEN/8, x16, x1, x2) + +inst_176: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x400; + valaddr_reg:x15; val_offset:306*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 306*FLEN/8, x16, x1, x2) + +inst_177: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8400; + valaddr_reg:x15; val_offset:308*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 308*FLEN/8, x16, x1, x2) + +inst_178: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x401; + valaddr_reg:x15; val_offset:310*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 310*FLEN/8, x16, x1, x2) + +inst_179: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8455; + valaddr_reg:x15; val_offset:312*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 312*FLEN/8, x16, x1, x2) + +inst_180: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x7bff; + valaddr_reg:x15; val_offset:314*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 314*FLEN/8, x16, x1, x2) + +inst_181: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xfbff; + valaddr_reg:x15; val_offset:316*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 316*FLEN/8, x16, x1, x2) + +inst_182: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x7c00; + valaddr_reg:x15; val_offset:318*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 318*FLEN/8, x16, x1, x2) + +inst_183: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xfc00; + valaddr_reg:x15; val_offset:320*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 320*FLEN/8, x16, x1, x2) + +inst_184: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x7e00; + valaddr_reg:x15; val_offset:322*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 322*FLEN/8, x16, x1, x2) + +inst_185: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xfe00; + valaddr_reg:x15; val_offset:324*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 324*FLEN/8, x16, x1, x2) + +inst_186: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x7e01; + valaddr_reg:x15; val_offset:326*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 326*FLEN/8, x16, x1, x2) + +inst_187: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xfe55; + valaddr_reg:x15; val_offset:328*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 328*FLEN/8, x16, x1, x2) + +inst_188: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x7c01; + valaddr_reg:x15; val_offset:330*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 330*FLEN/8, x16, x1, x2) + +inst_189: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xfd55; + valaddr_reg:x15; val_offset:332*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 332*FLEN/8, x16, x1, x2) + +inst_190: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x3c00; + valaddr_reg:x15; val_offset:334*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 334*FLEN/8, x16, x1, x2) + +inst_191: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xbc00; + valaddr_reg:x15; val_offset:336*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 336*FLEN/8, x16, x1, x2) + +inst_192: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x0; + valaddr_reg:x15; val_offset:338*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 338*FLEN/8, x16, x1, x2) + +inst_193: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x8000; + valaddr_reg:x15; val_offset:340*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 340*FLEN/8, x16, x1, x2) + +inst_194: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x1; + valaddr_reg:x15; val_offset:342*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 342*FLEN/8, x16, x1, x2) + +inst_195: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x8001; + valaddr_reg:x15; val_offset:344*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 344*FLEN/8, x16, x1, x2) + +inst_196: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x2; + valaddr_reg:x15; val_offset:346*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 346*FLEN/8, x16, x1, x2) + +inst_197: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x83fe; + valaddr_reg:x15; val_offset:348*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 348*FLEN/8, x16, x1, x2) + +inst_198: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x3ff; + valaddr_reg:x15; val_offset:350*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 350*FLEN/8, x16, x1, x2) + +inst_199: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x83ff; + valaddr_reg:x15; val_offset:352*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 352*FLEN/8, x16, x1, x2) + +inst_200: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x400; + valaddr_reg:x15; val_offset:354*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 354*FLEN/8, x16, x1, x2) + +inst_201: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x8400; + valaddr_reg:x15; val_offset:356*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 356*FLEN/8, x16, x1, x2) + +inst_202: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x401; + valaddr_reg:x15; val_offset:358*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 358*FLEN/8, x16, x1, x2) + +inst_203: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x8455; + valaddr_reg:x15; val_offset:360*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 360*FLEN/8, x16, x1, x2) + +inst_204: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7bff; + valaddr_reg:x15; val_offset:362*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 362*FLEN/8, x16, x1, x2) + +inst_205: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xfbff; + valaddr_reg:x15; val_offset:364*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 364*FLEN/8, x16, x1, x2) + +inst_206: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7c00; + valaddr_reg:x15; val_offset:366*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 366*FLEN/8, x16, x1, x2) + +inst_207: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xfc00; + valaddr_reg:x15; val_offset:368*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 368*FLEN/8, x16, x1, x2) + +inst_208: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7e00; + valaddr_reg:x15; val_offset:370*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 370*FLEN/8, x16, x1, x2) + +inst_209: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xfe00; + valaddr_reg:x15; val_offset:372*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 372*FLEN/8, x16, x1, x2) + +inst_210: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7e01; + valaddr_reg:x15; val_offset:374*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 374*FLEN/8, x16, x1, x2) + +inst_211: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xfe55; + valaddr_reg:x15; val_offset:376*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 376*FLEN/8, x16, x1, x2) + +inst_212: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7c01; + valaddr_reg:x15; val_offset:378*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 378*FLEN/8, x16, x1, x2) + +inst_213: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xfd55; + valaddr_reg:x15; val_offset:380*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 380*FLEN/8, x16, x1, x2) + +inst_214: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x3c00; + valaddr_reg:x15; val_offset:382*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 382*FLEN/8, x16, x1, x2) + +inst_215: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xbc00; + valaddr_reg:x15; val_offset:384*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 384*FLEN/8, x16, x1, x2) + +inst_216: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x0; + valaddr_reg:x15; val_offset:386*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 386*FLEN/8, x16, x1, x2) + +inst_217: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8000; + valaddr_reg:x15; val_offset:388*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 388*FLEN/8, x16, x1, x2) + +inst_218: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x1; + valaddr_reg:x15; val_offset:390*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 390*FLEN/8, x16, x1, x2) + +inst_219: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8001; + valaddr_reg:x15; val_offset:392*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 392*FLEN/8, x16, x1, x2) + +inst_220: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x2; + valaddr_reg:x15; val_offset:394*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 394*FLEN/8, x16, x1, x2) + +inst_221: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x83fe; + valaddr_reg:x15; val_offset:396*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 396*FLEN/8, x16, x1, x2) + +inst_222: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x3ff; + valaddr_reg:x15; val_offset:398*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 398*FLEN/8, x16, x1, x2) + +inst_223: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x83ff; + valaddr_reg:x15; val_offset:400*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 400*FLEN/8, x16, x1, x2) + +inst_224: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x400; + valaddr_reg:x15; val_offset:402*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 402*FLEN/8, x16, x1, x2) + +inst_225: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8400; + valaddr_reg:x15; val_offset:404*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 404*FLEN/8, x16, x1, x2) + +inst_226: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x401; + valaddr_reg:x15; val_offset:406*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 406*FLEN/8, x16, x1, x2) + +inst_227: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8455; + valaddr_reg:x15; val_offset:408*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 408*FLEN/8, x16, x1, x2) + +inst_228: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x7bff; + valaddr_reg:x15; val_offset:410*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 410*FLEN/8, x16, x1, x2) + +inst_229: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xfbff; + valaddr_reg:x15; val_offset:412*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 412*FLEN/8, x16, x1, x2) + +inst_230: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x7c00; + valaddr_reg:x15; val_offset:414*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 414*FLEN/8, x16, x1, x2) + +inst_231: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xfc00; + valaddr_reg:x15; val_offset:416*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 416*FLEN/8, x16, x1, x2) + +inst_232: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x7e00; + valaddr_reg:x15; val_offset:418*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 418*FLEN/8, x16, x1, x2) + +inst_233: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xfe00; + valaddr_reg:x15; val_offset:420*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 420*FLEN/8, x16, x1, x2) + +inst_234: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x7e01; + valaddr_reg:x15; val_offset:422*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 422*FLEN/8, x16, x1, x2) + +inst_235: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xfe55; + valaddr_reg:x15; val_offset:424*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 424*FLEN/8, x16, x1, x2) + +inst_236: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x7c01; + valaddr_reg:x15; val_offset:426*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 426*FLEN/8, x16, x1, x2) + +inst_237: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xfd55; + valaddr_reg:x15; val_offset:428*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 428*FLEN/8, x16, x1, x2) + +inst_238: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x3c00; + valaddr_reg:x15; val_offset:430*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 430*FLEN/8, x16, x1, x2) + +inst_239: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xbc00; + valaddr_reg:x15; val_offset:432*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 432*FLEN/8, x16, x1, x2) + +inst_240: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x0; + valaddr_reg:x15; val_offset:434*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 434*FLEN/8, x16, x1, x2) + +inst_241: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x8000; + valaddr_reg:x15; val_offset:436*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 436*FLEN/8, x16, x1, x2) + +inst_242: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x1; + valaddr_reg:x15; val_offset:438*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 438*FLEN/8, x16, x1, x2) + +inst_243: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x8001; + valaddr_reg:x15; val_offset:440*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 440*FLEN/8, x16, x1, x2) + +inst_244: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x2; + valaddr_reg:x15; val_offset:442*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 442*FLEN/8, x16, x1, x2) + +inst_245: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x83fe; + valaddr_reg:x15; val_offset:444*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 444*FLEN/8, x16, x1, x2) + +inst_246: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x3ff; + valaddr_reg:x15; val_offset:446*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 446*FLEN/8, x16, x1, x2) + +inst_247: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x83ff; + valaddr_reg:x15; val_offset:448*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 448*FLEN/8, x16, x1, x2) + +inst_248: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x400; + valaddr_reg:x15; val_offset:450*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 450*FLEN/8, x16, x1, x2) + +inst_249: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x8400; + valaddr_reg:x15; val_offset:452*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 452*FLEN/8, x16, x1, x2) + +inst_250: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x401; + valaddr_reg:x15; val_offset:454*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 454*FLEN/8, x16, x1, x2) + +inst_251: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x8455; + valaddr_reg:x15; val_offset:456*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 456*FLEN/8, x16, x1, x2) + +inst_252: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x7bff; + valaddr_reg:x15; val_offset:458*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 458*FLEN/8, x16, x1, x2) + +inst_253: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xfbff; + valaddr_reg:x15; val_offset:460*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 460*FLEN/8, x16, x1, x2) + +inst_254: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x7c00; + valaddr_reg:x15; val_offset:462*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 462*FLEN/8, x16, x1, x2) + +inst_255: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xfc00; + valaddr_reg:x15; val_offset:464*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 464*FLEN/8, x16, x1, x2) + +inst_256: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x7e00; + valaddr_reg:x15; val_offset:466*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 466*FLEN/8, x16, x1, x2) + +inst_257: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xfe00; + valaddr_reg:x15; val_offset:468*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 468*FLEN/8, x16, x1, x2) + +inst_258: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x7e01; + valaddr_reg:x15; val_offset:470*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 470*FLEN/8, x16, x1, x2) + +inst_259: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xfe55; + valaddr_reg:x15; val_offset:472*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 472*FLEN/8, x16, x1, x2) + +inst_260: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x7c01; + valaddr_reg:x15; val_offset:474*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 474*FLEN/8, x16, x1, x2) + +inst_261: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xfd55; + valaddr_reg:x15; val_offset:476*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 476*FLEN/8, x16, x1, x2) + +inst_262: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x3c00; + valaddr_reg:x15; val_offset:478*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 478*FLEN/8, x16, x1, x2) + +inst_263: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xbc00; + valaddr_reg:x15; val_offset:480*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 480*FLEN/8, x16, x1, x2) + +inst_264: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x0; + valaddr_reg:x15; val_offset:482*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 482*FLEN/8, x16, x1, x2) + +inst_265: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x8000; + valaddr_reg:x15; val_offset:484*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 484*FLEN/8, x16, x1, x2) + +inst_266: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x1; + valaddr_reg:x15; val_offset:486*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 486*FLEN/8, x16, x1, x2) + +inst_267: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x8001; + valaddr_reg:x15; val_offset:488*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 488*FLEN/8, x16, x1, x2) + +inst_268: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x2; + valaddr_reg:x15; val_offset:490*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 490*FLEN/8, x16, x1, x2) + +inst_269: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x83fe; + valaddr_reg:x15; val_offset:492*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 492*FLEN/8, x16, x1, x2) + +inst_270: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x3ff; + valaddr_reg:x15; val_offset:494*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 494*FLEN/8, x16, x1, x2) + +inst_271: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x83ff; + valaddr_reg:x15; val_offset:496*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 496*FLEN/8, x16, x1, x2) + +inst_272: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x400; + valaddr_reg:x15; val_offset:498*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 498*FLEN/8, x16, x1, x2) + +inst_273: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x8400; + valaddr_reg:x15; val_offset:500*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 500*FLEN/8, x16, x1, x2) + +inst_274: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x401; + valaddr_reg:x15; val_offset:502*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 502*FLEN/8, x16, x1, x2) + +inst_275: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x8455; + valaddr_reg:x15; val_offset:504*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 504*FLEN/8, x16, x1, x2) + +inst_276: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x7bff; + valaddr_reg:x15; val_offset:506*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 506*FLEN/8, x16, x1, x2) + +inst_277: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xfbff; + valaddr_reg:x15; val_offset:508*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 508*FLEN/8, x16, x1, x2) + +inst_278: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x7c00; + valaddr_reg:x15; val_offset:510*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 510*FLEN/8, x16, x1, x2) + +inst_279: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xfc00; + valaddr_reg:x15; val_offset:512*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 512*FLEN/8, x16, x1, x2) + +inst_280: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x7e00; + valaddr_reg:x15; val_offset:514*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 514*FLEN/8, x16, x1, x2) + +inst_281: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xfe00; + valaddr_reg:x15; val_offset:516*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 516*FLEN/8, x16, x1, x2) + +inst_282: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x7e01; + valaddr_reg:x15; val_offset:518*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 518*FLEN/8, x16, x1, x2) + +inst_283: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xfe55; + valaddr_reg:x15; val_offset:520*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 520*FLEN/8, x16, x1, x2) + +inst_284: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x7c01; + valaddr_reg:x15; val_offset:522*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 522*FLEN/8, x16, x1, x2) + +inst_285: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xfd55; + valaddr_reg:x15; val_offset:524*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 524*FLEN/8, x16, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_2) + +inst_286: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x3c00; + valaddr_reg:x15; val_offset:526*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 526*FLEN/8, x16, x1, x2) + +inst_287: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xbc00; + valaddr_reg:x15; val_offset:528*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 528*FLEN/8, x16, x1, x2) + +inst_288: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x0; + valaddr_reg:x15; val_offset:530*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 530*FLEN/8, x16, x1, x2) + +inst_289: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8000; + valaddr_reg:x15; val_offset:532*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 532*FLEN/8, x16, x1, x2) + +inst_290: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x1; + valaddr_reg:x15; val_offset:534*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 534*FLEN/8, x16, x1, x2) + +inst_291: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8001; + valaddr_reg:x15; val_offset:536*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 536*FLEN/8, x16, x1, x2) + +inst_292: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x2; + valaddr_reg:x15; val_offset:538*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 538*FLEN/8, x16, x1, x2) + +inst_293: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x83fe; + valaddr_reg:x15; val_offset:540*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 540*FLEN/8, x16, x1, x2) + +inst_294: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x3ff; + valaddr_reg:x15; val_offset:542*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 542*FLEN/8, x16, x1, x2) + +inst_295: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x83ff; + valaddr_reg:x15; val_offset:544*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 544*FLEN/8, x16, x1, x2) + +inst_296: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x400; + valaddr_reg:x15; val_offset:546*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 546*FLEN/8, x16, x1, x2) + +inst_297: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8400; + valaddr_reg:x15; val_offset:548*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 548*FLEN/8, x16, x1, x2) + +inst_298: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x401; + valaddr_reg:x15; val_offset:550*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 550*FLEN/8, x16, x1, x2) + +inst_299: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8455; + valaddr_reg:x15; val_offset:552*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 552*FLEN/8, x16, x1, x2) + +inst_300: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7bff; + valaddr_reg:x15; val_offset:554*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 554*FLEN/8, x16, x1, x2) + +inst_301: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xfbff; + valaddr_reg:x15; val_offset:556*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 556*FLEN/8, x16, x1, x2) + +inst_302: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7c00; + valaddr_reg:x15; val_offset:558*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 558*FLEN/8, x16, x1, x2) + +inst_303: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xfc00; + valaddr_reg:x15; val_offset:560*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 560*FLEN/8, x16, x1, x2) + +inst_304: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7e00; + valaddr_reg:x15; val_offset:562*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 562*FLEN/8, x16, x1, x2) + +inst_305: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xfe00; + valaddr_reg:x15; val_offset:564*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 564*FLEN/8, x16, x1, x2) + +inst_306: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7e01; + valaddr_reg:x15; val_offset:566*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 566*FLEN/8, x16, x1, x2) + +inst_307: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xfe55; + valaddr_reg:x15; val_offset:568*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 568*FLEN/8, x16, x1, x2) + +inst_308: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7c01; + valaddr_reg:x15; val_offset:570*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 570*FLEN/8, x16, x1, x2) + +inst_309: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xfd55; + valaddr_reg:x15; val_offset:572*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 572*FLEN/8, x16, x1, x2) + +inst_310: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x3c00; + valaddr_reg:x15; val_offset:574*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 574*FLEN/8, x16, x1, x2) + +inst_311: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xbc00; + valaddr_reg:x15; val_offset:576*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 576*FLEN/8, x16, x1, x2) + +inst_312: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x0; + valaddr_reg:x15; val_offset:578*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 578*FLEN/8, x16, x1, x2) + +inst_313: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8000; + valaddr_reg:x15; val_offset:580*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 580*FLEN/8, x16, x1, x2) + +inst_314: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x1; + valaddr_reg:x15; val_offset:582*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 582*FLEN/8, x16, x1, x2) + +inst_315: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8001; + valaddr_reg:x15; val_offset:584*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 584*FLEN/8, x16, x1, x2) + +inst_316: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x2; + valaddr_reg:x15; val_offset:586*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 586*FLEN/8, x16, x1, x2) + +inst_317: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x83fe; + valaddr_reg:x15; val_offset:588*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 588*FLEN/8, x16, x1, x2) + +inst_318: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x3ff; + valaddr_reg:x15; val_offset:590*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 590*FLEN/8, x16, x1, x2) + +inst_319: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x83ff; + valaddr_reg:x15; val_offset:592*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 592*FLEN/8, x16, x1, x2) + +inst_320: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x400; + valaddr_reg:x15; val_offset:594*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 594*FLEN/8, x16, x1, x2) + +inst_321: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8400; + valaddr_reg:x15; val_offset:596*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 596*FLEN/8, x16, x1, x2) + +inst_322: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x401; + valaddr_reg:x15; val_offset:598*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 598*FLEN/8, x16, x1, x2) + +inst_323: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8455; + valaddr_reg:x15; val_offset:600*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 600*FLEN/8, x16, x1, x2) + +inst_324: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7bff; + valaddr_reg:x15; val_offset:602*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 602*FLEN/8, x16, x1, x2) + +inst_325: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfbff; + valaddr_reg:x15; val_offset:604*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 604*FLEN/8, x16, x1, x2) + +inst_326: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7c00; + valaddr_reg:x15; val_offset:606*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 606*FLEN/8, x16, x1, x2) + +inst_327: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfc00; + valaddr_reg:x15; val_offset:608*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 608*FLEN/8, x16, x1, x2) + +inst_328: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7e00; + valaddr_reg:x15; val_offset:610*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 610*FLEN/8, x16, x1, x2) + +inst_329: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfe00; + valaddr_reg:x15; val_offset:612*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 612*FLEN/8, x16, x1, x2) + +inst_330: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7e01; + valaddr_reg:x15; val_offset:614*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 614*FLEN/8, x16, x1, x2) + +inst_331: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfe55; + valaddr_reg:x15; val_offset:616*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 616*FLEN/8, x16, x1, x2) + +inst_332: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7c01; + valaddr_reg:x15; val_offset:618*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 618*FLEN/8, x16, x1, x2) + +inst_333: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfd55; + valaddr_reg:x15; val_offset:620*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 620*FLEN/8, x16, x1, x2) + +inst_334: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x3c00; + valaddr_reg:x15; val_offset:622*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 622*FLEN/8, x16, x1, x2) + +inst_335: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xbc00; + valaddr_reg:x15; val_offset:624*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 624*FLEN/8, x16, x1, x2) + +inst_336: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x0; + valaddr_reg:x15; val_offset:626*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 626*FLEN/8, x16, x1, x2) + +inst_337: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x8000; + valaddr_reg:x15; val_offset:628*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 628*FLEN/8, x16, x1, x2) + +inst_338: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x1; + valaddr_reg:x15; val_offset:630*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 630*FLEN/8, x16, x1, x2) + +inst_339: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x8001; + valaddr_reg:x15; val_offset:632*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 632*FLEN/8, x16, x1, x2) + +inst_340: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x2; + valaddr_reg:x15; val_offset:634*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 634*FLEN/8, x16, x1, x2) + +inst_341: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x83fe; + valaddr_reg:x15; val_offset:636*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 636*FLEN/8, x16, x1, x2) + +inst_342: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x3ff; + valaddr_reg:x15; val_offset:638*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 638*FLEN/8, x16, x1, x2) + +inst_343: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x83ff; + valaddr_reg:x15; val_offset:640*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 640*FLEN/8, x16, x1, x2) + +inst_344: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x400; + valaddr_reg:x15; val_offset:642*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 642*FLEN/8, x16, x1, x2) + +inst_345: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x8400; + valaddr_reg:x15; val_offset:644*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 644*FLEN/8, x16, x1, x2) + +inst_346: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x401; + valaddr_reg:x15; val_offset:646*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 646*FLEN/8, x16, x1, x2) + +inst_347: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x8455; + valaddr_reg:x15; val_offset:648*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 648*FLEN/8, x16, x1, x2) + +inst_348: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x7bff; + valaddr_reg:x15; val_offset:650*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 650*FLEN/8, x16, x1, x2) + +inst_349: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xfbff; + valaddr_reg:x15; val_offset:652*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 652*FLEN/8, x16, x1, x2) + +inst_350: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x7c00; + valaddr_reg:x15; val_offset:654*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 654*FLEN/8, x16, x1, x2) + +inst_351: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xfc00; + valaddr_reg:x15; val_offset:656*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 656*FLEN/8, x16, x1, x2) + +inst_352: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x7e00; + valaddr_reg:x15; val_offset:658*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 658*FLEN/8, x16, x1, x2) + +inst_353: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xfe00; + valaddr_reg:x15; val_offset:660*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 660*FLEN/8, x16, x1, x2) + +inst_354: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x7e01; + valaddr_reg:x15; val_offset:662*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 662*FLEN/8, x16, x1, x2) + +inst_355: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xfe55; + valaddr_reg:x15; val_offset:664*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 664*FLEN/8, x16, x1, x2) + +inst_356: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x7c01; + valaddr_reg:x15; val_offset:666*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 666*FLEN/8, x16, x1, x2) + +inst_357: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xfd55; + valaddr_reg:x15; val_offset:668*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 668*FLEN/8, x16, x1, x2) + +inst_358: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x3c00; + valaddr_reg:x15; val_offset:670*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 670*FLEN/8, x16, x1, x2) + +inst_359: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xbc00; + valaddr_reg:x15; val_offset:672*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 672*FLEN/8, x16, x1, x2) + +inst_360: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x0; + valaddr_reg:x15; val_offset:674*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 674*FLEN/8, x16, x1, x2) + +inst_361: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x8000; + valaddr_reg:x15; val_offset:676*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 676*FLEN/8, x16, x1, x2) + +inst_362: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x1; + valaddr_reg:x15; val_offset:678*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 678*FLEN/8, x16, x1, x2) + +inst_363: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x8001; + valaddr_reg:x15; val_offset:680*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 680*FLEN/8, x16, x1, x2) + +inst_364: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x2; + valaddr_reg:x15; val_offset:682*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 682*FLEN/8, x16, x1, x2) + +inst_365: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x83fe; + valaddr_reg:x15; val_offset:684*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 684*FLEN/8, x16, x1, x2) + +inst_366: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x3ff; + valaddr_reg:x15; val_offset:686*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 686*FLEN/8, x16, x1, x2) + +inst_367: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x83ff; + valaddr_reg:x15; val_offset:688*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 688*FLEN/8, x16, x1, x2) + +inst_368: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x400; + valaddr_reg:x15; val_offset:690*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 690*FLEN/8, x16, x1, x2) + +inst_369: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x8400; + valaddr_reg:x15; val_offset:692*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 692*FLEN/8, x16, x1, x2) + +inst_370: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x401; + valaddr_reg:x15; val_offset:694*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 694*FLEN/8, x16, x1, x2) + +inst_371: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x8455; + valaddr_reg:x15; val_offset:696*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 696*FLEN/8, x16, x1, x2) + +inst_372: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x7bff; + valaddr_reg:x15; val_offset:698*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 698*FLEN/8, x16, x1, x2) + +inst_373: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xfbff; + valaddr_reg:x15; val_offset:700*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 700*FLEN/8, x16, x1, x2) + +inst_374: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x7c00; + valaddr_reg:x15; val_offset:702*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 702*FLEN/8, x16, x1, x2) + +inst_375: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xfc00; + valaddr_reg:x15; val_offset:704*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 704*FLEN/8, x16, x1, x2) + +inst_376: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x7e00; + valaddr_reg:x15; val_offset:706*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 706*FLEN/8, x16, x1, x2) + +inst_377: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xfe00; + valaddr_reg:x15; val_offset:708*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 708*FLEN/8, x16, x1, x2) + +inst_378: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x7e01; + valaddr_reg:x15; val_offset:710*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 710*FLEN/8, x16, x1, x2) + +inst_379: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xfe55; + valaddr_reg:x15; val_offset:712*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 712*FLEN/8, x16, x1, x2) + +inst_380: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x7c01; + valaddr_reg:x15; val_offset:714*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 714*FLEN/8, x16, x1, x2) + +inst_381: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xfd55; + valaddr_reg:x15; val_offset:716*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 716*FLEN/8, x16, x1, x2) + +inst_382: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x3c00; + valaddr_reg:x15; val_offset:718*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 718*FLEN/8, x16, x1, x2) + +inst_383: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xbc00; + valaddr_reg:x15; val_offset:720*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 720*FLEN/8, x16, x1, x2) + +inst_384: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x0; + valaddr_reg:x15; val_offset:722*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 722*FLEN/8, x16, x1, x2) + +inst_385: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x8000; + valaddr_reg:x15; val_offset:724*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 724*FLEN/8, x16, x1, x2) + +inst_386: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x1; + valaddr_reg:x15; val_offset:726*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 726*FLEN/8, x16, x1, x2) + +inst_387: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x8001; + valaddr_reg:x15; val_offset:728*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 728*FLEN/8, x16, x1, x2) + +inst_388: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x2; + valaddr_reg:x15; val_offset:730*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 730*FLEN/8, x16, x1, x2) + +inst_389: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x83fe; + valaddr_reg:x15; val_offset:732*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 732*FLEN/8, x16, x1, x2) + +inst_390: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x3ff; + valaddr_reg:x15; val_offset:734*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 734*FLEN/8, x16, x1, x2) + +inst_391: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x83ff; + valaddr_reg:x15; val_offset:736*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 736*FLEN/8, x16, x1, x2) + +inst_392: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x400; + valaddr_reg:x15; val_offset:738*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 738*FLEN/8, x16, x1, x2) + +inst_393: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x8400; + valaddr_reg:x15; val_offset:740*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 740*FLEN/8, x16, x1, x2) + +inst_394: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x401; + valaddr_reg:x15; val_offset:742*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 742*FLEN/8, x16, x1, x2) + +inst_395: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x8455; + valaddr_reg:x15; val_offset:744*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 744*FLEN/8, x16, x1, x2) + +inst_396: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x7bff; + valaddr_reg:x15; val_offset:746*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 746*FLEN/8, x16, x1, x2) + +inst_397: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xfbff; + valaddr_reg:x15; val_offset:748*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 748*FLEN/8, x16, x1, x2) + +inst_398: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x7c00; + valaddr_reg:x15; val_offset:750*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 750*FLEN/8, x16, x1, x2) + +inst_399: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xfc00; + valaddr_reg:x15; val_offset:752*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 752*FLEN/8, x16, x1, x2) + +inst_400: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x7e00; + valaddr_reg:x15; val_offset:754*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 754*FLEN/8, x16, x1, x2) + +inst_401: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xfe00; + valaddr_reg:x15; val_offset:756*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 756*FLEN/8, x16, x1, x2) + +inst_402: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x7e01; + valaddr_reg:x15; val_offset:758*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 758*FLEN/8, x16, x1, x2) + +inst_403: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xfe55; + valaddr_reg:x15; val_offset:760*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 760*FLEN/8, x16, x1, x2) + +inst_404: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x7c01; + valaddr_reg:x15; val_offset:762*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 762*FLEN/8, x16, x1, x2) + +inst_405: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xfd55; + valaddr_reg:x15; val_offset:764*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 764*FLEN/8, x16, x1, x2) + +inst_406: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x3c00; + valaddr_reg:x15; val_offset:766*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 766*FLEN/8, x16, x1, x2) + +inst_407: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xbc00; + valaddr_reg:x15; val_offset:768*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 768*FLEN/8, x16, x1, x2) + +inst_408: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x0; + valaddr_reg:x15; val_offset:770*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 770*FLEN/8, x16, x1, x2) + +inst_409: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x8000; + valaddr_reg:x15; val_offset:772*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 772*FLEN/8, x16, x1, x2) + +inst_410: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x1; + valaddr_reg:x15; val_offset:774*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 774*FLEN/8, x16, x1, x2) + +inst_411: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x8001; + valaddr_reg:x15; val_offset:776*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 776*FLEN/8, x16, x1, x2) + +inst_412: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x2; + valaddr_reg:x15; val_offset:778*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 778*FLEN/8, x16, x1, x2) + +inst_413: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x83fe; + valaddr_reg:x15; val_offset:780*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 780*FLEN/8, x16, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_3) + +inst_414: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x3ff; + valaddr_reg:x15; val_offset:782*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 782*FLEN/8, x16, x1, x2) + +inst_415: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x83ff; + valaddr_reg:x15; val_offset:784*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 784*FLEN/8, x16, x1, x2) + +inst_416: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x400; + valaddr_reg:x15; val_offset:786*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 786*FLEN/8, x16, x1, x2) + +inst_417: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x8400; + valaddr_reg:x15; val_offset:788*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 788*FLEN/8, x16, x1, x2) + +inst_418: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x401; + valaddr_reg:x15; val_offset:790*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 790*FLEN/8, x16, x1, x2) + +inst_419: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x8455; + valaddr_reg:x15; val_offset:792*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 792*FLEN/8, x16, x1, x2) + +inst_420: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x7bff; + valaddr_reg:x15; val_offset:794*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 794*FLEN/8, x16, x1, x2) + +inst_421: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xfbff; + valaddr_reg:x15; val_offset:796*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 796*FLEN/8, x16, x1, x2) + +inst_422: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x7c00; + valaddr_reg:x15; val_offset:798*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 798*FLEN/8, x16, x1, x2) + +inst_423: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xfc00; + valaddr_reg:x15; val_offset:800*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 800*FLEN/8, x16, x1, x2) + +inst_424: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x7e00; + valaddr_reg:x15; val_offset:802*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 802*FLEN/8, x16, x1, x2) + +inst_425: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xfe00; + valaddr_reg:x15; val_offset:804*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 804*FLEN/8, x16, x1, x2) + +inst_426: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x7e01; + valaddr_reg:x15; val_offset:806*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 806*FLEN/8, x16, x1, x2) + +inst_427: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xfe55; + valaddr_reg:x15; val_offset:808*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 808*FLEN/8, x16, x1, x2) + +inst_428: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x7c01; + valaddr_reg:x15; val_offset:810*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 810*FLEN/8, x16, x1, x2) + +inst_429: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xfd55; + valaddr_reg:x15; val_offset:812*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 812*FLEN/8, x16, x1, x2) + +inst_430: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x3c00; + valaddr_reg:x15; val_offset:814*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 814*FLEN/8, x16, x1, x2) + +inst_431: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xbc00; + valaddr_reg:x15; val_offset:816*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 816*FLEN/8, x16, x1, x2) + +inst_432: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x0; + valaddr_reg:x15; val_offset:818*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 818*FLEN/8, x16, x1, x2) + +inst_433: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x8000; + valaddr_reg:x15; val_offset:820*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 820*FLEN/8, x16, x1, x2) + +inst_434: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x1; + valaddr_reg:x15; val_offset:822*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 822*FLEN/8, x16, x1, x2) + +inst_435: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x8001; + valaddr_reg:x15; val_offset:824*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 824*FLEN/8, x16, x1, x2) + +inst_436: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x2; + valaddr_reg:x15; val_offset:826*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 826*FLEN/8, x16, x1, x2) + +inst_437: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x83fe; + valaddr_reg:x15; val_offset:828*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 828*FLEN/8, x16, x1, x2) + +inst_438: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x3ff; + valaddr_reg:x15; val_offset:830*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 830*FLEN/8, x16, x1, x2) + +inst_439: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x83ff; + valaddr_reg:x15; val_offset:832*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 832*FLEN/8, x16, x1, x2) + +inst_440: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x400; + valaddr_reg:x15; val_offset:834*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 834*FLEN/8, x16, x1, x2) + +inst_441: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x8400; + valaddr_reg:x15; val_offset:836*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 836*FLEN/8, x16, x1, x2) + +inst_442: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x401; + valaddr_reg:x15; val_offset:838*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 838*FLEN/8, x16, x1, x2) + +inst_443: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x8455; + valaddr_reg:x15; val_offset:840*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 840*FLEN/8, x16, x1, x2) + +inst_444: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x7bff; + valaddr_reg:x15; val_offset:842*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 842*FLEN/8, x16, x1, x2) + +inst_445: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xfbff; + valaddr_reg:x15; val_offset:844*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 844*FLEN/8, x16, x1, x2) + +inst_446: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x7c00; + valaddr_reg:x15; val_offset:846*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 846*FLEN/8, x16, x1, x2) + +inst_447: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xfc00; + valaddr_reg:x15; val_offset:848*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 848*FLEN/8, x16, x1, x2) + +inst_448: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x7e00; + valaddr_reg:x15; val_offset:850*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 850*FLEN/8, x16, x1, x2) + +inst_449: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xfe00; + valaddr_reg:x15; val_offset:852*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 852*FLEN/8, x16, x1, x2) + +inst_450: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x7e01; + valaddr_reg:x15; val_offset:854*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 854*FLEN/8, x16, x1, x2) + +inst_451: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xfe55; + valaddr_reg:x15; val_offset:856*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 856*FLEN/8, x16, x1, x2) + +inst_452: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x7c01; + valaddr_reg:x15; val_offset:858*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 858*FLEN/8, x16, x1, x2) + +inst_453: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xfd55; + valaddr_reg:x15; val_offset:860*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 860*FLEN/8, x16, x1, x2) + +inst_454: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x3c00; + valaddr_reg:x15; val_offset:862*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 862*FLEN/8, x16, x1, x2) + +inst_455: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xbc00; + valaddr_reg:x15; val_offset:864*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 864*FLEN/8, x16, x1, x2) + +inst_456: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x0; + valaddr_reg:x15; val_offset:866*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 866*FLEN/8, x16, x1, x2) + +inst_457: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x8000; + valaddr_reg:x15; val_offset:868*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 868*FLEN/8, x16, x1, x2) + +inst_458: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x1; + valaddr_reg:x15; val_offset:870*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 870*FLEN/8, x16, x1, x2) + +inst_459: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x8001; + valaddr_reg:x15; val_offset:872*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 872*FLEN/8, x16, x1, x2) + +inst_460: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x2; + valaddr_reg:x15; val_offset:874*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 874*FLEN/8, x16, x1, x2) + +inst_461: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x83fe; + valaddr_reg:x15; val_offset:876*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 876*FLEN/8, x16, x1, x2) + +inst_462: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x3ff; + valaddr_reg:x15; val_offset:878*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 878*FLEN/8, x16, x1, x2) + +inst_463: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x83ff; + valaddr_reg:x15; val_offset:880*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 880*FLEN/8, x16, x1, x2) + +inst_464: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x400; + valaddr_reg:x15; val_offset:882*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 882*FLEN/8, x16, x1, x2) + +inst_465: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x8400; + valaddr_reg:x15; val_offset:884*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 884*FLEN/8, x16, x1, x2) + +inst_466: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x401; + valaddr_reg:x15; val_offset:886*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 886*FLEN/8, x16, x1, x2) + +inst_467: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x8455; + valaddr_reg:x15; val_offset:888*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 888*FLEN/8, x16, x1, x2) + +inst_468: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x7bff; + valaddr_reg:x15; val_offset:890*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 890*FLEN/8, x16, x1, x2) + +inst_469: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xfbff; + valaddr_reg:x15; val_offset:892*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 892*FLEN/8, x16, x1, x2) + +inst_470: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x7c00; + valaddr_reg:x15; val_offset:894*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 894*FLEN/8, x16, x1, x2) + +inst_471: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xfc00; + valaddr_reg:x15; val_offset:896*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 896*FLEN/8, x16, x1, x2) + +inst_472: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x7e00; + valaddr_reg:x15; val_offset:898*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 898*FLEN/8, x16, x1, x2) + +inst_473: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xfe00; + valaddr_reg:x15; val_offset:900*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 900*FLEN/8, x16, x1, x2) + +inst_474: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x7e01; + valaddr_reg:x15; val_offset:902*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 902*FLEN/8, x16, x1, x2) + +inst_475: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xfe55; + valaddr_reg:x15; val_offset:904*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 904*FLEN/8, x16, x1, x2) + +inst_476: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x7c01; + valaddr_reg:x15; val_offset:906*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 906*FLEN/8, x16, x1, x2) + +inst_477: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xfd55; + valaddr_reg:x15; val_offset:908*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 908*FLEN/8, x16, x1, x2) + +inst_478: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x3c00; + valaddr_reg:x15; val_offset:910*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 910*FLEN/8, x16, x1, x2) + +inst_479: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xbc00; + valaddr_reg:x15; val_offset:912*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 912*FLEN/8, x16, x1, x2) + +inst_480: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x0; + valaddr_reg:x15; val_offset:914*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 914*FLEN/8, x16, x1, x2) + +inst_481: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x8000; + valaddr_reg:x15; val_offset:916*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 916*FLEN/8, x16, x1, x2) + +inst_482: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x1; + valaddr_reg:x15; val_offset:918*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 918*FLEN/8, x16, x1, x2) + +inst_483: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x8001; + valaddr_reg:x15; val_offset:920*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 920*FLEN/8, x16, x1, x2) + +inst_484: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x2; + valaddr_reg:x15; val_offset:922*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 922*FLEN/8, x16, x1, x2) + +inst_485: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x83fe; + valaddr_reg:x15; val_offset:924*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 924*FLEN/8, x16, x1, x2) + +inst_486: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x3ff; + valaddr_reg:x15; val_offset:926*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 926*FLEN/8, x16, x1, x2) + +inst_487: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x83ff; + valaddr_reg:x15; val_offset:928*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 928*FLEN/8, x16, x1, x2) + +inst_488: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x400; + valaddr_reg:x15; val_offset:930*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 930*FLEN/8, x16, x1, x2) + +inst_489: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x8400; + valaddr_reg:x15; val_offset:932*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 932*FLEN/8, x16, x1, x2) + +inst_490: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x401; + valaddr_reg:x15; val_offset:934*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 934*FLEN/8, x16, x1, x2) + +inst_491: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x8455; + valaddr_reg:x15; val_offset:936*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 936*FLEN/8, x16, x1, x2) + +inst_492: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x7bff; + valaddr_reg:x15; val_offset:938*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 938*FLEN/8, x16, x1, x2) + +inst_493: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xfbff; + valaddr_reg:x15; val_offset:940*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 940*FLEN/8, x16, x1, x2) + +inst_494: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x7c00; + valaddr_reg:x15; val_offset:942*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 942*FLEN/8, x16, x1, x2) + +inst_495: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xfc00; + valaddr_reg:x15; val_offset:944*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 944*FLEN/8, x16, x1, x2) + +inst_496: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x7e00; + valaddr_reg:x15; val_offset:946*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 946*FLEN/8, x16, x1, x2) + +inst_497: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xfe00; + valaddr_reg:x15; val_offset:948*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 948*FLEN/8, x16, x1, x2) + +inst_498: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x7e01; + valaddr_reg:x15; val_offset:950*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 950*FLEN/8, x16, x1, x2) + +inst_499: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xfe55; + valaddr_reg:x15; val_offset:952*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 952*FLEN/8, x16, x1, x2) + +inst_500: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x7c01; + valaddr_reg:x15; val_offset:954*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 954*FLEN/8, x16, x1, x2) + +inst_501: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xfd55; + valaddr_reg:x15; val_offset:956*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 956*FLEN/8, x16, x1, x2) + +inst_502: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x3c00; + valaddr_reg:x15; val_offset:958*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 958*FLEN/8, x16, x1, x2) + +inst_503: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xbc00; + valaddr_reg:x15; val_offset:960*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 960*FLEN/8, x16, x1, x2) + +inst_504: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x0; + valaddr_reg:x15; val_offset:962*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 962*FLEN/8, x16, x1, x2) + +inst_505: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x8000; + valaddr_reg:x15; val_offset:964*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 964*FLEN/8, x16, x1, x2) + +inst_506: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x1; + valaddr_reg:x15; val_offset:966*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 966*FLEN/8, x16, x1, x2) + +inst_507: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x8001; + valaddr_reg:x15; val_offset:968*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 968*FLEN/8, x16, x1, x2) + +inst_508: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x2; + valaddr_reg:x15; val_offset:970*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 970*FLEN/8, x16, x1, x2) + +inst_509: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x83fe; + valaddr_reg:x15; val_offset:972*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 972*FLEN/8, x16, x1, x2) + +inst_510: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x3ff; + valaddr_reg:x15; val_offset:974*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 974*FLEN/8, x16, x1, x2) + +inst_511: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x83ff; + valaddr_reg:x15; val_offset:976*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 976*FLEN/8, x16, x1, x2) + +inst_512: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x400; + valaddr_reg:x15; val_offset:978*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 978*FLEN/8, x16, x1, x2) + +inst_513: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x8400; + valaddr_reg:x15; val_offset:980*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 980*FLEN/8, x16, x1, x2) + +inst_514: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x401; + valaddr_reg:x15; val_offset:982*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 982*FLEN/8, x16, x1, x2) + +inst_515: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x8455; + valaddr_reg:x15; val_offset:984*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 984*FLEN/8, x16, x1, x2) + +inst_516: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x7bff; + valaddr_reg:x15; val_offset:986*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 986*FLEN/8, x16, x1, x2) + +inst_517: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xfbff; + valaddr_reg:x15; val_offset:988*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 988*FLEN/8, x16, x1, x2) + +inst_518: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x7c00; + valaddr_reg:x15; val_offset:990*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 990*FLEN/8, x16, x1, x2) + +inst_519: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xfc00; + valaddr_reg:x15; val_offset:992*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 992*FLEN/8, x16, x1, x2) + +inst_520: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x7e00; + valaddr_reg:x15; val_offset:994*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 994*FLEN/8, x16, x1, x2) + +inst_521: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xfe00; + valaddr_reg:x15; val_offset:996*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 996*FLEN/8, x16, x1, x2) + +inst_522: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x7e01; + valaddr_reg:x15; val_offset:998*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 998*FLEN/8, x16, x1, x2) + +inst_523: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xfe55; + valaddr_reg:x15; val_offset:1000*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 1000*FLEN/8, x16, x1, x2) + +inst_524: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x7c01; + valaddr_reg:x15; val_offset:1002*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 1002*FLEN/8, x16, x1, x2) + +inst_525: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xfd55; + valaddr_reg:x15; val_offset:1004*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 1004*FLEN/8, x16, x1, x2) + +inst_526: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x3c00; + valaddr_reg:x15; val_offset:1006*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 1006*FLEN/8, x16, x1, x2) + +inst_527: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xbc00; + valaddr_reg:x15; val_offset:1008*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 1008*FLEN/8, x16, x1, x2) + +inst_528: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x0; + valaddr_reg:x15; val_offset:1010*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 1010*FLEN/8, x16, x1, x2) + +inst_529: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x8000; + valaddr_reg:x15; val_offset:1012*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 1012*FLEN/8, x16, x1, x2) + +inst_530: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x1; + valaddr_reg:x15; val_offset:1014*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 1014*FLEN/8, x16, x1, x2) + +inst_531: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x8001; + valaddr_reg:x15; val_offset:1016*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 1016*FLEN/8, x16, x1, x2) + +inst_532: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2; + valaddr_reg:x15; val_offset:1018*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 1018*FLEN/8, x16, x1, x2) + +inst_533: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x83fe; + valaddr_reg:x15; val_offset:1020*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 1020*FLEN/8, x16, x1, x2) + +inst_534: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3ff; + valaddr_reg:x15; val_offset:1022*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 1022*FLEN/8, x16, x1, x2) + +inst_535: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x83ff; + valaddr_reg:x15; val_offset:1024*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 1024*FLEN/8, x16, x1, x2) + +inst_536: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x400; + valaddr_reg:x15; val_offset:1026*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 1026*FLEN/8, x16, x1, x2) + +inst_537: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x8400; + valaddr_reg:x15; val_offset:1028*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 1028*FLEN/8, x16, x1, x2) + +inst_538: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x401; + valaddr_reg:x15; val_offset:1030*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 1030*FLEN/8, x16, x1, x2) + +inst_539: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x8455; + valaddr_reg:x15; val_offset:1032*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 1032*FLEN/8, x16, x1, x2) + +inst_540: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7bff; + valaddr_reg:x15; val_offset:1034*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 1034*FLEN/8, x16, x1, x2) + +inst_541: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xfbff; + valaddr_reg:x15; val_offset:1036*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 1036*FLEN/8, x16, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_4) + +inst_542: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7c00; + valaddr_reg:x15; val_offset:1038*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 1038*FLEN/8, x16, x1, x2) + +inst_543: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xfc00; + valaddr_reg:x15; val_offset:1040*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 1040*FLEN/8, x16, x1, x2) + +inst_544: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7e00; + valaddr_reg:x15; val_offset:1042*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 1042*FLEN/8, x16, x1, x2) + +inst_545: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xfe00; + valaddr_reg:x15; val_offset:1044*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 1044*FLEN/8, x16, x1, x2) + +inst_546: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7e01; + valaddr_reg:x15; val_offset:1046*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 1046*FLEN/8, x16, x1, x2) + +inst_547: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xfe55; + valaddr_reg:x15; val_offset:1048*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 1048*FLEN/8, x16, x1, x2) + +inst_548: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7c01; + valaddr_reg:x15; val_offset:1050*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 1050*FLEN/8, x16, x1, x2) + +inst_549: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xfd55; + valaddr_reg:x15; val_offset:1052*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 1052*FLEN/8, x16, x1, x2) + +inst_550: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3c00; + valaddr_reg:x15; val_offset:1054*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 1054*FLEN/8, x16, x1, x2) + +inst_551: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xbc00; + valaddr_reg:x15; val_offset:1056*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 1056*FLEN/8, x16, x1, x2) + +inst_552: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x0; + valaddr_reg:x15; val_offset:1058*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 1058*FLEN/8, x16, x1, x2) + +inst_553: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x8000; + valaddr_reg:x15; val_offset:1060*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 1060*FLEN/8, x16, x1, x2) + +inst_554: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x1; + valaddr_reg:x15; val_offset:1062*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 1062*FLEN/8, x16, x1, x2) + +inst_555: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x8001; + valaddr_reg:x15; val_offset:1064*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 1064*FLEN/8, x16, x1, x2) + +inst_556: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x2; + valaddr_reg:x15; val_offset:1066*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 1066*FLEN/8, x16, x1, x2) + +inst_557: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x83fe; + valaddr_reg:x15; val_offset:1068*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 1068*FLEN/8, x16, x1, x2) + +inst_558: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x3ff; + valaddr_reg:x15; val_offset:1070*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 1070*FLEN/8, x16, x1, x2) + +inst_559: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x83ff; + valaddr_reg:x15; val_offset:1072*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 1072*FLEN/8, x16, x1, x2) + +inst_560: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x400; + valaddr_reg:x15; val_offset:1074*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 1074*FLEN/8, x16, x1, x2) + +inst_561: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x8400; + valaddr_reg:x15; val_offset:1076*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 1076*FLEN/8, x16, x1, x2) + +inst_562: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x401; + valaddr_reg:x15; val_offset:1078*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 1078*FLEN/8, x16, x1, x2) + +inst_563: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x8455; + valaddr_reg:x15; val_offset:1080*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 1080*FLEN/8, x16, x1, x2) + +inst_564: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x7bff; + valaddr_reg:x15; val_offset:1082*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 1082*FLEN/8, x16, x1, x2) + +inst_565: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xfbff; + valaddr_reg:x15; val_offset:1084*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 1084*FLEN/8, x16, x1, x2) + +inst_566: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x7c00; + valaddr_reg:x15; val_offset:1086*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 1086*FLEN/8, x16, x1, x2) + +inst_567: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xfc00; + valaddr_reg:x15; val_offset:1088*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 1088*FLEN/8, x16, x1, x2) + +inst_568: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x7e00; + valaddr_reg:x15; val_offset:1090*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 1090*FLEN/8, x16, x1, x2) + +inst_569: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xfe00; + valaddr_reg:x15; val_offset:1092*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 1092*FLEN/8, x16, x1, x2) + +inst_570: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x7e01; + valaddr_reg:x15; val_offset:1094*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 1094*FLEN/8, x16, x1, x2) + +inst_571: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xfe55; + valaddr_reg:x15; val_offset:1096*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 1096*FLEN/8, x16, x1, x2) + +inst_572: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x7c01; + valaddr_reg:x15; val_offset:1098*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 1098*FLEN/8, x16, x1, x2) + +inst_573: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xfd55; + valaddr_reg:x15; val_offset:1100*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 1100*FLEN/8, x16, x1, x2) + +inst_574: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x3c00; + valaddr_reg:x15; val_offset:1102*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 1102*FLEN/8, x16, x1, x2) + +inst_575: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbc00; + valaddr_reg:x15; val_offset:1104*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 1104*FLEN/8, x16, x1, x2) + +inst_576: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x1; + valaddr_reg:x15; val_offset:1106*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 1106*FLEN/8, x16, x1, x2) + +inst_577: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x2; + valaddr_reg:x15; val_offset:1108*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 1108*FLEN/8, x16, x1, x2) + +inst_578: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x8455; + valaddr_reg:x15; val_offset:1110*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 1110*FLEN/8, x16, x1, x2) + +inst_579: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x7e00; + valaddr_reg:x15; val_offset:1112*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 1112*FLEN/8, x16, x1, x2) + +inst_580: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjn.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xfe55; + valaddr_reg:x15; val_offset:1114*FLEN/8; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP_NRM(fsgnjn.h, x31, x30, x29, 0, 0, x15, 1114*FLEN/8, x16, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(1023,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(1024,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(1025,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31743,32,FLEN) +test_dataset_1: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31744,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32256,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32257,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31745,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(15360,32,FLEN) +test_dataset_2: +NAN_BOXED(0,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(33790,16,FLEN) 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+NAN_BOXED(1,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(65109,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x4_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x4_1: + .fill 30*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x10_0: + .fill 30*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_0: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_2: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_3: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_4: + .fill 78*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fsgnjx_b1-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fsgnjx_b1-01.S new file mode 100644 index 000000000..a7ba3fc28 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fsgnjx_b1-01.S @@ -0,0 +1,5934 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 05:27:02 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fsgnjx.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fsgnjx.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fsgnjx_b1 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fsgnjx_b1) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x21,test_dataset_0) +RVTEST_SIGBASE(x3,signature_x3_1) + +inst_0: +// rs1 == rs2 == rd, rs1==x26, rs2==x26, rd==x26,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x26; op2:x26; dest:x26; op1val:0x0; op2val:0x0; + valaddr_reg:x21; val_offset:0*FLEN/8; fcsr: 0; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x26, x26, x26, 0, 0, x21, 0*FLEN/8, x23, x3, x10) + +inst_1: +// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==x24, rs2==x22, rd==x13,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x24; op2:x22; dest:x13; op1val:0x0; op2val:0x8000; + valaddr_reg:x21; val_offset:2*FLEN/8; fcsr: 0; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x13, x24, x22, 0, 0, x21, 2*FLEN/8, x23, x3, x10) + +inst_2: +// rs2 == rd != rs1, rs1==x22, rs2==x24, rd==x24,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x22; op2:x24; dest:x24; op1val:0x0; op2val:0x1; + valaddr_reg:x21; val_offset:4*FLEN/8; fcsr: 0; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x24, x22, x24, 0, 0, x21, 4*FLEN/8, x23, x3, x10) + +inst_3: +// rs1 == rs2 != rd, rs1==x27, rs2==x27, rd==x1,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x27; op2:x27; dest:x1; op1val:0x0; op2val:0x0; + valaddr_reg:x21; val_offset:6*FLEN/8; fcsr: 0; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x1, x27, x27, 0, 0, x21, 6*FLEN/8, x23, x3, x10) + +inst_4: +// rs1 == rd != rs2, rs1==x6, rs2==x17, rd==x6,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x6; op2:x17; dest:x6; op1val:0x0; op2val:0x2; + valaddr_reg:x21; val_offset:8*FLEN/8; fcsr: 0; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x6, x6, x17, 0, 0, x21, 8*FLEN/8, x23, x3, x10) + +inst_5: +// rs1==x13, rs2==x14, rd==x5,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x13; op2:x14; dest:x5; op1val:0x0; op2val:0x83fe; + valaddr_reg:x21; val_offset:10*FLEN/8; fcsr: 0; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x5, x13, x14, 0, 0, x21, 10*FLEN/8, x23, x3, x10) + +inst_6: +// rs1==x30, rs2==x8, rd==x28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x8; dest:x28; op1val:0x0; op2val:0x3ff; + valaddr_reg:x21; val_offset:12*FLEN/8; fcsr: 0; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x28, x30, x8, 0, 0, x21, 12*FLEN/8, x23, x3, x10) + +inst_7: +// rs1==x2, rs2==x9, rd==x16,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x2; op2:x9; dest:x16; op1val:0x0; op2val:0x83ff; + valaddr_reg:x21; val_offset:14*FLEN/8; fcsr: 0; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x16, x2, x9, 0, 0, x21, 14*FLEN/8, x23, x3, x10) + +inst_8: +// rs1==x17, rs2==x4, rd==x0,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x17; op2:x4; dest:x0; op1val:0x0; op2val:0x400; + valaddr_reg:x21; val_offset:16*FLEN/8; fcsr: 0; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x0, x17, x4, 0, 0, x21, 16*FLEN/8, x23, x3, x10) + +inst_9: +// rs1==x19, rs2==x28, rd==x7,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x19; op2:x28; dest:x7; op1val:0x0; op2val:0x8400; + valaddr_reg:x21; val_offset:18*FLEN/8; fcsr: 0; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x7, x19, x28, 0, 0, x21, 18*FLEN/8, x23, x3, x10) + +inst_10: +// rs1==x18, rs2==x13, rd==x17,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x18; op2:x13; dest:x17; op1val:0x0; op2val:0x401; + valaddr_reg:x21; val_offset:20*FLEN/8; fcsr: 0; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x17, x18, x13, 0, 0, x21, 20*FLEN/8, x23, x3, x10) + +inst_11: +// rs1==x15, rs2==x20, rd==x19,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x15; op2:x20; dest:x19; op1val:0x0; op2val:0x8455; + valaddr_reg:x21; val_offset:22*FLEN/8; fcsr: 0; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x19, x15, x20, 0, 0, x21, 22*FLEN/8, x23, x3, x10) + +inst_12: +// rs1==x28, rs2==x12, rd==x11,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x28; op2:x12; dest:x11; op1val:0x0; op2val:0x7bff; + valaddr_reg:x21; val_offset:24*FLEN/8; fcsr: 0; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x11, x28, x12, 0, 0, x21, 24*FLEN/8, x23, x3, x10) +RVTEST_VALBASEUPD(x6,test_dataset_1) + +inst_13: +// rs1==x0, rs2==x25, rd==x21,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x0; op2:x25; dest:x21; op1val:0x0; op2val:0xfbff; + valaddr_reg:x6; val_offset:0*FLEN/8; fcsr: 0; + correctval:??; testreg:x10 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x21, x0, x25, 0, 0, x6, 0*FLEN/8, x19, x3, x10) +RVTEST_SIGBASE(x13,signature_x13_0) + +inst_14: +// rs1==x7, rs2==x3, rd==x31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x7; op2:x3; dest:x31; op1val:0x0; op2val:0x7c00; + valaddr_reg:x6; val_offset:2*FLEN/8; fcsr: 0; + correctval:??; testreg:x17 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x7, x3, 0, 0, x6, 2*FLEN/8, x19, x13, x17) + +inst_15: +// rs1==x16, rs2==x7, rd==x10,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x16; op2:x7; dest:x10; op1val:0x0; op2val:0xfc00; + valaddr_reg:x6; val_offset:4*FLEN/8; fcsr: 0; + correctval:??; testreg:x17 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x10, x16, x7, 0, 0, x6, 4*FLEN/8, x19, x13, x17) + +inst_16: +// rs1==x4, rs2==x1, rd==x30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x4; op2:x1; dest:x30; op1val:0x0; op2val:0x7e00; + valaddr_reg:x6; val_offset:6*FLEN/8; fcsr: 0; + correctval:??; testreg:x17 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x30, x4, x1, 0, 0, x6, 6*FLEN/8, x19, x13, x17) + +inst_17: +// rs1==x21, rs2==x30, rd==x23,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x21; op2:x30; dest:x23; op1val:0x0; op2val:0xfe00; + valaddr_reg:x6; val_offset:8*FLEN/8; fcsr: 0; + correctval:??; testreg:x17 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x23, x21, x30, 0, 0, x6, 8*FLEN/8, x19, x13, x17) + +inst_18: +// rs1==x14, rs2==x2, rd==x9,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x14; op2:x2; dest:x9; op1val:0x0; op2val:0x7e01; + valaddr_reg:x6; val_offset:10*FLEN/8; fcsr: 0; + correctval:??; testreg:x17 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x9, x14, x2, 0, 0, x6, 10*FLEN/8, x19, x13, x17) + +inst_19: +// rs1==x12, rs2==x31, rd==x8,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x12; op2:x31; dest:x8; op1val:0x0; op2val:0xfe55; + valaddr_reg:x6; val_offset:12*FLEN/8; fcsr: 0; + correctval:??; testreg:x17 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x8, x12, x31, 0, 0, x6, 12*FLEN/8, x19, x13, x17) + +inst_20: +// rs1==x29, rs2==x16, rd==x20,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x29; op2:x16; dest:x20; op1val:0x0; op2val:0x7c01; + valaddr_reg:x6; val_offset:14*FLEN/8; fcsr: 0; + correctval:??; testreg:x17 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x20, x29, x16, 0, 0, x6, 14*FLEN/8, x19, x13, x17) + +inst_21: +// rs1==x3, rs2==x15, rd==x29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x3; op2:x15; dest:x29; op1val:0x0; op2val:0xfd55; + valaddr_reg:x6; val_offset:16*FLEN/8; fcsr: 0; + correctval:??; testreg:x17 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x29, x3, x15, 0, 0, x6, 16*FLEN/8, x19, x13, x17) + +inst_22: +// rs1==x9, rs2==x23, rd==x18,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x9; op2:x23; dest:x18; op1val:0x0; op2val:0x3c00; + valaddr_reg:x6; val_offset:18*FLEN/8; fcsr: 0; + correctval:??; testreg:x17 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x18, x9, x23, 0, 0, x6, 18*FLEN/8, x19, x13, x17) + +inst_23: +// rs1==x11, rs2==x5, rd==x4,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x11; op2:x5; dest:x4; op1val:0x0; op2val:0xbc00; + valaddr_reg:x6; val_offset:20*FLEN/8; fcsr: 0; + correctval:??; testreg:x17 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x4, x11, x5, 0, 0, x6, 20*FLEN/8, x19, x13, x17) + +inst_24: +// rs1==x31, rs2==x18, rd==x3,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x31; op2:x18; dest:x3; op1val:0x8000; op2val:0x0; + valaddr_reg:x6; val_offset:22*FLEN/8; fcsr: 0; + correctval:??; testreg:x17 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x3, x31, x18, 0, 0, x6, 22*FLEN/8, x19, x13, x17) + +inst_25: +// rs1==x1, rs2==x21, rd==x15,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x1; op2:x21; dest:x15; op1val:0x8000; op2val:0x8000; + valaddr_reg:x6; val_offset:24*FLEN/8; fcsr: 0; + correctval:??; testreg:x17 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x15, x1, x21, 0, 0, x6, 24*FLEN/8, x19, x13, x17) + +inst_26: +// rs1==x8, rs2==x11, rd==x22,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x8; op2:x11; dest:x22; op1val:0x8000; op2val:0x1; + valaddr_reg:x6; val_offset:26*FLEN/8; fcsr: 0; + correctval:??; testreg:x17 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x22, x8, x11, 0, 0, x6, 26*FLEN/8, x19, x13, x17) +RVTEST_VALBASEUPD(x4,test_dataset_2) + +inst_27: +// rs1==x5, rs2==x6, rd==x12,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x5; op2:x6; dest:x12; op1val:0x8000; op2val:0x8001; + valaddr_reg:x4; val_offset:0*FLEN/8; fcsr: 0; + correctval:??; testreg:x17 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x12, x5, x6, 0, 0, x4, 0*FLEN/8, x7, x13, x17) + +inst_28: +// rs1==x10, rs2==x0, rd==x27,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x10; op2:x0; dest:x27; op1val:0x8000; op2val:0x0; + valaddr_reg:x4; val_offset:2*FLEN/8; fcsr: 0; + correctval:??; testreg:x17 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x27, x10, x0, 0, 0, x4, 2*FLEN/8, x7, x13, x17) + +inst_29: +// rs1==x20, rs2==x19, rd==x14,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x20; op2:x19; dest:x14; op1val:0x8000; op2val:0x83fe; + valaddr_reg:x4; val_offset:4*FLEN/8; fcsr: 0; + correctval:??; testreg:x17 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x14, x20, x19, 0, 0, x4, 4*FLEN/8, x7, x13, x17) + +inst_30: +// rs1==x23, rs2==x29, rd==x25,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x23; op2:x29; dest:x25; op1val:0x8000; op2val:0x3ff; + valaddr_reg:x4; val_offset:6*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x25, x23, x29, 0, 0, x4, 6*FLEN/8, x7, x13, x3) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_31: +// rs1==x25, rs2==x10, rd==x2,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x25; op2:x10; dest:x2; op1val:0x8000; op2val:0x83ff; + valaddr_reg:x4; val_offset:8*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x2, x25, x10, 0, 0, x4, 8*FLEN/8, x7, x1, x3) + +inst_32: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x400; + valaddr_reg:x4; val_offset:10*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 10*FLEN/8, x7, x1, x3) + +inst_33: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8400; + valaddr_reg:x4; val_offset:12*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 12*FLEN/8, x7, x1, x3) + +inst_34: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x401; + valaddr_reg:x4; val_offset:14*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 14*FLEN/8, x7, x1, x3) + +inst_35: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8455; + valaddr_reg:x4; val_offset:16*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 16*FLEN/8, x7, x1, x3) + +inst_36: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x7bff; + valaddr_reg:x4; val_offset:18*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 18*FLEN/8, x7, x1, x3) + +inst_37: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xfbff; + valaddr_reg:x4; val_offset:20*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 20*FLEN/8, x7, x1, x3) + +inst_38: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x7c00; + valaddr_reg:x4; val_offset:22*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 22*FLEN/8, x7, x1, x3) + +inst_39: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xfc00; + valaddr_reg:x4; val_offset:24*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 24*FLEN/8, x7, x1, x3) + +inst_40: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x7e00; + valaddr_reg:x4; val_offset:26*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 26*FLEN/8, x7, x1, x3) + +inst_41: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xfe00; + valaddr_reg:x4; val_offset:28*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 28*FLEN/8, x7, x1, x3) + +inst_42: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x7e01; + valaddr_reg:x4; val_offset:30*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 30*FLEN/8, x7, x1, x3) + +inst_43: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xfe55; + valaddr_reg:x4; val_offset:32*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 32*FLEN/8, x7, x1, x3) + +inst_44: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x7c01; + valaddr_reg:x4; val_offset:34*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 34*FLEN/8, x7, x1, x3) + +inst_45: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xfd55; + valaddr_reg:x4; val_offset:36*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 36*FLEN/8, x7, x1, x3) + +inst_46: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x3c00; + valaddr_reg:x4; val_offset:38*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 38*FLEN/8, x7, x1, x3) + +inst_47: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xbc00; + valaddr_reg:x4; val_offset:40*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 40*FLEN/8, x7, x1, x3) + +inst_48: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x0; + valaddr_reg:x4; val_offset:42*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 42*FLEN/8, x7, x1, x3) + +inst_49: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x8000; + valaddr_reg:x4; val_offset:44*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 44*FLEN/8, x7, x1, x3) + +inst_50: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x1; + valaddr_reg:x4; val_offset:46*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 46*FLEN/8, x7, x1, x3) + +inst_51: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x8001; + valaddr_reg:x4; val_offset:48*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 48*FLEN/8, x7, x1, x3) + +inst_52: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x2; + valaddr_reg:x4; val_offset:50*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 50*FLEN/8, x7, x1, x3) + +inst_53: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x83fe; + valaddr_reg:x4; val_offset:52*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 52*FLEN/8, x7, x1, x3) + +inst_54: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x3ff; + valaddr_reg:x4; val_offset:54*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 54*FLEN/8, x7, x1, x3) + +inst_55: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x83ff; + valaddr_reg:x4; val_offset:56*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 56*FLEN/8, x7, x1, x3) + +inst_56: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x400; + valaddr_reg:x4; val_offset:58*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 58*FLEN/8, x7, x1, x3) + +inst_57: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x8400; + valaddr_reg:x4; val_offset:60*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 60*FLEN/8, x7, x1, x3) + +inst_58: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x401; + valaddr_reg:x4; val_offset:62*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 62*FLEN/8, x7, x1, x3) + +inst_59: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x8455; + valaddr_reg:x4; val_offset:64*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 64*FLEN/8, x7, x1, x3) + +inst_60: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7bff; + valaddr_reg:x4; val_offset:66*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 66*FLEN/8, x7, x1, x3) + +inst_61: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xfbff; + valaddr_reg:x4; val_offset:68*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 68*FLEN/8, x7, x1, x3) + +inst_62: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7c00; + valaddr_reg:x4; val_offset:70*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 70*FLEN/8, x7, x1, x3) + +inst_63: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xfc00; + valaddr_reg:x4; val_offset:72*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 72*FLEN/8, x7, x1, x3) + +inst_64: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7e00; + valaddr_reg:x4; val_offset:74*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 74*FLEN/8, x7, x1, x3) + +inst_65: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xfe00; + valaddr_reg:x4; val_offset:76*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 76*FLEN/8, x7, x1, x3) + +inst_66: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7e01; + valaddr_reg:x4; val_offset:78*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 78*FLEN/8, x7, x1, x3) + +inst_67: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xfe55; + valaddr_reg:x4; val_offset:80*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 80*FLEN/8, x7, x1, x3) + +inst_68: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7c01; + valaddr_reg:x4; val_offset:82*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 82*FLEN/8, x7, x1, x3) + +inst_69: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xfd55; + valaddr_reg:x4; val_offset:84*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 84*FLEN/8, x7, x1, x3) + +inst_70: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x3c00; + valaddr_reg:x4; val_offset:86*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 86*FLEN/8, x7, x1, x3) + +inst_71: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xbc00; + valaddr_reg:x4; val_offset:88*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 88*FLEN/8, x7, x1, x3) + +inst_72: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x0; + valaddr_reg:x4; val_offset:90*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 90*FLEN/8, x7, x1, x3) + +inst_73: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8000; + valaddr_reg:x4; val_offset:92*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 92*FLEN/8, x7, x1, x3) + +inst_74: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x1; + valaddr_reg:x4; val_offset:94*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 94*FLEN/8, x7, x1, x3) + +inst_75: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8001; + valaddr_reg:x4; val_offset:96*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 96*FLEN/8, x7, x1, x3) + +inst_76: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x2; + valaddr_reg:x4; val_offset:98*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 98*FLEN/8, x7, x1, x3) + +inst_77: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x83fe; + valaddr_reg:x4; val_offset:100*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 100*FLEN/8, x7, x1, x3) + +inst_78: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x3ff; + valaddr_reg:x4; val_offset:102*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 102*FLEN/8, x7, x1, x3) + +inst_79: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x83ff; + valaddr_reg:x4; val_offset:104*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 104*FLEN/8, x7, x1, x3) + +inst_80: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x400; + valaddr_reg:x4; val_offset:106*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 106*FLEN/8, x7, x1, x3) + +inst_81: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8400; + valaddr_reg:x4; val_offset:108*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 108*FLEN/8, x7, x1, x3) + +inst_82: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x401; + valaddr_reg:x4; val_offset:110*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 110*FLEN/8, x7, x1, x3) + +inst_83: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8455; + valaddr_reg:x4; val_offset:112*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 112*FLEN/8, x7, x1, x3) + +inst_84: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x7bff; + valaddr_reg:x4; val_offset:114*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 114*FLEN/8, x7, x1, x3) + +inst_85: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xfbff; + valaddr_reg:x4; val_offset:116*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 116*FLEN/8, x7, x1, x3) + +inst_86: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x7c00; + valaddr_reg:x4; val_offset:118*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 118*FLEN/8, x7, x1, x3) + +inst_87: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xfc00; + valaddr_reg:x4; val_offset:120*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 120*FLEN/8, x7, x1, x3) + +inst_88: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x7e00; + valaddr_reg:x4; val_offset:122*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 122*FLEN/8, x7, x1, x3) + +inst_89: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xfe00; + valaddr_reg:x4; val_offset:124*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 124*FLEN/8, x7, x1, x3) + +inst_90: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x7e01; + valaddr_reg:x4; val_offset:126*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 126*FLEN/8, x7, x1, x3) + +inst_91: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xfe55; + valaddr_reg:x4; val_offset:128*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 128*FLEN/8, x7, x1, x3) + +inst_92: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x7c01; + valaddr_reg:x4; val_offset:130*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 130*FLEN/8, x7, x1, x3) + +inst_93: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xfd55; + valaddr_reg:x4; val_offset:132*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 132*FLEN/8, x7, x1, x3) + +inst_94: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x3c00; + valaddr_reg:x4; val_offset:134*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 134*FLEN/8, x7, x1, x3) + +inst_95: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xbc00; + valaddr_reg:x4; val_offset:136*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 136*FLEN/8, x7, x1, x3) + +inst_96: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x0; + valaddr_reg:x4; val_offset:138*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 138*FLEN/8, x7, x1, x3) + +inst_97: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x8000; + valaddr_reg:x4; val_offset:140*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 140*FLEN/8, x7, x1, x3) + +inst_98: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x1; + valaddr_reg:x4; val_offset:142*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 142*FLEN/8, x7, x1, x3) + +inst_99: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x8001; + valaddr_reg:x4; val_offset:144*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 144*FLEN/8, x7, x1, x3) + +inst_100: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x2; + valaddr_reg:x4; val_offset:146*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 146*FLEN/8, x7, x1, x3) + +inst_101: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x83fe; + valaddr_reg:x4; val_offset:148*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 148*FLEN/8, x7, x1, x3) + +inst_102: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x3ff; + valaddr_reg:x4; val_offset:150*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 150*FLEN/8, x7, x1, x3) + +inst_103: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x83ff; + valaddr_reg:x4; val_offset:152*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 152*FLEN/8, x7, x1, x3) + +inst_104: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x400; + valaddr_reg:x4; val_offset:154*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 154*FLEN/8, x7, x1, x3) + +inst_105: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x8400; + valaddr_reg:x4; val_offset:156*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 156*FLEN/8, x7, x1, x3) + +inst_106: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x401; + valaddr_reg:x4; val_offset:158*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 158*FLEN/8, x7, x1, x3) + +inst_107: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x8455; + valaddr_reg:x4; val_offset:160*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 160*FLEN/8, x7, x1, x3) + +inst_108: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x7bff; + valaddr_reg:x4; val_offset:162*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 162*FLEN/8, x7, x1, x3) + +inst_109: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xfbff; + valaddr_reg:x4; val_offset:164*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 164*FLEN/8, x7, x1, x3) + +inst_110: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x7c00; + valaddr_reg:x4; val_offset:166*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 166*FLEN/8, x7, x1, x3) + +inst_111: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xfc00; + valaddr_reg:x4; val_offset:168*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 168*FLEN/8, x7, x1, x3) + +inst_112: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x7e00; + valaddr_reg:x4; val_offset:170*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 170*FLEN/8, x7, x1, x3) + +inst_113: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xfe00; + valaddr_reg:x4; val_offset:172*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 172*FLEN/8, x7, x1, x3) + +inst_114: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x7e01; + valaddr_reg:x4; val_offset:174*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 174*FLEN/8, x7, x1, x3) + +inst_115: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xfe55; + valaddr_reg:x4; val_offset:176*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 176*FLEN/8, x7, x1, x3) + +inst_116: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x7c01; + valaddr_reg:x4; val_offset:178*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 178*FLEN/8, x7, x1, x3) + +inst_117: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xfd55; + valaddr_reg:x4; val_offset:180*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 180*FLEN/8, x7, x1, x3) + +inst_118: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x3c00; + valaddr_reg:x4; val_offset:182*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 182*FLEN/8, x7, x1, x3) + +inst_119: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xbc00; + valaddr_reg:x4; val_offset:184*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 184*FLEN/8, x7, x1, x3) + +inst_120: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x0; + valaddr_reg:x4; val_offset:186*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 186*FLEN/8, x7, x1, x3) + +inst_121: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x8000; + valaddr_reg:x4; val_offset:188*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 188*FLEN/8, x7, x1, x3) + +inst_122: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x1; + valaddr_reg:x4; val_offset:190*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 190*FLEN/8, x7, x1, x3) + +inst_123: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x8001; + valaddr_reg:x4; val_offset:192*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 192*FLEN/8, x7, x1, x3) + +inst_124: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x2; + valaddr_reg:x4; val_offset:194*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 194*FLEN/8, x7, x1, x3) + +inst_125: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x83fe; + valaddr_reg:x4; val_offset:196*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 196*FLEN/8, x7, x1, x3) + +inst_126: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x3ff; + valaddr_reg:x4; val_offset:198*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 198*FLEN/8, x7, x1, x3) + +inst_127: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x83ff; + valaddr_reg:x4; val_offset:200*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 200*FLEN/8, x7, x1, x3) + +inst_128: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x400; + valaddr_reg:x4; val_offset:202*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 202*FLEN/8, x7, x1, x3) + +inst_129: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x8400; + valaddr_reg:x4; val_offset:204*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 204*FLEN/8, x7, x1, x3) + +inst_130: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x401; + valaddr_reg:x4; val_offset:206*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 206*FLEN/8, x7, x1, x3) + +inst_131: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x8455; + valaddr_reg:x4; val_offset:208*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 208*FLEN/8, x7, x1, x3) + +inst_132: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x7bff; + valaddr_reg:x4; val_offset:210*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 210*FLEN/8, x7, x1, x3) + +inst_133: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xfbff; + valaddr_reg:x4; val_offset:212*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 212*FLEN/8, x7, x1, x3) + +inst_134: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x7c00; + valaddr_reg:x4; val_offset:214*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 214*FLEN/8, x7, x1, x3) + +inst_135: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xfc00; + valaddr_reg:x4; val_offset:216*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 216*FLEN/8, x7, x1, x3) + +inst_136: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x7e00; + valaddr_reg:x4; val_offset:218*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 218*FLEN/8, x7, x1, x3) + +inst_137: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xfe00; + valaddr_reg:x4; val_offset:220*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 220*FLEN/8, x7, x1, x3) + +inst_138: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x7e01; + valaddr_reg:x4; val_offset:222*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 222*FLEN/8, x7, x1, x3) + +inst_139: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xfe55; + valaddr_reg:x4; val_offset:224*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 224*FLEN/8, x7, x1, x3) + +inst_140: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x7c01; + valaddr_reg:x4; val_offset:226*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 226*FLEN/8, x7, x1, x3) + +inst_141: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xfd55; + valaddr_reg:x4; val_offset:228*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 228*FLEN/8, x7, x1, x3) + +inst_142: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x3c00; + valaddr_reg:x4; val_offset:230*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 230*FLEN/8, x7, x1, x3) + +inst_143: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xbc00; + valaddr_reg:x4; val_offset:232*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 232*FLEN/8, x7, x1, x3) + +inst_144: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x0; + valaddr_reg:x4; val_offset:234*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 234*FLEN/8, x7, x1, x3) + +inst_145: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x8000; + valaddr_reg:x4; val_offset:236*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 236*FLEN/8, x7, x1, x3) + +inst_146: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x1; + valaddr_reg:x4; val_offset:238*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 238*FLEN/8, x7, x1, x3) + +inst_147: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x8001; + valaddr_reg:x4; val_offset:240*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 240*FLEN/8, x7, x1, x3) + +inst_148: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x2; + valaddr_reg:x4; val_offset:242*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 242*FLEN/8, x7, x1, x3) + +inst_149: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x83fe; + valaddr_reg:x4; val_offset:244*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 244*FLEN/8, x7, x1, x3) + +inst_150: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x3ff; + valaddr_reg:x4; val_offset:246*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 246*FLEN/8, x7, x1, x3) + +inst_151: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x83ff; + valaddr_reg:x4; val_offset:248*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 248*FLEN/8, x7, x1, x3) + +inst_152: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x400; + valaddr_reg:x4; val_offset:250*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 250*FLEN/8, x7, x1, x3) + +inst_153: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x8400; + valaddr_reg:x4; val_offset:252*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 252*FLEN/8, x7, x1, x3) + +inst_154: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x401; + valaddr_reg:x4; val_offset:254*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 254*FLEN/8, x7, x1, x3) + +inst_155: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x8455; + valaddr_reg:x4; val_offset:256*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 256*FLEN/8, x7, x1, x3) + +inst_156: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7bff; + valaddr_reg:x4; val_offset:258*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 258*FLEN/8, x7, x1, x3) + +inst_157: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xfbff; + valaddr_reg:x4; val_offset:260*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 260*FLEN/8, x7, x1, x3) + +inst_158: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7c00; + valaddr_reg:x4; val_offset:262*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 262*FLEN/8, x7, x1, x3) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_159: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xfc00; + valaddr_reg:x4; val_offset:264*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 264*FLEN/8, x7, x1, x3) + +inst_160: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7e00; + valaddr_reg:x4; val_offset:266*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 266*FLEN/8, x7, x1, x3) + +inst_161: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xfe00; + valaddr_reg:x4; val_offset:268*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 268*FLEN/8, x7, x1, x3) + +inst_162: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7e01; + valaddr_reg:x4; val_offset:270*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 270*FLEN/8, x7, x1, x3) + +inst_163: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xfe55; + valaddr_reg:x4; val_offset:272*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 272*FLEN/8, x7, x1, x3) + +inst_164: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7c01; + valaddr_reg:x4; val_offset:274*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 274*FLEN/8, x7, x1, x3) + +inst_165: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xfd55; + valaddr_reg:x4; val_offset:276*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 276*FLEN/8, x7, x1, x3) + +inst_166: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x3c00; + valaddr_reg:x4; val_offset:278*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 278*FLEN/8, x7, x1, x3) + +inst_167: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xbc00; + valaddr_reg:x4; val_offset:280*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 280*FLEN/8, x7, x1, x3) + +inst_168: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x0; + valaddr_reg:x4; val_offset:282*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 282*FLEN/8, x7, x1, x3) + +inst_169: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8000; + valaddr_reg:x4; val_offset:284*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 284*FLEN/8, x7, x1, x3) + +inst_170: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x1; + valaddr_reg:x4; val_offset:286*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 286*FLEN/8, x7, x1, x3) + +inst_171: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8001; + valaddr_reg:x4; val_offset:288*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 288*FLEN/8, x7, x1, x3) + +inst_172: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x2; + valaddr_reg:x4; val_offset:290*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 290*FLEN/8, x7, x1, x3) + +inst_173: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x83fe; + valaddr_reg:x4; val_offset:292*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 292*FLEN/8, x7, x1, x3) + +inst_174: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x3ff; + valaddr_reg:x4; val_offset:294*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 294*FLEN/8, x7, x1, x3) + +inst_175: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x83ff; + valaddr_reg:x4; val_offset:296*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 296*FLEN/8, x7, x1, x3) + +inst_176: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x400; + valaddr_reg:x4; val_offset:298*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 298*FLEN/8, x7, x1, x3) + +inst_177: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8400; + valaddr_reg:x4; val_offset:300*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 300*FLEN/8, x7, x1, x3) + +inst_178: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x401; + valaddr_reg:x4; val_offset:302*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 302*FLEN/8, x7, x1, x3) + +inst_179: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8455; + valaddr_reg:x4; val_offset:304*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 304*FLEN/8, x7, x1, x3) + +inst_180: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x7bff; + valaddr_reg:x4; val_offset:306*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 306*FLEN/8, x7, x1, x3) + +inst_181: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xfbff; + valaddr_reg:x4; val_offset:308*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 308*FLEN/8, x7, x1, x3) + +inst_182: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x7c00; + valaddr_reg:x4; val_offset:310*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 310*FLEN/8, x7, x1, x3) + +inst_183: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xfc00; + valaddr_reg:x4; val_offset:312*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 312*FLEN/8, x7, x1, x3) + +inst_184: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x7e00; + valaddr_reg:x4; val_offset:314*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 314*FLEN/8, x7, x1, x3) + +inst_185: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xfe00; + valaddr_reg:x4; val_offset:316*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 316*FLEN/8, x7, x1, x3) + +inst_186: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x7e01; + valaddr_reg:x4; val_offset:318*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 318*FLEN/8, x7, x1, x3) + +inst_187: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xfe55; + valaddr_reg:x4; val_offset:320*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 320*FLEN/8, x7, x1, x3) + +inst_188: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x7c01; + valaddr_reg:x4; val_offset:322*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 322*FLEN/8, x7, x1, x3) + +inst_189: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xfd55; + valaddr_reg:x4; val_offset:324*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 324*FLEN/8, x7, x1, x3) + +inst_190: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x3c00; + valaddr_reg:x4; val_offset:326*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 326*FLEN/8, x7, x1, x3) + +inst_191: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xbc00; + valaddr_reg:x4; val_offset:328*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 328*FLEN/8, x7, x1, x3) + +inst_192: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x0; + valaddr_reg:x4; val_offset:330*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 330*FLEN/8, x7, x1, x3) + +inst_193: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x8000; + valaddr_reg:x4; val_offset:332*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 332*FLEN/8, x7, x1, x3) + +inst_194: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x1; + valaddr_reg:x4; val_offset:334*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 334*FLEN/8, x7, x1, x3) + +inst_195: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x8001; + valaddr_reg:x4; val_offset:336*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 336*FLEN/8, x7, x1, x3) + +inst_196: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x2; + valaddr_reg:x4; val_offset:338*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 338*FLEN/8, x7, x1, x3) + +inst_197: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x83fe; + valaddr_reg:x4; val_offset:340*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 340*FLEN/8, x7, x1, x3) + +inst_198: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x3ff; + valaddr_reg:x4; val_offset:342*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 342*FLEN/8, x7, x1, x3) + +inst_199: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x83ff; + valaddr_reg:x4; val_offset:344*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 344*FLEN/8, x7, x1, x3) + +inst_200: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x400; + valaddr_reg:x4; val_offset:346*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 346*FLEN/8, x7, x1, x3) + +inst_201: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x8400; + valaddr_reg:x4; val_offset:348*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 348*FLEN/8, x7, x1, x3) + +inst_202: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x401; + valaddr_reg:x4; val_offset:350*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 350*FLEN/8, x7, x1, x3) + +inst_203: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x8455; + valaddr_reg:x4; val_offset:352*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 352*FLEN/8, x7, x1, x3) + +inst_204: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7bff; + valaddr_reg:x4; val_offset:354*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 354*FLEN/8, x7, x1, x3) + +inst_205: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xfbff; + valaddr_reg:x4; val_offset:356*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 356*FLEN/8, x7, x1, x3) + +inst_206: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7c00; + valaddr_reg:x4; val_offset:358*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 358*FLEN/8, x7, x1, x3) + +inst_207: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xfc00; + valaddr_reg:x4; val_offset:360*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 360*FLEN/8, x7, x1, x3) + +inst_208: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7e00; + valaddr_reg:x4; val_offset:362*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 362*FLEN/8, x7, x1, x3) + +inst_209: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xfe00; + valaddr_reg:x4; val_offset:364*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 364*FLEN/8, x7, x1, x3) + +inst_210: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7e01; + valaddr_reg:x4; val_offset:366*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 366*FLEN/8, x7, x1, x3) + +inst_211: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xfe55; + valaddr_reg:x4; val_offset:368*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 368*FLEN/8, x7, x1, x3) + +inst_212: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7c01; + valaddr_reg:x4; val_offset:370*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 370*FLEN/8, x7, x1, x3) + +inst_213: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xfd55; + valaddr_reg:x4; val_offset:372*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 372*FLEN/8, x7, x1, x3) + +inst_214: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x3c00; + valaddr_reg:x4; val_offset:374*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 374*FLEN/8, x7, x1, x3) + +inst_215: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xbc00; + valaddr_reg:x4; val_offset:376*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 376*FLEN/8, x7, x1, x3) + +inst_216: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x0; + valaddr_reg:x4; val_offset:378*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 378*FLEN/8, x7, x1, x3) + +inst_217: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8000; + valaddr_reg:x4; val_offset:380*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 380*FLEN/8, x7, x1, x3) + +inst_218: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x1; + valaddr_reg:x4; val_offset:382*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 382*FLEN/8, x7, x1, x3) + +inst_219: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8001; + valaddr_reg:x4; val_offset:384*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 384*FLEN/8, x7, x1, x3) + +inst_220: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x2; + valaddr_reg:x4; val_offset:386*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 386*FLEN/8, x7, x1, x3) + +inst_221: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x83fe; + valaddr_reg:x4; val_offset:388*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 388*FLEN/8, x7, x1, x3) + +inst_222: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x3ff; + valaddr_reg:x4; val_offset:390*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 390*FLEN/8, x7, x1, x3) + +inst_223: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x83ff; + valaddr_reg:x4; val_offset:392*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 392*FLEN/8, x7, x1, x3) + +inst_224: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x400; + valaddr_reg:x4; val_offset:394*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 394*FLEN/8, x7, x1, x3) + +inst_225: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8400; + valaddr_reg:x4; val_offset:396*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 396*FLEN/8, x7, x1, x3) + +inst_226: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x401; + valaddr_reg:x4; val_offset:398*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 398*FLEN/8, x7, x1, x3) + +inst_227: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8455; + valaddr_reg:x4; val_offset:400*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 400*FLEN/8, x7, x1, x3) + +inst_228: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x7bff; + valaddr_reg:x4; val_offset:402*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 402*FLEN/8, x7, x1, x3) + +inst_229: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xfbff; + valaddr_reg:x4; val_offset:404*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 404*FLEN/8, x7, x1, x3) + +inst_230: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x7c00; + valaddr_reg:x4; val_offset:406*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 406*FLEN/8, x7, x1, x3) + +inst_231: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xfc00; + valaddr_reg:x4; val_offset:408*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 408*FLEN/8, x7, x1, x3) + +inst_232: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x7e00; + valaddr_reg:x4; val_offset:410*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 410*FLEN/8, x7, x1, x3) + +inst_233: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xfe00; + valaddr_reg:x4; val_offset:412*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 412*FLEN/8, x7, x1, x3) + +inst_234: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x7e01; + valaddr_reg:x4; val_offset:414*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 414*FLEN/8, x7, x1, x3) + +inst_235: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xfe55; + valaddr_reg:x4; val_offset:416*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 416*FLEN/8, x7, x1, x3) + +inst_236: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x7c01; + valaddr_reg:x4; val_offset:418*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 418*FLEN/8, x7, x1, x3) + +inst_237: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xfd55; + valaddr_reg:x4; val_offset:420*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 420*FLEN/8, x7, x1, x3) + +inst_238: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x3c00; + valaddr_reg:x4; val_offset:422*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 422*FLEN/8, x7, x1, x3) + +inst_239: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xbc00; + valaddr_reg:x4; val_offset:424*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 424*FLEN/8, x7, x1, x3) + +inst_240: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x0; + valaddr_reg:x4; val_offset:426*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 426*FLEN/8, x7, x1, x3) + +inst_241: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x8000; + valaddr_reg:x4; val_offset:428*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 428*FLEN/8, x7, x1, x3) + +inst_242: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x1; + valaddr_reg:x4; val_offset:430*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 430*FLEN/8, x7, x1, x3) + +inst_243: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x8001; + valaddr_reg:x4; val_offset:432*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 432*FLEN/8, x7, x1, x3) + +inst_244: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x2; + valaddr_reg:x4; val_offset:434*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 434*FLEN/8, x7, x1, x3) + +inst_245: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x83fe; + valaddr_reg:x4; val_offset:436*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 436*FLEN/8, x7, x1, x3) + +inst_246: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x3ff; + valaddr_reg:x4; val_offset:438*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 438*FLEN/8, x7, x1, x3) + +inst_247: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x83ff; + valaddr_reg:x4; val_offset:440*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 440*FLEN/8, x7, x1, x3) + +inst_248: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x400; + valaddr_reg:x4; val_offset:442*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 442*FLEN/8, x7, x1, x3) + +inst_249: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x8400; + valaddr_reg:x4; val_offset:444*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 444*FLEN/8, x7, x1, x3) + +inst_250: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x401; + valaddr_reg:x4; val_offset:446*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 446*FLEN/8, x7, x1, x3) + +inst_251: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x8455; + valaddr_reg:x4; val_offset:448*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 448*FLEN/8, x7, x1, x3) + +inst_252: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x7bff; + valaddr_reg:x4; val_offset:450*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 450*FLEN/8, x7, x1, x3) + +inst_253: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xfbff; + valaddr_reg:x4; val_offset:452*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 452*FLEN/8, x7, x1, x3) + +inst_254: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x7c00; + valaddr_reg:x4; val_offset:454*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 454*FLEN/8, x7, x1, x3) + +inst_255: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xfc00; + valaddr_reg:x4; val_offset:456*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 456*FLEN/8, x7, x1, x3) + +inst_256: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x7e00; + valaddr_reg:x4; val_offset:458*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 458*FLEN/8, x7, x1, x3) + +inst_257: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xfe00; + valaddr_reg:x4; val_offset:460*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 460*FLEN/8, x7, x1, x3) + +inst_258: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x7e01; + valaddr_reg:x4; val_offset:462*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 462*FLEN/8, x7, x1, x3) + +inst_259: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xfe55; + valaddr_reg:x4; val_offset:464*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 464*FLEN/8, x7, x1, x3) + +inst_260: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x7c01; + valaddr_reg:x4; val_offset:466*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 466*FLEN/8, x7, x1, x3) + +inst_261: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xfd55; + valaddr_reg:x4; val_offset:468*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 468*FLEN/8, x7, x1, x3) + +inst_262: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x3c00; + valaddr_reg:x4; val_offset:470*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 470*FLEN/8, x7, x1, x3) + +inst_263: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xbc00; + valaddr_reg:x4; val_offset:472*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 472*FLEN/8, x7, x1, x3) + +inst_264: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x0; + valaddr_reg:x4; val_offset:474*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 474*FLEN/8, x7, x1, x3) + +inst_265: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x8000; + valaddr_reg:x4; val_offset:476*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 476*FLEN/8, x7, x1, x3) + +inst_266: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x1; + valaddr_reg:x4; val_offset:478*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 478*FLEN/8, x7, x1, x3) + +inst_267: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x8001; + valaddr_reg:x4; val_offset:480*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 480*FLEN/8, x7, x1, x3) + +inst_268: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x2; + valaddr_reg:x4; val_offset:482*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 482*FLEN/8, x7, x1, x3) + +inst_269: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x83fe; + valaddr_reg:x4; val_offset:484*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 484*FLEN/8, x7, x1, x3) + +inst_270: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x3ff; + valaddr_reg:x4; val_offset:486*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 486*FLEN/8, x7, x1, x3) + +inst_271: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x83ff; + valaddr_reg:x4; val_offset:488*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 488*FLEN/8, x7, x1, x3) + +inst_272: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x400; + valaddr_reg:x4; val_offset:490*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 490*FLEN/8, x7, x1, x3) + +inst_273: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x8400; + valaddr_reg:x4; val_offset:492*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 492*FLEN/8, x7, x1, x3) + +inst_274: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x401; + valaddr_reg:x4; val_offset:494*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 494*FLEN/8, x7, x1, x3) + +inst_275: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x8455; + valaddr_reg:x4; val_offset:496*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 496*FLEN/8, x7, x1, x3) + +inst_276: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x7bff; + valaddr_reg:x4; val_offset:498*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 498*FLEN/8, x7, x1, x3) + +inst_277: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xfbff; + valaddr_reg:x4; val_offset:500*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 500*FLEN/8, x7, x1, x3) + +inst_278: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x7c00; + valaddr_reg:x4; val_offset:502*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 502*FLEN/8, x7, x1, x3) + +inst_279: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xfc00; + valaddr_reg:x4; val_offset:504*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 504*FLEN/8, x7, x1, x3) + +inst_280: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x7e00; + valaddr_reg:x4; val_offset:506*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 506*FLEN/8, x7, x1, x3) + +inst_281: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xfe00; + valaddr_reg:x4; val_offset:508*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 508*FLEN/8, x7, x1, x3) + +inst_282: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x7e01; + valaddr_reg:x4; val_offset:510*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 510*FLEN/8, x7, x1, x3) + +inst_283: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xfe55; + valaddr_reg:x4; val_offset:512*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 512*FLEN/8, x7, x1, x3) + +inst_284: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x7c01; + valaddr_reg:x4; val_offset:514*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 514*FLEN/8, x7, x1, x3) + +inst_285: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xfd55; + valaddr_reg:x4; val_offset:516*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 516*FLEN/8, x7, x1, x3) + +inst_286: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x3c00; + valaddr_reg:x4; val_offset:518*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 518*FLEN/8, x7, x1, x3) +RVTEST_SIGBASE(x1,signature_x1_2) + +inst_287: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xbc00; + valaddr_reg:x4; val_offset:520*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 520*FLEN/8, x7, x1, x3) + +inst_288: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x0; + valaddr_reg:x4; val_offset:522*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 522*FLEN/8, x7, x1, x3) + +inst_289: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8000; + valaddr_reg:x4; val_offset:524*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 524*FLEN/8, x7, x1, x3) + +inst_290: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x1; + valaddr_reg:x4; val_offset:526*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 526*FLEN/8, x7, x1, x3) + +inst_291: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8001; + valaddr_reg:x4; val_offset:528*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 528*FLEN/8, x7, x1, x3) + +inst_292: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x2; + valaddr_reg:x4; val_offset:530*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 530*FLEN/8, x7, x1, x3) + +inst_293: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x83fe; + valaddr_reg:x4; val_offset:532*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 532*FLEN/8, x7, x1, x3) + +inst_294: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x3ff; + valaddr_reg:x4; val_offset:534*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 534*FLEN/8, x7, x1, x3) + +inst_295: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x83ff; + valaddr_reg:x4; val_offset:536*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 536*FLEN/8, x7, x1, x3) + +inst_296: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x400; + valaddr_reg:x4; val_offset:538*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 538*FLEN/8, x7, x1, x3) + +inst_297: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8400; + valaddr_reg:x4; val_offset:540*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 540*FLEN/8, x7, x1, x3) + +inst_298: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x401; + valaddr_reg:x4; val_offset:542*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 542*FLEN/8, x7, x1, x3) + +inst_299: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8455; + valaddr_reg:x4; val_offset:544*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 544*FLEN/8, x7, x1, x3) + +inst_300: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7bff; + valaddr_reg:x4; val_offset:546*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 546*FLEN/8, x7, x1, x3) + +inst_301: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xfbff; + valaddr_reg:x4; val_offset:548*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 548*FLEN/8, x7, x1, x3) + +inst_302: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7c00; + valaddr_reg:x4; val_offset:550*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 550*FLEN/8, x7, x1, x3) + +inst_303: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xfc00; + valaddr_reg:x4; val_offset:552*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 552*FLEN/8, x7, x1, x3) + +inst_304: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7e00; + valaddr_reg:x4; val_offset:554*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 554*FLEN/8, x7, x1, x3) + +inst_305: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xfe00; + valaddr_reg:x4; val_offset:556*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 556*FLEN/8, x7, x1, x3) + +inst_306: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7e01; + valaddr_reg:x4; val_offset:558*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 558*FLEN/8, x7, x1, x3) + +inst_307: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xfe55; + valaddr_reg:x4; val_offset:560*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 560*FLEN/8, x7, x1, x3) + +inst_308: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7c01; + valaddr_reg:x4; val_offset:562*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 562*FLEN/8, x7, x1, x3) + +inst_309: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xfd55; + valaddr_reg:x4; val_offset:564*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 564*FLEN/8, x7, x1, x3) + +inst_310: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x3c00; + valaddr_reg:x4; val_offset:566*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 566*FLEN/8, x7, x1, x3) + +inst_311: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xbc00; + valaddr_reg:x4; val_offset:568*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 568*FLEN/8, x7, x1, x3) + +inst_312: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x0; + valaddr_reg:x4; val_offset:570*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 570*FLEN/8, x7, x1, x3) + +inst_313: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8000; + valaddr_reg:x4; val_offset:572*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 572*FLEN/8, x7, x1, x3) + +inst_314: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x1; + valaddr_reg:x4; val_offset:574*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 574*FLEN/8, x7, x1, x3) + +inst_315: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8001; + valaddr_reg:x4; val_offset:576*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 576*FLEN/8, x7, x1, x3) + +inst_316: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x2; + valaddr_reg:x4; val_offset:578*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 578*FLEN/8, x7, x1, x3) + +inst_317: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x83fe; + valaddr_reg:x4; val_offset:580*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 580*FLEN/8, x7, x1, x3) + +inst_318: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x3ff; + valaddr_reg:x4; val_offset:582*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 582*FLEN/8, x7, x1, x3) + +inst_319: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x83ff; + valaddr_reg:x4; val_offset:584*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 584*FLEN/8, x7, x1, x3) + +inst_320: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x400; + valaddr_reg:x4; val_offset:586*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 586*FLEN/8, x7, x1, x3) + +inst_321: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8400; + valaddr_reg:x4; val_offset:588*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 588*FLEN/8, x7, x1, x3) + +inst_322: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x401; + valaddr_reg:x4; val_offset:590*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 590*FLEN/8, x7, x1, x3) + +inst_323: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8455; + valaddr_reg:x4; val_offset:592*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 592*FLEN/8, x7, x1, x3) + +inst_324: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7bff; + valaddr_reg:x4; val_offset:594*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 594*FLEN/8, x7, x1, x3) + +inst_325: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfbff; + valaddr_reg:x4; val_offset:596*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 596*FLEN/8, x7, x1, x3) + +inst_326: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7c00; + valaddr_reg:x4; val_offset:598*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 598*FLEN/8, x7, x1, x3) + +inst_327: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfc00; + valaddr_reg:x4; val_offset:600*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 600*FLEN/8, x7, x1, x3) + +inst_328: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7e00; + valaddr_reg:x4; val_offset:602*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 602*FLEN/8, x7, x1, x3) + +inst_329: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfe00; + valaddr_reg:x4; val_offset:604*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 604*FLEN/8, x7, x1, x3) + +inst_330: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7e01; + valaddr_reg:x4; val_offset:606*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 606*FLEN/8, x7, x1, x3) + +inst_331: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfe55; + valaddr_reg:x4; val_offset:608*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 608*FLEN/8, x7, x1, x3) + +inst_332: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7c01; + valaddr_reg:x4; val_offset:610*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 610*FLEN/8, x7, x1, x3) + +inst_333: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfd55; + valaddr_reg:x4; val_offset:612*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 612*FLEN/8, x7, x1, x3) + +inst_334: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x3c00; + valaddr_reg:x4; val_offset:614*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 614*FLEN/8, x7, x1, x3) + +inst_335: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xbc00; + valaddr_reg:x4; val_offset:616*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 616*FLEN/8, x7, x1, x3) + +inst_336: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x0; + valaddr_reg:x4; val_offset:618*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 618*FLEN/8, x7, x1, x3) + +inst_337: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x8000; + valaddr_reg:x4; val_offset:620*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 620*FLEN/8, x7, x1, x3) + +inst_338: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x1; + valaddr_reg:x4; val_offset:622*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 622*FLEN/8, x7, x1, x3) + +inst_339: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x8001; + valaddr_reg:x4; val_offset:624*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 624*FLEN/8, x7, x1, x3) + +inst_340: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x2; + valaddr_reg:x4; val_offset:626*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 626*FLEN/8, x7, x1, x3) + +inst_341: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x83fe; + valaddr_reg:x4; val_offset:628*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 628*FLEN/8, x7, x1, x3) + +inst_342: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x3ff; + valaddr_reg:x4; val_offset:630*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 630*FLEN/8, x7, x1, x3) + +inst_343: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x83ff; + valaddr_reg:x4; val_offset:632*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 632*FLEN/8, x7, x1, x3) + +inst_344: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x400; + valaddr_reg:x4; val_offset:634*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 634*FLEN/8, x7, x1, x3) + +inst_345: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x8400; + valaddr_reg:x4; val_offset:636*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 636*FLEN/8, x7, x1, x3) + +inst_346: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x401; + valaddr_reg:x4; val_offset:638*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 638*FLEN/8, x7, x1, x3) + +inst_347: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x8455; + valaddr_reg:x4; val_offset:640*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 640*FLEN/8, x7, x1, x3) + +inst_348: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x7bff; + valaddr_reg:x4; val_offset:642*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 642*FLEN/8, x7, x1, x3) + +inst_349: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xfbff; + valaddr_reg:x4; val_offset:644*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 644*FLEN/8, x7, x1, x3) + +inst_350: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x7c00; + valaddr_reg:x4; val_offset:646*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 646*FLEN/8, x7, x1, x3) + +inst_351: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xfc00; + valaddr_reg:x4; val_offset:648*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 648*FLEN/8, x7, x1, x3) + +inst_352: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x7e00; + valaddr_reg:x4; val_offset:650*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 650*FLEN/8, x7, x1, x3) + +inst_353: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xfe00; + valaddr_reg:x4; val_offset:652*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 652*FLEN/8, x7, x1, x3) + +inst_354: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x7e01; + valaddr_reg:x4; val_offset:654*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 654*FLEN/8, x7, x1, x3) + +inst_355: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xfe55; + valaddr_reg:x4; val_offset:656*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 656*FLEN/8, x7, x1, x3) + +inst_356: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x7c01; + valaddr_reg:x4; val_offset:658*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 658*FLEN/8, x7, x1, x3) + +inst_357: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xfd55; + valaddr_reg:x4; val_offset:660*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 660*FLEN/8, x7, x1, x3) + +inst_358: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x3c00; + valaddr_reg:x4; val_offset:662*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 662*FLEN/8, x7, x1, x3) + +inst_359: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xbc00; + valaddr_reg:x4; val_offset:664*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 664*FLEN/8, x7, x1, x3) + +inst_360: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x0; + valaddr_reg:x4; val_offset:666*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 666*FLEN/8, x7, x1, x3) + +inst_361: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x8000; + valaddr_reg:x4; val_offset:668*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 668*FLEN/8, x7, x1, x3) + +inst_362: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x1; + valaddr_reg:x4; val_offset:670*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 670*FLEN/8, x7, x1, x3) + +inst_363: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x8001; + valaddr_reg:x4; val_offset:672*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 672*FLEN/8, x7, x1, x3) + +inst_364: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x2; + valaddr_reg:x4; val_offset:674*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 674*FLEN/8, x7, x1, x3) + +inst_365: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x83fe; + valaddr_reg:x4; val_offset:676*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 676*FLEN/8, x7, x1, x3) + +inst_366: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x3ff; + valaddr_reg:x4; val_offset:678*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 678*FLEN/8, x7, x1, x3) + +inst_367: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x83ff; + valaddr_reg:x4; val_offset:680*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 680*FLEN/8, x7, x1, x3) + +inst_368: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x400; + valaddr_reg:x4; val_offset:682*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 682*FLEN/8, x7, x1, x3) + +inst_369: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x8400; + valaddr_reg:x4; val_offset:684*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 684*FLEN/8, x7, x1, x3) + +inst_370: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x401; + valaddr_reg:x4; val_offset:686*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 686*FLEN/8, x7, x1, x3) + +inst_371: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x8455; + valaddr_reg:x4; val_offset:688*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 688*FLEN/8, x7, x1, x3) + +inst_372: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x7bff; + valaddr_reg:x4; val_offset:690*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 690*FLEN/8, x7, x1, x3) + +inst_373: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xfbff; + valaddr_reg:x4; val_offset:692*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 692*FLEN/8, x7, x1, x3) + +inst_374: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x7c00; + valaddr_reg:x4; val_offset:694*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 694*FLEN/8, x7, x1, x3) + +inst_375: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xfc00; + valaddr_reg:x4; val_offset:696*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 696*FLEN/8, x7, x1, x3) + +inst_376: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x7e00; + valaddr_reg:x4; val_offset:698*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 698*FLEN/8, x7, x1, x3) + +inst_377: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xfe00; + valaddr_reg:x4; val_offset:700*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 700*FLEN/8, x7, x1, x3) + +inst_378: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x7e01; + valaddr_reg:x4; val_offset:702*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 702*FLEN/8, x7, x1, x3) + +inst_379: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xfe55; + valaddr_reg:x4; val_offset:704*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 704*FLEN/8, x7, x1, x3) + +inst_380: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x7c01; + valaddr_reg:x4; val_offset:706*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 706*FLEN/8, x7, x1, x3) + +inst_381: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xfd55; + valaddr_reg:x4; val_offset:708*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 708*FLEN/8, x7, x1, x3) + +inst_382: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x3c00; + valaddr_reg:x4; val_offset:710*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 710*FLEN/8, x7, x1, x3) + +inst_383: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xbc00; + valaddr_reg:x4; val_offset:712*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 712*FLEN/8, x7, x1, x3) + +inst_384: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x0; + valaddr_reg:x4; val_offset:714*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 714*FLEN/8, x7, x1, x3) + +inst_385: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x8000; + valaddr_reg:x4; val_offset:716*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 716*FLEN/8, x7, x1, x3) + +inst_386: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x1; + valaddr_reg:x4; val_offset:718*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 718*FLEN/8, x7, x1, x3) + +inst_387: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x8001; + valaddr_reg:x4; val_offset:720*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 720*FLEN/8, x7, x1, x3) + +inst_388: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x2; + valaddr_reg:x4; val_offset:722*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 722*FLEN/8, x7, x1, x3) + +inst_389: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x83fe; + valaddr_reg:x4; val_offset:724*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 724*FLEN/8, x7, x1, x3) + +inst_390: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x3ff; + valaddr_reg:x4; val_offset:726*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 726*FLEN/8, x7, x1, x3) + +inst_391: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x83ff; + valaddr_reg:x4; val_offset:728*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 728*FLEN/8, x7, x1, x3) + +inst_392: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x400; + valaddr_reg:x4; val_offset:730*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 730*FLEN/8, x7, x1, x3) + +inst_393: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x8400; + valaddr_reg:x4; val_offset:732*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 732*FLEN/8, x7, x1, x3) + +inst_394: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x401; + valaddr_reg:x4; val_offset:734*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 734*FLEN/8, x7, x1, x3) + +inst_395: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x8455; + valaddr_reg:x4; val_offset:736*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 736*FLEN/8, x7, x1, x3) + +inst_396: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x7bff; + valaddr_reg:x4; val_offset:738*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 738*FLEN/8, x7, x1, x3) + +inst_397: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xfbff; + valaddr_reg:x4; val_offset:740*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 740*FLEN/8, x7, x1, x3) + +inst_398: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x7c00; + valaddr_reg:x4; val_offset:742*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 742*FLEN/8, x7, x1, x3) + +inst_399: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xfc00; + valaddr_reg:x4; val_offset:744*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 744*FLEN/8, x7, x1, x3) + +inst_400: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x7e00; + valaddr_reg:x4; val_offset:746*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 746*FLEN/8, x7, x1, x3) + +inst_401: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xfe00; + valaddr_reg:x4; val_offset:748*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 748*FLEN/8, x7, x1, x3) + +inst_402: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x7e01; + valaddr_reg:x4; val_offset:750*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 750*FLEN/8, x7, x1, x3) + +inst_403: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xfe55; + valaddr_reg:x4; val_offset:752*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 752*FLEN/8, x7, x1, x3) + +inst_404: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x7c01; + valaddr_reg:x4; val_offset:754*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 754*FLEN/8, x7, x1, x3) + +inst_405: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xfd55; + valaddr_reg:x4; val_offset:756*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 756*FLEN/8, x7, x1, x3) + +inst_406: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x3c00; + valaddr_reg:x4; val_offset:758*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 758*FLEN/8, x7, x1, x3) + +inst_407: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xbc00; + valaddr_reg:x4; val_offset:760*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 760*FLEN/8, x7, x1, x3) + +inst_408: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x0; + valaddr_reg:x4; val_offset:762*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 762*FLEN/8, x7, x1, x3) + +inst_409: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x8000; + valaddr_reg:x4; val_offset:764*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 764*FLEN/8, x7, x1, x3) + +inst_410: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x1; + valaddr_reg:x4; val_offset:766*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 766*FLEN/8, x7, x1, x3) + +inst_411: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x8001; + valaddr_reg:x4; val_offset:768*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 768*FLEN/8, x7, x1, x3) + +inst_412: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x2; + valaddr_reg:x4; val_offset:770*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 770*FLEN/8, x7, x1, x3) + +inst_413: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x83fe; + valaddr_reg:x4; val_offset:772*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 772*FLEN/8, x7, x1, x3) + +inst_414: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x3ff; + valaddr_reg:x4; val_offset:774*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 774*FLEN/8, x7, x1, x3) +RVTEST_SIGBASE(x1,signature_x1_3) + +inst_415: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x83ff; + valaddr_reg:x4; val_offset:776*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 776*FLEN/8, x7, x1, x3) + +inst_416: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x400; + valaddr_reg:x4; val_offset:778*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 778*FLEN/8, x7, x1, x3) + +inst_417: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x8400; + valaddr_reg:x4; val_offset:780*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 780*FLEN/8, x7, x1, x3) + +inst_418: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x401; + valaddr_reg:x4; val_offset:782*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 782*FLEN/8, x7, x1, x3) + +inst_419: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x8455; + valaddr_reg:x4; val_offset:784*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 784*FLEN/8, x7, x1, x3) + +inst_420: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x7bff; + valaddr_reg:x4; val_offset:786*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 786*FLEN/8, x7, x1, x3) + +inst_421: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xfbff; + valaddr_reg:x4; val_offset:788*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 788*FLEN/8, x7, x1, x3) + +inst_422: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x7c00; + valaddr_reg:x4; val_offset:790*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 790*FLEN/8, x7, x1, x3) + +inst_423: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xfc00; + valaddr_reg:x4; val_offset:792*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 792*FLEN/8, x7, x1, x3) + +inst_424: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x7e00; + valaddr_reg:x4; val_offset:794*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 794*FLEN/8, x7, x1, x3) + +inst_425: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xfe00; + valaddr_reg:x4; val_offset:796*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 796*FLEN/8, x7, x1, x3) + +inst_426: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x7e01; + valaddr_reg:x4; val_offset:798*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 798*FLEN/8, x7, x1, x3) + +inst_427: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xfe55; + valaddr_reg:x4; val_offset:800*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 800*FLEN/8, x7, x1, x3) + +inst_428: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x7c01; + valaddr_reg:x4; val_offset:802*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 802*FLEN/8, x7, x1, x3) + +inst_429: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xfd55; + valaddr_reg:x4; val_offset:804*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 804*FLEN/8, x7, x1, x3) + +inst_430: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x3c00; + valaddr_reg:x4; val_offset:806*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 806*FLEN/8, x7, x1, x3) + +inst_431: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xbc00; + valaddr_reg:x4; val_offset:808*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 808*FLEN/8, x7, x1, x3) + +inst_432: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x0; + valaddr_reg:x4; val_offset:810*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 810*FLEN/8, x7, x1, x3) + +inst_433: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x8000; + valaddr_reg:x4; val_offset:812*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 812*FLEN/8, x7, x1, x3) + +inst_434: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x1; + valaddr_reg:x4; val_offset:814*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 814*FLEN/8, x7, x1, x3) + +inst_435: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x8001; + valaddr_reg:x4; val_offset:816*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 816*FLEN/8, x7, x1, x3) + +inst_436: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x2; + valaddr_reg:x4; val_offset:818*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 818*FLEN/8, x7, x1, x3) + +inst_437: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x83fe; + valaddr_reg:x4; val_offset:820*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 820*FLEN/8, x7, x1, x3) + +inst_438: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x3ff; + valaddr_reg:x4; val_offset:822*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 822*FLEN/8, x7, x1, x3) + +inst_439: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x83ff; + valaddr_reg:x4; val_offset:824*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 824*FLEN/8, x7, x1, x3) + +inst_440: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x400; + valaddr_reg:x4; val_offset:826*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 826*FLEN/8, x7, x1, x3) + +inst_441: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x8400; + valaddr_reg:x4; val_offset:828*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 828*FLEN/8, x7, x1, x3) + +inst_442: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x401; + valaddr_reg:x4; val_offset:830*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 830*FLEN/8, x7, x1, x3) + +inst_443: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x8455; + valaddr_reg:x4; val_offset:832*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 832*FLEN/8, x7, x1, x3) + +inst_444: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x7bff; + valaddr_reg:x4; val_offset:834*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 834*FLEN/8, x7, x1, x3) + +inst_445: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xfbff; + valaddr_reg:x4; val_offset:836*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 836*FLEN/8, x7, x1, x3) + +inst_446: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x7c00; + valaddr_reg:x4; val_offset:838*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 838*FLEN/8, x7, x1, x3) + +inst_447: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xfc00; + valaddr_reg:x4; val_offset:840*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 840*FLEN/8, x7, x1, x3) + +inst_448: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x7e00; + valaddr_reg:x4; val_offset:842*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 842*FLEN/8, x7, x1, x3) + +inst_449: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xfe00; + valaddr_reg:x4; val_offset:844*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 844*FLEN/8, x7, x1, x3) + +inst_450: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x7e01; + valaddr_reg:x4; val_offset:846*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 846*FLEN/8, x7, x1, x3) + +inst_451: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xfe55; + valaddr_reg:x4; val_offset:848*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 848*FLEN/8, x7, x1, x3) + +inst_452: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x7c01; + valaddr_reg:x4; val_offset:850*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 850*FLEN/8, x7, x1, x3) + +inst_453: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xfd55; + valaddr_reg:x4; val_offset:852*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 852*FLEN/8, x7, x1, x3) + +inst_454: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x3c00; + valaddr_reg:x4; val_offset:854*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 854*FLEN/8, x7, x1, x3) + +inst_455: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xbc00; + valaddr_reg:x4; val_offset:856*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 856*FLEN/8, x7, x1, x3) + +inst_456: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x0; + valaddr_reg:x4; val_offset:858*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 858*FLEN/8, x7, x1, x3) + +inst_457: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x8000; + valaddr_reg:x4; val_offset:860*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 860*FLEN/8, x7, x1, x3) + +inst_458: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x1; + valaddr_reg:x4; val_offset:862*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 862*FLEN/8, x7, x1, x3) + +inst_459: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x8001; + valaddr_reg:x4; val_offset:864*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 864*FLEN/8, x7, x1, x3) + +inst_460: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x2; + valaddr_reg:x4; val_offset:866*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 866*FLEN/8, x7, x1, x3) + +inst_461: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x83fe; + valaddr_reg:x4; val_offset:868*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 868*FLEN/8, x7, x1, x3) + +inst_462: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x3ff; + valaddr_reg:x4; val_offset:870*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 870*FLEN/8, x7, x1, x3) + +inst_463: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x83ff; + valaddr_reg:x4; val_offset:872*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 872*FLEN/8, x7, x1, x3) + +inst_464: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x400; + valaddr_reg:x4; val_offset:874*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 874*FLEN/8, x7, x1, x3) + +inst_465: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x8400; + valaddr_reg:x4; val_offset:876*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 876*FLEN/8, x7, x1, x3) + +inst_466: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x401; + valaddr_reg:x4; val_offset:878*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 878*FLEN/8, x7, x1, x3) + +inst_467: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x8455; + valaddr_reg:x4; val_offset:880*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 880*FLEN/8, x7, x1, x3) + +inst_468: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x7bff; + valaddr_reg:x4; val_offset:882*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 882*FLEN/8, x7, x1, x3) + +inst_469: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xfbff; + valaddr_reg:x4; val_offset:884*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 884*FLEN/8, x7, x1, x3) + +inst_470: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x7c00; + valaddr_reg:x4; val_offset:886*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 886*FLEN/8, x7, x1, x3) + +inst_471: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xfc00; + valaddr_reg:x4; val_offset:888*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 888*FLEN/8, x7, x1, x3) + +inst_472: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x7e00; + valaddr_reg:x4; val_offset:890*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 890*FLEN/8, x7, x1, x3) + +inst_473: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xfe00; + valaddr_reg:x4; val_offset:892*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 892*FLEN/8, x7, x1, x3) + +inst_474: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x7e01; + valaddr_reg:x4; val_offset:894*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 894*FLEN/8, x7, x1, x3) + +inst_475: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xfe55; + valaddr_reg:x4; val_offset:896*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 896*FLEN/8, x7, x1, x3) + +inst_476: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x7c01; + valaddr_reg:x4; val_offset:898*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 898*FLEN/8, x7, x1, x3) + +inst_477: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xfd55; + valaddr_reg:x4; val_offset:900*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 900*FLEN/8, x7, x1, x3) + +inst_478: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x3c00; + valaddr_reg:x4; val_offset:902*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 902*FLEN/8, x7, x1, x3) + +inst_479: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xbc00; + valaddr_reg:x4; val_offset:904*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 904*FLEN/8, x7, x1, x3) + +inst_480: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x0; + valaddr_reg:x4; val_offset:906*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 906*FLEN/8, x7, x1, x3) + +inst_481: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x8000; + valaddr_reg:x4; val_offset:908*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 908*FLEN/8, x7, x1, x3) + +inst_482: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x1; + valaddr_reg:x4; val_offset:910*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 910*FLEN/8, x7, x1, x3) + +inst_483: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x8001; + valaddr_reg:x4; val_offset:912*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 912*FLEN/8, x7, x1, x3) + +inst_484: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x2; + valaddr_reg:x4; val_offset:914*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 914*FLEN/8, x7, x1, x3) + +inst_485: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x83fe; + valaddr_reg:x4; val_offset:916*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 916*FLEN/8, x7, x1, x3) + +inst_486: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x3ff; + valaddr_reg:x4; val_offset:918*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 918*FLEN/8, x7, x1, x3) + +inst_487: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x83ff; + valaddr_reg:x4; val_offset:920*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 920*FLEN/8, x7, x1, x3) + +inst_488: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x400; + valaddr_reg:x4; val_offset:922*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 922*FLEN/8, x7, x1, x3) + +inst_489: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x8400; + valaddr_reg:x4; val_offset:924*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 924*FLEN/8, x7, x1, x3) + +inst_490: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x401; + valaddr_reg:x4; val_offset:926*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 926*FLEN/8, x7, x1, x3) + +inst_491: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x8455; + valaddr_reg:x4; val_offset:928*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 928*FLEN/8, x7, x1, x3) + +inst_492: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x7bff; + valaddr_reg:x4; val_offset:930*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 930*FLEN/8, x7, x1, x3) + +inst_493: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xfbff; + valaddr_reg:x4; val_offset:932*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 932*FLEN/8, x7, x1, x3) + +inst_494: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x7c00; + valaddr_reg:x4; val_offset:934*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 934*FLEN/8, x7, x1, x3) + +inst_495: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xfc00; + valaddr_reg:x4; val_offset:936*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 936*FLEN/8, x7, x1, x3) + +inst_496: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x7e00; + valaddr_reg:x4; val_offset:938*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 938*FLEN/8, x7, x1, x3) + +inst_497: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xfe00; + valaddr_reg:x4; val_offset:940*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 940*FLEN/8, x7, x1, x3) + +inst_498: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x7e01; + valaddr_reg:x4; val_offset:942*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 942*FLEN/8, x7, x1, x3) + +inst_499: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xfe55; + valaddr_reg:x4; val_offset:944*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 944*FLEN/8, x7, x1, x3) + +inst_500: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x7c01; + valaddr_reg:x4; val_offset:946*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 946*FLEN/8, x7, x1, x3) + +inst_501: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xfd55; + valaddr_reg:x4; val_offset:948*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 948*FLEN/8, x7, x1, x3) + +inst_502: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x3c00; + valaddr_reg:x4; val_offset:950*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 950*FLEN/8, x7, x1, x3) + +inst_503: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xbc00; + valaddr_reg:x4; val_offset:952*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 952*FLEN/8, x7, x1, x3) + +inst_504: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x0; + valaddr_reg:x4; val_offset:954*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 954*FLEN/8, x7, x1, x3) + +inst_505: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x8000; + valaddr_reg:x4; val_offset:956*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 956*FLEN/8, x7, x1, x3) + +inst_506: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x1; + valaddr_reg:x4; val_offset:958*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 958*FLEN/8, x7, x1, x3) + +inst_507: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x8001; + valaddr_reg:x4; val_offset:960*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 960*FLEN/8, x7, x1, x3) + +inst_508: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x2; + valaddr_reg:x4; val_offset:962*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 962*FLEN/8, x7, x1, x3) + +inst_509: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x83fe; + valaddr_reg:x4; val_offset:964*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 964*FLEN/8, x7, x1, x3) + +inst_510: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x3ff; + valaddr_reg:x4; val_offset:966*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 966*FLEN/8, x7, x1, x3) + +inst_511: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x83ff; + valaddr_reg:x4; val_offset:968*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 968*FLEN/8, x7, x1, x3) + +inst_512: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x400; + valaddr_reg:x4; val_offset:970*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 970*FLEN/8, x7, x1, x3) + +inst_513: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x8400; + valaddr_reg:x4; val_offset:972*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 972*FLEN/8, x7, x1, x3) + +inst_514: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x401; + valaddr_reg:x4; val_offset:974*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 974*FLEN/8, x7, x1, x3) + +inst_515: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x8455; + valaddr_reg:x4; val_offset:976*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 976*FLEN/8, x7, x1, x3) + +inst_516: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x7bff; + valaddr_reg:x4; val_offset:978*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 978*FLEN/8, x7, x1, x3) + +inst_517: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xfbff; + valaddr_reg:x4; val_offset:980*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 980*FLEN/8, x7, x1, x3) + +inst_518: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x7c00; + valaddr_reg:x4; val_offset:982*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 982*FLEN/8, x7, x1, x3) + +inst_519: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xfc00; + valaddr_reg:x4; val_offset:984*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 984*FLEN/8, x7, x1, x3) + +inst_520: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x7e00; + valaddr_reg:x4; val_offset:986*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 986*FLEN/8, x7, x1, x3) + +inst_521: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xfe00; + valaddr_reg:x4; val_offset:988*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 988*FLEN/8, x7, x1, x3) + +inst_522: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x7e01; + valaddr_reg:x4; val_offset:990*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 990*FLEN/8, x7, x1, x3) + +inst_523: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xfe55; + valaddr_reg:x4; val_offset:992*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 992*FLEN/8, x7, x1, x3) + +inst_524: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x7c01; + valaddr_reg:x4; val_offset:994*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 994*FLEN/8, x7, x1, x3) + +inst_525: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xfd55; + valaddr_reg:x4; val_offset:996*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 996*FLEN/8, x7, x1, x3) + +inst_526: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x3c00; + valaddr_reg:x4; val_offset:998*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 998*FLEN/8, x7, x1, x3) + +inst_527: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xbc00; + valaddr_reg:x4; val_offset:1000*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 1000*FLEN/8, x7, x1, x3) + +inst_528: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x0; + valaddr_reg:x4; val_offset:1002*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 1002*FLEN/8, x7, x1, x3) + +inst_529: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x8000; + valaddr_reg:x4; val_offset:1004*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 1004*FLEN/8, x7, x1, x3) + +inst_530: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x1; + valaddr_reg:x4; val_offset:1006*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 1006*FLEN/8, x7, x1, x3) + +inst_531: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x8001; + valaddr_reg:x4; val_offset:1008*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 1008*FLEN/8, x7, x1, x3) + +inst_532: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2; + valaddr_reg:x4; val_offset:1010*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 1010*FLEN/8, x7, x1, x3) + +inst_533: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x83fe; + valaddr_reg:x4; val_offset:1012*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 1012*FLEN/8, x7, x1, x3) + +inst_534: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3ff; + valaddr_reg:x4; val_offset:1014*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 1014*FLEN/8, x7, x1, x3) + +inst_535: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x83ff; + valaddr_reg:x4; val_offset:1016*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 1016*FLEN/8, x7, x1, x3) + +inst_536: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x400; + valaddr_reg:x4; val_offset:1018*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 1018*FLEN/8, x7, x1, x3) + +inst_537: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x8400; + valaddr_reg:x4; val_offset:1020*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 1020*FLEN/8, x7, x1, x3) + +inst_538: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x401; + valaddr_reg:x4; val_offset:1022*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 1022*FLEN/8, x7, x1, x3) + +inst_539: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x8455; + valaddr_reg:x4; val_offset:1024*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 1024*FLEN/8, x7, x1, x3) + +inst_540: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7bff; + valaddr_reg:x4; val_offset:1026*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 1026*FLEN/8, x7, x1, x3) + +inst_541: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xfbff; + valaddr_reg:x4; val_offset:1028*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 1028*FLEN/8, x7, x1, x3) + +inst_542: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7c00; + valaddr_reg:x4; val_offset:1030*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 1030*FLEN/8, x7, x1, x3) +RVTEST_SIGBASE(x1,signature_x1_4) + +inst_543: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xfc00; + valaddr_reg:x4; val_offset:1032*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 1032*FLEN/8, x7, x1, x3) + +inst_544: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7e00; + valaddr_reg:x4; val_offset:1034*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 1034*FLEN/8, x7, x1, x3) + +inst_545: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xfe00; + valaddr_reg:x4; val_offset:1036*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 1036*FLEN/8, x7, x1, x3) + +inst_546: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7e01; + valaddr_reg:x4; val_offset:1038*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 1038*FLEN/8, x7, x1, x3) + +inst_547: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xfe55; + valaddr_reg:x4; val_offset:1040*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 1040*FLEN/8, x7, x1, x3) + +inst_548: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7c01; + valaddr_reg:x4; val_offset:1042*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 1042*FLEN/8, x7, x1, x3) + +inst_549: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xfd55; + valaddr_reg:x4; val_offset:1044*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 1044*FLEN/8, x7, x1, x3) + +inst_550: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3c00; + valaddr_reg:x4; val_offset:1046*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 1046*FLEN/8, x7, x1, x3) + +inst_551: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xbc00; + valaddr_reg:x4; val_offset:1048*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 1048*FLEN/8, x7, x1, x3) + +inst_552: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x0; + valaddr_reg:x4; val_offset:1050*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 1050*FLEN/8, x7, x1, x3) + +inst_553: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x8000; + valaddr_reg:x4; val_offset:1052*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 1052*FLEN/8, x7, x1, x3) + +inst_554: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x1; + valaddr_reg:x4; val_offset:1054*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 1054*FLEN/8, x7, x1, x3) + +inst_555: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x8001; + valaddr_reg:x4; val_offset:1056*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 1056*FLEN/8, x7, x1, x3) + +inst_556: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x2; + valaddr_reg:x4; val_offset:1058*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 1058*FLEN/8, x7, x1, x3) + +inst_557: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x83fe; + valaddr_reg:x4; val_offset:1060*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 1060*FLEN/8, x7, x1, x3) + +inst_558: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x3ff; + valaddr_reg:x4; val_offset:1062*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 1062*FLEN/8, x7, x1, x3) + +inst_559: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x83ff; + valaddr_reg:x4; val_offset:1064*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 1064*FLEN/8, x7, x1, x3) + +inst_560: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x400; + valaddr_reg:x4; val_offset:1066*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 1066*FLEN/8, x7, x1, x3) + +inst_561: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x8400; + valaddr_reg:x4; val_offset:1068*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 1068*FLEN/8, x7, x1, x3) + +inst_562: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x401; + valaddr_reg:x4; val_offset:1070*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 1070*FLEN/8, x7, x1, x3) + +inst_563: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x8455; + valaddr_reg:x4; val_offset:1072*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 1072*FLEN/8, x7, x1, x3) + +inst_564: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x7bff; + valaddr_reg:x4; val_offset:1074*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 1074*FLEN/8, x7, x1, x3) + +inst_565: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xfbff; + valaddr_reg:x4; val_offset:1076*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 1076*FLEN/8, x7, x1, x3) + +inst_566: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x7c00; + valaddr_reg:x4; val_offset:1078*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 1078*FLEN/8, x7, x1, x3) + +inst_567: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xfc00; + valaddr_reg:x4; val_offset:1080*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 1080*FLEN/8, x7, x1, x3) + +inst_568: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x7e00; + valaddr_reg:x4; val_offset:1082*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 1082*FLEN/8, x7, x1, x3) + +inst_569: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xfe00; + valaddr_reg:x4; val_offset:1084*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 1084*FLEN/8, x7, x1, x3) + +inst_570: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x7e01; + valaddr_reg:x4; val_offset:1086*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 1086*FLEN/8, x7, x1, x3) + +inst_571: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xfe55; + valaddr_reg:x4; val_offset:1088*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 1088*FLEN/8, x7, x1, x3) + +inst_572: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x7c01; + valaddr_reg:x4; val_offset:1090*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 1090*FLEN/8, x7, x1, x3) + +inst_573: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xfd55; + valaddr_reg:x4; val_offset:1092*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 1092*FLEN/8, x7, x1, x3) + +inst_574: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x3c00; + valaddr_reg:x4; val_offset:1094*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 1094*FLEN/8, x7, x1, x3) + +inst_575: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbc00; + valaddr_reg:x4; val_offset:1096*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 1096*FLEN/8, x7, x1, x3) + +inst_576: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x0; + valaddr_reg:x4; val_offset:1098*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 1098*FLEN/8, x7, x1, x3) + +inst_577: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x8001; + valaddr_reg:x4; val_offset:1100*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 1100*FLEN/8, x7, x1, x3) + +inst_578: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x400; + valaddr_reg:x4; val_offset:1102*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 1102*FLEN/8, x7, x1, x3) + +inst_579: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xfbff; + valaddr_reg:x4; val_offset:1104*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 1104*FLEN/8, x7, x1, x3) + +inst_580: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsgnjx.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x2; + valaddr_reg:x4; val_offset:1106*FLEN/8; fcsr: 0; + correctval:??; testreg:x3 +*/ +TEST_FPRR_OP_NRM(fsgnjx.h, x31, x30, x29, 0, 0, x4, 1106*FLEN/8, x7, x1, x3) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(1,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(2,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(1023,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(1024,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(1025,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31743,32,FLEN) +test_dataset_1: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31744,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32256,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32257,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31745,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(15360,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1,32,FLEN) +test_dataset_2: +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(1023,16,FLEN) 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+NAN_BOXED(32257,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(2,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x3_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x3_1: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x13_0: + .fill 34*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_0: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_2: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_3: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_4: + .fill 76*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fsqrt_b1-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fsqrt_b1-01.S new file mode 100644 index 000000000..7e368b925 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fsqrt_b1-01.S @@ -0,0 +1,363 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 05:27:49 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fsqrt.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fsqrt.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fsqrt_b1 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fsqrt_b1) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x2,test_dataset_0) +RVTEST_SIGBASE(x4,signature_x4_1) + +inst_0: +// rs1 == rd, rs1==x22, rd==x22,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x22; dest:x22; op1val:0x0; valaddr_reg:x2; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x22, x22, dyn, 0, 0, x2, 0*FLEN/8, x9, x4, x5) + +inst_1: +// rs1 != rd, rs1==x3, rd==x18,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fsqrt.h ; op1:x3; dest:x18; op1val:0x8000; valaddr_reg:x2; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x18, x3, dyn, 0, 0, x2, 1*FLEN/8, x9, x4, x5) + +inst_2: +// rs1==x23, rd==x30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x23; dest:x30; op1val:0x1; valaddr_reg:x2; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x30, x23, dyn, 0, 0, x2, 2*FLEN/8, x9, x4, x5) + +inst_3: +// rs1==x29, rd==x0,fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fsqrt.h ; op1:x29; dest:x0; op1val:0x8001; valaddr_reg:x2; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x0, x29, dyn, 0, 0, x2, 3*FLEN/8, x9, x4, x5) + +inst_4: +// rs1==x30, rd==x31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x30; dest:x31; op1val:0x2; valaddr_reg:x2; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x31, x30, dyn, 0, 0, x2, 4*FLEN/8, x9, x4, x5) + +inst_5: +// rs1==x1, rd==x15,fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fsqrt.h ; op1:x1; dest:x15; op1val:0x83fe; valaddr_reg:x2; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x15, x1, dyn, 0, 0, x2, 5*FLEN/8, x9, x4, x5) + +inst_6: +// rs1==x31, rd==x21,fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x31; dest:x21; op1val:0x3ff; valaddr_reg:x2; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x21, x31, dyn, 0, 0, x2, 6*FLEN/8, x9, x4, x5) + +inst_7: +// rs1==x20, rd==x10,fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fsqrt.h ; op1:x20; dest:x10; op1val:0x83ff; valaddr_reg:x2; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x10, x20, dyn, 0, 0, x2, 7*FLEN/8, x9, x4, x5) + +inst_8: +// rs1==x7, rd==x13,fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x7; dest:x13; op1val:0x400; valaddr_reg:x2; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x13, x7, dyn, 0, 0, x2, 8*FLEN/8, x9, x4, x5) + +inst_9: +// rs1==x11, rd==x27,fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fsqrt.h ; op1:x11; dest:x27; op1val:0x8400; valaddr_reg:x2; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x27, x11, dyn, 0, 0, x2, 9*FLEN/8, x9, x4, x5) + +inst_10: +// rs1==x15, rd==x12,fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x15; dest:x12; op1val:0x401; valaddr_reg:x2; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x12, x15, dyn, 0, 0, x2, 10*FLEN/8, x9, x4, x5) + +inst_11: +// rs1==x25, rd==x6,fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fsqrt.h ; op1:x25; dest:x6; op1val:0x8455; valaddr_reg:x2; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x6, x25, dyn, 0, 0, x2, 11*FLEN/8, x9, x4, x5) + +inst_12: +// rs1==x14, rd==x17,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x14; dest:x17; op1val:0x7bff; valaddr_reg:x2; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x17, x14, dyn, 0, 0, x2, 12*FLEN/8, x9, x4, x5) + +inst_13: +// rs1==x16, rd==x8,fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fsqrt.h ; op1:x16; dest:x8; op1val:0xfbff; valaddr_reg:x2; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x8, x16, dyn, 0, 0, x2, 13*FLEN/8, x9, x4, x5) + +inst_14: +// rs1==x19, rd==x1,fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x19; dest:x1; op1val:0x7c00; valaddr_reg:x2; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x1, x19, dyn, 0, 0, x2, 14*FLEN/8, x9, x4, x5) +RVTEST_VALBASEUPD(x12,test_dataset_1) + +inst_15: +// rs1==x26, rd==x2,fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fsqrt.h ; op1:x26; dest:x2; op1val:0xfc00; valaddr_reg:x12; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x2, x26, dyn, 0, 0, x12, 0*FLEN/8, x21, x4, x5) + +inst_16: +// rs1==x28, rd==x7,fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x28; dest:x7; op1val:0x7e00; valaddr_reg:x12; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x15; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x7, x28, dyn, 0, 0, x12, 1*FLEN/8, x21, x4, x15) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_17: +// rs1==x9, rd==x19,fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fsqrt.h ; op1:x9; dest:x19; op1val:0xfe00; valaddr_reg:x12; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x15; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x19, x9, dyn, 0, 0, x12, 2*FLEN/8, x21, x1, x15) + +inst_18: +// rs1==x13, rd==x23,fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x13; dest:x23; op1val:0x7e01; valaddr_reg:x12; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x15; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x23, x13, dyn, 0, 0, x12, 3*FLEN/8, x21, x1, x15) + +inst_19: +// rs1==x6, rd==x11,fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fsqrt.h ; op1:x6; dest:x11; op1val:0xfe55; valaddr_reg:x12; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x15; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x11, x6, dyn, 0, 0, x12, 4*FLEN/8, x21, x1, x15) + +inst_20: +// rs1==x10, rd==x16,fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x10; dest:x16; op1val:0x7c01; valaddr_reg:x12; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x15; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x16, x10, dyn, 0, 0, x12, 5*FLEN/8, x21, x1, x15) + +inst_21: +// rs1==x27, rd==x28,fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fsqrt.h ; op1:x27; dest:x28; op1val:0xfd55; valaddr_reg:x12; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x15; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x28, x27, dyn, 0, 0, x12, 6*FLEN/8, x21, x1, x15) + +inst_22: +// rs1==x8, rd==x9,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x8; dest:x9; op1val:0x3c00; valaddr_reg:x12; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x15; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x9, x8, dyn, 0, 0, x12, 7*FLEN/8, x21, x1, x15) + +inst_23: +// rs1==x4, rd==x14,fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fsqrt.h ; op1:x4; dest:x14; op1val:0xbc00; valaddr_reg:x12; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x15; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x14, x4, dyn, 0, 0, x12, 8*FLEN/8, x21, x1, x15) + +inst_24: +// rs1==x2, rd==x26, +/* opcode: fsqrt.h ; op1:x2; dest:x26; op1val:0x0; valaddr_reg:x12; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x15; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x26, x2, dyn, 0, 0, x12, 9*FLEN/8, x21, x1, x15) + +inst_25: +// rs1==x5, rd==x20, +/* opcode: fsqrt.h ; op1:x5; dest:x20; op1val:0x0; valaddr_reg:x12; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x15; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x20, x5, dyn, 0, 0, x12, 10*FLEN/8, x21, x1, x15) + +inst_26: +// rs1==x24, rd==x3, +/* opcode: fsqrt.h ; op1:x24; dest:x3; op1val:0x0; valaddr_reg:x12; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x15; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x3, x24, dyn, 0, 0, x12, 11*FLEN/8, x21, x1, x15) + +inst_27: +// rs1==x0, rd==x24, +/* opcode: fsqrt.h ; op1:x0; dest:x24; op1val:0x0; valaddr_reg:x12; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x15; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x24, x0, dyn, 0, 0, x12, 12*FLEN/8, x21, x1, x15) + +inst_28: +// rs1==x17, rd==x25, +/* opcode: fsqrt.h ; op1:x17; dest:x25; op1val:0x0; valaddr_reg:x12; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x15; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x25, x17, dyn, 0, 0, x12, 13*FLEN/8, x21, x1, x15) + +inst_29: +// rs1==x18, rd==x29, +/* opcode: fsqrt.h ; op1:x18; dest:x29; op1val:0x0; valaddr_reg:x12; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x15; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x29, x18, dyn, 0, 0, x12, 14*FLEN/8, x21, x1, x15) +RVTEST_VALBASEUPD(x3,test_dataset_2) + +inst_30: +// rs1==x12, rd==x4, +/* opcode: fsqrt.h ; op1:x12; dest:x4; op1val:0x0; valaddr_reg:x3; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x15; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x4, x12, dyn, 0, 0, x3, 0*FLEN/8, x6, x1, x15) + +inst_31: +// rs1==x21, rd==x5, +/* opcode: fsqrt.h ; op1:x21; dest:x5; op1val:0x0; valaddr_reg:x3; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x15; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x5, x21, dyn, 0, 0, x3, 1*FLEN/8, x6, x1, x15) + +inst_32: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fsqrt.h ; op1:x30; dest:x31; op1val:0x8001; valaddr_reg:x3; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x31, x30, dyn, 0, 0, x3, 2*FLEN/8, x6, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1,32,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(2,32,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(1023,32,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(1024,32,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(1025,32,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31744,32,FLEN) +test_dataset_1: +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(32256,32,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(32257,32,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(31745,32,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(15360,32,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +test_dataset_2: +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32769,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x4_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x4_1: + .fill 34*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_0: + .fill 32*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fsqrt_b2-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fsqrt_b2-01.S new file mode 100644 index 000000000..8e1839645 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fsqrt_b2-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 05:27:49 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fsqrt.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fsqrt.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fsqrt_b2 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fsqrt_b2) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x19,test_dataset_0) +RVTEST_SIGBASE(x5,signature_x5_1) + +inst_0: +// rs1 == rd, rs1==x27, rd==x27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x27; dest:x27; op1val:0x0; valaddr_reg:x19; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x27, x27, dyn, 0, 0, x19, 0*FLEN/8, x21, x5, x13) + +inst_1: +// rs1 != rd, rs1==x3, rd==x17,fs1 == 0 and fe1 == 0x0f and fm1 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x3; dest:x17; op1val:0x3c02; valaddr_reg:x19; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x17, x3, dyn, 0, 0, x19, 1*FLEN/8, x21, x5, x13) + +inst_2: +// rs1==x2, rd==x18,fs1 == 0 and fe1 == 0x0f and fm1 == 0x004 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x2; dest:x18; op1val:0x3c04; valaddr_reg:x19; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x18, x2, dyn, 0, 0, x19, 2*FLEN/8, x21, x5, x13) + +inst_3: +// rs1==x20, rd==x11,fs1 == 0 and fe1 == 0x0f and fm1 == 0x008 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x20; dest:x11; op1val:0x3c08; valaddr_reg:x19; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x11, x20, dyn, 0, 0, x19, 3*FLEN/8, x21, x5, x13) + +inst_4: +// rs1==x22, rd==x23,fs1 == 0 and fe1 == 0x0f and fm1 == 0x010 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x22; dest:x23; op1val:0x3c10; valaddr_reg:x19; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x23, x22, dyn, 0, 0, x19, 4*FLEN/8, x21, x5, x13) + +inst_5: +// rs1==x24, rd==x14,fs1 == 0 and fe1 == 0x0f and fm1 == 0x020 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x24; dest:x14; op1val:0x3c20; valaddr_reg:x19; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x14, x24, dyn, 0, 0, x19, 5*FLEN/8, x21, x5, x13) + +inst_6: +// rs1==x28, rd==x4,fs1 == 0 and fe1 == 0x0f and fm1 == 0x041 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x28; dest:x4; op1val:0x3c41; valaddr_reg:x19; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x4, x28, dyn, 0, 0, x19, 6*FLEN/8, x21, x5, x13) + +inst_7: +// rs1==x9, rd==x1,fs1 == 0 and fe1 == 0x0f and fm1 == 0x084 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x9; dest:x1; op1val:0x3c84; valaddr_reg:x19; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x1, x9, dyn, 0, 0, x19, 7*FLEN/8, x21, x5, x13) + +inst_8: +// rs1==x17, rd==x7,fs1 == 0 and fe1 == 0x0f and fm1 == 0x110 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x17; dest:x7; op1val:0x3d10; valaddr_reg:x19; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x7, x17, dyn, 0, 0, x19, 8*FLEN/8, x21, x5, x13) + +inst_9: +// rs1==x15, rd==x8,fs1 == 0 and fe1 == 0x0f and fm1 == 0x240 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x15; dest:x8; op1val:0x3e40; valaddr_reg:x19; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x8, x15, dyn, 0, 0, x19, 9*FLEN/8, x21, x5, x13) + +inst_10: +// rs1==x4, rd==x20,fs1 == 0 and fe1 == 0x10 and fm1 == 0x080 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x4; dest:x20; op1val:0x4080; valaddr_reg:x19; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x20, x4, dyn, 0, 0, x19, 10*FLEN/8, x21, x5, x13) + +inst_11: +// rs1==x10, rd==x28,fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x10; dest:x28; op1val:0x7c00; valaddr_reg:x19; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x28, x10, dyn, 0, 0, x19, 11*FLEN/8, x21, x5, x13) + +inst_12: +// rs1==x6, rd==x31, +/* opcode: fsqrt.h ; op1:x6; dest:x31; op1val:0x0; valaddr_reg:x19; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x31, x6, dyn, 0, 0, x19, 12*FLEN/8, x21, x5, x13) + +inst_13: +// rs1==x7, rd==x0, +/* opcode: fsqrt.h ; op1:x7; dest:x0; op1val:0x0; valaddr_reg:x19; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x0, x7, dyn, 0, 0, x19, 13*FLEN/8, x21, x5, x13) + +inst_14: +// rs1==x11, rd==x26, +/* opcode: fsqrt.h ; op1:x11; dest:x26; op1val:0x0; valaddr_reg:x19; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x26, x11, dyn, 0, 0, x19, 14*FLEN/8, x21, x5, x13) + +inst_15: +// rs1==x23, rd==x9, +/* opcode: fsqrt.h ; op1:x23; dest:x9; op1val:0x0; valaddr_reg:x19; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x9, x23, dyn, 0, 0, x19, 15*FLEN/8, x21, x5, x13) + +inst_16: +// rs1==x16, rd==x12, +/* opcode: fsqrt.h ; op1:x16; dest:x12; op1val:0x0; valaddr_reg:x19; +val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x12, x16, dyn, 0, 0, x19, 16*FLEN/8, x21, x5, x13) +RVTEST_VALBASEUPD(x7,test_dataset_1) + +inst_17: +// rs1==x14, rd==x22, +/* opcode: fsqrt.h ; op1:x14; dest:x22; op1val:0x0; valaddr_reg:x7; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x22, x14, dyn, 0, 0, x7, 0*FLEN/8, x9, x5, x13) + +inst_18: +// rs1==x21, rd==x24, +/* opcode: fsqrt.h ; op1:x21; dest:x24; op1val:0x0; valaddr_reg:x7; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x24, x21, dyn, 0, 0, x7, 1*FLEN/8, x9, x5, x13) + +inst_19: +// rs1==x26, rd==x2, +/* opcode: fsqrt.h ; op1:x26; dest:x2; op1val:0x0; valaddr_reg:x7; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x2, x26, dyn, 0, 0, x7, 2*FLEN/8, x9, x5, x13) + +inst_20: +// rs1==x8, rd==x29, +/* opcode: fsqrt.h ; op1:x8; dest:x29; op1val:0x0; valaddr_reg:x7; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x29, x8, dyn, 0, 0, x7, 3*FLEN/8, x9, x5, x13) + +inst_21: +// rs1==x31, rd==x30, +/* opcode: fsqrt.h ; op1:x31; dest:x30; op1val:0x0; valaddr_reg:x7; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x30, x31, dyn, 0, 0, x7, 4*FLEN/8, x9, x5, x4) +RVTEST_SIGBASE(x2,signature_x2_0) + +inst_22: +// rs1==x25, rd==x10, +/* opcode: fsqrt.h ; op1:x25; dest:x10; op1val:0x0; valaddr_reg:x7; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x10, x25, dyn, 0, 0, x7, 5*FLEN/8, x9, x2, x4) + +inst_23: +// rs1==x12, rd==x6, +/* opcode: fsqrt.h ; op1:x12; dest:x6; op1val:0x0; valaddr_reg:x7; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x6, x12, dyn, 0, 0, x7, 6*FLEN/8, x9, x2, x4) + +inst_24: +// rs1==x29, rd==x15, +/* opcode: fsqrt.h ; op1:x29; dest:x15; op1val:0x0; valaddr_reg:x7; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x15, x29, dyn, 0, 0, x7, 7*FLEN/8, x9, x2, x4) + +inst_25: +// rs1==x1, rd==x13, +/* opcode: fsqrt.h ; op1:x1; dest:x13; op1val:0x0; valaddr_reg:x7; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x13, x1, dyn, 0, 0, x7, 8*FLEN/8, x9, x2, x4) + +inst_26: +// rs1==x0, rd==x25, +/* opcode: fsqrt.h ; op1:x0; dest:x25; op1val:0x0; valaddr_reg:x7; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x25, x0, dyn, 0, 0, x7, 9*FLEN/8, x9, x2, x4) + +inst_27: +// rs1==x19, rd==x3, +/* opcode: fsqrt.h ; op1:x19; dest:x3; op1val:0x0; valaddr_reg:x7; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x3, x19, dyn, 0, 0, x7, 10*FLEN/8, x9, x2, x4) + +inst_28: +// rs1==x18, rd==x21, +/* opcode: fsqrt.h ; op1:x18; dest:x21; op1val:0x0; valaddr_reg:x7; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x21, x18, dyn, 0, 0, x7, 11*FLEN/8, x9, x2, x4) + +inst_29: +// rs1==x30, rd==x5, +/* opcode: fsqrt.h ; op1:x30; dest:x5; op1val:0x0; valaddr_reg:x7; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x5, x30, dyn, 0, 0, x7, 12*FLEN/8, x9, x2, x4) + +inst_30: +// rs1==x5, rd==x16, +/* opcode: fsqrt.h ; op1:x5; dest:x16; op1val:0x0; valaddr_reg:x7; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x16, x5, dyn, 0, 0, x7, 13*FLEN/8, x9, x2, x4) + +inst_31: +// rs1==x13, rd==x19, +/* opcode: fsqrt.h ; op1:x13; dest:x19; op1val:0x0; valaddr_reg:x7; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x19, x13, dyn, 0, 0, x7, 14*FLEN/8, x9, x2, x4) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(15362,32,FLEN) +NAN_BOXED(15364,32,FLEN) +NAN_BOXED(15368,32,FLEN) +NAN_BOXED(15376,32,FLEN) +NAN_BOXED(15392,32,FLEN) +NAN_BOXED(15425,32,FLEN) +NAN_BOXED(15492,32,FLEN) +NAN_BOXED(15632,32,FLEN) +NAN_BOXED(15936,32,FLEN) +NAN_BOXED(16512,32,FLEN) +NAN_BOXED(31744,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +test_dataset_1: +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x5_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x5_1: + .fill 44*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_0: + .fill 20*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fsqrt_b20-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fsqrt_b20-01.S new file mode 100644 index 000000000..b4e6108a7 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fsqrt_b20-01.S @@ -0,0 +1,361 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 05:27:49 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fsqrt.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fsqrt.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fsqrt_b20 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fsqrt_b20) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x10,test_dataset_0) +RVTEST_SIGBASE(x4,signature_x4_1) + +inst_0: +// rs1 == rd, rs1==x5, rd==x5,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x5; dest:x5; op1val:0x7bff; valaddr_reg:x10; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x5, x5, dyn, 0, 0, x10, 0*FLEN/8, x11, x4, x9) + +inst_1: +// rs1 != rd, rs1==x29, rd==x25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x29; dest:x25; op1val:0x0; valaddr_reg:x10; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x25, x29, dyn, 0, 0, x10, 1*FLEN/8, x11, x4, x9) + +inst_2: +// rs1==x21, rd==x28,fs1 == 0 and fe1 == 0x18 and fm1 == 0x080 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x21; dest:x28; op1val:0x6080; valaddr_reg:x10; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x28, x21, dyn, 0, 0, x10, 2*FLEN/8, x11, x4, x9) + +inst_3: +// rs1==x31, rd==x7,fs1 == 0 and fe1 == 0x19 and fm1 == 0x110 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x31; dest:x7; op1val:0x6510; valaddr_reg:x10; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x7, x31, dyn, 0, 0, x10, 3*FLEN/8, x11, x4, x9) + +inst_4: +// rs1==x23, rd==x0,fs1 == 0 and fe1 == 0x00 and fm1 == 0x144 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x23; dest:x0; op1val:0x144; valaddr_reg:x10; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x0, x23, dyn, 0, 0, x10, 4*FLEN/8, x11, x4, x9) + +inst_5: +// rs1==x15, rd==x27,fs1 == 0 and fe1 == 0x04 and fm1 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x15; dest:x27; op1val:0x13c0; valaddr_reg:x10; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x27, x15, dyn, 0, 0, x10, 5*FLEN/8, x11, x4, x9) + +inst_6: +// rs1==x6, rd==x8,fs1 == 0 and fe1 == 0x0f and fm1 == 0x3e9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x6; dest:x8; op1val:0x3fe9; valaddr_reg:x10; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x8, x6, dyn, 0, 0, x10, 6*FLEN/8, x11, x4, x9) + +inst_7: +// rs1==x12, rd==x14,fs1 == 0 and fe1 == 0x19 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x12; dest:x14; op1val:0x6400; valaddr_reg:x10; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x14, x12, dyn, 0, 0, x10, 7*FLEN/8, x11, x4, x9) + +inst_8: +// rs1==x22, rd==x1, +/* opcode: fsqrt.h ; op1:x22; dest:x1; op1val:0x0; valaddr_reg:x10; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x1, x22, dyn, 0, 0, x10, 8*FLEN/8, x11, x4, x9) + +inst_9: +// rs1==x26, rd==x17, +/* opcode: fsqrt.h ; op1:x26; dest:x17; op1val:0x0; valaddr_reg:x10; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x17, x26, dyn, 0, 0, x10, 9*FLEN/8, x11, x4, x9) + +inst_10: +// rs1==x28, rd==x15, +/* opcode: fsqrt.h ; op1:x28; dest:x15; op1val:0x0; valaddr_reg:x10; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x15, x28, dyn, 0, 0, x10, 10*FLEN/8, x11, x4, x9) + +inst_11: +// rs1==x18, rd==x12, +/* opcode: fsqrt.h ; op1:x18; dest:x12; op1val:0x0; valaddr_reg:x10; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x12, x18, dyn, 0, 0, x10, 11*FLEN/8, x11, x4, x9) + +inst_12: +// rs1==x17, rd==x23, +/* opcode: fsqrt.h ; op1:x17; dest:x23; op1val:0x0; valaddr_reg:x10; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x23, x17, dyn, 0, 0, x10, 12*FLEN/8, x11, x4, x9) + +inst_13: +// rs1==x0, rd==x2, +/* opcode: fsqrt.h ; op1:x0; dest:x2; op1val:0x0; valaddr_reg:x10; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x2, x0, dyn, 0, 0, x10, 13*FLEN/8, x11, x4, x9) + +inst_14: +// rs1==x25, rd==x6, +/* opcode: fsqrt.h ; op1:x25; dest:x6; op1val:0x0; valaddr_reg:x10; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x6, x25, dyn, 0, 0, x10, 14*FLEN/8, x11, x4, x9) + +inst_15: +// rs1==x7, rd==x22, +/* opcode: fsqrt.h ; op1:x7; dest:x22; op1val:0x0; valaddr_reg:x10; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x22, x7, dyn, 0, 0, x10, 15*FLEN/8, x11, x4, x9) + +inst_16: +// rs1==x14, rd==x31, +/* opcode: fsqrt.h ; op1:x14; dest:x31; op1val:0x0; valaddr_reg:x10; +val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x31, x14, dyn, 0, 0, x10, 16*FLEN/8, x11, x4, x9) + +inst_17: +// rs1==x20, rd==x3, +/* opcode: fsqrt.h ; op1:x20; dest:x3; op1val:0x0; valaddr_reg:x10; +val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x3, x20, dyn, 0, 0, x10, 17*FLEN/8, x11, x4, x9) + +inst_18: +// rs1==x13, rd==x24, +/* opcode: fsqrt.h ; op1:x13; dest:x24; op1val:0x0; valaddr_reg:x10; +val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x24, x13, dyn, 0, 0, x10, 18*FLEN/8, x11, x4, x9) +RVTEST_VALBASEUPD(x5,test_dataset_1) + +inst_19: +// rs1==x3, rd==x10, +/* opcode: fsqrt.h ; op1:x3; dest:x10; op1val:0x0; valaddr_reg:x5; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x10, x3, dyn, 0, 0, x5, 0*FLEN/8, x6, x4, x9) + +inst_20: +// rs1==x2, rd==x18, +/* opcode: fsqrt.h ; op1:x2; dest:x18; op1val:0x0; valaddr_reg:x5; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x18, x2, dyn, 0, 0, x5, 1*FLEN/8, x6, x4, x9) + +inst_21: +// rs1==x8, rd==x26, +/* opcode: fsqrt.h ; op1:x8; dest:x26; op1val:0x0; valaddr_reg:x5; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x26, x8, dyn, 0, 0, x5, 2*FLEN/8, x6, x4, x9) + +inst_22: +// rs1==x10, rd==x30, +/* opcode: fsqrt.h ; op1:x10; dest:x30; op1val:0x0; valaddr_reg:x5; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x30, x10, dyn, 0, 0, x5, 3*FLEN/8, x6, x4, x9) + +inst_23: +// rs1==x1, rd==x11, +/* opcode: fsqrt.h ; op1:x1; dest:x11; op1val:0x0; valaddr_reg:x5; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x11, x1, dyn, 0, 0, x5, 4*FLEN/8, x6, x4, x2) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_24: +// rs1==x30, rd==x4, +/* opcode: fsqrt.h ; op1:x30; dest:x4; op1val:0x0; valaddr_reg:x5; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x4, x30, dyn, 0, 0, x5, 5*FLEN/8, x6, x1, x2) + +inst_25: +// rs1==x24, rd==x13, +/* opcode: fsqrt.h ; op1:x24; dest:x13; op1val:0x0; valaddr_reg:x5; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x13, x24, dyn, 0, 0, x5, 6*FLEN/8, x6, x1, x2) + +inst_26: +// rs1==x11, rd==x21, +/* opcode: fsqrt.h ; op1:x11; dest:x21; op1val:0x0; valaddr_reg:x5; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x21, x11, dyn, 0, 0, x5, 7*FLEN/8, x6, x1, x2) + +inst_27: +// rs1==x19, rd==x20, +/* opcode: fsqrt.h ; op1:x19; dest:x20; op1val:0x0; valaddr_reg:x5; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x20, x19, dyn, 0, 0, x5, 8*FLEN/8, x6, x1, x2) + +inst_28: +// rs1==x9, rd==x19, +/* opcode: fsqrt.h ; op1:x9; dest:x19; op1val:0x0; valaddr_reg:x5; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x19, x9, dyn, 0, 0, x5, 9*FLEN/8, x6, x1, x2) + +inst_29: +// rs1==x16, rd==x29, +/* opcode: fsqrt.h ; op1:x16; dest:x29; op1val:0x0; valaddr_reg:x5; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x29, x16, dyn, 0, 0, x5, 10*FLEN/8, x6, x1, x2) + +inst_30: +// rs1==x4, rd==x9, +/* opcode: fsqrt.h ; op1:x4; dest:x9; op1val:0x0; valaddr_reg:x5; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x9, x4, dyn, 0, 0, x5, 11*FLEN/8, x6, x1, x2) + +inst_31: +// rs1==x27, rd==x16, +/* opcode: fsqrt.h ; op1:x27; dest:x16; op1val:0x0; valaddr_reg:x5; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x16, x27, dyn, 0, 0, x5, 12*FLEN/8, x6, x1, x2) + +inst_32: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x144 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x30; dest:x31; op1val:0x144; valaddr_reg:x5; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x31, x30, dyn, 0, 0, x5, 13*FLEN/8, x6, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(24704,32,FLEN) +NAN_BOXED(25872,32,FLEN) +NAN_BOXED(324,32,FLEN) +NAN_BOXED(5056,32,FLEN) +NAN_BOXED(16361,32,FLEN) +NAN_BOXED(25600,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +test_dataset_1: +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(324,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x4_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x4_1: + .fill 48*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_0: + .fill 18*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fsqrt_b3-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fsqrt_b3-01.S new file mode 100644 index 000000000..1ad9f898a --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fsqrt_b3-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 05:27:49 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fsqrt.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fsqrt.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fsqrt_b3 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fsqrt_b3) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x10,signature_x10_1) + +inst_0: +// rs1 == rd, rs1==x17, rd==x17,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x17; dest:x17; op1val:0x0; valaddr_reg:x3; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x17, x17, dyn, 0, 0, x3, 0*FLEN/8, x7, x10, x2) + +inst_1: +// rs1 != rd, rs1==x12, rd==x8,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x12; dest:x8; op1val:0x0; valaddr_reg:x3; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP(fsqrt.h, x8, x12, dyn, 32, 0, x3, 1*FLEN/8, x7, x10, x2) + +inst_2: +// rs1==x15, rd==x26,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x15; dest:x26; op1val:0x0; valaddr_reg:x3; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP(fsqrt.h, x26, x15, dyn, 64, 0, x3, 2*FLEN/8, x7, x10, x2) + +inst_3: +// rs1==x20, rd==x30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x20; dest:x30; op1val:0x0; valaddr_reg:x3; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP(fsqrt.h, x30, x20, dyn, 96, 0, x3, 3*FLEN/8, x7, x10, x2) + +inst_4: +// rs1==x27, rd==x12,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x27; dest:x12; op1val:0x0; valaddr_reg:x3; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP(fsqrt.h, x12, x27, dyn, 128, 0, x3, 4*FLEN/8, x7, x10, x2) + +inst_5: +// rs1==x19, rd==x25,fs1 == 0 and fe1 == 0x1b and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x19; dest:x25; op1val:0x6c00; valaddr_reg:x3; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x25, x19, dyn, 0, 0, x3, 5*FLEN/8, x7, x10, x2) + +inst_6: +// rs1==x6, rd==x13,fs1 == 0 and fe1 == 0x1b and fm1 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x6; dest:x13; op1val:0x6c00; valaddr_reg:x3; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP(fsqrt.h, x13, x6, dyn, 32, 0, x3, 6*FLEN/8, x7, x10, x2) + +inst_7: +// rs1==x31, rd==x4,fs1 == 0 and fe1 == 0x1b and fm1 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x31; dest:x4; op1val:0x6c00; valaddr_reg:x3; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP(fsqrt.h, x4, x31, dyn, 64, 0, x3, 7*FLEN/8, x7, x10, x2) + +inst_8: +// rs1==x14, rd==x28,fs1 == 0 and fe1 == 0x1b and fm1 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x14; dest:x28; op1val:0x6c00; valaddr_reg:x3; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP(fsqrt.h, x28, x14, dyn, 96, 0, x3, 8*FLEN/8, x7, x10, x2) + +inst_9: +// rs1==x28, rd==x1,fs1 == 0 and fe1 == 0x1b and fm1 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x28; dest:x1; op1val:0x6c00; valaddr_reg:x3; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP(fsqrt.h, x1, x28, dyn, 128, 0, x3, 9*FLEN/8, x7, x10, x2) + +inst_10: +// rs1==x9, rd==x20,fs1 == 0 and fe1 == 0x05 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x9; dest:x20; op1val:0x1400; valaddr_reg:x3; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x20, x9, dyn, 0, 0, x3, 10*FLEN/8, x7, x10, x2) + +inst_11: +// rs1==x4, rd==x29,fs1 == 0 and fe1 == 0x05 and fm1 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x4; dest:x29; op1val:0x1400; valaddr_reg:x3; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP(fsqrt.h, x29, x4, dyn, 32, 0, x3, 11*FLEN/8, x7, x10, x2) + +inst_12: +// rs1==x18, rd==x16,fs1 == 0 and fe1 == 0x05 and fm1 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x18; dest:x16; op1val:0x1400; valaddr_reg:x3; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP(fsqrt.h, x16, x18, dyn, 64, 0, x3, 12*FLEN/8, x7, x10, x2) + +inst_13: +// rs1==x16, rd==x5,fs1 == 0 and fe1 == 0x05 and fm1 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x16; dest:x5; op1val:0x1400; valaddr_reg:x3; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP(fsqrt.h, x5, x16, dyn, 96, 0, x3, 13*FLEN/8, x7, x10, x2) + +inst_14: +// rs1==x25, rd==x19,fs1 == 0 and fe1 == 0x05 and fm1 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x25; dest:x19; op1val:0x1400; valaddr_reg:x3; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP(fsqrt.h, x19, x25, dyn, 128, 0, x3, 14*FLEN/8, x7, x10, x2) + +inst_15: +// rs1==x22, rd==x15, +/* opcode: fsqrt.h ; op1:x22; dest:x15; op1val:0x0; valaddr_reg:x3; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x15, x22, dyn, 0, 0, x3, 15*FLEN/8, x7, x10, x2) + +inst_16: +// rs1==x24, rd==x0, +/* opcode: fsqrt.h ; op1:x24; dest:x0; op1val:0x0; valaddr_reg:x3; +val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x0, x24, dyn, 0, 0, x3, 16*FLEN/8, x7, x10, x2) +RVTEST_VALBASEUPD(x12,test_dataset_1) + +inst_17: +// rs1==x5, rd==x21, +/* opcode: fsqrt.h ; op1:x5; dest:x21; op1val:0x0; valaddr_reg:x12; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x21, x5, dyn, 0, 0, x12, 0*FLEN/8, x15, x10, x2) + +inst_18: +// rs1==x21, rd==x9, +/* opcode: fsqrt.h ; op1:x21; dest:x9; op1val:0x0; valaddr_reg:x12; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x9, x21, dyn, 0, 0, x12, 1*FLEN/8, x15, x10, x2) + +inst_19: +// rs1==x3, rd==x22, +/* opcode: fsqrt.h ; op1:x3; dest:x22; op1val:0x0; valaddr_reg:x12; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x22, x3, dyn, 0, 0, x12, 2*FLEN/8, x15, x10, x2) + +inst_20: +// rs1==x7, rd==x2, +/* opcode: fsqrt.h ; op1:x7; dest:x2; op1val:0x0; valaddr_reg:x12; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x2, x7, dyn, 0, 0, x12, 3*FLEN/8, x15, x10, x5) +RVTEST_SIGBASE(x4,signature_x4_0) + +inst_21: +// rs1==x23, rd==x11, +/* opcode: fsqrt.h ; op1:x23; dest:x11; op1val:0x0; valaddr_reg:x12; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x11, x23, dyn, 0, 0, x12, 4*FLEN/8, x15, x4, x5) + +inst_22: +// rs1==x26, rd==x3, +/* opcode: fsqrt.h ; op1:x26; dest:x3; op1val:0x0; valaddr_reg:x12; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x3, x26, dyn, 0, 0, x12, 5*FLEN/8, x15, x4, x5) + +inst_23: +// rs1==x10, rd==x14, +/* opcode: fsqrt.h ; op1:x10; dest:x14; op1val:0x0; valaddr_reg:x12; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x14, x10, dyn, 0, 0, x12, 6*FLEN/8, x15, x4, x5) + +inst_24: +// rs1==x2, rd==x18, +/* opcode: fsqrt.h ; op1:x2; dest:x18; op1val:0x0; valaddr_reg:x12; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x18, x2, dyn, 0, 0, x12, 7*FLEN/8, x15, x4, x5) + +inst_25: +// rs1==x1, rd==x24, +/* opcode: fsqrt.h ; op1:x1; dest:x24; op1val:0x0; valaddr_reg:x12; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x24, x1, dyn, 0, 0, x12, 8*FLEN/8, x15, x4, x5) + +inst_26: +// rs1==x30, rd==x10, +/* opcode: fsqrt.h ; op1:x30; dest:x10; op1val:0x0; valaddr_reg:x12; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x10, x30, dyn, 0, 0, x12, 9*FLEN/8, x15, x4, x5) + +inst_27: +// rs1==x29, rd==x7, +/* opcode: fsqrt.h ; op1:x29; dest:x7; op1val:0x0; valaddr_reg:x12; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x7, x29, dyn, 0, 0, x12, 10*FLEN/8, x15, x4, x5) + +inst_28: +// rs1==x0, rd==x23, +/* opcode: fsqrt.h ; op1:x0; dest:x23; op1val:0x0; valaddr_reg:x12; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x23, x0, dyn, 0, 0, x12, 11*FLEN/8, x15, x4, x5) + +inst_29: +// rs1==x11, rd==x31, +/* opcode: fsqrt.h ; op1:x11; dest:x31; op1val:0x0; valaddr_reg:x12; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x31, x11, dyn, 0, 0, x12, 12*FLEN/8, x15, x4, x5) + +inst_30: +// rs1==x13, rd==x6, +/* opcode: fsqrt.h ; op1:x13; dest:x6; op1val:0x0; valaddr_reg:x12; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x6, x13, dyn, 0, 0, x12, 13*FLEN/8, x15, x4, x5) + +inst_31: +// rs1==x8, rd==x27, +/* opcode: fsqrt.h ; op1:x8; dest:x27; op1val:0x0; valaddr_reg:x12; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x27, x8, dyn, 0, 0, x12, 14*FLEN/8, x15, x4, x5) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(27648,32,FLEN) +NAN_BOXED(27648,32,FLEN) +NAN_BOXED(27648,32,FLEN) +NAN_BOXED(27648,32,FLEN) +NAN_BOXED(27648,32,FLEN) +NAN_BOXED(5120,32,FLEN) +NAN_BOXED(5120,32,FLEN) +NAN_BOXED(5120,32,FLEN) +NAN_BOXED(5120,32,FLEN) +NAN_BOXED(5120,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +test_dataset_1: +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x10_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x10_1: + .fill 42*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x4_0: + .fill 22*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fsqrt_b4-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fsqrt_b4-01.S new file mode 100644 index 000000000..a805e20fc --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fsqrt_b4-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 05:27:49 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fsqrt.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fsqrt.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fsqrt_b4 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fsqrt_b4) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x6,test_dataset_0) +RVTEST_SIGBASE(x7,signature_x7_1) + +inst_0: +// rs1 == rd, rs1==x23, rd==x23,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x23; dest:x23; op1val:0x7bff; valaddr_reg:x6; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x23, x23, dyn, 0, 0, x6, 0*FLEN/8, x12, x7, x9) + +inst_1: +// rs1 != rd, rs1==x30, rd==x14,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x30; dest:x14; op1val:0x7bff; valaddr_reg:x6; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val: 32 */ +TEST_FPSR_OP(fsqrt.h, x14, x30, dyn, 32, 0, x6, 1*FLEN/8, x12, x7, x9) + +inst_2: +// rs1==x1, rd==x24,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x1; dest:x24; op1val:0x7bff; valaddr_reg:x6; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val: 64 */ +TEST_FPSR_OP(fsqrt.h, x24, x1, dyn, 64, 0, x6, 2*FLEN/8, x12, x7, x9) + +inst_3: +// rs1==x14, rd==x22,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x14; dest:x22; op1val:0x7bff; valaddr_reg:x6; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val: 96 */ +TEST_FPSR_OP(fsqrt.h, x22, x14, dyn, 96, 0, x6, 3*FLEN/8, x12, x7, x9) + +inst_4: +// rs1==x3, rd==x30,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x3; dest:x30; op1val:0x7bff; valaddr_reg:x6; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val: 128 */ +TEST_FPSR_OP(fsqrt.h, x30, x3, dyn, 128, 0, x6, 4*FLEN/8, x12, x7, x9) + +inst_5: +// rs1==x19, rd==x25, +/* opcode: fsqrt.h ; op1:x19; dest:x25; op1val:0x0; valaddr_reg:x6; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x25, x19, dyn, 0, 0, x6, 5*FLEN/8, x12, x7, x9) + +inst_6: +// rs1==x28, rd==x3, +/* opcode: fsqrt.h ; op1:x28; dest:x3; op1val:0x0; valaddr_reg:x6; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x3, x28, dyn, 0, 0, x6, 6*FLEN/8, x12, x7, x9) + +inst_7: +// rs1==x25, rd==x8, +/* opcode: fsqrt.h ; op1:x25; dest:x8; op1val:0x0; valaddr_reg:x6; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x8, x25, dyn, 0, 0, x6, 7*FLEN/8, x12, x7, x9) + +inst_8: +// rs1==x24, rd==x15, +/* opcode: fsqrt.h ; op1:x24; dest:x15; op1val:0x0; valaddr_reg:x6; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x15, x24, dyn, 0, 0, x6, 8*FLEN/8, x12, x7, x9) + +inst_9: +// rs1==x27, rd==x11, +/* opcode: fsqrt.h ; op1:x27; dest:x11; op1val:0x0; valaddr_reg:x6; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x11, x27, dyn, 0, 0, x6, 9*FLEN/8, x12, x7, x9) + +inst_10: +// rs1==x26, rd==x19, +/* opcode: fsqrt.h ; op1:x26; dest:x19; op1val:0x0; valaddr_reg:x6; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x19, x26, dyn, 0, 0, x6, 10*FLEN/8, x12, x7, x9) + +inst_11: +// rs1==x8, rd==x10, +/* opcode: fsqrt.h ; op1:x8; dest:x10; op1val:0x0; valaddr_reg:x6; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x10, x8, dyn, 0, 0, x6, 11*FLEN/8, x12, x7, x9) + +inst_12: +// rs1==x29, rd==x31, +/* opcode: fsqrt.h ; op1:x29; dest:x31; op1val:0x0; valaddr_reg:x6; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x31, x29, dyn, 0, 0, x6, 12*FLEN/8, x12, x7, x9) + +inst_13: +// rs1==x2, rd==x0, +/* opcode: fsqrt.h ; op1:x2; dest:x0; op1val:0x0; valaddr_reg:x6; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x0, x2, dyn, 0, 0, x6, 13*FLEN/8, x12, x7, x9) + +inst_14: +// rs1==x22, rd==x26, +/* opcode: fsqrt.h ; op1:x22; dest:x26; op1val:0x0; valaddr_reg:x6; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x26, x22, dyn, 0, 0, x6, 14*FLEN/8, x12, x7, x9) + +inst_15: +// rs1==x4, rd==x20, +/* opcode: fsqrt.h ; op1:x4; dest:x20; op1val:0x0; valaddr_reg:x6; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x20, x4, dyn, 0, 0, x6, 15*FLEN/8, x12, x7, x9) + +inst_16: +// rs1==x16, rd==x18, +/* opcode: fsqrt.h ; op1:x16; dest:x18; op1val:0x0; valaddr_reg:x6; +val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x18, x16, dyn, 0, 0, x6, 16*FLEN/8, x12, x7, x9) + +inst_17: +// rs1==x11, rd==x2, +/* opcode: fsqrt.h ; op1:x11; dest:x2; op1val:0x0; valaddr_reg:x6; +val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x2, x11, dyn, 0, 0, x6, 17*FLEN/8, x12, x7, x9) + +inst_18: +// rs1==x5, rd==x1, +/* opcode: fsqrt.h ; op1:x5; dest:x1; op1val:0x0; valaddr_reg:x6; +val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x1, x5, dyn, 0, 0, x6, 18*FLEN/8, x12, x7, x9) +RVTEST_VALBASEUPD(x3,test_dataset_1) + +inst_19: +// rs1==x6, rd==x16, +/* opcode: fsqrt.h ; op1:x6; dest:x16; op1val:0x0; valaddr_reg:x3; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x16, x6, dyn, 0, 0, x3, 0*FLEN/8, x8, x7, x9) + +inst_20: +// rs1==x20, rd==x4, +/* opcode: fsqrt.h ; op1:x20; dest:x4; op1val:0x0; valaddr_reg:x3; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x4, x20, dyn, 0, 0, x3, 1*FLEN/8, x8, x7, x9) + +inst_21: +// rs1==x17, rd==x5, +/* opcode: fsqrt.h ; op1:x17; dest:x5; op1val:0x0; valaddr_reg:x3; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x5, x17, dyn, 0, 0, x3, 2*FLEN/8, x8, x7, x9) + +inst_22: +// rs1==x13, rd==x12, +/* opcode: fsqrt.h ; op1:x13; dest:x12; op1val:0x0; valaddr_reg:x3; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x12, x13, dyn, 0, 0, x3, 3*FLEN/8, x8, x7, x2) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_23: +// rs1==x10, rd==x6, +/* opcode: fsqrt.h ; op1:x10; dest:x6; op1val:0x0; valaddr_reg:x3; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x6, x10, dyn, 0, 0, x3, 4*FLEN/8, x8, x1, x2) + +inst_24: +// rs1==x15, rd==x21, +/* opcode: fsqrt.h ; op1:x15; dest:x21; op1val:0x0; valaddr_reg:x3; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x21, x15, dyn, 0, 0, x3, 5*FLEN/8, x8, x1, x2) + +inst_25: +// rs1==x0, rd==x7, +/* opcode: fsqrt.h ; op1:x0; dest:x7; op1val:0x0; valaddr_reg:x3; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x7, x0, dyn, 0, 0, x3, 6*FLEN/8, x8, x1, x2) + +inst_26: +// rs1==x21, rd==x17, +/* opcode: fsqrt.h ; op1:x21; dest:x17; op1val:0x0; valaddr_reg:x3; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x17, x21, dyn, 0, 0, x3, 7*FLEN/8, x8, x1, x2) + +inst_27: +// rs1==x31, rd==x9, +/* opcode: fsqrt.h ; op1:x31; dest:x9; op1val:0x0; valaddr_reg:x3; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x9, x31, dyn, 0, 0, x3, 8*FLEN/8, x8, x1, x2) + +inst_28: +// rs1==x12, rd==x29, +/* opcode: fsqrt.h ; op1:x12; dest:x29; op1val:0x0; valaddr_reg:x3; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x29, x12, dyn, 0, 0, x3, 9*FLEN/8, x8, x1, x2) + +inst_29: +// rs1==x7, rd==x28, +/* opcode: fsqrt.h ; op1:x7; dest:x28; op1val:0x0; valaddr_reg:x3; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x28, x7, dyn, 0, 0, x3, 10*FLEN/8, x8, x1, x2) + +inst_30: +// rs1==x9, rd==x27, +/* opcode: fsqrt.h ; op1:x9; dest:x27; op1val:0x0; valaddr_reg:x3; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x27, x9, dyn, 0, 0, x3, 11*FLEN/8, x8, x1, x2) + +inst_31: +// rs1==x18, rd==x13, +/* opcode: fsqrt.h ; op1:x18; dest:x13; op1val:0x0; valaddr_reg:x3; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x13, x18, dyn, 0, 0, x3, 12*FLEN/8, x8, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +test_dataset_1: +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x7_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x7_1: + .fill 46*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_0: + .fill 18*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fsqrt_b5-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fsqrt_b5-01.S new file mode 100644 index 000000000..e258a0ac3 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fsqrt_b5-01.S @@ -0,0 +1,361 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 05:27:49 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fsqrt.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fsqrt.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fsqrt_b5 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fsqrt_b5) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x1,test_dataset_0) +RVTEST_SIGBASE(x6,signature_x6_1) + +inst_0: +// rs1 == rd, rs1==x5, rd==x5,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x5; dest:x5; op1val:0x0; valaddr_reg:x1; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x8; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x5, x5, dyn, 0, 0, x1, 0*FLEN/8, x19, x6, x8) + +inst_1: +// rs1 != rd, rs1==x28, rd==x25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x28; dest:x25; op1val:0x0; valaddr_reg:x1; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x8; +fcsr_val: 32 */ +TEST_FPSR_OP(fsqrt.h, x25, x28, dyn, 32, 0, x1, 1*FLEN/8, x19, x6, x8) + +inst_2: +// rs1==x14, rd==x2,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x14; dest:x2; op1val:0x0; valaddr_reg:x1; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x8; +fcsr_val: 64 */ +TEST_FPSR_OP(fsqrt.h, x2, x14, dyn, 64, 0, x1, 2*FLEN/8, x19, x6, x8) + +inst_3: +// rs1==x10, rd==x13,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x10; dest:x13; op1val:0x0; valaddr_reg:x1; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x8; +fcsr_val: 96 */ +TEST_FPSR_OP(fsqrt.h, x13, x10, dyn, 96, 0, x1, 3*FLEN/8, x19, x6, x8) + +inst_4: +// rs1==x16, rd==x31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x16; dest:x31; op1val:0x0; valaddr_reg:x1; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x8; +fcsr_val: 128 */ +TEST_FPSR_OP(fsqrt.h, x31, x16, dyn, 128, 0, x1, 4*FLEN/8, x19, x6, x8) + +inst_5: +// rs1==x9, rd==x7,fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x9; dest:x7; op1val:0x1; valaddr_reg:x1; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x8; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x7, x9, dyn, 0, 0, x1, 5*FLEN/8, x19, x6, x8) + +inst_6: +// rs1==x27, rd==x28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x27; dest:x28; op1val:0x1; valaddr_reg:x1; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x8; +fcsr_val: 32 */ +TEST_FPSR_OP(fsqrt.h, x28, x27, dyn, 32, 0, x1, 6*FLEN/8, x19, x6, x8) + +inst_7: +// rs1==x7, rd==x12,fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x7; dest:x12; op1val:0x1; valaddr_reg:x1; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x8; +fcsr_val: 64 */ +TEST_FPSR_OP(fsqrt.h, x12, x7, dyn, 64, 0, x1, 7*FLEN/8, x19, x6, x8) + +inst_8: +// rs1==x12, rd==x3,fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x12; dest:x3; op1val:0x1; valaddr_reg:x1; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x8; +fcsr_val: 96 */ +TEST_FPSR_OP(fsqrt.h, x3, x12, dyn, 96, 0, x1, 8*FLEN/8, x19, x6, x8) + +inst_9: +// rs1==x23, rd==x21,fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x23; dest:x21; op1val:0x1; valaddr_reg:x1; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x8; +fcsr_val: 128 */ +TEST_FPSR_OP(fsqrt.h, x21, x23, dyn, 128, 0, x1, 9*FLEN/8, x19, x6, x8) + +inst_10: +// rs1==x2, rd==x9,fs1 == 0 and fe1 == 0x00 and fm1 == 0x004 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x2; dest:x9; op1val:0x4; valaddr_reg:x1; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x8; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x9, x2, dyn, 0, 0, x1, 10*FLEN/8, x19, x6, x8) + +inst_11: +// rs1==x18, rd==x4,fs1 == 0 and fe1 == 0x00 and fm1 == 0x004 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x18; dest:x4; op1val:0x4; valaddr_reg:x1; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x8; +fcsr_val: 32 */ +TEST_FPSR_OP(fsqrt.h, x4, x18, dyn, 32, 0, x1, 11*FLEN/8, x19, x6, x8) + +inst_12: +// rs1==x17, rd==x27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x004 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x17; dest:x27; op1val:0x4; valaddr_reg:x1; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x8; +fcsr_val: 64 */ +TEST_FPSR_OP(fsqrt.h, x27, x17, dyn, 64, 0, x1, 12*FLEN/8, x19, x6, x8) + +inst_13: +// rs1==x11, rd==x10,fs1 == 0 and fe1 == 0x00 and fm1 == 0x004 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x11; dest:x10; op1val:0x4; valaddr_reg:x1; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x8; +fcsr_val: 96 */ +TEST_FPSR_OP(fsqrt.h, x10, x11, dyn, 96, 0, x1, 13*FLEN/8, x19, x6, x8) + +inst_14: +// rs1==x30, rd==x23,fs1 == 0 and fe1 == 0x00 and fm1 == 0x004 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x30; dest:x23; op1val:0x4; valaddr_reg:x1; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x8; +fcsr_val: 128 */ +TEST_FPSR_OP(fsqrt.h, x23, x30, dyn, 128, 0, x1, 14*FLEN/8, x19, x6, x8) + +inst_15: +// rs1==x13, rd==x11,fs1 == 0 and fe1 == 0x00 and fm1 == 0x010 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x13; dest:x11; op1val:0x10; valaddr_reg:x1; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x8; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x11, x13, dyn, 0, 0, x1, 15*FLEN/8, x19, x6, x8) + +inst_16: +// rs1==x15, rd==x30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x010 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x15; dest:x30; op1val:0x10; valaddr_reg:x1; +val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x8; +fcsr_val: 32 */ +TEST_FPSR_OP(fsqrt.h, x30, x15, dyn, 32, 0, x1, 16*FLEN/8, x19, x6, x8) + +inst_17: +// rs1==x24, rd==x22,fs1 == 0 and fe1 == 0x00 and fm1 == 0x010 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x24; dest:x22; op1val:0x10; valaddr_reg:x1; +val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x8; +fcsr_val: 64 */ +TEST_FPSR_OP(fsqrt.h, x22, x24, dyn, 64, 0, x1, 17*FLEN/8, x19, x6, x8) +RVTEST_VALBASEUPD(x7,test_dataset_1) + +inst_18: +// rs1==x20, rd==x16,fs1 == 0 and fe1 == 0x00 and fm1 == 0x010 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x20; dest:x16; op1val:0x10; valaddr_reg:x7; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x8; +fcsr_val: 96 */ +TEST_FPSR_OP(fsqrt.h, x16, x20, dyn, 96, 0, x7, 0*FLEN/8, x9, x6, x8) + +inst_19: +// rs1==x31, rd==x1,fs1 == 0 and fe1 == 0x00 and fm1 == 0x010 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x31; dest:x1; op1val:0x10; valaddr_reg:x7; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x8; +fcsr_val: 128 */ +TEST_FPSR_OP(fsqrt.h, x1, x31, dyn, 128, 0, x7, 1*FLEN/8, x9, x6, x8) + +inst_20: +// rs1==x29, rd==x0,fs1 == 0 and fe1 == 0x00 and fm1 == 0x040 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x29; dest:x0; op1val:0x40; valaddr_reg:x7; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x0, x29, dyn, 0, 0, x7, 2*FLEN/8, x9, x6, x5) +RVTEST_SIGBASE(x2,signature_x2_0) + +inst_21: +// rs1==x3, rd==x14,fs1 == 0 and fe1 == 0x00 and fm1 == 0x040 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x3; dest:x14; op1val:0x40; valaddr_reg:x7; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val: 32 */ +TEST_FPSR_OP(fsqrt.h, x14, x3, dyn, 32, 0, x7, 3*FLEN/8, x9, x2, x5) + +inst_22: +// rs1==x6, rd==x8,fs1 == 0 and fe1 == 0x00 and fm1 == 0x040 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x6; dest:x8; op1val:0x40; valaddr_reg:x7; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val: 64 */ +TEST_FPSR_OP(fsqrt.h, x8, x6, dyn, 64, 0, x7, 4*FLEN/8, x9, x2, x5) + +inst_23: +// rs1==x26, rd==x24,fs1 == 0 and fe1 == 0x00 and fm1 == 0x040 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x26; dest:x24; op1val:0x40; valaddr_reg:x7; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val: 96 */ +TEST_FPSR_OP(fsqrt.h, x24, x26, dyn, 96, 0, x7, 5*FLEN/8, x9, x2, x5) + +inst_24: +// rs1==x21, rd==x15,fs1 == 0 and fe1 == 0x00 and fm1 == 0x040 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x21; dest:x15; op1val:0x40; valaddr_reg:x7; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val: 128 */ +TEST_FPSR_OP(fsqrt.h, x15, x21, dyn, 128, 0, x7, 6*FLEN/8, x9, x2, x5) + +inst_25: +// rs1==x19, rd==x29, +/* opcode: fsqrt.h ; op1:x19; dest:x29; op1val:0x0; valaddr_reg:x7; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x29, x19, dyn, 0, 0, x7, 7*FLEN/8, x9, x2, x5) + +inst_26: +// rs1==x8, rd==x17, +/* opcode: fsqrt.h ; op1:x8; dest:x17; op1val:0x0; valaddr_reg:x7; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x17, x8, dyn, 0, 0, x7, 8*FLEN/8, x9, x2, x5) + +inst_27: +// rs1==x4, rd==x6, +/* opcode: fsqrt.h ; op1:x4; dest:x6; op1val:0x0; valaddr_reg:x7; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x6, x4, dyn, 0, 0, x7, 9*FLEN/8, x9, x2, x5) + +inst_28: +// rs1==x22, rd==x18, +/* opcode: fsqrt.h ; op1:x22; dest:x18; op1val:0x0; valaddr_reg:x7; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x18, x22, dyn, 0, 0, x7, 10*FLEN/8, x9, x2, x5) + +inst_29: +// rs1==x0, rd==x26, +/* opcode: fsqrt.h ; op1:x0; dest:x26; op1val:0x0; valaddr_reg:x7; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x26, x0, dyn, 0, 0, x7, 11*FLEN/8, x9, x2, x5) + +inst_30: +// rs1==x25, rd==x20, +/* opcode: fsqrt.h ; op1:x25; dest:x20; op1val:0x0; valaddr_reg:x7; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x20, x25, dyn, 0, 0, x7, 12*FLEN/8, x9, x2, x5) + +inst_31: +// rs1==x1, rd==x19, +/* opcode: fsqrt.h ; op1:x1; dest:x19; op1val:0x0; valaddr_reg:x7; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x19, x1, dyn, 0, 0, x7, 13*FLEN/8, x9, x2, x5) + +inst_32: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x040 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x30; dest:x31; op1val:0x40; valaddr_reg:x7; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x31, x30, dyn, 0, 0, x7, 14*FLEN/8, x9, x2, x5) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(1,32,FLEN) +NAN_BOXED(1,32,FLEN) +NAN_BOXED(1,32,FLEN) +NAN_BOXED(1,32,FLEN) +NAN_BOXED(1,32,FLEN) +NAN_BOXED(4,32,FLEN) +NAN_BOXED(4,32,FLEN) +NAN_BOXED(4,32,FLEN) +NAN_BOXED(4,32,FLEN) +NAN_BOXED(4,32,FLEN) +NAN_BOXED(16,32,FLEN) +NAN_BOXED(16,32,FLEN) +NAN_BOXED(16,32,FLEN) +test_dataset_1: +NAN_BOXED(16,16,FLEN) +NAN_BOXED(16,16,FLEN) +NAN_BOXED(64,16,FLEN) +NAN_BOXED(64,16,FLEN) +NAN_BOXED(64,16,FLEN) +NAN_BOXED(64,16,FLEN) +NAN_BOXED(64,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x6_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x6_1: + .fill 42*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_0: + .fill 24*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fsqrt_b7-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fsqrt_b7-01.S new file mode 100644 index 000000000..8a990baeb --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fsqrt_b7-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 05:27:49 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fsqrt.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fsqrt.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fsqrt_b7 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fsqrt_b7) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x12,test_dataset_0) +RVTEST_SIGBASE(x11,signature_x11_1) + +inst_0: +// rs1 == rd, rs1==x27, rd==x27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x27; dest:x27; op1val:0x0; valaddr_reg:x12; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x26; +fcsr_val: 96 */ +TEST_FPSR_OP(fsqrt.h, x27, x27, dyn, 96, 0, x12, 0*FLEN/8, x14, x11, x26) + +inst_1: +// rs1 != rd, rs1==x22, rd==x6,fs1 == 0 and fe1 == 0x1b and fm1 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x22; dest:x6; op1val:0x6c00; valaddr_reg:x12; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x26; +fcsr_val: 96 */ +TEST_FPSR_OP(fsqrt.h, x6, x22, dyn, 96, 0, x12, 1*FLEN/8, x14, x11, x26) + +inst_2: +// rs1==x24, rd==x23,fs1 == 0 and fe1 == 0x05 and fm1 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x24; dest:x23; op1val:0x1400; valaddr_reg:x12; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x26; +fcsr_val: 96 */ +TEST_FPSR_OP(fsqrt.h, x23, x24, dyn, 96, 0, x12, 2*FLEN/8, x14, x11, x26) + +inst_3: +// rs1==x18, rd==x17, +/* opcode: fsqrt.h ; op1:x18; dest:x17; op1val:0x0; valaddr_reg:x12; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x26; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x17, x18, dyn, 0, 0, x12, 3*FLEN/8, x14, x11, x26) + +inst_4: +// rs1==x21, rd==x5, +/* opcode: fsqrt.h ; op1:x21; dest:x5; op1val:0x0; valaddr_reg:x12; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x26; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x5, x21, dyn, 0, 0, x12, 4*FLEN/8, x14, x11, x26) + +inst_5: +// rs1==x7, rd==x20, +/* opcode: fsqrt.h ; op1:x7; dest:x20; op1val:0x0; valaddr_reg:x12; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x26; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x20, x7, dyn, 0, 0, x12, 5*FLEN/8, x14, x11, x26) + +inst_6: +// rs1==x13, rd==x1, +/* opcode: fsqrt.h ; op1:x13; dest:x1; op1val:0x0; valaddr_reg:x12; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x26; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x1, x13, dyn, 0, 0, x12, 6*FLEN/8, x14, x11, x26) + +inst_7: +// rs1==x19, rd==x28, +/* opcode: fsqrt.h ; op1:x19; dest:x28; op1val:0x0; valaddr_reg:x12; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x26; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x28, x19, dyn, 0, 0, x12, 7*FLEN/8, x14, x11, x26) + +inst_8: +// rs1==x5, rd==x8, +/* opcode: fsqrt.h ; op1:x5; dest:x8; op1val:0x0; valaddr_reg:x12; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x26; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x8, x5, dyn, 0, 0, x12, 8*FLEN/8, x14, x11, x26) + +inst_9: +// rs1==x9, rd==x4, +/* opcode: fsqrt.h ; op1:x9; dest:x4; op1val:0x0; valaddr_reg:x12; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x26; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x4, x9, dyn, 0, 0, x12, 9*FLEN/8, x14, x11, x26) + +inst_10: +// rs1==x17, rd==x16, +/* opcode: fsqrt.h ; op1:x17; dest:x16; op1val:0x0; valaddr_reg:x12; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x26; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x16, x17, dyn, 0, 0, x12, 10*FLEN/8, x14, x11, x26) + +inst_11: +// rs1==x15, rd==x10, +/* opcode: fsqrt.h ; op1:x15; dest:x10; op1val:0x0; valaddr_reg:x12; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x26; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x10, x15, dyn, 0, 0, x12, 11*FLEN/8, x14, x11, x26) + +inst_12: +// rs1==x3, rd==x7, +/* opcode: fsqrt.h ; op1:x3; dest:x7; op1val:0x0; valaddr_reg:x12; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x26; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x7, x3, dyn, 0, 0, x12, 12*FLEN/8, x14, x11, x26) + +inst_13: +// rs1==x2, rd==x25, +/* opcode: fsqrt.h ; op1:x2; dest:x25; op1val:0x0; valaddr_reg:x12; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x26; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x25, x2, dyn, 0, 0, x12, 13*FLEN/8, x14, x11, x26) +RVTEST_VALBASEUPD(x5,test_dataset_1) + +inst_14: +// rs1==x1, rd==x3, +/* opcode: fsqrt.h ; op1:x1; dest:x3; op1val:0x0; valaddr_reg:x5; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x26; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x3, x1, dyn, 0, 0, x5, 0*FLEN/8, x7, x11, x26) + +inst_15: +// rs1==x12, rd==x14, +/* opcode: fsqrt.h ; op1:x12; dest:x14; op1val:0x0; valaddr_reg:x5; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x26; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x14, x12, dyn, 0, 0, x5, 1*FLEN/8, x7, x11, x26) + +inst_16: +// rs1==x26, rd==x21, +/* opcode: fsqrt.h ; op1:x26; dest:x21; op1val:0x0; valaddr_reg:x5; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x21, x26, dyn, 0, 0, x5, 2*FLEN/8, x7, x11, x3) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_17: +// rs1==x30, rd==x22, +/* opcode: fsqrt.h ; op1:x30; dest:x22; op1val:0x0; valaddr_reg:x5; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x22, x30, dyn, 0, 0, x5, 3*FLEN/8, x7, x1, x3) + +inst_18: +// rs1==x28, rd==x11, +/* opcode: fsqrt.h ; op1:x28; dest:x11; op1val:0x0; valaddr_reg:x5; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x11, x28, dyn, 0, 0, x5, 4*FLEN/8, x7, x1, x3) + +inst_19: +// rs1==x6, rd==x29, +/* opcode: fsqrt.h ; op1:x6; dest:x29; op1val:0x0; valaddr_reg:x5; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x29, x6, dyn, 0, 0, x5, 5*FLEN/8, x7, x1, x3) + +inst_20: +// rs1==x14, rd==x30, +/* opcode: fsqrt.h ; op1:x14; dest:x30; op1val:0x0; valaddr_reg:x5; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x30, x14, dyn, 0, 0, x5, 6*FLEN/8, x7, x1, x3) + +inst_21: +// rs1==x25, rd==x18, +/* opcode: fsqrt.h ; op1:x25; dest:x18; op1val:0x0; valaddr_reg:x5; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x18, x25, dyn, 0, 0, x5, 7*FLEN/8, x7, x1, x3) + +inst_22: +// rs1==x11, rd==x0, +/* opcode: fsqrt.h ; op1:x11; dest:x0; op1val:0x0; valaddr_reg:x5; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x0, x11, dyn, 0, 0, x5, 8*FLEN/8, x7, x1, x3) + +inst_23: +// rs1==x4, rd==x31, +/* opcode: fsqrt.h ; op1:x4; dest:x31; op1val:0x0; valaddr_reg:x5; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x31, x4, dyn, 0, 0, x5, 9*FLEN/8, x7, x1, x3) + +inst_24: +// rs1==x10, rd==x9, +/* opcode: fsqrt.h ; op1:x10; dest:x9; op1val:0x0; valaddr_reg:x5; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x9, x10, dyn, 0, 0, x5, 10*FLEN/8, x7, x1, x3) + +inst_25: +// rs1==x8, rd==x19, +/* opcode: fsqrt.h ; op1:x8; dest:x19; op1val:0x0; valaddr_reg:x5; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x19, x8, dyn, 0, 0, x5, 11*FLEN/8, x7, x1, x3) + +inst_26: +// rs1==x0, rd==x26, +/* opcode: fsqrt.h ; op1:x0; dest:x26; op1val:0x0; valaddr_reg:x5; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x26, x0, dyn, 0, 0, x5, 12*FLEN/8, x7, x1, x3) + +inst_27: +// rs1==x29, rd==x15, +/* opcode: fsqrt.h ; op1:x29; dest:x15; op1val:0x0; valaddr_reg:x5; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x15, x29, dyn, 0, 0, x5, 13*FLEN/8, x7, x1, x3) + +inst_28: +// rs1==x31, rd==x24, +/* opcode: fsqrt.h ; op1:x31; dest:x24; op1val:0x0; valaddr_reg:x5; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x24, x31, dyn, 0, 0, x5, 14*FLEN/8, x7, x1, x3) + +inst_29: +// rs1==x16, rd==x13, +/* opcode: fsqrt.h ; op1:x16; dest:x13; op1val:0x0; valaddr_reg:x5; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x13, x16, dyn, 0, 0, x5, 15*FLEN/8, x7, x1, x3) + +inst_30: +// rs1==x20, rd==x12, +/* opcode: fsqrt.h ; op1:x20; dest:x12; op1val:0x0; valaddr_reg:x5; +val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x12, x20, dyn, 0, 0, x5, 16*FLEN/8, x7, x1, x3) + +inst_31: +// rs1==x23, rd==x2, +/* opcode: fsqrt.h ; op1:x23; dest:x2; op1val:0x0; valaddr_reg:x5; +val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x2, x23, dyn, 0, 0, x5, 17*FLEN/8, x7, x1, x3) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(27648,32,FLEN) +NAN_BOXED(5120,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +test_dataset_1: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x11_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x11_1: + .fill 34*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_0: + .fill 30*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fsqrt_b8-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fsqrt_b8-01.S new file mode 100644 index 000000000..4417dcbc5 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fsqrt_b8-01.S @@ -0,0 +1,363 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 05:27:49 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fsqrt.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fsqrt.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fsqrt_b8 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fsqrt_b8) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x7,test_dataset_0) +RVTEST_SIGBASE(x4,signature_x4_1) + +inst_0: +// rs1 == rd, rs1==x18, rd==x18,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x18; dest:x18; op1val:0x0; valaddr_reg:x7; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x10; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x18, x18, dyn, 0, 0, x7, 0*FLEN/8, x13, x4, x10) + +inst_1: +// rs1 != rd, rs1==x17, rd==x5,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x17; dest:x5; op1val:0x0; valaddr_reg:x7; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x10; +fcsr_val: 32 */ +TEST_FPSR_OP(fsqrt.h, x5, x17, dyn, 32, 0, x7, 1*FLEN/8, x13, x4, x10) + +inst_2: +// rs1==x19, rd==x3,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x19; dest:x3; op1val:0x0; valaddr_reg:x7; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x10; +fcsr_val: 64 */ +TEST_FPSR_OP(fsqrt.h, x3, x19, dyn, 64, 0, x7, 2*FLEN/8, x13, x4, x10) + +inst_3: +// rs1==x5, rd==x31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x5; dest:x31; op1val:0x0; valaddr_reg:x7; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x10; +fcsr_val: 96 */ +TEST_FPSR_OP(fsqrt.h, x31, x5, dyn, 96, 0, x7, 3*FLEN/8, x13, x4, x10) + +inst_4: +// rs1==x23, rd==x16,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x23; dest:x16; op1val:0x0; valaddr_reg:x7; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x10; +fcsr_val: 128 */ +TEST_FPSR_OP(fsqrt.h, x16, x23, dyn, 128, 0, x7, 4*FLEN/8, x13, x4, x10) + +inst_5: +// rs1==x9, rd==x19,fs1 == 0 and fe1 == 0x1b and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x9; dest:x19; op1val:0x6c00; valaddr_reg:x7; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x10; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x19, x9, dyn, 0, 0, x7, 5*FLEN/8, x13, x4, x10) + +inst_6: +// rs1==x16, rd==x2,fs1 == 0 and fe1 == 0x1b and fm1 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x16; dest:x2; op1val:0x6c00; valaddr_reg:x7; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x10; +fcsr_val: 32 */ +TEST_FPSR_OP(fsqrt.h, x2, x16, dyn, 32, 0, x7, 6*FLEN/8, x13, x4, x10) + +inst_7: +// rs1==x2, rd==x21,fs1 == 0 and fe1 == 0x1b and fm1 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x2; dest:x21; op1val:0x6c00; valaddr_reg:x7; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x10; +fcsr_val: 64 */ +TEST_FPSR_OP(fsqrt.h, x21, x2, dyn, 64, 0, x7, 7*FLEN/8, x13, x4, x10) + +inst_8: +// rs1==x11, rd==x20,fs1 == 0 and fe1 == 0x1b and fm1 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x11; dest:x20; op1val:0x6c00; valaddr_reg:x7; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x10; +fcsr_val: 96 */ +TEST_FPSR_OP(fsqrt.h, x20, x11, dyn, 96, 0, x7, 8*FLEN/8, x13, x4, x10) + +inst_9: +// rs1==x1, rd==x26,fs1 == 0 and fe1 == 0x1b and fm1 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x1; dest:x26; op1val:0x6c00; valaddr_reg:x7; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x10; +fcsr_val: 128 */ +TEST_FPSR_OP(fsqrt.h, x26, x1, dyn, 128, 0, x7, 9*FLEN/8, x13, x4, x10) + +inst_10: +// rs1==x24, rd==x29,fs1 == 0 and fe1 == 0x05 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x24; dest:x29; op1val:0x1400; valaddr_reg:x7; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x10; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x29, x24, dyn, 0, 0, x7, 10*FLEN/8, x13, x4, x10) + +inst_11: +// rs1==x27, rd==x1,fs1 == 0 and fe1 == 0x05 and fm1 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x27; dest:x1; op1val:0x1400; valaddr_reg:x7; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x10; +fcsr_val: 32 */ +TEST_FPSR_OP(fsqrt.h, x1, x27, dyn, 32, 0, x7, 11*FLEN/8, x13, x4, x10) + +inst_12: +// rs1==x30, rd==x0,fs1 == 0 and fe1 == 0x05 and fm1 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x30; dest:x0; op1val:0x1400; valaddr_reg:x7; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x10; +fcsr_val: 64 */ +TEST_FPSR_OP(fsqrt.h, x0, x30, dyn, 64, 0, x7, 12*FLEN/8, x13, x4, x10) + +inst_13: +// rs1==x12, rd==x28,fs1 == 0 and fe1 == 0x05 and fm1 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x12; dest:x28; op1val:0x1400; valaddr_reg:x7; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x10; +fcsr_val: 96 */ +TEST_FPSR_OP(fsqrt.h, x28, x12, dyn, 96, 0, x7, 13*FLEN/8, x13, x4, x10) + +inst_14: +// rs1==x8, rd==x15,fs1 == 0 and fe1 == 0x05 and fm1 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x8; dest:x15; op1val:0x1400; valaddr_reg:x7; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x10; +fcsr_val: 128 */ +TEST_FPSR_OP(fsqrt.h, x15, x8, dyn, 128, 0, x7, 14*FLEN/8, x13, x4, x10) + +inst_15: +// rs1==x26, rd==x6, +/* opcode: fsqrt.h ; op1:x26; dest:x6; op1val:0x0; valaddr_reg:x7; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x10; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x6, x26, dyn, 0, 0, x7, 15*FLEN/8, x13, x4, x10) +RVTEST_VALBASEUPD(x5,test_dataset_1) + +inst_16: +// rs1==x14, rd==x12, +/* opcode: fsqrt.h ; op1:x14; dest:x12; op1val:0x0; valaddr_reg:x5; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x10; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x12, x14, dyn, 0, 0, x5, 0*FLEN/8, x16, x4, x10) + +inst_17: +// rs1==x0, rd==x7, +/* opcode: fsqrt.h ; op1:x0; dest:x7; op1val:0x0; valaddr_reg:x5; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x10; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x7, x0, dyn, 0, 0, x5, 1*FLEN/8, x16, x4, x10) + +inst_18: +// rs1==x3, rd==x11, +/* opcode: fsqrt.h ; op1:x3; dest:x11; op1val:0x0; valaddr_reg:x5; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x11, x3, dyn, 0, 0, x5, 2*FLEN/8, x16, x4, x2) + +inst_19: +// rs1==x20, rd==x25, +/* opcode: fsqrt.h ; op1:x20; dest:x25; op1val:0x0; valaddr_reg:x5; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x25, x20, dyn, 0, 0, x5, 3*FLEN/8, x16, x4, x2) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_20: +// rs1==x22, rd==x13, +/* opcode: fsqrt.h ; op1:x22; dest:x13; op1val:0x0; valaddr_reg:x5; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x13, x22, dyn, 0, 0, x5, 4*FLEN/8, x16, x1, x2) + +inst_21: +// rs1==x28, rd==x4, +/* opcode: fsqrt.h ; op1:x28; dest:x4; op1val:0x0; valaddr_reg:x5; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x4, x28, dyn, 0, 0, x5, 5*FLEN/8, x16, x1, x2) + +inst_22: +// rs1==x10, rd==x14, +/* opcode: fsqrt.h ; op1:x10; dest:x14; op1val:0x0; valaddr_reg:x5; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x14, x10, dyn, 0, 0, x5, 6*FLEN/8, x16, x1, x2) + +inst_23: +// rs1==x25, rd==x24, +/* opcode: fsqrt.h ; op1:x25; dest:x24; op1val:0x0; valaddr_reg:x5; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x24, x25, dyn, 0, 0, x5, 7*FLEN/8, x16, x1, x2) + +inst_24: +// rs1==x4, rd==x22, +/* opcode: fsqrt.h ; op1:x4; dest:x22; op1val:0x0; valaddr_reg:x5; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x22, x4, dyn, 0, 0, x5, 8*FLEN/8, x16, x1, x2) + +inst_25: +// rs1==x15, rd==x10, +/* opcode: fsqrt.h ; op1:x15; dest:x10; op1val:0x0; valaddr_reg:x5; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x10, x15, dyn, 0, 0, x5, 9*FLEN/8, x16, x1, x2) + +inst_26: +// rs1==x29, rd==x9, +/* opcode: fsqrt.h ; op1:x29; dest:x9; op1val:0x0; valaddr_reg:x5; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x9, x29, dyn, 0, 0, x5, 10*FLEN/8, x16, x1, x2) + +inst_27: +// rs1==x13, rd==x8, +/* opcode: fsqrt.h ; op1:x13; dest:x8; op1val:0x0; valaddr_reg:x5; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x8, x13, dyn, 0, 0, x5, 11*FLEN/8, x16, x1, x2) + +inst_28: +// rs1==x6, rd==x30, +/* opcode: fsqrt.h ; op1:x6; dest:x30; op1val:0x0; valaddr_reg:x5; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x30, x6, dyn, 0, 0, x5, 12*FLEN/8, x16, x1, x2) + +inst_29: +// rs1==x31, rd==x17, +/* opcode: fsqrt.h ; op1:x31; dest:x17; op1val:0x0; valaddr_reg:x5; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x17, x31, dyn, 0, 0, x5, 13*FLEN/8, x16, x1, x2) + +inst_30: +// rs1==x7, rd==x23, +/* opcode: fsqrt.h ; op1:x7; dest:x23; op1val:0x0; valaddr_reg:x5; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x23, x7, dyn, 0, 0, x5, 14*FLEN/8, x16, x1, x2) + +inst_31: +// rs1==x21, rd==x27, +/* opcode: fsqrt.h ; op1:x21; dest:x27; op1val:0x0; valaddr_reg:x5; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x27, x21, dyn, 0, 0, x5, 15*FLEN/8, x16, x1, x2) +RVTEST_VALBASEUPD(x3,test_dataset_2) + +inst_32: +// fs1 == 0 and fe1 == 0x05 and fm1 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x30; dest:x31; op1val:0x1400; valaddr_reg:x3; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP(fsqrt.h, x31, x30, dyn, 64, 0, x3, 0*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(27648,32,FLEN) +NAN_BOXED(27648,32,FLEN) +NAN_BOXED(27648,32,FLEN) +NAN_BOXED(27648,32,FLEN) +NAN_BOXED(27648,32,FLEN) +NAN_BOXED(5120,32,FLEN) +NAN_BOXED(5120,32,FLEN) +NAN_BOXED(5120,32,FLEN) +NAN_BOXED(5120,32,FLEN) +NAN_BOXED(5120,32,FLEN) +NAN_BOXED(0,32,FLEN) +test_dataset_1: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +test_dataset_2: +NAN_BOXED(5120,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x4_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x4_1: + .fill 40*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_0: + .fill 26*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fsqrt_b9-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fsqrt_b9-01.S new file mode 100644 index 000000000..d807e8073 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fsqrt_b9-01.S @@ -0,0 +1,361 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 05:27:49 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fsqrt.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fsqrt.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fsqrt_b9 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fsqrt_b9) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x2,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==x13, rd==x13,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x13; dest:x13; op1val:0x0; valaddr_reg:x2; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x23; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x13, x13, dyn, 0, 0, x2, 0*FLEN/8, x15, x1, x23) + +inst_1: +// rs1 != rd, rs1==x7, rd==x0,fs1 == 0 and fe1 == 0x08 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x7; dest:x0; op1val:0x2000; valaddr_reg:x2; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x23; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x0, x7, dyn, 0, 0, x2, 1*FLEN/8, x15, x1, x23) + +inst_2: +// rs1==x11, rd==x30,fs1 == 0 and fe1 == 0x0f and fm1 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x11; dest:x30; op1val:0x3ff8; valaddr_reg:x2; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x23; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x30, x11, dyn, 0, 0, x2, 2*FLEN/8, x15, x1, x23) + +inst_3: +// rs1==x22, rd==x3,fs1 == 0 and fe1 == 0x0c and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x22; dest:x3; op1val:0x3000; valaddr_reg:x2; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x23; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x3, x22, dyn, 0, 0, x2, 3*FLEN/8, x15, x1, x23) + +inst_4: +// rs1==x21, rd==x8,fs1 == 0 and fe1 == 0x0b and fm1 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x21; dest:x8; op1val:0x2ff8; valaddr_reg:x2; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x23; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x8, x21, dyn, 0, 0, x2, 4*FLEN/8, x15, x1, x23) + +inst_5: +// rs1==x19, rd==x31,fs1 == 0 and fe1 == 0x0e and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x19; dest:x31; op1val:0x3800; valaddr_reg:x2; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x23; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x31, x19, dyn, 0, 0, x2, 5*FLEN/8, x15, x1, x23) + +inst_6: +// rs1==x5, rd==x7,fs1 == 0 and fe1 == 0x09 and fm1 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x5; dest:x7; op1val:0x27f8; valaddr_reg:x2; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x23; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x7, x5, dyn, 0, 0, x2, 6*FLEN/8, x15, x1, x23) + +inst_7: +// rs1==x26, rd==x19,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x26; dest:x19; op1val:0x3c00; valaddr_reg:x2; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x23; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x19, x26, dyn, 0, 0, x2, 7*FLEN/8, x15, x1, x23) + +inst_8: +// rs1==x17, rd==x10,fs1 == 0 and fe1 == 0x08 and fm1 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x17; dest:x10; op1val:0x23f8; valaddr_reg:x2; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x23; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x10, x17, dyn, 0, 0, x2, 8*FLEN/8, x15, x1, x23) + +inst_9: +// rs1==x28, rd==x4,fs1 == 0 and fe1 == 0x0f and fm1 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x28; dest:x4; op1val:0x3e00; valaddr_reg:x2; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x23; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x4, x28, dyn, 0, 0, x2, 9*FLEN/8, x15, x1, x23) + +inst_10: +// rs1==x24, rd==x17,fs1 == 0 and fe1 == 0x08 and fm1 == 0x1f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x24; dest:x17; op1val:0x21f8; valaddr_reg:x2; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x23; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x17, x24, dyn, 0, 0, x2, 10*FLEN/8, x15, x1, x23) + +inst_11: +// rs1==x3, rd==x11,fs1 == 0 and fe1 == 0x0f and fm1 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x3; dest:x11; op1val:0x3f00; valaddr_reg:x2; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x23; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x11, x3, dyn, 0, 0, x2, 11*FLEN/8, x15, x1, x23) + +inst_12: +// rs1==x31, rd==x20,fs1 == 0 and fe1 == 0x08 and fm1 == 0x0f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x31; dest:x20; op1val:0x20f8; valaddr_reg:x2; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x23; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x20, x31, dyn, 0, 0, x2, 12*FLEN/8, x15, x1, x23) + +inst_13: +// rs1==x29, rd==x26,fs1 == 0 and fe1 == 0x0f and fm1 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x29; dest:x26; op1val:0x3f80; valaddr_reg:x2; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x23; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x26, x29, dyn, 0, 0, x2, 13*FLEN/8, x15, x1, x23) + +inst_14: +// rs1==x6, rd==x5,fs1 == 0 and fe1 == 0x08 and fm1 == 0x078 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x6; dest:x5; op1val:0x2078; valaddr_reg:x2; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x23; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x5, x6, dyn, 0, 0, x2, 14*FLEN/8, x15, x1, x23) + +inst_15: +// rs1==x14, rd==x9,fs1 == 0 and fe1 == 0x0f and fm1 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x14; dest:x9; op1val:0x3fc0; valaddr_reg:x2; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x23; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x9, x14, dyn, 0, 0, x2, 15*FLEN/8, x15, x1, x23) + +inst_16: +// rs1==x4, rd==x12,fs1 == 0 and fe1 == 0x08 and fm1 == 0x038 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x4; dest:x12; op1val:0x2038; valaddr_reg:x2; +val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x23; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x12, x4, dyn, 0, 0, x2, 16*FLEN/8, x15, x1, x23) + +inst_17: +// rs1==x9, rd==x29,fs1 == 0 and fe1 == 0x0f and fm1 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x9; dest:x29; op1val:0x3fe0; valaddr_reg:x2; +val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x23; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x29, x9, dyn, 0, 0, x2, 17*FLEN/8, x15, x1, x23) + +inst_18: +// rs1==x10, rd==x16,fs1 == 0 and fe1 == 0x08 and fm1 == 0x018 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x10; dest:x16; op1val:0x2018; valaddr_reg:x2; +val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x23; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x16, x10, dyn, 0, 0, x2, 18*FLEN/8, x15, x1, x23) +RVTEST_VALBASEUPD(x5,test_dataset_1) + +inst_19: +// rs1==x12, rd==x6,fs1 == 0 and fe1 == 0x0f and fm1 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x12; dest:x6; op1val:0x3ff0; valaddr_reg:x5; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x23; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x6, x12, dyn, 0, 0, x5, 0*FLEN/8, x7, x1, x23) + +inst_20: +// rs1==x15, rd==x14,fs1 == 0 and fe1 == 0x08 and fm1 == 0x008 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x15; dest:x14; op1val:0x2008; valaddr_reg:x5; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x23; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x14, x15, dyn, 0, 0, x5, 1*FLEN/8, x7, x1, x23) + +inst_21: +// rs1==x18, rd==x2,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x18; dest:x2; op1val:0x7bff; valaddr_reg:x5; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x23; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x2, x18, dyn, 0, 0, x5, 2*FLEN/8, x7, x1, x23) +RVTEST_SIGBASE(x3,signature_x3_0) + +inst_22: +// rs1==x23, rd==x22, +/* opcode: fsqrt.h ; op1:x23; dest:x22; op1val:0x0; valaddr_reg:x5; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x22, x23, dyn, 0, 0, x5, 3*FLEN/8, x7, x3, x4) + +inst_23: +// rs1==x20, rd==x23, +/* opcode: fsqrt.h ; op1:x20; dest:x23; op1val:0x0; valaddr_reg:x5; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x23, x20, dyn, 0, 0, x5, 4*FLEN/8, x7, x3, x4) + +inst_24: +// rs1==x30, rd==x1, +/* opcode: fsqrt.h ; op1:x30; dest:x1; op1val:0x0; valaddr_reg:x5; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x1, x30, dyn, 0, 0, x5, 5*FLEN/8, x7, x3, x4) + +inst_25: +// rs1==x8, rd==x25, +/* opcode: fsqrt.h ; op1:x8; dest:x25; op1val:0x0; valaddr_reg:x5; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x25, x8, dyn, 0, 0, x5, 6*FLEN/8, x7, x3, x4) + +inst_26: +// rs1==x16, rd==x24, +/* opcode: fsqrt.h ; op1:x16; dest:x24; op1val:0x0; valaddr_reg:x5; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x24, x16, dyn, 0, 0, x5, 7*FLEN/8, x7, x3, x4) + +inst_27: +// rs1==x1, rd==x21, +/* opcode: fsqrt.h ; op1:x1; dest:x21; op1val:0x0; valaddr_reg:x5; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x21, x1, dyn, 0, 0, x5, 8*FLEN/8, x7, x3, x4) + +inst_28: +// rs1==x2, rd==x28, +/* opcode: fsqrt.h ; op1:x2; dest:x28; op1val:0x0; valaddr_reg:x5; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x28, x2, dyn, 0, 0, x5, 9*FLEN/8, x7, x3, x4) + +inst_29: +// rs1==x25, rd==x15, +/* opcode: fsqrt.h ; op1:x25; dest:x15; op1val:0x0; valaddr_reg:x5; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x15, x25, dyn, 0, 0, x5, 10*FLEN/8, x7, x3, x4) + +inst_30: +// rs1==x27, rd==x18, +/* opcode: fsqrt.h ; op1:x27; dest:x18; op1val:0x0; valaddr_reg:x5; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x18, x27, dyn, 0, 0, x5, 11*FLEN/8, x7, x3, x4) + +inst_31: +// rs1==x0, rd==x27, +/* opcode: fsqrt.h ; op1:x0; dest:x27; op1val:0x0; valaddr_reg:x5; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x27, x0, dyn, 0, 0, x5, 12*FLEN/8, x7, x3, x4) + +inst_32: +// fs1 == 0 and fe1 == 0x08 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fsqrt.h ; op1:x30; dest:x31; op1val:0x2000; valaddr_reg:x5; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val: 0 */ +TEST_FPSR_OP(fsqrt.h, x31, x30, dyn, 0, 0, x5, 13*FLEN/8, x7, x3, x4) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(8192,32,FLEN) +NAN_BOXED(16376,32,FLEN) +NAN_BOXED(12288,32,FLEN) +NAN_BOXED(12280,32,FLEN) +NAN_BOXED(14336,32,FLEN) +NAN_BOXED(10232,32,FLEN) +NAN_BOXED(15360,32,FLEN) +NAN_BOXED(9208,32,FLEN) +NAN_BOXED(15872,32,FLEN) +NAN_BOXED(8696,32,FLEN) +NAN_BOXED(16128,32,FLEN) +NAN_BOXED(8440,32,FLEN) +NAN_BOXED(16256,32,FLEN) +NAN_BOXED(8312,32,FLEN) +NAN_BOXED(16320,32,FLEN) +NAN_BOXED(8248,32,FLEN) +NAN_BOXED(16352,32,FLEN) +NAN_BOXED(8216,32,FLEN) +test_dataset_1: +NAN_BOXED(16368,16,FLEN) +NAN_BOXED(8200,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(8192,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 44*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x3_0: + .fill 22*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fsub_b1-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fsub_b1-01.S new file mode 100644 index 000000000..964c6aa89 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fsub_b1-01.S @@ -0,0 +1,5353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 06:02:02 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fsub.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fsub.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fsub_b1 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fsub_b1) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x7,test_dataset_0) +RVTEST_SIGBASE(x6,signature_x6_1) + +inst_0: +// rs1 == rs2 == rd, rs1==x8, rs2==x8, rd==x8,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x8; op2:x8; dest:x8; op1val:0x0; op2val:0x0; + valaddr_reg:x7; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x18*/ +TEST_FPRR_OP(fsub.h, x8, x8, x8, dyn, 0, 0, x7, 0*FLEN/8, x19, x6, x18) + +inst_1: +// rs2 == rd != rs1, rs1==x10, rs2==x27, rd==x27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x10; op2:x27; dest:x27; op1val:0x0; op2val:0x8000; + valaddr_reg:x7; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x18*/ +TEST_FPRR_OP(fsub.h, x27, x10, x27, dyn, 0, 0, x7, 2*FLEN/8, x19, x6, x18) + +inst_2: +// rs1 == rd != rs2, rs1==x4, rs2==x31, rd==x4,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x4; op2:x31; dest:x4; op1val:0x0; op2val:0x1; + valaddr_reg:x7; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x18*/ +TEST_FPRR_OP(fsub.h, x4, x4, x31, dyn, 0, 0, x7, 4*FLEN/8, x19, x6, x18) + +inst_3: +// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==x11, rs2==x17, rd==x15,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x11; op2:x17; dest:x15; op1val:0x0; op2val:0x8001; + valaddr_reg:x7; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x18*/ +TEST_FPRR_OP(fsub.h, x15, x11, x17, dyn, 0, 0, x7, 6*FLEN/8, x19, x6, x18) + +inst_4: +// rs1 == rs2 != rd, rs1==x25, rs2==x25, rd==x11,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x25; op2:x25; dest:x11; op1val:0x0; op2val:0x0; + valaddr_reg:x7; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x18*/ +TEST_FPRR_OP(fsub.h, x11, x25, x25, dyn, 0, 0, x7, 8*FLEN/8, x19, x6, x18) + +inst_5: +// rs1==x3, rs2==x30, rd==x23,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x3; op2:x30; dest:x23; op1val:0x0; op2val:0x83fe; + valaddr_reg:x7; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x18*/ +TEST_FPRR_OP(fsub.h, x23, x3, x30, dyn, 0, 0, x7, 10*FLEN/8, x19, x6, x18) + +inst_6: +// rs1==x9, rs2==x14, rd==x10,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x9; op2:x14; dest:x10; op1val:0x0; op2val:0x3ff; + valaddr_reg:x7; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x18*/ +TEST_FPRR_OP(fsub.h, x10, x9, x14, dyn, 0, 0, x7, 12*FLEN/8, x19, x6, x18) + +inst_7: +// rs1==x22, rs2==x13, rd==x24,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x22; op2:x13; dest:x24; op1val:0x0; op2val:0x83ff; + valaddr_reg:x7; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x18*/ +TEST_FPRR_OP(fsub.h, x24, x22, x13, dyn, 0, 0, x7, 14*FLEN/8, x19, x6, x18) + +inst_8: +// rs1==x24, rs2==x1, rd==x14,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x24; op2:x1; dest:x14; op1val:0x0; op2val:0x400; + valaddr_reg:x7; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x18*/ +TEST_FPRR_OP(fsub.h, x14, x24, x1, dyn, 0, 0, x7, 16*FLEN/8, x19, x6, x18) + +inst_9: +// rs1==x2, rs2==x9, rd==x16,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x2; op2:x9; dest:x16; op1val:0x0; op2val:0x8400; + valaddr_reg:x7; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x18*/ +TEST_FPRR_OP(fsub.h, x16, x2, x9, dyn, 0, 0, x7, 18*FLEN/8, x19, x6, x18) + +inst_10: +// rs1==x12, rs2==x28, rd==x5,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x12; op2:x28; dest:x5; op1val:0x0; op2val:0x401; + valaddr_reg:x7; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x18*/ +TEST_FPRR_OP(fsub.h, x5, x12, x28, dyn, 0, 0, x7, 20*FLEN/8, x19, x6, x18) +RVTEST_VALBASEUPD(x2,test_dataset_1) + +inst_11: +// rs1==x31, rs2==x22, rd==x25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x31; op2:x22; dest:x25; op1val:0x0; op2val:0x8455; + valaddr_reg:x2; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x18*/ +TEST_FPRR_OP(fsub.h, x25, x31, x22, dyn, 0, 0, x2, 0*FLEN/8, x4, x6, x18) + +inst_12: +// rs1==x1, rs2==x7, rd==x22,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x1; op2:x7; dest:x22; op1val:0x0; op2val:0x7bff; + valaddr_reg:x2; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x18*/ +TEST_FPRR_OP(fsub.h, x22, x1, x7, dyn, 0, 0, x2, 2*FLEN/8, x4, x6, x18) + +inst_13: +// rs1==x14, rs2==x23, rd==x3,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x14; op2:x23; dest:x3; op1val:0x0; op2val:0xfbff; + valaddr_reg:x2; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x18*/ +TEST_FPRR_OP(fsub.h, x3, x14, x23, dyn, 0, 0, x2, 4*FLEN/8, x4, x6, x18) + +inst_14: +// rs1==x21, rs2==x12, rd==x1,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x21; op2:x12; dest:x1; op1val:0x0; op2val:0x7c00; + valaddr_reg:x2; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x18*/ +TEST_FPRR_OP(fsub.h, x1, x21, x12, dyn, 0, 0, x2, 6*FLEN/8, x4, x6, x18) + +inst_15: +// rs1==x5, rs2==x16, rd==x26,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x5; op2:x16; dest:x26; op1val:0x0; op2val:0xfc00; + valaddr_reg:x2; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8*/ +TEST_FPRR_OP(fsub.h, x26, x5, x16, dyn, 0, 0, x2, 8*FLEN/8, x4, x6, x8) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_16: +// rs1==x16, rs2==x19, rd==x20,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x16; op2:x19; dest:x20; op1val:0x0; op2val:0x7e00; + valaddr_reg:x2; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8*/ +TEST_FPRR_OP(fsub.h, x20, x16, x19, dyn, 0, 0, x2, 10*FLEN/8, x4, x1, x8) + +inst_17: +// rs1==x0, rs2==x15, rd==x9,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x0; op2:x15; dest:x9; op1val:0x0; op2val:0xfe00; + valaddr_reg:x2; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8*/ +TEST_FPRR_OP(fsub.h, x9, x0, x15, dyn, 0, 0, x2, 12*FLEN/8, x4, x1, x8) + +inst_18: +// rs1==x30, rs2==x3, rd==x21,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x3; dest:x21; op1val:0x0; op2val:0x7e01; + valaddr_reg:x2; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8*/ +TEST_FPRR_OP(fsub.h, x21, x30, x3, dyn, 0, 0, x2, 14*FLEN/8, x4, x1, x8) + +inst_19: +// rs1==x15, rs2==x5, rd==x19,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x15; op2:x5; dest:x19; op1val:0x0; op2val:0xfe55; + valaddr_reg:x2; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8*/ +TEST_FPRR_OP(fsub.h, x19, x15, x5, dyn, 0, 0, x2, 16*FLEN/8, x4, x1, x8) + +inst_20: +// rs1==x26, rs2==x6, rd==x31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x26; op2:x6; dest:x31; op1val:0x0; op2val:0x7c01; + valaddr_reg:x2; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8*/ +TEST_FPRR_OP(fsub.h, x31, x26, x6, dyn, 0, 0, x2, 18*FLEN/8, x4, x1, x8) + +inst_21: +// rs1==x20, rs2==x11, rd==x18,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x20; op2:x11; dest:x18; op1val:0x0; op2val:0xfd55; + valaddr_reg:x2; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8*/ +TEST_FPRR_OP(fsub.h, x18, x20, x11, dyn, 0, 0, x2, 20*FLEN/8, x4, x1, x8) + +inst_22: +// rs1==x17, rs2==x0, rd==x13,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x17; op2:x0; dest:x13; op1val:0x0; op2val:0x0; + valaddr_reg:x2; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8*/ +TEST_FPRR_OP(fsub.h, x13, x17, x0, dyn, 0, 0, x2, 22*FLEN/8, x4, x1, x8) + +inst_23: +// rs1==x13, rs2==x18, rd==x28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x13; op2:x18; dest:x28; op1val:0x0; op2val:0xbc00; + valaddr_reg:x2; val_offset:24*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8*/ +TEST_FPRR_OP(fsub.h, x28, x13, x18, dyn, 0, 0, x2, 24*FLEN/8, x4, x1, x8) +RVTEST_VALBASEUPD(x5,test_dataset_2) + +inst_24: +// rs1==x6, rs2==x26, rd==x29,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x6; op2:x26; dest:x29; op1val:0x8000; op2val:0x0; + valaddr_reg:x5; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8*/ +TEST_FPRR_OP(fsub.h, x29, x6, x26, dyn, 0, 0, x5, 0*FLEN/8, x9, x1, x8) + +inst_25: +// rs1==x27, rs2==x29, rd==x30,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x27; op2:x29; dest:x30; op1val:0x8000; op2val:0x8000; + valaddr_reg:x5; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8*/ +TEST_FPRR_OP(fsub.h, x30, x27, x29, dyn, 0, 0, x5, 2*FLEN/8, x9, x1, x8) + +inst_26: +// rs1==x19, rs2==x4, rd==x2,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x19; op2:x4; dest:x2; op1val:0x8000; op2val:0x1; + valaddr_reg:x5; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8*/ +TEST_FPRR_OP(fsub.h, x2, x19, x4, dyn, 0, 0, x5, 4*FLEN/8, x9, x1, x8) + +inst_27: +// rs1==x29, rs2==x21, rd==x12,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x29; op2:x21; dest:x12; op1val:0x8000; op2val:0x8001; + valaddr_reg:x5; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8*/ +TEST_FPRR_OP(fsub.h, x12, x29, x21, dyn, 0, 0, x5, 6*FLEN/8, x9, x1, x8) + +inst_28: +// rs1==x23, rs2==x20, rd==x7,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x23; op2:x20; dest:x7; op1val:0x8000; op2val:0x2; + valaddr_reg:x5; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8*/ +TEST_FPRR_OP(fsub.h, x7, x23, x20, dyn, 0, 0, x5, 8*FLEN/8, x9, x1, x8) + +inst_29: +// rs1==x18, rs2==x10, rd==x6,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x18; op2:x10; dest:x6; op1val:0x8000; op2val:0x83fe; + valaddr_reg:x5; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x8*/ +TEST_FPRR_OP(fsub.h, x6, x18, x10, dyn, 0, 0, x5, 10*FLEN/8, x9, x1, x8) + +inst_30: +// rs1==x7, rs2==x2, rd==x0,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x7; op2:x2; dest:x0; op1val:0x8000; op2val:0x3ff; + valaddr_reg:x5; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x0, x7, x2, dyn, 0, 0, x5, 12*FLEN/8, x9, x1, x3) + +inst_31: +// rs1==x28, rs2==x24, rd==x17,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x28; op2:x24; dest:x17; op1val:0x8000; op2val:0x83ff; + valaddr_reg:x5; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x17, x28, x24, dyn, 0, 0, x5, 14*FLEN/8, x9, x1, x3) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_32: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x400; + valaddr_reg:x5; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 16*FLEN/8, x9, x1, x3) + +inst_33: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8400; + valaddr_reg:x5; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 18*FLEN/8, x9, x1, x3) + +inst_34: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x401; + valaddr_reg:x5; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 20*FLEN/8, x9, x1, x3) + +inst_35: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8455; + valaddr_reg:x5; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 22*FLEN/8, x9, x1, x3) + +inst_36: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x7bff; + valaddr_reg:x5; val_offset:24*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 24*FLEN/8, x9, x1, x3) + +inst_37: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xfbff; + valaddr_reg:x5; val_offset:26*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 26*FLEN/8, x9, x1, x3) + +inst_38: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x7c00; + valaddr_reg:x5; val_offset:28*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 28*FLEN/8, x9, x1, x3) + +inst_39: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xfc00; + valaddr_reg:x5; val_offset:30*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 30*FLEN/8, x9, x1, x3) + +inst_40: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x7e00; + valaddr_reg:x5; val_offset:32*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 32*FLEN/8, x9, x1, x3) + +inst_41: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xfe00; + valaddr_reg:x5; val_offset:34*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 34*FLEN/8, x9, x1, x3) + +inst_42: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x7e01; + valaddr_reg:x5; val_offset:36*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 36*FLEN/8, x9, x1, x3) + +inst_43: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xfe55; + valaddr_reg:x5; val_offset:38*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 38*FLEN/8, x9, x1, x3) + +inst_44: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x7c01; + valaddr_reg:x5; val_offset:40*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 40*FLEN/8, x9, x1, x3) + +inst_45: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xfd55; + valaddr_reg:x5; val_offset:42*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 42*FLEN/8, x9, x1, x3) + +inst_46: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x3c00; + valaddr_reg:x5; val_offset:44*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 44*FLEN/8, x9, x1, x3) + +inst_47: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0xbc00; + valaddr_reg:x5; val_offset:46*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 46*FLEN/8, x9, x1, x3) + +inst_48: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x0; + valaddr_reg:x5; val_offset:48*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 48*FLEN/8, x9, x1, x3) + +inst_49: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x8000; + valaddr_reg:x5; val_offset:50*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 50*FLEN/8, x9, x1, x3) + +inst_50: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x1; + valaddr_reg:x5; val_offset:52*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 52*FLEN/8, x9, x1, x3) + +inst_51: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x8001; + valaddr_reg:x5; val_offset:54*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 54*FLEN/8, x9, x1, x3) + +inst_52: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x2; + valaddr_reg:x5; val_offset:56*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 56*FLEN/8, x9, x1, x3) + +inst_53: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x83fe; + valaddr_reg:x5; val_offset:58*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 58*FLEN/8, x9, x1, x3) + +inst_54: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x3ff; + valaddr_reg:x5; val_offset:60*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 60*FLEN/8, x9, x1, x3) + +inst_55: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x83ff; + valaddr_reg:x5; val_offset:62*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 62*FLEN/8, x9, x1, x3) + +inst_56: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x400; + valaddr_reg:x5; val_offset:64*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 64*FLEN/8, x9, x1, x3) + +inst_57: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x8400; + valaddr_reg:x5; val_offset:66*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 66*FLEN/8, x9, x1, x3) + +inst_58: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x401; + valaddr_reg:x5; val_offset:68*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 68*FLEN/8, x9, x1, x3) + +inst_59: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x8455; + valaddr_reg:x5; val_offset:70*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 70*FLEN/8, x9, x1, x3) + +inst_60: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7bff; + valaddr_reg:x5; val_offset:72*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 72*FLEN/8, x9, x1, x3) + +inst_61: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xfbff; + valaddr_reg:x5; val_offset:74*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 74*FLEN/8, x9, x1, x3) + +inst_62: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7c00; + valaddr_reg:x5; val_offset:76*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 76*FLEN/8, x9, x1, x3) + +inst_63: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xfc00; + valaddr_reg:x5; val_offset:78*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 78*FLEN/8, x9, x1, x3) + +inst_64: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7e00; + valaddr_reg:x5; val_offset:80*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 80*FLEN/8, x9, x1, x3) + +inst_65: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xfe00; + valaddr_reg:x5; val_offset:82*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 82*FLEN/8, x9, x1, x3) + +inst_66: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7e01; + valaddr_reg:x5; val_offset:84*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 84*FLEN/8, x9, x1, x3) + +inst_67: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xfe55; + valaddr_reg:x5; val_offset:86*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 86*FLEN/8, x9, x1, x3) + +inst_68: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7c01; + valaddr_reg:x5; val_offset:88*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 88*FLEN/8, x9, x1, x3) + +inst_69: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xfd55; + valaddr_reg:x5; val_offset:90*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 90*FLEN/8, x9, x1, x3) + +inst_70: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x3c00; + valaddr_reg:x5; val_offset:92*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 92*FLEN/8, x9, x1, x3) + +inst_71: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xbc00; + valaddr_reg:x5; val_offset:94*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 94*FLEN/8, x9, x1, x3) + +inst_72: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x0; + valaddr_reg:x5; val_offset:96*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 96*FLEN/8, x9, x1, x3) + +inst_73: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8000; + valaddr_reg:x5; val_offset:98*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 98*FLEN/8, x9, x1, x3) + +inst_74: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x1; + valaddr_reg:x5; val_offset:100*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 100*FLEN/8, x9, x1, x3) + +inst_75: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8001; + valaddr_reg:x5; val_offset:102*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 102*FLEN/8, x9, x1, x3) + +inst_76: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x2; + valaddr_reg:x5; val_offset:104*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 104*FLEN/8, x9, x1, x3) + +inst_77: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x83fe; + valaddr_reg:x5; val_offset:106*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 106*FLEN/8, x9, x1, x3) + +inst_78: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x3ff; + valaddr_reg:x5; val_offset:108*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 108*FLEN/8, x9, x1, x3) + +inst_79: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x83ff; + valaddr_reg:x5; val_offset:110*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 110*FLEN/8, x9, x1, x3) + +inst_80: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x400; + valaddr_reg:x5; val_offset:112*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 112*FLEN/8, x9, x1, x3) + +inst_81: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8400; + valaddr_reg:x5; val_offset:114*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 114*FLEN/8, x9, x1, x3) + +inst_82: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x401; + valaddr_reg:x5; val_offset:116*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 116*FLEN/8, x9, x1, x3) + +inst_83: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8455; + valaddr_reg:x5; val_offset:118*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 118*FLEN/8, x9, x1, x3) + +inst_84: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x7bff; + valaddr_reg:x5; val_offset:120*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 120*FLEN/8, x9, x1, x3) + +inst_85: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xfbff; + valaddr_reg:x5; val_offset:122*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 122*FLEN/8, x9, x1, x3) + +inst_86: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x7c00; + valaddr_reg:x5; val_offset:124*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 124*FLEN/8, x9, x1, x3) + +inst_87: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xfc00; + valaddr_reg:x5; val_offset:126*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 126*FLEN/8, x9, x1, x3) + +inst_88: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x7e00; + valaddr_reg:x5; val_offset:128*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 128*FLEN/8, x9, x1, x3) + +inst_89: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xfe00; + valaddr_reg:x5; val_offset:130*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 130*FLEN/8, x9, x1, x3) + +inst_90: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x7e01; + valaddr_reg:x5; val_offset:132*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 132*FLEN/8, x9, x1, x3) + +inst_91: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xfe55; + valaddr_reg:x5; val_offset:134*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 134*FLEN/8, x9, x1, x3) + +inst_92: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x7c01; + valaddr_reg:x5; val_offset:136*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 136*FLEN/8, x9, x1, x3) + +inst_93: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xfd55; + valaddr_reg:x5; val_offset:138*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 138*FLEN/8, x9, x1, x3) + +inst_94: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x3c00; + valaddr_reg:x5; val_offset:140*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 140*FLEN/8, x9, x1, x3) + +inst_95: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xbc00; + valaddr_reg:x5; val_offset:142*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 142*FLEN/8, x9, x1, x3) + +inst_96: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x0; + valaddr_reg:x5; val_offset:144*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 144*FLEN/8, x9, x1, x3) + +inst_97: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x8000; + valaddr_reg:x5; val_offset:146*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 146*FLEN/8, x9, x1, x3) + +inst_98: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x1; + valaddr_reg:x5; val_offset:148*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 148*FLEN/8, x9, x1, x3) + +inst_99: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x8001; + valaddr_reg:x5; val_offset:150*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 150*FLEN/8, x9, x1, x3) + +inst_100: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x2; + valaddr_reg:x5; val_offset:152*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 152*FLEN/8, x9, x1, x3) + +inst_101: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x83fe; + valaddr_reg:x5; val_offset:154*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 154*FLEN/8, x9, x1, x3) + +inst_102: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x3ff; + valaddr_reg:x5; val_offset:156*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 156*FLEN/8, x9, x1, x3) + +inst_103: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x83ff; + valaddr_reg:x5; val_offset:158*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 158*FLEN/8, x9, x1, x3) + +inst_104: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x400; + valaddr_reg:x5; val_offset:160*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 160*FLEN/8, x9, x1, x3) + +inst_105: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x8400; + valaddr_reg:x5; val_offset:162*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 162*FLEN/8, x9, x1, x3) + +inst_106: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x401; + valaddr_reg:x5; val_offset:164*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 164*FLEN/8, x9, x1, x3) + +inst_107: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x8455; + valaddr_reg:x5; val_offset:166*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 166*FLEN/8, x9, x1, x3) + +inst_108: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x7bff; + valaddr_reg:x5; val_offset:168*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 168*FLEN/8, x9, x1, x3) + +inst_109: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xfbff; + valaddr_reg:x5; val_offset:170*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 170*FLEN/8, x9, x1, x3) + +inst_110: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x7c00; + valaddr_reg:x5; val_offset:172*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 172*FLEN/8, x9, x1, x3) + +inst_111: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xfc00; + valaddr_reg:x5; val_offset:174*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 174*FLEN/8, x9, x1, x3) + +inst_112: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x7e00; + valaddr_reg:x5; val_offset:176*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 176*FLEN/8, x9, x1, x3) + +inst_113: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xfe00; + valaddr_reg:x5; val_offset:178*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 178*FLEN/8, x9, x1, x3) + +inst_114: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x7e01; + valaddr_reg:x5; val_offset:180*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 180*FLEN/8, x9, x1, x3) + +inst_115: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xfe55; + valaddr_reg:x5; val_offset:182*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 182*FLEN/8, x9, x1, x3) + +inst_116: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x7c01; + valaddr_reg:x5; val_offset:184*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 184*FLEN/8, x9, x1, x3) + +inst_117: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xfd55; + valaddr_reg:x5; val_offset:186*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 186*FLEN/8, x9, x1, x3) + +inst_118: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0x3c00; + valaddr_reg:x5; val_offset:188*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 188*FLEN/8, x9, x1, x3) + +inst_119: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2; op2val:0xbc00; + valaddr_reg:x5; val_offset:190*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 190*FLEN/8, x9, x1, x3) + +inst_120: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x0; + valaddr_reg:x5; val_offset:192*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 192*FLEN/8, x9, x1, x3) + +inst_121: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x8000; + valaddr_reg:x5; val_offset:194*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 194*FLEN/8, x9, x1, x3) + +inst_122: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x1; + valaddr_reg:x5; val_offset:196*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 196*FLEN/8, x9, x1, x3) + +inst_123: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x8001; + valaddr_reg:x5; val_offset:198*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 198*FLEN/8, x9, x1, x3) + +inst_124: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x2; + valaddr_reg:x5; val_offset:200*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 200*FLEN/8, x9, x1, x3) + +inst_125: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x83fe; + valaddr_reg:x5; val_offset:202*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 202*FLEN/8, x9, x1, x3) + +inst_126: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x3ff; + valaddr_reg:x5; val_offset:204*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 204*FLEN/8, x9, x1, x3) + +inst_127: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x83ff; + valaddr_reg:x5; val_offset:206*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 206*FLEN/8, x9, x1, x3) + +inst_128: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x400; + valaddr_reg:x5; val_offset:208*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 208*FLEN/8, x9, x1, x3) + +inst_129: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x8400; + valaddr_reg:x5; val_offset:210*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 210*FLEN/8, x9, x1, x3) + +inst_130: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x401; + valaddr_reg:x5; val_offset:212*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 212*FLEN/8, x9, x1, x3) + +inst_131: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x8455; + valaddr_reg:x5; val_offset:214*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 214*FLEN/8, x9, x1, x3) + +inst_132: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x7bff; + valaddr_reg:x5; val_offset:216*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 216*FLEN/8, x9, x1, x3) + +inst_133: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xfbff; + valaddr_reg:x5; val_offset:218*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 218*FLEN/8, x9, x1, x3) + +inst_134: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x7c00; + valaddr_reg:x5; val_offset:220*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 220*FLEN/8, x9, x1, x3) + +inst_135: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xfc00; + valaddr_reg:x5; val_offset:222*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 222*FLEN/8, x9, x1, x3) + +inst_136: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x7e00; + valaddr_reg:x5; val_offset:224*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 224*FLEN/8, x9, x1, x3) + +inst_137: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xfe00; + valaddr_reg:x5; val_offset:226*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 226*FLEN/8, x9, x1, x3) + +inst_138: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x7e01; + valaddr_reg:x5; val_offset:228*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 228*FLEN/8, x9, x1, x3) + +inst_139: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xfe55; + valaddr_reg:x5; val_offset:230*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 230*FLEN/8, x9, x1, x3) + +inst_140: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x7c01; + valaddr_reg:x5; val_offset:232*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 232*FLEN/8, x9, x1, x3) + +inst_141: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xfd55; + valaddr_reg:x5; val_offset:234*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 234*FLEN/8, x9, x1, x3) + +inst_142: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x3c00; + valaddr_reg:x5; val_offset:236*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 236*FLEN/8, x9, x1, x3) + +inst_143: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xbc00; + valaddr_reg:x5; val_offset:238*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 238*FLEN/8, x9, x1, x3) + +inst_144: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x0; + valaddr_reg:x5; val_offset:240*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 240*FLEN/8, x9, x1, x3) + +inst_145: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x8000; + valaddr_reg:x5; val_offset:242*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 242*FLEN/8, x9, x1, x3) + +inst_146: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x1; + valaddr_reg:x5; val_offset:244*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 244*FLEN/8, x9, x1, x3) + +inst_147: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x8001; + valaddr_reg:x5; val_offset:246*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 246*FLEN/8, x9, x1, x3) + +inst_148: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x2; + valaddr_reg:x5; val_offset:248*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 248*FLEN/8, x9, x1, x3) + +inst_149: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x83fe; + valaddr_reg:x5; val_offset:250*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 250*FLEN/8, x9, x1, x3) + +inst_150: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x3ff; + valaddr_reg:x5; val_offset:252*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 252*FLEN/8, x9, x1, x3) + +inst_151: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x83ff; + valaddr_reg:x5; val_offset:254*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 254*FLEN/8, x9, x1, x3) + +inst_152: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x400; + valaddr_reg:x5; val_offset:256*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 256*FLEN/8, x9, x1, x3) + +inst_153: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x8400; + valaddr_reg:x5; val_offset:258*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 258*FLEN/8, x9, x1, x3) + +inst_154: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x401; + valaddr_reg:x5; val_offset:260*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 260*FLEN/8, x9, x1, x3) + +inst_155: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x8455; + valaddr_reg:x5; val_offset:262*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 262*FLEN/8, x9, x1, x3) + +inst_156: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7bff; + valaddr_reg:x5; val_offset:264*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 264*FLEN/8, x9, x1, x3) + +inst_157: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xfbff; + valaddr_reg:x5; val_offset:266*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 266*FLEN/8, x9, x1, x3) + +inst_158: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7c00; + valaddr_reg:x5; val_offset:268*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 268*FLEN/8, x9, x1, x3) + +inst_159: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xfc00; + valaddr_reg:x5; val_offset:270*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 270*FLEN/8, x9, x1, x3) +RVTEST_SIGBASE(x1,signature_x1_2) + +inst_160: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7e00; + valaddr_reg:x5; val_offset:272*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 272*FLEN/8, x9, x1, x3) + +inst_161: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xfe00; + valaddr_reg:x5; val_offset:274*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 274*FLEN/8, x9, x1, x3) + +inst_162: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7e01; + valaddr_reg:x5; val_offset:276*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 276*FLEN/8, x9, x1, x3) + +inst_163: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xfe55; + valaddr_reg:x5; val_offset:278*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 278*FLEN/8, x9, x1, x3) + +inst_164: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7c01; + valaddr_reg:x5; val_offset:280*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 280*FLEN/8, x9, x1, x3) + +inst_165: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xfd55; + valaddr_reg:x5; val_offset:282*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 282*FLEN/8, x9, x1, x3) + +inst_166: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x3c00; + valaddr_reg:x5; val_offset:284*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 284*FLEN/8, x9, x1, x3) + +inst_167: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xbc00; + valaddr_reg:x5; val_offset:286*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 286*FLEN/8, x9, x1, x3) + +inst_168: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x0; + valaddr_reg:x5; val_offset:288*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 288*FLEN/8, x9, x1, x3) + +inst_169: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8000; + valaddr_reg:x5; val_offset:290*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 290*FLEN/8, x9, x1, x3) + +inst_170: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x1; + valaddr_reg:x5; val_offset:292*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 292*FLEN/8, x9, x1, x3) + +inst_171: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8001; + valaddr_reg:x5; val_offset:294*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 294*FLEN/8, x9, x1, x3) + +inst_172: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x2; + valaddr_reg:x5; val_offset:296*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 296*FLEN/8, x9, x1, x3) + +inst_173: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x83fe; + valaddr_reg:x5; val_offset:298*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 298*FLEN/8, x9, x1, x3) + +inst_174: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x3ff; + valaddr_reg:x5; val_offset:300*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 300*FLEN/8, x9, x1, x3) + +inst_175: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x83ff; + valaddr_reg:x5; val_offset:302*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 302*FLEN/8, x9, x1, x3) + +inst_176: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x400; + valaddr_reg:x5; val_offset:304*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 304*FLEN/8, x9, x1, x3) + +inst_177: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8400; + valaddr_reg:x5; val_offset:306*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 306*FLEN/8, x9, x1, x3) + +inst_178: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x401; + valaddr_reg:x5; val_offset:308*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 308*FLEN/8, x9, x1, x3) + +inst_179: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8455; + valaddr_reg:x5; val_offset:310*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 310*FLEN/8, x9, x1, x3) + +inst_180: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x7bff; + valaddr_reg:x5; val_offset:312*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 312*FLEN/8, x9, x1, x3) + +inst_181: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xfbff; + valaddr_reg:x5; val_offset:314*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 314*FLEN/8, x9, x1, x3) + +inst_182: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x7c00; + valaddr_reg:x5; val_offset:316*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 316*FLEN/8, x9, x1, x3) + +inst_183: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xfc00; + valaddr_reg:x5; val_offset:318*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 318*FLEN/8, x9, x1, x3) + +inst_184: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x7e00; + valaddr_reg:x5; val_offset:320*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 320*FLEN/8, x9, x1, x3) + +inst_185: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xfe00; + valaddr_reg:x5; val_offset:322*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 322*FLEN/8, x9, x1, x3) + +inst_186: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x7e01; + valaddr_reg:x5; val_offset:324*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 324*FLEN/8, x9, x1, x3) + +inst_187: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xfe55; + valaddr_reg:x5; val_offset:326*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 326*FLEN/8, x9, x1, x3) + +inst_188: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x7c01; + valaddr_reg:x5; val_offset:328*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 328*FLEN/8, x9, x1, x3) + +inst_189: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xfd55; + valaddr_reg:x5; val_offset:330*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 330*FLEN/8, x9, x1, x3) + +inst_190: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x3c00; + valaddr_reg:x5; val_offset:332*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 332*FLEN/8, x9, x1, x3) + +inst_191: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xbc00; + valaddr_reg:x5; val_offset:334*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 334*FLEN/8, x9, x1, x3) + +inst_192: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x0; + valaddr_reg:x5; val_offset:336*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 336*FLEN/8, x9, x1, x3) + +inst_193: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x8000; + valaddr_reg:x5; val_offset:338*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 338*FLEN/8, x9, x1, x3) + +inst_194: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x1; + valaddr_reg:x5; val_offset:340*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 340*FLEN/8, x9, x1, x3) + +inst_195: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x8001; + valaddr_reg:x5; val_offset:342*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 342*FLEN/8, x9, x1, x3) + +inst_196: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x2; + valaddr_reg:x5; val_offset:344*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 344*FLEN/8, x9, x1, x3) + +inst_197: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x83fe; + valaddr_reg:x5; val_offset:346*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 346*FLEN/8, x9, x1, x3) + +inst_198: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x3ff; + valaddr_reg:x5; val_offset:348*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 348*FLEN/8, x9, x1, x3) + +inst_199: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x83ff; + valaddr_reg:x5; val_offset:350*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 350*FLEN/8, x9, x1, x3) + +inst_200: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x400; + valaddr_reg:x5; val_offset:352*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 352*FLEN/8, x9, x1, x3) + +inst_201: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x8400; + valaddr_reg:x5; val_offset:354*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 354*FLEN/8, x9, x1, x3) + +inst_202: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x401; + valaddr_reg:x5; val_offset:356*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 356*FLEN/8, x9, x1, x3) + +inst_203: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x8455; + valaddr_reg:x5; val_offset:358*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 358*FLEN/8, x9, x1, x3) + +inst_204: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7bff; + valaddr_reg:x5; val_offset:360*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 360*FLEN/8, x9, x1, x3) + +inst_205: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xfbff; + valaddr_reg:x5; val_offset:362*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 362*FLEN/8, x9, x1, x3) + +inst_206: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7c00; + valaddr_reg:x5; val_offset:364*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 364*FLEN/8, x9, x1, x3) + +inst_207: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xfc00; + valaddr_reg:x5; val_offset:366*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 366*FLEN/8, x9, x1, x3) + +inst_208: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7e00; + valaddr_reg:x5; val_offset:368*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 368*FLEN/8, x9, x1, x3) + +inst_209: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xfe00; + valaddr_reg:x5; val_offset:370*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 370*FLEN/8, x9, x1, x3) + +inst_210: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7e01; + valaddr_reg:x5; val_offset:372*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 372*FLEN/8, x9, x1, x3) + +inst_211: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xfe55; + valaddr_reg:x5; val_offset:374*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 374*FLEN/8, x9, x1, x3) + +inst_212: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7c01; + valaddr_reg:x5; val_offset:376*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 376*FLEN/8, x9, x1, x3) + +inst_213: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xfd55; + valaddr_reg:x5; val_offset:378*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 378*FLEN/8, x9, x1, x3) + +inst_214: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x3c00; + valaddr_reg:x5; val_offset:380*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 380*FLEN/8, x9, x1, x3) + +inst_215: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xbc00; + valaddr_reg:x5; val_offset:382*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 382*FLEN/8, x9, x1, x3) + +inst_216: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x0; + valaddr_reg:x5; val_offset:384*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 384*FLEN/8, x9, x1, x3) + +inst_217: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8000; + valaddr_reg:x5; val_offset:386*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 386*FLEN/8, x9, x1, x3) + +inst_218: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x1; + valaddr_reg:x5; val_offset:388*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 388*FLEN/8, x9, x1, x3) + +inst_219: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8001; + valaddr_reg:x5; val_offset:390*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 390*FLEN/8, x9, x1, x3) + +inst_220: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x2; + valaddr_reg:x5; val_offset:392*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 392*FLEN/8, x9, x1, x3) + +inst_221: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x83fe; + valaddr_reg:x5; val_offset:394*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 394*FLEN/8, x9, x1, x3) + +inst_222: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x3ff; + valaddr_reg:x5; val_offset:396*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 396*FLEN/8, x9, x1, x3) + +inst_223: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x83ff; + valaddr_reg:x5; val_offset:398*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 398*FLEN/8, x9, x1, x3) + +inst_224: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x400; + valaddr_reg:x5; val_offset:400*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 400*FLEN/8, x9, x1, x3) + +inst_225: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8400; + valaddr_reg:x5; val_offset:402*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 402*FLEN/8, x9, x1, x3) + +inst_226: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x401; + valaddr_reg:x5; val_offset:404*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 404*FLEN/8, x9, x1, x3) + +inst_227: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8455; + valaddr_reg:x5; val_offset:406*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 406*FLEN/8, x9, x1, x3) + +inst_228: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x7bff; + valaddr_reg:x5; val_offset:408*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 408*FLEN/8, x9, x1, x3) + +inst_229: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xfbff; + valaddr_reg:x5; val_offset:410*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 410*FLEN/8, x9, x1, x3) + +inst_230: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x7c00; + valaddr_reg:x5; val_offset:412*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 412*FLEN/8, x9, x1, x3) + +inst_231: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xfc00; + valaddr_reg:x5; val_offset:414*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 414*FLEN/8, x9, x1, x3) + +inst_232: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x7e00; + valaddr_reg:x5; val_offset:416*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 416*FLEN/8, x9, x1, x3) + +inst_233: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xfe00; + valaddr_reg:x5; val_offset:418*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 418*FLEN/8, x9, x1, x3) + +inst_234: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x7e01; + valaddr_reg:x5; val_offset:420*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 420*FLEN/8, x9, x1, x3) + +inst_235: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xfe55; + valaddr_reg:x5; val_offset:422*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 422*FLEN/8, x9, x1, x3) + +inst_236: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x7c01; + valaddr_reg:x5; val_offset:424*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 424*FLEN/8, x9, x1, x3) + +inst_237: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xfd55; + valaddr_reg:x5; val_offset:426*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 426*FLEN/8, x9, x1, x3) + +inst_238: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x3c00; + valaddr_reg:x5; val_offset:428*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 428*FLEN/8, x9, x1, x3) + +inst_239: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xbc00; + valaddr_reg:x5; val_offset:430*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 430*FLEN/8, x9, x1, x3) + +inst_240: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x0; + valaddr_reg:x5; val_offset:432*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 432*FLEN/8, x9, x1, x3) + +inst_241: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x8000; + valaddr_reg:x5; val_offset:434*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 434*FLEN/8, x9, x1, x3) + +inst_242: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x1; + valaddr_reg:x5; val_offset:436*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 436*FLEN/8, x9, x1, x3) + +inst_243: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x8001; + valaddr_reg:x5; val_offset:438*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 438*FLEN/8, x9, x1, x3) + +inst_244: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x2; + valaddr_reg:x5; val_offset:440*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 440*FLEN/8, x9, x1, x3) + +inst_245: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x83fe; + valaddr_reg:x5; val_offset:442*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 442*FLEN/8, x9, x1, x3) + +inst_246: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x3ff; + valaddr_reg:x5; val_offset:444*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 444*FLEN/8, x9, x1, x3) + +inst_247: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x83ff; + valaddr_reg:x5; val_offset:446*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 446*FLEN/8, x9, x1, x3) + +inst_248: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x400; + valaddr_reg:x5; val_offset:448*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 448*FLEN/8, x9, x1, x3) + +inst_249: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x8400; + valaddr_reg:x5; val_offset:450*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 450*FLEN/8, x9, x1, x3) + +inst_250: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x401; + valaddr_reg:x5; val_offset:452*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 452*FLEN/8, x9, x1, x3) + +inst_251: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x8455; + valaddr_reg:x5; val_offset:454*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 454*FLEN/8, x9, x1, x3) + +inst_252: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x7bff; + valaddr_reg:x5; val_offset:456*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 456*FLEN/8, x9, x1, x3) + +inst_253: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xfbff; + valaddr_reg:x5; val_offset:458*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 458*FLEN/8, x9, x1, x3) + +inst_254: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x7c00; + valaddr_reg:x5; val_offset:460*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 460*FLEN/8, x9, x1, x3) + +inst_255: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xfc00; + valaddr_reg:x5; val_offset:462*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 462*FLEN/8, x9, x1, x3) + +inst_256: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x7e00; + valaddr_reg:x5; val_offset:464*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 464*FLEN/8, x9, x1, x3) + +inst_257: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xfe00; + valaddr_reg:x5; val_offset:466*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 466*FLEN/8, x9, x1, x3) + +inst_258: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x7e01; + valaddr_reg:x5; val_offset:468*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 468*FLEN/8, x9, x1, x3) + +inst_259: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xfe55; + valaddr_reg:x5; val_offset:470*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 470*FLEN/8, x9, x1, x3) + +inst_260: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x7c01; + valaddr_reg:x5; val_offset:472*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 472*FLEN/8, x9, x1, x3) + +inst_261: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xfd55; + valaddr_reg:x5; val_offset:474*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 474*FLEN/8, x9, x1, x3) + +inst_262: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x3c00; + valaddr_reg:x5; val_offset:476*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 476*FLEN/8, x9, x1, x3) + +inst_263: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0xbc00; + valaddr_reg:x5; val_offset:478*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 478*FLEN/8, x9, x1, x3) + +inst_264: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x0; + valaddr_reg:x5; val_offset:480*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 480*FLEN/8, x9, x1, x3) + +inst_265: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x8000; + valaddr_reg:x5; val_offset:482*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 482*FLEN/8, x9, x1, x3) + +inst_266: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x1; + valaddr_reg:x5; val_offset:484*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 484*FLEN/8, x9, x1, x3) + +inst_267: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x8001; + valaddr_reg:x5; val_offset:486*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 486*FLEN/8, x9, x1, x3) + +inst_268: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x2; + valaddr_reg:x5; val_offset:488*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 488*FLEN/8, x9, x1, x3) + +inst_269: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x83fe; + valaddr_reg:x5; val_offset:490*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 490*FLEN/8, x9, x1, x3) + +inst_270: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x3ff; + valaddr_reg:x5; val_offset:492*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 492*FLEN/8, x9, x1, x3) + +inst_271: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x83ff; + valaddr_reg:x5; val_offset:494*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 494*FLEN/8, x9, x1, x3) + +inst_272: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x400; + valaddr_reg:x5; val_offset:496*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 496*FLEN/8, x9, x1, x3) + +inst_273: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x8400; + valaddr_reg:x5; val_offset:498*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 498*FLEN/8, x9, x1, x3) + +inst_274: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x401; + valaddr_reg:x5; val_offset:500*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 500*FLEN/8, x9, x1, x3) + +inst_275: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x8455; + valaddr_reg:x5; val_offset:502*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 502*FLEN/8, x9, x1, x3) + +inst_276: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x7bff; + valaddr_reg:x5; val_offset:504*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 504*FLEN/8, x9, x1, x3) + +inst_277: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xfbff; + valaddr_reg:x5; val_offset:506*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 506*FLEN/8, x9, x1, x3) + +inst_278: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x7c00; + valaddr_reg:x5; val_offset:508*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 508*FLEN/8, x9, x1, x3) + +inst_279: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xfc00; + valaddr_reg:x5; val_offset:510*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 510*FLEN/8, x9, x1, x3) + +inst_280: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x7e00; + valaddr_reg:x5; val_offset:512*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 512*FLEN/8, x9, x1, x3) + +inst_281: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xfe00; + valaddr_reg:x5; val_offset:514*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 514*FLEN/8, x9, x1, x3) + +inst_282: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x7e01; + valaddr_reg:x5; val_offset:516*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 516*FLEN/8, x9, x1, x3) + +inst_283: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xfe55; + valaddr_reg:x5; val_offset:518*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 518*FLEN/8, x9, x1, x3) + +inst_284: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x7c01; + valaddr_reg:x5; val_offset:520*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 520*FLEN/8, x9, x1, x3) + +inst_285: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xfd55; + valaddr_reg:x5; val_offset:522*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 522*FLEN/8, x9, x1, x3) + +inst_286: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0x3c00; + valaddr_reg:x5; val_offset:524*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 524*FLEN/8, x9, x1, x3) + +inst_287: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8455; op2val:0xbc00; + valaddr_reg:x5; val_offset:526*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 526*FLEN/8, x9, x1, x3) +RVTEST_SIGBASE(x1,signature_x1_3) + +inst_288: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x0; + valaddr_reg:x5; val_offset:528*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 528*FLEN/8, x9, x1, x3) + +inst_289: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8000; + valaddr_reg:x5; val_offset:530*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 530*FLEN/8, x9, x1, x3) + +inst_290: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x1; + valaddr_reg:x5; val_offset:532*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 532*FLEN/8, x9, x1, x3) + +inst_291: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8001; + valaddr_reg:x5; val_offset:534*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 534*FLEN/8, x9, x1, x3) + +inst_292: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x2; + valaddr_reg:x5; val_offset:536*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 536*FLEN/8, x9, x1, x3) + +inst_293: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x83fe; + valaddr_reg:x5; val_offset:538*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 538*FLEN/8, x9, x1, x3) + +inst_294: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x3ff; + valaddr_reg:x5; val_offset:540*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 540*FLEN/8, x9, x1, x3) + +inst_295: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x83ff; + valaddr_reg:x5; val_offset:542*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 542*FLEN/8, x9, x1, x3) + +inst_296: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x400; + valaddr_reg:x5; val_offset:544*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 544*FLEN/8, x9, x1, x3) + +inst_297: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8400; + valaddr_reg:x5; val_offset:546*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 546*FLEN/8, x9, x1, x3) + +inst_298: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x401; + valaddr_reg:x5; val_offset:548*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 548*FLEN/8, x9, x1, x3) + +inst_299: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8455; + valaddr_reg:x5; val_offset:550*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 550*FLEN/8, x9, x1, x3) + +inst_300: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7bff; + valaddr_reg:x5; val_offset:552*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 552*FLEN/8, x9, x1, x3) + +inst_301: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xfbff; + valaddr_reg:x5; val_offset:554*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 554*FLEN/8, x9, x1, x3) + +inst_302: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7c00; + valaddr_reg:x5; val_offset:556*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 556*FLEN/8, x9, x1, x3) + +inst_303: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xfc00; + valaddr_reg:x5; val_offset:558*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 558*FLEN/8, x9, x1, x3) + +inst_304: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7e00; + valaddr_reg:x5; val_offset:560*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 560*FLEN/8, x9, x1, x3) + +inst_305: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xfe00; + valaddr_reg:x5; val_offset:562*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 562*FLEN/8, x9, x1, x3) + +inst_306: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7e01; + valaddr_reg:x5; val_offset:564*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 564*FLEN/8, x9, x1, x3) + +inst_307: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xfe55; + valaddr_reg:x5; val_offset:566*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 566*FLEN/8, x9, x1, x3) + +inst_308: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7c01; + valaddr_reg:x5; val_offset:568*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 568*FLEN/8, x9, x1, x3) + +inst_309: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xfd55; + valaddr_reg:x5; val_offset:570*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 570*FLEN/8, x9, x1, x3) + +inst_310: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x3c00; + valaddr_reg:x5; val_offset:572*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 572*FLEN/8, x9, x1, x3) + +inst_311: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xbc00; + valaddr_reg:x5; val_offset:574*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 574*FLEN/8, x9, x1, x3) + +inst_312: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x0; + valaddr_reg:x5; val_offset:576*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 576*FLEN/8, x9, x1, x3) + +inst_313: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8000; + valaddr_reg:x5; val_offset:578*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 578*FLEN/8, x9, x1, x3) + +inst_314: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x1; + valaddr_reg:x5; val_offset:580*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 580*FLEN/8, x9, x1, x3) + +inst_315: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8001; + valaddr_reg:x5; val_offset:582*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 582*FLEN/8, x9, x1, x3) + +inst_316: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x2; + valaddr_reg:x5; val_offset:584*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 584*FLEN/8, x9, x1, x3) + +inst_317: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x83fe; + valaddr_reg:x5; val_offset:586*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 586*FLEN/8, x9, x1, x3) + +inst_318: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x3ff; + valaddr_reg:x5; val_offset:588*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 588*FLEN/8, x9, x1, x3) + +inst_319: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x83ff; + valaddr_reg:x5; val_offset:590*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 590*FLEN/8, x9, x1, x3) + +inst_320: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x400; + valaddr_reg:x5; val_offset:592*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 592*FLEN/8, x9, x1, x3) + +inst_321: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8400; + valaddr_reg:x5; val_offset:594*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 594*FLEN/8, x9, x1, x3) + +inst_322: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x401; + valaddr_reg:x5; val_offset:596*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 596*FLEN/8, x9, x1, x3) + +inst_323: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8455; + valaddr_reg:x5; val_offset:598*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 598*FLEN/8, x9, x1, x3) + +inst_324: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7bff; + valaddr_reg:x5; val_offset:600*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 600*FLEN/8, x9, x1, x3) + +inst_325: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfbff; + valaddr_reg:x5; val_offset:602*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 602*FLEN/8, x9, x1, x3) + +inst_326: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7c00; + valaddr_reg:x5; val_offset:604*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 604*FLEN/8, x9, x1, x3) + +inst_327: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfc00; + valaddr_reg:x5; val_offset:606*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 606*FLEN/8, x9, x1, x3) + +inst_328: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7e00; + valaddr_reg:x5; val_offset:608*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 608*FLEN/8, x9, x1, x3) + +inst_329: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfe00; + valaddr_reg:x5; val_offset:610*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 610*FLEN/8, x9, x1, x3) + +inst_330: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7e01; + valaddr_reg:x5; val_offset:612*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 612*FLEN/8, x9, x1, x3) + +inst_331: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfe55; + valaddr_reg:x5; val_offset:614*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 614*FLEN/8, x9, x1, x3) + +inst_332: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x7c01; + valaddr_reg:x5; val_offset:616*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 616*FLEN/8, x9, x1, x3) + +inst_333: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfd55; + valaddr_reg:x5; val_offset:618*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 618*FLEN/8, x9, x1, x3) + +inst_334: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x3c00; + valaddr_reg:x5; val_offset:620*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 620*FLEN/8, x9, x1, x3) + +inst_335: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xbc00; + valaddr_reg:x5; val_offset:622*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 622*FLEN/8, x9, x1, x3) + +inst_336: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x0; + valaddr_reg:x5; val_offset:624*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 624*FLEN/8, x9, x1, x3) + +inst_337: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x8000; + valaddr_reg:x5; val_offset:626*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 626*FLEN/8, x9, x1, x3) + +inst_338: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x1; + valaddr_reg:x5; val_offset:628*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 628*FLEN/8, x9, x1, x3) + +inst_339: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x8001; + valaddr_reg:x5; val_offset:630*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 630*FLEN/8, x9, x1, x3) + +inst_340: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x2; + valaddr_reg:x5; val_offset:632*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 632*FLEN/8, x9, x1, x3) + +inst_341: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x83fe; + valaddr_reg:x5; val_offset:634*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 634*FLEN/8, x9, x1, x3) + +inst_342: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x3ff; + valaddr_reg:x5; val_offset:636*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 636*FLEN/8, x9, x1, x3) + +inst_343: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x83ff; + valaddr_reg:x5; val_offset:638*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 638*FLEN/8, x9, x1, x3) + +inst_344: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x400; + valaddr_reg:x5; val_offset:640*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 640*FLEN/8, x9, x1, x3) + +inst_345: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x8400; + valaddr_reg:x5; val_offset:642*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 642*FLEN/8, x9, x1, x3) + +inst_346: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x401; + valaddr_reg:x5; val_offset:644*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 644*FLEN/8, x9, x1, x3) + +inst_347: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x8455; + valaddr_reg:x5; val_offset:646*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 646*FLEN/8, x9, x1, x3) + +inst_348: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x7bff; + valaddr_reg:x5; val_offset:648*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 648*FLEN/8, x9, x1, x3) + +inst_349: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xfbff; + valaddr_reg:x5; val_offset:650*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 650*FLEN/8, x9, x1, x3) + +inst_350: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x7c00; + valaddr_reg:x5; val_offset:652*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 652*FLEN/8, x9, x1, x3) + +inst_351: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xfc00; + valaddr_reg:x5; val_offset:654*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 654*FLEN/8, x9, x1, x3) + +inst_352: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x7e00; + valaddr_reg:x5; val_offset:656*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 656*FLEN/8, x9, x1, x3) + +inst_353: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xfe00; + valaddr_reg:x5; val_offset:658*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 658*FLEN/8, x9, x1, x3) + +inst_354: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x7e01; + valaddr_reg:x5; val_offset:660*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 660*FLEN/8, x9, x1, x3) + +inst_355: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xfe55; + valaddr_reg:x5; val_offset:662*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 662*FLEN/8, x9, x1, x3) + +inst_356: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x7c01; + valaddr_reg:x5; val_offset:664*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 664*FLEN/8, x9, x1, x3) + +inst_357: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xfd55; + valaddr_reg:x5; val_offset:666*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 666*FLEN/8, x9, x1, x3) + +inst_358: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0x3c00; + valaddr_reg:x5; val_offset:668*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 668*FLEN/8, x9, x1, x3) + +inst_359: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c00; op2val:0xbc00; + valaddr_reg:x5; val_offset:670*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 670*FLEN/8, x9, x1, x3) + +inst_360: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x0; + valaddr_reg:x5; val_offset:672*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 672*FLEN/8, x9, x1, x3) + +inst_361: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x8000; + valaddr_reg:x5; val_offset:674*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 674*FLEN/8, x9, x1, x3) + +inst_362: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x1; + valaddr_reg:x5; val_offset:676*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 676*FLEN/8, x9, x1, x3) + +inst_363: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x8001; + valaddr_reg:x5; val_offset:678*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 678*FLEN/8, x9, x1, x3) + +inst_364: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x2; + valaddr_reg:x5; val_offset:680*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 680*FLEN/8, x9, x1, x3) + +inst_365: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x83fe; + valaddr_reg:x5; val_offset:682*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 682*FLEN/8, x9, x1, x3) + +inst_366: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x3ff; + valaddr_reg:x5; val_offset:684*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 684*FLEN/8, x9, x1, x3) + +inst_367: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x83ff; + valaddr_reg:x5; val_offset:686*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 686*FLEN/8, x9, x1, x3) + +inst_368: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x400; + valaddr_reg:x5; val_offset:688*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 688*FLEN/8, x9, x1, x3) + +inst_369: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x8400; + valaddr_reg:x5; val_offset:690*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 690*FLEN/8, x9, x1, x3) + +inst_370: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x401; + valaddr_reg:x5; val_offset:692*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 692*FLEN/8, x9, x1, x3) + +inst_371: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x8455; + valaddr_reg:x5; val_offset:694*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 694*FLEN/8, x9, x1, x3) + +inst_372: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x7bff; + valaddr_reg:x5; val_offset:696*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 696*FLEN/8, x9, x1, x3) + +inst_373: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xfbff; + valaddr_reg:x5; val_offset:698*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 698*FLEN/8, x9, x1, x3) + +inst_374: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x7c00; + valaddr_reg:x5; val_offset:700*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 700*FLEN/8, x9, x1, x3) + +inst_375: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xfc00; + valaddr_reg:x5; val_offset:702*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 702*FLEN/8, x9, x1, x3) + +inst_376: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x7e00; + valaddr_reg:x5; val_offset:704*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 704*FLEN/8, x9, x1, x3) + +inst_377: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xfe00; + valaddr_reg:x5; val_offset:706*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 706*FLEN/8, x9, x1, x3) + +inst_378: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x7e01; + valaddr_reg:x5; val_offset:708*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 708*FLEN/8, x9, x1, x3) + +inst_379: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xfe55; + valaddr_reg:x5; val_offset:710*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 710*FLEN/8, x9, x1, x3) + +inst_380: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x7c01; + valaddr_reg:x5; val_offset:712*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 712*FLEN/8, x9, x1, x3) + +inst_381: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xfd55; + valaddr_reg:x5; val_offset:714*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 714*FLEN/8, x9, x1, x3) + +inst_382: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0x3c00; + valaddr_reg:x5; val_offset:716*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 716*FLEN/8, x9, x1, x3) + +inst_383: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc00; op2val:0xbc00; + valaddr_reg:x5; val_offset:718*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 718*FLEN/8, x9, x1, x3) + +inst_384: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x0; + valaddr_reg:x5; val_offset:720*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 720*FLEN/8, x9, x1, x3) + +inst_385: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x8000; + valaddr_reg:x5; val_offset:722*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 722*FLEN/8, x9, x1, x3) + +inst_386: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x1; + valaddr_reg:x5; val_offset:724*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 724*FLEN/8, x9, x1, x3) + +inst_387: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x8001; + valaddr_reg:x5; val_offset:726*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 726*FLEN/8, x9, x1, x3) + +inst_388: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x2; + valaddr_reg:x5; val_offset:728*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 728*FLEN/8, x9, x1, x3) + +inst_389: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x83fe; + valaddr_reg:x5; val_offset:730*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 730*FLEN/8, x9, x1, x3) + +inst_390: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x3ff; + valaddr_reg:x5; val_offset:732*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 732*FLEN/8, x9, x1, x3) + +inst_391: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x83ff; + valaddr_reg:x5; val_offset:734*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 734*FLEN/8, x9, x1, x3) + +inst_392: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x400; + valaddr_reg:x5; val_offset:736*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 736*FLEN/8, x9, x1, x3) + +inst_393: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x8400; + valaddr_reg:x5; val_offset:738*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 738*FLEN/8, x9, x1, x3) + +inst_394: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x401; + valaddr_reg:x5; val_offset:740*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 740*FLEN/8, x9, x1, x3) + +inst_395: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x8455; + valaddr_reg:x5; val_offset:742*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 742*FLEN/8, x9, x1, x3) + +inst_396: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x7bff; + valaddr_reg:x5; val_offset:744*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 744*FLEN/8, x9, x1, x3) + +inst_397: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xfbff; + valaddr_reg:x5; val_offset:746*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 746*FLEN/8, x9, x1, x3) + +inst_398: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x7c00; + valaddr_reg:x5; val_offset:748*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 748*FLEN/8, x9, x1, x3) + +inst_399: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xfc00; + valaddr_reg:x5; val_offset:750*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 750*FLEN/8, x9, x1, x3) + +inst_400: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x7e00; + valaddr_reg:x5; val_offset:752*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 752*FLEN/8, x9, x1, x3) + +inst_401: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xfe00; + valaddr_reg:x5; val_offset:754*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 754*FLEN/8, x9, x1, x3) + +inst_402: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x7e01; + valaddr_reg:x5; val_offset:756*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 756*FLEN/8, x9, x1, x3) + +inst_403: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xfe55; + valaddr_reg:x5; val_offset:758*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 758*FLEN/8, x9, x1, x3) + +inst_404: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x7c01; + valaddr_reg:x5; val_offset:760*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 760*FLEN/8, x9, x1, x3) + +inst_405: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xfd55; + valaddr_reg:x5; val_offset:762*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 762*FLEN/8, x9, x1, x3) + +inst_406: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0x3c00; + valaddr_reg:x5; val_offset:764*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 764*FLEN/8, x9, x1, x3) + +inst_407: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e00; op2val:0xbc00; + valaddr_reg:x5; val_offset:766*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 766*FLEN/8, x9, x1, x3) + +inst_408: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x0; + valaddr_reg:x5; val_offset:768*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 768*FLEN/8, x9, x1, x3) + +inst_409: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x8000; + valaddr_reg:x5; val_offset:770*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 770*FLEN/8, x9, x1, x3) + +inst_410: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x1; + valaddr_reg:x5; val_offset:772*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 772*FLEN/8, x9, x1, x3) + +inst_411: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x8001; + valaddr_reg:x5; val_offset:774*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 774*FLEN/8, x9, x1, x3) + +inst_412: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x2; + valaddr_reg:x5; val_offset:776*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 776*FLEN/8, x9, x1, x3) + +inst_413: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x83fe; + valaddr_reg:x5; val_offset:778*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 778*FLEN/8, x9, x1, x3) + +inst_414: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x3ff; + valaddr_reg:x5; val_offset:780*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 780*FLEN/8, x9, x1, x3) + +inst_415: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x83ff; + valaddr_reg:x5; val_offset:782*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 782*FLEN/8, x9, x1, x3) +RVTEST_SIGBASE(x1,signature_x1_4) + +inst_416: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x400; + valaddr_reg:x5; val_offset:784*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 784*FLEN/8, x9, x1, x3) + +inst_417: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x8400; + valaddr_reg:x5; val_offset:786*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 786*FLEN/8, x9, x1, x3) + +inst_418: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x401; + valaddr_reg:x5; val_offset:788*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 788*FLEN/8, x9, x1, x3) + +inst_419: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x8455; + valaddr_reg:x5; val_offset:790*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 790*FLEN/8, x9, x1, x3) + +inst_420: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x7bff; + valaddr_reg:x5; val_offset:792*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 792*FLEN/8, x9, x1, x3) + +inst_421: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xfbff; + valaddr_reg:x5; val_offset:794*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 794*FLEN/8, x9, x1, x3) + +inst_422: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x7c00; + valaddr_reg:x5; val_offset:796*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 796*FLEN/8, x9, x1, x3) + +inst_423: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xfc00; + valaddr_reg:x5; val_offset:798*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 798*FLEN/8, x9, x1, x3) + +inst_424: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x7e00; + valaddr_reg:x5; val_offset:800*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 800*FLEN/8, x9, x1, x3) + +inst_425: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xfe00; + valaddr_reg:x5; val_offset:802*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 802*FLEN/8, x9, x1, x3) + +inst_426: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x7e01; + valaddr_reg:x5; val_offset:804*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 804*FLEN/8, x9, x1, x3) + +inst_427: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xfe55; + valaddr_reg:x5; val_offset:806*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 806*FLEN/8, x9, x1, x3) + +inst_428: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x7c01; + valaddr_reg:x5; val_offset:808*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 808*FLEN/8, x9, x1, x3) + +inst_429: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xfd55; + valaddr_reg:x5; val_offset:810*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 810*FLEN/8, x9, x1, x3) + +inst_430: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0x3c00; + valaddr_reg:x5; val_offset:812*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 812*FLEN/8, x9, x1, x3) + +inst_431: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe00; op2val:0xbc00; + valaddr_reg:x5; val_offset:814*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 814*FLEN/8, x9, x1, x3) + +inst_432: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x0; + valaddr_reg:x5; val_offset:816*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 816*FLEN/8, x9, x1, x3) + +inst_433: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x8000; + valaddr_reg:x5; val_offset:818*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 818*FLEN/8, x9, x1, x3) + +inst_434: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x1; + valaddr_reg:x5; val_offset:820*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 820*FLEN/8, x9, x1, x3) + +inst_435: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x8001; + valaddr_reg:x5; val_offset:822*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 822*FLEN/8, x9, x1, x3) + +inst_436: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x2; + valaddr_reg:x5; val_offset:824*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 824*FLEN/8, x9, x1, x3) + +inst_437: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x83fe; + valaddr_reg:x5; val_offset:826*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 826*FLEN/8, x9, x1, x3) + +inst_438: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x3ff; + valaddr_reg:x5; val_offset:828*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 828*FLEN/8, x9, x1, x3) + +inst_439: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x83ff; + valaddr_reg:x5; val_offset:830*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 830*FLEN/8, x9, x1, x3) + +inst_440: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x400; + valaddr_reg:x5; val_offset:832*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 832*FLEN/8, x9, x1, x3) + +inst_441: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x8400; + valaddr_reg:x5; val_offset:834*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 834*FLEN/8, x9, x1, x3) + +inst_442: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x401; + valaddr_reg:x5; val_offset:836*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 836*FLEN/8, x9, x1, x3) + +inst_443: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x8455; + valaddr_reg:x5; val_offset:838*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 838*FLEN/8, x9, x1, x3) + +inst_444: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x7bff; + valaddr_reg:x5; val_offset:840*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 840*FLEN/8, x9, x1, x3) + +inst_445: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xfbff; + valaddr_reg:x5; val_offset:842*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 842*FLEN/8, x9, x1, x3) + +inst_446: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x7c00; + valaddr_reg:x5; val_offset:844*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 844*FLEN/8, x9, x1, x3) + +inst_447: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xfc00; + valaddr_reg:x5; val_offset:846*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 846*FLEN/8, x9, x1, x3) + +inst_448: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x7e00; + valaddr_reg:x5; val_offset:848*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 848*FLEN/8, x9, x1, x3) + +inst_449: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xfe00; + valaddr_reg:x5; val_offset:850*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 850*FLEN/8, x9, x1, x3) + +inst_450: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x7e01; + valaddr_reg:x5; val_offset:852*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 852*FLEN/8, x9, x1, x3) + +inst_451: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xfe55; + valaddr_reg:x5; val_offset:854*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 854*FLEN/8, x9, x1, x3) + +inst_452: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x7c01; + valaddr_reg:x5; val_offset:856*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 856*FLEN/8, x9, x1, x3) + +inst_453: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xfd55; + valaddr_reg:x5; val_offset:858*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 858*FLEN/8, x9, x1, x3) + +inst_454: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0x3c00; + valaddr_reg:x5; val_offset:860*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 860*FLEN/8, x9, x1, x3) + +inst_455: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e01; op2val:0xbc00; + valaddr_reg:x5; val_offset:862*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 862*FLEN/8, x9, x1, x3) + +inst_456: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x0; + valaddr_reg:x5; val_offset:864*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 864*FLEN/8, x9, x1, x3) + +inst_457: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x8000; + valaddr_reg:x5; val_offset:866*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 866*FLEN/8, x9, x1, x3) + +inst_458: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x1; + valaddr_reg:x5; val_offset:868*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 868*FLEN/8, x9, x1, x3) + +inst_459: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x8001; + valaddr_reg:x5; val_offset:870*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 870*FLEN/8, x9, x1, x3) + +inst_460: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x2; + valaddr_reg:x5; val_offset:872*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 872*FLEN/8, x9, x1, x3) + +inst_461: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x83fe; + valaddr_reg:x5; val_offset:874*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 874*FLEN/8, x9, x1, x3) + +inst_462: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x3ff; + valaddr_reg:x5; val_offset:876*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 876*FLEN/8, x9, x1, x3) + +inst_463: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x83ff; + valaddr_reg:x5; val_offset:878*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 878*FLEN/8, x9, x1, x3) + +inst_464: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x400; + valaddr_reg:x5; val_offset:880*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 880*FLEN/8, x9, x1, x3) + +inst_465: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x8400; + valaddr_reg:x5; val_offset:882*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 882*FLEN/8, x9, x1, x3) + +inst_466: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x401; + valaddr_reg:x5; val_offset:884*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 884*FLEN/8, x9, x1, x3) + +inst_467: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x8455; + valaddr_reg:x5; val_offset:886*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 886*FLEN/8, x9, x1, x3) + +inst_468: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x7bff; + valaddr_reg:x5; val_offset:888*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 888*FLEN/8, x9, x1, x3) + +inst_469: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xfbff; + valaddr_reg:x5; val_offset:890*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 890*FLEN/8, x9, x1, x3) + +inst_470: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x7c00; + valaddr_reg:x5; val_offset:892*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 892*FLEN/8, x9, x1, x3) + +inst_471: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xfc00; + valaddr_reg:x5; val_offset:894*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 894*FLEN/8, x9, x1, x3) + +inst_472: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x7e00; + valaddr_reg:x5; val_offset:896*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 896*FLEN/8, x9, x1, x3) + +inst_473: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xfe00; + valaddr_reg:x5; val_offset:898*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 898*FLEN/8, x9, x1, x3) + +inst_474: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x7e01; + valaddr_reg:x5; val_offset:900*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 900*FLEN/8, x9, x1, x3) + +inst_475: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xfe55; + valaddr_reg:x5; val_offset:902*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 902*FLEN/8, x9, x1, x3) + +inst_476: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x7c01; + valaddr_reg:x5; val_offset:904*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 904*FLEN/8, x9, x1, x3) + +inst_477: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xfd55; + valaddr_reg:x5; val_offset:906*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 906*FLEN/8, x9, x1, x3) + +inst_478: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0x3c00; + valaddr_reg:x5; val_offset:908*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 908*FLEN/8, x9, x1, x3) + +inst_479: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe55; op2val:0xbc00; + valaddr_reg:x5; val_offset:910*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 910*FLEN/8, x9, x1, x3) + +inst_480: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x0; + valaddr_reg:x5; val_offset:912*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 912*FLEN/8, x9, x1, x3) + +inst_481: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x8000; + valaddr_reg:x5; val_offset:914*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 914*FLEN/8, x9, x1, x3) + +inst_482: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x1; + valaddr_reg:x5; val_offset:916*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 916*FLEN/8, x9, x1, x3) + +inst_483: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x8001; + valaddr_reg:x5; val_offset:918*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 918*FLEN/8, x9, x1, x3) + +inst_484: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x2; + valaddr_reg:x5; val_offset:920*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 920*FLEN/8, x9, x1, x3) + +inst_485: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x83fe; + valaddr_reg:x5; val_offset:922*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 922*FLEN/8, x9, x1, x3) + +inst_486: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x3ff; + valaddr_reg:x5; val_offset:924*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 924*FLEN/8, x9, x1, x3) + +inst_487: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x83ff; + valaddr_reg:x5; val_offset:926*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 926*FLEN/8, x9, x1, x3) + +inst_488: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x400; + valaddr_reg:x5; val_offset:928*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 928*FLEN/8, x9, x1, x3) + +inst_489: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x8400; + valaddr_reg:x5; val_offset:930*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 930*FLEN/8, x9, x1, x3) + +inst_490: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x401; + valaddr_reg:x5; val_offset:932*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 932*FLEN/8, x9, x1, x3) + +inst_491: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x8455; + valaddr_reg:x5; val_offset:934*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 934*FLEN/8, x9, x1, x3) + +inst_492: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x7bff; + valaddr_reg:x5; val_offset:936*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 936*FLEN/8, x9, x1, x3) + +inst_493: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xfbff; + valaddr_reg:x5; val_offset:938*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 938*FLEN/8, x9, x1, x3) + +inst_494: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x7c00; + valaddr_reg:x5; val_offset:940*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 940*FLEN/8, x9, x1, x3) + +inst_495: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xfc00; + valaddr_reg:x5; val_offset:942*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 942*FLEN/8, x9, x1, x3) + +inst_496: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x7e00; + valaddr_reg:x5; val_offset:944*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 944*FLEN/8, x9, x1, x3) + +inst_497: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xfe00; + valaddr_reg:x5; val_offset:946*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 946*FLEN/8, x9, x1, x3) + +inst_498: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x7e01; + valaddr_reg:x5; val_offset:948*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 948*FLEN/8, x9, x1, x3) + +inst_499: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xfe55; + valaddr_reg:x5; val_offset:950*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 950*FLEN/8, x9, x1, x3) + +inst_500: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x7c01; + valaddr_reg:x5; val_offset:952*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 952*FLEN/8, x9, x1, x3) + +inst_501: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xfd55; + valaddr_reg:x5; val_offset:954*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 954*FLEN/8, x9, x1, x3) + +inst_502: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0x3c00; + valaddr_reg:x5; val_offset:956*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 956*FLEN/8, x9, x1, x3) + +inst_503: +// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c01; op2val:0xbc00; + valaddr_reg:x5; val_offset:958*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 958*FLEN/8, x9, x1, x3) + +inst_504: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x0; + valaddr_reg:x5; val_offset:960*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 960*FLEN/8, x9, x1, x3) + +inst_505: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x8000; + valaddr_reg:x5; val_offset:962*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 962*FLEN/8, x9, x1, x3) + +inst_506: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x1; + valaddr_reg:x5; val_offset:964*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 964*FLEN/8, x9, x1, x3) + +inst_507: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x8001; + valaddr_reg:x5; val_offset:966*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 966*FLEN/8, x9, x1, x3) + +inst_508: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x2; + valaddr_reg:x5; val_offset:968*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 968*FLEN/8, x9, x1, x3) + +inst_509: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x83fe; + valaddr_reg:x5; val_offset:970*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 970*FLEN/8, x9, x1, x3) + +inst_510: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x3ff; + valaddr_reg:x5; val_offset:972*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 972*FLEN/8, x9, x1, x3) + +inst_511: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x83ff; + valaddr_reg:x5; val_offset:974*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 974*FLEN/8, x9, x1, x3) + +inst_512: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x400; + valaddr_reg:x5; val_offset:976*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 976*FLEN/8, x9, x1, x3) + +inst_513: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x8400; + valaddr_reg:x5; val_offset:978*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 978*FLEN/8, x9, x1, x3) + +inst_514: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x401; + valaddr_reg:x5; val_offset:980*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 980*FLEN/8, x9, x1, x3) + +inst_515: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x8455; + valaddr_reg:x5; val_offset:982*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 982*FLEN/8, x9, x1, x3) + +inst_516: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x7bff; + valaddr_reg:x5; val_offset:984*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 984*FLEN/8, x9, x1, x3) + +inst_517: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xfbff; + valaddr_reg:x5; val_offset:986*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 986*FLEN/8, x9, x1, x3) + +inst_518: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x7c00; + valaddr_reg:x5; val_offset:988*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 988*FLEN/8, x9, x1, x3) + +inst_519: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xfc00; + valaddr_reg:x5; val_offset:990*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 990*FLEN/8, x9, x1, x3) + +inst_520: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x7e00; + valaddr_reg:x5; val_offset:992*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 992*FLEN/8, x9, x1, x3) + +inst_521: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xfe00; + valaddr_reg:x5; val_offset:994*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 994*FLEN/8, x9, x1, x3) + +inst_522: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x7e01; + valaddr_reg:x5; val_offset:996*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 996*FLEN/8, x9, x1, x3) + +inst_523: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xfe55; + valaddr_reg:x5; val_offset:998*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 998*FLEN/8, x9, x1, x3) + +inst_524: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x7c01; + valaddr_reg:x5; val_offset:1000*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 1000*FLEN/8, x9, x1, x3) + +inst_525: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xfd55; + valaddr_reg:x5; val_offset:1002*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 1002*FLEN/8, x9, x1, x3) + +inst_526: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0x3c00; + valaddr_reg:x5; val_offset:1004*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 1004*FLEN/8, x9, x1, x3) + +inst_527: +// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfd55; op2val:0xbc00; + valaddr_reg:x5; val_offset:1006*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 1006*FLEN/8, x9, x1, x3) + +inst_528: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x0; + valaddr_reg:x5; val_offset:1008*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 1008*FLEN/8, x9, x1, x3) + +inst_529: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x8000; + valaddr_reg:x5; val_offset:1010*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 1010*FLEN/8, x9, x1, x3) + +inst_530: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x1; + valaddr_reg:x5; val_offset:1012*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 1012*FLEN/8, x9, x1, x3) + +inst_531: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x8001; + valaddr_reg:x5; val_offset:1014*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 1014*FLEN/8, x9, x1, x3) + +inst_532: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2; + valaddr_reg:x5; val_offset:1016*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 1016*FLEN/8, x9, x1, x3) + +inst_533: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x83fe; + valaddr_reg:x5; val_offset:1018*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 1018*FLEN/8, x9, x1, x3) + +inst_534: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3ff; + valaddr_reg:x5; val_offset:1020*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 1020*FLEN/8, x9, x1, x3) + +inst_535: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x83ff; + valaddr_reg:x5; val_offset:1022*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 1022*FLEN/8, x9, x1, x3) + +inst_536: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x400; + valaddr_reg:x5; val_offset:1024*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 1024*FLEN/8, x9, x1, x3) + +inst_537: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x8400; + valaddr_reg:x5; val_offset:1026*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 1026*FLEN/8, x9, x1, x3) + +inst_538: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x401; + valaddr_reg:x5; val_offset:1028*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 1028*FLEN/8, x9, x1, x3) + +inst_539: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x8455; + valaddr_reg:x5; val_offset:1030*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 1030*FLEN/8, x9, x1, x3) + +inst_540: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7bff; + valaddr_reg:x5; val_offset:1032*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 1032*FLEN/8, x9, x1, x3) + +inst_541: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xfbff; + valaddr_reg:x5; val_offset:1034*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 1034*FLEN/8, x9, x1, x3) + +inst_542: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7c00; + valaddr_reg:x5; val_offset:1036*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 1036*FLEN/8, x9, x1, x3) + +inst_543: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xfc00; + valaddr_reg:x5; val_offset:1038*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 1038*FLEN/8, x9, x1, x3) +RVTEST_SIGBASE(x1,signature_x1_5) + +inst_544: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7e00; + valaddr_reg:x5; val_offset:1040*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 1040*FLEN/8, x9, x1, x3) + +inst_545: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xfe00; + valaddr_reg:x5; val_offset:1042*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 1042*FLEN/8, x9, x1, x3) + +inst_546: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7e01; + valaddr_reg:x5; val_offset:1044*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 1044*FLEN/8, x9, x1, x3) + +inst_547: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xfe55; + valaddr_reg:x5; val_offset:1046*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 1046*FLEN/8, x9, x1, x3) + +inst_548: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7c01; + valaddr_reg:x5; val_offset:1048*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 1048*FLEN/8, x9, x1, x3) + +inst_549: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xfd55; + valaddr_reg:x5; val_offset:1050*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 1050*FLEN/8, x9, x1, x3) + +inst_550: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3c00; + valaddr_reg:x5; val_offset:1052*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 1052*FLEN/8, x9, x1, x3) + +inst_551: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0xbc00; + valaddr_reg:x5; val_offset:1054*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 1054*FLEN/8, x9, x1, x3) + +inst_552: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x0; + valaddr_reg:x5; val_offset:1056*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 1056*FLEN/8, x9, x1, x3) + +inst_553: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x8000; + valaddr_reg:x5; val_offset:1058*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 1058*FLEN/8, x9, x1, x3) + +inst_554: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x1; + valaddr_reg:x5; val_offset:1060*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 1060*FLEN/8, x9, x1, x3) + +inst_555: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x8001; + valaddr_reg:x5; val_offset:1062*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 1062*FLEN/8, x9, x1, x3) + +inst_556: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x2; + valaddr_reg:x5; val_offset:1064*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 1064*FLEN/8, x9, x1, x3) + +inst_557: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x83fe; + valaddr_reg:x5; val_offset:1066*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 1066*FLEN/8, x9, x1, x3) + +inst_558: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x3ff; + valaddr_reg:x5; val_offset:1068*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 1068*FLEN/8, x9, x1, x3) + +inst_559: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x83ff; + valaddr_reg:x5; val_offset:1070*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 1070*FLEN/8, x9, x1, x3) + +inst_560: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x400; + valaddr_reg:x5; val_offset:1072*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 1072*FLEN/8, x9, x1, x3) + +inst_561: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x8400; + valaddr_reg:x5; val_offset:1074*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 1074*FLEN/8, x9, x1, x3) + +inst_562: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x401; + valaddr_reg:x5; val_offset:1076*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 1076*FLEN/8, x9, x1, x3) + +inst_563: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x8455; + valaddr_reg:x5; val_offset:1078*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 1078*FLEN/8, x9, x1, x3) + +inst_564: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x7bff; + valaddr_reg:x5; val_offset:1080*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 1080*FLEN/8, x9, x1, x3) + +inst_565: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xfbff; + valaddr_reg:x5; val_offset:1082*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 1082*FLEN/8, x9, x1, x3) + +inst_566: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x7c00; + valaddr_reg:x5; val_offset:1084*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 1084*FLEN/8, x9, x1, x3) + +inst_567: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xfc00; + valaddr_reg:x5; val_offset:1086*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 1086*FLEN/8, x9, x1, x3) + +inst_568: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x7e00; + valaddr_reg:x5; val_offset:1088*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 1088*FLEN/8, x9, x1, x3) + +inst_569: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xfe00; + valaddr_reg:x5; val_offset:1090*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 1090*FLEN/8, x9, x1, x3) + +inst_570: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x7e01; + valaddr_reg:x5; val_offset:1092*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 1092*FLEN/8, x9, x1, x3) + +inst_571: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xfe55; + valaddr_reg:x5; val_offset:1094*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 1094*FLEN/8, x9, x1, x3) + +inst_572: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x7c01; + valaddr_reg:x5; val_offset:1096*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 1096*FLEN/8, x9, x1, x3) + +inst_573: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xfd55; + valaddr_reg:x5; val_offset:1098*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 1098*FLEN/8, x9, x1, x3) + +inst_574: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x3c00; + valaddr_reg:x5; val_offset:1100*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 1100*FLEN/8, x9, x1, x3) + +inst_575: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbc00; + valaddr_reg:x5; val_offset:1102*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 1102*FLEN/8, x9, x1, x3) + +inst_576: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x0; + valaddr_reg:x5; val_offset:1104*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 1104*FLEN/8, x9, x1, x3) + +inst_577: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x2; + valaddr_reg:x5; val_offset:1106*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 1106*FLEN/8, x9, x1, x3) + +inst_578: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xfe00; + valaddr_reg:x5; val_offset:1108*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 1108*FLEN/8, x9, x1, x3) + +inst_579: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x3c00; + valaddr_reg:x5; val_offset:1110*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 1110*FLEN/8, x9, x1, x3) + +inst_580: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x3ff; + valaddr_reg:x5; val_offset:1112*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 1112*FLEN/8, x9, x1, x3) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(1,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(1023,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(1024,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(1025,32,FLEN) +test_dataset_1: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31744,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32256,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32257,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31745,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(48128,16,FLEN) +test_dataset_2: +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1024,16,FLEN) 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+NAN_BOXED(32256,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(33877,16,FLEN) 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+NAN_BOXED(33791,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1023,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x6_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x6_1: + .fill 32*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_0: + .fill 32*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_2: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_3: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_4: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_5: + .fill 74*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fsub_b10-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fsub_b10-01.S new file mode 100644 index 000000000..7ea33c021 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fsub_b10-01.S @@ -0,0 +1,401 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 06:02:02 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fsub.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fsub.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fsub_b10 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fsub_b10) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x12,test_dataset_0) +RVTEST_SIGBASE(x8,signature_x8_1) + +inst_0: +// rs1 == rs2 == rd, rs1==x13, rs2==x13, rd==x13,fs1 == 0 and fe1 == 0x12 and fm1 == 0x0d5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x13; op2:x13; dest:x13; op1val:0x48d5; op2val:0x48d5; + valaddr_reg:x12; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x13, x13, x13, dyn, 0, 0, x12, 0*FLEN/8, x15, x8, x1) + +inst_1: +// rs2 == rd != rs1, rs1==x24, rs2==x20, rd==x20,fs1 == 0 and fe1 == 0x12 and fm1 == 0x0d5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x073 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x24; op2:x20; dest:x20; op1val:0x48d5; op2val:0x3873; + valaddr_reg:x12; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x20, x24, x20, dyn, 0, 0, x12, 2*FLEN/8, x15, x8, x1) + +inst_2: +// rs1 == rd != rs2, rs1==x26, rs2==x30, rd==x26,fs1 == 0 and fe1 == 0x12 and fm1 == 0x0d5 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x190 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x26; op2:x30; dest:x26; op1val:0x48d5; op2val:0x4590; + valaddr_reg:x12; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x26, x26, x30, dyn, 0, 0, x12, 4*FLEN/8, x15, x8, x1) + +inst_3: +// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==x14, rs2==x16, rd==x3,fs1 == 0 and fe1 == 0x12 and fm1 == 0x0d5 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x2f5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x14; op2:x16; dest:x3; op1val:0x48d5; op2val:0x52f5; + valaddr_reg:x12; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x3, x14, x16, dyn, 0, 0, x12, 6*FLEN/8, x15, x8, x1) + +inst_4: +// rs1 == rs2 != rd, rs1==x5, rs2==x5, rd==x2, +/* opcode: fsub.h ; op1:x5; op2:x5; dest:x2; op1val:0x0; op2val:0x0; + valaddr_reg:x12; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x2, x5, x5, dyn, 0, 0, x12, 8*FLEN/8, x15, x8, x1) + +inst_5: +// rs1==x4, rs2==x27, rd==x25, +/* opcode: fsub.h ; op1:x4; op2:x27; dest:x25; op1val:0x0; op2val:0x0; + valaddr_reg:x12; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x25, x4, x27, dyn, 0, 0, x12, 10*FLEN/8, x15, x8, x1) + +inst_6: +// rs1==x23, rs2==x10, rd==x5, +/* opcode: fsub.h ; op1:x23; op2:x10; dest:x5; op1val:0x0; op2val:0x0; + valaddr_reg:x12; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x5, x23, x10, dyn, 0, 0, x12, 12*FLEN/8, x15, x8, x1) + +inst_7: +// rs1==x2, rs2==x9, rd==x0, +/* opcode: fsub.h ; op1:x2; op2:x9; dest:x0; op1val:0x0; op2val:0x0; + valaddr_reg:x12; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x0, x2, x9, dyn, 0, 0, x12, 14*FLEN/8, x15, x8, x1) + +inst_8: +// rs1==x21, rs2==x4, rd==x10, +/* opcode: fsub.h ; op1:x21; op2:x4; dest:x10; op1val:0x0; op2val:0x0; + valaddr_reg:x12; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x10, x21, x4, dyn, 0, 0, x12, 16*FLEN/8, x15, x8, x1) + +inst_9: +// rs1==x30, rs2==x28, rd==x11, +/* opcode: fsub.h ; op1:x30; op2:x28; dest:x11; op1val:0x0; op2val:0x0; + valaddr_reg:x12; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x11, x30, x28, dyn, 0, 0, x12, 18*FLEN/8, x15, x8, x1) + +inst_10: +// rs1==x20, rs2==x7, rd==x28, +/* opcode: fsub.h ; op1:x20; op2:x7; dest:x28; op1val:0x0; op2val:0x0; + valaddr_reg:x12; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x28, x20, x7, dyn, 0, 0, x12, 20*FLEN/8, x15, x8, x1) + +inst_11: +// rs1==x19, rs2==x22, rd==x9, +/* opcode: fsub.h ; op1:x19; op2:x22; dest:x9; op1val:0x0; op2val:0x0; + valaddr_reg:x12; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x9, x19, x22, dyn, 0, 0, x12, 22*FLEN/8, x15, x8, x1) + +inst_12: +// rs1==x17, rs2==x6, rd==x21, +/* opcode: fsub.h ; op1:x17; op2:x6; dest:x21; op1val:0x0; op2val:0x0; + valaddr_reg:x12; val_offset:24*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x21, x17, x6, dyn, 0, 0, x12, 24*FLEN/8, x15, x8, x1) +RVTEST_VALBASEUPD(x10,test_dataset_1) + +inst_13: +// rs1==x11, rs2==x15, rd==x27, +/* opcode: fsub.h ; op1:x11; op2:x15; dest:x27; op1val:0x0; op2val:0x0; + valaddr_reg:x10; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x27, x11, x15, dyn, 0, 0, x10, 0*FLEN/8, x13, x8, x1) + +inst_14: +// rs1==x6, rs2==x1, rd==x7, +/* opcode: fsub.h ; op1:x6; op2:x1; dest:x7; op1val:0x0; op2val:0x0; + valaddr_reg:x10; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x11*/ +TEST_FPRR_OP(fsub.h, x7, x6, x1, dyn, 0, 0, x10, 2*FLEN/8, x13, x8, x11) +RVTEST_SIGBASE(x5,signature_x5_0) + +inst_15: +// rs1==x18, rs2==x0, rd==x8, +/* opcode: fsub.h ; op1:x18; op2:x0; dest:x8; op1val:0x0; op2val:0x0; + valaddr_reg:x10; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x11*/ +TEST_FPRR_OP(fsub.h, x8, x18, x0, dyn, 0, 0, x10, 4*FLEN/8, x13, x5, x11) + +inst_16: +// rs1==x15, rs2==x23, rd==x17, +/* opcode: fsub.h ; op1:x15; op2:x23; dest:x17; op1val:0x0; op2val:0x0; + valaddr_reg:x10; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x11*/ +TEST_FPRR_OP(fsub.h, x17, x15, x23, dyn, 0, 0, x10, 6*FLEN/8, x13, x5, x11) + +inst_17: +// rs1==x9, rs2==x19, rd==x23, +/* opcode: fsub.h ; op1:x9; op2:x19; dest:x23; op1val:0x0; op2val:0x0; + valaddr_reg:x10; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x11*/ +TEST_FPRR_OP(fsub.h, x23, x9, x19, dyn, 0, 0, x10, 8*FLEN/8, x13, x5, x11) + +inst_18: +// rs1==x0, rs2==x17, rd==x6, +/* opcode: fsub.h ; op1:x0; op2:x17; dest:x6; op1val:0x0; op2val:0x0; + valaddr_reg:x10; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x11*/ +TEST_FPRR_OP(fsub.h, x6, x0, x17, dyn, 0, 0, x10, 10*FLEN/8, x13, x5, x11) + +inst_19: +// rs1==x7, rs2==x2, rd==x16, +/* opcode: fsub.h ; op1:x7; op2:x2; dest:x16; op1val:0x0; op2val:0x0; + valaddr_reg:x10; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x11*/ +TEST_FPRR_OP(fsub.h, x16, x7, x2, dyn, 0, 0, x10, 12*FLEN/8, x13, x5, x11) + +inst_20: +// rs1==x3, rs2==x25, rd==x1, +/* opcode: fsub.h ; op1:x3; op2:x25; dest:x1; op1val:0x0; op2val:0x0; + valaddr_reg:x10; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x11*/ +TEST_FPRR_OP(fsub.h, x1, x3, x25, dyn, 0, 0, x10, 14*FLEN/8, x13, x5, x11) + +inst_21: +// rs1==x27, rs2==x24, rd==x19, +/* opcode: fsub.h ; op1:x27; op2:x24; dest:x19; op1val:0x0; op2val:0x0; + valaddr_reg:x10; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x11*/ +TEST_FPRR_OP(fsub.h, x19, x27, x24, dyn, 0, 0, x10, 16*FLEN/8, x13, x5, x11) + +inst_22: +// rs1==x31, rs2==x14, rd==x4, +/* opcode: fsub.h ; op1:x31; op2:x14; dest:x4; op1val:0x0; op2val:0x0; + valaddr_reg:x10; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x11*/ +TEST_FPRR_OP(fsub.h, x4, x31, x14, dyn, 0, 0, x10, 18*FLEN/8, x13, x5, x11) + +inst_23: +// rs1==x16, rs2==x26, rd==x12, +/* opcode: fsub.h ; op1:x16; op2:x26; dest:x12; op1val:0x0; op2val:0x0; + valaddr_reg:x10; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x11*/ +TEST_FPRR_OP(fsub.h, x12, x16, x26, dyn, 0, 0, x10, 20*FLEN/8, x13, x5, x11) + +inst_24: +// rs1==x22, rs2==x8, rd==x14, +/* opcode: fsub.h ; op1:x22; op2:x8; dest:x14; op1val:0x0; op2val:0x0; + valaddr_reg:x10; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x11*/ +TEST_FPRR_OP(fsub.h, x14, x22, x8, dyn, 0, 0, x10, 22*FLEN/8, x13, x5, x11) + +inst_25: +// rs1==x29, rs2==x18, rd==x24, +/* opcode: fsub.h ; op1:x29; op2:x18; dest:x24; op1val:0x0; op2val:0x0; + valaddr_reg:x10; val_offset:24*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x11*/ +TEST_FPRR_OP(fsub.h, x24, x29, x18, dyn, 0, 0, x10, 24*FLEN/8, x13, x5, x11) +RVTEST_VALBASEUPD(x4,test_dataset_2) + +inst_26: +// rs1==x10, rs2==x31, rd==x22, +/* opcode: fsub.h ; op1:x10; op2:x31; dest:x22; op1val:0x0; op2val:0x0; + valaddr_reg:x4; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x11*/ +TEST_FPRR_OP(fsub.h, x22, x10, x31, dyn, 0, 0, x4, 0*FLEN/8, x6, x5, x11) + +inst_27: +// rs1==x8, rs2==x12, rd==x29, +/* opcode: fsub.h ; op1:x8; op2:x12; dest:x29; op1val:0x0; op2val:0x0; + valaddr_reg:x4; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x11*/ +TEST_FPRR_OP(fsub.h, x29, x8, x12, dyn, 0, 0, x4, 2*FLEN/8, x6, x5, x11) + +inst_28: +// rs1==x1, rs2==x21, rd==x31, +/* opcode: fsub.h ; op1:x1; op2:x21; dest:x31; op1val:0x0; op2val:0x0; + valaddr_reg:x4; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x11*/ +TEST_FPRR_OP(fsub.h, x31, x1, x21, dyn, 0, 0, x4, 4*FLEN/8, x6, x5, x11) + +inst_29: +// rs1==x28, rs2==x29, rd==x30, +/* opcode: fsub.h ; op1:x28; op2:x29; dest:x30; op1val:0x0; op2val:0x0; + valaddr_reg:x4; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x30, x28, x29, dyn, 0, 0, x4, 6*FLEN/8, x6, x5, x2) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_30: +// rs1==x25, rs2==x11, rd==x18, +/* opcode: fsub.h ; op1:x25; op2:x11; dest:x18; op1val:0x0; op2val:0x0; + valaddr_reg:x4; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x18, x25, x11, dyn, 0, 0, x4, 8*FLEN/8, x6, x1, x2) + +inst_31: +// rs1==x12, rs2==x3, rd==x15, +/* opcode: fsub.h ; op1:x12; op2:x3; dest:x15; op1val:0x0; op2val:0x0; + valaddr_reg:x4; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x15, x12, x3, dyn, 0, 0, x4, 10*FLEN/8, x6, x1, x2) + +inst_32: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x0d5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x48d5; op2val:0x0; + valaddr_reg:x4; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 12*FLEN/8, x6, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(18645,32,FLEN) +NAN_BOXED(18645,32,FLEN) +NAN_BOXED(18645,32,FLEN) +NAN_BOXED(14451,32,FLEN) +NAN_BOXED(18645,32,FLEN) +NAN_BOXED(17808,32,FLEN) +NAN_BOXED(18645,32,FLEN) +NAN_BOXED(21237,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +test_dataset_1: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +test_dataset_2: +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(18645,16,FLEN) +NAN_BOXED(0,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x8_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x8_1: + .fill 30*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x5_0: + .fill 30*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_0: + .fill 6*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fsub_b11-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fsub_b11-01.S new file mode 100644 index 000000000..780bb12ba --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fsub_b11-01.S @@ -0,0 +1,30861 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 06:02:02 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fsub.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fsub.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fsub_b11 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fsub_b11) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x4,signature_x4_1) + +inst_0: +// rs1 == rs2 == rd, rs1==x10, rs2==x10, rd==x10,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x10; op2:x10; dest:x10; op1val:0x0; op2val:0x0; + valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9*/ +TEST_FPRR_OP(fsub.h, x10, x10, x10, dyn, 0, 0, x3, 0*FLEN/8, x17, x4, x9) + +inst_1: +// rs2 == rd != rs1, rs1==x0, rs2==x15, rd==x15,fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x0; op2:x15; dest:x15; op1val:0x0; op2val:0x0; + valaddr_reg:x3; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9*/ +TEST_FPRR_OP(fsub.h, x15, x0, x15, dyn, 0, 0, x3, 2*FLEN/8, x17, x4, x9) + +inst_2: +// rs1 == rd != rs2, rs1==x13, rs2==x30, rd==x13,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x13; op2:x30; dest:x13; op1val:0x0; op2val:0x3ff; + valaddr_reg:x3; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9*/ +TEST_FPRR_OP(fsub.h, x13, x13, x30, dyn, 0, 0, x3, 4*FLEN/8, x17, x4, x9) + +inst_3: +// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==x2, rs2==x18, rd==x16,fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x2; op2:x18; dest:x16; op1val:0x3ff; op2val:0x0; + valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9*/ +TEST_FPRR_OP(fsub.h, x16, x2, x18, dyn, 0, 0, x3, 6*FLEN/8, x17, x4, x9) + +inst_4: +// rs1 == rs2 != rd, rs1==x5, rs2==x5, rd==x6,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x5; op2:x5; dest:x6; op1val:0x0; op2val:0x0; + valaddr_reg:x3; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9*/ +TEST_FPRR_OP(fsub.h, x6, x5, x5, dyn, 0, 0, x3, 8*FLEN/8, x17, x4, x9) + +inst_5: +// rs1==x25, rs2==x27, rd==x23,fs1 == 0 and fe1 == 0x00 and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x25; op2:x27; dest:x23; op1val:0x200; op2val:0x0; + valaddr_reg:x3; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9*/ +TEST_FPRR_OP(fsub.h, x23, x25, x27, dyn, 0, 0, x3, 10*FLEN/8, x17, x4, x9) + +inst_6: +// rs1==x16, rs2==x29, rd==x7,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x16; op2:x29; dest:x7; op1val:0x0; op2val:0x1ff; + valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9*/ +TEST_FPRR_OP(fsub.h, x7, x16, x29, dyn, 0, 0, x3, 12*FLEN/8, x17, x4, x9) + +inst_7: +// rs1==x1, rs2==x8, rd==x14,fs1 == 0 and fe1 == 0x00 and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x1; op2:x8; dest:x14; op1val:0x1ff; op2val:0x0; + valaddr_reg:x3; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9*/ +TEST_FPRR_OP(fsub.h, x14, x1, x8, dyn, 0, 0, x3, 14*FLEN/8, x17, x4, x9) + +inst_8: +// rs1==x11, rs2==x12, rd==x28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x11; op2:x12; dest:x28; op1val:0x0; op2val:0x300; + valaddr_reg:x3; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9*/ +TEST_FPRR_OP(fsub.h, x28, x11, x12, dyn, 0, 0, x3, 16*FLEN/8, x17, x4, x9) + +inst_9: +// rs1==x26, rs2==x25, rd==x5,fs1 == 0 and fe1 == 0x00 and fm1 == 0x300 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x26; op2:x25; dest:x5; op1val:0x300; op2val:0x0; + valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9*/ +TEST_FPRR_OP(fsub.h, x5, x26, x25, dyn, 0, 0, x3, 18*FLEN/8, x17, x4, x9) + +inst_10: +// rs1==x14, rs2==x0, rd==x20,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x14; op2:x0; dest:x20; op1val:0x0; op2val:0x0; + valaddr_reg:x3; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9*/ +TEST_FPRR_OP(fsub.h, x20, x14, x0, dyn, 0, 0, x3, 20*FLEN/8, x17, x4, x9) + +inst_11: +// rs1==x28, rs2==x19, rd==x18,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x28; op2:x19; dest:x18; op1val:0xff; op2val:0x0; + valaddr_reg:x3; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9*/ +TEST_FPRR_OP(fsub.h, x18, x28, x19, dyn, 0, 0, x3, 22*FLEN/8, x17, x4, x9) +RVTEST_VALBASEUPD(x15,test_dataset_1) + +inst_12: +// rs1==x29, rs2==x16, rd==x3,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x29; op2:x16; dest:x3; op1val:0x0; op2val:0x380; + valaddr_reg:x15; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9*/ +TEST_FPRR_OP(fsub.h, x3, x29, x16, dyn, 0, 0, x15, 0*FLEN/8, x18, x4, x9) + +inst_13: +// rs1==x31, rs2==x22, rd==x2,fs1 == 0 and fe1 == 0x00 and fm1 == 0x380 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x31; op2:x22; dest:x2; op1val:0x380; op2val:0x0; + valaddr_reg:x15; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9*/ +TEST_FPRR_OP(fsub.h, x2, x31, x22, dyn, 0, 0, x15, 2*FLEN/8, x18, x4, x9) +RVTEST_SIGBASE(x5,signature_x5_0) + +inst_14: +// rs1==x4, rs2==x1, rd==x27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x4; op2:x1; dest:x27; op1val:0x0; op2val:0x7f; + valaddr_reg:x15; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x10*/ +TEST_FPRR_OP(fsub.h, x27, x4, x1, dyn, 0, 0, x15, 4*FLEN/8, x18, x5, x10) + +inst_15: +// rs1==x27, rs2==x6, rd==x1,fs1 == 0 and fe1 == 0x00 and fm1 == 0x07f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x27; op2:x6; dest:x1; op1val:0x7f; op2val:0x0; + valaddr_reg:x15; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x10*/ +TEST_FPRR_OP(fsub.h, x1, x27, x6, dyn, 0, 0, x15, 6*FLEN/8, x18, x5, x10) + +inst_16: +// rs1==x9, rs2==x2, rd==x24,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x9; op2:x2; dest:x24; op1val:0x0; op2val:0x3c0; + valaddr_reg:x15; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x10*/ +TEST_FPRR_OP(fsub.h, x24, x9, x2, dyn, 0, 0, x15, 8*FLEN/8, x18, x5, x10) + +inst_17: +// rs1==x21, rs2==x26, rd==x31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x21; op2:x26; dest:x31; op1val:0x3c0; op2val:0x0; + valaddr_reg:x15; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x10*/ +TEST_FPRR_OP(fsub.h, x31, x21, x26, dyn, 0, 0, x15, 10*FLEN/8, x18, x5, x10) + +inst_18: +// rs1==x7, rs2==x21, rd==x29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x7; op2:x21; dest:x29; op1val:0x0; op2val:0x3f; + valaddr_reg:x15; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x10*/ +TEST_FPRR_OP(fsub.h, x29, x7, x21, dyn, 0, 0, x15, 12*FLEN/8, x18, x5, x10) + +inst_19: +// rs1==x24, rs2==x13, rd==x9,fs1 == 0 and fe1 == 0x00 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x24; op2:x13; dest:x9; op1val:0x3f; op2val:0x0; + valaddr_reg:x15; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x10*/ +TEST_FPRR_OP(fsub.h, x9, x24, x13, dyn, 0, 0, x15, 14*FLEN/8, x18, x5, x10) + +inst_20: +// rs1==x19, rs2==x14, rd==x0,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x19; op2:x14; dest:x0; op1val:0x0; op2val:0x3e0; + valaddr_reg:x15; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x10*/ +TEST_FPRR_OP(fsub.h, x0, x19, x14, dyn, 0, 0, x15, 16*FLEN/8, x18, x5, x10) + +inst_21: +// rs1==x12, rs2==x24, rd==x8,fs1 == 0 and fe1 == 0x00 and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x12; op2:x24; dest:x8; op1val:0x3e0; op2val:0x0; + valaddr_reg:x15; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x10*/ +TEST_FPRR_OP(fsub.h, x8, x12, x24, dyn, 0, 0, x15, 18*FLEN/8, x18, x5, x10) + +inst_22: +// rs1==x6, rs2==x9, rd==x17,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x6; op2:x9; dest:x17; op1val:0x0; op2val:0x1f; + valaddr_reg:x15; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x10*/ +TEST_FPRR_OP(fsub.h, x17, x6, x9, dyn, 0, 0, x15, 20*FLEN/8, x18, x5, x10) + +inst_23: +// rs1==x20, rs2==x11, rd==x26,fs1 == 0 and fe1 == 0x00 and fm1 == 0x01f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x20; op2:x11; dest:x26; op1val:0x1f; op2val:0x0; + valaddr_reg:x15; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x10*/ +TEST_FPRR_OP(fsub.h, x26, x20, x11, dyn, 0, 0, x15, 22*FLEN/8, x18, x5, x10) +RVTEST_VALBASEUPD(x6,test_dataset_2) + +inst_24: +// rs1==x18, rs2==x17, rd==x19,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x18; op2:x17; dest:x19; op1val:0x0; op2val:0x3f0; + valaddr_reg:x6; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x10*/ +TEST_FPRR_OP(fsub.h, x19, x18, x17, dyn, 0, 0, x6, 0*FLEN/8, x9, x5, x10) + +inst_25: +// rs1==x23, rs2==x3, rd==x12,fs1 == 0 and fe1 == 0x00 and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x23; op2:x3; dest:x12; op1val:0x3f0; op2val:0x0; + valaddr_reg:x6; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x10*/ +TEST_FPRR_OP(fsub.h, x12, x23, x3, dyn, 0, 0, x6, 2*FLEN/8, x9, x5, x10) + +inst_26: +// rs1==x17, rs2==x31, rd==x11,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x17; op2:x31; dest:x11; op1val:0x0; op2val:0xf; + valaddr_reg:x6; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x10*/ +TEST_FPRR_OP(fsub.h, x11, x17, x31, dyn, 0, 0, x6, 4*FLEN/8, x9, x5, x10) + +inst_27: +// rs1==x30, rs2==x28, rd==x25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x00f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x28; dest:x25; op1val:0xf; op2val:0x0; + valaddr_reg:x6; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x10*/ +TEST_FPRR_OP(fsub.h, x25, x30, x28, dyn, 0, 0, x6, 6*FLEN/8, x9, x5, x10) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_28: +// rs1==x3, rs2==x20, rd==x30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x3; op2:x20; dest:x30; op1val:0x0; op2val:0x3f8; + valaddr_reg:x6; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x30, x3, x20, dyn, 0, 0, x6, 8*FLEN/8, x9, x1, x2) + +inst_29: +// rs1==x22, rs2==x7, rd==x21,fs1 == 0 and fe1 == 0x00 and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x22; op2:x7; dest:x21; op1val:0x3f8; op2val:0x0; + valaddr_reg:x6; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x21, x22, x7, dyn, 0, 0, x6, 10*FLEN/8, x9, x1, x2) + +inst_30: +// rs1==x8, rs2==x23, rd==x4,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x8; op2:x23; dest:x4; op1val:0x0; op2val:0x7; + valaddr_reg:x6; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x4, x8, x23, dyn, 0, 0, x6, 12*FLEN/8, x9, x1, x2) + +inst_31: +// rs1==x15, rs2==x4, rd==x22,fs1 == 0 and fe1 == 0x00 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x15; op2:x4; dest:x22; op1val:0x7; op2val:0x0; + valaddr_reg:x6; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x22, x15, x4, dyn, 0, 0, x6, 14*FLEN/8, x9, x1, x2) + +inst_32: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x3fc; + valaddr_reg:x6; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 16*FLEN/8, x9, x1, x2) + +inst_33: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fc; op2val:0x0; + valaddr_reg:x6; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 18*FLEN/8, x9, x1, x2) + +inst_34: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x3; + valaddr_reg:x6; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 20*FLEN/8, x9, x1, x2) + +inst_35: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x003 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3; op2val:0x0; + valaddr_reg:x6; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 22*FLEN/8, x9, x1, x2) + +inst_36: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x3fe; + valaddr_reg:x6; val_offset:24*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 24*FLEN/8, x9, x1, x2) + +inst_37: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fe; op2val:0x0; + valaddr_reg:x6; val_offset:26*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 26*FLEN/8, x9, x1, x2) + +inst_38: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1b6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x1b6; + valaddr_reg:x6; val_offset:28*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 28*FLEN/8, x9, x1, x2) + +inst_39: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1b6; op2val:0x0; + valaddr_reg:x6; val_offset:30*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 30*FLEN/8, x9, x1, x2) + +inst_40: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x36d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x36d; + valaddr_reg:x6; val_offset:32*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 32*FLEN/8, x9, x1, x2) + +inst_41: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x36d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x36d; op2val:0x0; + valaddr_reg:x6; val_offset:34*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 34*FLEN/8, x9, x1, x2) + +inst_42: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0cc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xcc; + valaddr_reg:x6; val_offset:36*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 36*FLEN/8, x9, x1, x2) + +inst_43: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0cc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xcc; op2val:0x0; + valaddr_reg:x6; val_offset:38*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 38*FLEN/8, x9, x1, x2) + +inst_44: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x333 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x333; + valaddr_reg:x6; val_offset:40*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 40*FLEN/8, x9, x1, x2) + +inst_45: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x333 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x333; op2val:0x0; + valaddr_reg:x6; val_offset:42*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 42*FLEN/8, x9, x1, x2) + +inst_46: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1dd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x1dd; + valaddr_reg:x6; val_offset:44*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 44*FLEN/8, x9, x1, x2) + +inst_47: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1dd; op2val:0x0; + valaddr_reg:x6; val_offset:46*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 46*FLEN/8, x9, x1, x2) + +inst_48: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x222 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x222; + valaddr_reg:x6; val_offset:48*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 48*FLEN/8, x9, x1, x2) + +inst_49: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x222 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x222; op2val:0x0; + valaddr_reg:x6; val_offset:50*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 50*FLEN/8, x9, x1, x2) + +inst_50: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x124 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x124; + valaddr_reg:x6; val_offset:52*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 52*FLEN/8, x9, x1, x2) + +inst_51: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x124 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x124; op2val:0x0; + valaddr_reg:x6; val_offset:54*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 54*FLEN/8, x9, x1, x2) + +inst_52: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2db and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x2db; + valaddr_reg:x6; val_offset:56*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 56*FLEN/8, x9, x1, x2) + +inst_53: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2db; op2val:0x0; + valaddr_reg:x6; val_offset:58*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 58*FLEN/8, x9, x1, x2) + +inst_54: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x199 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x199; + valaddr_reg:x6; val_offset:60*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 60*FLEN/8, x9, x1, x2) + +inst_55: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x199 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x199; op2val:0x0; + valaddr_reg:x6; val_offset:62*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 62*FLEN/8, x9, x1, x2) + +inst_56: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x266 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x266; + valaddr_reg:x6; val_offset:64*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 64*FLEN/8, x9, x1, x2) + +inst_57: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x266 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x266; op2val:0x0; + valaddr_reg:x6; val_offset:66*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 66*FLEN/8, x9, x1, x2) + +inst_58: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x9800; + valaddr_reg:x6; val_offset:68*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 68*FLEN/8, x9, x1, x2) + +inst_59: +// fs1 == 1 and fe1 == 0x06 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x9800; op2val:0x0; + valaddr_reg:x6; val_offset:70*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 70*FLEN/8, x9, x1, x2) + +inst_60: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x9bff; + valaddr_reg:x6; val_offset:72*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 72*FLEN/8, x9, x1, x2) + +inst_61: +// fs1 == 1 and fe1 == 0x06 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x9bff; op2val:0x0; + valaddr_reg:x6; val_offset:74*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 74*FLEN/8, x9, x1, x2) + +inst_62: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x9a00; + valaddr_reg:x6; val_offset:76*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 76*FLEN/8, x9, x1, x2) + +inst_63: +// fs1 == 1 and fe1 == 0x06 and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x9a00; op2val:0x0; + valaddr_reg:x6; val_offset:78*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 78*FLEN/8, x9, x1, x2) + +inst_64: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x99ff; + valaddr_reg:x6; val_offset:80*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 80*FLEN/8, x9, x1, x2) + +inst_65: +// fs1 == 1 and fe1 == 0x06 and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x99ff; op2val:0x0; + valaddr_reg:x6; val_offset:82*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 82*FLEN/8, x9, x1, x2) + +inst_66: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x9b00; + valaddr_reg:x6; val_offset:84*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 84*FLEN/8, x9, x1, x2) + +inst_67: +// fs1 == 1 and fe1 == 0x06 and fm1 == 0x300 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x9b00; op2val:0x0; + valaddr_reg:x6; val_offset:86*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 86*FLEN/8, x9, x1, x2) + +inst_68: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x98ff; + valaddr_reg:x6; val_offset:88*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 88*FLEN/8, x9, x1, x2) + +inst_69: +// fs1 == 1 and fe1 == 0x06 and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x98ff; op2val:0x0; + valaddr_reg:x6; val_offset:90*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 90*FLEN/8, x9, x1, x2) + +inst_70: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x9b80; + valaddr_reg:x6; val_offset:92*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 92*FLEN/8, x9, x1, x2) + +inst_71: +// fs1 == 1 and fe1 == 0x06 and fm1 == 0x380 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x9b80; op2val:0x0; + valaddr_reg:x6; val_offset:94*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 94*FLEN/8, x9, x1, x2) + +inst_72: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x987f; + valaddr_reg:x6; val_offset:96*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 96*FLEN/8, x9, x1, x2) + +inst_73: +// fs1 == 1 and fe1 == 0x06 and fm1 == 0x07f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x987f; op2val:0x0; + valaddr_reg:x6; val_offset:98*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 98*FLEN/8, x9, x1, x2) + +inst_74: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x9bc0; + valaddr_reg:x6; val_offset:100*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 100*FLEN/8, x9, x1, x2) + +inst_75: +// fs1 == 1 and fe1 == 0x06 and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x9bc0; op2val:0x0; + valaddr_reg:x6; val_offset:102*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 102*FLEN/8, x9, x1, x2) + +inst_76: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x983f; + valaddr_reg:x6; val_offset:104*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 104*FLEN/8, x9, x1, x2) + +inst_77: +// fs1 == 1 and fe1 == 0x06 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x983f; op2val:0x0; + valaddr_reg:x6; val_offset:106*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 106*FLEN/8, x9, x1, x2) + +inst_78: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x9be0; + valaddr_reg:x6; val_offset:108*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 108*FLEN/8, x9, x1, x2) + +inst_79: +// fs1 == 1 and fe1 == 0x06 and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x9be0; op2val:0x0; + valaddr_reg:x6; val_offset:110*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 110*FLEN/8, x9, x1, x2) + +inst_80: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x981f; + valaddr_reg:x6; val_offset:112*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 112*FLEN/8, x9, x1, x2) + +inst_81: +// fs1 == 1 and fe1 == 0x06 and fm1 == 0x01f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x981f; op2val:0x0; + valaddr_reg:x6; val_offset:114*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 114*FLEN/8, x9, x1, x2) + +inst_82: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x9bf0; + valaddr_reg:x6; val_offset:116*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 116*FLEN/8, x9, x1, x2) + +inst_83: +// fs1 == 1 and fe1 == 0x06 and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x9bf0; op2val:0x0; + valaddr_reg:x6; val_offset:118*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 118*FLEN/8, x9, x1, x2) + +inst_84: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x980f; + valaddr_reg:x6; val_offset:120*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 120*FLEN/8, x9, x1, x2) + +inst_85: +// fs1 == 1 and fe1 == 0x06 and fm1 == 0x00f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x980f; op2val:0x0; + valaddr_reg:x6; val_offset:122*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 122*FLEN/8, x9, x1, x2) + +inst_86: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x9bf8; + valaddr_reg:x6; val_offset:124*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 124*FLEN/8, x9, x1, x2) + +inst_87: +// fs1 == 1 and fe1 == 0x06 and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x9bf8; op2val:0x0; + valaddr_reg:x6; val_offset:126*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 126*FLEN/8, x9, x1, x2) + +inst_88: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x9807; + valaddr_reg:x6; val_offset:128*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 128*FLEN/8, x9, x1, x2) + +inst_89: +// fs1 == 1 and fe1 == 0x06 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x9807; op2val:0x0; + valaddr_reg:x6; val_offset:130*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 130*FLEN/8, x9, x1, x2) + +inst_90: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x9bfc; + valaddr_reg:x6; val_offset:132*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 132*FLEN/8, x9, x1, x2) + +inst_91: +// fs1 == 1 and fe1 == 0x06 and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x9bfc; op2val:0x0; + valaddr_reg:x6; val_offset:134*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 134*FLEN/8, x9, x1, x2) + +inst_92: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x9803; + valaddr_reg:x6; val_offset:136*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 136*FLEN/8, x9, x1, x2) + +inst_93: +// fs1 == 1 and fe1 == 0x06 and fm1 == 0x003 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x9803; op2val:0x0; + valaddr_reg:x6; val_offset:138*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 138*FLEN/8, x9, x1, x2) + +inst_94: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x9bfe; + valaddr_reg:x6; val_offset:140*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 140*FLEN/8, x9, x1, x2) + +inst_95: +// fs1 == 1 and fe1 == 0x06 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x9bfe; op2val:0x0; + valaddr_reg:x6; val_offset:142*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 142*FLEN/8, x9, x1, x2) + +inst_96: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x9801; + valaddr_reg:x6; val_offset:144*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 144*FLEN/8, x9, x1, x2) + +inst_97: +// fs1 == 1 and fe1 == 0x06 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x9801; op2val:0x0; + valaddr_reg:x6; val_offset:146*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 146*FLEN/8, x9, x1, x2) + +inst_98: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x400; + valaddr_reg:x6; val_offset:148*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 148*FLEN/8, x9, x1, x2) + +inst_99: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x0; + valaddr_reg:x6; val_offset:150*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 150*FLEN/8, x9, x1, x2) + +inst_100: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x7ff; + valaddr_reg:x6; val_offset:152*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 152*FLEN/8, x9, x1, x2) + +inst_101: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ff; op2val:0x0; + valaddr_reg:x6; val_offset:154*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 154*FLEN/8, x9, x1, x2) + +inst_102: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x600; + valaddr_reg:x6; val_offset:156*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 156*FLEN/8, x9, x1, x2) + +inst_103: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x600; op2val:0x0; + valaddr_reg:x6; val_offset:158*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 158*FLEN/8, x9, x1, x2) + +inst_104: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x5ff; + valaddr_reg:x6; val_offset:160*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 160*FLEN/8, x9, x1, x2) + +inst_105: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5ff; op2val:0x0; + valaddr_reg:x6; val_offset:162*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 162*FLEN/8, x9, x1, x2) + +inst_106: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x700; + valaddr_reg:x6; val_offset:164*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 164*FLEN/8, x9, x1, x2) + +inst_107: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x300 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x700; op2val:0x0; + valaddr_reg:x6; val_offset:166*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 166*FLEN/8, x9, x1, x2) + +inst_108: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x4ff; + valaddr_reg:x6; val_offset:168*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 168*FLEN/8, x9, x1, x2) + +inst_109: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4ff; op2val:0x0; + valaddr_reg:x6; val_offset:170*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 170*FLEN/8, x9, x1, x2) + +inst_110: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x780; + valaddr_reg:x6; val_offset:172*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 172*FLEN/8, x9, x1, x2) + +inst_111: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x380 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x780; op2val:0x0; + valaddr_reg:x6; val_offset:174*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 174*FLEN/8, x9, x1, x2) + +inst_112: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x47f; + valaddr_reg:x6; val_offset:176*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 176*FLEN/8, x9, x1, x2) + +inst_113: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x07f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x47f; op2val:0x0; + valaddr_reg:x6; val_offset:178*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 178*FLEN/8, x9, x1, x2) + +inst_114: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x7c0; + valaddr_reg:x6; val_offset:180*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 180*FLEN/8, x9, x1, x2) + +inst_115: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c0; op2val:0x0; + valaddr_reg:x6; val_offset:182*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 182*FLEN/8, x9, x1, x2) + +inst_116: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x43f; + valaddr_reg:x6; val_offset:184*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 184*FLEN/8, x9, x1, x2) + +inst_117: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x43f; op2val:0x0; + valaddr_reg:x6; val_offset:186*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 186*FLEN/8, x9, x1, x2) + +inst_118: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x7e0; + valaddr_reg:x6; val_offset:188*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 188*FLEN/8, x9, x1, x2) + +inst_119: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e0; op2val:0x0; + valaddr_reg:x6; val_offset:190*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 190*FLEN/8, x9, x1, x2) + +inst_120: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x41f; + valaddr_reg:x6; val_offset:192*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 192*FLEN/8, x9, x1, x2) + +inst_121: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x01f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x41f; op2val:0x0; + valaddr_reg:x6; val_offset:194*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 194*FLEN/8, x9, x1, x2) + +inst_122: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x7f0; + valaddr_reg:x6; val_offset:196*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 196*FLEN/8, x9, x1, x2) + +inst_123: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7f0; op2val:0x0; + valaddr_reg:x6; val_offset:198*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 198*FLEN/8, x9, x1, x2) + +inst_124: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x40f; + valaddr_reg:x6; val_offset:200*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 200*FLEN/8, x9, x1, x2) + +inst_125: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x00f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x40f; op2val:0x0; + valaddr_reg:x6; val_offset:202*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 202*FLEN/8, x9, x1, x2) + +inst_126: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x7f8; + valaddr_reg:x6; val_offset:204*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 204*FLEN/8, x9, x1, x2) + +inst_127: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7f8; op2val:0x0; + valaddr_reg:x6; val_offset:206*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 206*FLEN/8, x9, x1, x2) + +inst_128: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x407; + valaddr_reg:x6; val_offset:208*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 208*FLEN/8, x9, x1, x2) + +inst_129: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x407; op2val:0x0; + valaddr_reg:x6; val_offset:210*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 210*FLEN/8, x9, x1, x2) + +inst_130: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x7fc; + valaddr_reg:x6; val_offset:212*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 212*FLEN/8, x9, x1, x2) + +inst_131: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7fc; op2val:0x0; + valaddr_reg:x6; val_offset:214*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 214*FLEN/8, x9, x1, x2) + +inst_132: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x403; + valaddr_reg:x6; val_offset:216*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 216*FLEN/8, x9, x1, x2) + +inst_133: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x003 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x403; op2val:0x0; + valaddr_reg:x6; val_offset:218*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 218*FLEN/8, x9, x1, x2) + +inst_134: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x7fe; + valaddr_reg:x6; val_offset:220*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 220*FLEN/8, x9, x1, x2) + +inst_135: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7fe; op2val:0x0; + valaddr_reg:x6; val_offset:222*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 222*FLEN/8, x9, x1, x2) + +inst_136: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x401; + valaddr_reg:x6; val_offset:224*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 224*FLEN/8, x9, x1, x2) + +inst_137: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x0; + valaddr_reg:x6; val_offset:226*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 226*FLEN/8, x9, x1, x2) + +inst_138: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x800; + valaddr_reg:x6; val_offset:228*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 228*FLEN/8, x9, x1, x2) + +inst_139: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x800; op2val:0x0; + valaddr_reg:x6; val_offset:230*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 230*FLEN/8, x9, x1, x2) + +inst_140: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xbff; + valaddr_reg:x6; val_offset:232*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 232*FLEN/8, x9, x1, x2) + +inst_141: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbff; op2val:0x0; + valaddr_reg:x6; val_offset:234*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 234*FLEN/8, x9, x1, x2) + +inst_142: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xa00; + valaddr_reg:x6; val_offset:236*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 236*FLEN/8, x9, x1, x2) + +inst_143: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xa00; op2val:0x0; + valaddr_reg:x6; val_offset:238*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 238*FLEN/8, x9, x1, x2) + +inst_144: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x9ff; + valaddr_reg:x6; val_offset:240*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 240*FLEN/8, x9, x1, x2) + +inst_145: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x9ff; op2val:0x0; + valaddr_reg:x6; val_offset:242*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 242*FLEN/8, x9, x1, x2) + +inst_146: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xb00; + valaddr_reg:x6; val_offset:244*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 244*FLEN/8, x9, x1, x2) + +inst_147: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x300 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xb00; op2val:0x0; + valaddr_reg:x6; val_offset:246*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 246*FLEN/8, x9, x1, x2) + +inst_148: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x8ff; + valaddr_reg:x6; val_offset:248*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 248*FLEN/8, x9, x1, x2) + +inst_149: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8ff; op2val:0x0; + valaddr_reg:x6; val_offset:250*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 250*FLEN/8, x9, x1, x2) + +inst_150: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xb80; + valaddr_reg:x6; val_offset:252*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 252*FLEN/8, x9, x1, x2) + +inst_151: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x380 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xb80; op2val:0x0; + valaddr_reg:x6; val_offset:254*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 254*FLEN/8, x9, x1, x2) + +inst_152: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x87f; + valaddr_reg:x6; val_offset:256*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 256*FLEN/8, x9, x1, x2) + +inst_153: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x07f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x87f; op2val:0x0; + valaddr_reg:x6; val_offset:258*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 258*FLEN/8, x9, x1, x2) + +inst_154: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xbc0; + valaddr_reg:x6; val_offset:260*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 260*FLEN/8, x9, x1, x2) + +inst_155: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc0; op2val:0x0; + valaddr_reg:x6; val_offset:262*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 262*FLEN/8, x9, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_156: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x83f; + valaddr_reg:x6; val_offset:264*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 264*FLEN/8, x9, x1, x2) + +inst_157: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83f; op2val:0x0; + valaddr_reg:x6; val_offset:266*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 266*FLEN/8, x9, x1, x2) + +inst_158: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xbe0; + valaddr_reg:x6; val_offset:268*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 268*FLEN/8, x9, x1, x2) + +inst_159: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbe0; op2val:0x0; + valaddr_reg:x6; val_offset:270*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 270*FLEN/8, x9, x1, x2) + +inst_160: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x81f; + valaddr_reg:x6; val_offset:272*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 272*FLEN/8, x9, x1, x2) + +inst_161: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x01f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x81f; op2val:0x0; + valaddr_reg:x6; val_offset:274*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 274*FLEN/8, x9, x1, x2) + +inst_162: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xbf0; + valaddr_reg:x6; val_offset:276*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 276*FLEN/8, x9, x1, x2) + +inst_163: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbf0; op2val:0x0; + valaddr_reg:x6; val_offset:278*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 278*FLEN/8, x9, x1, x2) + +inst_164: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x80f; + valaddr_reg:x6; val_offset:280*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 280*FLEN/8, x9, x1, x2) + +inst_165: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x00f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x80f; op2val:0x0; + valaddr_reg:x6; val_offset:282*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 282*FLEN/8, x9, x1, x2) + +inst_166: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xbf8; + valaddr_reg:x6; val_offset:284*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 284*FLEN/8, x9, x1, x2) + +inst_167: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbf8; op2val:0x0; + valaddr_reg:x6; val_offset:286*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 286*FLEN/8, x9, x1, x2) + +inst_168: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x807; + valaddr_reg:x6; val_offset:288*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 288*FLEN/8, x9, x1, x2) + +inst_169: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x807; op2val:0x0; + valaddr_reg:x6; val_offset:290*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 290*FLEN/8, x9, x1, x2) + +inst_170: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xbfc; + valaddr_reg:x6; val_offset:292*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 292*FLEN/8, x9, x1, x2) + +inst_171: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbfc; op2val:0x0; + valaddr_reg:x6; val_offset:294*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 294*FLEN/8, x9, x1, x2) + +inst_172: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x803; + valaddr_reg:x6; val_offset:296*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 296*FLEN/8, x9, x1, x2) + +inst_173: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x003 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x803; op2val:0x0; + valaddr_reg:x6; val_offset:298*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 298*FLEN/8, x9, x1, x2) + +inst_174: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xbfe; + valaddr_reg:x6; val_offset:300*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 300*FLEN/8, x9, x1, x2) + +inst_175: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbfe; op2val:0x0; + valaddr_reg:x6; val_offset:302*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 302*FLEN/8, x9, x1, x2) + +inst_176: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x801; + valaddr_reg:x6; val_offset:304*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 304*FLEN/8, x9, x1, x2) + +inst_177: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x801; op2val:0x0; + valaddr_reg:x6; val_offset:306*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 306*FLEN/8, x9, x1, x2) + +inst_178: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xc00; + valaddr_reg:x6; val_offset:308*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 308*FLEN/8, x9, x1, x2) + +inst_179: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc00; op2val:0x0; + valaddr_reg:x6; val_offset:310*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 310*FLEN/8, x9, x1, x2) + +inst_180: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xfff; + valaddr_reg:x6; val_offset:312*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 312*FLEN/8, x9, x1, x2) + +inst_181: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfff; op2val:0x0; + valaddr_reg:x6; val_offset:314*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 314*FLEN/8, x9, x1, x2) + +inst_182: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xe00; + valaddr_reg:x6; val_offset:316*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 316*FLEN/8, x9, x1, x2) + +inst_183: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xe00; op2val:0x0; + valaddr_reg:x6; val_offset:318*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 318*FLEN/8, x9, x1, x2) + +inst_184: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xdff; + valaddr_reg:x6; val_offset:320*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 320*FLEN/8, x9, x1, x2) + +inst_185: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xdff; op2val:0x0; + valaddr_reg:x6; val_offset:322*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 322*FLEN/8, x9, x1, x2) + +inst_186: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xf00; + valaddr_reg:x6; val_offset:324*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 324*FLEN/8, x9, x1, x2) + +inst_187: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x300 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf00; op2val:0x0; + valaddr_reg:x6; val_offset:326*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 326*FLEN/8, x9, x1, x2) + +inst_188: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xcff; + valaddr_reg:x6; val_offset:328*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 328*FLEN/8, x9, x1, x2) + +inst_189: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xcff; op2val:0x0; + valaddr_reg:x6; val_offset:330*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 330*FLEN/8, x9, x1, x2) + +inst_190: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xf80; + valaddr_reg:x6; val_offset:332*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 332*FLEN/8, x9, x1, x2) + +inst_191: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x380 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf80; op2val:0x0; + valaddr_reg:x6; val_offset:334*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 334*FLEN/8, x9, x1, x2) + +inst_192: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xc7f; + valaddr_reg:x6; val_offset:336*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 336*FLEN/8, x9, x1, x2) + +inst_193: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x07f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc7f; op2val:0x0; + valaddr_reg:x6; val_offset:338*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 338*FLEN/8, x9, x1, x2) + +inst_194: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xfc0; + valaddr_reg:x6; val_offset:340*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 340*FLEN/8, x9, x1, x2) + +inst_195: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc0; op2val:0x0; + valaddr_reg:x6; val_offset:342*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 342*FLEN/8, x9, x1, x2) + +inst_196: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xc3f; + valaddr_reg:x6; val_offset:344*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 344*FLEN/8, x9, x1, x2) + +inst_197: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc3f; op2val:0x0; + valaddr_reg:x6; val_offset:346*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 346*FLEN/8, x9, x1, x2) + +inst_198: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xfe0; + valaddr_reg:x6; val_offset:348*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 348*FLEN/8, x9, x1, x2) + +inst_199: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe0; op2val:0x0; + valaddr_reg:x6; val_offset:350*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 350*FLEN/8, x9, x1, x2) + +inst_200: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xc1f; + valaddr_reg:x6; val_offset:352*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 352*FLEN/8, x9, x1, x2) + +inst_201: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x01f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc1f; op2val:0x0; + valaddr_reg:x6; val_offset:354*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 354*FLEN/8, x9, x1, x2) + +inst_202: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xff0; + valaddr_reg:x6; val_offset:356*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 356*FLEN/8, x9, x1, x2) + +inst_203: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xff0; op2val:0x0; + valaddr_reg:x6; val_offset:358*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 358*FLEN/8, x9, x1, x2) + +inst_204: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xc0f; + valaddr_reg:x6; val_offset:360*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 360*FLEN/8, x9, x1, x2) + +inst_205: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x00f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc0f; op2val:0x0; + valaddr_reg:x6; val_offset:362*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 362*FLEN/8, x9, x1, x2) + +inst_206: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xff8; + valaddr_reg:x6; val_offset:364*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 364*FLEN/8, x9, x1, x2) + +inst_207: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xff8; op2val:0x0; + valaddr_reg:x6; val_offset:366*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 366*FLEN/8, x9, x1, x2) + +inst_208: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xc07; + valaddr_reg:x6; val_offset:368*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 368*FLEN/8, x9, x1, x2) + +inst_209: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc07; op2val:0x0; + valaddr_reg:x6; val_offset:370*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 370*FLEN/8, x9, x1, x2) + +inst_210: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xffc; + valaddr_reg:x6; val_offset:372*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 372*FLEN/8, x9, x1, x2) + +inst_211: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xffc; op2val:0x0; + valaddr_reg:x6; val_offset:374*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 374*FLEN/8, x9, x1, x2) + +inst_212: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xc03; + valaddr_reg:x6; val_offset:376*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 376*FLEN/8, x9, x1, x2) + +inst_213: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x003 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc03; op2val:0x0; + valaddr_reg:x6; val_offset:378*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 378*FLEN/8, x9, x1, x2) + +inst_214: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xffe; + valaddr_reg:x6; val_offset:380*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 380*FLEN/8, x9, x1, x2) + +inst_215: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xffe; op2val:0x0; + valaddr_reg:x6; val_offset:382*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 382*FLEN/8, x9, x1, x2) + +inst_216: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xc01; + valaddr_reg:x6; val_offset:384*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 384*FLEN/8, x9, x1, x2) + +inst_217: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc01; op2val:0x0; + valaddr_reg:x6; val_offset:386*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 386*FLEN/8, x9, x1, x2) + +inst_218: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8001; + valaddr_reg:x6; val_offset:388*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 388*FLEN/8, x9, x1, x2) + +inst_219: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8000; + valaddr_reg:x6; val_offset:390*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 390*FLEN/8, x9, x1, x2) + +inst_220: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x83ff; + valaddr_reg:x6; val_offset:392*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 392*FLEN/8, x9, x1, x2) + +inst_221: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8000; + valaddr_reg:x6; val_offset:394*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 394*FLEN/8, x9, x1, x2) + +inst_222: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8200; + valaddr_reg:x6; val_offset:396*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 396*FLEN/8, x9, x1, x2) + +inst_223: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8200; op2val:0x8000; + valaddr_reg:x6; val_offset:398*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 398*FLEN/8, x9, x1, x2) + +inst_224: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x81ff; + valaddr_reg:x6; val_offset:400*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 400*FLEN/8, x9, x1, x2) + +inst_225: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x81ff; op2val:0x8000; + valaddr_reg:x6; val_offset:402*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 402*FLEN/8, x9, x1, x2) + +inst_226: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8300; + valaddr_reg:x6; val_offset:404*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 404*FLEN/8, x9, x1, x2) + +inst_227: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x300 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8300; op2val:0x8000; + valaddr_reg:x6; val_offset:406*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 406*FLEN/8, x9, x1, x2) + +inst_228: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x80ff; + valaddr_reg:x6; val_offset:408*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 408*FLEN/8, x9, x1, x2) + +inst_229: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x80ff; op2val:0x8000; + valaddr_reg:x6; val_offset:410*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 410*FLEN/8, x9, x1, x2) + +inst_230: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8380; + valaddr_reg:x6; val_offset:412*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 412*FLEN/8, x9, x1, x2) + +inst_231: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x380 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8380; op2val:0x8000; + valaddr_reg:x6; val_offset:414*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 414*FLEN/8, x9, x1, x2) + +inst_232: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x807f; + valaddr_reg:x6; val_offset:416*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 416*FLEN/8, x9, x1, x2) + +inst_233: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x07f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x807f; op2val:0x8000; + valaddr_reg:x6; val_offset:418*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 418*FLEN/8, x9, x1, x2) + +inst_234: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x83c0; + valaddr_reg:x6; val_offset:420*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 420*FLEN/8, x9, x1, x2) + +inst_235: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83c0; op2val:0x8000; + valaddr_reg:x6; val_offset:422*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 422*FLEN/8, x9, x1, x2) + +inst_236: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x803f; + valaddr_reg:x6; val_offset:424*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 424*FLEN/8, x9, x1, x2) + +inst_237: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x803f; op2val:0x8000; + valaddr_reg:x6; val_offset:426*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 426*FLEN/8, x9, x1, x2) + +inst_238: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x83e0; + valaddr_reg:x6; val_offset:428*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 428*FLEN/8, x9, x1, x2) + +inst_239: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83e0; op2val:0x8000; + valaddr_reg:x6; val_offset:430*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 430*FLEN/8, x9, x1, x2) + +inst_240: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x801f; + valaddr_reg:x6; val_offset:432*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 432*FLEN/8, x9, x1, x2) + +inst_241: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x01f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x801f; op2val:0x8000; + valaddr_reg:x6; val_offset:434*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 434*FLEN/8, x9, x1, x2) + +inst_242: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x83f0; + valaddr_reg:x6; val_offset:436*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 436*FLEN/8, x9, x1, x2) + +inst_243: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83f0; op2val:0x8000; + valaddr_reg:x6; val_offset:438*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 438*FLEN/8, x9, x1, x2) + +inst_244: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x800f; + valaddr_reg:x6; val_offset:440*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 440*FLEN/8, x9, x1, x2) + +inst_245: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x00f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x800f; op2val:0x8000; + valaddr_reg:x6; val_offset:442*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 442*FLEN/8, x9, x1, x2) + +inst_246: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x83f8; + valaddr_reg:x6; val_offset:444*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 444*FLEN/8, x9, x1, x2) + +inst_247: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83f8; op2val:0x8000; + valaddr_reg:x6; val_offset:446*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 446*FLEN/8, x9, x1, x2) + +inst_248: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8007; + valaddr_reg:x6; val_offset:448*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 448*FLEN/8, x9, x1, x2) + +inst_249: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8007; op2val:0x8000; + valaddr_reg:x6; val_offset:450*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 450*FLEN/8, x9, x1, x2) + +inst_250: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x83fc; + valaddr_reg:x6; val_offset:452*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 452*FLEN/8, x9, x1, x2) + +inst_251: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fc; op2val:0x8000; + valaddr_reg:x6; val_offset:454*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 454*FLEN/8, x9, x1, x2) + +inst_252: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8003; + valaddr_reg:x6; val_offset:456*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 456*FLEN/8, x9, x1, x2) + +inst_253: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8003; op2val:0x8000; + valaddr_reg:x6; val_offset:458*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 458*FLEN/8, x9, x1, x2) + +inst_254: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x83fe; + valaddr_reg:x6; val_offset:460*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 460*FLEN/8, x9, x1, x2) + +inst_255: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x8000; + valaddr_reg:x6; val_offset:462*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 462*FLEN/8, x9, x1, x2) + +inst_256: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1b6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x81b6; + valaddr_reg:x6; val_offset:464*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 464*FLEN/8, x9, x1, x2) + +inst_257: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x81b6; op2val:0x8000; + valaddr_reg:x6; val_offset:466*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 466*FLEN/8, x9, x1, x2) + +inst_258: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x36d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x836d; + valaddr_reg:x6; val_offset:468*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 468*FLEN/8, x9, x1, x2) + +inst_259: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x36d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x836d; op2val:0x8000; + valaddr_reg:x6; val_offset:470*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 470*FLEN/8, x9, x1, x2) + +inst_260: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0cc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x80cc; + valaddr_reg:x6; val_offset:472*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 472*FLEN/8, x9, x1, x2) + +inst_261: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0cc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x80cc; op2val:0x8000; + valaddr_reg:x6; val_offset:474*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 474*FLEN/8, x9, x1, x2) + +inst_262: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x333 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8333; + valaddr_reg:x6; val_offset:476*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 476*FLEN/8, x9, x1, x2) + +inst_263: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x333 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8333; op2val:0x8000; + valaddr_reg:x6; val_offset:478*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 478*FLEN/8, x9, x1, x2) + +inst_264: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1dd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x81dd; + valaddr_reg:x6; val_offset:480*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 480*FLEN/8, x9, x1, x2) + +inst_265: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1dd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x81dd; op2val:0x8000; + valaddr_reg:x6; val_offset:482*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 482*FLEN/8, x9, x1, x2) + +inst_266: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x222 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8222; + valaddr_reg:x6; val_offset:484*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 484*FLEN/8, x9, x1, x2) + +inst_267: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x222 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8222; op2val:0x8000; + valaddr_reg:x6; val_offset:486*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 486*FLEN/8, x9, x1, x2) + +inst_268: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x124 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8124; + valaddr_reg:x6; val_offset:488*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 488*FLEN/8, x9, x1, x2) + +inst_269: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x124 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8124; op2val:0x8000; + valaddr_reg:x6; val_offset:490*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 490*FLEN/8, x9, x1, x2) + +inst_270: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2db and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x82db; + valaddr_reg:x6; val_offset:492*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 492*FLEN/8, x9, x1, x2) + +inst_271: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x82db; op2val:0x8000; + valaddr_reg:x6; val_offset:494*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 494*FLEN/8, x9, x1, x2) + +inst_272: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x199 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8199; + valaddr_reg:x6; val_offset:496*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 496*FLEN/8, x9, x1, x2) + +inst_273: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x199 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8199; op2val:0x8000; + valaddr_reg:x6; val_offset:498*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 498*FLEN/8, x9, x1, x2) + +inst_274: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x266 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8266; + valaddr_reg:x6; val_offset:500*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 500*FLEN/8, x9, x1, x2) + +inst_275: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x266 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8266; op2val:0x8000; + valaddr_reg:x6; val_offset:502*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 502*FLEN/8, x9, x1, x2) + +inst_276: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x5400; + valaddr_reg:x6; val_offset:504*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 504*FLEN/8, x9, x1, x2) + +inst_277: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5400; op2val:0x8000; + valaddr_reg:x6; val_offset:506*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 506*FLEN/8, x9, x1, x2) + +inst_278: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x57ff; + valaddr_reg:x6; val_offset:508*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 508*FLEN/8, x9, x1, x2) + +inst_279: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x57ff; op2val:0x8000; + valaddr_reg:x6; val_offset:510*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 510*FLEN/8, x9, x1, x2) + +inst_280: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x5600; + valaddr_reg:x6; val_offset:512*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 512*FLEN/8, x9, x1, x2) + +inst_281: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5600; op2val:0x8000; + valaddr_reg:x6; val_offset:514*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 514*FLEN/8, x9, x1, x2) + +inst_282: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x55ff; + valaddr_reg:x6; val_offset:516*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 516*FLEN/8, x9, x1, x2) + +inst_283: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x55ff; op2val:0x8000; + valaddr_reg:x6; val_offset:518*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 518*FLEN/8, x9, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_2) + +inst_284: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x5700; + valaddr_reg:x6; val_offset:520*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 520*FLEN/8, x9, x1, x2) + +inst_285: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x300 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5700; op2val:0x8000; + valaddr_reg:x6; val_offset:522*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 522*FLEN/8, x9, x1, x2) + +inst_286: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x54ff; + valaddr_reg:x6; val_offset:524*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 524*FLEN/8, x9, x1, x2) + +inst_287: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x54ff; op2val:0x8000; + valaddr_reg:x6; val_offset:526*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 526*FLEN/8, x9, x1, x2) + +inst_288: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x5780; + valaddr_reg:x6; val_offset:528*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 528*FLEN/8, x9, x1, x2) + +inst_289: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x380 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5780; op2val:0x8000; + valaddr_reg:x6; val_offset:530*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 530*FLEN/8, x9, x1, x2) + +inst_290: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x547f; + valaddr_reg:x6; val_offset:532*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 532*FLEN/8, x9, x1, x2) + +inst_291: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x07f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x547f; op2val:0x8000; + valaddr_reg:x6; val_offset:534*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 534*FLEN/8, x9, x1, x2) + +inst_292: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x57c0; + valaddr_reg:x6; val_offset:536*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 536*FLEN/8, x9, x1, x2) + +inst_293: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x57c0; op2val:0x8000; + valaddr_reg:x6; val_offset:538*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 538*FLEN/8, x9, x1, x2) + +inst_294: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x543f; + valaddr_reg:x6; val_offset:540*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 540*FLEN/8, x9, x1, x2) + +inst_295: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x543f; op2val:0x8000; + valaddr_reg:x6; val_offset:542*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 542*FLEN/8, x9, x1, x2) + +inst_296: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x57e0; + valaddr_reg:x6; val_offset:544*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 544*FLEN/8, x9, x1, x2) + +inst_297: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x57e0; op2val:0x8000; + valaddr_reg:x6; val_offset:546*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 546*FLEN/8, x9, x1, x2) + +inst_298: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x541f; + valaddr_reg:x6; val_offset:548*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 548*FLEN/8, x9, x1, x2) + +inst_299: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x01f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x541f; op2val:0x8000; + valaddr_reg:x6; val_offset:550*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 550*FLEN/8, x9, x1, x2) + +inst_300: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x57f0; + valaddr_reg:x6; val_offset:552*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 552*FLEN/8, x9, x1, x2) + +inst_301: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x57f0; op2val:0x8000; + valaddr_reg:x6; val_offset:554*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 554*FLEN/8, x9, x1, x2) + +inst_302: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x540f; + valaddr_reg:x6; val_offset:556*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 556*FLEN/8, x9, x1, x2) + +inst_303: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x00f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x540f; op2val:0x8000; + valaddr_reg:x6; val_offset:558*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 558*FLEN/8, x9, x1, x2) + +inst_304: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x57f8; + valaddr_reg:x6; val_offset:560*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 560*FLEN/8, x9, x1, x2) + +inst_305: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x57f8; op2val:0x8000; + valaddr_reg:x6; val_offset:562*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 562*FLEN/8, x9, x1, x2) + +inst_306: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x5407; + valaddr_reg:x6; val_offset:564*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 564*FLEN/8, x9, x1, x2) + +inst_307: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5407; op2val:0x8000; + valaddr_reg:x6; val_offset:566*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 566*FLEN/8, x9, x1, x2) + +inst_308: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x57fc; + valaddr_reg:x6; val_offset:568*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 568*FLEN/8, x9, x1, x2) + +inst_309: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x57fc; op2val:0x8000; + valaddr_reg:x6; val_offset:570*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 570*FLEN/8, x9, x1, x2) + +inst_310: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x5403; + valaddr_reg:x6; val_offset:572*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 572*FLEN/8, x9, x1, x2) + +inst_311: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5403; op2val:0x8000; + valaddr_reg:x6; val_offset:574*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 574*FLEN/8, x9, x1, x2) + +inst_312: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x57fe; + valaddr_reg:x6; val_offset:576*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 576*FLEN/8, x9, x1, x2) + +inst_313: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x57fe; op2val:0x8000; + valaddr_reg:x6; val_offset:578*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 578*FLEN/8, x9, x1, x2) + +inst_314: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x5401; + valaddr_reg:x6; val_offset:580*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 580*FLEN/8, x9, x1, x2) + +inst_315: +// fs1 == 0 and fe1 == 0x15 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5401; op2val:0x8000; + valaddr_reg:x6; val_offset:582*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 582*FLEN/8, x9, x1, x2) + +inst_316: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8400; + valaddr_reg:x6; val_offset:584*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 584*FLEN/8, x9, x1, x2) + +inst_317: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8000; + valaddr_reg:x6; val_offset:586*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 586*FLEN/8, x9, x1, x2) + +inst_318: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x87ff; + valaddr_reg:x6; val_offset:588*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 588*FLEN/8, x9, x1, x2) + +inst_319: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x87ff; op2val:0x8000; + valaddr_reg:x6; val_offset:590*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 590*FLEN/8, x9, x1, x2) + +inst_320: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8600; + valaddr_reg:x6; val_offset:592*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 592*FLEN/8, x9, x1, x2) + +inst_321: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8600; op2val:0x8000; + valaddr_reg:x6; val_offset:594*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 594*FLEN/8, x9, x1, x2) + +inst_322: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x85ff; + valaddr_reg:x6; val_offset:596*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 596*FLEN/8, x9, x1, x2) + +inst_323: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x85ff; op2val:0x8000; + valaddr_reg:x6; val_offset:598*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 598*FLEN/8, x9, x1, x2) + +inst_324: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8700; + valaddr_reg:x6; val_offset:600*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 600*FLEN/8, x9, x1, x2) + +inst_325: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x300 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8700; op2val:0x8000; + valaddr_reg:x6; val_offset:602*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 602*FLEN/8, x9, x1, x2) + +inst_326: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x84ff; + valaddr_reg:x6; val_offset:604*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 604*FLEN/8, x9, x1, x2) + +inst_327: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x84ff; op2val:0x8000; + valaddr_reg:x6; val_offset:606*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 606*FLEN/8, x9, x1, x2) + +inst_328: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8780; + valaddr_reg:x6; val_offset:608*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 608*FLEN/8, x9, x1, x2) + +inst_329: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x380 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8780; op2val:0x8000; + valaddr_reg:x6; val_offset:610*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 610*FLEN/8, x9, x1, x2) + +inst_330: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x847f; + valaddr_reg:x6; val_offset:612*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 612*FLEN/8, x9, x1, x2) + +inst_331: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x07f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x847f; op2val:0x8000; + valaddr_reg:x6; val_offset:614*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 614*FLEN/8, x9, x1, x2) + +inst_332: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x87c0; + valaddr_reg:x6; val_offset:616*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 616*FLEN/8, x9, x1, x2) + +inst_333: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x87c0; op2val:0x8000; + valaddr_reg:x6; val_offset:618*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 618*FLEN/8, x9, x1, x2) + +inst_334: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x843f; + valaddr_reg:x6; val_offset:620*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 620*FLEN/8, x9, x1, x2) + +inst_335: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x843f; op2val:0x8000; + valaddr_reg:x6; val_offset:622*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 622*FLEN/8, x9, x1, x2) + +inst_336: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x87e0; + valaddr_reg:x6; val_offset:624*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 624*FLEN/8, x9, x1, x2) + +inst_337: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x87e0; op2val:0x8000; + valaddr_reg:x6; val_offset:626*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 626*FLEN/8, x9, x1, x2) + +inst_338: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x841f; + valaddr_reg:x6; val_offset:628*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 628*FLEN/8, x9, x1, x2) + +inst_339: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x01f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x841f; op2val:0x8000; + valaddr_reg:x6; val_offset:630*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 630*FLEN/8, x9, x1, x2) + +inst_340: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x87f0; + valaddr_reg:x6; val_offset:632*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 632*FLEN/8, x9, x1, x2) + +inst_341: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x87f0; op2val:0x8000; + valaddr_reg:x6; val_offset:634*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 634*FLEN/8, x9, x1, x2) + +inst_342: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x840f; + valaddr_reg:x6; val_offset:636*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 636*FLEN/8, x9, x1, x2) + +inst_343: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x00f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x840f; op2val:0x8000; + valaddr_reg:x6; val_offset:638*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 638*FLEN/8, x9, x1, x2) + +inst_344: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x87f8; + valaddr_reg:x6; val_offset:640*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 640*FLEN/8, x9, x1, x2) + +inst_345: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x87f8; op2val:0x8000; + valaddr_reg:x6; val_offset:642*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 642*FLEN/8, x9, x1, x2) + +inst_346: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8407; + valaddr_reg:x6; val_offset:644*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 644*FLEN/8, x9, x1, x2) + +inst_347: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8407; op2val:0x8000; + valaddr_reg:x6; val_offset:646*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 646*FLEN/8, x9, x1, x2) + +inst_348: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x87fc; + valaddr_reg:x6; val_offset:648*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 648*FLEN/8, x9, x1, x2) + +inst_349: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x87fc; op2val:0x8000; + valaddr_reg:x6; val_offset:650*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 650*FLEN/8, x9, x1, x2) + +inst_350: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8403; + valaddr_reg:x6; val_offset:652*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 652*FLEN/8, x9, x1, x2) + +inst_351: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8403; op2val:0x8000; + valaddr_reg:x6; val_offset:654*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 654*FLEN/8, x9, x1, x2) + +inst_352: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x87fe; + valaddr_reg:x6; val_offset:656*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 656*FLEN/8, x9, x1, x2) + +inst_353: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x87fe; op2val:0x8000; + valaddr_reg:x6; val_offset:658*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 658*FLEN/8, x9, x1, x2) + +inst_354: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8401; + valaddr_reg:x6; val_offset:660*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 660*FLEN/8, x9, x1, x2) + +inst_355: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8401; op2val:0x8000; + valaddr_reg:x6; val_offset:662*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 662*FLEN/8, x9, x1, x2) + +inst_356: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8800; + valaddr_reg:x6; val_offset:664*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 664*FLEN/8, x9, x1, x2) + +inst_357: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8800; op2val:0x8000; + valaddr_reg:x6; val_offset:666*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 666*FLEN/8, x9, x1, x2) + +inst_358: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8bff; + valaddr_reg:x6; val_offset:668*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 668*FLEN/8, x9, x1, x2) + +inst_359: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8bff; op2val:0x8000; + valaddr_reg:x6; val_offset:670*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 670*FLEN/8, x9, x1, x2) + +inst_360: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8a00; + valaddr_reg:x6; val_offset:672*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 672*FLEN/8, x9, x1, x2) + +inst_361: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8a00; op2val:0x8000; + valaddr_reg:x6; val_offset:674*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 674*FLEN/8, x9, x1, x2) + +inst_362: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x89ff; + valaddr_reg:x6; val_offset:676*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 676*FLEN/8, x9, x1, x2) + +inst_363: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x89ff; op2val:0x8000; + valaddr_reg:x6; val_offset:678*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 678*FLEN/8, x9, x1, x2) + +inst_364: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8b00; + valaddr_reg:x6; val_offset:680*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 680*FLEN/8, x9, x1, x2) + +inst_365: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x300 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8b00; op2val:0x8000; + valaddr_reg:x6; val_offset:682*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 682*FLEN/8, x9, x1, x2) + +inst_366: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x88ff; + valaddr_reg:x6; val_offset:684*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 684*FLEN/8, x9, x1, x2) + +inst_367: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x88ff; op2val:0x8000; + valaddr_reg:x6; val_offset:686*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 686*FLEN/8, x9, x1, x2) + +inst_368: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8b80; + valaddr_reg:x6; val_offset:688*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 688*FLEN/8, x9, x1, x2) + +inst_369: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x380 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8b80; op2val:0x8000; + valaddr_reg:x6; val_offset:690*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 690*FLEN/8, x9, x1, x2) + +inst_370: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x887f; + valaddr_reg:x6; val_offset:692*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 692*FLEN/8, x9, x1, x2) + +inst_371: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x07f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x887f; op2val:0x8000; + valaddr_reg:x6; val_offset:694*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 694*FLEN/8, x9, x1, x2) + +inst_372: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8bc0; + valaddr_reg:x6; val_offset:696*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 696*FLEN/8, x9, x1, x2) + +inst_373: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8bc0; op2val:0x8000; + valaddr_reg:x6; val_offset:698*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 698*FLEN/8, x9, x1, x2) + +inst_374: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x883f; + valaddr_reg:x6; val_offset:700*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 700*FLEN/8, x9, x1, x2) + +inst_375: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x883f; op2val:0x8000; + valaddr_reg:x6; val_offset:702*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 702*FLEN/8, x9, x1, x2) + +inst_376: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8be0; + valaddr_reg:x6; val_offset:704*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 704*FLEN/8, x9, x1, x2) + +inst_377: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8be0; op2val:0x8000; + valaddr_reg:x6; val_offset:706*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 706*FLEN/8, x9, x1, x2) + +inst_378: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x881f; + valaddr_reg:x6; val_offset:708*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 708*FLEN/8, x9, x1, x2) + +inst_379: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x01f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x881f; op2val:0x8000; + valaddr_reg:x6; val_offset:710*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 710*FLEN/8, x9, x1, x2) + +inst_380: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8bf0; + valaddr_reg:x6; val_offset:712*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 712*FLEN/8, x9, x1, x2) + +inst_381: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8bf0; op2val:0x8000; + valaddr_reg:x6; val_offset:714*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 714*FLEN/8, x9, x1, x2) + +inst_382: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x880f; + valaddr_reg:x6; val_offset:716*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 716*FLEN/8, x9, x1, x2) + +inst_383: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x00f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x880f; op2val:0x8000; + valaddr_reg:x6; val_offset:718*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 718*FLEN/8, x9, x1, x2) + +inst_384: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8bf8; + valaddr_reg:x6; val_offset:720*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 720*FLEN/8, x9, x1, x2) + +inst_385: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8bf8; op2val:0x8000; + valaddr_reg:x6; val_offset:722*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 722*FLEN/8, x9, x1, x2) + +inst_386: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8807; + valaddr_reg:x6; val_offset:724*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 724*FLEN/8, x9, x1, x2) + +inst_387: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8807; op2val:0x8000; + valaddr_reg:x6; val_offset:726*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 726*FLEN/8, x9, x1, x2) + +inst_388: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8bfc; + valaddr_reg:x6; val_offset:728*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 728*FLEN/8, x9, x1, x2) + +inst_389: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8bfc; op2val:0x8000; + valaddr_reg:x6; val_offset:730*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 730*FLEN/8, x9, x1, x2) + +inst_390: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8803; + valaddr_reg:x6; val_offset:732*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 732*FLEN/8, x9, x1, x2) + +inst_391: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8803; op2val:0x8000; + valaddr_reg:x6; val_offset:734*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 734*FLEN/8, x9, x1, x2) + +inst_392: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8bfe; + valaddr_reg:x6; val_offset:736*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 736*FLEN/8, x9, x1, x2) + +inst_393: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8bfe; op2val:0x8000; + valaddr_reg:x6; val_offset:738*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 738*FLEN/8, x9, x1, x2) + +inst_394: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8801; + valaddr_reg:x6; val_offset:740*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 740*FLEN/8, x9, x1, x2) + +inst_395: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8801; op2val:0x8000; + valaddr_reg:x6; val_offset:742*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 742*FLEN/8, x9, x1, x2) + +inst_396: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8c00; + valaddr_reg:x6; val_offset:744*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 744*FLEN/8, x9, x1, x2) + +inst_397: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8c00; op2val:0x8000; + valaddr_reg:x6; val_offset:746*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 746*FLEN/8, x9, x1, x2) + +inst_398: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8fff; + valaddr_reg:x6; val_offset:748*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 748*FLEN/8, x9, x1, x2) + +inst_399: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8fff; op2val:0x8000; + valaddr_reg:x6; val_offset:750*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 750*FLEN/8, x9, x1, x2) + +inst_400: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8e00; + valaddr_reg:x6; val_offset:752*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 752*FLEN/8, x9, x1, x2) + +inst_401: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8e00; op2val:0x8000; + valaddr_reg:x6; val_offset:754*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 754*FLEN/8, x9, x1, x2) + +inst_402: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8dff; + valaddr_reg:x6; val_offset:756*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 756*FLEN/8, x9, x1, x2) + +inst_403: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8dff; op2val:0x8000; + valaddr_reg:x6; val_offset:758*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 758*FLEN/8, x9, x1, x2) + +inst_404: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8f00; + valaddr_reg:x6; val_offset:760*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 760*FLEN/8, x9, x1, x2) + +inst_405: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x300 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8f00; op2val:0x8000; + valaddr_reg:x6; val_offset:762*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 762*FLEN/8, x9, x1, x2) + +inst_406: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8cff; + valaddr_reg:x6; val_offset:764*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 764*FLEN/8, x9, x1, x2) + +inst_407: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8cff; op2val:0x8000; + valaddr_reg:x6; val_offset:766*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 766*FLEN/8, x9, x1, x2) + +inst_408: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8f80; + valaddr_reg:x6; val_offset:768*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 768*FLEN/8, x9, x1, x2) + +inst_409: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x380 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8f80; op2val:0x8000; + valaddr_reg:x6; val_offset:770*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 770*FLEN/8, x9, x1, x2) + +inst_410: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8c7f; + valaddr_reg:x6; val_offset:772*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 772*FLEN/8, x9, x1, x2) + +inst_411: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x07f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8c7f; op2val:0x8000; + valaddr_reg:x6; val_offset:774*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 774*FLEN/8, x9, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_3) + +inst_412: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8fc0; + valaddr_reg:x6; val_offset:776*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 776*FLEN/8, x9, x1, x2) + +inst_413: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8fc0; op2val:0x8000; + valaddr_reg:x6; val_offset:778*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 778*FLEN/8, x9, x1, x2) + +inst_414: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8c3f; + valaddr_reg:x6; val_offset:780*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 780*FLEN/8, x9, x1, x2) + +inst_415: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8c3f; op2val:0x8000; + valaddr_reg:x6; val_offset:782*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 782*FLEN/8, x9, x1, x2) + +inst_416: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8fe0; + valaddr_reg:x6; val_offset:784*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 784*FLEN/8, x9, x1, x2) + +inst_417: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8fe0; op2val:0x8000; + valaddr_reg:x6; val_offset:786*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 786*FLEN/8, x9, x1, x2) + +inst_418: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8c1f; + valaddr_reg:x6; val_offset:788*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 788*FLEN/8, x9, x1, x2) + +inst_419: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x01f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8c1f; op2val:0x8000; + valaddr_reg:x6; val_offset:790*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 790*FLEN/8, x9, x1, x2) + +inst_420: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8ff0; + valaddr_reg:x6; val_offset:792*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 792*FLEN/8, x9, x1, x2) + +inst_421: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8ff0; op2val:0x8000; + valaddr_reg:x6; val_offset:794*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 794*FLEN/8, x9, x1, x2) + +inst_422: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8c0f; + valaddr_reg:x6; val_offset:796*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 796*FLEN/8, x9, x1, x2) + +inst_423: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x00f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8c0f; op2val:0x8000; + valaddr_reg:x6; val_offset:798*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 798*FLEN/8, x9, x1, x2) + +inst_424: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8ff8; + valaddr_reg:x6; val_offset:800*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 800*FLEN/8, x9, x1, x2) + +inst_425: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8ff8; op2val:0x8000; + valaddr_reg:x6; val_offset:802*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 802*FLEN/8, x9, x1, x2) + +inst_426: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8c07; + valaddr_reg:x6; val_offset:804*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 804*FLEN/8, x9, x1, x2) + +inst_427: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8c07; op2val:0x8000; + valaddr_reg:x6; val_offset:806*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 806*FLEN/8, x9, x1, x2) + +inst_428: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8ffc; + valaddr_reg:x6; val_offset:808*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 808*FLEN/8, x9, x1, x2) + +inst_429: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8ffc; op2val:0x8000; + valaddr_reg:x6; val_offset:810*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 810*FLEN/8, x9, x1, x2) + +inst_430: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8c03; + valaddr_reg:x6; val_offset:812*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 812*FLEN/8, x9, x1, x2) + +inst_431: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8c03; op2val:0x8000; + valaddr_reg:x6; val_offset:814*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 814*FLEN/8, x9, x1, x2) + +inst_432: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8ffe; + valaddr_reg:x6; val_offset:816*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 816*FLEN/8, x9, x1, x2) + +inst_433: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8ffe; op2val:0x8000; + valaddr_reg:x6; val_offset:818*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 818*FLEN/8, x9, x1, x2) + +inst_434: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8000; op2val:0x8c01; + valaddr_reg:x6; val_offset:820*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 820*FLEN/8, x9, x1, x2) + +inst_435: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8c01; op2val:0x8000; + valaddr_reg:x6; val_offset:822*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 822*FLEN/8, x9, x1, x2) + +inst_436: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x400; + valaddr_reg:x6; val_offset:824*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 824*FLEN/8, x9, x1, x2) + +inst_437: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x3c00; + valaddr_reg:x6; val_offset:826*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 826*FLEN/8, x9, x1, x2) + +inst_438: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7ff; + valaddr_reg:x6; val_offset:828*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 828*FLEN/8, x9, x1, x2) + +inst_439: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ff; op2val:0x3c00; + valaddr_reg:x6; val_offset:830*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 830*FLEN/8, x9, x1, x2) + +inst_440: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x600; + valaddr_reg:x6; val_offset:832*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 832*FLEN/8, x9, x1, x2) + +inst_441: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x600; op2val:0x3c00; + valaddr_reg:x6; val_offset:834*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 834*FLEN/8, x9, x1, x2) + +inst_442: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x5ff; + valaddr_reg:x6; val_offset:836*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 836*FLEN/8, x9, x1, x2) + +inst_443: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5ff; op2val:0x3c00; + valaddr_reg:x6; val_offset:838*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 838*FLEN/8, x9, x1, x2) + +inst_444: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x700; + valaddr_reg:x6; val_offset:840*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 840*FLEN/8, x9, x1, x2) + +inst_445: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x300 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x700; op2val:0x3c00; + valaddr_reg:x6; val_offset:842*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 842*FLEN/8, x9, x1, x2) + +inst_446: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x4ff; + valaddr_reg:x6; val_offset:844*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 844*FLEN/8, x9, x1, x2) + +inst_447: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4ff; op2val:0x3c00; + valaddr_reg:x6; val_offset:846*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 846*FLEN/8, x9, x1, x2) + +inst_448: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x780; + valaddr_reg:x6; val_offset:848*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 848*FLEN/8, x9, x1, x2) + +inst_449: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x380 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x780; op2val:0x3c00; + valaddr_reg:x6; val_offset:850*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 850*FLEN/8, x9, x1, x2) + +inst_450: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x47f; + valaddr_reg:x6; val_offset:852*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 852*FLEN/8, x9, x1, x2) + +inst_451: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x07f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x47f; op2val:0x3c00; + valaddr_reg:x6; val_offset:854*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 854*FLEN/8, x9, x1, x2) + +inst_452: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7c0; + valaddr_reg:x6; val_offset:856*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 856*FLEN/8, x9, x1, x2) + +inst_453: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c0; op2val:0x3c00; + valaddr_reg:x6; val_offset:858*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 858*FLEN/8, x9, x1, x2) + +inst_454: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x43f; + valaddr_reg:x6; val_offset:860*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 860*FLEN/8, x9, x1, x2) + +inst_455: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x43f; op2val:0x3c00; + valaddr_reg:x6; val_offset:862*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 862*FLEN/8, x9, x1, x2) + +inst_456: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7e0; + valaddr_reg:x6; val_offset:864*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 864*FLEN/8, x9, x1, x2) + +inst_457: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e0; op2val:0x3c00; + valaddr_reg:x6; val_offset:866*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 866*FLEN/8, x9, x1, x2) + +inst_458: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x41f; + valaddr_reg:x6; val_offset:868*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 868*FLEN/8, x9, x1, x2) + +inst_459: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x01f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x41f; op2val:0x3c00; + valaddr_reg:x6; val_offset:870*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 870*FLEN/8, x9, x1, x2) + +inst_460: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7f0; + valaddr_reg:x6; val_offset:872*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 872*FLEN/8, x9, x1, x2) + +inst_461: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7f0; op2val:0x3c00; + valaddr_reg:x6; val_offset:874*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 874*FLEN/8, x9, x1, x2) + +inst_462: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x40f; + valaddr_reg:x6; val_offset:876*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 876*FLEN/8, x9, x1, x2) + +inst_463: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x00f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x40f; op2val:0x3c00; + valaddr_reg:x6; val_offset:878*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 878*FLEN/8, x9, x1, x2) + +inst_464: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7f8; + valaddr_reg:x6; val_offset:880*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 880*FLEN/8, x9, x1, x2) + +inst_465: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7f8; op2val:0x3c00; + valaddr_reg:x6; val_offset:882*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 882*FLEN/8, x9, x1, x2) + +inst_466: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x407; + valaddr_reg:x6; val_offset:884*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 884*FLEN/8, x9, x1, x2) + +inst_467: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x407; op2val:0x3c00; + valaddr_reg:x6; val_offset:886*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 886*FLEN/8, x9, x1, x2) + +inst_468: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7fc; + valaddr_reg:x6; val_offset:888*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 888*FLEN/8, x9, x1, x2) + +inst_469: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7fc; op2val:0x3c00; + valaddr_reg:x6; val_offset:890*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 890*FLEN/8, x9, x1, x2) + +inst_470: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x403; + valaddr_reg:x6; val_offset:892*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 892*FLEN/8, x9, x1, x2) + +inst_471: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x003 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x403; op2val:0x3c00; + valaddr_reg:x6; val_offset:894*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 894*FLEN/8, x9, x1, x2) + +inst_472: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x7fe; + valaddr_reg:x6; val_offset:896*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 896*FLEN/8, x9, x1, x2) + +inst_473: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7fe; op2val:0x3c00; + valaddr_reg:x6; val_offset:898*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 898*FLEN/8, x9, x1, x2) + +inst_474: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x401; + valaddr_reg:x6; val_offset:900*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 900*FLEN/8, x9, x1, x2) + +inst_475: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x3c00; + valaddr_reg:x6; val_offset:902*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 902*FLEN/8, x9, x1, x2) + +inst_476: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3ffe; + valaddr_reg:x6; val_offset:904*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 904*FLEN/8, x9, x1, x2) + +inst_477: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ffe; op2val:0x3c00; + valaddr_reg:x6; val_offset:906*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 906*FLEN/8, x9, x1, x2) + +inst_478: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3c01; + valaddr_reg:x6; val_offset:908*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 908*FLEN/8, x9, x1, x2) + +inst_479: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c01; op2val:0x3c00; + valaddr_reg:x6; val_offset:910*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 910*FLEN/8, x9, x1, x2) + +inst_480: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1b6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3db6; + valaddr_reg:x6; val_offset:912*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 912*FLEN/8, x9, x1, x2) + +inst_481: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x1b6 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3db6; op2val:0x3c00; + valaddr_reg:x6; val_offset:914*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 914*FLEN/8, x9, x1, x2) + +inst_482: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x36d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3f6d; + valaddr_reg:x6; val_offset:916*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 916*FLEN/8, x9, x1, x2) + +inst_483: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x36d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3f6d; op2val:0x3c00; + valaddr_reg:x6; val_offset:918*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 918*FLEN/8, x9, x1, x2) + +inst_484: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0cc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3ccc; + valaddr_reg:x6; val_offset:920*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 920*FLEN/8, x9, x1, x2) + +inst_485: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x0cc and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ccc; op2val:0x3c00; + valaddr_reg:x6; val_offset:922*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 922*FLEN/8, x9, x1, x2) + +inst_486: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x333 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3f33; + valaddr_reg:x6; val_offset:924*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 924*FLEN/8, x9, x1, x2) + +inst_487: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x333 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3f33; op2val:0x3c00; + valaddr_reg:x6; val_offset:926*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 926*FLEN/8, x9, x1, x2) + +inst_488: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1dd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3ddd; + valaddr_reg:x6; val_offset:928*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 928*FLEN/8, x9, x1, x2) + +inst_489: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x1dd and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ddd; op2val:0x3c00; + valaddr_reg:x6; val_offset:930*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 930*FLEN/8, x9, x1, x2) + +inst_490: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x222 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3e22; + valaddr_reg:x6; val_offset:932*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 932*FLEN/8, x9, x1, x2) + +inst_491: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x222 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3e22; op2val:0x3c00; + valaddr_reg:x6; val_offset:934*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 934*FLEN/8, x9, x1, x2) + +inst_492: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x124 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3d24; + valaddr_reg:x6; val_offset:936*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 936*FLEN/8, x9, x1, x2) + +inst_493: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x124 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3d24; op2val:0x3c00; + valaddr_reg:x6; val_offset:938*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 938*FLEN/8, x9, x1, x2) + +inst_494: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2db and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3edb; + valaddr_reg:x6; val_offset:940*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 940*FLEN/8, x9, x1, x2) + +inst_495: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x2db and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3edb; op2val:0x3c00; + valaddr_reg:x6; val_offset:942*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 942*FLEN/8, x9, x1, x2) + +inst_496: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x199 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3d99; + valaddr_reg:x6; val_offset:944*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 944*FLEN/8, x9, x1, x2) + +inst_497: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x199 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3d99; op2val:0x3c00; + valaddr_reg:x6; val_offset:946*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 946*FLEN/8, x9, x1, x2) + +inst_498: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x266 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3e66; + valaddr_reg:x6; val_offset:948*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 948*FLEN/8, x9, x1, x2) + +inst_499: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x266 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3e66; op2val:0x3c00; + valaddr_reg:x6; val_offset:950*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 950*FLEN/8, x9, x1, x2) + +inst_500: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x5000; + valaddr_reg:x6; val_offset:952*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 952*FLEN/8, x9, x1, x2) + +inst_501: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5000; op2val:0x3c00; + valaddr_reg:x6; val_offset:954*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 954*FLEN/8, x9, x1, x2) + +inst_502: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x53ff; + valaddr_reg:x6; val_offset:956*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 956*FLEN/8, x9, x1, x2) + +inst_503: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x53ff; op2val:0x3c00; + valaddr_reg:x6; val_offset:958*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 958*FLEN/8, x9, x1, x2) + +inst_504: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x5200; + valaddr_reg:x6; val_offset:960*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 960*FLEN/8, x9, x1, x2) + +inst_505: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5200; op2val:0x3c00; + valaddr_reg:x6; val_offset:962*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 962*FLEN/8, x9, x1, x2) + +inst_506: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x51ff; + valaddr_reg:x6; val_offset:964*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 964*FLEN/8, x9, x1, x2) + +inst_507: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x51ff; op2val:0x3c00; + valaddr_reg:x6; val_offset:966*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 966*FLEN/8, x9, x1, x2) + +inst_508: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x5300; + valaddr_reg:x6; val_offset:968*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 968*FLEN/8, x9, x1, x2) + +inst_509: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x300 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5300; op2val:0x3c00; + valaddr_reg:x6; val_offset:970*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 970*FLEN/8, x9, x1, x2) + +inst_510: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x50ff; + valaddr_reg:x6; val_offset:972*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 972*FLEN/8, x9, x1, x2) + +inst_511: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x50ff; op2val:0x3c00; + valaddr_reg:x6; val_offset:974*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 974*FLEN/8, x9, x1, x2) + +inst_512: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x5380; + valaddr_reg:x6; val_offset:976*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 976*FLEN/8, x9, x1, x2) + +inst_513: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x380 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5380; op2val:0x3c00; + valaddr_reg:x6; val_offset:978*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 978*FLEN/8, x9, x1, x2) + +inst_514: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x507f; + valaddr_reg:x6; val_offset:980*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 980*FLEN/8, x9, x1, x2) + +inst_515: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x07f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x507f; op2val:0x3c00; + valaddr_reg:x6; val_offset:982*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 982*FLEN/8, x9, x1, x2) + +inst_516: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x53c0; + valaddr_reg:x6; val_offset:984*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 984*FLEN/8, x9, x1, x2) + +inst_517: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x53c0; op2val:0x3c00; + valaddr_reg:x6; val_offset:986*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 986*FLEN/8, x9, x1, x2) + +inst_518: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x503f; + valaddr_reg:x6; val_offset:988*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 988*FLEN/8, x9, x1, x2) + +inst_519: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x503f; op2val:0x3c00; + valaddr_reg:x6; val_offset:990*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 990*FLEN/8, x9, x1, x2) + +inst_520: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x53e0; + valaddr_reg:x6; val_offset:992*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 992*FLEN/8, x9, x1, x2) + +inst_521: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x53e0; op2val:0x3c00; + valaddr_reg:x6; val_offset:994*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 994*FLEN/8, x9, x1, x2) + +inst_522: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x501f; + valaddr_reg:x6; val_offset:996*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 996*FLEN/8, x9, x1, x2) + +inst_523: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x01f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x501f; op2val:0x3c00; + valaddr_reg:x6; val_offset:998*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 998*FLEN/8, x9, x1, x2) + +inst_524: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x53f0; + valaddr_reg:x6; val_offset:1000*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1000*FLEN/8, x9, x1, x2) + +inst_525: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x53f0; op2val:0x3c00; + valaddr_reg:x6; val_offset:1002*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1002*FLEN/8, x9, x1, x2) + +inst_526: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x500f; + valaddr_reg:x6; val_offset:1004*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1004*FLEN/8, x9, x1, x2) + +inst_527: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x00f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x500f; op2val:0x3c00; + valaddr_reg:x6; val_offset:1006*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1006*FLEN/8, x9, x1, x2) + +inst_528: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x53f8; + valaddr_reg:x6; val_offset:1008*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1008*FLEN/8, x9, x1, x2) + +inst_529: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x53f8; op2val:0x3c00; + valaddr_reg:x6; val_offset:1010*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1010*FLEN/8, x9, x1, x2) + +inst_530: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x5007; + valaddr_reg:x6; val_offset:1012*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1012*FLEN/8, x9, x1, x2) + +inst_531: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5007; op2val:0x3c00; + valaddr_reg:x6; val_offset:1014*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1014*FLEN/8, x9, x1, x2) + +inst_532: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x53fc; + valaddr_reg:x6; val_offset:1016*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1016*FLEN/8, x9, x1, x2) + +inst_533: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x53fc; op2val:0x3c00; + valaddr_reg:x6; val_offset:1018*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1018*FLEN/8, x9, x1, x2) + +inst_534: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x5003; + valaddr_reg:x6; val_offset:1020*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1020*FLEN/8, x9, x1, x2) + +inst_535: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x003 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5003; op2val:0x3c00; + valaddr_reg:x6; val_offset:1022*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1022*FLEN/8, x9, x1, x2) + +inst_536: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x53fe; + valaddr_reg:x6; val_offset:1024*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1024*FLEN/8, x9, x1, x2) + +inst_537: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x53fe; op2val:0x3c00; + valaddr_reg:x6; val_offset:1026*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1026*FLEN/8, x9, x1, x2) + +inst_538: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x5001; + valaddr_reg:x6; val_offset:1028*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1028*FLEN/8, x9, x1, x2) + +inst_539: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5001; op2val:0x3c00; + valaddr_reg:x6; val_offset:1030*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1030*FLEN/8, x9, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_4) + +inst_540: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2c00; + valaddr_reg:x6; val_offset:1032*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1032*FLEN/8, x9, x1, x2) + +inst_541: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2c00; op2val:0x3c00; + valaddr_reg:x6; val_offset:1034*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1034*FLEN/8, x9, x1, x2) + +inst_542: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2fff; + valaddr_reg:x6; val_offset:1036*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1036*FLEN/8, x9, x1, x2) + +inst_543: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2fff; op2val:0x3c00; + valaddr_reg:x6; val_offset:1038*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1038*FLEN/8, x9, x1, x2) + +inst_544: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2e00; + valaddr_reg:x6; val_offset:1040*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1040*FLEN/8, x9, x1, x2) + +inst_545: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e00; op2val:0x3c00; + valaddr_reg:x6; val_offset:1042*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1042*FLEN/8, x9, x1, x2) + +inst_546: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2dff; + valaddr_reg:x6; val_offset:1044*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1044*FLEN/8, x9, x1, x2) + +inst_547: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2dff; op2val:0x3c00; + valaddr_reg:x6; val_offset:1046*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1046*FLEN/8, x9, x1, x2) + +inst_548: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2f00; + valaddr_reg:x6; val_offset:1048*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1048*FLEN/8, x9, x1, x2) + +inst_549: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x300 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2f00; op2val:0x3c00; + valaddr_reg:x6; val_offset:1050*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1050*FLEN/8, x9, x1, x2) + +inst_550: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2cff; + valaddr_reg:x6; val_offset:1052*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1052*FLEN/8, x9, x1, x2) + +inst_551: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2cff; op2val:0x3c00; + valaddr_reg:x6; val_offset:1054*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1054*FLEN/8, x9, x1, x2) + +inst_552: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2f80; + valaddr_reg:x6; val_offset:1056*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1056*FLEN/8, x9, x1, x2) + +inst_553: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x380 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2f80; op2val:0x3c00; + valaddr_reg:x6; val_offset:1058*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1058*FLEN/8, x9, x1, x2) + +inst_554: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2c7f; + valaddr_reg:x6; val_offset:1060*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1060*FLEN/8, x9, x1, x2) + +inst_555: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x07f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2c7f; op2val:0x3c00; + valaddr_reg:x6; val_offset:1062*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1062*FLEN/8, x9, x1, x2) + +inst_556: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2fc0; + valaddr_reg:x6; val_offset:1064*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1064*FLEN/8, x9, x1, x2) + +inst_557: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2fc0; op2val:0x3c00; + valaddr_reg:x6; val_offset:1066*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1066*FLEN/8, x9, x1, x2) + +inst_558: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2c3f; + valaddr_reg:x6; val_offset:1068*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1068*FLEN/8, x9, x1, x2) + +inst_559: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x03f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2c3f; op2val:0x3c00; + valaddr_reg:x6; val_offset:1070*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1070*FLEN/8, x9, x1, x2) + +inst_560: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2fe0; + valaddr_reg:x6; val_offset:1072*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1072*FLEN/8, x9, x1, x2) + +inst_561: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2fe0; op2val:0x3c00; + valaddr_reg:x6; val_offset:1074*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1074*FLEN/8, x9, x1, x2) + +inst_562: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2c1f; + valaddr_reg:x6; val_offset:1076*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1076*FLEN/8, x9, x1, x2) + +inst_563: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x01f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2c1f; op2val:0x3c00; + valaddr_reg:x6; val_offset:1078*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1078*FLEN/8, x9, x1, x2) + +inst_564: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2ff0; + valaddr_reg:x6; val_offset:1080*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1080*FLEN/8, x9, x1, x2) + +inst_565: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ff0; op2val:0x3c00; + valaddr_reg:x6; val_offset:1082*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1082*FLEN/8, x9, x1, x2) + +inst_566: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2c0f; + valaddr_reg:x6; val_offset:1084*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1084*FLEN/8, x9, x1, x2) + +inst_567: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x00f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2c0f; op2val:0x3c00; + valaddr_reg:x6; val_offset:1086*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1086*FLEN/8, x9, x1, x2) + +inst_568: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2ff8; + valaddr_reg:x6; val_offset:1088*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1088*FLEN/8, x9, x1, x2) + +inst_569: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ff8; op2val:0x3c00; + valaddr_reg:x6; val_offset:1090*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1090*FLEN/8, x9, x1, x2) + +inst_570: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2c07; + valaddr_reg:x6; val_offset:1092*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1092*FLEN/8, x9, x1, x2) + +inst_571: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x007 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2c07; op2val:0x3c00; + valaddr_reg:x6; val_offset:1094*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1094*FLEN/8, x9, x1, x2) + +inst_572: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2ffc; + valaddr_reg:x6; val_offset:1096*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1096*FLEN/8, x9, x1, x2) + +inst_573: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ffc; op2val:0x3c00; + valaddr_reg:x6; val_offset:1098*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1098*FLEN/8, x9, x1, x2) + +inst_574: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2c03; + valaddr_reg:x6; val_offset:1100*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1100*FLEN/8, x9, x1, x2) + +inst_575: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x003 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2c03; op2val:0x3c00; + valaddr_reg:x6; val_offset:1102*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1102*FLEN/8, x9, x1, x2) + +inst_576: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2ffe; + valaddr_reg:x6; val_offset:1104*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1104*FLEN/8, x9, x1, x2) + +inst_577: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ffe; op2val:0x3c00; + valaddr_reg:x6; val_offset:1106*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1106*FLEN/8, x9, x1, x2) + +inst_578: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x2c01; + valaddr_reg:x6; val_offset:1108*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1108*FLEN/8, x9, x1, x2) + +inst_579: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2c01; op2val:0x3c00; + valaddr_reg:x6; val_offset:1110*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1110*FLEN/8, x9, x1, x2) + +inst_580: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3000; + valaddr_reg:x6; val_offset:1112*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1112*FLEN/8, x9, x1, x2) + +inst_581: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3000; op2val:0x3c00; + valaddr_reg:x6; val_offset:1114*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1114*FLEN/8, x9, x1, x2) + +inst_582: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x33ff; + valaddr_reg:x6; val_offset:1116*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1116*FLEN/8, x9, x1, x2) + +inst_583: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x33ff; op2val:0x3c00; + valaddr_reg:x6; val_offset:1118*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1118*FLEN/8, x9, x1, x2) + +inst_584: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3200; + valaddr_reg:x6; val_offset:1120*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1120*FLEN/8, x9, x1, x2) + +inst_585: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3200; op2val:0x3c00; + valaddr_reg:x6; val_offset:1122*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1122*FLEN/8, x9, x1, x2) + +inst_586: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x31ff; + valaddr_reg:x6; val_offset:1124*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1124*FLEN/8, x9, x1, x2) + +inst_587: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x31ff; op2val:0x3c00; + valaddr_reg:x6; val_offset:1126*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1126*FLEN/8, x9, x1, x2) + +inst_588: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3300; + valaddr_reg:x6; val_offset:1128*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1128*FLEN/8, x9, x1, x2) + +inst_589: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x300 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3300; op2val:0x3c00; + valaddr_reg:x6; val_offset:1130*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1130*FLEN/8, x9, x1, x2) + +inst_590: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x30ff; + valaddr_reg:x6; val_offset:1132*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1132*FLEN/8, x9, x1, x2) + +inst_591: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x30ff; op2val:0x3c00; + valaddr_reg:x6; val_offset:1134*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1134*FLEN/8, x9, x1, x2) + +inst_592: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3380; + valaddr_reg:x6; val_offset:1136*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1136*FLEN/8, x9, x1, x2) + +inst_593: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x380 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3380; op2val:0x3c00; + valaddr_reg:x6; val_offset:1138*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1138*FLEN/8, x9, x1, x2) + +inst_594: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x307f; + valaddr_reg:x6; val_offset:1140*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1140*FLEN/8, x9, x1, x2) + +inst_595: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x07f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x307f; op2val:0x3c00; + valaddr_reg:x6; val_offset:1142*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1142*FLEN/8, x9, x1, x2) + +inst_596: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x33c0; + valaddr_reg:x6; val_offset:1144*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1144*FLEN/8, x9, x1, x2) + +inst_597: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x33c0; op2val:0x3c00; + valaddr_reg:x6; val_offset:1146*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1146*FLEN/8, x9, x1, x2) + +inst_598: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x303f; + valaddr_reg:x6; val_offset:1148*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1148*FLEN/8, x9, x1, x2) + +inst_599: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x03f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x303f; op2val:0x3c00; + valaddr_reg:x6; val_offset:1150*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1150*FLEN/8, x9, x1, x2) + +inst_600: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x33e0; + valaddr_reg:x6; val_offset:1152*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1152*FLEN/8, x9, x1, x2) + +inst_601: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x33e0; op2val:0x3c00; + valaddr_reg:x6; val_offset:1154*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1154*FLEN/8, x9, x1, x2) + +inst_602: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x301f; + valaddr_reg:x6; val_offset:1156*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1156*FLEN/8, x9, x1, x2) + +inst_603: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x01f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x301f; op2val:0x3c00; + valaddr_reg:x6; val_offset:1158*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1158*FLEN/8, x9, x1, x2) + +inst_604: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x33f0; + valaddr_reg:x6; val_offset:1160*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1160*FLEN/8, x9, x1, x2) + +inst_605: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x33f0; op2val:0x3c00; + valaddr_reg:x6; val_offset:1162*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1162*FLEN/8, x9, x1, x2) + +inst_606: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x300f; + valaddr_reg:x6; val_offset:1164*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1164*FLEN/8, x9, x1, x2) + +inst_607: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x00f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x300f; op2val:0x3c00; + valaddr_reg:x6; val_offset:1166*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1166*FLEN/8, x9, x1, x2) + +inst_608: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x33f8; + valaddr_reg:x6; val_offset:1168*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1168*FLEN/8, x9, x1, x2) + +inst_609: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x33f8; op2val:0x3c00; + valaddr_reg:x6; val_offset:1170*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1170*FLEN/8, x9, x1, x2) + +inst_610: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3007; + valaddr_reg:x6; val_offset:1172*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1172*FLEN/8, x9, x1, x2) + +inst_611: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x007 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3007; op2val:0x3c00; + valaddr_reg:x6; val_offset:1174*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1174*FLEN/8, x9, x1, x2) + +inst_612: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x33fc; + valaddr_reg:x6; val_offset:1176*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1176*FLEN/8, x9, x1, x2) + +inst_613: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x33fc; op2val:0x3c00; + valaddr_reg:x6; val_offset:1178*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1178*FLEN/8, x9, x1, x2) + +inst_614: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3003; + valaddr_reg:x6; val_offset:1180*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1180*FLEN/8, x9, x1, x2) + +inst_615: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x003 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3003; op2val:0x3c00; + valaddr_reg:x6; val_offset:1182*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1182*FLEN/8, x9, x1, x2) + +inst_616: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x33fe; + valaddr_reg:x6; val_offset:1184*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1184*FLEN/8, x9, x1, x2) + +inst_617: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x33fe; op2val:0x3c00; + valaddr_reg:x6; val_offset:1186*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1186*FLEN/8, x9, x1, x2) + +inst_618: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3001; + valaddr_reg:x6; val_offset:1188*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1188*FLEN/8, x9, x1, x2) + +inst_619: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3001; op2val:0x3c00; + valaddr_reg:x6; val_offset:1190*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1190*FLEN/8, x9, x1, x2) + +inst_620: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3400; + valaddr_reg:x6; val_offset:1192*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1192*FLEN/8, x9, x1, x2) + +inst_621: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3400; op2val:0x3c00; + valaddr_reg:x6; val_offset:1194*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1194*FLEN/8, x9, x1, x2) + +inst_622: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x37ff; + valaddr_reg:x6; val_offset:1196*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1196*FLEN/8, x9, x1, x2) + +inst_623: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x37ff; op2val:0x3c00; + valaddr_reg:x6; val_offset:1198*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1198*FLEN/8, x9, x1, x2) + +inst_624: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3600; + valaddr_reg:x6; val_offset:1200*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1200*FLEN/8, x9, x1, x2) + +inst_625: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3600; op2val:0x3c00; + valaddr_reg:x6; val_offset:1202*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1202*FLEN/8, x9, x1, x2) + +inst_626: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x35ff; + valaddr_reg:x6; val_offset:1204*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1204*FLEN/8, x9, x1, x2) + +inst_627: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x35ff; op2val:0x3c00; + valaddr_reg:x6; val_offset:1206*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1206*FLEN/8, x9, x1, x2) + +inst_628: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3700; + valaddr_reg:x6; val_offset:1208*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1208*FLEN/8, x9, x1, x2) + +inst_629: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x300 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3700; op2val:0x3c00; + valaddr_reg:x6; val_offset:1210*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1210*FLEN/8, x9, x1, x2) + +inst_630: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x34ff; + valaddr_reg:x6; val_offset:1212*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1212*FLEN/8, x9, x1, x2) + +inst_631: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x34ff; op2val:0x3c00; + valaddr_reg:x6; val_offset:1214*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1214*FLEN/8, x9, x1, x2) + +inst_632: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3780; + valaddr_reg:x6; val_offset:1216*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1216*FLEN/8, x9, x1, x2) + +inst_633: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x380 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3780; op2val:0x3c00; + valaddr_reg:x6; val_offset:1218*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1218*FLEN/8, x9, x1, x2) + +inst_634: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x347f; + valaddr_reg:x6; val_offset:1220*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1220*FLEN/8, x9, x1, x2) + +inst_635: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x07f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x347f; op2val:0x3c00; + valaddr_reg:x6; val_offset:1222*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1222*FLEN/8, x9, x1, x2) + +inst_636: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x37c0; + valaddr_reg:x6; val_offset:1224*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1224*FLEN/8, x9, x1, x2) + +inst_637: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x37c0; op2val:0x3c00; + valaddr_reg:x6; val_offset:1226*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1226*FLEN/8, x9, x1, x2) + +inst_638: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x343f; + valaddr_reg:x6; val_offset:1228*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1228*FLEN/8, x9, x1, x2) + +inst_639: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x03f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x343f; op2val:0x3c00; + valaddr_reg:x6; val_offset:1230*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1230*FLEN/8, x9, x1, x2) + +inst_640: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x37e0; + valaddr_reg:x6; val_offset:1232*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1232*FLEN/8, x9, x1, x2) + +inst_641: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x37e0; op2val:0x3c00; + valaddr_reg:x6; val_offset:1234*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1234*FLEN/8, x9, x1, x2) + +inst_642: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x341f; + valaddr_reg:x6; val_offset:1236*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1236*FLEN/8, x9, x1, x2) + +inst_643: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x01f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x341f; op2val:0x3c00; + valaddr_reg:x6; val_offset:1238*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1238*FLEN/8, x9, x1, x2) + +inst_644: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x37f0; + valaddr_reg:x6; val_offset:1240*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1240*FLEN/8, x9, x1, x2) + +inst_645: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x37f0; op2val:0x3c00; + valaddr_reg:x6; val_offset:1242*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1242*FLEN/8, x9, x1, x2) + +inst_646: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x340f; + valaddr_reg:x6; val_offset:1244*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1244*FLEN/8, x9, x1, x2) + +inst_647: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x00f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x340f; op2val:0x3c00; + valaddr_reg:x6; val_offset:1246*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1246*FLEN/8, x9, x1, x2) + +inst_648: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x37f8; + valaddr_reg:x6; val_offset:1248*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1248*FLEN/8, x9, x1, x2) + +inst_649: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x37f8; op2val:0x3c00; + valaddr_reg:x6; val_offset:1250*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1250*FLEN/8, x9, x1, x2) + +inst_650: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3407; + valaddr_reg:x6; val_offset:1252*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1252*FLEN/8, x9, x1, x2) + +inst_651: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x007 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3407; op2val:0x3c00; + valaddr_reg:x6; val_offset:1254*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1254*FLEN/8, x9, x1, x2) + +inst_652: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x37fc; + valaddr_reg:x6; val_offset:1256*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1256*FLEN/8, x9, x1, x2) + +inst_653: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x37fc; op2val:0x3c00; + valaddr_reg:x6; val_offset:1258*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1258*FLEN/8, x9, x1, x2) + +inst_654: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3403; + valaddr_reg:x6; val_offset:1260*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1260*FLEN/8, x9, x1, x2) + +inst_655: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x003 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3403; op2val:0x3c00; + valaddr_reg:x6; val_offset:1262*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1262*FLEN/8, x9, x1, x2) + +inst_656: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x37fe; + valaddr_reg:x6; val_offset:1264*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1264*FLEN/8, x9, x1, x2) + +inst_657: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x37fe; op2val:0x3c00; + valaddr_reg:x6; val_offset:1266*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1266*FLEN/8, x9, x1, x2) + +inst_658: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3401; + valaddr_reg:x6; val_offset:1268*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1268*FLEN/8, x9, x1, x2) + +inst_659: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3401; op2val:0x3c00; + valaddr_reg:x6; val_offset:1270*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1270*FLEN/8, x9, x1, x2) + +inst_660: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3800; + valaddr_reg:x6; val_offset:1272*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1272*FLEN/8, x9, x1, x2) + +inst_661: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3800; op2val:0x3c00; + valaddr_reg:x6; val_offset:1274*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1274*FLEN/8, x9, x1, x2) + +inst_662: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3bff; + valaddr_reg:x6; val_offset:1276*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1276*FLEN/8, x9, x1, x2) + +inst_663: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bff; op2val:0x3c00; + valaddr_reg:x6; val_offset:1278*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1278*FLEN/8, x9, x1, x2) + +inst_664: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3a00; + valaddr_reg:x6; val_offset:1280*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1280*FLEN/8, x9, x1, x2) + +inst_665: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a00; op2val:0x3c00; + valaddr_reg:x6; val_offset:1282*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1282*FLEN/8, x9, x1, x2) + +inst_666: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x39ff; + valaddr_reg:x6; val_offset:1284*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1284*FLEN/8, x9, x1, x2) + +inst_667: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39ff; op2val:0x3c00; + valaddr_reg:x6; val_offset:1286*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1286*FLEN/8, x9, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_5) + +inst_668: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3b00; + valaddr_reg:x6; val_offset:1288*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1288*FLEN/8, x9, x1, x2) + +inst_669: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x300 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b00; op2val:0x3c00; + valaddr_reg:x6; val_offset:1290*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1290*FLEN/8, x9, x1, x2) + +inst_670: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x38ff; + valaddr_reg:x6; val_offset:1292*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1292*FLEN/8, x9, x1, x2) + +inst_671: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x38ff; op2val:0x3c00; + valaddr_reg:x6; val_offset:1294*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1294*FLEN/8, x9, x1, x2) + +inst_672: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3b80; + valaddr_reg:x6; val_offset:1296*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1296*FLEN/8, x9, x1, x2) + +inst_673: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x380 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b80; op2val:0x3c00; + valaddr_reg:x6; val_offset:1298*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1298*FLEN/8, x9, x1, x2) + +inst_674: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x387f; + valaddr_reg:x6; val_offset:1300*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1300*FLEN/8, x9, x1, x2) + +inst_675: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x07f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x387f; op2val:0x3c00; + valaddr_reg:x6; val_offset:1302*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1302*FLEN/8, x9, x1, x2) + +inst_676: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3bc0; + valaddr_reg:x6; val_offset:1304*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1304*FLEN/8, x9, x1, x2) + +inst_677: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bc0; op2val:0x3c00; + valaddr_reg:x6; val_offset:1306*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1306*FLEN/8, x9, x1, x2) + +inst_678: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x383f; + valaddr_reg:x6; val_offset:1308*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1308*FLEN/8, x9, x1, x2) + +inst_679: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x03f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x383f; op2val:0x3c00; + valaddr_reg:x6; val_offset:1310*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1310*FLEN/8, x9, x1, x2) + +inst_680: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3be0; + valaddr_reg:x6; val_offset:1312*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1312*FLEN/8, x9, x1, x2) + +inst_681: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3be0; op2val:0x3c00; + valaddr_reg:x6; val_offset:1314*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1314*FLEN/8, x9, x1, x2) + +inst_682: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x381f; + valaddr_reg:x6; val_offset:1316*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1316*FLEN/8, x9, x1, x2) + +inst_683: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x01f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x381f; op2val:0x3c00; + valaddr_reg:x6; val_offset:1318*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1318*FLEN/8, x9, x1, x2) + +inst_684: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3bf0; + valaddr_reg:x6; val_offset:1320*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1320*FLEN/8, x9, x1, x2) + +inst_685: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bf0; op2val:0x3c00; + valaddr_reg:x6; val_offset:1322*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1322*FLEN/8, x9, x1, x2) + +inst_686: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x380f; + valaddr_reg:x6; val_offset:1324*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1324*FLEN/8, x9, x1, x2) + +inst_687: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x00f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x380f; op2val:0x3c00; + valaddr_reg:x6; val_offset:1326*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1326*FLEN/8, x9, x1, x2) + +inst_688: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3bf8; + valaddr_reg:x6; val_offset:1328*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1328*FLEN/8, x9, x1, x2) + +inst_689: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bf8; op2val:0x3c00; + valaddr_reg:x6; val_offset:1330*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1330*FLEN/8, x9, x1, x2) + +inst_690: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3807; + valaddr_reg:x6; val_offset:1332*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1332*FLEN/8, x9, x1, x2) + +inst_691: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x007 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3807; op2val:0x3c00; + valaddr_reg:x6; val_offset:1334*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1334*FLEN/8, x9, x1, x2) + +inst_692: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3bfc; + valaddr_reg:x6; val_offset:1336*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1336*FLEN/8, x9, x1, x2) + +inst_693: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bfc; op2val:0x3c00; + valaddr_reg:x6; val_offset:1338*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1338*FLEN/8, x9, x1, x2) + +inst_694: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3803; + valaddr_reg:x6; val_offset:1340*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1340*FLEN/8, x9, x1, x2) + +inst_695: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x003 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3803; op2val:0x3c00; + valaddr_reg:x6; val_offset:1342*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1342*FLEN/8, x9, x1, x2) + +inst_696: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3bfe; + valaddr_reg:x6; val_offset:1344*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1344*FLEN/8, x9, x1, x2) + +inst_697: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bfe; op2val:0x3c00; + valaddr_reg:x6; val_offset:1346*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1346*FLEN/8, x9, x1, x2) + +inst_698: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3801; + valaddr_reg:x6; val_offset:1348*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1348*FLEN/8, x9, x1, x2) + +inst_699: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3801; op2val:0x3c00; + valaddr_reg:x6; val_offset:1350*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1350*FLEN/8, x9, x1, x2) + +inst_700: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3c00; + valaddr_reg:x6; val_offset:1352*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1352*FLEN/8, x9, x1, x2) + +inst_701: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3fff; + valaddr_reg:x6; val_offset:1354*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1354*FLEN/8, x9, x1, x2) + +inst_702: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fff; op2val:0x3c00; + valaddr_reg:x6; val_offset:1356*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1356*FLEN/8, x9, x1, x2) + +inst_703: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3e00; + valaddr_reg:x6; val_offset:1358*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1358*FLEN/8, x9, x1, x2) + +inst_704: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3e00; op2val:0x3c00; + valaddr_reg:x6; val_offset:1360*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1360*FLEN/8, x9, x1, x2) + +inst_705: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3dff; + valaddr_reg:x6; val_offset:1362*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1362*FLEN/8, x9, x1, x2) + +inst_706: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3dff; op2val:0x3c00; + valaddr_reg:x6; val_offset:1364*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1364*FLEN/8, x9, x1, x2) + +inst_707: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3f00; + valaddr_reg:x6; val_offset:1366*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1366*FLEN/8, x9, x1, x2) + +inst_708: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x300 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3f00; op2val:0x3c00; + valaddr_reg:x6; val_offset:1368*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1368*FLEN/8, x9, x1, x2) + +inst_709: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3cff; + valaddr_reg:x6; val_offset:1370*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1370*FLEN/8, x9, x1, x2) + +inst_710: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3cff; op2val:0x3c00; + valaddr_reg:x6; val_offset:1372*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1372*FLEN/8, x9, x1, x2) + +inst_711: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3f80; + valaddr_reg:x6; val_offset:1374*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1374*FLEN/8, x9, x1, x2) + +inst_712: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x380 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3f80; op2val:0x3c00; + valaddr_reg:x6; val_offset:1376*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1376*FLEN/8, x9, x1, x2) + +inst_713: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3c7f; + valaddr_reg:x6; val_offset:1378*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1378*FLEN/8, x9, x1, x2) + +inst_714: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x07f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c7f; op2val:0x3c00; + valaddr_reg:x6; val_offset:1380*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1380*FLEN/8, x9, x1, x2) + +inst_715: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3fc0; + valaddr_reg:x6; val_offset:1382*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1382*FLEN/8, x9, x1, x2) + +inst_716: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fc0; op2val:0x3c00; + valaddr_reg:x6; val_offset:1384*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1384*FLEN/8, x9, x1, x2) + +inst_717: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3c3f; + valaddr_reg:x6; val_offset:1386*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1386*FLEN/8, x9, x1, x2) + +inst_718: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x03f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c3f; op2val:0x3c00; + valaddr_reg:x6; val_offset:1388*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1388*FLEN/8, x9, x1, x2) + +inst_719: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3fe0; + valaddr_reg:x6; val_offset:1390*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1390*FLEN/8, x9, x1, x2) + +inst_720: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fe0; op2val:0x3c00; + valaddr_reg:x6; val_offset:1392*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1392*FLEN/8, x9, x1, x2) + +inst_721: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3c1f; + valaddr_reg:x6; val_offset:1394*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1394*FLEN/8, x9, x1, x2) + +inst_722: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x01f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c1f; op2val:0x3c00; + valaddr_reg:x6; val_offset:1396*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1396*FLEN/8, x9, x1, x2) + +inst_723: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3ff0; + valaddr_reg:x6; val_offset:1398*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1398*FLEN/8, x9, x1, x2) + +inst_724: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff0; op2val:0x3c00; + valaddr_reg:x6; val_offset:1400*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1400*FLEN/8, x9, x1, x2) + +inst_725: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3c0f; + valaddr_reg:x6; val_offset:1402*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1402*FLEN/8, x9, x1, x2) + +inst_726: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x00f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c0f; op2val:0x3c00; + valaddr_reg:x6; val_offset:1404*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1404*FLEN/8, x9, x1, x2) + +inst_727: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3ff8; + valaddr_reg:x6; val_offset:1406*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1406*FLEN/8, x9, x1, x2) + +inst_728: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff8; op2val:0x3c00; + valaddr_reg:x6; val_offset:1408*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1408*FLEN/8, x9, x1, x2) + +inst_729: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3c07; + valaddr_reg:x6; val_offset:1410*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1410*FLEN/8, x9, x1, x2) + +inst_730: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x007 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c07; op2val:0x3c00; + valaddr_reg:x6; val_offset:1412*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1412*FLEN/8, x9, x1, x2) + +inst_731: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3ffc; + valaddr_reg:x6; val_offset:1414*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1414*FLEN/8, x9, x1, x2) + +inst_732: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ffc; op2val:0x3c00; + valaddr_reg:x6; val_offset:1416*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1416*FLEN/8, x9, x1, x2) + +inst_733: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x3c03; + valaddr_reg:x6; val_offset:1418*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1418*FLEN/8, x9, x1, x2) + +inst_734: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x003 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c03; op2val:0x3c00; + valaddr_reg:x6; val_offset:1420*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1420*FLEN/8, x9, x1, x2) + +inst_735: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x4000; + valaddr_reg:x6; val_offset:1422*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1422*FLEN/8, x9, x1, x2) + +inst_736: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4000; op2val:0x3c00; + valaddr_reg:x6; val_offset:1424*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1424*FLEN/8, x9, x1, x2) + +inst_737: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x43ff; + valaddr_reg:x6; val_offset:1426*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1426*FLEN/8, x9, x1, x2) + +inst_738: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x43ff; op2val:0x3c00; + valaddr_reg:x6; val_offset:1428*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1428*FLEN/8, x9, x1, x2) + +inst_739: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x4200; + valaddr_reg:x6; val_offset:1430*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1430*FLEN/8, x9, x1, x2) + +inst_740: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4200; op2val:0x3c00; + valaddr_reg:x6; val_offset:1432*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1432*FLEN/8, x9, x1, x2) + +inst_741: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x41ff; + valaddr_reg:x6; val_offset:1434*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1434*FLEN/8, x9, x1, x2) + +inst_742: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x41ff; op2val:0x3c00; + valaddr_reg:x6; val_offset:1436*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1436*FLEN/8, x9, x1, x2) + +inst_743: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x4300; + valaddr_reg:x6; val_offset:1438*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1438*FLEN/8, x9, x1, x2) + +inst_744: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x300 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4300; op2val:0x3c00; + valaddr_reg:x6; val_offset:1440*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1440*FLEN/8, x9, x1, x2) + +inst_745: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x40ff; + valaddr_reg:x6; val_offset:1442*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1442*FLEN/8, x9, x1, x2) + +inst_746: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x40ff; op2val:0x3c00; + valaddr_reg:x6; val_offset:1444*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1444*FLEN/8, x9, x1, x2) + +inst_747: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x4380; + valaddr_reg:x6; val_offset:1446*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1446*FLEN/8, x9, x1, x2) + +inst_748: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x380 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4380; op2val:0x3c00; + valaddr_reg:x6; val_offset:1448*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1448*FLEN/8, x9, x1, x2) + +inst_749: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x407f; + valaddr_reg:x6; val_offset:1450*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1450*FLEN/8, x9, x1, x2) + +inst_750: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x07f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x407f; op2val:0x3c00; + valaddr_reg:x6; val_offset:1452*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1452*FLEN/8, x9, x1, x2) + +inst_751: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x43c0; + valaddr_reg:x6; val_offset:1454*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1454*FLEN/8, x9, x1, x2) + +inst_752: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x43c0; op2val:0x3c00; + valaddr_reg:x6; val_offset:1456*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1456*FLEN/8, x9, x1, x2) + +inst_753: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x403f; + valaddr_reg:x6; val_offset:1458*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1458*FLEN/8, x9, x1, x2) + +inst_754: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x403f; op2val:0x3c00; + valaddr_reg:x6; val_offset:1460*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1460*FLEN/8, x9, x1, x2) + +inst_755: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x43e0; + valaddr_reg:x6; val_offset:1462*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1462*FLEN/8, x9, x1, x2) + +inst_756: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x43e0; op2val:0x3c00; + valaddr_reg:x6; val_offset:1464*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1464*FLEN/8, x9, x1, x2) + +inst_757: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x401f; + valaddr_reg:x6; val_offset:1466*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1466*FLEN/8, x9, x1, x2) + +inst_758: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x01f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x401f; op2val:0x3c00; + valaddr_reg:x6; val_offset:1468*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1468*FLEN/8, x9, x1, x2) + +inst_759: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x43f0; + valaddr_reg:x6; val_offset:1470*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1470*FLEN/8, x9, x1, x2) + +inst_760: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x43f0; op2val:0x3c00; + valaddr_reg:x6; val_offset:1472*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1472*FLEN/8, x9, x1, x2) + +inst_761: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x400f; + valaddr_reg:x6; val_offset:1474*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1474*FLEN/8, x9, x1, x2) + +inst_762: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x00f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400f; op2val:0x3c00; + valaddr_reg:x6; val_offset:1476*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1476*FLEN/8, x9, x1, x2) + +inst_763: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x43f8; + valaddr_reg:x6; val_offset:1478*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1478*FLEN/8, x9, x1, x2) + +inst_764: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x43f8; op2val:0x3c00; + valaddr_reg:x6; val_offset:1480*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1480*FLEN/8, x9, x1, x2) + +inst_765: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x4007; + valaddr_reg:x6; val_offset:1482*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1482*FLEN/8, x9, x1, x2) + +inst_766: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4007; op2val:0x3c00; + valaddr_reg:x6; val_offset:1484*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1484*FLEN/8, x9, x1, x2) + +inst_767: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x43fc; + valaddr_reg:x6; val_offset:1486*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1486*FLEN/8, x9, x1, x2) + +inst_768: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x43fc; op2val:0x3c00; + valaddr_reg:x6; val_offset:1488*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1488*FLEN/8, x9, x1, x2) + +inst_769: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x4003; + valaddr_reg:x6; val_offset:1490*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1490*FLEN/8, x9, x1, x2) + +inst_770: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x003 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4003; op2val:0x3c00; + valaddr_reg:x6; val_offset:1492*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1492*FLEN/8, x9, x1, x2) + +inst_771: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x43fe; + valaddr_reg:x6; val_offset:1494*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1494*FLEN/8, x9, x1, x2) + +inst_772: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x43fe; op2val:0x3c00; + valaddr_reg:x6; val_offset:1496*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1496*FLEN/8, x9, x1, x2) + +inst_773: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x4001; + valaddr_reg:x6; val_offset:1498*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1498*FLEN/8, x9, x1, x2) + +inst_774: +// fs1 == 0 and fe1 == 0x10 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4001; op2val:0x3c00; + valaddr_reg:x6; val_offset:1500*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1500*FLEN/8, x9, x1, x2) + +inst_775: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x4400; + valaddr_reg:x6; val_offset:1502*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1502*FLEN/8, x9, x1, x2) + +inst_776: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4400; op2val:0x3c00; + valaddr_reg:x6; val_offset:1504*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1504*FLEN/8, x9, x1, x2) + +inst_777: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x47ff; + valaddr_reg:x6; val_offset:1506*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1506*FLEN/8, x9, x1, x2) + +inst_778: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x47ff; op2val:0x3c00; + valaddr_reg:x6; val_offset:1508*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1508*FLEN/8, x9, x1, x2) + +inst_779: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x4600; + valaddr_reg:x6; val_offset:1510*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1510*FLEN/8, x9, x1, x2) + +inst_780: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4600; op2val:0x3c00; + valaddr_reg:x6; val_offset:1512*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1512*FLEN/8, x9, x1, x2) + +inst_781: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x45ff; + valaddr_reg:x6; val_offset:1514*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1514*FLEN/8, x9, x1, x2) + +inst_782: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x45ff; op2val:0x3c00; + valaddr_reg:x6; val_offset:1516*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1516*FLEN/8, x9, x1, x2) + +inst_783: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x4700; + valaddr_reg:x6; val_offset:1518*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1518*FLEN/8, x9, x1, x2) + +inst_784: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x300 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4700; op2val:0x3c00; + valaddr_reg:x6; val_offset:1520*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1520*FLEN/8, x9, x1, x2) + +inst_785: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x44ff; + valaddr_reg:x6; val_offset:1522*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1522*FLEN/8, x9, x1, x2) + +inst_786: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x44ff; op2val:0x3c00; + valaddr_reg:x6; val_offset:1524*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1524*FLEN/8, x9, x1, x2) + +inst_787: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x4780; + valaddr_reg:x6; val_offset:1526*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1526*FLEN/8, x9, x1, x2) + +inst_788: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x380 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4780; op2val:0x3c00; + valaddr_reg:x6; val_offset:1528*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1528*FLEN/8, x9, x1, x2) + +inst_789: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x447f; + valaddr_reg:x6; val_offset:1530*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1530*FLEN/8, x9, x1, x2) + +inst_790: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x07f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x447f; op2val:0x3c00; + valaddr_reg:x6; val_offset:1532*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1532*FLEN/8, x9, x1, x2) + +inst_791: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x47c0; + valaddr_reg:x6; val_offset:1534*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1534*FLEN/8, x9, x1, x2) + +inst_792: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x47c0; op2val:0x3c00; + valaddr_reg:x6; val_offset:1536*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1536*FLEN/8, x9, x1, x2) + +inst_793: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x443f; + valaddr_reg:x6; val_offset:1538*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1538*FLEN/8, x9, x1, x2) + +inst_794: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x443f; op2val:0x3c00; + valaddr_reg:x6; val_offset:1540*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1540*FLEN/8, x9, x1, x2) + +inst_795: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x47e0; + valaddr_reg:x6; val_offset:1542*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1542*FLEN/8, x9, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_6) + +inst_796: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x47e0; op2val:0x3c00; + valaddr_reg:x6; val_offset:1544*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1544*FLEN/8, x9, x1, x2) + +inst_797: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x441f; + valaddr_reg:x6; val_offset:1546*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1546*FLEN/8, x9, x1, x2) + +inst_798: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x01f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x441f; op2val:0x3c00; + valaddr_reg:x6; val_offset:1548*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1548*FLEN/8, x9, x1, x2) + +inst_799: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x47f0; + valaddr_reg:x6; val_offset:1550*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1550*FLEN/8, x9, x1, x2) + +inst_800: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x47f0; op2val:0x3c00; + valaddr_reg:x6; val_offset:1552*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1552*FLEN/8, x9, x1, x2) + +inst_801: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x440f; + valaddr_reg:x6; val_offset:1554*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1554*FLEN/8, x9, x1, x2) + +inst_802: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x00f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x440f; op2val:0x3c00; + valaddr_reg:x6; val_offset:1556*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1556*FLEN/8, x9, x1, x2) + +inst_803: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x47f8; + valaddr_reg:x6; val_offset:1558*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1558*FLEN/8, x9, x1, x2) + +inst_804: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x47f8; op2val:0x3c00; + valaddr_reg:x6; val_offset:1560*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1560*FLEN/8, x9, x1, x2) + +inst_805: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x4407; + valaddr_reg:x6; val_offset:1562*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1562*FLEN/8, x9, x1, x2) + +inst_806: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4407; op2val:0x3c00; + valaddr_reg:x6; val_offset:1564*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1564*FLEN/8, x9, x1, x2) + +inst_807: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x47fc; + valaddr_reg:x6; val_offset:1566*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1566*FLEN/8, x9, x1, x2) + +inst_808: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x47fc; op2val:0x3c00; + valaddr_reg:x6; val_offset:1568*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1568*FLEN/8, x9, x1, x2) + +inst_809: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x4403; + valaddr_reg:x6; val_offset:1570*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1570*FLEN/8, x9, x1, x2) + +inst_810: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x003 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4403; op2val:0x3c00; + valaddr_reg:x6; val_offset:1572*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1572*FLEN/8, x9, x1, x2) + +inst_811: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x47fe; + valaddr_reg:x6; val_offset:1574*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1574*FLEN/8, x9, x1, x2) + +inst_812: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x47fe; op2val:0x3c00; + valaddr_reg:x6; val_offset:1576*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1576*FLEN/8, x9, x1, x2) + +inst_813: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x4401; + valaddr_reg:x6; val_offset:1578*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1578*FLEN/8, x9, x1, x2) + +inst_814: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4401; op2val:0x3c00; + valaddr_reg:x6; val_offset:1580*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1580*FLEN/8, x9, x1, x2) + +inst_815: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x4800; + valaddr_reg:x6; val_offset:1582*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1582*FLEN/8, x9, x1, x2) + +inst_816: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4800; op2val:0x3c00; + valaddr_reg:x6; val_offset:1584*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1584*FLEN/8, x9, x1, x2) + +inst_817: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x4bff; + valaddr_reg:x6; val_offset:1586*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1586*FLEN/8, x9, x1, x2) + +inst_818: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4bff; op2val:0x3c00; + valaddr_reg:x6; val_offset:1588*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1588*FLEN/8, x9, x1, x2) + +inst_819: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x4a00; + valaddr_reg:x6; val_offset:1590*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1590*FLEN/8, x9, x1, x2) + +inst_820: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x200 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4a00; op2val:0x3c00; + valaddr_reg:x6; val_offset:1592*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1592*FLEN/8, x9, x1, x2) + +inst_821: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x49ff; + valaddr_reg:x6; val_offset:1594*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1594*FLEN/8, x9, x1, x2) + +inst_822: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x49ff; op2val:0x3c00; + valaddr_reg:x6; val_offset:1596*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1596*FLEN/8, x9, x1, x2) + +inst_823: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x4b00; + valaddr_reg:x6; val_offset:1598*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1598*FLEN/8, x9, x1, x2) + +inst_824: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x300 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4b00; op2val:0x3c00; + valaddr_reg:x6; val_offset:1600*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1600*FLEN/8, x9, x1, x2) + +inst_825: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x48ff; + valaddr_reg:x6; val_offset:1602*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1602*FLEN/8, x9, x1, x2) + +inst_826: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x48ff; op2val:0x3c00; + valaddr_reg:x6; val_offset:1604*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1604*FLEN/8, x9, x1, x2) + +inst_827: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x4b80; + valaddr_reg:x6; val_offset:1606*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1606*FLEN/8, x9, x1, x2) + +inst_828: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x380 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4b80; op2val:0x3c00; + valaddr_reg:x6; val_offset:1608*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1608*FLEN/8, x9, x1, x2) + +inst_829: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x487f; + valaddr_reg:x6; val_offset:1610*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1610*FLEN/8, x9, x1, x2) + +inst_830: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x07f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x487f; op2val:0x3c00; + valaddr_reg:x6; val_offset:1612*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1612*FLEN/8, x9, x1, x2) + +inst_831: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x4bc0; + valaddr_reg:x6; val_offset:1614*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1614*FLEN/8, x9, x1, x2) + +inst_832: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4bc0; op2val:0x3c00; + valaddr_reg:x6; val_offset:1616*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1616*FLEN/8, x9, x1, x2) + +inst_833: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x483f; + valaddr_reg:x6; val_offset:1618*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1618*FLEN/8, x9, x1, x2) + +inst_834: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x483f; op2val:0x3c00; + valaddr_reg:x6; val_offset:1620*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1620*FLEN/8, x9, x1, x2) + +inst_835: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x4be0; + valaddr_reg:x6; val_offset:1622*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1622*FLEN/8, x9, x1, x2) + +inst_836: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4be0; op2val:0x3c00; + valaddr_reg:x6; val_offset:1624*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1624*FLEN/8, x9, x1, x2) + +inst_837: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x481f; + valaddr_reg:x6; val_offset:1626*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1626*FLEN/8, x9, x1, x2) + +inst_838: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x01f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x481f; op2val:0x3c00; + valaddr_reg:x6; val_offset:1628*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1628*FLEN/8, x9, x1, x2) + +inst_839: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x4bf0; + valaddr_reg:x6; val_offset:1630*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1630*FLEN/8, x9, x1, x2) + +inst_840: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4bf0; op2val:0x3c00; + valaddr_reg:x6; val_offset:1632*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1632*FLEN/8, x9, x1, x2) + +inst_841: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x480f; + valaddr_reg:x6; val_offset:1634*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1634*FLEN/8, x9, x1, x2) + +inst_842: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x00f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x480f; op2val:0x3c00; + valaddr_reg:x6; val_offset:1636*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1636*FLEN/8, x9, x1, x2) + +inst_843: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x4bf8; + valaddr_reg:x6; val_offset:1638*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1638*FLEN/8, x9, x1, x2) + +inst_844: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4bf8; op2val:0x3c00; + valaddr_reg:x6; val_offset:1640*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1640*FLEN/8, x9, x1, x2) + +inst_845: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x4807; + valaddr_reg:x6; val_offset:1642*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1642*FLEN/8, x9, x1, x2) + +inst_846: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4807; op2val:0x3c00; + valaddr_reg:x6; val_offset:1644*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1644*FLEN/8, x9, x1, x2) + +inst_847: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x4bfc; + valaddr_reg:x6; val_offset:1646*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1646*FLEN/8, x9, x1, x2) + +inst_848: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4bfc; op2val:0x3c00; + valaddr_reg:x6; val_offset:1648*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1648*FLEN/8, x9, x1, x2) + +inst_849: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x4803; + valaddr_reg:x6; val_offset:1650*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1650*FLEN/8, x9, x1, x2) + +inst_850: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x003 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4803; op2val:0x3c00; + valaddr_reg:x6; val_offset:1652*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1652*FLEN/8, x9, x1, x2) + +inst_851: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x4bfe; + valaddr_reg:x6; val_offset:1654*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1654*FLEN/8, x9, x1, x2) + +inst_852: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4bfe; op2val:0x3c00; + valaddr_reg:x6; val_offset:1656*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1656*FLEN/8, x9, x1, x2) + +inst_853: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c00; op2val:0x4801; + valaddr_reg:x6; val_offset:1658*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1658*FLEN/8, x9, x1, x2) + +inst_854: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4801; op2val:0x3c00; + valaddr_reg:x6; val_offset:1660*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1660*FLEN/8, x9, x1, x2) + +inst_855: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x8400; + valaddr_reg:x6; val_offset:1662*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1662*FLEN/8, x9, x1, x2) + +inst_856: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xbc00; + valaddr_reg:x6; val_offset:1664*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1664*FLEN/8, x9, x1, x2) + +inst_857: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x87ff; + valaddr_reg:x6; val_offset:1666*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1666*FLEN/8, x9, x1, x2) + +inst_858: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x87ff; op2val:0xbc00; + valaddr_reg:x6; val_offset:1668*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1668*FLEN/8, x9, x1, x2) + +inst_859: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x8600; + valaddr_reg:x6; val_offset:1670*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1670*FLEN/8, x9, x1, x2) + +inst_860: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8600; op2val:0xbc00; + valaddr_reg:x6; val_offset:1672*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1672*FLEN/8, x9, x1, x2) + +inst_861: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x85ff; + valaddr_reg:x6; val_offset:1674*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1674*FLEN/8, x9, x1, x2) + +inst_862: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x85ff; op2val:0xbc00; + valaddr_reg:x6; val_offset:1676*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1676*FLEN/8, x9, x1, x2) + +inst_863: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x8700; + valaddr_reg:x6; val_offset:1678*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1678*FLEN/8, x9, x1, x2) + +inst_864: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x300 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8700; op2val:0xbc00; + valaddr_reg:x6; val_offset:1680*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1680*FLEN/8, x9, x1, x2) + +inst_865: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x84ff; + valaddr_reg:x6; val_offset:1682*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1682*FLEN/8, x9, x1, x2) + +inst_866: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x84ff; op2val:0xbc00; + valaddr_reg:x6; val_offset:1684*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1684*FLEN/8, x9, x1, x2) + +inst_867: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x8780; + valaddr_reg:x6; val_offset:1686*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1686*FLEN/8, x9, x1, x2) + +inst_868: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x380 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8780; op2val:0xbc00; + valaddr_reg:x6; val_offset:1688*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1688*FLEN/8, x9, x1, x2) + +inst_869: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x847f; + valaddr_reg:x6; val_offset:1690*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1690*FLEN/8, x9, x1, x2) + +inst_870: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x07f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x847f; op2val:0xbc00; + valaddr_reg:x6; val_offset:1692*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1692*FLEN/8, x9, x1, x2) + +inst_871: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x87c0; + valaddr_reg:x6; val_offset:1694*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1694*FLEN/8, x9, x1, x2) + +inst_872: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x87c0; op2val:0xbc00; + valaddr_reg:x6; val_offset:1696*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1696*FLEN/8, x9, x1, x2) + +inst_873: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x843f; + valaddr_reg:x6; val_offset:1698*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1698*FLEN/8, x9, x1, x2) + +inst_874: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x843f; op2val:0xbc00; + valaddr_reg:x6; val_offset:1700*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1700*FLEN/8, x9, x1, x2) + +inst_875: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x87e0; + valaddr_reg:x6; val_offset:1702*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1702*FLEN/8, x9, x1, x2) + +inst_876: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x87e0; op2val:0xbc00; + valaddr_reg:x6; val_offset:1704*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1704*FLEN/8, x9, x1, x2) + +inst_877: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x841f; + valaddr_reg:x6; val_offset:1706*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1706*FLEN/8, x9, x1, x2) + +inst_878: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x01f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x841f; op2val:0xbc00; + valaddr_reg:x6; val_offset:1708*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1708*FLEN/8, x9, x1, x2) + +inst_879: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x87f0; + valaddr_reg:x6; val_offset:1710*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1710*FLEN/8, x9, x1, x2) + +inst_880: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x87f0; op2val:0xbc00; + valaddr_reg:x6; val_offset:1712*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1712*FLEN/8, x9, x1, x2) + +inst_881: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x840f; + valaddr_reg:x6; val_offset:1714*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1714*FLEN/8, x9, x1, x2) + +inst_882: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x00f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x840f; op2val:0xbc00; + valaddr_reg:x6; val_offset:1716*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1716*FLEN/8, x9, x1, x2) + +inst_883: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x87f8; + valaddr_reg:x6; val_offset:1718*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1718*FLEN/8, x9, x1, x2) + +inst_884: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x87f8; op2val:0xbc00; + valaddr_reg:x6; val_offset:1720*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1720*FLEN/8, x9, x1, x2) + +inst_885: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x8407; + valaddr_reg:x6; val_offset:1722*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1722*FLEN/8, x9, x1, x2) + +inst_886: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8407; op2val:0xbc00; + valaddr_reg:x6; val_offset:1724*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1724*FLEN/8, x9, x1, x2) + +inst_887: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x87fc; + valaddr_reg:x6; val_offset:1726*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1726*FLEN/8, x9, x1, x2) + +inst_888: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x87fc; op2val:0xbc00; + valaddr_reg:x6; val_offset:1728*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1728*FLEN/8, x9, x1, x2) + +inst_889: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x8403; + valaddr_reg:x6; val_offset:1730*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1730*FLEN/8, x9, x1, x2) + +inst_890: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8403; op2val:0xbc00; + valaddr_reg:x6; val_offset:1732*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1732*FLEN/8, x9, x1, x2) + +inst_891: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x87fe; + valaddr_reg:x6; val_offset:1734*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1734*FLEN/8, x9, x1, x2) + +inst_892: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x87fe; op2val:0xbc00; + valaddr_reg:x6; val_offset:1736*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1736*FLEN/8, x9, x1, x2) + +inst_893: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x8401; + valaddr_reg:x6; val_offset:1738*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1738*FLEN/8, x9, x1, x2) + +inst_894: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8401; op2val:0xbc00; + valaddr_reg:x6; val_offset:1740*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1740*FLEN/8, x9, x1, x2) + +inst_895: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbffe; + valaddr_reg:x6; val_offset:1742*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1742*FLEN/8, x9, x1, x2) + +inst_896: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbffe; op2val:0xbc00; + valaddr_reg:x6; val_offset:1744*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1744*FLEN/8, x9, x1, x2) + +inst_897: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbc01; + valaddr_reg:x6; val_offset:1746*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1746*FLEN/8, x9, x1, x2) + +inst_898: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc01; op2val:0xbc00; + valaddr_reg:x6; val_offset:1748*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1748*FLEN/8, x9, x1, x2) + +inst_899: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1b6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbdb6; + valaddr_reg:x6; val_offset:1750*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1750*FLEN/8, x9, x1, x2) + +inst_900: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x1b6 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbdb6; op2val:0xbc00; + valaddr_reg:x6; val_offset:1752*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1752*FLEN/8, x9, x1, x2) + +inst_901: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x36d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbf6d; + valaddr_reg:x6; val_offset:1754*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1754*FLEN/8, x9, x1, x2) + +inst_902: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x36d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbf6d; op2val:0xbc00; + valaddr_reg:x6; val_offset:1756*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1756*FLEN/8, x9, x1, x2) + +inst_903: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0cc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbccc; + valaddr_reg:x6; val_offset:1758*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1758*FLEN/8, x9, x1, x2) + +inst_904: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x0cc and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbccc; op2val:0xbc00; + valaddr_reg:x6; val_offset:1760*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1760*FLEN/8, x9, x1, x2) + +inst_905: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x333 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbf33; + valaddr_reg:x6; val_offset:1762*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1762*FLEN/8, x9, x1, x2) + +inst_906: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x333 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbf33; op2val:0xbc00; + valaddr_reg:x6; val_offset:1764*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1764*FLEN/8, x9, x1, x2) + +inst_907: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1dd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbddd; + valaddr_reg:x6; val_offset:1766*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1766*FLEN/8, x9, x1, x2) + +inst_908: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x1dd and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbddd; op2val:0xbc00; + valaddr_reg:x6; val_offset:1768*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1768*FLEN/8, x9, x1, x2) + +inst_909: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x222 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbe22; + valaddr_reg:x6; val_offset:1770*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1770*FLEN/8, x9, x1, x2) + +inst_910: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x222 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbe22; op2val:0xbc00; + valaddr_reg:x6; val_offset:1772*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1772*FLEN/8, x9, x1, x2) + +inst_911: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x124 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbd24; + valaddr_reg:x6; val_offset:1774*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1774*FLEN/8, x9, x1, x2) + +inst_912: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x124 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbd24; op2val:0xbc00; + valaddr_reg:x6; val_offset:1776*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1776*FLEN/8, x9, x1, x2) + +inst_913: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2db and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbedb; + valaddr_reg:x6; val_offset:1778*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1778*FLEN/8, x9, x1, x2) + +inst_914: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x2db and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbedb; op2val:0xbc00; + valaddr_reg:x6; val_offset:1780*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1780*FLEN/8, x9, x1, x2) + +inst_915: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x199 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbd99; + valaddr_reg:x6; val_offset:1782*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1782*FLEN/8, x9, x1, x2) + +inst_916: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x199 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbd99; op2val:0xbc00; + valaddr_reg:x6; val_offset:1784*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1784*FLEN/8, x9, x1, x2) + +inst_917: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x266 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbe66; + valaddr_reg:x6; val_offset:1786*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1786*FLEN/8, x9, x1, x2) + +inst_918: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x266 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbe66; op2val:0xbc00; + valaddr_reg:x6; val_offset:1788*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1788*FLEN/8, x9, x1, x2) + +inst_919: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x4400; + valaddr_reg:x6; val_offset:1790*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1790*FLEN/8, x9, x1, x2) + +inst_920: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4400; op2val:0xbc00; + valaddr_reg:x6; val_offset:1792*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1792*FLEN/8, x9, x1, x2) + +inst_921: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x47ff; + valaddr_reg:x6; val_offset:1794*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1794*FLEN/8, x9, x1, x2) + +inst_922: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x47ff; op2val:0xbc00; + valaddr_reg:x6; val_offset:1796*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1796*FLEN/8, x9, x1, x2) + +inst_923: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x4600; + valaddr_reg:x6; val_offset:1798*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1798*FLEN/8, x9, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_7) + +inst_924: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4600; op2val:0xbc00; + valaddr_reg:x6; val_offset:1800*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1800*FLEN/8, x9, x1, x2) + +inst_925: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x45ff; + valaddr_reg:x6; val_offset:1802*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1802*FLEN/8, x9, x1, x2) + +inst_926: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x45ff; op2val:0xbc00; + valaddr_reg:x6; val_offset:1804*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1804*FLEN/8, x9, x1, x2) + +inst_927: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x4700; + valaddr_reg:x6; val_offset:1806*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1806*FLEN/8, x9, x1, x2) + +inst_928: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x300 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4700; op2val:0xbc00; + valaddr_reg:x6; val_offset:1808*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1808*FLEN/8, x9, x1, x2) + +inst_929: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x44ff; + valaddr_reg:x6; val_offset:1810*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1810*FLEN/8, x9, x1, x2) + +inst_930: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x44ff; op2val:0xbc00; + valaddr_reg:x6; val_offset:1812*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1812*FLEN/8, x9, x1, x2) + +inst_931: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x4780; + valaddr_reg:x6; val_offset:1814*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1814*FLEN/8, x9, x1, x2) + +inst_932: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x380 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4780; op2val:0xbc00; + valaddr_reg:x6; val_offset:1816*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1816*FLEN/8, x9, x1, x2) + +inst_933: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x447f; + valaddr_reg:x6; val_offset:1818*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1818*FLEN/8, x9, x1, x2) + +inst_934: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x07f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x447f; op2val:0xbc00; + valaddr_reg:x6; val_offset:1820*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1820*FLEN/8, x9, x1, x2) + +inst_935: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x47c0; + valaddr_reg:x6; val_offset:1822*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1822*FLEN/8, x9, x1, x2) + +inst_936: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x47c0; op2val:0xbc00; + valaddr_reg:x6; val_offset:1824*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1824*FLEN/8, x9, x1, x2) + +inst_937: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x443f; + valaddr_reg:x6; val_offset:1826*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1826*FLEN/8, x9, x1, x2) + +inst_938: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x443f; op2val:0xbc00; + valaddr_reg:x6; val_offset:1828*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1828*FLEN/8, x9, x1, x2) + +inst_939: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x47e0; + valaddr_reg:x6; val_offset:1830*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1830*FLEN/8, x9, x1, x2) + +inst_940: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x47e0; op2val:0xbc00; + valaddr_reg:x6; val_offset:1832*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1832*FLEN/8, x9, x1, x2) + +inst_941: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x441f; + valaddr_reg:x6; val_offset:1834*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1834*FLEN/8, x9, x1, x2) + +inst_942: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x01f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x441f; op2val:0xbc00; + valaddr_reg:x6; val_offset:1836*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1836*FLEN/8, x9, x1, x2) + +inst_943: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x47f0; + valaddr_reg:x6; val_offset:1838*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1838*FLEN/8, x9, x1, x2) + +inst_944: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x47f0; op2val:0xbc00; + valaddr_reg:x6; val_offset:1840*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1840*FLEN/8, x9, x1, x2) + +inst_945: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x440f; + valaddr_reg:x6; val_offset:1842*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1842*FLEN/8, x9, x1, x2) + +inst_946: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x00f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x440f; op2val:0xbc00; + valaddr_reg:x6; val_offset:1844*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1844*FLEN/8, x9, x1, x2) + +inst_947: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x47f8; + valaddr_reg:x6; val_offset:1846*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1846*FLEN/8, x9, x1, x2) + +inst_948: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x47f8; op2val:0xbc00; + valaddr_reg:x6; val_offset:1848*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1848*FLEN/8, x9, x1, x2) + +inst_949: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x4407; + valaddr_reg:x6; val_offset:1850*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1850*FLEN/8, x9, x1, x2) + +inst_950: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4407; op2val:0xbc00; + valaddr_reg:x6; val_offset:1852*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1852*FLEN/8, x9, x1, x2) + +inst_951: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x47fc; + valaddr_reg:x6; val_offset:1854*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1854*FLEN/8, x9, x1, x2) + +inst_952: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x47fc; op2val:0xbc00; + valaddr_reg:x6; val_offset:1856*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1856*FLEN/8, x9, x1, x2) + +inst_953: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x4403; + valaddr_reg:x6; val_offset:1858*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1858*FLEN/8, x9, x1, x2) + +inst_954: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4403; op2val:0xbc00; + valaddr_reg:x6; val_offset:1860*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1860*FLEN/8, x9, x1, x2) + +inst_955: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x47fe; + valaddr_reg:x6; val_offset:1862*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1862*FLEN/8, x9, x1, x2) + +inst_956: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x47fe; op2val:0xbc00; + valaddr_reg:x6; val_offset:1864*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1864*FLEN/8, x9, x1, x2) + +inst_957: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0x4401; + valaddr_reg:x6; val_offset:1866*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1866*FLEN/8, x9, x1, x2) + +inst_958: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4401; op2val:0xbc00; + valaddr_reg:x6; val_offset:1868*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1868*FLEN/8, x9, x1, x2) + +inst_959: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xac00; + valaddr_reg:x6; val_offset:1870*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1870*FLEN/8, x9, x1, x2) + +inst_960: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xac00; op2val:0xbc00; + valaddr_reg:x6; val_offset:1872*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1872*FLEN/8, x9, x1, x2) + +inst_961: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xafff; + valaddr_reg:x6; val_offset:1874*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1874*FLEN/8, x9, x1, x2) + +inst_962: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xafff; op2val:0xbc00; + valaddr_reg:x6; val_offset:1876*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1876*FLEN/8, x9, x1, x2) + +inst_963: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xae00; + valaddr_reg:x6; val_offset:1878*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1878*FLEN/8, x9, x1, x2) + +inst_964: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xae00; op2val:0xbc00; + valaddr_reg:x6; val_offset:1880*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1880*FLEN/8, x9, x1, x2) + +inst_965: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xadff; + valaddr_reg:x6; val_offset:1882*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1882*FLEN/8, x9, x1, x2) + +inst_966: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xadff; op2val:0xbc00; + valaddr_reg:x6; val_offset:1884*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1884*FLEN/8, x9, x1, x2) + +inst_967: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xaf00; + valaddr_reg:x6; val_offset:1886*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1886*FLEN/8, x9, x1, x2) + +inst_968: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x300 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xaf00; op2val:0xbc00; + valaddr_reg:x6; val_offset:1888*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1888*FLEN/8, x9, x1, x2) + +inst_969: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xacff; + valaddr_reg:x6; val_offset:1890*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1890*FLEN/8, x9, x1, x2) + +inst_970: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xacff; op2val:0xbc00; + valaddr_reg:x6; val_offset:1892*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1892*FLEN/8, x9, x1, x2) + +inst_971: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xaf80; + valaddr_reg:x6; val_offset:1894*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1894*FLEN/8, x9, x1, x2) + +inst_972: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x380 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xaf80; op2val:0xbc00; + valaddr_reg:x6; val_offset:1896*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1896*FLEN/8, x9, x1, x2) + +inst_973: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xac7f; + valaddr_reg:x6; val_offset:1898*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1898*FLEN/8, x9, x1, x2) + +inst_974: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x07f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xac7f; op2val:0xbc00; + valaddr_reg:x6; val_offset:1900*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1900*FLEN/8, x9, x1, x2) + +inst_975: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xafc0; + valaddr_reg:x6; val_offset:1902*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1902*FLEN/8, x9, x1, x2) + +inst_976: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xafc0; op2val:0xbc00; + valaddr_reg:x6; val_offset:1904*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1904*FLEN/8, x9, x1, x2) + +inst_977: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xac3f; + valaddr_reg:x6; val_offset:1906*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1906*FLEN/8, x9, x1, x2) + +inst_978: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x03f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xac3f; op2val:0xbc00; + valaddr_reg:x6; val_offset:1908*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1908*FLEN/8, x9, x1, x2) + +inst_979: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xafe0; + valaddr_reg:x6; val_offset:1910*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1910*FLEN/8, x9, x1, x2) + +inst_980: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xafe0; op2val:0xbc00; + valaddr_reg:x6; val_offset:1912*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1912*FLEN/8, x9, x1, x2) + +inst_981: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xac1f; + valaddr_reg:x6; val_offset:1914*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1914*FLEN/8, x9, x1, x2) + +inst_982: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x01f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xac1f; op2val:0xbc00; + valaddr_reg:x6; val_offset:1916*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1916*FLEN/8, x9, x1, x2) + +inst_983: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xaff0; + valaddr_reg:x6; val_offset:1918*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1918*FLEN/8, x9, x1, x2) + +inst_984: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xaff0; op2val:0xbc00; + valaddr_reg:x6; val_offset:1920*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1920*FLEN/8, x9, x1, x2) + +inst_985: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xac0f; + valaddr_reg:x6; val_offset:1922*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1922*FLEN/8, x9, x1, x2) + +inst_986: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x00f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xac0f; op2val:0xbc00; + valaddr_reg:x6; val_offset:1924*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1924*FLEN/8, x9, x1, x2) + +inst_987: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xaff8; + valaddr_reg:x6; val_offset:1926*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1926*FLEN/8, x9, x1, x2) + +inst_988: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xaff8; op2val:0xbc00; + valaddr_reg:x6; val_offset:1928*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1928*FLEN/8, x9, x1, x2) + +inst_989: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xac07; + valaddr_reg:x6; val_offset:1930*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1930*FLEN/8, x9, x1, x2) + +inst_990: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x007 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xac07; op2val:0xbc00; + valaddr_reg:x6; val_offset:1932*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1932*FLEN/8, x9, x1, x2) + +inst_991: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xaffc; + valaddr_reg:x6; val_offset:1934*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1934*FLEN/8, x9, x1, x2) + +inst_992: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xaffc; op2val:0xbc00; + valaddr_reg:x6; val_offset:1936*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1936*FLEN/8, x9, x1, x2) + +inst_993: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xac03; + valaddr_reg:x6; val_offset:1938*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1938*FLEN/8, x9, x1, x2) + +inst_994: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x003 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xac03; op2val:0xbc00; + valaddr_reg:x6; val_offset:1940*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1940*FLEN/8, x9, x1, x2) + +inst_995: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xaffe; + valaddr_reg:x6; val_offset:1942*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1942*FLEN/8, x9, x1, x2) + +inst_996: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xaffe; op2val:0xbc00; + valaddr_reg:x6; val_offset:1944*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1944*FLEN/8, x9, x1, x2) + +inst_997: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xac01; + valaddr_reg:x6; val_offset:1946*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1946*FLEN/8, x9, x1, x2) + +inst_998: +// fs1 == 1 and fe1 == 0x0b and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xac01; op2val:0xbc00; + valaddr_reg:x6; val_offset:1948*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1948*FLEN/8, x9, x1, x2) + +inst_999: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb000; + valaddr_reg:x6; val_offset:1950*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1950*FLEN/8, x9, x1, x2) + +inst_1000: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xb000; op2val:0xbc00; + valaddr_reg:x6; val_offset:1952*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1952*FLEN/8, x9, x1, x2) + +inst_1001: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb3ff; + valaddr_reg:x6; val_offset:1954*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1954*FLEN/8, x9, x1, x2) + +inst_1002: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xb3ff; op2val:0xbc00; + valaddr_reg:x6; val_offset:1956*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1956*FLEN/8, x9, x1, x2) + +inst_1003: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb200; + valaddr_reg:x6; val_offset:1958*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1958*FLEN/8, x9, x1, x2) + +inst_1004: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xb200; op2val:0xbc00; + valaddr_reg:x6; val_offset:1960*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1960*FLEN/8, x9, x1, x2) + +inst_1005: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb1ff; + valaddr_reg:x6; val_offset:1962*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1962*FLEN/8, x9, x1, x2) + +inst_1006: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xb1ff; op2val:0xbc00; + valaddr_reg:x6; val_offset:1964*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1964*FLEN/8, x9, x1, x2) + +inst_1007: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb300; + valaddr_reg:x6; val_offset:1966*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1966*FLEN/8, x9, x1, x2) + +inst_1008: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x300 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xb300; op2val:0xbc00; + valaddr_reg:x6; val_offset:1968*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1968*FLEN/8, x9, x1, x2) + +inst_1009: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb0ff; + valaddr_reg:x6; val_offset:1970*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1970*FLEN/8, x9, x1, x2) + +inst_1010: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xb0ff; op2val:0xbc00; + valaddr_reg:x6; val_offset:1972*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1972*FLEN/8, x9, x1, x2) + +inst_1011: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb380; + valaddr_reg:x6; val_offset:1974*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1974*FLEN/8, x9, x1, x2) + +inst_1012: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x380 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xb380; op2val:0xbc00; + valaddr_reg:x6; val_offset:1976*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1976*FLEN/8, x9, x1, x2) + +inst_1013: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb07f; + valaddr_reg:x6; val_offset:1978*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1978*FLEN/8, x9, x1, x2) + +inst_1014: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x07f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xb07f; op2val:0xbc00; + valaddr_reg:x6; val_offset:1980*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1980*FLEN/8, x9, x1, x2) + +inst_1015: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb3c0; + valaddr_reg:x6; val_offset:1982*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1982*FLEN/8, x9, x1, x2) + +inst_1016: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xb3c0; op2val:0xbc00; + valaddr_reg:x6; val_offset:1984*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1984*FLEN/8, x9, x1, x2) + +inst_1017: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb03f; + valaddr_reg:x6; val_offset:1986*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1986*FLEN/8, x9, x1, x2) + +inst_1018: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x03f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xb03f; op2val:0xbc00; + valaddr_reg:x6; val_offset:1988*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1988*FLEN/8, x9, x1, x2) + +inst_1019: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb3e0; + valaddr_reg:x6; val_offset:1990*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1990*FLEN/8, x9, x1, x2) + +inst_1020: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xb3e0; op2val:0xbc00; + valaddr_reg:x6; val_offset:1992*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1992*FLEN/8, x9, x1, x2) + +inst_1021: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb01f; + valaddr_reg:x6; val_offset:1994*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1994*FLEN/8, x9, x1, x2) + +inst_1022: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x01f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xb01f; op2val:0xbc00; + valaddr_reg:x6; val_offset:1996*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1996*FLEN/8, x9, x1, x2) + +inst_1023: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb3f0; + valaddr_reg:x6; val_offset:1998*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 1998*FLEN/8, x9, x1, x2) + +inst_1024: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xb3f0; op2val:0xbc00; + valaddr_reg:x6; val_offset:2000*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2000*FLEN/8, x9, x1, x2) + +inst_1025: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb00f; + valaddr_reg:x6; val_offset:2002*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2002*FLEN/8, x9, x1, x2) + +inst_1026: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x00f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xb00f; op2val:0xbc00; + valaddr_reg:x6; val_offset:2004*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2004*FLEN/8, x9, x1, x2) + +inst_1027: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb3f8; + valaddr_reg:x6; val_offset:2006*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2006*FLEN/8, x9, x1, x2) + +inst_1028: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xb3f8; op2val:0xbc00; + valaddr_reg:x6; val_offset:2008*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2008*FLEN/8, x9, x1, x2) + +inst_1029: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb007; + valaddr_reg:x6; val_offset:2010*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2010*FLEN/8, x9, x1, x2) + +inst_1030: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x007 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xb007; op2val:0xbc00; + valaddr_reg:x6; val_offset:2012*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2012*FLEN/8, x9, x1, x2) + +inst_1031: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb3fc; + valaddr_reg:x6; val_offset:2014*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2014*FLEN/8, x9, x1, x2) + +inst_1032: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xb3fc; op2val:0xbc00; + valaddr_reg:x6; val_offset:2016*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2016*FLEN/8, x9, x1, x2) + +inst_1033: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb003; + valaddr_reg:x6; val_offset:2018*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2018*FLEN/8, x9, x1, x2) + +inst_1034: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x003 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xb003; op2val:0xbc00; + valaddr_reg:x6; val_offset:2020*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2020*FLEN/8, x9, x1, x2) + +inst_1035: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb3fe; + valaddr_reg:x6; val_offset:2022*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2022*FLEN/8, x9, x1, x2) + +inst_1036: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xb3fe; op2val:0xbc00; + valaddr_reg:x6; val_offset:2024*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2024*FLEN/8, x9, x1, x2) + +inst_1037: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb001; + valaddr_reg:x6; val_offset:2026*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2026*FLEN/8, x9, x1, x2) + +inst_1038: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xb001; op2val:0xbc00; + valaddr_reg:x6; val_offset:2028*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2028*FLEN/8, x9, x1, x2) + +inst_1039: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb400; + valaddr_reg:x6; val_offset:2030*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2030*FLEN/8, x9, x1, x2) + +inst_1040: +// fs1 == 1 and fe1 == 0x0d and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xb400; op2val:0xbc00; + valaddr_reg:x6; val_offset:2032*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2032*FLEN/8, x9, x1, x2) + +inst_1041: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb7ff; + valaddr_reg:x6; val_offset:2034*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2034*FLEN/8, x9, x1, x2) + +inst_1042: +// fs1 == 1 and fe1 == 0x0d and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xb7ff; op2val:0xbc00; + valaddr_reg:x6; val_offset:2036*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2036*FLEN/8, x9, x1, x2) + +inst_1043: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb600; + valaddr_reg:x6; val_offset:2038*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2038*FLEN/8, x9, x1, x2) + +inst_1044: +// fs1 == 1 and fe1 == 0x0d and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xb600; op2val:0xbc00; + valaddr_reg:x6; val_offset:2040*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2040*FLEN/8, x9, x1, x2) + +inst_1045: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb5ff; + valaddr_reg:x6; val_offset:2042*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2042*FLEN/8, x9, x1, x2) + +inst_1046: +// fs1 == 1 and fe1 == 0x0d and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xb5ff; op2val:0xbc00; + valaddr_reg:x6; val_offset:2044*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2044*FLEN/8, x9, x1, x2) + +inst_1047: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb700; + valaddr_reg:x6; val_offset:2046*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2046*FLEN/8, x9, x1, x2) + +inst_1048: +// fs1 == 1 and fe1 == 0x0d and fm1 == 0x300 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xb700; op2val:0xbc00; + valaddr_reg:x6; val_offset:2048*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2048*FLEN/8, x9, x1, x2) + +inst_1049: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb4ff; + valaddr_reg:x6; val_offset:2050*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2050*FLEN/8, x9, x1, x2) + +inst_1050: +// fs1 == 1 and fe1 == 0x0d and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xb4ff; op2val:0xbc00; + valaddr_reg:x6; val_offset:2052*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2052*FLEN/8, x9, x1, x2) + +inst_1051: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb780; + valaddr_reg:x6; val_offset:2054*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2054*FLEN/8, x9, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_8) + +inst_1052: +// fs1 == 1 and fe1 == 0x0d and fm1 == 0x380 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xb780; op2val:0xbc00; + valaddr_reg:x6; val_offset:2056*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2056*FLEN/8, x9, x1, x2) + +inst_1053: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb47f; + valaddr_reg:x6; val_offset:2058*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2058*FLEN/8, x9, x1, x2) + +inst_1054: +// fs1 == 1 and fe1 == 0x0d and fm1 == 0x07f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xb47f; op2val:0xbc00; + valaddr_reg:x6; val_offset:2060*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2060*FLEN/8, x9, x1, x2) + +inst_1055: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb7c0; + valaddr_reg:x6; val_offset:2062*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2062*FLEN/8, x9, x1, x2) + +inst_1056: +// fs1 == 1 and fe1 == 0x0d and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xb7c0; op2val:0xbc00; + valaddr_reg:x6; val_offset:2064*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2064*FLEN/8, x9, x1, x2) + +inst_1057: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb43f; + valaddr_reg:x6; val_offset:2066*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2066*FLEN/8, x9, x1, x2) + +inst_1058: +// fs1 == 1 and fe1 == 0x0d and fm1 == 0x03f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xb43f; op2val:0xbc00; + valaddr_reg:x6; val_offset:2068*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2068*FLEN/8, x9, x1, x2) + +inst_1059: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb7e0; + valaddr_reg:x6; val_offset:2070*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2070*FLEN/8, x9, x1, x2) + +inst_1060: +// fs1 == 1 and fe1 == 0x0d and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xb7e0; op2val:0xbc00; + valaddr_reg:x6; val_offset:2072*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2072*FLEN/8, x9, x1, x2) + +inst_1061: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb41f; + valaddr_reg:x6; val_offset:2074*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2074*FLEN/8, x9, x1, x2) + +inst_1062: +// fs1 == 1 and fe1 == 0x0d and fm1 == 0x01f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xb41f; op2val:0xbc00; + valaddr_reg:x6; val_offset:2076*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2076*FLEN/8, x9, x1, x2) + +inst_1063: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb7f0; + valaddr_reg:x6; val_offset:2078*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2078*FLEN/8, x9, x1, x2) + +inst_1064: +// fs1 == 1 and fe1 == 0x0d and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xb7f0; op2val:0xbc00; + valaddr_reg:x6; val_offset:2080*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2080*FLEN/8, x9, x1, x2) + +inst_1065: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb40f; + valaddr_reg:x6; val_offset:2082*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2082*FLEN/8, x9, x1, x2) + +inst_1066: +// fs1 == 1 and fe1 == 0x0d and fm1 == 0x00f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xb40f; op2val:0xbc00; + valaddr_reg:x6; val_offset:2084*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2084*FLEN/8, x9, x1, x2) + +inst_1067: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb7f8; + valaddr_reg:x6; val_offset:2086*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2086*FLEN/8, x9, x1, x2) + +inst_1068: +// fs1 == 1 and fe1 == 0x0d and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xb7f8; op2val:0xbc00; + valaddr_reg:x6; val_offset:2088*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2088*FLEN/8, x9, x1, x2) + +inst_1069: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb407; + valaddr_reg:x6; val_offset:2090*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2090*FLEN/8, x9, x1, x2) + +inst_1070: +// fs1 == 1 and fe1 == 0x0d and fm1 == 0x007 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xb407; op2val:0xbc00; + valaddr_reg:x6; val_offset:2092*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2092*FLEN/8, x9, x1, x2) + +inst_1071: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb7fc; + valaddr_reg:x6; val_offset:2094*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2094*FLEN/8, x9, x1, x2) + +inst_1072: +// fs1 == 1 and fe1 == 0x0d and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xb7fc; op2val:0xbc00; + valaddr_reg:x6; val_offset:2096*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2096*FLEN/8, x9, x1, x2) + +inst_1073: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb403; + valaddr_reg:x6; val_offset:2098*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2098*FLEN/8, x9, x1, x2) + +inst_1074: +// fs1 == 1 and fe1 == 0x0d and fm1 == 0x003 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xb403; op2val:0xbc00; + valaddr_reg:x6; val_offset:2100*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2100*FLEN/8, x9, x1, x2) + +inst_1075: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb7fe; + valaddr_reg:x6; val_offset:2102*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2102*FLEN/8, x9, x1, x2) + +inst_1076: +// fs1 == 1 and fe1 == 0x0d and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xb7fe; op2val:0xbc00; + valaddr_reg:x6; val_offset:2104*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2104*FLEN/8, x9, x1, x2) + +inst_1077: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb401; + valaddr_reg:x6; val_offset:2106*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2106*FLEN/8, x9, x1, x2) + +inst_1078: +// fs1 == 1 and fe1 == 0x0d and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xb401; op2val:0xbc00; + valaddr_reg:x6; val_offset:2108*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2108*FLEN/8, x9, x1, x2) + +inst_1079: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb800; + valaddr_reg:x6; val_offset:2110*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2110*FLEN/8, x9, x1, x2) + +inst_1080: +// fs1 == 1 and fe1 == 0x0e and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xb800; op2val:0xbc00; + valaddr_reg:x6; val_offset:2112*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2112*FLEN/8, x9, x1, x2) + +inst_1081: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbbff; + valaddr_reg:x6; val_offset:2114*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2114*FLEN/8, x9, x1, x2) + +inst_1082: +// fs1 == 1 and fe1 == 0x0e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbbff; op2val:0xbc00; + valaddr_reg:x6; val_offset:2116*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2116*FLEN/8, x9, x1, x2) + +inst_1083: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xba00; + valaddr_reg:x6; val_offset:2118*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2118*FLEN/8, x9, x1, x2) + +inst_1084: +// fs1 == 1 and fe1 == 0x0e and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xba00; op2val:0xbc00; + valaddr_reg:x6; val_offset:2120*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2120*FLEN/8, x9, x1, x2) + +inst_1085: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb9ff; + valaddr_reg:x6; val_offset:2122*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2122*FLEN/8, x9, x1, x2) + +inst_1086: +// fs1 == 1 and fe1 == 0x0e and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xb9ff; op2val:0xbc00; + valaddr_reg:x6; val_offset:2124*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2124*FLEN/8, x9, x1, x2) + +inst_1087: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbb00; + valaddr_reg:x6; val_offset:2126*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2126*FLEN/8, x9, x1, x2) + +inst_1088: +// fs1 == 1 and fe1 == 0x0e and fm1 == 0x300 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbb00; op2val:0xbc00; + valaddr_reg:x6; val_offset:2128*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2128*FLEN/8, x9, x1, x2) + +inst_1089: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb8ff; + valaddr_reg:x6; val_offset:2130*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2130*FLEN/8, x9, x1, x2) + +inst_1090: +// fs1 == 1 and fe1 == 0x0e and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xb8ff; op2val:0xbc00; + valaddr_reg:x6; val_offset:2132*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2132*FLEN/8, x9, x1, x2) + +inst_1091: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbb80; + valaddr_reg:x6; val_offset:2134*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2134*FLEN/8, x9, x1, x2) + +inst_1092: +// fs1 == 1 and fe1 == 0x0e and fm1 == 0x380 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbb80; op2val:0xbc00; + valaddr_reg:x6; val_offset:2136*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2136*FLEN/8, x9, x1, x2) + +inst_1093: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb87f; + valaddr_reg:x6; val_offset:2138*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2138*FLEN/8, x9, x1, x2) + +inst_1094: +// fs1 == 1 and fe1 == 0x0e and fm1 == 0x07f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xb87f; op2val:0xbc00; + valaddr_reg:x6; val_offset:2140*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2140*FLEN/8, x9, x1, x2) + +inst_1095: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbbc0; + valaddr_reg:x6; val_offset:2142*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2142*FLEN/8, x9, x1, x2) + +inst_1096: +// fs1 == 1 and fe1 == 0x0e and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbbc0; op2val:0xbc00; + valaddr_reg:x6; val_offset:2144*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2144*FLEN/8, x9, x1, x2) + +inst_1097: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb83f; + valaddr_reg:x6; val_offset:2146*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2146*FLEN/8, x9, x1, x2) + +inst_1098: +// fs1 == 1 and fe1 == 0x0e and fm1 == 0x03f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xb83f; op2val:0xbc00; + valaddr_reg:x6; val_offset:2148*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2148*FLEN/8, x9, x1, x2) + +inst_1099: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbbe0; + valaddr_reg:x6; val_offset:2150*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2150*FLEN/8, x9, x1, x2) + +inst_1100: +// fs1 == 1 and fe1 == 0x0e and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbbe0; op2val:0xbc00; + valaddr_reg:x6; val_offset:2152*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2152*FLEN/8, x9, x1, x2) + +inst_1101: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb81f; + valaddr_reg:x6; val_offset:2154*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2154*FLEN/8, x9, x1, x2) + +inst_1102: +// fs1 == 1 and fe1 == 0x0e and fm1 == 0x01f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xb81f; op2val:0xbc00; + valaddr_reg:x6; val_offset:2156*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2156*FLEN/8, x9, x1, x2) + +inst_1103: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbbf0; + valaddr_reg:x6; val_offset:2158*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2158*FLEN/8, x9, x1, x2) + +inst_1104: +// fs1 == 1 and fe1 == 0x0e and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbbf0; op2val:0xbc00; + valaddr_reg:x6; val_offset:2160*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2160*FLEN/8, x9, x1, x2) + +inst_1105: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb80f; + valaddr_reg:x6; val_offset:2162*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2162*FLEN/8, x9, x1, x2) + +inst_1106: +// fs1 == 1 and fe1 == 0x0e and fm1 == 0x00f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xb80f; op2val:0xbc00; + valaddr_reg:x6; val_offset:2164*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2164*FLEN/8, x9, x1, x2) + +inst_1107: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbbf8; + valaddr_reg:x6; val_offset:2166*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2166*FLEN/8, x9, x1, x2) + +inst_1108: +// fs1 == 1 and fe1 == 0x0e and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbbf8; op2val:0xbc00; + valaddr_reg:x6; val_offset:2168*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2168*FLEN/8, x9, x1, x2) + +inst_1109: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb807; + valaddr_reg:x6; val_offset:2170*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2170*FLEN/8, x9, x1, x2) + +inst_1110: +// fs1 == 1 and fe1 == 0x0e and fm1 == 0x007 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xb807; op2val:0xbc00; + valaddr_reg:x6; val_offset:2172*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2172*FLEN/8, x9, x1, x2) + +inst_1111: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbbfc; + valaddr_reg:x6; val_offset:2174*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2174*FLEN/8, x9, x1, x2) + +inst_1112: +// fs1 == 1 and fe1 == 0x0e and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbbfc; op2val:0xbc00; + valaddr_reg:x6; val_offset:2176*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2176*FLEN/8, x9, x1, x2) + +inst_1113: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb803; + valaddr_reg:x6; val_offset:2178*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2178*FLEN/8, x9, x1, x2) + +inst_1114: +// fs1 == 1 and fe1 == 0x0e and fm1 == 0x003 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xb803; op2val:0xbc00; + valaddr_reg:x6; val_offset:2180*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2180*FLEN/8, x9, x1, x2) + +inst_1115: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbbfe; + valaddr_reg:x6; val_offset:2182*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2182*FLEN/8, x9, x1, x2) + +inst_1116: +// fs1 == 1 and fe1 == 0x0e and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbbfe; op2val:0xbc00; + valaddr_reg:x6; val_offset:2184*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2184*FLEN/8, x9, x1, x2) + +inst_1117: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xb801; + valaddr_reg:x6; val_offset:2186*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2186*FLEN/8, x9, x1, x2) + +inst_1118: +// fs1 == 1 and fe1 == 0x0e and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xb801; op2val:0xbc00; + valaddr_reg:x6; val_offset:2188*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2188*FLEN/8, x9, x1, x2) + +inst_1119: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbc00; + valaddr_reg:x6; val_offset:2190*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2190*FLEN/8, x9, x1, x2) + +inst_1120: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbfff; + valaddr_reg:x6; val_offset:2192*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2192*FLEN/8, x9, x1, x2) + +inst_1121: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbfff; op2val:0xbc00; + valaddr_reg:x6; val_offset:2194*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2194*FLEN/8, x9, x1, x2) + +inst_1122: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbe00; + valaddr_reg:x6; val_offset:2196*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2196*FLEN/8, x9, x1, x2) + +inst_1123: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbe00; op2val:0xbc00; + valaddr_reg:x6; val_offset:2198*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2198*FLEN/8, x9, x1, x2) + +inst_1124: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbdff; + valaddr_reg:x6; val_offset:2200*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2200*FLEN/8, x9, x1, x2) + +inst_1125: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbdff; op2val:0xbc00; + valaddr_reg:x6; val_offset:2202*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2202*FLEN/8, x9, x1, x2) + +inst_1126: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbf00; + valaddr_reg:x6; val_offset:2204*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2204*FLEN/8, x9, x1, x2) + +inst_1127: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x300 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbf00; op2val:0xbc00; + valaddr_reg:x6; val_offset:2206*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2206*FLEN/8, x9, x1, x2) + +inst_1128: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbcff; + valaddr_reg:x6; val_offset:2208*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2208*FLEN/8, x9, x1, x2) + +inst_1129: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbcff; op2val:0xbc00; + valaddr_reg:x6; val_offset:2210*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2210*FLEN/8, x9, x1, x2) + +inst_1130: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbf80; + valaddr_reg:x6; val_offset:2212*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2212*FLEN/8, x9, x1, x2) + +inst_1131: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x380 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbf80; op2val:0xbc00; + valaddr_reg:x6; val_offset:2214*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2214*FLEN/8, x9, x1, x2) + +inst_1132: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbc7f; + valaddr_reg:x6; val_offset:2216*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2216*FLEN/8, x9, x1, x2) + +inst_1133: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x07f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc7f; op2val:0xbc00; + valaddr_reg:x6; val_offset:2218*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2218*FLEN/8, x9, x1, x2) + +inst_1134: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbfc0; + valaddr_reg:x6; val_offset:2220*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2220*FLEN/8, x9, x1, x2) + +inst_1135: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbfc0; op2val:0xbc00; + valaddr_reg:x6; val_offset:2222*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2222*FLEN/8, x9, x1, x2) + +inst_1136: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbc3f; + valaddr_reg:x6; val_offset:2224*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2224*FLEN/8, x9, x1, x2) + +inst_1137: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x03f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc3f; op2val:0xbc00; + valaddr_reg:x6; val_offset:2226*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2226*FLEN/8, x9, x1, x2) + +inst_1138: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbfe0; + valaddr_reg:x6; val_offset:2228*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2228*FLEN/8, x9, x1, x2) + +inst_1139: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbfe0; op2val:0xbc00; + valaddr_reg:x6; val_offset:2230*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2230*FLEN/8, x9, x1, x2) + +inst_1140: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbc1f; + valaddr_reg:x6; val_offset:2232*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2232*FLEN/8, x9, x1, x2) + +inst_1141: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x01f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc1f; op2val:0xbc00; + valaddr_reg:x6; val_offset:2234*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2234*FLEN/8, x9, x1, x2) + +inst_1142: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbff0; + valaddr_reg:x6; val_offset:2236*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2236*FLEN/8, x9, x1, x2) + +inst_1143: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbff0; op2val:0xbc00; + valaddr_reg:x6; val_offset:2238*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2238*FLEN/8, x9, x1, x2) + +inst_1144: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbc0f; + valaddr_reg:x6; val_offset:2240*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2240*FLEN/8, x9, x1, x2) + +inst_1145: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x00f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc0f; op2val:0xbc00; + valaddr_reg:x6; val_offset:2242*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2242*FLEN/8, x9, x1, x2) + +inst_1146: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbff8; + valaddr_reg:x6; val_offset:2244*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2244*FLEN/8, x9, x1, x2) + +inst_1147: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbff8; op2val:0xbc00; + valaddr_reg:x6; val_offset:2246*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2246*FLEN/8, x9, x1, x2) + +inst_1148: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbc07; + valaddr_reg:x6; val_offset:2248*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2248*FLEN/8, x9, x1, x2) + +inst_1149: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x007 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc07; op2val:0xbc00; + valaddr_reg:x6; val_offset:2250*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2250*FLEN/8, x9, x1, x2) + +inst_1150: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbffc; + valaddr_reg:x6; val_offset:2252*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2252*FLEN/8, x9, x1, x2) + +inst_1151: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbffc; op2val:0xbc00; + valaddr_reg:x6; val_offset:2254*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2254*FLEN/8, x9, x1, x2) + +inst_1152: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xbc03; + valaddr_reg:x6; val_offset:2256*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2256*FLEN/8, x9, x1, x2) + +inst_1153: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x003 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc03; op2val:0xbc00; + valaddr_reg:x6; val_offset:2258*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2258*FLEN/8, x9, x1, x2) + +inst_1154: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc000; + valaddr_reg:x6; val_offset:2260*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2260*FLEN/8, x9, x1, x2) + +inst_1155: +// fs1 == 1 and fe1 == 0x10 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc000; op2val:0xbc00; + valaddr_reg:x6; val_offset:2262*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2262*FLEN/8, x9, x1, x2) + +inst_1156: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc3ff; + valaddr_reg:x6; val_offset:2264*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2264*FLEN/8, x9, x1, x2) + +inst_1157: +// fs1 == 1 and fe1 == 0x10 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc3ff; op2val:0xbc00; + valaddr_reg:x6; val_offset:2266*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2266*FLEN/8, x9, x1, x2) + +inst_1158: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc200; + valaddr_reg:x6; val_offset:2268*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2268*FLEN/8, x9, x1, x2) + +inst_1159: +// fs1 == 1 and fe1 == 0x10 and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc200; op2val:0xbc00; + valaddr_reg:x6; val_offset:2270*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2270*FLEN/8, x9, x1, x2) + +inst_1160: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc1ff; + valaddr_reg:x6; val_offset:2272*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2272*FLEN/8, x9, x1, x2) + +inst_1161: +// fs1 == 1 and fe1 == 0x10 and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc1ff; op2val:0xbc00; + valaddr_reg:x6; val_offset:2274*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2274*FLEN/8, x9, x1, x2) + +inst_1162: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc300; + valaddr_reg:x6; val_offset:2276*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2276*FLEN/8, x9, x1, x2) + +inst_1163: +// fs1 == 1 and fe1 == 0x10 and fm1 == 0x300 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc300; op2val:0xbc00; + valaddr_reg:x6; val_offset:2278*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2278*FLEN/8, x9, x1, x2) + +inst_1164: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc0ff; + valaddr_reg:x6; val_offset:2280*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2280*FLEN/8, x9, x1, x2) + +inst_1165: +// fs1 == 1 and fe1 == 0x10 and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc0ff; op2val:0xbc00; + valaddr_reg:x6; val_offset:2282*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2282*FLEN/8, x9, x1, x2) + +inst_1166: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc380; + valaddr_reg:x6; val_offset:2284*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2284*FLEN/8, x9, x1, x2) + +inst_1167: +// fs1 == 1 and fe1 == 0x10 and fm1 == 0x380 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc380; op2val:0xbc00; + valaddr_reg:x6; val_offset:2286*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2286*FLEN/8, x9, x1, x2) + +inst_1168: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc07f; + valaddr_reg:x6; val_offset:2288*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2288*FLEN/8, x9, x1, x2) + +inst_1169: +// fs1 == 1 and fe1 == 0x10 and fm1 == 0x07f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc07f; op2val:0xbc00; + valaddr_reg:x6; val_offset:2290*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2290*FLEN/8, x9, x1, x2) + +inst_1170: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc3c0; + valaddr_reg:x6; val_offset:2292*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2292*FLEN/8, x9, x1, x2) + +inst_1171: +// fs1 == 1 and fe1 == 0x10 and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc3c0; op2val:0xbc00; + valaddr_reg:x6; val_offset:2294*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2294*FLEN/8, x9, x1, x2) + +inst_1172: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc03f; + valaddr_reg:x6; val_offset:2296*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2296*FLEN/8, x9, x1, x2) + +inst_1173: +// fs1 == 1 and fe1 == 0x10 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc03f; op2val:0xbc00; + valaddr_reg:x6; val_offset:2298*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2298*FLEN/8, x9, x1, x2) + +inst_1174: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc3e0; + valaddr_reg:x6; val_offset:2300*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2300*FLEN/8, x9, x1, x2) + +inst_1175: +// fs1 == 1 and fe1 == 0x10 and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc3e0; op2val:0xbc00; + valaddr_reg:x6; val_offset:2302*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2302*FLEN/8, x9, x1, x2) + +inst_1176: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc01f; + valaddr_reg:x6; val_offset:2304*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2304*FLEN/8, x9, x1, x2) + +inst_1177: +// fs1 == 1 and fe1 == 0x10 and fm1 == 0x01f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc01f; op2val:0xbc00; + valaddr_reg:x6; val_offset:2306*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2306*FLEN/8, x9, x1, x2) + +inst_1178: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc3f0; + valaddr_reg:x6; val_offset:2308*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2308*FLEN/8, x9, x1, x2) + +inst_1179: +// fs1 == 1 and fe1 == 0x10 and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc3f0; op2val:0xbc00; + valaddr_reg:x6; val_offset:2310*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2310*FLEN/8, x9, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_9) + +inst_1180: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc00f; + valaddr_reg:x6; val_offset:2312*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2312*FLEN/8, x9, x1, x2) + +inst_1181: +// fs1 == 1 and fe1 == 0x10 and fm1 == 0x00f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc00f; op2val:0xbc00; + valaddr_reg:x6; val_offset:2314*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2314*FLEN/8, x9, x1, x2) + +inst_1182: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc3f8; + valaddr_reg:x6; val_offset:2316*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2316*FLEN/8, x9, x1, x2) + +inst_1183: +// fs1 == 1 and fe1 == 0x10 and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc3f8; op2val:0xbc00; + valaddr_reg:x6; val_offset:2318*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2318*FLEN/8, x9, x1, x2) + +inst_1184: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc007; + valaddr_reg:x6; val_offset:2320*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2320*FLEN/8, x9, x1, x2) + +inst_1185: +// fs1 == 1 and fe1 == 0x10 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc007; op2val:0xbc00; + valaddr_reg:x6; val_offset:2322*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2322*FLEN/8, x9, x1, x2) + +inst_1186: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc3fc; + valaddr_reg:x6; val_offset:2324*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2324*FLEN/8, x9, x1, x2) + +inst_1187: +// fs1 == 1 and fe1 == 0x10 and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc3fc; op2val:0xbc00; + valaddr_reg:x6; val_offset:2326*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2326*FLEN/8, x9, x1, x2) + +inst_1188: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc003; + valaddr_reg:x6; val_offset:2328*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2328*FLEN/8, x9, x1, x2) + +inst_1189: +// fs1 == 1 and fe1 == 0x10 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc003; op2val:0xbc00; + valaddr_reg:x6; val_offset:2330*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2330*FLEN/8, x9, x1, x2) + +inst_1190: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc3fe; + valaddr_reg:x6; val_offset:2332*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2332*FLEN/8, x9, x1, x2) + +inst_1191: +// fs1 == 1 and fe1 == 0x10 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc3fe; op2val:0xbc00; + valaddr_reg:x6; val_offset:2334*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2334*FLEN/8, x9, x1, x2) + +inst_1192: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc001; + valaddr_reg:x6; val_offset:2336*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2336*FLEN/8, x9, x1, x2) + +inst_1193: +// fs1 == 1 and fe1 == 0x10 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc001; op2val:0xbc00; + valaddr_reg:x6; val_offset:2338*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2338*FLEN/8, x9, x1, x2) + +inst_1194: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc400; + valaddr_reg:x6; val_offset:2340*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2340*FLEN/8, x9, x1, x2) + +inst_1195: +// fs1 == 1 and fe1 == 0x11 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc400; op2val:0xbc00; + valaddr_reg:x6; val_offset:2342*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2342*FLEN/8, x9, x1, x2) + +inst_1196: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc7ff; + valaddr_reg:x6; val_offset:2344*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2344*FLEN/8, x9, x1, x2) + +inst_1197: +// fs1 == 1 and fe1 == 0x11 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc7ff; op2val:0xbc00; + valaddr_reg:x6; val_offset:2346*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2346*FLEN/8, x9, x1, x2) + +inst_1198: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc600; + valaddr_reg:x6; val_offset:2348*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2348*FLEN/8, x9, x1, x2) + +inst_1199: +// fs1 == 1 and fe1 == 0x11 and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc600; op2val:0xbc00; + valaddr_reg:x6; val_offset:2350*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2350*FLEN/8, x9, x1, x2) + +inst_1200: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc5ff; + valaddr_reg:x6; val_offset:2352*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2352*FLEN/8, x9, x1, x2) + +inst_1201: +// fs1 == 1 and fe1 == 0x11 and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc5ff; op2val:0xbc00; + valaddr_reg:x6; val_offset:2354*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2354*FLEN/8, x9, x1, x2) + +inst_1202: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc700; + valaddr_reg:x6; val_offset:2356*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2356*FLEN/8, x9, x1, x2) + +inst_1203: +// fs1 == 1 and fe1 == 0x11 and fm1 == 0x300 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc700; op2val:0xbc00; + valaddr_reg:x6; val_offset:2358*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2358*FLEN/8, x9, x1, x2) + +inst_1204: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc4ff; + valaddr_reg:x6; val_offset:2360*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2360*FLEN/8, x9, x1, x2) + +inst_1205: +// fs1 == 1 and fe1 == 0x11 and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc4ff; op2val:0xbc00; + valaddr_reg:x6; val_offset:2362*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2362*FLEN/8, x9, x1, x2) + +inst_1206: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc780; + valaddr_reg:x6; val_offset:2364*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2364*FLEN/8, x9, x1, x2) + +inst_1207: +// fs1 == 1 and fe1 == 0x11 and fm1 == 0x380 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc780; op2val:0xbc00; + valaddr_reg:x6; val_offset:2366*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2366*FLEN/8, x9, x1, x2) + +inst_1208: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc47f; + valaddr_reg:x6; val_offset:2368*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2368*FLEN/8, x9, x1, x2) + +inst_1209: +// fs1 == 1 and fe1 == 0x11 and fm1 == 0x07f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc47f; op2val:0xbc00; + valaddr_reg:x6; val_offset:2370*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2370*FLEN/8, x9, x1, x2) + +inst_1210: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc7c0; + valaddr_reg:x6; val_offset:2372*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2372*FLEN/8, x9, x1, x2) + +inst_1211: +// fs1 == 1 and fe1 == 0x11 and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc7c0; op2val:0xbc00; + valaddr_reg:x6; val_offset:2374*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2374*FLEN/8, x9, x1, x2) + +inst_1212: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc43f; + valaddr_reg:x6; val_offset:2376*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2376*FLEN/8, x9, x1, x2) + +inst_1213: +// fs1 == 1 and fe1 == 0x11 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc43f; op2val:0xbc00; + valaddr_reg:x6; val_offset:2378*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2378*FLEN/8, x9, x1, x2) + +inst_1214: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc7e0; + valaddr_reg:x6; val_offset:2380*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2380*FLEN/8, x9, x1, x2) + +inst_1215: +// fs1 == 1 and fe1 == 0x11 and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc7e0; op2val:0xbc00; + valaddr_reg:x6; val_offset:2382*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2382*FLEN/8, x9, x1, x2) + +inst_1216: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc41f; + valaddr_reg:x6; val_offset:2384*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2384*FLEN/8, x9, x1, x2) + +inst_1217: +// fs1 == 1 and fe1 == 0x11 and fm1 == 0x01f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc41f; op2val:0xbc00; + valaddr_reg:x6; val_offset:2386*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2386*FLEN/8, x9, x1, x2) + +inst_1218: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc7f0; + valaddr_reg:x6; val_offset:2388*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2388*FLEN/8, x9, x1, x2) + +inst_1219: +// fs1 == 1 and fe1 == 0x11 and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc7f0; op2val:0xbc00; + valaddr_reg:x6; val_offset:2390*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2390*FLEN/8, x9, x1, x2) + +inst_1220: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc40f; + valaddr_reg:x6; val_offset:2392*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2392*FLEN/8, x9, x1, x2) + +inst_1221: +// fs1 == 1 and fe1 == 0x11 and fm1 == 0x00f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc40f; op2val:0xbc00; + valaddr_reg:x6; val_offset:2394*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2394*FLEN/8, x9, x1, x2) + +inst_1222: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc7f8; + valaddr_reg:x6; val_offset:2396*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2396*FLEN/8, x9, x1, x2) + +inst_1223: +// fs1 == 1 and fe1 == 0x11 and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc7f8; op2val:0xbc00; + valaddr_reg:x6; val_offset:2398*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2398*FLEN/8, x9, x1, x2) + +inst_1224: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc407; + valaddr_reg:x6; val_offset:2400*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2400*FLEN/8, x9, x1, x2) + +inst_1225: +// fs1 == 1 and fe1 == 0x11 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc407; op2val:0xbc00; + valaddr_reg:x6; val_offset:2402*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2402*FLEN/8, x9, x1, x2) + +inst_1226: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc7fc; + valaddr_reg:x6; val_offset:2404*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2404*FLEN/8, x9, x1, x2) + +inst_1227: +// fs1 == 1 and fe1 == 0x11 and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc7fc; op2val:0xbc00; + valaddr_reg:x6; val_offset:2406*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2406*FLEN/8, x9, x1, x2) + +inst_1228: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc403; + valaddr_reg:x6; val_offset:2408*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2408*FLEN/8, x9, x1, x2) + +inst_1229: +// fs1 == 1 and fe1 == 0x11 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc403; op2val:0xbc00; + valaddr_reg:x6; val_offset:2410*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2410*FLEN/8, x9, x1, x2) + +inst_1230: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc7fe; + valaddr_reg:x6; val_offset:2412*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2412*FLEN/8, x9, x1, x2) + +inst_1231: +// fs1 == 1 and fe1 == 0x11 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc7fe; op2val:0xbc00; + valaddr_reg:x6; val_offset:2414*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2414*FLEN/8, x9, x1, x2) + +inst_1232: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc401; + valaddr_reg:x6; val_offset:2416*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2416*FLEN/8, x9, x1, x2) + +inst_1233: +// fs1 == 1 and fe1 == 0x11 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc401; op2val:0xbc00; + valaddr_reg:x6; val_offset:2418*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2418*FLEN/8, x9, x1, x2) + +inst_1234: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc800; + valaddr_reg:x6; val_offset:2420*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2420*FLEN/8, x9, x1, x2) + +inst_1235: +// fs1 == 1 and fe1 == 0x12 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc800; op2val:0xbc00; + valaddr_reg:x6; val_offset:2422*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2422*FLEN/8, x9, x1, x2) + +inst_1236: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xcbff; + valaddr_reg:x6; val_offset:2424*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2424*FLEN/8, x9, x1, x2) + +inst_1237: +// fs1 == 1 and fe1 == 0x12 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xcbff; op2val:0xbc00; + valaddr_reg:x6; val_offset:2426*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2426*FLEN/8, x9, x1, x2) + +inst_1238: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xca00; + valaddr_reg:x6; val_offset:2428*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2428*FLEN/8, x9, x1, x2) + +inst_1239: +// fs1 == 1 and fe1 == 0x12 and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xca00; op2val:0xbc00; + valaddr_reg:x6; val_offset:2430*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2430*FLEN/8, x9, x1, x2) + +inst_1240: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc9ff; + valaddr_reg:x6; val_offset:2432*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2432*FLEN/8, x9, x1, x2) + +inst_1241: +// fs1 == 1 and fe1 == 0x12 and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc9ff; op2val:0xbc00; + valaddr_reg:x6; val_offset:2434*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2434*FLEN/8, x9, x1, x2) + +inst_1242: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xcb00; + valaddr_reg:x6; val_offset:2436*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2436*FLEN/8, x9, x1, x2) + +inst_1243: +// fs1 == 1 and fe1 == 0x12 and fm1 == 0x300 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xcb00; op2val:0xbc00; + valaddr_reg:x6; val_offset:2438*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2438*FLEN/8, x9, x1, x2) + +inst_1244: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc8ff; + valaddr_reg:x6; val_offset:2440*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2440*FLEN/8, x9, x1, x2) + +inst_1245: +// fs1 == 1 and fe1 == 0x12 and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc8ff; op2val:0xbc00; + valaddr_reg:x6; val_offset:2442*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2442*FLEN/8, x9, x1, x2) + +inst_1246: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xcb80; + valaddr_reg:x6; val_offset:2444*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2444*FLEN/8, x9, x1, x2) + +inst_1247: +// fs1 == 1 and fe1 == 0x12 and fm1 == 0x380 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xcb80; op2val:0xbc00; + valaddr_reg:x6; val_offset:2446*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2446*FLEN/8, x9, x1, x2) + +inst_1248: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc87f; + valaddr_reg:x6; val_offset:2448*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2448*FLEN/8, x9, x1, x2) + +inst_1249: +// fs1 == 1 and fe1 == 0x12 and fm1 == 0x07f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc87f; op2val:0xbc00; + valaddr_reg:x6; val_offset:2450*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2450*FLEN/8, x9, x1, x2) + +inst_1250: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xcbc0; + valaddr_reg:x6; val_offset:2452*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2452*FLEN/8, x9, x1, x2) + +inst_1251: +// fs1 == 1 and fe1 == 0x12 and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xcbc0; op2val:0xbc00; + valaddr_reg:x6; val_offset:2454*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2454*FLEN/8, x9, x1, x2) + +inst_1252: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc83f; + valaddr_reg:x6; val_offset:2456*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2456*FLEN/8, x9, x1, x2) + +inst_1253: +// fs1 == 1 and fe1 == 0x12 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc83f; op2val:0xbc00; + valaddr_reg:x6; val_offset:2458*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2458*FLEN/8, x9, x1, x2) + +inst_1254: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xcbe0; + valaddr_reg:x6; val_offset:2460*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2460*FLEN/8, x9, x1, x2) + +inst_1255: +// fs1 == 1 and fe1 == 0x12 and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xcbe0; op2val:0xbc00; + valaddr_reg:x6; val_offset:2462*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2462*FLEN/8, x9, x1, x2) + +inst_1256: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc81f; + valaddr_reg:x6; val_offset:2464*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2464*FLEN/8, x9, x1, x2) + +inst_1257: +// fs1 == 1 and fe1 == 0x12 and fm1 == 0x01f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc81f; op2val:0xbc00; + valaddr_reg:x6; val_offset:2466*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2466*FLEN/8, x9, x1, x2) + +inst_1258: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xcbf0; + valaddr_reg:x6; val_offset:2468*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2468*FLEN/8, x9, x1, x2) + +inst_1259: +// fs1 == 1 and fe1 == 0x12 and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xcbf0; op2val:0xbc00; + valaddr_reg:x6; val_offset:2470*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2470*FLEN/8, x9, x1, x2) + +inst_1260: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc80f; + valaddr_reg:x6; val_offset:2472*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2472*FLEN/8, x9, x1, x2) + +inst_1261: +// fs1 == 1 and fe1 == 0x12 and fm1 == 0x00f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc80f; op2val:0xbc00; + valaddr_reg:x6; val_offset:2474*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2474*FLEN/8, x9, x1, x2) + +inst_1262: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xcbf8; + valaddr_reg:x6; val_offset:2476*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2476*FLEN/8, x9, x1, x2) + +inst_1263: +// fs1 == 1 and fe1 == 0x12 and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xcbf8; op2val:0xbc00; + valaddr_reg:x6; val_offset:2478*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2478*FLEN/8, x9, x1, x2) + +inst_1264: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc807; + valaddr_reg:x6; val_offset:2480*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2480*FLEN/8, x9, x1, x2) + +inst_1265: +// fs1 == 1 and fe1 == 0x12 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc807; op2val:0xbc00; + valaddr_reg:x6; val_offset:2482*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2482*FLEN/8, x9, x1, x2) + +inst_1266: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xcbfc; + valaddr_reg:x6; val_offset:2484*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2484*FLEN/8, x9, x1, x2) + +inst_1267: +// fs1 == 1 and fe1 == 0x12 and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xcbfc; op2val:0xbc00; + valaddr_reg:x6; val_offset:2486*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2486*FLEN/8, x9, x1, x2) + +inst_1268: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc803; + valaddr_reg:x6; val_offset:2488*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2488*FLEN/8, x9, x1, x2) + +inst_1269: +// fs1 == 1 and fe1 == 0x12 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc803; op2val:0xbc00; + valaddr_reg:x6; val_offset:2490*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2490*FLEN/8, x9, x1, x2) + +inst_1270: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xcbfe; + valaddr_reg:x6; val_offset:2492*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2492*FLEN/8, x9, x1, x2) + +inst_1271: +// fs1 == 1 and fe1 == 0x12 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xcbfe; op2val:0xbc00; + valaddr_reg:x6; val_offset:2494*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2494*FLEN/8, x9, x1, x2) + +inst_1272: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xc801; + valaddr_reg:x6; val_offset:2496*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2496*FLEN/8, x9, x1, x2) + +inst_1273: +// fs1 == 1 and fe1 == 0x12 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc801; op2val:0xbc00; + valaddr_reg:x6; val_offset:2498*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2498*FLEN/8, x9, x1, x2) + +inst_1274: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x1; + valaddr_reg:x6; val_offset:2500*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2500*FLEN/8, x9, x1, x2) + +inst_1275: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x3ff; + valaddr_reg:x6; val_offset:2502*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2502*FLEN/8, x9, x1, x2) + +inst_1276: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x1; + valaddr_reg:x6; val_offset:2504*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2504*FLEN/8, x9, x1, x2) + +inst_1277: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x200; + valaddr_reg:x6; val_offset:2506*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2506*FLEN/8, x9, x1, x2) + +inst_1278: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x200; op2val:0x1; + valaddr_reg:x6; val_offset:2508*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2508*FLEN/8, x9, x1, x2) + +inst_1279: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x1ff; + valaddr_reg:x6; val_offset:2510*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2510*FLEN/8, x9, x1, x2) + +inst_1280: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1ff; op2val:0x1; + valaddr_reg:x6; val_offset:2512*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2512*FLEN/8, x9, x1, x2) + +inst_1281: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x300; + valaddr_reg:x6; val_offset:2514*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2514*FLEN/8, x9, x1, x2) + +inst_1282: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x300 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x300; op2val:0x1; + valaddr_reg:x6; val_offset:2516*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2516*FLEN/8, x9, x1, x2) + +inst_1283: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xff; + valaddr_reg:x6; val_offset:2518*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2518*FLEN/8, x9, x1, x2) + +inst_1284: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xff; op2val:0x1; + valaddr_reg:x6; val_offset:2520*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2520*FLEN/8, x9, x1, x2) + +inst_1285: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x380; + valaddr_reg:x6; val_offset:2522*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2522*FLEN/8, x9, x1, x2) + +inst_1286: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x380 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x380; op2val:0x1; + valaddr_reg:x6; val_offset:2524*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2524*FLEN/8, x9, x1, x2) + +inst_1287: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7f; + valaddr_reg:x6; val_offset:2526*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2526*FLEN/8, x9, x1, x2) + +inst_1288: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x07f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7f; op2val:0x1; + valaddr_reg:x6; val_offset:2528*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2528*FLEN/8, x9, x1, x2) + +inst_1289: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x3c0; + valaddr_reg:x6; val_offset:2530*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2530*FLEN/8, x9, x1, x2) + +inst_1290: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c0; op2val:0x1; + valaddr_reg:x6; val_offset:2532*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2532*FLEN/8, x9, x1, x2) + +inst_1291: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x3f; + valaddr_reg:x6; val_offset:2534*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2534*FLEN/8, x9, x1, x2) + +inst_1292: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3f; op2val:0x1; + valaddr_reg:x6; val_offset:2536*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2536*FLEN/8, x9, x1, x2) + +inst_1293: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x3e0; + valaddr_reg:x6; val_offset:2538*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2538*FLEN/8, x9, x1, x2) + +inst_1294: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3e0; op2val:0x1; + valaddr_reg:x6; val_offset:2540*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2540*FLEN/8, x9, x1, x2) + +inst_1295: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x1f; + valaddr_reg:x6; val_offset:2542*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2542*FLEN/8, x9, x1, x2) + +inst_1296: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x01f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1f; op2val:0x1; + valaddr_reg:x6; val_offset:2544*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2544*FLEN/8, x9, x1, x2) + +inst_1297: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x3f0; + valaddr_reg:x6; val_offset:2546*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2546*FLEN/8, x9, x1, x2) + +inst_1298: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3f0; op2val:0x1; + valaddr_reg:x6; val_offset:2548*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2548*FLEN/8, x9, x1, x2) + +inst_1299: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xf; + valaddr_reg:x6; val_offset:2550*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2550*FLEN/8, x9, x1, x2) + +inst_1300: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf; op2val:0x1; + valaddr_reg:x6; val_offset:2552*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2552*FLEN/8, x9, x1, x2) + +inst_1301: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x3f8; + valaddr_reg:x6; val_offset:2554*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2554*FLEN/8, x9, x1, x2) + +inst_1302: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3f8; op2val:0x1; + valaddr_reg:x6; val_offset:2556*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2556*FLEN/8, x9, x1, x2) + +inst_1303: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7; + valaddr_reg:x6; val_offset:2558*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2558*FLEN/8, x9, x1, x2) + +inst_1304: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7; op2val:0x1; + valaddr_reg:x6; val_offset:2560*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2560*FLEN/8, x9, x1, x2) + +inst_1305: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x3fc; + valaddr_reg:x6; val_offset:2562*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2562*FLEN/8, x9, x1, x2) + +inst_1306: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fc; op2val:0x1; + valaddr_reg:x6; val_offset:2564*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2564*FLEN/8, x9, x1, x2) + +inst_1307: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x3; + valaddr_reg:x6; val_offset:2566*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2566*FLEN/8, x9, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_10) + +inst_1308: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x003 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3; op2val:0x1; + valaddr_reg:x6; val_offset:2568*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2568*FLEN/8, x9, x1, x2) + +inst_1309: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x3fe; + valaddr_reg:x6; val_offset:2570*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2570*FLEN/8, x9, x1, x2) + +inst_1310: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fe; op2val:0x1; + valaddr_reg:x6; val_offset:2572*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2572*FLEN/8, x9, x1, x2) + +inst_1311: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1b6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x1b6; + valaddr_reg:x6; val_offset:2574*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2574*FLEN/8, x9, x1, x2) + +inst_1312: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1b6; op2val:0x1; + valaddr_reg:x6; val_offset:2576*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2576*FLEN/8, x9, x1, x2) + +inst_1313: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x36d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x36d; + valaddr_reg:x6; val_offset:2578*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2578*FLEN/8, x9, x1, x2) + +inst_1314: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x36d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x36d; op2val:0x1; + valaddr_reg:x6; val_offset:2580*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2580*FLEN/8, x9, x1, x2) + +inst_1315: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0cc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xcc; + valaddr_reg:x6; val_offset:2582*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2582*FLEN/8, x9, x1, x2) + +inst_1316: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0cc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xcc; op2val:0x1; + valaddr_reg:x6; val_offset:2584*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2584*FLEN/8, x9, x1, x2) + +inst_1317: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x333 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x333; + valaddr_reg:x6; val_offset:2586*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2586*FLEN/8, x9, x1, x2) + +inst_1318: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x333 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x333; op2val:0x1; + valaddr_reg:x6; val_offset:2588*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2588*FLEN/8, x9, x1, x2) + +inst_1319: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1dd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x1dd; + valaddr_reg:x6; val_offset:2590*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2590*FLEN/8, x9, x1, x2) + +inst_1320: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1dd; op2val:0x1; + valaddr_reg:x6; val_offset:2592*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2592*FLEN/8, x9, x1, x2) + +inst_1321: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x222 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x222; + valaddr_reg:x6; val_offset:2594*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2594*FLEN/8, x9, x1, x2) + +inst_1322: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x222 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x222; op2val:0x1; + valaddr_reg:x6; val_offset:2596*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2596*FLEN/8, x9, x1, x2) + +inst_1323: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x124 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x124; + valaddr_reg:x6; val_offset:2598*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2598*FLEN/8, x9, x1, x2) + +inst_1324: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x124 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x124; op2val:0x1; + valaddr_reg:x6; val_offset:2600*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2600*FLEN/8, x9, x1, x2) + +inst_1325: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2db and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x2db; + valaddr_reg:x6; val_offset:2602*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2602*FLEN/8, x9, x1, x2) + +inst_1326: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2db; op2val:0x1; + valaddr_reg:x6; val_offset:2604*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2604*FLEN/8, x9, x1, x2) + +inst_1327: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x199 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x199; + valaddr_reg:x6; val_offset:2606*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2606*FLEN/8, x9, x1, x2) + +inst_1328: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x199 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x199; op2val:0x1; + valaddr_reg:x6; val_offset:2608*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2608*FLEN/8, x9, x1, x2) + +inst_1329: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x266 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x266; + valaddr_reg:x6; val_offset:2610*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2610*FLEN/8, x9, x1, x2) + +inst_1330: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x266 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x266; op2val:0x1; + valaddr_reg:x6; val_offset:2612*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2612*FLEN/8, x9, x1, x2) + +inst_1331: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x1801; + valaddr_reg:x6; val_offset:2614*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2614*FLEN/8, x9, x1, x2) + +inst_1332: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1801; op2val:0x1; + valaddr_reg:x6; val_offset:2616*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2616*FLEN/8, x9, x1, x2) + +inst_1333: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x1800; + valaddr_reg:x6; val_offset:2618*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2618*FLEN/8, x9, x1, x2) + +inst_1334: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1800; op2val:0x1; + valaddr_reg:x6; val_offset:2620*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2620*FLEN/8, x9, x1, x2) + +inst_1335: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x1bff; + valaddr_reg:x6; val_offset:2622*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2622*FLEN/8, x9, x1, x2) + +inst_1336: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1bff; op2val:0x1; + valaddr_reg:x6; val_offset:2624*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2624*FLEN/8, x9, x1, x2) + +inst_1337: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x1a00; + valaddr_reg:x6; val_offset:2626*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2626*FLEN/8, x9, x1, x2) + +inst_1338: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1a00; op2val:0x1; + valaddr_reg:x6; val_offset:2628*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2628*FLEN/8, x9, x1, x2) + +inst_1339: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x19ff; + valaddr_reg:x6; val_offset:2630*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2630*FLEN/8, x9, x1, x2) + +inst_1340: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x19ff; op2val:0x1; + valaddr_reg:x6; val_offset:2632*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2632*FLEN/8, x9, x1, x2) + +inst_1341: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x1b00; + valaddr_reg:x6; val_offset:2634*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2634*FLEN/8, x9, x1, x2) + +inst_1342: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x300 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1b00; op2val:0x1; + valaddr_reg:x6; val_offset:2636*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2636*FLEN/8, x9, x1, x2) + +inst_1343: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x18ff; + valaddr_reg:x6; val_offset:2638*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2638*FLEN/8, x9, x1, x2) + +inst_1344: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x18ff; op2val:0x1; + valaddr_reg:x6; val_offset:2640*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2640*FLEN/8, x9, x1, x2) + +inst_1345: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x1b80; + valaddr_reg:x6; val_offset:2642*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2642*FLEN/8, x9, x1, x2) + +inst_1346: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x380 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1b80; op2val:0x1; + valaddr_reg:x6; val_offset:2644*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2644*FLEN/8, x9, x1, x2) + +inst_1347: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x187f; + valaddr_reg:x6; val_offset:2646*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2646*FLEN/8, x9, x1, x2) + +inst_1348: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x07f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x187f; op2val:0x1; + valaddr_reg:x6; val_offset:2648*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2648*FLEN/8, x9, x1, x2) + +inst_1349: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x1bc0; + valaddr_reg:x6; val_offset:2650*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2650*FLEN/8, x9, x1, x2) + +inst_1350: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1bc0; op2val:0x1; + valaddr_reg:x6; val_offset:2652*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2652*FLEN/8, x9, x1, x2) + +inst_1351: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x183f; + valaddr_reg:x6; val_offset:2654*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2654*FLEN/8, x9, x1, x2) + +inst_1352: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x183f; op2val:0x1; + valaddr_reg:x6; val_offset:2656*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2656*FLEN/8, x9, x1, x2) + +inst_1353: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x1be0; + valaddr_reg:x6; val_offset:2658*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2658*FLEN/8, x9, x1, x2) + +inst_1354: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1be0; op2val:0x1; + valaddr_reg:x6; val_offset:2660*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2660*FLEN/8, x9, x1, x2) + +inst_1355: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x181f; + valaddr_reg:x6; val_offset:2662*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2662*FLEN/8, x9, x1, x2) + +inst_1356: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x01f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x181f; op2val:0x1; + valaddr_reg:x6; val_offset:2664*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2664*FLEN/8, x9, x1, x2) + +inst_1357: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x1bf0; + valaddr_reg:x6; val_offset:2666*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2666*FLEN/8, x9, x1, x2) + +inst_1358: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1bf0; op2val:0x1; + valaddr_reg:x6; val_offset:2668*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2668*FLEN/8, x9, x1, x2) + +inst_1359: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x180f; + valaddr_reg:x6; val_offset:2670*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2670*FLEN/8, x9, x1, x2) + +inst_1360: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x00f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x180f; op2val:0x1; + valaddr_reg:x6; val_offset:2672*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2672*FLEN/8, x9, x1, x2) + +inst_1361: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x1bf8; + valaddr_reg:x6; val_offset:2674*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2674*FLEN/8, x9, x1, x2) + +inst_1362: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1bf8; op2val:0x1; + valaddr_reg:x6; val_offset:2676*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2676*FLEN/8, x9, x1, x2) + +inst_1363: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x1807; + valaddr_reg:x6; val_offset:2678*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2678*FLEN/8, x9, x1, x2) + +inst_1364: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1807; op2val:0x1; + valaddr_reg:x6; val_offset:2680*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2680*FLEN/8, x9, x1, x2) + +inst_1365: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x1bfc; + valaddr_reg:x6; val_offset:2682*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2682*FLEN/8, x9, x1, x2) + +inst_1366: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1bfc; op2val:0x1; + valaddr_reg:x6; val_offset:2684*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2684*FLEN/8, x9, x1, x2) + +inst_1367: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x1803; + valaddr_reg:x6; val_offset:2686*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2686*FLEN/8, x9, x1, x2) + +inst_1368: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x003 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1803; op2val:0x1; + valaddr_reg:x6; val_offset:2688*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2688*FLEN/8, x9, x1, x2) + +inst_1369: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x1bfe; + valaddr_reg:x6; val_offset:2690*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2690*FLEN/8, x9, x1, x2) + +inst_1370: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1bfe; op2val:0x1; + valaddr_reg:x6; val_offset:2692*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2692*FLEN/8, x9, x1, x2) + +inst_1371: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x401; + valaddr_reg:x6; val_offset:2694*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2694*FLEN/8, x9, x1, x2) + +inst_1372: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x1; + valaddr_reg:x6; val_offset:2696*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2696*FLEN/8, x9, x1, x2) + +inst_1373: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x400; + valaddr_reg:x6; val_offset:2698*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2698*FLEN/8, x9, x1, x2) + +inst_1374: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x1; + valaddr_reg:x6; val_offset:2700*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2700*FLEN/8, x9, x1, x2) + +inst_1375: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7ff; + valaddr_reg:x6; val_offset:2702*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2702*FLEN/8, x9, x1, x2) + +inst_1376: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ff; op2val:0x1; + valaddr_reg:x6; val_offset:2704*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2704*FLEN/8, x9, x1, x2) + +inst_1377: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x600; + valaddr_reg:x6; val_offset:2706*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2706*FLEN/8, x9, x1, x2) + +inst_1378: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x600; op2val:0x1; + valaddr_reg:x6; val_offset:2708*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2708*FLEN/8, x9, x1, x2) + +inst_1379: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x5ff; + valaddr_reg:x6; val_offset:2710*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2710*FLEN/8, x9, x1, x2) + +inst_1380: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5ff; op2val:0x1; + valaddr_reg:x6; val_offset:2712*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2712*FLEN/8, x9, x1, x2) + +inst_1381: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x700; + valaddr_reg:x6; val_offset:2714*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2714*FLEN/8, x9, x1, x2) + +inst_1382: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x300 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x700; op2val:0x1; + valaddr_reg:x6; val_offset:2716*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2716*FLEN/8, x9, x1, x2) + +inst_1383: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x4ff; + valaddr_reg:x6; val_offset:2718*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2718*FLEN/8, x9, x1, x2) + +inst_1384: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4ff; op2val:0x1; + valaddr_reg:x6; val_offset:2720*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2720*FLEN/8, x9, x1, x2) + +inst_1385: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x780; + valaddr_reg:x6; val_offset:2722*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2722*FLEN/8, x9, x1, x2) + +inst_1386: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x380 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x780; op2val:0x1; + valaddr_reg:x6; val_offset:2724*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2724*FLEN/8, x9, x1, x2) + +inst_1387: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x47f; + valaddr_reg:x6; val_offset:2726*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2726*FLEN/8, x9, x1, x2) + +inst_1388: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x07f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x47f; op2val:0x1; + valaddr_reg:x6; val_offset:2728*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2728*FLEN/8, x9, x1, x2) + +inst_1389: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7c0; + valaddr_reg:x6; val_offset:2730*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2730*FLEN/8, x9, x1, x2) + +inst_1390: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c0; op2val:0x1; + valaddr_reg:x6; val_offset:2732*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2732*FLEN/8, x9, x1, x2) + +inst_1391: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x43f; + valaddr_reg:x6; val_offset:2734*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2734*FLEN/8, x9, x1, x2) + +inst_1392: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x43f; op2val:0x1; + valaddr_reg:x6; val_offset:2736*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2736*FLEN/8, x9, x1, x2) + +inst_1393: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7e0; + valaddr_reg:x6; val_offset:2738*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2738*FLEN/8, x9, x1, x2) + +inst_1394: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e0; op2val:0x1; + valaddr_reg:x6; val_offset:2740*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2740*FLEN/8, x9, x1, x2) + +inst_1395: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x41f; + valaddr_reg:x6; val_offset:2742*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2742*FLEN/8, x9, x1, x2) + +inst_1396: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x01f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x41f; op2val:0x1; + valaddr_reg:x6; val_offset:2744*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2744*FLEN/8, x9, x1, x2) + +inst_1397: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7f0; + valaddr_reg:x6; val_offset:2746*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2746*FLEN/8, x9, x1, x2) + +inst_1398: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7f0; op2val:0x1; + valaddr_reg:x6; val_offset:2748*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2748*FLEN/8, x9, x1, x2) + +inst_1399: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x40f; + valaddr_reg:x6; val_offset:2750*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2750*FLEN/8, x9, x1, x2) + +inst_1400: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x00f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x40f; op2val:0x1; + valaddr_reg:x6; val_offset:2752*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2752*FLEN/8, x9, x1, x2) + +inst_1401: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7f8; + valaddr_reg:x6; val_offset:2754*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2754*FLEN/8, x9, x1, x2) + +inst_1402: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7f8; op2val:0x1; + valaddr_reg:x6; val_offset:2756*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2756*FLEN/8, x9, x1, x2) + +inst_1403: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x407; + valaddr_reg:x6; val_offset:2758*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2758*FLEN/8, x9, x1, x2) + +inst_1404: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x407; op2val:0x1; + valaddr_reg:x6; val_offset:2760*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2760*FLEN/8, x9, x1, x2) + +inst_1405: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7fc; + valaddr_reg:x6; val_offset:2762*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2762*FLEN/8, x9, x1, x2) + +inst_1406: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7fc; op2val:0x1; + valaddr_reg:x6; val_offset:2764*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2764*FLEN/8, x9, x1, x2) + +inst_1407: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x403; + valaddr_reg:x6; val_offset:2766*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2766*FLEN/8, x9, x1, x2) + +inst_1408: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x003 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x403; op2val:0x1; + valaddr_reg:x6; val_offset:2768*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2768*FLEN/8, x9, x1, x2) + +inst_1409: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x7fe; + valaddr_reg:x6; val_offset:2770*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2770*FLEN/8, x9, x1, x2) + +inst_1410: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7fe; op2val:0x1; + valaddr_reg:x6; val_offset:2772*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2772*FLEN/8, x9, x1, x2) + +inst_1411: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x801; + valaddr_reg:x6; val_offset:2774*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2774*FLEN/8, x9, x1, x2) + +inst_1412: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x801; op2val:0x1; + valaddr_reg:x6; val_offset:2776*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2776*FLEN/8, x9, x1, x2) + +inst_1413: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x800; + valaddr_reg:x6; val_offset:2778*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2778*FLEN/8, x9, x1, x2) + +inst_1414: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x800; op2val:0x1; + valaddr_reg:x6; val_offset:2780*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2780*FLEN/8, x9, x1, x2) + +inst_1415: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xbff; + valaddr_reg:x6; val_offset:2782*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2782*FLEN/8, x9, x1, x2) + +inst_1416: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbff; op2val:0x1; + valaddr_reg:x6; val_offset:2784*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2784*FLEN/8, x9, x1, x2) + +inst_1417: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xa00; + valaddr_reg:x6; val_offset:2786*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2786*FLEN/8, x9, x1, x2) + +inst_1418: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xa00; op2val:0x1; + valaddr_reg:x6; val_offset:2788*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2788*FLEN/8, x9, x1, x2) + +inst_1419: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x9ff; + valaddr_reg:x6; val_offset:2790*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2790*FLEN/8, x9, x1, x2) + +inst_1420: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x9ff; op2val:0x1; + valaddr_reg:x6; val_offset:2792*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2792*FLEN/8, x9, x1, x2) + +inst_1421: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xb00; + valaddr_reg:x6; val_offset:2794*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2794*FLEN/8, x9, x1, x2) + +inst_1422: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x300 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xb00; op2val:0x1; + valaddr_reg:x6; val_offset:2796*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2796*FLEN/8, x9, x1, x2) + +inst_1423: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x8ff; + valaddr_reg:x6; val_offset:2798*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2798*FLEN/8, x9, x1, x2) + +inst_1424: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8ff; op2val:0x1; + valaddr_reg:x6; val_offset:2800*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2800*FLEN/8, x9, x1, x2) + +inst_1425: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xb80; + valaddr_reg:x6; val_offset:2802*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2802*FLEN/8, x9, x1, x2) + +inst_1426: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x380 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xb80; op2val:0x1; + valaddr_reg:x6; val_offset:2804*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2804*FLEN/8, x9, x1, x2) + +inst_1427: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x87f; + valaddr_reg:x6; val_offset:2806*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2806*FLEN/8, x9, x1, x2) + +inst_1428: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x07f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x87f; op2val:0x1; + valaddr_reg:x6; val_offset:2808*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2808*FLEN/8, x9, x1, x2) + +inst_1429: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xbc0; + valaddr_reg:x6; val_offset:2810*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2810*FLEN/8, x9, x1, x2) + +inst_1430: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc0; op2val:0x1; + valaddr_reg:x6; val_offset:2812*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2812*FLEN/8, x9, x1, x2) + +inst_1431: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x83f; + valaddr_reg:x6; val_offset:2814*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2814*FLEN/8, x9, x1, x2) + +inst_1432: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83f; op2val:0x1; + valaddr_reg:x6; val_offset:2816*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2816*FLEN/8, x9, x1, x2) + +inst_1433: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xbe0; + valaddr_reg:x6; val_offset:2818*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2818*FLEN/8, x9, x1, x2) + +inst_1434: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbe0; op2val:0x1; + valaddr_reg:x6; val_offset:2820*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2820*FLEN/8, x9, x1, x2) + +inst_1435: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x81f; + valaddr_reg:x6; val_offset:2822*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2822*FLEN/8, x9, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_11) + +inst_1436: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x01f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x81f; op2val:0x1; + valaddr_reg:x6; val_offset:2824*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2824*FLEN/8, x9, x1, x2) + +inst_1437: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xbf0; + valaddr_reg:x6; val_offset:2826*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2826*FLEN/8, x9, x1, x2) + +inst_1438: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbf0; op2val:0x1; + valaddr_reg:x6; val_offset:2828*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2828*FLEN/8, x9, x1, x2) + +inst_1439: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x80f; + valaddr_reg:x6; val_offset:2830*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2830*FLEN/8, x9, x1, x2) + +inst_1440: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x00f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x80f; op2val:0x1; + valaddr_reg:x6; val_offset:2832*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2832*FLEN/8, x9, x1, x2) + +inst_1441: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xbf8; + valaddr_reg:x6; val_offset:2834*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2834*FLEN/8, x9, x1, x2) + +inst_1442: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbf8; op2val:0x1; + valaddr_reg:x6; val_offset:2836*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2836*FLEN/8, x9, x1, x2) + +inst_1443: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x807; + valaddr_reg:x6; val_offset:2838*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2838*FLEN/8, x9, x1, x2) + +inst_1444: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x807; op2val:0x1; + valaddr_reg:x6; val_offset:2840*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2840*FLEN/8, x9, x1, x2) + +inst_1445: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xbfc; + valaddr_reg:x6; val_offset:2842*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2842*FLEN/8, x9, x1, x2) + +inst_1446: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbfc; op2val:0x1; + valaddr_reg:x6; val_offset:2844*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2844*FLEN/8, x9, x1, x2) + +inst_1447: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x803; + valaddr_reg:x6; val_offset:2846*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2846*FLEN/8, x9, x1, x2) + +inst_1448: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x003 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x803; op2val:0x1; + valaddr_reg:x6; val_offset:2848*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2848*FLEN/8, x9, x1, x2) + +inst_1449: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xbfe; + valaddr_reg:x6; val_offset:2850*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2850*FLEN/8, x9, x1, x2) + +inst_1450: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbfe; op2val:0x1; + valaddr_reg:x6; val_offset:2852*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2852*FLEN/8, x9, x1, x2) + +inst_1451: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xc01; + valaddr_reg:x6; val_offset:2854*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2854*FLEN/8, x9, x1, x2) + +inst_1452: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc01; op2val:0x1; + valaddr_reg:x6; val_offset:2856*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2856*FLEN/8, x9, x1, x2) + +inst_1453: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xc00; + valaddr_reg:x6; val_offset:2858*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2858*FLEN/8, x9, x1, x2) + +inst_1454: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc00; op2val:0x1; + valaddr_reg:x6; val_offset:2860*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2860*FLEN/8, x9, x1, x2) + +inst_1455: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xfff; + valaddr_reg:x6; val_offset:2862*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2862*FLEN/8, x9, x1, x2) + +inst_1456: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfff; op2val:0x1; + valaddr_reg:x6; val_offset:2864*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2864*FLEN/8, x9, x1, x2) + +inst_1457: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xe00; + valaddr_reg:x6; val_offset:2866*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2866*FLEN/8, x9, x1, x2) + +inst_1458: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xe00; op2val:0x1; + valaddr_reg:x6; val_offset:2868*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2868*FLEN/8, x9, x1, x2) + +inst_1459: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xdff; + valaddr_reg:x6; val_offset:2870*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2870*FLEN/8, x9, x1, x2) + +inst_1460: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xdff; op2val:0x1; + valaddr_reg:x6; val_offset:2872*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2872*FLEN/8, x9, x1, x2) + +inst_1461: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xf00; + valaddr_reg:x6; val_offset:2874*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2874*FLEN/8, x9, x1, x2) + +inst_1462: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x300 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf00; op2val:0x1; + valaddr_reg:x6; val_offset:2876*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2876*FLEN/8, x9, x1, x2) + +inst_1463: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xcff; + valaddr_reg:x6; val_offset:2878*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2878*FLEN/8, x9, x1, x2) + +inst_1464: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xcff; op2val:0x1; + valaddr_reg:x6; val_offset:2880*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2880*FLEN/8, x9, x1, x2) + +inst_1465: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xf80; + valaddr_reg:x6; val_offset:2882*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2882*FLEN/8, x9, x1, x2) + +inst_1466: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x380 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf80; op2val:0x1; + valaddr_reg:x6; val_offset:2884*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2884*FLEN/8, x9, x1, x2) + +inst_1467: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xc7f; + valaddr_reg:x6; val_offset:2886*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2886*FLEN/8, x9, x1, x2) + +inst_1468: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x07f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc7f; op2val:0x1; + valaddr_reg:x6; val_offset:2888*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2888*FLEN/8, x9, x1, x2) + +inst_1469: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xfc0; + valaddr_reg:x6; val_offset:2890*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2890*FLEN/8, x9, x1, x2) + +inst_1470: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc0; op2val:0x1; + valaddr_reg:x6; val_offset:2892*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2892*FLEN/8, x9, x1, x2) + +inst_1471: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xc3f; + valaddr_reg:x6; val_offset:2894*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2894*FLEN/8, x9, x1, x2) + +inst_1472: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc3f; op2val:0x1; + valaddr_reg:x6; val_offset:2896*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2896*FLEN/8, x9, x1, x2) + +inst_1473: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xfe0; + valaddr_reg:x6; val_offset:2898*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2898*FLEN/8, x9, x1, x2) + +inst_1474: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe0; op2val:0x1; + valaddr_reg:x6; val_offset:2900*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2900*FLEN/8, x9, x1, x2) + +inst_1475: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xc1f; + valaddr_reg:x6; val_offset:2902*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2902*FLEN/8, x9, x1, x2) + +inst_1476: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x01f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc1f; op2val:0x1; + valaddr_reg:x6; val_offset:2904*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2904*FLEN/8, x9, x1, x2) + +inst_1477: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xff0; + valaddr_reg:x6; val_offset:2906*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2906*FLEN/8, x9, x1, x2) + +inst_1478: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xff0; op2val:0x1; + valaddr_reg:x6; val_offset:2908*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2908*FLEN/8, x9, x1, x2) + +inst_1479: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xc0f; + valaddr_reg:x6; val_offset:2910*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2910*FLEN/8, x9, x1, x2) + +inst_1480: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x00f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc0f; op2val:0x1; + valaddr_reg:x6; val_offset:2912*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2912*FLEN/8, x9, x1, x2) + +inst_1481: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xff8; + valaddr_reg:x6; val_offset:2914*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2914*FLEN/8, x9, x1, x2) + +inst_1482: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xff8; op2val:0x1; + valaddr_reg:x6; val_offset:2916*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2916*FLEN/8, x9, x1, x2) + +inst_1483: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xc07; + valaddr_reg:x6; val_offset:2918*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2918*FLEN/8, x9, x1, x2) + +inst_1484: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc07; op2val:0x1; + valaddr_reg:x6; val_offset:2920*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2920*FLEN/8, x9, x1, x2) + +inst_1485: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xffc; + valaddr_reg:x6; val_offset:2922*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2922*FLEN/8, x9, x1, x2) + +inst_1486: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xffc; op2val:0x1; + valaddr_reg:x6; val_offset:2924*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2924*FLEN/8, x9, x1, x2) + +inst_1487: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xc03; + valaddr_reg:x6; val_offset:2926*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2926*FLEN/8, x9, x1, x2) + +inst_1488: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x003 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc03; op2val:0x1; + valaddr_reg:x6; val_offset:2928*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2928*FLEN/8, x9, x1, x2) + +inst_1489: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0xffe; + valaddr_reg:x6; val_offset:2930*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2930*FLEN/8, x9, x1, x2) + +inst_1490: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xffe; op2val:0x1; + valaddr_reg:x6; val_offset:2932*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2932*FLEN/8, x9, x1, x2) + +inst_1491: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8001; + valaddr_reg:x6; val_offset:2934*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2934*FLEN/8, x9, x1, x2) + +inst_1492: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x83ff; + valaddr_reg:x6; val_offset:2936*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2936*FLEN/8, x9, x1, x2) + +inst_1493: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8001; + valaddr_reg:x6; val_offset:2938*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2938*FLEN/8, x9, x1, x2) + +inst_1494: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8200; + valaddr_reg:x6; val_offset:2940*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2940*FLEN/8, x9, x1, x2) + +inst_1495: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8200; op2val:0x8001; + valaddr_reg:x6; val_offset:2942*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2942*FLEN/8, x9, x1, x2) + +inst_1496: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x81ff; + valaddr_reg:x6; val_offset:2944*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2944*FLEN/8, x9, x1, x2) + +inst_1497: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x81ff; op2val:0x8001; + valaddr_reg:x6; val_offset:2946*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2946*FLEN/8, x9, x1, x2) + +inst_1498: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8300; + valaddr_reg:x6; val_offset:2948*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2948*FLEN/8, x9, x1, x2) + +inst_1499: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x300 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8300; op2val:0x8001; + valaddr_reg:x6; val_offset:2950*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2950*FLEN/8, x9, x1, x2) + +inst_1500: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x80ff; + valaddr_reg:x6; val_offset:2952*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2952*FLEN/8, x9, x1, x2) + +inst_1501: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x80ff; op2val:0x8001; + valaddr_reg:x6; val_offset:2954*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2954*FLEN/8, x9, x1, x2) + +inst_1502: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8380; + valaddr_reg:x6; val_offset:2956*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2956*FLEN/8, x9, x1, x2) + +inst_1503: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x380 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8380; op2val:0x8001; + valaddr_reg:x6; val_offset:2958*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2958*FLEN/8, x9, x1, x2) + +inst_1504: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x807f; + valaddr_reg:x6; val_offset:2960*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2960*FLEN/8, x9, x1, x2) + +inst_1505: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x07f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x807f; op2val:0x8001; + valaddr_reg:x6; val_offset:2962*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2962*FLEN/8, x9, x1, x2) + +inst_1506: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x83c0; + valaddr_reg:x6; val_offset:2964*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2964*FLEN/8, x9, x1, x2) + +inst_1507: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83c0; op2val:0x8001; + valaddr_reg:x6; val_offset:2966*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2966*FLEN/8, x9, x1, x2) + +inst_1508: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x803f; + valaddr_reg:x6; val_offset:2968*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2968*FLEN/8, x9, x1, x2) + +inst_1509: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x803f; op2val:0x8001; + valaddr_reg:x6; val_offset:2970*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2970*FLEN/8, x9, x1, x2) + +inst_1510: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x83e0; + valaddr_reg:x6; val_offset:2972*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2972*FLEN/8, x9, x1, x2) + +inst_1511: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83e0; op2val:0x8001; + valaddr_reg:x6; val_offset:2974*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2974*FLEN/8, x9, x1, x2) + +inst_1512: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x801f; + valaddr_reg:x6; val_offset:2976*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2976*FLEN/8, x9, x1, x2) + +inst_1513: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x01f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x801f; op2val:0x8001; + valaddr_reg:x6; val_offset:2978*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2978*FLEN/8, x9, x1, x2) + +inst_1514: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x83f0; + valaddr_reg:x6; val_offset:2980*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2980*FLEN/8, x9, x1, x2) + +inst_1515: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83f0; op2val:0x8001; + valaddr_reg:x6; val_offset:2982*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2982*FLEN/8, x9, x1, x2) + +inst_1516: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x800f; + valaddr_reg:x6; val_offset:2984*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2984*FLEN/8, x9, x1, x2) + +inst_1517: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x00f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x800f; op2val:0x8001; + valaddr_reg:x6; val_offset:2986*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2986*FLEN/8, x9, x1, x2) + +inst_1518: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x83f8; + valaddr_reg:x6; val_offset:2988*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2988*FLEN/8, x9, x1, x2) + +inst_1519: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83f8; op2val:0x8001; + valaddr_reg:x6; val_offset:2990*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2990*FLEN/8, x9, x1, x2) + +inst_1520: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8007; + valaddr_reg:x6; val_offset:2992*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2992*FLEN/8, x9, x1, x2) + +inst_1521: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8007; op2val:0x8001; + valaddr_reg:x6; val_offset:2994*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2994*FLEN/8, x9, x1, x2) + +inst_1522: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x83fc; + valaddr_reg:x6; val_offset:2996*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2996*FLEN/8, x9, x1, x2) + +inst_1523: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fc; op2val:0x8001; + valaddr_reg:x6; val_offset:2998*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 2998*FLEN/8, x9, x1, x2) + +inst_1524: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8003; + valaddr_reg:x6; val_offset:3000*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3000*FLEN/8, x9, x1, x2) + +inst_1525: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8003; op2val:0x8001; + valaddr_reg:x6; val_offset:3002*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3002*FLEN/8, x9, x1, x2) + +inst_1526: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x83fe; + valaddr_reg:x6; val_offset:3004*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3004*FLEN/8, x9, x1, x2) + +inst_1527: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x8001; + valaddr_reg:x6; val_offset:3006*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3006*FLEN/8, x9, x1, x2) + +inst_1528: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1b6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x81b6; + valaddr_reg:x6; val_offset:3008*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3008*FLEN/8, x9, x1, x2) + +inst_1529: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x81b6; op2val:0x8001; + valaddr_reg:x6; val_offset:3010*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3010*FLEN/8, x9, x1, x2) + +inst_1530: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x36d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x836d; + valaddr_reg:x6; val_offset:3012*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3012*FLEN/8, x9, x1, x2) + +inst_1531: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x36d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x836d; op2val:0x8001; + valaddr_reg:x6; val_offset:3014*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3014*FLEN/8, x9, x1, x2) + +inst_1532: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0cc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x80cc; + valaddr_reg:x6; val_offset:3016*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3016*FLEN/8, x9, x1, x2) + +inst_1533: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0cc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x80cc; op2val:0x8001; + valaddr_reg:x6; val_offset:3018*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3018*FLEN/8, x9, x1, x2) + +inst_1534: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x333 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8333; + valaddr_reg:x6; val_offset:3020*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3020*FLEN/8, x9, x1, x2) + +inst_1535: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x333 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8333; op2val:0x8001; + valaddr_reg:x6; val_offset:3022*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3022*FLEN/8, x9, x1, x2) + +inst_1536: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1dd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x81dd; + valaddr_reg:x6; val_offset:3024*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3024*FLEN/8, x9, x1, x2) + +inst_1537: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1dd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x81dd; op2val:0x8001; + valaddr_reg:x6; val_offset:3026*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3026*FLEN/8, x9, x1, x2) + +inst_1538: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x222 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8222; + valaddr_reg:x6; val_offset:3028*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3028*FLEN/8, x9, x1, x2) + +inst_1539: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x222 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8222; op2val:0x8001; + valaddr_reg:x6; val_offset:3030*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3030*FLEN/8, x9, x1, x2) + +inst_1540: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x124 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8124; + valaddr_reg:x6; val_offset:3032*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3032*FLEN/8, x9, x1, x2) + +inst_1541: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x124 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8124; op2val:0x8001; + valaddr_reg:x6; val_offset:3034*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3034*FLEN/8, x9, x1, x2) + +inst_1542: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2db and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x82db; + valaddr_reg:x6; val_offset:3036*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3036*FLEN/8, x9, x1, x2) + +inst_1543: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x82db; op2val:0x8001; + valaddr_reg:x6; val_offset:3038*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3038*FLEN/8, x9, x1, x2) + +inst_1544: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x199 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8199; + valaddr_reg:x6; val_offset:3040*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3040*FLEN/8, x9, x1, x2) + +inst_1545: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x199 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8199; op2val:0x8001; + valaddr_reg:x6; val_offset:3042*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3042*FLEN/8, x9, x1, x2) + +inst_1546: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x266 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8266; + valaddr_reg:x6; val_offset:3044*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3044*FLEN/8, x9, x1, x2) + +inst_1547: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x266 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8266; op2val:0x8001; + valaddr_reg:x6; val_offset:3046*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3046*FLEN/8, x9, x1, x2) + +inst_1548: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x17 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xdc01; + valaddr_reg:x6; val_offset:3048*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3048*FLEN/8, x9, x1, x2) + +inst_1549: +// fs1 == 1 and fe1 == 0x17 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xdc01; op2val:0x8001; + valaddr_reg:x6; val_offset:3050*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3050*FLEN/8, x9, x1, x2) + +inst_1550: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x17 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xdc00; + valaddr_reg:x6; val_offset:3052*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3052*FLEN/8, x9, x1, x2) + +inst_1551: +// fs1 == 1 and fe1 == 0x17 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xdc00; op2val:0x8001; + valaddr_reg:x6; val_offset:3054*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3054*FLEN/8, x9, x1, x2) + +inst_1552: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x17 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xdfff; + valaddr_reg:x6; val_offset:3056*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3056*FLEN/8, x9, x1, x2) + +inst_1553: +// fs1 == 1 and fe1 == 0x17 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xdfff; op2val:0x8001; + valaddr_reg:x6; val_offset:3058*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3058*FLEN/8, x9, x1, x2) + +inst_1554: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x17 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xde00; + valaddr_reg:x6; val_offset:3060*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3060*FLEN/8, x9, x1, x2) + +inst_1555: +// fs1 == 1 and fe1 == 0x17 and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xde00; op2val:0x8001; + valaddr_reg:x6; val_offset:3062*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3062*FLEN/8, x9, x1, x2) + +inst_1556: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x17 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xddff; + valaddr_reg:x6; val_offset:3064*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3064*FLEN/8, x9, x1, x2) + +inst_1557: +// fs1 == 1 and fe1 == 0x17 and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xddff; op2val:0x8001; + valaddr_reg:x6; val_offset:3066*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3066*FLEN/8, x9, x1, x2) + +inst_1558: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x17 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xdf00; + valaddr_reg:x6; val_offset:3068*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3068*FLEN/8, x9, x1, x2) + +inst_1559: +// fs1 == 1 and fe1 == 0x17 and fm1 == 0x300 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xdf00; op2val:0x8001; + valaddr_reg:x6; val_offset:3070*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3070*FLEN/8, x9, x1, x2) + +inst_1560: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x17 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xdcff; + valaddr_reg:x6; val_offset:3072*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3072*FLEN/8, x9, x1, x2) + +inst_1561: +// fs1 == 1 and fe1 == 0x17 and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xdcff; op2val:0x8001; + valaddr_reg:x6; val_offset:3074*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3074*FLEN/8, x9, x1, x2) + +inst_1562: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x17 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xdf80; + valaddr_reg:x6; val_offset:3076*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3076*FLEN/8, x9, x1, x2) + +inst_1563: +// fs1 == 1 and fe1 == 0x17 and fm1 == 0x380 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xdf80; op2val:0x8001; + valaddr_reg:x6; val_offset:3078*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3078*FLEN/8, x9, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_12) + +inst_1564: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x17 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xdc7f; + valaddr_reg:x6; val_offset:3080*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3080*FLEN/8, x9, x1, x2) + +inst_1565: +// fs1 == 1 and fe1 == 0x17 and fm1 == 0x07f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xdc7f; op2val:0x8001; + valaddr_reg:x6; val_offset:3082*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3082*FLEN/8, x9, x1, x2) + +inst_1566: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x17 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xdfc0; + valaddr_reg:x6; val_offset:3084*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3084*FLEN/8, x9, x1, x2) + +inst_1567: +// fs1 == 1 and fe1 == 0x17 and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xdfc0; op2val:0x8001; + valaddr_reg:x6; val_offset:3086*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3086*FLEN/8, x9, x1, x2) + +inst_1568: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x17 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xdc3f; + valaddr_reg:x6; val_offset:3088*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3088*FLEN/8, x9, x1, x2) + +inst_1569: +// fs1 == 1 and fe1 == 0x17 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xdc3f; op2val:0x8001; + valaddr_reg:x6; val_offset:3090*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3090*FLEN/8, x9, x1, x2) + +inst_1570: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x17 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xdfe0; + valaddr_reg:x6; val_offset:3092*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3092*FLEN/8, x9, x1, x2) + +inst_1571: +// fs1 == 1 and fe1 == 0x17 and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xdfe0; op2val:0x8001; + valaddr_reg:x6; val_offset:3094*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3094*FLEN/8, x9, x1, x2) + +inst_1572: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x17 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xdc1f; + valaddr_reg:x6; val_offset:3096*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3096*FLEN/8, x9, x1, x2) + +inst_1573: +// fs1 == 1 and fe1 == 0x17 and fm1 == 0x01f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xdc1f; op2val:0x8001; + valaddr_reg:x6; val_offset:3098*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3098*FLEN/8, x9, x1, x2) + +inst_1574: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x17 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xdff0; + valaddr_reg:x6; val_offset:3100*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3100*FLEN/8, x9, x1, x2) + +inst_1575: +// fs1 == 1 and fe1 == 0x17 and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xdff0; op2val:0x8001; + valaddr_reg:x6; val_offset:3102*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3102*FLEN/8, x9, x1, x2) + +inst_1576: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x17 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xdc0f; + valaddr_reg:x6; val_offset:3104*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3104*FLEN/8, x9, x1, x2) + +inst_1577: +// fs1 == 1 and fe1 == 0x17 and fm1 == 0x00f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xdc0f; op2val:0x8001; + valaddr_reg:x6; val_offset:3106*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3106*FLEN/8, x9, x1, x2) + +inst_1578: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x17 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xdff8; + valaddr_reg:x6; val_offset:3108*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3108*FLEN/8, x9, x1, x2) + +inst_1579: +// fs1 == 1 and fe1 == 0x17 and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xdff8; op2val:0x8001; + valaddr_reg:x6; val_offset:3110*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3110*FLEN/8, x9, x1, x2) + +inst_1580: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x17 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xdc07; + valaddr_reg:x6; val_offset:3112*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3112*FLEN/8, x9, x1, x2) + +inst_1581: +// fs1 == 1 and fe1 == 0x17 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xdc07; op2val:0x8001; + valaddr_reg:x6; val_offset:3114*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3114*FLEN/8, x9, x1, x2) + +inst_1582: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x17 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xdffc; + valaddr_reg:x6; val_offset:3116*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3116*FLEN/8, x9, x1, x2) + +inst_1583: +// fs1 == 1 and fe1 == 0x17 and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xdffc; op2val:0x8001; + valaddr_reg:x6; val_offset:3118*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3118*FLEN/8, x9, x1, x2) + +inst_1584: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x17 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xdc03; + valaddr_reg:x6; val_offset:3120*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3120*FLEN/8, x9, x1, x2) + +inst_1585: +// fs1 == 1 and fe1 == 0x17 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xdc03; op2val:0x8001; + valaddr_reg:x6; val_offset:3122*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3122*FLEN/8, x9, x1, x2) + +inst_1586: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x17 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xdffe; + valaddr_reg:x6; val_offset:3124*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3124*FLEN/8, x9, x1, x2) + +inst_1587: +// fs1 == 1 and fe1 == 0x17 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xdffe; op2val:0x8001; + valaddr_reg:x6; val_offset:3126*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3126*FLEN/8, x9, x1, x2) + +inst_1588: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8401; + valaddr_reg:x6; val_offset:3128*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3128*FLEN/8, x9, x1, x2) + +inst_1589: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8401; op2val:0x8001; + valaddr_reg:x6; val_offset:3130*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3130*FLEN/8, x9, x1, x2) + +inst_1590: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8400; + valaddr_reg:x6; val_offset:3132*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3132*FLEN/8, x9, x1, x2) + +inst_1591: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8001; + valaddr_reg:x6; val_offset:3134*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3134*FLEN/8, x9, x1, x2) + +inst_1592: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x87ff; + valaddr_reg:x6; val_offset:3136*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3136*FLEN/8, x9, x1, x2) + +inst_1593: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x87ff; op2val:0x8001; + valaddr_reg:x6; val_offset:3138*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3138*FLEN/8, x9, x1, x2) + +inst_1594: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8600; + valaddr_reg:x6; val_offset:3140*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3140*FLEN/8, x9, x1, x2) + +inst_1595: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8600; op2val:0x8001; + valaddr_reg:x6; val_offset:3142*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3142*FLEN/8, x9, x1, x2) + +inst_1596: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x85ff; + valaddr_reg:x6; val_offset:3144*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3144*FLEN/8, x9, x1, x2) + +inst_1597: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x85ff; op2val:0x8001; + valaddr_reg:x6; val_offset:3146*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3146*FLEN/8, x9, x1, x2) + +inst_1598: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8700; + valaddr_reg:x6; val_offset:3148*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3148*FLEN/8, x9, x1, x2) + +inst_1599: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x300 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8700; op2val:0x8001; + valaddr_reg:x6; val_offset:3150*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3150*FLEN/8, x9, x1, x2) + +inst_1600: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x84ff; + valaddr_reg:x6; val_offset:3152*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3152*FLEN/8, x9, x1, x2) + +inst_1601: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x84ff; op2val:0x8001; + valaddr_reg:x6; val_offset:3154*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3154*FLEN/8, x9, x1, x2) + +inst_1602: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8780; + valaddr_reg:x6; val_offset:3156*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3156*FLEN/8, x9, x1, x2) + +inst_1603: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x380 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8780; op2val:0x8001; + valaddr_reg:x6; val_offset:3158*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3158*FLEN/8, x9, x1, x2) + +inst_1604: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x847f; + valaddr_reg:x6; val_offset:3160*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3160*FLEN/8, x9, x1, x2) + +inst_1605: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x07f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x847f; op2val:0x8001; + valaddr_reg:x6; val_offset:3162*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3162*FLEN/8, x9, x1, x2) + +inst_1606: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x87c0; + valaddr_reg:x6; val_offset:3164*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3164*FLEN/8, x9, x1, x2) + +inst_1607: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x87c0; op2val:0x8001; + valaddr_reg:x6; val_offset:3166*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3166*FLEN/8, x9, x1, x2) + +inst_1608: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x843f; + valaddr_reg:x6; val_offset:3168*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3168*FLEN/8, x9, x1, x2) + +inst_1609: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x843f; op2val:0x8001; + valaddr_reg:x6; val_offset:3170*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3170*FLEN/8, x9, x1, x2) + +inst_1610: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x87e0; + valaddr_reg:x6; val_offset:3172*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3172*FLEN/8, x9, x1, x2) + +inst_1611: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x87e0; op2val:0x8001; + valaddr_reg:x6; val_offset:3174*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3174*FLEN/8, x9, x1, x2) + +inst_1612: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x841f; + valaddr_reg:x6; val_offset:3176*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3176*FLEN/8, x9, x1, x2) + +inst_1613: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x01f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x841f; op2val:0x8001; + valaddr_reg:x6; val_offset:3178*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3178*FLEN/8, x9, x1, x2) + +inst_1614: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x87f0; + valaddr_reg:x6; val_offset:3180*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3180*FLEN/8, x9, x1, x2) + +inst_1615: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x87f0; op2val:0x8001; + valaddr_reg:x6; val_offset:3182*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3182*FLEN/8, x9, x1, x2) + +inst_1616: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x840f; + valaddr_reg:x6; val_offset:3184*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3184*FLEN/8, x9, x1, x2) + +inst_1617: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x00f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x840f; op2val:0x8001; + valaddr_reg:x6; val_offset:3186*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3186*FLEN/8, x9, x1, x2) + +inst_1618: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x87f8; + valaddr_reg:x6; val_offset:3188*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3188*FLEN/8, x9, x1, x2) + +inst_1619: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x87f8; op2val:0x8001; + valaddr_reg:x6; val_offset:3190*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3190*FLEN/8, x9, x1, x2) + +inst_1620: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8407; + valaddr_reg:x6; val_offset:3192*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3192*FLEN/8, x9, x1, x2) + +inst_1621: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8407; op2val:0x8001; + valaddr_reg:x6; val_offset:3194*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3194*FLEN/8, x9, x1, x2) + +inst_1622: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x87fc; + valaddr_reg:x6; val_offset:3196*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3196*FLEN/8, x9, x1, x2) + +inst_1623: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x87fc; op2val:0x8001; + valaddr_reg:x6; val_offset:3198*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3198*FLEN/8, x9, x1, x2) + +inst_1624: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8403; + valaddr_reg:x6; val_offset:3200*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3200*FLEN/8, x9, x1, x2) + +inst_1625: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8403; op2val:0x8001; + valaddr_reg:x6; val_offset:3202*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3202*FLEN/8, x9, x1, x2) + +inst_1626: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x87fe; + valaddr_reg:x6; val_offset:3204*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3204*FLEN/8, x9, x1, x2) + +inst_1627: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x87fe; op2val:0x8001; + valaddr_reg:x6; val_offset:3206*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3206*FLEN/8, x9, x1, x2) + +inst_1628: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8801; + valaddr_reg:x6; val_offset:3208*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3208*FLEN/8, x9, x1, x2) + +inst_1629: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8801; op2val:0x8001; + valaddr_reg:x6; val_offset:3210*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3210*FLEN/8, x9, x1, x2) + +inst_1630: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8800; + valaddr_reg:x6; val_offset:3212*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3212*FLEN/8, x9, x1, x2) + +inst_1631: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8800; op2val:0x8001; + valaddr_reg:x6; val_offset:3214*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3214*FLEN/8, x9, x1, x2) + +inst_1632: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8bff; + valaddr_reg:x6; val_offset:3216*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3216*FLEN/8, x9, x1, x2) + +inst_1633: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8bff; op2val:0x8001; + valaddr_reg:x6; val_offset:3218*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3218*FLEN/8, x9, x1, x2) + +inst_1634: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8a00; + valaddr_reg:x6; val_offset:3220*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3220*FLEN/8, x9, x1, x2) + +inst_1635: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8a00; op2val:0x8001; + valaddr_reg:x6; val_offset:3222*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3222*FLEN/8, x9, x1, x2) + +inst_1636: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x89ff; + valaddr_reg:x6; val_offset:3224*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3224*FLEN/8, x9, x1, x2) + +inst_1637: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x89ff; op2val:0x8001; + valaddr_reg:x6; val_offset:3226*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3226*FLEN/8, x9, x1, x2) + +inst_1638: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8b00; + valaddr_reg:x6; val_offset:3228*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3228*FLEN/8, x9, x1, x2) + +inst_1639: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x300 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8b00; op2val:0x8001; + valaddr_reg:x6; val_offset:3230*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3230*FLEN/8, x9, x1, x2) + +inst_1640: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x88ff; + valaddr_reg:x6; val_offset:3232*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3232*FLEN/8, x9, x1, x2) + +inst_1641: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x88ff; op2val:0x8001; + valaddr_reg:x6; val_offset:3234*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3234*FLEN/8, x9, x1, x2) + +inst_1642: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8b80; + valaddr_reg:x6; val_offset:3236*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3236*FLEN/8, x9, x1, x2) + +inst_1643: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x380 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8b80; op2val:0x8001; + valaddr_reg:x6; val_offset:3238*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3238*FLEN/8, x9, x1, x2) + +inst_1644: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x887f; + valaddr_reg:x6; val_offset:3240*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3240*FLEN/8, x9, x1, x2) + +inst_1645: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x07f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x887f; op2val:0x8001; + valaddr_reg:x6; val_offset:3242*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3242*FLEN/8, x9, x1, x2) + +inst_1646: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8bc0; + valaddr_reg:x6; val_offset:3244*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3244*FLEN/8, x9, x1, x2) + +inst_1647: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8bc0; op2val:0x8001; + valaddr_reg:x6; val_offset:3246*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3246*FLEN/8, x9, x1, x2) + +inst_1648: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x883f; + valaddr_reg:x6; val_offset:3248*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3248*FLEN/8, x9, x1, x2) + +inst_1649: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x883f; op2val:0x8001; + valaddr_reg:x6; val_offset:3250*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3250*FLEN/8, x9, x1, x2) + +inst_1650: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8be0; + valaddr_reg:x6; val_offset:3252*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3252*FLEN/8, x9, x1, x2) + +inst_1651: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8be0; op2val:0x8001; + valaddr_reg:x6; val_offset:3254*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3254*FLEN/8, x9, x1, x2) + +inst_1652: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x881f; + valaddr_reg:x6; val_offset:3256*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3256*FLEN/8, x9, x1, x2) + +inst_1653: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x01f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x881f; op2val:0x8001; + valaddr_reg:x6; val_offset:3258*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3258*FLEN/8, x9, x1, x2) + +inst_1654: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8bf0; + valaddr_reg:x6; val_offset:3260*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3260*FLEN/8, x9, x1, x2) + +inst_1655: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8bf0; op2val:0x8001; + valaddr_reg:x6; val_offset:3262*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3262*FLEN/8, x9, x1, x2) + +inst_1656: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x880f; + valaddr_reg:x6; val_offset:3264*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3264*FLEN/8, x9, x1, x2) + +inst_1657: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x00f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x880f; op2val:0x8001; + valaddr_reg:x6; val_offset:3266*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3266*FLEN/8, x9, x1, x2) + +inst_1658: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8bf8; + valaddr_reg:x6; val_offset:3268*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3268*FLEN/8, x9, x1, x2) + +inst_1659: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8bf8; op2val:0x8001; + valaddr_reg:x6; val_offset:3270*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3270*FLEN/8, x9, x1, x2) + +inst_1660: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8807; + valaddr_reg:x6; val_offset:3272*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3272*FLEN/8, x9, x1, x2) + +inst_1661: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8807; op2val:0x8001; + valaddr_reg:x6; val_offset:3274*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3274*FLEN/8, x9, x1, x2) + +inst_1662: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8bfc; + valaddr_reg:x6; val_offset:3276*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3276*FLEN/8, x9, x1, x2) + +inst_1663: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8bfc; op2val:0x8001; + valaddr_reg:x6; val_offset:3278*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3278*FLEN/8, x9, x1, x2) + +inst_1664: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8803; + valaddr_reg:x6; val_offset:3280*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3280*FLEN/8, x9, x1, x2) + +inst_1665: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8803; op2val:0x8001; + valaddr_reg:x6; val_offset:3282*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3282*FLEN/8, x9, x1, x2) + +inst_1666: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8bfe; + valaddr_reg:x6; val_offset:3284*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3284*FLEN/8, x9, x1, x2) + +inst_1667: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8bfe; op2val:0x8001; + valaddr_reg:x6; val_offset:3286*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3286*FLEN/8, x9, x1, x2) + +inst_1668: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8c01; + valaddr_reg:x6; val_offset:3288*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3288*FLEN/8, x9, x1, x2) + +inst_1669: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8c01; op2val:0x8001; + valaddr_reg:x6; val_offset:3290*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3290*FLEN/8, x9, x1, x2) + +inst_1670: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8c00; + valaddr_reg:x6; val_offset:3292*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3292*FLEN/8, x9, x1, x2) + +inst_1671: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8c00; op2val:0x8001; + valaddr_reg:x6; val_offset:3294*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3294*FLEN/8, x9, x1, x2) + +inst_1672: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8fff; + valaddr_reg:x6; val_offset:3296*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3296*FLEN/8, x9, x1, x2) + +inst_1673: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8fff; op2val:0x8001; + valaddr_reg:x6; val_offset:3298*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3298*FLEN/8, x9, x1, x2) + +inst_1674: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8e00; + valaddr_reg:x6; val_offset:3300*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3300*FLEN/8, x9, x1, x2) + +inst_1675: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8e00; op2val:0x8001; + valaddr_reg:x6; val_offset:3302*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3302*FLEN/8, x9, x1, x2) + +inst_1676: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8dff; + valaddr_reg:x6; val_offset:3304*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3304*FLEN/8, x9, x1, x2) + +inst_1677: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8dff; op2val:0x8001; + valaddr_reg:x6; val_offset:3306*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3306*FLEN/8, x9, x1, x2) + +inst_1678: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8f00; + valaddr_reg:x6; val_offset:3308*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3308*FLEN/8, x9, x1, x2) + +inst_1679: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x300 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8f00; op2val:0x8001; + valaddr_reg:x6; val_offset:3310*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3310*FLEN/8, x9, x1, x2) + +inst_1680: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8cff; + valaddr_reg:x6; val_offset:3312*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3312*FLEN/8, x9, x1, x2) + +inst_1681: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8cff; op2val:0x8001; + valaddr_reg:x6; val_offset:3314*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3314*FLEN/8, x9, x1, x2) + +inst_1682: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8f80; + valaddr_reg:x6; val_offset:3316*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3316*FLEN/8, x9, x1, x2) + +inst_1683: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x380 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8f80; op2val:0x8001; + valaddr_reg:x6; val_offset:3318*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3318*FLEN/8, x9, x1, x2) + +inst_1684: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8c7f; + valaddr_reg:x6; val_offset:3320*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3320*FLEN/8, x9, x1, x2) + +inst_1685: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x07f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8c7f; op2val:0x8001; + valaddr_reg:x6; val_offset:3322*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3322*FLEN/8, x9, x1, x2) + +inst_1686: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8fc0; + valaddr_reg:x6; val_offset:3324*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3324*FLEN/8, x9, x1, x2) + +inst_1687: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8fc0; op2val:0x8001; + valaddr_reg:x6; val_offset:3326*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3326*FLEN/8, x9, x1, x2) + +inst_1688: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8c3f; + valaddr_reg:x6; val_offset:3328*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3328*FLEN/8, x9, x1, x2) + +inst_1689: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8c3f; op2val:0x8001; + valaddr_reg:x6; val_offset:3330*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3330*FLEN/8, x9, x1, x2) + +inst_1690: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8fe0; + valaddr_reg:x6; val_offset:3332*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3332*FLEN/8, x9, x1, x2) + +inst_1691: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8fe0; op2val:0x8001; + valaddr_reg:x6; val_offset:3334*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3334*FLEN/8, x9, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_13) + +inst_1692: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8c1f; + valaddr_reg:x6; val_offset:3336*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3336*FLEN/8, x9, x1, x2) + +inst_1693: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x01f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8c1f; op2val:0x8001; + valaddr_reg:x6; val_offset:3338*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3338*FLEN/8, x9, x1, x2) + +inst_1694: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8ff0; + valaddr_reg:x6; val_offset:3340*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3340*FLEN/8, x9, x1, x2) + +inst_1695: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8ff0; op2val:0x8001; + valaddr_reg:x6; val_offset:3342*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3342*FLEN/8, x9, x1, x2) + +inst_1696: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8c0f; + valaddr_reg:x6; val_offset:3344*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3344*FLEN/8, x9, x1, x2) + +inst_1697: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x00f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8c0f; op2val:0x8001; + valaddr_reg:x6; val_offset:3346*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3346*FLEN/8, x9, x1, x2) + +inst_1698: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8ff8; + valaddr_reg:x6; val_offset:3348*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3348*FLEN/8, x9, x1, x2) + +inst_1699: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8ff8; op2val:0x8001; + valaddr_reg:x6; val_offset:3350*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3350*FLEN/8, x9, x1, x2) + +inst_1700: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8c07; + valaddr_reg:x6; val_offset:3352*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3352*FLEN/8, x9, x1, x2) + +inst_1701: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8c07; op2val:0x8001; + valaddr_reg:x6; val_offset:3354*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3354*FLEN/8, x9, x1, x2) + +inst_1702: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8ffc; + valaddr_reg:x6; val_offset:3356*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3356*FLEN/8, x9, x1, x2) + +inst_1703: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8ffc; op2val:0x8001; + valaddr_reg:x6; val_offset:3358*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3358*FLEN/8, x9, x1, x2) + +inst_1704: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8c03; + valaddr_reg:x6; val_offset:3360*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3360*FLEN/8, x9, x1, x2) + +inst_1705: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8c03; op2val:0x8001; + valaddr_reg:x6; val_offset:3362*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3362*FLEN/8, x9, x1, x2) + +inst_1706: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x8ffe; + valaddr_reg:x6; val_offset:3364*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3364*FLEN/8, x9, x1, x2) + +inst_1707: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8ffe; op2val:0x8001; + valaddr_reg:x6; val_offset:3366*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3366*FLEN/8, x9, x1, x2) + +inst_1708: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x3ff; + valaddr_reg:x6; val_offset:3368*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3368*FLEN/8, x9, x1, x2) + +inst_1709: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x1ff; + valaddr_reg:x6; val_offset:3370*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3370*FLEN/8, x9, x1, x2) + +inst_1710: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1ff; op2val:0x3ff; + valaddr_reg:x6; val_offset:3372*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3372*FLEN/8, x9, x1, x2) + +inst_1711: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x200; + valaddr_reg:x6; val_offset:3374*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3374*FLEN/8, x9, x1, x2) + +inst_1712: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x200; op2val:0x3ff; + valaddr_reg:x6; val_offset:3376*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3376*FLEN/8, x9, x1, x2) + +inst_1713: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xff; + valaddr_reg:x6; val_offset:3378*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3378*FLEN/8, x9, x1, x2) + +inst_1714: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xff; op2val:0x3ff; + valaddr_reg:x6; val_offset:3380*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3380*FLEN/8, x9, x1, x2) + +inst_1715: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x300; + valaddr_reg:x6; val_offset:3382*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3382*FLEN/8, x9, x1, x2) + +inst_1716: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x300 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x300; op2val:0x3ff; + valaddr_reg:x6; val_offset:3384*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3384*FLEN/8, x9, x1, x2) + +inst_1717: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7f; + valaddr_reg:x6; val_offset:3386*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3386*FLEN/8, x9, x1, x2) + +inst_1718: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x07f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7f; op2val:0x3ff; + valaddr_reg:x6; val_offset:3388*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3388*FLEN/8, x9, x1, x2) + +inst_1719: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x380; + valaddr_reg:x6; val_offset:3390*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3390*FLEN/8, x9, x1, x2) + +inst_1720: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x380 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x380; op2val:0x3ff; + valaddr_reg:x6; val_offset:3392*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3392*FLEN/8, x9, x1, x2) + +inst_1721: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x3f; + valaddr_reg:x6; val_offset:3394*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3394*FLEN/8, x9, x1, x2) + +inst_1722: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3f; op2val:0x3ff; + valaddr_reg:x6; val_offset:3396*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3396*FLEN/8, x9, x1, x2) + +inst_1723: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x3c0; + valaddr_reg:x6; val_offset:3398*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3398*FLEN/8, x9, x1, x2) + +inst_1724: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c0; op2val:0x3ff; + valaddr_reg:x6; val_offset:3400*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3400*FLEN/8, x9, x1, x2) + +inst_1725: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x1f; + valaddr_reg:x6; val_offset:3402*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3402*FLEN/8, x9, x1, x2) + +inst_1726: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x01f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1f; op2val:0x3ff; + valaddr_reg:x6; val_offset:3404*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3404*FLEN/8, x9, x1, x2) + +inst_1727: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x3e0; + valaddr_reg:x6; val_offset:3406*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3406*FLEN/8, x9, x1, x2) + +inst_1728: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3e0; op2val:0x3ff; + valaddr_reg:x6; val_offset:3408*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3408*FLEN/8, x9, x1, x2) + +inst_1729: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xf; + valaddr_reg:x6; val_offset:3410*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3410*FLEN/8, x9, x1, x2) + +inst_1730: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf; op2val:0x3ff; + valaddr_reg:x6; val_offset:3412*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3412*FLEN/8, x9, x1, x2) + +inst_1731: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x3f0; + valaddr_reg:x6; val_offset:3414*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3414*FLEN/8, x9, x1, x2) + +inst_1732: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3f0; op2val:0x3ff; + valaddr_reg:x6; val_offset:3416*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3416*FLEN/8, x9, x1, x2) + +inst_1733: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7; + valaddr_reg:x6; val_offset:3418*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3418*FLEN/8, x9, x1, x2) + +inst_1734: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7; op2val:0x3ff; + valaddr_reg:x6; val_offset:3420*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3420*FLEN/8, x9, x1, x2) + +inst_1735: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x3f8; + valaddr_reg:x6; val_offset:3422*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3422*FLEN/8, x9, x1, x2) + +inst_1736: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3f8; op2val:0x3ff; + valaddr_reg:x6; val_offset:3424*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3424*FLEN/8, x9, x1, x2) + +inst_1737: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x3; + valaddr_reg:x6; val_offset:3426*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3426*FLEN/8, x9, x1, x2) + +inst_1738: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x003 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3; op2val:0x3ff; + valaddr_reg:x6; val_offset:3428*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3428*FLEN/8, x9, x1, x2) + +inst_1739: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x3fc; + valaddr_reg:x6; val_offset:3430*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3430*FLEN/8, x9, x1, x2) + +inst_1740: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fc; op2val:0x3ff; + valaddr_reg:x6; val_offset:3432*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3432*FLEN/8, x9, x1, x2) + +inst_1741: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x3fe; + valaddr_reg:x6; val_offset:3434*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3434*FLEN/8, x9, x1, x2) + +inst_1742: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fe; op2val:0x3ff; + valaddr_reg:x6; val_offset:3436*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3436*FLEN/8, x9, x1, x2) + +inst_1743: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1b6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x1b6; + valaddr_reg:x6; val_offset:3438*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3438*FLEN/8, x9, x1, x2) + +inst_1744: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1b6; op2val:0x3ff; + valaddr_reg:x6; val_offset:3440*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3440*FLEN/8, x9, x1, x2) + +inst_1745: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x36d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x36d; + valaddr_reg:x6; val_offset:3442*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3442*FLEN/8, x9, x1, x2) + +inst_1746: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x36d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x36d; op2val:0x3ff; + valaddr_reg:x6; val_offset:3444*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3444*FLEN/8, x9, x1, x2) + +inst_1747: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0cc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xcc; + valaddr_reg:x6; val_offset:3446*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3446*FLEN/8, x9, x1, x2) + +inst_1748: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0cc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xcc; op2val:0x3ff; + valaddr_reg:x6; val_offset:3448*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3448*FLEN/8, x9, x1, x2) + +inst_1749: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x333 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x333; + valaddr_reg:x6; val_offset:3450*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3450*FLEN/8, x9, x1, x2) + +inst_1750: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x333 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x333; op2val:0x3ff; + valaddr_reg:x6; val_offset:3452*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3452*FLEN/8, x9, x1, x2) + +inst_1751: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1dd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x1dd; + valaddr_reg:x6; val_offset:3454*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3454*FLEN/8, x9, x1, x2) + +inst_1752: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1dd; op2val:0x3ff; + valaddr_reg:x6; val_offset:3456*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3456*FLEN/8, x9, x1, x2) + +inst_1753: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x222 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x222; + valaddr_reg:x6; val_offset:3458*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3458*FLEN/8, x9, x1, x2) + +inst_1754: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x222 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x222; op2val:0x3ff; + valaddr_reg:x6; val_offset:3460*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3460*FLEN/8, x9, x1, x2) + +inst_1755: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x124 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x124; + valaddr_reg:x6; val_offset:3462*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3462*FLEN/8, x9, x1, x2) + +inst_1756: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x124 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x124; op2val:0x3ff; + valaddr_reg:x6; val_offset:3464*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3464*FLEN/8, x9, x1, x2) + +inst_1757: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2db and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x2db; + valaddr_reg:x6; val_offset:3466*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3466*FLEN/8, x9, x1, x2) + +inst_1758: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2db; op2val:0x3ff; + valaddr_reg:x6; val_offset:3468*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3468*FLEN/8, x9, x1, x2) + +inst_1759: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x199 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x199; + valaddr_reg:x6; val_offset:3470*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3470*FLEN/8, x9, x1, x2) + +inst_1760: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x199 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x199; op2val:0x3ff; + valaddr_reg:x6; val_offset:3472*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3472*FLEN/8, x9, x1, x2) + +inst_1761: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x266 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x266; + valaddr_reg:x6; val_offset:3474*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3474*FLEN/8, x9, x1, x2) + +inst_1762: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x266 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x266; op2val:0x3ff; + valaddr_reg:x6; val_offset:3476*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3476*FLEN/8, x9, x1, x2) + +inst_1763: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xf3ff; + valaddr_reg:x6; val_offset:3478*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3478*FLEN/8, x9, x1, x2) + +inst_1764: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3ff; op2val:0x3ff; + valaddr_reg:x6; val_offset:3480*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3480*FLEN/8, x9, x1, x2) + +inst_1765: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1c and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xf000; + valaddr_reg:x6; val_offset:3482*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3482*FLEN/8, x9, x1, x2) + +inst_1766: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf000; op2val:0x3ff; + valaddr_reg:x6; val_offset:3484*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3484*FLEN/8, x9, x1, x2) + +inst_1767: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1c and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xf1ff; + valaddr_reg:x6; val_offset:3486*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3486*FLEN/8, x9, x1, x2) + +inst_1768: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf1ff; op2val:0x3ff; + valaddr_reg:x6; val_offset:3488*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3488*FLEN/8, x9, x1, x2) + +inst_1769: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1c and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xf200; + valaddr_reg:x6; val_offset:3490*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3490*FLEN/8, x9, x1, x2) + +inst_1770: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf200; op2val:0x3ff; + valaddr_reg:x6; val_offset:3492*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3492*FLEN/8, x9, x1, x2) + +inst_1771: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xf0ff; + valaddr_reg:x6; val_offset:3494*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3494*FLEN/8, x9, x1, x2) + +inst_1772: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0ff; op2val:0x3ff; + valaddr_reg:x6; val_offset:3496*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3496*FLEN/8, x9, x1, x2) + +inst_1773: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1c and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xf300; + valaddr_reg:x6; val_offset:3498*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3498*FLEN/8, x9, x1, x2) + +inst_1774: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x300 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf300; op2val:0x3ff; + valaddr_reg:x6; val_offset:3500*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3500*FLEN/8, x9, x1, x2) + +inst_1775: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1c and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xf07f; + valaddr_reg:x6; val_offset:3502*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3502*FLEN/8, x9, x1, x2) + +inst_1776: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x07f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf07f; op2val:0x3ff; + valaddr_reg:x6; val_offset:3504*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3504*FLEN/8, x9, x1, x2) + +inst_1777: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1c and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xf380; + valaddr_reg:x6; val_offset:3506*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3506*FLEN/8, x9, x1, x2) + +inst_1778: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x380 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf380; op2val:0x3ff; + valaddr_reg:x6; val_offset:3508*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3508*FLEN/8, x9, x1, x2) + +inst_1779: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1c and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xf03f; + valaddr_reg:x6; val_offset:3510*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3510*FLEN/8, x9, x1, x2) + +inst_1780: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x03f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf03f; op2val:0x3ff; + valaddr_reg:x6; val_offset:3512*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3512*FLEN/8, x9, x1, x2) + +inst_1781: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xf3c0; + valaddr_reg:x6; val_offset:3514*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3514*FLEN/8, x9, x1, x2) + +inst_1782: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3c0; op2val:0x3ff; + valaddr_reg:x6; val_offset:3516*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3516*FLEN/8, x9, x1, x2) + +inst_1783: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1c and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xf01f; + valaddr_reg:x6; val_offset:3518*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3518*FLEN/8, x9, x1, x2) + +inst_1784: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x01f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf01f; op2val:0x3ff; + valaddr_reg:x6; val_offset:3520*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3520*FLEN/8, x9, x1, x2) + +inst_1785: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xf3e0; + valaddr_reg:x6; val_offset:3522*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3522*FLEN/8, x9, x1, x2) + +inst_1786: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3e0; op2val:0x3ff; + valaddr_reg:x6; val_offset:3524*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3524*FLEN/8, x9, x1, x2) + +inst_1787: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1c and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xf00f; + valaddr_reg:x6; val_offset:3526*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3526*FLEN/8, x9, x1, x2) + +inst_1788: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x00f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf00f; op2val:0x3ff; + valaddr_reg:x6; val_offset:3528*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3528*FLEN/8, x9, x1, x2) + +inst_1789: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xf3f0; + valaddr_reg:x6; val_offset:3530*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3530*FLEN/8, x9, x1, x2) + +inst_1790: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3f0; op2val:0x3ff; + valaddr_reg:x6; val_offset:3532*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3532*FLEN/8, x9, x1, x2) + +inst_1791: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1c and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xf007; + valaddr_reg:x6; val_offset:3534*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3534*FLEN/8, x9, x1, x2) + +inst_1792: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x007 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf007; op2val:0x3ff; + valaddr_reg:x6; val_offset:3536*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3536*FLEN/8, x9, x1, x2) + +inst_1793: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xf3f8; + valaddr_reg:x6; val_offset:3538*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3538*FLEN/8, x9, x1, x2) + +inst_1794: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3f8; op2val:0x3ff; + valaddr_reg:x6; val_offset:3540*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3540*FLEN/8, x9, x1, x2) + +inst_1795: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1c and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xf003; + valaddr_reg:x6; val_offset:3542*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3542*FLEN/8, x9, x1, x2) + +inst_1796: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x003 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf003; op2val:0x3ff; + valaddr_reg:x6; val_offset:3544*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3544*FLEN/8, x9, x1, x2) + +inst_1797: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xf3fc; + valaddr_reg:x6; val_offset:3546*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3546*FLEN/8, x9, x1, x2) + +inst_1798: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3fc; op2val:0x3ff; + valaddr_reg:x6; val_offset:3548*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3548*FLEN/8, x9, x1, x2) + +inst_1799: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1c and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xf001; + valaddr_reg:x6; val_offset:3550*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3550*FLEN/8, x9, x1, x2) + +inst_1800: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf001; op2val:0x3ff; + valaddr_reg:x6; val_offset:3552*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3552*FLEN/8, x9, x1, x2) + +inst_1801: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xf3fe; + valaddr_reg:x6; val_offset:3554*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3554*FLEN/8, x9, x1, x2) + +inst_1802: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3fe; op2val:0x3ff; + valaddr_reg:x6; val_offset:3556*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3556*FLEN/8, x9, x1, x2) + +inst_1803: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7ff; + valaddr_reg:x6; val_offset:3558*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3558*FLEN/8, x9, x1, x2) + +inst_1804: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ff; op2val:0x3ff; + valaddr_reg:x6; val_offset:3560*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3560*FLEN/8, x9, x1, x2) + +inst_1805: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x400; + valaddr_reg:x6; val_offset:3562*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3562*FLEN/8, x9, x1, x2) + +inst_1806: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x3ff; + valaddr_reg:x6; val_offset:3564*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3564*FLEN/8, x9, x1, x2) + +inst_1807: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x5ff; + valaddr_reg:x6; val_offset:3566*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3566*FLEN/8, x9, x1, x2) + +inst_1808: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5ff; op2val:0x3ff; + valaddr_reg:x6; val_offset:3568*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3568*FLEN/8, x9, x1, x2) + +inst_1809: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x600; + valaddr_reg:x6; val_offset:3570*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3570*FLEN/8, x9, x1, x2) + +inst_1810: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x600; op2val:0x3ff; + valaddr_reg:x6; val_offset:3572*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3572*FLEN/8, x9, x1, x2) + +inst_1811: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x4ff; + valaddr_reg:x6; val_offset:3574*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3574*FLEN/8, x9, x1, x2) + +inst_1812: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4ff; op2val:0x3ff; + valaddr_reg:x6; val_offset:3576*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3576*FLEN/8, x9, x1, x2) + +inst_1813: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x700; + valaddr_reg:x6; val_offset:3578*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3578*FLEN/8, x9, x1, x2) + +inst_1814: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x300 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x700; op2val:0x3ff; + valaddr_reg:x6; val_offset:3580*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3580*FLEN/8, x9, x1, x2) + +inst_1815: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x47f; + valaddr_reg:x6; val_offset:3582*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3582*FLEN/8, x9, x1, x2) + +inst_1816: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x07f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x47f; op2val:0x3ff; + valaddr_reg:x6; val_offset:3584*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3584*FLEN/8, x9, x1, x2) + +inst_1817: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x780; + valaddr_reg:x6; val_offset:3586*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3586*FLEN/8, x9, x1, x2) + +inst_1818: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x380 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x780; op2val:0x3ff; + valaddr_reg:x6; val_offset:3588*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3588*FLEN/8, x9, x1, x2) + +inst_1819: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x43f; + valaddr_reg:x6; val_offset:3590*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3590*FLEN/8, x9, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_14) + +inst_1820: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x43f; op2val:0x3ff; + valaddr_reg:x6; val_offset:3592*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3592*FLEN/8, x9, x1, x2) + +inst_1821: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7c0; + valaddr_reg:x6; val_offset:3594*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3594*FLEN/8, x9, x1, x2) + +inst_1822: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c0; op2val:0x3ff; + valaddr_reg:x6; val_offset:3596*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3596*FLEN/8, x9, x1, x2) + +inst_1823: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x41f; + valaddr_reg:x6; val_offset:3598*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3598*FLEN/8, x9, x1, x2) + +inst_1824: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x01f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x41f; op2val:0x3ff; + valaddr_reg:x6; val_offset:3600*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3600*FLEN/8, x9, x1, x2) + +inst_1825: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7e0; + valaddr_reg:x6; val_offset:3602*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3602*FLEN/8, x9, x1, x2) + +inst_1826: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e0; op2val:0x3ff; + valaddr_reg:x6; val_offset:3604*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3604*FLEN/8, x9, x1, x2) + +inst_1827: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x40f; + valaddr_reg:x6; val_offset:3606*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3606*FLEN/8, x9, x1, x2) + +inst_1828: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x00f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x40f; op2val:0x3ff; + valaddr_reg:x6; val_offset:3608*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3608*FLEN/8, x9, x1, x2) + +inst_1829: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7f0; + valaddr_reg:x6; val_offset:3610*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3610*FLEN/8, x9, x1, x2) + +inst_1830: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7f0; op2val:0x3ff; + valaddr_reg:x6; val_offset:3612*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3612*FLEN/8, x9, x1, x2) + +inst_1831: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x407; + valaddr_reg:x6; val_offset:3614*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3614*FLEN/8, x9, x1, x2) + +inst_1832: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x407; op2val:0x3ff; + valaddr_reg:x6; val_offset:3616*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3616*FLEN/8, x9, x1, x2) + +inst_1833: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7f8; + valaddr_reg:x6; val_offset:3618*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3618*FLEN/8, x9, x1, x2) + +inst_1834: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7f8; op2val:0x3ff; + valaddr_reg:x6; val_offset:3620*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3620*FLEN/8, x9, x1, x2) + +inst_1835: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x403; + valaddr_reg:x6; val_offset:3622*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3622*FLEN/8, x9, x1, x2) + +inst_1836: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x003 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x403; op2val:0x3ff; + valaddr_reg:x6; val_offset:3624*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3624*FLEN/8, x9, x1, x2) + +inst_1837: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7fc; + valaddr_reg:x6; val_offset:3626*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3626*FLEN/8, x9, x1, x2) + +inst_1838: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7fc; op2val:0x3ff; + valaddr_reg:x6; val_offset:3628*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3628*FLEN/8, x9, x1, x2) + +inst_1839: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x401; + valaddr_reg:x6; val_offset:3630*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3630*FLEN/8, x9, x1, x2) + +inst_1840: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x3ff; + valaddr_reg:x6; val_offset:3632*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3632*FLEN/8, x9, x1, x2) + +inst_1841: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x7fe; + valaddr_reg:x6; val_offset:3634*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3634*FLEN/8, x9, x1, x2) + +inst_1842: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7fe; op2val:0x3ff; + valaddr_reg:x6; val_offset:3636*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3636*FLEN/8, x9, x1, x2) + +inst_1843: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xbff; + valaddr_reg:x6; val_offset:3638*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3638*FLEN/8, x9, x1, x2) + +inst_1844: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbff; op2val:0x3ff; + valaddr_reg:x6; val_offset:3640*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3640*FLEN/8, x9, x1, x2) + +inst_1845: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x02 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x800; + valaddr_reg:x6; val_offset:3642*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3642*FLEN/8, x9, x1, x2) + +inst_1846: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x800; op2val:0x3ff; + valaddr_reg:x6; val_offset:3644*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3644*FLEN/8, x9, x1, x2) + +inst_1847: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x02 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x9ff; + valaddr_reg:x6; val_offset:3646*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3646*FLEN/8, x9, x1, x2) + +inst_1848: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x9ff; op2val:0x3ff; + valaddr_reg:x6; val_offset:3648*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3648*FLEN/8, x9, x1, x2) + +inst_1849: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x02 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xa00; + valaddr_reg:x6; val_offset:3650*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3650*FLEN/8, x9, x1, x2) + +inst_1850: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xa00; op2val:0x3ff; + valaddr_reg:x6; val_offset:3652*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3652*FLEN/8, x9, x1, x2) + +inst_1851: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x02 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x8ff; + valaddr_reg:x6; val_offset:3654*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3654*FLEN/8, x9, x1, x2) + +inst_1852: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8ff; op2val:0x3ff; + valaddr_reg:x6; val_offset:3656*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3656*FLEN/8, x9, x1, x2) + +inst_1853: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x02 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xb00; + valaddr_reg:x6; val_offset:3658*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3658*FLEN/8, x9, x1, x2) + +inst_1854: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x300 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xb00; op2val:0x3ff; + valaddr_reg:x6; val_offset:3660*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3660*FLEN/8, x9, x1, x2) + +inst_1855: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x02 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x87f; + valaddr_reg:x6; val_offset:3662*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3662*FLEN/8, x9, x1, x2) + +inst_1856: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x07f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x87f; op2val:0x3ff; + valaddr_reg:x6; val_offset:3664*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3664*FLEN/8, x9, x1, x2) + +inst_1857: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x02 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xb80; + valaddr_reg:x6; val_offset:3666*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3666*FLEN/8, x9, x1, x2) + +inst_1858: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x380 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xb80; op2val:0x3ff; + valaddr_reg:x6; val_offset:3668*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3668*FLEN/8, x9, x1, x2) + +inst_1859: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x02 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x83f; + valaddr_reg:x6; val_offset:3670*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3670*FLEN/8, x9, x1, x2) + +inst_1860: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83f; op2val:0x3ff; + valaddr_reg:x6; val_offset:3672*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3672*FLEN/8, x9, x1, x2) + +inst_1861: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xbc0; + valaddr_reg:x6; val_offset:3674*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3674*FLEN/8, x9, x1, x2) + +inst_1862: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc0; op2val:0x3ff; + valaddr_reg:x6; val_offset:3676*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3676*FLEN/8, x9, x1, x2) + +inst_1863: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x02 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x81f; + valaddr_reg:x6; val_offset:3678*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3678*FLEN/8, x9, x1, x2) + +inst_1864: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x01f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x81f; op2val:0x3ff; + valaddr_reg:x6; val_offset:3680*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3680*FLEN/8, x9, x1, x2) + +inst_1865: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xbe0; + valaddr_reg:x6; val_offset:3682*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3682*FLEN/8, x9, x1, x2) + +inst_1866: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbe0; op2val:0x3ff; + valaddr_reg:x6; val_offset:3684*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3684*FLEN/8, x9, x1, x2) + +inst_1867: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x02 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x80f; + valaddr_reg:x6; val_offset:3686*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3686*FLEN/8, x9, x1, x2) + +inst_1868: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x00f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x80f; op2val:0x3ff; + valaddr_reg:x6; val_offset:3688*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3688*FLEN/8, x9, x1, x2) + +inst_1869: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xbf0; + valaddr_reg:x6; val_offset:3690*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3690*FLEN/8, x9, x1, x2) + +inst_1870: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbf0; op2val:0x3ff; + valaddr_reg:x6; val_offset:3692*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3692*FLEN/8, x9, x1, x2) + +inst_1871: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x02 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x807; + valaddr_reg:x6; val_offset:3694*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3694*FLEN/8, x9, x1, x2) + +inst_1872: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x807; op2val:0x3ff; + valaddr_reg:x6; val_offset:3696*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3696*FLEN/8, x9, x1, x2) + +inst_1873: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xbf8; + valaddr_reg:x6; val_offset:3698*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3698*FLEN/8, x9, x1, x2) + +inst_1874: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbf8; op2val:0x3ff; + valaddr_reg:x6; val_offset:3700*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3700*FLEN/8, x9, x1, x2) + +inst_1875: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x02 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x803; + valaddr_reg:x6; val_offset:3702*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3702*FLEN/8, x9, x1, x2) + +inst_1876: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x003 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x803; op2val:0x3ff; + valaddr_reg:x6; val_offset:3704*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3704*FLEN/8, x9, x1, x2) + +inst_1877: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xbfc; + valaddr_reg:x6; val_offset:3706*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3706*FLEN/8, x9, x1, x2) + +inst_1878: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbfc; op2val:0x3ff; + valaddr_reg:x6; val_offset:3708*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3708*FLEN/8, x9, x1, x2) + +inst_1879: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x02 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0x801; + valaddr_reg:x6; val_offset:3710*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3710*FLEN/8, x9, x1, x2) + +inst_1880: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x801; op2val:0x3ff; + valaddr_reg:x6; val_offset:3712*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3712*FLEN/8, x9, x1, x2) + +inst_1881: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xbfe; + valaddr_reg:x6; val_offset:3714*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3714*FLEN/8, x9, x1, x2) + +inst_1882: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbfe; op2val:0x3ff; + valaddr_reg:x6; val_offset:3716*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3716*FLEN/8, x9, x1, x2) + +inst_1883: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xfff; + valaddr_reg:x6; val_offset:3718*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3718*FLEN/8, x9, x1, x2) + +inst_1884: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfff; op2val:0x3ff; + valaddr_reg:x6; val_offset:3720*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3720*FLEN/8, x9, x1, x2) + +inst_1885: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x03 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xc00; + valaddr_reg:x6; val_offset:3722*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3722*FLEN/8, x9, x1, x2) + +inst_1886: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc00; op2val:0x3ff; + valaddr_reg:x6; val_offset:3724*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3724*FLEN/8, x9, x1, x2) + +inst_1887: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x03 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xdff; + valaddr_reg:x6; val_offset:3726*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3726*FLEN/8, x9, x1, x2) + +inst_1888: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xdff; op2val:0x3ff; + valaddr_reg:x6; val_offset:3728*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3728*FLEN/8, x9, x1, x2) + +inst_1889: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x03 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xe00; + valaddr_reg:x6; val_offset:3730*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3730*FLEN/8, x9, x1, x2) + +inst_1890: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x200 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xe00; op2val:0x3ff; + valaddr_reg:x6; val_offset:3732*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3732*FLEN/8, x9, x1, x2) + +inst_1891: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x03 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xcff; + valaddr_reg:x6; val_offset:3734*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3734*FLEN/8, x9, x1, x2) + +inst_1892: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xcff; op2val:0x3ff; + valaddr_reg:x6; val_offset:3736*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3736*FLEN/8, x9, x1, x2) + +inst_1893: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x03 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xf00; + valaddr_reg:x6; val_offset:3738*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3738*FLEN/8, x9, x1, x2) + +inst_1894: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x300 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf00; op2val:0x3ff; + valaddr_reg:x6; val_offset:3740*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3740*FLEN/8, x9, x1, x2) + +inst_1895: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x03 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xc7f; + valaddr_reg:x6; val_offset:3742*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3742*FLEN/8, x9, x1, x2) + +inst_1896: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x07f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc7f; op2val:0x3ff; + valaddr_reg:x6; val_offset:3744*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3744*FLEN/8, x9, x1, x2) + +inst_1897: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x03 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xf80; + valaddr_reg:x6; val_offset:3746*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3746*FLEN/8, x9, x1, x2) + +inst_1898: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x380 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf80; op2val:0x3ff; + valaddr_reg:x6; val_offset:3748*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3748*FLEN/8, x9, x1, x2) + +inst_1899: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x03 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xc3f; + valaddr_reg:x6; val_offset:3750*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3750*FLEN/8, x9, x1, x2) + +inst_1900: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc3f; op2val:0x3ff; + valaddr_reg:x6; val_offset:3752*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3752*FLEN/8, x9, x1, x2) + +inst_1901: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xfc0; + valaddr_reg:x6; val_offset:3754*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3754*FLEN/8, x9, x1, x2) + +inst_1902: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc0; op2val:0x3ff; + valaddr_reg:x6; val_offset:3756*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3756*FLEN/8, x9, x1, x2) + +inst_1903: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x03 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xc1f; + valaddr_reg:x6; val_offset:3758*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3758*FLEN/8, x9, x1, x2) + +inst_1904: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x01f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc1f; op2val:0x3ff; + valaddr_reg:x6; val_offset:3760*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3760*FLEN/8, x9, x1, x2) + +inst_1905: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xfe0; + valaddr_reg:x6; val_offset:3762*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3762*FLEN/8, x9, x1, x2) + +inst_1906: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe0; op2val:0x3ff; + valaddr_reg:x6; val_offset:3764*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3764*FLEN/8, x9, x1, x2) + +inst_1907: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x03 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xc0f; + valaddr_reg:x6; val_offset:3766*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3766*FLEN/8, x9, x1, x2) + +inst_1908: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x00f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc0f; op2val:0x3ff; + valaddr_reg:x6; val_offset:3768*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3768*FLEN/8, x9, x1, x2) + +inst_1909: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xff0; + valaddr_reg:x6; val_offset:3770*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3770*FLEN/8, x9, x1, x2) + +inst_1910: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xff0; op2val:0x3ff; + valaddr_reg:x6; val_offset:3772*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3772*FLEN/8, x9, x1, x2) + +inst_1911: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x03 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xc07; + valaddr_reg:x6; val_offset:3774*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3774*FLEN/8, x9, x1, x2) + +inst_1912: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc07; op2val:0x3ff; + valaddr_reg:x6; val_offset:3776*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3776*FLEN/8, x9, x1, x2) + +inst_1913: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xff8; + valaddr_reg:x6; val_offset:3778*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3778*FLEN/8, x9, x1, x2) + +inst_1914: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xff8; op2val:0x3ff; + valaddr_reg:x6; val_offset:3780*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3780*FLEN/8, x9, x1, x2) + +inst_1915: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x03 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xc03; + valaddr_reg:x6; val_offset:3782*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3782*FLEN/8, x9, x1, x2) + +inst_1916: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x003 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc03; op2val:0x3ff; + valaddr_reg:x6; val_offset:3784*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3784*FLEN/8, x9, x1, x2) + +inst_1917: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xffc; + valaddr_reg:x6; val_offset:3786*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3786*FLEN/8, x9, x1, x2) + +inst_1918: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xffc; op2val:0x3ff; + valaddr_reg:x6; val_offset:3788*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3788*FLEN/8, x9, x1, x2) + +inst_1919: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x03 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xc01; + valaddr_reg:x6; val_offset:3790*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3790*FLEN/8, x9, x1, x2) + +inst_1920: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc01; op2val:0x3ff; + valaddr_reg:x6; val_offset:3792*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3792*FLEN/8, x9, x1, x2) + +inst_1921: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ff; op2val:0xffe; + valaddr_reg:x6; val_offset:3794*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3794*FLEN/8, x9, x1, x2) + +inst_1922: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xffe; op2val:0x3ff; + valaddr_reg:x6; val_offset:3796*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3796*FLEN/8, x9, x1, x2) + +inst_1923: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x83ff; + valaddr_reg:x6; val_offset:3798*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3798*FLEN/8, x9, x1, x2) + +inst_1924: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x81ff; + valaddr_reg:x6; val_offset:3800*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3800*FLEN/8, x9, x1, x2) + +inst_1925: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x81ff; op2val:0x83ff; + valaddr_reg:x6; val_offset:3802*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3802*FLEN/8, x9, x1, x2) + +inst_1926: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8200; + valaddr_reg:x6; val_offset:3804*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3804*FLEN/8, x9, x1, x2) + +inst_1927: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8200; op2val:0x83ff; + valaddr_reg:x6; val_offset:3806*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3806*FLEN/8, x9, x1, x2) + +inst_1928: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x80ff; + valaddr_reg:x6; val_offset:3808*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3808*FLEN/8, x9, x1, x2) + +inst_1929: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x80ff; op2val:0x83ff; + valaddr_reg:x6; val_offset:3810*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3810*FLEN/8, x9, x1, x2) + +inst_1930: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8300; + valaddr_reg:x6; val_offset:3812*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3812*FLEN/8, x9, x1, x2) + +inst_1931: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x300 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8300; op2val:0x83ff; + valaddr_reg:x6; val_offset:3814*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3814*FLEN/8, x9, x1, x2) + +inst_1932: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x807f; + valaddr_reg:x6; val_offset:3816*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3816*FLEN/8, x9, x1, x2) + +inst_1933: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x07f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x807f; op2val:0x83ff; + valaddr_reg:x6; val_offset:3818*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3818*FLEN/8, x9, x1, x2) + +inst_1934: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8380; + valaddr_reg:x6; val_offset:3820*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3820*FLEN/8, x9, x1, x2) + +inst_1935: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x380 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8380; op2val:0x83ff; + valaddr_reg:x6; val_offset:3822*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3822*FLEN/8, x9, x1, x2) + +inst_1936: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x803f; + valaddr_reg:x6; val_offset:3824*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3824*FLEN/8, x9, x1, x2) + +inst_1937: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x803f; op2val:0x83ff; + valaddr_reg:x6; val_offset:3826*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3826*FLEN/8, x9, x1, x2) + +inst_1938: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x83c0; + valaddr_reg:x6; val_offset:3828*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3828*FLEN/8, x9, x1, x2) + +inst_1939: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83c0; op2val:0x83ff; + valaddr_reg:x6; val_offset:3830*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3830*FLEN/8, x9, x1, x2) + +inst_1940: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x801f; + valaddr_reg:x6; val_offset:3832*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3832*FLEN/8, x9, x1, x2) + +inst_1941: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x01f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x801f; op2val:0x83ff; + valaddr_reg:x6; val_offset:3834*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3834*FLEN/8, x9, x1, x2) + +inst_1942: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x83e0; + valaddr_reg:x6; val_offset:3836*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3836*FLEN/8, x9, x1, x2) + +inst_1943: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83e0; op2val:0x83ff; + valaddr_reg:x6; val_offset:3838*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3838*FLEN/8, x9, x1, x2) + +inst_1944: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x800f; + valaddr_reg:x6; val_offset:3840*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3840*FLEN/8, x9, x1, x2) + +inst_1945: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x00f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x800f; op2val:0x83ff; + valaddr_reg:x6; val_offset:3842*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3842*FLEN/8, x9, x1, x2) + +inst_1946: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x83f0; + valaddr_reg:x6; val_offset:3844*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3844*FLEN/8, x9, x1, x2) + +inst_1947: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83f0; op2val:0x83ff; + valaddr_reg:x6; val_offset:3846*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3846*FLEN/8, x9, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_15) + +inst_1948: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8007; + valaddr_reg:x6; val_offset:3848*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3848*FLEN/8, x9, x1, x2) + +inst_1949: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8007; op2val:0x83ff; + valaddr_reg:x6; val_offset:3850*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3850*FLEN/8, x9, x1, x2) + +inst_1950: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x83f8; + valaddr_reg:x6; val_offset:3852*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3852*FLEN/8, x9, x1, x2) + +inst_1951: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83f8; op2val:0x83ff; + valaddr_reg:x6; val_offset:3854*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3854*FLEN/8, x9, x1, x2) + +inst_1952: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8003; + valaddr_reg:x6; val_offset:3856*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3856*FLEN/8, x9, x1, x2) + +inst_1953: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8003; op2val:0x83ff; + valaddr_reg:x6; val_offset:3858*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3858*FLEN/8, x9, x1, x2) + +inst_1954: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x83fc; + valaddr_reg:x6; val_offset:3860*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3860*FLEN/8, x9, x1, x2) + +inst_1955: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fc; op2val:0x83ff; + valaddr_reg:x6; val_offset:3862*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3862*FLEN/8, x9, x1, x2) + +inst_1956: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x83fe; + valaddr_reg:x6; val_offset:3864*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3864*FLEN/8, x9, x1, x2) + +inst_1957: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x83ff; + valaddr_reg:x6; val_offset:3866*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3866*FLEN/8, x9, x1, x2) + +inst_1958: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1b6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x81b6; + valaddr_reg:x6; val_offset:3868*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3868*FLEN/8, x9, x1, x2) + +inst_1959: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x81b6; op2val:0x83ff; + valaddr_reg:x6; val_offset:3870*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3870*FLEN/8, x9, x1, x2) + +inst_1960: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x36d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x836d; + valaddr_reg:x6; val_offset:3872*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3872*FLEN/8, x9, x1, x2) + +inst_1961: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x36d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x836d; op2val:0x83ff; + valaddr_reg:x6; val_offset:3874*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3874*FLEN/8, x9, x1, x2) + +inst_1962: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0cc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x80cc; + valaddr_reg:x6; val_offset:3876*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3876*FLEN/8, x9, x1, x2) + +inst_1963: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0cc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x80cc; op2val:0x83ff; + valaddr_reg:x6; val_offset:3878*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3878*FLEN/8, x9, x1, x2) + +inst_1964: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x333 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8333; + valaddr_reg:x6; val_offset:3880*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3880*FLEN/8, x9, x1, x2) + +inst_1965: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x333 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8333; op2val:0x83ff; + valaddr_reg:x6; val_offset:3882*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3882*FLEN/8, x9, x1, x2) + +inst_1966: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1dd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x81dd; + valaddr_reg:x6; val_offset:3884*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3884*FLEN/8, x9, x1, x2) + +inst_1967: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1dd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x81dd; op2val:0x83ff; + valaddr_reg:x6; val_offset:3886*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3886*FLEN/8, x9, x1, x2) + +inst_1968: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x222 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8222; + valaddr_reg:x6; val_offset:3888*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3888*FLEN/8, x9, x1, x2) + +inst_1969: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x222 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8222; op2val:0x83ff; + valaddr_reg:x6; val_offset:3890*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3890*FLEN/8, x9, x1, x2) + +inst_1970: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x124 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8124; + valaddr_reg:x6; val_offset:3892*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3892*FLEN/8, x9, x1, x2) + +inst_1971: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x124 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8124; op2val:0x83ff; + valaddr_reg:x6; val_offset:3894*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3894*FLEN/8, x9, x1, x2) + +inst_1972: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2db and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x82db; + valaddr_reg:x6; val_offset:3896*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3896*FLEN/8, x9, x1, x2) + +inst_1973: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x82db; op2val:0x83ff; + valaddr_reg:x6; val_offset:3898*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3898*FLEN/8, x9, x1, x2) + +inst_1974: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x199 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8199; + valaddr_reg:x6; val_offset:3900*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3900*FLEN/8, x9, x1, x2) + +inst_1975: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x199 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8199; op2val:0x83ff; + valaddr_reg:x6; val_offset:3902*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3902*FLEN/8, x9, x1, x2) + +inst_1976: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x266 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8266; + valaddr_reg:x6; val_offset:3904*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3904*FLEN/8, x9, x1, x2) + +inst_1977: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x266 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8266; op2val:0x83ff; + valaddr_reg:x6; val_offset:3906*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3906*FLEN/8, x9, x1, x2) + +inst_1978: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0a and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xabff; + valaddr_reg:x6; val_offset:3908*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3908*FLEN/8, x9, x1, x2) + +inst_1979: +// fs1 == 1 and fe1 == 0x0a and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xabff; op2val:0x83ff; + valaddr_reg:x6; val_offset:3910*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3910*FLEN/8, x9, x1, x2) + +inst_1980: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0a and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xa800; + valaddr_reg:x6; val_offset:3912*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3912*FLEN/8, x9, x1, x2) + +inst_1981: +// fs1 == 1 and fe1 == 0x0a and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xa800; op2val:0x83ff; + valaddr_reg:x6; val_offset:3914*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3914*FLEN/8, x9, x1, x2) + +inst_1982: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0a and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xa9ff; + valaddr_reg:x6; val_offset:3916*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3916*FLEN/8, x9, x1, x2) + +inst_1983: +// fs1 == 1 and fe1 == 0x0a and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xa9ff; op2val:0x83ff; + valaddr_reg:x6; val_offset:3918*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3918*FLEN/8, x9, x1, x2) + +inst_1984: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0a and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xaa00; + valaddr_reg:x6; val_offset:3920*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3920*FLEN/8, x9, x1, x2) + +inst_1985: +// fs1 == 1 and fe1 == 0x0a and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xaa00; op2val:0x83ff; + valaddr_reg:x6; val_offset:3922*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3922*FLEN/8, x9, x1, x2) + +inst_1986: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0a and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xa8ff; + valaddr_reg:x6; val_offset:3924*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3924*FLEN/8, x9, x1, x2) + +inst_1987: +// fs1 == 1 and fe1 == 0x0a and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xa8ff; op2val:0x83ff; + valaddr_reg:x6; val_offset:3926*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3926*FLEN/8, x9, x1, x2) + +inst_1988: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0a and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xab00; + valaddr_reg:x6; val_offset:3928*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3928*FLEN/8, x9, x1, x2) + +inst_1989: +// fs1 == 1 and fe1 == 0x0a and fm1 == 0x300 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xab00; op2val:0x83ff; + valaddr_reg:x6; val_offset:3930*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3930*FLEN/8, x9, x1, x2) + +inst_1990: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0a and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xa87f; + valaddr_reg:x6; val_offset:3932*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3932*FLEN/8, x9, x1, x2) + +inst_1991: +// fs1 == 1 and fe1 == 0x0a and fm1 == 0x07f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xa87f; op2val:0x83ff; + valaddr_reg:x6; val_offset:3934*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3934*FLEN/8, x9, x1, x2) + +inst_1992: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0a and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xab80; + valaddr_reg:x6; val_offset:3936*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3936*FLEN/8, x9, x1, x2) + +inst_1993: +// fs1 == 1 and fe1 == 0x0a and fm1 == 0x380 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xab80; op2val:0x83ff; + valaddr_reg:x6; val_offset:3938*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3938*FLEN/8, x9, x1, x2) + +inst_1994: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0a and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xa83f; + valaddr_reg:x6; val_offset:3940*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3940*FLEN/8, x9, x1, x2) + +inst_1995: +// fs1 == 1 and fe1 == 0x0a and fm1 == 0x03f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xa83f; op2val:0x83ff; + valaddr_reg:x6; val_offset:3942*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3942*FLEN/8, x9, x1, x2) + +inst_1996: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0a and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xabc0; + valaddr_reg:x6; val_offset:3944*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3944*FLEN/8, x9, x1, x2) + +inst_1997: +// fs1 == 1 and fe1 == 0x0a and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xabc0; op2val:0x83ff; + valaddr_reg:x6; val_offset:3946*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3946*FLEN/8, x9, x1, x2) + +inst_1998: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0a and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xa81f; + valaddr_reg:x6; val_offset:3948*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3948*FLEN/8, x9, x1, x2) + +inst_1999: +// fs1 == 1 and fe1 == 0x0a and fm1 == 0x01f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xa81f; op2val:0x83ff; + valaddr_reg:x6; val_offset:3950*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3950*FLEN/8, x9, x1, x2) + +inst_2000: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0a and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xabe0; + valaddr_reg:x6; val_offset:3952*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3952*FLEN/8, x9, x1, x2) + +inst_2001: +// fs1 == 1 and fe1 == 0x0a and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xabe0; op2val:0x83ff; + valaddr_reg:x6; val_offset:3954*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3954*FLEN/8, x9, x1, x2) + +inst_2002: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0a and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xa80f; + valaddr_reg:x6; val_offset:3956*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3956*FLEN/8, x9, x1, x2) + +inst_2003: +// fs1 == 1 and fe1 == 0x0a and fm1 == 0x00f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xa80f; op2val:0x83ff; + valaddr_reg:x6; val_offset:3958*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3958*FLEN/8, x9, x1, x2) + +inst_2004: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0a and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xabf0; + valaddr_reg:x6; val_offset:3960*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3960*FLEN/8, x9, x1, x2) + +inst_2005: +// fs1 == 1 and fe1 == 0x0a and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xabf0; op2val:0x83ff; + valaddr_reg:x6; val_offset:3962*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3962*FLEN/8, x9, x1, x2) + +inst_2006: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0a and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xa807; + valaddr_reg:x6; val_offset:3964*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3964*FLEN/8, x9, x1, x2) + +inst_2007: +// fs1 == 1 and fe1 == 0x0a and fm1 == 0x007 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xa807; op2val:0x83ff; + valaddr_reg:x6; val_offset:3966*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3966*FLEN/8, x9, x1, x2) + +inst_2008: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0a and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xabf8; + valaddr_reg:x6; val_offset:3968*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3968*FLEN/8, x9, x1, x2) + +inst_2009: +// fs1 == 1 and fe1 == 0x0a and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xabf8; op2val:0x83ff; + valaddr_reg:x6; val_offset:3970*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3970*FLEN/8, x9, x1, x2) + +inst_2010: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0a and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xa803; + valaddr_reg:x6; val_offset:3972*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3972*FLEN/8, x9, x1, x2) + +inst_2011: +// fs1 == 1 and fe1 == 0x0a and fm1 == 0x003 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xa803; op2val:0x83ff; + valaddr_reg:x6; val_offset:3974*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3974*FLEN/8, x9, x1, x2) + +inst_2012: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0a and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xabfc; + valaddr_reg:x6; val_offset:3976*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3976*FLEN/8, x9, x1, x2) + +inst_2013: +// fs1 == 1 and fe1 == 0x0a and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xabfc; op2val:0x83ff; + valaddr_reg:x6; val_offset:3978*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3978*FLEN/8, x9, x1, x2) + +inst_2014: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0a and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xa801; + valaddr_reg:x6; val_offset:3980*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3980*FLEN/8, x9, x1, x2) + +inst_2015: +// fs1 == 1 and fe1 == 0x0a and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xa801; op2val:0x83ff; + valaddr_reg:x6; val_offset:3982*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3982*FLEN/8, x9, x1, x2) + +inst_2016: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0a and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xabfe; + valaddr_reg:x6; val_offset:3984*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3984*FLEN/8, x9, x1, x2) + +inst_2017: +// fs1 == 1 and fe1 == 0x0a and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xabfe; op2val:0x83ff; + valaddr_reg:x6; val_offset:3986*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3986*FLEN/8, x9, x1, x2) + +inst_2018: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x87ff; + valaddr_reg:x6; val_offset:3988*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3988*FLEN/8, x9, x1, x2) + +inst_2019: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x87ff; op2val:0x83ff; + valaddr_reg:x6; val_offset:3990*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3990*FLEN/8, x9, x1, x2) + +inst_2020: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8400; + valaddr_reg:x6; val_offset:3992*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3992*FLEN/8, x9, x1, x2) + +inst_2021: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x83ff; + valaddr_reg:x6; val_offset:3994*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3994*FLEN/8, x9, x1, x2) + +inst_2022: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x85ff; + valaddr_reg:x6; val_offset:3996*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3996*FLEN/8, x9, x1, x2) + +inst_2023: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x85ff; op2val:0x83ff; + valaddr_reg:x6; val_offset:3998*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 3998*FLEN/8, x9, x1, x2) + +inst_2024: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8600; + valaddr_reg:x6; val_offset:4000*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4000*FLEN/8, x9, x1, x2) + +inst_2025: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8600; op2val:0x83ff; + valaddr_reg:x6; val_offset:4002*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4002*FLEN/8, x9, x1, x2) + +inst_2026: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x84ff; + valaddr_reg:x6; val_offset:4004*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4004*FLEN/8, x9, x1, x2) + +inst_2027: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x84ff; op2val:0x83ff; + valaddr_reg:x6; val_offset:4006*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4006*FLEN/8, x9, x1, x2) + +inst_2028: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8700; + valaddr_reg:x6; val_offset:4008*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4008*FLEN/8, x9, x1, x2) + +inst_2029: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x300 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8700; op2val:0x83ff; + valaddr_reg:x6; val_offset:4010*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4010*FLEN/8, x9, x1, x2) + +inst_2030: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x847f; + valaddr_reg:x6; val_offset:4012*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4012*FLEN/8, x9, x1, x2) + +inst_2031: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x07f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x847f; op2val:0x83ff; + valaddr_reg:x6; val_offset:4014*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4014*FLEN/8, x9, x1, x2) + +inst_2032: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8780; + valaddr_reg:x6; val_offset:4016*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4016*FLEN/8, x9, x1, x2) + +inst_2033: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x380 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8780; op2val:0x83ff; + valaddr_reg:x6; val_offset:4018*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4018*FLEN/8, x9, x1, x2) + +inst_2034: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x843f; + valaddr_reg:x6; val_offset:4020*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4020*FLEN/8, x9, x1, x2) + +inst_2035: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x843f; op2val:0x83ff; + valaddr_reg:x6; val_offset:4022*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4022*FLEN/8, x9, x1, x2) + +inst_2036: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x87c0; + valaddr_reg:x6; val_offset:4024*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4024*FLEN/8, x9, x1, x2) + +inst_2037: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x87c0; op2val:0x83ff; + valaddr_reg:x6; val_offset:4026*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4026*FLEN/8, x9, x1, x2) + +inst_2038: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x841f; + valaddr_reg:x6; val_offset:4028*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4028*FLEN/8, x9, x1, x2) + +inst_2039: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x01f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x841f; op2val:0x83ff; + valaddr_reg:x6; val_offset:4030*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4030*FLEN/8, x9, x1, x2) + +inst_2040: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x87e0; + valaddr_reg:x6; val_offset:4032*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4032*FLEN/8, x9, x1, x2) + +inst_2041: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x87e0; op2val:0x83ff; + valaddr_reg:x6; val_offset:4034*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4034*FLEN/8, x9, x1, x2) + +inst_2042: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x840f; + valaddr_reg:x6; val_offset:4036*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4036*FLEN/8, x9, x1, x2) + +inst_2043: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x00f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x840f; op2val:0x83ff; + valaddr_reg:x6; val_offset:4038*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4038*FLEN/8, x9, x1, x2) + +inst_2044: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x87f0; + valaddr_reg:x6; val_offset:4040*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4040*FLEN/8, x9, x1, x2) + +inst_2045: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x87f0; op2val:0x83ff; + valaddr_reg:x6; val_offset:4042*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4042*FLEN/8, x9, x1, x2) + +inst_2046: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8407; + valaddr_reg:x6; val_offset:4044*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4044*FLEN/8, x9, x1, x2) + +inst_2047: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8407; op2val:0x83ff; + valaddr_reg:x6; val_offset:4046*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4046*FLEN/8, x9, x1, x2) + +inst_2048: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x87f8; + valaddr_reg:x6; val_offset:4048*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4048*FLEN/8, x9, x1, x2) + +inst_2049: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x87f8; op2val:0x83ff; + valaddr_reg:x6; val_offset:4050*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4050*FLEN/8, x9, x1, x2) + +inst_2050: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8403; + valaddr_reg:x6; val_offset:4052*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4052*FLEN/8, x9, x1, x2) + +inst_2051: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8403; op2val:0x83ff; + valaddr_reg:x6; val_offset:4054*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4054*FLEN/8, x9, x1, x2) + +inst_2052: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x87fc; + valaddr_reg:x6; val_offset:4056*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4056*FLEN/8, x9, x1, x2) + +inst_2053: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x87fc; op2val:0x83ff; + valaddr_reg:x6; val_offset:4058*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4058*FLEN/8, x9, x1, x2) + +inst_2054: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8401; + valaddr_reg:x6; val_offset:4060*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4060*FLEN/8, x9, x1, x2) + +inst_2055: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8401; op2val:0x83ff; + valaddr_reg:x6; val_offset:4062*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4062*FLEN/8, x9, x1, x2) + +inst_2056: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x87fe; + valaddr_reg:x6; val_offset:4064*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4064*FLEN/8, x9, x1, x2) + +inst_2057: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x87fe; op2val:0x83ff; + valaddr_reg:x6; val_offset:4066*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4066*FLEN/8, x9, x1, x2) + +inst_2058: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x02 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8bff; + valaddr_reg:x6; val_offset:4068*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4068*FLEN/8, x9, x1, x2) + +inst_2059: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8bff; op2val:0x83ff; + valaddr_reg:x6; val_offset:4070*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4070*FLEN/8, x9, x1, x2) + +inst_2060: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x02 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8800; + valaddr_reg:x6; val_offset:4072*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4072*FLEN/8, x9, x1, x2) + +inst_2061: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8800; op2val:0x83ff; + valaddr_reg:x6; val_offset:4074*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4074*FLEN/8, x9, x1, x2) + +inst_2062: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x89ff; + valaddr_reg:x6; val_offset:4076*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4076*FLEN/8, x9, x1, x2) + +inst_2063: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x89ff; op2val:0x83ff; + valaddr_reg:x6; val_offset:4078*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4078*FLEN/8, x9, x1, x2) + +inst_2064: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x02 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8a00; + valaddr_reg:x6; val_offset:4080*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4080*FLEN/8, x9, x1, x2) + +inst_2065: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8a00; op2val:0x83ff; + valaddr_reg:x6; val_offset:4082*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4082*FLEN/8, x9, x1, x2) + +inst_2066: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x02 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x88ff; + valaddr_reg:x6; val_offset:4084*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4084*FLEN/8, x9, x1, x2) + +inst_2067: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x88ff; op2val:0x83ff; + valaddr_reg:x6; val_offset:4086*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4086*FLEN/8, x9, x1, x2) + +inst_2068: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x02 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8b00; + valaddr_reg:x6; val_offset:4088*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4088*FLEN/8, x9, x1, x2) + +inst_2069: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x300 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8b00; op2val:0x83ff; + valaddr_reg:x6; val_offset:4090*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4090*FLEN/8, x9, x1, x2) + +inst_2070: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x02 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x887f; + valaddr_reg:x6; val_offset:4092*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4092*FLEN/8, x9, x1, x2) + +inst_2071: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x07f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x887f; op2val:0x83ff; + valaddr_reg:x6; val_offset:4094*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4094*FLEN/8, x9, x1, x2) + +inst_2072: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x02 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8b80; + valaddr_reg:x6; val_offset:4096*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4096*FLEN/8, x9, x1, x2) + +inst_2073: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x380 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8b80; op2val:0x83ff; + valaddr_reg:x6; val_offset:4098*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4098*FLEN/8, x9, x1, x2) + +inst_2074: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x02 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x883f; + valaddr_reg:x6; val_offset:4100*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4100*FLEN/8, x9, x1, x2) + +inst_2075: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x883f; op2val:0x83ff; + valaddr_reg:x6; val_offset:4102*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4102*FLEN/8, x9, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_16) + +inst_2076: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x02 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8bc0; + valaddr_reg:x6; val_offset:4104*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4104*FLEN/8, x9, x1, x2) + +inst_2077: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8bc0; op2val:0x83ff; + valaddr_reg:x6; val_offset:4106*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4106*FLEN/8, x9, x1, x2) + +inst_2078: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x02 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x881f; + valaddr_reg:x6; val_offset:4108*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4108*FLEN/8, x9, x1, x2) + +inst_2079: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x01f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x881f; op2val:0x83ff; + valaddr_reg:x6; val_offset:4110*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4110*FLEN/8, x9, x1, x2) + +inst_2080: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x02 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8be0; + valaddr_reg:x6; val_offset:4112*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4112*FLEN/8, x9, x1, x2) + +inst_2081: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8be0; op2val:0x83ff; + valaddr_reg:x6; val_offset:4114*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4114*FLEN/8, x9, x1, x2) + +inst_2082: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x02 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x880f; + valaddr_reg:x6; val_offset:4116*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4116*FLEN/8, x9, x1, x2) + +inst_2083: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x00f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x880f; op2val:0x83ff; + valaddr_reg:x6; val_offset:4118*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4118*FLEN/8, x9, x1, x2) + +inst_2084: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x02 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8bf0; + valaddr_reg:x6; val_offset:4120*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4120*FLEN/8, x9, x1, x2) + +inst_2085: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8bf0; op2val:0x83ff; + valaddr_reg:x6; val_offset:4122*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4122*FLEN/8, x9, x1, x2) + +inst_2086: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x02 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8807; + valaddr_reg:x6; val_offset:4124*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4124*FLEN/8, x9, x1, x2) + +inst_2087: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8807; op2val:0x83ff; + valaddr_reg:x6; val_offset:4126*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4126*FLEN/8, x9, x1, x2) + +inst_2088: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x02 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8bf8; + valaddr_reg:x6; val_offset:4128*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4128*FLEN/8, x9, x1, x2) + +inst_2089: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8bf8; op2val:0x83ff; + valaddr_reg:x6; val_offset:4130*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4130*FLEN/8, x9, x1, x2) + +inst_2090: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x02 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8803; + valaddr_reg:x6; val_offset:4132*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4132*FLEN/8, x9, x1, x2) + +inst_2091: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8803; op2val:0x83ff; + valaddr_reg:x6; val_offset:4134*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4134*FLEN/8, x9, x1, x2) + +inst_2092: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x02 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8bfc; + valaddr_reg:x6; val_offset:4136*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4136*FLEN/8, x9, x1, x2) + +inst_2093: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8bfc; op2val:0x83ff; + valaddr_reg:x6; val_offset:4138*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4138*FLEN/8, x9, x1, x2) + +inst_2094: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x02 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8801; + valaddr_reg:x6; val_offset:4140*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4140*FLEN/8, x9, x1, x2) + +inst_2095: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8801; op2val:0x83ff; + valaddr_reg:x6; val_offset:4142*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4142*FLEN/8, x9, x1, x2) + +inst_2096: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x02 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8bfe; + valaddr_reg:x6; val_offset:4144*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4144*FLEN/8, x9, x1, x2) + +inst_2097: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8bfe; op2val:0x83ff; + valaddr_reg:x6; val_offset:4146*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4146*FLEN/8, x9, x1, x2) + +inst_2098: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x03 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8fff; + valaddr_reg:x6; val_offset:4148*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4148*FLEN/8, x9, x1, x2) + +inst_2099: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8fff; op2val:0x83ff; + valaddr_reg:x6; val_offset:4150*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4150*FLEN/8, x9, x1, x2) + +inst_2100: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x03 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8c00; + valaddr_reg:x6; val_offset:4152*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4152*FLEN/8, x9, x1, x2) + +inst_2101: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8c00; op2val:0x83ff; + valaddr_reg:x6; val_offset:4154*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4154*FLEN/8, x9, x1, x2) + +inst_2102: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x03 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8dff; + valaddr_reg:x6; val_offset:4156*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4156*FLEN/8, x9, x1, x2) + +inst_2103: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8dff; op2val:0x83ff; + valaddr_reg:x6; val_offset:4158*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4158*FLEN/8, x9, x1, x2) + +inst_2104: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x03 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8e00; + valaddr_reg:x6; val_offset:4160*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4160*FLEN/8, x9, x1, x2) + +inst_2105: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x200 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8e00; op2val:0x83ff; + valaddr_reg:x6; val_offset:4162*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4162*FLEN/8, x9, x1, x2) + +inst_2106: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x03 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8cff; + valaddr_reg:x6; val_offset:4164*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4164*FLEN/8, x9, x1, x2) + +inst_2107: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8cff; op2val:0x83ff; + valaddr_reg:x6; val_offset:4166*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4166*FLEN/8, x9, x1, x2) + +inst_2108: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x03 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8f00; + valaddr_reg:x6; val_offset:4168*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4168*FLEN/8, x9, x1, x2) + +inst_2109: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x300 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8f00; op2val:0x83ff; + valaddr_reg:x6; val_offset:4170*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4170*FLEN/8, x9, x1, x2) + +inst_2110: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x03 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8c7f; + valaddr_reg:x6; val_offset:4172*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4172*FLEN/8, x9, x1, x2) + +inst_2111: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x07f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8c7f; op2val:0x83ff; + valaddr_reg:x6; val_offset:4174*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4174*FLEN/8, x9, x1, x2) + +inst_2112: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x03 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8f80; + valaddr_reg:x6; val_offset:4176*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4176*FLEN/8, x9, x1, x2) + +inst_2113: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x380 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8f80; op2val:0x83ff; + valaddr_reg:x6; val_offset:4178*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4178*FLEN/8, x9, x1, x2) + +inst_2114: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x03 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8c3f; + valaddr_reg:x6; val_offset:4180*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4180*FLEN/8, x9, x1, x2) + +inst_2115: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8c3f; op2val:0x83ff; + valaddr_reg:x6; val_offset:4182*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4182*FLEN/8, x9, x1, x2) + +inst_2116: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x03 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8fc0; + valaddr_reg:x6; val_offset:4184*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4184*FLEN/8, x9, x1, x2) + +inst_2117: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8fc0; op2val:0x83ff; + valaddr_reg:x6; val_offset:4186*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4186*FLEN/8, x9, x1, x2) + +inst_2118: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x03 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8c1f; + valaddr_reg:x6; val_offset:4188*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4188*FLEN/8, x9, x1, x2) + +inst_2119: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x01f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8c1f; op2val:0x83ff; + valaddr_reg:x6; val_offset:4190*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4190*FLEN/8, x9, x1, x2) + +inst_2120: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x03 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8fe0; + valaddr_reg:x6; val_offset:4192*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4192*FLEN/8, x9, x1, x2) + +inst_2121: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8fe0; op2val:0x83ff; + valaddr_reg:x6; val_offset:4194*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4194*FLEN/8, x9, x1, x2) + +inst_2122: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x03 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8c0f; + valaddr_reg:x6; val_offset:4196*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4196*FLEN/8, x9, x1, x2) + +inst_2123: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x00f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8c0f; op2val:0x83ff; + valaddr_reg:x6; val_offset:4198*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4198*FLEN/8, x9, x1, x2) + +inst_2124: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x03 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8ff0; + valaddr_reg:x6; val_offset:4200*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4200*FLEN/8, x9, x1, x2) + +inst_2125: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8ff0; op2val:0x83ff; + valaddr_reg:x6; val_offset:4202*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4202*FLEN/8, x9, x1, x2) + +inst_2126: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x03 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8c07; + valaddr_reg:x6; val_offset:4204*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4204*FLEN/8, x9, x1, x2) + +inst_2127: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8c07; op2val:0x83ff; + valaddr_reg:x6; val_offset:4206*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4206*FLEN/8, x9, x1, x2) + +inst_2128: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x03 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8ff8; + valaddr_reg:x6; val_offset:4208*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4208*FLEN/8, x9, x1, x2) + +inst_2129: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8ff8; op2val:0x83ff; + valaddr_reg:x6; val_offset:4210*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4210*FLEN/8, x9, x1, x2) + +inst_2130: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x03 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8c03; + valaddr_reg:x6; val_offset:4212*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4212*FLEN/8, x9, x1, x2) + +inst_2131: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8c03; op2val:0x83ff; + valaddr_reg:x6; val_offset:4214*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4214*FLEN/8, x9, x1, x2) + +inst_2132: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x03 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8ffc; + valaddr_reg:x6; val_offset:4216*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4216*FLEN/8, x9, x1, x2) + +inst_2133: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8ffc; op2val:0x83ff; + valaddr_reg:x6; val_offset:4218*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4218*FLEN/8, x9, x1, x2) + +inst_2134: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x03 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8c01; + valaddr_reg:x6; val_offset:4220*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4220*FLEN/8, x9, x1, x2) + +inst_2135: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8c01; op2val:0x83ff; + valaddr_reg:x6; val_offset:4222*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4222*FLEN/8, x9, x1, x2) + +inst_2136: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x03 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x8ffe; + valaddr_reg:x6; val_offset:4224*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4224*FLEN/8, x9, x1, x2) + +inst_2137: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8ffe; op2val:0x83ff; + valaddr_reg:x6; val_offset:4226*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4226*FLEN/8, x9, x1, x2) + +inst_2138: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x200; + valaddr_reg:x6; val_offset:4228*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4228*FLEN/8, x9, x1, x2) + +inst_2139: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x200; op2val:0x400; + valaddr_reg:x6; val_offset:4230*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4230*FLEN/8, x9, x1, x2) + +inst_2140: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x1ff; + valaddr_reg:x6; val_offset:4232*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4232*FLEN/8, x9, x1, x2) + +inst_2141: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1ff; op2val:0x400; + valaddr_reg:x6; val_offset:4234*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4234*FLEN/8, x9, x1, x2) + +inst_2142: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x300; + valaddr_reg:x6; val_offset:4236*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4236*FLEN/8, x9, x1, x2) + +inst_2143: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x300 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x300; op2val:0x400; + valaddr_reg:x6; val_offset:4238*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4238*FLEN/8, x9, x1, x2) + +inst_2144: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xff; + valaddr_reg:x6; val_offset:4240*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4240*FLEN/8, x9, x1, x2) + +inst_2145: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xff; op2val:0x400; + valaddr_reg:x6; val_offset:4242*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4242*FLEN/8, x9, x1, x2) + +inst_2146: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x380; + valaddr_reg:x6; val_offset:4244*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4244*FLEN/8, x9, x1, x2) + +inst_2147: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x380 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x380; op2val:0x400; + valaddr_reg:x6; val_offset:4246*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4246*FLEN/8, x9, x1, x2) + +inst_2148: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7f; + valaddr_reg:x6; val_offset:4248*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4248*FLEN/8, x9, x1, x2) + +inst_2149: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x07f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7f; op2val:0x400; + valaddr_reg:x6; val_offset:4250*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4250*FLEN/8, x9, x1, x2) + +inst_2150: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x3c0; + valaddr_reg:x6; val_offset:4252*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4252*FLEN/8, x9, x1, x2) + +inst_2151: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c0; op2val:0x400; + valaddr_reg:x6; val_offset:4254*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4254*FLEN/8, x9, x1, x2) + +inst_2152: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x3f; + valaddr_reg:x6; val_offset:4256*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4256*FLEN/8, x9, x1, x2) + +inst_2153: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3f; op2val:0x400; + valaddr_reg:x6; val_offset:4258*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4258*FLEN/8, x9, x1, x2) + +inst_2154: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x3e0; + valaddr_reg:x6; val_offset:4260*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4260*FLEN/8, x9, x1, x2) + +inst_2155: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3e0; op2val:0x400; + valaddr_reg:x6; val_offset:4262*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4262*FLEN/8, x9, x1, x2) + +inst_2156: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x1f; + valaddr_reg:x6; val_offset:4264*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4264*FLEN/8, x9, x1, x2) + +inst_2157: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x01f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1f; op2val:0x400; + valaddr_reg:x6; val_offset:4266*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4266*FLEN/8, x9, x1, x2) + +inst_2158: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x3f0; + valaddr_reg:x6; val_offset:4268*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4268*FLEN/8, x9, x1, x2) + +inst_2159: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3f0; op2val:0x400; + valaddr_reg:x6; val_offset:4270*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4270*FLEN/8, x9, x1, x2) + +inst_2160: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xf; + valaddr_reg:x6; val_offset:4272*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4272*FLEN/8, x9, x1, x2) + +inst_2161: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf; op2val:0x400; + valaddr_reg:x6; val_offset:4274*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4274*FLEN/8, x9, x1, x2) + +inst_2162: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x3f8; + valaddr_reg:x6; val_offset:4276*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4276*FLEN/8, x9, x1, x2) + +inst_2163: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3f8; op2val:0x400; + valaddr_reg:x6; val_offset:4278*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4278*FLEN/8, x9, x1, x2) + +inst_2164: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7; + valaddr_reg:x6; val_offset:4280*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4280*FLEN/8, x9, x1, x2) + +inst_2165: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7; op2val:0x400; + valaddr_reg:x6; val_offset:4282*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4282*FLEN/8, x9, x1, x2) + +inst_2166: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x3fc; + valaddr_reg:x6; val_offset:4284*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4284*FLEN/8, x9, x1, x2) + +inst_2167: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fc; op2val:0x400; + valaddr_reg:x6; val_offset:4286*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4286*FLEN/8, x9, x1, x2) + +inst_2168: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x3; + valaddr_reg:x6; val_offset:4288*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4288*FLEN/8, x9, x1, x2) + +inst_2169: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x003 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3; op2val:0x400; + valaddr_reg:x6; val_offset:4290*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4290*FLEN/8, x9, x1, x2) + +inst_2170: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x3fe; + valaddr_reg:x6; val_offset:4292*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4292*FLEN/8, x9, x1, x2) + +inst_2171: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3fe; op2val:0x400; + valaddr_reg:x6; val_offset:4294*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4294*FLEN/8, x9, x1, x2) + +inst_2172: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7fe; + valaddr_reg:x6; val_offset:4296*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4296*FLEN/8, x9, x1, x2) + +inst_2173: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7fe; op2val:0x400; + valaddr_reg:x6; val_offset:4298*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4298*FLEN/8, x9, x1, x2) + +inst_2174: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x401; + valaddr_reg:x6; val_offset:4300*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4300*FLEN/8, x9, x1, x2) + +inst_2175: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x401; op2val:0x400; + valaddr_reg:x6; val_offset:4302*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4302*FLEN/8, x9, x1, x2) + +inst_2176: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1b6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x5b6; + valaddr_reg:x6; val_offset:4304*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4304*FLEN/8, x9, x1, x2) + +inst_2177: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x1b6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5b6; op2val:0x400; + valaddr_reg:x6; val_offset:4306*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4306*FLEN/8, x9, x1, x2) + +inst_2178: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x36d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x76d; + valaddr_reg:x6; val_offset:4308*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4308*FLEN/8, x9, x1, x2) + +inst_2179: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x36d and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x76d; op2val:0x400; + valaddr_reg:x6; val_offset:4310*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4310*FLEN/8, x9, x1, x2) + +inst_2180: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0cc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x4cc; + valaddr_reg:x6; val_offset:4312*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4312*FLEN/8, x9, x1, x2) + +inst_2181: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x0cc and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4cc; op2val:0x400; + valaddr_reg:x6; val_offset:4314*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4314*FLEN/8, x9, x1, x2) + +inst_2182: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x333 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x733; + valaddr_reg:x6; val_offset:4316*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4316*FLEN/8, x9, x1, x2) + +inst_2183: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x333 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x733; op2val:0x400; + valaddr_reg:x6; val_offset:4318*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4318*FLEN/8, x9, x1, x2) + +inst_2184: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1dd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x5dd; + valaddr_reg:x6; val_offset:4320*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4320*FLEN/8, x9, x1, x2) + +inst_2185: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x1dd and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5dd; op2val:0x400; + valaddr_reg:x6; val_offset:4322*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4322*FLEN/8, x9, x1, x2) + +inst_2186: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x222 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x622; + valaddr_reg:x6; val_offset:4324*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4324*FLEN/8, x9, x1, x2) + +inst_2187: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x222 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x622; op2val:0x400; + valaddr_reg:x6; val_offset:4326*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4326*FLEN/8, x9, x1, x2) + +inst_2188: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x124 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x524; + valaddr_reg:x6; val_offset:4328*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4328*FLEN/8, x9, x1, x2) + +inst_2189: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x124 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x524; op2val:0x400; + valaddr_reg:x6; val_offset:4330*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4330*FLEN/8, x9, x1, x2) + +inst_2190: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x2db and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x6db; + valaddr_reg:x6; val_offset:4332*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4332*FLEN/8, x9, x1, x2) + +inst_2191: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x2db and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6db; op2val:0x400; + valaddr_reg:x6; val_offset:4334*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4334*FLEN/8, x9, x1, x2) + +inst_2192: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x199 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x599; + valaddr_reg:x6; val_offset:4336*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4336*FLEN/8, x9, x1, x2) + +inst_2193: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x199 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x599; op2val:0x400; + valaddr_reg:x6; val_offset:4338*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4338*FLEN/8, x9, x1, x2) + +inst_2194: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x266 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x666; + valaddr_reg:x6; val_offset:4340*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4340*FLEN/8, x9, x1, x2) + +inst_2195: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x266 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x666; op2val:0x400; + valaddr_reg:x6; val_offset:4342*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4342*FLEN/8, x9, x1, x2) + +inst_2196: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x9800; + valaddr_reg:x6; val_offset:4344*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4344*FLEN/8, x9, x1, x2) + +inst_2197: +// fs1 == 1 and fe1 == 0x06 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x9800; op2val:0x400; + valaddr_reg:x6; val_offset:4346*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4346*FLEN/8, x9, x1, x2) + +inst_2198: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x9bff; + valaddr_reg:x6; val_offset:4348*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4348*FLEN/8, x9, x1, x2) + +inst_2199: +// fs1 == 1 and fe1 == 0x06 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x9bff; op2val:0x400; + valaddr_reg:x6; val_offset:4350*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4350*FLEN/8, x9, x1, x2) + +inst_2200: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x9a00; + valaddr_reg:x6; val_offset:4352*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4352*FLEN/8, x9, x1, x2) + +inst_2201: +// fs1 == 1 and fe1 == 0x06 and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x9a00; op2val:0x400; + valaddr_reg:x6; val_offset:4354*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4354*FLEN/8, x9, x1, x2) + +inst_2202: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x99ff; + valaddr_reg:x6; val_offset:4356*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4356*FLEN/8, x9, x1, x2) + +inst_2203: +// fs1 == 1 and fe1 == 0x06 and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x99ff; op2val:0x400; + valaddr_reg:x6; val_offset:4358*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4358*FLEN/8, x9, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_17) + +inst_2204: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x9b00; + valaddr_reg:x6; val_offset:4360*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4360*FLEN/8, x9, x1, x2) + +inst_2205: +// fs1 == 1 and fe1 == 0x06 and fm1 == 0x300 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x9b00; op2val:0x400; + valaddr_reg:x6; val_offset:4362*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4362*FLEN/8, x9, x1, x2) + +inst_2206: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x98ff; + valaddr_reg:x6; val_offset:4364*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4364*FLEN/8, x9, x1, x2) + +inst_2207: +// fs1 == 1 and fe1 == 0x06 and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x98ff; op2val:0x400; + valaddr_reg:x6; val_offset:4366*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4366*FLEN/8, x9, x1, x2) + +inst_2208: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x9b80; + valaddr_reg:x6; val_offset:4368*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4368*FLEN/8, x9, x1, x2) + +inst_2209: +// fs1 == 1 and fe1 == 0x06 and fm1 == 0x380 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x9b80; op2val:0x400; + valaddr_reg:x6; val_offset:4370*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4370*FLEN/8, x9, x1, x2) + +inst_2210: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x987f; + valaddr_reg:x6; val_offset:4372*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4372*FLEN/8, x9, x1, x2) + +inst_2211: +// fs1 == 1 and fe1 == 0x06 and fm1 == 0x07f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x987f; op2val:0x400; + valaddr_reg:x6; val_offset:4374*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4374*FLEN/8, x9, x1, x2) + +inst_2212: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x9bc0; + valaddr_reg:x6; val_offset:4376*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4376*FLEN/8, x9, x1, x2) + +inst_2213: +// fs1 == 1 and fe1 == 0x06 and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x9bc0; op2val:0x400; + valaddr_reg:x6; val_offset:4378*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4378*FLEN/8, x9, x1, x2) + +inst_2214: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x983f; + valaddr_reg:x6; val_offset:4380*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4380*FLEN/8, x9, x1, x2) + +inst_2215: +// fs1 == 1 and fe1 == 0x06 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x983f; op2val:0x400; + valaddr_reg:x6; val_offset:4382*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4382*FLEN/8, x9, x1, x2) + +inst_2216: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x9be0; + valaddr_reg:x6; val_offset:4384*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4384*FLEN/8, x9, x1, x2) + +inst_2217: +// fs1 == 1 and fe1 == 0x06 and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x9be0; op2val:0x400; + valaddr_reg:x6; val_offset:4386*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4386*FLEN/8, x9, x1, x2) + +inst_2218: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x981f; + valaddr_reg:x6; val_offset:4388*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4388*FLEN/8, x9, x1, x2) + +inst_2219: +// fs1 == 1 and fe1 == 0x06 and fm1 == 0x01f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x981f; op2val:0x400; + valaddr_reg:x6; val_offset:4390*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4390*FLEN/8, x9, x1, x2) + +inst_2220: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x9bf0; + valaddr_reg:x6; val_offset:4392*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4392*FLEN/8, x9, x1, x2) + +inst_2221: +// fs1 == 1 and fe1 == 0x06 and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x9bf0; op2val:0x400; + valaddr_reg:x6; val_offset:4394*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4394*FLEN/8, x9, x1, x2) + +inst_2222: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x980f; + valaddr_reg:x6; val_offset:4396*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4396*FLEN/8, x9, x1, x2) + +inst_2223: +// fs1 == 1 and fe1 == 0x06 and fm1 == 0x00f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x980f; op2val:0x400; + valaddr_reg:x6; val_offset:4398*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4398*FLEN/8, x9, x1, x2) + +inst_2224: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x9bf8; + valaddr_reg:x6; val_offset:4400*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4400*FLEN/8, x9, x1, x2) + +inst_2225: +// fs1 == 1 and fe1 == 0x06 and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x9bf8; op2val:0x400; + valaddr_reg:x6; val_offset:4402*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4402*FLEN/8, x9, x1, x2) + +inst_2226: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x9807; + valaddr_reg:x6; val_offset:4404*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4404*FLEN/8, x9, x1, x2) + +inst_2227: +// fs1 == 1 and fe1 == 0x06 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x9807; op2val:0x400; + valaddr_reg:x6; val_offset:4406*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4406*FLEN/8, x9, x1, x2) + +inst_2228: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x9bfc; + valaddr_reg:x6; val_offset:4408*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4408*FLEN/8, x9, x1, x2) + +inst_2229: +// fs1 == 1 and fe1 == 0x06 and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x9bfc; op2val:0x400; + valaddr_reg:x6; val_offset:4410*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4410*FLEN/8, x9, x1, x2) + +inst_2230: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x9803; + valaddr_reg:x6; val_offset:4412*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4412*FLEN/8, x9, x1, x2) + +inst_2231: +// fs1 == 1 and fe1 == 0x06 and fm1 == 0x003 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x9803; op2val:0x400; + valaddr_reg:x6; val_offset:4414*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4414*FLEN/8, x9, x1, x2) + +inst_2232: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x9bfe; + valaddr_reg:x6; val_offset:4416*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4416*FLEN/8, x9, x1, x2) + +inst_2233: +// fs1 == 1 and fe1 == 0x06 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x9bfe; op2val:0x400; + valaddr_reg:x6; val_offset:4418*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4418*FLEN/8, x9, x1, x2) + +inst_2234: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x9801; + valaddr_reg:x6; val_offset:4420*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4420*FLEN/8, x9, x1, x2) + +inst_2235: +// fs1 == 1 and fe1 == 0x06 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x9801; op2val:0x400; + valaddr_reg:x6; val_offset:4422*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4422*FLEN/8, x9, x1, x2) + +inst_2236: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x400; + valaddr_reg:x6; val_offset:4424*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4424*FLEN/8, x9, x1, x2) + +inst_2237: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7ff; + valaddr_reg:x6; val_offset:4426*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4426*FLEN/8, x9, x1, x2) + +inst_2238: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ff; op2val:0x400; + valaddr_reg:x6; val_offset:4428*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4428*FLEN/8, x9, x1, x2) + +inst_2239: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x600; + valaddr_reg:x6; val_offset:4430*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4430*FLEN/8, x9, x1, x2) + +inst_2240: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x600; op2val:0x400; + valaddr_reg:x6; val_offset:4432*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4432*FLEN/8, x9, x1, x2) + +inst_2241: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x5ff; + valaddr_reg:x6; val_offset:4434*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4434*FLEN/8, x9, x1, x2) + +inst_2242: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5ff; op2val:0x400; + valaddr_reg:x6; val_offset:4436*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4436*FLEN/8, x9, x1, x2) + +inst_2243: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x700; + valaddr_reg:x6; val_offset:4438*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4438*FLEN/8, x9, x1, x2) + +inst_2244: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x300 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x700; op2val:0x400; + valaddr_reg:x6; val_offset:4440*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4440*FLEN/8, x9, x1, x2) + +inst_2245: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x4ff; + valaddr_reg:x6; val_offset:4442*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4442*FLEN/8, x9, x1, x2) + +inst_2246: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4ff; op2val:0x400; + valaddr_reg:x6; val_offset:4444*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4444*FLEN/8, x9, x1, x2) + +inst_2247: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x780; + valaddr_reg:x6; val_offset:4446*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4446*FLEN/8, x9, x1, x2) + +inst_2248: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x380 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x780; op2val:0x400; + valaddr_reg:x6; val_offset:4448*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4448*FLEN/8, x9, x1, x2) + +inst_2249: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x47f; + valaddr_reg:x6; val_offset:4450*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4450*FLEN/8, x9, x1, x2) + +inst_2250: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x07f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x47f; op2val:0x400; + valaddr_reg:x6; val_offset:4452*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4452*FLEN/8, x9, x1, x2) + +inst_2251: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7c0; + valaddr_reg:x6; val_offset:4454*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4454*FLEN/8, x9, x1, x2) + +inst_2252: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7c0; op2val:0x400; + valaddr_reg:x6; val_offset:4456*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4456*FLEN/8, x9, x1, x2) + +inst_2253: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x43f; + valaddr_reg:x6; val_offset:4458*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4458*FLEN/8, x9, x1, x2) + +inst_2254: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x43f; op2val:0x400; + valaddr_reg:x6; val_offset:4460*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4460*FLEN/8, x9, x1, x2) + +inst_2255: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7e0; + valaddr_reg:x6; val_offset:4462*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4462*FLEN/8, x9, x1, x2) + +inst_2256: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7e0; op2val:0x400; + valaddr_reg:x6; val_offset:4464*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4464*FLEN/8, x9, x1, x2) + +inst_2257: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x41f; + valaddr_reg:x6; val_offset:4466*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4466*FLEN/8, x9, x1, x2) + +inst_2258: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x01f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x41f; op2val:0x400; + valaddr_reg:x6; val_offset:4468*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4468*FLEN/8, x9, x1, x2) + +inst_2259: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7f0; + valaddr_reg:x6; val_offset:4470*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4470*FLEN/8, x9, x1, x2) + +inst_2260: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7f0; op2val:0x400; + valaddr_reg:x6; val_offset:4472*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4472*FLEN/8, x9, x1, x2) + +inst_2261: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x40f; + valaddr_reg:x6; val_offset:4474*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4474*FLEN/8, x9, x1, x2) + +inst_2262: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x00f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x40f; op2val:0x400; + valaddr_reg:x6; val_offset:4476*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4476*FLEN/8, x9, x1, x2) + +inst_2263: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7f8; + valaddr_reg:x6; val_offset:4478*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4478*FLEN/8, x9, x1, x2) + +inst_2264: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7f8; op2val:0x400; + valaddr_reg:x6; val_offset:4480*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4480*FLEN/8, x9, x1, x2) + +inst_2265: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x407; + valaddr_reg:x6; val_offset:4482*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4482*FLEN/8, x9, x1, x2) + +inst_2266: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x407; op2val:0x400; + valaddr_reg:x6; val_offset:4484*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4484*FLEN/8, x9, x1, x2) + +inst_2267: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x7fc; + valaddr_reg:x6; val_offset:4486*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4486*FLEN/8, x9, x1, x2) + +inst_2268: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7fc; op2val:0x400; + valaddr_reg:x6; val_offset:4488*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4488*FLEN/8, x9, x1, x2) + +inst_2269: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x403; + valaddr_reg:x6; val_offset:4490*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4490*FLEN/8, x9, x1, x2) + +inst_2270: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x003 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x403; op2val:0x400; + valaddr_reg:x6; val_offset:4492*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4492*FLEN/8, x9, x1, x2) + +inst_2271: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x800; + valaddr_reg:x6; val_offset:4494*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4494*FLEN/8, x9, x1, x2) + +inst_2272: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x800; op2val:0x400; + valaddr_reg:x6; val_offset:4496*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4496*FLEN/8, x9, x1, x2) + +inst_2273: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xbff; + valaddr_reg:x6; val_offset:4498*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4498*FLEN/8, x9, x1, x2) + +inst_2274: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbff; op2val:0x400; + valaddr_reg:x6; val_offset:4500*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4500*FLEN/8, x9, x1, x2) + +inst_2275: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xa00; + valaddr_reg:x6; val_offset:4502*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4502*FLEN/8, x9, x1, x2) + +inst_2276: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xa00; op2val:0x400; + valaddr_reg:x6; val_offset:4504*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4504*FLEN/8, x9, x1, x2) + +inst_2277: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x9ff; + valaddr_reg:x6; val_offset:4506*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4506*FLEN/8, x9, x1, x2) + +inst_2278: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x9ff; op2val:0x400; + valaddr_reg:x6; val_offset:4508*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4508*FLEN/8, x9, x1, x2) + +inst_2279: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xb00; + valaddr_reg:x6; val_offset:4510*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4510*FLEN/8, x9, x1, x2) + +inst_2280: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x300 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xb00; op2val:0x400; + valaddr_reg:x6; val_offset:4512*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4512*FLEN/8, x9, x1, x2) + +inst_2281: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x8ff; + valaddr_reg:x6; val_offset:4514*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4514*FLEN/8, x9, x1, x2) + +inst_2282: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8ff; op2val:0x400; + valaddr_reg:x6; val_offset:4516*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4516*FLEN/8, x9, x1, x2) + +inst_2283: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xb80; + valaddr_reg:x6; val_offset:4518*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4518*FLEN/8, x9, x1, x2) + +inst_2284: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x380 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xb80; op2val:0x400; + valaddr_reg:x6; val_offset:4520*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4520*FLEN/8, x9, x1, x2) + +inst_2285: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x87f; + valaddr_reg:x6; val_offset:4522*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4522*FLEN/8, x9, x1, x2) + +inst_2286: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x07f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x87f; op2val:0x400; + valaddr_reg:x6; val_offset:4524*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4524*FLEN/8, x9, x1, x2) + +inst_2287: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xbc0; + valaddr_reg:x6; val_offset:4526*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4526*FLEN/8, x9, x1, x2) + +inst_2288: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc0; op2val:0x400; + valaddr_reg:x6; val_offset:4528*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4528*FLEN/8, x9, x1, x2) + +inst_2289: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x83f; + valaddr_reg:x6; val_offset:4530*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4530*FLEN/8, x9, x1, x2) + +inst_2290: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83f; op2val:0x400; + valaddr_reg:x6; val_offset:4532*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4532*FLEN/8, x9, x1, x2) + +inst_2291: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xbe0; + valaddr_reg:x6; val_offset:4534*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4534*FLEN/8, x9, x1, x2) + +inst_2292: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbe0; op2val:0x400; + valaddr_reg:x6; val_offset:4536*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4536*FLEN/8, x9, x1, x2) + +inst_2293: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x81f; + valaddr_reg:x6; val_offset:4538*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4538*FLEN/8, x9, x1, x2) + +inst_2294: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x01f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x81f; op2val:0x400; + valaddr_reg:x6; val_offset:4540*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4540*FLEN/8, x9, x1, x2) + +inst_2295: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xbf0; + valaddr_reg:x6; val_offset:4542*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4542*FLEN/8, x9, x1, x2) + +inst_2296: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbf0; op2val:0x400; + valaddr_reg:x6; val_offset:4544*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4544*FLEN/8, x9, x1, x2) + +inst_2297: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x80f; + valaddr_reg:x6; val_offset:4546*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4546*FLEN/8, x9, x1, x2) + +inst_2298: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x00f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x80f; op2val:0x400; + valaddr_reg:x6; val_offset:4548*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4548*FLEN/8, x9, x1, x2) + +inst_2299: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xbf8; + valaddr_reg:x6; val_offset:4550*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4550*FLEN/8, x9, x1, x2) + +inst_2300: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbf8; op2val:0x400; + valaddr_reg:x6; val_offset:4552*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4552*FLEN/8, x9, x1, x2) + +inst_2301: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x807; + valaddr_reg:x6; val_offset:4554*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4554*FLEN/8, x9, x1, x2) + +inst_2302: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x807; op2val:0x400; + valaddr_reg:x6; val_offset:4556*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4556*FLEN/8, x9, x1, x2) + +inst_2303: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xbfc; + valaddr_reg:x6; val_offset:4558*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4558*FLEN/8, x9, x1, x2) + +inst_2304: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbfc; op2val:0x400; + valaddr_reg:x6; val_offset:4560*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4560*FLEN/8, x9, x1, x2) + +inst_2305: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x803; + valaddr_reg:x6; val_offset:4562*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4562*FLEN/8, x9, x1, x2) + +inst_2306: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x003 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x803; op2val:0x400; + valaddr_reg:x6; val_offset:4564*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4564*FLEN/8, x9, x1, x2) + +inst_2307: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xbfe; + valaddr_reg:x6; val_offset:4566*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4566*FLEN/8, x9, x1, x2) + +inst_2308: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbfe; op2val:0x400; + valaddr_reg:x6; val_offset:4568*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4568*FLEN/8, x9, x1, x2) + +inst_2309: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x801; + valaddr_reg:x6; val_offset:4570*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4570*FLEN/8, x9, x1, x2) + +inst_2310: +// fs1 == 0 and fe1 == 0x02 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x801; op2val:0x400; + valaddr_reg:x6; val_offset:4572*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4572*FLEN/8, x9, x1, x2) + +inst_2311: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xc00; + valaddr_reg:x6; val_offset:4574*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4574*FLEN/8, x9, x1, x2) + +inst_2312: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc00; op2val:0x400; + valaddr_reg:x6; val_offset:4576*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4576*FLEN/8, x9, x1, x2) + +inst_2313: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xfff; + valaddr_reg:x6; val_offset:4578*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4578*FLEN/8, x9, x1, x2) + +inst_2314: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfff; op2val:0x400; + valaddr_reg:x6; val_offset:4580*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4580*FLEN/8, x9, x1, x2) + +inst_2315: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xe00; + valaddr_reg:x6; val_offset:4582*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4582*FLEN/8, x9, x1, x2) + +inst_2316: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xe00; op2val:0x400; + valaddr_reg:x6; val_offset:4584*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4584*FLEN/8, x9, x1, x2) + +inst_2317: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xdff; + valaddr_reg:x6; val_offset:4586*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4586*FLEN/8, x9, x1, x2) + +inst_2318: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xdff; op2val:0x400; + valaddr_reg:x6; val_offset:4588*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4588*FLEN/8, x9, x1, x2) + +inst_2319: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xf00; + valaddr_reg:x6; val_offset:4590*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4590*FLEN/8, x9, x1, x2) + +inst_2320: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x300 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf00; op2val:0x400; + valaddr_reg:x6; val_offset:4592*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4592*FLEN/8, x9, x1, x2) + +inst_2321: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xcff; + valaddr_reg:x6; val_offset:4594*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4594*FLEN/8, x9, x1, x2) + +inst_2322: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xcff; op2val:0x400; + valaddr_reg:x6; val_offset:4596*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4596*FLEN/8, x9, x1, x2) + +inst_2323: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xf80; + valaddr_reg:x6; val_offset:4598*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4598*FLEN/8, x9, x1, x2) + +inst_2324: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x380 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf80; op2val:0x400; + valaddr_reg:x6; val_offset:4600*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4600*FLEN/8, x9, x1, x2) + +inst_2325: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xc7f; + valaddr_reg:x6; val_offset:4602*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4602*FLEN/8, x9, x1, x2) + +inst_2326: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x07f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc7f; op2val:0x400; + valaddr_reg:x6; val_offset:4604*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4604*FLEN/8, x9, x1, x2) + +inst_2327: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xfc0; + valaddr_reg:x6; val_offset:4606*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4606*FLEN/8, x9, x1, x2) + +inst_2328: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfc0; op2val:0x400; + valaddr_reg:x6; val_offset:4608*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4608*FLEN/8, x9, x1, x2) + +inst_2329: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xc3f; + valaddr_reg:x6; val_offset:4610*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4610*FLEN/8, x9, x1, x2) + +inst_2330: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc3f; op2val:0x400; + valaddr_reg:x6; val_offset:4612*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4612*FLEN/8, x9, x1, x2) + +inst_2331: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xfe0; + valaddr_reg:x6; val_offset:4614*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4614*FLEN/8, x9, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_18) + +inst_2332: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfe0; op2val:0x400; + valaddr_reg:x6; val_offset:4616*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4616*FLEN/8, x9, x1, x2) + +inst_2333: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xc1f; + valaddr_reg:x6; val_offset:4618*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4618*FLEN/8, x9, x1, x2) + +inst_2334: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x01f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc1f; op2val:0x400; + valaddr_reg:x6; val_offset:4620*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4620*FLEN/8, x9, x1, x2) + +inst_2335: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xff0; + valaddr_reg:x6; val_offset:4622*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4622*FLEN/8, x9, x1, x2) + +inst_2336: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xff0; op2val:0x400; + valaddr_reg:x6; val_offset:4624*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4624*FLEN/8, x9, x1, x2) + +inst_2337: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xc0f; + valaddr_reg:x6; val_offset:4626*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4626*FLEN/8, x9, x1, x2) + +inst_2338: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x00f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc0f; op2val:0x400; + valaddr_reg:x6; val_offset:4628*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4628*FLEN/8, x9, x1, x2) + +inst_2339: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xff8; + valaddr_reg:x6; val_offset:4630*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4630*FLEN/8, x9, x1, x2) + +inst_2340: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xff8; op2val:0x400; + valaddr_reg:x6; val_offset:4632*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4632*FLEN/8, x9, x1, x2) + +inst_2341: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xc07; + valaddr_reg:x6; val_offset:4634*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4634*FLEN/8, x9, x1, x2) + +inst_2342: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc07; op2val:0x400; + valaddr_reg:x6; val_offset:4636*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4636*FLEN/8, x9, x1, x2) + +inst_2343: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xffc; + valaddr_reg:x6; val_offset:4638*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4638*FLEN/8, x9, x1, x2) + +inst_2344: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xffc; op2val:0x400; + valaddr_reg:x6; val_offset:4640*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4640*FLEN/8, x9, x1, x2) + +inst_2345: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xc03; + valaddr_reg:x6; val_offset:4642*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4642*FLEN/8, x9, x1, x2) + +inst_2346: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x003 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc03; op2val:0x400; + valaddr_reg:x6; val_offset:4644*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4644*FLEN/8, x9, x1, x2) + +inst_2347: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xffe; + valaddr_reg:x6; val_offset:4646*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4646*FLEN/8, x9, x1, x2) + +inst_2348: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xffe; op2val:0x400; + valaddr_reg:x6; val_offset:4648*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4648*FLEN/8, x9, x1, x2) + +inst_2349: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x03 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0xc01; + valaddr_reg:x6; val_offset:4650*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4650*FLEN/8, x9, x1, x2) + +inst_2350: +// fs1 == 0 and fe1 == 0x03 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc01; op2val:0x400; + valaddr_reg:x6; val_offset:4652*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4652*FLEN/8, x9, x1, x2) + +inst_2351: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x1000; + valaddr_reg:x6; val_offset:4654*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4654*FLEN/8, x9, x1, x2) + +inst_2352: +// fs1 == 0 and fe1 == 0x04 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1000; op2val:0x400; + valaddr_reg:x6; val_offset:4656*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4656*FLEN/8, x9, x1, x2) + +inst_2353: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x13ff; + valaddr_reg:x6; val_offset:4658*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4658*FLEN/8, x9, x1, x2) + +inst_2354: +// fs1 == 0 and fe1 == 0x04 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x13ff; op2val:0x400; + valaddr_reg:x6; val_offset:4660*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4660*FLEN/8, x9, x1, x2) + +inst_2355: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x1200; + valaddr_reg:x6; val_offset:4662*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4662*FLEN/8, x9, x1, x2) + +inst_2356: +// fs1 == 0 and fe1 == 0x04 and fm1 == 0x200 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1200; op2val:0x400; + valaddr_reg:x6; val_offset:4664*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4664*FLEN/8, x9, x1, x2) + +inst_2357: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x11ff; + valaddr_reg:x6; val_offset:4666*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4666*FLEN/8, x9, x1, x2) + +inst_2358: +// fs1 == 0 and fe1 == 0x04 and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x11ff; op2val:0x400; + valaddr_reg:x6; val_offset:4668*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4668*FLEN/8, x9, x1, x2) + +inst_2359: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x1300; + valaddr_reg:x6; val_offset:4670*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4670*FLEN/8, x9, x1, x2) + +inst_2360: +// fs1 == 0 and fe1 == 0x04 and fm1 == 0x300 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1300; op2val:0x400; + valaddr_reg:x6; val_offset:4672*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4672*FLEN/8, x9, x1, x2) + +inst_2361: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x10ff; + valaddr_reg:x6; val_offset:4674*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4674*FLEN/8, x9, x1, x2) + +inst_2362: +// fs1 == 0 and fe1 == 0x04 and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x10ff; op2val:0x400; + valaddr_reg:x6; val_offset:4676*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4676*FLEN/8, x9, x1, x2) + +inst_2363: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x1380; + valaddr_reg:x6; val_offset:4678*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4678*FLEN/8, x9, x1, x2) + +inst_2364: +// fs1 == 0 and fe1 == 0x04 and fm1 == 0x380 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1380; op2val:0x400; + valaddr_reg:x6; val_offset:4680*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4680*FLEN/8, x9, x1, x2) + +inst_2365: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x107f; + valaddr_reg:x6; val_offset:4682*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4682*FLEN/8, x9, x1, x2) + +inst_2366: +// fs1 == 0 and fe1 == 0x04 and fm1 == 0x07f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x107f; op2val:0x400; + valaddr_reg:x6; val_offset:4684*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4684*FLEN/8, x9, x1, x2) + +inst_2367: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x13c0; + valaddr_reg:x6; val_offset:4686*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4686*FLEN/8, x9, x1, x2) + +inst_2368: +// fs1 == 0 and fe1 == 0x04 and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x13c0; op2val:0x400; + valaddr_reg:x6; val_offset:4688*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4688*FLEN/8, x9, x1, x2) + +inst_2369: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x103f; + valaddr_reg:x6; val_offset:4690*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4690*FLEN/8, x9, x1, x2) + +inst_2370: +// fs1 == 0 and fe1 == 0x04 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x103f; op2val:0x400; + valaddr_reg:x6; val_offset:4692*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4692*FLEN/8, x9, x1, x2) + +inst_2371: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x13e0; + valaddr_reg:x6; val_offset:4694*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4694*FLEN/8, x9, x1, x2) + +inst_2372: +// fs1 == 0 and fe1 == 0x04 and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x13e0; op2val:0x400; + valaddr_reg:x6; val_offset:4696*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4696*FLEN/8, x9, x1, x2) + +inst_2373: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x101f; + valaddr_reg:x6; val_offset:4698*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4698*FLEN/8, x9, x1, x2) + +inst_2374: +// fs1 == 0 and fe1 == 0x04 and fm1 == 0x01f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x101f; op2val:0x400; + valaddr_reg:x6; val_offset:4700*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4700*FLEN/8, x9, x1, x2) + +inst_2375: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x13f0; + valaddr_reg:x6; val_offset:4702*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4702*FLEN/8, x9, x1, x2) + +inst_2376: +// fs1 == 0 and fe1 == 0x04 and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x13f0; op2val:0x400; + valaddr_reg:x6; val_offset:4704*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4704*FLEN/8, x9, x1, x2) + +inst_2377: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x100f; + valaddr_reg:x6; val_offset:4706*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4706*FLEN/8, x9, x1, x2) + +inst_2378: +// fs1 == 0 and fe1 == 0x04 and fm1 == 0x00f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x100f; op2val:0x400; + valaddr_reg:x6; val_offset:4708*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4708*FLEN/8, x9, x1, x2) + +inst_2379: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x13f8; + valaddr_reg:x6; val_offset:4710*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4710*FLEN/8, x9, x1, x2) + +inst_2380: +// fs1 == 0 and fe1 == 0x04 and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x13f8; op2val:0x400; + valaddr_reg:x6; val_offset:4712*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4712*FLEN/8, x9, x1, x2) + +inst_2381: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x1007; + valaddr_reg:x6; val_offset:4714*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4714*FLEN/8, x9, x1, x2) + +inst_2382: +// fs1 == 0 and fe1 == 0x04 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1007; op2val:0x400; + valaddr_reg:x6; val_offset:4716*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4716*FLEN/8, x9, x1, x2) + +inst_2383: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x13fc; + valaddr_reg:x6; val_offset:4718*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4718*FLEN/8, x9, x1, x2) + +inst_2384: +// fs1 == 0 and fe1 == 0x04 and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x13fc; op2val:0x400; + valaddr_reg:x6; val_offset:4720*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4720*FLEN/8, x9, x1, x2) + +inst_2385: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x1003; + valaddr_reg:x6; val_offset:4722*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4722*FLEN/8, x9, x1, x2) + +inst_2386: +// fs1 == 0 and fe1 == 0x04 and fm1 == 0x003 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1003; op2val:0x400; + valaddr_reg:x6; val_offset:4724*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4724*FLEN/8, x9, x1, x2) + +inst_2387: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x13fe; + valaddr_reg:x6; val_offset:4726*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4726*FLEN/8, x9, x1, x2) + +inst_2388: +// fs1 == 0 and fe1 == 0x04 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x13fe; op2val:0x400; + valaddr_reg:x6; val_offset:4728*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4728*FLEN/8, x9, x1, x2) + +inst_2389: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x04 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x400; op2val:0x1001; + valaddr_reg:x6; val_offset:4730*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4730*FLEN/8, x9, x1, x2) + +inst_2390: +// fs1 == 0 and fe1 == 0x04 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1001; op2val:0x400; + valaddr_reg:x6; val_offset:4732*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4732*FLEN/8, x9, x1, x2) + +inst_2391: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8200; + valaddr_reg:x6; val_offset:4734*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4734*FLEN/8, x9, x1, x2) + +inst_2392: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8200; op2val:0x8400; + valaddr_reg:x6; val_offset:4736*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4736*FLEN/8, x9, x1, x2) + +inst_2393: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x81ff; + valaddr_reg:x6; val_offset:4738*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4738*FLEN/8, x9, x1, x2) + +inst_2394: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x81ff; op2val:0x8400; + valaddr_reg:x6; val_offset:4740*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4740*FLEN/8, x9, x1, x2) + +inst_2395: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8300; + valaddr_reg:x6; val_offset:4742*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4742*FLEN/8, x9, x1, x2) + +inst_2396: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x300 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8300; op2val:0x8400; + valaddr_reg:x6; val_offset:4744*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4744*FLEN/8, x9, x1, x2) + +inst_2397: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x80ff; + valaddr_reg:x6; val_offset:4746*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4746*FLEN/8, x9, x1, x2) + +inst_2398: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x80ff; op2val:0x8400; + valaddr_reg:x6; val_offset:4748*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4748*FLEN/8, x9, x1, x2) + +inst_2399: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8380; + valaddr_reg:x6; val_offset:4750*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4750*FLEN/8, x9, x1, x2) + +inst_2400: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x380 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8380; op2val:0x8400; + valaddr_reg:x6; val_offset:4752*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4752*FLEN/8, x9, x1, x2) + +inst_2401: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x807f; + valaddr_reg:x6; val_offset:4754*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4754*FLEN/8, x9, x1, x2) + +inst_2402: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x07f and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x807f; op2val:0x8400; + valaddr_reg:x6; val_offset:4756*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4756*FLEN/8, x9, x1, x2) + +inst_2403: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x83c0; + valaddr_reg:x6; val_offset:4758*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4758*FLEN/8, x9, x1, x2) + +inst_2404: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83c0; op2val:0x8400; + valaddr_reg:x6; val_offset:4760*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4760*FLEN/8, x9, x1, x2) + +inst_2405: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x803f; + valaddr_reg:x6; val_offset:4762*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4762*FLEN/8, x9, x1, x2) + +inst_2406: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x803f; op2val:0x8400; + valaddr_reg:x6; val_offset:4764*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4764*FLEN/8, x9, x1, x2) + +inst_2407: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x83e0; + valaddr_reg:x6; val_offset:4766*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4766*FLEN/8, x9, x1, x2) + +inst_2408: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83e0; op2val:0x8400; + valaddr_reg:x6; val_offset:4768*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4768*FLEN/8, x9, x1, x2) + +inst_2409: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x801f; + valaddr_reg:x6; val_offset:4770*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4770*FLEN/8, x9, x1, x2) + +inst_2410: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x01f and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x801f; op2val:0x8400; + valaddr_reg:x6; val_offset:4772*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4772*FLEN/8, x9, x1, x2) + +inst_2411: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x83f0; + valaddr_reg:x6; val_offset:4774*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4774*FLEN/8, x9, x1, x2) + +inst_2412: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83f0; op2val:0x8400; + valaddr_reg:x6; val_offset:4776*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4776*FLEN/8, x9, x1, x2) + +inst_2413: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x800f; + valaddr_reg:x6; val_offset:4778*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4778*FLEN/8, x9, x1, x2) + +inst_2414: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x00f and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x800f; op2val:0x8400; + valaddr_reg:x6; val_offset:4780*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4780*FLEN/8, x9, x1, x2) + +inst_2415: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x83f8; + valaddr_reg:x6; val_offset:4782*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4782*FLEN/8, x9, x1, x2) + +inst_2416: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83f8; op2val:0x8400; + valaddr_reg:x6; val_offset:4784*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4784*FLEN/8, x9, x1, x2) + +inst_2417: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8007; + valaddr_reg:x6; val_offset:4786*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4786*FLEN/8, x9, x1, x2) + +inst_2418: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8007; op2val:0x8400; + valaddr_reg:x6; val_offset:4788*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4788*FLEN/8, x9, x1, x2) + +inst_2419: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x83fc; + valaddr_reg:x6; val_offset:4790*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4790*FLEN/8, x9, x1, x2) + +inst_2420: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fc; op2val:0x8400; + valaddr_reg:x6; val_offset:4792*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4792*FLEN/8, x9, x1, x2) + +inst_2421: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8003; + valaddr_reg:x6; val_offset:4794*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4794*FLEN/8, x9, x1, x2) + +inst_2422: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8003; op2val:0x8400; + valaddr_reg:x6; val_offset:4796*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4796*FLEN/8, x9, x1, x2) + +inst_2423: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x83fe; + valaddr_reg:x6; val_offset:4798*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4798*FLEN/8, x9, x1, x2) + +inst_2424: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x8400; + valaddr_reg:x6; val_offset:4800*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4800*FLEN/8, x9, x1, x2) + +inst_2425: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x87fe; + valaddr_reg:x6; val_offset:4802*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4802*FLEN/8, x9, x1, x2) + +inst_2426: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x87fe; op2val:0x8400; + valaddr_reg:x6; val_offset:4804*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4804*FLEN/8, x9, x1, x2) + +inst_2427: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8401; + valaddr_reg:x6; val_offset:4806*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4806*FLEN/8, x9, x1, x2) + +inst_2428: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8401; op2val:0x8400; + valaddr_reg:x6; val_offset:4808*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4808*FLEN/8, x9, x1, x2) + +inst_2429: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x1b6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x85b6; + valaddr_reg:x6; val_offset:4810*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4810*FLEN/8, x9, x1, x2) + +inst_2430: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x1b6 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x85b6; op2val:0x8400; + valaddr_reg:x6; val_offset:4812*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4812*FLEN/8, x9, x1, x2) + +inst_2431: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x36d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x876d; + valaddr_reg:x6; val_offset:4814*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4814*FLEN/8, x9, x1, x2) + +inst_2432: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x36d and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x876d; op2val:0x8400; + valaddr_reg:x6; val_offset:4816*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4816*FLEN/8, x9, x1, x2) + +inst_2433: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0cc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x84cc; + valaddr_reg:x6; val_offset:4818*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4818*FLEN/8, x9, x1, x2) + +inst_2434: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x0cc and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x84cc; op2val:0x8400; + valaddr_reg:x6; val_offset:4820*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4820*FLEN/8, x9, x1, x2) + +inst_2435: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x333 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8733; + valaddr_reg:x6; val_offset:4822*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4822*FLEN/8, x9, x1, x2) + +inst_2436: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x333 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8733; op2val:0x8400; + valaddr_reg:x6; val_offset:4824*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4824*FLEN/8, x9, x1, x2) + +inst_2437: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x1dd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x85dd; + valaddr_reg:x6; val_offset:4826*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4826*FLEN/8, x9, x1, x2) + +inst_2438: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x1dd and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x85dd; op2val:0x8400; + valaddr_reg:x6; val_offset:4828*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4828*FLEN/8, x9, x1, x2) + +inst_2439: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x222 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8622; + valaddr_reg:x6; val_offset:4830*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4830*FLEN/8, x9, x1, x2) + +inst_2440: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x222 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8622; op2val:0x8400; + valaddr_reg:x6; val_offset:4832*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4832*FLEN/8, x9, x1, x2) + +inst_2441: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x124 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8524; + valaddr_reg:x6; val_offset:4834*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4834*FLEN/8, x9, x1, x2) + +inst_2442: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x124 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8524; op2val:0x8400; + valaddr_reg:x6; val_offset:4836*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4836*FLEN/8, x9, x1, x2) + +inst_2443: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x2db and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x86db; + valaddr_reg:x6; val_offset:4838*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4838*FLEN/8, x9, x1, x2) + +inst_2444: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x2db and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x86db; op2val:0x8400; + valaddr_reg:x6; val_offset:4840*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4840*FLEN/8, x9, x1, x2) + +inst_2445: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x199 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8599; + valaddr_reg:x6; val_offset:4842*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4842*FLEN/8, x9, x1, x2) + +inst_2446: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x199 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8599; op2val:0x8400; + valaddr_reg:x6; val_offset:4844*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4844*FLEN/8, x9, x1, x2) + +inst_2447: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x266 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8666; + valaddr_reg:x6; val_offset:4846*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4846*FLEN/8, x9, x1, x2) + +inst_2448: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x266 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8666; op2val:0x8400; + valaddr_reg:x6; val_offset:4848*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4848*FLEN/8, x9, x1, x2) + +inst_2449: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x3800; + valaddr_reg:x6; val_offset:4850*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4850*FLEN/8, x9, x1, x2) + +inst_2450: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3800; op2val:0x8400; + valaddr_reg:x6; val_offset:4852*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4852*FLEN/8, x9, x1, x2) + +inst_2451: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x3bff; + valaddr_reg:x6; val_offset:4854*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4854*FLEN/8, x9, x1, x2) + +inst_2452: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bff; op2val:0x8400; + valaddr_reg:x6; val_offset:4856*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4856*FLEN/8, x9, x1, x2) + +inst_2453: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x3a00; + valaddr_reg:x6; val_offset:4858*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4858*FLEN/8, x9, x1, x2) + +inst_2454: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a00; op2val:0x8400; + valaddr_reg:x6; val_offset:4860*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4860*FLEN/8, x9, x1, x2) + +inst_2455: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x39ff; + valaddr_reg:x6; val_offset:4862*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4862*FLEN/8, x9, x1, x2) + +inst_2456: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39ff; op2val:0x8400; + valaddr_reg:x6; val_offset:4864*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4864*FLEN/8, x9, x1, x2) + +inst_2457: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x3b00; + valaddr_reg:x6; val_offset:4866*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4866*FLEN/8, x9, x1, x2) + +inst_2458: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x300 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b00; op2val:0x8400; + valaddr_reg:x6; val_offset:4868*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4868*FLEN/8, x9, x1, x2) + +inst_2459: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x38ff; + valaddr_reg:x6; val_offset:4870*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4870*FLEN/8, x9, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_19) + +inst_2460: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x38ff; op2val:0x8400; + valaddr_reg:x6; val_offset:4872*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4872*FLEN/8, x9, x1, x2) + +inst_2461: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x3b80; + valaddr_reg:x6; val_offset:4874*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4874*FLEN/8, x9, x1, x2) + +inst_2462: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x380 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b80; op2val:0x8400; + valaddr_reg:x6; val_offset:4876*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4876*FLEN/8, x9, x1, x2) + +inst_2463: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x387f; + valaddr_reg:x6; val_offset:4878*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4878*FLEN/8, x9, x1, x2) + +inst_2464: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x07f and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x387f; op2val:0x8400; + valaddr_reg:x6; val_offset:4880*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4880*FLEN/8, x9, x1, x2) + +inst_2465: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x3bc0; + valaddr_reg:x6; val_offset:4882*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4882*FLEN/8, x9, x1, x2) + +inst_2466: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bc0; op2val:0x8400; + valaddr_reg:x6; val_offset:4884*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4884*FLEN/8, x9, x1, x2) + +inst_2467: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x383f; + valaddr_reg:x6; val_offset:4886*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4886*FLEN/8, x9, x1, x2) + +inst_2468: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x03f and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x383f; op2val:0x8400; + valaddr_reg:x6; val_offset:4888*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4888*FLEN/8, x9, x1, x2) + +inst_2469: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x3be0; + valaddr_reg:x6; val_offset:4890*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4890*FLEN/8, x9, x1, x2) + +inst_2470: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3be0; op2val:0x8400; + valaddr_reg:x6; val_offset:4892*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4892*FLEN/8, x9, x1, x2) + +inst_2471: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x381f; + valaddr_reg:x6; val_offset:4894*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4894*FLEN/8, x9, x1, x2) + +inst_2472: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x01f and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x381f; op2val:0x8400; + valaddr_reg:x6; val_offset:4896*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4896*FLEN/8, x9, x1, x2) + +inst_2473: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x3bf0; + valaddr_reg:x6; val_offset:4898*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4898*FLEN/8, x9, x1, x2) + +inst_2474: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bf0; op2val:0x8400; + valaddr_reg:x6; val_offset:4900*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4900*FLEN/8, x9, x1, x2) + +inst_2475: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x380f; + valaddr_reg:x6; val_offset:4902*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4902*FLEN/8, x9, x1, x2) + +inst_2476: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x00f and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x380f; op2val:0x8400; + valaddr_reg:x6; val_offset:4904*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4904*FLEN/8, x9, x1, x2) + +inst_2477: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x3bf8; + valaddr_reg:x6; val_offset:4906*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4906*FLEN/8, x9, x1, x2) + +inst_2478: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bf8; op2val:0x8400; + valaddr_reg:x6; val_offset:4908*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4908*FLEN/8, x9, x1, x2) + +inst_2479: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x3807; + valaddr_reg:x6; val_offset:4910*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4910*FLEN/8, x9, x1, x2) + +inst_2480: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x007 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3807; op2val:0x8400; + valaddr_reg:x6; val_offset:4912*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4912*FLEN/8, x9, x1, x2) + +inst_2481: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x3bfc; + valaddr_reg:x6; val_offset:4914*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4914*FLEN/8, x9, x1, x2) + +inst_2482: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bfc; op2val:0x8400; + valaddr_reg:x6; val_offset:4916*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4916*FLEN/8, x9, x1, x2) + +inst_2483: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x3803; + valaddr_reg:x6; val_offset:4918*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4918*FLEN/8, x9, x1, x2) + +inst_2484: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x003 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3803; op2val:0x8400; + valaddr_reg:x6; val_offset:4920*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4920*FLEN/8, x9, x1, x2) + +inst_2485: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x3bfe; + valaddr_reg:x6; val_offset:4922*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4922*FLEN/8, x9, x1, x2) + +inst_2486: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bfe; op2val:0x8400; + valaddr_reg:x6; val_offset:4924*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4924*FLEN/8, x9, x1, x2) + +inst_2487: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x3801; + valaddr_reg:x6; val_offset:4926*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4926*FLEN/8, x9, x1, x2) + +inst_2488: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3801; op2val:0x8400; + valaddr_reg:x6; val_offset:4928*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4928*FLEN/8, x9, x1, x2) + +inst_2489: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8400; + valaddr_reg:x6; val_offset:4930*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4930*FLEN/8, x9, x1, x2) + +inst_2490: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x87ff; + valaddr_reg:x6; val_offset:4932*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4932*FLEN/8, x9, x1, x2) + +inst_2491: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x87ff; op2val:0x8400; + valaddr_reg:x6; val_offset:4934*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4934*FLEN/8, x9, x1, x2) + +inst_2492: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8600; + valaddr_reg:x6; val_offset:4936*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4936*FLEN/8, x9, x1, x2) + +inst_2493: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8600; op2val:0x8400; + valaddr_reg:x6; val_offset:4938*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4938*FLEN/8, x9, x1, x2) + +inst_2494: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x85ff; + valaddr_reg:x6; val_offset:4940*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4940*FLEN/8, x9, x1, x2) + +inst_2495: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x85ff; op2val:0x8400; + valaddr_reg:x6; val_offset:4942*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4942*FLEN/8, x9, x1, x2) + +inst_2496: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8700; + valaddr_reg:x6; val_offset:4944*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4944*FLEN/8, x9, x1, x2) + +inst_2497: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x300 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8700; op2val:0x8400; + valaddr_reg:x6; val_offset:4946*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4946*FLEN/8, x9, x1, x2) + +inst_2498: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x84ff; + valaddr_reg:x6; val_offset:4948*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4948*FLEN/8, x9, x1, x2) + +inst_2499: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x84ff; op2val:0x8400; + valaddr_reg:x6; val_offset:4950*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4950*FLEN/8, x9, x1, x2) + +inst_2500: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8780; + valaddr_reg:x6; val_offset:4952*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4952*FLEN/8, x9, x1, x2) + +inst_2501: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x380 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8780; op2val:0x8400; + valaddr_reg:x6; val_offset:4954*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4954*FLEN/8, x9, x1, x2) + +inst_2502: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x847f; + valaddr_reg:x6; val_offset:4956*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4956*FLEN/8, x9, x1, x2) + +inst_2503: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x07f and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x847f; op2val:0x8400; + valaddr_reg:x6; val_offset:4958*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4958*FLEN/8, x9, x1, x2) + +inst_2504: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x87c0; + valaddr_reg:x6; val_offset:4960*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4960*FLEN/8, x9, x1, x2) + +inst_2505: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x87c0; op2val:0x8400; + valaddr_reg:x6; val_offset:4962*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4962*FLEN/8, x9, x1, x2) + +inst_2506: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x843f; + valaddr_reg:x6; val_offset:4964*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4964*FLEN/8, x9, x1, x2) + +inst_2507: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x843f; op2val:0x8400; + valaddr_reg:x6; val_offset:4966*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4966*FLEN/8, x9, x1, x2) + +inst_2508: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x87e0; + valaddr_reg:x6; val_offset:4968*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4968*FLEN/8, x9, x1, x2) + +inst_2509: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x87e0; op2val:0x8400; + valaddr_reg:x6; val_offset:4970*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4970*FLEN/8, x9, x1, x2) + +inst_2510: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x841f; + valaddr_reg:x6; val_offset:4972*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4972*FLEN/8, x9, x1, x2) + +inst_2511: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x01f and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x841f; op2val:0x8400; + valaddr_reg:x6; val_offset:4974*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4974*FLEN/8, x9, x1, x2) + +inst_2512: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x87f0; + valaddr_reg:x6; val_offset:4976*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4976*FLEN/8, x9, x1, x2) + +inst_2513: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x87f0; op2val:0x8400; + valaddr_reg:x6; val_offset:4978*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4978*FLEN/8, x9, x1, x2) + +inst_2514: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x840f; + valaddr_reg:x6; val_offset:4980*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4980*FLEN/8, x9, x1, x2) + +inst_2515: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x00f and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x840f; op2val:0x8400; + valaddr_reg:x6; val_offset:4982*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4982*FLEN/8, x9, x1, x2) + +inst_2516: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x87f8; + valaddr_reg:x6; val_offset:4984*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4984*FLEN/8, x9, x1, x2) + +inst_2517: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x87f8; op2val:0x8400; + valaddr_reg:x6; val_offset:4986*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4986*FLEN/8, x9, x1, x2) + +inst_2518: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8407; + valaddr_reg:x6; val_offset:4988*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4988*FLEN/8, x9, x1, x2) + +inst_2519: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8407; op2val:0x8400; + valaddr_reg:x6; val_offset:4990*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4990*FLEN/8, x9, x1, x2) + +inst_2520: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x87fc; + valaddr_reg:x6; val_offset:4992*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4992*FLEN/8, x9, x1, x2) + +inst_2521: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x87fc; op2val:0x8400; + valaddr_reg:x6; val_offset:4994*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4994*FLEN/8, x9, x1, x2) + +inst_2522: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8403; + valaddr_reg:x6; val_offset:4996*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4996*FLEN/8, x9, x1, x2) + +inst_2523: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8403; op2val:0x8400; + valaddr_reg:x6; val_offset:4998*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 4998*FLEN/8, x9, x1, x2) + +inst_2524: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8800; + valaddr_reg:x6; val_offset:5000*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5000*FLEN/8, x9, x1, x2) + +inst_2525: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8800; op2val:0x8400; + valaddr_reg:x6; val_offset:5002*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5002*FLEN/8, x9, x1, x2) + +inst_2526: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8bff; + valaddr_reg:x6; val_offset:5004*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5004*FLEN/8, x9, x1, x2) + +inst_2527: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8bff; op2val:0x8400; + valaddr_reg:x6; val_offset:5006*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5006*FLEN/8, x9, x1, x2) + +inst_2528: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8a00; + valaddr_reg:x6; val_offset:5008*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5008*FLEN/8, x9, x1, x2) + +inst_2529: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8a00; op2val:0x8400; + valaddr_reg:x6; val_offset:5010*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5010*FLEN/8, x9, x1, x2) + +inst_2530: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x89ff; + valaddr_reg:x6; val_offset:5012*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5012*FLEN/8, x9, x1, x2) + +inst_2531: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x89ff; op2val:0x8400; + valaddr_reg:x6; val_offset:5014*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5014*FLEN/8, x9, x1, x2) + +inst_2532: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8b00; + valaddr_reg:x6; val_offset:5016*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5016*FLEN/8, x9, x1, x2) + +inst_2533: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x300 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8b00; op2val:0x8400; + valaddr_reg:x6; val_offset:5018*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5018*FLEN/8, x9, x1, x2) + +inst_2534: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x88ff; + valaddr_reg:x6; val_offset:5020*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5020*FLEN/8, x9, x1, x2) + +inst_2535: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x88ff; op2val:0x8400; + valaddr_reg:x6; val_offset:5022*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5022*FLEN/8, x9, x1, x2) + +inst_2536: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8b80; + valaddr_reg:x6; val_offset:5024*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5024*FLEN/8, x9, x1, x2) + +inst_2537: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x380 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8b80; op2val:0x8400; + valaddr_reg:x6; val_offset:5026*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5026*FLEN/8, x9, x1, x2) + +inst_2538: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x887f; + valaddr_reg:x6; val_offset:5028*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5028*FLEN/8, x9, x1, x2) + +inst_2539: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x07f and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x887f; op2val:0x8400; + valaddr_reg:x6; val_offset:5030*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5030*FLEN/8, x9, x1, x2) + +inst_2540: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8bc0; + valaddr_reg:x6; val_offset:5032*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5032*FLEN/8, x9, x1, x2) + +inst_2541: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8bc0; op2val:0x8400; + valaddr_reg:x6; val_offset:5034*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5034*FLEN/8, x9, x1, x2) + +inst_2542: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x883f; + valaddr_reg:x6; val_offset:5036*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5036*FLEN/8, x9, x1, x2) + +inst_2543: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x883f; op2val:0x8400; + valaddr_reg:x6; val_offset:5038*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5038*FLEN/8, x9, x1, x2) + +inst_2544: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8be0; + valaddr_reg:x6; val_offset:5040*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5040*FLEN/8, x9, x1, x2) + +inst_2545: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8be0; op2val:0x8400; + valaddr_reg:x6; val_offset:5042*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5042*FLEN/8, x9, x1, x2) + +inst_2546: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x881f; + valaddr_reg:x6; val_offset:5044*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5044*FLEN/8, x9, x1, x2) + +inst_2547: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x01f and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x881f; op2val:0x8400; + valaddr_reg:x6; val_offset:5046*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5046*FLEN/8, x9, x1, x2) + +inst_2548: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8bf0; + valaddr_reg:x6; val_offset:5048*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5048*FLEN/8, x9, x1, x2) + +inst_2549: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8bf0; op2val:0x8400; + valaddr_reg:x6; val_offset:5050*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5050*FLEN/8, x9, x1, x2) + +inst_2550: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x880f; + valaddr_reg:x6; val_offset:5052*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5052*FLEN/8, x9, x1, x2) + +inst_2551: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x00f and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x880f; op2val:0x8400; + valaddr_reg:x6; val_offset:5054*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5054*FLEN/8, x9, x1, x2) + +inst_2552: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8bf8; + valaddr_reg:x6; val_offset:5056*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5056*FLEN/8, x9, x1, x2) + +inst_2553: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8bf8; op2val:0x8400; + valaddr_reg:x6; val_offset:5058*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5058*FLEN/8, x9, x1, x2) + +inst_2554: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8807; + valaddr_reg:x6; val_offset:5060*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5060*FLEN/8, x9, x1, x2) + +inst_2555: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8807; op2val:0x8400; + valaddr_reg:x6; val_offset:5062*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5062*FLEN/8, x9, x1, x2) + +inst_2556: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8bfc; + valaddr_reg:x6; val_offset:5064*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5064*FLEN/8, x9, x1, x2) + +inst_2557: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8bfc; op2val:0x8400; + valaddr_reg:x6; val_offset:5066*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5066*FLEN/8, x9, x1, x2) + +inst_2558: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8803; + valaddr_reg:x6; val_offset:5068*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5068*FLEN/8, x9, x1, x2) + +inst_2559: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8803; op2val:0x8400; + valaddr_reg:x6; val_offset:5070*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5070*FLEN/8, x9, x1, x2) + +inst_2560: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8bfe; + valaddr_reg:x6; val_offset:5072*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5072*FLEN/8, x9, x1, x2) + +inst_2561: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8bfe; op2val:0x8400; + valaddr_reg:x6; val_offset:5074*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5074*FLEN/8, x9, x1, x2) + +inst_2562: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8801; + valaddr_reg:x6; val_offset:5076*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5076*FLEN/8, x9, x1, x2) + +inst_2563: +// fs1 == 1 and fe1 == 0x02 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8801; op2val:0x8400; + valaddr_reg:x6; val_offset:5078*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5078*FLEN/8, x9, x1, x2) + +inst_2564: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8c00; + valaddr_reg:x6; val_offset:5080*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5080*FLEN/8, x9, x1, x2) + +inst_2565: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8c00; op2val:0x8400; + valaddr_reg:x6; val_offset:5082*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5082*FLEN/8, x9, x1, x2) + +inst_2566: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8fff; + valaddr_reg:x6; val_offset:5084*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5084*FLEN/8, x9, x1, x2) + +inst_2567: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8fff; op2val:0x8400; + valaddr_reg:x6; val_offset:5086*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5086*FLEN/8, x9, x1, x2) + +inst_2568: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8e00; + valaddr_reg:x6; val_offset:5088*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5088*FLEN/8, x9, x1, x2) + +inst_2569: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8e00; op2val:0x8400; + valaddr_reg:x6; val_offset:5090*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5090*FLEN/8, x9, x1, x2) + +inst_2570: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8dff; + valaddr_reg:x6; val_offset:5092*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5092*FLEN/8, x9, x1, x2) + +inst_2571: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8dff; op2val:0x8400; + valaddr_reg:x6; val_offset:5094*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5094*FLEN/8, x9, x1, x2) + +inst_2572: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8f00; + valaddr_reg:x6; val_offset:5096*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5096*FLEN/8, x9, x1, x2) + +inst_2573: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x300 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8f00; op2val:0x8400; + valaddr_reg:x6; val_offset:5098*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5098*FLEN/8, x9, x1, x2) + +inst_2574: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8cff; + valaddr_reg:x6; val_offset:5100*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5100*FLEN/8, x9, x1, x2) + +inst_2575: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8cff; op2val:0x8400; + valaddr_reg:x6; val_offset:5102*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5102*FLEN/8, x9, x1, x2) + +inst_2576: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8f80; + valaddr_reg:x6; val_offset:5104*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5104*FLEN/8, x9, x1, x2) + +inst_2577: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x380 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8f80; op2val:0x8400; + valaddr_reg:x6; val_offset:5106*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5106*FLEN/8, x9, x1, x2) + +inst_2578: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8c7f; + valaddr_reg:x6; val_offset:5108*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5108*FLEN/8, x9, x1, x2) + +inst_2579: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x07f and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8c7f; op2val:0x8400; + valaddr_reg:x6; val_offset:5110*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5110*FLEN/8, x9, x1, x2) + +inst_2580: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8fc0; + valaddr_reg:x6; val_offset:5112*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5112*FLEN/8, x9, x1, x2) + +inst_2581: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8fc0; op2val:0x8400; + valaddr_reg:x6; val_offset:5114*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5114*FLEN/8, x9, x1, x2) + +inst_2582: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8c3f; + valaddr_reg:x6; val_offset:5116*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5116*FLEN/8, x9, x1, x2) + +inst_2583: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8c3f; op2val:0x8400; + valaddr_reg:x6; val_offset:5118*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5118*FLEN/8, x9, x1, x2) + +inst_2584: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8fe0; + valaddr_reg:x6; val_offset:5120*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5120*FLEN/8, x9, x1, x2) + +inst_2585: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8fe0; op2val:0x8400; + valaddr_reg:x6; val_offset:5122*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5122*FLEN/8, x9, x1, x2) + +inst_2586: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8c1f; + valaddr_reg:x6; val_offset:5124*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5124*FLEN/8, x9, x1, x2) + +inst_2587: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x01f and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8c1f; op2val:0x8400; + valaddr_reg:x6; val_offset:5126*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5126*FLEN/8, x9, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_20) + +inst_2588: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8ff0; + valaddr_reg:x6; val_offset:5128*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5128*FLEN/8, x9, x1, x2) + +inst_2589: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8ff0; op2val:0x8400; + valaddr_reg:x6; val_offset:5130*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5130*FLEN/8, x9, x1, x2) + +inst_2590: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8c0f; + valaddr_reg:x6; val_offset:5132*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5132*FLEN/8, x9, x1, x2) + +inst_2591: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x00f and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8c0f; op2val:0x8400; + valaddr_reg:x6; val_offset:5134*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5134*FLEN/8, x9, x1, x2) + +inst_2592: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8ff8; + valaddr_reg:x6; val_offset:5136*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5136*FLEN/8, x9, x1, x2) + +inst_2593: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8ff8; op2val:0x8400; + valaddr_reg:x6; val_offset:5138*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5138*FLEN/8, x9, x1, x2) + +inst_2594: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8c07; + valaddr_reg:x6; val_offset:5140*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5140*FLEN/8, x9, x1, x2) + +inst_2595: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8c07; op2val:0x8400; + valaddr_reg:x6; val_offset:5142*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5142*FLEN/8, x9, x1, x2) + +inst_2596: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8ffc; + valaddr_reg:x6; val_offset:5144*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5144*FLEN/8, x9, x1, x2) + +inst_2597: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8ffc; op2val:0x8400; + valaddr_reg:x6; val_offset:5146*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5146*FLEN/8, x9, x1, x2) + +inst_2598: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8c03; + valaddr_reg:x6; val_offset:5148*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5148*FLEN/8, x9, x1, x2) + +inst_2599: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8c03; op2val:0x8400; + valaddr_reg:x6; val_offset:5150*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5150*FLEN/8, x9, x1, x2) + +inst_2600: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8ffe; + valaddr_reg:x6; val_offset:5152*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5152*FLEN/8, x9, x1, x2) + +inst_2601: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8ffe; op2val:0x8400; + valaddr_reg:x6; val_offset:5154*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5154*FLEN/8, x9, x1, x2) + +inst_2602: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x03 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x8c01; + valaddr_reg:x6; val_offset:5156*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5156*FLEN/8, x9, x1, x2) + +inst_2603: +// fs1 == 1 and fe1 == 0x03 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8c01; op2val:0x8400; + valaddr_reg:x6; val_offset:5158*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5158*FLEN/8, x9, x1, x2) + +inst_2604: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x9000; + valaddr_reg:x6; val_offset:5160*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5160*FLEN/8, x9, x1, x2) + +inst_2605: +// fs1 == 1 and fe1 == 0x04 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x9000; op2val:0x8400; + valaddr_reg:x6; val_offset:5162*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5162*FLEN/8, x9, x1, x2) + +inst_2606: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x93ff; + valaddr_reg:x6; val_offset:5164*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5164*FLEN/8, x9, x1, x2) + +inst_2607: +// fs1 == 1 and fe1 == 0x04 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x93ff; op2val:0x8400; + valaddr_reg:x6; val_offset:5166*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5166*FLEN/8, x9, x1, x2) + +inst_2608: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x9200; + valaddr_reg:x6; val_offset:5168*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5168*FLEN/8, x9, x1, x2) + +inst_2609: +// fs1 == 1 and fe1 == 0x04 and fm1 == 0x200 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x9200; op2val:0x8400; + valaddr_reg:x6; val_offset:5170*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5170*FLEN/8, x9, x1, x2) + +inst_2610: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x91ff; + valaddr_reg:x6; val_offset:5172*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5172*FLEN/8, x9, x1, x2) + +inst_2611: +// fs1 == 1 and fe1 == 0x04 and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x91ff; op2val:0x8400; + valaddr_reg:x6; val_offset:5174*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5174*FLEN/8, x9, x1, x2) + +inst_2612: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x9300; + valaddr_reg:x6; val_offset:5176*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5176*FLEN/8, x9, x1, x2) + +inst_2613: +// fs1 == 1 and fe1 == 0x04 and fm1 == 0x300 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x9300; op2val:0x8400; + valaddr_reg:x6; val_offset:5178*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5178*FLEN/8, x9, x1, x2) + +inst_2614: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x90ff; + valaddr_reg:x6; val_offset:5180*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5180*FLEN/8, x9, x1, x2) + +inst_2615: +// fs1 == 1 and fe1 == 0x04 and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x90ff; op2val:0x8400; + valaddr_reg:x6; val_offset:5182*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5182*FLEN/8, x9, x1, x2) + +inst_2616: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x9380; + valaddr_reg:x6; val_offset:5184*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5184*FLEN/8, x9, x1, x2) + +inst_2617: +// fs1 == 1 and fe1 == 0x04 and fm1 == 0x380 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x9380; op2val:0x8400; + valaddr_reg:x6; val_offset:5186*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5186*FLEN/8, x9, x1, x2) + +inst_2618: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x907f; + valaddr_reg:x6; val_offset:5188*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5188*FLEN/8, x9, x1, x2) + +inst_2619: +// fs1 == 1 and fe1 == 0x04 and fm1 == 0x07f and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x907f; op2val:0x8400; + valaddr_reg:x6; val_offset:5190*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5190*FLEN/8, x9, x1, x2) + +inst_2620: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x93c0; + valaddr_reg:x6; val_offset:5192*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5192*FLEN/8, x9, x1, x2) + +inst_2621: +// fs1 == 1 and fe1 == 0x04 and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x93c0; op2val:0x8400; + valaddr_reg:x6; val_offset:5194*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5194*FLEN/8, x9, x1, x2) + +inst_2622: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x903f; + valaddr_reg:x6; val_offset:5196*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5196*FLEN/8, x9, x1, x2) + +inst_2623: +// fs1 == 1 and fe1 == 0x04 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x903f; op2val:0x8400; + valaddr_reg:x6; val_offset:5198*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5198*FLEN/8, x9, x1, x2) + +inst_2624: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x93e0; + valaddr_reg:x6; val_offset:5200*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5200*FLEN/8, x9, x1, x2) + +inst_2625: +// fs1 == 1 and fe1 == 0x04 and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x93e0; op2val:0x8400; + valaddr_reg:x6; val_offset:5202*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5202*FLEN/8, x9, x1, x2) + +inst_2626: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x901f; + valaddr_reg:x6; val_offset:5204*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5204*FLEN/8, x9, x1, x2) + +inst_2627: +// fs1 == 1 and fe1 == 0x04 and fm1 == 0x01f and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x901f; op2val:0x8400; + valaddr_reg:x6; val_offset:5206*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5206*FLEN/8, x9, x1, x2) + +inst_2628: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x93f0; + valaddr_reg:x6; val_offset:5208*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5208*FLEN/8, x9, x1, x2) + +inst_2629: +// fs1 == 1 and fe1 == 0x04 and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x93f0; op2val:0x8400; + valaddr_reg:x6; val_offset:5210*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5210*FLEN/8, x9, x1, x2) + +inst_2630: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x900f; + valaddr_reg:x6; val_offset:5212*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5212*FLEN/8, x9, x1, x2) + +inst_2631: +// fs1 == 1 and fe1 == 0x04 and fm1 == 0x00f and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x900f; op2val:0x8400; + valaddr_reg:x6; val_offset:5214*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5214*FLEN/8, x9, x1, x2) + +inst_2632: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x93f8; + valaddr_reg:x6; val_offset:5216*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5216*FLEN/8, x9, x1, x2) + +inst_2633: +// fs1 == 1 and fe1 == 0x04 and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x93f8; op2val:0x8400; + valaddr_reg:x6; val_offset:5218*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5218*FLEN/8, x9, x1, x2) + +inst_2634: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x9007; + valaddr_reg:x6; val_offset:5220*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5220*FLEN/8, x9, x1, x2) + +inst_2635: +// fs1 == 1 and fe1 == 0x04 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x9007; op2val:0x8400; + valaddr_reg:x6; val_offset:5222*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5222*FLEN/8, x9, x1, x2) + +inst_2636: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x93fc; + valaddr_reg:x6; val_offset:5224*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5224*FLEN/8, x9, x1, x2) + +inst_2637: +// fs1 == 1 and fe1 == 0x04 and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x93fc; op2val:0x8400; + valaddr_reg:x6; val_offset:5226*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5226*FLEN/8, x9, x1, x2) + +inst_2638: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x9003; + valaddr_reg:x6; val_offset:5228*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5228*FLEN/8, x9, x1, x2) + +inst_2639: +// fs1 == 1 and fe1 == 0x04 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x9003; op2val:0x8400; + valaddr_reg:x6; val_offset:5230*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5230*FLEN/8, x9, x1, x2) + +inst_2640: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x93fe; + valaddr_reg:x6; val_offset:5232*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5232*FLEN/8, x9, x1, x2) + +inst_2641: +// fs1 == 1 and fe1 == 0x04 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x93fe; op2val:0x8400; + valaddr_reg:x6; val_offset:5234*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5234*FLEN/8, x9, x1, x2) + +inst_2642: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x9001; + valaddr_reg:x6; val_offset:5236*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5236*FLEN/8, x9, x1, x2) + +inst_2643: +// fs1 == 1 and fe1 == 0x04 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x9001; op2val:0x8400; + valaddr_reg:x6; val_offset:5238*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5238*FLEN/8, x9, x1, x2) + +inst_2644: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x06 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x1bff; + valaddr_reg:x6; val_offset:5240*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5240*FLEN/8, x9, x1, x2) + +inst_2645: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1bff; op2val:0x7bff; + valaddr_reg:x6; val_offset:5242*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5242*FLEN/8, x9, x1, x2) + +inst_2646: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x06 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x1800; + valaddr_reg:x6; val_offset:5244*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5244*FLEN/8, x9, x1, x2) + +inst_2647: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1800; op2val:0x7bff; + valaddr_reg:x6; val_offset:5246*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5246*FLEN/8, x9, x1, x2) + +inst_2648: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x06 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x19ff; + valaddr_reg:x6; val_offset:5248*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5248*FLEN/8, x9, x1, x2) + +inst_2649: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x19ff; op2val:0x7bff; + valaddr_reg:x6; val_offset:5250*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5250*FLEN/8, x9, x1, x2) + +inst_2650: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x06 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x1a00; + valaddr_reg:x6; val_offset:5252*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5252*FLEN/8, x9, x1, x2) + +inst_2651: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1a00; op2val:0x7bff; + valaddr_reg:x6; val_offset:5254*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5254*FLEN/8, x9, x1, x2) + +inst_2652: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x06 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x18ff; + valaddr_reg:x6; val_offset:5256*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5256*FLEN/8, x9, x1, x2) + +inst_2653: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x18ff; op2val:0x7bff; + valaddr_reg:x6; val_offset:5258*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5258*FLEN/8, x9, x1, x2) + +inst_2654: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x06 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x1b00; + valaddr_reg:x6; val_offset:5260*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5260*FLEN/8, x9, x1, x2) + +inst_2655: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x300 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1b00; op2val:0x7bff; + valaddr_reg:x6; val_offset:5262*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5262*FLEN/8, x9, x1, x2) + +inst_2656: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x06 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x187f; + valaddr_reg:x6; val_offset:5264*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5264*FLEN/8, x9, x1, x2) + +inst_2657: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x07f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x187f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5266*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5266*FLEN/8, x9, x1, x2) + +inst_2658: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x06 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x1b80; + valaddr_reg:x6; val_offset:5268*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5268*FLEN/8, x9, x1, x2) + +inst_2659: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x380 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1b80; op2val:0x7bff; + valaddr_reg:x6; val_offset:5270*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5270*FLEN/8, x9, x1, x2) + +inst_2660: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x06 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x183f; + valaddr_reg:x6; val_offset:5272*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5272*FLEN/8, x9, x1, x2) + +inst_2661: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x183f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5274*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5274*FLEN/8, x9, x1, x2) + +inst_2662: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x06 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x1bc0; + valaddr_reg:x6; val_offset:5276*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5276*FLEN/8, x9, x1, x2) + +inst_2663: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1bc0; op2val:0x7bff; + valaddr_reg:x6; val_offset:5278*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5278*FLEN/8, x9, x1, x2) + +inst_2664: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x06 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x181f; + valaddr_reg:x6; val_offset:5280*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5280*FLEN/8, x9, x1, x2) + +inst_2665: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x01f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x181f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5282*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5282*FLEN/8, x9, x1, x2) + +inst_2666: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x06 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x1be0; + valaddr_reg:x6; val_offset:5284*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5284*FLEN/8, x9, x1, x2) + +inst_2667: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1be0; op2val:0x7bff; + valaddr_reg:x6; val_offset:5286*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5286*FLEN/8, x9, x1, x2) + +inst_2668: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x06 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x180f; + valaddr_reg:x6; val_offset:5288*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5288*FLEN/8, x9, x1, x2) + +inst_2669: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x00f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x180f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5290*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5290*FLEN/8, x9, x1, x2) + +inst_2670: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x06 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x1bf0; + valaddr_reg:x6; val_offset:5292*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5292*FLEN/8, x9, x1, x2) + +inst_2671: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1bf0; op2val:0x7bff; + valaddr_reg:x6; val_offset:5294*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5294*FLEN/8, x9, x1, x2) + +inst_2672: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x06 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x1807; + valaddr_reg:x6; val_offset:5296*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5296*FLEN/8, x9, x1, x2) + +inst_2673: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1807; op2val:0x7bff; + valaddr_reg:x6; val_offset:5298*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5298*FLEN/8, x9, x1, x2) + +inst_2674: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x06 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x1bf8; + valaddr_reg:x6; val_offset:5300*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5300*FLEN/8, x9, x1, x2) + +inst_2675: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1bf8; op2val:0x7bff; + valaddr_reg:x6; val_offset:5302*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5302*FLEN/8, x9, x1, x2) + +inst_2676: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x06 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x1803; + valaddr_reg:x6; val_offset:5304*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5304*FLEN/8, x9, x1, x2) + +inst_2677: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x003 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1803; op2val:0x7bff; + valaddr_reg:x6; val_offset:5306*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5306*FLEN/8, x9, x1, x2) + +inst_2678: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x06 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x1bfc; + valaddr_reg:x6; val_offset:5308*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5308*FLEN/8, x9, x1, x2) + +inst_2679: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1bfc; op2val:0x7bff; + valaddr_reg:x6; val_offset:5310*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5310*FLEN/8, x9, x1, x2) + +inst_2680: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x06 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x1801; + valaddr_reg:x6; val_offset:5312*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5312*FLEN/8, x9, x1, x2) + +inst_2681: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1801; op2val:0x7bff; + valaddr_reg:x6; val_offset:5314*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5314*FLEN/8, x9, x1, x2) + +inst_2682: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x06 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x1bfe; + valaddr_reg:x6; val_offset:5316*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5316*FLEN/8, x9, x1, x2) + +inst_2683: +// fs1 == 0 and fe1 == 0x06 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1bfe; op2val:0x7bff; + valaddr_reg:x6; val_offset:5318*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5318*FLEN/8, x9, x1, x2) + +inst_2684: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7bfe; + valaddr_reg:x6; val_offset:5320*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5320*FLEN/8, x9, x1, x2) + +inst_2685: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bfe; op2val:0x7bff; + valaddr_reg:x6; val_offset:5322*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5322*FLEN/8, x9, x1, x2) + +inst_2686: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7801; + valaddr_reg:x6; val_offset:5324*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5324*FLEN/8, x9, x1, x2) + +inst_2687: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7801; op2val:0x7bff; + valaddr_reg:x6; val_offset:5326*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5326*FLEN/8, x9, x1, x2) + +inst_2688: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1b6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x79b6; + valaddr_reg:x6; val_offset:5328*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5328*FLEN/8, x9, x1, x2) + +inst_2689: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b6; op2val:0x7bff; + valaddr_reg:x6; val_offset:5330*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5330*FLEN/8, x9, x1, x2) + +inst_2690: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x36d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7b6d; + valaddr_reg:x6; val_offset:5332*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5332*FLEN/8, x9, x1, x2) + +inst_2691: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x36d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b6d; op2val:0x7bff; + valaddr_reg:x6; val_offset:5334*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5334*FLEN/8, x9, x1, x2) + +inst_2692: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0cc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x78cc; + valaddr_reg:x6; val_offset:5336*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5336*FLEN/8, x9, x1, x2) + +inst_2693: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0cc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x78cc; op2val:0x7bff; + valaddr_reg:x6; val_offset:5338*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5338*FLEN/8, x9, x1, x2) + +inst_2694: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x333 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7b33; + valaddr_reg:x6; val_offset:5340*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5340*FLEN/8, x9, x1, x2) + +inst_2695: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x333 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b33; op2val:0x7bff; + valaddr_reg:x6; val_offset:5342*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5342*FLEN/8, x9, x1, x2) + +inst_2696: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1dd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x79dd; + valaddr_reg:x6; val_offset:5344*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5344*FLEN/8, x9, x1, x2) + +inst_2697: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1dd and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79dd; op2val:0x7bff; + valaddr_reg:x6; val_offset:5346*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5346*FLEN/8, x9, x1, x2) + +inst_2698: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x222 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7a22; + valaddr_reg:x6; val_offset:5348*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5348*FLEN/8, x9, x1, x2) + +inst_2699: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x222 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a22; op2val:0x7bff; + valaddr_reg:x6; val_offset:5350*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5350*FLEN/8, x9, x1, x2) + +inst_2700: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x124 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7924; + valaddr_reg:x6; val_offset:5352*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5352*FLEN/8, x9, x1, x2) + +inst_2701: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x124 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7924; op2val:0x7bff; + valaddr_reg:x6; val_offset:5354*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5354*FLEN/8, x9, x1, x2) + +inst_2702: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2db and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7adb; + valaddr_reg:x6; val_offset:5356*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5356*FLEN/8, x9, x1, x2) + +inst_2703: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2db and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7adb; op2val:0x7bff; + valaddr_reg:x6; val_offset:5358*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5358*FLEN/8, x9, x1, x2) + +inst_2704: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x199 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7999; + valaddr_reg:x6; val_offset:5360*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5360*FLEN/8, x9, x1, x2) + +inst_2705: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x199 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7999; op2val:0x7bff; + valaddr_reg:x6; val_offset:5362*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5362*FLEN/8, x9, x1, x2) + +inst_2706: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x266 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7a66; + valaddr_reg:x6; val_offset:5364*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5364*FLEN/8, x9, x1, x2) + +inst_2707: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x266 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a66; op2val:0x7bff; + valaddr_reg:x6; val_offset:5366*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5366*FLEN/8, x9, x1, x2) + +inst_2708: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1a and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xebff; + valaddr_reg:x6; val_offset:5368*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5368*FLEN/8, x9, x1, x2) + +inst_2709: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xebff; op2val:0x7bff; + valaddr_reg:x6; val_offset:5370*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5370*FLEN/8, x9, x1, x2) + +inst_2710: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1a and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xe800; + valaddr_reg:x6; val_offset:5372*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5372*FLEN/8, x9, x1, x2) + +inst_2711: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xe800; op2val:0x7bff; + valaddr_reg:x6; val_offset:5374*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5374*FLEN/8, x9, x1, x2) + +inst_2712: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1a and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xe9ff; + valaddr_reg:x6; val_offset:5376*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5376*FLEN/8, x9, x1, x2) + +inst_2713: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xe9ff; op2val:0x7bff; + valaddr_reg:x6; val_offset:5378*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5378*FLEN/8, x9, x1, x2) + +inst_2714: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1a and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xea00; + valaddr_reg:x6; val_offset:5380*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5380*FLEN/8, x9, x1, x2) + +inst_2715: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xea00; op2val:0x7bff; + valaddr_reg:x6; val_offset:5382*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5382*FLEN/8, x9, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_21) + +inst_2716: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1a and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xe8ff; + valaddr_reg:x6; val_offset:5384*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5384*FLEN/8, x9, x1, x2) + +inst_2717: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xe8ff; op2val:0x7bff; + valaddr_reg:x6; val_offset:5386*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5386*FLEN/8, x9, x1, x2) + +inst_2718: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1a and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xeb00; + valaddr_reg:x6; val_offset:5388*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5388*FLEN/8, x9, x1, x2) + +inst_2719: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x300 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xeb00; op2val:0x7bff; + valaddr_reg:x6; val_offset:5390*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5390*FLEN/8, x9, x1, x2) + +inst_2720: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1a and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xe87f; + valaddr_reg:x6; val_offset:5392*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5392*FLEN/8, x9, x1, x2) + +inst_2721: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x07f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xe87f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5394*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5394*FLEN/8, x9, x1, x2) + +inst_2722: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1a and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xeb80; + valaddr_reg:x6; val_offset:5396*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5396*FLEN/8, x9, x1, x2) + +inst_2723: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x380 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xeb80; op2val:0x7bff; + valaddr_reg:x6; val_offset:5398*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5398*FLEN/8, x9, x1, x2) + +inst_2724: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1a and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xe83f; + valaddr_reg:x6; val_offset:5400*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5400*FLEN/8, x9, x1, x2) + +inst_2725: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x03f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xe83f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5402*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5402*FLEN/8, x9, x1, x2) + +inst_2726: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1a and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xebc0; + valaddr_reg:x6; val_offset:5404*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5404*FLEN/8, x9, x1, x2) + +inst_2727: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xebc0; op2val:0x7bff; + valaddr_reg:x6; val_offset:5406*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5406*FLEN/8, x9, x1, x2) + +inst_2728: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1a and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xe81f; + valaddr_reg:x6; val_offset:5408*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5408*FLEN/8, x9, x1, x2) + +inst_2729: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x01f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xe81f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5410*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5410*FLEN/8, x9, x1, x2) + +inst_2730: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1a and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xebe0; + valaddr_reg:x6; val_offset:5412*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5412*FLEN/8, x9, x1, x2) + +inst_2731: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xebe0; op2val:0x7bff; + valaddr_reg:x6; val_offset:5414*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5414*FLEN/8, x9, x1, x2) + +inst_2732: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1a and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xe80f; + valaddr_reg:x6; val_offset:5416*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5416*FLEN/8, x9, x1, x2) + +inst_2733: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x00f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xe80f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5418*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5418*FLEN/8, x9, x1, x2) + +inst_2734: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1a and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xebf0; + valaddr_reg:x6; val_offset:5420*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5420*FLEN/8, x9, x1, x2) + +inst_2735: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xebf0; op2val:0x7bff; + valaddr_reg:x6; val_offset:5422*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5422*FLEN/8, x9, x1, x2) + +inst_2736: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1a and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xe807; + valaddr_reg:x6; val_offset:5424*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5424*FLEN/8, x9, x1, x2) + +inst_2737: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x007 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xe807; op2val:0x7bff; + valaddr_reg:x6; val_offset:5426*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5426*FLEN/8, x9, x1, x2) + +inst_2738: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1a and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xebf8; + valaddr_reg:x6; val_offset:5428*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5428*FLEN/8, x9, x1, x2) + +inst_2739: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xebf8; op2val:0x7bff; + valaddr_reg:x6; val_offset:5430*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5430*FLEN/8, x9, x1, x2) + +inst_2740: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1a and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xe803; + valaddr_reg:x6; val_offset:5432*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5432*FLEN/8, x9, x1, x2) + +inst_2741: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x003 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xe803; op2val:0x7bff; + valaddr_reg:x6; val_offset:5434*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5434*FLEN/8, x9, x1, x2) + +inst_2742: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1a and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xebfc; + valaddr_reg:x6; val_offset:5436*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5436*FLEN/8, x9, x1, x2) + +inst_2743: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xebfc; op2val:0x7bff; + valaddr_reg:x6; val_offset:5438*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5438*FLEN/8, x9, x1, x2) + +inst_2744: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1a and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xe801; + valaddr_reg:x6; val_offset:5440*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5440*FLEN/8, x9, x1, x2) + +inst_2745: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xe801; op2val:0x7bff; + valaddr_reg:x6; val_offset:5442*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5442*FLEN/8, x9, x1, x2) + +inst_2746: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1a and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0xebfe; + valaddr_reg:x6; val_offset:5444*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5444*FLEN/8, x9, x1, x2) + +inst_2747: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xebfe; op2val:0x7bff; + valaddr_reg:x6; val_offset:5446*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5446*FLEN/8, x9, x1, x2) + +inst_2748: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1a and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6bff; + valaddr_reg:x6; val_offset:5448*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5448*FLEN/8, x9, x1, x2) + +inst_2749: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6bff; op2val:0x7bff; + valaddr_reg:x6; val_offset:5450*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5450*FLEN/8, x9, x1, x2) + +inst_2750: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1a and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6800; + valaddr_reg:x6; val_offset:5452*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5452*FLEN/8, x9, x1, x2) + +inst_2751: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6800; op2val:0x7bff; + valaddr_reg:x6; val_offset:5454*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5454*FLEN/8, x9, x1, x2) + +inst_2752: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1a and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x69ff; + valaddr_reg:x6; val_offset:5456*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5456*FLEN/8, x9, x1, x2) + +inst_2753: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x69ff; op2val:0x7bff; + valaddr_reg:x6; val_offset:5458*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5458*FLEN/8, x9, x1, x2) + +inst_2754: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1a and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6a00; + valaddr_reg:x6; val_offset:5460*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5460*FLEN/8, x9, x1, x2) + +inst_2755: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6a00; op2val:0x7bff; + valaddr_reg:x6; val_offset:5462*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5462*FLEN/8, x9, x1, x2) + +inst_2756: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1a and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x68ff; + valaddr_reg:x6; val_offset:5464*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5464*FLEN/8, x9, x1, x2) + +inst_2757: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x68ff; op2val:0x7bff; + valaddr_reg:x6; val_offset:5466*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5466*FLEN/8, x9, x1, x2) + +inst_2758: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1a and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6b00; + valaddr_reg:x6; val_offset:5468*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5468*FLEN/8, x9, x1, x2) + +inst_2759: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x300 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6b00; op2val:0x7bff; + valaddr_reg:x6; val_offset:5470*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5470*FLEN/8, x9, x1, x2) + +inst_2760: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1a and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x687f; + valaddr_reg:x6; val_offset:5472*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5472*FLEN/8, x9, x1, x2) + +inst_2761: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x07f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x687f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5474*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5474*FLEN/8, x9, x1, x2) + +inst_2762: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1a and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6b80; + valaddr_reg:x6; val_offset:5476*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5476*FLEN/8, x9, x1, x2) + +inst_2763: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x380 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6b80; op2val:0x7bff; + valaddr_reg:x6; val_offset:5478*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5478*FLEN/8, x9, x1, x2) + +inst_2764: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1a and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x683f; + valaddr_reg:x6; val_offset:5480*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5480*FLEN/8, x9, x1, x2) + +inst_2765: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x03f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x683f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5482*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5482*FLEN/8, x9, x1, x2) + +inst_2766: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1a and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6bc0; + valaddr_reg:x6; val_offset:5484*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5484*FLEN/8, x9, x1, x2) + +inst_2767: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6bc0; op2val:0x7bff; + valaddr_reg:x6; val_offset:5486*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5486*FLEN/8, x9, x1, x2) + +inst_2768: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1a and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x681f; + valaddr_reg:x6; val_offset:5488*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5488*FLEN/8, x9, x1, x2) + +inst_2769: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x01f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x681f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5490*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5490*FLEN/8, x9, x1, x2) + +inst_2770: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1a and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6be0; + valaddr_reg:x6; val_offset:5492*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5492*FLEN/8, x9, x1, x2) + +inst_2771: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6be0; op2val:0x7bff; + valaddr_reg:x6; val_offset:5494*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5494*FLEN/8, x9, x1, x2) + +inst_2772: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1a and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x680f; + valaddr_reg:x6; val_offset:5496*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5496*FLEN/8, x9, x1, x2) + +inst_2773: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x00f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x680f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5498*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5498*FLEN/8, x9, x1, x2) + +inst_2774: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1a and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6bf0; + valaddr_reg:x6; val_offset:5500*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5500*FLEN/8, x9, x1, x2) + +inst_2775: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6bf0; op2val:0x7bff; + valaddr_reg:x6; val_offset:5502*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5502*FLEN/8, x9, x1, x2) + +inst_2776: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1a and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6807; + valaddr_reg:x6; val_offset:5504*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5504*FLEN/8, x9, x1, x2) + +inst_2777: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x007 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6807; op2val:0x7bff; + valaddr_reg:x6; val_offset:5506*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5506*FLEN/8, x9, x1, x2) + +inst_2778: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1a and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6bf8; + valaddr_reg:x6; val_offset:5508*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5508*FLEN/8, x9, x1, x2) + +inst_2779: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6bf8; op2val:0x7bff; + valaddr_reg:x6; val_offset:5510*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5510*FLEN/8, x9, x1, x2) + +inst_2780: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1a and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6803; + valaddr_reg:x6; val_offset:5512*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5512*FLEN/8, x9, x1, x2) + +inst_2781: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x003 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6803; op2val:0x7bff; + valaddr_reg:x6; val_offset:5514*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5514*FLEN/8, x9, x1, x2) + +inst_2782: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1a and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6bfc; + valaddr_reg:x6; val_offset:5516*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5516*FLEN/8, x9, x1, x2) + +inst_2783: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6bfc; op2val:0x7bff; + valaddr_reg:x6; val_offset:5518*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5518*FLEN/8, x9, x1, x2) + +inst_2784: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1a and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6801; + valaddr_reg:x6; val_offset:5520*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5520*FLEN/8, x9, x1, x2) + +inst_2785: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6801; op2val:0x7bff; + valaddr_reg:x6; val_offset:5522*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5522*FLEN/8, x9, x1, x2) + +inst_2786: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1a and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6bfe; + valaddr_reg:x6; val_offset:5524*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5524*FLEN/8, x9, x1, x2) + +inst_2787: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6bfe; op2val:0x7bff; + valaddr_reg:x6; val_offset:5526*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5526*FLEN/8, x9, x1, x2) + +inst_2788: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6fff; + valaddr_reg:x6; val_offset:5528*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5528*FLEN/8, x9, x1, x2) + +inst_2789: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6fff; op2val:0x7bff; + valaddr_reg:x6; val_offset:5530*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5530*FLEN/8, x9, x1, x2) + +inst_2790: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1b and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6c00; + valaddr_reg:x6; val_offset:5532*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5532*FLEN/8, x9, x1, x2) + +inst_2791: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c00; op2val:0x7bff; + valaddr_reg:x6; val_offset:5534*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5534*FLEN/8, x9, x1, x2) + +inst_2792: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1b and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6dff; + valaddr_reg:x6; val_offset:5536*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5536*FLEN/8, x9, x1, x2) + +inst_2793: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6dff; op2val:0x7bff; + valaddr_reg:x6; val_offset:5538*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5538*FLEN/8, x9, x1, x2) + +inst_2794: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1b and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6e00; + valaddr_reg:x6; val_offset:5540*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5540*FLEN/8, x9, x1, x2) + +inst_2795: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e00; op2val:0x7bff; + valaddr_reg:x6; val_offset:5542*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5542*FLEN/8, x9, x1, x2) + +inst_2796: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6cff; + valaddr_reg:x6; val_offset:5544*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5544*FLEN/8, x9, x1, x2) + +inst_2797: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6cff; op2val:0x7bff; + valaddr_reg:x6; val_offset:5546*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5546*FLEN/8, x9, x1, x2) + +inst_2798: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1b and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6f00; + valaddr_reg:x6; val_offset:5548*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5548*FLEN/8, x9, x1, x2) + +inst_2799: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x300 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f00; op2val:0x7bff; + valaddr_reg:x6; val_offset:5550*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5550*FLEN/8, x9, x1, x2) + +inst_2800: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1b and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6c7f; + valaddr_reg:x6; val_offset:5552*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5552*FLEN/8, x9, x1, x2) + +inst_2801: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x07f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c7f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5554*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5554*FLEN/8, x9, x1, x2) + +inst_2802: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1b and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6f80; + valaddr_reg:x6; val_offset:5556*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5556*FLEN/8, x9, x1, x2) + +inst_2803: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x380 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f80; op2val:0x7bff; + valaddr_reg:x6; val_offset:5558*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5558*FLEN/8, x9, x1, x2) + +inst_2804: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1b and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6c3f; + valaddr_reg:x6; val_offset:5560*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5560*FLEN/8, x9, x1, x2) + +inst_2805: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x03f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c3f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5562*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5562*FLEN/8, x9, x1, x2) + +inst_2806: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6fc0; + valaddr_reg:x6; val_offset:5564*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5564*FLEN/8, x9, x1, x2) + +inst_2807: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6fc0; op2val:0x7bff; + valaddr_reg:x6; val_offset:5566*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5566*FLEN/8, x9, x1, x2) + +inst_2808: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1b and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6c1f; + valaddr_reg:x6; val_offset:5568*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5568*FLEN/8, x9, x1, x2) + +inst_2809: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x01f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c1f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5570*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5570*FLEN/8, x9, x1, x2) + +inst_2810: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6fe0; + valaddr_reg:x6; val_offset:5572*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5572*FLEN/8, x9, x1, x2) + +inst_2811: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6fe0; op2val:0x7bff; + valaddr_reg:x6; val_offset:5574*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5574*FLEN/8, x9, x1, x2) + +inst_2812: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1b and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6c0f; + valaddr_reg:x6; val_offset:5576*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5576*FLEN/8, x9, x1, x2) + +inst_2813: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x00f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c0f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5578*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5578*FLEN/8, x9, x1, x2) + +inst_2814: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6ff0; + valaddr_reg:x6; val_offset:5580*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5580*FLEN/8, x9, x1, x2) + +inst_2815: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ff0; op2val:0x7bff; + valaddr_reg:x6; val_offset:5582*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5582*FLEN/8, x9, x1, x2) + +inst_2816: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1b and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6c07; + valaddr_reg:x6; val_offset:5584*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5584*FLEN/8, x9, x1, x2) + +inst_2817: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x007 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c07; op2val:0x7bff; + valaddr_reg:x6; val_offset:5586*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5586*FLEN/8, x9, x1, x2) + +inst_2818: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6ff8; + valaddr_reg:x6; val_offset:5588*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5588*FLEN/8, x9, x1, x2) + +inst_2819: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ff8; op2val:0x7bff; + valaddr_reg:x6; val_offset:5590*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5590*FLEN/8, x9, x1, x2) + +inst_2820: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1b and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6c03; + valaddr_reg:x6; val_offset:5592*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5592*FLEN/8, x9, x1, x2) + +inst_2821: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x003 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c03; op2val:0x7bff; + valaddr_reg:x6; val_offset:5594*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5594*FLEN/8, x9, x1, x2) + +inst_2822: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6ffc; + valaddr_reg:x6; val_offset:5596*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5596*FLEN/8, x9, x1, x2) + +inst_2823: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ffc; op2val:0x7bff; + valaddr_reg:x6; val_offset:5598*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5598*FLEN/8, x9, x1, x2) + +inst_2824: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1b and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6c01; + valaddr_reg:x6; val_offset:5600*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5600*FLEN/8, x9, x1, x2) + +inst_2825: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6c01; op2val:0x7bff; + valaddr_reg:x6; val_offset:5602*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5602*FLEN/8, x9, x1, x2) + +inst_2826: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x6ffe; + valaddr_reg:x6; val_offset:5604*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5604*FLEN/8, x9, x1, x2) + +inst_2827: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ffe; op2val:0x7bff; + valaddr_reg:x6; val_offset:5606*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5606*FLEN/8, x9, x1, x2) + +inst_2828: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x73ff; + valaddr_reg:x6; val_offset:5608*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5608*FLEN/8, x9, x1, x2) + +inst_2829: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x73ff; op2val:0x7bff; + valaddr_reg:x6; val_offset:5610*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5610*FLEN/8, x9, x1, x2) + +inst_2830: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1c and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7000; + valaddr_reg:x6; val_offset:5612*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5612*FLEN/8, x9, x1, x2) + +inst_2831: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7000; op2val:0x7bff; + valaddr_reg:x6; val_offset:5614*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5614*FLEN/8, x9, x1, x2) + +inst_2832: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x71ff; + valaddr_reg:x6; val_offset:5616*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5616*FLEN/8, x9, x1, x2) + +inst_2833: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x71ff; op2val:0x7bff; + valaddr_reg:x6; val_offset:5618*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5618*FLEN/8, x9, x1, x2) + +inst_2834: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1c and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7200; + valaddr_reg:x6; val_offset:5620*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5620*FLEN/8, x9, x1, x2) + +inst_2835: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7200; op2val:0x7bff; + valaddr_reg:x6; val_offset:5622*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5622*FLEN/8, x9, x1, x2) + +inst_2836: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x70ff; + valaddr_reg:x6; val_offset:5624*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5624*FLEN/8, x9, x1, x2) + +inst_2837: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x70ff; op2val:0x7bff; + valaddr_reg:x6; val_offset:5626*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5626*FLEN/8, x9, x1, x2) + +inst_2838: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1c and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7300; + valaddr_reg:x6; val_offset:5628*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5628*FLEN/8, x9, x1, x2) + +inst_2839: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x300 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7300; op2val:0x7bff; + valaddr_reg:x6; val_offset:5630*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5630*FLEN/8, x9, x1, x2) + +inst_2840: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1c and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x707f; + valaddr_reg:x6; val_offset:5632*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5632*FLEN/8, x9, x1, x2) + +inst_2841: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x07f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x707f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5634*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5634*FLEN/8, x9, x1, x2) + +inst_2842: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1c and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7380; + valaddr_reg:x6; val_offset:5636*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5636*FLEN/8, x9, x1, x2) + +inst_2843: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x380 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7380; op2val:0x7bff; + valaddr_reg:x6; val_offset:5638*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5638*FLEN/8, x9, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_22) + +inst_2844: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1c and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x703f; + valaddr_reg:x6; val_offset:5640*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5640*FLEN/8, x9, x1, x2) + +inst_2845: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x03f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x703f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5642*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5642*FLEN/8, x9, x1, x2) + +inst_2846: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x73c0; + valaddr_reg:x6; val_offset:5644*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5644*FLEN/8, x9, x1, x2) + +inst_2847: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x73c0; op2val:0x7bff; + valaddr_reg:x6; val_offset:5646*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5646*FLEN/8, x9, x1, x2) + +inst_2848: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1c and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x701f; + valaddr_reg:x6; val_offset:5648*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5648*FLEN/8, x9, x1, x2) + +inst_2849: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x01f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x701f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5650*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5650*FLEN/8, x9, x1, x2) + +inst_2850: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x73e0; + valaddr_reg:x6; val_offset:5652*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5652*FLEN/8, x9, x1, x2) + +inst_2851: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x73e0; op2val:0x7bff; + valaddr_reg:x6; val_offset:5654*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5654*FLEN/8, x9, x1, x2) + +inst_2852: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1c and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x700f; + valaddr_reg:x6; val_offset:5656*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5656*FLEN/8, x9, x1, x2) + +inst_2853: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x00f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x700f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5658*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5658*FLEN/8, x9, x1, x2) + +inst_2854: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x73f0; + valaddr_reg:x6; val_offset:5660*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5660*FLEN/8, x9, x1, x2) + +inst_2855: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x73f0; op2val:0x7bff; + valaddr_reg:x6; val_offset:5662*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5662*FLEN/8, x9, x1, x2) + +inst_2856: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1c and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7007; + valaddr_reg:x6; val_offset:5664*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5664*FLEN/8, x9, x1, x2) + +inst_2857: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x007 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7007; op2val:0x7bff; + valaddr_reg:x6; val_offset:5666*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5666*FLEN/8, x9, x1, x2) + +inst_2858: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x73f8; + valaddr_reg:x6; val_offset:5668*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5668*FLEN/8, x9, x1, x2) + +inst_2859: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x73f8; op2val:0x7bff; + valaddr_reg:x6; val_offset:5670*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5670*FLEN/8, x9, x1, x2) + +inst_2860: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1c and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7003; + valaddr_reg:x6; val_offset:5672*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5672*FLEN/8, x9, x1, x2) + +inst_2861: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x003 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7003; op2val:0x7bff; + valaddr_reg:x6; val_offset:5674*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5674*FLEN/8, x9, x1, x2) + +inst_2862: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x73fc; + valaddr_reg:x6; val_offset:5676*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5676*FLEN/8, x9, x1, x2) + +inst_2863: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x73fc; op2val:0x7bff; + valaddr_reg:x6; val_offset:5678*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5678*FLEN/8, x9, x1, x2) + +inst_2864: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1c and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7001; + valaddr_reg:x6; val_offset:5680*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5680*FLEN/8, x9, x1, x2) + +inst_2865: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7001; op2val:0x7bff; + valaddr_reg:x6; val_offset:5682*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5682*FLEN/8, x9, x1, x2) + +inst_2866: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x73fe; + valaddr_reg:x6; val_offset:5684*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5684*FLEN/8, x9, x1, x2) + +inst_2867: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x73fe; op2val:0x7bff; + valaddr_reg:x6; val_offset:5686*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5686*FLEN/8, x9, x1, x2) + +inst_2868: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x77ff; + valaddr_reg:x6; val_offset:5688*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5688*FLEN/8, x9, x1, x2) + +inst_2869: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x77ff; op2val:0x7bff; + valaddr_reg:x6; val_offset:5690*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5690*FLEN/8, x9, x1, x2) + +inst_2870: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1d and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7400; + valaddr_reg:x6; val_offset:5692*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5692*FLEN/8, x9, x1, x2) + +inst_2871: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7400; op2val:0x7bff; + valaddr_reg:x6; val_offset:5694*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5694*FLEN/8, x9, x1, x2) + +inst_2872: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x75ff; + valaddr_reg:x6; val_offset:5696*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5696*FLEN/8, x9, x1, x2) + +inst_2873: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x75ff; op2val:0x7bff; + valaddr_reg:x6; val_offset:5698*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5698*FLEN/8, x9, x1, x2) + +inst_2874: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1d and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7600; + valaddr_reg:x6; val_offset:5700*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5700*FLEN/8, x9, x1, x2) + +inst_2875: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7600; op2val:0x7bff; + valaddr_reg:x6; val_offset:5702*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5702*FLEN/8, x9, x1, x2) + +inst_2876: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x74ff; + valaddr_reg:x6; val_offset:5704*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5704*FLEN/8, x9, x1, x2) + +inst_2877: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74ff; op2val:0x7bff; + valaddr_reg:x6; val_offset:5706*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5706*FLEN/8, x9, x1, x2) + +inst_2878: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1d and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7700; + valaddr_reg:x6; val_offset:5708*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5708*FLEN/8, x9, x1, x2) + +inst_2879: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x300 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7700; op2val:0x7bff; + valaddr_reg:x6; val_offset:5710*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5710*FLEN/8, x9, x1, x2) + +inst_2880: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1d and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x747f; + valaddr_reg:x6; val_offset:5712*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5712*FLEN/8, x9, x1, x2) + +inst_2881: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x07f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x747f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5714*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5714*FLEN/8, x9, x1, x2) + +inst_2882: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1d and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7780; + valaddr_reg:x6; val_offset:5716*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5716*FLEN/8, x9, x1, x2) + +inst_2883: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x380 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7780; op2val:0x7bff; + valaddr_reg:x6; val_offset:5718*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5718*FLEN/8, x9, x1, x2) + +inst_2884: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1d and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x743f; + valaddr_reg:x6; val_offset:5720*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5720*FLEN/8, x9, x1, x2) + +inst_2885: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x03f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x743f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5722*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5722*FLEN/8, x9, x1, x2) + +inst_2886: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x77c0; + valaddr_reg:x6; val_offset:5724*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5724*FLEN/8, x9, x1, x2) + +inst_2887: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x77c0; op2val:0x7bff; + valaddr_reg:x6; val_offset:5726*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5726*FLEN/8, x9, x1, x2) + +inst_2888: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1d and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x741f; + valaddr_reg:x6; val_offset:5728*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5728*FLEN/8, x9, x1, x2) + +inst_2889: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x01f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x741f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5730*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5730*FLEN/8, x9, x1, x2) + +inst_2890: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x77e0; + valaddr_reg:x6; val_offset:5732*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5732*FLEN/8, x9, x1, x2) + +inst_2891: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x77e0; op2val:0x7bff; + valaddr_reg:x6; val_offset:5734*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5734*FLEN/8, x9, x1, x2) + +inst_2892: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1d and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x740f; + valaddr_reg:x6; val_offset:5736*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5736*FLEN/8, x9, x1, x2) + +inst_2893: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x00f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x740f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5738*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5738*FLEN/8, x9, x1, x2) + +inst_2894: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x77f0; + valaddr_reg:x6; val_offset:5740*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5740*FLEN/8, x9, x1, x2) + +inst_2895: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x77f0; op2val:0x7bff; + valaddr_reg:x6; val_offset:5742*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5742*FLEN/8, x9, x1, x2) + +inst_2896: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1d and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7407; + valaddr_reg:x6; val_offset:5744*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5744*FLEN/8, x9, x1, x2) + +inst_2897: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x007 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7407; op2val:0x7bff; + valaddr_reg:x6; val_offset:5746*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5746*FLEN/8, x9, x1, x2) + +inst_2898: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x77f8; + valaddr_reg:x6; val_offset:5748*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5748*FLEN/8, x9, x1, x2) + +inst_2899: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x77f8; op2val:0x7bff; + valaddr_reg:x6; val_offset:5750*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5750*FLEN/8, x9, x1, x2) + +inst_2900: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1d and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7403; + valaddr_reg:x6; val_offset:5752*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5752*FLEN/8, x9, x1, x2) + +inst_2901: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x003 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7403; op2val:0x7bff; + valaddr_reg:x6; val_offset:5754*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5754*FLEN/8, x9, x1, x2) + +inst_2902: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x77fc; + valaddr_reg:x6; val_offset:5756*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5756*FLEN/8, x9, x1, x2) + +inst_2903: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x77fc; op2val:0x7bff; + valaddr_reg:x6; val_offset:5758*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5758*FLEN/8, x9, x1, x2) + +inst_2904: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1d and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7401; + valaddr_reg:x6; val_offset:5760*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5760*FLEN/8, x9, x1, x2) + +inst_2905: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7401; op2val:0x7bff; + valaddr_reg:x6; val_offset:5762*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5762*FLEN/8, x9, x1, x2) + +inst_2906: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x77fe; + valaddr_reg:x6; val_offset:5764*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5764*FLEN/8, x9, x1, x2) + +inst_2907: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x77fe; op2val:0x7bff; + valaddr_reg:x6; val_offset:5766*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5766*FLEN/8, x9, x1, x2) + +inst_2908: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7bff; + valaddr_reg:x6; val_offset:5768*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5768*FLEN/8, x9, x1, x2) + +inst_2909: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7800; + valaddr_reg:x6; val_offset:5770*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5770*FLEN/8, x9, x1, x2) + +inst_2910: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7800; op2val:0x7bff; + valaddr_reg:x6; val_offset:5772*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5772*FLEN/8, x9, x1, x2) + +inst_2911: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x79ff; + valaddr_reg:x6; val_offset:5774*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5774*FLEN/8, x9, x1, x2) + +inst_2912: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79ff; op2val:0x7bff; + valaddr_reg:x6; val_offset:5776*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5776*FLEN/8, x9, x1, x2) + +inst_2913: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7a00; + valaddr_reg:x6; val_offset:5778*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5778*FLEN/8, x9, x1, x2) + +inst_2914: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a00; op2val:0x7bff; + valaddr_reg:x6; val_offset:5780*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5780*FLEN/8, x9, x1, x2) + +inst_2915: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x78ff; + valaddr_reg:x6; val_offset:5782*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5782*FLEN/8, x9, x1, x2) + +inst_2916: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x78ff; op2val:0x7bff; + valaddr_reg:x6; val_offset:5784*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5784*FLEN/8, x9, x1, x2) + +inst_2917: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7b00; + valaddr_reg:x6; val_offset:5786*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5786*FLEN/8, x9, x1, x2) + +inst_2918: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x300 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b00; op2val:0x7bff; + valaddr_reg:x6; val_offset:5788*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5788*FLEN/8, x9, x1, x2) + +inst_2919: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x787f; + valaddr_reg:x6; val_offset:5790*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5790*FLEN/8, x9, x1, x2) + +inst_2920: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x07f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x787f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5792*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5792*FLEN/8, x9, x1, x2) + +inst_2921: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7b80; + valaddr_reg:x6; val_offset:5794*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5794*FLEN/8, x9, x1, x2) + +inst_2922: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x380 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b80; op2val:0x7bff; + valaddr_reg:x6; val_offset:5796*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5796*FLEN/8, x9, x1, x2) + +inst_2923: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x783f; + valaddr_reg:x6; val_offset:5798*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5798*FLEN/8, x9, x1, x2) + +inst_2924: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x03f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x783f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5800*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5800*FLEN/8, x9, x1, x2) + +inst_2925: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7bc0; + valaddr_reg:x6; val_offset:5802*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5802*FLEN/8, x9, x1, x2) + +inst_2926: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bc0; op2val:0x7bff; + valaddr_reg:x6; val_offset:5804*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5804*FLEN/8, x9, x1, x2) + +inst_2927: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x781f; + valaddr_reg:x6; val_offset:5806*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5806*FLEN/8, x9, x1, x2) + +inst_2928: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x01f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x781f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5808*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5808*FLEN/8, x9, x1, x2) + +inst_2929: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7be0; + valaddr_reg:x6; val_offset:5810*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5810*FLEN/8, x9, x1, x2) + +inst_2930: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7be0; op2val:0x7bff; + valaddr_reg:x6; val_offset:5812*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5812*FLEN/8, x9, x1, x2) + +inst_2931: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x780f; + valaddr_reg:x6; val_offset:5814*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5814*FLEN/8, x9, x1, x2) + +inst_2932: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x780f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5816*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5816*FLEN/8, x9, x1, x2) + +inst_2933: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7bf0; + valaddr_reg:x6; val_offset:5818*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5818*FLEN/8, x9, x1, x2) + +inst_2934: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bf0; op2val:0x7bff; + valaddr_reg:x6; val_offset:5820*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5820*FLEN/8, x9, x1, x2) + +inst_2935: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7807; + valaddr_reg:x6; val_offset:5822*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5822*FLEN/8, x9, x1, x2) + +inst_2936: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x007 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7807; op2val:0x7bff; + valaddr_reg:x6; val_offset:5824*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5824*FLEN/8, x9, x1, x2) + +inst_2937: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7bf8; + valaddr_reg:x6; val_offset:5826*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5826*FLEN/8, x9, x1, x2) + +inst_2938: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bf8; op2val:0x7bff; + valaddr_reg:x6; val_offset:5828*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5828*FLEN/8, x9, x1, x2) + +inst_2939: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7803; + valaddr_reg:x6; val_offset:5830*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5830*FLEN/8, x9, x1, x2) + +inst_2940: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x003 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7803; op2val:0x7bff; + valaddr_reg:x6; val_offset:5832*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5832*FLEN/8, x9, x1, x2) + +inst_2941: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x7bfc; + valaddr_reg:x6; val_offset:5834*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5834*FLEN/8, x9, x1, x2) + +inst_2942: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bfc; op2val:0x7bff; + valaddr_reg:x6; val_offset:5836*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5836*FLEN/8, x9, x1, x2) + +inst_2943: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x83ff; + valaddr_reg:x6; val_offset:5838*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5838*FLEN/8, x9, x1, x2) + +inst_2944: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0x7bff; + valaddr_reg:x6; val_offset:5840*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5840*FLEN/8, x9, x1, x2) + +inst_2945: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8001; + valaddr_reg:x6; val_offset:5842*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5842*FLEN/8, x9, x1, x2) + +inst_2946: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0x7bff; + valaddr_reg:x6; val_offset:5844*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5844*FLEN/8, x9, x1, x2) + +inst_2947: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x81ff; + valaddr_reg:x6; val_offset:5846*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5846*FLEN/8, x9, x1, x2) + +inst_2948: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x81ff; op2val:0x7bff; + valaddr_reg:x6; val_offset:5848*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5848*FLEN/8, x9, x1, x2) + +inst_2949: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8200; + valaddr_reg:x6; val_offset:5850*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5850*FLEN/8, x9, x1, x2) + +inst_2950: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8200; op2val:0x7bff; + valaddr_reg:x6; val_offset:5852*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5852*FLEN/8, x9, x1, x2) + +inst_2951: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x80ff; + valaddr_reg:x6; val_offset:5854*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5854*FLEN/8, x9, x1, x2) + +inst_2952: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x80ff; op2val:0x7bff; + valaddr_reg:x6; val_offset:5856*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5856*FLEN/8, x9, x1, x2) + +inst_2953: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8300; + valaddr_reg:x6; val_offset:5858*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5858*FLEN/8, x9, x1, x2) + +inst_2954: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x300 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8300; op2val:0x7bff; + valaddr_reg:x6; val_offset:5860*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5860*FLEN/8, x9, x1, x2) + +inst_2955: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x807f; + valaddr_reg:x6; val_offset:5862*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5862*FLEN/8, x9, x1, x2) + +inst_2956: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x07f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x807f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5864*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5864*FLEN/8, x9, x1, x2) + +inst_2957: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8380; + valaddr_reg:x6; val_offset:5866*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5866*FLEN/8, x9, x1, x2) + +inst_2958: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x380 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8380; op2val:0x7bff; + valaddr_reg:x6; val_offset:5868*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5868*FLEN/8, x9, x1, x2) + +inst_2959: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x803f; + valaddr_reg:x6; val_offset:5870*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5870*FLEN/8, x9, x1, x2) + +inst_2960: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x803f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5872*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5872*FLEN/8, x9, x1, x2) + +inst_2961: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x83c0; + valaddr_reg:x6; val_offset:5874*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5874*FLEN/8, x9, x1, x2) + +inst_2962: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83c0; op2val:0x7bff; + valaddr_reg:x6; val_offset:5876*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5876*FLEN/8, x9, x1, x2) + +inst_2963: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x801f; + valaddr_reg:x6; val_offset:5878*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5878*FLEN/8, x9, x1, x2) + +inst_2964: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x01f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x801f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5880*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5880*FLEN/8, x9, x1, x2) + +inst_2965: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x83e0; + valaddr_reg:x6; val_offset:5882*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5882*FLEN/8, x9, x1, x2) + +inst_2966: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83e0; op2val:0x7bff; + valaddr_reg:x6; val_offset:5884*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5884*FLEN/8, x9, x1, x2) + +inst_2967: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x800f; + valaddr_reg:x6; val_offset:5886*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5886*FLEN/8, x9, x1, x2) + +inst_2968: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x00f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x800f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5888*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5888*FLEN/8, x9, x1, x2) + +inst_2969: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x83f0; + valaddr_reg:x6; val_offset:5890*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5890*FLEN/8, x9, x1, x2) + +inst_2970: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83f0; op2val:0x7bff; + valaddr_reg:x6; val_offset:5892*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5892*FLEN/8, x9, x1, x2) + +inst_2971: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8007; + valaddr_reg:x6; val_offset:5894*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5894*FLEN/8, x9, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_23) + +inst_2972: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8007; op2val:0x7bff; + valaddr_reg:x6; val_offset:5896*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5896*FLEN/8, x9, x1, x2) + +inst_2973: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x83f8; + valaddr_reg:x6; val_offset:5898*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5898*FLEN/8, x9, x1, x2) + +inst_2974: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83f8; op2val:0x7bff; + valaddr_reg:x6; val_offset:5900*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5900*FLEN/8, x9, x1, x2) + +inst_2975: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8003; + valaddr_reg:x6; val_offset:5902*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5902*FLEN/8, x9, x1, x2) + +inst_2976: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x003 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8003; op2val:0x7bff; + valaddr_reg:x6; val_offset:5904*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5904*FLEN/8, x9, x1, x2) + +inst_2977: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x83fc; + valaddr_reg:x6; val_offset:5906*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5906*FLEN/8, x9, x1, x2) + +inst_2978: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fc; op2val:0x7bff; + valaddr_reg:x6; val_offset:5908*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5908*FLEN/8, x9, x1, x2) + +inst_2979: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x83fe; + valaddr_reg:x6; val_offset:5910*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5910*FLEN/8, x9, x1, x2) + +inst_2980: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0x7bff; + valaddr_reg:x6; val_offset:5912*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5912*FLEN/8, x9, x1, x2) + +inst_2981: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x87ff; + valaddr_reg:x6; val_offset:5914*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5914*FLEN/8, x9, x1, x2) + +inst_2982: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x87ff; op2val:0x7bff; + valaddr_reg:x6; val_offset:5916*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5916*FLEN/8, x9, x1, x2) + +inst_2983: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8400; + valaddr_reg:x6; val_offset:5918*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5918*FLEN/8, x9, x1, x2) + +inst_2984: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0x7bff; + valaddr_reg:x6; val_offset:5920*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5920*FLEN/8, x9, x1, x2) + +inst_2985: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x85ff; + valaddr_reg:x6; val_offset:5922*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5922*FLEN/8, x9, x1, x2) + +inst_2986: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x85ff; op2val:0x7bff; + valaddr_reg:x6; val_offset:5924*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5924*FLEN/8, x9, x1, x2) + +inst_2987: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8600; + valaddr_reg:x6; val_offset:5926*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5926*FLEN/8, x9, x1, x2) + +inst_2988: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x200 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8600; op2val:0x7bff; + valaddr_reg:x6; val_offset:5928*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5928*FLEN/8, x9, x1, x2) + +inst_2989: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x84ff; + valaddr_reg:x6; val_offset:5930*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5930*FLEN/8, x9, x1, x2) + +inst_2990: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x0ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x84ff; op2val:0x7bff; + valaddr_reg:x6; val_offset:5932*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5932*FLEN/8, x9, x1, x2) + +inst_2991: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8700; + valaddr_reg:x6; val_offset:5934*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5934*FLEN/8, x9, x1, x2) + +inst_2992: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x300 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8700; op2val:0x7bff; + valaddr_reg:x6; val_offset:5936*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5936*FLEN/8, x9, x1, x2) + +inst_2993: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x847f; + valaddr_reg:x6; val_offset:5938*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5938*FLEN/8, x9, x1, x2) + +inst_2994: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x07f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x847f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5940*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5940*FLEN/8, x9, x1, x2) + +inst_2995: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8780; + valaddr_reg:x6; val_offset:5942*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5942*FLEN/8, x9, x1, x2) + +inst_2996: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x380 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8780; op2val:0x7bff; + valaddr_reg:x6; val_offset:5944*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5944*FLEN/8, x9, x1, x2) + +inst_2997: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x843f; + valaddr_reg:x6; val_offset:5946*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5946*FLEN/8, x9, x1, x2) + +inst_2998: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x843f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5948*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5948*FLEN/8, x9, x1, x2) + +inst_2999: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x87c0; + valaddr_reg:x6; val_offset:5950*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5950*FLEN/8, x9, x1, x2) + +inst_3000: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x87c0; op2val:0x7bff; + valaddr_reg:x6; val_offset:5952*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5952*FLEN/8, x9, x1, x2) + +inst_3001: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x841f; + valaddr_reg:x6; val_offset:5954*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5954*FLEN/8, x9, x1, x2) + +inst_3002: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x01f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x841f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5956*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5956*FLEN/8, x9, x1, x2) + +inst_3003: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x87e0; + valaddr_reg:x6; val_offset:5958*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5958*FLEN/8, x9, x1, x2) + +inst_3004: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x87e0; op2val:0x7bff; + valaddr_reg:x6; val_offset:5960*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5960*FLEN/8, x9, x1, x2) + +inst_3005: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x840f; + valaddr_reg:x6; val_offset:5962*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5962*FLEN/8, x9, x1, x2) + +inst_3006: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x00f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x840f; op2val:0x7bff; + valaddr_reg:x6; val_offset:5964*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5964*FLEN/8, x9, x1, x2) + +inst_3007: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x87f0; + valaddr_reg:x6; val_offset:5966*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5966*FLEN/8, x9, x1, x2) + +inst_3008: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3f0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x87f0; op2val:0x7bff; + valaddr_reg:x6; val_offset:5968*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5968*FLEN/8, x9, x1, x2) + +inst_3009: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8407; + valaddr_reg:x6; val_offset:5970*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5970*FLEN/8, x9, x1, x2) + +inst_3010: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8407; op2val:0x7bff; + valaddr_reg:x6; val_offset:5972*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5972*FLEN/8, x9, x1, x2) + +inst_3011: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x87f8; + valaddr_reg:x6; val_offset:5974*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5974*FLEN/8, x9, x1, x2) + +inst_3012: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3f8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x87f8; op2val:0x7bff; + valaddr_reg:x6; val_offset:5976*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5976*FLEN/8, x9, x1, x2) + +inst_3013: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8403; + valaddr_reg:x6; val_offset:5978*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5978*FLEN/8, x9, x1, x2) + +inst_3014: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x003 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8403; op2val:0x7bff; + valaddr_reg:x6; val_offset:5980*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5980*FLEN/8, x9, x1, x2) + +inst_3015: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x87fc; + valaddr_reg:x6; val_offset:5982*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5982*FLEN/8, x9, x1, x2) + +inst_3016: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x87fc; op2val:0x7bff; + valaddr_reg:x6; val_offset:5984*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5984*FLEN/8, x9, x1, x2) + +inst_3017: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x8401; + valaddr_reg:x6; val_offset:5986*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5986*FLEN/8, x9, x1, x2) + +inst_3018: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8401; op2val:0x7bff; + valaddr_reg:x6; val_offset:5988*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5988*FLEN/8, x9, x1, x2) + +inst_3019: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bff; op2val:0x87fe; + valaddr_reg:x6; val_offset:5990*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5990*FLEN/8, x9, x1, x2) + +inst_3020: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x87fe; op2val:0x7bff; + valaddr_reg:x6; val_offset:5992*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5992*FLEN/8, x9, x1, x2) + +inst_3021: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xbfff; + valaddr_reg:x6; val_offset:5994*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5994*FLEN/8, x9, x1, x2) + +inst_3022: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbfff; op2val:0xfbff; + valaddr_reg:x6; val_offset:5996*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5996*FLEN/8, x9, x1, x2) + +inst_3023: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xbc00; + valaddr_reg:x6; val_offset:5998*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 5998*FLEN/8, x9, x1, x2) + +inst_3024: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc00; op2val:0xfbff; + valaddr_reg:x6; val_offset:6000*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6000*FLEN/8, x9, x1, x2) + +inst_3025: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xbdff; + valaddr_reg:x6; val_offset:6002*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6002*FLEN/8, x9, x1, x2) + +inst_3026: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbdff; op2val:0xfbff; + valaddr_reg:x6; val_offset:6004*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6004*FLEN/8, x9, x1, x2) + +inst_3027: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xbe00; + valaddr_reg:x6; val_offset:6006*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6006*FLEN/8, x9, x1, x2) + +inst_3028: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbe00; op2val:0xfbff; + valaddr_reg:x6; val_offset:6008*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6008*FLEN/8, x9, x1, x2) + +inst_3029: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xbcff; + valaddr_reg:x6; val_offset:6010*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6010*FLEN/8, x9, x1, x2) + +inst_3030: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbcff; op2val:0xfbff; + valaddr_reg:x6; val_offset:6012*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6012*FLEN/8, x9, x1, x2) + +inst_3031: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xbf00; + valaddr_reg:x6; val_offset:6014*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6014*FLEN/8, x9, x1, x2) + +inst_3032: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x300 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbf00; op2val:0xfbff; + valaddr_reg:x6; val_offset:6016*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6016*FLEN/8, x9, x1, x2) + +inst_3033: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xbc7f; + valaddr_reg:x6; val_offset:6018*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6018*FLEN/8, x9, x1, x2) + +inst_3034: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x07f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc7f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6020*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6020*FLEN/8, x9, x1, x2) + +inst_3035: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xbf80; + valaddr_reg:x6; val_offset:6022*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6022*FLEN/8, x9, x1, x2) + +inst_3036: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x380 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbf80; op2val:0xfbff; + valaddr_reg:x6; val_offset:6024*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6024*FLEN/8, x9, x1, x2) + +inst_3037: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xbc3f; + valaddr_reg:x6; val_offset:6026*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6026*FLEN/8, x9, x1, x2) + +inst_3038: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x03f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc3f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6028*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6028*FLEN/8, x9, x1, x2) + +inst_3039: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xbfc0; + valaddr_reg:x6; val_offset:6030*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6030*FLEN/8, x9, x1, x2) + +inst_3040: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbfc0; op2val:0xfbff; + valaddr_reg:x6; val_offset:6032*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6032*FLEN/8, x9, x1, x2) + +inst_3041: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xbc1f; + valaddr_reg:x6; val_offset:6034*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6034*FLEN/8, x9, x1, x2) + +inst_3042: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x01f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc1f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6036*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6036*FLEN/8, x9, x1, x2) + +inst_3043: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xbfe0; + valaddr_reg:x6; val_offset:6038*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6038*FLEN/8, x9, x1, x2) + +inst_3044: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbfe0; op2val:0xfbff; + valaddr_reg:x6; val_offset:6040*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6040*FLEN/8, x9, x1, x2) + +inst_3045: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xbc0f; + valaddr_reg:x6; val_offset:6042*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6042*FLEN/8, x9, x1, x2) + +inst_3046: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x00f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc0f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6044*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6044*FLEN/8, x9, x1, x2) + +inst_3047: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xbff0; + valaddr_reg:x6; val_offset:6046*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6046*FLEN/8, x9, x1, x2) + +inst_3048: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbff0; op2val:0xfbff; + valaddr_reg:x6; val_offset:6048*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6048*FLEN/8, x9, x1, x2) + +inst_3049: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xbc07; + valaddr_reg:x6; val_offset:6050*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6050*FLEN/8, x9, x1, x2) + +inst_3050: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x007 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc07; op2val:0xfbff; + valaddr_reg:x6; val_offset:6052*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6052*FLEN/8, x9, x1, x2) + +inst_3051: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xbff8; + valaddr_reg:x6; val_offset:6054*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6054*FLEN/8, x9, x1, x2) + +inst_3052: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbff8; op2val:0xfbff; + valaddr_reg:x6; val_offset:6056*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6056*FLEN/8, x9, x1, x2) + +inst_3053: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xbc03; + valaddr_reg:x6; val_offset:6058*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6058*FLEN/8, x9, x1, x2) + +inst_3054: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x003 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc03; op2val:0xfbff; + valaddr_reg:x6; val_offset:6060*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6060*FLEN/8, x9, x1, x2) + +inst_3055: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xbffc; + valaddr_reg:x6; val_offset:6062*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6062*FLEN/8, x9, x1, x2) + +inst_3056: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbffc; op2val:0xfbff; + valaddr_reg:x6; val_offset:6064*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6064*FLEN/8, x9, x1, x2) + +inst_3057: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xbc01; + valaddr_reg:x6; val_offset:6066*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6066*FLEN/8, x9, x1, x2) + +inst_3058: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbc01; op2val:0xfbff; + valaddr_reg:x6; val_offset:6068*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6068*FLEN/8, x9, x1, x2) + +inst_3059: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xbffe; + valaddr_reg:x6; val_offset:6070*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6070*FLEN/8, x9, x1, x2) + +inst_3060: +// fs1 == 1 and fe1 == 0x0f and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xbffe; op2val:0xfbff; + valaddr_reg:x6; val_offset:6072*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6072*FLEN/8, x9, x1, x2) + +inst_3061: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfbfe; + valaddr_reg:x6; val_offset:6074*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6074*FLEN/8, x9, x1, x2) + +inst_3062: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbfe; op2val:0xfbff; + valaddr_reg:x6; val_offset:6076*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6076*FLEN/8, x9, x1, x2) + +inst_3063: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf801; + valaddr_reg:x6; val_offset:6078*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6078*FLEN/8, x9, x1, x2) + +inst_3064: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf801; op2val:0xfbff; + valaddr_reg:x6; val_offset:6080*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6080*FLEN/8, x9, x1, x2) + +inst_3065: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1b6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf9b6; + valaddr_reg:x6; val_offset:6082*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6082*FLEN/8, x9, x1, x2) + +inst_3066: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x1b6 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf9b6; op2val:0xfbff; + valaddr_reg:x6; val_offset:6084*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6084*FLEN/8, x9, x1, x2) + +inst_3067: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x36d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfb6d; + valaddr_reg:x6; val_offset:6086*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6086*FLEN/8, x9, x1, x2) + +inst_3068: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x36d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb6d; op2val:0xfbff; + valaddr_reg:x6; val_offset:6088*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6088*FLEN/8, x9, x1, x2) + +inst_3069: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0cc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf8cc; + valaddr_reg:x6; val_offset:6090*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6090*FLEN/8, x9, x1, x2) + +inst_3070: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x0cc and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf8cc; op2val:0xfbff; + valaddr_reg:x6; val_offset:6092*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6092*FLEN/8, x9, x1, x2) + +inst_3071: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x333 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfb33; + valaddr_reg:x6; val_offset:6094*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6094*FLEN/8, x9, x1, x2) + +inst_3072: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x333 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb33; op2val:0xfbff; + valaddr_reg:x6; val_offset:6096*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6096*FLEN/8, x9, x1, x2) + +inst_3073: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1dd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf9dd; + valaddr_reg:x6; val_offset:6098*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6098*FLEN/8, x9, x1, x2) + +inst_3074: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x1dd and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf9dd; op2val:0xfbff; + valaddr_reg:x6; val_offset:6100*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6100*FLEN/8, x9, x1, x2) + +inst_3075: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x222 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfa22; + valaddr_reg:x6; val_offset:6102*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6102*FLEN/8, x9, x1, x2) + +inst_3076: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x222 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa22; op2val:0xfbff; + valaddr_reg:x6; val_offset:6104*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6104*FLEN/8, x9, x1, x2) + +inst_3077: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x124 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf924; + valaddr_reg:x6; val_offset:6106*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6106*FLEN/8, x9, x1, x2) + +inst_3078: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x124 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf924; op2val:0xfbff; + valaddr_reg:x6; val_offset:6108*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6108*FLEN/8, x9, x1, x2) + +inst_3079: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2db and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfadb; + valaddr_reg:x6; val_offset:6110*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6110*FLEN/8, x9, x1, x2) + +inst_3080: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x2db and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfadb; op2val:0xfbff; + valaddr_reg:x6; val_offset:6112*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6112*FLEN/8, x9, x1, x2) + +inst_3081: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x199 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf999; + valaddr_reg:x6; val_offset:6114*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6114*FLEN/8, x9, x1, x2) + +inst_3082: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x199 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf999; op2val:0xfbff; + valaddr_reg:x6; val_offset:6116*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6116*FLEN/8, x9, x1, x2) + +inst_3083: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x266 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfa66; + valaddr_reg:x6; val_offset:6118*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6118*FLEN/8, x9, x1, x2) + +inst_3084: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x266 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa66; op2val:0xfbff; + valaddr_reg:x6; val_offset:6120*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6120*FLEN/8, x9, x1, x2) + +inst_3085: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x09 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xa7ff; + valaddr_reg:x6; val_offset:6122*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6122*FLEN/8, x9, x1, x2) + +inst_3086: +// fs1 == 1 and fe1 == 0x09 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xa7ff; op2val:0xfbff; + valaddr_reg:x6; val_offset:6124*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6124*FLEN/8, x9, x1, x2) + +inst_3087: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x09 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xa400; + valaddr_reg:x6; val_offset:6126*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6126*FLEN/8, x9, x1, x2) + +inst_3088: +// fs1 == 1 and fe1 == 0x09 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xa400; op2val:0xfbff; + valaddr_reg:x6; val_offset:6128*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6128*FLEN/8, x9, x1, x2) + +inst_3089: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x09 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xa5ff; + valaddr_reg:x6; val_offset:6130*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6130*FLEN/8, x9, x1, x2) + +inst_3090: +// fs1 == 1 and fe1 == 0x09 and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xa5ff; op2val:0xfbff; + valaddr_reg:x6; val_offset:6132*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6132*FLEN/8, x9, x1, x2) + +inst_3091: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x09 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xa600; + valaddr_reg:x6; val_offset:6134*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6134*FLEN/8, x9, x1, x2) + +inst_3092: +// fs1 == 1 and fe1 == 0x09 and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xa600; op2val:0xfbff; + valaddr_reg:x6; val_offset:6136*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6136*FLEN/8, x9, x1, x2) + +inst_3093: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x09 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xa4ff; + valaddr_reg:x6; val_offset:6138*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6138*FLEN/8, x9, x1, x2) + +inst_3094: +// fs1 == 1 and fe1 == 0x09 and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xa4ff; op2val:0xfbff; + valaddr_reg:x6; val_offset:6140*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6140*FLEN/8, x9, x1, x2) + +inst_3095: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x09 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xa700; + valaddr_reg:x6; val_offset:6142*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6142*FLEN/8, x9, x1, x2) + +inst_3096: +// fs1 == 1 and fe1 == 0x09 and fm1 == 0x300 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xa700; op2val:0xfbff; + valaddr_reg:x6; val_offset:6144*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6144*FLEN/8, x9, x1, x2) + +inst_3097: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x09 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xa47f; + valaddr_reg:x6; val_offset:6146*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6146*FLEN/8, x9, x1, x2) + +inst_3098: +// fs1 == 1 and fe1 == 0x09 and fm1 == 0x07f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xa47f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6148*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6148*FLEN/8, x9, x1, x2) + +inst_3099: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x09 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xa780; + valaddr_reg:x6; val_offset:6150*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6150*FLEN/8, x9, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_24) + +inst_3100: +// fs1 == 1 and fe1 == 0x09 and fm1 == 0x380 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xa780; op2val:0xfbff; + valaddr_reg:x6; val_offset:6152*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6152*FLEN/8, x9, x1, x2) + +inst_3101: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x09 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xa43f; + valaddr_reg:x6; val_offset:6154*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6154*FLEN/8, x9, x1, x2) + +inst_3102: +// fs1 == 1 and fe1 == 0x09 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xa43f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6156*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6156*FLEN/8, x9, x1, x2) + +inst_3103: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x09 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xa7c0; + valaddr_reg:x6; val_offset:6158*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6158*FLEN/8, x9, x1, x2) + +inst_3104: +// fs1 == 1 and fe1 == 0x09 and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xa7c0; op2val:0xfbff; + valaddr_reg:x6; val_offset:6160*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6160*FLEN/8, x9, x1, x2) + +inst_3105: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x09 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xa41f; + valaddr_reg:x6; val_offset:6162*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6162*FLEN/8, x9, x1, x2) + +inst_3106: +// fs1 == 1 and fe1 == 0x09 and fm1 == 0x01f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xa41f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6164*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6164*FLEN/8, x9, x1, x2) + +inst_3107: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x09 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xa7e0; + valaddr_reg:x6; val_offset:6166*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6166*FLEN/8, x9, x1, x2) + +inst_3108: +// fs1 == 1 and fe1 == 0x09 and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xa7e0; op2val:0xfbff; + valaddr_reg:x6; val_offset:6168*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6168*FLEN/8, x9, x1, x2) + +inst_3109: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x09 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xa40f; + valaddr_reg:x6; val_offset:6170*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6170*FLEN/8, x9, x1, x2) + +inst_3110: +// fs1 == 1 and fe1 == 0x09 and fm1 == 0x00f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xa40f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6172*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6172*FLEN/8, x9, x1, x2) + +inst_3111: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x09 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xa7f0; + valaddr_reg:x6; val_offset:6174*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6174*FLEN/8, x9, x1, x2) + +inst_3112: +// fs1 == 1 and fe1 == 0x09 and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xa7f0; op2val:0xfbff; + valaddr_reg:x6; val_offset:6176*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6176*FLEN/8, x9, x1, x2) + +inst_3113: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x09 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xa407; + valaddr_reg:x6; val_offset:6178*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6178*FLEN/8, x9, x1, x2) + +inst_3114: +// fs1 == 1 and fe1 == 0x09 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xa407; op2val:0xfbff; + valaddr_reg:x6; val_offset:6180*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6180*FLEN/8, x9, x1, x2) + +inst_3115: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x09 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xa7f8; + valaddr_reg:x6; val_offset:6182*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6182*FLEN/8, x9, x1, x2) + +inst_3116: +// fs1 == 1 and fe1 == 0x09 and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xa7f8; op2val:0xfbff; + valaddr_reg:x6; val_offset:6184*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6184*FLEN/8, x9, x1, x2) + +inst_3117: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x09 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xa403; + valaddr_reg:x6; val_offset:6186*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6186*FLEN/8, x9, x1, x2) + +inst_3118: +// fs1 == 1 and fe1 == 0x09 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xa403; op2val:0xfbff; + valaddr_reg:x6; val_offset:6188*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6188*FLEN/8, x9, x1, x2) + +inst_3119: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x09 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xa7fc; + valaddr_reg:x6; val_offset:6190*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6190*FLEN/8, x9, x1, x2) + +inst_3120: +// fs1 == 1 and fe1 == 0x09 and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xa7fc; op2val:0xfbff; + valaddr_reg:x6; val_offset:6192*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6192*FLEN/8, x9, x1, x2) + +inst_3121: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x09 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xa401; + valaddr_reg:x6; val_offset:6194*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6194*FLEN/8, x9, x1, x2) + +inst_3122: +// fs1 == 1 and fe1 == 0x09 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xa401; op2val:0xfbff; + valaddr_reg:x6; val_offset:6196*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6196*FLEN/8, x9, x1, x2) + +inst_3123: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x09 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xa7fe; + valaddr_reg:x6; val_offset:6198*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6198*FLEN/8, x9, x1, x2) + +inst_3124: +// fs1 == 1 and fe1 == 0x09 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xa7fe; op2val:0xfbff; + valaddr_reg:x6; val_offset:6200*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6200*FLEN/8, x9, x1, x2) + +inst_3125: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1a and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xebff; + valaddr_reg:x6; val_offset:6202*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6202*FLEN/8, x9, x1, x2) + +inst_3126: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xebff; op2val:0xfbff; + valaddr_reg:x6; val_offset:6204*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6204*FLEN/8, x9, x1, x2) + +inst_3127: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1a and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xe800; + valaddr_reg:x6; val_offset:6206*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6206*FLEN/8, x9, x1, x2) + +inst_3128: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xe800; op2val:0xfbff; + valaddr_reg:x6; val_offset:6208*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6208*FLEN/8, x9, x1, x2) + +inst_3129: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1a and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xe9ff; + valaddr_reg:x6; val_offset:6210*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6210*FLEN/8, x9, x1, x2) + +inst_3130: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xe9ff; op2val:0xfbff; + valaddr_reg:x6; val_offset:6212*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6212*FLEN/8, x9, x1, x2) + +inst_3131: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1a and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xea00; + valaddr_reg:x6; val_offset:6214*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6214*FLEN/8, x9, x1, x2) + +inst_3132: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xea00; op2val:0xfbff; + valaddr_reg:x6; val_offset:6216*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6216*FLEN/8, x9, x1, x2) + +inst_3133: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1a and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xe8ff; + valaddr_reg:x6; val_offset:6218*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6218*FLEN/8, x9, x1, x2) + +inst_3134: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xe8ff; op2val:0xfbff; + valaddr_reg:x6; val_offset:6220*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6220*FLEN/8, x9, x1, x2) + +inst_3135: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1a and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xeb00; + valaddr_reg:x6; val_offset:6222*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6222*FLEN/8, x9, x1, x2) + +inst_3136: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x300 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xeb00; op2val:0xfbff; + valaddr_reg:x6; val_offset:6224*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6224*FLEN/8, x9, x1, x2) + +inst_3137: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1a and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xe87f; + valaddr_reg:x6; val_offset:6226*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6226*FLEN/8, x9, x1, x2) + +inst_3138: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x07f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xe87f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6228*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6228*FLEN/8, x9, x1, x2) + +inst_3139: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1a and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xeb80; + valaddr_reg:x6; val_offset:6230*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6230*FLEN/8, x9, x1, x2) + +inst_3140: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x380 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xeb80; op2val:0xfbff; + valaddr_reg:x6; val_offset:6232*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6232*FLEN/8, x9, x1, x2) + +inst_3141: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1a and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xe83f; + valaddr_reg:x6; val_offset:6234*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6234*FLEN/8, x9, x1, x2) + +inst_3142: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x03f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xe83f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6236*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6236*FLEN/8, x9, x1, x2) + +inst_3143: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1a and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xebc0; + valaddr_reg:x6; val_offset:6238*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6238*FLEN/8, x9, x1, x2) + +inst_3144: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xebc0; op2val:0xfbff; + valaddr_reg:x6; val_offset:6240*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6240*FLEN/8, x9, x1, x2) + +inst_3145: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1a and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xe81f; + valaddr_reg:x6; val_offset:6242*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6242*FLEN/8, x9, x1, x2) + +inst_3146: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x01f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xe81f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6244*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6244*FLEN/8, x9, x1, x2) + +inst_3147: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1a and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xebe0; + valaddr_reg:x6; val_offset:6246*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6246*FLEN/8, x9, x1, x2) + +inst_3148: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xebe0; op2val:0xfbff; + valaddr_reg:x6; val_offset:6248*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6248*FLEN/8, x9, x1, x2) + +inst_3149: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1a and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xe80f; + valaddr_reg:x6; val_offset:6250*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6250*FLEN/8, x9, x1, x2) + +inst_3150: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x00f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xe80f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6252*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6252*FLEN/8, x9, x1, x2) + +inst_3151: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1a and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xebf0; + valaddr_reg:x6; val_offset:6254*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6254*FLEN/8, x9, x1, x2) + +inst_3152: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xebf0; op2val:0xfbff; + valaddr_reg:x6; val_offset:6256*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6256*FLEN/8, x9, x1, x2) + +inst_3153: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1a and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xe807; + valaddr_reg:x6; val_offset:6258*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6258*FLEN/8, x9, x1, x2) + +inst_3154: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x007 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xe807; op2val:0xfbff; + valaddr_reg:x6; val_offset:6260*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6260*FLEN/8, x9, x1, x2) + +inst_3155: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1a and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xebf8; + valaddr_reg:x6; val_offset:6262*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6262*FLEN/8, x9, x1, x2) + +inst_3156: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xebf8; op2val:0xfbff; + valaddr_reg:x6; val_offset:6264*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6264*FLEN/8, x9, x1, x2) + +inst_3157: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1a and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xe803; + valaddr_reg:x6; val_offset:6266*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6266*FLEN/8, x9, x1, x2) + +inst_3158: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x003 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xe803; op2val:0xfbff; + valaddr_reg:x6; val_offset:6268*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6268*FLEN/8, x9, x1, x2) + +inst_3159: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1a and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xebfc; + valaddr_reg:x6; val_offset:6270*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6270*FLEN/8, x9, x1, x2) + +inst_3160: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xebfc; op2val:0xfbff; + valaddr_reg:x6; val_offset:6272*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6272*FLEN/8, x9, x1, x2) + +inst_3161: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1a and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xe801; + valaddr_reg:x6; val_offset:6274*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6274*FLEN/8, x9, x1, x2) + +inst_3162: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xe801; op2val:0xfbff; + valaddr_reg:x6; val_offset:6276*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6276*FLEN/8, x9, x1, x2) + +inst_3163: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1a and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xebfe; + valaddr_reg:x6; val_offset:6278*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6278*FLEN/8, x9, x1, x2) + +inst_3164: +// fs1 == 1 and fe1 == 0x1a and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xebfe; op2val:0xfbff; + valaddr_reg:x6; val_offset:6280*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6280*FLEN/8, x9, x1, x2) + +inst_3165: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1b and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xefff; + valaddr_reg:x6; val_offset:6282*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6282*FLEN/8, x9, x1, x2) + +inst_3166: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xefff; op2val:0xfbff; + valaddr_reg:x6; val_offset:6284*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6284*FLEN/8, x9, x1, x2) + +inst_3167: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1b and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xec00; + valaddr_reg:x6; val_offset:6286*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6286*FLEN/8, x9, x1, x2) + +inst_3168: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xec00; op2val:0xfbff; + valaddr_reg:x6; val_offset:6288*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6288*FLEN/8, x9, x1, x2) + +inst_3169: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1b and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xedff; + valaddr_reg:x6; val_offset:6290*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6290*FLEN/8, x9, x1, x2) + +inst_3170: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xedff; op2val:0xfbff; + valaddr_reg:x6; val_offset:6292*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6292*FLEN/8, x9, x1, x2) + +inst_3171: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1b and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xee00; + valaddr_reg:x6; val_offset:6294*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6294*FLEN/8, x9, x1, x2) + +inst_3172: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xee00; op2val:0xfbff; + valaddr_reg:x6; val_offset:6296*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6296*FLEN/8, x9, x1, x2) + +inst_3173: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1b and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xecff; + valaddr_reg:x6; val_offset:6298*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6298*FLEN/8, x9, x1, x2) + +inst_3174: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xecff; op2val:0xfbff; + valaddr_reg:x6; val_offset:6300*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6300*FLEN/8, x9, x1, x2) + +inst_3175: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1b and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xef00; + valaddr_reg:x6; val_offset:6302*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6302*FLEN/8, x9, x1, x2) + +inst_3176: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x300 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xef00; op2val:0xfbff; + valaddr_reg:x6; val_offset:6304*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6304*FLEN/8, x9, x1, x2) + +inst_3177: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1b and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xec7f; + valaddr_reg:x6; val_offset:6306*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6306*FLEN/8, x9, x1, x2) + +inst_3178: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x07f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xec7f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6308*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6308*FLEN/8, x9, x1, x2) + +inst_3179: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1b and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xef80; + valaddr_reg:x6; val_offset:6310*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6310*FLEN/8, x9, x1, x2) + +inst_3180: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x380 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xef80; op2val:0xfbff; + valaddr_reg:x6; val_offset:6312*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6312*FLEN/8, x9, x1, x2) + +inst_3181: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1b and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xec3f; + valaddr_reg:x6; val_offset:6314*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6314*FLEN/8, x9, x1, x2) + +inst_3182: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x03f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xec3f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6316*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6316*FLEN/8, x9, x1, x2) + +inst_3183: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1b and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xefc0; + valaddr_reg:x6; val_offset:6318*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6318*FLEN/8, x9, x1, x2) + +inst_3184: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xefc0; op2val:0xfbff; + valaddr_reg:x6; val_offset:6320*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6320*FLEN/8, x9, x1, x2) + +inst_3185: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1b and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xec1f; + valaddr_reg:x6; val_offset:6322*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6322*FLEN/8, x9, x1, x2) + +inst_3186: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x01f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xec1f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6324*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6324*FLEN/8, x9, x1, x2) + +inst_3187: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1b and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xefe0; + valaddr_reg:x6; val_offset:6326*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6326*FLEN/8, x9, x1, x2) + +inst_3188: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xefe0; op2val:0xfbff; + valaddr_reg:x6; val_offset:6328*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6328*FLEN/8, x9, x1, x2) + +inst_3189: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1b and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xec0f; + valaddr_reg:x6; val_offset:6330*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6330*FLEN/8, x9, x1, x2) + +inst_3190: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x00f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xec0f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6332*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6332*FLEN/8, x9, x1, x2) + +inst_3191: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1b and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xeff0; + valaddr_reg:x6; val_offset:6334*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6334*FLEN/8, x9, x1, x2) + +inst_3192: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xeff0; op2val:0xfbff; + valaddr_reg:x6; val_offset:6336*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6336*FLEN/8, x9, x1, x2) + +inst_3193: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1b and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xec07; + valaddr_reg:x6; val_offset:6338*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6338*FLEN/8, x9, x1, x2) + +inst_3194: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x007 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xec07; op2val:0xfbff; + valaddr_reg:x6; val_offset:6340*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6340*FLEN/8, x9, x1, x2) + +inst_3195: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1b and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xeff8; + valaddr_reg:x6; val_offset:6342*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6342*FLEN/8, x9, x1, x2) + +inst_3196: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xeff8; op2val:0xfbff; + valaddr_reg:x6; val_offset:6344*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6344*FLEN/8, x9, x1, x2) + +inst_3197: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1b and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xec03; + valaddr_reg:x6; val_offset:6346*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6346*FLEN/8, x9, x1, x2) + +inst_3198: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x003 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xec03; op2val:0xfbff; + valaddr_reg:x6; val_offset:6348*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6348*FLEN/8, x9, x1, x2) + +inst_3199: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1b and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xeffc; + valaddr_reg:x6; val_offset:6350*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6350*FLEN/8, x9, x1, x2) + +inst_3200: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xeffc; op2val:0xfbff; + valaddr_reg:x6; val_offset:6352*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6352*FLEN/8, x9, x1, x2) + +inst_3201: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1b and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xec01; + valaddr_reg:x6; val_offset:6354*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6354*FLEN/8, x9, x1, x2) + +inst_3202: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xec01; op2val:0xfbff; + valaddr_reg:x6; val_offset:6356*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6356*FLEN/8, x9, x1, x2) + +inst_3203: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1b and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xeffe; + valaddr_reg:x6; val_offset:6358*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6358*FLEN/8, x9, x1, x2) + +inst_3204: +// fs1 == 1 and fe1 == 0x1b and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xeffe; op2val:0xfbff; + valaddr_reg:x6; val_offset:6360*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6360*FLEN/8, x9, x1, x2) + +inst_3205: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf3ff; + valaddr_reg:x6; val_offset:6362*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6362*FLEN/8, x9, x1, x2) + +inst_3206: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3ff; op2val:0xfbff; + valaddr_reg:x6; val_offset:6364*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6364*FLEN/8, x9, x1, x2) + +inst_3207: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1c and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf000; + valaddr_reg:x6; val_offset:6366*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6366*FLEN/8, x9, x1, x2) + +inst_3208: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf000; op2val:0xfbff; + valaddr_reg:x6; val_offset:6368*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6368*FLEN/8, x9, x1, x2) + +inst_3209: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1c and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf1ff; + valaddr_reg:x6; val_offset:6370*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6370*FLEN/8, x9, x1, x2) + +inst_3210: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf1ff; op2val:0xfbff; + valaddr_reg:x6; val_offset:6372*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6372*FLEN/8, x9, x1, x2) + +inst_3211: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1c and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf200; + valaddr_reg:x6; val_offset:6374*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6374*FLEN/8, x9, x1, x2) + +inst_3212: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf200; op2val:0xfbff; + valaddr_reg:x6; val_offset:6376*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6376*FLEN/8, x9, x1, x2) + +inst_3213: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf0ff; + valaddr_reg:x6; val_offset:6378*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6378*FLEN/8, x9, x1, x2) + +inst_3214: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf0ff; op2val:0xfbff; + valaddr_reg:x6; val_offset:6380*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6380*FLEN/8, x9, x1, x2) + +inst_3215: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1c and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf300; + valaddr_reg:x6; val_offset:6382*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6382*FLEN/8, x9, x1, x2) + +inst_3216: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x300 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf300; op2val:0xfbff; + valaddr_reg:x6; val_offset:6384*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6384*FLEN/8, x9, x1, x2) + +inst_3217: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1c and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf07f; + valaddr_reg:x6; val_offset:6386*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6386*FLEN/8, x9, x1, x2) + +inst_3218: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x07f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf07f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6388*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6388*FLEN/8, x9, x1, x2) + +inst_3219: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1c and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf380; + valaddr_reg:x6; val_offset:6390*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6390*FLEN/8, x9, x1, x2) + +inst_3220: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x380 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf380; op2val:0xfbff; + valaddr_reg:x6; val_offset:6392*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6392*FLEN/8, x9, x1, x2) + +inst_3221: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1c and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf03f; + valaddr_reg:x6; val_offset:6394*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6394*FLEN/8, x9, x1, x2) + +inst_3222: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x03f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf03f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6396*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6396*FLEN/8, x9, x1, x2) + +inst_3223: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf3c0; + valaddr_reg:x6; val_offset:6398*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6398*FLEN/8, x9, x1, x2) + +inst_3224: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3c0; op2val:0xfbff; + valaddr_reg:x6; val_offset:6400*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6400*FLEN/8, x9, x1, x2) + +inst_3225: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1c and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf01f; + valaddr_reg:x6; val_offset:6402*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6402*FLEN/8, x9, x1, x2) + +inst_3226: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x01f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf01f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6404*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6404*FLEN/8, x9, x1, x2) + +inst_3227: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf3e0; + valaddr_reg:x6; val_offset:6406*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6406*FLEN/8, x9, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_25) + +inst_3228: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3e0; op2val:0xfbff; + valaddr_reg:x6; val_offset:6408*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6408*FLEN/8, x9, x1, x2) + +inst_3229: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1c and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf00f; + valaddr_reg:x6; val_offset:6410*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6410*FLEN/8, x9, x1, x2) + +inst_3230: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x00f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf00f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6412*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6412*FLEN/8, x9, x1, x2) + +inst_3231: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf3f0; + valaddr_reg:x6; val_offset:6414*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6414*FLEN/8, x9, x1, x2) + +inst_3232: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3f0; op2val:0xfbff; + valaddr_reg:x6; val_offset:6416*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6416*FLEN/8, x9, x1, x2) + +inst_3233: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1c and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf007; + valaddr_reg:x6; val_offset:6418*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6418*FLEN/8, x9, x1, x2) + +inst_3234: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x007 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf007; op2val:0xfbff; + valaddr_reg:x6; val_offset:6420*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6420*FLEN/8, x9, x1, x2) + +inst_3235: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf3f8; + valaddr_reg:x6; val_offset:6422*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6422*FLEN/8, x9, x1, x2) + +inst_3236: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3f8; op2val:0xfbff; + valaddr_reg:x6; val_offset:6424*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6424*FLEN/8, x9, x1, x2) + +inst_3237: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1c and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf003; + valaddr_reg:x6; val_offset:6426*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6426*FLEN/8, x9, x1, x2) + +inst_3238: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x003 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf003; op2val:0xfbff; + valaddr_reg:x6; val_offset:6428*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6428*FLEN/8, x9, x1, x2) + +inst_3239: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf3fc; + valaddr_reg:x6; val_offset:6430*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6430*FLEN/8, x9, x1, x2) + +inst_3240: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3fc; op2val:0xfbff; + valaddr_reg:x6; val_offset:6432*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6432*FLEN/8, x9, x1, x2) + +inst_3241: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1c and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf001; + valaddr_reg:x6; val_offset:6434*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6434*FLEN/8, x9, x1, x2) + +inst_3242: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf001; op2val:0xfbff; + valaddr_reg:x6; val_offset:6436*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6436*FLEN/8, x9, x1, x2) + +inst_3243: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf3fe; + valaddr_reg:x6; val_offset:6438*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6438*FLEN/8, x9, x1, x2) + +inst_3244: +// fs1 == 1 and fe1 == 0x1c and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf3fe; op2val:0xfbff; + valaddr_reg:x6; val_offset:6440*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6440*FLEN/8, x9, x1, x2) + +inst_3245: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf7ff; + valaddr_reg:x6; val_offset:6442*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6442*FLEN/8, x9, x1, x2) + +inst_3246: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf7ff; op2val:0xfbff; + valaddr_reg:x6; val_offset:6444*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6444*FLEN/8, x9, x1, x2) + +inst_3247: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1d and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf400; + valaddr_reg:x6; val_offset:6446*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6446*FLEN/8, x9, x1, x2) + +inst_3248: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf400; op2val:0xfbff; + valaddr_reg:x6; val_offset:6448*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6448*FLEN/8, x9, x1, x2) + +inst_3249: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1d and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf5ff; + valaddr_reg:x6; val_offset:6450*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6450*FLEN/8, x9, x1, x2) + +inst_3250: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf5ff; op2val:0xfbff; + valaddr_reg:x6; val_offset:6452*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6452*FLEN/8, x9, x1, x2) + +inst_3251: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1d and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf600; + valaddr_reg:x6; val_offset:6454*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6454*FLEN/8, x9, x1, x2) + +inst_3252: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf600; op2val:0xfbff; + valaddr_reg:x6; val_offset:6456*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6456*FLEN/8, x9, x1, x2) + +inst_3253: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1d and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf4ff; + valaddr_reg:x6; val_offset:6458*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6458*FLEN/8, x9, x1, x2) + +inst_3254: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf4ff; op2val:0xfbff; + valaddr_reg:x6; val_offset:6460*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6460*FLEN/8, x9, x1, x2) + +inst_3255: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1d and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf700; + valaddr_reg:x6; val_offset:6462*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6462*FLEN/8, x9, x1, x2) + +inst_3256: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x300 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf700; op2val:0xfbff; + valaddr_reg:x6; val_offset:6464*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6464*FLEN/8, x9, x1, x2) + +inst_3257: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1d and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf47f; + valaddr_reg:x6; val_offset:6466*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6466*FLEN/8, x9, x1, x2) + +inst_3258: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x07f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf47f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6468*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6468*FLEN/8, x9, x1, x2) + +inst_3259: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1d and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf780; + valaddr_reg:x6; val_offset:6470*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6470*FLEN/8, x9, x1, x2) + +inst_3260: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x380 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf780; op2val:0xfbff; + valaddr_reg:x6; val_offset:6472*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6472*FLEN/8, x9, x1, x2) + +inst_3261: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1d and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf43f; + valaddr_reg:x6; val_offset:6474*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6474*FLEN/8, x9, x1, x2) + +inst_3262: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x03f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf43f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6476*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6476*FLEN/8, x9, x1, x2) + +inst_3263: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf7c0; + valaddr_reg:x6; val_offset:6478*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6478*FLEN/8, x9, x1, x2) + +inst_3264: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf7c0; op2val:0xfbff; + valaddr_reg:x6; val_offset:6480*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6480*FLEN/8, x9, x1, x2) + +inst_3265: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1d and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf41f; + valaddr_reg:x6; val_offset:6482*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6482*FLEN/8, x9, x1, x2) + +inst_3266: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x01f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf41f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6484*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6484*FLEN/8, x9, x1, x2) + +inst_3267: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf7e0; + valaddr_reg:x6; val_offset:6486*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6486*FLEN/8, x9, x1, x2) + +inst_3268: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf7e0; op2val:0xfbff; + valaddr_reg:x6; val_offset:6488*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6488*FLEN/8, x9, x1, x2) + +inst_3269: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1d and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf40f; + valaddr_reg:x6; val_offset:6490*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6490*FLEN/8, x9, x1, x2) + +inst_3270: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x00f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf40f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6492*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6492*FLEN/8, x9, x1, x2) + +inst_3271: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf7f0; + valaddr_reg:x6; val_offset:6494*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6494*FLEN/8, x9, x1, x2) + +inst_3272: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf7f0; op2val:0xfbff; + valaddr_reg:x6; val_offset:6496*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6496*FLEN/8, x9, x1, x2) + +inst_3273: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1d and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf407; + valaddr_reg:x6; val_offset:6498*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6498*FLEN/8, x9, x1, x2) + +inst_3274: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x007 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf407; op2val:0xfbff; + valaddr_reg:x6; val_offset:6500*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6500*FLEN/8, x9, x1, x2) + +inst_3275: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf7f8; + valaddr_reg:x6; val_offset:6502*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6502*FLEN/8, x9, x1, x2) + +inst_3276: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf7f8; op2val:0xfbff; + valaddr_reg:x6; val_offset:6504*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6504*FLEN/8, x9, x1, x2) + +inst_3277: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1d and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf403; + valaddr_reg:x6; val_offset:6506*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6506*FLEN/8, x9, x1, x2) + +inst_3278: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x003 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf403; op2val:0xfbff; + valaddr_reg:x6; val_offset:6508*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6508*FLEN/8, x9, x1, x2) + +inst_3279: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf7fc; + valaddr_reg:x6; val_offset:6510*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6510*FLEN/8, x9, x1, x2) + +inst_3280: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf7fc; op2val:0xfbff; + valaddr_reg:x6; val_offset:6512*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6512*FLEN/8, x9, x1, x2) + +inst_3281: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1d and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf401; + valaddr_reg:x6; val_offset:6514*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6514*FLEN/8, x9, x1, x2) + +inst_3282: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf401; op2val:0xfbff; + valaddr_reg:x6; val_offset:6516*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6516*FLEN/8, x9, x1, x2) + +inst_3283: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf7fe; + valaddr_reg:x6; val_offset:6518*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6518*FLEN/8, x9, x1, x2) + +inst_3284: +// fs1 == 1 and fe1 == 0x1d and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf7fe; op2val:0xfbff; + valaddr_reg:x6; val_offset:6520*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6520*FLEN/8, x9, x1, x2) + +inst_3285: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfbff; + valaddr_reg:x6; val_offset:6522*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6522*FLEN/8, x9, x1, x2) + +inst_3286: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf800; + valaddr_reg:x6; val_offset:6524*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6524*FLEN/8, x9, x1, x2) + +inst_3287: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf800; op2val:0xfbff; + valaddr_reg:x6; val_offset:6526*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6526*FLEN/8, x9, x1, x2) + +inst_3288: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf9ff; + valaddr_reg:x6; val_offset:6528*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6528*FLEN/8, x9, x1, x2) + +inst_3289: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf9ff; op2val:0xfbff; + valaddr_reg:x6; val_offset:6530*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6530*FLEN/8, x9, x1, x2) + +inst_3290: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfa00; + valaddr_reg:x6; val_offset:6532*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6532*FLEN/8, x9, x1, x2) + +inst_3291: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfa00; op2val:0xfbff; + valaddr_reg:x6; val_offset:6534*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6534*FLEN/8, x9, x1, x2) + +inst_3292: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf8ff; + valaddr_reg:x6; val_offset:6536*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6536*FLEN/8, x9, x1, x2) + +inst_3293: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf8ff; op2val:0xfbff; + valaddr_reg:x6; val_offset:6538*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6538*FLEN/8, x9, x1, x2) + +inst_3294: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfb00; + valaddr_reg:x6; val_offset:6540*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6540*FLEN/8, x9, x1, x2) + +inst_3295: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x300 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb00; op2val:0xfbff; + valaddr_reg:x6; val_offset:6542*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6542*FLEN/8, x9, x1, x2) + +inst_3296: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf87f; + valaddr_reg:x6; val_offset:6544*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6544*FLEN/8, x9, x1, x2) + +inst_3297: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x07f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf87f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6546*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6546*FLEN/8, x9, x1, x2) + +inst_3298: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfb80; + valaddr_reg:x6; val_offset:6548*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6548*FLEN/8, x9, x1, x2) + +inst_3299: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x380 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfb80; op2val:0xfbff; + valaddr_reg:x6; val_offset:6550*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6550*FLEN/8, x9, x1, x2) + +inst_3300: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf83f; + valaddr_reg:x6; val_offset:6552*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6552*FLEN/8, x9, x1, x2) + +inst_3301: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x03f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf83f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6554*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6554*FLEN/8, x9, x1, x2) + +inst_3302: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfbc0; + valaddr_reg:x6; val_offset:6556*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6556*FLEN/8, x9, x1, x2) + +inst_3303: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbc0; op2val:0xfbff; + valaddr_reg:x6; val_offset:6558*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6558*FLEN/8, x9, x1, x2) + +inst_3304: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf81f; + valaddr_reg:x6; val_offset:6560*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6560*FLEN/8, x9, x1, x2) + +inst_3305: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x01f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf81f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6562*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6562*FLEN/8, x9, x1, x2) + +inst_3306: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfbe0; + valaddr_reg:x6; val_offset:6564*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6564*FLEN/8, x9, x1, x2) + +inst_3307: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbe0; op2val:0xfbff; + valaddr_reg:x6; val_offset:6566*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6566*FLEN/8, x9, x1, x2) + +inst_3308: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf80f; + valaddr_reg:x6; val_offset:6568*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6568*FLEN/8, x9, x1, x2) + +inst_3309: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x00f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf80f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6570*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6570*FLEN/8, x9, x1, x2) + +inst_3310: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfbf0; + valaddr_reg:x6; val_offset:6572*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6572*FLEN/8, x9, x1, x2) + +inst_3311: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbf0; op2val:0xfbff; + valaddr_reg:x6; val_offset:6574*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6574*FLEN/8, x9, x1, x2) + +inst_3312: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf807; + valaddr_reg:x6; val_offset:6576*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6576*FLEN/8, x9, x1, x2) + +inst_3313: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x007 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf807; op2val:0xfbff; + valaddr_reg:x6; val_offset:6578*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6578*FLEN/8, x9, x1, x2) + +inst_3314: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfbf8; + valaddr_reg:x6; val_offset:6580*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6580*FLEN/8, x9, x1, x2) + +inst_3315: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbf8; op2val:0xfbff; + valaddr_reg:x6; val_offset:6582*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6582*FLEN/8, x9, x1, x2) + +inst_3316: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xf803; + valaddr_reg:x6; val_offset:6584*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6584*FLEN/8, x9, x1, x2) + +inst_3317: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x003 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xf803; op2val:0xfbff; + valaddr_reg:x6; val_offset:6586*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6586*FLEN/8, x9, x1, x2) + +inst_3318: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0xfbfc; + valaddr_reg:x6; val_offset:6588*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6588*FLEN/8, x9, x1, x2) + +inst_3319: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbfc; op2val:0xfbff; + valaddr_reg:x6; val_offset:6590*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6590*FLEN/8, x9, x1, x2) + +inst_3320: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x83ff; + valaddr_reg:x6; val_offset:6592*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6592*FLEN/8, x9, x1, x2) + +inst_3321: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83ff; op2val:0xfbff; + valaddr_reg:x6; val_offset:6594*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6594*FLEN/8, x9, x1, x2) + +inst_3322: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8001; + valaddr_reg:x6; val_offset:6596*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6596*FLEN/8, x9, x1, x2) + +inst_3323: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8001; op2val:0xfbff; + valaddr_reg:x6; val_offset:6598*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6598*FLEN/8, x9, x1, x2) + +inst_3324: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x81ff; + valaddr_reg:x6; val_offset:6600*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6600*FLEN/8, x9, x1, x2) + +inst_3325: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x81ff; op2val:0xfbff; + valaddr_reg:x6; val_offset:6602*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6602*FLEN/8, x9, x1, x2) + +inst_3326: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8200; + valaddr_reg:x6; val_offset:6604*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6604*FLEN/8, x9, x1, x2) + +inst_3327: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8200; op2val:0xfbff; + valaddr_reg:x6; val_offset:6606*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6606*FLEN/8, x9, x1, x2) + +inst_3328: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x80ff; + valaddr_reg:x6; val_offset:6608*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6608*FLEN/8, x9, x1, x2) + +inst_3329: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x80ff; op2val:0xfbff; + valaddr_reg:x6; val_offset:6610*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6610*FLEN/8, x9, x1, x2) + +inst_3330: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8300; + valaddr_reg:x6; val_offset:6612*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6612*FLEN/8, x9, x1, x2) + +inst_3331: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x300 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8300; op2val:0xfbff; + valaddr_reg:x6; val_offset:6614*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6614*FLEN/8, x9, x1, x2) + +inst_3332: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x807f; + valaddr_reg:x6; val_offset:6616*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6616*FLEN/8, x9, x1, x2) + +inst_3333: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x07f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x807f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6618*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6618*FLEN/8, x9, x1, x2) + +inst_3334: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8380; + valaddr_reg:x6; val_offset:6620*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6620*FLEN/8, x9, x1, x2) + +inst_3335: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x380 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8380; op2val:0xfbff; + valaddr_reg:x6; val_offset:6622*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6622*FLEN/8, x9, x1, x2) + +inst_3336: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x803f; + valaddr_reg:x6; val_offset:6624*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6624*FLEN/8, x9, x1, x2) + +inst_3337: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x803f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6626*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6626*FLEN/8, x9, x1, x2) + +inst_3338: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x83c0; + valaddr_reg:x6; val_offset:6628*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6628*FLEN/8, x9, x1, x2) + +inst_3339: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83c0; op2val:0xfbff; + valaddr_reg:x6; val_offset:6630*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6630*FLEN/8, x9, x1, x2) + +inst_3340: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x801f; + valaddr_reg:x6; val_offset:6632*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6632*FLEN/8, x9, x1, x2) + +inst_3341: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x01f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x801f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6634*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6634*FLEN/8, x9, x1, x2) + +inst_3342: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x83e0; + valaddr_reg:x6; val_offset:6636*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6636*FLEN/8, x9, x1, x2) + +inst_3343: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83e0; op2val:0xfbff; + valaddr_reg:x6; val_offset:6638*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6638*FLEN/8, x9, x1, x2) + +inst_3344: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x800f; + valaddr_reg:x6; val_offset:6640*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6640*FLEN/8, x9, x1, x2) + +inst_3345: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x00f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x800f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6642*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6642*FLEN/8, x9, x1, x2) + +inst_3346: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x83f0; + valaddr_reg:x6; val_offset:6644*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6644*FLEN/8, x9, x1, x2) + +inst_3347: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83f0; op2val:0xfbff; + valaddr_reg:x6; val_offset:6646*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6646*FLEN/8, x9, x1, x2) + +inst_3348: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8007; + valaddr_reg:x6; val_offset:6648*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6648*FLEN/8, x9, x1, x2) + +inst_3349: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8007; op2val:0xfbff; + valaddr_reg:x6; val_offset:6650*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6650*FLEN/8, x9, x1, x2) + +inst_3350: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x83f8; + valaddr_reg:x6; val_offset:6652*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6652*FLEN/8, x9, x1, x2) + +inst_3351: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83f8; op2val:0xfbff; + valaddr_reg:x6; val_offset:6654*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6654*FLEN/8, x9, x1, x2) + +inst_3352: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8003; + valaddr_reg:x6; val_offset:6656*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6656*FLEN/8, x9, x1, x2) + +inst_3353: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8003; op2val:0xfbff; + valaddr_reg:x6; val_offset:6658*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6658*FLEN/8, x9, x1, x2) + +inst_3354: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x83fc; + valaddr_reg:x6; val_offset:6660*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6660*FLEN/8, x9, x1, x2) + +inst_3355: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fc; op2val:0xfbff; + valaddr_reg:x6; val_offset:6662*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6662*FLEN/8, x9, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_26) + +inst_3356: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x83fe; + valaddr_reg:x6; val_offset:6664*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6664*FLEN/8, x9, x1, x2) + +inst_3357: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x83fe; op2val:0xfbff; + valaddr_reg:x6; val_offset:6666*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6666*FLEN/8, x9, x1, x2) + +inst_3358: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x87ff; + valaddr_reg:x6; val_offset:6668*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6668*FLEN/8, x9, x1, x2) + +inst_3359: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x87ff; op2val:0xfbff; + valaddr_reg:x6; val_offset:6670*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6670*FLEN/8, x9, x1, x2) + +inst_3360: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8400; + valaddr_reg:x6; val_offset:6672*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6672*FLEN/8, x9, x1, x2) + +inst_3361: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8400; op2val:0xfbff; + valaddr_reg:x6; val_offset:6674*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6674*FLEN/8, x9, x1, x2) + +inst_3362: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x1ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x85ff; + valaddr_reg:x6; val_offset:6676*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6676*FLEN/8, x9, x1, x2) + +inst_3363: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x85ff; op2val:0xfbff; + valaddr_reg:x6; val_offset:6678*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6678*FLEN/8, x9, x1, x2) + +inst_3364: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8600; + valaddr_reg:x6; val_offset:6680*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6680*FLEN/8, x9, x1, x2) + +inst_3365: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x200 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8600; op2val:0xfbff; + valaddr_reg:x6; val_offset:6682*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6682*FLEN/8, x9, x1, x2) + +inst_3366: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x84ff; + valaddr_reg:x6; val_offset:6684*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6684*FLEN/8, x9, x1, x2) + +inst_3367: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x84ff; op2val:0xfbff; + valaddr_reg:x6; val_offset:6686*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6686*FLEN/8, x9, x1, x2) + +inst_3368: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8700; + valaddr_reg:x6; val_offset:6688*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6688*FLEN/8, x9, x1, x2) + +inst_3369: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x300 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8700; op2val:0xfbff; + valaddr_reg:x6; val_offset:6690*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6690*FLEN/8, x9, x1, x2) + +inst_3370: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x847f; + valaddr_reg:x6; val_offset:6692*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6692*FLEN/8, x9, x1, x2) + +inst_3371: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x07f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x847f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6694*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6694*FLEN/8, x9, x1, x2) + +inst_3372: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x380 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8780; + valaddr_reg:x6; val_offset:6696*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6696*FLEN/8, x9, x1, x2) + +inst_3373: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x380 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8780; op2val:0xfbff; + valaddr_reg:x6; val_offset:6698*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6698*FLEN/8, x9, x1, x2) + +inst_3374: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x03f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x843f; + valaddr_reg:x6; val_offset:6700*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6700*FLEN/8, x9, x1, x2) + +inst_3375: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x843f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6702*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6702*FLEN/8, x9, x1, x2) + +inst_3376: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x87c0; + valaddr_reg:x6; val_offset:6704*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6704*FLEN/8, x9, x1, x2) + +inst_3377: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3c0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x87c0; op2val:0xfbff; + valaddr_reg:x6; val_offset:6706*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6706*FLEN/8, x9, x1, x2) + +inst_3378: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x841f; + valaddr_reg:x6; val_offset:6708*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6708*FLEN/8, x9, x1, x2) + +inst_3379: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x01f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x841f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6710*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6710*FLEN/8, x9, x1, x2) + +inst_3380: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x87e0; + valaddr_reg:x6; val_offset:6712*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6712*FLEN/8, x9, x1, x2) + +inst_3381: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3e0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x87e0; op2val:0xfbff; + valaddr_reg:x6; val_offset:6714*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6714*FLEN/8, x9, x1, x2) + +inst_3382: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x840f; + valaddr_reg:x6; val_offset:6716*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6716*FLEN/8, x9, x1, x2) + +inst_3383: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x00f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x840f; op2val:0xfbff; + valaddr_reg:x6; val_offset:6718*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6718*FLEN/8, x9, x1, x2) + +inst_3384: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x87f0; + valaddr_reg:x6; val_offset:6720*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6720*FLEN/8, x9, x1, x2) + +inst_3385: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x87f0; op2val:0xfbff; + valaddr_reg:x6; val_offset:6722*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6722*FLEN/8, x9, x1, x2) + +inst_3386: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8407; + valaddr_reg:x6; val_offset:6724*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6724*FLEN/8, x9, x1, x2) + +inst_3387: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8407; op2val:0xfbff; + valaddr_reg:x6; val_offset:6726*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6726*FLEN/8, x9, x1, x2) + +inst_3388: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x87f8; + valaddr_reg:x6; val_offset:6728*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6728*FLEN/8, x9, x1, x2) + +inst_3389: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3f8 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x87f8; op2val:0xfbff; + valaddr_reg:x6; val_offset:6730*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6730*FLEN/8, x9, x1, x2) + +inst_3390: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8403; + valaddr_reg:x6; val_offset:6732*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6732*FLEN/8, x9, x1, x2) + +inst_3391: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8403; op2val:0xfbff; + valaddr_reg:x6; val_offset:6734*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6734*FLEN/8, x9, x1, x2) + +inst_3392: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x87fc; + valaddr_reg:x6; val_offset:6736*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6736*FLEN/8, x9, x1, x2) + +inst_3393: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x87fc; op2val:0xfbff; + valaddr_reg:x6; val_offset:6738*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6738*FLEN/8, x9, x1, x2) + +inst_3394: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x8401; + valaddr_reg:x6; val_offset:6740*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6740*FLEN/8, x9, x1, x2) + +inst_3395: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x8401; op2val:0xfbff; + valaddr_reg:x6; val_offset:6742*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6742*FLEN/8, x9, x1, x2) + +inst_3396: +// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xfbff; op2val:0x87fe; + valaddr_reg:x6; val_offset:6744*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6744*FLEN/8, x9, x1, x2) + +inst_3397: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x87fe; op2val:0xfbff; + valaddr_reg:x6; val_offset:6746*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6746*FLEN/8, x9, x1, x2) + +inst_3398: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x1; + valaddr_reg:x6; val_offset:6748*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6748*FLEN/8, x9, x1, x2) + +inst_3399: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x0; + valaddr_reg:x6; val_offset:6750*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6750*FLEN/8, x9, x1, x2) + +inst_3400: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x200; + valaddr_reg:x6; val_offset:6752*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6752*FLEN/8, x9, x1, x2) + +inst_3401: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0xff; + valaddr_reg:x6; val_offset:6754*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6754*FLEN/8, x9, x1, x2) + +inst_3402: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x0; op2val:0x3e0; + valaddr_reg:x6; val_offset:6756*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x6, 6756*FLEN/8, x9, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(1023,32,FLEN) +NAN_BOXED(1023,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(512,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(511,32,FLEN) +NAN_BOXED(511,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(768,32,FLEN) +NAN_BOXED(768,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(255,32,FLEN) +NAN_BOXED(0,32,FLEN) +test_dataset_1: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(896,32,FLEN) +NAN_BOXED(896,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(127,32,FLEN) +NAN_BOXED(127,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(960,32,FLEN) +NAN_BOXED(960,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(63,32,FLEN) +NAN_BOXED(63,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(992,32,FLEN) +NAN_BOXED(992,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31,32,FLEN) +NAN_BOXED(31,32,FLEN) +NAN_BOXED(0,32,FLEN) +test_dataset_2: +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1008,16,FLEN) +NAN_BOXED(1008,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(15,16,FLEN) +NAN_BOXED(15,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1016,16,FLEN) +NAN_BOXED(1016,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(7,16,FLEN) +NAN_BOXED(7,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1020,16,FLEN) +NAN_BOXED(1020,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(3,16,FLEN) +NAN_BOXED(3,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1022,16,FLEN) +NAN_BOXED(1022,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(438,16,FLEN) +NAN_BOXED(438,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(877,16,FLEN) +NAN_BOXED(877,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(204,16,FLEN) +NAN_BOXED(204,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(819,16,FLEN) +NAN_BOXED(819,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(477,16,FLEN) +NAN_BOXED(477,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(546,16,FLEN) +NAN_BOXED(546,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(292,16,FLEN) +NAN_BOXED(292,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(731,16,FLEN) +NAN_BOXED(731,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(409,16,FLEN) +NAN_BOXED(409,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(614,16,FLEN) +NAN_BOXED(614,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(38912,16,FLEN) +NAN_BOXED(38912,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(39935,16,FLEN) +NAN_BOXED(39935,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(39424,16,FLEN) +NAN_BOXED(39424,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(39423,16,FLEN) +NAN_BOXED(39423,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(39680,16,FLEN) +NAN_BOXED(39680,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(39167,16,FLEN) +NAN_BOXED(39167,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(39808,16,FLEN) +NAN_BOXED(39808,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(39039,16,FLEN) +NAN_BOXED(39039,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(39872,16,FLEN) +NAN_BOXED(39872,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(38975,16,FLEN) +NAN_BOXED(38975,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(39904,16,FLEN) +NAN_BOXED(39904,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(38943,16,FLEN) +NAN_BOXED(38943,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(39920,16,FLEN) +NAN_BOXED(39920,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(38927,16,FLEN) +NAN_BOXED(38927,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(39928,16,FLEN) +NAN_BOXED(39928,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(38919,16,FLEN) +NAN_BOXED(38919,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(39932,16,FLEN) +NAN_BOXED(39932,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(38915,16,FLEN) +NAN_BOXED(38915,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(39934,16,FLEN) +NAN_BOXED(39934,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(38913,16,FLEN) +NAN_BOXED(38913,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(2047,16,FLEN) +NAN_BOXED(2047,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1536,16,FLEN) +NAN_BOXED(1536,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1535,16,FLEN) +NAN_BOXED(1535,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1792,16,FLEN) +NAN_BOXED(1792,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1279,16,FLEN) +NAN_BOXED(1279,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1920,16,FLEN) +NAN_BOXED(1920,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1151,16,FLEN) +NAN_BOXED(1151,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1984,16,FLEN) +NAN_BOXED(1984,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1087,16,FLEN) +NAN_BOXED(1087,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(2016,16,FLEN) +NAN_BOXED(2016,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1055,16,FLEN) +NAN_BOXED(1055,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(2032,16,FLEN) +NAN_BOXED(2032,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1039,16,FLEN) +NAN_BOXED(1039,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(2040,16,FLEN) +NAN_BOXED(2040,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1031,16,FLEN) +NAN_BOXED(1031,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(2044,16,FLEN) +NAN_BOXED(2044,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1027,16,FLEN) +NAN_BOXED(1027,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(2046,16,FLEN) +NAN_BOXED(2046,16,FLEN) +NAN_BOXED(0,16,FLEN) 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+NAN_BOXED(34784,16,FLEN) +NAN_BOXED(34784,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(33807,16,FLEN) +NAN_BOXED(33807,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(34800,16,FLEN) +NAN_BOXED(34800,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(33799,16,FLEN) +NAN_BOXED(33799,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(34808,16,FLEN) +NAN_BOXED(34808,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(33795,16,FLEN) +NAN_BOXED(33795,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(34812,16,FLEN) +NAN_BOXED(34812,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(33793,16,FLEN) +NAN_BOXED(33793,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(34814,16,FLEN) +NAN_BOXED(34814,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(512,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(255,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(992,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x4_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x4_1: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x5_0: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_0: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_2: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_3: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_4: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_5: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_6: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_7: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_8: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_9: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_10: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_11: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_12: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_13: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_14: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_15: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_16: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_17: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_18: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_19: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_20: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_21: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_22: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_23: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_24: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_25: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_26: + .fill 94*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fsub_b12-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fsub_b12-01.S new file mode 100644 index 000000000..823e76d18 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fsub_b12-01.S @@ -0,0 +1,603 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 06:02:02 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fsub.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fsub.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fsub_b12 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fsub_b12) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x10,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rs2 == rd, rs1==x18, rs2==x18, rd==x18,fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1b3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x18; op2:x18; dest:x18; op1val:0x704c; op2val:0x704c; + valaddr_reg:x10; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9*/ +TEST_FPRR_OP(fsub.h, x18, x18, x18, dyn, 0, 0, x10, 0*FLEN/8, x22, x1, x9) + +inst_1: +// rs2 == rd != rs1, rs1==x14, rs2==x3, rd==x3,fs1 == 0 and fe1 == 0x1e and fm1 == 0x21b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x011 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x14; op2:x3; dest:x3; op1val:0x7a1b; op2val:0x7811; + valaddr_reg:x10; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9*/ +TEST_FPRR_OP(fsub.h, x3, x14, x3, dyn, 0, 0, x10, 2*FLEN/8, x22, x1, x9) + +inst_2: +// rs1 == rd != rs2, rs1==x12, rs2==x17, rd==x12,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ec and fs2 == 0 and fe2 == 0x1a and fm2 == 0x1e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x12; op2:x17; dest:x12; op1val:0x77ec; op2val:0x69e0; + valaddr_reg:x10; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9*/ +TEST_FPRR_OP(fsub.h, x12, x12, x17, dyn, 0, 0, x10, 4*FLEN/8, x22, x1, x9) + +inst_3: +// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==x17, rs2==x15, rd==x2,fs1 == 0 and fe1 == 0x1e and fm1 == 0x135 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x062 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x17; op2:x15; dest:x2; op1val:0x7935; op2val:0xf062; + valaddr_reg:x10; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9*/ +TEST_FPRR_OP(fsub.h, x2, x17, x15, dyn, 0, 0, x10, 6*FLEN/8, x22, x1, x9) + +inst_4: +// rs1 == rs2 != rd, rs1==x29, rs2==x29, rd==x6,fs1 == 0 and fe1 == 0x1b and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x030 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x29; op2:x29; dest:x6; op1val:0x6e01; op2val:0x6e01; + valaddr_reg:x10; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9*/ +TEST_FPRR_OP(fsub.h, x6, x29, x29, dyn, 0, 0, x10, 8*FLEN/8, x22, x1, x9) + +inst_5: +// rs1==x13, rs2==x8, rd==x5,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x1d and fm2 == 0x271 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x13; op2:x8; dest:x5; op1val:0x7aae; op2val:0x7671; + valaddr_reg:x10; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9*/ +TEST_FPRR_OP(fsub.h, x5, x13, x8, dyn, 0, 0, x10, 10*FLEN/8, x22, x1, x9) + +inst_6: +// rs1==x20, rs2==x6, rd==x29,fs1 == 0 and fe1 == 0x1e and fm1 == 0x218 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x214 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x20; op2:x6; dest:x29; op1val:0x7a18; op2val:0x7a14; + valaddr_reg:x10; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9*/ +TEST_FPRR_OP(fsub.h, x29, x20, x6, dyn, 0, 0, x10, 12*FLEN/8, x22, x1, x9) + +inst_7: +// rs1==x2, rs2==x13, rd==x27,fs1 == 0 and fe1 == 0x1d and fm1 == 0x31f and fs2 == 1 and fe2 == 0x1d and fm2 == 0x06a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x2; op2:x13; dest:x27; op1val:0x771f; op2val:0xf46a; + valaddr_reg:x10; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9*/ +TEST_FPRR_OP(fsub.h, x27, x2, x13, dyn, 0, 0, x10, 14*FLEN/8, x22, x1, x9) + +inst_8: +// rs1==x8, rs2==x27, rd==x14,fs1 == 0 and fe1 == 0x1c and fm1 == 0x351 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1ba and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x8; op2:x27; dest:x14; op1val:0x7351; op2val:0xf9ba; + valaddr_reg:x10; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9*/ +TEST_FPRR_OP(fsub.h, x14, x8, x27, dyn, 0, 0, x10, 16*FLEN/8, x22, x1, x9) + +inst_9: +// rs1==x11, rs2==x23, rd==x4,fs1 == 0 and fe1 == 0x1e and fm1 == 0x335 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2f6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x11; op2:x23; dest:x4; op1val:0x7b35; op2val:0x7af6; + valaddr_reg:x10; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9*/ +TEST_FPRR_OP(fsub.h, x4, x11, x23, dyn, 0, 0, x10, 18*FLEN/8, x22, x1, x9) + +inst_10: +// rs1==x21, rs2==x12, rd==x13,fs1 == 0 and fe1 == 0x19 and fm1 == 0x282 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x020 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x21; op2:x12; dest:x13; op1val:0x6682; op2val:0xf820; + valaddr_reg:x10; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9*/ +TEST_FPRR_OP(fsub.h, x13, x21, x12, dyn, 0, 0, x10, 20*FLEN/8, x22, x1, x9) + +inst_11: +// rs1==x15, rs2==x7, rd==x31,fs1 == 0 and fe1 == 0x1e and fm1 == 0x382 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x076 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x15; op2:x7; dest:x31; op1val:0x7b82; op2val:0x7876; + valaddr_reg:x10; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9*/ +TEST_FPRR_OP(fsub.h, x31, x15, x7, dyn, 0, 0, x10, 22*FLEN/8, x22, x1, x9) + +inst_12: +// rs1==x26, rs2==x19, rd==x16,fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ed and fs2 == 1 and fe2 == 0x1c and fm2 == 0x292 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x26; op2:x19; dest:x16; op1val:0x72ed; op2val:0xf292; + valaddr_reg:x10; val_offset:24*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9*/ +TEST_FPRR_OP(fsub.h, x16, x26, x19, dyn, 0, 0, x10, 24*FLEN/8, x22, x1, x9) +RVTEST_VALBASEUPD(x13,test_dataset_1) + +inst_13: +// rs1==x22, rs2==x14, rd==x8,fs1 == 0 and fe1 == 0x19 and fm1 == 0x36e and fs2 == 1 and fe2 == 0x1c and fm2 == 0x229 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x22; op2:x14; dest:x8; op1val:0x676e; op2val:0xf229; + valaddr_reg:x13; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9*/ +TEST_FPRR_OP(fsub.h, x8, x22, x14, dyn, 0, 0, x13, 0*FLEN/8, x16, x1, x9) + +inst_14: +// rs1==x31, rs2==x4, rd==x10,fs1 == 0 and fe1 == 0x1d and fm1 == 0x300 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x369 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x31; op2:x4; dest:x10; op1val:0x7700; op2val:0xeb69; + valaddr_reg:x13; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x9*/ +TEST_FPRR_OP(fsub.h, x10, x31, x4, dyn, 0, 0, x13, 2*FLEN/8, x16, x1, x9) + +inst_15: +// rs1==x0, rs2==x20, rd==x15,fs1 == 0 and fe1 == 0x1c and fm1 == 0x374 and fs2 == 0 and fe2 == 0x16 and fm2 == 0x084 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x0; op2:x20; dest:x15; op1val:0x0; op2val:0x5884; + valaddr_reg:x13; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12*/ +TEST_FPRR_OP(fsub.h, x15, x0, x20, dyn, 0, 0, x13, 4*FLEN/8, x16, x1, x12) + +inst_16: +// rs1==x30, rs2==x5, rd==x11,fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ff and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3b3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x5; dest:x11; op1val:0x72ff; op2val:0xf3b3; + valaddr_reg:x13; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12*/ +TEST_FPRR_OP(fsub.h, x11, x30, x5, dyn, 0, 0, x13, 6*FLEN/8, x16, x1, x12) +RVTEST_SIGBASE(x8,signature_x8_0) + +inst_17: +// rs1==x6, rs2==x25, rd==x9,fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a2 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x04a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x6; op2:x25; dest:x9; op1val:0x74a2; op2val:0x744a; + valaddr_reg:x13; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12*/ +TEST_FPRR_OP(fsub.h, x9, x6, x25, dyn, 0, 0, x13, 8*FLEN/8, x16, x8, x12) + +inst_18: +// rs1==x9, rs2==x31, rd==x21,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b2 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x07e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x9; op2:x31; dest:x21; op1val:0x7ab2; op2val:0x747e; + valaddr_reg:x13; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12*/ +TEST_FPRR_OP(fsub.h, x21, x9, x31, dyn, 0, 0, x13, 10*FLEN/8, x16, x8, x12) + +inst_19: +// rs1==x27, rs2==x2, rd==x0,fs1 == 0 and fe1 == 0x1e and fm1 == 0x122 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x34c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x27; op2:x2; dest:x0; op1val:0x7922; op2val:0x774c; + valaddr_reg:x13; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12*/ +TEST_FPRR_OP(fsub.h, x0, x27, x2, dyn, 0, 0, x13, 12*FLEN/8, x16, x8, x12) + +inst_20: +// rs1==x28, rs2==x0, rd==x23,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ef and fs2 == 0 and fe2 == 0x1c and fm2 == 0x03d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x28; op2:x0; dest:x23; op1val:0x7bef; op2val:0x0; + valaddr_reg:x13; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12*/ +TEST_FPRR_OP(fsub.h, x23, x28, x0, dyn, 0, 0, x13, 14*FLEN/8, x16, x8, x12) + +inst_21: +// rs1==x7, rs2==x9, rd==x24,fs1 == 0 and fe1 == 0x1b and fm1 == 0x3bb and fs2 == 1 and fe2 == 0x1c and fm2 == 0x2c6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x7; op2:x9; dest:x24; op1val:0x6fbb; op2val:0xf2c6; + valaddr_reg:x13; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12*/ +TEST_FPRR_OP(fsub.h, x24, x7, x9, dyn, 0, 0, x13, 16*FLEN/8, x16, x8, x12) + +inst_22: +// rs1==x3, rs2==x10, rd==x30,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c4 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x143 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x3; op2:x10; dest:x30; op1val:0x79c4; op2val:0x6143; + valaddr_reg:x13; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12*/ +TEST_FPRR_OP(fsub.h, x30, x3, x10, dyn, 0, 0, x13, 18*FLEN/8, x16, x8, x12) + +inst_23: +// rs1==x5, rs2==x11, rd==x17,fs1 == 0 and fe1 == 0x1e and fm1 == 0x37c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x01c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x5; op2:x11; dest:x17; op1val:0x7b7c; op2val:0x781c; + valaddr_reg:x13; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12*/ +TEST_FPRR_OP(fsub.h, x17, x5, x11, dyn, 0, 0, x13, 20*FLEN/8, x16, x8, x12) +RVTEST_VALBASEUPD(x3,test_dataset_2) + +inst_24: +// rs1==x10, rs2==x26, rd==x25,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a3 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x11b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x10; op2:x26; dest:x25; op1val:0x7aa3; op2val:0x711b; + valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12*/ +TEST_FPRR_OP(fsub.h, x25, x10, x26, dyn, 0, 0, x3, 0*FLEN/8, x6, x8, x12) + +inst_25: +// rs1==x1, rs2==x28, rd==x26,fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d9 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x08b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x1; op2:x28; dest:x26; op1val:0x74d9; op2val:0xf48b; + valaddr_reg:x3; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12*/ +TEST_FPRR_OP(fsub.h, x26, x1, x28, dyn, 0, 0, x3, 2*FLEN/8, x6, x8, x12) + +inst_26: +// rs1==x16, rs2==x22, rd==x28,fs1 == 0 and fe1 == 0x1e and fm1 == 0x30e and fs2 == 0 and fe2 == 0x1a and fm2 == 0x0a4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x16; op2:x22; dest:x28; op1val:0x7b0e; op2val:0x68a4; + valaddr_reg:x3; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12*/ +TEST_FPRR_OP(fsub.h, x28, x16, x22, dyn, 0, 0, x3, 4*FLEN/8, x6, x8, x12) + +inst_27: +// rs1==x25, rs2==x16, rd==x19,fs1 == 0 and fe1 == 0x1e and fm1 == 0x00a and fs2 == 1 and fe2 == 0x1b and fm2 == 0x15b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x25; op2:x16; dest:x19; op1val:0x780a; op2val:0xed5b; + valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12*/ +TEST_FPRR_OP(fsub.h, x19, x25, x16, dyn, 0, 0, x3, 6*FLEN/8, x6, x8, x12) + +inst_28: +// rs1==x19, rs2==x30, rd==x20,fs1 == 0 and fe1 == 0x1a and fm1 == 0x06a and fs2 == 1 and fe2 == 0x1c and fm2 == 0x2a8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x19; op2:x30; dest:x20; op1val:0x686a; op2val:0xf2a8; + valaddr_reg:x3; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12*/ +TEST_FPRR_OP(fsub.h, x20, x19, x30, dyn, 0, 0, x3, 8*FLEN/8, x6, x8, x12) + +inst_29: +// rs1==x24, rs2==x21, rd==x7,fs1 == 0 and fe1 == 0x1e and fm1 == 0x260 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x220 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x24; op2:x21; dest:x7; op1val:0x7a60; op2val:0x7620; + valaddr_reg:x3; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12*/ +TEST_FPRR_OP(fsub.h, x7, x24, x21, dyn, 0, 0, x3, 10*FLEN/8, x6, x8, x12) + +inst_30: +// rs1==x4, rs2==x24, rd==x22,fs1 == 0 and fe1 == 0x1c and fm1 == 0x188 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x202 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x4; op2:x24; dest:x22; op1val:0x7188; op2val:0xf602; + valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12*/ +TEST_FPRR_OP(fsub.h, x22, x4, x24, dyn, 0, 0, x3, 12*FLEN/8, x6, x8, x12) + +inst_31: +// rs1==x23,fs1 == 0 and fe1 == 0x1e and fm1 == 0x19f and fs2 == 0 and fe2 == 0x19 and fm2 == 0x34e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x23; op2:x22; dest:x0; op1val:0x799f; op2val:0x674e; + valaddr_reg:x3; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x0, x23, x22, dyn, 0, 0, x3, 14*FLEN/8, x6, x8, x2) + +inst_32: +// rs2==x1,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1fe and fs2 == 1 and fe2 == 0x1b and fm2 == 0x01c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x26; op2:x1; dest:x31; op1val:0x75fe; op2val:0xec1c; + valaddr_reg:x3; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x26, x1, dyn, 0, 0, x3, 16*FLEN/8, x6, x8, x2) + +inst_33: +// rd==x1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x010 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x051 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x5; op2:x21; dest:x1; op1val:0x7810; op2val:0xf451; + valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x1, x5, x21, dyn, 0, 0, x3, 18*FLEN/8, x6, x8, x2) + +inst_34: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02a and fs2 == 0 and fe2 == 0x1c and fm2 == 0x015 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x782a; op2val:0x7015; + valaddr_reg:x3; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 20*FLEN/8, x6, x8, x2) + +inst_35: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d4 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x35b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x77d4; op2val:0x775b; + valaddr_reg:x3; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 22*FLEN/8, x6, x8, x2) + +inst_36: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x190 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x146 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6990; op2val:0xf946; + valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 24*FLEN/8, x6, x8, x2) + +inst_37: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3dc and fs2 == 0 and fe2 == 0x1d and fm2 == 0x23c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bdc; op2val:0x763c; + valaddr_reg:x3; val_offset:26*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 26*FLEN/8, x6, x8, x2) + +inst_38: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x24b and fs2 == 0 and fe2 == 0x1c and fm2 == 0x323 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x764b; op2val:0x7323; + valaddr_reg:x3; val_offset:28*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 28*FLEN/8, x6, x8, x2) + +inst_39: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3ac and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7804; op2val:0xf7ac; + valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 30*FLEN/8, x6, x8, x2) + +inst_40: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x229 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x362 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a29; op2val:0x7362; + valaddr_reg:x3; val_offset:32*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 32*FLEN/8, x6, x8, x2) + +inst_41: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x105 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ae1; op2val:0x7905; + valaddr_reg:x3; val_offset:34*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 34*FLEN/8, x6, x8, x2) + +inst_42: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x01b and fs2 == 1 and fe2 == 0x1d and fm2 == 0x304 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x781b; op2val:0xf704; + valaddr_reg:x3; val_offset:36*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 36*FLEN/8, x6, x8, x2) + +inst_43: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09e and fs2 == 0 and fe2 == 0x1b and fm2 == 0x397 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x789e; op2val:0x6f97; + valaddr_reg:x3; val_offset:38*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 38*FLEN/8, x6, x8, x2) + +inst_44: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x04e and fs2 == 1 and fe2 == 0x1d and fm2 == 0x075 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x744e; op2val:0xf475; + valaddr_reg:x3; val_offset:40*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 40*FLEN/8, x6, x8, x2) + +inst_45: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x39b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba7; op2val:0x7b9b; + valaddr_reg:x3; val_offset:42*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 42*FLEN/8, x6, x8, x2) + +inst_46: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x244 and fs2 == 1 and fe2 == 0x1a and fm2 == 0x0b6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a44; op2val:0xe8b6; + valaddr_reg:x3; val_offset:44*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 44*FLEN/8, x6, x8, x2) + +inst_47: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x316 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0a8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b16; op2val:0x70a8; + valaddr_reg:x3; val_offset:46*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 46*FLEN/8, x6, x8, x2) + +inst_48: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x278 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0a5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a78; op2val:0x74a5; + valaddr_reg:x3; val_offset:48*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 48*FLEN/8, x6, x8, x2) + +inst_49: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x07d and fs2 == 0 and fe2 == 0x1c and fm2 == 0x053 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x787d; op2val:0x7053; + valaddr_reg:x3; val_offset:50*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 50*FLEN/8, x6, x8, x2) + +inst_50: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1b3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x704c; op2val:0xf9b3; + valaddr_reg:x3; val_offset:52*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 52*FLEN/8, x6, x8, x2) + +inst_51: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x030 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e01; op2val:0x6c30; + valaddr_reg:x3; val_offset:54*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 54*FLEN/8, x6, x8, x2) + +inst_52: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x374 and fs2 == 0 and fe2 == 0x16 and fm2 == 0x084 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7374; op2val:0x5884; + valaddr_reg:x3; val_offset:56*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 56*FLEN/8, x6, x8, x2) + +inst_53: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x122 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x34c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7922; op2val:0x774c; + valaddr_reg:x3; val_offset:58*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 58*FLEN/8, x6, x8, x2) + +inst_54: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ef and fs2 == 0 and fe2 == 0x1c and fm2 == 0x03d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bef; op2val:0x703d; + valaddr_reg:x3; val_offset:60*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 60*FLEN/8, x6, x8, x2) + +inst_55: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19f and fs2 == 0 and fe2 == 0x19 and fm2 == 0x34e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x799f; op2val:0x674e; + valaddr_reg:x3; val_offset:62*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 62*FLEN/8, x6, x8, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(28748,32,FLEN) +NAN_BOXED(28748,16,FLEN) +NAN_BOXED(31259,32,FLEN) +NAN_BOXED(30737,32,FLEN) +NAN_BOXED(30700,32,FLEN) +NAN_BOXED(27104,32,FLEN) +NAN_BOXED(31029,32,FLEN) +NAN_BOXED(61538,16,FLEN) +NAN_BOXED(28161,32,FLEN) +NAN_BOXED(28161,32,FLEN) +NAN_BOXED(31406,32,FLEN) +NAN_BOXED(30321,32,FLEN) +NAN_BOXED(31256,32,FLEN) +NAN_BOXED(31252,32,FLEN) +NAN_BOXED(30495,32,FLEN) +NAN_BOXED(62570,16,FLEN) +NAN_BOXED(29521,32,FLEN) +NAN_BOXED(63930,16,FLEN) +NAN_BOXED(31541,32,FLEN) +NAN_BOXED(31478,32,FLEN) +NAN_BOXED(26242,32,FLEN) +NAN_BOXED(63520,16,FLEN) +NAN_BOXED(31618,32,FLEN) +NAN_BOXED(30838,32,FLEN) +NAN_BOXED(29421,32,FLEN) +NAN_BOXED(62098,16,FLEN) +test_dataset_1: +NAN_BOXED(26478,32,FLEN) +NAN_BOXED(61993,16,FLEN) +NAN_BOXED(30464,32,FLEN) +NAN_BOXED(60265,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(22660,32,FLEN) +NAN_BOXED(29439,32,FLEN) +NAN_BOXED(62387,16,FLEN) +NAN_BOXED(29858,32,FLEN) +NAN_BOXED(29770,32,FLEN) +NAN_BOXED(31410,32,FLEN) +NAN_BOXED(29822,32,FLEN) +NAN_BOXED(31010,32,FLEN) +NAN_BOXED(30540,32,FLEN) +NAN_BOXED(31727,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(28603,32,FLEN) +NAN_BOXED(62150,16,FLEN) +NAN_BOXED(31172,32,FLEN) +NAN_BOXED(24899,32,FLEN) +NAN_BOXED(31612,32,FLEN) +NAN_BOXED(30748,32,FLEN) +test_dataset_2: +NAN_BOXED(31395,16,FLEN) +NAN_BOXED(28955,16,FLEN) +NAN_BOXED(29913,16,FLEN) +NAN_BOXED(62603,16,FLEN) +NAN_BOXED(31502,16,FLEN) +NAN_BOXED(26788,16,FLEN) +NAN_BOXED(30730,16,FLEN) +NAN_BOXED(60763,16,FLEN) +NAN_BOXED(26730,16,FLEN) +NAN_BOXED(62120,16,FLEN) +NAN_BOXED(31328,16,FLEN) +NAN_BOXED(30240,16,FLEN) +NAN_BOXED(29064,16,FLEN) +NAN_BOXED(62978,16,FLEN) +NAN_BOXED(31135,16,FLEN) +NAN_BOXED(26446,16,FLEN) +NAN_BOXED(30206,16,FLEN) +NAN_BOXED(60444,16,FLEN) +NAN_BOXED(30736,16,FLEN) +NAN_BOXED(62545,16,FLEN) +NAN_BOXED(30762,16,FLEN) +NAN_BOXED(28693,16,FLEN) +NAN_BOXED(30676,16,FLEN) +NAN_BOXED(30555,16,FLEN) +NAN_BOXED(27024,16,FLEN) +NAN_BOXED(63814,16,FLEN) +NAN_BOXED(31708,16,FLEN) +NAN_BOXED(30268,16,FLEN) +NAN_BOXED(30283,16,FLEN) +NAN_BOXED(29475,16,FLEN) +NAN_BOXED(30724,16,FLEN) +NAN_BOXED(63404,16,FLEN) +NAN_BOXED(31273,16,FLEN) +NAN_BOXED(29538,16,FLEN) +NAN_BOXED(31457,16,FLEN) +NAN_BOXED(30981,16,FLEN) +NAN_BOXED(30747,16,FLEN) +NAN_BOXED(63236,16,FLEN) +NAN_BOXED(30878,16,FLEN) +NAN_BOXED(28567,16,FLEN) +NAN_BOXED(29774,16,FLEN) +NAN_BOXED(62581,16,FLEN) +NAN_BOXED(31655,16,FLEN) +NAN_BOXED(31643,16,FLEN) +NAN_BOXED(31300,16,FLEN) +NAN_BOXED(59574,16,FLEN) +NAN_BOXED(31510,16,FLEN) +NAN_BOXED(28840,16,FLEN) +NAN_BOXED(31352,16,FLEN) +NAN_BOXED(29861,16,FLEN) +NAN_BOXED(30845,16,FLEN) +NAN_BOXED(28755,16,FLEN) +NAN_BOXED(28748,16,FLEN) +NAN_BOXED(63923,16,FLEN) +NAN_BOXED(28161,16,FLEN) +NAN_BOXED(27696,16,FLEN) +NAN_BOXED(29556,16,FLEN) +NAN_BOXED(22660,16,FLEN) +NAN_BOXED(31010,16,FLEN) +NAN_BOXED(30540,16,FLEN) +NAN_BOXED(31727,16,FLEN) +NAN_BOXED(28733,16,FLEN) +NAN_BOXED(31135,16,FLEN) +NAN_BOXED(26446,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 34*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x8_0: + .fill 78*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fsub_b13-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fsub_b13-01.S new file mode 100644 index 000000000..e4aa5ef5c --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fsub_b13-01.S @@ -0,0 +1,1922 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 06:02:02 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fsub.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fsub.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fsub_b13 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fsub_b13) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x9,test_dataset_0) +RVTEST_SIGBASE(x10,signature_x10_1) + +inst_0: +// rs1 == rs2 == rd, rs1==x7, rs2==x7, rd==x7,fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x7; op2:x7; dest:x7; op1val:0x704c; op2val:0x704c; + valaddr_reg:x9; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x14*/ +TEST_FPRR_OP(fsub.h, x7, x7, x7, dyn, 0, 0, x9, 0*FLEN/8, x15, x10, x14) + +inst_1: +// rs2 == rd != rs1, rs1==x16, rs2==x31, rd==x31,fs1 == 0 and fe1 == 0x1e and fm1 == 0x21b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x21b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x16; op2:x31; dest:x31; op1val:0x7a1b; op2val:0x7a1b; + valaddr_reg:x9; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x14*/ +TEST_FPRR_OP(fsub.h, x31, x16, x31, dyn, 0, 0, x9, 2*FLEN/8, x15, x10, x14) + +inst_2: +// rs1 == rd != rs2, rs1==x28, rs2==x11, rd==x28,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ec and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3ec and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x28; op2:x11; dest:x28; op1val:0x77ec; op2val:0x77ec; + valaddr_reg:x9; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x14*/ +TEST_FPRR_OP(fsub.h, x28, x28, x11, dyn, 0, 0, x9, 4*FLEN/8, x15, x10, x14) + +inst_3: +// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==x25, rs2==x16, rd==x19,fs1 == 0 and fe1 == 0x1e and fm1 == 0x135 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x135 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x25; op2:x16; dest:x19; op1val:0x7935; op2val:0x7935; + valaddr_reg:x9; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x14*/ +TEST_FPRR_OP(fsub.h, x19, x25, x16, dyn, 0, 0, x9, 6*FLEN/8, x15, x10, x14) + +inst_4: +// rs1 == rs2 != rd, rs1==x8, rs2==x8, rd==x27,fs1 == 0 and fe1 == 0x1b and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x8; op2:x8; dest:x27; op1val:0x6e01; op2val:0x6e01; + valaddr_reg:x9; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x14*/ +TEST_FPRR_OP(fsub.h, x27, x8, x8, dyn, 0, 0, x9, 8*FLEN/8, x15, x10, x14) + +inst_5: +// rs1==x5, rs2==x24, rd==x22,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ae and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x5; op2:x24; dest:x22; op1val:0x7aae; op2val:0x7aae; + valaddr_reg:x9; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x14*/ +TEST_FPRR_OP(fsub.h, x22, x5, x24, dyn, 0, 0, x9, 10*FLEN/8, x15, x10, x14) + +inst_6: +// rs1==x21, rs2==x25, rd==x29,fs1 == 0 and fe1 == 0x1e and fm1 == 0x218 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x218 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x21; op2:x25; dest:x29; op1val:0x7a18; op2val:0x7a18; + valaddr_reg:x9; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x14*/ +TEST_FPRR_OP(fsub.h, x29, x21, x25, dyn, 0, 0, x9, 12*FLEN/8, x15, x10, x14) + +inst_7: +// rs1==x3, rs2==x19, rd==x12,fs1 == 0 and fe1 == 0x1d and fm1 == 0x31f and fs2 == 0 and fe2 == 0x1d and fm2 == 0x31f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x3; op2:x19; dest:x12; op1val:0x771f; op2val:0x771f; + valaddr_reg:x9; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x14*/ +TEST_FPRR_OP(fsub.h, x12, x3, x19, dyn, 0, 0, x9, 14*FLEN/8, x15, x10, x14) + +inst_8: +// rs1==x0, rs2==x28, rd==x25,fs1 == 0 and fe1 == 0x1c and fm1 == 0x351 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x351 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x0; op2:x28; dest:x25; op1val:0x0; op2val:0x7351; + valaddr_reg:x9; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x14*/ +TEST_FPRR_OP(fsub.h, x25, x0, x28, dyn, 0, 0, x9, 16*FLEN/8, x15, x10, x14) + +inst_9: +// rs1==x12, rs2==x2, rd==x6,fs1 == 0 and fe1 == 0x1e and fm1 == 0x335 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x335 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x12; op2:x2; dest:x6; op1val:0x7b35; op2val:0x7b35; + valaddr_reg:x9; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x14*/ +TEST_FPRR_OP(fsub.h, x6, x12, x2, dyn, 0, 0, x9, 18*FLEN/8, x15, x10, x14) + +inst_10: +// rs1==x17, rs2==x29, rd==x13,fs1 == 0 and fe1 == 0x19 and fm1 == 0x282 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x282 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x17; op2:x29; dest:x13; op1val:0x6682; op2val:0x6682; + valaddr_reg:x9; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x14*/ +TEST_FPRR_OP(fsub.h, x13, x17, x29, dyn, 0, 0, x9, 20*FLEN/8, x15, x10, x14) + +inst_11: +// rs1==x31, rs2==x22, rd==x1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x382 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x382 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x31; op2:x22; dest:x1; op1val:0x7b82; op2val:0x7b82; + valaddr_reg:x9; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x14*/ +TEST_FPRR_OP(fsub.h, x1, x31, x22, dyn, 0, 0, x9, 22*FLEN/8, x15, x10, x14) + +inst_12: +// rs1==x4, rs2==x21, rd==x17,fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ed and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2ed and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x4; op2:x21; dest:x17; op1val:0x72ed; op2val:0x72ed; + valaddr_reg:x9; val_offset:24*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x14*/ +TEST_FPRR_OP(fsub.h, x17, x4, x21, dyn, 0, 0, x9, 24*FLEN/8, x15, x10, x14) + +inst_13: +// rs1==x26, rs2==x5, rd==x4,fs1 == 0 and fe1 == 0x19 and fm1 == 0x36e and fs2 == 0 and fe2 == 0x19 and fm2 == 0x36e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x26; op2:x5; dest:x4; op1val:0x676e; op2val:0x676e; + valaddr_reg:x9; val_offset:26*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x14*/ +TEST_FPRR_OP(fsub.h, x4, x26, x5, dyn, 0, 0, x9, 26*FLEN/8, x15, x10, x14) +RVTEST_VALBASEUPD(x18,test_dataset_1) + +inst_14: +// rs1==x24, rs2==x23, rd==x8,fs1 == 0 and fe1 == 0x1d and fm1 == 0x300 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x24; op2:x23; dest:x8; op1val:0x7700; op2val:0x7700; + valaddr_reg:x18; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x14*/ +TEST_FPRR_OP(fsub.h, x8, x24, x23, dyn, 0, 0, x18, 0*FLEN/8, x19, x10, x14) + +inst_15: +// rs1==x9, rs2==x4, rd==x11,fs1 == 0 and fe1 == 0x1c and fm1 == 0x374 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x374 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x9; op2:x4; dest:x11; op1val:0x7374; op2val:0x7374; + valaddr_reg:x18; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x14*/ +TEST_FPRR_OP(fsub.h, x11, x9, x4, dyn, 0, 0, x18, 2*FLEN/8, x19, x10, x14) + +inst_16: +// rs1==x23, rs2==x17, rd==x24,fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ff and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x23; op2:x17; dest:x24; op1val:0x72ff; op2val:0x72ff; + valaddr_reg:x18; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7*/ +TEST_FPRR_OP(fsub.h, x24, x23, x17, dyn, 0, 0, x18, 4*FLEN/8, x19, x10, x7) + +inst_17: +// rs1==x22, rs2==x20, rd==x14,fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a2 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0a2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x22; op2:x20; dest:x14; op1val:0x74a2; op2val:0x74a2; + valaddr_reg:x18; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7*/ +TEST_FPRR_OP(fsub.h, x14, x22, x20, dyn, 0, 0, x18, 6*FLEN/8, x19, x10, x7) +RVTEST_SIGBASE(x4,signature_x4_0) + +inst_18: +// rs1==x10, rs2==x27, rd==x15,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x10; op2:x27; dest:x15; op1val:0x7ab2; op2val:0x7ab2; + valaddr_reg:x18; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7*/ +TEST_FPRR_OP(fsub.h, x15, x10, x27, dyn, 0, 0, x18, 8*FLEN/8, x19, x4, x7) + +inst_19: +// rs1==x30, rs2==x12, rd==x26,fs1 == 0 and fe1 == 0x1e and fm1 == 0x122 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x122 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x12; dest:x26; op1val:0x7922; op2val:0x7922; + valaddr_reg:x18; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7*/ +TEST_FPRR_OP(fsub.h, x26, x30, x12, dyn, 0, 0, x18, 10*FLEN/8, x19, x4, x7) + +inst_20: +// rs1==x14, rs2==x9, rd==x16,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ef and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ef and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x14; op2:x9; dest:x16; op1val:0x7bef; op2val:0x7bef; + valaddr_reg:x18; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7*/ +TEST_FPRR_OP(fsub.h, x16, x14, x9, dyn, 0, 0, x18, 12*FLEN/8, x19, x4, x7) + +inst_21: +// rs1==x6, rs2==x15, rd==x21,fs1 == 0 and fe1 == 0x1b and fm1 == 0x3bb and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3bb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x6; op2:x15; dest:x21; op1val:0x6fbb; op2val:0x6fbb; + valaddr_reg:x18; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7*/ +TEST_FPRR_OP(fsub.h, x21, x6, x15, dyn, 0, 0, x18, 14*FLEN/8, x19, x4, x7) + +inst_22: +// rs1==x2, rs2==x26, rd==x10,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1c4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x2; op2:x26; dest:x10; op1val:0x79c4; op2val:0x79c4; + valaddr_reg:x18; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7*/ +TEST_FPRR_OP(fsub.h, x10, x2, x26, dyn, 0, 0, x18, 16*FLEN/8, x19, x4, x7) + +inst_23: +// rs1==x11, rs2==x1, rd==x5,fs1 == 0 and fe1 == 0x1e and fm1 == 0x37c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x37c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x11; op2:x1; dest:x5; op1val:0x7b7c; op2val:0x7b7c; + valaddr_reg:x18; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7*/ +TEST_FPRR_OP(fsub.h, x5, x11, x1, dyn, 0, 0, x18, 18*FLEN/8, x19, x4, x7) + +inst_24: +// rs1==x1, rs2==x13, rd==x9,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2a3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x1; op2:x13; dest:x9; op1val:0x7aa3; op2val:0x7aa3; + valaddr_reg:x18; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7*/ +TEST_FPRR_OP(fsub.h, x9, x1, x13, dyn, 0, 0, x18, 20*FLEN/8, x19, x4, x7) + +inst_25: +// rs1==x27, rs2==x30, rd==x3,fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d9 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0d9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x27; op2:x30; dest:x3; op1val:0x74d9; op2val:0x74d9; + valaddr_reg:x18; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7*/ +TEST_FPRR_OP(fsub.h, x3, x27, x30, dyn, 0, 0, x18, 22*FLEN/8, x19, x4, x7) +RVTEST_VALBASEUPD(x5,test_dataset_2) + +inst_26: +// rs1==x29, rs2==x3, rd==x20,fs1 == 0 and fe1 == 0x1e and fm1 == 0x30e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x30e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x29; op2:x3; dest:x20; op1val:0x7b0e; op2val:0x7b0e; + valaddr_reg:x5; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7*/ +TEST_FPRR_OP(fsub.h, x20, x29, x3, dyn, 0, 0, x5, 0*FLEN/8, x8, x4, x7) + +inst_27: +// rs1==x19, rs2==x0, rd==x2,fs1 == 0 and fe1 == 0x1e and fm1 == 0x00a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x00a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x19; op2:x0; dest:x2; op1val:0x780a; op2val:0x0; + valaddr_reg:x5; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7*/ +TEST_FPRR_OP(fsub.h, x2, x19, x0, dyn, 0, 0, x5, 2*FLEN/8, x8, x4, x7) + +inst_28: +// rs1==x20, rs2==x14, rd==x18,fs1 == 0 and fe1 == 0x1a and fm1 == 0x06a and fs2 == 0 and fe2 == 0x1a and fm2 == 0x06a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x20; op2:x14; dest:x18; op1val:0x686a; op2val:0x686a; + valaddr_reg:x5; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x7*/ +TEST_FPRR_OP(fsub.h, x18, x20, x14, dyn, 0, 0, x5, 4*FLEN/8, x8, x4, x7) + +inst_29: +// rs1==x15, rs2==x18, rd==x0,fs1 == 0 and fe1 == 0x1e and fm1 == 0x260 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x260 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x15; op2:x18; dest:x0; op1val:0x7a60; op2val:0x7a60; + valaddr_reg:x5; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x0, x15, x18, dyn, 0, 0, x5, 6*FLEN/8, x8, x4, x1) + +inst_30: +// rs1==x13, rs2==x10, rd==x23,fs1 == 0 and fe1 == 0x1c and fm1 == 0x188 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x188 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x13; op2:x10; dest:x23; op1val:0x7188; op2val:0x7188; + valaddr_reg:x5; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x23, x13, x10, dyn, 0, 0, x5, 8*FLEN/8, x8, x4, x1) + +inst_31: +// rs1==x18, rs2==x6, rd==x30,fs1 == 0 and fe1 == 0x1e and fm1 == 0x19f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x19f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x18; op2:x6; dest:x30; op1val:0x799f; op2val:0x799f; + valaddr_reg:x5; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x30, x18, x6, dyn, 0, 0, x5, 10*FLEN/8, x8, x4, x1) + +inst_32: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1fe and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x75fe; op2val:0x75fe; + valaddr_reg:x5; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 12*FLEN/8, x8, x4, x1) + +inst_33: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x010 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x010 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7810; op2val:0x7810; + valaddr_reg:x5; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 14*FLEN/8, x8, x4, x1) + +inst_34: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x02a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x782a; op2val:0x782a; + valaddr_reg:x5; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 16*FLEN/8, x8, x4, x1) + +inst_35: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d4 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3d4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x77d4; op2val:0x77d4; + valaddr_reg:x5; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 18*FLEN/8, x8, x4, x1) + +inst_36: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x190 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x190 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6990; op2val:0x6990; + valaddr_reg:x5; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 20*FLEN/8, x8, x4, x1) + +inst_37: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3dc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3dc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bdc; op2val:0x7bdc; + valaddr_reg:x5; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 22*FLEN/8, x8, x4, x1) + +inst_38: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x24b and fs2 == 0 and fe2 == 0x1d and fm2 == 0x24b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x764b; op2val:0x764b; + valaddr_reg:x5; val_offset:24*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 24*FLEN/8, x8, x4, x1) + +inst_39: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x004 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7804; op2val:0x7804; + valaddr_reg:x5; val_offset:26*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 26*FLEN/8, x8, x4, x1) + +inst_40: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x229 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x229 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a29; op2val:0x7a29; + valaddr_reg:x5; val_offset:28*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 28*FLEN/8, x8, x4, x1) + +inst_41: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2e1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ae1; op2val:0x7ae1; + valaddr_reg:x5; val_offset:30*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 30*FLEN/8, x8, x4, x1) + +inst_42: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x01b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x01b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x781b; op2val:0x781b; + valaddr_reg:x5; val_offset:32*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 32*FLEN/8, x8, x4, x1) + +inst_43: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x09e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x789e; op2val:0x789e; + valaddr_reg:x5; val_offset:34*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 34*FLEN/8, x8, x4, x1) + +inst_44: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x04e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x04e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x744e; op2val:0x744e; + valaddr_reg:x5; val_offset:36*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 36*FLEN/8, x8, x4, x1) + +inst_45: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3a7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba7; op2val:0x7ba7; + valaddr_reg:x5; val_offset:38*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 38*FLEN/8, x8, x4, x1) + +inst_46: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x244 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x244 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a44; op2val:0x7a44; + valaddr_reg:x5; val_offset:40*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 40*FLEN/8, x8, x4, x1) + +inst_47: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x316 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x316 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b16; op2val:0x7b16; + valaddr_reg:x5; val_offset:42*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 42*FLEN/8, x8, x4, x1) + +inst_48: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x278 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x278 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a78; op2val:0x7a78; + valaddr_reg:x5; val_offset:44*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 44*FLEN/8, x8, x4, x1) + +inst_49: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x07d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x07d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x787d; op2val:0x787d; + valaddr_reg:x5; val_offset:46*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 46*FLEN/8, x8, x4, x1) + +inst_50: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x32e and fs2 == 0 and fe2 == 0x1a and fm2 == 0x32e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6b2e; op2val:0x6b2e; + valaddr_reg:x5; val_offset:48*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 48*FLEN/8, x8, x4, x1) + +inst_51: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x08e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x08e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x788e; op2val:0x788e; + valaddr_reg:x5; val_offset:50*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 50*FLEN/8, x8, x4, x1) + +inst_52: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x009 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x009 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7809; op2val:0x7809; + valaddr_reg:x5; val_offset:52*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 52*FLEN/8, x8, x4, x1) + +inst_53: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1b4 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1b4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x75b4; op2val:0x75b4; + valaddr_reg:x5; val_offset:54*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 54*FLEN/8, x8, x4, x1) + +inst_54: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x04e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x784e; op2val:0x784e; + valaddr_reg:x5; val_offset:56*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 56*FLEN/8, x8, x4, x1) + +inst_55: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0e5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x78e5; op2val:0x78e5; + valaddr_reg:x5; val_offset:58*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 58*FLEN/8, x8, x4, x1) + +inst_56: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x328 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x328 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6728; op2val:0x6728; + valaddr_reg:x5; val_offset:60*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 60*FLEN/8, x8, x4, x1) + +inst_57: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1ab and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1ab and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x71ab; op2val:0x71ab; + valaddr_reg:x5; val_offset:62*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 62*FLEN/8, x8, x4, x1) + +inst_58: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2e2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ae2; op2val:0x7ae2; + valaddr_reg:x5; val_offset:64*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 64*FLEN/8, x8, x4, x1) + +inst_59: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x25f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a5f; op2val:0x7a5f; + valaddr_reg:x5; val_offset:66*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 66*FLEN/8, x8, x4, x1) + +inst_60: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x015 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x015 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7415; op2val:0x7415; + valaddr_reg:x5; val_offset:68*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 68*FLEN/8, x8, x4, x1) + +inst_61: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x161 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x161 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7961; op2val:0x7961; + valaddr_reg:x5; val_offset:70*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 70*FLEN/8, x8, x4, x1) + +inst_62: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x045 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x045 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6445; op2val:0x6445; + valaddr_reg:x5; val_offset:72*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 72*FLEN/8, x8, x4, x1) + +inst_63: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a0a; op2val:0x7a0a; + valaddr_reg:x5; val_offset:74*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 74*FLEN/8, x8, x4, x1) + +inst_64: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x300 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f00; op2val:0x6f00; + valaddr_reg:x5; val_offset:76*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 76*FLEN/8, x8, x4, x1) + +inst_65: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x182 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x182 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7582; op2val:0x7582; + valaddr_reg:x5; val_offset:78*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 78*FLEN/8, x8, x4, x1) + +inst_66: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x11b and fs2 == 0 and fe2 == 0x1c and fm2 == 0x11b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x711b; op2val:0x711b; + valaddr_reg:x5; val_offset:80*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 80*FLEN/8, x8, x4, x1) + +inst_67: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x160 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x160 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7160; op2val:0x7160; + valaddr_reg:x5; val_offset:82*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 82*FLEN/8, x8, x4, x1) + +inst_68: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1b0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b0; op2val:0x79b0; + valaddr_reg:x5; val_offset:84*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 84*FLEN/8, x8, x4, x1) + +inst_69: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x126 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x126 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7526; op2val:0x7526; + valaddr_reg:x5; val_offset:86*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 86*FLEN/8, x8, x4, x1) + +inst_70: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x20c and fs2 == 0 and fe2 == 0x19 and fm2 == 0x20c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x660c; op2val:0x660c; + valaddr_reg:x5; val_offset:88*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 88*FLEN/8, x8, x4, x1) + +inst_71: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2bb and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2bb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x76bb; op2val:0x76bb; + valaddr_reg:x5; val_offset:90*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 90*FLEN/8, x8, x4, x1) + +inst_72: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2f5 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2f5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ef5; op2val:0x6ef5; + valaddr_reg:x5; val_offset:92*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 92*FLEN/8, x8, x4, x1) + +inst_73: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x014 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x014 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7814; op2val:0x7814; + valaddr_reg:x5; val_offset:94*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 94*FLEN/8, x8, x4, x1) + +inst_74: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0d7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x78d7; op2val:0x78d7; + valaddr_reg:x5; val_offset:96*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 96*FLEN/8, x8, x4, x1) + +inst_75: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x153 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x153 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6553; op2val:0x6553; + valaddr_reg:x5; val_offset:98*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 98*FLEN/8, x8, x4, x1) + +inst_76: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0af and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0af and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x70af; op2val:0x70af; + valaddr_reg:x5; val_offset:100*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 100*FLEN/8, x8, x4, x1) + +inst_77: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x11f and fs2 == 0 and fe2 == 0x1c and fm2 == 0x11f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x711f; op2val:0x711f; + valaddr_reg:x5; val_offset:102*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 102*FLEN/8, x8, x4, x1) + +inst_78: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x16c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x16c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x796c; op2val:0x796c; + valaddr_reg:x5; val_offset:104*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 104*FLEN/8, x8, x4, x1) + +inst_79: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x30e and fs2 == 0 and fe2 == 0x1c and fm2 == 0x30e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x730e; op2val:0x730e; + valaddr_reg:x5; val_offset:106*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 106*FLEN/8, x8, x4, x1) + +inst_80: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x261 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x261 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a61; op2val:0x7a61; + valaddr_reg:x5; val_offset:108*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 108*FLEN/8, x8, x4, x1) + +inst_81: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x323 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x323 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7323; op2val:0x7323; + valaddr_reg:x5; val_offset:110*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 110*FLEN/8, x8, x4, x1) + +inst_82: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x250 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x250 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7650; op2val:0x7650; + valaddr_reg:x5; val_offset:112*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 112*FLEN/8, x8, x4, x1) + +inst_83: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x123 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x123 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7523; op2val:0x7523; + valaddr_reg:x5; val_offset:114*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 114*FLEN/8, x8, x4, x1) + +inst_84: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x385 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x385 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6b85; op2val:0x6b85; + valaddr_reg:x5; val_offset:116*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 116*FLEN/8, x8, x4, x1) + +inst_85: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3bd and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3bd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bbd; op2val:0x7bbd; + valaddr_reg:x5; val_offset:118*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 118*FLEN/8, x8, x4, x1) + +inst_86: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0e6 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0e6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74e6; op2val:0x74e6; + valaddr_reg:x5; val_offset:120*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 120*FLEN/8, x8, x4, x1) + +inst_87: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f6 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0f6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74f6; op2val:0x74f6; + valaddr_reg:x5; val_offset:122*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 122*FLEN/8, x8, x4, x1) + +inst_88: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1f2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79f2; op2val:0x79f2; + valaddr_reg:x5; val_offset:124*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 124*FLEN/8, x8, x4, x1) + +inst_89: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x009 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x009 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7409; op2val:0x7409; + valaddr_reg:x5; val_offset:126*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 126*FLEN/8, x8, x4, x1) + +inst_90: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x306 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x306 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b06; op2val:0x7b06; + valaddr_reg:x5; val_offset:128*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 128*FLEN/8, x8, x4, x1) + +inst_91: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x28d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a8d; op2val:0x7a8d; + valaddr_reg:x5; val_offset:130*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 130*FLEN/8, x8, x4, x1) + +inst_92: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x08f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x08f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x788f; op2val:0x788f; + valaddr_reg:x5; val_offset:132*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 132*FLEN/8, x8, x4, x1) + +inst_93: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7af0; op2val:0x7af0; + valaddr_reg:x5; val_offset:134*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 134*FLEN/8, x8, x4, x1) + +inst_94: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1a1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79a1; op2val:0x79a1; + valaddr_reg:x5; val_offset:136*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 136*FLEN/8, x8, x4, x1) + +inst_95: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x20b and fs2 == 0 and fe2 == 0x1d and fm2 == 0x20b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x760b; op2val:0x760b; + valaddr_reg:x5; val_offset:138*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 138*FLEN/8, x8, x4, x1) + +inst_96: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x294 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x294 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7294; op2val:0x7294; + valaddr_reg:x5; val_offset:140*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 140*FLEN/8, x8, x4, x1) + +inst_97: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2ec and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2ec and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x76ec; op2val:0x76ec; + valaddr_reg:x5; val_offset:142*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 142*FLEN/8, x8, x4, x1) + +inst_98: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2ae and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6eae; op2val:0x6eae; + valaddr_reg:x5; val_offset:144*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 144*FLEN/8, x8, x4, x1) + +inst_99: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0bc and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0bc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74bc; op2val:0x74bc; + valaddr_reg:x5; val_offset:146*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 146*FLEN/8, x8, x4, x1) + +inst_100: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x133 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x133 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7533; op2val:0x7533; + valaddr_reg:x5; val_offset:148*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 148*FLEN/8, x8, x4, x1) + +inst_101: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x331 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x331 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b31; op2val:0x7b31; + valaddr_reg:x5; val_offset:150*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 150*FLEN/8, x8, x4, x1) + +inst_102: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x26c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x26c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x726c; op2val:0x726c; + valaddr_reg:x5; val_offset:152*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 152*FLEN/8, x8, x4, x1) + +inst_103: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3e4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7be4; op2val:0x7be4; + valaddr_reg:x5; val_offset:154*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 154*FLEN/8, x8, x4, x1) + +inst_104: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x16c and fs2 == 0 and fe2 == 0x1d and fm2 == 0x16c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x756c; op2val:0x756c; + valaddr_reg:x5; val_offset:156*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 156*FLEN/8, x8, x4, x1) + +inst_105: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x164 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x164 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7964; op2val:0x7964; + valaddr_reg:x5; val_offset:158*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 158*FLEN/8, x8, x4, x1) + +inst_106: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x374 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x374 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b74; op2val:0x7b74; + valaddr_reg:x5; val_offset:160*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 160*FLEN/8, x8, x4, x1) + +inst_107: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3bf and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3bf and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x77bf; op2val:0x77bf; + valaddr_reg:x5; val_offset:162*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 162*FLEN/8, x8, x4, x1) + +inst_108: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x381 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x381 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7381; op2val:0x7381; + valaddr_reg:x5; val_offset:164*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 164*FLEN/8, x8, x4, x1) + +inst_109: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x16a and fs2 == 0 and fe2 == 0x1b and fm2 == 0x16a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d6a; op2val:0x6d6a; + valaddr_reg:x5; val_offset:166*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 166*FLEN/8, x8, x4, x1) + +inst_110: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x348 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x348 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b48; op2val:0x7b48; + valaddr_reg:x5; val_offset:168*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 168*FLEN/8, x8, x4, x1) + +inst_111: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x211 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x211 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a11; op2val:0x7a11; + valaddr_reg:x5; val_offset:170*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 170*FLEN/8, x8, x4, x1) + +inst_112: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab9; op2val:0x7ab9; + valaddr_reg:x5; val_offset:172*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 172*FLEN/8, x8, x4, x1) + +inst_113: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x171 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x171 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7571; op2val:0x7571; + valaddr_reg:x5; val_offset:174*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 174*FLEN/8, x8, x4, x1) + +inst_114: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ef and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aef; op2val:0x7aef; + valaddr_reg:x5; val_offset:176*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 176*FLEN/8, x8, x4, x1) + +inst_115: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3a1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba1; op2val:0x7ba1; + valaddr_reg:x5; val_offset:178*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 178*FLEN/8, x8, x4, x1) + +inst_116: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x054 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x054 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7054; op2val:0x7054; + valaddr_reg:x5; val_offset:180*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 180*FLEN/8, x8, x4, x1) + +inst_117: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2ab and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2ab and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6eab; op2val:0x6eab; + valaddr_reg:x5; val_offset:182*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 182*FLEN/8, x8, x4, x1) + +inst_118: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0ae and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0ae and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6cae; op2val:0x6cae; + valaddr_reg:x5; val_offset:184*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 184*FLEN/8, x8, x4, x1) + +inst_119: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x24d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x24d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a4d; op2val:0x7a4d; + valaddr_reg:x5; val_offset:186*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 186*FLEN/8, x8, x4, x1) + +inst_120: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x173 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x173 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7573; op2val:0x7573; + valaddr_reg:x5; val_offset:188*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 188*FLEN/8, x8, x4, x1) + +inst_121: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x240 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x240 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a40; op2val:0x7a40; + valaddr_reg:x5; val_offset:190*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 190*FLEN/8, x8, x4, x1) + +inst_122: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x090 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x090 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7890; op2val:0x7890; + valaddr_reg:x5; val_offset:192*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 192*FLEN/8, x8, x4, x1) + +inst_123: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x13a and fs2 == 0 and fe2 == 0x1b and fm2 == 0x13a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d3a; op2val:0x6d3a; + valaddr_reg:x5; val_offset:194*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 194*FLEN/8, x8, x4, x1) + +inst_124: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x31f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x31f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b1f; op2val:0x7b1f; + valaddr_reg:x5; val_offset:196*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 196*FLEN/8, x8, x4, x1) + +inst_125: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x365 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x365 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b65; op2val:0x7b65; + valaddr_reg:x5; val_offset:198*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 198*FLEN/8, x8, x4, x1) + +inst_126: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x06e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x06e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x746e; op2val:0x746e; + valaddr_reg:x5; val_offset:200*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 200*FLEN/8, x8, x4, x1) + +inst_127: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x29e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x29e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a9e; op2val:0x7a9e; + valaddr_reg:x5; val_offset:202*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 202*FLEN/8, x8, x4, x1) + +inst_128: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x15c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x795c; op2val:0x795c; + valaddr_reg:x5; val_offset:204*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 204*FLEN/8, x8, x4, x1) + +inst_129: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x35c and fs2 == 0 and fe2 == 0x1b and fm2 == 0x35c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f5c; op2val:0x6f5c; + valaddr_reg:x5; val_offset:206*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 206*FLEN/8, x8, x4, x1) + +inst_130: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x11e and fs2 == 0 and fe2 == 0x1a and fm2 == 0x11e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x691e; op2val:0x691e; + valaddr_reg:x5; val_offset:208*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 208*FLEN/8, x8, x4, x1) + +inst_131: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3e6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7be6; op2val:0x7be6; + valaddr_reg:x5; val_offset:210*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 210*FLEN/8, x8, x4, x1) + +inst_132: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x364 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x364 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f64; op2val:0x6f64; + valaddr_reg:x5; val_offset:212*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 212*FLEN/8, x8, x4, x1) + +inst_133: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3b8 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3b8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x73b8; op2val:0x73b8; + valaddr_reg:x5; val_offset:214*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 214*FLEN/8, x8, x4, x1) + +inst_134: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x294 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x294 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e94; op2val:0x6e94; + valaddr_reg:x5; val_offset:216*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 216*FLEN/8, x8, x4, x1) + +inst_135: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x20c and fs2 == 0 and fe2 == 0x1d and fm2 == 0x20c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x760c; op2val:0x760c; + valaddr_reg:x5; val_offset:218*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 218*FLEN/8, x8, x4, x1) + +inst_136: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x345 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x345 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b45; op2val:0x7b45; + valaddr_reg:x5; val_offset:220*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 220*FLEN/8, x8, x4, x1) + +inst_137: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x00d and fs2 == 0 and fe2 == 0x1d and fm2 == 0x00d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x740d; op2val:0x740d; + valaddr_reg:x5; val_offset:222*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 222*FLEN/8, x8, x4, x1) + +inst_138: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x267 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x267 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e67; op2val:0x6e67; + valaddr_reg:x5; val_offset:224*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 224*FLEN/8, x8, x4, x1) + +inst_139: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x111 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x111 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6911; op2val:0x6911; + valaddr_reg:x5; val_offset:226*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 226*FLEN/8, x8, x4, x1) + +inst_140: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3db and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3db and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bdb; op2val:0x7bdb; + valaddr_reg:x5; val_offset:228*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 228*FLEN/8, x8, x4, x1) + +inst_141: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0c5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x78c5; op2val:0x78c5; + valaddr_reg:x5; val_offset:230*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 230*FLEN/8, x8, x4, x1) + +inst_142: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x102 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x102 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7502; op2val:0x7502; + valaddr_reg:x5; val_offset:232*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 232*FLEN/8, x8, x4, x1) + +inst_143: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x34d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x34d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b4d; op2val:0x7b4d; + valaddr_reg:x5; val_offset:234*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 234*FLEN/8, x8, x4, x1) + +inst_144: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3c1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bc1; op2val:0x7bc1; + valaddr_reg:x5; val_offset:236*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 236*FLEN/8, x8, x4, x1) + +inst_145: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2e2 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2e2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x72e2; op2val:0x72e2; + valaddr_reg:x5; val_offset:238*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 238*FLEN/8, x8, x4, x1) +RVTEST_SIGBASE(x4,signature_x4_1) + +inst_146: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3d5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bd5; op2val:0x7bd5; + valaddr_reg:x5; val_offset:240*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 240*FLEN/8, x8, x4, x1) + +inst_147: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x180 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x180 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7980; op2val:0x7980; + valaddr_reg:x5; val_offset:242*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 242*FLEN/8, x8, x4, x1) + +inst_148: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x024 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x024 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7424; op2val:0x7424; + valaddr_reg:x5; val_offset:244*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 244*FLEN/8, x8, x4, x1) + +inst_149: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ea and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0ea and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74ea; op2val:0x74ea; + valaddr_reg:x5; val_offset:246*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 246*FLEN/8, x8, x4, x1) + +inst_150: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x134 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x134 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d34; op2val:0x6d34; + valaddr_reg:x5; val_offset:248*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 248*FLEN/8, x8, x4, x1) + +inst_151: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x136 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x136 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7936; op2val:0x7936; + valaddr_reg:x5; val_offset:250*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 250*FLEN/8, x8, x4, x1) + +inst_152: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x385 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x385 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b85; op2val:0x7b85; + valaddr_reg:x5; val_offset:252*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 252*FLEN/8, x8, x4, x1) + +inst_153: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0e7 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0e7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74e7; op2val:0x74e7; + valaddr_reg:x5; val_offset:254*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 254*FLEN/8, x8, x4, x1) + +inst_154: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x110 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x110 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7510; op2val:0x7510; + valaddr_reg:x5; val_offset:256*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 256*FLEN/8, x8, x4, x1) + +inst_155: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x324 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x324 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b24; op2val:0x7b24; + valaddr_reg:x5; val_offset:258*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 258*FLEN/8, x8, x4, x1) + +inst_156: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x158 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x158 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7558; op2val:0x7558; + valaddr_reg:x5; val_offset:260*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 260*FLEN/8, x8, x4, x1) + +inst_157: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0a1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x78a1; op2val:0x78a1; + valaddr_reg:x5; val_offset:262*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 262*FLEN/8, x8, x4, x1) + +inst_158: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3d6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x73d6; op2val:0x73d6; + valaddr_reg:x5; val_offset:264*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 264*FLEN/8, x8, x4, x1) + +inst_159: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3cb and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3cb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x73cb; op2val:0x73cb; + valaddr_reg:x5; val_offset:266*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 266*FLEN/8, x8, x4, x1) + +inst_160: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x068 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x068 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7868; op2val:0x7868; + valaddr_reg:x5; val_offset:268*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 268*FLEN/8, x8, x4, x1) + +inst_161: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0ce and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0ce and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6cce; op2val:0x6cce; + valaddr_reg:x5; val_offset:270*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 270*FLEN/8, x8, x4, x1) + +inst_162: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a6 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0a6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74a6; op2val:0x74a6; + valaddr_reg:x5; val_offset:272*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 272*FLEN/8, x8, x4, x1) + +inst_163: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3e3 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3e3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x77e3; op2val:0x77e3; + valaddr_reg:x5; val_offset:274*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 274*FLEN/8, x8, x4, x1) + +inst_164: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0ee and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0ee and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x70ee; op2val:0x70ee; + valaddr_reg:x5; val_offset:276*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 276*FLEN/8, x8, x4, x1) + +inst_165: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x25b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a5b; op2val:0x7a5b; + valaddr_reg:x5; val_offset:278*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 278*FLEN/8, x8, x4, x1) + +inst_166: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x397 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x397 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b97; op2val:0x7b97; + valaddr_reg:x5; val_offset:280*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 280*FLEN/8, x8, x4, x1) + +inst_167: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x234 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x234 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a34; op2val:0x7a34; + valaddr_reg:x5; val_offset:282*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 282*FLEN/8, x8, x4, x1) + +inst_168: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x291 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x291 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a91; op2val:0x7a91; + valaddr_reg:x5; val_offset:284*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 284*FLEN/8, x8, x4, x1) + +inst_169: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2d6 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2d6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ed6; op2val:0x6ed6; + valaddr_reg:x5; val_offset:286*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 286*FLEN/8, x8, x4, x1) + +inst_170: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x359 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x359 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b59; op2val:0x7b59; + valaddr_reg:x5; val_offset:288*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 288*FLEN/8, x8, x4, x1) + +inst_171: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x325 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x325 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b25; op2val:0x7b25; + valaddr_reg:x5; val_offset:290*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 290*FLEN/8, x8, x4, x1) + +inst_172: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x347 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x347 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b47; op2val:0x7b47; + valaddr_reg:x5; val_offset:292*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 292*FLEN/8, x8, x4, x1) + +inst_173: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x10d and fs2 == 0 and fe2 == 0x1d and fm2 == 0x10d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x750d; op2val:0x750d; + valaddr_reg:x5; val_offset:294*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 294*FLEN/8, x8, x4, x1) + +inst_174: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x26d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a6d; op2val:0x7a6d; + valaddr_reg:x5; val_offset:296*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 296*FLEN/8, x8, x4, x1) + +inst_175: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab8; op2val:0x7ab8; + valaddr_reg:x5; val_offset:298*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 298*FLEN/8, x8, x4, x1) + +inst_176: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x183 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x183 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7983; op2val:0x7983; + valaddr_reg:x5; val_offset:300*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 300*FLEN/8, x8, x4, x1) + +inst_177: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2eb and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2eb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x76eb; op2val:0x76eb; + valaddr_reg:x5; val_offset:302*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 302*FLEN/8, x8, x4, x1) + +inst_178: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1b7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b7; op2val:0x79b7; + valaddr_reg:x5; val_offset:304*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 304*FLEN/8, x8, x4, x1) + +inst_179: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x00a and fs2 == 0 and fe2 == 0x1d and fm2 == 0x00a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x740a; op2val:0x740a; + valaddr_reg:x5; val_offset:306*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 306*FLEN/8, x8, x4, x1) + +inst_180: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3b4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb4; op2val:0x7bb4; + valaddr_reg:x5; val_offset:308*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 308*FLEN/8, x8, x4, x1) + +inst_181: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x064 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x064 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7864; op2val:0x7864; + valaddr_reg:x5; val_offset:310*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 310*FLEN/8, x8, x4, x1) + +inst_182: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ce and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ce and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ace; op2val:0x7ace; + valaddr_reg:x5; val_offset:312*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 312*FLEN/8, x8, x4, x1) + +inst_183: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x254 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x254 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7654; op2val:0x7654; + valaddr_reg:x5; val_offset:314*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 314*FLEN/8, x8, x4, x1) + +inst_184: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x020 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x020 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7420; op2val:0x7420; + valaddr_reg:x5; val_offset:316*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 316*FLEN/8, x8, x4, x1) + +inst_185: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x12b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x792b; op2val:0x792b; + valaddr_reg:x5; val_offset:318*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 318*FLEN/8, x8, x4, x1) + +inst_186: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ad and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1ad and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x75ad; op2val:0x75ad; + valaddr_reg:x5; val_offset:320*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 320*FLEN/8, x8, x4, x1) + +inst_187: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7000; op2val:0x7000; + valaddr_reg:x5; val_offset:322*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 322*FLEN/8, x8, x4, x1) + +inst_188: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2a0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aa0; op2val:0x7aa0; + valaddr_reg:x5; val_offset:324*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 324*FLEN/8, x8, x4, x1) + +inst_189: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26a and fs2 == 0 and fe2 == 0x1d and fm2 == 0x26a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x766a; op2val:0x766a; + valaddr_reg:x5; val_offset:326*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 326*FLEN/8, x8, x4, x1) + +inst_190: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x378 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x378 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7378; op2val:0x7378; + valaddr_reg:x5; val_offset:328*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 328*FLEN/8, x8, x4, x1) + +inst_191: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x03a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x03a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x783a; op2val:0x783a; + valaddr_reg:x5; val_offset:330*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 330*FLEN/8, x8, x4, x1) + +inst_192: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x130 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x130 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7930; op2val:0x7930; + valaddr_reg:x5; val_offset:332*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 332*FLEN/8, x8, x4, x1) + +inst_193: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x17d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x17d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x797d; op2val:0x797d; + valaddr_reg:x5; val_offset:334*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 334*FLEN/8, x8, x4, x1) + +inst_194: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39f and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x739f; op2val:0x739f; + valaddr_reg:x5; val_offset:336*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 336*FLEN/8, x8, x4, x1) + +inst_195: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a8 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3a8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x77a8; op2val:0x77a8; + valaddr_reg:x5; val_offset:338*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 338*FLEN/8, x8, x4, x1) + +inst_196: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x297 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x297 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7697; op2val:0x7697; + valaddr_reg:x5; val_offset:340*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 340*FLEN/8, x8, x4, x1) + +inst_197: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x704c; op2val:0x704c; + valaddr_reg:x5; val_offset:342*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 342*FLEN/8, x8, x4, x1) + +inst_198: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e01; op2val:0x6e01; + valaddr_reg:x5; val_offset:344*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 344*FLEN/8, x8, x4, x1) + +inst_199: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x351 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x351 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7351; op2val:0x7351; + valaddr_reg:x5; val_offset:346*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 346*FLEN/8, x8, x4, x1) + +inst_200: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x00a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x780a; op2val:0x780a; + valaddr_reg:x5; val_offset:348*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 348*FLEN/8, x8, x4, x1) + +inst_201: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x260 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x260 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a60; op2val:0x7a60; + valaddr_reg:x5; val_offset:350*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x5, 350*FLEN/8, x8, x4, x1) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(28748,32,FLEN) +NAN_BOXED(28748,32,FLEN) +NAN_BOXED(31259,32,FLEN) +NAN_BOXED(31259,32,FLEN) +NAN_BOXED(30700,32,FLEN) +NAN_BOXED(30700,32,FLEN) +NAN_BOXED(31029,32,FLEN) +NAN_BOXED(31029,32,FLEN) +NAN_BOXED(28161,32,FLEN) +NAN_BOXED(28161,32,FLEN) +NAN_BOXED(31406,32,FLEN) +NAN_BOXED(31406,32,FLEN) +NAN_BOXED(31256,32,FLEN) +NAN_BOXED(31256,32,FLEN) +NAN_BOXED(30495,32,FLEN) +NAN_BOXED(30495,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(29521,32,FLEN) +NAN_BOXED(31541,32,FLEN) +NAN_BOXED(31541,32,FLEN) +NAN_BOXED(26242,32,FLEN) +NAN_BOXED(26242,32,FLEN) +NAN_BOXED(31618,32,FLEN) +NAN_BOXED(31618,32,FLEN) +NAN_BOXED(29421,32,FLEN) +NAN_BOXED(29421,32,FLEN) +NAN_BOXED(26478,32,FLEN) +NAN_BOXED(26478,32,FLEN) +test_dataset_1: +NAN_BOXED(30464,32,FLEN) +NAN_BOXED(30464,32,FLEN) +NAN_BOXED(29556,32,FLEN) +NAN_BOXED(29556,32,FLEN) +NAN_BOXED(29439,32,FLEN) +NAN_BOXED(29439,32,FLEN) +NAN_BOXED(29858,32,FLEN) +NAN_BOXED(29858,32,FLEN) +NAN_BOXED(31410,32,FLEN) +NAN_BOXED(31410,32,FLEN) +NAN_BOXED(31010,32,FLEN) +NAN_BOXED(31010,32,FLEN) +NAN_BOXED(31727,32,FLEN) +NAN_BOXED(31727,32,FLEN) +NAN_BOXED(28603,32,FLEN) +NAN_BOXED(28603,32,FLEN) +NAN_BOXED(31172,32,FLEN) +NAN_BOXED(31172,32,FLEN) +NAN_BOXED(31612,32,FLEN) +NAN_BOXED(31612,32,FLEN) +NAN_BOXED(31395,32,FLEN) +NAN_BOXED(31395,32,FLEN) +NAN_BOXED(29913,32,FLEN) +NAN_BOXED(29913,32,FLEN) +test_dataset_2: +NAN_BOXED(31502,16,FLEN) +NAN_BOXED(31502,16,FLEN) +NAN_BOXED(30730,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(26730,16,FLEN) +NAN_BOXED(26730,16,FLEN) +NAN_BOXED(31328,16,FLEN) +NAN_BOXED(31328,16,FLEN) +NAN_BOXED(29064,16,FLEN) +NAN_BOXED(29064,16,FLEN) +NAN_BOXED(31135,16,FLEN) +NAN_BOXED(31135,16,FLEN) +NAN_BOXED(30206,16,FLEN) +NAN_BOXED(30206,16,FLEN) +NAN_BOXED(30736,16,FLEN) +NAN_BOXED(30736,16,FLEN) +NAN_BOXED(30762,16,FLEN) +NAN_BOXED(30762,16,FLEN) +NAN_BOXED(30676,16,FLEN) +NAN_BOXED(30676,16,FLEN) +NAN_BOXED(27024,16,FLEN) +NAN_BOXED(27024,16,FLEN) +NAN_BOXED(31708,16,FLEN) +NAN_BOXED(31708,16,FLEN) +NAN_BOXED(30283,16,FLEN) +NAN_BOXED(30283,16,FLEN) +NAN_BOXED(30724,16,FLEN) +NAN_BOXED(30724,16,FLEN) +NAN_BOXED(31273,16,FLEN) +NAN_BOXED(31273,16,FLEN) +NAN_BOXED(31457,16,FLEN) +NAN_BOXED(31457,16,FLEN) +NAN_BOXED(30747,16,FLEN) +NAN_BOXED(30747,16,FLEN) +NAN_BOXED(30878,16,FLEN) +NAN_BOXED(30878,16,FLEN) +NAN_BOXED(29774,16,FLEN) +NAN_BOXED(29774,16,FLEN) +NAN_BOXED(31655,16,FLEN) +NAN_BOXED(31655,16,FLEN) +NAN_BOXED(31300,16,FLEN) +NAN_BOXED(31300,16,FLEN) +NAN_BOXED(31510,16,FLEN) +NAN_BOXED(31510,16,FLEN) +NAN_BOXED(31352,16,FLEN) +NAN_BOXED(31352,16,FLEN) +NAN_BOXED(30845,16,FLEN) +NAN_BOXED(30845,16,FLEN) +NAN_BOXED(27438,16,FLEN) +NAN_BOXED(27438,16,FLEN) +NAN_BOXED(30862,16,FLEN) +NAN_BOXED(30862,16,FLEN) +NAN_BOXED(30729,16,FLEN) +NAN_BOXED(30729,16,FLEN) +NAN_BOXED(30132,16,FLEN) +NAN_BOXED(30132,16,FLEN) +NAN_BOXED(30798,16,FLEN) +NAN_BOXED(30798,16,FLEN) +NAN_BOXED(30949,16,FLEN) +NAN_BOXED(30949,16,FLEN) +NAN_BOXED(26408,16,FLEN) +NAN_BOXED(26408,16,FLEN) +NAN_BOXED(29099,16,FLEN) +NAN_BOXED(29099,16,FLEN) +NAN_BOXED(31458,16,FLEN) +NAN_BOXED(31458,16,FLEN) +NAN_BOXED(31327,16,FLEN) +NAN_BOXED(31327,16,FLEN) +NAN_BOXED(29717,16,FLEN) +NAN_BOXED(29717,16,FLEN) +NAN_BOXED(31073,16,FLEN) +NAN_BOXED(31073,16,FLEN) +NAN_BOXED(25669,16,FLEN) +NAN_BOXED(25669,16,FLEN) +NAN_BOXED(31242,16,FLEN) +NAN_BOXED(31242,16,FLEN) +NAN_BOXED(28416,16,FLEN) +NAN_BOXED(28416,16,FLEN) +NAN_BOXED(30082,16,FLEN) +NAN_BOXED(30082,16,FLEN) +NAN_BOXED(28955,16,FLEN) +NAN_BOXED(28955,16,FLEN) +NAN_BOXED(29024,16,FLEN) +NAN_BOXED(29024,16,FLEN) +NAN_BOXED(31152,16,FLEN) +NAN_BOXED(31152,16,FLEN) +NAN_BOXED(29990,16,FLEN) +NAN_BOXED(29990,16,FLEN) +NAN_BOXED(26124,16,FLEN) +NAN_BOXED(26124,16,FLEN) +NAN_BOXED(30395,16,FLEN) +NAN_BOXED(30395,16,FLEN) +NAN_BOXED(28405,16,FLEN) +NAN_BOXED(28405,16,FLEN) +NAN_BOXED(30740,16,FLEN) +NAN_BOXED(30740,16,FLEN) +NAN_BOXED(30935,16,FLEN) +NAN_BOXED(30935,16,FLEN) +NAN_BOXED(25939,16,FLEN) +NAN_BOXED(25939,16,FLEN) +NAN_BOXED(28847,16,FLEN) +NAN_BOXED(28847,16,FLEN) +NAN_BOXED(28959,16,FLEN) +NAN_BOXED(28959,16,FLEN) +NAN_BOXED(31084,16,FLEN) +NAN_BOXED(31084,16,FLEN) +NAN_BOXED(29454,16,FLEN) +NAN_BOXED(29454,16,FLEN) +NAN_BOXED(31329,16,FLEN) +NAN_BOXED(31329,16,FLEN) +NAN_BOXED(29475,16,FLEN) +NAN_BOXED(29475,16,FLEN) +NAN_BOXED(30288,16,FLEN) +NAN_BOXED(30288,16,FLEN) +NAN_BOXED(29987,16,FLEN) +NAN_BOXED(29987,16,FLEN) +NAN_BOXED(27525,16,FLEN) +NAN_BOXED(27525,16,FLEN) +NAN_BOXED(31677,16,FLEN) +NAN_BOXED(31677,16,FLEN) +NAN_BOXED(29926,16,FLEN) +NAN_BOXED(29926,16,FLEN) +NAN_BOXED(29942,16,FLEN) +NAN_BOXED(29942,16,FLEN) +NAN_BOXED(31218,16,FLEN) +NAN_BOXED(31218,16,FLEN) +NAN_BOXED(29705,16,FLEN) +NAN_BOXED(29705,16,FLEN) +NAN_BOXED(31494,16,FLEN) +NAN_BOXED(31494,16,FLEN) +NAN_BOXED(31373,16,FLEN) +NAN_BOXED(31373,16,FLEN) +NAN_BOXED(30863,16,FLEN) +NAN_BOXED(30863,16,FLEN) +NAN_BOXED(31472,16,FLEN) +NAN_BOXED(31472,16,FLEN) +NAN_BOXED(31137,16,FLEN) +NAN_BOXED(31137,16,FLEN) +NAN_BOXED(30219,16,FLEN) +NAN_BOXED(30219,16,FLEN) +NAN_BOXED(29332,16,FLEN) +NAN_BOXED(29332,16,FLEN) +NAN_BOXED(30444,16,FLEN) +NAN_BOXED(30444,16,FLEN) +NAN_BOXED(28334,16,FLEN) +NAN_BOXED(28334,16,FLEN) +NAN_BOXED(29884,16,FLEN) +NAN_BOXED(29884,16,FLEN) +NAN_BOXED(30003,16,FLEN) +NAN_BOXED(30003,16,FLEN) +NAN_BOXED(31537,16,FLEN) +NAN_BOXED(31537,16,FLEN) +NAN_BOXED(29292,16,FLEN) +NAN_BOXED(29292,16,FLEN) +NAN_BOXED(31716,16,FLEN) +NAN_BOXED(31716,16,FLEN) +NAN_BOXED(30060,16,FLEN) +NAN_BOXED(30060,16,FLEN) +NAN_BOXED(31076,16,FLEN) +NAN_BOXED(31076,16,FLEN) +NAN_BOXED(31604,16,FLEN) +NAN_BOXED(31604,16,FLEN) +NAN_BOXED(30655,16,FLEN) +NAN_BOXED(30655,16,FLEN) +NAN_BOXED(29569,16,FLEN) +NAN_BOXED(29569,16,FLEN) +NAN_BOXED(28010,16,FLEN) +NAN_BOXED(28010,16,FLEN) +NAN_BOXED(31560,16,FLEN) +NAN_BOXED(31560,16,FLEN) +NAN_BOXED(31249,16,FLEN) +NAN_BOXED(31249,16,FLEN) +NAN_BOXED(31417,16,FLEN) +NAN_BOXED(31417,16,FLEN) +NAN_BOXED(30065,16,FLEN) +NAN_BOXED(30065,16,FLEN) +NAN_BOXED(31471,16,FLEN) +NAN_BOXED(31471,16,FLEN) +NAN_BOXED(31649,16,FLEN) +NAN_BOXED(31649,16,FLEN) +NAN_BOXED(28756,16,FLEN) +NAN_BOXED(28756,16,FLEN) +NAN_BOXED(28331,16,FLEN) +NAN_BOXED(28331,16,FLEN) +NAN_BOXED(27822,16,FLEN) +NAN_BOXED(27822,16,FLEN) +NAN_BOXED(31309,16,FLEN) +NAN_BOXED(31309,16,FLEN) +NAN_BOXED(30067,16,FLEN) +NAN_BOXED(30067,16,FLEN) +NAN_BOXED(31296,16,FLEN) +NAN_BOXED(31296,16,FLEN) +NAN_BOXED(30864,16,FLEN) +NAN_BOXED(30864,16,FLEN) +NAN_BOXED(27962,16,FLEN) +NAN_BOXED(27962,16,FLEN) +NAN_BOXED(31519,16,FLEN) +NAN_BOXED(31519,16,FLEN) +NAN_BOXED(31589,16,FLEN) +NAN_BOXED(31589,16,FLEN) +NAN_BOXED(29806,16,FLEN) +NAN_BOXED(29806,16,FLEN) +NAN_BOXED(31390,16,FLEN) +NAN_BOXED(31390,16,FLEN) +NAN_BOXED(31068,16,FLEN) +NAN_BOXED(31068,16,FLEN) +NAN_BOXED(28508,16,FLEN) +NAN_BOXED(28508,16,FLEN) +NAN_BOXED(26910,16,FLEN) +NAN_BOXED(26910,16,FLEN) +NAN_BOXED(31718,16,FLEN) +NAN_BOXED(31718,16,FLEN) +NAN_BOXED(28516,16,FLEN) +NAN_BOXED(28516,16,FLEN) +NAN_BOXED(29624,16,FLEN) +NAN_BOXED(29624,16,FLEN) +NAN_BOXED(28308,16,FLEN) +NAN_BOXED(28308,16,FLEN) +NAN_BOXED(30220,16,FLEN) +NAN_BOXED(30220,16,FLEN) +NAN_BOXED(31557,16,FLEN) +NAN_BOXED(31557,16,FLEN) +NAN_BOXED(29709,16,FLEN) +NAN_BOXED(29709,16,FLEN) +NAN_BOXED(28263,16,FLEN) +NAN_BOXED(28263,16,FLEN) +NAN_BOXED(26897,16,FLEN) +NAN_BOXED(26897,16,FLEN) +NAN_BOXED(31707,16,FLEN) +NAN_BOXED(31707,16,FLEN) +NAN_BOXED(30917,16,FLEN) +NAN_BOXED(30917,16,FLEN) +NAN_BOXED(29954,16,FLEN) +NAN_BOXED(29954,16,FLEN) +NAN_BOXED(31565,16,FLEN) +NAN_BOXED(31565,16,FLEN) +NAN_BOXED(31681,16,FLEN) +NAN_BOXED(31681,16,FLEN) +NAN_BOXED(29410,16,FLEN) +NAN_BOXED(29410,16,FLEN) +NAN_BOXED(31701,16,FLEN) +NAN_BOXED(31701,16,FLEN) +NAN_BOXED(31104,16,FLEN) +NAN_BOXED(31104,16,FLEN) +NAN_BOXED(29732,16,FLEN) +NAN_BOXED(29732,16,FLEN) +NAN_BOXED(29930,16,FLEN) +NAN_BOXED(29930,16,FLEN) +NAN_BOXED(27956,16,FLEN) +NAN_BOXED(27956,16,FLEN) +NAN_BOXED(31030,16,FLEN) +NAN_BOXED(31030,16,FLEN) +NAN_BOXED(31621,16,FLEN) +NAN_BOXED(31621,16,FLEN) +NAN_BOXED(29927,16,FLEN) +NAN_BOXED(29927,16,FLEN) +NAN_BOXED(29968,16,FLEN) +NAN_BOXED(29968,16,FLEN) +NAN_BOXED(31524,16,FLEN) +NAN_BOXED(31524,16,FLEN) +NAN_BOXED(30040,16,FLEN) +NAN_BOXED(30040,16,FLEN) +NAN_BOXED(30881,16,FLEN) +NAN_BOXED(30881,16,FLEN) +NAN_BOXED(29654,16,FLEN) +NAN_BOXED(29654,16,FLEN) +NAN_BOXED(29643,16,FLEN) +NAN_BOXED(29643,16,FLEN) +NAN_BOXED(30824,16,FLEN) +NAN_BOXED(30824,16,FLEN) +NAN_BOXED(27854,16,FLEN) +NAN_BOXED(27854,16,FLEN) +NAN_BOXED(29862,16,FLEN) +NAN_BOXED(29862,16,FLEN) +NAN_BOXED(30691,16,FLEN) +NAN_BOXED(30691,16,FLEN) +NAN_BOXED(28910,16,FLEN) +NAN_BOXED(28910,16,FLEN) +NAN_BOXED(31323,16,FLEN) +NAN_BOXED(31323,16,FLEN) +NAN_BOXED(31639,16,FLEN) +NAN_BOXED(31639,16,FLEN) +NAN_BOXED(31284,16,FLEN) +NAN_BOXED(31284,16,FLEN) +NAN_BOXED(31377,16,FLEN) +NAN_BOXED(31377,16,FLEN) +NAN_BOXED(28374,16,FLEN) +NAN_BOXED(28374,16,FLEN) +NAN_BOXED(31577,16,FLEN) +NAN_BOXED(31577,16,FLEN) +NAN_BOXED(31525,16,FLEN) +NAN_BOXED(31525,16,FLEN) +NAN_BOXED(31559,16,FLEN) +NAN_BOXED(31559,16,FLEN) +NAN_BOXED(29965,16,FLEN) +NAN_BOXED(29965,16,FLEN) +NAN_BOXED(31341,16,FLEN) +NAN_BOXED(31341,16,FLEN) +NAN_BOXED(31416,16,FLEN) +NAN_BOXED(31416,16,FLEN) +NAN_BOXED(31107,16,FLEN) +NAN_BOXED(31107,16,FLEN) +NAN_BOXED(30443,16,FLEN) +NAN_BOXED(30443,16,FLEN) +NAN_BOXED(31159,16,FLEN) +NAN_BOXED(31159,16,FLEN) +NAN_BOXED(29706,16,FLEN) +NAN_BOXED(29706,16,FLEN) +NAN_BOXED(31668,16,FLEN) +NAN_BOXED(31668,16,FLEN) +NAN_BOXED(30820,16,FLEN) +NAN_BOXED(30820,16,FLEN) +NAN_BOXED(31438,16,FLEN) +NAN_BOXED(31438,16,FLEN) +NAN_BOXED(30292,16,FLEN) +NAN_BOXED(30292,16,FLEN) +NAN_BOXED(29728,16,FLEN) +NAN_BOXED(29728,16,FLEN) +NAN_BOXED(31019,16,FLEN) +NAN_BOXED(31019,16,FLEN) +NAN_BOXED(30125,16,FLEN) +NAN_BOXED(30125,16,FLEN) +NAN_BOXED(28672,16,FLEN) +NAN_BOXED(28672,16,FLEN) +NAN_BOXED(31392,16,FLEN) +NAN_BOXED(31392,16,FLEN) +NAN_BOXED(30314,16,FLEN) +NAN_BOXED(30314,16,FLEN) +NAN_BOXED(29560,16,FLEN) +NAN_BOXED(29560,16,FLEN) +NAN_BOXED(30778,16,FLEN) +NAN_BOXED(30778,16,FLEN) +NAN_BOXED(31024,16,FLEN) +NAN_BOXED(31024,16,FLEN) +NAN_BOXED(31101,16,FLEN) +NAN_BOXED(31101,16,FLEN) +NAN_BOXED(29599,16,FLEN) +NAN_BOXED(29599,16,FLEN) +NAN_BOXED(30632,16,FLEN) +NAN_BOXED(30632,16,FLEN) +NAN_BOXED(30359,16,FLEN) +NAN_BOXED(30359,16,FLEN) +NAN_BOXED(28748,16,FLEN) +NAN_BOXED(28748,16,FLEN) +NAN_BOXED(28161,16,FLEN) +NAN_BOXED(28161,16,FLEN) +NAN_BOXED(29521,16,FLEN) +NAN_BOXED(29521,16,FLEN) +NAN_BOXED(30730,16,FLEN) +NAN_BOXED(30730,16,FLEN) +NAN_BOXED(31328,16,FLEN) +NAN_BOXED(31328,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x10_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x10_1: + .fill 36*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x4_0: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x4_1: + .fill 112*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fsub_b2-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fsub_b2-01.S new file mode 100644 index 000000000..691352894 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fsub_b2-01.S @@ -0,0 +1,1229 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 06:02:02 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fsub.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fsub.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fsub_b2 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fsub_b2) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x5,test_dataset_0) +RVTEST_SIGBASE(x12,signature_x12_1) + +inst_0: +// rs1 == rs2 == rd, rs1==x17, rs2==x17, rd==x17,fs1 == 0 and fe1 == 0x00 and fm1 == 0x012 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x010 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x17; op2:x17; dest:x17; op1val:0x12; op2val:0x12; + valaddr_reg:x5; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x13*/ +TEST_FPRR_OP(fsub.h, x17, x17, x17, dyn, 0, 0, x5, 0*FLEN/8, x21, x12, x13) + +inst_1: +// rs2 == rd != rs1, rs1==x15, rs2==x29, rd==x29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x062 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x060 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x15; op2:x29; dest:x29; op1val:0x62; op2val:0x60; + valaddr_reg:x5; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x13*/ +TEST_FPRR_OP(fsub.h, x29, x15, x29, dyn, 0, 0, x5, 2*FLEN/8, x21, x12, x13) + +inst_2: +// rs1 == rd != rs2, rs1==x25, rs2==x7, rd==x25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x021 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x01d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x25; op2:x7; dest:x25; op1val:0x21; op2val:0x1d; + valaddr_reg:x5; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x13*/ +TEST_FPRR_OP(fsub.h, x25, x25, x7, dyn, 0, 0, x5, 4*FLEN/8, x21, x12, x13) + +inst_3: +// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==x9, rs2==x27, rd==x6,fs1 == 0 and fe1 == 0x00 and fm1 == 0x040 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x038 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x9; op2:x27; dest:x6; op1val:0x40; op2val:0x38; + valaddr_reg:x5; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x13*/ +TEST_FPRR_OP(fsub.h, x6, x9, x27, dyn, 0, 0, x5, 6*FLEN/8, x21, x12, x13) + +inst_4: +// rs1 == rs2 != rd, rs1==x30, rs2==x30, rd==x20,fs1 == 0 and fe1 == 0x00 and fm1 == 0x03a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x02a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x30; dest:x20; op1val:0x3a; op2val:0x3a; + valaddr_reg:x5; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x13*/ +TEST_FPRR_OP(fsub.h, x20, x30, x30, dyn, 0, 0, x5, 8*FLEN/8, x21, x12, x13) + +inst_5: +// rs1==x14, rs2==x20, rd==x27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x054 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x034 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x14; op2:x20; dest:x27; op1val:0x54; op2val:0x34; + valaddr_reg:x5; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x13*/ +TEST_FPRR_OP(fsub.h, x27, x14, x20, dyn, 0, 0, x5, 10*FLEN/8, x21, x12, x13) + +inst_6: +// rs1==x29, rs2==x1, rd==x2,fs1 == 0 and fe1 == 0x00 and fm1 == 0x01b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x025 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x29; op2:x1; dest:x2; op1val:0x1b; op2val:0x8025; + valaddr_reg:x5; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x13*/ +TEST_FPRR_OP(fsub.h, x2, x29, x1, dyn, 0, 0, x5, 12*FLEN/8, x21, x12, x13) + +inst_7: +// rs1==x0, rs2==x16, rd==x30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x041 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x0; op2:x16; dest:x30; op1val:0x0; op2val:0x8041; + valaddr_reg:x5; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x13*/ +TEST_FPRR_OP(fsub.h, x30, x0, x16, dyn, 0, 0, x5, 14*FLEN/8, x21, x12, x13) + +inst_8: +// rs1==x2, rs2==x10, rd==x18,fs1 == 0 and fe1 == 0x00 and fm1 == 0x032 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0ce and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x2; op2:x10; dest:x18; op1val:0x32; op2val:0x80ce; + valaddr_reg:x5; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x13*/ +TEST_FPRR_OP(fsub.h, x18, x2, x10, dyn, 0, 0, x5, 16*FLEN/8, x21, x12, x13) + +inst_9: +// rs1==x8, rs2==x28, rd==x26,fs1 == 0 and fe1 == 0x00 and fm1 == 0x04e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1b2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x8; op2:x28; dest:x26; op1val:0x4e; op2val:0x81b2; + valaddr_reg:x5; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x13*/ +TEST_FPRR_OP(fsub.h, x26, x8, x28, dyn, 0, 0, x5, 18*FLEN/8, x21, x12, x13) + +inst_10: +// rs1==x19, rs2==x23, rd==x4,fs1 == 0 and fe1 == 0x00 and fm1 == 0x063 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x064 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x19; op2:x23; dest:x4; op1val:0x63; op2val:0x64; + valaddr_reg:x5; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x13*/ +TEST_FPRR_OP(fsub.h, x4, x19, x23, dyn, 0, 0, x5, 20*FLEN/8, x21, x12, x13) + +inst_11: +// rs1==x10, rs2==x15, rd==x16,fs1 == 0 and fe1 == 0x00 and fm1 == 0x05a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x05c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x10; op2:x15; dest:x16; op1val:0x5a; op2val:0x5c; + valaddr_reg:x5; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x13*/ +TEST_FPRR_OP(fsub.h, x16, x10, x15, dyn, 0, 0, x5, 22*FLEN/8, x21, x12, x13) + +inst_12: +// rs1==x11, rs2==x3, rd==x9,fs1 == 0 and fe1 == 0x00 and fm1 == 0x023 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x027 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x11; op2:x3; dest:x9; op1val:0x23; op2val:0x27; + valaddr_reg:x5; val_offset:24*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x13*/ +TEST_FPRR_OP(fsub.h, x9, x11, x3, dyn, 0, 0, x5, 24*FLEN/8, x21, x12, x13) +RVTEST_VALBASEUPD(x2,test_dataset_1) + +inst_13: +// rs1==x21, rs2==x4, rd==x5,fs1 == 0 and fe1 == 0x00 and fm1 == 0x01e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x026 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x21; op2:x4; dest:x5; op1val:0x1e; op2val:0x26; + valaddr_reg:x2; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x13*/ +TEST_FPRR_OP(fsub.h, x5, x21, x4, dyn, 0, 0, x2, 0*FLEN/8, x7, x12, x13) +RVTEST_SIGBASE(x17,signature_x17_0) + +inst_14: +// rs1==x22, rs2==x25, rd==x24,fs1 == 0 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x01e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x22; op2:x25; dest:x24; op1val:0xe; op2val:0x1e; + valaddr_reg:x2; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x20*/ +TEST_FPRR_OP(fsub.h, x24, x22, x25, dyn, 0, 0, x2, 2*FLEN/8, x7, x17, x20) + +inst_15: +// rs1==x3, rs2==x0, rd==x13,fs1 == 0 and fe1 == 0x00 and fm1 == 0x004 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x024 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x3; op2:x0; dest:x13; op1val:0x4; op2val:0x0; + valaddr_reg:x2; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x20*/ +TEST_FPRR_OP(fsub.h, x13, x3, x0, dyn, 0, 0, x2, 4*FLEN/8, x7, x17, x20) + +inst_16: +// rs1==x5, rs2==x21, rd==x0,fs1 == 0 and fe1 == 0x00 and fm1 == 0x004 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x044 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x5; op2:x21; dest:x0; op1val:0x4; op2val:0x44; + valaddr_reg:x2; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x20*/ +TEST_FPRR_OP(fsub.h, x0, x5, x21, dyn, 0, 0, x2, 6*FLEN/8, x7, x17, x20) + +inst_17: +// rs1==x4, rs2==x11, rd==x19,fs1 == 0 and fe1 == 0x00 and fm1 == 0x046 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0c6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x4; op2:x11; dest:x19; op1val:0x46; op2val:0xc6; + valaddr_reg:x2; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x20*/ +TEST_FPRR_OP(fsub.h, x19, x4, x11, dyn, 0, 0, x2, 8*FLEN/8, x7, x17, x20) + +inst_18: +// rs1==x18, rs2==x19, rd==x21,fs1 == 0 and fe1 == 0x00 and fm1 == 0x031 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x131 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x18; op2:x19; dest:x21; op1val:0x31; op2val:0x131; + valaddr_reg:x2; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x20*/ +TEST_FPRR_OP(fsub.h, x21, x18, x19, dyn, 0, 0, x2, 10*FLEN/8, x7, x17, x20) + +inst_19: +// rs1==x12, rs2==x9, rd==x28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x01c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x21c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x12; op2:x9; dest:x28; op1val:0x1c; op2val:0x21c; + valaddr_reg:x2; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x20*/ +TEST_FPRR_OP(fsub.h, x28, x12, x9, dyn, 0, 0, x2, 12*FLEN/8, x7, x17, x20) + +inst_20: +// rs1==x27, rs2==x24, rd==x11,fs1 == 0 and fe1 == 0x0f and fm1 == 0x05d and fs2 == 0 and fe2 == 0x0b and fm2 == 0x1c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x27; op2:x24; dest:x11; op1val:0x3c5d; op2val:0x2dc0; + valaddr_reg:x2; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x20*/ +TEST_FPRR_OP(fsub.h, x11, x27, x24, dyn, 0, 0, x2, 14*FLEN/8, x7, x17, x20) + +inst_21: +// rs1==x13, rs2==x14, rd==x22,fs1 == 0 and fe1 == 0x0f and fm1 == 0x044 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x020 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x13; op2:x14; dest:x22; op1val:0x3c44; op2val:0x2c20; + valaddr_reg:x2; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x20*/ +TEST_FPRR_OP(fsub.h, x22, x13, x14, dyn, 0, 0, x2, 16*FLEN/8, x7, x17, x20) + +inst_22: +// rs1==x28, rs2==x18, rd==x3,fs1 == 0 and fe1 == 0x0f and fm1 == 0x062 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x1e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x28; op2:x18; dest:x3; op1val:0x3c62; op2val:0x2de0; + valaddr_reg:x2; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x20*/ +TEST_FPRR_OP(fsub.h, x3, x28, x18, dyn, 0, 0, x2, 18*FLEN/8, x7, x17, x20) + +inst_23: +// rs1==x16, rs2==x5, rd==x10,fs1 == 0 and fe1 == 0x0f and fm1 == 0x040 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x16; op2:x5; dest:x10; op1val:0x3c40; op2val:0x2b00; + valaddr_reg:x2; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x20*/ +TEST_FPRR_OP(fsub.h, x10, x16, x5, dyn, 0, 0, x2, 20*FLEN/8, x7, x17, x20) + +inst_24: +// rs1==x6, rs2==x22, rd==x23,fs1 == 0 and fe1 == 0x0f and fm1 == 0x01e and fs2 == 0 and fe2 == 0x08 and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x6; op2:x22; dest:x23; op1val:0x3c1e; op2val:0x2300; + valaddr_reg:x2; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x20*/ +TEST_FPRR_OP(fsub.h, x23, x6, x22, dyn, 0, 0, x2, 22*FLEN/8, x7, x17, x20) + +inst_25: +// rs1==x1, rs2==x31, rd==x15,fs1 == 0 and fe1 == 0x0f and fm1 == 0x01e and fs2 == 1 and fe2 == 0x06 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x1; op2:x31; dest:x15; op1val:0x3c1e; op2val:0x9800; + valaddr_reg:x2; val_offset:24*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x20*/ +TEST_FPRR_OP(fsub.h, x15, x1, x31, dyn, 0, 0, x2, 24*FLEN/8, x7, x17, x20) +RVTEST_VALBASEUPD(x4,test_dataset_2) + +inst_26: +// rs1==x23, rs2==x6, rd==x7,fs1 == 0 and fe1 == 0x0f and fm1 == 0x01d and fs2 == 1 and fe2 == 0x0a and fm2 == 0x060 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x23; op2:x6; dest:x7; op1val:0x3c1d; op2val:0xa860; + valaddr_reg:x4; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x20*/ +TEST_FPRR_OP(fsub.h, x7, x23, x6, dyn, 0, 0, x4, 0*FLEN/8, x5, x17, x20) + +inst_27: +// rs1==x24, rs2==x12, rd==x31,fs1 == 0 and fe1 == 0x0f and fm1 == 0x03b and fs2 == 1 and fe2 == 0x0b and fm2 == 0x050 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x24; op2:x12; dest:x31; op1val:0x3c3b; op2val:0xac50; + valaddr_reg:x4; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x20*/ +TEST_FPRR_OP(fsub.h, x31, x24, x12, dyn, 0, 0, x4, 2*FLEN/8, x5, x17, x20) + +inst_28: +// rs1==x7, rs2==x2, rd==x8,fs1 == 0 and fe1 == 0x0f and fm1 == 0x003 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3e8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x7; op2:x2; dest:x8; op1val:0x3c03; op2val:0xb3e8; + valaddr_reg:x4; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x20*/ +TEST_FPRR_OP(fsub.h, x8, x7, x2, dyn, 0, 0, x4, 4*FLEN/8, x5, x17, x20) +RVTEST_SIGBASE(x2,signature_x2_0) + +inst_29: +// rs1==x20, rs2==x8, rd==x12,fs1 == 0 and fe1 == 0x0f and fm1 == 0x048 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x20; op2:x8; dest:x12; op1val:0x3c48; op2val:0xb6e0; + valaddr_reg:x4; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x12, x20, x8, dyn, 0, 0, x4, 6*FLEN/8, x5, x2, x3) + +inst_30: +// rs1==x26, rs2==x13, rd==x14,fs1 == 0 and fe1 == 0x0f and fm1 == 0x00d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x007 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x26; op2:x13; dest:x14; op1val:0x3c0d; op2val:0x4007; + valaddr_reg:x4; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x14, x26, x13, dyn, 0, 0, x4, 8*FLEN/8, x5, x2, x3) + +inst_31: +// rs1==x31, rs2==x26, rd==x1,fs1 == 0 and fe1 == 0x0f and fm1 == 0x051 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x029 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x31; op2:x26; dest:x1; op1val:0x3c51; op2val:0x4029; + valaddr_reg:x4; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x1, x31, x26, dyn, 0, 0, x4, 10*FLEN/8, x5, x2, x3) + +inst_32: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x026 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x015 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c26; op2val:0x4015; + valaddr_reg:x4; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 12*FLEN/8, x5, x2, x3) + +inst_33: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x060 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x034 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c60; op2val:0x4034; + valaddr_reg:x4; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 14*FLEN/8, x5, x2, x3) + +inst_34: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x05d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x036 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c5d; op2val:0x4036; + valaddr_reg:x4; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 16*FLEN/8, x5, x2, x3) + +inst_35: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x041 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x030 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c41; op2val:0x4030; + valaddr_reg:x4; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 18*FLEN/8, x5, x2, x3) + +inst_36: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x041 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x040 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c41; op2val:0x4040; + valaddr_reg:x4; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 20*FLEN/8, x5, x2, x3) + +inst_37: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x019 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x04c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c19; op2val:0x404c; + valaddr_reg:x4; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 22*FLEN/8, x5, x2, x3) + +inst_38: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x025 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x092 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c25; op2val:0x4092; + valaddr_reg:x4; val_offset:24*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 24*FLEN/8, x5, x2, x3) + +inst_39: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x040 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x120 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c40; op2val:0x4120; + valaddr_reg:x4; val_offset:26*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 26*FLEN/8, x5, x2, x3) + +inst_40: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x033 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x031 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x33; op2val:0x31; + valaddr_reg:x4; val_offset:28*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 28*FLEN/8, x5, x2, x3) + +inst_41: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x005 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5; op2val:0x2; + valaddr_reg:x4; val_offset:30*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 30*FLEN/8, x5, x2, x3) + +inst_42: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x020 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x01b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x20; op2val:0x1b; + valaddr_reg:x4; val_offset:32*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 32*FLEN/8, x5, x2, x3) + +inst_43: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x034 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x02b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x34; op2val:0x2b; + valaddr_reg:x4; val_offset:34*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 34*FLEN/8, x5, x2, x3) + +inst_44: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x056 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x045 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x56; op2val:0x45; + valaddr_reg:x4; val_offset:36*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 36*FLEN/8, x5, x2, x3) + +inst_45: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x02f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2f; op2val:0xe; + valaddr_reg:x4; val_offset:38*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 38*FLEN/8, x5, x2, x3) + +inst_46: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x05a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x019 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5a; op2val:0x19; + valaddr_reg:x4; val_offset:40*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 40*FLEN/8, x5, x2, x3) + +inst_47: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x05f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x022 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5f; op2val:0x8022; + valaddr_reg:x4; val_offset:42*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 42*FLEN/8, x5, x2, x3) + +inst_48: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0f5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xc; op2val:0x80f5; + valaddr_reg:x4; val_offset:44*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 44*FLEN/8, x5, x2, x3) + +inst_49: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1ac and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x55; op2val:0x81ac; + valaddr_reg:x4; val_offset:46*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 46*FLEN/8, x5, x2, x3) + +inst_50: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0xe; op2val:0xf; + valaddr_reg:x4; val_offset:48*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 48*FLEN/8, x5, x2, x3) + +inst_51: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x043 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x046 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x43; op2val:0x46; + valaddr_reg:x4; val_offset:50*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 50*FLEN/8, x5, x2, x3) + +inst_52: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x030 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x035 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x30; op2val:0x35; + valaddr_reg:x4; val_offset:52*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 52*FLEN/8, x5, x2, x3) + +inst_53: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x05e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x067 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5e; op2val:0x67; + valaddr_reg:x4; val_offset:54*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 54*FLEN/8, x5, x2, x3) + +inst_54: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x04e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3d; op2val:0x4e; + valaddr_reg:x4; val_offset:56*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 56*FLEN/8, x5, x2, x3) + +inst_55: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x028 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x049 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x28; op2val:0x49; + valaddr_reg:x4; val_offset:58*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 58*FLEN/8, x5, x2, x3) + +inst_56: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x04f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x090 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4f; op2val:0x90; + valaddr_reg:x4; val_offset:60*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 60*FLEN/8, x5, x2, x3) + +inst_57: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x04b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0cc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4b; op2val:0xcc; + valaddr_reg:x4; val_offset:62*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 62*FLEN/8, x5, x2, x3) + +inst_58: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x053 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x154 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x53; op2val:0x154; + valaddr_reg:x4; val_offset:64*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 64*FLEN/8, x5, x2, x3) + +inst_59: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x016 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x16; op2val:0x217; + valaddr_reg:x4; val_offset:66*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 66*FLEN/8, x5, x2, x3) + +inst_60: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x01e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1e; op2val:0x83e0; + valaddr_reg:x4; val_offset:68*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 68*FLEN/8, x5, x2, x3) + +inst_61: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x063 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x39a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x63; op2val:0x839a; + valaddr_reg:x4; val_offset:70*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 70*FLEN/8, x5, x2, x3) + +inst_62: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x046 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3b5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x46; op2val:0x83b5; + valaddr_reg:x4; val_offset:72*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 72*FLEN/8, x5, x2, x3) + +inst_63: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x01e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3d9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1e; op2val:0x83d9; + valaddr_reg:x4; val_offset:74*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 74*FLEN/8, x5, x2, x3) + +inst_64: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x042 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ad and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x42; op2val:0x83ad; + valaddr_reg:x4; val_offset:76*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 76*FLEN/8, x5, x2, x3) + +inst_65: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x04a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x395 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4a; op2val:0x8395; + valaddr_reg:x4; val_offset:78*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 78*FLEN/8, x5, x2, x3) + +inst_66: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x384 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b; op2val:0x8384; + valaddr_reg:x4; val_offset:80*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 80*FLEN/8, x5, x2, x3) + +inst_67: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x32a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x55; op2val:0x832a; + valaddr_reg:x4; val_offset:82*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 82*FLEN/8, x5, x2, x3) + +inst_68: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x04e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2b1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4e; op2val:0x82b1; + valaddr_reg:x4; val_offset:84*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 84*FLEN/8, x5, x2, x3) + +inst_69: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1; op2val:0x81fd; + valaddr_reg:x4; val_offset:86*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 86*FLEN/8, x5, x2, x3) + +inst_70: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x05f and fs2 == 0 and fe2 == 0x01 and fm2 == 0x05d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5f; op2val:0x45d; + valaddr_reg:x4; val_offset:88*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 88*FLEN/8, x5, x2, x3) + +inst_71: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x011 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x11; op2val:0x40e; + valaddr_reg:x4; val_offset:90*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 90*FLEN/8, x5, x2, x3) + +inst_72: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x048 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x043 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x48; op2val:0x443; + valaddr_reg:x4; val_offset:92*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 92*FLEN/8, x5, x2, x3) + +inst_73: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x02e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x37; op2val:0x42e; + valaddr_reg:x4; val_offset:94*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 94*FLEN/8, x5, x2, x3) + +inst_74: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03e and fs2 == 0 and fe2 == 0x01 and fm2 == 0x02d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3e; op2val:0x42d; + valaddr_reg:x4; val_offset:96*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 96*FLEN/8, x5, x2, x3) + +inst_75: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x049 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x028 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x49; op2val:0x428; + valaddr_reg:x4; val_offset:98*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 98*FLEN/8, x5, x2, x3) + +inst_76: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x01a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3d9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1a; op2val:0x3d9; + valaddr_reg:x4; val_offset:100*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 100*FLEN/8, x5, x2, x3) + +inst_77: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x035 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3b4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x35; op2val:0x3b4; + valaddr_reg:x4; val_offset:102*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 102*FLEN/8, x5, x2, x3) + +inst_78: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x02e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x32d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e; op2val:0x32d; + valaddr_reg:x4; val_offset:104*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 104*FLEN/8, x5, x2, x3) + +inst_79: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x02d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x22c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d; op2val:0x22c; + valaddr_reg:x4; val_offset:106*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 106*FLEN/8, x5, x2, x3) + +inst_80: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x045 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x044 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x445; op2val:0x44; + valaddr_reg:x4; val_offset:108*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 108*FLEN/8, x5, x2, x3) + +inst_81: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x050 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x04e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x450; op2val:0x4e; + valaddr_reg:x4; val_offset:110*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 110*FLEN/8, x5, x2, x3) + +inst_82: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x02b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x027 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x42b; op2val:0x27; + valaddr_reg:x4; val_offset:112*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 112*FLEN/8, x5, x2, x3) + +inst_83: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x04d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x045 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x44d; op2val:0x45; + valaddr_reg:x4; val_offset:114*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 114*FLEN/8, x5, x2, x3) + +inst_84: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x01e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x41e; op2val:0xe; + valaddr_reg:x4; val_offset:116*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 116*FLEN/8, x5, x2, x3) + +inst_85: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x017 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x009 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x417; op2val:0x8009; + valaddr_reg:x4; val_offset:118*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 118*FLEN/8, x5, x2, x3) + +inst_86: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x04b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x44b; op2val:0xb; + valaddr_reg:x4; val_offset:120*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 120*FLEN/8, x5, x2, x3) + +inst_87: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x00c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x074 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x40c; op2val:0x8074; + valaddr_reg:x4; val_offset:122*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 122*FLEN/8, x5, x2, x3) + +inst_88: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x021 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0df and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x421; op2val:0x80df; + valaddr_reg:x4; val_offset:124*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 124*FLEN/8, x5, x2, x3) + +inst_89: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x057 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1a9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x457; op2val:0x81a9; + valaddr_reg:x4; val_offset:126*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 126*FLEN/8, x5, x2, x3) + +inst_90: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x00b and fs2 == 0 and fe2 == 0x02 and fm2 == 0x006 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x40b; op2val:0x806; + valaddr_reg:x4; val_offset:128*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 128*FLEN/8, x5, x2, x3) + +inst_91: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x03a and fs2 == 0 and fe2 == 0x02 and fm2 == 0x01e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x43a; op2val:0x81e; + valaddr_reg:x4; val_offset:130*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 130*FLEN/8, x5, x2, x3) + +inst_92: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x061 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x032 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x461; op2val:0x832; + valaddr_reg:x4; val_offset:132*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 132*FLEN/8, x5, x2, x3) + +inst_93: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x024 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x016 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x424; op2val:0x816; + valaddr_reg:x4; val_offset:134*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 134*FLEN/8, x5, x2, x3) + +inst_94: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x023 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x019 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x423; op2val:0x819; + valaddr_reg:x4; val_offset:136*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 136*FLEN/8, x5, x2, x3) + +inst_95: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x050 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x038 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x450; op2val:0x838; + valaddr_reg:x4; val_offset:138*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 138*FLEN/8, x5, x2, x3) + +inst_96: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x02d and fs2 == 0 and fe2 == 0x02 and fm2 == 0x036 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x42d; op2val:0x836; + valaddr_reg:x4; val_offset:140*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 140*FLEN/8, x5, x2, x3) + +inst_97: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x009 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x044 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x409; op2val:0x844; + valaddr_reg:x4; val_offset:142*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 142*FLEN/8, x5, x2, x3) + +inst_98: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x015 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x08a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x415; op2val:0x88a; + valaddr_reg:x4; val_offset:144*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 144*FLEN/8, x5, x2, x3) + +inst_99: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x044 and fs2 == 0 and fe2 == 0x02 and fm2 == 0x122 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x444; op2val:0x922; + valaddr_reg:x4; val_offset:146*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 146*FLEN/8, x5, x2, x3) + +inst_100: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x055 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x352 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7855; op2val:0xf752; + valaddr_reg:x4; val_offset:148*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 148*FLEN/8, x5, x2, x3) + +inst_101: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x053 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x354 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7853; op2val:0xf754; + valaddr_reg:x4; val_offset:150*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 150*FLEN/8, x5, x2, x3) + +inst_102: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x026 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7826; op2val:0xf7aa; + valaddr_reg:x4; val_offset:152*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 152*FLEN/8, x5, x2, x3) + +inst_103: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x05a and fs2 == 1 and fe2 == 0x1d and fm2 == 0x33a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x785a; op2val:0xf73a; + valaddr_reg:x4; val_offset:154*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 154*FLEN/8, x5, x2, x3) + +inst_104: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x040 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x35e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7840; op2val:0xf75e; + valaddr_reg:x4; val_offset:156*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 156*FLEN/8, x5, x2, x3) + +inst_105: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00f and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3a0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x780f; op2val:0xf7a0; + valaddr_reg:x4; val_offset:158*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 158*FLEN/8, x5, x2, x3) + +inst_106: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x028 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x32e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7828; op2val:0xf72e; + valaddr_reg:x4; val_offset:160*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 160*FLEN/8, x5, x2, x3) + +inst_107: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02c and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2a6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x782c; op2val:0xf6a6; + valaddr_reg:x4; val_offset:162*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 162*FLEN/8, x5, x2, x3) + +inst_108: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x019 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x1cc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7819; op2val:0xf5cc; + valaddr_reg:x4; val_offset:164*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 164*FLEN/8, x5, x2, x3) + +inst_109: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00e and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3c4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x780e; op2val:0xf3c4; + valaddr_reg:x4; val_offset:166*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 166*FLEN/8, x5, x2, x3) + +inst_110: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x05e and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x785e; op2val:0x7c00; + valaddr_reg:x4; val_offset:168*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 168*FLEN/8, x5, x2, x3) + +inst_111: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x01b and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x781b; op2val:0x7c00; + valaddr_reg:x4; val_offset:170*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 170*FLEN/8, x5, x2, x3) + +inst_112: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x038 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7838; op2val:0x7c00; + valaddr_reg:x4; val_offset:172*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 172*FLEN/8, x5, x2, x3) + +inst_113: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x01d and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x781d; op2val:0x7c00; + valaddr_reg:x4; val_offset:174*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 174*FLEN/8, x5, x2, x3) + +inst_114: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x033 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7833; op2val:0x7c00; + valaddr_reg:x4; val_offset:176*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 176*FLEN/8, x5, x2, x3) + +inst_115: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x005 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7805; op2val:0x7c00; + valaddr_reg:x4; val_offset:178*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 178*FLEN/8, x5, x2, x3) + +inst_116: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x015 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7815; op2val:0x7c00; + valaddr_reg:x4; val_offset:180*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 180*FLEN/8, x5, x2, x3) + +inst_117: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x05b and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x785b; op2val:0x7c00; + valaddr_reg:x4; val_offset:182*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 182*FLEN/8, x5, x2, x3) + +inst_118: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x057 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7857; op2val:0x7c00; + valaddr_reg:x4; val_offset:184*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 184*FLEN/8, x5, x2, x3) + +inst_119: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x046 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7846; op2val:0x7c00; + valaddr_reg:x4; val_offset:186*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 186*FLEN/8, x5, x2, x3) + +inst_120: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x012 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x010 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x12; op2val:0x10; + valaddr_reg:x4; val_offset:188*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 188*FLEN/8, x5, x2, x3) + +inst_121: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x02a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a; op2val:0x2a; + valaddr_reg:x4; val_offset:190*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 190*FLEN/8, x5, x2, x3) + +inst_122: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x041 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3f; op2val:0x8041; + valaddr_reg:x4; val_offset:192*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 192*FLEN/8, x5, x2, x3) + +inst_123: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x004 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x024 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4; op2val:0x24; + valaddr_reg:x4; val_offset:194*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 194*FLEN/8, x5, x2, x3) + +inst_124: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x004 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x044 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4; op2val:0x44; + valaddr_reg:x4; val_offset:196*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x3*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 196*FLEN/8, x5, x2, x3) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(18,32,FLEN) +NAN_BOXED(18,32,FLEN) +NAN_BOXED(98,32,FLEN) +NAN_BOXED(96,32,FLEN) +NAN_BOXED(33,32,FLEN) +NAN_BOXED(29,32,FLEN) +NAN_BOXED(64,32,FLEN) +NAN_BOXED(56,32,FLEN) +NAN_BOXED(58,32,FLEN) +NAN_BOXED(58,32,FLEN) +NAN_BOXED(84,32,FLEN) +NAN_BOXED(52,32,FLEN) +NAN_BOXED(27,32,FLEN) +NAN_BOXED(32805,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32833,16,FLEN) +NAN_BOXED(50,32,FLEN) +NAN_BOXED(32974,16,FLEN) +NAN_BOXED(78,32,FLEN) +NAN_BOXED(33202,16,FLEN) +NAN_BOXED(99,32,FLEN) +NAN_BOXED(100,32,FLEN) +NAN_BOXED(90,32,FLEN) +NAN_BOXED(92,32,FLEN) +NAN_BOXED(35,32,FLEN) +NAN_BOXED(39,32,FLEN) +test_dataset_1: +NAN_BOXED(30,32,FLEN) +NAN_BOXED(38,32,FLEN) +NAN_BOXED(14,32,FLEN) +NAN_BOXED(30,32,FLEN) +NAN_BOXED(4,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(4,32,FLEN) +NAN_BOXED(68,32,FLEN) +NAN_BOXED(70,32,FLEN) +NAN_BOXED(198,32,FLEN) +NAN_BOXED(49,32,FLEN) +NAN_BOXED(305,32,FLEN) +NAN_BOXED(28,32,FLEN) +NAN_BOXED(540,32,FLEN) +NAN_BOXED(15453,32,FLEN) +NAN_BOXED(11712,32,FLEN) +NAN_BOXED(15428,32,FLEN) +NAN_BOXED(11296,32,FLEN) +NAN_BOXED(15458,32,FLEN) +NAN_BOXED(11744,32,FLEN) +NAN_BOXED(15424,32,FLEN) +NAN_BOXED(11008,32,FLEN) +NAN_BOXED(15390,32,FLEN) +NAN_BOXED(8960,32,FLEN) +NAN_BOXED(15390,32,FLEN) +NAN_BOXED(38912,16,FLEN) +test_dataset_2: +NAN_BOXED(15389,16,FLEN) +NAN_BOXED(43104,16,FLEN) +NAN_BOXED(15419,16,FLEN) +NAN_BOXED(44112,16,FLEN) +NAN_BOXED(15363,16,FLEN) +NAN_BOXED(46056,16,FLEN) +NAN_BOXED(15432,16,FLEN) +NAN_BOXED(46816,16,FLEN) +NAN_BOXED(15373,16,FLEN) +NAN_BOXED(16391,16,FLEN) +NAN_BOXED(15441,16,FLEN) +NAN_BOXED(16425,16,FLEN) +NAN_BOXED(15398,16,FLEN) +NAN_BOXED(16405,16,FLEN) +NAN_BOXED(15456,16,FLEN) +NAN_BOXED(16436,16,FLEN) +NAN_BOXED(15453,16,FLEN) +NAN_BOXED(16438,16,FLEN) +NAN_BOXED(15425,16,FLEN) +NAN_BOXED(16432,16,FLEN) +NAN_BOXED(15425,16,FLEN) +NAN_BOXED(16448,16,FLEN) +NAN_BOXED(15385,16,FLEN) +NAN_BOXED(16460,16,FLEN) +NAN_BOXED(15397,16,FLEN) +NAN_BOXED(16530,16,FLEN) +NAN_BOXED(15424,16,FLEN) +NAN_BOXED(16672,16,FLEN) +NAN_BOXED(51,16,FLEN) +NAN_BOXED(49,16,FLEN) +NAN_BOXED(5,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(32,16,FLEN) +NAN_BOXED(27,16,FLEN) +NAN_BOXED(52,16,FLEN) +NAN_BOXED(43,16,FLEN) +NAN_BOXED(86,16,FLEN) +NAN_BOXED(69,16,FLEN) +NAN_BOXED(47,16,FLEN) +NAN_BOXED(14,16,FLEN) +NAN_BOXED(90,16,FLEN) +NAN_BOXED(25,16,FLEN) +NAN_BOXED(95,16,FLEN) +NAN_BOXED(32802,16,FLEN) +NAN_BOXED(12,16,FLEN) +NAN_BOXED(33013,16,FLEN) +NAN_BOXED(85,16,FLEN) +NAN_BOXED(33196,16,FLEN) +NAN_BOXED(14,16,FLEN) +NAN_BOXED(15,16,FLEN) +NAN_BOXED(67,16,FLEN) +NAN_BOXED(70,16,FLEN) +NAN_BOXED(48,16,FLEN) +NAN_BOXED(53,16,FLEN) +NAN_BOXED(94,16,FLEN) +NAN_BOXED(103,16,FLEN) +NAN_BOXED(61,16,FLEN) +NAN_BOXED(78,16,FLEN) +NAN_BOXED(40,16,FLEN) +NAN_BOXED(73,16,FLEN) +NAN_BOXED(79,16,FLEN) +NAN_BOXED(144,16,FLEN) +NAN_BOXED(75,16,FLEN) +NAN_BOXED(204,16,FLEN) +NAN_BOXED(83,16,FLEN) +NAN_BOXED(340,16,FLEN) +NAN_BOXED(22,16,FLEN) +NAN_BOXED(535,16,FLEN) +NAN_BOXED(30,16,FLEN) +NAN_BOXED(33760,16,FLEN) +NAN_BOXED(99,16,FLEN) +NAN_BOXED(33690,16,FLEN) +NAN_BOXED(70,16,FLEN) +NAN_BOXED(33717,16,FLEN) +NAN_BOXED(30,16,FLEN) +NAN_BOXED(33753,16,FLEN) +NAN_BOXED(66,16,FLEN) +NAN_BOXED(33709,16,FLEN) +NAN_BOXED(74,16,FLEN) +NAN_BOXED(33685,16,FLEN) +NAN_BOXED(59,16,FLEN) +NAN_BOXED(33668,16,FLEN) +NAN_BOXED(85,16,FLEN) +NAN_BOXED(33578,16,FLEN) +NAN_BOXED(78,16,FLEN) +NAN_BOXED(33457,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(33277,16,FLEN) +NAN_BOXED(95,16,FLEN) +NAN_BOXED(1117,16,FLEN) +NAN_BOXED(17,16,FLEN) +NAN_BOXED(1038,16,FLEN) +NAN_BOXED(72,16,FLEN) +NAN_BOXED(1091,16,FLEN) +NAN_BOXED(55,16,FLEN) +NAN_BOXED(1070,16,FLEN) +NAN_BOXED(62,16,FLEN) +NAN_BOXED(1069,16,FLEN) +NAN_BOXED(73,16,FLEN) +NAN_BOXED(1064,16,FLEN) +NAN_BOXED(26,16,FLEN) +NAN_BOXED(985,16,FLEN) +NAN_BOXED(53,16,FLEN) +NAN_BOXED(948,16,FLEN) +NAN_BOXED(46,16,FLEN) +NAN_BOXED(813,16,FLEN) +NAN_BOXED(45,16,FLEN) +NAN_BOXED(556,16,FLEN) +NAN_BOXED(1093,16,FLEN) +NAN_BOXED(68,16,FLEN) +NAN_BOXED(1104,16,FLEN) +NAN_BOXED(78,16,FLEN) +NAN_BOXED(1067,16,FLEN) +NAN_BOXED(39,16,FLEN) +NAN_BOXED(1101,16,FLEN) +NAN_BOXED(69,16,FLEN) +NAN_BOXED(1054,16,FLEN) +NAN_BOXED(14,16,FLEN) +NAN_BOXED(1047,16,FLEN) +NAN_BOXED(32777,16,FLEN) +NAN_BOXED(1099,16,FLEN) +NAN_BOXED(11,16,FLEN) +NAN_BOXED(1036,16,FLEN) +NAN_BOXED(32884,16,FLEN) +NAN_BOXED(1057,16,FLEN) +NAN_BOXED(32991,16,FLEN) +NAN_BOXED(1111,16,FLEN) +NAN_BOXED(33193,16,FLEN) +NAN_BOXED(1035,16,FLEN) +NAN_BOXED(2054,16,FLEN) +NAN_BOXED(1082,16,FLEN) +NAN_BOXED(2078,16,FLEN) +NAN_BOXED(1121,16,FLEN) +NAN_BOXED(2098,16,FLEN) +NAN_BOXED(1060,16,FLEN) +NAN_BOXED(2070,16,FLEN) +NAN_BOXED(1059,16,FLEN) +NAN_BOXED(2073,16,FLEN) +NAN_BOXED(1104,16,FLEN) +NAN_BOXED(2104,16,FLEN) +NAN_BOXED(1069,16,FLEN) +NAN_BOXED(2102,16,FLEN) +NAN_BOXED(1033,16,FLEN) +NAN_BOXED(2116,16,FLEN) +NAN_BOXED(1045,16,FLEN) +NAN_BOXED(2186,16,FLEN) +NAN_BOXED(1092,16,FLEN) +NAN_BOXED(2338,16,FLEN) +NAN_BOXED(30805,16,FLEN) +NAN_BOXED(63314,16,FLEN) +NAN_BOXED(30803,16,FLEN) +NAN_BOXED(63316,16,FLEN) +NAN_BOXED(30758,16,FLEN) +NAN_BOXED(63402,16,FLEN) +NAN_BOXED(30810,16,FLEN) +NAN_BOXED(63290,16,FLEN) +NAN_BOXED(30784,16,FLEN) +NAN_BOXED(63326,16,FLEN) +NAN_BOXED(30735,16,FLEN) +NAN_BOXED(63392,16,FLEN) +NAN_BOXED(30760,16,FLEN) +NAN_BOXED(63278,16,FLEN) +NAN_BOXED(30764,16,FLEN) +NAN_BOXED(63142,16,FLEN) +NAN_BOXED(30745,16,FLEN) +NAN_BOXED(62924,16,FLEN) +NAN_BOXED(30734,16,FLEN) +NAN_BOXED(62404,16,FLEN) +NAN_BOXED(30814,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(30747,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(30776,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(30749,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(30771,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(30725,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(30741,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(30811,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(30807,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(30790,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(18,16,FLEN) +NAN_BOXED(16,16,FLEN) +NAN_BOXED(58,16,FLEN) +NAN_BOXED(42,16,FLEN) +NAN_BOXED(63,16,FLEN) +NAN_BOXED(32833,16,FLEN) +NAN_BOXED(4,16,FLEN) +NAN_BOXED(36,16,FLEN) +NAN_BOXED(4,16,FLEN) +NAN_BOXED(68,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x12_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x12_1: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x17_0: + .fill 30*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_0: + .fill 192*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fsub_b3-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fsub_b3-01.S new file mode 100644 index 000000000..dffc74793 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fsub_b3-01.S @@ -0,0 +1,10161 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 06:02:02 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fsub.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fsub.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fsub_b3 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fsub_b3) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x9,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rs2 == rd, rs1==x23, rs2==x23, rd==x23,fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x23; op2:x23; dest:x23; op1val:0x704c; op2val:0x704c; + valaddr_reg:x9; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4*/ +TEST_FPRR_OP(fsub.h, x23, x23, x23, dyn, 0, 0, x9, 0*FLEN/8, x20, x1, x4) + +inst_1: +// rs2 == rd != rs1, rs1==x15, rs2==x7, rd==x7,fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x15; op2:x7; dest:x7; op1val:0x704c; op2val:0x704c; + valaddr_reg:x9; val_offset:2*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4*/ +TEST_FPRR_OP(fsub.h, x7, x15, x7, dyn, 32, 0, x9, 2*FLEN/8, x20, x1, x4) + +inst_2: +// rs1 == rd != rs2, rs1==x6, rs2==x10, rd==x6,fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x6; op2:x10; dest:x6; op1val:0x704c; op2val:0x704c; + valaddr_reg:x9; val_offset:4*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4*/ +TEST_FPRR_OP(fsub.h, x6, x6, x10, dyn, 64, 0, x9, 4*FLEN/8, x20, x1, x4) + +inst_3: +// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==x28, rs2==x2, rd==x29,fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x28; op2:x2; dest:x29; op1val:0x704c; op2val:0x704c; + valaddr_reg:x9; val_offset:6*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4*/ +TEST_FPRR_OP(fsub.h, x29, x28, x2, dyn, 96, 0, x9, 6*FLEN/8, x20, x1, x4) + +inst_4: +// rs1 == rs2 != rd, rs1==x0, rs2==x0, rd==x17,fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x0; op2:x0; dest:x17; op1val:0x0; op2val:0x0; + valaddr_reg:x9; val_offset:8*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4*/ +TEST_FPRR_OP(fsub.h, x17, x0, x0, dyn, 128, 0, x9, 8*FLEN/8, x20, x1, x4) + +inst_5: +// rs1==x31, rs2==x6, rd==x11,fs1 == 0 and fe1 == 0x1e and fm1 == 0x21b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x21b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x31; op2:x6; dest:x11; op1val:0x7a1b; op2val:0x7a1b; + valaddr_reg:x9; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4*/ +TEST_FPRR_OP(fsub.h, x11, x31, x6, dyn, 0, 0, x9, 10*FLEN/8, x20, x1, x4) + +inst_6: +// rs1==x11, rs2==x12, rd==x30,fs1 == 0 and fe1 == 0x1e and fm1 == 0x21b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x21b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x11; op2:x12; dest:x30; op1val:0x7a1b; op2val:0x7a1b; + valaddr_reg:x9; val_offset:12*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4*/ +TEST_FPRR_OP(fsub.h, x30, x11, x12, dyn, 32, 0, x9, 12*FLEN/8, x20, x1, x4) + +inst_7: +// rs1==x5, rs2==x8, rd==x19,fs1 == 0 and fe1 == 0x1e and fm1 == 0x21b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x21b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x5; op2:x8; dest:x19; op1val:0x7a1b; op2val:0x7a1b; + valaddr_reg:x9; val_offset:14*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4*/ +TEST_FPRR_OP(fsub.h, x19, x5, x8, dyn, 64, 0, x9, 14*FLEN/8, x20, x1, x4) + +inst_8: +// rs1==x18, rs2==x19, rd==x16,fs1 == 0 and fe1 == 0x1e and fm1 == 0x21b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x21b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x18; op2:x19; dest:x16; op1val:0x7a1b; op2val:0x7a1b; + valaddr_reg:x9; val_offset:16*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4*/ +TEST_FPRR_OP(fsub.h, x16, x18, x19, dyn, 96, 0, x9, 16*FLEN/8, x20, x1, x4) + +inst_9: +// rs1==x12, rs2==x24, rd==x10,fs1 == 0 and fe1 == 0x1e and fm1 == 0x21b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x21b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x12; op2:x24; dest:x10; op1val:0x7a1b; op2val:0x7a1b; + valaddr_reg:x9; val_offset:18*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x4*/ +TEST_FPRR_OP(fsub.h, x10, x12, x24, dyn, 128, 0, x9, 18*FLEN/8, x20, x1, x4) + +inst_10: +// rs1==x14, rs2==x26, rd==x3,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ec and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3ec and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x14; op2:x26; dest:x3; op1val:0x77ec; op2val:0x77ec; + valaddr_reg:x9; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x4*/ +TEST_FPRR_OP(fsub.h, x3, x14, x26, dyn, 0, 0, x9, 20*FLEN/8, x20, x1, x4) + +inst_11: +// rs1==x13, rs2==x22, rd==x12,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ec and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3ec and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x13; op2:x22; dest:x12; op1val:0x77ec; op2val:0x77ec; + valaddr_reg:x9; val_offset:22*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x4*/ +TEST_FPRR_OP(fsub.h, x12, x13, x22, dyn, 32, 0, x9, 22*FLEN/8, x20, x1, x4) +RVTEST_VALBASEUPD(x5,test_dataset_1) + +inst_12: +// rs1==x27, rs2==x9, rd==x22,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ec and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3ec and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x27; op2:x9; dest:x22; op1val:0x77ec; op2val:0x77ec; + valaddr_reg:x5; val_offset:0*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x4*/ +TEST_FPRR_OP(fsub.h, x22, x27, x9, dyn, 64, 0, x5, 0*FLEN/8, x12, x1, x4) +RVTEST_SIGBASE(x6,signature_x6_0) + +inst_13: +// rs1==x22, rs2==x13, rd==x20,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ec and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3ec and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x22; op2:x13; dest:x20; op1val:0x77ec; op2val:0x77ec; + valaddr_reg:x5; val_offset:2*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x10*/ +TEST_FPRR_OP(fsub.h, x20, x22, x13, dyn, 96, 0, x5, 2*FLEN/8, x12, x6, x10) + +inst_14: +// rs1==x2, rs2==x11, rd==x24,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ec and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3ec and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x2; op2:x11; dest:x24; op1val:0x77ec; op2val:0x77ec; + valaddr_reg:x5; val_offset:4*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x10*/ +TEST_FPRR_OP(fsub.h, x24, x2, x11, dyn, 128, 0, x5, 4*FLEN/8, x12, x6, x10) + +inst_15: +// rs1==x16, rs2==x21, rd==x15,fs1 == 0 and fe1 == 0x1e and fm1 == 0x135 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x135 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x16; op2:x21; dest:x15; op1val:0x7935; op2val:0x7935; + valaddr_reg:x5; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x10*/ +TEST_FPRR_OP(fsub.h, x15, x16, x21, dyn, 0, 0, x5, 6*FLEN/8, x12, x6, x10) + +inst_16: +// rs1==x3, rs2==x31, rd==x1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x135 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x135 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x3; op2:x31; dest:x1; op1val:0x7935; op2val:0x7935; + valaddr_reg:x5; val_offset:8*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x10*/ +TEST_FPRR_OP(fsub.h, x1, x3, x31, dyn, 32, 0, x5, 8*FLEN/8, x12, x6, x10) + +inst_17: +// rs1==x7, rs2==x29, rd==x27,fs1 == 0 and fe1 == 0x1e and fm1 == 0x135 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x135 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x7; op2:x29; dest:x27; op1val:0x7935; op2val:0x7935; + valaddr_reg:x5; val_offset:10*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x10*/ +TEST_FPRR_OP(fsub.h, x27, x7, x29, dyn, 64, 0, x5, 10*FLEN/8, x12, x6, x10) + +inst_18: +// rs1==x21, rs2==x17, rd==x25,fs1 == 0 and fe1 == 0x1e and fm1 == 0x135 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x135 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x21; op2:x17; dest:x25; op1val:0x7935; op2val:0x7935; + valaddr_reg:x5; val_offset:12*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x10*/ +TEST_FPRR_OP(fsub.h, x25, x21, x17, dyn, 96, 0, x5, 12*FLEN/8, x12, x6, x10) + +inst_19: +// rs1==x29, rs2==x16, rd==x28,fs1 == 0 and fe1 == 0x1e and fm1 == 0x135 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x135 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x29; op2:x16; dest:x28; op1val:0x7935; op2val:0x7935; + valaddr_reg:x5; val_offset:14*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x10*/ +TEST_FPRR_OP(fsub.h, x28, x29, x16, dyn, 128, 0, x5, 14*FLEN/8, x12, x6, x10) + +inst_20: +// rs1==x26, rs2==x20, rd==x18,fs1 == 0 and fe1 == 0x1b and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x26; op2:x20; dest:x18; op1val:0x6e01; op2val:0x6e01; + valaddr_reg:x5; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x10*/ +TEST_FPRR_OP(fsub.h, x18, x26, x20, dyn, 0, 0, x5, 16*FLEN/8, x12, x6, x10) + +inst_21: +// rs1==x1, rs2==x15, rd==x4,fs1 == 0 and fe1 == 0x1b and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x201 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x1; op2:x15; dest:x4; op1val:0x6e01; op2val:0x6e01; + valaddr_reg:x5; val_offset:18*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x10*/ +TEST_FPRR_OP(fsub.h, x4, x1, x15, dyn, 32, 0, x5, 18*FLEN/8, x12, x6, x10) + +inst_22: +// rs1==x20, rs2==x18, rd==x9,fs1 == 0 and fe1 == 0x1b and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x201 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x20; op2:x18; dest:x9; op1val:0x6e01; op2val:0x6e01; + valaddr_reg:x5; val_offset:20*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x10*/ +TEST_FPRR_OP(fsub.h, x9, x20, x18, dyn, 64, 0, x5, 20*FLEN/8, x12, x6, x10) + +inst_23: +// rs1==x25, rs2==x27, rd==x8,fs1 == 0 and fe1 == 0x1b and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x201 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x25; op2:x27; dest:x8; op1val:0x6e01; op2val:0x6e01; + valaddr_reg:x5; val_offset:22*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x10*/ +TEST_FPRR_OP(fsub.h, x8, x25, x27, dyn, 96, 0, x5, 22*FLEN/8, x12, x6, x10) +RVTEST_VALBASEUPD(x7,test_dataset_2) + +inst_24: +// rs1==x4, rs2==x1, rd==x31,fs1 == 0 and fe1 == 0x1b and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x201 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x4; op2:x1; dest:x31; op1val:0x6e01; op2val:0x6e01; + valaddr_reg:x7; val_offset:0*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x10*/ +TEST_FPRR_OP(fsub.h, x31, x4, x1, dyn, 128, 0, x7, 0*FLEN/8, x11, x6, x10) + +inst_25: +// rs1==x30, rs2==x14, rd==x5,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ae and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x14; dest:x5; op1val:0x7aae; op2val:0x7aae; + valaddr_reg:x7; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x10*/ +TEST_FPRR_OP(fsub.h, x5, x30, x14, dyn, 0, 0, x7, 2*FLEN/8, x11, x6, x10) +RVTEST_SIGBASE(x1,signature_x1_2) + +inst_26: +// rs1==x24, rs2==x30, rd==x2,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ae and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x24; op2:x30; dest:x2; op1val:0x7aae; op2val:0x7aae; + valaddr_reg:x7; val_offset:4*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x2, x24, x30, dyn, 32, 0, x7, 4*FLEN/8, x11, x1, x6) + +inst_27: +// rs1==x8, rs2==x28, rd==x0,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ae and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x8; op2:x28; dest:x0; op1val:0x7aae; op2val:0x7aae; + valaddr_reg:x7; val_offset:6*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x0, x8, x28, dyn, 64, 0, x7, 6*FLEN/8, x11, x1, x6) + +inst_28: +// rs1==x17, rs2==x3, rd==x26,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ae and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x17; op2:x3; dest:x26; op1val:0x7aae; op2val:0x7aae; + valaddr_reg:x7; val_offset:8*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x26, x17, x3, dyn, 96, 0, x7, 8*FLEN/8, x11, x1, x6) + +inst_29: +// rs1==x19, rs2==x25, rd==x13,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ae and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x19; op2:x25; dest:x13; op1val:0x7aae; op2val:0x7aae; + valaddr_reg:x7; val_offset:10*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x13, x19, x25, dyn, 128, 0, x7, 10*FLEN/8, x11, x1, x6) + +inst_30: +// rs1==x10, rs2==x4, rd==x21,fs1 == 0 and fe1 == 0x1e and fm1 == 0x218 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x218 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x10; op2:x4; dest:x21; op1val:0x7a18; op2val:0x7a18; + valaddr_reg:x7; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x21, x10, x4, dyn, 0, 0, x7, 12*FLEN/8, x11, x1, x6) + +inst_31: +// rs1==x9, rs2==x5, rd==x14,fs1 == 0 and fe1 == 0x1e and fm1 == 0x218 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x218 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x9; op2:x5; dest:x14; op1val:0x7a18; op2val:0x7a18; + valaddr_reg:x7; val_offset:14*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x14, x9, x5, dyn, 32, 0, x7, 14*FLEN/8, x11, x1, x6) + +inst_32: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x218 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x218 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a18; op2val:0x7a18; + valaddr_reg:x7; val_offset:16*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 16*FLEN/8, x11, x1, x6) + +inst_33: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x218 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x218 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a18; op2val:0x7a18; + valaddr_reg:x7; val_offset:18*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 18*FLEN/8, x11, x1, x6) + +inst_34: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x218 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x218 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a18; op2val:0x7a18; + valaddr_reg:x7; val_offset:20*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 20*FLEN/8, x11, x1, x6) + +inst_35: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31f and fs2 == 0 and fe2 == 0x1d and fm2 == 0x31f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x771f; op2val:0x771f; + valaddr_reg:x7; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 22*FLEN/8, x11, x1, x6) + +inst_36: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31f and fs2 == 0 and fe2 == 0x1d and fm2 == 0x31f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x771f; op2val:0x771f; + valaddr_reg:x7; val_offset:24*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 24*FLEN/8, x11, x1, x6) + +inst_37: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31f and fs2 == 0 and fe2 == 0x1d and fm2 == 0x31f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x771f; op2val:0x771f; + valaddr_reg:x7; val_offset:26*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 26*FLEN/8, x11, x1, x6) + +inst_38: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31f and fs2 == 0 and fe2 == 0x1d and fm2 == 0x31f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x771f; op2val:0x771f; + valaddr_reg:x7; val_offset:28*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 28*FLEN/8, x11, x1, x6) + +inst_39: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31f and fs2 == 0 and fe2 == 0x1d and fm2 == 0x31f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x771f; op2val:0x771f; + valaddr_reg:x7; val_offset:30*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 30*FLEN/8, x11, x1, x6) + +inst_40: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x351 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x351 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7351; op2val:0x7351; + valaddr_reg:x7; val_offset:32*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 32*FLEN/8, x11, x1, x6) + +inst_41: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x351 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x351 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7351; op2val:0x7351; + valaddr_reg:x7; val_offset:34*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 34*FLEN/8, x11, x1, x6) + +inst_42: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x351 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x351 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7351; op2val:0x7351; + valaddr_reg:x7; val_offset:36*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 36*FLEN/8, x11, x1, x6) + +inst_43: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x351 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x351 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7351; op2val:0x7351; + valaddr_reg:x7; val_offset:38*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 38*FLEN/8, x11, x1, x6) + +inst_44: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x351 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x351 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7351; op2val:0x7351; + valaddr_reg:x7; val_offset:40*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 40*FLEN/8, x11, x1, x6) + +inst_45: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x335 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x335 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b35; op2val:0x7b35; + valaddr_reg:x7; val_offset:42*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 42*FLEN/8, x11, x1, x6) + +inst_46: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x335 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x335 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b35; op2val:0x7b35; + valaddr_reg:x7; val_offset:44*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 44*FLEN/8, x11, x1, x6) + +inst_47: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x335 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x335 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b35; op2val:0x7b35; + valaddr_reg:x7; val_offset:46*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 46*FLEN/8, x11, x1, x6) + +inst_48: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x335 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x335 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b35; op2val:0x7b35; + valaddr_reg:x7; val_offset:48*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 48*FLEN/8, x11, x1, x6) + +inst_49: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x335 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x335 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b35; op2val:0x7b35; + valaddr_reg:x7; val_offset:50*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 50*FLEN/8, x11, x1, x6) + +inst_50: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x283 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x283 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6683; op2val:0x6683; + valaddr_reg:x7; val_offset:52*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 52*FLEN/8, x11, x1, x6) + +inst_51: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x283 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x283 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6683; op2val:0x6683; + valaddr_reg:x7; val_offset:54*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 54*FLEN/8, x11, x1, x6) + +inst_52: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x283 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x283 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6683; op2val:0x6683; + valaddr_reg:x7; val_offset:56*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 56*FLEN/8, x11, x1, x6) + +inst_53: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x283 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x283 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6683; op2val:0x6683; + valaddr_reg:x7; val_offset:58*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 58*FLEN/8, x11, x1, x6) + +inst_54: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x283 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x283 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6683; op2val:0x6683; + valaddr_reg:x7; val_offset:60*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 60*FLEN/8, x11, x1, x6) + +inst_55: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x382 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x382 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b82; op2val:0x7b82; + valaddr_reg:x7; val_offset:62*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 62*FLEN/8, x11, x1, x6) + +inst_56: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x382 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x382 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b82; op2val:0x7b82; + valaddr_reg:x7; val_offset:64*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 64*FLEN/8, x11, x1, x6) + +inst_57: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x382 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x382 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b82; op2val:0x7b82; + valaddr_reg:x7; val_offset:66*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 66*FLEN/8, x11, x1, x6) + +inst_58: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x382 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x382 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b82; op2val:0x7b82; + valaddr_reg:x7; val_offset:68*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 68*FLEN/8, x11, x1, x6) + +inst_59: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x382 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x382 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b82; op2val:0x7b82; + valaddr_reg:x7; val_offset:70*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 70*FLEN/8, x11, x1, x6) + +inst_60: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ed and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2ed and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x72ed; op2val:0x72ed; + valaddr_reg:x7; val_offset:72*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 72*FLEN/8, x11, x1, x6) + +inst_61: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ed and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2ed and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x72ed; op2val:0x72ed; + valaddr_reg:x7; val_offset:74*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 74*FLEN/8, x11, x1, x6) + +inst_62: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ed and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2ed and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x72ed; op2val:0x72ed; + valaddr_reg:x7; val_offset:76*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 76*FLEN/8, x11, x1, x6) + +inst_63: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ed and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2ed and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x72ed; op2val:0x72ed; + valaddr_reg:x7; val_offset:78*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 78*FLEN/8, x11, x1, x6) + +inst_64: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ed and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2ed and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x72ed; op2val:0x72ed; + valaddr_reg:x7; val_offset:80*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 80*FLEN/8, x11, x1, x6) + +inst_65: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x36f and fs2 == 0 and fe2 == 0x19 and fm2 == 0x36f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x676f; op2val:0x676f; + valaddr_reg:x7; val_offset:82*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 82*FLEN/8, x11, x1, x6) + +inst_66: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x36f and fs2 == 0 and fe2 == 0x19 and fm2 == 0x36f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x676f; op2val:0x676f; + valaddr_reg:x7; val_offset:84*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 84*FLEN/8, x11, x1, x6) + +inst_67: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x36f and fs2 == 0 and fe2 == 0x19 and fm2 == 0x36f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x676f; op2val:0x676f; + valaddr_reg:x7; val_offset:86*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 86*FLEN/8, x11, x1, x6) + +inst_68: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x36f and fs2 == 0 and fe2 == 0x19 and fm2 == 0x36f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x676f; op2val:0x676f; + valaddr_reg:x7; val_offset:88*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 88*FLEN/8, x11, x1, x6) + +inst_69: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x36f and fs2 == 0 and fe2 == 0x19 and fm2 == 0x36f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x676f; op2val:0x676f; + valaddr_reg:x7; val_offset:90*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 90*FLEN/8, x11, x1, x6) + +inst_70: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x300 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7700; op2val:0x7700; + valaddr_reg:x7; val_offset:92*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 92*FLEN/8, x11, x1, x6) + +inst_71: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x300 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x300 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7700; op2val:0x7700; + valaddr_reg:x7; val_offset:94*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 94*FLEN/8, x11, x1, x6) + +inst_72: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x300 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x300 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7700; op2val:0x7700; + valaddr_reg:x7; val_offset:96*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 96*FLEN/8, x11, x1, x6) + +inst_73: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x300 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x300 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7700; op2val:0x7700; + valaddr_reg:x7; val_offset:98*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 98*FLEN/8, x11, x1, x6) + +inst_74: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x300 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x300 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7700; op2val:0x7700; + valaddr_reg:x7; val_offset:100*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 100*FLEN/8, x11, x1, x6) + +inst_75: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x374 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x374 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7374; op2val:0x7374; + valaddr_reg:x7; val_offset:102*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 102*FLEN/8, x11, x1, x6) + +inst_76: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x374 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x374 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7374; op2val:0x7374; + valaddr_reg:x7; val_offset:104*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 104*FLEN/8, x11, x1, x6) + +inst_77: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x374 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x374 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7374; op2val:0x7374; + valaddr_reg:x7; val_offset:106*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 106*FLEN/8, x11, x1, x6) + +inst_78: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x374 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x374 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7374; op2val:0x7374; + valaddr_reg:x7; val_offset:108*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 108*FLEN/8, x11, x1, x6) + +inst_79: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x374 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x374 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7374; op2val:0x7374; + valaddr_reg:x7; val_offset:110*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 110*FLEN/8, x11, x1, x6) + +inst_80: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ff and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x72ff; op2val:0x72ff; + valaddr_reg:x7; val_offset:112*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 112*FLEN/8, x11, x1, x6) + +inst_81: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ff and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x72ff; op2val:0x72ff; + valaddr_reg:x7; val_offset:114*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 114*FLEN/8, x11, x1, x6) + +inst_82: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ff and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x72ff; op2val:0x72ff; + valaddr_reg:x7; val_offset:116*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 116*FLEN/8, x11, x1, x6) + +inst_83: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ff and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x72ff; op2val:0x72ff; + valaddr_reg:x7; val_offset:118*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 118*FLEN/8, x11, x1, x6) + +inst_84: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ff and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x72ff; op2val:0x72ff; + valaddr_reg:x7; val_offset:120*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 120*FLEN/8, x11, x1, x6) + +inst_85: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a2 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0a2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74a2; op2val:0x74a2; + valaddr_reg:x7; val_offset:122*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 122*FLEN/8, x11, x1, x6) + +inst_86: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a2 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0a2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74a2; op2val:0x74a2; + valaddr_reg:x7; val_offset:124*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 124*FLEN/8, x11, x1, x6) + +inst_87: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a2 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0a2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74a2; op2val:0x74a2; + valaddr_reg:x7; val_offset:126*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 126*FLEN/8, x11, x1, x6) + +inst_88: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a2 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0a2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74a2; op2val:0x74a2; + valaddr_reg:x7; val_offset:128*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 128*FLEN/8, x11, x1, x6) + +inst_89: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a2 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0a2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74a2; op2val:0x74a2; + valaddr_reg:x7; val_offset:130*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 130*FLEN/8, x11, x1, x6) + +inst_90: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab2; op2val:0x7ab2; + valaddr_reg:x7; val_offset:132*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 132*FLEN/8, x11, x1, x6) + +inst_91: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab2; op2val:0x7ab2; + valaddr_reg:x7; val_offset:134*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 134*FLEN/8, x11, x1, x6) + +inst_92: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab2; op2val:0x7ab2; + valaddr_reg:x7; val_offset:136*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 136*FLEN/8, x11, x1, x6) + +inst_93: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab2; op2val:0x7ab2; + valaddr_reg:x7; val_offset:138*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 138*FLEN/8, x11, x1, x6) + +inst_94: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab2; op2val:0x7ab2; + valaddr_reg:x7; val_offset:140*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 140*FLEN/8, x11, x1, x6) + +inst_95: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x122 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x122 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7922; op2val:0x7922; + valaddr_reg:x7; val_offset:142*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 142*FLEN/8, x11, x1, x6) + +inst_96: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x122 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x122 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7922; op2val:0x7922; + valaddr_reg:x7; val_offset:144*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 144*FLEN/8, x11, x1, x6) + +inst_97: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x122 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x122 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7922; op2val:0x7922; + valaddr_reg:x7; val_offset:146*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 146*FLEN/8, x11, x1, x6) + +inst_98: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x122 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x122 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7922; op2val:0x7922; + valaddr_reg:x7; val_offset:148*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 148*FLEN/8, x11, x1, x6) + +inst_99: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x122 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x122 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7922; op2val:0x7922; + valaddr_reg:x7; val_offset:150*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 150*FLEN/8, x11, x1, x6) + +inst_100: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ef and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ef and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bef; op2val:0x7bef; + valaddr_reg:x7; val_offset:152*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 152*FLEN/8, x11, x1, x6) + +inst_101: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ef and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ef and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bef; op2val:0x7bef; + valaddr_reg:x7; val_offset:154*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 154*FLEN/8, x11, x1, x6) + +inst_102: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ef and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ef and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bef; op2val:0x7bef; + valaddr_reg:x7; val_offset:156*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 156*FLEN/8, x11, x1, x6) + +inst_103: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ef and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ef and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bef; op2val:0x7bef; + valaddr_reg:x7; val_offset:158*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 158*FLEN/8, x11, x1, x6) + +inst_104: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ef and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ef and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bef; op2val:0x7bef; + valaddr_reg:x7; val_offset:160*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 160*FLEN/8, x11, x1, x6) + +inst_105: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3bb and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3bb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6fbb; op2val:0x6fbb; + valaddr_reg:x7; val_offset:162*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 162*FLEN/8, x11, x1, x6) + +inst_106: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3bb and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3bb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6fbb; op2val:0x6fbb; + valaddr_reg:x7; val_offset:164*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 164*FLEN/8, x11, x1, x6) + +inst_107: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3bb and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3bb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6fbb; op2val:0x6fbb; + valaddr_reg:x7; val_offset:166*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 166*FLEN/8, x11, x1, x6) + +inst_108: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3bb and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3bb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6fbb; op2val:0x6fbb; + valaddr_reg:x7; val_offset:168*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 168*FLEN/8, x11, x1, x6) + +inst_109: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3bb and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3bb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6fbb; op2val:0x6fbb; + valaddr_reg:x7; val_offset:170*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 170*FLEN/8, x11, x1, x6) + +inst_110: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1c4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c4; op2val:0x79c4; + valaddr_reg:x7; val_offset:172*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 172*FLEN/8, x11, x1, x6) + +inst_111: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1c4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c4; op2val:0x79c4; + valaddr_reg:x7; val_offset:174*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 174*FLEN/8, x11, x1, x6) + +inst_112: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1c4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c4; op2val:0x79c4; + valaddr_reg:x7; val_offset:176*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 176*FLEN/8, x11, x1, x6) + +inst_113: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1c4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c4; op2val:0x79c4; + valaddr_reg:x7; val_offset:178*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 178*FLEN/8, x11, x1, x6) + +inst_114: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1c4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c4; op2val:0x79c4; + valaddr_reg:x7; val_offset:180*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 180*FLEN/8, x11, x1, x6) + +inst_115: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x37c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b7c; op2val:0x7b7c; + valaddr_reg:x7; val_offset:182*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 182*FLEN/8, x11, x1, x6) + +inst_116: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x37c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b7c; op2val:0x7b7c; + valaddr_reg:x7; val_offset:184*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 184*FLEN/8, x11, x1, x6) + +inst_117: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x37c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b7c; op2val:0x7b7c; + valaddr_reg:x7; val_offset:186*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 186*FLEN/8, x11, x1, x6) + +inst_118: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x37c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b7c; op2val:0x7b7c; + valaddr_reg:x7; val_offset:188*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 188*FLEN/8, x11, x1, x6) + +inst_119: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x37c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b7c; op2val:0x7b7c; + valaddr_reg:x7; val_offset:190*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 190*FLEN/8, x11, x1, x6) + +inst_120: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2a3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aa3; op2val:0x7aa3; + valaddr_reg:x7; val_offset:192*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 192*FLEN/8, x11, x1, x6) + +inst_121: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2a3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aa3; op2val:0x7aa3; + valaddr_reg:x7; val_offset:194*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 194*FLEN/8, x11, x1, x6) + +inst_122: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2a3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aa3; op2val:0x7aa3; + valaddr_reg:x7; val_offset:196*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 196*FLEN/8, x11, x1, x6) + +inst_123: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2a3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aa3; op2val:0x7aa3; + valaddr_reg:x7; val_offset:198*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 198*FLEN/8, x11, x1, x6) + +inst_124: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2a3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aa3; op2val:0x7aa3; + valaddr_reg:x7; val_offset:200*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 200*FLEN/8, x11, x1, x6) + +inst_125: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0da and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0da and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74da; op2val:0x74da; + valaddr_reg:x7; val_offset:202*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 202*FLEN/8, x11, x1, x6) + +inst_126: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0da and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0da and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74da; op2val:0x74da; + valaddr_reg:x7; val_offset:204*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 204*FLEN/8, x11, x1, x6) + +inst_127: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0da and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0da and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74da; op2val:0x74da; + valaddr_reg:x7; val_offset:206*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 206*FLEN/8, x11, x1, x6) + +inst_128: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0da and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0da and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74da; op2val:0x74da; + valaddr_reg:x7; val_offset:208*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 208*FLEN/8, x11, x1, x6) + +inst_129: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0da and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0da and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74da; op2val:0x74da; + valaddr_reg:x7; val_offset:210*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 210*FLEN/8, x11, x1, x6) + +inst_130: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x30e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b0e; op2val:0x7b0e; + valaddr_reg:x7; val_offset:212*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 212*FLEN/8, x11, x1, x6) + +inst_131: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x30e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b0e; op2val:0x7b0e; + valaddr_reg:x7; val_offset:214*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 214*FLEN/8, x11, x1, x6) + +inst_132: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x30e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b0e; op2val:0x7b0e; + valaddr_reg:x7; val_offset:216*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 216*FLEN/8, x11, x1, x6) + +inst_133: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x30e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b0e; op2val:0x7b0e; + valaddr_reg:x7; val_offset:218*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 218*FLEN/8, x11, x1, x6) + +inst_134: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x30e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b0e; op2val:0x7b0e; + valaddr_reg:x7; val_offset:220*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 220*FLEN/8, x11, x1, x6) + +inst_135: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x00a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x780a; op2val:0x780a; + valaddr_reg:x7; val_offset:222*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 222*FLEN/8, x11, x1, x6) + +inst_136: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x00a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x780a; op2val:0x780a; + valaddr_reg:x7; val_offset:224*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 224*FLEN/8, x11, x1, x6) + +inst_137: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x00a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x780a; op2val:0x780a; + valaddr_reg:x7; val_offset:226*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 226*FLEN/8, x11, x1, x6) + +inst_138: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x00a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x780a; op2val:0x780a; + valaddr_reg:x7; val_offset:228*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 228*FLEN/8, x11, x1, x6) + +inst_139: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x00a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x780a; op2val:0x780a; + valaddr_reg:x7; val_offset:230*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 230*FLEN/8, x11, x1, x6) + +inst_140: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x06b and fs2 == 0 and fe2 == 0x1a and fm2 == 0x06b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x686b; op2val:0x686b; + valaddr_reg:x7; val_offset:232*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 232*FLEN/8, x11, x1, x6) + +inst_141: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x06b and fs2 == 0 and fe2 == 0x1a and fm2 == 0x06b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x686b; op2val:0x686b; + valaddr_reg:x7; val_offset:234*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 234*FLEN/8, x11, x1, x6) + +inst_142: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x06b and fs2 == 0 and fe2 == 0x1a and fm2 == 0x06b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x686b; op2val:0x686b; + valaddr_reg:x7; val_offset:236*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 236*FLEN/8, x11, x1, x6) + +inst_143: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x06b and fs2 == 0 and fe2 == 0x1a and fm2 == 0x06b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x686b; op2val:0x686b; + valaddr_reg:x7; val_offset:238*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 238*FLEN/8, x11, x1, x6) + +inst_144: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x06b and fs2 == 0 and fe2 == 0x1a and fm2 == 0x06b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x686b; op2val:0x686b; + valaddr_reg:x7; val_offset:240*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 240*FLEN/8, x11, x1, x6) + +inst_145: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x260 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x260 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a60; op2val:0x7a60; + valaddr_reg:x7; val_offset:242*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 242*FLEN/8, x11, x1, x6) + +inst_146: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x260 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x260 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a60; op2val:0x7a60; + valaddr_reg:x7; val_offset:244*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 244*FLEN/8, x11, x1, x6) + +inst_147: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x260 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x260 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a60; op2val:0x7a60; + valaddr_reg:x7; val_offset:246*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 246*FLEN/8, x11, x1, x6) + +inst_148: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x260 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x260 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a60; op2val:0x7a60; + valaddr_reg:x7; val_offset:248*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 248*FLEN/8, x11, x1, x6) + +inst_149: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x260 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x260 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a60; op2val:0x7a60; + valaddr_reg:x7; val_offset:250*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 250*FLEN/8, x11, x1, x6) + +inst_150: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x188 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x188 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7188; op2val:0x7188; + valaddr_reg:x7; val_offset:252*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 252*FLEN/8, x11, x1, x6) + +inst_151: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x188 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x188 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7188; op2val:0x7188; + valaddr_reg:x7; val_offset:254*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 254*FLEN/8, x11, x1, x6) + +inst_152: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x188 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x188 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7188; op2val:0x7188; + valaddr_reg:x7; val_offset:256*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 256*FLEN/8, x11, x1, x6) + +inst_153: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x188 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x188 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7188; op2val:0x7188; + valaddr_reg:x7; val_offset:258*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 258*FLEN/8, x11, x1, x6) +RVTEST_SIGBASE(x1,signature_x1_3) + +inst_154: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x188 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x188 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7188; op2val:0x7188; + valaddr_reg:x7; val_offset:260*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 260*FLEN/8, x11, x1, x6) + +inst_155: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x19f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x799f; op2val:0x799f; + valaddr_reg:x7; val_offset:262*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 262*FLEN/8, x11, x1, x6) + +inst_156: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x19f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x799f; op2val:0x799f; + valaddr_reg:x7; val_offset:264*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 264*FLEN/8, x11, x1, x6) + +inst_157: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x19f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x799f; op2val:0x799f; + valaddr_reg:x7; val_offset:266*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 266*FLEN/8, x11, x1, x6) + +inst_158: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x19f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x799f; op2val:0x799f; + valaddr_reg:x7; val_offset:268*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 268*FLEN/8, x11, x1, x6) + +inst_159: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x19f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x799f; op2val:0x799f; + valaddr_reg:x7; val_offset:270*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 270*FLEN/8, x11, x1, x6) + +inst_160: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1fe and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x75fe; op2val:0x75fe; + valaddr_reg:x7; val_offset:272*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 272*FLEN/8, x11, x1, x6) + +inst_161: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1fe and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1fe and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x75fe; op2val:0x75fe; + valaddr_reg:x7; val_offset:274*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 274*FLEN/8, x11, x1, x6) + +inst_162: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1fe and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1fe and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x75fe; op2val:0x75fe; + valaddr_reg:x7; val_offset:276*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 276*FLEN/8, x11, x1, x6) + +inst_163: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1fe and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1fe and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x75fe; op2val:0x75fe; + valaddr_reg:x7; val_offset:278*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 278*FLEN/8, x11, x1, x6) + +inst_164: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1fe and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1fe and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x75fe; op2val:0x75fe; + valaddr_reg:x7; val_offset:280*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 280*FLEN/8, x11, x1, x6) + +inst_165: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x010 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x010 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7810; op2val:0x7810; + valaddr_reg:x7; val_offset:282*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 282*FLEN/8, x11, x1, x6) + +inst_166: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x010 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x010 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7810; op2val:0x7810; + valaddr_reg:x7; val_offset:284*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 284*FLEN/8, x11, x1, x6) + +inst_167: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x010 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x010 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7810; op2val:0x7810; + valaddr_reg:x7; val_offset:286*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 286*FLEN/8, x11, x1, x6) + +inst_168: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x010 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x010 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7810; op2val:0x7810; + valaddr_reg:x7; val_offset:288*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 288*FLEN/8, x11, x1, x6) + +inst_169: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x010 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x010 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7810; op2val:0x7810; + valaddr_reg:x7; val_offset:290*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 290*FLEN/8, x11, x1, x6) + +inst_170: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x02a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x782a; op2val:0x782a; + valaddr_reg:x7; val_offset:292*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 292*FLEN/8, x11, x1, x6) + +inst_171: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x02a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x782a; op2val:0x782a; + valaddr_reg:x7; val_offset:294*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 294*FLEN/8, x11, x1, x6) + +inst_172: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x02a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x782a; op2val:0x782a; + valaddr_reg:x7; val_offset:296*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 296*FLEN/8, x11, x1, x6) + +inst_173: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x02a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x782a; op2val:0x782a; + valaddr_reg:x7; val_offset:298*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 298*FLEN/8, x11, x1, x6) + +inst_174: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x02a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x782a; op2val:0x782a; + valaddr_reg:x7; val_offset:300*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 300*FLEN/8, x11, x1, x6) + +inst_175: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d4 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3d4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x77d4; op2val:0x77d4; + valaddr_reg:x7; val_offset:302*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 302*FLEN/8, x11, x1, x6) + +inst_176: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d4 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3d4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x77d4; op2val:0x77d4; + valaddr_reg:x7; val_offset:304*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 304*FLEN/8, x11, x1, x6) + +inst_177: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d4 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3d4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x77d4; op2val:0x77d4; + valaddr_reg:x7; val_offset:306*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 306*FLEN/8, x11, x1, x6) + +inst_178: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d4 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3d4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x77d4; op2val:0x77d4; + valaddr_reg:x7; val_offset:308*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 308*FLEN/8, x11, x1, x6) + +inst_179: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d4 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3d4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x77d4; op2val:0x77d4; + valaddr_reg:x7; val_offset:310*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 310*FLEN/8, x11, x1, x6) + +inst_180: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x190 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x190 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6990; op2val:0x6990; + valaddr_reg:x7; val_offset:312*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 312*FLEN/8, x11, x1, x6) + +inst_181: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x190 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x190 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6990; op2val:0x6990; + valaddr_reg:x7; val_offset:314*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 314*FLEN/8, x11, x1, x6) + +inst_182: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x190 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x190 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6990; op2val:0x6990; + valaddr_reg:x7; val_offset:316*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 316*FLEN/8, x11, x1, x6) + +inst_183: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x190 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x190 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6990; op2val:0x6990; + valaddr_reg:x7; val_offset:318*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 318*FLEN/8, x11, x1, x6) + +inst_184: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x190 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x190 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6990; op2val:0x6990; + valaddr_reg:x7; val_offset:320*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 320*FLEN/8, x11, x1, x6) + +inst_185: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3dc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3dc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bdc; op2val:0x7bdc; + valaddr_reg:x7; val_offset:322*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 322*FLEN/8, x11, x1, x6) + +inst_186: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3dc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3dc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bdc; op2val:0x7bdc; + valaddr_reg:x7; val_offset:324*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 324*FLEN/8, x11, x1, x6) + +inst_187: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3dc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3dc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bdc; op2val:0x7bdc; + valaddr_reg:x7; val_offset:326*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 326*FLEN/8, x11, x1, x6) + +inst_188: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3dc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3dc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bdc; op2val:0x7bdc; + valaddr_reg:x7; val_offset:328*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 328*FLEN/8, x11, x1, x6) + +inst_189: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3dc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3dc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bdc; op2val:0x7bdc; + valaddr_reg:x7; val_offset:330*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 330*FLEN/8, x11, x1, x6) + +inst_190: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x24b and fs2 == 0 and fe2 == 0x1d and fm2 == 0x24b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x764b; op2val:0x764b; + valaddr_reg:x7; val_offset:332*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 332*FLEN/8, x11, x1, x6) + +inst_191: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x24b and fs2 == 0 and fe2 == 0x1d and fm2 == 0x24b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x764b; op2val:0x764b; + valaddr_reg:x7; val_offset:334*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 334*FLEN/8, x11, x1, x6) + +inst_192: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x24b and fs2 == 0 and fe2 == 0x1d and fm2 == 0x24b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x764b; op2val:0x764b; + valaddr_reg:x7; val_offset:336*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 336*FLEN/8, x11, x1, x6) + +inst_193: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x24b and fs2 == 0 and fe2 == 0x1d and fm2 == 0x24b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x764b; op2val:0x764b; + valaddr_reg:x7; val_offset:338*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 338*FLEN/8, x11, x1, x6) + +inst_194: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x24b and fs2 == 0 and fe2 == 0x1d and fm2 == 0x24b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x764b; op2val:0x764b; + valaddr_reg:x7; val_offset:340*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 340*FLEN/8, x11, x1, x6) + +inst_195: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x004 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7804; op2val:0x7804; + valaddr_reg:x7; val_offset:342*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 342*FLEN/8, x11, x1, x6) + +inst_196: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x004 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7804; op2val:0x7804; + valaddr_reg:x7; val_offset:344*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 344*FLEN/8, x11, x1, x6) + +inst_197: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x004 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7804; op2val:0x7804; + valaddr_reg:x7; val_offset:346*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 346*FLEN/8, x11, x1, x6) + +inst_198: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x004 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7804; op2val:0x7804; + valaddr_reg:x7; val_offset:348*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 348*FLEN/8, x11, x1, x6) + +inst_199: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x004 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7804; op2val:0x7804; + valaddr_reg:x7; val_offset:350*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 350*FLEN/8, x11, x1, x6) + +inst_200: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x229 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x229 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a29; op2val:0x7a29; + valaddr_reg:x7; val_offset:352*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 352*FLEN/8, x11, x1, x6) + +inst_201: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x229 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x229 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a29; op2val:0x7a29; + valaddr_reg:x7; val_offset:354*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 354*FLEN/8, x11, x1, x6) + +inst_202: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x229 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x229 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a29; op2val:0x7a29; + valaddr_reg:x7; val_offset:356*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 356*FLEN/8, x11, x1, x6) + +inst_203: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x229 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x229 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a29; op2val:0x7a29; + valaddr_reg:x7; val_offset:358*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 358*FLEN/8, x11, x1, x6) + +inst_204: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x229 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x229 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a29; op2val:0x7a29; + valaddr_reg:x7; val_offset:360*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 360*FLEN/8, x11, x1, x6) + +inst_205: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2e1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ae1; op2val:0x7ae1; + valaddr_reg:x7; val_offset:362*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 362*FLEN/8, x11, x1, x6) + +inst_206: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2e1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ae1; op2val:0x7ae1; + valaddr_reg:x7; val_offset:364*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 364*FLEN/8, x11, x1, x6) + +inst_207: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2e1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ae1; op2val:0x7ae1; + valaddr_reg:x7; val_offset:366*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 366*FLEN/8, x11, x1, x6) + +inst_208: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2e1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ae1; op2val:0x7ae1; + valaddr_reg:x7; val_offset:368*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 368*FLEN/8, x11, x1, x6) + +inst_209: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2e1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ae1; op2val:0x7ae1; + valaddr_reg:x7; val_offset:370*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 370*FLEN/8, x11, x1, x6) + +inst_210: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x01b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x01b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x781b; op2val:0x781b; + valaddr_reg:x7; val_offset:372*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 372*FLEN/8, x11, x1, x6) + +inst_211: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x01b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x01b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x781b; op2val:0x781b; + valaddr_reg:x7; val_offset:374*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 374*FLEN/8, x11, x1, x6) + +inst_212: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x01b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x01b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x781b; op2val:0x781b; + valaddr_reg:x7; val_offset:376*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 376*FLEN/8, x11, x1, x6) + +inst_213: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x01b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x01b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x781b; op2val:0x781b; + valaddr_reg:x7; val_offset:378*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 378*FLEN/8, x11, x1, x6) + +inst_214: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x01b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x01b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x781b; op2val:0x781b; + valaddr_reg:x7; val_offset:380*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 380*FLEN/8, x11, x1, x6) + +inst_215: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x09e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x789e; op2val:0x789e; + valaddr_reg:x7; val_offset:382*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 382*FLEN/8, x11, x1, x6) + +inst_216: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x09e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x789e; op2val:0x789e; + valaddr_reg:x7; val_offset:384*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 384*FLEN/8, x11, x1, x6) + +inst_217: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x09e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x789e; op2val:0x789e; + valaddr_reg:x7; val_offset:386*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 386*FLEN/8, x11, x1, x6) + +inst_218: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x09e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x789e; op2val:0x789e; + valaddr_reg:x7; val_offset:388*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 388*FLEN/8, x11, x1, x6) + +inst_219: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x09e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x789e; op2val:0x789e; + valaddr_reg:x7; val_offset:390*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 390*FLEN/8, x11, x1, x6) + +inst_220: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x04e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x04e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x744e; op2val:0x744e; + valaddr_reg:x7; val_offset:392*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 392*FLEN/8, x11, x1, x6) + +inst_221: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x04e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x04e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x744e; op2val:0x744e; + valaddr_reg:x7; val_offset:394*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 394*FLEN/8, x11, x1, x6) + +inst_222: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x04e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x04e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x744e; op2val:0x744e; + valaddr_reg:x7; val_offset:396*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 396*FLEN/8, x11, x1, x6) + +inst_223: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x04e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x04e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x744e; op2val:0x744e; + valaddr_reg:x7; val_offset:398*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 398*FLEN/8, x11, x1, x6) + +inst_224: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x04e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x04e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x744e; op2val:0x744e; + valaddr_reg:x7; val_offset:400*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 400*FLEN/8, x11, x1, x6) + +inst_225: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3a7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba7; op2val:0x7ba7; + valaddr_reg:x7; val_offset:402*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 402*FLEN/8, x11, x1, x6) + +inst_226: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3a7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba7; op2val:0x7ba7; + valaddr_reg:x7; val_offset:404*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 404*FLEN/8, x11, x1, x6) + +inst_227: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3a7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba7; op2val:0x7ba7; + valaddr_reg:x7; val_offset:406*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 406*FLEN/8, x11, x1, x6) + +inst_228: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3a7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba7; op2val:0x7ba7; + valaddr_reg:x7; val_offset:408*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 408*FLEN/8, x11, x1, x6) + +inst_229: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3a7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba7; op2val:0x7ba7; + valaddr_reg:x7; val_offset:410*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 410*FLEN/8, x11, x1, x6) + +inst_230: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x244 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x244 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a44; op2val:0x7a44; + valaddr_reg:x7; val_offset:412*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 412*FLEN/8, x11, x1, x6) + +inst_231: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x244 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x244 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a44; op2val:0x7a44; + valaddr_reg:x7; val_offset:414*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 414*FLEN/8, x11, x1, x6) + +inst_232: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x244 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x244 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a44; op2val:0x7a44; + valaddr_reg:x7; val_offset:416*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 416*FLEN/8, x11, x1, x6) + +inst_233: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x244 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x244 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a44; op2val:0x7a44; + valaddr_reg:x7; val_offset:418*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 418*FLEN/8, x11, x1, x6) + +inst_234: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x244 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x244 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a44; op2val:0x7a44; + valaddr_reg:x7; val_offset:420*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 420*FLEN/8, x11, x1, x6) + +inst_235: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x316 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x316 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b16; op2val:0x7b16; + valaddr_reg:x7; val_offset:422*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 422*FLEN/8, x11, x1, x6) + +inst_236: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x316 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x316 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b16; op2val:0x7b16; + valaddr_reg:x7; val_offset:424*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 424*FLEN/8, x11, x1, x6) + +inst_237: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x316 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x316 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b16; op2val:0x7b16; + valaddr_reg:x7; val_offset:426*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 426*FLEN/8, x11, x1, x6) + +inst_238: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x316 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x316 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b16; op2val:0x7b16; + valaddr_reg:x7; val_offset:428*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 428*FLEN/8, x11, x1, x6) + +inst_239: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x316 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x316 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b16; op2val:0x7b16; + valaddr_reg:x7; val_offset:430*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 430*FLEN/8, x11, x1, x6) + +inst_240: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x278 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x278 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a78; op2val:0x7a78; + valaddr_reg:x7; val_offset:432*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 432*FLEN/8, x11, x1, x6) + +inst_241: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x278 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x278 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a78; op2val:0x7a78; + valaddr_reg:x7; val_offset:434*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 434*FLEN/8, x11, x1, x6) + +inst_242: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x278 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x278 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a78; op2val:0x7a78; + valaddr_reg:x7; val_offset:436*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 436*FLEN/8, x11, x1, x6) + +inst_243: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x278 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x278 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a78; op2val:0x7a78; + valaddr_reg:x7; val_offset:438*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 438*FLEN/8, x11, x1, x6) + +inst_244: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x278 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x278 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a78; op2val:0x7a78; + valaddr_reg:x7; val_offset:440*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 440*FLEN/8, x11, x1, x6) + +inst_245: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x07d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x07d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x787d; op2val:0x787d; + valaddr_reg:x7; val_offset:442*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 442*FLEN/8, x11, x1, x6) + +inst_246: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x07d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x07d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x787d; op2val:0x787d; + valaddr_reg:x7; val_offset:444*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 444*FLEN/8, x11, x1, x6) + +inst_247: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x07d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x07d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x787d; op2val:0x787d; + valaddr_reg:x7; val_offset:446*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 446*FLEN/8, x11, x1, x6) + +inst_248: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x07d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x07d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x787d; op2val:0x787d; + valaddr_reg:x7; val_offset:448*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 448*FLEN/8, x11, x1, x6) + +inst_249: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x07d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x07d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x787d; op2val:0x787d; + valaddr_reg:x7; val_offset:450*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 450*FLEN/8, x11, x1, x6) + +inst_250: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x32e and fs2 == 0 and fe2 == 0x1a and fm2 == 0x32e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6b2e; op2val:0x6b2e; + valaddr_reg:x7; val_offset:452*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 452*FLEN/8, x11, x1, x6) + +inst_251: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x32e and fs2 == 0 and fe2 == 0x1a and fm2 == 0x32e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6b2e; op2val:0x6b2e; + valaddr_reg:x7; val_offset:454*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 454*FLEN/8, x11, x1, x6) + +inst_252: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x32e and fs2 == 0 and fe2 == 0x1a and fm2 == 0x32e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6b2e; op2val:0x6b2e; + valaddr_reg:x7; val_offset:456*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 456*FLEN/8, x11, x1, x6) + +inst_253: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x32e and fs2 == 0 and fe2 == 0x1a and fm2 == 0x32e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6b2e; op2val:0x6b2e; + valaddr_reg:x7; val_offset:458*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 458*FLEN/8, x11, x1, x6) + +inst_254: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x32e and fs2 == 0 and fe2 == 0x1a and fm2 == 0x32e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6b2e; op2val:0x6b2e; + valaddr_reg:x7; val_offset:460*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 460*FLEN/8, x11, x1, x6) + +inst_255: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x08e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x08e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x788e; op2val:0x788e; + valaddr_reg:x7; val_offset:462*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 462*FLEN/8, x11, x1, x6) + +inst_256: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x08e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x08e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x788e; op2val:0x788e; + valaddr_reg:x7; val_offset:464*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 464*FLEN/8, x11, x1, x6) + +inst_257: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x08e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x08e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x788e; op2val:0x788e; + valaddr_reg:x7; val_offset:466*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 466*FLEN/8, x11, x1, x6) + +inst_258: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x08e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x08e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x788e; op2val:0x788e; + valaddr_reg:x7; val_offset:468*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 468*FLEN/8, x11, x1, x6) + +inst_259: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x08e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x08e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x788e; op2val:0x788e; + valaddr_reg:x7; val_offset:470*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 470*FLEN/8, x11, x1, x6) + +inst_260: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x009 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x009 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7809; op2val:0x7809; + valaddr_reg:x7; val_offset:472*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 472*FLEN/8, x11, x1, x6) + +inst_261: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x009 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x009 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7809; op2val:0x7809; + valaddr_reg:x7; val_offset:474*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 474*FLEN/8, x11, x1, x6) + +inst_262: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x009 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x009 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7809; op2val:0x7809; + valaddr_reg:x7; val_offset:476*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 476*FLEN/8, x11, x1, x6) + +inst_263: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x009 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x009 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7809; op2val:0x7809; + valaddr_reg:x7; val_offset:478*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 478*FLEN/8, x11, x1, x6) + +inst_264: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x009 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x009 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7809; op2val:0x7809; + valaddr_reg:x7; val_offset:480*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 480*FLEN/8, x11, x1, x6) + +inst_265: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1b4 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1b4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x75b4; op2val:0x75b4; + valaddr_reg:x7; val_offset:482*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 482*FLEN/8, x11, x1, x6) + +inst_266: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1b4 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1b4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x75b4; op2val:0x75b4; + valaddr_reg:x7; val_offset:484*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 484*FLEN/8, x11, x1, x6) + +inst_267: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1b4 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1b4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x75b4; op2val:0x75b4; + valaddr_reg:x7; val_offset:486*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 486*FLEN/8, x11, x1, x6) + +inst_268: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1b4 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1b4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x75b4; op2val:0x75b4; + valaddr_reg:x7; val_offset:488*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 488*FLEN/8, x11, x1, x6) + +inst_269: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1b4 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1b4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x75b4; op2val:0x75b4; + valaddr_reg:x7; val_offset:490*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 490*FLEN/8, x11, x1, x6) + +inst_270: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x04e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x784e; op2val:0x784e; + valaddr_reg:x7; val_offset:492*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 492*FLEN/8, x11, x1, x6) + +inst_271: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x04e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x784e; op2val:0x784e; + valaddr_reg:x7; val_offset:494*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 494*FLEN/8, x11, x1, x6) + +inst_272: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x04e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x784e; op2val:0x784e; + valaddr_reg:x7; val_offset:496*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 496*FLEN/8, x11, x1, x6) + +inst_273: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x04e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x784e; op2val:0x784e; + valaddr_reg:x7; val_offset:498*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 498*FLEN/8, x11, x1, x6) + +inst_274: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x04e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x784e; op2val:0x784e; + valaddr_reg:x7; val_offset:500*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 500*FLEN/8, x11, x1, x6) + +inst_275: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0e5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x78e5; op2val:0x78e5; + valaddr_reg:x7; val_offset:502*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 502*FLEN/8, x11, x1, x6) + +inst_276: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0e5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x78e5; op2val:0x78e5; + valaddr_reg:x7; val_offset:504*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 504*FLEN/8, x11, x1, x6) + +inst_277: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0e5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x78e5; op2val:0x78e5; + valaddr_reg:x7; val_offset:506*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 506*FLEN/8, x11, x1, x6) + +inst_278: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0e5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x78e5; op2val:0x78e5; + valaddr_reg:x7; val_offset:508*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 508*FLEN/8, x11, x1, x6) + +inst_279: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0e5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x78e5; op2val:0x78e5; + valaddr_reg:x7; val_offset:510*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 510*FLEN/8, x11, x1, x6) + +inst_280: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x329 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x329 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6729; op2val:0x6729; + valaddr_reg:x7; val_offset:512*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 512*FLEN/8, x11, x1, x6) + +inst_281: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x329 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x329 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6729; op2val:0x6729; + valaddr_reg:x7; val_offset:514*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 514*FLEN/8, x11, x1, x6) +RVTEST_SIGBASE(x1,signature_x1_4) + +inst_282: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x329 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x329 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6729; op2val:0x6729; + valaddr_reg:x7; val_offset:516*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 516*FLEN/8, x11, x1, x6) + +inst_283: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x329 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x329 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6729; op2val:0x6729; + valaddr_reg:x7; val_offset:518*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 518*FLEN/8, x11, x1, x6) + +inst_284: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x329 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x329 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6729; op2val:0x6729; + valaddr_reg:x7; val_offset:520*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 520*FLEN/8, x11, x1, x6) + +inst_285: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1ab and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1ab and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x71ab; op2val:0x71ab; + valaddr_reg:x7; val_offset:522*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 522*FLEN/8, x11, x1, x6) + +inst_286: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1ab and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1ab and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x71ab; op2val:0x71ab; + valaddr_reg:x7; val_offset:524*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 524*FLEN/8, x11, x1, x6) + +inst_287: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1ab and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1ab and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x71ab; op2val:0x71ab; + valaddr_reg:x7; val_offset:526*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 526*FLEN/8, x11, x1, x6) + +inst_288: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1ab and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1ab and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x71ab; op2val:0x71ab; + valaddr_reg:x7; val_offset:528*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 528*FLEN/8, x11, x1, x6) + +inst_289: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1ab and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1ab and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x71ab; op2val:0x71ab; + valaddr_reg:x7; val_offset:530*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 530*FLEN/8, x11, x1, x6) + +inst_290: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2e2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ae2; op2val:0x7ae2; + valaddr_reg:x7; val_offset:532*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 532*FLEN/8, x11, x1, x6) + +inst_291: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2e2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ae2; op2val:0x7ae2; + valaddr_reg:x7; val_offset:534*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 534*FLEN/8, x11, x1, x6) + +inst_292: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2e2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ae2; op2val:0x7ae2; + valaddr_reg:x7; val_offset:536*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 536*FLEN/8, x11, x1, x6) + +inst_293: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2e2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ae2; op2val:0x7ae2; + valaddr_reg:x7; val_offset:538*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 538*FLEN/8, x11, x1, x6) + +inst_294: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2e2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ae2; op2val:0x7ae2; + valaddr_reg:x7; val_offset:540*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 540*FLEN/8, x11, x1, x6) + +inst_295: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x25f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a5f; op2val:0x7a5f; + valaddr_reg:x7; val_offset:542*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 542*FLEN/8, x11, x1, x6) + +inst_296: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x25f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a5f; op2val:0x7a5f; + valaddr_reg:x7; val_offset:544*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 544*FLEN/8, x11, x1, x6) + +inst_297: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x25f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a5f; op2val:0x7a5f; + valaddr_reg:x7; val_offset:546*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 546*FLEN/8, x11, x1, x6) + +inst_298: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x25f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a5f; op2val:0x7a5f; + valaddr_reg:x7; val_offset:548*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 548*FLEN/8, x11, x1, x6) + +inst_299: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x25f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a5f; op2val:0x7a5f; + valaddr_reg:x7; val_offset:550*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 550*FLEN/8, x11, x1, x6) + +inst_300: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x015 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x015 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7415; op2val:0x7415; + valaddr_reg:x7; val_offset:552*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 552*FLEN/8, x11, x1, x6) + +inst_301: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x015 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x015 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7415; op2val:0x7415; + valaddr_reg:x7; val_offset:554*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 554*FLEN/8, x11, x1, x6) + +inst_302: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x015 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x015 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7415; op2val:0x7415; + valaddr_reg:x7; val_offset:556*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 556*FLEN/8, x11, x1, x6) + +inst_303: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x015 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x015 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7415; op2val:0x7415; + valaddr_reg:x7; val_offset:558*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 558*FLEN/8, x11, x1, x6) + +inst_304: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x015 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x015 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7415; op2val:0x7415; + valaddr_reg:x7; val_offset:560*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 560*FLEN/8, x11, x1, x6) + +inst_305: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x161 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x161 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7961; op2val:0x7961; + valaddr_reg:x7; val_offset:562*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 562*FLEN/8, x11, x1, x6) + +inst_306: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x161 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x161 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7961; op2val:0x7961; + valaddr_reg:x7; val_offset:564*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 564*FLEN/8, x11, x1, x6) + +inst_307: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x161 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x161 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7961; op2val:0x7961; + valaddr_reg:x7; val_offset:566*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 566*FLEN/8, x11, x1, x6) + +inst_308: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x161 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x161 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7961; op2val:0x7961; + valaddr_reg:x7; val_offset:568*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 568*FLEN/8, x11, x1, x6) + +inst_309: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x161 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x161 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7961; op2val:0x7961; + valaddr_reg:x7; val_offset:570*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 570*FLEN/8, x11, x1, x6) + +inst_310: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x046 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x046 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6446; op2val:0x6446; + valaddr_reg:x7; val_offset:572*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 572*FLEN/8, x11, x1, x6) + +inst_311: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x046 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x046 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6446; op2val:0x6446; + valaddr_reg:x7; val_offset:574*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 574*FLEN/8, x11, x1, x6) + +inst_312: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x046 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x046 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6446; op2val:0x6446; + valaddr_reg:x7; val_offset:576*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 576*FLEN/8, x11, x1, x6) + +inst_313: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x046 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x046 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6446; op2val:0x6446; + valaddr_reg:x7; val_offset:578*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 578*FLEN/8, x11, x1, x6) + +inst_314: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x046 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x046 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6446; op2val:0x6446; + valaddr_reg:x7; val_offset:580*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 580*FLEN/8, x11, x1, x6) + +inst_315: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a0a; op2val:0x7a0a; + valaddr_reg:x7; val_offset:582*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 582*FLEN/8, x11, x1, x6) + +inst_316: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a0a; op2val:0x7a0a; + valaddr_reg:x7; val_offset:584*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 584*FLEN/8, x11, x1, x6) + +inst_317: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a0a; op2val:0x7a0a; + valaddr_reg:x7; val_offset:586*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 586*FLEN/8, x11, x1, x6) + +inst_318: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a0a; op2val:0x7a0a; + valaddr_reg:x7; val_offset:588*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 588*FLEN/8, x11, x1, x6) + +inst_319: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a0a; op2val:0x7a0a; + valaddr_reg:x7; val_offset:590*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 590*FLEN/8, x11, x1, x6) + +inst_320: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x301 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x301 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f01; op2val:0x6f01; + valaddr_reg:x7; val_offset:592*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 592*FLEN/8, x11, x1, x6) + +inst_321: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x301 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x301 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f01; op2val:0x6f01; + valaddr_reg:x7; val_offset:594*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 594*FLEN/8, x11, x1, x6) + +inst_322: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x301 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x301 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f01; op2val:0x6f01; + valaddr_reg:x7; val_offset:596*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 596*FLEN/8, x11, x1, x6) + +inst_323: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x301 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x301 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f01; op2val:0x6f01; + valaddr_reg:x7; val_offset:598*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 598*FLEN/8, x11, x1, x6) + +inst_324: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x301 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x301 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f01; op2val:0x6f01; + valaddr_reg:x7; val_offset:600*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 600*FLEN/8, x11, x1, x6) + +inst_325: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x182 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x182 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7582; op2val:0x7582; + valaddr_reg:x7; val_offset:602*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 602*FLEN/8, x11, x1, x6) + +inst_326: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x182 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x182 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7582; op2val:0x7582; + valaddr_reg:x7; val_offset:604*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 604*FLEN/8, x11, x1, x6) + +inst_327: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x182 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x182 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7582; op2val:0x7582; + valaddr_reg:x7; val_offset:606*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 606*FLEN/8, x11, x1, x6) + +inst_328: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x182 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x182 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7582; op2val:0x7582; + valaddr_reg:x7; val_offset:608*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 608*FLEN/8, x11, x1, x6) + +inst_329: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x182 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x182 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7582; op2val:0x7582; + valaddr_reg:x7; val_offset:610*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 610*FLEN/8, x11, x1, x6) + +inst_330: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x11b and fs2 == 0 and fe2 == 0x1c and fm2 == 0x11b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x711b; op2val:0x711b; + valaddr_reg:x7; val_offset:612*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 612*FLEN/8, x11, x1, x6) + +inst_331: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x11b and fs2 == 0 and fe2 == 0x1c and fm2 == 0x11b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x711b; op2val:0x711b; + valaddr_reg:x7; val_offset:614*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 614*FLEN/8, x11, x1, x6) + +inst_332: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x11b and fs2 == 0 and fe2 == 0x1c and fm2 == 0x11b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x711b; op2val:0x711b; + valaddr_reg:x7; val_offset:616*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 616*FLEN/8, x11, x1, x6) + +inst_333: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x11b and fs2 == 0 and fe2 == 0x1c and fm2 == 0x11b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x711b; op2val:0x711b; + valaddr_reg:x7; val_offset:618*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 618*FLEN/8, x11, x1, x6) + +inst_334: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x11b and fs2 == 0 and fe2 == 0x1c and fm2 == 0x11b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x711b; op2val:0x711b; + valaddr_reg:x7; val_offset:620*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 620*FLEN/8, x11, x1, x6) + +inst_335: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x160 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x160 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7160; op2val:0x7160; + valaddr_reg:x7; val_offset:622*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 622*FLEN/8, x11, x1, x6) + +inst_336: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x160 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x160 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7160; op2val:0x7160; + valaddr_reg:x7; val_offset:624*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 624*FLEN/8, x11, x1, x6) + +inst_337: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x160 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x160 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7160; op2val:0x7160; + valaddr_reg:x7; val_offset:626*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 626*FLEN/8, x11, x1, x6) + +inst_338: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x160 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x160 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7160; op2val:0x7160; + valaddr_reg:x7; val_offset:628*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 628*FLEN/8, x11, x1, x6) + +inst_339: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x160 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x160 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7160; op2val:0x7160; + valaddr_reg:x7; val_offset:630*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 630*FLEN/8, x11, x1, x6) + +inst_340: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1b0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b0; op2val:0x79b0; + valaddr_reg:x7; val_offset:632*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 632*FLEN/8, x11, x1, x6) + +inst_341: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1b0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b0; op2val:0x79b0; + valaddr_reg:x7; val_offset:634*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 634*FLEN/8, x11, x1, x6) + +inst_342: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1b0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b0; op2val:0x79b0; + valaddr_reg:x7; val_offset:636*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 636*FLEN/8, x11, x1, x6) + +inst_343: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1b0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b0; op2val:0x79b0; + valaddr_reg:x7; val_offset:638*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 638*FLEN/8, x11, x1, x6) + +inst_344: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1b0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b0; op2val:0x79b0; + valaddr_reg:x7; val_offset:640*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 640*FLEN/8, x11, x1, x6) + +inst_345: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x126 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x126 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7526; op2val:0x7526; + valaddr_reg:x7; val_offset:642*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 642*FLEN/8, x11, x1, x6) + +inst_346: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x126 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x126 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7526; op2val:0x7526; + valaddr_reg:x7; val_offset:644*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 644*FLEN/8, x11, x1, x6) + +inst_347: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x126 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x126 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7526; op2val:0x7526; + valaddr_reg:x7; val_offset:646*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 646*FLEN/8, x11, x1, x6) + +inst_348: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x126 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x126 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7526; op2val:0x7526; + valaddr_reg:x7; val_offset:648*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 648*FLEN/8, x11, x1, x6) + +inst_349: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x126 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x126 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7526; op2val:0x7526; + valaddr_reg:x7; val_offset:650*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 650*FLEN/8, x11, x1, x6) + +inst_350: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x20d and fs2 == 0 and fe2 == 0x19 and fm2 == 0x20d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x660d; op2val:0x660d; + valaddr_reg:x7; val_offset:652*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 652*FLEN/8, x11, x1, x6) + +inst_351: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x20d and fs2 == 0 and fe2 == 0x19 and fm2 == 0x20d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x660d; op2val:0x660d; + valaddr_reg:x7; val_offset:654*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 654*FLEN/8, x11, x1, x6) + +inst_352: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x20d and fs2 == 0 and fe2 == 0x19 and fm2 == 0x20d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x660d; op2val:0x660d; + valaddr_reg:x7; val_offset:656*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 656*FLEN/8, x11, x1, x6) + +inst_353: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x20d and fs2 == 0 and fe2 == 0x19 and fm2 == 0x20d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x660d; op2val:0x660d; + valaddr_reg:x7; val_offset:658*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 658*FLEN/8, x11, x1, x6) + +inst_354: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x20d and fs2 == 0 and fe2 == 0x19 and fm2 == 0x20d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x660d; op2val:0x660d; + valaddr_reg:x7; val_offset:660*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 660*FLEN/8, x11, x1, x6) + +inst_355: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2bb and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2bb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x76bb; op2val:0x76bb; + valaddr_reg:x7; val_offset:662*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 662*FLEN/8, x11, x1, x6) + +inst_356: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2bb and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2bb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x76bb; op2val:0x76bb; + valaddr_reg:x7; val_offset:664*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 664*FLEN/8, x11, x1, x6) + +inst_357: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2bb and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2bb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x76bb; op2val:0x76bb; + valaddr_reg:x7; val_offset:666*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 666*FLEN/8, x11, x1, x6) + +inst_358: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2bb and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2bb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x76bb; op2val:0x76bb; + valaddr_reg:x7; val_offset:668*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 668*FLEN/8, x11, x1, x6) + +inst_359: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2bb and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2bb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x76bb; op2val:0x76bb; + valaddr_reg:x7; val_offset:670*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 670*FLEN/8, x11, x1, x6) + +inst_360: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2f5 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2f5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ef5; op2val:0x6ef5; + valaddr_reg:x7; val_offset:672*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 672*FLEN/8, x11, x1, x6) + +inst_361: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2f5 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2f5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ef5; op2val:0x6ef5; + valaddr_reg:x7; val_offset:674*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 674*FLEN/8, x11, x1, x6) + +inst_362: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2f5 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2f5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ef5; op2val:0x6ef5; + valaddr_reg:x7; val_offset:676*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 676*FLEN/8, x11, x1, x6) + +inst_363: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2f5 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2f5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ef5; op2val:0x6ef5; + valaddr_reg:x7; val_offset:678*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 678*FLEN/8, x11, x1, x6) + +inst_364: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2f5 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2f5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ef5; op2val:0x6ef5; + valaddr_reg:x7; val_offset:680*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 680*FLEN/8, x11, x1, x6) + +inst_365: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x014 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x014 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7814; op2val:0x7814; + valaddr_reg:x7; val_offset:682*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 682*FLEN/8, x11, x1, x6) + +inst_366: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x014 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x014 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7814; op2val:0x7814; + valaddr_reg:x7; val_offset:684*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 684*FLEN/8, x11, x1, x6) + +inst_367: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x014 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x014 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7814; op2val:0x7814; + valaddr_reg:x7; val_offset:686*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 686*FLEN/8, x11, x1, x6) + +inst_368: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x014 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x014 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7814; op2val:0x7814; + valaddr_reg:x7; val_offset:688*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 688*FLEN/8, x11, x1, x6) + +inst_369: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x014 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x014 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7814; op2val:0x7814; + valaddr_reg:x7; val_offset:690*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 690*FLEN/8, x11, x1, x6) + +inst_370: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0d7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x78d7; op2val:0x78d7; + valaddr_reg:x7; val_offset:692*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 692*FLEN/8, x11, x1, x6) + +inst_371: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0d7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x78d7; op2val:0x78d7; + valaddr_reg:x7; val_offset:694*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 694*FLEN/8, x11, x1, x6) + +inst_372: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0d7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x78d7; op2val:0x78d7; + valaddr_reg:x7; val_offset:696*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 696*FLEN/8, x11, x1, x6) + +inst_373: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0d7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x78d7; op2val:0x78d7; + valaddr_reg:x7; val_offset:698*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 698*FLEN/8, x11, x1, x6) + +inst_374: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0d7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x78d7; op2val:0x78d7; + valaddr_reg:x7; val_offset:700*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 700*FLEN/8, x11, x1, x6) + +inst_375: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x154 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x154 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6554; op2val:0x6554; + valaddr_reg:x7; val_offset:702*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 702*FLEN/8, x11, x1, x6) + +inst_376: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x154 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x154 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6554; op2val:0x6554; + valaddr_reg:x7; val_offset:704*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 704*FLEN/8, x11, x1, x6) + +inst_377: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x154 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x154 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6554; op2val:0x6554; + valaddr_reg:x7; val_offset:706*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 706*FLEN/8, x11, x1, x6) + +inst_378: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x154 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x154 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6554; op2val:0x6554; + valaddr_reg:x7; val_offset:708*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 708*FLEN/8, x11, x1, x6) + +inst_379: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x154 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x154 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6554; op2val:0x6554; + valaddr_reg:x7; val_offset:710*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 710*FLEN/8, x11, x1, x6) + +inst_380: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0af and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0af and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x70af; op2val:0x70af; + valaddr_reg:x7; val_offset:712*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 712*FLEN/8, x11, x1, x6) + +inst_381: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0af and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0af and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x70af; op2val:0x70af; + valaddr_reg:x7; val_offset:714*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 714*FLEN/8, x11, x1, x6) + +inst_382: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0af and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0af and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x70af; op2val:0x70af; + valaddr_reg:x7; val_offset:716*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 716*FLEN/8, x11, x1, x6) + +inst_383: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0af and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0af and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x70af; op2val:0x70af; + valaddr_reg:x7; val_offset:718*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 718*FLEN/8, x11, x1, x6) + +inst_384: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0af and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0af and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x70af; op2val:0x70af; + valaddr_reg:x7; val_offset:720*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 720*FLEN/8, x11, x1, x6) + +inst_385: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x120 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x120 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7120; op2val:0x7120; + valaddr_reg:x7; val_offset:722*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 722*FLEN/8, x11, x1, x6) + +inst_386: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x120 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x120 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7120; op2val:0x7120; + valaddr_reg:x7; val_offset:724*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 724*FLEN/8, x11, x1, x6) + +inst_387: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x120 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x120 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7120; op2val:0x7120; + valaddr_reg:x7; val_offset:726*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 726*FLEN/8, x11, x1, x6) + +inst_388: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x120 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x120 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7120; op2val:0x7120; + valaddr_reg:x7; val_offset:728*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 728*FLEN/8, x11, x1, x6) + +inst_389: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x120 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x120 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7120; op2val:0x7120; + valaddr_reg:x7; val_offset:730*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 730*FLEN/8, x11, x1, x6) + +inst_390: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x16c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x16c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x796c; op2val:0x796c; + valaddr_reg:x7; val_offset:732*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 732*FLEN/8, x11, x1, x6) + +inst_391: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x16c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x16c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x796c; op2val:0x796c; + valaddr_reg:x7; val_offset:734*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 734*FLEN/8, x11, x1, x6) + +inst_392: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x16c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x16c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x796c; op2val:0x796c; + valaddr_reg:x7; val_offset:736*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 736*FLEN/8, x11, x1, x6) + +inst_393: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x16c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x16c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x796c; op2val:0x796c; + valaddr_reg:x7; val_offset:738*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 738*FLEN/8, x11, x1, x6) + +inst_394: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x16c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x16c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x796c; op2val:0x796c; + valaddr_reg:x7; val_offset:740*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 740*FLEN/8, x11, x1, x6) + +inst_395: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x30e and fs2 == 0 and fe2 == 0x1c and fm2 == 0x30e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x730e; op2val:0x730e; + valaddr_reg:x7; val_offset:742*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 742*FLEN/8, x11, x1, x6) + +inst_396: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x30e and fs2 == 0 and fe2 == 0x1c and fm2 == 0x30e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x730e; op2val:0x730e; + valaddr_reg:x7; val_offset:744*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 744*FLEN/8, x11, x1, x6) + +inst_397: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x30e and fs2 == 0 and fe2 == 0x1c and fm2 == 0x30e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x730e; op2val:0x730e; + valaddr_reg:x7; val_offset:746*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 746*FLEN/8, x11, x1, x6) + +inst_398: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x30e and fs2 == 0 and fe2 == 0x1c and fm2 == 0x30e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x730e; op2val:0x730e; + valaddr_reg:x7; val_offset:748*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 748*FLEN/8, x11, x1, x6) + +inst_399: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x30e and fs2 == 0 and fe2 == 0x1c and fm2 == 0x30e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x730e; op2val:0x730e; + valaddr_reg:x7; val_offset:750*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 750*FLEN/8, x11, x1, x6) + +inst_400: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x261 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x261 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a61; op2val:0x7a61; + valaddr_reg:x7; val_offset:752*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 752*FLEN/8, x11, x1, x6) + +inst_401: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x261 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x261 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a61; op2val:0x7a61; + valaddr_reg:x7; val_offset:754*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 754*FLEN/8, x11, x1, x6) + +inst_402: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x261 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x261 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a61; op2val:0x7a61; + valaddr_reg:x7; val_offset:756*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 756*FLEN/8, x11, x1, x6) + +inst_403: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x261 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x261 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a61; op2val:0x7a61; + valaddr_reg:x7; val_offset:758*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 758*FLEN/8, x11, x1, x6) + +inst_404: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x261 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x261 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a61; op2val:0x7a61; + valaddr_reg:x7; val_offset:760*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 760*FLEN/8, x11, x1, x6) + +inst_405: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x323 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x323 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7323; op2val:0x7323; + valaddr_reg:x7; val_offset:762*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 762*FLEN/8, x11, x1, x6) + +inst_406: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x323 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x323 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7323; op2val:0x7323; + valaddr_reg:x7; val_offset:764*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 764*FLEN/8, x11, x1, x6) + +inst_407: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x323 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x323 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7323; op2val:0x7323; + valaddr_reg:x7; val_offset:766*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 766*FLEN/8, x11, x1, x6) + +inst_408: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x323 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x323 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7323; op2val:0x7323; + valaddr_reg:x7; val_offset:768*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 768*FLEN/8, x11, x1, x6) + +inst_409: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x323 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x323 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7323; op2val:0x7323; + valaddr_reg:x7; val_offset:770*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 770*FLEN/8, x11, x1, x6) +RVTEST_SIGBASE(x1,signature_x1_5) + +inst_410: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x250 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x250 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7650; op2val:0x7650; + valaddr_reg:x7; val_offset:772*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 772*FLEN/8, x11, x1, x6) + +inst_411: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x250 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x250 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7650; op2val:0x7650; + valaddr_reg:x7; val_offset:774*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 774*FLEN/8, x11, x1, x6) + +inst_412: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x250 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x250 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7650; op2val:0x7650; + valaddr_reg:x7; val_offset:776*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 776*FLEN/8, x11, x1, x6) + +inst_413: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x250 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x250 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7650; op2val:0x7650; + valaddr_reg:x7; val_offset:778*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 778*FLEN/8, x11, x1, x6) + +inst_414: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x250 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x250 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7650; op2val:0x7650; + valaddr_reg:x7; val_offset:780*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 780*FLEN/8, x11, x1, x6) + +inst_415: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x123 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x123 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7523; op2val:0x7523; + valaddr_reg:x7; val_offset:782*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 782*FLEN/8, x11, x1, x6) + +inst_416: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x123 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x123 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7523; op2val:0x7523; + valaddr_reg:x7; val_offset:784*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 784*FLEN/8, x11, x1, x6) + +inst_417: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x123 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x123 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7523; op2val:0x7523; + valaddr_reg:x7; val_offset:786*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 786*FLEN/8, x11, x1, x6) + +inst_418: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x123 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x123 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7523; op2val:0x7523; + valaddr_reg:x7; val_offset:788*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 788*FLEN/8, x11, x1, x6) + +inst_419: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x123 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x123 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7523; op2val:0x7523; + valaddr_reg:x7; val_offset:790*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 790*FLEN/8, x11, x1, x6) + +inst_420: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x385 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x385 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6b85; op2val:0x6b85; + valaddr_reg:x7; val_offset:792*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 792*FLEN/8, x11, x1, x6) + +inst_421: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x385 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x385 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6b85; op2val:0x6b85; + valaddr_reg:x7; val_offset:794*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 794*FLEN/8, x11, x1, x6) + +inst_422: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x385 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x385 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6b85; op2val:0x6b85; + valaddr_reg:x7; val_offset:796*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 796*FLEN/8, x11, x1, x6) + +inst_423: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x385 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x385 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6b85; op2val:0x6b85; + valaddr_reg:x7; val_offset:798*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 798*FLEN/8, x11, x1, x6) + +inst_424: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x385 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x385 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6b85; op2val:0x6b85; + valaddr_reg:x7; val_offset:800*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 800*FLEN/8, x11, x1, x6) + +inst_425: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3bd and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3bd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bbd; op2val:0x7bbd; + valaddr_reg:x7; val_offset:802*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 802*FLEN/8, x11, x1, x6) + +inst_426: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3bd and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3bd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bbd; op2val:0x7bbd; + valaddr_reg:x7; val_offset:804*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 804*FLEN/8, x11, x1, x6) + +inst_427: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3bd and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3bd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bbd; op2val:0x7bbd; + valaddr_reg:x7; val_offset:806*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 806*FLEN/8, x11, x1, x6) + +inst_428: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3bd and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3bd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bbd; op2val:0x7bbd; + valaddr_reg:x7; val_offset:808*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 808*FLEN/8, x11, x1, x6) + +inst_429: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3bd and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3bd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bbd; op2val:0x7bbd; + valaddr_reg:x7; val_offset:810*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 810*FLEN/8, x11, x1, x6) + +inst_430: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0e6 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0e6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74e6; op2val:0x74e6; + valaddr_reg:x7; val_offset:812*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 812*FLEN/8, x11, x1, x6) + +inst_431: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0e6 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0e6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74e6; op2val:0x74e6; + valaddr_reg:x7; val_offset:814*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 814*FLEN/8, x11, x1, x6) + +inst_432: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0e6 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0e6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74e6; op2val:0x74e6; + valaddr_reg:x7; val_offset:816*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 816*FLEN/8, x11, x1, x6) + +inst_433: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0e6 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0e6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74e6; op2val:0x74e6; + valaddr_reg:x7; val_offset:818*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 818*FLEN/8, x11, x1, x6) + +inst_434: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0e6 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0e6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74e6; op2val:0x74e6; + valaddr_reg:x7; val_offset:820*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 820*FLEN/8, x11, x1, x6) + +inst_435: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f6 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0f6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74f6; op2val:0x74f6; + valaddr_reg:x7; val_offset:822*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 822*FLEN/8, x11, x1, x6) + +inst_436: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f6 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0f6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74f6; op2val:0x74f6; + valaddr_reg:x7; val_offset:824*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 824*FLEN/8, x11, x1, x6) + +inst_437: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f6 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0f6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74f6; op2val:0x74f6; + valaddr_reg:x7; val_offset:826*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 826*FLEN/8, x11, x1, x6) + +inst_438: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f6 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0f6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74f6; op2val:0x74f6; + valaddr_reg:x7; val_offset:828*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 828*FLEN/8, x11, x1, x6) + +inst_439: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f6 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0f6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74f6; op2val:0x74f6; + valaddr_reg:x7; val_offset:830*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 830*FLEN/8, x11, x1, x6) + +inst_440: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1f2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79f2; op2val:0x79f2; + valaddr_reg:x7; val_offset:832*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 832*FLEN/8, x11, x1, x6) + +inst_441: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1f2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79f2; op2val:0x79f2; + valaddr_reg:x7; val_offset:834*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 834*FLEN/8, x11, x1, x6) + +inst_442: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1f2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79f2; op2val:0x79f2; + valaddr_reg:x7; val_offset:836*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 836*FLEN/8, x11, x1, x6) + +inst_443: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1f2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79f2; op2val:0x79f2; + valaddr_reg:x7; val_offset:838*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 838*FLEN/8, x11, x1, x6) + +inst_444: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1f2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79f2; op2val:0x79f2; + valaddr_reg:x7; val_offset:840*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 840*FLEN/8, x11, x1, x6) + +inst_445: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x009 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x009 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7409; op2val:0x7409; + valaddr_reg:x7; val_offset:842*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 842*FLEN/8, x11, x1, x6) + +inst_446: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x009 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x009 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7409; op2val:0x7409; + valaddr_reg:x7; val_offset:844*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 844*FLEN/8, x11, x1, x6) + +inst_447: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x009 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x009 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7409; op2val:0x7409; + valaddr_reg:x7; val_offset:846*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 846*FLEN/8, x11, x1, x6) + +inst_448: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x009 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x009 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7409; op2val:0x7409; + valaddr_reg:x7; val_offset:848*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 848*FLEN/8, x11, x1, x6) + +inst_449: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x009 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x009 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7409; op2val:0x7409; + valaddr_reg:x7; val_offset:850*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 850*FLEN/8, x11, x1, x6) + +inst_450: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x306 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x306 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b06; op2val:0x7b06; + valaddr_reg:x7; val_offset:852*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 852*FLEN/8, x11, x1, x6) + +inst_451: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x306 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x306 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b06; op2val:0x7b06; + valaddr_reg:x7; val_offset:854*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 854*FLEN/8, x11, x1, x6) + +inst_452: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x306 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x306 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b06; op2val:0x7b06; + valaddr_reg:x7; val_offset:856*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 856*FLEN/8, x11, x1, x6) + +inst_453: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x306 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x306 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b06; op2val:0x7b06; + valaddr_reg:x7; val_offset:858*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 858*FLEN/8, x11, x1, x6) + +inst_454: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x306 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x306 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b06; op2val:0x7b06; + valaddr_reg:x7; val_offset:860*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 860*FLEN/8, x11, x1, x6) + +inst_455: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x28d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a8d; op2val:0x7a8d; + valaddr_reg:x7; val_offset:862*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 862*FLEN/8, x11, x1, x6) + +inst_456: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x28d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a8d; op2val:0x7a8d; + valaddr_reg:x7; val_offset:864*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 864*FLEN/8, x11, x1, x6) + +inst_457: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x28d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a8d; op2val:0x7a8d; + valaddr_reg:x7; val_offset:866*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 866*FLEN/8, x11, x1, x6) + +inst_458: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x28d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a8d; op2val:0x7a8d; + valaddr_reg:x7; val_offset:868*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 868*FLEN/8, x11, x1, x6) + +inst_459: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x28d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a8d; op2val:0x7a8d; + valaddr_reg:x7; val_offset:870*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 870*FLEN/8, x11, x1, x6) + +inst_460: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x08f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x08f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x788f; op2val:0x788f; + valaddr_reg:x7; val_offset:872*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 872*FLEN/8, x11, x1, x6) + +inst_461: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x08f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x08f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x788f; op2val:0x788f; + valaddr_reg:x7; val_offset:874*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 874*FLEN/8, x11, x1, x6) + +inst_462: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x08f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x08f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x788f; op2val:0x788f; + valaddr_reg:x7; val_offset:876*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 876*FLEN/8, x11, x1, x6) + +inst_463: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x08f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x08f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x788f; op2val:0x788f; + valaddr_reg:x7; val_offset:878*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 878*FLEN/8, x11, x1, x6) + +inst_464: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x08f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x08f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x788f; op2val:0x788f; + valaddr_reg:x7; val_offset:880*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 880*FLEN/8, x11, x1, x6) + +inst_465: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7af0; op2val:0x7af0; + valaddr_reg:x7; val_offset:882*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 882*FLEN/8, x11, x1, x6) + +inst_466: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2f0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7af0; op2val:0x7af0; + valaddr_reg:x7; val_offset:884*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 884*FLEN/8, x11, x1, x6) + +inst_467: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2f0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7af0; op2val:0x7af0; + valaddr_reg:x7; val_offset:886*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 886*FLEN/8, x11, x1, x6) + +inst_468: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2f0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7af0; op2val:0x7af0; + valaddr_reg:x7; val_offset:888*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 888*FLEN/8, x11, x1, x6) + +inst_469: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2f0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7af0; op2val:0x7af0; + valaddr_reg:x7; val_offset:890*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 890*FLEN/8, x11, x1, x6) + +inst_470: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1a1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79a1; op2val:0x79a1; + valaddr_reg:x7; val_offset:892*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 892*FLEN/8, x11, x1, x6) + +inst_471: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1a1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79a1; op2val:0x79a1; + valaddr_reg:x7; val_offset:894*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 894*FLEN/8, x11, x1, x6) + +inst_472: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1a1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79a1; op2val:0x79a1; + valaddr_reg:x7; val_offset:896*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 896*FLEN/8, x11, x1, x6) + +inst_473: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1a1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79a1; op2val:0x79a1; + valaddr_reg:x7; val_offset:898*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 898*FLEN/8, x11, x1, x6) + +inst_474: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1a1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79a1; op2val:0x79a1; + valaddr_reg:x7; val_offset:900*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 900*FLEN/8, x11, x1, x6) + +inst_475: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x20b and fs2 == 0 and fe2 == 0x1d and fm2 == 0x20b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x760b; op2val:0x760b; + valaddr_reg:x7; val_offset:902*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 902*FLEN/8, x11, x1, x6) + +inst_476: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x20b and fs2 == 0 and fe2 == 0x1d and fm2 == 0x20b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x760b; op2val:0x760b; + valaddr_reg:x7; val_offset:904*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 904*FLEN/8, x11, x1, x6) + +inst_477: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x20b and fs2 == 0 and fe2 == 0x1d and fm2 == 0x20b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x760b; op2val:0x760b; + valaddr_reg:x7; val_offset:906*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 906*FLEN/8, x11, x1, x6) + +inst_478: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x20b and fs2 == 0 and fe2 == 0x1d and fm2 == 0x20b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x760b; op2val:0x760b; + valaddr_reg:x7; val_offset:908*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 908*FLEN/8, x11, x1, x6) + +inst_479: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x20b and fs2 == 0 and fe2 == 0x1d and fm2 == 0x20b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x760b; op2val:0x760b; + valaddr_reg:x7; val_offset:910*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 910*FLEN/8, x11, x1, x6) + +inst_480: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x294 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x294 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7294; op2val:0x7294; + valaddr_reg:x7; val_offset:912*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 912*FLEN/8, x11, x1, x6) + +inst_481: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x294 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x294 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7294; op2val:0x7294; + valaddr_reg:x7; val_offset:914*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 914*FLEN/8, x11, x1, x6) + +inst_482: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x294 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x294 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7294; op2val:0x7294; + valaddr_reg:x7; val_offset:916*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 916*FLEN/8, x11, x1, x6) + +inst_483: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x294 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x294 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7294; op2val:0x7294; + valaddr_reg:x7; val_offset:918*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 918*FLEN/8, x11, x1, x6) + +inst_484: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x294 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x294 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7294; op2val:0x7294; + valaddr_reg:x7; val_offset:920*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 920*FLEN/8, x11, x1, x6) + +inst_485: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2ec and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2ec and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x76ec; op2val:0x76ec; + valaddr_reg:x7; val_offset:922*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 922*FLEN/8, x11, x1, x6) + +inst_486: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2ec and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2ec and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x76ec; op2val:0x76ec; + valaddr_reg:x7; val_offset:924*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 924*FLEN/8, x11, x1, x6) + +inst_487: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2ec and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2ec and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x76ec; op2val:0x76ec; + valaddr_reg:x7; val_offset:926*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 926*FLEN/8, x11, x1, x6) + +inst_488: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2ec and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2ec and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x76ec; op2val:0x76ec; + valaddr_reg:x7; val_offset:928*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 928*FLEN/8, x11, x1, x6) + +inst_489: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2ec and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2ec and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x76ec; op2val:0x76ec; + valaddr_reg:x7; val_offset:930*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 930*FLEN/8, x11, x1, x6) + +inst_490: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2ae and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6eae; op2val:0x6eae; + valaddr_reg:x7; val_offset:932*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 932*FLEN/8, x11, x1, x6) + +inst_491: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2ae and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6eae; op2val:0x6eae; + valaddr_reg:x7; val_offset:934*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 934*FLEN/8, x11, x1, x6) + +inst_492: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2ae and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6eae; op2val:0x6eae; + valaddr_reg:x7; val_offset:936*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 936*FLEN/8, x11, x1, x6) + +inst_493: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2ae and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6eae; op2val:0x6eae; + valaddr_reg:x7; val_offset:938*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 938*FLEN/8, x11, x1, x6) + +inst_494: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2ae and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6eae; op2val:0x6eae; + valaddr_reg:x7; val_offset:940*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 940*FLEN/8, x11, x1, x6) + +inst_495: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0bc and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0bc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74bc; op2val:0x74bc; + valaddr_reg:x7; val_offset:942*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 942*FLEN/8, x11, x1, x6) + +inst_496: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0bc and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0bc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74bc; op2val:0x74bc; + valaddr_reg:x7; val_offset:944*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 944*FLEN/8, x11, x1, x6) + +inst_497: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0bc and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0bc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74bc; op2val:0x74bc; + valaddr_reg:x7; val_offset:946*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 946*FLEN/8, x11, x1, x6) + +inst_498: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0bc and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0bc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74bc; op2val:0x74bc; + valaddr_reg:x7; val_offset:948*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 948*FLEN/8, x11, x1, x6) + +inst_499: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0bc and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0bc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74bc; op2val:0x74bc; + valaddr_reg:x7; val_offset:950*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 950*FLEN/8, x11, x1, x6) + +inst_500: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x134 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x134 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7534; op2val:0x7534; + valaddr_reg:x7; val_offset:952*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 952*FLEN/8, x11, x1, x6) + +inst_501: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x134 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x134 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7534; op2val:0x7534; + valaddr_reg:x7; val_offset:954*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 954*FLEN/8, x11, x1, x6) + +inst_502: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x134 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x134 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7534; op2val:0x7534; + valaddr_reg:x7; val_offset:956*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 956*FLEN/8, x11, x1, x6) + +inst_503: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x134 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x134 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7534; op2val:0x7534; + valaddr_reg:x7; val_offset:958*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 958*FLEN/8, x11, x1, x6) + +inst_504: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x134 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x134 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7534; op2val:0x7534; + valaddr_reg:x7; val_offset:960*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 960*FLEN/8, x11, x1, x6) + +inst_505: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x331 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x331 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b31; op2val:0x7b31; + valaddr_reg:x7; val_offset:962*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 962*FLEN/8, x11, x1, x6) + +inst_506: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x331 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x331 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b31; op2val:0x7b31; + valaddr_reg:x7; val_offset:964*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 964*FLEN/8, x11, x1, x6) + +inst_507: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x331 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x331 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b31; op2val:0x7b31; + valaddr_reg:x7; val_offset:966*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 966*FLEN/8, x11, x1, x6) + +inst_508: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x331 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x331 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b31; op2val:0x7b31; + valaddr_reg:x7; val_offset:968*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 968*FLEN/8, x11, x1, x6) + +inst_509: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x331 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x331 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b31; op2val:0x7b31; + valaddr_reg:x7; val_offset:970*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 970*FLEN/8, x11, x1, x6) + +inst_510: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x26c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x26c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x726c; op2val:0x726c; + valaddr_reg:x7; val_offset:972*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 972*FLEN/8, x11, x1, x6) + +inst_511: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x26c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x26c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x726c; op2val:0x726c; + valaddr_reg:x7; val_offset:974*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 974*FLEN/8, x11, x1, x6) + +inst_512: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x26c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x26c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x726c; op2val:0x726c; + valaddr_reg:x7; val_offset:976*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 976*FLEN/8, x11, x1, x6) + +inst_513: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x26c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x26c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x726c; op2val:0x726c; + valaddr_reg:x7; val_offset:978*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 978*FLEN/8, x11, x1, x6) + +inst_514: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x26c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x26c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x726c; op2val:0x726c; + valaddr_reg:x7; val_offset:980*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 980*FLEN/8, x11, x1, x6) + +inst_515: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3e4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7be4; op2val:0x7be4; + valaddr_reg:x7; val_offset:982*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 982*FLEN/8, x11, x1, x6) + +inst_516: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3e4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7be4; op2val:0x7be4; + valaddr_reg:x7; val_offset:984*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 984*FLEN/8, x11, x1, x6) + +inst_517: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3e4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7be4; op2val:0x7be4; + valaddr_reg:x7; val_offset:986*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 986*FLEN/8, x11, x1, x6) + +inst_518: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3e4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7be4; op2val:0x7be4; + valaddr_reg:x7; val_offset:988*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 988*FLEN/8, x11, x1, x6) + +inst_519: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3e4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7be4; op2val:0x7be4; + valaddr_reg:x7; val_offset:990*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 990*FLEN/8, x11, x1, x6) + +inst_520: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x16c and fs2 == 0 and fe2 == 0x1d and fm2 == 0x16c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x756c; op2val:0x756c; + valaddr_reg:x7; val_offset:992*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 992*FLEN/8, x11, x1, x6) + +inst_521: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x16c and fs2 == 0 and fe2 == 0x1d and fm2 == 0x16c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x756c; op2val:0x756c; + valaddr_reg:x7; val_offset:994*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 994*FLEN/8, x11, x1, x6) + +inst_522: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x16c and fs2 == 0 and fe2 == 0x1d and fm2 == 0x16c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x756c; op2val:0x756c; + valaddr_reg:x7; val_offset:996*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 996*FLEN/8, x11, x1, x6) + +inst_523: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x16c and fs2 == 0 and fe2 == 0x1d and fm2 == 0x16c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x756c; op2val:0x756c; + valaddr_reg:x7; val_offset:998*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 998*FLEN/8, x11, x1, x6) + +inst_524: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x16c and fs2 == 0 and fe2 == 0x1d and fm2 == 0x16c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x756c; op2val:0x756c; + valaddr_reg:x7; val_offset:1000*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1000*FLEN/8, x11, x1, x6) + +inst_525: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x164 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x164 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7964; op2val:0x7964; + valaddr_reg:x7; val_offset:1002*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1002*FLEN/8, x11, x1, x6) + +inst_526: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x164 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x164 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7964; op2val:0x7964; + valaddr_reg:x7; val_offset:1004*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1004*FLEN/8, x11, x1, x6) + +inst_527: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x164 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x164 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7964; op2val:0x7964; + valaddr_reg:x7; val_offset:1006*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1006*FLEN/8, x11, x1, x6) + +inst_528: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x164 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x164 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7964; op2val:0x7964; + valaddr_reg:x7; val_offset:1008*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1008*FLEN/8, x11, x1, x6) + +inst_529: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x164 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x164 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7964; op2val:0x7964; + valaddr_reg:x7; val_offset:1010*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1010*FLEN/8, x11, x1, x6) + +inst_530: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x374 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x374 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b74; op2val:0x7b74; + valaddr_reg:x7; val_offset:1012*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1012*FLEN/8, x11, x1, x6) + +inst_531: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x374 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x374 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b74; op2val:0x7b74; + valaddr_reg:x7; val_offset:1014*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1014*FLEN/8, x11, x1, x6) + +inst_532: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x374 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x374 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b74; op2val:0x7b74; + valaddr_reg:x7; val_offset:1016*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1016*FLEN/8, x11, x1, x6) + +inst_533: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x374 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x374 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b74; op2val:0x7b74; + valaddr_reg:x7; val_offset:1018*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1018*FLEN/8, x11, x1, x6) + +inst_534: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x374 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x374 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b74; op2val:0x7b74; + valaddr_reg:x7; val_offset:1020*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1020*FLEN/8, x11, x1, x6) + +inst_535: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3bf and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3bf and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x77bf; op2val:0x77bf; + valaddr_reg:x7; val_offset:1022*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1022*FLEN/8, x11, x1, x6) + +inst_536: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3bf and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3bf and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x77bf; op2val:0x77bf; + valaddr_reg:x7; val_offset:1024*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1024*FLEN/8, x11, x1, x6) + +inst_537: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3bf and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3bf and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x77bf; op2val:0x77bf; + valaddr_reg:x7; val_offset:1026*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1026*FLEN/8, x11, x1, x6) +RVTEST_SIGBASE(x1,signature_x1_6) + +inst_538: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3bf and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3bf and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x77bf; op2val:0x77bf; + valaddr_reg:x7; val_offset:1028*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1028*FLEN/8, x11, x1, x6) + +inst_539: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3bf and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3bf and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x77bf; op2val:0x77bf; + valaddr_reg:x7; val_offset:1030*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1030*FLEN/8, x11, x1, x6) + +inst_540: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x381 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x381 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7381; op2val:0x7381; + valaddr_reg:x7; val_offset:1032*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1032*FLEN/8, x11, x1, x6) + +inst_541: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x381 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x381 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7381; op2val:0x7381; + valaddr_reg:x7; val_offset:1034*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1034*FLEN/8, x11, x1, x6) + +inst_542: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x381 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x381 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7381; op2val:0x7381; + valaddr_reg:x7; val_offset:1036*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1036*FLEN/8, x11, x1, x6) + +inst_543: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x381 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x381 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7381; op2val:0x7381; + valaddr_reg:x7; val_offset:1038*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1038*FLEN/8, x11, x1, x6) + +inst_544: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x381 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x381 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7381; op2val:0x7381; + valaddr_reg:x7; val_offset:1040*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1040*FLEN/8, x11, x1, x6) + +inst_545: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x16a and fs2 == 0 and fe2 == 0x1b and fm2 == 0x16a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d6a; op2val:0x6d6a; + valaddr_reg:x7; val_offset:1042*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1042*FLEN/8, x11, x1, x6) + +inst_546: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x16a and fs2 == 0 and fe2 == 0x1b and fm2 == 0x16a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d6a; op2val:0x6d6a; + valaddr_reg:x7; val_offset:1044*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1044*FLEN/8, x11, x1, x6) + +inst_547: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x16a and fs2 == 0 and fe2 == 0x1b and fm2 == 0x16a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d6a; op2val:0x6d6a; + valaddr_reg:x7; val_offset:1046*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1046*FLEN/8, x11, x1, x6) + +inst_548: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x16a and fs2 == 0 and fe2 == 0x1b and fm2 == 0x16a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d6a; op2val:0x6d6a; + valaddr_reg:x7; val_offset:1048*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1048*FLEN/8, x11, x1, x6) + +inst_549: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x16a and fs2 == 0 and fe2 == 0x1b and fm2 == 0x16a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d6a; op2val:0x6d6a; + valaddr_reg:x7; val_offset:1050*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1050*FLEN/8, x11, x1, x6) + +inst_550: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x348 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x348 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b48; op2val:0x7b48; + valaddr_reg:x7; val_offset:1052*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1052*FLEN/8, x11, x1, x6) + +inst_551: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x348 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x348 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b48; op2val:0x7b48; + valaddr_reg:x7; val_offset:1054*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1054*FLEN/8, x11, x1, x6) + +inst_552: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x348 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x348 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b48; op2val:0x7b48; + valaddr_reg:x7; val_offset:1056*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1056*FLEN/8, x11, x1, x6) + +inst_553: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x348 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x348 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b48; op2val:0x7b48; + valaddr_reg:x7; val_offset:1058*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1058*FLEN/8, x11, x1, x6) + +inst_554: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x348 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x348 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b48; op2val:0x7b48; + valaddr_reg:x7; val_offset:1060*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1060*FLEN/8, x11, x1, x6) + +inst_555: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x211 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x211 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a11; op2val:0x7a11; + valaddr_reg:x7; val_offset:1062*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1062*FLEN/8, x11, x1, x6) + +inst_556: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x211 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x211 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a11; op2val:0x7a11; + valaddr_reg:x7; val_offset:1064*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1064*FLEN/8, x11, x1, x6) + +inst_557: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x211 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x211 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a11; op2val:0x7a11; + valaddr_reg:x7; val_offset:1066*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1066*FLEN/8, x11, x1, x6) + +inst_558: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x211 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x211 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a11; op2val:0x7a11; + valaddr_reg:x7; val_offset:1068*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1068*FLEN/8, x11, x1, x6) + +inst_559: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x211 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x211 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a11; op2val:0x7a11; + valaddr_reg:x7; val_offset:1070*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1070*FLEN/8, x11, x1, x6) + +inst_560: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab9; op2val:0x7ab9; + valaddr_reg:x7; val_offset:1072*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1072*FLEN/8, x11, x1, x6) + +inst_561: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab9; op2val:0x7ab9; + valaddr_reg:x7; val_offset:1074*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1074*FLEN/8, x11, x1, x6) + +inst_562: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab9; op2val:0x7ab9; + valaddr_reg:x7; val_offset:1076*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1076*FLEN/8, x11, x1, x6) + +inst_563: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab9; op2val:0x7ab9; + valaddr_reg:x7; val_offset:1078*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1078*FLEN/8, x11, x1, x6) + +inst_564: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab9; op2val:0x7ab9; + valaddr_reg:x7; val_offset:1080*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1080*FLEN/8, x11, x1, x6) + +inst_565: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x171 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x171 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7571; op2val:0x7571; + valaddr_reg:x7; val_offset:1082*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1082*FLEN/8, x11, x1, x6) + +inst_566: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x171 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x171 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7571; op2val:0x7571; + valaddr_reg:x7; val_offset:1084*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1084*FLEN/8, x11, x1, x6) + +inst_567: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x171 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x171 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7571; op2val:0x7571; + valaddr_reg:x7; val_offset:1086*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1086*FLEN/8, x11, x1, x6) + +inst_568: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x171 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x171 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7571; op2val:0x7571; + valaddr_reg:x7; val_offset:1088*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1088*FLEN/8, x11, x1, x6) + +inst_569: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x171 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x171 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7571; op2val:0x7571; + valaddr_reg:x7; val_offset:1090*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1090*FLEN/8, x11, x1, x6) + +inst_570: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ef and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aef; op2val:0x7aef; + valaddr_reg:x7; val_offset:1092*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1092*FLEN/8, x11, x1, x6) + +inst_571: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ef and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aef; op2val:0x7aef; + valaddr_reg:x7; val_offset:1094*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1094*FLEN/8, x11, x1, x6) + +inst_572: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ef and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aef; op2val:0x7aef; + valaddr_reg:x7; val_offset:1096*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1096*FLEN/8, x11, x1, x6) + +inst_573: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ef and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aef; op2val:0x7aef; + valaddr_reg:x7; val_offset:1098*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1098*FLEN/8, x11, x1, x6) + +inst_574: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ef and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aef; op2val:0x7aef; + valaddr_reg:x7; val_offset:1100*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1100*FLEN/8, x11, x1, x6) + +inst_575: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3a1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba1; op2val:0x7ba1; + valaddr_reg:x7; val_offset:1102*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1102*FLEN/8, x11, x1, x6) + +inst_576: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3a1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba1; op2val:0x7ba1; + valaddr_reg:x7; val_offset:1104*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1104*FLEN/8, x11, x1, x6) + +inst_577: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3a1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba1; op2val:0x7ba1; + valaddr_reg:x7; val_offset:1106*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1106*FLEN/8, x11, x1, x6) + +inst_578: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3a1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba1; op2val:0x7ba1; + valaddr_reg:x7; val_offset:1108*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1108*FLEN/8, x11, x1, x6) + +inst_579: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3a1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba1; op2val:0x7ba1; + valaddr_reg:x7; val_offset:1110*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1110*FLEN/8, x11, x1, x6) + +inst_580: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x054 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x054 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7054; op2val:0x7054; + valaddr_reg:x7; val_offset:1112*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1112*FLEN/8, x11, x1, x6) + +inst_581: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x054 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x054 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7054; op2val:0x7054; + valaddr_reg:x7; val_offset:1114*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1114*FLEN/8, x11, x1, x6) + +inst_582: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x054 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x054 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7054; op2val:0x7054; + valaddr_reg:x7; val_offset:1116*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1116*FLEN/8, x11, x1, x6) + +inst_583: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x054 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x054 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7054; op2val:0x7054; + valaddr_reg:x7; val_offset:1118*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1118*FLEN/8, x11, x1, x6) + +inst_584: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x054 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x054 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7054; op2val:0x7054; + valaddr_reg:x7; val_offset:1120*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1120*FLEN/8, x11, x1, x6) + +inst_585: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2ab and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2ab and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6eab; op2val:0x6eab; + valaddr_reg:x7; val_offset:1122*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1122*FLEN/8, x11, x1, x6) + +inst_586: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2ab and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2ab and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6eab; op2val:0x6eab; + valaddr_reg:x7; val_offset:1124*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1124*FLEN/8, x11, x1, x6) + +inst_587: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2ab and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2ab and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6eab; op2val:0x6eab; + valaddr_reg:x7; val_offset:1126*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1126*FLEN/8, x11, x1, x6) + +inst_588: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2ab and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2ab and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6eab; op2val:0x6eab; + valaddr_reg:x7; val_offset:1128*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1128*FLEN/8, x11, x1, x6) + +inst_589: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2ab and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2ab and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6eab; op2val:0x6eab; + valaddr_reg:x7; val_offset:1130*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1130*FLEN/8, x11, x1, x6) + +inst_590: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0ae and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0ae and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6cae; op2val:0x6cae; + valaddr_reg:x7; val_offset:1132*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1132*FLEN/8, x11, x1, x6) + +inst_591: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0ae and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0ae and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6cae; op2val:0x6cae; + valaddr_reg:x7; val_offset:1134*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1134*FLEN/8, x11, x1, x6) + +inst_592: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0ae and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0ae and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6cae; op2val:0x6cae; + valaddr_reg:x7; val_offset:1136*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1136*FLEN/8, x11, x1, x6) + +inst_593: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0ae and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0ae and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6cae; op2val:0x6cae; + valaddr_reg:x7; val_offset:1138*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1138*FLEN/8, x11, x1, x6) + +inst_594: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0ae and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0ae and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6cae; op2val:0x6cae; + valaddr_reg:x7; val_offset:1140*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1140*FLEN/8, x11, x1, x6) + +inst_595: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x24d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x24d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a4d; op2val:0x7a4d; + valaddr_reg:x7; val_offset:1142*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1142*FLEN/8, x11, x1, x6) + +inst_596: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x24d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x24d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a4d; op2val:0x7a4d; + valaddr_reg:x7; val_offset:1144*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1144*FLEN/8, x11, x1, x6) + +inst_597: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x24d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x24d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a4d; op2val:0x7a4d; + valaddr_reg:x7; val_offset:1146*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1146*FLEN/8, x11, x1, x6) + +inst_598: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x24d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x24d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a4d; op2val:0x7a4d; + valaddr_reg:x7; val_offset:1148*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1148*FLEN/8, x11, x1, x6) + +inst_599: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x24d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x24d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a4d; op2val:0x7a4d; + valaddr_reg:x7; val_offset:1150*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1150*FLEN/8, x11, x1, x6) + +inst_600: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x173 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x173 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7573; op2val:0x7573; + valaddr_reg:x7; val_offset:1152*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1152*FLEN/8, x11, x1, x6) + +inst_601: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x173 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x173 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7573; op2val:0x7573; + valaddr_reg:x7; val_offset:1154*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1154*FLEN/8, x11, x1, x6) + +inst_602: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x173 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x173 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7573; op2val:0x7573; + valaddr_reg:x7; val_offset:1156*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1156*FLEN/8, x11, x1, x6) + +inst_603: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x173 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x173 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7573; op2val:0x7573; + valaddr_reg:x7; val_offset:1158*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1158*FLEN/8, x11, x1, x6) + +inst_604: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x173 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x173 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7573; op2val:0x7573; + valaddr_reg:x7; val_offset:1160*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1160*FLEN/8, x11, x1, x6) + +inst_605: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x240 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x240 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a40; op2val:0x7a40; + valaddr_reg:x7; val_offset:1162*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1162*FLEN/8, x11, x1, x6) + +inst_606: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x240 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x240 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a40; op2val:0x7a40; + valaddr_reg:x7; val_offset:1164*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1164*FLEN/8, x11, x1, x6) + +inst_607: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x240 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x240 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a40; op2val:0x7a40; + valaddr_reg:x7; val_offset:1166*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1166*FLEN/8, x11, x1, x6) + +inst_608: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x240 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x240 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a40; op2val:0x7a40; + valaddr_reg:x7; val_offset:1168*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1168*FLEN/8, x11, x1, x6) + +inst_609: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x240 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x240 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a40; op2val:0x7a40; + valaddr_reg:x7; val_offset:1170*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1170*FLEN/8, x11, x1, x6) + +inst_610: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x090 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x090 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7890; op2val:0x7890; + valaddr_reg:x7; val_offset:1172*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1172*FLEN/8, x11, x1, x6) + +inst_611: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x090 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x090 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7890; op2val:0x7890; + valaddr_reg:x7; val_offset:1174*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1174*FLEN/8, x11, x1, x6) + +inst_612: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x090 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x090 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7890; op2val:0x7890; + valaddr_reg:x7; val_offset:1176*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1176*FLEN/8, x11, x1, x6) + +inst_613: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x090 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x090 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7890; op2val:0x7890; + valaddr_reg:x7; val_offset:1178*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1178*FLEN/8, x11, x1, x6) + +inst_614: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x090 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x090 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7890; op2val:0x7890; + valaddr_reg:x7; val_offset:1180*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1180*FLEN/8, x11, x1, x6) + +inst_615: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x13a and fs2 == 0 and fe2 == 0x1b and fm2 == 0x13a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d3a; op2val:0x6d3a; + valaddr_reg:x7; val_offset:1182*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1182*FLEN/8, x11, x1, x6) + +inst_616: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x13a and fs2 == 0 and fe2 == 0x1b and fm2 == 0x13a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d3a; op2val:0x6d3a; + valaddr_reg:x7; val_offset:1184*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1184*FLEN/8, x11, x1, x6) + +inst_617: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x13a and fs2 == 0 and fe2 == 0x1b and fm2 == 0x13a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d3a; op2val:0x6d3a; + valaddr_reg:x7; val_offset:1186*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1186*FLEN/8, x11, x1, x6) + +inst_618: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x13a and fs2 == 0 and fe2 == 0x1b and fm2 == 0x13a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d3a; op2val:0x6d3a; + valaddr_reg:x7; val_offset:1188*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1188*FLEN/8, x11, x1, x6) + +inst_619: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x13a and fs2 == 0 and fe2 == 0x1b and fm2 == 0x13a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d3a; op2val:0x6d3a; + valaddr_reg:x7; val_offset:1190*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1190*FLEN/8, x11, x1, x6) + +inst_620: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x31f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x31f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b1f; op2val:0x7b1f; + valaddr_reg:x7; val_offset:1192*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1192*FLEN/8, x11, x1, x6) + +inst_621: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x31f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x31f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b1f; op2val:0x7b1f; + valaddr_reg:x7; val_offset:1194*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1194*FLEN/8, x11, x1, x6) + +inst_622: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x31f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x31f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b1f; op2val:0x7b1f; + valaddr_reg:x7; val_offset:1196*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1196*FLEN/8, x11, x1, x6) + +inst_623: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x31f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x31f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b1f; op2val:0x7b1f; + valaddr_reg:x7; val_offset:1198*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1198*FLEN/8, x11, x1, x6) + +inst_624: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x31f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x31f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b1f; op2val:0x7b1f; + valaddr_reg:x7; val_offset:1200*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1200*FLEN/8, x11, x1, x6) + +inst_625: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x365 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x365 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b65; op2val:0x7b65; + valaddr_reg:x7; val_offset:1202*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1202*FLEN/8, x11, x1, x6) + +inst_626: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x365 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x365 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b65; op2val:0x7b65; + valaddr_reg:x7; val_offset:1204*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1204*FLEN/8, x11, x1, x6) + +inst_627: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x365 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x365 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b65; op2val:0x7b65; + valaddr_reg:x7; val_offset:1206*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1206*FLEN/8, x11, x1, x6) + +inst_628: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x365 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x365 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b65; op2val:0x7b65; + valaddr_reg:x7; val_offset:1208*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1208*FLEN/8, x11, x1, x6) + +inst_629: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x365 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x365 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b65; op2val:0x7b65; + valaddr_reg:x7; val_offset:1210*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1210*FLEN/8, x11, x1, x6) + +inst_630: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x06e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x06e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x746e; op2val:0x746e; + valaddr_reg:x7; val_offset:1212*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1212*FLEN/8, x11, x1, x6) + +inst_631: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x06e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x06e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x746e; op2val:0x746e; + valaddr_reg:x7; val_offset:1214*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1214*FLEN/8, x11, x1, x6) + +inst_632: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x06e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x06e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x746e; op2val:0x746e; + valaddr_reg:x7; val_offset:1216*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1216*FLEN/8, x11, x1, x6) + +inst_633: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x06e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x06e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x746e; op2val:0x746e; + valaddr_reg:x7; val_offset:1218*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1218*FLEN/8, x11, x1, x6) + +inst_634: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x06e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x06e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x746e; op2val:0x746e; + valaddr_reg:x7; val_offset:1220*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1220*FLEN/8, x11, x1, x6) + +inst_635: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x29e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x29e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a9e; op2val:0x7a9e; + valaddr_reg:x7; val_offset:1222*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1222*FLEN/8, x11, x1, x6) + +inst_636: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x29e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x29e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a9e; op2val:0x7a9e; + valaddr_reg:x7; val_offset:1224*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1224*FLEN/8, x11, x1, x6) + +inst_637: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x29e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x29e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a9e; op2val:0x7a9e; + valaddr_reg:x7; val_offset:1226*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1226*FLEN/8, x11, x1, x6) + +inst_638: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x29e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x29e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a9e; op2val:0x7a9e; + valaddr_reg:x7; val_offset:1228*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1228*FLEN/8, x11, x1, x6) + +inst_639: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x29e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x29e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a9e; op2val:0x7a9e; + valaddr_reg:x7; val_offset:1230*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1230*FLEN/8, x11, x1, x6) + +inst_640: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x15c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x795c; op2val:0x795c; + valaddr_reg:x7; val_offset:1232*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1232*FLEN/8, x11, x1, x6) + +inst_641: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x15c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x795c; op2val:0x795c; + valaddr_reg:x7; val_offset:1234*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1234*FLEN/8, x11, x1, x6) + +inst_642: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x15c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x795c; op2val:0x795c; + valaddr_reg:x7; val_offset:1236*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1236*FLEN/8, x11, x1, x6) + +inst_643: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x15c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x795c; op2val:0x795c; + valaddr_reg:x7; val_offset:1238*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1238*FLEN/8, x11, x1, x6) + +inst_644: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x15c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x795c; op2val:0x795c; + valaddr_reg:x7; val_offset:1240*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1240*FLEN/8, x11, x1, x6) + +inst_645: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x35d and fs2 == 0 and fe2 == 0x1b and fm2 == 0x35d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f5d; op2val:0x6f5d; + valaddr_reg:x7; val_offset:1242*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1242*FLEN/8, x11, x1, x6) + +inst_646: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x35d and fs2 == 0 and fe2 == 0x1b and fm2 == 0x35d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f5d; op2val:0x6f5d; + valaddr_reg:x7; val_offset:1244*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1244*FLEN/8, x11, x1, x6) + +inst_647: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x35d and fs2 == 0 and fe2 == 0x1b and fm2 == 0x35d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f5d; op2val:0x6f5d; + valaddr_reg:x7; val_offset:1246*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1246*FLEN/8, x11, x1, x6) + +inst_648: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x35d and fs2 == 0 and fe2 == 0x1b and fm2 == 0x35d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f5d; op2val:0x6f5d; + valaddr_reg:x7; val_offset:1248*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1248*FLEN/8, x11, x1, x6) + +inst_649: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x35d and fs2 == 0 and fe2 == 0x1b and fm2 == 0x35d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f5d; op2val:0x6f5d; + valaddr_reg:x7; val_offset:1250*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1250*FLEN/8, x11, x1, x6) + +inst_650: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x11f and fs2 == 0 and fe2 == 0x1a and fm2 == 0x11f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x691f; op2val:0x691f; + valaddr_reg:x7; val_offset:1252*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1252*FLEN/8, x11, x1, x6) + +inst_651: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x11f and fs2 == 0 and fe2 == 0x1a and fm2 == 0x11f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x691f; op2val:0x691f; + valaddr_reg:x7; val_offset:1254*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1254*FLEN/8, x11, x1, x6) + +inst_652: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x11f and fs2 == 0 and fe2 == 0x1a and fm2 == 0x11f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x691f; op2val:0x691f; + valaddr_reg:x7; val_offset:1256*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1256*FLEN/8, x11, x1, x6) + +inst_653: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x11f and fs2 == 0 and fe2 == 0x1a and fm2 == 0x11f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x691f; op2val:0x691f; + valaddr_reg:x7; val_offset:1258*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1258*FLEN/8, x11, x1, x6) + +inst_654: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x11f and fs2 == 0 and fe2 == 0x1a and fm2 == 0x11f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x691f; op2val:0x691f; + valaddr_reg:x7; val_offset:1260*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1260*FLEN/8, x11, x1, x6) + +inst_655: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3e6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7be6; op2val:0x7be6; + valaddr_reg:x7; val_offset:1262*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1262*FLEN/8, x11, x1, x6) + +inst_656: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3e6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7be6; op2val:0x7be6; + valaddr_reg:x7; val_offset:1264*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1264*FLEN/8, x11, x1, x6) + +inst_657: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3e6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7be6; op2val:0x7be6; + valaddr_reg:x7; val_offset:1266*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1266*FLEN/8, x11, x1, x6) + +inst_658: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3e6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7be6; op2val:0x7be6; + valaddr_reg:x7; val_offset:1268*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1268*FLEN/8, x11, x1, x6) + +inst_659: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3e6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7be6; op2val:0x7be6; + valaddr_reg:x7; val_offset:1270*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1270*FLEN/8, x11, x1, x6) + +inst_660: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x364 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x364 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f64; op2val:0x6f64; + valaddr_reg:x7; val_offset:1272*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1272*FLEN/8, x11, x1, x6) + +inst_661: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x364 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x364 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f64; op2val:0x6f64; + valaddr_reg:x7; val_offset:1274*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1274*FLEN/8, x11, x1, x6) + +inst_662: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x364 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x364 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f64; op2val:0x6f64; + valaddr_reg:x7; val_offset:1276*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1276*FLEN/8, x11, x1, x6) + +inst_663: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x364 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x364 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f64; op2val:0x6f64; + valaddr_reg:x7; val_offset:1278*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1278*FLEN/8, x11, x1, x6) + +inst_664: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x364 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x364 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f64; op2val:0x6f64; + valaddr_reg:x7; val_offset:1280*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1280*FLEN/8, x11, x1, x6) + +inst_665: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3b8 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3b8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x73b8; op2val:0x73b8; + valaddr_reg:x7; val_offset:1282*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1282*FLEN/8, x11, x1, x6) +RVTEST_SIGBASE(x1,signature_x1_7) + +inst_666: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3b8 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3b8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x73b8; op2val:0x73b8; + valaddr_reg:x7; val_offset:1284*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1284*FLEN/8, x11, x1, x6) + +inst_667: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3b8 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3b8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x73b8; op2val:0x73b8; + valaddr_reg:x7; val_offset:1286*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1286*FLEN/8, x11, x1, x6) + +inst_668: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3b8 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3b8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x73b8; op2val:0x73b8; + valaddr_reg:x7; val_offset:1288*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1288*FLEN/8, x11, x1, x6) + +inst_669: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3b8 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3b8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x73b8; op2val:0x73b8; + valaddr_reg:x7; val_offset:1290*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1290*FLEN/8, x11, x1, x6) + +inst_670: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x294 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x294 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e94; op2val:0x6e94; + valaddr_reg:x7; val_offset:1292*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1292*FLEN/8, x11, x1, x6) + +inst_671: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x294 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x294 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e94; op2val:0x6e94; + valaddr_reg:x7; val_offset:1294*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1294*FLEN/8, x11, x1, x6) + +inst_672: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x294 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x294 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e94; op2val:0x6e94; + valaddr_reg:x7; val_offset:1296*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1296*FLEN/8, x11, x1, x6) + +inst_673: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x294 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x294 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e94; op2val:0x6e94; + valaddr_reg:x7; val_offset:1298*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1298*FLEN/8, x11, x1, x6) + +inst_674: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x294 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x294 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e94; op2val:0x6e94; + valaddr_reg:x7; val_offset:1300*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1300*FLEN/8, x11, x1, x6) + +inst_675: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x20c and fs2 == 0 and fe2 == 0x1d and fm2 == 0x20c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x760c; op2val:0x760c; + valaddr_reg:x7; val_offset:1302*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1302*FLEN/8, x11, x1, x6) + +inst_676: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x20c and fs2 == 0 and fe2 == 0x1d and fm2 == 0x20c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x760c; op2val:0x760c; + valaddr_reg:x7; val_offset:1304*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1304*FLEN/8, x11, x1, x6) + +inst_677: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x20c and fs2 == 0 and fe2 == 0x1d and fm2 == 0x20c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x760c; op2val:0x760c; + valaddr_reg:x7; val_offset:1306*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1306*FLEN/8, x11, x1, x6) + +inst_678: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x20c and fs2 == 0 and fe2 == 0x1d and fm2 == 0x20c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x760c; op2val:0x760c; + valaddr_reg:x7; val_offset:1308*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1308*FLEN/8, x11, x1, x6) + +inst_679: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x20c and fs2 == 0 and fe2 == 0x1d and fm2 == 0x20c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x760c; op2val:0x760c; + valaddr_reg:x7; val_offset:1310*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1310*FLEN/8, x11, x1, x6) + +inst_680: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x345 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x345 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b45; op2val:0x7b45; + valaddr_reg:x7; val_offset:1312*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1312*FLEN/8, x11, x1, x6) + +inst_681: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x345 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x345 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b45; op2val:0x7b45; + valaddr_reg:x7; val_offset:1314*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1314*FLEN/8, x11, x1, x6) + +inst_682: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x345 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x345 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b45; op2val:0x7b45; + valaddr_reg:x7; val_offset:1316*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1316*FLEN/8, x11, x1, x6) + +inst_683: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x345 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x345 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b45; op2val:0x7b45; + valaddr_reg:x7; val_offset:1318*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1318*FLEN/8, x11, x1, x6) + +inst_684: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x345 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x345 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b45; op2val:0x7b45; + valaddr_reg:x7; val_offset:1320*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1320*FLEN/8, x11, x1, x6) + +inst_685: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x00d and fs2 == 0 and fe2 == 0x1d and fm2 == 0x00d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x740d; op2val:0x740d; + valaddr_reg:x7; val_offset:1322*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1322*FLEN/8, x11, x1, x6) + +inst_686: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x00d and fs2 == 0 and fe2 == 0x1d and fm2 == 0x00d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x740d; op2val:0x740d; + valaddr_reg:x7; val_offset:1324*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1324*FLEN/8, x11, x1, x6) + +inst_687: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x00d and fs2 == 0 and fe2 == 0x1d and fm2 == 0x00d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x740d; op2val:0x740d; + valaddr_reg:x7; val_offset:1326*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1326*FLEN/8, x11, x1, x6) + +inst_688: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x00d and fs2 == 0 and fe2 == 0x1d and fm2 == 0x00d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x740d; op2val:0x740d; + valaddr_reg:x7; val_offset:1328*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1328*FLEN/8, x11, x1, x6) + +inst_689: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x00d and fs2 == 0 and fe2 == 0x1d and fm2 == 0x00d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x740d; op2val:0x740d; + valaddr_reg:x7; val_offset:1330*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1330*FLEN/8, x11, x1, x6) + +inst_690: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x267 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x267 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e67; op2val:0x6e67; + valaddr_reg:x7; val_offset:1332*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1332*FLEN/8, x11, x1, x6) + +inst_691: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x267 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x267 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e67; op2val:0x6e67; + valaddr_reg:x7; val_offset:1334*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1334*FLEN/8, x11, x1, x6) + +inst_692: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x267 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x267 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e67; op2val:0x6e67; + valaddr_reg:x7; val_offset:1336*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1336*FLEN/8, x11, x1, x6) + +inst_693: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x267 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x267 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e67; op2val:0x6e67; + valaddr_reg:x7; val_offset:1338*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1338*FLEN/8, x11, x1, x6) + +inst_694: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x267 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x267 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e67; op2val:0x6e67; + valaddr_reg:x7; val_offset:1340*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1340*FLEN/8, x11, x1, x6) + +inst_695: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x112 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x112 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6912; op2val:0x6912; + valaddr_reg:x7; val_offset:1342*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1342*FLEN/8, x11, x1, x6) + +inst_696: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x112 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x112 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6912; op2val:0x6912; + valaddr_reg:x7; val_offset:1344*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1344*FLEN/8, x11, x1, x6) + +inst_697: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x112 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x112 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6912; op2val:0x6912; + valaddr_reg:x7; val_offset:1346*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1346*FLEN/8, x11, x1, x6) + +inst_698: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x112 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x112 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6912; op2val:0x6912; + valaddr_reg:x7; val_offset:1348*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1348*FLEN/8, x11, x1, x6) + +inst_699: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x112 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x112 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6912; op2val:0x6912; + valaddr_reg:x7; val_offset:1350*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1350*FLEN/8, x11, x1, x6) + +inst_700: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3db and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3db and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bdb; op2val:0x7bdb; + valaddr_reg:x7; val_offset:1352*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1352*FLEN/8, x11, x1, x6) + +inst_701: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3db and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3db and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bdb; op2val:0x7bdb; + valaddr_reg:x7; val_offset:1354*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1354*FLEN/8, x11, x1, x6) + +inst_702: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3db and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3db and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bdb; op2val:0x7bdb; + valaddr_reg:x7; val_offset:1356*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1356*FLEN/8, x11, x1, x6) + +inst_703: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3db and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3db and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bdb; op2val:0x7bdb; + valaddr_reg:x7; val_offset:1358*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1358*FLEN/8, x11, x1, x6) + +inst_704: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3db and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3db and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bdb; op2val:0x7bdb; + valaddr_reg:x7; val_offset:1360*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1360*FLEN/8, x11, x1, x6) + +inst_705: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0c5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x78c5; op2val:0x78c5; + valaddr_reg:x7; val_offset:1362*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1362*FLEN/8, x11, x1, x6) + +inst_706: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0c5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x78c5; op2val:0x78c5; + valaddr_reg:x7; val_offset:1364*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1364*FLEN/8, x11, x1, x6) + +inst_707: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0c5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x78c5; op2val:0x78c5; + valaddr_reg:x7; val_offset:1366*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1366*FLEN/8, x11, x1, x6) + +inst_708: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0c5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x78c5; op2val:0x78c5; + valaddr_reg:x7; val_offset:1368*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1368*FLEN/8, x11, x1, x6) + +inst_709: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0c5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x78c5; op2val:0x78c5; + valaddr_reg:x7; val_offset:1370*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1370*FLEN/8, x11, x1, x6) + +inst_710: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x102 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x102 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7502; op2val:0x7502; + valaddr_reg:x7; val_offset:1372*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1372*FLEN/8, x11, x1, x6) + +inst_711: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x102 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x102 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7502; op2val:0x7502; + valaddr_reg:x7; val_offset:1374*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1374*FLEN/8, x11, x1, x6) + +inst_712: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x102 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x102 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7502; op2val:0x7502; + valaddr_reg:x7; val_offset:1376*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1376*FLEN/8, x11, x1, x6) + +inst_713: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x102 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x102 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7502; op2val:0x7502; + valaddr_reg:x7; val_offset:1378*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1378*FLEN/8, x11, x1, x6) + +inst_714: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x102 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x102 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7502; op2val:0x7502; + valaddr_reg:x7; val_offset:1380*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1380*FLEN/8, x11, x1, x6) + +inst_715: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x34d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x34d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b4d; op2val:0x7b4d; + valaddr_reg:x7; val_offset:1382*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1382*FLEN/8, x11, x1, x6) + +inst_716: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x34d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x34d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b4d; op2val:0x7b4d; + valaddr_reg:x7; val_offset:1384*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1384*FLEN/8, x11, x1, x6) + +inst_717: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x34d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x34d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b4d; op2val:0x7b4d; + valaddr_reg:x7; val_offset:1386*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1386*FLEN/8, x11, x1, x6) + +inst_718: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x34d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x34d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b4d; op2val:0x7b4d; + valaddr_reg:x7; val_offset:1388*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1388*FLEN/8, x11, x1, x6) + +inst_719: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x34d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x34d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b4d; op2val:0x7b4d; + valaddr_reg:x7; val_offset:1390*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1390*FLEN/8, x11, x1, x6) + +inst_720: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3c1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bc1; op2val:0x7bc1; + valaddr_reg:x7; val_offset:1392*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1392*FLEN/8, x11, x1, x6) + +inst_721: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3c1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bc1; op2val:0x7bc1; + valaddr_reg:x7; val_offset:1394*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1394*FLEN/8, x11, x1, x6) + +inst_722: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3c1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bc1; op2val:0x7bc1; + valaddr_reg:x7; val_offset:1396*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1396*FLEN/8, x11, x1, x6) + +inst_723: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3c1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bc1; op2val:0x7bc1; + valaddr_reg:x7; val_offset:1398*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1398*FLEN/8, x11, x1, x6) + +inst_724: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3c1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bc1; op2val:0x7bc1; + valaddr_reg:x7; val_offset:1400*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1400*FLEN/8, x11, x1, x6) + +inst_725: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2e2 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2e2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x72e2; op2val:0x72e2; + valaddr_reg:x7; val_offset:1402*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1402*FLEN/8, x11, x1, x6) + +inst_726: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2e2 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2e2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x72e2; op2val:0x72e2; + valaddr_reg:x7; val_offset:1404*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1404*FLEN/8, x11, x1, x6) + +inst_727: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2e2 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2e2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x72e2; op2val:0x72e2; + valaddr_reg:x7; val_offset:1406*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1406*FLEN/8, x11, x1, x6) + +inst_728: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2e2 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2e2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x72e2; op2val:0x72e2; + valaddr_reg:x7; val_offset:1408*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1408*FLEN/8, x11, x1, x6) + +inst_729: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2e2 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2e2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x72e2; op2val:0x72e2; + valaddr_reg:x7; val_offset:1410*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1410*FLEN/8, x11, x1, x6) + +inst_730: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3d5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bd5; op2val:0x7bd5; + valaddr_reg:x7; val_offset:1412*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1412*FLEN/8, x11, x1, x6) + +inst_731: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3d5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bd5; op2val:0x7bd5; + valaddr_reg:x7; val_offset:1414*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1414*FLEN/8, x11, x1, x6) + +inst_732: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3d5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bd5; op2val:0x7bd5; + valaddr_reg:x7; val_offset:1416*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1416*FLEN/8, x11, x1, x6) + +inst_733: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3d5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bd5; op2val:0x7bd5; + valaddr_reg:x7; val_offset:1418*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1418*FLEN/8, x11, x1, x6) + +inst_734: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3d5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bd5; op2val:0x7bd5; + valaddr_reg:x7; val_offset:1420*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1420*FLEN/8, x11, x1, x6) + +inst_735: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x180 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x180 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7980; op2val:0x7980; + valaddr_reg:x7; val_offset:1422*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1422*FLEN/8, x11, x1, x6) + +inst_736: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x180 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x180 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7980; op2val:0x7980; + valaddr_reg:x7; val_offset:1424*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1424*FLEN/8, x11, x1, x6) + +inst_737: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x180 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x180 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7980; op2val:0x7980; + valaddr_reg:x7; val_offset:1426*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1426*FLEN/8, x11, x1, x6) + +inst_738: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x180 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x180 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7980; op2val:0x7980; + valaddr_reg:x7; val_offset:1428*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1428*FLEN/8, x11, x1, x6) + +inst_739: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x180 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x180 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7980; op2val:0x7980; + valaddr_reg:x7; val_offset:1430*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1430*FLEN/8, x11, x1, x6) + +inst_740: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x024 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x024 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7424; op2val:0x7424; + valaddr_reg:x7; val_offset:1432*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1432*FLEN/8, x11, x1, x6) + +inst_741: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x024 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x024 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7424; op2val:0x7424; + valaddr_reg:x7; val_offset:1434*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1434*FLEN/8, x11, x1, x6) + +inst_742: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x024 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x024 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7424; op2val:0x7424; + valaddr_reg:x7; val_offset:1436*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1436*FLEN/8, x11, x1, x6) + +inst_743: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x024 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x024 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7424; op2val:0x7424; + valaddr_reg:x7; val_offset:1438*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1438*FLEN/8, x11, x1, x6) + +inst_744: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x024 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x024 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7424; op2val:0x7424; + valaddr_reg:x7; val_offset:1440*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1440*FLEN/8, x11, x1, x6) + +inst_745: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ea and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0ea and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74ea; op2val:0x74ea; + valaddr_reg:x7; val_offset:1442*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1442*FLEN/8, x11, x1, x6) + +inst_746: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ea and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0ea and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74ea; op2val:0x74ea; + valaddr_reg:x7; val_offset:1444*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1444*FLEN/8, x11, x1, x6) + +inst_747: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ea and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0ea and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74ea; op2val:0x74ea; + valaddr_reg:x7; val_offset:1446*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1446*FLEN/8, x11, x1, x6) + +inst_748: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ea and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0ea and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74ea; op2val:0x74ea; + valaddr_reg:x7; val_offset:1448*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1448*FLEN/8, x11, x1, x6) + +inst_749: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ea and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0ea and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74ea; op2val:0x74ea; + valaddr_reg:x7; val_offset:1450*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1450*FLEN/8, x11, x1, x6) + +inst_750: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x134 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x134 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d34; op2val:0x6d34; + valaddr_reg:x7; val_offset:1452*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1452*FLEN/8, x11, x1, x6) + +inst_751: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x134 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x134 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d34; op2val:0x6d34; + valaddr_reg:x7; val_offset:1454*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1454*FLEN/8, x11, x1, x6) + +inst_752: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x134 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x134 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d34; op2val:0x6d34; + valaddr_reg:x7; val_offset:1456*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1456*FLEN/8, x11, x1, x6) + +inst_753: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x134 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x134 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d34; op2val:0x6d34; + valaddr_reg:x7; val_offset:1458*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1458*FLEN/8, x11, x1, x6) + +inst_754: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x134 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x134 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d34; op2val:0x6d34; + valaddr_reg:x7; val_offset:1460*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1460*FLEN/8, x11, x1, x6) + +inst_755: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x136 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x136 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7936; op2val:0x7936; + valaddr_reg:x7; val_offset:1462*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1462*FLEN/8, x11, x1, x6) + +inst_756: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x136 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x136 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7936; op2val:0x7936; + valaddr_reg:x7; val_offset:1464*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1464*FLEN/8, x11, x1, x6) + +inst_757: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x136 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x136 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7936; op2val:0x7936; + valaddr_reg:x7; val_offset:1466*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1466*FLEN/8, x11, x1, x6) + +inst_758: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x136 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x136 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7936; op2val:0x7936; + valaddr_reg:x7; val_offset:1468*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1468*FLEN/8, x11, x1, x6) + +inst_759: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x136 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x136 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7936; op2val:0x7936; + valaddr_reg:x7; val_offset:1470*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1470*FLEN/8, x11, x1, x6) + +inst_760: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x385 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x385 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b85; op2val:0x7b85; + valaddr_reg:x7; val_offset:1472*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1472*FLEN/8, x11, x1, x6) + +inst_761: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x385 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x385 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b85; op2val:0x7b85; + valaddr_reg:x7; val_offset:1474*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1474*FLEN/8, x11, x1, x6) + +inst_762: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x385 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x385 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b85; op2val:0x7b85; + valaddr_reg:x7; val_offset:1476*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1476*FLEN/8, x11, x1, x6) + +inst_763: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x385 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x385 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b85; op2val:0x7b85; + valaddr_reg:x7; val_offset:1478*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1478*FLEN/8, x11, x1, x6) + +inst_764: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x385 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x385 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b85; op2val:0x7b85; + valaddr_reg:x7; val_offset:1480*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1480*FLEN/8, x11, x1, x6) + +inst_765: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0e8 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0e8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74e8; op2val:0x74e8; + valaddr_reg:x7; val_offset:1482*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1482*FLEN/8, x11, x1, x6) + +inst_766: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0e8 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0e8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74e8; op2val:0x74e8; + valaddr_reg:x7; val_offset:1484*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1484*FLEN/8, x11, x1, x6) + +inst_767: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0e8 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0e8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74e8; op2val:0x74e8; + valaddr_reg:x7; val_offset:1486*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1486*FLEN/8, x11, x1, x6) + +inst_768: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0e8 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0e8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74e8; op2val:0x74e8; + valaddr_reg:x7; val_offset:1488*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1488*FLEN/8, x11, x1, x6) + +inst_769: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0e8 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0e8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74e8; op2val:0x74e8; + valaddr_reg:x7; val_offset:1490*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1490*FLEN/8, x11, x1, x6) + +inst_770: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x110 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x110 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7510; op2val:0x7510; + valaddr_reg:x7; val_offset:1492*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1492*FLEN/8, x11, x1, x6) + +inst_771: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x110 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x110 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7510; op2val:0x7510; + valaddr_reg:x7; val_offset:1494*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1494*FLEN/8, x11, x1, x6) + +inst_772: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x110 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x110 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7510; op2val:0x7510; + valaddr_reg:x7; val_offset:1496*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1496*FLEN/8, x11, x1, x6) + +inst_773: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x110 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x110 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7510; op2val:0x7510; + valaddr_reg:x7; val_offset:1498*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1498*FLEN/8, x11, x1, x6) + +inst_774: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x110 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x110 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7510; op2val:0x7510; + valaddr_reg:x7; val_offset:1500*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1500*FLEN/8, x11, x1, x6) + +inst_775: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x324 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x324 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b24; op2val:0x7b24; + valaddr_reg:x7; val_offset:1502*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1502*FLEN/8, x11, x1, x6) + +inst_776: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x324 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x324 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b24; op2val:0x7b24; + valaddr_reg:x7; val_offset:1504*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1504*FLEN/8, x11, x1, x6) + +inst_777: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x324 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x324 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b24; op2val:0x7b24; + valaddr_reg:x7; val_offset:1506*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1506*FLEN/8, x11, x1, x6) + +inst_778: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x324 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x324 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b24; op2val:0x7b24; + valaddr_reg:x7; val_offset:1508*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1508*FLEN/8, x11, x1, x6) + +inst_779: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x324 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x324 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b24; op2val:0x7b24; + valaddr_reg:x7; val_offset:1510*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1510*FLEN/8, x11, x1, x6) + +inst_780: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x158 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x158 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7558; op2val:0x7558; + valaddr_reg:x7; val_offset:1512*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1512*FLEN/8, x11, x1, x6) + +inst_781: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x158 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x158 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7558; op2val:0x7558; + valaddr_reg:x7; val_offset:1514*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1514*FLEN/8, x11, x1, x6) + +inst_782: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x158 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x158 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7558; op2val:0x7558; + valaddr_reg:x7; val_offset:1516*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1516*FLEN/8, x11, x1, x6) + +inst_783: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x158 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x158 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7558; op2val:0x7558; + valaddr_reg:x7; val_offset:1518*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1518*FLEN/8, x11, x1, x6) + +inst_784: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x158 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x158 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7558; op2val:0x7558; + valaddr_reg:x7; val_offset:1520*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1520*FLEN/8, x11, x1, x6) + +inst_785: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0a1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x78a1; op2val:0x78a1; + valaddr_reg:x7; val_offset:1522*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1522*FLEN/8, x11, x1, x6) + +inst_786: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0a1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x78a1; op2val:0x78a1; + valaddr_reg:x7; val_offset:1524*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1524*FLEN/8, x11, x1, x6) + +inst_787: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0a1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x78a1; op2val:0x78a1; + valaddr_reg:x7; val_offset:1526*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1526*FLEN/8, x11, x1, x6) + +inst_788: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0a1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x78a1; op2val:0x78a1; + valaddr_reg:x7; val_offset:1528*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1528*FLEN/8, x11, x1, x6) + +inst_789: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0a1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x78a1; op2val:0x78a1; + valaddr_reg:x7; val_offset:1530*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1530*FLEN/8, x11, x1, x6) + +inst_790: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3d6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x73d6; op2val:0x73d6; + valaddr_reg:x7; val_offset:1532*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1532*FLEN/8, x11, x1, x6) + +inst_791: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3d6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x73d6; op2val:0x73d6; + valaddr_reg:x7; val_offset:1534*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1534*FLEN/8, x11, x1, x6) + +inst_792: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3d6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x73d6; op2val:0x73d6; + valaddr_reg:x7; val_offset:1536*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1536*FLEN/8, x11, x1, x6) + +inst_793: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3d6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x73d6; op2val:0x73d6; + valaddr_reg:x7; val_offset:1538*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1538*FLEN/8, x11, x1, x6) +RVTEST_SIGBASE(x1,signature_x1_8) + +inst_794: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3d6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x73d6; op2val:0x73d6; + valaddr_reg:x7; val_offset:1540*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1540*FLEN/8, x11, x1, x6) + +inst_795: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3cb and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3cb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x73cb; op2val:0x73cb; + valaddr_reg:x7; val_offset:1542*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1542*FLEN/8, x11, x1, x6) + +inst_796: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3cb and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3cb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x73cb; op2val:0x73cb; + valaddr_reg:x7; val_offset:1544*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1544*FLEN/8, x11, x1, x6) + +inst_797: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3cb and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3cb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x73cb; op2val:0x73cb; + valaddr_reg:x7; val_offset:1546*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1546*FLEN/8, x11, x1, x6) + +inst_798: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3cb and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3cb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x73cb; op2val:0x73cb; + valaddr_reg:x7; val_offset:1548*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1548*FLEN/8, x11, x1, x6) + +inst_799: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3cb and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3cb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x73cb; op2val:0x73cb; + valaddr_reg:x7; val_offset:1550*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1550*FLEN/8, x11, x1, x6) + +inst_800: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x068 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x068 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7868; op2val:0x7868; + valaddr_reg:x7; val_offset:1552*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1552*FLEN/8, x11, x1, x6) + +inst_801: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x068 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x068 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7868; op2val:0x7868; + valaddr_reg:x7; val_offset:1554*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1554*FLEN/8, x11, x1, x6) + +inst_802: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x068 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x068 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7868; op2val:0x7868; + valaddr_reg:x7; val_offset:1556*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1556*FLEN/8, x11, x1, x6) + +inst_803: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x068 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x068 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7868; op2val:0x7868; + valaddr_reg:x7; val_offset:1558*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1558*FLEN/8, x11, x1, x6) + +inst_804: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x068 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x068 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7868; op2val:0x7868; + valaddr_reg:x7; val_offset:1560*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1560*FLEN/8, x11, x1, x6) + +inst_805: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0ce and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0ce and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6cce; op2val:0x6cce; + valaddr_reg:x7; val_offset:1562*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1562*FLEN/8, x11, x1, x6) + +inst_806: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0ce and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0ce and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6cce; op2val:0x6cce; + valaddr_reg:x7; val_offset:1564*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1564*FLEN/8, x11, x1, x6) + +inst_807: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0ce and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0ce and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6cce; op2val:0x6cce; + valaddr_reg:x7; val_offset:1566*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1566*FLEN/8, x11, x1, x6) + +inst_808: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0ce and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0ce and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6cce; op2val:0x6cce; + valaddr_reg:x7; val_offset:1568*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1568*FLEN/8, x11, x1, x6) + +inst_809: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0ce and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0ce and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6cce; op2val:0x6cce; + valaddr_reg:x7; val_offset:1570*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1570*FLEN/8, x11, x1, x6) + +inst_810: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a6 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0a6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74a6; op2val:0x74a6; + valaddr_reg:x7; val_offset:1572*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1572*FLEN/8, x11, x1, x6) + +inst_811: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a6 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0a6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74a6; op2val:0x74a6; + valaddr_reg:x7; val_offset:1574*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1574*FLEN/8, x11, x1, x6) + +inst_812: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a6 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0a6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74a6; op2val:0x74a6; + valaddr_reg:x7; val_offset:1576*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1576*FLEN/8, x11, x1, x6) + +inst_813: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a6 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0a6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74a6; op2val:0x74a6; + valaddr_reg:x7; val_offset:1578*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1578*FLEN/8, x11, x1, x6) + +inst_814: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a6 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0a6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74a6; op2val:0x74a6; + valaddr_reg:x7; val_offset:1580*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1580*FLEN/8, x11, x1, x6) + +inst_815: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3e3 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3e3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x77e3; op2val:0x77e3; + valaddr_reg:x7; val_offset:1582*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1582*FLEN/8, x11, x1, x6) + +inst_816: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3e3 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3e3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x77e3; op2val:0x77e3; + valaddr_reg:x7; val_offset:1584*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1584*FLEN/8, x11, x1, x6) + +inst_817: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3e3 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3e3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x77e3; op2val:0x77e3; + valaddr_reg:x7; val_offset:1586*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1586*FLEN/8, x11, x1, x6) + +inst_818: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3e3 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3e3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x77e3; op2val:0x77e3; + valaddr_reg:x7; val_offset:1588*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1588*FLEN/8, x11, x1, x6) + +inst_819: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3e3 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3e3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x77e3; op2val:0x77e3; + valaddr_reg:x7; val_offset:1590*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1590*FLEN/8, x11, x1, x6) + +inst_820: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0ee and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0ee and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x70ee; op2val:0x70ee; + valaddr_reg:x7; val_offset:1592*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1592*FLEN/8, x11, x1, x6) + +inst_821: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0ee and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0ee and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x70ee; op2val:0x70ee; + valaddr_reg:x7; val_offset:1594*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1594*FLEN/8, x11, x1, x6) + +inst_822: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0ee and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0ee and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x70ee; op2val:0x70ee; + valaddr_reg:x7; val_offset:1596*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1596*FLEN/8, x11, x1, x6) + +inst_823: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0ee and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0ee and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x70ee; op2val:0x70ee; + valaddr_reg:x7; val_offset:1598*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1598*FLEN/8, x11, x1, x6) + +inst_824: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0ee and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0ee and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x70ee; op2val:0x70ee; + valaddr_reg:x7; val_offset:1600*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1600*FLEN/8, x11, x1, x6) + +inst_825: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x25b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a5b; op2val:0x7a5b; + valaddr_reg:x7; val_offset:1602*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1602*FLEN/8, x11, x1, x6) + +inst_826: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x25b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a5b; op2val:0x7a5b; + valaddr_reg:x7; val_offset:1604*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1604*FLEN/8, x11, x1, x6) + +inst_827: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x25b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a5b; op2val:0x7a5b; + valaddr_reg:x7; val_offset:1606*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1606*FLEN/8, x11, x1, x6) + +inst_828: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x25b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a5b; op2val:0x7a5b; + valaddr_reg:x7; val_offset:1608*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1608*FLEN/8, x11, x1, x6) + +inst_829: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x25b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a5b; op2val:0x7a5b; + valaddr_reg:x7; val_offset:1610*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1610*FLEN/8, x11, x1, x6) + +inst_830: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x397 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x395 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b97; op2val:0x7b95; + valaddr_reg:x7; val_offset:1612*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1612*FLEN/8, x11, x1, x6) + +inst_831: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x397 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x395 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b97; op2val:0x7b95; + valaddr_reg:x7; val_offset:1614*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1614*FLEN/8, x11, x1, x6) + +inst_832: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x397 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x395 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b97; op2val:0x7b95; + valaddr_reg:x7; val_offset:1616*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1616*FLEN/8, x11, x1, x6) + +inst_833: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x397 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x395 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b97; op2val:0x7b95; + valaddr_reg:x7; val_offset:1618*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1618*FLEN/8, x11, x1, x6) + +inst_834: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x397 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x395 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b97; op2val:0x7b95; + valaddr_reg:x7; val_offset:1620*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1620*FLEN/8, x11, x1, x6) + +inst_835: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x234 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x232 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a34; op2val:0x7a32; + valaddr_reg:x7; val_offset:1622*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1622*FLEN/8, x11, x1, x6) + +inst_836: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x234 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x232 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a34; op2val:0x7a32; + valaddr_reg:x7; val_offset:1624*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1624*FLEN/8, x11, x1, x6) + +inst_837: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x234 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x232 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a34; op2val:0x7a32; + valaddr_reg:x7; val_offset:1626*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1626*FLEN/8, x11, x1, x6) + +inst_838: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x234 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x232 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a34; op2val:0x7a32; + valaddr_reg:x7; val_offset:1628*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1628*FLEN/8, x11, x1, x6) + +inst_839: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x234 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x232 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a34; op2val:0x7a32; + valaddr_reg:x7; val_offset:1630*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1630*FLEN/8, x11, x1, x6) + +inst_840: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x291 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x28f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a91; op2val:0x7a8f; + valaddr_reg:x7; val_offset:1632*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1632*FLEN/8, x11, x1, x6) + +inst_841: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x291 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x28f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a91; op2val:0x7a8f; + valaddr_reg:x7; val_offset:1634*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1634*FLEN/8, x11, x1, x6) + +inst_842: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x291 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x28f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a91; op2val:0x7a8f; + valaddr_reg:x7; val_offset:1636*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1636*FLEN/8, x11, x1, x6) + +inst_843: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x291 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x28f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a91; op2val:0x7a8f; + valaddr_reg:x7; val_offset:1638*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1638*FLEN/8, x11, x1, x6) + +inst_844: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x291 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x28f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a91; op2val:0x7a8f; + valaddr_reg:x7; val_offset:1640*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1640*FLEN/8, x11, x1, x6) + +inst_845: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2d6 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2c6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ed6; op2val:0x6ec6; + valaddr_reg:x7; val_offset:1642*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1642*FLEN/8, x11, x1, x6) + +inst_846: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2d6 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2c6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ed6; op2val:0x6ec6; + valaddr_reg:x7; val_offset:1644*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1644*FLEN/8, x11, x1, x6) + +inst_847: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2d6 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2c6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ed6; op2val:0x6ec6; + valaddr_reg:x7; val_offset:1646*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1646*FLEN/8, x11, x1, x6) + +inst_848: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2d6 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2c6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ed6; op2val:0x6ec6; + valaddr_reg:x7; val_offset:1648*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1648*FLEN/8, x11, x1, x6) + +inst_849: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2d6 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2c6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ed6; op2val:0x6ec6; + valaddr_reg:x7; val_offset:1650*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1650*FLEN/8, x11, x1, x6) + +inst_850: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x359 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x357 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b59; op2val:0x7b57; + valaddr_reg:x7; val_offset:1652*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1652*FLEN/8, x11, x1, x6) + +inst_851: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x359 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x357 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b59; op2val:0x7b57; + valaddr_reg:x7; val_offset:1654*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1654*FLEN/8, x11, x1, x6) + +inst_852: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x359 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x357 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b59; op2val:0x7b57; + valaddr_reg:x7; val_offset:1656*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1656*FLEN/8, x11, x1, x6) + +inst_853: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x359 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x357 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b59; op2val:0x7b57; + valaddr_reg:x7; val_offset:1658*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1658*FLEN/8, x11, x1, x6) + +inst_854: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x359 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x357 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b59; op2val:0x7b57; + valaddr_reg:x7; val_offset:1660*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1660*FLEN/8, x11, x1, x6) + +inst_855: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x325 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x323 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b25; op2val:0x7b23; + valaddr_reg:x7; val_offset:1662*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1662*FLEN/8, x11, x1, x6) + +inst_856: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x325 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x323 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b25; op2val:0x7b23; + valaddr_reg:x7; val_offset:1664*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1664*FLEN/8, x11, x1, x6) + +inst_857: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x325 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x323 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b25; op2val:0x7b23; + valaddr_reg:x7; val_offset:1666*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1666*FLEN/8, x11, x1, x6) + +inst_858: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x325 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x323 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b25; op2val:0x7b23; + valaddr_reg:x7; val_offset:1668*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1668*FLEN/8, x11, x1, x6) + +inst_859: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x325 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x323 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b25; op2val:0x7b23; + valaddr_reg:x7; val_offset:1670*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1670*FLEN/8, x11, x1, x6) + +inst_860: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x347 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x345 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b47; op2val:0x7b45; + valaddr_reg:x7; val_offset:1672*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1672*FLEN/8, x11, x1, x6) + +inst_861: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x347 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x345 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b47; op2val:0x7b45; + valaddr_reg:x7; val_offset:1674*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1674*FLEN/8, x11, x1, x6) + +inst_862: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x347 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x345 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b47; op2val:0x7b45; + valaddr_reg:x7; val_offset:1676*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1676*FLEN/8, x11, x1, x6) + +inst_863: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x347 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x345 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b47; op2val:0x7b45; + valaddr_reg:x7; val_offset:1678*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1678*FLEN/8, x11, x1, x6) + +inst_864: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x347 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x345 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b47; op2val:0x7b45; + valaddr_reg:x7; val_offset:1680*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1680*FLEN/8, x11, x1, x6) + +inst_865: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x10e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x112 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x750e; op2val:0x7512; + valaddr_reg:x7; val_offset:1682*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1682*FLEN/8, x11, x1, x6) + +inst_866: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x10e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x112 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x750e; op2val:0x7512; + valaddr_reg:x7; val_offset:1684*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1684*FLEN/8, x11, x1, x6) + +inst_867: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x10e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x112 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x750e; op2val:0x7512; + valaddr_reg:x7; val_offset:1686*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1686*FLEN/8, x11, x1, x6) + +inst_868: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x10e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x112 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x750e; op2val:0x7512; + valaddr_reg:x7; val_offset:1688*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1688*FLEN/8, x11, x1, x6) + +inst_869: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x10e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x112 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x750e; op2val:0x7512; + valaddr_reg:x7; val_offset:1690*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1690*FLEN/8, x11, x1, x6) + +inst_870: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x26f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a6d; op2val:0x7a6f; + valaddr_reg:x7; val_offset:1692*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1692*FLEN/8, x11, x1, x6) + +inst_871: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x26f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a6d; op2val:0x7a6f; + valaddr_reg:x7; val_offset:1694*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1694*FLEN/8, x11, x1, x6) + +inst_872: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x26f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a6d; op2val:0x7a6f; + valaddr_reg:x7; val_offset:1696*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1696*FLEN/8, x11, x1, x6) + +inst_873: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x26f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a6d; op2val:0x7a6f; + valaddr_reg:x7; val_offset:1698*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1698*FLEN/8, x11, x1, x6) + +inst_874: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x26f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a6d; op2val:0x7a6f; + valaddr_reg:x7; val_offset:1700*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1700*FLEN/8, x11, x1, x6) + +inst_875: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ba and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab8; op2val:0x7aba; + valaddr_reg:x7; val_offset:1702*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1702*FLEN/8, x11, x1, x6) + +inst_876: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ba and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab8; op2val:0x7aba; + valaddr_reg:x7; val_offset:1704*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1704*FLEN/8, x11, x1, x6) + +inst_877: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ba and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab8; op2val:0x7aba; + valaddr_reg:x7; val_offset:1706*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1706*FLEN/8, x11, x1, x6) + +inst_878: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ba and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab8; op2val:0x7aba; + valaddr_reg:x7; val_offset:1708*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1708*FLEN/8, x11, x1, x6) + +inst_879: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ba and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab8; op2val:0x7aba; + valaddr_reg:x7; val_offset:1710*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1710*FLEN/8, x11, x1, x6) + +inst_880: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x183 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x185 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7983; op2val:0x7985; + valaddr_reg:x7; val_offset:1712*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1712*FLEN/8, x11, x1, x6) + +inst_881: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x183 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x185 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7983; op2val:0x7985; + valaddr_reg:x7; val_offset:1714*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1714*FLEN/8, x11, x1, x6) + +inst_882: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x183 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x185 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7983; op2val:0x7985; + valaddr_reg:x7; val_offset:1716*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1716*FLEN/8, x11, x1, x6) + +inst_883: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x183 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x185 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7983; op2val:0x7985; + valaddr_reg:x7; val_offset:1718*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1718*FLEN/8, x11, x1, x6) + +inst_884: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x183 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x185 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7983; op2val:0x7985; + valaddr_reg:x7; val_offset:1720*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1720*FLEN/8, x11, x1, x6) + +inst_885: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2eb and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2ef and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x76eb; op2val:0x76ef; + valaddr_reg:x7; val_offset:1722*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1722*FLEN/8, x11, x1, x6) + +inst_886: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2eb and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2ef and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x76eb; op2val:0x76ef; + valaddr_reg:x7; val_offset:1724*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1724*FLEN/8, x11, x1, x6) + +inst_887: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2eb and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2ef and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x76eb; op2val:0x76ef; + valaddr_reg:x7; val_offset:1726*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1726*FLEN/8, x11, x1, x6) + +inst_888: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2eb and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2ef and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x76eb; op2val:0x76ef; + valaddr_reg:x7; val_offset:1728*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1728*FLEN/8, x11, x1, x6) + +inst_889: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2eb and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2ef and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x76eb; op2val:0x76ef; + valaddr_reg:x7; val_offset:1730*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1730*FLEN/8, x11, x1, x6) + +inst_890: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1b9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b7; op2val:0x79b9; + valaddr_reg:x7; val_offset:1732*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1732*FLEN/8, x11, x1, x6) + +inst_891: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1b9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b7; op2val:0x79b9; + valaddr_reg:x7; val_offset:1734*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1734*FLEN/8, x11, x1, x6) + +inst_892: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1b9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b7; op2val:0x79b9; + valaddr_reg:x7; val_offset:1736*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1736*FLEN/8, x11, x1, x6) + +inst_893: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1b9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b7; op2val:0x79b9; + valaddr_reg:x7; val_offset:1738*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1738*FLEN/8, x11, x1, x6) + +inst_894: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1b9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b7; op2val:0x79b9; + valaddr_reg:x7; val_offset:1740*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1740*FLEN/8, x11, x1, x6) + +inst_895: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x00a and fs2 == 0 and fe2 == 0x1d and fm2 == 0x00e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x740a; op2val:0x740e; + valaddr_reg:x7; val_offset:1742*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1742*FLEN/8, x11, x1, x6) + +inst_896: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x00a and fs2 == 0 and fe2 == 0x1d and fm2 == 0x00e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x740a; op2val:0x740e; + valaddr_reg:x7; val_offset:1744*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1744*FLEN/8, x11, x1, x6) + +inst_897: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x00a and fs2 == 0 and fe2 == 0x1d and fm2 == 0x00e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x740a; op2val:0x740e; + valaddr_reg:x7; val_offset:1746*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1746*FLEN/8, x11, x1, x6) + +inst_898: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x00a and fs2 == 0 and fe2 == 0x1d and fm2 == 0x00e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x740a; op2val:0x740e; + valaddr_reg:x7; val_offset:1748*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1748*FLEN/8, x11, x1, x6) + +inst_899: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x00a and fs2 == 0 and fe2 == 0x1d and fm2 == 0x00e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x740a; op2val:0x740e; + valaddr_reg:x7; val_offset:1750*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1750*FLEN/8, x11, x1, x6) + +inst_900: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3b6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb4; op2val:0x7bb6; + valaddr_reg:x7; val_offset:1752*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1752*FLEN/8, x11, x1, x6) + +inst_901: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3b6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb4; op2val:0x7bb6; + valaddr_reg:x7; val_offset:1754*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1754*FLEN/8, x11, x1, x6) + +inst_902: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3b6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb4; op2val:0x7bb6; + valaddr_reg:x7; val_offset:1756*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1756*FLEN/8, x11, x1, x6) + +inst_903: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3b6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb4; op2val:0x7bb6; + valaddr_reg:x7; val_offset:1758*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1758*FLEN/8, x11, x1, x6) + +inst_904: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3b6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb4; op2val:0x7bb6; + valaddr_reg:x7; val_offset:1760*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1760*FLEN/8, x11, x1, x6) + +inst_905: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x064 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x066 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7864; op2val:0x7866; + valaddr_reg:x7; val_offset:1762*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1762*FLEN/8, x11, x1, x6) + +inst_906: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x064 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x066 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7864; op2val:0x7866; + valaddr_reg:x7; val_offset:1764*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1764*FLEN/8, x11, x1, x6) + +inst_907: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x064 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x066 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7864; op2val:0x7866; + valaddr_reg:x7; val_offset:1766*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1766*FLEN/8, x11, x1, x6) + +inst_908: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x064 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x066 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7864; op2val:0x7866; + valaddr_reg:x7; val_offset:1768*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1768*FLEN/8, x11, x1, x6) + +inst_909: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x064 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x066 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7864; op2val:0x7866; + valaddr_reg:x7; val_offset:1770*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1770*FLEN/8, x11, x1, x6) + +inst_910: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ce and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2d0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ace; op2val:0x7ad0; + valaddr_reg:x7; val_offset:1772*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1772*FLEN/8, x11, x1, x6) + +inst_911: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ce and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2d0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ace; op2val:0x7ad0; + valaddr_reg:x7; val_offset:1774*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1774*FLEN/8, x11, x1, x6) + +inst_912: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ce and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2d0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ace; op2val:0x7ad0; + valaddr_reg:x7; val_offset:1776*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1776*FLEN/8, x11, x1, x6) + +inst_913: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ce and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2d0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ace; op2val:0x7ad0; + valaddr_reg:x7; val_offset:1778*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1778*FLEN/8, x11, x1, x6) + +inst_914: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ce and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2d0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ace; op2val:0x7ad0; + valaddr_reg:x7; val_offset:1780*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1780*FLEN/8, x11, x1, x6) + +inst_915: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x254 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x258 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7654; op2val:0x7658; + valaddr_reg:x7; val_offset:1782*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1782*FLEN/8, x11, x1, x6) + +inst_916: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x254 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x258 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7654; op2val:0x7658; + valaddr_reg:x7; val_offset:1784*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1784*FLEN/8, x11, x1, x6) + +inst_917: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x254 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x258 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7654; op2val:0x7658; + valaddr_reg:x7; val_offset:1786*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1786*FLEN/8, x11, x1, x6) + +inst_918: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x254 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x258 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7654; op2val:0x7658; + valaddr_reg:x7; val_offset:1788*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1788*FLEN/8, x11, x1, x6) + +inst_919: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x254 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x258 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7654; op2val:0x7658; + valaddr_reg:x7; val_offset:1790*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1790*FLEN/8, x11, x1, x6) + +inst_920: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x020 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x024 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7420; op2val:0x7424; + valaddr_reg:x7; val_offset:1792*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1792*FLEN/8, x11, x1, x6) + +inst_921: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x020 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x024 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7420; op2val:0x7424; + valaddr_reg:x7; val_offset:1794*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1794*FLEN/8, x11, x1, x6) +RVTEST_SIGBASE(x1,signature_x1_9) + +inst_922: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x020 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x024 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7420; op2val:0x7424; + valaddr_reg:x7; val_offset:1796*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1796*FLEN/8, x11, x1, x6) + +inst_923: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x020 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x024 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7420; op2val:0x7424; + valaddr_reg:x7; val_offset:1798*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1798*FLEN/8, x11, x1, x6) + +inst_924: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x020 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x024 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7420; op2val:0x7424; + valaddr_reg:x7; val_offset:1800*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1800*FLEN/8, x11, x1, x6) + +inst_925: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x12d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x792b; op2val:0x792d; + valaddr_reg:x7; val_offset:1802*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1802*FLEN/8, x11, x1, x6) + +inst_926: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x12d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x792b; op2val:0x792d; + valaddr_reg:x7; val_offset:1804*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1804*FLEN/8, x11, x1, x6) + +inst_927: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x12d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x792b; op2val:0x792d; + valaddr_reg:x7; val_offset:1806*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1806*FLEN/8, x11, x1, x6) + +inst_928: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x12d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x792b; op2val:0x792d; + valaddr_reg:x7; val_offset:1808*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1808*FLEN/8, x11, x1, x6) + +inst_929: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x12d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x792b; op2val:0x792d; + valaddr_reg:x7; val_offset:1810*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1810*FLEN/8, x11, x1, x6) + +inst_930: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x090 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x092 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7890; op2val:0x7892; + valaddr_reg:x7; val_offset:1812*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1812*FLEN/8, x11, x1, x6) + +inst_931: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x090 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x092 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7890; op2val:0x7892; + valaddr_reg:x7; val_offset:1814*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1814*FLEN/8, x11, x1, x6) + +inst_932: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x090 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x092 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7890; op2val:0x7892; + valaddr_reg:x7; val_offset:1816*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1816*FLEN/8, x11, x1, x6) + +inst_933: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x090 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x092 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7890; op2val:0x7892; + valaddr_reg:x7; val_offset:1818*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1818*FLEN/8, x11, x1, x6) + +inst_934: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x090 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x092 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7890; op2val:0x7892; + valaddr_reg:x7; val_offset:1820*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1820*FLEN/8, x11, x1, x6) + +inst_935: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ad and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1a9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x75ad; op2val:0x75a9; + valaddr_reg:x7; val_offset:1822*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1822*FLEN/8, x11, x1, x6) + +inst_936: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ad and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1a9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x75ad; op2val:0x75a9; + valaddr_reg:x7; val_offset:1824*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1824*FLEN/8, x11, x1, x6) + +inst_937: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ad and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1a9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x75ad; op2val:0x75a9; + valaddr_reg:x7; val_offset:1826*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1826*FLEN/8, x11, x1, x6) + +inst_938: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ad and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1a9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x75ad; op2val:0x75a9; + valaddr_reg:x7; val_offset:1828*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1828*FLEN/8, x11, x1, x6) + +inst_939: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ad and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1a9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x75ad; op2val:0x75a9; + valaddr_reg:x7; val_offset:1830*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1830*FLEN/8, x11, x1, x6) + +inst_940: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3f1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7000; op2val:0x6ff1; + valaddr_reg:x7; val_offset:1832*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1832*FLEN/8, x11, x1, x6) + +inst_941: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3f1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7000; op2val:0x6ff1; + valaddr_reg:x7; val_offset:1834*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1834*FLEN/8, x11, x1, x6) + +inst_942: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3f1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7000; op2val:0x6ff1; + valaddr_reg:x7; val_offset:1836*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1836*FLEN/8, x11, x1, x6) + +inst_943: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3f1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7000; op2val:0x6ff1; + valaddr_reg:x7; val_offset:1838*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1838*FLEN/8, x11, x1, x6) + +inst_944: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3f1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7000; op2val:0x6ff1; + valaddr_reg:x7; val_offset:1840*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1840*FLEN/8, x11, x1, x6) + +inst_945: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x29e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aa0; op2val:0x7a9e; + valaddr_reg:x7; val_offset:1842*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1842*FLEN/8, x11, x1, x6) + +inst_946: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x29e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aa0; op2val:0x7a9e; + valaddr_reg:x7; val_offset:1844*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1844*FLEN/8, x11, x1, x6) + +inst_947: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x29e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aa0; op2val:0x7a9e; + valaddr_reg:x7; val_offset:1846*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1846*FLEN/8, x11, x1, x6) + +inst_948: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x29e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aa0; op2val:0x7a9e; + valaddr_reg:x7; val_offset:1848*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1848*FLEN/8, x11, x1, x6) + +inst_949: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x29e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aa0; op2val:0x7a9e; + valaddr_reg:x7; val_offset:1850*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1850*FLEN/8, x11, x1, x6) + +inst_950: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26a and fs2 == 0 and fe2 == 0x1d and fm2 == 0x266 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x766a; op2val:0x7666; + valaddr_reg:x7; val_offset:1852*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1852*FLEN/8, x11, x1, x6) + +inst_951: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26a and fs2 == 0 and fe2 == 0x1d and fm2 == 0x266 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x766a; op2val:0x7666; + valaddr_reg:x7; val_offset:1854*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1854*FLEN/8, x11, x1, x6) + +inst_952: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26a and fs2 == 0 and fe2 == 0x1d and fm2 == 0x266 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x766a; op2val:0x7666; + valaddr_reg:x7; val_offset:1856*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1856*FLEN/8, x11, x1, x6) + +inst_953: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26a and fs2 == 0 and fe2 == 0x1d and fm2 == 0x266 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x766a; op2val:0x7666; + valaddr_reg:x7; val_offset:1858*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1858*FLEN/8, x11, x1, x6) + +inst_954: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26a and fs2 == 0 and fe2 == 0x1d and fm2 == 0x266 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x766a; op2val:0x7666; + valaddr_reg:x7; val_offset:1860*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1860*FLEN/8, x11, x1, x6) + +inst_955: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x378 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x370 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7378; op2val:0x7370; + valaddr_reg:x7; val_offset:1862*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1862*FLEN/8, x11, x1, x6) + +inst_956: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x378 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x370 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7378; op2val:0x7370; + valaddr_reg:x7; val_offset:1864*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1864*FLEN/8, x11, x1, x6) + +inst_957: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x378 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x370 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7378; op2val:0x7370; + valaddr_reg:x7; val_offset:1866*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1866*FLEN/8, x11, x1, x6) + +inst_958: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x378 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x370 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7378; op2val:0x7370; + valaddr_reg:x7; val_offset:1868*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1868*FLEN/8, x11, x1, x6) + +inst_959: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x378 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x370 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7378; op2val:0x7370; + valaddr_reg:x7; val_offset:1870*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1870*FLEN/8, x11, x1, x6) + +inst_960: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x03a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x038 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x783a; op2val:0x7838; + valaddr_reg:x7; val_offset:1872*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1872*FLEN/8, x11, x1, x6) + +inst_961: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x03a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x038 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x783a; op2val:0x7838; + valaddr_reg:x7; val_offset:1874*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1874*FLEN/8, x11, x1, x6) + +inst_962: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x03a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x038 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x783a; op2val:0x7838; + valaddr_reg:x7; val_offset:1876*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1876*FLEN/8, x11, x1, x6) + +inst_963: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x03a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x038 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x783a; op2val:0x7838; + valaddr_reg:x7; val_offset:1878*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1878*FLEN/8, x11, x1, x6) + +inst_964: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x03a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x038 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x783a; op2val:0x7838; + valaddr_reg:x7; val_offset:1880*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1880*FLEN/8, x11, x1, x6) + +inst_965: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x130 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x12e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7930; op2val:0x792e; + valaddr_reg:x7; val_offset:1882*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1882*FLEN/8, x11, x1, x6) + +inst_966: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x130 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x12e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7930; op2val:0x792e; + valaddr_reg:x7; val_offset:1884*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1884*FLEN/8, x11, x1, x6) + +inst_967: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x130 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x12e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7930; op2val:0x792e; + valaddr_reg:x7; val_offset:1886*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1886*FLEN/8, x11, x1, x6) + +inst_968: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x130 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x12e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7930; op2val:0x792e; + valaddr_reg:x7; val_offset:1888*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1888*FLEN/8, x11, x1, x6) + +inst_969: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x130 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x12e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7930; op2val:0x792e; + valaddr_reg:x7; val_offset:1890*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1890*FLEN/8, x11, x1, x6) + +inst_970: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x17d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x17d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x797d; op2val:0x797d; + valaddr_reg:x7; val_offset:1892*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1892*FLEN/8, x11, x1, x6) + +inst_971: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x17d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x17d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x797d; op2val:0x797d; + valaddr_reg:x7; val_offset:1894*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1894*FLEN/8, x11, x1, x6) + +inst_972: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x17d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x17d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x797d; op2val:0x797d; + valaddr_reg:x7; val_offset:1896*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1896*FLEN/8, x11, x1, x6) + +inst_973: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x17d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x17d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x797d; op2val:0x797d; + valaddr_reg:x7; val_offset:1898*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1898*FLEN/8, x11, x1, x6) + +inst_974: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x17d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x17d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x797d; op2val:0x797d; + valaddr_reg:x7; val_offset:1900*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1900*FLEN/8, x11, x1, x6) + +inst_975: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39f and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x739f; op2val:0x739f; + valaddr_reg:x7; val_offset:1902*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1902*FLEN/8, x11, x1, x6) + +inst_976: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39f and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x739f; op2val:0x739f; + valaddr_reg:x7; val_offset:1904*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1904*FLEN/8, x11, x1, x6) + +inst_977: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39f and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x739f; op2val:0x739f; + valaddr_reg:x7; val_offset:1906*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1906*FLEN/8, x11, x1, x6) + +inst_978: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39f and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x739f; op2val:0x739f; + valaddr_reg:x7; val_offset:1908*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1908*FLEN/8, x11, x1, x6) + +inst_979: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39f and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x739f; op2val:0x739f; + valaddr_reg:x7; val_offset:1910*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1910*FLEN/8, x11, x1, x6) + +inst_980: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a8 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3a8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x77a8; op2val:0x77a8; + valaddr_reg:x7; val_offset:1912*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1912*FLEN/8, x11, x1, x6) + +inst_981: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a8 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3a8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x77a8; op2val:0x77a8; + valaddr_reg:x7; val_offset:1914*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1914*FLEN/8, x11, x1, x6) + +inst_982: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a8 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3a8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x77a8; op2val:0x77a8; + valaddr_reg:x7; val_offset:1916*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1916*FLEN/8, x11, x1, x6) + +inst_983: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a8 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3a8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x77a8; op2val:0x77a8; + valaddr_reg:x7; val_offset:1918*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1918*FLEN/8, x11, x1, x6) + +inst_984: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a8 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3a8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x77a8; op2val:0x77a8; + valaddr_reg:x7; val_offset:1920*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1920*FLEN/8, x11, x1, x6) + +inst_985: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x297 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x297 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7697; op2val:0x7697; + valaddr_reg:x7; val_offset:1922*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1922*FLEN/8, x11, x1, x6) + +inst_986: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x297 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x297 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7697; op2val:0x7697; + valaddr_reg:x7; val_offset:1924*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1924*FLEN/8, x11, x1, x6) + +inst_987: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x297 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x297 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7697; op2val:0x7697; + valaddr_reg:x7; val_offset:1926*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1926*FLEN/8, x11, x1, x6) + +inst_988: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x297 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x297 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7697; op2val:0x7697; + valaddr_reg:x7; val_offset:1928*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1928*FLEN/8, x11, x1, x6) + +inst_989: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x297 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x297 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7697; op2val:0x7697; + valaddr_reg:x7; val_offset:1930*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1930*FLEN/8, x11, x1, x6) + +inst_990: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x340 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x340 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b40; op2val:0x7b40; + valaddr_reg:x7; val_offset:1932*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1932*FLEN/8, x11, x1, x6) + +inst_991: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x340 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x340 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b40; op2val:0x7b40; + valaddr_reg:x7; val_offset:1934*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1934*FLEN/8, x11, x1, x6) + +inst_992: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x340 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x340 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b40; op2val:0x7b40; + valaddr_reg:x7; val_offset:1936*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1936*FLEN/8, x11, x1, x6) + +inst_993: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x340 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x340 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b40; op2val:0x7b40; + valaddr_reg:x7; val_offset:1938*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1938*FLEN/8, x11, x1, x6) + +inst_994: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x340 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x340 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b40; op2val:0x7b40; + valaddr_reg:x7; val_offset:1940*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1940*FLEN/8, x11, x1, x6) + +inst_995: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x066 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x066 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7466; op2val:0x7466; + valaddr_reg:x7; val_offset:1942*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1942*FLEN/8, x11, x1, x6) + +inst_996: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x066 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x066 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7466; op2val:0x7466; + valaddr_reg:x7; val_offset:1944*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1944*FLEN/8, x11, x1, x6) + +inst_997: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x066 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x066 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7466; op2val:0x7466; + valaddr_reg:x7; val_offset:1946*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1946*FLEN/8, x11, x1, x6) + +inst_998: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x066 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x066 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7466; op2val:0x7466; + valaddr_reg:x7; val_offset:1948*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1948*FLEN/8, x11, x1, x6) + +inst_999: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x066 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x066 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7466; op2val:0x7466; + valaddr_reg:x7; val_offset:1950*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1950*FLEN/8, x11, x1, x6) + +inst_1000: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x22b and fs2 == 0 and fe2 == 0x1a and fm2 == 0x22b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6a2b; op2val:0x6a2b; + valaddr_reg:x7; val_offset:1952*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1952*FLEN/8, x11, x1, x6) + +inst_1001: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x22b and fs2 == 0 and fe2 == 0x1a and fm2 == 0x22b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6a2b; op2val:0x6a2b; + valaddr_reg:x7; val_offset:1954*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1954*FLEN/8, x11, x1, x6) + +inst_1002: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x22b and fs2 == 0 and fe2 == 0x1a and fm2 == 0x22b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6a2b; op2val:0x6a2b; + valaddr_reg:x7; val_offset:1956*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1956*FLEN/8, x11, x1, x6) + +inst_1003: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x22b and fs2 == 0 and fe2 == 0x1a and fm2 == 0x22b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6a2b; op2val:0x6a2b; + valaddr_reg:x7; val_offset:1958*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1958*FLEN/8, x11, x1, x6) + +inst_1004: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x22b and fs2 == 0 and fe2 == 0x1a and fm2 == 0x22b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6a2b; op2val:0x6a2b; + valaddr_reg:x7; val_offset:1960*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1960*FLEN/8, x11, x1, x6) + +inst_1005: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x017 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x017 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7817; op2val:0x7817; + valaddr_reg:x7; val_offset:1962*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1962*FLEN/8, x11, x1, x6) + +inst_1006: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x017 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x017 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7817; op2val:0x7817; + valaddr_reg:x7; val_offset:1964*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1964*FLEN/8, x11, x1, x6) + +inst_1007: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x017 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x017 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7817; op2val:0x7817; + valaddr_reg:x7; val_offset:1966*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1966*FLEN/8, x11, x1, x6) + +inst_1008: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x017 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x017 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7817; op2val:0x7817; + valaddr_reg:x7; val_offset:1968*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1968*FLEN/8, x11, x1, x6) + +inst_1009: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x017 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x017 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7817; op2val:0x7817; + valaddr_reg:x7; val_offset:1970*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1970*FLEN/8, x11, x1, x6) + +inst_1010: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x119 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x119 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7119; op2val:0x7119; + valaddr_reg:x7; val_offset:1972*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1972*FLEN/8, x11, x1, x6) + +inst_1011: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x119 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x119 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7119; op2val:0x7119; + valaddr_reg:x7; val_offset:1974*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1974*FLEN/8, x11, x1, x6) + +inst_1012: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x119 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x119 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7119; op2val:0x7119; + valaddr_reg:x7; val_offset:1976*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1976*FLEN/8, x11, x1, x6) + +inst_1013: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x119 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x119 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7119; op2val:0x7119; + valaddr_reg:x7; val_offset:1978*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1978*FLEN/8, x11, x1, x6) + +inst_1014: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x119 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x119 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7119; op2val:0x7119; + valaddr_reg:x7; val_offset:1980*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1980*FLEN/8, x11, x1, x6) + +inst_1015: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x30f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b0f; op2val:0x7b0f; + valaddr_reg:x7; val_offset:1982*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1982*FLEN/8, x11, x1, x6) + +inst_1016: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x30f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b0f; op2val:0x7b0f; + valaddr_reg:x7; val_offset:1984*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1984*FLEN/8, x11, x1, x6) + +inst_1017: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x30f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b0f; op2val:0x7b0f; + valaddr_reg:x7; val_offset:1986*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1986*FLEN/8, x11, x1, x6) + +inst_1018: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x30f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b0f; op2val:0x7b0f; + valaddr_reg:x7; val_offset:1988*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1988*FLEN/8, x11, x1, x6) + +inst_1019: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x30f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b0f; op2val:0x7b0f; + valaddr_reg:x7; val_offset:1990*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1990*FLEN/8, x11, x1, x6) + +inst_1020: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x189 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x189 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7989; op2val:0x7989; + valaddr_reg:x7; val_offset:1992*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1992*FLEN/8, x11, x1, x6) + +inst_1021: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x189 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x189 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7989; op2val:0x7989; + valaddr_reg:x7; val_offset:1994*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1994*FLEN/8, x11, x1, x6) + +inst_1022: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x189 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x189 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7989; op2val:0x7989; + valaddr_reg:x7; val_offset:1996*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1996*FLEN/8, x11, x1, x6) + +inst_1023: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x189 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x189 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7989; op2val:0x7989; + valaddr_reg:x7; val_offset:1998*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1998*FLEN/8, x11, x1, x6) + +inst_1024: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x189 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x189 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7989; op2val:0x7989; + valaddr_reg:x7; val_offset:2000*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 2000*FLEN/8, x11, x1, x6) + +inst_1025: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1f1 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1f1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x75f1; op2val:0x75f1; + valaddr_reg:x7; val_offset:2002*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 2002*FLEN/8, x11, x1, x6) + +inst_1026: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1f1 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1f1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x75f1; op2val:0x75f1; + valaddr_reg:x7; val_offset:2004*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 2004*FLEN/8, x11, x1, x6) + +inst_1027: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1f1 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1f1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x75f1; op2val:0x75f1; + valaddr_reg:x7; val_offset:2006*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 2006*FLEN/8, x11, x1, x6) + +inst_1028: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1f1 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1f1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x75f1; op2val:0x75f1; + valaddr_reg:x7; val_offset:2008*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 2008*FLEN/8, x11, x1, x6) + +inst_1029: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1f1 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1f1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x75f1; op2val:0x75f1; + valaddr_reg:x7; val_offset:2010*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 2010*FLEN/8, x11, x1, x6) + +inst_1030: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1e3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1e3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79e3; op2val:0x79e3; + valaddr_reg:x7; val_offset:2012*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 2012*FLEN/8, x11, x1, x6) + +inst_1031: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1e3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1e3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79e3; op2val:0x79e3; + valaddr_reg:x7; val_offset:2014*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 2014*FLEN/8, x11, x1, x6) + +inst_1032: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1e3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1e3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79e3; op2val:0x79e3; + valaddr_reg:x7; val_offset:2016*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 2016*FLEN/8, x11, x1, x6) + +inst_1033: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1e3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1e3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79e3; op2val:0x79e3; + valaddr_reg:x7; val_offset:2018*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 2018*FLEN/8, x11, x1, x6) + +inst_1034: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1e3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1e3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79e3; op2val:0x79e3; + valaddr_reg:x7; val_offset:2020*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 2020*FLEN/8, x11, x1, x6) + +inst_1035: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2d8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ad8; op2val:0x7ad8; + valaddr_reg:x7; val_offset:2022*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 2022*FLEN/8, x11, x1, x6) + +inst_1036: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2d8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ad8; op2val:0x7ad8; + valaddr_reg:x7; val_offset:2024*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 2024*FLEN/8, x11, x1, x6) + +inst_1037: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2d8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ad8; op2val:0x7ad8; + valaddr_reg:x7; val_offset:2026*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 2026*FLEN/8, x11, x1, x6) + +inst_1038: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2d8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ad8; op2val:0x7ad8; + valaddr_reg:x7; val_offset:2028*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 2028*FLEN/8, x11, x1, x6) + +inst_1039: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2d8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ad8; op2val:0x7ad8; + valaddr_reg:x7; val_offset:2030*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 2030*FLEN/8, x11, x1, x6) + +inst_1040: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ad and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ad and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bad; op2val:0x7bad; + valaddr_reg:x7; val_offset:2032*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 2032*FLEN/8, x11, x1, x6) + +inst_1041: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ad and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ad and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bad; op2val:0x7bad; + valaddr_reg:x7; val_offset:2034*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 2034*FLEN/8, x11, x1, x6) + +inst_1042: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ad and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ad and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bad; op2val:0x7bad; + valaddr_reg:x7; val_offset:2036*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 2036*FLEN/8, x11, x1, x6) + +inst_1043: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ad and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ad and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bad; op2val:0x7bad; + valaddr_reg:x7; val_offset:2038*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 2038*FLEN/8, x11, x1, x6) + +inst_1044: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ad and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ad and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bad; op2val:0x7bad; + valaddr_reg:x7; val_offset:2040*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 2040*FLEN/8, x11, x1, x6) + +inst_1045: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1a3 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1a3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x71a3; op2val:0x71a3; + valaddr_reg:x7; val_offset:2042*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 2042*FLEN/8, x11, x1, x6) + +inst_1046: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1a3 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1a3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x71a3; op2val:0x71a3; + valaddr_reg:x7; val_offset:2044*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 2044*FLEN/8, x11, x1, x6) + +inst_1047: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1a3 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1a3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x71a3; op2val:0x71a3; + valaddr_reg:x7; val_offset:2046*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 2046*FLEN/8, x11, x1, x6) + +inst_1048: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1a3 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1a3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x71a3; op2val:0x71a3; + valaddr_reg:x7; val_offset:2048*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 2048*FLEN/8, x11, x1, x6) + +inst_1049: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1a3 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1a3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x71a3; op2val:0x71a3; + valaddr_reg:x7; val_offset:2050*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 2050*FLEN/8, x11, x1, x6) +RVTEST_SIGBASE(x1,signature_x1_10) + +inst_1050: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2f5 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2f5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x72f5; op2val:0x72f5; + valaddr_reg:x7; val_offset:2052*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 2052*FLEN/8, x11, x1, x6) + +inst_1051: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2f5 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2f5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x72f5; op2val:0x72f5; + valaddr_reg:x7; val_offset:2054*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 2054*FLEN/8, x11, x1, x6) + +inst_1052: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2f5 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2f5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x72f5; op2val:0x72f5; + valaddr_reg:x7; val_offset:2056*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 2056*FLEN/8, x11, x1, x6) + +inst_1053: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2f5 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2f5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x72f5; op2val:0x72f5; + valaddr_reg:x7; val_offset:2058*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 2058*FLEN/8, x11, x1, x6) + +inst_1054: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2f5 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2f5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x72f5; op2val:0x72f5; + valaddr_reg:x7; val_offset:2060*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 2060*FLEN/8, x11, x1, x6) + +inst_1055: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a0f; op2val:0x7a0f; + valaddr_reg:x7; val_offset:2062*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 2062*FLEN/8, x11, x1, x6) + +inst_1056: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a0f; op2val:0x7a0f; + valaddr_reg:x7; val_offset:2064*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 2064*FLEN/8, x11, x1, x6) + +inst_1057: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a0f; op2val:0x7a0f; + valaddr_reg:x7; val_offset:2066*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 2066*FLEN/8, x11, x1, x6) + +inst_1058: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a0f; op2val:0x7a0f; + valaddr_reg:x7; val_offset:2068*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 2068*FLEN/8, x11, x1, x6) + +inst_1059: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a0f; op2val:0x7a0f; + valaddr_reg:x7; val_offset:2070*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 2070*FLEN/8, x11, x1, x6) + +inst_1060: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x173 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x173 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7973; op2val:0x7973; + valaddr_reg:x7; val_offset:2072*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 2072*FLEN/8, x11, x1, x6) + +inst_1061: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x173 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x173 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7973; op2val:0x7973; + valaddr_reg:x7; val_offset:2074*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 2074*FLEN/8, x11, x1, x6) + +inst_1062: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x173 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x173 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7973; op2val:0x7973; + valaddr_reg:x7; val_offset:2076*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 2076*FLEN/8, x11, x1, x6) + +inst_1063: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x173 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x173 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7973; op2val:0x7973; + valaddr_reg:x7; val_offset:2078*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 2078*FLEN/8, x11, x1, x6) + +inst_1064: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x173 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x173 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7973; op2val:0x7973; + valaddr_reg:x7; val_offset:2080*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 2080*FLEN/8, x11, x1, x6) + +inst_1065: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x190 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x190 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7590; op2val:0x7590; + valaddr_reg:x7; val_offset:2082*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 2082*FLEN/8, x11, x1, x6) + +inst_1066: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x190 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x190 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7590; op2val:0x7590; + valaddr_reg:x7; val_offset:2084*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 2084*FLEN/8, x11, x1, x6) + +inst_1067: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x190 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x190 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7590; op2val:0x7590; + valaddr_reg:x7; val_offset:2086*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 2086*FLEN/8, x11, x1, x6) + +inst_1068: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x190 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x190 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7590; op2val:0x7590; + valaddr_reg:x7; val_offset:2088*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 2088*FLEN/8, x11, x1, x6) + +inst_1069: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x190 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x190 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7590; op2val:0x7590; + valaddr_reg:x7; val_offset:2090*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 2090*FLEN/8, x11, x1, x6) + +inst_1070: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x145 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x145 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7145; op2val:0x7145; + valaddr_reg:x7; val_offset:2092*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 2092*FLEN/8, x11, x1, x6) + +inst_1071: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x145 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x145 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7145; op2val:0x7145; + valaddr_reg:x7; val_offset:2094*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 2094*FLEN/8, x11, x1, x6) + +inst_1072: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x145 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x145 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7145; op2val:0x7145; + valaddr_reg:x7; val_offset:2096*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 2096*FLEN/8, x11, x1, x6) + +inst_1073: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x145 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x145 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7145; op2val:0x7145; + valaddr_reg:x7; val_offset:2098*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 2098*FLEN/8, x11, x1, x6) + +inst_1074: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x145 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x145 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7145; op2val:0x7145; + valaddr_reg:x7; val_offset:2100*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 2100*FLEN/8, x11, x1, x6) + +inst_1075: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x135 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x135 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6935; op2val:0x6935; + valaddr_reg:x7; val_offset:2102*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 2102*FLEN/8, x11, x1, x6) + +inst_1076: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x135 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x135 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6935; op2val:0x6935; + valaddr_reg:x7; val_offset:2104*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 2104*FLEN/8, x11, x1, x6) + +inst_1077: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x135 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x135 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6935; op2val:0x6935; + valaddr_reg:x7; val_offset:2106*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 2106*FLEN/8, x11, x1, x6) + +inst_1078: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x135 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x135 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6935; op2val:0x6935; + valaddr_reg:x7; val_offset:2108*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 2108*FLEN/8, x11, x1, x6) + +inst_1079: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x135 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x135 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6935; op2val:0x6935; + valaddr_reg:x7; val_offset:2110*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 2110*FLEN/8, x11, x1, x6) + +inst_1080: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x275 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x275 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a75; op2val:0x7a75; + valaddr_reg:x7; val_offset:2112*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 2112*FLEN/8, x11, x1, x6) + +inst_1081: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x275 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x275 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a75; op2val:0x7a75; + valaddr_reg:x7; val_offset:2114*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 2114*FLEN/8, x11, x1, x6) + +inst_1082: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x275 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x275 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a75; op2val:0x7a75; + valaddr_reg:x7; val_offset:2116*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 2116*FLEN/8, x11, x1, x6) + +inst_1083: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x275 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x275 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a75; op2val:0x7a75; + valaddr_reg:x7; val_offset:2118*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 2118*FLEN/8, x11, x1, x6) + +inst_1084: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x275 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x275 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a75; op2val:0x7a75; + valaddr_reg:x7; val_offset:2120*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 2120*FLEN/8, x11, x1, x6) + +inst_1085: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x047 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x047 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7447; op2val:0x7447; + valaddr_reg:x7; val_offset:2122*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 2122*FLEN/8, x11, x1, x6) + +inst_1086: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x047 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x047 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7447; op2val:0x7447; + valaddr_reg:x7; val_offset:2124*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 2124*FLEN/8, x11, x1, x6) + +inst_1087: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x047 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x047 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7447; op2val:0x7447; + valaddr_reg:x7; val_offset:2126*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 2126*FLEN/8, x11, x1, x6) + +inst_1088: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x047 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x047 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7447; op2val:0x7447; + valaddr_reg:x7; val_offset:2128*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 2128*FLEN/8, x11, x1, x6) + +inst_1089: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x047 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x047 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7447; op2val:0x7447; + valaddr_reg:x7; val_offset:2130*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 2130*FLEN/8, x11, x1, x6) + +inst_1090: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ab and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ab and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bab; op2val:0x7bab; + valaddr_reg:x7; val_offset:2132*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 2132*FLEN/8, x11, x1, x6) + +inst_1091: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ab and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ab and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bab; op2val:0x7bab; + valaddr_reg:x7; val_offset:2134*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 2134*FLEN/8, x11, x1, x6) + +inst_1092: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ab and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ab and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bab; op2val:0x7bab; + valaddr_reg:x7; val_offset:2136*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 2136*FLEN/8, x11, x1, x6) + +inst_1093: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ab and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ab and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bab; op2val:0x7bab; + valaddr_reg:x7; val_offset:2138*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 2138*FLEN/8, x11, x1, x6) + +inst_1094: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ab and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ab and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bab; op2val:0x7bab; + valaddr_reg:x7; val_offset:2140*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 2140*FLEN/8, x11, x1, x6) + +inst_1095: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x233 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x233 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a33; op2val:0x7a33; + valaddr_reg:x7; val_offset:2142*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 2142*FLEN/8, x11, x1, x6) + +inst_1096: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x233 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x233 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a33; op2val:0x7a33; + valaddr_reg:x7; val_offset:2144*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 2144*FLEN/8, x11, x1, x6) + +inst_1097: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x233 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x233 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a33; op2val:0x7a33; + valaddr_reg:x7; val_offset:2146*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 2146*FLEN/8, x11, x1, x6) + +inst_1098: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x233 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x233 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a33; op2val:0x7a33; + valaddr_reg:x7; val_offset:2148*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 2148*FLEN/8, x11, x1, x6) + +inst_1099: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x233 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x233 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a33; op2val:0x7a33; + valaddr_reg:x7; val_offset:2150*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 2150*FLEN/8, x11, x1, x6) + +inst_1100: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x146 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x146 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7946; op2val:0x7946; + valaddr_reg:x7; val_offset:2152*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 2152*FLEN/8, x11, x1, x6) + +inst_1101: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x146 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x146 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7946; op2val:0x7946; + valaddr_reg:x7; val_offset:2154*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 2154*FLEN/8, x11, x1, x6) + +inst_1102: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x146 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x146 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7946; op2val:0x7946; + valaddr_reg:x7; val_offset:2156*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 2156*FLEN/8, x11, x1, x6) + +inst_1103: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x146 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x146 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7946; op2val:0x7946; + valaddr_reg:x7; val_offset:2158*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 2158*FLEN/8, x11, x1, x6) + +inst_1104: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x146 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x146 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7946; op2val:0x7946; + valaddr_reg:x7; val_offset:2160*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 2160*FLEN/8, x11, x1, x6) + +inst_1105: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x31e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x771e; op2val:0x771e; + valaddr_reg:x7; val_offset:2162*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 2162*FLEN/8, x11, x1, x6) + +inst_1106: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x31e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x771e; op2val:0x771e; + valaddr_reg:x7; val_offset:2164*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 2164*FLEN/8, x11, x1, x6) + +inst_1107: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x31e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x771e; op2val:0x771e; + valaddr_reg:x7; val_offset:2166*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 2166*FLEN/8, x11, x1, x6) + +inst_1108: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x31e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x771e; op2val:0x771e; + valaddr_reg:x7; val_offset:2168*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 2168*FLEN/8, x11, x1, x6) + +inst_1109: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x31e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x771e; op2val:0x771e; + valaddr_reg:x7; val_offset:2170*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 2170*FLEN/8, x11, x1, x6) + +inst_1110: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x704c; op2val:0x704c; + valaddr_reg:x7; val_offset:2172*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 2172*FLEN/8, x11, x1, x6) + +inst_1111: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x704c; op2val:0x704c; + valaddr_reg:x7; val_offset:2174*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 2174*FLEN/8, x11, x1, x6) + +inst_1112: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ae and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aae; op2val:0x7aae; + valaddr_reg:x7; val_offset:2176*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 2176*FLEN/8, x11, x1, x6) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(28748,32,FLEN) +NAN_BOXED(28748,32,FLEN) +NAN_BOXED(28748,32,FLEN) +NAN_BOXED(28748,32,FLEN) +NAN_BOXED(28748,32,FLEN) +NAN_BOXED(28748,32,FLEN) +NAN_BOXED(28748,32,FLEN) +NAN_BOXED(28748,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31259,32,FLEN) +NAN_BOXED(31259,32,FLEN) +NAN_BOXED(31259,32,FLEN) +NAN_BOXED(31259,32,FLEN) +NAN_BOXED(31259,32,FLEN) +NAN_BOXED(31259,32,FLEN) +NAN_BOXED(31259,32,FLEN) +NAN_BOXED(31259,32,FLEN) +NAN_BOXED(31259,32,FLEN) +NAN_BOXED(31259,32,FLEN) +NAN_BOXED(30700,32,FLEN) +NAN_BOXED(30700,32,FLEN) +NAN_BOXED(30700,32,FLEN) +NAN_BOXED(30700,32,FLEN) +test_dataset_1: +NAN_BOXED(30700,32,FLEN) +NAN_BOXED(30700,32,FLEN) +NAN_BOXED(30700,32,FLEN) +NAN_BOXED(30700,32,FLEN) +NAN_BOXED(30700,32,FLEN) +NAN_BOXED(30700,32,FLEN) +NAN_BOXED(31029,32,FLEN) +NAN_BOXED(31029,32,FLEN) +NAN_BOXED(31029,32,FLEN) +NAN_BOXED(31029,32,FLEN) +NAN_BOXED(31029,32,FLEN) +NAN_BOXED(31029,32,FLEN) +NAN_BOXED(31029,32,FLEN) +NAN_BOXED(31029,32,FLEN) +NAN_BOXED(31029,32,FLEN) +NAN_BOXED(31029,32,FLEN) +NAN_BOXED(28161,32,FLEN) +NAN_BOXED(28161,32,FLEN) +NAN_BOXED(28161,32,FLEN) +NAN_BOXED(28161,32,FLEN) +NAN_BOXED(28161,32,FLEN) +NAN_BOXED(28161,32,FLEN) +NAN_BOXED(28161,32,FLEN) +NAN_BOXED(28161,32,FLEN) +test_dataset_2: +NAN_BOXED(28161,16,FLEN) +NAN_BOXED(28161,16,FLEN) +NAN_BOXED(31406,16,FLEN) +NAN_BOXED(31406,16,FLEN) +NAN_BOXED(31406,16,FLEN) +NAN_BOXED(31406,16,FLEN) +NAN_BOXED(31406,16,FLEN) +NAN_BOXED(31406,16,FLEN) +NAN_BOXED(31406,16,FLEN) +NAN_BOXED(31406,16,FLEN) +NAN_BOXED(31406,16,FLEN) +NAN_BOXED(31406,16,FLEN) +NAN_BOXED(31256,16,FLEN) +NAN_BOXED(31256,16,FLEN) +NAN_BOXED(31256,16,FLEN) +NAN_BOXED(31256,16,FLEN) +NAN_BOXED(31256,16,FLEN) +NAN_BOXED(31256,16,FLEN) +NAN_BOXED(31256,16,FLEN) +NAN_BOXED(31256,16,FLEN) +NAN_BOXED(31256,16,FLEN) +NAN_BOXED(31256,16,FLEN) +NAN_BOXED(30495,16,FLEN) +NAN_BOXED(30495,16,FLEN) +NAN_BOXED(30495,16,FLEN) +NAN_BOXED(30495,16,FLEN) +NAN_BOXED(30495,16,FLEN) +NAN_BOXED(30495,16,FLEN) +NAN_BOXED(30495,16,FLEN) +NAN_BOXED(30495,16,FLEN) +NAN_BOXED(30495,16,FLEN) +NAN_BOXED(30495,16,FLEN) +NAN_BOXED(29521,16,FLEN) +NAN_BOXED(29521,16,FLEN) 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+NAN_BOXED(28953,16,FLEN) +NAN_BOXED(28953,16,FLEN) +NAN_BOXED(28953,16,FLEN) +NAN_BOXED(28953,16,FLEN) +NAN_BOXED(28953,16,FLEN) +NAN_BOXED(28953,16,FLEN) +NAN_BOXED(28953,16,FLEN) +NAN_BOXED(28953,16,FLEN) +NAN_BOXED(28953,16,FLEN) +NAN_BOXED(28953,16,FLEN) +NAN_BOXED(31503,16,FLEN) +NAN_BOXED(31503,16,FLEN) +NAN_BOXED(31503,16,FLEN) +NAN_BOXED(31503,16,FLEN) +NAN_BOXED(31503,16,FLEN) +NAN_BOXED(31503,16,FLEN) +NAN_BOXED(31503,16,FLEN) +NAN_BOXED(31503,16,FLEN) +NAN_BOXED(31503,16,FLEN) +NAN_BOXED(31503,16,FLEN) +NAN_BOXED(31113,16,FLEN) +NAN_BOXED(31113,16,FLEN) +NAN_BOXED(31113,16,FLEN) +NAN_BOXED(31113,16,FLEN) +NAN_BOXED(31113,16,FLEN) +NAN_BOXED(31113,16,FLEN) +NAN_BOXED(31113,16,FLEN) +NAN_BOXED(31113,16,FLEN) +NAN_BOXED(31113,16,FLEN) +NAN_BOXED(31113,16,FLEN) +NAN_BOXED(30193,16,FLEN) +NAN_BOXED(30193,16,FLEN) +NAN_BOXED(30193,16,FLEN) +NAN_BOXED(30193,16,FLEN) +NAN_BOXED(30193,16,FLEN) +NAN_BOXED(30193,16,FLEN) +NAN_BOXED(30193,16,FLEN) +NAN_BOXED(30193,16,FLEN) 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+NAN_BOXED(30494,16,FLEN) +NAN_BOXED(30494,16,FLEN) +NAN_BOXED(30494,16,FLEN) +NAN_BOXED(30494,16,FLEN) +NAN_BOXED(30494,16,FLEN) +NAN_BOXED(30494,16,FLEN) +NAN_BOXED(30494,16,FLEN) +NAN_BOXED(30494,16,FLEN) +NAN_BOXED(30494,16,FLEN) +NAN_BOXED(30494,16,FLEN) +NAN_BOXED(28748,16,FLEN) +NAN_BOXED(28748,16,FLEN) +NAN_BOXED(28748,16,FLEN) +NAN_BOXED(28748,16,FLEN) +NAN_BOXED(31406,16,FLEN) +NAN_BOXED(31406,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 26*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x6_0: + .fill 26*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_2: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_3: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_4: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_5: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_6: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_7: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_8: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_9: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_10: + .fill 126*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fsub_b4-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fsub_b4-01.S new file mode 100644 index 000000000..d6c89906b --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fsub_b4-01.S @@ -0,0 +1,1400 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 06:02:02 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fsub.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fsub.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fsub_b4 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fsub_b4) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x5,test_dataset_0) +RVTEST_SIGBASE(x4,signature_x4_1) + +inst_0: +// rs1 == rs2 == rd, rs1==x14, rs2==x14, rd==x14,fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2eb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x14; op2:x14; dest:x14; op1val:0x704c; op2val:0x704c; + valaddr_reg:x5; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x14, x14, x14, dyn, 0, 0, x5, 0*FLEN/8, x8, x4, x6) + +inst_1: +// rs2 == rd != rs1, rs1==x21, rs2==x11, rd==x11,fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2eb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x21; op2:x11; dest:x11; op1val:0x704c; op2val:0xfaeb; + valaddr_reg:x5; val_offset:2*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x11, x21, x11, dyn, 32, 0, x5, 2*FLEN/8, x8, x4, x6) + +inst_2: +// rs1 == rd != rs2, rs1==x0, rs2==x12, rd==x0,fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2eb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x0; op2:x12; dest:x0; op1val:0x0; op2val:0xfaeb; + valaddr_reg:x5; val_offset:4*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x0, x0, x12, dyn, 64, 0, x5, 4*FLEN/8, x8, x4, x6) + +inst_3: +// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==x23, rs2==x27, rd==x21,fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2eb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x23; op2:x27; dest:x21; op1val:0x704c; op2val:0xfaeb; + valaddr_reg:x5; val_offset:6*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x21, x23, x27, dyn, 96, 0, x5, 6*FLEN/8, x8, x4, x6) + +inst_4: +// rs1 == rs2 != rd, rs1==x16, rs2==x16, rd==x30,fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2eb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x16; op2:x16; dest:x30; op1val:0x704c; op2val:0x704c; + valaddr_reg:x5; val_offset:8*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x30, x16, x16, dyn, 128, 0, x5, 8*FLEN/8, x8, x4, x6) + +inst_5: +// rs1==x19, rs2==x13, rd==x29,fs1 == 0 and fe1 == 0x1e and fm1 == 0x21b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x19; op2:x13; dest:x29; op1val:0x7a1b; op2val:0x7bff; + valaddr_reg:x5; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x29, x19, x13, dyn, 0, 0, x5, 10*FLEN/8, x8, x4, x6) + +inst_6: +// rs1==x2, rs2==x23, rd==x25,fs1 == 0 and fe1 == 0x1e and fm1 == 0x21b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x2; op2:x23; dest:x25; op1val:0x7a1b; op2val:0x7bff; + valaddr_reg:x5; val_offset:12*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x25, x2, x23, dyn, 32, 0, x5, 12*FLEN/8, x8, x4, x6) + +inst_7: +// rs1==x22, rs2==x1, rd==x17,fs1 == 0 and fe1 == 0x1e and fm1 == 0x21b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x22; op2:x1; dest:x17; op1val:0x7a1b; op2val:0x7bff; + valaddr_reg:x5; val_offset:14*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x17, x22, x1, dyn, 64, 0, x5, 14*FLEN/8, x8, x4, x6) + +inst_8: +// rs1==x28, rs2==x7, rd==x16,fs1 == 0 and fe1 == 0x1e and fm1 == 0x21b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x28; op2:x7; dest:x16; op1val:0x7a1b; op2val:0x7bff; + valaddr_reg:x5; val_offset:16*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x16, x28, x7, dyn, 96, 0, x5, 16*FLEN/8, x8, x4, x6) + +inst_9: +// rs1==x15, rs2==x9, rd==x3,fs1 == 0 and fe1 == 0x1e and fm1 == 0x21b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x15; op2:x9; dest:x3; op1val:0x7a1b; op2val:0x7bff; + valaddr_reg:x5; val_offset:18*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x3, x15, x9, dyn, 128, 0, x5, 18*FLEN/8, x8, x4, x6) + +inst_10: +// rs1==x10, rs2==x31, rd==x12,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ec and fs2 == 1 and fe2 == 0x1e and fm2 == 0x008 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x10; op2:x31; dest:x12; op1val:0x77ec; op2val:0xf808; + valaddr_reg:x5; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x12, x10, x31, dyn, 0, 0, x5, 20*FLEN/8, x8, x4, x6) +RVTEST_VALBASEUPD(x10,test_dataset_1) + +inst_11: +// rs1==x30, rs2==x26, rd==x31,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ec and fs2 == 1 and fe2 == 0x1e and fm2 == 0x008 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x26; dest:x31; op1val:0x77ec; op2val:0xf808; + valaddr_reg:x10; val_offset:0*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x31, x30, x26, dyn, 32, 0, x10, 0*FLEN/8, x15, x4, x6) + +inst_12: +// rs1==x31, rs2==x8, rd==x5,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ec and fs2 == 1 and fe2 == 0x1e and fm2 == 0x008 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x31; op2:x8; dest:x5; op1val:0x77ec; op2val:0xf808; + valaddr_reg:x10; val_offset:2*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x5, x31, x8, dyn, 64, 0, x10, 2*FLEN/8, x15, x4, x6) +RVTEST_SIGBASE(x14,signature_x14_0) + +inst_13: +// rs1==x7, rs2==x2, rd==x19,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ec and fs2 == 1 and fe2 == 0x1e and fm2 == 0x008 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x7; op2:x2; dest:x19; op1val:0x77ec; op2val:0xf808; + valaddr_reg:x10; val_offset:4*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12*/ +TEST_FPRR_OP(fsub.h, x19, x7, x2, dyn, 96, 0, x10, 4*FLEN/8, x15, x14, x12) + +inst_14: +// rs1==x6, rs2==x18, rd==x9,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ec and fs2 == 1 and fe2 == 0x1e and fm2 == 0x008 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x6; op2:x18; dest:x9; op1val:0x77ec; op2val:0xf808; + valaddr_reg:x10; val_offset:6*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12*/ +TEST_FPRR_OP(fsub.h, x9, x6, x18, dyn, 128, 0, x10, 6*FLEN/8, x15, x14, x12) + +inst_15: +// rs1==x29, rs2==x6, rd==x22,fs1 == 0 and fe1 == 0x1e and fm1 == 0x135 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x29; op2:x6; dest:x22; op1val:0x7935; op2val:0x7bff; + valaddr_reg:x10; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12*/ +TEST_FPRR_OP(fsub.h, x22, x29, x6, dyn, 0, 0, x10, 8*FLEN/8, x15, x14, x12) + +inst_16: +// rs1==x11, rs2==x21, rd==x7,fs1 == 0 and fe1 == 0x1e and fm1 == 0x135 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x11; op2:x21; dest:x7; op1val:0x7935; op2val:0x7bff; + valaddr_reg:x10; val_offset:10*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12*/ +TEST_FPRR_OP(fsub.h, x7, x11, x21, dyn, 32, 0, x10, 10*FLEN/8, x15, x14, x12) + +inst_17: +// rs1==x25, rs2==x17, rd==x8,fs1 == 0 and fe1 == 0x1e and fm1 == 0x135 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x25; op2:x17; dest:x8; op1val:0x7935; op2val:0x7bff; + valaddr_reg:x10; val_offset:12*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12*/ +TEST_FPRR_OP(fsub.h, x8, x25, x17, dyn, 64, 0, x10, 12*FLEN/8, x15, x14, x12) + +inst_18: +// rs1==x26, rs2==x0, rd==x18,fs1 == 0 and fe1 == 0x1e and fm1 == 0x135 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x26; op2:x0; dest:x18; op1val:0x7935; op2val:0x0; + valaddr_reg:x10; val_offset:14*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12*/ +TEST_FPRR_OP(fsub.h, x18, x26, x0, dyn, 96, 0, x10, 14*FLEN/8, x15, x14, x12) + +inst_19: +// rs1==x5, rs2==x19, rd==x4,fs1 == 0 and fe1 == 0x1e and fm1 == 0x135 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x5; op2:x19; dest:x4; op1val:0x7935; op2val:0x7bff; + valaddr_reg:x10; val_offset:16*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12*/ +TEST_FPRR_OP(fsub.h, x4, x5, x19, dyn, 128, 0, x10, 16*FLEN/8, x15, x14, x12) + +inst_20: +// rs1==x3, rs2==x24, rd==x6,fs1 == 0 and fe1 == 0x1b and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x33e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x3; op2:x24; dest:x6; op1val:0x6e01; op2val:0xfb3e; + valaddr_reg:x10; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12*/ +TEST_FPRR_OP(fsub.h, x6, x3, x24, dyn, 0, 0, x10, 18*FLEN/8, x15, x14, x12) + +inst_21: +// rs1==x1, rs2==x4, rd==x2,fs1 == 0 and fe1 == 0x1b and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x33e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x1; op2:x4; dest:x2; op1val:0x6e01; op2val:0xfb3e; + valaddr_reg:x10; val_offset:20*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12*/ +TEST_FPRR_OP(fsub.h, x2, x1, x4, dyn, 32, 0, x10, 20*FLEN/8, x15, x14, x12) + +inst_22: +// rs1==x18, rs2==x25, rd==x26,fs1 == 0 and fe1 == 0x1b and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x33e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x18; op2:x25; dest:x26; op1val:0x6e01; op2val:0xfb3e; + valaddr_reg:x10; val_offset:22*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12*/ +TEST_FPRR_OP(fsub.h, x26, x18, x25, dyn, 64, 0, x10, 22*FLEN/8, x15, x14, x12) + +inst_23: +// rs1==x4, rs2==x20, rd==x13,fs1 == 0 and fe1 == 0x1b and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x33e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x4; op2:x20; dest:x13; op1val:0x6e01; op2val:0xfb3e; + valaddr_reg:x10; val_offset:24*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x12*/ +TEST_FPRR_OP(fsub.h, x13, x4, x20, dyn, 96, 0, x10, 24*FLEN/8, x15, x14, x12) +RVTEST_VALBASEUPD(x4,test_dataset_2) + +inst_24: +// rs1==x20, rs2==x3, rd==x27,fs1 == 0 and fe1 == 0x1b and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x33e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x20; op2:x3; dest:x27; op1val:0x6e01; op2val:0xfb3e; + valaddr_reg:x4; val_offset:0*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x12*/ +TEST_FPRR_OP(fsub.h, x27, x20, x3, dyn, 128, 0, x4, 0*FLEN/8, x6, x14, x12) + +inst_25: +// rs1==x27, rs2==x5, rd==x23,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x27; op2:x5; dest:x23; op1val:0x7aae; op2val:0x7bff; + valaddr_reg:x4; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x12*/ +TEST_FPRR_OP(fsub.h, x23, x27, x5, dyn, 0, 0, x4, 2*FLEN/8, x6, x14, x12) + +inst_26: +// rs1==x13, rs2==x10, rd==x20,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x13; op2:x10; dest:x20; op1val:0x7aae; op2val:0x7bff; + valaddr_reg:x4; val_offset:4*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x12*/ +TEST_FPRR_OP(fsub.h, x20, x13, x10, dyn, 32, 0, x4, 4*FLEN/8, x6, x14, x12) + +inst_27: +// rs1==x24, rs2==x28, rd==x10,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x24; op2:x28; dest:x10; op1val:0x7aae; op2val:0x7bff; + valaddr_reg:x4; val_offset:6*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x12*/ +TEST_FPRR_OP(fsub.h, x10, x24, x28, dyn, 64, 0, x4, 6*FLEN/8, x6, x14, x12) + +inst_28: +// rs1==x17, rs2==x29, rd==x1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x17; op2:x29; dest:x1; op1val:0x7aae; op2val:0x7bff; + valaddr_reg:x4; val_offset:8*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x1, x17, x29, dyn, 96, 0, x4, 8*FLEN/8, x6, x14, x2) + +inst_29: +// rs1==x8, rs2==x22, rd==x24,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x8; op2:x22; dest:x24; op1val:0x7aae; op2val:0x7bff; + valaddr_reg:x4; val_offset:10*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x24, x8, x22, dyn, 128, 0, x4, 10*FLEN/8, x6, x14, x2) + +inst_30: +// rs1==x12, rs2==x15, rd==x28,fs1 == 0 and fe1 == 0x1e and fm1 == 0x218 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x39a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x12; op2:x15; dest:x28; op1val:0x7a18; op2val:0xf39a; + valaddr_reg:x4; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x28, x12, x15, dyn, 0, 0, x4, 12*FLEN/8, x6, x14, x2) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_31: +// rs1==x9, rs2==x30, rd==x15,fs1 == 0 and fe1 == 0x1e and fm1 == 0x218 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x39a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x9; op2:x30; dest:x15; op1val:0x7a18; op2val:0xf39a; + valaddr_reg:x4; val_offset:14*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x15, x9, x30, dyn, 32, 0, x4, 14*FLEN/8, x6, x1, x2) + +inst_32: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x218 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x39a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a18; op2val:0xf39a; + valaddr_reg:x4; val_offset:16*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x4, 16*FLEN/8, x6, x1, x2) + +inst_33: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x218 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x39a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a18; op2val:0xf39a; + valaddr_reg:x4; val_offset:18*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x4, 18*FLEN/8, x6, x1, x2) + +inst_34: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x218 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x39a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a18; op2val:0xf39a; + valaddr_reg:x4; val_offset:20*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x4, 20*FLEN/8, x6, x1, x2) + +inst_35: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x771f; op2val:0x7bff; + valaddr_reg:x4; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 22*FLEN/8, x6, x1, x2) + +inst_36: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x771f; op2val:0x7bff; + valaddr_reg:x4; val_offset:24*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x4, 24*FLEN/8, x6, x1, x2) + +inst_37: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x771f; op2val:0x7bff; + valaddr_reg:x4; val_offset:26*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x4, 26*FLEN/8, x6, x1, x2) + +inst_38: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x771f; op2val:0x7bff; + valaddr_reg:x4; val_offset:28*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x4, 28*FLEN/8, x6, x1, x2) + +inst_39: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x771f; op2val:0x7bff; + valaddr_reg:x4; val_offset:30*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x4, 30*FLEN/8, x6, x1, x2) + +inst_40: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x351 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x22a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7351; op2val:0xfa2a; + valaddr_reg:x4; val_offset:32*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 32*FLEN/8, x6, x1, x2) + +inst_41: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x351 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x22a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7351; op2val:0xfa2a; + valaddr_reg:x4; val_offset:34*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x4, 34*FLEN/8, x6, x1, x2) + +inst_42: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x351 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x22a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7351; op2val:0xfa2a; + valaddr_reg:x4; val_offset:36*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x4, 36*FLEN/8, x6, x1, x2) + +inst_43: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x351 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x22a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7351; op2val:0xfa2a; + valaddr_reg:x4; val_offset:38*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x4, 38*FLEN/8, x6, x1, x2) + +inst_44: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x351 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x22a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7351; op2val:0xfa2a; + valaddr_reg:x4; val_offset:40*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x4, 40*FLEN/8, x6, x1, x2) + +inst_45: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x335 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b35; op2val:0x7bff; + valaddr_reg:x4; val_offset:42*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 42*FLEN/8, x6, x1, x2) + +inst_46: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x335 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b35; op2val:0x7bff; + valaddr_reg:x4; val_offset:44*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x4, 44*FLEN/8, x6, x1, x2) + +inst_47: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x335 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b35; op2val:0x7bff; + valaddr_reg:x4; val_offset:46*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x4, 46*FLEN/8, x6, x1, x2) + +inst_48: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x335 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b35; op2val:0x7bff; + valaddr_reg:x4; val_offset:48*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x4, 48*FLEN/8, x6, x1, x2) + +inst_49: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x335 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b35; op2val:0x7bff; + valaddr_reg:x4; val_offset:50*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x4, 50*FLEN/8, x6, x1, x2) + +inst_50: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x283 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ca and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6683; op2val:0xfbca; + valaddr_reg:x4; val_offset:52*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 52*FLEN/8, x6, x1, x2) + +inst_51: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x283 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ca and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6683; op2val:0xfbca; + valaddr_reg:x4; val_offset:54*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x4, 54*FLEN/8, x6, x1, x2) + +inst_52: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x283 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ca and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6683; op2val:0xfbca; + valaddr_reg:x4; val_offset:56*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x4, 56*FLEN/8, x6, x1, x2) + +inst_53: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x283 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ca and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6683; op2val:0xfbca; + valaddr_reg:x4; val_offset:58*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x4, 58*FLEN/8, x6, x1, x2) + +inst_54: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x283 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ca and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6683; op2val:0xfbca; + valaddr_reg:x4; val_offset:60*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x4, 60*FLEN/8, x6, x1, x2) + +inst_55: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x382 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b82; op2val:0x7bff; + valaddr_reg:x4; val_offset:62*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 62*FLEN/8, x6, x1, x2) + +inst_56: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x382 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b82; op2val:0x7bff; + valaddr_reg:x4; val_offset:64*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x4, 64*FLEN/8, x6, x1, x2) + +inst_57: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x382 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b82; op2val:0x7bff; + valaddr_reg:x4; val_offset:66*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x4, 66*FLEN/8, x6, x1, x2) + +inst_58: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x382 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b82; op2val:0x7bff; + valaddr_reg:x4; val_offset:68*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x4, 68*FLEN/8, x6, x1, x2) + +inst_59: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x382 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b82; op2val:0x7bff; + valaddr_reg:x4; val_offset:70*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x4, 70*FLEN/8, x6, x1, x2) + +inst_60: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ed and fs2 == 1 and fe2 == 0x1e and fm2 == 0x243 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x72ed; op2val:0xfa43; + valaddr_reg:x4; val_offset:72*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 72*FLEN/8, x6, x1, x2) + +inst_61: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ed and fs2 == 1 and fe2 == 0x1e and fm2 == 0x243 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x72ed; op2val:0xfa43; + valaddr_reg:x4; val_offset:74*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x4, 74*FLEN/8, x6, x1, x2) + +inst_62: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ed and fs2 == 1 and fe2 == 0x1e and fm2 == 0x243 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x72ed; op2val:0xfa43; + valaddr_reg:x4; val_offset:76*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x4, 76*FLEN/8, x6, x1, x2) + +inst_63: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ed and fs2 == 1 and fe2 == 0x1e and fm2 == 0x243 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x72ed; op2val:0xfa43; + valaddr_reg:x4; val_offset:78*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x4, 78*FLEN/8, x6, x1, x2) + +inst_64: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ed and fs2 == 1 and fe2 == 0x1e and fm2 == 0x243 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x72ed; op2val:0xfa43; + valaddr_reg:x4; val_offset:80*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x4, 80*FLEN/8, x6, x1, x2) + +inst_65: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x36f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x676f; op2val:0x7bff; + valaddr_reg:x4; val_offset:82*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 82*FLEN/8, x6, x1, x2) + +inst_66: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x36f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x676f; op2val:0x7bff; + valaddr_reg:x4; val_offset:84*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x4, 84*FLEN/8, x6, x1, x2) + +inst_67: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x36f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x676f; op2val:0x7bff; + valaddr_reg:x4; val_offset:86*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x4, 86*FLEN/8, x6, x1, x2) + +inst_68: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x36f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x676f; op2val:0x7bff; + valaddr_reg:x4; val_offset:88*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x4, 88*FLEN/8, x6, x1, x2) + +inst_69: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x36f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x676f; op2val:0x7bff; + valaddr_reg:x4; val_offset:90*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x4, 90*FLEN/8, x6, x1, x2) + +inst_70: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x300 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7700; op2val:0x7500; + valaddr_reg:x4; val_offset:92*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 92*FLEN/8, x6, x1, x2) + +inst_71: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x300 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x100 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7700; op2val:0x7500; + valaddr_reg:x4; val_offset:94*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x4, 94*FLEN/8, x6, x1, x2) + +inst_72: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x300 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x100 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7700; op2val:0x7500; + valaddr_reg:x4; val_offset:96*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x4, 96*FLEN/8, x6, x1, x2) + +inst_73: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x300 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x100 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7700; op2val:0x7500; + valaddr_reg:x4; val_offset:98*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x4, 98*FLEN/8, x6, x1, x2) + +inst_74: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x300 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x100 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7700; op2val:0x7500; + valaddr_reg:x4; val_offset:100*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x4, 100*FLEN/8, x6, x1, x2) + +inst_75: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x374 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1ba and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7374; op2val:0x75ba; + valaddr_reg:x4; val_offset:102*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 102*FLEN/8, x6, x1, x2) + +inst_76: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x374 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1ba and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7374; op2val:0x75ba; + valaddr_reg:x4; val_offset:104*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x4, 104*FLEN/8, x6, x1, x2) + +inst_77: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x374 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1ba and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7374; op2val:0x75ba; + valaddr_reg:x4; val_offset:106*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x4, 106*FLEN/8, x6, x1, x2) + +inst_78: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x374 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1ba and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7374; op2val:0x75ba; + valaddr_reg:x4; val_offset:108*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x4, 108*FLEN/8, x6, x1, x2) + +inst_79: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x374 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1ba and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7374; op2val:0x75ba; + valaddr_reg:x4; val_offset:110*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x4, 110*FLEN/8, x6, x1, x2) + +inst_80: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ff and fs2 == 1 and fe2 == 0x19 and fm2 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x72ff; op2val:0xe7fc; + valaddr_reg:x4; val_offset:112*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 112*FLEN/8, x6, x1, x2) + +inst_81: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ff and fs2 == 1 and fe2 == 0x19 and fm2 == 0x3fc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x72ff; op2val:0xe7fc; + valaddr_reg:x4; val_offset:114*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x4, 114*FLEN/8, x6, x1, x2) + +inst_82: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ff and fs2 == 1 and fe2 == 0x19 and fm2 == 0x3fc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x72ff; op2val:0xe7fc; + valaddr_reg:x4; val_offset:116*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x4, 116*FLEN/8, x6, x1, x2) + +inst_83: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ff and fs2 == 1 and fe2 == 0x19 and fm2 == 0x3fc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x72ff; op2val:0xe7fc; + valaddr_reg:x4; val_offset:118*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x4, 118*FLEN/8, x6, x1, x2) + +inst_84: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ff and fs2 == 1 and fe2 == 0x19 and fm2 == 0x3fc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x72ff; op2val:0xe7fc; + valaddr_reg:x4; val_offset:120*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x4, 120*FLEN/8, x6, x1, x2) + +inst_85: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x050 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74a2; op2val:0x7850; + valaddr_reg:x4; val_offset:122*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 122*FLEN/8, x6, x1, x2) + +inst_86: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x050 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74a2; op2val:0x7850; + valaddr_reg:x4; val_offset:124*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x4, 124*FLEN/8, x6, x1, x2) + +inst_87: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x050 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74a2; op2val:0x7850; + valaddr_reg:x4; val_offset:126*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x4, 126*FLEN/8, x6, x1, x2) + +inst_88: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x050 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74a2; op2val:0x7850; + valaddr_reg:x4; val_offset:128*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x4, 128*FLEN/8, x6, x1, x2) + +inst_89: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x050 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74a2; op2val:0x7850; + valaddr_reg:x4; val_offset:130*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x4, 130*FLEN/8, x6, x1, x2) + +inst_90: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b2 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x166 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab2; op2val:0x7566; + valaddr_reg:x4; val_offset:132*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 132*FLEN/8, x6, x1, x2) + +inst_91: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b2 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x166 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab2; op2val:0x7566; + valaddr_reg:x4; val_offset:134*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x4, 134*FLEN/8, x6, x1, x2) + +inst_92: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b2 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x166 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab2; op2val:0x7566; + valaddr_reg:x4; val_offset:136*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x4, 136*FLEN/8, x6, x1, x2) + +inst_93: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b2 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x166 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab2; op2val:0x7566; + valaddr_reg:x4; val_offset:138*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x4, 138*FLEN/8, x6, x1, x2) + +inst_94: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b2 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x166 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab2; op2val:0x7566; + valaddr_reg:x4; val_offset:140*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x4, 140*FLEN/8, x6, x1, x2) + +inst_95: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x122 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7922; op2val:0x7bff; + valaddr_reg:x4; val_offset:142*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 142*FLEN/8, x6, x1, x2) + +inst_96: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x122 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7922; op2val:0x7bff; + valaddr_reg:x4; val_offset:144*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x4, 144*FLEN/8, x6, x1, x2) + +inst_97: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x122 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7922; op2val:0x7bff; + valaddr_reg:x4; val_offset:146*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x4, 146*FLEN/8, x6, x1, x2) + +inst_98: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x122 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7922; op2val:0x7bff; + valaddr_reg:x4; val_offset:148*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x4, 148*FLEN/8, x6, x1, x2) + +inst_99: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x122 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7922; op2val:0x7bff; + valaddr_reg:x4; val_offset:150*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x4, 150*FLEN/8, x6, x1, x2) + +inst_100: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ef and fs2 == 1 and fe2 == 0x17 and fm2 == 0x3a1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bef; op2val:0xdfa1; + valaddr_reg:x4; val_offset:152*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 152*FLEN/8, x6, x1, x2) + +inst_101: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ef and fs2 == 1 and fe2 == 0x17 and fm2 == 0x3a1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bef; op2val:0xdfa1; + valaddr_reg:x4; val_offset:154*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x4, 154*FLEN/8, x6, x1, x2) + +inst_102: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ef and fs2 == 1 and fe2 == 0x17 and fm2 == 0x3a1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bef; op2val:0xdfa1; + valaddr_reg:x4; val_offset:156*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x4, 156*FLEN/8, x6, x1, x2) + +inst_103: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ef and fs2 == 1 and fe2 == 0x17 and fm2 == 0x3a1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bef; op2val:0xdfa1; + valaddr_reg:x4; val_offset:158*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x4, 158*FLEN/8, x6, x1, x2) + +inst_104: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ef and fs2 == 1 and fe2 == 0x17 and fm2 == 0x3a1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bef; op2val:0xdfa1; + valaddr_reg:x4; val_offset:160*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x4, 160*FLEN/8, x6, x1, x2) + +inst_105: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3bb and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6fbb; op2val:0x7bff; + valaddr_reg:x4; val_offset:162*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 162*FLEN/8, x6, x1, x2) + +inst_106: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3bb and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6fbb; op2val:0x7bff; + valaddr_reg:x4; val_offset:164*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x4, 164*FLEN/8, x6, x1, x2) + +inst_107: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3bb and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6fbb; op2val:0x7bff; + valaddr_reg:x4; val_offset:166*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x4, 166*FLEN/8, x6, x1, x2) + +inst_108: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3bb and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6fbb; op2val:0x7bff; + valaddr_reg:x4; val_offset:168*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x4, 168*FLEN/8, x6, x1, x2) + +inst_109: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3bb and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6fbb; op2val:0x7bff; + valaddr_reg:x4; val_offset:170*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x4, 170*FLEN/8, x6, x1, x2) + +inst_110: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c4; op2val:0xfbff; + valaddr_reg:x4; val_offset:172*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 172*FLEN/8, x6, x1, x2) + +inst_111: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c4; op2val:0xfbff; + valaddr_reg:x4; val_offset:174*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x4, 174*FLEN/8, x6, x1, x2) + +inst_112: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c4; op2val:0xfbff; + valaddr_reg:x4; val_offset:176*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x4, 176*FLEN/8, x6, x1, x2) + +inst_113: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c4; op2val:0xfbff; + valaddr_reg:x4; val_offset:178*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x4, 178*FLEN/8, x6, x1, x2) + +inst_114: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c4; op2val:0xfbff; + valaddr_reg:x4; val_offset:180*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x4, 180*FLEN/8, x6, x1, x2) + +inst_115: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b7c; op2val:0x7bff; + valaddr_reg:x4; val_offset:182*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 182*FLEN/8, x6, x1, x2) + +inst_116: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b7c; op2val:0x7bff; + valaddr_reg:x4; val_offset:184*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x4, 184*FLEN/8, x6, x1, x2) + +inst_117: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b7c; op2val:0x7bff; + valaddr_reg:x4; val_offset:186*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x4, 186*FLEN/8, x6, x1, x2) + +inst_118: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b7c; op2val:0x7bff; + valaddr_reg:x4; val_offset:188*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x4, 188*FLEN/8, x6, x1, x2) + +inst_119: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b7c; op2val:0x7bff; + valaddr_reg:x4; val_offset:190*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x4, 190*FLEN/8, x6, x1, x2) + +inst_120: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aa3; op2val:0xfbff; + valaddr_reg:x4; val_offset:192*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 192*FLEN/8, x6, x1, x2) + +inst_121: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aa3; op2val:0xfbff; + valaddr_reg:x4; val_offset:194*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x4, 194*FLEN/8, x6, x1, x2) + +inst_122: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aa3; op2val:0xfbff; + valaddr_reg:x4; val_offset:196*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x4, 196*FLEN/8, x6, x1, x2) + +inst_123: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aa3; op2val:0xfbff; + valaddr_reg:x4; val_offset:198*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x4, 198*FLEN/8, x6, x1, x2) + +inst_124: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aa3; op2val:0xfbff; + valaddr_reg:x4; val_offset:200*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x4, 200*FLEN/8, x6, x1, x2) + +inst_125: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0da and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74da; op2val:0x7bff; + valaddr_reg:x4; val_offset:202*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 202*FLEN/8, x6, x1, x2) + +inst_126: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0da and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74da; op2val:0x7bff; + valaddr_reg:x4; val_offset:204*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x4, 204*FLEN/8, x6, x1, x2) + +inst_127: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0da and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74da; op2val:0x7bff; + valaddr_reg:x4; val_offset:206*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x4, 206*FLEN/8, x6, x1, x2) + +inst_128: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0da and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74da; op2val:0x7bff; + valaddr_reg:x4; val_offset:208*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x4, 208*FLEN/8, x6, x1, x2) + +inst_129: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0da and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74da; op2val:0x7bff; + valaddr_reg:x4; val_offset:210*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x4, 210*FLEN/8, x6, x1, x2) + +inst_130: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b0e; op2val:0xfbff; + valaddr_reg:x4; val_offset:212*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 212*FLEN/8, x6, x1, x2) + +inst_131: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b0e; op2val:0xfbff; + valaddr_reg:x4; val_offset:214*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x4, 214*FLEN/8, x6, x1, x2) + +inst_132: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b0e; op2val:0xfbff; + valaddr_reg:x4; val_offset:216*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x4, 216*FLEN/8, x6, x1, x2) + +inst_133: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b0e; op2val:0xfbff; + valaddr_reg:x4; val_offset:218*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x4, 218*FLEN/8, x6, x1, x2) + +inst_134: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b0e; op2val:0xfbff; + valaddr_reg:x4; val_offset:220*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x4, 220*FLEN/8, x6, x1, x2) + +inst_135: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x780a; op2val:0x7bff; + valaddr_reg:x4; val_offset:222*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 222*FLEN/8, x6, x1, x2) + +inst_136: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x780a; op2val:0x7bff; + valaddr_reg:x4; val_offset:224*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x4, 224*FLEN/8, x6, x1, x2) + +inst_137: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x780a; op2val:0x7bff; + valaddr_reg:x4; val_offset:226*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x4, 226*FLEN/8, x6, x1, x2) + +inst_138: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x780a; op2val:0x7bff; + valaddr_reg:x4; val_offset:228*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x4, 228*FLEN/8, x6, x1, x2) + +inst_139: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x780a; op2val:0x7bff; + valaddr_reg:x4; val_offset:230*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x4, 230*FLEN/8, x6, x1, x2) + +inst_140: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2eb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x704c; op2val:0xfaeb; + valaddr_reg:x4; val_offset:232*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x4, 232*FLEN/8, x6, x1, x2) + +inst_141: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2eb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x704c; op2val:0xfaeb; + valaddr_reg:x4; val_offset:234*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x4, 234*FLEN/8, x6, x1, x2) + +inst_142: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2eb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x704c; op2val:0xfaeb; + valaddr_reg:x4; val_offset:236*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x4, 236*FLEN/8, x6, x1, x2) + +inst_143: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x135 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7935; op2val:0x7bff; + valaddr_reg:x4; val_offset:238*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x4, 238*FLEN/8, x6, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(28748,32,FLEN) +NAN_BOXED(28748,16,FLEN) +NAN_BOXED(28748,32,FLEN) +NAN_BOXED(64235,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64235,16,FLEN) +NAN_BOXED(28748,32,FLEN) +NAN_BOXED(64235,16,FLEN) +NAN_BOXED(28748,32,FLEN) +NAN_BOXED(28748,16,FLEN) +NAN_BOXED(31259,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(31259,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(31259,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(31259,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(31259,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(30700,32,FLEN) +NAN_BOXED(63496,16,FLEN) +test_dataset_1: +NAN_BOXED(30700,32,FLEN) +NAN_BOXED(63496,16,FLEN) +NAN_BOXED(30700,32,FLEN) +NAN_BOXED(63496,16,FLEN) +NAN_BOXED(30700,32,FLEN) +NAN_BOXED(63496,16,FLEN) +NAN_BOXED(30700,32,FLEN) +NAN_BOXED(63496,16,FLEN) +NAN_BOXED(31029,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(31029,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(31029,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(31029,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31029,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(28161,32,FLEN) +NAN_BOXED(64318,16,FLEN) +NAN_BOXED(28161,32,FLEN) +NAN_BOXED(64318,16,FLEN) +NAN_BOXED(28161,32,FLEN) +NAN_BOXED(64318,16,FLEN) +NAN_BOXED(28161,32,FLEN) +NAN_BOXED(64318,16,FLEN) +test_dataset_2: +NAN_BOXED(28161,16,FLEN) +NAN_BOXED(64318,16,FLEN) +NAN_BOXED(31406,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31406,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31406,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31406,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31406,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31256,16,FLEN) +NAN_BOXED(62362,16,FLEN) +NAN_BOXED(31256,16,FLEN) +NAN_BOXED(62362,16,FLEN) +NAN_BOXED(31256,16,FLEN) +NAN_BOXED(62362,16,FLEN) +NAN_BOXED(31256,16,FLEN) +NAN_BOXED(62362,16,FLEN) +NAN_BOXED(31256,16,FLEN) +NAN_BOXED(62362,16,FLEN) +NAN_BOXED(30495,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30495,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30495,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30495,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30495,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29521,16,FLEN) +NAN_BOXED(64042,16,FLEN) +NAN_BOXED(29521,16,FLEN) +NAN_BOXED(64042,16,FLEN) +NAN_BOXED(29521,16,FLEN) +NAN_BOXED(64042,16,FLEN) +NAN_BOXED(29521,16,FLEN) +NAN_BOXED(64042,16,FLEN) +NAN_BOXED(29521,16,FLEN) +NAN_BOXED(64042,16,FLEN) +NAN_BOXED(31541,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31541,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31541,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31541,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31541,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(26243,16,FLEN) +NAN_BOXED(64458,16,FLEN) +NAN_BOXED(26243,16,FLEN) +NAN_BOXED(64458,16,FLEN) +NAN_BOXED(26243,16,FLEN) +NAN_BOXED(64458,16,FLEN) +NAN_BOXED(26243,16,FLEN) +NAN_BOXED(64458,16,FLEN) +NAN_BOXED(26243,16,FLEN) +NAN_BOXED(64458,16,FLEN) +NAN_BOXED(31618,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31618,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31618,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31618,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31618,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29421,16,FLEN) +NAN_BOXED(64067,16,FLEN) +NAN_BOXED(29421,16,FLEN) +NAN_BOXED(64067,16,FLEN) +NAN_BOXED(29421,16,FLEN) +NAN_BOXED(64067,16,FLEN) +NAN_BOXED(29421,16,FLEN) +NAN_BOXED(64067,16,FLEN) +NAN_BOXED(29421,16,FLEN) +NAN_BOXED(64067,16,FLEN) +NAN_BOXED(26479,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(26479,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(26479,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(26479,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(26479,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30464,16,FLEN) +NAN_BOXED(29952,16,FLEN) +NAN_BOXED(30464,16,FLEN) +NAN_BOXED(29952,16,FLEN) +NAN_BOXED(30464,16,FLEN) +NAN_BOXED(29952,16,FLEN) +NAN_BOXED(30464,16,FLEN) +NAN_BOXED(29952,16,FLEN) +NAN_BOXED(30464,16,FLEN) +NAN_BOXED(29952,16,FLEN) +NAN_BOXED(29556,16,FLEN) +NAN_BOXED(30138,16,FLEN) +NAN_BOXED(29556,16,FLEN) +NAN_BOXED(30138,16,FLEN) +NAN_BOXED(29556,16,FLEN) +NAN_BOXED(30138,16,FLEN) +NAN_BOXED(29556,16,FLEN) +NAN_BOXED(30138,16,FLEN) +NAN_BOXED(29556,16,FLEN) +NAN_BOXED(30138,16,FLEN) +NAN_BOXED(29439,16,FLEN) +NAN_BOXED(59388,16,FLEN) +NAN_BOXED(29439,16,FLEN) +NAN_BOXED(59388,16,FLEN) +NAN_BOXED(29439,16,FLEN) +NAN_BOXED(59388,16,FLEN) +NAN_BOXED(29439,16,FLEN) +NAN_BOXED(59388,16,FLEN) +NAN_BOXED(29439,16,FLEN) +NAN_BOXED(59388,16,FLEN) +NAN_BOXED(29858,16,FLEN) +NAN_BOXED(30800,16,FLEN) +NAN_BOXED(29858,16,FLEN) +NAN_BOXED(30800,16,FLEN) +NAN_BOXED(29858,16,FLEN) +NAN_BOXED(30800,16,FLEN) +NAN_BOXED(29858,16,FLEN) +NAN_BOXED(30800,16,FLEN) +NAN_BOXED(29858,16,FLEN) +NAN_BOXED(30800,16,FLEN) +NAN_BOXED(31410,16,FLEN) +NAN_BOXED(30054,16,FLEN) +NAN_BOXED(31410,16,FLEN) +NAN_BOXED(30054,16,FLEN) +NAN_BOXED(31410,16,FLEN) +NAN_BOXED(30054,16,FLEN) +NAN_BOXED(31410,16,FLEN) +NAN_BOXED(30054,16,FLEN) +NAN_BOXED(31410,16,FLEN) +NAN_BOXED(30054,16,FLEN) +NAN_BOXED(31010,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31010,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31010,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31010,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31010,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31727,16,FLEN) +NAN_BOXED(57249,16,FLEN) +NAN_BOXED(31727,16,FLEN) +NAN_BOXED(57249,16,FLEN) +NAN_BOXED(31727,16,FLEN) +NAN_BOXED(57249,16,FLEN) +NAN_BOXED(31727,16,FLEN) +NAN_BOXED(57249,16,FLEN) +NAN_BOXED(31727,16,FLEN) +NAN_BOXED(57249,16,FLEN) +NAN_BOXED(28603,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(28603,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(28603,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(28603,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(28603,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31172,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31172,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31172,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31172,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31172,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31612,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31612,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31612,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31612,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31612,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31395,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31395,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31395,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31395,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31395,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(29914,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29914,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29914,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29914,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(29914,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(31502,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31502,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31502,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31502,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31502,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(30730,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30730,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30730,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30730,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(30730,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(28748,16,FLEN) +NAN_BOXED(64235,16,FLEN) +NAN_BOXED(28748,16,FLEN) +NAN_BOXED(64235,16,FLEN) +NAN_BOXED(28748,16,FLEN) +NAN_BOXED(64235,16,FLEN) +NAN_BOXED(31029,16,FLEN) +NAN_BOXED(31743,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x4_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x4_1: + .fill 26*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x14_0: + .fill 36*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_0: + .fill 226*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fsub_b5-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fsub_b5-01.S new file mode 100644 index 000000000..4aa518ef7 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fsub_b5-01.S @@ -0,0 +1,2120 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 06:02:02 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fsub.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fsub.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fsub_b5 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fsub_b5) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x4,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rs2 == rd, rs1==x25, rs2==x25, rd==x25,fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x25; op2:x25; dest:x25; op1val:0x704c; op2val:0x704c; + valaddr_reg:x4; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x25, x25, x25, dyn, 0, 0, x4, 0*FLEN/8, x5, x1, x2) + +inst_1: +// rs2 == rd != rs1, rs1==x11, rs2==x28, rd==x28,fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x11; op2:x28; dest:x28; op1val:0x704c; op2val:0x704c; + valaddr_reg:x4; val_offset:2*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x28, x11, x28, dyn, 32, 0, x4, 2*FLEN/8, x5, x1, x2) + +inst_2: +// rs1 == rd != rs2, rs1==x0, rs2==x21, rd==x0,fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x0; op2:x21; dest:x0; op1val:0x0; op2val:0x704c; + valaddr_reg:x4; val_offset:4*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x0, x0, x21, dyn, 64, 0, x4, 4*FLEN/8, x5, x1, x2) + +inst_3: +// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==x13, rs2==x15, rd==x20,fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x13; op2:x15; dest:x20; op1val:0x704c; op2val:0x704c; + valaddr_reg:x4; val_offset:6*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x20, x13, x15, dyn, 96, 0, x4, 6*FLEN/8, x5, x1, x2) + +inst_4: +// rs1 == rs2 != rd, rs1==x3, rs2==x3, rd==x13,fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x3; op2:x3; dest:x13; op1val:0x704c; op2val:0x704c; + valaddr_reg:x4; val_offset:8*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x13, x3, x3, dyn, 128, 0, x4, 8*FLEN/8, x5, x1, x2) + +inst_5: +// rs1==x23, rs2==x10, rd==x19,fs1 == 0 and fe1 == 0x1e and fm1 == 0x21b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x21b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x23; op2:x10; dest:x19; op1val:0x7a1b; op2val:0x7a1b; + valaddr_reg:x4; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x19, x23, x10, dyn, 0, 0, x4, 10*FLEN/8, x5, x1, x2) + +inst_6: +// rs1==x19, rs2==x11, rd==x23,fs1 == 0 and fe1 == 0x1e and fm1 == 0x21b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x21b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x19; op2:x11; dest:x23; op1val:0x7a1b; op2val:0x7a1b; + valaddr_reg:x4; val_offset:12*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x23, x19, x11, dyn, 32, 0, x4, 12*FLEN/8, x5, x1, x2) + +inst_7: +// rs1==x12, rs2==x14, rd==x15,fs1 == 0 and fe1 == 0x1e and fm1 == 0x21b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x21b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x12; op2:x14; dest:x15; op1val:0x7a1b; op2val:0x7a1b; + valaddr_reg:x4; val_offset:14*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x15, x12, x14, dyn, 64, 0, x4, 14*FLEN/8, x5, x1, x2) + +inst_8: +// rs1==x10, rs2==x23, rd==x6,fs1 == 0 and fe1 == 0x1e and fm1 == 0x21b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x21b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x10; op2:x23; dest:x6; op1val:0x7a1b; op2val:0x7a1b; + valaddr_reg:x4; val_offset:16*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x6, x10, x23, dyn, 96, 0, x4, 16*FLEN/8, x5, x1, x2) + +inst_9: +// rs1==x20, rs2==x13, rd==x27,fs1 == 0 and fe1 == 0x1e and fm1 == 0x21b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x21b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x20; op2:x13; dest:x27; op1val:0x7a1b; op2val:0x7a1b; + valaddr_reg:x4; val_offset:18*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x27, x20, x13, dyn, 128, 0, x4, 18*FLEN/8, x5, x1, x2) + +inst_10: +// rs1==x14, rs2==x7, rd==x9,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ec and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3ec and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x14; op2:x7; dest:x9; op1val:0x77ec; op2val:0x77ec; + valaddr_reg:x4; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x9, x14, x7, dyn, 0, 0, x4, 20*FLEN/8, x5, x1, x2) + +inst_11: +// rs1==x17, rs2==x16, rd==x18,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ec and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3ec and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x17; op2:x16; dest:x18; op1val:0x77ec; op2val:0x77ec; + valaddr_reg:x4; val_offset:22*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x18, x17, x16, dyn, 32, 0, x4, 22*FLEN/8, x5, x1, x2) + +inst_12: +// rs1==x29, rs2==x8, rd==x14,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ec and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3ec and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x29; op2:x8; dest:x14; op1val:0x77ec; op2val:0x77ec; + valaddr_reg:x4; val_offset:24*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x14, x29, x8, dyn, 64, 0, x4, 24*FLEN/8, x5, x1, x2) + +inst_13: +// rs1==x24, rs2==x26, rd==x12,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ec and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3ec and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x24; op2:x26; dest:x12; op1val:0x77ec; op2val:0x77ec; + valaddr_reg:x4; val_offset:26*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x12, x24, x26, dyn, 96, 0, x4, 26*FLEN/8, x5, x1, x2) +RVTEST_VALBASEUPD(x11,test_dataset_1) + +inst_14: +// rs1==x28, rs2==x20, rd==x7,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ec and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3ec and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x28; op2:x20; dest:x7; op1val:0x77ec; op2val:0x77ec; + valaddr_reg:x11; val_offset:0*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x7, x28, x20, dyn, 128, 0, x11, 0*FLEN/8, x12, x1, x2) + +inst_15: +// rs1==x9, rs2==x29, rd==x4,fs1 == 0 and fe1 == 0x1e and fm1 == 0x135 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x135 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x9; op2:x29; dest:x4; op1val:0x7935; op2val:0x7935; + valaddr_reg:x11; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x4, x9, x29, dyn, 0, 0, x11, 2*FLEN/8, x12, x1, x2) + +inst_16: +// rs1==x31, rs2==x0, rd==x5,fs1 == 0 and fe1 == 0x1e and fm1 == 0x135 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x135 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x31; op2:x0; dest:x5; op1val:0x7935; op2val:0x0; + valaddr_reg:x11; val_offset:4*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x14*/ +TEST_FPRR_OP(fsub.h, x5, x31, x0, dyn, 32, 0, x11, 4*FLEN/8, x12, x1, x14) +RVTEST_SIGBASE(x13,signature_x13_0) + +inst_17: +// rs1==x26, rs2==x30, rd==x10,fs1 == 0 and fe1 == 0x1e and fm1 == 0x135 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x135 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x26; op2:x30; dest:x10; op1val:0x7935; op2val:0x7935; + valaddr_reg:x11; val_offset:6*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x14*/ +TEST_FPRR_OP(fsub.h, x10, x26, x30, dyn, 64, 0, x11, 6*FLEN/8, x12, x13, x14) + +inst_18: +// rs1==x5, rs2==x9, rd==x30,fs1 == 0 and fe1 == 0x1e and fm1 == 0x135 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x135 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x5; op2:x9; dest:x30; op1val:0x7935; op2val:0x7935; + valaddr_reg:x11; val_offset:8*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x14*/ +TEST_FPRR_OP(fsub.h, x30, x5, x9, dyn, 96, 0, x11, 8*FLEN/8, x12, x13, x14) + +inst_19: +// rs1==x4, rs2==x1, rd==x8,fs1 == 0 and fe1 == 0x1e and fm1 == 0x135 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x135 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x4; op2:x1; dest:x8; op1val:0x7935; op2val:0x7935; + valaddr_reg:x11; val_offset:10*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x14*/ +TEST_FPRR_OP(fsub.h, x8, x4, x1, dyn, 128, 0, x11, 10*FLEN/8, x12, x13, x14) + +inst_20: +// rs1==x15, rs2==x24, rd==x3,fs1 == 0 and fe1 == 0x1b and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x15; op2:x24; dest:x3; op1val:0x6e01; op2val:0x6e01; + valaddr_reg:x11; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x14*/ +TEST_FPRR_OP(fsub.h, x3, x15, x24, dyn, 0, 0, x11, 12*FLEN/8, x12, x13, x14) + +inst_21: +// rs1==x8, rs2==x2, rd==x16,fs1 == 0 and fe1 == 0x1b and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x201 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x8; op2:x2; dest:x16; op1val:0x6e01; op2val:0x6e01; + valaddr_reg:x11; val_offset:14*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x14*/ +TEST_FPRR_OP(fsub.h, x16, x8, x2, dyn, 32, 0, x11, 14*FLEN/8, x12, x13, x14) + +inst_22: +// rs1==x2, rs2==x6, rd==x21,fs1 == 0 and fe1 == 0x1b and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x201 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x2; op2:x6; dest:x21; op1val:0x6e01; op2val:0x6e01; + valaddr_reg:x11; val_offset:16*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x14*/ +TEST_FPRR_OP(fsub.h, x21, x2, x6, dyn, 64, 0, x11, 16*FLEN/8, x12, x13, x14) + +inst_23: +// rs1==x6, rs2==x19, rd==x17,fs1 == 0 and fe1 == 0x1b and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x201 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x6; op2:x19; dest:x17; op1val:0x6e01; op2val:0x6e01; + valaddr_reg:x11; val_offset:18*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x14*/ +TEST_FPRR_OP(fsub.h, x17, x6, x19, dyn, 96, 0, x11, 18*FLEN/8, x12, x13, x14) + +inst_24: +// rs1==x7, rs2==x27, rd==x22,fs1 == 0 and fe1 == 0x1b and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x201 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x7; op2:x27; dest:x22; op1val:0x6e01; op2val:0x6e01; + valaddr_reg:x11; val_offset:20*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x14*/ +TEST_FPRR_OP(fsub.h, x22, x7, x27, dyn, 128, 0, x11, 20*FLEN/8, x12, x13, x14) +RVTEST_VALBASEUPD(x3,test_dataset_2) + +inst_25: +// rs1==x1, rs2==x17, rd==x31,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ae and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x1; op2:x17; dest:x31; op1val:0x7aae; op2val:0x7aae; + valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x14*/ +TEST_FPRR_OP(fsub.h, x31, x1, x17, dyn, 0, 0, x3, 0*FLEN/8, x6, x13, x14) + +inst_26: +// rs1==x21, rs2==x4, rd==x26,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ae and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x21; op2:x4; dest:x26; op1val:0x7aae; op2val:0x7aae; + valaddr_reg:x3; val_offset:2*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x14*/ +TEST_FPRR_OP(fsub.h, x26, x21, x4, dyn, 32, 0, x3, 2*FLEN/8, x6, x13, x14) + +inst_27: +// rs1==x16, rs2==x22, rd==x29,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ae and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x16; op2:x22; dest:x29; op1val:0x7aae; op2val:0x7aae; + valaddr_reg:x3; val_offset:4*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x14*/ +TEST_FPRR_OP(fsub.h, x29, x16, x22, dyn, 64, 0, x3, 4*FLEN/8, x6, x13, x14) + +inst_28: +// rs1==x30, rs2==x18, rd==x2,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ae and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x18; dest:x2; op1val:0x7aae; op2val:0x7aae; + valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x14*/ +TEST_FPRR_OP(fsub.h, x2, x30, x18, dyn, 96, 0, x3, 6*FLEN/8, x6, x13, x14) + +inst_29: +// rs1==x22, rs2==x5, rd==x24,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ae and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x22; op2:x5; dest:x24; op1val:0x7aae; op2val:0x7aae; + valaddr_reg:x3; val_offset:8*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x14*/ +TEST_FPRR_OP(fsub.h, x24, x22, x5, dyn, 128, 0, x3, 8*FLEN/8, x6, x13, x14) + +inst_30: +// rs1==x27, rs2==x31, rd==x11,fs1 == 0 and fe1 == 0x1e and fm1 == 0x218 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x218 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x27; op2:x31; dest:x11; op1val:0x7a18; op2val:0x7a18; + valaddr_reg:x3; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x14*/ +TEST_FPRR_OP(fsub.h, x11, x27, x31, dyn, 0, 0, x3, 10*FLEN/8, x6, x13, x14) + +inst_31: +// rs1==x18, rs2==x12, rd==x1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x218 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x218 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x18; op2:x12; dest:x1; op1val:0x7a18; op2val:0x7a18; + valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x14*/ +TEST_FPRR_OP(fsub.h, x1, x18, x12, dyn, 32, 0, x3, 12*FLEN/8, x6, x13, x14) + +inst_32: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x218 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x218 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a18; op2val:0x7a18; + valaddr_reg:x3; val_offset:14*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 14*FLEN/8, x6, x13, x1) + +inst_33: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x218 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x218 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a18; op2val:0x7a18; + valaddr_reg:x3; val_offset:16*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 16*FLEN/8, x6, x13, x1) + +inst_34: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x218 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x218 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a18; op2val:0x7a18; + valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 18*FLEN/8, x6, x13, x1) + +inst_35: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31f and fs2 == 0 and fe2 == 0x1d and fm2 == 0x31f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x771f; op2val:0x771f; + valaddr_reg:x3; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 20*FLEN/8, x6, x13, x1) + +inst_36: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31f and fs2 == 0 and fe2 == 0x1d and fm2 == 0x31f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x771f; op2val:0x771f; + valaddr_reg:x3; val_offset:22*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 22*FLEN/8, x6, x13, x1) + +inst_37: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31f and fs2 == 0 and fe2 == 0x1d and fm2 == 0x31f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x771f; op2val:0x771f; + valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 24*FLEN/8, x6, x13, x1) + +inst_38: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31f and fs2 == 0 and fe2 == 0x1d and fm2 == 0x31f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x771f; op2val:0x771f; + valaddr_reg:x3; val_offset:26*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 26*FLEN/8, x6, x13, x1) + +inst_39: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31f and fs2 == 0 and fe2 == 0x1d and fm2 == 0x31f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x771f; op2val:0x771f; + valaddr_reg:x3; val_offset:28*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 28*FLEN/8, x6, x13, x1) + +inst_40: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x351 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x351 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7351; op2val:0x7351; + valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 30*FLEN/8, x6, x13, x1) + +inst_41: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x351 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x351 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7351; op2val:0x7351; + valaddr_reg:x3; val_offset:32*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 32*FLEN/8, x6, x13, x1) + +inst_42: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x351 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x351 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7351; op2val:0x7351; + valaddr_reg:x3; val_offset:34*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 34*FLEN/8, x6, x13, x1) + +inst_43: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x351 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x351 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7351; op2val:0x7351; + valaddr_reg:x3; val_offset:36*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 36*FLEN/8, x6, x13, x1) + +inst_44: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x351 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x351 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7351; op2val:0x7351; + valaddr_reg:x3; val_offset:38*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 38*FLEN/8, x6, x13, x1) + +inst_45: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x335 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x335 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b35; op2val:0x7b35; + valaddr_reg:x3; val_offset:40*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 40*FLEN/8, x6, x13, x1) + +inst_46: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x335 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x335 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b35; op2val:0x7b35; + valaddr_reg:x3; val_offset:42*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 42*FLEN/8, x6, x13, x1) + +inst_47: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x335 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x335 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b35; op2val:0x7b35; + valaddr_reg:x3; val_offset:44*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 44*FLEN/8, x6, x13, x1) + +inst_48: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x335 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x335 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b35; op2val:0x7b35; + valaddr_reg:x3; val_offset:46*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 46*FLEN/8, x6, x13, x1) + +inst_49: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x335 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x335 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b35; op2val:0x7b35; + valaddr_reg:x3; val_offset:48*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 48*FLEN/8, x6, x13, x1) + +inst_50: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x283 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x283 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6683; op2val:0x6683; + valaddr_reg:x3; val_offset:50*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 50*FLEN/8, x6, x13, x1) + +inst_51: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x283 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x283 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6683; op2val:0x6683; + valaddr_reg:x3; val_offset:52*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 52*FLEN/8, x6, x13, x1) + +inst_52: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x283 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x283 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6683; op2val:0x6683; + valaddr_reg:x3; val_offset:54*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 54*FLEN/8, x6, x13, x1) + +inst_53: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x283 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x283 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6683; op2val:0x6683; + valaddr_reg:x3; val_offset:56*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 56*FLEN/8, x6, x13, x1) + +inst_54: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x283 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x283 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6683; op2val:0x6683; + valaddr_reg:x3; val_offset:58*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 58*FLEN/8, x6, x13, x1) + +inst_55: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x382 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x382 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b82; op2val:0x7b82; + valaddr_reg:x3; val_offset:60*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 60*FLEN/8, x6, x13, x1) + +inst_56: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x382 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x382 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b82; op2val:0x7b82; + valaddr_reg:x3; val_offset:62*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 62*FLEN/8, x6, x13, x1) + +inst_57: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x382 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x382 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b82; op2val:0x7b82; + valaddr_reg:x3; val_offset:64*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 64*FLEN/8, x6, x13, x1) + +inst_58: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x382 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x382 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b82; op2val:0x7b82; + valaddr_reg:x3; val_offset:66*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 66*FLEN/8, x6, x13, x1) + +inst_59: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x382 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x382 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b82; op2val:0x7b82; + valaddr_reg:x3; val_offset:68*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 68*FLEN/8, x6, x13, x1) + +inst_60: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ed and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2ed and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x72ed; op2val:0x72ed; + valaddr_reg:x3; val_offset:70*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 70*FLEN/8, x6, x13, x1) + +inst_61: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ed and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2ed and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x72ed; op2val:0x72ed; + valaddr_reg:x3; val_offset:72*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 72*FLEN/8, x6, x13, x1) + +inst_62: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ed and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2ed and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x72ed; op2val:0x72ed; + valaddr_reg:x3; val_offset:74*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 74*FLEN/8, x6, x13, x1) + +inst_63: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ed and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2ed and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x72ed; op2val:0x72ed; + valaddr_reg:x3; val_offset:76*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 76*FLEN/8, x6, x13, x1) + +inst_64: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ed and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2ed and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x72ed; op2val:0x72ed; + valaddr_reg:x3; val_offset:78*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 78*FLEN/8, x6, x13, x1) + +inst_65: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x36f and fs2 == 0 and fe2 == 0x19 and fm2 == 0x36f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x676f; op2val:0x676f; + valaddr_reg:x3; val_offset:80*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 80*FLEN/8, x6, x13, x1) + +inst_66: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x36f and fs2 == 0 and fe2 == 0x19 and fm2 == 0x36f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x676f; op2val:0x676f; + valaddr_reg:x3; val_offset:82*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 82*FLEN/8, x6, x13, x1) + +inst_67: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x36f and fs2 == 0 and fe2 == 0x19 and fm2 == 0x36f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x676f; op2val:0x676f; + valaddr_reg:x3; val_offset:84*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 84*FLEN/8, x6, x13, x1) + +inst_68: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x36f and fs2 == 0 and fe2 == 0x19 and fm2 == 0x36f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x676f; op2val:0x676f; + valaddr_reg:x3; val_offset:86*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 86*FLEN/8, x6, x13, x1) + +inst_69: +// fs1 == 0 and fe1 == 0x19 and fm1 == 0x36f and fs2 == 0 and fe2 == 0x19 and fm2 == 0x36f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x676f; op2val:0x676f; + valaddr_reg:x3; val_offset:88*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 88*FLEN/8, x6, x13, x1) + +inst_70: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x300 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7700; op2val:0x7700; + valaddr_reg:x3; val_offset:90*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 90*FLEN/8, x6, x13, x1) + +inst_71: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x300 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x300 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7700; op2val:0x7700; + valaddr_reg:x3; val_offset:92*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 92*FLEN/8, x6, x13, x1) + +inst_72: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x300 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x300 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7700; op2val:0x7700; + valaddr_reg:x3; val_offset:94*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 94*FLEN/8, x6, x13, x1) + +inst_73: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x300 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x300 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7700; op2val:0x7700; + valaddr_reg:x3; val_offset:96*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 96*FLEN/8, x6, x13, x1) + +inst_74: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x300 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x300 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7700; op2val:0x7700; + valaddr_reg:x3; val_offset:98*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 98*FLEN/8, x6, x13, x1) + +inst_75: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x374 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x374 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7374; op2val:0x7374; + valaddr_reg:x3; val_offset:100*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 100*FLEN/8, x6, x13, x1) + +inst_76: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x374 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x374 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7374; op2val:0x7374; + valaddr_reg:x3; val_offset:102*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 102*FLEN/8, x6, x13, x1) + +inst_77: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x374 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x374 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7374; op2val:0x7374; + valaddr_reg:x3; val_offset:104*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 104*FLEN/8, x6, x13, x1) + +inst_78: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x374 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x374 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7374; op2val:0x7374; + valaddr_reg:x3; val_offset:106*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 106*FLEN/8, x6, x13, x1) + +inst_79: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x374 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x374 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7374; op2val:0x7374; + valaddr_reg:x3; val_offset:108*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 108*FLEN/8, x6, x13, x1) + +inst_80: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ff and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x72ff; op2val:0x72ff; + valaddr_reg:x3; val_offset:110*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 110*FLEN/8, x6, x13, x1) + +inst_81: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ff and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x72ff; op2val:0x72ff; + valaddr_reg:x3; val_offset:112*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 112*FLEN/8, x6, x13, x1) + +inst_82: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ff and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x72ff; op2val:0x72ff; + valaddr_reg:x3; val_offset:114*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 114*FLEN/8, x6, x13, x1) + +inst_83: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ff and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x72ff; op2val:0x72ff; + valaddr_reg:x3; val_offset:116*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 116*FLEN/8, x6, x13, x1) + +inst_84: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ff and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x72ff; op2val:0x72ff; + valaddr_reg:x3; val_offset:118*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 118*FLEN/8, x6, x13, x1) + +inst_85: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a2 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0a2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74a2; op2val:0x74a2; + valaddr_reg:x3; val_offset:120*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 120*FLEN/8, x6, x13, x1) + +inst_86: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a2 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0a2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74a2; op2val:0x74a2; + valaddr_reg:x3; val_offset:122*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 122*FLEN/8, x6, x13, x1) + +inst_87: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a2 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0a2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74a2; op2val:0x74a2; + valaddr_reg:x3; val_offset:124*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 124*FLEN/8, x6, x13, x1) + +inst_88: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a2 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0a2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74a2; op2val:0x74a2; + valaddr_reg:x3; val_offset:126*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 126*FLEN/8, x6, x13, x1) + +inst_89: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a2 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0a2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74a2; op2val:0x74a2; + valaddr_reg:x3; val_offset:128*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 128*FLEN/8, x6, x13, x1) + +inst_90: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab2; op2val:0x7ab2; + valaddr_reg:x3; val_offset:130*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 130*FLEN/8, x6, x13, x1) + +inst_91: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab2; op2val:0x7ab2; + valaddr_reg:x3; val_offset:132*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 132*FLEN/8, x6, x13, x1) + +inst_92: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab2; op2val:0x7ab2; + valaddr_reg:x3; val_offset:134*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 134*FLEN/8, x6, x13, x1) + +inst_93: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab2; op2val:0x7ab2; + valaddr_reg:x3; val_offset:136*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 136*FLEN/8, x6, x13, x1) + +inst_94: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab2; op2val:0x7ab2; + valaddr_reg:x3; val_offset:138*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 138*FLEN/8, x6, x13, x1) + +inst_95: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x122 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x122 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7922; op2val:0x7922; + valaddr_reg:x3; val_offset:140*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 140*FLEN/8, x6, x13, x1) + +inst_96: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x122 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x122 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7922; op2val:0x7922; + valaddr_reg:x3; val_offset:142*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 142*FLEN/8, x6, x13, x1) + +inst_97: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x122 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x122 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7922; op2val:0x7922; + valaddr_reg:x3; val_offset:144*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 144*FLEN/8, x6, x13, x1) + +inst_98: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x122 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x122 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7922; op2val:0x7922; + valaddr_reg:x3; val_offset:146*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 146*FLEN/8, x6, x13, x1) + +inst_99: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x122 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x122 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7922; op2val:0x7922; + valaddr_reg:x3; val_offset:148*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 148*FLEN/8, x6, x13, x1) + +inst_100: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ef and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ef and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bef; op2val:0x7bef; + valaddr_reg:x3; val_offset:150*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 150*FLEN/8, x6, x13, x1) + +inst_101: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ef and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ef and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bef; op2val:0x7bef; + valaddr_reg:x3; val_offset:152*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 152*FLEN/8, x6, x13, x1) + +inst_102: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ef and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ef and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bef; op2val:0x7bef; + valaddr_reg:x3; val_offset:154*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 154*FLEN/8, x6, x13, x1) + +inst_103: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ef and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ef and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bef; op2val:0x7bef; + valaddr_reg:x3; val_offset:156*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 156*FLEN/8, x6, x13, x1) + +inst_104: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ef and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ef and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bef; op2val:0x7bef; + valaddr_reg:x3; val_offset:158*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 158*FLEN/8, x6, x13, x1) + +inst_105: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3bb and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3bb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6fbb; op2val:0x6fbb; + valaddr_reg:x3; val_offset:160*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 160*FLEN/8, x6, x13, x1) + +inst_106: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3bb and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3bb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6fbb; op2val:0x6fbb; + valaddr_reg:x3; val_offset:162*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 162*FLEN/8, x6, x13, x1) + +inst_107: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3bb and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3bb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6fbb; op2val:0x6fbb; + valaddr_reg:x3; val_offset:164*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 164*FLEN/8, x6, x13, x1) + +inst_108: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3bb and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3bb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6fbb; op2val:0x6fbb; + valaddr_reg:x3; val_offset:166*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 166*FLEN/8, x6, x13, x1) + +inst_109: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3bb and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3bb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6fbb; op2val:0x6fbb; + valaddr_reg:x3; val_offset:168*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 168*FLEN/8, x6, x13, x1) + +inst_110: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1c4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c4; op2val:0x79c4; + valaddr_reg:x3; val_offset:170*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 170*FLEN/8, x6, x13, x1) + +inst_111: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1c4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c4; op2val:0x79c4; + valaddr_reg:x3; val_offset:172*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 172*FLEN/8, x6, x13, x1) + +inst_112: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1c4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c4; op2val:0x79c4; + valaddr_reg:x3; val_offset:174*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 174*FLEN/8, x6, x13, x1) + +inst_113: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1c4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c4; op2val:0x79c4; + valaddr_reg:x3; val_offset:176*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 176*FLEN/8, x6, x13, x1) + +inst_114: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1c4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c4; op2val:0x79c4; + valaddr_reg:x3; val_offset:178*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 178*FLEN/8, x6, x13, x1) + +inst_115: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x37c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b7c; op2val:0x7b7c; + valaddr_reg:x3; val_offset:180*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 180*FLEN/8, x6, x13, x1) + +inst_116: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x37c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b7c; op2val:0x7b7c; + valaddr_reg:x3; val_offset:182*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 182*FLEN/8, x6, x13, x1) + +inst_117: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x37c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b7c; op2val:0x7b7c; + valaddr_reg:x3; val_offset:184*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 184*FLEN/8, x6, x13, x1) + +inst_118: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x37c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b7c; op2val:0x7b7c; + valaddr_reg:x3; val_offset:186*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 186*FLEN/8, x6, x13, x1) + +inst_119: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x37c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b7c; op2val:0x7b7c; + valaddr_reg:x3; val_offset:188*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 188*FLEN/8, x6, x13, x1) + +inst_120: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2a3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aa3; op2val:0x7aa3; + valaddr_reg:x3; val_offset:190*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 190*FLEN/8, x6, x13, x1) + +inst_121: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2a3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aa3; op2val:0x7aa3; + valaddr_reg:x3; val_offset:192*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 192*FLEN/8, x6, x13, x1) + +inst_122: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2a3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aa3; op2val:0x7aa3; + valaddr_reg:x3; val_offset:194*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 194*FLEN/8, x6, x13, x1) + +inst_123: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2a3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aa3; op2val:0x7aa3; + valaddr_reg:x3; val_offset:196*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 196*FLEN/8, x6, x13, x1) + +inst_124: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2a3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aa3; op2val:0x7aa3; + valaddr_reg:x3; val_offset:198*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 198*FLEN/8, x6, x13, x1) + +inst_125: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0da and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0da and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74da; op2val:0x74da; + valaddr_reg:x3; val_offset:200*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 200*FLEN/8, x6, x13, x1) + +inst_126: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0da and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0da and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74da; op2val:0x74da; + valaddr_reg:x3; val_offset:202*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 202*FLEN/8, x6, x13, x1) + +inst_127: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0da and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0da and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74da; op2val:0x74da; + valaddr_reg:x3; val_offset:204*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 204*FLEN/8, x6, x13, x1) + +inst_128: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0da and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0da and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74da; op2val:0x74da; + valaddr_reg:x3; val_offset:206*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 206*FLEN/8, x6, x13, x1) + +inst_129: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0da and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0da and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74da; op2val:0x74da; + valaddr_reg:x3; val_offset:208*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 208*FLEN/8, x6, x13, x1) + +inst_130: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x30e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b0e; op2val:0x7b0e; + valaddr_reg:x3; val_offset:210*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 210*FLEN/8, x6, x13, x1) + +inst_131: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x30e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b0e; op2val:0x7b0e; + valaddr_reg:x3; val_offset:212*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 212*FLEN/8, x6, x13, x1) + +inst_132: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x30e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b0e; op2val:0x7b0e; + valaddr_reg:x3; val_offset:214*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 214*FLEN/8, x6, x13, x1) + +inst_133: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x30e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b0e; op2val:0x7b0e; + valaddr_reg:x3; val_offset:216*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 216*FLEN/8, x6, x13, x1) + +inst_134: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x30e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b0e; op2val:0x7b0e; + valaddr_reg:x3; val_offset:218*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 218*FLEN/8, x6, x13, x1) + +inst_135: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x00a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x780a; op2val:0x780a; + valaddr_reg:x3; val_offset:220*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 220*FLEN/8, x6, x13, x1) + +inst_136: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x00a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x780a; op2val:0x780a; + valaddr_reg:x3; val_offset:222*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 222*FLEN/8, x6, x13, x1) + +inst_137: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x00a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x780a; op2val:0x780a; + valaddr_reg:x3; val_offset:224*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 224*FLEN/8, x6, x13, x1) + +inst_138: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x00a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x780a; op2val:0x780a; + valaddr_reg:x3; val_offset:226*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 226*FLEN/8, x6, x13, x1) + +inst_139: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x00a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x780a; op2val:0x780a; + valaddr_reg:x3; val_offset:228*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 228*FLEN/8, x6, x13, x1) + +inst_140: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x06b and fs2 == 0 and fe2 == 0x1a and fm2 == 0x06b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x686b; op2val:0x686b; + valaddr_reg:x3; val_offset:230*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 230*FLEN/8, x6, x13, x1) + +inst_141: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x06b and fs2 == 0 and fe2 == 0x1a and fm2 == 0x06b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x686b; op2val:0x686b; + valaddr_reg:x3; val_offset:232*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 232*FLEN/8, x6, x13, x1) + +inst_142: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x06b and fs2 == 0 and fe2 == 0x1a and fm2 == 0x06b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x686b; op2val:0x686b; + valaddr_reg:x3; val_offset:234*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 234*FLEN/8, x6, x13, x1) + +inst_143: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x06b and fs2 == 0 and fe2 == 0x1a and fm2 == 0x06b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x686b; op2val:0x686b; + valaddr_reg:x3; val_offset:236*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 236*FLEN/8, x6, x13, x1) + +inst_144: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x06b and fs2 == 0 and fe2 == 0x1a and fm2 == 0x06b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x686b; op2val:0x686b; + valaddr_reg:x3; val_offset:238*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 238*FLEN/8, x6, x13, x1) +RVTEST_SIGBASE(x13,signature_x13_1) + +inst_145: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x260 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x260 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a60; op2val:0x7a60; + valaddr_reg:x3; val_offset:240*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 240*FLEN/8, x6, x13, x1) + +inst_146: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x260 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x260 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a60; op2val:0x7a60; + valaddr_reg:x3; val_offset:242*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 242*FLEN/8, x6, x13, x1) + +inst_147: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x260 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x260 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a60; op2val:0x7a60; + valaddr_reg:x3; val_offset:244*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 244*FLEN/8, x6, x13, x1) + +inst_148: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x260 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x260 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a60; op2val:0x7a60; + valaddr_reg:x3; val_offset:246*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 246*FLEN/8, x6, x13, x1) + +inst_149: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x260 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x260 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a60; op2val:0x7a60; + valaddr_reg:x3; val_offset:248*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 248*FLEN/8, x6, x13, x1) + +inst_150: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x188 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x188 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7188; op2val:0x7188; + valaddr_reg:x3; val_offset:250*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 250*FLEN/8, x6, x13, x1) + +inst_151: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x188 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x188 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7188; op2val:0x7188; + valaddr_reg:x3; val_offset:252*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 252*FLEN/8, x6, x13, x1) + +inst_152: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x188 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x188 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7188; op2val:0x7188; + valaddr_reg:x3; val_offset:254*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 254*FLEN/8, x6, x13, x1) + +inst_153: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x188 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x188 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7188; op2val:0x7188; + valaddr_reg:x3; val_offset:256*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 256*FLEN/8, x6, x13, x1) + +inst_154: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x188 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x188 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7188; op2val:0x7188; + valaddr_reg:x3; val_offset:258*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 258*FLEN/8, x6, x13, x1) + +inst_155: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x19f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x799f; op2val:0x799f; + valaddr_reg:x3; val_offset:260*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 260*FLEN/8, x6, x13, x1) + +inst_156: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x19f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x799f; op2val:0x799f; + valaddr_reg:x3; val_offset:262*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 262*FLEN/8, x6, x13, x1) + +inst_157: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x19f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x799f; op2val:0x799f; + valaddr_reg:x3; val_offset:264*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 264*FLEN/8, x6, x13, x1) + +inst_158: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x19f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x799f; op2val:0x799f; + valaddr_reg:x3; val_offset:266*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 266*FLEN/8, x6, x13, x1) + +inst_159: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x19f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x799f; op2val:0x799f; + valaddr_reg:x3; val_offset:268*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 268*FLEN/8, x6, x13, x1) + +inst_160: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1fe and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x75fe; op2val:0x75fe; + valaddr_reg:x3; val_offset:270*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 270*FLEN/8, x6, x13, x1) + +inst_161: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1fe and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1fe and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x75fe; op2val:0x75fe; + valaddr_reg:x3; val_offset:272*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 272*FLEN/8, x6, x13, x1) + +inst_162: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1fe and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1fe and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x75fe; op2val:0x75fe; + valaddr_reg:x3; val_offset:274*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 274*FLEN/8, x6, x13, x1) + +inst_163: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1fe and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1fe and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x75fe; op2val:0x75fe; + valaddr_reg:x3; val_offset:276*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 276*FLEN/8, x6, x13, x1) + +inst_164: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1fe and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1fe and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x75fe; op2val:0x75fe; + valaddr_reg:x3; val_offset:278*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 278*FLEN/8, x6, x13, x1) + +inst_165: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x010 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x010 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7810; op2val:0x7810; + valaddr_reg:x3; val_offset:280*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 280*FLEN/8, x6, x13, x1) + +inst_166: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x010 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x010 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7810; op2val:0x7810; + valaddr_reg:x3; val_offset:282*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 282*FLEN/8, x6, x13, x1) + +inst_167: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x010 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x010 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7810; op2val:0x7810; + valaddr_reg:x3; val_offset:284*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 284*FLEN/8, x6, x13, x1) + +inst_168: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x010 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x010 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7810; op2val:0x7810; + valaddr_reg:x3; val_offset:286*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 286*FLEN/8, x6, x13, x1) + +inst_169: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x010 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x010 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7810; op2val:0x7810; + valaddr_reg:x3; val_offset:288*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 288*FLEN/8, x6, x13, x1) + +inst_170: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x02a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x782a; op2val:0x782a; + valaddr_reg:x3; val_offset:290*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 290*FLEN/8, x6, x13, x1) + +inst_171: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x02a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x782a; op2val:0x782a; + valaddr_reg:x3; val_offset:292*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 292*FLEN/8, x6, x13, x1) + +inst_172: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x02a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x782a; op2val:0x782a; + valaddr_reg:x3; val_offset:294*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 294*FLEN/8, x6, x13, x1) + +inst_173: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x02a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x782a; op2val:0x782a; + valaddr_reg:x3; val_offset:296*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 296*FLEN/8, x6, x13, x1) + +inst_174: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x02a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x782a; op2val:0x782a; + valaddr_reg:x3; val_offset:298*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 298*FLEN/8, x6, x13, x1) + +inst_175: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d4 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3d4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x77d4; op2val:0x77d4; + valaddr_reg:x3; val_offset:300*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 300*FLEN/8, x6, x13, x1) + +inst_176: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d4 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3d4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x77d4; op2val:0x77d4; + valaddr_reg:x3; val_offset:302*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 302*FLEN/8, x6, x13, x1) + +inst_177: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d4 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3d4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x77d4; op2val:0x77d4; + valaddr_reg:x3; val_offset:304*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 304*FLEN/8, x6, x13, x1) + +inst_178: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d4 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3d4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x77d4; op2val:0x77d4; + valaddr_reg:x3; val_offset:306*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 306*FLEN/8, x6, x13, x1) + +inst_179: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d4 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3d4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x77d4; op2val:0x77d4; + valaddr_reg:x3; val_offset:308*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 308*FLEN/8, x6, x13, x1) + +inst_180: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x190 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x190 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6990; op2val:0x6990; + valaddr_reg:x3; val_offset:310*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 310*FLEN/8, x6, x13, x1) + +inst_181: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x190 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x190 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6990; op2val:0x6990; + valaddr_reg:x3; val_offset:312*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 312*FLEN/8, x6, x13, x1) + +inst_182: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x190 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x190 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6990; op2val:0x6990; + valaddr_reg:x3; val_offset:314*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 314*FLEN/8, x6, x13, x1) + +inst_183: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x190 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x190 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6990; op2val:0x6990; + valaddr_reg:x3; val_offset:316*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 316*FLEN/8, x6, x13, x1) + +inst_184: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x190 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x190 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6990; op2val:0x6990; + valaddr_reg:x3; val_offset:318*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 318*FLEN/8, x6, x13, x1) + +inst_185: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3dc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3dc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bdc; op2val:0x7bdc; + valaddr_reg:x3; val_offset:320*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 320*FLEN/8, x6, x13, x1) + +inst_186: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3dc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3dc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bdc; op2val:0x7bdc; + valaddr_reg:x3; val_offset:322*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 322*FLEN/8, x6, x13, x1) + +inst_187: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3dc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3dc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bdc; op2val:0x7bdc; + valaddr_reg:x3; val_offset:324*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 324*FLEN/8, x6, x13, x1) + +inst_188: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3dc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3dc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bdc; op2val:0x7bdc; + valaddr_reg:x3; val_offset:326*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 326*FLEN/8, x6, x13, x1) + +inst_189: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3dc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3dc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bdc; op2val:0x7bdc; + valaddr_reg:x3; val_offset:328*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 328*FLEN/8, x6, x13, x1) + +inst_190: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x24b and fs2 == 0 and fe2 == 0x1d and fm2 == 0x24b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x764b; op2val:0x764b; + valaddr_reg:x3; val_offset:330*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 330*FLEN/8, x6, x13, x1) + +inst_191: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x24b and fs2 == 0 and fe2 == 0x1d and fm2 == 0x24b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x764b; op2val:0x764b; + valaddr_reg:x3; val_offset:332*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 332*FLEN/8, x6, x13, x1) + +inst_192: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x24b and fs2 == 0 and fe2 == 0x1d and fm2 == 0x24b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x764b; op2val:0x764b; + valaddr_reg:x3; val_offset:334*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 334*FLEN/8, x6, x13, x1) + +inst_193: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x24b and fs2 == 0 and fe2 == 0x1d and fm2 == 0x24b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x764b; op2val:0x764b; + valaddr_reg:x3; val_offset:336*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 336*FLEN/8, x6, x13, x1) + +inst_194: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x24b and fs2 == 0 and fe2 == 0x1d and fm2 == 0x24b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x764b; op2val:0x764b; + valaddr_reg:x3; val_offset:338*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 338*FLEN/8, x6, x13, x1) + +inst_195: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x004 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7804; op2val:0x7804; + valaddr_reg:x3; val_offset:340*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 340*FLEN/8, x6, x13, x1) + +inst_196: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x004 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7804; op2val:0x7804; + valaddr_reg:x3; val_offset:342*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 342*FLEN/8, x6, x13, x1) + +inst_197: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x004 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7804; op2val:0x7804; + valaddr_reg:x3; val_offset:344*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 344*FLEN/8, x6, x13, x1) + +inst_198: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x004 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7804; op2val:0x7804; + valaddr_reg:x3; val_offset:346*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 346*FLEN/8, x6, x13, x1) + +inst_199: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x004 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7804; op2val:0x7804; + valaddr_reg:x3; val_offset:348*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 348*FLEN/8, x6, x13, x1) + +inst_200: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x229 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x229 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a29; op2val:0x7a29; + valaddr_reg:x3; val_offset:350*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 350*FLEN/8, x6, x13, x1) + +inst_201: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x229 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x229 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a29; op2val:0x7a29; + valaddr_reg:x3; val_offset:352*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 352*FLEN/8, x6, x13, x1) + +inst_202: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x229 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x229 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a29; op2val:0x7a29; + valaddr_reg:x3; val_offset:354*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 354*FLEN/8, x6, x13, x1) + +inst_203: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x229 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x229 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a29; op2val:0x7a29; + valaddr_reg:x3; val_offset:356*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 356*FLEN/8, x6, x13, x1) + +inst_204: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x229 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x229 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a29; op2val:0x7a29; + valaddr_reg:x3; val_offset:358*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 358*FLEN/8, x6, x13, x1) + +inst_205: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2e1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ae1; op2val:0x7ae1; + valaddr_reg:x3; val_offset:360*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 360*FLEN/8, x6, x13, x1) + +inst_206: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2e1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ae1; op2val:0x7ae1; + valaddr_reg:x3; val_offset:362*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 362*FLEN/8, x6, x13, x1) + +inst_207: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2e1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ae1; op2val:0x7ae1; + valaddr_reg:x3; val_offset:364*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 364*FLEN/8, x6, x13, x1) + +inst_208: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2e1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ae1; op2val:0x7ae1; + valaddr_reg:x3; val_offset:366*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 366*FLEN/8, x6, x13, x1) + +inst_209: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2e1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ae1; op2val:0x7ae1; + valaddr_reg:x3; val_offset:368*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 368*FLEN/8, x6, x13, x1) + +inst_210: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x01b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x01b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x781b; op2val:0x781b; + valaddr_reg:x3; val_offset:370*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 370*FLEN/8, x6, x13, x1) + +inst_211: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x01b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x01b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x781b; op2val:0x781b; + valaddr_reg:x3; val_offset:372*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 372*FLEN/8, x6, x13, x1) + +inst_212: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x01b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x01b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x781b; op2val:0x781b; + valaddr_reg:x3; val_offset:374*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 374*FLEN/8, x6, x13, x1) + +inst_213: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x01b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x01b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x781b; op2val:0x781b; + valaddr_reg:x3; val_offset:376*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 376*FLEN/8, x6, x13, x1) + +inst_214: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x01b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x01b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x781b; op2val:0x781b; + valaddr_reg:x3; val_offset:378*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 378*FLEN/8, x6, x13, x1) + +inst_215: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x09e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x789e; op2val:0x789e; + valaddr_reg:x3; val_offset:380*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 380*FLEN/8, x6, x13, x1) + +inst_216: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x09e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x789e; op2val:0x789e; + valaddr_reg:x3; val_offset:382*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 382*FLEN/8, x6, x13, x1) + +inst_217: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x09e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x789e; op2val:0x789e; + valaddr_reg:x3; val_offset:384*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 384*FLEN/8, x6, x13, x1) + +inst_218: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x09e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x789e; op2val:0x789e; + valaddr_reg:x3; val_offset:386*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 386*FLEN/8, x6, x13, x1) + +inst_219: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x09e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x789e; op2val:0x789e; + valaddr_reg:x3; val_offset:388*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 388*FLEN/8, x6, x13, x1) + +inst_220: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x704c; op2val:0x704c; + valaddr_reg:x3; val_offset:390*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 390*FLEN/8, x6, x13, x1) + +inst_221: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x704c; op2val:0x704c; + valaddr_reg:x3; val_offset:392*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 392*FLEN/8, x6, x13, x1) + +inst_222: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x704c; op2val:0x704c; + valaddr_reg:x3; val_offset:394*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 394*FLEN/8, x6, x13, x1) + +inst_223: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x135 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x135 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7935; op2val:0x7935; + valaddr_reg:x3; val_offset:396*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 396*FLEN/8, x6, x13, x1) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(28748,32,FLEN) +NAN_BOXED(28748,32,FLEN) +NAN_BOXED(28748,32,FLEN) +NAN_BOXED(28748,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(28748,32,FLEN) +NAN_BOXED(28748,32,FLEN) +NAN_BOXED(28748,32,FLEN) +NAN_BOXED(28748,32,FLEN) +NAN_BOXED(28748,32,FLEN) +NAN_BOXED(31259,32,FLEN) +NAN_BOXED(31259,32,FLEN) +NAN_BOXED(31259,32,FLEN) +NAN_BOXED(31259,32,FLEN) +NAN_BOXED(31259,32,FLEN) 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+NAN_BOXED(30676,16,FLEN) +NAN_BOXED(30676,16,FLEN) +NAN_BOXED(30676,16,FLEN) +NAN_BOXED(30676,16,FLEN) +NAN_BOXED(27024,16,FLEN) +NAN_BOXED(27024,16,FLEN) +NAN_BOXED(27024,16,FLEN) +NAN_BOXED(27024,16,FLEN) +NAN_BOXED(27024,16,FLEN) +NAN_BOXED(27024,16,FLEN) +NAN_BOXED(27024,16,FLEN) +NAN_BOXED(27024,16,FLEN) +NAN_BOXED(27024,16,FLEN) +NAN_BOXED(27024,16,FLEN) +NAN_BOXED(31708,16,FLEN) +NAN_BOXED(31708,16,FLEN) +NAN_BOXED(31708,16,FLEN) +NAN_BOXED(31708,16,FLEN) +NAN_BOXED(31708,16,FLEN) +NAN_BOXED(31708,16,FLEN) +NAN_BOXED(31708,16,FLEN) +NAN_BOXED(31708,16,FLEN) +NAN_BOXED(31708,16,FLEN) +NAN_BOXED(31708,16,FLEN) +NAN_BOXED(30283,16,FLEN) +NAN_BOXED(30283,16,FLEN) +NAN_BOXED(30283,16,FLEN) +NAN_BOXED(30283,16,FLEN) +NAN_BOXED(30283,16,FLEN) +NAN_BOXED(30283,16,FLEN) +NAN_BOXED(30283,16,FLEN) +NAN_BOXED(30283,16,FLEN) +NAN_BOXED(30283,16,FLEN) +NAN_BOXED(30283,16,FLEN) +NAN_BOXED(30724,16,FLEN) +NAN_BOXED(30724,16,FLEN) +NAN_BOXED(30724,16,FLEN) +NAN_BOXED(30724,16,FLEN) +NAN_BOXED(30724,16,FLEN) +NAN_BOXED(30724,16,FLEN) +NAN_BOXED(30724,16,FLEN) +NAN_BOXED(30724,16,FLEN) +NAN_BOXED(30724,16,FLEN) +NAN_BOXED(30724,16,FLEN) +NAN_BOXED(31273,16,FLEN) +NAN_BOXED(31273,16,FLEN) +NAN_BOXED(31273,16,FLEN) +NAN_BOXED(31273,16,FLEN) +NAN_BOXED(31273,16,FLEN) +NAN_BOXED(31273,16,FLEN) +NAN_BOXED(31273,16,FLEN) +NAN_BOXED(31273,16,FLEN) +NAN_BOXED(31273,16,FLEN) +NAN_BOXED(31273,16,FLEN) +NAN_BOXED(31457,16,FLEN) +NAN_BOXED(31457,16,FLEN) +NAN_BOXED(31457,16,FLEN) +NAN_BOXED(31457,16,FLEN) +NAN_BOXED(31457,16,FLEN) +NAN_BOXED(31457,16,FLEN) +NAN_BOXED(31457,16,FLEN) +NAN_BOXED(31457,16,FLEN) +NAN_BOXED(31457,16,FLEN) +NAN_BOXED(31457,16,FLEN) +NAN_BOXED(30747,16,FLEN) +NAN_BOXED(30747,16,FLEN) +NAN_BOXED(30747,16,FLEN) +NAN_BOXED(30747,16,FLEN) +NAN_BOXED(30747,16,FLEN) +NAN_BOXED(30747,16,FLEN) +NAN_BOXED(30747,16,FLEN) +NAN_BOXED(30747,16,FLEN) +NAN_BOXED(30747,16,FLEN) +NAN_BOXED(30747,16,FLEN) +NAN_BOXED(30878,16,FLEN) +NAN_BOXED(30878,16,FLEN) +NAN_BOXED(30878,16,FLEN) +NAN_BOXED(30878,16,FLEN) +NAN_BOXED(30878,16,FLEN) +NAN_BOXED(30878,16,FLEN) +NAN_BOXED(30878,16,FLEN) +NAN_BOXED(30878,16,FLEN) +NAN_BOXED(30878,16,FLEN) +NAN_BOXED(30878,16,FLEN) +NAN_BOXED(28748,16,FLEN) +NAN_BOXED(28748,16,FLEN) +NAN_BOXED(28748,16,FLEN) +NAN_BOXED(28748,16,FLEN) +NAN_BOXED(28748,16,FLEN) +NAN_BOXED(28748,16,FLEN) +NAN_BOXED(31029,16,FLEN) +NAN_BOXED(31029,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 34*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x13_0: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x13_1: + .fill 158*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fsub_b7-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fsub_b7-01.S new file mode 100644 index 000000000..f7ad33f66 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fsub_b7-01.S @@ -0,0 +1,653 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 06:02:02 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fsub.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fsub.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fsub_b7 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fsub_b7) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x2,signature_x2_1) + +inst_0: +// rs1 == rs2 == rd, rs1==x8, rs2==x8, rd==x8,fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x8; op2:x8; dest:x8; op1val:0x704c; op2val:0x704c; + valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x8, x8, x8, dyn, 96, 0, x3, 0*FLEN/8, x5, x2, x1) + +inst_1: +// rs2 == rd != rs1, rs1==x26, rs2==x9, rd==x9,fs1 == 0 and fe1 == 0x1e and fm1 == 0x21b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x21b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x26; op2:x9; dest:x9; op1val:0x7a1b; op2val:0x7a1b; + valaddr_reg:x3; val_offset:2*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x9, x26, x9, dyn, 96, 0, x3, 2*FLEN/8, x5, x2, x1) + +inst_2: +// rs1 == rd != rs2, rs1==x24, rs2==x13, rd==x24,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ec and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3ec and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x24; op2:x13; dest:x24; op1val:0x77ec; op2val:0x77ec; + valaddr_reg:x3; val_offset:4*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x24, x24, x13, dyn, 96, 0, x3, 4*FLEN/8, x5, x2, x1) + +inst_3: +// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==x10, rs2==x11, rd==x16,fs1 == 0 and fe1 == 0x1e and fm1 == 0x135 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x135 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x10; op2:x11; dest:x16; op1val:0x7935; op2val:0x7935; + valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x16, x10, x11, dyn, 96, 0, x3, 6*FLEN/8, x5, x2, x1) + +inst_4: +// rs1 == rs2 != rd, rs1==x27, rs2==x27, rd==x20,fs1 == 0 and fe1 == 0x1b and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x201 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x27; op2:x27; dest:x20; op1val:0x6e01; op2val:0x6e01; + valaddr_reg:x3; val_offset:8*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x20, x27, x27, dyn, 96, 0, x3, 8*FLEN/8, x5, x2, x1) + +inst_5: +// rs1==x30, rs2==x16, rd==x29,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ae and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x16; dest:x29; op1val:0x7aae; op2val:0x7aae; + valaddr_reg:x3; val_offset:10*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x29, x30, x16, dyn, 96, 0, x3, 10*FLEN/8, x5, x2, x1) + +inst_6: +// rs1==x23, rs2==x29, rd==x10,fs1 == 0 and fe1 == 0x1e and fm1 == 0x218 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x218 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x23; op2:x29; dest:x10; op1val:0x7a18; op2val:0x7a18; + valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x10, x23, x29, dyn, 96, 0, x3, 12*FLEN/8, x5, x2, x1) + +inst_7: +// rs1==x12, rs2==x18, rd==x15,fs1 == 0 and fe1 == 0x1d and fm1 == 0x31f and fs2 == 0 and fe2 == 0x1d and fm2 == 0x31f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x12; op2:x18; dest:x15; op1val:0x771f; op2val:0x771f; + valaddr_reg:x3; val_offset:14*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x15, x12, x18, dyn, 96, 0, x3, 14*FLEN/8, x5, x2, x1) + +inst_8: +// rs1==x21, rs2==x0, rd==x30,fs1 == 0 and fe1 == 0x1c and fm1 == 0x351 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x351 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x21; op2:x0; dest:x30; op1val:0x7351; op2val:0x0; + valaddr_reg:x3; val_offset:16*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x30, x21, x0, dyn, 96, 0, x3, 16*FLEN/8, x5, x2, x1) + +inst_9: +// rs1==x17, rs2==x7, rd==x4,fs1 == 0 and fe1 == 0x1e and fm1 == 0x335 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x335 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x17; op2:x7; dest:x4; op1val:0x7b35; op2val:0x7b35; + valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x4, x17, x7, dyn, 96, 0, x3, 18*FLEN/8, x5, x2, x1) + +inst_10: +// rs1==x6, rs2==x23, rd==x26,fs1 == 0 and fe1 == 0x19 and fm1 == 0x283 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x283 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x6; op2:x23; dest:x26; op1val:0x6683; op2val:0x6683; + valaddr_reg:x3; val_offset:20*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x26, x6, x23, dyn, 96, 0, x3, 20*FLEN/8, x5, x2, x1) + +inst_11: +// rs1==x15, rs2==x4, rd==x12,fs1 == 0 and fe1 == 0x1e and fm1 == 0x382 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x382 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x15; op2:x4; dest:x12; op1val:0x7b82; op2val:0x7b82; + valaddr_reg:x3; val_offset:22*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x12, x15, x4, dyn, 96, 0, x3, 22*FLEN/8, x5, x2, x1) + +inst_12: +// rs1==x28, rs2==x14, rd==x7,fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ed and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2ed and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x28; op2:x14; dest:x7; op1val:0x72ed; op2val:0x72ed; + valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x7, x28, x14, dyn, 96, 0, x3, 24*FLEN/8, x5, x2, x1) +RVTEST_VALBASEUPD(x16,test_dataset_1) + +inst_13: +// rs1==x19, rs2==x10, rd==x22,fs1 == 0 and fe1 == 0x19 and fm1 == 0x36f and fs2 == 0 and fe2 == 0x19 and fm2 == 0x36f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x19; op2:x10; dest:x22; op1val:0x676f; op2val:0x676f; + valaddr_reg:x16; val_offset:0*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x1*/ +TEST_FPRR_OP(fsub.h, x22, x19, x10, dyn, 96, 0, x16, 0*FLEN/8, x20, x2, x1) + +inst_14: +// rs1==x25, rs2==x3, rd==x1,fs1 == 0 and fe1 == 0x1d and fm1 == 0x300 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x300 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x25; op2:x3; dest:x1; op1val:0x7700; op2val:0x7700; + valaddr_reg:x16; val_offset:2*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x10*/ +TEST_FPRR_OP(fsub.h, x1, x25, x3, dyn, 96, 0, x16, 2*FLEN/8, x20, x2, x10) +RVTEST_SIGBASE(x8,signature_x8_0) + +inst_15: +// rs1==x7, rs2==x1, rd==x14,fs1 == 0 and fe1 == 0x1c and fm1 == 0x374 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x374 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x7; op2:x1; dest:x14; op1val:0x7374; op2val:0x7374; + valaddr_reg:x16; val_offset:4*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x10*/ +TEST_FPRR_OP(fsub.h, x14, x7, x1, dyn, 96, 0, x16, 4*FLEN/8, x20, x8, x10) + +inst_16: +// rs1==x2, rs2==x31, rd==x6,fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ff and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x2; op2:x31; dest:x6; op1val:0x72ff; op2val:0x72ff; + valaddr_reg:x16; val_offset:6*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x10*/ +TEST_FPRR_OP(fsub.h, x6, x2, x31, dyn, 96, 0, x16, 6*FLEN/8, x20, x8, x10) + +inst_17: +// rs1==x9, rs2==x2, rd==x11,fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a2 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0a2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x9; op2:x2; dest:x11; op1val:0x74a2; op2val:0x74a2; + valaddr_reg:x16; val_offset:8*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x10*/ +TEST_FPRR_OP(fsub.h, x11, x9, x2, dyn, 96, 0, x16, 8*FLEN/8, x20, x8, x10) + +inst_18: +// rs1==x31, rs2==x6, rd==x2,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x31; op2:x6; dest:x2; op1val:0x7ab2; op2val:0x7ab2; + valaddr_reg:x16; val_offset:10*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x10*/ +TEST_FPRR_OP(fsub.h, x2, x31, x6, dyn, 96, 0, x16, 10*FLEN/8, x20, x8, x10) + +inst_19: +// rs1==x4, rs2==x5, rd==x3,fs1 == 0 and fe1 == 0x1e and fm1 == 0x122 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x122 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x4; op2:x5; dest:x3; op1val:0x7922; op2val:0x7922; + valaddr_reg:x16; val_offset:12*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x10*/ +TEST_FPRR_OP(fsub.h, x3, x4, x5, dyn, 96, 0, x16, 12*FLEN/8, x20, x8, x10) + +inst_20: +// rs1==x14, rs2==x15, rd==x13,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ef and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ef and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x14; op2:x15; dest:x13; op1val:0x7bef; op2val:0x7bef; + valaddr_reg:x16; val_offset:14*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x10*/ +TEST_FPRR_OP(fsub.h, x13, x14, x15, dyn, 96, 0, x16, 14*FLEN/8, x20, x8, x10) + +inst_21: +// rs1==x29, rs2==x12, rd==x27,fs1 == 0 and fe1 == 0x1b and fm1 == 0x3bb and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3bb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x29; op2:x12; dest:x27; op1val:0x6fbb; op2val:0x6fbb; + valaddr_reg:x16; val_offset:16*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x10*/ +TEST_FPRR_OP(fsub.h, x27, x29, x12, dyn, 96, 0, x16, 16*FLEN/8, x20, x8, x10) + +inst_22: +// rs1==x18, rs2==x26, rd==x23,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1c4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x18; op2:x26; dest:x23; op1val:0x79c4; op2val:0x79c4; + valaddr_reg:x16; val_offset:18*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x10*/ +TEST_FPRR_OP(fsub.h, x23, x18, x26, dyn, 96, 0, x16, 18*FLEN/8, x20, x8, x10) + +inst_23: +// rs1==x22, rs2==x30, rd==x17,fs1 == 0 and fe1 == 0x1e and fm1 == 0x37c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x37c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x22; op2:x30; dest:x17; op1val:0x7b7c; op2val:0x7b7c; + valaddr_reg:x16; val_offset:20*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x10*/ +TEST_FPRR_OP(fsub.h, x17, x22, x30, dyn, 96, 0, x16, 20*FLEN/8, x20, x8, x10) +RVTEST_VALBASEUPD(x6,test_dataset_2) + +inst_24: +// rs1==x20, rs2==x22, rd==x19,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2a3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x20; op2:x22; dest:x19; op1val:0x7aa3; op2val:0x7aa3; + valaddr_reg:x6; val_offset:0*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x10*/ +TEST_FPRR_OP(fsub.h, x19, x20, x22, dyn, 96, 0, x6, 0*FLEN/8, x7, x8, x10) + +inst_25: +// rs1==x11, rs2==x24, rd==x28,fs1 == 0 and fe1 == 0x1d and fm1 == 0x0da and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0da and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x11; op2:x24; dest:x28; op1val:0x74da; op2val:0x74da; + valaddr_reg:x6; val_offset:2*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4*/ +TEST_FPRR_OP(fsub.h, x28, x11, x24, dyn, 96, 0, x6, 2*FLEN/8, x7, x8, x4) +RVTEST_SIGBASE(x2,signature_x2_2) + +inst_26: +// rs1==x0, rs2==x17, rd==x31,fs1 == 0 and fe1 == 0x1e and fm1 == 0x30e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x30e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x0; op2:x17; dest:x31; op1val:0x0; op2val:0x7b0e; + valaddr_reg:x6; val_offset:4*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4*/ +TEST_FPRR_OP(fsub.h, x31, x0, x17, dyn, 96, 0, x6, 4*FLEN/8, x7, x2, x4) + +inst_27: +// rs1==x3, rs2==x28, rd==x18,fs1 == 0 and fe1 == 0x1e and fm1 == 0x00a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x00a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x3; op2:x28; dest:x18; op1val:0x780a; op2val:0x780a; + valaddr_reg:x6; val_offset:6*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4*/ +TEST_FPRR_OP(fsub.h, x18, x3, x28, dyn, 96, 0, x6, 6*FLEN/8, x7, x2, x4) + +inst_28: +// rs1==x5, rs2==x21, rd==x0,fs1 == 0 and fe1 == 0x1a and fm1 == 0x06b and fs2 == 0 and fe2 == 0x1a and fm2 == 0x06b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x5; op2:x21; dest:x0; op1val:0x686b; op2val:0x686b; + valaddr_reg:x6; val_offset:8*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4*/ +TEST_FPRR_OP(fsub.h, x0, x5, x21, dyn, 96, 0, x6, 8*FLEN/8, x7, x2, x4) + +inst_29: +// rs1==x16, rs2==x25, rd==x5,fs1 == 0 and fe1 == 0x1e and fm1 == 0x260 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x260 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x16; op2:x25; dest:x5; op1val:0x7a60; op2val:0x7a60; + valaddr_reg:x6; val_offset:10*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4*/ +TEST_FPRR_OP(fsub.h, x5, x16, x25, dyn, 96, 0, x6, 10*FLEN/8, x7, x2, x4) + +inst_30: +// rs1==x13, rs2==x20, rd==x25,fs1 == 0 and fe1 == 0x1c and fm1 == 0x188 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x188 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x13; op2:x20; dest:x25; op1val:0x7188; op2val:0x7188; + valaddr_reg:x6; val_offset:12*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4*/ +TEST_FPRR_OP(fsub.h, x25, x13, x20, dyn, 96, 0, x6, 12*FLEN/8, x7, x2, x4) + +inst_31: +// rs1==x1, rs2==x19, rd==x21,fs1 == 0 and fe1 == 0x1e and fm1 == 0x19f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x19f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x1; op2:x19; dest:x21; op1val:0x799f; op2val:0x799f; + valaddr_reg:x6; val_offset:14*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4*/ +TEST_FPRR_OP(fsub.h, x21, x1, x19, dyn, 96, 0, x6, 14*FLEN/8, x7, x2, x4) + +inst_32: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1fe and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1fe and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x75fe; op2val:0x75fe; + valaddr_reg:x6; val_offset:16*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x6, 16*FLEN/8, x7, x2, x4) + +inst_33: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x010 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x010 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7810; op2val:0x7810; + valaddr_reg:x6; val_offset:18*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x6, 18*FLEN/8, x7, x2, x4) + +inst_34: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x02a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x782a; op2val:0x782a; + valaddr_reg:x6; val_offset:20*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x6, 20*FLEN/8, x7, x2, x4) + +inst_35: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d4 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3d4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x77d4; op2val:0x77d4; + valaddr_reg:x6; val_offset:22*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x6, 22*FLEN/8, x7, x2, x4) + +inst_36: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x190 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x190 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6990; op2val:0x6990; + valaddr_reg:x6; val_offset:24*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x6, 24*FLEN/8, x7, x2, x4) + +inst_37: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3dc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3dc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bdc; op2val:0x7bdc; + valaddr_reg:x6; val_offset:26*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x6, 26*FLEN/8, x7, x2, x4) + +inst_38: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x24b and fs2 == 0 and fe2 == 0x1d and fm2 == 0x24b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x764b; op2val:0x764b; + valaddr_reg:x6; val_offset:28*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x6, 28*FLEN/8, x7, x2, x4) + +inst_39: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x004 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7804; op2val:0x7804; + valaddr_reg:x6; val_offset:30*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x6, 30*FLEN/8, x7, x2, x4) + +inst_40: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x229 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x229 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a29; op2val:0x7a29; + valaddr_reg:x6; val_offset:32*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x6, 32*FLEN/8, x7, x2, x4) + +inst_41: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2e1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ae1; op2val:0x7ae1; + valaddr_reg:x6; val_offset:34*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x6, 34*FLEN/8, x7, x2, x4) + +inst_42: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x01b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x019 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x781b; op2val:0x7819; + valaddr_reg:x6; val_offset:36*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x6, 36*FLEN/8, x7, x2, x4) + +inst_43: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x09c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x789e; op2val:0x789c; + valaddr_reg:x6; val_offset:38*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x6, 38*FLEN/8, x7, x2, x4) + +inst_44: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x04e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x04a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x744e; op2val:0x744a; + valaddr_reg:x6; val_offset:40*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x6, 40*FLEN/8, x7, x2, x4) + +inst_45: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3a5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba7; op2val:0x7ba5; + valaddr_reg:x6; val_offset:42*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x6, 42*FLEN/8, x7, x2, x4) + +inst_46: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x244 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x242 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a44; op2val:0x7a42; + valaddr_reg:x6; val_offset:44*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x6, 44*FLEN/8, x7, x2, x4) + +inst_47: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x316 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x314 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b16; op2val:0x7b14; + valaddr_reg:x6; val_offset:46*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x6, 46*FLEN/8, x7, x2, x4) + +inst_48: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x278 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x276 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a78; op2val:0x7a76; + valaddr_reg:x6; val_offset:48*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x6, 48*FLEN/8, x7, x2, x4) + +inst_49: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x07d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x07d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x787d; op2val:0x787d; + valaddr_reg:x6; val_offset:50*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x6, 50*FLEN/8, x7, x2, x4) + +inst_50: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x32e and fs2 == 0 and fe2 == 0x1a and fm2 == 0x32e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6b2e; op2val:0x6b2e; + valaddr_reg:x6; val_offset:52*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x6, 52*FLEN/8, x7, x2, x4) + +inst_51: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x08e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x08e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x788e; op2val:0x788e; + valaddr_reg:x6; val_offset:54*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x6, 54*FLEN/8, x7, x2, x4) + +inst_52: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x009 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x009 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7809; op2val:0x7809; + valaddr_reg:x6; val_offset:56*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x6, 56*FLEN/8, x7, x2, x4) + +inst_53: +// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1b4 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1b4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x75b4; op2val:0x75b4; + valaddr_reg:x6; val_offset:58*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x6, 58*FLEN/8, x7, x2, x4) + +inst_54: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x04e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x784e; op2val:0x784e; + valaddr_reg:x6; val_offset:60*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x6, 60*FLEN/8, x7, x2, x4) + +inst_55: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0e5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x78e5; op2val:0x78e5; + valaddr_reg:x6; val_offset:62*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x6, 62*FLEN/8, x7, x2, x4) + +inst_56: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x704c; op2val:0x704c; + valaddr_reg:x6; val_offset:64*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x6, 64*FLEN/8, x7, x2, x4) + +inst_57: +// fs1 == 0 and fe1 == 0x1b and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x201 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e01; op2val:0x6e01; + valaddr_reg:x6; val_offset:66*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x6, 66*FLEN/8, x7, x2, x4) + +inst_58: +// fs1 == 0 and fe1 == 0x1c and fm1 == 0x351 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x351 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7351; op2val:0x7351; + valaddr_reg:x6; val_offset:68*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x6, 68*FLEN/8, x7, x2, x4) + +inst_59: +// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x30e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b0e; op2val:0x7b0e; + valaddr_reg:x6; val_offset:70*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x6, 70*FLEN/8, x7, x2, x4) + +inst_60: +// fs1 == 0 and fe1 == 0x1a and fm1 == 0x06b and fs2 == 0 and fe2 == 0x1a and fm2 == 0x06b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x686b; op2val:0x686b; + valaddr_reg:x6; val_offset:72*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x4*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x6, 72*FLEN/8, x7, x2, x4) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(28748,32,FLEN) +NAN_BOXED(28748,32,FLEN) +NAN_BOXED(31259,32,FLEN) +NAN_BOXED(31259,32,FLEN) +NAN_BOXED(30700,32,FLEN) +NAN_BOXED(30700,32,FLEN) +NAN_BOXED(31029,32,FLEN) +NAN_BOXED(31029,32,FLEN) +NAN_BOXED(28161,32,FLEN) +NAN_BOXED(28161,32,FLEN) +NAN_BOXED(31406,32,FLEN) +NAN_BOXED(31406,32,FLEN) +NAN_BOXED(31256,32,FLEN) +NAN_BOXED(31256,32,FLEN) +NAN_BOXED(30495,32,FLEN) +NAN_BOXED(30495,32,FLEN) +NAN_BOXED(29521,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(31541,32,FLEN) +NAN_BOXED(31541,32,FLEN) +NAN_BOXED(26243,32,FLEN) +NAN_BOXED(26243,32,FLEN) +NAN_BOXED(31618,32,FLEN) +NAN_BOXED(31618,32,FLEN) +NAN_BOXED(29421,32,FLEN) +NAN_BOXED(29421,32,FLEN) +test_dataset_1: +NAN_BOXED(26479,32,FLEN) +NAN_BOXED(26479,32,FLEN) +NAN_BOXED(30464,32,FLEN) +NAN_BOXED(30464,32,FLEN) +NAN_BOXED(29556,32,FLEN) +NAN_BOXED(29556,32,FLEN) +NAN_BOXED(29439,32,FLEN) +NAN_BOXED(29439,32,FLEN) +NAN_BOXED(29858,32,FLEN) +NAN_BOXED(29858,32,FLEN) +NAN_BOXED(31410,32,FLEN) +NAN_BOXED(31410,32,FLEN) +NAN_BOXED(31010,32,FLEN) +NAN_BOXED(31010,32,FLEN) +NAN_BOXED(31727,32,FLEN) +NAN_BOXED(31727,32,FLEN) +NAN_BOXED(28603,32,FLEN) +NAN_BOXED(28603,32,FLEN) +NAN_BOXED(31172,32,FLEN) +NAN_BOXED(31172,32,FLEN) +NAN_BOXED(31612,32,FLEN) +NAN_BOXED(31612,32,FLEN) +test_dataset_2: +NAN_BOXED(31395,16,FLEN) +NAN_BOXED(31395,16,FLEN) +NAN_BOXED(29914,16,FLEN) +NAN_BOXED(29914,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31502,16,FLEN) +NAN_BOXED(30730,16,FLEN) +NAN_BOXED(30730,16,FLEN) +NAN_BOXED(26731,16,FLEN) +NAN_BOXED(26731,16,FLEN) +NAN_BOXED(31328,16,FLEN) +NAN_BOXED(31328,16,FLEN) +NAN_BOXED(29064,16,FLEN) +NAN_BOXED(29064,16,FLEN) +NAN_BOXED(31135,16,FLEN) +NAN_BOXED(31135,16,FLEN) +NAN_BOXED(30206,16,FLEN) +NAN_BOXED(30206,16,FLEN) +NAN_BOXED(30736,16,FLEN) +NAN_BOXED(30736,16,FLEN) +NAN_BOXED(30762,16,FLEN) +NAN_BOXED(30762,16,FLEN) +NAN_BOXED(30676,16,FLEN) +NAN_BOXED(30676,16,FLEN) +NAN_BOXED(27024,16,FLEN) +NAN_BOXED(27024,16,FLEN) +NAN_BOXED(31708,16,FLEN) +NAN_BOXED(31708,16,FLEN) +NAN_BOXED(30283,16,FLEN) +NAN_BOXED(30283,16,FLEN) +NAN_BOXED(30724,16,FLEN) +NAN_BOXED(30724,16,FLEN) +NAN_BOXED(31273,16,FLEN) +NAN_BOXED(31273,16,FLEN) +NAN_BOXED(31457,16,FLEN) +NAN_BOXED(31457,16,FLEN) +NAN_BOXED(30747,16,FLEN) +NAN_BOXED(30745,16,FLEN) +NAN_BOXED(30878,16,FLEN) +NAN_BOXED(30876,16,FLEN) +NAN_BOXED(29774,16,FLEN) +NAN_BOXED(29770,16,FLEN) +NAN_BOXED(31655,16,FLEN) +NAN_BOXED(31653,16,FLEN) +NAN_BOXED(31300,16,FLEN) +NAN_BOXED(31298,16,FLEN) +NAN_BOXED(31510,16,FLEN) +NAN_BOXED(31508,16,FLEN) +NAN_BOXED(31352,16,FLEN) +NAN_BOXED(31350,16,FLEN) +NAN_BOXED(30845,16,FLEN) +NAN_BOXED(30845,16,FLEN) +NAN_BOXED(27438,16,FLEN) +NAN_BOXED(27438,16,FLEN) +NAN_BOXED(30862,16,FLEN) +NAN_BOXED(30862,16,FLEN) +NAN_BOXED(30729,16,FLEN) +NAN_BOXED(30729,16,FLEN) +NAN_BOXED(30132,16,FLEN) +NAN_BOXED(30132,16,FLEN) +NAN_BOXED(30798,16,FLEN) +NAN_BOXED(30798,16,FLEN) +NAN_BOXED(30949,16,FLEN) +NAN_BOXED(30949,16,FLEN) +NAN_BOXED(28748,16,FLEN) +NAN_BOXED(28748,16,FLEN) +NAN_BOXED(28161,16,FLEN) +NAN_BOXED(28161,16,FLEN) +NAN_BOXED(29521,16,FLEN) +NAN_BOXED(29521,16,FLEN) +NAN_BOXED(31502,16,FLEN) +NAN_BOXED(31502,16,FLEN) +NAN_BOXED(26731,16,FLEN) +NAN_BOXED(26731,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x2_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_1: + .fill 30*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x8_0: + .fill 22*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_2: + .fill 70*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zhinx/src/fsub_b8-01.S b/riscv-test-suite/rv32i_m/Zhinx/src/fsub_b8-01.S new file mode 100644 index 000000000..861ddd756 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zhinx/src/fsub_b8-01.S @@ -0,0 +1,15032 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 06:02:02 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fsub.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fsub.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fsub_b8 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fsub_b8) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x1,test_dataset_0) +RVTEST_SIGBASE(x10,signature_x10_1) + +inst_0: +// rs1 == rs2 == rd, rs1==x0, rs2==x0, rd==x0,fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ec and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ec and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x0; op2:x0; dest:x0; op1val:0x0; op2val:0x0; + valaddr_reg:x1; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x14*/ +TEST_FPRR_OP(fsub.h, x0, x0, x0, dyn, 0, 0, x1, 0*FLEN/8, x2, x10, x14) + +inst_1: +// rs2 == rd != rs1, rs1==x16, rs2==x31, rd==x31,fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ec and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ec and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x16; op2:x31; dest:x31; op1val:0x3aec; op2val:0x3aec; + valaddr_reg:x1; val_offset:2*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x14*/ +TEST_FPRR_OP(fsub.h, x31, x16, x31, dyn, 32, 0, x1, 2*FLEN/8, x2, x10, x14) + +inst_2: +// rs1 == rd != rs2, rs1==x8, rs2==x21, rd==x8,fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ec and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ec and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x8; op2:x21; dest:x8; op1val:0x3aec; op2val:0x3aec; + valaddr_reg:x1; val_offset:4*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x14*/ +TEST_FPRR_OP(fsub.h, x8, x8, x21, dyn, 64, 0, x1, 4*FLEN/8, x2, x10, x14) + +inst_3: +// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==x22, rs2==x24, rd==x15,fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ec and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ec and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x22; op2:x24; dest:x15; op1val:0x3aec; op2val:0x3aec; + valaddr_reg:x1; val_offset:6*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x14*/ +TEST_FPRR_OP(fsub.h, x15, x22, x24, dyn, 96, 0, x1, 6*FLEN/8, x2, x10, x14) + +inst_4: +// rs1 == rs2 != rd, rs1==x29, rs2==x29, rd==x18,fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ec and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ec and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x29; op2:x29; dest:x18; op1val:0x3aec; op2val:0x3aec; + valaddr_reg:x1; val_offset:8*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x14*/ +TEST_FPRR_OP(fsub.h, x18, x29, x29, dyn, 128, 0, x1, 8*FLEN/8, x2, x10, x14) + +inst_5: +// rs1==x17, rs2==x27, rd==x19,fs1 == 0 and fe1 == 0x0c and fm1 == 0x38f and fs2 == 0 and fe2 == 0x0c and fm2 == 0x38f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x17; op2:x27; dest:x19; op1val:0x338f; op2val:0x338f; + valaddr_reg:x1; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x14*/ +TEST_FPRR_OP(fsub.h, x19, x17, x27, dyn, 0, 0, x1, 10*FLEN/8, x2, x10, x14) + +inst_6: +// rs1==x7, rs2==x23, rd==x4,fs1 == 0 and fe1 == 0x0c and fm1 == 0x38f and fs2 == 0 and fe2 == 0x0c and fm2 == 0x38f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x7; op2:x23; dest:x4; op1val:0x338f; op2val:0x338f; + valaddr_reg:x1; val_offset:12*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x14*/ +TEST_FPRR_OP(fsub.h, x4, x7, x23, dyn, 32, 0, x1, 12*FLEN/8, x2, x10, x14) + +inst_7: +// rs1==x23, rs2==x22, rd==x11,fs1 == 0 and fe1 == 0x0c and fm1 == 0x38f and fs2 == 0 and fe2 == 0x0c and fm2 == 0x38f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x23; op2:x22; dest:x11; op1val:0x338f; op2val:0x338f; + valaddr_reg:x1; val_offset:14*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x14*/ +TEST_FPRR_OP(fsub.h, x11, x23, x22, dyn, 64, 0, x1, 14*FLEN/8, x2, x10, x14) + +inst_8: +// rs1==x15, rs2==x13, rd==x12,fs1 == 0 and fe1 == 0x0c and fm1 == 0x38f and fs2 == 0 and fe2 == 0x0c and fm2 == 0x38f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x15; op2:x13; dest:x12; op1val:0x338f; op2val:0x338f; + valaddr_reg:x1; val_offset:16*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x14*/ +TEST_FPRR_OP(fsub.h, x12, x15, x13, dyn, 96, 0, x1, 16*FLEN/8, x2, x10, x14) + +inst_9: +// rs1==x30, rs2==x17, rd==x25,fs1 == 0 and fe1 == 0x0c and fm1 == 0x38f and fs2 == 0 and fe2 == 0x0c and fm2 == 0x38f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x17; dest:x25; op1val:0x338f; op2val:0x338f; + valaddr_reg:x1; val_offset:18*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x14*/ +TEST_FPRR_OP(fsub.h, x25, x30, x17, dyn, 128, 0, x1, 18*FLEN/8, x2, x10, x14) + +inst_10: +// rs1==x4, rs2==x16, rd==x5,fs1 == 0 and fe1 == 0x0e and fm1 == 0x009 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x009 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x4; op2:x16; dest:x5; op1val:0x3809; op2val:0x3809; + valaddr_reg:x1; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x14*/ +TEST_FPRR_OP(fsub.h, x5, x4, x16, dyn, 0, 0, x1, 20*FLEN/8, x2, x10, x14) + +inst_11: +// rs1==x19, rs2==x6, rd==x23,fs1 == 0 and fe1 == 0x0e and fm1 == 0x009 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x009 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x19; op2:x6; dest:x23; op1val:0x3809; op2val:0x3809; + valaddr_reg:x1; val_offset:22*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x14*/ +TEST_FPRR_OP(fsub.h, x23, x19, x6, dyn, 32, 0, x1, 22*FLEN/8, x2, x10, x14) + +inst_12: +// rs1==x11, rs2==x7, rd==x16,fs1 == 0 and fe1 == 0x0e and fm1 == 0x009 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x009 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x11; op2:x7; dest:x16; op1val:0x3809; op2val:0x3809; + valaddr_reg:x1; val_offset:24*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x14*/ +TEST_FPRR_OP(fsub.h, x16, x11, x7, dyn, 64, 0, x1, 24*FLEN/8, x2, x10, x14) + +inst_13: +// rs1==x18, rs2==x4, rd==x3,fs1 == 0 and fe1 == 0x0e and fm1 == 0x009 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x009 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x18; op2:x4; dest:x3; op1val:0x3809; op2val:0x3809; + valaddr_reg:x1; val_offset:26*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x14*/ +TEST_FPRR_OP(fsub.h, x3, x18, x4, dyn, 96, 0, x1, 26*FLEN/8, x2, x10, x14) +RVTEST_VALBASEUPD(x11,test_dataset_1) + +inst_14: +// rs1==x6, rs2==x3, rd==x9,fs1 == 0 and fe1 == 0x0e and fm1 == 0x009 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x009 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x6; op2:x3; dest:x9; op1val:0x3809; op2val:0x3809; + valaddr_reg:x11; val_offset:0*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x14*/ +TEST_FPRR_OP(fsub.h, x9, x6, x3, dyn, 128, 0, x11, 0*FLEN/8, x13, x10, x14) + +inst_15: +// rs1==x1, rs2==x2, rd==x29,fs1 == 0 and fe1 == 0x0d and fm1 == 0x193 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x193 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x1; op2:x2; dest:x29; op1val:0x3593; op2val:0x3593; + valaddr_reg:x11; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x14*/ +TEST_FPRR_OP(fsub.h, x29, x1, x2, dyn, 0, 0, x11, 2*FLEN/8, x13, x10, x14) +RVTEST_SIGBASE(x4,signature_x4_0) + +inst_16: +// rs1==x28, rs2==x14, rd==x30,fs1 == 0 and fe1 == 0x0d and fm1 == 0x193 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x193 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x28; op2:x14; dest:x30; op1val:0x3593; op2val:0x3593; + valaddr_reg:x11; val_offset:4*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x30, x28, x14, dyn, 32, 0, x11, 4*FLEN/8, x13, x4, x6) + +inst_17: +// rs1==x31, rs2==x25, rd==x17,fs1 == 0 and fe1 == 0x0d and fm1 == 0x193 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x193 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x31; op2:x25; dest:x17; op1val:0x3593; op2val:0x3593; + valaddr_reg:x11; val_offset:6*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x17, x31, x25, dyn, 64, 0, x11, 6*FLEN/8, x13, x4, x6) + +inst_18: +// rs1==x10, rs2==x8, rd==x20,fs1 == 0 and fe1 == 0x0d and fm1 == 0x193 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x193 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x10; op2:x8; dest:x20; op1val:0x3593; op2val:0x3593; + valaddr_reg:x11; val_offset:8*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x20, x10, x8, dyn, 96, 0, x11, 8*FLEN/8, x13, x4, x6) + +inst_19: +// rs1==x3, rs2==x18, rd==x27,fs1 == 0 and fe1 == 0x0d and fm1 == 0x193 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x193 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x3; op2:x18; dest:x27; op1val:0x3593; op2val:0x3593; + valaddr_reg:x11; val_offset:10*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x27, x3, x18, dyn, 128, 0, x11, 10*FLEN/8, x13, x4, x6) + +inst_20: +// rs1==x26, rs2==x30, rd==x7,fs1 == 0 and fe1 == 0x0e and fm1 == 0x33f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x33f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x26; op2:x30; dest:x7; op1val:0x3b3f; op2val:0x3b3f; + valaddr_reg:x11; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x7, x26, x30, dyn, 0, 0, x11, 12*FLEN/8, x13, x4, x6) + +inst_21: +// rs1==x5, rs2==x19, rd==x14,fs1 == 0 and fe1 == 0x0e and fm1 == 0x33f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x33f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x5; op2:x19; dest:x14; op1val:0x3b3f; op2val:0x3b3f; + valaddr_reg:x11; val_offset:14*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x14, x5, x19, dyn, 32, 0, x11, 14*FLEN/8, x13, x4, x6) + +inst_22: +// rs1==x14, rs2==x12, rd==x26,fs1 == 0 and fe1 == 0x0e and fm1 == 0x33f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x33f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x14; op2:x12; dest:x26; op1val:0x3b3f; op2val:0x3b3f; + valaddr_reg:x11; val_offset:16*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x26, x14, x12, dyn, 64, 0, x11, 16*FLEN/8, x13, x4, x6) + +inst_23: +// rs1==x2, rs2==x20, rd==x10,fs1 == 0 and fe1 == 0x0e and fm1 == 0x33f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x33f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x2; op2:x20; dest:x10; op1val:0x3b3f; op2val:0x3b3f; + valaddr_reg:x11; val_offset:18*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x10, x2, x20, dyn, 96, 0, x11, 18*FLEN/8, x13, x4, x6) + +inst_24: +// rs1==x27, rs2==x28, rd==x24,fs1 == 0 and fe1 == 0x0e and fm1 == 0x33f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x33f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x27; op2:x28; dest:x24; op1val:0x3b3f; op2val:0x3b3f; + valaddr_reg:x11; val_offset:20*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x24, x27, x28, dyn, 128, 0, x11, 20*FLEN/8, x13, x4, x6) + +inst_25: +// rs1==x12, rs2==x1, rd==x22,fs1 == 0 and fe1 == 0x0c and fm1 == 0x141 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x141 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x12; op2:x1; dest:x22; op1val:0x3141; op2val:0x3141; + valaddr_reg:x11; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x22, x12, x1, dyn, 0, 0, x11, 22*FLEN/8, x13, x4, x6) +RVTEST_VALBASEUPD(x3,test_dataset_2) + +inst_26: +// rs1==x9, rs2==x26, rd==x21,fs1 == 0 and fe1 == 0x0c and fm1 == 0x141 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x141 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x9; op2:x26; dest:x21; op1val:0x3141; op2val:0x3141; + valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x21, x9, x26, dyn, 32, 0, x3, 0*FLEN/8, x7, x4, x6) + +inst_27: +// rs1==x25, rs2==x5, rd==x13,fs1 == 0 and fe1 == 0x0c and fm1 == 0x141 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x141 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x25; op2:x5; dest:x13; op1val:0x3141; op2val:0x3141; + valaddr_reg:x3; val_offset:2*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x13, x25, x5, dyn, 64, 0, x3, 2*FLEN/8, x7, x4, x6) + +inst_28: +// rs1==x13, rs2==x10, rd==x1,fs1 == 0 and fe1 == 0x0c and fm1 == 0x141 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x141 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x13; op2:x10; dest:x1; op1val:0x3141; op2val:0x3141; + valaddr_reg:x3; val_offset:4*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x1, x13, x10, dyn, 96, 0, x3, 4*FLEN/8, x7, x4, x6) + +inst_29: +// rs1==x21, rs2==x9, rd==x2,fs1 == 0 and fe1 == 0x0c and fm1 == 0x141 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x141 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x21; op2:x9; dest:x2; op1val:0x3141; op2val:0x3141; + valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x2, x21, x9, dyn, 128, 0, x3, 6*FLEN/8, x7, x4, x6) + +inst_30: +// rs1==x20, rs2==x11, rd==x28,fs1 == 0 and fe1 == 0x0c and fm1 == 0x39b and fs2 == 0 and fe2 == 0x0c and fm2 == 0x39b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x20; op2:x11; dest:x28; op1val:0x339b; op2val:0x339b; + valaddr_reg:x3; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x6*/ +TEST_FPRR_OP(fsub.h, x28, x20, x11, dyn, 0, 0, x3, 8*FLEN/8, x7, x4, x6) + +inst_31: +// rs1==x24, rs2==x15, rd==x6,fs1 == 0 and fe1 == 0x0c and fm1 == 0x39b and fs2 == 0 and fe2 == 0x0c and fm2 == 0x39b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x24; op2:x15; dest:x6; op1val:0x339b; op2val:0x339b; + valaddr_reg:x3; val_offset:10*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x6, x24, x15, dyn, 32, 0, x3, 10*FLEN/8, x7, x4, x2) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_32: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x39b and fs2 == 0 and fe2 == 0x0c and fm2 == 0x39b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x339b; op2val:0x339b; + valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 12*FLEN/8, x7, x1, x2) + +inst_33: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x39b and fs2 == 0 and fe2 == 0x0c and fm2 == 0x39b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x339b; op2val:0x339b; + valaddr_reg:x3; val_offset:14*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 14*FLEN/8, x7, x1, x2) + +inst_34: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x39b and fs2 == 0 and fe2 == 0x0c and fm2 == 0x39b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x339b; op2val:0x339b; + valaddr_reg:x3; val_offset:16*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 16*FLEN/8, x7, x1, x2) + +inst_35: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x06f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x06f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x386f; op2val:0x386f; + valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 18*FLEN/8, x7, x1, x2) + +inst_36: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x06f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x06f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x386f; op2val:0x386f; + valaddr_reg:x3; val_offset:20*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 20*FLEN/8, x7, x1, x2) + +inst_37: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x06f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x06f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x386f; op2val:0x386f; + valaddr_reg:x3; val_offset:22*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 22*FLEN/8, x7, x1, x2) + +inst_38: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x06f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x06f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x386f; op2val:0x386f; + valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 24*FLEN/8, x7, x1, x2) + +inst_39: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x06f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x06f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x386f; op2val:0x386f; + valaddr_reg:x3; val_offset:26*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 26*FLEN/8, x7, x1, x2) + +inst_40: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x22b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x22b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a2b; op2val:0x3a2b; + valaddr_reg:x3; val_offset:28*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 28*FLEN/8, x7, x1, x2) + +inst_41: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x22b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x22b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a2b; op2val:0x3a2b; + valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 30*FLEN/8, x7, x1, x2) + +inst_42: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x22b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x22b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a2b; op2val:0x3a2b; + valaddr_reg:x3; val_offset:32*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 32*FLEN/8, x7, x1, x2) + +inst_43: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x22b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x22b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a2b; op2val:0x3a2b; + valaddr_reg:x3; val_offset:34*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 34*FLEN/8, x7, x1, x2) + +inst_44: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x22b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x22b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a2b; op2val:0x3a2b; + valaddr_reg:x3; val_offset:36*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 36*FLEN/8, x7, x1, x2) + +inst_45: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x24f and fs2 == 0 and fe2 == 0x0b and fm2 == 0x24f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e4f; op2val:0x2e4f; + valaddr_reg:x3; val_offset:38*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 38*FLEN/8, x7, x1, x2) + +inst_46: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x24f and fs2 == 0 and fe2 == 0x0b and fm2 == 0x24f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e4f; op2val:0x2e4f; + valaddr_reg:x3; val_offset:40*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 40*FLEN/8, x7, x1, x2) + +inst_47: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x24f and fs2 == 0 and fe2 == 0x0b and fm2 == 0x24f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e4f; op2val:0x2e4f; + valaddr_reg:x3; val_offset:42*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 42*FLEN/8, x7, x1, x2) + +inst_48: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x24f and fs2 == 0 and fe2 == 0x0b and fm2 == 0x24f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e4f; op2val:0x2e4f; + valaddr_reg:x3; val_offset:44*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 44*FLEN/8, x7, x1, x2) + +inst_49: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x24f and fs2 == 0 and fe2 == 0x0b and fm2 == 0x24f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e4f; op2val:0x2e4f; + valaddr_reg:x3; val_offset:46*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 46*FLEN/8, x7, x1, x2) + +inst_50: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3cb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3cb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bcb; op2val:0x3bcb; + valaddr_reg:x3; val_offset:48*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 48*FLEN/8, x7, x1, x2) + +inst_51: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3cb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3cb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bcb; op2val:0x3bcb; + valaddr_reg:x3; val_offset:50*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 50*FLEN/8, x7, x1, x2) + +inst_52: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3cb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3cb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bcb; op2val:0x3bcb; + valaddr_reg:x3; val_offset:52*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 52*FLEN/8, x7, x1, x2) + +inst_53: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3cb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3cb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bcb; op2val:0x3bcb; + valaddr_reg:x3; val_offset:54*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 54*FLEN/8, x7, x1, x2) + +inst_54: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3cb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3cb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bcb; op2val:0x3bcb; + valaddr_reg:x3; val_offset:56*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 56*FLEN/8, x7, x1, x2) + +inst_55: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x3c9 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x3c9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2bc9; op2val:0x2bc9; + valaddr_reg:x3; val_offset:58*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 58*FLEN/8, x7, x1, x2) + +inst_56: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x3c9 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x3c9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2bc9; op2val:0x2bc9; + valaddr_reg:x3; val_offset:60*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 60*FLEN/8, x7, x1, x2) + +inst_57: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x3c9 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x3c9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2bc9; op2val:0x2bc9; + valaddr_reg:x3; val_offset:62*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 62*FLEN/8, x7, x1, x2) + +inst_58: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x3c9 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x3c9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2bc9; op2val:0x2bc9; + valaddr_reg:x3; val_offset:64*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 64*FLEN/8, x7, x1, x2) + +inst_59: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x3c9 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x3c9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2bc9; op2val:0x2bc9; + valaddr_reg:x3; val_offset:66*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 66*FLEN/8, x7, x1, x2) + +inst_60: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x244 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x244 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a44; op2val:0x3a44; + valaddr_reg:x3; val_offset:68*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 68*FLEN/8, x7, x1, x2) + +inst_61: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x244 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x244 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a44; op2val:0x3a44; + valaddr_reg:x3; val_offset:70*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 70*FLEN/8, x7, x1, x2) + +inst_62: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x244 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x244 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a44; op2val:0x3a44; + valaddr_reg:x3; val_offset:72*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 72*FLEN/8, x7, x1, x2) + +inst_63: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x244 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x244 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a44; op2val:0x3a44; + valaddr_reg:x3; val_offset:74*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 74*FLEN/8, x7, x1, x2) + +inst_64: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x244 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x244 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a44; op2val:0x3a44; + valaddr_reg:x3; val_offset:76*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 76*FLEN/8, x7, x1, x2) + +inst_65: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c4 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3c4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bc4; op2val:0x3bc4; + valaddr_reg:x3; val_offset:78*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 78*FLEN/8, x7, x1, x2) + +inst_66: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c4 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3c4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bc4; op2val:0x3bc4; + valaddr_reg:x3; val_offset:80*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 80*FLEN/8, x7, x1, x2) + +inst_67: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c4 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3c4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bc4; op2val:0x3bc4; + valaddr_reg:x3; val_offset:82*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 82*FLEN/8, x7, x1, x2) + +inst_68: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c4 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3c4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bc4; op2val:0x3bc4; + valaddr_reg:x3; val_offset:84*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 84*FLEN/8, x7, x1, x2) + +inst_69: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c4 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3c4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bc4; op2val:0x3bc4; + valaddr_reg:x3; val_offset:86*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 86*FLEN/8, x7, x1, x2) + +inst_70: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x07f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x387f; op2val:0x387f; + valaddr_reg:x3; val_offset:88*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 88*FLEN/8, x7, x1, x2) + +inst_71: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x07f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x07f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x387f; op2val:0x387f; + valaddr_reg:x3; val_offset:90*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 90*FLEN/8, x7, x1, x2) + +inst_72: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x07f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x07f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x387f; op2val:0x387f; + valaddr_reg:x3; val_offset:92*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 92*FLEN/8, x7, x1, x2) + +inst_73: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x07f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x07f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x387f; op2val:0x387f; + valaddr_reg:x3; val_offset:94*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 94*FLEN/8, x7, x1, x2) + +inst_74: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x07f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x07f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x387f; op2val:0x387f; + valaddr_reg:x3; val_offset:96*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 96*FLEN/8, x7, x1, x2) + +inst_75: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x222 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x222 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a22; op2val:0x3a22; + valaddr_reg:x3; val_offset:98*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 98*FLEN/8, x7, x1, x2) + +inst_76: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x222 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x222 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a22; op2val:0x3a22; + valaddr_reg:x3; val_offset:100*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 100*FLEN/8, x7, x1, x2) + +inst_77: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x222 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x222 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a22; op2val:0x3a22; + valaddr_reg:x3; val_offset:102*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 102*FLEN/8, x7, x1, x2) + +inst_78: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x222 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x222 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a22; op2val:0x3a22; + valaddr_reg:x3; val_offset:104*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 104*FLEN/8, x7, x1, x2) + +inst_79: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x222 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x222 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a22; op2val:0x3a22; + valaddr_reg:x3; val_offset:106*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 106*FLEN/8, x7, x1, x2) + +inst_80: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x23f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a3f; op2val:0x3a3f; + valaddr_reg:x3; val_offset:108*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 108*FLEN/8, x7, x1, x2) + +inst_81: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x23f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a3f; op2val:0x3a3f; + valaddr_reg:x3; val_offset:110*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 110*FLEN/8, x7, x1, x2) + +inst_82: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x23f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a3f; op2val:0x3a3f; + valaddr_reg:x3; val_offset:112*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 112*FLEN/8, x7, x1, x2) + +inst_83: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x23f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a3f; op2val:0x3a3f; + valaddr_reg:x3; val_offset:114*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 114*FLEN/8, x7, x1, x2) + +inst_84: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x23f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a3f; op2val:0x3a3f; + valaddr_reg:x3; val_offset:116*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 116*FLEN/8, x7, x1, x2) + +inst_85: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ae and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1ae and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39ae; op2val:0x39ae; + valaddr_reg:x3; val_offset:118*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 118*FLEN/8, x7, x1, x2) + +inst_86: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ae and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1ae and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39ae; op2val:0x39ae; + valaddr_reg:x3; val_offset:120*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 120*FLEN/8, x7, x1, x2) + +inst_87: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ae and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1ae and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39ae; op2val:0x39ae; + valaddr_reg:x3; val_offset:122*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 122*FLEN/8, x7, x1, x2) + +inst_88: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ae and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1ae and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39ae; op2val:0x39ae; + valaddr_reg:x3; val_offset:124*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 124*FLEN/8, x7, x1, x2) + +inst_89: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ae and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1ae and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39ae; op2val:0x39ae; + valaddr_reg:x3; val_offset:126*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 126*FLEN/8, x7, x1, x2) + +inst_90: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x132 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x132 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3132; op2val:0x3132; + valaddr_reg:x3; val_offset:128*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 128*FLEN/8, x7, x1, x2) + +inst_91: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x132 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x132 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3132; op2val:0x3132; + valaddr_reg:x3; val_offset:130*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 130*FLEN/8, x7, x1, x2) + +inst_92: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x132 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x132 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3132; op2val:0x3132; + valaddr_reg:x3; val_offset:132*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 132*FLEN/8, x7, x1, x2) + +inst_93: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x132 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x132 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3132; op2val:0x3132; + valaddr_reg:x3; val_offset:134*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 134*FLEN/8, x7, x1, x2) + +inst_94: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x132 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x132 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3132; op2val:0x3132; + valaddr_reg:x3; val_offset:136*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 136*FLEN/8, x7, x1, x2) + +inst_95: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1b9 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1b9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x35b9; op2val:0x35b9; + valaddr_reg:x3; val_offset:138*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 138*FLEN/8, x7, x1, x2) + +inst_96: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1b9 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1b9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x35b9; op2val:0x35b9; + valaddr_reg:x3; val_offset:140*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 140*FLEN/8, x7, x1, x2) + +inst_97: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1b9 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1b9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x35b9; op2val:0x35b9; + valaddr_reg:x3; val_offset:142*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 142*FLEN/8, x7, x1, x2) + +inst_98: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1b9 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1b9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x35b9; op2val:0x35b9; + valaddr_reg:x3; val_offset:144*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 144*FLEN/8, x7, x1, x2) + +inst_99: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1b9 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1b9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x35b9; op2val:0x35b9; + valaddr_reg:x3; val_offset:146*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 146*FLEN/8, x7, x1, x2) + +inst_100: +// fs1 == 0 and fe1 == 0x07 and fm1 == 0x3a2 and fs2 == 0 and fe2 == 0x07 and fm2 == 0x3a2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1fa2; op2val:0x1fa2; + valaddr_reg:x3; val_offset:148*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 148*FLEN/8, x7, x1, x2) + +inst_101: +// fs1 == 0 and fe1 == 0x07 and fm1 == 0x3a2 and fs2 == 0 and fe2 == 0x07 and fm2 == 0x3a2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1fa2; op2val:0x1fa2; + valaddr_reg:x3; val_offset:150*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 150*FLEN/8, x7, x1, x2) + +inst_102: +// fs1 == 0 and fe1 == 0x07 and fm1 == 0x3a2 and fs2 == 0 and fe2 == 0x07 and fm2 == 0x3a2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1fa2; op2val:0x1fa2; + valaddr_reg:x3; val_offset:152*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 152*FLEN/8, x7, x1, x2) + +inst_103: +// fs1 == 0 and fe1 == 0x07 and fm1 == 0x3a2 and fs2 == 0 and fe2 == 0x07 and fm2 == 0x3a2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1fa2; op2val:0x1fa2; + valaddr_reg:x3; val_offset:154*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 154*FLEN/8, x7, x1, x2) + +inst_104: +// fs1 == 0 and fe1 == 0x07 and fm1 == 0x3a2 and fs2 == 0 and fe2 == 0x07 and fm2 == 0x3a2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x1fa2; op2val:0x1fa2; + valaddr_reg:x3; val_offset:156*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 156*FLEN/8, x7, x1, x2) + +inst_105: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x308 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x308 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b08; op2val:0x3b08; + valaddr_reg:x3; val_offset:158*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 158*FLEN/8, x7, x1, x2) + +inst_106: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x308 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x308 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b08; op2val:0x3b08; + valaddr_reg:x3; val_offset:160*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 160*FLEN/8, x7, x1, x2) + +inst_107: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x308 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x308 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b08; op2val:0x3b08; + valaddr_reg:x3; val_offset:162*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 162*FLEN/8, x7, x1, x2) + +inst_108: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x308 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x308 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b08; op2val:0x3b08; + valaddr_reg:x3; val_offset:164*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 164*FLEN/8, x7, x1, x2) + +inst_109: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x308 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x308 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b08; op2val:0x3b08; + valaddr_reg:x3; val_offset:166*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 166*FLEN/8, x7, x1, x2) + +inst_110: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x074 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x074 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3474; op2val:0x3474; + valaddr_reg:x3; val_offset:168*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 168*FLEN/8, x7, x1, x2) + +inst_111: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x074 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x074 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3474; op2val:0x3474; + valaddr_reg:x3; val_offset:170*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 170*FLEN/8, x7, x1, x2) + +inst_112: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x074 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x074 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3474; op2val:0x3474; + valaddr_reg:x3; val_offset:172*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 172*FLEN/8, x7, x1, x2) + +inst_113: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x074 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x074 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3474; op2val:0x3474; + valaddr_reg:x3; val_offset:174*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 174*FLEN/8, x7, x1, x2) + +inst_114: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x074 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x074 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3474; op2val:0x3474; + valaddr_reg:x3; val_offset:176*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 176*FLEN/8, x7, x1, x2) + +inst_115: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x011 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x011 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2c11; op2val:0x2c11; + valaddr_reg:x3; val_offset:178*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 178*FLEN/8, x7, x1, x2) + +inst_116: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x011 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x011 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2c11; op2val:0x2c11; + valaddr_reg:x3; val_offset:180*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 180*FLEN/8, x7, x1, x2) + +inst_117: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x011 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x011 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2c11; op2val:0x2c11; + valaddr_reg:x3; val_offset:182*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 182*FLEN/8, x7, x1, x2) + +inst_118: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x011 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x011 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2c11; op2val:0x2c11; + valaddr_reg:x3; val_offset:184*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 184*FLEN/8, x7, x1, x2) + +inst_119: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x011 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x011 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2c11; op2val:0x2c11; + valaddr_reg:x3; val_offset:186*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 186*FLEN/8, x7, x1, x2) + +inst_120: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x170 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x170 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3170; op2val:0x3170; + valaddr_reg:x3; val_offset:188*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 188*FLEN/8, x7, x1, x2) + +inst_121: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x170 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x170 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3170; op2val:0x3170; + valaddr_reg:x3; val_offset:190*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 190*FLEN/8, x7, x1, x2) + +inst_122: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x170 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x170 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3170; op2val:0x3170; + valaddr_reg:x3; val_offset:192*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 192*FLEN/8, x7, x1, x2) + +inst_123: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x170 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x170 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3170; op2val:0x3170; + valaddr_reg:x3; val_offset:194*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 194*FLEN/8, x7, x1, x2) + +inst_124: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x170 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x170 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3170; op2val:0x3170; + valaddr_reg:x3; val_offset:196*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 196*FLEN/8, x7, x1, x2) + +inst_125: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x192 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x192 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3992; op2val:0x3992; + valaddr_reg:x3; val_offset:198*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 198*FLEN/8, x7, x1, x2) + +inst_126: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x192 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x192 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3992; op2val:0x3992; + valaddr_reg:x3; val_offset:200*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 200*FLEN/8, x7, x1, x2) + +inst_127: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x192 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x192 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3992; op2val:0x3992; + valaddr_reg:x3; val_offset:202*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 202*FLEN/8, x7, x1, x2) + +inst_128: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x192 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x192 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3992; op2val:0x3992; + valaddr_reg:x3; val_offset:204*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 204*FLEN/8, x7, x1, x2) + +inst_129: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x192 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x192 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3992; op2val:0x3992; + valaddr_reg:x3; val_offset:206*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 206*FLEN/8, x7, x1, x2) + +inst_130: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x385 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x385 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2f85; op2val:0x2f85; + valaddr_reg:x3; val_offset:208*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 208*FLEN/8, x7, x1, x2) + +inst_131: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x385 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x385 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2f85; op2val:0x2f85; + valaddr_reg:x3; val_offset:210*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 210*FLEN/8, x7, x1, x2) + +inst_132: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x385 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x385 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2f85; op2val:0x2f85; + valaddr_reg:x3; val_offset:212*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 212*FLEN/8, x7, x1, x2) + +inst_133: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x385 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x385 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2f85; op2val:0x2f85; + valaddr_reg:x3; val_offset:214*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 214*FLEN/8, x7, x1, x2) + +inst_134: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x385 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x385 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2f85; op2val:0x2f85; + valaddr_reg:x3; val_offset:216*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 216*FLEN/8, x7, x1, x2) + +inst_135: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ea and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3ea and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x37ea; op2val:0x37ea; + valaddr_reg:x3; val_offset:218*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 218*FLEN/8, x7, x1, x2) + +inst_136: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ea and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3ea and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x37ea; op2val:0x37ea; + valaddr_reg:x3; val_offset:220*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 220*FLEN/8, x7, x1, x2) + +inst_137: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ea and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3ea and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x37ea; op2val:0x37ea; + valaddr_reg:x3; val_offset:222*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 222*FLEN/8, x7, x1, x2) + +inst_138: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ea and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3ea and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x37ea; op2val:0x37ea; + valaddr_reg:x3; val_offset:224*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 224*FLEN/8, x7, x1, x2) + +inst_139: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ea and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3ea and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x37ea; op2val:0x37ea; + valaddr_reg:x3; val_offset:226*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 226*FLEN/8, x7, x1, x2) + +inst_140: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3b9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bb9; op2val:0x3bb9; + valaddr_reg:x3; val_offset:228*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 228*FLEN/8, x7, x1, x2) + +inst_141: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3b9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bb9; op2val:0x3bb9; + valaddr_reg:x3; val_offset:230*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 230*FLEN/8, x7, x1, x2) + +inst_142: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3b9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bb9; op2val:0x3bb9; + valaddr_reg:x3; val_offset:232*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 232*FLEN/8, x7, x1, x2) + +inst_143: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3b9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bb9; op2val:0x3bb9; + valaddr_reg:x3; val_offset:234*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 234*FLEN/8, x7, x1, x2) + +inst_144: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3b9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3b9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bb9; op2val:0x3bb9; + valaddr_reg:x3; val_offset:236*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 236*FLEN/8, x7, x1, x2) + +inst_145: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x27b and fs2 == 0 and fe2 == 0x0c and fm2 == 0x27b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x327b; op2val:0x327b; + valaddr_reg:x3; val_offset:238*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 238*FLEN/8, x7, x1, x2) + +inst_146: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x27b and fs2 == 0 and fe2 == 0x0c and fm2 == 0x27b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x327b; op2val:0x327b; + valaddr_reg:x3; val_offset:240*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 240*FLEN/8, x7, x1, x2) + +inst_147: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x27b and fs2 == 0 and fe2 == 0x0c and fm2 == 0x27b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x327b; op2val:0x327b; + valaddr_reg:x3; val_offset:242*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 242*FLEN/8, x7, x1, x2) + +inst_148: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x27b and fs2 == 0 and fe2 == 0x0c and fm2 == 0x27b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x327b; op2val:0x327b; + valaddr_reg:x3; val_offset:244*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 244*FLEN/8, x7, x1, x2) + +inst_149: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x27b and fs2 == 0 and fe2 == 0x0c and fm2 == 0x27b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x327b; op2val:0x327b; + valaddr_reg:x3; val_offset:246*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 246*FLEN/8, x7, x1, x2) + +inst_150: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x29d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x29d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a9d; op2val:0x3a9d; + valaddr_reg:x3; val_offset:248*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 248*FLEN/8, x7, x1, x2) + +inst_151: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x29d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x29d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a9d; op2val:0x3a9d; + valaddr_reg:x3; val_offset:250*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 250*FLEN/8, x7, x1, x2) + +inst_152: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x29d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x29d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a9d; op2val:0x3a9d; + valaddr_reg:x3; val_offset:252*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 252*FLEN/8, x7, x1, x2) + +inst_153: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x29d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x29d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a9d; op2val:0x3a9d; + valaddr_reg:x3; val_offset:254*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 254*FLEN/8, x7, x1, x2) + +inst_154: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x29d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x29d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a9d; op2val:0x3a9d; + valaddr_reg:x3; val_offset:256*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 256*FLEN/8, x7, x1, x2) + +inst_155: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0c0 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x34c0; op2val:0x34c0; + valaddr_reg:x3; val_offset:258*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 258*FLEN/8, x7, x1, x2) + +inst_156: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0c0 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0c0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x34c0; op2val:0x34c0; + valaddr_reg:x3; val_offset:260*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 260*FLEN/8, x7, x1, x2) + +inst_157: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0c0 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0c0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x34c0; op2val:0x34c0; + valaddr_reg:x3; val_offset:262*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 262*FLEN/8, x7, x1, x2) + +inst_158: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0c0 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0c0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x34c0; op2val:0x34c0; + valaddr_reg:x3; val_offset:264*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 264*FLEN/8, x7, x1, x2) + +inst_159: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0c0 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0c0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x34c0; op2val:0x34c0; + valaddr_reg:x3; val_offset:266*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 266*FLEN/8, x7, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_160: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3900; op2val:0x3900; + valaddr_reg:x3; val_offset:268*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 268*FLEN/8, x7, x1, x2) + +inst_161: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x100 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3900; op2val:0x3900; + valaddr_reg:x3; val_offset:270*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 270*FLEN/8, x7, x1, x2) + +inst_162: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x100 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3900; op2val:0x3900; + valaddr_reg:x3; val_offset:272*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 272*FLEN/8, x7, x1, x2) + +inst_163: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x100 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3900; op2val:0x3900; + valaddr_reg:x3; val_offset:274*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 274*FLEN/8, x7, x1, x2) + +inst_164: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x100 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3900; op2val:0x3900; + valaddr_reg:x3; val_offset:276*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 276*FLEN/8, x7, x1, x2) + +inst_165: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3dd and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3dd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x37dd; op2val:0x37dd; + valaddr_reg:x3; val_offset:278*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 278*FLEN/8, x7, x1, x2) + +inst_166: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3dd and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3dd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x37dd; op2val:0x37dd; + valaddr_reg:x3; val_offset:280*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 280*FLEN/8, x7, x1, x2) + +inst_167: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3dd and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3dd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x37dd; op2val:0x37dd; + valaddr_reg:x3; val_offset:282*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 282*FLEN/8, x7, x1, x2) + +inst_168: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3dd and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3dd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x37dd; op2val:0x37dd; + valaddr_reg:x3; val_offset:284*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 284*FLEN/8, x7, x1, x2) + +inst_169: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3dd and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3dd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x37dd; op2val:0x37dd; + valaddr_reg:x3; val_offset:286*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 286*FLEN/8, x7, x1, x2) + +inst_170: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3aa and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x37aa; op2val:0x37aa; + valaddr_reg:x3; val_offset:288*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 288*FLEN/8, x7, x1, x2) + +inst_171: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3aa and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3aa and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x37aa; op2val:0x37aa; + valaddr_reg:x3; val_offset:290*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 290*FLEN/8, x7, x1, x2) + +inst_172: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3aa and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3aa and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x37aa; op2val:0x37aa; + valaddr_reg:x3; val_offset:292*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 292*FLEN/8, x7, x1, x2) + +inst_173: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3aa and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3aa and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x37aa; op2val:0x37aa; + valaddr_reg:x3; val_offset:294*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 294*FLEN/8, x7, x1, x2) + +inst_174: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3aa and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3aa and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x37aa; op2val:0x37aa; + valaddr_reg:x3; val_offset:296*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 296*FLEN/8, x7, x1, x2) + +inst_175: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x015 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x015 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3815; op2val:0x3815; + valaddr_reg:x3; val_offset:298*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 298*FLEN/8, x7, x1, x2) + +inst_176: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x015 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x015 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3815; op2val:0x3815; + valaddr_reg:x3; val_offset:300*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 300*FLEN/8, x7, x1, x2) + +inst_177: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x015 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x015 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3815; op2val:0x3815; + valaddr_reg:x3; val_offset:302*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 302*FLEN/8, x7, x1, x2) + +inst_178: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x015 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x015 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3815; op2val:0x3815; + valaddr_reg:x3; val_offset:304*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 304*FLEN/8, x7, x1, x2) + +inst_179: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x015 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x015 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3815; op2val:0x3815; + valaddr_reg:x3; val_offset:306*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 306*FLEN/8, x7, x1, x2) + +inst_180: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3a6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3a6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ba6; op2val:0x3ba6; + valaddr_reg:x3; val_offset:308*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 308*FLEN/8, x7, x1, x2) + +inst_181: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3a6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3a6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ba6; op2val:0x3ba6; + valaddr_reg:x3; val_offset:310*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 310*FLEN/8, x7, x1, x2) + +inst_182: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3a6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3a6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ba6; op2val:0x3ba6; + valaddr_reg:x3; val_offset:312*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 312*FLEN/8, x7, x1, x2) + +inst_183: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3a6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3a6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ba6; op2val:0x3ba6; + valaddr_reg:x3; val_offset:314*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 314*FLEN/8, x7, x1, x2) + +inst_184: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3a6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3a6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ba6; op2val:0x3ba6; + valaddr_reg:x3; val_offset:316*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 316*FLEN/8, x7, x1, x2) + +inst_185: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x04d and fs2 == 0 and fe2 == 0x09 and fm2 == 0x04d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x244d; op2val:0x244d; + valaddr_reg:x3; val_offset:318*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 318*FLEN/8, x7, x1, x2) + +inst_186: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x04d and fs2 == 0 and fe2 == 0x09 and fm2 == 0x04d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x244d; op2val:0x244d; + valaddr_reg:x3; val_offset:320*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 320*FLEN/8, x7, x1, x2) + +inst_187: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x04d and fs2 == 0 and fe2 == 0x09 and fm2 == 0x04d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x244d; op2val:0x244d; + valaddr_reg:x3; val_offset:322*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 322*FLEN/8, x7, x1, x2) + +inst_188: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x04d and fs2 == 0 and fe2 == 0x09 and fm2 == 0x04d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x244d; op2val:0x244d; + valaddr_reg:x3; val_offset:324*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 324*FLEN/8, x7, x1, x2) + +inst_189: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x04d and fs2 == 0 and fe2 == 0x09 and fm2 == 0x04d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x244d; op2val:0x244d; + valaddr_reg:x3; val_offset:326*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 326*FLEN/8, x7, x1, x2) + +inst_190: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0d9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x38d9; op2val:0x38d9; + valaddr_reg:x3; val_offset:328*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 328*FLEN/8, x7, x1, x2) + +inst_191: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0d9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x38d9; op2val:0x38d9; + valaddr_reg:x3; val_offset:330*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 330*FLEN/8, x7, x1, x2) + +inst_192: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0d9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x38d9; op2val:0x38d9; + valaddr_reg:x3; val_offset:332*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 332*FLEN/8, x7, x1, x2) + +inst_193: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0d9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x38d9; op2val:0x38d9; + valaddr_reg:x3; val_offset:334*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 334*FLEN/8, x7, x1, x2) + +inst_194: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0d9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x38d9; op2val:0x38d9; + valaddr_reg:x3; val_offset:336*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 336*FLEN/8, x7, x1, x2) + +inst_195: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3f6 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3f6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x37f6; op2val:0x37f6; + valaddr_reg:x3; val_offset:338*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 338*FLEN/8, x7, x1, x2) + +inst_196: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3f6 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3f6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x37f6; op2val:0x37f6; + valaddr_reg:x3; val_offset:340*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 340*FLEN/8, x7, x1, x2) + +inst_197: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3f6 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3f6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x37f6; op2val:0x37f6; + valaddr_reg:x3; val_offset:342*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 342*FLEN/8, x7, x1, x2) + +inst_198: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3f6 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3f6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x37f6; op2val:0x37f6; + valaddr_reg:x3; val_offset:344*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 344*FLEN/8, x7, x1, x2) + +inst_199: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3f6 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3f6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x37f6; op2val:0x37f6; + valaddr_reg:x3; val_offset:346*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 346*FLEN/8, x7, x1, x2) + +inst_200: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x357 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x357 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3357; op2val:0x3357; + valaddr_reg:x3; val_offset:348*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 348*FLEN/8, x7, x1, x2) + +inst_201: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x357 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x357 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3357; op2val:0x3357; + valaddr_reg:x3; val_offset:350*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 350*FLEN/8, x7, x1, x2) + +inst_202: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x357 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x357 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3357; op2val:0x3357; + valaddr_reg:x3; val_offset:352*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 352*FLEN/8, x7, x1, x2) + +inst_203: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x357 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x357 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3357; op2val:0x3357; + valaddr_reg:x3; val_offset:354*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 354*FLEN/8, x7, x1, x2) + +inst_204: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x357 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x357 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3357; op2val:0x3357; + valaddr_reg:x3; val_offset:356*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 356*FLEN/8, x7, x1, x2) + +inst_205: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x078 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x078 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3078; op2val:0x3078; + valaddr_reg:x3; val_offset:358*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 358*FLEN/8, x7, x1, x2) + +inst_206: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x078 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x078 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3078; op2val:0x3078; + valaddr_reg:x3; val_offset:360*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 360*FLEN/8, x7, x1, x2) + +inst_207: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x078 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x078 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3078; op2val:0x3078; + valaddr_reg:x3; val_offset:362*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 362*FLEN/8, x7, x1, x2) + +inst_208: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x078 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x078 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3078; op2val:0x3078; + valaddr_reg:x3; val_offset:364*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 364*FLEN/8, x7, x1, x2) + +inst_209: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x078 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x078 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3078; op2val:0x3078; + valaddr_reg:x3; val_offset:366*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 366*FLEN/8, x7, x1, x2) + +inst_210: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3c7 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3c7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x37c7; op2val:0x37c7; + valaddr_reg:x3; val_offset:368*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 368*FLEN/8, x7, x1, x2) + +inst_211: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3c7 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3c7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x37c7; op2val:0x37c7; + valaddr_reg:x3; val_offset:370*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 370*FLEN/8, x7, x1, x2) + +inst_212: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3c7 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3c7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x37c7; op2val:0x37c7; + valaddr_reg:x3; val_offset:372*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 372*FLEN/8, x7, x1, x2) + +inst_213: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3c7 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3c7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x37c7; op2val:0x37c7; + valaddr_reg:x3; val_offset:374*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 374*FLEN/8, x7, x1, x2) + +inst_214: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3c7 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3c7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x37c7; op2val:0x37c7; + valaddr_reg:x3; val_offset:376*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 376*FLEN/8, x7, x1, x2) + +inst_215: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2c1 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2c1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x36c1; op2val:0x36c1; + valaddr_reg:x3; val_offset:378*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 378*FLEN/8, x7, x1, x2) + +inst_216: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2c1 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2c1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x36c1; op2val:0x36c1; + valaddr_reg:x3; val_offset:380*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 380*FLEN/8, x7, x1, x2) + +inst_217: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2c1 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2c1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x36c1; op2val:0x36c1; + valaddr_reg:x3; val_offset:382*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 382*FLEN/8, x7, x1, x2) + +inst_218: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2c1 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2c1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x36c1; op2val:0x36c1; + valaddr_reg:x3; val_offset:384*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 384*FLEN/8, x7, x1, x2) + +inst_219: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2c1 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2c1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x36c1; op2val:0x36c1; + valaddr_reg:x3; val_offset:386*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 386*FLEN/8, x7, x1, x2) + +inst_220: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1d8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1d8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39d8; op2val:0x39d8; + valaddr_reg:x3; val_offset:388*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 388*FLEN/8, x7, x1, x2) + +inst_221: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1d8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1d8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39d8; op2val:0x39d8; + valaddr_reg:x3; val_offset:390*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 390*FLEN/8, x7, x1, x2) + +inst_222: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1d8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1d8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39d8; op2val:0x39d8; + valaddr_reg:x3; val_offset:392*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 392*FLEN/8, x7, x1, x2) + +inst_223: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1d8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1d8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39d8; op2val:0x39d8; + valaddr_reg:x3; val_offset:394*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 394*FLEN/8, x7, x1, x2) + +inst_224: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1d8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1d8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39d8; op2val:0x39d8; + valaddr_reg:x3; val_offset:396*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 396*FLEN/8, x7, x1, x2) + +inst_225: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x17f and fs2 == 0 and fe2 == 0x0a and fm2 == 0x17d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x297f; op2val:0x297d; + valaddr_reg:x3; val_offset:398*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 398*FLEN/8, x7, x1, x2) + +inst_226: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x17f and fs2 == 0 and fe2 == 0x0a and fm2 == 0x17d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x297f; op2val:0x297d; + valaddr_reg:x3; val_offset:400*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 400*FLEN/8, x7, x1, x2) + +inst_227: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x17f and fs2 == 0 and fe2 == 0x0a and fm2 == 0x17d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x297f; op2val:0x297d; + valaddr_reg:x3; val_offset:402*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 402*FLEN/8, x7, x1, x2) + +inst_228: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x17f and fs2 == 0 and fe2 == 0x0a and fm2 == 0x17d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x297f; op2val:0x297d; + valaddr_reg:x3; val_offset:404*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 404*FLEN/8, x7, x1, x2) + +inst_229: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x17f and fs2 == 0 and fe2 == 0x0a and fm2 == 0x17d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x297f; op2val:0x297d; + valaddr_reg:x3; val_offset:406*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 406*FLEN/8, x7, x1, x2) + +inst_230: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2ec and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2ec and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x32ec; op2val:0x32ec; + valaddr_reg:x3; val_offset:408*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 408*FLEN/8, x7, x1, x2) + +inst_231: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2ec and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2ec and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x32ec; op2val:0x32ec; + valaddr_reg:x3; val_offset:410*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 410*FLEN/8, x7, x1, x2) + +inst_232: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2ec and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2ec and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x32ec; op2val:0x32ec; + valaddr_reg:x3; val_offset:412*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 412*FLEN/8, x7, x1, x2) + +inst_233: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2ec and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2ec and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x32ec; op2val:0x32ec; + valaddr_reg:x3; val_offset:414*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 414*FLEN/8, x7, x1, x2) + +inst_234: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2ec and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2ec and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x32ec; op2val:0x32ec; + valaddr_reg:x3; val_offset:416*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 416*FLEN/8, x7, x1, x2) + +inst_235: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x349 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x348 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2f49; op2val:0x2f48; + valaddr_reg:x3; val_offset:418*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 418*FLEN/8, x7, x1, x2) + +inst_236: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x349 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x348 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2f49; op2val:0x2f48; + valaddr_reg:x3; val_offset:420*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 420*FLEN/8, x7, x1, x2) + +inst_237: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x349 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x348 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2f49; op2val:0x2f48; + valaddr_reg:x3; val_offset:422*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 422*FLEN/8, x7, x1, x2) + +inst_238: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x349 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x348 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2f49; op2val:0x2f48; + valaddr_reg:x3; val_offset:424*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 424*FLEN/8, x7, x1, x2) + +inst_239: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x349 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x348 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2f49; op2val:0x2f48; + valaddr_reg:x3; val_offset:426*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 426*FLEN/8, x7, x1, x2) + +inst_240: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x21b and fs2 == 0 and fe2 == 0x0c and fm2 == 0x21b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x321b; op2val:0x321b; + valaddr_reg:x3; val_offset:428*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 428*FLEN/8, x7, x1, x2) + +inst_241: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x21b and fs2 == 0 and fe2 == 0x0c and fm2 == 0x21b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x321b; op2val:0x321b; + valaddr_reg:x3; val_offset:430*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 430*FLEN/8, x7, x1, x2) + +inst_242: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x21b and fs2 == 0 and fe2 == 0x0c and fm2 == 0x21b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x321b; op2val:0x321b; + valaddr_reg:x3; val_offset:432*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 432*FLEN/8, x7, x1, x2) + +inst_243: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x21b and fs2 == 0 and fe2 == 0x0c and fm2 == 0x21b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x321b; op2val:0x321b; + valaddr_reg:x3; val_offset:434*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 434*FLEN/8, x7, x1, x2) + +inst_244: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x21b and fs2 == 0 and fe2 == 0x0c and fm2 == 0x21b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x321b; op2val:0x321b; + valaddr_reg:x3; val_offset:436*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 436*FLEN/8, x7, x1, x2) + +inst_245: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x304 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x304 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3704; op2val:0x3704; + valaddr_reg:x3; val_offset:438*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 438*FLEN/8, x7, x1, x2) + +inst_246: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x304 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x304 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3704; op2val:0x3704; + valaddr_reg:x3; val_offset:440*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 440*FLEN/8, x7, x1, x2) + +inst_247: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x304 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x304 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3704; op2val:0x3704; + valaddr_reg:x3; val_offset:442*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 442*FLEN/8, x7, x1, x2) + +inst_248: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x304 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x304 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3704; op2val:0x3704; + valaddr_reg:x3; val_offset:444*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 444*FLEN/8, x7, x1, x2) + +inst_249: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x304 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x304 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3704; op2val:0x3704; + valaddr_reg:x3; val_offset:446*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 446*FLEN/8, x7, x1, x2) + +inst_250: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x38d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x38c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b8d; op2val:0x3b8c; + valaddr_reg:x3; val_offset:448*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 448*FLEN/8, x7, x1, x2) + +inst_251: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x38d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x38c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b8d; op2val:0x3b8c; + valaddr_reg:x3; val_offset:450*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 450*FLEN/8, x7, x1, x2) + +inst_252: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x38d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x38c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b8d; op2val:0x3b8c; + valaddr_reg:x3; val_offset:452*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 452*FLEN/8, x7, x1, x2) + +inst_253: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x38d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x38c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b8d; op2val:0x3b8c; + valaddr_reg:x3; val_offset:454*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 454*FLEN/8, x7, x1, x2) + +inst_254: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x38d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x38c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b8d; op2val:0x3b8c; + valaddr_reg:x3; val_offset:456*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 456*FLEN/8, x7, x1, x2) + +inst_255: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2e1 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2e1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x36e1; op2val:0x36e1; + valaddr_reg:x3; val_offset:458*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 458*FLEN/8, x7, x1, x2) + +inst_256: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2e1 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2e1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x36e1; op2val:0x36e1; + valaddr_reg:x3; val_offset:460*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 460*FLEN/8, x7, x1, x2) + +inst_257: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2e1 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2e1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x36e1; op2val:0x36e1; + valaddr_reg:x3; val_offset:462*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 462*FLEN/8, x7, x1, x2) + +inst_258: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2e1 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2e1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x36e1; op2val:0x36e1; + valaddr_reg:x3; val_offset:464*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 464*FLEN/8, x7, x1, x2) + +inst_259: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2e1 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2e1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x36e1; op2val:0x36e1; + valaddr_reg:x3; val_offset:466*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 466*FLEN/8, x7, x1, x2) + +inst_260: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ec and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3ec and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x37ec; op2val:0x37ec; + valaddr_reg:x3; val_offset:468*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 468*FLEN/8, x7, x1, x2) + +inst_261: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ec and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3ec and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x37ec; op2val:0x37ec; + valaddr_reg:x3; val_offset:470*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 470*FLEN/8, x7, x1, x2) + +inst_262: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ec and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3ec and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x37ec; op2val:0x37ec; + valaddr_reg:x3; val_offset:472*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 472*FLEN/8, x7, x1, x2) + +inst_263: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ec and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3ec and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x37ec; op2val:0x37ec; + valaddr_reg:x3; val_offset:474*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 474*FLEN/8, x7, x1, x2) + +inst_264: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ec and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3ec and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x37ec; op2val:0x37ec; + valaddr_reg:x3; val_offset:476*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 476*FLEN/8, x7, x1, x2) + +inst_265: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x125 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x125 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3925; op2val:0x3925; + valaddr_reg:x3; val_offset:478*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 478*FLEN/8, x7, x1, x2) + +inst_266: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x125 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x125 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3925; op2val:0x3925; + valaddr_reg:x3; val_offset:480*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 480*FLEN/8, x7, x1, x2) + +inst_267: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x125 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x125 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3925; op2val:0x3925; + valaddr_reg:x3; val_offset:482*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 482*FLEN/8, x7, x1, x2) + +inst_268: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x125 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x125 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3925; op2val:0x3925; + valaddr_reg:x3; val_offset:484*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 484*FLEN/8, x7, x1, x2) + +inst_269: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x125 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x125 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3925; op2val:0x3925; + valaddr_reg:x3; val_offset:486*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 486*FLEN/8, x7, x1, x2) + +inst_270: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x362 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x362 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3762; op2val:0x3762; + valaddr_reg:x3; val_offset:488*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 488*FLEN/8, x7, x1, x2) + +inst_271: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x362 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x362 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3762; op2val:0x3762; + valaddr_reg:x3; val_offset:490*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 490*FLEN/8, x7, x1, x2) + +inst_272: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x362 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x362 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3762; op2val:0x3762; + valaddr_reg:x3; val_offset:492*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 492*FLEN/8, x7, x1, x2) + +inst_273: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x362 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x362 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3762; op2val:0x3762; + valaddr_reg:x3; val_offset:494*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 494*FLEN/8, x7, x1, x2) + +inst_274: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x362 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x362 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3762; op2val:0x3762; + valaddr_reg:x3; val_offset:496*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 496*FLEN/8, x7, x1, x2) + +inst_275: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x233 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x233 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3633; op2val:0x3633; + valaddr_reg:x3; val_offset:498*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 498*FLEN/8, x7, x1, x2) + +inst_276: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x233 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x233 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3633; op2val:0x3633; + valaddr_reg:x3; val_offset:500*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 500*FLEN/8, x7, x1, x2) + +inst_277: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x233 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x233 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3633; op2val:0x3633; + valaddr_reg:x3; val_offset:502*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 502*FLEN/8, x7, x1, x2) + +inst_278: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x233 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x233 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3633; op2val:0x3633; + valaddr_reg:x3; val_offset:504*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 504*FLEN/8, x7, x1, x2) + +inst_279: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x233 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x233 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3633; op2val:0x3633; + valaddr_reg:x3; val_offset:506*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 506*FLEN/8, x7, x1, x2) + +inst_280: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3c6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bc6; op2val:0x3bc6; + valaddr_reg:x3; val_offset:508*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 508*FLEN/8, x7, x1, x2) + +inst_281: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3c6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bc6; op2val:0x3bc6; + valaddr_reg:x3; val_offset:510*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 510*FLEN/8, x7, x1, x2) + +inst_282: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3c6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bc6; op2val:0x3bc6; + valaddr_reg:x3; val_offset:512*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 512*FLEN/8, x7, x1, x2) + +inst_283: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3c6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bc6; op2val:0x3bc6; + valaddr_reg:x3; val_offset:514*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 514*FLEN/8, x7, x1, x2) + +inst_284: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3c6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bc6; op2val:0x3bc6; + valaddr_reg:x3; val_offset:516*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 516*FLEN/8, x7, x1, x2) + +inst_285: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x295 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x294 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a95; op2val:0x3a94; + valaddr_reg:x3; val_offset:518*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 518*FLEN/8, x7, x1, x2) + +inst_286: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x295 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x294 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a95; op2val:0x3a94; + valaddr_reg:x3; val_offset:520*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 520*FLEN/8, x7, x1, x2) + +inst_287: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x295 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x294 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a95; op2val:0x3a94; + valaddr_reg:x3; val_offset:522*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 522*FLEN/8, x7, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_2) + +inst_288: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x295 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x294 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a95; op2val:0x3a94; + valaddr_reg:x3; val_offset:524*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 524*FLEN/8, x7, x1, x2) + +inst_289: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x295 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x294 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a95; op2val:0x3a94; + valaddr_reg:x3; val_offset:526*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 526*FLEN/8, x7, x1, x2) + +inst_290: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x073 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x072 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3073; op2val:0x3072; + valaddr_reg:x3; val_offset:528*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 528*FLEN/8, x7, x1, x2) + +inst_291: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x073 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x072 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3073; op2val:0x3072; + valaddr_reg:x3; val_offset:530*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 530*FLEN/8, x7, x1, x2) + +inst_292: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x073 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x072 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3073; op2val:0x3072; + valaddr_reg:x3; val_offset:532*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 532*FLEN/8, x7, x1, x2) + +inst_293: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x073 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x072 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3073; op2val:0x3072; + valaddr_reg:x3; val_offset:534*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 534*FLEN/8, x7, x1, x2) + +inst_294: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x073 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x072 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3073; op2val:0x3072; + valaddr_reg:x3; val_offset:536*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 536*FLEN/8, x7, x1, x2) + +inst_295: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x27e and fs2 == 0 and fe2 == 0x0c and fm2 == 0x27e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x327e; op2val:0x327e; + valaddr_reg:x3; val_offset:538*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 538*FLEN/8, x7, x1, x2) + +inst_296: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x27e and fs2 == 0 and fe2 == 0x0c and fm2 == 0x27e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x327e; op2val:0x327e; + valaddr_reg:x3; val_offset:540*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 540*FLEN/8, x7, x1, x2) + +inst_297: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x27e and fs2 == 0 and fe2 == 0x0c and fm2 == 0x27e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x327e; op2val:0x327e; + valaddr_reg:x3; val_offset:542*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 542*FLEN/8, x7, x1, x2) + +inst_298: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x27e and fs2 == 0 and fe2 == 0x0c and fm2 == 0x27e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x327e; op2val:0x327e; + valaddr_reg:x3; val_offset:544*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 544*FLEN/8, x7, x1, x2) + +inst_299: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x27e and fs2 == 0 and fe2 == 0x0c and fm2 == 0x27e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x327e; op2val:0x327e; + valaddr_reg:x3; val_offset:546*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 546*FLEN/8, x7, x1, x2) + +inst_300: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1f5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1f5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39f5; op2val:0x39f5; + valaddr_reg:x3; val_offset:548*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 548*FLEN/8, x7, x1, x2) + +inst_301: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1f5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1f5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39f5; op2val:0x39f5; + valaddr_reg:x3; val_offset:550*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 550*FLEN/8, x7, x1, x2) + +inst_302: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1f5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1f5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39f5; op2val:0x39f5; + valaddr_reg:x3; val_offset:552*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 552*FLEN/8, x7, x1, x2) + +inst_303: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1f5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1f5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39f5; op2val:0x39f5; + valaddr_reg:x3; val_offset:554*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 554*FLEN/8, x7, x1, x2) + +inst_304: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1f5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1f5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39f5; op2val:0x39f5; + valaddr_reg:x3; val_offset:556*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 556*FLEN/8, x7, x1, x2) + +inst_305: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x13b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x13a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x353b; op2val:0x353a; + valaddr_reg:x3; val_offset:558*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 558*FLEN/8, x7, x1, x2) + +inst_306: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x13b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x13a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x353b; op2val:0x353a; + valaddr_reg:x3; val_offset:560*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 560*FLEN/8, x7, x1, x2) + +inst_307: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x13b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x13a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x353b; op2val:0x353a; + valaddr_reg:x3; val_offset:562*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 562*FLEN/8, x7, x1, x2) + +inst_308: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x13b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x13a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x353b; op2val:0x353a; + valaddr_reg:x3; val_offset:564*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 564*FLEN/8, x7, x1, x2) + +inst_309: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x13b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x13a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x353b; op2val:0x353a; + valaddr_reg:x3; val_offset:566*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 566*FLEN/8, x7, x1, x2) + +inst_310: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3dd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3dd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bdd; op2val:0x3bdd; + valaddr_reg:x3; val_offset:568*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 568*FLEN/8, x7, x1, x2) + +inst_311: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3dd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3dd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bdd; op2val:0x3bdd; + valaddr_reg:x3; val_offset:570*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 570*FLEN/8, x7, x1, x2) + +inst_312: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3dd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3dd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bdd; op2val:0x3bdd; + valaddr_reg:x3; val_offset:572*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 572*FLEN/8, x7, x1, x2) + +inst_313: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3dd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3dd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bdd; op2val:0x3bdd; + valaddr_reg:x3; val_offset:574*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 574*FLEN/8, x7, x1, x2) + +inst_314: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3dd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3dd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bdd; op2val:0x3bdd; + valaddr_reg:x3; val_offset:576*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 576*FLEN/8, x7, x1, x2) + +inst_315: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3d2 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3d2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x33d2; op2val:0x33d2; + valaddr_reg:x3; val_offset:578*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 578*FLEN/8, x7, x1, x2) + +inst_316: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3d2 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3d2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x33d2; op2val:0x33d2; + valaddr_reg:x3; val_offset:580*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 580*FLEN/8, x7, x1, x2) + +inst_317: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3d2 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3d2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x33d2; op2val:0x33d2; + valaddr_reg:x3; val_offset:582*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 582*FLEN/8, x7, x1, x2) + +inst_318: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3d2 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3d2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x33d2; op2val:0x33d2; + valaddr_reg:x3; val_offset:584*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 584*FLEN/8, x7, x1, x2) + +inst_319: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3d2 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3d2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x33d2; op2val:0x33d2; + valaddr_reg:x3; val_offset:586*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 586*FLEN/8, x7, x1, x2) + +inst_320: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x31f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b1f; op2val:0x3b1f; + valaddr_reg:x3; val_offset:588*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 588*FLEN/8, x7, x1, x2) + +inst_321: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x31f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b1f; op2val:0x3b1f; + valaddr_reg:x3; val_offset:590*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 590*FLEN/8, x7, x1, x2) + +inst_322: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x31f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b1f; op2val:0x3b1f; + valaddr_reg:x3; val_offset:592*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 592*FLEN/8, x7, x1, x2) + +inst_323: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x31f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b1f; op2val:0x3b1f; + valaddr_reg:x3; val_offset:594*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 594*FLEN/8, x7, x1, x2) + +inst_324: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x31f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b1f; op2val:0x3b1f; + valaddr_reg:x3; val_offset:596*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 596*FLEN/8, x7, x1, x2) + +inst_325: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x13e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x13e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x393e; op2val:0x393e; + valaddr_reg:x3; val_offset:598*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 598*FLEN/8, x7, x1, x2) + +inst_326: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x13e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x13e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x393e; op2val:0x393e; + valaddr_reg:x3; val_offset:600*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 600*FLEN/8, x7, x1, x2) + +inst_327: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x13e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x13e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x393e; op2val:0x393e; + valaddr_reg:x3; val_offset:602*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 602*FLEN/8, x7, x1, x2) + +inst_328: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x13e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x13e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x393e; op2val:0x393e; + valaddr_reg:x3; val_offset:604*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 604*FLEN/8, x7, x1, x2) + +inst_329: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x13e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x13e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x393e; op2val:0x393e; + valaddr_reg:x3; val_offset:606*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 606*FLEN/8, x7, x1, x2) + +inst_330: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2b8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ab9; op2val:0x3ab8; + valaddr_reg:x3; val_offset:608*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 608*FLEN/8, x7, x1, x2) + +inst_331: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2b8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ab9; op2val:0x3ab8; + valaddr_reg:x3; val_offset:610*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 610*FLEN/8, x7, x1, x2) + +inst_332: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2b8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ab9; op2val:0x3ab8; + valaddr_reg:x3; val_offset:612*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 612*FLEN/8, x7, x1, x2) + +inst_333: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2b8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ab9; op2val:0x3ab8; + valaddr_reg:x3; val_offset:614*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 614*FLEN/8, x7, x1, x2) + +inst_334: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2b8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ab9; op2val:0x3ab8; + valaddr_reg:x3; val_offset:616*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 616*FLEN/8, x7, x1, x2) + +inst_335: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2a7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2a7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aa7; op2val:0x3aa7; + valaddr_reg:x3; val_offset:618*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 618*FLEN/8, x7, x1, x2) + +inst_336: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2a7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2a7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aa7; op2val:0x3aa7; + valaddr_reg:x3; val_offset:620*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 620*FLEN/8, x7, x1, x2) + +inst_337: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2a7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2a7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aa7; op2val:0x3aa7; + valaddr_reg:x3; val_offset:622*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 622*FLEN/8, x7, x1, x2) + +inst_338: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2a7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2a7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aa7; op2val:0x3aa7; + valaddr_reg:x3; val_offset:624*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 624*FLEN/8, x7, x1, x2) + +inst_339: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2a7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2a7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aa7; op2val:0x3aa7; + valaddr_reg:x3; val_offset:626*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 626*FLEN/8, x7, x1, x2) + +inst_340: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x09d and fs2 == 0 and fe2 == 0x0d and fm2 == 0x09d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x349d; op2val:0x349d; + valaddr_reg:x3; val_offset:628*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 628*FLEN/8, x7, x1, x2) + +inst_341: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x09d and fs2 == 0 and fe2 == 0x0d and fm2 == 0x09d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x349d; op2val:0x349d; + valaddr_reg:x3; val_offset:630*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 630*FLEN/8, x7, x1, x2) + +inst_342: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x09d and fs2 == 0 and fe2 == 0x0d and fm2 == 0x09d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x349d; op2val:0x349d; + valaddr_reg:x3; val_offset:632*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 632*FLEN/8, x7, x1, x2) + +inst_343: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x09d and fs2 == 0 and fe2 == 0x0d and fm2 == 0x09d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x349d; op2val:0x349d; + valaddr_reg:x3; val_offset:634*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 634*FLEN/8, x7, x1, x2) + +inst_344: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x09d and fs2 == 0 and fe2 == 0x0d and fm2 == 0x09d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x349d; op2val:0x349d; + valaddr_reg:x3; val_offset:636*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 636*FLEN/8, x7, x1, x2) + +inst_345: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x16c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x16c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x396c; op2val:0x396c; + valaddr_reg:x3; val_offset:638*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 638*FLEN/8, x7, x1, x2) + +inst_346: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x16c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x16c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x396c; op2val:0x396c; + valaddr_reg:x3; val_offset:640*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 640*FLEN/8, x7, x1, x2) + +inst_347: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x16c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x16c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x396c; op2val:0x396c; + valaddr_reg:x3; val_offset:642*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 642*FLEN/8, x7, x1, x2) + +inst_348: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x16c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x16c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x396c; op2val:0x396c; + valaddr_reg:x3; val_offset:644*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 644*FLEN/8, x7, x1, x2) + +inst_349: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x16c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x16c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x396c; op2val:0x396c; + valaddr_reg:x3; val_offset:646*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 646*FLEN/8, x7, x1, x2) + +inst_350: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3cf and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3cf and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bcf; op2val:0x3bcf; + valaddr_reg:x3; val_offset:648*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 648*FLEN/8, x7, x1, x2) + +inst_351: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3cf and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3cf and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bcf; op2val:0x3bcf; + valaddr_reg:x3; val_offset:650*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 650*FLEN/8, x7, x1, x2) + +inst_352: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3cf and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3cf and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bcf; op2val:0x3bcf; + valaddr_reg:x3; val_offset:652*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 652*FLEN/8, x7, x1, x2) + +inst_353: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3cf and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3cf and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bcf; op2val:0x3bcf; + valaddr_reg:x3; val_offset:654*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 654*FLEN/8, x7, x1, x2) + +inst_354: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3cf and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3cf and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bcf; op2val:0x3bcf; + valaddr_reg:x3; val_offset:656*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 656*FLEN/8, x7, x1, x2) + +inst_355: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0a2 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0a1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x38a2; op2val:0x38a1; + valaddr_reg:x3; val_offset:658*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 658*FLEN/8, x7, x1, x2) + +inst_356: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0a2 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0a1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x38a2; op2val:0x38a1; + valaddr_reg:x3; val_offset:660*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 660*FLEN/8, x7, x1, x2) + +inst_357: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0a2 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0a1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x38a2; op2val:0x38a1; + valaddr_reg:x3; val_offset:662*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 662*FLEN/8, x7, x1, x2) + +inst_358: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0a2 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0a1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x38a2; op2val:0x38a1; + valaddr_reg:x3; val_offset:664*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 664*FLEN/8, x7, x1, x2) + +inst_359: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0a2 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0a1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x38a2; op2val:0x38a1; + valaddr_reg:x3; val_offset:666*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 666*FLEN/8, x7, x1, x2) + +inst_360: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x321 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x321 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b21; op2val:0x3b21; + valaddr_reg:x3; val_offset:668*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 668*FLEN/8, x7, x1, x2) + +inst_361: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x321 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x321 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b21; op2val:0x3b21; + valaddr_reg:x3; val_offset:670*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 670*FLEN/8, x7, x1, x2) + +inst_362: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x321 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x321 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b21; op2val:0x3b21; + valaddr_reg:x3; val_offset:672*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 672*FLEN/8, x7, x1, x2) + +inst_363: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x321 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x321 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b21; op2val:0x3b21; + valaddr_reg:x3; val_offset:674*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 674*FLEN/8, x7, x1, x2) + +inst_364: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x321 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x321 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b21; op2val:0x3b21; + valaddr_reg:x3; val_offset:676*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 676*FLEN/8, x7, x1, x2) + +inst_365: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3d6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x37d6; op2val:0x37d6; + valaddr_reg:x3; val_offset:678*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 678*FLEN/8, x7, x1, x2) + +inst_366: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3d6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x37d6; op2val:0x37d6; + valaddr_reg:x3; val_offset:680*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 680*FLEN/8, x7, x1, x2) + +inst_367: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3d6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x37d6; op2val:0x37d6; + valaddr_reg:x3; val_offset:682*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 682*FLEN/8, x7, x1, x2) + +inst_368: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3d6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x37d6; op2val:0x37d6; + valaddr_reg:x3; val_offset:684*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 684*FLEN/8, x7, x1, x2) + +inst_369: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3d6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x37d6; op2val:0x37d6; + valaddr_reg:x3; val_offset:686*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 686*FLEN/8, x7, x1, x2) + +inst_370: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x24f and fs2 == 0 and fe2 == 0x0d and fm2 == 0x24f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x364f; op2val:0x364f; + valaddr_reg:x3; val_offset:688*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 688*FLEN/8, x7, x1, x2) + +inst_371: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x24f and fs2 == 0 and fe2 == 0x0d and fm2 == 0x24f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x364f; op2val:0x364f; + valaddr_reg:x3; val_offset:690*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 690*FLEN/8, x7, x1, x2) + +inst_372: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x24f and fs2 == 0 and fe2 == 0x0d and fm2 == 0x24f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x364f; op2val:0x364f; + valaddr_reg:x3; val_offset:692*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 692*FLEN/8, x7, x1, x2) + +inst_373: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x24f and fs2 == 0 and fe2 == 0x0d and fm2 == 0x24f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x364f; op2val:0x364f; + valaddr_reg:x3; val_offset:694*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 694*FLEN/8, x7, x1, x2) + +inst_374: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x24f and fs2 == 0 and fe2 == 0x0d and fm2 == 0x24f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x364f; op2val:0x364f; + valaddr_reg:x3; val_offset:696*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 696*FLEN/8, x7, x1, x2) + +inst_375: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3d5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bd5; op2val:0x3bd5; + valaddr_reg:x3; val_offset:698*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 698*FLEN/8, x7, x1, x2) + +inst_376: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3d5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bd5; op2val:0x3bd5; + valaddr_reg:x3; val_offset:700*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 700*FLEN/8, x7, x1, x2) + +inst_377: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3d5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bd5; op2val:0x3bd5; + valaddr_reg:x3; val_offset:702*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 702*FLEN/8, x7, x1, x2) + +inst_378: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3d5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bd5; op2val:0x3bd5; + valaddr_reg:x3; val_offset:704*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 704*FLEN/8, x7, x1, x2) + +inst_379: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3d5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bd5; op2val:0x3bd5; + valaddr_reg:x3; val_offset:706*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 706*FLEN/8, x7, x1, x2) + +inst_380: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d4 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ad4; op2val:0x3ad3; + valaddr_reg:x3; val_offset:708*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 708*FLEN/8, x7, x1, x2) + +inst_381: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d4 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ad4; op2val:0x3ad3; + valaddr_reg:x3; val_offset:710*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 710*FLEN/8, x7, x1, x2) + +inst_382: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d4 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ad4; op2val:0x3ad3; + valaddr_reg:x3; val_offset:712*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 712*FLEN/8, x7, x1, x2) + +inst_383: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d4 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ad4; op2val:0x3ad3; + valaddr_reg:x3; val_offset:714*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 714*FLEN/8, x7, x1, x2) + +inst_384: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d4 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ad4; op2val:0x3ad3; + valaddr_reg:x3; val_offset:716*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 716*FLEN/8, x7, x1, x2) + +inst_385: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2b7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ab7; op2val:0x3ab7; + valaddr_reg:x3; val_offset:718*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 718*FLEN/8, x7, x1, x2) + +inst_386: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2b7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ab7; op2val:0x3ab7; + valaddr_reg:x3; val_offset:720*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 720*FLEN/8, x7, x1, x2) + +inst_387: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2b7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ab7; op2val:0x3ab7; + valaddr_reg:x3; val_offset:722*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 722*FLEN/8, x7, x1, x2) + +inst_388: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2b7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ab7; op2val:0x3ab7; + valaddr_reg:x3; val_offset:724*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 724*FLEN/8, x7, x1, x2) + +inst_389: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2b7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ab7; op2val:0x3ab7; + valaddr_reg:x3; val_offset:726*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 726*FLEN/8, x7, x1, x2) + +inst_390: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x126 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x126 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3526; op2val:0x3526; + valaddr_reg:x3; val_offset:728*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 728*FLEN/8, x7, x1, x2) + +inst_391: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x126 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x126 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3526; op2val:0x3526; + valaddr_reg:x3; val_offset:730*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 730*FLEN/8, x7, x1, x2) + +inst_392: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x126 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x126 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3526; op2val:0x3526; + valaddr_reg:x3; val_offset:732*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 732*FLEN/8, x7, x1, x2) + +inst_393: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x126 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x126 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3526; op2val:0x3526; + valaddr_reg:x3; val_offset:734*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 734*FLEN/8, x7, x1, x2) + +inst_394: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x126 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x126 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3526; op2val:0x3526; + valaddr_reg:x3; val_offset:736*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 736*FLEN/8, x7, x1, x2) + +inst_395: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x23c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a3c; op2val:0x3a3c; + valaddr_reg:x3; val_offset:738*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 738*FLEN/8, x7, x1, x2) + +inst_396: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x23c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a3c; op2val:0x3a3c; + valaddr_reg:x3; val_offset:740*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 740*FLEN/8, x7, x1, x2) + +inst_397: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x23c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a3c; op2val:0x3a3c; + valaddr_reg:x3; val_offset:742*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 742*FLEN/8, x7, x1, x2) + +inst_398: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x23c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a3c; op2val:0x3a3c; + valaddr_reg:x3; val_offset:744*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 744*FLEN/8, x7, x1, x2) + +inst_399: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x23c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a3c; op2val:0x3a3c; + valaddr_reg:x3; val_offset:746*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 746*FLEN/8, x7, x1, x2) + +inst_400: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x278 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x278 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3278; op2val:0x3278; + valaddr_reg:x3; val_offset:748*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 748*FLEN/8, x7, x1, x2) + +inst_401: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x278 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x278 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3278; op2val:0x3278; + valaddr_reg:x3; val_offset:750*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 750*FLEN/8, x7, x1, x2) + +inst_402: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x278 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x278 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3278; op2val:0x3278; + valaddr_reg:x3; val_offset:752*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 752*FLEN/8, x7, x1, x2) + +inst_403: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x278 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x278 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3278; op2val:0x3278; + valaddr_reg:x3; val_offset:754*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 754*FLEN/8, x7, x1, x2) + +inst_404: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x278 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x278 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3278; op2val:0x3278; + valaddr_reg:x3; val_offset:756*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 756*FLEN/8, x7, x1, x2) + +inst_405: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x236 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x236 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a36; op2val:0x3a36; + valaddr_reg:x3; val_offset:758*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 758*FLEN/8, x7, x1, x2) + +inst_406: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x236 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x236 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a36; op2val:0x3a36; + valaddr_reg:x3; val_offset:760*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 760*FLEN/8, x7, x1, x2) + +inst_407: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x236 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x236 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a36; op2val:0x3a36; + valaddr_reg:x3; val_offset:762*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 762*FLEN/8, x7, x1, x2) + +inst_408: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x236 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x236 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a36; op2val:0x3a36; + valaddr_reg:x3; val_offset:764*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 764*FLEN/8, x7, x1, x2) + +inst_409: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x236 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x236 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a36; op2val:0x3a36; + valaddr_reg:x3; val_offset:766*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 766*FLEN/8, x7, x1, x2) + +inst_410: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0d7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x38d7; op2val:0x38d7; + valaddr_reg:x3; val_offset:768*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 768*FLEN/8, x7, x1, x2) + +inst_411: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0d7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x38d7; op2val:0x38d7; + valaddr_reg:x3; val_offset:770*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 770*FLEN/8, x7, x1, x2) + +inst_412: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0d7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x38d7; op2val:0x38d7; + valaddr_reg:x3; val_offset:772*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 772*FLEN/8, x7, x1, x2) + +inst_413: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0d7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x38d7; op2val:0x38d7; + valaddr_reg:x3; val_offset:774*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 774*FLEN/8, x7, x1, x2) + +inst_414: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0d7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x38d7; op2val:0x38d7; + valaddr_reg:x3; val_offset:776*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 776*FLEN/8, x7, x1, x2) + +inst_415: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x16e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x16e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x396e; op2val:0x396e; + valaddr_reg:x3; val_offset:778*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 778*FLEN/8, x7, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_3) + +inst_416: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x16e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x16e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x396e; op2val:0x396e; + valaddr_reg:x3; val_offset:780*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 780*FLEN/8, x7, x1, x2) + +inst_417: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x16e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x16e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x396e; op2val:0x396e; + valaddr_reg:x3; val_offset:782*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 782*FLEN/8, x7, x1, x2) + +inst_418: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x16e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x16e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x396e; op2val:0x396e; + valaddr_reg:x3; val_offset:784*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 784*FLEN/8, x7, x1, x2) + +inst_419: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x16e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x16e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x396e; op2val:0x396e; + valaddr_reg:x3; val_offset:786*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 786*FLEN/8, x7, x1, x2) + +inst_420: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x387 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x387 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b87; op2val:0x3b87; + valaddr_reg:x3; val_offset:788*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 788*FLEN/8, x7, x1, x2) + +inst_421: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x387 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x387 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b87; op2val:0x3b87; + valaddr_reg:x3; val_offset:790*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 790*FLEN/8, x7, x1, x2) + +inst_422: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x387 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x387 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b87; op2val:0x3b87; + valaddr_reg:x3; val_offset:792*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 792*FLEN/8, x7, x1, x2) + +inst_423: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x387 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x387 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b87; op2val:0x3b87; + valaddr_reg:x3; val_offset:794*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 794*FLEN/8, x7, x1, x2) + +inst_424: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x387 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x387 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b87; op2val:0x3b87; + valaddr_reg:x3; val_offset:796*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 796*FLEN/8, x7, x1, x2) + +inst_425: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x01d and fs2 == 0 and fe2 == 0x0a and fm2 == 0x01b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x281d; op2val:0x281b; + valaddr_reg:x3; val_offset:798*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 798*FLEN/8, x7, x1, x2) + +inst_426: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x01d and fs2 == 0 and fe2 == 0x0a and fm2 == 0x01b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x281d; op2val:0x281b; + valaddr_reg:x3; val_offset:800*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 800*FLEN/8, x7, x1, x2) + +inst_427: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x01d and fs2 == 0 and fe2 == 0x0a and fm2 == 0x01b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x281d; op2val:0x281b; + valaddr_reg:x3; val_offset:802*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 802*FLEN/8, x7, x1, x2) + +inst_428: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x01d and fs2 == 0 and fe2 == 0x0a and fm2 == 0x01b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x281d; op2val:0x281b; + valaddr_reg:x3; val_offset:804*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 804*FLEN/8, x7, x1, x2) + +inst_429: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x01d and fs2 == 0 and fe2 == 0x0a and fm2 == 0x01b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x281d; op2val:0x281b; + valaddr_reg:x3; val_offset:806*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 806*FLEN/8, x7, x1, x2) + +inst_430: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x18c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x18c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x398c; op2val:0x398c; + valaddr_reg:x3; val_offset:808*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 808*FLEN/8, x7, x1, x2) + +inst_431: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x18c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x18c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x398c; op2val:0x398c; + valaddr_reg:x3; val_offset:810*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 810*FLEN/8, x7, x1, x2) + +inst_432: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x18c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x18c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x398c; op2val:0x398c; + valaddr_reg:x3; val_offset:812*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 812*FLEN/8, x7, x1, x2) + +inst_433: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x18c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x18c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x398c; op2val:0x398c; + valaddr_reg:x3; val_offset:814*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 814*FLEN/8, x7, x1, x2) + +inst_434: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x18c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x18c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x398c; op2val:0x398c; + valaddr_reg:x3; val_offset:816*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 816*FLEN/8, x7, x1, x2) + +inst_435: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x184 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x184 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3984; op2val:0x3984; + valaddr_reg:x3; val_offset:818*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 818*FLEN/8, x7, x1, x2) + +inst_436: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x184 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x184 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3984; op2val:0x3984; + valaddr_reg:x3; val_offset:820*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 820*FLEN/8, x7, x1, x2) + +inst_437: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x184 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x184 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3984; op2val:0x3984; + valaddr_reg:x3; val_offset:822*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 822*FLEN/8, x7, x1, x2) + +inst_438: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x184 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x184 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3984; op2val:0x3984; + valaddr_reg:x3; val_offset:824*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 824*FLEN/8, x7, x1, x2) + +inst_439: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x184 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x184 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3984; op2val:0x3984; + valaddr_reg:x3; val_offset:826*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 826*FLEN/8, x7, x1, x2) + +inst_440: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x019 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x019 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3419; op2val:0x3419; + valaddr_reg:x3; val_offset:828*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 828*FLEN/8, x7, x1, x2) + +inst_441: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x019 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x019 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3419; op2val:0x3419; + valaddr_reg:x3; val_offset:830*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 830*FLEN/8, x7, x1, x2) + +inst_442: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x019 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x019 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3419; op2val:0x3419; + valaddr_reg:x3; val_offset:832*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 832*FLEN/8, x7, x1, x2) + +inst_443: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x019 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x019 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3419; op2val:0x3419; + valaddr_reg:x3; val_offset:834*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 834*FLEN/8, x7, x1, x2) + +inst_444: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x019 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x019 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3419; op2val:0x3419; + valaddr_reg:x3; val_offset:836*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 836*FLEN/8, x7, x1, x2) + +inst_445: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1fb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39fb; op2val:0x39fb; + valaddr_reg:x3; val_offset:838*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 838*FLEN/8, x7, x1, x2) + +inst_446: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1fb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39fb; op2val:0x39fb; + valaddr_reg:x3; val_offset:840*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 840*FLEN/8, x7, x1, x2) + +inst_447: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1fb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39fb; op2val:0x39fb; + valaddr_reg:x3; val_offset:842*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 842*FLEN/8, x7, x1, x2) + +inst_448: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1fb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39fb; op2val:0x39fb; + valaddr_reg:x3; val_offset:844*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 844*FLEN/8, x7, x1, x2) + +inst_449: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1fb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39fb; op2val:0x39fb; + valaddr_reg:x3; val_offset:846*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 846*FLEN/8, x7, x1, x2) + +inst_450: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3c3 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3c3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2fc3; op2val:0x2fc3; + valaddr_reg:x3; val_offset:848*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 848*FLEN/8, x7, x1, x2) + +inst_451: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3c3 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3c3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2fc3; op2val:0x2fc3; + valaddr_reg:x3; val_offset:850*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 850*FLEN/8, x7, x1, x2) + +inst_452: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3c3 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3c3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2fc3; op2val:0x2fc3; + valaddr_reg:x3; val_offset:852*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 852*FLEN/8, x7, x1, x2) + +inst_453: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3c3 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3c3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2fc3; op2val:0x2fc3; + valaddr_reg:x3; val_offset:854*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 854*FLEN/8, x7, x1, x2) + +inst_454: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3c3 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3c3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2fc3; op2val:0x2fc3; + valaddr_reg:x3; val_offset:856*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 856*FLEN/8, x7, x1, x2) + +inst_455: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1c7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x31c7; op2val:0x31c7; + valaddr_reg:x3; val_offset:858*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 858*FLEN/8, x7, x1, x2) + +inst_456: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1c7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x31c7; op2val:0x31c7; + valaddr_reg:x3; val_offset:860*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 860*FLEN/8, x7, x1, x2) + +inst_457: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1c7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x31c7; op2val:0x31c7; + valaddr_reg:x3; val_offset:862*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 862*FLEN/8, x7, x1, x2) + +inst_458: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1c7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x31c7; op2val:0x31c7; + valaddr_reg:x3; val_offset:864*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 864*FLEN/8, x7, x1, x2) + +inst_459: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1c7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x31c7; op2val:0x31c7; + valaddr_reg:x3; val_offset:866*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 866*FLEN/8, x7, x1, x2) + +inst_460: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2e0 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x36e0; op2val:0x36e0; + valaddr_reg:x3; val_offset:868*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 868*FLEN/8, x7, x1, x2) + +inst_461: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2e0 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2e0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x36e0; op2val:0x36e0; + valaddr_reg:x3; val_offset:870*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 870*FLEN/8, x7, x1, x2) + +inst_462: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2e0 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2e0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x36e0; op2val:0x36e0; + valaddr_reg:x3; val_offset:872*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 872*FLEN/8, x7, x1, x2) + +inst_463: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2e0 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2e0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x36e0; op2val:0x36e0; + valaddr_reg:x3; val_offset:874*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 874*FLEN/8, x7, x1, x2) + +inst_464: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2e0 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2e0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x36e0; op2val:0x36e0; + valaddr_reg:x3; val_offset:876*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 876*FLEN/8, x7, x1, x2) + +inst_465: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x03b and fs2 == 0 and fe2 == 0x0c and fm2 == 0x03b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x303b; op2val:0x303b; + valaddr_reg:x3; val_offset:878*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 878*FLEN/8, x7, x1, x2) + +inst_466: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x03b and fs2 == 0 and fe2 == 0x0c and fm2 == 0x03b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x303b; op2val:0x303b; + valaddr_reg:x3; val_offset:880*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 880*FLEN/8, x7, x1, x2) + +inst_467: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x03b and fs2 == 0 and fe2 == 0x0c and fm2 == 0x03b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x303b; op2val:0x303b; + valaddr_reg:x3; val_offset:882*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 882*FLEN/8, x7, x1, x2) + +inst_468: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x03b and fs2 == 0 and fe2 == 0x0c and fm2 == 0x03b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x303b; op2val:0x303b; + valaddr_reg:x3; val_offset:884*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 884*FLEN/8, x7, x1, x2) + +inst_469: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x03b and fs2 == 0 and fe2 == 0x0c and fm2 == 0x03b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x303b; op2val:0x303b; + valaddr_reg:x3; val_offset:886*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 886*FLEN/8, x7, x1, x2) + +inst_470: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0bc and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0bc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x34bc; op2val:0x34bc; + valaddr_reg:x3; val_offset:888*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 888*FLEN/8, x7, x1, x2) + +inst_471: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0bc and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0bc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x34bc; op2val:0x34bc; + valaddr_reg:x3; val_offset:890*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 890*FLEN/8, x7, x1, x2) + +inst_472: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0bc and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0bc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x34bc; op2val:0x34bc; + valaddr_reg:x3; val_offset:892*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 892*FLEN/8, x7, x1, x2) + +inst_473: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0bc and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0bc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x34bc; op2val:0x34bc; + valaddr_reg:x3; val_offset:894*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 894*FLEN/8, x7, x1, x2) + +inst_474: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0bc and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0bc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x34bc; op2val:0x34bc; + valaddr_reg:x3; val_offset:896*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 896*FLEN/8, x7, x1, x2) + +inst_475: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0f9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0f9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x38f9; op2val:0x38f9; + valaddr_reg:x3; val_offset:898*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 898*FLEN/8, x7, x1, x2) + +inst_476: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0f9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0f9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x38f9; op2val:0x38f9; + valaddr_reg:x3; val_offset:900*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 900*FLEN/8, x7, x1, x2) + +inst_477: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0f9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0f9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x38f9; op2val:0x38f9; + valaddr_reg:x3; val_offset:902*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 902*FLEN/8, x7, x1, x2) + +inst_478: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0f9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0f9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x38f9; op2val:0x38f9; + valaddr_reg:x3; val_offset:904*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 904*FLEN/8, x7, x1, x2) + +inst_479: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0f9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0f9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x38f9; op2val:0x38f9; + valaddr_reg:x3; val_offset:906*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 906*FLEN/8, x7, x1, x2) + +inst_480: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x25a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x25a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a5a; op2val:0x3a5a; + valaddr_reg:x3; val_offset:908*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 908*FLEN/8, x7, x1, x2) + +inst_481: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x25a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x25a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a5a; op2val:0x3a5a; + valaddr_reg:x3; val_offset:910*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 910*FLEN/8, x7, x1, x2) + +inst_482: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x25a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x25a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a5a; op2val:0x3a5a; + valaddr_reg:x3; val_offset:912*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 912*FLEN/8, x7, x1, x2) + +inst_483: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x25a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x25a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a5a; op2val:0x3a5a; + valaddr_reg:x3; val_offset:914*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 914*FLEN/8, x7, x1, x2) + +inst_484: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x25a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x25a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a5a; op2val:0x3a5a; + valaddr_reg:x3; val_offset:916*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 916*FLEN/8, x7, x1, x2) + +inst_485: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x089 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x089 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3889; op2val:0x3889; + valaddr_reg:x3; val_offset:918*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 918*FLEN/8, x7, x1, x2) + +inst_486: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x089 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x089 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3889; op2val:0x3889; + valaddr_reg:x3; val_offset:920*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 920*FLEN/8, x7, x1, x2) + +inst_487: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x089 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x089 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3889; op2val:0x3889; + valaddr_reg:x3; val_offset:922*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 922*FLEN/8, x7, x1, x2) + +inst_488: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x089 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x089 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3889; op2val:0x3889; + valaddr_reg:x3; val_offset:924*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 924*FLEN/8, x7, x1, x2) + +inst_489: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x089 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x089 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3889; op2val:0x3889; + valaddr_reg:x3; val_offset:926*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 926*FLEN/8, x7, x1, x2) + +inst_490: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x32a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x32a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b2a; op2val:0x3b2a; + valaddr_reg:x3; val_offset:928*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 928*FLEN/8, x7, x1, x2) + +inst_491: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x32a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x32a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b2a; op2val:0x3b2a; + valaddr_reg:x3; val_offset:930*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 930*FLEN/8, x7, x1, x2) + +inst_492: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x32a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x32a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b2a; op2val:0x3b2a; + valaddr_reg:x3; val_offset:932*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 932*FLEN/8, x7, x1, x2) + +inst_493: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x32a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x32a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b2a; op2val:0x3b2a; + valaddr_reg:x3; val_offset:934*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 934*FLEN/8, x7, x1, x2) + +inst_494: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x32a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x32a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b2a; op2val:0x3b2a; + valaddr_reg:x3; val_offset:936*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 936*FLEN/8, x7, x1, x2) + +inst_495: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a1 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1a1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39a1; op2val:0x39a1; + valaddr_reg:x3; val_offset:938*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 938*FLEN/8, x7, x1, x2) + +inst_496: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a1 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1a1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39a1; op2val:0x39a1; + valaddr_reg:x3; val_offset:940*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 940*FLEN/8, x7, x1, x2) + +inst_497: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a1 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1a1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39a1; op2val:0x39a1; + valaddr_reg:x3; val_offset:942*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 942*FLEN/8, x7, x1, x2) + +inst_498: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a1 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1a1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39a1; op2val:0x39a1; + valaddr_reg:x3; val_offset:944*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 944*FLEN/8, x7, x1, x2) + +inst_499: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1a1 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1a1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39a1; op2val:0x39a1; + valaddr_reg:x3; val_offset:946*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 946*FLEN/8, x7, x1, x2) + +inst_500: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x165 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x165 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3965; op2val:0x3965; + valaddr_reg:x3; val_offset:948*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 948*FLEN/8, x7, x1, x2) + +inst_501: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x165 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x165 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3965; op2val:0x3965; + valaddr_reg:x3; val_offset:950*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 950*FLEN/8, x7, x1, x2) + +inst_502: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x165 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x165 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3965; op2val:0x3965; + valaddr_reg:x3; val_offset:952*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 952*FLEN/8, x7, x1, x2) + +inst_503: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x165 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x165 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3965; op2val:0x3965; + valaddr_reg:x3; val_offset:954*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 954*FLEN/8, x7, x1, x2) + +inst_504: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x165 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x165 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3965; op2val:0x3965; + valaddr_reg:x3; val_offset:956*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 956*FLEN/8, x7, x1, x2) + +inst_505: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x26c and fs2 == 0 and fe2 == 0x0b and fm2 == 0x26b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e6c; op2val:0x2e6b; + valaddr_reg:x3; val_offset:958*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 958*FLEN/8, x7, x1, x2) + +inst_506: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x26c and fs2 == 0 and fe2 == 0x0b and fm2 == 0x26b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e6c; op2val:0x2e6b; + valaddr_reg:x3; val_offset:960*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 960*FLEN/8, x7, x1, x2) + +inst_507: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x26c and fs2 == 0 and fe2 == 0x0b and fm2 == 0x26b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e6c; op2val:0x2e6b; + valaddr_reg:x3; val_offset:962*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 962*FLEN/8, x7, x1, x2) + +inst_508: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x26c and fs2 == 0 and fe2 == 0x0b and fm2 == 0x26b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e6c; op2val:0x2e6b; + valaddr_reg:x3; val_offset:964*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 964*FLEN/8, x7, x1, x2) + +inst_509: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x26c and fs2 == 0 and fe2 == 0x0b and fm2 == 0x26b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2e6c; op2val:0x2e6b; + valaddr_reg:x3; val_offset:966*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 966*FLEN/8, x7, x1, x2) + +inst_510: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x264 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x264 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a64; op2val:0x3a64; + valaddr_reg:x3; val_offset:968*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 968*FLEN/8, x7, x1, x2) + +inst_511: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x264 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x264 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a64; op2val:0x3a64; + valaddr_reg:x3; val_offset:970*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 970*FLEN/8, x7, x1, x2) + +inst_512: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x264 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x264 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a64; op2val:0x3a64; + valaddr_reg:x3; val_offset:972*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 972*FLEN/8, x7, x1, x2) + +inst_513: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x264 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x264 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a64; op2val:0x3a64; + valaddr_reg:x3; val_offset:974*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 974*FLEN/8, x7, x1, x2) + +inst_514: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x264 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x264 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a64; op2val:0x3a64; + valaddr_reg:x3; val_offset:976*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 976*FLEN/8, x7, x1, x2) + +inst_515: +// fs1 == 0 and fe1 == 0x08 and fm1 == 0x2a6 and fs2 == 0 and fe2 == 0x08 and fm2 == 0x2a1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x22a6; op2val:0x22a1; + valaddr_reg:x3; val_offset:978*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 978*FLEN/8, x7, x1, x2) + +inst_516: +// fs1 == 0 and fe1 == 0x08 and fm1 == 0x2a6 and fs2 == 0 and fe2 == 0x08 and fm2 == 0x2a1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x22a6; op2val:0x22a1; + valaddr_reg:x3; val_offset:980*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 980*FLEN/8, x7, x1, x2) + +inst_517: +// fs1 == 0 and fe1 == 0x08 and fm1 == 0x2a6 and fs2 == 0 and fe2 == 0x08 and fm2 == 0x2a1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x22a6; op2val:0x22a1; + valaddr_reg:x3; val_offset:982*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 982*FLEN/8, x7, x1, x2) + +inst_518: +// fs1 == 0 and fe1 == 0x08 and fm1 == 0x2a6 and fs2 == 0 and fe2 == 0x08 and fm2 == 0x2a1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x22a6; op2val:0x22a1; + valaddr_reg:x3; val_offset:984*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 984*FLEN/8, x7, x1, x2) + +inst_519: +// fs1 == 0 and fe1 == 0x08 and fm1 == 0x2a6 and fs2 == 0 and fe2 == 0x08 and fm2 == 0x2a1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x22a6; op2val:0x22a1; + valaddr_reg:x3; val_offset:986*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 986*FLEN/8, x7, x1, x2) + +inst_520: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x149 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x149 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3949; op2val:0x3949; + valaddr_reg:x3; val_offset:988*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 988*FLEN/8, x7, x1, x2) + +inst_521: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x149 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x149 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3949; op2val:0x3949; + valaddr_reg:x3; val_offset:990*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 990*FLEN/8, x7, x1, x2) + +inst_522: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x149 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x149 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3949; op2val:0x3949; + valaddr_reg:x3; val_offset:992*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 992*FLEN/8, x7, x1, x2) + +inst_523: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x149 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x149 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3949; op2val:0x3949; + valaddr_reg:x3; val_offset:994*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 994*FLEN/8, x7, x1, x2) + +inst_524: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x149 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x149 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3949; op2val:0x3949; + valaddr_reg:x3; val_offset:996*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 996*FLEN/8, x7, x1, x2) + +inst_525: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x135 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x135 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3535; op2val:0x3535; + valaddr_reg:x3; val_offset:998*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 998*FLEN/8, x7, x1, x2) + +inst_526: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x135 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x135 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3535; op2val:0x3535; + valaddr_reg:x3; val_offset:1000*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1000*FLEN/8, x7, x1, x2) + +inst_527: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x135 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x135 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3535; op2val:0x3535; + valaddr_reg:x3; val_offset:1002*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1002*FLEN/8, x7, x1, x2) + +inst_528: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x135 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x135 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3535; op2val:0x3535; + valaddr_reg:x3; val_offset:1004*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1004*FLEN/8, x7, x1, x2) + +inst_529: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x135 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x135 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3535; op2val:0x3535; + valaddr_reg:x3; val_offset:1006*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1006*FLEN/8, x7, x1, x2) + +inst_530: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x057 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x056 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2c57; op2val:0x2c56; + valaddr_reg:x3; val_offset:1008*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1008*FLEN/8, x7, x1, x2) + +inst_531: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x057 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x056 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2c57; op2val:0x2c56; + valaddr_reg:x3; val_offset:1010*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1010*FLEN/8, x7, x1, x2) + +inst_532: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x057 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x056 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2c57; op2val:0x2c56; + valaddr_reg:x3; val_offset:1012*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1012*FLEN/8, x7, x1, x2) + +inst_533: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x057 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x056 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2c57; op2val:0x2c56; + valaddr_reg:x3; val_offset:1014*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1014*FLEN/8, x7, x1, x2) + +inst_534: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x057 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x056 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2c57; op2val:0x2c56; + valaddr_reg:x3; val_offset:1016*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1016*FLEN/8, x7, x1, x2) + +inst_535: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x387 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x386 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2f87; op2val:0x2f86; + valaddr_reg:x3; val_offset:1018*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1018*FLEN/8, x7, x1, x2) + +inst_536: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x387 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x386 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2f87; op2val:0x2f86; + valaddr_reg:x3; val_offset:1020*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1020*FLEN/8, x7, x1, x2) + +inst_537: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x387 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x386 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2f87; op2val:0x2f86; + valaddr_reg:x3; val_offset:1022*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1022*FLEN/8, x7, x1, x2) + +inst_538: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x387 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x386 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2f87; op2val:0x2f86; + valaddr_reg:x3; val_offset:1024*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1024*FLEN/8, x7, x1, x2) + +inst_539: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x387 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x386 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2f87; op2val:0x2f86; + valaddr_reg:x3; val_offset:1026*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1026*FLEN/8, x7, x1, x2) + +inst_540: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x01f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x01f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x381f; op2val:0x381f; + valaddr_reg:x3; val_offset:1028*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1028*FLEN/8, x7, x1, x2) + +inst_541: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x01f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x01f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x381f; op2val:0x381f; + valaddr_reg:x3; val_offset:1030*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1030*FLEN/8, x7, x1, x2) + +inst_542: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x01f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x01f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x381f; op2val:0x381f; + valaddr_reg:x3; val_offset:1032*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1032*FLEN/8, x7, x1, x2) + +inst_543: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x01f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x01f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x381f; op2val:0x381f; + valaddr_reg:x3; val_offset:1034*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1034*FLEN/8, x7, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_4) + +inst_544: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x01f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x01f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x381f; op2val:0x381f; + valaddr_reg:x3; val_offset:1036*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1036*FLEN/8, x7, x1, x2) + +inst_545: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x21f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x21f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a1f; op2val:0x3a1f; + valaddr_reg:x3; val_offset:1038*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1038*FLEN/8, x7, x1, x2) + +inst_546: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x21f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x21f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a1f; op2val:0x3a1f; + valaddr_reg:x3; val_offset:1040*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1040*FLEN/8, x7, x1, x2) + +inst_547: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x21f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x21f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a1f; op2val:0x3a1f; + valaddr_reg:x3; val_offset:1042*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1042*FLEN/8, x7, x1, x2) + +inst_548: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x21f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x21f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a1f; op2val:0x3a1f; + valaddr_reg:x3; val_offset:1044*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1044*FLEN/8, x7, x1, x2) + +inst_549: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x21f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x21f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a1f; op2val:0x3a1f; + valaddr_reg:x3; val_offset:1046*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1046*FLEN/8, x7, x1, x2) + +inst_550: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x352 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x352 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b52; op2val:0x3b52; + valaddr_reg:x3; val_offset:1048*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1048*FLEN/8, x7, x1, x2) + +inst_551: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x352 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x352 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b52; op2val:0x3b52; + valaddr_reg:x3; val_offset:1050*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1050*FLEN/8, x7, x1, x2) + +inst_552: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x352 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x352 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b52; op2val:0x3b52; + valaddr_reg:x3; val_offset:1052*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1052*FLEN/8, x7, x1, x2) + +inst_553: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x352 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x352 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b52; op2val:0x3b52; + valaddr_reg:x3; val_offset:1054*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1054*FLEN/8, x7, x1, x2) + +inst_554: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x352 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x352 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b52; op2val:0x3b52; + valaddr_reg:x3; val_offset:1056*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1056*FLEN/8, x7, x1, x2) + +inst_555: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1b2 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x1b2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2db2; op2val:0x2db2; + valaddr_reg:x3; val_offset:1058*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1058*FLEN/8, x7, x1, x2) + +inst_556: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1b2 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x1b2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2db2; op2val:0x2db2; + valaddr_reg:x3; val_offset:1060*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1060*FLEN/8, x7, x1, x2) + +inst_557: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1b2 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x1b2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2db2; op2val:0x2db2; + valaddr_reg:x3; val_offset:1062*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1062*FLEN/8, x7, x1, x2) + +inst_558: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1b2 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x1b2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2db2; op2val:0x2db2; + valaddr_reg:x3; val_offset:1064*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1064*FLEN/8, x7, x1, x2) + +inst_559: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1b2 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x1b2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2db2; op2val:0x2db2; + valaddr_reg:x3; val_offset:1066*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1066*FLEN/8, x7, x1, x2) + +inst_560: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3b5 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3b5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x33b5; op2val:0x33b5; + valaddr_reg:x3; val_offset:1068*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1068*FLEN/8, x7, x1, x2) + +inst_561: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3b5 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3b5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x33b5; op2val:0x33b5; + valaddr_reg:x3; val_offset:1070*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1070*FLEN/8, x7, x1, x2) + +inst_562: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3b5 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3b5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x33b5; op2val:0x33b5; + valaddr_reg:x3; val_offset:1072*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1072*FLEN/8, x7, x1, x2) + +inst_563: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3b5 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3b5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x33b5; op2val:0x33b5; + valaddr_reg:x3; val_offset:1074*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1074*FLEN/8, x7, x1, x2) + +inst_564: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3b5 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3b5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x33b5; op2val:0x33b5; + valaddr_reg:x3; val_offset:1076*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1076*FLEN/8, x7, x1, x2) + +inst_565: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x115 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x115 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3115; op2val:0x3115; + valaddr_reg:x3; val_offset:1078*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1078*FLEN/8, x7, x1, x2) + +inst_566: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x115 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x115 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3115; op2val:0x3115; + valaddr_reg:x3; val_offset:1080*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1080*FLEN/8, x7, x1, x2) + +inst_567: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x115 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x115 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3115; op2val:0x3115; + valaddr_reg:x3; val_offset:1082*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1082*FLEN/8, x7, x1, x2) + +inst_568: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x115 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x115 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3115; op2val:0x3115; + valaddr_reg:x3; val_offset:1084*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1084*FLEN/8, x7, x1, x2) + +inst_569: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x115 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x115 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3115; op2val:0x3115; + valaddr_reg:x3; val_offset:1086*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1086*FLEN/8, x7, x1, x2) + +inst_570: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x147 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x147 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3947; op2val:0x3947; + valaddr_reg:x3; val_offset:1088*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1088*FLEN/8, x7, x1, x2) + +inst_571: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x147 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x147 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3947; op2val:0x3947; + valaddr_reg:x3; val_offset:1090*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1090*FLEN/8, x7, x1, x2) + +inst_572: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x147 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x147 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3947; op2val:0x3947; + valaddr_reg:x3; val_offset:1092*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1092*FLEN/8, x7, x1, x2) + +inst_573: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x147 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x147 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3947; op2val:0x3947; + valaddr_reg:x3; val_offset:1094*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1094*FLEN/8, x7, x1, x2) + +inst_574: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x147 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x147 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3947; op2val:0x3947; + valaddr_reg:x3; val_offset:1096*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1096*FLEN/8, x7, x1, x2) + +inst_575: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x03e and fs2 == 0 and fe2 == 0x0c and fm2 == 0x03e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x303e; op2val:0x303e; + valaddr_reg:x3; val_offset:1098*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1098*FLEN/8, x7, x1, x2) + +inst_576: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x03e and fs2 == 0 and fe2 == 0x0c and fm2 == 0x03e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x303e; op2val:0x303e; + valaddr_reg:x3; val_offset:1100*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1100*FLEN/8, x7, x1, x2) + +inst_577: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x03e and fs2 == 0 and fe2 == 0x0c and fm2 == 0x03e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x303e; op2val:0x303e; + valaddr_reg:x3; val_offset:1102*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1102*FLEN/8, x7, x1, x2) + +inst_578: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x03e and fs2 == 0 and fe2 == 0x0c and fm2 == 0x03e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x303e; op2val:0x303e; + valaddr_reg:x3; val_offset:1104*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1104*FLEN/8, x7, x1, x2) + +inst_579: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x03e and fs2 == 0 and fe2 == 0x0c and fm2 == 0x03e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x303e; op2val:0x303e; + valaddr_reg:x3; val_offset:1106*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1106*FLEN/8, x7, x1, x2) + +inst_580: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x1da and fs2 == 0 and fe2 == 0x0a and fm2 == 0x1d9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x29da; op2val:0x29d9; + valaddr_reg:x3; val_offset:1108*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1108*FLEN/8, x7, x1, x2) + +inst_581: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x1da and fs2 == 0 and fe2 == 0x0a and fm2 == 0x1d9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x29da; op2val:0x29d9; + valaddr_reg:x3; val_offset:1110*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1110*FLEN/8, x7, x1, x2) + +inst_582: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x1da and fs2 == 0 and fe2 == 0x0a and fm2 == 0x1d9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x29da; op2val:0x29d9; + valaddr_reg:x3; val_offset:1112*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1112*FLEN/8, x7, x1, x2) + +inst_583: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x1da and fs2 == 0 and fe2 == 0x0a and fm2 == 0x1d9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x29da; op2val:0x29d9; + valaddr_reg:x3; val_offset:1114*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1114*FLEN/8, x7, x1, x2) + +inst_584: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x1da and fs2 == 0 and fe2 == 0x0a and fm2 == 0x1d9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x29da; op2val:0x29d9; + valaddr_reg:x3; val_offset:1116*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1116*FLEN/8, x7, x1, x2) + +inst_585: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ea and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ea and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aea; op2val:0x3aea; + valaddr_reg:x3; val_offset:1118*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1118*FLEN/8, x7, x1, x2) + +inst_586: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ea and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ea and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aea; op2val:0x3aea; + valaddr_reg:x3; val_offset:1120*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1120*FLEN/8, x7, x1, x2) + +inst_587: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ea and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ea and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aea; op2val:0x3aea; + valaddr_reg:x3; val_offset:1122*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1122*FLEN/8, x7, x1, x2) + +inst_588: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ea and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ea and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aea; op2val:0x3aea; + valaddr_reg:x3; val_offset:1124*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1124*FLEN/8, x7, x1, x2) + +inst_589: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ea and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ea and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aea; op2val:0x3aea; + valaddr_reg:x3; val_offset:1126*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1126*FLEN/8, x7, x1, x2) + +inst_590: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x36a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b6a; op2val:0x3b6a; + valaddr_reg:x3; val_offset:1128*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1128*FLEN/8, x7, x1, x2) + +inst_591: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x36a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b6a; op2val:0x3b6a; + valaddr_reg:x3; val_offset:1130*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1130*FLEN/8, x7, x1, x2) + +inst_592: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x36a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b6a; op2val:0x3b6a; + valaddr_reg:x3; val_offset:1132*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1132*FLEN/8, x7, x1, x2) + +inst_593: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x36a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b6a; op2val:0x3b6a; + valaddr_reg:x3; val_offset:1134*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1134*FLEN/8, x7, x1, x2) + +inst_594: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x36a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b6a; op2val:0x3b6a; + valaddr_reg:x3; val_offset:1136*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1136*FLEN/8, x7, x1, x2) + +inst_595: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2c8 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2c7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x32c8; op2val:0x32c7; + valaddr_reg:x3; val_offset:1138*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1138*FLEN/8, x7, x1, x2) + +inst_596: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2c8 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2c7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x32c8; op2val:0x32c7; + valaddr_reg:x3; val_offset:1140*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1140*FLEN/8, x7, x1, x2) + +inst_597: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2c8 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2c7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x32c8; op2val:0x32c7; + valaddr_reg:x3; val_offset:1142*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1142*FLEN/8, x7, x1, x2) + +inst_598: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2c8 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2c7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x32c8; op2val:0x32c7; + valaddr_reg:x3; val_offset:1144*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1144*FLEN/8, x7, x1, x2) + +inst_599: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2c8 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2c7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x32c8; op2val:0x32c7; + valaddr_reg:x3; val_offset:1146*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1146*FLEN/8, x7, x1, x2) + +inst_600: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x145 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x145 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3945; op2val:0x3945; + valaddr_reg:x3; val_offset:1148*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1148*FLEN/8, x7, x1, x2) + +inst_601: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x145 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x145 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3945; op2val:0x3945; + valaddr_reg:x3; val_offset:1150*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1150*FLEN/8, x7, x1, x2) + +inst_602: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x145 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x145 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3945; op2val:0x3945; + valaddr_reg:x3; val_offset:1152*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1152*FLEN/8, x7, x1, x2) + +inst_603: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x145 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x145 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3945; op2val:0x3945; + valaddr_reg:x3; val_offset:1154*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1154*FLEN/8, x7, x1, x2) + +inst_604: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x145 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x145 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3945; op2val:0x3945; + valaddr_reg:x3; val_offset:1156*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1156*FLEN/8, x7, x1, x2) + +inst_605: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2fa and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2fa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x32fa; op2val:0x32fa; + valaddr_reg:x3; val_offset:1158*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1158*FLEN/8, x7, x1, x2) + +inst_606: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2fa and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2fa and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x32fa; op2val:0x32fa; + valaddr_reg:x3; val_offset:1160*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1160*FLEN/8, x7, x1, x2) + +inst_607: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2fa and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2fa and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x32fa; op2val:0x32fa; + valaddr_reg:x3; val_offset:1162*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1162*FLEN/8, x7, x1, x2) + +inst_608: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2fa and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2fa and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x32fa; op2val:0x32fa; + valaddr_reg:x3; val_offset:1164*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1164*FLEN/8, x7, x1, x2) + +inst_609: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2fa and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2fa and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x32fa; op2val:0x32fa; + valaddr_reg:x3; val_offset:1166*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1166*FLEN/8, x7, x1, x2) + +inst_610: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2de and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2de and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x36de; op2val:0x36de; + valaddr_reg:x3; val_offset:1168*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1168*FLEN/8, x7, x1, x2) + +inst_611: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2de and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2de and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x36de; op2val:0x36de; + valaddr_reg:x3; val_offset:1170*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1170*FLEN/8, x7, x1, x2) + +inst_612: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2de and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2de and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x36de; op2val:0x36de; + valaddr_reg:x3; val_offset:1172*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1172*FLEN/8, x7, x1, x2) + +inst_613: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2de and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2de and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x36de; op2val:0x36de; + valaddr_reg:x3; val_offset:1174*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1174*FLEN/8, x7, x1, x2) + +inst_614: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2de and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2de and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x36de; op2val:0x36de; + valaddr_reg:x3; val_offset:1176*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1176*FLEN/8, x7, x1, x2) + +inst_615: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x358 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x358 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b58; op2val:0x3b58; + valaddr_reg:x3; val_offset:1178*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1178*FLEN/8, x7, x1, x2) + +inst_616: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x358 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x358 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b58; op2val:0x3b58; + valaddr_reg:x3; val_offset:1180*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1180*FLEN/8, x7, x1, x2) + +inst_617: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x358 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x358 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b58; op2val:0x3b58; + valaddr_reg:x3; val_offset:1182*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1182*FLEN/8, x7, x1, x2) + +inst_618: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x358 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x358 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b58; op2val:0x3b58; + valaddr_reg:x3; val_offset:1184*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1184*FLEN/8, x7, x1, x2) + +inst_619: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x358 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x358 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b58; op2val:0x3b58; + valaddr_reg:x3; val_offset:1186*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1186*FLEN/8, x7, x1, x2) + +inst_620: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2fe and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2fd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2efe; op2val:0x2efd; + valaddr_reg:x3; val_offset:1188*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1188*FLEN/8, x7, x1, x2) + +inst_621: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2fe and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2fd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2efe; op2val:0x2efd; + valaddr_reg:x3; val_offset:1190*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1190*FLEN/8, x7, x1, x2) + +inst_622: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2fe and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2fd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2efe; op2val:0x2efd; + valaddr_reg:x3; val_offset:1192*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1192*FLEN/8, x7, x1, x2) + +inst_623: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2fe and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2fd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2efe; op2val:0x2efd; + valaddr_reg:x3; val_offset:1194*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1194*FLEN/8, x7, x1, x2) + +inst_624: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2fe and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2fd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2efe; op2val:0x2efd; + valaddr_reg:x3; val_offset:1196*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1196*FLEN/8, x7, x1, x2) + +inst_625: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0cc and fs2 == 0 and fe2 == 0x0b and fm2 == 0x0cb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ccc; op2val:0x2ccb; + valaddr_reg:x3; val_offset:1198*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1198*FLEN/8, x7, x1, x2) + +inst_626: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0cc and fs2 == 0 and fe2 == 0x0b and fm2 == 0x0cb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ccc; op2val:0x2ccb; + valaddr_reg:x3; val_offset:1200*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1200*FLEN/8, x7, x1, x2) + +inst_627: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0cc and fs2 == 0 and fe2 == 0x0b and fm2 == 0x0cb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ccc; op2val:0x2ccb; + valaddr_reg:x3; val_offset:1202*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1202*FLEN/8, x7, x1, x2) + +inst_628: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0cc and fs2 == 0 and fe2 == 0x0b and fm2 == 0x0cb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ccc; op2val:0x2ccb; + valaddr_reg:x3; val_offset:1204*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1204*FLEN/8, x7, x1, x2) + +inst_629: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0cc and fs2 == 0 and fe2 == 0x0b and fm2 == 0x0cb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ccc; op2val:0x2ccb; + valaddr_reg:x3; val_offset:1206*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1206*FLEN/8, x7, x1, x2) + +inst_630: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1c8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1c8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39c8; op2val:0x39c8; + valaddr_reg:x3; val_offset:1208*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1208*FLEN/8, x7, x1, x2) + +inst_631: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1c8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1c8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39c8; op2val:0x39c8; + valaddr_reg:x3; val_offset:1210*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1210*FLEN/8, x7, x1, x2) + +inst_632: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1c8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1c8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39c8; op2val:0x39c8; + valaddr_reg:x3; val_offset:1212*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1212*FLEN/8, x7, x1, x2) + +inst_633: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1c8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1c8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39c8; op2val:0x39c8; + valaddr_reg:x3; val_offset:1214*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1214*FLEN/8, x7, x1, x2) + +inst_634: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1c8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1c8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39c8; op2val:0x39c8; + valaddr_reg:x3; val_offset:1216*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1216*FLEN/8, x7, x1, x2) + +inst_635: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x183 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x182 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3183; op2val:0x3182; + valaddr_reg:x3; val_offset:1218*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1218*FLEN/8, x7, x1, x2) + +inst_636: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x183 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x182 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3183; op2val:0x3182; + valaddr_reg:x3; val_offset:1220*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1220*FLEN/8, x7, x1, x2) + +inst_637: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x183 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x182 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3183; op2val:0x3182; + valaddr_reg:x3; val_offset:1222*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1222*FLEN/8, x7, x1, x2) + +inst_638: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x183 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x182 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3183; op2val:0x3182; + valaddr_reg:x3; val_offset:1224*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1224*FLEN/8, x7, x1, x2) + +inst_639: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x183 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x182 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3183; op2val:0x3182; + valaddr_reg:x3; val_offset:1226*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1226*FLEN/8, x7, x1, x2) + +inst_640: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x146 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x145 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3546; op2val:0x3545; + valaddr_reg:x3; val_offset:1228*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1228*FLEN/8, x7, x1, x2) + +inst_641: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x146 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x145 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3546; op2val:0x3545; + valaddr_reg:x3; val_offset:1230*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1230*FLEN/8, x7, x1, x2) + +inst_642: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x146 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x145 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3546; op2val:0x3545; + valaddr_reg:x3; val_offset:1232*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1232*FLEN/8, x7, x1, x2) + +inst_643: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x146 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x145 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3546; op2val:0x3545; + valaddr_reg:x3; val_offset:1234*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1234*FLEN/8, x7, x1, x2) + +inst_644: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x146 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x145 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3546; op2val:0x3545; + valaddr_reg:x3; val_offset:1236*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1236*FLEN/8, x7, x1, x2) + +inst_645: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x314 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x314 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b14; op2val:0x3b14; + valaddr_reg:x3; val_offset:1238*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1238*FLEN/8, x7, x1, x2) + +inst_646: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x314 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x314 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b14; op2val:0x3b14; + valaddr_reg:x3; val_offset:1240*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1240*FLEN/8, x7, x1, x2) + +inst_647: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x314 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x314 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b14; op2val:0x3b14; + valaddr_reg:x3; val_offset:1242*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1242*FLEN/8, x7, x1, x2) + +inst_648: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x314 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x314 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b14; op2val:0x3b14; + valaddr_reg:x3; val_offset:1244*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1244*FLEN/8, x7, x1, x2) + +inst_649: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x314 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x314 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b14; op2val:0x3b14; + valaddr_reg:x3; val_offset:1246*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1246*FLEN/8, x7, x1, x2) + +inst_650: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ae and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3ad and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bae; op2val:0x3bad; + valaddr_reg:x3; val_offset:1248*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1248*FLEN/8, x7, x1, x2) + +inst_651: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ae and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3ad and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bae; op2val:0x3bad; + valaddr_reg:x3; val_offset:1250*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1250*FLEN/8, x7, x1, x2) + +inst_652: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ae and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3ad and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bae; op2val:0x3bad; + valaddr_reg:x3; val_offset:1252*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1252*FLEN/8, x7, x1, x2) + +inst_653: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ae and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3ad and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bae; op2val:0x3bad; + valaddr_reg:x3; val_offset:1254*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1254*FLEN/8, x7, x1, x2) + +inst_654: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ae and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3ad and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bae; op2val:0x3bad; + valaddr_reg:x3; val_offset:1256*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1256*FLEN/8, x7, x1, x2) + +inst_655: +// fs1 == 0 and fe1 == 0x08 and fm1 == 0x218 and fs2 == 0 and fe2 == 0x08 and fm2 == 0x20f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2218; op2val:0x220f; + valaddr_reg:x3; val_offset:1258*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1258*FLEN/8, x7, x1, x2) + +inst_656: +// fs1 == 0 and fe1 == 0x08 and fm1 == 0x218 and fs2 == 0 and fe2 == 0x08 and fm2 == 0x20f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2218; op2val:0x220f; + valaddr_reg:x3; val_offset:1260*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1260*FLEN/8, x7, x1, x2) + +inst_657: +// fs1 == 0 and fe1 == 0x08 and fm1 == 0x218 and fs2 == 0 and fe2 == 0x08 and fm2 == 0x20f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2218; op2val:0x220f; + valaddr_reg:x3; val_offset:1262*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1262*FLEN/8, x7, x1, x2) + +inst_658: +// fs1 == 0 and fe1 == 0x08 and fm1 == 0x218 and fs2 == 0 and fe2 == 0x08 and fm2 == 0x20f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2218; op2val:0x220f; + valaddr_reg:x3; val_offset:1264*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1264*FLEN/8, x7, x1, x2) + +inst_659: +// fs1 == 0 and fe1 == 0x08 and fm1 == 0x218 and fs2 == 0 and fe2 == 0x08 and fm2 == 0x20f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2218; op2val:0x220f; + valaddr_reg:x3; val_offset:1266*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1266*FLEN/8, x7, x1, x2) + +inst_660: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x313 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x313 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b13; op2val:0x3b13; + valaddr_reg:x3; val_offset:1268*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1268*FLEN/8, x7, x1, x2) + +inst_661: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x313 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x313 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b13; op2val:0x3b13; + valaddr_reg:x3; val_offset:1270*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1270*FLEN/8, x7, x1, x2) + +inst_662: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x313 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x313 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b13; op2val:0x3b13; + valaddr_reg:x3; val_offset:1272*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1272*FLEN/8, x7, x1, x2) + +inst_663: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x313 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x313 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b13; op2val:0x3b13; + valaddr_reg:x3; val_offset:1274*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1274*FLEN/8, x7, x1, x2) + +inst_664: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x313 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x313 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b13; op2val:0x3b13; + valaddr_reg:x3; val_offset:1276*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1276*FLEN/8, x7, x1, x2) + +inst_665: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x211 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x211 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a11; op2val:0x3a11; + valaddr_reg:x3; val_offset:1278*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1278*FLEN/8, x7, x1, x2) + +inst_666: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x211 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x211 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a11; op2val:0x3a11; + valaddr_reg:x3; val_offset:1280*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1280*FLEN/8, x7, x1, x2) + +inst_667: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x211 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x211 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a11; op2val:0x3a11; + valaddr_reg:x3; val_offset:1282*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1282*FLEN/8, x7, x1, x2) + +inst_668: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x211 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x211 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a11; op2val:0x3a11; + valaddr_reg:x3; val_offset:1284*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1284*FLEN/8, x7, x1, x2) + +inst_669: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x211 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x211 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a11; op2val:0x3a11; + valaddr_reg:x3; val_offset:1286*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1286*FLEN/8, x7, x1, x2) + +inst_670: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x32d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x32d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b2d; op2val:0x3b2d; + valaddr_reg:x3; val_offset:1288*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1288*FLEN/8, x7, x1, x2) + +inst_671: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x32d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x32d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b2d; op2val:0x3b2d; + valaddr_reg:x3; val_offset:1290*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1290*FLEN/8, x7, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_5) + +inst_672: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x32d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x32d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b2d; op2val:0x3b2d; + valaddr_reg:x3; val_offset:1292*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1292*FLEN/8, x7, x1, x2) + +inst_673: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x32d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x32d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b2d; op2val:0x3b2d; + valaddr_reg:x3; val_offset:1294*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1294*FLEN/8, x7, x1, x2) + +inst_674: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x32d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x32d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b2d; op2val:0x3b2d; + valaddr_reg:x3; val_offset:1296*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1296*FLEN/8, x7, x1, x2) + +inst_675: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1d0 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x1cf and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2dd0; op2val:0x2dcf; + valaddr_reg:x3; val_offset:1298*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1298*FLEN/8, x7, x1, x2) + +inst_676: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1d0 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x1cf and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2dd0; op2val:0x2dcf; + valaddr_reg:x3; val_offset:1300*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1300*FLEN/8, x7, x1, x2) + +inst_677: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1d0 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x1cf and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2dd0; op2val:0x2dcf; + valaddr_reg:x3; val_offset:1302*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1302*FLEN/8, x7, x1, x2) + +inst_678: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1d0 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x1cf and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2dd0; op2val:0x2dcf; + valaddr_reg:x3; val_offset:1304*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1304*FLEN/8, x7, x1, x2) + +inst_679: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1d0 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x1cf and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2dd0; op2val:0x2dcf; + valaddr_reg:x3; val_offset:1306*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1306*FLEN/8, x7, x1, x2) + +inst_680: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1f9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1f8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39f9; op2val:0x39f8; + valaddr_reg:x3; val_offset:1308*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1308*FLEN/8, x7, x1, x2) + +inst_681: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1f9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1f8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39f9; op2val:0x39f8; + valaddr_reg:x3; val_offset:1310*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1310*FLEN/8, x7, x1, x2) + +inst_682: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1f9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1f8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39f9; op2val:0x39f8; + valaddr_reg:x3; val_offset:1312*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1312*FLEN/8, x7, x1, x2) + +inst_683: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1f9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1f8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39f9; op2val:0x39f8; + valaddr_reg:x3; val_offset:1314*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1314*FLEN/8, x7, x1, x2) + +inst_684: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1f9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1f8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39f9; op2val:0x39f8; + valaddr_reg:x3; val_offset:1316*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1316*FLEN/8, x7, x1, x2) + +inst_685: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x332 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x332 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b32; op2val:0x3b32; + valaddr_reg:x3; val_offset:1318*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1318*FLEN/8, x7, x1, x2) + +inst_686: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x332 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x332 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b32; op2val:0x3b32; + valaddr_reg:x3; val_offset:1320*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1320*FLEN/8, x7, x1, x2) + +inst_687: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x332 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x332 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b32; op2val:0x3b32; + valaddr_reg:x3; val_offset:1322*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1322*FLEN/8, x7, x1, x2) + +inst_688: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x332 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x332 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b32; op2val:0x3b32; + valaddr_reg:x3; val_offset:1324*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1324*FLEN/8, x7, x1, x2) + +inst_689: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x332 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x332 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b32; op2val:0x3b32; + valaddr_reg:x3; val_offset:1326*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1326*FLEN/8, x7, x1, x2) + +inst_690: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ae and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3ae and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bae; op2val:0x3bae; + valaddr_reg:x3; val_offset:1328*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1328*FLEN/8, x7, x1, x2) + +inst_691: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ae and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3ae and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bae; op2val:0x3bae; + valaddr_reg:x3; val_offset:1330*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1330*FLEN/8, x7, x1, x2) + +inst_692: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ae and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3ae and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bae; op2val:0x3bae; + valaddr_reg:x3; val_offset:1332*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1332*FLEN/8, x7, x1, x2) + +inst_693: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ae and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3ae and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bae; op2val:0x3bae; + valaddr_reg:x3; val_offset:1334*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1334*FLEN/8, x7, x1, x2) + +inst_694: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ae and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3ae and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bae; op2val:0x3bae; + valaddr_reg:x3; val_offset:1336*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1336*FLEN/8, x7, x1, x2) + +inst_695: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x079 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x075 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2479; op2val:0x2475; + valaddr_reg:x3; val_offset:1338*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1338*FLEN/8, x7, x1, x2) + +inst_696: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x079 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x075 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2479; op2val:0x2475; + valaddr_reg:x3; val_offset:1340*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1340*FLEN/8, x7, x1, x2) + +inst_697: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x079 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x075 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2479; op2val:0x2475; + valaddr_reg:x3; val_offset:1342*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1342*FLEN/8, x7, x1, x2) + +inst_698: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x079 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x075 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2479; op2val:0x2475; + valaddr_reg:x3; val_offset:1344*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1344*FLEN/8, x7, x1, x2) + +inst_699: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x079 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x075 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2479; op2val:0x2475; + valaddr_reg:x3; val_offset:1346*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1346*FLEN/8, x7, x1, x2) + +inst_700: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x274 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x274 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3674; op2val:0x3674; + valaddr_reg:x3; val_offset:1348*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1348*FLEN/8, x7, x1, x2) + +inst_701: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x274 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x274 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3674; op2val:0x3674; + valaddr_reg:x3; val_offset:1350*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1350*FLEN/8, x7, x1, x2) + +inst_702: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x274 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x274 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3674; op2val:0x3674; + valaddr_reg:x3; val_offset:1352*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1352*FLEN/8, x7, x1, x2) + +inst_703: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x274 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x274 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3674; op2val:0x3674; + valaddr_reg:x3; val_offset:1354*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1354*FLEN/8, x7, x1, x2) + +inst_704: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x274 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x274 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3674; op2val:0x3674; + valaddr_reg:x3; val_offset:1356*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1356*FLEN/8, x7, x1, x2) + +inst_705: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x17e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x17e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x397e; op2val:0x397e; + valaddr_reg:x3; val_offset:1358*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1358*FLEN/8, x7, x1, x2) + +inst_706: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x17e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x17e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x397e; op2val:0x397e; + valaddr_reg:x3; val_offset:1360*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1360*FLEN/8, x7, x1, x2) + +inst_707: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x17e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x17e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x397e; op2val:0x397e; + valaddr_reg:x3; val_offset:1362*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1362*FLEN/8, x7, x1, x2) + +inst_708: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x17e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x17e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x397e; op2val:0x397e; + valaddr_reg:x3; val_offset:1364*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1364*FLEN/8, x7, x1, x2) + +inst_709: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x17e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x17e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x397e; op2val:0x397e; + valaddr_reg:x3; val_offset:1366*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1366*FLEN/8, x7, x1, x2) + +inst_710: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x18b and fs2 == 0 and fe2 == 0x0b and fm2 == 0x18a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d8b; op2val:0x2d8a; + valaddr_reg:x3; val_offset:1368*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1368*FLEN/8, x7, x1, x2) + +inst_711: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x18b and fs2 == 0 and fe2 == 0x0b and fm2 == 0x18a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d8b; op2val:0x2d8a; + valaddr_reg:x3; val_offset:1370*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1370*FLEN/8, x7, x1, x2) + +inst_712: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x18b and fs2 == 0 and fe2 == 0x0b and fm2 == 0x18a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d8b; op2val:0x2d8a; + valaddr_reg:x3; val_offset:1372*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1372*FLEN/8, x7, x1, x2) + +inst_713: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x18b and fs2 == 0 and fe2 == 0x0b and fm2 == 0x18a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d8b; op2val:0x2d8a; + valaddr_reg:x3; val_offset:1374*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1374*FLEN/8, x7, x1, x2) + +inst_714: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x18b and fs2 == 0 and fe2 == 0x0b and fm2 == 0x18a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d8b; op2val:0x2d8a; + valaddr_reg:x3; val_offset:1376*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1376*FLEN/8, x7, x1, x2) + +inst_715: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x3bf and fs2 == 0 and fe2 == 0x09 and fm2 == 0x3bb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x27bf; op2val:0x27bb; + valaddr_reg:x3; val_offset:1378*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1378*FLEN/8, x7, x1, x2) + +inst_716: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x3bf and fs2 == 0 and fe2 == 0x09 and fm2 == 0x3bb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x27bf; op2val:0x27bb; + valaddr_reg:x3; val_offset:1380*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1380*FLEN/8, x7, x1, x2) + +inst_717: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x3bf and fs2 == 0 and fe2 == 0x09 and fm2 == 0x3bb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x27bf; op2val:0x27bb; + valaddr_reg:x3; val_offset:1382*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1382*FLEN/8, x7, x1, x2) + +inst_718: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x3bf and fs2 == 0 and fe2 == 0x09 and fm2 == 0x3bb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x27bf; op2val:0x27bb; + valaddr_reg:x3; val_offset:1384*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1384*FLEN/8, x7, x1, x2) + +inst_719: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x3bf and fs2 == 0 and fe2 == 0x09 and fm2 == 0x3bb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x27bf; op2val:0x27bb; + valaddr_reg:x3; val_offset:1386*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1386*FLEN/8, x7, x1, x2) + +inst_720: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x247 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x247 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a47; op2val:0x3a47; + valaddr_reg:x3; val_offset:1388*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1388*FLEN/8, x7, x1, x2) + +inst_721: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x247 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x247 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a47; op2val:0x3a47; + valaddr_reg:x3; val_offset:1390*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1390*FLEN/8, x7, x1, x2) + +inst_722: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x247 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x247 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a47; op2val:0x3a47; + valaddr_reg:x3; val_offset:1392*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1392*FLEN/8, x7, x1, x2) + +inst_723: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x247 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x247 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a47; op2val:0x3a47; + valaddr_reg:x3; val_offset:1394*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1394*FLEN/8, x7, x1, x2) + +inst_724: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x247 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x247 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a47; op2val:0x3a47; + valaddr_reg:x3; val_offset:1396*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1396*FLEN/8, x7, x1, x2) + +inst_725: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x125 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x121 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2525; op2val:0x2521; + valaddr_reg:x3; val_offset:1398*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1398*FLEN/8, x7, x1, x2) + +inst_726: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x125 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x121 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2525; op2val:0x2521; + valaddr_reg:x3; val_offset:1400*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1400*FLEN/8, x7, x1, x2) + +inst_727: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x125 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x121 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2525; op2val:0x2521; + valaddr_reg:x3; val_offset:1402*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1402*FLEN/8, x7, x1, x2) + +inst_728: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x125 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x121 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2525; op2val:0x2521; + valaddr_reg:x3; val_offset:1404*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1404*FLEN/8, x7, x1, x2) + +inst_729: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x125 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x121 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2525; op2val:0x2521; + valaddr_reg:x3; val_offset:1406*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1406*FLEN/8, x7, x1, x2) + +inst_730: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0fd and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0fd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x34fd; op2val:0x34fd; + valaddr_reg:x3; val_offset:1408*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1408*FLEN/8, x7, x1, x2) + +inst_731: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0fd and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0fd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x34fd; op2val:0x34fd; + valaddr_reg:x3; val_offset:1410*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1410*FLEN/8, x7, x1, x2) + +inst_732: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0fd and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0fd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x34fd; op2val:0x34fd; + valaddr_reg:x3; val_offset:1412*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1412*FLEN/8, x7, x1, x2) + +inst_733: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0fd and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0fd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x34fd; op2val:0x34fd; + valaddr_reg:x3; val_offset:1414*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1414*FLEN/8, x7, x1, x2) + +inst_734: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0fd and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0fd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x34fd; op2val:0x34fd; + valaddr_reg:x3; val_offset:1416*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1416*FLEN/8, x7, x1, x2) + +inst_735: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ed and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1ed and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39ed; op2val:0x39ed; + valaddr_reg:x3; val_offset:1418*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1418*FLEN/8, x7, x1, x2) + +inst_736: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ed and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1ed and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39ed; op2val:0x39ed; + valaddr_reg:x3; val_offset:1420*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1420*FLEN/8, x7, x1, x2) + +inst_737: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ed and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1ed and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39ed; op2val:0x39ed; + valaddr_reg:x3; val_offset:1422*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1422*FLEN/8, x7, x1, x2) + +inst_738: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ed and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1ed and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39ed; op2val:0x39ed; + valaddr_reg:x3; val_offset:1424*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1424*FLEN/8, x7, x1, x2) + +inst_739: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ed and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1ed and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39ed; op2val:0x39ed; + valaddr_reg:x3; val_offset:1426*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1426*FLEN/8, x7, x1, x2) + +inst_740: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x18a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x18a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x398a; op2val:0x398a; + valaddr_reg:x3; val_offset:1428*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1428*FLEN/8, x7, x1, x2) + +inst_741: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x18a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x18a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x398a; op2val:0x398a; + valaddr_reg:x3; val_offset:1430*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1430*FLEN/8, x7, x1, x2) + +inst_742: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x18a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x18a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x398a; op2val:0x398a; + valaddr_reg:x3; val_offset:1432*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1432*FLEN/8, x7, x1, x2) + +inst_743: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x18a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x18a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x398a; op2val:0x398a; + valaddr_reg:x3; val_offset:1434*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1434*FLEN/8, x7, x1, x2) + +inst_744: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x18a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x18a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x398a; op2val:0x398a; + valaddr_reg:x3; val_offset:1436*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1436*FLEN/8, x7, x1, x2) + +inst_745: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x359 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x359 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b59; op2val:0x3b59; + valaddr_reg:x3; val_offset:1438*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1438*FLEN/8, x7, x1, x2) + +inst_746: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x359 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x359 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b59; op2val:0x3b59; + valaddr_reg:x3; val_offset:1440*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1440*FLEN/8, x7, x1, x2) + +inst_747: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x359 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x359 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b59; op2val:0x3b59; + valaddr_reg:x3; val_offset:1442*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1442*FLEN/8, x7, x1, x2) + +inst_748: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x359 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x359 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b59; op2val:0x3b59; + valaddr_reg:x3; val_offset:1444*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1444*FLEN/8, x7, x1, x2) + +inst_749: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x359 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x359 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b59; op2val:0x3b59; + valaddr_reg:x3; val_offset:1446*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1446*FLEN/8, x7, x1, x2) + +inst_750: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x045 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x041 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2445; op2val:0x2441; + valaddr_reg:x3; val_offset:1448*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1448*FLEN/8, x7, x1, x2) + +inst_751: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x045 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x041 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2445; op2val:0x2441; + valaddr_reg:x3; val_offset:1450*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1450*FLEN/8, x7, x1, x2) + +inst_752: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x045 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x041 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2445; op2val:0x2441; + valaddr_reg:x3; val_offset:1452*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1452*FLEN/8, x7, x1, x2) + +inst_753: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x045 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x041 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2445; op2val:0x2441; + valaddr_reg:x3; val_offset:1454*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1454*FLEN/8, x7, x1, x2) + +inst_754: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x045 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x041 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2445; op2val:0x2441; + valaddr_reg:x3; val_offset:1456*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1456*FLEN/8, x7, x1, x2) + +inst_755: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x191 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x191 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3591; op2val:0x3591; + valaddr_reg:x3; val_offset:1458*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1458*FLEN/8, x7, x1, x2) + +inst_756: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x191 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x191 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3591; op2val:0x3591; + valaddr_reg:x3; val_offset:1460*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1460*FLEN/8, x7, x1, x2) + +inst_757: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x191 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x191 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3591; op2val:0x3591; + valaddr_reg:x3; val_offset:1462*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1462*FLEN/8, x7, x1, x2) + +inst_758: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x191 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x191 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3591; op2val:0x3591; + valaddr_reg:x3; val_offset:1464*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1464*FLEN/8, x7, x1, x2) + +inst_759: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x191 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x191 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3591; op2val:0x3591; + valaddr_reg:x3; val_offset:1466*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1466*FLEN/8, x7, x1, x2) + +inst_760: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x397 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x395 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b97; op2val:0x2b95; + valaddr_reg:x3; val_offset:1468*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1468*FLEN/8, x7, x1, x2) + +inst_761: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x397 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x395 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b97; op2val:0x2b95; + valaddr_reg:x3; val_offset:1470*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1470*FLEN/8, x7, x1, x2) + +inst_762: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x397 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x395 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b97; op2val:0x2b95; + valaddr_reg:x3; val_offset:1472*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1472*FLEN/8, x7, x1, x2) + +inst_763: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x397 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x395 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b97; op2val:0x2b95; + valaddr_reg:x3; val_offset:1474*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1474*FLEN/8, x7, x1, x2) + +inst_764: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x397 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x395 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b97; op2val:0x2b95; + valaddr_reg:x3; val_offset:1476*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1476*FLEN/8, x7, x1, x2) + +inst_765: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x18b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x18b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x398b; op2val:0x398b; + valaddr_reg:x3; val_offset:1478*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1478*FLEN/8, x7, x1, x2) + +inst_766: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x18b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x18b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x398b; op2val:0x398b; + valaddr_reg:x3; val_offset:1480*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1480*FLEN/8, x7, x1, x2) + +inst_767: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x18b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x18b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x398b; op2val:0x398b; + valaddr_reg:x3; val_offset:1482*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1482*FLEN/8, x7, x1, x2) + +inst_768: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x18b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x18b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x398b; op2val:0x398b; + valaddr_reg:x3; val_offset:1484*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1484*FLEN/8, x7, x1, x2) + +inst_769: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x18b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x18b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x398b; op2val:0x398b; + valaddr_reg:x3; val_offset:1486*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1486*FLEN/8, x7, x1, x2) + +inst_770: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x177 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x177 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3977; op2val:0x3977; + valaddr_reg:x3; val_offset:1488*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1488*FLEN/8, x7, x1, x2) + +inst_771: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x177 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x177 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3977; op2val:0x3977; + valaddr_reg:x3; val_offset:1490*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1490*FLEN/8, x7, x1, x2) + +inst_772: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x177 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x177 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3977; op2val:0x3977; + valaddr_reg:x3; val_offset:1492*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1492*FLEN/8, x7, x1, x2) + +inst_773: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x177 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x177 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3977; op2val:0x3977; + valaddr_reg:x3; val_offset:1494*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1494*FLEN/8, x7, x1, x2) + +inst_774: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x177 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x177 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3977; op2val:0x3977; + valaddr_reg:x3; val_offset:1496*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1496*FLEN/8, x7, x1, x2) + +inst_775: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2d1 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2d0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ed1; op2val:0x2ed0; + valaddr_reg:x3; val_offset:1498*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1498*FLEN/8, x7, x1, x2) + +inst_776: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2d1 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2d0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ed1; op2val:0x2ed0; + valaddr_reg:x3; val_offset:1500*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1500*FLEN/8, x7, x1, x2) + +inst_777: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2d1 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2d0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ed1; op2val:0x2ed0; + valaddr_reg:x3; val_offset:1502*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1502*FLEN/8, x7, x1, x2) + +inst_778: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2d1 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2d0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ed1; op2val:0x2ed0; + valaddr_reg:x3; val_offset:1504*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1504*FLEN/8, x7, x1, x2) + +inst_779: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2d1 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2d0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ed1; op2val:0x2ed0; + valaddr_reg:x3; val_offset:1506*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1506*FLEN/8, x7, x1, x2) + +inst_780: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x153 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x153 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3953; op2val:0x3953; + valaddr_reg:x3; val_offset:1508*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1508*FLEN/8, x7, x1, x2) + +inst_781: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x153 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x153 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3953; op2val:0x3953; + valaddr_reg:x3; val_offset:1510*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1510*FLEN/8, x7, x1, x2) + +inst_782: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x153 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x153 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3953; op2val:0x3953; + valaddr_reg:x3; val_offset:1512*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1512*FLEN/8, x7, x1, x2) + +inst_783: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x153 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x153 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3953; op2val:0x3953; + valaddr_reg:x3; val_offset:1514*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1514*FLEN/8, x7, x1, x2) + +inst_784: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x153 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x153 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3953; op2val:0x3953; + valaddr_reg:x3; val_offset:1516*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1516*FLEN/8, x7, x1, x2) + +inst_785: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2bc and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2bc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x36bc; op2val:0x36bc; + valaddr_reg:x3; val_offset:1518*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1518*FLEN/8, x7, x1, x2) + +inst_786: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2bc and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2bc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x36bc; op2val:0x36bc; + valaddr_reg:x3; val_offset:1520*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1520*FLEN/8, x7, x1, x2) + +inst_787: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2bc and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2bc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x36bc; op2val:0x36bc; + valaddr_reg:x3; val_offset:1522*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1522*FLEN/8, x7, x1, x2) + +inst_788: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2bc and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2bc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x36bc; op2val:0x36bc; + valaddr_reg:x3; val_offset:1524*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1524*FLEN/8, x7, x1, x2) + +inst_789: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2bc and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2bc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x36bc; op2val:0x36bc; + valaddr_reg:x3; val_offset:1526*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1526*FLEN/8, x7, x1, x2) + +inst_790: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x20a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x209 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a0a; op2val:0x3a09; + valaddr_reg:x3; val_offset:1528*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1528*FLEN/8, x7, x1, x2) + +inst_791: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x20a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x209 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a0a; op2val:0x3a09; + valaddr_reg:x3; val_offset:1530*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1530*FLEN/8, x7, x1, x2) + +inst_792: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x20a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x209 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a0a; op2val:0x3a09; + valaddr_reg:x3; val_offset:1532*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1532*FLEN/8, x7, x1, x2) + +inst_793: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x20a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x209 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a0a; op2val:0x3a09; + valaddr_reg:x3; val_offset:1534*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1534*FLEN/8, x7, x1, x2) + +inst_794: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x20a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x209 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a0a; op2val:0x3a09; + valaddr_reg:x3; val_offset:1536*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1536*FLEN/8, x7, x1, x2) + +inst_795: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x20c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x20c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a0c; op2val:0x3a0c; + valaddr_reg:x3; val_offset:1538*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1538*FLEN/8, x7, x1, x2) + +inst_796: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x20c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x20c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a0c; op2val:0x3a0c; + valaddr_reg:x3; val_offset:1540*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1540*FLEN/8, x7, x1, x2) + +inst_797: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x20c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x20c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a0c; op2val:0x3a0c; + valaddr_reg:x3; val_offset:1542*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1542*FLEN/8, x7, x1, x2) + +inst_798: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x20c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x20c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a0c; op2val:0x3a0c; + valaddr_reg:x3; val_offset:1544*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1544*FLEN/8, x7, x1, x2) + +inst_799: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x20c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x20c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a0c; op2val:0x3a0c; + valaddr_reg:x3; val_offset:1546*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1546*FLEN/8, x7, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_6) + +inst_800: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x32e and fs2 == 0 and fe2 == 0x0d and fm2 == 0x32e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x372e; op2val:0x372e; + valaddr_reg:x3; val_offset:1548*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1548*FLEN/8, x7, x1, x2) + +inst_801: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x32e and fs2 == 0 and fe2 == 0x0d and fm2 == 0x32e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x372e; op2val:0x372e; + valaddr_reg:x3; val_offset:1550*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1550*FLEN/8, x7, x1, x2) + +inst_802: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x32e and fs2 == 0 and fe2 == 0x0d and fm2 == 0x32e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x372e; op2val:0x372e; + valaddr_reg:x3; val_offset:1552*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1552*FLEN/8, x7, x1, x2) + +inst_803: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x32e and fs2 == 0 and fe2 == 0x0d and fm2 == 0x32e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x372e; op2val:0x372e; + valaddr_reg:x3; val_offset:1554*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1554*FLEN/8, x7, x1, x2) + +inst_804: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x32e and fs2 == 0 and fe2 == 0x0d and fm2 == 0x32e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x372e; op2val:0x372e; + valaddr_reg:x3; val_offset:1556*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1556*FLEN/8, x7, x1, x2) + +inst_805: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x366 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x366 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b66; op2val:0x3b66; + valaddr_reg:x3; val_offset:1558*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1558*FLEN/8, x7, x1, x2) + +inst_806: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x366 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x366 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b66; op2val:0x3b66; + valaddr_reg:x3; val_offset:1560*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1560*FLEN/8, x7, x1, x2) + +inst_807: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x366 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x366 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b66; op2val:0x3b66; + valaddr_reg:x3; val_offset:1562*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1562*FLEN/8, x7, x1, x2) + +inst_808: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x366 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x366 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b66; op2val:0x3b66; + valaddr_reg:x3; val_offset:1564*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1564*FLEN/8, x7, x1, x2) + +inst_809: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x366 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x366 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b66; op2val:0x3b66; + valaddr_reg:x3; val_offset:1566*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1566*FLEN/8, x7, x1, x2) + +inst_810: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ac and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1ac and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39ac; op2val:0x39ac; + valaddr_reg:x3; val_offset:1568*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1568*FLEN/8, x7, x1, x2) + +inst_811: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ac and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1ac and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39ac; op2val:0x39ac; + valaddr_reg:x3; val_offset:1570*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1570*FLEN/8, x7, x1, x2) + +inst_812: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ac and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1ac and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39ac; op2val:0x39ac; + valaddr_reg:x3; val_offset:1572*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1572*FLEN/8, x7, x1, x2) + +inst_813: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ac and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1ac and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39ac; op2val:0x39ac; + valaddr_reg:x3; val_offset:1574*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1574*FLEN/8, x7, x1, x2) + +inst_814: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ac and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1ac and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39ac; op2val:0x39ac; + valaddr_reg:x3; val_offset:1576*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1576*FLEN/8, x7, x1, x2) + +inst_815: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x00d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x00d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x380d; op2val:0x380d; + valaddr_reg:x3; val_offset:1578*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1578*FLEN/8, x7, x1, x2) + +inst_816: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x00d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x00d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x380d; op2val:0x380d; + valaddr_reg:x3; val_offset:1580*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1580*FLEN/8, x7, x1, x2) + +inst_817: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x00d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x00d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x380d; op2val:0x380d; + valaddr_reg:x3; val_offset:1582*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1582*FLEN/8, x7, x1, x2) + +inst_818: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x00d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x00d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x380d; op2val:0x380d; + valaddr_reg:x3; val_offset:1584*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1584*FLEN/8, x7, x1, x2) + +inst_819: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x00d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x00d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x380d; op2val:0x380d; + valaddr_reg:x3; val_offset:1586*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1586*FLEN/8, x7, x1, x2) + +inst_820: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2c4 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2c4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ac4; op2val:0x3ac4; + valaddr_reg:x3; val_offset:1588*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1588*FLEN/8, x7, x1, x2) + +inst_821: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2c4 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2c4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ac4; op2val:0x3ac4; + valaddr_reg:x3; val_offset:1590*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1590*FLEN/8, x7, x1, x2) + +inst_822: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2c4 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2c4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ac4; op2val:0x3ac4; + valaddr_reg:x3; val_offset:1592*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1592*FLEN/8, x7, x1, x2) + +inst_823: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2c4 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2c4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ac4; op2val:0x3ac4; + valaddr_reg:x3; val_offset:1594*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1594*FLEN/8, x7, x1, x2) + +inst_824: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2c4 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2c4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ac4; op2val:0x3ac4; + valaddr_reg:x3; val_offset:1596*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1596*FLEN/8, x7, x1, x2) + +inst_825: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x28f and fs2 == 0 and fe2 == 0x0c and fm2 == 0x28f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x328f; op2val:0x328f; + valaddr_reg:x3; val_offset:1598*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1598*FLEN/8, x7, x1, x2) + +inst_826: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x28f and fs2 == 0 and fe2 == 0x0c and fm2 == 0x28f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x328f; op2val:0x328f; + valaddr_reg:x3; val_offset:1600*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1600*FLEN/8, x7, x1, x2) + +inst_827: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x28f and fs2 == 0 and fe2 == 0x0c and fm2 == 0x28f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x328f; op2val:0x328f; + valaddr_reg:x3; val_offset:1602*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1602*FLEN/8, x7, x1, x2) + +inst_828: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x28f and fs2 == 0 and fe2 == 0x0c and fm2 == 0x28f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x328f; op2val:0x328f; + valaddr_reg:x3; val_offset:1604*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1604*FLEN/8, x7, x1, x2) + +inst_829: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x28f and fs2 == 0 and fe2 == 0x0c and fm2 == 0x28f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x328f; op2val:0x328f; + valaddr_reg:x3; val_offset:1606*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1606*FLEN/8, x7, x1, x2) + +inst_830: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x281 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x27f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2a81; op2val:0x2a7f; + valaddr_reg:x3; val_offset:1608*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1608*FLEN/8, x7, x1, x2) + +inst_831: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x281 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x27f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2a81; op2val:0x2a7f; + valaddr_reg:x3; val_offset:1610*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1610*FLEN/8, x7, x1, x2) + +inst_832: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x281 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x27f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2a81; op2val:0x2a7f; + valaddr_reg:x3; val_offset:1612*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1612*FLEN/8, x7, x1, x2) + +inst_833: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x281 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x27f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2a81; op2val:0x2a7f; + valaddr_reg:x3; val_offset:1614*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1614*FLEN/8, x7, x1, x2) + +inst_834: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x281 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x27f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2a81; op2val:0x2a7f; + valaddr_reg:x3; val_offset:1616*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1616*FLEN/8, x7, x1, x2) + +inst_835: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x329 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x329 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3329; op2val:0x3329; + valaddr_reg:x3; val_offset:1618*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1618*FLEN/8, x7, x1, x2) + +inst_836: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x329 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x329 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3329; op2val:0x3329; + valaddr_reg:x3; val_offset:1620*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1620*FLEN/8, x7, x1, x2) + +inst_837: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x329 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x329 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3329; op2val:0x3329; + valaddr_reg:x3; val_offset:1622*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1622*FLEN/8, x7, x1, x2) + +inst_838: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x329 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x329 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3329; op2val:0x3329; + valaddr_reg:x3; val_offset:1624*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1624*FLEN/8, x7, x1, x2) + +inst_839: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x329 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x329 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3329; op2val:0x3329; + valaddr_reg:x3; val_offset:1626*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1626*FLEN/8, x7, x1, x2) + +inst_840: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1b6 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1b5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x31b6; op2val:0x31b5; + valaddr_reg:x3; val_offset:1628*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1628*FLEN/8, x7, x1, x2) + +inst_841: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1b6 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1b5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x31b6; op2val:0x31b5; + valaddr_reg:x3; val_offset:1630*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1630*FLEN/8, x7, x1, x2) + +inst_842: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1b6 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1b5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x31b6; op2val:0x31b5; + valaddr_reg:x3; val_offset:1632*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1632*FLEN/8, x7, x1, x2) + +inst_843: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1b6 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1b5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x31b6; op2val:0x31b5; + valaddr_reg:x3; val_offset:1634*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1634*FLEN/8, x7, x1, x2) + +inst_844: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1b6 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1b5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x31b6; op2val:0x31b5; + valaddr_reg:x3; val_offset:1636*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1636*FLEN/8, x7, x1, x2) + +inst_845: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x325 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x324 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b25; op2val:0x3b24; + valaddr_reg:x3; val_offset:1638*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1638*FLEN/8, x7, x1, x2) + +inst_846: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x325 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x324 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b25; op2val:0x3b24; + valaddr_reg:x3; val_offset:1640*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1640*FLEN/8, x7, x1, x2) + +inst_847: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x325 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x324 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b25; op2val:0x3b24; + valaddr_reg:x3; val_offset:1642*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1642*FLEN/8, x7, x1, x2) + +inst_848: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x325 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x324 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b25; op2val:0x3b24; + valaddr_reg:x3; val_offset:1644*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1644*FLEN/8, x7, x1, x2) + +inst_849: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x325 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x324 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b25; op2val:0x3b24; + valaddr_reg:x3; val_offset:1646*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1646*FLEN/8, x7, x1, x2) + +inst_850: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x12a and fs2 == 0 and fe2 == 0x0b and fm2 == 0x129 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d2a; op2val:0x2d29; + valaddr_reg:x3; val_offset:1648*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1648*FLEN/8, x7, x1, x2) + +inst_851: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x12a and fs2 == 0 and fe2 == 0x0b and fm2 == 0x129 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d2a; op2val:0x2d29; + valaddr_reg:x3; val_offset:1650*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1650*FLEN/8, x7, x1, x2) + +inst_852: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x12a and fs2 == 0 and fe2 == 0x0b and fm2 == 0x129 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d2a; op2val:0x2d29; + valaddr_reg:x3; val_offset:1652*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1652*FLEN/8, x7, x1, x2) + +inst_853: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x12a and fs2 == 0 and fe2 == 0x0b and fm2 == 0x129 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d2a; op2val:0x2d29; + valaddr_reg:x3; val_offset:1654*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1654*FLEN/8, x7, x1, x2) + +inst_854: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x12a and fs2 == 0 and fe2 == 0x0b and fm2 == 0x129 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d2a; op2val:0x2d29; + valaddr_reg:x3; val_offset:1656*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1656*FLEN/8, x7, x1, x2) + +inst_855: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2cd and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2cc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ecd; op2val:0x2ecc; + valaddr_reg:x3; val_offset:1658*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1658*FLEN/8, x7, x1, x2) + +inst_856: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2cd and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2cc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ecd; op2val:0x2ecc; + valaddr_reg:x3; val_offset:1660*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1660*FLEN/8, x7, x1, x2) + +inst_857: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2cd and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2cc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ecd; op2val:0x2ecc; + valaddr_reg:x3; val_offset:1662*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1662*FLEN/8, x7, x1, x2) + +inst_858: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2cd and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2cc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ecd; op2val:0x2ecc; + valaddr_reg:x3; val_offset:1664*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1664*FLEN/8, x7, x1, x2) + +inst_859: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2cd and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2cc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2ecd; op2val:0x2ecc; + valaddr_reg:x3; val_offset:1666*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1666*FLEN/8, x7, x1, x2) + +inst_860: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1bb and fs2 == 0 and fe2 == 0x0b and fm2 == 0x1ba and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2dbb; op2val:0x2dba; + valaddr_reg:x3; val_offset:1668*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1668*FLEN/8, x7, x1, x2) + +inst_861: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1bb and fs2 == 0 and fe2 == 0x0b and fm2 == 0x1ba and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2dbb; op2val:0x2dba; + valaddr_reg:x3; val_offset:1670*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1670*FLEN/8, x7, x1, x2) + +inst_862: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1bb and fs2 == 0 and fe2 == 0x0b and fm2 == 0x1ba and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2dbb; op2val:0x2dba; + valaddr_reg:x3; val_offset:1672*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1672*FLEN/8, x7, x1, x2) + +inst_863: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1bb and fs2 == 0 and fe2 == 0x0b and fm2 == 0x1ba and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2dbb; op2val:0x2dba; + valaddr_reg:x3; val_offset:1674*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1674*FLEN/8, x7, x1, x2) + +inst_864: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1bb and fs2 == 0 and fe2 == 0x0b and fm2 == 0x1ba and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2dbb; op2val:0x2dba; + valaddr_reg:x3; val_offset:1676*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1676*FLEN/8, x7, x1, x2) + +inst_865: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x178 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x178 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3978; op2val:0x3978; + valaddr_reg:x3; val_offset:1678*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1678*FLEN/8, x7, x1, x2) + +inst_866: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x178 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x178 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3978; op2val:0x3978; + valaddr_reg:x3; val_offset:1680*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1680*FLEN/8, x7, x1, x2) + +inst_867: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x178 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x178 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3978; op2val:0x3978; + valaddr_reg:x3; val_offset:1682*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1682*FLEN/8, x7, x1, x2) + +inst_868: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x178 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x178 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3978; op2val:0x3978; + valaddr_reg:x3; val_offset:1684*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1684*FLEN/8, x7, x1, x2) + +inst_869: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x178 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x178 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3978; op2val:0x3978; + valaddr_reg:x3; val_offset:1686*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1686*FLEN/8, x7, x1, x2) + +inst_870: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x247 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x246 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3247; op2val:0x3246; + valaddr_reg:x3; val_offset:1688*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1688*FLEN/8, x7, x1, x2) + +inst_871: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x247 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x246 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3247; op2val:0x3246; + valaddr_reg:x3; val_offset:1690*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1690*FLEN/8, x7, x1, x2) + +inst_872: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x247 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x246 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3247; op2val:0x3246; + valaddr_reg:x3; val_offset:1692*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1692*FLEN/8, x7, x1, x2) + +inst_873: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x247 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x246 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3247; op2val:0x3246; + valaddr_reg:x3; val_offset:1694*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1694*FLEN/8, x7, x1, x2) + +inst_874: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x247 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x246 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3247; op2val:0x3246; + valaddr_reg:x3; val_offset:1696*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1696*FLEN/8, x7, x1, x2) + +inst_875: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x119 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x118 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3119; op2val:0x3118; + valaddr_reg:x3; val_offset:1698*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1698*FLEN/8, x7, x1, x2) + +inst_876: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x119 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x118 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3119; op2val:0x3118; + valaddr_reg:x3; val_offset:1700*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1700*FLEN/8, x7, x1, x2) + +inst_877: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x119 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x118 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3119; op2val:0x3118; + valaddr_reg:x3; val_offset:1702*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1702*FLEN/8, x7, x1, x2) + +inst_878: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x119 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x118 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3119; op2val:0x3118; + valaddr_reg:x3; val_offset:1704*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1704*FLEN/8, x7, x1, x2) + +inst_879: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x119 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x118 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3119; op2val:0x3118; + valaddr_reg:x3; val_offset:1706*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1706*FLEN/8, x7, x1, x2) + +inst_880: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0f7 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0f7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x34f7; op2val:0x34f7; + valaddr_reg:x3; val_offset:1708*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1708*FLEN/8, x7, x1, x2) + +inst_881: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0f7 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0f7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x34f7; op2val:0x34f7; + valaddr_reg:x3; val_offset:1710*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1710*FLEN/8, x7, x1, x2) + +inst_882: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0f7 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0f7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x34f7; op2val:0x34f7; + valaddr_reg:x3; val_offset:1712*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1712*FLEN/8, x7, x1, x2) + +inst_883: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0f7 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0f7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x34f7; op2val:0x34f7; + valaddr_reg:x3; val_offset:1714*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1714*FLEN/8, x7, x1, x2) + +inst_884: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0f7 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0f7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x34f7; op2val:0x34f7; + valaddr_reg:x3; val_offset:1716*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1716*FLEN/8, x7, x1, x2) + +inst_885: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x08a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x089 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x388a; op2val:0x3889; + valaddr_reg:x3; val_offset:1718*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1718*FLEN/8, x7, x1, x2) + +inst_886: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x08a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x089 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x388a; op2val:0x3889; + valaddr_reg:x3; val_offset:1720*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1720*FLEN/8, x7, x1, x2) + +inst_887: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x08a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x089 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x388a; op2val:0x3889; + valaddr_reg:x3; val_offset:1722*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1722*FLEN/8, x7, x1, x2) + +inst_888: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x08a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x089 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x388a; op2val:0x3889; + valaddr_reg:x3; val_offset:1724*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1724*FLEN/8, x7, x1, x2) + +inst_889: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x08a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x089 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x388a; op2val:0x3889; + valaddr_reg:x3; val_offset:1726*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1726*FLEN/8, x7, x1, x2) + +inst_890: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x090 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x090 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3490; op2val:0x3490; + valaddr_reg:x3; val_offset:1728*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1728*FLEN/8, x7, x1, x2) + +inst_891: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x090 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x090 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3490; op2val:0x3490; + valaddr_reg:x3; val_offset:1730*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1730*FLEN/8, x7, x1, x2) + +inst_892: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x090 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x090 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3490; op2val:0x3490; + valaddr_reg:x3; val_offset:1732*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1732*FLEN/8, x7, x1, x2) + +inst_893: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x090 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x090 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3490; op2val:0x3490; + valaddr_reg:x3; val_offset:1734*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1734*FLEN/8, x7, x1, x2) + +inst_894: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x090 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x090 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3490; op2val:0x3490; + valaddr_reg:x3; val_offset:1736*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1736*FLEN/8, x7, x1, x2) + +inst_895: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fa and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1fa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39fa; op2val:0x39fa; + valaddr_reg:x3; val_offset:1738*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1738*FLEN/8, x7, x1, x2) + +inst_896: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fa and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1fa and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39fa; op2val:0x39fa; + valaddr_reg:x3; val_offset:1740*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1740*FLEN/8, x7, x1, x2) + +inst_897: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fa and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1fa and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39fa; op2val:0x39fa; + valaddr_reg:x3; val_offset:1742*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1742*FLEN/8, x7, x1, x2) + +inst_898: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fa and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1fa and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39fa; op2val:0x39fa; + valaddr_reg:x3; val_offset:1744*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1744*FLEN/8, x7, x1, x2) + +inst_899: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fa and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1fa and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39fa; op2val:0x39fa; + valaddr_reg:x3; val_offset:1746*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1746*FLEN/8, x7, x1, x2) + +inst_900: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x0b1 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x0af and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x28b1; op2val:0x28af; + valaddr_reg:x3; val_offset:1748*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1748*FLEN/8, x7, x1, x2) + +inst_901: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x0b1 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x0af and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x28b1; op2val:0x28af; + valaddr_reg:x3; val_offset:1750*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1750*FLEN/8, x7, x1, x2) + +inst_902: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x0b1 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x0af and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x28b1; op2val:0x28af; + valaddr_reg:x3; val_offset:1752*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1752*FLEN/8, x7, x1, x2) + +inst_903: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x0b1 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x0af and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x28b1; op2val:0x28af; + valaddr_reg:x3; val_offset:1754*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1754*FLEN/8, x7, x1, x2) + +inst_904: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x0b1 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x0af and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x28b1; op2val:0x28af; + valaddr_reg:x3; val_offset:1756*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1756*FLEN/8, x7, x1, x2) + +inst_905: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x336 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x336 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3736; op2val:0x3736; + valaddr_reg:x3; val_offset:1758*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1758*FLEN/8, x7, x1, x2) + +inst_906: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x336 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x336 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3736; op2val:0x3736; + valaddr_reg:x3; val_offset:1760*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1760*FLEN/8, x7, x1, x2) + +inst_907: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x336 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x336 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3736; op2val:0x3736; + valaddr_reg:x3; val_offset:1762*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1762*FLEN/8, x7, x1, x2) + +inst_908: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x336 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x336 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3736; op2val:0x3736; + valaddr_reg:x3; val_offset:1764*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1764*FLEN/8, x7, x1, x2) + +inst_909: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x336 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x336 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3736; op2val:0x3736; + valaddr_reg:x3; val_offset:1766*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1766*FLEN/8, x7, x1, x2) + +inst_910: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0c2 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0c2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x30c2; op2val:0x30c2; + valaddr_reg:x3; val_offset:1768*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1768*FLEN/8, x7, x1, x2) + +inst_911: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0c2 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0c2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x30c2; op2val:0x30c2; + valaddr_reg:x3; val_offset:1770*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1770*FLEN/8, x7, x1, x2) + +inst_912: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0c2 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0c2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x30c2; op2val:0x30c2; + valaddr_reg:x3; val_offset:1772*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1772*FLEN/8, x7, x1, x2) + +inst_913: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0c2 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0c2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x30c2; op2val:0x30c2; + valaddr_reg:x3; val_offset:1774*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1774*FLEN/8, x7, x1, x2) + +inst_914: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0c2 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0c2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x30c2; op2val:0x30c2; + valaddr_reg:x3; val_offset:1776*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1776*FLEN/8, x7, x1, x2) + +inst_915: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0d5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x38d5; op2val:0x38d5; + valaddr_reg:x3; val_offset:1778*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1778*FLEN/8, x7, x1, x2) + +inst_916: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0d5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x38d5; op2val:0x38d5; + valaddr_reg:x3; val_offset:1780*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1780*FLEN/8, x7, x1, x2) + +inst_917: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0d5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x38d5; op2val:0x38d5; + valaddr_reg:x3; val_offset:1782*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1782*FLEN/8, x7, x1, x2) + +inst_918: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0d5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x38d5; op2val:0x38d5; + valaddr_reg:x3; val_offset:1784*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1784*FLEN/8, x7, x1, x2) + +inst_919: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d5 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0d5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x38d5; op2val:0x38d5; + valaddr_reg:x3; val_offset:1786*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1786*FLEN/8, x7, x1, x2) + +inst_920: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ef and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1ef and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39ef; op2val:0x39ef; + valaddr_reg:x3; val_offset:1788*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1788*FLEN/8, x7, x1, x2) + +inst_921: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ef and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1ef and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39ef; op2val:0x39ef; + valaddr_reg:x3; val_offset:1790*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1790*FLEN/8, x7, x1, x2) + +inst_922: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ef and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1ef and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39ef; op2val:0x39ef; + valaddr_reg:x3; val_offset:1792*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1792*FLEN/8, x7, x1, x2) + +inst_923: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ef and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1ef and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39ef; op2val:0x39ef; + valaddr_reg:x3; val_offset:1794*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1794*FLEN/8, x7, x1, x2) + +inst_924: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ef and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1ef and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39ef; op2val:0x39ef; + valaddr_reg:x3; val_offset:1796*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1796*FLEN/8, x7, x1, x2) + +inst_925: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a8 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1a8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x35a8; op2val:0x35a8; + valaddr_reg:x3; val_offset:1798*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1798*FLEN/8, x7, x1, x2) + +inst_926: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a8 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1a8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x35a8; op2val:0x35a8; + valaddr_reg:x3; val_offset:1800*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1800*FLEN/8, x7, x1, x2) + +inst_927: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a8 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1a8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x35a8; op2val:0x35a8; + valaddr_reg:x3; val_offset:1802*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1802*FLEN/8, x7, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_7) + +inst_928: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a8 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1a8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x35a8; op2val:0x35a8; + valaddr_reg:x3; val_offset:1804*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1804*FLEN/8, x7, x1, x2) + +inst_929: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a8 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1a8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x35a8; op2val:0x35a8; + valaddr_reg:x3; val_offset:1806*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1806*FLEN/8, x7, x1, x2) + +inst_930: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x129 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x128 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3929; op2val:0x3928; + valaddr_reg:x3; val_offset:1808*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1808*FLEN/8, x7, x1, x2) + +inst_931: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x129 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x128 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3929; op2val:0x3928; + valaddr_reg:x3; val_offset:1810*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1810*FLEN/8, x7, x1, x2) + +inst_932: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x129 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x128 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3929; op2val:0x3928; + valaddr_reg:x3; val_offset:1812*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1812*FLEN/8, x7, x1, x2) + +inst_933: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x129 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x128 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3929; op2val:0x3928; + valaddr_reg:x3; val_offset:1814*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1814*FLEN/8, x7, x1, x2) + +inst_934: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x129 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x128 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3929; op2val:0x3928; + valaddr_reg:x3; val_offset:1816*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1816*FLEN/8, x7, x1, x2) + +inst_935: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ff and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aff; op2val:0x3aff; + valaddr_reg:x3; val_offset:1818*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1818*FLEN/8, x7, x1, x2) + +inst_936: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ff and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aff; op2val:0x3aff; + valaddr_reg:x3; val_offset:1820*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1820*FLEN/8, x7, x1, x2) + +inst_937: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ff and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aff; op2val:0x3aff; + valaddr_reg:x3; val_offset:1822*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1822*FLEN/8, x7, x1, x2) + +inst_938: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ff and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aff; op2val:0x3aff; + valaddr_reg:x3; val_offset:1824*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1824*FLEN/8, x7, x1, x2) + +inst_939: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ff and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aff; op2val:0x3aff; + valaddr_reg:x3; val_offset:1826*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1826*FLEN/8, x7, x1, x2) + +inst_940: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x179 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x179 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3179; op2val:0x3179; + valaddr_reg:x3; val_offset:1828*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1828*FLEN/8, x7, x1, x2) + +inst_941: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x179 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x179 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3179; op2val:0x3179; + valaddr_reg:x3; val_offset:1830*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1830*FLEN/8, x7, x1, x2) + +inst_942: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x179 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x179 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3179; op2val:0x3179; + valaddr_reg:x3; val_offset:1832*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1832*FLEN/8, x7, x1, x2) + +inst_943: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x179 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x179 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3179; op2val:0x3179; + valaddr_reg:x3; val_offset:1834*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1834*FLEN/8, x7, x1, x2) + +inst_944: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x179 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x179 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3179; op2val:0x3179; + valaddr_reg:x3; val_offset:1836*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1836*FLEN/8, x7, x1, x2) + +inst_945: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ca and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0ca and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x38ca; op2val:0x38ca; + valaddr_reg:x3; val_offset:1838*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1838*FLEN/8, x7, x1, x2) + +inst_946: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ca and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0ca and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x38ca; op2val:0x38ca; + valaddr_reg:x3; val_offset:1840*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1840*FLEN/8, x7, x1, x2) + +inst_947: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ca and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0ca and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x38ca; op2val:0x38ca; + valaddr_reg:x3; val_offset:1842*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1842*FLEN/8, x7, x1, x2) + +inst_948: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ca and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0ca and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x38ca; op2val:0x38ca; + valaddr_reg:x3; val_offset:1844*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1844*FLEN/8, x7, x1, x2) + +inst_949: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ca and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0ca and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x38ca; op2val:0x38ca; + valaddr_reg:x3; val_offset:1846*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1846*FLEN/8, x7, x1, x2) + +inst_950: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x221 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x221 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a21; op2val:0x3a21; + valaddr_reg:x3; val_offset:1848*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1848*FLEN/8, x7, x1, x2) + +inst_951: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x221 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x221 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a21; op2val:0x3a21; + valaddr_reg:x3; val_offset:1850*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1850*FLEN/8, x7, x1, x2) + +inst_952: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x221 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x221 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a21; op2val:0x3a21; + valaddr_reg:x3; val_offset:1852*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1852*FLEN/8, x7, x1, x2) + +inst_953: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x221 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x221 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a21; op2val:0x3a21; + valaddr_reg:x3; val_offset:1854*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1854*FLEN/8, x7, x1, x2) + +inst_954: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x221 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x221 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a21; op2val:0x3a21; + valaddr_reg:x3; val_offset:1856*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1856*FLEN/8, x7, x1, x2) + +inst_955: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x38a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x38a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x378a; op2val:0x378a; + valaddr_reg:x3; val_offset:1858*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1858*FLEN/8, x7, x1, x2) + +inst_956: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x38a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x38a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x378a; op2val:0x378a; + valaddr_reg:x3; val_offset:1860*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1860*FLEN/8, x7, x1, x2) + +inst_957: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x38a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x38a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x378a; op2val:0x378a; + valaddr_reg:x3; val_offset:1862*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1862*FLEN/8, x7, x1, x2) + +inst_958: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x38a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x38a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x378a; op2val:0x378a; + valaddr_reg:x3; val_offset:1864*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1864*FLEN/8, x7, x1, x2) + +inst_959: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x38a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x38a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x378a; op2val:0x378a; + valaddr_reg:x3; val_offset:1866*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1866*FLEN/8, x7, x1, x2) + +inst_960: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x19e and fs2 == 0 and fe2 == 0x0d and fm2 == 0x19e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x359e; op2val:0x359e; + valaddr_reg:x3; val_offset:1868*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1868*FLEN/8, x7, x1, x2) + +inst_961: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x19e and fs2 == 0 and fe2 == 0x0d and fm2 == 0x19e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x359e; op2val:0x359e; + valaddr_reg:x3; val_offset:1870*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1870*FLEN/8, x7, x1, x2) + +inst_962: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x19e and fs2 == 0 and fe2 == 0x0d and fm2 == 0x19e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x359e; op2val:0x359e; + valaddr_reg:x3; val_offset:1872*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1872*FLEN/8, x7, x1, x2) + +inst_963: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x19e and fs2 == 0 and fe2 == 0x0d and fm2 == 0x19e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x359e; op2val:0x359e; + valaddr_reg:x3; val_offset:1874*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1874*FLEN/8, x7, x1, x2) + +inst_964: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x19e and fs2 == 0 and fe2 == 0x0d and fm2 == 0x19e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x359e; op2val:0x359e; + valaddr_reg:x3; val_offset:1876*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1876*FLEN/8, x7, x1, x2) + +inst_965: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x104 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x103 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3504; op2val:0x3503; + valaddr_reg:x3; val_offset:1878*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1878*FLEN/8, x7, x1, x2) + +inst_966: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x104 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x103 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3504; op2val:0x3503; + valaddr_reg:x3; val_offset:1880*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1880*FLEN/8, x7, x1, x2) + +inst_967: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x104 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x103 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3504; op2val:0x3503; + valaddr_reg:x3; val_offset:1882*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1882*FLEN/8, x7, x1, x2) + +inst_968: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x104 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x103 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3504; op2val:0x3503; + valaddr_reg:x3; val_offset:1884*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1884*FLEN/8, x7, x1, x2) + +inst_969: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x104 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x103 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3504; op2val:0x3503; + valaddr_reg:x3; val_offset:1886*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1886*FLEN/8, x7, x1, x2) + +inst_970: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x217 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x217 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a17; op2val:0x3a17; + valaddr_reg:x3; val_offset:1888*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1888*FLEN/8, x7, x1, x2) + +inst_971: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x217 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x217 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a17; op2val:0x3a17; + valaddr_reg:x3; val_offset:1890*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1890*FLEN/8, x7, x1, x2) + +inst_972: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x217 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x217 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a17; op2val:0x3a17; + valaddr_reg:x3; val_offset:1892*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1892*FLEN/8, x7, x1, x2) + +inst_973: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x217 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x217 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a17; op2val:0x3a17; + valaddr_reg:x3; val_offset:1894*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1894*FLEN/8, x7, x1, x2) + +inst_974: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x217 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x217 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a17; op2val:0x3a17; + valaddr_reg:x3; val_offset:1896*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1896*FLEN/8, x7, x1, x2) + +inst_975: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x02b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x382b; op2val:0x382b; + valaddr_reg:x3; val_offset:1898*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1898*FLEN/8, x7, x1, x2) + +inst_976: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x02b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x382b; op2val:0x382b; + valaddr_reg:x3; val_offset:1900*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1900*FLEN/8, x7, x1, x2) + +inst_977: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x02b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x382b; op2val:0x382b; + valaddr_reg:x3; val_offset:1902*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1902*FLEN/8, x7, x1, x2) + +inst_978: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x02b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x382b; op2val:0x382b; + valaddr_reg:x3; val_offset:1904*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1904*FLEN/8, x7, x1, x2) + +inst_979: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x02b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x382b; op2val:0x382b; + valaddr_reg:x3; val_offset:1906*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1906*FLEN/8, x7, x1, x2) + +inst_980: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0b3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0b3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x38b3; op2val:0x38b3; + valaddr_reg:x3; val_offset:1908*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1908*FLEN/8, x7, x1, x2) + +inst_981: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0b3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0b3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x38b3; op2val:0x38b3; + valaddr_reg:x3; val_offset:1910*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1910*FLEN/8, x7, x1, x2) + +inst_982: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0b3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0b3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x38b3; op2val:0x38b3; + valaddr_reg:x3; val_offset:1912*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1912*FLEN/8, x7, x1, x2) + +inst_983: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0b3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0b3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x38b3; op2val:0x38b3; + valaddr_reg:x3; val_offset:1914*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1914*FLEN/8, x7, x1, x2) + +inst_984: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0b3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0b3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x38b3; op2val:0x38b3; + valaddr_reg:x3; val_offset:1916*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1916*FLEN/8, x7, x1, x2) + +inst_985: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1f5 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x1f4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2df5; op2val:0x2df4; + valaddr_reg:x3; val_offset:1918*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1918*FLEN/8, x7, x1, x2) + +inst_986: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1f5 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x1f4 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2df5; op2val:0x2df4; + valaddr_reg:x3; val_offset:1920*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1920*FLEN/8, x7, x1, x2) + +inst_987: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1f5 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x1f4 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2df5; op2val:0x2df4; + valaddr_reg:x3; val_offset:1922*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1922*FLEN/8, x7, x1, x2) + +inst_988: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1f5 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x1f4 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2df5; op2val:0x2df4; + valaddr_reg:x3; val_offset:1924*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1924*FLEN/8, x7, x1, x2) + +inst_989: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1f5 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x1f4 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2df5; op2val:0x2df4; + valaddr_reg:x3; val_offset:1926*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1926*FLEN/8, x7, x1, x2) + +inst_990: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1cc and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1cc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39cc; op2val:0x39cc; + valaddr_reg:x3; val_offset:1928*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1928*FLEN/8, x7, x1, x2) + +inst_991: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1cc and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1cc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39cc; op2val:0x39cc; + valaddr_reg:x3; val_offset:1930*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1930*FLEN/8, x7, x1, x2) + +inst_992: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1cc and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1cc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39cc; op2val:0x39cc; + valaddr_reg:x3; val_offset:1932*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1932*FLEN/8, x7, x1, x2) + +inst_993: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1cc and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1cc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39cc; op2val:0x39cc; + valaddr_reg:x3; val_offset:1934*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1934*FLEN/8, x7, x1, x2) + +inst_994: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1cc and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1cc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39cc; op2val:0x39cc; + valaddr_reg:x3; val_offset:1936*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1936*FLEN/8, x7, x1, x2) + +inst_995: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x39d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x39d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b9d; op2val:0x3b9d; + valaddr_reg:x3; val_offset:1938*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1938*FLEN/8, x7, x1, x2) + +inst_996: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x39d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x39d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b9d; op2val:0x3b9d; + valaddr_reg:x3; val_offset:1940*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1940*FLEN/8, x7, x1, x2) + +inst_997: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x39d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x39d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b9d; op2val:0x3b9d; + valaddr_reg:x3; val_offset:1942*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1942*FLEN/8, x7, x1, x2) + +inst_998: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x39d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x39d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b9d; op2val:0x3b9d; + valaddr_reg:x3; val_offset:1944*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1944*FLEN/8, x7, x1, x2) + +inst_999: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x39d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x39d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b9d; op2val:0x3b9d; + valaddr_reg:x3; val_offset:1946*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1946*FLEN/8, x7, x1, x2) + +inst_1000: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3d0 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3cf and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x37d0; op2val:0x37cf; + valaddr_reg:x3; val_offset:1948*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1948*FLEN/8, x7, x1, x2) + +inst_1001: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3d0 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3cf and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x37d0; op2val:0x37cf; + valaddr_reg:x3; val_offset:1950*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1950*FLEN/8, x7, x1, x2) + +inst_1002: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3d0 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3cf and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x37d0; op2val:0x37cf; + valaddr_reg:x3; val_offset:1952*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1952*FLEN/8, x7, x1, x2) + +inst_1003: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3d0 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3cf and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x37d0; op2val:0x37cf; + valaddr_reg:x3; val_offset:1954*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1954*FLEN/8, x7, x1, x2) + +inst_1004: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3d0 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3cf and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x37d0; op2val:0x37cf; + valaddr_reg:x3; val_offset:1956*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1956*FLEN/8, x7, x1, x2) + +inst_1005: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2b9 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ab9; op2val:0x3ab9; + valaddr_reg:x3; val_offset:1958*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1958*FLEN/8, x7, x1, x2) + +inst_1006: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2b9 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ab9; op2val:0x3ab9; + valaddr_reg:x3; val_offset:1960*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1960*FLEN/8, x7, x1, x2) + +inst_1007: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2b9 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ab9; op2val:0x3ab9; + valaddr_reg:x3; val_offset:1962*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1962*FLEN/8, x7, x1, x2) + +inst_1008: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2b9 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ab9; op2val:0x3ab9; + valaddr_reg:x3; val_offset:1964*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1964*FLEN/8, x7, x1, x2) + +inst_1009: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b9 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2b9 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ab9; op2val:0x3ab9; + valaddr_reg:x3; val_offset:1966*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1966*FLEN/8, x7, x1, x2) + +inst_1010: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x37d and fs2 == 0 and fe2 == 0x0b and fm2 == 0x37c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2f7d; op2val:0x2f7c; + valaddr_reg:x3; val_offset:1968*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1968*FLEN/8, x7, x1, x2) + +inst_1011: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x37d and fs2 == 0 and fe2 == 0x0b and fm2 == 0x37c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2f7d; op2val:0x2f7c; + valaddr_reg:x3; val_offset:1970*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1970*FLEN/8, x7, x1, x2) + +inst_1012: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x37d and fs2 == 0 and fe2 == 0x0b and fm2 == 0x37c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2f7d; op2val:0x2f7c; + valaddr_reg:x3; val_offset:1972*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1972*FLEN/8, x7, x1, x2) + +inst_1013: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x37d and fs2 == 0 and fe2 == 0x0b and fm2 == 0x37c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2f7d; op2val:0x2f7c; + valaddr_reg:x3; val_offset:1974*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1974*FLEN/8, x7, x1, x2) + +inst_1014: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x37d and fs2 == 0 and fe2 == 0x0b and fm2 == 0x37c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2f7d; op2val:0x2f7c; + valaddr_reg:x3; val_offset:1976*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1976*FLEN/8, x7, x1, x2) + +inst_1015: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0eb and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0eb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x34eb; op2val:0x34eb; + valaddr_reg:x3; val_offset:1978*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1978*FLEN/8, x7, x1, x2) + +inst_1016: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0eb and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0eb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x34eb; op2val:0x34eb; + valaddr_reg:x3; val_offset:1980*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1980*FLEN/8, x7, x1, x2) + +inst_1017: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0eb and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0eb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x34eb; op2val:0x34eb; + valaddr_reg:x3; val_offset:1982*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1982*FLEN/8, x7, x1, x2) + +inst_1018: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0eb and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0eb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x34eb; op2val:0x34eb; + valaddr_reg:x3; val_offset:1984*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1984*FLEN/8, x7, x1, x2) + +inst_1019: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0eb and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0eb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x34eb; op2val:0x34eb; + valaddr_reg:x3; val_offset:1986*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1986*FLEN/8, x7, x1, x2) + +inst_1020: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x106 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x106 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3906; op2val:0x3906; + valaddr_reg:x3; val_offset:1988*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1988*FLEN/8, x7, x1, x2) + +inst_1021: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x106 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x106 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3906; op2val:0x3906; + valaddr_reg:x3; val_offset:1990*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 1990*FLEN/8, x7, x1, x2) + +inst_1022: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x106 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x106 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3906; op2val:0x3906; + valaddr_reg:x3; val_offset:1992*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 1992*FLEN/8, x7, x1, x2) + +inst_1023: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x106 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x106 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3906; op2val:0x3906; + valaddr_reg:x3; val_offset:1994*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 1994*FLEN/8, x7, x1, x2) + +inst_1024: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x106 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x106 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3906; op2val:0x3906; + valaddr_reg:x3; val_offset:1996*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 1996*FLEN/8, x7, x1, x2) + +inst_1025: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x037 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x037 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3437; op2val:0x3437; + valaddr_reg:x3; val_offset:1998*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 1998*FLEN/8, x7, x1, x2) + +inst_1026: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x037 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x037 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3437; op2val:0x3437; + valaddr_reg:x3; val_offset:2000*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2000*FLEN/8, x7, x1, x2) + +inst_1027: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x037 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x037 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3437; op2val:0x3437; + valaddr_reg:x3; val_offset:2002*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2002*FLEN/8, x7, x1, x2) + +inst_1028: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x037 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x037 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3437; op2val:0x3437; + valaddr_reg:x3; val_offset:2004*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2004*FLEN/8, x7, x1, x2) + +inst_1029: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x037 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x037 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3437; op2val:0x3437; + valaddr_reg:x3; val_offset:2006*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2006*FLEN/8, x7, x1, x2) + +inst_1030: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x099 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x099 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3099; op2val:0x3099; + valaddr_reg:x3; val_offset:2008*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2008*FLEN/8, x7, x1, x2) + +inst_1031: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x099 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x099 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3099; op2val:0x3099; + valaddr_reg:x3; val_offset:2010*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2010*FLEN/8, x7, x1, x2) + +inst_1032: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x099 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x099 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3099; op2val:0x3099; + valaddr_reg:x3; val_offset:2012*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2012*FLEN/8, x7, x1, x2) + +inst_1033: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x099 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x099 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3099; op2val:0x3099; + valaddr_reg:x3; val_offset:2014*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2014*FLEN/8, x7, x1, x2) + +inst_1034: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x099 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x099 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3099; op2val:0x3099; + valaddr_reg:x3; val_offset:2016*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2016*FLEN/8, x7, x1, x2) + +inst_1035: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x11e and fs2 == 0 and fe2 == 0x0a and fm2 == 0x11c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x291e; op2val:0x291c; + valaddr_reg:x3; val_offset:2018*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2018*FLEN/8, x7, x1, x2) + +inst_1036: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x11e and fs2 == 0 and fe2 == 0x0a and fm2 == 0x11c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x291e; op2val:0x291c; + valaddr_reg:x3; val_offset:2020*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2020*FLEN/8, x7, x1, x2) + +inst_1037: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x11e and fs2 == 0 and fe2 == 0x0a and fm2 == 0x11c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x291e; op2val:0x291c; + valaddr_reg:x3; val_offset:2022*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2022*FLEN/8, x7, x1, x2) + +inst_1038: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x11e and fs2 == 0 and fe2 == 0x0a and fm2 == 0x11c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x291e; op2val:0x291c; + valaddr_reg:x3; val_offset:2024*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2024*FLEN/8, x7, x1, x2) + +inst_1039: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x11e and fs2 == 0 and fe2 == 0x0a and fm2 == 0x11c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x291e; op2val:0x291c; + valaddr_reg:x3; val_offset:2026*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2026*FLEN/8, x7, x1, x2) + +inst_1040: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x297 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x296 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a97; op2val:0x3a96; + valaddr_reg:x3; val_offset:2028*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2028*FLEN/8, x7, x1, x2) + +inst_1041: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x297 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x296 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a97; op2val:0x3a96; + valaddr_reg:x3; val_offset:2030*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2030*FLEN/8, x7, x1, x2) + +inst_1042: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x297 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x296 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a97; op2val:0x3a96; + valaddr_reg:x3; val_offset:2032*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2032*FLEN/8, x7, x1, x2) + +inst_1043: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x297 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x296 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a97; op2val:0x3a96; + valaddr_reg:x3; val_offset:2034*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2034*FLEN/8, x7, x1, x2) + +inst_1044: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x297 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x296 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a97; op2val:0x3a96; + valaddr_reg:x3; val_offset:2036*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2036*FLEN/8, x7, x1, x2) + +inst_1045: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x242 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x242 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a42; op2val:0x3a42; + valaddr_reg:x3; val_offset:2038*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2038*FLEN/8, x7, x1, x2) + +inst_1046: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x242 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x242 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a42; op2val:0x3a42; + valaddr_reg:x3; val_offset:2040*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2040*FLEN/8, x7, x1, x2) + +inst_1047: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x242 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x242 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a42; op2val:0x3a42; + valaddr_reg:x3; val_offset:2042*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2042*FLEN/8, x7, x1, x2) + +inst_1048: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x242 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x242 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a42; op2val:0x3a42; + valaddr_reg:x3; val_offset:2044*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2044*FLEN/8, x7, x1, x2) + +inst_1049: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x242 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x242 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a42; op2val:0x3a42; + valaddr_reg:x3; val_offset:2046*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2046*FLEN/8, x7, x1, x2) + +inst_1050: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x33c0; op2val:0x33c0; + valaddr_reg:x3; val_offset:2048*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2048*FLEN/8, x7, x1, x2) + +inst_1051: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3c0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x33c0; op2val:0x33c0; + valaddr_reg:x3; val_offset:2050*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2050*FLEN/8, x7, x1, x2) + +inst_1052: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3c0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x33c0; op2val:0x33c0; + valaddr_reg:x3; val_offset:2052*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2052*FLEN/8, x7, x1, x2) + +inst_1053: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3c0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x33c0; op2val:0x33c0; + valaddr_reg:x3; val_offset:2054*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2054*FLEN/8, x7, x1, x2) + +inst_1054: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3c0 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3c0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x33c0; op2val:0x33c0; + valaddr_reg:x3; val_offset:2056*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2056*FLEN/8, x7, x1, x2) + +inst_1055: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x118 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x117 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3518; op2val:0x3517; + valaddr_reg:x3; val_offset:2058*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2058*FLEN/8, x7, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_8) + +inst_1056: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x118 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x117 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3518; op2val:0x3517; + valaddr_reg:x3; val_offset:2060*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2060*FLEN/8, x7, x1, x2) + +inst_1057: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x118 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x117 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3518; op2val:0x3517; + valaddr_reg:x3; val_offset:2062*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2062*FLEN/8, x7, x1, x2) + +inst_1058: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x118 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x117 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3518; op2val:0x3517; + valaddr_reg:x3; val_offset:2064*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2064*FLEN/8, x7, x1, x2) + +inst_1059: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x118 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x117 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3518; op2val:0x3517; + valaddr_reg:x3; val_offset:2066*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2066*FLEN/8, x7, x1, x2) + +inst_1060: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x137 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x137 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3937; op2val:0x3937; + valaddr_reg:x3; val_offset:2068*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2068*FLEN/8, x7, x1, x2) + +inst_1061: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x137 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x137 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3937; op2val:0x3937; + valaddr_reg:x3; val_offset:2070*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2070*FLEN/8, x7, x1, x2) + +inst_1062: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x137 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x137 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3937; op2val:0x3937; + valaddr_reg:x3; val_offset:2072*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2072*FLEN/8, x7, x1, x2) + +inst_1063: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x137 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x137 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3937; op2val:0x3937; + valaddr_reg:x3; val_offset:2074*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2074*FLEN/8, x7, x1, x2) + +inst_1064: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x137 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x137 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3937; op2val:0x3937; + valaddr_reg:x3; val_offset:2076*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2076*FLEN/8, x7, x1, x2) + +inst_1065: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ae and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aae; op2val:0x3aae; + valaddr_reg:x3; val_offset:2078*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2078*FLEN/8, x7, x1, x2) + +inst_1066: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ae and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aae; op2val:0x3aae; + valaddr_reg:x3; val_offset:2080*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2080*FLEN/8, x7, x1, x2) + +inst_1067: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ae and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aae; op2val:0x3aae; + valaddr_reg:x3; val_offset:2082*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2082*FLEN/8, x7, x1, x2) + +inst_1068: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ae and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aae; op2val:0x3aae; + valaddr_reg:x3; val_offset:2084*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2084*FLEN/8, x7, x1, x2) + +inst_1069: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ae and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aae; op2val:0x3aae; + valaddr_reg:x3; val_offset:2086*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2086*FLEN/8, x7, x1, x2) + +inst_1070: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ac and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3ac and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bac; op2val:0x3bac; + valaddr_reg:x3; val_offset:2088*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2088*FLEN/8, x7, x1, x2) + +inst_1071: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ac and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3ac and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bac; op2val:0x3bac; + valaddr_reg:x3; val_offset:2090*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2090*FLEN/8, x7, x1, x2) + +inst_1072: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ac and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3ac and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bac; op2val:0x3bac; + valaddr_reg:x3; val_offset:2092*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2092*FLEN/8, x7, x1, x2) + +inst_1073: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ac and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3ac and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bac; op2val:0x3bac; + valaddr_reg:x3; val_offset:2094*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2094*FLEN/8, x7, x1, x2) + +inst_1074: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ac and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3ac and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bac; op2val:0x3bac; + valaddr_reg:x3; val_offset:2096*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2096*FLEN/8, x7, x1, x2) + +inst_1075: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x225 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x225 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3225; op2val:0x3225; + valaddr_reg:x3; val_offset:2098*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2098*FLEN/8, x7, x1, x2) + +inst_1076: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x225 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x225 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3225; op2val:0x3225; + valaddr_reg:x3; val_offset:2100*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2100*FLEN/8, x7, x1, x2) + +inst_1077: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x225 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x225 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3225; op2val:0x3225; + valaddr_reg:x3; val_offset:2102*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2102*FLEN/8, x7, x1, x2) + +inst_1078: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x225 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x225 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3225; op2val:0x3225; + valaddr_reg:x3; val_offset:2104*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2104*FLEN/8, x7, x1, x2) + +inst_1079: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x225 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x225 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3225; op2val:0x3225; + valaddr_reg:x3; val_offset:2106*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2106*FLEN/8, x7, x1, x2) + +inst_1080: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1dc and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1db and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39dc; op2val:0x39db; + valaddr_reg:x3; val_offset:2108*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2108*FLEN/8, x7, x1, x2) + +inst_1081: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1dc and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1db and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39dc; op2val:0x39db; + valaddr_reg:x3; val_offset:2110*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2110*FLEN/8, x7, x1, x2) + +inst_1082: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1dc and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1db and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39dc; op2val:0x39db; + valaddr_reg:x3; val_offset:2112*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2112*FLEN/8, x7, x1, x2) + +inst_1083: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1dc and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1db and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39dc; op2val:0x39db; + valaddr_reg:x3; val_offset:2114*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2114*FLEN/8, x7, x1, x2) + +inst_1084: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1dc and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1db and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39dc; op2val:0x39db; + valaddr_reg:x3; val_offset:2116*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2116*FLEN/8, x7, x1, x2) + +inst_1085: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x133 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x131 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2933; op2val:0x2931; + valaddr_reg:x3; val_offset:2118*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2118*FLEN/8, x7, x1, x2) + +inst_1086: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x133 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x131 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2933; op2val:0x2931; + valaddr_reg:x3; val_offset:2120*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2120*FLEN/8, x7, x1, x2) + +inst_1087: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x133 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x131 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2933; op2val:0x2931; + valaddr_reg:x3; val_offset:2122*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2122*FLEN/8, x7, x1, x2) + +inst_1088: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x133 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x131 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2933; op2val:0x2931; + valaddr_reg:x3; val_offset:2124*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2124*FLEN/8, x7, x1, x2) + +inst_1089: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x133 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x131 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2933; op2val:0x2931; + valaddr_reg:x3; val_offset:2126*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2126*FLEN/8, x7, x1, x2) + +inst_1090: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x32d and fs2 == 0 and fe2 == 0x0c and fm2 == 0x32c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x332d; op2val:0x332c; + valaddr_reg:x3; val_offset:2128*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2128*FLEN/8, x7, x1, x2) + +inst_1091: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x32d and fs2 == 0 and fe2 == 0x0c and fm2 == 0x32c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x332d; op2val:0x332c; + valaddr_reg:x3; val_offset:2130*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2130*FLEN/8, x7, x1, x2) + +inst_1092: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x32d and fs2 == 0 and fe2 == 0x0c and fm2 == 0x32c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x332d; op2val:0x332c; + valaddr_reg:x3; val_offset:2132*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2132*FLEN/8, x7, x1, x2) + +inst_1093: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x32d and fs2 == 0 and fe2 == 0x0c and fm2 == 0x32c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x332d; op2val:0x332c; + valaddr_reg:x3; val_offset:2134*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2134*FLEN/8, x7, x1, x2) + +inst_1094: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x32d and fs2 == 0 and fe2 == 0x0c and fm2 == 0x32c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x332d; op2val:0x332c; + valaddr_reg:x3; val_offset:2136*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2136*FLEN/8, x7, x1, x2) + +inst_1095: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x171 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x171 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3571; op2val:0x3571; + valaddr_reg:x3; val_offset:2138*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2138*FLEN/8, x7, x1, x2) + +inst_1096: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x171 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x171 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3571; op2val:0x3571; + valaddr_reg:x3; val_offset:2140*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2140*FLEN/8, x7, x1, x2) + +inst_1097: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x171 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x171 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3571; op2val:0x3571; + valaddr_reg:x3; val_offset:2142*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2142*FLEN/8, x7, x1, x2) + +inst_1098: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x171 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x171 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3571; op2val:0x3571; + valaddr_reg:x3; val_offset:2144*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2144*FLEN/8, x7, x1, x2) + +inst_1099: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x171 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x171 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3571; op2val:0x3571; + valaddr_reg:x3; val_offset:2146*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2146*FLEN/8, x7, x1, x2) + +inst_1100: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x070 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x070 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3870; op2val:0x3870; + valaddr_reg:x3; val_offset:2148*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2148*FLEN/8, x7, x1, x2) + +inst_1101: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x070 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x070 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3870; op2val:0x3870; + valaddr_reg:x3; val_offset:2150*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2150*FLEN/8, x7, x1, x2) + +inst_1102: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x070 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x070 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3870; op2val:0x3870; + valaddr_reg:x3; val_offset:2152*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2152*FLEN/8, x7, x1, x2) + +inst_1103: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x070 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x070 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3870; op2val:0x3870; + valaddr_reg:x3; val_offset:2154*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2154*FLEN/8, x7, x1, x2) + +inst_1104: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x070 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x070 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3870; op2val:0x3870; + valaddr_reg:x3; val_offset:2156*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2156*FLEN/8, x7, x1, x2) + +inst_1105: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x363 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x35e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2763; op2val:0x275e; + valaddr_reg:x3; val_offset:2158*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2158*FLEN/8, x7, x1, x2) + +inst_1106: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x363 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x35e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2763; op2val:0x275e; + valaddr_reg:x3; val_offset:2160*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2160*FLEN/8, x7, x1, x2) + +inst_1107: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x363 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x35e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2763; op2val:0x275e; + valaddr_reg:x3; val_offset:2162*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2162*FLEN/8, x7, x1, x2) + +inst_1108: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x363 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x35e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2763; op2val:0x275e; + valaddr_reg:x3; val_offset:2164*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2164*FLEN/8, x7, x1, x2) + +inst_1109: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x363 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x35e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2763; op2val:0x275e; + valaddr_reg:x3; val_offset:2166*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2166*FLEN/8, x7, x1, x2) + +inst_1110: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x250 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x250 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3250; op2val:0x3250; + valaddr_reg:x3; val_offset:2168*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2168*FLEN/8, x7, x1, x2) + +inst_1111: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x250 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x250 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3250; op2val:0x3250; + valaddr_reg:x3; val_offset:2170*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2170*FLEN/8, x7, x1, x2) + +inst_1112: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x250 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x250 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3250; op2val:0x3250; + valaddr_reg:x3; val_offset:2172*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2172*FLEN/8, x7, x1, x2) + +inst_1113: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x250 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x250 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3250; op2val:0x3250; + valaddr_reg:x3; val_offset:2174*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2174*FLEN/8, x7, x1, x2) + +inst_1114: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x250 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x250 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3250; op2val:0x3250; + valaddr_reg:x3; val_offset:2176*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2176*FLEN/8, x7, x1, x2) + +inst_1115: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2fd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3afd; op2val:0x3afd; + valaddr_reg:x3; val_offset:2178*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2178*FLEN/8, x7, x1, x2) + +inst_1116: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2fd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3afd; op2val:0x3afd; + valaddr_reg:x3; val_offset:2180*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2180*FLEN/8, x7, x1, x2) + +inst_1117: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2fd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3afd; op2val:0x3afd; + valaddr_reg:x3; val_offset:2182*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2182*FLEN/8, x7, x1, x2) + +inst_1118: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2fd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3afd; op2val:0x3afd; + valaddr_reg:x3; val_offset:2184*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2184*FLEN/8, x7, x1, x2) + +inst_1119: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fd and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2fd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3afd; op2val:0x3afd; + valaddr_reg:x3; val_offset:2186*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2186*FLEN/8, x7, x1, x2) + +inst_1120: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x263 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x263 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3663; op2val:0x3663; + valaddr_reg:x3; val_offset:2188*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2188*FLEN/8, x7, x1, x2) + +inst_1121: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x263 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x263 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3663; op2val:0x3663; + valaddr_reg:x3; val_offset:2190*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2190*FLEN/8, x7, x1, x2) + +inst_1122: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x263 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x263 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3663; op2val:0x3663; + valaddr_reg:x3; val_offset:2192*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2192*FLEN/8, x7, x1, x2) + +inst_1123: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x263 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x263 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3663; op2val:0x3663; + valaddr_reg:x3; val_offset:2194*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2194*FLEN/8, x7, x1, x2) + +inst_1124: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x263 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x263 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3663; op2val:0x3663; + valaddr_reg:x3; val_offset:2196*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2196*FLEN/8, x7, x1, x2) + +inst_1125: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x30e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x30e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b0e; op2val:0x3b0e; + valaddr_reg:x3; val_offset:2198*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2198*FLEN/8, x7, x1, x2) + +inst_1126: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x30e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x30e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b0e; op2val:0x3b0e; + valaddr_reg:x3; val_offset:2200*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2200*FLEN/8, x7, x1, x2) + +inst_1127: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x30e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x30e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b0e; op2val:0x3b0e; + valaddr_reg:x3; val_offset:2202*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2202*FLEN/8, x7, x1, x2) + +inst_1128: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x30e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x30e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b0e; op2val:0x3b0e; + valaddr_reg:x3; val_offset:2204*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2204*FLEN/8, x7, x1, x2) + +inst_1129: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x30e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x30e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b0e; op2val:0x3b0e; + valaddr_reg:x3; val_offset:2206*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2206*FLEN/8, x7, x1, x2) + +inst_1130: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x203 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x203 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a03; op2val:0x3a03; + valaddr_reg:x3; val_offset:2208*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2208*FLEN/8, x7, x1, x2) + +inst_1131: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x203 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x203 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a03; op2val:0x3a03; + valaddr_reg:x3; val_offset:2210*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2210*FLEN/8, x7, x1, x2) + +inst_1132: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x203 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x203 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a03; op2val:0x3a03; + valaddr_reg:x3; val_offset:2212*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2212*FLEN/8, x7, x1, x2) + +inst_1133: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x203 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x203 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a03; op2val:0x3a03; + valaddr_reg:x3; val_offset:2214*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2214*FLEN/8, x7, x1, x2) + +inst_1134: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x203 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x203 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a03; op2val:0x3a03; + valaddr_reg:x3; val_offset:2216*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2216*FLEN/8, x7, x1, x2) + +inst_1135: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3f7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bf7; op2val:0x3bf7; + valaddr_reg:x3; val_offset:2218*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2218*FLEN/8, x7, x1, x2) + +inst_1136: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3f7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bf7; op2val:0x3bf7; + valaddr_reg:x3; val_offset:2220*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2220*FLEN/8, x7, x1, x2) + +inst_1137: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3f7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bf7; op2val:0x3bf7; + valaddr_reg:x3; val_offset:2222*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2222*FLEN/8, x7, x1, x2) + +inst_1138: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3f7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bf7; op2val:0x3bf7; + valaddr_reg:x3; val_offset:2224*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2224*FLEN/8, x7, x1, x2) + +inst_1139: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3f7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bf7; op2val:0x3bf7; + valaddr_reg:x3; val_offset:2226*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2226*FLEN/8, x7, x1, x2) + +inst_1140: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x07d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x07d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x387d; op2val:0x387d; + valaddr_reg:x3; val_offset:2228*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2228*FLEN/8, x7, x1, x2) + +inst_1141: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x07d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x07d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x387d; op2val:0x387d; + valaddr_reg:x3; val_offset:2230*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2230*FLEN/8, x7, x1, x2) + +inst_1142: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x07d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x07d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x387d; op2val:0x387d; + valaddr_reg:x3; val_offset:2232*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2232*FLEN/8, x7, x1, x2) + +inst_1143: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x07d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x07d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x387d; op2val:0x387d; + valaddr_reg:x3; val_offset:2234*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2234*FLEN/8, x7, x1, x2) + +inst_1144: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x07d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x07d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x387d; op2val:0x387d; + valaddr_reg:x3; val_offset:2236*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2236*FLEN/8, x7, x1, x2) + +inst_1145: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1f5 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1f5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x35f5; op2val:0x35f5; + valaddr_reg:x3; val_offset:2238*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2238*FLEN/8, x7, x1, x2) + +inst_1146: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1f5 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1f5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x35f5; op2val:0x35f5; + valaddr_reg:x3; val_offset:2240*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2240*FLEN/8, x7, x1, x2) + +inst_1147: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1f5 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1f5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x35f5; op2val:0x35f5; + valaddr_reg:x3; val_offset:2242*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2242*FLEN/8, x7, x1, x2) + +inst_1148: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1f5 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1f5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x35f5; op2val:0x35f5; + valaddr_reg:x3; val_offset:2244*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2244*FLEN/8, x7, x1, x2) + +inst_1149: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1f5 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1f5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x35f5; op2val:0x35f5; + valaddr_reg:x3; val_offset:2246*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2246*FLEN/8, x7, x1, x2) + +inst_1150: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x145 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x144 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3145; op2val:0x3144; + valaddr_reg:x3; val_offset:2248*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2248*FLEN/8, x7, x1, x2) + +inst_1151: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x145 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x144 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3145; op2val:0x3144; + valaddr_reg:x3; val_offset:2250*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2250*FLEN/8, x7, x1, x2) + +inst_1152: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x145 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x144 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3145; op2val:0x3144; + valaddr_reg:x3; val_offset:2252*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2252*FLEN/8, x7, x1, x2) + +inst_1153: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x145 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x144 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3145; op2val:0x3144; + valaddr_reg:x3; val_offset:2254*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2254*FLEN/8, x7, x1, x2) + +inst_1154: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x145 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x144 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3145; op2val:0x3144; + valaddr_reg:x3; val_offset:2256*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2256*FLEN/8, x7, x1, x2) + +inst_1155: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1b8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1b8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39b8; op2val:0x39b8; + valaddr_reg:x3; val_offset:2258*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2258*FLEN/8, x7, x1, x2) + +inst_1156: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1b8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1b8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39b8; op2val:0x39b8; + valaddr_reg:x3; val_offset:2260*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2260*FLEN/8, x7, x1, x2) + +inst_1157: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1b8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1b8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39b8; op2val:0x39b8; + valaddr_reg:x3; val_offset:2262*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2262*FLEN/8, x7, x1, x2) + +inst_1158: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1b8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1b8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39b8; op2val:0x39b8; + valaddr_reg:x3; val_offset:2264*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2264*FLEN/8, x7, x1, x2) + +inst_1159: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1b8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1b8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39b8; op2val:0x39b8; + valaddr_reg:x3; val_offset:2266*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2266*FLEN/8, x7, x1, x2) + +inst_1160: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1d0 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1d0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39d0; op2val:0x39d0; + valaddr_reg:x3; val_offset:2268*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2268*FLEN/8, x7, x1, x2) + +inst_1161: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1d0 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1d0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39d0; op2val:0x39d0; + valaddr_reg:x3; val_offset:2270*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2270*FLEN/8, x7, x1, x2) + +inst_1162: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1d0 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1d0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39d0; op2val:0x39d0; + valaddr_reg:x3; val_offset:2272*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2272*FLEN/8, x7, x1, x2) + +inst_1163: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1d0 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1d0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39d0; op2val:0x39d0; + valaddr_reg:x3; val_offset:2274*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2274*FLEN/8, x7, x1, x2) + +inst_1164: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1d0 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1d0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39d0; op2val:0x39d0; + valaddr_reg:x3; val_offset:2276*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2276*FLEN/8, x7, x1, x2) + +inst_1165: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fe and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39fe; op2val:0x39fe; + valaddr_reg:x3; val_offset:2278*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2278*FLEN/8, x7, x1, x2) + +inst_1166: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fe and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1fe and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39fe; op2val:0x39fe; + valaddr_reg:x3; val_offset:2280*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2280*FLEN/8, x7, x1, x2) + +inst_1167: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fe and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1fe and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39fe; op2val:0x39fe; + valaddr_reg:x3; val_offset:2282*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2282*FLEN/8, x7, x1, x2) + +inst_1168: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fe and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1fe and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39fe; op2val:0x39fe; + valaddr_reg:x3; val_offset:2284*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2284*FLEN/8, x7, x1, x2) + +inst_1169: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1fe and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1fe and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39fe; op2val:0x39fe; + valaddr_reg:x3; val_offset:2286*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2286*FLEN/8, x7, x1, x2) + +inst_1170: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2af and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2af and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x32af; op2val:0x32af; + valaddr_reg:x3; val_offset:2288*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2288*FLEN/8, x7, x1, x2) + +inst_1171: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2af and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2af and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x32af; op2val:0x32af; + valaddr_reg:x3; val_offset:2290*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2290*FLEN/8, x7, x1, x2) + +inst_1172: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2af and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2af and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x32af; op2val:0x32af; + valaddr_reg:x3; val_offset:2292*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2292*FLEN/8, x7, x1, x2) + +inst_1173: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2af and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2af and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x32af; op2val:0x32af; + valaddr_reg:x3; val_offset:2294*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2294*FLEN/8, x7, x1, x2) + +inst_1174: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2af and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2af and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x32af; op2val:0x32af; + valaddr_reg:x3; val_offset:2296*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2296*FLEN/8, x7, x1, x2) + +inst_1175: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x2c5 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x2c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x26c5; op2val:0x26c0; + valaddr_reg:x3; val_offset:2298*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2298*FLEN/8, x7, x1, x2) + +inst_1176: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x2c5 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x2c0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x26c5; op2val:0x26c0; + valaddr_reg:x3; val_offset:2300*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2300*FLEN/8, x7, x1, x2) + +inst_1177: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x2c5 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x2c0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x26c5; op2val:0x26c0; + valaddr_reg:x3; val_offset:2302*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2302*FLEN/8, x7, x1, x2) + +inst_1178: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x2c5 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x2c0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x26c5; op2val:0x26c0; + valaddr_reg:x3; val_offset:2304*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2304*FLEN/8, x7, x1, x2) + +inst_1179: +// fs1 == 0 and fe1 == 0x09 and fm1 == 0x2c5 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x2c0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x26c5; op2val:0x26c0; + valaddr_reg:x3; val_offset:2306*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2306*FLEN/8, x7, x1, x2) + +inst_1180: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x012 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x012 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3812; op2val:0x3812; + valaddr_reg:x3; val_offset:2308*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2308*FLEN/8, x7, x1, x2) + +inst_1181: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x012 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x012 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3812; op2val:0x3812; + valaddr_reg:x3; val_offset:2310*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2310*FLEN/8, x7, x1, x2) + +inst_1182: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x012 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x012 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3812; op2val:0x3812; + valaddr_reg:x3; val_offset:2312*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2312*FLEN/8, x7, x1, x2) + +inst_1183: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x012 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x012 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3812; op2val:0x3812; + valaddr_reg:x3; val_offset:2314*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2314*FLEN/8, x7, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_9) + +inst_1184: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x012 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x012 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3812; op2val:0x3812; + valaddr_reg:x3; val_offset:2316*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2316*FLEN/8, x7, x1, x2) + +inst_1185: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x364 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x363 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3364; op2val:0x3363; + valaddr_reg:x3; val_offset:2318*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2318*FLEN/8, x7, x1, x2) + +inst_1186: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x364 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x363 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3364; op2val:0x3363; + valaddr_reg:x3; val_offset:2320*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2320*FLEN/8, x7, x1, x2) + +inst_1187: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x364 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x363 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3364; op2val:0x3363; + valaddr_reg:x3; val_offset:2322*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2322*FLEN/8, x7, x1, x2) + +inst_1188: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x364 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x363 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3364; op2val:0x3363; + valaddr_reg:x3; val_offset:2324*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2324*FLEN/8, x7, x1, x2) + +inst_1189: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x364 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x363 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3364; op2val:0x3363; + valaddr_reg:x3; val_offset:2326*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2326*FLEN/8, x7, x1, x2) + +inst_1190: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ef and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0ef and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x38ef; op2val:0x38ef; + valaddr_reg:x3; val_offset:2328*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2328*FLEN/8, x7, x1, x2) + +inst_1191: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ef and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0ef and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x38ef; op2val:0x38ef; + valaddr_reg:x3; val_offset:2330*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2330*FLEN/8, x7, x1, x2) + +inst_1192: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ef and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0ef and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x38ef; op2val:0x38ef; + valaddr_reg:x3; val_offset:2332*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2332*FLEN/8, x7, x1, x2) + +inst_1193: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ef and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0ef and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x38ef; op2val:0x38ef; + valaddr_reg:x3; val_offset:2334*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2334*FLEN/8, x7, x1, x2) + +inst_1194: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ef and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0ef and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x38ef; op2val:0x38ef; + valaddr_reg:x3; val_offset:2336*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2336*FLEN/8, x7, x1, x2) + +inst_1195: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x322 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x322 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b22; op2val:0x3b22; + valaddr_reg:x3; val_offset:2338*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2338*FLEN/8, x7, x1, x2) + +inst_1196: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x322 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x322 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b22; op2val:0x3b22; + valaddr_reg:x3; val_offset:2340*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2340*FLEN/8, x7, x1, x2) + +inst_1197: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x322 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x322 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b22; op2val:0x3b22; + valaddr_reg:x3; val_offset:2342*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2342*FLEN/8, x7, x1, x2) + +inst_1198: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x322 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x322 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b22; op2val:0x3b22; + valaddr_reg:x3; val_offset:2344*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2344*FLEN/8, x7, x1, x2) + +inst_1199: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x322 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x322 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b22; op2val:0x3b22; + valaddr_reg:x3; val_offset:2346*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2346*FLEN/8, x7, x1, x2) + +inst_1200: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x346 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x346 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3746; op2val:0x3746; + valaddr_reg:x3; val_offset:2348*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2348*FLEN/8, x7, x1, x2) + +inst_1201: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x346 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x346 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3746; op2val:0x3746; + valaddr_reg:x3; val_offset:2350*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2350*FLEN/8, x7, x1, x2) + +inst_1202: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x346 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x346 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3746; op2val:0x3746; + valaddr_reg:x3; val_offset:2352*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2352*FLEN/8, x7, x1, x2) + +inst_1203: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x346 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x346 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3746; op2val:0x3746; + valaddr_reg:x3; val_offset:2354*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2354*FLEN/8, x7, x1, x2) + +inst_1204: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x346 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x346 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3746; op2val:0x3746; + valaddr_reg:x3; val_offset:2356*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2356*FLEN/8, x7, x1, x2) + +inst_1205: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3a5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x33a5; op2val:0x33a5; + valaddr_reg:x3; val_offset:2358*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2358*FLEN/8, x7, x1, x2) + +inst_1206: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3a5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x33a5; op2val:0x33a5; + valaddr_reg:x3; val_offset:2360*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2360*FLEN/8, x7, x1, x2) + +inst_1207: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3a5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x33a5; op2val:0x33a5; + valaddr_reg:x3; val_offset:2362*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2362*FLEN/8, x7, x1, x2) + +inst_1208: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3a5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x33a5; op2val:0x33a5; + valaddr_reg:x3; val_offset:2364*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2364*FLEN/8, x7, x1, x2) + +inst_1209: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3a5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x33a5; op2val:0x33a5; + valaddr_reg:x3; val_offset:2366*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2366*FLEN/8, x7, x1, x2) + +inst_1210: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2e8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2e8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ae8; op2val:0x3ae8; + valaddr_reg:x3; val_offset:2368*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2368*FLEN/8, x7, x1, x2) + +inst_1211: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2e8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2e8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ae8; op2val:0x3ae8; + valaddr_reg:x3; val_offset:2370*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2370*FLEN/8, x7, x1, x2) + +inst_1212: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2e8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2e8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ae8; op2val:0x3ae8; + valaddr_reg:x3; val_offset:2372*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2372*FLEN/8, x7, x1, x2) + +inst_1213: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2e8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2e8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ae8; op2val:0x3ae8; + valaddr_reg:x3; val_offset:2374*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2374*FLEN/8, x7, x1, x2) + +inst_1214: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2e8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2e8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ae8; op2val:0x3ae8; + valaddr_reg:x3; val_offset:2376*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2376*FLEN/8, x7, x1, x2) + +inst_1215: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2d6 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2d6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x36d6; op2val:0x36d6; + valaddr_reg:x3; val_offset:2378*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2378*FLEN/8, x7, x1, x2) + +inst_1216: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2d6 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2d6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x36d6; op2val:0x36d6; + valaddr_reg:x3; val_offset:2380*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2380*FLEN/8, x7, x1, x2) + +inst_1217: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2d6 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2d6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x36d6; op2val:0x36d6; + valaddr_reg:x3; val_offset:2382*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2382*FLEN/8, x7, x1, x2) + +inst_1218: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2d6 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2d6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x36d6; op2val:0x36d6; + valaddr_reg:x3; val_offset:2384*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2384*FLEN/8, x7, x1, x2) + +inst_1219: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2d6 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x2d6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x36d6; op2val:0x36d6; + valaddr_reg:x3; val_offset:2386*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2386*FLEN/8, x7, x1, x2) + +inst_1220: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3f3 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3f3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x37f3; op2val:0x37f3; + valaddr_reg:x3; val_offset:2388*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2388*FLEN/8, x7, x1, x2) + +inst_1221: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3f3 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3f3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x37f3; op2val:0x37f3; + valaddr_reg:x3; val_offset:2390*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2390*FLEN/8, x7, x1, x2) + +inst_1222: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3f3 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3f3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x37f3; op2val:0x37f3; + valaddr_reg:x3; val_offset:2392*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2392*FLEN/8, x7, x1, x2) + +inst_1223: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3f3 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3f3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x37f3; op2val:0x37f3; + valaddr_reg:x3; val_offset:2394*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2394*FLEN/8, x7, x1, x2) + +inst_1224: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3f3 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3f3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x37f3; op2val:0x37f3; + valaddr_reg:x3; val_offset:2396*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2396*FLEN/8, x7, x1, x2) + +inst_1225: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x38b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x38b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x378b; op2val:0x378b; + valaddr_reg:x3; val_offset:2398*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2398*FLEN/8, x7, x1, x2) + +inst_1226: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x38b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x38b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x378b; op2val:0x378b; + valaddr_reg:x3; val_offset:2400*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2400*FLEN/8, x7, x1, x2) + +inst_1227: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x38b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x38b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x378b; op2val:0x378b; + valaddr_reg:x3; val_offset:2402*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2402*FLEN/8, x7, x1, x2) + +inst_1228: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x38b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x38b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x378b; op2val:0x378b; + valaddr_reg:x3; val_offset:2404*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2404*FLEN/8, x7, x1, x2) + +inst_1229: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x38b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x38b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x378b; op2val:0x378b; + valaddr_reg:x3; val_offset:2406*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2406*FLEN/8, x7, x1, x2) + +inst_1230: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x337 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x064 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4f37; op2val:0xd064; + valaddr_reg:x3; val_offset:2408*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2408*FLEN/8, x7, x1, x2) + +inst_1231: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x337 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x064 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4f37; op2val:0xd064; + valaddr_reg:x3; val_offset:2410*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2410*FLEN/8, x7, x1, x2) + +inst_1232: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x337 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x064 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4f37; op2val:0xd064; + valaddr_reg:x3; val_offset:2412*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2412*FLEN/8, x7, x1, x2) + +inst_1233: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x337 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x064 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4f37; op2val:0xd064; + valaddr_reg:x3; val_offset:2414*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2414*FLEN/8, x7, x1, x2) + +inst_1234: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x337 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x064 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4f37; op2val:0xd064; + valaddr_reg:x3; val_offset:2416*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2416*FLEN/8, x7, x1, x2) + +inst_1235: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x10d and fs2 == 1 and fe2 == 0x14 and fm2 == 0x179 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4d0d; op2val:0xd179; + valaddr_reg:x3; val_offset:2418*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2418*FLEN/8, x7, x1, x2) + +inst_1236: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x10d and fs2 == 1 and fe2 == 0x14 and fm2 == 0x179 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4d0d; op2val:0xd179; + valaddr_reg:x3; val_offset:2420*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2420*FLEN/8, x7, x1, x2) + +inst_1237: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x10d and fs2 == 1 and fe2 == 0x14 and fm2 == 0x179 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4d0d; op2val:0xd179; + valaddr_reg:x3; val_offset:2422*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2422*FLEN/8, x7, x1, x2) + +inst_1238: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x10d and fs2 == 1 and fe2 == 0x14 and fm2 == 0x179 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4d0d; op2val:0xd179; + valaddr_reg:x3; val_offset:2424*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2424*FLEN/8, x7, x1, x2) + +inst_1239: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x10d and fs2 == 1 and fe2 == 0x14 and fm2 == 0x179 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4d0d; op2val:0xd179; + valaddr_reg:x3; val_offset:2426*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2426*FLEN/8, x7, x1, x2) + +inst_1240: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x24a and fs2 == 1 and fe2 == 0x12 and fm2 == 0x2d5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x524a; op2val:0xcad5; + valaddr_reg:x3; val_offset:2428*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2428*FLEN/8, x7, x1, x2) + +inst_1241: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x24a and fs2 == 1 and fe2 == 0x12 and fm2 == 0x2d5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x524a; op2val:0xcad5; + valaddr_reg:x3; val_offset:2430*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2430*FLEN/8, x7, x1, x2) + +inst_1242: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x24a and fs2 == 1 and fe2 == 0x12 and fm2 == 0x2d5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x524a; op2val:0xcad5; + valaddr_reg:x3; val_offset:2432*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2432*FLEN/8, x7, x1, x2) + +inst_1243: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x24a and fs2 == 1 and fe2 == 0x12 and fm2 == 0x2d5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x524a; op2val:0xcad5; + valaddr_reg:x3; val_offset:2434*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2434*FLEN/8, x7, x1, x2) + +inst_1244: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x24a and fs2 == 1 and fe2 == 0x12 and fm2 == 0x2d5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x524a; op2val:0xcad5; + valaddr_reg:x3; val_offset:2436*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2436*FLEN/8, x7, x1, x2) + +inst_1245: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5000; op2val:0xcfff; + valaddr_reg:x3; val_offset:2438*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2438*FLEN/8, x7, x1, x2) + +inst_1246: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5000; op2val:0xcfff; + valaddr_reg:x3; val_offset:2440*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2440*FLEN/8, x7, x1, x2) + +inst_1247: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5000; op2val:0xcfff; + valaddr_reg:x3; val_offset:2442*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2442*FLEN/8, x7, x1, x2) + +inst_1248: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5000; op2val:0xcfff; + valaddr_reg:x3; val_offset:2444*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2444*FLEN/8, x7, x1, x2) + +inst_1249: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5000; op2val:0xcfff; + valaddr_reg:x3; val_offset:2446*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2446*FLEN/8, x7, x1, x2) + +inst_1250: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x232 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x0e6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4e32; op2val:0xd0e6; + valaddr_reg:x3; val_offset:2448*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2448*FLEN/8, x7, x1, x2) + +inst_1251: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x232 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x0e6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4e32; op2val:0xd0e6; + valaddr_reg:x3; val_offset:2450*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2450*FLEN/8, x7, x1, x2) + +inst_1252: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x232 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x0e6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4e32; op2val:0xd0e6; + valaddr_reg:x3; val_offset:2452*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2452*FLEN/8, x7, x1, x2) + +inst_1253: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x232 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x0e6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4e32; op2val:0xd0e6; + valaddr_reg:x3; val_offset:2454*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2454*FLEN/8, x7, x1, x2) + +inst_1254: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x232 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x0e6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4e32; op2val:0xd0e6; + valaddr_reg:x3; val_offset:2456*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2456*FLEN/8, x7, x1, x2) + +inst_1255: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x0fa and fs2 == 1 and fe2 == 0x14 and fm2 == 0x3d8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3cfa; op2val:0xd3d8; + valaddr_reg:x3; val_offset:2458*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2458*FLEN/8, x7, x1, x2) + +inst_1256: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x0fa and fs2 == 1 and fe2 == 0x14 and fm2 == 0x3d8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3cfa; op2val:0xd3d8; + valaddr_reg:x3; val_offset:2460*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2460*FLEN/8, x7, x1, x2) + +inst_1257: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x0fa and fs2 == 1 and fe2 == 0x14 and fm2 == 0x3d8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3cfa; op2val:0xd3d8; + valaddr_reg:x3; val_offset:2462*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2462*FLEN/8, x7, x1, x2) + +inst_1258: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x0fa and fs2 == 1 and fe2 == 0x14 and fm2 == 0x3d8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3cfa; op2val:0xd3d8; + valaddr_reg:x3; val_offset:2464*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2464*FLEN/8, x7, x1, x2) + +inst_1259: +// fs1 == 0 and fe1 == 0x0f and fm1 == 0x0fa and fs2 == 1 and fe2 == 0x14 and fm2 == 0x3d8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3cfa; op2val:0xd3d8; + valaddr_reg:x3; val_offset:2466*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2466*FLEN/8, x7, x1, x2) + +inst_1260: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x0d6 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x254 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x50d6; op2val:0xce54; + valaddr_reg:x3; val_offset:2468*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2468*FLEN/8, x7, x1, x2) + +inst_1261: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x0d6 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x254 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x50d6; op2val:0xce54; + valaddr_reg:x3; val_offset:2470*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2470*FLEN/8, x7, x1, x2) + +inst_1262: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x0d6 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x254 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x50d6; op2val:0xce54; + valaddr_reg:x3; val_offset:2472*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2472*FLEN/8, x7, x1, x2) + +inst_1263: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x0d6 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x254 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x50d6; op2val:0xce54; + valaddr_reg:x3; val_offset:2474*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2474*FLEN/8, x7, x1, x2) + +inst_1264: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x0d6 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x254 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x50d6; op2val:0xce54; + valaddr_reg:x3; val_offset:2476*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2476*FLEN/8, x7, x1, x2) + +inst_1265: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2a8 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x15f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x52a8; op2val:0xc95f; + valaddr_reg:x3; val_offset:2478*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2478*FLEN/8, x7, x1, x2) + +inst_1266: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2a8 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x15f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x52a8; op2val:0xc95f; + valaddr_reg:x3; val_offset:2480*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2480*FLEN/8, x7, x1, x2) + +inst_1267: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2a8 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x15f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x52a8; op2val:0xc95f; + valaddr_reg:x3; val_offset:2482*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2482*FLEN/8, x7, x1, x2) + +inst_1268: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2a8 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x15f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x52a8; op2val:0xc95f; + valaddr_reg:x3; val_offset:2484*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2484*FLEN/8, x7, x1, x2) + +inst_1269: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2a8 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x15f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x52a8; op2val:0xc95f; + valaddr_reg:x3; val_offset:2486*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2486*FLEN/8, x7, x1, x2) + +inst_1270: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3e6 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x28b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x53e6; op2val:0xba8b; + valaddr_reg:x3; val_offset:2488*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2488*FLEN/8, x7, x1, x2) + +inst_1271: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3e6 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x28b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x53e6; op2val:0xba8b; + valaddr_reg:x3; val_offset:2490*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2490*FLEN/8, x7, x1, x2) + +inst_1272: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3e6 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x28b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x53e6; op2val:0xba8b; + valaddr_reg:x3; val_offset:2492*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2492*FLEN/8, x7, x1, x2) + +inst_1273: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3e6 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x28b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x53e6; op2val:0xba8b; + valaddr_reg:x3; val_offset:2494*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2494*FLEN/8, x7, x1, x2) + +inst_1274: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3e6 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x28b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x53e6; op2val:0xba8b; + valaddr_reg:x3; val_offset:2496*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2496*FLEN/8, x7, x1, x2) + +inst_1275: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2b2 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x136 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x52b2; op2val:0xc936; + valaddr_reg:x3; val_offset:2498*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2498*FLEN/8, x7, x1, x2) + +inst_1276: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2b2 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x136 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x52b2; op2val:0xc936; + valaddr_reg:x3; val_offset:2500*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2500*FLEN/8, x7, x1, x2) + +inst_1277: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2b2 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x136 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x52b2; op2val:0xc936; + valaddr_reg:x3; val_offset:2502*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2502*FLEN/8, x7, x1, x2) + +inst_1278: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2b2 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x136 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x52b2; op2val:0xc936; + valaddr_reg:x3; val_offset:2504*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2504*FLEN/8, x7, x1, x2) + +inst_1279: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2b2 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x136 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x52b2; op2val:0xc936; + valaddr_reg:x3; val_offset:2506*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2506*FLEN/8, x7, x1, x2) + +inst_1280: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1fd and fs2 == 1 and fe2 == 0x13 and fm2 == 0x005 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x51fd; op2val:0xcc05; + valaddr_reg:x3; val_offset:2508*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2508*FLEN/8, x7, x1, x2) + +inst_1281: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1fd and fs2 == 1 and fe2 == 0x13 and fm2 == 0x005 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x51fd; op2val:0xcc05; + valaddr_reg:x3; val_offset:2510*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2510*FLEN/8, x7, x1, x2) + +inst_1282: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1fd and fs2 == 1 and fe2 == 0x13 and fm2 == 0x005 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x51fd; op2val:0xcc05; + valaddr_reg:x3; val_offset:2512*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2512*FLEN/8, x7, x1, x2) + +inst_1283: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1fd and fs2 == 1 and fe2 == 0x13 and fm2 == 0x005 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x51fd; op2val:0xcc05; + valaddr_reg:x3; val_offset:2514*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2514*FLEN/8, x7, x1, x2) + +inst_1284: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1fd and fs2 == 1 and fe2 == 0x13 and fm2 == 0x005 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x51fd; op2val:0xcc05; + valaddr_reg:x3; val_offset:2516*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2516*FLEN/8, x7, x1, x2) + +inst_1285: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x10f and fs2 == 1 and fe2 == 0x14 and fm2 == 0x178 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4d0f; op2val:0xd178; + valaddr_reg:x3; val_offset:2518*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2518*FLEN/8, x7, x1, x2) + +inst_1286: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x10f and fs2 == 1 and fe2 == 0x14 and fm2 == 0x178 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4d0f; op2val:0xd178; + valaddr_reg:x3; val_offset:2520*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2520*FLEN/8, x7, x1, x2) + +inst_1287: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x10f and fs2 == 1 and fe2 == 0x14 and fm2 == 0x178 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4d0f; op2val:0xd178; + valaddr_reg:x3; val_offset:2522*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2522*FLEN/8, x7, x1, x2) + +inst_1288: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x10f and fs2 == 1 and fe2 == 0x14 and fm2 == 0x178 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4d0f; op2val:0xd178; + valaddr_reg:x3; val_offset:2524*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2524*FLEN/8, x7, x1, x2) + +inst_1289: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x10f and fs2 == 1 and fe2 == 0x14 and fm2 == 0x178 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4d0f; op2val:0xd178; + valaddr_reg:x3; val_offset:2526*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2526*FLEN/8, x7, x1, x2) + +inst_1290: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x102 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x1fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5102; op2val:0xcdfc; + valaddr_reg:x3; val_offset:2528*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2528*FLEN/8, x7, x1, x2) + +inst_1291: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x102 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x1fc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5102; op2val:0xcdfc; + valaddr_reg:x3; val_offset:2530*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2530*FLEN/8, x7, x1, x2) + +inst_1292: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x102 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x1fc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5102; op2val:0xcdfc; + valaddr_reg:x3; val_offset:2532*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2532*FLEN/8, x7, x1, x2) + +inst_1293: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x102 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x1fc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5102; op2val:0xcdfc; + valaddr_reg:x3; val_offset:2534*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2534*FLEN/8, x7, x1, x2) + +inst_1294: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x102 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x1fc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5102; op2val:0xcdfc; + valaddr_reg:x3; val_offset:2536*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2536*FLEN/8, x7, x1, x2) + +inst_1295: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x1e9 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x10b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4de9; op2val:0xd10b; + valaddr_reg:x3; val_offset:2538*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2538*FLEN/8, x7, x1, x2) + +inst_1296: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x1e9 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x10b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4de9; op2val:0xd10b; + valaddr_reg:x3; val_offset:2540*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2540*FLEN/8, x7, x1, x2) + +inst_1297: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x1e9 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x10b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4de9; op2val:0xd10b; + valaddr_reg:x3; val_offset:2542*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2542*FLEN/8, x7, x1, x2) + +inst_1298: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x1e9 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x10b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4de9; op2val:0xd10b; + valaddr_reg:x3; val_offset:2544*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2544*FLEN/8, x7, x1, x2) + +inst_1299: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x1e9 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x10b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4de9; op2val:0xd10b; + valaddr_reg:x3; val_offset:2546*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2546*FLEN/8, x7, x1, x2) + +inst_1300: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x261 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x0cf and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4e61; op2val:0xd0cf; + valaddr_reg:x3; val_offset:2548*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2548*FLEN/8, x7, x1, x2) + +inst_1301: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x261 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x0cf and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4e61; op2val:0xd0cf; + valaddr_reg:x3; val_offset:2550*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2550*FLEN/8, x7, x1, x2) + +inst_1302: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x261 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x0cf and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4e61; op2val:0xd0cf; + valaddr_reg:x3; val_offset:2552*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2552*FLEN/8, x7, x1, x2) + +inst_1303: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x261 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x0cf and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4e61; op2val:0xd0cf; + valaddr_reg:x3; val_offset:2554*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2554*FLEN/8, x7, x1, x2) + +inst_1304: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x261 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x0cf and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4e61; op2val:0xd0cf; + valaddr_reg:x3; val_offset:2556*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2556*FLEN/8, x7, x1, x2) + +inst_1305: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x2a2 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x0af and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4ea2; op2val:0xd0af; + valaddr_reg:x3; val_offset:2558*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2558*FLEN/8, x7, x1, x2) + +inst_1306: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x2a2 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x0af and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4ea2; op2val:0xd0af; + valaddr_reg:x3; val_offset:2560*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2560*FLEN/8, x7, x1, x2) + +inst_1307: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x2a2 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x0af and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4ea2; op2val:0xd0af; + valaddr_reg:x3; val_offset:2562*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2562*FLEN/8, x7, x1, x2) + +inst_1308: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x2a2 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x0af and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4ea2; op2val:0xd0af; + valaddr_reg:x3; val_offset:2564*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2564*FLEN/8, x7, x1, x2) + +inst_1309: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x2a2 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x0af and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4ea2; op2val:0xd0af; + valaddr_reg:x3; val_offset:2566*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2566*FLEN/8, x7, x1, x2) + +inst_1310: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x0ba and fs2 == 1 and fe2 == 0x13 and fm2 == 0x28b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x50ba; op2val:0xce8b; + valaddr_reg:x3; val_offset:2568*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2568*FLEN/8, x7, x1, x2) + +inst_1311: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x0ba and fs2 == 1 and fe2 == 0x13 and fm2 == 0x28b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x50ba; op2val:0xce8b; + valaddr_reg:x3; val_offset:2570*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2570*FLEN/8, x7, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_10) + +inst_1312: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x0ba and fs2 == 1 and fe2 == 0x13 and fm2 == 0x28b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x50ba; op2val:0xce8b; + valaddr_reg:x3; val_offset:2572*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2572*FLEN/8, x7, x1, x2) + +inst_1313: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x0ba and fs2 == 1 and fe2 == 0x13 and fm2 == 0x28b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x50ba; op2val:0xce8b; + valaddr_reg:x3; val_offset:2574*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2574*FLEN/8, x7, x1, x2) + +inst_1314: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x0ba and fs2 == 1 and fe2 == 0x13 and fm2 == 0x28b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x50ba; op2val:0xce8b; + valaddr_reg:x3; val_offset:2576*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2576*FLEN/8, x7, x1, x2) + +inst_1315: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x332 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x26e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5332; op2val:0xc66e; + valaddr_reg:x3; val_offset:2578*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2578*FLEN/8, x7, x1, x2) + +inst_1316: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x332 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x26e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5332; op2val:0xc66e; + valaddr_reg:x3; val_offset:2580*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2580*FLEN/8, x7, x1, x2) + +inst_1317: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x332 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x26e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5332; op2val:0xc66e; + valaddr_reg:x3; val_offset:2582*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2582*FLEN/8, x7, x1, x2) + +inst_1318: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x332 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x26e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5332; op2val:0xc66e; + valaddr_reg:x3; val_offset:2584*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2584*FLEN/8, x7, x1, x2) + +inst_1319: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x332 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x26e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5332; op2val:0xc66e; + valaddr_reg:x3; val_offset:2586*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2586*FLEN/8, x7, x1, x2) + +inst_1320: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x3fd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5001; op2val:0xcffd; + valaddr_reg:x3; val_offset:2588*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2588*FLEN/8, x7, x1, x2) + +inst_1321: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x3fd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5001; op2val:0xcffd; + valaddr_reg:x3; val_offset:2590*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2590*FLEN/8, x7, x1, x2) + +inst_1322: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x3fd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5001; op2val:0xcffd; + valaddr_reg:x3; val_offset:2592*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2592*FLEN/8, x7, x1, x2) + +inst_1323: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x3fd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5001; op2val:0xcffd; + valaddr_reg:x3; val_offset:2594*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2594*FLEN/8, x7, x1, x2) + +inst_1324: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x001 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x3fd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5001; op2val:0xcffd; + valaddr_reg:x3; val_offset:2596*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2596*FLEN/8, x7, x1, x2) + +inst_1325: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x12b and fs2 == 1 and fe2 == 0x13 and fm2 == 0x1aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x512b; op2val:0xcdaa; + valaddr_reg:x3; val_offset:2598*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2598*FLEN/8, x7, x1, x2) + +inst_1326: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x12b and fs2 == 1 and fe2 == 0x13 and fm2 == 0x1aa and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x512b; op2val:0xcdaa; + valaddr_reg:x3; val_offset:2600*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2600*FLEN/8, x7, x1, x2) + +inst_1327: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x12b and fs2 == 1 and fe2 == 0x13 and fm2 == 0x1aa and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x512b; op2val:0xcdaa; + valaddr_reg:x3; val_offset:2602*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2602*FLEN/8, x7, x1, x2) + +inst_1328: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x12b and fs2 == 1 and fe2 == 0x13 and fm2 == 0x1aa and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x512b; op2val:0xcdaa; + valaddr_reg:x3; val_offset:2604*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2604*FLEN/8, x7, x1, x2) + +inst_1329: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x12b and fs2 == 1 and fe2 == 0x13 and fm2 == 0x1aa and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x512b; op2val:0xcdaa; + valaddr_reg:x3; val_offset:2606*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2606*FLEN/8, x7, x1, x2) + +inst_1330: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x115 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x1d5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5115; op2val:0xcdd5; + valaddr_reg:x3; val_offset:2608*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2608*FLEN/8, x7, x1, x2) + +inst_1331: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x115 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x1d5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5115; op2val:0xcdd5; + valaddr_reg:x3; val_offset:2610*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2610*FLEN/8, x7, x1, x2) + +inst_1332: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x115 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x1d5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5115; op2val:0xcdd5; + valaddr_reg:x3; val_offset:2612*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2612*FLEN/8, x7, x1, x2) + +inst_1333: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x115 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x1d5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5115; op2val:0xcdd5; + valaddr_reg:x3; val_offset:2614*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2614*FLEN/8, x7, x1, x2) + +inst_1334: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x115 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x1d5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5115; op2val:0xcdd5; + valaddr_reg:x3; val_offset:2616*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2616*FLEN/8, x7, x1, x2) + +inst_1335: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x114 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x1d7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5114; op2val:0xcdd7; + valaddr_reg:x3; val_offset:2618*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2618*FLEN/8, x7, x1, x2) + +inst_1336: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x114 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x1d7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5114; op2val:0xcdd7; + valaddr_reg:x3; val_offset:2620*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2620*FLEN/8, x7, x1, x2) + +inst_1337: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x114 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x1d7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5114; op2val:0xcdd7; + valaddr_reg:x3; val_offset:2622*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2622*FLEN/8, x7, x1, x2) + +inst_1338: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x114 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x1d7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5114; op2val:0xcdd7; + valaddr_reg:x3; val_offset:2624*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2624*FLEN/8, x7, x1, x2) + +inst_1339: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x114 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x1d7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5114; op2val:0xcdd7; + valaddr_reg:x3; val_offset:2626*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2626*FLEN/8, x7, x1, x2) + +inst_1340: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x381 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3ec and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5381; op2val:0xc3ec; + valaddr_reg:x3; val_offset:2628*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2628*FLEN/8, x7, x1, x2) + +inst_1341: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x381 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3ec and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5381; op2val:0xc3ec; + valaddr_reg:x3; val_offset:2630*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2630*FLEN/8, x7, x1, x2) + +inst_1342: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x381 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3ec and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5381; op2val:0xc3ec; + valaddr_reg:x3; val_offset:2632*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2632*FLEN/8, x7, x1, x2) + +inst_1343: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x381 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3ec and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5381; op2val:0xc3ec; + valaddr_reg:x3; val_offset:2634*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2634*FLEN/8, x7, x1, x2) + +inst_1344: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x381 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3ec and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5381; op2val:0xc3ec; + valaddr_reg:x3; val_offset:2636*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2636*FLEN/8, x7, x1, x2) + +inst_1345: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2ca and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0d7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x52ca; op2val:0xc8d7; + valaddr_reg:x3; val_offset:2638*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2638*FLEN/8, x7, x1, x2) + +inst_1346: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2ca and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0d7 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x52ca; op2val:0xc8d7; + valaddr_reg:x3; val_offset:2640*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2640*FLEN/8, x7, x1, x2) + +inst_1347: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2ca and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0d7 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x52ca; op2val:0xc8d7; + valaddr_reg:x3; val_offset:2642*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2642*FLEN/8, x7, x1, x2) + +inst_1348: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2ca and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0d7 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x52ca; op2val:0xc8d7; + valaddr_reg:x3; val_offset:2644*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2644*FLEN/8, x7, x1, x2) + +inst_1349: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2ca and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0d7 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x52ca; op2val:0xc8d7; + valaddr_reg:x3; val_offset:2646*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2646*FLEN/8, x7, x1, x2) + +inst_1350: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x28c and fs2 == 1 and fe2 == 0x12 and fm2 == 0x1d1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x528c; op2val:0xc9d1; + valaddr_reg:x3; val_offset:2648*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2648*FLEN/8, x7, x1, x2) + +inst_1351: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x28c and fs2 == 1 and fe2 == 0x12 and fm2 == 0x1d1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x528c; op2val:0xc9d1; + valaddr_reg:x3; val_offset:2650*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2650*FLEN/8, x7, x1, x2) + +inst_1352: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x28c and fs2 == 1 and fe2 == 0x12 and fm2 == 0x1d1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x528c; op2val:0xc9d1; + valaddr_reg:x3; val_offset:2652*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2652*FLEN/8, x7, x1, x2) + +inst_1353: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x28c and fs2 == 1 and fe2 == 0x12 and fm2 == 0x1d1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x528c; op2val:0xc9d1; + valaddr_reg:x3; val_offset:2654*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2654*FLEN/8, x7, x1, x2) + +inst_1354: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x28c and fs2 == 1 and fe2 == 0x12 and fm2 == 0x1d1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x528c; op2val:0xc9d1; + valaddr_reg:x3; val_offset:2656*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2656*FLEN/8, x7, x1, x2) + +inst_1355: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x1c1 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x11f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4dc1; op2val:0xd11f; + valaddr_reg:x3; val_offset:2658*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2658*FLEN/8, x7, x1, x2) + +inst_1356: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x1c1 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x11f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4dc1; op2val:0xd11f; + valaddr_reg:x3; val_offset:2660*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2660*FLEN/8, x7, x1, x2) + +inst_1357: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x1c1 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x11f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4dc1; op2val:0xd11f; + valaddr_reg:x3; val_offset:2662*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2662*FLEN/8, x7, x1, x2) + +inst_1358: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x1c1 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x11f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4dc1; op2val:0xd11f; + valaddr_reg:x3; val_offset:2664*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2664*FLEN/8, x7, x1, x2) + +inst_1359: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x1c1 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x11f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4dc1; op2val:0xd11f; + valaddr_reg:x3; val_offset:2666*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2666*FLEN/8, x7, x1, x2) + +inst_1360: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1b3 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x099 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x51b3; op2val:0xcc99; + valaddr_reg:x3; val_offset:2668*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2668*FLEN/8, x7, x1, x2) + +inst_1361: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1b3 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x099 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x51b3; op2val:0xcc99; + valaddr_reg:x3; val_offset:2670*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2670*FLEN/8, x7, x1, x2) + +inst_1362: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1b3 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x099 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x51b3; op2val:0xcc99; + valaddr_reg:x3; val_offset:2672*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2672*FLEN/8, x7, x1, x2) + +inst_1363: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1b3 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x099 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x51b3; op2val:0xcc99; + valaddr_reg:x3; val_offset:2674*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2674*FLEN/8, x7, x1, x2) + +inst_1364: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1b3 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x099 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x51b3; op2val:0xcc99; + valaddr_reg:x3; val_offset:2676*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2676*FLEN/8, x7, x1, x2) + +inst_1365: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x069 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x32e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5069; op2val:0xcf2e; + valaddr_reg:x3; val_offset:2678*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2678*FLEN/8, x7, x1, x2) + +inst_1366: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x069 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x32e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5069; op2val:0xcf2e; + valaddr_reg:x3; val_offset:2680*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2680*FLEN/8, x7, x1, x2) + +inst_1367: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x069 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x32e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5069; op2val:0xcf2e; + valaddr_reg:x3; val_offset:2682*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2682*FLEN/8, x7, x1, x2) + +inst_1368: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x069 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x32e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5069; op2val:0xcf2e; + valaddr_reg:x3; val_offset:2684*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2684*FLEN/8, x7, x1, x2) + +inst_1369: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x069 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x32e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5069; op2val:0xcf2e; + valaddr_reg:x3; val_offset:2686*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2686*FLEN/8, x7, x1, x2) + +inst_1370: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2af and fs2 == 1 and fe2 == 0x12 and fm2 == 0x142 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x52af; op2val:0xc942; + valaddr_reg:x3; val_offset:2688*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2688*FLEN/8, x7, x1, x2) + +inst_1371: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2af and fs2 == 1 and fe2 == 0x12 and fm2 == 0x142 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x52af; op2val:0xc942; + valaddr_reg:x3; val_offset:2690*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2690*FLEN/8, x7, x1, x2) + +inst_1372: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2af and fs2 == 1 and fe2 == 0x12 and fm2 == 0x142 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x52af; op2val:0xc942; + valaddr_reg:x3; val_offset:2692*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2692*FLEN/8, x7, x1, x2) + +inst_1373: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2af and fs2 == 1 and fe2 == 0x12 and fm2 == 0x142 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x52af; op2val:0xc942; + valaddr_reg:x3; val_offset:2694*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2694*FLEN/8, x7, x1, x2) + +inst_1374: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2af and fs2 == 1 and fe2 == 0x12 and fm2 == 0x142 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x52af; op2val:0xc942; + valaddr_reg:x3; val_offset:2696*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2696*FLEN/8, x7, x1, x2) + +inst_1375: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x39b and fs2 == 1 and fe2 == 0x14 and fm2 == 0x032 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4f9b; op2val:0xd032; + valaddr_reg:x3; val_offset:2698*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2698*FLEN/8, x7, x1, x2) + +inst_1376: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x39b and fs2 == 1 and fe2 == 0x14 and fm2 == 0x032 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4f9b; op2val:0xd032; + valaddr_reg:x3; val_offset:2700*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2700*FLEN/8, x7, x1, x2) + +inst_1377: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x39b and fs2 == 1 and fe2 == 0x14 and fm2 == 0x032 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4f9b; op2val:0xd032; + valaddr_reg:x3; val_offset:2702*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2702*FLEN/8, x7, x1, x2) + +inst_1378: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x39b and fs2 == 1 and fe2 == 0x14 and fm2 == 0x032 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4f9b; op2val:0xd032; + valaddr_reg:x3; val_offset:2704*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2704*FLEN/8, x7, x1, x2) + +inst_1379: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x39b and fs2 == 1 and fe2 == 0x14 and fm2 == 0x032 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4f9b; op2val:0xd032; + valaddr_reg:x3; val_offset:2706*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2706*FLEN/8, x7, x1, x2) + +inst_1380: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x024 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x3b6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5024; op2val:0xcfb6; + valaddr_reg:x3; val_offset:2708*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2708*FLEN/8, x7, x1, x2) + +inst_1381: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x024 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x3b6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5024; op2val:0xcfb6; + valaddr_reg:x3; val_offset:2710*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2710*FLEN/8, x7, x1, x2) + +inst_1382: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x024 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x3b6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5024; op2val:0xcfb6; + valaddr_reg:x3; val_offset:2712*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2712*FLEN/8, x7, x1, x2) + +inst_1383: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x024 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x3b6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5024; op2val:0xcfb6; + valaddr_reg:x3; val_offset:2714*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2714*FLEN/8, x7, x1, x2) + +inst_1384: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x024 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x3b6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5024; op2val:0xcfb6; + valaddr_reg:x3; val_offset:2716*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2716*FLEN/8, x7, x1, x2) + +inst_1385: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x2e8 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x08c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4ee8; op2val:0xd08c; + valaddr_reg:x3; val_offset:2718*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2718*FLEN/8, x7, x1, x2) + +inst_1386: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x2e8 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x08c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4ee8; op2val:0xd08c; + valaddr_reg:x3; val_offset:2720*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2720*FLEN/8, x7, x1, x2) + +inst_1387: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x2e8 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x08c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4ee8; op2val:0xd08c; + valaddr_reg:x3; val_offset:2722*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2722*FLEN/8, x7, x1, x2) + +inst_1388: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x2e8 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x08c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4ee8; op2val:0xd08c; + valaddr_reg:x3; val_offset:2724*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2724*FLEN/8, x7, x1, x2) + +inst_1389: +// fs1 == 0 and fe1 == 0x13 and fm1 == 0x2e8 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x08c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4ee8; op2val:0xd08c; + valaddr_reg:x3; val_offset:2726*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2726*FLEN/8, x7, x1, x2) + +inst_1390: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x14c and fs2 == 1 and fe2 == 0x13 and fm2 == 0x167 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x514c; op2val:0xcd67; + valaddr_reg:x3; val_offset:2728*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2728*FLEN/8, x7, x1, x2) + +inst_1391: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x14c and fs2 == 1 and fe2 == 0x13 and fm2 == 0x167 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x514c; op2val:0xcd67; + valaddr_reg:x3; val_offset:2730*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2730*FLEN/8, x7, x1, x2) + +inst_1392: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x14c and fs2 == 1 and fe2 == 0x13 and fm2 == 0x167 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x514c; op2val:0xcd67; + valaddr_reg:x3; val_offset:2732*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2732*FLEN/8, x7, x1, x2) + +inst_1393: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x14c and fs2 == 1 and fe2 == 0x13 and fm2 == 0x167 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x514c; op2val:0xcd67; + valaddr_reg:x3; val_offset:2734*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2734*FLEN/8, x7, x1, x2) + +inst_1394: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x14c and fs2 == 1 and fe2 == 0x13 and fm2 == 0x167 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x514c; op2val:0xcd67; + valaddr_reg:x3; val_offset:2736*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2736*FLEN/8, x7, x1, x2) + +inst_1395: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x01e and fs2 == 1 and fe2 == 0x13 and fm2 == 0x3c3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x501e; op2val:0xcfc3; + valaddr_reg:x3; val_offset:2738*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2738*FLEN/8, x7, x1, x2) + +inst_1396: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x01e and fs2 == 1 and fe2 == 0x13 and fm2 == 0x3c3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x501e; op2val:0xcfc3; + valaddr_reg:x3; val_offset:2740*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2740*FLEN/8, x7, x1, x2) + +inst_1397: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x01e and fs2 == 1 and fe2 == 0x13 and fm2 == 0x3c3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x501e; op2val:0xcfc3; + valaddr_reg:x3; val_offset:2742*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2742*FLEN/8, x7, x1, x2) + +inst_1398: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x01e and fs2 == 1 and fe2 == 0x13 and fm2 == 0x3c3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x501e; op2val:0xcfc3; + valaddr_reg:x3; val_offset:2744*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2744*FLEN/8, x7, x1, x2) + +inst_1399: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x01e and fs2 == 1 and fe2 == 0x13 and fm2 == 0x3c3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x501e; op2val:0xcfc3; + valaddr_reg:x3; val_offset:2746*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2746*FLEN/8, x7, x1, x2) + +inst_1400: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x190 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x0e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5190; op2val:0xcce0; + valaddr_reg:x3; val_offset:2748*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2748*FLEN/8, x7, x1, x2) + +inst_1401: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x190 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x0e0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5190; op2val:0xcce0; + valaddr_reg:x3; val_offset:2750*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2750*FLEN/8, x7, x1, x2) + +inst_1402: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x190 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x0e0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5190; op2val:0xcce0; + valaddr_reg:x3; val_offset:2752*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2752*FLEN/8, x7, x1, x2) + +inst_1403: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x190 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x0e0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5190; op2val:0xcce0; + valaddr_reg:x3; val_offset:2754*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2754*FLEN/8, x7, x1, x2) + +inst_1404: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x190 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x0e0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5190; op2val:0xcce0; + valaddr_reg:x3; val_offset:2756*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2756*FLEN/8, x7, x1, x2) + +inst_1405: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x18d and fs2 == 1 and fe2 == 0x13 and fm2 == 0x0e6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x518d; op2val:0xcce6; + valaddr_reg:x3; val_offset:2758*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2758*FLEN/8, x7, x1, x2) + +inst_1406: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x18d and fs2 == 1 and fe2 == 0x13 and fm2 == 0x0e6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x518d; op2val:0xcce6; + valaddr_reg:x3; val_offset:2760*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2760*FLEN/8, x7, x1, x2) + +inst_1407: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x18d and fs2 == 1 and fe2 == 0x13 and fm2 == 0x0e6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x518d; op2val:0xcce6; + valaddr_reg:x3; val_offset:2762*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2762*FLEN/8, x7, x1, x2) + +inst_1408: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x18d and fs2 == 1 and fe2 == 0x13 and fm2 == 0x0e6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x518d; op2val:0xcce6; + valaddr_reg:x3; val_offset:2764*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2764*FLEN/8, x7, x1, x2) + +inst_1409: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x18d and fs2 == 1 and fe2 == 0x13 and fm2 == 0x0e6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x518d; op2val:0xcce6; + valaddr_reg:x3; val_offset:2766*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2766*FLEN/8, x7, x1, x2) + +inst_1410: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x314 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x23b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4b14; op2val:0xd23b; + valaddr_reg:x3; val_offset:2768*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2768*FLEN/8, x7, x1, x2) + +inst_1411: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x314 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x23b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4b14; op2val:0xd23b; + valaddr_reg:x3; val_offset:2770*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2770*FLEN/8, x7, x1, x2) + +inst_1412: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x314 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x23b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4b14; op2val:0xd23b; + valaddr_reg:x3; val_offset:2772*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2772*FLEN/8, x7, x1, x2) + +inst_1413: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x314 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x23b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4b14; op2val:0xd23b; + valaddr_reg:x3; val_offset:2774*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2774*FLEN/8, x7, x1, x2) + +inst_1414: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x314 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x23b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x4b14; op2val:0xd23b; + valaddr_reg:x3; val_offset:2776*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2776*FLEN/8, x7, x1, x2) + +inst_1415: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x31a and fs2 == 1 and fe2 == 0x11 and fm2 == 0x32e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x531a; op2val:0xc72e; + valaddr_reg:x3; val_offset:2778*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2778*FLEN/8, x7, x1, x2) + +inst_1416: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x31a and fs2 == 1 and fe2 == 0x11 and fm2 == 0x32e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x531a; op2val:0xc72e; + valaddr_reg:x3; val_offset:2780*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2780*FLEN/8, x7, x1, x2) + +inst_1417: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x31a and fs2 == 1 and fe2 == 0x11 and fm2 == 0x32e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x531a; op2val:0xc72e; + valaddr_reg:x3; val_offset:2782*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2782*FLEN/8, x7, x1, x2) + +inst_1418: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x31a and fs2 == 1 and fe2 == 0x11 and fm2 == 0x32e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x531a; op2val:0xc72e; + valaddr_reg:x3; val_offset:2784*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2784*FLEN/8, x7, x1, x2) + +inst_1419: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x31a and fs2 == 1 and fe2 == 0x11 and fm2 == 0x32e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x531a; op2val:0xc72e; + valaddr_reg:x3; val_offset:2786*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2786*FLEN/8, x7, x1, x2) + +inst_1420: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x1b7 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x349 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x45b7; op2val:0xd349; + valaddr_reg:x3; val_offset:2788*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2788*FLEN/8, x7, x1, x2) + +inst_1421: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x1b7 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x349 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x45b7; op2val:0xd349; + valaddr_reg:x3; val_offset:2790*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2790*FLEN/8, x7, x1, x2) + +inst_1422: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x1b7 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x349 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x45b7; op2val:0xd349; + valaddr_reg:x3; val_offset:2792*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2792*FLEN/8, x7, x1, x2) + +inst_1423: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x1b7 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x349 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x45b7; op2val:0xd349; + valaddr_reg:x3; val_offset:2794*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2794*FLEN/8, x7, x1, x2) + +inst_1424: +// fs1 == 0 and fe1 == 0x11 and fm1 == 0x1b7 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x349 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x45b7; op2val:0xd349; + valaddr_reg:x3; val_offset:2796*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2796*FLEN/8, x7, x1, x2) + +inst_1425: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x03e and fs2 == 1 and fe2 == 0x13 and fm2 == 0x382 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x503e; op2val:0xcf82; + valaddr_reg:x3; val_offset:2798*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2798*FLEN/8, x7, x1, x2) + +inst_1426: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x03e and fs2 == 1 and fe2 == 0x13 and fm2 == 0x382 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x503e; op2val:0xcf82; + valaddr_reg:x3; val_offset:2800*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2800*FLEN/8, x7, x1, x2) + +inst_1427: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x03e and fs2 == 1 and fe2 == 0x13 and fm2 == 0x382 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x503e; op2val:0xcf82; + valaddr_reg:x3; val_offset:2802*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2802*FLEN/8, x7, x1, x2) + +inst_1428: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x03e and fs2 == 1 and fe2 == 0x13 and fm2 == 0x382 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x503e; op2val:0xcf82; + valaddr_reg:x3; val_offset:2804*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2804*FLEN/8, x7, x1, x2) + +inst_1429: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x03e and fs2 == 1 and fe2 == 0x13 and fm2 == 0x382 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x503e; op2val:0xcf82; + valaddr_reg:x3; val_offset:2806*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2806*FLEN/8, x7, x1, x2) + +inst_1430: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x027 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x3b1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5027; op2val:0xcfb1; + valaddr_reg:x3; val_offset:2808*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2808*FLEN/8, x7, x1, x2) + +inst_1431: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x027 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x3b1 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5027; op2val:0xcfb1; + valaddr_reg:x3; val_offset:2810*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2810*FLEN/8, x7, x1, x2) + +inst_1432: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x027 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x3b1 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5027; op2val:0xcfb1; + valaddr_reg:x3; val_offset:2812*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2812*FLEN/8, x7, x1, x2) + +inst_1433: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x027 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x3b1 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5027; op2val:0xcfb1; + valaddr_reg:x3; val_offset:2814*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2814*FLEN/8, x7, x1, x2) + +inst_1434: +// fs1 == 0 and fe1 == 0x14 and fm1 == 0x027 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x3b1 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x5027; op2val:0xcfb1; + valaddr_reg:x3; val_offset:2816*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2816*FLEN/8, x7, x1, x2) + +inst_1435: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x1cf and fs2 == 1 and fe2 == 0x14 and fm2 == 0x28c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x49cf; op2val:0xd28c; + valaddr_reg:x3; val_offset:2818*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2818*FLEN/8, x7, x1, x2) + +inst_1436: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x1cf and fs2 == 1 and fe2 == 0x14 and fm2 == 0x28c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x49cf; op2val:0xd28c; + valaddr_reg:x3; val_offset:2820*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2820*FLEN/8, x7, x1, x2) + +inst_1437: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x1cf and fs2 == 1 and fe2 == 0x14 and fm2 == 0x28c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x49cf; op2val:0xd28c; + valaddr_reg:x3; val_offset:2822*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2822*FLEN/8, x7, x1, x2) + +inst_1438: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x1cf and fs2 == 1 and fe2 == 0x14 and fm2 == 0x28c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x49cf; op2val:0xd28c; + valaddr_reg:x3; val_offset:2824*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2824*FLEN/8, x7, x1, x2) + +inst_1439: +// fs1 == 0 and fe1 == 0x12 and fm1 == 0x1cf and fs2 == 1 and fe2 == 0x14 and fm2 == 0x28c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x49cf; op2val:0xd28c; + valaddr_reg:x3; val_offset:2826*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2826*FLEN/8, x7, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_11) + +inst_1440: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0f1 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x071 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x34f1; op2val:0x3471; + valaddr_reg:x3; val_offset:2828*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2828*FLEN/8, x7, x1, x2) + +inst_1441: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0f1 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x071 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x34f1; op2val:0x3471; + valaddr_reg:x3; val_offset:2830*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2830*FLEN/8, x7, x1, x2) + +inst_1442: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0f1 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x071 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x34f1; op2val:0x3471; + valaddr_reg:x3; val_offset:2832*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2832*FLEN/8, x7, x1, x2) + +inst_1443: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0f1 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x071 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x34f1; op2val:0x3471; + valaddr_reg:x3; val_offset:2834*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2834*FLEN/8, x7, x1, x2) + +inst_1444: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0f1 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x071 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x34f1; op2val:0x3471; + valaddr_reg:x3; val_offset:2836*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2836*FLEN/8, x7, x1, x2) + +inst_1445: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1e8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1a8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39e8; op2val:0x39a8; + valaddr_reg:x3; val_offset:2838*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2838*FLEN/8, x7, x1, x2) + +inst_1446: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1e8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1a8 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39e8; op2val:0x39a8; + valaddr_reg:x3; val_offset:2840*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2840*FLEN/8, x7, x1, x2) + +inst_1447: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1e8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1a8 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39e8; op2val:0x39a8; + valaddr_reg:x3; val_offset:2842*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2842*FLEN/8, x7, x1, x2) + +inst_1448: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1e8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1a8 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39e8; op2val:0x39a8; + valaddr_reg:x3; val_offset:2844*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2844*FLEN/8, x7, x1, x2) + +inst_1449: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1e8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1a8 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x39e8; op2val:0x39a8; + valaddr_reg:x3; val_offset:2846*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2846*FLEN/8, x7, x1, x2) + +inst_1450: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x233 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1f3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a33; op2val:0x39f3; + valaddr_reg:x3; val_offset:2848*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2848*FLEN/8, x7, x1, x2) + +inst_1451: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x233 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1f3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a33; op2val:0x39f3; + valaddr_reg:x3; val_offset:2850*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2850*FLEN/8, x7, x1, x2) + +inst_1452: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x233 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1f3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a33; op2val:0x39f3; + valaddr_reg:x3; val_offset:2852*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2852*FLEN/8, x7, x1, x2) + +inst_1453: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x233 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1f3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a33; op2val:0x39f3; + valaddr_reg:x3; val_offset:2854*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2854*FLEN/8, x7, x1, x2) + +inst_1454: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x233 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1f3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a33; op2val:0x39f3; + valaddr_reg:x3; val_offset:2856*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2856*FLEN/8, x7, x1, x2) + +inst_1455: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2aa and fs2 == 0 and fe2 == 0x0e and fm2 == 0x26a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aaa; op2val:0x3a6a; + valaddr_reg:x3; val_offset:2858*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2858*FLEN/8, x7, x1, x2) + +inst_1456: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2aa and fs2 == 0 and fe2 == 0x0e and fm2 == 0x26a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aaa; op2val:0x3a6a; + valaddr_reg:x3; val_offset:2860*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2860*FLEN/8, x7, x1, x2) + +inst_1457: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2aa and fs2 == 0 and fe2 == 0x0e and fm2 == 0x26a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aaa; op2val:0x3a6a; + valaddr_reg:x3; val_offset:2862*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2862*FLEN/8, x7, x1, x2) + +inst_1458: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2aa and fs2 == 0 and fe2 == 0x0e and fm2 == 0x26a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aaa; op2val:0x3a6a; + valaddr_reg:x3; val_offset:2864*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2864*FLEN/8, x7, x1, x2) + +inst_1459: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2aa and fs2 == 0 and fe2 == 0x0e and fm2 == 0x26a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aaa; op2val:0x3a6a; + valaddr_reg:x3; val_offset:2866*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2866*FLEN/8, x7, x1, x2) + +inst_1460: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x121 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x021 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3121; op2val:0x3021; + valaddr_reg:x3; val_offset:2868*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2868*FLEN/8, x7, x1, x2) + +inst_1461: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x121 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x021 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3121; op2val:0x3021; + valaddr_reg:x3; val_offset:2870*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2870*FLEN/8, x7, x1, x2) + +inst_1462: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x121 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x021 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3121; op2val:0x3021; + valaddr_reg:x3; val_offset:2872*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2872*FLEN/8, x7, x1, x2) + +inst_1463: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x121 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x021 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3121; op2val:0x3021; + valaddr_reg:x3; val_offset:2874*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2874*FLEN/8, x7, x1, x2) + +inst_1464: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x121 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x021 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3121; op2val:0x3021; + valaddr_reg:x3; val_offset:2876*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2876*FLEN/8, x7, x1, x2) + +inst_1465: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x246 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x206 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a46; op2val:0x3a06; + valaddr_reg:x3; val_offset:2878*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2878*FLEN/8, x7, x1, x2) + +inst_1466: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x246 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x206 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a46; op2val:0x3a06; + valaddr_reg:x3; val_offset:2880*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2880*FLEN/8, x7, x1, x2) + +inst_1467: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x246 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x206 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a46; op2val:0x3a06; + valaddr_reg:x3; val_offset:2882*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2882*FLEN/8, x7, x1, x2) + +inst_1468: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x246 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x206 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a46; op2val:0x3a06; + valaddr_reg:x3; val_offset:2884*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2884*FLEN/8, x7, x1, x2) + +inst_1469: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x246 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x206 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a46; op2val:0x3a06; + valaddr_reg:x3; val_offset:2886*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2886*FLEN/8, x7, x1, x2) + +inst_1470: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x10b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x08b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x350b; op2val:0x348b; + valaddr_reg:x3; val_offset:2888*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2888*FLEN/8, x7, x1, x2) + +inst_1471: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x10b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x08b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x350b; op2val:0x348b; + valaddr_reg:x3; val_offset:2890*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2890*FLEN/8, x7, x1, x2) + +inst_1472: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x10b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x08b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x350b; op2val:0x348b; + valaddr_reg:x3; val_offset:2892*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2892*FLEN/8, x7, x1, x2) + +inst_1473: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x10b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x08b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x350b; op2val:0x348b; + valaddr_reg:x3; val_offset:2894*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2894*FLEN/8, x7, x1, x2) + +inst_1474: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x10b and fs2 == 0 and fe2 == 0x0d and fm2 == 0x08b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x350b; op2val:0x348b; + valaddr_reg:x3; val_offset:2896*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2896*FLEN/8, x7, x1, x2) + +inst_1475: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x383 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bc3; op2val:0x3b83; + valaddr_reg:x3; val_offset:2898*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2898*FLEN/8, x7, x1, x2) + +inst_1476: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x383 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bc3; op2val:0x3b83; + valaddr_reg:x3; val_offset:2900*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2900*FLEN/8, x7, x1, x2) + +inst_1477: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x383 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bc3; op2val:0x3b83; + valaddr_reg:x3; val_offset:2902*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2902*FLEN/8, x7, x1, x2) + +inst_1478: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x383 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bc3; op2val:0x3b83; + valaddr_reg:x3; val_offset:2904*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2904*FLEN/8, x7, x1, x2) + +inst_1479: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x383 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3bc3; op2val:0x3b83; + valaddr_reg:x3; val_offset:2906*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2906*FLEN/8, x7, x1, x2) + +inst_1480: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x25a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1da and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x365a; op2val:0x35da; + valaddr_reg:x3; val_offset:2908*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2908*FLEN/8, x7, x1, x2) + +inst_1481: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x25a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1da and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x365a; op2val:0x35da; + valaddr_reg:x3; val_offset:2910*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2910*FLEN/8, x7, x1, x2) + +inst_1482: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x25a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1da and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x365a; op2val:0x35da; + valaddr_reg:x3; val_offset:2912*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2912*FLEN/8, x7, x1, x2) + +inst_1483: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x25a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1da and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x365a; op2val:0x35da; + valaddr_reg:x3; val_offset:2914*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2914*FLEN/8, x7, x1, x2) + +inst_1484: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x25a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1da and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x365a; op2val:0x35da; + valaddr_reg:x3; val_offset:2916*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2916*FLEN/8, x7, x1, x2) + +inst_1485: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0a7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x067 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x38a7; op2val:0x3867; + valaddr_reg:x3; val_offset:2918*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2918*FLEN/8, x7, x1, x2) + +inst_1486: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0a7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x067 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x38a7; op2val:0x3867; + valaddr_reg:x3; val_offset:2920*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2920*FLEN/8, x7, x1, x2) + +inst_1487: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0a7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x067 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x38a7; op2val:0x3867; + valaddr_reg:x3; val_offset:2922*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2922*FLEN/8, x7, x1, x2) + +inst_1488: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0a7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x067 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x38a7; op2val:0x3867; + valaddr_reg:x3; val_offset:2924*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2924*FLEN/8, x7, x1, x2) + +inst_1489: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0a7 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x067 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x38a7; op2val:0x3867; + valaddr_reg:x3; val_offset:2926*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2926*FLEN/8, x7, x1, x2) + +inst_1490: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3a7 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2a6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x33a7; op2val:0x32a6; + valaddr_reg:x3; val_offset:2928*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2928*FLEN/8, x7, x1, x2) + +inst_1491: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3a7 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2a6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x33a7; op2val:0x32a6; + valaddr_reg:x3; val_offset:2930*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2930*FLEN/8, x7, x1, x2) + +inst_1492: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3a7 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2a6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x33a7; op2val:0x32a6; + valaddr_reg:x3; val_offset:2932*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2932*FLEN/8, x7, x1, x2) + +inst_1493: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3a7 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2a6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x33a7; op2val:0x32a6; + valaddr_reg:x3; val_offset:2934*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2934*FLEN/8, x7, x1, x2) + +inst_1494: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3a7 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x2a6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x33a7; op2val:0x32a6; + valaddr_reg:x3; val_offset:2936*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2936*FLEN/8, x7, x1, x2) + +inst_1495: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x24c and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1cc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x364c; op2val:0x35cc; + valaddr_reg:x3; val_offset:2938*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2938*FLEN/8, x7, x1, x2) + +inst_1496: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x24c and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1cc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x364c; op2val:0x35cc; + valaddr_reg:x3; val_offset:2940*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2940*FLEN/8, x7, x1, x2) + +inst_1497: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x24c and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1cc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x364c; op2val:0x35cc; + valaddr_reg:x3; val_offset:2942*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2942*FLEN/8, x7, x1, x2) + +inst_1498: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x24c and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1cc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x364c; op2val:0x35cc; + valaddr_reg:x3; val_offset:2944*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2944*FLEN/8, x7, x1, x2) + +inst_1499: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x24c and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1cc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x364c; op2val:0x35cc; + valaddr_reg:x3; val_offset:2946*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2946*FLEN/8, x7, x1, x2) + +inst_1500: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x357 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x2af and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b57; op2val:0x26af; + valaddr_reg:x3; val_offset:2948*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2948*FLEN/8, x7, x1, x2) + +inst_1501: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x357 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x2af and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b57; op2val:0x26af; + valaddr_reg:x3; val_offset:2950*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2950*FLEN/8, x7, x1, x2) + +inst_1502: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x357 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x2af and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b57; op2val:0x26af; + valaddr_reg:x3; val_offset:2952*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2952*FLEN/8, x7, x1, x2) + +inst_1503: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x357 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x2af and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b57; op2val:0x26af; + valaddr_reg:x3; val_offset:2954*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2954*FLEN/8, x7, x1, x2) + +inst_1504: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x357 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x2af and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b57; op2val:0x26af; + valaddr_reg:x3; val_offset:2956*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2956*FLEN/8, x7, x1, x2) + +inst_1505: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x362 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x162 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2f62; op2val:0x2d62; + valaddr_reg:x3; val_offset:2958*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2958*FLEN/8, x7, x1, x2) + +inst_1506: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x362 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x162 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2f62; op2val:0x2d62; + valaddr_reg:x3; val_offset:2960*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2960*FLEN/8, x7, x1, x2) + +inst_1507: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x362 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x162 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2f62; op2val:0x2d62; + valaddr_reg:x3; val_offset:2962*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2962*FLEN/8, x7, x1, x2) + +inst_1508: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x362 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x162 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2f62; op2val:0x2d62; + valaddr_reg:x3; val_offset:2964*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2964*FLEN/8, x7, x1, x2) + +inst_1509: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x362 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x162 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2f62; op2val:0x2d62; + valaddr_reg:x3; val_offset:2966*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2966*FLEN/8, x7, x1, x2) + +inst_1510: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x29a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x21a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x369a; op2val:0x361a; + valaddr_reg:x3; val_offset:2968*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2968*FLEN/8, x7, x1, x2) + +inst_1511: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x29a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x21a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x369a; op2val:0x361a; + valaddr_reg:x3; val_offset:2970*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2970*FLEN/8, x7, x1, x2) + +inst_1512: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x29a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x21a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x369a; op2val:0x361a; + valaddr_reg:x3; val_offset:2972*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2972*FLEN/8, x7, x1, x2) + +inst_1513: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x29a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x21a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x369a; op2val:0x361a; + valaddr_reg:x3; val_offset:2974*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2974*FLEN/8, x7, x1, x2) + +inst_1514: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x29a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x21a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x369a; op2val:0x361a; + valaddr_reg:x3; val_offset:2976*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2976*FLEN/8, x7, x1, x2) + +inst_1515: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x356 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x37d6; op2val:0x3756; + valaddr_reg:x3; val_offset:2978*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2978*FLEN/8, x7, x1, x2) + +inst_1516: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x356 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x37d6; op2val:0x3756; + valaddr_reg:x3; val_offset:2980*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2980*FLEN/8, x7, x1, x2) + +inst_1517: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x356 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x37d6; op2val:0x3756; + valaddr_reg:x3; val_offset:2982*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2982*FLEN/8, x7, x1, x2) + +inst_1518: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x356 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x37d6; op2val:0x3756; + valaddr_reg:x3; val_offset:2984*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2984*FLEN/8, x7, x1, x2) + +inst_1519: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x356 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x37d6; op2val:0x3756; + valaddr_reg:x3; val_offset:2986*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2986*FLEN/8, x7, x1, x2) + +inst_1520: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ee and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ae and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aee; op2val:0x3aae; + valaddr_reg:x3; val_offset:2988*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2988*FLEN/8, x7, x1, x2) + +inst_1521: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ee and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ae and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aee; op2val:0x3aae; + valaddr_reg:x3; val_offset:2990*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 2990*FLEN/8, x7, x1, x2) + +inst_1522: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ee and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ae and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aee; op2val:0x3aae; + valaddr_reg:x3; val_offset:2992*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 2992*FLEN/8, x7, x1, x2) + +inst_1523: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ee and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ae and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aee; op2val:0x3aae; + valaddr_reg:x3; val_offset:2994*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 2994*FLEN/8, x7, x1, x2) + +inst_1524: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ee and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ae and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aee; op2val:0x3aae; + valaddr_reg:x3; val_offset:2996*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 2996*FLEN/8, x7, x1, x2) + +inst_1525: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x133 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0f3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3933; op2val:0x38f3; + valaddr_reg:x3; val_offset:2998*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 2998*FLEN/8, x7, x1, x2) + +inst_1526: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x133 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0f3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3933; op2val:0x38f3; + valaddr_reg:x3; val_offset:3000*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 3000*FLEN/8, x7, x1, x2) + +inst_1527: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x133 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0f3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3933; op2val:0x38f3; + valaddr_reg:x3; val_offset:3002*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 3002*FLEN/8, x7, x1, x2) + +inst_1528: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x133 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0f3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3933; op2val:0x38f3; + valaddr_reg:x3; val_offset:3004*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 3004*FLEN/8, x7, x1, x2) + +inst_1529: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x133 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0f3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3933; op2val:0x38f3; + valaddr_reg:x3; val_offset:3006*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 3006*FLEN/8, x7, x1, x2) + +inst_1530: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x222 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1e2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a22; op2val:0x39e2; + valaddr_reg:x3; val_offset:3008*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 3008*FLEN/8, x7, x1, x2) + +inst_1531: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x222 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1e2 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a22; op2val:0x39e2; + valaddr_reg:x3; val_offset:3010*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 3010*FLEN/8, x7, x1, x2) + +inst_1532: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x222 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1e2 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a22; op2val:0x39e2; + valaddr_reg:x3; val_offset:3012*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 3012*FLEN/8, x7, x1, x2) + +inst_1533: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x222 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1e2 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a22; op2val:0x39e2; + valaddr_reg:x3; val_offset:3014*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 3014*FLEN/8, x7, x1, x2) + +inst_1534: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x222 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1e2 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a22; op2val:0x39e2; + valaddr_reg:x3; val_offset:3016*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 3016*FLEN/8, x7, x1, x2) + +inst_1535: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0dd and fs2 == 0 and fe2 == 0x0d and fm2 == 0x05d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x34dd; op2val:0x345d; + valaddr_reg:x3; val_offset:3018*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 3018*FLEN/8, x7, x1, x2) + +inst_1536: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0dd and fs2 == 0 and fe2 == 0x0d and fm2 == 0x05d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x34dd; op2val:0x345d; + valaddr_reg:x3; val_offset:3020*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 3020*FLEN/8, x7, x1, x2) + +inst_1537: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0dd and fs2 == 0 and fe2 == 0x0d and fm2 == 0x05d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x34dd; op2val:0x345d; + valaddr_reg:x3; val_offset:3022*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 3022*FLEN/8, x7, x1, x2) + +inst_1538: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0dd and fs2 == 0 and fe2 == 0x0d and fm2 == 0x05d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x34dd; op2val:0x345d; + valaddr_reg:x3; val_offset:3024*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 3024*FLEN/8, x7, x1, x2) + +inst_1539: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0dd and fs2 == 0 and fe2 == 0x0d and fm2 == 0x05d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x34dd; op2val:0x345d; + valaddr_reg:x3; val_offset:3026*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 3026*FLEN/8, x7, x1, x2) + +inst_1540: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x32c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ec and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b2c; op2val:0x3aec; + valaddr_reg:x3; val_offset:3028*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 3028*FLEN/8, x7, x1, x2) + +inst_1541: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x32c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ec and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b2c; op2val:0x3aec; + valaddr_reg:x3; val_offset:3030*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 3030*FLEN/8, x7, x1, x2) + +inst_1542: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x32c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ec and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b2c; op2val:0x3aec; + valaddr_reg:x3; val_offset:3032*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 3032*FLEN/8, x7, x1, x2) + +inst_1543: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x32c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ec and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b2c; op2val:0x3aec; + valaddr_reg:x3; val_offset:3034*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 3034*FLEN/8, x7, x1, x2) + +inst_1544: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x32c and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ec and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b2c; op2val:0x3aec; + valaddr_reg:x3; val_offset:3036*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 3036*FLEN/8, x7, x1, x2) + +inst_1545: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02f and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3de and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x382f; op2val:0x37de; + valaddr_reg:x3; val_offset:3038*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 3038*FLEN/8, x7, x1, x2) + +inst_1546: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02f and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3de and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x382f; op2val:0x37de; + valaddr_reg:x3; val_offset:3040*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 3040*FLEN/8, x7, x1, x2) + +inst_1547: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02f and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3de and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x382f; op2val:0x37de; + valaddr_reg:x3; val_offset:3042*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 3042*FLEN/8, x7, x1, x2) + +inst_1548: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02f and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3de and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x382f; op2val:0x37de; + valaddr_reg:x3; val_offset:3044*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 3044*FLEN/8, x7, x1, x2) + +inst_1549: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02f and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3de and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x382f; op2val:0x37de; + valaddr_reg:x3; val_offset:3046*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 3046*FLEN/8, x7, x1, x2) + +inst_1550: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x28d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x24d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a8d; op2val:0x3a4d; + valaddr_reg:x3; val_offset:3048*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 3048*FLEN/8, x7, x1, x2) + +inst_1551: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x28d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x24d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a8d; op2val:0x3a4d; + valaddr_reg:x3; val_offset:3050*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 3050*FLEN/8, x7, x1, x2) + +inst_1552: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x28d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x24d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a8d; op2val:0x3a4d; + valaddr_reg:x3; val_offset:3052*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 3052*FLEN/8, x7, x1, x2) + +inst_1553: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x28d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x24d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a8d; op2val:0x3a4d; + valaddr_reg:x3; val_offset:3054*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 3054*FLEN/8, x7, x1, x2) + +inst_1554: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x28d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x24d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a8d; op2val:0x3a4d; + valaddr_reg:x3; val_offset:3056*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 3056*FLEN/8, x7, x1, x2) + +inst_1555: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2bd and fs2 == 0 and fe2 == 0x0d and fm2 == 0x23d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x36bd; op2val:0x363d; + valaddr_reg:x3; val_offset:3058*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 3058*FLEN/8, x7, x1, x2) + +inst_1556: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2bd and fs2 == 0 and fe2 == 0x0d and fm2 == 0x23d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x36bd; op2val:0x363d; + valaddr_reg:x3; val_offset:3060*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 3060*FLEN/8, x7, x1, x2) + +inst_1557: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2bd and fs2 == 0 and fe2 == 0x0d and fm2 == 0x23d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x36bd; op2val:0x363d; + valaddr_reg:x3; val_offset:3062*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 3062*FLEN/8, x7, x1, x2) + +inst_1558: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2bd and fs2 == 0 and fe2 == 0x0d and fm2 == 0x23d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x36bd; op2val:0x363d; + valaddr_reg:x3; val_offset:3064*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 3064*FLEN/8, x7, x1, x2) + +inst_1559: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2bd and fs2 == 0 and fe2 == 0x0d and fm2 == 0x23d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x36bd; op2val:0x363d; + valaddr_reg:x3; val_offset:3066*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 3066*FLEN/8, x7, x1, x2) + +inst_1560: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x252 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x212 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a52; op2val:0x3a12; + valaddr_reg:x3; val_offset:3068*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 3068*FLEN/8, x7, x1, x2) + +inst_1561: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x252 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x212 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a52; op2val:0x3a12; + valaddr_reg:x3; val_offset:3070*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 3070*FLEN/8, x7, x1, x2) + +inst_1562: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x252 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x212 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a52; op2val:0x3a12; + valaddr_reg:x3; val_offset:3072*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 3072*FLEN/8, x7, x1, x2) + +inst_1563: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x252 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x212 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a52; op2val:0x3a12; + valaddr_reg:x3; val_offset:3074*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 3074*FLEN/8, x7, x1, x2) + +inst_1564: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x252 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x212 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a52; op2val:0x3a12; + valaddr_reg:x3; val_offset:3076*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 3076*FLEN/8, x7, x1, x2) + +inst_1565: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x116 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x096 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3516; op2val:0x3496; + valaddr_reg:x3; val_offset:3078*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 3078*FLEN/8, x7, x1, x2) + +inst_1566: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x116 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x096 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3516; op2val:0x3496; + valaddr_reg:x3; val_offset:3080*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 3080*FLEN/8, x7, x1, x2) + +inst_1567: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x116 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x096 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3516; op2val:0x3496; + valaddr_reg:x3; val_offset:3082*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 3082*FLEN/8, x7, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_12) + +inst_1568: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x116 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x096 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3516; op2val:0x3496; + valaddr_reg:x3; val_offset:3084*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 3084*FLEN/8, x7, x1, x2) + +inst_1569: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x116 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x096 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3516; op2val:0x3496; + valaddr_reg:x3; val_offset:3086*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 3086*FLEN/8, x7, x1, x2) + +inst_1570: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x039 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x072 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2c39; op2val:0x2872; + valaddr_reg:x3; val_offset:3088*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 3088*FLEN/8, x7, x1, x2) + +inst_1571: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x039 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x072 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2c39; op2val:0x2872; + valaddr_reg:x3; val_offset:3090*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 3090*FLEN/8, x7, x1, x2) + +inst_1572: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x039 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x072 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2c39; op2val:0x2872; + valaddr_reg:x3; val_offset:3092*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 3092*FLEN/8, x7, x1, x2) + +inst_1573: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x039 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x072 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2c39; op2val:0x2872; + valaddr_reg:x3; val_offset:3094*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 3094*FLEN/8, x7, x1, x2) + +inst_1574: +// fs1 == 0 and fe1 == 0x0b and fm1 == 0x039 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x072 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x2c39; op2val:0x2872; + valaddr_reg:x3; val_offset:3096*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 3096*FLEN/8, x7, x1, x2) + +inst_1575: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x158 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x118 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3958; op2val:0x3918; + valaddr_reg:x3; val_offset:3098*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 3098*FLEN/8, x7, x1, x2) + +inst_1576: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x158 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x118 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3958; op2val:0x3918; + valaddr_reg:x3; val_offset:3100*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 3100*FLEN/8, x7, x1, x2) + +inst_1577: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x158 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x118 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3958; op2val:0x3918; + valaddr_reg:x3; val_offset:3102*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 3102*FLEN/8, x7, x1, x2) + +inst_1578: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x158 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x118 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3958; op2val:0x3918; + valaddr_reg:x3; val_offset:3104*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 3104*FLEN/8, x7, x1, x2) + +inst_1579: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x158 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x118 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3958; op2val:0x3918; + valaddr_reg:x3; val_offset:3106*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 3106*FLEN/8, x7, x1, x2) + +inst_1580: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x315 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b15; op2val:0x3ad5; + valaddr_reg:x3; val_offset:3108*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 3108*FLEN/8, x7, x1, x2) + +inst_1581: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x315 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d5 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b15; op2val:0x3ad5; + valaddr_reg:x3; val_offset:3110*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 3110*FLEN/8, x7, x1, x2) + +inst_1582: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x315 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d5 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b15; op2val:0x3ad5; + valaddr_reg:x3; val_offset:3112*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 3112*FLEN/8, x7, x1, x2) + +inst_1583: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x315 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d5 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b15; op2val:0x3ad5; + valaddr_reg:x3; val_offset:3114*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 3114*FLEN/8, x7, x1, x2) + +inst_1584: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x315 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d5 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b15; op2val:0x3ad5; + valaddr_reg:x3; val_offset:3116*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 3116*FLEN/8, x7, x1, x2) + +inst_1585: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x343 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x303 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b43; op2val:0x3b03; + valaddr_reg:x3; val_offset:3118*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 3118*FLEN/8, x7, x1, x2) + +inst_1586: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x343 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x303 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b43; op2val:0x3b03; + valaddr_reg:x3; val_offset:3120*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 3120*FLEN/8, x7, x1, x2) + +inst_1587: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x343 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x303 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b43; op2val:0x3b03; + valaddr_reg:x3; val_offset:3122*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 3122*FLEN/8, x7, x1, x2) + +inst_1588: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x343 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x303 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b43; op2val:0x3b03; + valaddr_reg:x3; val_offset:3124*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 3124*FLEN/8, x7, x1, x2) + +inst_1589: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x343 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x303 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3b43; op2val:0x3b03; + valaddr_reg:x3; val_offset:3126*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 3126*FLEN/8, x7, x1, x2) + +inst_1590: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x029 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3d3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3829; op2val:0x37d3; + valaddr_reg:x3; val_offset:3128*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 3128*FLEN/8, x7, x1, x2) + +inst_1591: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x029 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3d3 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3829; op2val:0x37d3; + valaddr_reg:x3; val_offset:3130*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 3130*FLEN/8, x7, x1, x2) + +inst_1592: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x029 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3d3 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3829; op2val:0x37d3; + valaddr_reg:x3; val_offset:3132*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 3132*FLEN/8, x7, x1, x2) + +inst_1593: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x029 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3d3 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3829; op2val:0x37d3; + valaddr_reg:x3; val_offset:3134*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 3134*FLEN/8, x7, x1, x2) + +inst_1594: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x029 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3d3 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3829; op2val:0x37d3; + valaddr_reg:x3; val_offset:3136*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 3136*FLEN/8, x7, x1, x2) + +inst_1595: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b1 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x271 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ab1; op2val:0x3a71; + valaddr_reg:x3; val_offset:3138*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 3138*FLEN/8, x7, x1, x2) + +inst_1596: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b1 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x271 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ab1; op2val:0x3a71; + valaddr_reg:x3; val_offset:3140*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 3140*FLEN/8, x7, x1, x2) + +inst_1597: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b1 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x271 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ab1; op2val:0x3a71; + valaddr_reg:x3; val_offset:3142*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 3142*FLEN/8, x7, x1, x2) + +inst_1598: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b1 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x271 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ab1; op2val:0x3a71; + valaddr_reg:x3; val_offset:3144*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 3144*FLEN/8, x7, x1, x2) + +inst_1599: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b1 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x271 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3ab1; op2val:0x3a71; + valaddr_reg:x3; val_offset:3146*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 3146*FLEN/8, x7, x1, x2) + +inst_1600: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x293 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x193 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3293; op2val:0x3193; + valaddr_reg:x3; val_offset:3148*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 3148*FLEN/8, x7, x1, x2) + +inst_1601: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x293 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x193 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3293; op2val:0x3193; + valaddr_reg:x3; val_offset:3150*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 3150*FLEN/8, x7, x1, x2) + +inst_1602: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x293 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x193 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3293; op2val:0x3193; + valaddr_reg:x3; val_offset:3152*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 3152*FLEN/8, x7, x1, x2) + +inst_1603: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x293 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x193 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3293; op2val:0x3193; + valaddr_reg:x3; val_offset:3154*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 3154*FLEN/8, x7, x1, x2) + +inst_1604: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x293 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x193 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3293; op2val:0x3193; + valaddr_reg:x3; val_offset:3156*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 3156*FLEN/8, x7, x1, x2) + +inst_1605: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x302 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x282 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3702; op2val:0x3682; + valaddr_reg:x3; val_offset:3158*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 3158*FLEN/8, x7, x1, x2) + +inst_1606: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x302 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x282 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3702; op2val:0x3682; + valaddr_reg:x3; val_offset:3160*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 3160*FLEN/8, x7, x1, x2) + +inst_1607: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x302 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x282 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3702; op2val:0x3682; + valaddr_reg:x3; val_offset:3162*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 3162*FLEN/8, x7, x1, x2) + +inst_1608: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x302 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x282 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3702; op2val:0x3682; + valaddr_reg:x3; val_offset:3164*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 3164*FLEN/8, x7, x1, x2) + +inst_1609: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x302 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x282 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3702; op2val:0x3682; + valaddr_reg:x3; val_offset:3166*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 3166*FLEN/8, x7, x1, x2) + +inst_1610: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0eb and fs2 == 0 and fe2 == 0x0d and fm2 == 0x06b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x34eb; op2val:0x346b; + valaddr_reg:x3; val_offset:3168*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 3168*FLEN/8, x7, x1, x2) + +inst_1611: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0eb and fs2 == 0 and fe2 == 0x0d and fm2 == 0x06b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x34eb; op2val:0x346b; + valaddr_reg:x3; val_offset:3170*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 3170*FLEN/8, x7, x1, x2) + +inst_1612: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0eb and fs2 == 0 and fe2 == 0x0d and fm2 == 0x06b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x34eb; op2val:0x346b; + valaddr_reg:x3; val_offset:3172*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 3172*FLEN/8, x7, x1, x2) + +inst_1613: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0eb and fs2 == 0 and fe2 == 0x0d and fm2 == 0x06b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x34eb; op2val:0x346b; + valaddr_reg:x3; val_offset:3174*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 3174*FLEN/8, x7, x1, x2) + +inst_1614: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0eb and fs2 == 0 and fe2 == 0x0d and fm2 == 0x06b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x34eb; op2val:0x346b; + valaddr_reg:x3; val_offset:3176*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 3176*FLEN/8, x7, x1, x2) + +inst_1615: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2cc and fs2 == 0 and fe2 == 0x0d and fm2 == 0x24c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x36cc; op2val:0x364c; + valaddr_reg:x3; val_offset:3178*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 3178*FLEN/8, x7, x1, x2) + +inst_1616: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2cc and fs2 == 0 and fe2 == 0x0d and fm2 == 0x24c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x36cc; op2val:0x364c; + valaddr_reg:x3; val_offset:3180*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 3180*FLEN/8, x7, x1, x2) + +inst_1617: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2cc and fs2 == 0 and fe2 == 0x0d and fm2 == 0x24c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x36cc; op2val:0x364c; + valaddr_reg:x3; val_offset:3182*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 3182*FLEN/8, x7, x1, x2) + +inst_1618: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2cc and fs2 == 0 and fe2 == 0x0d and fm2 == 0x24c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x36cc; op2val:0x364c; + valaddr_reg:x3; val_offset:3184*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 3184*FLEN/8, x7, x1, x2) + +inst_1619: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2cc and fs2 == 0 and fe2 == 0x0d and fm2 == 0x24c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x36cc; op2val:0x364c; + valaddr_reg:x3; val_offset:3186*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 3186*FLEN/8, x7, x1, x2) + +inst_1620: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x0b2 and fs2 == 0 and fe2 == 0x07 and fm2 == 0x18f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x28b2; op2val:0x1d8f; + valaddr_reg:x3; val_offset:3188*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 3188*FLEN/8, x7, x1, x2) + +inst_1621: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x0b2 and fs2 == 0 and fe2 == 0x07 and fm2 == 0x18f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x28b2; op2val:0x1d8f; + valaddr_reg:x3; val_offset:3190*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 3190*FLEN/8, x7, x1, x2) + +inst_1622: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x0b2 and fs2 == 0 and fe2 == 0x07 and fm2 == 0x18f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x28b2; op2val:0x1d8f; + valaddr_reg:x3; val_offset:3192*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 3192*FLEN/8, x7, x1, x2) + +inst_1623: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x0b2 and fs2 == 0 and fe2 == 0x07 and fm2 == 0x18f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x28b2; op2val:0x1d8f; + valaddr_reg:x3; val_offset:3194*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 3194*FLEN/8, x7, x1, x2) + +inst_1624: +// fs1 == 0 and fe1 == 0x0a and fm1 == 0x0b2 and fs2 == 0 and fe2 == 0x07 and fm2 == 0x18f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x28b2; op2val:0x1d8f; + valaddr_reg:x3; val_offset:3196*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 3196*FLEN/8, x7, x1, x2) + +inst_1625: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x347 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x247 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3347; op2val:0x3247; + valaddr_reg:x3; val_offset:3198*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 3198*FLEN/8, x7, x1, x2) + +inst_1626: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x347 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x247 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3347; op2val:0x3247; + valaddr_reg:x3; val_offset:3200*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 3200*FLEN/8, x7, x1, x2) + +inst_1627: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x347 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x247 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3347; op2val:0x3247; + valaddr_reg:x3; val_offset:3202*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 3202*FLEN/8, x7, x1, x2) + +inst_1628: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x347 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x247 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3347; op2val:0x3247; + valaddr_reg:x3; val_offset:3204*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 3204*FLEN/8, x7, x1, x2) + +inst_1629: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x347 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x247 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3347; op2val:0x3247; + valaddr_reg:x3; val_offset:3206*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 3206*FLEN/8, x7, x1, x2) + +inst_1630: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x185 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x145 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3985; op2val:0x3945; + valaddr_reg:x3; val_offset:3208*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 3208*FLEN/8, x7, x1, x2) + +inst_1631: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x185 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x145 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3985; op2val:0x3945; + valaddr_reg:x3; val_offset:3210*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 3210*FLEN/8, x7, x1, x2) + +inst_1632: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x185 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x145 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3985; op2val:0x3945; + valaddr_reg:x3; val_offset:3212*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 3212*FLEN/8, x7, x1, x2) + +inst_1633: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x185 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x145 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3985; op2val:0x3945; + valaddr_reg:x3; val_offset:3214*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 3214*FLEN/8, x7, x1, x2) + +inst_1634: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x185 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x145 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3985; op2val:0x3945; + valaddr_reg:x3; val_offset:3216*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 3216*FLEN/8, x7, x1, x2) + +inst_1635: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x301 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x281 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3701; op2val:0x3681; + valaddr_reg:x3; val_offset:3218*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 3218*FLEN/8, x7, x1, x2) + +inst_1636: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x301 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x281 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3701; op2val:0x3681; + valaddr_reg:x3; val_offset:3220*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 3220*FLEN/8, x7, x1, x2) + +inst_1637: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x301 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x281 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3701; op2val:0x3681; + valaddr_reg:x3; val_offset:3222*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 3222*FLEN/8, x7, x1, x2) + +inst_1638: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x301 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x281 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3701; op2val:0x3681; + valaddr_reg:x3; val_offset:3224*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 3224*FLEN/8, x7, x1, x2) + +inst_1639: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x301 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x281 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3701; op2val:0x3681; + valaddr_reg:x3; val_offset:3226*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 3226*FLEN/8, x7, x1, x2) + +inst_1640: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0a6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x38e6; op2val:0x38a6; + valaddr_reg:x3; val_offset:3228*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 3228*FLEN/8, x7, x1, x2) + +inst_1641: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0a6 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x38e6; op2val:0x38a6; + valaddr_reg:x3; val_offset:3230*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 3230*FLEN/8, x7, x1, x2) + +inst_1642: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0a6 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x38e6; op2val:0x38a6; + valaddr_reg:x3; val_offset:3232*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 3232*FLEN/8, x7, x1, x2) + +inst_1643: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0a6 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x38e6; op2val:0x38a6; + valaddr_reg:x3; val_offset:3234*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 3234*FLEN/8, x7, x1, x2) + +inst_1644: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e6 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0a6 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x38e6; op2val:0x38a6; + valaddr_reg:x3; val_offset:3236*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 3236*FLEN/8, x7, x1, x2) + +inst_1645: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x03e and fs2 == 0 and fe2 == 0x0c and fm2 == 0x37c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x343e; op2val:0x337c; + valaddr_reg:x3; val_offset:3238*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 3238*FLEN/8, x7, x1, x2) + +inst_1646: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x03e and fs2 == 0 and fe2 == 0x0c and fm2 == 0x37c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x343e; op2val:0x337c; + valaddr_reg:x3; val_offset:3240*FLEN/8; rmval:dyn; fcsr: 32; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x3, 3240*FLEN/8, x7, x1, x2) + +inst_1647: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x03e and fs2 == 0 and fe2 == 0x0c and fm2 == 0x37c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x343e; op2val:0x337c; + valaddr_reg:x3; val_offset:3242*FLEN/8; rmval:dyn; fcsr: 64; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x3, 3242*FLEN/8, x7, x1, x2) + +inst_1648: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x03e and fs2 == 0 and fe2 == 0x0c and fm2 == 0x37c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x343e; op2val:0x337c; + valaddr_reg:x3; val_offset:3244*FLEN/8; rmval:dyn; fcsr: 96; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x3, 3244*FLEN/8, x7, x1, x2) + +inst_1649: +// fs1 == 0 and fe1 == 0x0d and fm1 == 0x03e and fs2 == 0 and fe2 == 0x0c and fm2 == 0x37c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x343e; op2val:0x337c; + valaddr_reg:x3; val_offset:3246*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 3246*FLEN/8, x7, x1, x2) + +inst_1650: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ec and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ec and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aec; op2val:0x3aec; + valaddr_reg:x3; val_offset:3248*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x3, 3248*FLEN/8, x7, x1, x2) + +inst_1651: +// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ec and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2ec and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 +/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x3aec; op2val:0x3aec; + valaddr_reg:x3; val_offset:3250*FLEN/8; rmval:dyn; fcsr: 128; + correctval:??; testreg:x2*/ +TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x3, 3250*FLEN/8, x7, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(15084,32,FLEN) +NAN_BOXED(15084,32,FLEN) +NAN_BOXED(15084,32,FLEN) +NAN_BOXED(15084,32,FLEN) +NAN_BOXED(15084,32,FLEN) +NAN_BOXED(15084,32,FLEN) +NAN_BOXED(15084,32,FLEN) +NAN_BOXED(15084,32,FLEN) +NAN_BOXED(13199,32,FLEN) +NAN_BOXED(13199,32,FLEN) +NAN_BOXED(13199,32,FLEN) +NAN_BOXED(13199,32,FLEN) +NAN_BOXED(13199,32,FLEN) +NAN_BOXED(13199,32,FLEN) +NAN_BOXED(13199,32,FLEN) +NAN_BOXED(13199,32,FLEN) +NAN_BOXED(13199,32,FLEN) +NAN_BOXED(13199,32,FLEN) +NAN_BOXED(14345,32,FLEN) +NAN_BOXED(14345,32,FLEN) +NAN_BOXED(14345,32,FLEN) +NAN_BOXED(14345,32,FLEN) +NAN_BOXED(14345,32,FLEN) +NAN_BOXED(14345,32,FLEN) +NAN_BOXED(14345,32,FLEN) +NAN_BOXED(14345,32,FLEN) +test_dataset_1: +NAN_BOXED(14345,32,FLEN) +NAN_BOXED(14345,32,FLEN) +NAN_BOXED(13715,32,FLEN) +NAN_BOXED(13715,32,FLEN) +NAN_BOXED(13715,32,FLEN) +NAN_BOXED(13715,32,FLEN) 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+NAN_BOXED(15084,16,FLEN) +NAN_BOXED(15084,16,FLEN) +NAN_BOXED(15084,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x10_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x10_1: + .fill 32*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x4_0: + .fill 32*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_0: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_2: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_3: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_4: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_5: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_6: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_7: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_8: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_9: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_10: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_11: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_12: + .fill 168*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/D_Zcd/src/c.fld-01.S b/riscv-test-suite/rv64i_m/D_Zcd/src/c.fld-01.S new file mode 100644 index 000000000..905d4833c --- /dev/null +++ b/riscv-test-suite/rv64i_m/D_Zcd/src/c.fld-01.S @@ -0,0 +1,173 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.0 +// timestamp : Wed Aug 16 05:06:00 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/riscv-ctg/sample_cgfs/RV32C/fld.cgf \ + \ +// -- xlen 64 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.fld instruction of the RISC-V RV64FDC extension for the c.fld covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64IFDC") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*C.*);def TEST_CASE_1=True;",c.fld) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 != rd, rs1==x15, rd==f15,imm_val == 0 and fcsr == 0, +// opcode:c.fld; op1:x15; dest:f15; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,0,x15,f15,0x0,c.fld,0,x4) + +inst_1: +// rs1==x14, rd==f14,imm_val > 0 and fcsr == 0, +// opcode:c.fld; op1:x14; dest:f14; immval:0xf8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,0,x14,f14,0xf8,c.fld,0,x4) + +inst_2: +// rs1==x13, rd==f13,imm_val == 168, +// opcode:c.fld; op1:x13; dest:f13; immval:0xa8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x13,f13,0xa8,c.fld,0,x4) + +inst_3: +// rs1==x12, rd==f12,imm_val == 80, +// opcode:c.fld; op1:x12; dest:f12; immval:0x50; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x12,f12,0x50,c.fld,0,x4) + +inst_4: +// rs1==x11, rd==f11,imm_val == 8, +// opcode:c.fld; op1:x11; dest:f11; immval:0x8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x11,f11,0x8,c.fld,0,x4) + +inst_5: +// rs1==x10, rd==f10,imm_val == 16, +// opcode:c.fld; op1:x10; dest:f10; immval:0x10; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x10,f10,0x10,c.fld,0,x4) + +inst_6: +// rs1==x9, rd==f9,imm_val == 240, +// opcode:c.fld; op1:x9; dest:f9; immval:0xf0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x9,f9,0xf0,c.fld,0,x4) + +inst_7: +// rs1==x8, rd==f8,imm_val == 232, +// opcode:c.fld; op1:x8; dest:f8; immval:0xe8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x8,f8,0xe8,c.fld,0,x4) + +inst_8: +// imm_val == 216, +// opcode:c.fld; op1:x15; dest:f15; immval:0xd8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x15,f15,0xd8,c.fld,0,x4) + +inst_9: +// imm_val == 184, +// opcode:c.fld; op1:x15; dest:f15; immval:0xb8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x15,f15,0xb8,c.fld,0,x4) + +inst_10: +// imm_val == 120, +// opcode:c.fld; op1:x15; dest:f15; immval:0x78; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x15,f15,0x78,c.fld,0,x4) + +inst_11: +// imm_val == 32, +// opcode:c.fld; op1:x15; dest:f15; immval:0x20; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x15,f15,0x20,c.fld,0,x4) + +inst_12: +// imm_val == 64, +// opcode:c.fld; op1:x15; dest:f15; immval:0x40; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x15,f15,0x40,c.fld,0,x4) + +inst_13: +// imm_val == 128, +// opcode:c.fld; op1:x15; dest:f15; immval:0x80; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x15,f15,0x80,c.fld,0,x4) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: + + + + + + + + + + + + + + +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/D_Zcd/src/c.fldsp-01.S b/riscv-test-suite/rv64i_m/D_Zcd/src/c.fldsp-01.S new file mode 100644 index 000000000..8594fffd0 --- /dev/null +++ b/riscv-test-suite/rv64i_m/D_Zcd/src/c.fldsp-01.S @@ -0,0 +1,247 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.0 +// timestamp : Wed Aug 16 05:06:00 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/riscv-ctg/sample_cgfs/RV32C/fld.cgf \ + \ +// -- xlen 64 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.fldsp instruction of the RISC-V RV64FDC extension for the c.fldsp covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64IFDC") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*C.*);def TEST_CASE_1=True;",c.fldsp) + +RVTEST_FP_ENABLE() +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rd==f31, imm_val == 0, +// opcode:c.fldsp; op1:x2; dest:f31; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f31,0x0,c.fldsp,0,x4) + +inst_1: +// rd==f30, imm_val > 0, +// opcode:c.fldsp; op1:x2; dest:f30; immval:0x1f8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f30,0x1f8,c.fldsp,0,x4) + +inst_2: +// rd==f29, imm_val == 168, +// opcode:c.fldsp; op1:x2; dest:f29; immval:0xa8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f29,0xa8,c.fldsp,0,x4) + +inst_3: +// rd==f28, imm_val == 336, +// opcode:c.fldsp; op1:x2; dest:f28; immval:0x150; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f28,0x150,c.fldsp,0,x4) + +inst_4: +// rd==f27, imm_val == 496, +// opcode:c.fldsp; op1:x2; dest:f27; immval:0x1f0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f27,0x1f0,c.fldsp,0,x4) + +inst_5: +// rd==f26, imm_val == 488, +// opcode:c.fldsp; op1:x2; dest:f26; immval:0x1e8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f26,0x1e8,c.fldsp,0,x4) + +inst_6: +// rd==f25, imm_val == 472, +// opcode:c.fldsp; op1:x2; dest:f25; immval:0x1d8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f25,0x1d8,c.fldsp,0,x4) + +inst_7: +// rd==f24, imm_val == 440, +// opcode:c.fldsp; op1:x2; dest:f24; immval:0x1b8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f24,0x1b8,c.fldsp,0,x4) + +inst_8: +// rd==f23, imm_val == 376, +// opcode:c.fldsp; op1:x2; dest:f23; immval:0x178; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f23,0x178,c.fldsp,0,x4) + +inst_9: +// rd==f22, imm_val == 248, +// opcode:c.fldsp; op1:x2; dest:f22; immval:0xf8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f22,0xf8,c.fldsp,0,x4) + +inst_10: +// rd==f21, imm_val == 8, +// opcode:c.fldsp; op1:x2; dest:f21; immval:0x8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f21,0x8,c.fldsp,0,x4) + +inst_11: +// rd==f20, imm_val == 16, +// opcode:c.fldsp; op1:x2; dest:f20; immval:0x10; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f20,0x10,c.fldsp,0,x4) + +inst_12: +// rd==f19, imm_val == 32, +// opcode:c.fldsp; op1:x2; dest:f19; immval:0x20; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f19,0x20,c.fldsp,0,x4) + +inst_13: +// rd==f18, imm_val == 64, +// opcode:c.fldsp; op1:x2; dest:f18; immval:0x40; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f18,0x40,c.fldsp,0,x4) + +inst_14: +// rd==f17, imm_val == 128, +// opcode:c.fldsp; op1:x2; dest:f17; immval:0x80; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f17,0x80,c.fldsp,0,x4) + +inst_15: +// rd==f16, imm_val == 256, +// opcode:c.fldsp; op1:x2; dest:f16; immval:0x100; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f16,0x100,c.fldsp,0,x4) + +inst_16: +// rd==f15, +// opcode:c.fldsp; op1:x2; dest:f15; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f15,0x0,c.fldsp,0,x4) + +inst_17: +// rd==f14, +// opcode:c.fldsp; op1:x2; dest:f14; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f14,0x0,c.fldsp,0,x4) + +inst_18: +// rd==f13, +// opcode:c.fldsp; op1:x2; dest:f13; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f13,0x0,c.fldsp,0,x4) + +inst_19: +// rd==f12, +// opcode:c.fldsp; op1:x2; dest:f12; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f12,0x0,c.fldsp,0,x4) + +inst_20: +// rd==f11, +// opcode:c.fldsp; op1:x2; dest:f11; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f11,0x0,c.fldsp,0,x4) + +inst_21: +// rd==f10, +// opcode:c.fldsp; op1:x2; dest:f10; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f10,0x0,c.fldsp,0,x4) + +inst_22: +// rd==f9, +// opcode:c.fldsp; op1:x2; dest:f9; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f9,0x0,c.fldsp,0,x4) + +inst_23: +// rd==f8, +// opcode:c.fldsp; op1:x2; dest:f8; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f8,0x0,c.fldsp,0,x4) + +inst_24: +// rd==f7, +// opcode:c.fldsp; op1:x2; dest:f7; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f7,0x0,c.fldsp,0,x4) + +inst_25: +// rd==f6, +// opcode:c.fldsp; op1:x2; dest:f6; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f6,0x0,c.fldsp,0,x4) + +inst_26: +// rd==f5, +// opcode:c.fldsp; op1:x2; dest:f5; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f5,0x0,c.fldsp,0,x4) + +inst_27: +// rd==f4, +// opcode:c.fldsp; op1:x2; dest:f4; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f4,0x0,c.fldsp,0,x4) + +inst_28: +// rd==f3, +// opcode:c.fldsp; op1:x2; dest:f3; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f3,0x0,c.fldsp,0,x4) + +inst_29: +// rd==f2, +// opcode:c.fldsp; op1:x2; dest:f2; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f2,0x0,c.fldsp,0,x4) + +inst_30: +// rd==f1, +// opcode:c.fldsp; op1:x2; dest:f1; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f1,0x0,c.fldsp,0,x4) + +inst_31: +// rd==f0, +// opcode:c.fldsp; op1:x2; dest:f0; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f0,0x0,c.fldsp,0,x4) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 64*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/D_Zcd/src/c.fsd-01.S b/riscv-test-suite/rv64i_m/D_Zcd/src/c.fsd-01.S new file mode 100644 index 000000000..b09cc9731 --- /dev/null +++ b/riscv-test-suite/rv64i_m/D_Zcd/src/c.fsd-01.S @@ -0,0 +1,213 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.0 +// timestamp : Wed Aug 16 05:06:00 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/riscv-ctg/sample_cgfs/RV32C/fld.cgf \ + \ +// -- xlen 64 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.fsd instruction of the RISC-V RV64FDC extension for the c.fsd covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64IFDC") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*C.*);def TEST_CASE_1=True;",c.fsd) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0:// rs1 != rs2, rs1==x15, rs2==f15,imm_val == 0, +// opcode: c.fsd; op1:x15; op2:f15; op2val:-0x1; immval:0x0; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 0*FLEN/8; +TEST_STORE_F(x1,x2,0,x15,f15,0x0,0*SIGALIGN,c.fsd,0,x4,x3, 0*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_1) + +inst_1:// rs1==x14, rs2==f14,imm_val > 0, +// opcode: c.fsd; op1:x14; op2:f14; op2val:-0x1; immval:0xf8; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 1*FLEN/8; +TEST_STORE_F(x1,x2,0,x14,f14,0xf8,2*SIGALIGN,c.fsd,0,x4,x3, 1*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_2) + +inst_2:// rs1==x13, rs2==f13,imm_val == 168, +// opcode: c.fsd; op1:x13; op2:f13; op2val:-0x1; immval:0xa8; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 2*FLEN/8; +TEST_STORE_F(x1,x2,0,x13,f13,0xa8,4*SIGALIGN,c.fsd,0,x4,x3, 2*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_3) + +inst_3:// rs1==x12, rs2==f12,imm_val == 80, +// opcode: c.fsd; op1:x12; op2:f12; op2val:-0x1; immval:0x50; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 3*FLEN/8; +TEST_STORE_F(x1,x2,0,x12,f12,0x50,6*SIGALIGN,c.fsd,0,x4,x3, 3*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_4) + +inst_4:// rs1==x11, rs2==f11,imm_val == 8, +// opcode: c.fsd; op1:x11; op2:f11; op2val:-0x1; immval:0x8; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 4*FLEN/8; +TEST_STORE_F(x1,x2,0,x11,f11,0x8,8*SIGALIGN,c.fsd,0,x4,x3, 4*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_5) + +inst_5:// rs1==x10, rs2==f10,imm_val == 16, +// opcode: c.fsd; op1:x10; op2:f10; op2val:-0x1; immval:0x10; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 5*FLEN/8; +TEST_STORE_F(x1,x2,0,x10,f10,0x10,10*SIGALIGN,c.fsd,0,x4,x3, 5*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_6) + +inst_6:// rs1==x9, rs2==f9,imm_val == 240, +// opcode: c.fsd; op1:x9; op2:f9; op2val:-0x1; immval:0xf0; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 6*FLEN/8; +TEST_STORE_F(x1,x2,0,x9,f9,0xf0,12*SIGALIGN,c.fsd,0,x4,x3, 6*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_7) + +inst_7:// rs1==x8, rs2==f8,imm_val == 232, +// opcode: c.fsd; op1:x8; op2:f8; op2val:-0x1; immval:0xe8; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 7*FLEN/8; +TEST_STORE_F(x1,x2,0,x8,f8,0xe8,14*SIGALIGN,c.fsd,0,x4,x3, 7*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_8) + +inst_8:// imm_val == 216, +// opcode: c.fsd; op1:x15; op2:f15; op2val:-0x1; immval:0xd8; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 8*FLEN/8; +TEST_STORE_F(x1,x2,0,x15,f15,0xd8,16*SIGALIGN,c.fsd,0,x4,x3, 8*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_9) + +inst_9:// imm_val == 184, +// opcode: c.fsd; op1:x15; op2:f15; op2val:-0x1; immval:0xb8; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 9*FLEN/8; +TEST_STORE_F(x1,x2,0,x15,f15,0xb8,18*SIGALIGN,c.fsd,0,x4,x3, 9*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_10) + +inst_10:// imm_val == 120, +// opcode: c.fsd; op1:x15; op2:f15; op2val:-0x1; immval:0x78; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 10*FLEN/8; +TEST_STORE_F(x1,x2,0,x15,f15,0x78,20*SIGALIGN,c.fsd,0,x4,x3, 10*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_11) + +inst_11:// imm_val == 32, +// opcode: c.fsd; op1:x15; op2:f15; op2val:-0x1; immval:0x20; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 11*FLEN/8; +TEST_STORE_F(x1,x2,0,x15,f15,0x20,22*SIGALIGN,c.fsd,0,x4,x3, 11*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_12) + +inst_12:// imm_val == 64, +// opcode: c.fsd; op1:x15; op2:f15; op2val:-0x1; immval:0x40; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 12*FLEN/8; +TEST_STORE_F(x1,x2,0,x15,f15,0x40,24*SIGALIGN,c.fsd,0,x4,x3, 12*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_13) + +inst_13:// imm_val == 128, +// opcode: c.fsd; op1:x15; op2:f15; op2val:-0x1; immval:0x80; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 13*FLEN/8; +TEST_STORE_F(x1,x2,0,x15,f15,0x80,26*SIGALIGN,c.fsd,0,x4,x3, 13*FLEN/8) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: + + +test_dataset_1: + + +test_dataset_2: + + +test_dataset_3: + + +test_dataset_4: + + +test_dataset_5: + + +test_dataset_6: + + +test_dataset_7: + + +test_dataset_8: + + +test_dataset_9: + + +test_dataset_10: + + +test_dataset_11: + + +test_dataset_12: + + +test_dataset_13: + + +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/D_Zcd/src/c.fsdsp-01.S b/riscv-test-suite/rv64i_m/D_Zcd/src/c.fsdsp-01.S new file mode 100644 index 000000000..51ba670e0 --- /dev/null +++ b/riscv-test-suite/rv64i_m/D_Zcd/src/c.fsdsp-01.S @@ -0,0 +1,343 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.0 +// timestamp : Wed Aug 16 05:06:00 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/riscv-ctg/sample_cgfs/RV32C/fld.cgf \ + \ +// -- xlen 64 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.fsdsp instruction of the RISC-V RV64FDC extension for the c.fsdsp covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64IFDC") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*C.*);def TEST_CASE_1=True;",c.fsdsp) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x4,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0:// rs2==f31, imm_val == 0, +// opcode: c.fsdsp; op1:x2; op2:f31; op2val:-0x1; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 0*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f31,0x0,0*SIGALIGN,c.fsdsp,0,x5,x4,0*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_1) + +inst_1:// rs2==f30, imm_val > 0, +// opcode: c.fsdsp; op1:x2; op2:f30; op2val:-0x1; immval:0x1f8; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 1*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f30,0x1f8,2*SIGALIGN,c.fsdsp,0,x5,x4,1*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_2) + +inst_2:// rs2==f29, imm_val == 168, +// opcode: c.fsdsp; op1:x2; op2:f29; op2val:-0x1; immval:0xa8; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 2*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f29,0xa8,4*SIGALIGN,c.fsdsp,0,x5,x4,2*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_3) + +inst_3:// rs2==f28, imm_val == 336, +// opcode: c.fsdsp; op1:x2; op2:f28; op2val:-0x1; immval:0x150; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 3*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f28,0x150,6*SIGALIGN,c.fsdsp,0,x5,x4,3*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_4) + +inst_4:// rs2==f27, imm_val == 496, +// opcode: c.fsdsp; op1:x2; op2:f27; op2val:-0x1; immval:0x1f0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 4*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f27,0x1f0,8*SIGALIGN,c.fsdsp,0,x5,x4,4*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_5) + +inst_5:// rs2==f26, imm_val == 488, +// opcode: c.fsdsp; op1:x2; op2:f26; op2val:-0x1; immval:0x1e8; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 5*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f26,0x1e8,10*SIGALIGN,c.fsdsp,0,x5,x4,5*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_6) + +inst_6:// rs2==f25, imm_val == 472, +// opcode: c.fsdsp; op1:x2; op2:f25; op2val:-0x1; immval:0x1d8; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 6*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f25,0x1d8,12*SIGALIGN,c.fsdsp,0,x5,x4,6*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_7) + +inst_7:// rs2==f24, imm_val == 440, +// opcode: c.fsdsp; op1:x2; op2:f24; op2val:-0x1; immval:0x1b8; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 7*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f24,0x1b8,14*SIGALIGN,c.fsdsp,0,x5,x4,7*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_8) + +inst_8:// rs2==f23, imm_val == 376, +// opcode: c.fsdsp; op1:x2; op2:f23; op2val:-0x1; immval:0x178; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 8*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f23,0x178,16*SIGALIGN,c.fsdsp,0,x5,x4,8*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_9) + +inst_9:// rs2==f22, imm_val == 248, +// opcode: c.fsdsp; op1:x2; op2:f22; op2val:-0x1; immval:0xf8; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 9*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f22,0xf8,18*SIGALIGN,c.fsdsp,0,x5,x4,9*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_10) + +inst_10:// rs2==f21, imm_val == 8, +// opcode: c.fsdsp; op1:x2; op2:f21; op2val:-0x1; immval:0x8; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 10*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f21,0x8,20*SIGALIGN,c.fsdsp,0,x5,x4,10*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_11) + +inst_11:// rs2==f20, imm_val == 16, +// opcode: c.fsdsp; op1:x2; op2:f20; op2val:-0x1; immval:0x10; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 11*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f20,0x10,22*SIGALIGN,c.fsdsp,0,x5,x4,11*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_12) + +inst_12:// rs2==f19, imm_val == 32, +// opcode: c.fsdsp; op1:x2; op2:f19; op2val:-0x1; immval:0x20; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 12*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f19,0x20,24*SIGALIGN,c.fsdsp,0,x5,x4,12*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_13) + +inst_13:// rs2==f18, imm_val == 64, +// opcode: c.fsdsp; op1:x2; op2:f18; op2val:-0x1; immval:0x40; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 13*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f18,0x40,26*SIGALIGN,c.fsdsp,0,x5,x4,13*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_14) + +inst_14:// rs2==f17, imm_val == 128, +// opcode: c.fsdsp; op1:x2; op2:f17; op2val:-0x1; immval:0x80; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 14*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f17,0x80,28*SIGALIGN,c.fsdsp,0,x5,x4,14*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_15) + +inst_15:// rs2==f16, imm_val == 256, +// opcode: c.fsdsp; op1:x2; op2:f16; op2val:-0x1; immval:0x100; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 15*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f16,0x100,30*SIGALIGN,c.fsdsp,0,x5,x4,15*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_16) + +inst_16:// rs2==f15, +// opcode: c.fsdsp; op1:x2; op2:f15; op2val:0x0; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 16*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f15,0x0,32*SIGALIGN,c.fsdsp,0,x5,x4,16*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_17) + +inst_17:// rs2==f14, +// opcode: c.fsdsp; op1:x2; op2:f14; op2val:0x0; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 17*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f14,0x0,34*SIGALIGN,c.fsdsp,0,x5,x4,17*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_18) + +inst_18:// rs2==f13, +// opcode: c.fsdsp; op1:x2; op2:f13; op2val:0x0; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 18*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f13,0x0,36*SIGALIGN,c.fsdsp,0,x5,x4,18*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_19) + +inst_19:// rs2==f12, +// opcode: c.fsdsp; op1:x2; op2:f12; op2val:0x0; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 19*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f12,0x0,38*SIGALIGN,c.fsdsp,0,x5,x4,19*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_20) + +inst_20:// rs2==f11, +// opcode: c.fsdsp; op1:x2; op2:f11; op2val:0x0; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 20*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f11,0x0,40*SIGALIGN,c.fsdsp,0,x5,x4,20*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_21) + +inst_21:// rs2==f10, +// opcode: c.fsdsp; op1:x2; op2:f10; op2val:0x0; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 21*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f10,0x0,42*SIGALIGN,c.fsdsp,0,x5,x4,21*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_22) + +inst_22:// rs2==f9, +// opcode: c.fsdsp; op1:x2; op2:f9; op2val:0x0; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 22*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f9,0x0,44*SIGALIGN,c.fsdsp,0,x5,x4,22*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_23) + +inst_23:// rs2==f8, +// opcode: c.fsdsp; op1:x2; op2:f8; op2val:0x0; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 23*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f8,0x0,46*SIGALIGN,c.fsdsp,0,x5,x4,23*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_24) + +inst_24:// rs2==f7, +// opcode: c.fsdsp; op1:x2; op2:f7; op2val:0x0; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 24*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f7,0x0,48*SIGALIGN,c.fsdsp,0,x5,x4,24*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_25) + +inst_25:// rs2==f6, +// opcode: c.fsdsp; op1:x2; op2:f6; op2val:0x0; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 25*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f6,0x0,50*SIGALIGN,c.fsdsp,0,x5,x4,25*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_26) + +inst_26:// rs2==f5, +// opcode: c.fsdsp; op1:x2; op2:f5; op2val:0x0; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 26*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f5,0x0,52*SIGALIGN,c.fsdsp,0,x5,x4,26*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_27) + +inst_27:// rs2==f4, +// opcode: c.fsdsp; op1:x2; op2:f4; op2val:0x0; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 27*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f4,0x0,54*SIGALIGN,c.fsdsp,0,x5,x4,27*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_28) + +inst_28:// rs2==f3, +// opcode: c.fsdsp; op1:x2; op2:f3; op2val:0x0; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 28*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f3,0x0,56*SIGALIGN,c.fsdsp,0,x5,x4,28*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_29) + +inst_29:// rs2==f2, +// opcode: c.fsdsp; op1:x2; op2:f2; op2val:0x0; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 29*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f2,0x0,58*SIGALIGN,c.fsdsp,0,x5,x4,29*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_30) + +inst_30:// rs2==f1, +// opcode: c.fsdsp; op1:x2; op2:f1; op2val:0x0; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 30*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f1,0x0,60*SIGALIGN,c.fsdsp,0,x5,x4,30*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_31) + +inst_31:// rs2==f0, +// opcode: c.fsdsp; op1:x2; op2:f0; op2val:0x0; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 31*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f0,0x0,62*SIGALIGN,c.fsdsp,0,x5,x4,31*FLEN/8) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: + +test_dataset_1: + +test_dataset_2: + +test_dataset_3: + +test_dataset_4: + +test_dataset_5: + +test_dataset_6: + +test_dataset_7: + +test_dataset_8: + +test_dataset_9: + +test_dataset_10: + +test_dataset_11: + +test_dataset_12: + +test_dataset_13: + +test_dataset_14: + +test_dataset_15: + +test_dataset_16: + +test_dataset_17: + +test_dataset_18: + +test_dataset_19: + +test_dataset_20: + +test_dataset_21: + +test_dataset_22: + +test_dataset_23: + +test_dataset_24: + +test_dataset_25: + +test_dataset_26: + +test_dataset_27: + +test_dataset_28: + +test_dataset_29: + +test_dataset_30: + +test_dataset_31: + +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 64*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/I/src/sra-01.S b/riscv-test-suite/rv64i_m/I/src/sra-01.S index 00bc7b446..a40803ed3 100644 --- a/riscv-test-suite/rv64i_m/I/src/sra-01.S +++ b/riscv-test-suite/rv64i_m/I/src/sra-01.S @@ -1,11 +1,13 @@ // ----------- -// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg) -// version : 0.4.1 -// timestamp : Wed Dec 16 03:45:17 2020 GMT +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Mon Nov 18 08:18:47 2024 GMT // usage : riscv_ctg \ -// -- cgf ('/scratch/git-repo/incoresemi/riscv-compliance/riscv_ctg/sample_cgfs/dataset.cgf', '/scratch/git-repo/incoresemi/riscv-compliance/riscv_ctg/sample_cgfs/rv64i.cgf') \ -// -- xlen 64 \ +// -- cgf // --cgf /workspaces/riscv-arch-test/coverage/dataset.cgf \ +// --cgf /workspaces/riscv-arch-test/coverage/i/rv64i.cgf \ + \ +// -- xlen 64 \ // ----------- // // ----------- @@ -13,7 +15,7 @@ // SPDX-License-Identifier: BSD-3-Clause // ----------- // -// This assembly file tests the sra instruction of the RISC-V i extension for the sra covergroup. +// This assembly file tests the sra instruction of the RISC-V RV64 extension for the sra covergroup. // #include "model_test.h" #include "arch_test.h" @@ -27,780 +29,195 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",sra) +RVTEST_CASE(0,"//check ISA:=regex(.*I.*);def TEST_CASE_1=True;",sra) -RVTEST_SIGBASE( x9,signature_x9_1) +RVTEST_SIGBASE(x1,signature_x1_1) inst_0: -// rs1 == rs2 != rd, rs1==x23, rs2==x23, rd==x7, rs1_val < 0 and rs2_val > 0 and rs2_val < xlen, rs1_val == -34359738369 -// opcode: sra ; op1:x23; op2:x23; dest:x7; op1val:-0x800000001; op2val:-0x800000001 -TEST_RR_OP(sra, x7, x23, x23, -0x1, -0x800000001, -0x800000001, x9, 0, x10) +// rs1 == rs2 != rd, rs1==x30, rs2==x30, rd==x31, rs1_val < 0 and rs2_val == 0, +// opcode: sra ; op1:x30; op2:x30; dest:x31; op1val:-0xb504f332; op2val:-0xb504f332 +TEST_RR_OP(sra, x31, x30, x30, -0x2d414, -0xb504f332, -0xb504f332, x1, 0*XLEN/8, x2) inst_1: -// rs2 == rd != rs1, rs1==x15, rs2==x3, rd==x3, rs1_val > 0 and rs2_val > 0 and rs2_val < xlen, rs1_val == 4294967296 -// opcode: sra ; op1:x15; op2:x3; dest:x3; op1val:0x100000000; op2val:0x3 -TEST_RR_OP(sra, x3, x15, x3, 0x20000000, 0x100000000, 0x3, x9, 8, x10) +// rs1 == rs2 == rd, rs1==x29, rs2==x29, rd==x29, rs1_val < 0 and rs2_val > 0 and rs2_val < xlen, +// opcode: sra ; op1:x29; op2:x29; dest:x29; op1val:-0xb504f332; op2val:-0xb504f332 +TEST_RR_OP(sra, x29, x29, x29, -0x2d414, -0xb504f332, -0xb504f332, x1, 1*XLEN/8, x2) inst_2: -// rs1 == rs2 == rd, rs1==x4, rs2==x4, rd==x4, rs1_val < 0 and rs2_val == 0, rs1_val == -4294967297 -// opcode: sra ; op1:x4; op2:x4; dest:x4; op1val:-0x100000001; op2val:-0x100000001 -TEST_RR_OP(sra, x4, x4, x4, -0x1, -0x100000001, -0x100000001, x9, 16, x10) +// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==x31, rs2==x28, rd==x30, rs1_val == (-2**(xlen-1)) and rs2_val >= 0 and rs2_val < xlen, +// opcode: sra ; op1:x31; op2:x28; dest:x30; op1val:-0x8000000000000000; op2val:0x3f +TEST_RR_OP(sra, x30, x31, x28, -0x1, -0x8000000000000000, 0x3f, x1, 2*XLEN/8, x2) inst_3: -// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==x27, rs2==x24, rd==x30, rs1_val > 0 and rs2_val == 0, rs1_val==3689348814741910323 -// opcode: sra ; op1:x27; op2:x24; dest:x30; op1val:0x3333333333333333; op2val:0x0 -TEST_RR_OP(sra, x30, x27, x24, 0x3333333333333333, 0x3333333333333333, 0x0, x9, 24, x10) +// rs2 == rd != rs1, rs1==x28, rs2==x27, rd==x27, rs1_val == (2**(xlen-1)-1) and rs2_val >= 0 and rs2_val < xlen, rs1_val > 0 and rs2_val > 0 and rs2_val < xlen +// opcode: sra ; op1:x28; op2:x27; dest:x27; op1val:0x7fffffffffffffff; op2val:0x3f +TEST_RR_OP(sra, x27, x28, x27, 0x0, 0x7fffffffffffffff, 0x3f, x1, 3*XLEN/8, x2) inst_4: -// rs1 == rd != rs2, rs1==x20, rs2==x18, rd==x20, rs1_val == rs2_val and rs2_val > 0 and rs2_val < xlen, rs1_val == 1 and rs2_val >= 0 and rs2_val < xlen, rs1_val == 1, rs2_val == 1 -// opcode: sra ; op1:x20; op2:x18; dest:x20; op1val:0x1; op2val:0x1 -TEST_RR_OP(sra, x20, x20, x18, 0x0, 0x1, 0x1, x9, 32, x10) +// rs1 == rd != rs2, rs1==x26, rs2==x31, rd==x26, rs1_val == 0 and rs2_val >= 0 and rs2_val < xlen, +// opcode: sra ; op1:x26; op2:x31; dest:x26; op1val:0x0; op2val:0x3f +TEST_RR_OP(sra, x26, x26, x31, 0x0, 0x0, 0x3f, x1, 4*XLEN/8, x2) inst_5: -// rs1==x2, rs2==x15, rd==x24, rs1_val == (-2**(xlen-1)) and rs2_val >= 0 and rs2_val < xlen, rs1_val == -9223372036854775808, rs2_val == 2 -// opcode: sra ; op1:x2; op2:x15; dest:x24; op1val:-0x8000000000000000; op2val:0x2 -TEST_RR_OP(sra, x24, x2, x15, -0x2000000000000000, -0x8000000000000000, 0x2, x9, 40, x10) +// rs1==x27, rs2==x26, rd==x28, rs1_val == 1 and rs2_val >= 0 and rs2_val < xlen, +// opcode: sra ; op1:x27; op2:x26; dest:x28; op1val:0x1; op2val:0x3f +TEST_RR_OP(sra, x28, x27, x26, 0x0, 0x1, 0x3f, x1, 5*XLEN/8, x2) inst_6: -// rs1==x13, rs2==x8, rd==x26, rs1_val == 0 and rs2_val >= 0 and rs2_val < xlen, rs1_val==0 -// opcode: sra ; op1:x13; op2:x8; dest:x26; op1val:0x0; op2val:0xe -TEST_RR_OP(sra, x26, x13, x8, 0x0, 0x0, 0xe, x9, 48, x10) +// rs1==x24, rs2==x23, rd==x25, rs1_val == rs2_val and rs2_val > 0 and rs2_val < xlen, +// opcode: sra ; op1:x24; op2:x23; dest:x25; op1val:0x20; op2val:0x20 +TEST_RR_OP(sra, x25, x24, x23, 0x0, 0x20, 0x20, x1, 6*XLEN/8, x2) inst_7: -// rs1==x14, rs2==x0, rd==x28, rs1_val == (2**(xlen-1)-1) and rs2_val >= 0 and rs2_val < xlen, rs1_val == 9223372036854775807 -// opcode: sra ; op1:x14; op2:x0; dest:x28; op1val:0x7fffffffffffffff; op2val:0x0 -TEST_RR_OP(sra, x28, x14, x0, 0x7fffffffffffffff, 0x7fffffffffffffff, 0x0, x9, 56, x10) +// rs1==x23, rs2==x25, rd==x24, rs1_val > 0 and rs2_val == 0, +// opcode: sra ; op1:x23; op2:x25; dest:x24; op1val:0xb504f334; op2val:0x0 +TEST_RR_OP(sra, x24, x23, x25, 0xb504f334, 0xb504f334, 0x0, x1, 7*XLEN/8, x2) inst_8: -// rs1==x25, rs2==x22, rd==x6, rs1_val == 2, rs1_val==2 -// opcode: sra ; op1:x25; op2:x22; dest:x6; op1val:0x2; op2val:0xa -TEST_RR_OP(sra, x6, x25, x22, 0x0, 0x2, 0xa, x9, 64, x10) +// rs1==x25, rs2==x24, rd==x23, +// opcode: sra ; op1:x25; op2:x24; dest:x23; op1val:0x0; op2val:0x0 +TEST_RR_OP(sra, x23, x25, x24, 0x0, 0x0, 0x0, x1, 8*XLEN/8, x2) inst_9: -// rs1==x29, rs2==x12, rd==x18, rs1_val == 4, rs1_val==4 -// opcode: sra ; op1:x29; op2:x12; dest:x18; op1val:0x4; op2val:0x7 -TEST_RR_OP(sra, x18, x29, x12, 0x0, 0x4, 0x7, x9, 72, x10) +// rs1==x21, rs2==x20, rd==x22, +// opcode: sra ; op1:x21; op2:x20; dest:x22; op1val:0x0; op2val:0x0 +TEST_RR_OP(sra, x22, x21, x20, 0x0, 0x0, 0x0, x1, 9*XLEN/8, x2) inst_10: -// rs1==x3, rs2==x28, rd==x11, rs1_val == 8, -// opcode: sra ; op1:x3; op2:x28; dest:x11; op1val:0x8; op2val:0xa -TEST_RR_OP(sra, x11, x3, x28, 0x0, 0x8, 0xa, x9, 80, x10) +// rs1==x20, rs2==x22, rd==x21, +// opcode: sra ; op1:x20; op2:x22; dest:x21; op1val:0x0; op2val:0x0 +TEST_RR_OP(sra, x21, x20, x22, 0x0, 0x0, 0x0, x1, 10*XLEN/8, x2) inst_11: -// rs1==x0, rs2==x16, rd==x8, rs1_val == 16, -// opcode: sra ; op1:x0; op2:x16; dest:x8; op1val:0x0; op2val:0x6 -TEST_RR_OP(sra, x8, x0, x16, 0x0, 0x0, 0x6, x9, 88, x10) +// rs1==x22, rs2==x21, rd==x20, +// opcode: sra ; op1:x22; op2:x21; dest:x20; op1val:0x0; op2val:0x0 +TEST_RR_OP(sra, x20, x22, x21, 0x0, 0x0, 0x0, x1, 11*XLEN/8, x2) inst_12: -// rs1==x24, rs2==x5, rd==x12, rs1_val == 32, -// opcode: sra ; op1:x24; op2:x5; dest:x12; op1val:0x20; op2val:0x1 -TEST_RR_OP(sra, x12, x24, x5, 0x10, 0x20, 0x1, x9, 96, x10) +// rs1==x18, rs2==x17, rd==x19, +// opcode: sra ; op1:x18; op2:x17; dest:x19; op1val:0x0; op2val:0x0 +TEST_RR_OP(sra, x19, x18, x17, 0x0, 0x0, 0x0, x1, 12*XLEN/8, x2) inst_13: -// rs1==x31, rs2==x21, rd==x2, rs1_val == 64, rs2_val == 8 -// opcode: sra ; op1:x31; op2:x21; dest:x2; op1val:0x40; op2val:0x8 -TEST_RR_OP(sra, x2, x31, x21, 0x0, 0x40, 0x8, x9, 104, x10) +// rs1==x17, rs2==x19, rd==x18, +// opcode: sra ; op1:x17; op2:x19; dest:x18; op1val:0x0; op2val:0x0 +TEST_RR_OP(sra, x18, x17, x19, 0x0, 0x0, 0x0, x1, 13*XLEN/8, x2) inst_14: -// rs1==x8, rs2==x1, rd==x21, rs1_val == 128, -// opcode: sra ; op1:x8; op2:x1; dest:x21; op1val:0x80; op2val:0xe -TEST_RR_OP(sra, x21, x8, x1, 0x0, 0x80, 0xe, x9, 112, x10) +// rs1==x19, rs2==x18, rd==x17, +// opcode: sra ; op1:x19; op2:x18; dest:x17; op1val:0x0; op2val:0x0 +TEST_RR_OP(sra, x17, x19, x18, 0x0, 0x0, 0x0, x1, 14*XLEN/8, x2) inst_15: -// rs1==x1, rs2==x30, rd==x14, rs1_val == 256, -// opcode: sra ; op1:x1; op2:x30; dest:x14; op1val:0x100; op2val:0x3 -TEST_RR_OP(sra, x14, x1, x30, 0x20, 0x100, 0x3, x9, 120, x4) +// rs1==x15, rs2==x14, rd==x16, +// opcode: sra ; op1:x15; op2:x14; dest:x16; op1val:0x0; op2val:0x0 +TEST_RR_OP(sra, x16, x15, x14, 0x0, 0x0, 0x0, x1, 15*XLEN/8, x2) inst_16: -// rs1==x16, rs2==x10, rd==x0, rs1_val == 512, -// opcode: sra ; op1:x16; op2:x10; dest:x0; op1val:0x200; op2val:0xb -TEST_RR_OP(sra, x0, x16, x10, 0, 0x200, 0xb, x9, 128, x4) -RVTEST_SIGBASE( x3,signature_x3_0) +// rs1==x14, rs2==x16, rd==x15, +// opcode: sra ; op1:x14; op2:x16; dest:x15; op1val:0x0; op2val:0x0 +TEST_RR_OP(sra, x15, x14, x16, 0x0, 0x0, 0x0, x1, 16*XLEN/8, x2) inst_17: -// rs1==x26, rs2==x29, rd==x10, rs1_val == 1024, -// opcode: sra ; op1:x26; op2:x29; dest:x10; op1val:0x400; op2val:0xe -TEST_RR_OP(sra, x10, x26, x29, 0x0, 0x400, 0xe, x3, 0, x4) +// rs1==x16, rs2==x15, rd==x14, +// opcode: sra ; op1:x16; op2:x15; dest:x14; op1val:0x0; op2val:0x0 +TEST_RR_OP(sra, x14, x16, x15, 0x0, 0x0, 0x0, x1, 17*XLEN/8, x2) inst_18: -// rs1==x9, rs2==x27, rd==x31, rs1_val == 2048, rs2_val == 42 -// opcode: sra ; op1:x9; op2:x27; dest:x31; op1val:0x800; op2val:0x2a -TEST_RR_OP(sra, x31, x9, x27, 0x0, 0x800, 0x2a, x3, 8, x4) +// rs1==x12, rs2==x11, rd==x13, +// opcode: sra ; op1:x12; op2:x11; dest:x13; op1val:0x0; op2val:0x0 +TEST_RR_OP(sra, x13, x12, x11, 0x0, 0x0, 0x0, x1, 18*XLEN/8, x2) inst_19: -// rs1==x22, rs2==x19, rd==x1, rs1_val == 4096, rs2_val == 4 -// opcode: sra ; op1:x22; op2:x19; dest:x1; op1val:0x1000; op2val:0x4 -TEST_RR_OP(sra, x1, x22, x19, 0x100, 0x1000, 0x4, x3, 16, x4) +// rs1==x11, rs2==x13, rd==x12, +// opcode: sra ; op1:x11; op2:x13; dest:x12; op1val:0x0; op2val:0x0 +TEST_RR_OP(sra, x12, x11, x13, 0x0, 0x0, 0x0, x1, 19*XLEN/8, x2) inst_20: -// rs1==x17, rs2==x13, rd==x9, rs1_val == 8192, -// opcode: sra ; op1:x17; op2:x13; dest:x9; op1val:0x2000; op2val:0x9 -TEST_RR_OP(sra, x9, x17, x13, 0x10, 0x2000, 0x9, x3, 24, x4) +// rs1==x13, rs2==x12, rd==x11, +// opcode: sra ; op1:x13; op2:x12; dest:x11; op1val:0x0; op2val:0x0 +TEST_RR_OP(sra, x11, x13, x12, 0x0, 0x0, 0x0, x1, 20*XLEN/8, x2) inst_21: -// rs1==x18, rs2==x7, rd==x13, rs1_val == 16384, rs2_val == 31 -// opcode: sra ; op1:x18; op2:x7; dest:x13; op1val:0x4000; op2val:0x1f -TEST_RR_OP(sra, x13, x18, x7, 0x0, 0x4000, 0x1f, x3, 32, x4) +// rs1==x9, rs2==x8, rd==x10, +// opcode: sra ; op1:x9; op2:x8; dest:x10; op1val:0x0; op2val:0x0 +TEST_RR_OP(sra, x10, x9, x8, 0x0, 0x0, 0x0, x1, 21*XLEN/8, x2) inst_22: -// rs1==x7, rs2==x31, rd==x19, rs1_val == 32768, -// opcode: sra ; op1:x7; op2:x31; dest:x19; op1val:0x8000; op2val:0x9 -TEST_RR_OP(sra, x19, x7, x31, 0x40, 0x8000, 0x9, x3, 40, x4) +// rs1==x8, rs2==x10, rd==x9, +// opcode: sra ; op1:x8; op2:x10; dest:x9; op1val:0x0; op2val:0x0 +TEST_RR_OP(sra, x9, x8, x10, 0x0, 0x0, 0x0, x1, 22*XLEN/8, x2) inst_23: -// rs1==x21, rs2==x26, rd==x23, rs1_val == 65536, -// opcode: sra ; op1:x21; op2:x26; dest:x23; op1val:0x10000; op2val:0x3 -TEST_RR_OP(sra, x23, x21, x26, 0x2000, 0x10000, 0x3, x3, 48, x4) +// rs1==x10, rs2==x9, rd==x8, +// opcode: sra ; op1:x10; op2:x9; dest:x8; op1val:0x0; op2val:0x0 +TEST_RR_OP(sra, x8, x10, x9, 0x0, 0x0, 0x0, x1, 23*XLEN/8, x2) inst_24: -// rs1==x10, rs2==x11, rd==x29, rs1_val == 131072, -// opcode: sra ; op1:x10; op2:x11; dest:x29; op1val:0x20000; op2val:0x3 -TEST_RR_OP(sra, x29, x10, x11, 0x4000, 0x20000, 0x3, x3, 56, x4) +// rs1==x6, rs2==x5, rd==x7, +// opcode: sra ; op1:x6; op2:x5; dest:x7; op1val:0x0; op2val:0x0 +TEST_RR_OP(sra, x7, x6, x5, 0x0, 0x0, 0x0, x1, 24*XLEN/8, x2) +RVTEST_SIGBASE(x8,signature_x8_0) inst_25: -// rs1==x19, rs2==x2, rd==x27, rs1_val == 262144, -// opcode: sra ; op1:x19; op2:x2; dest:x27; op1val:0x40000; op2val:0x8 -TEST_RR_OP(sra, x27, x19, x2, 0x400, 0x40000, 0x8, x3, 64, x4) +// rs1==x5, rs2==x7, rd==x6, +// opcode: sra ; op1:x5; op2:x7; dest:x6; op1val:0x0; op2val:0x0 +TEST_RR_OP(sra, x6, x5, x7, 0x0, 0x0, 0x0, x8, 0*XLEN/8, x9) inst_26: -// rs1==x12, rs2==x6, rd==x17, rs1_val == 524288, -// opcode: sra ; op1:x12; op2:x6; dest:x17; op1val:0x80000; op2val:0x7 -TEST_RR_OP(sra, x17, x12, x6, 0x1000, 0x80000, 0x7, x3, 72, x4) +// rs1==x7, rs2==x6, rd==x5, +// opcode: sra ; op1:x7; op2:x6; dest:x5; op1val:0x0; op2val:0x0 +TEST_RR_OP(sra, x5, x7, x6, 0x0, 0x0, 0x0, x8, 1*XLEN/8, x9) inst_27: -// rs1==x5, rs2==x14, rd==x22, rs1_val == 1048576, rs2_val == 32 -// opcode: sra ; op1:x5; op2:x14; dest:x22; op1val:0x100000; op2val:0x20 -TEST_RR_OP(sra, x22, x5, x14, 0x0, 0x100000, 0x20, x3, 80, x4) +// rs1==x3, rs2==x2, rd==x4, +// opcode: sra ; op1:x3; op2:x2; dest:x4; op1val:0x0; op2val:0x0 +TEST_RR_OP(sra, x4, x3, x2, 0x0, 0x0, 0x0, x8, 2*XLEN/8, x9) inst_28: -// rs1==x6, rs2==x9, rd==x16, rs1_val == 2097152, -// opcode: sra ; op1:x6; op2:x9; dest:x16; op1val:0x200000; op2val:0x4 -TEST_RR_OP(sra, x16, x6, x9, 0x20000, 0x200000, 0x4, x3, 88, x4) +// rs1==x2, rs2==x4, rd==x3, +// opcode: sra ; op1:x2; op2:x4; dest:x3; op1val:0x0; op2val:0x0 +TEST_RR_OP(sra, x3, x2, x4, 0x0, 0x0, 0x0, x8, 3*XLEN/8, x9) inst_29: -// rs1==x30, rs2==x25, rd==x5, rs1_val == 4194304, -// opcode: sra ; op1:x30; op2:x25; dest:x5; op1val:0x400000; op2val:0x2a -TEST_RR_OP(sra, x5, x30, x25, 0x0, 0x400000, 0x2a, x3, 96, x4) +// rs1==x4, rs2==x3, rd==x2, +// opcode: sra ; op1:x4; op2:x3; dest:x2; op1val:0x0; op2val:0x0 +TEST_RR_OP(sra, x2, x4, x3, 0x0, 0x0, 0x0, x8, 4*XLEN/8, x9) inst_30: -// rs1==x28, rs2==x20, rd==x15, rs1_val == 8388608, rs2_val == 21 -// opcode: sra ; op1:x28; op2:x20; dest:x15; op1val:0x800000; op2val:0x15 -TEST_RR_OP(sra, x15, x28, x20, 0x4, 0x800000, 0x15, x3, 104, x4) +// rs1==x1, +// opcode: sra ; op1:x1; op2:x30; dest:x31; op1val:0x0; op2val:0x0 +TEST_RR_OP(sra, x31, x1, x30, 0x0, 0x0, 0x0, x8, 5*XLEN/8, x9) inst_31: -// rs1==x11, rs2==x17, rd==x25, rs1_val == 16777216, -// opcode: sra ; op1:x11; op2:x17; dest:x25; op1val:0x1000000; op2val:0x15 -TEST_RR_OP(sra, x25, x11, x17, 0x8, 0x1000000, 0x15, x3, 112, x1) +// rs1==x0, +// opcode: sra ; op1:x0; op2:x30; dest:x31; op1val:0x0; op2val:0x0 +TEST_RR_OP(sra, x31, x0, x30, 0x0, 0x0, 0x0, x8, 6*XLEN/8, x9) inst_32: -// rs1_val == 33554432, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x2000000; op2val:0x1f -TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x2000000, 0x1f, x3, 120, x1) +// rs2==x1, +// opcode: sra ; op1:x30; op2:x1; dest:x31; op1val:0x0; op2val:0x0 +TEST_RR_OP(sra, x31, x30, x1, 0x0, 0x0, 0x0, x8, 7*XLEN/8, x9) inst_33: -// rs1_val == 67108864, rs2_val == 16 -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x4000000; op2val:0x10 -TEST_RR_OP(sra, x12, x10, x11, 0x400, 0x4000000, 0x10, x3, 128, x1) +// rs2==x0, +// opcode: sra ; op1:x30; op2:x0; dest:x31; op1val:0x0; op2val:0x0 +TEST_RR_OP(sra, x31, x30, x0, 0x0, 0x0, 0x0, x8, 8*XLEN/8, x9) inst_34: -// rs1_val == 134217728, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x8000000; op2val:0x2 -TEST_RR_OP(sra, x12, x10, x11, 0x2000000, 0x8000000, 0x2, x3, 136, x1) +// rd==x1, +// opcode: sra ; op1:x31; op2:x30; dest:x1; op1val:0x0; op2val:0x0 +TEST_RR_OP(sra, x1, x31, x30, 0x0, 0x0, 0x0, x8, 9*XLEN/8, x9) inst_35: -// rs1_val == 268435456, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x10000000; op2val:0xd -TEST_RR_OP(sra, x12, x10, x11, 0x8000, 0x10000000, 0xd, x3, 144, x1) +// rd==x0, +// opcode: sra ; op1:x31; op2:x30; dest:x0; op1val:0x0; op2val:0x0 +TEST_RR_OP(sra, x0, x31, x30, 0, 0x0, 0x0, x8, 10*XLEN/8, x9) inst_36: -// rs1_val == 536870912, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x20000000; op2val:0x3 -TEST_RR_OP(sra, x12, x10, x11, 0x4000000, 0x20000000, 0x3, x3, 152, x1) - -inst_37: -// rs1_val == 1073741824, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x40000000; op2val:0xc -TEST_RR_OP(sra, x12, x10, x11, 0x40000, 0x40000000, 0xc, x3, 160, x1) - -inst_38: -// rs1_val == 2147483648, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x80000000; op2val:0xb -TEST_RR_OP(sra, x12, x10, x11, 0x100000, 0x80000000, 0xb, x3, 168, x1) - -inst_39: -// rs1_val == 8589934592, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x200000000; op2val:0xa -TEST_RR_OP(sra, x12, x10, x11, 0x800000, 0x200000000, 0xa, x3, 176, x1) - -inst_40: -// rs1_val == 17179869184, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x400000000; op2val:0xe -TEST_RR_OP(sra, x12, x10, x11, 0x100000, 0x400000000, 0xe, x3, 184, x1) - -inst_41: -// rs1_val == 34359738368, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x800000000; op2val:0xf -TEST_RR_OP(sra, x12, x10, x11, 0x100000, 0x800000000, 0xf, x3, 192, x1) - -inst_42: -// rs1_val == 68719476736, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x1000000000; op2val:0x20 -TEST_RR_OP(sra, x12, x10, x11, 0x10, 0x1000000000, 0x20, x3, 200, x1) - -inst_43: -// rs1_val == 137438953472, rs2_val == 47 -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x2000000000; op2val:0x2f -TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x2000000000, 0x2f, x3, 208, x1) - -inst_44: -// rs1_val == 274877906944, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x4000000000; op2val:0x2a -TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x4000000000, 0x2a, x3, 216, x1) - -inst_45: -// rs1_val == 549755813888, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x8000000000; op2val:0x10 -TEST_RR_OP(sra, x12, x10, x11, 0x800000, 0x8000000000, 0x10, x3, 224, x1) - -inst_46: -// rs1_val == 1099511627776, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x10000000000; op2val:0xc -TEST_RR_OP(sra, x12, x10, x11, 0x10000000, 0x10000000000, 0xc, x3, 232, x1) - -inst_47: -// rs1_val == 2199023255552, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x20000000000; op2val:0x2a -TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x20000000000, 0x2a, x3, 240, x1) - -inst_48: -// rs1_val == 4398046511104, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x40000000000; op2val:0x5 -TEST_RR_OP(sra, x12, x10, x11, 0x2000000000, 0x40000000000, 0x5, x3, 248, x1) - -inst_49: -// rs1_val == 8796093022208, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x80000000000; op2val:0x8 -TEST_RR_OP(sra, x12, x10, x11, 0x800000000, 0x80000000000, 0x8, x3, 256, x1) - -inst_50: -// rs1_val == 17592186044416, rs2_val == 55 -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x100000000000; op2val:0x37 -TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x100000000000, 0x37, x3, 264, x1) - -inst_51: -// rs1_val == 35184372088832, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x200000000000; op2val:0x37 -TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x200000000000, 0x37, x3, 272, x1) - -inst_52: -// rs1_val == 70368744177664, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x400000000000; op2val:0xc -TEST_RR_OP(sra, x12, x10, x11, 0x400000000, 0x400000000000, 0xc, x3, 280, x1) - -inst_53: -// rs1_val == 140737488355328, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x800000000000; op2val:0x2a -TEST_RR_OP(sra, x12, x10, x11, 0x20, 0x800000000000, 0x2a, x3, 288, x1) - -inst_54: -// rs1_val == 281474976710656, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x1000000000000; op2val:0x2a -TEST_RR_OP(sra, x12, x10, x11, 0x40, 0x1000000000000, 0x2a, x3, 296, x1) - -inst_55: -// rs1_val == 562949953421312, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x2000000000000; op2val:0xe -TEST_RR_OP(sra, x12, x10, x11, 0x800000000, 0x2000000000000, 0xe, x3, 304, x1) - -inst_56: -// rs1_val == 1125899906842624, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x4000000000000; op2val:0xc -TEST_RR_OP(sra, x12, x10, x11, 0x4000000000, 0x4000000000000, 0xc, x3, 312, x1) - -inst_57: -// rs1_val == 2251799813685248, rs2_val == 61 -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x8000000000000; op2val:0x3d -TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x8000000000000, 0x3d, x3, 320, x1) - -inst_58: -// rs1_val == 4503599627370496, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x10000000000000; op2val:0xc -TEST_RR_OP(sra, x12, x10, x11, 0x10000000000, 0x10000000000000, 0xc, x3, 328, x1) - -inst_59: -// rs1_val == 9007199254740992, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x20000000000000; op2val:0xe -TEST_RR_OP(sra, x12, x10, x11, 0x8000000000, 0x20000000000000, 0xe, x3, 336, x1) - -inst_60: -// rs1_val == 18014398509481984, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x40000000000000; op2val:0x3d -TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x40000000000000, 0x3d, x3, 344, x1) - -inst_61: -// rs1_val == 36028797018963968, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x80000000000000; op2val:0x15 -TEST_RR_OP(sra, x12, x10, x11, 0x400000000, 0x80000000000000, 0x15, x3, 352, x1) - -inst_62: -// rs1_val == 72057594037927936, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x100000000000000; op2val:0x4 -TEST_RR_OP(sra, x12, x10, x11, 0x10000000000000, 0x100000000000000, 0x4, x3, 360, x1) - -inst_63: -// rs1_val == 144115188075855872, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x200000000000000; op2val:0x1 -TEST_RR_OP(sra, x12, x10, x11, 0x100000000000000, 0x200000000000000, 0x1, x3, 368, x1) - -inst_64: -// rs1_val == 288230376151711744, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x400000000000000; op2val:0x3d -TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x400000000000000, 0x3d, x3, 376, x1) - -inst_65: -// rs1_val == 576460752303423488, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x800000000000000; op2val:0x3 -TEST_RR_OP(sra, x12, x10, x11, 0x100000000000000, 0x800000000000000, 0x3, x3, 384, x1) - -inst_66: -// rs1_val == 1152921504606846976, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x1000000000000000; op2val:0x10 -TEST_RR_OP(sra, x12, x10, x11, 0x100000000000, 0x1000000000000000, 0x10, x3, 392, x1) - -inst_67: -// rs1_val == 2305843009213693952, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x2000000000000000; op2val:0x2f -TEST_RR_OP(sra, x12, x10, x11, 0x4000, 0x2000000000000000, 0x2f, x3, 400, x1) - -inst_68: -// rs1_val == 4611686018427387904, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x4000000000000000; op2val:0x12 -TEST_RR_OP(sra, x12, x10, x11, 0x100000000000, 0x4000000000000000, 0x12, x3, 408, x1) - -inst_69: -// rs1_val == -2, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x2; op2val:0x3d -TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x2, 0x3d, x3, 416, x1) - -inst_70: -// rs1_val == -3, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x3; op2val:0x10 -TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x3, 0x10, x3, 424, x1) - -inst_71: -// rs1_val == -5, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x5; op2val:0x15 -TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x5, 0x15, x3, 432, x1) - -inst_72: -// rs1_val == -9, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x9; op2val:0x2 -TEST_RR_OP(sra, x12, x10, x11, -0x3, -0x9, 0x2, x3, 440, x1) - -inst_73: -// rs1_val == -17, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x11; op2val:0xa -TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x11, 0xa, x3, 448, x1) - -inst_74: -// rs1_val == -33, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x21; op2val:0x20 -TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x21, 0x20, x3, 456, x1) - -inst_75: -// rs1_val == -65, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x41; op2val:0x0 -TEST_RR_OP(sra, x12, x10, x11, -0x41, -0x41, 0x0, x3, 464, x1) - -inst_76: -// rs1_val == -129, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x81; op2val:0x7 -TEST_RR_OP(sra, x12, x10, x11, -0x2, -0x81, 0x7, x3, 472, x1) - -inst_77: -// rs1_val == -257, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x101; op2val:0x7 -TEST_RR_OP(sra, x12, x10, x11, -0x3, -0x101, 0x7, x3, 480, x1) - -inst_78: -// rs1_val == -513, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x201; op2val:0x3f -TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x201, 0x3f, x3, 488, x1) - -inst_79: -// rs1_val == -1025, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x401; op2val:0x37 -TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x401, 0x37, x3, 496, x1) - -inst_80: -// rs1_val == -2049, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x801; op2val:0x8 -TEST_RR_OP(sra, x12, x10, x11, -0x9, -0x801, 0x8, x3, 504, x1) - -inst_81: -// rs1_val == -4097, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x1001; op2val:0x8 -TEST_RR_OP(sra, x12, x10, x11, -0x11, -0x1001, 0x8, x3, 512, x1) - -inst_82: -// rs1_val == -8193, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x2001; op2val:0x7 -TEST_RR_OP(sra, x12, x10, x11, -0x41, -0x2001, 0x7, x3, 520, x1) - -inst_83: -// rs1_val == -16385, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x4001; op2val:0x3 -TEST_RR_OP(sra, x12, x10, x11, -0x801, -0x4001, 0x3, x3, 528, x1) - -inst_84: -// rs1_val == -32769, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x8001; op2val:0xc -TEST_RR_OP(sra, x12, x10, x11, -0x9, -0x8001, 0xc, x3, 536, x1) - -inst_85: -// rs1_val == -65537, rs2_val == 62 -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x10001; op2val:0x3e -TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x10001, 0x3e, x3, 544, x1) - -inst_86: -// rs1_val == -131073, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x20001; op2val:0x20 -TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x20001, 0x20, x3, 552, x1) - -inst_87: -// rs1_val == -262145, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x40001; op2val:0xc -TEST_RR_OP(sra, x12, x10, x11, -0x41, -0x40001, 0xc, x3, 560, x1) - -inst_88: -// rs1_val == -36028797018963969, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x80000000000001; op2val:0x6 -TEST_RR_OP(sra, x12, x10, x11, -0x2000000000001, -0x80000000000001, 0x6, x3, 568, x1) - -inst_89: -// rs1_val == -72057594037927937, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x100000000000001; op2val:0xe -TEST_RR_OP(sra, x12, x10, x11, -0x40000000001, -0x100000000000001, 0xe, x3, 576, x1) - -inst_90: -// rs1_val == -144115188075855873, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x200000000000001; op2val:0x5 -TEST_RR_OP(sra, x12, x10, x11, -0x10000000000001, -0x200000000000001, 0x5, x3, 584, x1) - -inst_91: -// rs1_val == -288230376151711745, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x400000000000001; op2val:0x2 -TEST_RR_OP(sra, x12, x10, x11, -0x100000000000001, -0x400000000000001, 0x2, x3, 592, x1) - -inst_92: -// rs1_val == -576460752303423489, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x800000000000001; op2val:0x7 -TEST_RR_OP(sra, x12, x10, x11, -0x10000000000001, -0x800000000000001, 0x7, x3, 600, x1) - -inst_93: -// rs1_val == -1152921504606846977, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x1000000000000001; op2val:0x4 -TEST_RR_OP(sra, x12, x10, x11, -0x100000000000001, -0x1000000000000001, 0x4, x3, 608, x1) - -inst_94: -// rs1_val == -2305843009213693953, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x2000000000000001; op2val:0x3 -TEST_RR_OP(sra, x12, x10, x11, -0x400000000000001, -0x2000000000000001, 0x3, x3, 616, x1) - -inst_95: -// rs1_val == -4611686018427387905, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x4000000000000001; op2val:0x1 -TEST_RR_OP(sra, x12, x10, x11, -0x2000000000000001, -0x4000000000000001, 0x1, x3, 624, x1) - -inst_96: -// rs1_val == 6148914691236517205, rs1_val==6148914691236517205 -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x5555555555555555; op2val:0x9 -TEST_RR_OP(sra, x12, x10, x11, 0x2aaaaaaaaaaaaa, 0x5555555555555555, 0x9, x3, 632, x1) - -inst_97: -// rs1_val == -6148914691236517206, rs1_val==-6148914691236517206 -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x5555555555555556; op2val:0x7 -TEST_RR_OP(sra, x12, x10, x11, -0xaaaaaaaaaaaaab, -0x5555555555555556, 0x7, x3, 640, x1) - -inst_98: -// rs1_val==3, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x3; op2val:0x1 -TEST_RR_OP(sra, x12, x10, x11, 0x1, 0x3, 0x1, x3, 648, x1) - -inst_99: -// rs1_val==5, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x5; op2val:0x20 -TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x5, 0x20, x3, 656, x1) - -inst_100: -// rs1_val==7378697629483820646, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x6666666666666666; op2val:0xc -TEST_RR_OP(sra, x12, x10, x11, 0x6666666666666, 0x6666666666666666, 0xc, x3, 664, x1) - -inst_101: -// rs1_val==-3037000499, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0xb504f333; op2val:0xb -TEST_RR_OP(sra, x12, x10, x11, -0x16a09f, -0xb504f333, 0xb, x3, 672, x1) - -inst_102: -// rs1_val==3037000499, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0xb504f333; op2val:0x1f -TEST_RR_OP(sra, x12, x10, x11, 0x1, 0xb504f333, 0x1f, x3, 680, x1) - -inst_103: -// rs1_val==6148914691236517204, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x5555555555555554; op2val:0x37 -TEST_RR_OP(sra, x12, x10, x11, 0xaa, 0x5555555555555554, 0x37, x3, 688, x1) - -inst_104: -// rs1_val==3689348814741910322, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x3333333333333332; op2val:0x20 -TEST_RR_OP(sra, x12, x10, x11, 0x33333333, 0x3333333333333332, 0x20, x3, 696, x1) - -inst_105: -// rs1_val==7378697629483820645, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x6666666666666665; op2val:0x9 -TEST_RR_OP(sra, x12, x10, x11, 0x33333333333333, 0x6666666666666665, 0x9, x3, 704, x1) - -inst_106: -// rs1_val==3037000498, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0xb504f332; op2val:0x15 -TEST_RR_OP(sra, x12, x10, x11, 0x5a8, 0xb504f332, 0x15, x3, 712, x1) - -inst_107: -// rs1_val==6148914691236517206, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x5555555555555556; op2val:0xe -TEST_RR_OP(sra, x12, x10, x11, 0x1555555555555, 0x5555555555555556, 0xe, x3, 720, x1) - -inst_108: -// rs1_val==-6148914691236517205, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x5555555555555555; op2val:0xe -TEST_RR_OP(sra, x12, x10, x11, -0x1555555555556, -0x5555555555555555, 0xe, x3, 728, x1) - -inst_109: -// rs1_val==6, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x6; op2val:0x3e -TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x6, 0x3e, x3, 736, x1) - -inst_110: -// rs1_val==3689348814741910324, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x3333333333333334; op2val:0x12 -TEST_RR_OP(sra, x12, x10, x11, 0xccccccccccc, 0x3333333333333334, 0x12, x3, 744, x1) - -inst_111: -// rs1_val==7378697629483820647, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x6666666666666667; op2val:0xe -TEST_RR_OP(sra, x12, x10, x11, 0x1999999999999, 0x6666666666666667, 0xe, x3, 752, x1) - -inst_112: -// rs1_val==-3037000498, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0xb504f332; op2val:0x11 -TEST_RR_OP(sra, x12, x10, x11, -0x5a83, -0xb504f332, 0x11, x3, 760, x1) - -inst_113: -// rs1_val==3037000500, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0xb504f334; op2val:0x2a -TEST_RR_OP(sra, x12, x10, x11, 0x0, 0xb504f334, 0x2a, x3, 768, x1) - -inst_114: -// rs2_val == 59, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x800000000000001; op2val:0x3b -TEST_RR_OP(sra, x12, x10, x11, -0x2, -0x800000000000001, 0x3b, x3, 776, x1) - -inst_115: -// rs1_val == -524289, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x80001; op2val:0x20 -TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x80001, 0x20, x3, 784, x1) - -inst_116: -// rs1_val == -1048577, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x100001; op2val:0x11 -TEST_RR_OP(sra, x12, x10, x11, -0x9, -0x100001, 0x11, x3, 792, x1) - -inst_117: -// rs1_val == -2097153, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x200001; op2val:0x5 -TEST_RR_OP(sra, x12, x10, x11, -0x10001, -0x200001, 0x5, x3, 800, x1) - -inst_118: -// rs1_val == -4194305, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x400001; op2val:0x20 -TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x400001, 0x20, x3, 808, x1) - -inst_119: -// rs1_val == -8388609, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x800001; op2val:0xc -TEST_RR_OP(sra, x12, x10, x11, -0x801, -0x800001, 0xc, x3, 816, x1) - -inst_120: -// rs1_val == -16777217, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x1000001; op2val:0xa -TEST_RR_OP(sra, x12, x10, x11, -0x4001, -0x1000001, 0xa, x3, 824, x1) - -inst_121: -// rs1_val == -33554433, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x2000001; op2val:0xc -TEST_RR_OP(sra, x12, x10, x11, -0x2001, -0x2000001, 0xc, x3, 832, x1) - -inst_122: -// rs1_val == -67108865, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x4000001; op2val:0x3 -TEST_RR_OP(sra, x12, x10, x11, -0x800001, -0x4000001, 0x3, x3, 840, x1) - -inst_123: -// rs1_val == -134217729, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x8000001; op2val:0x3d -TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x8000001, 0x3d, x3, 848, x1) - -inst_124: -// rs1_val == -268435457, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x10000001; op2val:0x11 -TEST_RR_OP(sra, x12, x10, x11, -0x801, -0x10000001, 0x11, x3, 856, x1) - -inst_125: -// rs1_val == -536870913, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x20000001; op2val:0x2f -TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x20000001, 0x2f, x3, 864, x1) - -inst_126: -// rs1_val == -1073741825, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x40000001; op2val:0x9 -TEST_RR_OP(sra, x12, x10, x11, -0x200001, -0x40000001, 0x9, x3, 872, x1) - -inst_127: -// rs1_val == -2147483649, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x80000001; op2val:0xd -TEST_RR_OP(sra, x12, x10, x11, -0x40001, -0x80000001, 0xd, x3, 880, x1) - -inst_128: -// rs1_val == -8589934593, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x200000001; op2val:0xa -TEST_RR_OP(sra, x12, x10, x11, -0x800001, -0x200000001, 0xa, x3, 888, x1) - -inst_129: -// rs1_val == -17179869185, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x400000001; op2val:0x3b -TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x400000001, 0x3b, x3, 896, x1) - -inst_130: -// rs1_val == -68719476737, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x1000000001; op2val:0xe -TEST_RR_OP(sra, x12, x10, x11, -0x400001, -0x1000000001, 0xe, x3, 904, x1) - -inst_131: -// rs1_val == -137438953473, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x2000000001; op2val:0x2f -TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x2000000001, 0x2f, x3, 912, x1) - -inst_132: -// rs1_val == -274877906945, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x4000000001; op2val:0xa -TEST_RR_OP(sra, x12, x10, x11, -0x10000001, -0x4000000001, 0xa, x3, 920, x1) - -inst_133: -// rs1_val == -549755813889, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x8000000001; op2val:0x37 -TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x8000000001, 0x37, x3, 928, x1) - -inst_134: -// rs1_val == -1099511627777, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x10000000001; op2val:0x9 -TEST_RR_OP(sra, x12, x10, x11, -0x80000001, -0x10000000001, 0x9, x3, 936, x1) - -inst_135: -// rs1_val == -2199023255553, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x20000000001; op2val:0xd -TEST_RR_OP(sra, x12, x10, x11, -0x10000001, -0x20000000001, 0xd, x3, 944, x1) - -inst_136: -// rs1_val == -4398046511105, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x40000000001; op2val:0x1f -TEST_RR_OP(sra, x12, x10, x11, -0x801, -0x40000000001, 0x1f, x3, 952, x1) - -inst_137: -// rs1_val == -8796093022209, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x80000000001; op2val:0x12 -TEST_RR_OP(sra, x12, x10, x11, -0x2000001, -0x80000000001, 0x12, x3, 960, x1) - -inst_138: -// rs1_val == -17592186044417, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x100000000001; op2val:0x7 -TEST_RR_OP(sra, x12, x10, x11, -0x2000000001, -0x100000000001, 0x7, x3, 968, x1) - -inst_139: -// rs1_val == -35184372088833, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x200000000001; op2val:0x1 -TEST_RR_OP(sra, x12, x10, x11, -0x100000000001, -0x200000000001, 0x1, x3, 976, x1) - -inst_140: -// rs1_val == -70368744177665, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x400000000001; op2val:0xf -TEST_RR_OP(sra, x12, x10, x11, -0x80000001, -0x400000000001, 0xf, x3, 984, x1) - -inst_141: -// rs1_val == -140737488355329, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x800000000001; op2val:0xb -TEST_RR_OP(sra, x12, x10, x11, -0x1000000001, -0x800000000001, 0xb, x3, 992, x1) - -inst_142: -// rs1_val == -281474976710657, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x1000000000001; op2val:0x3 -TEST_RR_OP(sra, x12, x10, x11, -0x200000000001, -0x1000000000001, 0x3, x3, 1000, x1) - -inst_143: -// rs1_val == -562949953421313, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x2000000000001; op2val:0x3f -TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x2000000000001, 0x3f, x3, 1008, x1) - -inst_144: -// rs1_val == -1125899906842625, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x4000000000001; op2val:0x7 -TEST_RR_OP(sra, x12, x10, x11, -0x80000000001, -0x4000000000001, 0x7, x3, 1016, x1) - -inst_145: -// rs1_val == -2251799813685249, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x8000000000001; op2val:0x1 -TEST_RR_OP(sra, x12, x10, x11, -0x4000000000001, -0x8000000000001, 0x1, x3, 1024, x1) - -inst_146: -// rs1_val == -4503599627370497, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x10000000000001; op2val:0xf -TEST_RR_OP(sra, x12, x10, x11, -0x2000000001, -0x10000000000001, 0xf, x3, 1032, x1) - -inst_147: -// rs1_val == -9007199254740993, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x20000000000001; op2val:0xa -TEST_RR_OP(sra, x12, x10, x11, -0x80000000001, -0x20000000000001, 0xa, x3, 1040, x1) - -inst_148: -// rs1_val == -18014398509481985, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x40000000000001; op2val:0xe -TEST_RR_OP(sra, x12, x10, x11, -0x10000000001, -0x40000000000001, 0xe, x3, 1048, x1) - -inst_149: -// rs1_val < 0 and rs2_val > 0 and rs2_val < xlen, rs1_val == -34359738369 -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x800000001; op2val:0x7 -TEST_RR_OP(sra, x12, x10, x11, -0x10000001, -0x800000001, 0x7, x3, 1056, x1) - -inst_150: -// rs1_val < 0 and rs2_val == 0, rs1_val == -4294967297 -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x100000001; op2val:0x0 -TEST_RR_OP(sra, x12, x10, x11, -0x100000001, -0x100000001, 0x0, x3, 1064, x1) - -inst_151: -// rs1_val == (2**(xlen-1)-1) and rs2_val >= 0 and rs2_val < xlen, rs1_val == 9223372036854775807 -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x7fffffffffffffff; op2val:0x3 -TEST_RR_OP(sra, x12, x10, x11, 0xfffffffffffffff, 0x7fffffffffffffff, 0x3, x3, 1072, x1) - -inst_152: -// rs1_val == 16, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x10; op2val:0x6 -TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x10, 0x6, x3, 1080, x1) - -inst_153: -// rs1_val == 512, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x200; op2val:0xb -TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x200, 0xb, x3, 1088, x1) +// rs1_val < 0 and rs2_val == 0, +// opcode: sra ; op1:x30; op2:x29; dest:x31; op1val:-0xb504f332; op2val:0x0 +TEST_RR_OP(sra, x31, x30, x29, -0xb504f332, -0xb504f332, 0x0, x8, 11*XLEN/8, x9) #endif @@ -809,50 +226,50 @@ RVMODEL_HALT RVTEST_DATA_BEGIN .align 4 - rvtest_data: .word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab RVTEST_DATA_END - RVMODEL_DATA_BEGIN rvtest_sig_begin: sig_begin_canary: CANARY; -signature_x9_0: - .fill 0*(XLEN/32),4,0xdeadbeef +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef -signature_x9_1: - .fill 17*(XLEN/32),4,0xdeadbeef +signature_x1_1: + .fill 25*((XLEN/8)/4),4,0xdeadbeef -signature_x3_0: - .fill 137*(XLEN/32),4,0xdeadbeef -#ifdef rvtest_mtrap_routine +signature_x8_0: + .fill 12*((XLEN/8)/4),4,0xdeadbeef +#ifdef rvtest_mtrap_routine tsig_begin_canary: CANARY; + mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef + .fill 64*XLEN/32,4,0xdeadbeef + tsig_end_canary: CANARY; - #endif #ifdef rvtest_gpr_save gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef + .fill 32*XLEN/32,4,0xdeadbeef #endif + sig_end_canary: CANARY; rvtest_sig_end: diff --git a/riscv-test-suite/rv64i_m/I/src/sraw-01.S b/riscv-test-suite/rv64i_m/I/src/sraw-01.S index 003d45517..9e813d4bd 100644 --- a/riscv-test-suite/rv64i_m/I/src/sraw-01.S +++ b/riscv-test-suite/rv64i_m/I/src/sraw-01.S @@ -1,11 +1,13 @@ // ----------- -// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg) -// version : 0.4.1 -// timestamp : Wed Dec 16 03:45:17 2020 GMT +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Tue Nov 19 02:34:25 2024 GMT // usage : riscv_ctg \ -// -- cgf ('/scratch/git-repo/incoresemi/riscv-compliance/riscv_ctg/sample_cgfs/dataset.cgf', '/scratch/git-repo/incoresemi/riscv-compliance/riscv_ctg/sample_cgfs/rv64i.cgf') \ -// -- xlen 64 \ +// -- cgf // --cgf /workspaces/riscv-arch-test/coverage/dataset.cgf \ +// --cgf /workspaces/riscv-arch-test/coverage/i/rv64i.cgf \ + \ +// -- xlen 64 \ // ----------- // // ----------- @@ -13,7 +15,7 @@ // SPDX-License-Identifier: BSD-3-Clause // ----------- // -// This assembly file tests the sraw instruction of the RISC-V i extension for the sraw covergroup. +// This assembly file tests the sraw instruction of the RISC-V RV64 extension for the sraw covergroup. // #include "model_test.h" #include "arch_test.h" @@ -27,780 +29,190 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*);def TEST_CASE_1=True;",sraw) +RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*);def TEST_CASE_1=True;",sraw) -RVTEST_SIGBASE( x3,signature_x3_1) +RVTEST_SIGBASE(x1,signature_x1_1) inst_0: -// rs1 == rs2 != rd, rs1==x13, rs2==x13, rd==x2, rs1_val < 0 and rs2_val > 0 and rs2_val < xlen, rs1_val == -257, rs2_val == 1 -// opcode: sraw ; op1:x13; op2:x13; dest:x2; op1val:-0x101; op2val:-0x101 -TEST_RR_OP(sraw, x2, x13, x13, -0x1, -0x101, -0x101, x3, 0, x14) +// rs1 == rs2 != rd, rs1==x30, rs2==x30, rd==x31, rs1_val < 0 and rs2_val == 0, +// opcode: sraw ; op1:x30; op2:x30; dest:x31; op1val:-0xb504f332; op2val:-0xb504f332 +TEST_RR_OP(sraw, x31, x30, x30, 0x12bec, -0xb504f332, -0xb504f332, x1, 0*XLEN/8, x2) inst_1: -// rs2 == rd != rs1, rs1==x5, rs2==x15, rd==x15, rs1_val > 0 and rs2_val > 0 and rs2_val < xlen, rs1_val == 4096 -// opcode: sraw ; op1:x5; op2:x15; dest:x15; op1val:0x1000; op2val:0x1f -TEST_RR_OP(sraw, x15, x5, x15, 0x0, 0x1000, 0x1f, x3, 8, x14) +// rs1 == rd != rs2, rs1==x29, rs2==x31, rd==x29, rs1_val < 0 and rs2_val > 0 and rs2_val < xlen, +// opcode: sraw ; op1:x29; op2:x31; dest:x29; op1val:-0xb504f332; op2val:0x1f +TEST_RR_OP(sraw, x29, x29, x31, 0x0, -0xb504f332, 0x1f, x1, 1*XLEN/8, x2) inst_2: -// rs1 == rs2 == rd, rs1==x6, rs2==x6, rd==x6, rs1_val < 0 and rs2_val == 0, rs1_val == -131073 -// opcode: sraw ; op1:x6; op2:x6; dest:x6; op1val:-0x20001; op2val:-0x20001 -TEST_RR_OP(sraw, x6, x6, x6, -0x1, -0x20001, -0x20001, x3, 16, x14) +// rs1 == rs2 == rd, rs1==x28, rs2==x28, rd==x28, rs1_val == (-2**(xlen-1)) and rs2_val >= 0 and rs2_val < xlen, +// opcode: sraw ; op1:x28; op2:x28; dest:x28; op1val:-0x8000000000000000; op2val:-0x8000000000000000 +TEST_RR_OP(sraw, x28, x28, x28, 0x0, -0x8000000000000000, -0x8000000000000000, x1, 2*XLEN/8, x2) inst_3: -// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==x25, rs2==x26, rd==x13, rs1_val > 0 and rs2_val == 0, rs1_val == 524288 -// opcode: sraw ; op1:x25; op2:x26; dest:x13; op1val:0x80000; op2val:0x0 -TEST_RR_OP(sraw, x13, x25, x26, 0x80000, 0x80000, 0x0, x3, 24, x14) +// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==x31, rs2==x29, rd==x30, rs1_val == (2**(xlen-1)-1) and rs2_val >= 0 and rs2_val < xlen, rs1_val > 0 and rs2_val > 0 and rs2_val < xlen +// opcode: sraw ; op1:x31; op2:x29; dest:x30; op1val:0x7fffffffffffffff; op2val:0x1f +TEST_RR_OP(sraw, x30, x31, x29, -0x1, 0x7fffffffffffffff, 0x1f, x1, 3*XLEN/8, x2) inst_4: -// rs1 == rd != rs2, rs1==x23, rs2==x11, rd==x23, rs1_val == rs2_val and rs2_val > 0 and rs2_val < xlen, -// opcode: sraw ; op1:x23; op2:x11; dest:x23; op1val:0x9; op2val:0x9 -TEST_RR_OP(sraw, x23, x23, x11, 0x0, 0x9, 0x9, x3, 32, x14) +// rs2 == rd != rs1, rs1==x26, rs2==x27, rd==x27, rs1_val == 0 and rs2_val >= 0 and rs2_val < xlen, +// opcode: sraw ; op1:x26; op2:x27; dest:x27; op1val:0x0; op2val:0x1f +TEST_RR_OP(sraw, x27, x26, x27, 0x0, 0x0, 0x1f, x1, 4*XLEN/8, x2) inst_5: -// rs1==x9, rs2==x18, rd==x0, rs1_val == (-2**(xlen-1)) and rs2_val >= 0 and rs2_val < xlen, rs1_val == -9223372036854775808 -// opcode: sraw ; op1:x9; op2:x18; dest:x0; op1val:-0x8000000000000000; op2val:0xe -TEST_RR_OP(sraw, x0, x9, x18, 0, -0x8000000000000000, 0xe, x3, 40, x14) +// rs1==x27, rs2==x25, rd==x26, rs1_val == 1 and rs2_val >= 0 and rs2_val < xlen, +// opcode: sraw ; op1:x27; op2:x25; dest:x26; op1val:0x1; op2val:0x1f +TEST_RR_OP(sraw, x26, x27, x25, 0x0, 0x1, 0x1f, x1, 5*XLEN/8, x2) inst_6: -// rs1==x11, rs2==x27, rd==x9, rs1_val == 0 and rs2_val >= 0 and rs2_val < xlen, rs1_val==0 -// opcode: sraw ; op1:x11; op2:x27; dest:x9; op1val:0x0; op2val:0x13 -TEST_RR_OP(sraw, x9, x11, x27, 0x0, 0x0, 0x13, x3, 48, x14) +// rs1==x24, rs2==x26, rd==x25, rs1_val == rs2_val and rs2_val > 0 and rs2_val < xlen, +// opcode: sraw ; op1:x24; op2:x26; dest:x25; op1val:0x10; op2val:0x10 +TEST_RR_OP(sraw, x25, x24, x26, 0x0, 0x10, 0x10, x1, 6*XLEN/8, x2) inst_7: -// rs1==x30, rs2==x12, rd==x8, rs1_val == (2**(xlen-1)-1) and rs2_val >= 0 and rs2_val < xlen, rs1_val == 9223372036854775807, rs2_val == 21 -// opcode: sraw ; op1:x30; op2:x12; dest:x8; op1val:0x7fffffffffffffff; op2val:0x15 -TEST_RR_OP(sraw, x8, x30, x12, -0x1, 0x7fffffffffffffff, 0x15, x3, 56, x14) +// rs1==x25, rs2==x23, rd==x24, rs1_val > 0 and rs2_val == 0, +// opcode: sraw ; op1:x25; op2:x23; dest:x24; op1val:0xb504f334; op2val:0x0 +TEST_RR_OP(sraw, x24, x25, x23, -0x4afb0ccc, 0xb504f334, 0x0, x1, 7*XLEN/8, x2) inst_8: -// rs1==x29, rs2==x7, rd==x21, rs1_val == 1 and rs2_val >= 0 and rs2_val < xlen, rs1_val == 1 -// opcode: sraw ; op1:x29; op2:x7; dest:x21; op1val:0x1; op2val:0x0 -TEST_RR_OP(sraw, x21, x29, x7, 0x1, 0x1, 0x0, x3, 64, x14) +// rs1==x22, rs2==x24, rd==x23, +// opcode: sraw ; op1:x22; op2:x24; dest:x23; op1val:0x0; op2val:0x0 +TEST_RR_OP(sraw, x23, x22, x24, 0x0, 0x0, 0x0, x1, 8*XLEN/8, x2) inst_9: -// rs1==x0, rs2==x24, rd==x5, rs1_val == 2, rs1_val==2, rs2_val == 10 -// opcode: sraw ; op1:x0; op2:x24; dest:x5; op1val:0x0; op2val:0xa -TEST_RR_OP(sraw, x5, x0, x24, 0x0, 0x0, 0xa, x3, 72, x14) +// rs1==x23, rs2==x21, rd==x22, +// opcode: sraw ; op1:x23; op2:x21; dest:x22; op1val:0x0; op2val:0x0 +TEST_RR_OP(sraw, x22, x23, x21, 0x0, 0x0, 0x0, x1, 9*XLEN/8, x2) inst_10: -// rs1==x19, rs2==x22, rd==x27, rs1_val == 4, rs1_val==4 -// opcode: sraw ; op1:x19; op2:x22; dest:x27; op1val:0x4; op2val:0x13 -TEST_RR_OP(sraw, x27, x19, x22, 0x0, 0x4, 0x13, x3, 80, x14) +// rs1==x20, rs2==x22, rd==x21, +// opcode: sraw ; op1:x20; op2:x22; dest:x21; op1val:0x0; op2val:0x0 +TEST_RR_OP(sraw, x21, x20, x22, 0x0, 0x0, 0x0, x1, 10*XLEN/8, x2) inst_11: -// rs1==x17, rs2==x4, rd==x1, rs1_val == 8, -// opcode: sraw ; op1:x17; op2:x4; dest:x1; op1val:0x8; op2val:0x9 -TEST_RR_OP(sraw, x1, x17, x4, 0x0, 0x8, 0x9, x3, 88, x14) +// rs1==x21, rs2==x19, rd==x20, +// opcode: sraw ; op1:x21; op2:x19; dest:x20; op1val:0x0; op2val:0x0 +TEST_RR_OP(sraw, x20, x21, x19, 0x0, 0x0, 0x0, x1, 11*XLEN/8, x2) inst_12: -// rs1==x1, rs2==x25, rd==x31, rs1_val == 16, rs2_val == 23 -// opcode: sraw ; op1:x1; op2:x25; dest:x31; op1val:0x10; op2val:0x17 -TEST_RR_OP(sraw, x31, x1, x25, 0x0, 0x10, 0x17, x3, 96, x14) +// rs1==x18, rs2==x20, rd==x19, +// opcode: sraw ; op1:x18; op2:x20; dest:x19; op1val:0x0; op2val:0x0 +TEST_RR_OP(sraw, x19, x18, x20, 0x0, 0x0, 0x0, x1, 12*XLEN/8, x2) inst_13: -// rs1==x10, rs2==x9, rd==x30, rs1_val == 32, rs2_val == 15 -// opcode: sraw ; op1:x10; op2:x9; dest:x30; op1val:0x20; op2val:0xf -TEST_RR_OP(sraw, x30, x10, x9, 0x0, 0x20, 0xf, x3, 104, x14) +// rs1==x19, rs2==x17, rd==x18, +// opcode: sraw ; op1:x19; op2:x17; dest:x18; op1val:0x0; op2val:0x0 +TEST_RR_OP(sraw, x18, x19, x17, 0x0, 0x0, 0x0, x1, 13*XLEN/8, x2) inst_14: -// rs1==x16, rs2==x23, rd==x26, rs1_val == 64, -// opcode: sraw ; op1:x16; op2:x23; dest:x26; op1val:0x40; op2val:0x17 -TEST_RR_OP(sraw, x26, x16, x23, 0x0, 0x40, 0x17, x3, 112, x14) +// rs1==x16, rs2==x18, rd==x17, +// opcode: sraw ; op1:x16; op2:x18; dest:x17; op1val:0x0; op2val:0x0 +TEST_RR_OP(sraw, x17, x16, x18, 0x0, 0x0, 0x0, x1, 14*XLEN/8, x2) inst_15: -// rs1==x21, rs2==x8, rd==x28, rs1_val == 128, rs2_val == 4 -// opcode: sraw ; op1:x21; op2:x8; dest:x28; op1val:0x80; op2val:0x4 -TEST_RR_OP(sraw, x28, x21, x8, 0x8, 0x80, 0x4, x3, 120, x9) -RVTEST_SIGBASE( x6,signature_x6_0) +// rs1==x17, rs2==x15, rd==x16, +// opcode: sraw ; op1:x17; op2:x15; dest:x16; op1val:0x0; op2val:0x0 +TEST_RR_OP(sraw, x16, x17, x15, 0x0, 0x0, 0x0, x1, 15*XLEN/8, x2) inst_16: -// rs1==x20, rs2==x16, rd==x24, rs1_val == 256, -// opcode: sraw ; op1:x20; op2:x16; dest:x24; op1val:0x100; op2val:0xd -TEST_RR_OP(sraw, x24, x20, x16, 0x0, 0x100, 0xd, x6, 0, x9) +// rs1==x14, rs2==x16, rd==x15, +// opcode: sraw ; op1:x14; op2:x16; dest:x15; op1val:0x0; op2val:0x0 +TEST_RR_OP(sraw, x15, x14, x16, 0x0, 0x0, 0x0, x1, 16*XLEN/8, x2) inst_17: -// rs1==x27, rs2==x2, rd==x17, rs1_val == 512, -// opcode: sraw ; op1:x27; op2:x2; dest:x17; op1val:0x200; op2val:0xe -TEST_RR_OP(sraw, x17, x27, x2, 0x0, 0x200, 0xe, x6, 8, x9) +// rs1==x15, rs2==x13, rd==x14, +// opcode: sraw ; op1:x15; op2:x13; dest:x14; op1val:0x0; op2val:0x0 +TEST_RR_OP(sraw, x14, x15, x13, 0x0, 0x0, 0x0, x1, 17*XLEN/8, x2) inst_18: -// rs1==x15, rs2==x10, rd==x22, rs1_val == 1024, -// opcode: sraw ; op1:x15; op2:x10; dest:x22; op1val:0x400; op2val:0x5 -TEST_RR_OP(sraw, x22, x15, x10, 0x20, 0x400, 0x5, x6, 16, x9) +// rs1==x12, rs2==x14, rd==x13, +// opcode: sraw ; op1:x12; op2:x14; dest:x13; op1val:0x0; op2val:0x0 +TEST_RR_OP(sraw, x13, x12, x14, 0x0, 0x0, 0x0, x1, 18*XLEN/8, x2) inst_19: -// rs1==x7, rs2==x30, rd==x11, rs1_val == 2048, -// opcode: sraw ; op1:x7; op2:x30; dest:x11; op1val:0x800; op2val:0xa -TEST_RR_OP(sraw, x11, x7, x30, 0x2, 0x800, 0xa, x6, 24, x9) +// rs1==x13, rs2==x11, rd==x12, +// opcode: sraw ; op1:x13; op2:x11; dest:x12; op1val:0x0; op2val:0x0 +TEST_RR_OP(sraw, x12, x13, x11, 0x0, 0x0, 0x0, x1, 19*XLEN/8, x2) inst_20: -// rs1==x28, rs2==x1, rd==x25, rs1_val == 8192, rs2_val == 27 -// opcode: sraw ; op1:x28; op2:x1; dest:x25; op1val:0x2000; op2val:0x1b -TEST_RR_OP(sraw, x25, x28, x1, 0x0, 0x2000, 0x1b, x6, 32, x9) +// rs1==x10, rs2==x12, rd==x11, +// opcode: sraw ; op1:x10; op2:x12; dest:x11; op1val:0x0; op2val:0x0 +TEST_RR_OP(sraw, x11, x10, x12, 0x0, 0x0, 0x0, x1, 20*XLEN/8, x2) inst_21: -// rs1==x31, rs2==x0, rd==x12, rs1_val == 16384, rs2_val == 2 -// opcode: sraw ; op1:x31; op2:x0; dest:x12; op1val:0x4000; op2val:0x0 -TEST_RR_OP(sraw, x12, x31, x0, 0x4000, 0x4000, 0x0, x6, 40, x9) +// rs1==x11, rs2==x9, rd==x10, +// opcode: sraw ; op1:x11; op2:x9; dest:x10; op1val:0x0; op2val:0x0 +TEST_RR_OP(sraw, x10, x11, x9, 0x0, 0x0, 0x0, x1, 21*XLEN/8, x2) inst_22: -// rs1==x22, rs2==x29, rd==x20, rs1_val == 32768, -// opcode: sraw ; op1:x22; op2:x29; dest:x20; op1val:0x8000; op2val:0xb -TEST_RR_OP(sraw, x20, x22, x29, 0x10, 0x8000, 0xb, x6, 48, x9) +// rs1==x8, rs2==x10, rd==x9, +// opcode: sraw ; op1:x8; op2:x10; dest:x9; op1val:0x0; op2val:0x0 +TEST_RR_OP(sraw, x9, x8, x10, 0x0, 0x0, 0x0, x1, 22*XLEN/8, x2) inst_23: -// rs1==x14, rs2==x28, rd==x3, rs1_val == 65536, rs2_val == 16 -// opcode: sraw ; op1:x14; op2:x28; dest:x3; op1val:0x10000; op2val:0x10 -TEST_RR_OP(sraw, x3, x14, x28, 0x1, 0x10000, 0x10, x6, 56, x9) +// rs1==x9, rs2==x7, rd==x8, +// opcode: sraw ; op1:x9; op2:x7; dest:x8; op1val:0x0; op2val:0x0 +TEST_RR_OP(sraw, x8, x9, x7, 0x0, 0x0, 0x0, x1, 23*XLEN/8, x2) inst_24: -// rs1==x3, rs2==x21, rd==x29, rs1_val == 131072, -// opcode: sraw ; op1:x3; op2:x21; dest:x29; op1val:0x20000; op2val:0x13 -TEST_RR_OP(sraw, x29, x3, x21, 0x0, 0x20000, 0x13, x6, 64, x9) +// rs1==x6, rs2==x8, rd==x7, +// opcode: sraw ; op1:x6; op2:x8; dest:x7; op1val:0x0; op2val:0x0 +TEST_RR_OP(sraw, x7, x6, x8, 0x0, 0x0, 0x0, x1, 24*XLEN/8, x9) +RVTEST_SIGBASE(x8,signature_x8_0) inst_25: -// rs1==x24, rs2==x20, rd==x14, rs1_val == 262144, -// opcode: sraw ; op1:x24; op2:x20; dest:x14; op1val:0x40000; op2val:0x10 -TEST_RR_OP(sraw, x14, x24, x20, 0x4, 0x40000, 0x10, x6, 72, x9) +// rs1==x7, rs2==x5, rd==x6, +// opcode: sraw ; op1:x7; op2:x5; dest:x6; op1val:0x0; op2val:0x0 +TEST_RR_OP(sraw, x6, x7, x5, 0x0, 0x0, 0x0, x8, 0*XLEN/8, x9) inst_26: -// rs1==x2, rs2==x19, rd==x10, rs1_val == 1048576, rs2_val == 29 -// opcode: sraw ; op1:x2; op2:x19; dest:x10; op1val:0x100000; op2val:0x1d -TEST_RR_OP(sraw, x10, x2, x19, 0x0, 0x100000, 0x1d, x6, 80, x9) +// rs1==x4, rs2==x6, rd==x5, +// opcode: sraw ; op1:x4; op2:x6; dest:x5; op1val:0x0; op2val:0x0 +TEST_RR_OP(sraw, x5, x4, x6, 0x0, 0x0, 0x0, x8, 1*XLEN/8, x9) inst_27: -// rs1==x18, rs2==x14, rd==x16, rs1_val == 2097152, -// opcode: sraw ; op1:x18; op2:x14; dest:x16; op1val:0x200000; op2val:0xe -TEST_RR_OP(sraw, x16, x18, x14, 0x80, 0x200000, 0xe, x6, 88, x9) +// rs1==x5, rs2==x3, rd==x4, +// opcode: sraw ; op1:x5; op2:x3; dest:x4; op1val:0x0; op2val:0x0 +TEST_RR_OP(sraw, x4, x5, x3, 0x0, 0x0, 0x0, x8, 2*XLEN/8, x9) inst_28: -// rs1==x12, rs2==x17, rd==x18, rs1_val == 4194304, -// opcode: sraw ; op1:x12; op2:x17; dest:x18; op1val:0x400000; op2val:0x12 -TEST_RR_OP(sraw, x18, x12, x17, 0x10, 0x400000, 0x12, x6, 96, x9) +// rs1==x2, rs2==x4, rd==x3, +// opcode: sraw ; op1:x2; op2:x4; dest:x3; op1val:0x0; op2val:0x0 +TEST_RR_OP(sraw, x3, x2, x4, 0x0, 0x0, 0x0, x8, 3*XLEN/8, x9) inst_29: -// rs1==x8, rs2==x5, rd==x4, rs1_val == 8388608, -// opcode: sraw ; op1:x8; op2:x5; dest:x4; op1val:0x800000; op2val:0xd -TEST_RR_OP(sraw, x4, x8, x5, 0x400, 0x800000, 0xd, x6, 104, x9) +// rs1==x3, rs2==x1, rd==x2, +// opcode: sraw ; op1:x3; op2:x1; dest:x2; op1val:0x0; op2val:0x0 +TEST_RR_OP(sraw, x2, x3, x1, 0x0, 0x0, 0x0, x8, 4*XLEN/8, x9) inst_30: -// rs1==x4, rs2==x31, rd==x7, rs1_val == 16777216, -// opcode: sraw ; op1:x4; op2:x31; dest:x7; op1val:0x1000000; op2val:0x9 -TEST_RR_OP(sraw, x7, x4, x31, 0x8000, 0x1000000, 0x9, x6, 112, x9) +// rs1==x0, rs2==x2, rd==x1, +// opcode: sraw ; op1:x0; op2:x2; dest:x1; op1val:0x0; op2val:0x0 +TEST_RR_OP(sraw, x1, x0, x2, 0x0, 0x0, 0x0, x8, 5*XLEN/8, x9) inst_31: -// rs1==x26, rs2==x3, rd==x19, rs1_val == 33554432, rs2_val == 8 -// opcode: sraw ; op1:x26; op2:x3; dest:x19; op1val:0x2000000; op2val:0x8 -TEST_RR_OP(sraw, x19, x26, x3, 0x20000, 0x2000000, 0x8, x6, 120, x9) +// rs1==x1, +// opcode: sraw ; op1:x1; op2:x30; dest:x31; op1val:0x0; op2val:0x0 +TEST_RR_OP(sraw, x31, x1, x30, 0x0, 0x0, 0x0, x8, 6*XLEN/8, x9) inst_32: -// rs1_val == 67108864, rs2_val == 30 -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x4000000; op2val:0x1e -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x4000000, 0x1e, x6, 128, x1) +// rs2==x0, +// opcode: sraw ; op1:x30; op2:x0; dest:x31; op1val:0x0; op2val:0x0 +TEST_RR_OP(sraw, x31, x30, x0, 0x0, 0x0, 0x0, x8, 7*XLEN/8, x9) inst_33: -// rs1_val == 134217728, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x8000000; op2val:0xc -TEST_RR_OP(sraw, x12, x10, x11, 0x8000, 0x8000000, 0xc, x6, 136, x1) +// rd==x0, +// opcode: sraw ; op1:x31; op2:x30; dest:x0; op1val:0x0; op2val:0x0 +TEST_RR_OP(sraw, x0, x31, x30, 0, 0x0, 0x0, x8, 8*XLEN/8, x9) inst_34: -// rs1_val == 268435456, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x10000000; op2val:0x1e -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x10000000, 0x1e, x6, 144, x1) +// rs1_val < 0 and rs2_val == 0, +// opcode: sraw ; op1:x30; op2:x29; dest:x31; op1val:-0xb504f332; op2val:0x0 +TEST_RR_OP(sraw, x31, x30, x29, 0x4afb0cce, -0xb504f332, 0x0, x8, 9*XLEN/8, x9) inst_35: -// rs1_val == 536870912, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x20000000; op2val:0x0 -TEST_RR_OP(sraw, x12, x10, x11, 0x20000000, 0x20000000, 0x0, x6, 152, x1) - -inst_36: -// rs1_val == 1073741824, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x40000000; op2val:0x1e -TEST_RR_OP(sraw, x12, x10, x11, 0x1, 0x40000000, 0x1e, x6, 160, x1) - -inst_37: -// rs1_val == 2147483648, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x80000000; op2val:0xd -TEST_RR_OP(sraw, x12, x10, x11, -0x40000, 0x80000000, 0xd, x6, 168, x1) - -inst_38: -// rs1_val == 4294967296, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x100000000; op2val:0x4 -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x100000000, 0x4, x6, 176, x1) - -inst_39: -// rs1_val == 8589934592, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x200000000; op2val:0x11 -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x200000000, 0x11, x6, 184, x1) - -inst_40: -// rs1_val == 17179869184, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x400000000; op2val:0x4 -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x400000000, 0x4, x6, 192, x1) - -inst_41: -// rs1_val == 34359738368, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x800000000; op2val:0xa -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x800000000, 0xa, x6, 200, x1) - -inst_42: -// rs1_val == 68719476736, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x1000000000; op2val:0x5 -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x1000000000, 0x5, x6, 208, x1) - -inst_43: -// rs1_val == 137438953472, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x2000000000; op2val:0x1f -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x2000000000, 0x1f, x6, 216, x1) - -inst_44: -// rs1_val == 274877906944, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x4000000000; op2val:0xa -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x4000000000, 0xa, x6, 224, x1) - -inst_45: -// rs1_val == 549755813888, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x8000000000; op2val:0x1e -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x8000000000, 0x1e, x6, 232, x1) - -inst_46: -// rs1_val == 1099511627776, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x10000000000; op2val:0x1 -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x10000000000, 0x1, x6, 240, x1) - -inst_47: -// rs1_val == 2199023255552, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x20000000000; op2val:0x1 -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x20000000000, 0x1, x6, 248, x1) - -inst_48: -// rs1_val == 4398046511104, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x40000000000; op2val:0x4 -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x40000000000, 0x4, x6, 256, x1) - -inst_49: -// rs1_val == 8796093022208, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x80000000000; op2val:0x2 -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x80000000000, 0x2, x6, 264, x1) - -inst_50: -// rs1_val == 17592186044416, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x100000000000; op2val:0x9 -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x100000000000, 0x9, x6, 272, x1) - -inst_51: -// rs1_val == 35184372088832, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x200000000000; op2val:0x1f -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x200000000000, 0x1f, x6, 280, x1) - -inst_52: -// rs1_val == 70368744177664, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x400000000000; op2val:0x17 -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x400000000000, 0x17, x6, 288, x1) - -inst_53: -// rs1_val == 140737488355328, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x800000000000; op2val:0x6 -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x800000000000, 0x6, x6, 296, x1) - -inst_54: -// rs1_val == 281474976710656, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x1000000000000; op2val:0xc -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x1000000000000, 0xc, x6, 304, x1) - -inst_55: -// rs1_val == 562949953421312, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x2000000000000; op2val:0xb -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x2000000000000, 0xb, x6, 312, x1) - -inst_56: -// rs1_val == 1125899906842624, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x4000000000000; op2val:0x8 -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x4000000000000, 0x8, x6, 320, x1) - -inst_57: -// rs1_val == 2251799813685248, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x8000000000000; op2val:0xc -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x8000000000000, 0xc, x6, 328, x1) - -inst_58: -// rs1_val == 4503599627370496, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x10000000000000; op2val:0x1b -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x10000000000000, 0x1b, x6, 336, x1) - -inst_59: -// rs1_val == 9007199254740992, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x20000000000000; op2val:0x0 -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x20000000000000, 0x0, x6, 344, x1) - -inst_60: -// rs1_val == 18014398509481984, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x40000000000000; op2val:0x1d -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x40000000000000, 0x1d, x6, 352, x1) - -inst_61: -// rs1_val == 36028797018963968, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x80000000000000; op2val:0x1d -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x80000000000000, 0x1d, x6, 360, x1) - -inst_62: -// rs1_val == 72057594037927936, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x100000000000000; op2val:0x17 -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x100000000000000, 0x17, x6, 368, x1) - -inst_63: -// rs1_val == 144115188075855872, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x200000000000000; op2val:0x17 -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x200000000000000, 0x17, x6, 376, x1) - -inst_64: -// rs1_val == 288230376151711744, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x400000000000000; op2val:0xa -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x400000000000000, 0xa, x6, 384, x1) - -inst_65: -// rs1_val == 576460752303423488, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x800000000000000; op2val:0xa -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x800000000000000, 0xa, x6, 392, x1) - -inst_66: -// rs1_val == 1152921504606846976, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x1000000000000000; op2val:0x5 -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x1000000000000000, 0x5, x6, 400, x1) - -inst_67: -// rs1_val == 2305843009213693952, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x2000000000000000; op2val:0x3 -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x2000000000000000, 0x3, x6, 408, x1) - -inst_68: -// rs1_val == 4611686018427387904, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x4000000000000000; op2val:0x6 -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x4000000000000000, 0x6, x6, 416, x1) - -inst_69: -// rs1_val == -2, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x2; op2val:0x1f -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x2, 0x1f, x6, 424, x1) - -inst_70: -// rs1_val == -3, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x3; op2val:0xa -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x3, 0xa, x6, 432, x1) - -inst_71: -// rs1_val == -5, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x5; op2val:0x1f -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x5, 0x1f, x6, 440, x1) - -inst_72: -// rs1_val == -9, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x9; op2val:0x8 -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x9, 0x8, x6, 448, x1) - -inst_73: -// rs1_val == -17, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x11; op2val:0xd -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x11, 0xd, x6, 456, x1) - -inst_74: -// rs1_val == -33, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x21; op2val:0x15 -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x21, 0x15, x6, 464, x1) - -inst_75: -// rs1_val == -65, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x41; op2val:0x15 -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x41, 0x15, x6, 472, x1) - -inst_76: -// rs1_val == -129, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x81; op2val:0x2 -TEST_RR_OP(sraw, x12, x10, x11, -0x21, -0x81, 0x2, x6, 480, x1) - -inst_77: -// rs1_val == -513, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x201; op2val:0x9 -TEST_RR_OP(sraw, x12, x10, x11, -0x2, -0x201, 0x9, x6, 488, x1) - -inst_78: -// rs1_val == -1025, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x401; op2val:0x15 -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x401, 0x15, x6, 496, x1) - -inst_79: -// rs1_val == -2049, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x801; op2val:0x17 -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x801, 0x17, x6, 504, x1) - -inst_80: -// rs1_val == -4097, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x1001; op2val:0x4 -TEST_RR_OP(sraw, x12, x10, x11, -0x101, -0x1001, 0x4, x6, 512, x1) - -inst_81: -// rs1_val == -8193, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x2001; op2val:0x5 -TEST_RR_OP(sraw, x12, x10, x11, -0x101, -0x2001, 0x5, x6, 520, x1) - -inst_82: -// rs1_val == -16385, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x4001; op2val:0x0 -TEST_RR_OP(sraw, x12, x10, x11, -0x4001, -0x4001, 0x0, x6, 528, x1) - -inst_83: -// rs1_val == -32769, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x8001; op2val:0x7 -TEST_RR_OP(sraw, x12, x10, x11, -0x101, -0x8001, 0x7, x6, 536, x1) - -inst_84: -// rs1_val == -65537, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x10001; op2val:0x1f -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x10001, 0x1f, x6, 544, x1) - -inst_85: -// rs1_val == -262145, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x40001; op2val:0xb -TEST_RR_OP(sraw, x12, x10, x11, -0x81, -0x40001, 0xb, x6, 552, x1) - -inst_86: -// rs1_val == -524289, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x80001; op2val:0x6 -TEST_RR_OP(sraw, x12, x10, x11, -0x2001, -0x80001, 0x6, x6, 560, x1) - -inst_87: -// rs1_val == -1048577, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x100001; op2val:0x5 -TEST_RR_OP(sraw, x12, x10, x11, -0x8001, -0x100001, 0x5, x6, 568, x1) - -inst_88: -// rs1_val == -36028797018963969, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x80000000000001; op2val:0xb -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x80000000000001, 0xb, x6, 576, x1) - -inst_89: -// rs1_val == -72057594037927937, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x100000000000001; op2val:0x17 -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x100000000000001, 0x17, x6, 584, x1) - -inst_90: -// rs1_val == -144115188075855873, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x200000000000001; op2val:0x10 -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x200000000000001, 0x10, x6, 592, x1) - -inst_91: -// rs1_val == -288230376151711745, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x400000000000001; op2val:0x11 -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x400000000000001, 0x11, x6, 600, x1) - -inst_92: -// rs1_val == -576460752303423489, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x800000000000001; op2val:0x0 -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x800000000000001, 0x0, x6, 608, x1) - -inst_93: -// rs1_val == -1152921504606846977, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x1000000000000001; op2val:0x0 -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x1000000000000001, 0x0, x6, 616, x1) - -inst_94: -// rs1_val == -2305843009213693953, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x2000000000000001; op2val:0x1d -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x2000000000000001, 0x1d, x6, 624, x1) - -inst_95: -// rs1_val == -4611686018427387905, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x4000000000000001; op2val:0x7 -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x4000000000000001, 0x7, x6, 632, x1) - -inst_96: -// rs1_val == 6148914691236517205, rs1_val==6148914691236517205 -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x5555555555555555; op2val:0x7 -TEST_RR_OP(sraw, x12, x10, x11, 0xaaaaaa, 0x5555555555555555, 0x7, x6, 640, x1) - -inst_97: -// rs1_val == -6148914691236517206, rs1_val==-6148914691236517206 -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x5555555555555556; op2val:0x9 -TEST_RR_OP(sraw, x12, x10, x11, -0x2aaaab, -0x5555555555555556, 0x9, x6, 648, x1) - -inst_98: -// rs1_val==3, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x3; op2val:0x12 -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x3, 0x12, x6, 656, x1) - -inst_99: -// rs1_val==5, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x5; op2val:0x1 -TEST_RR_OP(sraw, x12, x10, x11, 0x2, 0x5, 0x1, x6, 664, x1) - -inst_100: -// rs1_val==3689348814741910323, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x3333333333333333; op2val:0x1d -TEST_RR_OP(sraw, x12, x10, x11, 0x1, 0x3333333333333333, 0x1d, x6, 672, x1) - -inst_101: -// rs1_val==7378697629483820646, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x6666666666666666; op2val:0x3 -TEST_RR_OP(sraw, x12, x10, x11, 0xccccccc, 0x6666666666666666, 0x3, x6, 680, x1) - -inst_102: -// rs1_val==-3037000499, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0xb504f333; op2val:0x13 -TEST_RR_OP(sraw, x12, x10, x11, 0x95f, -0xb504f333, 0x13, x6, 688, x1) - -inst_103: -// rs1_val==3037000499, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0xb504f333; op2val:0xc -TEST_RR_OP(sraw, x12, x10, x11, -0x4afb1, 0xb504f333, 0xc, x6, 696, x1) - -inst_104: -// rs1_val==6148914691236517204, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x5555555555555554; op2val:0x1e -TEST_RR_OP(sraw, x12, x10, x11, 0x1, 0x5555555555555554, 0x1e, x6, 704, x1) - -inst_105: -// rs1_val==3689348814741910322, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x3333333333333332; op2val:0x9 -TEST_RR_OP(sraw, x12, x10, x11, 0x199999, 0x3333333333333332, 0x9, x6, 712, x1) - -inst_106: -// rs1_val==7378697629483820645, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x6666666666666665; op2val:0x2 -TEST_RR_OP(sraw, x12, x10, x11, 0x19999999, 0x6666666666666665, 0x2, x6, 720, x1) - -inst_107: -// rs1_val==3037000498, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0xb504f332; op2val:0x15 -TEST_RR_OP(sraw, x12, x10, x11, -0x258, 0xb504f332, 0x15, x6, 728, x1) - -inst_108: -// rs1_val==6148914691236517206, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x5555555555555556; op2val:0x1e -TEST_RR_OP(sraw, x12, x10, x11, 0x1, 0x5555555555555556, 0x1e, x6, 736, x1) - -inst_109: -// rs1_val==-6148914691236517205, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x5555555555555555; op2val:0xe -TEST_RR_OP(sraw, x12, x10, x11, -0x15556, -0x5555555555555555, 0xe, x6, 744, x1) - -inst_110: -// rs1_val==6, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x6; op2val:0xa -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x6, 0xa, x6, 752, x1) - -inst_111: -// rs1_val==3689348814741910324, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x3333333333333334; op2val:0xe -TEST_RR_OP(sraw, x12, x10, x11, 0xcccc, 0x3333333333333334, 0xe, x6, 760, x1) - -inst_112: -// rs1_val==7378697629483820647, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x6666666666666667; op2val:0x11 -TEST_RR_OP(sraw, x12, x10, x11, 0x3333, 0x6666666666666667, 0x11, x6, 768, x1) - -inst_113: -// rs1_val==-3037000498, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0xb504f332; op2val:0x4 -TEST_RR_OP(sraw, x12, x10, x11, 0x4afb0cc, -0xb504f332, 0x4, x6, 776, x1) - -inst_114: -// rs1_val==3037000500, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0xb504f334; op2val:0x1d -TEST_RR_OP(sraw, x12, x10, x11, -0x3, 0xb504f334, 0x1d, x6, 784, x1) - -inst_115: -// rs1_val == -2097153, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x200001; op2val:0xf -TEST_RR_OP(sraw, x12, x10, x11, -0x41, -0x200001, 0xf, x6, 792, x1) - -inst_116: -// rs1_val == -4194305, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x400001; op2val:0xd -TEST_RR_OP(sraw, x12, x10, x11, -0x201, -0x400001, 0xd, x6, 800, x1) - -inst_117: -// rs1_val == -8388609, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x800001; op2val:0x1e -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x800001, 0x1e, x6, 808, x1) - -inst_118: -// rs1_val == -16777217, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x1000001; op2val:0xe -TEST_RR_OP(sraw, x12, x10, x11, -0x401, -0x1000001, 0xe, x6, 816, x1) - -inst_119: -// rs1_val == -33554433, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x2000001; op2val:0x5 -TEST_RR_OP(sraw, x12, x10, x11, -0x100001, -0x2000001, 0x5, x6, 824, x1) - -inst_120: -// rs1_val == -67108865, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x4000001; op2val:0x8 -TEST_RR_OP(sraw, x12, x10, x11, -0x40001, -0x4000001, 0x8, x6, 832, x1) - -inst_121: -// rs1_val == -134217729, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x8000001; op2val:0x7 -TEST_RR_OP(sraw, x12, x10, x11, -0x100001, -0x8000001, 0x7, x6, 840, x1) - -inst_122: -// rs1_val == -268435457, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x10000001; op2val:0xb -TEST_RR_OP(sraw, x12, x10, x11, -0x20001, -0x10000001, 0xb, x6, 848, x1) - -inst_123: -// rs1_val == -536870913, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x20000001; op2val:0x11 -TEST_RR_OP(sraw, x12, x10, x11, -0x1001, -0x20000001, 0x11, x6, 856, x1) - -inst_124: -// rs1_val == -1073741825, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x40000001; op2val:0x6 -TEST_RR_OP(sraw, x12, x10, x11, -0x1000001, -0x40000001, 0x6, x6, 864, x1) - -inst_125: -// rs1_val == -2147483649, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x80000001; op2val:0xf -TEST_RR_OP(sraw, x12, x10, x11, 0xffff, -0x80000001, 0xf, x6, 872, x1) - -inst_126: -// rs1_val == -4294967297, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x100000001; op2val:0x17 -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x100000001, 0x17, x6, 880, x1) - -inst_127: -// rs1_val == -8589934593, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x200000001; op2val:0x2 -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x200000001, 0x2, x6, 888, x1) - -inst_128: -// rs1_val == -17179869185, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x400000001; op2val:0x17 -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x400000001, 0x17, x6, 896, x1) - -inst_129: -// rs1_val == -34359738369, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x800000001; op2val:0x0 -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x800000001, 0x0, x6, 904, x1) - -inst_130: -// rs1_val == -68719476737, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x1000000001; op2val:0x11 -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x1000000001, 0x11, x6, 912, x1) - -inst_131: -// rs1_val == -137438953473, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x2000000001; op2val:0x1 -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x2000000001, 0x1, x6, 920, x1) - -inst_132: -// rs1_val == -274877906945, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x4000000001; op2val:0x1f -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x4000000001, 0x1f, x6, 928, x1) - -inst_133: -// rs1_val == -549755813889, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x8000000001; op2val:0x6 -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x8000000001, 0x6, x6, 936, x1) - -inst_134: -// rs1_val == -1099511627777, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x10000000001; op2val:0x1b -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x10000000001, 0x1b, x6, 944, x1) - -inst_135: -// rs1_val == -2199023255553, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x20000000001; op2val:0xa -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x20000000001, 0xa, x6, 952, x1) - -inst_136: -// rs1_val == -4398046511105, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x40000000001; op2val:0x2 -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x40000000001, 0x2, x6, 960, x1) - -inst_137: -// rs1_val == -8796093022209, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x80000000001; op2val:0x8 -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x80000000001, 0x8, x6, 968, x1) - -inst_138: -// rs1_val == -17592186044417, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x100000000001; op2val:0xd -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x100000000001, 0xd, x6, 976, x1) - -inst_139: -// rs1_val == -35184372088833, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x200000000001; op2val:0xa -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x200000000001, 0xa, x6, 984, x1) - -inst_140: -// rs1_val == -70368744177665, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x400000000001; op2val:0x17 -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x400000000001, 0x17, x6, 992, x1) - -inst_141: -// rs1_val == -140737488355329, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x800000000001; op2val:0x12 -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x800000000001, 0x12, x6, 1000, x1) - -inst_142: -// rs1_val == -281474976710657, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x1000000000001; op2val:0x9 -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x1000000000001, 0x9, x6, 1008, x1) - -inst_143: -// rs1_val == -562949953421313, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x2000000000001; op2val:0x13 -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x2000000000001, 0x13, x6, 1016, x1) - -inst_144: -// rs1_val == -1125899906842625, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x4000000000001; op2val:0xa -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x4000000000001, 0xa, x6, 1024, x1) - -inst_145: -// rs1_val == -2251799813685249, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x8000000000001; op2val:0x1 -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x8000000000001, 0x1, x6, 1032, x1) - -inst_146: -// rs1_val == -4503599627370497, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x10000000000001; op2val:0x2 -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x10000000000001, 0x2, x6, 1040, x1) - -inst_147: -// rs1_val == -9007199254740993, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x20000000000001; op2val:0x1f -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x20000000000001, 0x1f, x6, 1048, x1) - -inst_148: -// rs1_val == -18014398509481985, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x40000000000001; op2val:0x4 -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x40000000000001, 0x4, x6, 1056, x1) - -inst_149: -// rs1_val < 0 and rs2_val > 0 and rs2_val < xlen, rs1_val == -257, rs2_val == 1 -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x101; op2val:0x1 -TEST_RR_OP(sraw, x12, x10, x11, -0x81, -0x101, 0x1, x6, 1064, x1) - -inst_150: -// rs1_val < 0 and rs2_val == 0, rs1_val == -131073 -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x20001; op2val:0x0 -TEST_RR_OP(sraw, x12, x10, x11, -0x20001, -0x20001, 0x0, x6, 1072, x1) - -inst_151: -// rs1_val == (-2**(xlen-1)) and rs2_val >= 0 and rs2_val < xlen, rs1_val == -9223372036854775808 -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x8000000000000000; op2val:0xe -TEST_RR_OP(sraw, x12, x10, x11, 0x0, -0x8000000000000000, 0xe, x6, 1080, x1) - -inst_152: -// rs1_val == 2, rs1_val==2, rs2_val == 10 -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x2; op2val:0xa -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x2, 0xa, x6, 1088, x1) - -inst_153: -// rs1_val == 16384, rs2_val == 2 -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x4000; op2val:0x2 -TEST_RR_OP(sraw, x12, x10, x11, 0x1000, 0x4000, 0x2, x6, 1096, x1) +// rs1_val == (-2**(xlen-1)) and rs2_val >= 0 and rs2_val < xlen, +// opcode: sraw ; op1:x30; op2:x29; dest:x31; op1val:-0x8000000000000000; op2val:0x1f +TEST_RR_OP(sraw, x31, x30, x29, 0x0, -0x8000000000000000, 0x1f, x8, 10*XLEN/8, x9) #endif @@ -809,50 +221,50 @@ RVMODEL_HALT RVTEST_DATA_BEGIN .align 4 - rvtest_data: .word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab RVTEST_DATA_END - RVMODEL_DATA_BEGIN rvtest_sig_begin: sig_begin_canary: CANARY; -signature_x3_0: - .fill 0*(XLEN/32),4,0xdeadbeef +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef -signature_x3_1: - .fill 16*(XLEN/32),4,0xdeadbeef +signature_x1_1: + .fill 25*((XLEN/8)/4),4,0xdeadbeef -signature_x6_0: - .fill 138*(XLEN/32),4,0xdeadbeef -#ifdef rvtest_mtrap_routine +signature_x8_0: + .fill 11*((XLEN/8)/4),4,0xdeadbeef +#ifdef rvtest_mtrap_routine tsig_begin_canary: CANARY; + mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef + .fill 64*XLEN/32,4,0xdeadbeef + tsig_end_canary: CANARY; - #endif #ifdef rvtest_gpr_save gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef + .fill 32*XLEN/32,4,0xdeadbeef #endif + sig_end_canary: CANARY; rvtest_sig_end: diff --git a/riscv-test-suite/rv64i_m/Zhinx/src/fcvt.l.h_b1-01.S b/riscv-test-suite/rv64i_m/Zhinx/src/fcvt.l.h_b1-01.S new file mode 100644 index 000000000..e20300059 --- /dev/null +++ b/riscv-test-suite/rv64i_m/Zhinx/src/fcvt.l.h_b1-01.S @@ -0,0 +1,328 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 04:45:28 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64Zhinx/rv64h_fcvt.l.h.cgf \ + \ +// -- xlen 64 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.l.h instruction of the RISC-V RV64_Zfinx_Zhinx extension for the fcvt.l.h_b1 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fcvt.l.h_b1) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0:// rs1==x24, rd==x26,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x24; dest:x26; op1val:0x0; valaddr_reg:x3; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x26, x24, dyn, 0, 0, x3, 0*FLEN/8, x12, x1, x7,FLREG) + +inst_1:// rs1==x23, rd==x4,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x23; dest:x4; op1val:0x8000; valaddr_reg:x3; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x4, x23, dyn, 0, 0, x3, 1*FLEN/8, x12, x1, x7,FLREG) + +inst_2:// rs1==x9, rd==x19,fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x9; dest:x19; op1val:0x1; valaddr_reg:x3; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x19, x9, dyn, 0, 0, x3, 2*FLEN/8, x12, x1, x7,FLREG) + +inst_3:// rs1==x4, rd==x31,fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x4; dest:x31; op1val:0x8001; valaddr_reg:x3; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x4, dyn, 0, 0, x3, 3*FLEN/8, x12, x1, x7,FLREG) + +inst_4:// rs1==x11, rd==x13,fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x11; dest:x13; op1val:0x2; valaddr_reg:x3; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x13, x11, dyn, 0, 0, x3, 4*FLEN/8, x12, x1, x7,FLREG) + +inst_5:// rs1==x8, rd==x0,fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x8; dest:x0; op1val:0x83fe; valaddr_reg:x3; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x0, x8, dyn, 0, 0, x3, 5*FLEN/8, x12, x1, x7,FLREG) + +inst_6:// rs1==x14, rd==x18,fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x14; dest:x18; op1val:0x3ff; valaddr_reg:x3; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x18, x14, dyn, 0, 0, x3, 6*FLEN/8, x12, x1, x7,FLREG) + +inst_7:// rs1==x16, rd==x11,fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x16; dest:x11; op1val:0x83ff; valaddr_reg:x3; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x11, x16, dyn, 0, 0, x3, 7*FLEN/8, x12, x1, x7,FLREG) + +inst_8:// rs1==x22, rd==x14,fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x22; dest:x14; op1val:0x400; valaddr_reg:x3; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x14, x22, dyn, 0, 0, x3, 8*FLEN/8, x12, x1, x7,FLREG) + +inst_9:// rs1==x18, rd==x16,fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x18; dest:x16; op1val:0x8400; valaddr_reg:x3; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x16, x18, dyn, 0, 0, x3, 9*FLEN/8, x12, x1, x7,FLREG) + +inst_10:// rs1==x26, rd==x25,fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x26; dest:x25; op1val:0x401; valaddr_reg:x3; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x25, x26, dyn, 0, 0, x3, 10*FLEN/8, x12, x1, x7,FLREG) + +inst_11:// rs1==x6, rd==x24,fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x6; dest:x24; op1val:0x8455; valaddr_reg:x3; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x24, x6, dyn, 0, 0, x3, 11*FLEN/8, x12, x1, x7,FLREG) + +inst_12:// rs1==x29, rd==x15,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x29; dest:x15; op1val:0x7bff; valaddr_reg:x3; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x15, x29, dyn, 0, 0, x3, 12*FLEN/8, x12, x1, x7,FLREG) + +inst_13:// rs1==x27, rd==x28,fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x27; dest:x28; op1val:0xfbff; valaddr_reg:x3; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x28, x27, dyn, 0, 0, x3, 13*FLEN/8, x12, x1, x7,FLREG) + +inst_14:// rs1==x10, rd==x5,fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x10; dest:x5; op1val:0x7c00; valaddr_reg:x3; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x5, x10, dyn, 0, 0, x3, 14*FLEN/8, x12, x1, x7,FLREG) + +inst_15:// rs1==x19, rd==x10,fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x19; dest:x10; op1val:0xfc00; valaddr_reg:x3; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x10, x19, dyn, 0, 0, x3, 15*FLEN/8, x12, x1, x7,FLREG) + +inst_16:// rs1==x31, rd==x9,fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x31; dest:x9; op1val:0x7e00; valaddr_reg:x3; +val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x9, x31, dyn, 0, 0, x3, 16*FLEN/8, x12, x1, x7,FLREG) + +inst_17:// rs1==x5, rd==x23,fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x5; dest:x23; op1val:0xfe00; valaddr_reg:x3; +val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x23, x5, dyn, 0, 0, x3, 17*FLEN/8, x12, x1, x7,FLREG) + +inst_18:// rs1==x2, rd==x30,fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x2; dest:x30; op1val:0x7e01; valaddr_reg:x3; +val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x30, x2, dyn, 0, 0, x3, 18*FLEN/8, x12, x1, x7,FLREG) +RVTEST_VALBASEUPD(x9,test_dataset_1) + +inst_19:// rs1==x12, rd==x29,fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x12; dest:x29; op1val:0xfe55; valaddr_reg:x9; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x29, x12, dyn, 0, 0, x9, 0*FLEN/8, x10, x1, x7,FLREG) + +inst_20:// rs1==x13, rd==x3,fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x13; dest:x3; op1val:0x7c01; valaddr_reg:x9; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x7; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x3, x13, dyn, 0, 0, x9, 1*FLEN/8, x10, x1, x7,FLREG) + +inst_21:// rs1==x25, rd==x20,fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x25; dest:x20; op1val:0xfd55; valaddr_reg:x9; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x20, x25, dyn, 0, 0, x9, 2*FLEN/8, x10, x1, x5,FLREG) +RVTEST_SIGBASE(x4,signature_x4_0) + +inst_22:// rs1==x20, rd==x12,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x20; dest:x12; op1val:0x3c00; valaddr_reg:x9; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x12, x20, dyn, 0, 0, x9, 3*FLEN/8, x10, x4, x5,FLREG) + +inst_23:// rs1==x21, rd==x7,fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x21; dest:x7; op1val:0xbc00; valaddr_reg:x9; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x7, x21, dyn, 0, 0, x9, 4*FLEN/8, x10, x4, x5,FLREG) + +inst_24:// rs1==x0, rd==x2, +/* opcode: fcvt.l.h ; op1:x0; dest:x2; op1val:0x0; valaddr_reg:x9; +val_offset:5*FLEN/8; rmval:rne; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x2, x0, rne, 0, 0, x9, 5*FLEN/8, x10, x4, x5,FLREG) + +inst_25:// rs1==x1, rd==x17, +/* opcode: fcvt.l.h ; op1:x1; dest:x17; op1val:0x0; valaddr_reg:x9; +val_offset:6*FLEN/8; rmval:rne; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x17, x1, rne, 0, 0, x9, 6*FLEN/8, x10, x4, x5,FLREG) + +inst_26:// rs1==x30, rd==x22, +/* opcode: fcvt.l.h ; op1:x30; dest:x22; op1val:0x0; valaddr_reg:x9; +val_offset:7*FLEN/8; rmval:rne; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x22, x30, rne, 0, 0, x9, 7*FLEN/8, x10, x4, x5,FLREG) + +inst_27:// rs1==x15, rd==x1, +/* opcode: fcvt.l.h ; op1:x15; dest:x1; op1val:0x0; valaddr_reg:x9; +val_offset:8*FLEN/8; rmval:rne; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x1, x15, rne, 0, 0, x9, 8*FLEN/8, x10, x4, x5,FLREG) + +inst_28:// rs1==x3, rd==x21, +/* opcode: fcvt.l.h ; op1:x3; dest:x21; op1val:0x0; valaddr_reg:x9; +val_offset:9*FLEN/8; rmval:rne; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x21, x3, rne, 0, 0, x9, 9*FLEN/8, x10, x4, x5,FLREG) + +inst_29:// rs1==x17, rd==x6, +/* opcode: fcvt.l.h ; op1:x17; dest:x6; op1val:0x0; valaddr_reg:x9; +val_offset:10*FLEN/8; rmval:rne; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x6, x17, rne, 0, 0, x9, 10*FLEN/8, x10, x4, x5,FLREG) + +inst_30:// rs1==x28, rd==x8, +/* opcode: fcvt.l.h ; op1:x28; dest:x8; op1val:0x0; valaddr_reg:x9; +val_offset:11*FLEN/8; rmval:rne; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x8, x28, rne, 0, 0, x9, 11*FLEN/8, x10, x4, x5,FLREG) + +inst_31:// rs1==x7, rd==x27, +/* opcode: fcvt.l.h ; op1:x7; dest:x27; op1val:0x0; valaddr_reg:x9; +val_offset:12*FLEN/8; rmval:rne; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x27, x7, rne, 0, 0, x9, 12*FLEN/8, x10, x4, x5,FLREG) + +inst_32:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x83fe; valaddr_reg:x9; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x9, 13*FLEN/8, x10, x4, x5,FLREG) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1,32,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(2,32,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(1023,32,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(1024,32,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(1025,32,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31744,32,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(32256,32,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(32257,32,FLEN) +test_dataset_1: +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(33790,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 44*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x4_0: + .fill 22*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/Zhinx/src/fcvt.l.h_b22-01.S b/riscv-test-suite/rv64i_m/Zhinx/src/fcvt.l.h_b22-01.S new file mode 100644 index 000000000..31c42daca --- /dev/null +++ b/riscv-test-suite/rv64i_m/Zhinx/src/fcvt.l.h_b22-01.S @@ -0,0 +1,615 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 04:45:28 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64Zhinx/rv64h_fcvt.l.h.cgf \ + \ +// -- xlen 64 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.l.h instruction of the RISC-V RV64_Zfinx_Zhinx extension for the fcvt.l.h_b22 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fcvt.l.h_b22) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x7,test_dataset_0) +RVTEST_SIGBASE(x3,signature_x3_1) + +inst_0:// rs1 == rd, rs1==x26, rd==x26,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x26; dest:x26; op1val:0x3249; valaddr_reg:x7; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x18; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x26, x26, dyn, 0, 0, x7, 0*FLEN/8, x19, x3, x18,FLREG) + +inst_1:// rs1 != rd, rs1==x25, rd==x14,fs1 == 0 and fe1 == 0x0d and fm1 == 0x1b7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x25; dest:x14; op1val:0x35b7; valaddr_reg:x7; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x18; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x14, x25, dyn, 0, 0, x7, 1*FLEN/8, x19, x3, x18,FLREG) + +inst_2:// rs1==x4, rd==x16,fs1 == 0 and fe1 == 0x0e and fm1 == 0x24f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x4; dest:x16; op1val:0x3a4f; valaddr_reg:x7; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x18; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x16, x4, dyn, 0, 0, x7, 2*FLEN/8, x19, x3, x18,FLREG) + +inst_3:// rs1==x29, rd==x17,fs1 == 0 and fe1 == 0x0f and fm1 == 0x0d3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x29; dest:x17; op1val:0x3cd3; valaddr_reg:x7; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x18; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x17, x29, dyn, 0, 0, x7, 3*FLEN/8, x19, x3, x18,FLREG) + +inst_4:// rs1==x21, rd==x11,fs1 == 0 and fe1 == 0x10 and fm1 == 0x340 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x21; dest:x11; op1val:0x4340; valaddr_reg:x7; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x18; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x11, x21, dyn, 0, 0, x7, 4*FLEN/8, x19, x3, x18,FLREG) + +inst_5:// rs1==x9, rd==x22,fs1 == 0 and fe1 == 0x11 and fm1 == 0x34b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x9; dest:x22; op1val:0x474b; valaddr_reg:x7; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x18; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x22, x9, dyn, 0, 0, x7, 5*FLEN/8, x19, x3, x18,FLREG) + +inst_6:// rs1==x12, rd==x29,fs1 == 1 and fe1 == 0x12 and fm1 == 0x29d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x12; dest:x29; op1val:0xca9d; valaddr_reg:x7; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x18; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x29, x12, dyn, 0, 0, x7, 6*FLEN/8, x19, x3, x18,FLREG) + +inst_7:// rs1==x5, rd==x15,fs1 == 0 and fe1 == 0x13 and fm1 == 0x0a4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x5; dest:x15; op1val:0x4ca4; valaddr_reg:x7; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x18; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x15, x5, dyn, 0, 0, x7, 7*FLEN/8, x19, x3, x18,FLREG) + +inst_8:// rs1==x13, rd==x23,fs1 == 0 and fe1 == 0x14 and fm1 == 0x215 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x13; dest:x23; op1val:0x5215; valaddr_reg:x7; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x18; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x23, x13, dyn, 0, 0, x7, 8*FLEN/8, x19, x3, x18,FLREG) + +inst_9:// rs1==x23, rd==x9,fs1 == 0 and fe1 == 0x15 and fm1 == 0x14f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x23; dest:x9; op1val:0x554f; valaddr_reg:x7; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x18; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x9, x23, dyn, 0, 0, x7, 9*FLEN/8, x19, x3, x18,FLREG) + +inst_10:// rs1==x11, rd==x30,fs1 == 1 and fe1 == 0x16 and fm1 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x11; dest:x30; op1val:0xd8ff; valaddr_reg:x7; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x18; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x30, x11, dyn, 0, 0, x7, 10*FLEN/8, x19, x3, x18,FLREG) + +inst_11:// rs1==x16, rd==x6,fs1 == 1 and fe1 == 0x17 and fm1 == 0x3cf and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x16; dest:x6; op1val:0xdfcf; valaddr_reg:x7; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x18; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x6, x16, dyn, 0, 0, x7, 11*FLEN/8, x19, x3, x18,FLREG) + +inst_12:// rs1==x8, rd==x4,fs1 == 0 and fe1 == 0x18 and fm1 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x8; dest:x4; op1val:0x63fc; valaddr_reg:x7; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x18; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x4, x8, dyn, 0, 0, x7, 12*FLEN/8, x19, x3, x18,FLREG) + +inst_13:// rs1==x20, rd==x2,fs1 == 0 and fe1 == 0x19 and fm1 == 0x02d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x20; dest:x2; op1val:0x642d; valaddr_reg:x7; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x18; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x2, x20, dyn, 0, 0, x7, 13*FLEN/8, x19, x3, x18,FLREG) + +inst_14:// rs1==x28, rd==x5,fs1 == 0 and fe1 == 0x1a and fm1 == 0x370 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x28; dest:x5; op1val:0x6b70; valaddr_reg:x7; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x18; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x5, x28, dyn, 0, 0, x7, 14*FLEN/8, x19, x3, x18,FLREG) + +inst_15:// rs1==x22, rd==x12,fs1 == 0 and fe1 == 0x1b and fm1 == 0x269 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x22; dest:x12; op1val:0x6e69; valaddr_reg:x7; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x18; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x12, x22, dyn, 0, 0, x7, 15*FLEN/8, x19, x3, x18,FLREG) + +inst_16:// rs1==x1, rd==x8,fs1 == 0 and fe1 == 0x1c and fm1 == 0x186 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x1; dest:x8; op1val:0x7186; valaddr_reg:x7; +val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x18; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x8, x1, dyn, 0, 0, x7, 16*FLEN/8, x19, x3, x18,FLREG) + +inst_17:// rs1==x30, rd==x10,fs1 == 1 and fe1 == 0x1d and fm1 == 0x122 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x10; op1val:0xf522; valaddr_reg:x7; +val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x18; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x10, x30, dyn, 0, 0, x7, 17*FLEN/8, x19, x3, x18,FLREG) +RVTEST_VALBASEUPD(x8,test_dataset_1) + +inst_18:// rs1==x10, rd==x24,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x10; dest:x24; op1val:0x7ab3; valaddr_reg:x8; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x18; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x24, x10, dyn, 0, 0, x8, 0*FLEN/8, x9, x3, x18,FLREG) + +inst_19:// rs1==x7, rd==x27,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x7; dest:x27; op1val:0x7bff; valaddr_reg:x8; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x18; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x27, x7, dyn, 0, 0, x8, 1*FLEN/8, x9, x3, x18,FLREG) +RVTEST_SIGBASE(x4,signature_x4_0) + +inst_20:// rs1==x17, rd==x18,fs1 == 1 and fe1 == 0x00 and fm1 == 0x2be and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x17; dest:x18; op1val:0x82be; valaddr_reg:x8; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x18, x17, dyn, 0, 0, x8, 2*FLEN/8, x9, x4, x5,FLREG) + +inst_21:// rs1==x0, rd==x31,fs1 == 1 and fe1 == 0x01 and fm1 == 0x2a5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x0; dest:x31; op1val:0x0; valaddr_reg:x8; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x0, dyn, 0, 0, x8, 3*FLEN/8, x9, x4, x5,FLREG) + +inst_22:// rs1==x3, rd==x19,fs1 == 1 and fe1 == 0x02 and fm1 == 0x088 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x3; dest:x19; op1val:0x8888; valaddr_reg:x8; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x19, x3, dyn, 0, 0, x8, 4*FLEN/8, x9, x4, x5,FLREG) + +inst_23:// rs1==x27, rd==x0,fs1 == 1 and fe1 == 0x03 and fm1 == 0x312 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x27; dest:x0; op1val:0x8f12; valaddr_reg:x8; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x0, x27, dyn, 0, 0, x8, 5*FLEN/8, x9, x4, x5,FLREG) + +inst_24:// rs1==x6, rd==x3,fs1 == 1 and fe1 == 0x04 and fm1 == 0x3ed and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x6; dest:x3; op1val:0x93ed; valaddr_reg:x8; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x3, x6, dyn, 0, 0, x8, 6*FLEN/8, x9, x4, x5,FLREG) + +inst_25:// rs1==x14, rd==x25,fs1 == 1 and fe1 == 0x05 and fm1 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x14; dest:x25; op1val:0x97e0; valaddr_reg:x8; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x25, x14, dyn, 0, 0, x8, 7*FLEN/8, x9, x4, x5,FLREG) + +inst_26:// rs1==x31, rd==x13,fs1 == 1 and fe1 == 0x06 and fm1 == 0x274 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x31; dest:x13; op1val:0x9a74; valaddr_reg:x8; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x13, x31, dyn, 0, 0, x8, 8*FLEN/8, x9, x4, x5,FLREG) + +inst_27:// rs1==x24, rd==x1,fs1 == 1 and fe1 == 0x07 and fm1 == 0x02d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x24; dest:x1; op1val:0x9c2d; valaddr_reg:x8; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x1, x24, dyn, 0, 0, x8, 9*FLEN/8, x9, x4, x5,FLREG) + +inst_28:// rs1==x15, rd==x20,fs1 == 1 and fe1 == 0x08 and fm1 == 0x004 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x15; dest:x20; op1val:0xa004; valaddr_reg:x8; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x20, x15, dyn, 0, 0, x8, 10*FLEN/8, x9, x4, x5,FLREG) + +inst_29:// rs1==x19, rd==x7,fs1 == 1 and fe1 == 0x09 and fm1 == 0x089 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x19; dest:x7; op1val:0xa489; valaddr_reg:x8; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x7, x19, dyn, 0, 0, x8, 11*FLEN/8, x9, x4, x5,FLREG) + +inst_30:// rs1==x2, rd==x28,fs1 == 1 and fe1 == 0x0a and fm1 == 0x3c3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x2; dest:x28; op1val:0xabc3; valaddr_reg:x8; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x28, x2, dyn, 0, 0, x8, 12*FLEN/8, x9, x4, x5,FLREG) + +inst_31:// rs1==x18, rd==x21,fs1 == 1 and fe1 == 0x0b and fm1 == 0x136 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x18; dest:x21; op1val:0xad36; valaddr_reg:x8; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x21, x18, dyn, 0, 0, x8, 13*FLEN/8, x9, x4, x5,FLREG) + +inst_32:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x176 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xb176; valaddr_reg:x8; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x8, 14*FLEN/8, x9, x4, x5,FLREG) + +inst_33:// fs1 == 1 and fe1 == 0x0d and fm1 == 0x397 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xb797; valaddr_reg:x8; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x8, 15*FLEN/8, x9, x4, x5,FLREG) + +inst_34:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x141 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xb941; valaddr_reg:x8; +val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x8, 16*FLEN/8, x9, x4, x5,FLREG) + +inst_35:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x232 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xbe32; valaddr_reg:x8; +val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x8, 17*FLEN/8, x9, x4, x5,FLREG) + +inst_36:// fs1 == 1 and fe1 == 0x10 and fm1 == 0x1be and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xc1be; valaddr_reg:x8; +val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x8, 18*FLEN/8, x9, x4, x5,FLREG) + +inst_37:// fs1 == 1 and fe1 == 0x11 and fm1 == 0x042 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xc442; valaddr_reg:x8; +val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x8, 19*FLEN/8, x9, x4, x5,FLREG) + +inst_38:// fs1 == 1 and fe1 == 0x12 and fm1 == 0x256 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xca56; valaddr_reg:x8; +val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x8, 20*FLEN/8, x9, x4, x5,FLREG) + +inst_39:// fs1 == 1 and fe1 == 0x13 and fm1 == 0x360 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xcf60; valaddr_reg:x8; +val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x8, 21*FLEN/8, x9, x4, x5,FLREG) + +inst_40:// fs1 == 1 and fe1 == 0x14 and fm1 == 0x0a0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xd0a0; valaddr_reg:x8; +val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x8, 22*FLEN/8, x9, x4, x5,FLREG) + +inst_41:// fs1 == 1 and fe1 == 0x15 and fm1 == 0x0e5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xd4e5; valaddr_reg:x8; +val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x8, 23*FLEN/8, x9, x4, x5,FLREG) + +inst_42:// fs1 == 1 and fe1 == 0x16 and fm1 == 0x1a6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xd9a6; valaddr_reg:x8; +val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x8, 24*FLEN/8, x9, x4, x5,FLREG) + +inst_43:// fs1 == 1 and fe1 == 0x17 and fm1 == 0x025 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xdc25; valaddr_reg:x8; +val_offset:25*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x8, 25*FLEN/8, x9, x4, x5,FLREG) + +inst_44:// fs1 == 1 and fe1 == 0x18 and fm1 == 0x1fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xe1fc; valaddr_reg:x8; +val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x8, 26*FLEN/8, x9, x4, x5,FLREG) + +inst_45:// fs1 == 1 and fe1 == 0x19 and fm1 == 0x345 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xe745; valaddr_reg:x8; +val_offset:27*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x8, 27*FLEN/8, x9, x4, x5,FLREG) + +inst_46:// fs1 == 1 and fe1 == 0x1a and fm1 == 0x2a1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xeaa1; valaddr_reg:x8; +val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x8, 28*FLEN/8, x9, x4, x5,FLREG) + +inst_47:// fs1 == 1 and fe1 == 0x1b and fm1 == 0x222 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xee22; valaddr_reg:x8; +val_offset:29*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x8, 29*FLEN/8, x9, x4, x5,FLREG) + +inst_48:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x36b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xf36b; valaddr_reg:x8; +val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x8, 30*FLEN/8, x9, x4, x5,FLREG) + +inst_49:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x099 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xf499; valaddr_reg:x8; +val_offset:31*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x8, 31*FLEN/8, x9, x4, x5,FLREG) + +inst_50:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x244 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xfa44; valaddr_reg:x8; +val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x8, 32*FLEN/8, x9, x4, x5,FLREG) + +inst_51:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xfbff; valaddr_reg:x8; +val_offset:33*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x8, 33*FLEN/8, x9, x4, x5,FLREG) + +inst_52:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x267 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x267; valaddr_reg:x8; +val_offset:34*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x8, 34*FLEN/8, x9, x4, x5,FLREG) + +inst_53:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x073 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x473; valaddr_reg:x8; +val_offset:35*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x8, 35*FLEN/8, x9, x4, x5,FLREG) + +inst_54:// fs1 == 0 and fe1 == 0x02 and fm1 == 0x31a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xb1a; valaddr_reg:x8; +val_offset:36*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x8, 36*FLEN/8, x9, x4, x5,FLREG) + +inst_55:// fs1 == 0 and fe1 == 0x03 and fm1 == 0x062 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xc62; valaddr_reg:x8; +val_offset:37*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x8, 37*FLEN/8, x9, x4, x5,FLREG) + +inst_56:// fs1 == 0 and fe1 == 0x04 and fm1 == 0x0aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x10aa; valaddr_reg:x8; +val_offset:38*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x8, 38*FLEN/8, x9, x4, x5,FLREG) + +inst_57:// fs1 == 0 and fe1 == 0x05 and fm1 == 0x33a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x173a; valaddr_reg:x8; +val_offset:39*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x8, 39*FLEN/8, x9, x4, x5,FLREG) + +inst_58:// fs1 == 0 and fe1 == 0x06 and fm1 == 0x3ca and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x1bca; valaddr_reg:x8; +val_offset:40*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x8, 40*FLEN/8, x9, x4, x5,FLREG) + +inst_59:// fs1 == 0 and fe1 == 0x07 and fm1 == 0x1bb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x1dbb; valaddr_reg:x8; +val_offset:41*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x8, 41*FLEN/8, x9, x4, x5,FLREG) + +inst_60:// fs1 == 0 and fe1 == 0x08 and fm1 == 0x1a8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x21a8; valaddr_reg:x8; +val_offset:42*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x8, 42*FLEN/8, x9, x4, x5,FLREG) + +inst_61:// fs1 == 0 and fe1 == 0x09 and fm1 == 0x0fb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x24fb; valaddr_reg:x8; +val_offset:43*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x8, 43*FLEN/8, x9, x4, x5,FLREG) + +inst_62:// fs1 == 0 and fe1 == 0x0a and fm1 == 0x119 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x2919; valaddr_reg:x8; +val_offset:44*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x8, 44*FLEN/8, x9, x4, x5,FLREG) + +inst_63:// fs1 == 0 and fe1 == 0x0b and fm1 == 0x278 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x2e78; valaddr_reg:x8; +val_offset:45*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x8, 45*FLEN/8, x9, x4, x5,FLREG) + +inst_64:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0b6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x30b6; valaddr_reg:x8; +val_offset:46*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x8, 46*FLEN/8, x9, x4, x5,FLREG) + +inst_65:// fs1 == 0 and fe1 == 0x0d and fm1 == 0x07a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x347a; valaddr_reg:x8; +val_offset:47*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x8, 47*FLEN/8, x9, x4, x5,FLREG) + +inst_66:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1d2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x39d2; valaddr_reg:x8; +val_offset:48*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x8, 48*FLEN/8, x9, x4, x5,FLREG) + +inst_67:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x0a8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x3ca8; valaddr_reg:x8; +val_offset:49*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x8, 49*FLEN/8, x9, x4, x5,FLREG) + +inst_68:// fs1 == 0 and fe1 == 0x10 and fm1 == 0x298 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x4298; valaddr_reg:x8; +val_offset:50*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x8, 50*FLEN/8, x9, x4, x5,FLREG) + +inst_69:// fs1 == 0 and fe1 == 0x11 and fm1 == 0x348 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x4748; valaddr_reg:x8; +val_offset:51*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x8, 51*FLEN/8, x9, x4, x5,FLREG) + +inst_70:// fs1 == 0 and fe1 == 0x16 and fm1 == 0x31c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x5b1c; valaddr_reg:x8; +val_offset:52*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x8, 52*FLEN/8, x9, x4, x5,FLREG) + +inst_71:// fs1 == 0 and fe1 == 0x18 and fm1 == 0x317 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x6317; valaddr_reg:x8; +val_offset:53*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x8, 53*FLEN/8, x9, x4, x5,FLREG) + +inst_72:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x2a5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x86a5; valaddr_reg:x8; +val_offset:54*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x8, 54*FLEN/8, x9, x4, x5,FLREG) + +inst_73:// fs1 == 1 and fe1 == 0x03 and fm1 == 0x312 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x8f12; valaddr_reg:x8; +val_offset:55*FLEN/8; rmval:dyn; correctval:??; testreg:x5; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x8, 55*FLEN/8, x9, x4, x5,FLREG) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(12873,32,FLEN) +NAN_BOXED(13751,32,FLEN) +NAN_BOXED(14927,32,FLEN) +NAN_BOXED(15571,32,FLEN) +NAN_BOXED(17216,32,FLEN) +NAN_BOXED(18251,32,FLEN) +NAN_BOXED(51869,16,FLEN) +NAN_BOXED(19620,32,FLEN) +NAN_BOXED(21013,32,FLEN) +NAN_BOXED(21839,32,FLEN) +NAN_BOXED(55551,16,FLEN) +NAN_BOXED(57295,16,FLEN) +NAN_BOXED(25596,32,FLEN) +NAN_BOXED(25645,32,FLEN) +NAN_BOXED(27504,32,FLEN) +NAN_BOXED(28265,32,FLEN) +NAN_BOXED(29062,32,FLEN) +NAN_BOXED(62754,16,FLEN) +test_dataset_1: +NAN_BOXED(31411,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(33470,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(34952,16,FLEN) +NAN_BOXED(36626,16,FLEN) +NAN_BOXED(37869,16,FLEN) +NAN_BOXED(38880,16,FLEN) +NAN_BOXED(39540,16,FLEN) +NAN_BOXED(39981,16,FLEN) +NAN_BOXED(40964,16,FLEN) +NAN_BOXED(42121,16,FLEN) +NAN_BOXED(43971,16,FLEN) +NAN_BOXED(44342,16,FLEN) +NAN_BOXED(45430,16,FLEN) +NAN_BOXED(46999,16,FLEN) +NAN_BOXED(47425,16,FLEN) +NAN_BOXED(48690,16,FLEN) +NAN_BOXED(49598,16,FLEN) +NAN_BOXED(50242,16,FLEN) +NAN_BOXED(51798,16,FLEN) +NAN_BOXED(53088,16,FLEN) +NAN_BOXED(53408,16,FLEN) +NAN_BOXED(54501,16,FLEN) +NAN_BOXED(55718,16,FLEN) +NAN_BOXED(56357,16,FLEN) +NAN_BOXED(57852,16,FLEN) +NAN_BOXED(59205,16,FLEN) +NAN_BOXED(60065,16,FLEN) +NAN_BOXED(60962,16,FLEN) +NAN_BOXED(62315,16,FLEN) +NAN_BOXED(62617,16,FLEN) +NAN_BOXED(64068,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(615,16,FLEN) +NAN_BOXED(1139,16,FLEN) +NAN_BOXED(2842,16,FLEN) +NAN_BOXED(3170,16,FLEN) +NAN_BOXED(4266,16,FLEN) +NAN_BOXED(5946,16,FLEN) +NAN_BOXED(7114,16,FLEN) +NAN_BOXED(7611,16,FLEN) +NAN_BOXED(8616,16,FLEN) +NAN_BOXED(9467,16,FLEN) +NAN_BOXED(10521,16,FLEN) +NAN_BOXED(11896,16,FLEN) +NAN_BOXED(12470,16,FLEN) +NAN_BOXED(13434,16,FLEN) +NAN_BOXED(14802,16,FLEN) +NAN_BOXED(15528,16,FLEN) +NAN_BOXED(17048,16,FLEN) +NAN_BOXED(18248,16,FLEN) +NAN_BOXED(23324,16,FLEN) +NAN_BOXED(25367,16,FLEN) +NAN_BOXED(34469,16,FLEN) +NAN_BOXED(36626,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x3_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x3_1: + .fill 40*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x4_0: + .fill 108*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/Zhinx/src/fcvt.l.h_b23-01.S b/riscv-test-suite/rv64i_m/Zhinx/src/fcvt.l.h_b23-01.S new file mode 100644 index 000000000..2ee451a97 --- /dev/null +++ b/riscv-test-suite/rv64i_m/Zhinx/src/fcvt.l.h_b23-01.S @@ -0,0 +1,426 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 04:45:28 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64Zhinx/rv64h_fcvt.l.h.cgf \ + \ +// -- xlen 64 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.l.h instruction of the RISC-V RV64_Zfinx_Zhinx extension for the fcvt.l.h_b23 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fcvt.l.h_b23) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x20,test_dataset_0) +RVTEST_SIGBASE(x2,signature_x2_1) + +inst_0:// rs1 == rd, rs1==x14, rd==x14,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x14; dest:x14; op1val:0x77fc; valaddr_reg:x20; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x14, x14, dyn, 0, 0, x20, 0*FLEN/8, x22, x2, x4,FLREG) + +inst_1:// rs1 != rd, rs1==x13, rd==x27,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x13; dest:x27; op1val:0x77fc; valaddr_reg:x20; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.l.h, x27, x13, dyn, 32, 0, x20, 1*FLEN/8, x22, x2, x4,FLREG) + +inst_2:// rs1==x26, rd==x29,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x26; dest:x29; op1val:0x77fc; valaddr_reg:x20; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.l.h, x29, x26, dyn, 64, 0, x20, 2*FLEN/8, x22, x2, x4,FLREG) + +inst_3:// rs1==x12, rd==x16,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x12; dest:x16; op1val:0x77fc; valaddr_reg:x20; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.l.h, x16, x12, dyn, 96, 0, x20, 3*FLEN/8, x22, x2, x4,FLREG) + +inst_4:// rs1==x7, rd==x0,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x7; dest:x0; op1val:0x77fc; valaddr_reg:x20; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.l.h, x0, x7, dyn, 128, 0, x20, 4*FLEN/8, x22, x2, x4,FLREG) + +inst_5:// rs1==x27, rd==x6,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x27; dest:x6; op1val:0x77fd; valaddr_reg:x20; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x6, x27, dyn, 0, 0, x20, 5*FLEN/8, x22, x2, x4,FLREG) + +inst_6:// rs1==x25, rd==x11,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x25; dest:x11; op1val:0x77fd; valaddr_reg:x20; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.l.h, x11, x25, dyn, 32, 0, x20, 6*FLEN/8, x22, x2, x4,FLREG) + +inst_7:// rs1==x6, rd==x9,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x6; dest:x9; op1val:0x77fd; valaddr_reg:x20; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.l.h, x9, x6, dyn, 64, 0, x20, 7*FLEN/8, x22, x2, x4,FLREG) + +inst_8:// rs1==x5, rd==x25,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x5; dest:x25; op1val:0x77fd; valaddr_reg:x20; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.l.h, x25, x5, dyn, 96, 0, x20, 8*FLEN/8, x22, x2, x4,FLREG) + +inst_9:// rs1==x17, rd==x5,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x17; dest:x5; op1val:0x77fd; valaddr_reg:x20; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.l.h, x5, x17, dyn, 128, 0, x20, 9*FLEN/8, x22, x2, x4,FLREG) + +inst_10:// rs1==x18, rd==x28,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x18; dest:x28; op1val:0x77fe; valaddr_reg:x20; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x28, x18, dyn, 0, 0, x20, 10*FLEN/8, x22, x2, x4,FLREG) + +inst_11:// rs1==x11, rd==x13,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x11; dest:x13; op1val:0x77fe; valaddr_reg:x20; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.l.h, x13, x11, dyn, 32, 0, x20, 11*FLEN/8, x22, x2, x4,FLREG) + +inst_12:// rs1==x31, rd==x10,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x31; dest:x10; op1val:0x77fe; valaddr_reg:x20; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.l.h, x10, x31, dyn, 64, 0, x20, 12*FLEN/8, x22, x2, x4,FLREG) + +inst_13:// rs1==x8, rd==x21,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x8; dest:x21; op1val:0x77fe; valaddr_reg:x20; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.l.h, x21, x8, dyn, 96, 0, x20, 13*FLEN/8, x22, x2, x4,FLREG) + +inst_14:// rs1==x9, rd==x7,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x9; dest:x7; op1val:0x77fe; valaddr_reg:x20; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.l.h, x7, x9, dyn, 128, 0, x20, 14*FLEN/8, x22, x2, x4,FLREG) + +inst_15:// rs1==x19, rd==x18,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x19; dest:x18; op1val:0x77ff; valaddr_reg:x20; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x18, x19, dyn, 0, 0, x20, 15*FLEN/8, x22, x2, x4,FLREG) + +inst_16:// rs1==x15, rd==x31,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x15; dest:x31; op1val:0x77ff; valaddr_reg:x20; +val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.l.h, x31, x15, dyn, 32, 0, x20, 16*FLEN/8, x22, x2, x4,FLREG) + +inst_17:// rs1==x0, rd==x1,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x0; dest:x1; op1val:0x0; valaddr_reg:x20; +val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.l.h, x1, x0, dyn, 64, 0, x20, 17*FLEN/8, x22, x2, x4,FLREG) + +inst_18:// rs1==x21, rd==x12,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x21; dest:x12; op1val:0x77ff; valaddr_reg:x20; +val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.l.h, x12, x21, dyn, 96, 0, x20, 18*FLEN/8, x22, x2, x4,FLREG) + +inst_19:// rs1==x3, rd==x26,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x3; dest:x26; op1val:0x77ff; valaddr_reg:x20; +val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.l.h, x26, x3, dyn, 128, 0, x20, 19*FLEN/8, x22, x2, x4,FLREG) +RVTEST_VALBASEUPD(x7,test_dataset_1) + +inst_20:// rs1==x22, rd==x23,fs1 == 0 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x22; dest:x23; op1val:0x7800; valaddr_reg:x7; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x23, x22, dyn, 0, 0, x7, 0*FLEN/8, x9, x2, x4,FLREG) + +inst_21:// rs1==x23, rd==x20,fs1 == 0 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x23; dest:x20; op1val:0x7800; valaddr_reg:x7; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x6; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.l.h, x20, x23, dyn, 32, 0, x7, 1*FLEN/8, x9, x2, x6,FLREG) +RVTEST_SIGBASE(x5,signature_x5_0) + +inst_22:// rs1==x24, rd==x3,fs1 == 0 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x24; dest:x3; op1val:0x7800; valaddr_reg:x7; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x6; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.l.h, x3, x24, dyn, 64, 0, x7, 2*FLEN/8, x9, x5, x6,FLREG) + +inst_23:// rs1==x2, rd==x30,fs1 == 0 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x2; dest:x30; op1val:0x7800; valaddr_reg:x7; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x6; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.l.h, x30, x2, dyn, 96, 0, x7, 3*FLEN/8, x9, x5, x6,FLREG) + +inst_24:// rs1==x30, rd==x19,fs1 == 0 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x19; op1val:0x7800; valaddr_reg:x7; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x6; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.l.h, x19, x30, dyn, 128, 0, x7, 4*FLEN/8, x9, x5, x6,FLREG) + +inst_25:// rs1==x28, rd==x17,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x28; dest:x17; op1val:0x7801; valaddr_reg:x7; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x6; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x17, x28, dyn, 0, 0, x7, 5*FLEN/8, x9, x5, x6,FLREG) + +inst_26:// rs1==x16, rd==x15,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x16; dest:x15; op1val:0x7801; valaddr_reg:x7; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x6; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.l.h, x15, x16, dyn, 32, 0, x7, 6*FLEN/8, x9, x5, x6,FLREG) + +inst_27:// rs1==x20, rd==x22,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x20; dest:x22; op1val:0x7801; valaddr_reg:x7; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x6; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.l.h, x22, x20, dyn, 64, 0, x7, 7*FLEN/8, x9, x5, x6,FLREG) + +inst_28:// rs1==x1, rd==x4,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x1; dest:x4; op1val:0x7801; valaddr_reg:x7; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x6; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.l.h, x4, x1, dyn, 96, 0, x7, 8*FLEN/8, x9, x5, x6,FLREG) + +inst_29:// rs1==x10, rd==x8,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x10; dest:x8; op1val:0x7801; valaddr_reg:x7; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x6; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.l.h, x8, x10, dyn, 128, 0, x7, 9*FLEN/8, x9, x5, x6,FLREG) + +inst_30:// rs1==x29, rd==x2,fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x29; dest:x2; op1val:0x7802; valaddr_reg:x7; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x6; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x2, x29, dyn, 0, 0, x7, 10*FLEN/8, x9, x5, x6,FLREG) + +inst_31:// rs1==x4, rd==x24,fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x4; dest:x24; op1val:0x7802; valaddr_reg:x7; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x6; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.l.h, x24, x4, dyn, 32, 0, x7, 11*FLEN/8, x9, x5, x6,FLREG) + +inst_32:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x7802; valaddr_reg:x7; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x6; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 64, 0, x7, 12*FLEN/8, x9, x5, x6,FLREG) + +inst_33:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x7802; valaddr_reg:x7; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x6; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 96, 0, x7, 13*FLEN/8, x9, x5, x6,FLREG) + +inst_34:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x7802; valaddr_reg:x7; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x6; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 128, 0, x7, 14*FLEN/8, x9, x5, x6,FLREG) + +inst_35:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x7803; valaddr_reg:x7; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x6; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x7, 15*FLEN/8, x9, x5, x6,FLREG) + +inst_36:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x003 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x7803; valaddr_reg:x7; +val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x6; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 32, 0, x7, 16*FLEN/8, x9, x5, x6,FLREG) + +inst_37:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x003 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x7803; valaddr_reg:x7; +val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x6; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 64, 0, x7, 17*FLEN/8, x9, x5, x6,FLREG) + +inst_38:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x003 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x7803; valaddr_reg:x7; +val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x6; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 96, 0, x7, 18*FLEN/8, x9, x5, x6,FLREG) + +inst_39:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x003 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x7803; valaddr_reg:x7; +val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x6; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 128, 0, x7, 19*FLEN/8, x9, x5, x6,FLREG) + +inst_40:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x7804; valaddr_reg:x7; +val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x6; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x7, 20*FLEN/8, x9, x5, x6,FLREG) + +inst_41:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x7804; valaddr_reg:x7; +val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x6; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 32, 0, x7, 21*FLEN/8, x9, x5, x6,FLREG) + +inst_42:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x7804; valaddr_reg:x7; +val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x6; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 64, 0, x7, 22*FLEN/8, x9, x5, x6,FLREG) + +inst_43:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x7804; valaddr_reg:x7; +val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x6; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 96, 0, x7, 23*FLEN/8, x9, x5, x6,FLREG) + +inst_44:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x7804; valaddr_reg:x7; +val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x6; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 128, 0, x7, 24*FLEN/8, x9, x5, x6,FLREG) + +inst_45:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x77fc; valaddr_reg:x7; +val_offset:25*FLEN/8; rmval:dyn; correctval:??; testreg:x6; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 128, 0, x7, 25*FLEN/8, x9, x5, x6,FLREG) + +inst_46:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x77ff; valaddr_reg:x7; +val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x6; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 64, 0, x7, 26*FLEN/8, x9, x5, x6,FLREG) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(30716,32,FLEN) +NAN_BOXED(30716,32,FLEN) +NAN_BOXED(30716,32,FLEN) +NAN_BOXED(30716,32,FLEN) +NAN_BOXED(30716,32,FLEN) +NAN_BOXED(30717,32,FLEN) +NAN_BOXED(30717,32,FLEN) +NAN_BOXED(30717,32,FLEN) +NAN_BOXED(30717,32,FLEN) +NAN_BOXED(30717,32,FLEN) +NAN_BOXED(30718,32,FLEN) +NAN_BOXED(30718,32,FLEN) +NAN_BOXED(30718,32,FLEN) +NAN_BOXED(30718,32,FLEN) +NAN_BOXED(30718,32,FLEN) +NAN_BOXED(30719,32,FLEN) +NAN_BOXED(30719,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(30719,32,FLEN) +NAN_BOXED(30719,32,FLEN) +test_dataset_1: +NAN_BOXED(30720,16,FLEN) +NAN_BOXED(30720,16,FLEN) +NAN_BOXED(30720,16,FLEN) +NAN_BOXED(30720,16,FLEN) +NAN_BOXED(30720,16,FLEN) +NAN_BOXED(30721,16,FLEN) +NAN_BOXED(30721,16,FLEN) +NAN_BOXED(30721,16,FLEN) +NAN_BOXED(30721,16,FLEN) +NAN_BOXED(30721,16,FLEN) +NAN_BOXED(30722,16,FLEN) +NAN_BOXED(30722,16,FLEN) +NAN_BOXED(30722,16,FLEN) +NAN_BOXED(30722,16,FLEN) +NAN_BOXED(30722,16,FLEN) +NAN_BOXED(30723,16,FLEN) +NAN_BOXED(30723,16,FLEN) +NAN_BOXED(30723,16,FLEN) +NAN_BOXED(30723,16,FLEN) +NAN_BOXED(30723,16,FLEN) +NAN_BOXED(30724,16,FLEN) +NAN_BOXED(30724,16,FLEN) +NAN_BOXED(30724,16,FLEN) +NAN_BOXED(30724,16,FLEN) +NAN_BOXED(30724,16,FLEN) +NAN_BOXED(30716,16,FLEN) +NAN_BOXED(30719,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x2_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_1: + .fill 44*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x5_0: + .fill 50*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/Zhinx/src/fcvt.l.h_b24-01.S b/riscv-test-suite/rv64i_m/Zhinx/src/fcvt.l.h_b24-01.S new file mode 100644 index 000000000..1bff75e1b --- /dev/null +++ b/riscv-test-suite/rv64i_m/Zhinx/src/fcvt.l.h_b24-01.S @@ -0,0 +1,848 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 04:45:28 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64Zhinx/rv64h_fcvt.l.h.cgf \ + \ +// -- xlen 64 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.l.h instruction of the RISC-V RV64_Zfinx_Zhinx extension for the fcvt.l.h_b24 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fcvt.l.h_b24) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x7,test_dataset_0) +RVTEST_SIGBASE(x11,signature_x11_1) + +inst_0:// rs1 == rd, rs1==x24, rd==x24,fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x24; dest:x24; op1val:0xbc00; valaddr_reg:x7; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x24, x24, dyn, 0, 0, x7, 0*FLEN/8, x17, x11, x13,FLREG) + +inst_1:// rs1 != rd, rs1==x25, rd==x1,fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x25; dest:x1; op1val:0xbc00; valaddr_reg:x7; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.l.h, x1, x25, dyn, 32, 0, x7, 1*FLEN/8, x17, x11, x13,FLREG) + +inst_2:// rs1==x9, rd==x4,fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x9; dest:x4; op1val:0xbc00; valaddr_reg:x7; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.l.h, x4, x9, dyn, 64, 0, x7, 2*FLEN/8, x17, x11, x13,FLREG) + +inst_3:// rs1==x6, rd==x19,fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x6; dest:x19; op1val:0xbc00; valaddr_reg:x7; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.l.h, x19, x6, dyn, 96, 0, x7, 3*FLEN/8, x17, x11, x13,FLREG) + +inst_4:// rs1==x5, rd==x18,fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x5; dest:x18; op1val:0xbc00; valaddr_reg:x7; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.l.h, x18, x5, dyn, 128, 0, x7, 4*FLEN/8, x17, x11, x13,FLREG) + +inst_5:// rs1==x31, rd==x8,fs1 == 0 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x31; dest:x8; op1val:0x3beb; valaddr_reg:x7; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x8, x31, dyn, 0, 0, x7, 5*FLEN/8, x17, x11, x13,FLREG) + +inst_6:// rs1==x12, rd==x6,fs1 == 0 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x12; dest:x6; op1val:0x3beb; valaddr_reg:x7; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.l.h, x6, x12, dyn, 32, 0, x7, 6*FLEN/8, x17, x11, x13,FLREG) + +inst_7:// rs1==x20, rd==x27,fs1 == 0 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x20; dest:x27; op1val:0x3beb; valaddr_reg:x7; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.l.h, x27, x20, dyn, 64, 0, x7, 7*FLEN/8, x17, x11, x13,FLREG) + +inst_8:// rs1==x21, rd==x30,fs1 == 0 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x21; dest:x30; op1val:0x3beb; valaddr_reg:x7; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.l.h, x30, x21, dyn, 96, 0, x7, 8*FLEN/8, x17, x11, x13,FLREG) + +inst_9:// rs1==x28, rd==x15,fs1 == 0 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x28; dest:x15; op1val:0x3beb; valaddr_reg:x7; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.l.h, x15, x28, dyn, 128, 0, x7, 9*FLEN/8, x17, x11, x13,FLREG) + +inst_10:// rs1==x3, rd==x0,fs1 == 1 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x3; dest:x0; op1val:0xbc0a; valaddr_reg:x7; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x0, x3, dyn, 0, 0, x7, 10*FLEN/8, x17, x11, x13,FLREG) + +inst_11:// rs1==x1, rd==x16,fs1 == 1 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x1; dest:x16; op1val:0xbc0a; valaddr_reg:x7; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.l.h, x16, x1, dyn, 32, 0, x7, 11*FLEN/8, x17, x11, x13,FLREG) + +inst_12:// rs1==x14, rd==x2,fs1 == 1 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x14; dest:x2; op1val:0xbc0a; valaddr_reg:x7; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.l.h, x2, x14, dyn, 64, 0, x7, 12*FLEN/8, x17, x11, x13,FLREG) + +inst_13:// rs1==x30, rd==x3,fs1 == 1 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x3; op1val:0xbc0a; valaddr_reg:x7; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.l.h, x3, x30, dyn, 96, 0, x7, 13*FLEN/8, x17, x11, x13,FLREG) + +inst_14:// rs1==x18, rd==x29,fs1 == 1 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x18; dest:x29; op1val:0xbc0a; valaddr_reg:x7; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.l.h, x29, x18, dyn, 128, 0, x7, 14*FLEN/8, x17, x11, x13,FLREG) + +inst_15:// rs1==x10, rd==x14,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x10; dest:x14; op1val:0x3c00; valaddr_reg:x7; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x14, x10, dyn, 0, 0, x7, 15*FLEN/8, x17, x11, x13,FLREG) +RVTEST_VALBASEUPD(x6,test_dataset_1) + +inst_16:// rs1==x4, rd==x7,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x4; dest:x7; op1val:0x3c00; valaddr_reg:x6; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.l.h, x7, x4, dyn, 32, 0, x6, 0*FLEN/8, x14, x11, x13,FLREG) + +inst_17:// rs1==x8, rd==x26,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x8; dest:x26; op1val:0x3c00; valaddr_reg:x6; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.l.h, x26, x8, dyn, 64, 0, x6, 1*FLEN/8, x14, x11, x13,FLREG) + +inst_18:// rs1==x22, rd==x21,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x22; dest:x21; op1val:0x3c00; valaddr_reg:x6; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.l.h, x21, x22, dyn, 96, 0, x6, 2*FLEN/8, x14, x11, x3,FLREG) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_19:// rs1==x0, rd==x20,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x0; dest:x20; op1val:0x0; valaddr_reg:x6; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.l.h, x20, x0, dyn, 128, 0, x6, 3*FLEN/8, x14, x1, x3,FLREG) + +inst_20:// rs1==x29, rd==x10,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x29; dest:x10; op1val:0xf0; valaddr_reg:x6; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x10, x29, dyn, 0, 0, x6, 4*FLEN/8, x14, x1, x3,FLREG) + +inst_21:// rs1==x7, rd==x22,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x7; dest:x22; op1val:0xf0; valaddr_reg:x6; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.l.h, x22, x7, dyn, 32, 0, x6, 5*FLEN/8, x14, x1, x3,FLREG) + +inst_22:// rs1==x26, rd==x11,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x26; dest:x11; op1val:0xf0; valaddr_reg:x6; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.l.h, x11, x26, dyn, 64, 0, x6, 6*FLEN/8, x14, x1, x3,FLREG) + +inst_23:// rs1==x15, rd==x28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x15; dest:x28; op1val:0xf0; valaddr_reg:x6; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.l.h, x28, x15, dyn, 96, 0, x6, 7*FLEN/8, x14, x1, x3,FLREG) + +inst_24:// rs1==x23, rd==x9,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x23; dest:x9; op1val:0xf0; valaddr_reg:x6; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.l.h, x9, x23, dyn, 128, 0, x6, 8*FLEN/8, x14, x1, x3,FLREG) + +inst_25:// rs1==x16, rd==x23,fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x16; dest:x23; op1val:0xaf0a; valaddr_reg:x6; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x23, x16, dyn, 0, 0, x6, 9*FLEN/8, x14, x1, x3,FLREG) + +inst_26:// rs1==x2, rd==x12,fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x2; dest:x12; op1val:0xaf0a; valaddr_reg:x6; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.l.h, x12, x2, dyn, 32, 0, x6, 10*FLEN/8, x14, x1, x3,FLREG) + +inst_27:// rs1==x11, rd==x17,fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x11; dest:x17; op1val:0xaf0a; valaddr_reg:x6; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.l.h, x17, x11, dyn, 64, 0, x6, 11*FLEN/8, x14, x1, x3,FLREG) + +inst_28:// rs1==x27, rd==x13,fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x27; dest:x13; op1val:0xaf0a; valaddr_reg:x6; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.l.h, x13, x27, dyn, 96, 0, x6, 12*FLEN/8, x14, x1, x3,FLREG) + +inst_29:// rs1==x13, rd==x25,fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x13; dest:x25; op1val:0xaf0a; valaddr_reg:x6; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.l.h, x25, x13, dyn, 128, 0, x6, 13*FLEN/8, x14, x1, x3,FLREG) + +inst_30:// rs1==x17, rd==x31,fs1 == 0 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x17; dest:x31; op1val:0x211e; valaddr_reg:x6; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x17, dyn, 0, 0, x6, 14*FLEN/8, x14, x1, x3,FLREG) + +inst_31:// rs1==x19, rd==x5,fs1 == 0 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x19; dest:x5; op1val:0x211e; valaddr_reg:x6; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.l.h, x5, x19, dyn, 32, 0, x6, 15*FLEN/8, x14, x1, x3,FLREG) +RVTEST_VALBASEUPD(x2,test_dataset_2) + +inst_32:// fs1 == 0 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x211e; valaddr_reg:x2; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 64, 0, x2, 0*FLEN/8, x4, x1, x3,FLREG) + +inst_33:// fs1 == 0 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x211e; valaddr_reg:x2; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 96, 0, x2, 1*FLEN/8, x4, x1, x3,FLREG) + +inst_34:// fs1 == 0 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x211e; valaddr_reg:x2; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 128, 0, x2, 2*FLEN/8, x4, x1, x3,FLREG) + +inst_35:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xbbeb; valaddr_reg:x2; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x2, 3*FLEN/8, x4, x1, x3,FLREG) + +inst_36:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xbbeb; valaddr_reg:x2; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 32, 0, x2, 4*FLEN/8, x4, x1, x3,FLREG) + +inst_37:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xbbeb; valaddr_reg:x2; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 64, 0, x2, 5*FLEN/8, x4, x1, x3,FLREG) + +inst_38:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xbbeb; valaddr_reg:x2; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 96, 0, x2, 6*FLEN/8, x4, x1, x3,FLREG) + +inst_39:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xbbeb; valaddr_reg:x2; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 128, 0, x2, 7*FLEN/8, x4, x1, x3,FLREG) + +inst_40:// fs1 == 1 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xa11e; valaddr_reg:x2; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x2, 8*FLEN/8, x4, x1, x3,FLREG) + +inst_41:// fs1 == 1 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xa11e; valaddr_reg:x2; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 32, 0, x2, 9*FLEN/8, x4, x1, x3,FLREG) + +inst_42:// fs1 == 1 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xa11e; valaddr_reg:x2; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 64, 0, x2, 10*FLEN/8, x4, x1, x3,FLREG) + +inst_43:// fs1 == 1 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xa11e; valaddr_reg:x2; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 96, 0, x2, 11*FLEN/8, x4, x1, x3,FLREG) + +inst_44:// fs1 == 1 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xa11e; valaddr_reg:x2; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 128, 0, x2, 12*FLEN/8, x4, x1, x3,FLREG) + +inst_45:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xbb33; valaddr_reg:x2; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x2, 13*FLEN/8, x4, x1, x3,FLREG) + +inst_46:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xbb33; valaddr_reg:x2; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 32, 0, x2, 14*FLEN/8, x4, x1, x3,FLREG) + +inst_47:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xbb33; valaddr_reg:x2; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 64, 0, x2, 15*FLEN/8, x4, x1, x3,FLREG) + +inst_48:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xbb33; valaddr_reg:x2; +val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 96, 0, x2, 16*FLEN/8, x4, x1, x3,FLREG) + +inst_49:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xbb33; valaddr_reg:x2; +val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 128, 0, x2, 17*FLEN/8, x4, x1, x3,FLREG) + +inst_50:// fs1 == 1 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xae66; valaddr_reg:x2; +val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x2, 18*FLEN/8, x4, x1, x3,FLREG) + +inst_51:// fs1 == 1 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xae66; valaddr_reg:x2; +val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 32, 0, x2, 19*FLEN/8, x4, x1, x3,FLREG) + +inst_52:// fs1 == 1 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xae66; valaddr_reg:x2; +val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 64, 0, x2, 20*FLEN/8, x4, x1, x3,FLREG) + +inst_53:// fs1 == 1 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xae66; valaddr_reg:x2; +val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 96, 0, x2, 21*FLEN/8, x4, x1, x3,FLREG) + +inst_54:// fs1 == 1 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xae66; valaddr_reg:x2; +val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 128, 0, x2, 22*FLEN/8, x4, x1, x3,FLREG) + +inst_55:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x3c66; valaddr_reg:x2; +val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x2, 23*FLEN/8, x4, x1, x3,FLREG) + +inst_56:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x3c66; valaddr_reg:x2; +val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 32, 0, x2, 24*FLEN/8, x4, x1, x3,FLREG) + +inst_57:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x3c66; valaddr_reg:x2; +val_offset:25*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 64, 0, x2, 25*FLEN/8, x4, x1, x3,FLREG) + +inst_58:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x3c66; valaddr_reg:x2; +val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 96, 0, x2, 26*FLEN/8, x4, x1, x3,FLREG) + +inst_59:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x3c66; valaddr_reg:x2; +val_offset:27*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 128, 0, x2, 27*FLEN/8, x4, x1, x3,FLREG) + +inst_60:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x3b33; valaddr_reg:x2; +val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x2, 28*FLEN/8, x4, x1, x3,FLREG) + +inst_61:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x3b33; valaddr_reg:x2; +val_offset:29*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 32, 0, x2, 29*FLEN/8, x4, x1, x3,FLREG) + +inst_62:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x3b33; valaddr_reg:x2; +val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 64, 0, x2, 30*FLEN/8, x4, x1, x3,FLREG) + +inst_63:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x3b33; valaddr_reg:x2; +val_offset:31*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 96, 0, x2, 31*FLEN/8, x4, x1, x3,FLREG) + +inst_64:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x3b33; valaddr_reg:x2; +val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 128, 0, x2, 32*FLEN/8, x4, x1, x3,FLREG) + +inst_65:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x3c70; valaddr_reg:x2; +val_offset:33*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x2, 33*FLEN/8, x4, x1, x3,FLREG) + +inst_66:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x3c70; valaddr_reg:x2; +val_offset:34*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 32, 0, x2, 34*FLEN/8, x4, x1, x3,FLREG) + +inst_67:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x3c70; valaddr_reg:x2; +val_offset:35*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 64, 0, x2, 35*FLEN/8, x4, x1, x3,FLREG) + +inst_68:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x3c70; valaddr_reg:x2; +val_offset:36*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 96, 0, x2, 36*FLEN/8, x4, x1, x3,FLREG) + +inst_69:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x3c70; valaddr_reg:x2; +val_offset:37*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 128, 0, x2, 37*FLEN/8, x4, x1, x3,FLREG) + +inst_70:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xbc70; valaddr_reg:x2; +val_offset:38*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x2, 38*FLEN/8, x4, x1, x3,FLREG) + +inst_71:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xbc70; valaddr_reg:x2; +val_offset:39*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 32, 0, x2, 39*FLEN/8, x4, x1, x3,FLREG) + +inst_72:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xbc70; valaddr_reg:x2; +val_offset:40*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 64, 0, x2, 40*FLEN/8, x4, x1, x3,FLREG) + +inst_73:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xbc70; valaddr_reg:x2; +val_offset:41*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 96, 0, x2, 41*FLEN/8, x4, x1, x3,FLREG) + +inst_74:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xbc70; valaddr_reg:x2; +val_offset:42*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 128, 0, x2, 42*FLEN/8, x4, x1, x3,FLREG) + +inst_75:// fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x2e66; valaddr_reg:x2; +val_offset:43*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x2, 43*FLEN/8, x4, x1, x3,FLREG) + +inst_76:// fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x2e66; valaddr_reg:x2; +val_offset:44*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 32, 0, x2, 44*FLEN/8, x4, x1, x3,FLREG) + +inst_77:// fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x2e66; valaddr_reg:x2; +val_offset:45*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 64, 0, x2, 45*FLEN/8, x4, x1, x3,FLREG) + +inst_78:// fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x2e66; valaddr_reg:x2; +val_offset:46*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 96, 0, x2, 46*FLEN/8, x4, x1, x3,FLREG) + +inst_79:// fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x2e66; valaddr_reg:x2; +val_offset:47*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 128, 0, x2, 47*FLEN/8, x4, x1, x3,FLREG) + +inst_80:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xbb1e; valaddr_reg:x2; +val_offset:48*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x2, 48*FLEN/8, x4, x1, x3,FLREG) + +inst_81:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xbb1e; valaddr_reg:x2; +val_offset:49*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 32, 0, x2, 49*FLEN/8, x4, x1, x3,FLREG) + +inst_82:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xbb1e; valaddr_reg:x2; +val_offset:50*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 64, 0, x2, 50*FLEN/8, x4, x1, x3,FLREG) + +inst_83:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xbb1e; valaddr_reg:x2; +val_offset:51*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 96, 0, x2, 51*FLEN/8, x4, x1, x3,FLREG) + +inst_84:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xbb1e; valaddr_reg:x2; +val_offset:52*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 128, 0, x2, 52*FLEN/8, x4, x1, x3,FLREG) + +inst_85:// fs1 == 0 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x2f0a; valaddr_reg:x2; +val_offset:53*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x2, 53*FLEN/8, x4, x1, x3,FLREG) + +inst_86:// fs1 == 0 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x2f0a; valaddr_reg:x2; +val_offset:54*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 32, 0, x2, 54*FLEN/8, x4, x1, x3,FLREG) + +inst_87:// fs1 == 0 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x2f0a; valaddr_reg:x2; +val_offset:55*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 64, 0, x2, 55*FLEN/8, x4, x1, x3,FLREG) + +inst_88:// fs1 == 0 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x2f0a; valaddr_reg:x2; +val_offset:56*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 96, 0, x2, 56*FLEN/8, x4, x1, x3,FLREG) + +inst_89:// fs1 == 0 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x2f0a; valaddr_reg:x2; +val_offset:57*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 128, 0, x2, 57*FLEN/8, x4, x1, x3,FLREG) + +inst_90:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x3c0a; valaddr_reg:x2; +val_offset:58*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x2, 58*FLEN/8, x4, x1, x3,FLREG) + +inst_91:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x3c0a; valaddr_reg:x2; +val_offset:59*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 32, 0, x2, 59*FLEN/8, x4, x1, x3,FLREG) + +inst_92:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x3c0a; valaddr_reg:x2; +val_offset:60*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 64, 0, x2, 60*FLEN/8, x4, x1, x3,FLREG) + +inst_93:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x3c0a; valaddr_reg:x2; +val_offset:61*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 96, 0, x2, 61*FLEN/8, x4, x1, x3,FLREG) + +inst_94:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x3c0a; valaddr_reg:x2; +val_offset:62*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 128, 0, x2, 62*FLEN/8, x4, x1, x3,FLREG) + +inst_95:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xbc66; valaddr_reg:x2; +val_offset:63*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x2, 63*FLEN/8, x4, x1, x3,FLREG) + +inst_96:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xbc66; valaddr_reg:x2; +val_offset:64*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 32, 0, x2, 64*FLEN/8, x4, x1, x3,FLREG) + +inst_97:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xbc66; valaddr_reg:x2; +val_offset:65*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 64, 0, x2, 65*FLEN/8, x4, x1, x3,FLREG) + +inst_98:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xbc66; valaddr_reg:x2; +val_offset:66*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 96, 0, x2, 66*FLEN/8, x4, x1, x3,FLREG) + +inst_99:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xbc66; valaddr_reg:x2; +val_offset:67*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 128, 0, x2, 67*FLEN/8, x4, x1, x3,FLREG) + +inst_100:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x3b1e; valaddr_reg:x2; +val_offset:68*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x2, 68*FLEN/8, x4, x1, x3,FLREG) + +inst_101:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x3b1e; valaddr_reg:x2; +val_offset:69*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 32, 0, x2, 69*FLEN/8, x4, x1, x3,FLREG) + +inst_102:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x3b1e; valaddr_reg:x2; +val_offset:70*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 64, 0, x2, 70*FLEN/8, x4, x1, x3,FLREG) + +inst_103:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x3b1e; valaddr_reg:x2; +val_offset:71*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 96, 0, x2, 71*FLEN/8, x4, x1, x3,FLREG) + +inst_104:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x3b1e; valaddr_reg:x2; +val_offset:72*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 128, 0, x2, 72*FLEN/8, x4, x1, x3,FLREG) + +inst_105:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xbc0a; valaddr_reg:x2; +val_offset:73*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x2, 73*FLEN/8, x4, x1, x3,FLREG) + +inst_106:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x3c00; valaddr_reg:x2; +val_offset:74*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 128, 0, x2, 74*FLEN/8, x4, x1, x3,FLREG) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(15339,32,FLEN) +NAN_BOXED(15339,32,FLEN) +NAN_BOXED(15339,32,FLEN) +NAN_BOXED(15339,32,FLEN) +NAN_BOXED(15339,32,FLEN) +NAN_BOXED(48138,16,FLEN) +NAN_BOXED(48138,16,FLEN) +NAN_BOXED(48138,16,FLEN) +NAN_BOXED(48138,16,FLEN) +NAN_BOXED(48138,16,FLEN) +NAN_BOXED(15360,32,FLEN) +test_dataset_1: +NAN_BOXED(15360,32,FLEN) +NAN_BOXED(15360,32,FLEN) +NAN_BOXED(15360,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(240,32,FLEN) +NAN_BOXED(240,32,FLEN) +NAN_BOXED(240,32,FLEN) +NAN_BOXED(240,32,FLEN) +NAN_BOXED(240,32,FLEN) +NAN_BOXED(44810,16,FLEN) +NAN_BOXED(44810,16,FLEN) +NAN_BOXED(44810,16,FLEN) +NAN_BOXED(44810,16,FLEN) +NAN_BOXED(44810,16,FLEN) +NAN_BOXED(8478,32,FLEN) +NAN_BOXED(8478,32,FLEN) +test_dataset_2: +NAN_BOXED(8478,16,FLEN) +NAN_BOXED(8478,16,FLEN) +NAN_BOXED(8478,16,FLEN) +NAN_BOXED(48107,16,FLEN) +NAN_BOXED(48107,16,FLEN) +NAN_BOXED(48107,16,FLEN) +NAN_BOXED(48107,16,FLEN) +NAN_BOXED(48107,16,FLEN) +NAN_BOXED(41246,16,FLEN) +NAN_BOXED(41246,16,FLEN) +NAN_BOXED(41246,16,FLEN) +NAN_BOXED(41246,16,FLEN) +NAN_BOXED(41246,16,FLEN) +NAN_BOXED(47923,16,FLEN) +NAN_BOXED(47923,16,FLEN) +NAN_BOXED(47923,16,FLEN) +NAN_BOXED(47923,16,FLEN) +NAN_BOXED(47923,16,FLEN) +NAN_BOXED(44646,16,FLEN) +NAN_BOXED(44646,16,FLEN) +NAN_BOXED(44646,16,FLEN) +NAN_BOXED(44646,16,FLEN) +NAN_BOXED(44646,16,FLEN) +NAN_BOXED(15462,16,FLEN) +NAN_BOXED(15462,16,FLEN) +NAN_BOXED(15462,16,FLEN) +NAN_BOXED(15462,16,FLEN) +NAN_BOXED(15462,16,FLEN) +NAN_BOXED(15155,16,FLEN) +NAN_BOXED(15155,16,FLEN) +NAN_BOXED(15155,16,FLEN) +NAN_BOXED(15155,16,FLEN) +NAN_BOXED(15155,16,FLEN) +NAN_BOXED(15472,16,FLEN) +NAN_BOXED(15472,16,FLEN) +NAN_BOXED(15472,16,FLEN) +NAN_BOXED(15472,16,FLEN) +NAN_BOXED(15472,16,FLEN) +NAN_BOXED(48240,16,FLEN) +NAN_BOXED(48240,16,FLEN) +NAN_BOXED(48240,16,FLEN) +NAN_BOXED(48240,16,FLEN) +NAN_BOXED(48240,16,FLEN) +NAN_BOXED(11878,16,FLEN) +NAN_BOXED(11878,16,FLEN) +NAN_BOXED(11878,16,FLEN) +NAN_BOXED(11878,16,FLEN) +NAN_BOXED(11878,16,FLEN) +NAN_BOXED(47902,16,FLEN) +NAN_BOXED(47902,16,FLEN) +NAN_BOXED(47902,16,FLEN) +NAN_BOXED(47902,16,FLEN) +NAN_BOXED(47902,16,FLEN) +NAN_BOXED(12042,16,FLEN) +NAN_BOXED(12042,16,FLEN) +NAN_BOXED(12042,16,FLEN) +NAN_BOXED(12042,16,FLEN) +NAN_BOXED(12042,16,FLEN) +NAN_BOXED(15370,16,FLEN) +NAN_BOXED(15370,16,FLEN) +NAN_BOXED(15370,16,FLEN) +NAN_BOXED(15370,16,FLEN) +NAN_BOXED(15370,16,FLEN) +NAN_BOXED(48230,16,FLEN) +NAN_BOXED(48230,16,FLEN) +NAN_BOXED(48230,16,FLEN) +NAN_BOXED(48230,16,FLEN) +NAN_BOXED(48230,16,FLEN) +NAN_BOXED(15134,16,FLEN) +NAN_BOXED(15134,16,FLEN) +NAN_BOXED(15134,16,FLEN) +NAN_BOXED(15134,16,FLEN) +NAN_BOXED(15134,16,FLEN) +NAN_BOXED(48138,16,FLEN) +NAN_BOXED(15360,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x11_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x11_1: + .fill 38*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_0: + .fill 176*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/Zhinx/src/fcvt.l.h_b27-01.S b/riscv-test-suite/rv64i_m/Zhinx/src/fcvt.l.h_b27-01.S new file mode 100644 index 000000000..24ac61137 --- /dev/null +++ b/riscv-test-suite/rv64i_m/Zhinx/src/fcvt.l.h_b27-01.S @@ -0,0 +1,328 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 04:45:28 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64Zhinx/rv64h_fcvt.l.h.cgf \ + \ +// -- xlen 64 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.l.h instruction of the RISC-V RV64_Zfinx_Zhinx extension for the fcvt.l.h_b27 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fcvt.l.h_b27) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x6,test_dataset_0) +RVTEST_SIGBASE(x13,signature_x13_1) + +inst_0:// rs1 == rd, rs1==x10, rd==x10,fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x10; dest:x10; op1val:0x7c01; valaddr_reg:x6; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x24; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x10, x10, dyn, 0, 0, x6, 0*FLEN/8, x18, x13, x24,FLREG) + +inst_1:// rs1 != rd, rs1==x0, rd==x3,fs1 == 1 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x0; dest:x3; op1val:0x0; valaddr_reg:x6; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x24; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x3, x0, dyn, 0, 0, x6, 1*FLEN/8, x18, x13, x24,FLREG) + +inst_2:// rs1==x28, rd==x22,fs1 == 0 and fe1 == 0x1f and fm1 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x28; dest:x22; op1val:0x7d55; valaddr_reg:x6; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x24; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x22, x28, dyn, 0, 0, x6, 2*FLEN/8, x18, x13, x24,FLREG) + +inst_3:// rs1==x1, rd==x29,fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x1; dest:x29; op1val:0xfd55; valaddr_reg:x6; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x24; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x29, x1, dyn, 0, 0, x6, 3*FLEN/8, x18, x13, x24,FLREG) + +inst_4:// rs1==x29, rd==x27,fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x29; dest:x27; op1val:0x7e01; valaddr_reg:x6; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x24; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x27, x29, dyn, 0, 0, x6, 4*FLEN/8, x18, x13, x24,FLREG) + +inst_5:// rs1==x22, rd==x9,fs1 == 1 and fe1 == 0x1f and fm1 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x22; dest:x9; op1val:0xfe01; valaddr_reg:x6; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x24; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x9, x22, dyn, 0, 0, x6, 5*FLEN/8, x18, x13, x24,FLREG) + +inst_6:// rs1==x25, rd==x19,fs1 == 0 and fe1 == 0x1f and fm1 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x25; dest:x19; op1val:0x7e55; valaddr_reg:x6; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x24; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x19, x25, dyn, 0, 0, x6, 6*FLEN/8, x18, x13, x24,FLREG) + +inst_7:// rs1==x14, rd==x26,fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x14; dest:x26; op1val:0xfe55; valaddr_reg:x6; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x24; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x26, x14, dyn, 0, 0, x6, 7*FLEN/8, x18, x13, x24,FLREG) + +inst_8:// rs1==x5, rd==x0, +/* opcode: fcvt.l.h ; op1:x5; dest:x0; op1val:0x0; valaddr_reg:x6; +val_offset:8*FLEN/8; rmval:rne; correctval:??; testreg:x24; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x0, x5, rne, 0, 0, x6, 8*FLEN/8, x18, x13, x24,FLREG) + +inst_9:// rs1==x20, rd==x1, +/* opcode: fcvt.l.h ; op1:x20; dest:x1; op1val:0x0; valaddr_reg:x6; +val_offset:9*FLEN/8; rmval:rne; correctval:??; testreg:x24; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x1, x20, rne, 0, 0, x6, 9*FLEN/8, x18, x13, x24,FLREG) + +inst_10:// rs1==x4, rd==x12, +/* opcode: fcvt.l.h ; op1:x4; dest:x12; op1val:0x0; valaddr_reg:x6; +val_offset:10*FLEN/8; rmval:rne; correctval:??; testreg:x24; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x12, x4, rne, 0, 0, x6, 10*FLEN/8, x18, x13, x24,FLREG) + +inst_11:// rs1==x16, rd==x7, +/* opcode: fcvt.l.h ; op1:x16; dest:x7; op1val:0x0; valaddr_reg:x6; +val_offset:11*FLEN/8; rmval:rne; correctval:??; testreg:x24; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x7, x16, rne, 0, 0, x6, 11*FLEN/8, x18, x13, x24,FLREG) + +inst_12:// rs1==x2, rd==x17, +/* opcode: fcvt.l.h ; op1:x2; dest:x17; op1val:0x0; valaddr_reg:x6; +val_offset:12*FLEN/8; rmval:rne; correctval:??; testreg:x24; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x17, x2, rne, 0, 0, x6, 12*FLEN/8, x18, x13, x24,FLREG) + +inst_13:// rs1==x27, rd==x28, +/* opcode: fcvt.l.h ; op1:x27; dest:x28; op1val:0x0; valaddr_reg:x6; +val_offset:13*FLEN/8; rmval:rne; correctval:??; testreg:x24; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x28, x27, rne, 0, 0, x6, 13*FLEN/8, x18, x13, x24,FLREG) + +inst_14:// rs1==x3, rd==x14, +/* opcode: fcvt.l.h ; op1:x3; dest:x14; op1val:0x0; valaddr_reg:x6; +val_offset:14*FLEN/8; rmval:rne; correctval:??; testreg:x24; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x14, x3, rne, 0, 0, x6, 14*FLEN/8, x18, x13, x24,FLREG) + +inst_15:// rs1==x9, rd==x25, +/* opcode: fcvt.l.h ; op1:x9; dest:x25; op1val:0x0; valaddr_reg:x6; +val_offset:15*FLEN/8; rmval:rne; correctval:??; testreg:x24; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x25, x9, rne, 0, 0, x6, 15*FLEN/8, x18, x13, x24,FLREG) + +inst_16:// rs1==x7, rd==x16, +/* opcode: fcvt.l.h ; op1:x7; dest:x16; op1val:0x0; valaddr_reg:x6; +val_offset:16*FLEN/8; rmval:rne; correctval:??; testreg:x24; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x16, x7, rne, 0, 0, x6, 16*FLEN/8, x18, x13, x24,FLREG) + +inst_17:// rs1==x21, rd==x2, +/* opcode: fcvt.l.h ; op1:x21; dest:x2; op1val:0x0; valaddr_reg:x6; +val_offset:17*FLEN/8; rmval:rne; correctval:??; testreg:x24; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x2, x21, rne, 0, 0, x6, 17*FLEN/8, x18, x13, x24,FLREG) + +inst_18:// rs1==x23, rd==x15, +/* opcode: fcvt.l.h ; op1:x23; dest:x15; op1val:0x0; valaddr_reg:x6; +val_offset:18*FLEN/8; rmval:rne; correctval:??; testreg:x24; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x15, x23, rne, 0, 0, x6, 18*FLEN/8, x18, x13, x24,FLREG) + +inst_19:// rs1==x11, rd==x8, +/* opcode: fcvt.l.h ; op1:x11; dest:x8; op1val:0x0; valaddr_reg:x6; +val_offset:19*FLEN/8; rmval:rne; correctval:??; testreg:x24; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x8, x11, rne, 0, 0, x6, 19*FLEN/8, x18, x13, x24,FLREG) +RVTEST_VALBASEUPD(x3,test_dataset_1) + +inst_20:// rs1==x18, rd==x6, +/* opcode: fcvt.l.h ; op1:x18; dest:x6; op1val:0x0; valaddr_reg:x3; +val_offset:0*FLEN/8; rmval:rne; correctval:??; testreg:x24; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x6, x18, rne, 0, 0, x3, 0*FLEN/8, x7, x13, x24,FLREG) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_21:// rs1==x6, rd==x5, +/* opcode: fcvt.l.h ; op1:x6; dest:x5; op1val:0x0; valaddr_reg:x3; +val_offset:1*FLEN/8; rmval:rne; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x5, x6, rne, 0, 0, x3, 1*FLEN/8, x7, x1, x2,FLREG) + +inst_22:// rs1==x19, rd==x11, +/* opcode: fcvt.l.h ; op1:x19; dest:x11; op1val:0x0; valaddr_reg:x3; +val_offset:2*FLEN/8; rmval:rne; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x11, x19, rne, 0, 0, x3, 2*FLEN/8, x7, x1, x2,FLREG) + +inst_23:// rs1==x8, rd==x23, +/* opcode: fcvt.l.h ; op1:x8; dest:x23; op1val:0x0; valaddr_reg:x3; +val_offset:3*FLEN/8; rmval:rne; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x23, x8, rne, 0, 0, x3, 3*FLEN/8, x7, x1, x2,FLREG) + +inst_24:// rs1==x30, rd==x20, +/* opcode: fcvt.l.h ; op1:x30; dest:x20; op1val:0x0; valaddr_reg:x3; +val_offset:4*FLEN/8; rmval:rne; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x20, x30, rne, 0, 0, x3, 4*FLEN/8, x7, x1, x2,FLREG) + +inst_25:// rs1==x31, rd==x30, +/* opcode: fcvt.l.h ; op1:x31; dest:x30; op1val:0x0; valaddr_reg:x3; +val_offset:5*FLEN/8; rmval:rne; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x30, x31, rne, 0, 0, x3, 5*FLEN/8, x7, x1, x2,FLREG) + +inst_26:// rs1==x13, rd==x4, +/* opcode: fcvt.l.h ; op1:x13; dest:x4; op1val:0x0; valaddr_reg:x3; +val_offset:6*FLEN/8; rmval:rne; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x4, x13, rne, 0, 0, x3, 6*FLEN/8, x7, x1, x2,FLREG) + +inst_27:// rs1==x26, rd==x31, +/* opcode: fcvt.l.h ; op1:x26; dest:x31; op1val:0x0; valaddr_reg:x3; +val_offset:7*FLEN/8; rmval:rne; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x26, rne, 0, 0, x3, 7*FLEN/8, x7, x1, x2,FLREG) + +inst_28:// rs1==x12, rd==x21, +/* opcode: fcvt.l.h ; op1:x12; dest:x21; op1val:0x0; valaddr_reg:x3; +val_offset:8*FLEN/8; rmval:rne; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x21, x12, rne, 0, 0, x3, 8*FLEN/8, x7, x1, x2,FLREG) + +inst_29:// rs1==x24, rd==x18, +/* opcode: fcvt.l.h ; op1:x24; dest:x18; op1val:0x0; valaddr_reg:x3; +val_offset:9*FLEN/8; rmval:rne; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x18, x24, rne, 0, 0, x3, 9*FLEN/8, x7, x1, x2,FLREG) + +inst_30:// rs1==x17, rd==x13, +/* opcode: fcvt.l.h ; op1:x17; dest:x13; op1val:0x0; valaddr_reg:x3; +val_offset:10*FLEN/8; rmval:rne; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x13, x17, rne, 0, 0, x3, 10*FLEN/8, x7, x1, x2,FLREG) + +inst_31:// rs1==x15, rd==x24, +/* opcode: fcvt.l.h ; op1:x15; dest:x24; op1val:0x0; valaddr_reg:x3; +val_offset:11*FLEN/8; rmval:rne; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x24, x15, rne, 0, 0, x3, 11*FLEN/8, x7, x1, x2,FLREG) + +inst_32:// fs1 == 1 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xfc01; valaddr_reg:x3; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x3, 12*FLEN/8, x7, x1, x2,FLREG) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(31745,32,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32085,32,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32257,32,FLEN) +NAN_BOXED(65025,16,FLEN) +NAN_BOXED(32341,32,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +test_dataset_1: +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(64513,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x13_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x13_1: + .fill 42*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_0: + .fill 24*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/Zhinx/src/fcvt.l.h_b28-01.S b/riscv-test-suite/rv64i_m/Zhinx/src/fcvt.l.h_b28-01.S new file mode 100644 index 000000000..5a59a5ba5 --- /dev/null +++ b/riscv-test-suite/rv64i_m/Zhinx/src/fcvt.l.h_b28-01.S @@ -0,0 +1,337 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 04:45:28 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64Zhinx/rv64h_fcvt.l.h.cgf \ + \ +// -- xlen 64 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.l.h instruction of the RISC-V RV64_Zfinx_Zhinx extension for the fcvt.l.h_b28 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fcvt.l.h_b28) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x2,test_dataset_0) +RVTEST_SIGBASE(x18,signature_x18_1) + +inst_0:// rs1 == rd, rs1==x24, rd==x24,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x24; dest:x24; op1val:0x0; valaddr_reg:x2; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x20; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x24, x24, dyn, 0, 0, x2, 0*FLEN/8, x13, x18, x20,FLREG) + +inst_1:// rs1 != rd, rs1==x29, rd==x8,fs1 == 0 and fe1 == 0x0e and fm1 == 0x092 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x29; dest:x8; op1val:0x3892; valaddr_reg:x2; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x20; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x8, x29, dyn, 0, 0, x2, 1*FLEN/8, x13, x18, x20,FLREG) + +inst_2:// rs1==x31, rd==x5,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x31; dest:x5; op1val:0x3c00; valaddr_reg:x2; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x20; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x5, x31, dyn, 0, 0, x2, 2*FLEN/8, x13, x18, x20,FLREG) + +inst_3:// rs1==x10, rd==x0,fs1 == 0 and fe1 == 0x0f and fm1 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x10; dest:x0; op1val:0x3d00; valaddr_reg:x2; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x20; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x0, x10, dyn, 0, 0, x2, 3*FLEN/8, x13, x18, x20,FLREG) + +inst_4:// rs1==x8, rd==x25,fs1 == 0 and fe1 == 0x0f and fm1 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x8; dest:x25; op1val:0x3e00; valaddr_reg:x2; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x20; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x25, x8, dyn, 0, 0, x2, 4*FLEN/8, x13, x18, x20,FLREG) + +inst_5:// rs1==x23, rd==x6,fs1 == 0 and fe1 == 0x0f and fm1 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x23; dest:x6; op1val:0x3f00; valaddr_reg:x2; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x20; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x6, x23, dyn, 0, 0, x2, 5*FLEN/8, x13, x18, x20,FLREG) + +inst_6:// rs1==x15, rd==x22,fs1 == 0 and fe1 == 0x10 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x15; dest:x22; op1val:0x4000; valaddr_reg:x2; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x20; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x22, x15, dyn, 0, 0, x2, 6*FLEN/8, x13, x18, x20,FLREG) + +inst_7:// rs1==x16, rd==x11,fs1 == 0 and fe1 == 0x10 and fm1 == 0x080 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x16; dest:x11; op1val:0x4080; valaddr_reg:x2; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x20; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x11, x16, dyn, 0, 0, x2, 7*FLEN/8, x13, x18, x20,FLREG) + +inst_8:// rs1==x19, rd==x14,fs1 == 0 and fe1 == 0x10 and fm1 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x19; dest:x14; op1val:0x4100; valaddr_reg:x2; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x20; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x14, x19, dyn, 0, 0, x2, 8*FLEN/8, x13, x18, x20,FLREG) + +inst_9:// rs1==x3, rd==x1,fs1 == 0 and fe1 == 0x10 and fm1 == 0x180 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x3; dest:x1; op1val:0x4180; valaddr_reg:x2; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x20; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x1, x3, dyn, 0, 0, x2, 9*FLEN/8, x13, x18, x20,FLREG) + +inst_10:// rs1==x27, rd==x4,fs1 == 0 and fe1 == 0x1c and fm1 == 0x2dc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x27; dest:x4; op1val:0x72dc; valaddr_reg:x2; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x20; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x4, x27, dyn, 0, 0, x2, 10*FLEN/8, x13, x18, x20,FLREG) + +inst_11:// rs1==x9, rd==x12,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x9; dest:x12; op1val:0x77ff; valaddr_reg:x2; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x20; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x12, x9, dyn, 0, 0, x2, 11*FLEN/8, x13, x18, x20,FLREG) + +inst_12:// rs1==x17, rd==x7,fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x17; dest:x7; op1val:0x7c00; valaddr_reg:x2; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x20; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x7, x17, dyn, 0, 0, x2, 12*FLEN/8, x13, x18, x20,FLREG) + +inst_13:// rs1==x12, rd==x3,fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x12; dest:x3; op1val:0x7c01; valaddr_reg:x2; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x20; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x3, x12, dyn, 0, 0, x2, 13*FLEN/8, x13, x18, x20,FLREG) + +inst_14:// rs1==x25, rd==x26,fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x25; dest:x26; op1val:0x7e01; valaddr_reg:x2; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x20; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x26, x25, dyn, 0, 0, x2, 14*FLEN/8, x13, x18, x20,FLREG) +RVTEST_VALBASEUPD(x8,test_dataset_1) + +inst_15:// rs1==x11, rd==x2,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x11; dest:x2; op1val:0x8000; valaddr_reg:x8; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x20; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x2, x11, dyn, 0, 0, x8, 0*FLEN/8, x12, x18, x20,FLREG) + +inst_16:// rs1==x26, rd==x17,fs1 == 1 and fe1 == 0x0d and fm1 == 0x2c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x26; dest:x17; op1val:0xb6c0; valaddr_reg:x8; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x20; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x17, x26, dyn, 0, 0, x8, 1*FLEN/8, x12, x18, x20,FLREG) + +inst_17:// rs1==x2, rd==x29,fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x2; dest:x29; op1val:0xbc00; valaddr_reg:x8; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x20; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x29, x2, dyn, 0, 0, x8, 2*FLEN/8, x12, x18, x20,FLREG) + +inst_18:// rs1==x4, rd==x27,fs1 == 1 and fe1 == 0x10 and fm1 == 0x180 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x4; dest:x27; op1val:0xc180; valaddr_reg:x8; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x20; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x27, x4, dyn, 0, 0, x8, 3*FLEN/8, x12, x18, x20,FLREG) + +inst_19:// rs1==x13, rd==x30,fs1 == 1 and fe1 == 0x10 and fm1 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x13; dest:x30; op1val:0xc100; valaddr_reg:x8; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x20; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x30, x13, dyn, 0, 0, x8, 4*FLEN/8, x12, x18, x20,FLREG) +RVTEST_SIGBASE(x2,signature_x2_0) + +inst_20:// rs1==x0, rd==x15,fs1 == 1 and fe1 == 0x10 and fm1 == 0x080 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x0; dest:x15; op1val:0x0; valaddr_reg:x8; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x15, x0, dyn, 0, 0, x8, 5*FLEN/8, x12, x2, x3,FLREG) + +inst_21:// rs1==x1, rd==x10,fs1 == 1 and fe1 == 0x10 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x1; dest:x10; op1val:0xc000; valaddr_reg:x8; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x10, x1, dyn, 0, 0, x8, 6*FLEN/8, x12, x2, x3,FLREG) + +inst_22:// rs1==x22, rd==x21,fs1 == 1 and fe1 == 0x0f and fm1 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x22; dest:x21; op1val:0xbf00; valaddr_reg:x8; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x21, x22, dyn, 0, 0, x8, 7*FLEN/8, x12, x2, x3,FLREG) + +inst_23:// rs1==x28, rd==x19,fs1 == 1 and fe1 == 0x0f and fm1 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x28; dest:x19; op1val:0xbe00; valaddr_reg:x8; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x19, x28, dyn, 0, 0, x8, 8*FLEN/8, x12, x2, x3,FLREG) + +inst_24:// rs1==x18, rd==x28,fs1 == 1 and fe1 == 0x0f and fm1 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x18; dest:x28; op1val:0xbd00; valaddr_reg:x8; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x28, x18, dyn, 0, 0, x8, 9*FLEN/8, x12, x2, x3,FLREG) + +inst_25:// rs1==x20, rd==x13,fs1 == 1 and fe1 == 0x1d and fm1 == 0x259 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x20; dest:x13; op1val:0xf659; valaddr_reg:x8; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x13, x20, dyn, 0, 0, x8, 10*FLEN/8, x12, x2, x3,FLREG) + +inst_26:// rs1==x21, rd==x16,fs1 == 1 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x21; dest:x16; op1val:0xf800; valaddr_reg:x8; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x16, x21, dyn, 0, 0, x8, 11*FLEN/8, x12, x2, x3,FLREG) + +inst_27:// rs1==x7, rd==x31,fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x7; dest:x31; op1val:0xfc00; valaddr_reg:x8; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x7, dyn, 0, 0, x8, 12*FLEN/8, x12, x2, x3,FLREG) + +inst_28:// rs1==x5, rd==x23, +/* opcode: fcvt.l.h ; op1:x5; dest:x23; op1val:0x0; valaddr_reg:x8; +val_offset:13*FLEN/8; rmval:rne; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x23, x5, rne, 0, 0, x8, 13*FLEN/8, x12, x2, x3,FLREG) + +inst_29:// rs1==x30, rd==x9, +/* opcode: fcvt.l.h ; op1:x30; dest:x9; op1val:0x0; valaddr_reg:x8; +val_offset:14*FLEN/8; rmval:rne; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x9, x30, rne, 0, 0, x8, 14*FLEN/8, x12, x2, x3,FLREG) + +inst_30:// rs1==x6, rd==x20, +/* opcode: fcvt.l.h ; op1:x6; dest:x20; op1val:0x0; valaddr_reg:x8; +val_offset:15*FLEN/8; rmval:rne; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x20, x6, rne, 0, 0, x8, 15*FLEN/8, x12, x2, x3,FLREG) +RVTEST_VALBASEUPD(x1,test_dataset_2) + +inst_31:// rs1==x14, rd==x18, +/* opcode: fcvt.l.h ; op1:x14; dest:x18; op1val:0x0; valaddr_reg:x1; +val_offset:0*FLEN/8; rmval:rne; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x18, x14, rne, 0, 0, x1, 0*FLEN/8, x4, x2, x3,FLREG) + +inst_32:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x3d00; valaddr_reg:x1; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x1, 1*FLEN/8, x4, x2, x3,FLREG) + +inst_33:// fs1 == 1 and fe1 == 0x10 and fm1 == 0x080 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xc080; valaddr_reg:x1; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x1, 2*FLEN/8, x4, x2, x3,FLREG) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(14482,32,FLEN) +NAN_BOXED(15360,32,FLEN) +NAN_BOXED(15616,32,FLEN) +NAN_BOXED(15872,32,FLEN) +NAN_BOXED(16128,32,FLEN) +NAN_BOXED(16384,32,FLEN) +NAN_BOXED(16512,32,FLEN) +NAN_BOXED(16640,32,FLEN) +NAN_BOXED(16768,32,FLEN) +NAN_BOXED(29404,32,FLEN) +NAN_BOXED(30719,32,FLEN) +NAN_BOXED(31744,32,FLEN) +NAN_BOXED(31745,32,FLEN) +NAN_BOXED(32257,32,FLEN) +test_dataset_1: +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(46784,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(49536,16,FLEN) +NAN_BOXED(49408,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(49152,16,FLEN) +NAN_BOXED(48896,16,FLEN) +NAN_BOXED(48640,16,FLEN) +NAN_BOXED(48384,16,FLEN) +NAN_BOXED(63065,16,FLEN) +NAN_BOXED(63488,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +test_dataset_2: +NAN_BOXED(0,16,FLEN) +NAN_BOXED(15616,16,FLEN) +NAN_BOXED(49280,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x18_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x18_1: + .fill 40*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_0: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/Zhinx/src/fcvt.l.h_b29-01.S b/riscv-test-suite/rv64i_m/Zhinx/src/fcvt.l.h_b29-01.S new file mode 100644 index 000000000..0d592249f --- /dev/null +++ b/riscv-test-suite/rv64i_m/Zhinx/src/fcvt.l.h_b29-01.S @@ -0,0 +1,671 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 04:45:28 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64Zhinx/rv64h_fcvt.l.h.cgf \ + \ +// -- xlen 64 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.l.h instruction of the RISC-V RV64_Zfinx_Zhinx extension for the fcvt.l.h_b29 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fcvt.l.h_b29) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x5,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0:// rs1 == rd, rs1==x22, rd==x22,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x22; dest:x22; op1val:0x3248; valaddr_reg:x5; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x22, x22, dyn, 0, 0, x5, 0*FLEN/8, x7, x1, x4,FLREG) + +inst_1:// rs1 != rd, rs1==x2, rd==x15,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x2; dest:x15; op1val:0x3248; valaddr_reg:x5; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.l.h, x15, x2, dyn, 32, 0, x5, 1*FLEN/8, x7, x1, x4,FLREG) + +inst_2:// rs1==x9, rd==x25,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x9; dest:x25; op1val:0x3248; valaddr_reg:x5; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.l.h, x25, x9, dyn, 64, 0, x5, 2*FLEN/8, x7, x1, x4,FLREG) + +inst_3:// rs1==x11, rd==x10,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x11; dest:x10; op1val:0x3248; valaddr_reg:x5; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.l.h, x10, x11, dyn, 96, 0, x5, 3*FLEN/8, x7, x1, x4,FLREG) + +inst_4:// rs1==x28, rd==x3,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x28; dest:x3; op1val:0x3248; valaddr_reg:x5; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.l.h, x3, x28, dyn, 128, 0, x5, 4*FLEN/8, x7, x1, x4,FLREG) + +inst_5:// rs1==x3, rd==x30,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x3; dest:x30; op1val:0x3249; valaddr_reg:x5; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x30, x3, dyn, 0, 0, x5, 5*FLEN/8, x7, x1, x4,FLREG) + +inst_6:// rs1==x14, rd==x19,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x14; dest:x19; op1val:0x3249; valaddr_reg:x5; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.l.h, x19, x14, dyn, 32, 0, x5, 6*FLEN/8, x7, x1, x4,FLREG) + +inst_7:// rs1==x13, rd==x8,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x13; dest:x8; op1val:0x3249; valaddr_reg:x5; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.l.h, x8, x13, dyn, 64, 0, x5, 7*FLEN/8, x7, x1, x4,FLREG) + +inst_8:// rs1==x0, rd==x20,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x0; dest:x20; op1val:0x0; valaddr_reg:x5; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.l.h, x20, x0, dyn, 96, 0, x5, 8*FLEN/8, x7, x1, x4,FLREG) + +inst_9:// rs1==x24, rd==x9,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x24; dest:x9; op1val:0x3249; valaddr_reg:x5; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.l.h, x9, x24, dyn, 128, 0, x5, 9*FLEN/8, x7, x1, x4,FLREG) + +inst_10:// rs1==x19, rd==x14,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x19; dest:x14; op1val:0x324a; valaddr_reg:x5; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x14, x19, dyn, 0, 0, x5, 10*FLEN/8, x7, x1, x4,FLREG) + +inst_11:// rs1==x6, rd==x12,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x6; dest:x12; op1val:0x324a; valaddr_reg:x5; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.l.h, x12, x6, dyn, 32, 0, x5, 11*FLEN/8, x7, x1, x4,FLREG) + +inst_12:// rs1==x25, rd==x29,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x25; dest:x29; op1val:0x324a; valaddr_reg:x5; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.l.h, x29, x25, dyn, 64, 0, x5, 12*FLEN/8, x7, x1, x4,FLREG) + +inst_13:// rs1==x30, rd==x26,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x26; op1val:0x324a; valaddr_reg:x5; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.l.h, x26, x30, dyn, 96, 0, x5, 13*FLEN/8, x7, x1, x4,FLREG) + +inst_14:// rs1==x21, rd==x27,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x21; dest:x27; op1val:0x324a; valaddr_reg:x5; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.l.h, x27, x21, dyn, 128, 0, x5, 14*FLEN/8, x7, x1, x4,FLREG) + +inst_15:// rs1==x31, rd==x28,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x31; dest:x28; op1val:0x324b; valaddr_reg:x5; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x28, x31, dyn, 0, 0, x5, 15*FLEN/8, x7, x1, x4,FLREG) + +inst_16:// rs1==x8, rd==x31,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x8; dest:x31; op1val:0x324b; valaddr_reg:x5; +val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.l.h, x31, x8, dyn, 32, 0, x5, 16*FLEN/8, x7, x1, x4,FLREG) + +inst_17:// rs1==x12, rd==x11,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x12; dest:x11; op1val:0x324b; valaddr_reg:x5; +val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.l.h, x11, x12, dyn, 64, 0, x5, 17*FLEN/8, x7, x1, x4,FLREG) + +inst_18:// rs1==x27, rd==x6,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x27; dest:x6; op1val:0x324b; valaddr_reg:x5; +val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.l.h, x6, x27, dyn, 96, 0, x5, 18*FLEN/8, x7, x1, x4,FLREG) + +inst_19:// rs1==x20, rd==x23,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x20; dest:x23; op1val:0x324b; valaddr_reg:x5; +val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.l.h, x23, x20, dyn, 128, 0, x5, 19*FLEN/8, x7, x1, x4,FLREG) +RVTEST_VALBASEUPD(x6,test_dataset_1) + +inst_20:// rs1==x29, rd==x2,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x29; dest:x2; op1val:0x324c; valaddr_reg:x6; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x2, x29, dyn, 0, 0, x6, 0*FLEN/8, x8, x1, x4,FLREG) + +inst_21:// rs1==x26, rd==x13,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x26; dest:x13; op1val:0x324c; valaddr_reg:x6; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.l.h, x13, x26, dyn, 32, 0, x6, 1*FLEN/8, x8, x1, x4,FLREG) + +inst_22:// rs1==x16, rd==x5,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x16; dest:x5; op1val:0x324c; valaddr_reg:x6; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.l.h, x5, x16, dyn, 64, 0, x6, 2*FLEN/8, x8, x1, x4,FLREG) + +inst_23:// rs1==x5, rd==x4,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x5; dest:x4; op1val:0x324c; valaddr_reg:x6; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.l.h, x4, x5, dyn, 96, 0, x6, 3*FLEN/8, x8, x1, x3,FLREG) +RVTEST_SIGBASE(x2,signature_x2_0) + +inst_24:// rs1==x4, rd==x1,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x4; dest:x1; op1val:0x324c; valaddr_reg:x6; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.l.h, x1, x4, dyn, 128, 0, x6, 4*FLEN/8, x8, x2, x3,FLREG) + +inst_25:// rs1==x1, rd==x7,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x1; dest:x7; op1val:0x324d; valaddr_reg:x6; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x7, x1, dyn, 0, 0, x6, 5*FLEN/8, x8, x2, x3,FLREG) + +inst_26:// rs1==x18, rd==x24,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x18; dest:x24; op1val:0x324d; valaddr_reg:x6; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.l.h, x24, x18, dyn, 32, 0, x6, 6*FLEN/8, x8, x2, x3,FLREG) + +inst_27:// rs1==x10, rd==x17,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x10; dest:x17; op1val:0x324d; valaddr_reg:x6; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.l.h, x17, x10, dyn, 64, 0, x6, 7*FLEN/8, x8, x2, x3,FLREG) + +inst_28:// rs1==x17, rd==x0,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x17; dest:x0; op1val:0x324d; valaddr_reg:x6; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.l.h, x0, x17, dyn, 96, 0, x6, 8*FLEN/8, x8, x2, x3,FLREG) + +inst_29:// rs1==x7, rd==x21,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x7; dest:x21; op1val:0x324d; valaddr_reg:x6; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.l.h, x21, x7, dyn, 128, 0, x6, 9*FLEN/8, x8, x2, x3,FLREG) + +inst_30:// rs1==x15, rd==x18,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x15; dest:x18; op1val:0x324e; valaddr_reg:x6; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x18, x15, dyn, 0, 0, x6, 10*FLEN/8, x8, x2, x3,FLREG) + +inst_31:// rs1==x23, rd==x16,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x23; dest:x16; op1val:0x324e; valaddr_reg:x6; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.l.h, x16, x23, dyn, 32, 0, x6, 11*FLEN/8, x8, x2, x3,FLREG) + +inst_32:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x324e; valaddr_reg:x6; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 64, 0, x6, 12*FLEN/8, x8, x2, x3,FLREG) + +inst_33:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x324e; valaddr_reg:x6; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 96, 0, x6, 13*FLEN/8, x8, x2, x3,FLREG) + +inst_34:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x324e; valaddr_reg:x6; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 128, 0, x6, 14*FLEN/8, x8, x2, x3,FLREG) + +inst_35:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x324f; valaddr_reg:x6; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x6, 15*FLEN/8, x8, x2, x3,FLREG) + +inst_36:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x324f; valaddr_reg:x6; +val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 32, 0, x6, 16*FLEN/8, x8, x2, x3,FLREG) + +inst_37:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x324f; valaddr_reg:x6; +val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 64, 0, x6, 17*FLEN/8, x8, x2, x3,FLREG) + +inst_38:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x324f; valaddr_reg:x6; +val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 96, 0, x6, 18*FLEN/8, x8, x2, x3,FLREG) + +inst_39:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x324f; valaddr_reg:x6; +val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 128, 0, x6, 19*FLEN/8, x8, x2, x3,FLREG) + +inst_40:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xb248; valaddr_reg:x6; +val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x6, 20*FLEN/8, x8, x2, x3,FLREG) + +inst_41:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xb248; valaddr_reg:x6; +val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 32, 0, x6, 21*FLEN/8, x8, x2, x3,FLREG) + +inst_42:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xb248; valaddr_reg:x6; +val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 64, 0, x6, 22*FLEN/8, x8, x2, x3,FLREG) + +inst_43:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xb248; valaddr_reg:x6; +val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 96, 0, x6, 23*FLEN/8, x8, x2, x3,FLREG) + +inst_44:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xb248; valaddr_reg:x6; +val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 128, 0, x6, 24*FLEN/8, x8, x2, x3,FLREG) + +inst_45:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xb249; valaddr_reg:x6; +val_offset:25*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x6, 25*FLEN/8, x8, x2, x3,FLREG) + +inst_46:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xb249; valaddr_reg:x6; +val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 32, 0, x6, 26*FLEN/8, x8, x2, x3,FLREG) + +inst_47:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xb249; valaddr_reg:x6; +val_offset:27*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 64, 0, x6, 27*FLEN/8, x8, x2, x3,FLREG) + +inst_48:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xb249; valaddr_reg:x6; +val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 96, 0, x6, 28*FLEN/8, x8, x2, x3,FLREG) + +inst_49:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xb249; valaddr_reg:x6; +val_offset:29*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 128, 0, x6, 29*FLEN/8, x8, x2, x3,FLREG) + +inst_50:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xb24a; valaddr_reg:x6; +val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x6, 30*FLEN/8, x8, x2, x3,FLREG) + +inst_51:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xb24a; valaddr_reg:x6; +val_offset:31*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 32, 0, x6, 31*FLEN/8, x8, x2, x3,FLREG) + +inst_52:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xb24a; valaddr_reg:x6; +val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 64, 0, x6, 32*FLEN/8, x8, x2, x3,FLREG) + +inst_53:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xb24a; valaddr_reg:x6; +val_offset:33*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 96, 0, x6, 33*FLEN/8, x8, x2, x3,FLREG) + +inst_54:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xb24a; valaddr_reg:x6; +val_offset:34*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 128, 0, x6, 34*FLEN/8, x8, x2, x3,FLREG) + +inst_55:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xb24b; valaddr_reg:x6; +val_offset:35*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x6, 35*FLEN/8, x8, x2, x3,FLREG) + +inst_56:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xb24b; valaddr_reg:x6; +val_offset:36*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 32, 0, x6, 36*FLEN/8, x8, x2, x3,FLREG) + +inst_57:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xb24b; valaddr_reg:x6; +val_offset:37*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 64, 0, x6, 37*FLEN/8, x8, x2, x3,FLREG) + +inst_58:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xb24b; valaddr_reg:x6; +val_offset:38*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 96, 0, x6, 38*FLEN/8, x8, x2, x3,FLREG) + +inst_59:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xb24b; valaddr_reg:x6; +val_offset:39*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 128, 0, x6, 39*FLEN/8, x8, x2, x3,FLREG) + +inst_60:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xb24c; valaddr_reg:x6; +val_offset:40*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x6, 40*FLEN/8, x8, x2, x3,FLREG) + +inst_61:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xb24c; valaddr_reg:x6; +val_offset:41*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 32, 0, x6, 41*FLEN/8, x8, x2, x3,FLREG) + +inst_62:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xb24c; valaddr_reg:x6; +val_offset:42*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 64, 0, x6, 42*FLEN/8, x8, x2, x3,FLREG) + +inst_63:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xb24c; valaddr_reg:x6; +val_offset:43*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 96, 0, x6, 43*FLEN/8, x8, x2, x3,FLREG) + +inst_64:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xb24c; valaddr_reg:x6; +val_offset:44*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 128, 0, x6, 44*FLEN/8, x8, x2, x3,FLREG) + +inst_65:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xb24d; valaddr_reg:x6; +val_offset:45*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x6, 45*FLEN/8, x8, x2, x3,FLREG) + +inst_66:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xb24d; valaddr_reg:x6; +val_offset:46*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 32, 0, x6, 46*FLEN/8, x8, x2, x3,FLREG) + +inst_67:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xb24d; valaddr_reg:x6; +val_offset:47*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 64, 0, x6, 47*FLEN/8, x8, x2, x3,FLREG) + +inst_68:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xb24d; valaddr_reg:x6; +val_offset:48*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 96, 0, x6, 48*FLEN/8, x8, x2, x3,FLREG) + +inst_69:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xb24d; valaddr_reg:x6; +val_offset:49*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 128, 0, x6, 49*FLEN/8, x8, x2, x3,FLREG) + +inst_70:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xb24e; valaddr_reg:x6; +val_offset:50*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x6, 50*FLEN/8, x8, x2, x3,FLREG) + +inst_71:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xb24e; valaddr_reg:x6; +val_offset:51*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 32, 0, x6, 51*FLEN/8, x8, x2, x3,FLREG) + +inst_72:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xb24e; valaddr_reg:x6; +val_offset:52*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 64, 0, x6, 52*FLEN/8, x8, x2, x3,FLREG) + +inst_73:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xb24e; valaddr_reg:x6; +val_offset:53*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 96, 0, x6, 53*FLEN/8, x8, x2, x3,FLREG) + +inst_74:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xb24e; valaddr_reg:x6; +val_offset:54*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 128, 0, x6, 54*FLEN/8, x8, x2, x3,FLREG) + +inst_75:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xb24f; valaddr_reg:x6; +val_offset:55*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 0, 0, x6, 55*FLEN/8, x8, x2, x3,FLREG) + +inst_76:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xb24f; valaddr_reg:x6; +val_offset:56*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 32, 0, x6, 56*FLEN/8, x8, x2, x3,FLREG) + +inst_77:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xb24f; valaddr_reg:x6; +val_offset:57*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 64, 0, x6, 57*FLEN/8, x8, x2, x3,FLREG) + +inst_78:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xb24f; valaddr_reg:x6; +val_offset:58*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 96, 0, x6, 58*FLEN/8, x8, x2, x3,FLREG) + +inst_79:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0xb24f; valaddr_reg:x6; +val_offset:59*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 128, 0, x6, 59*FLEN/8, x8, x2, x3,FLREG) + +inst_80:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x3249; valaddr_reg:x6; +val_offset:60*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 96, 0, x6, 60*FLEN/8, x8, x2, x3,FLREG) + +inst_81:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.l.h ; op1:x30; dest:x31; op1val:0x324d; valaddr_reg:x6; +val_offset:61*FLEN/8; rmval:dyn; correctval:??; testreg:x3; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.l.h, x31, x30, dyn, 96, 0, x6, 61*FLEN/8, x8, x2, x3,FLREG) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(12872,32,FLEN) +NAN_BOXED(12872,32,FLEN) +NAN_BOXED(12872,32,FLEN) +NAN_BOXED(12872,32,FLEN) +NAN_BOXED(12872,32,FLEN) +NAN_BOXED(12873,32,FLEN) +NAN_BOXED(12873,32,FLEN) +NAN_BOXED(12873,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(12873,32,FLEN) +NAN_BOXED(12874,32,FLEN) +NAN_BOXED(12874,32,FLEN) +NAN_BOXED(12874,32,FLEN) +NAN_BOXED(12874,32,FLEN) +NAN_BOXED(12874,32,FLEN) +NAN_BOXED(12875,32,FLEN) +NAN_BOXED(12875,32,FLEN) +NAN_BOXED(12875,32,FLEN) +NAN_BOXED(12875,32,FLEN) +NAN_BOXED(12875,32,FLEN) +test_dataset_1: +NAN_BOXED(12876,16,FLEN) +NAN_BOXED(12876,16,FLEN) +NAN_BOXED(12876,16,FLEN) +NAN_BOXED(12876,16,FLEN) +NAN_BOXED(12876,16,FLEN) +NAN_BOXED(12877,16,FLEN) +NAN_BOXED(12877,16,FLEN) +NAN_BOXED(12877,16,FLEN) +NAN_BOXED(12877,16,FLEN) +NAN_BOXED(12877,16,FLEN) +NAN_BOXED(12878,16,FLEN) +NAN_BOXED(12878,16,FLEN) +NAN_BOXED(12878,16,FLEN) +NAN_BOXED(12878,16,FLEN) +NAN_BOXED(12878,16,FLEN) +NAN_BOXED(12879,16,FLEN) +NAN_BOXED(12879,16,FLEN) +NAN_BOXED(12879,16,FLEN) +NAN_BOXED(12879,16,FLEN) +NAN_BOXED(12879,16,FLEN) +NAN_BOXED(45640,16,FLEN) +NAN_BOXED(45640,16,FLEN) +NAN_BOXED(45640,16,FLEN) +NAN_BOXED(45640,16,FLEN) +NAN_BOXED(45640,16,FLEN) +NAN_BOXED(45641,16,FLEN) +NAN_BOXED(45641,16,FLEN) +NAN_BOXED(45641,16,FLEN) +NAN_BOXED(45641,16,FLEN) +NAN_BOXED(45641,16,FLEN) +NAN_BOXED(45642,16,FLEN) +NAN_BOXED(45642,16,FLEN) +NAN_BOXED(45642,16,FLEN) +NAN_BOXED(45642,16,FLEN) +NAN_BOXED(45642,16,FLEN) +NAN_BOXED(45643,16,FLEN) +NAN_BOXED(45643,16,FLEN) +NAN_BOXED(45643,16,FLEN) +NAN_BOXED(45643,16,FLEN) +NAN_BOXED(45643,16,FLEN) +NAN_BOXED(45644,16,FLEN) +NAN_BOXED(45644,16,FLEN) +NAN_BOXED(45644,16,FLEN) +NAN_BOXED(45644,16,FLEN) +NAN_BOXED(45644,16,FLEN) +NAN_BOXED(45645,16,FLEN) +NAN_BOXED(45645,16,FLEN) +NAN_BOXED(45645,16,FLEN) +NAN_BOXED(45645,16,FLEN) +NAN_BOXED(45645,16,FLEN) +NAN_BOXED(45646,16,FLEN) +NAN_BOXED(45646,16,FLEN) +NAN_BOXED(45646,16,FLEN) +NAN_BOXED(45646,16,FLEN) +NAN_BOXED(45646,16,FLEN) +NAN_BOXED(45647,16,FLEN) +NAN_BOXED(45647,16,FLEN) +NAN_BOXED(45647,16,FLEN) +NAN_BOXED(45647,16,FLEN) +NAN_BOXED(45647,16,FLEN) +NAN_BOXED(12873,16,FLEN) +NAN_BOXED(12877,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 48*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_0: + .fill 116*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/Zhinx/src/fcvt.lu.h_b1-01.S b/riscv-test-suite/rv64i_m/Zhinx/src/fcvt.lu.h_b1-01.S new file mode 100644 index 000000000..1b111fe0c --- /dev/null +++ b/riscv-test-suite/rv64i_m/Zhinx/src/fcvt.lu.h_b1-01.S @@ -0,0 +1,328 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 04:44:02 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64Zhinx/rv64h_fcvt.lu.h.cgf \ + \ +// -- xlen 64 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.lu.h instruction of the RISC-V RV64_Zfinx_Zhinx extension for the fcvt.lu.h_b1 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fcvt.lu.h_b1) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x15,test_dataset_0) +RVTEST_SIGBASE(x8,signature_x8_1) + +inst_0:// rs1==x4, rd==x31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x4; dest:x31; op1val:0x0; valaddr_reg:x15; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x18; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x4, dyn, 0, 0, x15, 0*FLEN/8, x23, x8, x18,FLREG) + +inst_1:// rs1==x1, rd==x9,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x1; dest:x9; op1val:0x8000; valaddr_reg:x15; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x18; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x9, x1, dyn, 0, 0, x15, 1*FLEN/8, x23, x8, x18,FLREG) + +inst_2:// rs1==x11, rd==x3,fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x11; dest:x3; op1val:0x1; valaddr_reg:x15; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x18; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x3, x11, dyn, 0, 0, x15, 2*FLEN/8, x23, x8, x18,FLREG) + +inst_3:// rs1==x12, rd==x20,fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x12; dest:x20; op1val:0x8001; valaddr_reg:x15; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x18; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x20, x12, dyn, 0, 0, x15, 3*FLEN/8, x23, x8, x18,FLREG) + +inst_4:// rs1==x30, rd==x11,fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x11; op1val:0x2; valaddr_reg:x15; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x18; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x11, x30, dyn, 0, 0, x15, 4*FLEN/8, x23, x8, x18,FLREG) + +inst_5:// rs1==x5, rd==x10,fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x5; dest:x10; op1val:0x83fe; valaddr_reg:x15; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x18; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x10, x5, dyn, 0, 0, x15, 5*FLEN/8, x23, x8, x18,FLREG) + +inst_6:// rs1==x22, rd==x25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x22; dest:x25; op1val:0x3ff; valaddr_reg:x15; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x18; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x25, x22, dyn, 0, 0, x15, 6*FLEN/8, x23, x8, x18,FLREG) + +inst_7:// rs1==x25, rd==x29,fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x25; dest:x29; op1val:0x83ff; valaddr_reg:x15; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x18; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x29, x25, dyn, 0, 0, x15, 7*FLEN/8, x23, x8, x18,FLREG) + +inst_8:// rs1==x19, rd==x21,fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x19; dest:x21; op1val:0x400; valaddr_reg:x15; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x18; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x21, x19, dyn, 0, 0, x15, 8*FLEN/8, x23, x8, x18,FLREG) + +inst_9:// rs1==x31, rd==x28,fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x31; dest:x28; op1val:0x8400; valaddr_reg:x15; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x18; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x28, x31, dyn, 0, 0, x15, 9*FLEN/8, x23, x8, x18,FLREG) + +inst_10:// rs1==x13, rd==x14,fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x13; dest:x14; op1val:0x401; valaddr_reg:x15; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x18; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x14, x13, dyn, 0, 0, x15, 10*FLEN/8, x23, x8, x18,FLREG) + +inst_11:// rs1==x9, rd==x16,fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x9; dest:x16; op1val:0x8455; valaddr_reg:x15; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x18; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x16, x9, dyn, 0, 0, x15, 11*FLEN/8, x23, x8, x18,FLREG) + +inst_12:// rs1==x26, rd==x30,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x26; dest:x30; op1val:0x7bff; valaddr_reg:x15; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x18; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x30, x26, dyn, 0, 0, x15, 12*FLEN/8, x23, x8, x18,FLREG) + +inst_13:// rs1==x21, rd==x13,fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x21; dest:x13; op1val:0xfbff; valaddr_reg:x15; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x18; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x13, x21, dyn, 0, 0, x15, 13*FLEN/8, x23, x8, x18,FLREG) + +inst_14:// rs1==x28, rd==x0,fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x28; dest:x0; op1val:0x7c00; valaddr_reg:x15; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x18; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x0, x28, dyn, 0, 0, x15, 14*FLEN/8, x23, x8, x18,FLREG) + +inst_15:// rs1==x17, rd==x19,fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x17; dest:x19; op1val:0xfc00; valaddr_reg:x15; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x18; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x19, x17, dyn, 0, 0, x15, 15*FLEN/8, x23, x8, x18,FLREG) + +inst_16:// rs1==x20, rd==x4,fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x20; dest:x4; op1val:0x7e00; valaddr_reg:x15; +val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x18; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x4, x20, dyn, 0, 0, x15, 16*FLEN/8, x23, x8, x18,FLREG) + +inst_17:// rs1==x2, rd==x17,fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x2; dest:x17; op1val:0xfe00; valaddr_reg:x15; +val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x18; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x17, x2, dyn, 0, 0, x15, 17*FLEN/8, x23, x8, x18,FLREG) + +inst_18:// rs1==x6, rd==x7,fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x6; dest:x7; op1val:0x7e01; valaddr_reg:x15; +val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x18; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x7, x6, dyn, 0, 0, x15, 18*FLEN/8, x23, x8, x18,FLREG) +RVTEST_VALBASEUPD(x11,test_dataset_1) + +inst_19:// rs1==x27, rd==x15,fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x27; dest:x15; op1val:0xfe55; valaddr_reg:x11; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x18; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x15, x27, dyn, 0, 0, x11, 0*FLEN/8, x13, x8, x18,FLREG) +RVTEST_SIGBASE(x4,signature_x4_0) + +inst_20:// rs1==x23, rd==x6,fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x23; dest:x6; op1val:0x7c01; valaddr_reg:x11; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x6, x23, dyn, 0, 0, x11, 1*FLEN/8, x13, x4, x9,FLREG) + +inst_21:// rs1==x15, rd==x1,fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x15; dest:x1; op1val:0xfd55; valaddr_reg:x11; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x1, x15, dyn, 0, 0, x11, 2*FLEN/8, x13, x4, x9,FLREG) + +inst_22:// rs1==x10, rd==x8,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x10; dest:x8; op1val:0x3c00; valaddr_reg:x11; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x8, x10, dyn, 0, 0, x11, 3*FLEN/8, x13, x4, x9,FLREG) + +inst_23:// rs1==x18, rd==x2,fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x18; dest:x2; op1val:0xbc00; valaddr_reg:x11; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x2, x18, dyn, 0, 0, x11, 4*FLEN/8, x13, x4, x9,FLREG) + +inst_24:// rs1==x7, rd==x22, +/* opcode: fcvt.lu.h ; op1:x7; dest:x22; op1val:0x0; valaddr_reg:x11; +val_offset:5*FLEN/8; rmval:rne; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x22, x7, rne, 0, 0, x11, 5*FLEN/8, x13, x4, x9,FLREG) + +inst_25:// rs1==x14, rd==x26, +/* opcode: fcvt.lu.h ; op1:x14; dest:x26; op1val:0x0; valaddr_reg:x11; +val_offset:6*FLEN/8; rmval:rne; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x26, x14, rne, 0, 0, x11, 6*FLEN/8, x13, x4, x9,FLREG) + +inst_26:// rs1==x3, rd==x18, +/* opcode: fcvt.lu.h ; op1:x3; dest:x18; op1val:0x0; valaddr_reg:x11; +val_offset:7*FLEN/8; rmval:rne; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x18, x3, rne, 0, 0, x11, 7*FLEN/8, x13, x4, x9,FLREG) + +inst_27:// rs1==x8, rd==x23, +/* opcode: fcvt.lu.h ; op1:x8; dest:x23; op1val:0x0; valaddr_reg:x11; +val_offset:8*FLEN/8; rmval:rne; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x23, x8, rne, 0, 0, x11, 8*FLEN/8, x13, x4, x9,FLREG) + +inst_28:// rs1==x29, rd==x27, +/* opcode: fcvt.lu.h ; op1:x29; dest:x27; op1val:0x0; valaddr_reg:x11; +val_offset:9*FLEN/8; rmval:rne; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x27, x29, rne, 0, 0, x11, 9*FLEN/8, x13, x4, x9,FLREG) + +inst_29:// rs1==x16, rd==x12, +/* opcode: fcvt.lu.h ; op1:x16; dest:x12; op1val:0x0; valaddr_reg:x11; +val_offset:10*FLEN/8; rmval:rne; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x12, x16, rne, 0, 0, x11, 10*FLEN/8, x13, x4, x9,FLREG) + +inst_30:// rs1==x0, rd==x24, +/* opcode: fcvt.lu.h ; op1:x0; dest:x24; op1val:0x0; valaddr_reg:x11; +val_offset:11*FLEN/8; rmval:rne; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x24, x0, rne, 0, 0, x11, 11*FLEN/8, x13, x4, x9,FLREG) + +inst_31:// rs1==x24, rd==x5, +/* opcode: fcvt.lu.h ; op1:x24; dest:x5; op1val:0x0; valaddr_reg:x11; +val_offset:12*FLEN/8; rmval:rne; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x5, x24, rne, 0, 0, x11, 12*FLEN/8, x13, x4, x9,FLREG) + +inst_32:// fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x7c00; valaddr_reg:x11; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x11, 13*FLEN/8, x13, x4, x9,FLREG) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1,32,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(2,32,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(1023,32,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(1024,32,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(1025,32,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31744,32,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(32256,32,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(32257,32,FLEN) +test_dataset_1: +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(31744,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x8_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x8_1: + .fill 40*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x4_0: + .fill 26*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/Zhinx/src/fcvt.lu.h_b22-01.S b/riscv-test-suite/rv64i_m/Zhinx/src/fcvt.lu.h_b22-01.S new file mode 100644 index 000000000..336bb457e --- /dev/null +++ b/riscv-test-suite/rv64i_m/Zhinx/src/fcvt.lu.h_b22-01.S @@ -0,0 +1,617 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 04:44:02 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64Zhinx/rv64h_fcvt.lu.h.cgf \ + \ +// -- xlen 64 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.lu.h instruction of the RISC-V RV64_Zfinx_Zhinx extension for the fcvt.lu.h_b22 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fcvt.lu.h_b22) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x8,test_dataset_0) +RVTEST_SIGBASE(x3,signature_x3_1) + +inst_0:// rs1 != rd, rs1==x20, rd==x4,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x20; dest:x4; op1val:0x3249; valaddr_reg:x8; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x10; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x4, x20, dyn, 0, 0, x8, 0*FLEN/8, x12, x3, x10,FLREG) + +inst_1:// rs1 == rd, rs1==x28, rd==x28,fs1 == 0 and fe1 == 0x0d and fm1 == 0x1b7 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x28; dest:x28; op1val:0x35b7; valaddr_reg:x8; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x10; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x28, x28, dyn, 0, 0, x8, 1*FLEN/8, x12, x3, x10,FLREG) + +inst_2:// rs1==x25, rd==x2,fs1 == 0 and fe1 == 0x0e and fm1 == 0x24f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x25; dest:x2; op1val:0x3a4f; valaddr_reg:x8; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x10; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x2, x25, dyn, 0, 0, x8, 2*FLEN/8, x12, x3, x10,FLREG) + +inst_3:// rs1==x0, rd==x16,fs1 == 0 and fe1 == 0x0f and fm1 == 0x0d3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x0; dest:x16; op1val:0x0; valaddr_reg:x8; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x10; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x16, x0, dyn, 0, 0, x8, 3*FLEN/8, x12, x3, x10,FLREG) + +inst_4:// rs1==x16, rd==x13,fs1 == 0 and fe1 == 0x10 and fm1 == 0x340 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x16; dest:x13; op1val:0x4340; valaddr_reg:x8; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x10; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x13, x16, dyn, 0, 0, x8, 4*FLEN/8, x12, x3, x10,FLREG) + +inst_5:// rs1==x30, rd==x25,fs1 == 0 and fe1 == 0x11 and fm1 == 0x34b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x25; op1val:0x474b; valaddr_reg:x8; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x10; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x25, x30, dyn, 0, 0, x8, 5*FLEN/8, x12, x3, x10,FLREG) + +inst_6:// rs1==x21, rd==x14,fs1 == 1 and fe1 == 0x12 and fm1 == 0x29d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x21; dest:x14; op1val:0xca9d; valaddr_reg:x8; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x10; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x14, x21, dyn, 0, 0, x8, 6*FLEN/8, x12, x3, x10,FLREG) + +inst_7:// rs1==x24, rd==x29,fs1 == 0 and fe1 == 0x13 and fm1 == 0x0a4 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x24; dest:x29; op1val:0x4ca4; valaddr_reg:x8; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x10; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x29, x24, dyn, 0, 0, x8, 7*FLEN/8, x12, x3, x10,FLREG) + +inst_8:// rs1==x29, rd==x19,fs1 == 0 and fe1 == 0x14 and fm1 == 0x215 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x29; dest:x19; op1val:0x5215; valaddr_reg:x8; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x10; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x19, x29, dyn, 0, 0, x8, 8*FLEN/8, x12, x3, x10,FLREG) + +inst_9:// rs1==x6, rd==x17,fs1 == 0 and fe1 == 0x15 and fm1 == 0x14f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x6; dest:x17; op1val:0x554f; valaddr_reg:x8; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x10; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x17, x6, dyn, 0, 0, x8, 9*FLEN/8, x12, x3, x10,FLREG) + +inst_10:// rs1==x26, rd==x15,fs1 == 1 and fe1 == 0x16 and fm1 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x26; dest:x15; op1val:0xd8ff; valaddr_reg:x8; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x10; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x15, x26, dyn, 0, 0, x8, 10*FLEN/8, x12, x3, x10,FLREG) + +inst_11:// rs1==x14, rd==x5,fs1 == 1 and fe1 == 0x17 and fm1 == 0x3cf and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x14; dest:x5; op1val:0xdfcf; valaddr_reg:x8; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x10; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x5, x14, dyn, 0, 0, x8, 11*FLEN/8, x12, x3, x10,FLREG) + +inst_12:// rs1==x1, rd==x20,fs1 == 0 and fe1 == 0x18 and fm1 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x1; dest:x20; op1val:0x63fc; valaddr_reg:x8; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x10; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x20, x1, dyn, 0, 0, x8, 12*FLEN/8, x12, x3, x10,FLREG) + +inst_13:// rs1==x7, rd==x18,fs1 == 0 and fe1 == 0x19 and fm1 == 0x02d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x7; dest:x18; op1val:0x642d; valaddr_reg:x8; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x10; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x18, x7, dyn, 0, 0, x8, 13*FLEN/8, x12, x3, x10,FLREG) + +inst_14:// rs1==x11, rd==x30,fs1 == 0 and fe1 == 0x1a and fm1 == 0x370 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x11; dest:x30; op1val:0x6b70; valaddr_reg:x8; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x10; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x30, x11, dyn, 0, 0, x8, 14*FLEN/8, x12, x3, x10,FLREG) + +inst_15:// rs1==x9, rd==x23,fs1 == 0 and fe1 == 0x1b and fm1 == 0x269 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x9; dest:x23; op1val:0x6e69; valaddr_reg:x8; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x10; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x23, x9, dyn, 0, 0, x8, 15*FLEN/8, x12, x3, x10,FLREG) +RVTEST_VALBASEUPD(x16,test_dataset_1) + +inst_16:// rs1==x18, rd==x8,fs1 == 0 and fe1 == 0x1c and fm1 == 0x186 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x18; dest:x8; op1val:0x7186; valaddr_reg:x16; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x10; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x8, x18, dyn, 0, 0, x16, 0*FLEN/8, x25, x3, x10,FLREG) + +inst_17:// rs1==x5, rd==x31,fs1 == 1 and fe1 == 0x1d and fm1 == 0x122 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x5; dest:x31; op1val:0xf522; valaddr_reg:x16; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x10; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x5, dyn, 0, 0, x16, 1*FLEN/8, x25, x3, x10,FLREG) + +inst_18:// rs1==x8, rd==x9,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x8; dest:x9; op1val:0x7ab3; valaddr_reg:x16; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x14; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x9, x8, dyn, 0, 0, x16, 2*FLEN/8, x25, x3, x14,FLREG) + +inst_19:// rs1==x17, rd==x7,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x17; dest:x7; op1val:0x7bff; valaddr_reg:x16; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x14; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x7, x17, dyn, 0, 0, x16, 3*FLEN/8, x25, x3, x14,FLREG) + +inst_20:// rs1==x15, rd==x27,fs1 == 1 and fe1 == 0x00 and fm1 == 0x2be and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x15; dest:x27; op1val:0x82be; valaddr_reg:x16; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x14; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x27, x15, dyn, 0, 0, x16, 4*FLEN/8, x25, x3, x14,FLREG) +RVTEST_SIGBASE(x5,signature_x5_0) + +inst_21:// rs1==x23, rd==x0,fs1 == 1 and fe1 == 0x01 and fm1 == 0x2a5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x23; dest:x0; op1val:0x86a5; valaddr_reg:x16; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x14; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x0, x23, dyn, 0, 0, x16, 5*FLEN/8, x25, x5, x14,FLREG) + +inst_22:// rs1==x10, rd==x24,fs1 == 1 and fe1 == 0x02 and fm1 == 0x088 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x10; dest:x24; op1val:0x8888; valaddr_reg:x16; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x14; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x24, x10, dyn, 0, 0, x16, 6*FLEN/8, x25, x5, x14,FLREG) + +inst_23:// rs1==x19, rd==x6,fs1 == 1 and fe1 == 0x03 and fm1 == 0x312 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x19; dest:x6; op1val:0x8f12; valaddr_reg:x16; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x14; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x6, x19, dyn, 0, 0, x16, 7*FLEN/8, x25, x5, x14,FLREG) + +inst_24:// rs1==x2, rd==x1,fs1 == 1 and fe1 == 0x04 and fm1 == 0x3ed and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x2; dest:x1; op1val:0x93ed; valaddr_reg:x16; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x14; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x1, x2, dyn, 0, 0, x16, 8*FLEN/8, x25, x5, x14,FLREG) + +inst_25:// rs1==x31, rd==x26,fs1 == 1 and fe1 == 0x05 and fm1 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x31; dest:x26; op1val:0x97e0; valaddr_reg:x16; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x14; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x26, x31, dyn, 0, 0, x16, 9*FLEN/8, x25, x5, x14,FLREG) + +inst_26:// rs1==x12, rd==x22,fs1 == 1 and fe1 == 0x06 and fm1 == 0x274 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x12; dest:x22; op1val:0x9a74; valaddr_reg:x16; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x14; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x22, x12, dyn, 0, 0, x16, 10*FLEN/8, x25, x5, x14,FLREG) + +inst_27:// rs1==x27, rd==x21,fs1 == 1 and fe1 == 0x07 and fm1 == 0x02d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x27; dest:x21; op1val:0x9c2d; valaddr_reg:x16; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x14; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x21, x27, dyn, 0, 0, x16, 11*FLEN/8, x25, x5, x14,FLREG) + +inst_28:// rs1==x4, rd==x11,fs1 == 1 and fe1 == 0x08 and fm1 == 0x004 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x4; dest:x11; op1val:0xa004; valaddr_reg:x16; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x14; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x11, x4, dyn, 0, 0, x16, 12*FLEN/8, x25, x5, x14,FLREG) + +inst_29:// rs1==x22, rd==x10,fs1 == 1 and fe1 == 0x09 and fm1 == 0x089 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x22; dest:x10; op1val:0xa489; valaddr_reg:x16; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x14; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x10, x22, dyn, 0, 0, x16, 13*FLEN/8, x25, x5, x14,FLREG) + +inst_30:// rs1==x13, rd==x12,fs1 == 1 and fe1 == 0x0a and fm1 == 0x3c3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x13; dest:x12; op1val:0xabc3; valaddr_reg:x16; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x14; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x12, x13, dyn, 0, 0, x16, 14*FLEN/8, x25, x5, x14,FLREG) + +inst_31:// rs1==x3,fs1 == 1 and fe1 == 0x0b and fm1 == 0x136 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x3; dest:x20; op1val:0xad36; valaddr_reg:x16; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x14; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x20, x3, dyn, 0, 0, x16, 15*FLEN/8, x25, x5, x14,FLREG) +RVTEST_VALBASEUPD(x1,test_dataset_2) + +inst_32:// rd==x3,fs1 == 1 and fe1 == 0x0c and fm1 == 0x176 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x12; dest:x3; op1val:0xb176; valaddr_reg:x1; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x14; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x3, x12, dyn, 0, 0, x1, 0*FLEN/8, x2, x5, x14,FLREG) + +inst_33:// fs1 == 1 and fe1 == 0x0d and fm1 == 0x397 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xb797; valaddr_reg:x1; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x14; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x1, 1*FLEN/8, x2, x5, x14,FLREG) + +inst_34:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x141 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xb941; valaddr_reg:x1; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x14; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x1, 2*FLEN/8, x2, x5, x14,FLREG) + +inst_35:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x232 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xbe32; valaddr_reg:x1; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x14; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x1, 3*FLEN/8, x2, x5, x14,FLREG) + +inst_36:// fs1 == 1 and fe1 == 0x10 and fm1 == 0x1be and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xc1be; valaddr_reg:x1; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x14; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x1, 4*FLEN/8, x2, x5, x14,FLREG) + +inst_37:// fs1 == 1 and fe1 == 0x11 and fm1 == 0x042 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xc442; valaddr_reg:x1; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x14; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x1, 5*FLEN/8, x2, x5, x14,FLREG) + +inst_38:// fs1 == 1 and fe1 == 0x12 and fm1 == 0x256 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xca56; valaddr_reg:x1; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x14; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x1, 6*FLEN/8, x2, x5, x14,FLREG) + +inst_39:// fs1 == 1 and fe1 == 0x13 and fm1 == 0x360 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xcf60; valaddr_reg:x1; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x14; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x1, 7*FLEN/8, x2, x5, x14,FLREG) + +inst_40:// fs1 == 1 and fe1 == 0x14 and fm1 == 0x0a0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xd0a0; valaddr_reg:x1; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x14; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x1, 8*FLEN/8, x2, x5, x14,FLREG) + +inst_41:// fs1 == 1 and fe1 == 0x15 and fm1 == 0x0e5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xd4e5; valaddr_reg:x1; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x14; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x1, 9*FLEN/8, x2, x5, x14,FLREG) + +inst_42:// fs1 == 1 and fe1 == 0x16 and fm1 == 0x1a6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xd9a6; valaddr_reg:x1; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x14; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x1, 10*FLEN/8, x2, x5, x14,FLREG) + +inst_43:// fs1 == 1 and fe1 == 0x17 and fm1 == 0x025 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xdc25; valaddr_reg:x1; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x14; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x1, 11*FLEN/8, x2, x5, x14,FLREG) + +inst_44:// fs1 == 1 and fe1 == 0x18 and fm1 == 0x1fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xe1fc; valaddr_reg:x1; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x14; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x1, 12*FLEN/8, x2, x5, x14,FLREG) + +inst_45:// fs1 == 1 and fe1 == 0x19 and fm1 == 0x345 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xe745; valaddr_reg:x1; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x14; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x1, 13*FLEN/8, x2, x5, x14,FLREG) + +inst_46:// fs1 == 1 and fe1 == 0x1a and fm1 == 0x2a1 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xeaa1; valaddr_reg:x1; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x14; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x1, 14*FLEN/8, x2, x5, x14,FLREG) + +inst_47:// fs1 == 1 and fe1 == 0x1b and fm1 == 0x222 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xee22; valaddr_reg:x1; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x14; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x1, 15*FLEN/8, x2, x5, x14,FLREG) + +inst_48:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x36b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xf36b; valaddr_reg:x1; +val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x14; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x1, 16*FLEN/8, x2, x5, x14,FLREG) + +inst_49:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x099 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xf499; valaddr_reg:x1; +val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x14; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x1, 17*FLEN/8, x2, x5, x14,FLREG) + +inst_50:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x244 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xfa44; valaddr_reg:x1; +val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x14; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x1, 18*FLEN/8, x2, x5, x14,FLREG) + +inst_51:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xfbff; valaddr_reg:x1; +val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x14; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x1, 19*FLEN/8, x2, x5, x14,FLREG) + +inst_52:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x267 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x267; valaddr_reg:x1; +val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x14; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x1, 20*FLEN/8, x2, x5, x14,FLREG) + +inst_53:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x073 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x473; valaddr_reg:x1; +val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x14; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x1, 21*FLEN/8, x2, x5, x14,FLREG) + +inst_54:// fs1 == 0 and fe1 == 0x02 and fm1 == 0x31a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xb1a; valaddr_reg:x1; +val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x14; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x1, 22*FLEN/8, x2, x5, x14,FLREG) + +inst_55:// fs1 == 0 and fe1 == 0x03 and fm1 == 0x062 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xc62; valaddr_reg:x1; +val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x14; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x1, 23*FLEN/8, x2, x5, x14,FLREG) + +inst_56:// fs1 == 0 and fe1 == 0x04 and fm1 == 0x0aa and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x10aa; valaddr_reg:x1; +val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x14; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x1, 24*FLEN/8, x2, x5, x14,FLREG) + +inst_57:// fs1 == 0 and fe1 == 0x05 and fm1 == 0x33a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x173a; valaddr_reg:x1; +val_offset:25*FLEN/8; rmval:dyn; correctval:??; testreg:x14; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x1, 25*FLEN/8, x2, x5, x14,FLREG) + +inst_58:// fs1 == 0 and fe1 == 0x06 and fm1 == 0x3ca and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x1bca; valaddr_reg:x1; +val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x14; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x1, 26*FLEN/8, x2, x5, x14,FLREG) + +inst_59:// fs1 == 0 and fe1 == 0x07 and fm1 == 0x1bb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x1dbb; valaddr_reg:x1; +val_offset:27*FLEN/8; rmval:dyn; correctval:??; testreg:x14; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x1, 27*FLEN/8, x2, x5, x14,FLREG) + +inst_60:// fs1 == 0 and fe1 == 0x08 and fm1 == 0x1a8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x21a8; valaddr_reg:x1; +val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x14; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x1, 28*FLEN/8, x2, x5, x14,FLREG) + +inst_61:// fs1 == 0 and fe1 == 0x09 and fm1 == 0x0fb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x24fb; valaddr_reg:x1; +val_offset:29*FLEN/8; rmval:dyn; correctval:??; testreg:x14; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x1, 29*FLEN/8, x2, x5, x14,FLREG) + +inst_62:// fs1 == 0 and fe1 == 0x0a and fm1 == 0x119 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x2919; valaddr_reg:x1; +val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x14; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x1, 30*FLEN/8, x2, x5, x14,FLREG) + +inst_63:// fs1 == 0 and fe1 == 0x0b and fm1 == 0x278 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x2e78; valaddr_reg:x1; +val_offset:31*FLEN/8; rmval:dyn; correctval:??; testreg:x14; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x1, 31*FLEN/8, x2, x5, x14,FLREG) + +inst_64:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0b6 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x30b6; valaddr_reg:x1; +val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x14; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x1, 32*FLEN/8, x2, x5, x14,FLREG) + +inst_65:// fs1 == 0 and fe1 == 0x0d and fm1 == 0x07a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x347a; valaddr_reg:x1; +val_offset:33*FLEN/8; rmval:dyn; correctval:??; testreg:x14; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x1, 33*FLEN/8, x2, x5, x14,FLREG) + +inst_66:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1d2 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x39d2; valaddr_reg:x1; +val_offset:34*FLEN/8; rmval:dyn; correctval:??; testreg:x14; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x1, 34*FLEN/8, x2, x5, x14,FLREG) + +inst_67:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x0a8 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x3ca8; valaddr_reg:x1; +val_offset:35*FLEN/8; rmval:dyn; correctval:??; testreg:x14; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x1, 35*FLEN/8, x2, x5, x14,FLREG) + +inst_68:// fs1 == 0 and fe1 == 0x10 and fm1 == 0x298 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x4298; valaddr_reg:x1; +val_offset:36*FLEN/8; rmval:dyn; correctval:??; testreg:x14; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x1, 36*FLEN/8, x2, x5, x14,FLREG) + +inst_69:// fs1 == 0 and fe1 == 0x11 and fm1 == 0x348 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x4748; valaddr_reg:x1; +val_offset:37*FLEN/8; rmval:dyn; correctval:??; testreg:x14; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x1, 37*FLEN/8, x2, x5, x14,FLREG) + +inst_70:// fs1 == 0 and fe1 == 0x16 and fm1 == 0x31c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x5b1c; valaddr_reg:x1; +val_offset:38*FLEN/8; rmval:dyn; correctval:??; testreg:x14; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x1, 38*FLEN/8, x2, x5, x14,FLREG) + +inst_71:// fs1 == 0 and fe1 == 0x18 and fm1 == 0x317 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x6317; valaddr_reg:x1; +val_offset:39*FLEN/8; rmval:dyn; correctval:??; testreg:x14; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x1, 39*FLEN/8, x2, x5, x14,FLREG) + +inst_72:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x0d3 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x3cd3; valaddr_reg:x1; +val_offset:40*FLEN/8; rmval:dyn; correctval:??; testreg:x14; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x1, 40*FLEN/8, x2, x5, x14,FLREG) + +inst_73:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x2a5 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x86a5; valaddr_reg:x1; +val_offset:41*FLEN/8; rmval:dyn; correctval:??; testreg:x14; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x1, 41*FLEN/8, x2, x5, x14,FLREG) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(12873,32,FLEN) +NAN_BOXED(13751,32,FLEN) +NAN_BOXED(14927,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(17216,32,FLEN) +NAN_BOXED(18251,32,FLEN) +NAN_BOXED(51869,16,FLEN) +NAN_BOXED(19620,32,FLEN) +NAN_BOXED(21013,32,FLEN) +NAN_BOXED(21839,32,FLEN) +NAN_BOXED(55551,16,FLEN) +NAN_BOXED(57295,16,FLEN) +NAN_BOXED(25596,32,FLEN) +NAN_BOXED(25645,32,FLEN) +NAN_BOXED(27504,32,FLEN) +NAN_BOXED(28265,32,FLEN) +test_dataset_1: +NAN_BOXED(29062,32,FLEN) +NAN_BOXED(62754,16,FLEN) +NAN_BOXED(31411,32,FLEN) +NAN_BOXED(31743,32,FLEN) +NAN_BOXED(33470,16,FLEN) +NAN_BOXED(34469,16,FLEN) +NAN_BOXED(34952,16,FLEN) +NAN_BOXED(36626,16,FLEN) +NAN_BOXED(37869,16,FLEN) +NAN_BOXED(38880,16,FLEN) +NAN_BOXED(39540,16,FLEN) +NAN_BOXED(39981,16,FLEN) +NAN_BOXED(40964,16,FLEN) +NAN_BOXED(42121,16,FLEN) +NAN_BOXED(43971,16,FLEN) +NAN_BOXED(44342,16,FLEN) +test_dataset_2: +NAN_BOXED(45430,16,FLEN) +NAN_BOXED(46999,16,FLEN) +NAN_BOXED(47425,16,FLEN) +NAN_BOXED(48690,16,FLEN) +NAN_BOXED(49598,16,FLEN) +NAN_BOXED(50242,16,FLEN) +NAN_BOXED(51798,16,FLEN) +NAN_BOXED(53088,16,FLEN) +NAN_BOXED(53408,16,FLEN) +NAN_BOXED(54501,16,FLEN) +NAN_BOXED(55718,16,FLEN) +NAN_BOXED(56357,16,FLEN) +NAN_BOXED(57852,16,FLEN) +NAN_BOXED(59205,16,FLEN) +NAN_BOXED(60065,16,FLEN) +NAN_BOXED(60962,16,FLEN) +NAN_BOXED(62315,16,FLEN) +NAN_BOXED(62617,16,FLEN) +NAN_BOXED(64068,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(615,16,FLEN) +NAN_BOXED(1139,16,FLEN) +NAN_BOXED(2842,16,FLEN) +NAN_BOXED(3170,16,FLEN) +NAN_BOXED(4266,16,FLEN) +NAN_BOXED(5946,16,FLEN) +NAN_BOXED(7114,16,FLEN) +NAN_BOXED(7611,16,FLEN) +NAN_BOXED(8616,16,FLEN) +NAN_BOXED(9467,16,FLEN) +NAN_BOXED(10521,16,FLEN) +NAN_BOXED(11896,16,FLEN) +NAN_BOXED(12470,16,FLEN) +NAN_BOXED(13434,16,FLEN) +NAN_BOXED(14802,16,FLEN) +NAN_BOXED(15528,16,FLEN) +NAN_BOXED(17048,16,FLEN) +NAN_BOXED(18248,16,FLEN) +NAN_BOXED(23324,16,FLEN) +NAN_BOXED(25367,16,FLEN) +NAN_BOXED(15571,16,FLEN) +NAN_BOXED(34469,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x3_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x3_1: + .fill 42*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x5_0: + .fill 106*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/Zhinx/src/fcvt.lu.h_b23-01.S b/riscv-test-suite/rv64i_m/Zhinx/src/fcvt.lu.h_b23-01.S new file mode 100644 index 000000000..2ec6717cd --- /dev/null +++ b/riscv-test-suite/rv64i_m/Zhinx/src/fcvt.lu.h_b23-01.S @@ -0,0 +1,428 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 04:44:02 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64Zhinx/rv64h_fcvt.lu.h.cgf \ + \ +// -- xlen 64 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.lu.h instruction of the RISC-V RV64_Zfinx_Zhinx extension for the fcvt.lu.h_b23 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fcvt.lu.h_b23) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x2,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0:// rs1 != rd, rs1==x7, rd==x23,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x7; dest:x23; op1val:0x77fc; valaddr_reg:x2; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x22; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x23, x7, dyn, 0, 0, x2, 0*FLEN/8, x13, x1, x22,FLREG) + +inst_1:// rs1 == rd, rs1==x21, rd==x21,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x21; dest:x21; op1val:0x77fc; valaddr_reg:x2; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x22; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.lu.h, x21, x21, dyn, 32, 0, x2, 1*FLEN/8, x13, x1, x22,FLREG) + +inst_2:// rs1==x12, rd==x5,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x12; dest:x5; op1val:0x77fc; valaddr_reg:x2; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x22; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.lu.h, x5, x12, dyn, 64, 0, x2, 2*FLEN/8, x13, x1, x22,FLREG) + +inst_3:// rs1==x15, rd==x30,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x15; dest:x30; op1val:0x77fc; valaddr_reg:x2; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x22; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.lu.h, x30, x15, dyn, 96, 0, x2, 3*FLEN/8, x13, x1, x22,FLREG) + +inst_4:// rs1==x19, rd==x4,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x19; dest:x4; op1val:0x77fc; valaddr_reg:x2; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x22; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.lu.h, x4, x19, dyn, 128, 0, x2, 4*FLEN/8, x13, x1, x22,FLREG) + +inst_5:// rs1==x14, rd==x20,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fd and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x14; dest:x20; op1val:0x77fd; valaddr_reg:x2; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x22; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x20, x14, dyn, 0, 0, x2, 5*FLEN/8, x13, x1, x22,FLREG) + +inst_6:// rs1==x18, rd==x31,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fd and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x18; dest:x31; op1val:0x77fd; valaddr_reg:x2; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x22; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.lu.h, x31, x18, dyn, 32, 0, x2, 6*FLEN/8, x13, x1, x22,FLREG) + +inst_7:// rs1==x28, rd==x17,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fd and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x28; dest:x17; op1val:0x77fd; valaddr_reg:x2; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x22; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.lu.h, x17, x28, dyn, 64, 0, x2, 7*FLEN/8, x13, x1, x22,FLREG) + +inst_8:// rs1==x31, rd==x25,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fd and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x31; dest:x25; op1val:0x77fd; valaddr_reg:x2; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x22; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.lu.h, x25, x31, dyn, 96, 0, x2, 8*FLEN/8, x13, x1, x22,FLREG) + +inst_9:// rs1==x9, rd==x8,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fd and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x9; dest:x8; op1val:0x77fd; valaddr_reg:x2; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x22; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.lu.h, x8, x9, dyn, 128, 0, x2, 9*FLEN/8, x13, x1, x22,FLREG) + +inst_10:// rs1==x6, rd==x12,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x6; dest:x12; op1val:0x77fe; valaddr_reg:x2; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x22; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x12, x6, dyn, 0, 0, x2, 10*FLEN/8, x13, x1, x22,FLREG) + +inst_11:// rs1==x8, rd==x11,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x8; dest:x11; op1val:0x77fe; valaddr_reg:x2; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x22; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.lu.h, x11, x8, dyn, 32, 0, x2, 11*FLEN/8, x13, x1, x22,FLREG) + +inst_12:// rs1==x26, rd==x18,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x26; dest:x18; op1val:0x77fe; valaddr_reg:x2; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x22; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.lu.h, x18, x26, dyn, 64, 0, x2, 12*FLEN/8, x13, x1, x22,FLREG) + +inst_13:// rs1==x23, rd==x16,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x23; dest:x16; op1val:0x77fe; valaddr_reg:x2; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x22; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.lu.h, x16, x23, dyn, 96, 0, x2, 13*FLEN/8, x13, x1, x22,FLREG) + +inst_14:// rs1==x3, rd==x15,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x3; dest:x15; op1val:0x77fe; valaddr_reg:x2; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x22; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.lu.h, x15, x3, dyn, 128, 0, x2, 14*FLEN/8, x13, x1, x22,FLREG) + +inst_15:// rs1==x10, rd==x27,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x10; dest:x27; op1val:0x77ff; valaddr_reg:x2; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x22; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x27, x10, dyn, 0, 0, x2, 15*FLEN/8, x13, x1, x22,FLREG) +RVTEST_VALBASEUPD(x15,test_dataset_1) + +inst_16:// rs1==x13, rd==x2,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x13; dest:x2; op1val:0x77ff; valaddr_reg:x15; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x22; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.lu.h, x2, x13, dyn, 32, 0, x15, 0*FLEN/8, x18, x1, x22,FLREG) +RVTEST_SIGBASE(x8,signature_x8_0) + +inst_17:// rs1==x11, rd==x26,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x11; dest:x26; op1val:0x77ff; valaddr_reg:x15; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x12; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.lu.h, x26, x11, dyn, 64, 0, x15, 1*FLEN/8, x18, x8, x12,FLREG) + +inst_18:// rs1==x20, rd==x19,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x20; dest:x19; op1val:0x77ff; valaddr_reg:x15; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x12; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.lu.h, x19, x20, dyn, 96, 0, x15, 2*FLEN/8, x18, x8, x12,FLREG) + +inst_19:// rs1==x30, rd==x10,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x10; op1val:0x77ff; valaddr_reg:x15; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x12; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.lu.h, x10, x30, dyn, 128, 0, x15, 3*FLEN/8, x18, x8, x12,FLREG) + +inst_20:// rs1==x16, rd==x9,fs1 == 0 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x16; dest:x9; op1val:0x7800; valaddr_reg:x15; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x12; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x9, x16, dyn, 0, 0, x15, 4*FLEN/8, x18, x8, x12,FLREG) + +inst_21:// rs1==x27, rd==x1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x27; dest:x1; op1val:0x7800; valaddr_reg:x15; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x12; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.lu.h, x1, x27, dyn, 32, 0, x15, 5*FLEN/8, x18, x8, x12,FLREG) + +inst_22:// rs1==x1, rd==x14,fs1 == 0 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x1; dest:x14; op1val:0x7800; valaddr_reg:x15; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x12; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.lu.h, x14, x1, dyn, 64, 0, x15, 6*FLEN/8, x18, x8, x12,FLREG) + +inst_23:// rs1==x2, rd==x7,fs1 == 0 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x2; dest:x7; op1val:0x7800; valaddr_reg:x15; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x12; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.lu.h, x7, x2, dyn, 96, 0, x15, 7*FLEN/8, x18, x8, x12,FLREG) + +inst_24:// rs1==x25, rd==x6,fs1 == 0 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x25; dest:x6; op1val:0x7800; valaddr_reg:x15; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x12; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.lu.h, x6, x25, dyn, 128, 0, x15, 8*FLEN/8, x18, x8, x12,FLREG) + +inst_25:// rs1==x4, rd==x0,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x4; dest:x0; op1val:0x7801; valaddr_reg:x15; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x12; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x0, x4, dyn, 0, 0, x15, 9*FLEN/8, x18, x8, x12,FLREG) + +inst_26:// rs1==x0, rd==x13,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x0; dest:x13; op1val:0x0; valaddr_reg:x15; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x12; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.lu.h, x13, x0, dyn, 32, 0, x15, 10*FLEN/8, x18, x8, x12,FLREG) + +inst_27:// rs1==x24, rd==x3,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x24; dest:x3; op1val:0x7801; valaddr_reg:x15; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x12; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.lu.h, x3, x24, dyn, 64, 0, x15, 11*FLEN/8, x18, x8, x12,FLREG) + +inst_28:// rs1==x29, rd==x22,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x29; dest:x22; op1val:0x7801; valaddr_reg:x15; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x12; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.lu.h, x22, x29, dyn, 96, 0, x15, 12*FLEN/8, x18, x8, x12,FLREG) + +inst_29:// rs1==x22, rd==x24,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x22; dest:x24; op1val:0x7801; valaddr_reg:x15; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x12; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.lu.h, x24, x22, dyn, 128, 0, x15, 13*FLEN/8, x18, x8, x12,FLREG) + +inst_30:// rs1==x17, rd==x28,fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x17; dest:x28; op1val:0x7802; valaddr_reg:x15; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x12; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x28, x17, dyn, 0, 0, x15, 14*FLEN/8, x18, x8, x12,FLREG) + +inst_31:// rs1==x5, rd==x29,fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x5; dest:x29; op1val:0x7802; valaddr_reg:x15; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x12; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.lu.h, x29, x5, dyn, 32, 0, x15, 15*FLEN/8, x18, x8, x12,FLREG) +RVTEST_VALBASEUPD(x1,test_dataset_2) + +inst_32:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x7802; valaddr_reg:x1; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x12; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 64, 0, x1, 0*FLEN/8, x2, x8, x12,FLREG) + +inst_33:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x7802; valaddr_reg:x1; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x12; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 96, 0, x1, 1*FLEN/8, x2, x8, x12,FLREG) + +inst_34:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x7802; valaddr_reg:x1; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x12; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 128, 0, x1, 2*FLEN/8, x2, x8, x12,FLREG) + +inst_35:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x7803; valaddr_reg:x1; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x12; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x1, 3*FLEN/8, x2, x8, x12,FLREG) + +inst_36:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x003 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x7803; valaddr_reg:x1; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x12; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 32, 0, x1, 4*FLEN/8, x2, x8, x12,FLREG) + +inst_37:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x003 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x7803; valaddr_reg:x1; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x12; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 64, 0, x1, 5*FLEN/8, x2, x8, x12,FLREG) + +inst_38:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x003 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x7803; valaddr_reg:x1; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x12; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 96, 0, x1, 6*FLEN/8, x2, x8, x12,FLREG) + +inst_39:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x003 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x7803; valaddr_reg:x1; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x12; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 128, 0, x1, 7*FLEN/8, x2, x8, x12,FLREG) + +inst_40:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x7804; valaddr_reg:x1; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x12; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x1, 8*FLEN/8, x2, x8, x12,FLREG) + +inst_41:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x7804; valaddr_reg:x1; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x12; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 32, 0, x1, 9*FLEN/8, x2, x8, x12,FLREG) + +inst_42:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x7804; valaddr_reg:x1; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x12; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 64, 0, x1, 10*FLEN/8, x2, x8, x12,FLREG) + +inst_43:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x7804; valaddr_reg:x1; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x12; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 96, 0, x1, 11*FLEN/8, x2, x8, x12,FLREG) + +inst_44:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x7804; valaddr_reg:x1; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x12; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 128, 0, x1, 12*FLEN/8, x2, x8, x12,FLREG) + +inst_45:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x7801; valaddr_reg:x1; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x12; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x1, 13*FLEN/8, x2, x8, x12,FLREG) + +inst_46:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x7801; valaddr_reg:x1; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x12; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 32, 0, x1, 14*FLEN/8, x2, x8, x12,FLREG) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(30716,32,FLEN) +NAN_BOXED(30716,32,FLEN) +NAN_BOXED(30716,32,FLEN) +NAN_BOXED(30716,32,FLEN) +NAN_BOXED(30716,32,FLEN) +NAN_BOXED(30717,32,FLEN) +NAN_BOXED(30717,32,FLEN) +NAN_BOXED(30717,32,FLEN) +NAN_BOXED(30717,32,FLEN) +NAN_BOXED(30717,32,FLEN) +NAN_BOXED(30718,32,FLEN) +NAN_BOXED(30718,32,FLEN) +NAN_BOXED(30718,32,FLEN) +NAN_BOXED(30718,32,FLEN) +NAN_BOXED(30718,32,FLEN) +NAN_BOXED(30719,32,FLEN) +test_dataset_1: +NAN_BOXED(30719,32,FLEN) +NAN_BOXED(30719,32,FLEN) +NAN_BOXED(30719,32,FLEN) +NAN_BOXED(30719,32,FLEN) +NAN_BOXED(30720,32,FLEN) +NAN_BOXED(30720,32,FLEN) +NAN_BOXED(30720,32,FLEN) +NAN_BOXED(30720,32,FLEN) +NAN_BOXED(30720,32,FLEN) +NAN_BOXED(30721,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(30721,32,FLEN) +NAN_BOXED(30721,32,FLEN) +NAN_BOXED(30721,32,FLEN) +NAN_BOXED(30722,32,FLEN) +NAN_BOXED(30722,32,FLEN) +test_dataset_2: +NAN_BOXED(30722,16,FLEN) +NAN_BOXED(30722,16,FLEN) +NAN_BOXED(30722,16,FLEN) +NAN_BOXED(30723,16,FLEN) +NAN_BOXED(30723,16,FLEN) +NAN_BOXED(30723,16,FLEN) +NAN_BOXED(30723,16,FLEN) +NAN_BOXED(30723,16,FLEN) +NAN_BOXED(30724,16,FLEN) +NAN_BOXED(30724,16,FLEN) +NAN_BOXED(30724,16,FLEN) +NAN_BOXED(30724,16,FLEN) +NAN_BOXED(30724,16,FLEN) +NAN_BOXED(30721,16,FLEN) +NAN_BOXED(30721,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 34*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x8_0: + .fill 60*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/Zhinx/src/fcvt.lu.h_b24-01.S b/riscv-test-suite/rv64i_m/Zhinx/src/fcvt.lu.h_b24-01.S new file mode 100644 index 000000000..aefeb10d9 --- /dev/null +++ b/riscv-test-suite/rv64i_m/Zhinx/src/fcvt.lu.h_b24-01.S @@ -0,0 +1,848 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 04:44:02 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64Zhinx/rv64h_fcvt.lu.h.cgf \ + \ +// -- xlen 64 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.lu.h instruction of the RISC-V RV64_Zfinx_Zhinx extension for the fcvt.lu.h_b24 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fcvt.lu.h_b24) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x9,test_dataset_0) +RVTEST_SIGBASE(x3,signature_x3_1) + +inst_0:// rs1 != rd, rs1==x0, rd==x28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x0; dest:x28; op1val:0x0; valaddr_reg:x9; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x28, x0, dyn, 0, 0, x9, 0*FLEN/8, x12, x3, x4,FLREG) + +inst_1:// rs1 == rd, rs1==x14, rd==x14,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x14; dest:x14; op1val:0xf0; valaddr_reg:x9; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.lu.h, x14, x14, dyn, 32, 0, x9, 1*FLEN/8, x12, x3, x4,FLREG) + +inst_2:// rs1==x31, rd==x7,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x31; dest:x7; op1val:0xf0; valaddr_reg:x9; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.lu.h, x7, x31, dyn, 64, 0, x9, 2*FLEN/8, x12, x3, x4,FLREG) + +inst_3:// rs1==x19, rd==x1,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x19; dest:x1; op1val:0xf0; valaddr_reg:x9; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.lu.h, x1, x19, dyn, 96, 0, x9, 3*FLEN/8, x12, x3, x4,FLREG) + +inst_4:// rs1==x8, rd==x18,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x8; dest:x18; op1val:0xf0; valaddr_reg:x9; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.lu.h, x18, x8, dyn, 128, 0, x9, 4*FLEN/8, x12, x3, x4,FLREG) + +inst_5:// rs1==x25, rd==x11,fs1 == 1 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x25; dest:x11; op1val:0xa11e; valaddr_reg:x9; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x11, x25, dyn, 0, 0, x9, 5*FLEN/8, x12, x3, x4,FLREG) + +inst_6:// rs1==x6, rd==x16,fs1 == 1 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x6; dest:x16; op1val:0xa11e; valaddr_reg:x9; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.lu.h, x16, x6, dyn, 32, 0, x9, 6*FLEN/8, x12, x3, x4,FLREG) + +inst_7:// rs1==x17, rd==x21,fs1 == 1 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x17; dest:x21; op1val:0xa11e; valaddr_reg:x9; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.lu.h, x21, x17, dyn, 64, 0, x9, 7*FLEN/8, x12, x3, x4,FLREG) + +inst_8:// rs1==x30, rd==x6,fs1 == 1 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x6; op1val:0xa11e; valaddr_reg:x9; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.lu.h, x6, x30, dyn, 96, 0, x9, 8*FLEN/8, x12, x3, x4,FLREG) + +inst_9:// rs1==x1, rd==x10,fs1 == 1 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x1; dest:x10; op1val:0xa11e; valaddr_reg:x9; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.lu.h, x10, x1, dyn, 128, 0, x9, 9*FLEN/8, x12, x3, x4,FLREG) + +inst_10:// rs1==x15, rd==x23,fs1 == 0 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x15; dest:x23; op1val:0x3beb; valaddr_reg:x9; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x23, x15, dyn, 0, 0, x9, 10*FLEN/8, x12, x3, x4,FLREG) + +inst_11:// rs1==x29, rd==x26,fs1 == 0 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x29; dest:x26; op1val:0x3beb; valaddr_reg:x9; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.lu.h, x26, x29, dyn, 32, 0, x9, 11*FLEN/8, x12, x3, x4,FLREG) + +inst_12:// rs1==x13, rd==x0,fs1 == 0 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x13; dest:x0; op1val:0x3beb; valaddr_reg:x9; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.lu.h, x0, x13, dyn, 64, 0, x9, 12*FLEN/8, x12, x3, x4,FLREG) + +inst_13:// rs1==x18, rd==x5,fs1 == 0 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x18; dest:x5; op1val:0x3beb; valaddr_reg:x9; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.lu.h, x5, x18, dyn, 96, 0, x9, 13*FLEN/8, x12, x3, x4,FLREG) + +inst_14:// rs1==x2, rd==x15,fs1 == 0 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x2; dest:x15; op1val:0x3beb; valaddr_reg:x9; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.lu.h, x15, x2, dyn, 128, 0, x9, 14*FLEN/8, x12, x3, x4,FLREG) + +inst_15:// rs1==x16, rd==x2,fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x16; dest:x2; op1val:0x2e66; valaddr_reg:x9; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x2, x16, dyn, 0, 0, x9, 15*FLEN/8, x12, x3, x4,FLREG) + +inst_16:// rs1==x27, rd==x30,fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x27; dest:x30; op1val:0x2e66; valaddr_reg:x9; +val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.lu.h, x30, x27, dyn, 32, 0, x9, 16*FLEN/8, x12, x3, x4,FLREG) +RVTEST_VALBASEUPD(x6,test_dataset_1) + +inst_17:// rs1==x10, rd==x12,fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x10; dest:x12; op1val:0x2e66; valaddr_reg:x6; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.lu.h, x12, x10, dyn, 64, 0, x6, 0*FLEN/8, x15, x3, x4,FLREG) + +inst_18:// rs1==x20, rd==x22,fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x20; dest:x22; op1val:0x2e66; valaddr_reg:x6; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x4; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.lu.h, x22, x20, dyn, 96, 0, x6, 1*FLEN/8, x15, x3, x4,FLREG) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_19:// rs1==x21, rd==x8,fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x21; dest:x8; op1val:0x2e66; valaddr_reg:x6; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.lu.h, x8, x21, dyn, 128, 0, x6, 2*FLEN/8, x15, x1, x2,FLREG) + +inst_20:// rs1==x4, rd==x25,fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x4; dest:x25; op1val:0xaf0a; valaddr_reg:x6; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x25, x4, dyn, 0, 0, x6, 3*FLEN/8, x15, x1, x2,FLREG) + +inst_21:// rs1==x7, rd==x13,fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x7; dest:x13; op1val:0xaf0a; valaddr_reg:x6; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.lu.h, x13, x7, dyn, 32, 0, x6, 4*FLEN/8, x15, x1, x2,FLREG) + +inst_22:// rs1==x9, rd==x4,fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x9; dest:x4; op1val:0xaf0a; valaddr_reg:x6; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.lu.h, x4, x9, dyn, 64, 0, x6, 5*FLEN/8, x15, x1, x2,FLREG) + +inst_23:// rs1==x24, rd==x19,fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x24; dest:x19; op1val:0xaf0a; valaddr_reg:x6; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.lu.h, x19, x24, dyn, 96, 0, x6, 6*FLEN/8, x15, x1, x2,FLREG) + +inst_24:// rs1==x11, rd==x9,fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x11; dest:x9; op1val:0xaf0a; valaddr_reg:x6; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.lu.h, x9, x11, dyn, 128, 0, x6, 7*FLEN/8, x15, x1, x2,FLREG) + +inst_25:// rs1==x28, rd==x24,fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x28; dest:x24; op1val:0x3c66; valaddr_reg:x6; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x24, x28, dyn, 0, 0, x6, 8*FLEN/8, x15, x1, x2,FLREG) + +inst_26:// rs1==x5, rd==x27,fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x5; dest:x27; op1val:0x3c66; valaddr_reg:x6; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.lu.h, x27, x5, dyn, 32, 0, x6, 9*FLEN/8, x15, x1, x2,FLREG) + +inst_27:// rs1==x12, rd==x31,fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x12; dest:x31; op1val:0x3c66; valaddr_reg:x6; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.lu.h, x31, x12, dyn, 64, 0, x6, 10*FLEN/8, x15, x1, x2,FLREG) + +inst_28:// rs1==x26, rd==x17,fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x26; dest:x17; op1val:0x3c66; valaddr_reg:x6; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.lu.h, x17, x26, dyn, 96, 0, x6, 11*FLEN/8, x15, x1, x2,FLREG) + +inst_29:// rs1==x23, rd==x29,fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x23; dest:x29; op1val:0x3c66; valaddr_reg:x6; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.lu.h, x29, x23, dyn, 128, 0, x6, 12*FLEN/8, x15, x1, x2,FLREG) + +inst_30:// rs1==x22, rd==x20,fs1 == 1 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x22; dest:x20; op1val:0xbb1e; valaddr_reg:x6; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x20, x22, dyn, 0, 0, x6, 13*FLEN/8, x15, x1, x2,FLREG) + +inst_31:// rs1==x3,fs1 == 1 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x3; dest:x14; op1val:0xbb1e; valaddr_reg:x6; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.lu.h, x14, x3, dyn, 32, 0, x6, 14*FLEN/8, x15, x1, x2,FLREG) +RVTEST_VALBASEUPD(x4,test_dataset_2) + +inst_32:// rd==x3,fs1 == 1 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x19; dest:x3; op1val:0xbb1e; valaddr_reg:x4; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.lu.h, x3, x19, dyn, 64, 0, x4, 0*FLEN/8, x5, x1, x2,FLREG) + +inst_33:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xbb1e; valaddr_reg:x4; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 96, 0, x4, 1*FLEN/8, x5, x1, x2,FLREG) + +inst_34:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xbb1e; valaddr_reg:x4; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 128, 0, x4, 2*FLEN/8, x5, x1, x2,FLREG) + +inst_35:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xbc00; valaddr_reg:x4; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x4, 3*FLEN/8, x5, x1, x2,FLREG) + +inst_36:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xbc00; valaddr_reg:x4; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 32, 0, x4, 4*FLEN/8, x5, x1, x2,FLREG) + +inst_37:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xbc00; valaddr_reg:x4; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 64, 0, x4, 5*FLEN/8, x5, x1, x2,FLREG) + +inst_38:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xbc00; valaddr_reg:x4; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 96, 0, x4, 6*FLEN/8, x5, x1, x2,FLREG) + +inst_39:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xbc00; valaddr_reg:x4; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 128, 0, x4, 7*FLEN/8, x5, x1, x2,FLREG) + +inst_40:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x3c00; valaddr_reg:x4; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x4, 8*FLEN/8, x5, x1, x2,FLREG) + +inst_41:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x3c00; valaddr_reg:x4; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 32, 0, x4, 9*FLEN/8, x5, x1, x2,FLREG) + +inst_42:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x3c00; valaddr_reg:x4; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 64, 0, x4, 10*FLEN/8, x5, x1, x2,FLREG) + +inst_43:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x3c00; valaddr_reg:x4; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 96, 0, x4, 11*FLEN/8, x5, x1, x2,FLREG) + +inst_44:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x3c00; valaddr_reg:x4; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 128, 0, x4, 12*FLEN/8, x5, x1, x2,FLREG) + +inst_45:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xbb33; valaddr_reg:x4; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x4, 13*FLEN/8, x5, x1, x2,FLREG) + +inst_46:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xbb33; valaddr_reg:x4; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 32, 0, x4, 14*FLEN/8, x5, x1, x2,FLREG) + +inst_47:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xbb33; valaddr_reg:x4; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 64, 0, x4, 15*FLEN/8, x5, x1, x2,FLREG) + +inst_48:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xbb33; valaddr_reg:x4; +val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 96, 0, x4, 16*FLEN/8, x5, x1, x2,FLREG) + +inst_49:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xbb33; valaddr_reg:x4; +val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 128, 0, x4, 17*FLEN/8, x5, x1, x2,FLREG) + +inst_50:// fs1 == 1 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xae66; valaddr_reg:x4; +val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x4, 18*FLEN/8, x5, x1, x2,FLREG) + +inst_51:// fs1 == 1 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xae66; valaddr_reg:x4; +val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 32, 0, x4, 19*FLEN/8, x5, x1, x2,FLREG) + +inst_52:// fs1 == 1 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xae66; valaddr_reg:x4; +val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 64, 0, x4, 20*FLEN/8, x5, x1, x2,FLREG) + +inst_53:// fs1 == 1 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xae66; valaddr_reg:x4; +val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 96, 0, x4, 21*FLEN/8, x5, x1, x2,FLREG) + +inst_54:// fs1 == 1 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xae66; valaddr_reg:x4; +val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 128, 0, x4, 22*FLEN/8, x5, x1, x2,FLREG) + +inst_55:// fs1 == 0 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x211e; valaddr_reg:x4; +val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x4, 23*FLEN/8, x5, x1, x2,FLREG) + +inst_56:// fs1 == 0 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x211e; valaddr_reg:x4; +val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 32, 0, x4, 24*FLEN/8, x5, x1, x2,FLREG) + +inst_57:// fs1 == 0 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x211e; valaddr_reg:x4; +val_offset:25*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 64, 0, x4, 25*FLEN/8, x5, x1, x2,FLREG) + +inst_58:// fs1 == 0 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x211e; valaddr_reg:x4; +val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 96, 0, x4, 26*FLEN/8, x5, x1, x2,FLREG) + +inst_59:// fs1 == 0 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x211e; valaddr_reg:x4; +val_offset:27*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 128, 0, x4, 27*FLEN/8, x5, x1, x2,FLREG) + +inst_60:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x3c0a; valaddr_reg:x4; +val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x4, 28*FLEN/8, x5, x1, x2,FLREG) + +inst_61:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x3c0a; valaddr_reg:x4; +val_offset:29*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 32, 0, x4, 29*FLEN/8, x5, x1, x2,FLREG) + +inst_62:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x3c0a; valaddr_reg:x4; +val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 64, 0, x4, 30*FLEN/8, x5, x1, x2,FLREG) + +inst_63:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x3c0a; valaddr_reg:x4; +val_offset:31*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 96, 0, x4, 31*FLEN/8, x5, x1, x2,FLREG) + +inst_64:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x3c0a; valaddr_reg:x4; +val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 128, 0, x4, 32*FLEN/8, x5, x1, x2,FLREG) + +inst_65:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xbc0a; valaddr_reg:x4; +val_offset:33*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x4, 33*FLEN/8, x5, x1, x2,FLREG) + +inst_66:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xbc0a; valaddr_reg:x4; +val_offset:34*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 32, 0, x4, 34*FLEN/8, x5, x1, x2,FLREG) + +inst_67:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xbc0a; valaddr_reg:x4; +val_offset:35*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 64, 0, x4, 35*FLEN/8, x5, x1, x2,FLREG) + +inst_68:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xbc0a; valaddr_reg:x4; +val_offset:36*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 96, 0, x4, 36*FLEN/8, x5, x1, x2,FLREG) + +inst_69:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xbc0a; valaddr_reg:x4; +val_offset:37*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 128, 0, x4, 37*FLEN/8, x5, x1, x2,FLREG) + +inst_70:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x3c70; valaddr_reg:x4; +val_offset:38*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x4, 38*FLEN/8, x5, x1, x2,FLREG) + +inst_71:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x3c70; valaddr_reg:x4; +val_offset:39*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 32, 0, x4, 39*FLEN/8, x5, x1, x2,FLREG) + +inst_72:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x3c70; valaddr_reg:x4; +val_offset:40*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 64, 0, x4, 40*FLEN/8, x5, x1, x2,FLREG) + +inst_73:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x3c70; valaddr_reg:x4; +val_offset:41*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 96, 0, x4, 41*FLEN/8, x5, x1, x2,FLREG) + +inst_74:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x3c70; valaddr_reg:x4; +val_offset:42*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 128, 0, x4, 42*FLEN/8, x5, x1, x2,FLREG) + +inst_75:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xbbeb; valaddr_reg:x4; +val_offset:43*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x4, 43*FLEN/8, x5, x1, x2,FLREG) + +inst_76:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xbbeb; valaddr_reg:x4; +val_offset:44*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 32, 0, x4, 44*FLEN/8, x5, x1, x2,FLREG) + +inst_77:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xbbeb; valaddr_reg:x4; +val_offset:45*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 64, 0, x4, 45*FLEN/8, x5, x1, x2,FLREG) + +inst_78:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xbbeb; valaddr_reg:x4; +val_offset:46*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 96, 0, x4, 46*FLEN/8, x5, x1, x2,FLREG) + +inst_79:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xbbeb; valaddr_reg:x4; +val_offset:47*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 128, 0, x4, 47*FLEN/8, x5, x1, x2,FLREG) + +inst_80:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xbc70; valaddr_reg:x4; +val_offset:48*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x4, 48*FLEN/8, x5, x1, x2,FLREG) + +inst_81:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xbc70; valaddr_reg:x4; +val_offset:49*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 32, 0, x4, 49*FLEN/8, x5, x1, x2,FLREG) + +inst_82:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xbc70; valaddr_reg:x4; +val_offset:50*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 64, 0, x4, 50*FLEN/8, x5, x1, x2,FLREG) + +inst_83:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xbc70; valaddr_reg:x4; +val_offset:51*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 96, 0, x4, 51*FLEN/8, x5, x1, x2,FLREG) + +inst_84:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xbc70; valaddr_reg:x4; +val_offset:52*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 128, 0, x4, 52*FLEN/8, x5, x1, x2,FLREG) + +inst_85:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x3b33; valaddr_reg:x4; +val_offset:53*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x4, 53*FLEN/8, x5, x1, x2,FLREG) + +inst_86:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x3b33; valaddr_reg:x4; +val_offset:54*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 32, 0, x4, 54*FLEN/8, x5, x1, x2,FLREG) + +inst_87:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x3b33; valaddr_reg:x4; +val_offset:55*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 64, 0, x4, 55*FLEN/8, x5, x1, x2,FLREG) + +inst_88:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x3b33; valaddr_reg:x4; +val_offset:56*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 96, 0, x4, 56*FLEN/8, x5, x1, x2,FLREG) + +inst_89:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x3b33; valaddr_reg:x4; +val_offset:57*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 128, 0, x4, 57*FLEN/8, x5, x1, x2,FLREG) + +inst_90:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x3b1e; valaddr_reg:x4; +val_offset:58*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x4, 58*FLEN/8, x5, x1, x2,FLREG) + +inst_91:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x3b1e; valaddr_reg:x4; +val_offset:59*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 32, 0, x4, 59*FLEN/8, x5, x1, x2,FLREG) + +inst_92:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x3b1e; valaddr_reg:x4; +val_offset:60*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 64, 0, x4, 60*FLEN/8, x5, x1, x2,FLREG) + +inst_93:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x3b1e; valaddr_reg:x4; +val_offset:61*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 96, 0, x4, 61*FLEN/8, x5, x1, x2,FLREG) + +inst_94:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x3b1e; valaddr_reg:x4; +val_offset:62*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 128, 0, x4, 62*FLEN/8, x5, x1, x2,FLREG) + +inst_95:// fs1 == 0 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x2f0a; valaddr_reg:x4; +val_offset:63*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x4, 63*FLEN/8, x5, x1, x2,FLREG) + +inst_96:// fs1 == 0 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x2f0a; valaddr_reg:x4; +val_offset:64*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 32, 0, x4, 64*FLEN/8, x5, x1, x2,FLREG) + +inst_97:// fs1 == 0 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x2f0a; valaddr_reg:x4; +val_offset:65*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 64, 0, x4, 65*FLEN/8, x5, x1, x2,FLREG) + +inst_98:// fs1 == 0 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x2f0a; valaddr_reg:x4; +val_offset:66*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 96, 0, x4, 66*FLEN/8, x5, x1, x2,FLREG) + +inst_99:// fs1 == 0 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x2f0a; valaddr_reg:x4; +val_offset:67*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 128, 0, x4, 67*FLEN/8, x5, x1, x2,FLREG) + +inst_100:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xbc66; valaddr_reg:x4; +val_offset:68*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x4, 68*FLEN/8, x5, x1, x2,FLREG) + +inst_101:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xbc66; valaddr_reg:x4; +val_offset:69*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 32, 0, x4, 69*FLEN/8, x5, x1, x2,FLREG) + +inst_102:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xbc66; valaddr_reg:x4; +val_offset:70*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 64, 0, x4, 70*FLEN/8, x5, x1, x2,FLREG) + +inst_103:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xbc66; valaddr_reg:x4; +val_offset:71*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 96, 0, x4, 71*FLEN/8, x5, x1, x2,FLREG) + +inst_104:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xbc66; valaddr_reg:x4; +val_offset:72*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 128, 0, x4, 72*FLEN/8, x5, x1, x2,FLREG) + +inst_105:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xf0; valaddr_reg:x4; +val_offset:73*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x4, 73*FLEN/8, x5, x1, x2,FLREG) + +inst_106:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x3beb; valaddr_reg:x4; +val_offset:74*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 64, 0, x4, 74*FLEN/8, x5, x1, x2,FLREG) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(240,32,FLEN) +NAN_BOXED(240,32,FLEN) +NAN_BOXED(240,32,FLEN) +NAN_BOXED(240,32,FLEN) +NAN_BOXED(41246,16,FLEN) +NAN_BOXED(41246,16,FLEN) +NAN_BOXED(41246,16,FLEN) +NAN_BOXED(41246,16,FLEN) +NAN_BOXED(41246,16,FLEN) +NAN_BOXED(15339,32,FLEN) +NAN_BOXED(15339,32,FLEN) +NAN_BOXED(15339,32,FLEN) +NAN_BOXED(15339,32,FLEN) +NAN_BOXED(15339,32,FLEN) +NAN_BOXED(11878,32,FLEN) +NAN_BOXED(11878,32,FLEN) +test_dataset_1: +NAN_BOXED(11878,32,FLEN) +NAN_BOXED(11878,32,FLEN) +NAN_BOXED(11878,32,FLEN) +NAN_BOXED(44810,16,FLEN) +NAN_BOXED(44810,16,FLEN) +NAN_BOXED(44810,16,FLEN) +NAN_BOXED(44810,16,FLEN) +NAN_BOXED(44810,16,FLEN) +NAN_BOXED(15462,32,FLEN) +NAN_BOXED(15462,32,FLEN) +NAN_BOXED(15462,32,FLEN) +NAN_BOXED(15462,32,FLEN) +NAN_BOXED(15462,32,FLEN) +NAN_BOXED(47902,16,FLEN) +NAN_BOXED(47902,16,FLEN) +test_dataset_2: +NAN_BOXED(47902,16,FLEN) +NAN_BOXED(47902,16,FLEN) +NAN_BOXED(47902,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(47923,16,FLEN) +NAN_BOXED(47923,16,FLEN) +NAN_BOXED(47923,16,FLEN) +NAN_BOXED(47923,16,FLEN) +NAN_BOXED(47923,16,FLEN) +NAN_BOXED(44646,16,FLEN) +NAN_BOXED(44646,16,FLEN) +NAN_BOXED(44646,16,FLEN) +NAN_BOXED(44646,16,FLEN) +NAN_BOXED(44646,16,FLEN) +NAN_BOXED(8478,16,FLEN) +NAN_BOXED(8478,16,FLEN) +NAN_BOXED(8478,16,FLEN) +NAN_BOXED(8478,16,FLEN) +NAN_BOXED(8478,16,FLEN) +NAN_BOXED(15370,16,FLEN) +NAN_BOXED(15370,16,FLEN) +NAN_BOXED(15370,16,FLEN) +NAN_BOXED(15370,16,FLEN) +NAN_BOXED(15370,16,FLEN) +NAN_BOXED(48138,16,FLEN) +NAN_BOXED(48138,16,FLEN) +NAN_BOXED(48138,16,FLEN) +NAN_BOXED(48138,16,FLEN) +NAN_BOXED(48138,16,FLEN) +NAN_BOXED(15472,16,FLEN) +NAN_BOXED(15472,16,FLEN) +NAN_BOXED(15472,16,FLEN) +NAN_BOXED(15472,16,FLEN) +NAN_BOXED(15472,16,FLEN) +NAN_BOXED(48107,16,FLEN) +NAN_BOXED(48107,16,FLEN) +NAN_BOXED(48107,16,FLEN) +NAN_BOXED(48107,16,FLEN) +NAN_BOXED(48107,16,FLEN) +NAN_BOXED(48240,16,FLEN) +NAN_BOXED(48240,16,FLEN) +NAN_BOXED(48240,16,FLEN) +NAN_BOXED(48240,16,FLEN) +NAN_BOXED(48240,16,FLEN) +NAN_BOXED(15155,16,FLEN) +NAN_BOXED(15155,16,FLEN) +NAN_BOXED(15155,16,FLEN) +NAN_BOXED(15155,16,FLEN) +NAN_BOXED(15155,16,FLEN) +NAN_BOXED(15134,16,FLEN) +NAN_BOXED(15134,16,FLEN) +NAN_BOXED(15134,16,FLEN) +NAN_BOXED(15134,16,FLEN) +NAN_BOXED(15134,16,FLEN) +NAN_BOXED(12042,16,FLEN) +NAN_BOXED(12042,16,FLEN) +NAN_BOXED(12042,16,FLEN) +NAN_BOXED(12042,16,FLEN) +NAN_BOXED(12042,16,FLEN) +NAN_BOXED(48230,16,FLEN) +NAN_BOXED(48230,16,FLEN) +NAN_BOXED(48230,16,FLEN) +NAN_BOXED(48230,16,FLEN) +NAN_BOXED(48230,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(15339,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x3_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x3_1: + .fill 38*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_0: + .fill 176*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/Zhinx/src/fcvt.lu.h_b27-01.S b/riscv-test-suite/rv64i_m/Zhinx/src/fcvt.lu.h_b27-01.S new file mode 100644 index 000000000..823b1791f --- /dev/null +++ b/riscv-test-suite/rv64i_m/Zhinx/src/fcvt.lu.h_b27-01.S @@ -0,0 +1,321 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 04:44:02 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64Zhinx/rv64h_fcvt.lu.h.cgf \ + \ +// -- xlen 64 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.lu.h instruction of the RISC-V RV64_Zfinx_Zhinx extension for the fcvt.lu.h_b27 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fcvt.lu.h_b27) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x11,test_dataset_0) +RVTEST_SIGBASE(x5,signature_x5_1) + +inst_0:// rs1 != rd, rs1==x2, rd==x15,fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x2; dest:x15; op1val:0x7c01; valaddr_reg:x11; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x8; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x15, x2, dyn, 0, 0, x11, 0*FLEN/8, x20, x5, x8,FLREG) + +inst_1:// rs1 == rd, rs1==x31, rd==x31,fs1 == 1 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x31; dest:x31; op1val:0xfc01; valaddr_reg:x11; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x8; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x31, dyn, 0, 0, x11, 1*FLEN/8, x20, x5, x8,FLREG) + +inst_2:// rs1==x21, rd==x14,fs1 == 0 and fe1 == 0x1f and fm1 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x21; dest:x14; op1val:0x7d55; valaddr_reg:x11; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x8; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x14, x21, dyn, 0, 0, x11, 2*FLEN/8, x20, x5, x8,FLREG) + +inst_3:// rs1==x14, rd==x28,fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x14; dest:x28; op1val:0xfd55; valaddr_reg:x11; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x8; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x28, x14, dyn, 0, 0, x11, 3*FLEN/8, x20, x5, x8,FLREG) + +inst_4:// rs1==x6, rd==x27,fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x6; dest:x27; op1val:0x7e01; valaddr_reg:x11; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x8; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x27, x6, dyn, 0, 0, x11, 4*FLEN/8, x20, x5, x8,FLREG) + +inst_5:// rs1==x7, rd==x4,fs1 == 1 and fe1 == 0x1f and fm1 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x7; dest:x4; op1val:0xfe01; valaddr_reg:x11; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x8; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x4, x7, dyn, 0, 0, x11, 5*FLEN/8, x20, x5, x8,FLREG) + +inst_6:// rs1==x19, rd==x1,fs1 == 0 and fe1 == 0x1f and fm1 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x19; dest:x1; op1val:0x7e55; valaddr_reg:x11; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x8; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x1, x19, dyn, 0, 0, x11, 6*FLEN/8, x20, x5, x8,FLREG) + +inst_7:// rs1==x4, rd==x7,fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x4; dest:x7; op1val:0xfe55; valaddr_reg:x11; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x8; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x7, x4, dyn, 0, 0, x11, 7*FLEN/8, x20, x5, x8,FLREG) + +inst_8:// rs1==x24, rd==x10, +/* opcode: fcvt.lu.h ; op1:x24; dest:x10; op1val:0x0; valaddr_reg:x11; +val_offset:8*FLEN/8; rmval:rne; correctval:??; testreg:x8; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x10, x24, rne, 0, 0, x11, 8*FLEN/8, x20, x5, x8,FLREG) + +inst_9:// rs1==x13, rd==x19, +/* opcode: fcvt.lu.h ; op1:x13; dest:x19; op1val:0x0; valaddr_reg:x11; +val_offset:9*FLEN/8; rmval:rne; correctval:??; testreg:x8; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x19, x13, rne, 0, 0, x11, 9*FLEN/8, x20, x5, x8,FLREG) + +inst_10:// rs1==x16, rd==x13, +/* opcode: fcvt.lu.h ; op1:x16; dest:x13; op1val:0x0; valaddr_reg:x11; +val_offset:10*FLEN/8; rmval:rne; correctval:??; testreg:x8; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x13, x16, rne, 0, 0, x11, 10*FLEN/8, x20, x5, x8,FLREG) + +inst_11:// rs1==x28, rd==x6, +/* opcode: fcvt.lu.h ; op1:x28; dest:x6; op1val:0x0; valaddr_reg:x11; +val_offset:11*FLEN/8; rmval:rne; correctval:??; testreg:x8; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x6, x28, rne, 0, 0, x11, 11*FLEN/8, x20, x5, x8,FLREG) + +inst_12:// rs1==x9, rd==x30, +/* opcode: fcvt.lu.h ; op1:x9; dest:x30; op1val:0x0; valaddr_reg:x11; +val_offset:12*FLEN/8; rmval:rne; correctval:??; testreg:x8; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x30, x9, rne, 0, 0, x11, 12*FLEN/8, x20, x5, x8,FLREG) + +inst_13:// rs1==x17, rd==x12, +/* opcode: fcvt.lu.h ; op1:x17; dest:x12; op1val:0x0; valaddr_reg:x11; +val_offset:13*FLEN/8; rmval:rne; correctval:??; testreg:x8; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x12, x17, rne, 0, 0, x11, 13*FLEN/8, x20, x5, x8,FLREG) + +inst_14:// rs1==x29, rd==x3, +/* opcode: fcvt.lu.h ; op1:x29; dest:x3; op1val:0x0; valaddr_reg:x11; +val_offset:14*FLEN/8; rmval:rne; correctval:??; testreg:x8; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x3, x29, rne, 0, 0, x11, 14*FLEN/8, x20, x5, x8,FLREG) + +inst_15:// rs1==x1, rd==x26, +/* opcode: fcvt.lu.h ; op1:x1; dest:x26; op1val:0x0; valaddr_reg:x11; +val_offset:15*FLEN/8; rmval:rne; correctval:??; testreg:x8; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x26, x1, rne, 0, 0, x11, 15*FLEN/8, x20, x5, x8,FLREG) + +inst_16:// rs1==x12, rd==x21, +/* opcode: fcvt.lu.h ; op1:x12; dest:x21; op1val:0x0; valaddr_reg:x11; +val_offset:16*FLEN/8; rmval:rne; correctval:??; testreg:x8; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x21, x12, rne, 0, 0, x11, 16*FLEN/8, x20, x5, x8,FLREG) + +inst_17:// rs1==x25, rd==x18, +/* opcode: fcvt.lu.h ; op1:x25; dest:x18; op1val:0x0; valaddr_reg:x11; +val_offset:17*FLEN/8; rmval:rne; correctval:??; testreg:x8; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x18, x25, rne, 0, 0, x11, 17*FLEN/8, x20, x5, x8,FLREG) +RVTEST_VALBASEUPD(x6,test_dataset_1) + +inst_18:// rs1==x18, rd==x25, +/* opcode: fcvt.lu.h ; op1:x18; dest:x25; op1val:0x0; valaddr_reg:x6; +val_offset:0*FLEN/8; rmval:rne; correctval:??; testreg:x8; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x25, x18, rne, 0, 0, x6, 0*FLEN/8, x7, x5, x8,FLREG) + +inst_19:// rs1==x20, rd==x23, +/* opcode: fcvt.lu.h ; op1:x20; dest:x23; op1val:0x0; valaddr_reg:x6; +val_offset:1*FLEN/8; rmval:rne; correctval:??; testreg:x8; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x23, x20, rne, 0, 0, x6, 1*FLEN/8, x7, x5, x8,FLREG) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_20:// rs1==x23, rd==x0, +/* opcode: fcvt.lu.h ; op1:x23; dest:x0; op1val:0x0; valaddr_reg:x6; +val_offset:2*FLEN/8; rmval:rne; correctval:??; testreg:x4; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x0, x23, rne, 0, 0, x6, 2*FLEN/8, x7, x1, x4,FLREG) + +inst_21:// rs1==x8, rd==x11, +/* opcode: fcvt.lu.h ; op1:x8; dest:x11; op1val:0x0; valaddr_reg:x6; +val_offset:3*FLEN/8; rmval:rne; correctval:??; testreg:x4; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x11, x8, rne, 0, 0, x6, 3*FLEN/8, x7, x1, x4,FLREG) + +inst_22:// rs1==x15, rd==x2, +/* opcode: fcvt.lu.h ; op1:x15; dest:x2; op1val:0x0; valaddr_reg:x6; +val_offset:4*FLEN/8; rmval:rne; correctval:??; testreg:x4; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x2, x15, rne, 0, 0, x6, 4*FLEN/8, x7, x1, x4,FLREG) + +inst_23:// rs1==x30, rd==x20, +/* opcode: fcvt.lu.h ; op1:x30; dest:x20; op1val:0x0; valaddr_reg:x6; +val_offset:5*FLEN/8; rmval:rne; correctval:??; testreg:x4; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x20, x30, rne, 0, 0, x6, 5*FLEN/8, x7, x1, x4,FLREG) + +inst_24:// rs1==x26, rd==x22, +/* opcode: fcvt.lu.h ; op1:x26; dest:x22; op1val:0x0; valaddr_reg:x6; +val_offset:6*FLEN/8; rmval:rne; correctval:??; testreg:x4; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x22, x26, rne, 0, 0, x6, 6*FLEN/8, x7, x1, x4,FLREG) + +inst_25:// rs1==x10, rd==x8, +/* opcode: fcvt.lu.h ; op1:x10; dest:x8; op1val:0x0; valaddr_reg:x6; +val_offset:7*FLEN/8; rmval:rne; correctval:??; testreg:x4; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x8, x10, rne, 0, 0, x6, 7*FLEN/8, x7, x1, x4,FLREG) + +inst_26:// rs1==x0, rd==x16, +/* opcode: fcvt.lu.h ; op1:x0; dest:x16; op1val:0x0; valaddr_reg:x6; +val_offset:8*FLEN/8; rmval:rne; correctval:??; testreg:x4; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x16, x0, rne, 0, 0, x6, 8*FLEN/8, x7, x1, x4,FLREG) + +inst_27:// rs1==x27, rd==x5, +/* opcode: fcvt.lu.h ; op1:x27; dest:x5; op1val:0x0; valaddr_reg:x6; +val_offset:9*FLEN/8; rmval:rne; correctval:??; testreg:x4; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x5, x27, rne, 0, 0, x6, 9*FLEN/8, x7, x1, x4,FLREG) + +inst_28:// rs1==x11, rd==x29, +/* opcode: fcvt.lu.h ; op1:x11; dest:x29; op1val:0x0; valaddr_reg:x6; +val_offset:10*FLEN/8; rmval:rne; correctval:??; testreg:x4; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x29, x11, rne, 0, 0, x6, 10*FLEN/8, x7, x1, x4,FLREG) + +inst_29:// rs1==x3, rd==x24, +/* opcode: fcvt.lu.h ; op1:x3; dest:x24; op1val:0x0; valaddr_reg:x6; +val_offset:11*FLEN/8; rmval:rne; correctval:??; testreg:x4; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x24, x3, rne, 0, 0, x6, 11*FLEN/8, x7, x1, x4,FLREG) + +inst_30:// rs1==x5, rd==x9, +/* opcode: fcvt.lu.h ; op1:x5; dest:x9; op1val:0x0; valaddr_reg:x6; +val_offset:12*FLEN/8; rmval:rne; correctval:??; testreg:x4; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x9, x5, rne, 0, 0, x6, 12*FLEN/8, x7, x1, x4,FLREG) + +inst_31:// rs1==x22, rd==x17, +/* opcode: fcvt.lu.h ; op1:x22; dest:x17; op1val:0x0; valaddr_reg:x6; +val_offset:13*FLEN/8; rmval:rne; correctval:??; testreg:x4; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x17, x22, rne, 0, 0, x6, 13*FLEN/8, x7, x1, x4,FLREG) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(31745,32,FLEN) +NAN_BOXED(64513,16,FLEN) +NAN_BOXED(32085,32,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32257,32,FLEN) +NAN_BOXED(65025,16,FLEN) +NAN_BOXED(32341,32,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +test_dataset_1: +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x5_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x5_1: + .fill 40*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_0: + .fill 24*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/Zhinx/src/fcvt.lu.h_b28-01.S b/riscv-test-suite/rv64i_m/Zhinx/src/fcvt.lu.h_b28-01.S new file mode 100644 index 000000000..e3c06f8f5 --- /dev/null +++ b/riscv-test-suite/rv64i_m/Zhinx/src/fcvt.lu.h_b28-01.S @@ -0,0 +1,335 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 04:44:02 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64Zhinx/rv64h_fcvt.lu.h.cgf \ + \ +// -- xlen 64 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.lu.h instruction of the RISC-V RV64_Zfinx_Zhinx extension for the fcvt.lu.h_b28 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fcvt.lu.h_b28) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x1,test_dataset_0) +RVTEST_SIGBASE(x2,signature_x2_1) + +inst_0:// rs1 != rd, rs1==x20, rd==x11,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x20; dest:x11; op1val:0x0; valaddr_reg:x1; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x19; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x11, x20, dyn, 0, 0, x1, 0*FLEN/8, x8, x2, x19,FLREG) + +inst_1:// rs1 == rd, rs1==x12, rd==x12,fs1 == 0 and fe1 == 0x0e and fm1 == 0x092 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x12; dest:x12; op1val:0x3892; valaddr_reg:x1; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x19; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x12, x12, dyn, 0, 0, x1, 1*FLEN/8, x8, x2, x19,FLREG) + +inst_2:// rs1==x26, rd==x21,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x26; dest:x21; op1val:0x3c00; valaddr_reg:x1; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x19; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x21, x26, dyn, 0, 0, x1, 2*FLEN/8, x8, x2, x19,FLREG) + +inst_3:// rs1==x29, rd==x25,fs1 == 0 and fe1 == 0x0f and fm1 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x29; dest:x25; op1val:0x3d00; valaddr_reg:x1; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x19; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x25, x29, dyn, 0, 0, x1, 3*FLEN/8, x8, x2, x19,FLREG) + +inst_4:// rs1==x10, rd==x6,fs1 == 0 and fe1 == 0x0f and fm1 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x10; dest:x6; op1val:0x3e00; valaddr_reg:x1; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x19; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x6, x10, dyn, 0, 0, x1, 4*FLEN/8, x8, x2, x19,FLREG) + +inst_5:// rs1==x18, rd==x28,fs1 == 0 and fe1 == 0x0f and fm1 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x18; dest:x28; op1val:0x3f00; valaddr_reg:x1; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x19; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x28, x18, dyn, 0, 0, x1, 5*FLEN/8, x8, x2, x19,FLREG) + +inst_6:// rs1==x0, rd==x22,fs1 == 0 and fe1 == 0x10 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x0; dest:x22; op1val:0x0; valaddr_reg:x1; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x19; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x22, x0, dyn, 0, 0, x1, 6*FLEN/8, x8, x2, x19,FLREG) + +inst_7:// rs1==x17, rd==x7,fs1 == 0 and fe1 == 0x10 and fm1 == 0x080 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x17; dest:x7; op1val:0x4080; valaddr_reg:x1; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x19; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x7, x17, dyn, 0, 0, x1, 7*FLEN/8, x8, x2, x19,FLREG) + +inst_8:// rs1==x9, rd==x23,fs1 == 0 and fe1 == 0x10 and fm1 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x9; dest:x23; op1val:0x4100; valaddr_reg:x1; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x19; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x23, x9, dyn, 0, 0, x1, 8*FLEN/8, x8, x2, x19,FLREG) + +inst_9:// rs1==x14, rd==x5,fs1 == 0 and fe1 == 0x10 and fm1 == 0x180 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x14; dest:x5; op1val:0x4180; valaddr_reg:x1; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x19; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x5, x14, dyn, 0, 0, x1, 9*FLEN/8, x8, x2, x19,FLREG) + +inst_10:// rs1==x13, rd==x20,fs1 == 0 and fe1 == 0x1c and fm1 == 0x2dc and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x13; dest:x20; op1val:0x72dc; valaddr_reg:x1; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x19; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x20, x13, dyn, 0, 0, x1, 10*FLEN/8, x8, x2, x19,FLREG) + +inst_11:// rs1==x22, rd==x18,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x22; dest:x18; op1val:0x77ff; valaddr_reg:x1; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x19; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x18, x22, dyn, 0, 0, x1, 11*FLEN/8, x8, x2, x19,FLREG) + +inst_12:// rs1==x3, rd==x10,fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x3; dest:x10; op1val:0x7c00; valaddr_reg:x1; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x19; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x10, x3, dyn, 0, 0, x1, 12*FLEN/8, x8, x2, x19,FLREG) + +inst_13:// rs1==x15, rd==x14,fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x15; dest:x14; op1val:0x7c01; valaddr_reg:x1; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x19; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x14, x15, dyn, 0, 0, x1, 13*FLEN/8, x8, x2, x19,FLREG) + +inst_14:// rs1==x23, rd==x3,fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x23; dest:x3; op1val:0x7e01; valaddr_reg:x1; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x19; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x3, x23, dyn, 0, 0, x1, 14*FLEN/8, x8, x2, x19,FLREG) + +inst_15:// rs1==x6, rd==x30,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x6; dest:x30; op1val:0x8000; valaddr_reg:x1; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x19; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x30, x6, dyn, 0, 0, x1, 15*FLEN/8, x8, x2, x19,FLREG) + +inst_16:// rs1==x7, rd==x4,fs1 == 1 and fe1 == 0x0d and fm1 == 0x2c0 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x7; dest:x4; op1val:0xb6c0; valaddr_reg:x1; +val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x19; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x4, x7, dyn, 0, 0, x1, 16*FLEN/8, x8, x2, x19,FLREG) + +inst_17:// rs1==x21, rd==x26,fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x21; dest:x26; op1val:0xbc00; valaddr_reg:x1; +val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x19; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x26, x21, dyn, 0, 0, x1, 17*FLEN/8, x8, x2, x19,FLREG) + +inst_18:// rs1==x30, rd==x16,fs1 == 1 and fe1 == 0x10 and fm1 == 0x180 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x16; op1val:0xc180; valaddr_reg:x1; +val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x19; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x16, x30, dyn, 0, 0, x1, 18*FLEN/8, x8, x2, x19,FLREG) +RVTEST_VALBASEUPD(x7,test_dataset_1) + +inst_19:// rs1==x25, rd==x15,fs1 == 1 and fe1 == 0x10 and fm1 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x25; dest:x15; op1val:0xc100; valaddr_reg:x7; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x19; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x15, x25, dyn, 0, 0, x7, 0*FLEN/8, x10, x2, x19,FLREG) + +inst_20:// rs1==x1, rd==x8,fs1 == 1 and fe1 == 0x10 and fm1 == 0x080 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x1; dest:x8; op1val:0xc080; valaddr_reg:x7; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x19; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x8, x1, dyn, 0, 0, x7, 1*FLEN/8, x10, x2, x19,FLREG) + +inst_21:// rs1==x24, rd==x27,fs1 == 1 and fe1 == 0x10 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x24; dest:x27; op1val:0xc000; valaddr_reg:x7; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x6; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x27, x24, dyn, 0, 0, x7, 2*FLEN/8, x10, x2, x6,FLREG) +RVTEST_SIGBASE(x3,signature_x3_0) + +inst_22:// rs1==x27, rd==x2,fs1 == 1 and fe1 == 0x0f and fm1 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x27; dest:x2; op1val:0xbf00; valaddr_reg:x7; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x6; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x2, x27, dyn, 0, 0, x7, 3*FLEN/8, x10, x3, x6,FLREG) + +inst_23:// rs1==x5, rd==x29,fs1 == 1 and fe1 == 0x0f and fm1 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x5; dest:x29; op1val:0xbe00; valaddr_reg:x7; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x6; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x29, x5, dyn, 0, 0, x7, 4*FLEN/8, x10, x3, x6,FLREG) + +inst_24:// rs1==x19, rd==x17,fs1 == 1 and fe1 == 0x0f and fm1 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x19; dest:x17; op1val:0xbd00; valaddr_reg:x7; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x6; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x17, x19, dyn, 0, 0, x7, 5*FLEN/8, x10, x3, x6,FLREG) + +inst_25:// rs1==x8, rd==x0,fs1 == 1 and fe1 == 0x1d and fm1 == 0x259 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x8; dest:x0; op1val:0xf659; valaddr_reg:x7; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x6; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x0, x8, dyn, 0, 0, x7, 6*FLEN/8, x10, x3, x6,FLREG) + +inst_26:// rs1==x28, rd==x1,fs1 == 1 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x28; dest:x1; op1val:0xf800; valaddr_reg:x7; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x6; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x1, x28, dyn, 0, 0, x7, 7*FLEN/8, x10, x3, x6,FLREG) + +inst_27:// rs1==x31, rd==x13,fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x31; dest:x13; op1val:0xfc00; valaddr_reg:x7; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x6; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x13, x31, dyn, 0, 0, x7, 8*FLEN/8, x10, x3, x6,FLREG) + +inst_28:// rs1==x11, rd==x24, +/* opcode: fcvt.lu.h ; op1:x11; dest:x24; op1val:0x0; valaddr_reg:x7; +val_offset:9*FLEN/8; rmval:rne; correctval:??; testreg:x6; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x24, x11, rne, 0, 0, x7, 9*FLEN/8, x10, x3, x6,FLREG) + +inst_29:// rs1==x4, rd==x9, +/* opcode: fcvt.lu.h ; op1:x4; dest:x9; op1val:0x0; valaddr_reg:x7; +val_offset:10*FLEN/8; rmval:rne; correctval:??; testreg:x6; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x9, x4, rne, 0, 0, x7, 10*FLEN/8, x10, x3, x6,FLREG) + +inst_30:// rs1==x16, rd==x19, +/* opcode: fcvt.lu.h ; op1:x16; dest:x19; op1val:0x0; valaddr_reg:x7; +val_offset:11*FLEN/8; rmval:rne; correctval:??; testreg:x6; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x19, x16, rne, 0, 0, x7, 11*FLEN/8, x10, x3, x6,FLREG) + +inst_31:// rs1==x2, rd==x31, +/* opcode: fcvt.lu.h ; op1:x2; dest:x31; op1val:0x0; valaddr_reg:x7; +val_offset:12*FLEN/8; rmval:rne; correctval:??; testreg:x6; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x2, rne, 0, 0, x7, 12*FLEN/8, x10, x3, x6,FLREG) + +inst_32:// fs1 == 0 and fe1 == 0x10 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x4000; valaddr_reg:x7; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x6; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x7, 13*FLEN/8, x10, x3, x6,FLREG) + +inst_33:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x259 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xf659; valaddr_reg:x7; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x6; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x7, 14*FLEN/8, x10, x3, x6,FLREG) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(14482,32,FLEN) +NAN_BOXED(15360,32,FLEN) +NAN_BOXED(15616,32,FLEN) +NAN_BOXED(15872,32,FLEN) +NAN_BOXED(16128,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(16512,32,FLEN) +NAN_BOXED(16640,32,FLEN) +NAN_BOXED(16768,32,FLEN) +NAN_BOXED(29404,32,FLEN) +NAN_BOXED(30719,32,FLEN) +NAN_BOXED(31744,32,FLEN) +NAN_BOXED(31745,32,FLEN) +NAN_BOXED(32257,32,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(46784,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(49536,16,FLEN) +test_dataset_1: +NAN_BOXED(49408,16,FLEN) +NAN_BOXED(49280,16,FLEN) +NAN_BOXED(49152,16,FLEN) +NAN_BOXED(48896,16,FLEN) +NAN_BOXED(48640,16,FLEN) +NAN_BOXED(48384,16,FLEN) +NAN_BOXED(63065,16,FLEN) +NAN_BOXED(63488,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(16384,16,FLEN) +NAN_BOXED(63065,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x2_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x2_1: + .fill 44*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x3_0: + .fill 24*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/Zhinx/src/fcvt.lu.h_b29-01.S b/riscv-test-suite/rv64i_m/Zhinx/src/fcvt.lu.h_b29-01.S new file mode 100644 index 000000000..c29ae6cb7 --- /dev/null +++ b/riscv-test-suite/rv64i_m/Zhinx/src/fcvt.lu.h_b29-01.S @@ -0,0 +1,673 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Sep 25 04:44:02 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64Zhinx/rv64h_fcvt.lu.h.cgf \ + \ +// -- xlen 64 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.lu.h instruction of the RISC-V RV64_Zfinx_Zhinx extension for the fcvt.lu.h_b29 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64I_Zfinx_Zhinx") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fcvt.lu.h_b29) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x6,test_dataset_0) +RVTEST_SIGBASE(x7,signature_x7_1) + +inst_0:// rs1 != rd, rs1==x25, rd==x4,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x25; dest:x4; op1val:0x3248; valaddr_reg:x6; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x4, x25, dyn, 0, 0, x6, 0*FLEN/8, x11, x7, x9,FLREG) + +inst_1:// rs1 == rd, rs1==x20, rd==x20,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x20; dest:x20; op1val:0x3248; valaddr_reg:x6; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.lu.h, x20, x20, dyn, 32, 0, x6, 1*FLEN/8, x11, x7, x9,FLREG) + +inst_2:// rs1==x3, rd==x23,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x3; dest:x23; op1val:0x3248; valaddr_reg:x6; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.lu.h, x23, x3, dyn, 64, 0, x6, 2*FLEN/8, x11, x7, x9,FLREG) + +inst_3:// rs1==x19, rd==x28,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x19; dest:x28; op1val:0x3248; valaddr_reg:x6; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.lu.h, x28, x19, dyn, 96, 0, x6, 3*FLEN/8, x11, x7, x9,FLREG) + +inst_4:// rs1==x1, rd==x24,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x1; dest:x24; op1val:0x3248; valaddr_reg:x6; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.lu.h, x24, x1, dyn, 128, 0, x6, 4*FLEN/8, x11, x7, x9,FLREG) + +inst_5:// rs1==x14, rd==x17,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x14; dest:x17; op1val:0x3249; valaddr_reg:x6; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x17, x14, dyn, 0, 0, x6, 5*FLEN/8, x11, x7, x9,FLREG) + +inst_6:// rs1==x5, rd==x8,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x5; dest:x8; op1val:0x3249; valaddr_reg:x6; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.lu.h, x8, x5, dyn, 32, 0, x6, 6*FLEN/8, x11, x7, x9,FLREG) + +inst_7:// rs1==x23, rd==x29,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x23; dest:x29; op1val:0x3249; valaddr_reg:x6; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.lu.h, x29, x23, dyn, 64, 0, x6, 7*FLEN/8, x11, x7, x9,FLREG) + +inst_8:// rs1==x28, rd==x10,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x28; dest:x10; op1val:0x3249; valaddr_reg:x6; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.lu.h, x10, x28, dyn, 96, 0, x6, 8*FLEN/8, x11, x7, x9,FLREG) + +inst_9:// rs1==x31, rd==x3,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x31; dest:x3; op1val:0x3249; valaddr_reg:x6; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.lu.h, x3, x31, dyn, 128, 0, x6, 9*FLEN/8, x11, x7, x9,FLREG) + +inst_10:// rs1==x21, rd==x13,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x21; dest:x13; op1val:0x324a; valaddr_reg:x6; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x13, x21, dyn, 0, 0, x6, 10*FLEN/8, x11, x7, x9,FLREG) + +inst_11:// rs1==x13, rd==x27,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x13; dest:x27; op1val:0x324a; valaddr_reg:x6; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.lu.h, x27, x13, dyn, 32, 0, x6, 11*FLEN/8, x11, x7, x9,FLREG) + +inst_12:// rs1==x12, rd==x26,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x12; dest:x26; op1val:0x324a; valaddr_reg:x6; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.lu.h, x26, x12, dyn, 64, 0, x6, 12*FLEN/8, x11, x7, x9,FLREG) + +inst_13:// rs1==x2, rd==x22,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x2; dest:x22; op1val:0x324a; valaddr_reg:x6; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.lu.h, x22, x2, dyn, 96, 0, x6, 13*FLEN/8, x11, x7, x9,FLREG) + +inst_14:// rs1==x18, rd==x25,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x18; dest:x25; op1val:0x324a; valaddr_reg:x6; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.lu.h, x25, x18, dyn, 128, 0, x6, 14*FLEN/8, x11, x7, x9,FLREG) +RVTEST_VALBASEUPD(x20,test_dataset_1) + +inst_15:// rs1==x6, rd==x16,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x6; dest:x16; op1val:0x324b; valaddr_reg:x20; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x9; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x16, x6, dyn, 0, 0, x20, 0*FLEN/8, x23, x7, x9,FLREG) + +inst_16:// rs1==x22, rd==x5,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x22; dest:x5; op1val:0x324b; valaddr_reg:x20; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.lu.h, x5, x22, dyn, 32, 0, x20, 1*FLEN/8, x23, x7, x13,FLREG) + +inst_17:// rs1==x8, rd==x15,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x8; dest:x15; op1val:0x324b; valaddr_reg:x20; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.lu.h, x15, x8, dyn, 64, 0, x20, 2*FLEN/8, x23, x7, x13,FLREG) +RVTEST_SIGBASE(x3,signature_x3_0) + +inst_18:// rs1==x16, rd==x0,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x16; dest:x0; op1val:0x324b; valaddr_reg:x20; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.lu.h, x0, x16, dyn, 96, 0, x20, 3*FLEN/8, x23, x3, x13,FLREG) + +inst_19:// rs1==x11, rd==x6,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x11; dest:x6; op1val:0x324b; valaddr_reg:x20; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.lu.h, x6, x11, dyn, 128, 0, x20, 4*FLEN/8, x23, x3, x13,FLREG) + +inst_20:// rs1==x24, rd==x21,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x24; dest:x21; op1val:0x324c; valaddr_reg:x20; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x21, x24, dyn, 0, 0, x20, 5*FLEN/8, x23, x3, x13,FLREG) + +inst_21:// rs1==x15, rd==x31,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x15; dest:x31; op1val:0x324c; valaddr_reg:x20; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.lu.h, x31, x15, dyn, 32, 0, x20, 6*FLEN/8, x23, x3, x13,FLREG) + +inst_22:// rs1==x27, rd==x30,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x27; dest:x30; op1val:0x324c; valaddr_reg:x20; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.lu.h, x30, x27, dyn, 64, 0, x20, 7*FLEN/8, x23, x3, x13,FLREG) + +inst_23:// rs1==x29, rd==x12,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x29; dest:x12; op1val:0x324c; valaddr_reg:x20; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.lu.h, x12, x29, dyn, 96, 0, x20, 8*FLEN/8, x23, x3, x13,FLREG) + +inst_24:// rs1==x30, rd==x18,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x18; op1val:0x324c; valaddr_reg:x20; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.lu.h, x18, x30, dyn, 128, 0, x20, 9*FLEN/8, x23, x3, x13,FLREG) + +inst_25:// rs1==x7, rd==x1,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x7; dest:x1; op1val:0x324d; valaddr_reg:x20; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x1, x7, dyn, 0, 0, x20, 10*FLEN/8, x23, x3, x13,FLREG) + +inst_26:// rs1==x9, rd==x2,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x9; dest:x2; op1val:0x324d; valaddr_reg:x20; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.lu.h, x2, x9, dyn, 32, 0, x20, 11*FLEN/8, x23, x3, x13,FLREG) + +inst_27:// rs1==x4, rd==x7,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x4; dest:x7; op1val:0x324d; valaddr_reg:x20; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.lu.h, x7, x4, dyn, 64, 0, x20, 12*FLEN/8, x23, x3, x13,FLREG) + +inst_28:// rs1==x0, rd==x11,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x0; dest:x11; op1val:0x0; valaddr_reg:x20; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.lu.h, x11, x0, dyn, 96, 0, x20, 13*FLEN/8, x23, x3, x13,FLREG) + +inst_29:// rs1==x17, rd==x19,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x17; dest:x19; op1val:0x324d; valaddr_reg:x20; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.lu.h, x19, x17, dyn, 128, 0, x20, 14*FLEN/8, x23, x3, x13,FLREG) + +inst_30:// rs1==x10, rd==x9,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x10; dest:x9; op1val:0x324e; valaddr_reg:x20; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x9, x10, dyn, 0, 0, x20, 15*FLEN/8, x23, x3, x13,FLREG) + +inst_31:// rs1==x26, rd==x14,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x26; dest:x14; op1val:0x324e; valaddr_reg:x20; +val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.lu.h, x14, x26, dyn, 32, 0, x20, 16*FLEN/8, x23, x3, x13,FLREG) +RVTEST_VALBASEUPD(x1,test_dataset_2) + +inst_32:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x324e; valaddr_reg:x1; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 64, 0, x1, 0*FLEN/8, x2, x3, x13,FLREG) + +inst_33:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x324e; valaddr_reg:x1; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 96, 0, x1, 1*FLEN/8, x2, x3, x13,FLREG) + +inst_34:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x324e; valaddr_reg:x1; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 128, 0, x1, 2*FLEN/8, x2, x3, x13,FLREG) + +inst_35:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x324f; valaddr_reg:x1; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x1, 3*FLEN/8, x2, x3, x13,FLREG) + +inst_36:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x324f; valaddr_reg:x1; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 32, 0, x1, 4*FLEN/8, x2, x3, x13,FLREG) + +inst_37:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x324f; valaddr_reg:x1; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 64, 0, x1, 5*FLEN/8, x2, x3, x13,FLREG) + +inst_38:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x324f; valaddr_reg:x1; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 96, 0, x1, 6*FLEN/8, x2, x3, x13,FLREG) + +inst_39:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x324f; valaddr_reg:x1; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 128, 0, x1, 7*FLEN/8, x2, x3, x13,FLREG) + +inst_40:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xb248; valaddr_reg:x1; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x1, 8*FLEN/8, x2, x3, x13,FLREG) + +inst_41:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xb248; valaddr_reg:x1; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 32, 0, x1, 9*FLEN/8, x2, x3, x13,FLREG) + +inst_42:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xb248; valaddr_reg:x1; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 64, 0, x1, 10*FLEN/8, x2, x3, x13,FLREG) + +inst_43:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xb248; valaddr_reg:x1; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 96, 0, x1, 11*FLEN/8, x2, x3, x13,FLREG) + +inst_44:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xb248; valaddr_reg:x1; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 128, 0, x1, 12*FLEN/8, x2, x3, x13,FLREG) + +inst_45:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xb249; valaddr_reg:x1; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x1, 13*FLEN/8, x2, x3, x13,FLREG) + +inst_46:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xb249; valaddr_reg:x1; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 32, 0, x1, 14*FLEN/8, x2, x3, x13,FLREG) + +inst_47:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xb249; valaddr_reg:x1; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 64, 0, x1, 15*FLEN/8, x2, x3, x13,FLREG) + +inst_48:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xb249; valaddr_reg:x1; +val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 96, 0, x1, 16*FLEN/8, x2, x3, x13,FLREG) + +inst_49:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xb249; valaddr_reg:x1; +val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 128, 0, x1, 17*FLEN/8, x2, x3, x13,FLREG) + +inst_50:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xb24a; valaddr_reg:x1; +val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x1, 18*FLEN/8, x2, x3, x13,FLREG) + +inst_51:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xb24a; valaddr_reg:x1; +val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 32, 0, x1, 19*FLEN/8, x2, x3, x13,FLREG) + +inst_52:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xb24a; valaddr_reg:x1; +val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 64, 0, x1, 20*FLEN/8, x2, x3, x13,FLREG) + +inst_53:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xb24a; valaddr_reg:x1; +val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 96, 0, x1, 21*FLEN/8, x2, x3, x13,FLREG) + +inst_54:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xb24a; valaddr_reg:x1; +val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 128, 0, x1, 22*FLEN/8, x2, x3, x13,FLREG) + +inst_55:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xb24b; valaddr_reg:x1; +val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x1, 23*FLEN/8, x2, x3, x13,FLREG) + +inst_56:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xb24b; valaddr_reg:x1; +val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 32, 0, x1, 24*FLEN/8, x2, x3, x13,FLREG) + +inst_57:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xb24b; valaddr_reg:x1; +val_offset:25*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 64, 0, x1, 25*FLEN/8, x2, x3, x13,FLREG) + +inst_58:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xb24b; valaddr_reg:x1; +val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 96, 0, x1, 26*FLEN/8, x2, x3, x13,FLREG) + +inst_59:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xb24b; valaddr_reg:x1; +val_offset:27*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 128, 0, x1, 27*FLEN/8, x2, x3, x13,FLREG) + +inst_60:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xb24c; valaddr_reg:x1; +val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x1, 28*FLEN/8, x2, x3, x13,FLREG) + +inst_61:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xb24c; valaddr_reg:x1; +val_offset:29*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 32, 0, x1, 29*FLEN/8, x2, x3, x13,FLREG) + +inst_62:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xb24c; valaddr_reg:x1; +val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 64, 0, x1, 30*FLEN/8, x2, x3, x13,FLREG) + +inst_63:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xb24c; valaddr_reg:x1; +val_offset:31*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 96, 0, x1, 31*FLEN/8, x2, x3, x13,FLREG) + +inst_64:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xb24c; valaddr_reg:x1; +val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 128, 0, x1, 32*FLEN/8, x2, x3, x13,FLREG) + +inst_65:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xb24d; valaddr_reg:x1; +val_offset:33*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x1, 33*FLEN/8, x2, x3, x13,FLREG) + +inst_66:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xb24d; valaddr_reg:x1; +val_offset:34*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 32, 0, x1, 34*FLEN/8, x2, x3, x13,FLREG) + +inst_67:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xb24d; valaddr_reg:x1; +val_offset:35*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 64, 0, x1, 35*FLEN/8, x2, x3, x13,FLREG) + +inst_68:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xb24d; valaddr_reg:x1; +val_offset:36*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 96, 0, x1, 36*FLEN/8, x2, x3, x13,FLREG) + +inst_69:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xb24d; valaddr_reg:x1; +val_offset:37*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 128, 0, x1, 37*FLEN/8, x2, x3, x13,FLREG) + +inst_70:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xb24e; valaddr_reg:x1; +val_offset:38*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x1, 38*FLEN/8, x2, x3, x13,FLREG) + +inst_71:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xb24e; valaddr_reg:x1; +val_offset:39*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 32, 0, x1, 39*FLEN/8, x2, x3, x13,FLREG) + +inst_72:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xb24e; valaddr_reg:x1; +val_offset:40*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 64, 0, x1, 40*FLEN/8, x2, x3, x13,FLREG) + +inst_73:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xb24e; valaddr_reg:x1; +val_offset:41*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 96, 0, x1, 41*FLEN/8, x2, x3, x13,FLREG) + +inst_74:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xb24e; valaddr_reg:x1; +val_offset:42*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 128, 0, x1, 42*FLEN/8, x2, x3, x13,FLREG) + +inst_75:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x0 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xb24f; valaddr_reg:x1; +val_offset:43*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:0*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 0, 0, x1, 43*FLEN/8, x2, x3, x13,FLREG) + +inst_76:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x20 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xb24f; valaddr_reg:x1; +val_offset:44*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:32*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 32, 0, x1, 44*FLEN/8, x2, x3, x13,FLREG) + +inst_77:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x40 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xb24f; valaddr_reg:x1; +val_offset:45*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:64*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 64, 0, x1, 45*FLEN/8, x2, x3, x13,FLREG) + +inst_78:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xb24f; valaddr_reg:x1; +val_offset:46*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 96, 0, x1, 46*FLEN/8, x2, x3, x13,FLREG) + +inst_79:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x80 and rm_val == 7 and rs1_sgn_prefix == 0xffff +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0xb24f; valaddr_reg:x1; +val_offset:47*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:128*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 128, 0, x1, 47*FLEN/8, x2, x3, x13,FLREG) + +inst_80:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x324b; valaddr_reg:x1; +val_offset:48*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 96, 0, x1, 48*FLEN/8, x2, x3, x13,FLREG) + +inst_81:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x60 and rm_val == 7 and rs1_sgn_prefix == 0x0000 +/* opcode: fcvt.lu.h ; op1:x30; dest:x31; op1val:0x324d; valaddr_reg:x1; +val_offset:49*FLEN/8; rmval:dyn; correctval:??; testreg:x13; +fcsr_val:96*/ +TEST_FPID_OP(fcvt.lu.h, x31, x30, dyn, 96, 0, x1, 49*FLEN/8, x2, x3, x13,FLREG) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(12872,32,FLEN) +NAN_BOXED(12872,32,FLEN) +NAN_BOXED(12872,32,FLEN) +NAN_BOXED(12872,32,FLEN) +NAN_BOXED(12872,32,FLEN) +NAN_BOXED(12873,32,FLEN) +NAN_BOXED(12873,32,FLEN) +NAN_BOXED(12873,32,FLEN) +NAN_BOXED(12873,32,FLEN) +NAN_BOXED(12873,32,FLEN) +NAN_BOXED(12874,32,FLEN) +NAN_BOXED(12874,32,FLEN) +NAN_BOXED(12874,32,FLEN) +NAN_BOXED(12874,32,FLEN) +NAN_BOXED(12874,32,FLEN) +test_dataset_1: +NAN_BOXED(12875,32,FLEN) +NAN_BOXED(12875,32,FLEN) +NAN_BOXED(12875,32,FLEN) +NAN_BOXED(12875,32,FLEN) +NAN_BOXED(12875,32,FLEN) +NAN_BOXED(12876,32,FLEN) +NAN_BOXED(12876,32,FLEN) +NAN_BOXED(12876,32,FLEN) +NAN_BOXED(12876,32,FLEN) +NAN_BOXED(12876,32,FLEN) +NAN_BOXED(12877,32,FLEN) +NAN_BOXED(12877,32,FLEN) +NAN_BOXED(12877,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(12877,32,FLEN) +NAN_BOXED(12878,32,FLEN) +NAN_BOXED(12878,32,FLEN) +test_dataset_2: +NAN_BOXED(12878,16,FLEN) +NAN_BOXED(12878,16,FLEN) +NAN_BOXED(12878,16,FLEN) +NAN_BOXED(12879,16,FLEN) +NAN_BOXED(12879,16,FLEN) +NAN_BOXED(12879,16,FLEN) +NAN_BOXED(12879,16,FLEN) +NAN_BOXED(12879,16,FLEN) +NAN_BOXED(45640,16,FLEN) +NAN_BOXED(45640,16,FLEN) +NAN_BOXED(45640,16,FLEN) +NAN_BOXED(45640,16,FLEN) +NAN_BOXED(45640,16,FLEN) +NAN_BOXED(45641,16,FLEN) +NAN_BOXED(45641,16,FLEN) +NAN_BOXED(45641,16,FLEN) +NAN_BOXED(45641,16,FLEN) +NAN_BOXED(45641,16,FLEN) +NAN_BOXED(45642,16,FLEN) +NAN_BOXED(45642,16,FLEN) +NAN_BOXED(45642,16,FLEN) +NAN_BOXED(45642,16,FLEN) +NAN_BOXED(45642,16,FLEN) +NAN_BOXED(45643,16,FLEN) +NAN_BOXED(45643,16,FLEN) +NAN_BOXED(45643,16,FLEN) +NAN_BOXED(45643,16,FLEN) +NAN_BOXED(45643,16,FLEN) +NAN_BOXED(45644,16,FLEN) +NAN_BOXED(45644,16,FLEN) +NAN_BOXED(45644,16,FLEN) +NAN_BOXED(45644,16,FLEN) +NAN_BOXED(45644,16,FLEN) +NAN_BOXED(45645,16,FLEN) +NAN_BOXED(45645,16,FLEN) +NAN_BOXED(45645,16,FLEN) +NAN_BOXED(45645,16,FLEN) +NAN_BOXED(45645,16,FLEN) +NAN_BOXED(45646,16,FLEN) +NAN_BOXED(45646,16,FLEN) +NAN_BOXED(45646,16,FLEN) +NAN_BOXED(45646,16,FLEN) +NAN_BOXED(45646,16,FLEN) +NAN_BOXED(45647,16,FLEN) +NAN_BOXED(45647,16,FLEN) +NAN_BOXED(45647,16,FLEN) +NAN_BOXED(45647,16,FLEN) +NAN_BOXED(45647,16,FLEN) +NAN_BOXED(12875,16,FLEN) +NAN_BOXED(12877,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x7_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x7_1: + .fill 36*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x3_0: + .fill 128*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END